From 0848cf2be71732b8b22f74506cba6d54d2bacc1a Mon Sep 17 00:00:00 2001 From: Huoji's <1296564236@qq.com> Date: Sat, 3 Aug 2024 02:01:16 +0800 Subject: [PATCH] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=E9=A1=B9=E7=9B=AE=E6=96=87?= =?UTF-8?q?=E4=BB=B6=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- white_patch_detect.sln | 31 + .../capstone-master/.appveyor.yml | 14 + .../capstone-master/.gitattributes | 1 + .../.github/workflows/coverity-scan.yml | 41 + .../.github/workflows/fuzz.yml | 23 + .../.github/workflows/python-publish.yml | 80 + white_patch_detect/capstone-master/.gitignore | 124 + .../capstone-master/.travis.yml | 75 + .../capstone-master/CMakeLists.txt | 629 + .../capstone-master/COMPILE.TXT | 200 + .../capstone-master/COMPILE_CMAKE.TXT | 114 + .../capstone-master/COMPILE_MSVC.TXT | 122 + .../capstone-master/CREDITS.TXT | 83 + white_patch_detect/capstone-master/ChangeLog | 701 + white_patch_detect/capstone-master/HACK.TXT | 102 + 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create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsGenSubtargetInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsMapping.c create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsMapping.h create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsMappingInsn.inc create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsModule.c create mode 100644 white_patch_detect/capstone-master/arch/Mips/MipsModule.h create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.c create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.h create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCGenAsmWriter.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCGenDisassemblerTables.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCGenInstrInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCGenSubtargetInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.c create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.h create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCMappingInsn.inc create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCModule.c create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCModule.h create mode 100644 white_patch_detect/capstone-master/arch/PowerPC/PPCPredicates.h create mode 100644 white_patch_detect/capstone-master/arch/Sparc/Sparc.h create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.c create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.h create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcGenAsmWriter.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcGenDisassemblerTables.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcGenInstrInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcGenSubtargetInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcMapping.c create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcMapping.h create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcMappingInsn.inc create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcModule.c create mode 100644 white_patch_detect/capstone-master/arch/Sparc/SparcModule.h create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.c create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.h create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenAsmWriter.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenDisassemblerTables.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInsnNameMaps.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInstrInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZGenSubtargetInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.c create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.h create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.c create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.h create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZMappingInsn.inc create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.c create mode 100644 white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.h create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.c create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.h create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.c create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.h create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.c create mode 100644 white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.h create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.c create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.h create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreGenAsmWriter.inc create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreGenDisassemblerTables.inc create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreGenInstrInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreGenRegisterInfo.inc create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.c create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.h create mode 100644 white_patch_detect/capstone-master/arch/XCore/XCoreMapping.c create mode 100644 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white_patch_detect/capstone-master/bindings/java/TestBasic.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestM680x.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestMips.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestPpc.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestSparc.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestSystemz.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestX86.java create mode 100644 white_patch_detect/capstone-master/bindings/java/TestXcore.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/.gitignore create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Arm.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Arm64.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Arm64_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Arm_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Capstone.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Evm_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/M680x.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/M680x_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/M68k_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Mips.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Mips_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Ppc.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Ppc_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Sparc.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Sparc_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Systemz.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Sysz_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/TMS320C64x_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/X86.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/X86_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Xcore.java create mode 100644 white_patch_detect/capstone-master/bindings/java/capstone/Xcore_const.java create mode 100644 white_patch_detect/capstone-master/bindings/java/run.sh create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/Makefile create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/README create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/arm.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/arm64.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/arm64_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/arm_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/capstone.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/evm_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/m680x.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/m680x_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/m68k_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/mips.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/mips_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/ocaml.c create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/ppc.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/ppc_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/sparc.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/sparc_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/systemz.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/sysz_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_arm.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_arm64.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_basic.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_detail.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_m680x.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_mips.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_ppc.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_sparc.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_systemz.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_x86.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/test_xcore.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/tms320c64x_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/x86.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/x86_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/xcore.ml create mode 100644 white_patch_detect/capstone-master/bindings/ocaml/xcore_const.ml create mode 100644 white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.Format.ps1xml create mode 100644 white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psd1 create mode 100644 white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psm1 create mode 100644 white_patch_detect/capstone-master/bindings/powershell/Capstone/Lib/Capstone/.gitignore create mode 100644 white_patch_detect/capstone-master/bindings/powershell/README.md create mode 100644 white_patch_detect/capstone-master/bindings/python/.gitignore create mode 100644 white_patch_detect/capstone-master/bindings/python/BUILDING.txt create mode 100644 white_patch_detect/capstone-master/bindings/python/LICENSE.TXT create mode 100644 white_patch_detect/capstone-master/bindings/python/MANIFEST.in create mode 100644 white_patch_detect/capstone-master/bindings/python/Makefile create mode 100644 white_patch_detect/capstone-master/bindings/python/README.txt create mode 100644 white_patch_detect/capstone-master/bindings/python/build_wheel.sh create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/arm.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/arm64.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/arm64_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/arm_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/evm.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/evm_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/m680x.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/m680x_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/m68k.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/m68k_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/mips.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/mips_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/mos65xx.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/mos65xx_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/ppc.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/ppc_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/sparc.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/sparc_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/systemz.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/sysz_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/x86.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/x86_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/xcore.py create mode 100644 white_patch_detect/capstone-master/bindings/python/capstone/xcore_const.py create mode 100644 white_patch_detect/capstone-master/bindings/python/prebuilt/.gitkeep create mode 100644 white_patch_detect/capstone-master/bindings/python/pyx/README create mode 100644 white_patch_detect/capstone-master/bindings/python/pyx/ccapstone.pxd create mode 100644 white_patch_detect/capstone-master/bindings/python/setup.cfg create mode 100644 white_patch_detect/capstone-master/bindings/python/setup.py create mode 100644 white_patch_detect/capstone-master/bindings/python/setup_cython.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_all.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_arm.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_arm64.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_basic.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_customized_mnem.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_detail.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_evm.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_lite.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_m680x.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_m68k.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_mips.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_mos65xx.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_ppc.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_skipdata.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_sparc.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_systemz.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_tms320c64x.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_x86.py create mode 100644 white_patch_detect/capstone-master/bindings/python/test_xcore.py create mode 100644 white_patch_detect/capstone-master/bindings/python/xprint.py create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CDisassembler.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CInstDetails.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CInstruction.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CX86Inst.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CX86OpMem.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/CX86Operand.cls create mode 100644 white_patch_detect/capstone-master/bindings/vb6/Form1.frm create mode 100644 white_patch_detect/capstone-master/bindings/vb6/Form1.frx create mode 100644 white_patch_detect/capstone-master/bindings/vb6/Module1.bas create mode 100644 white_patch_detect/capstone-master/bindings/vb6/Project1.vbp create mode 100644 white_patch_detect/capstone-master/bindings/vb6/README.txt create mode 100644 white_patch_detect/capstone-master/bindings/vb6/mMisc.bas create mode 100644 white_patch_detect/capstone-master/bindings/vb6/mx86.bas create mode 100644 white_patch_detect/capstone-master/bindings/vb6/screenshot.png create mode 100644 white_patch_detect/capstone-master/bindings/vb6/vbCapstone.cpp create mode 100644 white_patch_detect/capstone-master/bindings/vb6/vbCapstone.sln create mode 100644 white_patch_detect/capstone-master/bindings/vb6/vbCapstone.vcproj create mode 100644 white_patch_detect/capstone-master/capstone.pc.in create mode 100644 white_patch_detect/capstone-master/cmake.sh create mode 100644 white_patch_detect/capstone-master/config.mk create mode 100644 white_patch_detect/capstone-master/contrib/README create mode 100644 white_patch_detect/capstone-master/contrib/cs_driver/README create mode 100644 white_patch_detect/capstone-master/contrib/cs_driver/cs_driver.sln create mode 100644 white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.c create mode 100644 white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj create mode 100644 white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters create mode 100644 white_patch_detect/capstone-master/contrib/objdump/objdump-m68k.py create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch create mode 100644 white_patch_detect/capstone-master/contrib/sysz_update/README.md create mode 100644 white_patch_detect/capstone-master/contrib/windows_kernel/README create mode 100644 white_patch_detect/capstone-master/contrib/windows_kernel/libc.cpp create mode 100644 white_patch_detect/capstone-master/contrib/windows_kernel/libc.h create mode 100644 white_patch_detect/capstone-master/cs.c create mode 100644 white_patch_detect/capstone-master/cs_priv.h create mode 100644 white_patch_detect/capstone-master/cstool/Makefile create mode 100644 white_patch_detect/capstone-master/cstool/README create mode 100644 white_patch_detect/capstone-master/cstool/cstool.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_arm.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_arm64.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_evm.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_m680x.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_m68k.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_mips.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_mos65xx.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_ppc.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_sparc.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_systemz.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_tms320c64x.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_x86.c create mode 100644 white_patch_detect/capstone-master/cstool/cstool_xcore.c create mode 100644 white_patch_detect/capstone-master/cstool/getopt.h create mode 100644 white_patch_detect/capstone-master/docs/BHUSA2014-capstone.pdf create mode 100644 white_patch_detect/capstone-master/docs/README create mode 100644 white_patch_detect/capstone-master/docs/capstone-logo.png create mode 100644 white_patch_detect/capstone-master/functions.mk create mode 100644 white_patch_detect/capstone-master/include/capstone/arm.h create mode 100644 white_patch_detect/capstone-master/include/capstone/arm64.h create mode 100644 white_patch_detect/capstone-master/include/capstone/capstone.h create mode 100644 white_patch_detect/capstone-master/include/capstone/evm.h create mode 100644 white_patch_detect/capstone-master/include/capstone/m680x.h create mode 100644 white_patch_detect/capstone-master/include/capstone/m68k.h create mode 100644 white_patch_detect/capstone-master/include/capstone/mips.h create mode 100644 white_patch_detect/capstone-master/include/capstone/mos65xx.h create mode 100644 white_patch_detect/capstone-master/include/capstone/platform.h create mode 100644 white_patch_detect/capstone-master/include/capstone/ppc.h create mode 100644 white_patch_detect/capstone-master/include/capstone/sparc.h create mode 100644 white_patch_detect/capstone-master/include/capstone/systemz.h create mode 100644 white_patch_detect/capstone-master/include/capstone/tms320c64x.h create mode 100644 white_patch_detect/capstone-master/include/capstone/x86.h create mode 100644 white_patch_detect/capstone-master/include/capstone/xcore.h create mode 100644 white_patch_detect/capstone-master/include/platform.h create mode 100644 white_patch_detect/capstone-master/include/windowsce/intrin.h create mode 100644 white_patch_detect/capstone-master/include/windowsce/stdint.h create mode 100644 white_patch_detect/capstone-master/make.sh create mode 100644 white_patch_detect/capstone-master/msvc/README create mode 100644 white_patch_detect/capstone-master/msvc/capstone.sln create mode 100644 white_patch_detect/capstone-master/msvc/capstone_dll/capstone_dll.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/capstone_static/capstone_static.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/cstool/cstool.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_arm/test_arm.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_arm64/test_arm64.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_customized_mnem/test_customized_mnem.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_detail/test_detail.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_iter/test_iter.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_m68k/test_m68k.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_mips/test_mips.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_ppc/test_ppc.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_skipdata/test_skipdata.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_sparc/test_sparc.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_systemz/test_systemz.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_winkernel/test_winkernel.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_x86/test_x86.vcxproj create mode 100644 white_patch_detect/capstone-master/msvc/test_xcore/test_xcore.vcxproj create mode 100644 white_patch_detect/capstone-master/nmake.bat create mode 100644 white_patch_detect/capstone-master/pkgconfig.mk create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/basic-a64-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/gicv3-regs.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-2velem.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-3vdiff.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-aba-abd.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-across.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-pairwise.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-sub-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-bitwise-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-compare-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-crypto.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-extract.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-facge-facgt.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-frsqrt-frecp.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-halving-add-sub.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min-pairwise.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-mla-mls-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-mov.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-mul-div-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-perm.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-halving-add.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-add-sub.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-abs.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-add-sub.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-compare.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-cvt.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-dup.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-fp-compare.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-mul.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-neg.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-recip.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift-imm.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift-left-long.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-copy.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-multi-elem.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-one-elem.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-misc.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-shift.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/neon-tbl.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/AArch64/trace-regs.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/hilo-addressing.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-expansions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions-EB.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-alu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions-64.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-coprocessor-encodings.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-dsp-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-expansions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-fpu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-jump-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-memory-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips-register-names.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips64-alu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips64-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips64-register-names.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/mips_directives.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/nabi-regs.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/set-at-directive.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_2r.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_2rf.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_3r.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_3rf.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_bit.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_cbranch.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_ctrlregs.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_elm.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insert.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insve.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_i10.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_i5.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_i8.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_lsa.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_mi10.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Mips/test_vec.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-ext.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-fp.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-vmx.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-operands.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/README create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-alu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-atomic-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-ctrl-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-fp-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-mem-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc-vis.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-alu-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-ctrl-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparcv8-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/Sparc/sparcv9-instructions.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good-z196.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good.s.cs create mode 100644 white_patch_detect/capstone-master/suite/MC/SystemZ/regs-good.s.cs create mode 100644 white_patch_detect/capstone-master/suite/README create mode 100644 white_patch_detect/capstone-master/suite/autogen_x86imm.py create mode 100644 white_patch_detect/capstone-master/suite/benchmark.py create mode 100644 white_patch_detect/capstone-master/suite/benchmark/Makefile create mode 100644 white_patch_detect/capstone-master/suite/benchmark/test_iter_benchmark.c create mode 100644 white_patch_detect/capstone-master/suite/capstone_get_setup.c create mode 100644 white_patch_detect/capstone-master/suite/compile_all.sh create mode 100644 white_patch_detect/capstone-master/suite/cstest/Makefile create mode 100644 white_patch_detect/capstone-master/suite/cstest/README.md create mode 100644 white_patch_detect/capstone-master/suite/cstest/build_cstest.sh create mode 100644 white_patch_detect/capstone-master/suite/cstest/cstest_report.py create mode 100644 white_patch_detect/capstone-master/suite/cstest/include/capstone_test.h create mode 100644 white_patch_detect/capstone-master/suite/cstest/include/factory.h create mode 100644 white_patch_detect/capstone-master/suite/cstest/include/helper.h create mode 100644 white_patch_detect/capstone-master/suite/cstest/issues.cs create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/arm64_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/arm_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/capstone_test.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/evm_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/helper.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/m680x_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/m68k_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/main.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/mips_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/mos65xx_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/ppc_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/sparc_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/systemz_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/tms320c64x_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/x86_detail.c create mode 100644 white_patch_detect/capstone-master/suite/cstest/src/xcore_detail.c create mode 100644 white_patch_detect/capstone-master/suite/disasm_mc.py create mode 100644 white_patch_detect/capstone-master/suite/disasm_mc.sh create mode 100644 white_patch_detect/capstone-master/suite/fuzz.py create mode 100644 white_patch_detect/capstone-master/suite/fuzz/Makefile create mode 100644 white_patch_detect/capstone-master/suite/fuzz/README create mode 100644 white_patch_detect/capstone-master/suite/fuzz/driverbin.c create mode 100644 white_patch_detect/capstone-master/suite/fuzz/drivermc.c create mode 100644 white_patch_detect/capstone-master/suite/fuzz/fuzz_diff.c create mode 100644 white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.c create mode 100644 white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.options create mode 100644 white_patch_detect/capstone-master/suite/fuzz/fuzz_harness.c create mode 100644 white_patch_detect/capstone-master/suite/fuzz/fuzz_llvm.cpp create mode 100644 white_patch_detect/capstone-master/suite/fuzz/onefile.c create mode 100644 white_patch_detect/capstone-master/suite/patch_major_os_version.py create mode 100644 white_patch_detect/capstone-master/suite/ppcbranch.py create mode 100644 white_patch_detect/capstone-master/suite/python_capstone_setup.py create mode 100644 white_patch_detect/capstone-master/suite/regress.py create mode 100644 white_patch_detect/capstone-master/suite/regress/LICENSE create mode 100644 white_patch_detect/capstone-master/suite/regress/Makefile create mode 100644 white_patch_detect/capstone-master/suite/regress/invalid_read_in_print_operand.c create mode 100644 white_patch_detect/capstone-master/suite/regress/regress.py create mode 100644 white_patch_detect/capstone-master/suite/test_all.sh create mode 100644 white_patch_detect/capstone-master/suite/test_c.sh create mode 100644 white_patch_detect/capstone-master/suite/test_corpus.py create mode 100644 white_patch_detect/capstone-master/suite/test_group_name.py create mode 100644 white_patch_detect/capstone-master/suite/test_mc.py create mode 100644 white_patch_detect/capstone-master/suite/test_mc.sh create mode 100644 white_patch_detect/capstone-master/suite/test_python.sh create mode 100644 white_patch_detect/capstone-master/suite/x86odd.py create mode 100644 white_patch_detect/capstone-master/tests/Makefile create mode 100644 white_patch_detect/capstone-master/tests/README create mode 100644 white_patch_detect/capstone-master/tests/test_arm.c create mode 100644 white_patch_detect/capstone-master/tests/test_arm64.c create mode 100644 white_patch_detect/capstone-master/tests/test_basic.c create mode 100644 white_patch_detect/capstone-master/tests/test_customized_mnem.c create mode 100644 white_patch_detect/capstone-master/tests/test_detail.c create mode 100644 white_patch_detect/capstone-master/tests/test_evm.c create mode 100644 white_patch_detect/capstone-master/tests/test_iter.c create mode 100644 white_patch_detect/capstone-master/tests/test_m680x.c create mode 100644 white_patch_detect/capstone-master/tests/test_m68k.c create mode 100644 white_patch_detect/capstone-master/tests/test_mips.c create mode 100644 white_patch_detect/capstone-master/tests/test_mos65xx.c create mode 100644 white_patch_detect/capstone-master/tests/test_ppc.c create mode 100644 white_patch_detect/capstone-master/tests/test_skipdata.c create mode 100644 white_patch_detect/capstone-master/tests/test_sparc.c create mode 100644 white_patch_detect/capstone-master/tests/test_systemz.c create mode 100644 white_patch_detect/capstone-master/tests/test_tms320c64x.c create mode 100644 white_patch_detect/capstone-master/tests/test_winkernel.cpp create mode 100644 white_patch_detect/capstone-master/tests/test_x86.c create mode 100644 white_patch_detect/capstone-master/tests/test_xcore.c create mode 100644 white_patch_detect/capstone-master/utils.c create mode 100644 white_patch_detect/capstone-master/utils.h create mode 100644 white_patch_detect/capstone-master/windows/README create mode 100644 white_patch_detect/capstone-master/windows/winkernel_mm.c create mode 100644 white_patch_detect/capstone-master/windows/winkernel_mm.h create mode 100644 white_patch_detect/capstone-master/windowsce/.gitignore create mode 100644 white_patch_detect/capstone-master/windowsce/COMPILE.md create mode 100644 white_patch_detect/capstone-master/windowsce/make_windowsce7-armv7.bat create mode 100644 white_patch_detect/capstone-master/windowsce/make_windowsce8-armv7.bat create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.pbxproj create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Dynamic Library.xcscheme create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Framework.xcscheme create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Static Library.xcscheme create mode 100644 white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Tests.xcscheme create mode 100644 white_patch_detect/capstone-master/xcode/CapstoneFramework/Info.plist create mode 100644 white_patch_detect/capstone-master/xcode/CapstoneFramework/module.modulemap create mode 100644 white_patch_detect/capstone-master/xcode/README.md create mode 100644 white_patch_detect/libs/capstone64.lib create mode 100644 white_patch_detect/pe/pe.cpp create mode 100644 white_patch_detect/pe/pe.h create mode 100644 white_patch_detect/white_patch_detect.cpp create mode 100644 white_patch_detect/white_patch_detect.vcxproj create mode 100644 white_patch_detect/white_patch_detect.vcxproj.filters diff --git a/white_patch_detect.sln b/white_patch_detect.sln new file mode 100644 index 0000000..54f0f90 --- /dev/null +++ b/white_patch_detect.sln @@ -0,0 +1,31 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.33130.400 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "white_patch_detect", "white_patch_detect\white_patch_detect.vcxproj", "{A54C53B1-63C5-405C-9BB6-6426F1B9D00B}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|x64 = Debug|x64 + Debug|x86 = Debug|x86 + Release|x64 = Release|x64 + Release|x86 = Release|x86 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Debug|x64.ActiveCfg = Debug|x64 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Debug|x64.Build.0 = Debug|x64 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Debug|x86.ActiveCfg = Debug|Win32 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Debug|x86.Build.0 = Debug|Win32 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Release|x64.ActiveCfg = Release|x64 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Release|x64.Build.0 = Release|x64 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Release|x86.ActiveCfg = Release|Win32 + {A54C53B1-63C5-405C-9BB6-6426F1B9D00B}.Release|x86.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {035C4218-0D4D-4277-9BDC-C5FA94C7BABC} + EndGlobalSection +EndGlobal diff --git a/white_patch_detect/capstone-master/.appveyor.yml b/white_patch_detect/capstone-master/.appveyor.yml new file mode 100644 index 0000000..87b8bf4 --- /dev/null +++ b/white_patch_detect/capstone-master/.appveyor.yml @@ -0,0 +1,14 @@ +version: 4.0-{build} + +os: + - Visual Studio 2015 + +before_build: + - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 + +build_script: + - mkdir build + - cd build + - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. + - nmake + diff --git a/white_patch_detect/capstone-master/.gitattributes b/white_patch_detect/capstone-master/.gitattributes new file mode 100644 index 0000000..03e638d --- /dev/null +++ b/white_patch_detect/capstone-master/.gitattributes @@ -0,0 +1 @@ +/arch/**/*.inc linguist-language=C diff --git a/white_patch_detect/capstone-master/.github/workflows/coverity-scan.yml b/white_patch_detect/capstone-master/.github/workflows/coverity-scan.yml new file mode 100644 index 0000000..c93446e --- /dev/null +++ b/white_patch_detect/capstone-master/.github/workflows/coverity-scan.yml @@ -0,0 +1,41 @@ +name: coverity-scan +on: + schedule: + - cron: '0 18 * * 1,4' # Bi-weekly at 18:00 UTC on Monday and Thursday + +jobs: + latest: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v1 + - name: Download Coverity Build Tool + run: | + wget -q https://scan.coverity.com/download/cxx/linux64 --post-data "token=$TOKEN&project=capstone-next" -O cov-analysis-linux64.tar.gz + mkdir cov-analysis-linux64 + tar xzf cov-analysis-linux64.tar.gz --strip 1 -C cov-analysis-linux64 + env: + TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + + - name: Fixed world writable dirs + run: | + chmod go-w $HOME + sudo chmod -R go-w /usr/share + + - name: Build with cov-build + run: | + export PATH=`pwd`/cov-analysis-linux64/bin:$PATH + cov-build --dir cov-int make + + - name: Submit the result to Coverity Scan + run: | + tar czvf capstone.tgz cov-int + curl \ + --form project=capstone-next \ + --form token=$TOKEN \ + --form email=noreply@capstone-engine.org \ + --form file=@capstone.tgz \ + --form version=trunk \ + --form description="capstone" \ + https://scan.coverity.com/builds?project=capstone-next + env: + TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} diff --git a/white_patch_detect/capstone-master/.github/workflows/fuzz.yml b/white_patch_detect/capstone-master/.github/workflows/fuzz.yml new file mode 100644 index 0000000..5aa8527 --- /dev/null +++ b/white_patch_detect/capstone-master/.github/workflows/fuzz.yml @@ -0,0 +1,23 @@ +name: CIFuzz +on: [pull_request] +jobs: + Fuzzing: + runs-on: ubuntu-latest + steps: + - name: Build Fuzzers + uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master + with: + oss-fuzz-project-name: 'capstone' + dry-run: false + - name: Run Fuzzers + uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master + with: + oss-fuzz-project-name: 'capstone' + fuzz-seconds: 600 + dry-run: false + - name: Upload Crash + uses: actions/upload-artifact@v1 + if: failure() + with: + name: artifacts + path: ./out/artifacts diff --git a/white_patch_detect/capstone-master/.github/workflows/python-publish.yml b/white_patch_detect/capstone-master/.github/workflows/python-publish.yml new file mode 100644 index 0000000..6f5e855 --- /dev/null +++ b/white_patch_detect/capstone-master/.github/workflows/python-publish.yml @@ -0,0 +1,80 @@ +name: PyPI 馃摝 Distribution + +on: [push] + +jobs: + build: + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: [macos-latest, ubuntu-latest, windows-latest] + platform: [x32, x64] + steps: + - uses: actions/checkout@v2 + + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.x' + + - name: Set up MSVC x86 + if: matrix.os == 'windows-latest' && matrix.platform == 'x32' + uses: ilammy/msvc-dev-cmd@v1 + with: + arch: x86 + + - name: Set up MSVC x64 + if: matrix.os == 'windows-latest' && matrix.platform == 'x64' + uses: ilammy/msvc-dev-cmd@v1 + + - name: Install dependencies + run: | + pip install setuptools wheel + + - name: Build distribution 馃摝 + shell: bash + run: | + if [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'windows-latest' ]; then + cd bindings/python && python setup.py build -p win32 bdist_wheel -p win32 + elif [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'ubuntu-latest' ]; then + docker run --rm -v `pwd`/:/work dockcross/manylinux1-x86 > ./dockcross + chmod +x ./dockcross + ./dockcross bindings/python/build_wheel.sh + elif [ ${{ matrix.platform }} == 'x64' ] && [ ${{ matrix.os }} == 'ubuntu-latest' ]; then + docker run --rm -v `pwd`/:/work dockcross/manylinux1-x64 > ./dockcross + chmod +x ./dockcross + ./dockcross bindings/python/build_wheel.sh + elif [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'macos-latest' ]; then + cd bindings/python && python setup.py sdist + else + cd bindings/python && python setup.py bdist_wheel + fi + + - uses: actions/upload-artifact@v2 + with: + path: ${{ github.workspace }}/bindings/python/dist/* + + publish: + needs: [build] + runs-on: ubuntu-latest + if: startsWith(github.ref, 'refs/tags') + steps: + - uses: actions/download-artifact@v2 + with: + name: artifact + path: dist + + - name: Publish distribution 馃摝 to test PyPI + uses: pypa/gh-action-pypi-publish@master + with: + user: __token__ + password: ${{ secrets.testpypi_pass }} + repository_url: https://test.pypi.org/legacy/ + + - name: Publish distribution 馃摝 to PyPI + if: ${{ success() }} + uses: pypa/gh-action-pypi-publish@master + with: + user: __token__ + password: ${{ secrets.pypi_pass }} diff --git a/white_patch_detect/capstone-master/.gitignore b/white_patch_detect/capstone-master/.gitignore new file mode 100644 index 0000000..da89f95 --- /dev/null +++ b/white_patch_detect/capstone-master/.gitignore @@ -0,0 +1,124 @@ +.DS_Store + +# Object files +*.o +*.ko + +# Gcc dependency-tracking files +*.d + +# Libraries +*.lib +*.a + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app + +# python +bindings/python/build/ +bindings/python/capstone.egg-info/ +*.pyc + +# java +bindings/java/capstone.jar + +# ocaml +bindings/ocaml/*.cmi +bindings/ocaml/*.cmx +bindings/ocaml/*.cmxa +bindings/ocaml/*.mli +bindings/ocaml/test +bindings/ocaml/test_arm +bindings/ocaml/test_arm64 +bindings/ocaml/test_basic +bindings/ocaml/test_mips +bindings/ocaml/test_x86 +bindings/ocaml/test_detail +bindings/ocaml/test_ppc +bindings/ocaml/test_sparc +bindings/ocaml/test_systemz +bindings/ocaml/test_xcore +bindings/ocaml/test_m680x + + +# test binaries +tests/test_basic +tests/test_detail +tests/test_iter +tests/test_arm +tests/test_arm64 +tests/test_mips +tests/test_x86 +tests/test_ppc +tests/test_skipdata +tests/test_sparc +tests/test_systemz +tests/test_xcore +tests/*.static +tests/test_customized_mnem +tests/test_m68k +tests/test_tms320c64x +tests/test_m680x +tests/test_evm +tests/test_mos65xx + +# regress binaries +suite/regress/invalid_read_in_print_operand + +# vim tmp file +*.swp +*~ + +capstone.pc + +# local files +_* + +# freebsd ports: generated file with "make makesum" command +packages/freebsd/ports/devel/capstone/distinfo + +# VisualStudio +ProjectUpgradeLog.log +Debug/ +Release/ +ipch/ +build*/ +*.sdf +*.opensdf +*.suo +*.user +*.backup +*.VC.db +*.VC.opendb + +# CMake build directories +build*/ + +# Xcode +xcode/Capstone.xcodeproj/xcuserdata +xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata + +# suite/ +test_arm_regression +test_arm_regression.o +fuzz_harness +test_iter_benchmark +fuzz_bindisasm +fuzz_disasm +capstone_get_setup + + +*.s + +cstool/cstool + +# android +android-ndk-* diff --git a/white_patch_detect/capstone-master/.travis.yml b/white_patch_detect/capstone-master/.travis.yml new file mode 100644 index 0000000..42a6322 --- /dev/null +++ b/white_patch_detect/capstone-master/.travis.yml @@ -0,0 +1,75 @@ +language: cpp +sudo: false +before_install: + - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH +before_script: + - wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip + - unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz + # TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default + - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka + - chmod +x suite/cstest/build_cstest.sh +script: + - ./make.sh + - make check + - sudo make install + - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi + - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi + - if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi + - if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi + - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi + - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi +compiler: + - clang + - gcc +os: + - linux + - osx +matrix: + include: + - name: xenial gcc + os: linux + dist: xenial + compiler: gcc + addons: + apt: + packages: + - libcmocka-dev + - name: bionic gcc (ARM64) + arch: arm64 + os: linux + dist: bionic + compiler: gcc + addons: + apt: + packages: + - libcmocka-dev + - unzip + - name: bionic gcc (System Z) + arch: s390x + os: linux + dist: bionic + compiler: gcc + addons: + apt: + packages: + - libcmocka-dev + - name: xenial clang + os: linux + dist: xenial + compiler: clang + addons: + apt: + packages: + - libcmocka-dev + - name: fuzza + env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" LDFLAGS="-fsanitize=address" NOPYTEST=true + compiler: clang + os: linux + - name: fuzzm + env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" LDFLAGS="-fsanitize=memory" NOPYTEST=true + compiler: clang + os: linux + - name: fuzzu + env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer" LDFLAGS="-fsanitize=undefined" NOPYTEST=true + compiler: clang + os: linux diff --git a/white_patch_detect/capstone-master/CMakeLists.txt b/white_patch_detect/capstone-master/CMakeLists.txt new file mode 100644 index 0000000..e821053 --- /dev/null +++ b/white_patch_detect/capstone-master/CMakeLists.txt @@ -0,0 +1,629 @@ +cmake_minimum_required(VERSION 2.8.12) +project(capstone) + +set(VERSION_MAJOR 5) +set(VERSION_MINOR 0) +set(VERSION_PATCH 0) + +if(POLICY CMP0042) + # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html + cmake_policy(SET CMP0042 NEW) +endif(POLICY CMP0042) + +if (POLICY CMP0048) + # use old policy to honor version set using VERSION_* variables to preserve backwards + # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and + # set VERSION using project(capstone VERSION 4.0.0). + # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html + cmake_policy (SET CMP0048 OLD) +endif() + +# to configure the options specify them in in the command line or change them in the cmake UI. +# Don't edit the makefile! +option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ON) +option(CAPSTONE_BUILD_STATIC "Build static library" ON) +option(CAPSTONE_BUILD_SHARED "Build shared library" ON) +option(CAPSTONE_BUILD_DIET "Build diet library" OFF) +option(CAPSTONE_BUILD_TESTS "Build tests" ON) +option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) +option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) +option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON) +option(CAPSTONE_INSTALL "Generate install target" ON) + +set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX) +set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX) + +list(LENGTH SUPPORTED_ARCHITECTURES count) +math(EXPR count "${count}-1") +# create options controlling whether support for a particular architecture is needed +foreach(i RANGE ${count}) + list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture) + list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label) + option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ${CAPSTONE_ARCHITECTURE_DEFAULT}) +endforeach(i) + +# propagate architecture support variables to preprocessor +foreach(supported_architecture ${SUPPORTED_ARCHITECTURES}) + set(option_name "CAPSTONE_${supported_architecture}_SUPPORT") + if(${option_name}) + message("Enabling ${option_name}") + add_definitions("-D${option_name}") + endif() +endforeach(supported_architecture) + +option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF) +option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF) +option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF) + +if (MSVC) + set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT") + set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd") +endif () + +enable_testing() + +if (CAPSTONE_BUILD_DIET) + add_definitions(-DCAPSTONE_DIET) +endif () + +if (CAPSTONE_USE_DEFAULT_ALLOC) + add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) +endif () + +if (CAPSTONE_X86_REDUCE) + add_definitions(-DCAPSTONE_X86_REDUCE) +endif () + +if (CAPSTONE_X86_ATT_DISABLE) + add_definitions(-DCAPSTONE_X86_ATT_DISABLE) +endif () + +## sources +set(SOURCES_ENGINE + cs.c + MCInst.c + MCInstrDesc.c + MCRegisterInfo.c + SStream.c + utils.c +) +set(HEADERS_ENGINE + cs_priv.h + LEB128.h + MathExtras.h + MCDisassembler.h + MCFixedLenDisassembler.h + MCInst.h + MCInstrDesc.h + MCRegisterInfo.h + SStream.h + utils.h + ) + +set(HEADERS_COMMON + include/capstone/arm64.h + include/capstone/arm.h + include/capstone/capstone.h + include/capstone/evm.h + include/capstone/mips.h + include/capstone/ppc.h + include/capstone/x86.h + include/capstone/sparc.h + include/capstone/systemz.h + include/capstone/xcore.h + include/capstone/m68k.h + include/capstone/tms320c64x.h + include/capstone/m680x.h + include/capstone/mos65xx.h + include/capstone/platform.h + ) + +set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) + +## architecture support +if (CAPSTONE_ARM_SUPPORT) + add_definitions(-DCAPSTONE_HAS_ARM) + set(SOURCES_ARM + arch/ARM/ARMDisassembler.c + arch/ARM/ARMInstPrinter.c + arch/ARM/ARMMapping.c + arch/ARM/ARMModule.c + ) + set(HEADERS_ARM + arch/ARM/ARMAddressingModes.h + arch/ARM/ARMBaseInfo.h + arch/ARM/ARMDisassembler.h + arch/ARM/ARMGenAsmWriter.inc + arch/ARM/ARMGenDisassemblerTables.inc + arch/ARM/ARMGenInstrInfo.inc + arch/ARM/ARMGenRegisterInfo.inc + arch/ARM/ARMGenSubtargetInfo.inc + arch/ARM/ARMInstPrinter.h + arch/ARM/ARMMapping.h + arch/ARM/ARMMappingInsn.inc + arch/ARM/ARMMappingInsnOp.inc + ) + set(HEADERS_ARM + arch/ARM/ARMAddressingModes.h + arch/ARM/ARMBaseInfo.h + arch/ARM/ARMDisassembler.h + arch/ARM/ARMGenAsmWriter.inc + arch/ARM/ARMGenDisassemblerTables.inc + arch/ARM/ARMGenInstrInfo.inc + arch/ARM/ARMGenRegisterInfo.inc + arch/ARM/ARMGenSubtargetInfo.inc + arch/ARM/ARMInstPrinter.h + arch/ARM/ARMMapping.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_arm.c) +endif () + +if (CAPSTONE_ARM64_SUPPORT) + add_definitions(-DCAPSTONE_HAS_ARM64) + set(SOURCES_ARM64 + arch/AArch64/AArch64BaseInfo.c + arch/AArch64/AArch64Disassembler.c + arch/AArch64/AArch64InstPrinter.c + arch/AArch64/AArch64Mapping.c + arch/AArch64/AArch64Module.c + ) + set(HEADERS_ARM64 + arch/AArch64/AArch64AddressingModes.h + arch/AArch64/AArch64BaseInfo.h + arch/AArch64/AArch64Disassembler.h + arch/AArch64/AArch64GenAsmWriter.inc + arch/AArch64/AArch64GenDisassemblerTables.inc + arch/AArch64/AArch64GenInstrInfo.inc + arch/AArch64/AArch64GenRegisterInfo.inc + arch/AArch64/AArch64GenSubtargetInfo.inc + arch/AArch64/AArch64InstPrinter.h + arch/AArch64/AArch64Mapping.h + arch/AArch64/AArch64MappingInsn.inc + ) + set(HEADERS_ARM64 + arch/AArch64/AArch64AddressingModes.h + arch/AArch64/AArch64BaseInfo.h + arch/AArch64/AArch64Disassembler.h + arch/AArch64/AArch64GenAsmWriter.inc + arch/AArch64/AArch64GenDisassemblerTables.inc + arch/AArch64/AArch64GenInstrInfo.inc + arch/AArch64/AArch64GenRegisterInfo.inc + arch/AArch64/AArch64GenSubtargetInfo.inc + arch/AArch64/AArch64InstPrinter.h + arch/AArch64/AArch64Mapping.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c) +endif () + +if (CAPSTONE_MIPS_SUPPORT) + add_definitions(-DCAPSTONE_HAS_MIPS) + set(SOURCES_MIPS + arch/Mips/MipsDisassembler.c + arch/Mips/MipsInstPrinter.c + arch/Mips/MipsMapping.c + arch/Mips/MipsModule.c + ) + set(HEADERS_MIPS + arch/Mips/MipsDisassembler.h + arch/Mips/MipsGenAsmWriter.inc + arch/Mips/MipsGenDisassemblerTables.inc + arch/Mips/MipsGenInstrInfo.inc + arch/Mips/MipsGenRegisterInfo.inc + arch/Mips/MipsGenSubtargetInfo.inc + arch/Mips/MipsInstPrinter.h + arch/Mips/MipsMapping.h + arch/Mips/MipsMappingInsn.inc + ) + set(HEADERS_MIPS + arch/Mips/MipsDisassembler.h + arch/Mips/MipsGenAsmWriter.inc + arch/Mips/MipsGenDisassemblerTables.inc + arch/Mips/MipsGenInstrInfo.inc + arch/Mips/MipsGenRegisterInfo.inc + arch/Mips/MipsGenSubtargetInfo.inc + arch/Mips/MipsInstPrinter.h + arch/Mips/MipsMapping.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) +endif () + +if (CAPSTONE_PPC_SUPPORT) + add_definitions(-DCAPSTONE_HAS_POWERPC) + set(SOURCES_PPC + arch/PowerPC/PPCDisassembler.c + arch/PowerPC/PPCInstPrinter.c + arch/PowerPC/PPCMapping.c + arch/PowerPC/PPCModule.c + ) + set(HEADERS_PPC + arch/PowerPC/PPCDisassembler.h + arch/PowerPC/PPCGenAsmWriter.inc + arch/PowerPC/PPCGenDisassemblerTables.inc + arch/PowerPC/PPCGenInstrInfo.inc + arch/PowerPC/PPCGenRegisterInfo.inc + arch/PowerPC/PPCGenSubtargetInfo.inc + arch/PowerPC/PPCInstPrinter.h + arch/PowerPC/PPCMapping.h + arch/PowerPC/PPCMappingInsn.inc + arch/PowerPC/PPCPredicates.h + ) + set(HEADERS_PPC + arch/PowerPC/PPCDisassembler.h + arch/PowerPC/PPCGenAsmWriter.inc + arch/PowerPC/PPCGenDisassemblerTables.inc + arch/PowerPC/PPCGenInstrInfo.inc + arch/PowerPC/PPCGenRegisterInfo.inc + arch/PowerPC/PPCGenSubtargetInfo.inc + arch/PowerPC/PPCInstPrinter.h + arch/PowerPC/PPCMapping.h + arch/PowerPC/PPCPredicates.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c) +endif () + +if (CAPSTONE_X86_SUPPORT) + add_definitions(-DCAPSTONE_HAS_X86) + set(SOURCES_X86 + arch/X86/X86Disassembler.c + arch/X86/X86DisassemblerDecoder.c + arch/X86/X86IntelInstPrinter.c + arch/X86/X86Mapping.c + arch/X86/X86Module.c + ) + set(HEADERS_X86 + arch/X86/X86BaseInfo.h + arch/X86/X86Disassembler.h + arch/X86/X86DisassemblerDecoder.h + arch/X86/X86DisassemblerDecoderCommon.h + arch/X86/X86GenAsmWriter.inc + arch/X86/X86GenAsmWriter1.inc + arch/X86/X86GenAsmWriter1_reduce.inc + arch/X86/X86GenAsmWriter_reduce.inc + arch/X86/X86GenDisassemblerTables.inc + arch/X86/X86GenDisassemblerTables_reduce.inc + arch/X86/X86GenInstrInfo.inc + arch/X86/X86GenInstrInfo_reduce.inc + arch/X86/X86GenRegisterInfo.inc + arch/X86/X86InstPrinter.h + arch/X86/X86Mapping.h + arch/X86/X86MappingInsn.inc + arch/X86/X86MappingInsnOp.inc + arch/X86/X86MappingInsnOp_reduce.inc + arch/X86/X86MappingInsn_reduce.inc + ) + set(HEADERS_X86 + arch/X86/X86BaseInfo.h + arch/X86/X86Disassembler.h + arch/X86/X86DisassemblerDecoder.h + arch/X86/X86DisassemblerDecoderCommon.h + arch/X86/X86GenAsmWriter.inc + arch/X86/X86GenAsmWriter1.inc + arch/X86/X86GenAsmWriter1_reduce.inc + arch/X86/X86GenAsmWriter_reduce.inc + arch/X86/X86GenDisassemblerTables.inc + arch/X86/X86GenDisassemblerTables_reduce.inc + arch/X86/X86GenInstrInfo.inc + arch/X86/X86GenInstrInfo_reduce.inc + arch/X86/X86GenRegisterInfo.inc + arch/X86/X86InstPrinter.h + arch/X86/X86Mapping.h + ) + if (NOT CAPSTONE_BUILD_DIET) + set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c) + endif () + set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c) +endif () + +if (CAPSTONE_SPARC_SUPPORT) + add_definitions(-DCAPSTONE_HAS_SPARC) + set(SOURCES_SPARC + arch/Sparc/SparcDisassembler.c + arch/Sparc/SparcInstPrinter.c + arch/Sparc/SparcMapping.c + arch/Sparc/SparcModule.c + ) + set(HEADERS_SPARC + arch/Sparc/Sparc.h + arch/Sparc/SparcDisassembler.h + arch/Sparc/SparcGenAsmWriter.inc + arch/Sparc/SparcGenDisassemblerTables.inc + arch/Sparc/SparcGenInstrInfo.inc + arch/Sparc/SparcGenRegisterInfo.inc + arch/Sparc/SparcGenSubtargetInfo.inc + arch/Sparc/SparcInstPrinter.h + arch/Sparc/SparcMapping.h + arch/Sparc/SparcMappingInsn.inc + ) + set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c) +endif () + +if (CAPSTONE_SYSZ_SUPPORT) + add_definitions(-DCAPSTONE_HAS_SYSZ) + set(SOURCES_SYSZ + arch/SystemZ/SystemZDisassembler.c + arch/SystemZ/SystemZInstPrinter.c + arch/SystemZ/SystemZMapping.c + arch/SystemZ/SystemZModule.c + arch/SystemZ/SystemZMCTargetDesc.c + ) + set(HEADERS_SYSZ + arch/SystemZ/SystemZDisassembler.h + arch/SystemZ/SystemZGenAsmWriter.inc + arch/SystemZ/SystemZGenDisassemblerTables.inc + arch/SystemZ/SystemZGenInsnNameMaps.inc + arch/SystemZ/SystemZGenInstrInfo.inc + arch/SystemZ/SystemZGenRegisterInfo.inc + arch/SystemZ/SystemZGenSubtargetInfo.inc + arch/SystemZ/SystemZInstPrinter.h + arch/SystemZ/SystemZMapping.h + arch/SystemZ/SystemZMappingInsn.inc + arch/SystemZ/SystemZMCTargetDesc.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c) +endif () + +if (CAPSTONE_XCORE_SUPPORT) + add_definitions(-DCAPSTONE_HAS_XCORE) + set(SOURCES_XCORE + arch/XCore/XCoreDisassembler.c + arch/XCore/XCoreInstPrinter.c + arch/XCore/XCoreMapping.c + arch/XCore/XCoreModule.c + ) + set(HEADERS_XCORE + arch/XCore/XCoreDisassembler.h + arch/XCore/XCoreGenAsmWriter.inc + arch/XCore/XCoreGenDisassemblerTables.inc + arch/XCore/XCoreGenInstrInfo.inc + arch/XCore/XCoreGenRegisterInfo.inc + arch/XCore/XCoreInstPrinter.h + arch/XCore/XCoreMapping.h + arch/XCore/XCoreMappingInsn.inc + ) + set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c) +endif () + +if (CAPSTONE_M68K_SUPPORT) + add_definitions(-DCAPSTONE_HAS_M68K) + set(SOURCES_M68K + arch/M68K/M68KDisassembler.c + arch/M68K/M68KInstPrinter.c + arch/M68K/M68KModule.c + ) + set(HEADERS_M68K + arch/M68K/M68KDisassembler.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c) +endif () + +if (CAPSTONE_TMS320C64X_SUPPORT) + add_definitions(-DCAPSTONE_HAS_TMS320C64X) + set(SOURCES_TMS320C64X + arch/TMS320C64x/TMS320C64xDisassembler.c + arch/TMS320C64x/TMS320C64xInstPrinter.c + arch/TMS320C64x/TMS320C64xMapping.c + arch/TMS320C64x/TMS320C64xModule.c + ) + set(HEADERS_TMS320C64X + arch/TMS320C64x/TMS320C64xDisassembler.h + arch/TMS320C64x/TMS320C64xGenAsmWriter.inc + arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc + arch/TMS320C64x/TMS320C64xGenInstrInfo.inc + arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc + arch/TMS320C64x/TMS320C64xInstPrinter.h + arch/TMS320C64x/TMS320C64xMapping.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c) +endif () + +if (CAPSTONE_M680X_SUPPORT) + add_definitions(-DCAPSTONE_HAS_M680X) + set(SOURCES_M680X + arch/M680X/M680XDisassembler.c + arch/M680X/M680XInstPrinter.c + arch/M680X/M680XModule.c + ) + set(HEADERS_M680X + arch/M680X/M680XInstPrinter.h + arch/M680X/M680XDisassembler.h + arch/M680X/M680XDisassemblerInternals.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c) +endif () + +if (CAPSTONE_EVM_SUPPORT) + add_definitions(-DCAPSTONE_HAS_EVM) + set(SOURCES_EVM + arch/EVM/EVMDisassembler.c + arch/EVM/EVMInstPrinter.c + arch/EVM/EVMMapping.c + arch/EVM/EVMModule.c + ) + set(HEADERS_EVM + arch/EVM/EVMDisassembler.h + arch/EVM/EVMInstPrinter.h + arch/EVM/EVMMapping.h + arch/EVM/EVMMappingInsn.inc + ) + set(TEST_SOURCES ${TEST_SOURCES} test_evm.c) +endif () + +if (CAPSTONE_MOS65XX_SUPPORT) + add_definitions(-DCAPSTONE_HAS_MOS65XX) + set(SOURCES_MOS65XX + arch/MOS65XX/MOS65XXModule.c + arch/MOS65XX/MOS65XXDisassembler.c) + set(HEADERS_SOURCES_MOS65XX + arch/MOS65XX/MOS65XXDisassembler.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c) +endif () + +if (CAPSTONE_OSXKERNEL_SUPPORT) + add_definitions(-DCAPSTONE_HAS_OSXKERNEL) +endif () + +set(ALL_SOURCES + ${SOURCES_ENGINE} + ${SOURCES_ARM} + ${SOURCES_ARM64} + ${SOURCES_MIPS} + ${SOURCES_PPC} + ${SOURCES_X86} + ${SOURCES_SPARC} + ${SOURCES_SYSZ} + ${SOURCES_XCORE} + ${SOURCES_M68K} + ${SOURCES_TMS320C64X} + ${SOURCES_M680X} + ${SOURCES_EVM} + ${SOURCES_MOS65XX} + ) + +set(ALL_HEADERS + ${HEADERS_COMMON} + ${HEADERS_ENGINE} + ${HEADERS_ARM} + ${HEADERS_ARM64} + ${HEADERS_MIPS} + ${HEADERS_PPC} + ${HEADERS_X86} + ${HEADERS_SPARC} + ${HEADERS_SYSZ} + ${HEADERS_XCORE} + ${HEADERS_M68K} + ${HEADERS_TMS320C64X} + ${HEADERS_M680X} + ${HEADERS_EVM} + ${HEADERS_MOS65XX} + ) + +include_directories("${PROJECT_SOURCE_DIR}/include") + +## properties +# version info +set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) + +## targets +if (CAPSTONE_BUILD_STATIC) + add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS}) + set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone) + set(default-target capstone-static) +endif () + +# Force static runtime libraries +if (CAPSTONE_BUILD_STATIC_RUNTIME) + FOREACH(flag + CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO + CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT + CMAKE_CXX_FLAGS_RELEASE CMAKE_CXX_FLAGS_RELWITHDEBINFO + CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_DEBUG_INIT) + if (MSVC) + STRING(REPLACE "/MD" "/MT" "${flag}" "${${flag}}") + SET("${flag}" "${${flag}} /EHsc") + endif (MSVC) + ENDFOREACH() +endif () + +if (CAPSTONE_BUILD_SHARED) + add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS}) + set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone) + set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED) + + if (MSVC) + set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib) + else() + set_target_properties(capstone-shared PROPERTIES + VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} + SOVERSION ${VERSION_MAJOR}) + endif () + + if(NOT DEFINED default-target) # honor `capstone-static` for tests first. + set(default-target capstone-shared) + add_definitions(-DCAPSTONE_SHARED) + endif () +endif () + +if (CAPSTONE_BUILD_TESTS) + foreach (TSRC ${TEST_SOURCES}) + STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) + add_executable(${TBIN} "tests/${TSRC}") + target_link_libraries(${TBIN} ${default-target}) + add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN}) + endforeach () + if (CAPSTONE_ARM_SUPPORT) + set(ARM_REGRESS_TEST test_arm_regression.c) + STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) + add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") + target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) + add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN}) + endif() + # fuzz target built with the tests + add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c) + target_link_libraries(fuzz_disasm ${default-target}) +endif () + +source_group("Source\\Engine" FILES ${SOURCES_ENGINE}) +source_group("Source\\ARM" FILES ${SOURCES_ARM}) +source_group("Source\\ARM64" FILES ${SOURCES_ARM64}) +source_group("Source\\Mips" FILES ${SOURCES_MIPS}) +source_group("Source\\PowerPC" FILES ${SOURCES_PPC}) +source_group("Source\\Sparc" FILES ${SOURCES_SPARC}) +source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ}) +source_group("Source\\X86" FILES ${SOURCES_X86}) +source_group("Source\\XCore" FILES ${SOURCES_XCORE}) +source_group("Source\\M68K" FILES ${SOURCES_M68K}) +source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X}) +source_group("Source\\M680X" FILES ${SOURCES_M680X}) +source_group("Source\\EVM" FILES ${SOURCES_EVM}) +source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX}) + +source_group("Include\\Common" FILES ${HEADERS_COMMON}) +source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) +source_group("Include\\ARM" FILES ${HEADERS_ARM}) +source_group("Include\\ARM64" FILES ${HEADERS_ARM64}) +source_group("Include\\Mips" FILES ${HEADERS_MIPS}) +source_group("Include\\PowerPC" FILES ${HEADERS_PPC}) +source_group("Include\\Sparc" FILES ${HEADERS_SPARC}) +source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ}) +source_group("Include\\X86" FILES ${HEADERS_X86}) +source_group("Include\\XCore" FILES ${HEADERS_XCORE}) +source_group("Include\\M68K" FILES ${HEADERS_M68K}) +source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X}) +source_group("Include\\M680X" FILES ${HEADERS_MC680X}) +source_group("Include\\EVM" FILES ${HEADERS_EVM}) +source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX}) + +### test library 64bit routine: +include("GNUInstallDirs") + +## installation +if (CAPSTONE_INSTALL) + install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone) +endif () +configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY) + +if (CAPSTONE_BUILD_STATIC AND CAPSTONE_INSTALL) + install(TARGETS capstone-static + RUNTIME DESTINATION bin + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) +endif () + +if (CAPSTONE_BUILD_SHARED AND CAPSTONE_INSTALL) + install(TARGETS capstone-shared + RUNTIME DESTINATION bin + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) +endif () + +if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL) +FILE(GLOB CSTOOL_SRC cstool/*.c) +add_executable(cstool ${CSTOOL_SRC}) +target_link_libraries(cstool ${default-target}) + +if (CAPSTONE_INSTALL) + install(TARGETS cstool DESTINATION bin) + install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig) +endif () +endif () diff --git a/white_patch_detect/capstone-master/COMPILE.TXT b/white_patch_detect/capstone-master/COMPILE.TXT new file mode 100644 index 0000000..847d415 --- /dev/null +++ b/white_patch_detect/capstone-master/COMPILE.TXT @@ -0,0 +1,200 @@ +This documentation explains how to compile, install & run Capstone on MacOSX, +Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows. + +To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT. + +To compile using CMake, see COMPILE_CMAKE.TXT. + +To compile using XCode on MacOSX, see xcode/README.md. + +To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md. + + *-*-*-*-*-* + +Capstone requires no prerequisite packages, so it is easy to compile & install. + + + +(0) Tailor Capstone to your need. + + Out of all archtitectures supported by Capstone, if you just need several + selected archs, choose the ones you want to compile in by editing "config.mk" + before going to next steps. + + By default, all architectures are compiled. + + The other way of customize Capstone without having to edit config.mk is to + pass the desired options on the commandline to ./make.sh. Currently, + Capstone supports 7 options, as followings. + + - CAPSTONE_ARCHS: specify list of architectures to compiled in. + - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management. + - CAPSTONE_DIET: use this to make the output binaries more compact. + - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller. + - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86. + - CAPSTONE_STATIC: build static library. + - CAPSTONE_SHARED: build dynamic (shared) library. + + By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE + modes are disable, and builds all the static & shared libraries. + + To avoid editing config.mk for these customization, we can pass their values to + make.sh, as followings. + + $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh + + NOTE: on commandline, put these values in front of ./make.sh, not after it. + + For each option, refer to docs/README for more details. + + + +(1) Compile from source + + On *nix (such as MacOSX, Linux, *BSD, Solaris): + + - To compile for current platform, run: + + $ ./make.sh + + - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary: + + $ ./make.sh nix32 + + + +(2) Install Capstone on *nix + + To install Capstone, run: + + $ sudo ./make.sh install + + For FreeBSD/OpenBSD, where sudo is unavailable, run: + + $ su; ./make.sh install + + Users are then required to enter root password to copy Capstone into machine + system directories. + + Afterwards, run ./tests/test* to see the tests disassembling sample code. + + + NOTE: The core framework installed by "./make.sh install" consist of + following files: + + /usr/include/capstone/arm.h + /usr/include/capstone/arm64.h + /usr/include/capstone/capstone.h + /usr/include/capstone/evm.h + /usr/include/capstone/m680x.h + /usr/include/capstone/m68k.h + /usr/include/capstone/mips.h + /usr/include/capstone/mos65xx.h + /usr/include/capstone/platform.h + /usr/include/capstone/ppc.h + /usr/include/capstone/sparc.h + /usr/include/capstone/systemz.h + /usr/include/capstone/tms320c64x.h + /usr/include/capstone/x86.h + /usr/include/capstone/xcore.h + /usr/lib/libcapstone.a + /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX) + + + +(3) Cross-compile for Windows from *nix + + To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64 + for 64-bit binaries) are required. + + - To cross-compile Windows 32-bit binary, simply run: + + $ ./make.sh cross-win32 + + - To cross-compile Windows 64-bit binary, run: + + $ ./make.sh cross-win64 + + Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then + be used on Windows machine. + + + +(4) Cross-compile for iOS from Mac OSX. + + To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. + + - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run: + $ ./make.sh ios_armv7 + + - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run: + $ ./make.sh ios_armv7s + + - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run: + $ ./make.sh ios_arm64 + + - To cross-compile for all iDevices (armv7 + armv7s + arm64), run: + $ ./make.sh ios + + Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then + be used on iOS devices. + + + +(5) Cross-compile for Android + + To cross-compile for Android (smartphone/tablet), Android NDK is required. + NOTE: Only ARM and ARM64 are currently supported. + + $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm + or + $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64 + + Resulted files libcapstone.so, libcapstone.a & tests/test* can then + be used on Android devices. + + + +(6) Compile on Windows with Cygwin + + To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run: + + - To compile Windows 32-bit binary under Cygwin, run: + + $ ./make.sh cygwin-mingw32 + + - To compile Windows 64-bit binary under Cygwin, run: + + $ ./make.sh cygwin-mingw64 + + Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then + be used on Windows machine. + + + +(7) By default, "cc" (default C compiler on the system) is used as compiler. + + - To use "clang" compiler instead, run the command below: + + $ ./make.sh clang + + - To use "gcc" compiler instead, run: + + $ ./make.sh gcc + + + +(8) To uninstall Capstone, run the command below: + + $ sudo ./make.sh uninstall + + + +(9) Language bindings + + So far, Python, Ocaml & Java are supported by bindings in the main code. + Look for the bindings under directory bindings/, and refer to README file + of corresponding languages. + + Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to + these can be found at address http://capstone-engine.org/download.html diff --git a/white_patch_detect/capstone-master/COMPILE_CMAKE.TXT b/white_patch_detect/capstone-master/COMPILE_CMAKE.TXT new file mode 100644 index 0000000..51e2eb6 --- /dev/null +++ b/white_patch_detect/capstone-master/COMPILE_CMAKE.TXT @@ -0,0 +1,114 @@ +This documentation explains how to compile Capstone with CMake, focus on +using Microsoft Visual C as the compiler. + +To compile Capstone on *nix, see COMPILE.TXT. + +To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT. + + *-*-*-*-*-* + +This documentation requires CMake & Windows SDK or MS Visual Studio installed on +your machine. + +Get CMake for free from http://www.cmake.org. + + + +(0) Tailor Capstone to your need. + + Out of archtitectures supported by Capstone, if you just need several selected archs, + run "cmake" with the unwanted archs disabled (set to 0) as followings. + + - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. + - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64. + - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. + - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. + - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. + - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX. + - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC. + - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc. + - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ. + - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore. + - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86. + - CAPSTONE_TMS320C64X_SUPPORT: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X. + - CAPSTONE_EVM_SUPPORT: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM. + - CAPSTONE_ARCHITECTURE_DEFAULT: Whether architectures are enabled by default. + Set this of OFF with -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF to disable all architectures by default. + You can then enable them again with one of the CAPSTONE__SUPPORT options. + + By default, all architectures are compiled in. + + + Besides, Capstone also allows some more customization via following macros. + + - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management. + - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact. + - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. + - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. + + By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE + modes are disabled. To use your own memory allocations, turn ON both DIET & + X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1 + + + For each option, refer to docs/README for more details. + + + +(1) CMake allows you to generate different generators to build Capstone. Below is + some examples on how to build Capstone on Windows with CMake. + + (*) You can let CMake select a generator for you. Do: + + mkdir build + cd build + cmake .. + + This last command is also where you can pass additional CMake configuration flags + using `-D=`. Then to build use: + + cmake --build . --config Release + + + (*) To build Capstone using Nmake of Windows SDK, do: + + mkdir build + cd build + ..\nmake.bat + + After this, find the samples test*.exe, capstone.lib & capstone.dll + in the same directory. + + + + (*) To build Capstone using Visual Studio, choose the generator accordingly to the + version of Visual Studio on your machine. For example, with Visual Studio 2013, do: + + mkdir build + cd build + cmake -G "Visual Studio 12" .. + + After this, find capstone.sln in the same directory. Open it with Visual Studio + and build the solution including libraries & all test as usual. + + + +(2) You can make sure the prior steps successfully worked by launching one of the + testing binary (test*.exe). + +(3) You can also enable just one specific architecture by passing the architecture name + to either the cmake.sh or nmake.bat scripts. e.g.: + + ../cmake.sh x86 + + Will just target the x86 architecture. The list of available architectures is: ARM, + ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX. + +(4) You can also create an installation image with cmake, by using the 'install' target. + Use: + + cmake --build . --config Release --target install + + This will normally install an image in a default location (`C:\Program Files` on Windows), + so it's good to explicitly set this location when configuring CMake. Use: `-DCMAKE_INSTALL_PREFIX=image` + for instance, to put the installation in the 'image' subdirectory of the build directory. diff --git a/white_patch_detect/capstone-master/COMPILE_MSVC.TXT b/white_patch_detect/capstone-master/COMPILE_MSVC.TXT new file mode 100644 index 0000000..b2d9bdd --- /dev/null +++ b/white_patch_detect/capstone-master/COMPILE_MSVC.TXT @@ -0,0 +1,122 @@ +This documentation explains how to compile Capstone on Windows using +Microsoft Visual Studio version 2010 or newer. + +To compile Capstone on *nix, see COMPILE.TXT + +To compile Capstone with CMake, see COMPILE_CMAKE.TXT + + *-*-*-*-*-* + +Capstone requires no prerequisite packages with default configurations, so it is +easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln" +and follow the instructions below. + +NOTE: This requires Visual Studio 2010 or newer versions. + +If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer +versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. + + +(0) Tailor Capstone to your need. + + Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, + Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose + the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln", + then directly editing the projects "capstone_static" & "capstone_dll" for static + and dynamic libraries, respectively. This must be done before going to the next + steps. + + In VisualStudio interface, modify the preprocessor definitions via + "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor" + to customize Capstone library, as followings. + + - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. + - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support. + - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. + - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. + - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support. + - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support. + - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support. + - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support. + - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support. + + By default, all 9 architectures are compiled in. + + + Besides, Capstone also allows some more customization via following macros. + + - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management. + - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact. + - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller. + - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable + AT&T syntax on x86. + + By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE + modes are disable. + + + For each option, refer to docs/README for more details. + + + +(1) Compile from source on Windows with Visual Studio + + - Choose the configuration and the platform you want: Release/Debug & Win32/Win64. + - Build only the libraries, or the libraries along with all the tests. + - "capstone_static_winkernel" is for compiling Capstone for a driver and + "test_winkernel" is a test for a driver, and those are excluded from build by + default. To compile them, open the Configuration Manager through the [Build] + menu and check "Build" check boxes for those project. + + + +(2) You can make sure the prior steps successfully worked by launching one of the + testing binary (test*.exe). + + The testing binary for a driver "test_winkernel.sys" is made up of all tests for + supported architectures configured with the step (0) along side its own tests. + Below explains a procedure to run the test driver and check test results. + + On the x64 platform, the test signing mode has to be enabled to install the test + driver. To do it, open the command prompt with the administrator privileges and + type the following command, and then restart the system to activate the change: + + >bcdedit /set testsigning on + + Test results from the test driver is sent to kernel debug buffer. In order to + see those results, download DebugView and run it with the administrator + privileges, then check [Capture Kernel] through the [Capture] menu. + + DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx + + To install and uninstall the driver, use the 'sc' command. For installing and + executing test_winkernel.sys, execute the following commands with the + administrator privileges: + + >sc create test_winkernel type= kernel binPath= + [SC] CreateService SUCCESS + + >sc start test_winkernel + [SC] StartService FAILED 995: + + The I/O operation has been aborted because of either a thread exit or an application request. + + To uninstall the driver, execute the following commands with the administrator + privileges: + + >sc delete test_winkernel + >bcdedit /deletevalue testsigning + + + +(3) Installing and building capstone via vcpkg + + You can download and install capstone using the vcpkg(https://github.com/Microsoft/vcpkg) dependency manager: + + git clone https://github.com/Microsoft/vcpkg.git + cd vcpkg + ./bootstrap-vcpkg.sh + ./vcpkg integrate install + vcpkg install capstone + + The capstone port in vcpkg is kept up to date by Microsoft team members and community contributors. If the version is out of date, please create an issue or pull request on the vcpkg repository(https://github.com/Microsoft/vcpkg). \ No newline at end of file diff --git a/white_patch_detect/capstone-master/CREDITS.TXT b/white_patch_detect/capstone-master/CREDITS.TXT new file mode 100644 index 0000000..051b42b --- /dev/null +++ b/white_patch_detect/capstone-master/CREDITS.TXT @@ -0,0 +1,83 @@ +This file credits all the contributors of the Capstone engine project. + +Key developers +============== +1. Nguyen Anh Quynh + - Core engine + - Bindings: Python, Ruby, OCaml, Java, C# + +2. Tan Sheng Di + - Bindings: Ruby + +3. Ben Nagy + - Bindings: Ruby, Go + +4. Dang Hoang Vu + - Bindings: Java + + +Beta testers (in random order) +============================== +Pancake +Van Hauser +FX of Phenoelit +The Grugq, The Grugq <-- our hero for submitting the first ever patch! +Isaac Dawson, Veracode Inc +Patroklos Argyroudis, Census Inc. (http://census-labs.com) +Attila Suszter +Le Dinh Long +Nicolas Ruff +Gunther +Alex Ionescu, Winsider Seminars & Solutions Inc. +Snare +Daniel Godas-Lopez +Joshua J. Drake +Edgar Barbosa +Ralf-Philipp Weinmann +Hugo Fortier +Joxean Koret +Bruce Dang +Andrew Dunham + + +Contributors (in no particular order) +===================================== +(Please let us know if you want to have your name here) + +Ole Andr茅 Vadla Ravn氓s (author of the 100th Pull-Request in our Github repo, thanks!) +Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC. +Daniel Pistelli: Cmake support. +Peter Hlavaty: integrate Capstone for Windows kernel drivers. +Guillaume Jeanne: Ocaml binding. +Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features. +David Mart铆nez Moreno & Hilko Bengen: Debian package. +F茅lix Cloutier: Xcode project. +Benoit Lecocq: OpenBSD package. +Christophe Avoinne (Hlide): Improve memory management for better performance. +Michael Cohen & Nguyen Tan Cong: Python module installer. +Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. +Felix Gr枚bert (Google): fuzz testing harness. +Xipiter LLC: Capstone logo redesigned. +Satoshi Tanda: Support Windows kernel driver. +Tang Yuhang: cstool. +Andrew Dutcher: better Python setup. +Ruben Boonen: PowerShell binding. +David Zimmer: VB6 binding. +Philippe Antoine: Integration with oss-fuzz and various fixes. +Bui Dinh Cuong: Explicit registers accessed for Arm64. +Vincent B茅nony: Explicit registers accessed for X86. +Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. +Felix Gr枚bert (Google): fuzz testing harness. +Daniel Collin & Nicolas Planel: M68K architecture. +Pranith Kumar: Explicit registers accessed for Arm64. +Xipiter LLC: Capstone logo redesigned. +Satoshi Tanda: Support Windows kernel driver. +Koutheir Attouchi: Support for Windows CE. +Fotis Loukos: TMS320C64x architecture. +Wolfgang Schwotzer: M680X architecture. +Philippe Antoine: Integration with oss-fuzz and various fixes. +Stephen Eckels (stevemk14ebr): x86 encoding features +Sebastian Macke: MOS65XX architecture +Ilya Leoshkevich: SystemZ architecture improvements. +Do Minh Tuan: Regression testing tool (cstest) +Kevin Foo (chfl4gs): PyPI github actions workflow. diff --git a/white_patch_detect/capstone-master/ChangeLog b/white_patch_detect/capstone-master/ChangeLog new file mode 100644 index 0000000..af3ebf8 --- /dev/null +++ b/white_patch_detect/capstone-master/ChangeLog @@ -0,0 +1,701 @@ +This file details the changelog of Capstone. + +--------------------------------- +Version 4.0.1: January 10th, 2019 + + +[ Core ] + +- Fix some issues for packaging (Debian, Gentoo). +- Better support for building with Mingw. +- cstool has new option -s to turn on skipdata mode. +- cstool -v now report build settings of the core. +- Add suite/capstone_get_setup.c so users can integrate with their own code + to retrieve Capstone settings at build time. + + +[ Arm ] + +- Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back again (see #1317) +- Remove ARM_REG_PC group for BX instruction. + + +[ X86 ] + +- Fix: endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64 (#1129) + + +[ M680X ] + +- Fix some issues reported by clang-analyzer (#1329). + + +[ Python ] + +- Fix skipdata setup. +- Add getter/setter for skipdata_mnem, skipdata_callback. + + +--------------------------------- +Version 4.0: December 18th, 2018 + + +[ Core ] + +- New APIs: cs_regs_access() +- Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM. +- Various updates & bugfixes for all architectures. +- Add 4 new architectures: EVM, M68K, M680X & TMS320C64x. +- Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE. +- Add new error types: CS_ERR_X86_MASM. + + +[ X86 ] + +- Add XOP code condition type in x86_xop_cc. +- Add some info on encoding to cs_x86 in cs_x86_encoding. +- Add register flags update in cs_x86.{eflags, fpu_flags} +- Change cs_x86.disp type from int32_t to int64_t. +- Add new groups: X86_GRP_VM & X86_GRP_FPU. +- Lots of new instructions (AVX) + + +[ ARM64 ] + +- Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS. + + +[ Mips ] + +- Add mode CS_MODE_MIPS2. + + +[ PPC ] + +- Change cs_ppc_op.imm type from int32_t to int64_t. +- Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX. +- Lots of new instructions (QPX among them) + + +[ Sparc ] + +- Change cs_sparc_op.imm type from int32_t to int64_t. + + +[ Binding ] + +- New bindings: PowerShell & VB6 + + +--------------------------------- +Version 3.0.5: July 18th, 2018 + + +[ Core ] + +- Fix the include path for Android builds when building cstool. +- Add posibility to disable universal build for Mac OS. +- cstool: Separate instruction bytes by spaces. +- Fix code path of pkg-config in Cmake. +- Update XCode project for XCode 9.1. +- Add Cortex-M support to cstool. +- Cmake forces to be build using MT with MSVC. +- Better support for Mac OS kernel. + + +[ X86 ] + +- Fix some issues in handling EVEX & VEX3 instructions. +- Fix immediate operand for AND instruction in ATT mode. +- Fix ATT syntax when imm operand is 0. +- Better handle XACQUIRE/XRELEASE. +- Fix imm operand of RETF. + + +[ ARM ] + +- Fix an integer overlow bug. + + +[ ARM64 ] + +- Bug fix for incorrect operand type in certain load/store instructions. + + +[ Mips ] + +- Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32 + + +[ PPC ] + +- Fix endian check. + + +[ Sparc ] + +- Fix an integer overlow bug. + + +[ SystemZ ] + +- Fix an integer overlow bug. + + +[ Python binding ] + +- Raise error on accessing irrelevant data fields if skipdata & detail modes are enable. + + +--------------------------------- +Version 3.0.5-rc3: July 31st, 2017 + + +[ Core ] + +- Fix compilation for MacOS kernel extension +- cstool to support armbe and arm64be modes +- Add nmake.bat for Windows build +- Fix an integer overflow for Windows kernel driver +- Support to embedded Capstone into MacOS kernel +- cstool: fix mips64 mode +- Fix a compiling error in MS Visual Studio 2015 +- Install pkgconfig file with CMake build +- Fix SOVERSION property of CMake build +- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc +- Fix MingW build +- Better handle CMake installation for Linux 64bit + + +[ X86 ] + +- Support BND prefix of Intel MPX extension +- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66 +- LOCK NOP is a valid instruction +- Fix ATT syntax for instruction with zero offset segment register +- LES/LDS are invalid in 64bit mode +- Fix number of operands for some MOV instructions + + +[ ARM ] + +- Fix POP reg to update SP register +- Update flags for UADD8 instruction + + +[ ARM64 ] + +- Better performance with new lookup table +- Handle system registers added in ARMv8.1/2 + + +[ Java binding ] + +- Better handle input with invalid code + + +[ Visual Basic binding ] + +- New binding + +--------------------------------- +Version 3.0.5-rc2: March 2nd, 2017 + + +[ Core ] + +- Fix build for Visual Studio 2012 +- Fix X86_REL_ADDR macro +- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA +- Better support for embedding Capstone into Windows kernel drivers +- Support to embedded Capstone into MacOS kernel +- Support MacOS 10.11 and up +- Better support for Cygwin +- Support build packages for FreeBSD & DragonflyBSD +- Add a command-line tool "cstool" +- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc + + +[ X86 ] + +- Some random 16-bit code can be handled wrongly. +- Remove abundant operand type X86_OP_FP +- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL +- Add X86_REG_EFLAGS for STC and STD +- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT +- Rename registers ST0-ST7 to be consistent with asm output + + +[ ARM ] + +- Properly handle IT instruction +- Fix LDRSB +- Fix writeback for LDR +- Fix Thumb BigEndian setup + + +[ ARM64 ] + +- Fix arith extender +- Fix writeback for LDR +- Rename enum arm64_mrs_reg to arm64_sysreg + + +[ PowerPC ] + +- Print 0 offset for memory operand + + +[ Sparc ] + +- Fix POPC instruction + + +[ Python binding ] + +- Better PyPy support +- Add __version__ +- Better support for Python 3 +- Fix CS_SKIPDATA_CALLBACK prototype +- Cast skipdata function inside binding to simplify the API + + +[ Java binding ] + +- Better handle input with invalid code + + +[ PowerShell ] + +- New binding + +--------------------------------- +Version 3.0.4: July 15th, 2015 + + +[ Library ] + +- Improve cross-compile for Android using Android NDK. +- Support cross-compile for AArch64 Android (with Linux GCC). +- Removed osxkernel_inttypes.h that is incompatible with BSD license. +- Make it possible to compile with CC having a space inside (like "ccache gcc"). + + +[ X86 ] + +- Fix a null pointer dereference bug on handling code with special prefixes. +- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax. +- Print immediate operand in positive form in some algorithm instructions. +- Properly decode some SSE instructions. + + +[ PowerPC ] + +- Fixed a memory corruption bug. +- Fixed a memory corruption bug for the engine built in DIET mode. + + +[ Mips ] + +- Fixed instruction ID of SUBU instruction. +- Fixed a memory corruption bug. + + +[ Arm ] + +- Fixed a memory corruption bug on IT instruction. + + +[ XCore ] + +- Fixed a memory corruption bug when instruction has a memory operand. + + +[ Python ] + +- Support Virtualenv. +- setup.py supports option --user if not in a virtualenv to allow for local usage. +- Properly handle the destruction of Cs object in the case the shared library + was already unloaded. + +--------------------------------- +Version 3.0.3: May 08th, 2015 + + +[ Library ] + +- Support to embed into Mac OS X kernel extensions. +- Now it is possible to compile Capstone with older C compilers, such as + GCC 4.8 on Ubuntu 12.04. +- Add "test_iter" to MSVC project. + + +[ X86 ] + +- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support + $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of + "rcll %edx"). +- CMPXCHG16B is a valid instruction with LOCK prefix. +- Fixed a segfault on the input of 0xF3. + + +[ Arm ] + +- BLX instruction modifies PC & LR registers. + + +[ Sparc ] + +- Improved displacement decoding for sparc banching instructions. + + +[ Python binding ] + +- Fix for Cython so it can properly initialize. +- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type. +- Properly support compile with Cygwin & install binding (setup.py). + +--------------------------------- +Version 3.0.2: March 11th, 2015 + + +[ Library ] + +- On *nix, only export symbols that are part of the API (instead of all + the internal symbols). + + +[ X86 ] + +- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding. +- Fix implicit registers read/written & instruction groups of some instructions. +- More flexible on the order of prefixes, so better handle some tricky + instructions. +- REPNE prefix can go with STOS & MOVS instructions. +- Fix a compilation bug for X86_REDUCE mode. +- Fix operand size of instructions with operand PTR [] + + +[ Arm ] + +- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode). +- Fix a bug on handling the If-Then block. + + +[ Mips ] + +- Sanity check for the input size for MIPS64 mode. + + +[ MSVC ] + +- Compile capstone.dll with static runtime MSVCR built in. + + +[ Python binding ] + +- Fix a compiling issue of Cython binding with gcc 4.9. + +--------------------------------- +Version 3.0.1: February 03rd, 2015 + +[ X86 ] + +- Properly handle LOCK, REP, REPE & REPNE prefixes. +- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions. +- Print LJUMP/LCALL without * as prefix for Intel syntax. +- Handle REX prefix properly for segment/MMX related instructions (x86_64). +- Instruction with length > 15 is consider invalid. +- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, + FSTP, FSTPNCE, NOP. +- Handle some tricky code for some X86_64 instructions with REX prefix. +- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg +- MOV32ms & MOV32sm should reference word rather than dword. + + +[ Arm64 ] + +- BL & BLR instructions do not read SP register. +- Print absolute (rather than relative) address for instructions B, BL, + CBNZ, ADR. + + +[ Arm ] + +- Instructions ADC & SBC do not update flags. +- BL & BLX do not read SP, but PC register. +- Alias LDR instruction with operands [sp], 4 to POP. +- Print immediate operand of MVN instruction in positive hexadecimal form. + + +[ PowerPC ] + +- Fix some compilation bugs when DIET mode is enable. +- Populate SLWI/SRWI instruction details with SH operand. + + +[ Python binding ] + +- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes. +- Fixed a memory leak for Cython disasm functions when we immaturely quit + the enumeration of disassembled instructions. +- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable + at the same time. +- Fix a memory leaking bug when when we stop enumeration over the disassembled + instructions prematurely. +- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx). + +--------------------------------- +Version 3.0: November 19th, 2014 + +[ API ] + +- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials. +- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but + marked obsolete to be removed in future) +- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going + from the next legitimate instruction. See docs/README for tutorials. +- More details provided in cs_detail struct for all architectures. +- API version was bumped to 3.0. + + +[ Bindings ] + +- Python binding supports Python3 (besides Python2). +- Support Ocaml binding. +- Java: add close() method to be used to deinitialize a Capstone object when + no longer use it. + + +[ Architectures ] + +- New architectures: Sparc, SystemZ & XCore. +- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86. +- Support more instructions for Arm, Arm64, Mips, PowerPC & X86. +- Always expose absolute addresses rather than relative addresses (Arm, Arm64, + Mips, PPC, Sparc, X86). +- Use common instruction operand types REG, IMM, MEM & FP across all + architectures (to enable cross-architecture analysis). +- Use common instruction group types across all architectures (to enable + cross-architecture analysis). + + +[ X86 ] + +- X86 engine is mature & handles all the malware tricks (that we are aware of). +- Added a lot of new instructions (such as AVX512, 3DNow, etc). +- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE. +- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions. +- More friendly disassembly for JMP16i (in the form segment:offset) + + +[ Mips ] + +- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) & + MipsGP64 (CS_MODE_MIPSGP64). +- Removed the ABI-only mode CS_MODE_N64. +- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 & + CS_MODE_64). + + +[ ARM ] + +- Support new mode CS_MODE_V8 for Armv8 A32 encodings. +- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions + + +[ ARM64 ] + +- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions. + + +[ PowerPC ] + +- Do not print a dot in front of absolute address. + + +[ Other features ] + +- Support for Microsoft Visual Studio (so enable Windows native compilation). +- Support CMake compilation. +- Cross-compile for Android. +- Build libraries/tests using XCode project +- Much faster, while consuming less memory for all architectures. + +--------------------------------- +Version 2.1.2: April 3rd, 2014 + +This is a stable release to fix some bugs deep in the core. There is no update +to any architectures or bindings, so bindings version 2.1 can be used with this +version 2.1.2 just fine. + +[ Core changes] + +- Support cross-compilation for all iDevices (iPhone/iPad/iPod). +- X86: do not print memory offset in negative form. +- Fix a bug in X86 when Capstone cannot handle short instruction. +- Print negative number above -9 without prefix 0x (arm64, mips, arm). +- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris). +- Set library versioning for dylib of OSX. + +--------------------------------- +Version 2.1.1: March 13th, 2014 + +This is a stable release to fix some bugs deep in the core. There is no update +to any architectures or bindings, so bindings version 2.1 can be used with this +version 2.1.1 just fine. + +[ Core changes] + +- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can + trigger this flaw. +- Fix a crash issue when embedding Capstone into OSX kernel. This should + also enable Capstone to be embedded into other systems with limited stack + memory size such as Linux kernel or some firmwares. +- Use a proper SONAME for library versioning (Linux). + +--------------------------------- +Version 2.1: March 5th, 2014 + +[ API changes ] + +- API version has been bumped to 2.1. +- Change prototype of cs_close() to be able to invalidate closed handle. + See http://capstone-engine.org/version_2.1_API.html for more information. +- Extend cs_support() to handle more query types, not only about supported + architectures. This change is backward compatible, however, so existent code + do not need to be modified to support this. +- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of + the engine. +- New error code CS_ERR_DIET to report errors about newly added diet mode. +- New error code CS_ERR_VERSION to report issue of incompatible versions between + bindings & core engine. + + +[ Core changes ] + +- On memory usage, Capstone uses about 40% less memory, while still faster + than version 2.0. +- All architectures are much smaller: binaries size reduce at least 30%. + Especially, X86-only binary reduces from 1.9MB to just 720KB. +- Support "diet" mode, in which engine size is further reduced (by around 40%) + for embedding purpose. The price to pay is that we have to sacrifice some + non-critical data fields. See http://capstone-engine.org/diet.html for more + details. + + +[ Architectures ] + +- Update all 5 architectures to fix bugs. +- PowerPC: + - New instructions: FMR & MSYNC. +- Mips: + - New instruction: DLSA +- X86: + - Properly handle AVX-512 instructions. + - New instructions: PSETPM, SALC, INT1, GETSEC. + - Fix some memory leaking issues in case of prefixed instructions such + as LOCK, REP, REPNE. + + +[ Python binding ] + +- Verify the core version at initialization time. Refuse to run if its version + is different from the core's version. +- New API disasm_lite() added to Cs class. This light API only returns tuples of + (address, size, mnemonic, op_str), rather than list of CsInsn objects. This + improves performance by around 30% in some benchmarks. +- New API version_bind() returns binding's version, which might differ from + the core's API version if the binding is out-of-date. +- New API debug() returns information on Cython support, diet status & archs + compiled in. +- Fixed some memory leaking bugs for Cython binding. +- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups. +- Support diet mode. + + +[ Java binding ] + +- Fix some memory leaking bugs. +- New API version() returns combined version. +- Support diet mode. +- Better support for detail option. + + +[ Miscellaneous ] + +- make.sh now can uninstall the core engine. This is done with: + + $ sudo ./make.sh uninstall + +---------------------------------- +Version 2.0: January 22nd, 2014 + +Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. + +[ API changes ] + +- API version has been bumped to 2.0 (see cs_version() API) +- New API cs_strerror(errno) returns a string describing error code given + in its only argument. +- cs_version() now returns combined version encoding both major & minor versions. +- New option CS_OPT_MODE allows to change engine鈥檚 mode at run-time with + cs_option(). +- New option CS_OPT_MEM allows to specify user-defined functions for dynamically + memory management used internally by Capstone. This is useful to embed Capstone + into special environments such as kernel or firware. +- New API cs_support() can be used to check if this lib supports a particular + architecture (this is necessary since we now allow to choose which architectures + to compile in). +- The detail option is OFF by default now. To get detail information, it should be + explicitly turned ON. The details then can be accessed using cs_insn.detail + pointer (to newly added structure cs_detail) + + +[ Core changes ] + +- On memory usage, Capstone uses much less memory, but a lot faster now. +- User now can choose which architectures to be supported by modifying config.mk + before compiling/installing. + + +[ Architectures ] + +- Arm + - Support Big-Endian mode (besides Little-Endian mode). + - Support friendly register, so instead of output sub "r12,r11,0x14", + we have "sub ip,fp,0x14". +- Arm64: support Big-Endian mode (besides Little-Endian mode). +- PowerPC: newly added. +- Mips: support friendly register, so instead of output "srl $2,$1,0x1f", + we have "srl $v0,$at,0x1f". +- X86: bug fixes. + + +[ Python binding ] + +- Python binding is vastly improved in performance: around 3 ~ 4 times faster + than in 1.0. +- Cython support has been added, which can further speed up over the default + pure Python binding (up to 30% in some cases) +- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) + to return succesfully disassembled instructions. This improves the performance + and reduces memory usage. + + +[ Java binding ] + +- Better performance & bug fixes. + + +[ Miscellaneous ] + +- Fixed some installation issues with Gentoo Linux. +- Capstone now can easily compile/install on all *nix, including Linux, OSX, + {Net, Free, Open}BSD & Solaris. + +---------------------------------- +[Version 1.0]: December 18th, 2013 + +- Initial public release. + diff --git a/white_patch_detect/capstone-master/HACK.TXT b/white_patch_detect/capstone-master/HACK.TXT new file mode 100644 index 0000000..a928621 --- /dev/null +++ b/white_patch_detect/capstone-master/HACK.TXT @@ -0,0 +1,102 @@ +Code structure +-------------- + +Capstone source is organized as followings. + +. <- core engine + README + COMPILE.TXT etc +鈹溾攢鈹 arch <- code handling disasm engine for each arch +鈹偮犅 鈹溾攢鈹 AArch64 <- ARM64 (aka ARMv8) engine +鈹偮犅 鈹溾攢鈹 ARM <- ARM engine +鈹偮犅 鈹溾攢鈹 EVM <- Ethereum engine +鈹偮犅 鈹溾攢鈹 M680X <- M680X engine +鈹偮犅 鈹溾攢鈹 M68K <- M68K engine +鈹偮犅 鈹溾攢鈹 Mips <- Mips engine +鈹偮犅 鈹溾攢鈹 MOS65XX <- MOS65XX engine +鈹偮犅 鈹溾攢鈹 PowerPC <- PowerPC engine +鈹偮犅 鈹溾攢鈹 Sparc <- Sparc engine +鈹偮犅 鈹溾攢鈹 SystemZ <- SystemZ engine +鈹偮犅 鈹溾攢鈹 TMS320C64x <- TMS320C64x engine +鈹偮犅 鈹溾攢鈹 X86 <- X86 engine +鈹偮犅 鈹斺攢鈹 XCore <- XCore engine +鈹溾攢鈹 bindings <- all bindings are under this dir +鈹偮犅 鈹溾攢鈹 java <- Java bindings + test code +鈹偮犅 鈹溾攢鈹 ocaml <- Ocaml bindings + test code +鈹偮犅 鈹斺攢鈹 python <- Python bindings + test code +鈹溾攢鈹 contrib <- Code contributed by community to help Capstone integration +鈹溾攢鈹 cstool <- Cstool +鈹溾攢鈹 docs <- Documentation +鈹溾攢鈹 include <- API headers in C language (*.h) +鈹溾攢鈹 msvc <- Microsoft Visual Studio support (for Windows compile) +鈹溾攢鈹 packages <- Packages for Linux/OSX/BSD. +鈹溾攢鈹 windows <- Windows support (for Windows kernel driver compile) +鈹溾攢鈹 suite <- Development test tools - for Capstone developers only +鈹溾攢鈹 tests <- Test code (in C language) +鈹斺攢鈹 xcode <- Xcode support (for MacOSX compile) + + +Follow instructions in COMPILE.TXT for how to compile and run test code. + +Note: if you find some strange bugs, it is recommended to firstly clean +the code and try to recompile/reinstall again. This can be done with: + + $ ./make.sh + $ sudo ./make.sh install + +Then test Capstone with cstool, for example: + + $ cstool x32 "90 91" + +At the same time, for Java/Ocaml/Python bindings, be sure to always use +the bindings coming with the core to avoid potential incompatibility issue +with older versions. +See bindings//README for detail instructions on how to compile & +install the bindings. + + +Coding style +------------ +- C code follows Linux kernel coding style, using tabs for indentation. +- Python code uses 4 spaces for indentation. + + +Adding an architecture +---------------------- + +Obviously, you first need to write all the logic and put it in a new directory arch/newarch +Then, you have to modify other files. +(You can look for one architecture such as EVM in these files to get what you need to do) + +Integrate: +- cs.c +- cstool/cstool.c +- cstool/cstool_newarch.c: print the architecture specific details +- include/capstone/capstone.h +- include/capstone/newarch.h: create this file to export all specifics about the new architecture + +Compile: +- CMakeLists.txt +- Makefile +- config.mk + +Tests: +- tests/Makefile +- tests/test_basic.c +- tests/test_detail.c +- tests/test_iter.c +- tests/test_newarch.c +- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms + +Bindings: +- bindings/Makefile +- bindings/const_generator.py: add the header file and the architecture +- bindings/python/Makefile +- bindings/python/capstone/__init__.py +- bindings/python/capstone/newarch.py: define the python structures +- bindings/python/capstone/newarch_const.py: generate this file +- bindings/python/test_newarch.py: create a basic decoding test +- bindings/python/test_all.py + +Docs: +- README.md +- HACK.txt +- CREDITS.txt: add your name diff --git a/white_patch_detect/capstone-master/LEB128.h b/white_patch_detect/capstone-master/LEB128.h new file mode 100644 index 0000000..4fbc2cd --- /dev/null +++ b/white_patch_detect/capstone-master/LEB128.h @@ -0,0 +1,38 @@ +//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares some utility functions for encoding SLEB128 and +// ULEB128 values. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_SUPPORT_LEB128_H +#define CS_LLVM_SUPPORT_LEB128_H + +#include "include/capstone/capstone.h" + +/// Utility function to decode a ULEB128 value. +static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) +{ + const uint8_t *orig_p = p; + uint64_t Value = 0; + unsigned Shift = 0; + do { + Value += (uint64_t)(*p & 0x7f) << Shift; + Shift += 7; + } while (*p++ >= 128); + if (n) + *n = (unsigned)(p - orig_p); + return Value; +} + +#endif // LLVM_SYSTEM_LEB128_H diff --git a/white_patch_detect/capstone-master/LICENSE.TXT b/white_patch_detect/capstone-master/LICENSE.TXT new file mode 100644 index 0000000..0dabdc7 --- /dev/null +++ b/white_patch_detect/capstone-master/LICENSE.TXT @@ -0,0 +1,31 @@ +This is the software license for Capstone disassembly framework. +Capstone has been designed & implemented by Nguyen Anh Quynh + +See http://www.capstone-engine.org for further information. + +Copyright (c) 2013, COSEINC. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. +* Neither the name of the developer(s) nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/white_patch_detect/capstone-master/LICENSE_LLVM.TXT b/white_patch_detect/capstone-master/LICENSE_LLVM.TXT new file mode 100644 index 0000000..66d6647 --- /dev/null +++ b/white_patch_detect/capstone-master/LICENSE_LLVM.TXT @@ -0,0 +1,71 @@ +============================================================================== +LLVM Release License +============================================================================== +University of Illinois/NCSA +Open Source License + +Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. +All rights reserved. + +Developed by: + + LLVM Team + + University of Illinois at Urbana-Champaign + + http://llvm.org + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal with +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimers. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimers in the + documentation and/or other materials provided with the distribution. + + * Neither the names of the LLVM Team, University of Illinois at + Urbana-Champaign, nor the names of its contributors may be used to + endorse or promote products derived from this Software without specific + prior written permission. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE +SOFTWARE. + +============================================================================== +Copyrights and Licenses for Third Party Software Distributed with LLVM: +============================================================================== +The LLVM software contains code written by third parties. Such software will +have its own individual LICENSE.TXT file in the directory in which it appears. +This file will describe the copyrights, license, and restrictions which apply +to that code. + +The disclaimer of warranty in the University of Illinois Open Source License +applies to all code in the LLVM Distribution, and nothing in any of the +other licenses gives permission to use the names of the LLVM Team or the +University of Illinois to endorse or promote products derived from this +Software. + +The following pieces of software have additional or alternate copyrights, +licenses, and/or restrictions: + +Program Directory +------- --------- +Autoconf llvm/autoconf + llvm/projects/ModuleMaker/autoconf + llvm/projects/sample/autoconf +Google Test llvm/utils/unittest/googletest +OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} +pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} +ARM contributions llvm/lib/Target/ARM/LICENSE.TXT +md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h diff --git a/white_patch_detect/capstone-master/MCDisassembler.h b/white_patch_detect/capstone-master/MCDisassembler.h new file mode 100644 index 0000000..35d8e63 --- /dev/null +++ b/white_patch_detect/capstone-master/MCDisassembler.h @@ -0,0 +1,14 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_MCDISASSEMBLER_H +#define CS_MCDISASSEMBLER_H + +typedef enum DecodeStatus { + MCDisassembler_Fail = 0, + MCDisassembler_SoftFail = 1, + MCDisassembler_Success = 3, +} DecodeStatus; + +#endif + diff --git a/white_patch_detect/capstone-master/MCFixedLenDisassembler.h b/white_patch_detect/capstone-master/MCFixedLenDisassembler.h new file mode 100644 index 0000000..27ac115 --- /dev/null +++ b/white_patch_detect/capstone-master/MCFixedLenDisassembler.h @@ -0,0 +1,30 @@ +//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Fixed length disassembler decoder state machine driver. +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H +#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H + +// Disassembler state machine opcodes. +enum DecoderOps { + MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) + MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) + MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, + // uleb128 Val, uint16_t NumToSkip) + MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) + MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) + MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) + MCD_OPC_Fail // OPC_Fail() +}; + +#endif diff --git a/white_patch_detect/capstone-master/MCInst.c b/white_patch_detect/capstone-master/MCInst.c new file mode 100644 index 0000000..a9ac3b0 --- /dev/null +++ b/white_patch_detect/capstone-master/MCInst.c @@ -0,0 +1,182 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#include +#endif +#include + +#include "MCInst.h" +#include "utils.h" + +#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) + +void MCInst_Init(MCInst *inst) +{ + unsigned int i; + + for (i = 0; i < 48; i++) { + inst->Operands[i].Kind = kInvalid; + inst->Operands[i].ImmVal = 0; + } + + inst->Opcode = 0; + inst->OpcodePub = 0; + inst->size = 0; + inst->has_imm = false; + inst->op1_size = 0; + inst->writeback = false; + inst->ac_idx = 0; + inst->popcode_adjust = 0; + inst->assembly[0] = '\0'; +} + +void MCInst_clear(MCInst *inst) +{ + inst->size = 0; +} + +// do not free @Op +void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) +{ + int i; + + for(i = inst->size; i > index; i--) + //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); + inst->Operands[i] = inst->Operands[i-1]; + + inst->Operands[index] = *Op; + inst->size++; +} + +void MCInst_setOpcode(MCInst *inst, unsigned Op) +{ + inst->Opcode = Op; +} + +void MCInst_setOpcodePub(MCInst *inst, unsigned Op) +{ + inst->OpcodePub = Op; +} + +unsigned MCInst_getOpcode(const MCInst *inst) +{ + return inst->Opcode; +} + +unsigned MCInst_getOpcodePub(const MCInst *inst) +{ + return inst->OpcodePub; +} + +MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) +{ + return &inst->Operands[i]; +} + +unsigned MCInst_getNumOperands(const MCInst *inst) +{ + return inst->size; +} + +// This addOperand2 function doesnt free Op +void MCInst_addOperand2(MCInst *inst, MCOperand *Op) +{ + inst->Operands[inst->size] = *Op; + + inst->size++; +} + +bool MCOperand_isValid(const MCOperand *op) +{ + return op->Kind != kInvalid; +} + +bool MCOperand_isReg(const MCOperand *op) +{ + return op->Kind == kRegister; +} + +bool MCOperand_isImm(const MCOperand *op) +{ + return op->Kind == kImmediate; +} + +bool MCOperand_isFPImm(const MCOperand *op) +{ + return op->Kind == kFPImmediate; +} + +/// getReg - Returns the register number. +unsigned MCOperand_getReg(const MCOperand *op) +{ + return op->RegVal; +} + +/// setReg - Set the register number. +void MCOperand_setReg(MCOperand *op, unsigned Reg) +{ + op->RegVal = Reg; +} + +int64_t MCOperand_getImm(MCOperand *op) +{ + return op->ImmVal; +} + +void MCOperand_setImm(MCOperand *op, int64_t Val) +{ + op->ImmVal = Val; +} + +double MCOperand_getFPImm(const MCOperand *op) +{ + return op->FPImmVal; +} + +void MCOperand_setFPImm(MCOperand *op, double Val) +{ + op->FPImmVal = Val; +} + +MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) +{ + MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); + + op->Kind = kRegister; + op->RegVal = Reg; + + return op; +} + +void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) +{ + MCOperand *op = &(mcInst->Operands[mcInst->size]); + mcInst->size++; + + op->Kind = kRegister; + op->RegVal = Reg; +} + +MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) +{ + MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); + + op->Kind = kImmediate; + op->ImmVal = Val; + + return op; +} + +void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) +{ + MCOperand *op = &(mcInst->Operands[mcInst->size]); + mcInst->size++; + + op->Kind = kImmediate; + op->ImmVal = Val; +} diff --git a/white_patch_detect/capstone-master/MCInst.h b/white_patch_detect/capstone-master/MCInst.h new file mode 100644 index 0000000..6e95c3a --- /dev/null +++ b/white_patch_detect/capstone-master/MCInst.h @@ -0,0 +1,135 @@ +//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MCInst and MCOperand classes, which +// is the basic representation used to represent low-level machine code +// instructions. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_MCINST_H +#define CS_MCINST_H + +#include "include/capstone/capstone.h" + +typedef struct MCInst MCInst; +typedef struct cs_struct cs_struct; +typedef struct MCOperand MCOperand; + +/// MCOperand - Instances of this class represent operands of the MCInst class. +/// This is a simple discriminated union. +struct MCOperand { + enum { + kInvalid = 0, ///< Uninitialized. + kRegister, ///< Register operand. + kImmediate, ///< Immediate operand. + kFPImmediate, ///< Floating-point immediate operand. + } MachineOperandType; + unsigned char Kind; + + union { + unsigned RegVal; + int64_t ImmVal; + double FPImmVal; + }; +}; + +bool MCOperand_isValid(const MCOperand *op); + +bool MCOperand_isReg(const MCOperand *op); + +bool MCOperand_isImm(const MCOperand *op); + +bool MCOperand_isFPImm(const MCOperand *op); + +bool MCOperand_isInst(const MCOperand *op); + +/// getReg - Returns the register number. +unsigned MCOperand_getReg(const MCOperand *op); + +/// setReg - Set the register number. +void MCOperand_setReg(MCOperand *op, unsigned Reg); + +int64_t MCOperand_getImm(MCOperand *op); + +void MCOperand_setImm(MCOperand *op, int64_t Val); + +double MCOperand_getFPImm(const MCOperand *op); + +void MCOperand_setFPImm(MCOperand *op, double Val); + +const MCInst *MCOperand_getInst(const MCOperand *op); + +void MCOperand_setInst(MCOperand *op, const MCInst *Val); + +// create Reg operand in the next slot +void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); + +// create Reg operand use the last-unused slot +MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); + +// create Imm operand in the next slot +void MCOperand_CreateImm0(MCInst *inst, int64_t Val); + +// create Imm operand in the last-unused slot +MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); + +/// MCInst - Instances of this class represent a single low-level machine +/// instruction. +struct MCInst { + unsigned OpcodePub; + uint8_t size; // number of operands + bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax + uint8_t op1_size; // size of 1st operand - for X86 Intel syntax + unsigned Opcode; + MCOperand Operands[48]; + cs_insn *flat_insn; // insn to be exposed to public + uint64_t address; // address of this insn + cs_struct *csh; // save the main csh + uint8_t x86opsize; // opsize for [mem] operand + + // (Optional) instruction prefix, which can be up to 4 bytes. + // A prefix byte gets value 0 when irrelevant. + // This is copied from cs_x86 struct + uint8_t x86_prefix[4]; + uint8_t imm_size; // immediate size for X86_OP_IMM operand + bool writeback; // writeback for ARM + // operand access index for list of registers sharing the same access right (for ARM) + uint8_t ac_idx; + uint8_t popcode_adjust; // Pseudo X86 instruction adjust + char assembly[8]; // for special instruction, so that we dont need printer + unsigned char evm_data[32]; // for EVM PUSH operand +}; + +void MCInst_Init(MCInst *inst); + +void MCInst_clear(MCInst *inst); + +// do not free operand after inserting +void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); + +void MCInst_setOpcode(MCInst *inst, unsigned Op); + +unsigned MCInst_getOpcode(const MCInst*); + +void MCInst_setOpcodePub(MCInst *inst, unsigned Op); + +unsigned MCInst_getOpcodePub(const MCInst*); + +MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); + +unsigned MCInst_getNumOperands(const MCInst *inst); + +// This addOperand2 function doesnt free Op +void MCInst_addOperand2(MCInst *inst, MCOperand *Op); + +#endif diff --git a/white_patch_detect/capstone-master/MCInstrDesc.c b/white_patch_detect/capstone-master/MCInstrDesc.c new file mode 100644 index 0000000..1f70d86 --- /dev/null +++ b/white_patch_detect/capstone-master/MCInstrDesc.c @@ -0,0 +1,18 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "MCInstrDesc.h" + +/// isPredicate - Set if this is one of the operands that made up of +/// the predicate operand that controls an isPredicable() instruction. +bool MCOperandInfo_isPredicate(const MCOperandInfo *m) +{ + return m->Flags & (1 << MCOI_Predicate); +} + +/// isOptionalDef - Set if this operand is a optional def. +/// +bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m) +{ + return m->Flags & (1 << MCOI_OptionalDef); +} diff --git a/white_patch_detect/capstone-master/MCInstrDesc.h b/white_patch_detect/capstone-master/MCInstrDesc.h new file mode 100644 index 0000000..a71ec57 --- /dev/null +++ b/white_patch_detect/capstone-master/MCInstrDesc.h @@ -0,0 +1,144 @@ +//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCOperandInfo and MCInstrDesc classes, which +// are used to describe target instructions and their operands. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_MC_MCINSTRDESC_H +#define CS_LLVM_MC_MCINSTRDESC_H + +#include "capstone/platform.h" + +//===----------------------------------------------------------------------===// +// Machine Operand Flags and Description +//===----------------------------------------------------------------------===// + +// Operand constraints +enum MCOI_OperandConstraint { + MCOI_TIED_TO = 0, // Must be allocated the same register as. + MCOI_EARLY_CLOBBER // Operand is an early clobber register operand +}; + +/// OperandFlags - These are flags set on operands, but should be considered +/// private, all access should go through the MCOperandInfo accessors. +/// See the accessors for a description of what these are. +enum MCOI_OperandFlags { + MCOI_LookupPtrRegClass = 0, + MCOI_Predicate, + MCOI_OptionalDef +}; + +/// Operand Type - Operands are tagged with one of the values of this enum. +enum MCOI_OperandType { + MCOI_OPERAND_UNKNOWN, + MCOI_OPERAND_IMMEDIATE, + MCOI_OPERAND_REGISTER, + MCOI_OPERAND_MEMORY, + MCOI_OPERAND_PCREL +}; + + +/// MCOperandInfo - This holds information about one operand of a machine +/// instruction, indicating the register class for register operands, etc. +/// +typedef struct MCOperandInfo { + /// RegClass - This specifies the register class enumeration of the operand + /// if the operand is a register. If isLookupPtrRegClass is set, then this is + /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to + /// get a dynamic register class. + int16_t RegClass; + + /// Flags - These are flags from the MCOI::OperandFlags enum. + uint8_t Flags; + + /// OperandType - Information about the type of the operand. + uint8_t OperandType; + + /// Lower 16 bits are used to specify which constraints are set. The higher 16 + /// bits are used to specify the value of constraints (4 bits each). + uint32_t Constraints; + /// Currently no other information. +} MCOperandInfo; + + +//===----------------------------------------------------------------------===// +// Machine Instruction Flags and Description +//===----------------------------------------------------------------------===// + +/// MCInstrDesc flags - These should be considered private to the +/// implementation of the MCInstrDesc class. Clients should use the predicate +/// methods on MCInstrDesc, not use these directly. These all correspond to +/// bitfields in the MCInstrDesc::Flags field. +enum { + MCID_Variadic = 0, + MCID_HasOptionalDef, + MCID_Pseudo, + MCID_Return, + MCID_Call, + MCID_Barrier, + MCID_Terminator, + MCID_Branch, + MCID_IndirectBranch, + MCID_Compare, + MCID_MoveImm, + MCID_Bitcast, + MCID_Select, + MCID_DelaySlot, + MCID_FoldableAsLoad, + MCID_MayLoad, + MCID_MayStore, + MCID_Predicable, + MCID_NotDuplicable, + MCID_UnmodeledSideEffects, + MCID_Commutable, + MCID_ConvertibleTo3Addr, + MCID_UsesCustomInserter, + MCID_HasPostISelHook, + MCID_Rematerializable, + MCID_CheapAsAMove, + MCID_ExtraSrcRegAllocReq, + MCID_ExtraDefRegAllocReq, + MCID_RegSequence, + MCID_ExtractSubreg, + MCID_InsertSubreg +}; + +/// MCInstrDesc - Describe properties that are true of each instruction in the +/// target description file. This captures information about side effects, +/// register use and many other things. There is one instance of this struct +/// for each target instruction class, and the MachineInstr class points to +/// this struct directly to describe itself. +typedef struct MCInstrDesc { + unsigned short Opcode; // The opcode number + unsigned char NumOperands; // Num of args (may be more if variable_ops) + unsigned char NumDefs; // Num of args that are definitions + unsigned short SchedClass; // enum identifying instr sched class + unsigned char Size; // Number of bytes in encoding. + unsigned Flags; // Flags identifying machine instr class + uint64_t TSFlags; // Target Specific Flag values + char ImplicitUses; // Registers implicitly read by this instr + char ImplicitDefs; // Registers implicitly defined by this instr + const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands + uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any + // A complex method to determine is a certain is deprecated or not, and return + // the reason for deprecation. + //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &); + unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer +} MCInstrDesc; + +bool MCOperandInfo_isPredicate(const MCOperandInfo *m); + +bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m); + +#endif diff --git a/white_patch_detect/capstone-master/MCRegisterInfo.c b/white_patch_detect/capstone-master/MCRegisterInfo.c new file mode 100644 index 0000000..66db2f8 --- /dev/null +++ b/white_patch_detect/capstone-master/MCRegisterInfo.c @@ -0,0 +1,143 @@ +//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements MCRegisterInfo functions. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "MCRegisterInfo.h" + +/// DiffListIterator - Base iterator class that can traverse the +/// differentially encoded register and regunit lists in DiffLists. +/// Don't use this class directly, use one of the specialized sub-classes +/// defined below. +typedef struct DiffListIterator { + uint16_t Val; + const MCPhysReg *List; +} DiffListIterator; + +void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, + const MCRegisterDesc *D, unsigned NR, + unsigned RA, unsigned PC, + const MCRegisterClass *C, unsigned NC, + uint16_t (*RURoots)[2], unsigned NRU, + const MCPhysReg *DL, + const char *Strings, + const uint16_t *SubIndices, unsigned NumIndices, + const uint16_t *RET) +{ + RI->Desc = D; + RI->NumRegs = NR; + RI->RAReg = RA; + RI->PCReg = PC; + RI->Classes = C; + RI->DiffLists = DL; + RI->RegStrings = Strings; + RI->NumClasses = NC; + RI->RegUnitRoots = RURoots; + RI->NumRegUnits = NRU; + RI->SubRegIndices = SubIndices; + RI->NumSubRegIndices = NumIndices; + RI->RegEncodingTable = RET; +} + +static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList) +{ + d->Val = InitVal; + d->List = DiffList; +} + +static uint16_t DiffListIterator_getVal(DiffListIterator *d) +{ + return d->Val; +} + +static bool DiffListIterator_next(DiffListIterator *d) +{ + MCPhysReg D; + + if (d->List == 0) + return false; + + D = *d->List; + d->List++; + d->Val += D; + + if (!D) + d->List = 0; + + return (D != 0); +} + +static bool DiffListIterator_isValid(DiffListIterator *d) +{ + return (d->List != 0); +} + +unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) +{ + DiffListIterator iter; + + if (Reg >= RI->NumRegs) { + return 0; + } + + DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); + DiffListIterator_next(&iter); + + while(DiffListIterator_isValid(&iter)) { + uint16_t val = DiffListIterator_getVal(&iter); + if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) + return val; + + DiffListIterator_next(&iter); + } + + return 0; +} + +unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx) +{ + DiffListIterator iter; + const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; + + DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); + DiffListIterator_next(&iter); + + while(DiffListIterator_isValid(&iter)) { + if (*SRI == Idx) + return DiffListIterator_getVal(&iter); + DiffListIterator_next(&iter); + ++SRI; + } + + return 0; +} + +const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i) +{ + //assert(i < getNumRegClasses() && "Register Class ID out of range"); + if (i >= RI->NumClasses) + return 0; + return &(RI->Classes[i]); +} + +bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) +{ + unsigned InByte = Reg % 8; + unsigned Byte = Reg / 8; + + if (Byte >= c->RegSetSize) + return false; + + return (c->RegSet[Byte] & (1 << InByte)) != 0; +} diff --git a/white_patch_detect/capstone-master/MCRegisterInfo.h b/white_patch_detect/capstone-master/MCRegisterInfo.h new file mode 100644 index 0000000..3744ef7 --- /dev/null +++ b/white_patch_detect/capstone-master/MCRegisterInfo.h @@ -0,0 +1,116 @@ +//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes an abstract interface used to get information about a +// target machines register file. This information is used for a variety of +// purposed, especially register allocation. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_MC_MCREGISTERINFO_H +#define CS_LLVM_MC_MCREGISTERINFO_H + +#include "capstone/platform.h" + +/// An unsigned integer type large enough to represent all physical registers, +/// but not necessarily virtual registers. +typedef uint16_t MCPhysReg; +typedef const MCPhysReg* iterator; + +typedef struct MCRegisterClass { + iterator RegsBegin; + const uint8_t *RegSet; + uint32_t NameIdx; + uint16_t RegsSize; + uint16_t RegSetSize; + uint16_t ID; + uint16_t RegSize, Alignment; // Size & Alignment of register in bytes + int8_t CopyCost; + bool Allocatable; +} MCRegisterClass; + +/// MCRegisterDesc - This record contains information about a particular +/// register. The SubRegs field is a zero terminated array of registers that +/// are sub-registers of the specific register, e.g. AL, AH are sub-registers +/// of AX. The SuperRegs field is a zero terminated array of registers that are +/// super-registers of the specific register, e.g. RAX, EAX, are +/// super-registers of AX. +/// +typedef struct MCRegisterDesc { + uint32_t Name; // Printable name for the reg (for debugging) + uint32_t SubRegs; // Sub-register set, described above + uint32_t SuperRegs; // Super-register set, described above + + // Offset into MCRI::SubRegIndices of a list of sub-register indices for each + // sub-register in SubRegs. + uint32_t SubRegIndices; + + // RegUnits - Points to the list of register units. The low 4 bits holds the + // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. + uint32_t RegUnits; + + /// Index into list with lane mask sequences. The sequence contains a lanemask + /// for every register unit. + uint16_t RegUnitLaneMasks; +} MCRegisterDesc; + +/// MCRegisterInfo base class - We assume that the target defines a static +/// array of MCRegisterDesc objects that represent all of the machine +/// registers that the target has. As such, we simply have to track a pointer +/// to this array so that we can turn register number into a register +/// descriptor. +/// +/// Note this class is designed to be a base class of TargetRegisterInfo, which +/// is the interface used by codegen. However, specific targets *should never* +/// specialize this class. MCRegisterInfo should only contain getters to access +/// TableGen generated physical register data. It must not be extended with +/// virtual methods. +/// +typedef struct MCRegisterInfo { + const MCRegisterDesc *Desc; // Pointer to the descriptor array + unsigned NumRegs; // Number of entries in the array + unsigned RAReg; // Return address register + unsigned PCReg; // Program counter register + const MCRegisterClass *Classes; // Pointer to the regclass array + unsigned NumClasses; // Number of entries in the array + unsigned NumRegUnits; // Number of regunits. + uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. + const MCPhysReg *DiffLists; // Pointer to the difflists array + const char *RegStrings; // Pointer to the string table. + const uint16_t *SubRegIndices; // Pointer to the subreg lookup + // array. + unsigned NumSubRegIndices; // Number of subreg indices. + const uint16_t *RegEncodingTable; // Pointer to array of register + // encodings. +} MCRegisterInfo; + +void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, + const MCRegisterDesc *D, unsigned NR, unsigned RA, + unsigned PC, + const MCRegisterClass *C, unsigned NC, + uint16_t (*RURoots)[2], + unsigned NRU, + const MCPhysReg *DL, + const char *Strings, + const uint16_t *SubIndices, + unsigned NumIndices, + const uint16_t *RET); + +unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC); + +unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx); + +const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i); + +bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); + +#endif diff --git a/white_patch_detect/capstone-master/Makefile b/white_patch_detect/capstone-master/Makefile new file mode 100644 index 0000000..826aeb8 --- /dev/null +++ b/white_patch_detect/capstone-master/Makefile @@ -0,0 +1,549 @@ +# Capstone Disassembly Engine +# By Nguyen Anh Quynh , 2013-2014 + +include config.mk +include pkgconfig.mk # package version +include functions.mk + +# Verbose output? +V ?= 0 + +OS := $(shell uname) +ifeq ($(OS),Darwin) +LIBARCHS ?= x86_64 +PREFIX ?= /usr/local +endif + +ifeq ($(PKG_EXTRA),) +PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR) +else +PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) +endif + +ifeq ($(CROSS),) +RANLIB ?= ranlib +else ifeq ($(ANDROID), 1) +CC = $(CROSS)/../../bin/clang +AR = $(CROSS)/ar +RANLIB = $(CROSS)/ranlib +STRIP = $(CROSS)/strip +else +CC = $(CROSS)gcc +AR = $(CROSS)ar +RANLIB = $(CROSS)ranlib +STRIP = $(CROSS)strip +endif + +ifneq (,$(findstring yes,$(CAPSTONE_DIET))) +CFLAGS ?= -Os +CFLAGS += -DCAPSTONE_DIET +else +CFLAGS ?= -O3 +endif + +ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) +CFLAGS += -DCAPSTONE_X86_ATT_DISABLE +endif + +CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude + +ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) +CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM +endif + +ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes) +CFLAGS += -DCAPSTONE_HAS_OSXKERNEL +SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path) +CFLAGS += -mmacosx-version-min=10.5 \ + -isysroot$(SDKROOT) \ + -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \ + -mkernel \ + -fno-builtin +endif + +PREFIX ?= /usr +DESTDIR ?= +ifndef BUILDDIR +BLDIR = . +OBJDIR = . +else +BLDIR = $(abspath $(BUILDDIR)) +OBJDIR = $(BLDIR)/obj +endif +INCDIR ?= $(PREFIX)/include + +UNAME_S := $(shell uname -s) + +LIBDIRARCH ?= lib +# Uncomment the below line to installs x86_64 libs to lib64/ directory. +# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'. +#LIBDIRARCH ?= lib64 +LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH) +BINDIR = $(DESTDIR)$(PREFIX)/bin + +LIBDATADIR = $(LIBDIR) + +# Don't redefine $LIBDATADIR when global environment variable +# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework. + +ifndef USE_GENERIC_LIBDATADIR +ifeq ($(UNAME_S), FreeBSD) +LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata +endif +ifeq ($(UNAME_S), DragonFly) +LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata +endif +endif + +INSTALL_BIN ?= install +INSTALL_DATA ?= $(INSTALL_BIN) -m0644 +INSTALL_LIB ?= $(INSTALL_BIN) -m0755 + +LIBNAME = capstone + + +DEP_ARM = +DEP_ARM += $(wildcard arch/ARM/ARM*.inc) + +LIBOBJ_ARM = +ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_ARM + LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c) + LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o) +endif + +DEP_ARM64 = +DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc) + +LIBOBJ_ARM64 = +ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_ARM64 + LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c) + LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o) +endif + + +DEP_M68K = +DEP_M68K += $(wildcard arch/M68K/M68K*.h) + +LIBOBJ_M68K = +ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_M68K + LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c) + LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o) +endif + +DEP_MIPS = +DEP_MIPS += $(wildcard arch/Mips/Mips*.inc) + +LIBOBJ_MIPS = +ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_MIPS + LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c) + LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o) +endif + + +DEP_PPC = +DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc) + +LIBOBJ_PPC = +ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_POWERPC + LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c) + LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o) +endif + + +DEP_SPARC = +DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc) + +LIBOBJ_SPARC = +ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_SPARC + LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c) + LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o) +endif + + +DEP_SYSZ = +DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc) + +LIBOBJ_SYSZ = +ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_SYSZ + LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c) + LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o) +endif + + +# by default, we compile full X86 instruction sets +X86_REDUCE = +ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE))) +X86_REDUCE = _reduce +CFLAGS += -DCAPSTONE_X86_REDUCE -Os +endif + +DEP_X86 = +DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86GenRegisterInfo.inc +DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc +DEP_X86 += arch/X86/X86ImmSize.inc + +LIBOBJ_X86 = +ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_X86 + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o +# assembly syntax is irrelevant in Diet mode, when this info is suppressed +ifeq (,$(findstring yes,$(CAPSTONE_DIET))) +ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o +endif +endif + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o + LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o +endif + + +DEP_XCORE = +DEP_XCORE += $(wildcard arch/XCore/XCore*.inc) + +LIBOBJ_XCORE = +ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_XCORE + LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c) + LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o) +endif + + +DEP_TMS320C64X = +DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc) + +LIBOBJ_TMS320C64X = +ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_TMS320C64X + LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c) + LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o) +endif + +DEP_M680X = +DEP_M680X += $(wildcard arch/M680X/*.inc) +DEP_M680X += $(wildcard arch/M680X/M680X*.h) + +LIBOBJ_M680X = +ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_M680X + LIBSRC_M680X += $(wildcard arch/M680X/*.c) + LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o) +endif + + +DEP_EVM = +DEP_EVM += $(wildcard arch/EVM/EVM*.inc) + +LIBOBJ_EVM = +ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_EVM + LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c) + LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o) +endif + + +DEP_MOS65XX = +DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc) + +LIBOBJ_MOS65XX = +ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_MOS65XX + LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c) + LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o) +endif + + +LIBOBJ = +LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o +LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) +LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) +LIBOBJ += $(OBJDIR)/MCInst.o + + +ifeq ($(PKG_EXTRA),) +PKGCFGDIR = $(LIBDATADIR)/pkgconfig +else +PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig +ifeq ($(PKGCFGDIR),) +PKGCFGDIR = $(LIBDATADIR)/pkgconfig +endif +endif + +API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}') +VERSION_EXT = + +IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ") +ifeq ($(IS_APPLE),1) +# on MacOS, do not build in Universal format by default +MACOS_UNIVERSAL ?= no +ifeq ($(MACOS_UNIVERSAL),yes) +CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +endif +EXT = dylib +VERSION_EXT = $(API_MAJOR).$(EXT) +$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) +AR_EXT = a +# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE +# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default +ifneq ($(HOMEBREW_CAPSTONE),1) +ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) +# remove string check because OSX kernel complains about missing symbols +CFLAGS += -D_FORTIFY_SOURCE=0 +endif +endif +else +CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +$(LIBNAME)_LDFLAGS += -shared +# Cygwin? +IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) +ifeq ($(IS_CYGWIN),1) +EXT = dll +AR_EXT = lib +# Cygwin doesn't like -fPIC +CFLAGS := $(CFLAGS:-fPIC=) +# On Windows we need the shared library to be executable +else +# mingw? +IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) +ifeq ($(IS_MINGW),1) +EXT = dll +AR_EXT = lib +# mingw doesn't like -fPIC either +CFLAGS := $(CFLAGS:-fPIC=) +# On Windows we need the shared library to be executable +else +# Linux, *BSD +EXT = so +VERSION_EXT = $(EXT).$(API_MAJOR) +AR_EXT = a +$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT) +endif +endif +endif + +ifeq ($(CAPSTONE_SHARED),yes) +ifeq ($(IS_MINGW),1) +LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) +else ifeq ($(IS_CYGWIN),1) +LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) +else # *nix +LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT) +CFLAGS += -fvisibility=hidden +endif +endif + +ifeq ($(CAPSTONE_STATIC),yes) +ifeq ($(IS_MINGW),1) +ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) +else ifeq ($(IS_CYGWIN),1) +ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) +else +ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT) +endif +endif + +PKGCFGF = $(BLDIR)/$(LIBNAME).pc + +.PHONY: all clean install uninstall dist + +all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF) +ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) + @V=$(V) CC=$(CC) $(MAKE) -C cstool +ifndef BUILDDIR + $(MAKE) -C tests + $(MAKE) -C suite/fuzz +else + $(MAKE) -C tests BUILDDIR=$(BLDIR) + $(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR) +endif + $(call install-library,$(BLDIR)/tests/) +endif + +ifeq ($(CAPSTONE_SHARED),yes) +$(LIBRARY): $(LIBOBJ) +ifeq ($(V),0) + $(call log,LINK,$(@:$(BLDIR)/%=%)) + @$(create-library) +else + $(create-library) +endif +endif + +$(LIBOBJ): config.mk *.h include/capstone/*.h + +$(LIBOBJ_ARM): $(DEP_ARM) +$(LIBOBJ_ARM64): $(DEP_ARM64) +$(LIBOBJ_M68K): $(DEP_M68K) +$(LIBOBJ_MIPS): $(DEP_MIPS) +$(LIBOBJ_PPC): $(DEP_PPC) +$(LIBOBJ_SPARC): $(DEP_SPARC) +$(LIBOBJ_SYSZ): $(DEP_SYSZ) +$(LIBOBJ_X86): $(DEP_X86) +$(LIBOBJ_XCORE): $(DEP_XCORE) +$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X) +$(LIBOBJ_M680X): $(DEP_M680X) +$(LIBOBJ_EVM): $(DEP_EVM) +$(LIBOBJ_MOS65XX): $(DEP_MOS65XX) + +ifeq ($(CAPSTONE_STATIC),yes) +$(ARCHIVE): $(LIBOBJ) + @rm -f $(ARCHIVE) +ifeq ($(V),0) + $(call log,AR,$(@:$(BLDIR)/%=%)) + @$(create-archive) +else + $(create-archive) +endif +endif + +$(PKGCFGF): +ifeq ($(V),0) + $(call log,GEN,$(@:$(BLDIR)/%=%)) + @$(generate-pkgcfg) +else + $(generate-pkgcfg) +endif + +install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY) + mkdir -p $(LIBDIR) + $(call install-library,$(LIBDIR)) +ifeq ($(CAPSTONE_STATIC),yes) + $(INSTALL_DATA) $(ARCHIVE) $(LIBDIR) +endif + mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME) + $(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME) + mkdir -p $(PKGCFGDIR) + $(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR) +ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) + mkdir -p $(BINDIR) + $(INSTALL_LIB) cstool/cstool $(BINDIR) +endif + +uninstall: + rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME) + rm -f $(LIBDIR)/lib$(LIBNAME).* + rm -f $(PKGCFGDIR)/$(LIBNAME).pc +ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) + rm -f $(BINDIR)/cstool +endif + +clean: + rm -f $(LIBOBJ) + rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc + rm -f $(PKGCFGF) + [ "${ANDROID}" = "1" ] && rm -rf android-ndk-* || true + +ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) + $(MAKE) -C cstool clean + $(MAKE) -C tests clean + $(MAKE) -C suite/fuzz clean + rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT) +endif + +ifdef BUILDDIR + rm -rf $(BUILDDIR) +endif + +ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) + $(MAKE) -C bindings/python clean + $(MAKE) -C bindings/java clean + $(MAKE) -C bindings/ocaml clean +endif + + +TAG ?= HEAD +ifeq ($(TAG), HEAD) +DIST_VERSION = latest +else +DIST_VERSION = $(TAG) +endif + +dist: + git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz + git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip + + +TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc +TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_mos65xx +TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static +TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static +TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static +TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static +TESTS += test_mos65xx.static +check: $(TESTS) fuzztest fuzzallcorp +test_%: + ./tests/$@ > /dev/null && echo OK || echo FAILED + +FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs') + +fuzztest: + ./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS) + +fuzzallcorp: +ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),) + ./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/ +else + @echo "Skipping tests on whole corpus" +endif + +$(OBJDIR)/%.o: %.c + @mkdir -p $(@D) +ifeq ($(V),0) + $(call log,CC,$(@:$(OBJDIR)/%=%)) + @$(compile) +else + $(compile) +endif + + +ifeq ($(CAPSTONE_SHARED),yes) +define install-library + $(INSTALL_LIB) $(LIBRARY) $1 + $(if $(VERSION_EXT), + cd $1 && \ + rm -f lib$(LIBNAME).$(EXT) && \ + ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)) +endef +else +define install-library +endef +endif + + +define create-archive + $(AR) q $(ARCHIVE) $(LIBOBJ) + $(RANLIB) $(ARCHIVE) +endef + + +define create-library + $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY) +endef + + +define generate-pkgcfg + mkdir -p $(BLDIR) + echo 'Name: capstone' > $(PKGCFGF) + echo 'Description: Capstone disassembly engine' >> $(PKGCFGF) + echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF) + echo 'libdir=$(LIBDIR)' >> $(PKGCFGF) + echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF) + echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF) + echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF) + echo 'Cflags: -I$${includedir}' >> $(PKGCFGF) +endef diff --git a/white_patch_detect/capstone-master/MathExtras.h b/white_patch_detect/capstone-master/MathExtras.h new file mode 100644 index 0000000..1890b93 --- /dev/null +++ b/white_patch_detect/capstone-master/MathExtras.h @@ -0,0 +1,442 @@ +//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains some functions that are useful for math stuff. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H +#define CS_LLVM_SUPPORT_MATHEXTRAS_H + +#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) +#include "windowsce/intrin.h" +#elif defined(_MSC_VER) +#include +#endif + +#ifndef __cplusplus +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#define inline /* inline */ +#endif +#endif + +// NOTE: The following support functions use the _32/_64 extensions instead of +// type overloading so that signed and unsigned integers can be used without +// ambiguity. + +/// Hi_32 - This function returns the high 32 bits of a 64 bit value. +static inline uint32_t Hi_32(uint64_t Value) { + return (uint32_t)(Value >> 32); +} + +/// Lo_32 - This function returns the low 32 bits of a 64 bit value. +static inline uint32_t Lo_32(uint64_t Value) { + return (uint32_t)(Value); +} + +/// isUIntN - Checks if an unsigned integer fits into the given (dynamic) +/// bit width. +static inline bool isUIntN(unsigned N, uint64_t x) { + return x == (x & (~0ULL >> (64 - N))); +} + +/// isIntN - Checks if an signed integer fits into the given (dynamic) +/// bit width. +//static inline bool isIntN(unsigned N, int64_t x) { +// return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1))); +//} + +/// isMask_32 - This function returns true if the argument is a sequence of ones +/// starting at the least significant bit with the remainder zero (32 bit +/// version). Ex. isMask_32(0x0000FFFFU) == true. +static inline bool isMask_32(uint32_t Value) { + return Value && ((Value + 1) & Value) == 0; +} + +/// isMask_64 - This function returns true if the argument is a sequence of ones +/// starting at the least significant bit with the remainder zero (64 bit +/// version). +static inline bool isMask_64(uint64_t Value) { + return Value && ((Value + 1) & Value) == 0; +} + +/// isShiftedMask_32 - This function returns true if the argument contains a +/// sequence of ones with the remainder zero (32 bit version.) +/// Ex. isShiftedMask_32(0x0000FF00U) == true. +static inline bool isShiftedMask_32(uint32_t Value) { + return isMask_32((Value - 1) | Value); +} + +/// isShiftedMask_64 - This function returns true if the argument contains a +/// sequence of ones with the remainder zero (64 bit version.) +static inline bool isShiftedMask_64(uint64_t Value) { + return isMask_64((Value - 1) | Value); +} + +/// isPowerOf2_32 - This function returns true if the argument is a power of +/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) +static inline bool isPowerOf2_32(uint32_t Value) { + return Value && !(Value & (Value - 1)); +} + +/// CountLeadingZeros_32 - this function performs the platform optimal form of +/// counting the number of zeros from the most significant bit to the first one +/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. +/// Returns 32 if the word is zero. +static inline unsigned CountLeadingZeros_32(uint32_t Value) { + unsigned Count; // result +#if __GNUC__ >= 4 + // PowerPC is defined for __builtin_clz(0) +#if !defined(__ppc__) && !defined(__ppc64__) + if (!Value) return 32; +#endif + Count = __builtin_clz(Value); +#else + unsigned Shift; + if (!Value) return 32; + Count = 0; + // bisection method for count leading zeros + for (Shift = 32 >> 1; Shift; Shift >>= 1) { + uint32_t Tmp = Value >> Shift; + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } +#endif + return Count; +} + +/// CountLeadingOnes_32 - this function performs the operation of +/// counting the number of ones from the most significant bit to the first zero +/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8. +/// Returns 32 if the word is all ones. +static inline unsigned CountLeadingOnes_32(uint32_t Value) { + return CountLeadingZeros_32(~Value); +} + +/// CountLeadingZeros_64 - This function performs the platform optimal form +/// of counting the number of zeros from the most significant bit to the first +/// one bit (64 bit edition.) +/// Returns 64 if the word is zero. +static inline unsigned CountLeadingZeros_64(uint64_t Value) { + unsigned Count; // result +#if __GNUC__ >= 4 + // PowerPC is defined for __builtin_clzll(0) +#if !defined(__ppc__) && !defined(__ppc64__) + if (!Value) return 64; +#endif + Count = __builtin_clzll(Value); +#else +#ifndef _MSC_VER + unsigned Shift; + if (sizeof(long) == sizeof(int64_t)) + { + if (!Value) return 64; + Count = 0; + // bisection method for count leading zeros + for (Shift = 64 >> 1; Shift; Shift >>= 1) { + uint64_t Tmp = Value >> Shift; + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } + } + else +#endif + { + // get hi portion + uint32_t Hi = Hi_32(Value); + + // if some bits in hi portion + if (Hi) { + // leading zeros in hi portion plus all bits in lo portion + Count = CountLeadingZeros_32(Hi); + } else { + // get lo portion + uint32_t Lo = Lo_32(Value); + // same as 32 bit value + Count = CountLeadingZeros_32(Lo)+32; + } + } +#endif + return Count; +} + +/// CountLeadingOnes_64 - This function performs the operation +/// of counting the number of ones from the most significant bit to the first +/// zero bit (64 bit edition.) +/// Returns 64 if the word is all ones. +static inline unsigned CountLeadingOnes_64(uint64_t Value) { + return CountLeadingZeros_64(~Value); +} + +/// CountTrailingZeros_32 - this function performs the platform optimal form of +/// counting the number of zeros from the least significant bit to the first one +/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8. +/// Returns 32 if the word is zero. +static inline unsigned CountTrailingZeros_32(uint32_t Value) { +#if __GNUC__ >= 4 + return Value ? __builtin_ctz(Value) : 32; +#else + static const unsigned Mod37BitPosition[] = { + 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, + 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, + 5, 20, 8, 19, 18 + }; + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return Mod37BitPosition[(-Value & Value) % 37]; + return Mod37BitPosition[((1 + ~Value) & Value) % 37]; +#endif +} + +/// CountTrailingOnes_32 - this function performs the operation of +/// counting the number of ones from the least significant bit to the first zero +/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8. +/// Returns 32 if the word is all ones. +static inline unsigned CountTrailingOnes_32(uint32_t Value) { + return CountTrailingZeros_32(~Value); +} + +/// CountTrailingZeros_64 - This function performs the platform optimal form +/// of counting the number of zeros from the least significant bit to the first +/// one bit (64 bit edition.) +/// Returns 64 if the word is zero. +static inline unsigned CountTrailingZeros_64(uint64_t Value) { +#if __GNUC__ >= 4 + return Value ? __builtin_ctzll(Value) : 64; +#else + static const unsigned Mod67Position[] = { + 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, + 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, + 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, + 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, + 7, 48, 35, 6, 34, 33, 0 + }; + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return Mod67Position[(-Value & Value) % 67]; + return Mod67Position[((1 + ~Value) & Value) % 67]; +#endif +} + +/// CountTrailingOnes_64 - This function performs the operation +/// of counting the number of ones from the least significant bit to the first +/// zero bit (64 bit edition.) +/// Returns 64 if the word is all ones. +static inline unsigned CountTrailingOnes_64(uint64_t Value) { + return CountTrailingZeros_64(~Value); +} + +/// CountPopulation_32 - this function counts the number of set bits in a value. +/// Ex. CountPopulation(0xF000F000) = 8 +/// Returns 0 if the word is zero. +static inline unsigned CountPopulation_32(uint32_t Value) { +#if __GNUC__ >= 4 + return __builtin_popcount(Value); +#else + uint32_t v = Value - ((Value >> 1) & 0x55555555); + v = (v & 0x33333333) + ((v >> 2) & 0x33333333); + return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; +#endif +} + +/// CountPopulation_64 - this function counts the number of set bits in a value, +/// (64 bit edition.) +static inline unsigned CountPopulation_64(uint64_t Value) { +#if __GNUC__ >= 4 + return __builtin_popcountll(Value); +#else + uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); + v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); + v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + return (uint64_t)((v * 0x0101010101010101ULL) >> 56); +#endif +} + +/// Log2_32 - This function returns the floor log base 2 of the specified value, +/// -1 if the value is zero. (32 bit edition.) +/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 +static inline unsigned Log2_32(uint32_t Value) { + return 31 - CountLeadingZeros_32(Value); +} + +/// Log2_64 - This function returns the floor log base 2 of the specified value, +/// -1 if the value is zero. (64 bit edition.) +static inline unsigned Log2_64(uint64_t Value) { + return 63 - CountLeadingZeros_64(Value); +} + +/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified +/// value, 32 if the value is zero. (32 bit edition). +/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 +static inline unsigned Log2_32_Ceil(uint32_t Value) { + return 32-CountLeadingZeros_32(Value-1); +} + +/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified +/// value, 64 if the value is zero. (64 bit edition.) +static inline unsigned Log2_64_Ceil(uint64_t Value) { + return 64-CountLeadingZeros_64(Value-1); +} + +/// GreatestCommonDivisor64 - Return the greatest common divisor of the two +/// values using Euclid's algorithm. +static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { + while (B) { + uint64_t T = B; + B = A % B; + A = T; + } + return A; +} + +/// BitsToDouble - This function takes a 64-bit integer and returns the bit +/// equivalent double. +static inline double BitsToDouble(uint64_t Bits) { + union { + uint64_t L; + double D; + } T; + T.L = Bits; + return T.D; +} + +/// BitsToFloat - This function takes a 32-bit integer and returns the bit +/// equivalent float. +static inline float BitsToFloat(uint32_t Bits) { + union { + uint32_t I; + float F; + } T; + T.I = Bits; + return T.F; +} + +/// DoubleToBits - This function takes a double and returns the bit +/// equivalent 64-bit integer. Note that copying doubles around +/// changes the bits of NaNs on some hosts, notably x86, so this +/// routine cannot be used if these bits are needed. +static inline uint64_t DoubleToBits(double Double) { + union { + uint64_t L; + double D; + } T; + T.D = Double; + return T.L; +} + +/// FloatToBits - This function takes a float and returns the bit +/// equivalent 32-bit integer. Note that copying floats around +/// changes the bits of NaNs on some hosts, notably x86, so this +/// routine cannot be used if these bits are needed. +static inline uint32_t FloatToBits(float Float) { + union { + uint32_t I; + float F; + } T; + T.F = Float; + return T.I; +} + +/// MinAlign - A and B are either alignments or offsets. Return the minimum +/// alignment that may be assumed after adding the two together. +static inline uint64_t MinAlign(uint64_t A, uint64_t B) { + // The largest power of 2 that divides both A and B. + // + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return (A | B) & -(A | B); + return (A | B) & (1 + ~(A | B)); +} + +/// NextPowerOf2 - Returns the next power of two (in 64-bits) +/// that is strictly greater than A. Returns zero on overflow. +static inline uint64_t NextPowerOf2(uint64_t A) { + A |= (A >> 1); + A |= (A >> 2); + A |= (A >> 4); + A |= (A >> 8); + A |= (A >> 16); + A |= (A >> 32); + return A + 1; +} + +/// Returns the next integer (mod 2**64) that is greater than or equal to +/// \p Value and is a multiple of \p Align. \p Align must be non-zero. +/// +/// Examples: +/// \code +/// RoundUpToAlignment(5, 8) = 8 +/// RoundUpToAlignment(17, 8) = 24 +/// RoundUpToAlignment(~0LL, 8) = 0 +/// \endcode +static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { + return ((Value + Align - 1) / Align) * Align; +} + +/// Returns the offset to the next integer (mod 2**64) that is greater than +/// or equal to \p Value and is a multiple of \p Align. \p Align must be +/// non-zero. +static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { + return RoundUpToAlignment(Value, Align) - Value; +} + +/// abs64 - absolute value of a 64-bit int. Not all environments support +/// "abs" on whatever their name for the 64-bit int type is. The absolute +/// value of the largest negative number is undefined, as with "abs". +static inline int64_t abs64(int64_t x) { + return (x < 0) ? -x : x; +} + +/// \brief Sign extend number in the bottom B bits of X to a 32-bit int. +/// Requires 0 < B <= 32. +static inline int32_t SignExtend32(uint32_t X, unsigned B) { + return (int32_t)(X << (32 - B)) >> (32 - B); +} + +/// \brief Sign extend number in the bottom B bits of X to a 64-bit int. +/// Requires 0 < B <= 64. +static inline int64_t SignExtend64(uint64_t X, unsigned B) { + return (int64_t)(X << (64 - B)) >> (64 - B); +} + +/// \brief Count number of 0's from the most significant bit to the least +/// stopping at the first 1. +/// +/// Only unsigned integral types are allowed. +/// +/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are +/// valid arguments. +static inline unsigned int countLeadingZeros(int x) +{ + int i; + const unsigned bits = sizeof(x) * 8; + unsigned count = bits; + + if (x < 0) { + return 0; + } + for (i = bits; --i; ) { + if (x == 0) break; + count--; + x >>= 1; + } + + return count; +} + +#endif diff --git a/white_patch_detect/capstone-master/README.md b/white_patch_detect/capstone-master/README.md new file mode 100644 index 0000000..1a61b94 --- /dev/null +++ b/white_patch_detect/capstone-master/README.md @@ -0,0 +1,67 @@ +Capstone Engine +=============== + +[![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=master)](https://travis-ci.org/aquynh/capstone) +[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/master?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/master) +[![pypi package](https://badge.fury.io/py/capstone.svg)](https://pypi.python.org/pypi/capstone) +[![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone) + +Capstone is a disassembly framework with the target of becoming the ultimate +disasm engine for binary analysis and reversing in the security community. + +Created by Nguyen Anh Quynh, then developed and maintained by a small community, +Capstone offers some unparalleled features: + +- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K, + Mips, MOS65XX, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64). + +- Having clean/simple/lightweight/intuitive architecture-neutral API. + +- Provide details on disassembled instruction (called 鈥渄ecomposer鈥 by others). + +- Provide semantics of the disassembled instruction, such as list of implicit + registers read & written. + +- Implemented in pure C language, with lightweight bindings for D, Clojure, F#, + Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python, + Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala + (ready either in main code, or provided externally by the community). + +- Native support for all popular platforms: Windows, Mac OSX, iOS, Android, + Linux, \*BSD, Solaris, etc. + +- Thread-safe by design. + +- Special support for embedding into firmware or OS kernel. + +- High performance & suitable for malware analysis (capable of handling various + X86 malware tricks). + +- Distributed under the open source BSD license. + +Further information is available at http://www.capstone-engine.org + + +Compile +------- + +See COMPILE.TXT file for how to compile and install Capstone. + + +Documentation +------------- + +See docs/README for how to customize & program your own tools with Capstone. + + +Hack +---- + +See HACK.TXT file for the structure of the source code. + + +License +------- + +This project is released under the BSD license. If you redistribute the binary +or source code of Capstone, please attach file LICENSE.TXT with your products. diff --git a/white_patch_detect/capstone-master/RELEASE_NOTES b/white_patch_detect/capstone-master/RELEASE_NOTES new file mode 100644 index 0000000..e69de29 diff --git a/white_patch_detect/capstone-master/SPONSORS.TXT b/white_patch_detect/capstone-master/SPONSORS.TXT new file mode 100644 index 0000000..e737e2a --- /dev/null +++ b/white_patch_detect/capstone-master/SPONSORS.TXT @@ -0,0 +1,20 @@ +* Version 4.0.1 - January 10th, 2019 + +Release 4.0.1 was sponsored by the following companies (in no particular order). + +- NowSecure: https://www.nowsecure.com +- Verichains: https://verichains.io +- Vsec: https://vsec.com.vn + +----------------------------------- +* Version 4.0 - December 18th, 2018 + +Capstone 4.0 version marks 5 years of the project! +This release was sponsored by the following companies (in no particular order). + +- Thinkst Canary: https://canary.tools +- NowSecure: https://www.nowsecure.com +- ECQ: https://e-cq.net +- Senrio: https://senr.io +- GracefulBits: https://gracefulbits.com +- Catena Cyber: https://catenacyber.fr diff --git a/white_patch_detect/capstone-master/SStream.c b/white_patch_detect/capstone-master/SStream.c new file mode 100644 index 0000000..5ae237f --- /dev/null +++ b/white_patch_detect/capstone-master/SStream.c @@ -0,0 +1,188 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#include +#else +#include +#include +#endif +#include + +#include + +#include "SStream.h" +#include "cs_priv.h" +#include "utils.h" + +#ifdef _MSC_VER +#pragma warning(disable: 4996) // disable MSVC's warning on strcpy() +#endif + +void SStream_Init(SStream *ss) +{ + ss->index = 0; + ss->buffer[0] = '\0'; +} + +void SStream_concat0(SStream *ss, const char *s) +{ +#ifndef CAPSTONE_DIET + unsigned int len = (unsigned int) strlen(s); + + memcpy(ss->buffer + ss->index, s, len); + ss->index += len; + ss->buffer[ss->index] = '\0'; +#endif +} + +void SStream_concat(SStream *ss, const char *fmt, ...) +{ +#ifndef CAPSTONE_DIET + va_list ap; + int ret; + + va_start(ap, fmt); + ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); + va_end(ap); + ss->index += ret; +#endif +} + +// print number with prefix # +void printInt64Bang(SStream *O, int64_t val) +{ + if (val >= 0) { + if (val > HEX_THRESHOLD) + SStream_concat(O, "#0x%"PRIx64, val); + else + SStream_concat(O, "#%"PRIu64, val); + } else { + if (val <- HEX_THRESHOLD) { + if (val == LONG_MIN) + SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val); + else + SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val); + } + else + SStream_concat(O, "#-%"PRIu64, -val); + } +} + +void printUInt64Bang(SStream *O, uint64_t val) +{ + if (val > HEX_THRESHOLD) + SStream_concat(O, "#0x%"PRIx64, val); + else + SStream_concat(O, "#%"PRIu64, val); +} + +// print number +void printInt64(SStream *O, int64_t val) +{ + if (val >= 0) { + if (val > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, val); + else + SStream_concat(O, "%"PRIu64, val); + } else { + if (val <- HEX_THRESHOLD) { + if (val == LONG_MIN) + SStream_concat(O, "-0x%"PRIx64, (uint64_t)val); + else + SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val); + } + else + SStream_concat(O, "-%"PRIu64, -val); + } +} + +// print number in decimal mode +void printInt32BangDec(SStream *O, int32_t val) +{ + if (val >= 0) + SStream_concat(O, "#%u", val); + else + if (val == INT_MIN) + SStream_concat(O, "#-%u", val); + else + SStream_concat(O, "#-%u", (uint32_t)-val); +} + +void printInt32Bang(SStream *O, int32_t val) +{ + if (val >= 0) { + if (val > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", val); + else + SStream_concat(O, "#%u", val); + } else { + if (val <- HEX_THRESHOLD) { + if (val == INT_MIN) + SStream_concat(O, "#-0x%x", (uint32_t)val); + else + SStream_concat(O, "#-0x%x", (uint32_t)-val); + } + else + SStream_concat(O, "#-%u", -val); + } +} + +void printInt32(SStream *O, int32_t val) +{ + if (val >= 0) { + if (val > HEX_THRESHOLD) + SStream_concat(O, "0x%x", val); + else + SStream_concat(O, "%u", val); + } else { + if (val <- HEX_THRESHOLD) { + if (val == INT_MIN) + SStream_concat(O, "-0x%x", (uint32_t)val); + else + SStream_concat(O, "-0x%x", (uint32_t)-val); + } + else + SStream_concat(O, "-%u", -val); + } +} + +void printUInt32Bang(SStream *O, uint32_t val) +{ + if (val > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", val); + else + SStream_concat(O, "#%u", val); +} + +void printUInt32(SStream *O, uint32_t val) +{ + if (val > HEX_THRESHOLD) + SStream_concat(O, "0x%x", val); + else + SStream_concat(O, "%u", val); +} + +/* + int main() + { + SStream ss; + int64_t i; + + SStream_Init(&ss); + + SStream_concat(&ss, "hello "); + SStream_concat(&ss, "%d - 0x%x", 200, 16); + + i = 123; + SStream_concat(&ss, " + %ld", i); + SStream_concat(&ss, "%s", "haaaaa"); + + printf("%s\n", ss.buffer); + + return 0; + } + */ diff --git a/white_patch_detect/capstone-master/SStream.h b/white_patch_detect/capstone-master/SStream.h new file mode 100644 index 0000000..3473085 --- /dev/null +++ b/white_patch_detect/capstone-master/SStream.h @@ -0,0 +1,37 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SSTREAM_H_ +#define CS_SSTREAM_H_ + +#include "include/capstone/platform.h" + +typedef struct SStream { + char buffer[512]; + int index; +} SStream; + +void SStream_Init(SStream *ss); + +void SStream_concat(SStream *ss, const char *fmt, ...); + +void SStream_concat0(SStream *ss, const char *s); + +void printInt64Bang(SStream *O, int64_t val); + +void printUInt64Bang(SStream *O, uint64_t val); + +void printInt64(SStream *O, int64_t val); + +void printInt32Bang(SStream *O, int32_t val); + +void printInt32(SStream *O, int32_t val); + +void printUInt32Bang(SStream *O, uint32_t val); + +void printUInt32(SStream *O, uint32_t val); + +// print number in decimal mode +void printInt32BangDec(SStream *O, int32_t val); + +#endif diff --git a/white_patch_detect/capstone-master/TODO b/white_patch_detect/capstone-master/TODO new file mode 100644 index 0000000..e7117ee --- /dev/null +++ b/white_patch_detect/capstone-master/TODO @@ -0,0 +1,16 @@ +Issues to be solved in next versions + + +[Core] + +- X86 can already handle all the malware tricks we are aware of. If you find + any such instruction sequence that Capstone disassembles wrongly or fails + completely, please report. Fixing this issue is always the top priority of + our project. + +- More optimization for better performance. + + +[Bindings] + +- OCaml binding is working, but still needs to support the core API better. diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64AddressingModes.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64AddressingModes.h new file mode 100644 index 0000000..2d714e8 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64AddressingModes.h @@ -0,0 +1,225 @@ +//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the AArch64 addressing mode implementation stuff. +// +//===----------------------------------------------------------------------===// + +#ifndef CS_AARCH64_ADDRESSINGMODES_H +#define CS_AARCH64_ADDRESSINGMODES_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MathExtras.h" + +/// AArch64_AM - AArch64 Addressing Mode Stuff + +//===----------------------------------------------------------------------===// +// Shifts +// + +typedef enum AArch64_AM_ShiftExtendType { + AArch64_AM_InvalidShiftExtend = -1, + AArch64_AM_LSL = 0, + AArch64_AM_LSR, + AArch64_AM_ASR, + AArch64_AM_ROR, + AArch64_AM_MSL, + + AArch64_AM_UXTB, + AArch64_AM_UXTH, + AArch64_AM_UXTW, + AArch64_AM_UXTX, + + AArch64_AM_SXTB, + AArch64_AM_SXTH, + AArch64_AM_SXTW, + AArch64_AM_SXTX, +} AArch64_AM_ShiftExtendType; + +/// getShiftName - Get the string encoding for the shift type. +static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) +{ + switch (ST) { + default: return NULL; // never reach + case AArch64_AM_LSL: return "lsl"; + case AArch64_AM_LSR: return "lsr"; + case AArch64_AM_ASR: return "asr"; + case AArch64_AM_ROR: return "ror"; + case AArch64_AM_MSL: return "msl"; + case AArch64_AM_UXTB: return "uxtb"; + case AArch64_AM_UXTH: return "uxth"; + case AArch64_AM_UXTW: return "uxtw"; + case AArch64_AM_UXTX: return "uxtx"; + case AArch64_AM_SXTB: return "sxtb"; + case AArch64_AM_SXTH: return "sxth"; + case AArch64_AM_SXTW: return "sxtw"; + case AArch64_AM_SXTX: return "sxtx"; + } +} + +/// getShiftType - Extract the shift type. +static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) +{ + switch ((Imm >> 6) & 0x7) { + default: return AArch64_AM_InvalidShiftExtend; + case 0: return AArch64_AM_LSL; + case 1: return AArch64_AM_LSR; + case 2: return AArch64_AM_ASR; + case 3: return AArch64_AM_ROR; + case 4: return AArch64_AM_MSL; + } +} + +/// getShiftValue - Extract the shift value. +static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) +{ + return Imm & 0x3f; +} + +//===----------------------------------------------------------------------===// +// Extends +// + +/// getArithShiftValue - get the arithmetic shift value. +static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) +{ + return Imm & 0x7; +} + +/// getExtendType - Extract the extend type for operands of arithmetic ops. +static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) +{ + // assert((Imm & 0x7) == Imm && "invalid immediate!"); + switch (Imm) { + default: // llvm_unreachable("Compiler bug!"); + case 0: return AArch64_AM_UXTB; + case 1: return AArch64_AM_UXTH; + case 2: return AArch64_AM_UXTW; + case 3: return AArch64_AM_UXTX; + case 4: return AArch64_AM_SXTB; + case 5: return AArch64_AM_SXTH; + case 6: return AArch64_AM_SXTW; + case 7: return AArch64_AM_SXTX; + } +} + +static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm) +{ + return AArch64_AM_getExtendType((Imm >> 3) & 0x7); +} + +static inline uint64_t ror(uint64_t elt, unsigned size) +{ + return ((elt & 1) << (size-1)) | (elt >> 1); +} + +/// decodeLogicalImmediate - Decode a logical immediate value in the form +/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the +/// integer value it represents with regSize bits. +static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize) +{ + // Extract the N, imms, and immr fields. + unsigned N = (val >> 12) & 1; + unsigned immr = (val >> 6) & 0x3f; + unsigned imms = val & 0x3f; + unsigned i; + + // assert((regSize == 64 || N == 0) && "undefined logical immediate encoding"); + int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); + // assert(len >= 0 && "undefined logical immediate encoding"); + unsigned size = (1 << len); + unsigned R = immr & (size - 1); + unsigned S = imms & (size - 1); + // assert(S != size - 1 && "undefined logical immediate encoding"); + uint64_t pattern = (1ULL << (S + 1)) - 1; + for (i = 0; i < R; ++i) + pattern = ror(pattern, size); + + // Replicate the pattern to fill the regSize. + while (size != regSize) { + pattern |= (pattern << size); + size *= 2; + } + + return pattern; +} + +/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value +/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) +/// is a valid encoding for an integer value with regSize bits. +static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize) +{ + unsigned size; + unsigned S; + int len; + // Extract the N and imms fields needed for checking. + unsigned N = (val >> 12) & 1; + unsigned imms = val & 0x3f; + + if (regSize == 32 && N != 0) // undefined logical immediate encoding + return false; + len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); + if (len < 0) // undefined logical immediate encoding + return false; + size = (1 << len); + S = imms & (size - 1); + if (S == size - 1) // undefined logical immediate encoding + return false; + + return true; +} + +//===----------------------------------------------------------------------===// +// Floating-point Immediates +// +static inline float AArch64_AM_getFPImmFloat(unsigned Imm) +{ + // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; + + uint8_t Sign = (Imm >> 7) & 0x1; + uint8_t Exp = (Imm >> 4) & 0x7; + uint8_t Mantissa = Imm & 0xf; + + // 8-bit FP iEEEE Float Encoding + // abcd efgh aBbbbbbc defgh000 00000000 00000000 + // + // where B = NOT(b); + + FPUnion.I = 0; + FPUnion.I |= ((uint32_t)Sign) << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; + + return FPUnion.F; +} + +//===--------------------------------------------------------------------===// +// AdvSIMD Modified Immediates +//===--------------------------------------------------------------------===// + +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) +{ + static const uint32_t lookup[16] = { + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff + }; + return lookup[Imm & 0x0f] | ((uint64_t)lookup[Imm >> 4] << 32); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.c b/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.c new file mode 100644 index 0000000..4478f48 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.c @@ -0,0 +1,987 @@ +//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides basic encoding and assembly information for AArch64. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_ARM64 + +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#pragma warning(disable:4996) // disable MSVC's warning on strcpy() +#pragma warning(disable:28719) // disable MSVC's warning on strcpy() +#endif + +#include "../../utils.h" + +#include +#include + +#include "AArch64BaseInfo.h" + +const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid) +{ + unsigned i; + for (i = 0; i < N->NumPairs; ++i) { + if (N->Pairs[i].Value == Value) { + *Valid = true; + return N->Pairs[i].Name; + } + } + + *Valid = false; + return 0; +} + +// compare s1 with lower(s2) +// return true if s1 == lower(f2), and false otherwise +static bool compare_lower_str(const char *s1, const char *s2) +{ + bool res; + char *lower = cs_strdup(s2), *c; + for (c = lower; *c; c++) + *c = (char)tolower((int) *c); + + res = (strcmp(s1, lower) == 0); + cs_mem_free(lower); + + return res; +} + +uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid) +{ + unsigned i; + for (i = 0; i < N->NumPairs; ++i) { + if (compare_lower_str(N->Pairs[i].Name, Name)) { + *Valid = true; + return N->Pairs[i].Value; + } + } + + *Valid = false; + return (uint32_t)-1; +} + +bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value) +{ + return Value < N->TooBigImm; +} + +// return a string representing the number X +// NOTE: caller must free() the result itself to avoid memory leak +static char *utostr(uint64_t X, bool isNeg) +{ + char Buffer[22]; + char *BufPtr = Buffer+21; + char *result; + + Buffer[21] = '\0'; + if (X == 0) *--BufPtr = '0'; // Handle special case... + + while (X) { + *--BufPtr = X % 10 + '0'; + X /= 10; + } + + if (isNeg) *--BufPtr = '-'; // Add negative sign... + + result = cs_strdup(BufPtr); + return result; +} + +static const A64NamedImmMapper_Mapping SysRegPairs[] = { + {"pan", A64SysReg_PAN}, + {"uao", A64SysReg_UAO}, + {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1}, + {"osdtrtx_el1", A64SysReg_OSDTRTX_EL1}, + {"teecr32_el1", A64SysReg_TEECR32_EL1}, + {"mdccint_el1", A64SysReg_MDCCINT_EL1}, + {"mdscr_el1", A64SysReg_MDSCR_EL1}, + {"dbgdtr_el0", A64SysReg_DBGDTR_EL0}, + {"oseccr_el1", A64SysReg_OSECCR_EL1}, + {"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2}, + {"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1}, + {"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1}, + {"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1}, + {"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1}, + {"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1}, + {"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1}, + {"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1}, + {"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1}, + {"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1}, + {"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1}, + {"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1}, + {"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1}, + {"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1}, + {"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1}, + {"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1}, + {"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1}, + {"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1}, + {"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1}, + {"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1}, + {"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1}, + {"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1}, + {"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1}, + {"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1}, + {"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1}, + {"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1}, + {"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1}, + {"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1}, + {"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1}, + {"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1}, + {"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1}, + {"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1}, + {"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1}, + {"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1}, + {"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1}, + {"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1}, + {"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1}, + {"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1}, + {"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1}, + {"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1}, + {"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1}, + {"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1}, + {"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1}, + {"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1}, + {"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1}, + {"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1}, + {"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1}, + {"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1}, + {"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1}, + {"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1}, + {"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1}, + {"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1}, + {"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1}, + {"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1}, + {"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1}, + {"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1}, + {"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1}, + {"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1}, + {"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1}, + {"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1}, + {"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1}, + {"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1}, + {"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1}, + {"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1}, + {"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1}, + {"teehbr32_el1", A64SysReg_TEEHBR32_EL1}, + {"osdlr_el1", A64SysReg_OSDLR_EL1}, + {"dbgprcr_el1", A64SysReg_DBGPRCR_EL1}, + {"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1}, + {"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1}, + {"csselr_el1", A64SysReg_CSSELR_EL1}, + {"vpidr_el2", A64SysReg_VPIDR_EL2}, + {"vmpidr_el2", A64SysReg_VMPIDR_EL2}, + {"sctlr_el1", A64SysReg_SCTLR_EL1}, + {"sctlr_el12", A64SysReg_SCTLR_EL12}, + {"sctlr_el2", A64SysReg_SCTLR_EL2}, + {"sctlr_el3", A64SysReg_SCTLR_EL3}, + {"actlr_el1", A64SysReg_ACTLR_EL1}, + {"actlr_el2", A64SysReg_ACTLR_EL2}, + {"actlr_el3", A64SysReg_ACTLR_EL3}, + {"cpacr_el1", A64SysReg_CPACR_EL1}, + {"cpacr_el12", A64SysReg_CPACR_EL12}, + {"hcr_el2", A64SysReg_HCR_EL2}, + {"scr_el3", A64SysReg_SCR_EL3}, + {"mdcr_el2", A64SysReg_MDCR_EL2}, + {"sder32_el3", A64SysReg_SDER32_EL3}, + {"cptr_el2", A64SysReg_CPTR_EL2}, + {"cptr_el3", A64SysReg_CPTR_EL3}, + {"hstr_el2", A64SysReg_HSTR_EL2}, + {"hacr_el2", A64SysReg_HACR_EL2}, + {"mdcr_el3", A64SysReg_MDCR_EL3}, + {"ttbr0_el1", A64SysReg_TTBR0_EL1}, + {"ttbr0_el12", A64SysReg_TTBR0_EL12}, + {"ttbr0_el2", A64SysReg_TTBR0_EL2}, + {"ttbr0_el3", A64SysReg_TTBR0_EL3}, + {"ttbr1_el1", A64SysReg_TTBR1_EL1}, + {"ttbr1_el12", A64SysReg_TTBR1_EL12}, + {"ttbr1_el2", A64SysReg_TTBR1_EL2}, + {"tcr_el1", A64SysReg_TCR_EL1}, + {"tcr_el12", A64SysReg_TCR_EL12}, + {"tcr_el2", A64SysReg_TCR_EL2}, + {"tcr_el3", A64SysReg_TCR_EL3}, + {"vttbr_el2", A64SysReg_VTTBR_EL2}, + {"vtcr_el2", A64SysReg_VTCR_EL2}, + {"dacr32_el2", A64SysReg_DACR32_EL2}, + {"spsr_el1", A64SysReg_SPSR_EL1}, + {"spsr_el12", A64SysReg_SPSR_EL12}, + {"spsr_el2", A64SysReg_SPSR_EL2}, + {"spsr_el3", A64SysReg_SPSR_EL3}, + {"elr_el1", A64SysReg_ELR_EL1}, + {"elr_el12", A64SysReg_ELR_EL12}, + {"elr_el2", A64SysReg_ELR_EL2}, + {"elr_el3", A64SysReg_ELR_EL3}, + {"sp_el0", A64SysReg_SP_EL0}, + {"sp_el1", A64SysReg_SP_EL1}, + {"sp_el2", A64SysReg_SP_EL2}, + {"spsel", A64SysReg_SPSel}, + {"nzcv", A64SysReg_NZCV}, + {"daif", A64SysReg_DAIF}, + {"currentel", A64SysReg_CurrentEL}, + {"spsr_irq", A64SysReg_SPSR_irq}, + {"spsr_abt", A64SysReg_SPSR_abt}, + {"spsr_und", A64SysReg_SPSR_und}, + {"spsr_fiq", A64SysReg_SPSR_fiq}, + {"fpcr", A64SysReg_FPCR}, + {"fpsr", A64SysReg_FPSR}, + {"dspsr_el0", A64SysReg_DSPSR_EL0}, + {"dlr_el0", A64SysReg_DLR_EL0}, + {"ifsr32_el2", A64SysReg_IFSR32_EL2}, + {"afsr0_el1", A64SysReg_AFSR0_EL1}, + {"afsr0_el12", A64SysReg_AFSR0_EL12}, + {"afsr0_el2", A64SysReg_AFSR0_EL2}, + {"afsr0_el3", A64SysReg_AFSR0_EL3}, + {"afsr1_el1", A64SysReg_AFSR1_EL1}, + {"afsr1_el12", A64SysReg_AFSR1_EL12}, + {"afsr1_el2", A64SysReg_AFSR1_EL2}, + {"afsr1_el3", A64SysReg_AFSR1_EL3}, + {"esr_el1", A64SysReg_ESR_EL1}, + {"esr_el12", A64SysReg_ESR_EL12}, + {"esr_el2", A64SysReg_ESR_EL2}, + {"esr_el3", A64SysReg_ESR_EL3}, + {"fpexc32_el2", A64SysReg_FPEXC32_EL2}, + {"far_el1", A64SysReg_FAR_EL1}, + {"far_el12", A64SysReg_FAR_EL12}, + {"far_el2", A64SysReg_FAR_EL2}, + {"far_el3", A64SysReg_FAR_EL3}, + {"hpfar_el2", A64SysReg_HPFAR_EL2}, + {"par_el1", A64SysReg_PAR_EL1}, + {"pmcr_el0", A64SysReg_PMCR_EL0}, + {"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0}, + {"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0}, + {"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0}, + {"pmselr_el0", A64SysReg_PMSELR_EL0}, + {"pmccntr_el0", A64SysReg_PMCCNTR_EL0}, + {"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0}, + {"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0}, + {"pmuserenr_el0", A64SysReg_PMUSERENR_EL0}, + {"pmintenset_el1", A64SysReg_PMINTENSET_EL1}, + {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1}, + {"pmovsset_el0", A64SysReg_PMOVSSET_EL0}, + {"mair_el1", A64SysReg_MAIR_EL1}, + {"mair_el12", A64SysReg_MAIR_EL12}, + {"mair_el2", A64SysReg_MAIR_EL2}, + {"mair_el3", A64SysReg_MAIR_EL3}, + {"amair_el1", A64SysReg_AMAIR_EL1}, + {"amair_el12", A64SysReg_AMAIR_EL12}, + {"amair_el2", A64SysReg_AMAIR_EL2}, + {"amair_el3", A64SysReg_AMAIR_EL3}, + {"vbar_el1", A64SysReg_VBAR_EL1}, + {"vbar_el12", A64SysReg_VBAR_EL12}, + {"vbar_el2", A64SysReg_VBAR_EL2}, + {"vbar_el3", A64SysReg_VBAR_EL3}, + {"rmr_el1", A64SysReg_RMR_EL1}, + {"rmr_el2", A64SysReg_RMR_EL2}, + {"rmr_el3", A64SysReg_RMR_EL3}, + {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1}, + {"contextidr_el12", A64SysReg_CONTEXTIDR_EL12}, + {"contextidr_el2", A64SysReg_CONTEXTIDR_EL2}, + {"tpidr_el0", A64SysReg_TPIDR_EL0}, + {"tpidr_el2", A64SysReg_TPIDR_EL2}, + {"tpidr_el3", A64SysReg_TPIDR_EL3}, + {"tpidrro_el0", A64SysReg_TPIDRRO_EL0}, + {"tpidr_el1", A64SysReg_TPIDR_EL1}, + {"cntfrq_el0", A64SysReg_CNTFRQ_EL0}, + {"cntvoff_el2", A64SysReg_CNTVOFF_EL2}, + {"cntkctl_el1", A64SysReg_CNTKCTL_EL1}, + {"cntkctl_el12", A64SysReg_CNTKCTL_EL12}, + {"cnthctl_el2", A64SysReg_CNTHCTL_EL2}, + {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0}, + {"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02}, + {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2}, + {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1}, + {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0}, + {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2}, + {"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2}, + {"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2}, + {"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2}, + {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1}, + {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0}, + {"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02}, + {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2}, + {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1}, + {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0}, + {"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02}, + {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0}, + {"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02}, + {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0}, + {"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02}, + {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0}, + {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0}, + {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0}, + {"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0}, + {"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0}, + {"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0}, + {"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0}, + {"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0}, + {"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0}, + {"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0}, + {"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0}, + {"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0}, + {"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0}, + {"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0}, + {"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0}, + {"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0}, + {"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0}, + {"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0}, + {"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0}, + {"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0}, + {"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0}, + {"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0}, + {"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0}, + {"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0}, + {"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0}, + {"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0}, + {"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0}, + {"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0}, + {"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0}, + {"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0}, + {"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0}, + {"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0}, + {"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0}, + {"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0}, + {"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0}, + {"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0}, + {"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0}, + {"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0}, + {"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0}, + {"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0}, + {"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0}, + {"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0}, + {"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0}, + {"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0}, + {"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0}, + {"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0}, + {"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0}, + {"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0}, + {"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0}, + {"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0}, + {"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0}, + {"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0}, + {"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0}, + {"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0}, + {"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0}, + {"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0}, + {"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0}, + {"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0}, + {"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0}, + {"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0}, + {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0}, + {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0}, + {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0}, + {"lorc_el1", A64SysReg_LORC_EL1}, + {"lorea_el1", A64SysReg_LOREA_EL1}, + {"lorn_el1", A64SysReg_LORN_EL1}, + {"lorsa_el1", A64SysReg_LORSA_EL1}, + + // Trace registers + {"trcprgctlr", A64SysReg_TRCPRGCTLR}, + {"trcprocselr", A64SysReg_TRCPROCSELR}, + {"trcconfigr", A64SysReg_TRCCONFIGR}, + {"trcauxctlr", A64SysReg_TRCAUXCTLR}, + {"trceventctl0r", A64SysReg_TRCEVENTCTL0R}, + {"trceventctl1r", A64SysReg_TRCEVENTCTL1R}, + {"trcstallctlr", A64SysReg_TRCSTALLCTLR}, + {"trctsctlr", A64SysReg_TRCTSCTLR}, + {"trcsyncpr", A64SysReg_TRCSYNCPR}, + {"trcccctlr", A64SysReg_TRCCCCTLR}, + {"trcbbctlr", A64SysReg_TRCBBCTLR}, + {"trctraceidr", A64SysReg_TRCTRACEIDR}, + {"trcqctlr", A64SysReg_TRCQCTLR}, + {"trcvictlr", A64SysReg_TRCVICTLR}, + {"trcviiectlr", A64SysReg_TRCVIIECTLR}, + {"trcvissctlr", A64SysReg_TRCVISSCTLR}, + {"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR}, + {"trcvdctlr", A64SysReg_TRCVDCTLR}, + {"trcvdsacctlr", A64SysReg_TRCVDSACCTLR}, + {"trcvdarcctlr", A64SysReg_TRCVDARCCTLR}, + {"trcseqevr0", A64SysReg_TRCSEQEVR0}, + {"trcseqevr1", A64SysReg_TRCSEQEVR1}, + {"trcseqevr2", A64SysReg_TRCSEQEVR2}, + {"trcseqrstevr", A64SysReg_TRCSEQRSTEVR}, + {"trcseqstr", A64SysReg_TRCSEQSTR}, + {"trcextinselr", A64SysReg_TRCEXTINSELR}, + {"trccntrldvr0", A64SysReg_TRCCNTRLDVR0}, + {"trccntrldvr1", A64SysReg_TRCCNTRLDVR1}, + {"trccntrldvr2", A64SysReg_TRCCNTRLDVR2}, + {"trccntrldvr3", A64SysReg_TRCCNTRLDVR3}, + {"trccntctlr0", A64SysReg_TRCCNTCTLR0}, + {"trccntctlr1", A64SysReg_TRCCNTCTLR1}, + {"trccntctlr2", A64SysReg_TRCCNTCTLR2}, + {"trccntctlr3", A64SysReg_TRCCNTCTLR3}, + {"trccntvr0", A64SysReg_TRCCNTVR0}, + {"trccntvr1", A64SysReg_TRCCNTVR1}, + {"trccntvr2", A64SysReg_TRCCNTVR2}, + {"trccntvr3", A64SysReg_TRCCNTVR3}, + {"trcimspec0", A64SysReg_TRCIMSPEC0}, + {"trcimspec1", A64SysReg_TRCIMSPEC1}, + {"trcimspec2", A64SysReg_TRCIMSPEC2}, + {"trcimspec3", A64SysReg_TRCIMSPEC3}, + {"trcimspec4", A64SysReg_TRCIMSPEC4}, + {"trcimspec5", A64SysReg_TRCIMSPEC5}, + {"trcimspec6", A64SysReg_TRCIMSPEC6}, + {"trcimspec7", A64SysReg_TRCIMSPEC7}, + {"trcrsctlr2", A64SysReg_TRCRSCTLR2}, + {"trcrsctlr3", A64SysReg_TRCRSCTLR3}, + {"trcrsctlr4", A64SysReg_TRCRSCTLR4}, + {"trcrsctlr5", A64SysReg_TRCRSCTLR5}, + {"trcrsctlr6", A64SysReg_TRCRSCTLR6}, + {"trcrsctlr7", A64SysReg_TRCRSCTLR7}, + {"trcrsctlr8", A64SysReg_TRCRSCTLR8}, + {"trcrsctlr9", A64SysReg_TRCRSCTLR9}, + {"trcrsctlr10", A64SysReg_TRCRSCTLR10}, + {"trcrsctlr11", A64SysReg_TRCRSCTLR11}, + {"trcrsctlr12", A64SysReg_TRCRSCTLR12}, + {"trcrsctlr13", A64SysReg_TRCRSCTLR13}, + {"trcrsctlr14", A64SysReg_TRCRSCTLR14}, + {"trcrsctlr15", A64SysReg_TRCRSCTLR15}, + {"trcrsctlr16", A64SysReg_TRCRSCTLR16}, + {"trcrsctlr17", A64SysReg_TRCRSCTLR17}, + {"trcrsctlr18", A64SysReg_TRCRSCTLR18}, + {"trcrsctlr19", A64SysReg_TRCRSCTLR19}, + {"trcrsctlr20", A64SysReg_TRCRSCTLR20}, + {"trcrsctlr21", A64SysReg_TRCRSCTLR21}, + {"trcrsctlr22", A64SysReg_TRCRSCTLR22}, + {"trcrsctlr23", A64SysReg_TRCRSCTLR23}, + {"trcrsctlr24", A64SysReg_TRCRSCTLR24}, + {"trcrsctlr25", A64SysReg_TRCRSCTLR25}, + {"trcrsctlr26", A64SysReg_TRCRSCTLR26}, + {"trcrsctlr27", A64SysReg_TRCRSCTLR27}, + {"trcrsctlr28", A64SysReg_TRCRSCTLR28}, + {"trcrsctlr29", A64SysReg_TRCRSCTLR29}, + {"trcrsctlr30", A64SysReg_TRCRSCTLR30}, + {"trcrsctlr31", A64SysReg_TRCRSCTLR31}, + {"trcssccr0", A64SysReg_TRCSSCCR0}, + {"trcssccr1", A64SysReg_TRCSSCCR1}, + {"trcssccr2", A64SysReg_TRCSSCCR2}, + {"trcssccr3", A64SysReg_TRCSSCCR3}, + {"trcssccr4", A64SysReg_TRCSSCCR4}, + {"trcssccr5", A64SysReg_TRCSSCCR5}, + {"trcssccr6", A64SysReg_TRCSSCCR6}, + {"trcssccr7", A64SysReg_TRCSSCCR7}, + {"trcsscsr0", A64SysReg_TRCSSCSR0}, + {"trcsscsr1", A64SysReg_TRCSSCSR1}, + {"trcsscsr2", A64SysReg_TRCSSCSR2}, + {"trcsscsr3", A64SysReg_TRCSSCSR3}, + {"trcsscsr4", A64SysReg_TRCSSCSR4}, + {"trcsscsr5", A64SysReg_TRCSSCSR5}, + {"trcsscsr6", A64SysReg_TRCSSCSR6}, + {"trcsscsr7", A64SysReg_TRCSSCSR7}, + {"trcsspcicr0", A64SysReg_TRCSSPCICR0}, + {"trcsspcicr1", A64SysReg_TRCSSPCICR1}, + {"trcsspcicr2", A64SysReg_TRCSSPCICR2}, + {"trcsspcicr3", A64SysReg_TRCSSPCICR3}, + {"trcsspcicr4", A64SysReg_TRCSSPCICR4}, + {"trcsspcicr5", A64SysReg_TRCSSPCICR5}, + {"trcsspcicr6", A64SysReg_TRCSSPCICR6}, + {"trcsspcicr7", A64SysReg_TRCSSPCICR7}, + {"trcpdcr", A64SysReg_TRCPDCR}, + {"trcacvr0", A64SysReg_TRCACVR0}, + {"trcacvr1", A64SysReg_TRCACVR1}, + {"trcacvr2", A64SysReg_TRCACVR2}, + {"trcacvr3", A64SysReg_TRCACVR3}, + {"trcacvr4", A64SysReg_TRCACVR4}, + {"trcacvr5", A64SysReg_TRCACVR5}, + {"trcacvr6", A64SysReg_TRCACVR6}, + {"trcacvr7", A64SysReg_TRCACVR7}, + {"trcacvr8", A64SysReg_TRCACVR8}, + {"trcacvr9", A64SysReg_TRCACVR9}, + {"trcacvr10", A64SysReg_TRCACVR10}, + {"trcacvr11", A64SysReg_TRCACVR11}, + {"trcacvr12", A64SysReg_TRCACVR12}, + {"trcacvr13", A64SysReg_TRCACVR13}, + {"trcacvr14", A64SysReg_TRCACVR14}, + {"trcacvr15", A64SysReg_TRCACVR15}, + {"trcacatr0", A64SysReg_TRCACATR0}, + {"trcacatr1", A64SysReg_TRCACATR1}, + {"trcacatr2", A64SysReg_TRCACATR2}, + {"trcacatr3", A64SysReg_TRCACATR3}, + {"trcacatr4", A64SysReg_TRCACATR4}, + {"trcacatr5", A64SysReg_TRCACATR5}, + {"trcacatr6", A64SysReg_TRCACATR6}, + {"trcacatr7", A64SysReg_TRCACATR7}, + {"trcacatr8", A64SysReg_TRCACATR8}, + {"trcacatr9", A64SysReg_TRCACATR9}, + {"trcacatr10", A64SysReg_TRCACATR10}, + {"trcacatr11", A64SysReg_TRCACATR11}, + {"trcacatr12", A64SysReg_TRCACATR12}, + {"trcacatr13", A64SysReg_TRCACATR13}, + {"trcacatr14", A64SysReg_TRCACATR14}, + {"trcacatr15", A64SysReg_TRCACATR15}, + {"trcdvcvr0", A64SysReg_TRCDVCVR0}, + {"trcdvcvr1", A64SysReg_TRCDVCVR1}, + {"trcdvcvr2", A64SysReg_TRCDVCVR2}, + {"trcdvcvr3", A64SysReg_TRCDVCVR3}, + {"trcdvcvr4", A64SysReg_TRCDVCVR4}, + {"trcdvcvr5", A64SysReg_TRCDVCVR5}, + {"trcdvcvr6", A64SysReg_TRCDVCVR6}, + {"trcdvcvr7", A64SysReg_TRCDVCVR7}, + {"trcdvcmr0", A64SysReg_TRCDVCMR0}, + {"trcdvcmr1", A64SysReg_TRCDVCMR1}, + {"trcdvcmr2", A64SysReg_TRCDVCMR2}, + {"trcdvcmr3", A64SysReg_TRCDVCMR3}, + {"trcdvcmr4", A64SysReg_TRCDVCMR4}, + {"trcdvcmr5", A64SysReg_TRCDVCMR5}, + {"trcdvcmr6", A64SysReg_TRCDVCMR6}, + {"trcdvcmr7", A64SysReg_TRCDVCMR7}, + {"trccidcvr0", A64SysReg_TRCCIDCVR0}, + {"trccidcvr1", A64SysReg_TRCCIDCVR1}, + {"trccidcvr2", A64SysReg_TRCCIDCVR2}, + {"trccidcvr3", A64SysReg_TRCCIDCVR3}, + {"trccidcvr4", A64SysReg_TRCCIDCVR4}, + {"trccidcvr5", A64SysReg_TRCCIDCVR5}, + {"trccidcvr6", A64SysReg_TRCCIDCVR6}, + {"trccidcvr7", A64SysReg_TRCCIDCVR7}, + {"trcvmidcvr0", A64SysReg_TRCVMIDCVR0}, + {"trcvmidcvr1", A64SysReg_TRCVMIDCVR1}, + {"trcvmidcvr2", A64SysReg_TRCVMIDCVR2}, + {"trcvmidcvr3", A64SysReg_TRCVMIDCVR3}, + {"trcvmidcvr4", A64SysReg_TRCVMIDCVR4}, + {"trcvmidcvr5", A64SysReg_TRCVMIDCVR5}, + {"trcvmidcvr6", A64SysReg_TRCVMIDCVR6}, + {"trcvmidcvr7", A64SysReg_TRCVMIDCVR7}, + {"trccidcctlr0", A64SysReg_TRCCIDCCTLR0}, + {"trccidcctlr1", A64SysReg_TRCCIDCCTLR1}, + {"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0}, + {"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1}, + {"trcitctrl", A64SysReg_TRCITCTRL}, + {"trcclaimset", A64SysReg_TRCCLAIMSET}, + {"trcclaimclr", A64SysReg_TRCCLAIMCLR}, + + // GICv3 registers + {"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1}, + {"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1}, + {"icc_pmr_el1", A64SysReg_ICC_PMR_EL1}, + {"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1}, + {"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3}, + {"icc_sre_el1", A64SysReg_ICC_SRE_EL1}, + {"icc_sre_el2", A64SysReg_ICC_SRE_EL2}, + {"icc_sre_el3", A64SysReg_ICC_SRE_EL3}, + {"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1}, + {"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1}, + {"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3}, + {"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1}, + {"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1}, + {"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1}, + {"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1}, + {"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1}, + {"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1}, + {"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1}, + {"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1}, + {"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1}, + {"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2}, + {"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2}, + {"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2}, + {"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2}, + {"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2}, + {"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2}, + {"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2}, + {"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2}, + {"ich_hcr_el2", A64SysReg_ICH_HCR_EL2}, + {"ich_misr_el2", A64SysReg_ICH_MISR_EL2}, + {"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2}, + {"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2}, + {"ich_lr0_el2", A64SysReg_ICH_LR0_EL2}, + {"ich_lr1_el2", A64SysReg_ICH_LR1_EL2}, + {"ich_lr2_el2", A64SysReg_ICH_LR2_EL2}, + {"ich_lr3_el2", A64SysReg_ICH_LR3_EL2}, + {"ich_lr4_el2", A64SysReg_ICH_LR4_EL2}, + {"ich_lr5_el2", A64SysReg_ICH_LR5_EL2}, + {"ich_lr6_el2", A64SysReg_ICH_LR6_EL2}, + {"ich_lr7_el2", A64SysReg_ICH_LR7_EL2}, + {"ich_lr8_el2", A64SysReg_ICH_LR8_EL2}, + {"ich_lr9_el2", A64SysReg_ICH_LR9_EL2}, + {"ich_lr10_el2", A64SysReg_ICH_LR10_EL2}, + {"ich_lr11_el2", A64SysReg_ICH_LR11_EL2}, + {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2}, + {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2}, + {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2}, + {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}, + + // Statistical profiling registers + {"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1}, + {"pmbptr_el1", A64SysReg_PMBPTR_EL1}, + {"pmbsr_el1", A64SysReg_PMBSR_EL1}, + {"pmscr_el1", A64SysReg_PMSCR_EL1}, + {"pmscr_el12", A64SysReg_PMSCR_EL12}, + {"pmscr_el2", A64SysReg_PMSCR_EL2}, + {"pmsicr_el1", A64SysReg_PMSICR_EL1}, + {"pmsirr_el1", A64SysReg_PMSIRR_EL1}, + {"pmsfcr_el1", A64SysReg_PMSFCR_EL1}, + {"pmsevfr_el1", A64SysReg_PMSEVFR_EL1}, + {"pmslatfr_el1", A64SysReg_PMSLATFR_EL1} +}; + +static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = { + {"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3} +}; + +// result must be a big enough buffer: 128 bytes is more than enough +void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result) +{ + int dummy; + uint32_t Op0, Op1, CRn, CRm, Op2; + char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S; + unsigned i; + + // First search the registers shared by all + for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) { + if (SysRegPairs[i].Value == Bits) { + strcpy(result, SysRegPairs[i].Name); + return; + } + } + + // Next search for target specific registers + // if (FeatureBits & AArch64_ProcCyclone) { + if (true) { + for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) { + if (CycloneSysRegPairs[i].Value == Bits) { + strcpy(result, CycloneSysRegPairs[i].Name); + return; + } + } + } + + // Now try the instruction-specific registers (either read-only or + // write-only). + for (i = 0; i < S->NumInstPairs; ++i) { + if (S->InstPairs[i].Value == Bits) { + strcpy(result, S->InstPairs[i].Name); + return; + } + } + + Op0 = (Bits >> 14) & 0x3; + Op1 = (Bits >> 11) & 0x7; + CRn = (Bits >> 7) & 0xf; + CRm = (Bits >> 3) & 0xf; + Op2 = Bits & 0x7; + + Op0S = utostr(Op0, false); + Op1S = utostr(Op1, false); + CRnS = utostr(CRn, false); + CRmS = utostr(CRm, false); + Op2S = utostr(Op2, false); + + //printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S); + dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S); + (void)dummy; + + cs_mem_free(Op0S); + cs_mem_free(Op1S); + cs_mem_free(CRnS); + cs_mem_free(CRmS); + cs_mem_free(Op2S); +} + +static const A64NamedImmMapper_Mapping TLBIPairs[] = { + {"ipas2e1is", A64TLBI_IPAS2E1IS}, + {"ipas2le1is", A64TLBI_IPAS2LE1IS}, + {"vmalle1is", A64TLBI_VMALLE1IS}, + {"alle2is", A64TLBI_ALLE2IS}, + {"alle3is", A64TLBI_ALLE3IS}, + {"vae1is", A64TLBI_VAE1IS}, + {"vae2is", A64TLBI_VAE2IS}, + {"vae3is", A64TLBI_VAE3IS}, + {"aside1is", A64TLBI_ASIDE1IS}, + {"vaae1is", A64TLBI_VAAE1IS}, + {"alle1is", A64TLBI_ALLE1IS}, + {"vale1is", A64TLBI_VALE1IS}, + {"vale2is", A64TLBI_VALE2IS}, + {"vale3is", A64TLBI_VALE3IS}, + {"vmalls12e1is", A64TLBI_VMALLS12E1IS}, + {"vaale1is", A64TLBI_VAALE1IS}, + {"ipas2e1", A64TLBI_IPAS2E1}, + {"ipas2le1", A64TLBI_IPAS2LE1}, + {"vmalle1", A64TLBI_VMALLE1}, + {"alle2", A64TLBI_ALLE2}, + {"alle3", A64TLBI_ALLE3}, + {"vae1", A64TLBI_VAE1}, + {"vae2", A64TLBI_VAE2}, + {"vae3", A64TLBI_VAE3}, + {"aside1", A64TLBI_ASIDE1}, + {"vaae1", A64TLBI_VAAE1}, + {"alle1", A64TLBI_ALLE1}, + {"vale1", A64TLBI_VALE1}, + {"vale2", A64TLBI_VALE2}, + {"vale3", A64TLBI_VALE3}, + {"vmalls12e1", A64TLBI_VMALLS12E1}, + {"vaale1", A64TLBI_VAALE1} +}; + +const A64NamedImmMapper A64TLBI_TLBIMapper = { + TLBIPairs, + ARR_SIZE(TLBIPairs), + 0, +}; + +static const A64NamedImmMapper_Mapping ATPairs[] = { + {"s1e1r", A64AT_S1E1R}, + {"s1e2r", A64AT_S1E2R}, + {"s1e3r", A64AT_S1E3R}, + {"s1e1w", A64AT_S1E1W}, + {"s1e2w", A64AT_S1E2W}, + {"s1e3w", A64AT_S1E3W}, + {"s1e0r", A64AT_S1E0R}, + {"s1e0w", A64AT_S1E0W}, + {"s12e1r", A64AT_S12E1R}, + {"s12e1w", A64AT_S12E1W}, + {"s12e0r", A64AT_S12E0R}, + {"s12e0w", A64AT_S12E0W} +}; + +const A64NamedImmMapper A64AT_ATMapper = { + ATPairs, + ARR_SIZE(ATPairs), + 0, +}; + +static const A64NamedImmMapper_Mapping DBarrierPairs[] = { + {"oshld", A64DB_OSHLD}, + {"oshst", A64DB_OSHST}, + {"osh", A64DB_OSH}, + {"nshld", A64DB_NSHLD}, + {"nshst", A64DB_NSHST}, + {"nsh", A64DB_NSH}, + {"ishld", A64DB_ISHLD}, + {"ishst", A64DB_ISHST}, + {"ish", A64DB_ISH}, + {"ld", A64DB_LD}, + {"st", A64DB_ST}, + {"sy", A64DB_SY} +}; + +const A64NamedImmMapper A64DB_DBarrierMapper = { + DBarrierPairs, + ARR_SIZE(DBarrierPairs), + 16, +}; + +static const A64NamedImmMapper_Mapping DCPairs[] = { + {"zva", A64DC_ZVA}, + {"ivac", A64DC_IVAC}, + {"isw", A64DC_ISW}, + {"cvac", A64DC_CVAC}, + {"csw", A64DC_CSW}, + {"cvau", A64DC_CVAU}, + {"civac", A64DC_CIVAC}, + {"cisw", A64DC_CISW} +}; + +const A64NamedImmMapper A64DC_DCMapper = { + DCPairs, + ARR_SIZE(DCPairs), + 0, +}; + +static const A64NamedImmMapper_Mapping ICPairs[] = { + {"ialluis", A64IC_IALLUIS}, + {"iallu", A64IC_IALLU}, + {"ivau", A64IC_IVAU} +}; + +const A64NamedImmMapper A64IC_ICMapper = { + ICPairs, + ARR_SIZE(ICPairs), + 0, +}; + +static const A64NamedImmMapper_Mapping ISBPairs[] = { + {"sy", A64DB_SY}, +}; + +const A64NamedImmMapper A64ISB_ISBMapper = { + ISBPairs, + ARR_SIZE(ISBPairs), + 16, +}; + +static const A64NamedImmMapper_Mapping PRFMPairs[] = { + {"pldl1keep", A64PRFM_PLDL1KEEP}, + {"pldl1strm", A64PRFM_PLDL1STRM}, + {"pldl2keep", A64PRFM_PLDL2KEEP}, + {"pldl2strm", A64PRFM_PLDL2STRM}, + {"pldl3keep", A64PRFM_PLDL3KEEP}, + {"pldl3strm", A64PRFM_PLDL3STRM}, + {"plil1keep", A64PRFM_PLIL1KEEP}, + {"plil1strm", A64PRFM_PLIL1STRM}, + {"plil2keep", A64PRFM_PLIL2KEEP}, + {"plil2strm", A64PRFM_PLIL2STRM}, + {"plil3keep", A64PRFM_PLIL3KEEP}, + {"plil3strm", A64PRFM_PLIL3STRM}, + {"pstl1keep", A64PRFM_PSTL1KEEP}, + {"pstl1strm", A64PRFM_PSTL1STRM}, + {"pstl2keep", A64PRFM_PSTL2KEEP}, + {"pstl2strm", A64PRFM_PSTL2STRM}, + {"pstl3keep", A64PRFM_PSTL3KEEP}, + {"pstl3strm", A64PRFM_PSTL3STRM} +}; + +const A64NamedImmMapper A64PRFM_PRFMMapper = { + PRFMPairs, + ARR_SIZE(PRFMPairs), + 32, +}; + +static const A64NamedImmMapper_Mapping PStatePairs[] = { + {"spsel", A64PState_SPSel}, + {"daifset", A64PState_DAIFSet}, + {"daifclr", A64PState_DAIFClr}, + {"pan", A64PState_PAN}, + {"uao", A64PState_UAO} +}; + +const A64NamedImmMapper A64PState_PStateMapper = { + PStatePairs, + ARR_SIZE(PStatePairs), + 0, +}; + +static const A64NamedImmMapper_Mapping MRSPairs[] = { + {"mdccsr_el0", A64SysReg_MDCCSR_EL0}, + {"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0}, + {"mdrar_el1", A64SysReg_MDRAR_EL1}, + {"oslsr_el1", A64SysReg_OSLSR_EL1}, + {"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1}, + {"pmceid0_el0", A64SysReg_PMCEID0_EL0}, + {"pmceid1_el0", A64SysReg_PMCEID1_EL0}, + {"midr_el1", A64SysReg_MIDR_EL1}, + {"ccsidr_el1", A64SysReg_CCSIDR_EL1}, + {"clidr_el1", A64SysReg_CLIDR_EL1}, + {"ctr_el0", A64SysReg_CTR_EL0}, + {"mpidr_el1", A64SysReg_MPIDR_EL1}, + {"revidr_el1", A64SysReg_REVIDR_EL1}, + {"aidr_el1", A64SysReg_AIDR_EL1}, + {"dczid_el0", A64SysReg_DCZID_EL0}, + {"id_pfr0_el1", A64SysReg_ID_PFR0_EL1}, + {"id_pfr1_el1", A64SysReg_ID_PFR1_EL1}, + {"id_dfr0_el1", A64SysReg_ID_DFR0_EL1}, + {"id_afr0_el1", A64SysReg_ID_AFR0_EL1}, + {"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1}, + {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1}, + {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1}, + {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1}, + {"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1}, + {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1}, + {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1}, + {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1}, + {"id_isar3_el1", A64SysReg_ID_ISAR3_EL1}, + {"id_isar4_el1", A64SysReg_ID_ISAR4_EL1}, + {"id_isar5_el1", A64SysReg_ID_ISAR5_EL1}, + {"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1}, + {"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1}, + {"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1}, + {"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1}, + {"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1}, + {"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1}, + {"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1}, + {"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1}, + {"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1}, + {"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1}, + {"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1}, + {"lorid_el1", A64SysReg_LORID_EL1}, + {"mvfr0_el1", A64SysReg_MVFR0_EL1}, + {"mvfr1_el1", A64SysReg_MVFR1_EL1}, + {"mvfr2_el1", A64SysReg_MVFR2_EL1}, + {"rvbar_el1", A64SysReg_RVBAR_EL1}, + {"rvbar_el2", A64SysReg_RVBAR_EL2}, + {"rvbar_el3", A64SysReg_RVBAR_EL3}, + {"isr_el1", A64SysReg_ISR_EL1}, + {"cntpct_el0", A64SysReg_CNTPCT_EL0}, + {"cntvct_el0", A64SysReg_CNTVCT_EL0}, + + // Trace registers + {"trcstatr", A64SysReg_TRCSTATR}, + {"trcidr8", A64SysReg_TRCIDR8}, + {"trcidr9", A64SysReg_TRCIDR9}, + {"trcidr10", A64SysReg_TRCIDR10}, + {"trcidr11", A64SysReg_TRCIDR11}, + {"trcidr12", A64SysReg_TRCIDR12}, + {"trcidr13", A64SysReg_TRCIDR13}, + {"trcidr0", A64SysReg_TRCIDR0}, + {"trcidr1", A64SysReg_TRCIDR1}, + {"trcidr2", A64SysReg_TRCIDR2}, + {"trcidr3", A64SysReg_TRCIDR3}, + {"trcidr4", A64SysReg_TRCIDR4}, + {"trcidr5", A64SysReg_TRCIDR5}, + {"trcidr6", A64SysReg_TRCIDR6}, + {"trcidr7", A64SysReg_TRCIDR7}, + {"trcoslsr", A64SysReg_TRCOSLSR}, + {"trcpdsr", A64SysReg_TRCPDSR}, + {"trcdevaff0", A64SysReg_TRCDEVAFF0}, + {"trcdevaff1", A64SysReg_TRCDEVAFF1}, + {"trclsr", A64SysReg_TRCLSR}, + {"trcauthstatus", A64SysReg_TRCAUTHSTATUS}, + {"trcdevarch", A64SysReg_TRCDEVARCH}, + {"trcdevid", A64SysReg_TRCDEVID}, + {"trcdevtype", A64SysReg_TRCDEVTYPE}, + {"trcpidr4", A64SysReg_TRCPIDR4}, + {"trcpidr5", A64SysReg_TRCPIDR5}, + {"trcpidr6", A64SysReg_TRCPIDR6}, + {"trcpidr7", A64SysReg_TRCPIDR7}, + {"trcpidr0", A64SysReg_TRCPIDR0}, + {"trcpidr1", A64SysReg_TRCPIDR1}, + {"trcpidr2", A64SysReg_TRCPIDR2}, + {"trcpidr3", A64SysReg_TRCPIDR3}, + {"trccidr0", A64SysReg_TRCCIDR0}, + {"trccidr1", A64SysReg_TRCCIDR1}, + {"trccidr2", A64SysReg_TRCCIDR2}, + {"trccidr3", A64SysReg_TRCCIDR3}, + + // GICv3 registers + {"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1}, + {"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1}, + {"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1}, + {"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1}, + {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1}, + {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2}, + {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2}, + {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}, + + // Statistical profiling registers + {"pmsidr_el1", A64SysReg_PMSIDR_EL1}, + {"pmbidr_el1", A64SysReg_PMBIDR_EL1} +}; + +const A64SysRegMapper AArch64_MRSMapper = { + NULL, + MRSPairs, + ARR_SIZE(MRSPairs), +}; + +static const A64NamedImmMapper_Mapping MSRPairs[] = { + {"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0}, + {"oslar_el1", A64SysReg_OSLAR_EL1}, + {"pmswinc_el0", A64SysReg_PMSWINC_EL0}, + + // Trace registers + {"trcoslar", A64SysReg_TRCOSLAR}, + {"trclar", A64SysReg_TRCLAR}, + + // GICv3 registers + {"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1}, + {"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1}, + {"icc_dir_el1", A64SysReg_ICC_DIR_EL1}, + {"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1}, + {"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1}, + {"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1} +}; + +const A64SysRegMapper AArch64_MSRMapper = { + NULL, + MSRPairs, + ARR_SIZE(MSRPairs), +}; + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.h new file mode 100644 index 0000000..3c082a1 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64BaseInfo.h @@ -0,0 +1,1010 @@ +//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the AArch64 target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_AARCH64_BASEINFO_H +#define CS_LLVM_AARCH64_BASEINFO_H + +#include +#include + +#ifndef __cplusplus +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#define inline /* inline */ +#endif +#endif + +inline static unsigned getWRegFromXReg(unsigned Reg) +{ + switch (Reg) { + case ARM64_REG_X0: return ARM64_REG_W0; + case ARM64_REG_X1: return ARM64_REG_W1; + case ARM64_REG_X2: return ARM64_REG_W2; + case ARM64_REG_X3: return ARM64_REG_W3; + case ARM64_REG_X4: return ARM64_REG_W4; + case ARM64_REG_X5: return ARM64_REG_W5; + case ARM64_REG_X6: return ARM64_REG_W6; + case ARM64_REG_X7: return ARM64_REG_W7; + case ARM64_REG_X8: return ARM64_REG_W8; + case ARM64_REG_X9: return ARM64_REG_W9; + case ARM64_REG_X10: return ARM64_REG_W10; + case ARM64_REG_X11: return ARM64_REG_W11; + case ARM64_REG_X12: return ARM64_REG_W12; + case ARM64_REG_X13: return ARM64_REG_W13; + case ARM64_REG_X14: return ARM64_REG_W14; + case ARM64_REG_X15: return ARM64_REG_W15; + case ARM64_REG_X16: return ARM64_REG_W16; + case ARM64_REG_X17: return ARM64_REG_W17; + case ARM64_REG_X18: return ARM64_REG_W18; + case ARM64_REG_X19: return ARM64_REG_W19; + case ARM64_REG_X20: return ARM64_REG_W20; + case ARM64_REG_X21: return ARM64_REG_W21; + case ARM64_REG_X22: return ARM64_REG_W22; + case ARM64_REG_X23: return ARM64_REG_W23; + case ARM64_REG_X24: return ARM64_REG_W24; + case ARM64_REG_X25: return ARM64_REG_W25; + case ARM64_REG_X26: return ARM64_REG_W26; + case ARM64_REG_X27: return ARM64_REG_W27; + case ARM64_REG_X28: return ARM64_REG_W28; + case ARM64_REG_FP: return ARM64_REG_W29; + case ARM64_REG_LR: return ARM64_REG_W30; + case ARM64_REG_SP: return ARM64_REG_WSP; + case ARM64_REG_XZR: return ARM64_REG_WZR; + } + + // For anything else, return it unchanged. + return Reg; +} + +// // Enums corresponding to AArch64 condition codes +// The CondCodes constants map directly to the 4-bit encoding of the +// condition field for predicated instructions. +typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point) + A64CC_EQ = 0, // Equal Equal + A64CC_NE, // Not equal Not equal, or unordered + A64CC_HS, // Unsigned higher or same >, ==, or unordered + A64CC_LO, // Unsigned lower or same Less than + A64CC_MI, // Minus, negative Less than + A64CC_PL, // Plus, positive or zero >, ==, or unordered + A64CC_VS, // Overflow Unordered + A64CC_VC, // No overflow Ordered + A64CC_HI, // Unsigned higher Greater than, or unordered + A64CC_LS, // Unsigned lower or same Less than or equal + A64CC_GE, // Greater than or equal Greater than or equal + A64CC_LT, // Less than Less than, or unordered + A64CC_GT, // Signed greater than Greater than + A64CC_LE, // Signed less than or equal <, ==, or unordered + A64CC_AL, // Always (unconditional) Always (unconditional) + A64CC_NV, // Always (unconditional) Always (unconditional) + // Note the NV exists purely to disassemble 0b1111. Execution is "always". + A64CC_Invalid +} A64CC_CondCode; + +inline static const char *getCondCodeName(A64CC_CondCode CC) +{ + switch (CC) { + default: return NULL; // never reach + case A64CC_EQ: return "eq"; + case A64CC_NE: return "ne"; + case A64CC_HS: return "hs"; + case A64CC_LO: return "lo"; + case A64CC_MI: return "mi"; + case A64CC_PL: return "pl"; + case A64CC_VS: return "vs"; + case A64CC_VC: return "vc"; + case A64CC_HI: return "hi"; + case A64CC_LS: return "ls"; + case A64CC_GE: return "ge"; + case A64CC_LT: return "lt"; + case A64CC_GT: return "gt"; + case A64CC_LE: return "le"; + case A64CC_AL: return "al"; + case A64CC_NV: return "nv"; + } +} + +inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code) +{ + // To reverse a condition it's necessary to only invert the low bit: + return (A64CC_CondCode)((unsigned)Code ^ 0x1); +} + +/// Instances of this class can perform bidirectional mapping from random +/// identifier strings to operand encodings. For example "MSR" takes a named +/// system-register which must be encoded somehow and decoded for printing. This +/// central location means that the information for those transformations is not +/// duplicated and remains in sync. +/// +/// FIXME: currently the algorithm is a completely unoptimised linear +/// search. Obviously this could be improved, but we would probably want to work +/// out just how often these instructions are emitted before working on it. It +/// might even be optimal to just reorder the tables for the common instructions +/// rather than changing the algorithm. +typedef struct A64NamedImmMapper_Mapping { + const char *Name; + uint32_t Value; +} A64NamedImmMapper_Mapping; + +typedef struct A64NamedImmMapper { + const A64NamedImmMapper_Mapping *Pairs; + size_t NumPairs; + uint32_t TooBigImm; +} A64NamedImmMapper; + +typedef struct A64SysRegMapper { + const A64NamedImmMapper_Mapping *SysRegPairs; + const A64NamedImmMapper_Mapping *InstPairs; + size_t NumInstPairs; +} A64SysRegMapper; + +extern const A64SysRegMapper AArch64_MSRMapper; +extern const A64SysRegMapper AArch64_MRSMapper; + +extern const A64NamedImmMapper A64DB_DBarrierMapper; +extern const A64NamedImmMapper A64AT_ATMapper; +extern const A64NamedImmMapper A64DC_DCMapper; +extern const A64NamedImmMapper A64IC_ICMapper; +extern const A64NamedImmMapper A64ISB_ISBMapper; +extern const A64NamedImmMapper A64PRFM_PRFMMapper; +extern const A64NamedImmMapper A64PState_PStateMapper; +extern const A64NamedImmMapper A64TLBI_TLBIMapper; + +enum { + A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2 + A64AT_S1E1R = 0x43c0, // 01 000 0111 1000 000 + A64AT_S1E2R = 0x63c0, // 01 100 0111 1000 000 + A64AT_S1E3R = 0x73c0, // 01 110 0111 1000 000 + A64AT_S1E1W = 0x43c1, // 01 000 0111 1000 001 + A64AT_S1E2W = 0x63c1, // 01 100 0111 1000 001 + A64AT_S1E3W = 0x73c1, // 01 110 0111 1000 001 + A64AT_S1E0R = 0x43c2, // 01 000 0111 1000 010 + A64AT_S1E0W = 0x43c3, // 01 000 0111 1000 011 + A64AT_S12E1R = 0x63c4, // 01 100 0111 1000 100 + A64AT_S12E1W = 0x63c5, // 01 100 0111 1000 101 + A64AT_S12E0R = 0x63c6, // 01 100 0111 1000 110 + A64AT_S12E0W = 0x63c7 // 01 100 0111 1000 111 +}; + +enum A64DBValues { + A64DB_Invalid = -1, + A64DB_OSHLD = 0x1, + A64DB_OSHST = 0x2, + A64DB_OSH = 0x3, + A64DB_NSHLD = 0x5, + A64DB_NSHST = 0x6, + A64DB_NSH = 0x7, + A64DB_ISHLD = 0x9, + A64DB_ISHST = 0xa, + A64DB_ISH = 0xb, + A64DB_LD = 0xd, + A64DB_ST = 0xe, + A64DB_SY = 0xf +}; + +enum A64DCValues { + A64DC_Invalid = -1, // Op1 CRn CRm Op2 + A64DC_ZVA = 0x5ba1, // 01 011 0111 0100 001 + A64DC_IVAC = 0x43b1, // 01 000 0111 0110 001 + A64DC_ISW = 0x43b2, // 01 000 0111 0110 010 + A64DC_CVAC = 0x5bd1, // 01 011 0111 1010 001 + A64DC_CSW = 0x43d2, // 01 000 0111 1010 010 + A64DC_CVAU = 0x5bd9, // 01 011 0111 1011 001 + A64DC_CIVAC = 0x5bf1, // 01 011 0111 1110 001 + A64DC_CISW = 0x43f2 // 01 000 0111 1110 010 +}; + +enum A64ICValues { + A64IC_Invalid = -1, // Op1 CRn CRm Op2 + A64IC_IALLUIS = 0x0388, // 000 0111 0001 000 + A64IC_IALLU = 0x03a8, // 000 0111 0101 000 + A64IC_IVAU = 0x1ba9 // 011 0111 0101 001 +}; + +enum A64ISBValues { + A64ISB_Invalid = -1, + A64ISB_SY = 0xf +}; + +enum A64PRFMValues { + A64PRFM_Invalid = -1, + A64PRFM_PLDL1KEEP = 0x00, + A64PRFM_PLDL1STRM = 0x01, + A64PRFM_PLDL2KEEP = 0x02, + A64PRFM_PLDL2STRM = 0x03, + A64PRFM_PLDL3KEEP = 0x04, + A64PRFM_PLDL3STRM = 0x05, + A64PRFM_PLIL1KEEP = 0x08, + A64PRFM_PLIL1STRM = 0x09, + A64PRFM_PLIL2KEEP = 0x0a, + A64PRFM_PLIL2STRM = 0x0b, + A64PRFM_PLIL3KEEP = 0x0c, + A64PRFM_PLIL3STRM = 0x0d, + A64PRFM_PSTL1KEEP = 0x10, + A64PRFM_PSTL1STRM = 0x11, + A64PRFM_PSTL2KEEP = 0x12, + A64PRFM_PSTL2STRM = 0x13, + A64PRFM_PSTL3KEEP = 0x14, + A64PRFM_PSTL3STRM = 0x15 +}; + +enum A64PStateValues { + A64PState_Invalid = -1, + A64PState_SPSel = 0x05, + A64PState_DAIFSet = 0x1e, + A64PState_DAIFClr = 0x1f, + A64PState_PAN = 0x4, + A64PState_UAO = 0x3 +}; + +typedef enum A64SE_ShiftExtSpecifiers { + A64SE_Invalid = -1, + A64SE_LSL, + A64SE_MSL, + A64SE_LSR, + A64SE_ASR, + A64SE_ROR, + + A64SE_UXTB, + A64SE_UXTH, + A64SE_UXTW, + A64SE_UXTX, + + A64SE_SXTB, + A64SE_SXTH, + A64SE_SXTW, + A64SE_SXTX +} A64SE_ShiftExtSpecifiers; + +typedef enum A64Layout_VectorLayout { + A64Layout_Invalid = -1, + A64Layout_VL_8B, + A64Layout_VL_4H, + A64Layout_VL_2S, + A64Layout_VL_1D, + + A64Layout_VL_16B, + A64Layout_VL_8H, + A64Layout_VL_4S, + A64Layout_VL_2D, + + // Bare layout for the 128-bit vector + // (only show ".b", ".h", ".s", ".d" without vector number) + A64Layout_VL_B, + A64Layout_VL_H, + A64Layout_VL_S, + A64Layout_VL_D +} A64Layout_VectorLayout; + +inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout) +{ + switch (Layout) { + case A64Layout_VL_8B: return ".8b"; + case A64Layout_VL_4H: return ".4h"; + case A64Layout_VL_2S: return ".2s"; + case A64Layout_VL_1D: return ".1d"; + case A64Layout_VL_16B: return ".16b"; + case A64Layout_VL_8H: return ".8h"; + case A64Layout_VL_4S: return ".4s"; + case A64Layout_VL_2D: return ".2d"; + case A64Layout_VL_B: return ".b"; + case A64Layout_VL_H: return ".h"; + case A64Layout_VL_S: return ".s"; + case A64Layout_VL_D: return ".d"; + default: return NULL; // never reach + } +} + +enum A64SysRegROValues { + A64SysReg_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 + A64SysReg_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 + A64SysReg_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 + A64SysReg_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 + A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 + A64SysReg_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 + A64SysReg_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 + A64SysReg_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 + A64SysReg_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 + A64SysReg_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 + A64SysReg_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 + A64SysReg_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 + A64SysReg_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 + A64SysReg_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 + A64SysReg_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 + A64SysReg_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 + A64SysReg_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 + A64SysReg_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 + A64SysReg_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 + A64SysReg_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 + A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 + A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 + A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 + A64SysReg_ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110 + A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 + A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 + A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 + A64SysReg_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 + A64SysReg_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 + A64SysReg_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 + A64SysReg_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 + A64SysReg_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 + A64SysReg_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 + A64SysReg_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 + A64SysReg_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 + A64SysReg_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 + A64SysReg_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 + A64SysReg_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 + A64SysReg_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 + A64SysReg_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 + A64SysReg_ID_A64MMFR2_EL1 = 0xC03A, // 11 000 0000 0111 010 + A64SysReg_LORC_EL1 = 0xc523, // 11 000 1010 0100 011 + A64SysReg_LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 + A64SysReg_LORID_EL1 = 0xc527, // 11 000 1010 0100 111 + A64SysReg_LORN_EL1 = 0xc522, // 11 000 1010 0100 010 + A64SysReg_LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 + A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 + A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 + A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 + A64SysReg_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 + A64SysReg_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 + A64SysReg_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 + A64SysReg_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 + A64SysReg_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 + A64SysReg_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 + + // Trace registers + A64SysReg_TRCSTATR = 0x8818, // 10 001 0000 0011 000 + A64SysReg_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 + A64SysReg_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 + A64SysReg_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 + A64SysReg_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 + A64SysReg_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 + A64SysReg_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 + A64SysReg_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 + A64SysReg_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 + A64SysReg_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 + A64SysReg_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 + A64SysReg_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 + A64SysReg_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 + A64SysReg_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 + A64SysReg_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 + A64SysReg_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 + A64SysReg_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 + A64SysReg_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 + A64SysReg_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 + A64SysReg_TRCLSR = 0x8bee, // 10 001 0111 1101 110 + A64SysReg_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 + A64SysReg_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 + A64SysReg_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 + A64SysReg_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 + A64SysReg_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 + A64SysReg_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 + A64SysReg_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 + A64SysReg_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 + A64SysReg_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 + A64SysReg_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 + A64SysReg_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 + A64SysReg_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 + A64SysReg_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 + A64SysReg_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 + A64SysReg_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 + A64SysReg_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 + + // GICv3 registers + A64SysReg_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 + A64SysReg_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 + A64SysReg_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 + A64SysReg_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 + A64SysReg_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 + A64SysReg_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 + A64SysReg_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 + A64SysReg_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 +}; + +enum A64SysRegWOValues { + A64SysReg_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 + A64SysReg_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 + A64SysReg_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 + + // Trace Registers + A64SysReg_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 + A64SysReg_TRCLAR = 0x8be6, // 10 001 0111 1100 110 + + // GICv3 registers + A64SysReg_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 + A64SysReg_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 + A64SysReg_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 + A64SysReg_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 + A64SysReg_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 + A64SysReg_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 +}; + +enum A64SysRegValues { + A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2 + A64SysReg_PAN = 0xc213, // 11 000 0100 0010 011 + A64SysReg_UAO = 0xc214, // 11 000 0100 0010 100 + A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 + A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 + A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 + A64SysReg_MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 + A64SysReg_MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 + A64SysReg_DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 + A64SysReg_OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 + A64SysReg_DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 + A64SysReg_DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 + A64SysReg_DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 + A64SysReg_DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 + A64SysReg_DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 + A64SysReg_DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 + A64SysReg_DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 + A64SysReg_DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 + A64SysReg_DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 + A64SysReg_DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 + A64SysReg_DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 + A64SysReg_DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 + A64SysReg_DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 + A64SysReg_DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 + A64SysReg_DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 + A64SysReg_DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 + A64SysReg_DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 + A64SysReg_DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 + A64SysReg_DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 + A64SysReg_DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 + A64SysReg_DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 + A64SysReg_DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 + A64SysReg_DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 + A64SysReg_DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 + A64SysReg_DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 + A64SysReg_DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 + A64SysReg_DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 + A64SysReg_DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 + A64SysReg_DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 + A64SysReg_DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 + A64SysReg_DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 + A64SysReg_DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 + A64SysReg_DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 + A64SysReg_DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 + A64SysReg_DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 + A64SysReg_DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 + A64SysReg_DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 + A64SysReg_DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 + A64SysReg_DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 + A64SysReg_DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 + A64SysReg_DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 + A64SysReg_DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 + A64SysReg_DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 + A64SysReg_DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 + A64SysReg_DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 + A64SysReg_DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 + A64SysReg_DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 + A64SysReg_DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 + A64SysReg_DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 + A64SysReg_DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 + A64SysReg_DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 + A64SysReg_DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 + A64SysReg_DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 + A64SysReg_DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 + A64SysReg_DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 + A64SysReg_DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 + A64SysReg_DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 + A64SysReg_DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 + A64SysReg_DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 + A64SysReg_DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 + A64SysReg_DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 + A64SysReg_DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 + A64SysReg_DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 + A64SysReg_DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 + A64SysReg_DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 + A64SysReg_TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 + A64SysReg_OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 + A64SysReg_DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 + A64SysReg_DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 + A64SysReg_DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 + A64SysReg_CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 + A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 + A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 + A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 + A64SysReg_CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 + A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 + A64SysReg_SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 + A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 + A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 + A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 + A64SysReg_ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 + A64SysReg_ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 + A64SysReg_HCR_EL2 = 0xe088, // 11 100 0001 0001 000 + A64SysReg_SCR_EL3 = 0xf088, // 11 110 0001 0001 000 + A64SysReg_MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 + A64SysReg_SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 + A64SysReg_CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 + A64SysReg_CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 + A64SysReg_HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 + A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 + A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 + A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 + A64SysReg_TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 + A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 + A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 + A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 + A64SysReg_TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 + A64SysReg_TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 + A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010 + A64SysReg_TCR_EL12 = 0xe902, // 11 101 0010 0000 010 + A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010 + A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010 + A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 + A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 + A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 + A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 + A64SysReg_SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 + A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 + A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 + A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001 + A64SysReg_ELR_EL12 = 0xea01, // 11 101 0100 0000 001 + A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001 + A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001 + A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000 + A64SysReg_SP_EL1 = 0xe208, // 11 100 0100 0001 000 + A64SysReg_SP_EL2 = 0xf208, // 11 110 0100 0001 000 + A64SysReg_SPSel = 0xc210, // 11 000 0100 0010 000 + A64SysReg_NZCV = 0xda10, // 11 011 0100 0010 000 + A64SysReg_DAIF = 0xda11, // 11 011 0100 0010 001 + A64SysReg_CurrentEL = 0xc212, // 11 000 0100 0010 010 + A64SysReg_SPSR_irq = 0xe218, // 11 100 0100 0011 000 + A64SysReg_SPSR_abt = 0xe219, // 11 100 0100 0011 001 + A64SysReg_SPSR_und = 0xe21a, // 11 100 0100 0011 010 + A64SysReg_SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 + A64SysReg_FPCR = 0xda20, // 11 011 0100 0100 000 + A64SysReg_FPSR = 0xda21, // 11 011 0100 0100 001 + A64SysReg_DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 + A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001 + A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 + A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 + A64SysReg_AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 + A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 + A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 + A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 + A64SysReg_AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 + A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 + A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 + A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000 + A64SysReg_ESR_EL12 = 0xea90, // 11 101 0101 0010 000 + A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000 + A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000 + A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 + A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000 + A64SysReg_FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 + A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000 + A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000 + A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 + A64SysReg_PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 + A64SysReg_PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 + A64SysReg_PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 + A64SysReg_PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 + A64SysReg_PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 + A64SysReg_PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 + A64SysReg_PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 + A64SysReg_PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 + A64SysReg_PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 + A64SysReg_PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 + A64SysReg_PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 + A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 + A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 + A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 + A64SysReg_MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 + A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 + A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 + A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 + A64SysReg_AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 + A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 + A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 + A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 + A64SysReg_VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 + A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 + A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 + A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010 + A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010 + A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010 + A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 + A64SysReg_CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 + A64SysReg_CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 + A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 + A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 + A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 + A64SysReg_TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 + A64SysReg_TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 + A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 + A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 + A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 + A64SysReg_CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 + A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 + A64SysReg_CNTHVCTL_EL2 = 0xe719, // 11 100 1110 0011 001 + A64SysReg_CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 + A64SysReg_CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 + A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 + A64SysReg_CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 + A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 + A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 + A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 + A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 + A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 + A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 + A64SysReg_CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 + A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 + A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 + A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 + A64SysReg_CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 + A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 + A64SysReg_CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 + A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 + A64SysReg_CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 + A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 + A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 + A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 + A64SysReg_PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 + A64SysReg_PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 + A64SysReg_PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 + A64SysReg_PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 + A64SysReg_PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 + A64SysReg_PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 + A64SysReg_PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 + A64SysReg_PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 + A64SysReg_PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 + A64SysReg_PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 + A64SysReg_PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 + A64SysReg_PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 + A64SysReg_PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 + A64SysReg_PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 + A64SysReg_PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 + A64SysReg_PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 + A64SysReg_PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 + A64SysReg_PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 + A64SysReg_PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 + A64SysReg_PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 + A64SysReg_PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 + A64SysReg_PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 + A64SysReg_PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 + A64SysReg_PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 + A64SysReg_PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 + A64SysReg_PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 + A64SysReg_PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 + A64SysReg_PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 + A64SysReg_PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 + A64SysReg_PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 + A64SysReg_PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 + A64SysReg_PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 + A64SysReg_PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 + A64SysReg_PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 + A64SysReg_PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 + A64SysReg_PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 + A64SysReg_PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 + A64SysReg_PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 + A64SysReg_PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 + A64SysReg_PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 + A64SysReg_PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 + A64SysReg_PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 + A64SysReg_PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 + A64SysReg_PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 + A64SysReg_PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 + A64SysReg_PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 + A64SysReg_PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 + A64SysReg_PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 + A64SysReg_PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 + A64SysReg_PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 + A64SysReg_PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 + A64SysReg_PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 + A64SysReg_PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 + A64SysReg_PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 + A64SysReg_PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 + A64SysReg_PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 + A64SysReg_PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 + A64SysReg_PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 + A64SysReg_PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 + A64SysReg_PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 + + // Trace registers + A64SysReg_TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 + A64SysReg_TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 + A64SysReg_TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 + A64SysReg_TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 + A64SysReg_TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 + A64SysReg_TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 + A64SysReg_TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 + A64SysReg_TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 + A64SysReg_TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 + A64SysReg_TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 + A64SysReg_TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 + A64SysReg_TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 + A64SysReg_TRCQCTLR = 0x8809, // 10 001 0000 0001 001 + A64SysReg_TRCVICTLR = 0x8802, // 10 001 0000 0000 010 + A64SysReg_TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 + A64SysReg_TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 + A64SysReg_TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 + A64SysReg_TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 + A64SysReg_TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 + A64SysReg_TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 + A64SysReg_TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 + A64SysReg_TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 + A64SysReg_TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 + A64SysReg_TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 + A64SysReg_TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 + A64SysReg_TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 + A64SysReg_TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 + A64SysReg_TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 + A64SysReg_TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 + A64SysReg_TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 + A64SysReg_TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 + A64SysReg_TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 + A64SysReg_TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 + A64SysReg_TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 + A64SysReg_TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 + A64SysReg_TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 + A64SysReg_TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 + A64SysReg_TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 + A64SysReg_TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 + A64SysReg_TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 + A64SysReg_TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 + A64SysReg_TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 + A64SysReg_TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 + A64SysReg_TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 + A64SysReg_TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 + A64SysReg_TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 + A64SysReg_TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 + A64SysReg_TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 + A64SysReg_TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 + A64SysReg_TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 + A64SysReg_TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 + A64SysReg_TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 + A64SysReg_TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 + A64SysReg_TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 + A64SysReg_TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 + A64SysReg_TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 + A64SysReg_TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 + A64SysReg_TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 + A64SysReg_TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 + A64SysReg_TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 + A64SysReg_TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 + A64SysReg_TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 + A64SysReg_TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 + A64SysReg_TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 + A64SysReg_TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 + A64SysReg_TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 + A64SysReg_TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 + A64SysReg_TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 + A64SysReg_TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 + A64SysReg_TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 + A64SysReg_TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 + A64SysReg_TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 + A64SysReg_TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 + A64SysReg_TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 + A64SysReg_TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 + A64SysReg_TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 + A64SysReg_TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 + A64SysReg_TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 + A64SysReg_TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 + A64SysReg_TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 + A64SysReg_TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 + A64SysReg_TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 + A64SysReg_TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 + A64SysReg_TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 + A64SysReg_TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 + A64SysReg_TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 + A64SysReg_TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 + A64SysReg_TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 + A64SysReg_TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 + A64SysReg_TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 + A64SysReg_TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 + A64SysReg_TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 + A64SysReg_TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 + A64SysReg_TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 + A64SysReg_TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 + A64SysReg_TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 + A64SysReg_TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 + A64SysReg_TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 + A64SysReg_TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 + A64SysReg_TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 + A64SysReg_TRCPDCR = 0x88a4, // 10 001 0001 0100 100 + A64SysReg_TRCACVR0 = 0x8900, // 10 001 0010 0000 000 + A64SysReg_TRCACVR1 = 0x8910, // 10 001 0010 0010 000 + A64SysReg_TRCACVR2 = 0x8920, // 10 001 0010 0100 000 + A64SysReg_TRCACVR3 = 0x8930, // 10 001 0010 0110 000 + A64SysReg_TRCACVR4 = 0x8940, // 10 001 0010 1000 000 + A64SysReg_TRCACVR5 = 0x8950, // 10 001 0010 1010 000 + A64SysReg_TRCACVR6 = 0x8960, // 10 001 0010 1100 000 + A64SysReg_TRCACVR7 = 0x8970, // 10 001 0010 1110 000 + A64SysReg_TRCACVR8 = 0x8901, // 10 001 0010 0000 001 + A64SysReg_TRCACVR9 = 0x8911, // 10 001 0010 0010 001 + A64SysReg_TRCACVR10 = 0x8921, // 10 001 0010 0100 001 + A64SysReg_TRCACVR11 = 0x8931, // 10 001 0010 0110 001 + A64SysReg_TRCACVR12 = 0x8941, // 10 001 0010 1000 001 + A64SysReg_TRCACVR13 = 0x8951, // 10 001 0010 1010 001 + A64SysReg_TRCACVR14 = 0x8961, // 10 001 0010 1100 001 + A64SysReg_TRCACVR15 = 0x8971, // 10 001 0010 1110 001 + A64SysReg_TRCACATR0 = 0x8902, // 10 001 0010 0000 010 + A64SysReg_TRCACATR1 = 0x8912, // 10 001 0010 0010 010 + A64SysReg_TRCACATR2 = 0x8922, // 10 001 0010 0100 010 + A64SysReg_TRCACATR3 = 0x8932, // 10 001 0010 0110 010 + A64SysReg_TRCACATR4 = 0x8942, // 10 001 0010 1000 010 + A64SysReg_TRCACATR5 = 0x8952, // 10 001 0010 1010 010 + A64SysReg_TRCACATR6 = 0x8962, // 10 001 0010 1100 010 + A64SysReg_TRCACATR7 = 0x8972, // 10 001 0010 1110 010 + A64SysReg_TRCACATR8 = 0x8903, // 10 001 0010 0000 011 + A64SysReg_TRCACATR9 = 0x8913, // 10 001 0010 0010 011 + A64SysReg_TRCACATR10 = 0x8923, // 10 001 0010 0100 011 + A64SysReg_TRCACATR11 = 0x8933, // 10 001 0010 0110 011 + A64SysReg_TRCACATR12 = 0x8943, // 10 001 0010 1000 011 + A64SysReg_TRCACATR13 = 0x8953, // 10 001 0010 1010 011 + A64SysReg_TRCACATR14 = 0x8963, // 10 001 0010 1100 011 + A64SysReg_TRCACATR15 = 0x8973, // 10 001 0010 1110 011 + A64SysReg_TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 + A64SysReg_TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 + A64SysReg_TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 + A64SysReg_TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 + A64SysReg_TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 + A64SysReg_TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 + A64SysReg_TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 + A64SysReg_TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 + A64SysReg_TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 + A64SysReg_TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 + A64SysReg_TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 + A64SysReg_TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 + A64SysReg_TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 + A64SysReg_TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 + A64SysReg_TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 + A64SysReg_TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 + A64SysReg_TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 + A64SysReg_TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 + A64SysReg_TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 + A64SysReg_TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 + A64SysReg_TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 + A64SysReg_TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 + A64SysReg_TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 + A64SysReg_TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 + A64SysReg_TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 + A64SysReg_TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 + A64SysReg_TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 + A64SysReg_TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 + A64SysReg_TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 + A64SysReg_TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 + A64SysReg_TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 + A64SysReg_TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 + A64SysReg_TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 + A64SysReg_TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 + A64SysReg_TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 + A64SysReg_TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 + A64SysReg_TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 + A64SysReg_TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 + A64SysReg_TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 + + // GICv3 registers + A64SysReg_ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 + A64SysReg_ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 + A64SysReg_ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 + A64SysReg_ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 + A64SysReg_ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 + A64SysReg_ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 + A64SysReg_ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 + A64SysReg_ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 + A64SysReg_ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 + A64SysReg_ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 + A64SysReg_ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 + A64SysReg_ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 + A64SysReg_ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 + A64SysReg_ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 + A64SysReg_ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 + A64SysReg_ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 + A64SysReg_ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 + A64SysReg_ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 + A64SysReg_ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 + A64SysReg_ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 + A64SysReg_ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 + A64SysReg_ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 + A64SysReg_ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 + A64SysReg_ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 + A64SysReg_ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 + A64SysReg_ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 + A64SysReg_ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 + A64SysReg_ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 + A64SysReg_ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 + A64SysReg_ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 + A64SysReg_ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 + A64SysReg_ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 + A64SysReg_ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 + A64SysReg_ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 + A64SysReg_ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 + A64SysReg_ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 + A64SysReg_ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 + A64SysReg_ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 + A64SysReg_ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 + A64SysReg_ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 + A64SysReg_ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 + A64SysReg_ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 + A64SysReg_ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 + A64SysReg_ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 + A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 + A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 + A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 + A64SysReg_ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 + + // Statistical profiling registers + A64SysReg_PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111 + A64SysReg_PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111 + A64SysReg_PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000 + A64SysReg_PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001 + A64SysReg_PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011 + A64SysReg_PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000 + A64SysReg_PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000 + A64SysReg_PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000 + A64SysReg_PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010 + A64SysReg_PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011 + A64SysReg_PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100 + A64SysReg_PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101 + A64SysReg_PMSLATFR_EL1 = 0xc4ce // 11 000 1001 1001 110 +}; + +// Cyclone specific system registers +enum A64CycloneSysRegValues { + A64SysReg_CPM_IOACC_CTL_EL3 = 0xff90 +}; + +enum A64TLBIValues { + A64TLBI_Invalid = -1, // Op0 Op1 CRn CRm Op2 + A64TLBI_IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 + A64TLBI_IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 + A64TLBI_VMALLE1IS = 0x4418, // 01 000 1000 0011 000 + A64TLBI_ALLE2IS = 0x6418, // 01 100 1000 0011 000 + A64TLBI_ALLE3IS = 0x7418, // 01 110 1000 0011 000 + A64TLBI_VAE1IS = 0x4419, // 01 000 1000 0011 001 + A64TLBI_VAE2IS = 0x6419, // 01 100 1000 0011 001 + A64TLBI_VAE3IS = 0x7419, // 01 110 1000 0011 001 + A64TLBI_ASIDE1IS = 0x441a, // 01 000 1000 0011 010 + A64TLBI_VAAE1IS = 0x441b, // 01 000 1000 0011 011 + A64TLBI_ALLE1IS = 0x641c, // 01 100 1000 0011 100 + A64TLBI_VALE1IS = 0x441d, // 01 000 1000 0011 101 + A64TLBI_VALE2IS = 0x641d, // 01 100 1000 0011 101 + A64TLBI_VALE3IS = 0x741d, // 01 110 1000 0011 101 + A64TLBI_VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 + A64TLBI_VAALE1IS = 0x441f, // 01 000 1000 0011 111 + A64TLBI_IPAS2E1 = 0x6421, // 01 100 1000 0100 001 + A64TLBI_IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 + A64TLBI_VMALLE1 = 0x4438, // 01 000 1000 0111 000 + A64TLBI_ALLE2 = 0x6438, // 01 100 1000 0111 000 + A64TLBI_ALLE3 = 0x7438, // 01 110 1000 0111 000 + A64TLBI_VAE1 = 0x4439, // 01 000 1000 0111 001 + A64TLBI_VAE2 = 0x6439, // 01 100 1000 0111 001 + A64TLBI_VAE3 = 0x7439, // 01 110 1000 0111 001 + A64TLBI_ASIDE1 = 0x443a, // 01 000 1000 0111 010 + A64TLBI_VAAE1 = 0x443b, // 01 000 1000 0111 011 + A64TLBI_ALLE1 = 0x643c, // 01 100 1000 0111 100 + A64TLBI_VALE1 = 0x443d, // 01 000 1000 0111 101 + A64TLBI_VALE2 = 0x643d, // 01 100 1000 0111 101 + A64TLBI_VALE3 = 0x743d, // 01 110 1000 0111 101 + A64TLBI_VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 + A64TLBI_VAALE1 = 0x443f // 01 000 1000 0111 111 +}; + +bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm); + +const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid); + +uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid); + +bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value); + +void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result); + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.c b/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.c new file mode 100644 index 0000000..2ce96fa --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.c @@ -0,0 +1,1672 @@ +//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the functions necessary to decode AArch64 instruction +// bitpatterns into MCInsts (with the help of TableGenerated information from +// the instruction definitions). +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_ARM64 + +#include // DEBUG +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "AArch64Disassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" + +#include "AArch64BaseInfo.h" +#include "AArch64AddressingModes.h" + + +// Forward declare these because the autogenerated code will reference them. +// Definitions are further down. +static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, + uint32_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, + uint32_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, + uint32_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, + uint32_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder); +static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder); +static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder); +static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder); + +static bool Check(DecodeStatus *Out, DecodeStatus In) +{ + switch (In) { + default: // never reach + return true; + case MCDisassembler_Success: + // Out stays the same. + return true; + case MCDisassembler_SoftFail: + *Out = In; + return true; + case MCDisassembler_Fail: + *Out = In; + return false; + } + // llvm_unreachable("Invalid DecodeStatus!"); +} + +// Hacky: enable all features for disassembler +static uint64_t getFeatureBits(int feature) +{ + // enable all features + return (uint64_t)-1; +} + +#define GET_SUBTARGETINFO_ENUM +#include "AArch64GenSubtargetInfo.inc" + +#include "AArch64GenDisassemblerTables.inc" + +#define GET_INSTRINFO_ENUM +#include "AArch64GenInstrInfo.inc" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "AArch64GenRegisterInfo.inc" + +#define Success MCDisassembler_Success +#define Fail MCDisassembler_Fail +#define SoftFail MCDisassembler_SoftFail + +static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, + const uint8_t *code, size_t code_len, + uint16_t *Size, + uint64_t Address, MCRegisterInfo *MRI) +{ + uint32_t insn; + DecodeStatus result; + size_t i; + + if (code_len < 4) { + // not enough data + *Size = 0; + return MCDisassembler_Fail; + } + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64)); + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++) + MI->flat_insn->detail->arm64.operands[i].vector_index = -1; + } + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn = (code[3] << 0) | (code[2] << 8) | + (code[1] << 16) | ((uint32_t) code[0] << 24); + else + insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | + (code[1] << 8) | (code[0] << 0); + + // Calling the auto-generated decoder function. + result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + *Size = 0; + return MCDisassembler_Fail; +} + +bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info) +{ + DecodeStatus status = _getInstruction((cs_struct *)ud, instr, + code, code_len, + size, + address, (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +static const unsigned FPR128DecoderTable[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, + AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, + AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, + AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, + AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, + AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, + AArch64_Q30, AArch64_Q31 +}; + +static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + if (RegNo > 31) + return Fail; + + Register = FPR128DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + if (RegNo > 15) + return Fail; + + return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); +} + +static const unsigned FPR64DecoderTable[] = { + AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, + AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, + AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, + AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, + AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, + AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, + AArch64_D30, AArch64_D31 +}; + +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = FPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR32DecoderTable[] = { + AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, + AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, + AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, + AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, + AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, + AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, + AArch64_S30, AArch64_S31 +}; + +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = FPR32DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR16DecoderTable[] = { + AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, + AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, + AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, + AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, + AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, + AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, + AArch64_H30, AArch64_H31 +}; + +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = FPR16DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR8DecoderTable[] = { + AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, + AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, + AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, + AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, + AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, + AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, + AArch64_B30, AArch64_B31 +}; + +static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = FPR8DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned GPR64DecoderTable[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, AArch64_XZR +}; + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = GPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = GPR64DecoderTable[RegNo]; + if (Register == AArch64_XZR) + Register = AArch64_SP; + + MCOperand_CreateReg0(Inst, Register); + + return Success; +} + +static const unsigned GPR32DecoderTable[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, AArch64_WZR +}; + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = GPR32DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = GPR32DecoderTable[RegNo]; + if (Register == AArch64_WZR) + Register = AArch64_WSP; + + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned VectorDecoderTable[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, + AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, + AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, + AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, + AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, + AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, + AArch64_Q30, AArch64_Q31 +}; + +static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = VectorDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQDecoderTable[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, + AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, + AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, + AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, + AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0 +}; + +static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = QQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQQDecoderTable[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, + AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, + AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, + AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, + AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, + AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1 +}; + +static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = QQQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQQQDecoderTable[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, + AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, + AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, + AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, + AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, + AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2 +}; + +static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + if (RegNo > 31) + return Fail; + + Register = QQQQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDecoderTable[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, + AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, + AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, + AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, + AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0 +}; + +static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = DDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDDecoderTable[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, + AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, + AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, + AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, + AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, + AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, + AArch64_D30_D31_D0, AArch64_D31_D0_D1 +}; + +static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = DDDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDDDecoderTable[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, + AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, + AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, + AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, + AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, + AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, + AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2 +}; + +static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return Fail; + + Register = DDDDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) +{ + // scale{5} is asserted as 1 in tblgen. + Imm |= 0x20; + MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; +} + +static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) +{ + MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; +} + +static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + int64_t ImmVal = Imm; + + // Sign-extend 19-bit immediate. + if (ImmVal & (1 << (19 - 1))) + ImmVal |= ~((1LL << 19) - 1); + + MCOperand_CreateImm0(Inst, ImmVal); + return Success; +} + +static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); + MCOperand_CreateImm0(Inst, Imm & 1); + return Success; +} + +static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, Imm); + + // Every system register in the encoding space is valid with the syntax + // S____, so decoding system registers always succeeds. + return Success; +} + +static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, + const void *Decoder) +{ + MCOperand_CreateImm0(Inst, Imm); + + return Success; +} + +static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + const void *Decoder) +{ + // This decoder exists to add the dummy Lane operand to the MCInst, which must + // be 1 in assembly but has no other real manifestation. + unsigned Rd = fieldFromInstruction(Insn, 0, 5); + unsigned Rn = fieldFromInstruction(Insn, 5, 5); + unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); + + if (IsToVec) { + DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); + } else { + DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); + DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); + } + + // Add the lane + MCOperand_CreateImm0(Inst, 1); + + return Success; +} + +static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, + unsigned Add) +{ + MCOperand_CreateImm0(Inst, Add - Imm); + return Success; +} + +static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, + unsigned Add) +{ + MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); + return Success; +} + +static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm, 64); +} + +static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); +} + +static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm, 32); +} + +static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); +} + +static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm, 16); +} + +static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); +} + +static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftRImm(Inst, Imm, 8); +} + +static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftLImm(Inst, Imm, 64); +} + +static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftLImm(Inst, Imm, 32); +} + +static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftLImm(Inst, Imm, 16); +} + +static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, const void *Decoder) +{ + return DecodeVecShiftLImm(Inst, Imm, 8); +} + +static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Rm = fieldFromInstruction(insn, 16, 5); + unsigned shiftHi = fieldFromInstruction(insn, 22, 2); + unsigned shiftLo = fieldFromInstruction(insn, 10, 6); + unsigned shift = (shiftHi << 6) | shiftLo; + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_ADDWrs: + case AArch64_ADDSWrs: + case AArch64_SUBWrs: + case AArch64_SUBSWrs: + // if shift == '11' then ReservedValue() + if (shiftHi == 0x3) + return Fail; + // Deliberate fallthrough + case AArch64_ANDWrs: + case AArch64_ANDSWrs: + case AArch64_BICWrs: + case AArch64_BICSWrs: + case AArch64_ORRWrs: + case AArch64_ORNWrs: + case AArch64_EORWrs: + case AArch64_EONWrs: { + // if sf == '0' and imm6<5> == '1' then ReservedValue() + if (shiftLo >> 5 == 1) + return Fail; + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + case AArch64_ADDXrs: + case AArch64_ADDSXrs: + case AArch64_SUBXrs: + case AArch64_SUBSXrs: + // if shift == '11' then ReservedValue() + if (shiftHi == 0x3) + return Fail; + // Deliberate fallthrough + case AArch64_ANDXrs: + case AArch64_ANDSXrs: + case AArch64_BICXrs: + case AArch64_BICSXrs: + case AArch64_ORRXrs: + case AArch64_ORNXrs: + case AArch64_EORXrs: + case AArch64_EONXrs: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + + MCOperand_CreateImm0(Inst, shift); + return Success; +} + +static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned imm = fieldFromInstruction(insn, 5, 16); + unsigned shift = fieldFromInstruction(insn, 21, 2); + + shift <<= 4; + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_MOVZWi: + case AArch64_MOVNWi: + case AArch64_MOVKWi: + if (shift & (1U << 5)) + return Fail; + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + break; + case AArch64_MOVZXi: + case AArch64_MOVNXi: + case AArch64_MOVKXi: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + break; + } + + if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || + MCInst_getOpcode(Inst) == AArch64_MOVKXi) + MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); + + MCOperand_CreateImm0(Inst, imm); + MCOperand_CreateImm0(Inst, shift); + return Success; +} + +static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned offset = fieldFromInstruction(insn, 10, 12); + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_PRFMui: + // Rt is an immediate in prefetch. + MCOperand_CreateImm0(Inst, Rt); + break; + case AArch64_STRBBui: + case AArch64_LDRBBui: + case AArch64_LDRSBWui: + case AArch64_STRHHui: + case AArch64_LDRHHui: + case AArch64_LDRSHWui: + case AArch64_STRWui: + case AArch64_LDRWui: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRSBXui: + case AArch64_LDRSHXui: + case AArch64_LDRSWui: + case AArch64_STRXui: + case AArch64_LDRXui: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRQui: + case AArch64_STRQui: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRDui: + case AArch64_STRDui: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRSui: + case AArch64_STRSui: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRHui: + case AArch64_STRHui: + DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDRBui: + case AArch64_STRBui: + DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, offset); + + return Success; +} + +static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + bool IsLoad; + bool IsIndexed; + bool IsFP; + unsigned Rt = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + int64_t offset = fieldFromInstruction(insn, 12, 9); + + // offset is a 9-bit signed immediate, so sign extend it to + // fill the unsigned. + if (offset & (1 << (9 - 1))) + offset |= ~((1LL << 9) - 1); + + // First operand is always the writeback to the address register, if needed. + switch (MCInst_getOpcode(Inst)) { + default: + break; + case AArch64_LDRSBWpre: + case AArch64_LDRSHWpre: + case AArch64_STRBBpre: + case AArch64_LDRBBpre: + case AArch64_STRHHpre: + case AArch64_LDRHHpre: + case AArch64_STRWpre: + case AArch64_LDRWpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSHWpost: + case AArch64_STRBBpost: + case AArch64_LDRBBpost: + case AArch64_STRHHpost: + case AArch64_LDRHHpost: + case AArch64_STRWpost: + case AArch64_LDRWpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHXpre: + case AArch64_STRXpre: + case AArch64_LDRSWpre: + case AArch64_LDRXpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSHXpost: + case AArch64_STRXpost: + case AArch64_LDRSWpost: + case AArch64_LDRXpost: + case AArch64_LDRQpre: + case AArch64_STRQpre: + case AArch64_LDRQpost: + case AArch64_STRQpost: + case AArch64_LDRDpre: + case AArch64_STRDpre: + case AArch64_LDRDpost: + case AArch64_STRDpost: + case AArch64_LDRSpre: + case AArch64_STRSpre: + case AArch64_LDRSpost: + case AArch64_STRSpost: + case AArch64_LDRHpre: + case AArch64_STRHpre: + case AArch64_LDRHpost: + case AArch64_STRHpost: + case AArch64_LDRBpre: + case AArch64_STRBpre: + case AArch64_LDRBpost: + case AArch64_STRBpost: + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + break; + } + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_PRFUMi: + // Rt is an immediate in prefetch. + MCOperand_CreateImm0(Inst, Rt); + break; + case AArch64_STURBBi: + case AArch64_LDURBBi: + case AArch64_LDURSBWi: + case AArch64_STURHHi: + case AArch64_LDURHHi: + case AArch64_LDURSHWi: + case AArch64_STURWi: + case AArch64_LDURWi: + case AArch64_LDTRSBWi: + case AArch64_LDTRSHWi: + case AArch64_STTRWi: + case AArch64_LDTRWi: + case AArch64_STTRHi: + case AArch64_LDTRHi: + case AArch64_LDTRBi: + case AArch64_STTRBi: + case AArch64_LDRSBWpre: + case AArch64_LDRSHWpre: + case AArch64_STRBBpre: + case AArch64_LDRBBpre: + case AArch64_STRHHpre: + case AArch64_LDRHHpre: + case AArch64_STRWpre: + case AArch64_LDRWpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSHWpost: + case AArch64_STRBBpost: + case AArch64_LDRBBpost: + case AArch64_STRHHpost: + case AArch64_LDRHHpost: + case AArch64_STRWpost: + case AArch64_LDRWpost: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURSBXi: + case AArch64_LDURSHXi: + case AArch64_LDURSWi: + case AArch64_STURXi: + case AArch64_LDURXi: + case AArch64_LDTRSBXi: + case AArch64_LDTRSHXi: + case AArch64_LDTRSWi: + case AArch64_STTRXi: + case AArch64_LDTRXi: + case AArch64_LDRSBXpre: + case AArch64_LDRSHXpre: + case AArch64_STRXpre: + case AArch64_LDRSWpre: + case AArch64_LDRXpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSHXpost: + case AArch64_STRXpost: + case AArch64_LDRSWpost: + case AArch64_LDRXpost: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURQi: + case AArch64_STURQi: + case AArch64_LDRQpre: + case AArch64_STRQpre: + case AArch64_LDRQpost: + case AArch64_STRQpost: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURDi: + case AArch64_STURDi: + case AArch64_LDRDpre: + case AArch64_STRDpre: + case AArch64_LDRDpost: + case AArch64_STRDpost: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURSi: + case AArch64_STURSi: + case AArch64_LDRSpre: + case AArch64_STRSpre: + case AArch64_LDRSpost: + case AArch64_STRSpost: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURHi: + case AArch64_STURHi: + case AArch64_LDRHpre: + case AArch64_STRHpre: + case AArch64_LDRHpost: + case AArch64_STRHpost: + DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURBi: + case AArch64_STURBi: + case AArch64_LDRBpre: + case AArch64_STRBpre: + case AArch64_LDRBpost: + case AArch64_STRBpost: + DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + MCOperand_CreateImm0(Inst, offset); + + IsLoad = fieldFromInstruction(insn, 22, 1) != 0; + IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; + IsFP = fieldFromInstruction(insn, 26, 1) != 0; + + // Cannot write back to a transfer register (but xzr != sp). + if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction(insn, 10, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Opcode = MCInst_getOpcode(Inst); + + switch (Opcode) { + default: + return Fail; + case AArch64_STLXRW: + case AArch64_STLXRB: + case AArch64_STLXRH: + case AArch64_STXRW: + case AArch64_STXRB: + case AArch64_STXRH: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + // FALLTHROUGH + case AArch64_LDARW: + case AArch64_LDARB: + case AArch64_LDARH: + case AArch64_LDAXRW: + case AArch64_LDAXRB: + case AArch64_LDAXRH: + case AArch64_LDXRW: + case AArch64_LDXRB: + case AArch64_LDXRH: + case AArch64_STLRW: + case AArch64_STLRB: + case AArch64_STLRH: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_STLXRX: + case AArch64_STXRX: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + // FALLTHROUGH + case AArch64_LDARX: + case AArch64_LDAXRX: + case AArch64_LDXRX: + case AArch64_STLRX: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_STLXPW: + case AArch64_STXPW: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + // FALLTHROUGH + case AArch64_LDAXPW: + case AArch64_LDXPW: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_STLXPX: + case AArch64_STXPX: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + // FALLTHROUGH + case AArch64_LDAXPX: + case AArch64_LDXPX: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + + // You shouldn't load to the same register twice in an instruction... + if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || + Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && + Rt == Rt2) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + const void *Decoder) +{ + unsigned Rt = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction(insn, 10, 5); + int32_t offset = fieldFromInstruction(insn, 15, 7); + bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0; + unsigned Opcode = MCInst_getOpcode(Inst); + bool NeedsDisjointWritebackTransfer = false; + + // offset is a 7-bit signed immediate, so sign extend it to + // fill the unsigned. + if (offset & (1 << (7 - 1))) + offset |= ~((1LL << 7) - 1); + + // First operand is always writeback of base register. + switch (Opcode) { + default: + break; + case AArch64_LDPXpost: + case AArch64_STPXpost: + case AArch64_LDPSWpost: + case AArch64_LDPXpre: + case AArch64_STPXpre: + case AArch64_LDPSWpre: + case AArch64_LDPWpost: + case AArch64_STPWpost: + case AArch64_LDPWpre: + case AArch64_STPWpre: + case AArch64_LDPQpost: + case AArch64_STPQpost: + case AArch64_LDPQpre: + case AArch64_STPQpre: + case AArch64_LDPDpost: + case AArch64_STPDpost: + case AArch64_LDPDpre: + case AArch64_STPDpre: + case AArch64_LDPSpost: + case AArch64_STPSpost: + case AArch64_LDPSpre: + case AArch64_STPSpre: + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + break; + } + + switch (Opcode) { + default: + return Fail; + case AArch64_LDPXpost: + case AArch64_STPXpost: + case AArch64_LDPSWpost: + case AArch64_LDPXpre: + case AArch64_STPXpre: + case AArch64_LDPSWpre: + NeedsDisjointWritebackTransfer = true; + // Fallthrough + case AArch64_LDNPXi: + case AArch64_STNPXi: + case AArch64_LDPXi: + case AArch64_STPXi: + case AArch64_LDPSWi: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDPWpost: + case AArch64_STPWpost: + case AArch64_LDPWpre: + case AArch64_STPWpre: + NeedsDisjointWritebackTransfer = true; + // Fallthrough + case AArch64_LDNPWi: + case AArch64_STNPWi: + case AArch64_LDPWi: + case AArch64_STPWi: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPQi: + case AArch64_STNPQi: + case AArch64_LDPQpost: + case AArch64_STPQpost: + case AArch64_LDPQi: + case AArch64_STPQi: + case AArch64_LDPQpre: + case AArch64_STPQpre: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPDi: + case AArch64_STNPDi: + case AArch64_LDPDpost: + case AArch64_STPDpost: + case AArch64_LDPDi: + case AArch64_STPDi: + case AArch64_LDPDpre: + case AArch64_STPDpre: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPSi: + case AArch64_STNPSi: + case AArch64_LDPSpost: + case AArch64_STPSpost: + case AArch64_LDPSi: + case AArch64_STPSi: + case AArch64_LDPSpre: + case AArch64_STPSpre: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + MCOperand_CreateImm0(Inst, offset); + + // You shouldn't load to the same register twice in an instruction... + if (IsLoad && Rt == Rt2) + return SoftFail; + + // ... or do any operation that writes-back to a transfer register. But note + // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. + if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rd, Rn, Rm; + unsigned extend = fieldFromInstruction(insn, 10, 6); + unsigned shift = extend & 0x7; + + if (shift > 4) + return Fail; + + Rd = fieldFromInstruction(insn, 0, 5); + Rn = fieldFromInstruction(insn, 5, 5); + Rm = fieldFromInstruction(insn, 16, 5); + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_ADDWrx: + case AArch64_SUBWrx: + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDSWrx: + case AArch64_SUBSWrx: + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDXrx: + case AArch64_SUBXrx: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDSXrx: + case AArch64_SUBSXrx: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDXrx64: + case AArch64_SUBXrx64: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_SUBSXrx64: + case AArch64_ADDSXrx64: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + + MCOperand_CreateImm0(Inst, extend); + return Success; +} + +static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Datasize = fieldFromInstruction(insn, 31, 1); + unsigned imm; + + if (Datasize) { + if (MCInst_getOpcode(Inst) == AArch64_ANDSXri) + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + imm = fieldFromInstruction(insn, 10, 13); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) + return Fail; + } else { + if (MCInst_getOpcode(Inst) == AArch64_ANDSWri) + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + imm = fieldFromInstruction(insn, 10, 12); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) + return Fail; + } + + MCOperand_CreateImm0(Inst, imm); + return Success; +} + +static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned cmode = fieldFromInstruction(insn, 12, 4); + unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; + imm |= fieldFromInstruction(insn, 5, 5); + + if (MCInst_getOpcode(Inst) == AArch64_MOVID) + DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + + MCOperand_CreateImm0(Inst, imm); + + switch (MCInst_getOpcode(Inst)) { + default: + break; + case AArch64_MOVIv4i16: + case AArch64_MOVIv8i16: + case AArch64_MVNIv4i16: + case AArch64_MVNIv8i16: + case AArch64_MOVIv2i32: + case AArch64_MOVIv4i32: + case AArch64_MVNIv2i32: + case AArch64_MVNIv4i32: + MCOperand_CreateImm0(Inst, (cmode & 6) << 2); + break; + case AArch64_MOVIv2s_msl: + case AArch64_MOVIv4s_msl: + case AArch64_MVNIv2s_msl: + case AArch64_MVNIv4s_msl: + MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108); + break; + } + + return Success; +} + +static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned cmode = fieldFromInstruction(insn, 12, 4); + unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; + imm |= fieldFromInstruction(insn, 5, 5); + + // Tied operands added twice. + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + + MCOperand_CreateImm0(Inst, imm); + MCOperand_CreateImm0(Inst, (cmode & 6) << 2); + + return Success; +} + +static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; + imm |= fieldFromInstruction(insn, 29, 2); + + // Sign-extend the 21-bit immediate. + if (imm & (1 << (21 - 1))) + imm |= ~((1LL << 21) - 1); + + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, imm); + + return Success; +} + +static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, + uint64_t Addr, const void *Decoder) +{ + unsigned Rd = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Imm = fieldFromInstruction(insn, 10, 14); + unsigned S = fieldFromInstruction(insn, 29, 1); + unsigned Datasize = fieldFromInstruction(insn, 31, 1); + + unsigned ShifterVal = (Imm >> 12) & 3; + unsigned ImmVal = Imm & 0xFFF; + + if (ShifterVal != 0 && ShifterVal != 1) + return Fail; + + if (Datasize) { + if (Rd == 31 && !S) + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + } else { + if (Rd == 31 && !S) + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + } + + //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, ImmVal); + MCOperand_CreateImm0(Inst, 12 * ShifterVal); + return Success; +} + +static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, + uint64_t Addr, + const void *Decoder) +{ + int64_t imm = fieldFromInstruction(insn, 0, 26); + + // Sign-extend the 26-bit immediate. + if (imm & (1 << (26 - 1))) + imm |= ~((1LL << 26) - 1); + + // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) + MCOperand_CreateImm0(Inst, imm); + + return Success; +} + +static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, + const void *Decoder) +{ + uint32_t op1 = fieldFromInstruction(insn, 16, 3); + uint32_t op2 = fieldFromInstruction(insn, 5, 3); + uint32_t crm = fieldFromInstruction(insn, 8, 4); + bool ValidNamed; + uint32_t pstate_field = (op1 << 3) | op2; + + MCOperand_CreateImm0(Inst, pstate_field); + MCOperand_CreateImm0(Inst, crm); + + A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed); + + return ValidNamed ? Success : Fail; +} + +static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, + uint64_t Addr, const void *Decoder) +{ + uint32_t Rt = fieldFromInstruction(insn, 0, 5); + uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5; + uint64_t dst = fieldFromInstruction(insn, 5, 14); + + bit |= fieldFromInstruction(insn, 19, 5); + + // Sign-extend 14-bit immediate. + if (dst & (1 << (14 - 1))) + dst |= ~((1LL << 14) - 1); + + if (fieldFromInstruction(insn, 31, 1) == 0) + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + else + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + + MCOperand_CreateImm0(Inst, bit); + //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) + MCOperand_CreateImm0(Inst, dst); + + return Success; +} + +void AArch64_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(AArch64RegDesc, 420, + RA, PC, + AArch64MCRegisterClasses, 43, + AArch64RegUnitRoots, 66, AArch64RegDiffLists, + AArch64RegStrings, + AArch64SubRegIdxLists, 53, + AArch64SubRegIdxRanges, + AArch64RegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420, + 0, 0, + AArch64MCRegisterClasses, 43, + 0, 0, AArch64RegDiffLists, + 0, + AArch64SubRegIdxLists, 53, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.h new file mode 100644 index 0000000..153dbca --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Disassembler.h @@ -0,0 +1,16 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_AARCH64_DISASSEMBLER_H +#define CS_AARCH64_DISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void AArch64_init(MCRegisterInfo *MRI); + +bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64GenAsmWriter.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenAsmWriter.inc new file mode 100644 index 0000000..69dea43 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenAsmWriter.inc @@ -0,0 +1,12611 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2694U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 2687U, // BUNDLE + 2704U, // LIFETIME_START + 2674U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 6182U, // ABSv16i8 + 553920550U, // ABSv1i64 + 1074272294U, // ABSv2i32 + 1611405350U, // ABSv2i64 + 2148538406U, // ABSv4i16 + 2685671462U, // ABSv4i32 + 3222804518U, // ABSv8i16 + 3759937574U, // ABSv8i8 + 17049662U, // ADCSWr + 17049662U, // ADCSXr + 17048298U, // ADCWr + 17048298U, // ADCXr + 537400863U, // ADDHNv2i64_v2i32 + 571748634U, // ADDHNv2i64_v4i32 + 1074796063U, // ADDHNv4i32_v4i16 + 1108881690U, // ADDHNv4i32_v8i16 + 1644179738U, // ADDHNv8i16_v16i8 + 1612453407U, // ADDHNv8i16_v8i8 + 2147489464U, // ADDPv16i8 + 2684884664U, // ADDPv2i32 + 537663160U, // ADDPv2i64 + 1610884792U, // ADDPv2i64p + 3222279864U, // ADDPv4i16 + 1075058360U, // ADDPv4i32 + 1612191416U, // ADDPv8i16 + 3759937208U, // ADDPv8i8 + 17049674U, // ADDSWri + 0U, // ADDSWrr + 17049674U, // ADDSWrs + 17049674U, // ADDSWrx + 17049674U, // ADDSXri + 0U, // ADDSXrr + 17049674U, // ADDSXrs + 17049674U, // ADDSXrx + 17049674U, // ADDSXrx64 + 272671U, // ADDVv16i8v + 2147756319U, // ADDVv4i16v + 2684627231U, // ADDVv4i32v + 3221498143U, // ADDVv8i16v + 3758369055U, // ADDVv8i8v + 17048359U, // ADDWri + 0U, // ADDWrr + 17048359U, // ADDWrs + 17048359U, // ADDWrx + 17048359U, // ADDXri + 0U, // ADDXrr + 17048359U, // ADDXrs + 17048359U, // ADDXrx + 17048359U, // ADDXrx64 + 2147488551U, // ADDv16i8 + 17048359U, // ADDv1i64 + 2684883751U, // ADDv2i32 + 537662247U, // ADDv2i64 + 3222278951U, // ADDv4i16 + 1075057447U, // ADDv4i32 + 1612190503U, // ADDv8i16 + 3759936295U, // ADDv8i8 + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 553920403U, // ADR + 50603811U, // ADRP + 33567598U, // AESDrr + 33567656U, // AESErr + 4852U, // AESIMCrr + 4860U, // AESMCrr + 17049680U, // ANDSWri + 0U, // ANDSWrr + 17049680U, // ANDSWrs + 17049680U, // ANDSXri + 0U, // ANDSXrr + 17049680U, // ANDSXrs + 17048425U, // ANDWri + 0U, // ANDWrr + 17048425U, // ANDWrs + 17048425U, // ANDXri + 0U, // ANDXrr + 17048425U, // ANDXrs + 2147488617U, // ANDv16i8 + 3759936361U, // ANDv8i8 + 17049553U, // ASRVWr + 17049553U, // ASRVXr + 16935U, // B + 67380710U, // BFMWri + 67380710U, // BFMXri + 0U, // BICSWrr + 17049668U, // BICSWrs + 0U, // BICSXrr + 17049668U, // BICSXrs + 0U, // BICWrr + 17048303U, // BICWrs + 0U, // BICXrr + 17048303U, // BICXrs + 2147488495U, // BICv16i8 + 84423407U, // BICv2i32 + 84947695U, // BICv4i16 + 85209839U, // BICv4i32 + 85471983U, // BICv8i16 + 3759936239U, // BICv8i8 + 2147488704U, // BIFv16i8 + 3759936448U, // BIFv8i8 + 2181052603U, // BITv16i8 + 3793500347U, // BITv8i8 + 17641U, // BL + 2107319U, // BLR + 2107279U, // BR + 21688U, // BRK + 2181051810U, // BSLv16i8 + 3793499554U, // BSLv8i8 + 27247U, // Bcc + 100936257U, // CBNZW + 100936257U, // CBNZX + 100936242U, // CBZW + 100936242U, // CBZX + 17049144U, // CCMNWi + 17049144U, // CCMNWr + 17049144U, // CCMNXi + 17049144U, // CCMNXr + 17049316U, // CCMPWi + 17049316U, // CCMPWr + 17049316U, // CCMPXi + 17049316U, // CCMPXr + 2107924U, // CLREX + 553920604U, // CLSWr + 553920604U, // CLSXr + 6236U, // CLSv16i8 + 1074272348U, // CLSv2i32 + 2148538460U, // CLSv4i16 + 2685671516U, // CLSv4i32 + 3222804572U, // CLSv8i16 + 3759937628U, // CLSv8i8 + 553921084U, // CLZWr + 553921084U, // CLZXr + 6716U, // CLZv16i8 + 1074272828U, // CLZv2i32 + 2148538940U, // CLZv4i16 + 2685671996U, // CLZv4i32 + 3222805052U, // CLZv8i16 + 3759938108U, // CLZv8i8 + 2147489643U, // CMEQv16i8 + 5995U, // CMEQv16i8rz + 17049451U, // CMEQv1i64 + 553920363U, // CMEQv1i64rz + 2684884843U, // CMEQv2i32 + 1074272107U, // CMEQv2i32rz + 537663339U, // CMEQv2i64 + 1611405163U, // CMEQv2i64rz + 3222280043U, // CMEQv4i16 + 2148538219U, // CMEQv4i16rz + 1075058539U, // CMEQv4i32 + 2685671275U, // CMEQv4i32rz + 1612191595U, // CMEQv8i16 + 3222804331U, // CMEQv8i16rz + 3759937387U, // CMEQv8i8 + 3759937387U, // CMEQv8i8rz + 2147488636U, // CMGEv16i8 + 4988U, // CMGEv16i8rz + 17048444U, // CMGEv1i64 + 553919356U, // CMGEv1i64rz + 2684883836U, // CMGEv2i32 + 1074271100U, // CMGEv2i32rz + 537662332U, // CMGEv2i64 + 1611404156U, // CMGEv2i64rz + 3222279036U, // CMGEv4i16 + 2148537212U, // CMGEv4i16rz + 1075057532U, // CMGEv4i32 + 2685670268U, // CMGEv4i32rz + 1612190588U, // CMGEv8i16 + 3222803324U, // CMGEv8i16rz + 3759936380U, // CMGEv8i8 + 3759936380U, // CMGEv8i8rz + 2147489972U, // CMGTv16i8 + 6324U, // CMGTv16i8rz + 17049780U, // CMGTv1i64 + 553920692U, // CMGTv1i64rz + 2684885172U, // CMGTv2i32 + 1074272436U, // CMGTv2i32rz + 537663668U, // CMGTv2i64 + 1611405492U, // CMGTv2i64rz + 3222280372U, // CMGTv4i16 + 2148538548U, // CMGTv4i16rz + 1075058868U, // CMGTv4i32 + 2685671604U, // CMGTv4i32rz + 1612191924U, // CMGTv8i16 + 3222804660U, // CMGTv8i16rz + 3759937716U, // CMGTv8i8 + 3759937716U, // CMGTv8i8rz + 2147488916U, // CMHIv16i8 + 17048724U, // CMHIv1i64 + 2684884116U, // CMHIv2i32 + 537662612U, // CMHIv2i64 + 3222279316U, // CMHIv4i16 + 1075057812U, // CMHIv4i32 + 1612190868U, // CMHIv8i16 + 3759936660U, // CMHIv8i8 + 2147489878U, // CMHSv16i8 + 17049686U, // CMHSv1i64 + 2684885078U, // CMHSv2i32 + 537663574U, // CMHSv2i64 + 3222280278U, // CMHSv4i16 + 1075058774U, // CMHSv4i32 + 1612191830U, // CMHSv8i16 + 3759937622U, // CMHSv8i8 + 4995U, // CMLEv16i8rz + 553919363U, // CMLEv1i64rz + 1074271107U, // CMLEv2i32rz + 1611404163U, // CMLEv2i64rz + 2148537219U, // CMLEv4i16rz + 2685670275U, // CMLEv4i32rz + 3222803331U, // CMLEv8i16rz + 3759936387U, // CMLEv8i8rz + 6342U, // CMLTv16i8rz + 553920710U, // CMLTv1i64rz + 1074272454U, // CMLTv2i32rz + 1611405510U, // CMLTv2i64rz + 2148538566U, // CMLTv4i16rz + 2685671622U, // CMLTv4i32rz + 3222804678U, // CMLTv8i16rz + 3759937734U, // CMLTv8i8rz + 2147490013U, // CMTSTv16i8 + 17049821U, // CMTSTv1i64 + 2684885213U, // CMTSTv2i32 + 537663709U, // CMTSTv2i64 + 3222280413U, // CMTSTv4i16 + 1075058909U, // CMTSTv4i32 + 1612191965U, // CMTSTv8i16 + 3759937757U, // CMTSTv8i8 + 6348U, // CNTv16i8 + 3759937740U, // CNTv8i8 + 272763U, // CPYi16 + 537143675U, // CPYi32 + 1074014587U, // CPYi64 + 1610885499U, // CPYi8 + 17048098U, // CRC32Brr + 17048106U, // CRC32CBrr + 17048575U, // CRC32CHrr + 17050039U, // CRC32CWrr + 17050123U, // CRC32CXrr + 17048558U, // CRC32Hrr + 17050017U, // CRC32Wrr + 17050092U, // CRC32Xrr + 17048888U, // CSELWr + 17048888U, // CSELXr + 17048323U, // CSINCWr + 17048323U, // CSINCXr + 17049971U, // CSINVWr + 17049971U, // CSINVXr + 17048544U, // CSNEGWr + 17048544U, // CSNEGXr + 20524U, // DCPS1 + 20889U, // DCPS2 + 20938U, // DCPS3 + 29235U, // DMB + 2719U, // DRPS + 29324U, // DSB + 553654070U, // DUPv16i8gpr + 1610618678U, // DUPv16i8lane + 554178358U, // DUPv2i32gpr + 537401142U, // DUPv2i32lane + 554440502U, // DUPv2i64gpr + 1074534198U, // DUPv2i64lane + 554702646U, // DUPv4i16gpr + 1054518U, // DUPv4i16lane + 554964790U, // DUPv4i32gpr + 538187574U, // DUPv4i32lane + 555226934U, // DUPv8i16gpr + 1578806U, // DUPv8i16lane + 555489078U, // DUPv8i8gpr + 1612453686U, // DUPv8i8lane + 0U, // EONWrr + 17049150U, // EONWrs + 0U, // EONXrr + 17049150U, // EONXrs + 17049538U, // EORWri + 0U, // EORWrr + 17049538U, // EORWrs + 17049538U, // EORXri + 0U, // EORXrr + 17049538U, // EORXrs + 2147489730U, // EORv16i8 + 3759937474U, // EORv8i8 + 2724U, // ERET + 17049585U, // EXTRWrri + 17049585U, // EXTRXrri + 2147490026U, // EXTv16i8 + 3759937770U, // EXTv8i8 + 0U, // F128CSEL + 17048340U, // FABD32 + 17048340U, // FABD64 + 2684883732U, // FABDv2f32 + 537662228U, // FABDv2f64 + 1075057428U, // FABDv4f32 + 553920549U, // FABSDr + 553920549U, // FABSSr + 1074272293U, // FABSv2f32 + 1611405349U, // FABSv2f64 + 2685671461U, // FABSv4f32 + 17048436U, // FACGE32 + 17048436U, // FACGE64 + 2684883828U, // FACGEv2f32 + 537662324U, // FACGEv2f64 + 1075057524U, // FACGEv4f32 + 17049772U, // FACGT32 + 17049772U, // FACGT64 + 2684885164U, // FACGTv2f32 + 537663660U, // FACGTv2f64 + 1075058860U, // FACGTv4f32 + 17048358U, // FADDDrr + 2684884663U, // FADDPv2f32 + 537663159U, // FADDPv2f64 + 1074013879U, // FADDPv2i32p + 1610884791U, // FADDPv2i64p + 1075058359U, // FADDPv4f32 + 17048358U, // FADDSrr + 2684883750U, // FADDv2f32 + 537662246U, // FADDv2f64 + 1075057446U, // FADDv4f32 + 17049315U, // FCCMPDrr + 17048473U, // FCCMPEDrr + 17048473U, // FCCMPESrr + 17049315U, // FCCMPSrr + 17049450U, // FCMEQ32 + 17049450U, // FCMEQ64 + 2164533098U, // FCMEQv1i32rz + 2164533098U, // FCMEQv1i64rz + 2684884842U, // FCMEQv2f32 + 537663338U, // FCMEQv2f64 + 2684884842U, // FCMEQv2i32rz + 3222017898U, // FCMEQv2i64rz + 1075058538U, // FCMEQv4f32 + 3759413098U, // FCMEQv4i32rz + 17048443U, // FCMGE32 + 17048443U, // FCMGE64 + 2164532091U, // FCMGEv1i32rz + 2164532091U, // FCMGEv1i64rz + 2684883835U, // FCMGEv2f32 + 537662331U, // FCMGEv2f64 + 2684883835U, // FCMGEv2i32rz + 3222016891U, // FCMGEv2i64rz + 1075057531U, // FCMGEv4f32 + 3759412091U, // FCMGEv4i32rz + 17049779U, // FCMGT32 + 17049779U, // FCMGT64 + 2164533427U, // FCMGTv1i32rz + 2164533427U, // FCMGTv1i64rz + 2684885171U, // FCMGTv2f32 + 537663667U, // FCMGTv2f64 + 2684885171U, // FCMGTv2i32rz + 3222018227U, // FCMGTv2i64rz + 1075058867U, // FCMGTv4f32 + 3759413427U, // FCMGTv4i32rz + 2164532098U, // FCMLEv1i32rz + 2164532098U, // FCMLEv1i64rz + 2684883842U, // FCMLEv2i32rz + 3222016898U, // FCMLEv2i64rz + 3759412098U, // FCMLEv4i32rz + 2164533445U, // FCMLTv1i32rz + 2164533445U, // FCMLTv1i64rz + 2684885189U, // FCMLTv2i32rz + 3222018245U, // FCMLTv2i64rz + 3759413445U, // FCMLTv4i32rz + 2369258U, // FCMPDri + 553920234U, // FCMPDrr + 2368417U, // FCMPEDri + 553919393U, // FCMPEDrr + 2368417U, // FCMPESri + 553919393U, // FCMPESrr + 2369258U, // FCMPSri + 553920234U, // FCMPSrr + 17048887U, // FCSELDrrr + 17048887U, // FCSELSrrr + 553920541U, // FCVTASUWDr + 553920541U, // FCVTASUWSr + 553920541U, // FCVTASUXDr + 553920541U, // FCVTASUXSr + 553920541U, // FCVTASv1i32 + 553920541U, // FCVTASv1i64 + 1074272285U, // FCVTASv2f32 + 1611405341U, // FCVTASv2f64 + 2685671453U, // FCVTASv4f32 + 553920751U, // FCVTAUUWDr + 553920751U, // FCVTAUUWSr + 553920751U, // FCVTAUUXDr + 553920751U, // FCVTAUUXSr + 553920751U, // FCVTAUv1i32 + 553920751U, // FCVTAUv1i64 + 1074272495U, // FCVTAUv2f32 + 1611405551U, // FCVTAUv2f64 + 2685671663U, // FCVTAUv4f32 + 553920740U, // FCVTDHr + 553920740U, // FCVTDSr + 553920740U, // FCVTHDr + 553920740U, // FCVTHSr + 1074533828U, // FCVTLv2i32 + 2148799940U, // FCVTLv4i16 + 2685145352U, // FCVTLv4i32 + 3222540552U, // FCVTLv8i16 + 553920615U, // FCVTMSUWDr + 553920615U, // FCVTMSUWSr + 553920615U, // FCVTMSUXDr + 553920615U, // FCVTMSUXSr + 553920615U, // FCVTMSv1i32 + 553920615U, // FCVTMSv1i64 + 1074272359U, // FCVTMSv2f32 + 1611405415U, // FCVTMSv2f64 + 2685671527U, // FCVTMSv4f32 + 553920767U, // FCVTMUUWDr + 553920767U, // FCVTMUUWSr + 553920767U, // FCVTMUUXDr + 553920767U, // FCVTMUUXSr + 553920767U, // FCVTMUv1i32 + 553920767U, // FCVTMUv1i64 + 1074272511U, // FCVTMUv2f32 + 1611405567U, // FCVTMUv2f64 + 2685671679U, // FCVTMUv4f32 + 553920628U, // FCVTNSUWDr + 553920628U, // FCVTNSUWSr + 553920628U, // FCVTNSUXDr + 553920628U, // FCVTNSUXSr + 553920628U, // FCVTNSv1i32 + 553920628U, // FCVTNSv1i64 + 1074272372U, // FCVTNSv2f32 + 1611405428U, // FCVTNSv2f64 + 2685671540U, // FCVTNSv4f32 + 553920775U, // FCVTNUUWDr + 553920775U, // FCVTNUUWSr + 553920775U, // FCVTNUUXDr + 553920775U, // FCVTNUUXSr + 553920775U, // FCVTNUv1i32 + 553920775U, // FCVTNUv1i64 + 1074272519U, // FCVTNUv2f32 + 1611405575U, // FCVTNUv2f64 + 2685671687U, // FCVTNUv4f32 + 1611142770U, // FCVTNv2i32 + 2685408882U, // FCVTNv4i16 + 1645490510U, // FCVTNv4i32 + 2719494478U, // FCVTNv8i16 + 553920644U, // FCVTPSUWDr + 553920644U, // FCVTPSUWSr + 553920644U, // FCVTPSUXDr + 553920644U, // FCVTPSUXSr + 553920644U, // FCVTPSv1i32 + 553920644U, // FCVTPSv1i64 + 1074272388U, // FCVTPSv2f32 + 1611405444U, // FCVTPSv2f64 + 2685671556U, // FCVTPSv4f32 + 553920783U, // FCVTPUUWDr + 553920783U, // FCVTPUUWSr + 553920783U, // FCVTPUUXDr + 553920783U, // FCVTPUUXSr + 553920783U, // FCVTPUv1i32 + 553920783U, // FCVTPUv1i64 + 1074272527U, // FCVTPUv2f32 + 1611405583U, // FCVTPUv2f64 + 2685671695U, // FCVTPUv4f32 + 553920740U, // FCVTSDr + 553920740U, // FCVTSHr + 553920168U, // FCVTXNv1i64 + 1611142824U, // FCVTXNv2f32 + 1645490564U, // FCVTXNv4f32 + 17049759U, // FCVTZSSWDri + 17049759U, // FCVTZSSWSri + 17049759U, // FCVTZSSXDri + 17049759U, // FCVTZSSXSri + 553920671U, // FCVTZSUWDr + 553920671U, // FCVTZSUWSr + 553920671U, // FCVTZSUXDr + 553920671U, // FCVTZSUXSr + 17049759U, // FCVTZS_IntSWDri + 17049759U, // FCVTZS_IntSWSri + 17049759U, // FCVTZS_IntSXDri + 17049759U, // FCVTZS_IntSXSri + 553920671U, // FCVTZS_IntUWDr + 553920671U, // FCVTZS_IntUWSr + 553920671U, // FCVTZS_IntUXDr + 553920671U, // FCVTZS_IntUXSr + 1074272415U, // FCVTZS_Intv2f32 + 1611405471U, // FCVTZS_Intv2f64 + 2685671583U, // FCVTZS_Intv4f32 + 17049759U, // FCVTZSd + 17049759U, // FCVTZSs + 553920671U, // FCVTZSv1i32 + 553920671U, // FCVTZSv1i64 + 1074272415U, // FCVTZSv2f32 + 1611405471U, // FCVTZSv2f64 + 2684885151U, // FCVTZSv2i32_shift + 537663647U, // FCVTZSv2i64_shift + 2685671583U, // FCVTZSv4f32 + 1075058847U, // FCVTZSv4i32_shift + 17049879U, // FCVTZUSWDri + 17049879U, // FCVTZUSWSri + 17049879U, // FCVTZUSXDri + 17049879U, // FCVTZUSXSri + 553920791U, // FCVTZUUWDr + 553920791U, // FCVTZUUWSr + 553920791U, // FCVTZUUXDr + 553920791U, // FCVTZUUXSr + 17049879U, // FCVTZU_IntSWDri + 17049879U, // FCVTZU_IntSWSri + 17049879U, // FCVTZU_IntSXDri + 17049879U, // FCVTZU_IntSXSri + 553920791U, // FCVTZU_IntUWDr + 553920791U, // FCVTZU_IntUWSr + 553920791U, // FCVTZU_IntUXDr + 553920791U, // FCVTZU_IntUXSr + 1074272535U, // FCVTZU_Intv2f32 + 1611405591U, // FCVTZU_Intv2f64 + 2685671703U, // FCVTZU_Intv4f32 + 17049879U, // FCVTZUd + 17049879U, // FCVTZUs + 553920791U, // FCVTZUv1i32 + 553920791U, // FCVTZUv1i64 + 1074272535U, // FCVTZUv2f32 + 1611405591U, // FCVTZUv2f64 + 2684885271U, // FCVTZUv2i32_shift + 537663767U, // FCVTZUv2i64_shift + 2685671703U, // FCVTZUv4f32 + 1075058967U, // FCVTZUv4i32_shift + 17049898U, // FDIVDrr + 17049898U, // FDIVSrr + 2684885290U, // FDIVv2f32 + 537663786U, // FDIVv2f64 + 1075058986U, // FDIVv4f32 + 17048394U, // FMADDDrrr + 17048394U, // FMADDSrrr + 17050100U, // FMAXDrr + 17049087U, // FMAXNMDrr + 2684884729U, // FMAXNMPv2f32 + 537663225U, // FMAXNMPv2f64 + 1074013945U, // FMAXNMPv2i32p + 1610884857U, // FMAXNMPv2i64p + 1075058425U, // FMAXNMPv4f32 + 17049087U, // FMAXNMSrr + 2684627285U, // FMAXNMVv4i32v + 2684884479U, // FMAXNMv2f32 + 537662975U, // FMAXNMv2f64 + 1075058175U, // FMAXNMv4f32 + 2684884802U, // FMAXPv2f32 + 537663298U, // FMAXPv2f64 + 1074014018U, // FMAXPv2i32p + 1610884930U, // FMAXPv2i64p + 1075058498U, // FMAXPv4f32 + 17050100U, // FMAXSrr + 2684627340U, // FMAXVv4i32v + 2684885492U, // FMAXv2f32 + 537663988U, // FMAXv2f64 + 1075059188U, // FMAXv4f32 + 17049126U, // FMINDrr + 17049079U, // FMINNMDrr + 2684884720U, // FMINNMPv2f32 + 537663216U, // FMINNMPv2f64 + 1074013936U, // FMINNMPv2i32p + 1610884848U, // FMINNMPv2i64p + 1075058416U, // FMINNMPv4f32 + 17049079U, // FMINNMSrr + 2684627276U, // FMINNMVv4i32v + 2684884471U, // FMINNMv2f32 + 537662967U, // FMINNMv2f64 + 1075058167U, // FMINNMv4f32 + 2684884744U, // FMINPv2f32 + 537663240U, // FMINPv2f64 + 1074013960U, // FMINPv2i32p + 1610884872U, // FMINPv2i64p + 1075058440U, // FMINPv4f32 + 17049126U, // FMINSrr + 2684627294U, // FMINVv4i32v + 2684884518U, // FMINv2f32 + 537663014U, // FMINv2f64 + 1075058214U, // FMINv4f32 + 67404282U, // FMLAv1i32_indexed + 67404282U, // FMLAv1i64_indexed + 2718446074U, // FMLAv2f32 + 571224570U, // FMLAv2f64 + 2718446074U, // FMLAv2i32_indexed + 571224570U, // FMLAv2i64_indexed + 1108619770U, // FMLAv4f32 + 1108619770U, // FMLAv4i32_indexed + 67405921U, // FMLSv1i32_indexed + 67405921U, // FMLSv1i64_indexed + 2718447713U, // FMLSv2f32 + 571226209U, // FMLSv2f64 + 2718447713U, // FMLSv2i32_indexed + 571226209U, // FMLSv2i64_indexed + 1108621409U, // FMLSv4f32 + 1108621409U, // FMLSv4i32_indexed + 1074014586U, // FMOVDXHighr + 553920890U, // FMOVDXr + 117713274U, // FMOVDi + 553920890U, // FMOVDr + 553920890U, // FMOVSWr + 117713274U, // FMOVSi + 553920890U, // FMOVSr + 553920890U, // FMOVWSr + 556276090U, // FMOVXDHighr + 553920890U, // FMOVXDr + 117971322U, // FMOVv2f32_ns + 118233466U, // FMOVv2f64_ns + 118757754U, // FMOVv4f32_ns + 17048257U, // FMSUBDrrr + 17048257U, // FMSUBSrrr + 17049035U, // FMULDrr + 17049035U, // FMULSrr + 17050139U, // FMULX32 + 17050139U, // FMULX64 + 17050139U, // FMULXv1i32_indexed + 17050139U, // FMULXv1i64_indexed + 2684885531U, // FMULXv2f32 + 537664027U, // FMULXv2f64 + 2684885531U, // FMULXv2i32_indexed + 537664027U, // FMULXv2i64_indexed + 1075059227U, // FMULXv4f32 + 1075059227U, // FMULXv4i32_indexed + 17049035U, // FMULv1i32_indexed + 17049035U, // FMULv1i64_indexed + 2684884427U, // FMULv2f32 + 537662923U, // FMULv2f64 + 2684884427U, // FMULv2i32_indexed + 537662923U, // FMULv2i64_indexed + 1075058123U, // FMULv4f32 + 1075058123U, // FMULv4i32_indexed + 553919443U, // FNEGDr + 553919443U, // FNEGSr + 1074271187U, // FNEGv2f32 + 1611404243U, // FNEGv2f64 + 2685670355U, // FNEGv4f32 + 17048401U, // FNMADDDrrr + 17048401U, // FNMADDSrrr + 17048264U, // FNMSUBDrrr + 17048264U, // FNMSUBSrrr + 17049041U, // FNMULDrr + 17049041U, // FNMULSrr + 553919369U, // FRECPEv1i32 + 553919369U, // FRECPEv1i64 + 1074271113U, // FRECPEv2f32 + 1611404169U, // FRECPEv2f64 + 2685670281U, // FRECPEv4f32 + 17049724U, // FRECPS32 + 17049724U, // FRECPS64 + 2684885116U, // FRECPSv2f32 + 537663612U, // FRECPSv2f64 + 1075058812U, // FRECPSv4f32 + 553921058U, // FRECPXv1i32 + 553921058U, // FRECPXv1i64 + 553919002U, // FRINTADr + 553919002U, // FRINTASr + 1074270746U, // FRINTAv2f32 + 1611403802U, // FRINTAv2f64 + 2685669914U, // FRINTAv4f32 + 553919658U, // FRINTIDr + 553919658U, // FRINTISr + 1074271402U, // FRINTIv2f32 + 1611404458U, // FRINTIv2f64 + 2685670570U, // FRINTIv4f32 + 553920007U, // FRINTMDr + 553920007U, // FRINTMSr + 1074271751U, // FRINTMv2f32 + 1611404807U, // FRINTMv2f64 + 2685670919U, // FRINTMv4f32 + 553920106U, // FRINTNDr + 553920106U, // FRINTNSr + 1074271850U, // FRINTNv2f32 + 1611404906U, // FRINTNv2f64 + 2685671018U, // FRINTNv4f32 + 553920297U, // FRINTPDr + 553920297U, // FRINTPSr + 1074272041U, // FRINTPv2f32 + 1611405097U, // FRINTPv2f64 + 2685671209U, // FRINTPv4f32 + 553921066U, // FRINTXDr + 553921066U, // FRINTXSr + 1074272810U, // FRINTXv2f32 + 1611405866U, // FRINTXv2f64 + 2685671978U, // FRINTXv4f32 + 553921101U, // FRINTZDr + 553921101U, // FRINTZSr + 1074272845U, // FRINTZv2f32 + 1611405901U, // FRINTZv2f64 + 2685672013U, // FRINTZv4f32 + 553919406U, // FRSQRTEv1i32 + 553919406U, // FRSQRTEv1i64 + 1074271150U, // FRSQRTEv2f32 + 1611404206U, // FRSQRTEv2f64 + 2685670318U, // FRSQRTEv4f32 + 17049745U, // FRSQRTS32 + 17049745U, // FRSQRTS64 + 2684885137U, // FRSQRTSv2f32 + 537663633U, // FRSQRTSv2f64 + 1075058833U, // FRSQRTSv4f32 + 553920726U, // FSQRTDr + 553920726U, // FSQRTSr + 1074272470U, // FSQRTv2f32 + 1611405526U, // FSQRTv2f64 + 2685671638U, // FSQRTv4f32 + 17048237U, // FSUBDrr + 17048237U, // FSUBSrr + 2684883629U, // FSUBv2f32 + 537662125U, // FSUBv2f64 + 1075057325U, // FSUBv4f32 + 23145U, // HINT + 22720U, // HLT + 21258U, // HVC + 137115759U, // INSvi16gpr + 153892975U, // INSvi16lane + 137377903U, // INSvi32gpr + 691026031U, // INSvi32lane + 136853615U, // INSvi64gpr + 1227372655U, // INSvi64lane + 137640047U, // INSvi8gpr + 1765029999U, // INSvi8lane + 29329U, // ISB + 36885U, // LD1Fourv16b + 3710997U, // LD1Fourv16b_POST + 45077U, // LD1Fourv1d + 3981333U, // LD1Fourv1d_POST + 53269U, // LD1Fourv2d + 3727381U, // LD1Fourv2d_POST + 61461U, // LD1Fourv2s + 3997717U, // LD1Fourv2s_POST + 69653U, // LD1Fourv4h + 4005909U, // LD1Fourv4h_POST + 77845U, // LD1Fourv4s + 3751957U, // LD1Fourv4s_POST + 86037U, // LD1Fourv8b + 4022293U, // LD1Fourv8b_POST + 94229U, // LD1Fourv8h + 3768341U, // LD1Fourv8h_POST + 36885U, // LD1Onev16b + 4235285U, // LD1Onev16b_POST + 45077U, // LD1Onev1d + 4505621U, // LD1Onev1d_POST + 53269U, // LD1Onev2d + 4251669U, // LD1Onev2d_POST + 61461U, // LD1Onev2s + 4522005U, // LD1Onev2s_POST + 69653U, // LD1Onev4h + 4530197U, // LD1Onev4h_POST + 77845U, // LD1Onev4s + 4276245U, // LD1Onev4s_POST + 86037U, // LD1Onev8b + 4546581U, // LD1Onev8b_POST + 94229U, // LD1Onev8h + 4292629U, // LD1Onev8h_POST + 38769U, // LD1Rv16b + 4761457U, // LD1Rv16b_POST + 46961U, // LD1Rv1d + 4507505U, // LD1Rv1d_POST + 55153U, // LD1Rv2d + 4515697U, // LD1Rv2d_POST + 63345U, // LD1Rv2s + 5048177U, // LD1Rv2s_POST + 71537U, // LD1Rv4h + 5318513U, // LD1Rv4h_POST + 79729U, // LD1Rv4s + 5064561U, // LD1Rv4s_POST + 87921U, // LD1Rv8b + 4810609U, // LD1Rv8b_POST + 96113U, // LD1Rv8h + 5343089U, // LD1Rv8h_POST + 36885U, // LD1Threev16b + 5546005U, // LD1Threev16b_POST + 45077U, // LD1Threev1d + 5816341U, // LD1Threev1d_POST + 53269U, // LD1Threev2d + 5562389U, // LD1Threev2d_POST + 61461U, // LD1Threev2s + 5832725U, // LD1Threev2s_POST + 69653U, // LD1Threev4h + 5840917U, // LD1Threev4h_POST + 77845U, // LD1Threev4s + 5586965U, // LD1Threev4s_POST + 86037U, // LD1Threev8b + 5857301U, // LD1Threev8b_POST + 94229U, // LD1Threev8h + 5603349U, // LD1Threev8h_POST + 36885U, // LD1Twov16b + 3973141U, // LD1Twov16b_POST + 45077U, // LD1Twov1d + 4243477U, // LD1Twov1d_POST + 53269U, // LD1Twov2d + 3989525U, // LD1Twov2d_POST + 61461U, // LD1Twov2s + 4259861U, // LD1Twov2s_POST + 69653U, // LD1Twov4h + 4268053U, // LD1Twov4h_POST + 77845U, // LD1Twov4s + 4014101U, // LD1Twov4s_POST + 86037U, // LD1Twov8b + 4284437U, // LD1Twov8b_POST + 94229U, // LD1Twov8h + 4030485U, // LD1Twov8h_POST + 6131733U, // LD1i16 + 6397973U, // LD1i16_POST + 6139925U, // LD1i32 + 6668309U, // LD1i32_POST + 6148117U, // LD1i64 + 6938645U, // LD1i64_POST + 6156309U, // LD1i8 + 7208981U, // LD1i8_POST + 38775U, // LD2Rv16b + 5285751U, // LD2Rv16b_POST + 46967U, // LD2Rv1d + 4245367U, // LD2Rv1d_POST + 55159U, // LD2Rv2d + 4253559U, // LD2Rv2d_POST + 63351U, // LD2Rv2s + 4523895U, // LD2Rv2s_POST + 71543U, // LD2Rv4h + 5056375U, // LD2Rv4h_POST + 79735U, // LD2Rv4s + 4540279U, // LD2Rv4s_POST + 87927U, // LD2Rv8b + 5334903U, // LD2Rv8b_POST + 96119U, // LD2Rv8h + 5080951U, // LD2Rv8h_POST + 36947U, // LD2Twov16b + 3973203U, // LD2Twov16b_POST + 53331U, // LD2Twov2d + 3989587U, // LD2Twov2d_POST + 61523U, // LD2Twov2s + 4259923U, // LD2Twov2s_POST + 69715U, // LD2Twov4h + 4268115U, // LD2Twov4h_POST + 77907U, // LD2Twov4s + 4014163U, // LD2Twov4s_POST + 86099U, // LD2Twov8b + 4284499U, // LD2Twov8b_POST + 94291U, // LD2Twov8h + 4030547U, // LD2Twov8h_POST + 6131795U, // LD2i16 + 6660179U, // LD2i16_POST + 6139987U, // LD2i32 + 6930515U, // LD2i32_POST + 6148179U, // LD2i64 + 7462995U, // LD2i64_POST + 6156371U, // LD2i8 + 6422611U, // LD2i8_POST + 38781U, // LD3Rv16b + 7645053U, // LD3Rv16b_POST + 46973U, // LD3Rv1d + 5818237U, // LD3Rv1d_POST + 55165U, // LD3Rv2d + 5826429U, // LD3Rv2d_POST + 63357U, // LD3Rv2s + 7931773U, // LD3Rv2s_POST + 71549U, // LD3Rv4h + 8202109U, // LD3Rv4h_POST + 79741U, // LD3Rv4s + 7948157U, // LD3Rv4s_POST + 87933U, // LD3Rv8b + 7694205U, // LD3Rv8b_POST + 96125U, // LD3Rv8h + 8226685U, // LD3Rv8h_POST + 37317U, // LD3Threev16b + 5546437U, // LD3Threev16b_POST + 53701U, // LD3Threev2d + 5562821U, // LD3Threev2d_POST + 61893U, // LD3Threev2s + 5833157U, // LD3Threev2s_POST + 70085U, // LD3Threev4h + 5841349U, // LD3Threev4h_POST + 78277U, // LD3Threev4s + 5587397U, // LD3Threev4s_POST + 86469U, // LD3Threev8b + 5857733U, // LD3Threev8b_POST + 94661U, // LD3Threev8h + 5603781U, // LD3Threev8h_POST + 6132165U, // LD3i16 + 8495557U, // LD3i16_POST + 6140357U, // LD3i32 + 8765893U, // LD3i32_POST + 6148549U, // LD3i64 + 9036229U, // LD3i64_POST + 6156741U, // LD3i8 + 9306565U, // LD3i8_POST + 37341U, // LD4Fourv16b + 3711453U, // LD4Fourv16b_POST + 53725U, // LD4Fourv2d + 3727837U, // LD4Fourv2d_POST + 61917U, // LD4Fourv2s + 3998173U, // LD4Fourv2s_POST + 70109U, // LD4Fourv4h + 4006365U, // LD4Fourv4h_POST + 78301U, // LD4Fourv4s + 3752413U, // LD4Fourv4s_POST + 86493U, // LD4Fourv8b + 4022749U, // LD4Fourv8b_POST + 94685U, // LD4Fourv8h + 3768797U, // LD4Fourv8h_POST + 38787U, // LD4Rv16b + 5023619U, // LD4Rv16b_POST + 46979U, // LD4Rv1d + 3983235U, // LD4Rv1d_POST + 55171U, // LD4Rv2d + 3991427U, // LD4Rv2d_POST + 63363U, // LD4Rv2s + 4261763U, // LD4Rv2s_POST + 71555U, // LD4Rv4h + 4532099U, // LD4Rv4h_POST + 79747U, // LD4Rv4s + 4278147U, // LD4Rv4s_POST + 87939U, // LD4Rv8b + 5072771U, // LD4Rv8b_POST + 96131U, // LD4Rv8h + 4556675U, // LD4Rv8h_POST + 6132189U, // LD4i16 + 6922717U, // LD4i16_POST + 6140381U, // LD4i32 + 7455197U, // LD4i32_POST + 6148573U, // LD4i64 + 9560541U, // LD4i64_POST + 6156765U, // LD4i8 + 6685149U, // LD4i8_POST + 26485304U, // LDARB + 26485801U, // LDARH + 26486665U, // LDARW + 26486665U, // LDARX + 553920315U, // LDAXPW + 553920315U, // LDAXPX + 26485358U, // LDAXRB + 26485855U, // LDAXRH + 26486787U, // LDAXRW + 26486787U, // LDAXRX + 553920258U, // LDNPDi + 553920258U, // LDNPQi + 553920258U, // LDNPSi + 553920258U, // LDNPWi + 553920258U, // LDNPXi + 553920190U, // LDPDi + 604276414U, // LDPDpost + 604276414U, // LDPDpre + 553920190U, // LDPQi + 604276414U, // LDPQpost + 604276414U, // LDPQpre + 553920974U, // LDPSWi + 604277198U, // LDPSWpost + 604277198U, // LDPSWpre + 553920190U, // LDPSi + 604276414U, // LDPSpost + 604276414U, // LDPSpre + 553920190U, // LDPWi + 604276414U, // LDPWpost + 604276414U, // LDPWpre + 553920190U, // LDPXi + 604276414U, // LDPXpost + 604276414U, // LDPXpre + 1150583359U, // LDRBBpost + 76841535U, // LDRBBpre + 26485311U, // LDRBBroW + 26485311U, // LDRBBroX + 26485311U, // LDRBBui + 1150584728U, // LDRBpost + 76842904U, // LDRBpre + 26486680U, // LDRBroW + 26486680U, // LDRBroX + 26486680U, // LDRBui + 100935576U, // LDRDl + 1150584728U, // LDRDpost + 76842904U, // LDRDpre + 26486680U, // LDRDroW + 26486680U, // LDRDroX + 26486680U, // LDRDui + 1150583856U, // LDRHHpost + 76842032U, // LDRHHpre + 26485808U, // LDRHHroW + 26485808U, // LDRHHroX + 26485808U, // LDRHHui + 1150584728U, // LDRHpost + 76842904U, // LDRHpre + 26486680U, // LDRHroW + 26486680U, // LDRHroX + 26486680U, // LDRHui + 100935576U, // LDRQl + 1150584728U, // LDRQpost + 76842904U, // LDRQpre + 26486680U, // LDRQroW + 26486680U, // LDRQroX + 26486680U, // LDRQui + 1150583446U, // LDRSBWpost + 76841622U, // LDRSBWpre + 26485398U, // LDRSBWroW + 26485398U, // LDRSBWroX + 26485398U, // LDRSBWui + 1150583446U, // LDRSBXpost + 76841622U, // LDRSBXpre + 26485398U, // LDRSBXroW + 26485398U, // LDRSBXroX + 26485398U, // LDRSBXui + 1150583933U, // LDRSHWpost + 76842109U, // LDRSHWpre + 26485885U, // LDRSHWroW + 26485885U, // LDRSHWroX + 26485885U, // LDRSHWui + 1150583933U, // LDRSHXpost + 76842109U, // LDRSHXpre + 26485885U, // LDRSHXroW + 26485885U, // LDRSHXroX + 26485885U, // LDRSHXui + 100936149U, // LDRSWl + 1150585301U, // LDRSWpost + 76843477U, // LDRSWpre + 26487253U, // LDRSWroW + 26487253U, // LDRSWroX + 26487253U, // LDRSWui + 100935576U, // LDRSl + 1150584728U, // LDRSpost + 76842904U, // LDRSpre + 26486680U, // LDRSroW + 26486680U, // LDRSroX + 26486680U, // LDRSui + 100935576U, // LDRWl + 1150584728U, // LDRWpost + 76842904U, // LDRWpre + 26486680U, // LDRWroW + 26486680U, // LDRWroX + 26486680U, // LDRWui + 100935576U, // LDRXl + 1150584728U, // LDRXpost + 76842904U, // LDRXpre + 26486680U, // LDRXroW + 26486680U, // LDRXroX + 26486680U, // LDRXui + 26485324U, // LDTRBi + 26485821U, // LDTRHi + 26485405U, // LDTRSBWi + 26485405U, // LDTRSBXi + 26485892U, // LDTRSHWi + 26485892U, // LDTRSHXi + 26487260U, // LDTRSWi + 26486752U, // LDTRWi + 26486752U, // LDTRXi + 26485344U, // LDURBBi + 26486775U, // LDURBi + 26486775U, // LDURDi + 26485841U, // LDURHHi + 26486775U, // LDURHi + 26486775U, // LDURQi + 26485413U, // LDURSBWi + 26485413U, // LDURSBXi + 26485900U, // LDURSHWi + 26485900U, // LDURSHXi + 26487268U, // LDURSWi + 26486775U, // LDURSi + 26486775U, // LDURWi + 26486775U, // LDURXi + 553920343U, // LDXPW + 553920343U, // LDXPX + 26485366U, // LDXRB + 26485863U, // LDXRH + 26486794U, // LDXRW + 26486794U, // LDXRX + 0U, // LOADgot + 17049003U, // LSLVWr + 17049003U, // LSLVXr + 17049558U, // LSRVWr + 17049558U, // LSRVXr + 17048395U, // MADDWrrr + 17048395U, // MADDXrrr + 2181050875U, // MLAv16i8 + 2718446075U, // MLAv2i32 + 2718446075U, // MLAv2i32_indexed + 3255841275U, // MLAv4i16 + 3255841275U, // MLAv4i16_indexed + 1108619771U, // MLAv4i32 + 1108619771U, // MLAv4i32_indexed + 1645752827U, // MLAv8i16 + 1645752827U, // MLAv8i16_indexed + 3793498619U, // MLAv8i8 + 2181052514U, // MLSv16i8 + 2718447714U, // MLSv2i32 + 2718447714U, // MLSv2i32_indexed + 3255842914U, // MLSv4i16 + 3255842914U, // MLSv4i16_indexed + 1108621410U, // MLSv4i32 + 1108621410U, // MLSv4i32_indexed + 1645754466U, // MLSv8i16 + 1645754466U, // MLSv8i16_indexed + 3793500258U, // MLSv8i8 + 168043698U, // MOVID + 721425586U, // MOVIv16b_ns + 168563890U, // MOVIv2d_ns + 1795691698U, // MOVIv2i32 + 1795691698U, // MOVIv2s_msl + 1796215986U, // MOVIv4i16 + 1796478130U, // MOVIv4i32 + 1796478130U, // MOVIv4s_msl + 723260594U, // MOVIv8b_ns + 1796740274U, // MOVIv8i16 + 84157629U, // MOVKWi + 84157629U, // MOVKXi + 1795434146U, // MOVNWi + 1795434146U, // MOVNXi + 1795435093U, // MOVZWi + 1795435093U, // MOVZXi + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 201599116U, // MRS + 137179U, // MSR + 141275U, // MSRpstate + 17048258U, // MSUBWrrr + 17048258U, // MSUBXrrr + 2147489228U, // MULv16i8 + 2684884428U, // MULv2i32 + 2684884428U, // MULv2i32_indexed + 3222279628U, // MULv4i16 + 3222279628U, // MULv4i16_indexed + 1075058124U, // MULv4i32 + 1075058124U, // MULv4i32_indexed + 1612191180U, // MULv8i16 + 1612191180U, // MULv8i16_indexed + 3759936972U, // MULv8i8 + 1795691679U, // MVNIv2i32 + 1795691679U, // MVNIv2s_msl + 1796215967U, // MVNIv4i16 + 1796478111U, // MVNIv4i32 + 1796478111U, // MVNIv4s_msl + 1796740255U, // MVNIv8i16 + 5076U, // NEGv16i8 + 553919444U, // NEGv1i64 + 1074271188U, // NEGv2i32 + 1611404244U, // NEGv2i64 + 2148537300U, // NEGv4i16 + 2685670356U, // NEGv4i32 + 3222803412U, // NEGv8i16 + 3759936468U, // NEGv8i8 + 6353U, // NOTv16i8 + 3759937745U, // NOTv8i8 + 0U, // ORNWrr + 17049189U, // ORNWrs + 0U, // ORNXrr + 17049189U, // ORNXrs + 2147489381U, // ORNv16i8 + 3759937125U, // ORNv8i8 + 17049548U, // ORRWri + 0U, // ORRWrr + 17049548U, // ORRWrs + 17049548U, // ORRXri + 0U, // ORRXrr + 17049548U, // ORRXrs + 2147489740U, // ORRv16i8 + 84424652U, // ORRv2i32 + 84948940U, // ORRv4i16 + 85211084U, // ORRv4i32 + 85473228U, // ORRv8i16 + 3759937484U, // ORRv8i8 + 2149060822U, // PMULLv16i8 + 228070797U, // PMULLv1i64 + 244846806U, // PMULLv2i64 + 3759674765U, // PMULLv8i8 + 2147489240U, // PMULv16i8 + 3759936984U, // PMULv8i8 + 101070321U, // PRFMl + 26621425U, // PRFMroW + 26621425U, // PRFMroX + 26621425U, // PRFMui + 26621455U, // PRFUMi + 537400862U, // RADDHNv2i64_v2i32 + 571748633U, // RADDHNv2i64_v4i32 + 1074796062U, // RADDHNv4i32_v4i16 + 1108881689U, // RADDHNv4i32_v8i16 + 1644179737U, // RADDHNv8i16_v16i8 + 1612453406U, // RADDHNv8i16_v8i8 + 553920698U, // RBITWr + 553920698U, // RBITXr + 6330U, // RBITv16i8 + 3759937722U, // RBITv8i8 + 2107559U, // RET + 0U, // RET_ReallyLR + 553918951U, // REV16Wr + 553918951U, // REV16Xr + 4583U, // REV16v16i8 + 3759935975U, // REV16v8i8 + 553918540U, // REV32Xr + 4172U, // REV32v16i8 + 2148536396U, // REV32v4i16 + 3222802508U, // REV32v8i16 + 3759935564U, // REV32v8i8 + 4566U, // REV64v16i8 + 1074270678U, // REV64v2i32 + 2148536790U, // REV64v4i16 + 2685669846U, // REV64v4i32 + 3222802902U, // REV64v8i16 + 3759935958U, // REV64v8i8 + 553920805U, // REVWr + 553920805U, // REVXr + 17049543U, // RORVWr + 17049543U, // RORVXr + 1644179766U, // RSHRNv16i8_shift + 537400917U, // RSHRNv2i32_shift + 1074796117U, // RSHRNv4i16_shift + 571748662U, // RSHRNv4i32_shift + 1108881718U, // RSHRNv8i16_shift + 1612453461U, // RSHRNv8i8_shift + 537400854U, // RSUBHNv2i64_v2i32 + 571748624U, // RSUBHNv2i64_v4i32 + 1074796054U, // RSUBHNv4i32_v4i16 + 1108881680U, // RSUBHNv4i32_v8i16 + 1644179728U, // RSUBHNv8i16_v16i8 + 1612453398U, // RSUBHNv8i16_v8i8 + 2182623330U, // SABALv16i8_v8i16 + 2718708931U, // SABALv2i32_v2i64 + 3256104131U, // SABALv4i16_v4i32 + 1108095074U, // SABALv4i32_v2i64 + 1645490274U, // SABALv8i16_v4i32 + 3793237187U, // SABALv8i8_v8i16 + 2181050862U, // SABAv16i8 + 2718446062U, // SABAv2i32 + 3255841262U, // SABAv4i16 + 1108619758U, // SABAv4i32 + 1645752814U, // SABAv8i16 + 3793498606U, // SABAv8i8 + 2149060764U, // SABDLv16i8_v8i16 + 2685146379U, // SABDLv2i32_v2i64 + 3222541579U, // SABDLv4i16_v4i32 + 1074532508U, // SABDLv4i32_v2i64 + 1611927708U, // SABDLv8i16_v4i32 + 3759674635U, // SABDLv8i8_v8i16 + 2147488538U, // SABDv16i8 + 2684883738U, // SABDv2i32 + 3222278938U, // SABDv4i16 + 1075057434U, // SABDv4i32 + 1612190490U, // SABDv8i16 + 3759936282U, // SABDv8i8 + 35141315U, // SADALPv16i8_v8i16 + 1117533891U, // SADALPv2i32_v1i64 + 2181576387U, // SADALPv4i16_v2i32 + 2718709443U, // SADALPv4i32_v2i64 + 3256104643U, // SADALPv8i16_v4i32 + 3792713411U, // SADALPv8i8_v4i16 + 1578707U, // SADDLPv16i8_v8i16 + 1083971283U, // SADDLPv2i32_v1i64 + 2148013779U, // SADDLPv4i16_v2i32 + 2685146835U, // SADDLPv4i32_v2i64 + 3222542035U, // SADDLPv8i16_v4i32 + 3759150803U, // SADDLPv8i8_v4i16 + 272700U, // SADDLVv16i8v + 2147756348U, // SADDLVv4i16v + 2684627260U, // SADDLVv4i32v + 3221498172U, // SADDLVv8i16v + 3758369084U, // SADDLVv8i8v + 2149060780U, // SADDLv16i8_v8i16 + 2685146409U, // SADDLv2i32_v2i64 + 3222541609U, // SADDLv4i16_v4i32 + 1074532524U, // SADDLv4i32_v2i64 + 1611927724U, // SADDLv8i16_v4i32 + 3759674665U, // SADDLv8i8_v8i16 + 1612190133U, // SADDWv16i8_v8i16 + 537663936U, // SADDWv2i32_v2i64 + 1075059136U, // SADDWv4i16_v4i32 + 537661877U, // SADDWv4i32_v2i64 + 1075057077U, // SADDWv8i16_v4i32 + 1612192192U, // SADDWv8i8_v8i16 + 17049656U, // SBCSWr + 17049656U, // SBCSXr + 17048293U, // SBCWr + 17048293U, // SBCXr + 17049061U, // SBFMWri + 17049061U, // SBFMXri + 17048517U, // SCVTFSWDri + 17048517U, // SCVTFSWSri + 17048517U, // SCVTFSXDri + 17048517U, // SCVTFSXSri + 553919429U, // SCVTFUWDri + 553919429U, // SCVTFUWSri + 553919429U, // SCVTFUXDri + 553919429U, // SCVTFUXSri + 17048517U, // SCVTFd + 17048517U, // SCVTFs + 553919429U, // SCVTFv1i32 + 553919429U, // SCVTFv1i64 + 1074271173U, // SCVTFv2f32 + 1611404229U, // SCVTFv2f64 + 2684883909U, // SCVTFv2i32_shift + 537662405U, // SCVTFv2i64_shift + 2685670341U, // SCVTFv4f32 + 1075057605U, // SCVTFv4i32_shift + 17049904U, // SDIVWr + 17049904U, // SDIVXr + 17049904U, // SDIV_IntWr + 17049904U, // SDIV_IntXr + 67404510U, // SHA1Crrr + 553919463U, // SHA1Hrr + 67405278U, // SHA1Mrrr + 67405488U, // SHA1Prrr + 1108619265U, // SHA1SU0rrr + 2719232056U, // SHA1SU1rr + 67403864U, // SHA256H2rrr + 67404790U, // SHA256Hrrr + 2719232010U, // SHA256SU0rr + 1108619329U, // SHA256SU1rrr + 2147488572U, // SHADDv16i8 + 2684883772U, // SHADDv2i32 + 3222278972U, // SHADDv4i16 + 1075057468U, // SHADDv4i32 + 1612190524U, // SHADDv8i16 + 3759936316U, // SHADDv8i8 + 2149060797U, // SHLLv16i8 + 2685146487U, // SHLLv2i32 + 3222541687U, // SHLLv4i16 + 3758887101U, // SHLLv4i32 + 1315005U, // SHLLv8i16 + 538449271U, // SHLLv8i8 + 17048896U, // SHLd + 2147489088U, // SHLv16i8_shift + 2684884288U, // SHLv2i32_shift + 537662784U, // SHLv2i64_shift + 3222279488U, // SHLv4i16_shift + 1075057984U, // SHLv4i32_shift + 1612191040U, // SHLv8i16_shift + 3759936832U, // SHLv8i8_shift + 1644179748U, // SHRNv16i8_shift + 537400901U, // SHRNv2i32_shift + 1074796101U, // SHRNv4i16_shift + 571748644U, // SHRNv4i32_shift + 1108881700U, // SHRNv8i16_shift + 1612453445U, // SHRNv8i8_shift + 2147488435U, // SHSUBv16i8 + 2684883635U, // SHSUBv2i32 + 3222278835U, // SHSUBv4i16 + 1075057331U, // SHSUBv4i32 + 1612190387U, // SHSUBv8i16 + 3759936179U, // SHSUBv8i8 + 67404954U, // SLId + 2181051546U, // SLIv16i8_shift + 2718446746U, // SLIv2i32_shift + 571225242U, // SLIv2i64_shift + 3255841946U, // SLIv4i16_shift + 1108620442U, // SLIv4i32_shift + 1645753498U, // SLIv8i16_shift + 3793499290U, // SLIv8i8_shift + 17048857U, // SMADDLrrr + 2147489609U, // SMAXPv16i8 + 2684884809U, // SMAXPv2i32 + 3222280009U, // SMAXPv4i16 + 1075058505U, // SMAXPv4i32 + 1612191561U, // SMAXPv8i16 + 3759937353U, // SMAXPv8i8 + 272787U, // SMAXVv16i8v + 2147756435U, // SMAXVv4i16v + 2684627347U, // SMAXVv4i32v + 3221498259U, // SMAXVv8i16v + 3758369171U, // SMAXVv8i8v + 2147490298U, // SMAXv16i8 + 2684885498U, // SMAXv2i32 + 3222280698U, // SMAXv4i16 + 1075059194U, // SMAXv4i32 + 1612192250U, // SMAXv8i16 + 3759938042U, // SMAXv8i8 + 21246U, // SMC + 2147489551U, // SMINPv16i8 + 2684884751U, // SMINPv2i32 + 3222279951U, // SMINPv4i16 + 1075058447U, // SMINPv4i32 + 1612191503U, // SMINPv8i16 + 3759937295U, // SMINPv8i8 + 272741U, // SMINVv16i8v + 2147756389U, // SMINVv4i16v + 2684627301U, // SMINVv4i32v + 3221498213U, // SMINVv8i16v + 3758369125U, // SMINVv8i8v + 2147489324U, // SMINv16i8 + 2684884524U, // SMINv2i32 + 3222279724U, // SMINv4i16 + 1075058220U, // SMINv4i32 + 1612191276U, // SMINv8i16 + 3759937068U, // SMINv8i8 + 2182623356U, // SMLALv16i8_v8i16 + 2718708954U, // SMLALv2i32_indexed + 2718708954U, // SMLALv2i32_v2i64 + 3256104154U, // SMLALv4i16_indexed + 3256104154U, // SMLALv4i16_v4i32 + 1108095100U, // SMLALv4i32_indexed + 1108095100U, // SMLALv4i32_v2i64 + 1645490300U, // SMLALv8i16_indexed + 1645490300U, // SMLALv8i16_v4i32 + 3793237210U, // SMLALv8i8_v8i16 + 2182623480U, // SMLSLv16i8_v8i16 + 2718709168U, // SMLSLv2i32_indexed + 2718709168U, // SMLSLv2i32_v2i64 + 3256104368U, // SMLSLv4i16_indexed + 3256104368U, // SMLSLv4i16_v4i32 + 1108095224U, // SMLSLv4i32_indexed + 1108095224U, // SMLSLv4i32_v2i64 + 1645490424U, // SMLSLv8i16_indexed + 1645490424U, // SMLSLv8i16_v4i32 + 3793237424U, // SMLSLv8i8_v8i16 + 272768U, // SMOVvi16to32 + 272768U, // SMOVvi16to64 + 537143680U, // SMOVvi32to64 + 1610885504U, // SMOVvi8to32 + 1610885504U, // SMOVvi8to64 + 17048813U, // SMSUBLrrr + 17048603U, // SMULHrr + 2149060830U, // SMULLv16i8_v8i16 + 2685146516U, // SMULLv2i32_indexed + 2685146516U, // SMULLv2i32_v2i64 + 3222541716U, // SMULLv4i16_indexed + 3222541716U, // SMULLv4i16_v4i32 + 1074532574U, // SMULLv4i32_indexed + 1074532574U, // SMULLv4i32_v2i64 + 1611927774U, // SMULLv8i16_indexed + 1611927774U, // SMULLv8i16_v4i32 + 3759674772U, // SMULLv8i8_v8i16 + 6187U, // SQABSv16i8 + 553920555U, // SQABSv1i16 + 553920555U, // SQABSv1i32 + 553920555U, // SQABSv1i64 + 553920555U, // SQABSv1i8 + 1074272299U, // SQABSv2i32 + 1611405355U, // SQABSv2i64 + 2148538411U, // SQABSv4i16 + 2685671467U, // SQABSv4i32 + 3222804523U, // SQABSv8i16 + 3759937579U, // SQABSv8i8 + 2147488602U, // SQADDv16i8 + 17048410U, // SQADDv1i16 + 17048410U, // SQADDv1i32 + 17048410U, // SQADDv1i64 + 17048410U, // SQADDv1i8 + 2684883802U, // SQADDv2i32 + 537662298U, // SQADDv2i64 + 3222279002U, // SQADDv4i16 + 1075057498U, // SQADDv4i32 + 1612190554U, // SQADDv8i16 + 3759936346U, // SQADDv8i8 + 67405009U, // SQDMLALi16 + 67405009U, // SQDMLALi32 + 67405009U, // SQDMLALv1i32_indexed + 67405009U, // SQDMLALv1i64_indexed + 2718708945U, // SQDMLALv2i32_indexed + 2718708945U, // SQDMLALv2i32_v2i64 + 3256104145U, // SQDMLALv4i16_indexed + 3256104145U, // SQDMLALv4i16_v4i32 + 1108095090U, // SQDMLALv4i32_indexed + 1108095090U, // SQDMLALv4i32_v2i64 + 1645490290U, // SQDMLALv8i16_indexed + 1645490290U, // SQDMLALv8i16_v4i32 + 67405223U, // SQDMLSLi16 + 67405223U, // SQDMLSLi32 + 67405223U, // SQDMLSLv1i32_indexed + 67405223U, // SQDMLSLv1i64_indexed + 2718709159U, // SQDMLSLv2i32_indexed + 2718709159U, // SQDMLSLv2i32_v2i64 + 3256104359U, // SQDMLSLv4i16_indexed + 3256104359U, // SQDMLSLv4i16_v4i32 + 1108095214U, // SQDMLSLv4i32_indexed + 1108095214U, // SQDMLSLv4i32_v2i64 + 1645490414U, // SQDMLSLv8i16_indexed + 1645490414U, // SQDMLSLv8i16_v4i32 + 17048584U, // SQDMULHv1i16 + 17048584U, // SQDMULHv1i16_indexed + 17048584U, // SQDMULHv1i32 + 17048584U, // SQDMULHv1i32_indexed + 2684883976U, // SQDMULHv2i32 + 2684883976U, // SQDMULHv2i32_indexed + 3222279176U, // SQDMULHv4i16 + 3222279176U, // SQDMULHv4i16_indexed + 1075057672U, // SQDMULHv4i32 + 1075057672U, // SQDMULHv4i32_indexed + 1612190728U, // SQDMULHv8i16 + 1612190728U, // SQDMULHv8i16_indexed + 17048964U, // SQDMULLi16 + 17048964U, // SQDMULLi32 + 17048964U, // SQDMULLv1i32_indexed + 17048964U, // SQDMULLv1i64_indexed + 2685146500U, // SQDMULLv2i32_indexed + 2685146500U, // SQDMULLv2i32_v2i64 + 3222541700U, // SQDMULLv4i16_indexed + 3222541700U, // SQDMULLv4i16_v4i32 + 1074532556U, // SQDMULLv4i32_indexed + 1074532556U, // SQDMULLv4i32_v2i64 + 1611927756U, // SQDMULLv8i16_indexed + 1611927756U, // SQDMULLv8i16_v4i32 + 5081U, // SQNEGv16i8 + 553919449U, // SQNEGv1i16 + 553919449U, // SQNEGv1i32 + 553919449U, // SQNEGv1i64 + 553919449U, // SQNEGv1i8 + 1074271193U, // SQNEGv2i32 + 1611404249U, // SQNEGv2i64 + 2148537305U, // SQNEGv4i16 + 2685670361U, // SQNEGv4i32 + 3222803417U, // SQNEGv8i16 + 3759936473U, // SQNEGv8i8 + 17048593U, // SQRDMULHv1i16 + 17048593U, // SQRDMULHv1i16_indexed + 17048593U, // SQRDMULHv1i32 + 17048593U, // SQRDMULHv1i32_indexed + 2684883985U, // SQRDMULHv2i32 + 2684883985U, // SQRDMULHv2i32_indexed + 3222279185U, // SQRDMULHv4i16 + 3222279185U, // SQRDMULHv4i16_indexed + 1075057681U, // SQRDMULHv4i32 + 1075057681U, // SQRDMULHv4i32_indexed + 1612190737U, // SQRDMULHv8i16 + 1612190737U, // SQRDMULHv8i16_indexed + 2147489100U, // SQRSHLv16i8 + 17048908U, // SQRSHLv1i16 + 17048908U, // SQRSHLv1i32 + 17048908U, // SQRSHLv1i64 + 17048908U, // SQRSHLv1i8 + 2684884300U, // SQRSHLv2i32 + 537662796U, // SQRSHLv2i64 + 3222279500U, // SQRSHLv4i16 + 1075057996U, // SQRSHLv4i32 + 1612191052U, // SQRSHLv8i16 + 3759936844U, // SQRSHLv8i8 + 17049171U, // SQRSHRNb + 17049171U, // SQRSHRNh + 17049171U, // SQRSHRNs + 1644179764U, // SQRSHRNv16i8_shift + 537400915U, // SQRSHRNv2i32_shift + 1074796115U, // SQRSHRNv4i16_shift + 571748660U, // SQRSHRNv4i32_shift + 1108881716U, // SQRSHRNv8i16_shift + 1612453459U, // SQRSHRNv8i8_shift + 17049232U, // SQRSHRUNb + 17049232U, // SQRSHRUNh + 17049232U, // SQRSHRUNs + 1644179824U, // SQRSHRUNv16i8_shift + 537400976U, // SQRSHRUNv2i32_shift + 1074796176U, // SQRSHRUNv4i16_shift + 571748720U, // SQRSHRUNv4i32_shift + 1108881776U, // SQRSHRUNv8i16_shift + 1612453520U, // SQRSHRUNv8i8_shift + 17049847U, // SQSHLUb + 17049847U, // SQSHLUd + 17049847U, // SQSHLUh + 17049847U, // SQSHLUs + 2147490039U, // SQSHLUv16i8_shift + 2684885239U, // SQSHLUv2i32_shift + 537663735U, // SQSHLUv2i64_shift + 3222280439U, // SQSHLUv4i16_shift + 1075058935U, // SQSHLUv4i32_shift + 1612191991U, // SQSHLUv8i16_shift + 3759937783U, // SQSHLUv8i8_shift + 17048894U, // SQSHLb + 17048894U, // SQSHLd + 17048894U, // SQSHLh + 17048894U, // SQSHLs + 2147489086U, // SQSHLv16i8 + 2147489086U, // SQSHLv16i8_shift + 17048894U, // SQSHLv1i16 + 17048894U, // SQSHLv1i32 + 17048894U, // SQSHLv1i64 + 17048894U, // SQSHLv1i8 + 2684884286U, // SQSHLv2i32 + 2684884286U, // SQSHLv2i32_shift + 537662782U, // SQSHLv2i64 + 537662782U, // SQSHLv2i64_shift + 3222279486U, // SQSHLv4i16 + 3222279486U, // SQSHLv4i16_shift + 1075057982U, // SQSHLv4i32 + 1075057982U, // SQSHLv4i32_shift + 1612191038U, // SQSHLv8i16 + 1612191038U, // SQSHLv8i16_shift + 3759936830U, // SQSHLv8i8 + 3759936830U, // SQSHLv8i8_shift + 17049155U, // SQSHRNb + 17049155U, // SQSHRNh + 17049155U, // SQSHRNs + 1644179746U, // SQSHRNv16i8_shift + 537400899U, // SQSHRNv2i32_shift + 1074796099U, // SQSHRNv4i16_shift + 571748642U, // SQSHRNv4i32_shift + 1108881698U, // SQSHRNv8i16_shift + 1612453443U, // SQSHRNv8i8_shift + 17049223U, // SQSHRUNb + 17049223U, // SQSHRUNh + 17049223U, // SQSHRUNs + 1644179814U, // SQSHRUNv16i8_shift + 537400967U, // SQSHRUNv2i32_shift + 1074796167U, // SQSHRUNv4i16_shift + 571748710U, // SQSHRUNv4i32_shift + 1108881766U, // SQSHRUNv8i16_shift + 1612453511U, // SQSHRUNv8i8_shift + 2147488464U, // SQSUBv16i8 + 17048272U, // SQSUBv1i16 + 17048272U, // SQSUBv1i32 + 17048272U, // SQSUBv1i64 + 17048272U, // SQSUBv1i8 + 2684883664U, // SQSUBv2i32 + 537662160U, // SQSUBv2i64 + 3222278864U, // SQSUBv4i16 + 1075057360U, // SQSUBv4i32 + 1612190416U, // SQSUBv8i16 + 3759936208U, // SQSUBv8i8 + 3254792534U, // SQXTNv16i8 + 553920121U, // SQXTNv1i16 + 553920121U, // SQXTNv1i32 + 553920121U, // SQXTNv1i8 + 1611142777U, // SQXTNv2i32 + 2685408889U, // SQXTNv4i16 + 1645490518U, // SQXTNv4i32 + 2719494486U, // SQXTNv8i16 + 3223066233U, // SQXTNv8i8 + 3254792571U, // SQXTUNv16i8 + 553920154U, // SQXTUNv1i16 + 553920154U, // SQXTUNv1i32 + 553920154U, // SQXTUNv1i8 + 1611142810U, // SQXTUNv2i32 + 2685408922U, // SQXTUNv4i16 + 1645490555U, // SQXTUNv4i32 + 2719494523U, // SQXTUNv8i16 + 3223066266U, // SQXTUNv8i8 + 2147488556U, // SRHADDv16i8 + 2684883756U, // SRHADDv2i32 + 3222278956U, // SRHADDv4i16 + 1075057452U, // SRHADDv4i32 + 1612190508U, // SRHADDv8i16 + 3759936300U, // SRHADDv8i8 + 67404965U, // SRId + 2181051557U, // SRIv16i8_shift + 2718446757U, // SRIv2i32_shift + 571225253U, // SRIv2i64_shift + 3255841957U, // SRIv4i16_shift + 1108620453U, // SRIv4i32_shift + 1645753509U, // SRIv8i16_shift + 3793499301U, // SRIv8i8_shift + 2147489116U, // SRSHLv16i8 + 17048924U, // SRSHLv1i64 + 2684884316U, // SRSHLv2i32 + 537662812U, // SRSHLv2i64 + 3222279516U, // SRSHLv4i16 + 1075058012U, // SRSHLv4i32 + 1612191068U, // SRSHLv8i16 + 3759936860U, // SRSHLv8i8 + 17049501U, // SRSHRd + 2147489693U, // SRSHRv16i8_shift + 2684884893U, // SRSHRv2i32_shift + 537663389U, // SRSHRv2i64_shift + 3222280093U, // SRSHRv4i16_shift + 1075058589U, // SRSHRv4i32_shift + 1612191645U, // SRSHRv8i16_shift + 3759937437U, // SRSHRv8i8_shift + 67404288U, // SRSRAd + 2181050880U, // SRSRAv16i8_shift + 2718446080U, // SRSRAv2i32_shift + 571224576U, // SRSRAv2i64_shift + 3255841280U, // SRSRAv4i16_shift + 1108619776U, // SRSRAv4i32_shift + 1645752832U, // SRSRAv8i16_shift + 3793498624U, // SRSRAv8i8_shift + 2149060796U, // SSHLLv16i8_shift + 2685146486U, // SSHLLv2i32_shift + 3222541686U, // SSHLLv4i16_shift + 1074532540U, // SSHLLv4i32_shift + 1611927740U, // SSHLLv8i16_shift + 3759674742U, // SSHLLv8i8_shift + 2147489130U, // SSHLv16i8 + 17048938U, // SSHLv1i64 + 2684884330U, // SSHLv2i32 + 537662826U, // SSHLv2i64 + 3222279530U, // SSHLv4i16 + 1075058026U, // SSHLv4i32 + 1612191082U, // SSHLv8i16 + 3759936874U, // SSHLv8i8 + 17049515U, // SSHRd + 2147489707U, // SSHRv16i8_shift + 2684884907U, // SSHRv2i32_shift + 537663403U, // SSHRv2i64_shift + 3222280107U, // SSHRv4i16_shift + 1075058603U, // SSHRv4i32_shift + 1612191659U, // SSHRv8i16_shift + 3759937451U, // SSHRv8i8_shift + 67404302U, // SSRAd + 2181050894U, // SSRAv16i8_shift + 2718446094U, // SSRAv2i32_shift + 571224590U, // SSRAv2i64_shift + 3255841294U, // SSRAv4i16_shift + 1108619790U, // SSRAv4i32_shift + 1645752846U, // SSRAv8i16_shift + 3793498638U, // SSRAv8i8_shift + 2149060748U, // SSUBLv16i8_v8i16 + 2685146365U, // SSUBLv2i32_v2i64 + 3222541565U, // SSUBLv4i16_v4i32 + 1074532492U, // SSUBLv4i32_v2i64 + 1611927692U, // SSUBLv8i16_v4i32 + 3759674621U, // SSUBLv8i8_v8i16 + 1612190117U, // SSUBWv16i8_v8i16 + 537663913U, // SSUBWv2i32_v2i64 + 1075059113U, // SSUBWv4i16_v4i32 + 537661861U, // SSUBWv4i32_v2i64 + 1075057061U, // SSUBWv8i16_v4i32 + 1612192169U, // SSUBWv8i8_v8i16 + 36915U, // ST1Fourv16b + 3711027U, // ST1Fourv16b_POST + 45107U, // ST1Fourv1d + 3981363U, // ST1Fourv1d_POST + 53299U, // ST1Fourv2d + 3727411U, // ST1Fourv2d_POST + 61491U, // ST1Fourv2s + 3997747U, // ST1Fourv2s_POST + 69683U, // ST1Fourv4h + 4005939U, // ST1Fourv4h_POST + 77875U, // ST1Fourv4s + 3751987U, // ST1Fourv4s_POST + 86067U, // ST1Fourv8b + 4022323U, // ST1Fourv8b_POST + 94259U, // ST1Fourv8h + 3768371U, // ST1Fourv8h_POST + 36915U, // ST1Onev16b + 4235315U, // ST1Onev16b_POST + 45107U, // ST1Onev1d + 4505651U, // ST1Onev1d_POST + 53299U, // ST1Onev2d + 4251699U, // ST1Onev2d_POST + 61491U, // ST1Onev2s + 4522035U, // ST1Onev2s_POST + 69683U, // ST1Onev4h + 4530227U, // ST1Onev4h_POST + 77875U, // ST1Onev4s + 4276275U, // ST1Onev4s_POST + 86067U, // ST1Onev8b + 4546611U, // ST1Onev8b_POST + 94259U, // ST1Onev8h + 4292659U, // ST1Onev8h_POST + 36915U, // ST1Threev16b + 5546035U, // ST1Threev16b_POST + 45107U, // ST1Threev1d + 5816371U, // ST1Threev1d_POST + 53299U, // ST1Threev2d + 5562419U, // ST1Threev2d_POST + 61491U, // ST1Threev2s + 5832755U, // ST1Threev2s_POST + 69683U, // ST1Threev4h + 5840947U, // ST1Threev4h_POST + 77875U, // ST1Threev4s + 5586995U, // ST1Threev4s_POST + 86067U, // ST1Threev8b + 5857331U, // ST1Threev8b_POST + 94259U, // ST1Threev8h + 5603379U, // ST1Threev8h_POST + 36915U, // ST1Twov16b + 3973171U, // ST1Twov16b_POST + 45107U, // ST1Twov1d + 4243507U, // ST1Twov1d_POST + 53299U, // ST1Twov2d + 3989555U, // ST1Twov2d_POST + 61491U, // ST1Twov2s + 4259891U, // ST1Twov2s_POST + 69683U, // ST1Twov4h + 4268083U, // ST1Twov4h_POST + 77875U, // ST1Twov4s + 4014131U, // ST1Twov4s_POST + 86067U, // ST1Twov8b + 4284467U, // ST1Twov8b_POST + 94259U, // ST1Twov8h + 4030515U, // ST1Twov8h_POST + 147507U, // ST1i16 + 262246451U, // ST1i16_POST + 151603U, // ST1i32 + 279031859U, // ST1i32_POST + 155699U, // ST1i64 + 295817267U, // ST1i64_POST + 159795U, // ST1i8 + 312602675U, // ST1i8_POST + 37280U, // ST2Twov16b + 3973536U, // ST2Twov16b_POST + 53664U, // ST2Twov2d + 3989920U, // ST2Twov2d_POST + 61856U, // ST2Twov2s + 4260256U, // ST2Twov2s_POST + 70048U, // ST2Twov4h + 4268448U, // ST2Twov4h_POST + 78240U, // ST2Twov4s + 4014496U, // ST2Twov4s_POST + 86432U, // ST2Twov8b + 4284832U, // ST2Twov8b_POST + 94624U, // ST2Twov8h + 4030880U, // ST2Twov8h_POST + 147872U, // ST2i16 + 279024032U, // ST2i16_POST + 151968U, // ST2i32 + 295809440U, // ST2i32_POST + 156064U, // ST2i64 + 329372064U, // ST2i64_POST + 160160U, // ST2i8 + 262271392U, // ST2i8_POST + 37329U, // ST3Threev16b + 5546449U, // ST3Threev16b_POST + 53713U, // ST3Threev2d + 5562833U, // ST3Threev2d_POST + 61905U, // ST3Threev2s + 5833169U, // ST3Threev2s_POST + 70097U, // ST3Threev4h + 5841361U, // ST3Threev4h_POST + 78289U, // ST3Threev4s + 5587409U, // ST3Threev4s_POST + 86481U, // ST3Threev8b + 5857745U, // ST3Threev8b_POST + 94673U, // ST3Threev8h + 5603793U, // ST3Threev8h_POST + 147921U, // ST3i16 + 346132945U, // ST3i16_POST + 152017U, // ST3i32 + 362918353U, // ST3i32_POST + 156113U, // ST3i64 + 379703761U, // ST3i64_POST + 160209U, // ST3i8 + 396489169U, // ST3i8_POST + 37346U, // ST4Fourv16b + 3711458U, // ST4Fourv16b_POST + 53730U, // ST4Fourv2d + 3727842U, // ST4Fourv2d_POST + 61922U, // ST4Fourv2s + 3998178U, // ST4Fourv2s_POST + 70114U, // ST4Fourv4h + 4006370U, // ST4Fourv4h_POST + 78306U, // ST4Fourv4s + 3752418U, // ST4Fourv4s_POST + 86498U, // ST4Fourv8b + 4022754U, // ST4Fourv8b_POST + 94690U, // ST4Fourv8h + 3768802U, // ST4Fourv8h_POST + 147938U, // ST4i16 + 295801314U, // ST4i16_POST + 152034U, // ST4i32 + 329363938U, // ST4i32_POST + 156130U, // ST4i64 + 413258210U, // ST4i64_POST + 160226U, // ST4i8 + 279048674U, // ST4i8_POST + 26485317U, // STLRB + 26485814U, // STLRH + 26486716U, // STLRW + 26486716U, // STLRX + 17049437U, // STLXPW + 17049437U, // STLXPX + 553919101U, // STLXRB + 553919598U, // STLXRH + 553920528U, // STLXRW + 553920528U, // STLXRX + 553920285U, // STNPDi + 553920285U, // STNPQi + 553920285U, // STNPSi + 553920285U, // STNPWi + 553920285U, // STNPXi + 553920305U, // STPDi + 604276529U, // STPDpost + 604276529U, // STPDpre + 553920305U, // STPQi + 604276529U, // STPQpost + 604276529U, // STPQpre + 553920305U, // STPSi + 604276529U, // STPSpost + 604276529U, // STPSpre + 553920305U, // STPWi + 604276529U, // STPWpost + 604276529U, // STPWpre + 553920305U, // STPXi + 604276529U, // STPXpost + 604276529U, // STPXpre + 1150583379U, // STRBBpost + 76841555U, // STRBBpre + 26485331U, // STRBBroW + 26485331U, // STRBBroX + 26485331U, // STRBBui + 1150584806U, // STRBpost + 76842982U, // STRBpre + 26486758U, // STRBroW + 26486758U, // STRBroX + 26486758U, // STRBui + 1150584806U, // STRDpost + 76842982U, // STRDpre + 26486758U, // STRDroW + 26486758U, // STRDroX + 26486758U, // STRDui + 1150583876U, // STRHHpost + 76842052U, // STRHHpre + 26485828U, // STRHHroW + 26485828U, // STRHHroX + 26485828U, // STRHHui + 1150584806U, // STRHpost + 76842982U, // STRHpre + 26486758U, // STRHroW + 26486758U, // STRHroX + 26486758U, // STRHui + 1150584806U, // STRQpost + 76842982U, // STRQpre + 26486758U, // STRQroW + 26486758U, // STRQroX + 26486758U, // STRQui + 1150584806U, // STRSpost + 76842982U, // STRSpre + 26486758U, // STRSroW + 26486758U, // STRSroX + 26486758U, // STRSui + 1150584806U, // STRWpost + 76842982U, // STRWpre + 26486758U, // STRWroW + 26486758U, // STRWroX + 26486758U, // STRWui + 1150584806U, // STRXpost + 76842982U, // STRXpre + 26486758U, // STRXroW + 26486758U, // STRXroX + 26486758U, // STRXui + 26485337U, // STTRBi + 26485834U, // STTRHi + 26486763U, // STTRWi + 26486763U, // STTRXi + 26485351U, // STURBBi + 26486781U, // STURBi + 26486781U, // STURDi + 26485848U, // STURHHi + 26486781U, // STURHi + 26486781U, // STURQi + 26486781U, // STURSi + 26486781U, // STURWi + 26486781U, // STURXi + 17049444U, // STXPW + 17049444U, // STXPX + 553919109U, // STXRB + 553919606U, // STXRH + 553920535U, // STXRW + 553920535U, // STXRX + 537400855U, // SUBHNv2i64_v2i32 + 571748625U, // SUBHNv2i64_v4i32 + 1074796055U, // SUBHNv4i32_v4i16 + 1108881681U, // SUBHNv4i32_v8i16 + 1644179729U, // SUBHNv8i16_v16i8 + 1612453399U, // SUBHNv8i16_v8i8 + 17049650U, // SUBSWri + 0U, // SUBSWrr + 17049650U, // SUBSWrs + 17049650U, // SUBSWrx + 17049650U, // SUBSXri + 0U, // SUBSXrr + 17049650U, // SUBSXrs + 17049650U, // SUBSXrx + 17049650U, // SUBSXrx64 + 17048238U, // SUBWri + 0U, // SUBWrr + 17048238U, // SUBWrs + 17048238U, // SUBWrx + 17048238U, // SUBXri + 0U, // SUBXrr + 17048238U, // SUBXrs + 17048238U, // SUBXrx + 17048238U, // SUBXrx64 + 2147488430U, // SUBv16i8 + 17048238U, // SUBv1i64 + 2684883630U, // SUBv2i32 + 537662126U, // SUBv2i64 + 3222278830U, // SUBv4i16 + 1075057326U, // SUBv4i32 + 1612190382U, // SUBv8i16 + 3759936174U, // SUBv8i8 + 33567585U, // SUQADDv16i8 + 604275553U, // SUQADDv1i16 + 604275553U, // SUQADDv1i32 + 604275553U, // SUQADDv1i64 + 604275553U, // SUQADDv1i8 + 1107833697U, // SUQADDv2i32 + 1644966753U, // SUQADDv2i64 + 2182099809U, // SUQADDv4i16 + 2719232865U, // SUQADDv4i32 + 3256365921U, // SUQADDv8i16 + 3793498977U, // SUQADDv8i8 + 21263U, // SVC + 17049022U, // SYSLxt + 419702938U, // SYSxt + 436212968U, // TBLv16i8Four + 436212968U, // TBLv16i8One + 436212968U, // TBLv16i8Three + 436212968U, // TBLv16i8Two + 4196144360U, // TBLv8i8Four + 4196144360U, // TBLv8i8One + 4196144360U, // TBLv8i8Three + 4196144360U, // TBLv8i8Two + 17050183U, // TBNZW + 17050183U, // TBNZX + 452999686U, // TBXv16i8Four + 452999686U, // TBXv16i8One + 452999686U, // TBXv16i8Three + 452999686U, // TBXv16i8Two + 4212931078U, // TBXv8i8Four + 4212931078U, // TBXv8i8One + 4212931078U, // TBXv8i8Three + 4212931078U, // TBXv8i8Two + 17050167U, // TBZW + 17050167U, // TBZX + 0U, // TCRETURNdi + 0U, // TCRETURNri + 2107995U, // TLSDESCCALL + 0U, // TLSDESC_BLR + 2147487770U, // TRN1v16i8 + 2684882970U, // TRN1v2i32 + 537661466U, // TRN1v2i64 + 3222278170U, // TRN1v4i16 + 1075056666U, // TRN1v4i32 + 1612189722U, // TRN1v8i16 + 3759935514U, // TRN1v8i8 + 2147488072U, // TRN2v16i8 + 2684883272U, // TRN2v2i32 + 537661768U, // TRN2v2i64 + 3222278472U, // TRN2v4i16 + 1075056968U, // TRN2v4i32 + 1612190024U, // TRN2v8i16 + 3759935816U, // TRN2v8i8 + 2182623338U, // UABALv16i8_v8i16 + 2718708938U, // UABALv2i32_v2i64 + 3256104138U, // UABALv4i16_v4i32 + 1108095082U, // UABALv4i32_v2i64 + 1645490282U, // UABALv8i16_v4i32 + 3793237194U, // UABALv8i8_v8i16 + 2181050868U, // UABAv16i8 + 2718446068U, // UABAv2i32 + 3255841268U, // UABAv4i16 + 1108619764U, // UABAv4i32 + 1645752820U, // UABAv8i16 + 3793498612U, // UABAv8i8 + 2149060772U, // UABDLv16i8_v8i16 + 2685146386U, // UABDLv2i32_v2i64 + 3222541586U, // UABDLv4i16_v4i32 + 1074532516U, // UABDLv4i32_v2i64 + 1611927716U, // UABDLv8i16_v4i32 + 3759674642U, // UABDLv8i8_v8i16 + 2147488544U, // UABDv16i8 + 2684883744U, // UABDv2i32 + 3222278944U, // UABDv4i16 + 1075057440U, // UABDv4i32 + 1612190496U, // UABDv8i16 + 3759936288U, // UABDv8i8 + 35141323U, // UADALPv16i8_v8i16 + 1117533899U, // UADALPv2i32_v1i64 + 2181576395U, // UADALPv4i16_v2i32 + 2718709451U, // UADALPv4i32_v2i64 + 3256104651U, // UADALPv8i16_v4i32 + 3792713419U, // UADALPv8i8_v4i16 + 1578715U, // UADDLPv16i8_v8i16 + 1083971291U, // UADDLPv2i32_v1i64 + 2148013787U, // UADDLPv4i16_v2i32 + 2685146843U, // UADDLPv4i32_v2i64 + 3222542043U, // UADDLPv8i16_v4i32 + 3759150811U, // UADDLPv8i8_v4i16 + 272708U, // UADDLVv16i8v + 2147756356U, // UADDLVv4i16v + 2684627268U, // UADDLVv4i32v + 3221498180U, // UADDLVv8i16v + 3758369092U, // UADDLVv8i8v + 2149060788U, // UADDLv16i8_v8i16 + 2685146416U, // UADDLv2i32_v2i64 + 3222541616U, // UADDLv4i16_v4i32 + 1074532532U, // UADDLv4i32_v2i64 + 1611927732U, // UADDLv8i16_v4i32 + 3759674672U, // UADDLv8i8_v8i16 + 1612190141U, // UADDWv16i8_v8i16 + 537663943U, // UADDWv2i32_v2i64 + 1075059143U, // UADDWv4i16_v4i32 + 537661885U, // UADDWv4i32_v2i64 + 1075057085U, // UADDWv8i16_v4i32 + 1612192199U, // UADDWv8i8_v8i16 + 17049067U, // UBFMWri + 17049067U, // UBFMXri + 17048524U, // UCVTFSWDri + 17048524U, // UCVTFSWSri + 17048524U, // UCVTFSXDri + 17048524U, // UCVTFSXSri + 553919436U, // UCVTFUWDri + 553919436U, // UCVTFUWSri + 553919436U, // UCVTFUXDri + 553919436U, // UCVTFUXSri + 17048524U, // UCVTFd + 17048524U, // UCVTFs + 553919436U, // UCVTFv1i32 + 553919436U, // UCVTFv1i64 + 1074271180U, // UCVTFv2f32 + 1611404236U, // UCVTFv2f64 + 2684883916U, // UCVTFv2i32_shift + 537662412U, // UCVTFv2i64_shift + 2685670348U, // UCVTFv4f32 + 1075057612U, // UCVTFv4i32_shift + 17049910U, // UDIVWr + 17049910U, // UDIVXr + 17049910U, // UDIV_IntWr + 17049910U, // UDIV_IntXr + 2147488579U, // UHADDv16i8 + 2684883779U, // UHADDv2i32 + 3222278979U, // UHADDv4i16 + 1075057475U, // UHADDv4i32 + 1612190531U, // UHADDv8i16 + 3759936323U, // UHADDv8i8 + 2147488442U, // UHSUBv16i8 + 2684883642U, // UHSUBv2i32 + 3222278842U, // UHSUBv4i16 + 1075057338U, // UHSUBv4i32 + 1612190394U, // UHSUBv8i16 + 3759936186U, // UHSUBv8i8 + 17048865U, // UMADDLrrr + 2147489616U, // UMAXPv16i8 + 2684884816U, // UMAXPv2i32 + 3222280016U, // UMAXPv4i16 + 1075058512U, // UMAXPv4i32 + 1612191568U, // UMAXPv8i16 + 3759937360U, // UMAXPv8i8 + 272794U, // UMAXVv16i8v + 2147756442U, // UMAXVv4i16v + 2684627354U, // UMAXVv4i32v + 3221498266U, // UMAXVv8i16v + 3758369178U, // UMAXVv8i8v + 2147490304U, // UMAXv16i8 + 2684885504U, // UMAXv2i32 + 3222280704U, // UMAXv4i16 + 1075059200U, // UMAXv4i32 + 1612192256U, // UMAXv8i16 + 3759938048U, // UMAXv8i8 + 2147489558U, // UMINPv16i8 + 2684884758U, // UMINPv2i32 + 3222279958U, // UMINPv4i16 + 1075058454U, // UMINPv4i32 + 1612191510U, // UMINPv8i16 + 3759937302U, // UMINPv8i8 + 272748U, // UMINVv16i8v + 2147756396U, // UMINVv4i16v + 2684627308U, // UMINVv4i32v + 3221498220U, // UMINVv8i16v + 3758369132U, // UMINVv8i8v + 2147489330U, // UMINv16i8 + 2684884530U, // UMINv2i32 + 3222279730U, // UMINv4i16 + 1075058226U, // UMINv4i32 + 1612191282U, // UMINv8i16 + 3759937074U, // UMINv8i8 + 2182623364U, // UMLALv16i8_v8i16 + 2718708961U, // UMLALv2i32_indexed + 2718708961U, // UMLALv2i32_v2i64 + 3256104161U, // UMLALv4i16_indexed + 3256104161U, // UMLALv4i16_v4i32 + 1108095108U, // UMLALv4i32_indexed + 1108095108U, // UMLALv4i32_v2i64 + 1645490308U, // UMLALv8i16_indexed + 1645490308U, // UMLALv8i16_v4i32 + 3793237217U, // UMLALv8i8_v8i16 + 2182623488U, // UMLSLv16i8_v8i16 + 2718709175U, // UMLSLv2i32_indexed + 2718709175U, // UMLSLv2i32_v2i64 + 3256104375U, // UMLSLv4i16_indexed + 3256104375U, // UMLSLv4i16_v4i32 + 1108095232U, // UMLSLv4i32_indexed + 1108095232U, // UMLSLv4i32_v2i64 + 1645490432U, // UMLSLv8i16_indexed + 1645490432U, // UMLSLv8i16_v4i32 + 3793237431U, // UMLSLv8i8_v8i16 + 272774U, // UMOVvi16 + 537143686U, // UMOVvi32 + 1074014598U, // UMOVvi64 + 1610885510U, // UMOVvi8 + 17048821U, // UMSUBLrrr + 17048610U, // UMULHrr + 2149060838U, // UMULLv16i8_v8i16 + 2685146523U, // UMULLv2i32_indexed + 2685146523U, // UMULLv2i32_v2i64 + 3222541723U, // UMULLv4i16_indexed + 3222541723U, // UMULLv4i16_v4i32 + 1074532582U, // UMULLv4i32_indexed + 1074532582U, // UMULLv4i32_v2i64 + 1611927782U, // UMULLv8i16_indexed + 1611927782U, // UMULLv8i16_v4i32 + 3759674779U, // UMULLv8i8_v8i16 + 2147488610U, // UQADDv16i8 + 17048418U, // UQADDv1i16 + 17048418U, // UQADDv1i32 + 17048418U, // UQADDv1i64 + 17048418U, // UQADDv1i8 + 2684883810U, // UQADDv2i32 + 537662306U, // UQADDv2i64 + 3222279010U, // UQADDv4i16 + 1075057506U, // UQADDv4i32 + 1612190562U, // UQADDv8i16 + 3759936354U, // UQADDv8i8 + 2147489108U, // UQRSHLv16i8 + 17048916U, // UQRSHLv1i16 + 17048916U, // UQRSHLv1i32 + 17048916U, // UQRSHLv1i64 + 17048916U, // UQRSHLv1i8 + 2684884308U, // UQRSHLv2i32 + 537662804U, // UQRSHLv2i64 + 3222279508U, // UQRSHLv4i16 + 1075058004U, // UQRSHLv4i32 + 1612191060U, // UQRSHLv8i16 + 3759936852U, // UQRSHLv8i8 + 17049180U, // UQRSHRNb + 17049180U, // UQRSHRNh + 17049180U, // UQRSHRNs + 1644179774U, // UQRSHRNv16i8_shift + 537400924U, // UQRSHRNv2i32_shift + 1074796124U, // UQRSHRNv4i16_shift + 571748670U, // UQRSHRNv4i32_shift + 1108881726U, // UQRSHRNv8i16_shift + 1612453468U, // UQRSHRNv8i8_shift + 17048901U, // UQSHLb + 17048901U, // UQSHLd + 17048901U, // UQSHLh + 17048901U, // UQSHLs + 2147489093U, // UQSHLv16i8 + 2147489093U, // UQSHLv16i8_shift + 17048901U, // UQSHLv1i16 + 17048901U, // UQSHLv1i32 + 17048901U, // UQSHLv1i64 + 17048901U, // UQSHLv1i8 + 2684884293U, // UQSHLv2i32 + 2684884293U, // UQSHLv2i32_shift + 537662789U, // UQSHLv2i64 + 537662789U, // UQSHLv2i64_shift + 3222279493U, // UQSHLv4i16 + 3222279493U, // UQSHLv4i16_shift + 1075057989U, // UQSHLv4i32 + 1075057989U, // UQSHLv4i32_shift + 1612191045U, // UQSHLv8i16 + 1612191045U, // UQSHLv8i16_shift + 3759936837U, // UQSHLv8i8 + 3759936837U, // UQSHLv8i8_shift + 17049163U, // UQSHRNb + 17049163U, // UQSHRNh + 17049163U, // UQSHRNs + 1644179755U, // UQSHRNv16i8_shift + 537400907U, // UQSHRNv2i32_shift + 1074796107U, // UQSHRNv4i16_shift + 571748651U, // UQSHRNv4i32_shift + 1108881707U, // UQSHRNv8i16_shift + 1612453451U, // UQSHRNv8i8_shift + 2147488471U, // UQSUBv16i8 + 17048279U, // UQSUBv1i16 + 17048279U, // UQSUBv1i32 + 17048279U, // UQSUBv1i64 + 17048279U, // UQSUBv1i8 + 2684883671U, // UQSUBv2i32 + 537662167U, // UQSUBv2i64 + 3222278871U, // UQSUBv4i16 + 1075057367U, // UQSUBv4i32 + 1612190423U, // UQSUBv8i16 + 3759936215U, // UQSUBv8i8 + 3254792542U, // UQXTNv16i8 + 553920128U, // UQXTNv1i16 + 553920128U, // UQXTNv1i32 + 553920128U, // UQXTNv1i8 + 1611142784U, // UQXTNv2i32 + 2685408896U, // UQXTNv4i16 + 1645490526U, // UQXTNv4i32 + 2719494494U, // UQXTNv8i16 + 3223066240U, // UQXTNv8i8 + 1074271121U, // URECPEv2i32 + 2685670289U, // URECPEv4i32 + 2147488564U, // URHADDv16i8 + 2684883764U, // URHADDv2i32 + 3222278964U, // URHADDv4i16 + 1075057460U, // URHADDv4i32 + 1612190516U, // URHADDv8i16 + 3759936308U, // URHADDv8i8 + 2147489123U, // URSHLv16i8 + 17048931U, // URSHLv1i64 + 2684884323U, // URSHLv2i32 + 537662819U, // URSHLv2i64 + 3222279523U, // URSHLv4i16 + 1075058019U, // URSHLv4i32 + 1612191075U, // URSHLv8i16 + 3759936867U, // URSHLv8i8 + 17049508U, // URSHRd + 2147489700U, // URSHRv16i8_shift + 2684884900U, // URSHRv2i32_shift + 537663396U, // URSHRv2i64_shift + 3222280100U, // URSHRv4i16_shift + 1075058596U, // URSHRv4i32_shift + 1612191652U, // URSHRv8i16_shift + 3759937444U, // URSHRv8i8_shift + 1074271159U, // URSQRTEv2i32 + 2685670327U, // URSQRTEv4i32 + 67404295U, // URSRAd + 2181050887U, // URSRAv16i8_shift + 2718446087U, // URSRAv2i32_shift + 571224583U, // URSRAv2i64_shift + 3255841287U, // URSRAv4i16_shift + 1108619783U, // URSRAv4i32_shift + 1645752839U, // URSRAv8i16_shift + 3793498631U, // URSRAv8i8_shift + 2149060804U, // USHLLv16i8_shift + 2685146493U, // USHLLv2i32_shift + 3222541693U, // USHLLv4i16_shift + 1074532548U, // USHLLv4i32_shift + 1611927748U, // USHLLv8i16_shift + 3759674749U, // USHLLv8i8_shift + 2147489136U, // USHLv16i8 + 17048944U, // USHLv1i64 + 2684884336U, // USHLv2i32 + 537662832U, // USHLv2i64 + 3222279536U, // USHLv4i16 + 1075058032U, // USHLv4i32 + 1612191088U, // USHLv8i16 + 3759936880U, // USHLv8i8 + 17049521U, // USHRd + 2147489713U, // USHRv16i8_shift + 2684884913U, // USHRv2i32_shift + 537663409U, // USHRv2i64_shift + 3222280113U, // USHRv4i16_shift + 1075058609U, // USHRv4i32_shift + 1612191665U, // USHRv8i16_shift + 3759937457U, // USHRv8i8_shift + 33567577U, // USQADDv16i8 + 604275545U, // USQADDv1i16 + 604275545U, // USQADDv1i32 + 604275545U, // USQADDv1i64 + 604275545U, // USQADDv1i8 + 1107833689U, // USQADDv2i32 + 1644966745U, // USQADDv2i64 + 2182099801U, // USQADDv4i16 + 2719232857U, // USQADDv4i32 + 3256365913U, // USQADDv8i16 + 3793498969U, // USQADDv8i8 + 67404308U, // USRAd + 2181050900U, // USRAv16i8_shift + 2718446100U, // USRAv2i32_shift + 571224596U, // USRAv2i64_shift + 3255841300U, // USRAv4i16_shift + 1108619796U, // USRAv4i32_shift + 1645752852U, // USRAv8i16_shift + 3793498644U, // USRAv8i8_shift + 2149060756U, // USUBLv16i8_v8i16 + 2685146372U, // USUBLv2i32_v2i64 + 3222541572U, // USUBLv4i16_v4i32 + 1074532500U, // USUBLv4i32_v2i64 + 1611927700U, // USUBLv8i16_v4i32 + 3759674628U, // USUBLv8i8_v8i16 + 1612190125U, // USUBWv16i8_v8i16 + 537663920U, // USUBWv2i32_v2i64 + 1075059120U, // USUBWv4i16_v4i32 + 537661869U, // USUBWv4i32_v2i64 + 1075057069U, // USUBWv8i16_v4i32 + 1612192176U, // USUBWv8i8_v8i16 + 2147487782U, // UZP1v16i8 + 2684882982U, // UZP1v2i32 + 537661478U, // UZP1v2i64 + 3222278182U, // UZP1v4i16 + 1075056678U, // UZP1v4i32 + 1612189734U, // UZP1v8i16 + 3759935526U, // UZP1v8i8 + 2147488147U, // UZP2v16i8 + 2684883347U, // UZP2v2i32 + 537661843U, // UZP2v2i64 + 3222278547U, // UZP2v4i16 + 1075057043U, // UZP2v4i32 + 1612190099U, // UZP2v8i16 + 3759935891U, // UZP2v8i8 + 3254792536U, // XTNv16i8 + 1611142779U, // XTNv2i32 + 2685408891U, // XTNv4i16 + 1645490520U, // XTNv4i32 + 2719494488U, // XTNv8i16 + 3223066235U, // XTNv8i8 + 2147487776U, // ZIP1v16i8 + 2684882976U, // ZIP1v2i32 + 537661472U, // ZIP1v2i64 + 3222278176U, // ZIP1v4i16 + 1075056672U, // ZIP1v4i32 + 1612189728U, // ZIP1v8i16 + 3759935520U, // ZIP1v8i8 + 2147488141U, // ZIP2v16i8 + 2684883341U, // ZIP2v2i32 + 537661837U, // ZIP2v2i64 + 3222278541U, // ZIP2v4i16 + 1075057037U, // ZIP2v4i32 + 1612190093U, // ZIP2v8i16 + 3759935885U, // ZIP2v8i8 + 0U + }; + + static const uint32_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 0U, // ABSv16i8 + 0U, // ABSv1i64 + 0U, // ABSv2i32 + 0U, // ABSv2i64 + 0U, // ABSv4i16 + 0U, // ABSv4i32 + 0U, // ABSv8i16 + 0U, // ABSv8i8 + 1U, // ADCSWr + 1U, // ADCSXr + 1U, // ADCWr + 1U, // ADCXr + 265U, // ADDHNv2i64_v2i32 + 273U, // ADDHNv2i64_v4i32 + 521U, // ADDHNv4i32_v4i16 + 529U, // ADDHNv4i32_v8i16 + 785U, // ADDHNv8i16_v16i8 + 777U, // ADDHNv8i16_v8i8 + 1033U, // ADDPv16i8 + 1289U, // ADDPv2i32 + 265U, // ADDPv2i64 + 0U, // ADDPv2i64p + 1545U, // ADDPv4i16 + 521U, // ADDPv4i32 + 777U, // ADDPv8i16 + 1801U, // ADDPv8i8 + 25U, // ADDSWri + 0U, // ADDSWrr + 33U, // ADDSWrs + 41U, // ADDSWrx + 25U, // ADDSXri + 0U, // ADDSXrr + 33U, // ADDSXrs + 41U, // ADDSXrx + 2049U, // ADDSXrx64 + 0U, // ADDVv16i8v + 0U, // ADDVv4i16v + 0U, // ADDVv4i32v + 0U, // ADDVv8i16v + 0U, // ADDVv8i8v + 25U, // ADDWri + 0U, // ADDWrr + 33U, // ADDWrs + 41U, // ADDWrx + 25U, // ADDXri + 0U, // ADDXrr + 33U, // ADDXrs + 41U, // ADDXrx + 2049U, // ADDXrx64 + 1033U, // ADDv16i8 + 1U, // ADDv1i64 + 1289U, // ADDv2i32 + 265U, // ADDv2i64 + 1545U, // ADDv4i16 + 521U, // ADDv4i32 + 777U, // ADDv8i16 + 1801U, // ADDv8i8 + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADR + 0U, // ADRP + 0U, // AESDrr + 0U, // AESErr + 0U, // AESIMCrr + 0U, // AESMCrr + 49U, // ANDSWri + 0U, // ANDSWrr + 33U, // ANDSWrs + 57U, // ANDSXri + 0U, // ANDSXrr + 33U, // ANDSXrs + 49U, // ANDWri + 0U, // ANDWrr + 33U, // ANDWrs + 57U, // ANDXri + 0U, // ANDXrr + 33U, // ANDXrs + 1033U, // ANDv16i8 + 1801U, // ANDv8i8 + 1U, // ASRVWr + 1U, // ASRVXr + 0U, // B + 2369U, // BFMWri + 2369U, // BFMXri + 0U, // BICSWrr + 33U, // BICSWrs + 0U, // BICSXrr + 33U, // BICSXrs + 0U, // BICWrr + 33U, // BICWrs + 0U, // BICXrr + 33U, // BICXrs + 1033U, // BICv16i8 + 0U, // BICv2i32 + 0U, // BICv4i16 + 0U, // BICv4i32 + 0U, // BICv8i16 + 1801U, // BICv8i8 + 1033U, // BIFv16i8 + 1801U, // BIFv8i8 + 1041U, // BITv16i8 + 1809U, // BITv8i8 + 0U, // BL + 0U, // BLR + 0U, // BR + 0U, // BRK + 1041U, // BSLv16i8 + 1809U, // BSLv8i8 + 0U, // Bcc + 0U, // CBNZW + 0U, // CBNZX + 0U, // CBZW + 0U, // CBZX + 10497U, // CCMNWi + 10497U, // CCMNWr + 10497U, // CCMNXi + 10497U, // CCMNXr + 10497U, // CCMPWi + 10497U, // CCMPWr + 10497U, // CCMPXi + 10497U, // CCMPXr + 0U, // CLREX + 0U, // CLSWr + 0U, // CLSXr + 0U, // CLSv16i8 + 0U, // CLSv2i32 + 0U, // CLSv4i16 + 0U, // CLSv4i32 + 0U, // CLSv8i16 + 0U, // CLSv8i8 + 0U, // CLZWr + 0U, // CLZXr + 0U, // CLZv16i8 + 0U, // CLZv2i32 + 0U, // CLZv4i16 + 0U, // CLZv4i32 + 0U, // CLZv8i16 + 0U, // CLZv8i8 + 1033U, // CMEQv16i8 + 2U, // CMEQv16i8rz + 1U, // CMEQv1i64 + 2U, // CMEQv1i64rz + 1289U, // CMEQv2i32 + 2U, // CMEQv2i32rz + 265U, // CMEQv2i64 + 2U, // CMEQv2i64rz + 1545U, // CMEQv4i16 + 2U, // CMEQv4i16rz + 521U, // CMEQv4i32 + 2U, // CMEQv4i32rz + 777U, // CMEQv8i16 + 2U, // CMEQv8i16rz + 1801U, // CMEQv8i8 + 2U, // CMEQv8i8rz + 1033U, // CMGEv16i8 + 2U, // CMGEv16i8rz + 1U, // CMGEv1i64 + 2U, // CMGEv1i64rz + 1289U, // CMGEv2i32 + 2U, // CMGEv2i32rz + 265U, // CMGEv2i64 + 2U, // CMGEv2i64rz + 1545U, // CMGEv4i16 + 2U, // CMGEv4i16rz + 521U, // CMGEv4i32 + 2U, // CMGEv4i32rz + 777U, // CMGEv8i16 + 2U, // CMGEv8i16rz + 1801U, // CMGEv8i8 + 2U, // CMGEv8i8rz + 1033U, // CMGTv16i8 + 2U, // CMGTv16i8rz + 1U, // CMGTv1i64 + 2U, // CMGTv1i64rz + 1289U, // CMGTv2i32 + 2U, // CMGTv2i32rz + 265U, // CMGTv2i64 + 2U, // CMGTv2i64rz + 1545U, // CMGTv4i16 + 2U, // CMGTv4i16rz + 521U, // CMGTv4i32 + 2U, // CMGTv4i32rz + 777U, // CMGTv8i16 + 2U, // CMGTv8i16rz + 1801U, // CMGTv8i8 + 2U, // CMGTv8i8rz + 1033U, // CMHIv16i8 + 1U, // CMHIv1i64 + 1289U, // CMHIv2i32 + 265U, // CMHIv2i64 + 1545U, // CMHIv4i16 + 521U, // CMHIv4i32 + 777U, // CMHIv8i16 + 1801U, // CMHIv8i8 + 1033U, // CMHSv16i8 + 1U, // CMHSv1i64 + 1289U, // CMHSv2i32 + 265U, // CMHSv2i64 + 1545U, // CMHSv4i16 + 521U, // CMHSv4i32 + 777U, // CMHSv8i16 + 1801U, // CMHSv8i8 + 2U, // CMLEv16i8rz + 2U, // CMLEv1i64rz + 2U, // CMLEv2i32rz + 2U, // CMLEv2i64rz + 2U, // CMLEv4i16rz + 2U, // CMLEv4i32rz + 2U, // CMLEv8i16rz + 2U, // CMLEv8i8rz + 2U, // CMLTv16i8rz + 2U, // CMLTv1i64rz + 2U, // CMLTv2i32rz + 2U, // CMLTv2i64rz + 2U, // CMLTv4i16rz + 2U, // CMLTv4i32rz + 2U, // CMLTv8i16rz + 2U, // CMLTv8i8rz + 1033U, // CMTSTv16i8 + 1U, // CMTSTv1i64 + 1289U, // CMTSTv2i32 + 265U, // CMTSTv2i64 + 1545U, // CMTSTv4i16 + 521U, // CMTSTv4i32 + 777U, // CMTSTv8i16 + 1801U, // CMTSTv8i8 + 0U, // CNTv16i8 + 0U, // CNTv8i8 + 75U, // CPYi16 + 75U, // CPYi32 + 75U, // CPYi64 + 75U, // CPYi8 + 1U, // CRC32Brr + 1U, // CRC32CBrr + 1U, // CRC32CHrr + 1U, // CRC32CWrr + 1U, // CRC32CXrr + 1U, // CRC32Hrr + 1U, // CRC32Wrr + 1U, // CRC32Xrr + 10497U, // CSELWr + 10497U, // CSELXr + 10497U, // CSINCWr + 10497U, // CSINCXr + 10497U, // CSINVWr + 10497U, // CSINVXr + 10497U, // CSNEGWr + 10497U, // CSNEGXr + 0U, // DCPS1 + 0U, // DCPS2 + 0U, // DCPS3 + 0U, // DMB + 0U, // DRPS + 0U, // DSB + 0U, // DUPv16i8gpr + 75U, // DUPv16i8lane + 0U, // DUPv2i32gpr + 75U, // DUPv2i32lane + 0U, // DUPv2i64gpr + 75U, // DUPv2i64lane + 0U, // DUPv4i16gpr + 75U, // DUPv4i16lane + 0U, // DUPv4i32gpr + 75U, // DUPv4i32lane + 0U, // DUPv8i16gpr + 75U, // DUPv8i16lane + 0U, // DUPv8i8gpr + 75U, // DUPv8i8lane + 0U, // EONWrr + 33U, // EONWrs + 0U, // EONXrr + 33U, // EONXrs + 49U, // EORWri + 0U, // EORWrr + 33U, // EORWrs + 57U, // EORXri + 0U, // EORXrr + 33U, // EORXrs + 1033U, // EORv16i8 + 1801U, // EORv8i8 + 0U, // ERET + 18689U, // EXTRWrri + 18689U, // EXTRXrri + 2569U, // EXTv16i8 + 2825U, // EXTv8i8 + 0U, // F128CSEL + 1U, // FABD32 + 1U, // FABD64 + 1289U, // FABDv2f32 + 265U, // FABDv2f64 + 521U, // FABDv4f32 + 0U, // FABSDr + 0U, // FABSSr + 0U, // FABSv2f32 + 0U, // FABSv2f64 + 0U, // FABSv4f32 + 1U, // FACGE32 + 1U, // FACGE64 + 1289U, // FACGEv2f32 + 265U, // FACGEv2f64 + 521U, // FACGEv4f32 + 1U, // FACGT32 + 1U, // FACGT64 + 1289U, // FACGTv2f32 + 265U, // FACGTv2f64 + 521U, // FACGTv4f32 + 1U, // FADDDrr + 1289U, // FADDPv2f32 + 265U, // FADDPv2f64 + 0U, // FADDPv2i32p + 0U, // FADDPv2i64p + 521U, // FADDPv4f32 + 1U, // FADDSrr + 1289U, // FADDv2f32 + 265U, // FADDv2f64 + 521U, // FADDv4f32 + 10497U, // FCCMPDrr + 10497U, // FCCMPEDrr + 10497U, // FCCMPESrr + 10497U, // FCCMPSrr + 1U, // FCMEQ32 + 1U, // FCMEQ64 + 3U, // FCMEQv1i32rz + 3U, // FCMEQv1i64rz + 1289U, // FCMEQv2f32 + 265U, // FCMEQv2f64 + 3U, // FCMEQv2i32rz + 3U, // FCMEQv2i64rz + 521U, // FCMEQv4f32 + 3U, // FCMEQv4i32rz + 1U, // FCMGE32 + 1U, // FCMGE64 + 3U, // FCMGEv1i32rz + 3U, // FCMGEv1i64rz + 1289U, // FCMGEv2f32 + 265U, // FCMGEv2f64 + 3U, // FCMGEv2i32rz + 3U, // FCMGEv2i64rz + 521U, // FCMGEv4f32 + 3U, // FCMGEv4i32rz + 1U, // FCMGT32 + 1U, // FCMGT64 + 3U, // FCMGTv1i32rz + 3U, // FCMGTv1i64rz + 1289U, // FCMGTv2f32 + 265U, // FCMGTv2f64 + 3U, // FCMGTv2i32rz + 3U, // FCMGTv2i64rz + 521U, // FCMGTv4f32 + 3U, // FCMGTv4i32rz + 3U, // FCMLEv1i32rz + 3U, // FCMLEv1i64rz + 3U, // FCMLEv2i32rz + 3U, // FCMLEv2i64rz + 3U, // FCMLEv4i32rz + 3U, // FCMLTv1i32rz + 3U, // FCMLTv1i64rz + 3U, // FCMLTv2i32rz + 3U, // FCMLTv2i64rz + 3U, // FCMLTv4i32rz + 0U, // FCMPDri + 0U, // FCMPDrr + 0U, // FCMPEDri + 0U, // FCMPEDrr + 0U, // FCMPESri + 0U, // FCMPESrr + 0U, // FCMPSri + 0U, // FCMPSrr + 10497U, // FCSELDrrr + 10497U, // FCSELSrrr + 0U, // FCVTASUWDr + 0U, // FCVTASUWSr + 0U, // FCVTASUXDr + 0U, // FCVTASUXSr + 0U, // FCVTASv1i32 + 0U, // FCVTASv1i64 + 0U, // FCVTASv2f32 + 0U, // FCVTASv2f64 + 0U, // FCVTASv4f32 + 0U, // FCVTAUUWDr + 0U, // FCVTAUUWSr + 0U, // FCVTAUUXDr + 0U, // FCVTAUUXSr + 0U, // FCVTAUv1i32 + 0U, // FCVTAUv1i64 + 0U, // FCVTAUv2f32 + 0U, // FCVTAUv2f64 + 0U, // FCVTAUv4f32 + 0U, // FCVTDHr + 0U, // FCVTDSr + 0U, // FCVTHDr + 0U, // FCVTHSr + 0U, // FCVTLv2i32 + 0U, // FCVTLv4i16 + 0U, // FCVTLv4i32 + 0U, // FCVTLv8i16 + 0U, // FCVTMSUWDr + 0U, // FCVTMSUWSr + 0U, // FCVTMSUXDr + 0U, // FCVTMSUXSr + 0U, // FCVTMSv1i32 + 0U, // FCVTMSv1i64 + 0U, // FCVTMSv2f32 + 0U, // FCVTMSv2f64 + 0U, // FCVTMSv4f32 + 0U, // FCVTMUUWDr + 0U, // FCVTMUUWSr + 0U, // FCVTMUUXDr + 0U, // FCVTMUUXSr + 0U, // FCVTMUv1i32 + 0U, // FCVTMUv1i64 + 0U, // FCVTMUv2f32 + 0U, // FCVTMUv2f64 + 0U, // FCVTMUv4f32 + 0U, // FCVTNSUWDr + 0U, // FCVTNSUWSr + 0U, // FCVTNSUXDr + 0U, // FCVTNSUXSr + 0U, // FCVTNSv1i32 + 0U, // FCVTNSv1i64 + 0U, // FCVTNSv2f32 + 0U, // FCVTNSv2f64 + 0U, // FCVTNSv4f32 + 0U, // FCVTNUUWDr + 0U, // FCVTNUUWSr + 0U, // FCVTNUUXDr + 0U, // FCVTNUUXSr + 0U, // FCVTNUv1i32 + 0U, // FCVTNUv1i64 + 0U, // FCVTNUv2f32 + 0U, // FCVTNUv2f64 + 0U, // FCVTNUv4f32 + 0U, // FCVTNv2i32 + 0U, // FCVTNv4i16 + 0U, // FCVTNv4i32 + 0U, // FCVTNv8i16 + 0U, // FCVTPSUWDr + 0U, // FCVTPSUWSr + 0U, // FCVTPSUXDr + 0U, // FCVTPSUXSr + 0U, // FCVTPSv1i32 + 0U, // FCVTPSv1i64 + 0U, // FCVTPSv2f32 + 0U, // FCVTPSv2f64 + 0U, // FCVTPSv4f32 + 0U, // FCVTPUUWDr + 0U, // FCVTPUUWSr + 0U, // FCVTPUUXDr + 0U, // FCVTPUUXSr + 0U, // FCVTPUv1i32 + 0U, // FCVTPUv1i64 + 0U, // FCVTPUv2f32 + 0U, // FCVTPUv2f64 + 0U, // FCVTPUv4f32 + 0U, // FCVTSDr + 0U, // FCVTSHr + 0U, // FCVTXNv1i64 + 0U, // FCVTXNv2f32 + 0U, // FCVTXNv4f32 + 1U, // FCVTZSSWDri + 1U, // FCVTZSSWSri + 1U, // FCVTZSSXDri + 1U, // FCVTZSSXSri + 0U, // FCVTZSUWDr + 0U, // FCVTZSUWSr + 0U, // FCVTZSUXDr + 0U, // FCVTZSUXSr + 1U, // FCVTZS_IntSWDri + 1U, // FCVTZS_IntSWSri + 1U, // FCVTZS_IntSXDri + 1U, // FCVTZS_IntSXSri + 0U, // FCVTZS_IntUWDr + 0U, // FCVTZS_IntUWSr + 0U, // FCVTZS_IntUXDr + 0U, // FCVTZS_IntUXSr + 0U, // FCVTZS_Intv2f32 + 0U, // FCVTZS_Intv2f64 + 0U, // FCVTZS_Intv4f32 + 1U, // FCVTZSd + 1U, // FCVTZSs + 0U, // FCVTZSv1i32 + 0U, // FCVTZSv1i64 + 0U, // FCVTZSv2f32 + 0U, // FCVTZSv2f64 + 1U, // FCVTZSv2i32_shift + 1U, // FCVTZSv2i64_shift + 0U, // FCVTZSv4f32 + 1U, // FCVTZSv4i32_shift + 1U, // FCVTZUSWDri + 1U, // FCVTZUSWSri + 1U, // FCVTZUSXDri + 1U, // FCVTZUSXSri + 0U, // FCVTZUUWDr + 0U, // FCVTZUUWSr + 0U, // FCVTZUUXDr + 0U, // FCVTZUUXSr + 1U, // FCVTZU_IntSWDri + 1U, // FCVTZU_IntSWSri + 1U, // FCVTZU_IntSXDri + 1U, // FCVTZU_IntSXSri + 0U, // FCVTZU_IntUWDr + 0U, // FCVTZU_IntUWSr + 0U, // FCVTZU_IntUXDr + 0U, // FCVTZU_IntUXSr + 0U, // FCVTZU_Intv2f32 + 0U, // FCVTZU_Intv2f64 + 0U, // FCVTZU_Intv4f32 + 1U, // FCVTZUd + 1U, // FCVTZUs + 0U, // FCVTZUv1i32 + 0U, // FCVTZUv1i64 + 0U, // FCVTZUv2f32 + 0U, // FCVTZUv2f64 + 1U, // FCVTZUv2i32_shift + 1U, // FCVTZUv2i64_shift + 0U, // FCVTZUv4f32 + 1U, // FCVTZUv4i32_shift + 1U, // FDIVDrr + 1U, // FDIVSrr + 1289U, // FDIVv2f32 + 265U, // FDIVv2f64 + 521U, // FDIVv4f32 + 18689U, // FMADDDrrr + 18689U, // FMADDSrrr + 1U, // FMAXDrr + 1U, // FMAXNMDrr + 1289U, // FMAXNMPv2f32 + 265U, // FMAXNMPv2f64 + 0U, // FMAXNMPv2i32p + 0U, // FMAXNMPv2i64p + 521U, // FMAXNMPv4f32 + 1U, // FMAXNMSrr + 0U, // FMAXNMVv4i32v + 1289U, // FMAXNMv2f32 + 265U, // FMAXNMv2f64 + 521U, // FMAXNMv4f32 + 1289U, // FMAXPv2f32 + 265U, // FMAXPv2f64 + 0U, // FMAXPv2i32p + 0U, // FMAXPv2i64p + 521U, // FMAXPv4f32 + 1U, // FMAXSrr + 0U, // FMAXVv4i32v + 1289U, // FMAXv2f32 + 265U, // FMAXv2f64 + 521U, // FMAXv4f32 + 1U, // FMINDrr + 1U, // FMINNMDrr + 1289U, // FMINNMPv2f32 + 265U, // FMINNMPv2f64 + 0U, // FMINNMPv2i32p + 0U, // FMINNMPv2i64p + 521U, // FMINNMPv4f32 + 1U, // FMINNMSrr + 0U, // FMINNMVv4i32v + 1289U, // FMINNMv2f32 + 265U, // FMINNMv2f64 + 521U, // FMINNMv4f32 + 1289U, // FMINPv2f32 + 265U, // FMINPv2f64 + 0U, // FMINPv2i32p + 0U, // FMINPv2i64p + 521U, // FMINPv4f32 + 1U, // FMINSrr + 0U, // FMINVv4i32v + 1289U, // FMINv2f32 + 265U, // FMINv2f64 + 521U, // FMINv4f32 + 27665U, // FMLAv1i32_indexed + 27921U, // FMLAv1i64_indexed + 1297U, // FMLAv2f32 + 273U, // FMLAv2f64 + 27665U, // FMLAv2i32_indexed + 27921U, // FMLAv2i64_indexed + 529U, // FMLAv4f32 + 27665U, // FMLAv4i32_indexed + 27665U, // FMLSv1i32_indexed + 27921U, // FMLSv1i64_indexed + 1297U, // FMLSv2f32 + 273U, // FMLSv2f64 + 27665U, // FMLSv2i32_indexed + 27921U, // FMLSv2i64_indexed + 529U, // FMLSv4f32 + 27665U, // FMLSv4i32_indexed + 75U, // FMOVDXHighr + 0U, // FMOVDXr + 0U, // FMOVDi + 0U, // FMOVDr + 0U, // FMOVSWr + 0U, // FMOVSi + 0U, // FMOVSr + 0U, // FMOVWSr + 0U, // FMOVXDHighr + 0U, // FMOVXDr + 0U, // FMOVv2f32_ns + 0U, // FMOVv2f64_ns + 0U, // FMOVv4f32_ns + 18689U, // FMSUBDrrr + 18689U, // FMSUBSrrr + 1U, // FMULDrr + 1U, // FMULSrr + 1U, // FMULX32 + 1U, // FMULX64 + 35849U, // FMULXv1i32_indexed + 36105U, // FMULXv1i64_indexed + 1289U, // FMULXv2f32 + 265U, // FMULXv2f64 + 35849U, // FMULXv2i32_indexed + 36105U, // FMULXv2i64_indexed + 521U, // FMULXv4f32 + 35849U, // FMULXv4i32_indexed + 35849U, // FMULv1i32_indexed + 36105U, // FMULv1i64_indexed + 1289U, // FMULv2f32 + 265U, // FMULv2f64 + 35849U, // FMULv2i32_indexed + 36105U, // FMULv2i64_indexed + 521U, // FMULv4f32 + 35849U, // FMULv4i32_indexed + 0U, // FNEGDr + 0U, // FNEGSr + 0U, // FNEGv2f32 + 0U, // FNEGv2f64 + 0U, // FNEGv4f32 + 18689U, // FNMADDDrrr + 18689U, // FNMADDSrrr + 18689U, // FNMSUBDrrr + 18689U, // FNMSUBSrrr + 1U, // FNMULDrr + 1U, // FNMULSrr + 0U, // FRECPEv1i32 + 0U, // FRECPEv1i64 + 0U, // FRECPEv2f32 + 0U, // FRECPEv2f64 + 0U, // FRECPEv4f32 + 1U, // FRECPS32 + 1U, // FRECPS64 + 1289U, // FRECPSv2f32 + 265U, // FRECPSv2f64 + 521U, // FRECPSv4f32 + 0U, // FRECPXv1i32 + 0U, // FRECPXv1i64 + 0U, // FRINTADr + 0U, // FRINTASr + 0U, // FRINTAv2f32 + 0U, // FRINTAv2f64 + 0U, // FRINTAv4f32 + 0U, // FRINTIDr + 0U, // FRINTISr + 0U, // FRINTIv2f32 + 0U, // FRINTIv2f64 + 0U, // FRINTIv4f32 + 0U, // FRINTMDr + 0U, // FRINTMSr + 0U, // FRINTMv2f32 + 0U, // FRINTMv2f64 + 0U, // FRINTMv4f32 + 0U, // FRINTNDr + 0U, // FRINTNSr + 0U, // FRINTNv2f32 + 0U, // FRINTNv2f64 + 0U, // FRINTNv4f32 + 0U, // FRINTPDr + 0U, // FRINTPSr + 0U, // FRINTPv2f32 + 0U, // FRINTPv2f64 + 0U, // FRINTPv4f32 + 0U, // FRINTXDr + 0U, // FRINTXSr + 0U, // FRINTXv2f32 + 0U, // FRINTXv2f64 + 0U, // FRINTXv4f32 + 0U, // FRINTZDr + 0U, // FRINTZSr + 0U, // FRINTZv2f32 + 0U, // FRINTZv2f64 + 0U, // FRINTZv4f32 + 0U, // FRSQRTEv1i32 + 0U, // FRSQRTEv1i64 + 0U, // FRSQRTEv2f32 + 0U, // FRSQRTEv2f64 + 0U, // FRSQRTEv4f32 + 1U, // FRSQRTS32 + 1U, // FRSQRTS64 + 1289U, // FRSQRTSv2f32 + 265U, // FRSQRTSv2f64 + 521U, // FRSQRTSv4f32 + 0U, // FSQRTDr + 0U, // FSQRTSr + 0U, // FSQRTv2f32 + 0U, // FSQRTv2f64 + 0U, // FSQRTv4f32 + 1U, // FSUBDrr + 1U, // FSUBSrr + 1289U, // FSUBv2f32 + 265U, // FSUBv2f64 + 521U, // FSUBv4f32 + 0U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // INSvi16gpr + 83U, // INSvi16lane + 0U, // INSvi32gpr + 83U, // INSvi32lane + 0U, // INSvi64gpr + 83U, // INSvi64lane + 0U, // INSvi8gpr + 83U, // INSvi8lane + 0U, // ISB + 0U, // LD1Fourv16b + 0U, // LD1Fourv16b_POST + 0U, // LD1Fourv1d + 0U, // LD1Fourv1d_POST + 0U, // LD1Fourv2d + 0U, // LD1Fourv2d_POST + 0U, // LD1Fourv2s + 0U, // LD1Fourv2s_POST + 0U, // LD1Fourv4h + 0U, // LD1Fourv4h_POST + 0U, // LD1Fourv4s + 0U, // LD1Fourv4s_POST + 0U, // LD1Fourv8b + 0U, // LD1Fourv8b_POST + 0U, // LD1Fourv8h + 0U, // LD1Fourv8h_POST + 0U, // LD1Onev16b + 0U, // LD1Onev16b_POST + 0U, // LD1Onev1d + 0U, // LD1Onev1d_POST + 0U, // LD1Onev2d + 0U, // LD1Onev2d_POST + 0U, // LD1Onev2s + 0U, // LD1Onev2s_POST + 0U, // LD1Onev4h + 0U, // LD1Onev4h_POST + 0U, // LD1Onev4s + 0U, // LD1Onev4s_POST + 0U, // LD1Onev8b + 0U, // LD1Onev8b_POST + 0U, // LD1Onev8h + 0U, // LD1Onev8h_POST + 0U, // LD1Rv16b + 0U, // LD1Rv16b_POST + 0U, // LD1Rv1d + 0U, // LD1Rv1d_POST + 0U, // LD1Rv2d + 0U, // LD1Rv2d_POST + 0U, // LD1Rv2s + 0U, // LD1Rv2s_POST + 0U, // LD1Rv4h + 0U, // LD1Rv4h_POST + 0U, // LD1Rv4s + 0U, // LD1Rv4s_POST + 0U, // LD1Rv8b + 0U, // LD1Rv8b_POST + 0U, // LD1Rv8h + 0U, // LD1Rv8h_POST + 0U, // LD1Threev16b + 0U, // LD1Threev16b_POST + 0U, // LD1Threev1d + 0U, // LD1Threev1d_POST + 0U, // LD1Threev2d + 0U, // LD1Threev2d_POST + 0U, // LD1Threev2s + 0U, // LD1Threev2s_POST + 0U, // LD1Threev4h + 0U, // LD1Threev4h_POST + 0U, // LD1Threev4s + 0U, // LD1Threev4s_POST + 0U, // LD1Threev8b + 0U, // LD1Threev8b_POST + 0U, // LD1Threev8h + 0U, // LD1Threev8h_POST + 0U, // LD1Twov16b + 0U, // LD1Twov16b_POST + 0U, // LD1Twov1d + 0U, // LD1Twov1d_POST + 0U, // LD1Twov2d + 0U, // LD1Twov2d_POST + 0U, // LD1Twov2s + 0U, // LD1Twov2s_POST + 0U, // LD1Twov4h + 0U, // LD1Twov4h_POST + 0U, // LD1Twov4s + 0U, // LD1Twov4s_POST + 0U, // LD1Twov8b + 0U, // LD1Twov8b_POST + 0U, // LD1Twov8h + 0U, // LD1Twov8h_POST + 0U, // LD1i16 + 0U, // LD1i16_POST + 0U, // LD1i32 + 0U, // LD1i32_POST + 0U, // LD1i64 + 0U, // LD1i64_POST + 0U, // LD1i8 + 0U, // LD1i8_POST + 0U, // LD2Rv16b + 0U, // LD2Rv16b_POST + 0U, // LD2Rv1d + 0U, // LD2Rv1d_POST + 0U, // LD2Rv2d + 0U, // LD2Rv2d_POST + 0U, // LD2Rv2s + 0U, // LD2Rv2s_POST + 0U, // LD2Rv4h + 0U, // LD2Rv4h_POST + 0U, // LD2Rv4s + 0U, // LD2Rv4s_POST + 0U, // LD2Rv8b + 0U, // LD2Rv8b_POST + 0U, // LD2Rv8h + 0U, // LD2Rv8h_POST + 0U, // LD2Twov16b + 0U, // LD2Twov16b_POST + 0U, // LD2Twov2d + 0U, // LD2Twov2d_POST + 0U, // LD2Twov2s + 0U, // LD2Twov2s_POST + 0U, // LD2Twov4h + 0U, // LD2Twov4h_POST + 0U, // LD2Twov4s + 0U, // LD2Twov4s_POST + 0U, // LD2Twov8b + 0U, // LD2Twov8b_POST + 0U, // LD2Twov8h + 0U, // LD2Twov8h_POST + 0U, // LD2i16 + 0U, // LD2i16_POST + 0U, // LD2i32 + 0U, // LD2i32_POST + 0U, // LD2i64 + 0U, // LD2i64_POST + 0U, // LD2i8 + 0U, // LD2i8_POST + 0U, // LD3Rv16b + 0U, // LD3Rv16b_POST + 0U, // LD3Rv1d + 0U, // LD3Rv1d_POST + 0U, // LD3Rv2d + 0U, // LD3Rv2d_POST + 0U, // LD3Rv2s + 0U, // LD3Rv2s_POST + 0U, // LD3Rv4h + 0U, // LD3Rv4h_POST + 0U, // LD3Rv4s + 0U, // LD3Rv4s_POST + 0U, // LD3Rv8b + 0U, // LD3Rv8b_POST + 0U, // LD3Rv8h + 0U, // LD3Rv8h_POST + 0U, // LD3Threev16b + 0U, // LD3Threev16b_POST + 0U, // LD3Threev2d + 0U, // LD3Threev2d_POST + 0U, // LD3Threev2s + 0U, // LD3Threev2s_POST + 0U, // LD3Threev4h + 0U, // LD3Threev4h_POST + 0U, // LD3Threev4s + 0U, // LD3Threev4s_POST + 0U, // LD3Threev8b + 0U, // LD3Threev8b_POST + 0U, // LD3Threev8h + 0U, // LD3Threev8h_POST + 0U, // LD3i16 + 0U, // LD3i16_POST + 0U, // LD3i32 + 0U, // LD3i32_POST + 0U, // LD3i64 + 0U, // LD3i64_POST + 0U, // LD3i8 + 0U, // LD3i8_POST + 0U, // LD4Fourv16b + 0U, // LD4Fourv16b_POST + 0U, // LD4Fourv2d + 0U, // LD4Fourv2d_POST + 0U, // LD4Fourv2s + 0U, // LD4Fourv2s_POST + 0U, // LD4Fourv4h + 0U, // LD4Fourv4h_POST + 0U, // LD4Fourv4s + 0U, // LD4Fourv4s_POST + 0U, // LD4Fourv8b + 0U, // LD4Fourv8b_POST + 0U, // LD4Fourv8h + 0U, // LD4Fourv8h_POST + 0U, // LD4Rv16b + 0U, // LD4Rv16b_POST + 0U, // LD4Rv1d + 0U, // LD4Rv1d_POST + 0U, // LD4Rv2d + 0U, // LD4Rv2d_POST + 0U, // LD4Rv2s + 0U, // LD4Rv2s_POST + 0U, // LD4Rv4h + 0U, // LD4Rv4h_POST + 0U, // LD4Rv4s + 0U, // LD4Rv4s_POST + 0U, // LD4Rv8b + 0U, // LD4Rv8b_POST + 0U, // LD4Rv8h + 0U, // LD4Rv8h_POST + 0U, // LD4i16 + 0U, // LD4i16_POST + 0U, // LD4i32 + 0U, // LD4i32_POST + 0U, // LD4i64 + 0U, // LD4i64_POST + 0U, // LD4i8 + 0U, // LD4i8_POST + 4U, // LDARB + 4U, // LDARH + 4U, // LDARW + 4U, // LDARX + 3588U, // LDAXPW + 3588U, // LDAXPX + 4U, // LDAXRB + 4U, // LDAXRH + 4U, // LDAXRW + 4U, // LDAXRX + 43268U, // LDNPDi + 51460U, // LDNPQi + 59652U, // LDNPSi + 59652U, // LDNPWi + 43268U, // LDNPXi + 43268U, // LDPDi + 69444U, // LDPDpost + 330052U, // LDPDpre + 51460U, // LDPQi + 77636U, // LDPQpost + 338244U, // LDPQpre + 59652U, // LDPSWi + 85828U, // LDPSWpost + 346436U, // LDPSWpre + 59652U, // LDPSi + 85828U, // LDPSpost + 346436U, // LDPSpre + 59652U, // LDPWi + 85828U, // LDPWpost + 346436U, // LDPWpre + 43268U, // LDPXi + 69444U, // LDPXpost + 330052U, // LDPXpre + 4U, // LDRBBpost + 4161U, // LDRBBpre + 92417U, // LDRBBroW + 100609U, // LDRBBroX + 89U, // LDRBBui + 4U, // LDRBpost + 4161U, // LDRBpre + 92417U, // LDRBroW + 100609U, // LDRBroX + 89U, // LDRBui + 0U, // LDRDl + 4U, // LDRDpost + 4161U, // LDRDpre + 108801U, // LDRDroW + 116993U, // LDRDroX + 97U, // LDRDui + 4U, // LDRHHpost + 4161U, // LDRHHpre + 125185U, // LDRHHroW + 133377U, // LDRHHroX + 105U, // LDRHHui + 4U, // LDRHpost + 4161U, // LDRHpre + 125185U, // LDRHroW + 133377U, // LDRHroX + 105U, // LDRHui + 0U, // LDRQl + 4U, // LDRQpost + 4161U, // LDRQpre + 141569U, // LDRQroW + 149761U, // LDRQroX + 113U, // LDRQui + 4U, // LDRSBWpost + 4161U, // LDRSBWpre + 92417U, // LDRSBWroW + 100609U, // LDRSBWroX + 89U, // LDRSBWui + 4U, // LDRSBXpost + 4161U, // LDRSBXpre + 92417U, // LDRSBXroW + 100609U, // LDRSBXroX + 89U, // LDRSBXui + 4U, // LDRSHWpost + 4161U, // LDRSHWpre + 125185U, // LDRSHWroW + 133377U, // LDRSHWroX + 105U, // LDRSHWui + 4U, // LDRSHXpost + 4161U, // LDRSHXpre + 125185U, // LDRSHXroW + 133377U, // LDRSHXroX + 105U, // LDRSHXui + 0U, // LDRSWl + 4U, // LDRSWpost + 4161U, // LDRSWpre + 157953U, // LDRSWroW + 166145U, // LDRSWroX + 121U, // LDRSWui + 0U, // LDRSl + 4U, // LDRSpost + 4161U, // LDRSpre + 157953U, // LDRSroW + 166145U, // LDRSroX + 121U, // LDRSui + 0U, // LDRWl + 4U, // LDRWpost + 4161U, // LDRWpre + 157953U, // LDRWroW + 166145U, // LDRWroX + 121U, // LDRWui + 0U, // LDRXl + 4U, // LDRXpost + 4161U, // LDRXpre + 108801U, // LDRXroW + 116993U, // LDRXroX + 97U, // LDRXui + 3585U, // LDTRBi + 3585U, // LDTRHi + 3585U, // LDTRSBWi + 3585U, // LDTRSBXi + 3585U, // LDTRSHWi + 3585U, // LDTRSHXi + 3585U, // LDTRSWi + 3585U, // LDTRWi + 3585U, // LDTRXi + 3585U, // LDURBBi + 3585U, // LDURBi + 3585U, // LDURDi + 3585U, // LDURHHi + 3585U, // LDURHi + 3585U, // LDURQi + 3585U, // LDURSBWi + 3585U, // LDURSBXi + 3585U, // LDURSHWi + 3585U, // LDURSHXi + 3585U, // LDURSWi + 3585U, // LDURSi + 3585U, // LDURWi + 3585U, // LDURXi + 3588U, // LDXPW + 3588U, // LDXPX + 4U, // LDXRB + 4U, // LDXRH + 4U, // LDXRW + 4U, // LDXRX + 0U, // LOADgot + 1U, // LSLVWr + 1U, // LSLVXr + 1U, // LSRVWr + 1U, // LSRVXr + 18689U, // MADDWrrr + 18689U, // MADDXrrr + 1041U, // MLAv16i8 + 1297U, // MLAv2i32 + 27665U, // MLAv2i32_indexed + 1553U, // MLAv4i16 + 28945U, // MLAv4i16_indexed + 529U, // MLAv4i32 + 27665U, // MLAv4i32_indexed + 785U, // MLAv8i16 + 28945U, // MLAv8i16_indexed + 1809U, // MLAv8i8 + 1041U, // MLSv16i8 + 1297U, // MLSv2i32 + 27665U, // MLSv2i32_indexed + 1553U, // MLSv4i16 + 28945U, // MLSv4i16_indexed + 529U, // MLSv4i32 + 27665U, // MLSv4i32_indexed + 785U, // MLSv8i16 + 28945U, // MLSv8i16_indexed + 1809U, // MLSv8i8 + 0U, // MOVID + 0U, // MOVIv16b_ns + 0U, // MOVIv2d_ns + 4U, // MOVIv2i32 + 4U, // MOVIv2s_msl + 4U, // MOVIv4i16 + 4U, // MOVIv4i32 + 4U, // MOVIv4s_msl + 0U, // MOVIv8b_ns + 4U, // MOVIv8i16 + 0U, // MOVKWi + 0U, // MOVKXi + 4U, // MOVNWi + 4U, // MOVNXi + 4U, // MOVZWi + 4U, // MOVZXi + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 0U, // MRS + 0U, // MSR + 0U, // MSRpstate + 18689U, // MSUBWrrr + 18689U, // MSUBXrrr + 1033U, // MULv16i8 + 1289U, // MULv2i32 + 35849U, // MULv2i32_indexed + 1545U, // MULv4i16 + 37129U, // MULv4i16_indexed + 521U, // MULv4i32 + 35849U, // MULv4i32_indexed + 777U, // MULv8i16 + 37129U, // MULv8i16_indexed + 1801U, // MULv8i8 + 4U, // MVNIv2i32 + 4U, // MVNIv2s_msl + 4U, // MVNIv4i16 + 4U, // MVNIv4i32 + 4U, // MVNIv4s_msl + 4U, // MVNIv8i16 + 0U, // NEGv16i8 + 0U, // NEGv1i64 + 0U, // NEGv2i32 + 0U, // NEGv2i64 + 0U, // NEGv4i16 + 0U, // NEGv4i32 + 0U, // NEGv8i16 + 0U, // NEGv8i8 + 0U, // NOTv16i8 + 0U, // NOTv8i8 + 0U, // ORNWrr + 33U, // ORNWrs + 0U, // ORNXrr + 33U, // ORNXrs + 1033U, // ORNv16i8 + 1801U, // ORNv8i8 + 49U, // ORRWri + 0U, // ORRWrr + 33U, // ORRWrs + 57U, // ORRXri + 0U, // ORRXrr + 33U, // ORRXrs + 1033U, // ORRv16i8 + 0U, // ORRv2i32 + 0U, // ORRv4i16 + 0U, // ORRv4i32 + 0U, // ORRv8i16 + 1801U, // ORRv8i8 + 1033U, // PMULLv16i8 + 0U, // PMULLv1i64 + 0U, // PMULLv2i64 + 1801U, // PMULLv8i8 + 1033U, // PMULv16i8 + 1801U, // PMULv8i8 + 0U, // PRFMl + 108801U, // PRFMroW + 116993U, // PRFMroX + 97U, // PRFMui + 3585U, // PRFUMi + 265U, // RADDHNv2i64_v2i32 + 273U, // RADDHNv2i64_v4i32 + 521U, // RADDHNv4i32_v4i16 + 529U, // RADDHNv4i32_v8i16 + 785U, // RADDHNv8i16_v16i8 + 777U, // RADDHNv8i16_v8i8 + 0U, // RBITWr + 0U, // RBITXr + 0U, // RBITv16i8 + 0U, // RBITv8i8 + 0U, // RET + 0U, // RET_ReallyLR + 0U, // REV16Wr + 0U, // REV16Xr + 0U, // REV16v16i8 + 0U, // REV16v8i8 + 0U, // REV32Xr + 0U, // REV32v16i8 + 0U, // REV32v4i16 + 0U, // REV32v8i16 + 0U, // REV32v8i8 + 0U, // REV64v16i8 + 0U, // REV64v2i32 + 0U, // REV64v4i16 + 0U, // REV64v4i32 + 0U, // REV64v8i16 + 0U, // REV64v8i8 + 0U, // REVWr + 0U, // REVXr + 1U, // RORVWr + 1U, // RORVXr + 65U, // RSHRNv16i8_shift + 1U, // RSHRNv2i32_shift + 1U, // RSHRNv4i16_shift + 65U, // RSHRNv4i32_shift + 65U, // RSHRNv8i16_shift + 1U, // RSHRNv8i8_shift + 265U, // RSUBHNv2i64_v2i32 + 273U, // RSUBHNv2i64_v4i32 + 521U, // RSUBHNv4i32_v4i16 + 529U, // RSUBHNv4i32_v8i16 + 785U, // RSUBHNv8i16_v16i8 + 777U, // RSUBHNv8i16_v8i8 + 1041U, // SABALv16i8_v8i16 + 1297U, // SABALv2i32_v2i64 + 1553U, // SABALv4i16_v4i32 + 529U, // SABALv4i32_v2i64 + 785U, // SABALv8i16_v4i32 + 1809U, // SABALv8i8_v8i16 + 1041U, // SABAv16i8 + 1297U, // SABAv2i32 + 1553U, // SABAv4i16 + 529U, // SABAv4i32 + 785U, // SABAv8i16 + 1809U, // SABAv8i8 + 1033U, // SABDLv16i8_v8i16 + 1289U, // SABDLv2i32_v2i64 + 1545U, // SABDLv4i16_v4i32 + 521U, // SABDLv4i32_v2i64 + 777U, // SABDLv8i16_v4i32 + 1801U, // SABDLv8i8_v8i16 + 1033U, // SABDv16i8 + 1289U, // SABDv2i32 + 1545U, // SABDv4i16 + 521U, // SABDv4i32 + 777U, // SABDv8i16 + 1801U, // SABDv8i8 + 0U, // SADALPv16i8_v8i16 + 0U, // SADALPv2i32_v1i64 + 0U, // SADALPv4i16_v2i32 + 0U, // SADALPv4i32_v2i64 + 0U, // SADALPv8i16_v4i32 + 0U, // SADALPv8i8_v4i16 + 0U, // SADDLPv16i8_v8i16 + 0U, // SADDLPv2i32_v1i64 + 0U, // SADDLPv4i16_v2i32 + 0U, // SADDLPv4i32_v2i64 + 0U, // SADDLPv8i16_v4i32 + 0U, // SADDLPv8i8_v4i16 + 0U, // SADDLVv16i8v + 0U, // SADDLVv4i16v + 0U, // SADDLVv4i32v + 0U, // SADDLVv8i16v + 0U, // SADDLVv8i8v + 1033U, // SADDLv16i8_v8i16 + 1289U, // SADDLv2i32_v2i64 + 1545U, // SADDLv4i16_v4i32 + 521U, // SADDLv4i32_v2i64 + 777U, // SADDLv8i16_v4i32 + 1801U, // SADDLv8i8_v8i16 + 1033U, // SADDWv16i8_v8i16 + 1289U, // SADDWv2i32_v2i64 + 1545U, // SADDWv4i16_v4i32 + 521U, // SADDWv4i32_v2i64 + 777U, // SADDWv8i16_v4i32 + 1801U, // SADDWv8i8_v8i16 + 1U, // SBCSWr + 1U, // SBCSXr + 1U, // SBCWr + 1U, // SBCXr + 18689U, // SBFMWri + 18689U, // SBFMXri + 1U, // SCVTFSWDri + 1U, // SCVTFSWSri + 1U, // SCVTFSXDri + 1U, // SCVTFSXSri + 0U, // SCVTFUWDri + 0U, // SCVTFUWSri + 0U, // SCVTFUXDri + 0U, // SCVTFUXSri + 1U, // SCVTFd + 1U, // SCVTFs + 0U, // SCVTFv1i32 + 0U, // SCVTFv1i64 + 0U, // SCVTFv2f32 + 0U, // SCVTFv2f64 + 1U, // SCVTFv2i32_shift + 1U, // SCVTFv2i64_shift + 0U, // SCVTFv4f32 + 1U, // SCVTFv4i32_shift + 1U, // SDIVWr + 1U, // SDIVXr + 1U, // SDIV_IntWr + 1U, // SDIV_IntXr + 529U, // SHA1Crrr + 0U, // SHA1Hrr + 529U, // SHA1Mrrr + 529U, // SHA1Prrr + 529U, // SHA1SU0rrr + 0U, // SHA1SU1rr + 529U, // SHA256H2rrr + 529U, // SHA256Hrrr + 0U, // SHA256SU0rr + 529U, // SHA256SU1rrr + 1033U, // SHADDv16i8 + 1289U, // SHADDv2i32 + 1545U, // SHADDv4i16 + 521U, // SHADDv4i32 + 777U, // SHADDv8i16 + 1801U, // SHADDv8i8 + 4U, // SHLLv16i8 + 4U, // SHLLv2i32 + 4U, // SHLLv4i16 + 4U, // SHLLv4i32 + 5U, // SHLLv8i16 + 5U, // SHLLv8i8 + 1U, // SHLd + 1U, // SHLv16i8_shift + 1U, // SHLv2i32_shift + 1U, // SHLv2i64_shift + 1U, // SHLv4i16_shift + 1U, // SHLv4i32_shift + 1U, // SHLv8i16_shift + 1U, // SHLv8i8_shift + 65U, // SHRNv16i8_shift + 1U, // SHRNv2i32_shift + 1U, // SHRNv4i16_shift + 65U, // SHRNv4i32_shift + 65U, // SHRNv8i16_shift + 1U, // SHRNv8i8_shift + 1033U, // SHSUBv16i8 + 1289U, // SHSUBv2i32 + 1545U, // SHSUBv4i16 + 521U, // SHSUBv4i32 + 777U, // SHSUBv8i16 + 1801U, // SHSUBv8i8 + 65U, // SLId + 65U, // SLIv16i8_shift + 65U, // SLIv2i32_shift + 65U, // SLIv2i64_shift + 65U, // SLIv4i16_shift + 65U, // SLIv4i32_shift + 65U, // SLIv8i16_shift + 65U, // SLIv8i8_shift + 18689U, // SMADDLrrr + 1033U, // SMAXPv16i8 + 1289U, // SMAXPv2i32 + 1545U, // SMAXPv4i16 + 521U, // SMAXPv4i32 + 777U, // SMAXPv8i16 + 1801U, // SMAXPv8i8 + 0U, // SMAXVv16i8v + 0U, // SMAXVv4i16v + 0U, // SMAXVv4i32v + 0U, // SMAXVv8i16v + 0U, // SMAXVv8i8v + 1033U, // SMAXv16i8 + 1289U, // SMAXv2i32 + 1545U, // SMAXv4i16 + 521U, // SMAXv4i32 + 777U, // SMAXv8i16 + 1801U, // SMAXv8i8 + 0U, // SMC + 1033U, // SMINPv16i8 + 1289U, // SMINPv2i32 + 1545U, // SMINPv4i16 + 521U, // SMINPv4i32 + 777U, // SMINPv8i16 + 1801U, // SMINPv8i8 + 0U, // SMINVv16i8v + 0U, // SMINVv4i16v + 0U, // SMINVv4i32v + 0U, // SMINVv8i16v + 0U, // SMINVv8i8v + 1033U, // SMINv16i8 + 1289U, // SMINv2i32 + 1545U, // SMINv4i16 + 521U, // SMINv4i32 + 777U, // SMINv8i16 + 1801U, // SMINv8i8 + 1041U, // SMLALv16i8_v8i16 + 27665U, // SMLALv2i32_indexed + 1297U, // SMLALv2i32_v2i64 + 28945U, // SMLALv4i16_indexed + 1553U, // SMLALv4i16_v4i32 + 27665U, // SMLALv4i32_indexed + 529U, // SMLALv4i32_v2i64 + 28945U, // SMLALv8i16_indexed + 785U, // SMLALv8i16_v4i32 + 1809U, // SMLALv8i8_v8i16 + 1041U, // SMLSLv16i8_v8i16 + 27665U, // SMLSLv2i32_indexed + 1297U, // SMLSLv2i32_v2i64 + 28945U, // SMLSLv4i16_indexed + 1553U, // SMLSLv4i16_v4i32 + 27665U, // SMLSLv4i32_indexed + 529U, // SMLSLv4i32_v2i64 + 28945U, // SMLSLv8i16_indexed + 785U, // SMLSLv8i16_v4i32 + 1809U, // SMLSLv8i8_v8i16 + 75U, // SMOVvi16to32 + 75U, // SMOVvi16to64 + 75U, // SMOVvi32to64 + 75U, // SMOVvi8to32 + 75U, // SMOVvi8to64 + 18689U, // SMSUBLrrr + 1U, // SMULHrr + 1033U, // SMULLv16i8_v8i16 + 35849U, // SMULLv2i32_indexed + 1289U, // SMULLv2i32_v2i64 + 37129U, // SMULLv4i16_indexed + 1545U, // SMULLv4i16_v4i32 + 35849U, // SMULLv4i32_indexed + 521U, // SMULLv4i32_v2i64 + 37129U, // SMULLv8i16_indexed + 777U, // SMULLv8i16_v4i32 + 1801U, // SMULLv8i8_v8i16 + 0U, // SQABSv16i8 + 0U, // SQABSv1i16 + 0U, // SQABSv1i32 + 0U, // SQABSv1i64 + 0U, // SQABSv1i8 + 0U, // SQABSv2i32 + 0U, // SQABSv2i64 + 0U, // SQABSv4i16 + 0U, // SQABSv4i32 + 0U, // SQABSv8i16 + 0U, // SQABSv8i8 + 1033U, // SQADDv16i8 + 1U, // SQADDv1i16 + 1U, // SQADDv1i32 + 1U, // SQADDv1i64 + 1U, // SQADDv1i8 + 1289U, // SQADDv2i32 + 265U, // SQADDv2i64 + 1545U, // SQADDv4i16 + 521U, // SQADDv4i32 + 777U, // SQADDv8i16 + 1801U, // SQADDv8i8 + 65U, // SQDMLALi16 + 65U, // SQDMLALi32 + 28945U, // SQDMLALv1i32_indexed + 27665U, // SQDMLALv1i64_indexed + 27665U, // SQDMLALv2i32_indexed + 1297U, // SQDMLALv2i32_v2i64 + 28945U, // SQDMLALv4i16_indexed + 1553U, // SQDMLALv4i16_v4i32 + 27665U, // SQDMLALv4i32_indexed + 529U, // SQDMLALv4i32_v2i64 + 28945U, // SQDMLALv8i16_indexed + 785U, // SQDMLALv8i16_v4i32 + 65U, // SQDMLSLi16 + 65U, // SQDMLSLi32 + 28945U, // SQDMLSLv1i32_indexed + 27665U, // SQDMLSLv1i64_indexed + 27665U, // SQDMLSLv2i32_indexed + 1297U, // SQDMLSLv2i32_v2i64 + 28945U, // SQDMLSLv4i16_indexed + 1553U, // SQDMLSLv4i16_v4i32 + 27665U, // SQDMLSLv4i32_indexed + 529U, // SQDMLSLv4i32_v2i64 + 28945U, // SQDMLSLv8i16_indexed + 785U, // SQDMLSLv8i16_v4i32 + 1U, // SQDMULHv1i16 + 37129U, // SQDMULHv1i16_indexed + 1U, // SQDMULHv1i32 + 35849U, // SQDMULHv1i32_indexed + 1289U, // SQDMULHv2i32 + 35849U, // SQDMULHv2i32_indexed + 1545U, // SQDMULHv4i16 + 37129U, // SQDMULHv4i16_indexed + 521U, // SQDMULHv4i32 + 35849U, // SQDMULHv4i32_indexed + 777U, // SQDMULHv8i16 + 37129U, // SQDMULHv8i16_indexed + 1U, // SQDMULLi16 + 1U, // SQDMULLi32 + 37129U, // SQDMULLv1i32_indexed + 35849U, // SQDMULLv1i64_indexed + 35849U, // SQDMULLv2i32_indexed + 1289U, // SQDMULLv2i32_v2i64 + 37129U, // SQDMULLv4i16_indexed + 1545U, // SQDMULLv4i16_v4i32 + 35849U, // SQDMULLv4i32_indexed + 521U, // SQDMULLv4i32_v2i64 + 37129U, // SQDMULLv8i16_indexed + 777U, // SQDMULLv8i16_v4i32 + 0U, // SQNEGv16i8 + 0U, // SQNEGv1i16 + 0U, // SQNEGv1i32 + 0U, // SQNEGv1i64 + 0U, // SQNEGv1i8 + 0U, // SQNEGv2i32 + 0U, // SQNEGv2i64 + 0U, // SQNEGv4i16 + 0U, // SQNEGv4i32 + 0U, // SQNEGv8i16 + 0U, // SQNEGv8i8 + 1U, // SQRDMULHv1i16 + 37129U, // SQRDMULHv1i16_indexed + 1U, // SQRDMULHv1i32 + 35849U, // SQRDMULHv1i32_indexed + 1289U, // SQRDMULHv2i32 + 35849U, // SQRDMULHv2i32_indexed + 1545U, // SQRDMULHv4i16 + 37129U, // SQRDMULHv4i16_indexed + 521U, // SQRDMULHv4i32 + 35849U, // SQRDMULHv4i32_indexed + 777U, // SQRDMULHv8i16 + 37129U, // SQRDMULHv8i16_indexed + 1033U, // SQRSHLv16i8 + 1U, // SQRSHLv1i16 + 1U, // SQRSHLv1i32 + 1U, // SQRSHLv1i64 + 1U, // SQRSHLv1i8 + 1289U, // SQRSHLv2i32 + 265U, // SQRSHLv2i64 + 1545U, // SQRSHLv4i16 + 521U, // SQRSHLv4i32 + 777U, // SQRSHLv8i16 + 1801U, // SQRSHLv8i8 + 1U, // SQRSHRNb + 1U, // SQRSHRNh + 1U, // SQRSHRNs + 65U, // SQRSHRNv16i8_shift + 1U, // SQRSHRNv2i32_shift + 1U, // SQRSHRNv4i16_shift + 65U, // SQRSHRNv4i32_shift + 65U, // SQRSHRNv8i16_shift + 1U, // SQRSHRNv8i8_shift + 1U, // SQRSHRUNb + 1U, // SQRSHRUNh + 1U, // SQRSHRUNs + 65U, // SQRSHRUNv16i8_shift + 1U, // SQRSHRUNv2i32_shift + 1U, // SQRSHRUNv4i16_shift + 65U, // SQRSHRUNv4i32_shift + 65U, // SQRSHRUNv8i16_shift + 1U, // SQRSHRUNv8i8_shift + 1U, // SQSHLUb + 1U, // SQSHLUd + 1U, // SQSHLUh + 1U, // SQSHLUs + 1U, // SQSHLUv16i8_shift + 1U, // SQSHLUv2i32_shift + 1U, // SQSHLUv2i64_shift + 1U, // SQSHLUv4i16_shift + 1U, // SQSHLUv4i32_shift + 1U, // SQSHLUv8i16_shift + 1U, // SQSHLUv8i8_shift + 1U, // SQSHLb + 1U, // SQSHLd + 1U, // SQSHLh + 1U, // SQSHLs + 1033U, // SQSHLv16i8 + 1U, // SQSHLv16i8_shift + 1U, // SQSHLv1i16 + 1U, // SQSHLv1i32 + 1U, // SQSHLv1i64 + 1U, // SQSHLv1i8 + 1289U, // SQSHLv2i32 + 1U, // SQSHLv2i32_shift + 265U, // SQSHLv2i64 + 1U, // SQSHLv2i64_shift + 1545U, // SQSHLv4i16 + 1U, // SQSHLv4i16_shift + 521U, // SQSHLv4i32 + 1U, // SQSHLv4i32_shift + 777U, // SQSHLv8i16 + 1U, // SQSHLv8i16_shift + 1801U, // SQSHLv8i8 + 1U, // SQSHLv8i8_shift + 1U, // SQSHRNb + 1U, // SQSHRNh + 1U, // SQSHRNs + 65U, // SQSHRNv16i8_shift + 1U, // SQSHRNv2i32_shift + 1U, // SQSHRNv4i16_shift + 65U, // SQSHRNv4i32_shift + 65U, // SQSHRNv8i16_shift + 1U, // SQSHRNv8i8_shift + 1U, // SQSHRUNb + 1U, // SQSHRUNh + 1U, // SQSHRUNs + 65U, // SQSHRUNv16i8_shift + 1U, // SQSHRUNv2i32_shift + 1U, // SQSHRUNv4i16_shift + 65U, // SQSHRUNv4i32_shift + 65U, // SQSHRUNv8i16_shift + 1U, // SQSHRUNv8i8_shift + 1033U, // SQSUBv16i8 + 1U, // SQSUBv1i16 + 1U, // SQSUBv1i32 + 1U, // SQSUBv1i64 + 1U, // SQSUBv1i8 + 1289U, // SQSUBv2i32 + 265U, // SQSUBv2i64 + 1545U, // SQSUBv4i16 + 521U, // SQSUBv4i32 + 777U, // SQSUBv8i16 + 1801U, // SQSUBv8i8 + 0U, // SQXTNv16i8 + 0U, // SQXTNv1i16 + 0U, // SQXTNv1i32 + 0U, // SQXTNv1i8 + 0U, // SQXTNv2i32 + 0U, // SQXTNv4i16 + 0U, // SQXTNv4i32 + 0U, // SQXTNv8i16 + 0U, // SQXTNv8i8 + 0U, // SQXTUNv16i8 + 0U, // SQXTUNv1i16 + 0U, // SQXTUNv1i32 + 0U, // SQXTUNv1i8 + 0U, // SQXTUNv2i32 + 0U, // SQXTUNv4i16 + 0U, // SQXTUNv4i32 + 0U, // SQXTUNv8i16 + 0U, // SQXTUNv8i8 + 1033U, // SRHADDv16i8 + 1289U, // SRHADDv2i32 + 1545U, // SRHADDv4i16 + 521U, // SRHADDv4i32 + 777U, // SRHADDv8i16 + 1801U, // SRHADDv8i8 + 65U, // SRId + 65U, // SRIv16i8_shift + 65U, // SRIv2i32_shift + 65U, // SRIv2i64_shift + 65U, // SRIv4i16_shift + 65U, // SRIv4i32_shift + 65U, // SRIv8i16_shift + 65U, // SRIv8i8_shift + 1033U, // SRSHLv16i8 + 1U, // SRSHLv1i64 + 1289U, // SRSHLv2i32 + 265U, // SRSHLv2i64 + 1545U, // SRSHLv4i16 + 521U, // SRSHLv4i32 + 777U, // SRSHLv8i16 + 1801U, // SRSHLv8i8 + 1U, // SRSHRd + 1U, // SRSHRv16i8_shift + 1U, // SRSHRv2i32_shift + 1U, // SRSHRv2i64_shift + 1U, // SRSHRv4i16_shift + 1U, // SRSHRv4i32_shift + 1U, // SRSHRv8i16_shift + 1U, // SRSHRv8i8_shift + 65U, // SRSRAd + 65U, // SRSRAv16i8_shift + 65U, // SRSRAv2i32_shift + 65U, // SRSRAv2i64_shift + 65U, // SRSRAv4i16_shift + 65U, // SRSRAv4i32_shift + 65U, // SRSRAv8i16_shift + 65U, // SRSRAv8i8_shift + 1U, // SSHLLv16i8_shift + 1U, // SSHLLv2i32_shift + 1U, // SSHLLv4i16_shift + 1U, // SSHLLv4i32_shift + 1U, // SSHLLv8i16_shift + 1U, // SSHLLv8i8_shift + 1033U, // SSHLv16i8 + 1U, // SSHLv1i64 + 1289U, // SSHLv2i32 + 265U, // SSHLv2i64 + 1545U, // SSHLv4i16 + 521U, // SSHLv4i32 + 777U, // SSHLv8i16 + 1801U, // SSHLv8i8 + 1U, // SSHRd + 1U, // SSHRv16i8_shift + 1U, // SSHRv2i32_shift + 1U, // SSHRv2i64_shift + 1U, // SSHRv4i16_shift + 1U, // SSHRv4i32_shift + 1U, // SSHRv8i16_shift + 1U, // SSHRv8i8_shift + 65U, // SSRAd + 65U, // SSRAv16i8_shift + 65U, // SSRAv2i32_shift + 65U, // SSRAv2i64_shift + 65U, // SSRAv4i16_shift + 65U, // SSRAv4i32_shift + 65U, // SSRAv8i16_shift + 65U, // SSRAv8i8_shift + 1033U, // SSUBLv16i8_v8i16 + 1289U, // SSUBLv2i32_v2i64 + 1545U, // SSUBLv4i16_v4i32 + 521U, // SSUBLv4i32_v2i64 + 777U, // SSUBLv8i16_v4i32 + 1801U, // SSUBLv8i8_v8i16 + 1033U, // SSUBWv16i8_v8i16 + 1289U, // SSUBWv2i32_v2i64 + 1545U, // SSUBWv4i16_v4i32 + 521U, // SSUBWv4i32_v2i64 + 777U, // SSUBWv8i16_v4i32 + 1801U, // SSUBWv8i8_v8i16 + 0U, // ST1Fourv16b + 0U, // ST1Fourv16b_POST + 0U, // ST1Fourv1d + 0U, // ST1Fourv1d_POST + 0U, // ST1Fourv2d + 0U, // ST1Fourv2d_POST + 0U, // ST1Fourv2s + 0U, // ST1Fourv2s_POST + 0U, // ST1Fourv4h + 0U, // ST1Fourv4h_POST + 0U, // ST1Fourv4s + 0U, // ST1Fourv4s_POST + 0U, // ST1Fourv8b + 0U, // ST1Fourv8b_POST + 0U, // ST1Fourv8h + 0U, // ST1Fourv8h_POST + 0U, // ST1Onev16b + 0U, // ST1Onev16b_POST + 0U, // ST1Onev1d + 0U, // ST1Onev1d_POST + 0U, // ST1Onev2d + 0U, // ST1Onev2d_POST + 0U, // ST1Onev2s + 0U, // ST1Onev2s_POST + 0U, // ST1Onev4h + 0U, // ST1Onev4h_POST + 0U, // ST1Onev4s + 0U, // ST1Onev4s_POST + 0U, // ST1Onev8b + 0U, // ST1Onev8b_POST + 0U, // ST1Onev8h + 0U, // ST1Onev8h_POST + 0U, // ST1Threev16b + 0U, // ST1Threev16b_POST + 0U, // ST1Threev1d + 0U, // ST1Threev1d_POST + 0U, // ST1Threev2d + 0U, // ST1Threev2d_POST + 0U, // ST1Threev2s + 0U, // ST1Threev2s_POST + 0U, // ST1Threev4h + 0U, // ST1Threev4h_POST + 0U, // ST1Threev4s + 0U, // ST1Threev4s_POST + 0U, // ST1Threev8b + 0U, // ST1Threev8b_POST + 0U, // ST1Threev8h + 0U, // ST1Threev8h_POST + 0U, // ST1Twov16b + 0U, // ST1Twov16b_POST + 0U, // ST1Twov1d + 0U, // ST1Twov1d_POST + 0U, // ST1Twov2d + 0U, // ST1Twov2d_POST + 0U, // ST1Twov2s + 0U, // ST1Twov2s_POST + 0U, // ST1Twov4h + 0U, // ST1Twov4h_POST + 0U, // ST1Twov4s + 0U, // ST1Twov4s_POST + 0U, // ST1Twov8b + 0U, // ST1Twov8b_POST + 0U, // ST1Twov8h + 0U, // ST1Twov8h_POST + 0U, // ST1i16 + 0U, // ST1i16_POST + 0U, // ST1i32 + 0U, // ST1i32_POST + 0U, // ST1i64 + 0U, // ST1i64_POST + 0U, // ST1i8 + 0U, // ST1i8_POST + 0U, // ST2Twov16b + 0U, // ST2Twov16b_POST + 0U, // ST2Twov2d + 0U, // ST2Twov2d_POST + 0U, // ST2Twov2s + 0U, // ST2Twov2s_POST + 0U, // ST2Twov4h + 0U, // ST2Twov4h_POST + 0U, // ST2Twov4s + 0U, // ST2Twov4s_POST + 0U, // ST2Twov8b + 0U, // ST2Twov8b_POST + 0U, // ST2Twov8h + 0U, // ST2Twov8h_POST + 0U, // ST2i16 + 0U, // ST2i16_POST + 0U, // ST2i32 + 0U, // ST2i32_POST + 0U, // ST2i64 + 0U, // ST2i64_POST + 0U, // ST2i8 + 0U, // ST2i8_POST + 0U, // ST3Threev16b + 0U, // ST3Threev16b_POST + 0U, // ST3Threev2d + 0U, // ST3Threev2d_POST + 0U, // ST3Threev2s + 0U, // ST3Threev2s_POST + 0U, // ST3Threev4h + 0U, // ST3Threev4h_POST + 0U, // ST3Threev4s + 0U, // ST3Threev4s_POST + 0U, // ST3Threev8b + 0U, // ST3Threev8b_POST + 0U, // ST3Threev8h + 0U, // ST3Threev8h_POST + 0U, // ST3i16 + 0U, // ST3i16_POST + 0U, // ST3i32 + 0U, // ST3i32_POST + 0U, // ST3i64 + 0U, // ST3i64_POST + 0U, // ST3i8 + 0U, // ST3i8_POST + 0U, // ST4Fourv16b + 0U, // ST4Fourv16b_POST + 0U, // ST4Fourv2d + 0U, // ST4Fourv2d_POST + 0U, // ST4Fourv2s + 0U, // ST4Fourv2s_POST + 0U, // ST4Fourv4h + 0U, // ST4Fourv4h_POST + 0U, // ST4Fourv4s + 0U, // ST4Fourv4s_POST + 0U, // ST4Fourv8b + 0U, // ST4Fourv8b_POST + 0U, // ST4Fourv8h + 0U, // ST4Fourv8h_POST + 0U, // ST4i16 + 0U, // ST4i16_POST + 0U, // ST4i32 + 0U, // ST4i32_POST + 0U, // ST4i64 + 0U, // ST4i64_POST + 0U, // ST4i8 + 0U, // ST4i8_POST + 4U, // STLRB + 4U, // STLRH + 4U, // STLRW + 4U, // STLRX + 4609U, // STLXPW + 4609U, // STLXPX + 3588U, // STLXRB + 3588U, // STLXRH + 3588U, // STLXRW + 3588U, // STLXRX + 43268U, // STNPDi + 51460U, // STNPQi + 59652U, // STNPSi + 59652U, // STNPWi + 43268U, // STNPXi + 43268U, // STPDi + 69444U, // STPDpost + 330052U, // STPDpre + 51460U, // STPQi + 77636U, // STPQpost + 338244U, // STPQpre + 59652U, // STPSi + 85828U, // STPSpost + 346436U, // STPSpre + 59652U, // STPWi + 85828U, // STPWpost + 346436U, // STPWpre + 43268U, // STPXi + 69444U, // STPXpost + 330052U, // STPXpre + 4U, // STRBBpost + 4161U, // STRBBpre + 92417U, // STRBBroW + 100609U, // STRBBroX + 89U, // STRBBui + 4U, // STRBpost + 4161U, // STRBpre + 92417U, // STRBroW + 100609U, // STRBroX + 89U, // STRBui + 4U, // STRDpost + 4161U, // STRDpre + 108801U, // STRDroW + 116993U, // STRDroX + 97U, // STRDui + 4U, // STRHHpost + 4161U, // STRHHpre + 125185U, // STRHHroW + 133377U, // STRHHroX + 105U, // STRHHui + 4U, // STRHpost + 4161U, // STRHpre + 125185U, // STRHroW + 133377U, // STRHroX + 105U, // STRHui + 4U, // STRQpost + 4161U, // STRQpre + 141569U, // STRQroW + 149761U, // STRQroX + 113U, // STRQui + 4U, // STRSpost + 4161U, // STRSpre + 157953U, // STRSroW + 166145U, // STRSroX + 121U, // STRSui + 4U, // STRWpost + 4161U, // STRWpre + 157953U, // STRWroW + 166145U, // STRWroX + 121U, // STRWui + 4U, // STRXpost + 4161U, // STRXpre + 108801U, // STRXroW + 116993U, // STRXroX + 97U, // STRXui + 3585U, // STTRBi + 3585U, // STTRHi + 3585U, // STTRWi + 3585U, // STTRXi + 3585U, // STURBBi + 3585U, // STURBi + 3585U, // STURDi + 3585U, // STURHHi + 3585U, // STURHi + 3585U, // STURQi + 3585U, // STURSi + 3585U, // STURWi + 3585U, // STURXi + 4609U, // STXPW + 4609U, // STXPX + 3588U, // STXRB + 3588U, // STXRH + 3588U, // STXRW + 3588U, // STXRX + 265U, // SUBHNv2i64_v2i32 + 273U, // SUBHNv2i64_v4i32 + 521U, // SUBHNv4i32_v4i16 + 529U, // SUBHNv4i32_v8i16 + 785U, // SUBHNv8i16_v16i8 + 777U, // SUBHNv8i16_v8i8 + 25U, // SUBSWri + 0U, // SUBSWrr + 33U, // SUBSWrs + 41U, // SUBSWrx + 25U, // SUBSXri + 0U, // SUBSXrr + 33U, // SUBSXrs + 41U, // SUBSXrx + 2049U, // SUBSXrx64 + 25U, // SUBWri + 0U, // SUBWrr + 33U, // SUBWrs + 41U, // SUBWrx + 25U, // SUBXri + 0U, // SUBXrr + 33U, // SUBXrs + 41U, // SUBXrx + 2049U, // SUBXrx64 + 1033U, // SUBv16i8 + 1U, // SUBv1i64 + 1289U, // SUBv2i32 + 265U, // SUBv2i64 + 1545U, // SUBv4i16 + 521U, // SUBv4i32 + 777U, // SUBv8i16 + 1801U, // SUBv8i8 + 0U, // SUQADDv16i8 + 0U, // SUQADDv1i16 + 0U, // SUQADDv1i32 + 0U, // SUQADDv1i64 + 0U, // SUQADDv1i8 + 0U, // SUQADDv2i32 + 0U, // SUQADDv2i64 + 0U, // SUQADDv4i16 + 0U, // SUQADDv4i32 + 0U, // SUQADDv8i16 + 0U, // SUQADDv8i8 + 0U, // SVC + 129U, // SYSLxt + 0U, // SYSxt + 0U, // TBLv16i8Four + 0U, // TBLv16i8One + 0U, // TBLv16i8Three + 0U, // TBLv16i8Two + 0U, // TBLv8i8Four + 0U, // TBLv8i8One + 0U, // TBLv8i8Three + 0U, // TBLv8i8Two + 137U, // TBNZW + 137U, // TBNZX + 0U, // TBXv16i8Four + 0U, // TBXv16i8One + 0U, // TBXv16i8Three + 0U, // TBXv16i8Two + 0U, // TBXv8i8Four + 0U, // TBXv8i8One + 0U, // TBXv8i8Three + 0U, // TBXv8i8Two + 137U, // TBZW + 137U, // TBZX + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TLSDESCCALL + 0U, // TLSDESC_BLR + 1033U, // TRN1v16i8 + 1289U, // TRN1v2i32 + 265U, // TRN1v2i64 + 1545U, // TRN1v4i16 + 521U, // TRN1v4i32 + 777U, // TRN1v8i16 + 1801U, // TRN1v8i8 + 1033U, // TRN2v16i8 + 1289U, // TRN2v2i32 + 265U, // TRN2v2i64 + 1545U, // TRN2v4i16 + 521U, // TRN2v4i32 + 777U, // TRN2v8i16 + 1801U, // TRN2v8i8 + 1041U, // UABALv16i8_v8i16 + 1297U, // UABALv2i32_v2i64 + 1553U, // UABALv4i16_v4i32 + 529U, // UABALv4i32_v2i64 + 785U, // UABALv8i16_v4i32 + 1809U, // UABALv8i8_v8i16 + 1041U, // UABAv16i8 + 1297U, // UABAv2i32 + 1553U, // UABAv4i16 + 529U, // UABAv4i32 + 785U, // UABAv8i16 + 1809U, // UABAv8i8 + 1033U, // UABDLv16i8_v8i16 + 1289U, // UABDLv2i32_v2i64 + 1545U, // UABDLv4i16_v4i32 + 521U, // UABDLv4i32_v2i64 + 777U, // UABDLv8i16_v4i32 + 1801U, // UABDLv8i8_v8i16 + 1033U, // UABDv16i8 + 1289U, // UABDv2i32 + 1545U, // UABDv4i16 + 521U, // UABDv4i32 + 777U, // UABDv8i16 + 1801U, // UABDv8i8 + 0U, // UADALPv16i8_v8i16 + 0U, // UADALPv2i32_v1i64 + 0U, // UADALPv4i16_v2i32 + 0U, // UADALPv4i32_v2i64 + 0U, // UADALPv8i16_v4i32 + 0U, // UADALPv8i8_v4i16 + 0U, // UADDLPv16i8_v8i16 + 0U, // UADDLPv2i32_v1i64 + 0U, // UADDLPv4i16_v2i32 + 0U, // UADDLPv4i32_v2i64 + 0U, // UADDLPv8i16_v4i32 + 0U, // UADDLPv8i8_v4i16 + 0U, // UADDLVv16i8v + 0U, // UADDLVv4i16v + 0U, // UADDLVv4i32v + 0U, // UADDLVv8i16v + 0U, // UADDLVv8i8v + 1033U, // UADDLv16i8_v8i16 + 1289U, // UADDLv2i32_v2i64 + 1545U, // UADDLv4i16_v4i32 + 521U, // UADDLv4i32_v2i64 + 777U, // UADDLv8i16_v4i32 + 1801U, // UADDLv8i8_v8i16 + 1033U, // UADDWv16i8_v8i16 + 1289U, // UADDWv2i32_v2i64 + 1545U, // UADDWv4i16_v4i32 + 521U, // UADDWv4i32_v2i64 + 777U, // UADDWv8i16_v4i32 + 1801U, // UADDWv8i8_v8i16 + 18689U, // UBFMWri + 18689U, // UBFMXri + 1U, // UCVTFSWDri + 1U, // UCVTFSWSri + 1U, // UCVTFSXDri + 1U, // UCVTFSXSri + 0U, // UCVTFUWDri + 0U, // UCVTFUWSri + 0U, // UCVTFUXDri + 0U, // UCVTFUXSri + 1U, // UCVTFd + 1U, // UCVTFs + 0U, // UCVTFv1i32 + 0U, // UCVTFv1i64 + 0U, // UCVTFv2f32 + 0U, // UCVTFv2f64 + 1U, // UCVTFv2i32_shift + 1U, // UCVTFv2i64_shift + 0U, // UCVTFv4f32 + 1U, // UCVTFv4i32_shift + 1U, // UDIVWr + 1U, // UDIVXr + 1U, // UDIV_IntWr + 1U, // UDIV_IntXr + 1033U, // UHADDv16i8 + 1289U, // UHADDv2i32 + 1545U, // UHADDv4i16 + 521U, // UHADDv4i32 + 777U, // UHADDv8i16 + 1801U, // UHADDv8i8 + 1033U, // UHSUBv16i8 + 1289U, // UHSUBv2i32 + 1545U, // UHSUBv4i16 + 521U, // UHSUBv4i32 + 777U, // UHSUBv8i16 + 1801U, // UHSUBv8i8 + 18689U, // UMADDLrrr + 1033U, // UMAXPv16i8 + 1289U, // UMAXPv2i32 + 1545U, // UMAXPv4i16 + 521U, // UMAXPv4i32 + 777U, // UMAXPv8i16 + 1801U, // UMAXPv8i8 + 0U, // UMAXVv16i8v + 0U, // UMAXVv4i16v + 0U, // UMAXVv4i32v + 0U, // UMAXVv8i16v + 0U, // UMAXVv8i8v + 1033U, // UMAXv16i8 + 1289U, // UMAXv2i32 + 1545U, // UMAXv4i16 + 521U, // UMAXv4i32 + 777U, // UMAXv8i16 + 1801U, // UMAXv8i8 + 1033U, // UMINPv16i8 + 1289U, // UMINPv2i32 + 1545U, // UMINPv4i16 + 521U, // UMINPv4i32 + 777U, // UMINPv8i16 + 1801U, // UMINPv8i8 + 0U, // UMINVv16i8v + 0U, // UMINVv4i16v + 0U, // UMINVv4i32v + 0U, // UMINVv8i16v + 0U, // UMINVv8i8v + 1033U, // UMINv16i8 + 1289U, // UMINv2i32 + 1545U, // UMINv4i16 + 521U, // UMINv4i32 + 777U, // UMINv8i16 + 1801U, // UMINv8i8 + 1041U, // UMLALv16i8_v8i16 + 27665U, // UMLALv2i32_indexed + 1297U, // UMLALv2i32_v2i64 + 28945U, // UMLALv4i16_indexed + 1553U, // UMLALv4i16_v4i32 + 27665U, // UMLALv4i32_indexed + 529U, // UMLALv4i32_v2i64 + 28945U, // UMLALv8i16_indexed + 785U, // UMLALv8i16_v4i32 + 1809U, // UMLALv8i8_v8i16 + 1041U, // UMLSLv16i8_v8i16 + 27665U, // UMLSLv2i32_indexed + 1297U, // UMLSLv2i32_v2i64 + 28945U, // UMLSLv4i16_indexed + 1553U, // UMLSLv4i16_v4i32 + 27665U, // UMLSLv4i32_indexed + 529U, // UMLSLv4i32_v2i64 + 28945U, // UMLSLv8i16_indexed + 785U, // UMLSLv8i16_v4i32 + 1809U, // UMLSLv8i8_v8i16 + 75U, // UMOVvi16 + 75U, // UMOVvi32 + 75U, // UMOVvi64 + 75U, // UMOVvi8 + 18689U, // UMSUBLrrr + 1U, // UMULHrr + 1033U, // UMULLv16i8_v8i16 + 35849U, // UMULLv2i32_indexed + 1289U, // UMULLv2i32_v2i64 + 37129U, // UMULLv4i16_indexed + 1545U, // UMULLv4i16_v4i32 + 35849U, // UMULLv4i32_indexed + 521U, // UMULLv4i32_v2i64 + 37129U, // UMULLv8i16_indexed + 777U, // UMULLv8i16_v4i32 + 1801U, // UMULLv8i8_v8i16 + 1033U, // UQADDv16i8 + 1U, // UQADDv1i16 + 1U, // UQADDv1i32 + 1U, // UQADDv1i64 + 1U, // UQADDv1i8 + 1289U, // UQADDv2i32 + 265U, // UQADDv2i64 + 1545U, // UQADDv4i16 + 521U, // UQADDv4i32 + 777U, // UQADDv8i16 + 1801U, // UQADDv8i8 + 1033U, // UQRSHLv16i8 + 1U, // UQRSHLv1i16 + 1U, // UQRSHLv1i32 + 1U, // UQRSHLv1i64 + 1U, // UQRSHLv1i8 + 1289U, // UQRSHLv2i32 + 265U, // UQRSHLv2i64 + 1545U, // UQRSHLv4i16 + 521U, // UQRSHLv4i32 + 777U, // UQRSHLv8i16 + 1801U, // UQRSHLv8i8 + 1U, // UQRSHRNb + 1U, // UQRSHRNh + 1U, // UQRSHRNs + 65U, // UQRSHRNv16i8_shift + 1U, // UQRSHRNv2i32_shift + 1U, // UQRSHRNv4i16_shift + 65U, // UQRSHRNv4i32_shift + 65U, // UQRSHRNv8i16_shift + 1U, // UQRSHRNv8i8_shift + 1U, // UQSHLb + 1U, // UQSHLd + 1U, // UQSHLh + 1U, // UQSHLs + 1033U, // UQSHLv16i8 + 1U, // UQSHLv16i8_shift + 1U, // UQSHLv1i16 + 1U, // UQSHLv1i32 + 1U, // UQSHLv1i64 + 1U, // UQSHLv1i8 + 1289U, // UQSHLv2i32 + 1U, // UQSHLv2i32_shift + 265U, // UQSHLv2i64 + 1U, // UQSHLv2i64_shift + 1545U, // UQSHLv4i16 + 1U, // UQSHLv4i16_shift + 521U, // UQSHLv4i32 + 1U, // UQSHLv4i32_shift + 777U, // UQSHLv8i16 + 1U, // UQSHLv8i16_shift + 1801U, // UQSHLv8i8 + 1U, // UQSHLv8i8_shift + 1U, // UQSHRNb + 1U, // UQSHRNh + 1U, // UQSHRNs + 65U, // UQSHRNv16i8_shift + 1U, // UQSHRNv2i32_shift + 1U, // UQSHRNv4i16_shift + 65U, // UQSHRNv4i32_shift + 65U, // UQSHRNv8i16_shift + 1U, // UQSHRNv8i8_shift + 1033U, // UQSUBv16i8 + 1U, // UQSUBv1i16 + 1U, // UQSUBv1i32 + 1U, // UQSUBv1i64 + 1U, // UQSUBv1i8 + 1289U, // UQSUBv2i32 + 265U, // UQSUBv2i64 + 1545U, // UQSUBv4i16 + 521U, // UQSUBv4i32 + 777U, // UQSUBv8i16 + 1801U, // UQSUBv8i8 + 0U, // UQXTNv16i8 + 0U, // UQXTNv1i16 + 0U, // UQXTNv1i32 + 0U, // UQXTNv1i8 + 0U, // UQXTNv2i32 + 0U, // UQXTNv4i16 + 0U, // UQXTNv4i32 + 0U, // UQXTNv8i16 + 0U, // UQXTNv8i8 + 0U, // URECPEv2i32 + 0U, // URECPEv4i32 + 1033U, // URHADDv16i8 + 1289U, // URHADDv2i32 + 1545U, // URHADDv4i16 + 521U, // URHADDv4i32 + 777U, // URHADDv8i16 + 1801U, // URHADDv8i8 + 1033U, // URSHLv16i8 + 1U, // URSHLv1i64 + 1289U, // URSHLv2i32 + 265U, // URSHLv2i64 + 1545U, // URSHLv4i16 + 521U, // URSHLv4i32 + 777U, // URSHLv8i16 + 1801U, // URSHLv8i8 + 1U, // URSHRd + 1U, // URSHRv16i8_shift + 1U, // URSHRv2i32_shift + 1U, // URSHRv2i64_shift + 1U, // URSHRv4i16_shift + 1U, // URSHRv4i32_shift + 1U, // URSHRv8i16_shift + 1U, // URSHRv8i8_shift + 0U, // URSQRTEv2i32 + 0U, // URSQRTEv4i32 + 65U, // URSRAd + 65U, // URSRAv16i8_shift + 65U, // URSRAv2i32_shift + 65U, // URSRAv2i64_shift + 65U, // URSRAv4i16_shift + 65U, // URSRAv4i32_shift + 65U, // URSRAv8i16_shift + 65U, // URSRAv8i8_shift + 1U, // USHLLv16i8_shift + 1U, // USHLLv2i32_shift + 1U, // USHLLv4i16_shift + 1U, // USHLLv4i32_shift + 1U, // USHLLv8i16_shift + 1U, // USHLLv8i8_shift + 1033U, // USHLv16i8 + 1U, // USHLv1i64 + 1289U, // USHLv2i32 + 265U, // USHLv2i64 + 1545U, // USHLv4i16 + 521U, // USHLv4i32 + 777U, // USHLv8i16 + 1801U, // USHLv8i8 + 1U, // USHRd + 1U, // USHRv16i8_shift + 1U, // USHRv2i32_shift + 1U, // USHRv2i64_shift + 1U, // USHRv4i16_shift + 1U, // USHRv4i32_shift + 1U, // USHRv8i16_shift + 1U, // USHRv8i8_shift + 0U, // USQADDv16i8 + 0U, // USQADDv1i16 + 0U, // USQADDv1i32 + 0U, // USQADDv1i64 + 0U, // USQADDv1i8 + 0U, // USQADDv2i32 + 0U, // USQADDv2i64 + 0U, // USQADDv4i16 + 0U, // USQADDv4i32 + 0U, // USQADDv8i16 + 0U, // USQADDv8i8 + 65U, // USRAd + 65U, // USRAv16i8_shift + 65U, // USRAv2i32_shift + 65U, // USRAv2i64_shift + 65U, // USRAv4i16_shift + 65U, // USRAv4i32_shift + 65U, // USRAv8i16_shift + 65U, // USRAv8i8_shift + 1033U, // USUBLv16i8_v8i16 + 1289U, // USUBLv2i32_v2i64 + 1545U, // USUBLv4i16_v4i32 + 521U, // USUBLv4i32_v2i64 + 777U, // USUBLv8i16_v4i32 + 1801U, // USUBLv8i8_v8i16 + 1033U, // USUBWv16i8_v8i16 + 1289U, // USUBWv2i32_v2i64 + 1545U, // USUBWv4i16_v4i32 + 521U, // USUBWv4i32_v2i64 + 777U, // USUBWv8i16_v4i32 + 1801U, // USUBWv8i8_v8i16 + 1033U, // UZP1v16i8 + 1289U, // UZP1v2i32 + 265U, // UZP1v2i64 + 1545U, // UZP1v4i16 + 521U, // UZP1v4i32 + 777U, // UZP1v8i16 + 1801U, // UZP1v8i8 + 1033U, // UZP2v16i8 + 1289U, // UZP2v2i32 + 265U, // UZP2v2i64 + 1545U, // UZP2v4i16 + 521U, // UZP2v4i32 + 777U, // UZP2v8i16 + 1801U, // UZP2v8i8 + 0U, // XTNv16i8 + 0U, // XTNv2i32 + 0U, // XTNv4i16 + 0U, // XTNv4i32 + 0U, // XTNv8i16 + 0U, // XTNv8i8 + 1033U, // ZIP1v16i8 + 1289U, // ZIP1v2i32 + 265U, // ZIP1v2i64 + 1545U, // ZIP1v4i16 + 521U, // ZIP1v4i32 + 777U, // ZIP1v8i16 + 1801U, // ZIP1v8i8 + 1033U, // ZIP2v16i8 + 1289U, // ZIP2v2i32 + 265U, // ZIP2v2i64 + 1545U, // ZIP2v4i16 + 521U, // ZIP2v4i32 + 777U, // ZIP2v8i16 + 1801U, // ZIP2v8i8 + 0U + }; + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, + /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, + /* 20 */ 'l', 'd', '1', 9, 0, + /* 25 */ 't', 'r', 'n', '1', 9, 0, + /* 31 */ 'z', 'i', 'p', '1', 9, 0, + /* 37 */ 'u', 'z', 'p', '1', 9, 0, + /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0, + /* 50 */ 's', 't', '1', 9, 0, + /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, + /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, + /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0, + /* 82 */ 'l', 'd', '2', 9, 0, + /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, + /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, + /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, + /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, + /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, + /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, + /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, + /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, + /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, + /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, + /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, + /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, + /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, + /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, + /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, + /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, + /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, + /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, + /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, + /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, + /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, + /* 327 */ 't', 'r', 'n', '2', 9, 0, + /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, + /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, + /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, + /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, + /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, + /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, + /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, + /* 396 */ 'z', 'i', 'p', '2', 9, 0, + /* 402 */ 'u', 'z', 'p', '2', 9, 0, + /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0, + /* 415 */ 's', 't', '2', 9, 0, + /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, + /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, + /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, + /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, + /* 452 */ 'l', 'd', '3', 9, 0, + /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0, + /* 464 */ 's', 't', '3', 9, 0, + /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0, + /* 476 */ 'l', 'd', '4', 9, 0, + /* 481 */ 's', 't', '4', 9, 0, + /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0, + /* 493 */ 's', 'a', 'b', 'a', 9, 0, + /* 499 */ 'u', 'a', 'b', 'a', 9, 0, + /* 505 */ 'f', 'm', 'l', 'a', 9, 0, + /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0, + /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0, + /* 525 */ 's', 's', 'r', 'a', 9, 0, + /* 531 */ 'u', 's', 'r', 'a', 9, 0, + /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, + /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, + /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, + /* 562 */ 'd', 'm', 'b', 9, 0, + /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0, + /* 574 */ 'l', 'd', 'r', 'b', 9, 0, + /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0, + /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0, + /* 594 */ 's', 't', 'r', 'b', 9, 0, + /* 600 */ 's', 't', 't', 'r', 'b', 9, 0, + /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0, + /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0, + /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, + /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0, + /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, + /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0, + /* 651 */ 'd', 's', 'b', 9, 0, + /* 656 */ 'i', 's', 'b', 9, 0, + /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0, + /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, + /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, + /* 684 */ 'f', 's', 'u', 'b', 9, 0, + /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0, + /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0, + /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0, + /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, + /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0, + /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0, + /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0, + /* 740 */ 's', 'b', 'c', 9, 0, + /* 745 */ 'a', 'd', 'c', 9, 0, + /* 750 */ 'b', 'i', 'c', 9, 0, + /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, + /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0, + /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0, + /* 777 */ 'h', 'v', 'c', 9, 0, + /* 782 */ 's', 'v', 'c', 9, 0, + /* 787 */ 'f', 'a', 'b', 'd', 9, 0, + /* 793 */ 's', 'a', 'b', 'd', 9, 0, + /* 799 */ 'u', 'a', 'b', 'd', 9, 0, + /* 805 */ 'f', 'a', 'd', 'd', 9, 0, + /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, + /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, + /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0, + /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0, + /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0, + /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, + /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, + /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, + /* 872 */ 'a', 'n', 'd', 9, 0, + /* 877 */ 'a', 'e', 's', 'd', 9, 0, + /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0, + /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0, + /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0, + /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, + /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, + /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, + /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0, + /* 935 */ 'a', 'e', 's', 'e', 9, 0, + /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, + /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, + /* 959 */ 'b', 'i', 'f', 9, 0, + /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0, + /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0, + /* 978 */ 'f', 'n', 'e', 'g', 9, 0, + /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0, + /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0, + /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0, + /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, + /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, + /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, + /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, + /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, + /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0, + /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0, + /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0, + /* 1071 */ 'l', 'd', 'r', 'h', 9, 0, + /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0, + /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0, + /* 1091 */ 's', 't', 'r', 'h', 9, 0, + /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0, + /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0, + /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0, + /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, + /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0, + /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, + /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0, + /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0, + /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, + /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, + /* 1171 */ 'c', 'm', 'h', 'i', 9, 0, + /* 1177 */ 's', 'l', 'i', 9, 0, + /* 1182 */ 'm', 'v', 'n', 'i', 9, 0, + /* 1188 */ 's', 'r', 'i', 9, 0, + /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, + /* 1201 */ 'm', 'o', 'v', 'i', 9, 0, + /* 1207 */ 'b', 'r', 'k', 9, 0, + /* 1212 */ 'm', 'o', 'v', 'k', 9, 0, + /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0, + /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0, + /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, + /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0, + /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0, + /* 1255 */ 't', 'b', 'l', 9, 0, + /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, + /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, + /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0, + /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0, + /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0, + /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0, + /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, + /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, + /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0, + /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0, + /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0, + /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0, + /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0, + /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, + /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, + /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0, + /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0, + /* 1385 */ 's', 's', 'h', 'l', 9, 0, + /* 1391 */ 'u', 's', 'h', 'l', 9, 0, + /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0, + /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0, + /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, + /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0, + /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0, + /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0, + /* 1441 */ 'b', 's', 'l', 9, 0, + /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, + /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0, + /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0, + /* 1469 */ 's', 'y', 's', 'l', 9, 0, + /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0, + /* 1482 */ 'f', 'm', 'u', 'l', 9, 0, + /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0, + /* 1495 */ 'p', 'm', 'u', 'l', 9, 0, + /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0, + /* 1508 */ 's', 'b', 'f', 'm', 9, 0, + /* 1514 */ 'u', 'b', 'f', 'm', 9, 0, + /* 1520 */ 'p', 'r', 'f', 'm', 9, 0, + /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, + /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, + /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, + /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0, + /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, + /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, + /* 1573 */ 'f', 'm', 'i', 'n', 9, 0, + /* 1579 */ 's', 'm', 'i', 'n', 9, 0, + /* 1585 */ 'u', 'm', 'i', 'n', 9, 0, + /* 1591 */ 'c', 'c', 'm', 'n', 9, 0, + /* 1597 */ 'e', 'o', 'n', 9, 0, + /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, + /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, + /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, + /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, + /* 1636 */ 'o', 'r', 'n', 9, 0, + /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, + /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0, + /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0, + /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0, + /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, + /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, + /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, + /* 1697 */ 'm', 'o', 'v', 'n', 9, 0, + /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, + /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0, + /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0, + /* 1725 */ 'l', 'd', 'p', 9, 0, + /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, + /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, + /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, + /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, + /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0, + /* 1769 */ 'f', 'c', 'm', 'p', 9, 0, + /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, + /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, + /* 1793 */ 'l', 'd', 'n', 'p', 9, 0, + /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0, + /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0, + /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0, + /* 1820 */ 's', 't', 'n', 'p', 9, 0, + /* 1826 */ 'a', 'd', 'r', 'p', 9, 0, + /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, + /* 1840 */ 's', 't', 'p', 9, 0, + /* 1845 */ 'd', 'u', 'p', 9, 0, + /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0, + /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0, + /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0, + /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0, + /* 1878 */ 'l', 'd', 'x', 'p', 9, 0, + /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0, + /* 1891 */ 's', 't', 'x', 'p', 9, 0, + /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0, + /* 1904 */ 'l', 'd', '1', 'r', 9, 0, + /* 1910 */ 'l', 'd', '2', 'r', 9, 0, + /* 1916 */ 'l', 'd', '3', 'r', 9, 0, + /* 1922 */ 'l', 'd', '4', 'r', 9, 0, + /* 1928 */ 'l', 'd', 'a', 'r', 9, 0, + /* 1934 */ 'b', 'r', 9, 0, + /* 1938 */ 'a', 'd', 'r', 9, 0, + /* 1943 */ 'l', 'd', 'r', 9, 0, + /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0, + /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0, + /* 1962 */ 's', 's', 'h', 'r', 9, 0, + /* 1968 */ 'u', 's', 'h', 'r', 9, 0, + /* 1974 */ 'b', 'l', 'r', 9, 0, + /* 1979 */ 's', 't', 'l', 'r', 9, 0, + /* 1985 */ 'e', 'o', 'r', 9, 0, + /* 1990 */ 'r', 'o', 'r', 9, 0, + /* 1995 */ 'o', 'r', 'r', 9, 0, + /* 2000 */ 'a', 's', 'r', 9, 0, + /* 2005 */ 'l', 's', 'r', 9, 0, + /* 2010 */ 'm', 's', 'r', 9, 0, + /* 2015 */ 'l', 'd', 't', 'r', 9, 0, + /* 2021 */ 's', 't', 'r', 9, 0, + /* 2026 */ 's', 't', 't', 'r', 9, 0, + /* 2032 */ 'e', 'x', 't', 'r', 9, 0, + /* 2038 */ 'l', 'd', 'u', 'r', 9, 0, + /* 2044 */ 's', 't', 'u', 'r', 9, 0, + /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0, + /* 2057 */ 'l', 'd', 'x', 'r', 9, 0, + /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0, + /* 2070 */ 's', 't', 'x', 'r', 9, 0, + /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, + /* 2084 */ 'f', 'a', 'b', 's', 9, 0, + /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0, + /* 2097 */ 's', 'u', 'b', 's', 9, 0, + /* 2103 */ 's', 'b', 'c', 's', 9, 0, + /* 2109 */ 'a', 'd', 'c', 's', 9, 0, + /* 2115 */ 'b', 'i', 'c', 's', 9, 0, + /* 2121 */ 'a', 'd', 'd', 's', 9, 0, + /* 2127 */ 'a', 'n', 'd', 's', 9, 0, + /* 2133 */ 'c', 'm', 'h', 's', 9, 0, + /* 2139 */ 'c', 'l', 's', 9, 0, + /* 2144 */ 'f', 'm', 'l', 's', 9, 0, + /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, + /* 2158 */ 'i', 'n', 's', 9, 0, + /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, + /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, + /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, + /* 2187 */ 'm', 'r', 's', 9, 0, + /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, + /* 2201 */ 's', 'y', 's', 9, 0, + /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, + /* 2214 */ 'r', 'e', 't', 9, 0, + /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0, + /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0, + /* 2233 */ 'r', 'b', 'i', 't', 9, 0, + /* 2239 */ 'h', 'l', 't', 9, 0, + /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0, + /* 2251 */ 'c', 'n', 't', 9, 0, + /* 2256 */ 'n', 'o', 't', 9, 0, + /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0, + /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0, + /* 2275 */ 'f', 'c', 'v', 't', 9, 0, + /* 2281 */ 'e', 'x', 't', 9, 0, + /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, + /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, + /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, + /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, + /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, + /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, + /* 2334 */ 'a', 'd', 'd', 'v', 9, 0, + /* 2340 */ 'r', 'e', 'v', 9, 0, + /* 2345 */ 'f', 'd', 'i', 'v', 9, 0, + /* 2351 */ 's', 'd', 'i', 'v', 9, 0, + /* 2357 */ 'u', 'd', 'i', 'v', 9, 0, + /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, + /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, + /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, + /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, + /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0, + /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0, + /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0, + /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0, + /* 2425 */ 'f', 'm', 'o', 'v', 9, 0, + /* 2431 */ 's', 'm', 'o', 'v', 9, 0, + /* 2437 */ 'u', 'm', 'o', 'v', 9, 0, + /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0, + /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0, + /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0, + /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, + /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0, + /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0, + /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, + /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0, + /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0, + /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0, + /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0, + /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, + /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, + /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, + /* 2547 */ 'f', 'm', 'a', 'x', 9, 0, + /* 2553 */ 's', 'm', 'a', 'x', 9, 0, + /* 2559 */ 'u', 'm', 'a', 'x', 9, 0, + /* 2565 */ 't', 'b', 'x', 9, 0, + /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, + /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0, + /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0, + /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, + /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, + /* 2609 */ 'c', 'b', 'z', 9, 0, + /* 2614 */ 't', 'b', 'z', 9, 0, + /* 2619 */ 'c', 'l', 'z', 9, 0, + /* 2624 */ 'c', 'b', 'n', 'z', 9, 0, + /* 2630 */ 't', 'b', 'n', 'z', 9, 0, + /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, + /* 2644 */ 'm', 'o', 'v', 'z', 9, 0, + /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, + /* 2664 */ 'h', 'i', 'n', 't', 32, 0, + /* 2670 */ 'b', '.', 0, + /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2718 */ 'd', 'r', 'p', 's', 0, + /* 2723 */ 'e', 'r', 'e', 't', 0, + }; +#endif + + // Emit the opcode for the instruction. + uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; + uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; + uint64_t Bits = (Bits2 << 32) | Bits1; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 6 bits for 40 unique commands. + //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63); + switch ((Bits >> 12) & 63) { + default: // unreachable. + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET + return; + break; + case 1: + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand(MI, 0, O); + break; + case 2: + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... + printOperand(MI, 0, O); + break; + case 3: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand(MI, 1, O); + break; + case 4: + // B, BL + printAlignedLabel(MI, 0, O); + return; + break; + case 5: + // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC + printHexImm(MI, 0, O); + return; + break; + case 6: + // Bcc + printCondCode(MI, 0, O); + SStream_concat0(O, "\t"); + printAlignedLabel(MI, 1, O); + return; + break; + case 7: + // DMB, DSB, ISB + printBarrierOption(MI, 0, O); + return; + break; + case 8: + // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind... + printOperand(MI, 1, O); + break; + case 9: + // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... + printTypedVectorList(MI, 0, O, 16, 'b', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 10: + // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... + printTypedVectorList(MI, 1, O, 16, 'b', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 11: + // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... + printTypedVectorList(MI, 0, O, 1, 'd', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 12: + // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 1, 'd', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 13: + // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... + printTypedVectorList(MI, 0, O, 2, 'd', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 14: + // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 2, 'd', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 15: + // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... + printTypedVectorList(MI, 0, O, 2, 's', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 16: + // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 2, 's', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 17: + // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... + printTypedVectorList(MI, 0, O, 4, 'h', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 18: + // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 4, 'h', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 19: + // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... + printTypedVectorList(MI, 0, O, 4, 's', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 20: + // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 4, 's', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 21: + // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... + printTypedVectorList(MI, 0, O, 8, 'b', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 22: + // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 8, 'b', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 23: + // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... + printTypedVectorList(MI, 0, O, 8, 'h', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 24: + // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 8, 'h', MRI); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 25: + // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... + printTypedVectorList(MI, 1, O, 0, 'h', MRI); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 26: + // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST + printTypedVectorList(MI, 2, O, 0, 'h', MRI); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 27: + // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... + printTypedVectorList(MI, 1, O, 0, 's', MRI); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 28: + // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST + printTypedVectorList(MI, 2, O, 0, 's', MRI); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 29: + // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... + printTypedVectorList(MI, 1, O, 0, 'd', MRI); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 30: + // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST + printTypedVectorList(MI, 2, O, 0, 'd', MRI); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 31: + // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... + printTypedVectorList(MI, 1, O, 0, 'b', MRI); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 32: + // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST + printTypedVectorList(MI, 2, O, 0, 'b', MRI); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 33: + // MSR + printMSRSystemRegister(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 34: + // MSRpstate + printSystemPStateField(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 35: + // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi + printPrefetchOp(MI, 0, O); + break; + case 36: + // ST1i16, ST2i16, ST3i16, ST4i16 + printTypedVectorList(MI, 0, O, 0, 'h', MRI); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 37: + // ST1i32, ST2i32, ST3i32, ST4i32 + printTypedVectorList(MI, 0, O, 0, 's', MRI); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 38: + // ST1i64, ST2i64, ST3i64, ST4i64 + printTypedVectorList(MI, 0, O, 0, 'd', MRI); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 39: + // ST1i8, ST2i8, ST3i8, ST4i8 + printTypedVectorList(MI, 0, O, 0, 'b', MRI); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + } + + + // Fragment 1 encoded into 6 bits for 41 unique commands. + //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63); + switch ((Bits >> 18) & 63) { + default: // unreachable. + case 0: + // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + break; + case 1: + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... + SStream_concat0(O, ", "); + break; + case 2: + // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... + SStream_concat0(O, ".2s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + break; + case 3: + // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + break; + case 4: + // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... + SStream_concat0(O, ".4h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + break; + case 5: + // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... + SStream_concat0(O, ".4s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + break; + case 6: + // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... + SStream_concat0(O, ".8h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + break; + case 7: + // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + break; + case 8: + // BLR, BR, CLREX, RET, TLSDESCCALL + return; + break; + case 9: + // FCMPDri, FCMPEDri, FCMPESri, FCMPSri + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0.0); + return; + break; + case 10: + // FMOVXDHighr, INSvi64gpr, INSvi64lane + SStream_concat0(O, ".d"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 11: + // INSvi16gpr, INSvi16lane + SStream_concat0(O, ".h"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 12: + // INSvi32gpr, INSvi32lane + SStream_concat0(O, ".s"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 13: + // INSvi8gpr, INSvi8lane + SStream_concat0(O, ".b"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 14: + // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... + printPostIncOperand2(MI, 3, O, 64); + return; + break; + case 15: + // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... + printPostIncOperand2(MI, 3, O, 32); + return; + break; + case 16: + // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... + printPostIncOperand2(MI, 3, O, 16); + return; + break; + case 17: + // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... + printPostIncOperand2(MI, 3, O, 8); + return; + break; + case 18: + // LD1Rv16b_POST, LD1Rv8b_POST + printPostIncOperand2(MI, 3, O, 1); + return; + break; + case 19: + // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... + printPostIncOperand2(MI, 3, O, 4); + return; + break; + case 20: + // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST + printPostIncOperand2(MI, 3, O, 2); + return; + break; + case 21: + // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... + printPostIncOperand2(MI, 3, O, 48); + return; + break; + case 22: + // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... + printPostIncOperand2(MI, 3, O, 24); + return; + break; + case 23: + // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 24: + // LD1i16_POST, LD2i8_POST + printPostIncOperand2(MI, 5, O, 2); + return; + break; + case 25: + // LD1i32_POST, LD2i16_POST, LD4i8_POST + printPostIncOperand2(MI, 5, O, 4); + return; + break; + case 26: + // LD1i64_POST, LD2i32_POST, LD4i16_POST + printPostIncOperand2(MI, 5, O, 8); + return; + break; + case 27: + // LD1i8_POST + printPostIncOperand2(MI, 5, O, 1); + return; + break; + case 28: + // LD2i64_POST, LD4i32_POST + printPostIncOperand2(MI, 5, O, 16); + return; + break; + case 29: + // LD3Rv16b_POST, LD3Rv8b_POST + printPostIncOperand2(MI, 3, O, 3); + return; + break; + case 30: + // LD3Rv2s_POST, LD3Rv4s_POST + printPostIncOperand2(MI, 3, O, 12); + return; + break; + case 31: + // LD3Rv4h_POST, LD3Rv8h_POST + printPostIncOperand2(MI, 3, O, 6); + return; + break; + case 32: + // LD3i16_POST + printPostIncOperand2(MI, 5, O, 6); + return; + break; + case 33: + // LD3i32_POST + printPostIncOperand2(MI, 5, O, 12); + return; + break; + case 34: + // LD3i64_POST + printPostIncOperand2(MI, 5, O, 24); + return; + break; + case 35: + // LD3i8_POST + printPostIncOperand2(MI, 5, O, 3); + return; + break; + case 36: + // LD4i64_POST + printPostIncOperand2(MI, 5, O, 32); + return; + break; + case 37: + // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,... + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + break; + case 38: + // PMULLv1i64, PMULLv2i64 + SStream_concat0(O, ".1q, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); + printVRegOperand(MI, 1, O); + break; + case 39: + // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... + SStream_concat0(O, ".1d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + break; + case 40: + // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + } + + + // Fragment 2 encoded into 5 bits for 28 unique commands. + //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); + switch ((Bits >> 24) & 31) { + default: // unreachable. + case 0: + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand(MI, 1, O); + break; + case 1: + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD... + printOperand(MI, 1, O); + break; + case 2: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand(MI, 2, O); + break; + case 3: + // ADRP + printAdrpLabel(MI, 1, O); + return; + break; + case 4: + // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe... + printOperand(MI, 2, O); + break; + case 5: + // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... + printHexImm(MI, 2, O); + printShifter(MI, 3, O); + return; + break; + case 6: + // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... + printAlignedLabel(MI, 1, O); + return; + break; + case 7: + // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns + printFPImmOperand(MI, 1, O); + return; + break; + case 8: + // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr + printOperand(MI, 3, O); + return; + break; + case 9: + // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane + printVRegOperand(MI, 3, O); + break; + case 10: + // MOVID, MOVIv2d_ns + printSIMDType10Operand(MI, 1, O); + return; + break; + case 11: + // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... + printHexImm(MI, 1, O); + break; + case 12: + // MRS + printMRSSystemRegister(MI, 1, O); + return; + break; + case 13: + // PMULLv1i64 + SStream_concat0(O, ".1d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + printVRegOperand(MI, 2, O); + SStream_concat0(O, ".1d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + return; + break; + case 14: + // PMULLv2i64 + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + printVRegOperand(MI, 2, O); + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + return; + break; + case 15: + // ST1i16_POST, ST2i8_POST + printPostIncOperand2(MI, 4, O, 2); + return; + break; + case 16: + // ST1i32_POST, ST2i16_POST, ST4i8_POST + printPostIncOperand2(MI, 4, O, 4); + return; + break; + case 17: + // ST1i64_POST, ST2i32_POST, ST4i16_POST + printPostIncOperand2(MI, 4, O, 8); + return; + break; + case 18: + // ST1i8_POST + printPostIncOperand2(MI, 4, O, 1); + return; + break; + case 19: + // ST2i64_POST, ST4i32_POST + printPostIncOperand2(MI, 4, O, 16); + return; + break; + case 20: + // ST3i16_POST + printPostIncOperand2(MI, 4, O, 6); + return; + break; + case 21: + // ST3i32_POST + printPostIncOperand2(MI, 4, O, 12); + return; + break; + case 22: + // ST3i64_POST + printPostIncOperand2(MI, 4, O, 24); + return; + break; + case 23: + // ST3i8_POST + printPostIncOperand2(MI, 4, O, 3); + return; + break; + case 24: + // ST4i64_POST + printPostIncOperand2(MI, 4, O, 32); + return; + break; + case 25: + // SYSxt + printSysCROperand(MI, 1, O); + SStream_concat0(O, ", "); + printSysCROperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 26: + // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... + printTypedVectorList(MI, 1, O, 16, 'b', MRI); + SStream_concat0(O, ", "); + printVRegOperand(MI, 2, O); + break; + case 27: + // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... + printTypedVectorList(MI, 2, O, 16, 'b', MRI); + SStream_concat0(O, ", "); + printVRegOperand(MI, 3, O); + break; + } + + + // Fragment 3 encoded into 6 bits for 42 unique commands. + //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63); + switch ((Bits >> 29) & 63) { + default: // unreachable. + case 0: + // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... + SStream_concat0(O, ".16b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + return; + break; + case 1: + // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D... + return; + break; + case 2: + // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... + SStream_concat0(O, ".2s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + return; + break; + case 3: + // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + return; + break; + case 4: + // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v... + SStream_concat0(O, ".4h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + return; + break; + case 5: + // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... + SStream_concat0(O, ".4s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + return; + break; + case 6: + // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v... + SStream_concat0(O, ".8h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + return; + break; + case 7: + // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... + SStream_concat0(O, ".8b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + return; + break; + case 8: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS... + SStream_concat0(O, ", "); + break; + case 9: + // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + break; + case 10: + // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... + SStream_concat0(O, ".4s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + break; + case 11: + // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... + SStream_concat0(O, ".8h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + break; + case 12: + // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + break; + case 13: + // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... + SStream_concat0(O, ".2s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + break; + case 14: + // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... + SStream_concat0(O, ".4h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + break; + case 15: + // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + break; + case 16: + // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz + SStream_concat0(O, ".16b, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + arm64_op_addFP(MI, 0.0); + return; + break; + case 17: + // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz + SStream_concat0(O, ", #0"); + arm64_op_addImm(MI, 0); + return; + break; + case 18: + // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz + SStream_concat0(O, ".2s, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addImm(MI, 0); + return; + break; + case 19: + // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz + SStream_concat0(O, ".2d, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + arm64_op_addImm(MI, 0); + return; + break; + case 20: + // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz + SStream_concat0(O, ".4h, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + arm64_op_addImm(MI, 0); + return; + break; + case 21: + // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz + SStream_concat0(O, ".4s, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addImm(MI, 0); + return; + break; + case 22: + // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz + SStream_concat0(O, ".8h, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + arm64_op_addImm(MI, 0); + return; + break; + case 23: + // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz + SStream_concat0(O, ".8b, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + arm64_op_addImm(MI, 0); + return; + break; + case 24: + // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... + SStream_concat0(O, ".h"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); + break; + case 25: + // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... + SStream_concat0(O, ".s"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); + break; + case 26: + // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 + SStream_concat0(O, ".d"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); + break; + case 27: + // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... + SStream_concat0(O, ".b"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); + break; + case 28: + // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ... + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0.0); + return; + break; + case 29: + // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz + SStream_concat0(O, ".2s, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addFP(MI, 0.0); + return; + break; + case 30: + // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz + SStream_concat0(O, ".2d, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + arm64_op_addFP(MI, 0.0); + return; + break; + case 31: + // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz + SStream_concat0(O, ".4s, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addFP(MI, 0.0); + return; + break; + case 32: + // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX... + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 33: + // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos... + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + break; + case 34: + // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 3, O); + return; + break; + case 35: + // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... + printShifter(MI, 2, O); + return; + break; + case 36: + // SHLLv16i8 + SStream_concat0(O, ".16b, #8"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + arm64_op_addImm(MI, 8); + return; + break; + case 37: + // SHLLv2i32 + SStream_concat0(O, ".2s, #32"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addImm(MI, 32); + return; + break; + case 38: + // SHLLv4i16 + SStream_concat0(O, ".4h, #16"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + arm64_op_addImm(MI, 16); + return; + break; + case 39: + // SHLLv4i32 + SStream_concat0(O, ".4s, #32"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addImm(MI, 32); + return; + break; + case 40: + // SHLLv8i16 + SStream_concat0(O, ".8h, #16"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + arm64_op_addImm(MI, 16); + return; + break; + case 41: + // SHLLv8i8 + SStream_concat0(O, ".8b, #8"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + arm64_op_addImm(MI, 8); + return; + break; + } + + + // Fragment 4 encoded into 5 bits for 18 unique commands. + //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); + switch ((Bits >> 35) & 31) { + default: // unreachable. + case 0: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A... + printOperand(MI, 2, O); + break; + case 1: + // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... + printVRegOperand(MI, 2, O); + break; + case 2: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... + printVRegOperand(MI, 3, O); + break; + case 3: + // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri + printAddSubImm(MI, 2, O); + return; + break; + case 4: + // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... + printShiftedRegister(MI, 2, O); + return; + break; + case 5: + // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx + printExtendedRegister(MI, 2, O); + return; + break; + case 6: + // ANDSWri, ANDWri, EORWri, ORRWri + printLogicalImm32(MI, 2, O); + return; + break; + case 7: + // ANDSXri, ANDXri, EORXri, ORRXri + printLogicalImm64(MI, 2, O); + return; + break; + case 8: + // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW... + printOperand(MI, 3, O); + break; + case 9: + // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... + printVectorIndex(MI, 2, O); + return; + break; + case 10: + // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane + printVectorIndex(MI, 4, O); + return; + break; + case 11: + // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui + printUImm12Offset2(MI, 2, O, 1); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 12: + // LDRDui, LDRXui, PRFMui, STRDui, STRXui + printUImm12Offset2(MI, 2, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 13: + // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui + printUImm12Offset2(MI, 2, O, 2); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 14: + // LDRQui, STRQui + printUImm12Offset2(MI, 2, O, 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 15: + // LDRSWui, LDRSui, LDRWui, STRSui, STRWui + printUImm12Offset2(MI, 2, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 16: + // SYSLxt + printSysCROperand(MI, 2, O); + SStream_concat0(O, ", "); + printSysCROperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 17: + // TBNZW, TBNZX, TBZW, TBZX + printAlignedLabel(MI, 2, O); + return; + break; + } + + + // Fragment 5 encoded into 5 bits for 19 unique commands. + //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31); + switch ((Bits >> 40) & 31) { + default: // unreachable. + case 0: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG... + return; + break; + case 1: + // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + return; + break; + case 2: + // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... + SStream_concat0(O, ".4s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + return; + break; + case 3: + // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... + SStream_concat0(O, ".8h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + return; + break; + case 4: + // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... + SStream_concat0(O, ".16b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + return; + break; + case 5: + // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... + SStream_concat0(O, ".2s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + return; + break; + case 6: + // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... + SStream_concat0(O, ".4h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + return; + break; + case 7: + // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... + SStream_concat0(O, ".8b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + return; + break; + case 8: + // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 + printArithExtend(MI, 3, O); + return; + break; + case 9: + // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi... + SStream_concat0(O, ", "); + break; + case 10: + // EXTv16i8 + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + printOperand(MI, 3, O); + return; + break; + case 11: + // EXTv8i8 + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + printOperand(MI, 3, O); + return; + break; + case 12: + // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind... + SStream_concat0(O, ".s"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); + break; + case 13: + // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... + SStream_concat0(O, ".d"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); + break; + case 14: + // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi... + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 15: + // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 16: + // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... + SStream_concat0(O, "]!"); + set_mem_access(MI, false); + return; + break; + case 17: + // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed... + SStream_concat0(O, ".h"); + arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); + break; + case 18: + // STLXPW, STLXPX, STXPW, STXPX + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + } + + + // Fragment 6 encoded into 5 bits for 21 unique commands. + //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31); + switch ((Bits >> 45) & 31) { + default: // unreachable. + case 0: + // BFMWri, BFMXri + printOperand(MI, 4, O); + return; + break; + case 1: + // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... + printCondCode(MI, 3, O); + return; + break; + case 2: + // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD... + printOperand(MI, 3, O); + return; + break; + case 3: + // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind... + printVectorIndex(MI, 4, O); + return; + break; + case 4: + // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64... + printVectorIndex(MI, 3, O); + return; + break; + case 5: + // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi + printImmScale(MI, 3, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 6: + // LDNPQi, LDPQi, STNPQi, STPQi + printImmScale(MI, 3, O, 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 7: + // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi + printImmScale(MI, 3, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 8: + // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... + printImmScale(MI, 4, O, 8); + break; + case 9: + // LDPQpost, LDPQpre, STPQpost, STPQpre + printImmScale(MI, 4, O, 16); + break; + case 10: + // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... + printImmScale(MI, 4, O, 4); + break; + case 11: + // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW + printMemExtend(MI, 3, O, 'w', 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 12: + // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX + printMemExtend(MI, 3, O, 'x', 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 13: + // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW + printMemExtend(MI, 3, O, 'w', 64); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 14: + // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX + printMemExtend(MI, 3, O, 'x', 64); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 15: + // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW + printMemExtend(MI, 3, O, 'w', 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 16: + // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX + printMemExtend(MI, 3, O, 'x', 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 17: + // LDRQroW, STRQroW + printMemExtend(MI, 3, O, 'w', 128); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 18: + // LDRQroX, STRQroX + printMemExtend(MI, 3, O, 'x', 128); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 19: + // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW + printMemExtend(MI, 3, O, 'w', 32); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 20: + // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX + printMemExtend(MI, 3, O, 'x', 32); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + } + + + // Fragment 7 encoded into 1 bits for 2 unique commands. + //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1); + if ((Bits >> 50) & 1) { + // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... + SStream_concat0(O, "]!"); + set_mem_access(MI, false); + return; + } else { + // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... + return; + } +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo, int AltIdx) +{ + // assert(RegNo && RegNo < 420 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrsNoRegAltName[] = { + /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, + /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, + /* 26 */ 'b', '1', '0', 0, + /* 30 */ 'd', '1', '0', 0, + /* 34 */ 'h', '1', '0', 0, + /* 38 */ 'q', '1', '0', 0, + /* 42 */ 's', '1', '0', 0, + /* 46 */ 'w', '1', '0', 0, + /* 50 */ 'x', '1', '0', 0, + /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, + /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, + /* 86 */ 'b', '2', '0', 0, + /* 90 */ 'd', '2', '0', 0, + /* 94 */ 'h', '2', '0', 0, + /* 98 */ 'q', '2', '0', 0, + /* 102 */ 's', '2', '0', 0, + /* 106 */ 'w', '2', '0', 0, + /* 110 */ 'x', '2', '0', 0, + /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, + /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, + /* 146 */ 'b', '3', '0', 0, + /* 150 */ 'd', '3', '0', 0, + /* 154 */ 'h', '3', '0', 0, + /* 158 */ 'q', '3', '0', 0, + /* 162 */ 's', '3', '0', 0, + /* 166 */ 'w', '3', '0', 0, + /* 170 */ 'x', '3', '0', 0, + /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, + /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, + /* 204 */ 'b', '0', 0, + /* 207 */ 'd', '0', 0, + /* 210 */ 'h', '0', 0, + /* 213 */ 'q', '0', 0, + /* 216 */ 's', '0', 0, + /* 219 */ 'w', '0', 0, + /* 222 */ 'x', '0', 0, + /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, + /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, + /* 253 */ 'b', '1', '1', 0, + /* 257 */ 'd', '1', '1', 0, + /* 261 */ 'h', '1', '1', 0, + /* 265 */ 'q', '1', '1', 0, + /* 269 */ 's', '1', '1', 0, + /* 273 */ 'w', '1', '1', 0, + /* 277 */ 'x', '1', '1', 0, + /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, + /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, + /* 313 */ 'b', '2', '1', 0, + /* 317 */ 'd', '2', '1', 0, + /* 321 */ 'h', '2', '1', 0, + /* 325 */ 'q', '2', '1', 0, + /* 329 */ 's', '2', '1', 0, + /* 333 */ 'w', '2', '1', 0, + /* 337 */ 'x', '2', '1', 0, + /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, + /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, + /* 373 */ 'b', '3', '1', 0, + /* 377 */ 'd', '3', '1', 0, + /* 381 */ 'h', '3', '1', 0, + /* 385 */ 'q', '3', '1', 0, + /* 389 */ 's', '3', '1', 0, + /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, + /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, + /* 421 */ 'b', '1', 0, + /* 424 */ 'd', '1', 0, + /* 427 */ 'h', '1', 0, + /* 430 */ 'q', '1', 0, + /* 433 */ 's', '1', 0, + /* 436 */ 'w', '1', 0, + /* 439 */ 'x', '1', 0, + /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, + /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, + /* 472 */ 'b', '1', '2', 0, + /* 476 */ 'd', '1', '2', 0, + /* 480 */ 'h', '1', '2', 0, + /* 484 */ 'q', '1', '2', 0, + /* 488 */ 's', '1', '2', 0, + /* 492 */ 'w', '1', '2', 0, + /* 496 */ 'x', '1', '2', 0, + /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, + /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, + /* 532 */ 'b', '2', '2', 0, + /* 536 */ 'd', '2', '2', 0, + /* 540 */ 'h', '2', '2', 0, + /* 544 */ 'q', '2', '2', 0, + /* 548 */ 's', '2', '2', 0, + /* 552 */ 'w', '2', '2', 0, + /* 556 */ 'x', '2', '2', 0, + /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, + /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, + /* 586 */ 'b', '2', 0, + /* 589 */ 'd', '2', 0, + /* 592 */ 'h', '2', 0, + /* 595 */ 'q', '2', 0, + /* 598 */ 's', '2', 0, + /* 601 */ 'w', '2', 0, + /* 604 */ 'x', '2', 0, + /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, + /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, + /* 639 */ 'b', '1', '3', 0, + /* 643 */ 'd', '1', '3', 0, + /* 647 */ 'h', '1', '3', 0, + /* 651 */ 'q', '1', '3', 0, + /* 655 */ 's', '1', '3', 0, + /* 659 */ 'w', '1', '3', 0, + /* 663 */ 'x', '1', '3', 0, + /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, + /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, + /* 699 */ 'b', '2', '3', 0, + /* 703 */ 'd', '2', '3', 0, + /* 707 */ 'h', '2', '3', 0, + /* 711 */ 'q', '2', '3', 0, + /* 715 */ 's', '2', '3', 0, + /* 719 */ 'w', '2', '3', 0, + /* 723 */ 'x', '2', '3', 0, + /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, + /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, + /* 751 */ 'b', '3', 0, + /* 754 */ 'd', '3', 0, + /* 757 */ 'h', '3', 0, + /* 760 */ 'q', '3', 0, + /* 763 */ 's', '3', 0, + /* 766 */ 'w', '3', 0, + /* 769 */ 'x', '3', 0, + /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, + /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, + /* 804 */ 'b', '1', '4', 0, + /* 808 */ 'd', '1', '4', 0, + /* 812 */ 'h', '1', '4', 0, + /* 816 */ 'q', '1', '4', 0, + /* 820 */ 's', '1', '4', 0, + /* 824 */ 'w', '1', '4', 0, + /* 828 */ 'x', '1', '4', 0, + /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, + /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, + /* 864 */ 'b', '2', '4', 0, + /* 868 */ 'd', '2', '4', 0, + /* 872 */ 'h', '2', '4', 0, + /* 876 */ 'q', '2', '4', 0, + /* 880 */ 's', '2', '4', 0, + /* 884 */ 'w', '2', '4', 0, + /* 888 */ 'x', '2', '4', 0, + /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, + /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, + /* 916 */ 'b', '4', 0, + /* 919 */ 'd', '4', 0, + /* 922 */ 'h', '4', 0, + /* 925 */ 'q', '4', 0, + /* 928 */ 's', '4', 0, + /* 931 */ 'w', '4', 0, + /* 934 */ 'x', '4', 0, + /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, + /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, + /* 969 */ 'b', '1', '5', 0, + /* 973 */ 'd', '1', '5', 0, + /* 977 */ 'h', '1', '5', 0, + /* 981 */ 'q', '1', '5', 0, + /* 985 */ 's', '1', '5', 0, + /* 989 */ 'w', '1', '5', 0, + /* 993 */ 'x', '1', '5', 0, + /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, + /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, + /* 1029 */ 'b', '2', '5', 0, + /* 1033 */ 'd', '2', '5', 0, + /* 1037 */ 'h', '2', '5', 0, + /* 1041 */ 'q', '2', '5', 0, + /* 1045 */ 's', '2', '5', 0, + /* 1049 */ 'w', '2', '5', 0, + /* 1053 */ 'x', '2', '5', 0, + /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, + /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, + /* 1081 */ 'b', '5', 0, + /* 1084 */ 'd', '5', 0, + /* 1087 */ 'h', '5', 0, + /* 1090 */ 'q', '5', 0, + /* 1093 */ 's', '5', 0, + /* 1096 */ 'w', '5', 0, + /* 1099 */ 'x', '5', 0, + /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, + /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, + /* 1134 */ 'b', '1', '6', 0, + /* 1138 */ 'd', '1', '6', 0, + /* 1142 */ 'h', '1', '6', 0, + /* 1146 */ 'q', '1', '6', 0, + /* 1150 */ 's', '1', '6', 0, + /* 1154 */ 'w', '1', '6', 0, + /* 1158 */ 'x', '1', '6', 0, + /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, + /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, + /* 1194 */ 'b', '2', '6', 0, + /* 1198 */ 'd', '2', '6', 0, + /* 1202 */ 'h', '2', '6', 0, + /* 1206 */ 'q', '2', '6', 0, + /* 1210 */ 's', '2', '6', 0, + /* 1214 */ 'w', '2', '6', 0, + /* 1218 */ 'x', '2', '6', 0, + /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, + /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, + /* 1246 */ 'b', '6', 0, + /* 1249 */ 'd', '6', 0, + /* 1252 */ 'h', '6', 0, + /* 1255 */ 'q', '6', 0, + /* 1258 */ 's', '6', 0, + /* 1261 */ 'w', '6', 0, + /* 1264 */ 'x', '6', 0, + /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, + /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, + /* 1299 */ 'b', '1', '7', 0, + /* 1303 */ 'd', '1', '7', 0, + /* 1307 */ 'h', '1', '7', 0, + /* 1311 */ 'q', '1', '7', 0, + /* 1315 */ 's', '1', '7', 0, + /* 1319 */ 'w', '1', '7', 0, + /* 1323 */ 'x', '1', '7', 0, + /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, + /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, + /* 1359 */ 'b', '2', '7', 0, + /* 1363 */ 'd', '2', '7', 0, + /* 1367 */ 'h', '2', '7', 0, + /* 1371 */ 'q', '2', '7', 0, + /* 1375 */ 's', '2', '7', 0, + /* 1379 */ 'w', '2', '7', 0, + /* 1383 */ 'x', '2', '7', 0, + /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, + /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, + /* 1411 */ 'b', '7', 0, + /* 1414 */ 'd', '7', 0, + /* 1417 */ 'h', '7', 0, + /* 1420 */ 'q', '7', 0, + /* 1423 */ 's', '7', 0, + /* 1426 */ 'w', '7', 0, + /* 1429 */ 'x', '7', 0, + /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, + /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, + /* 1464 */ 'b', '1', '8', 0, + /* 1468 */ 'd', '1', '8', 0, + /* 1472 */ 'h', '1', '8', 0, + /* 1476 */ 'q', '1', '8', 0, + /* 1480 */ 's', '1', '8', 0, + /* 1484 */ 'w', '1', '8', 0, + /* 1488 */ 'x', '1', '8', 0, + /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, + /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, + /* 1524 */ 'b', '2', '8', 0, + /* 1528 */ 'd', '2', '8', 0, + /* 1532 */ 'h', '2', '8', 0, + /* 1536 */ 'q', '2', '8', 0, + /* 1540 */ 's', '2', '8', 0, + /* 1544 */ 'w', '2', '8', 0, + /* 1548 */ 'x', '2', '8', 0, + /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, + /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, + /* 1576 */ 'b', '8', 0, + /* 1579 */ 'd', '8', 0, + /* 1582 */ 'h', '8', 0, + /* 1585 */ 'q', '8', 0, + /* 1588 */ 's', '8', 0, + /* 1591 */ 'w', '8', 0, + /* 1594 */ 'x', '8', 0, + /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, + /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, + /* 1629 */ 'b', '1', '9', 0, + /* 1633 */ 'd', '1', '9', 0, + /* 1637 */ 'h', '1', '9', 0, + /* 1641 */ 'q', '1', '9', 0, + /* 1645 */ 's', '1', '9', 0, + /* 1649 */ 'w', '1', '9', 0, + /* 1653 */ 'x', '1', '9', 0, + /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, + /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, + /* 1689 */ 'b', '2', '9', 0, + /* 1693 */ 'd', '2', '9', 0, + /* 1697 */ 'h', '2', '9', 0, + /* 1701 */ 'q', '2', '9', 0, + /* 1705 */ 's', '2', '9', 0, + /* 1709 */ 'w', '2', '9', 0, + /* 1713 */ 'x', '2', '9', 0, + /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, + /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, + /* 1741 */ 'b', '9', 0, + /* 1744 */ 'd', '9', 0, + /* 1747 */ 'h', '9', 0, + /* 1750 */ 'q', '9', 0, + /* 1753 */ 's', '9', 0, + /* 1756 */ 'w', '9', 0, + /* 1759 */ 'x', '9', 0, + /* 1762 */ 'w', 's', 'p', 0, + /* 1766 */ 'w', 'z', 'r', 0, + /* 1770 */ 'x', 'z', 'r', 0, + /* 1774 */ 'n', 'z', 'c', 'v', 0, + }; + + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, + 1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, + 313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, + 754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, + 1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, + 377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, + 647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, + 1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, + 1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, + 711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, + 1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, + 1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, + 436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, + 989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, + 1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, + 496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, + 1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, + 449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, + 1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, + 0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, + 832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, + 1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, + 1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, + 397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, + 796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, + 1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, + 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, + 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, + 1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, + 301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, + }; + + static const char AsmStrsvreg[] = { + /* 0 */ 'v', '1', '0', 0, + /* 4 */ 'v', '2', '0', 0, + /* 8 */ 'v', '3', '0', 0, + /* 12 */ 'v', '0', 0, + /* 15 */ 'v', '1', '1', 0, + /* 19 */ 'v', '2', '1', 0, + /* 23 */ 'v', '3', '1', 0, + /* 27 */ 'v', '1', 0, + /* 30 */ 'v', '1', '2', 0, + /* 34 */ 'v', '2', '2', 0, + /* 38 */ 'v', '2', 0, + /* 41 */ 'v', '1', '3', 0, + /* 45 */ 'v', '2', '3', 0, + /* 49 */ 'v', '3', 0, + /* 52 */ 'v', '1', '4', 0, + /* 56 */ 'v', '2', '4', 0, + /* 60 */ 'v', '4', 0, + /* 63 */ 'v', '1', '5', 0, + /* 67 */ 'v', '2', '5', 0, + /* 71 */ 'v', '5', 0, + /* 74 */ 'v', '1', '6', 0, + /* 78 */ 'v', '2', '6', 0, + /* 82 */ 'v', '6', 0, + /* 85 */ 'v', '1', '7', 0, + /* 89 */ 'v', '2', '7', 0, + /* 93 */ 'v', '7', 0, + /* 96 */ 'v', '1', '8', 0, + /* 100 */ 'v', '2', '8', 0, + /* 104 */ 'v', '8', 0, + /* 107 */ 'v', '1', '9', 0, + /* 111 */ 'v', '2', '9', 0, + /* 115 */ 'v', '9', 0, + }; + + static const uint16_t RegAsmOffsetvreg[] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, + 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, + 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, + 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, + 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, + 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, + 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, + 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, + 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, + 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, + 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, + 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, + 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, + 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, + 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, + 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, + 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, + }; + + const uint16_t *RegAsmOffset; + const char *AsmStrs; + + switch(AltIdx) { + default: // llvm_unreachable("Invalid register alt name index!"); + case AArch64_NoRegAltName: + AsmStrs = AsmStrsNoRegAltName; + RegAsmOffset = RegAsmOffsetNoRegAltName; + break; + case AArch64_vreg: + AsmStrs = AsmStrsvreg; + RegAsmOffset = RegAsmOffsetvreg; + break; + } + //int i; + //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/2; i++) + // printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1); + //printf("*************************\n"); + //for (i = 0; i < sizeof(RegAsmOffsetvreg)/2; i++) + // printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1); + //printf("-------------------------\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI) +{ + // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx); + switch (PrintMethodIdx) { + default: + // llvm_unreachable("Unknown PrintMethod kind"); + break; + case 0: + printAddSubImm(MI, OpIdx, OS); + break; + case 1: + printShifter(MI, OpIdx, OS); + break; + case 2: + printArithExtend(MI, OpIdx, OS); + break; + case 3: + printLogicalImm32(MI, OpIdx, OS); + break; + case 4: + printLogicalImm64(MI, OpIdx, OS); + break; + case 5: + printVRegOperand(MI, OpIdx, OS); + break; + case 6: + printHexImm(MI, OpIdx, OS); + break; + case 7: + printInverseCondCode(MI, OpIdx, OS); + break; + case 8: + printVectorIndex(MI, OpIdx, OS); + break; + case 9: + printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI); + break; + case 10: + printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI); + break; + case 11: + printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI); + break; + case 12: + printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI); + break; + case 13: + printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI); + break; + case 14: + printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI); + break; + case 15: + printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI); + break; + case 16: + printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI); + break; + case 17: + printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI); + break; + case 18: + printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI); + break; + case 19: + printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI); + break; + case 20: + printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI); + break; + case 21: + printPrefetchOp(MI, OpIdx, OS); + break; + case 22: + printSysCROperand(MI, OpIdx, OS); + break; + } +} + +static bool AArch64InstPrinterValidateMCOperand( + MCOperand *MCOp, unsigned PredicateIndex) +{ + switch (PredicateIndex) { + default: + // llvm_unreachable("Unknown MCOperandPredicate kind"); + case 1: { + return (MCOperand_isImm(MCOp) && + MCOperand_getImm(MCOp) != ARM64_CC_AL && + MCOperand_getImm(MCOp) != ARM64_CC_NV); + } + } +} + +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +{ + #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + const char *AsmString; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case AArch64_ADDSWri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { + // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) + AsmString = "cmn $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case AArch64_ADDSWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) + AsmString = "cmn $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) + AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "adds $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDSWrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "cmn $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "adds $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDSXri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { + // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) + AsmString = "cmn $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case AArch64_ADDSXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) + AsmString = "cmn $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) + AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "adds $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDSXrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + break; + } + return NULL; + case AArch64_ADDSXrx64: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "cmn $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "adds $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDWri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) + AsmString = "mov $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) + AsmString = "mov $\x01, $\x02"; + break; + } + return NULL; + case AArch64_ADDWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDWrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDXri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) + AsmString = "mov $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) + AsmString = "mov $\x01, $\x02"; + break; + } + return NULL; + case AArch64_ADDXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ADDXrx64: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "add $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ANDSWri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) { + // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) + AsmString = "tst $\x02, $\xFF\x03\x04"; + break; + } + return NULL; + case AArch64_ANDSWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) + AsmString = "tst $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) + AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "ands $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ANDSXri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) { + // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) + AsmString = "tst $\x02, $\xFF\x03\x05"; + break; + } + return NULL; + case AArch64_ANDSXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) + AsmString = "tst $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) + AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "ands $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ANDWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "and $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ANDXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "and $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_BICSWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "bics $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_BICSXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "bics $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_BICWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "bic $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_BICXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "bic $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_BICv2i32: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (BICv2i32 V64:$Vd, imm0_255:$imm, 0) + AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_BICv4i16: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (BICv4i16 V64:$Vd, imm0_255:$imm, 0) + AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_BICv4i32: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (BICv4i32 V128:$Vd, imm0_255:$imm, 0) + AsmString = "bic $\xFF\x01\x06.4s, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_BICv8i16: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (BICv8i16 V128:$Vd, imm0_255:$imm, 0) + AsmString = "bic $\xFF\x01\x06.8h, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_CLREX: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { + // (CLREX 15) + AsmString = "clrex"; + break; + } + return NULL; + case AArch64_CSINCWr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) + AsmString = "cset $\x01, $\xFF\x04\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) + AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_CSINCXr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) + AsmString = "cset $\x01, $\xFF\x04\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) + AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_CSINVWr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) + AsmString = "csetm $\x01, $\xFF\x04\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) + AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_CSINVXr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) + AsmString = "csetm $\x01, $\xFF\x04\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) + AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_CSNEGWr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) + AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_CSNEGXr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) + AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; + break; + } + return NULL; + case AArch64_DCPS1: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (DCPS1 0) + AsmString = "dcps1"; + break; + } + return NULL; + case AArch64_DCPS2: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (DCPS2 0) + AsmString = "dcps2"; + break; + } + return NULL; + case AArch64_DCPS3: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (DCPS3 0) + AsmString = "dcps3"; + break; + } + return NULL; + case AArch64_EONWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "eon $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EONXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "eon $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EORWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "eor $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EORXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "eor $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EXTRWrri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) + AsmString = "ror $\x01, $\x02, $\x04"; + break; + } + return NULL; + case AArch64_EXTRXrri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) + AsmString = "ror $\x01, $\x02, $\x04"; + break; + } + return NULL; + case AArch64_HINT: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (HINT { 0, 0, 0 }) + AsmString = "nop"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { + // (HINT { 0, 0, 1 }) + AsmString = "yield"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { + // (HINT { 0, 1, 0 }) + AsmString = "wfe"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { + // (HINT { 0, 1, 1 }) + AsmString = "wfi"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { + // (HINT { 1, 0, 0 }) + AsmString = "sev"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { + // (HINT { 1, 0, 1 }) + AsmString = "sevl"; + break; + } + return NULL; + case AArch64_INSvi16gpr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) + AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\x03"; + break; + } + return NULL; + case AArch64_INSvi16lane: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) + AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\xFF\x03\x06.h$\xFF\x04\x09"; + break; + } + return NULL; + case AArch64_INSvi32gpr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) + AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\x03"; + break; + } + return NULL; + case AArch64_INSvi32lane: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) + AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\xFF\x03\x06.s$\xFF\x04\x09"; + break; + } + return NULL; + case AArch64_INSvi64gpr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) + AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\x03"; + break; + } + return NULL; + case AArch64_INSvi64lane: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) + AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\xFF\x03\x06.d$\xFF\x04\x09"; + break; + } + return NULL; + case AArch64_INSvi8gpr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) + AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\x03"; + break; + } + return NULL; + case AArch64_INSvi8lane: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) + AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\xFF\x03\x06.b$\xFF\x04\x09"; + break; + } + return NULL; + case AArch64_ISB: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { + // (ISB 15) + AsmString = "isb"; + break; + } + return NULL; + case AArch64_LD1Fourv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD1Fourv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Fourv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD1Fourv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Fourv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Fourv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD1Fourv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x10, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Fourv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x11, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD1Onev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Onev1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Onev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Onev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Onev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Onev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Onev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x10, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Onev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x11, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Rv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0A, [$\x01], #1"; + break; + } + return NULL; + case AArch64_LD1Rv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0B, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Rv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0C, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1Rv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0D, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD1Rv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0E, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD1Rv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x0F, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD1Rv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x10, [$\x01], #1"; + break; + } + return NULL; + case AArch64_LD1Rv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) + AsmString = "ld1r $\xFF\x02\x11, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD1Threev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD1Threev1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD1Threev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD1Threev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD1Threev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD1Threev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD1Threev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x10, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD1Threev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x11, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD1Twov16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Twov1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Twov2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Twov2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Twov4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Twov4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1Twov8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x10, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1Twov8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) + AsmString = "ld1 $\xFF\x02\x11, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "ld1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD1i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) + AsmString = "ld1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD1i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) + AsmString = "ld1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD1i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "ld1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; + break; + } + return NULL; + case AArch64_LD2Rv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0A, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD2Rv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0B, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2Rv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0C, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2Rv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0D, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD2Rv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0E, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD2Rv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x0F, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD2Rv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x10, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD2Rv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) + AsmString = "ld2r $\xFF\x02\x11, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD2Twov16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x0A, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD2Twov2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x0C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD2Twov2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x0D, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2Twov4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x0E, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2Twov4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x0F, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD2Twov8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x10, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2Twov8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) + AsmString = "ld2 $\xFF\x02\x11, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD2i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "ld2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD2i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) + AsmString = "ld2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD2i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) + AsmString = "ld2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD2i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) + AsmString = "ld2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD3Rv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0A, [$\x01], #3"; + break; + } + return NULL; + case AArch64_LD3Rv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0B, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3Rv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0C, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3Rv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0D, [$\x01], #12"; + break; + } + return NULL; + case AArch64_LD3Rv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0E, [$\x01], #6"; + break; + } + return NULL; + case AArch64_LD3Rv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x0F, [$\x01], #12"; + break; + } + return NULL; + case AArch64_LD3Rv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x10, [$\x01], #3"; + break; + } + return NULL; + case AArch64_LD3Rv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) + AsmString = "ld3r $\xFF\x02\x11, [$\x01], #6"; + break; + } + return NULL; + case AArch64_LD3Threev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x0A, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD3Threev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x0C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD3Threev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x0D, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3Threev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x0E, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3Threev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x0F, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD3Threev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x10, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3Threev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) + AsmString = "ld3 $\xFF\x02\x11, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD3i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "ld3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; + break; + } + return NULL; + case AArch64_LD3i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) + AsmString = "ld3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; + break; + } + return NULL; + case AArch64_LD3i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) + AsmString = "ld3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; + break; + } + return NULL; + case AArch64_LD3i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "ld3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; + break; + } + return NULL; + case AArch64_LD4Fourv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x0A, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD4Fourv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x0C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD4Fourv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x0D, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4Fourv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x0E, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4Fourv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x0F, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD4Fourv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x10, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4Fourv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) + AsmString = "ld4 $\xFF\x02\x11, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD4Rv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0A, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD4Rv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0B, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4Rv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4Rv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0D, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD4Rv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0E, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD4Rv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x0F, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD4Rv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x10, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LD4Rv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) + AsmString = "ld4r $\xFF\x02\x11, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD4i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "ld4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD4i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) + AsmString = "ld4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD4i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) + AsmString = "ld4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD4i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "ld4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LDNPDi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNPQi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNPSi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNPWi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNPXi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPDi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPQi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPSWi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPSWi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldpsw $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPSi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPWi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDPXi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (LDPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDRBBroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrb $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRBBui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRBroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRBui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRBui FPR8:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRDroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRDui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRDui FPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRHHroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrh $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRHHui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRHroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRHui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRHui FPR16:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRQroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRQui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRQui FPR128:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSBWroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrsb $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSBWui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrsb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSBXroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrsb $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSBXui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrsb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSHWroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrsh $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSHWui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrsh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSHXroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrsh $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSHXui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrsh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSWroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldrsw $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSWui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrsw $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRSroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRSui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRSui FPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRWroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRWui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRWui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRXroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_LDRXui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDRXui GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRSBWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrsb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRSBXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrsb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRSHWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrsh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRSHXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrsh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRSWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtrsw $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDTRXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldtr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURBBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldurb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURBi FPR8:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURDi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURDi FPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURHHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldurh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURHi FPR16:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURQi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURQi FPR128:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSBWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldursb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSBXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldursb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSHWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldursh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSHXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldursh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldursw $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURSi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURSi FPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDURXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (LDURXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_MADDWrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { + // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) + AsmString = "mul $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_MADDXrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) + AsmString = "mul $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_MOVKWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { + // (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16) + AsmString = "movk $\x01, $\x02"; + break; + } + return NULL; + case AArch64_MOVKXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) { + // (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48) + AsmString = "movk $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) { + // (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32) + AsmString = "movk $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { + // (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16) + AsmString = "movk $\x01, $\x02"; + break; + } + return NULL; + case AArch64_MSUBWrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { + // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) + AsmString = "mneg $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_MSUBXrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) + AsmString = "mneg $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_NOTv16i8: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { + // (NOTv16i8 V128:$Vd, V128:$Vn) + AsmString = "mvn $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; + break; + } + return NULL; + case AArch64_NOTv8i8: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { + // (NOTv8i8 V64:$Vd, V64:$Vn) + AsmString = "mvn $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; + break; + } + return NULL; + case AArch64_ORNWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) + AsmString = "mvn $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) + AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "orn $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORNXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) + AsmString = "mvn $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) + AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "orn $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORRWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) + AsmString = "mov $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "orr $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORRXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) + AsmString = "mov $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "orr $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORRv16i8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (ORRv16i8 V128:$dst, V128:$src, V128:$src) + AsmString = "mov $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; + break; + } + return NULL; + case AArch64_ORRv2i32: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ORRv2i32 V64:$Vd, imm0_255:$imm, 0) + AsmString = "orr $\xFF\x01\x06.2s, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_ORRv4i16: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ORRv4i16 V64:$Vd, imm0_255:$imm, 0) + AsmString = "orr $\xFF\x01\x06.4h, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_ORRv4i32: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ORRv4i32 V128:$Vd, imm0_255:$imm, 0) + AsmString = "orr $\xFF\x01\x06.4s, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_ORRv8i16: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (ORRv8i16 V128:$Vd, imm0_255:$imm, 0) + AsmString = "orr $\xFF\x01\x06.8h, $\xFF\x02\x07"; + break; + } + return NULL; + case AArch64_ORRv8i8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (ORRv8i8 V64:$dst, V64:$src, V64:$src) + AsmString = "mov $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; + break; + } + return NULL; + case AArch64_PRFMroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "prfm $\xFF\x01\x16, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_PRFMui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) + AsmString = "prfm $\xFF\x01\x16, [$\x02]"; + break; + } + return NULL; + case AArch64_PRFUMi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) + AsmString = "prfum $\xFF\x01\x16, [$\x02]"; + break; + } + return NULL; + case AArch64_RET: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) { + // (RET LR) + AsmString = "ret"; + break; + } + return NULL; + case AArch64_SBCSWr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SBCSWr GPR32:$dst, WZR, GPR32:$src) + AsmString = "ngcs $\x01, $\x03"; + break; + } + return NULL; + case AArch64_SBCSXr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SBCSXr GPR64:$dst, XZR, GPR64:$src) + AsmString = "ngcs $\x01, $\x03"; + break; + } + return NULL; + case AArch64_SBCWr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SBCWr GPR32:$dst, WZR, GPR32:$src) + AsmString = "ngc $\x01, $\x03"; + break; + } + return NULL; + case AArch64_SBCXr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SBCXr GPR64:$dst, XZR, GPR64:$src) + AsmString = "ngc $\x01, $\x03"; + break; + } + return NULL; + case AArch64_SBFMWri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { + // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) + AsmString = "asr $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) + AsmString = "sxtb $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) + AsmString = "sxth $\x01, $\x02"; + break; + } + return NULL; + case AArch64_SBFMXri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { + // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) + AsmString = "asr $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) + AsmString = "sxtb $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) + AsmString = "sxth $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) + AsmString = "sxtw $\x01, $\x02"; + break; + } + return NULL; + case AArch64_SMADDLrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) + AsmString = "smull $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SMSUBLrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) + AsmString = "smnegl $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ST1Fourv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0A, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST1Fourv1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0B, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Fourv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST1Fourv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0D, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Fourv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0E, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Fourv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0F, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST1Fourv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x10, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Fourv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x11, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST1Onev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0A, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Onev1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0B, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST1Onev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0C, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Onev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0D, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST1Onev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0E, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST1Onev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0F, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Onev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x10, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST1Onev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x11, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Threev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0A, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST1Threev1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0B, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST1Threev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST1Threev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0D, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST1Threev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0E, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST1Threev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0F, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST1Threev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x10, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST1Threev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x11, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST1Twov16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0A, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Twov1d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0B, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Twov2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Twov2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0D, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Twov4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0E, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Twov4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x0F, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1Twov8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x10, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST1Twov8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) + AsmString = "st1 $\xFF\x02\x11, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "st1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; + break; + } + return NULL; + case AArch64_ST1i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) + AsmString = "st1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_ST1i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) + AsmString = "st1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST1i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "st1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; + break; + } + return NULL; + case AArch64_ST2Twov16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x0A, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST2Twov2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x0C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST2Twov2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x0D, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST2Twov4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x0E, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST2Twov4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x0F, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST2Twov8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x10, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST2Twov8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) + AsmString = "st2 $\xFF\x02\x11, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST2i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "st2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_ST2i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) + AsmString = "st2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST2i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) + AsmString = "st2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST2i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) + AsmString = "st2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; + break; + } + return NULL; + case AArch64_ST3Threev16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x0A, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST3Threev2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x0C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST3Threev2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x0D, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST3Threev4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x0E, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST3Threev4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x0F, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST3Threev8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x10, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST3Threev8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) + AsmString = "st3 $\xFF\x02\x11, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST3i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "st3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; + break; + } + return NULL; + case AArch64_ST3i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) + AsmString = "st3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; + break; + } + return NULL; + case AArch64_ST3i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) + AsmString = "st3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; + break; + } + return NULL; + case AArch64_ST3i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "st3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; + break; + } + return NULL; + case AArch64_ST4Fourv16b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x0A, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST4Fourv2d_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x0C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST4Fourv2s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x0D, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST4Fourv4h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x0E, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST4Fourv4s_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x0F, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST4Fourv8b_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x10, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST4Fourv8h_POST: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) + AsmString = "st4 $\xFF\x02\x11, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST4i16_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) + AsmString = "st4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; + break; + } + return NULL; + case AArch64_ST4i32_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) + AsmString = "st4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; + break; + } + return NULL; + case AArch64_ST4i64_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) + AsmString = "st4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST4i8_POST: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) + AsmString = "st4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; + break; + } + return NULL; + case AArch64_STNPDi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STNPQi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STNPSi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STNPWi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STNPXi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stnp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STPDi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STPQi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STPSi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STPWi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STPXi: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (STPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_STRBBroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "strb $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRBBui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRBBui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "strb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRBroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRBui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRBui FPR8:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRDroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRDui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRDui FPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRHHroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "strh $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRHHui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRHHui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "strh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRHroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRHui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRHui FPR16:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRQroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRQui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRQui FPR128:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRSroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRSui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRSui FPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRWroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRWui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRWui GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STRXroX: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { + // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; + break; + } + return NULL; + case AArch64_STRXui: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STRXui GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STTRBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "sttrb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STTRHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "sttrh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STTRWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "sttr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STTRXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "sttr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURBBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURBBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "sturb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURBi FPR8:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURDi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURDi FPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURHHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURHHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "sturh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURHi FPR16:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURQi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURQi FPR128:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURSi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURSi FPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STURXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (STURXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_SUBSWri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { + // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) + AsmString = "cmp $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case AArch64_SUBSWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) + AsmString = "cmp $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) + AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) + AsmString = "negs $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) + AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "subs $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBSWrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "cmp $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "subs $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBSXri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { + // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) + AsmString = "cmp $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case AArch64_SUBSXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) + AsmString = "cmp $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) + AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) + AsmString = "negs $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) + AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "subs $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBSXrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + break; + } + return NULL; + case AArch64_SUBSXrx64: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "cmp $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "subs $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBWrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) + AsmString = "neg $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) + AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBWrx: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { + // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBXrs: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) + AsmString = "neg $\x01, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) + AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SUBXrx64: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { + // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) + AsmString = "sub $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SYSxt: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { + // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) + AsmString = "sys $\x01, $\xFF\x02\x17, $\xFF\x03\x17, $\x04"; + break; + } + return NULL; + case AArch64_UBFMWri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { + // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) + AsmString = "lsr $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) + AsmString = "uxtb $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) + AsmString = "uxth $\x01, $\x02"; + break; + } + return NULL; + case AArch64_UBFMXri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { + // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) + AsmString = "lsr $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) + AsmString = "uxtb $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) + AsmString = "uxth $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) + AsmString = "uxtw $\x01, $\x02"; + break; + } + return NULL; + case AArch64_UMADDLrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) + AsmString = "umull $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_UMOVvi32: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { + // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) + AsmString = "mov $\x01, $\xFF\x02\x06.s$\xFF\x03\x09"; + break; + } + return NULL; + case AArch64_UMOVvi64: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { + // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) + AsmString = "mov $\x01, $\xFF\x02\x06.d$\xFF\x03\x09"; + break; + } + return NULL; + case AArch64_UMSUBLrrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) + AsmString = "umnegl $\x01, $\x02, $\x03"; + break; + } + return NULL; + } + + tmp = cs_strdup(AsmString); + AsmMnem = tmp; + for(AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '[') { + SStream_concat0(OS, "["); + set_mem_access(MI, true); + } + else if (*c == ']') { + SStream_concat0(OS, "]"); + set_mem_access(MI, false); + } + else if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS, MRI); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + return tmp; +} + +#endif // PRINT_ALIAS_INSTR diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64GenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenDisassemblerTables.inc new file mode 100644 index 0000000..ac4ca8d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenDisassemblerTables.inc @@ -0,0 +1,12742 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * AArch64 Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ... +/* 3 */ MCD_OPC_FilterValue, 2, 86, 4, // Skip to: 1117 +/* 7 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 10 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 146 +/* 14 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 17 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 98 +/* 21 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 24 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 47 +/* 28 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 31 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 39 +/* 35 */ MCD_OPC_Decode, 147, 15, 0, // Opcode: STXRB +/* 39 */ MCD_OPC_FilterValue, 1, 150, 158, // Skip to: 40641 +/* 43 */ MCD_OPC_Decode, 191, 14, 0, // Opcode: STLXRB +/* 47 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 70 +/* 51 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 54 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 62 +/* 58 */ MCD_OPC_Decode, 171, 8, 0, // Opcode: LDXRB +/* 62 */ MCD_OPC_FilterValue, 1, 127, 158, // Skip to: 40641 +/* 66 */ MCD_OPC_Decode, 171, 7, 0, // Opcode: LDAXRB +/* 70 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 84 +/* 74 */ MCD_OPC_CheckField, 15, 1, 1, 113, 158, // Skip to: 40641 +/* 80 */ MCD_OPC_Decode, 185, 14, 0, // Opcode: STLRB +/* 84 */ MCD_OPC_FilterValue, 6, 105, 158, // Skip to: 40641 +/* 88 */ MCD_OPC_CheckField, 15, 1, 1, 99, 158, // Skip to: 40641 +/* 94 */ MCD_OPC_Decode, 165, 7, 0, // Opcode: LDARB +/* 98 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 119 +/* 102 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 105 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 112 +/* 109 */ MCD_OPC_Decode, 95, 1, // Opcode: ANDWrs +/* 112 */ MCD_OPC_FilterValue, 1, 77, 158, // Skip to: 40641 +/* 116 */ MCD_OPC_Decode, 111, 1, // Opcode: BICWrs +/* 119 */ MCD_OPC_FilterValue, 3, 70, 158, // Skip to: 40641 +/* 123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 126 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 133 +/* 130 */ MCD_OPC_Decode, 64, 1, // Opcode: ADDWrs +/* 133 */ MCD_OPC_FilterValue, 1, 56, 158, // Skip to: 40641 +/* 137 */ MCD_OPC_CheckField, 22, 2, 0, 50, 158, // Skip to: 40641 +/* 143 */ MCD_OPC_Decode, 65, 2, // Opcode: ADDWrx +/* 146 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 281 +/* 150 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 153 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 192 +/* 157 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 160 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 168 +/* 164 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: STNPWi +/* 168 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 176 +/* 172 */ MCD_OPC_Decode, 178, 7, 3, // Opcode: LDNPWi +/* 176 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 184 +/* 180 */ MCD_OPC_Decode, 210, 14, 3, // Opcode: STPWpost +/* 184 */ MCD_OPC_FilterValue, 3, 5, 158, // Skip to: 40641 +/* 188 */ MCD_OPC_Decode, 193, 7, 3, // Opcode: LDPWpost +/* 192 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 231 +/* 196 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 199 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 207 +/* 203 */ MCD_OPC_Decode, 209, 14, 3, // Opcode: STPWi +/* 207 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 215 +/* 211 */ MCD_OPC_Decode, 192, 7, 3, // Opcode: LDPWi +/* 215 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 223 +/* 219 */ MCD_OPC_Decode, 211, 14, 3, // Opcode: STPWpre +/* 223 */ MCD_OPC_FilterValue, 3, 222, 157, // Skip to: 40641 +/* 227 */ MCD_OPC_Decode, 194, 7, 3, // Opcode: LDPWpre +/* 231 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 254 +/* 235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 238 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 246 +/* 242 */ MCD_OPC_Decode, 137, 9, 1, // Opcode: ORRWrs +/* 246 */ MCD_OPC_FilterValue, 1, 199, 157, // Skip to: 40641 +/* 250 */ MCD_OPC_Decode, 130, 9, 1, // Opcode: ORNWrs +/* 254 */ MCD_OPC_FilterValue, 3, 191, 157, // Skip to: 40641 +/* 258 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 261 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 268 +/* 265 */ MCD_OPC_Decode, 50, 1, // Opcode: ADDSWrs +/* 268 */ MCD_OPC_FilterValue, 1, 177, 157, // Skip to: 40641 +/* 272 */ MCD_OPC_CheckField, 22, 2, 0, 171, 157, // Skip to: 40641 +/* 278 */ MCD_OPC_Decode, 51, 2, // Opcode: ADDSWrx +/* 281 */ MCD_OPC_FilterValue, 2, 136, 0, // Skip to: 421 +/* 285 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 288 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 369 +/* 292 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 295 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 318 +/* 299 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 302 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 310 +/* 306 */ MCD_OPC_Decode, 148, 15, 0, // Opcode: STXRH +/* 310 */ MCD_OPC_FilterValue, 1, 135, 157, // Skip to: 40641 +/* 314 */ MCD_OPC_Decode, 192, 14, 0, // Opcode: STLXRH +/* 318 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 341 +/* 322 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 325 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 333 +/* 329 */ MCD_OPC_Decode, 172, 8, 0, // Opcode: LDXRH +/* 333 */ MCD_OPC_FilterValue, 1, 112, 157, // Skip to: 40641 +/* 337 */ MCD_OPC_Decode, 172, 7, 0, // Opcode: LDAXRH +/* 341 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 355 +/* 345 */ MCD_OPC_CheckField, 15, 1, 1, 98, 157, // Skip to: 40641 +/* 351 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: STLRH +/* 355 */ MCD_OPC_FilterValue, 6, 90, 157, // Skip to: 40641 +/* 359 */ MCD_OPC_CheckField, 15, 1, 1, 84, 157, // Skip to: 40641 +/* 365 */ MCD_OPC_Decode, 166, 7, 0, // Opcode: LDARH +/* 369 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 392 +/* 373 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 376 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 384 +/* 380 */ MCD_OPC_Decode, 168, 2, 1, // Opcode: EORWrs +/* 384 */ MCD_OPC_FilterValue, 1, 61, 157, // Skip to: 40641 +/* 388 */ MCD_OPC_Decode, 163, 2, 1, // Opcode: EONWrs +/* 392 */ MCD_OPC_FilterValue, 3, 53, 157, // Skip to: 40641 +/* 396 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 399 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 407 +/* 403 */ MCD_OPC_Decode, 168, 15, 1, // Opcode: SUBWrs +/* 407 */ MCD_OPC_FilterValue, 1, 38, 157, // Skip to: 40641 +/* 411 */ MCD_OPC_CheckField, 22, 2, 0, 32, 157, // Skip to: 40641 +/* 417 */ MCD_OPC_Decode, 169, 15, 2, // Opcode: SUBWrx +/* 421 */ MCD_OPC_FilterValue, 3, 90, 0, // Skip to: 515 +/* 425 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 428 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 442 +/* 432 */ MCD_OPC_CheckField, 22, 2, 3, 11, 157, // Skip to: 40641 +/* 438 */ MCD_OPC_Decode, 187, 7, 3, // Opcode: LDPSWpost +/* 442 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 465 +/* 446 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 449 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 457 +/* 453 */ MCD_OPC_Decode, 186, 7, 3, // Opcode: LDPSWi +/* 457 */ MCD_OPC_FilterValue, 3, 244, 156, // Skip to: 40641 +/* 461 */ MCD_OPC_Decode, 188, 7, 3, // Opcode: LDPSWpre +/* 465 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 486 +/* 469 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 472 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 479 +/* 476 */ MCD_OPC_Decode, 89, 1, // Opcode: ANDSWrs +/* 479 */ MCD_OPC_FilterValue, 1, 222, 156, // Skip to: 40641 +/* 483 */ MCD_OPC_Decode, 107, 1, // Opcode: BICSWrs +/* 486 */ MCD_OPC_FilterValue, 3, 215, 156, // Skip to: 40641 +/* 490 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 493 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 501 +/* 497 */ MCD_OPC_Decode, 159, 15, 1, // Opcode: SUBSWrs +/* 501 */ MCD_OPC_FilterValue, 1, 200, 156, // Skip to: 40641 +/* 505 */ MCD_OPC_CheckField, 22, 2, 0, 194, 156, // Skip to: 40641 +/* 511 */ MCD_OPC_Decode, 160, 15, 2, // Opcode: SUBSWrx +/* 515 */ MCD_OPC_FilterValue, 4, 188, 0, // Skip to: 707 +/* 519 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 522 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 649 +/* 526 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 529 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 552 +/* 533 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 536 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 544 +/* 540 */ MCD_OPC_Decode, 149, 15, 0, // Opcode: STXRW +/* 544 */ MCD_OPC_FilterValue, 1, 157, 156, // Skip to: 40641 +/* 548 */ MCD_OPC_Decode, 193, 14, 0, // Opcode: STLXRW +/* 552 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 575 +/* 556 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 559 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 567 +/* 563 */ MCD_OPC_Decode, 145, 15, 0, // Opcode: STXPW +/* 567 */ MCD_OPC_FilterValue, 1, 134, 156, // Skip to: 40641 +/* 571 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: STLXPW +/* 575 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 598 +/* 579 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 582 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 590 +/* 586 */ MCD_OPC_Decode, 173, 8, 0, // Opcode: LDXRW +/* 590 */ MCD_OPC_FilterValue, 1, 111, 156, // Skip to: 40641 +/* 594 */ MCD_OPC_Decode, 173, 7, 0, // Opcode: LDAXRW +/* 598 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 621 +/* 602 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 605 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 613 +/* 609 */ MCD_OPC_Decode, 169, 8, 0, // Opcode: LDXPW +/* 613 */ MCD_OPC_FilterValue, 1, 88, 156, // Skip to: 40641 +/* 617 */ MCD_OPC_Decode, 169, 7, 0, // Opcode: LDAXPW +/* 621 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 635 +/* 625 */ MCD_OPC_CheckField, 15, 1, 1, 74, 156, // Skip to: 40641 +/* 631 */ MCD_OPC_Decode, 187, 14, 0, // Opcode: STLRW +/* 635 */ MCD_OPC_FilterValue, 6, 66, 156, // Skip to: 40641 +/* 639 */ MCD_OPC_CheckField, 15, 1, 1, 60, 156, // Skip to: 40641 +/* 645 */ MCD_OPC_Decode, 167, 7, 0, // Opcode: LDARW +/* 649 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 670 +/* 653 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 656 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 663 +/* 660 */ MCD_OPC_Decode, 98, 1, // Opcode: ANDXrs +/* 663 */ MCD_OPC_FilterValue, 1, 38, 156, // Skip to: 40641 +/* 667 */ MCD_OPC_Decode, 113, 1, // Opcode: BICXrs +/* 670 */ MCD_OPC_FilterValue, 3, 31, 156, // Skip to: 40641 +/* 674 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 677 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 684 +/* 681 */ MCD_OPC_Decode, 68, 1, // Opcode: ADDXrs +/* 684 */ MCD_OPC_FilterValue, 1, 17, 156, // Skip to: 40641 +/* 688 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 691 */ MCD_OPC_FilterValue, 0, 10, 156, // Skip to: 40641 +/* 695 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 704 +/* 701 */ MCD_OPC_Decode, 70, 2, // Opcode: ADDXrx64 +/* 704 */ MCD_OPC_Decode, 69, 2, // Opcode: ADDXrx +/* 707 */ MCD_OPC_FilterValue, 5, 141, 0, // Skip to: 852 +/* 711 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 714 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 753 +/* 718 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 721 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 729 +/* 725 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: STNPXi +/* 729 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 737 +/* 733 */ MCD_OPC_Decode, 179, 7, 3, // Opcode: LDNPXi +/* 737 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 745 +/* 741 */ MCD_OPC_Decode, 213, 14, 3, // Opcode: STPXpost +/* 745 */ MCD_OPC_FilterValue, 3, 212, 155, // Skip to: 40641 +/* 749 */ MCD_OPC_Decode, 196, 7, 3, // Opcode: LDPXpost +/* 753 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 792 +/* 757 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 760 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 768 +/* 764 */ MCD_OPC_Decode, 212, 14, 3, // Opcode: STPXi +/* 768 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 776 +/* 772 */ MCD_OPC_Decode, 195, 7, 3, // Opcode: LDPXi +/* 776 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 784 +/* 780 */ MCD_OPC_Decode, 214, 14, 3, // Opcode: STPXpre +/* 784 */ MCD_OPC_FilterValue, 3, 173, 155, // Skip to: 40641 +/* 788 */ MCD_OPC_Decode, 197, 7, 3, // Opcode: LDPXpre +/* 792 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 815 +/* 796 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 799 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 807 +/* 803 */ MCD_OPC_Decode, 140, 9, 1, // Opcode: ORRXrs +/* 807 */ MCD_OPC_FilterValue, 1, 150, 155, // Skip to: 40641 +/* 811 */ MCD_OPC_Decode, 132, 9, 1, // Opcode: ORNXrs +/* 815 */ MCD_OPC_FilterValue, 3, 142, 155, // Skip to: 40641 +/* 819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 822 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 829 +/* 826 */ MCD_OPC_Decode, 54, 1, // Opcode: ADDSXrs +/* 829 */ MCD_OPC_FilterValue, 1, 128, 155, // Skip to: 40641 +/* 833 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 836 */ MCD_OPC_FilterValue, 0, 121, 155, // Skip to: 40641 +/* 840 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 849 +/* 846 */ MCD_OPC_Decode, 56, 2, // Opcode: ADDSXrx64 +/* 849 */ MCD_OPC_Decode, 55, 2, // Opcode: ADDSXrx +/* 852 */ MCD_OPC_FilterValue, 6, 193, 0, // Skip to: 1049 +/* 856 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 859 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 986 +/* 863 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 866 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 889 +/* 870 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 873 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 881 +/* 877 */ MCD_OPC_Decode, 150, 15, 0, // Opcode: STXRX +/* 881 */ MCD_OPC_FilterValue, 1, 76, 155, // Skip to: 40641 +/* 885 */ MCD_OPC_Decode, 194, 14, 0, // Opcode: STLXRX +/* 889 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 912 +/* 893 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 896 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 904 +/* 900 */ MCD_OPC_Decode, 146, 15, 0, // Opcode: STXPX +/* 904 */ MCD_OPC_FilterValue, 1, 53, 155, // Skip to: 40641 +/* 908 */ MCD_OPC_Decode, 190, 14, 0, // Opcode: STLXPX +/* 912 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 935 +/* 916 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 919 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 927 +/* 923 */ MCD_OPC_Decode, 174, 8, 0, // Opcode: LDXRX +/* 927 */ MCD_OPC_FilterValue, 1, 30, 155, // Skip to: 40641 +/* 931 */ MCD_OPC_Decode, 174, 7, 0, // Opcode: LDAXRX +/* 935 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 958 +/* 939 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 942 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 950 +/* 946 */ MCD_OPC_Decode, 170, 8, 0, // Opcode: LDXPX +/* 950 */ MCD_OPC_FilterValue, 1, 7, 155, // Skip to: 40641 +/* 954 */ MCD_OPC_Decode, 170, 7, 0, // Opcode: LDAXPX +/* 958 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 972 +/* 962 */ MCD_OPC_CheckField, 15, 1, 1, 249, 154, // Skip to: 40641 +/* 968 */ MCD_OPC_Decode, 188, 14, 0, // Opcode: STLRX +/* 972 */ MCD_OPC_FilterValue, 6, 241, 154, // Skip to: 40641 +/* 976 */ MCD_OPC_CheckField, 15, 1, 1, 235, 154, // Skip to: 40641 +/* 982 */ MCD_OPC_Decode, 168, 7, 0, // Opcode: LDARX +/* 986 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1009 +/* 990 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 993 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1001 +/* 997 */ MCD_OPC_Decode, 171, 2, 1, // Opcode: EORXrs +/* 1001 */ MCD_OPC_FilterValue, 1, 212, 154, // Skip to: 40641 +/* 1005 */ MCD_OPC_Decode, 165, 2, 1, // Opcode: EONXrs +/* 1009 */ MCD_OPC_FilterValue, 3, 204, 154, // Skip to: 40641 +/* 1013 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 1016 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1024 +/* 1020 */ MCD_OPC_Decode, 172, 15, 1, // Opcode: SUBXrs +/* 1024 */ MCD_OPC_FilterValue, 1, 189, 154, // Skip to: 40641 +/* 1028 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 1031 */ MCD_OPC_FilterValue, 0, 182, 154, // Skip to: 40641 +/* 1035 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1045 +/* 1041 */ MCD_OPC_Decode, 174, 15, 2, // Opcode: SUBXrx64 +/* 1045 */ MCD_OPC_Decode, 173, 15, 2, // Opcode: SUBXrx +/* 1049 */ MCD_OPC_FilterValue, 7, 164, 154, // Skip to: 40641 +/* 1053 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 1056 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1078 +/* 1060 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 1063 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1070 +/* 1067 */ MCD_OPC_Decode, 92, 1, // Opcode: ANDSXrs +/* 1070 */ MCD_OPC_FilterValue, 3, 143, 154, // Skip to: 40641 +/* 1074 */ MCD_OPC_Decode, 163, 15, 1, // Opcode: SUBSXrs +/* 1078 */ MCD_OPC_FilterValue, 1, 135, 154, // Skip to: 40641 +/* 1082 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 1085 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1092 +/* 1089 */ MCD_OPC_Decode, 109, 1, // Opcode: BICSXrs +/* 1092 */ MCD_OPC_FilterValue, 3, 121, 154, // Skip to: 40641 +/* 1096 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 1099 */ MCD_OPC_FilterValue, 0, 114, 154, // Skip to: 40641 +/* 1103 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1113 +/* 1109 */ MCD_OPC_Decode, 165, 15, 2, // Opcode: SUBSXrx64 +/* 1113 */ MCD_OPC_Decode, 164, 15, 2, // Opcode: SUBSXrx +/* 1117 */ MCD_OPC_FilterValue, 3, 236, 110, // Skip to: 29517 +/* 1121 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 1124 */ MCD_OPC_FilterValue, 0, 165, 2, // Skip to: 1805 +/* 1128 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 1131 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 1438 +/* 1135 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 1138 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1150 +/* 1142 */ MCD_OPC_CheckPredicate, 0, 71, 154, // Skip to: 40641 +/* 1146 */ MCD_OPC_Decode, 173, 14, 4, // Opcode: ST4Fourv8b +/* 1150 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1162 +/* 1154 */ MCD_OPC_CheckPredicate, 0, 59, 154, // Skip to: 40641 +/* 1158 */ MCD_OPC_Decode, 169, 14, 4, // Opcode: ST4Fourv4h +/* 1162 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1174 +/* 1166 */ MCD_OPC_CheckPredicate, 0, 47, 154, // Skip to: 40641 +/* 1170 */ MCD_OPC_Decode, 167, 14, 4, // Opcode: ST4Fourv2s +/* 1174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1186 +/* 1178 */ MCD_OPC_CheckPredicate, 0, 35, 154, // Skip to: 40641 +/* 1182 */ MCD_OPC_Decode, 187, 13, 4, // Opcode: ST1Fourv8b +/* 1186 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1198 +/* 1190 */ MCD_OPC_CheckPredicate, 0, 23, 154, // Skip to: 40641 +/* 1194 */ MCD_OPC_Decode, 183, 13, 4, // Opcode: ST1Fourv4h +/* 1198 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1210 +/* 1202 */ MCD_OPC_CheckPredicate, 0, 11, 154, // Skip to: 40641 +/* 1206 */ MCD_OPC_Decode, 181, 13, 4, // Opcode: ST1Fourv2s +/* 1210 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1222 +/* 1214 */ MCD_OPC_CheckPredicate, 0, 255, 153, // Skip to: 40641 +/* 1218 */ MCD_OPC_Decode, 177, 13, 4, // Opcode: ST1Fourv1d +/* 1222 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1234 +/* 1226 */ MCD_OPC_CheckPredicate, 0, 243, 153, // Skip to: 40641 +/* 1230 */ MCD_OPC_Decode, 151, 14, 5, // Opcode: ST3Threev8b +/* 1234 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1246 +/* 1238 */ MCD_OPC_CheckPredicate, 0, 231, 153, // Skip to: 40641 +/* 1242 */ MCD_OPC_Decode, 147, 14, 5, // Opcode: ST3Threev4h +/* 1246 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1258 +/* 1250 */ MCD_OPC_CheckPredicate, 0, 219, 153, // Skip to: 40641 +/* 1254 */ MCD_OPC_Decode, 145, 14, 5, // Opcode: ST3Threev2s +/* 1258 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1270 +/* 1262 */ MCD_OPC_CheckPredicate, 0, 207, 153, // Skip to: 40641 +/* 1266 */ MCD_OPC_Decode, 219, 13, 5, // Opcode: ST1Threev8b +/* 1270 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1282 +/* 1274 */ MCD_OPC_CheckPredicate, 0, 195, 153, // Skip to: 40641 +/* 1278 */ MCD_OPC_Decode, 215, 13, 5, // Opcode: ST1Threev4h +/* 1282 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1294 +/* 1286 */ MCD_OPC_CheckPredicate, 0, 183, 153, // Skip to: 40641 +/* 1290 */ MCD_OPC_Decode, 213, 13, 5, // Opcode: ST1Threev2s +/* 1294 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1306 +/* 1298 */ MCD_OPC_CheckPredicate, 0, 171, 153, // Skip to: 40641 +/* 1302 */ MCD_OPC_Decode, 209, 13, 5, // Opcode: ST1Threev1d +/* 1306 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1318 +/* 1310 */ MCD_OPC_CheckPredicate, 0, 159, 153, // Skip to: 40641 +/* 1314 */ MCD_OPC_Decode, 203, 13, 6, // Opcode: ST1Onev8b +/* 1318 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1330 +/* 1322 */ MCD_OPC_CheckPredicate, 0, 147, 153, // Skip to: 40641 +/* 1326 */ MCD_OPC_Decode, 199, 13, 6, // Opcode: ST1Onev4h +/* 1330 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1342 +/* 1334 */ MCD_OPC_CheckPredicate, 0, 135, 153, // Skip to: 40641 +/* 1338 */ MCD_OPC_Decode, 197, 13, 6, // Opcode: ST1Onev2s +/* 1342 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1354 +/* 1346 */ MCD_OPC_CheckPredicate, 0, 123, 153, // Skip to: 40641 +/* 1350 */ MCD_OPC_Decode, 193, 13, 6, // Opcode: ST1Onev1d +/* 1354 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1366 +/* 1358 */ MCD_OPC_CheckPredicate, 0, 111, 153, // Skip to: 40641 +/* 1362 */ MCD_OPC_Decode, 129, 14, 7, // Opcode: ST2Twov8b +/* 1366 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1378 +/* 1370 */ MCD_OPC_CheckPredicate, 0, 99, 153, // Skip to: 40641 +/* 1374 */ MCD_OPC_Decode, 253, 13, 7, // Opcode: ST2Twov4h +/* 1378 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1390 +/* 1382 */ MCD_OPC_CheckPredicate, 0, 87, 153, // Skip to: 40641 +/* 1386 */ MCD_OPC_Decode, 251, 13, 7, // Opcode: ST2Twov2s +/* 1390 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1402 +/* 1394 */ MCD_OPC_CheckPredicate, 0, 75, 153, // Skip to: 40641 +/* 1398 */ MCD_OPC_Decode, 235, 13, 7, // Opcode: ST1Twov8b +/* 1402 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1414 +/* 1406 */ MCD_OPC_CheckPredicate, 0, 63, 153, // Skip to: 40641 +/* 1410 */ MCD_OPC_Decode, 231, 13, 7, // Opcode: ST1Twov4h +/* 1414 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1426 +/* 1418 */ MCD_OPC_CheckPredicate, 0, 51, 153, // Skip to: 40641 +/* 1422 */ MCD_OPC_Decode, 229, 13, 7, // Opcode: ST1Twov2s +/* 1426 */ MCD_OPC_FilterValue, 43, 43, 153, // Skip to: 40641 +/* 1430 */ MCD_OPC_CheckPredicate, 0, 39, 153, // Skip to: 40641 +/* 1434 */ MCD_OPC_Decode, 225, 13, 7, // Opcode: ST1Twov1d +/* 1438 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1446 +/* 1442 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: STNPSi +/* 1446 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 1789 +/* 1450 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 1453 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1465 +/* 1457 */ MCD_OPC_CheckPredicate, 0, 12, 153, // Skip to: 40641 +/* 1461 */ MCD_OPC_Decode, 163, 14, 8, // Opcode: ST4Fourv16b +/* 1465 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1477 +/* 1469 */ MCD_OPC_CheckPredicate, 0, 0, 153, // Skip to: 40641 +/* 1473 */ MCD_OPC_Decode, 175, 14, 8, // Opcode: ST4Fourv8h +/* 1477 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1489 +/* 1481 */ MCD_OPC_CheckPredicate, 0, 244, 152, // Skip to: 40641 +/* 1485 */ MCD_OPC_Decode, 171, 14, 8, // Opcode: ST4Fourv4s +/* 1489 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1501 +/* 1493 */ MCD_OPC_CheckPredicate, 0, 232, 152, // Skip to: 40641 +/* 1497 */ MCD_OPC_Decode, 165, 14, 8, // Opcode: ST4Fourv2d +/* 1501 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1513 +/* 1505 */ MCD_OPC_CheckPredicate, 0, 220, 152, // Skip to: 40641 +/* 1509 */ MCD_OPC_Decode, 175, 13, 8, // Opcode: ST1Fourv16b +/* 1513 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1525 +/* 1517 */ MCD_OPC_CheckPredicate, 0, 208, 152, // Skip to: 40641 +/* 1521 */ MCD_OPC_Decode, 189, 13, 8, // Opcode: ST1Fourv8h +/* 1525 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1537 +/* 1529 */ MCD_OPC_CheckPredicate, 0, 196, 152, // Skip to: 40641 +/* 1533 */ MCD_OPC_Decode, 185, 13, 8, // Opcode: ST1Fourv4s +/* 1537 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1549 +/* 1541 */ MCD_OPC_CheckPredicate, 0, 184, 152, // Skip to: 40641 +/* 1545 */ MCD_OPC_Decode, 179, 13, 8, // Opcode: ST1Fourv2d +/* 1549 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1561 +/* 1553 */ MCD_OPC_CheckPredicate, 0, 172, 152, // Skip to: 40641 +/* 1557 */ MCD_OPC_Decode, 141, 14, 9, // Opcode: ST3Threev16b +/* 1561 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1573 +/* 1565 */ MCD_OPC_CheckPredicate, 0, 160, 152, // Skip to: 40641 +/* 1569 */ MCD_OPC_Decode, 153, 14, 9, // Opcode: ST3Threev8h +/* 1573 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1585 +/* 1577 */ MCD_OPC_CheckPredicate, 0, 148, 152, // Skip to: 40641 +/* 1581 */ MCD_OPC_Decode, 149, 14, 9, // Opcode: ST3Threev4s +/* 1585 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1597 +/* 1589 */ MCD_OPC_CheckPredicate, 0, 136, 152, // Skip to: 40641 +/* 1593 */ MCD_OPC_Decode, 143, 14, 9, // Opcode: ST3Threev2d +/* 1597 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1609 +/* 1601 */ MCD_OPC_CheckPredicate, 0, 124, 152, // Skip to: 40641 +/* 1605 */ MCD_OPC_Decode, 207, 13, 9, // Opcode: ST1Threev16b +/* 1609 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1621 +/* 1613 */ MCD_OPC_CheckPredicate, 0, 112, 152, // Skip to: 40641 +/* 1617 */ MCD_OPC_Decode, 221, 13, 9, // Opcode: ST1Threev8h +/* 1621 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1633 +/* 1625 */ MCD_OPC_CheckPredicate, 0, 100, 152, // Skip to: 40641 +/* 1629 */ MCD_OPC_Decode, 217, 13, 9, // Opcode: ST1Threev4s +/* 1633 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1645 +/* 1637 */ MCD_OPC_CheckPredicate, 0, 88, 152, // Skip to: 40641 +/* 1641 */ MCD_OPC_Decode, 211, 13, 9, // Opcode: ST1Threev2d +/* 1645 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1657 +/* 1649 */ MCD_OPC_CheckPredicate, 0, 76, 152, // Skip to: 40641 +/* 1653 */ MCD_OPC_Decode, 191, 13, 10, // Opcode: ST1Onev16b +/* 1657 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1669 +/* 1661 */ MCD_OPC_CheckPredicate, 0, 64, 152, // Skip to: 40641 +/* 1665 */ MCD_OPC_Decode, 205, 13, 10, // Opcode: ST1Onev8h +/* 1669 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1681 +/* 1673 */ MCD_OPC_CheckPredicate, 0, 52, 152, // Skip to: 40641 +/* 1677 */ MCD_OPC_Decode, 201, 13, 10, // Opcode: ST1Onev4s +/* 1681 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1693 +/* 1685 */ MCD_OPC_CheckPredicate, 0, 40, 152, // Skip to: 40641 +/* 1689 */ MCD_OPC_Decode, 195, 13, 10, // Opcode: ST1Onev2d +/* 1693 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1705 +/* 1697 */ MCD_OPC_CheckPredicate, 0, 28, 152, // Skip to: 40641 +/* 1701 */ MCD_OPC_Decode, 247, 13, 11, // Opcode: ST2Twov16b +/* 1705 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1717 +/* 1709 */ MCD_OPC_CheckPredicate, 0, 16, 152, // Skip to: 40641 +/* 1713 */ MCD_OPC_Decode, 131, 14, 11, // Opcode: ST2Twov8h +/* 1717 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1729 +/* 1721 */ MCD_OPC_CheckPredicate, 0, 4, 152, // Skip to: 40641 +/* 1725 */ MCD_OPC_Decode, 255, 13, 11, // Opcode: ST2Twov4s +/* 1729 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 1741 +/* 1733 */ MCD_OPC_CheckPredicate, 0, 248, 151, // Skip to: 40641 +/* 1737 */ MCD_OPC_Decode, 249, 13, 11, // Opcode: ST2Twov2d +/* 1741 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1753 +/* 1745 */ MCD_OPC_CheckPredicate, 0, 236, 151, // Skip to: 40641 +/* 1749 */ MCD_OPC_Decode, 223, 13, 11, // Opcode: ST1Twov16b +/* 1753 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1765 +/* 1757 */ MCD_OPC_CheckPredicate, 0, 224, 151, // Skip to: 40641 +/* 1761 */ MCD_OPC_Decode, 237, 13, 11, // Opcode: ST1Twov8h +/* 1765 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1777 +/* 1769 */ MCD_OPC_CheckPredicate, 0, 212, 151, // Skip to: 40641 +/* 1773 */ MCD_OPC_Decode, 233, 13, 11, // Opcode: ST1Twov4s +/* 1777 */ MCD_OPC_FilterValue, 43, 204, 151, // Skip to: 40641 +/* 1781 */ MCD_OPC_CheckPredicate, 0, 200, 151, // Skip to: 40641 +/* 1785 */ MCD_OPC_Decode, 227, 13, 11, // Opcode: ST1Twov2d +/* 1789 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1797 +/* 1793 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: STNPDi +/* 1797 */ MCD_OPC_FilterValue, 5, 184, 151, // Skip to: 40641 +/* 1801 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: STNPQi +/* 1805 */ MCD_OPC_FilterValue, 1, 165, 2, // Skip to: 2486 +/* 1809 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 1812 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 2119 +/* 1816 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 1819 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1831 +/* 1823 */ MCD_OPC_CheckPredicate, 0, 158, 151, // Skip to: 40641 +/* 1827 */ MCD_OPC_Decode, 137, 7, 4, // Opcode: LD4Fourv8b +/* 1831 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1843 +/* 1835 */ MCD_OPC_CheckPredicate, 0, 146, 151, // Skip to: 40641 +/* 1839 */ MCD_OPC_Decode, 133, 7, 4, // Opcode: LD4Fourv4h +/* 1843 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1855 +/* 1847 */ MCD_OPC_CheckPredicate, 0, 134, 151, // Skip to: 40641 +/* 1851 */ MCD_OPC_Decode, 131, 7, 4, // Opcode: LD4Fourv2s +/* 1855 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1867 +/* 1859 */ MCD_OPC_CheckPredicate, 0, 122, 151, // Skip to: 40641 +/* 1863 */ MCD_OPC_Decode, 231, 5, 4, // Opcode: LD1Fourv8b +/* 1867 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1879 +/* 1871 */ MCD_OPC_CheckPredicate, 0, 110, 151, // Skip to: 40641 +/* 1875 */ MCD_OPC_Decode, 227, 5, 4, // Opcode: LD1Fourv4h +/* 1879 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1891 +/* 1883 */ MCD_OPC_CheckPredicate, 0, 98, 151, // Skip to: 40641 +/* 1887 */ MCD_OPC_Decode, 225, 5, 4, // Opcode: LD1Fourv2s +/* 1891 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1903 +/* 1895 */ MCD_OPC_CheckPredicate, 0, 86, 151, // Skip to: 40641 +/* 1899 */ MCD_OPC_Decode, 221, 5, 4, // Opcode: LD1Fourv1d +/* 1903 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1915 +/* 1907 */ MCD_OPC_CheckPredicate, 0, 74, 151, // Skip to: 40641 +/* 1911 */ MCD_OPC_Decode, 243, 6, 5, // Opcode: LD3Threev8b +/* 1915 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1927 +/* 1919 */ MCD_OPC_CheckPredicate, 0, 62, 151, // Skip to: 40641 +/* 1923 */ MCD_OPC_Decode, 239, 6, 5, // Opcode: LD3Threev4h +/* 1927 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1939 +/* 1931 */ MCD_OPC_CheckPredicate, 0, 50, 151, // Skip to: 40641 +/* 1935 */ MCD_OPC_Decode, 237, 6, 5, // Opcode: LD3Threev2s +/* 1939 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1951 +/* 1943 */ MCD_OPC_CheckPredicate, 0, 38, 151, // Skip to: 40641 +/* 1947 */ MCD_OPC_Decode, 151, 6, 5, // Opcode: LD1Threev8b +/* 1951 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1963 +/* 1955 */ MCD_OPC_CheckPredicate, 0, 26, 151, // Skip to: 40641 +/* 1959 */ MCD_OPC_Decode, 147, 6, 5, // Opcode: LD1Threev4h +/* 1963 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1975 +/* 1967 */ MCD_OPC_CheckPredicate, 0, 14, 151, // Skip to: 40641 +/* 1971 */ MCD_OPC_Decode, 145, 6, 5, // Opcode: LD1Threev2s +/* 1975 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1987 +/* 1979 */ MCD_OPC_CheckPredicate, 0, 2, 151, // Skip to: 40641 +/* 1983 */ MCD_OPC_Decode, 141, 6, 5, // Opcode: LD1Threev1d +/* 1987 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1999 +/* 1991 */ MCD_OPC_CheckPredicate, 0, 246, 150, // Skip to: 40641 +/* 1995 */ MCD_OPC_Decode, 247, 5, 6, // Opcode: LD1Onev8b +/* 1999 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2011 +/* 2003 */ MCD_OPC_CheckPredicate, 0, 234, 150, // Skip to: 40641 +/* 2007 */ MCD_OPC_Decode, 243, 5, 6, // Opcode: LD1Onev4h +/* 2011 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2023 +/* 2015 */ MCD_OPC_CheckPredicate, 0, 222, 150, // Skip to: 40641 +/* 2019 */ MCD_OPC_Decode, 241, 5, 6, // Opcode: LD1Onev2s +/* 2023 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2035 +/* 2027 */ MCD_OPC_CheckPredicate, 0, 210, 150, // Skip to: 40641 +/* 2031 */ MCD_OPC_Decode, 237, 5, 6, // Opcode: LD1Onev1d +/* 2035 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2047 +/* 2039 */ MCD_OPC_CheckPredicate, 0, 198, 150, // Skip to: 40641 +/* 2043 */ MCD_OPC_Decode, 205, 6, 7, // Opcode: LD2Twov8b +/* 2047 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2059 +/* 2051 */ MCD_OPC_CheckPredicate, 0, 186, 150, // Skip to: 40641 +/* 2055 */ MCD_OPC_Decode, 201, 6, 7, // Opcode: LD2Twov4h +/* 2059 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2071 +/* 2063 */ MCD_OPC_CheckPredicate, 0, 174, 150, // Skip to: 40641 +/* 2067 */ MCD_OPC_Decode, 199, 6, 7, // Opcode: LD2Twov2s +/* 2071 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2083 +/* 2075 */ MCD_OPC_CheckPredicate, 0, 162, 150, // Skip to: 40641 +/* 2079 */ MCD_OPC_Decode, 167, 6, 7, // Opcode: LD1Twov8b +/* 2083 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2095 +/* 2087 */ MCD_OPC_CheckPredicate, 0, 150, 150, // Skip to: 40641 +/* 2091 */ MCD_OPC_Decode, 163, 6, 7, // Opcode: LD1Twov4h +/* 2095 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2107 +/* 2099 */ MCD_OPC_CheckPredicate, 0, 138, 150, // Skip to: 40641 +/* 2103 */ MCD_OPC_Decode, 161, 6, 7, // Opcode: LD1Twov2s +/* 2107 */ MCD_OPC_FilterValue, 43, 130, 150, // Skip to: 40641 +/* 2111 */ MCD_OPC_CheckPredicate, 0, 126, 150, // Skip to: 40641 +/* 2115 */ MCD_OPC_Decode, 157, 6, 7, // Opcode: LD1Twov1d +/* 2119 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2127 +/* 2123 */ MCD_OPC_Decode, 177, 7, 3, // Opcode: LDNPSi +/* 2127 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 2470 +/* 2131 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 2134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2146 +/* 2138 */ MCD_OPC_CheckPredicate, 0, 99, 150, // Skip to: 40641 +/* 2142 */ MCD_OPC_Decode, 255, 6, 8, // Opcode: LD4Fourv16b +/* 2146 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2158 +/* 2150 */ MCD_OPC_CheckPredicate, 0, 87, 150, // Skip to: 40641 +/* 2154 */ MCD_OPC_Decode, 139, 7, 8, // Opcode: LD4Fourv8h +/* 2158 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2170 +/* 2162 */ MCD_OPC_CheckPredicate, 0, 75, 150, // Skip to: 40641 +/* 2166 */ MCD_OPC_Decode, 135, 7, 8, // Opcode: LD4Fourv4s +/* 2170 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2182 +/* 2174 */ MCD_OPC_CheckPredicate, 0, 63, 150, // Skip to: 40641 +/* 2178 */ MCD_OPC_Decode, 129, 7, 8, // Opcode: LD4Fourv2d +/* 2182 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 2194 +/* 2186 */ MCD_OPC_CheckPredicate, 0, 51, 150, // Skip to: 40641 +/* 2190 */ MCD_OPC_Decode, 219, 5, 8, // Opcode: LD1Fourv16b +/* 2194 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 2206 +/* 2198 */ MCD_OPC_CheckPredicate, 0, 39, 150, // Skip to: 40641 +/* 2202 */ MCD_OPC_Decode, 233, 5, 8, // Opcode: LD1Fourv8h +/* 2206 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 2218 +/* 2210 */ MCD_OPC_CheckPredicate, 0, 27, 150, // Skip to: 40641 +/* 2214 */ MCD_OPC_Decode, 229, 5, 8, // Opcode: LD1Fourv4s +/* 2218 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 2230 +/* 2222 */ MCD_OPC_CheckPredicate, 0, 15, 150, // Skip to: 40641 +/* 2226 */ MCD_OPC_Decode, 223, 5, 8, // Opcode: LD1Fourv2d +/* 2230 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 2242 +/* 2234 */ MCD_OPC_CheckPredicate, 0, 3, 150, // Skip to: 40641 +/* 2238 */ MCD_OPC_Decode, 233, 6, 9, // Opcode: LD3Threev16b +/* 2242 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 2254 +/* 2246 */ MCD_OPC_CheckPredicate, 0, 247, 149, // Skip to: 40641 +/* 2250 */ MCD_OPC_Decode, 245, 6, 9, // Opcode: LD3Threev8h +/* 2254 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2266 +/* 2258 */ MCD_OPC_CheckPredicate, 0, 235, 149, // Skip to: 40641 +/* 2262 */ MCD_OPC_Decode, 241, 6, 9, // Opcode: LD3Threev4s +/* 2266 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2278 +/* 2270 */ MCD_OPC_CheckPredicate, 0, 223, 149, // Skip to: 40641 +/* 2274 */ MCD_OPC_Decode, 235, 6, 9, // Opcode: LD3Threev2d +/* 2278 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 2290 +/* 2282 */ MCD_OPC_CheckPredicate, 0, 211, 149, // Skip to: 40641 +/* 2286 */ MCD_OPC_Decode, 139, 6, 9, // Opcode: LD1Threev16b +/* 2290 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 2302 +/* 2294 */ MCD_OPC_CheckPredicate, 0, 199, 149, // Skip to: 40641 +/* 2298 */ MCD_OPC_Decode, 153, 6, 9, // Opcode: LD1Threev8h +/* 2302 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 2314 +/* 2306 */ MCD_OPC_CheckPredicate, 0, 187, 149, // Skip to: 40641 +/* 2310 */ MCD_OPC_Decode, 149, 6, 9, // Opcode: LD1Threev4s +/* 2314 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 2326 +/* 2318 */ MCD_OPC_CheckPredicate, 0, 175, 149, // Skip to: 40641 +/* 2322 */ MCD_OPC_Decode, 143, 6, 9, // Opcode: LD1Threev2d +/* 2326 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 2338 +/* 2330 */ MCD_OPC_CheckPredicate, 0, 163, 149, // Skip to: 40641 +/* 2334 */ MCD_OPC_Decode, 235, 5, 10, // Opcode: LD1Onev16b +/* 2338 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2350 +/* 2342 */ MCD_OPC_CheckPredicate, 0, 151, 149, // Skip to: 40641 +/* 2346 */ MCD_OPC_Decode, 249, 5, 10, // Opcode: LD1Onev8h +/* 2350 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2362 +/* 2354 */ MCD_OPC_CheckPredicate, 0, 139, 149, // Skip to: 40641 +/* 2358 */ MCD_OPC_Decode, 245, 5, 10, // Opcode: LD1Onev4s +/* 2362 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2374 +/* 2366 */ MCD_OPC_CheckPredicate, 0, 127, 149, // Skip to: 40641 +/* 2370 */ MCD_OPC_Decode, 239, 5, 10, // Opcode: LD1Onev2d +/* 2374 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2386 +/* 2378 */ MCD_OPC_CheckPredicate, 0, 115, 149, // Skip to: 40641 +/* 2382 */ MCD_OPC_Decode, 195, 6, 11, // Opcode: LD2Twov16b +/* 2386 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2398 +/* 2390 */ MCD_OPC_CheckPredicate, 0, 103, 149, // Skip to: 40641 +/* 2394 */ MCD_OPC_Decode, 207, 6, 11, // Opcode: LD2Twov8h +/* 2398 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2410 +/* 2402 */ MCD_OPC_CheckPredicate, 0, 91, 149, // Skip to: 40641 +/* 2406 */ MCD_OPC_Decode, 203, 6, 11, // Opcode: LD2Twov4s +/* 2410 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 2422 +/* 2414 */ MCD_OPC_CheckPredicate, 0, 79, 149, // Skip to: 40641 +/* 2418 */ MCD_OPC_Decode, 197, 6, 11, // Opcode: LD2Twov2d +/* 2422 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2434 +/* 2426 */ MCD_OPC_CheckPredicate, 0, 67, 149, // Skip to: 40641 +/* 2430 */ MCD_OPC_Decode, 155, 6, 11, // Opcode: LD1Twov16b +/* 2434 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2446 +/* 2438 */ MCD_OPC_CheckPredicate, 0, 55, 149, // Skip to: 40641 +/* 2442 */ MCD_OPC_Decode, 169, 6, 11, // Opcode: LD1Twov8h +/* 2446 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2458 +/* 2450 */ MCD_OPC_CheckPredicate, 0, 43, 149, // Skip to: 40641 +/* 2454 */ MCD_OPC_Decode, 165, 6, 11, // Opcode: LD1Twov4s +/* 2458 */ MCD_OPC_FilterValue, 43, 35, 149, // Skip to: 40641 +/* 2462 */ MCD_OPC_CheckPredicate, 0, 31, 149, // Skip to: 40641 +/* 2466 */ MCD_OPC_Decode, 159, 6, 11, // Opcode: LD1Twov2d +/* 2470 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2478 +/* 2474 */ MCD_OPC_Decode, 175, 7, 3, // Opcode: LDNPDi +/* 2478 */ MCD_OPC_FilterValue, 5, 15, 149, // Skip to: 40641 +/* 2482 */ MCD_OPC_Decode, 176, 7, 3, // Opcode: LDNPQi +/* 2486 */ MCD_OPC_FilterValue, 2, 227, 3, // Skip to: 3485 +/* 2490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 2493 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 2950 +/* 2497 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 2500 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2518 +/* 2504 */ MCD_OPC_CheckPredicate, 0, 245, 148, // Skip to: 40641 +/* 2508 */ MCD_OPC_CheckField, 21, 1, 0, 239, 148, // Skip to: 40641 +/* 2514 */ MCD_OPC_Decode, 174, 14, 12, // Opcode: ST4Fourv8b_POST +/* 2518 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2536 +/* 2522 */ MCD_OPC_CheckPredicate, 0, 227, 148, // Skip to: 40641 +/* 2526 */ MCD_OPC_CheckField, 21, 1, 0, 221, 148, // Skip to: 40641 +/* 2532 */ MCD_OPC_Decode, 170, 14, 12, // Opcode: ST4Fourv4h_POST +/* 2536 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2554 +/* 2540 */ MCD_OPC_CheckPredicate, 0, 209, 148, // Skip to: 40641 +/* 2544 */ MCD_OPC_CheckField, 21, 1, 0, 203, 148, // Skip to: 40641 +/* 2550 */ MCD_OPC_Decode, 168, 14, 12, // Opcode: ST4Fourv2s_POST +/* 2554 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 2572 +/* 2558 */ MCD_OPC_CheckPredicate, 0, 191, 148, // Skip to: 40641 +/* 2562 */ MCD_OPC_CheckField, 21, 1, 0, 185, 148, // Skip to: 40641 +/* 2568 */ MCD_OPC_Decode, 188, 13, 12, // Opcode: ST1Fourv8b_POST +/* 2572 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 2590 +/* 2576 */ MCD_OPC_CheckPredicate, 0, 173, 148, // Skip to: 40641 +/* 2580 */ MCD_OPC_CheckField, 21, 1, 0, 167, 148, // Skip to: 40641 +/* 2586 */ MCD_OPC_Decode, 184, 13, 12, // Opcode: ST1Fourv4h_POST +/* 2590 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2608 +/* 2594 */ MCD_OPC_CheckPredicate, 0, 155, 148, // Skip to: 40641 +/* 2598 */ MCD_OPC_CheckField, 21, 1, 0, 149, 148, // Skip to: 40641 +/* 2604 */ MCD_OPC_Decode, 182, 13, 12, // Opcode: ST1Fourv2s_POST +/* 2608 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2626 +/* 2612 */ MCD_OPC_CheckPredicate, 0, 137, 148, // Skip to: 40641 +/* 2616 */ MCD_OPC_CheckField, 21, 1, 0, 131, 148, // Skip to: 40641 +/* 2622 */ MCD_OPC_Decode, 178, 13, 12, // Opcode: ST1Fourv1d_POST +/* 2626 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 2644 +/* 2630 */ MCD_OPC_CheckPredicate, 0, 119, 148, // Skip to: 40641 +/* 2634 */ MCD_OPC_CheckField, 21, 1, 0, 113, 148, // Skip to: 40641 +/* 2640 */ MCD_OPC_Decode, 152, 14, 13, // Opcode: ST3Threev8b_POST +/* 2644 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 2662 +/* 2648 */ MCD_OPC_CheckPredicate, 0, 101, 148, // Skip to: 40641 +/* 2652 */ MCD_OPC_CheckField, 21, 1, 0, 95, 148, // Skip to: 40641 +/* 2658 */ MCD_OPC_Decode, 148, 14, 13, // Opcode: ST3Threev4h_POST +/* 2662 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 2680 +/* 2666 */ MCD_OPC_CheckPredicate, 0, 83, 148, // Skip to: 40641 +/* 2670 */ MCD_OPC_CheckField, 21, 1, 0, 77, 148, // Skip to: 40641 +/* 2676 */ MCD_OPC_Decode, 146, 14, 13, // Opcode: ST3Threev2s_POST +/* 2680 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 2698 +/* 2684 */ MCD_OPC_CheckPredicate, 0, 65, 148, // Skip to: 40641 +/* 2688 */ MCD_OPC_CheckField, 21, 1, 0, 59, 148, // Skip to: 40641 +/* 2694 */ MCD_OPC_Decode, 220, 13, 13, // Opcode: ST1Threev8b_POST +/* 2698 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 2716 +/* 2702 */ MCD_OPC_CheckPredicate, 0, 47, 148, // Skip to: 40641 +/* 2706 */ MCD_OPC_CheckField, 21, 1, 0, 41, 148, // Skip to: 40641 +/* 2712 */ MCD_OPC_Decode, 216, 13, 13, // Opcode: ST1Threev4h_POST +/* 2716 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 2734 +/* 2720 */ MCD_OPC_CheckPredicate, 0, 29, 148, // Skip to: 40641 +/* 2724 */ MCD_OPC_CheckField, 21, 1, 0, 23, 148, // Skip to: 40641 +/* 2730 */ MCD_OPC_Decode, 214, 13, 13, // Opcode: ST1Threev2s_POST +/* 2734 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 2752 +/* 2738 */ MCD_OPC_CheckPredicate, 0, 11, 148, // Skip to: 40641 +/* 2742 */ MCD_OPC_CheckField, 21, 1, 0, 5, 148, // Skip to: 40641 +/* 2748 */ MCD_OPC_Decode, 210, 13, 13, // Opcode: ST1Threev1d_POST +/* 2752 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 2770 +/* 2756 */ MCD_OPC_CheckPredicate, 0, 249, 147, // Skip to: 40641 +/* 2760 */ MCD_OPC_CheckField, 21, 1, 0, 243, 147, // Skip to: 40641 +/* 2766 */ MCD_OPC_Decode, 204, 13, 14, // Opcode: ST1Onev8b_POST +/* 2770 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 2788 +/* 2774 */ MCD_OPC_CheckPredicate, 0, 231, 147, // Skip to: 40641 +/* 2778 */ MCD_OPC_CheckField, 21, 1, 0, 225, 147, // Skip to: 40641 +/* 2784 */ MCD_OPC_Decode, 200, 13, 14, // Opcode: ST1Onev4h_POST +/* 2788 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 2806 +/* 2792 */ MCD_OPC_CheckPredicate, 0, 213, 147, // Skip to: 40641 +/* 2796 */ MCD_OPC_CheckField, 21, 1, 0, 207, 147, // Skip to: 40641 +/* 2802 */ MCD_OPC_Decode, 198, 13, 14, // Opcode: ST1Onev2s_POST +/* 2806 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 2824 +/* 2810 */ MCD_OPC_CheckPredicate, 0, 195, 147, // Skip to: 40641 +/* 2814 */ MCD_OPC_CheckField, 21, 1, 0, 189, 147, // Skip to: 40641 +/* 2820 */ MCD_OPC_Decode, 194, 13, 14, // Opcode: ST1Onev1d_POST +/* 2824 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2842 +/* 2828 */ MCD_OPC_CheckPredicate, 0, 177, 147, // Skip to: 40641 +/* 2832 */ MCD_OPC_CheckField, 21, 1, 0, 171, 147, // Skip to: 40641 +/* 2838 */ MCD_OPC_Decode, 130, 14, 15, // Opcode: ST2Twov8b_POST +/* 2842 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2860 +/* 2846 */ MCD_OPC_CheckPredicate, 0, 159, 147, // Skip to: 40641 +/* 2850 */ MCD_OPC_CheckField, 21, 1, 0, 153, 147, // Skip to: 40641 +/* 2856 */ MCD_OPC_Decode, 254, 13, 15, // Opcode: ST2Twov4h_POST +/* 2860 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 2878 +/* 2864 */ MCD_OPC_CheckPredicate, 0, 141, 147, // Skip to: 40641 +/* 2868 */ MCD_OPC_CheckField, 21, 1, 0, 135, 147, // Skip to: 40641 +/* 2874 */ MCD_OPC_Decode, 252, 13, 15, // Opcode: ST2Twov2s_POST +/* 2878 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 2896 +/* 2882 */ MCD_OPC_CheckPredicate, 0, 123, 147, // Skip to: 40641 +/* 2886 */ MCD_OPC_CheckField, 21, 1, 0, 117, 147, // Skip to: 40641 +/* 2892 */ MCD_OPC_Decode, 236, 13, 15, // Opcode: ST1Twov8b_POST +/* 2896 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 2914 +/* 2900 */ MCD_OPC_CheckPredicate, 0, 105, 147, // Skip to: 40641 +/* 2904 */ MCD_OPC_CheckField, 21, 1, 0, 99, 147, // Skip to: 40641 +/* 2910 */ MCD_OPC_Decode, 232, 13, 15, // Opcode: ST1Twov4h_POST +/* 2914 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 2932 +/* 2918 */ MCD_OPC_CheckPredicate, 0, 87, 147, // Skip to: 40641 +/* 2922 */ MCD_OPC_CheckField, 21, 1, 0, 81, 147, // Skip to: 40641 +/* 2928 */ MCD_OPC_Decode, 230, 13, 15, // Opcode: ST1Twov2s_POST +/* 2932 */ MCD_OPC_FilterValue, 43, 73, 147, // Skip to: 40641 +/* 2936 */ MCD_OPC_CheckPredicate, 0, 69, 147, // Skip to: 40641 +/* 2940 */ MCD_OPC_CheckField, 21, 1, 0, 63, 147, // Skip to: 40641 +/* 2946 */ MCD_OPC_Decode, 226, 13, 15, // Opcode: ST1Twov1d_POST +/* 2950 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2958 +/* 2954 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: STPSpost +/* 2958 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 3469 +/* 2962 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 2965 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2983 +/* 2969 */ MCD_OPC_CheckPredicate, 0, 36, 147, // Skip to: 40641 +/* 2973 */ MCD_OPC_CheckField, 21, 1, 0, 30, 147, // Skip to: 40641 +/* 2979 */ MCD_OPC_Decode, 164, 14, 16, // Opcode: ST4Fourv16b_POST +/* 2983 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3001 +/* 2987 */ MCD_OPC_CheckPredicate, 0, 18, 147, // Skip to: 40641 +/* 2991 */ MCD_OPC_CheckField, 21, 1, 0, 12, 147, // Skip to: 40641 +/* 2997 */ MCD_OPC_Decode, 176, 14, 16, // Opcode: ST4Fourv8h_POST +/* 3001 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3019 +/* 3005 */ MCD_OPC_CheckPredicate, 0, 0, 147, // Skip to: 40641 +/* 3009 */ MCD_OPC_CheckField, 21, 1, 0, 250, 146, // Skip to: 40641 +/* 3015 */ MCD_OPC_Decode, 172, 14, 16, // Opcode: ST4Fourv4s_POST +/* 3019 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3037 +/* 3023 */ MCD_OPC_CheckPredicate, 0, 238, 146, // Skip to: 40641 +/* 3027 */ MCD_OPC_CheckField, 21, 1, 0, 232, 146, // Skip to: 40641 +/* 3033 */ MCD_OPC_Decode, 166, 14, 16, // Opcode: ST4Fourv2d_POST +/* 3037 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3055 +/* 3041 */ MCD_OPC_CheckPredicate, 0, 220, 146, // Skip to: 40641 +/* 3045 */ MCD_OPC_CheckField, 21, 1, 0, 214, 146, // Skip to: 40641 +/* 3051 */ MCD_OPC_Decode, 176, 13, 16, // Opcode: ST1Fourv16b_POST +/* 3055 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3073 +/* 3059 */ MCD_OPC_CheckPredicate, 0, 202, 146, // Skip to: 40641 +/* 3063 */ MCD_OPC_CheckField, 21, 1, 0, 196, 146, // Skip to: 40641 +/* 3069 */ MCD_OPC_Decode, 190, 13, 16, // Opcode: ST1Fourv8h_POST +/* 3073 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3091 +/* 3077 */ MCD_OPC_CheckPredicate, 0, 184, 146, // Skip to: 40641 +/* 3081 */ MCD_OPC_CheckField, 21, 1, 0, 178, 146, // Skip to: 40641 +/* 3087 */ MCD_OPC_Decode, 186, 13, 16, // Opcode: ST1Fourv4s_POST +/* 3091 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3109 +/* 3095 */ MCD_OPC_CheckPredicate, 0, 166, 146, // Skip to: 40641 +/* 3099 */ MCD_OPC_CheckField, 21, 1, 0, 160, 146, // Skip to: 40641 +/* 3105 */ MCD_OPC_Decode, 180, 13, 16, // Opcode: ST1Fourv2d_POST +/* 3109 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3127 +/* 3113 */ MCD_OPC_CheckPredicate, 0, 148, 146, // Skip to: 40641 +/* 3117 */ MCD_OPC_CheckField, 21, 1, 0, 142, 146, // Skip to: 40641 +/* 3123 */ MCD_OPC_Decode, 142, 14, 17, // Opcode: ST3Threev16b_POST +/* 3127 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3145 +/* 3131 */ MCD_OPC_CheckPredicate, 0, 130, 146, // Skip to: 40641 +/* 3135 */ MCD_OPC_CheckField, 21, 1, 0, 124, 146, // Skip to: 40641 +/* 3141 */ MCD_OPC_Decode, 154, 14, 17, // Opcode: ST3Threev8h_POST +/* 3145 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3163 +/* 3149 */ MCD_OPC_CheckPredicate, 0, 112, 146, // Skip to: 40641 +/* 3153 */ MCD_OPC_CheckField, 21, 1, 0, 106, 146, // Skip to: 40641 +/* 3159 */ MCD_OPC_Decode, 150, 14, 17, // Opcode: ST3Threev4s_POST +/* 3163 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 3181 +/* 3167 */ MCD_OPC_CheckPredicate, 0, 94, 146, // Skip to: 40641 +/* 3171 */ MCD_OPC_CheckField, 21, 1, 0, 88, 146, // Skip to: 40641 +/* 3177 */ MCD_OPC_Decode, 144, 14, 17, // Opcode: ST3Threev2d_POST +/* 3181 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3199 +/* 3185 */ MCD_OPC_CheckPredicate, 0, 76, 146, // Skip to: 40641 +/* 3189 */ MCD_OPC_CheckField, 21, 1, 0, 70, 146, // Skip to: 40641 +/* 3195 */ MCD_OPC_Decode, 208, 13, 17, // Opcode: ST1Threev16b_POST +/* 3199 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3217 +/* 3203 */ MCD_OPC_CheckPredicate, 0, 58, 146, // Skip to: 40641 +/* 3207 */ MCD_OPC_CheckField, 21, 1, 0, 52, 146, // Skip to: 40641 +/* 3213 */ MCD_OPC_Decode, 222, 13, 17, // Opcode: ST1Threev8h_POST +/* 3217 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3235 +/* 3221 */ MCD_OPC_CheckPredicate, 0, 40, 146, // Skip to: 40641 +/* 3225 */ MCD_OPC_CheckField, 21, 1, 0, 34, 146, // Skip to: 40641 +/* 3231 */ MCD_OPC_Decode, 218, 13, 17, // Opcode: ST1Threev4s_POST +/* 3235 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3253 +/* 3239 */ MCD_OPC_CheckPredicate, 0, 22, 146, // Skip to: 40641 +/* 3243 */ MCD_OPC_CheckField, 21, 1, 0, 16, 146, // Skip to: 40641 +/* 3249 */ MCD_OPC_Decode, 212, 13, 17, // Opcode: ST1Threev2d_POST +/* 3253 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3271 +/* 3257 */ MCD_OPC_CheckPredicate, 0, 4, 146, // Skip to: 40641 +/* 3261 */ MCD_OPC_CheckField, 21, 1, 0, 254, 145, // Skip to: 40641 +/* 3267 */ MCD_OPC_Decode, 192, 13, 18, // Opcode: ST1Onev16b_POST +/* 3271 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3289 +/* 3275 */ MCD_OPC_CheckPredicate, 0, 242, 145, // Skip to: 40641 +/* 3279 */ MCD_OPC_CheckField, 21, 1, 0, 236, 145, // Skip to: 40641 +/* 3285 */ MCD_OPC_Decode, 206, 13, 18, // Opcode: ST1Onev8h_POST +/* 3289 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3307 +/* 3293 */ MCD_OPC_CheckPredicate, 0, 224, 145, // Skip to: 40641 +/* 3297 */ MCD_OPC_CheckField, 21, 1, 0, 218, 145, // Skip to: 40641 +/* 3303 */ MCD_OPC_Decode, 202, 13, 18, // Opcode: ST1Onev4s_POST +/* 3307 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3325 +/* 3311 */ MCD_OPC_CheckPredicate, 0, 206, 145, // Skip to: 40641 +/* 3315 */ MCD_OPC_CheckField, 21, 1, 0, 200, 145, // Skip to: 40641 +/* 3321 */ MCD_OPC_Decode, 196, 13, 18, // Opcode: ST1Onev2d_POST +/* 3325 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3343 +/* 3329 */ MCD_OPC_CheckPredicate, 0, 188, 145, // Skip to: 40641 +/* 3333 */ MCD_OPC_CheckField, 21, 1, 0, 182, 145, // Skip to: 40641 +/* 3339 */ MCD_OPC_Decode, 248, 13, 19, // Opcode: ST2Twov16b_POST +/* 3343 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3361 +/* 3347 */ MCD_OPC_CheckPredicate, 0, 170, 145, // Skip to: 40641 +/* 3351 */ MCD_OPC_CheckField, 21, 1, 0, 164, 145, // Skip to: 40641 +/* 3357 */ MCD_OPC_Decode, 132, 14, 19, // Opcode: ST2Twov8h_POST +/* 3361 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3379 +/* 3365 */ MCD_OPC_CheckPredicate, 0, 152, 145, // Skip to: 40641 +/* 3369 */ MCD_OPC_CheckField, 21, 1, 0, 146, 145, // Skip to: 40641 +/* 3375 */ MCD_OPC_Decode, 128, 14, 19, // Opcode: ST2Twov4s_POST +/* 3379 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 3397 +/* 3383 */ MCD_OPC_CheckPredicate, 0, 134, 145, // Skip to: 40641 +/* 3387 */ MCD_OPC_CheckField, 21, 1, 0, 128, 145, // Skip to: 40641 +/* 3393 */ MCD_OPC_Decode, 250, 13, 19, // Opcode: ST2Twov2d_POST +/* 3397 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3415 +/* 3401 */ MCD_OPC_CheckPredicate, 0, 116, 145, // Skip to: 40641 +/* 3405 */ MCD_OPC_CheckField, 21, 1, 0, 110, 145, // Skip to: 40641 +/* 3411 */ MCD_OPC_Decode, 224, 13, 19, // Opcode: ST1Twov16b_POST +/* 3415 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3433 +/* 3419 */ MCD_OPC_CheckPredicate, 0, 98, 145, // Skip to: 40641 +/* 3423 */ MCD_OPC_CheckField, 21, 1, 0, 92, 145, // Skip to: 40641 +/* 3429 */ MCD_OPC_Decode, 238, 13, 19, // Opcode: ST1Twov8h_POST +/* 3433 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3451 +/* 3437 */ MCD_OPC_CheckPredicate, 0, 80, 145, // Skip to: 40641 +/* 3441 */ MCD_OPC_CheckField, 21, 1, 0, 74, 145, // Skip to: 40641 +/* 3447 */ MCD_OPC_Decode, 234, 13, 19, // Opcode: ST1Twov4s_POST +/* 3451 */ MCD_OPC_FilterValue, 43, 66, 145, // Skip to: 40641 +/* 3455 */ MCD_OPC_CheckPredicate, 0, 62, 145, // Skip to: 40641 +/* 3459 */ MCD_OPC_CheckField, 21, 1, 0, 56, 145, // Skip to: 40641 +/* 3465 */ MCD_OPC_Decode, 228, 13, 19, // Opcode: ST1Twov2d_POST +/* 3469 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3477 +/* 3473 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: STPDpost +/* 3477 */ MCD_OPC_FilterValue, 5, 40, 145, // Skip to: 40641 +/* 3481 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: STPQpost +/* 3485 */ MCD_OPC_FilterValue, 3, 227, 3, // Skip to: 4484 +/* 3489 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 3492 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 3949 +/* 3496 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3499 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3517 +/* 3503 */ MCD_OPC_CheckPredicate, 0, 14, 145, // Skip to: 40641 +/* 3507 */ MCD_OPC_CheckField, 21, 1, 0, 8, 145, // Skip to: 40641 +/* 3513 */ MCD_OPC_Decode, 138, 7, 12, // Opcode: LD4Fourv8b_POST +/* 3517 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3535 +/* 3521 */ MCD_OPC_CheckPredicate, 0, 252, 144, // Skip to: 40641 +/* 3525 */ MCD_OPC_CheckField, 21, 1, 0, 246, 144, // Skip to: 40641 +/* 3531 */ MCD_OPC_Decode, 134, 7, 12, // Opcode: LD4Fourv4h_POST +/* 3535 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3553 +/* 3539 */ MCD_OPC_CheckPredicate, 0, 234, 144, // Skip to: 40641 +/* 3543 */ MCD_OPC_CheckField, 21, 1, 0, 228, 144, // Skip to: 40641 +/* 3549 */ MCD_OPC_Decode, 132, 7, 12, // Opcode: LD4Fourv2s_POST +/* 3553 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3571 +/* 3557 */ MCD_OPC_CheckPredicate, 0, 216, 144, // Skip to: 40641 +/* 3561 */ MCD_OPC_CheckField, 21, 1, 0, 210, 144, // Skip to: 40641 +/* 3567 */ MCD_OPC_Decode, 232, 5, 12, // Opcode: LD1Fourv8b_POST +/* 3571 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3589 +/* 3575 */ MCD_OPC_CheckPredicate, 0, 198, 144, // Skip to: 40641 +/* 3579 */ MCD_OPC_CheckField, 21, 1, 0, 192, 144, // Skip to: 40641 +/* 3585 */ MCD_OPC_Decode, 228, 5, 12, // Opcode: LD1Fourv4h_POST +/* 3589 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3607 +/* 3593 */ MCD_OPC_CheckPredicate, 0, 180, 144, // Skip to: 40641 +/* 3597 */ MCD_OPC_CheckField, 21, 1, 0, 174, 144, // Skip to: 40641 +/* 3603 */ MCD_OPC_Decode, 226, 5, 12, // Opcode: LD1Fourv2s_POST +/* 3607 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3625 +/* 3611 */ MCD_OPC_CheckPredicate, 0, 162, 144, // Skip to: 40641 +/* 3615 */ MCD_OPC_CheckField, 21, 1, 0, 156, 144, // Skip to: 40641 +/* 3621 */ MCD_OPC_Decode, 222, 5, 12, // Opcode: LD1Fourv1d_POST +/* 3625 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3643 +/* 3629 */ MCD_OPC_CheckPredicate, 0, 144, 144, // Skip to: 40641 +/* 3633 */ MCD_OPC_CheckField, 21, 1, 0, 138, 144, // Skip to: 40641 +/* 3639 */ MCD_OPC_Decode, 244, 6, 13, // Opcode: LD3Threev8b_POST +/* 3643 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3661 +/* 3647 */ MCD_OPC_CheckPredicate, 0, 126, 144, // Skip to: 40641 +/* 3651 */ MCD_OPC_CheckField, 21, 1, 0, 120, 144, // Skip to: 40641 +/* 3657 */ MCD_OPC_Decode, 240, 6, 13, // Opcode: LD3Threev4h_POST +/* 3661 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3679 +/* 3665 */ MCD_OPC_CheckPredicate, 0, 108, 144, // Skip to: 40641 +/* 3669 */ MCD_OPC_CheckField, 21, 1, 0, 102, 144, // Skip to: 40641 +/* 3675 */ MCD_OPC_Decode, 238, 6, 13, // Opcode: LD3Threev2s_POST +/* 3679 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3697 +/* 3683 */ MCD_OPC_CheckPredicate, 0, 90, 144, // Skip to: 40641 +/* 3687 */ MCD_OPC_CheckField, 21, 1, 0, 84, 144, // Skip to: 40641 +/* 3693 */ MCD_OPC_Decode, 152, 6, 13, // Opcode: LD1Threev8b_POST +/* 3697 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3715 +/* 3701 */ MCD_OPC_CheckPredicate, 0, 72, 144, // Skip to: 40641 +/* 3705 */ MCD_OPC_CheckField, 21, 1, 0, 66, 144, // Skip to: 40641 +/* 3711 */ MCD_OPC_Decode, 148, 6, 13, // Opcode: LD1Threev4h_POST +/* 3715 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3733 +/* 3719 */ MCD_OPC_CheckPredicate, 0, 54, 144, // Skip to: 40641 +/* 3723 */ MCD_OPC_CheckField, 21, 1, 0, 48, 144, // Skip to: 40641 +/* 3729 */ MCD_OPC_Decode, 146, 6, 13, // Opcode: LD1Threev2s_POST +/* 3733 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3751 +/* 3737 */ MCD_OPC_CheckPredicate, 0, 36, 144, // Skip to: 40641 +/* 3741 */ MCD_OPC_CheckField, 21, 1, 0, 30, 144, // Skip to: 40641 +/* 3747 */ MCD_OPC_Decode, 142, 6, 13, // Opcode: LD1Threev1d_POST +/* 3751 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3769 +/* 3755 */ MCD_OPC_CheckPredicate, 0, 18, 144, // Skip to: 40641 +/* 3759 */ MCD_OPC_CheckField, 21, 1, 0, 12, 144, // Skip to: 40641 +/* 3765 */ MCD_OPC_Decode, 248, 5, 14, // Opcode: LD1Onev8b_POST +/* 3769 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3787 +/* 3773 */ MCD_OPC_CheckPredicate, 0, 0, 144, // Skip to: 40641 +/* 3777 */ MCD_OPC_CheckField, 21, 1, 0, 250, 143, // Skip to: 40641 +/* 3783 */ MCD_OPC_Decode, 244, 5, 14, // Opcode: LD1Onev4h_POST +/* 3787 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3805 +/* 3791 */ MCD_OPC_CheckPredicate, 0, 238, 143, // Skip to: 40641 +/* 3795 */ MCD_OPC_CheckField, 21, 1, 0, 232, 143, // Skip to: 40641 +/* 3801 */ MCD_OPC_Decode, 242, 5, 14, // Opcode: LD1Onev2s_POST +/* 3805 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3823 +/* 3809 */ MCD_OPC_CheckPredicate, 0, 220, 143, // Skip to: 40641 +/* 3813 */ MCD_OPC_CheckField, 21, 1, 0, 214, 143, // Skip to: 40641 +/* 3819 */ MCD_OPC_Decode, 238, 5, 14, // Opcode: LD1Onev1d_POST +/* 3823 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3841 +/* 3827 */ MCD_OPC_CheckPredicate, 0, 202, 143, // Skip to: 40641 +/* 3831 */ MCD_OPC_CheckField, 21, 1, 0, 196, 143, // Skip to: 40641 +/* 3837 */ MCD_OPC_Decode, 206, 6, 15, // Opcode: LD2Twov8b_POST +/* 3841 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3859 +/* 3845 */ MCD_OPC_CheckPredicate, 0, 184, 143, // Skip to: 40641 +/* 3849 */ MCD_OPC_CheckField, 21, 1, 0, 178, 143, // Skip to: 40641 +/* 3855 */ MCD_OPC_Decode, 202, 6, 15, // Opcode: LD2Twov4h_POST +/* 3859 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3877 +/* 3863 */ MCD_OPC_CheckPredicate, 0, 166, 143, // Skip to: 40641 +/* 3867 */ MCD_OPC_CheckField, 21, 1, 0, 160, 143, // Skip to: 40641 +/* 3873 */ MCD_OPC_Decode, 200, 6, 15, // Opcode: LD2Twov2s_POST +/* 3877 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3895 +/* 3881 */ MCD_OPC_CheckPredicate, 0, 148, 143, // Skip to: 40641 +/* 3885 */ MCD_OPC_CheckField, 21, 1, 0, 142, 143, // Skip to: 40641 +/* 3891 */ MCD_OPC_Decode, 168, 6, 15, // Opcode: LD1Twov8b_POST +/* 3895 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3913 +/* 3899 */ MCD_OPC_CheckPredicate, 0, 130, 143, // Skip to: 40641 +/* 3903 */ MCD_OPC_CheckField, 21, 1, 0, 124, 143, // Skip to: 40641 +/* 3909 */ MCD_OPC_Decode, 164, 6, 15, // Opcode: LD1Twov4h_POST +/* 3913 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3931 +/* 3917 */ MCD_OPC_CheckPredicate, 0, 112, 143, // Skip to: 40641 +/* 3921 */ MCD_OPC_CheckField, 21, 1, 0, 106, 143, // Skip to: 40641 +/* 3927 */ MCD_OPC_Decode, 162, 6, 15, // Opcode: LD1Twov2s_POST +/* 3931 */ MCD_OPC_FilterValue, 43, 98, 143, // Skip to: 40641 +/* 3935 */ MCD_OPC_CheckPredicate, 0, 94, 143, // Skip to: 40641 +/* 3939 */ MCD_OPC_CheckField, 21, 1, 0, 88, 143, // Skip to: 40641 +/* 3945 */ MCD_OPC_Decode, 158, 6, 15, // Opcode: LD1Twov1d_POST +/* 3949 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3957 +/* 3953 */ MCD_OPC_Decode, 190, 7, 3, // Opcode: LDPSpost +/* 3957 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 4468 +/* 3961 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3964 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3982 +/* 3968 */ MCD_OPC_CheckPredicate, 0, 61, 143, // Skip to: 40641 +/* 3972 */ MCD_OPC_CheckField, 21, 1, 0, 55, 143, // Skip to: 40641 +/* 3978 */ MCD_OPC_Decode, 128, 7, 16, // Opcode: LD4Fourv16b_POST +/* 3982 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4000 +/* 3986 */ MCD_OPC_CheckPredicate, 0, 43, 143, // Skip to: 40641 +/* 3990 */ MCD_OPC_CheckField, 21, 1, 0, 37, 143, // Skip to: 40641 +/* 3996 */ MCD_OPC_Decode, 140, 7, 16, // Opcode: LD4Fourv8h_POST +/* 4000 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 4018 +/* 4004 */ MCD_OPC_CheckPredicate, 0, 25, 143, // Skip to: 40641 +/* 4008 */ MCD_OPC_CheckField, 21, 1, 0, 19, 143, // Skip to: 40641 +/* 4014 */ MCD_OPC_Decode, 136, 7, 16, // Opcode: LD4Fourv4s_POST +/* 4018 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 4036 +/* 4022 */ MCD_OPC_CheckPredicate, 0, 7, 143, // Skip to: 40641 +/* 4026 */ MCD_OPC_CheckField, 21, 1, 0, 1, 143, // Skip to: 40641 +/* 4032 */ MCD_OPC_Decode, 130, 7, 16, // Opcode: LD4Fourv2d_POST +/* 4036 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 4054 +/* 4040 */ MCD_OPC_CheckPredicate, 0, 245, 142, // Skip to: 40641 +/* 4044 */ MCD_OPC_CheckField, 21, 1, 0, 239, 142, // Skip to: 40641 +/* 4050 */ MCD_OPC_Decode, 220, 5, 16, // Opcode: LD1Fourv16b_POST +/* 4054 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 4072 +/* 4058 */ MCD_OPC_CheckPredicate, 0, 227, 142, // Skip to: 40641 +/* 4062 */ MCD_OPC_CheckField, 21, 1, 0, 221, 142, // Skip to: 40641 +/* 4068 */ MCD_OPC_Decode, 234, 5, 16, // Opcode: LD1Fourv8h_POST +/* 4072 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 4090 +/* 4076 */ MCD_OPC_CheckPredicate, 0, 209, 142, // Skip to: 40641 +/* 4080 */ MCD_OPC_CheckField, 21, 1, 0, 203, 142, // Skip to: 40641 +/* 4086 */ MCD_OPC_Decode, 230, 5, 16, // Opcode: LD1Fourv4s_POST +/* 4090 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 4108 +/* 4094 */ MCD_OPC_CheckPredicate, 0, 191, 142, // Skip to: 40641 +/* 4098 */ MCD_OPC_CheckField, 21, 1, 0, 185, 142, // Skip to: 40641 +/* 4104 */ MCD_OPC_Decode, 224, 5, 16, // Opcode: LD1Fourv2d_POST +/* 4108 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 4126 +/* 4112 */ MCD_OPC_CheckPredicate, 0, 173, 142, // Skip to: 40641 +/* 4116 */ MCD_OPC_CheckField, 21, 1, 0, 167, 142, // Skip to: 40641 +/* 4122 */ MCD_OPC_Decode, 234, 6, 17, // Opcode: LD3Threev16b_POST +/* 4126 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 4144 +/* 4130 */ MCD_OPC_CheckPredicate, 0, 155, 142, // Skip to: 40641 +/* 4134 */ MCD_OPC_CheckField, 21, 1, 0, 149, 142, // Skip to: 40641 +/* 4140 */ MCD_OPC_Decode, 246, 6, 17, // Opcode: LD3Threev8h_POST +/* 4144 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 4162 +/* 4148 */ MCD_OPC_CheckPredicate, 0, 137, 142, // Skip to: 40641 +/* 4152 */ MCD_OPC_CheckField, 21, 1, 0, 131, 142, // Skip to: 40641 +/* 4158 */ MCD_OPC_Decode, 242, 6, 17, // Opcode: LD3Threev4s_POST +/* 4162 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 4180 +/* 4166 */ MCD_OPC_CheckPredicate, 0, 119, 142, // Skip to: 40641 +/* 4170 */ MCD_OPC_CheckField, 21, 1, 0, 113, 142, // Skip to: 40641 +/* 4176 */ MCD_OPC_Decode, 236, 6, 17, // Opcode: LD3Threev2d_POST +/* 4180 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 4198 +/* 4184 */ MCD_OPC_CheckPredicate, 0, 101, 142, // Skip to: 40641 +/* 4188 */ MCD_OPC_CheckField, 21, 1, 0, 95, 142, // Skip to: 40641 +/* 4194 */ MCD_OPC_Decode, 140, 6, 17, // Opcode: LD1Threev16b_POST +/* 4198 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 4216 +/* 4202 */ MCD_OPC_CheckPredicate, 0, 83, 142, // Skip to: 40641 +/* 4206 */ MCD_OPC_CheckField, 21, 1, 0, 77, 142, // Skip to: 40641 +/* 4212 */ MCD_OPC_Decode, 154, 6, 17, // Opcode: LD1Threev8h_POST +/* 4216 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 4234 +/* 4220 */ MCD_OPC_CheckPredicate, 0, 65, 142, // Skip to: 40641 +/* 4224 */ MCD_OPC_CheckField, 21, 1, 0, 59, 142, // Skip to: 40641 +/* 4230 */ MCD_OPC_Decode, 150, 6, 17, // Opcode: LD1Threev4s_POST +/* 4234 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 4252 +/* 4238 */ MCD_OPC_CheckPredicate, 0, 47, 142, // Skip to: 40641 +/* 4242 */ MCD_OPC_CheckField, 21, 1, 0, 41, 142, // Skip to: 40641 +/* 4248 */ MCD_OPC_Decode, 144, 6, 17, // Opcode: LD1Threev2d_POST +/* 4252 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 4270 +/* 4256 */ MCD_OPC_CheckPredicate, 0, 29, 142, // Skip to: 40641 +/* 4260 */ MCD_OPC_CheckField, 21, 1, 0, 23, 142, // Skip to: 40641 +/* 4266 */ MCD_OPC_Decode, 236, 5, 18, // Opcode: LD1Onev16b_POST +/* 4270 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 4288 +/* 4274 */ MCD_OPC_CheckPredicate, 0, 11, 142, // Skip to: 40641 +/* 4278 */ MCD_OPC_CheckField, 21, 1, 0, 5, 142, // Skip to: 40641 +/* 4284 */ MCD_OPC_Decode, 250, 5, 18, // Opcode: LD1Onev8h_POST +/* 4288 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 4306 +/* 4292 */ MCD_OPC_CheckPredicate, 0, 249, 141, // Skip to: 40641 +/* 4296 */ MCD_OPC_CheckField, 21, 1, 0, 243, 141, // Skip to: 40641 +/* 4302 */ MCD_OPC_Decode, 246, 5, 18, // Opcode: LD1Onev4s_POST +/* 4306 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 4324 +/* 4310 */ MCD_OPC_CheckPredicate, 0, 231, 141, // Skip to: 40641 +/* 4314 */ MCD_OPC_CheckField, 21, 1, 0, 225, 141, // Skip to: 40641 +/* 4320 */ MCD_OPC_Decode, 240, 5, 18, // Opcode: LD1Onev2d_POST +/* 4324 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 4342 +/* 4328 */ MCD_OPC_CheckPredicate, 0, 213, 141, // Skip to: 40641 +/* 4332 */ MCD_OPC_CheckField, 21, 1, 0, 207, 141, // Skip to: 40641 +/* 4338 */ MCD_OPC_Decode, 196, 6, 19, // Opcode: LD2Twov16b_POST +/* 4342 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 4360 +/* 4346 */ MCD_OPC_CheckPredicate, 0, 195, 141, // Skip to: 40641 +/* 4350 */ MCD_OPC_CheckField, 21, 1, 0, 189, 141, // Skip to: 40641 +/* 4356 */ MCD_OPC_Decode, 208, 6, 19, // Opcode: LD2Twov8h_POST +/* 4360 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 4378 +/* 4364 */ MCD_OPC_CheckPredicate, 0, 177, 141, // Skip to: 40641 +/* 4368 */ MCD_OPC_CheckField, 21, 1, 0, 171, 141, // Skip to: 40641 +/* 4374 */ MCD_OPC_Decode, 204, 6, 19, // Opcode: LD2Twov4s_POST +/* 4378 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 4396 +/* 4382 */ MCD_OPC_CheckPredicate, 0, 159, 141, // Skip to: 40641 +/* 4386 */ MCD_OPC_CheckField, 21, 1, 0, 153, 141, // Skip to: 40641 +/* 4392 */ MCD_OPC_Decode, 198, 6, 19, // Opcode: LD2Twov2d_POST +/* 4396 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 4414 +/* 4400 */ MCD_OPC_CheckPredicate, 0, 141, 141, // Skip to: 40641 +/* 4404 */ MCD_OPC_CheckField, 21, 1, 0, 135, 141, // Skip to: 40641 +/* 4410 */ MCD_OPC_Decode, 156, 6, 19, // Opcode: LD1Twov16b_POST +/* 4414 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 4432 +/* 4418 */ MCD_OPC_CheckPredicate, 0, 123, 141, // Skip to: 40641 +/* 4422 */ MCD_OPC_CheckField, 21, 1, 0, 117, 141, // Skip to: 40641 +/* 4428 */ MCD_OPC_Decode, 170, 6, 19, // Opcode: LD1Twov8h_POST +/* 4432 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 4450 +/* 4436 */ MCD_OPC_CheckPredicate, 0, 105, 141, // Skip to: 40641 +/* 4440 */ MCD_OPC_CheckField, 21, 1, 0, 99, 141, // Skip to: 40641 +/* 4446 */ MCD_OPC_Decode, 166, 6, 19, // Opcode: LD1Twov4s_POST +/* 4450 */ MCD_OPC_FilterValue, 43, 91, 141, // Skip to: 40641 +/* 4454 */ MCD_OPC_CheckPredicate, 0, 87, 141, // Skip to: 40641 +/* 4458 */ MCD_OPC_CheckField, 21, 1, 0, 81, 141, // Skip to: 40641 +/* 4464 */ MCD_OPC_Decode, 160, 6, 19, // Opcode: LD1Twov2d_POST +/* 4468 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 4476 +/* 4472 */ MCD_OPC_Decode, 181, 7, 3, // Opcode: LDPDpost +/* 4476 */ MCD_OPC_FilterValue, 5, 65, 141, // Skip to: 40641 +/* 4480 */ MCD_OPC_Decode, 184, 7, 3, // Opcode: LDPQpost +/* 4484 */ MCD_OPC_FilterValue, 4, 155, 1, // Skip to: 4899 +/* 4488 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 4491 */ MCD_OPC_FilterValue, 0, 117, 1, // Skip to: 4868 +/* 4495 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... +/* 4498 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4516 +/* 4502 */ MCD_OPC_CheckPredicate, 0, 39, 141, // Skip to: 40641 +/* 4506 */ MCD_OPC_CheckField, 31, 1, 0, 33, 141, // Skip to: 40641 +/* 4512 */ MCD_OPC_Decode, 245, 13, 20, // Opcode: ST1i8 +/* 4516 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4534 +/* 4520 */ MCD_OPC_CheckPredicate, 0, 21, 141, // Skip to: 40641 +/* 4524 */ MCD_OPC_CheckField, 31, 1, 0, 15, 141, // Skip to: 40641 +/* 4530 */ MCD_OPC_Decode, 161, 14, 21, // Opcode: ST3i8 +/* 4534 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4558 +/* 4538 */ MCD_OPC_CheckPredicate, 0, 3, 141, // Skip to: 40641 +/* 4542 */ MCD_OPC_CheckField, 31, 1, 0, 253, 140, // Skip to: 40641 +/* 4548 */ MCD_OPC_CheckField, 10, 1, 0, 247, 140, // Skip to: 40641 +/* 4554 */ MCD_OPC_Decode, 239, 13, 22, // Opcode: ST1i16 +/* 4558 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4582 +/* 4562 */ MCD_OPC_CheckPredicate, 0, 235, 140, // Skip to: 40641 +/* 4566 */ MCD_OPC_CheckField, 31, 1, 0, 229, 140, // Skip to: 40641 +/* 4572 */ MCD_OPC_CheckField, 10, 1, 0, 223, 140, // Skip to: 40641 +/* 4578 */ MCD_OPC_Decode, 155, 14, 23, // Opcode: ST3i16 +/* 4582 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 4631 +/* 4586 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 4589 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4607 +/* 4593 */ MCD_OPC_CheckPredicate, 0, 204, 140, // Skip to: 40641 +/* 4597 */ MCD_OPC_CheckField, 31, 1, 0, 198, 140, // Skip to: 40641 +/* 4603 */ MCD_OPC_Decode, 241, 13, 24, // Opcode: ST1i32 +/* 4607 */ MCD_OPC_FilterValue, 1, 190, 140, // Skip to: 40641 +/* 4611 */ MCD_OPC_CheckPredicate, 0, 186, 140, // Skip to: 40641 +/* 4615 */ MCD_OPC_CheckField, 31, 1, 0, 180, 140, // Skip to: 40641 +/* 4621 */ MCD_OPC_CheckField, 12, 1, 0, 174, 140, // Skip to: 40641 +/* 4627 */ MCD_OPC_Decode, 243, 13, 25, // Opcode: ST1i64 +/* 4631 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 4680 +/* 4635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 4638 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4656 +/* 4642 */ MCD_OPC_CheckPredicate, 0, 155, 140, // Skip to: 40641 +/* 4646 */ MCD_OPC_CheckField, 31, 1, 0, 149, 140, // Skip to: 40641 +/* 4652 */ MCD_OPC_Decode, 157, 14, 26, // Opcode: ST3i32 +/* 4656 */ MCD_OPC_FilterValue, 1, 141, 140, // Skip to: 40641 +/* 4660 */ MCD_OPC_CheckPredicate, 0, 137, 140, // Skip to: 40641 +/* 4664 */ MCD_OPC_CheckField, 31, 1, 0, 131, 140, // Skip to: 40641 +/* 4670 */ MCD_OPC_CheckField, 12, 1, 0, 125, 140, // Skip to: 40641 +/* 4676 */ MCD_OPC_Decode, 159, 14, 27, // Opcode: ST3i64 +/* 4680 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 4699 +/* 4685 */ MCD_OPC_CheckPredicate, 0, 112, 140, // Skip to: 40641 +/* 4689 */ MCD_OPC_CheckField, 31, 1, 0, 106, 140, // Skip to: 40641 +/* 4695 */ MCD_OPC_Decode, 139, 14, 28, // Opcode: ST2i8 +/* 4699 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 4718 +/* 4704 */ MCD_OPC_CheckPredicate, 0, 93, 140, // Skip to: 40641 +/* 4708 */ MCD_OPC_CheckField, 31, 1, 0, 87, 140, // Skip to: 40641 +/* 4714 */ MCD_OPC_Decode, 183, 14, 29, // Opcode: ST4i8 +/* 4718 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 4743 +/* 4723 */ MCD_OPC_CheckPredicate, 0, 74, 140, // Skip to: 40641 +/* 4727 */ MCD_OPC_CheckField, 31, 1, 0, 68, 140, // Skip to: 40641 +/* 4733 */ MCD_OPC_CheckField, 10, 1, 0, 62, 140, // Skip to: 40641 +/* 4739 */ MCD_OPC_Decode, 133, 14, 30, // Opcode: ST2i16 +/* 4743 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 4768 +/* 4748 */ MCD_OPC_CheckPredicate, 0, 49, 140, // Skip to: 40641 +/* 4752 */ MCD_OPC_CheckField, 31, 1, 0, 43, 140, // Skip to: 40641 +/* 4758 */ MCD_OPC_CheckField, 10, 1, 0, 37, 140, // Skip to: 40641 +/* 4764 */ MCD_OPC_Decode, 177, 14, 31, // Opcode: ST4i16 +/* 4768 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 4818 +/* 4773 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 4776 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4794 +/* 4780 */ MCD_OPC_CheckPredicate, 0, 17, 140, // Skip to: 40641 +/* 4784 */ MCD_OPC_CheckField, 31, 1, 0, 11, 140, // Skip to: 40641 +/* 4790 */ MCD_OPC_Decode, 135, 14, 32, // Opcode: ST2i32 +/* 4794 */ MCD_OPC_FilterValue, 1, 3, 140, // Skip to: 40641 +/* 4798 */ MCD_OPC_CheckPredicate, 0, 255, 139, // Skip to: 40641 +/* 4802 */ MCD_OPC_CheckField, 31, 1, 0, 249, 139, // Skip to: 40641 +/* 4808 */ MCD_OPC_CheckField, 12, 1, 0, 243, 139, // Skip to: 40641 +/* 4814 */ MCD_OPC_Decode, 137, 14, 33, // Opcode: ST2i64 +/* 4818 */ MCD_OPC_FilterValue, 133, 2, 234, 139, // Skip to: 40641 +/* 4823 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 4826 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4844 +/* 4830 */ MCD_OPC_CheckPredicate, 0, 223, 139, // Skip to: 40641 +/* 4834 */ MCD_OPC_CheckField, 31, 1, 0, 217, 139, // Skip to: 40641 +/* 4840 */ MCD_OPC_Decode, 179, 14, 34, // Opcode: ST4i32 +/* 4844 */ MCD_OPC_FilterValue, 1, 209, 139, // Skip to: 40641 +/* 4848 */ MCD_OPC_CheckPredicate, 0, 205, 139, // Skip to: 40641 +/* 4852 */ MCD_OPC_CheckField, 31, 1, 0, 199, 139, // Skip to: 40641 +/* 4858 */ MCD_OPC_CheckField, 12, 1, 0, 193, 139, // Skip to: 40641 +/* 4864 */ MCD_OPC_Decode, 181, 14, 35, // Opcode: ST4i64 +/* 4868 */ MCD_OPC_FilterValue, 1, 185, 139, // Skip to: 40641 +/* 4872 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 4875 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 4883 +/* 4879 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: STPSi +/* 4883 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 4891 +/* 4887 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: STPDi +/* 4891 */ MCD_OPC_FilterValue, 2, 162, 139, // Skip to: 40641 +/* 4895 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: STPQi +/* 4899 */ MCD_OPC_FilterValue, 5, 169, 3, // Skip to: 5840 +/* 4903 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 4906 */ MCD_OPC_FilterValue, 0, 131, 3, // Skip to: 5809 +/* 4910 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... +/* 4913 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4931 +/* 4917 */ MCD_OPC_CheckPredicate, 0, 136, 139, // Skip to: 40641 +/* 4921 */ MCD_OPC_CheckField, 31, 1, 0, 130, 139, // Skip to: 40641 +/* 4927 */ MCD_OPC_Decode, 177, 6, 36, // Opcode: LD1i8 +/* 4931 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4949 +/* 4935 */ MCD_OPC_CheckPredicate, 0, 118, 139, // Skip to: 40641 +/* 4939 */ MCD_OPC_CheckField, 31, 1, 0, 112, 139, // Skip to: 40641 +/* 4945 */ MCD_OPC_Decode, 253, 6, 37, // Opcode: LD3i8 +/* 4949 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4973 +/* 4953 */ MCD_OPC_CheckPredicate, 0, 100, 139, // Skip to: 40641 +/* 4957 */ MCD_OPC_CheckField, 31, 1, 0, 94, 139, // Skip to: 40641 +/* 4963 */ MCD_OPC_CheckField, 10, 1, 0, 88, 139, // Skip to: 40641 +/* 4969 */ MCD_OPC_Decode, 171, 6, 38, // Opcode: LD1i16 +/* 4973 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4997 +/* 4977 */ MCD_OPC_CheckPredicate, 0, 76, 139, // Skip to: 40641 +/* 4981 */ MCD_OPC_CheckField, 31, 1, 0, 70, 139, // Skip to: 40641 +/* 4987 */ MCD_OPC_CheckField, 10, 1, 0, 64, 139, // Skip to: 40641 +/* 4993 */ MCD_OPC_Decode, 247, 6, 39, // Opcode: LD3i16 +/* 4997 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 5046 +/* 5001 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5004 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5022 +/* 5008 */ MCD_OPC_CheckPredicate, 0, 45, 139, // Skip to: 40641 +/* 5012 */ MCD_OPC_CheckField, 31, 1, 0, 39, 139, // Skip to: 40641 +/* 5018 */ MCD_OPC_Decode, 173, 6, 40, // Opcode: LD1i32 +/* 5022 */ MCD_OPC_FilterValue, 1, 31, 139, // Skip to: 40641 +/* 5026 */ MCD_OPC_CheckPredicate, 0, 27, 139, // Skip to: 40641 +/* 5030 */ MCD_OPC_CheckField, 31, 1, 0, 21, 139, // Skip to: 40641 +/* 5036 */ MCD_OPC_CheckField, 12, 1, 0, 15, 139, // Skip to: 40641 +/* 5042 */ MCD_OPC_Decode, 175, 6, 41, // Opcode: LD1i64 +/* 5046 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 5095 +/* 5050 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5053 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5071 +/* 5057 */ MCD_OPC_CheckPredicate, 0, 252, 138, // Skip to: 40641 +/* 5061 */ MCD_OPC_CheckField, 31, 1, 0, 246, 138, // Skip to: 40641 +/* 5067 */ MCD_OPC_Decode, 249, 6, 42, // Opcode: LD3i32 +/* 5071 */ MCD_OPC_FilterValue, 1, 238, 138, // Skip to: 40641 +/* 5075 */ MCD_OPC_CheckPredicate, 0, 234, 138, // Skip to: 40641 +/* 5079 */ MCD_OPC_CheckField, 31, 1, 0, 228, 138, // Skip to: 40641 +/* 5085 */ MCD_OPC_CheckField, 12, 1, 0, 222, 138, // Skip to: 40641 +/* 5091 */ MCD_OPC_Decode, 251, 6, 43, // Opcode: LD3i64 +/* 5095 */ MCD_OPC_FilterValue, 6, 127, 0, // Skip to: 5226 +/* 5099 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 5102 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5133 +/* 5106 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5109 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5121 +/* 5113 */ MCD_OPC_CheckPredicate, 0, 196, 138, // Skip to: 40641 +/* 5117 */ MCD_OPC_Decode, 135, 6, 6, // Opcode: LD1Rv8b +/* 5121 */ MCD_OPC_FilterValue, 1, 188, 138, // Skip to: 40641 +/* 5125 */ MCD_OPC_CheckPredicate, 0, 184, 138, // Skip to: 40641 +/* 5129 */ MCD_OPC_Decode, 251, 5, 10, // Opcode: LD1Rv16b +/* 5133 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5164 +/* 5137 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5140 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5152 +/* 5144 */ MCD_OPC_CheckPredicate, 0, 165, 138, // Skip to: 40641 +/* 5148 */ MCD_OPC_Decode, 131, 6, 6, // Opcode: LD1Rv4h +/* 5152 */ MCD_OPC_FilterValue, 1, 157, 138, // Skip to: 40641 +/* 5156 */ MCD_OPC_CheckPredicate, 0, 153, 138, // Skip to: 40641 +/* 5160 */ MCD_OPC_Decode, 137, 6, 10, // Opcode: LD1Rv8h +/* 5164 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5195 +/* 5168 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5183 +/* 5175 */ MCD_OPC_CheckPredicate, 0, 134, 138, // Skip to: 40641 +/* 5179 */ MCD_OPC_Decode, 129, 6, 6, // Opcode: LD1Rv2s +/* 5183 */ MCD_OPC_FilterValue, 1, 126, 138, // Skip to: 40641 +/* 5187 */ MCD_OPC_CheckPredicate, 0, 122, 138, // Skip to: 40641 +/* 5191 */ MCD_OPC_Decode, 133, 6, 10, // Opcode: LD1Rv4s +/* 5195 */ MCD_OPC_FilterValue, 3, 114, 138, // Skip to: 40641 +/* 5199 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5202 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5214 +/* 5206 */ MCD_OPC_CheckPredicate, 0, 103, 138, // Skip to: 40641 +/* 5210 */ MCD_OPC_Decode, 253, 5, 6, // Opcode: LD1Rv1d +/* 5214 */ MCD_OPC_FilterValue, 1, 95, 138, // Skip to: 40641 +/* 5218 */ MCD_OPC_CheckPredicate, 0, 91, 138, // Skip to: 40641 +/* 5222 */ MCD_OPC_Decode, 255, 5, 10, // Opcode: LD1Rv2d +/* 5226 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 5357 +/* 5230 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 5233 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5264 +/* 5237 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5240 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5252 +/* 5244 */ MCD_OPC_CheckPredicate, 0, 65, 138, // Skip to: 40641 +/* 5248 */ MCD_OPC_Decode, 229, 6, 5, // Opcode: LD3Rv8b +/* 5252 */ MCD_OPC_FilterValue, 1, 57, 138, // Skip to: 40641 +/* 5256 */ MCD_OPC_CheckPredicate, 0, 53, 138, // Skip to: 40641 +/* 5260 */ MCD_OPC_Decode, 217, 6, 9, // Opcode: LD3Rv16b +/* 5264 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5295 +/* 5268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5271 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5283 +/* 5275 */ MCD_OPC_CheckPredicate, 0, 34, 138, // Skip to: 40641 +/* 5279 */ MCD_OPC_Decode, 225, 6, 5, // Opcode: LD3Rv4h +/* 5283 */ MCD_OPC_FilterValue, 1, 26, 138, // Skip to: 40641 +/* 5287 */ MCD_OPC_CheckPredicate, 0, 22, 138, // Skip to: 40641 +/* 5291 */ MCD_OPC_Decode, 231, 6, 9, // Opcode: LD3Rv8h +/* 5295 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5326 +/* 5299 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5302 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5314 +/* 5306 */ MCD_OPC_CheckPredicate, 0, 3, 138, // Skip to: 40641 +/* 5310 */ MCD_OPC_Decode, 223, 6, 5, // Opcode: LD3Rv2s +/* 5314 */ MCD_OPC_FilterValue, 1, 251, 137, // Skip to: 40641 +/* 5318 */ MCD_OPC_CheckPredicate, 0, 247, 137, // Skip to: 40641 +/* 5322 */ MCD_OPC_Decode, 227, 6, 9, // Opcode: LD3Rv4s +/* 5326 */ MCD_OPC_FilterValue, 3, 239, 137, // Skip to: 40641 +/* 5330 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5345 +/* 5337 */ MCD_OPC_CheckPredicate, 0, 228, 137, // Skip to: 40641 +/* 5341 */ MCD_OPC_Decode, 219, 6, 5, // Opcode: LD3Rv1d +/* 5345 */ MCD_OPC_FilterValue, 1, 220, 137, // Skip to: 40641 +/* 5349 */ MCD_OPC_CheckPredicate, 0, 216, 137, // Skip to: 40641 +/* 5353 */ MCD_OPC_Decode, 221, 6, 9, // Opcode: LD3Rv2d +/* 5357 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 5376 +/* 5362 */ MCD_OPC_CheckPredicate, 0, 203, 137, // Skip to: 40641 +/* 5366 */ MCD_OPC_CheckField, 31, 1, 0, 197, 137, // Skip to: 40641 +/* 5372 */ MCD_OPC_Decode, 215, 6, 44, // Opcode: LD2i8 +/* 5376 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 5395 +/* 5381 */ MCD_OPC_CheckPredicate, 0, 184, 137, // Skip to: 40641 +/* 5385 */ MCD_OPC_CheckField, 31, 1, 0, 178, 137, // Skip to: 40641 +/* 5391 */ MCD_OPC_Decode, 163, 7, 45, // Opcode: LD4i8 +/* 5395 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 5420 +/* 5400 */ MCD_OPC_CheckPredicate, 0, 165, 137, // Skip to: 40641 +/* 5404 */ MCD_OPC_CheckField, 31, 1, 0, 159, 137, // Skip to: 40641 +/* 5410 */ MCD_OPC_CheckField, 10, 1, 0, 153, 137, // Skip to: 40641 +/* 5416 */ MCD_OPC_Decode, 209, 6, 46, // Opcode: LD2i16 +/* 5420 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 5445 +/* 5425 */ MCD_OPC_CheckPredicate, 0, 140, 137, // Skip to: 40641 +/* 5429 */ MCD_OPC_CheckField, 31, 1, 0, 134, 137, // Skip to: 40641 +/* 5435 */ MCD_OPC_CheckField, 10, 1, 0, 128, 137, // Skip to: 40641 +/* 5441 */ MCD_OPC_Decode, 157, 7, 47, // Opcode: LD4i16 +/* 5445 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 5495 +/* 5450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5453 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5471 +/* 5457 */ MCD_OPC_CheckPredicate, 0, 108, 137, // Skip to: 40641 +/* 5461 */ MCD_OPC_CheckField, 31, 1, 0, 102, 137, // Skip to: 40641 +/* 5467 */ MCD_OPC_Decode, 211, 6, 48, // Opcode: LD2i32 +/* 5471 */ MCD_OPC_FilterValue, 1, 94, 137, // Skip to: 40641 +/* 5475 */ MCD_OPC_CheckPredicate, 0, 90, 137, // Skip to: 40641 +/* 5479 */ MCD_OPC_CheckField, 31, 1, 0, 84, 137, // Skip to: 40641 +/* 5485 */ MCD_OPC_CheckField, 12, 1, 0, 78, 137, // Skip to: 40641 +/* 5491 */ MCD_OPC_Decode, 213, 6, 49, // Opcode: LD2i64 +/* 5495 */ MCD_OPC_FilterValue, 133, 2, 45, 0, // Skip to: 5545 +/* 5500 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5503 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5521 +/* 5507 */ MCD_OPC_CheckPredicate, 0, 58, 137, // Skip to: 40641 +/* 5511 */ MCD_OPC_CheckField, 31, 1, 0, 52, 137, // Skip to: 40641 +/* 5517 */ MCD_OPC_Decode, 159, 7, 50, // Opcode: LD4i32 +/* 5521 */ MCD_OPC_FilterValue, 1, 44, 137, // Skip to: 40641 +/* 5525 */ MCD_OPC_CheckPredicate, 0, 40, 137, // Skip to: 40641 +/* 5529 */ MCD_OPC_CheckField, 31, 1, 0, 34, 137, // Skip to: 40641 +/* 5535 */ MCD_OPC_CheckField, 12, 1, 0, 28, 137, // Skip to: 40641 +/* 5541 */ MCD_OPC_Decode, 161, 7, 51, // Opcode: LD4i64 +/* 5545 */ MCD_OPC_FilterValue, 134, 2, 127, 0, // Skip to: 5677 +/* 5550 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 5553 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5584 +/* 5557 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5560 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5572 +/* 5564 */ MCD_OPC_CheckPredicate, 0, 1, 137, // Skip to: 40641 +/* 5568 */ MCD_OPC_Decode, 191, 6, 7, // Opcode: LD2Rv8b +/* 5572 */ MCD_OPC_FilterValue, 1, 249, 136, // Skip to: 40641 +/* 5576 */ MCD_OPC_CheckPredicate, 0, 245, 136, // Skip to: 40641 +/* 5580 */ MCD_OPC_Decode, 179, 6, 11, // Opcode: LD2Rv16b +/* 5584 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5615 +/* 5588 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5591 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5603 +/* 5595 */ MCD_OPC_CheckPredicate, 0, 226, 136, // Skip to: 40641 +/* 5599 */ MCD_OPC_Decode, 187, 6, 7, // Opcode: LD2Rv4h +/* 5603 */ MCD_OPC_FilterValue, 1, 218, 136, // Skip to: 40641 +/* 5607 */ MCD_OPC_CheckPredicate, 0, 214, 136, // Skip to: 40641 +/* 5611 */ MCD_OPC_Decode, 193, 6, 11, // Opcode: LD2Rv8h +/* 5615 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5646 +/* 5619 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5622 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5634 +/* 5626 */ MCD_OPC_CheckPredicate, 0, 195, 136, // Skip to: 40641 +/* 5630 */ MCD_OPC_Decode, 185, 6, 7, // Opcode: LD2Rv2s +/* 5634 */ MCD_OPC_FilterValue, 1, 187, 136, // Skip to: 40641 +/* 5638 */ MCD_OPC_CheckPredicate, 0, 183, 136, // Skip to: 40641 +/* 5642 */ MCD_OPC_Decode, 189, 6, 11, // Opcode: LD2Rv4s +/* 5646 */ MCD_OPC_FilterValue, 3, 175, 136, // Skip to: 40641 +/* 5650 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5653 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5665 +/* 5657 */ MCD_OPC_CheckPredicate, 0, 164, 136, // Skip to: 40641 +/* 5661 */ MCD_OPC_Decode, 181, 6, 7, // Opcode: LD2Rv1d +/* 5665 */ MCD_OPC_FilterValue, 1, 156, 136, // Skip to: 40641 +/* 5669 */ MCD_OPC_CheckPredicate, 0, 152, 136, // Skip to: 40641 +/* 5673 */ MCD_OPC_Decode, 183, 6, 11, // Opcode: LD2Rv2d +/* 5677 */ MCD_OPC_FilterValue, 135, 2, 143, 136, // Skip to: 40641 +/* 5682 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 5685 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5716 +/* 5689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5692 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5704 +/* 5696 */ MCD_OPC_CheckPredicate, 0, 125, 136, // Skip to: 40641 +/* 5700 */ MCD_OPC_Decode, 153, 7, 4, // Opcode: LD4Rv8b +/* 5704 */ MCD_OPC_FilterValue, 1, 117, 136, // Skip to: 40641 +/* 5708 */ MCD_OPC_CheckPredicate, 0, 113, 136, // Skip to: 40641 +/* 5712 */ MCD_OPC_Decode, 141, 7, 8, // Opcode: LD4Rv16b +/* 5716 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5747 +/* 5720 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5723 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5735 +/* 5727 */ MCD_OPC_CheckPredicate, 0, 94, 136, // Skip to: 40641 +/* 5731 */ MCD_OPC_Decode, 149, 7, 4, // Opcode: LD4Rv4h +/* 5735 */ MCD_OPC_FilterValue, 1, 86, 136, // Skip to: 40641 +/* 5739 */ MCD_OPC_CheckPredicate, 0, 82, 136, // Skip to: 40641 +/* 5743 */ MCD_OPC_Decode, 155, 7, 8, // Opcode: LD4Rv8h +/* 5747 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5778 +/* 5751 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5754 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5766 +/* 5758 */ MCD_OPC_CheckPredicate, 0, 63, 136, // Skip to: 40641 +/* 5762 */ MCD_OPC_Decode, 147, 7, 4, // Opcode: LD4Rv2s +/* 5766 */ MCD_OPC_FilterValue, 1, 55, 136, // Skip to: 40641 +/* 5770 */ MCD_OPC_CheckPredicate, 0, 51, 136, // Skip to: 40641 +/* 5774 */ MCD_OPC_Decode, 151, 7, 8, // Opcode: LD4Rv4s +/* 5778 */ MCD_OPC_FilterValue, 3, 43, 136, // Skip to: 40641 +/* 5782 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5785 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5797 +/* 5789 */ MCD_OPC_CheckPredicate, 0, 32, 136, // Skip to: 40641 +/* 5793 */ MCD_OPC_Decode, 143, 7, 4, // Opcode: LD4Rv1d +/* 5797 */ MCD_OPC_FilterValue, 1, 24, 136, // Skip to: 40641 +/* 5801 */ MCD_OPC_CheckPredicate, 0, 20, 136, // Skip to: 40641 +/* 5805 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: LD4Rv2d +/* 5809 */ MCD_OPC_FilterValue, 1, 12, 136, // Skip to: 40641 +/* 5813 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 5816 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5824 +/* 5820 */ MCD_OPC_Decode, 189, 7, 3, // Opcode: LDPSi +/* 5824 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 5832 +/* 5828 */ MCD_OPC_Decode, 180, 7, 3, // Opcode: LDPDi +/* 5832 */ MCD_OPC_FilterValue, 2, 245, 135, // Skip to: 40641 +/* 5836 */ MCD_OPC_Decode, 183, 7, 3, // Opcode: LDPQi +/* 5840 */ MCD_OPC_FilterValue, 6, 191, 1, // Skip to: 6291 +/* 5844 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 5847 */ MCD_OPC_FilterValue, 0, 153, 1, // Skip to: 6260 +/* 5851 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 5854 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5897 +/* 5858 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5861 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5879 +/* 5865 */ MCD_OPC_CheckPredicate, 0, 212, 135, // Skip to: 40641 +/* 5869 */ MCD_OPC_CheckField, 31, 1, 0, 206, 135, // Skip to: 40641 +/* 5875 */ MCD_OPC_Decode, 246, 13, 52, // Opcode: ST1i8_POST +/* 5879 */ MCD_OPC_FilterValue, 1, 198, 135, // Skip to: 40641 +/* 5883 */ MCD_OPC_CheckPredicate, 0, 194, 135, // Skip to: 40641 +/* 5887 */ MCD_OPC_CheckField, 31, 1, 0, 188, 135, // Skip to: 40641 +/* 5893 */ MCD_OPC_Decode, 140, 14, 53, // Opcode: ST2i8_POST +/* 5897 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 5940 +/* 5901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5904 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5922 +/* 5908 */ MCD_OPC_CheckPredicate, 0, 169, 135, // Skip to: 40641 +/* 5912 */ MCD_OPC_CheckField, 31, 1, 0, 163, 135, // Skip to: 40641 +/* 5918 */ MCD_OPC_Decode, 162, 14, 54, // Opcode: ST3i8_POST +/* 5922 */ MCD_OPC_FilterValue, 1, 155, 135, // Skip to: 40641 +/* 5926 */ MCD_OPC_CheckPredicate, 0, 151, 135, // Skip to: 40641 +/* 5930 */ MCD_OPC_CheckField, 31, 1, 0, 145, 135, // Skip to: 40641 +/* 5936 */ MCD_OPC_Decode, 184, 14, 55, // Opcode: ST4i8_POST +/* 5940 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 5995 +/* 5944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5947 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5971 +/* 5951 */ MCD_OPC_CheckPredicate, 0, 126, 135, // Skip to: 40641 +/* 5955 */ MCD_OPC_CheckField, 31, 1, 0, 120, 135, // Skip to: 40641 +/* 5961 */ MCD_OPC_CheckField, 10, 1, 0, 114, 135, // Skip to: 40641 +/* 5967 */ MCD_OPC_Decode, 240, 13, 56, // Opcode: ST1i16_POST +/* 5971 */ MCD_OPC_FilterValue, 1, 106, 135, // Skip to: 40641 +/* 5975 */ MCD_OPC_CheckPredicate, 0, 102, 135, // Skip to: 40641 +/* 5979 */ MCD_OPC_CheckField, 31, 1, 0, 96, 135, // Skip to: 40641 +/* 5985 */ MCD_OPC_CheckField, 10, 1, 0, 90, 135, // Skip to: 40641 +/* 5991 */ MCD_OPC_Decode, 134, 14, 57, // Opcode: ST2i16_POST +/* 5995 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6050 +/* 5999 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6002 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6026 +/* 6006 */ MCD_OPC_CheckPredicate, 0, 71, 135, // Skip to: 40641 +/* 6010 */ MCD_OPC_CheckField, 31, 1, 0, 65, 135, // Skip to: 40641 +/* 6016 */ MCD_OPC_CheckField, 10, 1, 0, 59, 135, // Skip to: 40641 +/* 6022 */ MCD_OPC_Decode, 156, 14, 58, // Opcode: ST3i16_POST +/* 6026 */ MCD_OPC_FilterValue, 1, 51, 135, // Skip to: 40641 +/* 6030 */ MCD_OPC_CheckPredicate, 0, 47, 135, // Skip to: 40641 +/* 6034 */ MCD_OPC_CheckField, 31, 1, 0, 41, 135, // Skip to: 40641 +/* 6040 */ MCD_OPC_CheckField, 10, 1, 0, 35, 135, // Skip to: 40641 +/* 6046 */ MCD_OPC_Decode, 178, 14, 59, // Opcode: ST4i16_POST +/* 6050 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6155 +/* 6054 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6057 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6100 +/* 6061 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6064 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6082 +/* 6068 */ MCD_OPC_CheckPredicate, 0, 9, 135, // Skip to: 40641 +/* 6072 */ MCD_OPC_CheckField, 31, 1, 0, 3, 135, // Skip to: 40641 +/* 6078 */ MCD_OPC_Decode, 242, 13, 60, // Opcode: ST1i32_POST +/* 6082 */ MCD_OPC_FilterValue, 1, 251, 134, // Skip to: 40641 +/* 6086 */ MCD_OPC_CheckPredicate, 0, 247, 134, // Skip to: 40641 +/* 6090 */ MCD_OPC_CheckField, 31, 1, 0, 241, 134, // Skip to: 40641 +/* 6096 */ MCD_OPC_Decode, 136, 14, 61, // Opcode: ST2i32_POST +/* 6100 */ MCD_OPC_FilterValue, 1, 233, 134, // Skip to: 40641 +/* 6104 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6107 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6131 +/* 6111 */ MCD_OPC_CheckPredicate, 0, 222, 134, // Skip to: 40641 +/* 6115 */ MCD_OPC_CheckField, 31, 1, 0, 216, 134, // Skip to: 40641 +/* 6121 */ MCD_OPC_CheckField, 12, 1, 0, 210, 134, // Skip to: 40641 +/* 6127 */ MCD_OPC_Decode, 244, 13, 62, // Opcode: ST1i64_POST +/* 6131 */ MCD_OPC_FilterValue, 1, 202, 134, // Skip to: 40641 +/* 6135 */ MCD_OPC_CheckPredicate, 0, 198, 134, // Skip to: 40641 +/* 6139 */ MCD_OPC_CheckField, 31, 1, 0, 192, 134, // Skip to: 40641 +/* 6145 */ MCD_OPC_CheckField, 12, 1, 0, 186, 134, // Skip to: 40641 +/* 6151 */ MCD_OPC_Decode, 138, 14, 63, // Opcode: ST2i64_POST +/* 6155 */ MCD_OPC_FilterValue, 5, 178, 134, // Skip to: 40641 +/* 6159 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6162 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6205 +/* 6166 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6169 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6187 +/* 6173 */ MCD_OPC_CheckPredicate, 0, 160, 134, // Skip to: 40641 +/* 6177 */ MCD_OPC_CheckField, 31, 1, 0, 154, 134, // Skip to: 40641 +/* 6183 */ MCD_OPC_Decode, 158, 14, 64, // Opcode: ST3i32_POST +/* 6187 */ MCD_OPC_FilterValue, 1, 146, 134, // Skip to: 40641 +/* 6191 */ MCD_OPC_CheckPredicate, 0, 142, 134, // Skip to: 40641 +/* 6195 */ MCD_OPC_CheckField, 31, 1, 0, 136, 134, // Skip to: 40641 +/* 6201 */ MCD_OPC_Decode, 180, 14, 65, // Opcode: ST4i32_POST +/* 6205 */ MCD_OPC_FilterValue, 1, 128, 134, // Skip to: 40641 +/* 6209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6212 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6236 +/* 6216 */ MCD_OPC_CheckPredicate, 0, 117, 134, // Skip to: 40641 +/* 6220 */ MCD_OPC_CheckField, 31, 1, 0, 111, 134, // Skip to: 40641 +/* 6226 */ MCD_OPC_CheckField, 12, 1, 0, 105, 134, // Skip to: 40641 +/* 6232 */ MCD_OPC_Decode, 160, 14, 66, // Opcode: ST3i64_POST +/* 6236 */ MCD_OPC_FilterValue, 1, 97, 134, // Skip to: 40641 +/* 6240 */ MCD_OPC_CheckPredicate, 0, 93, 134, // Skip to: 40641 +/* 6244 */ MCD_OPC_CheckField, 31, 1, 0, 87, 134, // Skip to: 40641 +/* 6250 */ MCD_OPC_CheckField, 12, 1, 0, 81, 134, // Skip to: 40641 +/* 6256 */ MCD_OPC_Decode, 182, 14, 67, // Opcode: ST4i64_POST +/* 6260 */ MCD_OPC_FilterValue, 1, 73, 134, // Skip to: 40641 +/* 6264 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6267 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6275 +/* 6271 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: STPSpre +/* 6275 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 6283 +/* 6279 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: STPDpre +/* 6283 */ MCD_OPC_FilterValue, 2, 50, 134, // Skip to: 40641 +/* 6287 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: STPQpre +/* 6291 */ MCD_OPC_FilterValue, 7, 245, 3, // Skip to: 7308 +/* 6295 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 6298 */ MCD_OPC_FilterValue, 0, 207, 3, // Skip to: 7277 +/* 6302 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 6305 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6348 +/* 6309 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6312 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6330 +/* 6316 */ MCD_OPC_CheckPredicate, 0, 17, 134, // Skip to: 40641 +/* 6320 */ MCD_OPC_CheckField, 31, 1, 0, 11, 134, // Skip to: 40641 +/* 6326 */ MCD_OPC_Decode, 178, 6, 68, // Opcode: LD1i8_POST +/* 6330 */ MCD_OPC_FilterValue, 1, 3, 134, // Skip to: 40641 +/* 6334 */ MCD_OPC_CheckPredicate, 0, 255, 133, // Skip to: 40641 +/* 6338 */ MCD_OPC_CheckField, 31, 1, 0, 249, 133, // Skip to: 40641 +/* 6344 */ MCD_OPC_Decode, 216, 6, 69, // Opcode: LD2i8_POST +/* 6348 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 6391 +/* 6352 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6355 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6373 +/* 6359 */ MCD_OPC_CheckPredicate, 0, 230, 133, // Skip to: 40641 +/* 6363 */ MCD_OPC_CheckField, 31, 1, 0, 224, 133, // Skip to: 40641 +/* 6369 */ MCD_OPC_Decode, 254, 6, 70, // Opcode: LD3i8_POST +/* 6373 */ MCD_OPC_FilterValue, 1, 216, 133, // Skip to: 40641 +/* 6377 */ MCD_OPC_CheckPredicate, 0, 212, 133, // Skip to: 40641 +/* 6381 */ MCD_OPC_CheckField, 31, 1, 0, 206, 133, // Skip to: 40641 +/* 6387 */ MCD_OPC_Decode, 164, 7, 71, // Opcode: LD4i8_POST +/* 6391 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6446 +/* 6395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6398 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6422 +/* 6402 */ MCD_OPC_CheckPredicate, 0, 187, 133, // Skip to: 40641 +/* 6406 */ MCD_OPC_CheckField, 31, 1, 0, 181, 133, // Skip to: 40641 +/* 6412 */ MCD_OPC_CheckField, 10, 1, 0, 175, 133, // Skip to: 40641 +/* 6418 */ MCD_OPC_Decode, 172, 6, 72, // Opcode: LD1i16_POST +/* 6422 */ MCD_OPC_FilterValue, 1, 167, 133, // Skip to: 40641 +/* 6426 */ MCD_OPC_CheckPredicate, 0, 163, 133, // Skip to: 40641 +/* 6430 */ MCD_OPC_CheckField, 31, 1, 0, 157, 133, // Skip to: 40641 +/* 6436 */ MCD_OPC_CheckField, 10, 1, 0, 151, 133, // Skip to: 40641 +/* 6442 */ MCD_OPC_Decode, 210, 6, 73, // Opcode: LD2i16_POST +/* 6446 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6501 +/* 6450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6453 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6477 +/* 6457 */ MCD_OPC_CheckPredicate, 0, 132, 133, // Skip to: 40641 +/* 6461 */ MCD_OPC_CheckField, 31, 1, 0, 126, 133, // Skip to: 40641 +/* 6467 */ MCD_OPC_CheckField, 10, 1, 0, 120, 133, // Skip to: 40641 +/* 6473 */ MCD_OPC_Decode, 248, 6, 74, // Opcode: LD3i16_POST +/* 6477 */ MCD_OPC_FilterValue, 1, 112, 133, // Skip to: 40641 +/* 6481 */ MCD_OPC_CheckPredicate, 0, 108, 133, // Skip to: 40641 +/* 6485 */ MCD_OPC_CheckField, 31, 1, 0, 102, 133, // Skip to: 40641 +/* 6491 */ MCD_OPC_CheckField, 10, 1, 0, 96, 133, // Skip to: 40641 +/* 6497 */ MCD_OPC_Decode, 158, 7, 75, // Opcode: LD4i16_POST +/* 6501 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6606 +/* 6505 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6508 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6551 +/* 6512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6515 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6533 +/* 6519 */ MCD_OPC_CheckPredicate, 0, 70, 133, // Skip to: 40641 +/* 6523 */ MCD_OPC_CheckField, 31, 1, 0, 64, 133, // Skip to: 40641 +/* 6529 */ MCD_OPC_Decode, 174, 6, 76, // Opcode: LD1i32_POST +/* 6533 */ MCD_OPC_FilterValue, 1, 56, 133, // Skip to: 40641 +/* 6537 */ MCD_OPC_CheckPredicate, 0, 52, 133, // Skip to: 40641 +/* 6541 */ MCD_OPC_CheckField, 31, 1, 0, 46, 133, // Skip to: 40641 +/* 6547 */ MCD_OPC_Decode, 212, 6, 77, // Opcode: LD2i32_POST +/* 6551 */ MCD_OPC_FilterValue, 1, 38, 133, // Skip to: 40641 +/* 6555 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6558 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6582 +/* 6562 */ MCD_OPC_CheckPredicate, 0, 27, 133, // Skip to: 40641 +/* 6566 */ MCD_OPC_CheckField, 31, 1, 0, 21, 133, // Skip to: 40641 +/* 6572 */ MCD_OPC_CheckField, 12, 1, 0, 15, 133, // Skip to: 40641 +/* 6578 */ MCD_OPC_Decode, 176, 6, 78, // Opcode: LD1i64_POST +/* 6582 */ MCD_OPC_FilterValue, 1, 7, 133, // Skip to: 40641 +/* 6586 */ MCD_OPC_CheckPredicate, 0, 3, 133, // Skip to: 40641 +/* 6590 */ MCD_OPC_CheckField, 31, 1, 0, 253, 132, // Skip to: 40641 +/* 6596 */ MCD_OPC_CheckField, 12, 1, 0, 247, 132, // Skip to: 40641 +/* 6602 */ MCD_OPC_Decode, 214, 6, 79, // Opcode: LD2i64_POST +/* 6606 */ MCD_OPC_FilterValue, 5, 101, 0, // Skip to: 6711 +/* 6610 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6613 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6656 +/* 6617 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6620 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6638 +/* 6624 */ MCD_OPC_CheckPredicate, 0, 221, 132, // Skip to: 40641 +/* 6628 */ MCD_OPC_CheckField, 31, 1, 0, 215, 132, // Skip to: 40641 +/* 6634 */ MCD_OPC_Decode, 250, 6, 80, // Opcode: LD3i32_POST +/* 6638 */ MCD_OPC_FilterValue, 1, 207, 132, // Skip to: 40641 +/* 6642 */ MCD_OPC_CheckPredicate, 0, 203, 132, // Skip to: 40641 +/* 6646 */ MCD_OPC_CheckField, 31, 1, 0, 197, 132, // Skip to: 40641 +/* 6652 */ MCD_OPC_Decode, 160, 7, 81, // Opcode: LD4i32_POST +/* 6656 */ MCD_OPC_FilterValue, 1, 189, 132, // Skip to: 40641 +/* 6660 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6663 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6687 +/* 6667 */ MCD_OPC_CheckPredicate, 0, 178, 132, // Skip to: 40641 +/* 6671 */ MCD_OPC_CheckField, 31, 1, 0, 172, 132, // Skip to: 40641 +/* 6677 */ MCD_OPC_CheckField, 12, 1, 0, 166, 132, // Skip to: 40641 +/* 6683 */ MCD_OPC_Decode, 252, 6, 82, // Opcode: LD3i64_POST +/* 6687 */ MCD_OPC_FilterValue, 1, 158, 132, // Skip to: 40641 +/* 6691 */ MCD_OPC_CheckPredicate, 0, 154, 132, // Skip to: 40641 +/* 6695 */ MCD_OPC_CheckField, 31, 1, 0, 148, 132, // Skip to: 40641 +/* 6701 */ MCD_OPC_CheckField, 12, 1, 0, 142, 132, // Skip to: 40641 +/* 6707 */ MCD_OPC_Decode, 162, 7, 83, // Opcode: LD4i64_POST +/* 6711 */ MCD_OPC_FilterValue, 6, 23, 1, // Skip to: 6994 +/* 6715 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 6718 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 6787 +/* 6722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6725 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6756 +/* 6729 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6732 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6744 +/* 6736 */ MCD_OPC_CheckPredicate, 0, 109, 132, // Skip to: 40641 +/* 6740 */ MCD_OPC_Decode, 136, 6, 14, // Opcode: LD1Rv8b_POST +/* 6744 */ MCD_OPC_FilterValue, 1, 101, 132, // Skip to: 40641 +/* 6748 */ MCD_OPC_CheckPredicate, 0, 97, 132, // Skip to: 40641 +/* 6752 */ MCD_OPC_Decode, 252, 5, 18, // Opcode: LD1Rv16b_POST +/* 6756 */ MCD_OPC_FilterValue, 1, 89, 132, // Skip to: 40641 +/* 6760 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6763 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6775 +/* 6767 */ MCD_OPC_CheckPredicate, 0, 78, 132, // Skip to: 40641 +/* 6771 */ MCD_OPC_Decode, 192, 6, 15, // Opcode: LD2Rv8b_POST +/* 6775 */ MCD_OPC_FilterValue, 1, 70, 132, // Skip to: 40641 +/* 6779 */ MCD_OPC_CheckPredicate, 0, 66, 132, // Skip to: 40641 +/* 6783 */ MCD_OPC_Decode, 180, 6, 19, // Opcode: LD2Rv16b_POST +/* 6787 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 6856 +/* 6791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6794 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6825 +/* 6798 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6801 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6813 +/* 6805 */ MCD_OPC_CheckPredicate, 0, 40, 132, // Skip to: 40641 +/* 6809 */ MCD_OPC_Decode, 132, 6, 14, // Opcode: LD1Rv4h_POST +/* 6813 */ MCD_OPC_FilterValue, 1, 32, 132, // Skip to: 40641 +/* 6817 */ MCD_OPC_CheckPredicate, 0, 28, 132, // Skip to: 40641 +/* 6821 */ MCD_OPC_Decode, 138, 6, 18, // Opcode: LD1Rv8h_POST +/* 6825 */ MCD_OPC_FilterValue, 1, 20, 132, // Skip to: 40641 +/* 6829 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6832 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6844 +/* 6836 */ MCD_OPC_CheckPredicate, 0, 9, 132, // Skip to: 40641 +/* 6840 */ MCD_OPC_Decode, 188, 6, 15, // Opcode: LD2Rv4h_POST +/* 6844 */ MCD_OPC_FilterValue, 1, 1, 132, // Skip to: 40641 +/* 6848 */ MCD_OPC_CheckPredicate, 0, 253, 131, // Skip to: 40641 +/* 6852 */ MCD_OPC_Decode, 194, 6, 19, // Opcode: LD2Rv8h_POST +/* 6856 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 6925 +/* 6860 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6863 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6894 +/* 6867 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6882 +/* 6874 */ MCD_OPC_CheckPredicate, 0, 227, 131, // Skip to: 40641 +/* 6878 */ MCD_OPC_Decode, 130, 6, 14, // Opcode: LD1Rv2s_POST +/* 6882 */ MCD_OPC_FilterValue, 1, 219, 131, // Skip to: 40641 +/* 6886 */ MCD_OPC_CheckPredicate, 0, 215, 131, // Skip to: 40641 +/* 6890 */ MCD_OPC_Decode, 134, 6, 18, // Opcode: LD1Rv4s_POST +/* 6894 */ MCD_OPC_FilterValue, 1, 207, 131, // Skip to: 40641 +/* 6898 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6901 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6913 +/* 6905 */ MCD_OPC_CheckPredicate, 0, 196, 131, // Skip to: 40641 +/* 6909 */ MCD_OPC_Decode, 186, 6, 15, // Opcode: LD2Rv2s_POST +/* 6913 */ MCD_OPC_FilterValue, 1, 188, 131, // Skip to: 40641 +/* 6917 */ MCD_OPC_CheckPredicate, 0, 184, 131, // Skip to: 40641 +/* 6921 */ MCD_OPC_Decode, 190, 6, 19, // Opcode: LD2Rv4s_POST +/* 6925 */ MCD_OPC_FilterValue, 3, 176, 131, // Skip to: 40641 +/* 6929 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 6932 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6963 +/* 6936 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6939 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6951 +/* 6943 */ MCD_OPC_CheckPredicate, 0, 158, 131, // Skip to: 40641 +/* 6947 */ MCD_OPC_Decode, 254, 5, 14, // Opcode: LD1Rv1d_POST +/* 6951 */ MCD_OPC_FilterValue, 1, 150, 131, // Skip to: 40641 +/* 6955 */ MCD_OPC_CheckPredicate, 0, 146, 131, // Skip to: 40641 +/* 6959 */ MCD_OPC_Decode, 128, 6, 18, // Opcode: LD1Rv2d_POST +/* 6963 */ MCD_OPC_FilterValue, 1, 138, 131, // Skip to: 40641 +/* 6967 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 6970 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6982 +/* 6974 */ MCD_OPC_CheckPredicate, 0, 127, 131, // Skip to: 40641 +/* 6978 */ MCD_OPC_Decode, 182, 6, 15, // Opcode: LD2Rv1d_POST +/* 6982 */ MCD_OPC_FilterValue, 1, 119, 131, // Skip to: 40641 +/* 6986 */ MCD_OPC_CheckPredicate, 0, 115, 131, // Skip to: 40641 +/* 6990 */ MCD_OPC_Decode, 184, 6, 19, // Opcode: LD2Rv2d_POST +/* 6994 */ MCD_OPC_FilterValue, 7, 107, 131, // Skip to: 40641 +/* 6998 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 7001 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 7070 +/* 7005 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7008 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7039 +/* 7012 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7015 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7027 +/* 7019 */ MCD_OPC_CheckPredicate, 0, 82, 131, // Skip to: 40641 +/* 7023 */ MCD_OPC_Decode, 230, 6, 13, // Opcode: LD3Rv8b_POST +/* 7027 */ MCD_OPC_FilterValue, 1, 74, 131, // Skip to: 40641 +/* 7031 */ MCD_OPC_CheckPredicate, 0, 70, 131, // Skip to: 40641 +/* 7035 */ MCD_OPC_Decode, 218, 6, 17, // Opcode: LD3Rv16b_POST +/* 7039 */ MCD_OPC_FilterValue, 1, 62, 131, // Skip to: 40641 +/* 7043 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7046 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7058 +/* 7050 */ MCD_OPC_CheckPredicate, 0, 51, 131, // Skip to: 40641 +/* 7054 */ MCD_OPC_Decode, 154, 7, 12, // Opcode: LD4Rv8b_POST +/* 7058 */ MCD_OPC_FilterValue, 1, 43, 131, // Skip to: 40641 +/* 7062 */ MCD_OPC_CheckPredicate, 0, 39, 131, // Skip to: 40641 +/* 7066 */ MCD_OPC_Decode, 142, 7, 16, // Opcode: LD4Rv16b_POST +/* 7070 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 7139 +/* 7074 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7077 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7108 +/* 7081 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7084 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7096 +/* 7088 */ MCD_OPC_CheckPredicate, 0, 13, 131, // Skip to: 40641 +/* 7092 */ MCD_OPC_Decode, 226, 6, 13, // Opcode: LD3Rv4h_POST +/* 7096 */ MCD_OPC_FilterValue, 1, 5, 131, // Skip to: 40641 +/* 7100 */ MCD_OPC_CheckPredicate, 0, 1, 131, // Skip to: 40641 +/* 7104 */ MCD_OPC_Decode, 232, 6, 17, // Opcode: LD3Rv8h_POST +/* 7108 */ MCD_OPC_FilterValue, 1, 249, 130, // Skip to: 40641 +/* 7112 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7115 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7127 +/* 7119 */ MCD_OPC_CheckPredicate, 0, 238, 130, // Skip to: 40641 +/* 7123 */ MCD_OPC_Decode, 150, 7, 12, // Opcode: LD4Rv4h_POST +/* 7127 */ MCD_OPC_FilterValue, 1, 230, 130, // Skip to: 40641 +/* 7131 */ MCD_OPC_CheckPredicate, 0, 226, 130, // Skip to: 40641 +/* 7135 */ MCD_OPC_Decode, 156, 7, 16, // Opcode: LD4Rv8h_POST +/* 7139 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 7208 +/* 7143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7146 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7177 +/* 7150 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7165 +/* 7157 */ MCD_OPC_CheckPredicate, 0, 200, 130, // Skip to: 40641 +/* 7161 */ MCD_OPC_Decode, 224, 6, 13, // Opcode: LD3Rv2s_POST +/* 7165 */ MCD_OPC_FilterValue, 1, 192, 130, // Skip to: 40641 +/* 7169 */ MCD_OPC_CheckPredicate, 0, 188, 130, // Skip to: 40641 +/* 7173 */ MCD_OPC_Decode, 228, 6, 17, // Opcode: LD3Rv4s_POST +/* 7177 */ MCD_OPC_FilterValue, 1, 180, 130, // Skip to: 40641 +/* 7181 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7184 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7196 +/* 7188 */ MCD_OPC_CheckPredicate, 0, 169, 130, // Skip to: 40641 +/* 7192 */ MCD_OPC_Decode, 148, 7, 12, // Opcode: LD4Rv2s_POST +/* 7196 */ MCD_OPC_FilterValue, 1, 161, 130, // Skip to: 40641 +/* 7200 */ MCD_OPC_CheckPredicate, 0, 157, 130, // Skip to: 40641 +/* 7204 */ MCD_OPC_Decode, 152, 7, 16, // Opcode: LD4Rv4s_POST +/* 7208 */ MCD_OPC_FilterValue, 3, 149, 130, // Skip to: 40641 +/* 7212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7215 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7246 +/* 7219 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7222 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7234 +/* 7226 */ MCD_OPC_CheckPredicate, 0, 131, 130, // Skip to: 40641 +/* 7230 */ MCD_OPC_Decode, 220, 6, 13, // Opcode: LD3Rv1d_POST +/* 7234 */ MCD_OPC_FilterValue, 1, 123, 130, // Skip to: 40641 +/* 7238 */ MCD_OPC_CheckPredicate, 0, 119, 130, // Skip to: 40641 +/* 7242 */ MCD_OPC_Decode, 222, 6, 17, // Opcode: LD3Rv2d_POST +/* 7246 */ MCD_OPC_FilterValue, 1, 111, 130, // Skip to: 40641 +/* 7250 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7253 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7265 +/* 7257 */ MCD_OPC_CheckPredicate, 0, 100, 130, // Skip to: 40641 +/* 7261 */ MCD_OPC_Decode, 144, 7, 12, // Opcode: LD4Rv1d_POST +/* 7265 */ MCD_OPC_FilterValue, 1, 92, 130, // Skip to: 40641 +/* 7269 */ MCD_OPC_CheckPredicate, 0, 88, 130, // Skip to: 40641 +/* 7273 */ MCD_OPC_Decode, 146, 7, 16, // Opcode: LD4Rv2d_POST +/* 7277 */ MCD_OPC_FilterValue, 1, 80, 130, // Skip to: 40641 +/* 7281 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 7284 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7292 +/* 7288 */ MCD_OPC_Decode, 191, 7, 3, // Opcode: LDPSpre +/* 7292 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 7300 +/* 7296 */ MCD_OPC_Decode, 182, 7, 3, // Opcode: LDPDpre +/* 7300 */ MCD_OPC_FilterValue, 2, 57, 130, // Skip to: 40641 +/* 7304 */ MCD_OPC_Decode, 185, 7, 3, // Opcode: LDPQpre +/* 7308 */ MCD_OPC_FilterValue, 8, 171, 21, // Skip to: 12859 +/* 7312 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 7315 */ MCD_OPC_FilterValue, 0, 36, 6, // Skip to: 8891 +/* 7319 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 7322 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7353 +/* 7326 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7329 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7341 +/* 7333 */ MCD_OPC_CheckPredicate, 0, 24, 130, // Skip to: 40641 +/* 7337 */ MCD_OPC_Decode, 202, 15, 84, // Opcode: TBLv8i8One +/* 7341 */ MCD_OPC_FilterValue, 1, 16, 130, // Skip to: 40641 +/* 7345 */ MCD_OPC_CheckPredicate, 0, 12, 130, // Skip to: 40641 +/* 7349 */ MCD_OPC_Decode, 247, 9, 85, // Opcode: SADDLv8i8_v8i16 +/* 7353 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 7428 +/* 7357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7360 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7416 +/* 7364 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 7367 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7404 +/* 7371 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 7374 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7392 +/* 7378 */ MCD_OPC_CheckPredicate, 0, 235, 129, // Skip to: 40641 +/* 7382 */ MCD_OPC_CheckField, 18, 1, 1, 229, 129, // Skip to: 40641 +/* 7388 */ MCD_OPC_Decode, 151, 2, 86, // Opcode: DUPv2i32lane +/* 7392 */ MCD_OPC_FilterValue, 1, 221, 129, // Skip to: 40641 +/* 7396 */ MCD_OPC_CheckPredicate, 0, 217, 129, // Skip to: 40641 +/* 7400 */ MCD_OPC_Decode, 155, 2, 87, // Opcode: DUPv4i16lane +/* 7404 */ MCD_OPC_FilterValue, 1, 209, 129, // Skip to: 40641 +/* 7408 */ MCD_OPC_CheckPredicate, 0, 205, 129, // Skip to: 40641 +/* 7412 */ MCD_OPC_Decode, 161, 2, 88, // Opcode: DUPv8i8lane +/* 7416 */ MCD_OPC_FilterValue, 1, 197, 129, // Skip to: 40641 +/* 7420 */ MCD_OPC_CheckPredicate, 0, 193, 129, // Skip to: 40641 +/* 7424 */ MCD_OPC_Decode, 169, 10, 89, // Opcode: SHADDv8i8 +/* 7428 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7446 +/* 7432 */ MCD_OPC_CheckPredicate, 0, 181, 129, // Skip to: 40641 +/* 7436 */ MCD_OPC_CheckField, 16, 6, 32, 175, 129, // Skip to: 40641 +/* 7442 */ MCD_OPC_Decode, 184, 9, 90, // Opcode: REV64v8i8 +/* 7446 */ MCD_OPC_FilterValue, 3, 58, 0, // Skip to: 7508 +/* 7450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7453 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 7496 +/* 7457 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 7460 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7472 +/* 7464 */ MCD_OPC_CheckPredicate, 0, 149, 129, // Skip to: 40641 +/* 7468 */ MCD_OPC_Decode, 160, 2, 91, // Opcode: DUPv8i8gpr +/* 7472 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7484 +/* 7476 */ MCD_OPC_CheckPredicate, 0, 137, 129, // Skip to: 40641 +/* 7480 */ MCD_OPC_Decode, 154, 2, 91, // Opcode: DUPv4i16gpr +/* 7484 */ MCD_OPC_FilterValue, 4, 129, 129, // Skip to: 40641 +/* 7488 */ MCD_OPC_CheckPredicate, 0, 125, 129, // Skip to: 40641 +/* 7492 */ MCD_OPC_Decode, 150, 2, 91, // Opcode: DUPv2i32gpr +/* 7496 */ MCD_OPC_FilterValue, 1, 117, 129, // Skip to: 40641 +/* 7500 */ MCD_OPC_CheckPredicate, 0, 113, 129, // Skip to: 40641 +/* 7504 */ MCD_OPC_Decode, 170, 11, 89, // Opcode: SQADDv8i8 +/* 7508 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 7539 +/* 7512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7515 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7527 +/* 7519 */ MCD_OPC_CheckPredicate, 0, 94, 129, // Skip to: 40641 +/* 7523 */ MCD_OPC_Decode, 212, 15, 92, // Opcode: TBXv8i8One +/* 7527 */ MCD_OPC_FilterValue, 1, 86, 129, // Skip to: 40641 +/* 7531 */ MCD_OPC_CheckPredicate, 0, 82, 129, // Skip to: 40641 +/* 7535 */ MCD_OPC_Decode, 253, 9, 93, // Opcode: SADDWv8i8_v8i16 +/* 7539 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 7557 +/* 7543 */ MCD_OPC_CheckPredicate, 0, 70, 129, // Skip to: 40641 +/* 7547 */ MCD_OPC_CheckField, 21, 1, 1, 64, 129, // Skip to: 40641 +/* 7553 */ MCD_OPC_Decode, 228, 12, 89, // Opcode: SRHADDv8i8 +/* 7557 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 7594 +/* 7561 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7564 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7576 +/* 7568 */ MCD_OPC_CheckPredicate, 0, 45, 129, // Skip to: 40641 +/* 7572 */ MCD_OPC_Decode, 186, 18, 89, // Opcode: UZP1v8i8 +/* 7576 */ MCD_OPC_FilterValue, 1, 37, 129, // Skip to: 40641 +/* 7580 */ MCD_OPC_CheckPredicate, 0, 33, 129, // Skip to: 40641 +/* 7584 */ MCD_OPC_CheckField, 16, 5, 0, 27, 129, // Skip to: 40641 +/* 7590 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: REV16v8i8 +/* 7594 */ MCD_OPC_FilterValue, 7, 13, 0, // Skip to: 7611 +/* 7598 */ MCD_OPC_CheckPredicate, 0, 15, 129, // Skip to: 40641 +/* 7602 */ MCD_OPC_CheckField, 21, 1, 1, 9, 129, // Skip to: 40641 +/* 7608 */ MCD_OPC_Decode, 100, 89, // Opcode: ANDv8i8 +/* 7611 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 7642 +/* 7615 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7618 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7630 +/* 7622 */ MCD_OPC_CheckPredicate, 0, 247, 128, // Skip to: 40641 +/* 7626 */ MCD_OPC_Decode, 204, 15, 94, // Opcode: TBLv8i8Two +/* 7630 */ MCD_OPC_FilterValue, 1, 239, 128, // Skip to: 40641 +/* 7634 */ MCD_OPC_CheckPredicate, 0, 235, 128, // Skip to: 40641 +/* 7638 */ MCD_OPC_Decode, 168, 13, 85, // Opcode: SSUBLv8i8_v8i16 +/* 7642 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 7660 +/* 7646 */ MCD_OPC_CheckPredicate, 0, 223, 128, // Skip to: 40641 +/* 7650 */ MCD_OPC_CheckField, 21, 1, 1, 217, 128, // Skip to: 40641 +/* 7656 */ MCD_OPC_Decode, 195, 10, 89, // Opcode: SHSUBv8i8 +/* 7660 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 7710 +/* 7664 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7679 +/* 7671 */ MCD_OPC_CheckPredicate, 0, 198, 128, // Skip to: 40641 +/* 7675 */ MCD_OPC_Decode, 227, 15, 89, // Opcode: TRN1v8i8 +/* 7679 */ MCD_OPC_FilterValue, 1, 190, 128, // Skip to: 40641 +/* 7683 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 7686 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7698 +/* 7690 */ MCD_OPC_CheckPredicate, 0, 179, 128, // Skip to: 40641 +/* 7694 */ MCD_OPC_Decode, 236, 9, 90, // Opcode: SADDLPv8i8_v4i16 +/* 7698 */ MCD_OPC_FilterValue, 1, 171, 128, // Skip to: 40641 +/* 7702 */ MCD_OPC_CheckPredicate, 0, 167, 128, // Skip to: 40641 +/* 7706 */ MCD_OPC_Decode, 199, 18, 95, // Opcode: XTNv8i8 +/* 7710 */ MCD_OPC_FilterValue, 11, 52, 0, // Skip to: 7766 +/* 7714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7717 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7754 +/* 7721 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 7724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7742 +/* 7728 */ MCD_OPC_CheckPredicate, 0, 141, 128, // Skip to: 40641 +/* 7732 */ MCD_OPC_CheckField, 17, 1, 1, 135, 128, // Skip to: 40641 +/* 7738 */ MCD_OPC_Decode, 132, 11, 96, // Opcode: SMOVvi16to32 +/* 7742 */ MCD_OPC_FilterValue, 1, 127, 128, // Skip to: 40641 +/* 7746 */ MCD_OPC_CheckPredicate, 0, 123, 128, // Skip to: 40641 +/* 7750 */ MCD_OPC_Decode, 135, 11, 97, // Opcode: SMOVvi8to32 +/* 7754 */ MCD_OPC_FilterValue, 1, 115, 128, // Skip to: 40641 +/* 7758 */ MCD_OPC_CheckPredicate, 0, 111, 128, // Skip to: 40641 +/* 7762 */ MCD_OPC_Decode, 204, 12, 89, // Opcode: SQSUBv8i8 +/* 7766 */ MCD_OPC_FilterValue, 12, 27, 0, // Skip to: 7797 +/* 7770 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7773 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7785 +/* 7777 */ MCD_OPC_CheckPredicate, 0, 92, 128, // Skip to: 40641 +/* 7781 */ MCD_OPC_Decode, 214, 15, 98, // Opcode: TBXv8i8Two +/* 7785 */ MCD_OPC_FilterValue, 1, 84, 128, // Skip to: 40641 +/* 7789 */ MCD_OPC_CheckPredicate, 0, 80, 128, // Skip to: 40641 +/* 7793 */ MCD_OPC_Decode, 174, 13, 93, // Opcode: SSUBWv8i8_v8i16 +/* 7797 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 7815 +/* 7801 */ MCD_OPC_CheckPredicate, 0, 68, 128, // Skip to: 40641 +/* 7805 */ MCD_OPC_CheckField, 21, 1, 1, 62, 128, // Skip to: 40641 +/* 7811 */ MCD_OPC_Decode, 206, 1, 89, // Opcode: CMGTv8i8 +/* 7815 */ MCD_OPC_FilterValue, 14, 46, 0, // Skip to: 7865 +/* 7819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7822 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7834 +/* 7826 */ MCD_OPC_CheckPredicate, 0, 43, 128, // Skip to: 40641 +/* 7830 */ MCD_OPC_Decode, 206, 18, 89, // Opcode: ZIP1v8i8 +/* 7834 */ MCD_OPC_FilterValue, 1, 35, 128, // Skip to: 40641 +/* 7838 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 7841 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7853 +/* 7845 */ MCD_OPC_CheckPredicate, 0, 24, 128, // Skip to: 40641 +/* 7849 */ MCD_OPC_Decode, 193, 15, 99, // Opcode: SUQADDv8i8 +/* 7853 */ MCD_OPC_FilterValue, 16, 16, 128, // Skip to: 40641 +/* 7857 */ MCD_OPC_CheckPredicate, 0, 12, 128, // Skip to: 40641 +/* 7861 */ MCD_OPC_Decode, 241, 9, 100, // Opcode: SADDLVv8i8v +/* 7865 */ MCD_OPC_FilterValue, 15, 71, 0, // Skip to: 7940 +/* 7869 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7872 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7928 +/* 7876 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 7879 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7916 +/* 7883 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 7886 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7904 +/* 7890 */ MCD_OPC_CheckPredicate, 0, 235, 127, // Skip to: 40641 +/* 7894 */ MCD_OPC_CheckField, 18, 1, 1, 229, 127, // Skip to: 40641 +/* 7900 */ MCD_OPC_Decode, 252, 16, 101, // Opcode: UMOVvi32 +/* 7904 */ MCD_OPC_FilterValue, 1, 221, 127, // Skip to: 40641 +/* 7908 */ MCD_OPC_CheckPredicate, 0, 217, 127, // Skip to: 40641 +/* 7912 */ MCD_OPC_Decode, 251, 16, 96, // Opcode: UMOVvi16 +/* 7916 */ MCD_OPC_FilterValue, 1, 209, 127, // Skip to: 40641 +/* 7920 */ MCD_OPC_CheckPredicate, 0, 205, 127, // Skip to: 40641 +/* 7924 */ MCD_OPC_Decode, 254, 16, 97, // Opcode: UMOVvi8 +/* 7928 */ MCD_OPC_FilterValue, 1, 197, 127, // Skip to: 40641 +/* 7932 */ MCD_OPC_CheckPredicate, 0, 193, 127, // Skip to: 40641 +/* 7936 */ MCD_OPC_Decode, 190, 1, 89, // Opcode: CMGEv8i8 +/* 7940 */ MCD_OPC_FilterValue, 16, 26, 0, // Skip to: 7970 +/* 7944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 7947 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7959 +/* 7951 */ MCD_OPC_CheckPredicate, 0, 174, 127, // Skip to: 40641 +/* 7955 */ MCD_OPC_Decode, 203, 15, 102, // Opcode: TBLv8i8Three +/* 7959 */ MCD_OPC_FilterValue, 1, 166, 127, // Skip to: 40641 +/* 7963 */ MCD_OPC_CheckPredicate, 0, 162, 127, // Skip to: 40641 +/* 7967 */ MCD_OPC_Decode, 39, 103, // Opcode: ADDHNv8i16_v8i8 +/* 7970 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 7988 +/* 7974 */ MCD_OPC_CheckPredicate, 0, 151, 127, // Skip to: 40641 +/* 7978 */ MCD_OPC_CheckField, 21, 1, 1, 145, 127, // Skip to: 40641 +/* 7984 */ MCD_OPC_Decode, 146, 13, 89, // Opcode: SSHLv8i8 +/* 7988 */ MCD_OPC_FilterValue, 18, 27, 0, // Skip to: 8019 +/* 7992 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 7995 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8007 +/* 7999 */ MCD_OPC_CheckPredicate, 0, 126, 127, // Skip to: 40641 +/* 8003 */ MCD_OPC_Decode, 151, 1, 90, // Opcode: CLSv8i8 +/* 8007 */ MCD_OPC_FilterValue, 33, 118, 127, // Skip to: 40641 +/* 8011 */ MCD_OPC_CheckPredicate, 0, 114, 127, // Skip to: 40641 +/* 8015 */ MCD_OPC_Decode, 213, 12, 95, // Opcode: SQXTNv8i8 +/* 8019 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 8037 +/* 8023 */ MCD_OPC_CheckPredicate, 0, 102, 127, // Skip to: 40641 +/* 8027 */ MCD_OPC_CheckField, 21, 1, 1, 96, 127, // Skip to: 40641 +/* 8033 */ MCD_OPC_Decode, 174, 12, 89, // Opcode: SQSHLv8i8 +/* 8037 */ MCD_OPC_FilterValue, 20, 27, 0, // Skip to: 8068 +/* 8041 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8044 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8056 +/* 8048 */ MCD_OPC_CheckPredicate, 0, 77, 127, // Skip to: 40641 +/* 8052 */ MCD_OPC_Decode, 213, 15, 104, // Opcode: TBXv8i8Three +/* 8056 */ MCD_OPC_FilterValue, 1, 69, 127, // Skip to: 40641 +/* 8060 */ MCD_OPC_CheckPredicate, 0, 65, 127, // Skip to: 40641 +/* 8064 */ MCD_OPC_Decode, 206, 9, 105, // Opcode: SABALv8i8_v8i16 +/* 8068 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 8086 +/* 8072 */ MCD_OPC_CheckPredicate, 0, 53, 127, // Skip to: 40641 +/* 8076 */ MCD_OPC_CheckField, 21, 1, 1, 47, 127, // Skip to: 40641 +/* 8082 */ MCD_OPC_Decode, 244, 12, 89, // Opcode: SRSHLv8i8 +/* 8086 */ MCD_OPC_FilterValue, 22, 33, 0, // Skip to: 8123 +/* 8090 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8105 +/* 8097 */ MCD_OPC_CheckPredicate, 0, 28, 127, // Skip to: 40641 +/* 8101 */ MCD_OPC_Decode, 193, 18, 89, // Opcode: UZP2v8i8 +/* 8105 */ MCD_OPC_FilterValue, 1, 20, 127, // Skip to: 40641 +/* 8109 */ MCD_OPC_CheckPredicate, 0, 16, 127, // Skip to: 40641 +/* 8113 */ MCD_OPC_CheckField, 16, 5, 0, 10, 127, // Skip to: 40641 +/* 8119 */ MCD_OPC_Decode, 249, 1, 90, // Opcode: CNTv8i8 +/* 8123 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 8141 +/* 8127 */ MCD_OPC_CheckPredicate, 0, 254, 126, // Skip to: 40641 +/* 8131 */ MCD_OPC_CheckField, 21, 1, 1, 248, 126, // Skip to: 40641 +/* 8137 */ MCD_OPC_Decode, 252, 11, 89, // Opcode: SQRSHLv8i8 +/* 8141 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 8172 +/* 8145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8148 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8160 +/* 8152 */ MCD_OPC_CheckPredicate, 0, 229, 126, // Skip to: 40641 +/* 8156 */ MCD_OPC_Decode, 201, 15, 106, // Opcode: TBLv8i8Four +/* 8160 */ MCD_OPC_FilterValue, 1, 221, 126, // Skip to: 40641 +/* 8164 */ MCD_OPC_CheckPredicate, 0, 217, 126, // Skip to: 40641 +/* 8168 */ MCD_OPC_Decode, 156, 15, 103, // Opcode: SUBHNv8i16_v8i8 +/* 8172 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 8190 +/* 8176 */ MCD_OPC_CheckPredicate, 0, 205, 126, // Skip to: 40641 +/* 8180 */ MCD_OPC_CheckField, 21, 1, 1, 199, 126, // Skip to: 40641 +/* 8186 */ MCD_OPC_Decode, 221, 10, 89, // Opcode: SMAXv8i8 +/* 8190 */ MCD_OPC_FilterValue, 26, 46, 0, // Skip to: 8240 +/* 8194 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8197 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8209 +/* 8201 */ MCD_OPC_CheckPredicate, 0, 180, 126, // Skip to: 40641 +/* 8205 */ MCD_OPC_Decode, 234, 15, 89, // Opcode: TRN2v8i8 +/* 8209 */ MCD_OPC_FilterValue, 1, 172, 126, // Skip to: 40641 +/* 8213 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 8216 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8228 +/* 8220 */ MCD_OPC_CheckPredicate, 0, 161, 126, // Skip to: 40641 +/* 8224 */ MCD_OPC_Decode, 230, 9, 99, // Opcode: SADALPv8i8_v4i16 +/* 8228 */ MCD_OPC_FilterValue, 1, 153, 126, // Skip to: 40641 +/* 8232 */ MCD_OPC_CheckPredicate, 0, 149, 126, // Skip to: 40641 +/* 8236 */ MCD_OPC_Decode, 199, 3, 95, // Opcode: FCVTNv4i16 +/* 8240 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 8258 +/* 8244 */ MCD_OPC_CheckPredicate, 0, 137, 126, // Skip to: 40641 +/* 8248 */ MCD_OPC_CheckField, 21, 1, 1, 131, 126, // Skip to: 40641 +/* 8254 */ MCD_OPC_Decode, 239, 10, 89, // Opcode: SMINv8i8 +/* 8258 */ MCD_OPC_FilterValue, 28, 27, 0, // Skip to: 8289 +/* 8262 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8265 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8277 +/* 8269 */ MCD_OPC_CheckPredicate, 0, 112, 126, // Skip to: 40641 +/* 8273 */ MCD_OPC_Decode, 211, 15, 107, // Opcode: TBXv8i8Four +/* 8277 */ MCD_OPC_FilterValue, 1, 104, 126, // Skip to: 40641 +/* 8281 */ MCD_OPC_CheckPredicate, 0, 100, 126, // Skip to: 40641 +/* 8285 */ MCD_OPC_Decode, 218, 9, 85, // Opcode: SABDLv8i8_v8i16 +/* 8289 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 8307 +/* 8293 */ MCD_OPC_CheckPredicate, 0, 88, 126, // Skip to: 40641 +/* 8297 */ MCD_OPC_CheckField, 21, 1, 1, 82, 126, // Skip to: 40641 +/* 8303 */ MCD_OPC_Decode, 224, 9, 89, // Opcode: SABDv8i8 +/* 8307 */ MCD_OPC_FilterValue, 30, 46, 0, // Skip to: 8357 +/* 8311 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8314 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8326 +/* 8318 */ MCD_OPC_CheckPredicate, 0, 63, 126, // Skip to: 40641 +/* 8322 */ MCD_OPC_Decode, 213, 18, 89, // Opcode: ZIP2v8i8 +/* 8326 */ MCD_OPC_FilterValue, 1, 55, 126, // Skip to: 40641 +/* 8330 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 8333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8345 +/* 8337 */ MCD_OPC_CheckPredicate, 0, 44, 126, // Skip to: 40641 +/* 8341 */ MCD_OPC_Decode, 159, 11, 90, // Opcode: SQABSv8i8 +/* 8345 */ MCD_OPC_FilterValue, 1, 36, 126, // Skip to: 40641 +/* 8349 */ MCD_OPC_CheckPredicate, 0, 32, 126, // Skip to: 40641 +/* 8353 */ MCD_OPC_Decode, 159, 3, 108, // Opcode: FCVTLv4i16 +/* 8357 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 8375 +/* 8361 */ MCD_OPC_CheckPredicate, 0, 20, 126, // Skip to: 40641 +/* 8365 */ MCD_OPC_CheckField, 21, 1, 1, 14, 126, // Skip to: 40641 +/* 8371 */ MCD_OPC_Decode, 212, 9, 109, // Opcode: SABAv8i8 +/* 8375 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 8393 +/* 8379 */ MCD_OPC_CheckPredicate, 0, 2, 126, // Skip to: 40641 +/* 8383 */ MCD_OPC_CheckField, 21, 1, 1, 252, 125, // Skip to: 40641 +/* 8389 */ MCD_OPC_Decode, 249, 10, 105, // Opcode: SMLALv8i8_v8i16 +/* 8393 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 8410 +/* 8397 */ MCD_OPC_CheckPredicate, 0, 240, 125, // Skip to: 40641 +/* 8401 */ MCD_OPC_CheckField, 21, 1, 1, 234, 125, // Skip to: 40641 +/* 8407 */ MCD_OPC_Decode, 78, 89, // Opcode: ADDv8i8 +/* 8410 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 8441 +/* 8414 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 8417 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8429 +/* 8421 */ MCD_OPC_CheckPredicate, 0, 216, 125, // Skip to: 40641 +/* 8425 */ MCD_OPC_Decode, 207, 1, 90, // Opcode: CMGTv8i8rz +/* 8429 */ MCD_OPC_FilterValue, 33, 208, 125, // Skip to: 40641 +/* 8433 */ MCD_OPC_CheckPredicate, 0, 204, 125, // Skip to: 40641 +/* 8437 */ MCD_OPC_Decode, 169, 5, 90, // Opcode: FRINTNv2f32 +/* 8441 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 8459 +/* 8445 */ MCD_OPC_CheckPredicate, 0, 192, 125, // Skip to: 40641 +/* 8449 */ MCD_OPC_CheckField, 21, 1, 1, 186, 125, // Skip to: 40641 +/* 8455 */ MCD_OPC_Decode, 247, 1, 89, // Opcode: CMTSTv8i8 +/* 8459 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 8477 +/* 8463 */ MCD_OPC_CheckPredicate, 0, 174, 125, // Skip to: 40641 +/* 8467 */ MCD_OPC_CheckField, 21, 1, 1, 168, 125, // Skip to: 40641 +/* 8473 */ MCD_OPC_Decode, 191, 8, 109, // Opcode: MLAv8i8 +/* 8477 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 8508 +/* 8481 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 8484 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8496 +/* 8488 */ MCD_OPC_CheckPredicate, 0, 149, 125, // Skip to: 40641 +/* 8492 */ MCD_OPC_Decode, 175, 1, 90, // Opcode: CMEQv8i8rz +/* 8496 */ MCD_OPC_FilterValue, 33, 141, 125, // Skip to: 40641 +/* 8500 */ MCD_OPC_CheckPredicate, 0, 137, 125, // Skip to: 40641 +/* 8504 */ MCD_OPC_Decode, 164, 5, 90, // Opcode: FRINTMv2f32 +/* 8508 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 8526 +/* 8512 */ MCD_OPC_CheckPredicate, 0, 125, 125, // Skip to: 40641 +/* 8516 */ MCD_OPC_CheckField, 21, 1, 1, 119, 125, // Skip to: 40641 +/* 8522 */ MCD_OPC_Decode, 240, 8, 89, // Opcode: MULv8i8 +/* 8526 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 8544 +/* 8530 */ MCD_OPC_CheckPredicate, 0, 107, 125, // Skip to: 40641 +/* 8534 */ MCD_OPC_CheckField, 21, 1, 1, 101, 125, // Skip to: 40641 +/* 8540 */ MCD_OPC_Decode, 131, 11, 105, // Opcode: SMLSLv8i8_v8i16 +/* 8544 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 8562 +/* 8548 */ MCD_OPC_CheckPredicate, 0, 89, 125, // Skip to: 40641 +/* 8552 */ MCD_OPC_CheckField, 21, 1, 1, 83, 125, // Skip to: 40641 +/* 8558 */ MCD_OPC_Decode, 210, 10, 89, // Opcode: SMAXPv8i8 +/* 8562 */ MCD_OPC_FilterValue, 42, 51, 0, // Skip to: 8617 +/* 8566 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 8569 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8581 +/* 8573 */ MCD_OPC_CheckPredicate, 0, 64, 125, // Skip to: 40641 +/* 8577 */ MCD_OPC_Decode, 239, 1, 90, // Opcode: CMLTv8i8rz +/* 8581 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8593 +/* 8585 */ MCD_OPC_CheckPredicate, 0, 52, 125, // Skip to: 40641 +/* 8589 */ MCD_OPC_Decode, 186, 3, 90, // Opcode: FCVTNSv2f32 +/* 8593 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 8605 +/* 8597 */ MCD_OPC_CheckPredicate, 0, 40, 125, // Skip to: 40641 +/* 8601 */ MCD_OPC_Decode, 215, 10, 110, // Opcode: SMAXVv8i8v +/* 8605 */ MCD_OPC_FilterValue, 49, 32, 125, // Skip to: 40641 +/* 8609 */ MCD_OPC_CheckPredicate, 0, 28, 125, // Skip to: 40641 +/* 8613 */ MCD_OPC_Decode, 233, 10, 110, // Opcode: SMINVv8i8v +/* 8617 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 8635 +/* 8621 */ MCD_OPC_CheckPredicate, 0, 16, 125, // Skip to: 40641 +/* 8625 */ MCD_OPC_CheckField, 21, 1, 1, 10, 125, // Skip to: 40641 +/* 8631 */ MCD_OPC_Decode, 228, 10, 89, // Opcode: SMINPv8i8 +/* 8635 */ MCD_OPC_FilterValue, 46, 37, 0, // Skip to: 8676 +/* 8639 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 8642 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 8653 +/* 8646 */ MCD_OPC_CheckPredicate, 0, 247, 124, // Skip to: 40641 +/* 8650 */ MCD_OPC_Decode, 29, 90, // Opcode: ABSv8i8 +/* 8653 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8665 +/* 8657 */ MCD_OPC_CheckPredicate, 0, 236, 124, // Skip to: 40641 +/* 8661 */ MCD_OPC_Decode, 168, 3, 90, // Opcode: FCVTMSv2f32 +/* 8665 */ MCD_OPC_FilterValue, 49, 228, 124, // Skip to: 40641 +/* 8669 */ MCD_OPC_CheckPredicate, 0, 224, 124, // Skip to: 40641 +/* 8673 */ MCD_OPC_Decode, 61, 110, // Opcode: ADDVv8i8v +/* 8676 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 8693 +/* 8680 */ MCD_OPC_CheckPredicate, 0, 213, 124, // Skip to: 40641 +/* 8684 */ MCD_OPC_CheckField, 21, 1, 1, 207, 124, // Skip to: 40641 +/* 8690 */ MCD_OPC_Decode, 47, 89, // Opcode: ADDPv8i8 +/* 8693 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 8711 +/* 8697 */ MCD_OPC_CheckPredicate, 0, 196, 124, // Skip to: 40641 +/* 8701 */ MCD_OPC_CheckField, 21, 1, 1, 190, 124, // Skip to: 40641 +/* 8707 */ MCD_OPC_Decode, 148, 11, 85, // Opcode: SMULLv8i8_v8i16 +/* 8711 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 8729 +/* 8715 */ MCD_OPC_CheckPredicate, 0, 178, 124, // Skip to: 40641 +/* 8719 */ MCD_OPC_CheckField, 21, 1, 1, 172, 124, // Skip to: 40641 +/* 8725 */ MCD_OPC_Decode, 171, 4, 89, // Opcode: FMAXNMv2f32 +/* 8729 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 8747 +/* 8733 */ MCD_OPC_CheckPredicate, 0, 160, 124, // Skip to: 40641 +/* 8737 */ MCD_OPC_CheckField, 16, 6, 33, 154, 124, // Skip to: 40641 +/* 8743 */ MCD_OPC_Decode, 142, 3, 90, // Opcode: FCVTASv2f32 +/* 8747 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 8765 +/* 8751 */ MCD_OPC_CheckPredicate, 0, 142, 124, // Skip to: 40641 +/* 8755 */ MCD_OPC_CheckField, 21, 1, 1, 136, 124, // Skip to: 40641 +/* 8761 */ MCD_OPC_Decode, 208, 4, 109, // Opcode: FMLAv2f32 +/* 8765 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 8783 +/* 8769 */ MCD_OPC_CheckPredicate, 0, 124, 124, // Skip to: 40641 +/* 8773 */ MCD_OPC_CheckField, 21, 1, 1, 118, 124, // Skip to: 40641 +/* 8779 */ MCD_OPC_Decode, 207, 2, 89, // Opcode: FADDv2f32 +/* 8783 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 8801 +/* 8787 */ MCD_OPC_CheckPredicate, 0, 106, 124, // Skip to: 40641 +/* 8791 */ MCD_OPC_CheckField, 16, 6, 33, 100, 124, // Skip to: 40641 +/* 8797 */ MCD_OPC_Decode, 144, 10, 90, // Opcode: SCVTFv2f32 +/* 8801 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 8819 +/* 8805 */ MCD_OPC_CheckPredicate, 0, 88, 124, // Skip to: 40641 +/* 8809 */ MCD_OPC_CheckField, 21, 1, 1, 82, 124, // Skip to: 40641 +/* 8815 */ MCD_OPC_Decode, 243, 4, 89, // Opcode: FMULXv2f32 +/* 8819 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 8837 +/* 8823 */ MCD_OPC_CheckPredicate, 0, 70, 124, // Skip to: 40641 +/* 8827 */ MCD_OPC_CheckField, 21, 1, 1, 64, 124, // Skip to: 40641 +/* 8833 */ MCD_OPC_Decode, 150, 9, 85, // Opcode: PMULLv8i8 +/* 8837 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 8855 +/* 8841 */ MCD_OPC_CheckPredicate, 0, 52, 124, // Skip to: 40641 +/* 8845 */ MCD_OPC_CheckField, 21, 1, 1, 46, 124, // Skip to: 40641 +/* 8851 */ MCD_OPC_Decode, 218, 2, 89, // Opcode: FCMEQv2f32 +/* 8855 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 8873 +/* 8859 */ MCD_OPC_CheckPredicate, 0, 34, 124, // Skip to: 40641 +/* 8863 */ MCD_OPC_CheckField, 21, 1, 1, 28, 124, // Skip to: 40641 +/* 8869 */ MCD_OPC_Decode, 181, 4, 89, // Opcode: FMAXv2f32 +/* 8873 */ MCD_OPC_FilterValue, 63, 20, 124, // Skip to: 40641 +/* 8877 */ MCD_OPC_CheckPredicate, 0, 16, 124, // Skip to: 40641 +/* 8881 */ MCD_OPC_CheckField, 21, 1, 1, 10, 124, // Skip to: 40641 +/* 8887 */ MCD_OPC_Decode, 147, 5, 89, // Opcode: FRECPSv2f32 +/* 8891 */ MCD_OPC_FilterValue, 1, 85, 4, // Skip to: 10004 +/* 8895 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 8898 */ MCD_OPC_FilterValue, 0, 64, 1, // Skip to: 9222 +/* 8902 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 8905 */ MCD_OPC_FilterValue, 0, 162, 0, // Skip to: 9071 +/* 8909 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 8912 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8924 +/* 8916 */ MCD_OPC_CheckPredicate, 0, 233, 123, // Skip to: 40641 +/* 8920 */ MCD_OPC_Decode, 178, 2, 111, // Opcode: EXTv8i8 +/* 8924 */ MCD_OPC_FilterValue, 1, 225, 123, // Skip to: 40641 +/* 8928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 8931 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8943 +/* 8935 */ MCD_OPC_CheckPredicate, 0, 214, 123, // Skip to: 40641 +/* 8939 */ MCD_OPC_Decode, 153, 16, 85, // Opcode: UADDLv8i8_v8i16 +/* 8943 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8961 +/* 8947 */ MCD_OPC_CheckPredicate, 0, 202, 123, // Skip to: 40641 +/* 8951 */ MCD_OPC_CheckField, 16, 5, 0, 196, 123, // Skip to: 40641 +/* 8957 */ MCD_OPC_Decode, 178, 9, 90, // Opcode: REV32v8i8 +/* 8961 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8973 +/* 8965 */ MCD_OPC_CheckPredicate, 0, 184, 123, // Skip to: 40641 +/* 8969 */ MCD_OPC_Decode, 159, 16, 93, // Opcode: UADDWv8i8_v8i16 +/* 8973 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8985 +/* 8977 */ MCD_OPC_CheckPredicate, 0, 172, 123, // Skip to: 40641 +/* 8981 */ MCD_OPC_Decode, 173, 18, 85, // Opcode: USUBLv8i8_v8i16 +/* 8985 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 9016 +/* 8989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 8992 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9004 +/* 8996 */ MCD_OPC_CheckPredicate, 0, 153, 123, // Skip to: 40641 +/* 9000 */ MCD_OPC_Decode, 142, 16, 90, // Opcode: UADDLPv8i8_v4i16 +/* 9004 */ MCD_OPC_FilterValue, 1, 145, 123, // Skip to: 40641 +/* 9008 */ MCD_OPC_CheckPredicate, 0, 141, 123, // Skip to: 40641 +/* 9012 */ MCD_OPC_Decode, 222, 12, 95, // Opcode: SQXTUNv8i8 +/* 9016 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9028 +/* 9020 */ MCD_OPC_CheckPredicate, 0, 129, 123, // Skip to: 40641 +/* 9024 */ MCD_OPC_Decode, 179, 18, 93, // Opcode: USUBWv8i8_v8i16 +/* 9028 */ MCD_OPC_FilterValue, 7, 121, 123, // Skip to: 40641 +/* 9032 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 9035 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9047 +/* 9039 */ MCD_OPC_CheckPredicate, 0, 110, 123, // Skip to: 40641 +/* 9043 */ MCD_OPC_Decode, 159, 18, 99, // Opcode: USQADDv8i8 +/* 9047 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 9059 +/* 9051 */ MCD_OPC_CheckPredicate, 0, 98, 123, // Skip to: 40641 +/* 9055 */ MCD_OPC_Decode, 175, 10, 108, // Opcode: SHLLv8i8 +/* 9059 */ MCD_OPC_FilterValue, 16, 90, 123, // Skip to: 40641 +/* 9063 */ MCD_OPC_CheckPredicate, 0, 86, 123, // Skip to: 40641 +/* 9067 */ MCD_OPC_Decode, 147, 16, 100, // Opcode: UADDLVv8i8v +/* 9071 */ MCD_OPC_FilterValue, 1, 78, 123, // Skip to: 40641 +/* 9075 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 9078 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9096 +/* 9082 */ MCD_OPC_CheckPredicate, 0, 67, 123, // Skip to: 40641 +/* 9086 */ MCD_OPC_CheckField, 21, 1, 1, 61, 123, // Skip to: 40641 +/* 9092 */ MCD_OPC_Decode, 189, 16, 89, // Opcode: UHADDv8i8 +/* 9096 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9114 +/* 9100 */ MCD_OPC_CheckPredicate, 0, 49, 123, // Skip to: 40641 +/* 9104 */ MCD_OPC_CheckField, 21, 1, 1, 43, 123, // Skip to: 40641 +/* 9110 */ MCD_OPC_Decode, 149, 17, 89, // Opcode: UQADDv8i8 +/* 9114 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9132 +/* 9118 */ MCD_OPC_CheckPredicate, 0, 31, 123, // Skip to: 40641 +/* 9122 */ MCD_OPC_CheckField, 21, 1, 1, 25, 123, // Skip to: 40641 +/* 9128 */ MCD_OPC_Decode, 228, 17, 89, // Opcode: URHADDv8i8 +/* 9132 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9150 +/* 9136 */ MCD_OPC_CheckPredicate, 0, 13, 123, // Skip to: 40641 +/* 9140 */ MCD_OPC_CheckField, 21, 1, 1, 7, 123, // Skip to: 40641 +/* 9146 */ MCD_OPC_Decode, 173, 2, 89, // Opcode: EORv8i8 +/* 9150 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9168 +/* 9154 */ MCD_OPC_CheckPredicate, 0, 251, 122, // Skip to: 40641 +/* 9158 */ MCD_OPC_CheckField, 21, 1, 1, 245, 122, // Skip to: 40641 +/* 9164 */ MCD_OPC_Decode, 195, 16, 89, // Opcode: UHSUBv8i8 +/* 9168 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9186 +/* 9172 */ MCD_OPC_CheckPredicate, 0, 233, 122, // Skip to: 40641 +/* 9176 */ MCD_OPC_CheckField, 21, 1, 1, 227, 122, // Skip to: 40641 +/* 9182 */ MCD_OPC_Decode, 211, 17, 89, // Opcode: UQSUBv8i8 +/* 9186 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9204 +/* 9190 */ MCD_OPC_CheckPredicate, 0, 215, 122, // Skip to: 40641 +/* 9194 */ MCD_OPC_CheckField, 21, 1, 1, 209, 122, // Skip to: 40641 +/* 9200 */ MCD_OPC_Decode, 215, 1, 89, // Opcode: CMHIv8i8 +/* 9204 */ MCD_OPC_FilterValue, 7, 201, 122, // Skip to: 40641 +/* 9208 */ MCD_OPC_CheckPredicate, 0, 197, 122, // Skip to: 40641 +/* 9212 */ MCD_OPC_CheckField, 21, 1, 1, 191, 122, // Skip to: 40641 +/* 9218 */ MCD_OPC_Decode, 223, 1, 89, // Opcode: CMHSv8i8 +/* 9222 */ MCD_OPC_FilterValue, 1, 48, 1, // Skip to: 9530 +/* 9226 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 9229 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9247 +/* 9233 */ MCD_OPC_CheckPredicate, 0, 172, 122, // Skip to: 40641 +/* 9237 */ MCD_OPC_CheckField, 21, 1, 1, 166, 122, // Skip to: 40641 +/* 9243 */ MCD_OPC_Decode, 163, 9, 103, // Opcode: RADDHNv8i16_v8i8 +/* 9247 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9265 +/* 9251 */ MCD_OPC_CheckPredicate, 0, 154, 122, // Skip to: 40641 +/* 9255 */ MCD_OPC_CheckField, 21, 1, 1, 148, 122, // Skip to: 40641 +/* 9261 */ MCD_OPC_Decode, 140, 18, 89, // Opcode: USHLv8i8 +/* 9265 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9296 +/* 9269 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 9272 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9284 +/* 9276 */ MCD_OPC_CheckPredicate, 0, 129, 122, // Skip to: 40641 +/* 9280 */ MCD_OPC_Decode, 159, 1, 90, // Opcode: CLZv8i8 +/* 9284 */ MCD_OPC_FilterValue, 33, 121, 122, // Skip to: 40641 +/* 9288 */ MCD_OPC_CheckPredicate, 0, 117, 122, // Skip to: 40641 +/* 9292 */ MCD_OPC_Decode, 220, 17, 95, // Opcode: UQXTNv8i8 +/* 9296 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9314 +/* 9300 */ MCD_OPC_CheckPredicate, 0, 105, 122, // Skip to: 40641 +/* 9304 */ MCD_OPC_CheckField, 21, 1, 1, 99, 122, // Skip to: 40641 +/* 9310 */ MCD_OPC_Decode, 190, 17, 89, // Opcode: UQSHLv8i8 +/* 9314 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9332 +/* 9318 */ MCD_OPC_CheckPredicate, 0, 87, 122, // Skip to: 40641 +/* 9322 */ MCD_OPC_CheckField, 21, 1, 1, 81, 122, // Skip to: 40641 +/* 9328 */ MCD_OPC_Decode, 240, 15, 105, // Opcode: UABALv8i8_v8i16 +/* 9332 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9350 +/* 9336 */ MCD_OPC_CheckPredicate, 0, 69, 122, // Skip to: 40641 +/* 9340 */ MCD_OPC_CheckField, 21, 1, 1, 63, 122, // Skip to: 40641 +/* 9346 */ MCD_OPC_Decode, 236, 17, 89, // Opcode: URSHLv8i8 +/* 9350 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9368 +/* 9354 */ MCD_OPC_CheckPredicate, 0, 51, 122, // Skip to: 40641 +/* 9358 */ MCD_OPC_CheckField, 16, 6, 32, 45, 122, // Skip to: 40641 +/* 9364 */ MCD_OPC_Decode, 128, 9, 90, // Opcode: NOTv8i8 +/* 9368 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9386 +/* 9372 */ MCD_OPC_CheckPredicate, 0, 33, 122, // Skip to: 40641 +/* 9376 */ MCD_OPC_CheckField, 21, 1, 1, 27, 122, // Skip to: 40641 +/* 9382 */ MCD_OPC_Decode, 160, 17, 89, // Opcode: UQRSHLv8i8 +/* 9386 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9404 +/* 9390 */ MCD_OPC_CheckPredicate, 0, 15, 122, // Skip to: 40641 +/* 9394 */ MCD_OPC_CheckField, 21, 1, 1, 9, 122, // Skip to: 40641 +/* 9400 */ MCD_OPC_Decode, 200, 9, 103, // Opcode: RSUBHNv8i16_v8i8 +/* 9404 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9422 +/* 9408 */ MCD_OPC_CheckPredicate, 0, 253, 121, // Skip to: 40641 +/* 9412 */ MCD_OPC_CheckField, 21, 1, 1, 247, 121, // Skip to: 40641 +/* 9418 */ MCD_OPC_Decode, 213, 16, 89, // Opcode: UMAXv8i8 +/* 9422 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 9440 +/* 9426 */ MCD_OPC_CheckPredicate, 0, 235, 121, // Skip to: 40641 +/* 9430 */ MCD_OPC_CheckField, 16, 6, 32, 229, 121, // Skip to: 40641 +/* 9436 */ MCD_OPC_Decode, 136, 16, 99, // Opcode: UADALPv8i8_v4i16 +/* 9440 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9458 +/* 9444 */ MCD_OPC_CheckPredicate, 0, 217, 121, // Skip to: 40641 +/* 9448 */ MCD_OPC_CheckField, 21, 1, 1, 211, 121, // Skip to: 40641 +/* 9454 */ MCD_OPC_Decode, 230, 16, 89, // Opcode: UMINv8i8 +/* 9458 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 9476 +/* 9462 */ MCD_OPC_CheckPredicate, 0, 199, 121, // Skip to: 40641 +/* 9466 */ MCD_OPC_CheckField, 21, 1, 1, 193, 121, // Skip to: 40641 +/* 9472 */ MCD_OPC_Decode, 252, 15, 85, // Opcode: UABDLv8i8_v8i16 +/* 9476 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9494 +/* 9480 */ MCD_OPC_CheckPredicate, 0, 181, 121, // Skip to: 40641 +/* 9484 */ MCD_OPC_CheckField, 21, 1, 1, 175, 121, // Skip to: 40641 +/* 9490 */ MCD_OPC_Decode, 130, 16, 89, // Opcode: UABDv8i8 +/* 9494 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 9512 +/* 9498 */ MCD_OPC_CheckPredicate, 0, 163, 121, // Skip to: 40641 +/* 9502 */ MCD_OPC_CheckField, 16, 6, 32, 157, 121, // Skip to: 40641 +/* 9508 */ MCD_OPC_Decode, 229, 11, 90, // Opcode: SQNEGv8i8 +/* 9512 */ MCD_OPC_FilterValue, 15, 149, 121, // Skip to: 40641 +/* 9516 */ MCD_OPC_CheckPredicate, 0, 145, 121, // Skip to: 40641 +/* 9520 */ MCD_OPC_CheckField, 21, 1, 1, 139, 121, // Skip to: 40641 +/* 9526 */ MCD_OPC_Decode, 246, 15, 109, // Opcode: UABAv8i8 +/* 9530 */ MCD_OPC_FilterValue, 2, 27, 1, // Skip to: 9817 +/* 9534 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 9537 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9555 +/* 9541 */ MCD_OPC_CheckPredicate, 0, 120, 121, // Skip to: 40641 +/* 9545 */ MCD_OPC_CheckField, 21, 1, 1, 114, 121, // Skip to: 40641 +/* 9551 */ MCD_OPC_Decode, 240, 16, 105, // Opcode: UMLALv8i8_v8i16 +/* 9555 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9573 +/* 9559 */ MCD_OPC_CheckPredicate, 0, 102, 121, // Skip to: 40641 +/* 9563 */ MCD_OPC_CheckField, 21, 1, 1, 96, 121, // Skip to: 40641 +/* 9569 */ MCD_OPC_Decode, 182, 15, 89, // Opcode: SUBv8i8 +/* 9573 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9604 +/* 9577 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 9580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9592 +/* 9584 */ MCD_OPC_CheckPredicate, 0, 77, 121, // Skip to: 40641 +/* 9588 */ MCD_OPC_Decode, 191, 1, 90, // Opcode: CMGEv8i8rz +/* 9592 */ MCD_OPC_FilterValue, 33, 69, 121, // Skip to: 40641 +/* 9596 */ MCD_OPC_CheckPredicate, 0, 65, 121, // Skip to: 40641 +/* 9600 */ MCD_OPC_Decode, 154, 5, 90, // Opcode: FRINTAv2f32 +/* 9604 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9622 +/* 9608 */ MCD_OPC_CheckPredicate, 0, 53, 121, // Skip to: 40641 +/* 9612 */ MCD_OPC_CheckField, 21, 1, 1, 47, 121, // Skip to: 40641 +/* 9618 */ MCD_OPC_Decode, 174, 1, 89, // Opcode: CMEQv8i8 +/* 9622 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9640 +/* 9626 */ MCD_OPC_CheckPredicate, 0, 35, 121, // Skip to: 40641 +/* 9630 */ MCD_OPC_CheckField, 21, 1, 1, 29, 121, // Skip to: 40641 +/* 9636 */ MCD_OPC_Decode, 201, 8, 109, // Opcode: MLSv8i8 +/* 9640 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 9671 +/* 9644 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 9647 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9659 +/* 9651 */ MCD_OPC_CheckPredicate, 0, 10, 121, // Skip to: 40641 +/* 9655 */ MCD_OPC_Decode, 231, 1, 90, // Opcode: CMLEv8i8rz +/* 9659 */ MCD_OPC_FilterValue, 33, 2, 121, // Skip to: 40641 +/* 9663 */ MCD_OPC_CheckPredicate, 0, 254, 120, // Skip to: 40641 +/* 9667 */ MCD_OPC_Decode, 179, 5, 90, // Opcode: FRINTXv2f32 +/* 9671 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9689 +/* 9675 */ MCD_OPC_CheckPredicate, 0, 242, 120, // Skip to: 40641 +/* 9679 */ MCD_OPC_CheckField, 21, 1, 1, 236, 120, // Skip to: 40641 +/* 9685 */ MCD_OPC_Decode, 152, 9, 89, // Opcode: PMULv8i8 +/* 9689 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9707 +/* 9693 */ MCD_OPC_CheckPredicate, 0, 224, 120, // Skip to: 40641 +/* 9697 */ MCD_OPC_CheckField, 21, 1, 1, 218, 120, // Skip to: 40641 +/* 9703 */ MCD_OPC_Decode, 250, 16, 105, // Opcode: UMLSLv8i8_v8i16 +/* 9707 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9725 +/* 9711 */ MCD_OPC_CheckPredicate, 0, 206, 120, // Skip to: 40641 +/* 9715 */ MCD_OPC_CheckField, 21, 1, 1, 200, 120, // Skip to: 40641 +/* 9721 */ MCD_OPC_Decode, 202, 16, 89, // Opcode: UMAXPv8i8 +/* 9725 */ MCD_OPC_FilterValue, 10, 39, 0, // Skip to: 9768 +/* 9729 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 9732 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 9744 +/* 9736 */ MCD_OPC_CheckPredicate, 0, 181, 120, // Skip to: 40641 +/* 9740 */ MCD_OPC_Decode, 195, 3, 90, // Opcode: FCVTNUv2f32 +/* 9744 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 9756 +/* 9748 */ MCD_OPC_CheckPredicate, 0, 169, 120, // Skip to: 40641 +/* 9752 */ MCD_OPC_Decode, 207, 16, 110, // Opcode: UMAXVv8i8v +/* 9756 */ MCD_OPC_FilterValue, 49, 161, 120, // Skip to: 40641 +/* 9760 */ MCD_OPC_CheckPredicate, 0, 157, 120, // Skip to: 40641 +/* 9764 */ MCD_OPC_Decode, 224, 16, 110, // Opcode: UMINVv8i8v +/* 9768 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9786 +/* 9772 */ MCD_OPC_CheckPredicate, 0, 145, 120, // Skip to: 40641 +/* 9776 */ MCD_OPC_CheckField, 21, 1, 1, 139, 120, // Skip to: 40641 +/* 9782 */ MCD_OPC_Decode, 219, 16, 89, // Opcode: UMINPv8i8 +/* 9786 */ MCD_OPC_FilterValue, 14, 131, 120, // Skip to: 40641 +/* 9790 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 9793 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9805 +/* 9797 */ MCD_OPC_CheckPredicate, 0, 120, 120, // Skip to: 40641 +/* 9801 */ MCD_OPC_Decode, 254, 8, 90, // Opcode: NEGv8i8 +/* 9805 */ MCD_OPC_FilterValue, 33, 112, 120, // Skip to: 40641 +/* 9809 */ MCD_OPC_CheckPredicate, 0, 108, 120, // Skip to: 40641 +/* 9813 */ MCD_OPC_Decode, 177, 3, 90, // Opcode: FCVTMUv2f32 +/* 9817 */ MCD_OPC_FilterValue, 3, 100, 120, // Skip to: 40641 +/* 9821 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 9824 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9842 +/* 9828 */ MCD_OPC_CheckPredicate, 0, 89, 120, // Skip to: 40641 +/* 9832 */ MCD_OPC_CheckField, 21, 1, 1, 83, 120, // Skip to: 40641 +/* 9838 */ MCD_OPC_Decode, 138, 17, 85, // Opcode: UMULLv8i8_v8i16 +/* 9842 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9860 +/* 9846 */ MCD_OPC_CheckPredicate, 0, 71, 120, // Skip to: 40641 +/* 9850 */ MCD_OPC_CheckField, 21, 1, 1, 65, 120, // Skip to: 40641 +/* 9856 */ MCD_OPC_Decode, 164, 4, 89, // Opcode: FMAXNMPv2f32 +/* 9860 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9878 +/* 9864 */ MCD_OPC_CheckPredicate, 0, 53, 120, // Skip to: 40641 +/* 9868 */ MCD_OPC_CheckField, 16, 6, 33, 47, 120, // Skip to: 40641 +/* 9874 */ MCD_OPC_Decode, 151, 3, 90, // Opcode: FCVTAUv2f32 +/* 9878 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9896 +/* 9882 */ MCD_OPC_CheckPredicate, 0, 35, 120, // Skip to: 40641 +/* 9886 */ MCD_OPC_CheckField, 21, 1, 1, 29, 120, // Skip to: 40641 +/* 9892 */ MCD_OPC_Decode, 201, 2, 89, // Opcode: FADDPv2f32 +/* 9896 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9914 +/* 9900 */ MCD_OPC_CheckPredicate, 0, 17, 120, // Skip to: 40641 +/* 9904 */ MCD_OPC_CheckField, 16, 6, 33, 11, 120, // Skip to: 40641 +/* 9910 */ MCD_OPC_Decode, 174, 16, 90, // Opcode: UCVTFv2f32 +/* 9914 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9932 +/* 9918 */ MCD_OPC_CheckPredicate, 0, 255, 119, // Skip to: 40641 +/* 9922 */ MCD_OPC_CheckField, 21, 1, 1, 249, 119, // Skip to: 40641 +/* 9928 */ MCD_OPC_Decode, 251, 4, 89, // Opcode: FMULv2f32 +/* 9932 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9950 +/* 9936 */ MCD_OPC_CheckPredicate, 0, 237, 119, // Skip to: 40641 +/* 9940 */ MCD_OPC_CheckField, 21, 1, 1, 231, 119, // Skip to: 40641 +/* 9946 */ MCD_OPC_Decode, 228, 2, 89, // Opcode: FCMGEv2f32 +/* 9950 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9968 +/* 9954 */ MCD_OPC_CheckPredicate, 0, 219, 119, // Skip to: 40641 +/* 9958 */ MCD_OPC_CheckField, 21, 1, 1, 213, 119, // Skip to: 40641 +/* 9964 */ MCD_OPC_Decode, 192, 2, 89, // Opcode: FACGEv2f32 +/* 9968 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9986 +/* 9972 */ MCD_OPC_CheckPredicate, 0, 201, 119, // Skip to: 40641 +/* 9976 */ MCD_OPC_CheckField, 21, 1, 1, 195, 119, // Skip to: 40641 +/* 9982 */ MCD_OPC_Decode, 174, 4, 89, // Opcode: FMAXPv2f32 +/* 9986 */ MCD_OPC_FilterValue, 15, 187, 119, // Skip to: 40641 +/* 9990 */ MCD_OPC_CheckPredicate, 0, 183, 119, // Skip to: 40641 +/* 9994 */ MCD_OPC_CheckField, 21, 1, 1, 177, 119, // Skip to: 40641 +/* 10000 */ MCD_OPC_Decode, 157, 4, 89, // Opcode: FDIVv2f32 +/* 10004 */ MCD_OPC_FilterValue, 2, 181, 6, // Skip to: 11725 +/* 10008 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 10011 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 10042 +/* 10015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10018 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10030 +/* 10022 */ MCD_OPC_CheckPredicate, 0, 151, 119, // Skip to: 40641 +/* 10026 */ MCD_OPC_Decode, 198, 15, 112, // Opcode: TBLv16i8One +/* 10030 */ MCD_OPC_FilterValue, 1, 143, 119, // Skip to: 40641 +/* 10034 */ MCD_OPC_CheckPredicate, 0, 139, 119, // Skip to: 40641 +/* 10038 */ MCD_OPC_Decode, 242, 9, 112, // Opcode: SADDLv16i8_v8i16 +/* 10042 */ MCD_OPC_FilterValue, 1, 90, 0, // Skip to: 10136 +/* 10046 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10049 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10124 +/* 10053 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 10056 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10112 +/* 10060 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 10063 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10100 +/* 10067 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 10070 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10088 +/* 10074 */ MCD_OPC_CheckPredicate, 0, 99, 119, // Skip to: 40641 +/* 10078 */ MCD_OPC_CheckField, 19, 1, 1, 93, 119, // Skip to: 40641 +/* 10084 */ MCD_OPC_Decode, 153, 2, 113, // Opcode: DUPv2i64lane +/* 10088 */ MCD_OPC_FilterValue, 1, 85, 119, // Skip to: 40641 +/* 10092 */ MCD_OPC_CheckPredicate, 0, 81, 119, // Skip to: 40641 +/* 10096 */ MCD_OPC_Decode, 157, 2, 114, // Opcode: DUPv4i32lane +/* 10100 */ MCD_OPC_FilterValue, 1, 73, 119, // Skip to: 40641 +/* 10104 */ MCD_OPC_CheckPredicate, 0, 69, 119, // Skip to: 40641 +/* 10108 */ MCD_OPC_Decode, 159, 2, 115, // Opcode: DUPv8i16lane +/* 10112 */ MCD_OPC_FilterValue, 1, 61, 119, // Skip to: 40641 +/* 10116 */ MCD_OPC_CheckPredicate, 0, 57, 119, // Skip to: 40641 +/* 10120 */ MCD_OPC_Decode, 149, 2, 116, // Opcode: DUPv16i8lane +/* 10124 */ MCD_OPC_FilterValue, 1, 49, 119, // Skip to: 40641 +/* 10128 */ MCD_OPC_CheckPredicate, 0, 45, 119, // Skip to: 40641 +/* 10132 */ MCD_OPC_Decode, 164, 10, 112, // Opcode: SHADDv16i8 +/* 10136 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10154 +/* 10140 */ MCD_OPC_CheckPredicate, 0, 33, 119, // Skip to: 40641 +/* 10144 */ MCD_OPC_CheckField, 16, 6, 32, 27, 119, // Skip to: 40641 +/* 10150 */ MCD_OPC_Decode, 179, 9, 117, // Opcode: REV64v16i8 +/* 10154 */ MCD_OPC_FilterValue, 3, 70, 0, // Skip to: 10228 +/* 10158 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10161 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 10216 +/* 10165 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10168 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 10180 +/* 10172 */ MCD_OPC_CheckPredicate, 0, 1, 119, // Skip to: 40641 +/* 10176 */ MCD_OPC_Decode, 148, 2, 118, // Opcode: DUPv16i8gpr +/* 10180 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 10192 +/* 10184 */ MCD_OPC_CheckPredicate, 0, 245, 118, // Skip to: 40641 +/* 10188 */ MCD_OPC_Decode, 158, 2, 118, // Opcode: DUPv8i16gpr +/* 10192 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 10204 +/* 10196 */ MCD_OPC_CheckPredicate, 0, 233, 118, // Skip to: 40641 +/* 10200 */ MCD_OPC_Decode, 156, 2, 118, // Opcode: DUPv4i32gpr +/* 10204 */ MCD_OPC_FilterValue, 8, 225, 118, // Skip to: 40641 +/* 10208 */ MCD_OPC_CheckPredicate, 0, 221, 118, // Skip to: 40641 +/* 10212 */ MCD_OPC_Decode, 152, 2, 119, // Opcode: DUPv2i64gpr +/* 10216 */ MCD_OPC_FilterValue, 1, 213, 118, // Skip to: 40641 +/* 10220 */ MCD_OPC_CheckPredicate, 0, 209, 118, // Skip to: 40641 +/* 10224 */ MCD_OPC_Decode, 160, 11, 112, // Opcode: SQADDv16i8 +/* 10228 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 10259 +/* 10232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10235 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10247 +/* 10239 */ MCD_OPC_CheckPredicate, 0, 190, 118, // Skip to: 40641 +/* 10243 */ MCD_OPC_Decode, 208, 15, 120, // Opcode: TBXv16i8One +/* 10247 */ MCD_OPC_FilterValue, 1, 182, 118, // Skip to: 40641 +/* 10251 */ MCD_OPC_CheckPredicate, 0, 178, 118, // Skip to: 40641 +/* 10255 */ MCD_OPC_Decode, 248, 9, 112, // Opcode: SADDWv16i8_v8i16 +/* 10259 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 10277 +/* 10263 */ MCD_OPC_CheckPredicate, 0, 166, 118, // Skip to: 40641 +/* 10267 */ MCD_OPC_CheckField, 21, 1, 1, 160, 118, // Skip to: 40641 +/* 10273 */ MCD_OPC_Decode, 223, 12, 112, // Opcode: SRHADDv16i8 +/* 10277 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 10314 +/* 10281 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10284 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10296 +/* 10288 */ MCD_OPC_CheckPredicate, 0, 141, 118, // Skip to: 40641 +/* 10292 */ MCD_OPC_Decode, 180, 18, 112, // Opcode: UZP1v16i8 +/* 10296 */ MCD_OPC_FilterValue, 1, 133, 118, // Skip to: 40641 +/* 10300 */ MCD_OPC_CheckPredicate, 0, 129, 118, // Skip to: 40641 +/* 10304 */ MCD_OPC_CheckField, 16, 5, 0, 123, 118, // Skip to: 40641 +/* 10310 */ MCD_OPC_Decode, 172, 9, 117, // Opcode: REV16v16i8 +/* 10314 */ MCD_OPC_FilterValue, 7, 89, 0, // Skip to: 10407 +/* 10318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10321 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10396 +/* 10325 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 10328 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10384 +/* 10332 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 10335 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10372 +/* 10339 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 10342 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10360 +/* 10346 */ MCD_OPC_CheckPredicate, 0, 83, 118, // Skip to: 40641 +/* 10350 */ MCD_OPC_CheckField, 19, 1, 1, 77, 118, // Skip to: 40641 +/* 10356 */ MCD_OPC_Decode, 214, 5, 121, // Opcode: INSvi64gpr +/* 10360 */ MCD_OPC_FilterValue, 1, 69, 118, // Skip to: 40641 +/* 10364 */ MCD_OPC_CheckPredicate, 0, 65, 118, // Skip to: 40641 +/* 10368 */ MCD_OPC_Decode, 212, 5, 122, // Opcode: INSvi32gpr +/* 10372 */ MCD_OPC_FilterValue, 1, 57, 118, // Skip to: 40641 +/* 10376 */ MCD_OPC_CheckPredicate, 0, 53, 118, // Skip to: 40641 +/* 10380 */ MCD_OPC_Decode, 210, 5, 123, // Opcode: INSvi16gpr +/* 10384 */ MCD_OPC_FilterValue, 1, 45, 118, // Skip to: 40641 +/* 10388 */ MCD_OPC_CheckPredicate, 0, 41, 118, // Skip to: 40641 +/* 10392 */ MCD_OPC_Decode, 216, 5, 124, // Opcode: INSvi8gpr +/* 10396 */ MCD_OPC_FilterValue, 1, 33, 118, // Skip to: 40641 +/* 10400 */ MCD_OPC_CheckPredicate, 0, 29, 118, // Skip to: 40641 +/* 10404 */ MCD_OPC_Decode, 99, 112, // Opcode: ANDv16i8 +/* 10407 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 10438 +/* 10411 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10414 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10426 +/* 10418 */ MCD_OPC_CheckPredicate, 0, 11, 118, // Skip to: 40641 +/* 10422 */ MCD_OPC_Decode, 200, 15, 125, // Opcode: TBLv16i8Two +/* 10426 */ MCD_OPC_FilterValue, 1, 3, 118, // Skip to: 40641 +/* 10430 */ MCD_OPC_CheckPredicate, 0, 255, 117, // Skip to: 40641 +/* 10434 */ MCD_OPC_Decode, 163, 13, 112, // Opcode: SSUBLv16i8_v8i16 +/* 10438 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 10456 +/* 10442 */ MCD_OPC_CheckPredicate, 0, 243, 117, // Skip to: 40641 +/* 10446 */ MCD_OPC_CheckField, 21, 1, 1, 237, 117, // Skip to: 40641 +/* 10452 */ MCD_OPC_Decode, 190, 10, 112, // Opcode: SHSUBv16i8 +/* 10456 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 10506 +/* 10460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10475 +/* 10467 */ MCD_OPC_CheckPredicate, 0, 218, 117, // Skip to: 40641 +/* 10471 */ MCD_OPC_Decode, 221, 15, 112, // Opcode: TRN1v16i8 +/* 10475 */ MCD_OPC_FilterValue, 1, 210, 117, // Skip to: 40641 +/* 10479 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10482 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10494 +/* 10486 */ MCD_OPC_CheckPredicate, 0, 199, 117, // Skip to: 40641 +/* 10490 */ MCD_OPC_Decode, 231, 9, 117, // Opcode: SADDLPv16i8_v8i16 +/* 10494 */ MCD_OPC_FilterValue, 1, 191, 117, // Skip to: 40641 +/* 10498 */ MCD_OPC_CheckPredicate, 0, 187, 117, // Skip to: 40641 +/* 10502 */ MCD_OPC_Decode, 194, 18, 126, // Opcode: XTNv16i8 +/* 10506 */ MCD_OPC_FilterValue, 11, 73, 0, // Skip to: 10583 +/* 10510 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10513 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 10571 +/* 10517 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 10520 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 10558 +/* 10524 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 10527 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10545 +/* 10531 */ MCD_OPC_CheckPredicate, 0, 154, 117, // Skip to: 40641 +/* 10535 */ MCD_OPC_CheckField, 18, 1, 1, 148, 117, // Skip to: 40641 +/* 10541 */ MCD_OPC_Decode, 134, 11, 127, // Opcode: SMOVvi32to64 +/* 10545 */ MCD_OPC_FilterValue, 1, 140, 117, // Skip to: 40641 +/* 10549 */ MCD_OPC_CheckPredicate, 0, 136, 117, // Skip to: 40641 +/* 10553 */ MCD_OPC_Decode, 133, 11, 128, 1, // Opcode: SMOVvi16to64 +/* 10558 */ MCD_OPC_FilterValue, 1, 127, 117, // Skip to: 40641 +/* 10562 */ MCD_OPC_CheckPredicate, 0, 123, 117, // Skip to: 40641 +/* 10566 */ MCD_OPC_Decode, 136, 11, 129, 1, // Opcode: SMOVvi8to64 +/* 10571 */ MCD_OPC_FilterValue, 1, 114, 117, // Skip to: 40641 +/* 10575 */ MCD_OPC_CheckPredicate, 0, 110, 117, // Skip to: 40641 +/* 10579 */ MCD_OPC_Decode, 194, 12, 112, // Opcode: SQSUBv16i8 +/* 10583 */ MCD_OPC_FilterValue, 12, 28, 0, // Skip to: 10615 +/* 10587 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10590 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10603 +/* 10594 */ MCD_OPC_CheckPredicate, 0, 91, 117, // Skip to: 40641 +/* 10598 */ MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: TBXv16i8Two +/* 10603 */ MCD_OPC_FilterValue, 1, 82, 117, // Skip to: 40641 +/* 10607 */ MCD_OPC_CheckPredicate, 0, 78, 117, // Skip to: 40641 +/* 10611 */ MCD_OPC_Decode, 169, 13, 112, // Opcode: SSUBWv16i8_v8i16 +/* 10615 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 10633 +/* 10619 */ MCD_OPC_CheckPredicate, 0, 66, 117, // Skip to: 40641 +/* 10623 */ MCD_OPC_CheckField, 21, 1, 1, 60, 117, // Skip to: 40641 +/* 10629 */ MCD_OPC_Decode, 192, 1, 112, // Opcode: CMGTv16i8 +/* 10633 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 10684 +/* 10637 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10640 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10652 +/* 10644 */ MCD_OPC_CheckPredicate, 0, 41, 117, // Skip to: 40641 +/* 10648 */ MCD_OPC_Decode, 200, 18, 112, // Opcode: ZIP1v16i8 +/* 10652 */ MCD_OPC_FilterValue, 1, 33, 117, // Skip to: 40641 +/* 10656 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10659 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10671 +/* 10663 */ MCD_OPC_CheckPredicate, 0, 22, 117, // Skip to: 40641 +/* 10667 */ MCD_OPC_Decode, 183, 15, 126, // Opcode: SUQADDv16i8 +/* 10671 */ MCD_OPC_FilterValue, 16, 14, 117, // Skip to: 40641 +/* 10675 */ MCD_OPC_CheckPredicate, 0, 10, 117, // Skip to: 40641 +/* 10679 */ MCD_OPC_Decode, 237, 9, 131, 1, // Opcode: SADDLVv16i8v +/* 10684 */ MCD_OPC_FilterValue, 15, 34, 0, // Skip to: 10722 +/* 10688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10691 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10710 +/* 10695 */ MCD_OPC_CheckPredicate, 0, 246, 116, // Skip to: 40641 +/* 10699 */ MCD_OPC_CheckField, 16, 4, 8, 240, 116, // Skip to: 40641 +/* 10705 */ MCD_OPC_Decode, 253, 16, 132, 1, // Opcode: UMOVvi64 +/* 10710 */ MCD_OPC_FilterValue, 1, 231, 116, // Skip to: 40641 +/* 10714 */ MCD_OPC_CheckPredicate, 0, 227, 116, // Skip to: 40641 +/* 10718 */ MCD_OPC_Decode, 176, 1, 112, // Opcode: CMGEv16i8 +/* 10722 */ MCD_OPC_FilterValue, 16, 27, 0, // Skip to: 10753 +/* 10726 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10729 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10742 +/* 10733 */ MCD_OPC_CheckPredicate, 0, 208, 116, // Skip to: 40641 +/* 10737 */ MCD_OPC_Decode, 199, 15, 133, 1, // Opcode: TBLv16i8Three +/* 10742 */ MCD_OPC_FilterValue, 1, 199, 116, // Skip to: 40641 +/* 10746 */ MCD_OPC_CheckPredicate, 0, 195, 116, // Skip to: 40641 +/* 10750 */ MCD_OPC_Decode, 38, 120, // Opcode: ADDHNv8i16_v16i8 +/* 10753 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 10771 +/* 10757 */ MCD_OPC_CheckPredicate, 0, 184, 116, // Skip to: 40641 +/* 10761 */ MCD_OPC_CheckField, 21, 1, 1, 178, 116, // Skip to: 40641 +/* 10767 */ MCD_OPC_Decode, 139, 13, 112, // Opcode: SSHLv16i8 +/* 10771 */ MCD_OPC_FilterValue, 18, 38, 0, // Skip to: 10813 +/* 10775 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 10778 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 10790 +/* 10782 */ MCD_OPC_CheckPredicate, 0, 159, 116, // Skip to: 40641 +/* 10786 */ MCD_OPC_Decode, 146, 1, 117, // Opcode: CLSv16i8 +/* 10790 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 10802 +/* 10794 */ MCD_OPC_CheckPredicate, 0, 147, 116, // Skip to: 40641 +/* 10798 */ MCD_OPC_Decode, 205, 12, 126, // Opcode: SQXTNv16i8 +/* 10802 */ MCD_OPC_FilterValue, 40, 139, 116, // Skip to: 40641 +/* 10806 */ MCD_OPC_CheckPredicate, 1, 135, 116, // Skip to: 40641 +/* 10810 */ MCD_OPC_Decode, 84, 126, // Opcode: AESErr +/* 10813 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 10831 +/* 10817 */ MCD_OPC_CheckPredicate, 0, 124, 116, // Skip to: 40641 +/* 10821 */ MCD_OPC_CheckField, 21, 1, 1, 118, 116, // Skip to: 40641 +/* 10827 */ MCD_OPC_Decode, 158, 12, 112, // Opcode: SQSHLv16i8 +/* 10831 */ MCD_OPC_FilterValue, 20, 28, 0, // Skip to: 10863 +/* 10835 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10838 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10851 +/* 10842 */ MCD_OPC_CheckPredicate, 0, 99, 116, // Skip to: 40641 +/* 10846 */ MCD_OPC_Decode, 209, 15, 134, 1, // Opcode: TBXv16i8Three +/* 10851 */ MCD_OPC_FilterValue, 1, 90, 116, // Skip to: 40641 +/* 10855 */ MCD_OPC_CheckPredicate, 0, 86, 116, // Skip to: 40641 +/* 10859 */ MCD_OPC_Decode, 201, 9, 120, // Opcode: SABALv16i8_v8i16 +/* 10863 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 10881 +/* 10867 */ MCD_OPC_CheckPredicate, 0, 74, 116, // Skip to: 40641 +/* 10871 */ MCD_OPC_CheckField, 21, 1, 1, 68, 116, // Skip to: 40641 +/* 10877 */ MCD_OPC_Decode, 237, 12, 112, // Opcode: SRSHLv16i8 +/* 10881 */ MCD_OPC_FilterValue, 22, 45, 0, // Skip to: 10930 +/* 10885 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10888 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10900 +/* 10892 */ MCD_OPC_CheckPredicate, 0, 49, 116, // Skip to: 40641 +/* 10896 */ MCD_OPC_Decode, 187, 18, 112, // Opcode: UZP2v16i8 +/* 10900 */ MCD_OPC_FilterValue, 1, 41, 116, // Skip to: 40641 +/* 10904 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10907 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10919 +/* 10911 */ MCD_OPC_CheckPredicate, 0, 30, 116, // Skip to: 40641 +/* 10915 */ MCD_OPC_Decode, 248, 1, 117, // Opcode: CNTv16i8 +/* 10919 */ MCD_OPC_FilterValue, 8, 22, 116, // Skip to: 40641 +/* 10923 */ MCD_OPC_CheckPredicate, 1, 18, 116, // Skip to: 40641 +/* 10927 */ MCD_OPC_Decode, 83, 126, // Opcode: AESDrr +/* 10930 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 10948 +/* 10934 */ MCD_OPC_CheckPredicate, 0, 7, 116, // Skip to: 40641 +/* 10938 */ MCD_OPC_CheckField, 21, 1, 1, 1, 116, // Skip to: 40641 +/* 10944 */ MCD_OPC_Decode, 242, 11, 112, // Opcode: SQRSHLv16i8 +/* 10948 */ MCD_OPC_FilterValue, 24, 28, 0, // Skip to: 10980 +/* 10952 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 10955 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10968 +/* 10959 */ MCD_OPC_CheckPredicate, 0, 238, 115, // Skip to: 40641 +/* 10963 */ MCD_OPC_Decode, 197, 15, 135, 1, // Opcode: TBLv16i8Four +/* 10968 */ MCD_OPC_FilterValue, 1, 229, 115, // Skip to: 40641 +/* 10972 */ MCD_OPC_CheckPredicate, 0, 225, 115, // Skip to: 40641 +/* 10976 */ MCD_OPC_Decode, 155, 15, 120, // Opcode: SUBHNv8i16_v16i8 +/* 10980 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 10998 +/* 10984 */ MCD_OPC_CheckPredicate, 0, 213, 115, // Skip to: 40641 +/* 10988 */ MCD_OPC_CheckField, 21, 1, 1, 207, 115, // Skip to: 40641 +/* 10994 */ MCD_OPC_Decode, 216, 10, 112, // Opcode: SMAXv16i8 +/* 10998 */ MCD_OPC_FilterValue, 26, 57, 0, // Skip to: 11059 +/* 11002 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 11005 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11017 +/* 11009 */ MCD_OPC_CheckPredicate, 0, 188, 115, // Skip to: 40641 +/* 11013 */ MCD_OPC_Decode, 228, 15, 112, // Opcode: TRN2v16i8 +/* 11017 */ MCD_OPC_FilterValue, 1, 180, 115, // Skip to: 40641 +/* 11021 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 11024 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11036 +/* 11028 */ MCD_OPC_CheckPredicate, 0, 169, 115, // Skip to: 40641 +/* 11032 */ MCD_OPC_Decode, 225, 9, 126, // Opcode: SADALPv16i8_v8i16 +/* 11036 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11048 +/* 11040 */ MCD_OPC_CheckPredicate, 0, 157, 115, // Skip to: 40641 +/* 11044 */ MCD_OPC_Decode, 201, 3, 126, // Opcode: FCVTNv8i16 +/* 11048 */ MCD_OPC_FilterValue, 8, 149, 115, // Skip to: 40641 +/* 11052 */ MCD_OPC_CheckPredicate, 1, 145, 115, // Skip to: 40641 +/* 11056 */ MCD_OPC_Decode, 86, 117, // Opcode: AESMCrr +/* 11059 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 11077 +/* 11063 */ MCD_OPC_CheckPredicate, 0, 134, 115, // Skip to: 40641 +/* 11067 */ MCD_OPC_CheckField, 21, 1, 1, 128, 115, // Skip to: 40641 +/* 11073 */ MCD_OPC_Decode, 234, 10, 112, // Opcode: SMINv16i8 +/* 11077 */ MCD_OPC_FilterValue, 28, 28, 0, // Skip to: 11109 +/* 11081 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 11084 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11097 +/* 11088 */ MCD_OPC_CheckPredicate, 0, 109, 115, // Skip to: 40641 +/* 11092 */ MCD_OPC_Decode, 207, 15, 136, 1, // Opcode: TBXv16i8Four +/* 11097 */ MCD_OPC_FilterValue, 1, 100, 115, // Skip to: 40641 +/* 11101 */ MCD_OPC_CheckPredicate, 0, 96, 115, // Skip to: 40641 +/* 11105 */ MCD_OPC_Decode, 213, 9, 112, // Opcode: SABDLv16i8_v8i16 +/* 11109 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 11127 +/* 11113 */ MCD_OPC_CheckPredicate, 0, 84, 115, // Skip to: 40641 +/* 11117 */ MCD_OPC_CheckField, 21, 1, 1, 78, 115, // Skip to: 40641 +/* 11123 */ MCD_OPC_Decode, 219, 9, 112, // Opcode: SABDv16i8 +/* 11127 */ MCD_OPC_FilterValue, 30, 57, 0, // Skip to: 11188 +/* 11131 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 11134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11146 +/* 11138 */ MCD_OPC_CheckPredicate, 0, 59, 115, // Skip to: 40641 +/* 11142 */ MCD_OPC_Decode, 207, 18, 112, // Opcode: ZIP2v16i8 +/* 11146 */ MCD_OPC_FilterValue, 1, 51, 115, // Skip to: 40641 +/* 11150 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 11153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11165 +/* 11157 */ MCD_OPC_CheckPredicate, 0, 40, 115, // Skip to: 40641 +/* 11161 */ MCD_OPC_Decode, 149, 11, 117, // Opcode: SQABSv16i8 +/* 11165 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11177 +/* 11169 */ MCD_OPC_CheckPredicate, 0, 28, 115, // Skip to: 40641 +/* 11173 */ MCD_OPC_Decode, 161, 3, 117, // Opcode: FCVTLv8i16 +/* 11177 */ MCD_OPC_FilterValue, 8, 20, 115, // Skip to: 40641 +/* 11181 */ MCD_OPC_CheckPredicate, 1, 16, 115, // Skip to: 40641 +/* 11185 */ MCD_OPC_Decode, 85, 117, // Opcode: AESIMCrr +/* 11188 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 11206 +/* 11192 */ MCD_OPC_CheckPredicate, 0, 5, 115, // Skip to: 40641 +/* 11196 */ MCD_OPC_CheckField, 21, 1, 1, 255, 114, // Skip to: 40641 +/* 11202 */ MCD_OPC_Decode, 207, 9, 120, // Opcode: SABAv16i8 +/* 11206 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 11224 +/* 11210 */ MCD_OPC_CheckPredicate, 0, 243, 114, // Skip to: 40641 +/* 11214 */ MCD_OPC_CheckField, 21, 1, 1, 237, 114, // Skip to: 40641 +/* 11220 */ MCD_OPC_Decode, 240, 10, 120, // Opcode: SMLALv16i8_v8i16 +/* 11224 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 11241 +/* 11228 */ MCD_OPC_CheckPredicate, 0, 225, 114, // Skip to: 40641 +/* 11232 */ MCD_OPC_CheckField, 21, 1, 1, 219, 114, // Skip to: 40641 +/* 11238 */ MCD_OPC_Decode, 71, 112, // Opcode: ADDv16i8 +/* 11241 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 11272 +/* 11245 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 11248 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11260 +/* 11252 */ MCD_OPC_CheckPredicate, 0, 201, 114, // Skip to: 40641 +/* 11256 */ MCD_OPC_Decode, 193, 1, 117, // Opcode: CMGTv16i8rz +/* 11260 */ MCD_OPC_FilterValue, 33, 193, 114, // Skip to: 40641 +/* 11264 */ MCD_OPC_CheckPredicate, 0, 189, 114, // Skip to: 40641 +/* 11268 */ MCD_OPC_Decode, 171, 5, 117, // Opcode: FRINTNv4f32 +/* 11272 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 11290 +/* 11276 */ MCD_OPC_CheckPredicate, 0, 177, 114, // Skip to: 40641 +/* 11280 */ MCD_OPC_CheckField, 21, 1, 1, 171, 114, // Skip to: 40641 +/* 11286 */ MCD_OPC_Decode, 240, 1, 112, // Opcode: CMTSTv16i8 +/* 11290 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 11308 +/* 11294 */ MCD_OPC_CheckPredicate, 0, 159, 114, // Skip to: 40641 +/* 11298 */ MCD_OPC_CheckField, 21, 1, 1, 153, 114, // Skip to: 40641 +/* 11304 */ MCD_OPC_Decode, 182, 8, 120, // Opcode: MLAv16i8 +/* 11308 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 11339 +/* 11312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 11315 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11327 +/* 11319 */ MCD_OPC_CheckPredicate, 0, 134, 114, // Skip to: 40641 +/* 11323 */ MCD_OPC_Decode, 161, 1, 117, // Opcode: CMEQv16i8rz +/* 11327 */ MCD_OPC_FilterValue, 33, 126, 114, // Skip to: 40641 +/* 11331 */ MCD_OPC_CheckPredicate, 0, 122, 114, // Skip to: 40641 +/* 11335 */ MCD_OPC_Decode, 166, 5, 117, // Opcode: FRINTMv4f32 +/* 11339 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 11357 +/* 11343 */ MCD_OPC_CheckPredicate, 0, 110, 114, // Skip to: 40641 +/* 11347 */ MCD_OPC_CheckField, 21, 1, 1, 104, 114, // Skip to: 40641 +/* 11353 */ MCD_OPC_Decode, 231, 8, 112, // Opcode: MULv16i8 +/* 11357 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 11375 +/* 11361 */ MCD_OPC_CheckPredicate, 0, 92, 114, // Skip to: 40641 +/* 11365 */ MCD_OPC_CheckField, 21, 1, 1, 86, 114, // Skip to: 40641 +/* 11371 */ MCD_OPC_Decode, 250, 10, 120, // Opcode: SMLSLv16i8_v8i16 +/* 11375 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 11393 +/* 11379 */ MCD_OPC_CheckPredicate, 0, 74, 114, // Skip to: 40641 +/* 11383 */ MCD_OPC_CheckField, 21, 1, 1, 68, 114, // Skip to: 40641 +/* 11389 */ MCD_OPC_Decode, 205, 10, 112, // Opcode: SMAXPv16i8 +/* 11393 */ MCD_OPC_FilterValue, 42, 53, 0, // Skip to: 11450 +/* 11397 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 11400 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11412 +/* 11404 */ MCD_OPC_CheckPredicate, 0, 49, 114, // Skip to: 40641 +/* 11408 */ MCD_OPC_Decode, 232, 1, 117, // Opcode: CMLTv16i8rz +/* 11412 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11424 +/* 11416 */ MCD_OPC_CheckPredicate, 0, 37, 114, // Skip to: 40641 +/* 11420 */ MCD_OPC_Decode, 188, 3, 117, // Opcode: FCVTNSv4f32 +/* 11424 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 11437 +/* 11428 */ MCD_OPC_CheckPredicate, 0, 25, 114, // Skip to: 40641 +/* 11432 */ MCD_OPC_Decode, 211, 10, 137, 1, // Opcode: SMAXVv16i8v +/* 11437 */ MCD_OPC_FilterValue, 49, 16, 114, // Skip to: 40641 +/* 11441 */ MCD_OPC_CheckPredicate, 0, 12, 114, // Skip to: 40641 +/* 11445 */ MCD_OPC_Decode, 229, 10, 137, 1, // Opcode: SMINVv16i8v +/* 11450 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 11468 +/* 11454 */ MCD_OPC_CheckPredicate, 0, 255, 113, // Skip to: 40641 +/* 11458 */ MCD_OPC_CheckField, 21, 1, 1, 249, 113, // Skip to: 40641 +/* 11464 */ MCD_OPC_Decode, 223, 10, 112, // Opcode: SMINPv16i8 +/* 11468 */ MCD_OPC_FilterValue, 46, 38, 0, // Skip to: 11510 +/* 11472 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 11475 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 11486 +/* 11479 */ MCD_OPC_CheckPredicate, 0, 230, 113, // Skip to: 40641 +/* 11483 */ MCD_OPC_Decode, 22, 117, // Opcode: ABSv16i8 +/* 11486 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11498 +/* 11490 */ MCD_OPC_CheckPredicate, 0, 219, 113, // Skip to: 40641 +/* 11494 */ MCD_OPC_Decode, 170, 3, 117, // Opcode: FCVTMSv4f32 +/* 11498 */ MCD_OPC_FilterValue, 49, 211, 113, // Skip to: 40641 +/* 11502 */ MCD_OPC_CheckPredicate, 0, 207, 113, // Skip to: 40641 +/* 11506 */ MCD_OPC_Decode, 57, 137, 1, // Opcode: ADDVv16i8v +/* 11510 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 11527 +/* 11514 */ MCD_OPC_CheckPredicate, 0, 195, 113, // Skip to: 40641 +/* 11518 */ MCD_OPC_CheckField, 21, 1, 1, 189, 113, // Skip to: 40641 +/* 11524 */ MCD_OPC_Decode, 40, 112, // Opcode: ADDPv16i8 +/* 11527 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 11545 +/* 11531 */ MCD_OPC_CheckPredicate, 0, 178, 113, // Skip to: 40641 +/* 11535 */ MCD_OPC_CheckField, 21, 1, 1, 172, 113, // Skip to: 40641 +/* 11541 */ MCD_OPC_Decode, 139, 11, 112, // Opcode: SMULLv16i8_v8i16 +/* 11545 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 11563 +/* 11549 */ MCD_OPC_CheckPredicate, 0, 160, 113, // Skip to: 40641 +/* 11553 */ MCD_OPC_CheckField, 21, 1, 1, 154, 113, // Skip to: 40641 +/* 11559 */ MCD_OPC_Decode, 173, 4, 112, // Opcode: FMAXNMv4f32 +/* 11563 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 11581 +/* 11567 */ MCD_OPC_CheckPredicate, 0, 142, 113, // Skip to: 40641 +/* 11571 */ MCD_OPC_CheckField, 16, 6, 33, 136, 113, // Skip to: 40641 +/* 11577 */ MCD_OPC_Decode, 144, 3, 117, // Opcode: FCVTASv4f32 +/* 11581 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 11599 +/* 11585 */ MCD_OPC_CheckPredicate, 0, 124, 113, // Skip to: 40641 +/* 11589 */ MCD_OPC_CheckField, 21, 1, 1, 118, 113, // Skip to: 40641 +/* 11595 */ MCD_OPC_Decode, 212, 4, 120, // Opcode: FMLAv4f32 +/* 11599 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 11617 +/* 11603 */ MCD_OPC_CheckPredicate, 0, 106, 113, // Skip to: 40641 +/* 11607 */ MCD_OPC_CheckField, 21, 1, 1, 100, 113, // Skip to: 40641 +/* 11613 */ MCD_OPC_Decode, 209, 2, 112, // Opcode: FADDv4f32 +/* 11617 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 11635 +/* 11621 */ MCD_OPC_CheckPredicate, 0, 88, 113, // Skip to: 40641 +/* 11625 */ MCD_OPC_CheckField, 16, 6, 33, 82, 113, // Skip to: 40641 +/* 11631 */ MCD_OPC_Decode, 148, 10, 117, // Opcode: SCVTFv4f32 +/* 11635 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 11653 +/* 11639 */ MCD_OPC_CheckPredicate, 0, 70, 113, // Skip to: 40641 +/* 11643 */ MCD_OPC_CheckField, 21, 1, 1, 64, 113, // Skip to: 40641 +/* 11649 */ MCD_OPC_Decode, 247, 4, 112, // Opcode: FMULXv4f32 +/* 11653 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 11671 +/* 11657 */ MCD_OPC_CheckPredicate, 0, 52, 113, // Skip to: 40641 +/* 11661 */ MCD_OPC_CheckField, 21, 1, 1, 46, 113, // Skip to: 40641 +/* 11667 */ MCD_OPC_Decode, 147, 9, 112, // Opcode: PMULLv16i8 +/* 11671 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 11689 +/* 11675 */ MCD_OPC_CheckPredicate, 0, 34, 113, // Skip to: 40641 +/* 11679 */ MCD_OPC_CheckField, 21, 1, 1, 28, 113, // Skip to: 40641 +/* 11685 */ MCD_OPC_Decode, 222, 2, 112, // Opcode: FCMEQv4f32 +/* 11689 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 11707 +/* 11693 */ MCD_OPC_CheckPredicate, 0, 16, 113, // Skip to: 40641 +/* 11697 */ MCD_OPC_CheckField, 21, 1, 1, 10, 113, // Skip to: 40641 +/* 11703 */ MCD_OPC_Decode, 183, 4, 112, // Opcode: FMAXv4f32 +/* 11707 */ MCD_OPC_FilterValue, 63, 2, 113, // Skip to: 40641 +/* 11711 */ MCD_OPC_CheckPredicate, 0, 254, 112, // Skip to: 40641 +/* 11715 */ MCD_OPC_CheckField, 21, 1, 1, 248, 112, // Skip to: 40641 +/* 11721 */ MCD_OPC_Decode, 149, 5, 112, // Opcode: FRECPSv4f32 +/* 11725 */ MCD_OPC_FilterValue, 3, 240, 112, // Skip to: 40641 +/* 11729 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 11732 */ MCD_OPC_FilterValue, 0, 60, 2, // Skip to: 12308 +/* 11736 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 11739 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 12040 +/* 11743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 11746 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11759 +/* 11750 */ MCD_OPC_CheckPredicate, 0, 215, 112, // Skip to: 40641 +/* 11754 */ MCD_OPC_Decode, 177, 2, 138, 1, // Opcode: EXTv16i8 +/* 11759 */ MCD_OPC_FilterValue, 1, 206, 112, // Skip to: 40641 +/* 11763 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 11766 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11778 +/* 11770 */ MCD_OPC_CheckPredicate, 0, 195, 112, // Skip to: 40641 +/* 11774 */ MCD_OPC_Decode, 148, 16, 112, // Opcode: UADDLv16i8_v8i16 +/* 11778 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11796 +/* 11782 */ MCD_OPC_CheckPredicate, 0, 183, 112, // Skip to: 40641 +/* 11786 */ MCD_OPC_CheckField, 16, 5, 0, 177, 112, // Skip to: 40641 +/* 11792 */ MCD_OPC_Decode, 175, 9, 117, // Opcode: REV32v16i8 +/* 11796 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 11808 +/* 11800 */ MCD_OPC_CheckPredicate, 0, 165, 112, // Skip to: 40641 +/* 11804 */ MCD_OPC_Decode, 154, 16, 112, // Opcode: UADDWv16i8_v8i16 +/* 11808 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11820 +/* 11812 */ MCD_OPC_CheckPredicate, 0, 153, 112, // Skip to: 40641 +/* 11816 */ MCD_OPC_Decode, 168, 18, 112, // Opcode: USUBLv16i8_v8i16 +/* 11820 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 11851 +/* 11824 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 11827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11839 +/* 11831 */ MCD_OPC_CheckPredicate, 0, 134, 112, // Skip to: 40641 +/* 11835 */ MCD_OPC_Decode, 137, 16, 117, // Opcode: UADDLPv16i8_v8i16 +/* 11839 */ MCD_OPC_FilterValue, 1, 126, 112, // Skip to: 40641 +/* 11843 */ MCD_OPC_CheckPredicate, 0, 122, 112, // Skip to: 40641 +/* 11847 */ MCD_OPC_Decode, 214, 12, 126, // Opcode: SQXTUNv16i8 +/* 11851 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 11863 +/* 11855 */ MCD_OPC_CheckPredicate, 0, 110, 112, // Skip to: 40641 +/* 11859 */ MCD_OPC_Decode, 174, 18, 112, // Opcode: USUBWv16i8_v8i16 +/* 11863 */ MCD_OPC_FilterValue, 7, 40, 0, // Skip to: 11907 +/* 11867 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 11870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11882 +/* 11874 */ MCD_OPC_CheckPredicate, 0, 91, 112, // Skip to: 40641 +/* 11878 */ MCD_OPC_Decode, 149, 18, 126, // Opcode: USQADDv16i8 +/* 11882 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11894 +/* 11886 */ MCD_OPC_CheckPredicate, 0, 79, 112, // Skip to: 40641 +/* 11890 */ MCD_OPC_Decode, 170, 10, 117, // Opcode: SHLLv16i8 +/* 11894 */ MCD_OPC_FilterValue, 16, 71, 112, // Skip to: 40641 +/* 11898 */ MCD_OPC_CheckPredicate, 0, 67, 112, // Skip to: 40641 +/* 11902 */ MCD_OPC_Decode, 143, 16, 131, 1, // Opcode: UADDLVv16i8v +/* 11907 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11919 +/* 11911 */ MCD_OPC_CheckPredicate, 0, 54, 112, // Skip to: 40641 +/* 11915 */ MCD_OPC_Decode, 162, 9, 120, // Opcode: RADDHNv8i16_v16i8 +/* 11919 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 11950 +/* 11923 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 11926 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11938 +/* 11930 */ MCD_OPC_CheckPredicate, 0, 35, 112, // Skip to: 40641 +/* 11934 */ MCD_OPC_Decode, 154, 1, 117, // Opcode: CLZv16i8 +/* 11938 */ MCD_OPC_FilterValue, 1, 27, 112, // Skip to: 40641 +/* 11942 */ MCD_OPC_CheckPredicate, 0, 23, 112, // Skip to: 40641 +/* 11946 */ MCD_OPC_Decode, 212, 17, 126, // Opcode: UQXTNv16i8 +/* 11950 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11962 +/* 11954 */ MCD_OPC_CheckPredicate, 0, 11, 112, // Skip to: 40641 +/* 11958 */ MCD_OPC_Decode, 235, 15, 120, // Opcode: UABALv16i8_v8i16 +/* 11962 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 11980 +/* 11966 */ MCD_OPC_CheckPredicate, 0, 255, 111, // Skip to: 40641 +/* 11970 */ MCD_OPC_CheckField, 16, 5, 0, 249, 111, // Skip to: 40641 +/* 11976 */ MCD_OPC_Decode, 255, 8, 117, // Opcode: NOTv16i8 +/* 11980 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11992 +/* 11984 */ MCD_OPC_CheckPredicate, 0, 237, 111, // Skip to: 40641 +/* 11988 */ MCD_OPC_Decode, 199, 9, 120, // Opcode: RSUBHNv8i16_v16i8 +/* 11992 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12010 +/* 11996 */ MCD_OPC_CheckPredicate, 0, 225, 111, // Skip to: 40641 +/* 12000 */ MCD_OPC_CheckField, 16, 5, 0, 219, 111, // Skip to: 40641 +/* 12006 */ MCD_OPC_Decode, 131, 16, 126, // Opcode: UADALPv16i8_v8i16 +/* 12010 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12022 +/* 12014 */ MCD_OPC_CheckPredicate, 0, 207, 111, // Skip to: 40641 +/* 12018 */ MCD_OPC_Decode, 247, 15, 112, // Opcode: UABDLv16i8_v8i16 +/* 12022 */ MCD_OPC_FilterValue, 15, 199, 111, // Skip to: 40641 +/* 12026 */ MCD_OPC_CheckPredicate, 0, 195, 111, // Skip to: 40641 +/* 12030 */ MCD_OPC_CheckField, 16, 5, 0, 189, 111, // Skip to: 40641 +/* 12036 */ MCD_OPC_Decode, 219, 11, 117, // Opcode: SQNEGv16i8 +/* 12040 */ MCD_OPC_FilterValue, 1, 181, 111, // Skip to: 40641 +/* 12044 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 12047 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12065 +/* 12051 */ MCD_OPC_CheckPredicate, 0, 170, 111, // Skip to: 40641 +/* 12055 */ MCD_OPC_CheckField, 21, 1, 1, 164, 111, // Skip to: 40641 +/* 12061 */ MCD_OPC_Decode, 231, 16, 120, // Opcode: UMLALv16i8_v8i16 +/* 12065 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 12096 +/* 12069 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 12072 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12084 +/* 12076 */ MCD_OPC_CheckPredicate, 0, 145, 111, // Skip to: 40641 +/* 12080 */ MCD_OPC_Decode, 177, 1, 117, // Opcode: CMGEv16i8rz +/* 12084 */ MCD_OPC_FilterValue, 33, 137, 111, // Skip to: 40641 +/* 12088 */ MCD_OPC_CheckPredicate, 0, 133, 111, // Skip to: 40641 +/* 12092 */ MCD_OPC_Decode, 156, 5, 117, // Opcode: FRINTAv4f32 +/* 12096 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 12127 +/* 12100 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 12103 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12115 +/* 12107 */ MCD_OPC_CheckPredicate, 0, 114, 111, // Skip to: 40641 +/* 12111 */ MCD_OPC_Decode, 224, 1, 117, // Opcode: CMLEv16i8rz +/* 12115 */ MCD_OPC_FilterValue, 33, 106, 111, // Skip to: 40641 +/* 12119 */ MCD_OPC_CheckPredicate, 0, 102, 111, // Skip to: 40641 +/* 12123 */ MCD_OPC_Decode, 181, 5, 117, // Opcode: FRINTXv4f32 +/* 12127 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12145 +/* 12131 */ MCD_OPC_CheckPredicate, 0, 90, 111, // Skip to: 40641 +/* 12135 */ MCD_OPC_CheckField, 21, 1, 1, 84, 111, // Skip to: 40641 +/* 12141 */ MCD_OPC_Decode, 241, 16, 120, // Opcode: UMLSLv16i8_v8i16 +/* 12145 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 12190 +/* 12149 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 12152 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12164 +/* 12156 */ MCD_OPC_CheckPredicate, 0, 65, 111, // Skip to: 40641 +/* 12160 */ MCD_OPC_Decode, 197, 3, 117, // Opcode: FCVTNUv4f32 +/* 12164 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 12177 +/* 12168 */ MCD_OPC_CheckPredicate, 0, 53, 111, // Skip to: 40641 +/* 12172 */ MCD_OPC_Decode, 203, 16, 137, 1, // Opcode: UMAXVv16i8v +/* 12177 */ MCD_OPC_FilterValue, 49, 44, 111, // Skip to: 40641 +/* 12181 */ MCD_OPC_CheckPredicate, 0, 40, 111, // Skip to: 40641 +/* 12185 */ MCD_OPC_Decode, 220, 16, 137, 1, // Opcode: UMINVv16i8v +/* 12190 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 12221 +/* 12194 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 12197 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12209 +/* 12201 */ MCD_OPC_CheckPredicate, 0, 20, 111, // Skip to: 40641 +/* 12205 */ MCD_OPC_Decode, 247, 8, 117, // Opcode: NEGv16i8 +/* 12209 */ MCD_OPC_FilterValue, 33, 12, 111, // Skip to: 40641 +/* 12213 */ MCD_OPC_CheckPredicate, 0, 8, 111, // Skip to: 40641 +/* 12217 */ MCD_OPC_Decode, 179, 3, 117, // Opcode: FCVTMUv4f32 +/* 12221 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12239 +/* 12225 */ MCD_OPC_CheckPredicate, 0, 252, 110, // Skip to: 40641 +/* 12229 */ MCD_OPC_CheckField, 21, 1, 1, 246, 110, // Skip to: 40641 +/* 12235 */ MCD_OPC_Decode, 129, 17, 112, // Opcode: UMULLv16i8_v8i16 +/* 12239 */ MCD_OPC_FilterValue, 9, 28, 0, // Skip to: 12271 +/* 12243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 12246 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12258 +/* 12250 */ MCD_OPC_CheckPredicate, 0, 227, 110, // Skip to: 40641 +/* 12254 */ MCD_OPC_Decode, 153, 3, 117, // Opcode: FCVTAUv4f32 +/* 12258 */ MCD_OPC_FilterValue, 48, 219, 110, // Skip to: 40641 +/* 12262 */ MCD_OPC_CheckPredicate, 0, 215, 110, // Skip to: 40641 +/* 12266 */ MCD_OPC_Decode, 170, 4, 139, 1, // Opcode: FMAXNMVv4i32v +/* 12271 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12289 +/* 12275 */ MCD_OPC_CheckPredicate, 0, 202, 110, // Skip to: 40641 +/* 12279 */ MCD_OPC_CheckField, 16, 6, 33, 196, 110, // Skip to: 40641 +/* 12285 */ MCD_OPC_Decode, 178, 16, 117, // Opcode: UCVTFv4f32 +/* 12289 */ MCD_OPC_FilterValue, 15, 188, 110, // Skip to: 40641 +/* 12293 */ MCD_OPC_CheckPredicate, 0, 184, 110, // Skip to: 40641 +/* 12297 */ MCD_OPC_CheckField, 16, 6, 48, 178, 110, // Skip to: 40641 +/* 12303 */ MCD_OPC_Decode, 180, 4, 139, 1, // Opcode: FMAXVv4i32v +/* 12308 */ MCD_OPC_FilterValue, 1, 169, 110, // Skip to: 40641 +/* 12312 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 12315 */ MCD_OPC_FilterValue, 0, 43, 1, // Skip to: 12618 +/* 12319 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12322 */ MCD_OPC_FilterValue, 0, 93, 0, // Skip to: 12419 +/* 12326 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 12329 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 12406 +/* 12333 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 12336 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 12387 +/* 12340 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 12343 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 12368 +/* 12347 */ MCD_OPC_CheckPredicate, 0, 130, 110, // Skip to: 40641 +/* 12351 */ MCD_OPC_CheckField, 19, 1, 1, 124, 110, // Skip to: 40641 +/* 12357 */ MCD_OPC_CheckField, 11, 3, 0, 118, 110, // Skip to: 40641 +/* 12363 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: INSvi64lane +/* 12368 */ MCD_OPC_FilterValue, 1, 109, 110, // Skip to: 40641 +/* 12372 */ MCD_OPC_CheckPredicate, 0, 105, 110, // Skip to: 40641 +/* 12376 */ MCD_OPC_CheckField, 11, 2, 0, 99, 110, // Skip to: 40641 +/* 12382 */ MCD_OPC_Decode, 213, 5, 141, 1, // Opcode: INSvi32lane +/* 12387 */ MCD_OPC_FilterValue, 1, 90, 110, // Skip to: 40641 +/* 12391 */ MCD_OPC_CheckPredicate, 0, 86, 110, // Skip to: 40641 +/* 12395 */ MCD_OPC_CheckField, 11, 1, 0, 80, 110, // Skip to: 40641 +/* 12401 */ MCD_OPC_Decode, 211, 5, 142, 1, // Opcode: INSvi16lane +/* 12406 */ MCD_OPC_FilterValue, 1, 71, 110, // Skip to: 40641 +/* 12410 */ MCD_OPC_CheckPredicate, 0, 67, 110, // Skip to: 40641 +/* 12414 */ MCD_OPC_Decode, 217, 5, 143, 1, // Opcode: INSvi8lane +/* 12419 */ MCD_OPC_FilterValue, 1, 58, 110, // Skip to: 40641 +/* 12423 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 12426 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12438 +/* 12430 */ MCD_OPC_CheckPredicate, 0, 47, 110, // Skip to: 40641 +/* 12434 */ MCD_OPC_Decode, 184, 16, 112, // Opcode: UHADDv16i8 +/* 12438 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 12450 +/* 12442 */ MCD_OPC_CheckPredicate, 0, 35, 110, // Skip to: 40641 +/* 12446 */ MCD_OPC_Decode, 139, 17, 112, // Opcode: UQADDv16i8 +/* 12450 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12462 +/* 12454 */ MCD_OPC_CheckPredicate, 0, 23, 110, // Skip to: 40641 +/* 12458 */ MCD_OPC_Decode, 223, 17, 112, // Opcode: URHADDv16i8 +/* 12462 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 12474 +/* 12466 */ MCD_OPC_CheckPredicate, 0, 11, 110, // Skip to: 40641 +/* 12470 */ MCD_OPC_Decode, 172, 2, 112, // Opcode: EORv16i8 +/* 12474 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 12486 +/* 12478 */ MCD_OPC_CheckPredicate, 0, 255, 109, // Skip to: 40641 +/* 12482 */ MCD_OPC_Decode, 190, 16, 112, // Opcode: UHSUBv16i8 +/* 12486 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 12498 +/* 12490 */ MCD_OPC_CheckPredicate, 0, 243, 109, // Skip to: 40641 +/* 12494 */ MCD_OPC_Decode, 201, 17, 112, // Opcode: UQSUBv16i8 +/* 12498 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 12510 +/* 12502 */ MCD_OPC_CheckPredicate, 0, 231, 109, // Skip to: 40641 +/* 12506 */ MCD_OPC_Decode, 208, 1, 112, // Opcode: CMHIv16i8 +/* 12510 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 12522 +/* 12514 */ MCD_OPC_CheckPredicate, 0, 219, 109, // Skip to: 40641 +/* 12518 */ MCD_OPC_Decode, 216, 1, 112, // Opcode: CMHSv16i8 +/* 12522 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12534 +/* 12526 */ MCD_OPC_CheckPredicate, 0, 207, 109, // Skip to: 40641 +/* 12530 */ MCD_OPC_Decode, 133, 18, 112, // Opcode: USHLv16i8 +/* 12534 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 12546 +/* 12538 */ MCD_OPC_CheckPredicate, 0, 195, 109, // Skip to: 40641 +/* 12542 */ MCD_OPC_Decode, 174, 17, 112, // Opcode: UQSHLv16i8 +/* 12546 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12558 +/* 12550 */ MCD_OPC_CheckPredicate, 0, 183, 109, // Skip to: 40641 +/* 12554 */ MCD_OPC_Decode, 229, 17, 112, // Opcode: URSHLv16i8 +/* 12558 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 12570 +/* 12562 */ MCD_OPC_CheckPredicate, 0, 171, 109, // Skip to: 40641 +/* 12566 */ MCD_OPC_Decode, 150, 17, 112, // Opcode: UQRSHLv16i8 +/* 12570 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 12582 +/* 12574 */ MCD_OPC_CheckPredicate, 0, 159, 109, // Skip to: 40641 +/* 12578 */ MCD_OPC_Decode, 208, 16, 112, // Opcode: UMAXv16i8 +/* 12582 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 12594 +/* 12586 */ MCD_OPC_CheckPredicate, 0, 147, 109, // Skip to: 40641 +/* 12590 */ MCD_OPC_Decode, 225, 16, 112, // Opcode: UMINv16i8 +/* 12594 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12606 +/* 12598 */ MCD_OPC_CheckPredicate, 0, 135, 109, // Skip to: 40641 +/* 12602 */ MCD_OPC_Decode, 253, 15, 112, // Opcode: UABDv16i8 +/* 12606 */ MCD_OPC_FilterValue, 15, 127, 109, // Skip to: 40641 +/* 12610 */ MCD_OPC_CheckPredicate, 0, 123, 109, // Skip to: 40641 +/* 12614 */ MCD_OPC_Decode, 241, 15, 120, // Opcode: UABAv16i8 +/* 12618 */ MCD_OPC_FilterValue, 1, 115, 109, // Skip to: 40641 +/* 12622 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 12625 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12643 +/* 12629 */ MCD_OPC_CheckPredicate, 0, 104, 109, // Skip to: 40641 +/* 12633 */ MCD_OPC_CheckField, 21, 1, 1, 98, 109, // Skip to: 40641 +/* 12639 */ MCD_OPC_Decode, 175, 15, 112, // Opcode: SUBv16i8 +/* 12643 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12661 +/* 12647 */ MCD_OPC_CheckPredicate, 0, 86, 109, // Skip to: 40641 +/* 12651 */ MCD_OPC_CheckField, 21, 1, 1, 80, 109, // Skip to: 40641 +/* 12657 */ MCD_OPC_Decode, 160, 1, 112, // Opcode: CMEQv16i8 +/* 12661 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12679 +/* 12665 */ MCD_OPC_CheckPredicate, 0, 68, 109, // Skip to: 40641 +/* 12669 */ MCD_OPC_CheckField, 21, 1, 1, 62, 109, // Skip to: 40641 +/* 12675 */ MCD_OPC_Decode, 192, 8, 120, // Opcode: MLSv16i8 +/* 12679 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12697 +/* 12683 */ MCD_OPC_CheckPredicate, 0, 50, 109, // Skip to: 40641 +/* 12687 */ MCD_OPC_CheckField, 21, 1, 1, 44, 109, // Skip to: 40641 +/* 12693 */ MCD_OPC_Decode, 151, 9, 112, // Opcode: PMULv16i8 +/* 12697 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12715 +/* 12701 */ MCD_OPC_CheckPredicate, 0, 32, 109, // Skip to: 40641 +/* 12705 */ MCD_OPC_CheckField, 21, 1, 1, 26, 109, // Skip to: 40641 +/* 12711 */ MCD_OPC_Decode, 197, 16, 112, // Opcode: UMAXPv16i8 +/* 12715 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12733 +/* 12719 */ MCD_OPC_CheckPredicate, 0, 14, 109, // Skip to: 40641 +/* 12723 */ MCD_OPC_CheckField, 21, 1, 1, 8, 109, // Skip to: 40641 +/* 12729 */ MCD_OPC_Decode, 214, 16, 112, // Opcode: UMINPv16i8 +/* 12733 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12751 +/* 12737 */ MCD_OPC_CheckPredicate, 0, 252, 108, // Skip to: 40641 +/* 12741 */ MCD_OPC_CheckField, 21, 1, 1, 246, 108, // Skip to: 40641 +/* 12747 */ MCD_OPC_Decode, 168, 4, 112, // Opcode: FMAXNMPv4f32 +/* 12751 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 12769 +/* 12755 */ MCD_OPC_CheckPredicate, 0, 234, 108, // Skip to: 40641 +/* 12759 */ MCD_OPC_CheckField, 21, 1, 1, 228, 108, // Skip to: 40641 +/* 12765 */ MCD_OPC_Decode, 205, 2, 112, // Opcode: FADDPv4f32 +/* 12769 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12787 +/* 12773 */ MCD_OPC_CheckPredicate, 0, 216, 108, // Skip to: 40641 +/* 12777 */ MCD_OPC_CheckField, 21, 1, 1, 210, 108, // Skip to: 40641 +/* 12783 */ MCD_OPC_Decode, 255, 4, 112, // Opcode: FMULv4f32 +/* 12787 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12805 +/* 12791 */ MCD_OPC_CheckPredicate, 0, 198, 108, // Skip to: 40641 +/* 12795 */ MCD_OPC_CheckField, 21, 1, 1, 192, 108, // Skip to: 40641 +/* 12801 */ MCD_OPC_Decode, 232, 2, 112, // Opcode: FCMGEv4f32 +/* 12805 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12823 +/* 12809 */ MCD_OPC_CheckPredicate, 0, 180, 108, // Skip to: 40641 +/* 12813 */ MCD_OPC_CheckField, 21, 1, 1, 174, 108, // Skip to: 40641 +/* 12819 */ MCD_OPC_Decode, 194, 2, 112, // Opcode: FACGEv4f32 +/* 12823 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 12841 +/* 12827 */ MCD_OPC_CheckPredicate, 0, 162, 108, // Skip to: 40641 +/* 12831 */ MCD_OPC_CheckField, 21, 1, 1, 156, 108, // Skip to: 40641 +/* 12837 */ MCD_OPC_Decode, 178, 4, 112, // Opcode: FMAXPv4f32 +/* 12841 */ MCD_OPC_FilterValue, 15, 148, 108, // Skip to: 40641 +/* 12845 */ MCD_OPC_CheckPredicate, 0, 144, 108, // Skip to: 40641 +/* 12849 */ MCD_OPC_CheckField, 21, 1, 1, 138, 108, // Skip to: 40641 +/* 12855 */ MCD_OPC_Decode, 159, 4, 112, // Opcode: FDIVv4f32 +/* 12859 */ MCD_OPC_FilterValue, 9, 131, 18, // Skip to: 17602 +/* 12863 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 12866 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 12945 +/* 12870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 12873 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12891 +/* 12877 */ MCD_OPC_CheckPredicate, 0, 112, 108, // Skip to: 40641 +/* 12881 */ MCD_OPC_CheckField, 21, 1, 1, 106, 108, // Skip to: 40641 +/* 12887 */ MCD_OPC_Decode, 244, 9, 85, // Opcode: SADDLv4i16_v4i32 +/* 12891 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12909 +/* 12895 */ MCD_OPC_CheckPredicate, 0, 94, 108, // Skip to: 40641 +/* 12899 */ MCD_OPC_CheckField, 21, 1, 1, 88, 108, // Skip to: 40641 +/* 12905 */ MCD_OPC_Decode, 150, 16, 85, // Opcode: UADDLv4i16_v4i32 +/* 12909 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12927 +/* 12913 */ MCD_OPC_CheckPredicate, 0, 76, 108, // Skip to: 40641 +/* 12917 */ MCD_OPC_CheckField, 21, 1, 1, 70, 108, // Skip to: 40641 +/* 12923 */ MCD_OPC_Decode, 246, 9, 112, // Opcode: SADDLv8i16_v4i32 +/* 12927 */ MCD_OPC_FilterValue, 3, 62, 108, // Skip to: 40641 +/* 12931 */ MCD_OPC_CheckPredicate, 0, 58, 108, // Skip to: 40641 +/* 12935 */ MCD_OPC_CheckField, 21, 1, 1, 52, 108, // Skip to: 40641 +/* 12941 */ MCD_OPC_Decode, 152, 16, 112, // Opcode: UADDLv8i16_v4i32 +/* 12945 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13024 +/* 12949 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 12952 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12970 +/* 12956 */ MCD_OPC_CheckPredicate, 0, 33, 108, // Skip to: 40641 +/* 12960 */ MCD_OPC_CheckField, 21, 1, 1, 27, 108, // Skip to: 40641 +/* 12966 */ MCD_OPC_Decode, 166, 10, 89, // Opcode: SHADDv4i16 +/* 12970 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12988 +/* 12974 */ MCD_OPC_CheckPredicate, 0, 15, 108, // Skip to: 40641 +/* 12978 */ MCD_OPC_CheckField, 21, 1, 1, 9, 108, // Skip to: 40641 +/* 12984 */ MCD_OPC_Decode, 186, 16, 89, // Opcode: UHADDv4i16 +/* 12988 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13006 +/* 12992 */ MCD_OPC_CheckPredicate, 0, 253, 107, // Skip to: 40641 +/* 12996 */ MCD_OPC_CheckField, 21, 1, 1, 247, 107, // Skip to: 40641 +/* 13002 */ MCD_OPC_Decode, 168, 10, 112, // Opcode: SHADDv8i16 +/* 13006 */ MCD_OPC_FilterValue, 3, 239, 107, // Skip to: 40641 +/* 13010 */ MCD_OPC_CheckPredicate, 0, 235, 107, // Skip to: 40641 +/* 13014 */ MCD_OPC_CheckField, 21, 1, 1, 229, 107, // Skip to: 40641 +/* 13020 */ MCD_OPC_Decode, 188, 16, 112, // Opcode: UHADDv8i16 +/* 13024 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 13103 +/* 13028 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13031 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13049 +/* 13035 */ MCD_OPC_CheckPredicate, 0, 210, 107, // Skip to: 40641 +/* 13039 */ MCD_OPC_CheckField, 16, 6, 32, 204, 107, // Skip to: 40641 +/* 13045 */ MCD_OPC_Decode, 181, 9, 90, // Opcode: REV64v4i16 +/* 13049 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13067 +/* 13053 */ MCD_OPC_CheckPredicate, 0, 192, 107, // Skip to: 40641 +/* 13057 */ MCD_OPC_CheckField, 16, 6, 32, 186, 107, // Skip to: 40641 +/* 13063 */ MCD_OPC_Decode, 176, 9, 90, // Opcode: REV32v4i16 +/* 13067 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13085 +/* 13071 */ MCD_OPC_CheckPredicate, 0, 174, 107, // Skip to: 40641 +/* 13075 */ MCD_OPC_CheckField, 16, 6, 32, 168, 107, // Skip to: 40641 +/* 13081 */ MCD_OPC_Decode, 183, 9, 117, // Opcode: REV64v8i16 +/* 13085 */ MCD_OPC_FilterValue, 3, 160, 107, // Skip to: 40641 +/* 13089 */ MCD_OPC_CheckPredicate, 0, 156, 107, // Skip to: 40641 +/* 13093 */ MCD_OPC_CheckField, 16, 6, 32, 150, 107, // Skip to: 40641 +/* 13099 */ MCD_OPC_Decode, 177, 9, 117, // Opcode: REV32v8i16 +/* 13103 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 13182 +/* 13107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13110 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13128 +/* 13114 */ MCD_OPC_CheckPredicate, 0, 131, 107, // Skip to: 40641 +/* 13118 */ MCD_OPC_CheckField, 21, 1, 1, 125, 107, // Skip to: 40641 +/* 13124 */ MCD_OPC_Decode, 167, 11, 89, // Opcode: SQADDv4i16 +/* 13128 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13146 +/* 13132 */ MCD_OPC_CheckPredicate, 0, 113, 107, // Skip to: 40641 +/* 13136 */ MCD_OPC_CheckField, 21, 1, 1, 107, 107, // Skip to: 40641 +/* 13142 */ MCD_OPC_Decode, 146, 17, 89, // Opcode: UQADDv4i16 +/* 13146 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13164 +/* 13150 */ MCD_OPC_CheckPredicate, 0, 95, 107, // Skip to: 40641 +/* 13154 */ MCD_OPC_CheckField, 21, 1, 1, 89, 107, // Skip to: 40641 +/* 13160 */ MCD_OPC_Decode, 169, 11, 112, // Opcode: SQADDv8i16 +/* 13164 */ MCD_OPC_FilterValue, 3, 81, 107, // Skip to: 40641 +/* 13168 */ MCD_OPC_CheckPredicate, 0, 77, 107, // Skip to: 40641 +/* 13172 */ MCD_OPC_CheckField, 21, 1, 1, 71, 107, // Skip to: 40641 +/* 13178 */ MCD_OPC_Decode, 148, 17, 112, // Opcode: UQADDv8i16 +/* 13182 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 13261 +/* 13186 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13189 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13207 +/* 13193 */ MCD_OPC_CheckPredicate, 0, 52, 107, // Skip to: 40641 +/* 13197 */ MCD_OPC_CheckField, 21, 1, 1, 46, 107, // Skip to: 40641 +/* 13203 */ MCD_OPC_Decode, 250, 9, 93, // Opcode: SADDWv4i16_v4i32 +/* 13207 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13225 +/* 13211 */ MCD_OPC_CheckPredicate, 0, 34, 107, // Skip to: 40641 +/* 13215 */ MCD_OPC_CheckField, 21, 1, 1, 28, 107, // Skip to: 40641 +/* 13221 */ MCD_OPC_Decode, 156, 16, 93, // Opcode: UADDWv4i16_v4i32 +/* 13225 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13243 +/* 13229 */ MCD_OPC_CheckPredicate, 0, 16, 107, // Skip to: 40641 +/* 13233 */ MCD_OPC_CheckField, 21, 1, 1, 10, 107, // Skip to: 40641 +/* 13239 */ MCD_OPC_Decode, 252, 9, 112, // Opcode: SADDWv8i16_v4i32 +/* 13243 */ MCD_OPC_FilterValue, 3, 2, 107, // Skip to: 40641 +/* 13247 */ MCD_OPC_CheckPredicate, 0, 254, 106, // Skip to: 40641 +/* 13251 */ MCD_OPC_CheckField, 21, 1, 1, 248, 106, // Skip to: 40641 +/* 13257 */ MCD_OPC_Decode, 158, 16, 112, // Opcode: UADDWv8i16_v4i32 +/* 13261 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 13340 +/* 13265 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13268 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13286 +/* 13272 */ MCD_OPC_CheckPredicate, 0, 229, 106, // Skip to: 40641 +/* 13276 */ MCD_OPC_CheckField, 21, 1, 1, 223, 106, // Skip to: 40641 +/* 13282 */ MCD_OPC_Decode, 225, 12, 89, // Opcode: SRHADDv4i16 +/* 13286 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13304 +/* 13290 */ MCD_OPC_CheckPredicate, 0, 211, 106, // Skip to: 40641 +/* 13294 */ MCD_OPC_CheckField, 21, 1, 1, 205, 106, // Skip to: 40641 +/* 13300 */ MCD_OPC_Decode, 225, 17, 89, // Opcode: URHADDv4i16 +/* 13304 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13322 +/* 13308 */ MCD_OPC_CheckPredicate, 0, 193, 106, // Skip to: 40641 +/* 13312 */ MCD_OPC_CheckField, 21, 1, 1, 187, 106, // Skip to: 40641 +/* 13318 */ MCD_OPC_Decode, 227, 12, 112, // Opcode: SRHADDv8i16 +/* 13322 */ MCD_OPC_FilterValue, 3, 179, 106, // Skip to: 40641 +/* 13326 */ MCD_OPC_CheckPredicate, 0, 175, 106, // Skip to: 40641 +/* 13330 */ MCD_OPC_CheckField, 21, 1, 1, 169, 106, // Skip to: 40641 +/* 13336 */ MCD_OPC_Decode, 227, 17, 112, // Opcode: URHADDv8i16 +/* 13340 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 13383 +/* 13344 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13347 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13365 +/* 13351 */ MCD_OPC_CheckPredicate, 0, 150, 106, // Skip to: 40641 +/* 13355 */ MCD_OPC_CheckField, 21, 1, 0, 144, 106, // Skip to: 40641 +/* 13361 */ MCD_OPC_Decode, 183, 18, 89, // Opcode: UZP1v4i16 +/* 13365 */ MCD_OPC_FilterValue, 2, 136, 106, // Skip to: 40641 +/* 13369 */ MCD_OPC_CheckPredicate, 0, 132, 106, // Skip to: 40641 +/* 13373 */ MCD_OPC_CheckField, 21, 1, 0, 126, 106, // Skip to: 40641 +/* 13379 */ MCD_OPC_Decode, 185, 18, 112, // Opcode: UZP1v8i16 +/* 13383 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 13460 +/* 13387 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13390 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 13407 +/* 13394 */ MCD_OPC_CheckPredicate, 0, 107, 106, // Skip to: 40641 +/* 13398 */ MCD_OPC_CheckField, 21, 1, 1, 101, 106, // Skip to: 40641 +/* 13404 */ MCD_OPC_Decode, 119, 89, // Opcode: BICv8i8 +/* 13407 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13425 +/* 13411 */ MCD_OPC_CheckPredicate, 0, 90, 106, // Skip to: 40641 +/* 13415 */ MCD_OPC_CheckField, 21, 1, 1, 84, 106, // Skip to: 40641 +/* 13421 */ MCD_OPC_Decode, 129, 1, 109, // Opcode: BSLv8i8 +/* 13425 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 13442 +/* 13429 */ MCD_OPC_CheckPredicate, 0, 72, 106, // Skip to: 40641 +/* 13433 */ MCD_OPC_CheckField, 21, 1, 1, 66, 106, // Skip to: 40641 +/* 13439 */ MCD_OPC_Decode, 114, 112, // Opcode: BICv16i8 +/* 13442 */ MCD_OPC_FilterValue, 3, 59, 106, // Skip to: 40641 +/* 13446 */ MCD_OPC_CheckPredicate, 0, 55, 106, // Skip to: 40641 +/* 13450 */ MCD_OPC_CheckField, 21, 1, 1, 49, 106, // Skip to: 40641 +/* 13456 */ MCD_OPC_Decode, 128, 1, 120, // Opcode: BSLv16i8 +/* 13460 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 13539 +/* 13464 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13467 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13485 +/* 13471 */ MCD_OPC_CheckPredicate, 0, 30, 106, // Skip to: 40641 +/* 13475 */ MCD_OPC_CheckField, 21, 1, 1, 24, 106, // Skip to: 40641 +/* 13481 */ MCD_OPC_Decode, 165, 13, 85, // Opcode: SSUBLv4i16_v4i32 +/* 13485 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13503 +/* 13489 */ MCD_OPC_CheckPredicate, 0, 12, 106, // Skip to: 40641 +/* 13493 */ MCD_OPC_CheckField, 21, 1, 1, 6, 106, // Skip to: 40641 +/* 13499 */ MCD_OPC_Decode, 170, 18, 85, // Opcode: USUBLv4i16_v4i32 +/* 13503 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13521 +/* 13507 */ MCD_OPC_CheckPredicate, 0, 250, 105, // Skip to: 40641 +/* 13511 */ MCD_OPC_CheckField, 21, 1, 1, 244, 105, // Skip to: 40641 +/* 13517 */ MCD_OPC_Decode, 167, 13, 112, // Opcode: SSUBLv8i16_v4i32 +/* 13521 */ MCD_OPC_FilterValue, 3, 236, 105, // Skip to: 40641 +/* 13525 */ MCD_OPC_CheckPredicate, 0, 232, 105, // Skip to: 40641 +/* 13529 */ MCD_OPC_CheckField, 21, 1, 1, 226, 105, // Skip to: 40641 +/* 13535 */ MCD_OPC_Decode, 172, 18, 112, // Opcode: USUBLv8i16_v4i32 +/* 13539 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 13618 +/* 13543 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13546 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13564 +/* 13550 */ MCD_OPC_CheckPredicate, 0, 207, 105, // Skip to: 40641 +/* 13554 */ MCD_OPC_CheckField, 21, 1, 1, 201, 105, // Skip to: 40641 +/* 13560 */ MCD_OPC_Decode, 192, 10, 89, // Opcode: SHSUBv4i16 +/* 13564 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13582 +/* 13568 */ MCD_OPC_CheckPredicate, 0, 189, 105, // Skip to: 40641 +/* 13572 */ MCD_OPC_CheckField, 21, 1, 1, 183, 105, // Skip to: 40641 +/* 13578 */ MCD_OPC_Decode, 192, 16, 89, // Opcode: UHSUBv4i16 +/* 13582 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13600 +/* 13586 */ MCD_OPC_CheckPredicate, 0, 171, 105, // Skip to: 40641 +/* 13590 */ MCD_OPC_CheckField, 21, 1, 1, 165, 105, // Skip to: 40641 +/* 13596 */ MCD_OPC_Decode, 194, 10, 112, // Opcode: SHSUBv8i16 +/* 13600 */ MCD_OPC_FilterValue, 3, 157, 105, // Skip to: 40641 +/* 13604 */ MCD_OPC_CheckPredicate, 0, 153, 105, // Skip to: 40641 +/* 13608 */ MCD_OPC_CheckField, 21, 1, 1, 147, 105, // Skip to: 40641 +/* 13614 */ MCD_OPC_Decode, 194, 16, 112, // Opcode: UHSUBv8i16 +/* 13618 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 13787 +/* 13622 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13625 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 13675 +/* 13629 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13632 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13644 +/* 13636 */ MCD_OPC_CheckPredicate, 0, 121, 105, // Skip to: 40641 +/* 13640 */ MCD_OPC_Decode, 224, 15, 89, // Opcode: TRN1v4i16 +/* 13644 */ MCD_OPC_FilterValue, 1, 113, 105, // Skip to: 40641 +/* 13648 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 13651 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13663 +/* 13655 */ MCD_OPC_CheckPredicate, 0, 102, 105, // Skip to: 40641 +/* 13659 */ MCD_OPC_Decode, 233, 9, 90, // Opcode: SADDLPv4i16_v2i32 +/* 13663 */ MCD_OPC_FilterValue, 1, 94, 105, // Skip to: 40641 +/* 13667 */ MCD_OPC_CheckPredicate, 0, 90, 105, // Skip to: 40641 +/* 13671 */ MCD_OPC_Decode, 196, 18, 95, // Opcode: XTNv4i16 +/* 13675 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 13706 +/* 13679 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 13682 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13694 +/* 13686 */ MCD_OPC_CheckPredicate, 0, 71, 105, // Skip to: 40641 +/* 13690 */ MCD_OPC_Decode, 139, 16, 90, // Opcode: UADDLPv4i16_v2i32 +/* 13694 */ MCD_OPC_FilterValue, 33, 63, 105, // Skip to: 40641 +/* 13698 */ MCD_OPC_CheckPredicate, 0, 59, 105, // Skip to: 40641 +/* 13702 */ MCD_OPC_Decode, 219, 12, 95, // Opcode: SQXTUNv4i16 +/* 13706 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 13756 +/* 13710 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13713 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13725 +/* 13717 */ MCD_OPC_CheckPredicate, 0, 40, 105, // Skip to: 40641 +/* 13721 */ MCD_OPC_Decode, 226, 15, 112, // Opcode: TRN1v8i16 +/* 13725 */ MCD_OPC_FilterValue, 1, 32, 105, // Skip to: 40641 +/* 13729 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 13732 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13744 +/* 13736 */ MCD_OPC_CheckPredicate, 0, 21, 105, // Skip to: 40641 +/* 13740 */ MCD_OPC_Decode, 235, 9, 117, // Opcode: SADDLPv8i16_v4i32 +/* 13744 */ MCD_OPC_FilterValue, 1, 13, 105, // Skip to: 40641 +/* 13748 */ MCD_OPC_CheckPredicate, 0, 9, 105, // Skip to: 40641 +/* 13752 */ MCD_OPC_Decode, 198, 18, 126, // Opcode: XTNv8i16 +/* 13756 */ MCD_OPC_FilterValue, 3, 1, 105, // Skip to: 40641 +/* 13760 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 13763 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13775 +/* 13767 */ MCD_OPC_CheckPredicate, 0, 246, 104, // Skip to: 40641 +/* 13771 */ MCD_OPC_Decode, 141, 16, 117, // Opcode: UADDLPv8i16_v4i32 +/* 13775 */ MCD_OPC_FilterValue, 33, 238, 104, // Skip to: 40641 +/* 13779 */ MCD_OPC_CheckPredicate, 0, 234, 104, // Skip to: 40641 +/* 13783 */ MCD_OPC_Decode, 221, 12, 126, // Opcode: SQXTUNv8i16 +/* 13787 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 13866 +/* 13791 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13794 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13812 +/* 13798 */ MCD_OPC_CheckPredicate, 0, 215, 104, // Skip to: 40641 +/* 13802 */ MCD_OPC_CheckField, 21, 1, 1, 209, 104, // Skip to: 40641 +/* 13808 */ MCD_OPC_Decode, 201, 12, 89, // Opcode: SQSUBv4i16 +/* 13812 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13830 +/* 13816 */ MCD_OPC_CheckPredicate, 0, 197, 104, // Skip to: 40641 +/* 13820 */ MCD_OPC_CheckField, 21, 1, 1, 191, 104, // Skip to: 40641 +/* 13826 */ MCD_OPC_Decode, 208, 17, 89, // Opcode: UQSUBv4i16 +/* 13830 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13848 +/* 13834 */ MCD_OPC_CheckPredicate, 0, 179, 104, // Skip to: 40641 +/* 13838 */ MCD_OPC_CheckField, 21, 1, 1, 173, 104, // Skip to: 40641 +/* 13844 */ MCD_OPC_Decode, 203, 12, 112, // Opcode: SQSUBv8i16 +/* 13848 */ MCD_OPC_FilterValue, 3, 165, 104, // Skip to: 40641 +/* 13852 */ MCD_OPC_CheckPredicate, 0, 161, 104, // Skip to: 40641 +/* 13856 */ MCD_OPC_CheckField, 21, 1, 1, 155, 104, // Skip to: 40641 +/* 13862 */ MCD_OPC_Decode, 210, 17, 112, // Opcode: UQSUBv8i16 +/* 13866 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 13945 +/* 13870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13873 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13891 +/* 13877 */ MCD_OPC_CheckPredicate, 0, 136, 104, // Skip to: 40641 +/* 13881 */ MCD_OPC_CheckField, 21, 1, 1, 130, 104, // Skip to: 40641 +/* 13887 */ MCD_OPC_Decode, 171, 13, 93, // Opcode: SSUBWv4i16_v4i32 +/* 13891 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13909 +/* 13895 */ MCD_OPC_CheckPredicate, 0, 118, 104, // Skip to: 40641 +/* 13899 */ MCD_OPC_CheckField, 21, 1, 1, 112, 104, // Skip to: 40641 +/* 13905 */ MCD_OPC_Decode, 176, 18, 93, // Opcode: USUBWv4i16_v4i32 +/* 13909 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13927 +/* 13913 */ MCD_OPC_CheckPredicate, 0, 100, 104, // Skip to: 40641 +/* 13917 */ MCD_OPC_CheckField, 21, 1, 1, 94, 104, // Skip to: 40641 +/* 13923 */ MCD_OPC_Decode, 173, 13, 112, // Opcode: SSUBWv8i16_v4i32 +/* 13927 */ MCD_OPC_FilterValue, 3, 86, 104, // Skip to: 40641 +/* 13931 */ MCD_OPC_CheckPredicate, 0, 82, 104, // Skip to: 40641 +/* 13935 */ MCD_OPC_CheckField, 21, 1, 1, 76, 104, // Skip to: 40641 +/* 13941 */ MCD_OPC_Decode, 178, 18, 112, // Opcode: USUBWv8i16_v4i32 +/* 13945 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 14024 +/* 13949 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 13952 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13970 +/* 13956 */ MCD_OPC_CheckPredicate, 0, 57, 104, // Skip to: 40641 +/* 13960 */ MCD_OPC_CheckField, 21, 1, 1, 51, 104, // Skip to: 40641 +/* 13966 */ MCD_OPC_Decode, 200, 1, 89, // Opcode: CMGTv4i16 +/* 13970 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13988 +/* 13974 */ MCD_OPC_CheckPredicate, 0, 39, 104, // Skip to: 40641 +/* 13978 */ MCD_OPC_CheckField, 21, 1, 1, 33, 104, // Skip to: 40641 +/* 13984 */ MCD_OPC_Decode, 212, 1, 89, // Opcode: CMHIv4i16 +/* 13988 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14006 +/* 13992 */ MCD_OPC_CheckPredicate, 0, 21, 104, // Skip to: 40641 +/* 13996 */ MCD_OPC_CheckField, 21, 1, 1, 15, 104, // Skip to: 40641 +/* 14002 */ MCD_OPC_Decode, 204, 1, 112, // Opcode: CMGTv8i16 +/* 14006 */ MCD_OPC_FilterValue, 3, 7, 104, // Skip to: 40641 +/* 14010 */ MCD_OPC_CheckPredicate, 0, 3, 104, // Skip to: 40641 +/* 14014 */ MCD_OPC_CheckField, 21, 1, 1, 253, 103, // Skip to: 40641 +/* 14020 */ MCD_OPC_Decode, 214, 1, 112, // Opcode: CMHIv8i16 +/* 14024 */ MCD_OPC_FilterValue, 14, 193, 0, // Skip to: 14221 +/* 14028 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14031 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 14082 +/* 14035 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 14038 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14050 +/* 14042 */ MCD_OPC_CheckPredicate, 0, 227, 103, // Skip to: 40641 +/* 14046 */ MCD_OPC_Decode, 203, 18, 89, // Opcode: ZIP1v4i16 +/* 14050 */ MCD_OPC_FilterValue, 1, 219, 103, // Skip to: 40641 +/* 14054 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 14057 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14069 +/* 14061 */ MCD_OPC_CheckPredicate, 0, 208, 103, // Skip to: 40641 +/* 14065 */ MCD_OPC_Decode, 190, 15, 99, // Opcode: SUQADDv4i16 +/* 14069 */ MCD_OPC_FilterValue, 16, 200, 103, // Skip to: 40641 +/* 14073 */ MCD_OPC_CheckPredicate, 0, 196, 103, // Skip to: 40641 +/* 14077 */ MCD_OPC_Decode, 238, 9, 144, 1, // Opcode: SADDLVv4i16v +/* 14082 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 14126 +/* 14086 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14089 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14101 +/* 14093 */ MCD_OPC_CheckPredicate, 0, 176, 103, // Skip to: 40641 +/* 14097 */ MCD_OPC_Decode, 156, 18, 99, // Opcode: USQADDv4i16 +/* 14101 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14113 +/* 14105 */ MCD_OPC_CheckPredicate, 0, 164, 103, // Skip to: 40641 +/* 14109 */ MCD_OPC_Decode, 172, 10, 108, // Opcode: SHLLv4i16 +/* 14113 */ MCD_OPC_FilterValue, 48, 156, 103, // Skip to: 40641 +/* 14117 */ MCD_OPC_CheckPredicate, 0, 152, 103, // Skip to: 40641 +/* 14121 */ MCD_OPC_Decode, 144, 16, 144, 1, // Opcode: UADDLVv4i16v +/* 14126 */ MCD_OPC_FilterValue, 2, 47, 0, // Skip to: 14177 +/* 14130 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 14133 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14145 +/* 14137 */ MCD_OPC_CheckPredicate, 0, 132, 103, // Skip to: 40641 +/* 14141 */ MCD_OPC_Decode, 205, 18, 112, // Opcode: ZIP1v8i16 +/* 14145 */ MCD_OPC_FilterValue, 1, 124, 103, // Skip to: 40641 +/* 14149 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 14152 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14164 +/* 14156 */ MCD_OPC_CheckPredicate, 0, 113, 103, // Skip to: 40641 +/* 14160 */ MCD_OPC_Decode, 192, 15, 126, // Opcode: SUQADDv8i16 +/* 14164 */ MCD_OPC_FilterValue, 16, 105, 103, // Skip to: 40641 +/* 14168 */ MCD_OPC_CheckPredicate, 0, 101, 103, // Skip to: 40641 +/* 14172 */ MCD_OPC_Decode, 240, 9, 139, 1, // Opcode: SADDLVv8i16v +/* 14177 */ MCD_OPC_FilterValue, 3, 92, 103, // Skip to: 40641 +/* 14181 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14184 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14196 +/* 14188 */ MCD_OPC_CheckPredicate, 0, 81, 103, // Skip to: 40641 +/* 14192 */ MCD_OPC_Decode, 158, 18, 126, // Opcode: USQADDv8i16 +/* 14196 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14208 +/* 14200 */ MCD_OPC_CheckPredicate, 0, 69, 103, // Skip to: 40641 +/* 14204 */ MCD_OPC_Decode, 174, 10, 117, // Opcode: SHLLv8i16 +/* 14208 */ MCD_OPC_FilterValue, 48, 61, 103, // Skip to: 40641 +/* 14212 */ MCD_OPC_CheckPredicate, 0, 57, 103, // Skip to: 40641 +/* 14216 */ MCD_OPC_Decode, 146, 16, 139, 1, // Opcode: UADDLVv8i16v +/* 14221 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 14300 +/* 14225 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14228 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14246 +/* 14232 */ MCD_OPC_CheckPredicate, 0, 37, 103, // Skip to: 40641 +/* 14236 */ MCD_OPC_CheckField, 21, 1, 1, 31, 103, // Skip to: 40641 +/* 14242 */ MCD_OPC_Decode, 184, 1, 89, // Opcode: CMGEv4i16 +/* 14246 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14264 +/* 14250 */ MCD_OPC_CheckPredicate, 0, 19, 103, // Skip to: 40641 +/* 14254 */ MCD_OPC_CheckField, 21, 1, 1, 13, 103, // Skip to: 40641 +/* 14260 */ MCD_OPC_Decode, 220, 1, 89, // Opcode: CMHSv4i16 +/* 14264 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14282 +/* 14268 */ MCD_OPC_CheckPredicate, 0, 1, 103, // Skip to: 40641 +/* 14272 */ MCD_OPC_CheckField, 21, 1, 1, 251, 102, // Skip to: 40641 +/* 14278 */ MCD_OPC_Decode, 188, 1, 112, // Opcode: CMGEv8i16 +/* 14282 */ MCD_OPC_FilterValue, 3, 243, 102, // Skip to: 40641 +/* 14286 */ MCD_OPC_CheckPredicate, 0, 239, 102, // Skip to: 40641 +/* 14290 */ MCD_OPC_CheckField, 21, 1, 1, 233, 102, // Skip to: 40641 +/* 14296 */ MCD_OPC_Decode, 222, 1, 112, // Opcode: CMHSv8i16 +/* 14300 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 14377 +/* 14304 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14307 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 14324 +/* 14311 */ MCD_OPC_CheckPredicate, 0, 214, 102, // Skip to: 40641 +/* 14315 */ MCD_OPC_CheckField, 21, 1, 1, 208, 102, // Skip to: 40641 +/* 14321 */ MCD_OPC_Decode, 36, 103, // Opcode: ADDHNv4i32_v4i16 +/* 14324 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14342 +/* 14328 */ MCD_OPC_CheckPredicate, 0, 197, 102, // Skip to: 40641 +/* 14332 */ MCD_OPC_CheckField, 21, 1, 1, 191, 102, // Skip to: 40641 +/* 14338 */ MCD_OPC_Decode, 160, 9, 103, // Opcode: RADDHNv4i32_v4i16 +/* 14342 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 14359 +/* 14346 */ MCD_OPC_CheckPredicate, 0, 179, 102, // Skip to: 40641 +/* 14350 */ MCD_OPC_CheckField, 21, 1, 1, 173, 102, // Skip to: 40641 +/* 14356 */ MCD_OPC_Decode, 37, 120, // Opcode: ADDHNv4i32_v8i16 +/* 14359 */ MCD_OPC_FilterValue, 3, 166, 102, // Skip to: 40641 +/* 14363 */ MCD_OPC_CheckPredicate, 0, 162, 102, // Skip to: 40641 +/* 14367 */ MCD_OPC_CheckField, 21, 1, 1, 156, 102, // Skip to: 40641 +/* 14373 */ MCD_OPC_Decode, 161, 9, 120, // Opcode: RADDHNv4i32_v8i16 +/* 14377 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 14456 +/* 14381 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14384 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14402 +/* 14388 */ MCD_OPC_CheckPredicate, 0, 137, 102, // Skip to: 40641 +/* 14392 */ MCD_OPC_CheckField, 21, 1, 1, 131, 102, // Skip to: 40641 +/* 14398 */ MCD_OPC_Decode, 143, 13, 89, // Opcode: SSHLv4i16 +/* 14402 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14420 +/* 14406 */ MCD_OPC_CheckPredicate, 0, 119, 102, // Skip to: 40641 +/* 14410 */ MCD_OPC_CheckField, 21, 1, 1, 113, 102, // Skip to: 40641 +/* 14416 */ MCD_OPC_Decode, 137, 18, 89, // Opcode: USHLv4i16 +/* 14420 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14438 +/* 14424 */ MCD_OPC_CheckPredicate, 0, 101, 102, // Skip to: 40641 +/* 14428 */ MCD_OPC_CheckField, 21, 1, 1, 95, 102, // Skip to: 40641 +/* 14434 */ MCD_OPC_Decode, 145, 13, 112, // Opcode: SSHLv8i16 +/* 14438 */ MCD_OPC_FilterValue, 3, 87, 102, // Skip to: 40641 +/* 14442 */ MCD_OPC_CheckPredicate, 0, 83, 102, // Skip to: 40641 +/* 14446 */ MCD_OPC_CheckField, 21, 1, 1, 77, 102, // Skip to: 40641 +/* 14452 */ MCD_OPC_Decode, 139, 18, 112, // Opcode: USHLv8i16 +/* 14456 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 14587 +/* 14460 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14463 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 14494 +/* 14467 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14470 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14482 +/* 14474 */ MCD_OPC_CheckPredicate, 0, 51, 102, // Skip to: 40641 +/* 14478 */ MCD_OPC_Decode, 148, 1, 90, // Opcode: CLSv4i16 +/* 14482 */ MCD_OPC_FilterValue, 33, 43, 102, // Skip to: 40641 +/* 14486 */ MCD_OPC_CheckPredicate, 0, 39, 102, // Skip to: 40641 +/* 14490 */ MCD_OPC_Decode, 210, 12, 95, // Opcode: SQXTNv4i16 +/* 14494 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 14525 +/* 14498 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14501 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14513 +/* 14505 */ MCD_OPC_CheckPredicate, 0, 20, 102, // Skip to: 40641 +/* 14509 */ MCD_OPC_Decode, 156, 1, 90, // Opcode: CLZv4i16 +/* 14513 */ MCD_OPC_FilterValue, 33, 12, 102, // Skip to: 40641 +/* 14517 */ MCD_OPC_CheckPredicate, 0, 8, 102, // Skip to: 40641 +/* 14521 */ MCD_OPC_Decode, 217, 17, 95, // Opcode: UQXTNv4i16 +/* 14525 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 14556 +/* 14529 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14532 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14544 +/* 14536 */ MCD_OPC_CheckPredicate, 0, 245, 101, // Skip to: 40641 +/* 14540 */ MCD_OPC_Decode, 150, 1, 117, // Opcode: CLSv8i16 +/* 14544 */ MCD_OPC_FilterValue, 33, 237, 101, // Skip to: 40641 +/* 14548 */ MCD_OPC_CheckPredicate, 0, 233, 101, // Skip to: 40641 +/* 14552 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: SQXTNv8i16 +/* 14556 */ MCD_OPC_FilterValue, 3, 225, 101, // Skip to: 40641 +/* 14560 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 14563 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14575 +/* 14567 */ MCD_OPC_CheckPredicate, 0, 214, 101, // Skip to: 40641 +/* 14571 */ MCD_OPC_Decode, 158, 1, 117, // Opcode: CLZv8i16 +/* 14575 */ MCD_OPC_FilterValue, 33, 206, 101, // Skip to: 40641 +/* 14579 */ MCD_OPC_CheckPredicate, 0, 202, 101, // Skip to: 40641 +/* 14583 */ MCD_OPC_Decode, 219, 17, 126, // Opcode: UQXTNv8i16 +/* 14587 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 14666 +/* 14591 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14594 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14612 +/* 14598 */ MCD_OPC_CheckPredicate, 0, 183, 101, // Skip to: 40641 +/* 14602 */ MCD_OPC_CheckField, 21, 1, 1, 177, 101, // Skip to: 40641 +/* 14608 */ MCD_OPC_Decode, 168, 12, 89, // Opcode: SQSHLv4i16 +/* 14612 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14630 +/* 14616 */ MCD_OPC_CheckPredicate, 0, 165, 101, // Skip to: 40641 +/* 14620 */ MCD_OPC_CheckField, 21, 1, 1, 159, 101, // Skip to: 40641 +/* 14626 */ MCD_OPC_Decode, 184, 17, 89, // Opcode: UQSHLv4i16 +/* 14630 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14648 +/* 14634 */ MCD_OPC_CheckPredicate, 0, 147, 101, // Skip to: 40641 +/* 14638 */ MCD_OPC_CheckField, 21, 1, 1, 141, 101, // Skip to: 40641 +/* 14644 */ MCD_OPC_Decode, 172, 12, 112, // Opcode: SQSHLv8i16 +/* 14648 */ MCD_OPC_FilterValue, 3, 133, 101, // Skip to: 40641 +/* 14652 */ MCD_OPC_CheckPredicate, 0, 129, 101, // Skip to: 40641 +/* 14656 */ MCD_OPC_CheckField, 21, 1, 1, 123, 101, // Skip to: 40641 +/* 14662 */ MCD_OPC_Decode, 188, 17, 112, // Opcode: UQSHLv8i16 +/* 14666 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 14745 +/* 14670 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14673 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14691 +/* 14677 */ MCD_OPC_CheckPredicate, 0, 104, 101, // Skip to: 40641 +/* 14681 */ MCD_OPC_CheckField, 21, 1, 1, 98, 101, // Skip to: 40641 +/* 14687 */ MCD_OPC_Decode, 203, 9, 105, // Opcode: SABALv4i16_v4i32 +/* 14691 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14709 +/* 14695 */ MCD_OPC_CheckPredicate, 0, 86, 101, // Skip to: 40641 +/* 14699 */ MCD_OPC_CheckField, 21, 1, 1, 80, 101, // Skip to: 40641 +/* 14705 */ MCD_OPC_Decode, 237, 15, 105, // Opcode: UABALv4i16_v4i32 +/* 14709 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14727 +/* 14713 */ MCD_OPC_CheckPredicate, 0, 68, 101, // Skip to: 40641 +/* 14717 */ MCD_OPC_CheckField, 21, 1, 1, 62, 101, // Skip to: 40641 +/* 14723 */ MCD_OPC_Decode, 205, 9, 120, // Opcode: SABALv8i16_v4i32 +/* 14727 */ MCD_OPC_FilterValue, 3, 54, 101, // Skip to: 40641 +/* 14731 */ MCD_OPC_CheckPredicate, 0, 50, 101, // Skip to: 40641 +/* 14735 */ MCD_OPC_CheckField, 21, 1, 1, 44, 101, // Skip to: 40641 +/* 14741 */ MCD_OPC_Decode, 239, 15, 120, // Opcode: UABALv8i16_v4i32 +/* 14745 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 14824 +/* 14749 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14752 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14770 +/* 14756 */ MCD_OPC_CheckPredicate, 0, 25, 101, // Skip to: 40641 +/* 14760 */ MCD_OPC_CheckField, 21, 1, 1, 19, 101, // Skip to: 40641 +/* 14766 */ MCD_OPC_Decode, 241, 12, 89, // Opcode: SRSHLv4i16 +/* 14770 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14788 +/* 14774 */ MCD_OPC_CheckPredicate, 0, 7, 101, // Skip to: 40641 +/* 14778 */ MCD_OPC_CheckField, 21, 1, 1, 1, 101, // Skip to: 40641 +/* 14784 */ MCD_OPC_Decode, 233, 17, 89, // Opcode: URSHLv4i16 +/* 14788 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14806 +/* 14792 */ MCD_OPC_CheckPredicate, 0, 245, 100, // Skip to: 40641 +/* 14796 */ MCD_OPC_CheckField, 21, 1, 1, 239, 100, // Skip to: 40641 +/* 14802 */ MCD_OPC_Decode, 243, 12, 112, // Opcode: SRSHLv8i16 +/* 14806 */ MCD_OPC_FilterValue, 3, 231, 100, // Skip to: 40641 +/* 14810 */ MCD_OPC_CheckPredicate, 0, 227, 100, // Skip to: 40641 +/* 14814 */ MCD_OPC_CheckField, 21, 1, 1, 221, 100, // Skip to: 40641 +/* 14820 */ MCD_OPC_Decode, 235, 17, 112, // Opcode: URSHLv8i16 +/* 14824 */ MCD_OPC_FilterValue, 22, 75, 0, // Skip to: 14903 +/* 14828 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14831 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14849 +/* 14835 */ MCD_OPC_CheckPredicate, 0, 202, 100, // Skip to: 40641 +/* 14839 */ MCD_OPC_CheckField, 21, 1, 0, 196, 100, // Skip to: 40641 +/* 14845 */ MCD_OPC_Decode, 190, 18, 89, // Opcode: UZP2v4i16 +/* 14849 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14867 +/* 14853 */ MCD_OPC_CheckPredicate, 0, 184, 100, // Skip to: 40641 +/* 14857 */ MCD_OPC_CheckField, 16, 6, 32, 178, 100, // Skip to: 40641 +/* 14863 */ MCD_OPC_Decode, 167, 9, 90, // Opcode: RBITv8i8 +/* 14867 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14885 +/* 14871 */ MCD_OPC_CheckPredicate, 0, 166, 100, // Skip to: 40641 +/* 14875 */ MCD_OPC_CheckField, 21, 1, 0, 160, 100, // Skip to: 40641 +/* 14881 */ MCD_OPC_Decode, 192, 18, 112, // Opcode: UZP2v8i16 +/* 14885 */ MCD_OPC_FilterValue, 3, 152, 100, // Skip to: 40641 +/* 14889 */ MCD_OPC_CheckPredicate, 0, 148, 100, // Skip to: 40641 +/* 14893 */ MCD_OPC_CheckField, 16, 6, 32, 142, 100, // Skip to: 40641 +/* 14899 */ MCD_OPC_Decode, 166, 9, 117, // Opcode: RBITv16i8 +/* 14903 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 14982 +/* 14907 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14910 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14928 +/* 14914 */ MCD_OPC_CheckPredicate, 0, 123, 100, // Skip to: 40641 +/* 14918 */ MCD_OPC_CheckField, 21, 1, 1, 117, 100, // Skip to: 40641 +/* 14924 */ MCD_OPC_Decode, 249, 11, 89, // Opcode: SQRSHLv4i16 +/* 14928 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14946 +/* 14932 */ MCD_OPC_CheckPredicate, 0, 105, 100, // Skip to: 40641 +/* 14936 */ MCD_OPC_CheckField, 21, 1, 1, 99, 100, // Skip to: 40641 +/* 14942 */ MCD_OPC_Decode, 157, 17, 89, // Opcode: UQRSHLv4i16 +/* 14946 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14964 +/* 14950 */ MCD_OPC_CheckPredicate, 0, 87, 100, // Skip to: 40641 +/* 14954 */ MCD_OPC_CheckField, 21, 1, 1, 81, 100, // Skip to: 40641 +/* 14960 */ MCD_OPC_Decode, 251, 11, 112, // Opcode: SQRSHLv8i16 +/* 14964 */ MCD_OPC_FilterValue, 3, 73, 100, // Skip to: 40641 +/* 14968 */ MCD_OPC_CheckPredicate, 0, 69, 100, // Skip to: 40641 +/* 14972 */ MCD_OPC_CheckField, 21, 1, 1, 63, 100, // Skip to: 40641 +/* 14978 */ MCD_OPC_Decode, 159, 17, 112, // Opcode: UQRSHLv8i16 +/* 14982 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 15061 +/* 14986 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 14989 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15007 +/* 14993 */ MCD_OPC_CheckPredicate, 0, 44, 100, // Skip to: 40641 +/* 14997 */ MCD_OPC_CheckField, 21, 1, 1, 38, 100, // Skip to: 40641 +/* 15003 */ MCD_OPC_Decode, 153, 15, 103, // Opcode: SUBHNv4i32_v4i16 +/* 15007 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15025 +/* 15011 */ MCD_OPC_CheckPredicate, 0, 26, 100, // Skip to: 40641 +/* 15015 */ MCD_OPC_CheckField, 21, 1, 1, 20, 100, // Skip to: 40641 +/* 15021 */ MCD_OPC_Decode, 197, 9, 103, // Opcode: RSUBHNv4i32_v4i16 +/* 15025 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15043 +/* 15029 */ MCD_OPC_CheckPredicate, 0, 8, 100, // Skip to: 40641 +/* 15033 */ MCD_OPC_CheckField, 21, 1, 1, 2, 100, // Skip to: 40641 +/* 15039 */ MCD_OPC_Decode, 154, 15, 120, // Opcode: SUBHNv4i32_v8i16 +/* 15043 */ MCD_OPC_FilterValue, 3, 250, 99, // Skip to: 40641 +/* 15047 */ MCD_OPC_CheckPredicate, 0, 246, 99, // Skip to: 40641 +/* 15051 */ MCD_OPC_CheckField, 21, 1, 1, 240, 99, // Skip to: 40641 +/* 15057 */ MCD_OPC_Decode, 198, 9, 120, // Opcode: RSUBHNv4i32_v8i16 +/* 15061 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 15140 +/* 15065 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15068 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15086 +/* 15072 */ MCD_OPC_CheckPredicate, 0, 221, 99, // Skip to: 40641 +/* 15076 */ MCD_OPC_CheckField, 21, 1, 1, 215, 99, // Skip to: 40641 +/* 15082 */ MCD_OPC_Decode, 218, 10, 89, // Opcode: SMAXv4i16 +/* 15086 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15104 +/* 15090 */ MCD_OPC_CheckPredicate, 0, 203, 99, // Skip to: 40641 +/* 15094 */ MCD_OPC_CheckField, 21, 1, 1, 197, 99, // Skip to: 40641 +/* 15100 */ MCD_OPC_Decode, 210, 16, 89, // Opcode: UMAXv4i16 +/* 15104 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15122 +/* 15108 */ MCD_OPC_CheckPredicate, 0, 185, 99, // Skip to: 40641 +/* 15112 */ MCD_OPC_CheckField, 21, 1, 1, 179, 99, // Skip to: 40641 +/* 15118 */ MCD_OPC_Decode, 220, 10, 112, // Opcode: SMAXv8i16 +/* 15122 */ MCD_OPC_FilterValue, 3, 171, 99, // Skip to: 40641 +/* 15126 */ MCD_OPC_CheckPredicate, 0, 167, 99, // Skip to: 40641 +/* 15130 */ MCD_OPC_CheckField, 21, 1, 1, 161, 99, // Skip to: 40641 +/* 15136 */ MCD_OPC_Decode, 212, 16, 112, // Opcode: UMAXv8i16 +/* 15140 */ MCD_OPC_FilterValue, 26, 165, 0, // Skip to: 15309 +/* 15144 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15147 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15197 +/* 15151 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 15154 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15166 +/* 15158 */ MCD_OPC_CheckPredicate, 0, 135, 99, // Skip to: 40641 +/* 15162 */ MCD_OPC_Decode, 231, 15, 89, // Opcode: TRN2v4i16 +/* 15166 */ MCD_OPC_FilterValue, 1, 127, 99, // Skip to: 40641 +/* 15170 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15173 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15185 +/* 15177 */ MCD_OPC_CheckPredicate, 0, 116, 99, // Skip to: 40641 +/* 15181 */ MCD_OPC_Decode, 227, 9, 99, // Opcode: SADALPv4i16_v2i32 +/* 15185 */ MCD_OPC_FilterValue, 1, 108, 99, // Skip to: 40641 +/* 15189 */ MCD_OPC_CheckPredicate, 0, 104, 99, // Skip to: 40641 +/* 15193 */ MCD_OPC_Decode, 198, 3, 95, // Opcode: FCVTNv2i32 +/* 15197 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 15228 +/* 15201 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 15204 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15216 +/* 15208 */ MCD_OPC_CheckPredicate, 0, 85, 99, // Skip to: 40641 +/* 15212 */ MCD_OPC_Decode, 133, 16, 99, // Opcode: UADALPv4i16_v2i32 +/* 15216 */ MCD_OPC_FilterValue, 33, 77, 99, // Skip to: 40641 +/* 15220 */ MCD_OPC_CheckPredicate, 0, 73, 99, // Skip to: 40641 +/* 15224 */ MCD_OPC_Decode, 223, 3, 95, // Opcode: FCVTXNv2f32 +/* 15228 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15278 +/* 15232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 15235 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15247 +/* 15239 */ MCD_OPC_CheckPredicate, 0, 54, 99, // Skip to: 40641 +/* 15243 */ MCD_OPC_Decode, 233, 15, 112, // Opcode: TRN2v8i16 +/* 15247 */ MCD_OPC_FilterValue, 1, 46, 99, // Skip to: 40641 +/* 15251 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15254 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15266 +/* 15258 */ MCD_OPC_CheckPredicate, 0, 35, 99, // Skip to: 40641 +/* 15262 */ MCD_OPC_Decode, 229, 9, 126, // Opcode: SADALPv8i16_v4i32 +/* 15266 */ MCD_OPC_FilterValue, 1, 27, 99, // Skip to: 40641 +/* 15270 */ MCD_OPC_CheckPredicate, 0, 23, 99, // Skip to: 40641 +/* 15274 */ MCD_OPC_Decode, 200, 3, 126, // Opcode: FCVTNv4i32 +/* 15278 */ MCD_OPC_FilterValue, 3, 15, 99, // Skip to: 40641 +/* 15282 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 15285 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15297 +/* 15289 */ MCD_OPC_CheckPredicate, 0, 4, 99, // Skip to: 40641 +/* 15293 */ MCD_OPC_Decode, 135, 16, 126, // Opcode: UADALPv8i16_v4i32 +/* 15297 */ MCD_OPC_FilterValue, 33, 252, 98, // Skip to: 40641 +/* 15301 */ MCD_OPC_CheckPredicate, 0, 248, 98, // Skip to: 40641 +/* 15305 */ MCD_OPC_Decode, 224, 3, 126, // Opcode: FCVTXNv4f32 +/* 15309 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 15388 +/* 15313 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15316 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15334 +/* 15320 */ MCD_OPC_CheckPredicate, 0, 229, 98, // Skip to: 40641 +/* 15324 */ MCD_OPC_CheckField, 21, 1, 1, 223, 98, // Skip to: 40641 +/* 15330 */ MCD_OPC_Decode, 236, 10, 89, // Opcode: SMINv4i16 +/* 15334 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15352 +/* 15338 */ MCD_OPC_CheckPredicate, 0, 211, 98, // Skip to: 40641 +/* 15342 */ MCD_OPC_CheckField, 21, 1, 1, 205, 98, // Skip to: 40641 +/* 15348 */ MCD_OPC_Decode, 227, 16, 89, // Opcode: UMINv4i16 +/* 15352 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15370 +/* 15356 */ MCD_OPC_CheckPredicate, 0, 193, 98, // Skip to: 40641 +/* 15360 */ MCD_OPC_CheckField, 21, 1, 1, 187, 98, // Skip to: 40641 +/* 15366 */ MCD_OPC_Decode, 238, 10, 112, // Opcode: SMINv8i16 +/* 15370 */ MCD_OPC_FilterValue, 3, 179, 98, // Skip to: 40641 +/* 15374 */ MCD_OPC_CheckPredicate, 0, 175, 98, // Skip to: 40641 +/* 15378 */ MCD_OPC_CheckField, 21, 1, 1, 169, 98, // Skip to: 40641 +/* 15384 */ MCD_OPC_Decode, 229, 16, 112, // Opcode: UMINv8i16 +/* 15388 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 15467 +/* 15392 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15395 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15413 +/* 15399 */ MCD_OPC_CheckPredicate, 0, 150, 98, // Skip to: 40641 +/* 15403 */ MCD_OPC_CheckField, 21, 1, 1, 144, 98, // Skip to: 40641 +/* 15409 */ MCD_OPC_Decode, 215, 9, 85, // Opcode: SABDLv4i16_v4i32 +/* 15413 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15431 +/* 15417 */ MCD_OPC_CheckPredicate, 0, 132, 98, // Skip to: 40641 +/* 15421 */ MCD_OPC_CheckField, 21, 1, 1, 126, 98, // Skip to: 40641 +/* 15427 */ MCD_OPC_Decode, 249, 15, 85, // Opcode: UABDLv4i16_v4i32 +/* 15431 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15449 +/* 15435 */ MCD_OPC_CheckPredicate, 0, 114, 98, // Skip to: 40641 +/* 15439 */ MCD_OPC_CheckField, 21, 1, 1, 108, 98, // Skip to: 40641 +/* 15445 */ MCD_OPC_Decode, 217, 9, 112, // Opcode: SABDLv8i16_v4i32 +/* 15449 */ MCD_OPC_FilterValue, 3, 100, 98, // Skip to: 40641 +/* 15453 */ MCD_OPC_CheckPredicate, 0, 96, 98, // Skip to: 40641 +/* 15457 */ MCD_OPC_CheckField, 21, 1, 1, 90, 98, // Skip to: 40641 +/* 15463 */ MCD_OPC_Decode, 251, 15, 112, // Opcode: UABDLv8i16_v4i32 +/* 15467 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 15546 +/* 15471 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15474 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15492 +/* 15478 */ MCD_OPC_CheckPredicate, 0, 71, 98, // Skip to: 40641 +/* 15482 */ MCD_OPC_CheckField, 21, 1, 1, 65, 98, // Skip to: 40641 +/* 15488 */ MCD_OPC_Decode, 221, 9, 89, // Opcode: SABDv4i16 +/* 15492 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15510 +/* 15496 */ MCD_OPC_CheckPredicate, 0, 53, 98, // Skip to: 40641 +/* 15500 */ MCD_OPC_CheckField, 21, 1, 1, 47, 98, // Skip to: 40641 +/* 15506 */ MCD_OPC_Decode, 255, 15, 89, // Opcode: UABDv4i16 +/* 15510 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15528 +/* 15514 */ MCD_OPC_CheckPredicate, 0, 35, 98, // Skip to: 40641 +/* 15518 */ MCD_OPC_CheckField, 21, 1, 1, 29, 98, // Skip to: 40641 +/* 15524 */ MCD_OPC_Decode, 223, 9, 112, // Opcode: SABDv8i16 +/* 15528 */ MCD_OPC_FilterValue, 3, 21, 98, // Skip to: 40641 +/* 15532 */ MCD_OPC_CheckPredicate, 0, 17, 98, // Skip to: 40641 +/* 15536 */ MCD_OPC_CheckField, 21, 1, 1, 11, 98, // Skip to: 40641 +/* 15542 */ MCD_OPC_Decode, 129, 16, 112, // Opcode: UABDv8i16 +/* 15546 */ MCD_OPC_FilterValue, 30, 139, 0, // Skip to: 15689 +/* 15550 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15553 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15603 +/* 15557 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 15560 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15572 +/* 15564 */ MCD_OPC_CheckPredicate, 0, 241, 97, // Skip to: 40641 +/* 15568 */ MCD_OPC_Decode, 210, 18, 89, // Opcode: ZIP2v4i16 +/* 15572 */ MCD_OPC_FilterValue, 1, 233, 97, // Skip to: 40641 +/* 15576 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15579 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15591 +/* 15583 */ MCD_OPC_CheckPredicate, 0, 222, 97, // Skip to: 40641 +/* 15587 */ MCD_OPC_Decode, 156, 11, 90, // Opcode: SQABSv4i16 +/* 15591 */ MCD_OPC_FilterValue, 1, 214, 97, // Skip to: 40641 +/* 15595 */ MCD_OPC_CheckPredicate, 0, 210, 97, // Skip to: 40641 +/* 15599 */ MCD_OPC_Decode, 158, 3, 108, // Opcode: FCVTLv2i32 +/* 15603 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15621 +/* 15607 */ MCD_OPC_CheckPredicate, 0, 198, 97, // Skip to: 40641 +/* 15611 */ MCD_OPC_CheckField, 16, 6, 32, 192, 97, // Skip to: 40641 +/* 15617 */ MCD_OPC_Decode, 226, 11, 90, // Opcode: SQNEGv4i16 +/* 15621 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15671 +/* 15625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 15628 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15640 +/* 15632 */ MCD_OPC_CheckPredicate, 0, 173, 97, // Skip to: 40641 +/* 15636 */ MCD_OPC_Decode, 212, 18, 112, // Opcode: ZIP2v8i16 +/* 15640 */ MCD_OPC_FilterValue, 1, 165, 97, // Skip to: 40641 +/* 15644 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15647 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15659 +/* 15651 */ MCD_OPC_CheckPredicate, 0, 154, 97, // Skip to: 40641 +/* 15655 */ MCD_OPC_Decode, 158, 11, 117, // Opcode: SQABSv8i16 +/* 15659 */ MCD_OPC_FilterValue, 1, 146, 97, // Skip to: 40641 +/* 15663 */ MCD_OPC_CheckPredicate, 0, 142, 97, // Skip to: 40641 +/* 15667 */ MCD_OPC_Decode, 160, 3, 117, // Opcode: FCVTLv4i32 +/* 15671 */ MCD_OPC_FilterValue, 3, 134, 97, // Skip to: 40641 +/* 15675 */ MCD_OPC_CheckPredicate, 0, 130, 97, // Skip to: 40641 +/* 15679 */ MCD_OPC_CheckField, 16, 6, 32, 124, 97, // Skip to: 40641 +/* 15685 */ MCD_OPC_Decode, 228, 11, 117, // Opcode: SQNEGv8i16 +/* 15689 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 15768 +/* 15693 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15696 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15714 +/* 15700 */ MCD_OPC_CheckPredicate, 0, 105, 97, // Skip to: 40641 +/* 15704 */ MCD_OPC_CheckField, 21, 1, 1, 99, 97, // Skip to: 40641 +/* 15710 */ MCD_OPC_Decode, 209, 9, 109, // Opcode: SABAv4i16 +/* 15714 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15732 +/* 15718 */ MCD_OPC_CheckPredicate, 0, 87, 97, // Skip to: 40641 +/* 15722 */ MCD_OPC_CheckField, 21, 1, 1, 81, 97, // Skip to: 40641 +/* 15728 */ MCD_OPC_Decode, 243, 15, 109, // Opcode: UABAv4i16 +/* 15732 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15750 +/* 15736 */ MCD_OPC_CheckPredicate, 0, 69, 97, // Skip to: 40641 +/* 15740 */ MCD_OPC_CheckField, 21, 1, 1, 63, 97, // Skip to: 40641 +/* 15746 */ MCD_OPC_Decode, 211, 9, 120, // Opcode: SABAv8i16 +/* 15750 */ MCD_OPC_FilterValue, 3, 55, 97, // Skip to: 40641 +/* 15754 */ MCD_OPC_CheckPredicate, 0, 51, 97, // Skip to: 40641 +/* 15758 */ MCD_OPC_CheckField, 21, 1, 1, 45, 97, // Skip to: 40641 +/* 15764 */ MCD_OPC_Decode, 245, 15, 120, // Opcode: UABAv8i16 +/* 15768 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 15847 +/* 15772 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15775 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15793 +/* 15779 */ MCD_OPC_CheckPredicate, 0, 26, 97, // Skip to: 40641 +/* 15783 */ MCD_OPC_CheckField, 21, 1, 1, 20, 97, // Skip to: 40641 +/* 15789 */ MCD_OPC_Decode, 244, 10, 105, // Opcode: SMLALv4i16_v4i32 +/* 15793 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15811 +/* 15797 */ MCD_OPC_CheckPredicate, 0, 8, 97, // Skip to: 40641 +/* 15801 */ MCD_OPC_CheckField, 21, 1, 1, 2, 97, // Skip to: 40641 +/* 15807 */ MCD_OPC_Decode, 235, 16, 105, // Opcode: UMLALv4i16_v4i32 +/* 15811 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15829 +/* 15815 */ MCD_OPC_CheckPredicate, 0, 246, 96, // Skip to: 40641 +/* 15819 */ MCD_OPC_CheckField, 21, 1, 1, 240, 96, // Skip to: 40641 +/* 15825 */ MCD_OPC_Decode, 248, 10, 120, // Opcode: SMLALv8i16_v4i32 +/* 15829 */ MCD_OPC_FilterValue, 3, 232, 96, // Skip to: 40641 +/* 15833 */ MCD_OPC_CheckPredicate, 0, 228, 96, // Skip to: 40641 +/* 15837 */ MCD_OPC_CheckField, 21, 1, 1, 222, 96, // Skip to: 40641 +/* 15843 */ MCD_OPC_Decode, 239, 16, 120, // Opcode: UMLALv8i16_v4i32 +/* 15847 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 15924 +/* 15851 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15854 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 15871 +/* 15858 */ MCD_OPC_CheckPredicate, 0, 203, 96, // Skip to: 40641 +/* 15862 */ MCD_OPC_CheckField, 21, 1, 1, 197, 96, // Skip to: 40641 +/* 15868 */ MCD_OPC_Decode, 75, 89, // Opcode: ADDv4i16 +/* 15871 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15889 +/* 15875 */ MCD_OPC_CheckPredicate, 0, 186, 96, // Skip to: 40641 +/* 15879 */ MCD_OPC_CheckField, 21, 1, 1, 180, 96, // Skip to: 40641 +/* 15885 */ MCD_OPC_Decode, 179, 15, 89, // Opcode: SUBv4i16 +/* 15889 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 15906 +/* 15893 */ MCD_OPC_CheckPredicate, 0, 168, 96, // Skip to: 40641 +/* 15897 */ MCD_OPC_CheckField, 21, 1, 1, 162, 96, // Skip to: 40641 +/* 15903 */ MCD_OPC_Decode, 77, 112, // Opcode: ADDv8i16 +/* 15906 */ MCD_OPC_FilterValue, 3, 155, 96, // Skip to: 40641 +/* 15910 */ MCD_OPC_CheckPredicate, 0, 151, 96, // Skip to: 40641 +/* 15914 */ MCD_OPC_CheckField, 21, 1, 1, 145, 96, // Skip to: 40641 +/* 15920 */ MCD_OPC_Decode, 181, 15, 112, // Opcode: SUBv8i16 +/* 15924 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 16029 +/* 15928 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 15931 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15949 +/* 15935 */ MCD_OPC_CheckPredicate, 0, 126, 96, // Skip to: 40641 +/* 15939 */ MCD_OPC_CheckField, 16, 6, 32, 120, 96, // Skip to: 40641 +/* 15945 */ MCD_OPC_Decode, 201, 1, 90, // Opcode: CMGTv4i16rz +/* 15949 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15967 +/* 15953 */ MCD_OPC_CheckPredicate, 0, 108, 96, // Skip to: 40641 +/* 15957 */ MCD_OPC_CheckField, 16, 6, 32, 102, 96, // Skip to: 40641 +/* 15963 */ MCD_OPC_Decode, 185, 1, 90, // Opcode: CMGEv4i16rz +/* 15967 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 15998 +/* 15971 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 15974 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15986 +/* 15978 */ MCD_OPC_CheckPredicate, 0, 83, 96, // Skip to: 40641 +/* 15982 */ MCD_OPC_Decode, 205, 1, 117, // Opcode: CMGTv8i16rz +/* 15986 */ MCD_OPC_FilterValue, 33, 75, 96, // Skip to: 40641 +/* 15990 */ MCD_OPC_CheckPredicate, 0, 71, 96, // Skip to: 40641 +/* 15994 */ MCD_OPC_Decode, 170, 5, 117, // Opcode: FRINTNv2f64 +/* 15998 */ MCD_OPC_FilterValue, 3, 63, 96, // Skip to: 40641 +/* 16002 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16005 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16017 +/* 16009 */ MCD_OPC_CheckPredicate, 0, 52, 96, // Skip to: 40641 +/* 16013 */ MCD_OPC_Decode, 189, 1, 117, // Opcode: CMGEv8i16rz +/* 16017 */ MCD_OPC_FilterValue, 33, 44, 96, // Skip to: 40641 +/* 16021 */ MCD_OPC_CheckPredicate, 0, 40, 96, // Skip to: 40641 +/* 16025 */ MCD_OPC_Decode, 155, 5, 117, // Opcode: FRINTAv2f64 +/* 16029 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 16108 +/* 16033 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16036 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16054 +/* 16040 */ MCD_OPC_CheckPredicate, 0, 21, 96, // Skip to: 40641 +/* 16044 */ MCD_OPC_CheckField, 21, 1, 1, 15, 96, // Skip to: 40641 +/* 16050 */ MCD_OPC_Decode, 244, 1, 89, // Opcode: CMTSTv4i16 +/* 16054 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16072 +/* 16058 */ MCD_OPC_CheckPredicate, 0, 3, 96, // Skip to: 40641 +/* 16062 */ MCD_OPC_CheckField, 21, 1, 1, 253, 95, // Skip to: 40641 +/* 16068 */ MCD_OPC_Decode, 168, 1, 89, // Opcode: CMEQv4i16 +/* 16072 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16090 +/* 16076 */ MCD_OPC_CheckPredicate, 0, 241, 95, // Skip to: 40641 +/* 16080 */ MCD_OPC_CheckField, 21, 1, 1, 235, 95, // Skip to: 40641 +/* 16086 */ MCD_OPC_Decode, 246, 1, 112, // Opcode: CMTSTv8i16 +/* 16090 */ MCD_OPC_FilterValue, 3, 227, 95, // Skip to: 40641 +/* 16094 */ MCD_OPC_CheckPredicate, 0, 223, 95, // Skip to: 40641 +/* 16098 */ MCD_OPC_CheckField, 21, 1, 1, 217, 95, // Skip to: 40641 +/* 16104 */ MCD_OPC_Decode, 172, 1, 112, // Opcode: CMEQv8i16 +/* 16108 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 16151 +/* 16112 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16115 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16133 +/* 16119 */ MCD_OPC_CheckPredicate, 0, 198, 95, // Skip to: 40641 +/* 16123 */ MCD_OPC_CheckField, 21, 1, 1, 192, 95, // Skip to: 40641 +/* 16129 */ MCD_OPC_Decode, 178, 11, 105, // Opcode: SQDMLALv4i16_v4i32 +/* 16133 */ MCD_OPC_FilterValue, 2, 184, 95, // Skip to: 40641 +/* 16137 */ MCD_OPC_CheckPredicate, 0, 180, 95, // Skip to: 40641 +/* 16141 */ MCD_OPC_CheckField, 21, 1, 1, 174, 95, // Skip to: 40641 +/* 16147 */ MCD_OPC_Decode, 182, 11, 120, // Opcode: SQDMLALv8i16_v4i32 +/* 16151 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 16230 +/* 16155 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16158 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16176 +/* 16162 */ MCD_OPC_CheckPredicate, 0, 155, 95, // Skip to: 40641 +/* 16166 */ MCD_OPC_CheckField, 21, 1, 1, 149, 95, // Skip to: 40641 +/* 16172 */ MCD_OPC_Decode, 185, 8, 109, // Opcode: MLAv4i16 +/* 16176 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16194 +/* 16180 */ MCD_OPC_CheckPredicate, 0, 137, 95, // Skip to: 40641 +/* 16184 */ MCD_OPC_CheckField, 21, 1, 1, 131, 95, // Skip to: 40641 +/* 16190 */ MCD_OPC_Decode, 195, 8, 109, // Opcode: MLSv4i16 +/* 16194 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16212 +/* 16198 */ MCD_OPC_CheckPredicate, 0, 119, 95, // Skip to: 40641 +/* 16202 */ MCD_OPC_CheckField, 21, 1, 1, 113, 95, // Skip to: 40641 +/* 16208 */ MCD_OPC_Decode, 189, 8, 120, // Opcode: MLAv8i16 +/* 16212 */ MCD_OPC_FilterValue, 3, 105, 95, // Skip to: 40641 +/* 16216 */ MCD_OPC_CheckPredicate, 0, 101, 95, // Skip to: 40641 +/* 16220 */ MCD_OPC_CheckField, 21, 1, 1, 95, 95, // Skip to: 40641 +/* 16226 */ MCD_OPC_Decode, 199, 8, 120, // Opcode: MLSv8i16 +/* 16230 */ MCD_OPC_FilterValue, 38, 101, 0, // Skip to: 16335 +/* 16234 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16237 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16255 +/* 16241 */ MCD_OPC_CheckPredicate, 0, 76, 95, // Skip to: 40641 +/* 16245 */ MCD_OPC_CheckField, 16, 6, 32, 70, 95, // Skip to: 40641 +/* 16251 */ MCD_OPC_Decode, 169, 1, 90, // Opcode: CMEQv4i16rz +/* 16255 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16273 +/* 16259 */ MCD_OPC_CheckPredicate, 0, 58, 95, // Skip to: 40641 +/* 16263 */ MCD_OPC_CheckField, 16, 6, 32, 52, 95, // Skip to: 40641 +/* 16269 */ MCD_OPC_Decode, 228, 1, 90, // Opcode: CMLEv4i16rz +/* 16273 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 16304 +/* 16277 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16280 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16292 +/* 16284 */ MCD_OPC_CheckPredicate, 0, 33, 95, // Skip to: 40641 +/* 16288 */ MCD_OPC_Decode, 173, 1, 117, // Opcode: CMEQv8i16rz +/* 16292 */ MCD_OPC_FilterValue, 33, 25, 95, // Skip to: 40641 +/* 16296 */ MCD_OPC_CheckPredicate, 0, 21, 95, // Skip to: 40641 +/* 16300 */ MCD_OPC_Decode, 165, 5, 117, // Opcode: FRINTMv2f64 +/* 16304 */ MCD_OPC_FilterValue, 3, 13, 95, // Skip to: 40641 +/* 16308 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16311 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16323 +/* 16315 */ MCD_OPC_CheckPredicate, 0, 2, 95, // Skip to: 40641 +/* 16319 */ MCD_OPC_Decode, 230, 1, 117, // Opcode: CMLEv8i16rz +/* 16323 */ MCD_OPC_FilterValue, 33, 250, 94, // Skip to: 40641 +/* 16327 */ MCD_OPC_CheckPredicate, 0, 246, 94, // Skip to: 40641 +/* 16331 */ MCD_OPC_Decode, 180, 5, 117, // Opcode: FRINTXv2f64 +/* 16335 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 16378 +/* 16339 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16342 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16360 +/* 16346 */ MCD_OPC_CheckPredicate, 0, 227, 94, // Skip to: 40641 +/* 16350 */ MCD_OPC_CheckField, 21, 1, 1, 221, 94, // Skip to: 40641 +/* 16356 */ MCD_OPC_Decode, 234, 8, 89, // Opcode: MULv4i16 +/* 16360 */ MCD_OPC_FilterValue, 2, 213, 94, // Skip to: 40641 +/* 16364 */ MCD_OPC_CheckPredicate, 0, 209, 94, // Skip to: 40641 +/* 16368 */ MCD_OPC_CheckField, 21, 1, 1, 203, 94, // Skip to: 40641 +/* 16374 */ MCD_OPC_Decode, 238, 8, 112, // Opcode: MULv8i16 +/* 16378 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 16457 +/* 16382 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16385 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16403 +/* 16389 */ MCD_OPC_CheckPredicate, 0, 184, 94, // Skip to: 40641 +/* 16393 */ MCD_OPC_CheckField, 21, 1, 1, 178, 94, // Skip to: 40641 +/* 16399 */ MCD_OPC_Decode, 254, 10, 105, // Opcode: SMLSLv4i16_v4i32 +/* 16403 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16421 +/* 16407 */ MCD_OPC_CheckPredicate, 0, 166, 94, // Skip to: 40641 +/* 16411 */ MCD_OPC_CheckField, 21, 1, 1, 160, 94, // Skip to: 40641 +/* 16417 */ MCD_OPC_Decode, 245, 16, 105, // Opcode: UMLSLv4i16_v4i32 +/* 16421 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16439 +/* 16425 */ MCD_OPC_CheckPredicate, 0, 148, 94, // Skip to: 40641 +/* 16429 */ MCD_OPC_CheckField, 21, 1, 1, 142, 94, // Skip to: 40641 +/* 16435 */ MCD_OPC_Decode, 130, 11, 120, // Opcode: SMLSLv8i16_v4i32 +/* 16439 */ MCD_OPC_FilterValue, 3, 134, 94, // Skip to: 40641 +/* 16443 */ MCD_OPC_CheckPredicate, 0, 130, 94, // Skip to: 40641 +/* 16447 */ MCD_OPC_CheckField, 21, 1, 1, 124, 94, // Skip to: 40641 +/* 16453 */ MCD_OPC_Decode, 249, 16, 120, // Opcode: UMLSLv8i16_v4i32 +/* 16457 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 16536 +/* 16461 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16464 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16482 +/* 16468 */ MCD_OPC_CheckPredicate, 0, 105, 94, // Skip to: 40641 +/* 16472 */ MCD_OPC_CheckField, 21, 1, 1, 99, 94, // Skip to: 40641 +/* 16478 */ MCD_OPC_Decode, 207, 10, 89, // Opcode: SMAXPv4i16 +/* 16482 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16500 +/* 16486 */ MCD_OPC_CheckPredicate, 0, 87, 94, // Skip to: 40641 +/* 16490 */ MCD_OPC_CheckField, 21, 1, 1, 81, 94, // Skip to: 40641 +/* 16496 */ MCD_OPC_Decode, 199, 16, 89, // Opcode: UMAXPv4i16 +/* 16500 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16518 +/* 16504 */ MCD_OPC_CheckPredicate, 0, 69, 94, // Skip to: 40641 +/* 16508 */ MCD_OPC_CheckField, 21, 1, 1, 63, 94, // Skip to: 40641 +/* 16514 */ MCD_OPC_Decode, 209, 10, 112, // Opcode: SMAXPv8i16 +/* 16518 */ MCD_OPC_FilterValue, 3, 55, 94, // Skip to: 40641 +/* 16522 */ MCD_OPC_CheckPredicate, 0, 51, 94, // Skip to: 40641 +/* 16526 */ MCD_OPC_CheckField, 21, 1, 1, 45, 94, // Skip to: 40641 +/* 16532 */ MCD_OPC_Decode, 201, 16, 112, // Opcode: UMAXPv8i16 +/* 16536 */ MCD_OPC_FilterValue, 42, 179, 0, // Skip to: 16719 +/* 16540 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16543 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 16574 +/* 16547 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16550 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16562 +/* 16554 */ MCD_OPC_CheckPredicate, 0, 19, 94, // Skip to: 40641 +/* 16558 */ MCD_OPC_Decode, 236, 1, 90, // Opcode: CMLTv4i16rz +/* 16562 */ MCD_OPC_FilterValue, 2, 11, 94, // Skip to: 40641 +/* 16566 */ MCD_OPC_CheckPredicate, 0, 7, 94, // Skip to: 40641 +/* 16570 */ MCD_OPC_Decode, 238, 1, 117, // Opcode: CMLTv8i16rz +/* 16574 */ MCD_OPC_FilterValue, 33, 27, 0, // Skip to: 16605 +/* 16578 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16581 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16593 +/* 16585 */ MCD_OPC_CheckPredicate, 0, 244, 93, // Skip to: 40641 +/* 16589 */ MCD_OPC_Decode, 187, 3, 117, // Opcode: FCVTNSv2f64 +/* 16593 */ MCD_OPC_FilterValue, 3, 236, 93, // Skip to: 40641 +/* 16597 */ MCD_OPC_CheckPredicate, 0, 232, 93, // Skip to: 40641 +/* 16601 */ MCD_OPC_Decode, 196, 3, 117, // Opcode: FCVTNUv2f64 +/* 16605 */ MCD_OPC_FilterValue, 48, 53, 0, // Skip to: 16662 +/* 16609 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16612 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16624 +/* 16616 */ MCD_OPC_CheckPredicate, 0, 213, 93, // Skip to: 40641 +/* 16620 */ MCD_OPC_Decode, 212, 10, 100, // Opcode: SMAXVv4i16v +/* 16624 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16636 +/* 16628 */ MCD_OPC_CheckPredicate, 0, 201, 93, // Skip to: 40641 +/* 16632 */ MCD_OPC_Decode, 204, 16, 100, // Opcode: UMAXVv4i16v +/* 16636 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16649 +/* 16640 */ MCD_OPC_CheckPredicate, 0, 189, 93, // Skip to: 40641 +/* 16644 */ MCD_OPC_Decode, 214, 10, 131, 1, // Opcode: SMAXVv8i16v +/* 16649 */ MCD_OPC_FilterValue, 3, 180, 93, // Skip to: 40641 +/* 16653 */ MCD_OPC_CheckPredicate, 0, 176, 93, // Skip to: 40641 +/* 16657 */ MCD_OPC_Decode, 206, 16, 131, 1, // Opcode: UMAXVv8i16v +/* 16662 */ MCD_OPC_FilterValue, 49, 167, 93, // Skip to: 40641 +/* 16666 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16669 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16681 +/* 16673 */ MCD_OPC_CheckPredicate, 0, 156, 93, // Skip to: 40641 +/* 16677 */ MCD_OPC_Decode, 230, 10, 100, // Opcode: SMINVv4i16v +/* 16681 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16693 +/* 16685 */ MCD_OPC_CheckPredicate, 0, 144, 93, // Skip to: 40641 +/* 16689 */ MCD_OPC_Decode, 221, 16, 100, // Opcode: UMINVv4i16v +/* 16693 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16706 +/* 16697 */ MCD_OPC_CheckPredicate, 0, 132, 93, // Skip to: 40641 +/* 16701 */ MCD_OPC_Decode, 232, 10, 131, 1, // Opcode: SMINVv8i16v +/* 16706 */ MCD_OPC_FilterValue, 3, 123, 93, // Skip to: 40641 +/* 16710 */ MCD_OPC_CheckPredicate, 0, 119, 93, // Skip to: 40641 +/* 16714 */ MCD_OPC_Decode, 223, 16, 131, 1, // Opcode: UMINVv8i16v +/* 16719 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 16798 +/* 16723 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16726 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16744 +/* 16730 */ MCD_OPC_CheckPredicate, 0, 99, 93, // Skip to: 40641 +/* 16734 */ MCD_OPC_CheckField, 21, 1, 1, 93, 93, // Skip to: 40641 +/* 16740 */ MCD_OPC_Decode, 225, 10, 89, // Opcode: SMINPv4i16 +/* 16744 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16762 +/* 16748 */ MCD_OPC_CheckPredicate, 0, 81, 93, // Skip to: 40641 +/* 16752 */ MCD_OPC_CheckField, 21, 1, 1, 75, 93, // Skip to: 40641 +/* 16758 */ MCD_OPC_Decode, 216, 16, 89, // Opcode: UMINPv4i16 +/* 16762 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16780 +/* 16766 */ MCD_OPC_CheckPredicate, 0, 63, 93, // Skip to: 40641 +/* 16770 */ MCD_OPC_CheckField, 21, 1, 1, 57, 93, // Skip to: 40641 +/* 16776 */ MCD_OPC_Decode, 227, 10, 112, // Opcode: SMINPv8i16 +/* 16780 */ MCD_OPC_FilterValue, 3, 49, 93, // Skip to: 40641 +/* 16784 */ MCD_OPC_CheckPredicate, 0, 45, 93, // Skip to: 40641 +/* 16788 */ MCD_OPC_CheckField, 21, 1, 1, 39, 93, // Skip to: 40641 +/* 16794 */ MCD_OPC_Decode, 218, 16, 112, // Opcode: UMINPv8i16 +/* 16798 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 16841 +/* 16802 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16805 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16823 +/* 16809 */ MCD_OPC_CheckPredicate, 0, 20, 93, // Skip to: 40641 +/* 16813 */ MCD_OPC_CheckField, 21, 1, 1, 14, 93, // Skip to: 40641 +/* 16819 */ MCD_OPC_Decode, 190, 11, 105, // Opcode: SQDMLSLv4i16_v4i32 +/* 16823 */ MCD_OPC_FilterValue, 2, 6, 93, // Skip to: 40641 +/* 16827 */ MCD_OPC_CheckPredicate, 0, 2, 93, // Skip to: 40641 +/* 16831 */ MCD_OPC_CheckField, 21, 1, 1, 252, 92, // Skip to: 40641 +/* 16837 */ MCD_OPC_Decode, 194, 11, 120, // Opcode: SQDMLSLv8i16_v4i32 +/* 16841 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 16920 +/* 16845 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16848 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16866 +/* 16852 */ MCD_OPC_CheckPredicate, 0, 233, 92, // Skip to: 40641 +/* 16856 */ MCD_OPC_CheckField, 21, 1, 1, 227, 92, // Skip to: 40641 +/* 16862 */ MCD_OPC_Decode, 201, 11, 89, // Opcode: SQDMULHv4i16 +/* 16866 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16884 +/* 16870 */ MCD_OPC_CheckPredicate, 0, 215, 92, // Skip to: 40641 +/* 16874 */ MCD_OPC_CheckField, 21, 1, 1, 209, 92, // Skip to: 40641 +/* 16880 */ MCD_OPC_Decode, 236, 11, 89, // Opcode: SQRDMULHv4i16 +/* 16884 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16902 +/* 16888 */ MCD_OPC_CheckPredicate, 0, 197, 92, // Skip to: 40641 +/* 16892 */ MCD_OPC_CheckField, 21, 1, 1, 191, 92, // Skip to: 40641 +/* 16898 */ MCD_OPC_Decode, 205, 11, 112, // Opcode: SQDMULHv8i16 +/* 16902 */ MCD_OPC_FilterValue, 3, 183, 92, // Skip to: 40641 +/* 16906 */ MCD_OPC_CheckPredicate, 0, 179, 92, // Skip to: 40641 +/* 16910 */ MCD_OPC_CheckField, 21, 1, 1, 173, 92, // Skip to: 40641 +/* 16916 */ MCD_OPC_Decode, 240, 11, 112, // Opcode: SQRDMULHv8i16 +/* 16920 */ MCD_OPC_FilterValue, 46, 123, 0, // Skip to: 17047 +/* 16924 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 16927 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 16956 +/* 16931 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16934 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16945 +/* 16938 */ MCD_OPC_CheckPredicate, 0, 147, 92, // Skip to: 40641 +/* 16942 */ MCD_OPC_Decode, 26, 90, // Opcode: ABSv4i16 +/* 16945 */ MCD_OPC_FilterValue, 49, 140, 92, // Skip to: 40641 +/* 16949 */ MCD_OPC_CheckPredicate, 0, 136, 92, // Skip to: 40641 +/* 16953 */ MCD_OPC_Decode, 58, 100, // Opcode: ADDVv4i16v +/* 16956 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16974 +/* 16960 */ MCD_OPC_CheckPredicate, 0, 125, 92, // Skip to: 40641 +/* 16964 */ MCD_OPC_CheckField, 16, 6, 32, 119, 92, // Skip to: 40641 +/* 16970 */ MCD_OPC_Decode, 251, 8, 90, // Opcode: NEGv4i16 +/* 16974 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 17016 +/* 16978 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 16981 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16992 +/* 16985 */ MCD_OPC_CheckPredicate, 0, 100, 92, // Skip to: 40641 +/* 16989 */ MCD_OPC_Decode, 28, 117, // Opcode: ABSv8i16 +/* 16992 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 17004 +/* 16996 */ MCD_OPC_CheckPredicate, 0, 89, 92, // Skip to: 40641 +/* 17000 */ MCD_OPC_Decode, 169, 3, 117, // Opcode: FCVTMSv2f64 +/* 17004 */ MCD_OPC_FilterValue, 49, 81, 92, // Skip to: 40641 +/* 17008 */ MCD_OPC_CheckPredicate, 0, 77, 92, // Skip to: 40641 +/* 17012 */ MCD_OPC_Decode, 60, 131, 1, // Opcode: ADDVv8i16v +/* 17016 */ MCD_OPC_FilterValue, 3, 69, 92, // Skip to: 40641 +/* 17020 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 17023 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 17035 +/* 17027 */ MCD_OPC_CheckPredicate, 0, 58, 92, // Skip to: 40641 +/* 17031 */ MCD_OPC_Decode, 253, 8, 117, // Opcode: NEGv8i16 +/* 17035 */ MCD_OPC_FilterValue, 33, 50, 92, // Skip to: 40641 +/* 17039 */ MCD_OPC_CheckPredicate, 0, 46, 92, // Skip to: 40641 +/* 17043 */ MCD_OPC_Decode, 178, 3, 117, // Opcode: FCVTMUv2f64 +/* 17047 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 17088 +/* 17051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17054 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 17071 +/* 17058 */ MCD_OPC_CheckPredicate, 0, 27, 92, // Skip to: 40641 +/* 17062 */ MCD_OPC_CheckField, 21, 1, 1, 21, 92, // Skip to: 40641 +/* 17068 */ MCD_OPC_Decode, 44, 89, // Opcode: ADDPv4i16 +/* 17071 */ MCD_OPC_FilterValue, 2, 14, 92, // Skip to: 40641 +/* 17075 */ MCD_OPC_CheckPredicate, 0, 10, 92, // Skip to: 40641 +/* 17079 */ MCD_OPC_CheckField, 21, 1, 1, 4, 92, // Skip to: 40641 +/* 17085 */ MCD_OPC_Decode, 46, 112, // Opcode: ADDPv8i16 +/* 17088 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 17167 +/* 17092 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17095 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17113 +/* 17099 */ MCD_OPC_CheckPredicate, 0, 242, 91, // Skip to: 40641 +/* 17103 */ MCD_OPC_CheckField, 21, 1, 1, 236, 91, // Skip to: 40641 +/* 17109 */ MCD_OPC_Decode, 143, 11, 85, // Opcode: SMULLv4i16_v4i32 +/* 17113 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17131 +/* 17117 */ MCD_OPC_CheckPredicate, 0, 224, 91, // Skip to: 40641 +/* 17121 */ MCD_OPC_CheckField, 21, 1, 1, 218, 91, // Skip to: 40641 +/* 17127 */ MCD_OPC_Decode, 133, 17, 85, // Opcode: UMULLv4i16_v4i32 +/* 17131 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17149 +/* 17135 */ MCD_OPC_CheckPredicate, 0, 206, 91, // Skip to: 40641 +/* 17139 */ MCD_OPC_CheckField, 21, 1, 1, 200, 91, // Skip to: 40641 +/* 17145 */ MCD_OPC_Decode, 147, 11, 112, // Opcode: SMULLv8i16_v4i32 +/* 17149 */ MCD_OPC_FilterValue, 3, 192, 91, // Skip to: 40641 +/* 17153 */ MCD_OPC_CheckPredicate, 0, 188, 91, // Skip to: 40641 +/* 17157 */ MCD_OPC_CheckField, 21, 1, 1, 182, 91, // Skip to: 40641 +/* 17163 */ MCD_OPC_Decode, 137, 17, 112, // Opcode: UMULLv8i16_v4i32 +/* 17167 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 17210 +/* 17171 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17174 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17192 +/* 17178 */ MCD_OPC_CheckPredicate, 0, 163, 91, // Skip to: 40641 +/* 17182 */ MCD_OPC_CheckField, 21, 1, 1, 157, 91, // Skip to: 40641 +/* 17188 */ MCD_OPC_Decode, 172, 4, 112, // Opcode: FMAXNMv2f64 +/* 17192 */ MCD_OPC_FilterValue, 3, 149, 91, // Skip to: 40641 +/* 17196 */ MCD_OPC_CheckPredicate, 0, 145, 91, // Skip to: 40641 +/* 17200 */ MCD_OPC_CheckField, 21, 1, 1, 139, 91, // Skip to: 40641 +/* 17206 */ MCD_OPC_Decode, 165, 4, 112, // Opcode: FMAXNMPv2f64 +/* 17210 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 17253 +/* 17214 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17217 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17235 +/* 17221 */ MCD_OPC_CheckPredicate, 0, 120, 91, // Skip to: 40641 +/* 17225 */ MCD_OPC_CheckField, 16, 6, 33, 114, 91, // Skip to: 40641 +/* 17231 */ MCD_OPC_Decode, 143, 3, 117, // Opcode: FCVTASv2f64 +/* 17235 */ MCD_OPC_FilterValue, 3, 106, 91, // Skip to: 40641 +/* 17239 */ MCD_OPC_CheckPredicate, 0, 102, 91, // Skip to: 40641 +/* 17243 */ MCD_OPC_CheckField, 16, 6, 33, 96, 91, // Skip to: 40641 +/* 17249 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: FCVTAUv2f64 +/* 17253 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 17277 +/* 17257 */ MCD_OPC_CheckPredicate, 0, 84, 91, // Skip to: 40641 +/* 17261 */ MCD_OPC_CheckField, 29, 3, 2, 78, 91, // Skip to: 40641 +/* 17267 */ MCD_OPC_CheckField, 21, 1, 1, 72, 91, // Skip to: 40641 +/* 17273 */ MCD_OPC_Decode, 209, 4, 120, // Opcode: FMLAv2f64 +/* 17277 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 17320 +/* 17281 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17302 +/* 17288 */ MCD_OPC_CheckPredicate, 0, 53, 91, // Skip to: 40641 +/* 17292 */ MCD_OPC_CheckField, 21, 1, 1, 47, 91, // Skip to: 40641 +/* 17298 */ MCD_OPC_Decode, 214, 11, 85, // Opcode: SQDMULLv4i16_v4i32 +/* 17302 */ MCD_OPC_FilterValue, 2, 39, 91, // Skip to: 40641 +/* 17306 */ MCD_OPC_CheckPredicate, 0, 35, 91, // Skip to: 40641 +/* 17310 */ MCD_OPC_CheckField, 21, 1, 1, 29, 91, // Skip to: 40641 +/* 17316 */ MCD_OPC_Decode, 218, 11, 112, // Opcode: SQDMULLv8i16_v4i32 +/* 17320 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 17363 +/* 17324 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17327 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17345 +/* 17331 */ MCD_OPC_CheckPredicate, 0, 10, 91, // Skip to: 40641 +/* 17335 */ MCD_OPC_CheckField, 21, 1, 1, 4, 91, // Skip to: 40641 +/* 17341 */ MCD_OPC_Decode, 208, 2, 112, // Opcode: FADDv2f64 +/* 17345 */ MCD_OPC_FilterValue, 3, 252, 90, // Skip to: 40641 +/* 17349 */ MCD_OPC_CheckPredicate, 0, 248, 90, // Skip to: 40641 +/* 17353 */ MCD_OPC_CheckField, 21, 1, 1, 242, 90, // Skip to: 40641 +/* 17359 */ MCD_OPC_Decode, 202, 2, 112, // Opcode: FADDPv2f64 +/* 17363 */ MCD_OPC_FilterValue, 54, 39, 0, // Skip to: 17406 +/* 17367 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17370 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17388 +/* 17374 */ MCD_OPC_CheckPredicate, 0, 223, 90, // Skip to: 40641 +/* 17378 */ MCD_OPC_CheckField, 16, 6, 33, 217, 90, // Skip to: 40641 +/* 17384 */ MCD_OPC_Decode, 145, 10, 117, // Opcode: SCVTFv2f64 +/* 17388 */ MCD_OPC_FilterValue, 3, 209, 90, // Skip to: 40641 +/* 17392 */ MCD_OPC_CheckPredicate, 0, 205, 90, // Skip to: 40641 +/* 17396 */ MCD_OPC_CheckField, 16, 6, 33, 199, 90, // Skip to: 40641 +/* 17402 */ MCD_OPC_Decode, 175, 16, 117, // Opcode: UCVTFv2f64 +/* 17406 */ MCD_OPC_FilterValue, 55, 39, 0, // Skip to: 17449 +/* 17410 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17413 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17431 +/* 17417 */ MCD_OPC_CheckPredicate, 0, 180, 90, // Skip to: 40641 +/* 17421 */ MCD_OPC_CheckField, 21, 1, 1, 174, 90, // Skip to: 40641 +/* 17427 */ MCD_OPC_Decode, 244, 4, 112, // Opcode: FMULXv2f64 +/* 17431 */ MCD_OPC_FilterValue, 3, 166, 90, // Skip to: 40641 +/* 17435 */ MCD_OPC_CheckPredicate, 0, 162, 90, // Skip to: 40641 +/* 17439 */ MCD_OPC_CheckField, 21, 1, 1, 156, 90, // Skip to: 40641 +/* 17445 */ MCD_OPC_Decode, 252, 4, 112, // Opcode: FMULv2f64 +/* 17449 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 17492 +/* 17453 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17456 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17474 +/* 17460 */ MCD_OPC_CheckPredicate, 0, 137, 90, // Skip to: 40641 +/* 17464 */ MCD_OPC_CheckField, 21, 1, 1, 131, 90, // Skip to: 40641 +/* 17470 */ MCD_OPC_Decode, 219, 2, 112, // Opcode: FCMEQv2f64 +/* 17474 */ MCD_OPC_FilterValue, 3, 123, 90, // Skip to: 40641 +/* 17478 */ MCD_OPC_CheckPredicate, 0, 119, 90, // Skip to: 40641 +/* 17482 */ MCD_OPC_CheckField, 21, 1, 1, 113, 90, // Skip to: 40641 +/* 17488 */ MCD_OPC_Decode, 229, 2, 112, // Opcode: FCMGEv2f64 +/* 17492 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 17516 +/* 17496 */ MCD_OPC_CheckPredicate, 0, 101, 90, // Skip to: 40641 +/* 17500 */ MCD_OPC_CheckField, 29, 3, 3, 95, 90, // Skip to: 40641 +/* 17506 */ MCD_OPC_CheckField, 21, 1, 1, 89, 90, // Skip to: 40641 +/* 17512 */ MCD_OPC_Decode, 193, 2, 112, // Opcode: FACGEv2f64 +/* 17516 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 17559 +/* 17520 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17523 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17541 +/* 17527 */ MCD_OPC_CheckPredicate, 0, 70, 90, // Skip to: 40641 +/* 17531 */ MCD_OPC_CheckField, 21, 1, 1, 64, 90, // Skip to: 40641 +/* 17537 */ MCD_OPC_Decode, 182, 4, 112, // Opcode: FMAXv2f64 +/* 17541 */ MCD_OPC_FilterValue, 3, 56, 90, // Skip to: 40641 +/* 17545 */ MCD_OPC_CheckPredicate, 0, 52, 90, // Skip to: 40641 +/* 17549 */ MCD_OPC_CheckField, 21, 1, 1, 46, 90, // Skip to: 40641 +/* 17555 */ MCD_OPC_Decode, 175, 4, 112, // Opcode: FMAXPv2f64 +/* 17559 */ MCD_OPC_FilterValue, 63, 38, 90, // Skip to: 40641 +/* 17563 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17566 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17584 +/* 17570 */ MCD_OPC_CheckPredicate, 0, 27, 90, // Skip to: 40641 +/* 17574 */ MCD_OPC_CheckField, 21, 1, 1, 21, 90, // Skip to: 40641 +/* 17580 */ MCD_OPC_Decode, 148, 5, 112, // Opcode: FRECPSv2f64 +/* 17584 */ MCD_OPC_FilterValue, 3, 13, 90, // Skip to: 40641 +/* 17588 */ MCD_OPC_CheckPredicate, 0, 9, 90, // Skip to: 40641 +/* 17592 */ MCD_OPC_CheckField, 21, 1, 1, 3, 90, // Skip to: 40641 +/* 17598 */ MCD_OPC_Decode, 158, 4, 112, // Opcode: FDIVv2f64 +/* 17602 */ MCD_OPC_FilterValue, 10, 165, 19, // Skip to: 22635 +/* 17606 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 17609 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 17688 +/* 17613 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17616 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17634 +/* 17620 */ MCD_OPC_CheckPredicate, 0, 233, 89, // Skip to: 40641 +/* 17624 */ MCD_OPC_CheckField, 21, 1, 1, 227, 89, // Skip to: 40641 +/* 17630 */ MCD_OPC_Decode, 243, 9, 85, // Opcode: SADDLv2i32_v2i64 +/* 17634 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17652 +/* 17638 */ MCD_OPC_CheckPredicate, 0, 215, 89, // Skip to: 40641 +/* 17642 */ MCD_OPC_CheckField, 21, 1, 1, 209, 89, // Skip to: 40641 +/* 17648 */ MCD_OPC_Decode, 149, 16, 85, // Opcode: UADDLv2i32_v2i64 +/* 17652 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17670 +/* 17656 */ MCD_OPC_CheckPredicate, 0, 197, 89, // Skip to: 40641 +/* 17660 */ MCD_OPC_CheckField, 21, 1, 1, 191, 89, // Skip to: 40641 +/* 17666 */ MCD_OPC_Decode, 245, 9, 112, // Opcode: SADDLv4i32_v2i64 +/* 17670 */ MCD_OPC_FilterValue, 3, 183, 89, // Skip to: 40641 +/* 17674 */ MCD_OPC_CheckPredicate, 0, 179, 89, // Skip to: 40641 +/* 17678 */ MCD_OPC_CheckField, 21, 1, 1, 173, 89, // Skip to: 40641 +/* 17684 */ MCD_OPC_Decode, 151, 16, 112, // Opcode: UADDLv4i32_v2i64 +/* 17688 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 17767 +/* 17692 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17695 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17713 +/* 17699 */ MCD_OPC_CheckPredicate, 0, 154, 89, // Skip to: 40641 +/* 17703 */ MCD_OPC_CheckField, 21, 1, 1, 148, 89, // Skip to: 40641 +/* 17709 */ MCD_OPC_Decode, 165, 10, 89, // Opcode: SHADDv2i32 +/* 17713 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17731 +/* 17717 */ MCD_OPC_CheckPredicate, 0, 136, 89, // Skip to: 40641 +/* 17721 */ MCD_OPC_CheckField, 21, 1, 1, 130, 89, // Skip to: 40641 +/* 17727 */ MCD_OPC_Decode, 185, 16, 89, // Opcode: UHADDv2i32 +/* 17731 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17749 +/* 17735 */ MCD_OPC_CheckPredicate, 0, 118, 89, // Skip to: 40641 +/* 17739 */ MCD_OPC_CheckField, 21, 1, 1, 112, 89, // Skip to: 40641 +/* 17745 */ MCD_OPC_Decode, 167, 10, 112, // Opcode: SHADDv4i32 +/* 17749 */ MCD_OPC_FilterValue, 3, 104, 89, // Skip to: 40641 +/* 17753 */ MCD_OPC_CheckPredicate, 0, 100, 89, // Skip to: 40641 +/* 17757 */ MCD_OPC_CheckField, 21, 1, 1, 94, 89, // Skip to: 40641 +/* 17763 */ MCD_OPC_Decode, 187, 16, 112, // Opcode: UHADDv4i32 +/* 17767 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 17810 +/* 17771 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17774 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17792 +/* 17778 */ MCD_OPC_CheckPredicate, 0, 75, 89, // Skip to: 40641 +/* 17782 */ MCD_OPC_CheckField, 16, 6, 32, 69, 89, // Skip to: 40641 +/* 17788 */ MCD_OPC_Decode, 180, 9, 90, // Opcode: REV64v2i32 +/* 17792 */ MCD_OPC_FilterValue, 2, 61, 89, // Skip to: 40641 +/* 17796 */ MCD_OPC_CheckPredicate, 0, 57, 89, // Skip to: 40641 +/* 17800 */ MCD_OPC_CheckField, 16, 6, 32, 51, 89, // Skip to: 40641 +/* 17806 */ MCD_OPC_Decode, 182, 9, 117, // Opcode: REV64v4i32 +/* 17810 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 17889 +/* 17814 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17817 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17835 +/* 17821 */ MCD_OPC_CheckPredicate, 0, 32, 89, // Skip to: 40641 +/* 17825 */ MCD_OPC_CheckField, 21, 1, 1, 26, 89, // Skip to: 40641 +/* 17831 */ MCD_OPC_Decode, 165, 11, 89, // Opcode: SQADDv2i32 +/* 17835 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17853 +/* 17839 */ MCD_OPC_CheckPredicate, 0, 14, 89, // Skip to: 40641 +/* 17843 */ MCD_OPC_CheckField, 21, 1, 1, 8, 89, // Skip to: 40641 +/* 17849 */ MCD_OPC_Decode, 144, 17, 89, // Opcode: UQADDv2i32 +/* 17853 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17871 +/* 17857 */ MCD_OPC_CheckPredicate, 0, 252, 88, // Skip to: 40641 +/* 17861 */ MCD_OPC_CheckField, 21, 1, 1, 246, 88, // Skip to: 40641 +/* 17867 */ MCD_OPC_Decode, 168, 11, 112, // Opcode: SQADDv4i32 +/* 17871 */ MCD_OPC_FilterValue, 3, 238, 88, // Skip to: 40641 +/* 17875 */ MCD_OPC_CheckPredicate, 0, 234, 88, // Skip to: 40641 +/* 17879 */ MCD_OPC_CheckField, 21, 1, 1, 228, 88, // Skip to: 40641 +/* 17885 */ MCD_OPC_Decode, 147, 17, 112, // Opcode: UQADDv4i32 +/* 17889 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 17968 +/* 17893 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17896 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17914 +/* 17900 */ MCD_OPC_CheckPredicate, 0, 209, 88, // Skip to: 40641 +/* 17904 */ MCD_OPC_CheckField, 21, 1, 1, 203, 88, // Skip to: 40641 +/* 17910 */ MCD_OPC_Decode, 249, 9, 93, // Opcode: SADDWv2i32_v2i64 +/* 17914 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17932 +/* 17918 */ MCD_OPC_CheckPredicate, 0, 191, 88, // Skip to: 40641 +/* 17922 */ MCD_OPC_CheckField, 21, 1, 1, 185, 88, // Skip to: 40641 +/* 17928 */ MCD_OPC_Decode, 155, 16, 93, // Opcode: UADDWv2i32_v2i64 +/* 17932 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17950 +/* 17936 */ MCD_OPC_CheckPredicate, 0, 173, 88, // Skip to: 40641 +/* 17940 */ MCD_OPC_CheckField, 21, 1, 1, 167, 88, // Skip to: 40641 +/* 17946 */ MCD_OPC_Decode, 251, 9, 112, // Opcode: SADDWv4i32_v2i64 +/* 17950 */ MCD_OPC_FilterValue, 3, 159, 88, // Skip to: 40641 +/* 17954 */ MCD_OPC_CheckPredicate, 0, 155, 88, // Skip to: 40641 +/* 17958 */ MCD_OPC_CheckField, 21, 1, 1, 149, 88, // Skip to: 40641 +/* 17964 */ MCD_OPC_Decode, 157, 16, 112, // Opcode: UADDWv4i32_v2i64 +/* 17968 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 18047 +/* 17972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 17975 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17993 +/* 17979 */ MCD_OPC_CheckPredicate, 0, 130, 88, // Skip to: 40641 +/* 17983 */ MCD_OPC_CheckField, 21, 1, 1, 124, 88, // Skip to: 40641 +/* 17989 */ MCD_OPC_Decode, 224, 12, 89, // Opcode: SRHADDv2i32 +/* 17993 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18011 +/* 17997 */ MCD_OPC_CheckPredicate, 0, 112, 88, // Skip to: 40641 +/* 18001 */ MCD_OPC_CheckField, 21, 1, 1, 106, 88, // Skip to: 40641 +/* 18007 */ MCD_OPC_Decode, 224, 17, 89, // Opcode: URHADDv2i32 +/* 18011 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18029 +/* 18015 */ MCD_OPC_CheckPredicate, 0, 94, 88, // Skip to: 40641 +/* 18019 */ MCD_OPC_CheckField, 21, 1, 1, 88, 88, // Skip to: 40641 +/* 18025 */ MCD_OPC_Decode, 226, 12, 112, // Opcode: SRHADDv4i32 +/* 18029 */ MCD_OPC_FilterValue, 3, 80, 88, // Skip to: 40641 +/* 18033 */ MCD_OPC_CheckPredicate, 0, 76, 88, // Skip to: 40641 +/* 18037 */ MCD_OPC_CheckField, 21, 1, 1, 70, 88, // Skip to: 40641 +/* 18043 */ MCD_OPC_Decode, 226, 17, 112, // Opcode: URHADDv4i32 +/* 18047 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 18090 +/* 18051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18054 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18072 +/* 18058 */ MCD_OPC_CheckPredicate, 0, 51, 88, // Skip to: 40641 +/* 18062 */ MCD_OPC_CheckField, 21, 1, 0, 45, 88, // Skip to: 40641 +/* 18068 */ MCD_OPC_Decode, 181, 18, 89, // Opcode: UZP1v2i32 +/* 18072 */ MCD_OPC_FilterValue, 2, 37, 88, // Skip to: 40641 +/* 18076 */ MCD_OPC_CheckPredicate, 0, 33, 88, // Skip to: 40641 +/* 18080 */ MCD_OPC_CheckField, 21, 1, 0, 27, 88, // Skip to: 40641 +/* 18086 */ MCD_OPC_Decode, 184, 18, 112, // Opcode: UZP1v4i32 +/* 18090 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 18167 +/* 18094 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18097 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18115 +/* 18101 */ MCD_OPC_CheckPredicate, 0, 8, 88, // Skip to: 40641 +/* 18105 */ MCD_OPC_CheckField, 21, 1, 1, 2, 88, // Skip to: 40641 +/* 18111 */ MCD_OPC_Decode, 146, 9, 89, // Opcode: ORRv8i8 +/* 18115 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 18132 +/* 18119 */ MCD_OPC_CheckPredicate, 0, 246, 87, // Skip to: 40641 +/* 18123 */ MCD_OPC_CheckField, 21, 1, 1, 240, 87, // Skip to: 40641 +/* 18129 */ MCD_OPC_Decode, 123, 109, // Opcode: BITv8i8 +/* 18132 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18150 +/* 18136 */ MCD_OPC_CheckPredicate, 0, 229, 87, // Skip to: 40641 +/* 18140 */ MCD_OPC_CheckField, 21, 1, 1, 223, 87, // Skip to: 40641 +/* 18146 */ MCD_OPC_Decode, 141, 9, 112, // Opcode: ORRv16i8 +/* 18150 */ MCD_OPC_FilterValue, 3, 215, 87, // Skip to: 40641 +/* 18154 */ MCD_OPC_CheckPredicate, 0, 211, 87, // Skip to: 40641 +/* 18158 */ MCD_OPC_CheckField, 21, 1, 1, 205, 87, // Skip to: 40641 +/* 18164 */ MCD_OPC_Decode, 122, 120, // Opcode: BITv16i8 +/* 18167 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 18246 +/* 18171 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18174 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18192 +/* 18178 */ MCD_OPC_CheckPredicate, 0, 187, 87, // Skip to: 40641 +/* 18182 */ MCD_OPC_CheckField, 21, 1, 1, 181, 87, // Skip to: 40641 +/* 18188 */ MCD_OPC_Decode, 164, 13, 85, // Opcode: SSUBLv2i32_v2i64 +/* 18192 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18210 +/* 18196 */ MCD_OPC_CheckPredicate, 0, 169, 87, // Skip to: 40641 +/* 18200 */ MCD_OPC_CheckField, 21, 1, 1, 163, 87, // Skip to: 40641 +/* 18206 */ MCD_OPC_Decode, 169, 18, 85, // Opcode: USUBLv2i32_v2i64 +/* 18210 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18228 +/* 18214 */ MCD_OPC_CheckPredicate, 0, 151, 87, // Skip to: 40641 +/* 18218 */ MCD_OPC_CheckField, 21, 1, 1, 145, 87, // Skip to: 40641 +/* 18224 */ MCD_OPC_Decode, 166, 13, 112, // Opcode: SSUBLv4i32_v2i64 +/* 18228 */ MCD_OPC_FilterValue, 3, 137, 87, // Skip to: 40641 +/* 18232 */ MCD_OPC_CheckPredicate, 0, 133, 87, // Skip to: 40641 +/* 18236 */ MCD_OPC_CheckField, 21, 1, 1, 127, 87, // Skip to: 40641 +/* 18242 */ MCD_OPC_Decode, 171, 18, 112, // Opcode: USUBLv4i32_v2i64 +/* 18246 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 18325 +/* 18250 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18253 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18271 +/* 18257 */ MCD_OPC_CheckPredicate, 0, 108, 87, // Skip to: 40641 +/* 18261 */ MCD_OPC_CheckField, 21, 1, 1, 102, 87, // Skip to: 40641 +/* 18267 */ MCD_OPC_Decode, 191, 10, 89, // Opcode: SHSUBv2i32 +/* 18271 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18289 +/* 18275 */ MCD_OPC_CheckPredicate, 0, 90, 87, // Skip to: 40641 +/* 18279 */ MCD_OPC_CheckField, 21, 1, 1, 84, 87, // Skip to: 40641 +/* 18285 */ MCD_OPC_Decode, 191, 16, 89, // Opcode: UHSUBv2i32 +/* 18289 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18307 +/* 18293 */ MCD_OPC_CheckPredicate, 0, 72, 87, // Skip to: 40641 +/* 18297 */ MCD_OPC_CheckField, 21, 1, 1, 66, 87, // Skip to: 40641 +/* 18303 */ MCD_OPC_Decode, 193, 10, 112, // Opcode: SHSUBv4i32 +/* 18307 */ MCD_OPC_FilterValue, 3, 58, 87, // Skip to: 40641 +/* 18311 */ MCD_OPC_CheckPredicate, 0, 54, 87, // Skip to: 40641 +/* 18315 */ MCD_OPC_CheckField, 21, 1, 1, 48, 87, // Skip to: 40641 +/* 18321 */ MCD_OPC_Decode, 193, 16, 112, // Opcode: UHSUBv4i32 +/* 18325 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 18494 +/* 18329 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18332 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 18382 +/* 18336 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 18339 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18351 +/* 18343 */ MCD_OPC_CheckPredicate, 0, 22, 87, // Skip to: 40641 +/* 18347 */ MCD_OPC_Decode, 222, 15, 89, // Opcode: TRN1v2i32 +/* 18351 */ MCD_OPC_FilterValue, 1, 14, 87, // Skip to: 40641 +/* 18355 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 18358 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18370 +/* 18362 */ MCD_OPC_CheckPredicate, 0, 3, 87, // Skip to: 40641 +/* 18366 */ MCD_OPC_Decode, 232, 9, 90, // Opcode: SADDLPv2i32_v1i64 +/* 18370 */ MCD_OPC_FilterValue, 1, 251, 86, // Skip to: 40641 +/* 18374 */ MCD_OPC_CheckPredicate, 0, 247, 86, // Skip to: 40641 +/* 18378 */ MCD_OPC_Decode, 195, 18, 95, // Opcode: XTNv2i32 +/* 18382 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18413 +/* 18386 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 18389 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18401 +/* 18393 */ MCD_OPC_CheckPredicate, 0, 228, 86, // Skip to: 40641 +/* 18397 */ MCD_OPC_Decode, 138, 16, 90, // Opcode: UADDLPv2i32_v1i64 +/* 18401 */ MCD_OPC_FilterValue, 33, 220, 86, // Skip to: 40641 +/* 18405 */ MCD_OPC_CheckPredicate, 0, 216, 86, // Skip to: 40641 +/* 18409 */ MCD_OPC_Decode, 218, 12, 95, // Opcode: SQXTUNv2i32 +/* 18413 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18463 +/* 18417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 18420 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18432 +/* 18424 */ MCD_OPC_CheckPredicate, 0, 197, 86, // Skip to: 40641 +/* 18428 */ MCD_OPC_Decode, 225, 15, 112, // Opcode: TRN1v4i32 +/* 18432 */ MCD_OPC_FilterValue, 1, 189, 86, // Skip to: 40641 +/* 18436 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 18439 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18451 +/* 18443 */ MCD_OPC_CheckPredicate, 0, 178, 86, // Skip to: 40641 +/* 18447 */ MCD_OPC_Decode, 234, 9, 117, // Opcode: SADDLPv4i32_v2i64 +/* 18451 */ MCD_OPC_FilterValue, 1, 170, 86, // Skip to: 40641 +/* 18455 */ MCD_OPC_CheckPredicate, 0, 166, 86, // Skip to: 40641 +/* 18459 */ MCD_OPC_Decode, 197, 18, 126, // Opcode: XTNv4i32 +/* 18463 */ MCD_OPC_FilterValue, 3, 158, 86, // Skip to: 40641 +/* 18467 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 18470 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18482 +/* 18474 */ MCD_OPC_CheckPredicate, 0, 147, 86, // Skip to: 40641 +/* 18478 */ MCD_OPC_Decode, 140, 16, 117, // Opcode: UADDLPv4i32_v2i64 +/* 18482 */ MCD_OPC_FilterValue, 33, 139, 86, // Skip to: 40641 +/* 18486 */ MCD_OPC_CheckPredicate, 0, 135, 86, // Skip to: 40641 +/* 18490 */ MCD_OPC_Decode, 220, 12, 126, // Opcode: SQXTUNv4i32 +/* 18494 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 18573 +/* 18498 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18501 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18519 +/* 18505 */ MCD_OPC_CheckPredicate, 0, 116, 86, // Skip to: 40641 +/* 18509 */ MCD_OPC_CheckField, 21, 1, 1, 110, 86, // Skip to: 40641 +/* 18515 */ MCD_OPC_Decode, 199, 12, 89, // Opcode: SQSUBv2i32 +/* 18519 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18537 +/* 18523 */ MCD_OPC_CheckPredicate, 0, 98, 86, // Skip to: 40641 +/* 18527 */ MCD_OPC_CheckField, 21, 1, 1, 92, 86, // Skip to: 40641 +/* 18533 */ MCD_OPC_Decode, 206, 17, 89, // Opcode: UQSUBv2i32 +/* 18537 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18555 +/* 18541 */ MCD_OPC_CheckPredicate, 0, 80, 86, // Skip to: 40641 +/* 18545 */ MCD_OPC_CheckField, 21, 1, 1, 74, 86, // Skip to: 40641 +/* 18551 */ MCD_OPC_Decode, 202, 12, 112, // Opcode: SQSUBv4i32 +/* 18555 */ MCD_OPC_FilterValue, 3, 66, 86, // Skip to: 40641 +/* 18559 */ MCD_OPC_CheckPredicate, 0, 62, 86, // Skip to: 40641 +/* 18563 */ MCD_OPC_CheckField, 21, 1, 1, 56, 86, // Skip to: 40641 +/* 18569 */ MCD_OPC_Decode, 209, 17, 112, // Opcode: UQSUBv4i32 +/* 18573 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 18652 +/* 18577 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18580 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18598 +/* 18584 */ MCD_OPC_CheckPredicate, 0, 37, 86, // Skip to: 40641 +/* 18588 */ MCD_OPC_CheckField, 21, 1, 1, 31, 86, // Skip to: 40641 +/* 18594 */ MCD_OPC_Decode, 170, 13, 93, // Opcode: SSUBWv2i32_v2i64 +/* 18598 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18616 +/* 18602 */ MCD_OPC_CheckPredicate, 0, 19, 86, // Skip to: 40641 +/* 18606 */ MCD_OPC_CheckField, 21, 1, 1, 13, 86, // Skip to: 40641 +/* 18612 */ MCD_OPC_Decode, 175, 18, 93, // Opcode: USUBWv2i32_v2i64 +/* 18616 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18634 +/* 18620 */ MCD_OPC_CheckPredicate, 0, 1, 86, // Skip to: 40641 +/* 18624 */ MCD_OPC_CheckField, 21, 1, 1, 251, 85, // Skip to: 40641 +/* 18630 */ MCD_OPC_Decode, 172, 13, 112, // Opcode: SSUBWv4i32_v2i64 +/* 18634 */ MCD_OPC_FilterValue, 3, 243, 85, // Skip to: 40641 +/* 18638 */ MCD_OPC_CheckPredicate, 0, 239, 85, // Skip to: 40641 +/* 18642 */ MCD_OPC_CheckField, 21, 1, 1, 233, 85, // Skip to: 40641 +/* 18648 */ MCD_OPC_Decode, 177, 18, 112, // Opcode: USUBWv4i32_v2i64 +/* 18652 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 18731 +/* 18656 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18659 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18677 +/* 18663 */ MCD_OPC_CheckPredicate, 0, 214, 85, // Skip to: 40641 +/* 18667 */ MCD_OPC_CheckField, 21, 1, 1, 208, 85, // Skip to: 40641 +/* 18673 */ MCD_OPC_Decode, 196, 1, 89, // Opcode: CMGTv2i32 +/* 18677 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18695 +/* 18681 */ MCD_OPC_CheckPredicate, 0, 196, 85, // Skip to: 40641 +/* 18685 */ MCD_OPC_CheckField, 21, 1, 1, 190, 85, // Skip to: 40641 +/* 18691 */ MCD_OPC_Decode, 210, 1, 89, // Opcode: CMHIv2i32 +/* 18695 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18713 +/* 18699 */ MCD_OPC_CheckPredicate, 0, 178, 85, // Skip to: 40641 +/* 18703 */ MCD_OPC_CheckField, 21, 1, 1, 172, 85, // Skip to: 40641 +/* 18709 */ MCD_OPC_Decode, 202, 1, 112, // Opcode: CMGTv4i32 +/* 18713 */ MCD_OPC_FilterValue, 3, 164, 85, // Skip to: 40641 +/* 18717 */ MCD_OPC_CheckPredicate, 0, 160, 85, // Skip to: 40641 +/* 18721 */ MCD_OPC_CheckField, 21, 1, 1, 154, 85, // Skip to: 40641 +/* 18727 */ MCD_OPC_Decode, 213, 1, 112, // Opcode: CMHIv4i32 +/* 18731 */ MCD_OPC_FilterValue, 14, 164, 0, // Skip to: 18899 +/* 18735 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18738 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 18775 +/* 18742 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 18745 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18757 +/* 18749 */ MCD_OPC_CheckPredicate, 0, 128, 85, // Skip to: 40641 +/* 18753 */ MCD_OPC_Decode, 201, 18, 89, // Opcode: ZIP1v2i32 +/* 18757 */ MCD_OPC_FilterValue, 1, 120, 85, // Skip to: 40641 +/* 18761 */ MCD_OPC_CheckPredicate, 0, 116, 85, // Skip to: 40641 +/* 18765 */ MCD_OPC_CheckField, 16, 5, 0, 110, 85, // Skip to: 40641 +/* 18771 */ MCD_OPC_Decode, 188, 15, 99, // Opcode: SUQADDv2i32 +/* 18775 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18806 +/* 18779 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 18782 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18794 +/* 18786 */ MCD_OPC_CheckPredicate, 0, 91, 85, // Skip to: 40641 +/* 18790 */ MCD_OPC_Decode, 154, 18, 99, // Opcode: USQADDv2i32 +/* 18794 */ MCD_OPC_FilterValue, 33, 83, 85, // Skip to: 40641 +/* 18798 */ MCD_OPC_CheckPredicate, 0, 79, 85, // Skip to: 40641 +/* 18802 */ MCD_OPC_Decode, 171, 10, 108, // Opcode: SHLLv2i32 +/* 18806 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18856 +/* 18810 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 18813 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18825 +/* 18817 */ MCD_OPC_CheckPredicate, 0, 60, 85, // Skip to: 40641 +/* 18821 */ MCD_OPC_Decode, 204, 18, 112, // Opcode: ZIP1v4i32 +/* 18825 */ MCD_OPC_FilterValue, 1, 52, 85, // Skip to: 40641 +/* 18829 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 18832 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18844 +/* 18836 */ MCD_OPC_CheckPredicate, 0, 41, 85, // Skip to: 40641 +/* 18840 */ MCD_OPC_Decode, 191, 15, 126, // Opcode: SUQADDv4i32 +/* 18844 */ MCD_OPC_FilterValue, 16, 33, 85, // Skip to: 40641 +/* 18848 */ MCD_OPC_CheckPredicate, 0, 29, 85, // Skip to: 40641 +/* 18852 */ MCD_OPC_Decode, 239, 9, 95, // Opcode: SADDLVv4i32v +/* 18856 */ MCD_OPC_FilterValue, 3, 21, 85, // Skip to: 40641 +/* 18860 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 18863 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18875 +/* 18867 */ MCD_OPC_CheckPredicate, 0, 10, 85, // Skip to: 40641 +/* 18871 */ MCD_OPC_Decode, 157, 18, 126, // Opcode: USQADDv4i32 +/* 18875 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 18887 +/* 18879 */ MCD_OPC_CheckPredicate, 0, 254, 84, // Skip to: 40641 +/* 18883 */ MCD_OPC_Decode, 173, 10, 117, // Opcode: SHLLv4i32 +/* 18887 */ MCD_OPC_FilterValue, 48, 246, 84, // Skip to: 40641 +/* 18891 */ MCD_OPC_CheckPredicate, 0, 242, 84, // Skip to: 40641 +/* 18895 */ MCD_OPC_Decode, 145, 16, 95, // Opcode: UADDLVv4i32v +/* 18899 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 18978 +/* 18903 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18906 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18924 +/* 18910 */ MCD_OPC_CheckPredicate, 0, 223, 84, // Skip to: 40641 +/* 18914 */ MCD_OPC_CheckField, 21, 1, 1, 217, 84, // Skip to: 40641 +/* 18920 */ MCD_OPC_Decode, 180, 1, 89, // Opcode: CMGEv2i32 +/* 18924 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18942 +/* 18928 */ MCD_OPC_CheckPredicate, 0, 205, 84, // Skip to: 40641 +/* 18932 */ MCD_OPC_CheckField, 21, 1, 1, 199, 84, // Skip to: 40641 +/* 18938 */ MCD_OPC_Decode, 218, 1, 89, // Opcode: CMHSv2i32 +/* 18942 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18960 +/* 18946 */ MCD_OPC_CheckPredicate, 0, 187, 84, // Skip to: 40641 +/* 18950 */ MCD_OPC_CheckField, 21, 1, 1, 181, 84, // Skip to: 40641 +/* 18956 */ MCD_OPC_Decode, 186, 1, 112, // Opcode: CMGEv4i32 +/* 18960 */ MCD_OPC_FilterValue, 3, 173, 84, // Skip to: 40641 +/* 18964 */ MCD_OPC_CheckPredicate, 0, 169, 84, // Skip to: 40641 +/* 18968 */ MCD_OPC_CheckField, 21, 1, 1, 163, 84, // Skip to: 40641 +/* 18974 */ MCD_OPC_Decode, 221, 1, 112, // Opcode: CMHSv4i32 +/* 18978 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 19055 +/* 18982 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 18985 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 19002 +/* 18989 */ MCD_OPC_CheckPredicate, 0, 144, 84, // Skip to: 40641 +/* 18993 */ MCD_OPC_CheckField, 21, 1, 1, 138, 84, // Skip to: 40641 +/* 18999 */ MCD_OPC_Decode, 34, 103, // Opcode: ADDHNv2i64_v2i32 +/* 19002 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19020 +/* 19006 */ MCD_OPC_CheckPredicate, 0, 127, 84, // Skip to: 40641 +/* 19010 */ MCD_OPC_CheckField, 21, 1, 1, 121, 84, // Skip to: 40641 +/* 19016 */ MCD_OPC_Decode, 158, 9, 103, // Opcode: RADDHNv2i64_v2i32 +/* 19020 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 19037 +/* 19024 */ MCD_OPC_CheckPredicate, 0, 109, 84, // Skip to: 40641 +/* 19028 */ MCD_OPC_CheckField, 21, 1, 1, 103, 84, // Skip to: 40641 +/* 19034 */ MCD_OPC_Decode, 35, 120, // Opcode: ADDHNv2i64_v4i32 +/* 19037 */ MCD_OPC_FilterValue, 3, 96, 84, // Skip to: 40641 +/* 19041 */ MCD_OPC_CheckPredicate, 0, 92, 84, // Skip to: 40641 +/* 19045 */ MCD_OPC_CheckField, 21, 1, 1, 86, 84, // Skip to: 40641 +/* 19051 */ MCD_OPC_Decode, 159, 9, 120, // Opcode: RADDHNv2i64_v4i32 +/* 19055 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 19134 +/* 19059 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19062 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19080 +/* 19066 */ MCD_OPC_CheckPredicate, 0, 67, 84, // Skip to: 40641 +/* 19070 */ MCD_OPC_CheckField, 21, 1, 1, 61, 84, // Skip to: 40641 +/* 19076 */ MCD_OPC_Decode, 141, 13, 89, // Opcode: SSHLv2i32 +/* 19080 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19098 +/* 19084 */ MCD_OPC_CheckPredicate, 0, 49, 84, // Skip to: 40641 +/* 19088 */ MCD_OPC_CheckField, 21, 1, 1, 43, 84, // Skip to: 40641 +/* 19094 */ MCD_OPC_Decode, 135, 18, 89, // Opcode: USHLv2i32 +/* 19098 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19116 +/* 19102 */ MCD_OPC_CheckPredicate, 0, 31, 84, // Skip to: 40641 +/* 19106 */ MCD_OPC_CheckField, 21, 1, 1, 25, 84, // Skip to: 40641 +/* 19112 */ MCD_OPC_Decode, 144, 13, 112, // Opcode: SSHLv4i32 +/* 19116 */ MCD_OPC_FilterValue, 3, 17, 84, // Skip to: 40641 +/* 19120 */ MCD_OPC_CheckPredicate, 0, 13, 84, // Skip to: 40641 +/* 19124 */ MCD_OPC_CheckField, 21, 1, 1, 7, 84, // Skip to: 40641 +/* 19130 */ MCD_OPC_Decode, 138, 18, 112, // Opcode: USHLv4i32 +/* 19134 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 19265 +/* 19138 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19141 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 19172 +/* 19145 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 19148 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19160 +/* 19152 */ MCD_OPC_CheckPredicate, 0, 237, 83, // Skip to: 40641 +/* 19156 */ MCD_OPC_Decode, 147, 1, 90, // Opcode: CLSv2i32 +/* 19160 */ MCD_OPC_FilterValue, 33, 229, 83, // Skip to: 40641 +/* 19164 */ MCD_OPC_CheckPredicate, 0, 225, 83, // Skip to: 40641 +/* 19168 */ MCD_OPC_Decode, 209, 12, 95, // Opcode: SQXTNv2i32 +/* 19172 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 19203 +/* 19176 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 19179 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19191 +/* 19183 */ MCD_OPC_CheckPredicate, 0, 206, 83, // Skip to: 40641 +/* 19187 */ MCD_OPC_Decode, 155, 1, 90, // Opcode: CLZv2i32 +/* 19191 */ MCD_OPC_FilterValue, 33, 198, 83, // Skip to: 40641 +/* 19195 */ MCD_OPC_CheckPredicate, 0, 194, 83, // Skip to: 40641 +/* 19199 */ MCD_OPC_Decode, 216, 17, 95, // Opcode: UQXTNv2i32 +/* 19203 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 19234 +/* 19207 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 19210 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19222 +/* 19214 */ MCD_OPC_CheckPredicate, 0, 175, 83, // Skip to: 40641 +/* 19218 */ MCD_OPC_Decode, 149, 1, 117, // Opcode: CLSv4i32 +/* 19222 */ MCD_OPC_FilterValue, 33, 167, 83, // Skip to: 40641 +/* 19226 */ MCD_OPC_CheckPredicate, 0, 163, 83, // Skip to: 40641 +/* 19230 */ MCD_OPC_Decode, 211, 12, 126, // Opcode: SQXTNv4i32 +/* 19234 */ MCD_OPC_FilterValue, 3, 155, 83, // Skip to: 40641 +/* 19238 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 19241 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19253 +/* 19245 */ MCD_OPC_CheckPredicate, 0, 144, 83, // Skip to: 40641 +/* 19249 */ MCD_OPC_Decode, 157, 1, 117, // Opcode: CLZv4i32 +/* 19253 */ MCD_OPC_FilterValue, 33, 136, 83, // Skip to: 40641 +/* 19257 */ MCD_OPC_CheckPredicate, 0, 132, 83, // Skip to: 40641 +/* 19261 */ MCD_OPC_Decode, 218, 17, 126, // Opcode: UQXTNv4i32 +/* 19265 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 19344 +/* 19269 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19272 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19290 +/* 19276 */ MCD_OPC_CheckPredicate, 0, 113, 83, // Skip to: 40641 +/* 19280 */ MCD_OPC_CheckField, 21, 1, 1, 107, 83, // Skip to: 40641 +/* 19286 */ MCD_OPC_Decode, 164, 12, 89, // Opcode: SQSHLv2i32 +/* 19290 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19308 +/* 19294 */ MCD_OPC_CheckPredicate, 0, 95, 83, // Skip to: 40641 +/* 19298 */ MCD_OPC_CheckField, 21, 1, 1, 89, 83, // Skip to: 40641 +/* 19304 */ MCD_OPC_Decode, 180, 17, 89, // Opcode: UQSHLv2i32 +/* 19308 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19326 +/* 19312 */ MCD_OPC_CheckPredicate, 0, 77, 83, // Skip to: 40641 +/* 19316 */ MCD_OPC_CheckField, 21, 1, 1, 71, 83, // Skip to: 40641 +/* 19322 */ MCD_OPC_Decode, 170, 12, 112, // Opcode: SQSHLv4i32 +/* 19326 */ MCD_OPC_FilterValue, 3, 63, 83, // Skip to: 40641 +/* 19330 */ MCD_OPC_CheckPredicate, 0, 59, 83, // Skip to: 40641 +/* 19334 */ MCD_OPC_CheckField, 21, 1, 1, 53, 83, // Skip to: 40641 +/* 19340 */ MCD_OPC_Decode, 186, 17, 112, // Opcode: UQSHLv4i32 +/* 19344 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 19423 +/* 19348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19351 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19369 +/* 19355 */ MCD_OPC_CheckPredicate, 0, 34, 83, // Skip to: 40641 +/* 19359 */ MCD_OPC_CheckField, 21, 1, 1, 28, 83, // Skip to: 40641 +/* 19365 */ MCD_OPC_Decode, 202, 9, 105, // Opcode: SABALv2i32_v2i64 +/* 19369 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19387 +/* 19373 */ MCD_OPC_CheckPredicate, 0, 16, 83, // Skip to: 40641 +/* 19377 */ MCD_OPC_CheckField, 21, 1, 1, 10, 83, // Skip to: 40641 +/* 19383 */ MCD_OPC_Decode, 236, 15, 105, // Opcode: UABALv2i32_v2i64 +/* 19387 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19405 +/* 19391 */ MCD_OPC_CheckPredicate, 0, 254, 82, // Skip to: 40641 +/* 19395 */ MCD_OPC_CheckField, 21, 1, 1, 248, 82, // Skip to: 40641 +/* 19401 */ MCD_OPC_Decode, 204, 9, 120, // Opcode: SABALv4i32_v2i64 +/* 19405 */ MCD_OPC_FilterValue, 3, 240, 82, // Skip to: 40641 +/* 19409 */ MCD_OPC_CheckPredicate, 0, 236, 82, // Skip to: 40641 +/* 19413 */ MCD_OPC_CheckField, 21, 1, 1, 230, 82, // Skip to: 40641 +/* 19419 */ MCD_OPC_Decode, 238, 15, 120, // Opcode: UABALv4i32_v2i64 +/* 19423 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 19502 +/* 19427 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19430 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19448 +/* 19434 */ MCD_OPC_CheckPredicate, 0, 211, 82, // Skip to: 40641 +/* 19438 */ MCD_OPC_CheckField, 21, 1, 1, 205, 82, // Skip to: 40641 +/* 19444 */ MCD_OPC_Decode, 239, 12, 89, // Opcode: SRSHLv2i32 +/* 19448 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19466 +/* 19452 */ MCD_OPC_CheckPredicate, 0, 193, 82, // Skip to: 40641 +/* 19456 */ MCD_OPC_CheckField, 21, 1, 1, 187, 82, // Skip to: 40641 +/* 19462 */ MCD_OPC_Decode, 231, 17, 89, // Opcode: URSHLv2i32 +/* 19466 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19484 +/* 19470 */ MCD_OPC_CheckPredicate, 0, 175, 82, // Skip to: 40641 +/* 19474 */ MCD_OPC_CheckField, 21, 1, 1, 169, 82, // Skip to: 40641 +/* 19480 */ MCD_OPC_Decode, 242, 12, 112, // Opcode: SRSHLv4i32 +/* 19484 */ MCD_OPC_FilterValue, 3, 161, 82, // Skip to: 40641 +/* 19488 */ MCD_OPC_CheckPredicate, 0, 157, 82, // Skip to: 40641 +/* 19492 */ MCD_OPC_CheckField, 21, 1, 1, 151, 82, // Skip to: 40641 +/* 19498 */ MCD_OPC_Decode, 234, 17, 112, // Opcode: URSHLv4i32 +/* 19502 */ MCD_OPC_FilterValue, 22, 39, 0, // Skip to: 19545 +/* 19506 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19509 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19527 +/* 19513 */ MCD_OPC_CheckPredicate, 0, 132, 82, // Skip to: 40641 +/* 19517 */ MCD_OPC_CheckField, 21, 1, 0, 126, 82, // Skip to: 40641 +/* 19523 */ MCD_OPC_Decode, 188, 18, 89, // Opcode: UZP2v2i32 +/* 19527 */ MCD_OPC_FilterValue, 2, 118, 82, // Skip to: 40641 +/* 19531 */ MCD_OPC_CheckPredicate, 0, 114, 82, // Skip to: 40641 +/* 19535 */ MCD_OPC_CheckField, 21, 1, 0, 108, 82, // Skip to: 40641 +/* 19541 */ MCD_OPC_Decode, 191, 18, 112, // Opcode: UZP2v4i32 +/* 19545 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 19624 +/* 19549 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19552 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19570 +/* 19556 */ MCD_OPC_CheckPredicate, 0, 89, 82, // Skip to: 40641 +/* 19560 */ MCD_OPC_CheckField, 21, 1, 1, 83, 82, // Skip to: 40641 +/* 19566 */ MCD_OPC_Decode, 247, 11, 89, // Opcode: SQRSHLv2i32 +/* 19570 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19588 +/* 19574 */ MCD_OPC_CheckPredicate, 0, 71, 82, // Skip to: 40641 +/* 19578 */ MCD_OPC_CheckField, 21, 1, 1, 65, 82, // Skip to: 40641 +/* 19584 */ MCD_OPC_Decode, 155, 17, 89, // Opcode: UQRSHLv2i32 +/* 19588 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19606 +/* 19592 */ MCD_OPC_CheckPredicate, 0, 53, 82, // Skip to: 40641 +/* 19596 */ MCD_OPC_CheckField, 21, 1, 1, 47, 82, // Skip to: 40641 +/* 19602 */ MCD_OPC_Decode, 250, 11, 112, // Opcode: SQRSHLv4i32 +/* 19606 */ MCD_OPC_FilterValue, 3, 39, 82, // Skip to: 40641 +/* 19610 */ MCD_OPC_CheckPredicate, 0, 35, 82, // Skip to: 40641 +/* 19614 */ MCD_OPC_CheckField, 21, 1, 1, 29, 82, // Skip to: 40641 +/* 19620 */ MCD_OPC_Decode, 158, 17, 112, // Opcode: UQRSHLv4i32 +/* 19624 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 19703 +/* 19628 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19631 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19649 +/* 19635 */ MCD_OPC_CheckPredicate, 0, 10, 82, // Skip to: 40641 +/* 19639 */ MCD_OPC_CheckField, 21, 1, 1, 4, 82, // Skip to: 40641 +/* 19645 */ MCD_OPC_Decode, 151, 15, 103, // Opcode: SUBHNv2i64_v2i32 +/* 19649 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19667 +/* 19653 */ MCD_OPC_CheckPredicate, 0, 248, 81, // Skip to: 40641 +/* 19657 */ MCD_OPC_CheckField, 21, 1, 1, 242, 81, // Skip to: 40641 +/* 19663 */ MCD_OPC_Decode, 195, 9, 103, // Opcode: RSUBHNv2i64_v2i32 +/* 19667 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19685 +/* 19671 */ MCD_OPC_CheckPredicate, 0, 230, 81, // Skip to: 40641 +/* 19675 */ MCD_OPC_CheckField, 21, 1, 1, 224, 81, // Skip to: 40641 +/* 19681 */ MCD_OPC_Decode, 152, 15, 120, // Opcode: SUBHNv2i64_v4i32 +/* 19685 */ MCD_OPC_FilterValue, 3, 216, 81, // Skip to: 40641 +/* 19689 */ MCD_OPC_CheckPredicate, 0, 212, 81, // Skip to: 40641 +/* 19693 */ MCD_OPC_CheckField, 21, 1, 1, 206, 81, // Skip to: 40641 +/* 19699 */ MCD_OPC_Decode, 196, 9, 120, // Opcode: RSUBHNv2i64_v4i32 +/* 19703 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 19782 +/* 19707 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19710 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19728 +/* 19714 */ MCD_OPC_CheckPredicate, 0, 187, 81, // Skip to: 40641 +/* 19718 */ MCD_OPC_CheckField, 21, 1, 1, 181, 81, // Skip to: 40641 +/* 19724 */ MCD_OPC_Decode, 217, 10, 89, // Opcode: SMAXv2i32 +/* 19728 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19746 +/* 19732 */ MCD_OPC_CheckPredicate, 0, 169, 81, // Skip to: 40641 +/* 19736 */ MCD_OPC_CheckField, 21, 1, 1, 163, 81, // Skip to: 40641 +/* 19742 */ MCD_OPC_Decode, 209, 16, 89, // Opcode: UMAXv2i32 +/* 19746 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19764 +/* 19750 */ MCD_OPC_CheckPredicate, 0, 151, 81, // Skip to: 40641 +/* 19754 */ MCD_OPC_CheckField, 21, 1, 1, 145, 81, // Skip to: 40641 +/* 19760 */ MCD_OPC_Decode, 219, 10, 112, // Opcode: SMAXv4i32 +/* 19764 */ MCD_OPC_FilterValue, 3, 137, 81, // Skip to: 40641 +/* 19768 */ MCD_OPC_CheckPredicate, 0, 133, 81, // Skip to: 40641 +/* 19772 */ MCD_OPC_CheckField, 21, 1, 1, 127, 81, // Skip to: 40641 +/* 19778 */ MCD_OPC_Decode, 211, 16, 112, // Opcode: UMAXv4i32 +/* 19782 */ MCD_OPC_FilterValue, 26, 113, 0, // Skip to: 19899 +/* 19786 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19789 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 19826 +/* 19793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 19796 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19808 +/* 19800 */ MCD_OPC_CheckPredicate, 0, 101, 81, // Skip to: 40641 +/* 19804 */ MCD_OPC_Decode, 229, 15, 89, // Opcode: TRN2v2i32 +/* 19808 */ MCD_OPC_FilterValue, 1, 93, 81, // Skip to: 40641 +/* 19812 */ MCD_OPC_CheckPredicate, 0, 89, 81, // Skip to: 40641 +/* 19816 */ MCD_OPC_CheckField, 16, 5, 0, 83, 81, // Skip to: 40641 +/* 19822 */ MCD_OPC_Decode, 226, 9, 99, // Opcode: SADALPv2i32_v1i64 +/* 19826 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19844 +/* 19830 */ MCD_OPC_CheckPredicate, 0, 71, 81, // Skip to: 40641 +/* 19834 */ MCD_OPC_CheckField, 16, 6, 32, 65, 81, // Skip to: 40641 +/* 19840 */ MCD_OPC_Decode, 132, 16, 99, // Opcode: UADALPv2i32_v1i64 +/* 19844 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 19881 +/* 19848 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 19851 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19863 +/* 19855 */ MCD_OPC_CheckPredicate, 0, 46, 81, // Skip to: 40641 +/* 19859 */ MCD_OPC_Decode, 232, 15, 112, // Opcode: TRN2v4i32 +/* 19863 */ MCD_OPC_FilterValue, 1, 38, 81, // Skip to: 40641 +/* 19867 */ MCD_OPC_CheckPredicate, 0, 34, 81, // Skip to: 40641 +/* 19871 */ MCD_OPC_CheckField, 16, 5, 0, 28, 81, // Skip to: 40641 +/* 19877 */ MCD_OPC_Decode, 228, 9, 126, // Opcode: SADALPv4i32_v2i64 +/* 19881 */ MCD_OPC_FilterValue, 3, 20, 81, // Skip to: 40641 +/* 19885 */ MCD_OPC_CheckPredicate, 0, 16, 81, // Skip to: 40641 +/* 19889 */ MCD_OPC_CheckField, 16, 6, 32, 10, 81, // Skip to: 40641 +/* 19895 */ MCD_OPC_Decode, 134, 16, 126, // Opcode: UADALPv4i32_v2i64 +/* 19899 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 19978 +/* 19903 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19906 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19924 +/* 19910 */ MCD_OPC_CheckPredicate, 0, 247, 80, // Skip to: 40641 +/* 19914 */ MCD_OPC_CheckField, 21, 1, 1, 241, 80, // Skip to: 40641 +/* 19920 */ MCD_OPC_Decode, 235, 10, 89, // Opcode: SMINv2i32 +/* 19924 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19942 +/* 19928 */ MCD_OPC_CheckPredicate, 0, 229, 80, // Skip to: 40641 +/* 19932 */ MCD_OPC_CheckField, 21, 1, 1, 223, 80, // Skip to: 40641 +/* 19938 */ MCD_OPC_Decode, 226, 16, 89, // Opcode: UMINv2i32 +/* 19942 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19960 +/* 19946 */ MCD_OPC_CheckPredicate, 0, 211, 80, // Skip to: 40641 +/* 19950 */ MCD_OPC_CheckField, 21, 1, 1, 205, 80, // Skip to: 40641 +/* 19956 */ MCD_OPC_Decode, 237, 10, 112, // Opcode: SMINv4i32 +/* 19960 */ MCD_OPC_FilterValue, 3, 197, 80, // Skip to: 40641 +/* 19964 */ MCD_OPC_CheckPredicate, 0, 193, 80, // Skip to: 40641 +/* 19968 */ MCD_OPC_CheckField, 21, 1, 1, 187, 80, // Skip to: 40641 +/* 19974 */ MCD_OPC_Decode, 228, 16, 112, // Opcode: UMINv4i32 +/* 19978 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 20057 +/* 19982 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 19985 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20003 +/* 19989 */ MCD_OPC_CheckPredicate, 0, 168, 80, // Skip to: 40641 +/* 19993 */ MCD_OPC_CheckField, 21, 1, 1, 162, 80, // Skip to: 40641 +/* 19999 */ MCD_OPC_Decode, 214, 9, 85, // Opcode: SABDLv2i32_v2i64 +/* 20003 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20021 +/* 20007 */ MCD_OPC_CheckPredicate, 0, 150, 80, // Skip to: 40641 +/* 20011 */ MCD_OPC_CheckField, 21, 1, 1, 144, 80, // Skip to: 40641 +/* 20017 */ MCD_OPC_Decode, 248, 15, 85, // Opcode: UABDLv2i32_v2i64 +/* 20021 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20039 +/* 20025 */ MCD_OPC_CheckPredicate, 0, 132, 80, // Skip to: 40641 +/* 20029 */ MCD_OPC_CheckField, 21, 1, 1, 126, 80, // Skip to: 40641 +/* 20035 */ MCD_OPC_Decode, 216, 9, 112, // Opcode: SABDLv4i32_v2i64 +/* 20039 */ MCD_OPC_FilterValue, 3, 118, 80, // Skip to: 40641 +/* 20043 */ MCD_OPC_CheckPredicate, 0, 114, 80, // Skip to: 40641 +/* 20047 */ MCD_OPC_CheckField, 21, 1, 1, 108, 80, // Skip to: 40641 +/* 20053 */ MCD_OPC_Decode, 250, 15, 112, // Opcode: UABDLv4i32_v2i64 +/* 20057 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 20136 +/* 20061 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20064 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20082 +/* 20068 */ MCD_OPC_CheckPredicate, 0, 89, 80, // Skip to: 40641 +/* 20072 */ MCD_OPC_CheckField, 21, 1, 1, 83, 80, // Skip to: 40641 +/* 20078 */ MCD_OPC_Decode, 220, 9, 89, // Opcode: SABDv2i32 +/* 20082 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20100 +/* 20086 */ MCD_OPC_CheckPredicate, 0, 71, 80, // Skip to: 40641 +/* 20090 */ MCD_OPC_CheckField, 21, 1, 1, 65, 80, // Skip to: 40641 +/* 20096 */ MCD_OPC_Decode, 254, 15, 89, // Opcode: UABDv2i32 +/* 20100 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20118 +/* 20104 */ MCD_OPC_CheckPredicate, 0, 53, 80, // Skip to: 40641 +/* 20108 */ MCD_OPC_CheckField, 21, 1, 1, 47, 80, // Skip to: 40641 +/* 20114 */ MCD_OPC_Decode, 222, 9, 112, // Opcode: SABDv4i32 +/* 20118 */ MCD_OPC_FilterValue, 3, 39, 80, // Skip to: 40641 +/* 20122 */ MCD_OPC_CheckPredicate, 0, 35, 80, // Skip to: 40641 +/* 20126 */ MCD_OPC_CheckField, 21, 1, 1, 29, 80, // Skip to: 40641 +/* 20132 */ MCD_OPC_Decode, 128, 16, 112, // Opcode: UABDv4i32 +/* 20136 */ MCD_OPC_FilterValue, 30, 113, 0, // Skip to: 20253 +/* 20140 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20143 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 20180 +/* 20147 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 20150 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20162 +/* 20154 */ MCD_OPC_CheckPredicate, 0, 3, 80, // Skip to: 40641 +/* 20158 */ MCD_OPC_Decode, 208, 18, 89, // Opcode: ZIP2v2i32 +/* 20162 */ MCD_OPC_FilterValue, 1, 251, 79, // Skip to: 40641 +/* 20166 */ MCD_OPC_CheckPredicate, 0, 247, 79, // Skip to: 40641 +/* 20170 */ MCD_OPC_CheckField, 16, 5, 0, 241, 79, // Skip to: 40641 +/* 20176 */ MCD_OPC_Decode, 154, 11, 90, // Opcode: SQABSv2i32 +/* 20180 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20198 +/* 20184 */ MCD_OPC_CheckPredicate, 0, 229, 79, // Skip to: 40641 +/* 20188 */ MCD_OPC_CheckField, 16, 6, 32, 223, 79, // Skip to: 40641 +/* 20194 */ MCD_OPC_Decode, 224, 11, 90, // Opcode: SQNEGv2i32 +/* 20198 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 20235 +/* 20202 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 20205 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20217 +/* 20209 */ MCD_OPC_CheckPredicate, 0, 204, 79, // Skip to: 40641 +/* 20213 */ MCD_OPC_Decode, 211, 18, 112, // Opcode: ZIP2v4i32 +/* 20217 */ MCD_OPC_FilterValue, 1, 196, 79, // Skip to: 40641 +/* 20221 */ MCD_OPC_CheckPredicate, 0, 192, 79, // Skip to: 40641 +/* 20225 */ MCD_OPC_CheckField, 16, 5, 0, 186, 79, // Skip to: 40641 +/* 20231 */ MCD_OPC_Decode, 157, 11, 117, // Opcode: SQABSv4i32 +/* 20235 */ MCD_OPC_FilterValue, 3, 178, 79, // Skip to: 40641 +/* 20239 */ MCD_OPC_CheckPredicate, 0, 174, 79, // Skip to: 40641 +/* 20243 */ MCD_OPC_CheckField, 16, 6, 32, 168, 79, // Skip to: 40641 +/* 20249 */ MCD_OPC_Decode, 227, 11, 117, // Opcode: SQNEGv4i32 +/* 20253 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 20332 +/* 20257 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20260 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20278 +/* 20264 */ MCD_OPC_CheckPredicate, 0, 149, 79, // Skip to: 40641 +/* 20268 */ MCD_OPC_CheckField, 21, 1, 1, 143, 79, // Skip to: 40641 +/* 20274 */ MCD_OPC_Decode, 208, 9, 109, // Opcode: SABAv2i32 +/* 20278 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20296 +/* 20282 */ MCD_OPC_CheckPredicate, 0, 131, 79, // Skip to: 40641 +/* 20286 */ MCD_OPC_CheckField, 21, 1, 1, 125, 79, // Skip to: 40641 +/* 20292 */ MCD_OPC_Decode, 242, 15, 109, // Opcode: UABAv2i32 +/* 20296 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20314 +/* 20300 */ MCD_OPC_CheckPredicate, 0, 113, 79, // Skip to: 40641 +/* 20304 */ MCD_OPC_CheckField, 21, 1, 1, 107, 79, // Skip to: 40641 +/* 20310 */ MCD_OPC_Decode, 210, 9, 120, // Opcode: SABAv4i32 +/* 20314 */ MCD_OPC_FilterValue, 3, 99, 79, // Skip to: 40641 +/* 20318 */ MCD_OPC_CheckPredicate, 0, 95, 79, // Skip to: 40641 +/* 20322 */ MCD_OPC_CheckField, 21, 1, 1, 89, 79, // Skip to: 40641 +/* 20328 */ MCD_OPC_Decode, 244, 15, 120, // Opcode: UABAv4i32 +/* 20332 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 20411 +/* 20336 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20339 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20357 +/* 20343 */ MCD_OPC_CheckPredicate, 0, 70, 79, // Skip to: 40641 +/* 20347 */ MCD_OPC_CheckField, 21, 1, 1, 64, 79, // Skip to: 40641 +/* 20353 */ MCD_OPC_Decode, 242, 10, 105, // Opcode: SMLALv2i32_v2i64 +/* 20357 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20375 +/* 20361 */ MCD_OPC_CheckPredicate, 0, 52, 79, // Skip to: 40641 +/* 20365 */ MCD_OPC_CheckField, 21, 1, 1, 46, 79, // Skip to: 40641 +/* 20371 */ MCD_OPC_Decode, 233, 16, 105, // Opcode: UMLALv2i32_v2i64 +/* 20375 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20393 +/* 20379 */ MCD_OPC_CheckPredicate, 0, 34, 79, // Skip to: 40641 +/* 20383 */ MCD_OPC_CheckField, 21, 1, 1, 28, 79, // Skip to: 40641 +/* 20389 */ MCD_OPC_Decode, 246, 10, 120, // Opcode: SMLALv4i32_v2i64 +/* 20393 */ MCD_OPC_FilterValue, 3, 20, 79, // Skip to: 40641 +/* 20397 */ MCD_OPC_CheckPredicate, 0, 16, 79, // Skip to: 40641 +/* 20401 */ MCD_OPC_CheckField, 21, 1, 1, 10, 79, // Skip to: 40641 +/* 20407 */ MCD_OPC_Decode, 237, 16, 120, // Opcode: UMLALv4i32_v2i64 +/* 20411 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 20488 +/* 20415 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20418 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 20435 +/* 20422 */ MCD_OPC_CheckPredicate, 0, 247, 78, // Skip to: 40641 +/* 20426 */ MCD_OPC_CheckField, 21, 1, 1, 241, 78, // Skip to: 40641 +/* 20432 */ MCD_OPC_Decode, 73, 89, // Opcode: ADDv2i32 +/* 20435 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20453 +/* 20439 */ MCD_OPC_CheckPredicate, 0, 230, 78, // Skip to: 40641 +/* 20443 */ MCD_OPC_CheckField, 21, 1, 1, 224, 78, // Skip to: 40641 +/* 20449 */ MCD_OPC_Decode, 177, 15, 89, // Opcode: SUBv2i32 +/* 20453 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 20470 +/* 20457 */ MCD_OPC_CheckPredicate, 0, 212, 78, // Skip to: 40641 +/* 20461 */ MCD_OPC_CheckField, 21, 1, 1, 206, 78, // Skip to: 40641 +/* 20467 */ MCD_OPC_Decode, 76, 112, // Opcode: ADDv4i32 +/* 20470 */ MCD_OPC_FilterValue, 3, 199, 78, // Skip to: 40641 +/* 20474 */ MCD_OPC_CheckPredicate, 0, 195, 78, // Skip to: 40641 +/* 20478 */ MCD_OPC_CheckField, 21, 1, 1, 189, 78, // Skip to: 40641 +/* 20484 */ MCD_OPC_Decode, 180, 15, 112, // Opcode: SUBv4i32 +/* 20488 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 20593 +/* 20492 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20495 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20526 +/* 20499 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20502 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20514 +/* 20506 */ MCD_OPC_CheckPredicate, 0, 163, 78, // Skip to: 40641 +/* 20510 */ MCD_OPC_Decode, 197, 1, 90, // Opcode: CMGTv2i32rz +/* 20514 */ MCD_OPC_FilterValue, 33, 155, 78, // Skip to: 40641 +/* 20518 */ MCD_OPC_CheckPredicate, 0, 151, 78, // Skip to: 40641 +/* 20522 */ MCD_OPC_Decode, 174, 5, 90, // Opcode: FRINTPv2f32 +/* 20526 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20544 +/* 20530 */ MCD_OPC_CheckPredicate, 0, 139, 78, // Skip to: 40641 +/* 20534 */ MCD_OPC_CheckField, 16, 6, 32, 133, 78, // Skip to: 40641 +/* 20540 */ MCD_OPC_Decode, 181, 1, 90, // Opcode: CMGEv2i32rz +/* 20544 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20575 +/* 20548 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20551 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20563 +/* 20555 */ MCD_OPC_CheckPredicate, 0, 114, 78, // Skip to: 40641 +/* 20559 */ MCD_OPC_Decode, 203, 1, 117, // Opcode: CMGTv4i32rz +/* 20563 */ MCD_OPC_FilterValue, 33, 106, 78, // Skip to: 40641 +/* 20567 */ MCD_OPC_CheckPredicate, 0, 102, 78, // Skip to: 40641 +/* 20571 */ MCD_OPC_Decode, 176, 5, 117, // Opcode: FRINTPv4f32 +/* 20575 */ MCD_OPC_FilterValue, 3, 94, 78, // Skip to: 40641 +/* 20579 */ MCD_OPC_CheckPredicate, 0, 90, 78, // Skip to: 40641 +/* 20583 */ MCD_OPC_CheckField, 16, 6, 32, 84, 78, // Skip to: 40641 +/* 20589 */ MCD_OPC_Decode, 187, 1, 117, // Opcode: CMGEv4i32rz +/* 20593 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 20672 +/* 20597 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20600 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20618 +/* 20604 */ MCD_OPC_CheckPredicate, 0, 65, 78, // Skip to: 40641 +/* 20608 */ MCD_OPC_CheckField, 21, 1, 1, 59, 78, // Skip to: 40641 +/* 20614 */ MCD_OPC_Decode, 242, 1, 89, // Opcode: CMTSTv2i32 +/* 20618 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20636 +/* 20622 */ MCD_OPC_CheckPredicate, 0, 47, 78, // Skip to: 40641 +/* 20626 */ MCD_OPC_CheckField, 21, 1, 1, 41, 78, // Skip to: 40641 +/* 20632 */ MCD_OPC_Decode, 164, 1, 89, // Opcode: CMEQv2i32 +/* 20636 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20654 +/* 20640 */ MCD_OPC_CheckPredicate, 0, 29, 78, // Skip to: 40641 +/* 20644 */ MCD_OPC_CheckField, 21, 1, 1, 23, 78, // Skip to: 40641 +/* 20650 */ MCD_OPC_Decode, 245, 1, 112, // Opcode: CMTSTv4i32 +/* 20654 */ MCD_OPC_FilterValue, 3, 15, 78, // Skip to: 40641 +/* 20658 */ MCD_OPC_CheckPredicate, 0, 11, 78, // Skip to: 40641 +/* 20662 */ MCD_OPC_CheckField, 21, 1, 1, 5, 78, // Skip to: 40641 +/* 20668 */ MCD_OPC_Decode, 170, 1, 112, // Opcode: CMEQv4i32 +/* 20672 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 20715 +/* 20676 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20679 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20697 +/* 20683 */ MCD_OPC_CheckPredicate, 0, 242, 77, // Skip to: 40641 +/* 20687 */ MCD_OPC_CheckField, 21, 1, 1, 236, 77, // Skip to: 40641 +/* 20693 */ MCD_OPC_Decode, 176, 11, 105, // Opcode: SQDMLALv2i32_v2i64 +/* 20697 */ MCD_OPC_FilterValue, 2, 228, 77, // Skip to: 40641 +/* 20701 */ MCD_OPC_CheckPredicate, 0, 224, 77, // Skip to: 40641 +/* 20705 */ MCD_OPC_CheckField, 21, 1, 1, 218, 77, // Skip to: 40641 +/* 20711 */ MCD_OPC_Decode, 180, 11, 120, // Opcode: SQDMLALv4i32_v2i64 +/* 20715 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 20794 +/* 20719 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20722 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20740 +/* 20726 */ MCD_OPC_CheckPredicate, 0, 199, 77, // Skip to: 40641 +/* 20730 */ MCD_OPC_CheckField, 21, 1, 1, 193, 77, // Skip to: 40641 +/* 20736 */ MCD_OPC_Decode, 183, 8, 109, // Opcode: MLAv2i32 +/* 20740 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20758 +/* 20744 */ MCD_OPC_CheckPredicate, 0, 181, 77, // Skip to: 40641 +/* 20748 */ MCD_OPC_CheckField, 21, 1, 1, 175, 77, // Skip to: 40641 +/* 20754 */ MCD_OPC_Decode, 193, 8, 109, // Opcode: MLSv2i32 +/* 20758 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20776 +/* 20762 */ MCD_OPC_CheckPredicate, 0, 163, 77, // Skip to: 40641 +/* 20766 */ MCD_OPC_CheckField, 21, 1, 1, 157, 77, // Skip to: 40641 +/* 20772 */ MCD_OPC_Decode, 187, 8, 120, // Opcode: MLAv4i32 +/* 20776 */ MCD_OPC_FilterValue, 3, 149, 77, // Skip to: 40641 +/* 20780 */ MCD_OPC_CheckPredicate, 0, 145, 77, // Skip to: 40641 +/* 20784 */ MCD_OPC_CheckField, 21, 1, 1, 139, 77, // Skip to: 40641 +/* 20790 */ MCD_OPC_Decode, 197, 8, 120, // Opcode: MLSv4i32 +/* 20794 */ MCD_OPC_FilterValue, 38, 127, 0, // Skip to: 20925 +/* 20798 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20801 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20832 +/* 20805 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20808 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20820 +/* 20812 */ MCD_OPC_CheckPredicate, 0, 113, 77, // Skip to: 40641 +/* 20816 */ MCD_OPC_Decode, 165, 1, 90, // Opcode: CMEQv2i32rz +/* 20820 */ MCD_OPC_FilterValue, 33, 105, 77, // Skip to: 40641 +/* 20824 */ MCD_OPC_CheckPredicate, 0, 101, 77, // Skip to: 40641 +/* 20828 */ MCD_OPC_Decode, 184, 5, 90, // Opcode: FRINTZv2f32 +/* 20832 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 20863 +/* 20836 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20839 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20851 +/* 20843 */ MCD_OPC_CheckPredicate, 0, 82, 77, // Skip to: 40641 +/* 20847 */ MCD_OPC_Decode, 226, 1, 90, // Opcode: CMLEv2i32rz +/* 20851 */ MCD_OPC_FilterValue, 33, 74, 77, // Skip to: 40641 +/* 20855 */ MCD_OPC_CheckPredicate, 0, 70, 77, // Skip to: 40641 +/* 20859 */ MCD_OPC_Decode, 159, 5, 90, // Opcode: FRINTIv2f32 +/* 20863 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20894 +/* 20867 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20870 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20882 +/* 20874 */ MCD_OPC_CheckPredicate, 0, 51, 77, // Skip to: 40641 +/* 20878 */ MCD_OPC_Decode, 171, 1, 117, // Opcode: CMEQv4i32rz +/* 20882 */ MCD_OPC_FilterValue, 33, 43, 77, // Skip to: 40641 +/* 20886 */ MCD_OPC_CheckPredicate, 0, 39, 77, // Skip to: 40641 +/* 20890 */ MCD_OPC_Decode, 186, 5, 117, // Opcode: FRINTZv4f32 +/* 20894 */ MCD_OPC_FilterValue, 3, 31, 77, // Skip to: 40641 +/* 20898 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 20901 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20913 +/* 20905 */ MCD_OPC_CheckPredicate, 0, 20, 77, // Skip to: 40641 +/* 20909 */ MCD_OPC_Decode, 229, 1, 117, // Opcode: CMLEv4i32rz +/* 20913 */ MCD_OPC_FilterValue, 33, 12, 77, // Skip to: 40641 +/* 20917 */ MCD_OPC_CheckPredicate, 0, 8, 77, // Skip to: 40641 +/* 20921 */ MCD_OPC_Decode, 161, 5, 117, // Opcode: FRINTIv4f32 +/* 20925 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 20968 +/* 20929 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20932 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20950 +/* 20936 */ MCD_OPC_CheckPredicate, 0, 245, 76, // Skip to: 40641 +/* 20940 */ MCD_OPC_CheckField, 21, 1, 1, 239, 76, // Skip to: 40641 +/* 20946 */ MCD_OPC_Decode, 232, 8, 89, // Opcode: MULv2i32 +/* 20950 */ MCD_OPC_FilterValue, 2, 231, 76, // Skip to: 40641 +/* 20954 */ MCD_OPC_CheckPredicate, 0, 227, 76, // Skip to: 40641 +/* 20958 */ MCD_OPC_CheckField, 21, 1, 1, 221, 76, // Skip to: 40641 +/* 20964 */ MCD_OPC_Decode, 236, 8, 112, // Opcode: MULv4i32 +/* 20968 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 21047 +/* 20972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 20975 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20993 +/* 20979 */ MCD_OPC_CheckPredicate, 0, 202, 76, // Skip to: 40641 +/* 20983 */ MCD_OPC_CheckField, 21, 1, 1, 196, 76, // Skip to: 40641 +/* 20989 */ MCD_OPC_Decode, 252, 10, 105, // Opcode: SMLSLv2i32_v2i64 +/* 20993 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21011 +/* 20997 */ MCD_OPC_CheckPredicate, 0, 184, 76, // Skip to: 40641 +/* 21001 */ MCD_OPC_CheckField, 21, 1, 1, 178, 76, // Skip to: 40641 +/* 21007 */ MCD_OPC_Decode, 243, 16, 105, // Opcode: UMLSLv2i32_v2i64 +/* 21011 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21029 +/* 21015 */ MCD_OPC_CheckPredicate, 0, 166, 76, // Skip to: 40641 +/* 21019 */ MCD_OPC_CheckField, 21, 1, 1, 160, 76, // Skip to: 40641 +/* 21025 */ MCD_OPC_Decode, 128, 11, 120, // Opcode: SMLSLv4i32_v2i64 +/* 21029 */ MCD_OPC_FilterValue, 3, 152, 76, // Skip to: 40641 +/* 21033 */ MCD_OPC_CheckPredicate, 0, 148, 76, // Skip to: 40641 +/* 21037 */ MCD_OPC_CheckField, 21, 1, 1, 142, 76, // Skip to: 40641 +/* 21043 */ MCD_OPC_Decode, 247, 16, 120, // Opcode: UMLSLv4i32_v2i64 +/* 21047 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 21126 +/* 21051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21054 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21072 +/* 21058 */ MCD_OPC_CheckPredicate, 0, 123, 76, // Skip to: 40641 +/* 21062 */ MCD_OPC_CheckField, 21, 1, 1, 117, 76, // Skip to: 40641 +/* 21068 */ MCD_OPC_Decode, 206, 10, 89, // Opcode: SMAXPv2i32 +/* 21072 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21090 +/* 21076 */ MCD_OPC_CheckPredicate, 0, 105, 76, // Skip to: 40641 +/* 21080 */ MCD_OPC_CheckField, 21, 1, 1, 99, 76, // Skip to: 40641 +/* 21086 */ MCD_OPC_Decode, 198, 16, 89, // Opcode: UMAXPv2i32 +/* 21090 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21108 +/* 21094 */ MCD_OPC_CheckPredicate, 0, 87, 76, // Skip to: 40641 +/* 21098 */ MCD_OPC_CheckField, 21, 1, 1, 81, 76, // Skip to: 40641 +/* 21104 */ MCD_OPC_Decode, 208, 10, 112, // Opcode: SMAXPv4i32 +/* 21108 */ MCD_OPC_FilterValue, 3, 73, 76, // Skip to: 40641 +/* 21112 */ MCD_OPC_CheckPredicate, 0, 69, 76, // Skip to: 40641 +/* 21116 */ MCD_OPC_CheckField, 21, 1, 1, 63, 76, // Skip to: 40641 +/* 21122 */ MCD_OPC_Decode, 200, 16, 112, // Opcode: UMAXPv4i32 +/* 21126 */ MCD_OPC_FilterValue, 42, 155, 0, // Skip to: 21285 +/* 21130 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21133 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 21164 +/* 21137 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21140 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21152 +/* 21144 */ MCD_OPC_CheckPredicate, 0, 37, 76, // Skip to: 40641 +/* 21148 */ MCD_OPC_Decode, 234, 1, 90, // Opcode: CMLTv2i32rz +/* 21152 */ MCD_OPC_FilterValue, 2, 29, 76, // Skip to: 40641 +/* 21156 */ MCD_OPC_CheckPredicate, 0, 25, 76, // Skip to: 40641 +/* 21160 */ MCD_OPC_Decode, 237, 1, 117, // Opcode: CMLTv4i32rz +/* 21164 */ MCD_OPC_FilterValue, 33, 51, 0, // Skip to: 21219 +/* 21168 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21183 +/* 21175 */ MCD_OPC_CheckPredicate, 0, 6, 76, // Skip to: 40641 +/* 21179 */ MCD_OPC_Decode, 208, 3, 90, // Opcode: FCVTPSv2f32 +/* 21183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 21195 +/* 21187 */ MCD_OPC_CheckPredicate, 0, 250, 75, // Skip to: 40641 +/* 21191 */ MCD_OPC_Decode, 217, 3, 90, // Opcode: FCVTPUv2f32 +/* 21195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 21207 +/* 21199 */ MCD_OPC_CheckPredicate, 0, 238, 75, // Skip to: 40641 +/* 21203 */ MCD_OPC_Decode, 210, 3, 117, // Opcode: FCVTPSv4f32 +/* 21207 */ MCD_OPC_FilterValue, 3, 230, 75, // Skip to: 40641 +/* 21211 */ MCD_OPC_CheckPredicate, 0, 226, 75, // Skip to: 40641 +/* 21215 */ MCD_OPC_Decode, 219, 3, 117, // Opcode: FCVTPUv4f32 +/* 21219 */ MCD_OPC_FilterValue, 48, 29, 0, // Skip to: 21252 +/* 21223 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21226 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21239 +/* 21230 */ MCD_OPC_CheckPredicate, 0, 207, 75, // Skip to: 40641 +/* 21234 */ MCD_OPC_Decode, 213, 10, 139, 1, // Opcode: SMAXVv4i32v +/* 21239 */ MCD_OPC_FilterValue, 3, 198, 75, // Skip to: 40641 +/* 21243 */ MCD_OPC_CheckPredicate, 0, 194, 75, // Skip to: 40641 +/* 21247 */ MCD_OPC_Decode, 205, 16, 139, 1, // Opcode: UMAXVv4i32v +/* 21252 */ MCD_OPC_FilterValue, 49, 185, 75, // Skip to: 40641 +/* 21256 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21259 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21272 +/* 21263 */ MCD_OPC_CheckPredicate, 0, 174, 75, // Skip to: 40641 +/* 21267 */ MCD_OPC_Decode, 231, 10, 139, 1, // Opcode: SMINVv4i32v +/* 21272 */ MCD_OPC_FilterValue, 3, 165, 75, // Skip to: 40641 +/* 21276 */ MCD_OPC_CheckPredicate, 0, 161, 75, // Skip to: 40641 +/* 21280 */ MCD_OPC_Decode, 222, 16, 139, 1, // Opcode: UMINVv4i32v +/* 21285 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 21364 +/* 21289 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21292 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21310 +/* 21296 */ MCD_OPC_CheckPredicate, 0, 141, 75, // Skip to: 40641 +/* 21300 */ MCD_OPC_CheckField, 21, 1, 1, 135, 75, // Skip to: 40641 +/* 21306 */ MCD_OPC_Decode, 224, 10, 89, // Opcode: SMINPv2i32 +/* 21310 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21328 +/* 21314 */ MCD_OPC_CheckPredicate, 0, 123, 75, // Skip to: 40641 +/* 21318 */ MCD_OPC_CheckField, 21, 1, 1, 117, 75, // Skip to: 40641 +/* 21324 */ MCD_OPC_Decode, 215, 16, 89, // Opcode: UMINPv2i32 +/* 21328 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21346 +/* 21332 */ MCD_OPC_CheckPredicate, 0, 105, 75, // Skip to: 40641 +/* 21336 */ MCD_OPC_CheckField, 21, 1, 1, 99, 75, // Skip to: 40641 +/* 21342 */ MCD_OPC_Decode, 226, 10, 112, // Opcode: SMINPv4i32 +/* 21346 */ MCD_OPC_FilterValue, 3, 91, 75, // Skip to: 40641 +/* 21350 */ MCD_OPC_CheckPredicate, 0, 87, 75, // Skip to: 40641 +/* 21354 */ MCD_OPC_CheckField, 21, 1, 1, 81, 75, // Skip to: 40641 +/* 21360 */ MCD_OPC_Decode, 217, 16, 112, // Opcode: UMINPv4i32 +/* 21364 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 21407 +/* 21368 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21371 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21389 +/* 21375 */ MCD_OPC_CheckPredicate, 0, 62, 75, // Skip to: 40641 +/* 21379 */ MCD_OPC_CheckField, 21, 1, 1, 56, 75, // Skip to: 40641 +/* 21385 */ MCD_OPC_Decode, 188, 11, 105, // Opcode: SQDMLSLv2i32_v2i64 +/* 21389 */ MCD_OPC_FilterValue, 2, 48, 75, // Skip to: 40641 +/* 21393 */ MCD_OPC_CheckPredicate, 0, 44, 75, // Skip to: 40641 +/* 21397 */ MCD_OPC_CheckField, 21, 1, 1, 38, 75, // Skip to: 40641 +/* 21403 */ MCD_OPC_Decode, 192, 11, 120, // Opcode: SQDMLSLv4i32_v2i64 +/* 21407 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 21486 +/* 21411 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21414 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21432 +/* 21418 */ MCD_OPC_CheckPredicate, 0, 19, 75, // Skip to: 40641 +/* 21422 */ MCD_OPC_CheckField, 21, 1, 1, 13, 75, // Skip to: 40641 +/* 21428 */ MCD_OPC_Decode, 199, 11, 89, // Opcode: SQDMULHv2i32 +/* 21432 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21450 +/* 21436 */ MCD_OPC_CheckPredicate, 0, 1, 75, // Skip to: 40641 +/* 21440 */ MCD_OPC_CheckField, 21, 1, 1, 251, 74, // Skip to: 40641 +/* 21446 */ MCD_OPC_Decode, 234, 11, 89, // Opcode: SQRDMULHv2i32 +/* 21450 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21468 +/* 21454 */ MCD_OPC_CheckPredicate, 0, 239, 74, // Skip to: 40641 +/* 21458 */ MCD_OPC_CheckField, 21, 1, 1, 233, 74, // Skip to: 40641 +/* 21464 */ MCD_OPC_Decode, 203, 11, 112, // Opcode: SQDMULHv4i32 +/* 21468 */ MCD_OPC_FilterValue, 3, 225, 74, // Skip to: 40641 +/* 21472 */ MCD_OPC_CheckPredicate, 0, 221, 74, // Skip to: 40641 +/* 21476 */ MCD_OPC_CheckField, 21, 1, 1, 215, 74, // Skip to: 40641 +/* 21482 */ MCD_OPC_Decode, 238, 11, 112, // Opcode: SQRDMULHv4i32 +/* 21486 */ MCD_OPC_FilterValue, 46, 137, 0, // Skip to: 21627 +/* 21490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21493 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 21523 +/* 21497 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21500 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21511 +/* 21504 */ MCD_OPC_CheckPredicate, 0, 189, 74, // Skip to: 40641 +/* 21508 */ MCD_OPC_Decode, 24, 90, // Opcode: ABSv2i32 +/* 21511 */ MCD_OPC_FilterValue, 33, 182, 74, // Skip to: 40641 +/* 21515 */ MCD_OPC_CheckPredicate, 0, 178, 74, // Skip to: 40641 +/* 21519 */ MCD_OPC_Decode, 248, 3, 90, // Opcode: FCVTZSv2f32 +/* 21523 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21554 +/* 21527 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21530 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21542 +/* 21534 */ MCD_OPC_CheckPredicate, 0, 159, 74, // Skip to: 40641 +/* 21538 */ MCD_OPC_Decode, 249, 8, 90, // Opcode: NEGv2i32 +/* 21542 */ MCD_OPC_FilterValue, 33, 151, 74, // Skip to: 40641 +/* 21546 */ MCD_OPC_CheckPredicate, 0, 147, 74, // Skip to: 40641 +/* 21550 */ MCD_OPC_Decode, 149, 4, 90, // Opcode: FCVTZUv2f32 +/* 21554 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 21596 +/* 21558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21561 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21572 +/* 21565 */ MCD_OPC_CheckPredicate, 0, 128, 74, // Skip to: 40641 +/* 21569 */ MCD_OPC_Decode, 27, 117, // Opcode: ABSv4i32 +/* 21572 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21584 +/* 21576 */ MCD_OPC_CheckPredicate, 0, 117, 74, // Skip to: 40641 +/* 21580 */ MCD_OPC_Decode, 252, 3, 117, // Opcode: FCVTZSv4f32 +/* 21584 */ MCD_OPC_FilterValue, 49, 109, 74, // Skip to: 40641 +/* 21588 */ MCD_OPC_CheckPredicate, 0, 105, 74, // Skip to: 40641 +/* 21592 */ MCD_OPC_Decode, 59, 139, 1, // Opcode: ADDVv4i32v +/* 21596 */ MCD_OPC_FilterValue, 3, 97, 74, // Skip to: 40641 +/* 21600 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21603 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21615 +/* 21607 */ MCD_OPC_CheckPredicate, 0, 86, 74, // Skip to: 40641 +/* 21611 */ MCD_OPC_Decode, 252, 8, 117, // Opcode: NEGv4i32 +/* 21615 */ MCD_OPC_FilterValue, 33, 78, 74, // Skip to: 40641 +/* 21619 */ MCD_OPC_CheckPredicate, 0, 74, 74, // Skip to: 40641 +/* 21623 */ MCD_OPC_Decode, 153, 4, 117, // Opcode: FCVTZUv4f32 +/* 21627 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 21668 +/* 21631 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21634 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 21651 +/* 21638 */ MCD_OPC_CheckPredicate, 0, 55, 74, // Skip to: 40641 +/* 21642 */ MCD_OPC_CheckField, 21, 1, 1, 49, 74, // Skip to: 40641 +/* 21648 */ MCD_OPC_Decode, 41, 89, // Opcode: ADDPv2i32 +/* 21651 */ MCD_OPC_FilterValue, 2, 42, 74, // Skip to: 40641 +/* 21655 */ MCD_OPC_CheckPredicate, 0, 38, 74, // Skip to: 40641 +/* 21659 */ MCD_OPC_CheckField, 21, 1, 1, 32, 74, // Skip to: 40641 +/* 21665 */ MCD_OPC_Decode, 45, 112, // Opcode: ADDPv4i32 +/* 21668 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 21747 +/* 21672 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21675 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21693 +/* 21679 */ MCD_OPC_CheckPredicate, 0, 14, 74, // Skip to: 40641 +/* 21683 */ MCD_OPC_CheckField, 21, 1, 1, 8, 74, // Skip to: 40641 +/* 21689 */ MCD_OPC_Decode, 141, 11, 85, // Opcode: SMULLv2i32_v2i64 +/* 21693 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21711 +/* 21697 */ MCD_OPC_CheckPredicate, 0, 252, 73, // Skip to: 40641 +/* 21701 */ MCD_OPC_CheckField, 21, 1, 1, 246, 73, // Skip to: 40641 +/* 21707 */ MCD_OPC_Decode, 131, 17, 85, // Opcode: UMULLv2i32_v2i64 +/* 21711 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21729 +/* 21715 */ MCD_OPC_CheckPredicate, 0, 234, 73, // Skip to: 40641 +/* 21719 */ MCD_OPC_CheckField, 21, 1, 1, 228, 73, // Skip to: 40641 +/* 21725 */ MCD_OPC_Decode, 145, 11, 112, // Opcode: SMULLv4i32_v2i64 +/* 21729 */ MCD_OPC_FilterValue, 3, 220, 73, // Skip to: 40641 +/* 21733 */ MCD_OPC_CheckPredicate, 0, 216, 73, // Skip to: 40641 +/* 21737 */ MCD_OPC_CheckField, 21, 1, 1, 210, 73, // Skip to: 40641 +/* 21743 */ MCD_OPC_Decode, 135, 17, 112, // Opcode: UMULLv4i32_v2i64 +/* 21747 */ MCD_OPC_FilterValue, 49, 75, 0, // Skip to: 21826 +/* 21751 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21754 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21772 +/* 21758 */ MCD_OPC_CheckPredicate, 0, 191, 73, // Skip to: 40641 +/* 21762 */ MCD_OPC_CheckField, 21, 1, 1, 185, 73, // Skip to: 40641 +/* 21768 */ MCD_OPC_Decode, 193, 4, 89, // Opcode: FMINNMv2f32 +/* 21772 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21790 +/* 21776 */ MCD_OPC_CheckPredicate, 0, 173, 73, // Skip to: 40641 +/* 21780 */ MCD_OPC_CheckField, 21, 1, 1, 167, 73, // Skip to: 40641 +/* 21786 */ MCD_OPC_Decode, 186, 4, 89, // Opcode: FMINNMPv2f32 +/* 21790 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21808 +/* 21794 */ MCD_OPC_CheckPredicate, 0, 155, 73, // Skip to: 40641 +/* 21798 */ MCD_OPC_CheckField, 21, 1, 1, 149, 73, // Skip to: 40641 +/* 21804 */ MCD_OPC_Decode, 195, 4, 112, // Opcode: FMINNMv4f32 +/* 21808 */ MCD_OPC_FilterValue, 3, 141, 73, // Skip to: 40641 +/* 21812 */ MCD_OPC_CheckPredicate, 0, 137, 73, // Skip to: 40641 +/* 21816 */ MCD_OPC_CheckField, 21, 1, 1, 131, 73, // Skip to: 40641 +/* 21822 */ MCD_OPC_Decode, 190, 4, 112, // Opcode: FMINNMPv4f32 +/* 21826 */ MCD_OPC_FilterValue, 50, 140, 0, // Skip to: 21970 +/* 21830 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21833 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 21864 +/* 21837 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21840 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21852 +/* 21844 */ MCD_OPC_CheckPredicate, 0, 105, 73, // Skip to: 40641 +/* 21848 */ MCD_OPC_Decode, 240, 2, 90, // Opcode: FCMGTv2i32rz +/* 21852 */ MCD_OPC_FilterValue, 33, 97, 73, // Skip to: 40641 +/* 21856 */ MCD_OPC_CheckPredicate, 0, 93, 73, // Skip to: 40641 +/* 21860 */ MCD_OPC_Decode, 221, 17, 90, // Opcode: URECPEv2i32 +/* 21864 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21895 +/* 21868 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21871 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21883 +/* 21875 */ MCD_OPC_CheckPredicate, 0, 74, 73, // Skip to: 40641 +/* 21879 */ MCD_OPC_Decode, 230, 2, 90, // Opcode: FCMGEv2i32rz +/* 21883 */ MCD_OPC_FilterValue, 33, 66, 73, // Skip to: 40641 +/* 21887 */ MCD_OPC_CheckPredicate, 0, 62, 73, // Skip to: 40641 +/* 21891 */ MCD_OPC_Decode, 245, 17, 90, // Opcode: URSQRTEv2i32 +/* 21895 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 21926 +/* 21899 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21902 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21914 +/* 21906 */ MCD_OPC_CheckPredicate, 0, 43, 73, // Skip to: 40641 +/* 21910 */ MCD_OPC_Decode, 243, 2, 117, // Opcode: FCMGTv4i32rz +/* 21914 */ MCD_OPC_FilterValue, 33, 35, 73, // Skip to: 40641 +/* 21918 */ MCD_OPC_CheckPredicate, 0, 31, 73, // Skip to: 40641 +/* 21922 */ MCD_OPC_Decode, 222, 17, 117, // Opcode: URECPEv4i32 +/* 21926 */ MCD_OPC_FilterValue, 3, 23, 73, // Skip to: 40641 +/* 21930 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 21933 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21945 +/* 21937 */ MCD_OPC_CheckPredicate, 0, 12, 73, // Skip to: 40641 +/* 21941 */ MCD_OPC_Decode, 233, 2, 117, // Opcode: FCMGEv4i32rz +/* 21945 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21957 +/* 21949 */ MCD_OPC_CheckPredicate, 0, 0, 73, // Skip to: 40641 +/* 21953 */ MCD_OPC_Decode, 246, 17, 117, // Opcode: URSQRTEv4i32 +/* 21957 */ MCD_OPC_FilterValue, 48, 248, 72, // Skip to: 40641 +/* 21961 */ MCD_OPC_CheckPredicate, 0, 244, 72, // Skip to: 40641 +/* 21965 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: FMINNMVv4i32v +/* 21970 */ MCD_OPC_FilterValue, 51, 39, 0, // Skip to: 22013 +/* 21974 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 21977 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21995 +/* 21981 */ MCD_OPC_CheckPredicate, 0, 224, 72, // Skip to: 40641 +/* 21985 */ MCD_OPC_CheckField, 21, 1, 1, 218, 72, // Skip to: 40641 +/* 21991 */ MCD_OPC_Decode, 216, 4, 109, // Opcode: FMLSv2f32 +/* 21995 */ MCD_OPC_FilterValue, 2, 210, 72, // Skip to: 40641 +/* 21999 */ MCD_OPC_CheckPredicate, 0, 206, 72, // Skip to: 40641 +/* 22003 */ MCD_OPC_CheckField, 21, 1, 1, 200, 72, // Skip to: 40641 +/* 22009 */ MCD_OPC_Decode, 220, 4, 120, // Opcode: FMLSv4f32 +/* 22013 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 22056 +/* 22017 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22020 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22038 +/* 22024 */ MCD_OPC_CheckPredicate, 0, 181, 72, // Skip to: 40641 +/* 22028 */ MCD_OPC_CheckField, 21, 1, 1, 175, 72, // Skip to: 40641 +/* 22034 */ MCD_OPC_Decode, 212, 11, 85, // Opcode: SQDMULLv2i32_v2i64 +/* 22038 */ MCD_OPC_FilterValue, 2, 167, 72, // Skip to: 40641 +/* 22042 */ MCD_OPC_CheckPredicate, 0, 163, 72, // Skip to: 40641 +/* 22046 */ MCD_OPC_CheckField, 21, 1, 1, 157, 72, // Skip to: 40641 +/* 22052 */ MCD_OPC_Decode, 216, 11, 112, // Opcode: SQDMULLv4i32_v2i64 +/* 22056 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 22135 +/* 22060 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22063 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22081 +/* 22067 */ MCD_OPC_CheckPredicate, 0, 138, 72, // Skip to: 40641 +/* 22071 */ MCD_OPC_CheckField, 21, 1, 1, 132, 72, // Skip to: 40641 +/* 22077 */ MCD_OPC_Decode, 204, 5, 89, // Opcode: FSUBv2f32 +/* 22081 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22099 +/* 22085 */ MCD_OPC_CheckPredicate, 0, 120, 72, // Skip to: 40641 +/* 22089 */ MCD_OPC_CheckField, 21, 1, 1, 114, 72, // Skip to: 40641 +/* 22095 */ MCD_OPC_Decode, 182, 2, 89, // Opcode: FABDv2f32 +/* 22099 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22117 +/* 22103 */ MCD_OPC_CheckPredicate, 0, 102, 72, // Skip to: 40641 +/* 22107 */ MCD_OPC_CheckField, 21, 1, 1, 96, 72, // Skip to: 40641 +/* 22113 */ MCD_OPC_Decode, 206, 5, 112, // Opcode: FSUBv4f32 +/* 22117 */ MCD_OPC_FilterValue, 3, 88, 72, // Skip to: 40641 +/* 22121 */ MCD_OPC_CheckPredicate, 0, 84, 72, // Skip to: 40641 +/* 22125 */ MCD_OPC_CheckField, 21, 1, 1, 78, 72, // Skip to: 40641 +/* 22131 */ MCD_OPC_Decode, 184, 2, 112, // Opcode: FABDv4f32 +/* 22135 */ MCD_OPC_FilterValue, 54, 127, 0, // Skip to: 22266 +/* 22139 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22142 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 22173 +/* 22146 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22149 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22161 +/* 22153 */ MCD_OPC_CheckPredicate, 0, 52, 72, // Skip to: 40641 +/* 22157 */ MCD_OPC_Decode, 220, 2, 90, // Opcode: FCMEQv2i32rz +/* 22161 */ MCD_OPC_FilterValue, 33, 44, 72, // Skip to: 40641 +/* 22165 */ MCD_OPC_CheckPredicate, 0, 40, 72, // Skip to: 40641 +/* 22169 */ MCD_OPC_Decode, 142, 5, 90, // Opcode: FRECPEv2f32 +/* 22173 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22204 +/* 22177 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22180 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22192 +/* 22184 */ MCD_OPC_CheckPredicate, 0, 21, 72, // Skip to: 40641 +/* 22188 */ MCD_OPC_Decode, 246, 2, 90, // Opcode: FCMLEv2i32rz +/* 22192 */ MCD_OPC_FilterValue, 33, 13, 72, // Skip to: 40641 +/* 22196 */ MCD_OPC_CheckPredicate, 0, 9, 72, // Skip to: 40641 +/* 22200 */ MCD_OPC_Decode, 189, 5, 90, // Opcode: FRSQRTEv2f32 +/* 22204 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 22235 +/* 22208 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22211 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22223 +/* 22215 */ MCD_OPC_CheckPredicate, 0, 246, 71, // Skip to: 40641 +/* 22219 */ MCD_OPC_Decode, 223, 2, 117, // Opcode: FCMEQv4i32rz +/* 22223 */ MCD_OPC_FilterValue, 33, 238, 71, // Skip to: 40641 +/* 22227 */ MCD_OPC_CheckPredicate, 0, 234, 71, // Skip to: 40641 +/* 22231 */ MCD_OPC_Decode, 144, 5, 117, // Opcode: FRECPEv4f32 +/* 22235 */ MCD_OPC_FilterValue, 3, 226, 71, // Skip to: 40641 +/* 22239 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22242 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22254 +/* 22246 */ MCD_OPC_CheckPredicate, 0, 215, 71, // Skip to: 40641 +/* 22250 */ MCD_OPC_Decode, 248, 2, 117, // Opcode: FCMLEv4i32rz +/* 22254 */ MCD_OPC_FilterValue, 33, 207, 71, // Skip to: 40641 +/* 22258 */ MCD_OPC_CheckPredicate, 0, 203, 71, // Skip to: 40641 +/* 22262 */ MCD_OPC_Decode, 191, 5, 117, // Opcode: FRSQRTEv4f32 +/* 22266 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 22309 +/* 22270 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22273 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22291 +/* 22277 */ MCD_OPC_CheckPredicate, 0, 184, 71, // Skip to: 40641 +/* 22281 */ MCD_OPC_CheckField, 21, 1, 1, 178, 71, // Skip to: 40641 +/* 22287 */ MCD_OPC_Decode, 238, 2, 89, // Opcode: FCMGTv2f32 +/* 22291 */ MCD_OPC_FilterValue, 3, 170, 71, // Skip to: 40641 +/* 22295 */ MCD_OPC_CheckPredicate, 0, 166, 71, // Skip to: 40641 +/* 22299 */ MCD_OPC_CheckField, 21, 1, 1, 160, 71, // Skip to: 40641 +/* 22305 */ MCD_OPC_Decode, 242, 2, 112, // Opcode: FCMGTv4f32 +/* 22309 */ MCD_OPC_FilterValue, 58, 39, 0, // Skip to: 22352 +/* 22313 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22316 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22334 +/* 22320 */ MCD_OPC_CheckPredicate, 0, 141, 71, // Skip to: 40641 +/* 22324 */ MCD_OPC_CheckField, 16, 6, 32, 135, 71, // Skip to: 40641 +/* 22330 */ MCD_OPC_Decode, 251, 2, 90, // Opcode: FCMLTv2i32rz +/* 22334 */ MCD_OPC_FilterValue, 2, 127, 71, // Skip to: 40641 +/* 22338 */ MCD_OPC_CheckPredicate, 0, 123, 71, // Skip to: 40641 +/* 22342 */ MCD_OPC_CheckField, 16, 6, 32, 117, 71, // Skip to: 40641 +/* 22348 */ MCD_OPC_Decode, 253, 2, 117, // Opcode: FCMLTv4i32rz +/* 22352 */ MCD_OPC_FilterValue, 59, 39, 0, // Skip to: 22395 +/* 22356 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22359 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22377 +/* 22363 */ MCD_OPC_CheckPredicate, 0, 98, 71, // Skip to: 40641 +/* 22367 */ MCD_OPC_CheckField, 21, 1, 1, 92, 71, // Skip to: 40641 +/* 22373 */ MCD_OPC_Decode, 197, 2, 89, // Opcode: FACGTv2f32 +/* 22377 */ MCD_OPC_FilterValue, 3, 84, 71, // Skip to: 40641 +/* 22381 */ MCD_OPC_CheckPredicate, 0, 80, 71, // Skip to: 40641 +/* 22385 */ MCD_OPC_CheckField, 21, 1, 1, 74, 71, // Skip to: 40641 +/* 22391 */ MCD_OPC_Decode, 199, 2, 112, // Opcode: FACGTv4f32 +/* 22395 */ MCD_OPC_FilterValue, 61, 75, 0, // Skip to: 22474 +/* 22399 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22402 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22420 +/* 22406 */ MCD_OPC_CheckPredicate, 0, 55, 71, // Skip to: 40641 +/* 22410 */ MCD_OPC_CheckField, 21, 1, 1, 49, 71, // Skip to: 40641 +/* 22416 */ MCD_OPC_Decode, 203, 4, 89, // Opcode: FMINv2f32 +/* 22420 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22438 +/* 22424 */ MCD_OPC_CheckPredicate, 0, 37, 71, // Skip to: 40641 +/* 22428 */ MCD_OPC_CheckField, 21, 1, 1, 31, 71, // Skip to: 40641 +/* 22434 */ MCD_OPC_Decode, 196, 4, 89, // Opcode: FMINPv2f32 +/* 22438 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22456 +/* 22442 */ MCD_OPC_CheckPredicate, 0, 19, 71, // Skip to: 40641 +/* 22446 */ MCD_OPC_CheckField, 21, 1, 1, 13, 71, // Skip to: 40641 +/* 22452 */ MCD_OPC_Decode, 205, 4, 112, // Opcode: FMINv4f32 +/* 22456 */ MCD_OPC_FilterValue, 3, 5, 71, // Skip to: 40641 +/* 22460 */ MCD_OPC_CheckPredicate, 0, 1, 71, // Skip to: 40641 +/* 22464 */ MCD_OPC_CheckField, 21, 1, 1, 251, 70, // Skip to: 40641 +/* 22470 */ MCD_OPC_Decode, 200, 4, 112, // Opcode: FMINPv4f32 +/* 22474 */ MCD_OPC_FilterValue, 62, 114, 0, // Skip to: 22592 +/* 22478 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22481 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22499 +/* 22485 */ MCD_OPC_CheckPredicate, 0, 232, 70, // Skip to: 40641 +/* 22489 */ MCD_OPC_CheckField, 16, 6, 32, 226, 70, // Skip to: 40641 +/* 22495 */ MCD_OPC_Decode, 187, 2, 90, // Opcode: FABSv2f32 +/* 22499 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22530 +/* 22503 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22506 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22518 +/* 22510 */ MCD_OPC_CheckPredicate, 0, 207, 70, // Skip to: 40641 +/* 22514 */ MCD_OPC_Decode, 131, 5, 90, // Opcode: FNEGv2f32 +/* 22518 */ MCD_OPC_FilterValue, 33, 199, 70, // Skip to: 40641 +/* 22522 */ MCD_OPC_CheckPredicate, 0, 195, 70, // Skip to: 40641 +/* 22526 */ MCD_OPC_Decode, 199, 5, 90, // Opcode: FSQRTv2f32 +/* 22530 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22548 +/* 22534 */ MCD_OPC_CheckPredicate, 0, 183, 70, // Skip to: 40641 +/* 22538 */ MCD_OPC_CheckField, 16, 6, 32, 177, 70, // Skip to: 40641 +/* 22544 */ MCD_OPC_Decode, 189, 2, 117, // Opcode: FABSv4f32 +/* 22548 */ MCD_OPC_FilterValue, 3, 169, 70, // Skip to: 40641 +/* 22552 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 22555 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22567 +/* 22559 */ MCD_OPC_CheckPredicate, 0, 158, 70, // Skip to: 40641 +/* 22563 */ MCD_OPC_Decode, 133, 5, 117, // Opcode: FNEGv4f32 +/* 22567 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 22579 +/* 22571 */ MCD_OPC_CheckPredicate, 0, 146, 70, // Skip to: 40641 +/* 22575 */ MCD_OPC_Decode, 201, 5, 117, // Opcode: FSQRTv4f32 +/* 22579 */ MCD_OPC_FilterValue, 48, 138, 70, // Skip to: 40641 +/* 22583 */ MCD_OPC_CheckPredicate, 0, 134, 70, // Skip to: 40641 +/* 22587 */ MCD_OPC_Decode, 202, 4, 139, 1, // Opcode: FMINVv4i32v +/* 22592 */ MCD_OPC_FilterValue, 63, 125, 70, // Skip to: 40641 +/* 22596 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22599 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22617 +/* 22603 */ MCD_OPC_CheckPredicate, 0, 114, 70, // Skip to: 40641 +/* 22607 */ MCD_OPC_CheckField, 21, 1, 1, 108, 70, // Skip to: 40641 +/* 22613 */ MCD_OPC_Decode, 194, 5, 89, // Opcode: FRSQRTSv2f32 +/* 22617 */ MCD_OPC_FilterValue, 2, 100, 70, // Skip to: 40641 +/* 22621 */ MCD_OPC_CheckPredicate, 0, 96, 70, // Skip to: 40641 +/* 22625 */ MCD_OPC_CheckField, 21, 1, 1, 90, 70, // Skip to: 40641 +/* 22631 */ MCD_OPC_Decode, 196, 5, 112, // Opcode: FRSQRTSv4f32 +/* 22635 */ MCD_OPC_FilterValue, 11, 193, 5, // Skip to: 24112 +/* 22639 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 22642 */ MCD_OPC_FilterValue, 3, 39, 0, // Skip to: 22685 +/* 22646 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22649 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22667 +/* 22653 */ MCD_OPC_CheckPredicate, 0, 64, 70, // Skip to: 40641 +/* 22657 */ MCD_OPC_CheckField, 21, 1, 1, 58, 70, // Skip to: 40641 +/* 22663 */ MCD_OPC_Decode, 166, 11, 112, // Opcode: SQADDv2i64 +/* 22667 */ MCD_OPC_FilterValue, 3, 50, 70, // Skip to: 40641 +/* 22671 */ MCD_OPC_CheckPredicate, 0, 46, 70, // Skip to: 40641 +/* 22675 */ MCD_OPC_CheckField, 21, 1, 1, 40, 70, // Skip to: 40641 +/* 22681 */ MCD_OPC_Decode, 145, 17, 112, // Opcode: UQADDv2i64 +/* 22685 */ MCD_OPC_FilterValue, 6, 20, 0, // Skip to: 22709 +/* 22689 */ MCD_OPC_CheckPredicate, 0, 28, 70, // Skip to: 40641 +/* 22693 */ MCD_OPC_CheckField, 29, 3, 2, 22, 70, // Skip to: 40641 +/* 22699 */ MCD_OPC_CheckField, 21, 1, 0, 16, 70, // Skip to: 40641 +/* 22705 */ MCD_OPC_Decode, 182, 18, 112, // Opcode: UZP1v2i64 +/* 22709 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 22786 +/* 22713 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22716 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22734 +/* 22720 */ MCD_OPC_CheckPredicate, 0, 253, 69, // Skip to: 40641 +/* 22724 */ MCD_OPC_CheckField, 21, 1, 1, 247, 69, // Skip to: 40641 +/* 22730 */ MCD_OPC_Decode, 134, 9, 89, // Opcode: ORNv8i8 +/* 22734 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 22751 +/* 22738 */ MCD_OPC_CheckPredicate, 0, 235, 69, // Skip to: 40641 +/* 22742 */ MCD_OPC_CheckField, 21, 1, 1, 229, 69, // Skip to: 40641 +/* 22748 */ MCD_OPC_Decode, 121, 89, // Opcode: BIFv8i8 +/* 22751 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22769 +/* 22755 */ MCD_OPC_CheckPredicate, 0, 218, 69, // Skip to: 40641 +/* 22759 */ MCD_OPC_CheckField, 21, 1, 1, 212, 69, // Skip to: 40641 +/* 22765 */ MCD_OPC_Decode, 133, 9, 112, // Opcode: ORNv16i8 +/* 22769 */ MCD_OPC_FilterValue, 3, 204, 69, // Skip to: 40641 +/* 22773 */ MCD_OPC_CheckPredicate, 0, 200, 69, // Skip to: 40641 +/* 22777 */ MCD_OPC_CheckField, 21, 1, 1, 194, 69, // Skip to: 40641 +/* 22783 */ MCD_OPC_Decode, 120, 112, // Opcode: BIFv16i8 +/* 22786 */ MCD_OPC_FilterValue, 10, 20, 0, // Skip to: 22810 +/* 22790 */ MCD_OPC_CheckPredicate, 0, 183, 69, // Skip to: 40641 +/* 22794 */ MCD_OPC_CheckField, 29, 3, 2, 177, 69, // Skip to: 40641 +/* 22800 */ MCD_OPC_CheckField, 21, 1, 0, 171, 69, // Skip to: 40641 +/* 22806 */ MCD_OPC_Decode, 223, 15, 112, // Opcode: TRN1v2i64 +/* 22810 */ MCD_OPC_FilterValue, 11, 39, 0, // Skip to: 22853 +/* 22814 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22817 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22835 +/* 22821 */ MCD_OPC_CheckPredicate, 0, 152, 69, // Skip to: 40641 +/* 22825 */ MCD_OPC_CheckField, 21, 1, 1, 146, 69, // Skip to: 40641 +/* 22831 */ MCD_OPC_Decode, 200, 12, 112, // Opcode: SQSUBv2i64 +/* 22835 */ MCD_OPC_FilterValue, 3, 138, 69, // Skip to: 40641 +/* 22839 */ MCD_OPC_CheckPredicate, 0, 134, 69, // Skip to: 40641 +/* 22843 */ MCD_OPC_CheckField, 21, 1, 1, 128, 69, // Skip to: 40641 +/* 22849 */ MCD_OPC_Decode, 207, 17, 112, // Opcode: UQSUBv2i64 +/* 22853 */ MCD_OPC_FilterValue, 13, 39, 0, // Skip to: 22896 +/* 22857 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22860 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22878 +/* 22864 */ MCD_OPC_CheckPredicate, 0, 109, 69, // Skip to: 40641 +/* 22868 */ MCD_OPC_CheckField, 21, 1, 1, 103, 69, // Skip to: 40641 +/* 22874 */ MCD_OPC_Decode, 198, 1, 112, // Opcode: CMGTv2i64 +/* 22878 */ MCD_OPC_FilterValue, 3, 95, 69, // Skip to: 40641 +/* 22882 */ MCD_OPC_CheckPredicate, 0, 91, 69, // Skip to: 40641 +/* 22886 */ MCD_OPC_CheckField, 21, 1, 1, 85, 69, // Skip to: 40641 +/* 22892 */ MCD_OPC_Decode, 211, 1, 112, // Opcode: CMHIv2i64 +/* 22896 */ MCD_OPC_FilterValue, 14, 64, 0, // Skip to: 22964 +/* 22900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22903 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22921 +/* 22907 */ MCD_OPC_CheckPredicate, 0, 66, 69, // Skip to: 40641 +/* 22911 */ MCD_OPC_CheckField, 29, 3, 2, 60, 69, // Skip to: 40641 +/* 22917 */ MCD_OPC_Decode, 202, 18, 112, // Opcode: ZIP1v2i64 +/* 22921 */ MCD_OPC_FilterValue, 1, 52, 69, // Skip to: 40641 +/* 22925 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22928 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22946 +/* 22932 */ MCD_OPC_CheckPredicate, 0, 41, 69, // Skip to: 40641 +/* 22936 */ MCD_OPC_CheckField, 16, 5, 0, 35, 69, // Skip to: 40641 +/* 22942 */ MCD_OPC_Decode, 189, 15, 126, // Opcode: SUQADDv2i64 +/* 22946 */ MCD_OPC_FilterValue, 3, 27, 69, // Skip to: 40641 +/* 22950 */ MCD_OPC_CheckPredicate, 0, 23, 69, // Skip to: 40641 +/* 22954 */ MCD_OPC_CheckField, 16, 5, 0, 17, 69, // Skip to: 40641 +/* 22960 */ MCD_OPC_Decode, 155, 18, 126, // Opcode: USQADDv2i64 +/* 22964 */ MCD_OPC_FilterValue, 15, 39, 0, // Skip to: 23007 +/* 22968 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 22971 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22989 +/* 22975 */ MCD_OPC_CheckPredicate, 0, 254, 68, // Skip to: 40641 +/* 22979 */ MCD_OPC_CheckField, 21, 1, 1, 248, 68, // Skip to: 40641 +/* 22985 */ MCD_OPC_Decode, 182, 1, 112, // Opcode: CMGEv2i64 +/* 22989 */ MCD_OPC_FilterValue, 3, 240, 68, // Skip to: 40641 +/* 22993 */ MCD_OPC_CheckPredicate, 0, 236, 68, // Skip to: 40641 +/* 22997 */ MCD_OPC_CheckField, 21, 1, 1, 230, 68, // Skip to: 40641 +/* 23003 */ MCD_OPC_Decode, 219, 1, 112, // Opcode: CMHSv2i64 +/* 23007 */ MCD_OPC_FilterValue, 17, 39, 0, // Skip to: 23050 +/* 23011 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23014 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23032 +/* 23018 */ MCD_OPC_CheckPredicate, 0, 211, 68, // Skip to: 40641 +/* 23022 */ MCD_OPC_CheckField, 21, 1, 1, 205, 68, // Skip to: 40641 +/* 23028 */ MCD_OPC_Decode, 142, 13, 112, // Opcode: SSHLv2i64 +/* 23032 */ MCD_OPC_FilterValue, 3, 197, 68, // Skip to: 40641 +/* 23036 */ MCD_OPC_CheckPredicate, 0, 193, 68, // Skip to: 40641 +/* 23040 */ MCD_OPC_CheckField, 21, 1, 1, 187, 68, // Skip to: 40641 +/* 23046 */ MCD_OPC_Decode, 136, 18, 112, // Opcode: USHLv2i64 +/* 23050 */ MCD_OPC_FilterValue, 19, 39, 0, // Skip to: 23093 +/* 23054 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23057 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23075 +/* 23061 */ MCD_OPC_CheckPredicate, 0, 168, 68, // Skip to: 40641 +/* 23065 */ MCD_OPC_CheckField, 21, 1, 1, 162, 68, // Skip to: 40641 +/* 23071 */ MCD_OPC_Decode, 166, 12, 112, // Opcode: SQSHLv2i64 +/* 23075 */ MCD_OPC_FilterValue, 3, 154, 68, // Skip to: 40641 +/* 23079 */ MCD_OPC_CheckPredicate, 0, 150, 68, // Skip to: 40641 +/* 23083 */ MCD_OPC_CheckField, 21, 1, 1, 144, 68, // Skip to: 40641 +/* 23089 */ MCD_OPC_Decode, 182, 17, 112, // Opcode: UQSHLv2i64 +/* 23093 */ MCD_OPC_FilterValue, 21, 39, 0, // Skip to: 23136 +/* 23097 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23100 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23118 +/* 23104 */ MCD_OPC_CheckPredicate, 0, 125, 68, // Skip to: 40641 +/* 23108 */ MCD_OPC_CheckField, 21, 1, 1, 119, 68, // Skip to: 40641 +/* 23114 */ MCD_OPC_Decode, 240, 12, 112, // Opcode: SRSHLv2i64 +/* 23118 */ MCD_OPC_FilterValue, 3, 111, 68, // Skip to: 40641 +/* 23122 */ MCD_OPC_CheckPredicate, 0, 107, 68, // Skip to: 40641 +/* 23126 */ MCD_OPC_CheckField, 21, 1, 1, 101, 68, // Skip to: 40641 +/* 23132 */ MCD_OPC_Decode, 232, 17, 112, // Opcode: URSHLv2i64 +/* 23136 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 23160 +/* 23140 */ MCD_OPC_CheckPredicate, 0, 89, 68, // Skip to: 40641 +/* 23144 */ MCD_OPC_CheckField, 29, 3, 2, 83, 68, // Skip to: 40641 +/* 23150 */ MCD_OPC_CheckField, 21, 1, 0, 77, 68, // Skip to: 40641 +/* 23156 */ MCD_OPC_Decode, 189, 18, 112, // Opcode: UZP2v2i64 +/* 23160 */ MCD_OPC_FilterValue, 23, 39, 0, // Skip to: 23203 +/* 23164 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23167 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23185 +/* 23171 */ MCD_OPC_CheckPredicate, 0, 58, 68, // Skip to: 40641 +/* 23175 */ MCD_OPC_CheckField, 21, 1, 1, 52, 68, // Skip to: 40641 +/* 23181 */ MCD_OPC_Decode, 248, 11, 112, // Opcode: SQRSHLv2i64 +/* 23185 */ MCD_OPC_FilterValue, 3, 44, 68, // Skip to: 40641 +/* 23189 */ MCD_OPC_CheckPredicate, 0, 40, 68, // Skip to: 40641 +/* 23193 */ MCD_OPC_CheckField, 21, 1, 1, 34, 68, // Skip to: 40641 +/* 23199 */ MCD_OPC_Decode, 156, 17, 112, // Opcode: UQRSHLv2i64 +/* 23203 */ MCD_OPC_FilterValue, 26, 20, 0, // Skip to: 23227 +/* 23207 */ MCD_OPC_CheckPredicate, 0, 22, 68, // Skip to: 40641 +/* 23211 */ MCD_OPC_CheckField, 29, 3, 2, 16, 68, // Skip to: 40641 +/* 23217 */ MCD_OPC_CheckField, 21, 1, 0, 10, 68, // Skip to: 40641 +/* 23223 */ MCD_OPC_Decode, 230, 15, 112, // Opcode: TRN2v2i64 +/* 23227 */ MCD_OPC_FilterValue, 30, 64, 0, // Skip to: 23295 +/* 23231 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 23234 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23252 +/* 23238 */ MCD_OPC_CheckPredicate, 0, 247, 67, // Skip to: 40641 +/* 23242 */ MCD_OPC_CheckField, 29, 3, 2, 241, 67, // Skip to: 40641 +/* 23248 */ MCD_OPC_Decode, 209, 18, 112, // Opcode: ZIP2v2i64 +/* 23252 */ MCD_OPC_FilterValue, 1, 233, 67, // Skip to: 40641 +/* 23256 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23259 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23277 +/* 23263 */ MCD_OPC_CheckPredicate, 0, 222, 67, // Skip to: 40641 +/* 23267 */ MCD_OPC_CheckField, 16, 5, 0, 216, 67, // Skip to: 40641 +/* 23273 */ MCD_OPC_Decode, 155, 11, 117, // Opcode: SQABSv2i64 +/* 23277 */ MCD_OPC_FilterValue, 3, 208, 67, // Skip to: 40641 +/* 23281 */ MCD_OPC_CheckPredicate, 0, 204, 67, // Skip to: 40641 +/* 23285 */ MCD_OPC_CheckField, 16, 5, 0, 198, 67, // Skip to: 40641 +/* 23291 */ MCD_OPC_Decode, 225, 11, 117, // Opcode: SQNEGv2i64 +/* 23295 */ MCD_OPC_FilterValue, 33, 38, 0, // Skip to: 23337 +/* 23299 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23302 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 23319 +/* 23306 */ MCD_OPC_CheckPredicate, 0, 179, 67, // Skip to: 40641 +/* 23310 */ MCD_OPC_CheckField, 21, 1, 1, 173, 67, // Skip to: 40641 +/* 23316 */ MCD_OPC_Decode, 74, 112, // Opcode: ADDv2i64 +/* 23319 */ MCD_OPC_FilterValue, 3, 166, 67, // Skip to: 40641 +/* 23323 */ MCD_OPC_CheckPredicate, 0, 162, 67, // Skip to: 40641 +/* 23327 */ MCD_OPC_CheckField, 21, 1, 1, 156, 67, // Skip to: 40641 +/* 23333 */ MCD_OPC_Decode, 178, 15, 112, // Opcode: SUBv2i64 +/* 23337 */ MCD_OPC_FilterValue, 34, 52, 0, // Skip to: 23393 +/* 23341 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 23344 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23375 +/* 23348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23351 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23363 +/* 23355 */ MCD_OPC_CheckPredicate, 0, 130, 67, // Skip to: 40641 +/* 23359 */ MCD_OPC_Decode, 199, 1, 117, // Opcode: CMGTv2i64rz +/* 23363 */ MCD_OPC_FilterValue, 3, 122, 67, // Skip to: 40641 +/* 23367 */ MCD_OPC_CheckPredicate, 0, 118, 67, // Skip to: 40641 +/* 23371 */ MCD_OPC_Decode, 183, 1, 117, // Opcode: CMGEv2i64rz +/* 23375 */ MCD_OPC_FilterValue, 33, 110, 67, // Skip to: 40641 +/* 23379 */ MCD_OPC_CheckPredicate, 0, 106, 67, // Skip to: 40641 +/* 23383 */ MCD_OPC_CheckField, 29, 3, 2, 100, 67, // Skip to: 40641 +/* 23389 */ MCD_OPC_Decode, 175, 5, 117, // Opcode: FRINTPv2f64 +/* 23393 */ MCD_OPC_FilterValue, 35, 39, 0, // Skip to: 23436 +/* 23397 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23400 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23418 +/* 23404 */ MCD_OPC_CheckPredicate, 0, 81, 67, // Skip to: 40641 +/* 23408 */ MCD_OPC_CheckField, 21, 1, 1, 75, 67, // Skip to: 40641 +/* 23414 */ MCD_OPC_Decode, 243, 1, 112, // Opcode: CMTSTv2i64 +/* 23418 */ MCD_OPC_FilterValue, 3, 67, 67, // Skip to: 40641 +/* 23422 */ MCD_OPC_CheckPredicate, 0, 63, 67, // Skip to: 40641 +/* 23426 */ MCD_OPC_CheckField, 21, 1, 1, 57, 67, // Skip to: 40641 +/* 23432 */ MCD_OPC_Decode, 166, 1, 112, // Opcode: CMEQv2i64 +/* 23436 */ MCD_OPC_FilterValue, 38, 65, 0, // Skip to: 23505 +/* 23440 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 23443 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23474 +/* 23447 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23450 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23462 +/* 23454 */ MCD_OPC_CheckPredicate, 0, 31, 67, // Skip to: 40641 +/* 23458 */ MCD_OPC_Decode, 167, 1, 117, // Opcode: CMEQv2i64rz +/* 23462 */ MCD_OPC_FilterValue, 3, 23, 67, // Skip to: 40641 +/* 23466 */ MCD_OPC_CheckPredicate, 0, 19, 67, // Skip to: 40641 +/* 23470 */ MCD_OPC_Decode, 227, 1, 117, // Opcode: CMLEv2i64rz +/* 23474 */ MCD_OPC_FilterValue, 33, 11, 67, // Skip to: 40641 +/* 23478 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23481 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23493 +/* 23485 */ MCD_OPC_CheckPredicate, 0, 0, 67, // Skip to: 40641 +/* 23489 */ MCD_OPC_Decode, 185, 5, 117, // Opcode: FRINTZv2f64 +/* 23493 */ MCD_OPC_FilterValue, 3, 248, 66, // Skip to: 40641 +/* 23497 */ MCD_OPC_CheckPredicate, 0, 244, 66, // Skip to: 40641 +/* 23501 */ MCD_OPC_Decode, 160, 5, 117, // Opcode: FRINTIv2f64 +/* 23505 */ MCD_OPC_FilterValue, 42, 52, 0, // Skip to: 23561 +/* 23509 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 23512 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 23530 +/* 23516 */ MCD_OPC_CheckPredicate, 0, 225, 66, // Skip to: 40641 +/* 23520 */ MCD_OPC_CheckField, 29, 3, 2, 219, 66, // Skip to: 40641 +/* 23526 */ MCD_OPC_Decode, 235, 1, 117, // Opcode: CMLTv2i64rz +/* 23530 */ MCD_OPC_FilterValue, 33, 211, 66, // Skip to: 40641 +/* 23534 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23537 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23549 +/* 23541 */ MCD_OPC_CheckPredicate, 0, 200, 66, // Skip to: 40641 +/* 23545 */ MCD_OPC_Decode, 209, 3, 117, // Opcode: FCVTPSv2f64 +/* 23549 */ MCD_OPC_FilterValue, 3, 192, 66, // Skip to: 40641 +/* 23553 */ MCD_OPC_CheckPredicate, 0, 188, 66, // Skip to: 40641 +/* 23557 */ MCD_OPC_Decode, 218, 3, 117, // Opcode: FCVTPUv2f64 +/* 23561 */ MCD_OPC_FilterValue, 46, 64, 0, // Skip to: 23629 +/* 23565 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 23568 */ MCD_OPC_FilterValue, 32, 26, 0, // Skip to: 23598 +/* 23572 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23575 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 23586 +/* 23579 */ MCD_OPC_CheckPredicate, 0, 162, 66, // Skip to: 40641 +/* 23583 */ MCD_OPC_Decode, 25, 117, // Opcode: ABSv2i64 +/* 23586 */ MCD_OPC_FilterValue, 3, 155, 66, // Skip to: 40641 +/* 23590 */ MCD_OPC_CheckPredicate, 0, 151, 66, // Skip to: 40641 +/* 23594 */ MCD_OPC_Decode, 250, 8, 117, // Opcode: NEGv2i64 +/* 23598 */ MCD_OPC_FilterValue, 33, 143, 66, // Skip to: 40641 +/* 23602 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23605 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23617 +/* 23609 */ MCD_OPC_CheckPredicate, 0, 132, 66, // Skip to: 40641 +/* 23613 */ MCD_OPC_Decode, 249, 3, 117, // Opcode: FCVTZSv2f64 +/* 23617 */ MCD_OPC_FilterValue, 3, 124, 66, // Skip to: 40641 +/* 23621 */ MCD_OPC_CheckPredicate, 0, 120, 66, // Skip to: 40641 +/* 23625 */ MCD_OPC_Decode, 150, 4, 117, // Opcode: FCVTZUv2f64 +/* 23629 */ MCD_OPC_FilterValue, 47, 19, 0, // Skip to: 23652 +/* 23633 */ MCD_OPC_CheckPredicate, 0, 108, 66, // Skip to: 40641 +/* 23637 */ MCD_OPC_CheckField, 29, 3, 2, 102, 66, // Skip to: 40641 +/* 23643 */ MCD_OPC_CheckField, 21, 1, 1, 96, 66, // Skip to: 40641 +/* 23649 */ MCD_OPC_Decode, 42, 112, // Opcode: ADDPv2i64 +/* 23652 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 23695 +/* 23656 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23659 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23677 +/* 23663 */ MCD_OPC_CheckPredicate, 0, 78, 66, // Skip to: 40641 +/* 23667 */ MCD_OPC_CheckField, 21, 1, 1, 72, 66, // Skip to: 40641 +/* 23673 */ MCD_OPC_Decode, 194, 4, 112, // Opcode: FMINNMv2f64 +/* 23677 */ MCD_OPC_FilterValue, 3, 64, 66, // Skip to: 40641 +/* 23681 */ MCD_OPC_CheckPredicate, 0, 60, 66, // Skip to: 40641 +/* 23685 */ MCD_OPC_CheckField, 21, 1, 1, 54, 66, // Skip to: 40641 +/* 23691 */ MCD_OPC_Decode, 187, 4, 112, // Opcode: FMINNMPv2f64 +/* 23695 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 23738 +/* 23699 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23702 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23720 +/* 23706 */ MCD_OPC_CheckPredicate, 0, 35, 66, // Skip to: 40641 +/* 23710 */ MCD_OPC_CheckField, 16, 6, 32, 29, 66, // Skip to: 40641 +/* 23716 */ MCD_OPC_Decode, 241, 2, 117, // Opcode: FCMGTv2i64rz +/* 23720 */ MCD_OPC_FilterValue, 3, 21, 66, // Skip to: 40641 +/* 23724 */ MCD_OPC_CheckPredicate, 0, 17, 66, // Skip to: 40641 +/* 23728 */ MCD_OPC_CheckField, 16, 6, 32, 11, 66, // Skip to: 40641 +/* 23734 */ MCD_OPC_Decode, 231, 2, 117, // Opcode: FCMGEv2i64rz +/* 23738 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 23762 +/* 23742 */ MCD_OPC_CheckPredicate, 0, 255, 65, // Skip to: 40641 +/* 23746 */ MCD_OPC_CheckField, 29, 3, 2, 249, 65, // Skip to: 40641 +/* 23752 */ MCD_OPC_CheckField, 21, 1, 1, 243, 65, // Skip to: 40641 +/* 23758 */ MCD_OPC_Decode, 217, 4, 120, // Opcode: FMLSv2f64 +/* 23762 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 23805 +/* 23766 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23769 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23787 +/* 23773 */ MCD_OPC_CheckPredicate, 0, 224, 65, // Skip to: 40641 +/* 23777 */ MCD_OPC_CheckField, 21, 1, 1, 218, 65, // Skip to: 40641 +/* 23783 */ MCD_OPC_Decode, 205, 5, 112, // Opcode: FSUBv2f64 +/* 23787 */ MCD_OPC_FilterValue, 3, 210, 65, // Skip to: 40641 +/* 23791 */ MCD_OPC_CheckPredicate, 0, 206, 65, // Skip to: 40641 +/* 23795 */ MCD_OPC_CheckField, 21, 1, 1, 200, 65, // Skip to: 40641 +/* 23801 */ MCD_OPC_Decode, 183, 2, 112, // Opcode: FABDv2f64 +/* 23805 */ MCD_OPC_FilterValue, 54, 65, 0, // Skip to: 23874 +/* 23809 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 23812 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23843 +/* 23816 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23819 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23831 +/* 23823 */ MCD_OPC_CheckPredicate, 0, 174, 65, // Skip to: 40641 +/* 23827 */ MCD_OPC_Decode, 221, 2, 117, // Opcode: FCMEQv2i64rz +/* 23831 */ MCD_OPC_FilterValue, 3, 166, 65, // Skip to: 40641 +/* 23835 */ MCD_OPC_CheckPredicate, 0, 162, 65, // Skip to: 40641 +/* 23839 */ MCD_OPC_Decode, 247, 2, 117, // Opcode: FCMLEv2i64rz +/* 23843 */ MCD_OPC_FilterValue, 33, 154, 65, // Skip to: 40641 +/* 23847 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23862 +/* 23854 */ MCD_OPC_CheckPredicate, 0, 143, 65, // Skip to: 40641 +/* 23858 */ MCD_OPC_Decode, 143, 5, 117, // Opcode: FRECPEv2f64 +/* 23862 */ MCD_OPC_FilterValue, 3, 135, 65, // Skip to: 40641 +/* 23866 */ MCD_OPC_CheckPredicate, 0, 131, 65, // Skip to: 40641 +/* 23870 */ MCD_OPC_Decode, 190, 5, 117, // Opcode: FRSQRTEv2f64 +/* 23874 */ MCD_OPC_FilterValue, 56, 39, 0, // Skip to: 23917 +/* 23878 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23881 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23899 +/* 23885 */ MCD_OPC_CheckPredicate, 1, 112, 65, // Skip to: 40641 +/* 23889 */ MCD_OPC_CheckField, 21, 1, 1, 106, 65, // Skip to: 40641 +/* 23895 */ MCD_OPC_Decode, 148, 9, 85, // Opcode: PMULLv1i64 +/* 23899 */ MCD_OPC_FilterValue, 2, 98, 65, // Skip to: 40641 +/* 23903 */ MCD_OPC_CheckPredicate, 1, 94, 65, // Skip to: 40641 +/* 23907 */ MCD_OPC_CheckField, 21, 1, 1, 88, 65, // Skip to: 40641 +/* 23913 */ MCD_OPC_Decode, 149, 9, 112, // Opcode: PMULLv2i64 +/* 23917 */ MCD_OPC_FilterValue, 57, 20, 0, // Skip to: 23941 +/* 23921 */ MCD_OPC_CheckPredicate, 0, 76, 65, // Skip to: 40641 +/* 23925 */ MCD_OPC_CheckField, 29, 3, 3, 70, 65, // Skip to: 40641 +/* 23931 */ MCD_OPC_CheckField, 21, 1, 1, 64, 65, // Skip to: 40641 +/* 23937 */ MCD_OPC_Decode, 239, 2, 112, // Opcode: FCMGTv2f64 +/* 23941 */ MCD_OPC_FilterValue, 58, 20, 0, // Skip to: 23965 +/* 23945 */ MCD_OPC_CheckPredicate, 0, 52, 65, // Skip to: 40641 +/* 23949 */ MCD_OPC_CheckField, 29, 3, 2, 46, 65, // Skip to: 40641 +/* 23955 */ MCD_OPC_CheckField, 16, 6, 32, 40, 65, // Skip to: 40641 +/* 23961 */ MCD_OPC_Decode, 252, 2, 117, // Opcode: FCMLTv2i64rz +/* 23965 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 23989 +/* 23969 */ MCD_OPC_CheckPredicate, 0, 28, 65, // Skip to: 40641 +/* 23973 */ MCD_OPC_CheckField, 29, 3, 3, 22, 65, // Skip to: 40641 +/* 23979 */ MCD_OPC_CheckField, 21, 1, 1, 16, 65, // Skip to: 40641 +/* 23985 */ MCD_OPC_Decode, 198, 2, 112, // Opcode: FACGTv2f64 +/* 23989 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 24032 +/* 23993 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 23996 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 24014 +/* 24000 */ MCD_OPC_CheckPredicate, 0, 253, 64, // Skip to: 40641 +/* 24004 */ MCD_OPC_CheckField, 21, 1, 1, 247, 64, // Skip to: 40641 +/* 24010 */ MCD_OPC_Decode, 204, 4, 112, // Opcode: FMINv2f64 +/* 24014 */ MCD_OPC_FilterValue, 3, 239, 64, // Skip to: 40641 +/* 24018 */ MCD_OPC_CheckPredicate, 0, 235, 64, // Skip to: 40641 +/* 24022 */ MCD_OPC_CheckField, 21, 1, 1, 229, 64, // Skip to: 40641 +/* 24028 */ MCD_OPC_Decode, 197, 4, 112, // Opcode: FMINPv2f64 +/* 24032 */ MCD_OPC_FilterValue, 62, 52, 0, // Skip to: 24088 +/* 24036 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 24039 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 24070 +/* 24043 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 24046 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 24058 +/* 24050 */ MCD_OPC_CheckPredicate, 0, 203, 64, // Skip to: 40641 +/* 24054 */ MCD_OPC_Decode, 188, 2, 117, // Opcode: FABSv2f64 +/* 24058 */ MCD_OPC_FilterValue, 3, 195, 64, // Skip to: 40641 +/* 24062 */ MCD_OPC_CheckPredicate, 0, 191, 64, // Skip to: 40641 +/* 24066 */ MCD_OPC_Decode, 132, 5, 117, // Opcode: FNEGv2f64 +/* 24070 */ MCD_OPC_FilterValue, 33, 183, 64, // Skip to: 40641 +/* 24074 */ MCD_OPC_CheckPredicate, 0, 179, 64, // Skip to: 40641 +/* 24078 */ MCD_OPC_CheckField, 29, 3, 3, 173, 64, // Skip to: 40641 +/* 24084 */ MCD_OPC_Decode, 200, 5, 117, // Opcode: FSQRTv2f64 +/* 24088 */ MCD_OPC_FilterValue, 63, 165, 64, // Skip to: 40641 +/* 24092 */ MCD_OPC_CheckPredicate, 0, 161, 64, // Skip to: 40641 +/* 24096 */ MCD_OPC_CheckField, 29, 3, 2, 155, 64, // Skip to: 40641 +/* 24102 */ MCD_OPC_CheckField, 21, 1, 1, 149, 64, // Skip to: 40641 +/* 24108 */ MCD_OPC_Decode, 195, 5, 112, // Opcode: FRSQRTSv2f64 +/* 24112 */ MCD_OPC_FilterValue, 12, 165, 13, // Skip to: 27609 +/* 24116 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 24119 */ MCD_OPC_FilterValue, 0, 66, 3, // Skip to: 24957 +/* 24123 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 24126 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 24813 +/* 24130 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 24133 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 24484 +/* 24137 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 24140 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24273 +/* 24144 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24147 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24240 +/* 24151 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24154 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24207 +/* 24158 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 24161 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24174 +/* 24165 */ MCD_OPC_CheckPredicate, 0, 88, 64, // Skip to: 40641 +/* 24169 */ MCD_OPC_Decode, 205, 8, 145, 1, // Opcode: MOVIv2i32 +/* 24174 */ MCD_OPC_FilterValue, 1, 79, 64, // Skip to: 40641 +/* 24178 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24194 +/* 24185 */ MCD_OPC_CheckPredicate, 0, 68, 64, // Skip to: 40641 +/* 24189 */ MCD_OPC_Decode, 154, 13, 146, 1, // Opcode: SSHRv8i8_shift +/* 24194 */ MCD_OPC_FilterValue, 1, 59, 64, // Skip to: 40641 +/* 24198 */ MCD_OPC_CheckPredicate, 0, 55, 64, // Skip to: 40641 +/* 24202 */ MCD_OPC_Decode, 252, 12, 146, 1, // Opcode: SRSHRv8i8_shift +/* 24207 */ MCD_OPC_FilterValue, 1, 46, 64, // Skip to: 40641 +/* 24211 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24214 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24227 +/* 24218 */ MCD_OPC_CheckPredicate, 0, 35, 64, // Skip to: 40641 +/* 24222 */ MCD_OPC_Decode, 151, 13, 147, 1, // Opcode: SSHRv4i16_shift +/* 24227 */ MCD_OPC_FilterValue, 1, 26, 64, // Skip to: 40641 +/* 24231 */ MCD_OPC_CheckPredicate, 0, 22, 64, // Skip to: 40641 +/* 24235 */ MCD_OPC_Decode, 249, 12, 147, 1, // Opcode: SRSHRv4i16_shift +/* 24240 */ MCD_OPC_FilterValue, 1, 13, 64, // Skip to: 40641 +/* 24244 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24247 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24260 +/* 24251 */ MCD_OPC_CheckPredicate, 0, 2, 64, // Skip to: 40641 +/* 24255 */ MCD_OPC_Decode, 149, 13, 148, 1, // Opcode: SSHRv2i32_shift +/* 24260 */ MCD_OPC_FilterValue, 1, 249, 63, // Skip to: 40641 +/* 24264 */ MCD_OPC_CheckPredicate, 0, 245, 63, // Skip to: 40641 +/* 24268 */ MCD_OPC_Decode, 247, 12, 148, 1, // Opcode: SRSHRv2i32_shift +/* 24273 */ MCD_OPC_FilterValue, 1, 236, 63, // Skip to: 40641 +/* 24277 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24280 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 24425 +/* 24284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24287 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 24366 +/* 24291 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 24294 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24307 +/* 24298 */ MCD_OPC_CheckPredicate, 0, 211, 63, // Skip to: 40641 +/* 24302 */ MCD_OPC_Decode, 142, 9, 149, 1, // Opcode: ORRv2i32 +/* 24307 */ MCD_OPC_FilterValue, 1, 202, 63, // Skip to: 40641 +/* 24311 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24314 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24327 +/* 24318 */ MCD_OPC_CheckPredicate, 0, 191, 63, // Skip to: 40641 +/* 24322 */ MCD_OPC_Decode, 162, 13, 150, 1, // Opcode: SSRAv8i8_shift +/* 24327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24340 +/* 24331 */ MCD_OPC_CheckPredicate, 0, 178, 63, // Skip to: 40641 +/* 24335 */ MCD_OPC_Decode, 132, 13, 150, 1, // Opcode: SRSRAv8i8_shift +/* 24340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24353 +/* 24344 */ MCD_OPC_CheckPredicate, 0, 165, 63, // Skip to: 40641 +/* 24348 */ MCD_OPC_Decode, 183, 10, 151, 1, // Opcode: SHLv8i8_shift +/* 24353 */ MCD_OPC_FilterValue, 3, 156, 63, // Skip to: 40641 +/* 24357 */ MCD_OPC_CheckPredicate, 0, 152, 63, // Skip to: 40641 +/* 24361 */ MCD_OPC_Decode, 175, 12, 151, 1, // Opcode: SQSHLv8i8_shift +/* 24366 */ MCD_OPC_FilterValue, 1, 143, 63, // Skip to: 40641 +/* 24370 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24373 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24386 +/* 24377 */ MCD_OPC_CheckPredicate, 0, 132, 63, // Skip to: 40641 +/* 24381 */ MCD_OPC_Decode, 159, 13, 152, 1, // Opcode: SSRAv4i16_shift +/* 24386 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24399 +/* 24390 */ MCD_OPC_CheckPredicate, 0, 119, 63, // Skip to: 40641 +/* 24394 */ MCD_OPC_Decode, 129, 13, 152, 1, // Opcode: SRSRAv4i16_shift +/* 24399 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24412 +/* 24403 */ MCD_OPC_CheckPredicate, 0, 106, 63, // Skip to: 40641 +/* 24407 */ MCD_OPC_Decode, 180, 10, 153, 1, // Opcode: SHLv4i16_shift +/* 24412 */ MCD_OPC_FilterValue, 3, 97, 63, // Skip to: 40641 +/* 24416 */ MCD_OPC_CheckPredicate, 0, 93, 63, // Skip to: 40641 +/* 24420 */ MCD_OPC_Decode, 169, 12, 153, 1, // Opcode: SQSHLv4i16_shift +/* 24425 */ MCD_OPC_FilterValue, 1, 84, 63, // Skip to: 40641 +/* 24429 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 24432 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24445 +/* 24436 */ MCD_OPC_CheckPredicate, 0, 73, 63, // Skip to: 40641 +/* 24440 */ MCD_OPC_Decode, 157, 13, 154, 1, // Opcode: SSRAv2i32_shift +/* 24445 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24458 +/* 24449 */ MCD_OPC_CheckPredicate, 0, 60, 63, // Skip to: 40641 +/* 24453 */ MCD_OPC_Decode, 255, 12, 154, 1, // Opcode: SRSRAv2i32_shift +/* 24458 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24471 +/* 24462 */ MCD_OPC_CheckPredicate, 0, 47, 63, // Skip to: 40641 +/* 24466 */ MCD_OPC_Decode, 178, 10, 155, 1, // Opcode: SHLv2i32_shift +/* 24471 */ MCD_OPC_FilterValue, 3, 38, 63, // Skip to: 40641 +/* 24475 */ MCD_OPC_CheckPredicate, 0, 34, 63, // Skip to: 40641 +/* 24479 */ MCD_OPC_Decode, 165, 12, 155, 1, // Opcode: SQSHLv2i32_shift +/* 24484 */ MCD_OPC_FilterValue, 1, 25, 63, // Skip to: 40641 +/* 24488 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 24491 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 24722 +/* 24495 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 24498 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24631 +/* 24502 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24505 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24598 +/* 24509 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24512 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24565 +/* 24516 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 24519 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24532 +/* 24523 */ MCD_OPC_CheckPredicate, 0, 242, 62, // Skip to: 40641 +/* 24527 */ MCD_OPC_Decode, 207, 8, 145, 1, // Opcode: MOVIv4i16 +/* 24532 */ MCD_OPC_FilterValue, 1, 233, 62, // Skip to: 40641 +/* 24536 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 24539 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24552 +/* 24543 */ MCD_OPC_CheckPredicate, 0, 222, 62, // Skip to: 40641 +/* 24547 */ MCD_OPC_Decode, 189, 10, 156, 1, // Opcode: SHRNv8i8_shift +/* 24552 */ MCD_OPC_FilterValue, 1, 213, 62, // Skip to: 40641 +/* 24556 */ MCD_OPC_CheckPredicate, 0, 209, 62, // Skip to: 40641 +/* 24560 */ MCD_OPC_Decode, 138, 13, 157, 1, // Opcode: SSHLLv8i8_shift +/* 24565 */ MCD_OPC_FilterValue, 1, 200, 62, // Skip to: 40641 +/* 24569 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 24572 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24585 +/* 24576 */ MCD_OPC_CheckPredicate, 0, 189, 62, // Skip to: 40641 +/* 24580 */ MCD_OPC_Decode, 186, 10, 158, 1, // Opcode: SHRNv4i16_shift +/* 24585 */ MCD_OPC_FilterValue, 1, 180, 62, // Skip to: 40641 +/* 24589 */ MCD_OPC_CheckPredicate, 0, 176, 62, // Skip to: 40641 +/* 24593 */ MCD_OPC_Decode, 135, 13, 159, 1, // Opcode: SSHLLv4i16_shift +/* 24598 */ MCD_OPC_FilterValue, 1, 167, 62, // Skip to: 40641 +/* 24602 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 24605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24618 +/* 24609 */ MCD_OPC_CheckPredicate, 0, 156, 62, // Skip to: 40641 +/* 24613 */ MCD_OPC_Decode, 185, 10, 160, 1, // Opcode: SHRNv2i32_shift +/* 24618 */ MCD_OPC_FilterValue, 1, 147, 62, // Skip to: 40641 +/* 24622 */ MCD_OPC_CheckPredicate, 0, 143, 62, // Skip to: 40641 +/* 24626 */ MCD_OPC_Decode, 134, 13, 161, 1, // Opcode: SSHLLv2i32_shift +/* 24631 */ MCD_OPC_FilterValue, 1, 134, 62, // Skip to: 40641 +/* 24635 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24638 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 24703 +/* 24642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24645 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24684 +/* 24649 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 24652 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24665 +/* 24656 */ MCD_OPC_CheckPredicate, 0, 109, 62, // Skip to: 40641 +/* 24660 */ MCD_OPC_Decode, 143, 9, 149, 1, // Opcode: ORRv4i16 +/* 24665 */ MCD_OPC_FilterValue, 1, 100, 62, // Skip to: 40641 +/* 24669 */ MCD_OPC_CheckPredicate, 0, 96, 62, // Skip to: 40641 +/* 24673 */ MCD_OPC_CheckField, 13, 1, 0, 90, 62, // Skip to: 40641 +/* 24679 */ MCD_OPC_Decode, 184, 12, 156, 1, // Opcode: SQSHRNv8i8_shift +/* 24684 */ MCD_OPC_FilterValue, 1, 81, 62, // Skip to: 40641 +/* 24688 */ MCD_OPC_CheckPredicate, 0, 77, 62, // Skip to: 40641 +/* 24692 */ MCD_OPC_CheckField, 13, 1, 0, 71, 62, // Skip to: 40641 +/* 24698 */ MCD_OPC_Decode, 181, 12, 158, 1, // Opcode: SQSHRNv4i16_shift +/* 24703 */ MCD_OPC_FilterValue, 1, 62, 62, // Skip to: 40641 +/* 24707 */ MCD_OPC_CheckPredicate, 0, 58, 62, // Skip to: 40641 +/* 24711 */ MCD_OPC_CheckField, 13, 1, 0, 52, 62, // Skip to: 40641 +/* 24717 */ MCD_OPC_Decode, 180, 12, 160, 1, // Opcode: SQSHRNv2i32_shift +/* 24722 */ MCD_OPC_FilterValue, 1, 43, 62, // Skip to: 40641 +/* 24726 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 24729 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24748 +/* 24733 */ MCD_OPC_CheckPredicate, 0, 32, 62, // Skip to: 40641 +/* 24737 */ MCD_OPC_CheckField, 19, 3, 0, 26, 62, // Skip to: 40641 +/* 24743 */ MCD_OPC_Decode, 206, 8, 145, 1, // Opcode: MOVIv2s_msl +/* 24748 */ MCD_OPC_FilterValue, 1, 17, 62, // Skip to: 40641 +/* 24752 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 24755 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24794 +/* 24759 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24762 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24781 +/* 24766 */ MCD_OPC_CheckPredicate, 0, 255, 61, // Skip to: 40641 +/* 24770 */ MCD_OPC_CheckField, 19, 2, 0, 249, 61, // Skip to: 40641 +/* 24776 */ MCD_OPC_Decode, 210, 8, 145, 1, // Opcode: MOVIv8b_ns +/* 24781 */ MCD_OPC_FilterValue, 1, 240, 61, // Skip to: 40641 +/* 24785 */ MCD_OPC_CheckPredicate, 0, 236, 61, // Skip to: 40641 +/* 24789 */ MCD_OPC_Decode, 146, 10, 148, 1, // Opcode: SCVTFv2i32_shift +/* 24794 */ MCD_OPC_FilterValue, 1, 227, 61, // Skip to: 40641 +/* 24798 */ MCD_OPC_CheckPredicate, 0, 223, 61, // Skip to: 40641 +/* 24802 */ MCD_OPC_CheckField, 19, 3, 0, 217, 61, // Skip to: 40641 +/* 24808 */ MCD_OPC_Decode, 232, 4, 145, 1, // Opcode: FMOVv2f32_ns +/* 24813 */ MCD_OPC_FilterValue, 3, 208, 61, // Skip to: 40641 +/* 24817 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 24820 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 24879 +/* 24824 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24827 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24866 +/* 24831 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24834 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24853 +/* 24838 */ MCD_OPC_CheckPredicate, 0, 183, 61, // Skip to: 40641 +/* 24842 */ MCD_OPC_CheckField, 19, 1, 1, 177, 61, // Skip to: 40641 +/* 24848 */ MCD_OPC_Decode, 194, 9, 156, 1, // Opcode: RSHRNv8i8_shift +/* 24853 */ MCD_OPC_FilterValue, 1, 168, 61, // Skip to: 40641 +/* 24857 */ MCD_OPC_CheckPredicate, 0, 164, 61, // Skip to: 40641 +/* 24861 */ MCD_OPC_Decode, 191, 9, 158, 1, // Opcode: RSHRNv4i16_shift +/* 24866 */ MCD_OPC_FilterValue, 1, 155, 61, // Skip to: 40641 +/* 24870 */ MCD_OPC_CheckPredicate, 0, 151, 61, // Skip to: 40641 +/* 24874 */ MCD_OPC_Decode, 190, 9, 160, 1, // Opcode: RSHRNv2i32_shift +/* 24879 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 24938 +/* 24883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24886 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24925 +/* 24890 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24893 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24912 +/* 24897 */ MCD_OPC_CheckPredicate, 0, 124, 61, // Skip to: 40641 +/* 24901 */ MCD_OPC_CheckField, 19, 1, 1, 118, 61, // Skip to: 40641 +/* 24907 */ MCD_OPC_Decode, 133, 12, 156, 1, // Opcode: SQRSHRNv8i8_shift +/* 24912 */ MCD_OPC_FilterValue, 1, 109, 61, // Skip to: 40641 +/* 24916 */ MCD_OPC_CheckPredicate, 0, 105, 61, // Skip to: 40641 +/* 24920 */ MCD_OPC_Decode, 130, 12, 158, 1, // Opcode: SQRSHRNv4i16_shift +/* 24925 */ MCD_OPC_FilterValue, 1, 96, 61, // Skip to: 40641 +/* 24929 */ MCD_OPC_CheckPredicate, 0, 92, 61, // Skip to: 40641 +/* 24933 */ MCD_OPC_Decode, 129, 12, 160, 1, // Opcode: SQRSHRNv2i32_shift +/* 24938 */ MCD_OPC_FilterValue, 15, 83, 61, // Skip to: 40641 +/* 24942 */ MCD_OPC_CheckPredicate, 0, 79, 61, // Skip to: 40641 +/* 24946 */ MCD_OPC_CheckField, 21, 1, 1, 73, 61, // Skip to: 40641 +/* 24952 */ MCD_OPC_Decode, 250, 3, 148, 1, // Opcode: FCVTZSv2i32_shift +/* 24957 */ MCD_OPC_FilterValue, 1, 128, 3, // Skip to: 25857 +/* 24961 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 24964 */ MCD_OPC_FilterValue, 1, 233, 2, // Skip to: 25713 +/* 24968 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 24971 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 25399 +/* 24975 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 24978 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 25189 +/* 24982 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 24985 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 25130 +/* 24989 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24992 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 25071 +/* 24996 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 24999 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25012 +/* 25003 */ MCD_OPC_CheckPredicate, 0, 18, 61, // Skip to: 40641 +/* 25007 */ MCD_OPC_Decode, 241, 8, 145, 1, // Opcode: MVNIv2i32 +/* 25012 */ MCD_OPC_FilterValue, 1, 9, 61, // Skip to: 40641 +/* 25016 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25019 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25032 +/* 25023 */ MCD_OPC_CheckPredicate, 0, 254, 60, // Skip to: 40641 +/* 25027 */ MCD_OPC_Decode, 148, 18, 146, 1, // Opcode: USHRv8i8_shift +/* 25032 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25045 +/* 25036 */ MCD_OPC_CheckPredicate, 0, 241, 60, // Skip to: 40641 +/* 25040 */ MCD_OPC_Decode, 244, 17, 146, 1, // Opcode: URSHRv8i8_shift +/* 25045 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25058 +/* 25049 */ MCD_OPC_CheckPredicate, 0, 228, 60, // Skip to: 40641 +/* 25053 */ MCD_OPC_Decode, 236, 12, 150, 1, // Opcode: SRIv8i8_shift +/* 25058 */ MCD_OPC_FilterValue, 3, 219, 60, // Skip to: 40641 +/* 25062 */ MCD_OPC_CheckPredicate, 0, 215, 60, // Skip to: 40641 +/* 25066 */ MCD_OPC_Decode, 153, 12, 151, 1, // Opcode: SQSHLUv8i8_shift +/* 25071 */ MCD_OPC_FilterValue, 1, 206, 60, // Skip to: 40641 +/* 25075 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25078 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25091 +/* 25082 */ MCD_OPC_CheckPredicate, 0, 195, 60, // Skip to: 40641 +/* 25086 */ MCD_OPC_Decode, 145, 18, 147, 1, // Opcode: USHRv4i16_shift +/* 25091 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25104 +/* 25095 */ MCD_OPC_CheckPredicate, 0, 182, 60, // Skip to: 40641 +/* 25099 */ MCD_OPC_Decode, 241, 17, 147, 1, // Opcode: URSHRv4i16_shift +/* 25104 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25117 +/* 25108 */ MCD_OPC_CheckPredicate, 0, 169, 60, // Skip to: 40641 +/* 25112 */ MCD_OPC_Decode, 233, 12, 152, 1, // Opcode: SRIv4i16_shift +/* 25117 */ MCD_OPC_FilterValue, 3, 160, 60, // Skip to: 40641 +/* 25121 */ MCD_OPC_CheckPredicate, 0, 156, 60, // Skip to: 40641 +/* 25125 */ MCD_OPC_Decode, 150, 12, 153, 1, // Opcode: SQSHLUv4i16_shift +/* 25130 */ MCD_OPC_FilterValue, 1, 147, 60, // Skip to: 40641 +/* 25134 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25137 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25150 +/* 25141 */ MCD_OPC_CheckPredicate, 0, 136, 60, // Skip to: 40641 +/* 25145 */ MCD_OPC_Decode, 143, 18, 148, 1, // Opcode: USHRv2i32_shift +/* 25150 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25163 +/* 25154 */ MCD_OPC_CheckPredicate, 0, 123, 60, // Skip to: 40641 +/* 25158 */ MCD_OPC_Decode, 239, 17, 148, 1, // Opcode: URSHRv2i32_shift +/* 25163 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25176 +/* 25167 */ MCD_OPC_CheckPredicate, 0, 110, 60, // Skip to: 40641 +/* 25171 */ MCD_OPC_Decode, 231, 12, 154, 1, // Opcode: SRIv2i32_shift +/* 25176 */ MCD_OPC_FilterValue, 3, 101, 60, // Skip to: 40641 +/* 25180 */ MCD_OPC_CheckPredicate, 0, 97, 60, // Skip to: 40641 +/* 25184 */ MCD_OPC_Decode, 148, 12, 155, 1, // Opcode: SQSHLUv2i32_shift +/* 25189 */ MCD_OPC_FilterValue, 1, 88, 60, // Skip to: 40641 +/* 25193 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25196 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 25340 +/* 25200 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25203 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 25281 +/* 25207 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 25210 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25222 +/* 25214 */ MCD_OPC_CheckPredicate, 0, 63, 60, // Skip to: 40641 +/* 25218 */ MCD_OPC_Decode, 115, 149, 1, // Opcode: BICv2i32 +/* 25222 */ MCD_OPC_FilterValue, 1, 55, 60, // Skip to: 40641 +/* 25226 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25229 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25242 +/* 25233 */ MCD_OPC_CheckPredicate, 0, 44, 60, // Skip to: 40641 +/* 25237 */ MCD_OPC_Decode, 167, 18, 150, 1, // Opcode: USRAv8i8_shift +/* 25242 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25255 +/* 25246 */ MCD_OPC_CheckPredicate, 0, 31, 60, // Skip to: 40641 +/* 25250 */ MCD_OPC_Decode, 254, 17, 150, 1, // Opcode: URSRAv8i8_shift +/* 25255 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25268 +/* 25259 */ MCD_OPC_CheckPredicate, 0, 18, 60, // Skip to: 40641 +/* 25263 */ MCD_OPC_Decode, 203, 10, 162, 1, // Opcode: SLIv8i8_shift +/* 25268 */ MCD_OPC_FilterValue, 3, 9, 60, // Skip to: 40641 +/* 25272 */ MCD_OPC_CheckPredicate, 0, 5, 60, // Skip to: 40641 +/* 25276 */ MCD_OPC_Decode, 191, 17, 151, 1, // Opcode: UQSHLv8i8_shift +/* 25281 */ MCD_OPC_FilterValue, 1, 252, 59, // Skip to: 40641 +/* 25285 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25288 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25301 +/* 25292 */ MCD_OPC_CheckPredicate, 0, 241, 59, // Skip to: 40641 +/* 25296 */ MCD_OPC_Decode, 164, 18, 152, 1, // Opcode: USRAv4i16_shift +/* 25301 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25314 +/* 25305 */ MCD_OPC_CheckPredicate, 0, 228, 59, // Skip to: 40641 +/* 25309 */ MCD_OPC_Decode, 251, 17, 152, 1, // Opcode: URSRAv4i16_shift +/* 25314 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25327 +/* 25318 */ MCD_OPC_CheckPredicate, 0, 215, 59, // Skip to: 40641 +/* 25322 */ MCD_OPC_Decode, 200, 10, 163, 1, // Opcode: SLIv4i16_shift +/* 25327 */ MCD_OPC_FilterValue, 3, 206, 59, // Skip to: 40641 +/* 25331 */ MCD_OPC_CheckPredicate, 0, 202, 59, // Skip to: 40641 +/* 25335 */ MCD_OPC_Decode, 185, 17, 153, 1, // Opcode: UQSHLv4i16_shift +/* 25340 */ MCD_OPC_FilterValue, 1, 193, 59, // Skip to: 40641 +/* 25344 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25347 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25360 +/* 25351 */ MCD_OPC_CheckPredicate, 0, 182, 59, // Skip to: 40641 +/* 25355 */ MCD_OPC_Decode, 162, 18, 154, 1, // Opcode: USRAv2i32_shift +/* 25360 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25373 +/* 25364 */ MCD_OPC_CheckPredicate, 0, 169, 59, // Skip to: 40641 +/* 25368 */ MCD_OPC_Decode, 249, 17, 154, 1, // Opcode: URSRAv2i32_shift +/* 25373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25386 +/* 25377 */ MCD_OPC_CheckPredicate, 0, 156, 59, // Skip to: 40641 +/* 25381 */ MCD_OPC_Decode, 198, 10, 164, 1, // Opcode: SLIv2i32_shift +/* 25386 */ MCD_OPC_FilterValue, 3, 147, 59, // Skip to: 40641 +/* 25390 */ MCD_OPC_CheckPredicate, 0, 143, 59, // Skip to: 40641 +/* 25394 */ MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: UQSHLv2i32_shift +/* 25399 */ MCD_OPC_FilterValue, 1, 134, 59, // Skip to: 40641 +/* 25403 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 25406 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 25636 +/* 25410 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 25413 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 25546 +/* 25417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25420 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25513 +/* 25424 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25427 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25480 +/* 25431 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 25434 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25447 +/* 25438 */ MCD_OPC_CheckPredicate, 0, 95, 59, // Skip to: 40641 +/* 25442 */ MCD_OPC_Decode, 243, 8, 145, 1, // Opcode: MVNIv4i16 +/* 25447 */ MCD_OPC_FilterValue, 1, 86, 59, // Skip to: 40641 +/* 25451 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 25454 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25467 +/* 25458 */ MCD_OPC_CheckPredicate, 0, 75, 59, // Skip to: 40641 +/* 25462 */ MCD_OPC_Decode, 193, 12, 156, 1, // Opcode: SQSHRUNv8i8_shift +/* 25467 */ MCD_OPC_FilterValue, 1, 66, 59, // Skip to: 40641 +/* 25471 */ MCD_OPC_CheckPredicate, 0, 62, 59, // Skip to: 40641 +/* 25475 */ MCD_OPC_Decode, 132, 18, 157, 1, // Opcode: USHLLv8i8_shift +/* 25480 */ MCD_OPC_FilterValue, 1, 53, 59, // Skip to: 40641 +/* 25484 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 25487 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25500 +/* 25491 */ MCD_OPC_CheckPredicate, 0, 42, 59, // Skip to: 40641 +/* 25495 */ MCD_OPC_Decode, 190, 12, 158, 1, // Opcode: SQSHRUNv4i16_shift +/* 25500 */ MCD_OPC_FilterValue, 1, 33, 59, // Skip to: 40641 +/* 25504 */ MCD_OPC_CheckPredicate, 0, 29, 59, // Skip to: 40641 +/* 25508 */ MCD_OPC_Decode, 129, 18, 159, 1, // Opcode: USHLLv4i16_shift +/* 25513 */ MCD_OPC_FilterValue, 1, 20, 59, // Skip to: 40641 +/* 25517 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 25520 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25533 +/* 25524 */ MCD_OPC_CheckPredicate, 0, 9, 59, // Skip to: 40641 +/* 25528 */ MCD_OPC_Decode, 189, 12, 160, 1, // Opcode: SQSHRUNv2i32_shift +/* 25533 */ MCD_OPC_FilterValue, 1, 0, 59, // Skip to: 40641 +/* 25537 */ MCD_OPC_CheckPredicate, 0, 252, 58, // Skip to: 40641 +/* 25541 */ MCD_OPC_Decode, 128, 18, 161, 1, // Opcode: USHLLv2i32_shift +/* 25546 */ MCD_OPC_FilterValue, 1, 243, 58, // Skip to: 40641 +/* 25550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25553 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 25617 +/* 25557 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25560 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 25598 +/* 25564 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 25567 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25579 +/* 25571 */ MCD_OPC_CheckPredicate, 0, 218, 58, // Skip to: 40641 +/* 25575 */ MCD_OPC_Decode, 116, 149, 1, // Opcode: BICv4i16 +/* 25579 */ MCD_OPC_FilterValue, 1, 210, 58, // Skip to: 40641 +/* 25583 */ MCD_OPC_CheckPredicate, 0, 206, 58, // Skip to: 40641 +/* 25587 */ MCD_OPC_CheckField, 13, 1, 0, 200, 58, // Skip to: 40641 +/* 25593 */ MCD_OPC_Decode, 200, 17, 156, 1, // Opcode: UQSHRNv8i8_shift +/* 25598 */ MCD_OPC_FilterValue, 1, 191, 58, // Skip to: 40641 +/* 25602 */ MCD_OPC_CheckPredicate, 0, 187, 58, // Skip to: 40641 +/* 25606 */ MCD_OPC_CheckField, 13, 1, 0, 181, 58, // Skip to: 40641 +/* 25612 */ MCD_OPC_Decode, 197, 17, 158, 1, // Opcode: UQSHRNv4i16_shift +/* 25617 */ MCD_OPC_FilterValue, 1, 172, 58, // Skip to: 40641 +/* 25621 */ MCD_OPC_CheckPredicate, 0, 168, 58, // Skip to: 40641 +/* 25625 */ MCD_OPC_CheckField, 13, 1, 0, 162, 58, // Skip to: 40641 +/* 25631 */ MCD_OPC_Decode, 196, 17, 160, 1, // Opcode: UQSHRNv2i32_shift +/* 25636 */ MCD_OPC_FilterValue, 1, 153, 58, // Skip to: 40641 +/* 25640 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 25643 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25662 +/* 25647 */ MCD_OPC_CheckPredicate, 0, 142, 58, // Skip to: 40641 +/* 25651 */ MCD_OPC_CheckField, 19, 3, 0, 136, 58, // Skip to: 40641 +/* 25657 */ MCD_OPC_Decode, 242, 8, 145, 1, // Opcode: MVNIv2s_msl +/* 25662 */ MCD_OPC_FilterValue, 1, 127, 58, // Skip to: 40641 +/* 25666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25669 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 25694 +/* 25673 */ MCD_OPC_CheckPredicate, 0, 116, 58, // Skip to: 40641 +/* 25677 */ MCD_OPC_CheckField, 19, 2, 0, 110, 58, // Skip to: 40641 +/* 25683 */ MCD_OPC_CheckField, 12, 1, 0, 104, 58, // Skip to: 40641 +/* 25689 */ MCD_OPC_Decode, 202, 8, 145, 1, // Opcode: MOVID +/* 25694 */ MCD_OPC_FilterValue, 1, 95, 58, // Skip to: 40641 +/* 25698 */ MCD_OPC_CheckPredicate, 0, 91, 58, // Skip to: 40641 +/* 25702 */ MCD_OPC_CheckField, 12, 1, 0, 85, 58, // Skip to: 40641 +/* 25708 */ MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: UCVTFv2i32_shift +/* 25713 */ MCD_OPC_FilterValue, 3, 76, 58, // Skip to: 40641 +/* 25717 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 25720 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 25779 +/* 25724 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25727 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25766 +/* 25731 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25734 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25753 +/* 25738 */ MCD_OPC_CheckPredicate, 0, 51, 58, // Skip to: 40641 +/* 25742 */ MCD_OPC_CheckField, 19, 1, 1, 45, 58, // Skip to: 40641 +/* 25748 */ MCD_OPC_Decode, 142, 12, 156, 1, // Opcode: SQRSHRUNv8i8_shift +/* 25753 */ MCD_OPC_FilterValue, 1, 36, 58, // Skip to: 40641 +/* 25757 */ MCD_OPC_CheckPredicate, 0, 32, 58, // Skip to: 40641 +/* 25761 */ MCD_OPC_Decode, 139, 12, 158, 1, // Opcode: SQRSHRUNv4i16_shift +/* 25766 */ MCD_OPC_FilterValue, 1, 23, 58, // Skip to: 40641 +/* 25770 */ MCD_OPC_CheckPredicate, 0, 19, 58, // Skip to: 40641 +/* 25774 */ MCD_OPC_Decode, 138, 12, 160, 1, // Opcode: SQRSHRUNv2i32_shift +/* 25779 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 25838 +/* 25783 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25786 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25825 +/* 25790 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25793 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25812 +/* 25797 */ MCD_OPC_CheckPredicate, 0, 248, 57, // Skip to: 40641 +/* 25801 */ MCD_OPC_CheckField, 19, 1, 1, 242, 57, // Skip to: 40641 +/* 25807 */ MCD_OPC_Decode, 169, 17, 156, 1, // Opcode: UQRSHRNv8i8_shift +/* 25812 */ MCD_OPC_FilterValue, 1, 233, 57, // Skip to: 40641 +/* 25816 */ MCD_OPC_CheckPredicate, 0, 229, 57, // Skip to: 40641 +/* 25820 */ MCD_OPC_Decode, 166, 17, 158, 1, // Opcode: UQRSHRNv4i16_shift +/* 25825 */ MCD_OPC_FilterValue, 1, 220, 57, // Skip to: 40641 +/* 25829 */ MCD_OPC_CheckPredicate, 0, 216, 57, // Skip to: 40641 +/* 25833 */ MCD_OPC_Decode, 165, 17, 160, 1, // Opcode: UQRSHRNv2i32_shift +/* 25838 */ MCD_OPC_FilterValue, 15, 207, 57, // Skip to: 40641 +/* 25842 */ MCD_OPC_CheckPredicate, 0, 203, 57, // Skip to: 40641 +/* 25846 */ MCD_OPC_CheckField, 21, 1, 1, 197, 57, // Skip to: 40641 +/* 25852 */ MCD_OPC_Decode, 151, 4, 148, 1, // Opcode: FCVTZUv2i32_shift +/* 25857 */ MCD_OPC_FilterValue, 2, 66, 3, // Skip to: 26695 +/* 25861 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 25864 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 26551 +/* 25868 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 25871 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 26222 +/* 25875 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 25878 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26011 +/* 25882 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 25885 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25978 +/* 25889 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25892 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25945 +/* 25896 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 25899 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25912 +/* 25903 */ MCD_OPC_CheckPredicate, 0, 142, 57, // Skip to: 40641 +/* 25907 */ MCD_OPC_Decode, 208, 8, 145, 1, // Opcode: MOVIv4i32 +/* 25912 */ MCD_OPC_FilterValue, 1, 133, 57, // Skip to: 40641 +/* 25916 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25932 +/* 25923 */ MCD_OPC_CheckPredicate, 0, 122, 57, // Skip to: 40641 +/* 25927 */ MCD_OPC_Decode, 148, 13, 165, 1, // Opcode: SSHRv16i8_shift +/* 25932 */ MCD_OPC_FilterValue, 1, 113, 57, // Skip to: 40641 +/* 25936 */ MCD_OPC_CheckPredicate, 0, 109, 57, // Skip to: 40641 +/* 25940 */ MCD_OPC_Decode, 246, 12, 165, 1, // Opcode: SRSHRv16i8_shift +/* 25945 */ MCD_OPC_FilterValue, 1, 100, 57, // Skip to: 40641 +/* 25949 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25952 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25965 +/* 25956 */ MCD_OPC_CheckPredicate, 0, 89, 57, // Skip to: 40641 +/* 25960 */ MCD_OPC_Decode, 153, 13, 166, 1, // Opcode: SSHRv8i16_shift +/* 25965 */ MCD_OPC_FilterValue, 1, 80, 57, // Skip to: 40641 +/* 25969 */ MCD_OPC_CheckPredicate, 0, 76, 57, // Skip to: 40641 +/* 25973 */ MCD_OPC_Decode, 251, 12, 166, 1, // Opcode: SRSHRv8i16_shift +/* 25978 */ MCD_OPC_FilterValue, 1, 67, 57, // Skip to: 40641 +/* 25982 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 25985 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25998 +/* 25989 */ MCD_OPC_CheckPredicate, 0, 56, 57, // Skip to: 40641 +/* 25993 */ MCD_OPC_Decode, 152, 13, 167, 1, // Opcode: SSHRv4i32_shift +/* 25998 */ MCD_OPC_FilterValue, 1, 47, 57, // Skip to: 40641 +/* 26002 */ MCD_OPC_CheckPredicate, 0, 43, 57, // Skip to: 40641 +/* 26006 */ MCD_OPC_Decode, 250, 12, 167, 1, // Opcode: SRSHRv4i32_shift +/* 26011 */ MCD_OPC_FilterValue, 1, 34, 57, // Skip to: 40641 +/* 26015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26018 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26163 +/* 26022 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26025 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26104 +/* 26029 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 26032 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26045 +/* 26036 */ MCD_OPC_CheckPredicate, 0, 9, 57, // Skip to: 40641 +/* 26040 */ MCD_OPC_Decode, 144, 9, 149, 1, // Opcode: ORRv4i32 +/* 26045 */ MCD_OPC_FilterValue, 1, 0, 57, // Skip to: 40641 +/* 26049 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26052 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26065 +/* 26056 */ MCD_OPC_CheckPredicate, 0, 245, 56, // Skip to: 40641 +/* 26060 */ MCD_OPC_Decode, 156, 13, 168, 1, // Opcode: SSRAv16i8_shift +/* 26065 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26078 +/* 26069 */ MCD_OPC_CheckPredicate, 0, 232, 56, // Skip to: 40641 +/* 26073 */ MCD_OPC_Decode, 254, 12, 168, 1, // Opcode: SRSRAv16i8_shift +/* 26078 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26091 +/* 26082 */ MCD_OPC_CheckPredicate, 0, 219, 56, // Skip to: 40641 +/* 26086 */ MCD_OPC_Decode, 177, 10, 169, 1, // Opcode: SHLv16i8_shift +/* 26091 */ MCD_OPC_FilterValue, 3, 210, 56, // Skip to: 40641 +/* 26095 */ MCD_OPC_CheckPredicate, 0, 206, 56, // Skip to: 40641 +/* 26099 */ MCD_OPC_Decode, 159, 12, 169, 1, // Opcode: SQSHLv16i8_shift +/* 26104 */ MCD_OPC_FilterValue, 1, 197, 56, // Skip to: 40641 +/* 26108 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26111 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26124 +/* 26115 */ MCD_OPC_CheckPredicate, 0, 186, 56, // Skip to: 40641 +/* 26119 */ MCD_OPC_Decode, 161, 13, 170, 1, // Opcode: SSRAv8i16_shift +/* 26124 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26137 +/* 26128 */ MCD_OPC_CheckPredicate, 0, 173, 56, // Skip to: 40641 +/* 26132 */ MCD_OPC_Decode, 131, 13, 170, 1, // Opcode: SRSRAv8i16_shift +/* 26137 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26150 +/* 26141 */ MCD_OPC_CheckPredicate, 0, 160, 56, // Skip to: 40641 +/* 26145 */ MCD_OPC_Decode, 182, 10, 171, 1, // Opcode: SHLv8i16_shift +/* 26150 */ MCD_OPC_FilterValue, 3, 151, 56, // Skip to: 40641 +/* 26154 */ MCD_OPC_CheckPredicate, 0, 147, 56, // Skip to: 40641 +/* 26158 */ MCD_OPC_Decode, 173, 12, 171, 1, // Opcode: SQSHLv8i16_shift +/* 26163 */ MCD_OPC_FilterValue, 1, 138, 56, // Skip to: 40641 +/* 26167 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26170 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26183 +/* 26174 */ MCD_OPC_CheckPredicate, 0, 127, 56, // Skip to: 40641 +/* 26178 */ MCD_OPC_Decode, 160, 13, 172, 1, // Opcode: SSRAv4i32_shift +/* 26183 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26196 +/* 26187 */ MCD_OPC_CheckPredicate, 0, 114, 56, // Skip to: 40641 +/* 26191 */ MCD_OPC_Decode, 130, 13, 172, 1, // Opcode: SRSRAv4i32_shift +/* 26196 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26209 +/* 26200 */ MCD_OPC_CheckPredicate, 0, 101, 56, // Skip to: 40641 +/* 26204 */ MCD_OPC_Decode, 181, 10, 173, 1, // Opcode: SHLv4i32_shift +/* 26209 */ MCD_OPC_FilterValue, 3, 92, 56, // Skip to: 40641 +/* 26213 */ MCD_OPC_CheckPredicate, 0, 88, 56, // Skip to: 40641 +/* 26217 */ MCD_OPC_Decode, 171, 12, 173, 1, // Opcode: SQSHLv4i32_shift +/* 26222 */ MCD_OPC_FilterValue, 1, 79, 56, // Skip to: 40641 +/* 26226 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 26229 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 26460 +/* 26233 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 26236 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26369 +/* 26240 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26243 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 26336 +/* 26247 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26250 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 26303 +/* 26254 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 26257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26270 +/* 26261 */ MCD_OPC_CheckPredicate, 0, 40, 56, // Skip to: 40641 +/* 26265 */ MCD_OPC_Decode, 211, 8, 145, 1, // Opcode: MOVIv8i16 +/* 26270 */ MCD_OPC_FilterValue, 1, 31, 56, // Skip to: 40641 +/* 26274 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 26277 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26290 +/* 26281 */ MCD_OPC_CheckPredicate, 0, 20, 56, // Skip to: 40641 +/* 26285 */ MCD_OPC_Decode, 184, 10, 174, 1, // Opcode: SHRNv16i8_shift +/* 26290 */ MCD_OPC_FilterValue, 1, 11, 56, // Skip to: 40641 +/* 26294 */ MCD_OPC_CheckPredicate, 0, 7, 56, // Skip to: 40641 +/* 26298 */ MCD_OPC_Decode, 133, 13, 169, 1, // Opcode: SSHLLv16i8_shift +/* 26303 */ MCD_OPC_FilterValue, 1, 254, 55, // Skip to: 40641 +/* 26307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 26310 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26323 +/* 26314 */ MCD_OPC_CheckPredicate, 0, 243, 55, // Skip to: 40641 +/* 26318 */ MCD_OPC_Decode, 188, 10, 175, 1, // Opcode: SHRNv8i16_shift +/* 26323 */ MCD_OPC_FilterValue, 1, 234, 55, // Skip to: 40641 +/* 26327 */ MCD_OPC_CheckPredicate, 0, 230, 55, // Skip to: 40641 +/* 26331 */ MCD_OPC_Decode, 137, 13, 171, 1, // Opcode: SSHLLv8i16_shift +/* 26336 */ MCD_OPC_FilterValue, 1, 221, 55, // Skip to: 40641 +/* 26340 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 26343 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26356 +/* 26347 */ MCD_OPC_CheckPredicate, 0, 210, 55, // Skip to: 40641 +/* 26351 */ MCD_OPC_Decode, 187, 10, 176, 1, // Opcode: SHRNv4i32_shift +/* 26356 */ MCD_OPC_FilterValue, 1, 201, 55, // Skip to: 40641 +/* 26360 */ MCD_OPC_CheckPredicate, 0, 197, 55, // Skip to: 40641 +/* 26364 */ MCD_OPC_Decode, 136, 13, 173, 1, // Opcode: SSHLLv4i32_shift +/* 26369 */ MCD_OPC_FilterValue, 1, 188, 55, // Skip to: 40641 +/* 26373 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26376 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 26441 +/* 26380 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26383 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26422 +/* 26387 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 26390 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26403 +/* 26394 */ MCD_OPC_CheckPredicate, 0, 163, 55, // Skip to: 40641 +/* 26398 */ MCD_OPC_Decode, 145, 9, 149, 1, // Opcode: ORRv8i16 +/* 26403 */ MCD_OPC_FilterValue, 1, 154, 55, // Skip to: 40641 +/* 26407 */ MCD_OPC_CheckPredicate, 0, 150, 55, // Skip to: 40641 +/* 26411 */ MCD_OPC_CheckField, 13, 1, 0, 144, 55, // Skip to: 40641 +/* 26417 */ MCD_OPC_Decode, 179, 12, 174, 1, // Opcode: SQSHRNv16i8_shift +/* 26422 */ MCD_OPC_FilterValue, 1, 135, 55, // Skip to: 40641 +/* 26426 */ MCD_OPC_CheckPredicate, 0, 131, 55, // Skip to: 40641 +/* 26430 */ MCD_OPC_CheckField, 13, 1, 0, 125, 55, // Skip to: 40641 +/* 26436 */ MCD_OPC_Decode, 183, 12, 175, 1, // Opcode: SQSHRNv8i16_shift +/* 26441 */ MCD_OPC_FilterValue, 1, 116, 55, // Skip to: 40641 +/* 26445 */ MCD_OPC_CheckPredicate, 0, 112, 55, // Skip to: 40641 +/* 26449 */ MCD_OPC_CheckField, 13, 1, 0, 106, 55, // Skip to: 40641 +/* 26455 */ MCD_OPC_Decode, 182, 12, 176, 1, // Opcode: SQSHRNv4i32_shift +/* 26460 */ MCD_OPC_FilterValue, 1, 97, 55, // Skip to: 40641 +/* 26464 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 26467 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26486 +/* 26471 */ MCD_OPC_CheckPredicate, 0, 86, 55, // Skip to: 40641 +/* 26475 */ MCD_OPC_CheckField, 19, 3, 0, 80, 55, // Skip to: 40641 +/* 26481 */ MCD_OPC_Decode, 209, 8, 145, 1, // Opcode: MOVIv4s_msl +/* 26486 */ MCD_OPC_FilterValue, 1, 71, 55, // Skip to: 40641 +/* 26490 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 26493 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26532 +/* 26497 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26500 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26519 +/* 26504 */ MCD_OPC_CheckPredicate, 0, 53, 55, // Skip to: 40641 +/* 26508 */ MCD_OPC_CheckField, 19, 2, 0, 47, 55, // Skip to: 40641 +/* 26514 */ MCD_OPC_Decode, 203, 8, 145, 1, // Opcode: MOVIv16b_ns +/* 26519 */ MCD_OPC_FilterValue, 1, 38, 55, // Skip to: 40641 +/* 26523 */ MCD_OPC_CheckPredicate, 0, 34, 55, // Skip to: 40641 +/* 26527 */ MCD_OPC_Decode, 149, 10, 167, 1, // Opcode: SCVTFv4i32_shift +/* 26532 */ MCD_OPC_FilterValue, 1, 25, 55, // Skip to: 40641 +/* 26536 */ MCD_OPC_CheckPredicate, 0, 21, 55, // Skip to: 40641 +/* 26540 */ MCD_OPC_CheckField, 19, 3, 0, 15, 55, // Skip to: 40641 +/* 26546 */ MCD_OPC_Decode, 234, 4, 145, 1, // Opcode: FMOVv4f32_ns +/* 26551 */ MCD_OPC_FilterValue, 3, 6, 55, // Skip to: 40641 +/* 26555 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 26558 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 26617 +/* 26562 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26565 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26604 +/* 26569 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26572 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26591 +/* 26576 */ MCD_OPC_CheckPredicate, 0, 237, 54, // Skip to: 40641 +/* 26580 */ MCD_OPC_CheckField, 19, 1, 1, 231, 54, // Skip to: 40641 +/* 26586 */ MCD_OPC_Decode, 189, 9, 174, 1, // Opcode: RSHRNv16i8_shift +/* 26591 */ MCD_OPC_FilterValue, 1, 222, 54, // Skip to: 40641 +/* 26595 */ MCD_OPC_CheckPredicate, 0, 218, 54, // Skip to: 40641 +/* 26599 */ MCD_OPC_Decode, 193, 9, 175, 1, // Opcode: RSHRNv8i16_shift +/* 26604 */ MCD_OPC_FilterValue, 1, 209, 54, // Skip to: 40641 +/* 26608 */ MCD_OPC_CheckPredicate, 0, 205, 54, // Skip to: 40641 +/* 26612 */ MCD_OPC_Decode, 192, 9, 176, 1, // Opcode: RSHRNv4i32_shift +/* 26617 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 26676 +/* 26621 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26624 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26663 +/* 26628 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26631 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26650 +/* 26635 */ MCD_OPC_CheckPredicate, 0, 178, 54, // Skip to: 40641 +/* 26639 */ MCD_OPC_CheckField, 19, 1, 1, 172, 54, // Skip to: 40641 +/* 26645 */ MCD_OPC_Decode, 128, 12, 174, 1, // Opcode: SQRSHRNv16i8_shift +/* 26650 */ MCD_OPC_FilterValue, 1, 163, 54, // Skip to: 40641 +/* 26654 */ MCD_OPC_CheckPredicate, 0, 159, 54, // Skip to: 40641 +/* 26658 */ MCD_OPC_Decode, 132, 12, 175, 1, // Opcode: SQRSHRNv8i16_shift +/* 26663 */ MCD_OPC_FilterValue, 1, 150, 54, // Skip to: 40641 +/* 26667 */ MCD_OPC_CheckPredicate, 0, 146, 54, // Skip to: 40641 +/* 26671 */ MCD_OPC_Decode, 131, 12, 176, 1, // Opcode: SQRSHRNv4i32_shift +/* 26676 */ MCD_OPC_FilterValue, 15, 137, 54, // Skip to: 40641 +/* 26680 */ MCD_OPC_CheckPredicate, 0, 133, 54, // Skip to: 40641 +/* 26684 */ MCD_OPC_CheckField, 21, 1, 1, 127, 54, // Skip to: 40641 +/* 26690 */ MCD_OPC_Decode, 253, 3, 167, 1, // Opcode: FCVTZSv4i32_shift +/* 26695 */ MCD_OPC_FilterValue, 3, 118, 54, // Skip to: 40641 +/* 26699 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 26702 */ MCD_OPC_FilterValue, 1, 247, 2, // Skip to: 27465 +/* 26706 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 26709 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 27137 +/* 26713 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 26716 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 26927 +/* 26720 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26723 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26868 +/* 26727 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26730 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26809 +/* 26734 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 26737 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26750 +/* 26741 */ MCD_OPC_CheckPredicate, 0, 72, 54, // Skip to: 40641 +/* 26745 */ MCD_OPC_Decode, 244, 8, 145, 1, // Opcode: MVNIv4i32 +/* 26750 */ MCD_OPC_FilterValue, 1, 63, 54, // Skip to: 40641 +/* 26754 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26757 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26770 +/* 26761 */ MCD_OPC_CheckPredicate, 0, 52, 54, // Skip to: 40641 +/* 26765 */ MCD_OPC_Decode, 142, 18, 165, 1, // Opcode: USHRv16i8_shift +/* 26770 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26783 +/* 26774 */ MCD_OPC_CheckPredicate, 0, 39, 54, // Skip to: 40641 +/* 26778 */ MCD_OPC_Decode, 238, 17, 165, 1, // Opcode: URSHRv16i8_shift +/* 26783 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26796 +/* 26787 */ MCD_OPC_CheckPredicate, 0, 26, 54, // Skip to: 40641 +/* 26791 */ MCD_OPC_Decode, 230, 12, 168, 1, // Opcode: SRIv16i8_shift +/* 26796 */ MCD_OPC_FilterValue, 3, 17, 54, // Skip to: 40641 +/* 26800 */ MCD_OPC_CheckPredicate, 0, 13, 54, // Skip to: 40641 +/* 26804 */ MCD_OPC_Decode, 147, 12, 169, 1, // Opcode: SQSHLUv16i8_shift +/* 26809 */ MCD_OPC_FilterValue, 1, 4, 54, // Skip to: 40641 +/* 26813 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26816 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26829 +/* 26820 */ MCD_OPC_CheckPredicate, 0, 249, 53, // Skip to: 40641 +/* 26824 */ MCD_OPC_Decode, 147, 18, 166, 1, // Opcode: USHRv8i16_shift +/* 26829 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26842 +/* 26833 */ MCD_OPC_CheckPredicate, 0, 236, 53, // Skip to: 40641 +/* 26837 */ MCD_OPC_Decode, 243, 17, 166, 1, // Opcode: URSHRv8i16_shift +/* 26842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26855 +/* 26846 */ MCD_OPC_CheckPredicate, 0, 223, 53, // Skip to: 40641 +/* 26850 */ MCD_OPC_Decode, 235, 12, 170, 1, // Opcode: SRIv8i16_shift +/* 26855 */ MCD_OPC_FilterValue, 3, 214, 53, // Skip to: 40641 +/* 26859 */ MCD_OPC_CheckPredicate, 0, 210, 53, // Skip to: 40641 +/* 26863 */ MCD_OPC_Decode, 152, 12, 171, 1, // Opcode: SQSHLUv8i16_shift +/* 26868 */ MCD_OPC_FilterValue, 1, 201, 53, // Skip to: 40641 +/* 26872 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26875 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26888 +/* 26879 */ MCD_OPC_CheckPredicate, 0, 190, 53, // Skip to: 40641 +/* 26883 */ MCD_OPC_Decode, 146, 18, 167, 1, // Opcode: USHRv4i32_shift +/* 26888 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26901 +/* 26892 */ MCD_OPC_CheckPredicate, 0, 177, 53, // Skip to: 40641 +/* 26896 */ MCD_OPC_Decode, 242, 17, 167, 1, // Opcode: URSHRv4i32_shift +/* 26901 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26914 +/* 26905 */ MCD_OPC_CheckPredicate, 0, 164, 53, // Skip to: 40641 +/* 26909 */ MCD_OPC_Decode, 234, 12, 172, 1, // Opcode: SRIv4i32_shift +/* 26914 */ MCD_OPC_FilterValue, 3, 155, 53, // Skip to: 40641 +/* 26918 */ MCD_OPC_CheckPredicate, 0, 151, 53, // Skip to: 40641 +/* 26922 */ MCD_OPC_Decode, 151, 12, 173, 1, // Opcode: SQSHLUv4i32_shift +/* 26927 */ MCD_OPC_FilterValue, 1, 142, 53, // Skip to: 40641 +/* 26931 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26934 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 27078 +/* 26938 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 26941 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 27019 +/* 26945 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 26948 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 26960 +/* 26952 */ MCD_OPC_CheckPredicate, 0, 117, 53, // Skip to: 40641 +/* 26956 */ MCD_OPC_Decode, 117, 149, 1, // Opcode: BICv4i32 +/* 26960 */ MCD_OPC_FilterValue, 1, 109, 53, // Skip to: 40641 +/* 26964 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 26967 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26980 +/* 26971 */ MCD_OPC_CheckPredicate, 0, 98, 53, // Skip to: 40641 +/* 26975 */ MCD_OPC_Decode, 161, 18, 168, 1, // Opcode: USRAv16i8_shift +/* 26980 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26993 +/* 26984 */ MCD_OPC_CheckPredicate, 0, 85, 53, // Skip to: 40641 +/* 26988 */ MCD_OPC_Decode, 248, 17, 168, 1, // Opcode: URSRAv16i8_shift +/* 26993 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27006 +/* 26997 */ MCD_OPC_CheckPredicate, 0, 72, 53, // Skip to: 40641 +/* 27001 */ MCD_OPC_Decode, 197, 10, 177, 1, // Opcode: SLIv16i8_shift +/* 27006 */ MCD_OPC_FilterValue, 3, 63, 53, // Skip to: 40641 +/* 27010 */ MCD_OPC_CheckPredicate, 0, 59, 53, // Skip to: 40641 +/* 27014 */ MCD_OPC_Decode, 175, 17, 169, 1, // Opcode: UQSHLv16i8_shift +/* 27019 */ MCD_OPC_FilterValue, 1, 50, 53, // Skip to: 40641 +/* 27023 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 27026 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27039 +/* 27030 */ MCD_OPC_CheckPredicate, 0, 39, 53, // Skip to: 40641 +/* 27034 */ MCD_OPC_Decode, 166, 18, 170, 1, // Opcode: USRAv8i16_shift +/* 27039 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27052 +/* 27043 */ MCD_OPC_CheckPredicate, 0, 26, 53, // Skip to: 40641 +/* 27047 */ MCD_OPC_Decode, 253, 17, 170, 1, // Opcode: URSRAv8i16_shift +/* 27052 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27065 +/* 27056 */ MCD_OPC_CheckPredicate, 0, 13, 53, // Skip to: 40641 +/* 27060 */ MCD_OPC_Decode, 202, 10, 178, 1, // Opcode: SLIv8i16_shift +/* 27065 */ MCD_OPC_FilterValue, 3, 4, 53, // Skip to: 40641 +/* 27069 */ MCD_OPC_CheckPredicate, 0, 0, 53, // Skip to: 40641 +/* 27073 */ MCD_OPC_Decode, 189, 17, 171, 1, // Opcode: UQSHLv8i16_shift +/* 27078 */ MCD_OPC_FilterValue, 1, 247, 52, // Skip to: 40641 +/* 27082 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 27085 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27098 +/* 27089 */ MCD_OPC_CheckPredicate, 0, 236, 52, // Skip to: 40641 +/* 27093 */ MCD_OPC_Decode, 165, 18, 172, 1, // Opcode: USRAv4i32_shift +/* 27098 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27111 +/* 27102 */ MCD_OPC_CheckPredicate, 0, 223, 52, // Skip to: 40641 +/* 27106 */ MCD_OPC_Decode, 252, 17, 172, 1, // Opcode: URSRAv4i32_shift +/* 27111 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27124 +/* 27115 */ MCD_OPC_CheckPredicate, 0, 210, 52, // Skip to: 40641 +/* 27119 */ MCD_OPC_Decode, 201, 10, 179, 1, // Opcode: SLIv4i32_shift +/* 27124 */ MCD_OPC_FilterValue, 3, 201, 52, // Skip to: 40641 +/* 27128 */ MCD_OPC_CheckPredicate, 0, 197, 52, // Skip to: 40641 +/* 27132 */ MCD_OPC_Decode, 187, 17, 173, 1, // Opcode: UQSHLv4i32_shift +/* 27137 */ MCD_OPC_FilterValue, 1, 188, 52, // Skip to: 40641 +/* 27141 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 27144 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 27374 +/* 27148 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 27151 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 27284 +/* 27155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27158 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 27251 +/* 27162 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 27165 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 27218 +/* 27169 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 27172 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27185 +/* 27176 */ MCD_OPC_CheckPredicate, 0, 149, 52, // Skip to: 40641 +/* 27180 */ MCD_OPC_Decode, 246, 8, 145, 1, // Opcode: MVNIv8i16 +/* 27185 */ MCD_OPC_FilterValue, 1, 140, 52, // Skip to: 40641 +/* 27189 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 27192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27205 +/* 27196 */ MCD_OPC_CheckPredicate, 0, 129, 52, // Skip to: 40641 +/* 27200 */ MCD_OPC_Decode, 188, 12, 174, 1, // Opcode: SQSHRUNv16i8_shift +/* 27205 */ MCD_OPC_FilterValue, 1, 120, 52, // Skip to: 40641 +/* 27209 */ MCD_OPC_CheckPredicate, 0, 116, 52, // Skip to: 40641 +/* 27213 */ MCD_OPC_Decode, 255, 17, 169, 1, // Opcode: USHLLv16i8_shift +/* 27218 */ MCD_OPC_FilterValue, 1, 107, 52, // Skip to: 40641 +/* 27222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 27225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27238 +/* 27229 */ MCD_OPC_CheckPredicate, 0, 96, 52, // Skip to: 40641 +/* 27233 */ MCD_OPC_Decode, 192, 12, 175, 1, // Opcode: SQSHRUNv8i16_shift +/* 27238 */ MCD_OPC_FilterValue, 1, 87, 52, // Skip to: 40641 +/* 27242 */ MCD_OPC_CheckPredicate, 0, 83, 52, // Skip to: 40641 +/* 27246 */ MCD_OPC_Decode, 131, 18, 171, 1, // Opcode: USHLLv8i16_shift +/* 27251 */ MCD_OPC_FilterValue, 1, 74, 52, // Skip to: 40641 +/* 27255 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 27258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27271 +/* 27262 */ MCD_OPC_CheckPredicate, 0, 63, 52, // Skip to: 40641 +/* 27266 */ MCD_OPC_Decode, 191, 12, 176, 1, // Opcode: SQSHRUNv4i32_shift +/* 27271 */ MCD_OPC_FilterValue, 1, 54, 52, // Skip to: 40641 +/* 27275 */ MCD_OPC_CheckPredicate, 0, 50, 52, // Skip to: 40641 +/* 27279 */ MCD_OPC_Decode, 130, 18, 173, 1, // Opcode: USHLLv4i32_shift +/* 27284 */ MCD_OPC_FilterValue, 1, 41, 52, // Skip to: 40641 +/* 27288 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27291 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 27355 +/* 27295 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 27298 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 27336 +/* 27302 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 27305 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 27317 +/* 27309 */ MCD_OPC_CheckPredicate, 0, 16, 52, // Skip to: 40641 +/* 27313 */ MCD_OPC_Decode, 118, 149, 1, // Opcode: BICv8i16 +/* 27317 */ MCD_OPC_FilterValue, 1, 8, 52, // Skip to: 40641 +/* 27321 */ MCD_OPC_CheckPredicate, 0, 4, 52, // Skip to: 40641 +/* 27325 */ MCD_OPC_CheckField, 13, 1, 0, 254, 51, // Skip to: 40641 +/* 27331 */ MCD_OPC_Decode, 195, 17, 174, 1, // Opcode: UQSHRNv16i8_shift +/* 27336 */ MCD_OPC_FilterValue, 1, 245, 51, // Skip to: 40641 +/* 27340 */ MCD_OPC_CheckPredicate, 0, 241, 51, // Skip to: 40641 +/* 27344 */ MCD_OPC_CheckField, 13, 1, 0, 235, 51, // Skip to: 40641 +/* 27350 */ MCD_OPC_Decode, 199, 17, 175, 1, // Opcode: UQSHRNv8i16_shift +/* 27355 */ MCD_OPC_FilterValue, 1, 226, 51, // Skip to: 40641 +/* 27359 */ MCD_OPC_CheckPredicate, 0, 222, 51, // Skip to: 40641 +/* 27363 */ MCD_OPC_CheckField, 13, 1, 0, 216, 51, // Skip to: 40641 +/* 27369 */ MCD_OPC_Decode, 198, 17, 176, 1, // Opcode: UQSHRNv4i32_shift +/* 27374 */ MCD_OPC_FilterValue, 1, 207, 51, // Skip to: 40641 +/* 27378 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 27381 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27400 +/* 27385 */ MCD_OPC_CheckPredicate, 0, 196, 51, // Skip to: 40641 +/* 27389 */ MCD_OPC_CheckField, 19, 3, 0, 190, 51, // Skip to: 40641 +/* 27395 */ MCD_OPC_Decode, 245, 8, 145, 1, // Opcode: MVNIv4s_msl +/* 27400 */ MCD_OPC_FilterValue, 1, 181, 51, // Skip to: 40641 +/* 27404 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 27407 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27446 +/* 27411 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27414 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27433 +/* 27418 */ MCD_OPC_CheckPredicate, 0, 163, 51, // Skip to: 40641 +/* 27422 */ MCD_OPC_CheckField, 19, 2, 0, 157, 51, // Skip to: 40641 +/* 27428 */ MCD_OPC_Decode, 204, 8, 145, 1, // Opcode: MOVIv2d_ns +/* 27433 */ MCD_OPC_FilterValue, 1, 148, 51, // Skip to: 40641 +/* 27437 */ MCD_OPC_CheckPredicate, 0, 144, 51, // Skip to: 40641 +/* 27441 */ MCD_OPC_Decode, 179, 16, 167, 1, // Opcode: UCVTFv4i32_shift +/* 27446 */ MCD_OPC_FilterValue, 1, 135, 51, // Skip to: 40641 +/* 27450 */ MCD_OPC_CheckPredicate, 0, 131, 51, // Skip to: 40641 +/* 27454 */ MCD_OPC_CheckField, 19, 3, 0, 125, 51, // Skip to: 40641 +/* 27460 */ MCD_OPC_Decode, 233, 4, 145, 1, // Opcode: FMOVv2f64_ns +/* 27465 */ MCD_OPC_FilterValue, 3, 116, 51, // Skip to: 40641 +/* 27469 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 27472 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 27531 +/* 27476 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27479 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27518 +/* 27483 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 27486 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27505 +/* 27490 */ MCD_OPC_CheckPredicate, 0, 91, 51, // Skip to: 40641 +/* 27494 */ MCD_OPC_CheckField, 19, 1, 1, 85, 51, // Skip to: 40641 +/* 27500 */ MCD_OPC_Decode, 137, 12, 174, 1, // Opcode: SQRSHRUNv16i8_shift +/* 27505 */ MCD_OPC_FilterValue, 1, 76, 51, // Skip to: 40641 +/* 27509 */ MCD_OPC_CheckPredicate, 0, 72, 51, // Skip to: 40641 +/* 27513 */ MCD_OPC_Decode, 141, 12, 175, 1, // Opcode: SQRSHRUNv8i16_shift +/* 27518 */ MCD_OPC_FilterValue, 1, 63, 51, // Skip to: 40641 +/* 27522 */ MCD_OPC_CheckPredicate, 0, 59, 51, // Skip to: 40641 +/* 27526 */ MCD_OPC_Decode, 140, 12, 176, 1, // Opcode: SQRSHRUNv4i32_shift +/* 27531 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 27590 +/* 27535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27538 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27577 +/* 27542 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 27545 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27564 +/* 27549 */ MCD_OPC_CheckPredicate, 0, 32, 51, // Skip to: 40641 +/* 27553 */ MCD_OPC_CheckField, 19, 1, 1, 26, 51, // Skip to: 40641 +/* 27559 */ MCD_OPC_Decode, 164, 17, 174, 1, // Opcode: UQRSHRNv16i8_shift +/* 27564 */ MCD_OPC_FilterValue, 1, 17, 51, // Skip to: 40641 +/* 27568 */ MCD_OPC_CheckPredicate, 0, 13, 51, // Skip to: 40641 +/* 27572 */ MCD_OPC_Decode, 168, 17, 175, 1, // Opcode: UQRSHRNv8i16_shift +/* 27577 */ MCD_OPC_FilterValue, 1, 4, 51, // Skip to: 40641 +/* 27581 */ MCD_OPC_CheckPredicate, 0, 0, 51, // Skip to: 40641 +/* 27585 */ MCD_OPC_Decode, 167, 17, 176, 1, // Opcode: UQRSHRNv4i32_shift +/* 27590 */ MCD_OPC_FilterValue, 15, 247, 50, // Skip to: 40641 +/* 27594 */ MCD_OPC_CheckPredicate, 0, 243, 50, // Skip to: 40641 +/* 27598 */ MCD_OPC_CheckField, 21, 1, 1, 237, 50, // Skip to: 40641 +/* 27604 */ MCD_OPC_Decode, 154, 4, 167, 1, // Opcode: FCVTZUv4i32_shift +/* 27609 */ MCD_OPC_FilterValue, 13, 221, 3, // Skip to: 28602 +/* 27613 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 27616 */ MCD_OPC_FilterValue, 0, 80, 0, // Skip to: 27700 +/* 27620 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 27623 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27642 +/* 27627 */ MCD_OPC_CheckPredicate, 0, 210, 50, // Skip to: 40641 +/* 27631 */ MCD_OPC_CheckField, 10, 1, 0, 204, 50, // Skip to: 40641 +/* 27637 */ MCD_OPC_Decode, 186, 8, 180, 1, // Opcode: MLAv4i16_indexed +/* 27642 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27661 +/* 27646 */ MCD_OPC_CheckPredicate, 0, 191, 50, // Skip to: 40641 +/* 27650 */ MCD_OPC_CheckField, 10, 2, 1, 185, 50, // Skip to: 40641 +/* 27656 */ MCD_OPC_Decode, 150, 13, 181, 1, // Opcode: SSHRv2i64_shift +/* 27661 */ MCD_OPC_FilterValue, 3, 176, 50, // Skip to: 40641 +/* 27665 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 27668 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27681 +/* 27672 */ MCD_OPC_CheckPredicate, 0, 165, 50, // Skip to: 40641 +/* 27676 */ MCD_OPC_Decode, 190, 8, 182, 1, // Opcode: MLAv8i16_indexed +/* 27681 */ MCD_OPC_FilterValue, 1, 156, 50, // Skip to: 40641 +/* 27685 */ MCD_OPC_CheckPredicate, 0, 152, 50, // Skip to: 40641 +/* 27689 */ MCD_OPC_CheckField, 11, 1, 0, 146, 50, // Skip to: 40641 +/* 27695 */ MCD_OPC_Decode, 144, 18, 181, 1, // Opcode: USHRv2i64_shift +/* 27700 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 27745 +/* 27704 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 27707 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27726 +/* 27711 */ MCD_OPC_CheckPredicate, 0, 126, 50, // Skip to: 40641 +/* 27715 */ MCD_OPC_CheckField, 10, 2, 1, 120, 50, // Skip to: 40641 +/* 27721 */ MCD_OPC_Decode, 158, 13, 183, 1, // Opcode: SSRAv2i64_shift +/* 27726 */ MCD_OPC_FilterValue, 3, 111, 50, // Skip to: 40641 +/* 27730 */ MCD_OPC_CheckPredicate, 0, 107, 50, // Skip to: 40641 +/* 27734 */ MCD_OPC_CheckField, 10, 2, 1, 101, 50, // Skip to: 40641 +/* 27740 */ MCD_OPC_Decode, 163, 18, 183, 1, // Opcode: USRAv2i64_shift +/* 27745 */ MCD_OPC_FilterValue, 2, 119, 0, // Skip to: 27868 +/* 27749 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 27752 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27771 +/* 27756 */ MCD_OPC_CheckPredicate, 0, 81, 50, // Skip to: 40641 +/* 27760 */ MCD_OPC_CheckField, 10, 1, 0, 75, 50, // Skip to: 40641 +/* 27766 */ MCD_OPC_Decode, 243, 10, 184, 1, // Opcode: SMLALv4i16_indexed +/* 27771 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27790 +/* 27775 */ MCD_OPC_CheckPredicate, 0, 62, 50, // Skip to: 40641 +/* 27779 */ MCD_OPC_CheckField, 10, 1, 0, 56, 50, // Skip to: 40641 +/* 27785 */ MCD_OPC_Decode, 234, 16, 184, 1, // Opcode: UMLALv4i16_indexed +/* 27790 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27829 +/* 27794 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 27797 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27810 +/* 27801 */ MCD_OPC_CheckPredicate, 0, 36, 50, // Skip to: 40641 +/* 27805 */ MCD_OPC_Decode, 247, 10, 182, 1, // Opcode: SMLALv8i16_indexed +/* 27810 */ MCD_OPC_FilterValue, 1, 27, 50, // Skip to: 40641 +/* 27814 */ MCD_OPC_CheckPredicate, 0, 23, 50, // Skip to: 40641 +/* 27818 */ MCD_OPC_CheckField, 11, 1, 0, 17, 50, // Skip to: 40641 +/* 27824 */ MCD_OPC_Decode, 248, 12, 181, 1, // Opcode: SRSHRv2i64_shift +/* 27829 */ MCD_OPC_FilterValue, 3, 8, 50, // Skip to: 40641 +/* 27833 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 27836 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27849 +/* 27840 */ MCD_OPC_CheckPredicate, 0, 253, 49, // Skip to: 40641 +/* 27844 */ MCD_OPC_Decode, 238, 16, 182, 1, // Opcode: UMLALv8i16_indexed +/* 27849 */ MCD_OPC_FilterValue, 1, 244, 49, // Skip to: 40641 +/* 27853 */ MCD_OPC_CheckPredicate, 0, 240, 49, // Skip to: 40641 +/* 27857 */ MCD_OPC_CheckField, 11, 1, 0, 234, 49, // Skip to: 40641 +/* 27863 */ MCD_OPC_Decode, 240, 17, 181, 1, // Opcode: URSHRv2i64_shift +/* 27868 */ MCD_OPC_FilterValue, 3, 80, 0, // Skip to: 27952 +/* 27872 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 27875 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27894 +/* 27879 */ MCD_OPC_CheckPredicate, 0, 214, 49, // Skip to: 40641 +/* 27883 */ MCD_OPC_CheckField, 10, 1, 0, 208, 49, // Skip to: 40641 +/* 27889 */ MCD_OPC_Decode, 177, 11, 184, 1, // Opcode: SQDMLALv4i16_indexed +/* 27894 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27933 +/* 27898 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 27901 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27914 +/* 27905 */ MCD_OPC_CheckPredicate, 0, 188, 49, // Skip to: 40641 +/* 27909 */ MCD_OPC_Decode, 181, 11, 182, 1, // Opcode: SQDMLALv8i16_indexed +/* 27914 */ MCD_OPC_FilterValue, 1, 179, 49, // Skip to: 40641 +/* 27918 */ MCD_OPC_CheckPredicate, 0, 175, 49, // Skip to: 40641 +/* 27922 */ MCD_OPC_CheckField, 11, 1, 0, 169, 49, // Skip to: 40641 +/* 27928 */ MCD_OPC_Decode, 128, 13, 183, 1, // Opcode: SRSRAv2i64_shift +/* 27933 */ MCD_OPC_FilterValue, 3, 160, 49, // Skip to: 40641 +/* 27937 */ MCD_OPC_CheckPredicate, 0, 156, 49, // Skip to: 40641 +/* 27941 */ MCD_OPC_CheckField, 10, 2, 1, 150, 49, // Skip to: 40641 +/* 27947 */ MCD_OPC_Decode, 250, 17, 183, 1, // Opcode: URSRAv2i64_shift +/* 27952 */ MCD_OPC_FilterValue, 4, 61, 0, // Skip to: 28017 +/* 27956 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 27959 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 27992 +/* 27963 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 27966 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27979 +/* 27970 */ MCD_OPC_CheckPredicate, 0, 123, 49, // Skip to: 40641 +/* 27974 */ MCD_OPC_Decode, 196, 8, 180, 1, // Opcode: MLSv4i16_indexed +/* 27979 */ MCD_OPC_FilterValue, 3, 114, 49, // Skip to: 40641 +/* 27983 */ MCD_OPC_CheckPredicate, 0, 110, 49, // Skip to: 40641 +/* 27987 */ MCD_OPC_Decode, 200, 8, 182, 1, // Opcode: MLSv8i16_indexed +/* 27992 */ MCD_OPC_FilterValue, 1, 101, 49, // Skip to: 40641 +/* 27996 */ MCD_OPC_CheckPredicate, 0, 97, 49, // Skip to: 40641 +/* 28000 */ MCD_OPC_CheckField, 29, 3, 3, 91, 49, // Skip to: 40641 +/* 28006 */ MCD_OPC_CheckField, 11, 1, 0, 85, 49, // Skip to: 40641 +/* 28012 */ MCD_OPC_Decode, 232, 12, 183, 1, // Opcode: SRIv2i64_shift +/* 28017 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28062 +/* 28021 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28024 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28043 +/* 28028 */ MCD_OPC_CheckPredicate, 0, 65, 49, // Skip to: 40641 +/* 28032 */ MCD_OPC_CheckField, 10, 2, 1, 59, 49, // Skip to: 40641 +/* 28038 */ MCD_OPC_Decode, 179, 10, 185, 1, // Opcode: SHLv2i64_shift +/* 28043 */ MCD_OPC_FilterValue, 3, 50, 49, // Skip to: 40641 +/* 28047 */ MCD_OPC_CheckPredicate, 0, 46, 49, // Skip to: 40641 +/* 28051 */ MCD_OPC_CheckField, 10, 2, 1, 40, 49, // Skip to: 40641 +/* 28057 */ MCD_OPC_Decode, 199, 10, 186, 1, // Opcode: SLIv2i64_shift +/* 28062 */ MCD_OPC_FilterValue, 6, 99, 0, // Skip to: 28165 +/* 28066 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28069 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28088 +/* 28073 */ MCD_OPC_CheckPredicate, 0, 20, 49, // Skip to: 40641 +/* 28077 */ MCD_OPC_CheckField, 10, 1, 0, 14, 49, // Skip to: 40641 +/* 28083 */ MCD_OPC_Decode, 253, 10, 184, 1, // Opcode: SMLSLv4i16_indexed +/* 28088 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28107 +/* 28092 */ MCD_OPC_CheckPredicate, 0, 1, 49, // Skip to: 40641 +/* 28096 */ MCD_OPC_CheckField, 10, 1, 0, 251, 48, // Skip to: 40641 +/* 28102 */ MCD_OPC_Decode, 244, 16, 184, 1, // Opcode: UMLSLv4i16_indexed +/* 28107 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28126 +/* 28111 */ MCD_OPC_CheckPredicate, 0, 238, 48, // Skip to: 40641 +/* 28115 */ MCD_OPC_CheckField, 10, 1, 0, 232, 48, // Skip to: 40641 +/* 28121 */ MCD_OPC_Decode, 129, 11, 182, 1, // Opcode: SMLSLv8i16_indexed +/* 28126 */ MCD_OPC_FilterValue, 3, 223, 48, // Skip to: 40641 +/* 28130 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 28133 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28146 +/* 28137 */ MCD_OPC_CheckPredicate, 0, 212, 48, // Skip to: 40641 +/* 28141 */ MCD_OPC_Decode, 248, 16, 182, 1, // Opcode: UMLSLv8i16_indexed +/* 28146 */ MCD_OPC_FilterValue, 1, 203, 48, // Skip to: 40641 +/* 28150 */ MCD_OPC_CheckPredicate, 0, 199, 48, // Skip to: 40641 +/* 28154 */ MCD_OPC_CheckField, 11, 1, 0, 193, 48, // Skip to: 40641 +/* 28160 */ MCD_OPC_Decode, 149, 12, 185, 1, // Opcode: SQSHLUv2i64_shift +/* 28165 */ MCD_OPC_FilterValue, 7, 80, 0, // Skip to: 28249 +/* 28169 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28172 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28191 +/* 28176 */ MCD_OPC_CheckPredicate, 0, 173, 48, // Skip to: 40641 +/* 28180 */ MCD_OPC_CheckField, 10, 1, 0, 167, 48, // Skip to: 40641 +/* 28186 */ MCD_OPC_Decode, 189, 11, 184, 1, // Opcode: SQDMLSLv4i16_indexed +/* 28191 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 28230 +/* 28195 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 28198 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28211 +/* 28202 */ MCD_OPC_CheckPredicate, 0, 147, 48, // Skip to: 40641 +/* 28206 */ MCD_OPC_Decode, 193, 11, 182, 1, // Opcode: SQDMLSLv8i16_indexed +/* 28211 */ MCD_OPC_FilterValue, 1, 138, 48, // Skip to: 40641 +/* 28215 */ MCD_OPC_CheckPredicate, 0, 134, 48, // Skip to: 40641 +/* 28219 */ MCD_OPC_CheckField, 11, 1, 0, 128, 48, // Skip to: 40641 +/* 28225 */ MCD_OPC_Decode, 167, 12, 185, 1, // Opcode: SQSHLv2i64_shift +/* 28230 */ MCD_OPC_FilterValue, 3, 119, 48, // Skip to: 40641 +/* 28234 */ MCD_OPC_CheckPredicate, 0, 115, 48, // Skip to: 40641 +/* 28238 */ MCD_OPC_CheckField, 10, 2, 1, 109, 48, // Skip to: 40641 +/* 28244 */ MCD_OPC_Decode, 183, 17, 185, 1, // Opcode: UQSHLv2i64_shift +/* 28249 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 28294 +/* 28253 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28256 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28275 +/* 28260 */ MCD_OPC_CheckPredicate, 0, 89, 48, // Skip to: 40641 +/* 28264 */ MCD_OPC_CheckField, 10, 1, 0, 83, 48, // Skip to: 40641 +/* 28270 */ MCD_OPC_Decode, 235, 8, 187, 1, // Opcode: MULv4i16_indexed +/* 28275 */ MCD_OPC_FilterValue, 2, 74, 48, // Skip to: 40641 +/* 28279 */ MCD_OPC_CheckPredicate, 0, 70, 48, // Skip to: 40641 +/* 28283 */ MCD_OPC_CheckField, 10, 1, 0, 64, 48, // Skip to: 40641 +/* 28289 */ MCD_OPC_Decode, 239, 8, 188, 1, // Opcode: MULv8i16_indexed +/* 28294 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 28377 +/* 28298 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28301 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28320 +/* 28305 */ MCD_OPC_CheckPredicate, 0, 44, 48, // Skip to: 40641 +/* 28309 */ MCD_OPC_CheckField, 10, 1, 0, 38, 48, // Skip to: 40641 +/* 28315 */ MCD_OPC_Decode, 142, 11, 189, 1, // Opcode: SMULLv4i16_indexed +/* 28320 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28339 +/* 28324 */ MCD_OPC_CheckPredicate, 0, 25, 48, // Skip to: 40641 +/* 28328 */ MCD_OPC_CheckField, 10, 1, 0, 19, 48, // Skip to: 40641 +/* 28334 */ MCD_OPC_Decode, 132, 17, 189, 1, // Opcode: UMULLv4i16_indexed +/* 28339 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28358 +/* 28343 */ MCD_OPC_CheckPredicate, 0, 6, 48, // Skip to: 40641 +/* 28347 */ MCD_OPC_CheckField, 10, 1, 0, 0, 48, // Skip to: 40641 +/* 28353 */ MCD_OPC_Decode, 146, 11, 188, 1, // Opcode: SMULLv8i16_indexed +/* 28358 */ MCD_OPC_FilterValue, 3, 247, 47, // Skip to: 40641 +/* 28362 */ MCD_OPC_CheckPredicate, 0, 243, 47, // Skip to: 40641 +/* 28366 */ MCD_OPC_CheckField, 10, 1, 0, 237, 47, // Skip to: 40641 +/* 28372 */ MCD_OPC_Decode, 136, 17, 188, 1, // Opcode: UMULLv8i16_indexed +/* 28377 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 28422 +/* 28381 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28384 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28403 +/* 28388 */ MCD_OPC_CheckPredicate, 0, 217, 47, // Skip to: 40641 +/* 28392 */ MCD_OPC_CheckField, 10, 1, 0, 211, 47, // Skip to: 40641 +/* 28398 */ MCD_OPC_Decode, 213, 11, 189, 1, // Opcode: SQDMULLv4i16_indexed +/* 28403 */ MCD_OPC_FilterValue, 2, 202, 47, // Skip to: 40641 +/* 28407 */ MCD_OPC_CheckPredicate, 0, 198, 47, // Skip to: 40641 +/* 28411 */ MCD_OPC_CheckField, 10, 1, 0, 192, 47, // Skip to: 40641 +/* 28417 */ MCD_OPC_Decode, 217, 11, 188, 1, // Opcode: SQDMULLv8i16_indexed +/* 28422 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 28467 +/* 28426 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28429 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28448 +/* 28433 */ MCD_OPC_CheckPredicate, 0, 172, 47, // Skip to: 40641 +/* 28437 */ MCD_OPC_CheckField, 10, 1, 0, 166, 47, // Skip to: 40641 +/* 28443 */ MCD_OPC_Decode, 202, 11, 187, 1, // Opcode: SQDMULHv4i16_indexed +/* 28448 */ MCD_OPC_FilterValue, 2, 157, 47, // Skip to: 40641 +/* 28452 */ MCD_OPC_CheckPredicate, 0, 153, 47, // Skip to: 40641 +/* 28456 */ MCD_OPC_CheckField, 10, 1, 0, 147, 47, // Skip to: 40641 +/* 28462 */ MCD_OPC_Decode, 206, 11, 188, 1, // Opcode: SQDMULHv8i16_indexed +/* 28467 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 28512 +/* 28471 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28474 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28493 +/* 28478 */ MCD_OPC_CheckPredicate, 0, 127, 47, // Skip to: 40641 +/* 28482 */ MCD_OPC_CheckField, 10, 1, 0, 121, 47, // Skip to: 40641 +/* 28488 */ MCD_OPC_Decode, 237, 11, 187, 1, // Opcode: SQRDMULHv4i16_indexed +/* 28493 */ MCD_OPC_FilterValue, 2, 112, 47, // Skip to: 40641 +/* 28497 */ MCD_OPC_CheckPredicate, 0, 108, 47, // Skip to: 40641 +/* 28501 */ MCD_OPC_CheckField, 10, 1, 0, 102, 47, // Skip to: 40641 +/* 28507 */ MCD_OPC_Decode, 241, 11, 188, 1, // Opcode: SQRDMULHv8i16_indexed +/* 28512 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 28557 +/* 28516 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28519 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28538 +/* 28523 */ MCD_OPC_CheckPredicate, 0, 82, 47, // Skip to: 40641 +/* 28527 */ MCD_OPC_CheckField, 10, 2, 1, 76, 47, // Skip to: 40641 +/* 28533 */ MCD_OPC_Decode, 147, 10, 181, 1, // Opcode: SCVTFv2i64_shift +/* 28538 */ MCD_OPC_FilterValue, 3, 67, 47, // Skip to: 40641 +/* 28542 */ MCD_OPC_CheckPredicate, 0, 63, 47, // Skip to: 40641 +/* 28546 */ MCD_OPC_CheckField, 10, 2, 1, 57, 47, // Skip to: 40641 +/* 28552 */ MCD_OPC_Decode, 177, 16, 181, 1, // Opcode: UCVTFv2i64_shift +/* 28557 */ MCD_OPC_FilterValue, 15, 48, 47, // Skip to: 40641 +/* 28561 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28564 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28583 +/* 28568 */ MCD_OPC_CheckPredicate, 0, 37, 47, // Skip to: 40641 +/* 28572 */ MCD_OPC_CheckField, 10, 2, 3, 31, 47, // Skip to: 40641 +/* 28578 */ MCD_OPC_Decode, 251, 3, 181, 1, // Opcode: FCVTZSv2i64_shift +/* 28583 */ MCD_OPC_FilterValue, 3, 22, 47, // Skip to: 40641 +/* 28587 */ MCD_OPC_CheckPredicate, 0, 18, 47, // Skip to: 40641 +/* 28591 */ MCD_OPC_CheckField, 10, 2, 3, 12, 47, // Skip to: 40641 +/* 28597 */ MCD_OPC_Decode, 152, 4, 181, 1, // Opcode: FCVTZUv2i64_shift +/* 28602 */ MCD_OPC_FilterValue, 14, 17, 3, // Skip to: 29391 +/* 28606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 28609 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 28654 +/* 28613 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28616 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28635 +/* 28620 */ MCD_OPC_CheckPredicate, 0, 241, 46, // Skip to: 40641 +/* 28624 */ MCD_OPC_CheckField, 10, 1, 0, 235, 46, // Skip to: 40641 +/* 28630 */ MCD_OPC_Decode, 184, 8, 190, 1, // Opcode: MLAv2i32_indexed +/* 28635 */ MCD_OPC_FilterValue, 3, 226, 46, // Skip to: 40641 +/* 28639 */ MCD_OPC_CheckPredicate, 0, 222, 46, // Skip to: 40641 +/* 28643 */ MCD_OPC_CheckField, 10, 1, 0, 216, 46, // Skip to: 40641 +/* 28649 */ MCD_OPC_Decode, 188, 8, 191, 1, // Opcode: MLAv4i32_indexed +/* 28654 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 28699 +/* 28658 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28661 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28680 +/* 28665 */ MCD_OPC_CheckPredicate, 0, 196, 46, // Skip to: 40641 +/* 28669 */ MCD_OPC_CheckField, 10, 1, 0, 190, 46, // Skip to: 40641 +/* 28675 */ MCD_OPC_Decode, 210, 4, 190, 1, // Opcode: FMLAv2i32_indexed +/* 28680 */ MCD_OPC_FilterValue, 2, 181, 46, // Skip to: 40641 +/* 28684 */ MCD_OPC_CheckPredicate, 0, 177, 46, // Skip to: 40641 +/* 28688 */ MCD_OPC_CheckField, 10, 1, 0, 171, 46, // Skip to: 40641 +/* 28694 */ MCD_OPC_Decode, 213, 4, 191, 1, // Opcode: FMLAv4i32_indexed +/* 28699 */ MCD_OPC_FilterValue, 2, 79, 0, // Skip to: 28782 +/* 28703 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28706 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28725 +/* 28710 */ MCD_OPC_CheckPredicate, 0, 151, 46, // Skip to: 40641 +/* 28714 */ MCD_OPC_CheckField, 10, 1, 0, 145, 46, // Skip to: 40641 +/* 28720 */ MCD_OPC_Decode, 241, 10, 192, 1, // Opcode: SMLALv2i32_indexed +/* 28725 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28744 +/* 28729 */ MCD_OPC_CheckPredicate, 0, 132, 46, // Skip to: 40641 +/* 28733 */ MCD_OPC_CheckField, 10, 1, 0, 126, 46, // Skip to: 40641 +/* 28739 */ MCD_OPC_Decode, 232, 16, 192, 1, // Opcode: UMLALv2i32_indexed +/* 28744 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28763 +/* 28748 */ MCD_OPC_CheckPredicate, 0, 113, 46, // Skip to: 40641 +/* 28752 */ MCD_OPC_CheckField, 10, 1, 0, 107, 46, // Skip to: 40641 +/* 28758 */ MCD_OPC_Decode, 245, 10, 191, 1, // Opcode: SMLALv4i32_indexed +/* 28763 */ MCD_OPC_FilterValue, 3, 98, 46, // Skip to: 40641 +/* 28767 */ MCD_OPC_CheckPredicate, 0, 94, 46, // Skip to: 40641 +/* 28771 */ MCD_OPC_CheckField, 10, 1, 0, 88, 46, // Skip to: 40641 +/* 28777 */ MCD_OPC_Decode, 236, 16, 191, 1, // Opcode: UMLALv4i32_indexed +/* 28782 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 28827 +/* 28786 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28789 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28808 +/* 28793 */ MCD_OPC_CheckPredicate, 0, 68, 46, // Skip to: 40641 +/* 28797 */ MCD_OPC_CheckField, 10, 1, 0, 62, 46, // Skip to: 40641 +/* 28803 */ MCD_OPC_Decode, 175, 11, 192, 1, // Opcode: SQDMLALv2i32_indexed +/* 28808 */ MCD_OPC_FilterValue, 2, 53, 46, // Skip to: 40641 +/* 28812 */ MCD_OPC_CheckPredicate, 0, 49, 46, // Skip to: 40641 +/* 28816 */ MCD_OPC_CheckField, 10, 1, 0, 43, 46, // Skip to: 40641 +/* 28822 */ MCD_OPC_Decode, 179, 11, 191, 1, // Opcode: SQDMLALv4i32_indexed +/* 28827 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 28872 +/* 28831 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28834 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28853 +/* 28838 */ MCD_OPC_CheckPredicate, 0, 23, 46, // Skip to: 40641 +/* 28842 */ MCD_OPC_CheckField, 10, 1, 0, 17, 46, // Skip to: 40641 +/* 28848 */ MCD_OPC_Decode, 194, 8, 190, 1, // Opcode: MLSv2i32_indexed +/* 28853 */ MCD_OPC_FilterValue, 3, 8, 46, // Skip to: 40641 +/* 28857 */ MCD_OPC_CheckPredicate, 0, 4, 46, // Skip to: 40641 +/* 28861 */ MCD_OPC_CheckField, 10, 1, 0, 254, 45, // Skip to: 40641 +/* 28867 */ MCD_OPC_Decode, 198, 8, 191, 1, // Opcode: MLSv4i32_indexed +/* 28872 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28917 +/* 28876 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28879 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28898 +/* 28883 */ MCD_OPC_CheckPredicate, 0, 234, 45, // Skip to: 40641 +/* 28887 */ MCD_OPC_CheckField, 10, 1, 0, 228, 45, // Skip to: 40641 +/* 28893 */ MCD_OPC_Decode, 218, 4, 190, 1, // Opcode: FMLSv2i32_indexed +/* 28898 */ MCD_OPC_FilterValue, 2, 219, 45, // Skip to: 40641 +/* 28902 */ MCD_OPC_CheckPredicate, 0, 215, 45, // Skip to: 40641 +/* 28906 */ MCD_OPC_CheckField, 10, 1, 0, 209, 45, // Skip to: 40641 +/* 28912 */ MCD_OPC_Decode, 221, 4, 191, 1, // Opcode: FMLSv4i32_indexed +/* 28917 */ MCD_OPC_FilterValue, 6, 79, 0, // Skip to: 29000 +/* 28921 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28924 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28943 +/* 28928 */ MCD_OPC_CheckPredicate, 0, 189, 45, // Skip to: 40641 +/* 28932 */ MCD_OPC_CheckField, 10, 1, 0, 183, 45, // Skip to: 40641 +/* 28938 */ MCD_OPC_Decode, 251, 10, 192, 1, // Opcode: SMLSLv2i32_indexed +/* 28943 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28962 +/* 28947 */ MCD_OPC_CheckPredicate, 0, 170, 45, // Skip to: 40641 +/* 28951 */ MCD_OPC_CheckField, 10, 1, 0, 164, 45, // Skip to: 40641 +/* 28957 */ MCD_OPC_Decode, 242, 16, 192, 1, // Opcode: UMLSLv2i32_indexed +/* 28962 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28981 +/* 28966 */ MCD_OPC_CheckPredicate, 0, 151, 45, // Skip to: 40641 +/* 28970 */ MCD_OPC_CheckField, 10, 1, 0, 145, 45, // Skip to: 40641 +/* 28976 */ MCD_OPC_Decode, 255, 10, 191, 1, // Opcode: SMLSLv4i32_indexed +/* 28981 */ MCD_OPC_FilterValue, 3, 136, 45, // Skip to: 40641 +/* 28985 */ MCD_OPC_CheckPredicate, 0, 132, 45, // Skip to: 40641 +/* 28989 */ MCD_OPC_CheckField, 10, 1, 0, 126, 45, // Skip to: 40641 +/* 28995 */ MCD_OPC_Decode, 246, 16, 191, 1, // Opcode: UMLSLv4i32_indexed +/* 29000 */ MCD_OPC_FilterValue, 7, 41, 0, // Skip to: 29045 +/* 29004 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29007 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29026 +/* 29011 */ MCD_OPC_CheckPredicate, 0, 106, 45, // Skip to: 40641 +/* 29015 */ MCD_OPC_CheckField, 10, 1, 0, 100, 45, // Skip to: 40641 +/* 29021 */ MCD_OPC_Decode, 187, 11, 192, 1, // Opcode: SQDMLSLv2i32_indexed +/* 29026 */ MCD_OPC_FilterValue, 2, 91, 45, // Skip to: 40641 +/* 29030 */ MCD_OPC_CheckPredicate, 0, 87, 45, // Skip to: 40641 +/* 29034 */ MCD_OPC_CheckField, 10, 1, 0, 81, 45, // Skip to: 40641 +/* 29040 */ MCD_OPC_Decode, 191, 11, 191, 1, // Opcode: SQDMLSLv4i32_indexed +/* 29045 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 29090 +/* 29049 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29052 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29071 +/* 29056 */ MCD_OPC_CheckPredicate, 0, 61, 45, // Skip to: 40641 +/* 29060 */ MCD_OPC_CheckField, 10, 1, 0, 55, 45, // Skip to: 40641 +/* 29066 */ MCD_OPC_Decode, 233, 8, 193, 1, // Opcode: MULv2i32_indexed +/* 29071 */ MCD_OPC_FilterValue, 2, 46, 45, // Skip to: 40641 +/* 29075 */ MCD_OPC_CheckPredicate, 0, 42, 45, // Skip to: 40641 +/* 29079 */ MCD_OPC_CheckField, 10, 1, 0, 36, 45, // Skip to: 40641 +/* 29085 */ MCD_OPC_Decode, 237, 8, 194, 1, // Opcode: MULv4i32_indexed +/* 29090 */ MCD_OPC_FilterValue, 9, 79, 0, // Skip to: 29173 +/* 29094 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29097 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29116 +/* 29101 */ MCD_OPC_CheckPredicate, 0, 16, 45, // Skip to: 40641 +/* 29105 */ MCD_OPC_CheckField, 10, 1, 0, 10, 45, // Skip to: 40641 +/* 29111 */ MCD_OPC_Decode, 253, 4, 193, 1, // Opcode: FMULv2i32_indexed +/* 29116 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29135 +/* 29120 */ MCD_OPC_CheckPredicate, 0, 253, 44, // Skip to: 40641 +/* 29124 */ MCD_OPC_CheckField, 10, 1, 0, 247, 44, // Skip to: 40641 +/* 29130 */ MCD_OPC_Decode, 245, 4, 193, 1, // Opcode: FMULXv2i32_indexed +/* 29135 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29154 +/* 29139 */ MCD_OPC_CheckPredicate, 0, 234, 44, // Skip to: 40641 +/* 29143 */ MCD_OPC_CheckField, 10, 1, 0, 228, 44, // Skip to: 40641 +/* 29149 */ MCD_OPC_Decode, 128, 5, 194, 1, // Opcode: FMULv4i32_indexed +/* 29154 */ MCD_OPC_FilterValue, 3, 219, 44, // Skip to: 40641 +/* 29158 */ MCD_OPC_CheckPredicate, 0, 215, 44, // Skip to: 40641 +/* 29162 */ MCD_OPC_CheckField, 10, 1, 0, 209, 44, // Skip to: 40641 +/* 29168 */ MCD_OPC_Decode, 248, 4, 194, 1, // Opcode: FMULXv4i32_indexed +/* 29173 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 29256 +/* 29177 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29180 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29199 +/* 29184 */ MCD_OPC_CheckPredicate, 0, 189, 44, // Skip to: 40641 +/* 29188 */ MCD_OPC_CheckField, 10, 1, 0, 183, 44, // Skip to: 40641 +/* 29194 */ MCD_OPC_Decode, 140, 11, 195, 1, // Opcode: SMULLv2i32_indexed +/* 29199 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29218 +/* 29203 */ MCD_OPC_CheckPredicate, 0, 170, 44, // Skip to: 40641 +/* 29207 */ MCD_OPC_CheckField, 10, 1, 0, 164, 44, // Skip to: 40641 +/* 29213 */ MCD_OPC_Decode, 130, 17, 195, 1, // Opcode: UMULLv2i32_indexed +/* 29218 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29237 +/* 29222 */ MCD_OPC_CheckPredicate, 0, 151, 44, // Skip to: 40641 +/* 29226 */ MCD_OPC_CheckField, 10, 1, 0, 145, 44, // Skip to: 40641 +/* 29232 */ MCD_OPC_Decode, 144, 11, 194, 1, // Opcode: SMULLv4i32_indexed +/* 29237 */ MCD_OPC_FilterValue, 3, 136, 44, // Skip to: 40641 +/* 29241 */ MCD_OPC_CheckPredicate, 0, 132, 44, // Skip to: 40641 +/* 29245 */ MCD_OPC_CheckField, 10, 1, 0, 126, 44, // Skip to: 40641 +/* 29251 */ MCD_OPC_Decode, 134, 17, 194, 1, // Opcode: UMULLv4i32_indexed +/* 29256 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 29301 +/* 29260 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29263 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29282 +/* 29267 */ MCD_OPC_CheckPredicate, 0, 106, 44, // Skip to: 40641 +/* 29271 */ MCD_OPC_CheckField, 10, 1, 0, 100, 44, // Skip to: 40641 +/* 29277 */ MCD_OPC_Decode, 211, 11, 195, 1, // Opcode: SQDMULLv2i32_indexed +/* 29282 */ MCD_OPC_FilterValue, 2, 91, 44, // Skip to: 40641 +/* 29286 */ MCD_OPC_CheckPredicate, 0, 87, 44, // Skip to: 40641 +/* 29290 */ MCD_OPC_CheckField, 10, 1, 0, 81, 44, // Skip to: 40641 +/* 29296 */ MCD_OPC_Decode, 215, 11, 194, 1, // Opcode: SQDMULLv4i32_indexed +/* 29301 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 29346 +/* 29305 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29308 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29327 +/* 29312 */ MCD_OPC_CheckPredicate, 0, 61, 44, // Skip to: 40641 +/* 29316 */ MCD_OPC_CheckField, 10, 1, 0, 55, 44, // Skip to: 40641 +/* 29322 */ MCD_OPC_Decode, 200, 11, 193, 1, // Opcode: SQDMULHv2i32_indexed +/* 29327 */ MCD_OPC_FilterValue, 2, 46, 44, // Skip to: 40641 +/* 29331 */ MCD_OPC_CheckPredicate, 0, 42, 44, // Skip to: 40641 +/* 29335 */ MCD_OPC_CheckField, 10, 1, 0, 36, 44, // Skip to: 40641 +/* 29341 */ MCD_OPC_Decode, 204, 11, 194, 1, // Opcode: SQDMULHv4i32_indexed +/* 29346 */ MCD_OPC_FilterValue, 13, 27, 44, // Skip to: 40641 +/* 29350 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29353 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29372 +/* 29357 */ MCD_OPC_CheckPredicate, 0, 16, 44, // Skip to: 40641 +/* 29361 */ MCD_OPC_CheckField, 10, 1, 0, 10, 44, // Skip to: 40641 +/* 29367 */ MCD_OPC_Decode, 235, 11, 193, 1, // Opcode: SQRDMULHv2i32_indexed +/* 29372 */ MCD_OPC_FilterValue, 2, 1, 44, // Skip to: 40641 +/* 29376 */ MCD_OPC_CheckPredicate, 0, 253, 43, // Skip to: 40641 +/* 29380 */ MCD_OPC_CheckField, 10, 1, 0, 247, 43, // Skip to: 40641 +/* 29386 */ MCD_OPC_Decode, 239, 11, 194, 1, // Opcode: SQRDMULHv4i32_indexed +/* 29391 */ MCD_OPC_FilterValue, 15, 238, 43, // Skip to: 40641 +/* 29395 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 29398 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 29429 +/* 29402 */ MCD_OPC_CheckPredicate, 0, 227, 43, // Skip to: 40641 +/* 29406 */ MCD_OPC_CheckField, 29, 3, 2, 221, 43, // Skip to: 40641 +/* 29412 */ MCD_OPC_CheckField, 21, 1, 0, 215, 43, // Skip to: 40641 +/* 29418 */ MCD_OPC_CheckField, 10, 1, 0, 209, 43, // Skip to: 40641 +/* 29424 */ MCD_OPC_Decode, 211, 4, 196, 1, // Opcode: FMLAv2i64_indexed +/* 29429 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 29460 +/* 29433 */ MCD_OPC_CheckPredicate, 0, 196, 43, // Skip to: 40641 +/* 29437 */ MCD_OPC_CheckField, 29, 3, 2, 190, 43, // Skip to: 40641 +/* 29443 */ MCD_OPC_CheckField, 21, 1, 0, 184, 43, // Skip to: 40641 +/* 29449 */ MCD_OPC_CheckField, 10, 1, 0, 178, 43, // Skip to: 40641 +/* 29455 */ MCD_OPC_Decode, 219, 4, 196, 1, // Opcode: FMLSv2i64_indexed +/* 29460 */ MCD_OPC_FilterValue, 9, 169, 43, // Skip to: 40641 +/* 29464 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29467 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 29492 +/* 29471 */ MCD_OPC_CheckPredicate, 0, 158, 43, // Skip to: 40641 +/* 29475 */ MCD_OPC_CheckField, 21, 1, 0, 152, 43, // Skip to: 40641 +/* 29481 */ MCD_OPC_CheckField, 10, 1, 0, 146, 43, // Skip to: 40641 +/* 29487 */ MCD_OPC_Decode, 254, 4, 197, 1, // Opcode: FMULv2i64_indexed +/* 29492 */ MCD_OPC_FilterValue, 3, 137, 43, // Skip to: 40641 +/* 29496 */ MCD_OPC_CheckPredicate, 0, 133, 43, // Skip to: 40641 +/* 29500 */ MCD_OPC_CheckField, 21, 1, 0, 127, 43, // Skip to: 40641 +/* 29506 */ MCD_OPC_CheckField, 10, 1, 0, 121, 43, // Skip to: 40641 +/* 29512 */ MCD_OPC_Decode, 246, 4, 197, 1, // Opcode: FMULXv2i64_indexed +/* 29517 */ MCD_OPC_FilterValue, 4, 191, 1, // Skip to: 29968 +/* 29521 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29524 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 29547 +/* 29528 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... +/* 29531 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29539 +/* 29535 */ MCD_OPC_Decode, 81, 198, 1, // Opcode: ADR +/* 29539 */ MCD_OPC_FilterValue, 1, 90, 43, // Skip to: 40641 +/* 29543 */ MCD_OPC_Decode, 82, 198, 1, // Opcode: ADRP +/* 29547 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 29622 +/* 29551 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29554 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29562 +/* 29558 */ MCD_OPC_Decode, 62, 199, 1, // Opcode: ADDWri +/* 29562 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 29570 +/* 29566 */ MCD_OPC_Decode, 48, 199, 1, // Opcode: ADDSWri +/* 29570 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 29579 +/* 29574 */ MCD_OPC_Decode, 166, 15, 199, 1, // Opcode: SUBWri +/* 29579 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 29588 +/* 29583 */ MCD_OPC_Decode, 157, 15, 199, 1, // Opcode: SUBSWri +/* 29588 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 29596 +/* 29592 */ MCD_OPC_Decode, 66, 199, 1, // Opcode: ADDXri +/* 29596 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 29604 +/* 29600 */ MCD_OPC_Decode, 52, 199, 1, // Opcode: ADDSXri +/* 29604 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 29613 +/* 29608 */ MCD_OPC_Decode, 170, 15, 199, 1, // Opcode: SUBXri +/* 29613 */ MCD_OPC_FilterValue, 7, 16, 43, // Skip to: 40641 +/* 29617 */ MCD_OPC_Decode, 161, 15, 199, 1, // Opcode: SUBSXri +/* 29622 */ MCD_OPC_FilterValue, 2, 197, 0, // Skip to: 29823 +/* 29626 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29629 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 29659 +/* 29633 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29650 +/* 29640 */ MCD_OPC_CheckField, 22, 1, 0, 243, 42, // Skip to: 40641 +/* 29646 */ MCD_OPC_Decode, 93, 200, 1, // Opcode: ANDWri +/* 29650 */ MCD_OPC_FilterValue, 1, 235, 42, // Skip to: 40641 +/* 29654 */ MCD_OPC_Decode, 214, 8, 201, 1, // Opcode: MOVNWi +/* 29659 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 29674 +/* 29663 */ MCD_OPC_CheckField, 22, 2, 0, 220, 42, // Skip to: 40641 +/* 29669 */ MCD_OPC_Decode, 135, 9, 200, 1, // Opcode: ORRWri +/* 29674 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 29705 +/* 29678 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29681 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29696 +/* 29685 */ MCD_OPC_CheckField, 22, 1, 0, 198, 42, // Skip to: 40641 +/* 29691 */ MCD_OPC_Decode, 166, 2, 200, 1, // Opcode: EORWri +/* 29696 */ MCD_OPC_FilterValue, 1, 189, 42, // Skip to: 40641 +/* 29700 */ MCD_OPC_Decode, 216, 8, 201, 1, // Opcode: MOVZWi +/* 29705 */ MCD_OPC_FilterValue, 3, 26, 0, // Skip to: 29735 +/* 29709 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29712 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29726 +/* 29716 */ MCD_OPC_CheckField, 22, 1, 0, 167, 42, // Skip to: 40641 +/* 29722 */ MCD_OPC_Decode, 87, 200, 1, // Opcode: ANDSWri +/* 29726 */ MCD_OPC_FilterValue, 1, 159, 42, // Skip to: 40641 +/* 29730 */ MCD_OPC_Decode, 212, 8, 201, 1, // Opcode: MOVKWi +/* 29735 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 29759 +/* 29739 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29742 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29750 +/* 29746 */ MCD_OPC_Decode, 96, 200, 1, // Opcode: ANDXri +/* 29750 */ MCD_OPC_FilterValue, 1, 135, 42, // Skip to: 40641 +/* 29754 */ MCD_OPC_Decode, 215, 8, 201, 1, // Opcode: MOVNXi +/* 29759 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 29774 +/* 29763 */ MCD_OPC_CheckField, 23, 1, 0, 120, 42, // Skip to: 40641 +/* 29769 */ MCD_OPC_Decode, 138, 9, 200, 1, // Opcode: ORRXri +/* 29774 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 29799 +/* 29778 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29781 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29790 +/* 29785 */ MCD_OPC_Decode, 169, 2, 200, 1, // Opcode: EORXri +/* 29790 */ MCD_OPC_FilterValue, 1, 95, 42, // Skip to: 40641 +/* 29794 */ MCD_OPC_Decode, 217, 8, 201, 1, // Opcode: MOVZXi +/* 29799 */ MCD_OPC_FilterValue, 7, 86, 42, // Skip to: 40641 +/* 29803 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 29806 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29814 +/* 29810 */ MCD_OPC_Decode, 90, 200, 1, // Opcode: ANDSXri +/* 29814 */ MCD_OPC_FilterValue, 1, 71, 42, // Skip to: 40641 +/* 29818 */ MCD_OPC_Decode, 213, 8, 201, 1, // Opcode: MOVKXi +/* 29823 */ MCD_OPC_FilterValue, 3, 62, 42, // Skip to: 40641 +/* 29827 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29830 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 29867 +/* 29834 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 29837 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29852 +/* 29841 */ MCD_OPC_CheckField, 15, 1, 0, 42, 42, // Skip to: 40641 +/* 29847 */ MCD_OPC_Decode, 130, 10, 202, 1, // Opcode: SBFMWri +/* 29852 */ MCD_OPC_FilterValue, 4, 33, 42, // Skip to: 40641 +/* 29856 */ MCD_OPC_CheckField, 15, 1, 0, 27, 42, // Skip to: 40641 +/* 29862 */ MCD_OPC_Decode, 175, 2, 203, 1, // Opcode: EXTRWrri +/* 29867 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 29887 +/* 29871 */ MCD_OPC_CheckField, 21, 3, 0, 12, 42, // Skip to: 40641 +/* 29877 */ MCD_OPC_CheckField, 15, 1, 0, 6, 42, // Skip to: 40641 +/* 29883 */ MCD_OPC_Decode, 104, 204, 1, // Opcode: BFMWri +/* 29887 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 29908 +/* 29891 */ MCD_OPC_CheckField, 21, 3, 0, 248, 41, // Skip to: 40641 +/* 29897 */ MCD_OPC_CheckField, 15, 1, 0, 242, 41, // Skip to: 40641 +/* 29903 */ MCD_OPC_Decode, 160, 16, 202, 1, // Opcode: UBFMWri +/* 29908 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 29939 +/* 29912 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 29915 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29924 +/* 29919 */ MCD_OPC_Decode, 131, 10, 205, 1, // Opcode: SBFMXri +/* 29924 */ MCD_OPC_FilterValue, 3, 217, 41, // Skip to: 40641 +/* 29928 */ MCD_OPC_CheckField, 21, 1, 0, 211, 41, // Skip to: 40641 +/* 29934 */ MCD_OPC_Decode, 176, 2, 206, 1, // Opcode: EXTRXrri +/* 29939 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 29953 +/* 29943 */ MCD_OPC_CheckField, 22, 2, 1, 196, 41, // Skip to: 40641 +/* 29949 */ MCD_OPC_Decode, 105, 207, 1, // Opcode: BFMXri +/* 29953 */ MCD_OPC_FilterValue, 6, 188, 41, // Skip to: 40641 +/* 29957 */ MCD_OPC_CheckField, 22, 2, 1, 182, 41, // Skip to: 40641 +/* 29963 */ MCD_OPC_Decode, 161, 16, 205, 1, // Opcode: UBFMXri +/* 29968 */ MCD_OPC_FilterValue, 5, 218, 1, // Skip to: 30446 +/* 29972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 29975 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29983 +/* 29979 */ MCD_OPC_Decode, 103, 208, 1, // Opcode: B +/* 29983 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 30026 +/* 29987 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29990 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29999 +/* 29994 */ MCD_OPC_Decode, 133, 1, 209, 1, // Opcode: CBZW +/* 29999 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30008 +/* 30003 */ MCD_OPC_Decode, 131, 1, 209, 1, // Opcode: CBNZW +/* 30008 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30017 +/* 30012 */ MCD_OPC_Decode, 215, 15, 210, 1, // Opcode: TBZW +/* 30017 */ MCD_OPC_FilterValue, 3, 124, 41, // Skip to: 40641 +/* 30021 */ MCD_OPC_Decode, 205, 15, 210, 1, // Opcode: TBNZW +/* 30026 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 30047 +/* 30030 */ MCD_OPC_CheckField, 24, 2, 0, 109, 41, // Skip to: 40641 +/* 30036 */ MCD_OPC_CheckField, 4, 1, 0, 103, 41, // Skip to: 40641 +/* 30042 */ MCD_OPC_Decode, 130, 1, 211, 1, // Opcode: Bcc +/* 30047 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 30055 +/* 30051 */ MCD_OPC_Decode, 124, 208, 1, // Opcode: BL +/* 30055 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 30098 +/* 30059 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30062 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30071 +/* 30066 */ MCD_OPC_Decode, 134, 1, 212, 1, // Opcode: CBZX +/* 30071 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30080 +/* 30075 */ MCD_OPC_Decode, 132, 1, 212, 1, // Opcode: CBNZX +/* 30080 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30089 +/* 30084 */ MCD_OPC_Decode, 216, 15, 210, 1, // Opcode: TBZX +/* 30089 */ MCD_OPC_FilterValue, 3, 52, 41, // Skip to: 40641 +/* 30093 */ MCD_OPC_Decode, 206, 15, 210, 1, // Opcode: TBNZX +/* 30098 */ MCD_OPC_FilterValue, 6, 43, 41, // Skip to: 40641 +/* 30102 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 30105 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 30139 +/* 30109 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 30112 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30121 +/* 30116 */ MCD_OPC_Decode, 194, 15, 213, 1, // Opcode: SVC +/* 30121 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30130 +/* 30125 */ MCD_OPC_Decode, 209, 5, 213, 1, // Opcode: HVC +/* 30130 */ MCD_OPC_FilterValue, 3, 11, 41, // Skip to: 40641 +/* 30134 */ MCD_OPC_Decode, 222, 10, 213, 1, // Opcode: SMC +/* 30139 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 30153 +/* 30143 */ MCD_OPC_CheckField, 0, 5, 0, 252, 40, // Skip to: 40641 +/* 30149 */ MCD_OPC_Decode, 127, 213, 1, // Opcode: BRK +/* 30153 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 30168 +/* 30157 */ MCD_OPC_CheckField, 0, 5, 0, 238, 40, // Skip to: 40641 +/* 30163 */ MCD_OPC_Decode, 208, 5, 213, 1, // Opcode: HLT +/* 30168 */ MCD_OPC_FilterValue, 5, 30, 0, // Skip to: 30202 +/* 30172 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 30175 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30184 +/* 30179 */ MCD_OPC_Decode, 142, 2, 213, 1, // Opcode: DCPS1 +/* 30184 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30193 +/* 30188 */ MCD_OPC_Decode, 143, 2, 213, 1, // Opcode: DCPS2 +/* 30193 */ MCD_OPC_FilterValue, 3, 204, 40, // Skip to: 40641 +/* 30197 */ MCD_OPC_Decode, 144, 2, 213, 1, // Opcode: DCPS3 +/* 30202 */ MCD_OPC_FilterValue, 8, 122, 0, // Skip to: 30328 +/* 30206 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 30209 */ MCD_OPC_FilterValue, 95, 11, 0, // Skip to: 30224 +/* 30213 */ MCD_OPC_CheckField, 12, 9, 51, 53, 0, // Skip to: 30272 +/* 30219 */ MCD_OPC_Decode, 143, 1, 214, 1, // Opcode: CLREX +/* 30224 */ MCD_OPC_FilterValue, 159, 1, 11, 0, // Skip to: 30240 +/* 30229 */ MCD_OPC_CheckField, 12, 9, 51, 37, 0, // Skip to: 30272 +/* 30235 */ MCD_OPC_Decode, 147, 2, 214, 1, // Opcode: DSB +/* 30240 */ MCD_OPC_FilterValue, 191, 1, 11, 0, // Skip to: 30256 +/* 30245 */ MCD_OPC_CheckField, 12, 9, 51, 21, 0, // Skip to: 30272 +/* 30251 */ MCD_OPC_Decode, 145, 2, 214, 1, // Opcode: DMB +/* 30256 */ MCD_OPC_FilterValue, 223, 1, 11, 0, // Skip to: 30272 +/* 30261 */ MCD_OPC_CheckField, 12, 9, 51, 5, 0, // Skip to: 30272 +/* 30267 */ MCD_OPC_Decode, 218, 5, 214, 1, // Opcode: ISB +/* 30272 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 30275 */ MCD_OPC_FilterValue, 31, 33, 0, // Skip to: 30312 +/* 30279 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 30282 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 30297 +/* 30286 */ MCD_OPC_CheckField, 16, 5, 3, 20, 0, // Skip to: 30312 +/* 30292 */ MCD_OPC_Decode, 207, 5, 215, 1, // Opcode: HINT +/* 30297 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 30312 +/* 30301 */ MCD_OPC_CheckField, 19, 2, 0, 5, 0, // Skip to: 30312 +/* 30307 */ MCD_OPC_Decode, 228, 8, 216, 1, // Opcode: MSRpstate +/* 30312 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, // Skip to: 30323 +/* 30318 */ MCD_OPC_Decode, 196, 15, 217, 1, // Opcode: SYSxt +/* 30323 */ MCD_OPC_Decode, 227, 8, 218, 1, // Opcode: MSR +/* 30328 */ MCD_OPC_FilterValue, 9, 16, 0, // Skip to: 30348 +/* 30332 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, // Skip to: 30343 +/* 30338 */ MCD_OPC_Decode, 195, 15, 219, 1, // Opcode: SYSLxt +/* 30343 */ MCD_OPC_Decode, 226, 8, 220, 1, // Opcode: MRS +/* 30348 */ MCD_OPC_FilterValue, 16, 17, 0, // Skip to: 30369 +/* 30352 */ MCD_OPC_CheckField, 10, 11, 192, 15, 42, 40, // Skip to: 40641 +/* 30359 */ MCD_OPC_CheckField, 0, 5, 0, 36, 40, // Skip to: 40641 +/* 30365 */ MCD_OPC_Decode, 126, 221, 1, // Opcode: BR +/* 30369 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 30390 +/* 30373 */ MCD_OPC_CheckField, 10, 11, 192, 15, 21, 40, // Skip to: 40641 +/* 30380 */ MCD_OPC_CheckField, 0, 5, 0, 15, 40, // Skip to: 40641 +/* 30386 */ MCD_OPC_Decode, 125, 221, 1, // Opcode: BLR +/* 30390 */ MCD_OPC_FilterValue, 18, 18, 0, // Skip to: 30412 +/* 30394 */ MCD_OPC_CheckField, 10, 11, 192, 15, 0, 40, // Skip to: 40641 +/* 30401 */ MCD_OPC_CheckField, 0, 5, 0, 250, 39, // Skip to: 40641 +/* 30407 */ MCD_OPC_Decode, 168, 9, 221, 1, // Opcode: RET +/* 30412 */ MCD_OPC_FilterValue, 20, 13, 0, // Skip to: 30429 +/* 30416 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 233, 39, // Skip to: 40641 +/* 30424 */ MCD_OPC_Decode, 174, 2, 222, 1, // Opcode: ERET +/* 30429 */ MCD_OPC_FilterValue, 21, 224, 39, // Skip to: 40641 +/* 30433 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 216, 39, // Skip to: 40641 +/* 30441 */ MCD_OPC_Decode, 146, 2, 222, 1, // Opcode: DRPS +/* 30446 */ MCD_OPC_FilterValue, 6, 54, 10, // Skip to: 33064 +/* 30450 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 30453 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 30754 +/* 30457 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30460 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30469 +/* 30464 */ MCD_OPC_Decode, 134, 8, 209, 1, // Opcode: LDRWl +/* 30469 */ MCD_OPC_FilterValue, 2, 244, 0, // Skip to: 30717 +/* 30473 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 30476 */ MCD_OPC_FilterValue, 0, 68, 0, // Skip to: 30548 +/* 30480 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 30483 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 30497 +/* 30487 */ MCD_OPC_CheckField, 12, 4, 0, 164, 39, // Skip to: 40641 +/* 30493 */ MCD_OPC_Decode, 32, 223, 1, // Opcode: ADCWr +/* 30497 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30506 +/* 30501 */ MCD_OPC_Decode, 134, 2, 224, 1, // Opcode: CSELWr +/* 30506 */ MCD_OPC_FilterValue, 6, 147, 39, // Skip to: 40641 +/* 30510 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 30513 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30522 +/* 30517 */ MCD_OPC_Decode, 176, 8, 223, 1, // Opcode: LSLVWr +/* 30522 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30535 +/* 30526 */ MCD_OPC_CheckPredicate, 2, 127, 39, // Skip to: 40641 +/* 30530 */ MCD_OPC_Decode, 254, 1, 223, 1, // Opcode: CRC32Brr +/* 30535 */ MCD_OPC_FilterValue, 5, 118, 39, // Skip to: 40641 +/* 30539 */ MCD_OPC_CheckPredicate, 2, 114, 39, // Skip to: 40641 +/* 30543 */ MCD_OPC_Decode, 255, 1, 223, 1, // Opcode: CRC32CBrr +/* 30548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 30606 +/* 30552 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 30555 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30564 +/* 30559 */ MCD_OPC_Decode, 136, 2, 224, 1, // Opcode: CSINCWr +/* 30564 */ MCD_OPC_FilterValue, 6, 89, 39, // Skip to: 40641 +/* 30568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 30571 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30580 +/* 30575 */ MCD_OPC_Decode, 178, 8, 223, 1, // Opcode: LSRVWr +/* 30580 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30593 +/* 30584 */ MCD_OPC_CheckPredicate, 2, 69, 39, // Skip to: 40641 +/* 30588 */ MCD_OPC_Decode, 131, 2, 223, 1, // Opcode: CRC32Hrr +/* 30593 */ MCD_OPC_FilterValue, 5, 60, 39, // Skip to: 40641 +/* 30597 */ MCD_OPC_CheckPredicate, 2, 56, 39, // Skip to: 40641 +/* 30601 */ MCD_OPC_Decode, 128, 2, 223, 1, // Opcode: CRC32CHrr +/* 30606 */ MCD_OPC_FilterValue, 2, 70, 0, // Skip to: 30680 +/* 30610 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 30613 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30628 +/* 30617 */ MCD_OPC_CheckField, 21, 3, 6, 34, 39, // Skip to: 40641 +/* 30623 */ MCD_OPC_Decode, 180, 16, 223, 1, // Opcode: UDIVWr +/* 30628 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 30642 +/* 30632 */ MCD_OPC_CheckField, 21, 3, 6, 19, 39, // Skip to: 40641 +/* 30638 */ MCD_OPC_Decode, 101, 223, 1, // Opcode: ASRVWr +/* 30642 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 30661 +/* 30646 */ MCD_OPC_CheckPredicate, 2, 7, 39, // Skip to: 40641 +/* 30650 */ MCD_OPC_CheckField, 21, 3, 6, 1, 39, // Skip to: 40641 +/* 30656 */ MCD_OPC_Decode, 132, 2, 223, 1, // Opcode: CRC32Wrr +/* 30661 */ MCD_OPC_FilterValue, 5, 248, 38, // Skip to: 40641 +/* 30665 */ MCD_OPC_CheckPredicate, 2, 244, 38, // Skip to: 40641 +/* 30669 */ MCD_OPC_CheckField, 21, 3, 6, 238, 38, // Skip to: 40641 +/* 30675 */ MCD_OPC_Decode, 129, 2, 223, 1, // Opcode: CRC32CWrr +/* 30680 */ MCD_OPC_FilterValue, 3, 229, 38, // Skip to: 40641 +/* 30684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 30687 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30702 +/* 30691 */ MCD_OPC_CheckField, 21, 3, 6, 216, 38, // Skip to: 40641 +/* 30697 */ MCD_OPC_Decode, 150, 10, 223, 1, // Opcode: SDIVWr +/* 30702 */ MCD_OPC_FilterValue, 2, 207, 38, // Skip to: 40641 +/* 30706 */ MCD_OPC_CheckField, 21, 3, 6, 201, 38, // Skip to: 40641 +/* 30712 */ MCD_OPC_Decode, 187, 9, 223, 1, // Opcode: RORVWr +/* 30717 */ MCD_OPC_FilterValue, 3, 192, 38, // Skip to: 40641 +/* 30721 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30724 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30739 +/* 30728 */ MCD_OPC_CheckField, 21, 3, 0, 179, 38, // Skip to: 40641 +/* 30734 */ MCD_OPC_Decode, 180, 8, 225, 1, // Opcode: MADDWrrr +/* 30739 */ MCD_OPC_FilterValue, 1, 170, 38, // Skip to: 40641 +/* 30743 */ MCD_OPC_CheckField, 21, 3, 0, 164, 38, // Skip to: 40641 +/* 30749 */ MCD_OPC_Decode, 229, 8, 225, 1, // Opcode: MSUBWrrr +/* 30754 */ MCD_OPC_FilterValue, 1, 224, 1, // Skip to: 31238 +/* 30758 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 30761 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 30854 +/* 30765 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 30768 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30783 +/* 30772 */ MCD_OPC_CheckField, 21, 1, 0, 135, 38, // Skip to: 40641 +/* 30778 */ MCD_OPC_Decode, 136, 15, 226, 1, // Opcode: STURBBi +/* 30783 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30798 +/* 30787 */ MCD_OPC_CheckField, 21, 1, 0, 120, 38, // Skip to: 40641 +/* 30793 */ MCD_OPC_Decode, 215, 14, 226, 1, // Opcode: STRBBpost +/* 30798 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30839 +/* 30802 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30805 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30814 +/* 30809 */ MCD_OPC_Decode, 132, 15, 226, 1, // Opcode: STTRBi +/* 30814 */ MCD_OPC_FilterValue, 1, 95, 38, // Skip to: 40641 +/* 30818 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 30821 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30830 +/* 30825 */ MCD_OPC_Decode, 217, 14, 227, 1, // Opcode: STRBBroW +/* 30830 */ MCD_OPC_FilterValue, 3, 79, 38, // Skip to: 40641 +/* 30834 */ MCD_OPC_Decode, 218, 14, 228, 1, // Opcode: STRBBroX +/* 30839 */ MCD_OPC_FilterValue, 3, 70, 38, // Skip to: 40641 +/* 30843 */ MCD_OPC_CheckField, 21, 1, 0, 64, 38, // Skip to: 40641 +/* 30849 */ MCD_OPC_Decode, 216, 14, 226, 1, // Opcode: STRBBpre +/* 30854 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 30947 +/* 30858 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 30861 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30876 +/* 30865 */ MCD_OPC_CheckField, 21, 1, 0, 42, 38, // Skip to: 40641 +/* 30871 */ MCD_OPC_Decode, 155, 8, 226, 1, // Opcode: LDURBBi +/* 30876 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30891 +/* 30880 */ MCD_OPC_CheckField, 21, 1, 0, 27, 38, // Skip to: 40641 +/* 30886 */ MCD_OPC_Decode, 198, 7, 226, 1, // Opcode: LDRBBpost +/* 30891 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30932 +/* 30895 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30898 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30907 +/* 30902 */ MCD_OPC_Decode, 146, 8, 226, 1, // Opcode: LDTRBi +/* 30907 */ MCD_OPC_FilterValue, 1, 2, 38, // Skip to: 40641 +/* 30911 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 30914 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30923 +/* 30918 */ MCD_OPC_Decode, 200, 7, 227, 1, // Opcode: LDRBBroW +/* 30923 */ MCD_OPC_FilterValue, 3, 242, 37, // Skip to: 40641 +/* 30927 */ MCD_OPC_Decode, 201, 7, 228, 1, // Opcode: LDRBBroX +/* 30932 */ MCD_OPC_FilterValue, 3, 233, 37, // Skip to: 40641 +/* 30936 */ MCD_OPC_CheckField, 21, 1, 0, 227, 37, // Skip to: 40641 +/* 30942 */ MCD_OPC_Decode, 199, 7, 226, 1, // Opcode: LDRBBpre +/* 30947 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31040 +/* 30951 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 30954 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30969 +/* 30958 */ MCD_OPC_CheckField, 21, 1, 0, 205, 37, // Skip to: 40641 +/* 30964 */ MCD_OPC_Decode, 162, 8, 226, 1, // Opcode: LDURSBXi +/* 30969 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30984 +/* 30973 */ MCD_OPC_CheckField, 21, 1, 0, 190, 37, // Skip to: 40641 +/* 30979 */ MCD_OPC_Decode, 235, 7, 226, 1, // Opcode: LDRSBXpost +/* 30984 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31025 +/* 30988 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30991 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31000 +/* 30995 */ MCD_OPC_Decode, 149, 8, 226, 1, // Opcode: LDTRSBXi +/* 31000 */ MCD_OPC_FilterValue, 1, 165, 37, // Skip to: 40641 +/* 31004 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31007 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31016 +/* 31011 */ MCD_OPC_Decode, 237, 7, 229, 1, // Opcode: LDRSBXroW +/* 31016 */ MCD_OPC_FilterValue, 3, 149, 37, // Skip to: 40641 +/* 31020 */ MCD_OPC_Decode, 238, 7, 230, 1, // Opcode: LDRSBXroX +/* 31025 */ MCD_OPC_FilterValue, 3, 140, 37, // Skip to: 40641 +/* 31029 */ MCD_OPC_CheckField, 21, 1, 0, 134, 37, // Skip to: 40641 +/* 31035 */ MCD_OPC_Decode, 236, 7, 226, 1, // Opcode: LDRSBXpre +/* 31040 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31133 +/* 31044 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31047 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31062 +/* 31051 */ MCD_OPC_CheckField, 21, 1, 0, 112, 37, // Skip to: 40641 +/* 31057 */ MCD_OPC_Decode, 161, 8, 226, 1, // Opcode: LDURSBWi +/* 31062 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31077 +/* 31066 */ MCD_OPC_CheckField, 21, 1, 0, 97, 37, // Skip to: 40641 +/* 31072 */ MCD_OPC_Decode, 230, 7, 226, 1, // Opcode: LDRSBWpost +/* 31077 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31118 +/* 31081 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 31084 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31093 +/* 31088 */ MCD_OPC_Decode, 148, 8, 226, 1, // Opcode: LDTRSBWi +/* 31093 */ MCD_OPC_FilterValue, 1, 72, 37, // Skip to: 40641 +/* 31097 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31100 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31109 +/* 31104 */ MCD_OPC_Decode, 232, 7, 227, 1, // Opcode: LDRSBWroW +/* 31109 */ MCD_OPC_FilterValue, 3, 56, 37, // Skip to: 40641 +/* 31113 */ MCD_OPC_Decode, 233, 7, 228, 1, // Opcode: LDRSBWroX +/* 31118 */ MCD_OPC_FilterValue, 3, 47, 37, // Skip to: 40641 +/* 31122 */ MCD_OPC_CheckField, 21, 1, 0, 41, 37, // Skip to: 40641 +/* 31128 */ MCD_OPC_Decode, 231, 7, 226, 1, // Opcode: LDRSBWpre +/* 31133 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31142 +/* 31137 */ MCD_OPC_Decode, 219, 14, 231, 1, // Opcode: STRBBui +/* 31142 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31151 +/* 31146 */ MCD_OPC_Decode, 202, 7, 231, 1, // Opcode: LDRBBui +/* 31151 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31160 +/* 31155 */ MCD_OPC_Decode, 239, 7, 231, 1, // Opcode: LDRSBXui +/* 31160 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31169 +/* 31164 */ MCD_OPC_Decode, 234, 7, 231, 1, // Opcode: LDRSBWui +/* 31169 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 31189 +/* 31173 */ MCD_OPC_CheckField, 21, 1, 0, 246, 36, // Skip to: 40641 +/* 31179 */ MCD_OPC_CheckField, 10, 6, 0, 240, 36, // Skip to: 40641 +/* 31185 */ MCD_OPC_Decode, 30, 223, 1, // Opcode: ADCSWr +/* 31189 */ MCD_OPC_FilterValue, 9, 232, 36, // Skip to: 40641 +/* 31193 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31196 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31217 +/* 31200 */ MCD_OPC_CheckField, 21, 1, 0, 219, 36, // Skip to: 40641 +/* 31206 */ MCD_OPC_CheckField, 4, 1, 0, 213, 36, // Skip to: 40641 +/* 31212 */ MCD_OPC_Decode, 136, 1, 232, 1, // Opcode: CCMNWr +/* 31217 */ MCD_OPC_FilterValue, 2, 204, 36, // Skip to: 40641 +/* 31221 */ MCD_OPC_CheckField, 21, 1, 0, 198, 36, // Skip to: 40641 +/* 31227 */ MCD_OPC_CheckField, 4, 1, 0, 192, 36, // Skip to: 40641 +/* 31233 */ MCD_OPC_Decode, 135, 1, 233, 1, // Opcode: CCMNWi +/* 31238 */ MCD_OPC_FilterValue, 2, 132, 0, // Skip to: 31374 +/* 31242 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 31245 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31254 +/* 31249 */ MCD_OPC_Decode, 140, 8, 212, 1, // Opcode: LDRXl +/* 31254 */ MCD_OPC_FilterValue, 2, 167, 36, // Skip to: 40641 +/* 31258 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31261 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 31317 +/* 31265 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 31268 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31283 +/* 31272 */ MCD_OPC_CheckField, 12, 4, 0, 147, 36, // Skip to: 40641 +/* 31278 */ MCD_OPC_Decode, 128, 10, 223, 1, // Opcode: SBCWr +/* 31283 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31292 +/* 31287 */ MCD_OPC_Decode, 138, 2, 224, 1, // Opcode: CSINVWr +/* 31292 */ MCD_OPC_FilterValue, 6, 129, 36, // Skip to: 40641 +/* 31296 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 31299 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31308 +/* 31303 */ MCD_OPC_Decode, 164, 9, 234, 1, // Opcode: RBITWr +/* 31308 */ MCD_OPC_FilterValue, 1, 113, 36, // Skip to: 40641 +/* 31312 */ MCD_OPC_Decode, 152, 1, 234, 1, // Opcode: CLZWr +/* 31317 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 31358 +/* 31321 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 31324 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31333 +/* 31328 */ MCD_OPC_Decode, 140, 2, 224, 1, // Opcode: CSNEGWr +/* 31333 */ MCD_OPC_FilterValue, 6, 88, 36, // Skip to: 40641 +/* 31337 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 31340 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31349 +/* 31344 */ MCD_OPC_Decode, 170, 9, 234, 1, // Opcode: REV16Wr +/* 31349 */ MCD_OPC_FilterValue, 1, 72, 36, // Skip to: 40641 +/* 31353 */ MCD_OPC_Decode, 144, 1, 234, 1, // Opcode: CLSWr +/* 31358 */ MCD_OPC_FilterValue, 2, 63, 36, // Skip to: 40641 +/* 31362 */ MCD_OPC_CheckField, 12, 12, 128, 24, 56, 36, // Skip to: 40641 +/* 31369 */ MCD_OPC_Decode, 185, 9, 234, 1, // Opcode: REVWr +/* 31374 */ MCD_OPC_FilterValue, 3, 225, 1, // Skip to: 31859 +/* 31378 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 31381 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 31474 +/* 31385 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31388 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31403 +/* 31392 */ MCD_OPC_CheckField, 21, 1, 0, 27, 36, // Skip to: 40641 +/* 31398 */ MCD_OPC_Decode, 139, 15, 226, 1, // Opcode: STURHHi +/* 31403 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31418 +/* 31407 */ MCD_OPC_CheckField, 21, 1, 0, 12, 36, // Skip to: 40641 +/* 31413 */ MCD_OPC_Decode, 230, 14, 226, 1, // Opcode: STRHHpost +/* 31418 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31459 +/* 31422 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 31425 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31434 +/* 31429 */ MCD_OPC_Decode, 133, 15, 226, 1, // Opcode: STTRHi +/* 31434 */ MCD_OPC_FilterValue, 1, 243, 35, // Skip to: 40641 +/* 31438 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31441 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31450 +/* 31445 */ MCD_OPC_Decode, 232, 14, 227, 1, // Opcode: STRHHroW +/* 31450 */ MCD_OPC_FilterValue, 3, 227, 35, // Skip to: 40641 +/* 31454 */ MCD_OPC_Decode, 233, 14, 228, 1, // Opcode: STRHHroX +/* 31459 */ MCD_OPC_FilterValue, 3, 218, 35, // Skip to: 40641 +/* 31463 */ MCD_OPC_CheckField, 21, 1, 0, 212, 35, // Skip to: 40641 +/* 31469 */ MCD_OPC_Decode, 231, 14, 226, 1, // Opcode: STRHHpre +/* 31474 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 31567 +/* 31478 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31481 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31496 +/* 31485 */ MCD_OPC_CheckField, 21, 1, 0, 190, 35, // Skip to: 40641 +/* 31491 */ MCD_OPC_Decode, 158, 8, 226, 1, // Opcode: LDURHHi +/* 31496 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31511 +/* 31500 */ MCD_OPC_CheckField, 21, 1, 0, 175, 35, // Skip to: 40641 +/* 31506 */ MCD_OPC_Decode, 214, 7, 226, 1, // Opcode: LDRHHpost +/* 31511 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31552 +/* 31515 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 31518 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31527 +/* 31522 */ MCD_OPC_Decode, 147, 8, 226, 1, // Opcode: LDTRHi +/* 31527 */ MCD_OPC_FilterValue, 1, 150, 35, // Skip to: 40641 +/* 31531 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31534 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31543 +/* 31538 */ MCD_OPC_Decode, 216, 7, 227, 1, // Opcode: LDRHHroW +/* 31543 */ MCD_OPC_FilterValue, 3, 134, 35, // Skip to: 40641 +/* 31547 */ MCD_OPC_Decode, 217, 7, 228, 1, // Opcode: LDRHHroX +/* 31552 */ MCD_OPC_FilterValue, 3, 125, 35, // Skip to: 40641 +/* 31556 */ MCD_OPC_CheckField, 21, 1, 0, 119, 35, // Skip to: 40641 +/* 31562 */ MCD_OPC_Decode, 215, 7, 226, 1, // Opcode: LDRHHpre +/* 31567 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31660 +/* 31571 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31574 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31589 +/* 31578 */ MCD_OPC_CheckField, 21, 1, 0, 97, 35, // Skip to: 40641 +/* 31584 */ MCD_OPC_Decode, 164, 8, 226, 1, // Opcode: LDURSHXi +/* 31589 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31604 +/* 31593 */ MCD_OPC_CheckField, 21, 1, 0, 82, 35, // Skip to: 40641 +/* 31599 */ MCD_OPC_Decode, 245, 7, 226, 1, // Opcode: LDRSHXpost +/* 31604 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31645 +/* 31608 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 31611 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31620 +/* 31615 */ MCD_OPC_Decode, 151, 8, 226, 1, // Opcode: LDTRSHXi +/* 31620 */ MCD_OPC_FilterValue, 1, 57, 35, // Skip to: 40641 +/* 31624 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31627 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31636 +/* 31631 */ MCD_OPC_Decode, 247, 7, 229, 1, // Opcode: LDRSHXroW +/* 31636 */ MCD_OPC_FilterValue, 3, 41, 35, // Skip to: 40641 +/* 31640 */ MCD_OPC_Decode, 248, 7, 230, 1, // Opcode: LDRSHXroX +/* 31645 */ MCD_OPC_FilterValue, 3, 32, 35, // Skip to: 40641 +/* 31649 */ MCD_OPC_CheckField, 21, 1, 0, 26, 35, // Skip to: 40641 +/* 31655 */ MCD_OPC_Decode, 246, 7, 226, 1, // Opcode: LDRSHXpre +/* 31660 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31753 +/* 31664 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31667 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31682 +/* 31671 */ MCD_OPC_CheckField, 21, 1, 0, 4, 35, // Skip to: 40641 +/* 31677 */ MCD_OPC_Decode, 163, 8, 226, 1, // Opcode: LDURSHWi +/* 31682 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31697 +/* 31686 */ MCD_OPC_CheckField, 21, 1, 0, 245, 34, // Skip to: 40641 +/* 31692 */ MCD_OPC_Decode, 240, 7, 226, 1, // Opcode: LDRSHWpost +/* 31697 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31738 +/* 31701 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 31704 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31713 +/* 31708 */ MCD_OPC_Decode, 150, 8, 226, 1, // Opcode: LDTRSHWi +/* 31713 */ MCD_OPC_FilterValue, 1, 220, 34, // Skip to: 40641 +/* 31717 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 31720 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31729 +/* 31724 */ MCD_OPC_Decode, 242, 7, 227, 1, // Opcode: LDRSHWroW +/* 31729 */ MCD_OPC_FilterValue, 3, 204, 34, // Skip to: 40641 +/* 31733 */ MCD_OPC_Decode, 243, 7, 228, 1, // Opcode: LDRSHWroX +/* 31738 */ MCD_OPC_FilterValue, 3, 195, 34, // Skip to: 40641 +/* 31742 */ MCD_OPC_CheckField, 21, 1, 0, 189, 34, // Skip to: 40641 +/* 31748 */ MCD_OPC_Decode, 241, 7, 226, 1, // Opcode: LDRSHWpre +/* 31753 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31762 +/* 31757 */ MCD_OPC_Decode, 234, 14, 231, 1, // Opcode: STRHHui +/* 31762 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31771 +/* 31766 */ MCD_OPC_Decode, 218, 7, 231, 1, // Opcode: LDRHHui +/* 31771 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31780 +/* 31775 */ MCD_OPC_Decode, 249, 7, 231, 1, // Opcode: LDRSHXui +/* 31780 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31789 +/* 31784 */ MCD_OPC_Decode, 244, 7, 231, 1, // Opcode: LDRSHWui +/* 31789 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 31810 +/* 31793 */ MCD_OPC_CheckField, 21, 1, 0, 138, 34, // Skip to: 40641 +/* 31799 */ MCD_OPC_CheckField, 10, 6, 0, 132, 34, // Skip to: 40641 +/* 31805 */ MCD_OPC_Decode, 254, 9, 223, 1, // Opcode: SBCSWr +/* 31810 */ MCD_OPC_FilterValue, 9, 123, 34, // Skip to: 40641 +/* 31814 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31817 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31838 +/* 31821 */ MCD_OPC_CheckField, 21, 1, 0, 110, 34, // Skip to: 40641 +/* 31827 */ MCD_OPC_CheckField, 4, 1, 0, 104, 34, // Skip to: 40641 +/* 31833 */ MCD_OPC_Decode, 140, 1, 232, 1, // Opcode: CCMPWr +/* 31838 */ MCD_OPC_FilterValue, 2, 95, 34, // Skip to: 40641 +/* 31842 */ MCD_OPC_CheckField, 21, 1, 0, 89, 34, // Skip to: 40641 +/* 31848 */ MCD_OPC_CheckField, 4, 1, 0, 83, 34, // Skip to: 40641 +/* 31854 */ MCD_OPC_Decode, 139, 1, 233, 1, // Opcode: CCMPWi +/* 31859 */ MCD_OPC_FilterValue, 4, 62, 1, // Skip to: 32181 +/* 31863 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 31866 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31875 +/* 31870 */ MCD_OPC_Decode, 250, 7, 212, 1, // Opcode: LDRSWl +/* 31875 */ MCD_OPC_FilterValue, 2, 190, 0, // Skip to: 32069 +/* 31879 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 31882 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 31927 +/* 31886 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 31889 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31903 +/* 31893 */ MCD_OPC_CheckField, 12, 4, 0, 38, 34, // Skip to: 40641 +/* 31899 */ MCD_OPC_Decode, 33, 235, 1, // Opcode: ADCXr +/* 31903 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31912 +/* 31907 */ MCD_OPC_Decode, 135, 2, 236, 1, // Opcode: CSELXr +/* 31912 */ MCD_OPC_FilterValue, 6, 21, 34, // Skip to: 40641 +/* 31916 */ MCD_OPC_CheckField, 12, 4, 2, 15, 34, // Skip to: 40641 +/* 31922 */ MCD_OPC_Decode, 177, 8, 235, 1, // Opcode: LSLVXr +/* 31927 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 31958 +/* 31931 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 31934 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31943 +/* 31938 */ MCD_OPC_Decode, 137, 2, 236, 1, // Opcode: CSINCXr +/* 31943 */ MCD_OPC_FilterValue, 6, 246, 33, // Skip to: 40641 +/* 31947 */ MCD_OPC_CheckField, 12, 4, 2, 240, 33, // Skip to: 40641 +/* 31953 */ MCD_OPC_Decode, 179, 8, 235, 1, // Opcode: LSRVXr +/* 31958 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 31994 +/* 31962 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 31965 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31980 +/* 31969 */ MCD_OPC_CheckField, 21, 3, 6, 218, 33, // Skip to: 40641 +/* 31975 */ MCD_OPC_Decode, 181, 16, 235, 1, // Opcode: UDIVXr +/* 31980 */ MCD_OPC_FilterValue, 2, 209, 33, // Skip to: 40641 +/* 31984 */ MCD_OPC_CheckField, 21, 3, 6, 203, 33, // Skip to: 40641 +/* 31990 */ MCD_OPC_Decode, 102, 235, 1, // Opcode: ASRVXr +/* 31994 */ MCD_OPC_FilterValue, 3, 195, 33, // Skip to: 40641 +/* 31998 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 32001 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32016 +/* 32005 */ MCD_OPC_CheckField, 21, 3, 6, 182, 33, // Skip to: 40641 +/* 32011 */ MCD_OPC_Decode, 151, 10, 235, 1, // Opcode: SDIVXr +/* 32016 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32031 +/* 32020 */ MCD_OPC_CheckField, 21, 3, 6, 167, 33, // Skip to: 40641 +/* 32026 */ MCD_OPC_Decode, 188, 9, 235, 1, // Opcode: RORVXr +/* 32031 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 32050 +/* 32035 */ MCD_OPC_CheckPredicate, 2, 154, 33, // Skip to: 40641 +/* 32039 */ MCD_OPC_CheckField, 21, 3, 6, 148, 33, // Skip to: 40641 +/* 32045 */ MCD_OPC_Decode, 133, 2, 237, 1, // Opcode: CRC32Xrr +/* 32050 */ MCD_OPC_FilterValue, 5, 139, 33, // Skip to: 40641 +/* 32054 */ MCD_OPC_CheckPredicate, 2, 135, 33, // Skip to: 40641 +/* 32058 */ MCD_OPC_CheckField, 21, 3, 6, 129, 33, // Skip to: 40641 +/* 32064 */ MCD_OPC_Decode, 130, 2, 237, 1, // Opcode: CRC32CXrr +/* 32069 */ MCD_OPC_FilterValue, 3, 120, 33, // Skip to: 40641 +/* 32073 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 32076 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 32101 +/* 32080 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 32083 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32092 +/* 32087 */ MCD_OPC_Decode, 181, 8, 238, 1, // Opcode: MADDXrrr +/* 32092 */ MCD_OPC_FilterValue, 1, 97, 33, // Skip to: 40641 +/* 32096 */ MCD_OPC_Decode, 230, 8, 238, 1, // Opcode: MSUBXrrr +/* 32101 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 32126 +/* 32105 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 32108 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32117 +/* 32112 */ MCD_OPC_Decode, 204, 10, 239, 1, // Opcode: SMADDLrrr +/* 32117 */ MCD_OPC_FilterValue, 1, 72, 33, // Skip to: 40641 +/* 32121 */ MCD_OPC_Decode, 137, 11, 239, 1, // Opcode: SMSUBLrrr +/* 32126 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32141 +/* 32130 */ MCD_OPC_CheckField, 15, 1, 0, 57, 33, // Skip to: 40641 +/* 32136 */ MCD_OPC_Decode, 138, 11, 235, 1, // Opcode: SMULHrr +/* 32141 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 32166 +/* 32145 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 32148 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32157 +/* 32152 */ MCD_OPC_Decode, 196, 16, 239, 1, // Opcode: UMADDLrrr +/* 32157 */ MCD_OPC_FilterValue, 1, 32, 33, // Skip to: 40641 +/* 32161 */ MCD_OPC_Decode, 255, 16, 239, 1, // Opcode: UMSUBLrrr +/* 32166 */ MCD_OPC_FilterValue, 6, 23, 33, // Skip to: 40641 +/* 32170 */ MCD_OPC_CheckField, 15, 1, 0, 17, 33, // Skip to: 40641 +/* 32176 */ MCD_OPC_Decode, 128, 17, 235, 1, // Opcode: UMULHrr +/* 32181 */ MCD_OPC_FilterValue, 5, 122, 1, // Skip to: 32563 +/* 32185 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 32188 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32281 +/* 32192 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32195 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32210 +/* 32199 */ MCD_OPC_CheckField, 21, 1, 0, 244, 32, // Skip to: 40641 +/* 32205 */ MCD_OPC_Decode, 143, 15, 226, 1, // Opcode: STURWi +/* 32210 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32225 +/* 32214 */ MCD_OPC_CheckField, 21, 1, 0, 229, 32, // Skip to: 40641 +/* 32220 */ MCD_OPC_Decode, 250, 14, 226, 1, // Opcode: STRWpost +/* 32225 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32266 +/* 32229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 32232 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32241 +/* 32236 */ MCD_OPC_Decode, 134, 15, 226, 1, // Opcode: STTRWi +/* 32241 */ MCD_OPC_FilterValue, 1, 204, 32, // Skip to: 40641 +/* 32245 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32248 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32257 +/* 32252 */ MCD_OPC_Decode, 252, 14, 227, 1, // Opcode: STRWroW +/* 32257 */ MCD_OPC_FilterValue, 3, 188, 32, // Skip to: 40641 +/* 32261 */ MCD_OPC_Decode, 253, 14, 228, 1, // Opcode: STRWroX +/* 32266 */ MCD_OPC_FilterValue, 3, 179, 32, // Skip to: 40641 +/* 32270 */ MCD_OPC_CheckField, 21, 1, 0, 173, 32, // Skip to: 40641 +/* 32276 */ MCD_OPC_Decode, 251, 14, 226, 1, // Opcode: STRWpre +/* 32281 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32374 +/* 32285 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32288 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32303 +/* 32292 */ MCD_OPC_CheckField, 21, 1, 0, 151, 32, // Skip to: 40641 +/* 32298 */ MCD_OPC_Decode, 167, 8, 226, 1, // Opcode: LDURWi +/* 32303 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32318 +/* 32307 */ MCD_OPC_CheckField, 21, 1, 0, 136, 32, // Skip to: 40641 +/* 32313 */ MCD_OPC_Decode, 135, 8, 226, 1, // Opcode: LDRWpost +/* 32318 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32359 +/* 32322 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 32325 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32334 +/* 32329 */ MCD_OPC_Decode, 153, 8, 226, 1, // Opcode: LDTRWi +/* 32334 */ MCD_OPC_FilterValue, 1, 111, 32, // Skip to: 40641 +/* 32338 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32341 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32350 +/* 32345 */ MCD_OPC_Decode, 137, 8, 227, 1, // Opcode: LDRWroW +/* 32350 */ MCD_OPC_FilterValue, 3, 95, 32, // Skip to: 40641 +/* 32354 */ MCD_OPC_Decode, 138, 8, 228, 1, // Opcode: LDRWroX +/* 32359 */ MCD_OPC_FilterValue, 3, 86, 32, // Skip to: 40641 +/* 32363 */ MCD_OPC_CheckField, 21, 1, 0, 80, 32, // Skip to: 40641 +/* 32369 */ MCD_OPC_Decode, 136, 8, 226, 1, // Opcode: LDRWpre +/* 32374 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 32467 +/* 32378 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32381 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32396 +/* 32385 */ MCD_OPC_CheckField, 21, 1, 0, 58, 32, // Skip to: 40641 +/* 32391 */ MCD_OPC_Decode, 165, 8, 226, 1, // Opcode: LDURSWi +/* 32396 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32411 +/* 32400 */ MCD_OPC_CheckField, 21, 1, 0, 43, 32, // Skip to: 40641 +/* 32406 */ MCD_OPC_Decode, 251, 7, 226, 1, // Opcode: LDRSWpost +/* 32411 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32452 +/* 32415 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 32418 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32427 +/* 32422 */ MCD_OPC_Decode, 152, 8, 226, 1, // Opcode: LDTRSWi +/* 32427 */ MCD_OPC_FilterValue, 1, 18, 32, // Skip to: 40641 +/* 32431 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32434 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32443 +/* 32438 */ MCD_OPC_Decode, 253, 7, 229, 1, // Opcode: LDRSWroW +/* 32443 */ MCD_OPC_FilterValue, 3, 2, 32, // Skip to: 40641 +/* 32447 */ MCD_OPC_Decode, 254, 7, 230, 1, // Opcode: LDRSWroX +/* 32452 */ MCD_OPC_FilterValue, 3, 249, 31, // Skip to: 40641 +/* 32456 */ MCD_OPC_CheckField, 21, 1, 0, 243, 31, // Skip to: 40641 +/* 32462 */ MCD_OPC_Decode, 252, 7, 226, 1, // Opcode: LDRSWpre +/* 32467 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32476 +/* 32471 */ MCD_OPC_Decode, 254, 14, 231, 1, // Opcode: STRWui +/* 32476 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 32485 +/* 32480 */ MCD_OPC_Decode, 139, 8, 231, 1, // Opcode: LDRWui +/* 32485 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 32494 +/* 32489 */ MCD_OPC_Decode, 255, 7, 231, 1, // Opcode: LDRSWui +/* 32494 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 32514 +/* 32498 */ MCD_OPC_CheckField, 21, 1, 0, 201, 31, // Skip to: 40641 +/* 32504 */ MCD_OPC_CheckField, 10, 6, 0, 195, 31, // Skip to: 40641 +/* 32510 */ MCD_OPC_Decode, 31, 235, 1, // Opcode: ADCSXr +/* 32514 */ MCD_OPC_FilterValue, 9, 187, 31, // Skip to: 40641 +/* 32518 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32521 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 32542 +/* 32525 */ MCD_OPC_CheckField, 21, 1, 0, 174, 31, // Skip to: 40641 +/* 32531 */ MCD_OPC_CheckField, 4, 1, 0, 168, 31, // Skip to: 40641 +/* 32537 */ MCD_OPC_Decode, 138, 1, 240, 1, // Opcode: CCMNXr +/* 32542 */ MCD_OPC_FilterValue, 2, 159, 31, // Skip to: 40641 +/* 32546 */ MCD_OPC_CheckField, 21, 1, 0, 153, 31, // Skip to: 40641 +/* 32552 */ MCD_OPC_CheckField, 4, 1, 0, 147, 31, // Skip to: 40641 +/* 32558 */ MCD_OPC_Decode, 137, 1, 241, 1, // Opcode: CCMNXi +/* 32563 */ MCD_OPC_FilterValue, 6, 148, 0, // Skip to: 32715 +/* 32567 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 32570 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32579 +/* 32574 */ MCD_OPC_Decode, 153, 9, 242, 1, // Opcode: PRFMl +/* 32579 */ MCD_OPC_FilterValue, 2, 122, 31, // Skip to: 40641 +/* 32583 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32586 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 32642 +/* 32590 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 32593 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32608 +/* 32597 */ MCD_OPC_CheckField, 12, 4, 0, 102, 31, // Skip to: 40641 +/* 32603 */ MCD_OPC_Decode, 129, 10, 235, 1, // Opcode: SBCXr +/* 32608 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32617 +/* 32612 */ MCD_OPC_Decode, 139, 2, 236, 1, // Opcode: CSINVXr +/* 32617 */ MCD_OPC_FilterValue, 6, 84, 31, // Skip to: 40641 +/* 32621 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 32624 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32633 +/* 32628 */ MCD_OPC_Decode, 165, 9, 243, 1, // Opcode: RBITXr +/* 32633 */ MCD_OPC_FilterValue, 1, 68, 31, // Skip to: 40641 +/* 32637 */ MCD_OPC_Decode, 153, 1, 243, 1, // Opcode: CLZXr +/* 32642 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 32683 +/* 32646 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 32649 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32658 +/* 32653 */ MCD_OPC_Decode, 141, 2, 236, 1, // Opcode: CSNEGXr +/* 32658 */ MCD_OPC_FilterValue, 6, 43, 31, // Skip to: 40641 +/* 32662 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 32665 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32674 +/* 32669 */ MCD_OPC_Decode, 171, 9, 243, 1, // Opcode: REV16Xr +/* 32674 */ MCD_OPC_FilterValue, 1, 27, 31, // Skip to: 40641 +/* 32678 */ MCD_OPC_Decode, 145, 1, 243, 1, // Opcode: CLSXr +/* 32683 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 32699 +/* 32687 */ MCD_OPC_CheckField, 12, 12, 128, 24, 11, 31, // Skip to: 40641 +/* 32694 */ MCD_OPC_Decode, 174, 9, 243, 1, // Opcode: REV32Xr +/* 32699 */ MCD_OPC_FilterValue, 3, 2, 31, // Skip to: 40641 +/* 32703 */ MCD_OPC_CheckField, 12, 12, 128, 24, 251, 30, // Skip to: 40641 +/* 32710 */ MCD_OPC_Decode, 186, 9, 243, 1, // Opcode: REVXr +/* 32715 */ MCD_OPC_FilterValue, 7, 242, 30, // Skip to: 40641 +/* 32719 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 32722 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32815 +/* 32726 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32729 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32744 +/* 32733 */ MCD_OPC_CheckField, 21, 1, 0, 222, 30, // Skip to: 40641 +/* 32739 */ MCD_OPC_Decode, 144, 15, 226, 1, // Opcode: STURXi +/* 32744 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32759 +/* 32748 */ MCD_OPC_CheckField, 21, 1, 0, 207, 30, // Skip to: 40641 +/* 32754 */ MCD_OPC_Decode, 255, 14, 226, 1, // Opcode: STRXpost +/* 32759 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32800 +/* 32763 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 32766 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32775 +/* 32770 */ MCD_OPC_Decode, 135, 15, 226, 1, // Opcode: STTRXi +/* 32775 */ MCD_OPC_FilterValue, 1, 182, 30, // Skip to: 40641 +/* 32779 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32782 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32791 +/* 32786 */ MCD_OPC_Decode, 129, 15, 229, 1, // Opcode: STRXroW +/* 32791 */ MCD_OPC_FilterValue, 3, 166, 30, // Skip to: 40641 +/* 32795 */ MCD_OPC_Decode, 130, 15, 230, 1, // Opcode: STRXroX +/* 32800 */ MCD_OPC_FilterValue, 3, 157, 30, // Skip to: 40641 +/* 32804 */ MCD_OPC_CheckField, 21, 1, 0, 151, 30, // Skip to: 40641 +/* 32810 */ MCD_OPC_Decode, 128, 15, 226, 1, // Opcode: STRXpre +/* 32815 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32908 +/* 32819 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32822 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32837 +/* 32826 */ MCD_OPC_CheckField, 21, 1, 0, 129, 30, // Skip to: 40641 +/* 32832 */ MCD_OPC_Decode, 168, 8, 226, 1, // Opcode: LDURXi +/* 32837 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32852 +/* 32841 */ MCD_OPC_CheckField, 21, 1, 0, 114, 30, // Skip to: 40641 +/* 32847 */ MCD_OPC_Decode, 141, 8, 226, 1, // Opcode: LDRXpost +/* 32852 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32893 +/* 32856 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 32859 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32868 +/* 32863 */ MCD_OPC_Decode, 154, 8, 226, 1, // Opcode: LDTRXi +/* 32868 */ MCD_OPC_FilterValue, 1, 89, 30, // Skip to: 40641 +/* 32872 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32875 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32884 +/* 32879 */ MCD_OPC_Decode, 143, 8, 229, 1, // Opcode: LDRXroW +/* 32884 */ MCD_OPC_FilterValue, 3, 73, 30, // Skip to: 40641 +/* 32888 */ MCD_OPC_Decode, 144, 8, 230, 1, // Opcode: LDRXroX +/* 32893 */ MCD_OPC_FilterValue, 3, 64, 30, // Skip to: 40641 +/* 32897 */ MCD_OPC_CheckField, 21, 1, 0, 58, 30, // Skip to: 40641 +/* 32903 */ MCD_OPC_Decode, 142, 8, 226, 1, // Opcode: LDRXpre +/* 32908 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 32967 +/* 32912 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 32915 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32930 +/* 32919 */ MCD_OPC_CheckField, 21, 1, 0, 36, 30, // Skip to: 40641 +/* 32925 */ MCD_OPC_Decode, 157, 9, 226, 1, // Opcode: PRFUMi +/* 32930 */ MCD_OPC_FilterValue, 2, 27, 30, // Skip to: 40641 +/* 32934 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 32937 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32952 +/* 32941 */ MCD_OPC_CheckField, 21, 1, 1, 14, 30, // Skip to: 40641 +/* 32947 */ MCD_OPC_Decode, 154, 9, 244, 1, // Opcode: PRFMroW +/* 32952 */ MCD_OPC_FilterValue, 3, 5, 30, // Skip to: 40641 +/* 32956 */ MCD_OPC_CheckField, 21, 1, 1, 255, 29, // Skip to: 40641 +/* 32962 */ MCD_OPC_Decode, 155, 9, 245, 1, // Opcode: PRFMroX +/* 32967 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32976 +/* 32971 */ MCD_OPC_Decode, 131, 15, 231, 1, // Opcode: STRXui +/* 32976 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 32985 +/* 32980 */ MCD_OPC_Decode, 145, 8, 231, 1, // Opcode: LDRXui +/* 32985 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 32994 +/* 32989 */ MCD_OPC_Decode, 156, 9, 231, 1, // Opcode: PRFMui +/* 32994 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 33015 +/* 32998 */ MCD_OPC_CheckField, 21, 1, 0, 213, 29, // Skip to: 40641 +/* 33004 */ MCD_OPC_CheckField, 10, 6, 0, 207, 29, // Skip to: 40641 +/* 33010 */ MCD_OPC_Decode, 255, 9, 235, 1, // Opcode: SBCSXr +/* 33015 */ MCD_OPC_FilterValue, 9, 198, 29, // Skip to: 40641 +/* 33019 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 33022 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 33043 +/* 33026 */ MCD_OPC_CheckField, 21, 1, 0, 185, 29, // Skip to: 40641 +/* 33032 */ MCD_OPC_CheckField, 4, 1, 0, 179, 29, // Skip to: 40641 +/* 33038 */ MCD_OPC_Decode, 142, 1, 240, 1, // Opcode: CCMPXr +/* 33043 */ MCD_OPC_FilterValue, 2, 170, 29, // Skip to: 40641 +/* 33047 */ MCD_OPC_CheckField, 21, 1, 0, 164, 29, // Skip to: 40641 +/* 33053 */ MCD_OPC_CheckField, 4, 1, 0, 158, 29, // Skip to: 40641 +/* 33059 */ MCD_OPC_Decode, 141, 1, 241, 1, // Opcode: CCMPXi +/* 33064 */ MCD_OPC_FilterValue, 7, 149, 29, // Skip to: 40641 +/* 33068 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 33071 */ MCD_OPC_FilterValue, 0, 8, 6, // Skip to: 34619 +/* 33075 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 33078 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 33087 +/* 33082 */ MCD_OPC_Decode, 128, 8, 246, 1, // Opcode: LDRSl +/* 33087 */ MCD_OPC_FilterValue, 2, 109, 5, // Skip to: 34480 +/* 33091 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 33094 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 33153 +/* 33098 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... +/* 33101 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33114 +/* 33105 */ MCD_OPC_CheckPredicate, 3, 108, 29, // Skip to: 40641 +/* 33109 */ MCD_OPC_Decode, 133, 10, 247, 1, // Opcode: SCVTFSWSri +/* 33114 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33127 +/* 33118 */ MCD_OPC_CheckPredicate, 3, 95, 29, // Skip to: 40641 +/* 33122 */ MCD_OPC_Decode, 163, 16, 247, 1, // Opcode: UCVTFSWSri +/* 33127 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33140 +/* 33131 */ MCD_OPC_CheckPredicate, 3, 82, 29, // Skip to: 40641 +/* 33135 */ MCD_OPC_Decode, 226, 3, 248, 1, // Opcode: FCVTZSSWSri +/* 33140 */ MCD_OPC_FilterValue, 51, 73, 29, // Skip to: 40641 +/* 33144 */ MCD_OPC_CheckPredicate, 3, 69, 29, // Skip to: 40641 +/* 33148 */ MCD_OPC_Decode, 255, 3, 248, 1, // Opcode: FCVTZUSWSri +/* 33153 */ MCD_OPC_FilterValue, 1, 125, 2, // Skip to: 33794 +/* 33157 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 33160 */ MCD_OPC_FilterValue, 0, 204, 1, // Skip to: 33624 +/* 33164 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 33167 */ MCD_OPC_FilterValue, 0, 178, 1, // Skip to: 33605 +/* 33171 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 33174 */ MCD_OPC_FilterValue, 0, 185, 0, // Skip to: 33363 +/* 33178 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 33181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33194 +/* 33185 */ MCD_OPC_CheckPredicate, 3, 28, 29, // Skip to: 40641 +/* 33189 */ MCD_OPC_Decode, 181, 3, 249, 1, // Opcode: FCVTNSUWSr +/* 33194 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33207 +/* 33198 */ MCD_OPC_CheckPredicate, 3, 15, 29, // Skip to: 40641 +/* 33202 */ MCD_OPC_Decode, 190, 3, 249, 1, // Opcode: FCVTNUUWSr +/* 33207 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33220 +/* 33211 */ MCD_OPC_CheckPredicate, 3, 2, 29, // Skip to: 40641 +/* 33215 */ MCD_OPC_Decode, 137, 10, 250, 1, // Opcode: SCVTFUWSri +/* 33220 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33233 +/* 33224 */ MCD_OPC_CheckPredicate, 3, 245, 28, // Skip to: 40641 +/* 33228 */ MCD_OPC_Decode, 167, 16, 250, 1, // Opcode: UCVTFUWSri +/* 33233 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33246 +/* 33237 */ MCD_OPC_CheckPredicate, 3, 232, 28, // Skip to: 40641 +/* 33241 */ MCD_OPC_Decode, 137, 3, 249, 1, // Opcode: FCVTASUWSr +/* 33246 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33259 +/* 33250 */ MCD_OPC_CheckPredicate, 3, 219, 28, // Skip to: 40641 +/* 33254 */ MCD_OPC_Decode, 146, 3, 249, 1, // Opcode: FCVTAUUWSr +/* 33259 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33272 +/* 33263 */ MCD_OPC_CheckPredicate, 3, 206, 28, // Skip to: 40641 +/* 33267 */ MCD_OPC_Decode, 226, 4, 249, 1, // Opcode: FMOVSWr +/* 33272 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33285 +/* 33276 */ MCD_OPC_CheckPredicate, 3, 193, 28, // Skip to: 40641 +/* 33280 */ MCD_OPC_Decode, 229, 4, 250, 1, // Opcode: FMOVWSr +/* 33285 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33298 +/* 33289 */ MCD_OPC_CheckPredicate, 3, 180, 28, // Skip to: 40641 +/* 33293 */ MCD_OPC_Decode, 203, 3, 249, 1, // Opcode: FCVTPSUWSr +/* 33298 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 33311 +/* 33302 */ MCD_OPC_CheckPredicate, 3, 167, 28, // Skip to: 40641 +/* 33306 */ MCD_OPC_Decode, 212, 3, 249, 1, // Opcode: FCVTPUUWSr +/* 33311 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33324 +/* 33315 */ MCD_OPC_CheckPredicate, 3, 154, 28, // Skip to: 40641 +/* 33319 */ MCD_OPC_Decode, 163, 3, 249, 1, // Opcode: FCVTMSUWSr +/* 33324 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 33337 +/* 33328 */ MCD_OPC_CheckPredicate, 3, 141, 28, // Skip to: 40641 +/* 33332 */ MCD_OPC_Decode, 172, 3, 249, 1, // Opcode: FCVTMUUWSr +/* 33337 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 33350 +/* 33341 */ MCD_OPC_CheckPredicate, 3, 128, 28, // Skip to: 40641 +/* 33345 */ MCD_OPC_Decode, 230, 3, 249, 1, // Opcode: FCVTZSUWSr +/* 33350 */ MCD_OPC_FilterValue, 25, 119, 28, // Skip to: 40641 +/* 33354 */ MCD_OPC_CheckPredicate, 3, 115, 28, // Skip to: 40641 +/* 33358 */ MCD_OPC_Decode, 131, 4, 249, 1, // Opcode: FCVTZUUWSr +/* 33363 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 33422 +/* 33367 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 33370 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33383 +/* 33374 */ MCD_OPC_CheckPredicate, 3, 95, 28, // Skip to: 40641 +/* 33378 */ MCD_OPC_Decode, 133, 3, 251, 1, // Opcode: FCMPSrr +/* 33383 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33396 +/* 33387 */ MCD_OPC_CheckPredicate, 3, 82, 28, // Skip to: 40641 +/* 33391 */ MCD_OPC_Decode, 132, 3, 252, 1, // Opcode: FCMPSri +/* 33396 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33409 +/* 33400 */ MCD_OPC_CheckPredicate, 3, 69, 28, // Skip to: 40641 +/* 33404 */ MCD_OPC_Decode, 131, 3, 251, 1, // Opcode: FCMPESrr +/* 33409 */ MCD_OPC_FilterValue, 24, 60, 28, // Skip to: 40641 +/* 33413 */ MCD_OPC_CheckPredicate, 3, 56, 28, // Skip to: 40641 +/* 33417 */ MCD_OPC_Decode, 130, 3, 252, 1, // Opcode: FCMPESri +/* 33422 */ MCD_OPC_FilterValue, 2, 81, 0, // Skip to: 33507 +/* 33426 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 33429 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33442 +/* 33433 */ MCD_OPC_CheckPredicate, 3, 36, 28, // Skip to: 40641 +/* 33437 */ MCD_OPC_Decode, 228, 4, 253, 1, // Opcode: FMOVSr +/* 33442 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33455 +/* 33446 */ MCD_OPC_CheckPredicate, 3, 23, 28, // Skip to: 40641 +/* 33450 */ MCD_OPC_Decode, 130, 5, 253, 1, // Opcode: FNEGSr +/* 33455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33468 +/* 33459 */ MCD_OPC_CheckPredicate, 3, 10, 28, // Skip to: 40641 +/* 33463 */ MCD_OPC_Decode, 168, 5, 253, 1, // Opcode: FRINTNSr +/* 33468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33481 +/* 33472 */ MCD_OPC_CheckPredicate, 3, 253, 27, // Skip to: 40641 +/* 33476 */ MCD_OPC_Decode, 163, 5, 253, 1, // Opcode: FRINTMSr +/* 33481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33494 +/* 33485 */ MCD_OPC_CheckPredicate, 3, 240, 27, // Skip to: 40641 +/* 33489 */ MCD_OPC_Decode, 153, 5, 253, 1, // Opcode: FRINTASr +/* 33494 */ MCD_OPC_FilterValue, 7, 231, 27, // Skip to: 40641 +/* 33498 */ MCD_OPC_CheckPredicate, 3, 227, 27, // Skip to: 40641 +/* 33502 */ MCD_OPC_Decode, 178, 5, 253, 1, // Opcode: FRINTXSr +/* 33507 */ MCD_OPC_FilterValue, 6, 218, 27, // Skip to: 40641 +/* 33511 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 33514 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33527 +/* 33518 */ MCD_OPC_CheckPredicate, 3, 207, 27, // Skip to: 40641 +/* 33522 */ MCD_OPC_Decode, 186, 2, 253, 1, // Opcode: FABSSr +/* 33527 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33540 +/* 33531 */ MCD_OPC_CheckPredicate, 3, 194, 27, // Skip to: 40641 +/* 33535 */ MCD_OPC_Decode, 198, 5, 253, 1, // Opcode: FSQRTSr +/* 33540 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33553 +/* 33544 */ MCD_OPC_CheckPredicate, 3, 181, 27, // Skip to: 40641 +/* 33548 */ MCD_OPC_Decode, 155, 3, 254, 1, // Opcode: FCVTDSr +/* 33553 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33566 +/* 33557 */ MCD_OPC_CheckPredicate, 3, 168, 27, // Skip to: 40641 +/* 33561 */ MCD_OPC_Decode, 157, 3, 255, 1, // Opcode: FCVTHSr +/* 33566 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33579 +/* 33570 */ MCD_OPC_CheckPredicate, 3, 155, 27, // Skip to: 40641 +/* 33574 */ MCD_OPC_Decode, 173, 5, 253, 1, // Opcode: FRINTPSr +/* 33579 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33592 +/* 33583 */ MCD_OPC_CheckPredicate, 3, 142, 27, // Skip to: 40641 +/* 33587 */ MCD_OPC_Decode, 183, 5, 253, 1, // Opcode: FRINTZSr +/* 33592 */ MCD_OPC_FilterValue, 7, 133, 27, // Skip to: 40641 +/* 33596 */ MCD_OPC_CheckPredicate, 3, 129, 27, // Skip to: 40641 +/* 33600 */ MCD_OPC_Decode, 158, 5, 253, 1, // Opcode: FRINTISr +/* 33605 */ MCD_OPC_FilterValue, 1, 120, 27, // Skip to: 40641 +/* 33609 */ MCD_OPC_CheckPredicate, 3, 116, 27, // Skip to: 40641 +/* 33613 */ MCD_OPC_CheckField, 5, 5, 0, 110, 27, // Skip to: 40641 +/* 33619 */ MCD_OPC_Decode, 227, 4, 128, 2, // Opcode: FMOVSi +/* 33624 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 33657 +/* 33628 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 33631 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33644 +/* 33635 */ MCD_OPC_CheckPredicate, 3, 90, 27, // Skip to: 40641 +/* 33639 */ MCD_OPC_Decode, 213, 2, 129, 2, // Opcode: FCCMPSrr +/* 33644 */ MCD_OPC_FilterValue, 1, 81, 27, // Skip to: 40641 +/* 33648 */ MCD_OPC_CheckPredicate, 3, 77, 27, // Skip to: 40641 +/* 33652 */ MCD_OPC_Decode, 212, 2, 129, 2, // Opcode: FCCMPESrr +/* 33657 */ MCD_OPC_FilterValue, 2, 120, 0, // Skip to: 33781 +/* 33661 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 33664 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33677 +/* 33668 */ MCD_OPC_CheckPredicate, 3, 57, 27, // Skip to: 40641 +/* 33672 */ MCD_OPC_Decode, 238, 4, 130, 2, // Opcode: FMULSrr +/* 33677 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33690 +/* 33681 */ MCD_OPC_CheckPredicate, 3, 44, 27, // Skip to: 40641 +/* 33685 */ MCD_OPC_Decode, 156, 4, 130, 2, // Opcode: FDIVSrr +/* 33690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33703 +/* 33694 */ MCD_OPC_CheckPredicate, 3, 31, 27, // Skip to: 40641 +/* 33698 */ MCD_OPC_Decode, 206, 2, 130, 2, // Opcode: FADDSrr +/* 33703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33716 +/* 33707 */ MCD_OPC_CheckPredicate, 3, 18, 27, // Skip to: 40641 +/* 33711 */ MCD_OPC_Decode, 203, 5, 130, 2, // Opcode: FSUBSrr +/* 33716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33729 +/* 33720 */ MCD_OPC_CheckPredicate, 3, 5, 27, // Skip to: 40641 +/* 33724 */ MCD_OPC_Decode, 179, 4, 130, 2, // Opcode: FMAXSrr +/* 33729 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33742 +/* 33733 */ MCD_OPC_CheckPredicate, 3, 248, 26, // Skip to: 40641 +/* 33737 */ MCD_OPC_Decode, 201, 4, 130, 2, // Opcode: FMINSrr +/* 33742 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33755 +/* 33746 */ MCD_OPC_CheckPredicate, 3, 235, 26, // Skip to: 40641 +/* 33750 */ MCD_OPC_Decode, 169, 4, 130, 2, // Opcode: FMAXNMSrr +/* 33755 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33768 +/* 33759 */ MCD_OPC_CheckPredicate, 3, 222, 26, // Skip to: 40641 +/* 33763 */ MCD_OPC_Decode, 191, 4, 130, 2, // Opcode: FMINNMSrr +/* 33768 */ MCD_OPC_FilterValue, 8, 213, 26, // Skip to: 40641 +/* 33772 */ MCD_OPC_CheckPredicate, 3, 209, 26, // Skip to: 40641 +/* 33776 */ MCD_OPC_Decode, 139, 5, 130, 2, // Opcode: FNMULSrr +/* 33781 */ MCD_OPC_FilterValue, 3, 200, 26, // Skip to: 40641 +/* 33785 */ MCD_OPC_CheckPredicate, 3, 196, 26, // Skip to: 40641 +/* 33789 */ MCD_OPC_Decode, 135, 3, 131, 2, // Opcode: FCSELSrrr +/* 33794 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 33853 +/* 33798 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... +/* 33801 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33814 +/* 33805 */ MCD_OPC_CheckPredicate, 3, 176, 26, // Skip to: 40641 +/* 33809 */ MCD_OPC_Decode, 132, 10, 132, 2, // Opcode: SCVTFSWDri +/* 33814 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33827 +/* 33818 */ MCD_OPC_CheckPredicate, 3, 163, 26, // Skip to: 40641 +/* 33822 */ MCD_OPC_Decode, 162, 16, 132, 2, // Opcode: UCVTFSWDri +/* 33827 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33840 +/* 33831 */ MCD_OPC_CheckPredicate, 3, 150, 26, // Skip to: 40641 +/* 33835 */ MCD_OPC_Decode, 225, 3, 133, 2, // Opcode: FCVTZSSWDri +/* 33840 */ MCD_OPC_FilterValue, 51, 141, 26, // Skip to: 40641 +/* 33844 */ MCD_OPC_CheckPredicate, 3, 137, 26, // Skip to: 40641 +/* 33848 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: FCVTZUSWDri +/* 33853 */ MCD_OPC_FilterValue, 3, 76, 2, // Skip to: 34445 +/* 33857 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 33860 */ MCD_OPC_FilterValue, 0, 164, 1, // Skip to: 34284 +/* 33864 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 33867 */ MCD_OPC_FilterValue, 0, 138, 1, // Skip to: 34265 +/* 33871 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 33874 */ MCD_OPC_FilterValue, 0, 157, 0, // Skip to: 34035 +/* 33878 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 33881 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33894 +/* 33885 */ MCD_OPC_CheckPredicate, 3, 96, 26, // Skip to: 40641 +/* 33889 */ MCD_OPC_Decode, 180, 3, 134, 2, // Opcode: FCVTNSUWDr +/* 33894 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33907 +/* 33898 */ MCD_OPC_CheckPredicate, 3, 83, 26, // Skip to: 40641 +/* 33902 */ MCD_OPC_Decode, 189, 3, 134, 2, // Opcode: FCVTNUUWDr +/* 33907 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 33919 +/* 33911 */ MCD_OPC_CheckPredicate, 3, 70, 26, // Skip to: 40641 +/* 33915 */ MCD_OPC_Decode, 136, 10, 91, // Opcode: SCVTFUWDri +/* 33919 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 33931 +/* 33923 */ MCD_OPC_CheckPredicate, 3, 58, 26, // Skip to: 40641 +/* 33927 */ MCD_OPC_Decode, 166, 16, 91, // Opcode: UCVTFUWDri +/* 33931 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33944 +/* 33935 */ MCD_OPC_CheckPredicate, 3, 46, 26, // Skip to: 40641 +/* 33939 */ MCD_OPC_Decode, 136, 3, 134, 2, // Opcode: FCVTASUWDr +/* 33944 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33957 +/* 33948 */ MCD_OPC_CheckPredicate, 3, 33, 26, // Skip to: 40641 +/* 33952 */ MCD_OPC_Decode, 145, 3, 134, 2, // Opcode: FCVTAUUWDr +/* 33957 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33970 +/* 33961 */ MCD_OPC_CheckPredicate, 3, 20, 26, // Skip to: 40641 +/* 33965 */ MCD_OPC_Decode, 202, 3, 134, 2, // Opcode: FCVTPSUWDr +/* 33970 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 33983 +/* 33974 */ MCD_OPC_CheckPredicate, 3, 7, 26, // Skip to: 40641 +/* 33978 */ MCD_OPC_Decode, 211, 3, 134, 2, // Opcode: FCVTPUUWDr +/* 33983 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33996 +/* 33987 */ MCD_OPC_CheckPredicate, 3, 250, 25, // Skip to: 40641 +/* 33991 */ MCD_OPC_Decode, 162, 3, 134, 2, // Opcode: FCVTMSUWDr +/* 33996 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 34009 +/* 34000 */ MCD_OPC_CheckPredicate, 3, 237, 25, // Skip to: 40641 +/* 34004 */ MCD_OPC_Decode, 171, 3, 134, 2, // Opcode: FCVTMUUWDr +/* 34009 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 34022 +/* 34013 */ MCD_OPC_CheckPredicate, 3, 224, 25, // Skip to: 40641 +/* 34017 */ MCD_OPC_Decode, 229, 3, 134, 2, // Opcode: FCVTZSUWDr +/* 34022 */ MCD_OPC_FilterValue, 25, 215, 25, // Skip to: 40641 +/* 34026 */ MCD_OPC_CheckPredicate, 3, 211, 25, // Skip to: 40641 +/* 34030 */ MCD_OPC_Decode, 130, 4, 134, 2, // Opcode: FCVTZUUWDr +/* 34035 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 34094 +/* 34039 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 34042 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34055 +/* 34046 */ MCD_OPC_CheckPredicate, 3, 191, 25, // Skip to: 40641 +/* 34050 */ MCD_OPC_Decode, 255, 2, 135, 2, // Opcode: FCMPDrr +/* 34055 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 34068 +/* 34059 */ MCD_OPC_CheckPredicate, 3, 178, 25, // Skip to: 40641 +/* 34063 */ MCD_OPC_Decode, 254, 2, 136, 2, // Opcode: FCMPDri +/* 34068 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 34081 +/* 34072 */ MCD_OPC_CheckPredicate, 3, 165, 25, // Skip to: 40641 +/* 34076 */ MCD_OPC_Decode, 129, 3, 135, 2, // Opcode: FCMPEDrr +/* 34081 */ MCD_OPC_FilterValue, 24, 156, 25, // Skip to: 40641 +/* 34085 */ MCD_OPC_CheckPredicate, 3, 152, 25, // Skip to: 40641 +/* 34089 */ MCD_OPC_Decode, 128, 3, 136, 2, // Opcode: FCMPEDri +/* 34094 */ MCD_OPC_FilterValue, 2, 88, 0, // Skip to: 34186 +/* 34098 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 34101 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34113 +/* 34105 */ MCD_OPC_CheckPredicate, 3, 132, 25, // Skip to: 40641 +/* 34109 */ MCD_OPC_Decode, 225, 4, 90, // Opcode: FMOVDr +/* 34113 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34125 +/* 34117 */ MCD_OPC_CheckPredicate, 3, 120, 25, // Skip to: 40641 +/* 34121 */ MCD_OPC_Decode, 129, 5, 90, // Opcode: FNEGDr +/* 34125 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 34138 +/* 34129 */ MCD_OPC_CheckPredicate, 3, 108, 25, // Skip to: 40641 +/* 34133 */ MCD_OPC_Decode, 220, 3, 144, 1, // Opcode: FCVTSDr +/* 34138 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34150 +/* 34142 */ MCD_OPC_CheckPredicate, 3, 95, 25, // Skip to: 40641 +/* 34146 */ MCD_OPC_Decode, 167, 5, 90, // Opcode: FRINTNDr +/* 34150 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34162 +/* 34154 */ MCD_OPC_CheckPredicate, 3, 83, 25, // Skip to: 40641 +/* 34158 */ MCD_OPC_Decode, 162, 5, 90, // Opcode: FRINTMDr +/* 34162 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34174 +/* 34166 */ MCD_OPC_CheckPredicate, 3, 71, 25, // Skip to: 40641 +/* 34170 */ MCD_OPC_Decode, 152, 5, 90, // Opcode: FRINTADr +/* 34174 */ MCD_OPC_FilterValue, 7, 63, 25, // Skip to: 40641 +/* 34178 */ MCD_OPC_CheckPredicate, 3, 59, 25, // Skip to: 40641 +/* 34182 */ MCD_OPC_Decode, 177, 5, 90, // Opcode: FRINTXDr +/* 34186 */ MCD_OPC_FilterValue, 6, 51, 25, // Skip to: 40641 +/* 34190 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 34193 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34205 +/* 34197 */ MCD_OPC_CheckPredicate, 3, 40, 25, // Skip to: 40641 +/* 34201 */ MCD_OPC_Decode, 185, 2, 90, // Opcode: FABSDr +/* 34205 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34217 +/* 34209 */ MCD_OPC_CheckPredicate, 3, 28, 25, // Skip to: 40641 +/* 34213 */ MCD_OPC_Decode, 197, 5, 90, // Opcode: FSQRTDr +/* 34217 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34229 +/* 34221 */ MCD_OPC_CheckPredicate, 3, 16, 25, // Skip to: 40641 +/* 34225 */ MCD_OPC_Decode, 156, 3, 100, // Opcode: FCVTHDr +/* 34229 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34241 +/* 34233 */ MCD_OPC_CheckPredicate, 3, 4, 25, // Skip to: 40641 +/* 34237 */ MCD_OPC_Decode, 172, 5, 90, // Opcode: FRINTPDr +/* 34241 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34253 +/* 34245 */ MCD_OPC_CheckPredicate, 3, 248, 24, // Skip to: 40641 +/* 34249 */ MCD_OPC_Decode, 182, 5, 90, // Opcode: FRINTZDr +/* 34253 */ MCD_OPC_FilterValue, 7, 240, 24, // Skip to: 40641 +/* 34257 */ MCD_OPC_CheckPredicate, 3, 236, 24, // Skip to: 40641 +/* 34261 */ MCD_OPC_Decode, 157, 5, 90, // Opcode: FRINTIDr +/* 34265 */ MCD_OPC_FilterValue, 1, 228, 24, // Skip to: 40641 +/* 34269 */ MCD_OPC_CheckPredicate, 3, 224, 24, // Skip to: 40641 +/* 34273 */ MCD_OPC_CheckField, 5, 5, 0, 218, 24, // Skip to: 40641 +/* 34279 */ MCD_OPC_Decode, 224, 4, 137, 2, // Opcode: FMOVDi +/* 34284 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34317 +/* 34288 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 34291 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34304 +/* 34295 */ MCD_OPC_CheckPredicate, 3, 198, 24, // Skip to: 40641 +/* 34299 */ MCD_OPC_Decode, 210, 2, 138, 2, // Opcode: FCCMPDrr +/* 34304 */ MCD_OPC_FilterValue, 1, 189, 24, // Skip to: 40641 +/* 34308 */ MCD_OPC_CheckPredicate, 3, 185, 24, // Skip to: 40641 +/* 34312 */ MCD_OPC_Decode, 211, 2, 138, 2, // Opcode: FCCMPEDrr +/* 34317 */ MCD_OPC_FilterValue, 2, 111, 0, // Skip to: 34432 +/* 34321 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 34324 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34336 +/* 34328 */ MCD_OPC_CheckPredicate, 3, 165, 24, // Skip to: 40641 +/* 34332 */ MCD_OPC_Decode, 237, 4, 89, // Opcode: FMULDrr +/* 34336 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34348 +/* 34340 */ MCD_OPC_CheckPredicate, 3, 153, 24, // Skip to: 40641 +/* 34344 */ MCD_OPC_Decode, 155, 4, 89, // Opcode: FDIVDrr +/* 34348 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 34360 +/* 34352 */ MCD_OPC_CheckPredicate, 3, 141, 24, // Skip to: 40641 +/* 34356 */ MCD_OPC_Decode, 200, 2, 89, // Opcode: FADDDrr +/* 34360 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34372 +/* 34364 */ MCD_OPC_CheckPredicate, 3, 129, 24, // Skip to: 40641 +/* 34368 */ MCD_OPC_Decode, 202, 5, 89, // Opcode: FSUBDrr +/* 34372 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34384 +/* 34376 */ MCD_OPC_CheckPredicate, 3, 117, 24, // Skip to: 40641 +/* 34380 */ MCD_OPC_Decode, 162, 4, 89, // Opcode: FMAXDrr +/* 34384 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34396 +/* 34388 */ MCD_OPC_CheckPredicate, 3, 105, 24, // Skip to: 40641 +/* 34392 */ MCD_OPC_Decode, 184, 4, 89, // Opcode: FMINDrr +/* 34396 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34408 +/* 34400 */ MCD_OPC_CheckPredicate, 3, 93, 24, // Skip to: 40641 +/* 34404 */ MCD_OPC_Decode, 163, 4, 89, // Opcode: FMAXNMDrr +/* 34408 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 34420 +/* 34412 */ MCD_OPC_CheckPredicate, 3, 81, 24, // Skip to: 40641 +/* 34416 */ MCD_OPC_Decode, 185, 4, 89, // Opcode: FMINNMDrr +/* 34420 */ MCD_OPC_FilterValue, 8, 73, 24, // Skip to: 40641 +/* 34424 */ MCD_OPC_CheckPredicate, 3, 69, 24, // Skip to: 40641 +/* 34428 */ MCD_OPC_Decode, 138, 5, 89, // Opcode: FNMULDrr +/* 34432 */ MCD_OPC_FilterValue, 3, 61, 24, // Skip to: 40641 +/* 34436 */ MCD_OPC_CheckPredicate, 3, 57, 24, // Skip to: 40641 +/* 34440 */ MCD_OPC_Decode, 134, 3, 139, 2, // Opcode: FCSELDrrr +/* 34445 */ MCD_OPC_FilterValue, 7, 48, 24, // Skip to: 40641 +/* 34449 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 34452 */ MCD_OPC_FilterValue, 144, 1, 9, 0, // Skip to: 34466 +/* 34457 */ MCD_OPC_CheckPredicate, 3, 36, 24, // Skip to: 40641 +/* 34461 */ MCD_OPC_Decode, 221, 3, 140, 2, // Opcode: FCVTSHr +/* 34466 */ MCD_OPC_FilterValue, 176, 1, 26, 24, // Skip to: 40641 +/* 34471 */ MCD_OPC_CheckPredicate, 3, 22, 24, // Skip to: 40641 +/* 34475 */ MCD_OPC_Decode, 154, 3, 141, 2, // Opcode: FCVTDHr +/* 34480 */ MCD_OPC_FilterValue, 3, 13, 24, // Skip to: 40641 +/* 34484 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 34487 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 34520 +/* 34491 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 34494 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34507 +/* 34498 */ MCD_OPC_CheckPredicate, 3, 251, 23, // Skip to: 40641 +/* 34502 */ MCD_OPC_Decode, 161, 4, 142, 2, // Opcode: FMADDSrrr +/* 34507 */ MCD_OPC_FilterValue, 1, 242, 23, // Skip to: 40641 +/* 34511 */ MCD_OPC_CheckPredicate, 3, 238, 23, // Skip to: 40641 +/* 34515 */ MCD_OPC_Decode, 236, 4, 142, 2, // Opcode: FMSUBSrrr +/* 34520 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34553 +/* 34524 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 34527 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34540 +/* 34531 */ MCD_OPC_CheckPredicate, 3, 218, 23, // Skip to: 40641 +/* 34535 */ MCD_OPC_Decode, 135, 5, 142, 2, // Opcode: FNMADDSrrr +/* 34540 */ MCD_OPC_FilterValue, 1, 209, 23, // Skip to: 40641 +/* 34544 */ MCD_OPC_CheckPredicate, 3, 205, 23, // Skip to: 40641 +/* 34548 */ MCD_OPC_Decode, 137, 5, 142, 2, // Opcode: FNMSUBSrrr +/* 34553 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 34586 +/* 34557 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 34560 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34573 +/* 34564 */ MCD_OPC_CheckPredicate, 3, 185, 23, // Skip to: 40641 +/* 34568 */ MCD_OPC_Decode, 160, 4, 143, 2, // Opcode: FMADDDrrr +/* 34573 */ MCD_OPC_FilterValue, 1, 176, 23, // Skip to: 40641 +/* 34577 */ MCD_OPC_CheckPredicate, 3, 172, 23, // Skip to: 40641 +/* 34581 */ MCD_OPC_Decode, 235, 4, 143, 2, // Opcode: FMSUBDrrr +/* 34586 */ MCD_OPC_FilterValue, 3, 163, 23, // Skip to: 40641 +/* 34590 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 34593 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34606 +/* 34597 */ MCD_OPC_CheckPredicate, 3, 152, 23, // Skip to: 40641 +/* 34601 */ MCD_OPC_Decode, 134, 5, 143, 2, // Opcode: FNMADDDrrr +/* 34606 */ MCD_OPC_FilterValue, 1, 143, 23, // Skip to: 40641 +/* 34610 */ MCD_OPC_CheckPredicate, 3, 139, 23, // Skip to: 40641 +/* 34614 */ MCD_OPC_Decode, 136, 5, 143, 2, // Opcode: FNMSUBDrrr +/* 34619 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 35018 +/* 34623 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 34626 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 34715 +/* 34630 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 34633 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34648 +/* 34637 */ MCD_OPC_CheckField, 21, 1, 0, 110, 23, // Skip to: 40641 +/* 34643 */ MCD_OPC_Decode, 137, 15, 226, 1, // Opcode: STURBi +/* 34648 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34663 +/* 34652 */ MCD_OPC_CheckField, 21, 1, 0, 95, 23, // Skip to: 40641 +/* 34658 */ MCD_OPC_Decode, 220, 14, 226, 1, // Opcode: STRBpost +/* 34663 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34700 +/* 34667 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 34670 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34685 +/* 34674 */ MCD_OPC_CheckField, 21, 1, 1, 73, 23, // Skip to: 40641 +/* 34680 */ MCD_OPC_Decode, 222, 14, 144, 2, // Opcode: STRBroW +/* 34685 */ MCD_OPC_FilterValue, 3, 64, 23, // Skip to: 40641 +/* 34689 */ MCD_OPC_CheckField, 21, 1, 1, 58, 23, // Skip to: 40641 +/* 34695 */ MCD_OPC_Decode, 223, 14, 145, 2, // Opcode: STRBroX +/* 34700 */ MCD_OPC_FilterValue, 3, 49, 23, // Skip to: 40641 +/* 34704 */ MCD_OPC_CheckField, 21, 1, 0, 43, 23, // Skip to: 40641 +/* 34710 */ MCD_OPC_Decode, 221, 14, 226, 1, // Opcode: STRBpre +/* 34715 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 34804 +/* 34719 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 34722 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34737 +/* 34726 */ MCD_OPC_CheckField, 21, 1, 0, 21, 23, // Skip to: 40641 +/* 34732 */ MCD_OPC_Decode, 156, 8, 226, 1, // Opcode: LDURBi +/* 34737 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34752 +/* 34741 */ MCD_OPC_CheckField, 21, 1, 0, 6, 23, // Skip to: 40641 +/* 34747 */ MCD_OPC_Decode, 203, 7, 226, 1, // Opcode: LDRBpost +/* 34752 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34789 +/* 34756 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 34759 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34774 +/* 34763 */ MCD_OPC_CheckField, 21, 1, 1, 240, 22, // Skip to: 40641 +/* 34769 */ MCD_OPC_Decode, 205, 7, 144, 2, // Opcode: LDRBroW +/* 34774 */ MCD_OPC_FilterValue, 3, 231, 22, // Skip to: 40641 +/* 34778 */ MCD_OPC_CheckField, 21, 1, 1, 225, 22, // Skip to: 40641 +/* 34784 */ MCD_OPC_Decode, 206, 7, 145, 2, // Opcode: LDRBroX +/* 34789 */ MCD_OPC_FilterValue, 3, 216, 22, // Skip to: 40641 +/* 34793 */ MCD_OPC_CheckField, 21, 1, 0, 210, 22, // Skip to: 40641 +/* 34799 */ MCD_OPC_Decode, 204, 7, 226, 1, // Opcode: LDRBpre +/* 34804 */ MCD_OPC_FilterValue, 2, 85, 0, // Skip to: 34893 +/* 34808 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 34811 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34826 +/* 34815 */ MCD_OPC_CheckField, 21, 1, 0, 188, 22, // Skip to: 40641 +/* 34821 */ MCD_OPC_Decode, 141, 15, 226, 1, // Opcode: STURQi +/* 34826 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34841 +/* 34830 */ MCD_OPC_CheckField, 21, 1, 0, 173, 22, // Skip to: 40641 +/* 34836 */ MCD_OPC_Decode, 240, 14, 226, 1, // Opcode: STRQpost +/* 34841 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34878 +/* 34845 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 34848 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34863 +/* 34852 */ MCD_OPC_CheckField, 21, 1, 1, 151, 22, // Skip to: 40641 +/* 34858 */ MCD_OPC_Decode, 242, 14, 146, 2, // Opcode: STRQroW +/* 34863 */ MCD_OPC_FilterValue, 3, 142, 22, // Skip to: 40641 +/* 34867 */ MCD_OPC_CheckField, 21, 1, 1, 136, 22, // Skip to: 40641 +/* 34873 */ MCD_OPC_Decode, 243, 14, 147, 2, // Opcode: STRQroX +/* 34878 */ MCD_OPC_FilterValue, 3, 127, 22, // Skip to: 40641 +/* 34882 */ MCD_OPC_CheckField, 21, 1, 0, 121, 22, // Skip to: 40641 +/* 34888 */ MCD_OPC_Decode, 241, 14, 226, 1, // Opcode: STRQpre +/* 34893 */ MCD_OPC_FilterValue, 3, 85, 0, // Skip to: 34982 +/* 34897 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 34900 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34915 +/* 34904 */ MCD_OPC_CheckField, 21, 1, 0, 99, 22, // Skip to: 40641 +/* 34910 */ MCD_OPC_Decode, 160, 8, 226, 1, // Opcode: LDURQi +/* 34915 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34930 +/* 34919 */ MCD_OPC_CheckField, 21, 1, 0, 84, 22, // Skip to: 40641 +/* 34925 */ MCD_OPC_Decode, 225, 7, 226, 1, // Opcode: LDRQpost +/* 34930 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34967 +/* 34934 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 34937 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34952 +/* 34941 */ MCD_OPC_CheckField, 21, 1, 1, 62, 22, // Skip to: 40641 +/* 34947 */ MCD_OPC_Decode, 227, 7, 146, 2, // Opcode: LDRQroW +/* 34952 */ MCD_OPC_FilterValue, 3, 53, 22, // Skip to: 40641 +/* 34956 */ MCD_OPC_CheckField, 21, 1, 1, 47, 22, // Skip to: 40641 +/* 34962 */ MCD_OPC_Decode, 228, 7, 147, 2, // Opcode: LDRQroX +/* 34967 */ MCD_OPC_FilterValue, 3, 38, 22, // Skip to: 40641 +/* 34971 */ MCD_OPC_CheckField, 21, 1, 0, 32, 22, // Skip to: 40641 +/* 34977 */ MCD_OPC_Decode, 226, 7, 226, 1, // Opcode: LDRQpre +/* 34982 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 34991 +/* 34986 */ MCD_OPC_Decode, 224, 14, 231, 1, // Opcode: STRBui +/* 34991 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 35000 +/* 34995 */ MCD_OPC_Decode, 207, 7, 231, 1, // Opcode: LDRBui +/* 35000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 35009 +/* 35004 */ MCD_OPC_Decode, 244, 14, 231, 1, // Opcode: STRQui +/* 35009 */ MCD_OPC_FilterValue, 7, 252, 21, // Skip to: 40641 +/* 35013 */ MCD_OPC_Decode, 229, 7, 231, 1, // Opcode: LDRQui +/* 35018 */ MCD_OPC_FilterValue, 2, 240, 8, // Skip to: 37310 +/* 35022 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 35025 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 35034 +/* 35029 */ MCD_OPC_Decode, 208, 7, 148, 2, // Opcode: LDRDl +/* 35034 */ MCD_OPC_FilterValue, 2, 175, 5, // Skip to: 36493 +/* 35038 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 35041 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 35060 +/* 35045 */ MCD_OPC_CheckPredicate, 1, 216, 21, // Skip to: 40641 +/* 35049 */ MCD_OPC_CheckField, 21, 3, 0, 210, 21, // Skip to: 40641 +/* 35055 */ MCD_OPC_Decode, 154, 10, 149, 2, // Opcode: SHA1Crrr +/* 35060 */ MCD_OPC_FilterValue, 1, 99, 0, // Skip to: 35163 +/* 35064 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 35067 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 35144 +/* 35071 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 35074 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 35125 +/* 35078 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 35081 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 35106 +/* 35085 */ MCD_OPC_CheckPredicate, 0, 176, 21, // Skip to: 40641 +/* 35089 */ MCD_OPC_CheckField, 21, 3, 0, 170, 21, // Skip to: 40641 +/* 35095 */ MCD_OPC_CheckField, 19, 1, 1, 164, 21, // Skip to: 40641 +/* 35101 */ MCD_OPC_Decode, 252, 1, 150, 2, // Opcode: CPYi64 +/* 35106 */ MCD_OPC_FilterValue, 1, 155, 21, // Skip to: 40641 +/* 35110 */ MCD_OPC_CheckPredicate, 0, 151, 21, // Skip to: 40641 +/* 35114 */ MCD_OPC_CheckField, 21, 3, 0, 145, 21, // Skip to: 40641 +/* 35120 */ MCD_OPC_Decode, 251, 1, 151, 2, // Opcode: CPYi32 +/* 35125 */ MCD_OPC_FilterValue, 1, 136, 21, // Skip to: 40641 +/* 35129 */ MCD_OPC_CheckPredicate, 0, 132, 21, // Skip to: 40641 +/* 35133 */ MCD_OPC_CheckField, 21, 3, 0, 126, 21, // Skip to: 40641 +/* 35139 */ MCD_OPC_Decode, 250, 1, 152, 2, // Opcode: CPYi16 +/* 35144 */ MCD_OPC_FilterValue, 1, 117, 21, // Skip to: 40641 +/* 35148 */ MCD_OPC_CheckPredicate, 0, 113, 21, // Skip to: 40641 +/* 35152 */ MCD_OPC_CheckField, 21, 3, 0, 107, 21, // Skip to: 40641 +/* 35158 */ MCD_OPC_Decode, 253, 1, 153, 2, // Opcode: CPYi8 +/* 35163 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 35182 +/* 35167 */ MCD_OPC_CheckPredicate, 1, 94, 21, // Skip to: 40641 +/* 35171 */ MCD_OPC_CheckField, 16, 8, 40, 88, 21, // Skip to: 40641 +/* 35177 */ MCD_OPC_Decode, 155, 10, 253, 1, // Opcode: SHA1Hrr +/* 35182 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 35240 +/* 35186 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35189 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35202 +/* 35193 */ MCD_OPC_CheckPredicate, 0, 68, 21, // Skip to: 40641 +/* 35197 */ MCD_OPC_Decode, 164, 11, 154, 2, // Opcode: SQADDv1i8 +/* 35202 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35215 +/* 35206 */ MCD_OPC_CheckPredicate, 0, 55, 21, // Skip to: 40641 +/* 35210 */ MCD_OPC_Decode, 161, 11, 155, 2, // Opcode: SQADDv1i16 +/* 35215 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35228 +/* 35219 */ MCD_OPC_CheckPredicate, 0, 42, 21, // Skip to: 40641 +/* 35223 */ MCD_OPC_Decode, 162, 11, 130, 2, // Opcode: SQADDv1i32 +/* 35228 */ MCD_OPC_FilterValue, 7, 33, 21, // Skip to: 40641 +/* 35232 */ MCD_OPC_CheckPredicate, 0, 29, 21, // Skip to: 40641 +/* 35236 */ MCD_OPC_Decode, 163, 11, 89, // Opcode: SQADDv1i64 +/* 35240 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 35259 +/* 35244 */ MCD_OPC_CheckPredicate, 1, 17, 21, // Skip to: 40641 +/* 35248 */ MCD_OPC_CheckField, 21, 3, 0, 11, 21, // Skip to: 40641 +/* 35254 */ MCD_OPC_Decode, 157, 10, 149, 2, // Opcode: SHA1Prrr +/* 35259 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 35277 +/* 35263 */ MCD_OPC_CheckPredicate, 1, 254, 20, // Skip to: 40641 +/* 35267 */ MCD_OPC_CheckField, 16, 8, 40, 248, 20, // Skip to: 40641 +/* 35273 */ MCD_OPC_Decode, 159, 10, 126, // Opcode: SHA1SU1rr +/* 35277 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 35296 +/* 35281 */ MCD_OPC_CheckPredicate, 1, 236, 20, // Skip to: 40641 +/* 35285 */ MCD_OPC_CheckField, 21, 3, 0, 230, 20, // Skip to: 40641 +/* 35291 */ MCD_OPC_Decode, 156, 10, 149, 2, // Opcode: SHA1Mrrr +/* 35296 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 35314 +/* 35300 */ MCD_OPC_CheckPredicate, 1, 217, 20, // Skip to: 40641 +/* 35304 */ MCD_OPC_CheckField, 16, 8, 40, 211, 20, // Skip to: 40641 +/* 35310 */ MCD_OPC_Decode, 162, 10, 126, // Opcode: SHA256SU0rr +/* 35314 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 35372 +/* 35318 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35321 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35334 +/* 35325 */ MCD_OPC_CheckPredicate, 0, 192, 20, // Skip to: 40641 +/* 35329 */ MCD_OPC_Decode, 198, 12, 154, 2, // Opcode: SQSUBv1i8 +/* 35334 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35347 +/* 35338 */ MCD_OPC_CheckPredicate, 0, 179, 20, // Skip to: 40641 +/* 35342 */ MCD_OPC_Decode, 195, 12, 155, 2, // Opcode: SQSUBv1i16 +/* 35347 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35360 +/* 35351 */ MCD_OPC_CheckPredicate, 0, 166, 20, // Skip to: 40641 +/* 35355 */ MCD_OPC_Decode, 196, 12, 130, 2, // Opcode: SQSUBv1i32 +/* 35360 */ MCD_OPC_FilterValue, 7, 157, 20, // Skip to: 40641 +/* 35364 */ MCD_OPC_CheckPredicate, 0, 153, 20, // Skip to: 40641 +/* 35368 */ MCD_OPC_Decode, 197, 12, 89, // Opcode: SQSUBv1i64 +/* 35372 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 35390 +/* 35376 */ MCD_OPC_CheckPredicate, 1, 141, 20, // Skip to: 40641 +/* 35380 */ MCD_OPC_CheckField, 21, 3, 0, 135, 20, // Skip to: 40641 +/* 35386 */ MCD_OPC_Decode, 158, 10, 120, // Opcode: SHA1SU0rrr +/* 35390 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 35408 +/* 35394 */ MCD_OPC_CheckPredicate, 0, 123, 20, // Skip to: 40641 +/* 35398 */ MCD_OPC_CheckField, 21, 3, 7, 117, 20, // Skip to: 40641 +/* 35404 */ MCD_OPC_Decode, 194, 1, 89, // Opcode: CMGTv1i64 +/* 35408 */ MCD_OPC_FilterValue, 14, 56, 0, // Skip to: 35468 +/* 35412 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 35415 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35428 +/* 35419 */ MCD_OPC_CheckPredicate, 0, 98, 20, // Skip to: 40641 +/* 35423 */ MCD_OPC_Decode, 187, 15, 156, 2, // Opcode: SUQADDv1i8 +/* 35428 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35441 +/* 35432 */ MCD_OPC_CheckPredicate, 0, 85, 20, // Skip to: 40641 +/* 35436 */ MCD_OPC_Decode, 184, 15, 157, 2, // Opcode: SUQADDv1i16 +/* 35441 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35455 +/* 35446 */ MCD_OPC_CheckPredicate, 0, 71, 20, // Skip to: 40641 +/* 35450 */ MCD_OPC_Decode, 185, 15, 158, 2, // Opcode: SUQADDv1i32 +/* 35455 */ MCD_OPC_FilterValue, 224, 1, 61, 20, // Skip to: 40641 +/* 35460 */ MCD_OPC_CheckPredicate, 0, 57, 20, // Skip to: 40641 +/* 35464 */ MCD_OPC_Decode, 186, 15, 99, // Opcode: SUQADDv1i64 +/* 35468 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 35486 +/* 35472 */ MCD_OPC_CheckPredicate, 0, 45, 20, // Skip to: 40641 +/* 35476 */ MCD_OPC_CheckField, 21, 3, 7, 39, 20, // Skip to: 40641 +/* 35482 */ MCD_OPC_Decode, 178, 1, 89, // Opcode: CMGEv1i64 +/* 35486 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 35504 +/* 35490 */ MCD_OPC_CheckPredicate, 1, 27, 20, // Skip to: 40641 +/* 35494 */ MCD_OPC_CheckField, 21, 3, 0, 21, 20, // Skip to: 40641 +/* 35500 */ MCD_OPC_Decode, 161, 10, 120, // Opcode: SHA256Hrrr +/* 35504 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 35522 +/* 35508 */ MCD_OPC_CheckPredicate, 0, 9, 20, // Skip to: 40641 +/* 35512 */ MCD_OPC_CheckField, 21, 3, 7, 3, 20, // Skip to: 40641 +/* 35518 */ MCD_OPC_Decode, 140, 13, 89, // Opcode: SSHLv1i64 +/* 35522 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 35569 +/* 35526 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 35529 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35542 +/* 35533 */ MCD_OPC_CheckPredicate, 0, 240, 19, // Skip to: 40641 +/* 35537 */ MCD_OPC_Decode, 208, 12, 159, 2, // Opcode: SQXTNv1i8 +/* 35542 */ MCD_OPC_FilterValue, 97, 9, 0, // Skip to: 35555 +/* 35546 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 40641 +/* 35550 */ MCD_OPC_Decode, 206, 12, 255, 1, // Opcode: SQXTNv1i16 +/* 35555 */ MCD_OPC_FilterValue, 161, 1, 217, 19, // Skip to: 40641 +/* 35560 */ MCD_OPC_CheckPredicate, 0, 213, 19, // Skip to: 40641 +/* 35564 */ MCD_OPC_Decode, 207, 12, 144, 1, // Opcode: SQXTNv1i32 +/* 35569 */ MCD_OPC_FilterValue, 19, 54, 0, // Skip to: 35627 +/* 35573 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35576 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35589 +/* 35580 */ MCD_OPC_CheckPredicate, 0, 193, 19, // Skip to: 40641 +/* 35584 */ MCD_OPC_Decode, 163, 12, 154, 2, // Opcode: SQSHLv1i8 +/* 35589 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35602 +/* 35593 */ MCD_OPC_CheckPredicate, 0, 180, 19, // Skip to: 40641 +/* 35597 */ MCD_OPC_Decode, 160, 12, 155, 2, // Opcode: SQSHLv1i16 +/* 35602 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35615 +/* 35606 */ MCD_OPC_CheckPredicate, 0, 167, 19, // Skip to: 40641 +/* 35610 */ MCD_OPC_Decode, 161, 12, 130, 2, // Opcode: SQSHLv1i32 +/* 35615 */ MCD_OPC_FilterValue, 7, 158, 19, // Skip to: 40641 +/* 35619 */ MCD_OPC_CheckPredicate, 0, 154, 19, // Skip to: 40641 +/* 35623 */ MCD_OPC_Decode, 162, 12, 89, // Opcode: SQSHLv1i64 +/* 35627 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 35645 +/* 35631 */ MCD_OPC_CheckPredicate, 1, 142, 19, // Skip to: 40641 +/* 35635 */ MCD_OPC_CheckField, 21, 3, 0, 136, 19, // Skip to: 40641 +/* 35641 */ MCD_OPC_Decode, 160, 10, 120, // Opcode: SHA256H2rrr +/* 35645 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 35663 +/* 35649 */ MCD_OPC_CheckPredicate, 0, 124, 19, // Skip to: 40641 +/* 35653 */ MCD_OPC_CheckField, 21, 3, 7, 118, 19, // Skip to: 40641 +/* 35659 */ MCD_OPC_Decode, 238, 12, 89, // Opcode: SRSHLv1i64 +/* 35663 */ MCD_OPC_FilterValue, 23, 54, 0, // Skip to: 35721 +/* 35667 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35670 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35683 +/* 35674 */ MCD_OPC_CheckPredicate, 0, 99, 19, // Skip to: 40641 +/* 35678 */ MCD_OPC_Decode, 246, 11, 154, 2, // Opcode: SQRSHLv1i8 +/* 35683 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35696 +/* 35687 */ MCD_OPC_CheckPredicate, 0, 86, 19, // Skip to: 40641 +/* 35691 */ MCD_OPC_Decode, 243, 11, 155, 2, // Opcode: SQRSHLv1i16 +/* 35696 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35709 +/* 35700 */ MCD_OPC_CheckPredicate, 0, 73, 19, // Skip to: 40641 +/* 35704 */ MCD_OPC_Decode, 244, 11, 130, 2, // Opcode: SQRSHLv1i32 +/* 35709 */ MCD_OPC_FilterValue, 7, 64, 19, // Skip to: 40641 +/* 35713 */ MCD_OPC_CheckPredicate, 0, 60, 19, // Skip to: 40641 +/* 35717 */ MCD_OPC_Decode, 245, 11, 89, // Opcode: SQRSHLv1i64 +/* 35721 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 35739 +/* 35725 */ MCD_OPC_CheckPredicate, 1, 48, 19, // Skip to: 40641 +/* 35729 */ MCD_OPC_CheckField, 21, 3, 0, 42, 19, // Skip to: 40641 +/* 35735 */ MCD_OPC_Decode, 163, 10, 120, // Opcode: SHA256SU1rrr +/* 35739 */ MCD_OPC_FilterValue, 30, 56, 0, // Skip to: 35799 +/* 35743 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 35746 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35759 +/* 35750 */ MCD_OPC_CheckPredicate, 0, 23, 19, // Skip to: 40641 +/* 35754 */ MCD_OPC_Decode, 153, 11, 160, 2, // Opcode: SQABSv1i8 +/* 35759 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35772 +/* 35763 */ MCD_OPC_CheckPredicate, 0, 10, 19, // Skip to: 40641 +/* 35767 */ MCD_OPC_Decode, 150, 11, 161, 2, // Opcode: SQABSv1i16 +/* 35772 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35786 +/* 35777 */ MCD_OPC_CheckPredicate, 0, 252, 18, // Skip to: 40641 +/* 35781 */ MCD_OPC_Decode, 151, 11, 253, 1, // Opcode: SQABSv1i32 +/* 35786 */ MCD_OPC_FilterValue, 224, 1, 242, 18, // Skip to: 40641 +/* 35791 */ MCD_OPC_CheckPredicate, 0, 238, 18, // Skip to: 40641 +/* 35795 */ MCD_OPC_Decode, 152, 11, 90, // Opcode: SQABSv1i64 +/* 35799 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 35816 +/* 35803 */ MCD_OPC_CheckPredicate, 0, 226, 18, // Skip to: 40641 +/* 35807 */ MCD_OPC_CheckField, 21, 3, 7, 220, 18, // Skip to: 40641 +/* 35813 */ MCD_OPC_Decode, 72, 89, // Opcode: ADDv1i64 +/* 35816 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 35835 +/* 35820 */ MCD_OPC_CheckPredicate, 0, 209, 18, // Skip to: 40641 +/* 35824 */ MCD_OPC_CheckField, 16, 8, 224, 1, 202, 18, // Skip to: 40641 +/* 35831 */ MCD_OPC_Decode, 195, 1, 90, // Opcode: CMGTv1i64rz +/* 35835 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 35853 +/* 35839 */ MCD_OPC_CheckPredicate, 0, 190, 18, // Skip to: 40641 +/* 35843 */ MCD_OPC_CheckField, 21, 3, 7, 184, 18, // Skip to: 40641 +/* 35849 */ MCD_OPC_Decode, 241, 1, 89, // Opcode: CMTSTv1i64 +/* 35853 */ MCD_OPC_FilterValue, 36, 29, 0, // Skip to: 35886 +/* 35857 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35860 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35873 +/* 35864 */ MCD_OPC_CheckPredicate, 0, 165, 18, // Skip to: 40641 +/* 35868 */ MCD_OPC_Decode, 171, 11, 162, 2, // Opcode: SQDMLALi16 +/* 35873 */ MCD_OPC_FilterValue, 5, 156, 18, // Skip to: 40641 +/* 35877 */ MCD_OPC_CheckPredicate, 0, 152, 18, // Skip to: 40641 +/* 35881 */ MCD_OPC_Decode, 172, 11, 163, 2, // Opcode: SQDMLALi32 +/* 35886 */ MCD_OPC_FilterValue, 38, 15, 0, // Skip to: 35905 +/* 35890 */ MCD_OPC_CheckPredicate, 0, 139, 18, // Skip to: 40641 +/* 35894 */ MCD_OPC_CheckField, 16, 8, 224, 1, 132, 18, // Skip to: 40641 +/* 35901 */ MCD_OPC_Decode, 163, 1, 90, // Opcode: CMEQv1i64rz +/* 35905 */ MCD_OPC_FilterValue, 42, 68, 0, // Skip to: 35977 +/* 35909 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 35912 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35925 +/* 35916 */ MCD_OPC_CheckPredicate, 0, 113, 18, // Skip to: 40641 +/* 35920 */ MCD_OPC_Decode, 184, 3, 253, 1, // Opcode: FCVTNSv1i32 +/* 35925 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 35937 +/* 35929 */ MCD_OPC_CheckPredicate, 0, 100, 18, // Skip to: 40641 +/* 35933 */ MCD_OPC_Decode, 185, 3, 90, // Opcode: FCVTNSv1i64 +/* 35937 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 35951 +/* 35942 */ MCD_OPC_CheckPredicate, 0, 87, 18, // Skip to: 40641 +/* 35946 */ MCD_OPC_Decode, 206, 3, 253, 1, // Opcode: FCVTPSv1i32 +/* 35951 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 35964 +/* 35956 */ MCD_OPC_CheckPredicate, 0, 73, 18, // Skip to: 40641 +/* 35960 */ MCD_OPC_Decode, 233, 1, 90, // Opcode: CMLTv1i64rz +/* 35964 */ MCD_OPC_FilterValue, 225, 1, 64, 18, // Skip to: 40641 +/* 35969 */ MCD_OPC_CheckPredicate, 0, 60, 18, // Skip to: 40641 +/* 35973 */ MCD_OPC_Decode, 207, 3, 90, // Opcode: FCVTPSv1i64 +/* 35977 */ MCD_OPC_FilterValue, 44, 29, 0, // Skip to: 36010 +/* 35981 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 35984 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35997 +/* 35988 */ MCD_OPC_CheckPredicate, 0, 41, 18, // Skip to: 40641 +/* 35992 */ MCD_OPC_Decode, 183, 11, 162, 2, // Opcode: SQDMLSLi16 +/* 35997 */ MCD_OPC_FilterValue, 5, 32, 18, // Skip to: 40641 +/* 36001 */ MCD_OPC_CheckPredicate, 0, 28, 18, // Skip to: 40641 +/* 36005 */ MCD_OPC_Decode, 184, 11, 163, 2, // Opcode: SQDMLSLi32 +/* 36010 */ MCD_OPC_FilterValue, 45, 29, 0, // Skip to: 36043 +/* 36014 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 36017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36030 +/* 36021 */ MCD_OPC_CheckPredicate, 0, 8, 18, // Skip to: 40641 +/* 36025 */ MCD_OPC_Decode, 195, 11, 155, 2, // Opcode: SQDMULHv1i16 +/* 36030 */ MCD_OPC_FilterValue, 5, 255, 17, // Skip to: 40641 +/* 36034 */ MCD_OPC_CheckPredicate, 0, 251, 17, // Skip to: 40641 +/* 36038 */ MCD_OPC_Decode, 197, 11, 130, 2, // Opcode: SQDMULHv1i32 +/* 36043 */ MCD_OPC_FilterValue, 46, 79, 0, // Skip to: 36126 +/* 36047 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 36050 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36063 +/* 36054 */ MCD_OPC_CheckPredicate, 0, 231, 17, // Skip to: 40641 +/* 36058 */ MCD_OPC_Decode, 166, 3, 253, 1, // Opcode: FCVTMSv1i32 +/* 36063 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36075 +/* 36067 */ MCD_OPC_CheckPredicate, 0, 218, 17, // Skip to: 40641 +/* 36071 */ MCD_OPC_Decode, 167, 3, 90, // Opcode: FCVTMSv1i64 +/* 36075 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36089 +/* 36080 */ MCD_OPC_CheckPredicate, 0, 205, 17, // Skip to: 40641 +/* 36084 */ MCD_OPC_Decode, 246, 3, 253, 1, // Opcode: FCVTZSv1i32 +/* 36089 */ MCD_OPC_FilterValue, 224, 1, 7, 0, // Skip to: 36101 +/* 36094 */ MCD_OPC_CheckPredicate, 0, 191, 17, // Skip to: 40641 +/* 36098 */ MCD_OPC_Decode, 23, 90, // Opcode: ABSv1i64 +/* 36101 */ MCD_OPC_FilterValue, 225, 1, 8, 0, // Skip to: 36114 +/* 36106 */ MCD_OPC_CheckPredicate, 0, 179, 17, // Skip to: 40641 +/* 36110 */ MCD_OPC_Decode, 247, 3, 90, // Opcode: FCVTZSv1i64 +/* 36114 */ MCD_OPC_FilterValue, 241, 1, 170, 17, // Skip to: 40641 +/* 36119 */ MCD_OPC_CheckPredicate, 0, 166, 17, // Skip to: 40641 +/* 36123 */ MCD_OPC_Decode, 43, 95, // Opcode: ADDPv2i64p +/* 36126 */ MCD_OPC_FilterValue, 50, 55, 0, // Skip to: 36185 +/* 36130 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 36133 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36146 +/* 36137 */ MCD_OPC_CheckPredicate, 0, 148, 17, // Skip to: 40641 +/* 36141 */ MCD_OPC_Decode, 140, 3, 253, 1, // Opcode: FCVTASv1i32 +/* 36146 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36158 +/* 36150 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 40641 +/* 36154 */ MCD_OPC_Decode, 141, 3, 90, // Opcode: FCVTASv1i64 +/* 36158 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36172 +/* 36163 */ MCD_OPC_CheckPredicate, 0, 122, 17, // Skip to: 40641 +/* 36167 */ MCD_OPC_Decode, 236, 2, 253, 1, // Opcode: FCMGTv1i32rz +/* 36172 */ MCD_OPC_FilterValue, 224, 1, 112, 17, // Skip to: 40641 +/* 36177 */ MCD_OPC_CheckPredicate, 0, 108, 17, // Skip to: 40641 +/* 36181 */ MCD_OPC_Decode, 237, 2, 90, // Opcode: FCMGTv1i64rz +/* 36185 */ MCD_OPC_FilterValue, 52, 29, 0, // Skip to: 36218 +/* 36189 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 36192 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36205 +/* 36196 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 40641 +/* 36200 */ MCD_OPC_Decode, 207, 11, 164, 2, // Opcode: SQDMULLi16 +/* 36205 */ MCD_OPC_FilterValue, 5, 80, 17, // Skip to: 40641 +/* 36209 */ MCD_OPC_CheckPredicate, 0, 76, 17, // Skip to: 40641 +/* 36213 */ MCD_OPC_Decode, 208, 11, 165, 2, // Opcode: SQDMULLi32 +/* 36218 */ MCD_OPC_FilterValue, 54, 82, 0, // Skip to: 36304 +/* 36222 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 36225 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36238 +/* 36229 */ MCD_OPC_CheckPredicate, 0, 56, 17, // Skip to: 40641 +/* 36233 */ MCD_OPC_Decode, 142, 10, 253, 1, // Opcode: SCVTFv1i32 +/* 36238 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36250 +/* 36242 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 40641 +/* 36246 */ MCD_OPC_Decode, 143, 10, 90, // Opcode: SCVTFv1i64 +/* 36250 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36264 +/* 36255 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 40641 +/* 36259 */ MCD_OPC_Decode, 216, 2, 253, 1, // Opcode: FCMEQv1i32rz +/* 36264 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36278 +/* 36269 */ MCD_OPC_CheckPredicate, 0, 16, 17, // Skip to: 40641 +/* 36273 */ MCD_OPC_Decode, 140, 5, 253, 1, // Opcode: FRECPEv1i32 +/* 36278 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 36291 +/* 36283 */ MCD_OPC_CheckPredicate, 0, 2, 17, // Skip to: 40641 +/* 36287 */ MCD_OPC_Decode, 217, 2, 90, // Opcode: FCMEQv1i64rz +/* 36291 */ MCD_OPC_FilterValue, 225, 1, 249, 16, // Skip to: 40641 +/* 36296 */ MCD_OPC_CheckPredicate, 0, 245, 16, // Skip to: 40641 +/* 36300 */ MCD_OPC_Decode, 141, 5, 90, // Opcode: FRECPEv1i64 +/* 36304 */ MCD_OPC_FilterValue, 55, 28, 0, // Skip to: 36336 +/* 36308 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 36311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36324 +/* 36315 */ MCD_OPC_CheckPredicate, 0, 226, 16, // Skip to: 40641 +/* 36319 */ MCD_OPC_Decode, 239, 4, 130, 2, // Opcode: FMULX32 +/* 36324 */ MCD_OPC_FilterValue, 3, 217, 16, // Skip to: 40641 +/* 36328 */ MCD_OPC_CheckPredicate, 0, 213, 16, // Skip to: 40641 +/* 36332 */ MCD_OPC_Decode, 240, 4, 89, // Opcode: FMULX64 +/* 36336 */ MCD_OPC_FilterValue, 57, 28, 0, // Skip to: 36368 +/* 36340 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 36343 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36356 +/* 36347 */ MCD_OPC_CheckPredicate, 0, 194, 16, // Skip to: 40641 +/* 36351 */ MCD_OPC_Decode, 214, 2, 130, 2, // Opcode: FCMEQ32 +/* 36356 */ MCD_OPC_FilterValue, 3, 185, 16, // Skip to: 40641 +/* 36360 */ MCD_OPC_CheckPredicate, 0, 181, 16, // Skip to: 40641 +/* 36364 */ MCD_OPC_Decode, 215, 2, 89, // Opcode: FCMEQ64 +/* 36368 */ MCD_OPC_FilterValue, 58, 30, 0, // Skip to: 36402 +/* 36372 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 36375 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36389 +/* 36380 */ MCD_OPC_CheckPredicate, 0, 161, 16, // Skip to: 40641 +/* 36384 */ MCD_OPC_Decode, 249, 2, 253, 1, // Opcode: FCMLTv1i32rz +/* 36389 */ MCD_OPC_FilterValue, 224, 1, 151, 16, // Skip to: 40641 +/* 36394 */ MCD_OPC_CheckPredicate, 0, 147, 16, // Skip to: 40641 +/* 36398 */ MCD_OPC_Decode, 250, 2, 90, // Opcode: FCMLTv1i64rz +/* 36402 */ MCD_OPC_FilterValue, 62, 30, 0, // Skip to: 36436 +/* 36406 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 36409 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36423 +/* 36414 */ MCD_OPC_CheckPredicate, 0, 127, 16, // Skip to: 40641 +/* 36418 */ MCD_OPC_Decode, 150, 5, 253, 1, // Opcode: FRECPXv1i32 +/* 36423 */ MCD_OPC_FilterValue, 225, 1, 117, 16, // Skip to: 40641 +/* 36428 */ MCD_OPC_CheckPredicate, 0, 113, 16, // Skip to: 40641 +/* 36432 */ MCD_OPC_Decode, 151, 5, 90, // Opcode: FRECPXv1i64 +/* 36436 */ MCD_OPC_FilterValue, 63, 105, 16, // Skip to: 40641 +/* 36440 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 36443 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36456 +/* 36447 */ MCD_OPC_CheckPredicate, 0, 94, 16, // Skip to: 40641 +/* 36451 */ MCD_OPC_Decode, 145, 5, 130, 2, // Opcode: FRECPS32 +/* 36456 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 36468 +/* 36460 */ MCD_OPC_CheckPredicate, 0, 81, 16, // Skip to: 40641 +/* 36464 */ MCD_OPC_Decode, 146, 5, 89, // Opcode: FRECPS64 +/* 36468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 36481 +/* 36472 */ MCD_OPC_CheckPredicate, 0, 69, 16, // Skip to: 40641 +/* 36476 */ MCD_OPC_Decode, 192, 5, 130, 2, // Opcode: FRSQRTS32 +/* 36481 */ MCD_OPC_FilterValue, 7, 60, 16, // Skip to: 40641 +/* 36485 */ MCD_OPC_CheckPredicate, 0, 56, 16, // Skip to: 40641 +/* 36489 */ MCD_OPC_Decode, 193, 5, 89, // Opcode: FRSQRTS64 +/* 36493 */ MCD_OPC_FilterValue, 3, 48, 16, // Skip to: 40641 +/* 36497 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 36500 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36525 +/* 36504 */ MCD_OPC_CheckPredicate, 0, 37, 16, // Skip to: 40641 +/* 36508 */ MCD_OPC_CheckField, 22, 2, 1, 31, 16, // Skip to: 40641 +/* 36514 */ MCD_OPC_CheckField, 10, 2, 1, 25, 16, // Skip to: 40641 +/* 36520 */ MCD_OPC_Decode, 147, 13, 166, 2, // Opcode: SSHRd +/* 36525 */ MCD_OPC_FilterValue, 1, 66, 0, // Skip to: 36595 +/* 36529 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 36532 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36551 +/* 36536 */ MCD_OPC_CheckPredicate, 0, 5, 16, // Skip to: 40641 +/* 36540 */ MCD_OPC_CheckField, 10, 2, 1, 255, 15, // Skip to: 40641 +/* 36546 */ MCD_OPC_Decode, 155, 13, 167, 2, // Opcode: SSRAd +/* 36551 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36570 +/* 36555 */ MCD_OPC_CheckPredicate, 0, 242, 15, // Skip to: 40641 +/* 36559 */ MCD_OPC_CheckField, 10, 1, 0, 236, 15, // Skip to: 40641 +/* 36565 */ MCD_OPC_Decode, 206, 4, 168, 2, // Opcode: FMLAv1i32_indexed +/* 36570 */ MCD_OPC_FilterValue, 3, 227, 15, // Skip to: 40641 +/* 36574 */ MCD_OPC_CheckPredicate, 0, 223, 15, // Skip to: 40641 +/* 36578 */ MCD_OPC_CheckField, 21, 1, 0, 217, 15, // Skip to: 40641 +/* 36584 */ MCD_OPC_CheckField, 10, 1, 0, 211, 15, // Skip to: 40641 +/* 36590 */ MCD_OPC_Decode, 207, 4, 169, 2, // Opcode: FMLAv1i64_indexed +/* 36595 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 36620 +/* 36599 */ MCD_OPC_CheckPredicate, 0, 198, 15, // Skip to: 40641 +/* 36603 */ MCD_OPC_CheckField, 22, 2, 1, 192, 15, // Skip to: 40641 +/* 36609 */ MCD_OPC_CheckField, 10, 2, 1, 186, 15, // Skip to: 40641 +/* 36615 */ MCD_OPC_Decode, 245, 12, 166, 2, // Opcode: SRSHRd +/* 36620 */ MCD_OPC_FilterValue, 3, 61, 0, // Skip to: 36685 +/* 36624 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 36627 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 36660 +/* 36631 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 36634 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36647 +/* 36638 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 40641 +/* 36642 */ MCD_OPC_Decode, 173, 11, 170, 2, // Opcode: SQDMLALv1i32_indexed +/* 36647 */ MCD_OPC_FilterValue, 2, 150, 15, // Skip to: 40641 +/* 36651 */ MCD_OPC_CheckPredicate, 0, 146, 15, // Skip to: 40641 +/* 36655 */ MCD_OPC_Decode, 174, 11, 171, 2, // Opcode: SQDMLALv1i64_indexed +/* 36660 */ MCD_OPC_FilterValue, 1, 137, 15, // Skip to: 40641 +/* 36664 */ MCD_OPC_CheckPredicate, 0, 133, 15, // Skip to: 40641 +/* 36668 */ MCD_OPC_CheckField, 22, 2, 1, 127, 15, // Skip to: 40641 +/* 36674 */ MCD_OPC_CheckField, 11, 1, 0, 121, 15, // Skip to: 40641 +/* 36680 */ MCD_OPC_Decode, 253, 12, 167, 2, // Opcode: SRSRAd +/* 36685 */ MCD_OPC_FilterValue, 5, 66, 0, // Skip to: 36755 +/* 36689 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 36692 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36711 +/* 36696 */ MCD_OPC_CheckPredicate, 0, 101, 15, // Skip to: 40641 +/* 36700 */ MCD_OPC_CheckField, 10, 2, 1, 95, 15, // Skip to: 40641 +/* 36706 */ MCD_OPC_Decode, 176, 10, 172, 2, // Opcode: SHLd +/* 36711 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36730 +/* 36715 */ MCD_OPC_CheckPredicate, 0, 82, 15, // Skip to: 40641 +/* 36719 */ MCD_OPC_CheckField, 10, 1, 0, 76, 15, // Skip to: 40641 +/* 36725 */ MCD_OPC_Decode, 214, 4, 168, 2, // Opcode: FMLSv1i32_indexed +/* 36730 */ MCD_OPC_FilterValue, 3, 67, 15, // Skip to: 40641 +/* 36734 */ MCD_OPC_CheckPredicate, 0, 63, 15, // Skip to: 40641 +/* 36738 */ MCD_OPC_CheckField, 21, 1, 0, 57, 15, // Skip to: 40641 +/* 36744 */ MCD_OPC_CheckField, 10, 1, 0, 51, 15, // Skip to: 40641 +/* 36750 */ MCD_OPC_Decode, 215, 4, 169, 2, // Opcode: FMLSv1i64_indexed +/* 36755 */ MCD_OPC_FilterValue, 7, 138, 0, // Skip to: 36897 +/* 36759 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 36762 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 36839 +/* 36766 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36769 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 36820 +/* 36773 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 36776 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36801 +/* 36780 */ MCD_OPC_CheckPredicate, 0, 17, 15, // Skip to: 40641 +/* 36784 */ MCD_OPC_CheckField, 19, 1, 1, 11, 15, // Skip to: 40641 +/* 36790 */ MCD_OPC_CheckField, 10, 2, 1, 5, 15, // Skip to: 40641 +/* 36796 */ MCD_OPC_Decode, 154, 12, 173, 2, // Opcode: SQSHLb +/* 36801 */ MCD_OPC_FilterValue, 1, 252, 14, // Skip to: 40641 +/* 36805 */ MCD_OPC_CheckPredicate, 0, 248, 14, // Skip to: 40641 +/* 36809 */ MCD_OPC_CheckField, 10, 2, 1, 242, 14, // Skip to: 40641 +/* 36815 */ MCD_OPC_Decode, 156, 12, 174, 2, // Opcode: SQSHLh +/* 36820 */ MCD_OPC_FilterValue, 1, 233, 14, // Skip to: 40641 +/* 36824 */ MCD_OPC_CheckPredicate, 0, 229, 14, // Skip to: 40641 +/* 36828 */ MCD_OPC_CheckField, 10, 2, 1, 223, 14, // Skip to: 40641 +/* 36834 */ MCD_OPC_Decode, 157, 12, 175, 2, // Opcode: SQSHLs +/* 36839 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 36878 +/* 36843 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 36846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 36859 +/* 36850 */ MCD_OPC_CheckPredicate, 0, 203, 14, // Skip to: 40641 +/* 36854 */ MCD_OPC_Decode, 185, 11, 170, 2, // Opcode: SQDMLSLv1i32_indexed +/* 36859 */ MCD_OPC_FilterValue, 1, 194, 14, // Skip to: 40641 +/* 36863 */ MCD_OPC_CheckPredicate, 0, 190, 14, // Skip to: 40641 +/* 36867 */ MCD_OPC_CheckField, 11, 1, 0, 184, 14, // Skip to: 40641 +/* 36873 */ MCD_OPC_Decode, 155, 12, 172, 2, // Opcode: SQSHLd +/* 36878 */ MCD_OPC_FilterValue, 2, 175, 14, // Skip to: 40641 +/* 36882 */ MCD_OPC_CheckPredicate, 0, 171, 14, // Skip to: 40641 +/* 36886 */ MCD_OPC_CheckField, 10, 1, 0, 165, 14, // Skip to: 40641 +/* 36892 */ MCD_OPC_Decode, 186, 11, 171, 2, // Opcode: SQDMLSLv1i64_indexed +/* 36897 */ MCD_OPC_FilterValue, 9, 172, 0, // Skip to: 37073 +/* 36901 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 36904 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 37029 +/* 36908 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 36911 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 36970 +/* 36915 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36918 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 36957 +/* 36922 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 36925 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 36944 +/* 36929 */ MCD_OPC_CheckPredicate, 0, 124, 14, // Skip to: 40641 +/* 36933 */ MCD_OPC_CheckField, 19, 1, 1, 118, 14, // Skip to: 40641 +/* 36939 */ MCD_OPC_Decode, 176, 12, 176, 2, // Opcode: SQSHRNb +/* 36944 */ MCD_OPC_FilterValue, 1, 109, 14, // Skip to: 40641 +/* 36948 */ MCD_OPC_CheckPredicate, 0, 105, 14, // Skip to: 40641 +/* 36952 */ MCD_OPC_Decode, 177, 12, 177, 2, // Opcode: SQSHRNh +/* 36957 */ MCD_OPC_FilterValue, 1, 96, 14, // Skip to: 40641 +/* 36961 */ MCD_OPC_CheckPredicate, 0, 92, 14, // Skip to: 40641 +/* 36965 */ MCD_OPC_Decode, 178, 12, 178, 2, // Opcode: SQSHRNs +/* 36970 */ MCD_OPC_FilterValue, 3, 83, 14, // Skip to: 40641 +/* 36974 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36977 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 37016 +/* 36981 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 36984 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 37003 +/* 36988 */ MCD_OPC_CheckPredicate, 0, 65, 14, // Skip to: 40641 +/* 36992 */ MCD_OPC_CheckField, 19, 1, 1, 59, 14, // Skip to: 40641 +/* 36998 */ MCD_OPC_Decode, 253, 11, 176, 2, // Opcode: SQRSHRNb +/* 37003 */ MCD_OPC_FilterValue, 1, 50, 14, // Skip to: 40641 +/* 37007 */ MCD_OPC_CheckPredicate, 0, 46, 14, // Skip to: 40641 +/* 37011 */ MCD_OPC_Decode, 254, 11, 177, 2, // Opcode: SQRSHRNh +/* 37016 */ MCD_OPC_FilterValue, 1, 37, 14, // Skip to: 40641 +/* 37020 */ MCD_OPC_CheckPredicate, 0, 33, 14, // Skip to: 40641 +/* 37024 */ MCD_OPC_Decode, 255, 11, 178, 2, // Opcode: SQRSHRNs +/* 37029 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 37048 +/* 37033 */ MCD_OPC_CheckPredicate, 0, 20, 14, // Skip to: 40641 +/* 37037 */ MCD_OPC_CheckField, 10, 1, 0, 14, 14, // Skip to: 40641 +/* 37043 */ MCD_OPC_Decode, 249, 4, 179, 2, // Opcode: FMULv1i32_indexed +/* 37048 */ MCD_OPC_FilterValue, 3, 5, 14, // Skip to: 40641 +/* 37052 */ MCD_OPC_CheckPredicate, 0, 1, 14, // Skip to: 40641 +/* 37056 */ MCD_OPC_CheckField, 21, 1, 0, 251, 13, // Skip to: 40641 +/* 37062 */ MCD_OPC_CheckField, 10, 1, 0, 245, 13, // Skip to: 40641 +/* 37068 */ MCD_OPC_Decode, 250, 4, 180, 2, // Opcode: FMULv1i64_indexed +/* 37073 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 37118 +/* 37077 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 37080 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37099 +/* 37084 */ MCD_OPC_CheckPredicate, 0, 225, 13, // Skip to: 40641 +/* 37088 */ MCD_OPC_CheckField, 10, 1, 0, 219, 13, // Skip to: 40641 +/* 37094 */ MCD_OPC_Decode, 209, 11, 181, 2, // Opcode: SQDMULLv1i32_indexed +/* 37099 */ MCD_OPC_FilterValue, 2, 210, 13, // Skip to: 40641 +/* 37103 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 40641 +/* 37107 */ MCD_OPC_CheckField, 10, 1, 0, 200, 13, // Skip to: 40641 +/* 37113 */ MCD_OPC_Decode, 210, 11, 182, 2, // Opcode: SQDMULLv1i64_indexed +/* 37118 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 37163 +/* 37122 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 37125 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37144 +/* 37129 */ MCD_OPC_CheckPredicate, 0, 180, 13, // Skip to: 40641 +/* 37133 */ MCD_OPC_CheckField, 10, 1, 0, 174, 13, // Skip to: 40641 +/* 37139 */ MCD_OPC_Decode, 196, 11, 183, 2, // Opcode: SQDMULHv1i16_indexed +/* 37144 */ MCD_OPC_FilterValue, 2, 165, 13, // Skip to: 40641 +/* 37148 */ MCD_OPC_CheckPredicate, 0, 161, 13, // Skip to: 40641 +/* 37152 */ MCD_OPC_CheckField, 10, 1, 0, 155, 13, // Skip to: 40641 +/* 37158 */ MCD_OPC_Decode, 198, 11, 179, 2, // Opcode: SQDMULHv1i32_indexed +/* 37163 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 37208 +/* 37167 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 37170 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37189 +/* 37174 */ MCD_OPC_CheckPredicate, 0, 135, 13, // Skip to: 40641 +/* 37178 */ MCD_OPC_CheckField, 10, 1, 0, 129, 13, // Skip to: 40641 +/* 37184 */ MCD_OPC_Decode, 231, 11, 183, 2, // Opcode: SQRDMULHv1i16_indexed +/* 37189 */ MCD_OPC_FilterValue, 2, 120, 13, // Skip to: 40641 +/* 37193 */ MCD_OPC_CheckPredicate, 0, 116, 13, // Skip to: 40641 +/* 37197 */ MCD_OPC_CheckField, 10, 1, 0, 110, 13, // Skip to: 40641 +/* 37203 */ MCD_OPC_Decode, 233, 11, 179, 2, // Opcode: SQRDMULHv1i32_indexed +/* 37208 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 37259 +/* 37212 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 37215 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37240 +/* 37219 */ MCD_OPC_CheckPredicate, 0, 90, 13, // Skip to: 40641 +/* 37223 */ MCD_OPC_CheckField, 21, 1, 1, 84, 13, // Skip to: 40641 +/* 37229 */ MCD_OPC_CheckField, 10, 2, 1, 78, 13, // Skip to: 40641 +/* 37235 */ MCD_OPC_Decode, 141, 10, 184, 2, // Opcode: SCVTFs +/* 37240 */ MCD_OPC_FilterValue, 1, 69, 13, // Skip to: 40641 +/* 37244 */ MCD_OPC_CheckPredicate, 0, 65, 13, // Skip to: 40641 +/* 37248 */ MCD_OPC_CheckField, 10, 2, 1, 59, 13, // Skip to: 40641 +/* 37254 */ MCD_OPC_Decode, 140, 10, 166, 2, // Opcode: SCVTFd +/* 37259 */ MCD_OPC_FilterValue, 15, 50, 13, // Skip to: 40641 +/* 37263 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 37266 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37291 +/* 37270 */ MCD_OPC_CheckPredicate, 0, 39, 13, // Skip to: 40641 +/* 37274 */ MCD_OPC_CheckField, 21, 1, 1, 33, 13, // Skip to: 40641 +/* 37280 */ MCD_OPC_CheckField, 10, 2, 3, 27, 13, // Skip to: 40641 +/* 37286 */ MCD_OPC_Decode, 245, 3, 184, 2, // Opcode: FCVTZSs +/* 37291 */ MCD_OPC_FilterValue, 1, 18, 13, // Skip to: 40641 +/* 37295 */ MCD_OPC_CheckPredicate, 0, 14, 13, // Skip to: 40641 +/* 37299 */ MCD_OPC_CheckField, 10, 2, 3, 8, 13, // Skip to: 40641 +/* 37305 */ MCD_OPC_Decode, 244, 3, 166, 2, // Opcode: FCVTZSd +/* 37310 */ MCD_OPC_FilterValue, 3, 212, 8, // Skip to: 39574 +/* 37314 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 37317 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 37406 +/* 37321 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 37324 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37339 +/* 37328 */ MCD_OPC_CheckField, 21, 1, 0, 235, 12, // Skip to: 40641 +/* 37334 */ MCD_OPC_Decode, 140, 15, 226, 1, // Opcode: STURHi +/* 37339 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37354 +/* 37343 */ MCD_OPC_CheckField, 21, 1, 0, 220, 12, // Skip to: 40641 +/* 37349 */ MCD_OPC_Decode, 235, 14, 226, 1, // Opcode: STRHpost +/* 37354 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37391 +/* 37358 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 37361 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37376 +/* 37365 */ MCD_OPC_CheckField, 21, 1, 1, 198, 12, // Skip to: 40641 +/* 37371 */ MCD_OPC_Decode, 237, 14, 185, 2, // Opcode: STRHroW +/* 37376 */ MCD_OPC_FilterValue, 3, 189, 12, // Skip to: 40641 +/* 37380 */ MCD_OPC_CheckField, 21, 1, 1, 183, 12, // Skip to: 40641 +/* 37386 */ MCD_OPC_Decode, 238, 14, 186, 2, // Opcode: STRHroX +/* 37391 */ MCD_OPC_FilterValue, 3, 174, 12, // Skip to: 40641 +/* 37395 */ MCD_OPC_CheckField, 21, 1, 0, 168, 12, // Skip to: 40641 +/* 37401 */ MCD_OPC_Decode, 236, 14, 226, 1, // Opcode: STRHpre +/* 37406 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 37495 +/* 37410 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 37413 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37428 +/* 37417 */ MCD_OPC_CheckField, 21, 1, 0, 146, 12, // Skip to: 40641 +/* 37423 */ MCD_OPC_Decode, 159, 8, 226, 1, // Opcode: LDURHi +/* 37428 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37443 +/* 37432 */ MCD_OPC_CheckField, 21, 1, 0, 131, 12, // Skip to: 40641 +/* 37438 */ MCD_OPC_Decode, 219, 7, 226, 1, // Opcode: LDRHpost +/* 37443 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37480 +/* 37447 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 37450 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37465 +/* 37454 */ MCD_OPC_CheckField, 21, 1, 1, 109, 12, // Skip to: 40641 +/* 37460 */ MCD_OPC_Decode, 221, 7, 185, 2, // Opcode: LDRHroW +/* 37465 */ MCD_OPC_FilterValue, 3, 100, 12, // Skip to: 40641 +/* 37469 */ MCD_OPC_CheckField, 21, 1, 1, 94, 12, // Skip to: 40641 +/* 37475 */ MCD_OPC_Decode, 222, 7, 186, 2, // Opcode: LDRHroX +/* 37480 */ MCD_OPC_FilterValue, 3, 85, 12, // Skip to: 40641 +/* 37484 */ MCD_OPC_CheckField, 21, 1, 0, 79, 12, // Skip to: 40641 +/* 37490 */ MCD_OPC_Decode, 220, 7, 226, 1, // Opcode: LDRHpre +/* 37495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 37504 +/* 37499 */ MCD_OPC_Decode, 239, 14, 231, 1, // Opcode: STRHui +/* 37504 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 37513 +/* 37508 */ MCD_OPC_Decode, 223, 7, 231, 1, // Opcode: LDRHui +/* 37513 */ MCD_OPC_FilterValue, 8, 60, 1, // Skip to: 37833 +/* 37517 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 37520 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37539 +/* 37524 */ MCD_OPC_CheckPredicate, 0, 41, 12, // Skip to: 40641 +/* 37528 */ MCD_OPC_CheckField, 21, 1, 1, 35, 12, // Skip to: 40641 +/* 37534 */ MCD_OPC_Decode, 143, 17, 154, 2, // Opcode: UQADDv1i8 +/* 37539 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37558 +/* 37543 */ MCD_OPC_CheckPredicate, 0, 22, 12, // Skip to: 40641 +/* 37547 */ MCD_OPC_CheckField, 16, 6, 33, 16, 12, // Skip to: 40641 +/* 37553 */ MCD_OPC_Decode, 217, 12, 159, 2, // Opcode: SQXTUNv1i8 +/* 37558 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37577 +/* 37562 */ MCD_OPC_CheckPredicate, 0, 3, 12, // Skip to: 40641 +/* 37566 */ MCD_OPC_CheckField, 21, 1, 1, 253, 11, // Skip to: 40641 +/* 37572 */ MCD_OPC_Decode, 205, 17, 154, 2, // Opcode: UQSUBv1i8 +/* 37577 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37596 +/* 37581 */ MCD_OPC_CheckPredicate, 0, 240, 11, // Skip to: 40641 +/* 37585 */ MCD_OPC_CheckField, 16, 6, 32, 234, 11, // Skip to: 40641 +/* 37591 */ MCD_OPC_Decode, 153, 18, 156, 2, // Opcode: USQADDv1i8 +/* 37596 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37615 +/* 37600 */ MCD_OPC_CheckPredicate, 0, 221, 11, // Skip to: 40641 +/* 37604 */ MCD_OPC_CheckField, 16, 6, 33, 215, 11, // Skip to: 40641 +/* 37610 */ MCD_OPC_Decode, 215, 17, 159, 2, // Opcode: UQXTNv1i8 +/* 37615 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37634 +/* 37619 */ MCD_OPC_CheckPredicate, 0, 202, 11, // Skip to: 40641 +/* 37623 */ MCD_OPC_CheckField, 21, 1, 1, 196, 11, // Skip to: 40641 +/* 37629 */ MCD_OPC_Decode, 179, 17, 154, 2, // Opcode: UQSHLv1i8 +/* 37634 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 37653 +/* 37638 */ MCD_OPC_CheckPredicate, 0, 183, 11, // Skip to: 40641 +/* 37642 */ MCD_OPC_CheckField, 21, 1, 1, 177, 11, // Skip to: 40641 +/* 37648 */ MCD_OPC_Decode, 154, 17, 154, 2, // Opcode: UQRSHLv1i8 +/* 37653 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 37672 +/* 37657 */ MCD_OPC_CheckPredicate, 0, 164, 11, // Skip to: 40641 +/* 37661 */ MCD_OPC_CheckField, 16, 6, 32, 158, 11, // Skip to: 40641 +/* 37667 */ MCD_OPC_Decode, 223, 11, 160, 2, // Opcode: SQNEGv1i8 +/* 37672 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 37691 +/* 37676 */ MCD_OPC_CheckPredicate, 0, 145, 11, // Skip to: 40641 +/* 37680 */ MCD_OPC_CheckField, 16, 6, 33, 139, 11, // Skip to: 40641 +/* 37686 */ MCD_OPC_Decode, 193, 3, 253, 1, // Opcode: FCVTNUv1i32 +/* 37691 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 37710 +/* 37695 */ MCD_OPC_CheckPredicate, 0, 126, 11, // Skip to: 40641 +/* 37699 */ MCD_OPC_CheckField, 16, 6, 33, 120, 11, // Skip to: 40641 +/* 37705 */ MCD_OPC_Decode, 175, 3, 253, 1, // Opcode: FCVTMUv1i32 +/* 37710 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 37743 +/* 37714 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 37717 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37730 +/* 37721 */ MCD_OPC_CheckPredicate, 0, 100, 11, // Skip to: 40641 +/* 37725 */ MCD_OPC_Decode, 149, 3, 253, 1, // Opcode: FCVTAUv1i32 +/* 37730 */ MCD_OPC_FilterValue, 48, 91, 11, // Skip to: 40641 +/* 37734 */ MCD_OPC_CheckPredicate, 0, 87, 11, // Skip to: 40641 +/* 37738 */ MCD_OPC_Decode, 166, 4, 144, 1, // Opcode: FMAXNMPv2i32p +/* 37743 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 37776 +/* 37747 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 37750 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37763 +/* 37754 */ MCD_OPC_CheckPredicate, 0, 67, 11, // Skip to: 40641 +/* 37758 */ MCD_OPC_Decode, 172, 16, 253, 1, // Opcode: UCVTFv1i32 +/* 37763 */ MCD_OPC_FilterValue, 48, 58, 11, // Skip to: 40641 +/* 37767 */ MCD_OPC_CheckPredicate, 0, 54, 11, // Skip to: 40641 +/* 37771 */ MCD_OPC_Decode, 203, 2, 144, 1, // Opcode: FADDPv2i32p +/* 37776 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 37795 +/* 37780 */ MCD_OPC_CheckPredicate, 0, 41, 11, // Skip to: 40641 +/* 37784 */ MCD_OPC_CheckField, 21, 1, 1, 35, 11, // Skip to: 40641 +/* 37790 */ MCD_OPC_Decode, 224, 2, 130, 2, // Opcode: FCMGE32 +/* 37795 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 37814 +/* 37799 */ MCD_OPC_CheckPredicate, 0, 22, 11, // Skip to: 40641 +/* 37803 */ MCD_OPC_CheckField, 21, 1, 1, 16, 11, // Skip to: 40641 +/* 37809 */ MCD_OPC_Decode, 190, 2, 130, 2, // Opcode: FACGE32 +/* 37814 */ MCD_OPC_FilterValue, 62, 7, 11, // Skip to: 40641 +/* 37818 */ MCD_OPC_CheckPredicate, 0, 3, 11, // Skip to: 40641 +/* 37822 */ MCD_OPC_CheckField, 16, 6, 48, 253, 10, // Skip to: 40641 +/* 37828 */ MCD_OPC_Decode, 176, 4, 144, 1, // Opcode: FMAXPv2i32p +/* 37833 */ MCD_OPC_FilterValue, 9, 89, 1, // Skip to: 38182 +/* 37837 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 37840 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37859 +/* 37844 */ MCD_OPC_CheckPredicate, 0, 233, 10, // Skip to: 40641 +/* 37848 */ MCD_OPC_CheckField, 21, 1, 1, 227, 10, // Skip to: 40641 +/* 37854 */ MCD_OPC_Decode, 140, 17, 155, 2, // Opcode: UQADDv1i16 +/* 37859 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37878 +/* 37863 */ MCD_OPC_CheckPredicate, 0, 214, 10, // Skip to: 40641 +/* 37867 */ MCD_OPC_CheckField, 16, 6, 33, 208, 10, // Skip to: 40641 +/* 37873 */ MCD_OPC_Decode, 215, 12, 255, 1, // Opcode: SQXTUNv1i16 +/* 37878 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37897 +/* 37882 */ MCD_OPC_CheckPredicate, 0, 195, 10, // Skip to: 40641 +/* 37886 */ MCD_OPC_CheckField, 21, 1, 1, 189, 10, // Skip to: 40641 +/* 37892 */ MCD_OPC_Decode, 202, 17, 155, 2, // Opcode: UQSUBv1i16 +/* 37897 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37916 +/* 37901 */ MCD_OPC_CheckPredicate, 0, 176, 10, // Skip to: 40641 +/* 37905 */ MCD_OPC_CheckField, 16, 6, 32, 170, 10, // Skip to: 40641 +/* 37911 */ MCD_OPC_Decode, 150, 18, 157, 2, // Opcode: USQADDv1i16 +/* 37916 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37935 +/* 37920 */ MCD_OPC_CheckPredicate, 0, 157, 10, // Skip to: 40641 +/* 37924 */ MCD_OPC_CheckField, 16, 6, 33, 151, 10, // Skip to: 40641 +/* 37930 */ MCD_OPC_Decode, 213, 17, 255, 1, // Opcode: UQXTNv1i16 +/* 37935 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37954 +/* 37939 */ MCD_OPC_CheckPredicate, 0, 138, 10, // Skip to: 40641 +/* 37943 */ MCD_OPC_CheckField, 21, 1, 1, 132, 10, // Skip to: 40641 +/* 37949 */ MCD_OPC_Decode, 176, 17, 155, 2, // Opcode: UQSHLv1i16 +/* 37954 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 37973 +/* 37958 */ MCD_OPC_CheckPredicate, 0, 119, 10, // Skip to: 40641 +/* 37962 */ MCD_OPC_CheckField, 21, 1, 1, 113, 10, // Skip to: 40641 +/* 37968 */ MCD_OPC_Decode, 151, 17, 155, 2, // Opcode: UQRSHLv1i16 +/* 37973 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 37992 +/* 37977 */ MCD_OPC_CheckPredicate, 0, 100, 10, // Skip to: 40641 +/* 37981 */ MCD_OPC_CheckField, 16, 6, 33, 94, 10, // Skip to: 40641 +/* 37987 */ MCD_OPC_Decode, 222, 3, 144, 1, // Opcode: FCVTXNv1i64 +/* 37992 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38011 +/* 37996 */ MCD_OPC_CheckPredicate, 0, 81, 10, // Skip to: 40641 +/* 38000 */ MCD_OPC_CheckField, 16, 6, 32, 75, 10, // Skip to: 40641 +/* 38006 */ MCD_OPC_Decode, 220, 11, 161, 2, // Opcode: SQNEGv1i16 +/* 38011 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38029 +/* 38015 */ MCD_OPC_CheckPredicate, 0, 62, 10, // Skip to: 40641 +/* 38019 */ MCD_OPC_CheckField, 16, 6, 33, 56, 10, // Skip to: 40641 +/* 38025 */ MCD_OPC_Decode, 194, 3, 90, // Opcode: FCVTNUv1i64 +/* 38029 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38048 +/* 38033 */ MCD_OPC_CheckPredicate, 0, 44, 10, // Skip to: 40641 +/* 38037 */ MCD_OPC_CheckField, 21, 1, 1, 38, 10, // Skip to: 40641 +/* 38043 */ MCD_OPC_Decode, 230, 11, 155, 2, // Opcode: SQRDMULHv1i16 +/* 38048 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 38066 +/* 38052 */ MCD_OPC_CheckPredicate, 0, 25, 10, // Skip to: 40641 +/* 38056 */ MCD_OPC_CheckField, 16, 6, 33, 19, 10, // Skip to: 40641 +/* 38062 */ MCD_OPC_Decode, 176, 3, 90, // Opcode: FCVTMUv1i64 +/* 38066 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38097 +/* 38070 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38073 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38085 +/* 38077 */ MCD_OPC_CheckPredicate, 0, 0, 10, // Skip to: 40641 +/* 38081 */ MCD_OPC_Decode, 150, 3, 90, // Opcode: FCVTAUv1i64 +/* 38085 */ MCD_OPC_FilterValue, 48, 248, 9, // Skip to: 40641 +/* 38089 */ MCD_OPC_CheckPredicate, 0, 244, 9, // Skip to: 40641 +/* 38093 */ MCD_OPC_Decode, 167, 4, 95, // Opcode: FMAXNMPv2i64p +/* 38097 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38128 +/* 38101 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38104 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38116 +/* 38108 */ MCD_OPC_CheckPredicate, 0, 225, 9, // Skip to: 40641 +/* 38112 */ MCD_OPC_Decode, 173, 16, 90, // Opcode: UCVTFv1i64 +/* 38116 */ MCD_OPC_FilterValue, 48, 217, 9, // Skip to: 40641 +/* 38120 */ MCD_OPC_CheckPredicate, 0, 213, 9, // Skip to: 40641 +/* 38124 */ MCD_OPC_Decode, 204, 2, 95, // Opcode: FADDPv2i64p +/* 38128 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38146 +/* 38132 */ MCD_OPC_CheckPredicate, 0, 201, 9, // Skip to: 40641 +/* 38136 */ MCD_OPC_CheckField, 21, 1, 1, 195, 9, // Skip to: 40641 +/* 38142 */ MCD_OPC_Decode, 225, 2, 89, // Opcode: FCMGE64 +/* 38146 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38164 +/* 38150 */ MCD_OPC_CheckPredicate, 0, 183, 9, // Skip to: 40641 +/* 38154 */ MCD_OPC_CheckField, 21, 1, 1, 177, 9, // Skip to: 40641 +/* 38160 */ MCD_OPC_Decode, 191, 2, 89, // Opcode: FACGE64 +/* 38164 */ MCD_OPC_FilterValue, 62, 169, 9, // Skip to: 40641 +/* 38168 */ MCD_OPC_CheckPredicate, 0, 165, 9, // Skip to: 40641 +/* 38172 */ MCD_OPC_CheckField, 16, 6, 48, 159, 9, // Skip to: 40641 +/* 38178 */ MCD_OPC_Decode, 177, 4, 95, // Opcode: FMAXPv2i64p +/* 38182 */ MCD_OPC_FilterValue, 10, 98, 1, // Skip to: 38540 +/* 38186 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 38189 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 38208 +/* 38193 */ MCD_OPC_CheckPredicate, 0, 140, 9, // Skip to: 40641 +/* 38197 */ MCD_OPC_CheckField, 21, 1, 1, 134, 9, // Skip to: 40641 +/* 38203 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: UQADDv1i32 +/* 38208 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 38227 +/* 38212 */ MCD_OPC_CheckPredicate, 0, 121, 9, // Skip to: 40641 +/* 38216 */ MCD_OPC_CheckField, 16, 6, 33, 115, 9, // Skip to: 40641 +/* 38222 */ MCD_OPC_Decode, 216, 12, 144, 1, // Opcode: SQXTUNv1i32 +/* 38227 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 38246 +/* 38231 */ MCD_OPC_CheckPredicate, 0, 102, 9, // Skip to: 40641 +/* 38235 */ MCD_OPC_CheckField, 21, 1, 1, 96, 9, // Skip to: 40641 +/* 38241 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: UQSUBv1i32 +/* 38246 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 38265 +/* 38250 */ MCD_OPC_CheckPredicate, 0, 83, 9, // Skip to: 40641 +/* 38254 */ MCD_OPC_CheckField, 16, 6, 32, 77, 9, // Skip to: 40641 +/* 38260 */ MCD_OPC_Decode, 151, 18, 158, 2, // Opcode: USQADDv1i32 +/* 38265 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 38284 +/* 38269 */ MCD_OPC_CheckPredicate, 0, 64, 9, // Skip to: 40641 +/* 38273 */ MCD_OPC_CheckField, 16, 6, 33, 58, 9, // Skip to: 40641 +/* 38279 */ MCD_OPC_Decode, 214, 17, 144, 1, // Opcode: UQXTNv1i32 +/* 38284 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 38303 +/* 38288 */ MCD_OPC_CheckPredicate, 0, 45, 9, // Skip to: 40641 +/* 38292 */ MCD_OPC_CheckField, 21, 1, 1, 39, 9, // Skip to: 40641 +/* 38298 */ MCD_OPC_Decode, 177, 17, 130, 2, // Opcode: UQSHLv1i32 +/* 38303 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 38322 +/* 38307 */ MCD_OPC_CheckPredicate, 0, 26, 9, // Skip to: 40641 +/* 38311 */ MCD_OPC_CheckField, 21, 1, 1, 20, 9, // Skip to: 40641 +/* 38317 */ MCD_OPC_Decode, 152, 17, 130, 2, // Opcode: UQRSHLv1i32 +/* 38322 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38341 +/* 38326 */ MCD_OPC_CheckPredicate, 0, 7, 9, // Skip to: 40641 +/* 38330 */ MCD_OPC_CheckField, 16, 6, 32, 1, 9, // Skip to: 40641 +/* 38336 */ MCD_OPC_Decode, 221, 11, 253, 1, // Opcode: SQNEGv1i32 +/* 38341 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 38360 +/* 38345 */ MCD_OPC_CheckPredicate, 0, 244, 8, // Skip to: 40641 +/* 38349 */ MCD_OPC_CheckField, 16, 6, 33, 238, 8, // Skip to: 40641 +/* 38355 */ MCD_OPC_Decode, 215, 3, 253, 1, // Opcode: FCVTPUv1i32 +/* 38360 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38379 +/* 38364 */ MCD_OPC_CheckPredicate, 0, 225, 8, // Skip to: 40641 +/* 38368 */ MCD_OPC_CheckField, 21, 1, 1, 219, 8, // Skip to: 40641 +/* 38374 */ MCD_OPC_Decode, 232, 11, 130, 2, // Opcode: SQRDMULHv1i32 +/* 38379 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 38398 +/* 38383 */ MCD_OPC_CheckPredicate, 0, 206, 8, // Skip to: 40641 +/* 38387 */ MCD_OPC_CheckField, 16, 6, 33, 200, 8, // Skip to: 40641 +/* 38393 */ MCD_OPC_Decode, 147, 4, 253, 1, // Opcode: FCVTZUv1i32 +/* 38398 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 38431 +/* 38402 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38405 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38418 +/* 38409 */ MCD_OPC_CheckPredicate, 0, 180, 8, // Skip to: 40641 +/* 38413 */ MCD_OPC_Decode, 226, 2, 253, 1, // Opcode: FCMGEv1i32rz +/* 38418 */ MCD_OPC_FilterValue, 48, 171, 8, // Skip to: 40641 +/* 38422 */ MCD_OPC_CheckPredicate, 0, 167, 8, // Skip to: 40641 +/* 38426 */ MCD_OPC_Decode, 188, 4, 144, 1, // Opcode: FMINNMPv2i32p +/* 38431 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 38450 +/* 38435 */ MCD_OPC_CheckPredicate, 0, 154, 8, // Skip to: 40641 +/* 38439 */ MCD_OPC_CheckField, 21, 1, 1, 148, 8, // Skip to: 40641 +/* 38445 */ MCD_OPC_Decode, 180, 2, 130, 2, // Opcode: FABD32 +/* 38450 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 38483 +/* 38454 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38457 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38470 +/* 38461 */ MCD_OPC_CheckPredicate, 0, 128, 8, // Skip to: 40641 +/* 38465 */ MCD_OPC_Decode, 244, 2, 253, 1, // Opcode: FCMLEv1i32rz +/* 38470 */ MCD_OPC_FilterValue, 33, 119, 8, // Skip to: 40641 +/* 38474 */ MCD_OPC_CheckPredicate, 0, 115, 8, // Skip to: 40641 +/* 38478 */ MCD_OPC_Decode, 187, 5, 253, 1, // Opcode: FRSQRTEv1i32 +/* 38483 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 38502 +/* 38487 */ MCD_OPC_CheckPredicate, 0, 102, 8, // Skip to: 40641 +/* 38491 */ MCD_OPC_CheckField, 21, 1, 1, 96, 8, // Skip to: 40641 +/* 38497 */ MCD_OPC_Decode, 234, 2, 130, 2, // Opcode: FCMGT32 +/* 38502 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 38521 +/* 38506 */ MCD_OPC_CheckPredicate, 0, 83, 8, // Skip to: 40641 +/* 38510 */ MCD_OPC_CheckField, 21, 1, 1, 77, 8, // Skip to: 40641 +/* 38516 */ MCD_OPC_Decode, 195, 2, 130, 2, // Opcode: FACGT32 +/* 38521 */ MCD_OPC_FilterValue, 62, 68, 8, // Skip to: 40641 +/* 38525 */ MCD_OPC_CheckPredicate, 0, 64, 8, // Skip to: 40641 +/* 38529 */ MCD_OPC_CheckField, 16, 6, 48, 58, 8, // Skip to: 40641 +/* 38535 */ MCD_OPC_Decode, 198, 4, 144, 1, // Opcode: FMINPv2i32p +/* 38540 */ MCD_OPC_FilterValue, 11, 182, 1, // Skip to: 38982 +/* 38544 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 38547 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 38565 +/* 38551 */ MCD_OPC_CheckPredicate, 0, 38, 8, // Skip to: 40641 +/* 38555 */ MCD_OPC_CheckField, 21, 1, 1, 32, 8, // Skip to: 40641 +/* 38561 */ MCD_OPC_Decode, 142, 17, 89, // Opcode: UQADDv1i64 +/* 38565 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 38583 +/* 38569 */ MCD_OPC_CheckPredicate, 0, 20, 8, // Skip to: 40641 +/* 38573 */ MCD_OPC_CheckField, 21, 1, 1, 14, 8, // Skip to: 40641 +/* 38579 */ MCD_OPC_Decode, 204, 17, 89, // Opcode: UQSUBv1i64 +/* 38583 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 38601 +/* 38587 */ MCD_OPC_CheckPredicate, 0, 2, 8, // Skip to: 40641 +/* 38591 */ MCD_OPC_CheckField, 21, 1, 1, 252, 7, // Skip to: 40641 +/* 38597 */ MCD_OPC_Decode, 209, 1, 89, // Opcode: CMHIv1i64 +/* 38601 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 38619 +/* 38605 */ MCD_OPC_CheckPredicate, 0, 240, 7, // Skip to: 40641 +/* 38609 */ MCD_OPC_CheckField, 16, 6, 32, 234, 7, // Skip to: 40641 +/* 38615 */ MCD_OPC_Decode, 152, 18, 99, // Opcode: USQADDv1i64 +/* 38619 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 38637 +/* 38623 */ MCD_OPC_CheckPredicate, 0, 222, 7, // Skip to: 40641 +/* 38627 */ MCD_OPC_CheckField, 21, 1, 1, 216, 7, // Skip to: 40641 +/* 38633 */ MCD_OPC_Decode, 217, 1, 89, // Opcode: CMHSv1i64 +/* 38637 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 38655 +/* 38641 */ MCD_OPC_CheckPredicate, 0, 204, 7, // Skip to: 40641 +/* 38645 */ MCD_OPC_CheckField, 21, 1, 1, 198, 7, // Skip to: 40641 +/* 38651 */ MCD_OPC_Decode, 134, 18, 89, // Opcode: USHLv1i64 +/* 38655 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 38673 +/* 38659 */ MCD_OPC_CheckPredicate, 0, 186, 7, // Skip to: 40641 +/* 38663 */ MCD_OPC_CheckField, 21, 1, 1, 180, 7, // Skip to: 40641 +/* 38669 */ MCD_OPC_Decode, 178, 17, 89, // Opcode: UQSHLv1i64 +/* 38673 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 38691 +/* 38677 */ MCD_OPC_CheckPredicate, 0, 168, 7, // Skip to: 40641 +/* 38681 */ MCD_OPC_CheckField, 21, 1, 1, 162, 7, // Skip to: 40641 +/* 38687 */ MCD_OPC_Decode, 230, 17, 89, // Opcode: URSHLv1i64 +/* 38691 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 38709 +/* 38695 */ MCD_OPC_CheckPredicate, 0, 150, 7, // Skip to: 40641 +/* 38699 */ MCD_OPC_CheckField, 21, 1, 1, 144, 7, // Skip to: 40641 +/* 38705 */ MCD_OPC_Decode, 153, 17, 89, // Opcode: UQRSHLv1i64 +/* 38709 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 38727 +/* 38713 */ MCD_OPC_CheckPredicate, 0, 132, 7, // Skip to: 40641 +/* 38717 */ MCD_OPC_CheckField, 16, 6, 32, 126, 7, // Skip to: 40641 +/* 38723 */ MCD_OPC_Decode, 222, 11, 90, // Opcode: SQNEGv1i64 +/* 38727 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 38745 +/* 38731 */ MCD_OPC_CheckPredicate, 0, 114, 7, // Skip to: 40641 +/* 38735 */ MCD_OPC_CheckField, 21, 1, 1, 108, 7, // Skip to: 40641 +/* 38741 */ MCD_OPC_Decode, 176, 15, 89, // Opcode: SUBv1i64 +/* 38745 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 38763 +/* 38749 */ MCD_OPC_CheckPredicate, 0, 96, 7, // Skip to: 40641 +/* 38753 */ MCD_OPC_CheckField, 16, 6, 32, 90, 7, // Skip to: 40641 +/* 38759 */ MCD_OPC_Decode, 179, 1, 90, // Opcode: CMGEv1i64rz +/* 38763 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 38781 +/* 38767 */ MCD_OPC_CheckPredicate, 0, 78, 7, // Skip to: 40641 +/* 38771 */ MCD_OPC_CheckField, 21, 1, 1, 72, 7, // Skip to: 40641 +/* 38777 */ MCD_OPC_Decode, 162, 1, 89, // Opcode: CMEQv1i64 +/* 38781 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 38799 +/* 38785 */ MCD_OPC_CheckPredicate, 0, 60, 7, // Skip to: 40641 +/* 38789 */ MCD_OPC_CheckField, 16, 6, 32, 54, 7, // Skip to: 40641 +/* 38795 */ MCD_OPC_Decode, 225, 1, 90, // Opcode: CMLEv1i64rz +/* 38799 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38817 +/* 38803 */ MCD_OPC_CheckPredicate, 0, 42, 7, // Skip to: 40641 +/* 38807 */ MCD_OPC_CheckField, 16, 6, 33, 36, 7, // Skip to: 40641 +/* 38813 */ MCD_OPC_Decode, 216, 3, 90, // Opcode: FCVTPUv1i64 +/* 38817 */ MCD_OPC_FilterValue, 46, 27, 0, // Skip to: 38848 +/* 38821 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38824 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38836 +/* 38828 */ MCD_OPC_CheckPredicate, 0, 17, 7, // Skip to: 40641 +/* 38832 */ MCD_OPC_Decode, 248, 8, 90, // Opcode: NEGv1i64 +/* 38836 */ MCD_OPC_FilterValue, 33, 9, 7, // Skip to: 40641 +/* 38840 */ MCD_OPC_CheckPredicate, 0, 5, 7, // Skip to: 40641 +/* 38844 */ MCD_OPC_Decode, 148, 4, 90, // Opcode: FCVTZUv1i64 +/* 38848 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38879 +/* 38852 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38855 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38867 +/* 38859 */ MCD_OPC_CheckPredicate, 0, 242, 6, // Skip to: 40641 +/* 38863 */ MCD_OPC_Decode, 227, 2, 90, // Opcode: FCMGEv1i64rz +/* 38867 */ MCD_OPC_FilterValue, 48, 234, 6, // Skip to: 40641 +/* 38871 */ MCD_OPC_CheckPredicate, 0, 230, 6, // Skip to: 40641 +/* 38875 */ MCD_OPC_Decode, 189, 4, 95, // Opcode: FMINNMPv2i64p +/* 38879 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 38897 +/* 38883 */ MCD_OPC_CheckPredicate, 0, 218, 6, // Skip to: 40641 +/* 38887 */ MCD_OPC_CheckField, 21, 1, 1, 212, 6, // Skip to: 40641 +/* 38893 */ MCD_OPC_Decode, 181, 2, 89, // Opcode: FABD64 +/* 38897 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38928 +/* 38901 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 38904 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38916 +/* 38908 */ MCD_OPC_CheckPredicate, 0, 193, 6, // Skip to: 40641 +/* 38912 */ MCD_OPC_Decode, 245, 2, 90, // Opcode: FCMLEv1i64rz +/* 38916 */ MCD_OPC_FilterValue, 33, 185, 6, // Skip to: 40641 +/* 38920 */ MCD_OPC_CheckPredicate, 0, 181, 6, // Skip to: 40641 +/* 38924 */ MCD_OPC_Decode, 188, 5, 90, // Opcode: FRSQRTEv1i64 +/* 38928 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38946 +/* 38932 */ MCD_OPC_CheckPredicate, 0, 169, 6, // Skip to: 40641 +/* 38936 */ MCD_OPC_CheckField, 21, 1, 1, 163, 6, // Skip to: 40641 +/* 38942 */ MCD_OPC_Decode, 235, 2, 89, // Opcode: FCMGT64 +/* 38946 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38964 +/* 38950 */ MCD_OPC_CheckPredicate, 0, 151, 6, // Skip to: 40641 +/* 38954 */ MCD_OPC_CheckField, 21, 1, 1, 145, 6, // Skip to: 40641 +/* 38960 */ MCD_OPC_Decode, 196, 2, 89, // Opcode: FACGT64 +/* 38964 */ MCD_OPC_FilterValue, 62, 137, 6, // Skip to: 40641 +/* 38968 */ MCD_OPC_CheckPredicate, 0, 133, 6, // Skip to: 40641 +/* 38972 */ MCD_OPC_CheckField, 16, 6, 48, 127, 6, // Skip to: 40641 +/* 38978 */ MCD_OPC_Decode, 199, 4, 95, // Opcode: FMINPv2i64p +/* 38982 */ MCD_OPC_FilterValue, 12, 139, 1, // Skip to: 39381 +/* 38986 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 38989 */ MCD_OPC_FilterValue, 25, 55, 0, // Skip to: 39048 +/* 38993 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38996 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39035 +/* 39000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39003 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39022 +/* 39007 */ MCD_OPC_CheckPredicate, 0, 94, 6, // Skip to: 40641 +/* 39011 */ MCD_OPC_CheckField, 19, 1, 1, 88, 6, // Skip to: 40641 +/* 39017 */ MCD_OPC_Decode, 143, 12, 173, 2, // Opcode: SQSHLUb +/* 39022 */ MCD_OPC_FilterValue, 1, 79, 6, // Skip to: 40641 +/* 39026 */ MCD_OPC_CheckPredicate, 0, 75, 6, // Skip to: 40641 +/* 39030 */ MCD_OPC_Decode, 145, 12, 174, 2, // Opcode: SQSHLUh +/* 39035 */ MCD_OPC_FilterValue, 1, 66, 6, // Skip to: 40641 +/* 39039 */ MCD_OPC_CheckPredicate, 0, 62, 6, // Skip to: 40641 +/* 39043 */ MCD_OPC_Decode, 146, 12, 175, 2, // Opcode: SQSHLUs +/* 39048 */ MCD_OPC_FilterValue, 29, 55, 0, // Skip to: 39107 +/* 39052 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39055 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39094 +/* 39059 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39062 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39081 +/* 39066 */ MCD_OPC_CheckPredicate, 0, 35, 6, // Skip to: 40641 +/* 39070 */ MCD_OPC_CheckField, 19, 1, 1, 29, 6, // Skip to: 40641 +/* 39076 */ MCD_OPC_Decode, 170, 17, 173, 2, // Opcode: UQSHLb +/* 39081 */ MCD_OPC_FilterValue, 1, 20, 6, // Skip to: 40641 +/* 39085 */ MCD_OPC_CheckPredicate, 0, 16, 6, // Skip to: 40641 +/* 39089 */ MCD_OPC_Decode, 172, 17, 174, 2, // Opcode: UQSHLh +/* 39094 */ MCD_OPC_FilterValue, 1, 7, 6, // Skip to: 40641 +/* 39098 */ MCD_OPC_CheckPredicate, 0, 3, 6, // Skip to: 40641 +/* 39102 */ MCD_OPC_Decode, 173, 17, 175, 2, // Opcode: UQSHLs +/* 39107 */ MCD_OPC_FilterValue, 33, 55, 0, // Skip to: 39166 +/* 39111 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39114 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39153 +/* 39118 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39121 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39140 +/* 39125 */ MCD_OPC_CheckPredicate, 0, 232, 5, // Skip to: 40641 +/* 39129 */ MCD_OPC_CheckField, 19, 1, 1, 226, 5, // Skip to: 40641 +/* 39135 */ MCD_OPC_Decode, 185, 12, 176, 2, // Opcode: SQSHRUNb +/* 39140 */ MCD_OPC_FilterValue, 1, 217, 5, // Skip to: 40641 +/* 39144 */ MCD_OPC_CheckPredicate, 0, 213, 5, // Skip to: 40641 +/* 39148 */ MCD_OPC_Decode, 186, 12, 177, 2, // Opcode: SQSHRUNh +/* 39153 */ MCD_OPC_FilterValue, 1, 204, 5, // Skip to: 40641 +/* 39157 */ MCD_OPC_CheckPredicate, 0, 200, 5, // Skip to: 40641 +/* 39161 */ MCD_OPC_Decode, 187, 12, 178, 2, // Opcode: SQSHRUNs +/* 39166 */ MCD_OPC_FilterValue, 35, 55, 0, // Skip to: 39225 +/* 39170 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39173 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39212 +/* 39177 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39180 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39199 +/* 39184 */ MCD_OPC_CheckPredicate, 0, 173, 5, // Skip to: 40641 +/* 39188 */ MCD_OPC_CheckField, 19, 1, 1, 167, 5, // Skip to: 40641 +/* 39194 */ MCD_OPC_Decode, 134, 12, 176, 2, // Opcode: SQRSHRUNb +/* 39199 */ MCD_OPC_FilterValue, 1, 158, 5, // Skip to: 40641 +/* 39203 */ MCD_OPC_CheckPredicate, 0, 154, 5, // Skip to: 40641 +/* 39207 */ MCD_OPC_Decode, 135, 12, 177, 2, // Opcode: SQRSHRUNh +/* 39212 */ MCD_OPC_FilterValue, 1, 145, 5, // Skip to: 40641 +/* 39216 */ MCD_OPC_CheckPredicate, 0, 141, 5, // Skip to: 40641 +/* 39220 */ MCD_OPC_Decode, 136, 12, 178, 2, // Opcode: SQRSHRUNs +/* 39225 */ MCD_OPC_FilterValue, 37, 55, 0, // Skip to: 39284 +/* 39229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39232 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39271 +/* 39236 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39239 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39258 +/* 39243 */ MCD_OPC_CheckPredicate, 0, 114, 5, // Skip to: 40641 +/* 39247 */ MCD_OPC_CheckField, 19, 1, 1, 108, 5, // Skip to: 40641 +/* 39253 */ MCD_OPC_Decode, 192, 17, 176, 2, // Opcode: UQSHRNb +/* 39258 */ MCD_OPC_FilterValue, 1, 99, 5, // Skip to: 40641 +/* 39262 */ MCD_OPC_CheckPredicate, 0, 95, 5, // Skip to: 40641 +/* 39266 */ MCD_OPC_Decode, 193, 17, 177, 2, // Opcode: UQSHRNh +/* 39271 */ MCD_OPC_FilterValue, 1, 86, 5, // Skip to: 40641 +/* 39275 */ MCD_OPC_CheckPredicate, 0, 82, 5, // Skip to: 40641 +/* 39279 */ MCD_OPC_Decode, 194, 17, 178, 2, // Opcode: UQSHRNs +/* 39284 */ MCD_OPC_FilterValue, 39, 55, 0, // Skip to: 39343 +/* 39288 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39291 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39330 +/* 39295 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 39298 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39317 +/* 39302 */ MCD_OPC_CheckPredicate, 0, 55, 5, // Skip to: 40641 +/* 39306 */ MCD_OPC_CheckField, 19, 1, 1, 49, 5, // Skip to: 40641 +/* 39312 */ MCD_OPC_Decode, 161, 17, 176, 2, // Opcode: UQRSHRNb +/* 39317 */ MCD_OPC_FilterValue, 1, 40, 5, // Skip to: 40641 +/* 39321 */ MCD_OPC_CheckPredicate, 0, 36, 5, // Skip to: 40641 +/* 39325 */ MCD_OPC_Decode, 162, 17, 177, 2, // Opcode: UQRSHRNh +/* 39330 */ MCD_OPC_FilterValue, 1, 27, 5, // Skip to: 40641 +/* 39334 */ MCD_OPC_CheckPredicate, 0, 23, 5, // Skip to: 40641 +/* 39338 */ MCD_OPC_Decode, 163, 17, 178, 2, // Opcode: UQRSHRNs +/* 39343 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39362 +/* 39347 */ MCD_OPC_CheckPredicate, 0, 10, 5, // Skip to: 40641 +/* 39351 */ MCD_OPC_CheckField, 21, 1, 1, 4, 5, // Skip to: 40641 +/* 39357 */ MCD_OPC_Decode, 171, 16, 184, 2, // Opcode: UCVTFs +/* 39362 */ MCD_OPC_FilterValue, 63, 251, 4, // Skip to: 40641 +/* 39366 */ MCD_OPC_CheckPredicate, 0, 247, 4, // Skip to: 40641 +/* 39370 */ MCD_OPC_CheckField, 21, 1, 1, 241, 4, // Skip to: 40641 +/* 39376 */ MCD_OPC_Decode, 146, 4, 184, 2, // Opcode: FCVTZUs +/* 39381 */ MCD_OPC_FilterValue, 13, 133, 0, // Skip to: 39518 +/* 39385 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 39388 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 39401 +/* 39392 */ MCD_OPC_CheckPredicate, 0, 221, 4, // Skip to: 40641 +/* 39396 */ MCD_OPC_Decode, 141, 18, 166, 2, // Opcode: USHRd +/* 39401 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 39414 +/* 39405 */ MCD_OPC_CheckPredicate, 0, 208, 4, // Skip to: 40641 +/* 39409 */ MCD_OPC_Decode, 160, 18, 167, 2, // Opcode: USRAd +/* 39414 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 39427 +/* 39418 */ MCD_OPC_CheckPredicate, 0, 195, 4, // Skip to: 40641 +/* 39422 */ MCD_OPC_Decode, 237, 17, 166, 2, // Opcode: URSHRd +/* 39427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 39440 +/* 39431 */ MCD_OPC_CheckPredicate, 0, 182, 4, // Skip to: 40641 +/* 39435 */ MCD_OPC_Decode, 247, 17, 167, 2, // Opcode: URSRAd +/* 39440 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 39453 +/* 39444 */ MCD_OPC_CheckPredicate, 0, 169, 4, // Skip to: 40641 +/* 39448 */ MCD_OPC_Decode, 229, 12, 167, 2, // Opcode: SRId +/* 39453 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 39466 +/* 39457 */ MCD_OPC_CheckPredicate, 0, 156, 4, // Skip to: 40641 +/* 39461 */ MCD_OPC_Decode, 196, 10, 187, 2, // Opcode: SLId +/* 39466 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39479 +/* 39470 */ MCD_OPC_CheckPredicate, 0, 143, 4, // Skip to: 40641 +/* 39474 */ MCD_OPC_Decode, 144, 12, 172, 2, // Opcode: SQSHLUd +/* 39479 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 39492 +/* 39483 */ MCD_OPC_CheckPredicate, 0, 130, 4, // Skip to: 40641 +/* 39487 */ MCD_OPC_Decode, 171, 17, 172, 2, // Opcode: UQSHLd +/* 39492 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 39505 +/* 39496 */ MCD_OPC_CheckPredicate, 0, 117, 4, // Skip to: 40641 +/* 39500 */ MCD_OPC_Decode, 170, 16, 166, 2, // Opcode: UCVTFd +/* 39505 */ MCD_OPC_FilterValue, 63, 108, 4, // Skip to: 40641 +/* 39509 */ MCD_OPC_CheckPredicate, 0, 104, 4, // Skip to: 40641 +/* 39513 */ MCD_OPC_Decode, 145, 4, 166, 2, // Opcode: FCVTZUd +/* 39518 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 39543 +/* 39522 */ MCD_OPC_CheckPredicate, 0, 91, 4, // Skip to: 40641 +/* 39526 */ MCD_OPC_CheckField, 12, 4, 9, 85, 4, // Skip to: 40641 +/* 39532 */ MCD_OPC_CheckField, 10, 1, 0, 79, 4, // Skip to: 40641 +/* 39538 */ MCD_OPC_Decode, 241, 4, 179, 2, // Opcode: FMULXv1i32_indexed +/* 39543 */ MCD_OPC_FilterValue, 15, 70, 4, // Skip to: 40641 +/* 39547 */ MCD_OPC_CheckPredicate, 0, 66, 4, // Skip to: 40641 +/* 39551 */ MCD_OPC_CheckField, 21, 1, 0, 60, 4, // Skip to: 40641 +/* 39557 */ MCD_OPC_CheckField, 12, 4, 9, 54, 4, // Skip to: 40641 +/* 39563 */ MCD_OPC_CheckField, 10, 1, 0, 48, 4, // Skip to: 40641 +/* 39569 */ MCD_OPC_Decode, 242, 4, 180, 2, // Opcode: FMULXv1i64_indexed +/* 39574 */ MCD_OPC_FilterValue, 4, 145, 2, // Skip to: 40235 +/* 39578 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 39581 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 39590 +/* 39585 */ MCD_OPC_Decode, 224, 7, 188, 2, // Opcode: LDRQl +/* 39590 */ MCD_OPC_FilterValue, 2, 23, 4, // Skip to: 40641 +/* 39594 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 39597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 39610 +/* 39601 */ MCD_OPC_CheckPredicate, 3, 12, 4, // Skip to: 40641 +/* 39605 */ MCD_OPC_Decode, 135, 10, 189, 2, // Opcode: SCVTFSXSri +/* 39610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 39623 +/* 39614 */ MCD_OPC_CheckPredicate, 3, 255, 3, // Skip to: 40641 +/* 39618 */ MCD_OPC_Decode, 165, 16, 189, 2, // Opcode: UCVTFSXSri +/* 39623 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 39636 +/* 39627 */ MCD_OPC_CheckPredicate, 3, 242, 3, // Skip to: 40641 +/* 39631 */ MCD_OPC_Decode, 228, 3, 190, 2, // Opcode: FCVTZSSXSri +/* 39636 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39649 +/* 39640 */ MCD_OPC_CheckPredicate, 3, 229, 3, // Skip to: 40641 +/* 39644 */ MCD_OPC_Decode, 129, 4, 190, 2, // Opcode: FCVTZUSXSri +/* 39649 */ MCD_OPC_FilterValue, 32, 15, 0, // Skip to: 39668 +/* 39653 */ MCD_OPC_CheckPredicate, 3, 216, 3, // Skip to: 40641 +/* 39657 */ MCD_OPC_CheckField, 10, 6, 0, 210, 3, // Skip to: 40641 +/* 39663 */ MCD_OPC_Decode, 183, 3, 191, 2, // Opcode: FCVTNSUXSr +/* 39668 */ MCD_OPC_FilterValue, 33, 15, 0, // Skip to: 39687 +/* 39672 */ MCD_OPC_CheckPredicate, 3, 197, 3, // Skip to: 40641 +/* 39676 */ MCD_OPC_CheckField, 10, 6, 0, 191, 3, // Skip to: 40641 +/* 39682 */ MCD_OPC_Decode, 192, 3, 191, 2, // Opcode: FCVTNUUXSr +/* 39687 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 39706 +/* 39691 */ MCD_OPC_CheckPredicate, 3, 178, 3, // Skip to: 40641 +/* 39695 */ MCD_OPC_CheckField, 10, 6, 0, 172, 3, // Skip to: 40641 +/* 39701 */ MCD_OPC_Decode, 139, 10, 192, 2, // Opcode: SCVTFUXSri +/* 39706 */ MCD_OPC_FilterValue, 35, 15, 0, // Skip to: 39725 +/* 39710 */ MCD_OPC_CheckPredicate, 3, 159, 3, // Skip to: 40641 +/* 39714 */ MCD_OPC_CheckField, 10, 6, 0, 153, 3, // Skip to: 40641 +/* 39720 */ MCD_OPC_Decode, 169, 16, 192, 2, // Opcode: UCVTFUXSri +/* 39725 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 39744 +/* 39729 */ MCD_OPC_CheckPredicate, 3, 140, 3, // Skip to: 40641 +/* 39733 */ MCD_OPC_CheckField, 10, 6, 0, 134, 3, // Skip to: 40641 +/* 39739 */ MCD_OPC_Decode, 139, 3, 191, 2, // Opcode: FCVTASUXSr +/* 39744 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 39763 +/* 39748 */ MCD_OPC_CheckPredicate, 3, 121, 3, // Skip to: 40641 +/* 39752 */ MCD_OPC_CheckField, 10, 6, 0, 115, 3, // Skip to: 40641 +/* 39758 */ MCD_OPC_Decode, 148, 3, 191, 2, // Opcode: FCVTAUUXSr +/* 39763 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 39782 +/* 39767 */ MCD_OPC_CheckPredicate, 3, 102, 3, // Skip to: 40641 +/* 39771 */ MCD_OPC_CheckField, 10, 6, 0, 96, 3, // Skip to: 40641 +/* 39777 */ MCD_OPC_Decode, 205, 3, 191, 2, // Opcode: FCVTPSUXSr +/* 39782 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 39801 +/* 39786 */ MCD_OPC_CheckPredicate, 3, 83, 3, // Skip to: 40641 +/* 39790 */ MCD_OPC_CheckField, 10, 6, 0, 77, 3, // Skip to: 40641 +/* 39796 */ MCD_OPC_Decode, 214, 3, 191, 2, // Opcode: FCVTPUUXSr +/* 39801 */ MCD_OPC_FilterValue, 48, 15, 0, // Skip to: 39820 +/* 39805 */ MCD_OPC_CheckPredicate, 3, 64, 3, // Skip to: 40641 +/* 39809 */ MCD_OPC_CheckField, 10, 6, 0, 58, 3, // Skip to: 40641 +/* 39815 */ MCD_OPC_Decode, 165, 3, 191, 2, // Opcode: FCVTMSUXSr +/* 39820 */ MCD_OPC_FilterValue, 49, 15, 0, // Skip to: 39839 +/* 39824 */ MCD_OPC_CheckPredicate, 3, 45, 3, // Skip to: 40641 +/* 39828 */ MCD_OPC_CheckField, 10, 6, 0, 39, 3, // Skip to: 40641 +/* 39834 */ MCD_OPC_Decode, 174, 3, 191, 2, // Opcode: FCVTMUUXSr +/* 39839 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 39858 +/* 39843 */ MCD_OPC_CheckPredicate, 3, 26, 3, // Skip to: 40641 +/* 39847 */ MCD_OPC_CheckField, 10, 6, 0, 20, 3, // Skip to: 40641 +/* 39853 */ MCD_OPC_Decode, 232, 3, 191, 2, // Opcode: FCVTZSUXSr +/* 39858 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39877 +/* 39862 */ MCD_OPC_CheckPredicate, 3, 7, 3, // Skip to: 40641 +/* 39866 */ MCD_OPC_CheckField, 10, 6, 0, 1, 3, // Skip to: 40641 +/* 39872 */ MCD_OPC_Decode, 133, 4, 191, 2, // Opcode: FCVTZUUXSr +/* 39877 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 39890 +/* 39881 */ MCD_OPC_CheckPredicate, 3, 244, 2, // Skip to: 40641 +/* 39885 */ MCD_OPC_Decode, 134, 10, 193, 2, // Opcode: SCVTFSXDri +/* 39890 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 39903 +/* 39894 */ MCD_OPC_CheckPredicate, 3, 231, 2, // Skip to: 40641 +/* 39898 */ MCD_OPC_Decode, 164, 16, 193, 2, // Opcode: UCVTFSXDri +/* 39903 */ MCD_OPC_FilterValue, 88, 9, 0, // Skip to: 39916 +/* 39907 */ MCD_OPC_CheckPredicate, 3, 218, 2, // Skip to: 40641 +/* 39911 */ MCD_OPC_Decode, 227, 3, 194, 2, // Opcode: FCVTZSSXDri +/* 39916 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 39929 +/* 39920 */ MCD_OPC_CheckPredicate, 3, 205, 2, // Skip to: 40641 +/* 39924 */ MCD_OPC_Decode, 128, 4, 194, 2, // Opcode: FCVTZUSXDri +/* 39929 */ MCD_OPC_FilterValue, 96, 15, 0, // Skip to: 39948 +/* 39933 */ MCD_OPC_CheckPredicate, 3, 192, 2, // Skip to: 40641 +/* 39937 */ MCD_OPC_CheckField, 10, 6, 0, 186, 2, // Skip to: 40641 +/* 39943 */ MCD_OPC_Decode, 182, 3, 195, 2, // Opcode: FCVTNSUXDr +/* 39948 */ MCD_OPC_FilterValue, 97, 15, 0, // Skip to: 39967 +/* 39952 */ MCD_OPC_CheckPredicate, 3, 173, 2, // Skip to: 40641 +/* 39956 */ MCD_OPC_CheckField, 10, 6, 0, 167, 2, // Skip to: 40641 +/* 39962 */ MCD_OPC_Decode, 191, 3, 195, 2, // Opcode: FCVTNUUXDr +/* 39967 */ MCD_OPC_FilterValue, 98, 15, 0, // Skip to: 39986 +/* 39971 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 40641 +/* 39975 */ MCD_OPC_CheckField, 10, 6, 0, 148, 2, // Skip to: 40641 +/* 39981 */ MCD_OPC_Decode, 138, 10, 196, 2, // Opcode: SCVTFUXDri +/* 39986 */ MCD_OPC_FilterValue, 99, 15, 0, // Skip to: 40005 +/* 39990 */ MCD_OPC_CheckPredicate, 3, 135, 2, // Skip to: 40641 +/* 39994 */ MCD_OPC_CheckField, 10, 6, 0, 129, 2, // Skip to: 40641 +/* 40000 */ MCD_OPC_Decode, 168, 16, 196, 2, // Opcode: UCVTFUXDri +/* 40005 */ MCD_OPC_FilterValue, 100, 15, 0, // Skip to: 40024 +/* 40009 */ MCD_OPC_CheckPredicate, 3, 116, 2, // Skip to: 40641 +/* 40013 */ MCD_OPC_CheckField, 10, 6, 0, 110, 2, // Skip to: 40641 +/* 40019 */ MCD_OPC_Decode, 138, 3, 195, 2, // Opcode: FCVTASUXDr +/* 40024 */ MCD_OPC_FilterValue, 101, 15, 0, // Skip to: 40043 +/* 40028 */ MCD_OPC_CheckPredicate, 3, 97, 2, // Skip to: 40641 +/* 40032 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, // Skip to: 40641 +/* 40038 */ MCD_OPC_Decode, 147, 3, 195, 2, // Opcode: FCVTAUUXDr +/* 40043 */ MCD_OPC_FilterValue, 102, 15, 0, // Skip to: 40062 +/* 40047 */ MCD_OPC_CheckPredicate, 3, 78, 2, // Skip to: 40641 +/* 40051 */ MCD_OPC_CheckField, 10, 6, 0, 72, 2, // Skip to: 40641 +/* 40057 */ MCD_OPC_Decode, 223, 4, 195, 2, // Opcode: FMOVDXr +/* 40062 */ MCD_OPC_FilterValue, 103, 15, 0, // Skip to: 40081 +/* 40066 */ MCD_OPC_CheckPredicate, 3, 59, 2, // Skip to: 40641 +/* 40070 */ MCD_OPC_CheckField, 10, 6, 0, 53, 2, // Skip to: 40641 +/* 40076 */ MCD_OPC_Decode, 231, 4, 196, 2, // Opcode: FMOVXDr +/* 40081 */ MCD_OPC_FilterValue, 104, 15, 0, // Skip to: 40100 +/* 40085 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 40641 +/* 40089 */ MCD_OPC_CheckField, 10, 6, 0, 34, 2, // Skip to: 40641 +/* 40095 */ MCD_OPC_Decode, 204, 3, 195, 2, // Opcode: FCVTPSUXDr +/* 40100 */ MCD_OPC_FilterValue, 105, 15, 0, // Skip to: 40119 +/* 40104 */ MCD_OPC_CheckPredicate, 3, 21, 2, // Skip to: 40641 +/* 40108 */ MCD_OPC_CheckField, 10, 6, 0, 15, 2, // Skip to: 40641 +/* 40114 */ MCD_OPC_Decode, 213, 3, 195, 2, // Opcode: FCVTPUUXDr +/* 40119 */ MCD_OPC_FilterValue, 112, 15, 0, // Skip to: 40138 +/* 40123 */ MCD_OPC_CheckPredicate, 3, 2, 2, // Skip to: 40641 +/* 40127 */ MCD_OPC_CheckField, 10, 6, 0, 252, 1, // Skip to: 40641 +/* 40133 */ MCD_OPC_Decode, 164, 3, 195, 2, // Opcode: FCVTMSUXDr +/* 40138 */ MCD_OPC_FilterValue, 113, 15, 0, // Skip to: 40157 +/* 40142 */ MCD_OPC_CheckPredicate, 3, 239, 1, // Skip to: 40641 +/* 40146 */ MCD_OPC_CheckField, 10, 6, 0, 233, 1, // Skip to: 40641 +/* 40152 */ MCD_OPC_Decode, 173, 3, 195, 2, // Opcode: FCVTMUUXDr +/* 40157 */ MCD_OPC_FilterValue, 120, 15, 0, // Skip to: 40176 +/* 40161 */ MCD_OPC_CheckPredicate, 3, 220, 1, // Skip to: 40641 +/* 40165 */ MCD_OPC_CheckField, 10, 6, 0, 214, 1, // Skip to: 40641 +/* 40171 */ MCD_OPC_Decode, 231, 3, 195, 2, // Opcode: FCVTZSUXDr +/* 40176 */ MCD_OPC_FilterValue, 121, 15, 0, // Skip to: 40195 +/* 40180 */ MCD_OPC_CheckPredicate, 3, 201, 1, // Skip to: 40641 +/* 40184 */ MCD_OPC_CheckField, 10, 6, 0, 195, 1, // Skip to: 40641 +/* 40190 */ MCD_OPC_Decode, 132, 4, 195, 2, // Opcode: FCVTZUUXDr +/* 40195 */ MCD_OPC_FilterValue, 174, 1, 15, 0, // Skip to: 40215 +/* 40200 */ MCD_OPC_CheckPredicate, 3, 181, 1, // Skip to: 40641 +/* 40204 */ MCD_OPC_CheckField, 10, 6, 0, 175, 1, // Skip to: 40641 +/* 40210 */ MCD_OPC_Decode, 222, 4, 197, 2, // Opcode: FMOVDXHighr +/* 40215 */ MCD_OPC_FilterValue, 175, 1, 165, 1, // Skip to: 40641 +/* 40220 */ MCD_OPC_CheckPredicate, 3, 161, 1, // Skip to: 40641 +/* 40224 */ MCD_OPC_CheckField, 10, 6, 0, 155, 1, // Skip to: 40641 +/* 40230 */ MCD_OPC_Decode, 230, 4, 197, 2, // Opcode: FMOVXDHighr +/* 40235 */ MCD_OPC_FilterValue, 5, 199, 0, // Skip to: 40438 +/* 40239 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 40242 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40331 +/* 40246 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 40249 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40264 +/* 40253 */ MCD_OPC_CheckField, 21, 1, 0, 126, 1, // Skip to: 40641 +/* 40259 */ MCD_OPC_Decode, 142, 15, 226, 1, // Opcode: STURSi +/* 40264 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40279 +/* 40268 */ MCD_OPC_CheckField, 21, 1, 0, 111, 1, // Skip to: 40641 +/* 40274 */ MCD_OPC_Decode, 245, 14, 226, 1, // Opcode: STRSpost +/* 40279 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40316 +/* 40283 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 40286 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40301 +/* 40290 */ MCD_OPC_CheckField, 21, 1, 1, 89, 1, // Skip to: 40641 +/* 40296 */ MCD_OPC_Decode, 247, 14, 198, 2, // Opcode: STRSroW +/* 40301 */ MCD_OPC_FilterValue, 3, 80, 1, // Skip to: 40641 +/* 40305 */ MCD_OPC_CheckField, 21, 1, 1, 74, 1, // Skip to: 40641 +/* 40311 */ MCD_OPC_Decode, 248, 14, 199, 2, // Opcode: STRSroX +/* 40316 */ MCD_OPC_FilterValue, 3, 65, 1, // Skip to: 40641 +/* 40320 */ MCD_OPC_CheckField, 21, 1, 0, 59, 1, // Skip to: 40641 +/* 40326 */ MCD_OPC_Decode, 246, 14, 226, 1, // Opcode: STRSpre +/* 40331 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40420 +/* 40335 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 40338 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40353 +/* 40342 */ MCD_OPC_CheckField, 21, 1, 0, 37, 1, // Skip to: 40641 +/* 40348 */ MCD_OPC_Decode, 166, 8, 226, 1, // Opcode: LDURSi +/* 40353 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40368 +/* 40357 */ MCD_OPC_CheckField, 21, 1, 0, 22, 1, // Skip to: 40641 +/* 40363 */ MCD_OPC_Decode, 129, 8, 226, 1, // Opcode: LDRSpost +/* 40368 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40405 +/* 40372 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 40375 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40390 +/* 40379 */ MCD_OPC_CheckField, 21, 1, 1, 0, 1, // Skip to: 40641 +/* 40385 */ MCD_OPC_Decode, 131, 8, 198, 2, // Opcode: LDRSroW +/* 40390 */ MCD_OPC_FilterValue, 3, 247, 0, // Skip to: 40641 +/* 40394 */ MCD_OPC_CheckField, 21, 1, 1, 241, 0, // Skip to: 40641 +/* 40400 */ MCD_OPC_Decode, 132, 8, 199, 2, // Opcode: LDRSroX +/* 40405 */ MCD_OPC_FilterValue, 3, 232, 0, // Skip to: 40641 +/* 40409 */ MCD_OPC_CheckField, 21, 1, 0, 226, 0, // Skip to: 40641 +/* 40415 */ MCD_OPC_Decode, 130, 8, 226, 1, // Opcode: LDRSpre +/* 40420 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40429 +/* 40424 */ MCD_OPC_Decode, 249, 14, 231, 1, // Opcode: STRSui +/* 40429 */ MCD_OPC_FilterValue, 5, 208, 0, // Skip to: 40641 +/* 40433 */ MCD_OPC_Decode, 133, 8, 231, 1, // Opcode: LDRSui +/* 40438 */ MCD_OPC_FilterValue, 7, 199, 0, // Skip to: 40641 +/* 40442 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 40445 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40534 +/* 40449 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 40452 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40467 +/* 40456 */ MCD_OPC_CheckField, 21, 1, 0, 179, 0, // Skip to: 40641 +/* 40462 */ MCD_OPC_Decode, 138, 15, 226, 1, // Opcode: STURDi +/* 40467 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40482 +/* 40471 */ MCD_OPC_CheckField, 21, 1, 0, 164, 0, // Skip to: 40641 +/* 40477 */ MCD_OPC_Decode, 225, 14, 226, 1, // Opcode: STRDpost +/* 40482 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40519 +/* 40486 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 40489 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40504 +/* 40493 */ MCD_OPC_CheckField, 21, 1, 1, 142, 0, // Skip to: 40641 +/* 40499 */ MCD_OPC_Decode, 227, 14, 200, 2, // Opcode: STRDroW +/* 40504 */ MCD_OPC_FilterValue, 3, 133, 0, // Skip to: 40641 +/* 40508 */ MCD_OPC_CheckField, 21, 1, 1, 127, 0, // Skip to: 40641 +/* 40514 */ MCD_OPC_Decode, 228, 14, 201, 2, // Opcode: STRDroX +/* 40519 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 40641 +/* 40523 */ MCD_OPC_CheckField, 21, 1, 0, 112, 0, // Skip to: 40641 +/* 40529 */ MCD_OPC_Decode, 226, 14, 226, 1, // Opcode: STRDpre +/* 40534 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40623 +/* 40538 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 40541 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40556 +/* 40545 */ MCD_OPC_CheckField, 21, 1, 0, 90, 0, // Skip to: 40641 +/* 40551 */ MCD_OPC_Decode, 157, 8, 226, 1, // Opcode: LDURDi +/* 40556 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40571 +/* 40560 */ MCD_OPC_CheckField, 21, 1, 0, 75, 0, // Skip to: 40641 +/* 40566 */ MCD_OPC_Decode, 209, 7, 226, 1, // Opcode: LDRDpost +/* 40571 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40608 +/* 40575 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 40578 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40593 +/* 40582 */ MCD_OPC_CheckField, 21, 1, 1, 53, 0, // Skip to: 40641 +/* 40588 */ MCD_OPC_Decode, 211, 7, 200, 2, // Opcode: LDRDroW +/* 40593 */ MCD_OPC_FilterValue, 3, 44, 0, // Skip to: 40641 +/* 40597 */ MCD_OPC_CheckField, 21, 1, 1, 38, 0, // Skip to: 40641 +/* 40603 */ MCD_OPC_Decode, 212, 7, 201, 2, // Opcode: LDRDroX +/* 40608 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 40641 +/* 40612 */ MCD_OPC_CheckField, 21, 1, 0, 23, 0, // Skip to: 40641 +/* 40618 */ MCD_OPC_Decode, 210, 7, 226, 1, // Opcode: LDRDpre +/* 40623 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40632 +/* 40627 */ MCD_OPC_Decode, 229, 14, 231, 1, // Opcode: STRDui +/* 40632 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 40641 +/* 40636 */ MCD_OPC_Decode, 213, 7, 231, 1, // Opcode: LDRDui +/* 40641 */ MCD_OPC_Fail, + 0 +}; + +static bool getbool(uint64_t b) +{ + return b != 0; +} + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + switch (Idx) { + default: // llvm_unreachable("Invalid index!"); + case 0: + return getbool((Bits & AArch64_FeatureNEON)); + case 1: + return getbool((Bits & AArch64_FeatureCrypto)); + case 2: + return getbool((Bits & AArch64_FeatureCRC)); + case 3: + return getbool((Bits & AArch64_FeatureFPARMv8)); + } +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 1: \ + if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 12: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 19: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 20: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 21: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 37: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 38: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 39: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 40: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 41: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 42: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 43: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 47: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 52: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 53: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 54: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 57: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 58: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 59: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 60: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 65: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 66: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 69: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 70: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 71: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 72: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 73: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 74: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 75: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 76: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 77: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 78: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 79: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 80: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 81: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 82: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 83: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 84: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 85: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 86: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 87: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 88: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 89: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 90: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 91: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 92: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 93: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 94: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 95: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 96: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 97: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 98: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 99: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 100: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 101: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 102: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 103: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 104: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 105: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 106: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 107: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 108: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 109: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 110: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 111: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 112: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 113: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 114: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 115: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 116: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 117: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 118: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 119: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 120: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 121: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 122: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 123: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 124: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 125: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 126: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 127: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 128: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 129: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 130: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 131: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 132: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 133: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 134: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 135: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 136: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 137: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 138: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 139: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 140: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 141: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 142: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 143: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 144: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 145: \ + if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 146: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 147: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 148: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 149: \ + if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 150: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 151: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 152: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 153: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 154: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 155: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 156: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 157: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 158: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 159: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 160: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 161: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 162: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 163: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 164: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 165: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 166: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 167: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 168: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 169: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 170: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 171: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 172: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 173: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 174: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 175: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 176: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 177: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 178: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 179: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 180: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 181: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 182: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 183: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 184: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 185: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 186: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 187: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 188: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 189: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 190: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 191: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 192: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 193: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 194: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 195: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 196: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 197: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 198: \ + if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 199: \ + if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 200: \ + if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 201: \ + if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 202: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 203: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 204: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 205: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 206: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 207: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 208: \ + if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 209: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 210: \ + if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 211: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 212: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 213: \ + tmp = fieldname(insn, 5, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 214: \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 215: \ + tmp = fieldname(insn, 5, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 216: \ + if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 217: \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 218: \ + tmp = fieldname(insn, 5, 16); \ + if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 219: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 220: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 16); \ + if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 221: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 222: \ + return S; \ + case 223: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 224: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 226: \ + if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 227: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 228: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 229: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 230: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 231: \ + if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 232: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 233: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 234: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 235: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 236: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 237: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 238: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 239: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 240: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 241: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 242: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 243: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 244: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 245: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 246: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 247: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 248: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 249: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 250: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 251: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 252: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 253: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 254: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 255: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 256: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 257: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 258: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 259: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 260: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 261: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 262: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 263: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 264: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 265: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 266: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 267: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 268: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 269: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 270: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 271: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 272: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 273: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 274: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 275: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 276: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 277: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 278: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 279: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 280: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 282: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 283: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 284: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 285: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 286: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 287: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 288: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 289: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 290: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 291: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 292: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 293: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 294: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 295: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 296: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 297: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 298: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 299: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 300: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 301: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 302: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 303: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 304: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 305: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 306: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 307: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 308: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 309: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 310: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 311: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 312: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 313: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 314: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 315: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 316: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 317: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 318: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 319: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 320: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 321: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 322: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 323: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 324: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 325: \ + if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 326: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 327: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 328: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + case 329: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction, uint32_t) +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) +DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64GenInstrInfo.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenInstrInfo.inc new file mode 100644 index 0000000..d3c87b9 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenInstrInfo.inc @@ -0,0 +1,2411 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + AArch64_PHI = 0, + AArch64_INLINEASM = 1, + AArch64_CFI_INSTRUCTION = 2, + AArch64_EH_LABEL = 3, + AArch64_GC_LABEL = 4, + AArch64_KILL = 5, + AArch64_EXTRACT_SUBREG = 6, + AArch64_INSERT_SUBREG = 7, + AArch64_IMPLICIT_DEF = 8, + AArch64_SUBREG_TO_REG = 9, + AArch64_COPY_TO_REGCLASS = 10, + AArch64_DBG_VALUE = 11, + AArch64_REG_SEQUENCE = 12, + AArch64_COPY = 13, + AArch64_BUNDLE = 14, + AArch64_LIFETIME_START = 15, + AArch64_LIFETIME_END = 16, + AArch64_STACKMAP = 17, + AArch64_PATCHPOINT = 18, + AArch64_LOAD_STACK_GUARD = 19, + AArch64_STATEPOINT = 20, + AArch64_FRAME_ALLOC = 21, + AArch64_ABSv16i8 = 22, + AArch64_ABSv1i64 = 23, + AArch64_ABSv2i32 = 24, + AArch64_ABSv2i64 = 25, + AArch64_ABSv4i16 = 26, + AArch64_ABSv4i32 = 27, + AArch64_ABSv8i16 = 28, + AArch64_ABSv8i8 = 29, + AArch64_ADCSWr = 30, + AArch64_ADCSXr = 31, + AArch64_ADCWr = 32, + AArch64_ADCXr = 33, + AArch64_ADDHNv2i64_v2i32 = 34, + AArch64_ADDHNv2i64_v4i32 = 35, + AArch64_ADDHNv4i32_v4i16 = 36, + AArch64_ADDHNv4i32_v8i16 = 37, + AArch64_ADDHNv8i16_v16i8 = 38, + AArch64_ADDHNv8i16_v8i8 = 39, + AArch64_ADDPv16i8 = 40, + AArch64_ADDPv2i32 = 41, + AArch64_ADDPv2i64 = 42, + AArch64_ADDPv2i64p = 43, + AArch64_ADDPv4i16 = 44, + AArch64_ADDPv4i32 = 45, + AArch64_ADDPv8i16 = 46, + AArch64_ADDPv8i8 = 47, + AArch64_ADDSWri = 48, + AArch64_ADDSWrr = 49, + AArch64_ADDSWrs = 50, + AArch64_ADDSWrx = 51, + AArch64_ADDSXri = 52, + AArch64_ADDSXrr = 53, + AArch64_ADDSXrs = 54, + AArch64_ADDSXrx = 55, + AArch64_ADDSXrx64 = 56, + AArch64_ADDVv16i8v = 57, + AArch64_ADDVv4i16v = 58, + AArch64_ADDVv4i32v = 59, + AArch64_ADDVv8i16v = 60, + AArch64_ADDVv8i8v = 61, + AArch64_ADDWri = 62, + AArch64_ADDWrr = 63, + AArch64_ADDWrs = 64, + AArch64_ADDWrx = 65, + AArch64_ADDXri = 66, + AArch64_ADDXrr = 67, + AArch64_ADDXrs = 68, + AArch64_ADDXrx = 69, + AArch64_ADDXrx64 = 70, + AArch64_ADDv16i8 = 71, + AArch64_ADDv1i64 = 72, + AArch64_ADDv2i32 = 73, + AArch64_ADDv2i64 = 74, + AArch64_ADDv4i16 = 75, + AArch64_ADDv4i32 = 76, + AArch64_ADDv8i16 = 77, + AArch64_ADDv8i8 = 78, + AArch64_ADJCALLSTACKDOWN = 79, + AArch64_ADJCALLSTACKUP = 80, + AArch64_ADR = 81, + AArch64_ADRP = 82, + AArch64_AESDrr = 83, + AArch64_AESErr = 84, + AArch64_AESIMCrr = 85, + AArch64_AESMCrr = 86, + AArch64_ANDSWri = 87, + AArch64_ANDSWrr = 88, + AArch64_ANDSWrs = 89, + AArch64_ANDSXri = 90, + AArch64_ANDSXrr = 91, + AArch64_ANDSXrs = 92, + AArch64_ANDWri = 93, + AArch64_ANDWrr = 94, + AArch64_ANDWrs = 95, + AArch64_ANDXri = 96, + AArch64_ANDXrr = 97, + AArch64_ANDXrs = 98, + AArch64_ANDv16i8 = 99, + AArch64_ANDv8i8 = 100, + AArch64_ASRVWr = 101, + AArch64_ASRVXr = 102, + AArch64_B = 103, + AArch64_BFMWri = 104, + AArch64_BFMXri = 105, + AArch64_BICSWrr = 106, + AArch64_BICSWrs = 107, + AArch64_BICSXrr = 108, + AArch64_BICSXrs = 109, + AArch64_BICWrr = 110, + AArch64_BICWrs = 111, + AArch64_BICXrr = 112, + AArch64_BICXrs = 113, + AArch64_BICv16i8 = 114, + AArch64_BICv2i32 = 115, + AArch64_BICv4i16 = 116, + AArch64_BICv4i32 = 117, + AArch64_BICv8i16 = 118, + AArch64_BICv8i8 = 119, + AArch64_BIFv16i8 = 120, + AArch64_BIFv8i8 = 121, + AArch64_BITv16i8 = 122, + AArch64_BITv8i8 = 123, + AArch64_BL = 124, + AArch64_BLR = 125, + AArch64_BR = 126, + AArch64_BRK = 127, + AArch64_BSLv16i8 = 128, + AArch64_BSLv8i8 = 129, + AArch64_Bcc = 130, + AArch64_CBNZW = 131, + AArch64_CBNZX = 132, + AArch64_CBZW = 133, + AArch64_CBZX = 134, + AArch64_CCMNWi = 135, + AArch64_CCMNWr = 136, + AArch64_CCMNXi = 137, + AArch64_CCMNXr = 138, + AArch64_CCMPWi = 139, + AArch64_CCMPWr = 140, + AArch64_CCMPXi = 141, + AArch64_CCMPXr = 142, + AArch64_CLREX = 143, + AArch64_CLSWr = 144, + AArch64_CLSXr = 145, + AArch64_CLSv16i8 = 146, + AArch64_CLSv2i32 = 147, + AArch64_CLSv4i16 = 148, + AArch64_CLSv4i32 = 149, + AArch64_CLSv8i16 = 150, + AArch64_CLSv8i8 = 151, + AArch64_CLZWr = 152, + AArch64_CLZXr = 153, + AArch64_CLZv16i8 = 154, + AArch64_CLZv2i32 = 155, + AArch64_CLZv4i16 = 156, + AArch64_CLZv4i32 = 157, + AArch64_CLZv8i16 = 158, + AArch64_CLZv8i8 = 159, + AArch64_CMEQv16i8 = 160, + AArch64_CMEQv16i8rz = 161, + AArch64_CMEQv1i64 = 162, + AArch64_CMEQv1i64rz = 163, + AArch64_CMEQv2i32 = 164, + AArch64_CMEQv2i32rz = 165, + AArch64_CMEQv2i64 = 166, + AArch64_CMEQv2i64rz = 167, + AArch64_CMEQv4i16 = 168, + AArch64_CMEQv4i16rz = 169, + AArch64_CMEQv4i32 = 170, + AArch64_CMEQv4i32rz = 171, + AArch64_CMEQv8i16 = 172, + AArch64_CMEQv8i16rz = 173, + AArch64_CMEQv8i8 = 174, + AArch64_CMEQv8i8rz = 175, + AArch64_CMGEv16i8 = 176, + AArch64_CMGEv16i8rz = 177, + AArch64_CMGEv1i64 = 178, + AArch64_CMGEv1i64rz = 179, + AArch64_CMGEv2i32 = 180, + AArch64_CMGEv2i32rz = 181, + AArch64_CMGEv2i64 = 182, + AArch64_CMGEv2i64rz = 183, + AArch64_CMGEv4i16 = 184, + AArch64_CMGEv4i16rz = 185, + AArch64_CMGEv4i32 = 186, + AArch64_CMGEv4i32rz = 187, + AArch64_CMGEv8i16 = 188, + AArch64_CMGEv8i16rz = 189, + AArch64_CMGEv8i8 = 190, + AArch64_CMGEv8i8rz = 191, + AArch64_CMGTv16i8 = 192, + AArch64_CMGTv16i8rz = 193, + AArch64_CMGTv1i64 = 194, + AArch64_CMGTv1i64rz = 195, + AArch64_CMGTv2i32 = 196, + AArch64_CMGTv2i32rz = 197, + AArch64_CMGTv2i64 = 198, + AArch64_CMGTv2i64rz = 199, + AArch64_CMGTv4i16 = 200, + AArch64_CMGTv4i16rz = 201, + AArch64_CMGTv4i32 = 202, + AArch64_CMGTv4i32rz = 203, + AArch64_CMGTv8i16 = 204, + AArch64_CMGTv8i16rz = 205, + AArch64_CMGTv8i8 = 206, + AArch64_CMGTv8i8rz = 207, + AArch64_CMHIv16i8 = 208, + AArch64_CMHIv1i64 = 209, + AArch64_CMHIv2i32 = 210, + AArch64_CMHIv2i64 = 211, + AArch64_CMHIv4i16 = 212, + AArch64_CMHIv4i32 = 213, + AArch64_CMHIv8i16 = 214, + AArch64_CMHIv8i8 = 215, + AArch64_CMHSv16i8 = 216, + AArch64_CMHSv1i64 = 217, + AArch64_CMHSv2i32 = 218, + AArch64_CMHSv2i64 = 219, + AArch64_CMHSv4i16 = 220, + AArch64_CMHSv4i32 = 221, + AArch64_CMHSv8i16 = 222, + AArch64_CMHSv8i8 = 223, + AArch64_CMLEv16i8rz = 224, + AArch64_CMLEv1i64rz = 225, + AArch64_CMLEv2i32rz = 226, + AArch64_CMLEv2i64rz = 227, + AArch64_CMLEv4i16rz = 228, + AArch64_CMLEv4i32rz = 229, + AArch64_CMLEv8i16rz = 230, + AArch64_CMLEv8i8rz = 231, + AArch64_CMLTv16i8rz = 232, + AArch64_CMLTv1i64rz = 233, + AArch64_CMLTv2i32rz = 234, + AArch64_CMLTv2i64rz = 235, + AArch64_CMLTv4i16rz = 236, + AArch64_CMLTv4i32rz = 237, + AArch64_CMLTv8i16rz = 238, + AArch64_CMLTv8i8rz = 239, + AArch64_CMTSTv16i8 = 240, + AArch64_CMTSTv1i64 = 241, + AArch64_CMTSTv2i32 = 242, + AArch64_CMTSTv2i64 = 243, + AArch64_CMTSTv4i16 = 244, + AArch64_CMTSTv4i32 = 245, + AArch64_CMTSTv8i16 = 246, + AArch64_CMTSTv8i8 = 247, + AArch64_CNTv16i8 = 248, + AArch64_CNTv8i8 = 249, + AArch64_CPYi16 = 250, + AArch64_CPYi32 = 251, + AArch64_CPYi64 = 252, + AArch64_CPYi8 = 253, + AArch64_CRC32Brr = 254, + AArch64_CRC32CBrr = 255, + AArch64_CRC32CHrr = 256, + AArch64_CRC32CWrr = 257, + AArch64_CRC32CXrr = 258, + AArch64_CRC32Hrr = 259, + AArch64_CRC32Wrr = 260, + AArch64_CRC32Xrr = 261, + AArch64_CSELWr = 262, + AArch64_CSELXr = 263, + AArch64_CSINCWr = 264, + AArch64_CSINCXr = 265, + AArch64_CSINVWr = 266, + AArch64_CSINVXr = 267, + AArch64_CSNEGWr = 268, + AArch64_CSNEGXr = 269, + AArch64_DCPS1 = 270, + AArch64_DCPS2 = 271, + AArch64_DCPS3 = 272, + AArch64_DMB = 273, + AArch64_DRPS = 274, + AArch64_DSB = 275, + AArch64_DUPv16i8gpr = 276, + AArch64_DUPv16i8lane = 277, + AArch64_DUPv2i32gpr = 278, + AArch64_DUPv2i32lane = 279, + AArch64_DUPv2i64gpr = 280, + AArch64_DUPv2i64lane = 281, + AArch64_DUPv4i16gpr = 282, + AArch64_DUPv4i16lane = 283, + AArch64_DUPv4i32gpr = 284, + AArch64_DUPv4i32lane = 285, + AArch64_DUPv8i16gpr = 286, + AArch64_DUPv8i16lane = 287, + AArch64_DUPv8i8gpr = 288, + AArch64_DUPv8i8lane = 289, + AArch64_EONWrr = 290, + AArch64_EONWrs = 291, + AArch64_EONXrr = 292, + AArch64_EONXrs = 293, + AArch64_EORWri = 294, + AArch64_EORWrr = 295, + AArch64_EORWrs = 296, + AArch64_EORXri = 297, + AArch64_EORXrr = 298, + AArch64_EORXrs = 299, + AArch64_EORv16i8 = 300, + AArch64_EORv8i8 = 301, + AArch64_ERET = 302, + AArch64_EXTRWrri = 303, + AArch64_EXTRXrri = 304, + AArch64_EXTv16i8 = 305, + AArch64_EXTv8i8 = 306, + AArch64_F128CSEL = 307, + AArch64_FABD32 = 308, + AArch64_FABD64 = 309, + AArch64_FABDv2f32 = 310, + AArch64_FABDv2f64 = 311, + AArch64_FABDv4f32 = 312, + AArch64_FABSDr = 313, + AArch64_FABSSr = 314, + AArch64_FABSv2f32 = 315, + AArch64_FABSv2f64 = 316, + AArch64_FABSv4f32 = 317, + AArch64_FACGE32 = 318, + AArch64_FACGE64 = 319, + AArch64_FACGEv2f32 = 320, + AArch64_FACGEv2f64 = 321, + AArch64_FACGEv4f32 = 322, + AArch64_FACGT32 = 323, + AArch64_FACGT64 = 324, + AArch64_FACGTv2f32 = 325, + AArch64_FACGTv2f64 = 326, + AArch64_FACGTv4f32 = 327, + AArch64_FADDDrr = 328, + AArch64_FADDPv2f32 = 329, + AArch64_FADDPv2f64 = 330, + AArch64_FADDPv2i32p = 331, + AArch64_FADDPv2i64p = 332, + AArch64_FADDPv4f32 = 333, + AArch64_FADDSrr = 334, + AArch64_FADDv2f32 = 335, + AArch64_FADDv2f64 = 336, + AArch64_FADDv4f32 = 337, + AArch64_FCCMPDrr = 338, + AArch64_FCCMPEDrr = 339, + AArch64_FCCMPESrr = 340, + AArch64_FCCMPSrr = 341, + AArch64_FCMEQ32 = 342, + AArch64_FCMEQ64 = 343, + AArch64_FCMEQv1i32rz = 344, + AArch64_FCMEQv1i64rz = 345, + AArch64_FCMEQv2f32 = 346, + AArch64_FCMEQv2f64 = 347, + AArch64_FCMEQv2i32rz = 348, + AArch64_FCMEQv2i64rz = 349, + AArch64_FCMEQv4f32 = 350, + AArch64_FCMEQv4i32rz = 351, + AArch64_FCMGE32 = 352, + AArch64_FCMGE64 = 353, + AArch64_FCMGEv1i32rz = 354, + AArch64_FCMGEv1i64rz = 355, + AArch64_FCMGEv2f32 = 356, + AArch64_FCMGEv2f64 = 357, + AArch64_FCMGEv2i32rz = 358, + AArch64_FCMGEv2i64rz = 359, + AArch64_FCMGEv4f32 = 360, + AArch64_FCMGEv4i32rz = 361, + AArch64_FCMGT32 = 362, + AArch64_FCMGT64 = 363, + AArch64_FCMGTv1i32rz = 364, + AArch64_FCMGTv1i64rz = 365, + AArch64_FCMGTv2f32 = 366, + AArch64_FCMGTv2f64 = 367, + AArch64_FCMGTv2i32rz = 368, + AArch64_FCMGTv2i64rz = 369, + AArch64_FCMGTv4f32 = 370, + AArch64_FCMGTv4i32rz = 371, + AArch64_FCMLEv1i32rz = 372, + AArch64_FCMLEv1i64rz = 373, + AArch64_FCMLEv2i32rz = 374, + AArch64_FCMLEv2i64rz = 375, + AArch64_FCMLEv4i32rz = 376, + AArch64_FCMLTv1i32rz = 377, + AArch64_FCMLTv1i64rz = 378, + AArch64_FCMLTv2i32rz = 379, + AArch64_FCMLTv2i64rz = 380, + AArch64_FCMLTv4i32rz = 381, + AArch64_FCMPDri = 382, + AArch64_FCMPDrr = 383, + AArch64_FCMPEDri = 384, + AArch64_FCMPEDrr = 385, + AArch64_FCMPESri = 386, + AArch64_FCMPESrr = 387, + AArch64_FCMPSri = 388, + AArch64_FCMPSrr = 389, + AArch64_FCSELDrrr = 390, + AArch64_FCSELSrrr = 391, + AArch64_FCVTASUWDr = 392, + AArch64_FCVTASUWSr = 393, + AArch64_FCVTASUXDr = 394, + AArch64_FCVTASUXSr = 395, + AArch64_FCVTASv1i32 = 396, + AArch64_FCVTASv1i64 = 397, + AArch64_FCVTASv2f32 = 398, + AArch64_FCVTASv2f64 = 399, + AArch64_FCVTASv4f32 = 400, + AArch64_FCVTAUUWDr = 401, + AArch64_FCVTAUUWSr = 402, + AArch64_FCVTAUUXDr = 403, + AArch64_FCVTAUUXSr = 404, + AArch64_FCVTAUv1i32 = 405, + AArch64_FCVTAUv1i64 = 406, + AArch64_FCVTAUv2f32 = 407, + AArch64_FCVTAUv2f64 = 408, + AArch64_FCVTAUv4f32 = 409, + AArch64_FCVTDHr = 410, + AArch64_FCVTDSr = 411, + AArch64_FCVTHDr = 412, + AArch64_FCVTHSr = 413, + AArch64_FCVTLv2i32 = 414, + AArch64_FCVTLv4i16 = 415, + AArch64_FCVTLv4i32 = 416, + AArch64_FCVTLv8i16 = 417, + AArch64_FCVTMSUWDr = 418, + AArch64_FCVTMSUWSr = 419, + AArch64_FCVTMSUXDr = 420, + AArch64_FCVTMSUXSr = 421, + AArch64_FCVTMSv1i32 = 422, + AArch64_FCVTMSv1i64 = 423, + AArch64_FCVTMSv2f32 = 424, + AArch64_FCVTMSv2f64 = 425, + AArch64_FCVTMSv4f32 = 426, + AArch64_FCVTMUUWDr = 427, + AArch64_FCVTMUUWSr = 428, + AArch64_FCVTMUUXDr = 429, + AArch64_FCVTMUUXSr = 430, + AArch64_FCVTMUv1i32 = 431, + AArch64_FCVTMUv1i64 = 432, + AArch64_FCVTMUv2f32 = 433, + AArch64_FCVTMUv2f64 = 434, + AArch64_FCVTMUv4f32 = 435, + AArch64_FCVTNSUWDr = 436, + AArch64_FCVTNSUWSr = 437, + AArch64_FCVTNSUXDr = 438, + AArch64_FCVTNSUXSr = 439, + AArch64_FCVTNSv1i32 = 440, + AArch64_FCVTNSv1i64 = 441, + AArch64_FCVTNSv2f32 = 442, + AArch64_FCVTNSv2f64 = 443, + AArch64_FCVTNSv4f32 = 444, + AArch64_FCVTNUUWDr = 445, + AArch64_FCVTNUUWSr = 446, + AArch64_FCVTNUUXDr = 447, + AArch64_FCVTNUUXSr = 448, + AArch64_FCVTNUv1i32 = 449, + AArch64_FCVTNUv1i64 = 450, + AArch64_FCVTNUv2f32 = 451, + AArch64_FCVTNUv2f64 = 452, + AArch64_FCVTNUv4f32 = 453, + AArch64_FCVTNv2i32 = 454, + AArch64_FCVTNv4i16 = 455, + AArch64_FCVTNv4i32 = 456, + AArch64_FCVTNv8i16 = 457, + AArch64_FCVTPSUWDr = 458, + AArch64_FCVTPSUWSr = 459, + AArch64_FCVTPSUXDr = 460, + AArch64_FCVTPSUXSr = 461, + AArch64_FCVTPSv1i32 = 462, + AArch64_FCVTPSv1i64 = 463, + AArch64_FCVTPSv2f32 = 464, + AArch64_FCVTPSv2f64 = 465, + AArch64_FCVTPSv4f32 = 466, + AArch64_FCVTPUUWDr = 467, + AArch64_FCVTPUUWSr = 468, + AArch64_FCVTPUUXDr = 469, + AArch64_FCVTPUUXSr = 470, + AArch64_FCVTPUv1i32 = 471, + AArch64_FCVTPUv1i64 = 472, + AArch64_FCVTPUv2f32 = 473, + AArch64_FCVTPUv2f64 = 474, + AArch64_FCVTPUv4f32 = 475, + AArch64_FCVTSDr = 476, + AArch64_FCVTSHr = 477, + AArch64_FCVTXNv1i64 = 478, + AArch64_FCVTXNv2f32 = 479, + AArch64_FCVTXNv4f32 = 480, + AArch64_FCVTZSSWDri = 481, + AArch64_FCVTZSSWSri = 482, + AArch64_FCVTZSSXDri = 483, + AArch64_FCVTZSSXSri = 484, + AArch64_FCVTZSUWDr = 485, + AArch64_FCVTZSUWSr = 486, + AArch64_FCVTZSUXDr = 487, + AArch64_FCVTZSUXSr = 488, + AArch64_FCVTZS_IntSWDri = 489, + AArch64_FCVTZS_IntSWSri = 490, + AArch64_FCVTZS_IntSXDri = 491, + AArch64_FCVTZS_IntSXSri = 492, + AArch64_FCVTZS_IntUWDr = 493, + AArch64_FCVTZS_IntUWSr = 494, + AArch64_FCVTZS_IntUXDr = 495, + AArch64_FCVTZS_IntUXSr = 496, + AArch64_FCVTZS_Intv2f32 = 497, + AArch64_FCVTZS_Intv2f64 = 498, + AArch64_FCVTZS_Intv4f32 = 499, + AArch64_FCVTZSd = 500, + AArch64_FCVTZSs = 501, + AArch64_FCVTZSv1i32 = 502, + AArch64_FCVTZSv1i64 = 503, + AArch64_FCVTZSv2f32 = 504, + AArch64_FCVTZSv2f64 = 505, + AArch64_FCVTZSv2i32_shift = 506, + AArch64_FCVTZSv2i64_shift = 507, + AArch64_FCVTZSv4f32 = 508, + AArch64_FCVTZSv4i32_shift = 509, + AArch64_FCVTZUSWDri = 510, + AArch64_FCVTZUSWSri = 511, + AArch64_FCVTZUSXDri = 512, + AArch64_FCVTZUSXSri = 513, + AArch64_FCVTZUUWDr = 514, + AArch64_FCVTZUUWSr = 515, + AArch64_FCVTZUUXDr = 516, + AArch64_FCVTZUUXSr = 517, + AArch64_FCVTZU_IntSWDri = 518, + AArch64_FCVTZU_IntSWSri = 519, + AArch64_FCVTZU_IntSXDri = 520, + AArch64_FCVTZU_IntSXSri = 521, + AArch64_FCVTZU_IntUWDr = 522, + AArch64_FCVTZU_IntUWSr = 523, + AArch64_FCVTZU_IntUXDr = 524, + AArch64_FCVTZU_IntUXSr = 525, + AArch64_FCVTZU_Intv2f32 = 526, + AArch64_FCVTZU_Intv2f64 = 527, + AArch64_FCVTZU_Intv4f32 = 528, + AArch64_FCVTZUd = 529, + AArch64_FCVTZUs = 530, + AArch64_FCVTZUv1i32 = 531, + AArch64_FCVTZUv1i64 = 532, + AArch64_FCVTZUv2f32 = 533, + AArch64_FCVTZUv2f64 = 534, + AArch64_FCVTZUv2i32_shift = 535, + AArch64_FCVTZUv2i64_shift = 536, + AArch64_FCVTZUv4f32 = 537, + AArch64_FCVTZUv4i32_shift = 538, + AArch64_FDIVDrr = 539, + AArch64_FDIVSrr = 540, + AArch64_FDIVv2f32 = 541, + AArch64_FDIVv2f64 = 542, + AArch64_FDIVv4f32 = 543, + AArch64_FMADDDrrr = 544, + AArch64_FMADDSrrr = 545, + AArch64_FMAXDrr = 546, + AArch64_FMAXNMDrr = 547, + AArch64_FMAXNMPv2f32 = 548, + AArch64_FMAXNMPv2f64 = 549, + AArch64_FMAXNMPv2i32p = 550, + AArch64_FMAXNMPv2i64p = 551, + AArch64_FMAXNMPv4f32 = 552, + AArch64_FMAXNMSrr = 553, + AArch64_FMAXNMVv4i32v = 554, + AArch64_FMAXNMv2f32 = 555, + AArch64_FMAXNMv2f64 = 556, + AArch64_FMAXNMv4f32 = 557, + AArch64_FMAXPv2f32 = 558, + AArch64_FMAXPv2f64 = 559, + AArch64_FMAXPv2i32p = 560, + AArch64_FMAXPv2i64p = 561, + AArch64_FMAXPv4f32 = 562, + AArch64_FMAXSrr = 563, + AArch64_FMAXVv4i32v = 564, + AArch64_FMAXv2f32 = 565, + AArch64_FMAXv2f64 = 566, + AArch64_FMAXv4f32 = 567, + AArch64_FMINDrr = 568, + AArch64_FMINNMDrr = 569, + AArch64_FMINNMPv2f32 = 570, + AArch64_FMINNMPv2f64 = 571, + AArch64_FMINNMPv2i32p = 572, + AArch64_FMINNMPv2i64p = 573, + AArch64_FMINNMPv4f32 = 574, + AArch64_FMINNMSrr = 575, + AArch64_FMINNMVv4i32v = 576, + AArch64_FMINNMv2f32 = 577, + AArch64_FMINNMv2f64 = 578, + AArch64_FMINNMv4f32 = 579, + AArch64_FMINPv2f32 = 580, + AArch64_FMINPv2f64 = 581, + AArch64_FMINPv2i32p = 582, + AArch64_FMINPv2i64p = 583, + AArch64_FMINPv4f32 = 584, + AArch64_FMINSrr = 585, + AArch64_FMINVv4i32v = 586, + AArch64_FMINv2f32 = 587, + AArch64_FMINv2f64 = 588, + AArch64_FMINv4f32 = 589, + AArch64_FMLAv1i32_indexed = 590, + AArch64_FMLAv1i64_indexed = 591, + AArch64_FMLAv2f32 = 592, + AArch64_FMLAv2f64 = 593, + AArch64_FMLAv2i32_indexed = 594, + AArch64_FMLAv2i64_indexed = 595, + AArch64_FMLAv4f32 = 596, + AArch64_FMLAv4i32_indexed = 597, + AArch64_FMLSv1i32_indexed = 598, + AArch64_FMLSv1i64_indexed = 599, + AArch64_FMLSv2f32 = 600, + AArch64_FMLSv2f64 = 601, + AArch64_FMLSv2i32_indexed = 602, + AArch64_FMLSv2i64_indexed = 603, + AArch64_FMLSv4f32 = 604, + AArch64_FMLSv4i32_indexed = 605, + AArch64_FMOVDXHighr = 606, + AArch64_FMOVDXr = 607, + AArch64_FMOVDi = 608, + AArch64_FMOVDr = 609, + AArch64_FMOVSWr = 610, + AArch64_FMOVSi = 611, + AArch64_FMOVSr = 612, + AArch64_FMOVWSr = 613, + AArch64_FMOVXDHighr = 614, + AArch64_FMOVXDr = 615, + AArch64_FMOVv2f32_ns = 616, + AArch64_FMOVv2f64_ns = 617, + AArch64_FMOVv4f32_ns = 618, + AArch64_FMSUBDrrr = 619, + AArch64_FMSUBSrrr = 620, + AArch64_FMULDrr = 621, + AArch64_FMULSrr = 622, + AArch64_FMULX32 = 623, + AArch64_FMULX64 = 624, + AArch64_FMULXv1i32_indexed = 625, + AArch64_FMULXv1i64_indexed = 626, + AArch64_FMULXv2f32 = 627, + AArch64_FMULXv2f64 = 628, + AArch64_FMULXv2i32_indexed = 629, + AArch64_FMULXv2i64_indexed = 630, + AArch64_FMULXv4f32 = 631, + AArch64_FMULXv4i32_indexed = 632, + AArch64_FMULv1i32_indexed = 633, + AArch64_FMULv1i64_indexed = 634, + AArch64_FMULv2f32 = 635, + AArch64_FMULv2f64 = 636, + AArch64_FMULv2i32_indexed = 637, + AArch64_FMULv2i64_indexed = 638, + AArch64_FMULv4f32 = 639, + AArch64_FMULv4i32_indexed = 640, + AArch64_FNEGDr = 641, + AArch64_FNEGSr = 642, + AArch64_FNEGv2f32 = 643, + AArch64_FNEGv2f64 = 644, + AArch64_FNEGv4f32 = 645, + AArch64_FNMADDDrrr = 646, + AArch64_FNMADDSrrr = 647, + AArch64_FNMSUBDrrr = 648, + AArch64_FNMSUBSrrr = 649, + AArch64_FNMULDrr = 650, + AArch64_FNMULSrr = 651, + AArch64_FRECPEv1i32 = 652, + AArch64_FRECPEv1i64 = 653, + AArch64_FRECPEv2f32 = 654, + AArch64_FRECPEv2f64 = 655, + AArch64_FRECPEv4f32 = 656, + AArch64_FRECPS32 = 657, + AArch64_FRECPS64 = 658, + AArch64_FRECPSv2f32 = 659, + AArch64_FRECPSv2f64 = 660, + AArch64_FRECPSv4f32 = 661, + AArch64_FRECPXv1i32 = 662, + AArch64_FRECPXv1i64 = 663, + AArch64_FRINTADr = 664, + AArch64_FRINTASr = 665, + AArch64_FRINTAv2f32 = 666, + AArch64_FRINTAv2f64 = 667, + AArch64_FRINTAv4f32 = 668, + AArch64_FRINTIDr = 669, + AArch64_FRINTISr = 670, + AArch64_FRINTIv2f32 = 671, + AArch64_FRINTIv2f64 = 672, + AArch64_FRINTIv4f32 = 673, + AArch64_FRINTMDr = 674, + AArch64_FRINTMSr = 675, + AArch64_FRINTMv2f32 = 676, + AArch64_FRINTMv2f64 = 677, + AArch64_FRINTMv4f32 = 678, + AArch64_FRINTNDr = 679, + AArch64_FRINTNSr = 680, + AArch64_FRINTNv2f32 = 681, + AArch64_FRINTNv2f64 = 682, + AArch64_FRINTNv4f32 = 683, + AArch64_FRINTPDr = 684, + AArch64_FRINTPSr = 685, + AArch64_FRINTPv2f32 = 686, + AArch64_FRINTPv2f64 = 687, + AArch64_FRINTPv4f32 = 688, + AArch64_FRINTXDr = 689, + AArch64_FRINTXSr = 690, + AArch64_FRINTXv2f32 = 691, + AArch64_FRINTXv2f64 = 692, + AArch64_FRINTXv4f32 = 693, + AArch64_FRINTZDr = 694, + AArch64_FRINTZSr = 695, + AArch64_FRINTZv2f32 = 696, + AArch64_FRINTZv2f64 = 697, + AArch64_FRINTZv4f32 = 698, + AArch64_FRSQRTEv1i32 = 699, + AArch64_FRSQRTEv1i64 = 700, + AArch64_FRSQRTEv2f32 = 701, + AArch64_FRSQRTEv2f64 = 702, + AArch64_FRSQRTEv4f32 = 703, + AArch64_FRSQRTS32 = 704, + AArch64_FRSQRTS64 = 705, + AArch64_FRSQRTSv2f32 = 706, + AArch64_FRSQRTSv2f64 = 707, + AArch64_FRSQRTSv4f32 = 708, + AArch64_FSQRTDr = 709, + AArch64_FSQRTSr = 710, + AArch64_FSQRTv2f32 = 711, + AArch64_FSQRTv2f64 = 712, + AArch64_FSQRTv4f32 = 713, + AArch64_FSUBDrr = 714, + AArch64_FSUBSrr = 715, + AArch64_FSUBv2f32 = 716, + AArch64_FSUBv2f64 = 717, + AArch64_FSUBv4f32 = 718, + AArch64_HINT = 719, + AArch64_HLT = 720, + AArch64_HVC = 721, + AArch64_INSvi16gpr = 722, + AArch64_INSvi16lane = 723, + AArch64_INSvi32gpr = 724, + AArch64_INSvi32lane = 725, + AArch64_INSvi64gpr = 726, + AArch64_INSvi64lane = 727, + AArch64_INSvi8gpr = 728, + AArch64_INSvi8lane = 729, + AArch64_ISB = 730, + AArch64_LD1Fourv16b = 731, + AArch64_LD1Fourv16b_POST = 732, + AArch64_LD1Fourv1d = 733, + AArch64_LD1Fourv1d_POST = 734, + AArch64_LD1Fourv2d = 735, + AArch64_LD1Fourv2d_POST = 736, + AArch64_LD1Fourv2s = 737, + AArch64_LD1Fourv2s_POST = 738, + AArch64_LD1Fourv4h = 739, + AArch64_LD1Fourv4h_POST = 740, + AArch64_LD1Fourv4s = 741, + AArch64_LD1Fourv4s_POST = 742, + AArch64_LD1Fourv8b = 743, + AArch64_LD1Fourv8b_POST = 744, + AArch64_LD1Fourv8h = 745, + AArch64_LD1Fourv8h_POST = 746, + AArch64_LD1Onev16b = 747, + AArch64_LD1Onev16b_POST = 748, + AArch64_LD1Onev1d = 749, + AArch64_LD1Onev1d_POST = 750, + AArch64_LD1Onev2d = 751, + AArch64_LD1Onev2d_POST = 752, + AArch64_LD1Onev2s = 753, + AArch64_LD1Onev2s_POST = 754, + AArch64_LD1Onev4h = 755, + AArch64_LD1Onev4h_POST = 756, + AArch64_LD1Onev4s = 757, + AArch64_LD1Onev4s_POST = 758, + AArch64_LD1Onev8b = 759, + AArch64_LD1Onev8b_POST = 760, + AArch64_LD1Onev8h = 761, + AArch64_LD1Onev8h_POST = 762, + AArch64_LD1Rv16b = 763, + AArch64_LD1Rv16b_POST = 764, + AArch64_LD1Rv1d = 765, + AArch64_LD1Rv1d_POST = 766, + AArch64_LD1Rv2d = 767, + AArch64_LD1Rv2d_POST = 768, + AArch64_LD1Rv2s = 769, + AArch64_LD1Rv2s_POST = 770, + AArch64_LD1Rv4h = 771, + AArch64_LD1Rv4h_POST = 772, + AArch64_LD1Rv4s = 773, + AArch64_LD1Rv4s_POST = 774, + AArch64_LD1Rv8b = 775, + AArch64_LD1Rv8b_POST = 776, + AArch64_LD1Rv8h = 777, + AArch64_LD1Rv8h_POST = 778, + AArch64_LD1Threev16b = 779, + AArch64_LD1Threev16b_POST = 780, + AArch64_LD1Threev1d = 781, + AArch64_LD1Threev1d_POST = 782, + AArch64_LD1Threev2d = 783, + AArch64_LD1Threev2d_POST = 784, + AArch64_LD1Threev2s = 785, + AArch64_LD1Threev2s_POST = 786, + AArch64_LD1Threev4h = 787, + AArch64_LD1Threev4h_POST = 788, + AArch64_LD1Threev4s = 789, + AArch64_LD1Threev4s_POST = 790, + AArch64_LD1Threev8b = 791, + AArch64_LD1Threev8b_POST = 792, + AArch64_LD1Threev8h = 793, + AArch64_LD1Threev8h_POST = 794, + AArch64_LD1Twov16b = 795, + AArch64_LD1Twov16b_POST = 796, + AArch64_LD1Twov1d = 797, + AArch64_LD1Twov1d_POST = 798, + AArch64_LD1Twov2d = 799, + AArch64_LD1Twov2d_POST = 800, + AArch64_LD1Twov2s = 801, + AArch64_LD1Twov2s_POST = 802, + AArch64_LD1Twov4h = 803, + AArch64_LD1Twov4h_POST = 804, + AArch64_LD1Twov4s = 805, + AArch64_LD1Twov4s_POST = 806, + AArch64_LD1Twov8b = 807, + AArch64_LD1Twov8b_POST = 808, + AArch64_LD1Twov8h = 809, + AArch64_LD1Twov8h_POST = 810, + AArch64_LD1i16 = 811, + AArch64_LD1i16_POST = 812, + AArch64_LD1i32 = 813, + AArch64_LD1i32_POST = 814, + AArch64_LD1i64 = 815, + AArch64_LD1i64_POST = 816, + AArch64_LD1i8 = 817, + AArch64_LD1i8_POST = 818, + AArch64_LD2Rv16b = 819, + AArch64_LD2Rv16b_POST = 820, + AArch64_LD2Rv1d = 821, + AArch64_LD2Rv1d_POST = 822, + AArch64_LD2Rv2d = 823, + AArch64_LD2Rv2d_POST = 824, + AArch64_LD2Rv2s = 825, + AArch64_LD2Rv2s_POST = 826, + AArch64_LD2Rv4h = 827, + AArch64_LD2Rv4h_POST = 828, + AArch64_LD2Rv4s = 829, + AArch64_LD2Rv4s_POST = 830, + AArch64_LD2Rv8b = 831, + AArch64_LD2Rv8b_POST = 832, + AArch64_LD2Rv8h = 833, + AArch64_LD2Rv8h_POST = 834, + AArch64_LD2Twov16b = 835, + AArch64_LD2Twov16b_POST = 836, + AArch64_LD2Twov2d = 837, + AArch64_LD2Twov2d_POST = 838, + AArch64_LD2Twov2s = 839, + AArch64_LD2Twov2s_POST = 840, + AArch64_LD2Twov4h = 841, + AArch64_LD2Twov4h_POST = 842, + AArch64_LD2Twov4s = 843, + AArch64_LD2Twov4s_POST = 844, + AArch64_LD2Twov8b = 845, + AArch64_LD2Twov8b_POST = 846, + AArch64_LD2Twov8h = 847, + AArch64_LD2Twov8h_POST = 848, + AArch64_LD2i16 = 849, + AArch64_LD2i16_POST = 850, + AArch64_LD2i32 = 851, + AArch64_LD2i32_POST = 852, + AArch64_LD2i64 = 853, + AArch64_LD2i64_POST = 854, + AArch64_LD2i8 = 855, + AArch64_LD2i8_POST = 856, + AArch64_LD3Rv16b = 857, + AArch64_LD3Rv16b_POST = 858, + AArch64_LD3Rv1d = 859, + AArch64_LD3Rv1d_POST = 860, + AArch64_LD3Rv2d = 861, + AArch64_LD3Rv2d_POST = 862, + AArch64_LD3Rv2s = 863, + AArch64_LD3Rv2s_POST = 864, + AArch64_LD3Rv4h = 865, + AArch64_LD3Rv4h_POST = 866, + AArch64_LD3Rv4s = 867, + AArch64_LD3Rv4s_POST = 868, + AArch64_LD3Rv8b = 869, + AArch64_LD3Rv8b_POST = 870, + AArch64_LD3Rv8h = 871, + AArch64_LD3Rv8h_POST = 872, + AArch64_LD3Threev16b = 873, + AArch64_LD3Threev16b_POST = 874, + AArch64_LD3Threev2d = 875, + AArch64_LD3Threev2d_POST = 876, + AArch64_LD3Threev2s = 877, + AArch64_LD3Threev2s_POST = 878, + AArch64_LD3Threev4h = 879, + AArch64_LD3Threev4h_POST = 880, + AArch64_LD3Threev4s = 881, + AArch64_LD3Threev4s_POST = 882, + AArch64_LD3Threev8b = 883, + AArch64_LD3Threev8b_POST = 884, + AArch64_LD3Threev8h = 885, + AArch64_LD3Threev8h_POST = 886, + AArch64_LD3i16 = 887, + AArch64_LD3i16_POST = 888, + AArch64_LD3i32 = 889, + AArch64_LD3i32_POST = 890, + AArch64_LD3i64 = 891, + AArch64_LD3i64_POST = 892, + AArch64_LD3i8 = 893, + AArch64_LD3i8_POST = 894, + AArch64_LD4Fourv16b = 895, + AArch64_LD4Fourv16b_POST = 896, + AArch64_LD4Fourv2d = 897, + AArch64_LD4Fourv2d_POST = 898, + AArch64_LD4Fourv2s = 899, + AArch64_LD4Fourv2s_POST = 900, + AArch64_LD4Fourv4h = 901, + AArch64_LD4Fourv4h_POST = 902, + AArch64_LD4Fourv4s = 903, + AArch64_LD4Fourv4s_POST = 904, + AArch64_LD4Fourv8b = 905, + AArch64_LD4Fourv8b_POST = 906, + AArch64_LD4Fourv8h = 907, + AArch64_LD4Fourv8h_POST = 908, + AArch64_LD4Rv16b = 909, + AArch64_LD4Rv16b_POST = 910, + AArch64_LD4Rv1d = 911, + AArch64_LD4Rv1d_POST = 912, + AArch64_LD4Rv2d = 913, + AArch64_LD4Rv2d_POST = 914, + AArch64_LD4Rv2s = 915, + AArch64_LD4Rv2s_POST = 916, + AArch64_LD4Rv4h = 917, + AArch64_LD4Rv4h_POST = 918, + AArch64_LD4Rv4s = 919, + AArch64_LD4Rv4s_POST = 920, + AArch64_LD4Rv8b = 921, + AArch64_LD4Rv8b_POST = 922, + AArch64_LD4Rv8h = 923, + AArch64_LD4Rv8h_POST = 924, + AArch64_LD4i16 = 925, + AArch64_LD4i16_POST = 926, + AArch64_LD4i32 = 927, + AArch64_LD4i32_POST = 928, + AArch64_LD4i64 = 929, + AArch64_LD4i64_POST = 930, + AArch64_LD4i8 = 931, + AArch64_LD4i8_POST = 932, + AArch64_LDARB = 933, + AArch64_LDARH = 934, + AArch64_LDARW = 935, + AArch64_LDARX = 936, + AArch64_LDAXPW = 937, + AArch64_LDAXPX = 938, + AArch64_LDAXRB = 939, + AArch64_LDAXRH = 940, + AArch64_LDAXRW = 941, + AArch64_LDAXRX = 942, + AArch64_LDNPDi = 943, + AArch64_LDNPQi = 944, + AArch64_LDNPSi = 945, + AArch64_LDNPWi = 946, + AArch64_LDNPXi = 947, + AArch64_LDPDi = 948, + AArch64_LDPDpost = 949, + AArch64_LDPDpre = 950, + AArch64_LDPQi = 951, + AArch64_LDPQpost = 952, + AArch64_LDPQpre = 953, + AArch64_LDPSWi = 954, + AArch64_LDPSWpost = 955, + AArch64_LDPSWpre = 956, + AArch64_LDPSi = 957, + AArch64_LDPSpost = 958, + AArch64_LDPSpre = 959, + AArch64_LDPWi = 960, + AArch64_LDPWpost = 961, + AArch64_LDPWpre = 962, + AArch64_LDPXi = 963, + AArch64_LDPXpost = 964, + AArch64_LDPXpre = 965, + AArch64_LDRBBpost = 966, + AArch64_LDRBBpre = 967, + AArch64_LDRBBroW = 968, + AArch64_LDRBBroX = 969, + AArch64_LDRBBui = 970, + AArch64_LDRBpost = 971, + AArch64_LDRBpre = 972, + AArch64_LDRBroW = 973, + AArch64_LDRBroX = 974, + AArch64_LDRBui = 975, + AArch64_LDRDl = 976, + AArch64_LDRDpost = 977, + AArch64_LDRDpre = 978, + AArch64_LDRDroW = 979, + AArch64_LDRDroX = 980, + AArch64_LDRDui = 981, + AArch64_LDRHHpost = 982, + AArch64_LDRHHpre = 983, + AArch64_LDRHHroW = 984, + AArch64_LDRHHroX = 985, + AArch64_LDRHHui = 986, + AArch64_LDRHpost = 987, + AArch64_LDRHpre = 988, + AArch64_LDRHroW = 989, + AArch64_LDRHroX = 990, + AArch64_LDRHui = 991, + AArch64_LDRQl = 992, + AArch64_LDRQpost = 993, + AArch64_LDRQpre = 994, + AArch64_LDRQroW = 995, + AArch64_LDRQroX = 996, + AArch64_LDRQui = 997, + AArch64_LDRSBWpost = 998, + AArch64_LDRSBWpre = 999, + AArch64_LDRSBWroW = 1000, + AArch64_LDRSBWroX = 1001, + AArch64_LDRSBWui = 1002, + AArch64_LDRSBXpost = 1003, + AArch64_LDRSBXpre = 1004, + AArch64_LDRSBXroW = 1005, + AArch64_LDRSBXroX = 1006, + AArch64_LDRSBXui = 1007, + AArch64_LDRSHWpost = 1008, + AArch64_LDRSHWpre = 1009, + AArch64_LDRSHWroW = 1010, + AArch64_LDRSHWroX = 1011, + AArch64_LDRSHWui = 1012, + AArch64_LDRSHXpost = 1013, + AArch64_LDRSHXpre = 1014, + AArch64_LDRSHXroW = 1015, + AArch64_LDRSHXroX = 1016, + AArch64_LDRSHXui = 1017, + AArch64_LDRSWl = 1018, + AArch64_LDRSWpost = 1019, + AArch64_LDRSWpre = 1020, + AArch64_LDRSWroW = 1021, + AArch64_LDRSWroX = 1022, + AArch64_LDRSWui = 1023, + AArch64_LDRSl = 1024, + AArch64_LDRSpost = 1025, + AArch64_LDRSpre = 1026, + AArch64_LDRSroW = 1027, + AArch64_LDRSroX = 1028, + AArch64_LDRSui = 1029, + AArch64_LDRWl = 1030, + AArch64_LDRWpost = 1031, + AArch64_LDRWpre = 1032, + AArch64_LDRWroW = 1033, + AArch64_LDRWroX = 1034, + AArch64_LDRWui = 1035, + AArch64_LDRXl = 1036, + AArch64_LDRXpost = 1037, + AArch64_LDRXpre = 1038, + AArch64_LDRXroW = 1039, + AArch64_LDRXroX = 1040, + AArch64_LDRXui = 1041, + AArch64_LDTRBi = 1042, + AArch64_LDTRHi = 1043, + AArch64_LDTRSBWi = 1044, + AArch64_LDTRSBXi = 1045, + AArch64_LDTRSHWi = 1046, + AArch64_LDTRSHXi = 1047, + AArch64_LDTRSWi = 1048, + AArch64_LDTRWi = 1049, + AArch64_LDTRXi = 1050, + AArch64_LDURBBi = 1051, + AArch64_LDURBi = 1052, + AArch64_LDURDi = 1053, + AArch64_LDURHHi = 1054, + AArch64_LDURHi = 1055, + AArch64_LDURQi = 1056, + AArch64_LDURSBWi = 1057, + AArch64_LDURSBXi = 1058, + AArch64_LDURSHWi = 1059, + AArch64_LDURSHXi = 1060, + AArch64_LDURSWi = 1061, + AArch64_LDURSi = 1062, + AArch64_LDURWi = 1063, + AArch64_LDURXi = 1064, + AArch64_LDXPW = 1065, + AArch64_LDXPX = 1066, + AArch64_LDXRB = 1067, + AArch64_LDXRH = 1068, + AArch64_LDXRW = 1069, + AArch64_LDXRX = 1070, + AArch64_LOADgot = 1071, + AArch64_LSLVWr = 1072, + AArch64_LSLVXr = 1073, + AArch64_LSRVWr = 1074, + AArch64_LSRVXr = 1075, + AArch64_MADDWrrr = 1076, + AArch64_MADDXrrr = 1077, + AArch64_MLAv16i8 = 1078, + AArch64_MLAv2i32 = 1079, + AArch64_MLAv2i32_indexed = 1080, + AArch64_MLAv4i16 = 1081, + AArch64_MLAv4i16_indexed = 1082, + AArch64_MLAv4i32 = 1083, + AArch64_MLAv4i32_indexed = 1084, + AArch64_MLAv8i16 = 1085, + AArch64_MLAv8i16_indexed = 1086, + AArch64_MLAv8i8 = 1087, + AArch64_MLSv16i8 = 1088, + AArch64_MLSv2i32 = 1089, + AArch64_MLSv2i32_indexed = 1090, + AArch64_MLSv4i16 = 1091, + AArch64_MLSv4i16_indexed = 1092, + AArch64_MLSv4i32 = 1093, + AArch64_MLSv4i32_indexed = 1094, + AArch64_MLSv8i16 = 1095, + AArch64_MLSv8i16_indexed = 1096, + AArch64_MLSv8i8 = 1097, + AArch64_MOVID = 1098, + AArch64_MOVIv16b_ns = 1099, + AArch64_MOVIv2d_ns = 1100, + AArch64_MOVIv2i32 = 1101, + AArch64_MOVIv2s_msl = 1102, + AArch64_MOVIv4i16 = 1103, + AArch64_MOVIv4i32 = 1104, + AArch64_MOVIv4s_msl = 1105, + AArch64_MOVIv8b_ns = 1106, + AArch64_MOVIv8i16 = 1107, + AArch64_MOVKWi = 1108, + AArch64_MOVKXi = 1109, + AArch64_MOVNWi = 1110, + AArch64_MOVNXi = 1111, + AArch64_MOVZWi = 1112, + AArch64_MOVZXi = 1113, + AArch64_MOVaddr = 1114, + AArch64_MOVaddrBA = 1115, + AArch64_MOVaddrCP = 1116, + AArch64_MOVaddrEXT = 1117, + AArch64_MOVaddrJT = 1118, + AArch64_MOVaddrTLS = 1119, + AArch64_MOVi32imm = 1120, + AArch64_MOVi64imm = 1121, + AArch64_MRS = 1122, + AArch64_MSR = 1123, + AArch64_MSRpstate = 1124, + AArch64_MSUBWrrr = 1125, + AArch64_MSUBXrrr = 1126, + AArch64_MULv16i8 = 1127, + AArch64_MULv2i32 = 1128, + AArch64_MULv2i32_indexed = 1129, + AArch64_MULv4i16 = 1130, + AArch64_MULv4i16_indexed = 1131, + AArch64_MULv4i32 = 1132, + AArch64_MULv4i32_indexed = 1133, + AArch64_MULv8i16 = 1134, + AArch64_MULv8i16_indexed = 1135, + AArch64_MULv8i8 = 1136, + AArch64_MVNIv2i32 = 1137, + AArch64_MVNIv2s_msl = 1138, + AArch64_MVNIv4i16 = 1139, + AArch64_MVNIv4i32 = 1140, + AArch64_MVNIv4s_msl = 1141, + AArch64_MVNIv8i16 = 1142, + AArch64_NEGv16i8 = 1143, + AArch64_NEGv1i64 = 1144, + AArch64_NEGv2i32 = 1145, + AArch64_NEGv2i64 = 1146, + AArch64_NEGv4i16 = 1147, + AArch64_NEGv4i32 = 1148, + AArch64_NEGv8i16 = 1149, + AArch64_NEGv8i8 = 1150, + AArch64_NOTv16i8 = 1151, + AArch64_NOTv8i8 = 1152, + AArch64_ORNWrr = 1153, + AArch64_ORNWrs = 1154, + AArch64_ORNXrr = 1155, + AArch64_ORNXrs = 1156, + AArch64_ORNv16i8 = 1157, + AArch64_ORNv8i8 = 1158, + AArch64_ORRWri = 1159, + AArch64_ORRWrr = 1160, + AArch64_ORRWrs = 1161, + AArch64_ORRXri = 1162, + AArch64_ORRXrr = 1163, + AArch64_ORRXrs = 1164, + AArch64_ORRv16i8 = 1165, + AArch64_ORRv2i32 = 1166, + AArch64_ORRv4i16 = 1167, + AArch64_ORRv4i32 = 1168, + AArch64_ORRv8i16 = 1169, + AArch64_ORRv8i8 = 1170, + AArch64_PMULLv16i8 = 1171, + AArch64_PMULLv1i64 = 1172, + AArch64_PMULLv2i64 = 1173, + AArch64_PMULLv8i8 = 1174, + AArch64_PMULv16i8 = 1175, + AArch64_PMULv8i8 = 1176, + AArch64_PRFMl = 1177, + AArch64_PRFMroW = 1178, + AArch64_PRFMroX = 1179, + AArch64_PRFMui = 1180, + AArch64_PRFUMi = 1181, + AArch64_RADDHNv2i64_v2i32 = 1182, + AArch64_RADDHNv2i64_v4i32 = 1183, + AArch64_RADDHNv4i32_v4i16 = 1184, + AArch64_RADDHNv4i32_v8i16 = 1185, + AArch64_RADDHNv8i16_v16i8 = 1186, + AArch64_RADDHNv8i16_v8i8 = 1187, + AArch64_RBITWr = 1188, + AArch64_RBITXr = 1189, + AArch64_RBITv16i8 = 1190, + AArch64_RBITv8i8 = 1191, + AArch64_RET = 1192, + AArch64_RET_ReallyLR = 1193, + AArch64_REV16Wr = 1194, + AArch64_REV16Xr = 1195, + AArch64_REV16v16i8 = 1196, + AArch64_REV16v8i8 = 1197, + AArch64_REV32Xr = 1198, + AArch64_REV32v16i8 = 1199, + AArch64_REV32v4i16 = 1200, + AArch64_REV32v8i16 = 1201, + AArch64_REV32v8i8 = 1202, + AArch64_REV64v16i8 = 1203, + AArch64_REV64v2i32 = 1204, + AArch64_REV64v4i16 = 1205, + AArch64_REV64v4i32 = 1206, + AArch64_REV64v8i16 = 1207, + AArch64_REV64v8i8 = 1208, + AArch64_REVWr = 1209, + AArch64_REVXr = 1210, + AArch64_RORVWr = 1211, + AArch64_RORVXr = 1212, + AArch64_RSHRNv16i8_shift = 1213, + AArch64_RSHRNv2i32_shift = 1214, + AArch64_RSHRNv4i16_shift = 1215, + AArch64_RSHRNv4i32_shift = 1216, + AArch64_RSHRNv8i16_shift = 1217, + AArch64_RSHRNv8i8_shift = 1218, + AArch64_RSUBHNv2i64_v2i32 = 1219, + AArch64_RSUBHNv2i64_v4i32 = 1220, + AArch64_RSUBHNv4i32_v4i16 = 1221, + AArch64_RSUBHNv4i32_v8i16 = 1222, + AArch64_RSUBHNv8i16_v16i8 = 1223, + AArch64_RSUBHNv8i16_v8i8 = 1224, + AArch64_SABALv16i8_v8i16 = 1225, + AArch64_SABALv2i32_v2i64 = 1226, + AArch64_SABALv4i16_v4i32 = 1227, + AArch64_SABALv4i32_v2i64 = 1228, + AArch64_SABALv8i16_v4i32 = 1229, + AArch64_SABALv8i8_v8i16 = 1230, + AArch64_SABAv16i8 = 1231, + AArch64_SABAv2i32 = 1232, + AArch64_SABAv4i16 = 1233, + AArch64_SABAv4i32 = 1234, + AArch64_SABAv8i16 = 1235, + AArch64_SABAv8i8 = 1236, + AArch64_SABDLv16i8_v8i16 = 1237, + AArch64_SABDLv2i32_v2i64 = 1238, + AArch64_SABDLv4i16_v4i32 = 1239, + AArch64_SABDLv4i32_v2i64 = 1240, + AArch64_SABDLv8i16_v4i32 = 1241, + AArch64_SABDLv8i8_v8i16 = 1242, + AArch64_SABDv16i8 = 1243, + AArch64_SABDv2i32 = 1244, + AArch64_SABDv4i16 = 1245, + AArch64_SABDv4i32 = 1246, + AArch64_SABDv8i16 = 1247, + AArch64_SABDv8i8 = 1248, + AArch64_SADALPv16i8_v8i16 = 1249, + AArch64_SADALPv2i32_v1i64 = 1250, + AArch64_SADALPv4i16_v2i32 = 1251, + AArch64_SADALPv4i32_v2i64 = 1252, + AArch64_SADALPv8i16_v4i32 = 1253, + AArch64_SADALPv8i8_v4i16 = 1254, + AArch64_SADDLPv16i8_v8i16 = 1255, + AArch64_SADDLPv2i32_v1i64 = 1256, + AArch64_SADDLPv4i16_v2i32 = 1257, + AArch64_SADDLPv4i32_v2i64 = 1258, + AArch64_SADDLPv8i16_v4i32 = 1259, + AArch64_SADDLPv8i8_v4i16 = 1260, + AArch64_SADDLVv16i8v = 1261, + AArch64_SADDLVv4i16v = 1262, + AArch64_SADDLVv4i32v = 1263, + AArch64_SADDLVv8i16v = 1264, + AArch64_SADDLVv8i8v = 1265, + AArch64_SADDLv16i8_v8i16 = 1266, + AArch64_SADDLv2i32_v2i64 = 1267, + AArch64_SADDLv4i16_v4i32 = 1268, + AArch64_SADDLv4i32_v2i64 = 1269, + AArch64_SADDLv8i16_v4i32 = 1270, + AArch64_SADDLv8i8_v8i16 = 1271, + AArch64_SADDWv16i8_v8i16 = 1272, + AArch64_SADDWv2i32_v2i64 = 1273, + AArch64_SADDWv4i16_v4i32 = 1274, + AArch64_SADDWv4i32_v2i64 = 1275, + AArch64_SADDWv8i16_v4i32 = 1276, + AArch64_SADDWv8i8_v8i16 = 1277, + AArch64_SBCSWr = 1278, + AArch64_SBCSXr = 1279, + AArch64_SBCWr = 1280, + AArch64_SBCXr = 1281, + AArch64_SBFMWri = 1282, + AArch64_SBFMXri = 1283, + AArch64_SCVTFSWDri = 1284, + AArch64_SCVTFSWSri = 1285, + AArch64_SCVTFSXDri = 1286, + AArch64_SCVTFSXSri = 1287, + AArch64_SCVTFUWDri = 1288, + AArch64_SCVTFUWSri = 1289, + AArch64_SCVTFUXDri = 1290, + AArch64_SCVTFUXSri = 1291, + AArch64_SCVTFd = 1292, + AArch64_SCVTFs = 1293, + AArch64_SCVTFv1i32 = 1294, + AArch64_SCVTFv1i64 = 1295, + AArch64_SCVTFv2f32 = 1296, + AArch64_SCVTFv2f64 = 1297, + AArch64_SCVTFv2i32_shift = 1298, + AArch64_SCVTFv2i64_shift = 1299, + AArch64_SCVTFv4f32 = 1300, + AArch64_SCVTFv4i32_shift = 1301, + AArch64_SDIVWr = 1302, + AArch64_SDIVXr = 1303, + AArch64_SDIV_IntWr = 1304, + AArch64_SDIV_IntXr = 1305, + AArch64_SHA1Crrr = 1306, + AArch64_SHA1Hrr = 1307, + AArch64_SHA1Mrrr = 1308, + AArch64_SHA1Prrr = 1309, + AArch64_SHA1SU0rrr = 1310, + AArch64_SHA1SU1rr = 1311, + AArch64_SHA256H2rrr = 1312, + AArch64_SHA256Hrrr = 1313, + AArch64_SHA256SU0rr = 1314, + AArch64_SHA256SU1rrr = 1315, + AArch64_SHADDv16i8 = 1316, + AArch64_SHADDv2i32 = 1317, + AArch64_SHADDv4i16 = 1318, + AArch64_SHADDv4i32 = 1319, + AArch64_SHADDv8i16 = 1320, + AArch64_SHADDv8i8 = 1321, + AArch64_SHLLv16i8 = 1322, + AArch64_SHLLv2i32 = 1323, + AArch64_SHLLv4i16 = 1324, + AArch64_SHLLv4i32 = 1325, + AArch64_SHLLv8i16 = 1326, + AArch64_SHLLv8i8 = 1327, + AArch64_SHLd = 1328, + AArch64_SHLv16i8_shift = 1329, + AArch64_SHLv2i32_shift = 1330, + AArch64_SHLv2i64_shift = 1331, + AArch64_SHLv4i16_shift = 1332, + AArch64_SHLv4i32_shift = 1333, + AArch64_SHLv8i16_shift = 1334, + AArch64_SHLv8i8_shift = 1335, + AArch64_SHRNv16i8_shift = 1336, + AArch64_SHRNv2i32_shift = 1337, + AArch64_SHRNv4i16_shift = 1338, + AArch64_SHRNv4i32_shift = 1339, + AArch64_SHRNv8i16_shift = 1340, + AArch64_SHRNv8i8_shift = 1341, + AArch64_SHSUBv16i8 = 1342, + AArch64_SHSUBv2i32 = 1343, + AArch64_SHSUBv4i16 = 1344, + AArch64_SHSUBv4i32 = 1345, + AArch64_SHSUBv8i16 = 1346, + AArch64_SHSUBv8i8 = 1347, + AArch64_SLId = 1348, + AArch64_SLIv16i8_shift = 1349, + AArch64_SLIv2i32_shift = 1350, + AArch64_SLIv2i64_shift = 1351, + AArch64_SLIv4i16_shift = 1352, + AArch64_SLIv4i32_shift = 1353, + AArch64_SLIv8i16_shift = 1354, + AArch64_SLIv8i8_shift = 1355, + AArch64_SMADDLrrr = 1356, + AArch64_SMAXPv16i8 = 1357, + AArch64_SMAXPv2i32 = 1358, + AArch64_SMAXPv4i16 = 1359, + AArch64_SMAXPv4i32 = 1360, + AArch64_SMAXPv8i16 = 1361, + AArch64_SMAXPv8i8 = 1362, + AArch64_SMAXVv16i8v = 1363, + AArch64_SMAXVv4i16v = 1364, + AArch64_SMAXVv4i32v = 1365, + AArch64_SMAXVv8i16v = 1366, + AArch64_SMAXVv8i8v = 1367, + AArch64_SMAXv16i8 = 1368, + AArch64_SMAXv2i32 = 1369, + AArch64_SMAXv4i16 = 1370, + AArch64_SMAXv4i32 = 1371, + AArch64_SMAXv8i16 = 1372, + AArch64_SMAXv8i8 = 1373, + AArch64_SMC = 1374, + AArch64_SMINPv16i8 = 1375, + AArch64_SMINPv2i32 = 1376, + AArch64_SMINPv4i16 = 1377, + AArch64_SMINPv4i32 = 1378, + AArch64_SMINPv8i16 = 1379, + AArch64_SMINPv8i8 = 1380, + AArch64_SMINVv16i8v = 1381, + AArch64_SMINVv4i16v = 1382, + AArch64_SMINVv4i32v = 1383, + AArch64_SMINVv8i16v = 1384, + AArch64_SMINVv8i8v = 1385, + AArch64_SMINv16i8 = 1386, + AArch64_SMINv2i32 = 1387, + AArch64_SMINv4i16 = 1388, + AArch64_SMINv4i32 = 1389, + AArch64_SMINv8i16 = 1390, + AArch64_SMINv8i8 = 1391, + AArch64_SMLALv16i8_v8i16 = 1392, + AArch64_SMLALv2i32_indexed = 1393, + AArch64_SMLALv2i32_v2i64 = 1394, + AArch64_SMLALv4i16_indexed = 1395, + AArch64_SMLALv4i16_v4i32 = 1396, + AArch64_SMLALv4i32_indexed = 1397, + AArch64_SMLALv4i32_v2i64 = 1398, + AArch64_SMLALv8i16_indexed = 1399, + AArch64_SMLALv8i16_v4i32 = 1400, + AArch64_SMLALv8i8_v8i16 = 1401, + AArch64_SMLSLv16i8_v8i16 = 1402, + AArch64_SMLSLv2i32_indexed = 1403, + AArch64_SMLSLv2i32_v2i64 = 1404, + AArch64_SMLSLv4i16_indexed = 1405, + AArch64_SMLSLv4i16_v4i32 = 1406, + AArch64_SMLSLv4i32_indexed = 1407, + AArch64_SMLSLv4i32_v2i64 = 1408, + AArch64_SMLSLv8i16_indexed = 1409, + AArch64_SMLSLv8i16_v4i32 = 1410, + AArch64_SMLSLv8i8_v8i16 = 1411, + AArch64_SMOVvi16to32 = 1412, + AArch64_SMOVvi16to64 = 1413, + AArch64_SMOVvi32to64 = 1414, + AArch64_SMOVvi8to32 = 1415, + AArch64_SMOVvi8to64 = 1416, + AArch64_SMSUBLrrr = 1417, + AArch64_SMULHrr = 1418, + AArch64_SMULLv16i8_v8i16 = 1419, + AArch64_SMULLv2i32_indexed = 1420, + AArch64_SMULLv2i32_v2i64 = 1421, + AArch64_SMULLv4i16_indexed = 1422, + AArch64_SMULLv4i16_v4i32 = 1423, + AArch64_SMULLv4i32_indexed = 1424, + AArch64_SMULLv4i32_v2i64 = 1425, + AArch64_SMULLv8i16_indexed = 1426, + AArch64_SMULLv8i16_v4i32 = 1427, + AArch64_SMULLv8i8_v8i16 = 1428, + AArch64_SQABSv16i8 = 1429, + AArch64_SQABSv1i16 = 1430, + AArch64_SQABSv1i32 = 1431, + AArch64_SQABSv1i64 = 1432, + AArch64_SQABSv1i8 = 1433, + AArch64_SQABSv2i32 = 1434, + AArch64_SQABSv2i64 = 1435, + AArch64_SQABSv4i16 = 1436, + AArch64_SQABSv4i32 = 1437, + AArch64_SQABSv8i16 = 1438, + AArch64_SQABSv8i8 = 1439, + AArch64_SQADDv16i8 = 1440, + AArch64_SQADDv1i16 = 1441, + AArch64_SQADDv1i32 = 1442, + AArch64_SQADDv1i64 = 1443, + AArch64_SQADDv1i8 = 1444, + AArch64_SQADDv2i32 = 1445, + AArch64_SQADDv2i64 = 1446, + AArch64_SQADDv4i16 = 1447, + AArch64_SQADDv4i32 = 1448, + AArch64_SQADDv8i16 = 1449, + AArch64_SQADDv8i8 = 1450, + AArch64_SQDMLALi16 = 1451, + AArch64_SQDMLALi32 = 1452, + AArch64_SQDMLALv1i32_indexed = 1453, + AArch64_SQDMLALv1i64_indexed = 1454, + AArch64_SQDMLALv2i32_indexed = 1455, + AArch64_SQDMLALv2i32_v2i64 = 1456, + AArch64_SQDMLALv4i16_indexed = 1457, + AArch64_SQDMLALv4i16_v4i32 = 1458, + AArch64_SQDMLALv4i32_indexed = 1459, + AArch64_SQDMLALv4i32_v2i64 = 1460, + AArch64_SQDMLALv8i16_indexed = 1461, + AArch64_SQDMLALv8i16_v4i32 = 1462, + AArch64_SQDMLSLi16 = 1463, + AArch64_SQDMLSLi32 = 1464, + AArch64_SQDMLSLv1i32_indexed = 1465, + AArch64_SQDMLSLv1i64_indexed = 1466, + AArch64_SQDMLSLv2i32_indexed = 1467, + AArch64_SQDMLSLv2i32_v2i64 = 1468, + AArch64_SQDMLSLv4i16_indexed = 1469, + AArch64_SQDMLSLv4i16_v4i32 = 1470, + AArch64_SQDMLSLv4i32_indexed = 1471, + AArch64_SQDMLSLv4i32_v2i64 = 1472, + AArch64_SQDMLSLv8i16_indexed = 1473, + AArch64_SQDMLSLv8i16_v4i32 = 1474, + AArch64_SQDMULHv1i16 = 1475, + AArch64_SQDMULHv1i16_indexed = 1476, + AArch64_SQDMULHv1i32 = 1477, + AArch64_SQDMULHv1i32_indexed = 1478, + AArch64_SQDMULHv2i32 = 1479, + AArch64_SQDMULHv2i32_indexed = 1480, + AArch64_SQDMULHv4i16 = 1481, + AArch64_SQDMULHv4i16_indexed = 1482, + AArch64_SQDMULHv4i32 = 1483, + AArch64_SQDMULHv4i32_indexed = 1484, + AArch64_SQDMULHv8i16 = 1485, + AArch64_SQDMULHv8i16_indexed = 1486, + AArch64_SQDMULLi16 = 1487, + AArch64_SQDMULLi32 = 1488, + AArch64_SQDMULLv1i32_indexed = 1489, + AArch64_SQDMULLv1i64_indexed = 1490, + AArch64_SQDMULLv2i32_indexed = 1491, + AArch64_SQDMULLv2i32_v2i64 = 1492, + AArch64_SQDMULLv4i16_indexed = 1493, + AArch64_SQDMULLv4i16_v4i32 = 1494, + AArch64_SQDMULLv4i32_indexed = 1495, + AArch64_SQDMULLv4i32_v2i64 = 1496, + AArch64_SQDMULLv8i16_indexed = 1497, + AArch64_SQDMULLv8i16_v4i32 = 1498, + AArch64_SQNEGv16i8 = 1499, + AArch64_SQNEGv1i16 = 1500, + AArch64_SQNEGv1i32 = 1501, + AArch64_SQNEGv1i64 = 1502, + AArch64_SQNEGv1i8 = 1503, + AArch64_SQNEGv2i32 = 1504, + AArch64_SQNEGv2i64 = 1505, + AArch64_SQNEGv4i16 = 1506, + AArch64_SQNEGv4i32 = 1507, + AArch64_SQNEGv8i16 = 1508, + AArch64_SQNEGv8i8 = 1509, + AArch64_SQRDMULHv1i16 = 1510, + AArch64_SQRDMULHv1i16_indexed = 1511, + AArch64_SQRDMULHv1i32 = 1512, + AArch64_SQRDMULHv1i32_indexed = 1513, + AArch64_SQRDMULHv2i32 = 1514, + AArch64_SQRDMULHv2i32_indexed = 1515, + AArch64_SQRDMULHv4i16 = 1516, + AArch64_SQRDMULHv4i16_indexed = 1517, + AArch64_SQRDMULHv4i32 = 1518, + AArch64_SQRDMULHv4i32_indexed = 1519, + AArch64_SQRDMULHv8i16 = 1520, + AArch64_SQRDMULHv8i16_indexed = 1521, + AArch64_SQRSHLv16i8 = 1522, + AArch64_SQRSHLv1i16 = 1523, + AArch64_SQRSHLv1i32 = 1524, + AArch64_SQRSHLv1i64 = 1525, + AArch64_SQRSHLv1i8 = 1526, + AArch64_SQRSHLv2i32 = 1527, + AArch64_SQRSHLv2i64 = 1528, + AArch64_SQRSHLv4i16 = 1529, + AArch64_SQRSHLv4i32 = 1530, + AArch64_SQRSHLv8i16 = 1531, + AArch64_SQRSHLv8i8 = 1532, + AArch64_SQRSHRNb = 1533, + AArch64_SQRSHRNh = 1534, + AArch64_SQRSHRNs = 1535, + AArch64_SQRSHRNv16i8_shift = 1536, + AArch64_SQRSHRNv2i32_shift = 1537, + AArch64_SQRSHRNv4i16_shift = 1538, + AArch64_SQRSHRNv4i32_shift = 1539, + AArch64_SQRSHRNv8i16_shift = 1540, + AArch64_SQRSHRNv8i8_shift = 1541, + AArch64_SQRSHRUNb = 1542, + AArch64_SQRSHRUNh = 1543, + AArch64_SQRSHRUNs = 1544, + AArch64_SQRSHRUNv16i8_shift = 1545, + AArch64_SQRSHRUNv2i32_shift = 1546, + AArch64_SQRSHRUNv4i16_shift = 1547, + AArch64_SQRSHRUNv4i32_shift = 1548, + AArch64_SQRSHRUNv8i16_shift = 1549, + AArch64_SQRSHRUNv8i8_shift = 1550, + AArch64_SQSHLUb = 1551, + AArch64_SQSHLUd = 1552, + AArch64_SQSHLUh = 1553, + AArch64_SQSHLUs = 1554, + AArch64_SQSHLUv16i8_shift = 1555, + AArch64_SQSHLUv2i32_shift = 1556, + AArch64_SQSHLUv2i64_shift = 1557, + AArch64_SQSHLUv4i16_shift = 1558, + AArch64_SQSHLUv4i32_shift = 1559, + AArch64_SQSHLUv8i16_shift = 1560, + AArch64_SQSHLUv8i8_shift = 1561, + AArch64_SQSHLb = 1562, + AArch64_SQSHLd = 1563, + AArch64_SQSHLh = 1564, + AArch64_SQSHLs = 1565, + AArch64_SQSHLv16i8 = 1566, + AArch64_SQSHLv16i8_shift = 1567, + AArch64_SQSHLv1i16 = 1568, + AArch64_SQSHLv1i32 = 1569, + AArch64_SQSHLv1i64 = 1570, + AArch64_SQSHLv1i8 = 1571, + AArch64_SQSHLv2i32 = 1572, + AArch64_SQSHLv2i32_shift = 1573, + AArch64_SQSHLv2i64 = 1574, + AArch64_SQSHLv2i64_shift = 1575, + AArch64_SQSHLv4i16 = 1576, + AArch64_SQSHLv4i16_shift = 1577, + AArch64_SQSHLv4i32 = 1578, + AArch64_SQSHLv4i32_shift = 1579, + AArch64_SQSHLv8i16 = 1580, + AArch64_SQSHLv8i16_shift = 1581, + AArch64_SQSHLv8i8 = 1582, + AArch64_SQSHLv8i8_shift = 1583, + AArch64_SQSHRNb = 1584, + AArch64_SQSHRNh = 1585, + AArch64_SQSHRNs = 1586, + AArch64_SQSHRNv16i8_shift = 1587, + AArch64_SQSHRNv2i32_shift = 1588, + AArch64_SQSHRNv4i16_shift = 1589, + AArch64_SQSHRNv4i32_shift = 1590, + AArch64_SQSHRNv8i16_shift = 1591, + AArch64_SQSHRNv8i8_shift = 1592, + AArch64_SQSHRUNb = 1593, + AArch64_SQSHRUNh = 1594, + AArch64_SQSHRUNs = 1595, + AArch64_SQSHRUNv16i8_shift = 1596, + AArch64_SQSHRUNv2i32_shift = 1597, + AArch64_SQSHRUNv4i16_shift = 1598, + AArch64_SQSHRUNv4i32_shift = 1599, + AArch64_SQSHRUNv8i16_shift = 1600, + AArch64_SQSHRUNv8i8_shift = 1601, + AArch64_SQSUBv16i8 = 1602, + AArch64_SQSUBv1i16 = 1603, + AArch64_SQSUBv1i32 = 1604, + AArch64_SQSUBv1i64 = 1605, + AArch64_SQSUBv1i8 = 1606, + AArch64_SQSUBv2i32 = 1607, + AArch64_SQSUBv2i64 = 1608, + AArch64_SQSUBv4i16 = 1609, + AArch64_SQSUBv4i32 = 1610, + AArch64_SQSUBv8i16 = 1611, + AArch64_SQSUBv8i8 = 1612, + AArch64_SQXTNv16i8 = 1613, + AArch64_SQXTNv1i16 = 1614, + AArch64_SQXTNv1i32 = 1615, + AArch64_SQXTNv1i8 = 1616, + AArch64_SQXTNv2i32 = 1617, + AArch64_SQXTNv4i16 = 1618, + AArch64_SQXTNv4i32 = 1619, + AArch64_SQXTNv8i16 = 1620, + AArch64_SQXTNv8i8 = 1621, + AArch64_SQXTUNv16i8 = 1622, + AArch64_SQXTUNv1i16 = 1623, + AArch64_SQXTUNv1i32 = 1624, + AArch64_SQXTUNv1i8 = 1625, + AArch64_SQXTUNv2i32 = 1626, + AArch64_SQXTUNv4i16 = 1627, + AArch64_SQXTUNv4i32 = 1628, + AArch64_SQXTUNv8i16 = 1629, + AArch64_SQXTUNv8i8 = 1630, + AArch64_SRHADDv16i8 = 1631, + AArch64_SRHADDv2i32 = 1632, + AArch64_SRHADDv4i16 = 1633, + AArch64_SRHADDv4i32 = 1634, + AArch64_SRHADDv8i16 = 1635, + AArch64_SRHADDv8i8 = 1636, + AArch64_SRId = 1637, + AArch64_SRIv16i8_shift = 1638, + AArch64_SRIv2i32_shift = 1639, + AArch64_SRIv2i64_shift = 1640, + AArch64_SRIv4i16_shift = 1641, + AArch64_SRIv4i32_shift = 1642, + AArch64_SRIv8i16_shift = 1643, + AArch64_SRIv8i8_shift = 1644, + AArch64_SRSHLv16i8 = 1645, + AArch64_SRSHLv1i64 = 1646, + AArch64_SRSHLv2i32 = 1647, + AArch64_SRSHLv2i64 = 1648, + AArch64_SRSHLv4i16 = 1649, + AArch64_SRSHLv4i32 = 1650, + AArch64_SRSHLv8i16 = 1651, + AArch64_SRSHLv8i8 = 1652, + AArch64_SRSHRd = 1653, + AArch64_SRSHRv16i8_shift = 1654, + AArch64_SRSHRv2i32_shift = 1655, + AArch64_SRSHRv2i64_shift = 1656, + AArch64_SRSHRv4i16_shift = 1657, + AArch64_SRSHRv4i32_shift = 1658, + AArch64_SRSHRv8i16_shift = 1659, + AArch64_SRSHRv8i8_shift = 1660, + AArch64_SRSRAd = 1661, + AArch64_SRSRAv16i8_shift = 1662, + AArch64_SRSRAv2i32_shift = 1663, + AArch64_SRSRAv2i64_shift = 1664, + AArch64_SRSRAv4i16_shift = 1665, + AArch64_SRSRAv4i32_shift = 1666, + AArch64_SRSRAv8i16_shift = 1667, + AArch64_SRSRAv8i8_shift = 1668, + AArch64_SSHLLv16i8_shift = 1669, + AArch64_SSHLLv2i32_shift = 1670, + AArch64_SSHLLv4i16_shift = 1671, + AArch64_SSHLLv4i32_shift = 1672, + AArch64_SSHLLv8i16_shift = 1673, + AArch64_SSHLLv8i8_shift = 1674, + AArch64_SSHLv16i8 = 1675, + AArch64_SSHLv1i64 = 1676, + AArch64_SSHLv2i32 = 1677, + AArch64_SSHLv2i64 = 1678, + AArch64_SSHLv4i16 = 1679, + AArch64_SSHLv4i32 = 1680, + AArch64_SSHLv8i16 = 1681, + AArch64_SSHLv8i8 = 1682, + AArch64_SSHRd = 1683, + AArch64_SSHRv16i8_shift = 1684, + AArch64_SSHRv2i32_shift = 1685, + AArch64_SSHRv2i64_shift = 1686, + AArch64_SSHRv4i16_shift = 1687, + AArch64_SSHRv4i32_shift = 1688, + AArch64_SSHRv8i16_shift = 1689, + AArch64_SSHRv8i8_shift = 1690, + AArch64_SSRAd = 1691, + AArch64_SSRAv16i8_shift = 1692, + AArch64_SSRAv2i32_shift = 1693, + AArch64_SSRAv2i64_shift = 1694, + AArch64_SSRAv4i16_shift = 1695, + AArch64_SSRAv4i32_shift = 1696, + AArch64_SSRAv8i16_shift = 1697, + AArch64_SSRAv8i8_shift = 1698, + AArch64_SSUBLv16i8_v8i16 = 1699, + AArch64_SSUBLv2i32_v2i64 = 1700, + AArch64_SSUBLv4i16_v4i32 = 1701, + AArch64_SSUBLv4i32_v2i64 = 1702, + AArch64_SSUBLv8i16_v4i32 = 1703, + AArch64_SSUBLv8i8_v8i16 = 1704, + AArch64_SSUBWv16i8_v8i16 = 1705, + AArch64_SSUBWv2i32_v2i64 = 1706, + AArch64_SSUBWv4i16_v4i32 = 1707, + AArch64_SSUBWv4i32_v2i64 = 1708, + AArch64_SSUBWv8i16_v4i32 = 1709, + AArch64_SSUBWv8i8_v8i16 = 1710, + AArch64_ST1Fourv16b = 1711, + AArch64_ST1Fourv16b_POST = 1712, + AArch64_ST1Fourv1d = 1713, + AArch64_ST1Fourv1d_POST = 1714, + AArch64_ST1Fourv2d = 1715, + AArch64_ST1Fourv2d_POST = 1716, + AArch64_ST1Fourv2s = 1717, + AArch64_ST1Fourv2s_POST = 1718, + AArch64_ST1Fourv4h = 1719, + AArch64_ST1Fourv4h_POST = 1720, + AArch64_ST1Fourv4s = 1721, + AArch64_ST1Fourv4s_POST = 1722, + AArch64_ST1Fourv8b = 1723, + AArch64_ST1Fourv8b_POST = 1724, + AArch64_ST1Fourv8h = 1725, + AArch64_ST1Fourv8h_POST = 1726, + AArch64_ST1Onev16b = 1727, + AArch64_ST1Onev16b_POST = 1728, + AArch64_ST1Onev1d = 1729, + AArch64_ST1Onev1d_POST = 1730, + AArch64_ST1Onev2d = 1731, + AArch64_ST1Onev2d_POST = 1732, + AArch64_ST1Onev2s = 1733, + AArch64_ST1Onev2s_POST = 1734, + AArch64_ST1Onev4h = 1735, + AArch64_ST1Onev4h_POST = 1736, + AArch64_ST1Onev4s = 1737, + AArch64_ST1Onev4s_POST = 1738, + AArch64_ST1Onev8b = 1739, + AArch64_ST1Onev8b_POST = 1740, + AArch64_ST1Onev8h = 1741, + AArch64_ST1Onev8h_POST = 1742, + AArch64_ST1Threev16b = 1743, + AArch64_ST1Threev16b_POST = 1744, + AArch64_ST1Threev1d = 1745, + AArch64_ST1Threev1d_POST = 1746, + AArch64_ST1Threev2d = 1747, + AArch64_ST1Threev2d_POST = 1748, + AArch64_ST1Threev2s = 1749, + AArch64_ST1Threev2s_POST = 1750, + AArch64_ST1Threev4h = 1751, + AArch64_ST1Threev4h_POST = 1752, + AArch64_ST1Threev4s = 1753, + AArch64_ST1Threev4s_POST = 1754, + AArch64_ST1Threev8b = 1755, + AArch64_ST1Threev8b_POST = 1756, + AArch64_ST1Threev8h = 1757, + AArch64_ST1Threev8h_POST = 1758, + AArch64_ST1Twov16b = 1759, + AArch64_ST1Twov16b_POST = 1760, + AArch64_ST1Twov1d = 1761, + AArch64_ST1Twov1d_POST = 1762, + AArch64_ST1Twov2d = 1763, + AArch64_ST1Twov2d_POST = 1764, + AArch64_ST1Twov2s = 1765, + AArch64_ST1Twov2s_POST = 1766, + AArch64_ST1Twov4h = 1767, + AArch64_ST1Twov4h_POST = 1768, + AArch64_ST1Twov4s = 1769, + AArch64_ST1Twov4s_POST = 1770, + AArch64_ST1Twov8b = 1771, + AArch64_ST1Twov8b_POST = 1772, + AArch64_ST1Twov8h = 1773, + AArch64_ST1Twov8h_POST = 1774, + AArch64_ST1i16 = 1775, + AArch64_ST1i16_POST = 1776, + AArch64_ST1i32 = 1777, + AArch64_ST1i32_POST = 1778, + AArch64_ST1i64 = 1779, + AArch64_ST1i64_POST = 1780, + AArch64_ST1i8 = 1781, + AArch64_ST1i8_POST = 1782, + AArch64_ST2Twov16b = 1783, + AArch64_ST2Twov16b_POST = 1784, + AArch64_ST2Twov2d = 1785, + AArch64_ST2Twov2d_POST = 1786, + AArch64_ST2Twov2s = 1787, + AArch64_ST2Twov2s_POST = 1788, + AArch64_ST2Twov4h = 1789, + AArch64_ST2Twov4h_POST = 1790, + AArch64_ST2Twov4s = 1791, + AArch64_ST2Twov4s_POST = 1792, + AArch64_ST2Twov8b = 1793, + AArch64_ST2Twov8b_POST = 1794, + AArch64_ST2Twov8h = 1795, + AArch64_ST2Twov8h_POST = 1796, + AArch64_ST2i16 = 1797, + AArch64_ST2i16_POST = 1798, + AArch64_ST2i32 = 1799, + AArch64_ST2i32_POST = 1800, + AArch64_ST2i64 = 1801, + AArch64_ST2i64_POST = 1802, + AArch64_ST2i8 = 1803, + AArch64_ST2i8_POST = 1804, + AArch64_ST3Threev16b = 1805, + AArch64_ST3Threev16b_POST = 1806, + AArch64_ST3Threev2d = 1807, + AArch64_ST3Threev2d_POST = 1808, + AArch64_ST3Threev2s = 1809, + AArch64_ST3Threev2s_POST = 1810, + AArch64_ST3Threev4h = 1811, + AArch64_ST3Threev4h_POST = 1812, + AArch64_ST3Threev4s = 1813, + AArch64_ST3Threev4s_POST = 1814, + AArch64_ST3Threev8b = 1815, + AArch64_ST3Threev8b_POST = 1816, + AArch64_ST3Threev8h = 1817, + AArch64_ST3Threev8h_POST = 1818, + AArch64_ST3i16 = 1819, + AArch64_ST3i16_POST = 1820, + AArch64_ST3i32 = 1821, + AArch64_ST3i32_POST = 1822, + AArch64_ST3i64 = 1823, + AArch64_ST3i64_POST = 1824, + AArch64_ST3i8 = 1825, + AArch64_ST3i8_POST = 1826, + AArch64_ST4Fourv16b = 1827, + AArch64_ST4Fourv16b_POST = 1828, + AArch64_ST4Fourv2d = 1829, + AArch64_ST4Fourv2d_POST = 1830, + AArch64_ST4Fourv2s = 1831, + AArch64_ST4Fourv2s_POST = 1832, + AArch64_ST4Fourv4h = 1833, + AArch64_ST4Fourv4h_POST = 1834, + AArch64_ST4Fourv4s = 1835, + AArch64_ST4Fourv4s_POST = 1836, + AArch64_ST4Fourv8b = 1837, + AArch64_ST4Fourv8b_POST = 1838, + AArch64_ST4Fourv8h = 1839, + AArch64_ST4Fourv8h_POST = 1840, + AArch64_ST4i16 = 1841, + AArch64_ST4i16_POST = 1842, + AArch64_ST4i32 = 1843, + AArch64_ST4i32_POST = 1844, + AArch64_ST4i64 = 1845, + AArch64_ST4i64_POST = 1846, + AArch64_ST4i8 = 1847, + AArch64_ST4i8_POST = 1848, + AArch64_STLRB = 1849, + AArch64_STLRH = 1850, + AArch64_STLRW = 1851, + AArch64_STLRX = 1852, + AArch64_STLXPW = 1853, + AArch64_STLXPX = 1854, + AArch64_STLXRB = 1855, + AArch64_STLXRH = 1856, + AArch64_STLXRW = 1857, + AArch64_STLXRX = 1858, + AArch64_STNPDi = 1859, + AArch64_STNPQi = 1860, + AArch64_STNPSi = 1861, + AArch64_STNPWi = 1862, + AArch64_STNPXi = 1863, + AArch64_STPDi = 1864, + AArch64_STPDpost = 1865, + AArch64_STPDpre = 1866, + AArch64_STPQi = 1867, + AArch64_STPQpost = 1868, + AArch64_STPQpre = 1869, + AArch64_STPSi = 1870, + AArch64_STPSpost = 1871, + AArch64_STPSpre = 1872, + AArch64_STPWi = 1873, + AArch64_STPWpost = 1874, + AArch64_STPWpre = 1875, + AArch64_STPXi = 1876, + AArch64_STPXpost = 1877, + AArch64_STPXpre = 1878, + AArch64_STRBBpost = 1879, + AArch64_STRBBpre = 1880, + AArch64_STRBBroW = 1881, + AArch64_STRBBroX = 1882, + AArch64_STRBBui = 1883, + AArch64_STRBpost = 1884, + AArch64_STRBpre = 1885, + AArch64_STRBroW = 1886, + AArch64_STRBroX = 1887, + AArch64_STRBui = 1888, + AArch64_STRDpost = 1889, + AArch64_STRDpre = 1890, + AArch64_STRDroW = 1891, + AArch64_STRDroX = 1892, + AArch64_STRDui = 1893, + AArch64_STRHHpost = 1894, + AArch64_STRHHpre = 1895, + AArch64_STRHHroW = 1896, + AArch64_STRHHroX = 1897, + AArch64_STRHHui = 1898, + AArch64_STRHpost = 1899, + AArch64_STRHpre = 1900, + AArch64_STRHroW = 1901, + AArch64_STRHroX = 1902, + AArch64_STRHui = 1903, + AArch64_STRQpost = 1904, + AArch64_STRQpre = 1905, + AArch64_STRQroW = 1906, + AArch64_STRQroX = 1907, + AArch64_STRQui = 1908, + AArch64_STRSpost = 1909, + AArch64_STRSpre = 1910, + AArch64_STRSroW = 1911, + AArch64_STRSroX = 1912, + AArch64_STRSui = 1913, + AArch64_STRWpost = 1914, + AArch64_STRWpre = 1915, + AArch64_STRWroW = 1916, + AArch64_STRWroX = 1917, + AArch64_STRWui = 1918, + AArch64_STRXpost = 1919, + AArch64_STRXpre = 1920, + AArch64_STRXroW = 1921, + AArch64_STRXroX = 1922, + AArch64_STRXui = 1923, + AArch64_STTRBi = 1924, + AArch64_STTRHi = 1925, + AArch64_STTRWi = 1926, + AArch64_STTRXi = 1927, + AArch64_STURBBi = 1928, + AArch64_STURBi = 1929, + AArch64_STURDi = 1930, + AArch64_STURHHi = 1931, + AArch64_STURHi = 1932, + AArch64_STURQi = 1933, + AArch64_STURSi = 1934, + AArch64_STURWi = 1935, + AArch64_STURXi = 1936, + AArch64_STXPW = 1937, + AArch64_STXPX = 1938, + AArch64_STXRB = 1939, + AArch64_STXRH = 1940, + AArch64_STXRW = 1941, + AArch64_STXRX = 1942, + AArch64_SUBHNv2i64_v2i32 = 1943, + AArch64_SUBHNv2i64_v4i32 = 1944, + AArch64_SUBHNv4i32_v4i16 = 1945, + AArch64_SUBHNv4i32_v8i16 = 1946, + AArch64_SUBHNv8i16_v16i8 = 1947, + AArch64_SUBHNv8i16_v8i8 = 1948, + AArch64_SUBSWri = 1949, + AArch64_SUBSWrr = 1950, + AArch64_SUBSWrs = 1951, + AArch64_SUBSWrx = 1952, + AArch64_SUBSXri = 1953, + AArch64_SUBSXrr = 1954, + AArch64_SUBSXrs = 1955, + AArch64_SUBSXrx = 1956, + AArch64_SUBSXrx64 = 1957, + AArch64_SUBWri = 1958, + AArch64_SUBWrr = 1959, + AArch64_SUBWrs = 1960, + AArch64_SUBWrx = 1961, + AArch64_SUBXri = 1962, + AArch64_SUBXrr = 1963, + AArch64_SUBXrs = 1964, + AArch64_SUBXrx = 1965, + AArch64_SUBXrx64 = 1966, + AArch64_SUBv16i8 = 1967, + AArch64_SUBv1i64 = 1968, + AArch64_SUBv2i32 = 1969, + AArch64_SUBv2i64 = 1970, + AArch64_SUBv4i16 = 1971, + AArch64_SUBv4i32 = 1972, + AArch64_SUBv8i16 = 1973, + AArch64_SUBv8i8 = 1974, + AArch64_SUQADDv16i8 = 1975, + AArch64_SUQADDv1i16 = 1976, + AArch64_SUQADDv1i32 = 1977, + AArch64_SUQADDv1i64 = 1978, + AArch64_SUQADDv1i8 = 1979, + AArch64_SUQADDv2i32 = 1980, + AArch64_SUQADDv2i64 = 1981, + AArch64_SUQADDv4i16 = 1982, + AArch64_SUQADDv4i32 = 1983, + AArch64_SUQADDv8i16 = 1984, + AArch64_SUQADDv8i8 = 1985, + AArch64_SVC = 1986, + AArch64_SYSLxt = 1987, + AArch64_SYSxt = 1988, + AArch64_TBLv16i8Four = 1989, + AArch64_TBLv16i8One = 1990, + AArch64_TBLv16i8Three = 1991, + AArch64_TBLv16i8Two = 1992, + AArch64_TBLv8i8Four = 1993, + AArch64_TBLv8i8One = 1994, + AArch64_TBLv8i8Three = 1995, + AArch64_TBLv8i8Two = 1996, + AArch64_TBNZW = 1997, + AArch64_TBNZX = 1998, + AArch64_TBXv16i8Four = 1999, + AArch64_TBXv16i8One = 2000, + AArch64_TBXv16i8Three = 2001, + AArch64_TBXv16i8Two = 2002, + AArch64_TBXv8i8Four = 2003, + AArch64_TBXv8i8One = 2004, + AArch64_TBXv8i8Three = 2005, + AArch64_TBXv8i8Two = 2006, + AArch64_TBZW = 2007, + AArch64_TBZX = 2008, + AArch64_TCRETURNdi = 2009, + AArch64_TCRETURNri = 2010, + AArch64_TLSDESCCALL = 2011, + AArch64_TLSDESC_BLR = 2012, + AArch64_TRN1v16i8 = 2013, + AArch64_TRN1v2i32 = 2014, + AArch64_TRN1v2i64 = 2015, + AArch64_TRN1v4i16 = 2016, + AArch64_TRN1v4i32 = 2017, + AArch64_TRN1v8i16 = 2018, + AArch64_TRN1v8i8 = 2019, + AArch64_TRN2v16i8 = 2020, + AArch64_TRN2v2i32 = 2021, + AArch64_TRN2v2i64 = 2022, + AArch64_TRN2v4i16 = 2023, + AArch64_TRN2v4i32 = 2024, + AArch64_TRN2v8i16 = 2025, + AArch64_TRN2v8i8 = 2026, + AArch64_UABALv16i8_v8i16 = 2027, + AArch64_UABALv2i32_v2i64 = 2028, + AArch64_UABALv4i16_v4i32 = 2029, + AArch64_UABALv4i32_v2i64 = 2030, + AArch64_UABALv8i16_v4i32 = 2031, + AArch64_UABALv8i8_v8i16 = 2032, + AArch64_UABAv16i8 = 2033, + AArch64_UABAv2i32 = 2034, + AArch64_UABAv4i16 = 2035, + AArch64_UABAv4i32 = 2036, + AArch64_UABAv8i16 = 2037, + AArch64_UABAv8i8 = 2038, + AArch64_UABDLv16i8_v8i16 = 2039, + AArch64_UABDLv2i32_v2i64 = 2040, + AArch64_UABDLv4i16_v4i32 = 2041, + AArch64_UABDLv4i32_v2i64 = 2042, + AArch64_UABDLv8i16_v4i32 = 2043, + AArch64_UABDLv8i8_v8i16 = 2044, + AArch64_UABDv16i8 = 2045, + AArch64_UABDv2i32 = 2046, + AArch64_UABDv4i16 = 2047, + AArch64_UABDv4i32 = 2048, + AArch64_UABDv8i16 = 2049, + AArch64_UABDv8i8 = 2050, + AArch64_UADALPv16i8_v8i16 = 2051, + AArch64_UADALPv2i32_v1i64 = 2052, + AArch64_UADALPv4i16_v2i32 = 2053, + AArch64_UADALPv4i32_v2i64 = 2054, + AArch64_UADALPv8i16_v4i32 = 2055, + AArch64_UADALPv8i8_v4i16 = 2056, + AArch64_UADDLPv16i8_v8i16 = 2057, + AArch64_UADDLPv2i32_v1i64 = 2058, + AArch64_UADDLPv4i16_v2i32 = 2059, + AArch64_UADDLPv4i32_v2i64 = 2060, + AArch64_UADDLPv8i16_v4i32 = 2061, + AArch64_UADDLPv8i8_v4i16 = 2062, + AArch64_UADDLVv16i8v = 2063, + AArch64_UADDLVv4i16v = 2064, + AArch64_UADDLVv4i32v = 2065, + AArch64_UADDLVv8i16v = 2066, + AArch64_UADDLVv8i8v = 2067, + AArch64_UADDLv16i8_v8i16 = 2068, + AArch64_UADDLv2i32_v2i64 = 2069, + AArch64_UADDLv4i16_v4i32 = 2070, + AArch64_UADDLv4i32_v2i64 = 2071, + AArch64_UADDLv8i16_v4i32 = 2072, + AArch64_UADDLv8i8_v8i16 = 2073, + AArch64_UADDWv16i8_v8i16 = 2074, + AArch64_UADDWv2i32_v2i64 = 2075, + AArch64_UADDWv4i16_v4i32 = 2076, + AArch64_UADDWv4i32_v2i64 = 2077, + AArch64_UADDWv8i16_v4i32 = 2078, + AArch64_UADDWv8i8_v8i16 = 2079, + AArch64_UBFMWri = 2080, + AArch64_UBFMXri = 2081, + AArch64_UCVTFSWDri = 2082, + AArch64_UCVTFSWSri = 2083, + AArch64_UCVTFSXDri = 2084, + AArch64_UCVTFSXSri = 2085, + AArch64_UCVTFUWDri = 2086, + AArch64_UCVTFUWSri = 2087, + AArch64_UCVTFUXDri = 2088, + AArch64_UCVTFUXSri = 2089, + AArch64_UCVTFd = 2090, + AArch64_UCVTFs = 2091, + AArch64_UCVTFv1i32 = 2092, + AArch64_UCVTFv1i64 = 2093, + AArch64_UCVTFv2f32 = 2094, + AArch64_UCVTFv2f64 = 2095, + AArch64_UCVTFv2i32_shift = 2096, + AArch64_UCVTFv2i64_shift = 2097, + AArch64_UCVTFv4f32 = 2098, + AArch64_UCVTFv4i32_shift = 2099, + AArch64_UDIVWr = 2100, + AArch64_UDIVXr = 2101, + AArch64_UDIV_IntWr = 2102, + AArch64_UDIV_IntXr = 2103, + AArch64_UHADDv16i8 = 2104, + AArch64_UHADDv2i32 = 2105, + AArch64_UHADDv4i16 = 2106, + AArch64_UHADDv4i32 = 2107, + AArch64_UHADDv8i16 = 2108, + AArch64_UHADDv8i8 = 2109, + AArch64_UHSUBv16i8 = 2110, + AArch64_UHSUBv2i32 = 2111, + AArch64_UHSUBv4i16 = 2112, + AArch64_UHSUBv4i32 = 2113, + AArch64_UHSUBv8i16 = 2114, + AArch64_UHSUBv8i8 = 2115, + AArch64_UMADDLrrr = 2116, + AArch64_UMAXPv16i8 = 2117, + AArch64_UMAXPv2i32 = 2118, + AArch64_UMAXPv4i16 = 2119, + AArch64_UMAXPv4i32 = 2120, + AArch64_UMAXPv8i16 = 2121, + AArch64_UMAXPv8i8 = 2122, + AArch64_UMAXVv16i8v = 2123, + AArch64_UMAXVv4i16v = 2124, + AArch64_UMAXVv4i32v = 2125, + AArch64_UMAXVv8i16v = 2126, + AArch64_UMAXVv8i8v = 2127, + AArch64_UMAXv16i8 = 2128, + AArch64_UMAXv2i32 = 2129, + AArch64_UMAXv4i16 = 2130, + AArch64_UMAXv4i32 = 2131, + AArch64_UMAXv8i16 = 2132, + AArch64_UMAXv8i8 = 2133, + AArch64_UMINPv16i8 = 2134, + AArch64_UMINPv2i32 = 2135, + AArch64_UMINPv4i16 = 2136, + AArch64_UMINPv4i32 = 2137, + AArch64_UMINPv8i16 = 2138, + AArch64_UMINPv8i8 = 2139, + AArch64_UMINVv16i8v = 2140, + AArch64_UMINVv4i16v = 2141, + AArch64_UMINVv4i32v = 2142, + AArch64_UMINVv8i16v = 2143, + AArch64_UMINVv8i8v = 2144, + AArch64_UMINv16i8 = 2145, + AArch64_UMINv2i32 = 2146, + AArch64_UMINv4i16 = 2147, + AArch64_UMINv4i32 = 2148, + AArch64_UMINv8i16 = 2149, + AArch64_UMINv8i8 = 2150, + AArch64_UMLALv16i8_v8i16 = 2151, + AArch64_UMLALv2i32_indexed = 2152, + AArch64_UMLALv2i32_v2i64 = 2153, + AArch64_UMLALv4i16_indexed = 2154, + AArch64_UMLALv4i16_v4i32 = 2155, + AArch64_UMLALv4i32_indexed = 2156, + AArch64_UMLALv4i32_v2i64 = 2157, + AArch64_UMLALv8i16_indexed = 2158, + AArch64_UMLALv8i16_v4i32 = 2159, + AArch64_UMLALv8i8_v8i16 = 2160, + AArch64_UMLSLv16i8_v8i16 = 2161, + AArch64_UMLSLv2i32_indexed = 2162, + AArch64_UMLSLv2i32_v2i64 = 2163, + AArch64_UMLSLv4i16_indexed = 2164, + AArch64_UMLSLv4i16_v4i32 = 2165, + AArch64_UMLSLv4i32_indexed = 2166, + AArch64_UMLSLv4i32_v2i64 = 2167, + AArch64_UMLSLv8i16_indexed = 2168, + AArch64_UMLSLv8i16_v4i32 = 2169, + AArch64_UMLSLv8i8_v8i16 = 2170, + AArch64_UMOVvi16 = 2171, + AArch64_UMOVvi32 = 2172, + AArch64_UMOVvi64 = 2173, + AArch64_UMOVvi8 = 2174, + AArch64_UMSUBLrrr = 2175, + AArch64_UMULHrr = 2176, + AArch64_UMULLv16i8_v8i16 = 2177, + AArch64_UMULLv2i32_indexed = 2178, + AArch64_UMULLv2i32_v2i64 = 2179, + AArch64_UMULLv4i16_indexed = 2180, + AArch64_UMULLv4i16_v4i32 = 2181, + AArch64_UMULLv4i32_indexed = 2182, + AArch64_UMULLv4i32_v2i64 = 2183, + AArch64_UMULLv8i16_indexed = 2184, + AArch64_UMULLv8i16_v4i32 = 2185, + AArch64_UMULLv8i8_v8i16 = 2186, + AArch64_UQADDv16i8 = 2187, + AArch64_UQADDv1i16 = 2188, + AArch64_UQADDv1i32 = 2189, + AArch64_UQADDv1i64 = 2190, + AArch64_UQADDv1i8 = 2191, + AArch64_UQADDv2i32 = 2192, + AArch64_UQADDv2i64 = 2193, + AArch64_UQADDv4i16 = 2194, + AArch64_UQADDv4i32 = 2195, + AArch64_UQADDv8i16 = 2196, + AArch64_UQADDv8i8 = 2197, + AArch64_UQRSHLv16i8 = 2198, + AArch64_UQRSHLv1i16 = 2199, + AArch64_UQRSHLv1i32 = 2200, + AArch64_UQRSHLv1i64 = 2201, + AArch64_UQRSHLv1i8 = 2202, + AArch64_UQRSHLv2i32 = 2203, + AArch64_UQRSHLv2i64 = 2204, + AArch64_UQRSHLv4i16 = 2205, + AArch64_UQRSHLv4i32 = 2206, + AArch64_UQRSHLv8i16 = 2207, + AArch64_UQRSHLv8i8 = 2208, + AArch64_UQRSHRNb = 2209, + AArch64_UQRSHRNh = 2210, + AArch64_UQRSHRNs = 2211, + AArch64_UQRSHRNv16i8_shift = 2212, + AArch64_UQRSHRNv2i32_shift = 2213, + AArch64_UQRSHRNv4i16_shift = 2214, + AArch64_UQRSHRNv4i32_shift = 2215, + AArch64_UQRSHRNv8i16_shift = 2216, + AArch64_UQRSHRNv8i8_shift = 2217, + AArch64_UQSHLb = 2218, + AArch64_UQSHLd = 2219, + AArch64_UQSHLh = 2220, + AArch64_UQSHLs = 2221, + AArch64_UQSHLv16i8 = 2222, + AArch64_UQSHLv16i8_shift = 2223, + AArch64_UQSHLv1i16 = 2224, + AArch64_UQSHLv1i32 = 2225, + AArch64_UQSHLv1i64 = 2226, + AArch64_UQSHLv1i8 = 2227, + AArch64_UQSHLv2i32 = 2228, + AArch64_UQSHLv2i32_shift = 2229, + AArch64_UQSHLv2i64 = 2230, + AArch64_UQSHLv2i64_shift = 2231, + AArch64_UQSHLv4i16 = 2232, + AArch64_UQSHLv4i16_shift = 2233, + AArch64_UQSHLv4i32 = 2234, + AArch64_UQSHLv4i32_shift = 2235, + AArch64_UQSHLv8i16 = 2236, + AArch64_UQSHLv8i16_shift = 2237, + AArch64_UQSHLv8i8 = 2238, + AArch64_UQSHLv8i8_shift = 2239, + AArch64_UQSHRNb = 2240, + AArch64_UQSHRNh = 2241, + AArch64_UQSHRNs = 2242, + AArch64_UQSHRNv16i8_shift = 2243, + AArch64_UQSHRNv2i32_shift = 2244, + AArch64_UQSHRNv4i16_shift = 2245, + AArch64_UQSHRNv4i32_shift = 2246, + AArch64_UQSHRNv8i16_shift = 2247, + AArch64_UQSHRNv8i8_shift = 2248, + AArch64_UQSUBv16i8 = 2249, + AArch64_UQSUBv1i16 = 2250, + AArch64_UQSUBv1i32 = 2251, + AArch64_UQSUBv1i64 = 2252, + AArch64_UQSUBv1i8 = 2253, + AArch64_UQSUBv2i32 = 2254, + AArch64_UQSUBv2i64 = 2255, + AArch64_UQSUBv4i16 = 2256, + AArch64_UQSUBv4i32 = 2257, + AArch64_UQSUBv8i16 = 2258, + AArch64_UQSUBv8i8 = 2259, + AArch64_UQXTNv16i8 = 2260, + AArch64_UQXTNv1i16 = 2261, + AArch64_UQXTNv1i32 = 2262, + AArch64_UQXTNv1i8 = 2263, + AArch64_UQXTNv2i32 = 2264, + AArch64_UQXTNv4i16 = 2265, + AArch64_UQXTNv4i32 = 2266, + AArch64_UQXTNv8i16 = 2267, + AArch64_UQXTNv8i8 = 2268, + AArch64_URECPEv2i32 = 2269, + AArch64_URECPEv4i32 = 2270, + AArch64_URHADDv16i8 = 2271, + AArch64_URHADDv2i32 = 2272, + AArch64_URHADDv4i16 = 2273, + AArch64_URHADDv4i32 = 2274, + AArch64_URHADDv8i16 = 2275, + AArch64_URHADDv8i8 = 2276, + AArch64_URSHLv16i8 = 2277, + AArch64_URSHLv1i64 = 2278, + AArch64_URSHLv2i32 = 2279, + AArch64_URSHLv2i64 = 2280, + AArch64_URSHLv4i16 = 2281, + AArch64_URSHLv4i32 = 2282, + AArch64_URSHLv8i16 = 2283, + AArch64_URSHLv8i8 = 2284, + AArch64_URSHRd = 2285, + AArch64_URSHRv16i8_shift = 2286, + AArch64_URSHRv2i32_shift = 2287, + AArch64_URSHRv2i64_shift = 2288, + AArch64_URSHRv4i16_shift = 2289, + AArch64_URSHRv4i32_shift = 2290, + AArch64_URSHRv8i16_shift = 2291, + AArch64_URSHRv8i8_shift = 2292, + AArch64_URSQRTEv2i32 = 2293, + AArch64_URSQRTEv4i32 = 2294, + AArch64_URSRAd = 2295, + AArch64_URSRAv16i8_shift = 2296, + AArch64_URSRAv2i32_shift = 2297, + AArch64_URSRAv2i64_shift = 2298, + AArch64_URSRAv4i16_shift = 2299, + AArch64_URSRAv4i32_shift = 2300, + AArch64_URSRAv8i16_shift = 2301, + AArch64_URSRAv8i8_shift = 2302, + AArch64_USHLLv16i8_shift = 2303, + AArch64_USHLLv2i32_shift = 2304, + AArch64_USHLLv4i16_shift = 2305, + AArch64_USHLLv4i32_shift = 2306, + AArch64_USHLLv8i16_shift = 2307, + AArch64_USHLLv8i8_shift = 2308, + AArch64_USHLv16i8 = 2309, + AArch64_USHLv1i64 = 2310, + AArch64_USHLv2i32 = 2311, + AArch64_USHLv2i64 = 2312, + AArch64_USHLv4i16 = 2313, + AArch64_USHLv4i32 = 2314, + AArch64_USHLv8i16 = 2315, + AArch64_USHLv8i8 = 2316, + AArch64_USHRd = 2317, + AArch64_USHRv16i8_shift = 2318, + AArch64_USHRv2i32_shift = 2319, + AArch64_USHRv2i64_shift = 2320, + AArch64_USHRv4i16_shift = 2321, + AArch64_USHRv4i32_shift = 2322, + AArch64_USHRv8i16_shift = 2323, + AArch64_USHRv8i8_shift = 2324, + AArch64_USQADDv16i8 = 2325, + AArch64_USQADDv1i16 = 2326, + AArch64_USQADDv1i32 = 2327, + AArch64_USQADDv1i64 = 2328, + AArch64_USQADDv1i8 = 2329, + AArch64_USQADDv2i32 = 2330, + AArch64_USQADDv2i64 = 2331, + AArch64_USQADDv4i16 = 2332, + AArch64_USQADDv4i32 = 2333, + AArch64_USQADDv8i16 = 2334, + AArch64_USQADDv8i8 = 2335, + AArch64_USRAd = 2336, + AArch64_USRAv16i8_shift = 2337, + AArch64_USRAv2i32_shift = 2338, + AArch64_USRAv2i64_shift = 2339, + AArch64_USRAv4i16_shift = 2340, + AArch64_USRAv4i32_shift = 2341, + AArch64_USRAv8i16_shift = 2342, + AArch64_USRAv8i8_shift = 2343, + AArch64_USUBLv16i8_v8i16 = 2344, + AArch64_USUBLv2i32_v2i64 = 2345, + AArch64_USUBLv4i16_v4i32 = 2346, + AArch64_USUBLv4i32_v2i64 = 2347, + AArch64_USUBLv8i16_v4i32 = 2348, + AArch64_USUBLv8i8_v8i16 = 2349, + AArch64_USUBWv16i8_v8i16 = 2350, + AArch64_USUBWv2i32_v2i64 = 2351, + AArch64_USUBWv4i16_v4i32 = 2352, + AArch64_USUBWv4i32_v2i64 = 2353, + AArch64_USUBWv8i16_v4i32 = 2354, + AArch64_USUBWv8i8_v8i16 = 2355, + AArch64_UZP1v16i8 = 2356, + AArch64_UZP1v2i32 = 2357, + AArch64_UZP1v2i64 = 2358, + AArch64_UZP1v4i16 = 2359, + AArch64_UZP1v4i32 = 2360, + AArch64_UZP1v8i16 = 2361, + AArch64_UZP1v8i8 = 2362, + AArch64_UZP2v16i8 = 2363, + AArch64_UZP2v2i32 = 2364, + AArch64_UZP2v2i64 = 2365, + AArch64_UZP2v4i16 = 2366, + AArch64_UZP2v4i32 = 2367, + AArch64_UZP2v8i16 = 2368, + AArch64_UZP2v8i8 = 2369, + AArch64_XTNv16i8 = 2370, + AArch64_XTNv2i32 = 2371, + AArch64_XTNv4i16 = 2372, + AArch64_XTNv4i32 = 2373, + AArch64_XTNv8i16 = 2374, + AArch64_XTNv8i8 = 2375, + AArch64_ZIP1v16i8 = 2376, + AArch64_ZIP1v2i32 = 2377, + AArch64_ZIP1v2i64 = 2378, + AArch64_ZIP1v4i16 = 2379, + AArch64_ZIP1v4i32 = 2380, + AArch64_ZIP1v8i16 = 2381, + AArch64_ZIP1v8i8 = 2382, + AArch64_ZIP2v16i8 = 2383, + AArch64_ZIP2v2i32 = 2384, + AArch64_ZIP2v2i64 = 2385, + AArch64_ZIP2v4i16 = 2386, + AArch64_ZIP2v4i32 = 2387, + AArch64_ZIP2v8i16 = 2388, + AArch64_ZIP2v8i8 = 2389, + AArch64_INSTRUCTION_LIST_END = 2390 +}; + +#endif // GET_INSTRINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64GenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenRegisterInfo.inc new file mode 100644 index 0000000..57eb693 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenRegisterInfo.inc @@ -0,0 +1,1540 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + AArch64_NoRegister, + AArch64_FP = 1, + AArch64_LR = 2, + AArch64_NZCV = 3, + AArch64_SP = 4, + AArch64_WSP = 5, + AArch64_WZR = 6, + AArch64_XZR = 7, + AArch64_B0 = 8, + AArch64_B1 = 9, + AArch64_B2 = 10, + AArch64_B3 = 11, + AArch64_B4 = 12, + AArch64_B5 = 13, + AArch64_B6 = 14, + AArch64_B7 = 15, + AArch64_B8 = 16, + AArch64_B9 = 17, + AArch64_B10 = 18, + AArch64_B11 = 19, + AArch64_B12 = 20, + AArch64_B13 = 21, + AArch64_B14 = 22, + AArch64_B15 = 23, + AArch64_B16 = 24, + AArch64_B17 = 25, + AArch64_B18 = 26, + AArch64_B19 = 27, + AArch64_B20 = 28, + AArch64_B21 = 29, + AArch64_B22 = 30, + AArch64_B23 = 31, + AArch64_B24 = 32, + AArch64_B25 = 33, + AArch64_B26 = 34, + AArch64_B27 = 35, + AArch64_B28 = 36, + AArch64_B29 = 37, + AArch64_B30 = 38, + AArch64_B31 = 39, + AArch64_D0 = 40, + AArch64_D1 = 41, + AArch64_D2 = 42, + AArch64_D3 = 43, + AArch64_D4 = 44, + AArch64_D5 = 45, + AArch64_D6 = 46, + AArch64_D7 = 47, + AArch64_D8 = 48, + AArch64_D9 = 49, + AArch64_D10 = 50, + AArch64_D11 = 51, + AArch64_D12 = 52, + AArch64_D13 = 53, + AArch64_D14 = 54, + AArch64_D15 = 55, + AArch64_D16 = 56, + AArch64_D17 = 57, + AArch64_D18 = 58, + AArch64_D19 = 59, + AArch64_D20 = 60, + AArch64_D21 = 61, + AArch64_D22 = 62, + AArch64_D23 = 63, + AArch64_D24 = 64, + AArch64_D25 = 65, + AArch64_D26 = 66, + AArch64_D27 = 67, + AArch64_D28 = 68, + AArch64_D29 = 69, + AArch64_D30 = 70, + AArch64_D31 = 71, + AArch64_H0 = 72, + AArch64_H1 = 73, + AArch64_H2 = 74, + AArch64_H3 = 75, + AArch64_H4 = 76, + AArch64_H5 = 77, + AArch64_H6 = 78, + AArch64_H7 = 79, + AArch64_H8 = 80, + AArch64_H9 = 81, + AArch64_H10 = 82, + AArch64_H11 = 83, + AArch64_H12 = 84, + AArch64_H13 = 85, + AArch64_H14 = 86, + AArch64_H15 = 87, + AArch64_H16 = 88, + AArch64_H17 = 89, + AArch64_H18 = 90, + AArch64_H19 = 91, + AArch64_H20 = 92, + AArch64_H21 = 93, + AArch64_H22 = 94, + AArch64_H23 = 95, + AArch64_H24 = 96, + AArch64_H25 = 97, + AArch64_H26 = 98, + AArch64_H27 = 99, + AArch64_H28 = 100, + AArch64_H29 = 101, + AArch64_H30 = 102, + AArch64_H31 = 103, + AArch64_Q0 = 104, + AArch64_Q1 = 105, + AArch64_Q2 = 106, + AArch64_Q3 = 107, + AArch64_Q4 = 108, + AArch64_Q5 = 109, + AArch64_Q6 = 110, + AArch64_Q7 = 111, + AArch64_Q8 = 112, + AArch64_Q9 = 113, + AArch64_Q10 = 114, + AArch64_Q11 = 115, + AArch64_Q12 = 116, + AArch64_Q13 = 117, + AArch64_Q14 = 118, + AArch64_Q15 = 119, + AArch64_Q16 = 120, + AArch64_Q17 = 121, + AArch64_Q18 = 122, + AArch64_Q19 = 123, + AArch64_Q20 = 124, + AArch64_Q21 = 125, + AArch64_Q22 = 126, + AArch64_Q23 = 127, + AArch64_Q24 = 128, + AArch64_Q25 = 129, + AArch64_Q26 = 130, + AArch64_Q27 = 131, + AArch64_Q28 = 132, + AArch64_Q29 = 133, + AArch64_Q30 = 134, + AArch64_Q31 = 135, + AArch64_S0 = 136, + AArch64_S1 = 137, + AArch64_S2 = 138, + AArch64_S3 = 139, + AArch64_S4 = 140, + AArch64_S5 = 141, + AArch64_S6 = 142, + AArch64_S7 = 143, + AArch64_S8 = 144, + AArch64_S9 = 145, + AArch64_S10 = 146, + AArch64_S11 = 147, + AArch64_S12 = 148, + AArch64_S13 = 149, + AArch64_S14 = 150, + AArch64_S15 = 151, + AArch64_S16 = 152, + AArch64_S17 = 153, + AArch64_S18 = 154, + AArch64_S19 = 155, + AArch64_S20 = 156, + AArch64_S21 = 157, + AArch64_S22 = 158, + AArch64_S23 = 159, + AArch64_S24 = 160, + AArch64_S25 = 161, + AArch64_S26 = 162, + AArch64_S27 = 163, + AArch64_S28 = 164, + AArch64_S29 = 165, + AArch64_S30 = 166, + AArch64_S31 = 167, + AArch64_W0 = 168, + AArch64_W1 = 169, + AArch64_W2 = 170, + AArch64_W3 = 171, + AArch64_W4 = 172, + AArch64_W5 = 173, + AArch64_W6 = 174, + AArch64_W7 = 175, + AArch64_W8 = 176, + AArch64_W9 = 177, + AArch64_W10 = 178, + AArch64_W11 = 179, + AArch64_W12 = 180, + AArch64_W13 = 181, + AArch64_W14 = 182, + AArch64_W15 = 183, + AArch64_W16 = 184, + AArch64_W17 = 185, + AArch64_W18 = 186, + AArch64_W19 = 187, + AArch64_W20 = 188, + AArch64_W21 = 189, + AArch64_W22 = 190, + AArch64_W23 = 191, + AArch64_W24 = 192, + AArch64_W25 = 193, + AArch64_W26 = 194, + AArch64_W27 = 195, + AArch64_W28 = 196, + AArch64_W29 = 197, + AArch64_W30 = 198, + AArch64_X0 = 199, + AArch64_X1 = 200, + AArch64_X2 = 201, + AArch64_X3 = 202, + AArch64_X4 = 203, + AArch64_X5 = 204, + AArch64_X6 = 205, + AArch64_X7 = 206, + AArch64_X8 = 207, + AArch64_X9 = 208, + AArch64_X10 = 209, + AArch64_X11 = 210, + AArch64_X12 = 211, + AArch64_X13 = 212, + AArch64_X14 = 213, + AArch64_X15 = 214, + AArch64_X16 = 215, + AArch64_X17 = 216, + AArch64_X18 = 217, + AArch64_X19 = 218, + AArch64_X20 = 219, + AArch64_X21 = 220, + AArch64_X22 = 221, + AArch64_X23 = 222, + AArch64_X24 = 223, + AArch64_X25 = 224, + AArch64_X26 = 225, + AArch64_X27 = 226, + AArch64_X28 = 227, + AArch64_D0_D1 = 228, + AArch64_D1_D2 = 229, + AArch64_D2_D3 = 230, + AArch64_D3_D4 = 231, + AArch64_D4_D5 = 232, + AArch64_D5_D6 = 233, + AArch64_D6_D7 = 234, + AArch64_D7_D8 = 235, + AArch64_D8_D9 = 236, + AArch64_D9_D10 = 237, + AArch64_D10_D11 = 238, + AArch64_D11_D12 = 239, + AArch64_D12_D13 = 240, + AArch64_D13_D14 = 241, + AArch64_D14_D15 = 242, + AArch64_D15_D16 = 243, + AArch64_D16_D17 = 244, + AArch64_D17_D18 = 245, + AArch64_D18_D19 = 246, + AArch64_D19_D20 = 247, + AArch64_D20_D21 = 248, + AArch64_D21_D22 = 249, + AArch64_D22_D23 = 250, + AArch64_D23_D24 = 251, + AArch64_D24_D25 = 252, + AArch64_D25_D26 = 253, + AArch64_D26_D27 = 254, + AArch64_D27_D28 = 255, + AArch64_D28_D29 = 256, + AArch64_D29_D30 = 257, + AArch64_D30_D31 = 258, + AArch64_D31_D0 = 259, + AArch64_D0_D1_D2_D3 = 260, + AArch64_D1_D2_D3_D4 = 261, + AArch64_D2_D3_D4_D5 = 262, + AArch64_D3_D4_D5_D6 = 263, + AArch64_D4_D5_D6_D7 = 264, + AArch64_D5_D6_D7_D8 = 265, + AArch64_D6_D7_D8_D9 = 266, + AArch64_D7_D8_D9_D10 = 267, + AArch64_D8_D9_D10_D11 = 268, + AArch64_D9_D10_D11_D12 = 269, + AArch64_D10_D11_D12_D13 = 270, + AArch64_D11_D12_D13_D14 = 271, + AArch64_D12_D13_D14_D15 = 272, + AArch64_D13_D14_D15_D16 = 273, + AArch64_D14_D15_D16_D17 = 274, + AArch64_D15_D16_D17_D18 = 275, + AArch64_D16_D17_D18_D19 = 276, + AArch64_D17_D18_D19_D20 = 277, + AArch64_D18_D19_D20_D21 = 278, + AArch64_D19_D20_D21_D22 = 279, + AArch64_D20_D21_D22_D23 = 280, + AArch64_D21_D22_D23_D24 = 281, + AArch64_D22_D23_D24_D25 = 282, + AArch64_D23_D24_D25_D26 = 283, + AArch64_D24_D25_D26_D27 = 284, + AArch64_D25_D26_D27_D28 = 285, + AArch64_D26_D27_D28_D29 = 286, + AArch64_D27_D28_D29_D30 = 287, + AArch64_D28_D29_D30_D31 = 288, + AArch64_D29_D30_D31_D0 = 289, + AArch64_D30_D31_D0_D1 = 290, + AArch64_D31_D0_D1_D2 = 291, + AArch64_D0_D1_D2 = 292, + AArch64_D1_D2_D3 = 293, + AArch64_D2_D3_D4 = 294, + AArch64_D3_D4_D5 = 295, + AArch64_D4_D5_D6 = 296, + AArch64_D5_D6_D7 = 297, + AArch64_D6_D7_D8 = 298, + AArch64_D7_D8_D9 = 299, + AArch64_D8_D9_D10 = 300, + AArch64_D9_D10_D11 = 301, + AArch64_D10_D11_D12 = 302, + AArch64_D11_D12_D13 = 303, + AArch64_D12_D13_D14 = 304, + AArch64_D13_D14_D15 = 305, + AArch64_D14_D15_D16 = 306, + AArch64_D15_D16_D17 = 307, + AArch64_D16_D17_D18 = 308, + AArch64_D17_D18_D19 = 309, + AArch64_D18_D19_D20 = 310, + AArch64_D19_D20_D21 = 311, + AArch64_D20_D21_D22 = 312, + AArch64_D21_D22_D23 = 313, + AArch64_D22_D23_D24 = 314, + AArch64_D23_D24_D25 = 315, + AArch64_D24_D25_D26 = 316, + AArch64_D25_D26_D27 = 317, + AArch64_D26_D27_D28 = 318, + AArch64_D27_D28_D29 = 319, + AArch64_D28_D29_D30 = 320, + AArch64_D29_D30_D31 = 321, + AArch64_D30_D31_D0 = 322, + AArch64_D31_D0_D1 = 323, + AArch64_Q0_Q1 = 324, + AArch64_Q1_Q2 = 325, + AArch64_Q2_Q3 = 326, + AArch64_Q3_Q4 = 327, + AArch64_Q4_Q5 = 328, + AArch64_Q5_Q6 = 329, + AArch64_Q6_Q7 = 330, + AArch64_Q7_Q8 = 331, + AArch64_Q8_Q9 = 332, + AArch64_Q9_Q10 = 333, + AArch64_Q10_Q11 = 334, + AArch64_Q11_Q12 = 335, + AArch64_Q12_Q13 = 336, + AArch64_Q13_Q14 = 337, + AArch64_Q14_Q15 = 338, + AArch64_Q15_Q16 = 339, + AArch64_Q16_Q17 = 340, + AArch64_Q17_Q18 = 341, + AArch64_Q18_Q19 = 342, + AArch64_Q19_Q20 = 343, + AArch64_Q20_Q21 = 344, + AArch64_Q21_Q22 = 345, + AArch64_Q22_Q23 = 346, + AArch64_Q23_Q24 = 347, + AArch64_Q24_Q25 = 348, + AArch64_Q25_Q26 = 349, + AArch64_Q26_Q27 = 350, + AArch64_Q27_Q28 = 351, + AArch64_Q28_Q29 = 352, + AArch64_Q29_Q30 = 353, + AArch64_Q30_Q31 = 354, + AArch64_Q31_Q0 = 355, + AArch64_Q0_Q1_Q2_Q3 = 356, + AArch64_Q1_Q2_Q3_Q4 = 357, + AArch64_Q2_Q3_Q4_Q5 = 358, + AArch64_Q3_Q4_Q5_Q6 = 359, + AArch64_Q4_Q5_Q6_Q7 = 360, + AArch64_Q5_Q6_Q7_Q8 = 361, + AArch64_Q6_Q7_Q8_Q9 = 362, + AArch64_Q7_Q8_Q9_Q10 = 363, + AArch64_Q8_Q9_Q10_Q11 = 364, + AArch64_Q9_Q10_Q11_Q12 = 365, + AArch64_Q10_Q11_Q12_Q13 = 366, + AArch64_Q11_Q12_Q13_Q14 = 367, + AArch64_Q12_Q13_Q14_Q15 = 368, + AArch64_Q13_Q14_Q15_Q16 = 369, + AArch64_Q14_Q15_Q16_Q17 = 370, + AArch64_Q15_Q16_Q17_Q18 = 371, + AArch64_Q16_Q17_Q18_Q19 = 372, + AArch64_Q17_Q18_Q19_Q20 = 373, + AArch64_Q18_Q19_Q20_Q21 = 374, + AArch64_Q19_Q20_Q21_Q22 = 375, + AArch64_Q20_Q21_Q22_Q23 = 376, + AArch64_Q21_Q22_Q23_Q24 = 377, + AArch64_Q22_Q23_Q24_Q25 = 378, + AArch64_Q23_Q24_Q25_Q26 = 379, + AArch64_Q24_Q25_Q26_Q27 = 380, + AArch64_Q25_Q26_Q27_Q28 = 381, + AArch64_Q26_Q27_Q28_Q29 = 382, + AArch64_Q27_Q28_Q29_Q30 = 383, + AArch64_Q28_Q29_Q30_Q31 = 384, + AArch64_Q29_Q30_Q31_Q0 = 385, + AArch64_Q30_Q31_Q0_Q1 = 386, + AArch64_Q31_Q0_Q1_Q2 = 387, + AArch64_Q0_Q1_Q2 = 388, + AArch64_Q1_Q2_Q3 = 389, + AArch64_Q2_Q3_Q4 = 390, + AArch64_Q3_Q4_Q5 = 391, + AArch64_Q4_Q5_Q6 = 392, + AArch64_Q5_Q6_Q7 = 393, + AArch64_Q6_Q7_Q8 = 394, + AArch64_Q7_Q8_Q9 = 395, + AArch64_Q8_Q9_Q10 = 396, + AArch64_Q9_Q10_Q11 = 397, + AArch64_Q10_Q11_Q12 = 398, + AArch64_Q11_Q12_Q13 = 399, + AArch64_Q12_Q13_Q14 = 400, + AArch64_Q13_Q14_Q15 = 401, + AArch64_Q14_Q15_Q16 = 402, + AArch64_Q15_Q16_Q17 = 403, + AArch64_Q16_Q17_Q18 = 404, + AArch64_Q17_Q18_Q19 = 405, + AArch64_Q18_Q19_Q20 = 406, + AArch64_Q19_Q20_Q21 = 407, + AArch64_Q20_Q21_Q22 = 408, + AArch64_Q21_Q22_Q23 = 409, + AArch64_Q22_Q23_Q24 = 410, + AArch64_Q23_Q24_Q25 = 411, + AArch64_Q24_Q25_Q26 = 412, + AArch64_Q25_Q26_Q27 = 413, + AArch64_Q26_Q27_Q28 = 414, + AArch64_Q27_Q28_Q29 = 415, + AArch64_Q28_Q29_Q30 = 416, + AArch64_Q29_Q30_Q31 = 417, + AArch64_Q30_Q31_Q0 = 418, + AArch64_Q31_Q0_Q1 = 419, + AArch64_NUM_TARGET_REGS // 420 +}; + +// Register classes +enum { + AArch64_FPR8RegClassID = 0, + AArch64_FPR16RegClassID = 1, + AArch64_GPR32allRegClassID = 2, + AArch64_FPR32RegClassID = 3, + AArch64_GPR32RegClassID = 4, + AArch64_GPR32spRegClassID = 5, + AArch64_GPR32commonRegClassID = 6, + AArch64_CCRRegClassID = 7, + AArch64_GPR32sponlyRegClassID = 8, + AArch64_GPR64allRegClassID = 9, + AArch64_FPR64RegClassID = 10, + AArch64_GPR64RegClassID = 11, + AArch64_GPR64spRegClassID = 12, + AArch64_GPR64commonRegClassID = 13, + AArch64_tcGPR64RegClassID = 14, + AArch64_GPR64sponlyRegClassID = 15, + AArch64_DDRegClassID = 16, + AArch64_FPR128RegClassID = 17, + AArch64_FPR128_loRegClassID = 18, + AArch64_DDDRegClassID = 19, + AArch64_DDDDRegClassID = 20, + AArch64_QQRegClassID = 21, + AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 22, + AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 23, + AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 24, + AArch64_QQQRegClassID = 25, + AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 26, + AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 27, + AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 28, + AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 29, + AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 30, + AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 31, + AArch64_QQQQRegClassID = 32, + AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 33, + AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 34, + AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 35, + AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 36, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 37, + AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 38, + AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 39, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 40, + AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 41, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42, +}; + +// Register alternate name indices +enum { + AArch64_NoRegAltName, // 0 + AArch64_vlist1, // 1 + AArch64_vreg, // 2 + AArch64_NUM_TARGET_REG_ALT_NAMES = 3 +}; + +// Subregister indices +enum { + AArch64_NoSubRegister, + AArch64_bsub, // 1 + AArch64_dsub, // 2 + AArch64_dsub0, // 3 + AArch64_dsub1, // 4 + AArch64_dsub2, // 5 + AArch64_dsub3, // 6 + AArch64_hsub, // 7 + AArch64_qhisub, // 8 + AArch64_qsub, // 9 + AArch64_qsub0, // 10 + AArch64_qsub1, // 11 + AArch64_qsub2, // 12 + AArch64_qsub3, // 13 + AArch64_ssub, // 14 + AArch64_sub_32, // 15 + AArch64_dsub1_then_bsub, // 16 + AArch64_dsub1_then_hsub, // 17 + AArch64_dsub1_then_ssub, // 18 + AArch64_dsub3_then_bsub, // 19 + AArch64_dsub3_then_hsub, // 20 + AArch64_dsub3_then_ssub, // 21 + AArch64_dsub2_then_bsub, // 22 + AArch64_dsub2_then_hsub, // 23 + AArch64_dsub2_then_ssub, // 24 + AArch64_qsub1_then_bsub, // 25 + AArch64_qsub1_then_dsub, // 26 + AArch64_qsub1_then_hsub, // 27 + AArch64_qsub1_then_ssub, // 28 + AArch64_qsub3_then_bsub, // 29 + AArch64_qsub3_then_dsub, // 30 + AArch64_qsub3_then_hsub, // 31 + AArch64_qsub3_then_ssub, // 32 + AArch64_qsub2_then_bsub, // 33 + AArch64_qsub2_then_dsub, // 34 + AArch64_qsub2_then_hsub, // 35 + AArch64_qsub2_then_ssub, // 36 + AArch64_dsub0_dsub1, // 37 + AArch64_dsub0_dsub1_dsub2, // 38 + AArch64_dsub1_dsub2, // 39 + AArch64_dsub1_dsub2_dsub3, // 40 + AArch64_dsub2_dsub3, // 41 + AArch64_dsub_qsub1_then_dsub, // 42 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 43 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 44 + AArch64_qsub0_qsub1, // 45 + AArch64_qsub0_qsub1_qsub2, // 46 + AArch64_qsub1_qsub2, // 47 + AArch64_qsub1_qsub2_qsub3, // 48 + AArch64_qsub2_qsub3, // 49 + AArch64_qsub1_then_dsub_qsub2_then_dsub, // 50 + AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 51 + AArch64_qsub2_then_dsub_qsub3_then_dsub, // 52 + AArch64_NUM_TARGET_SUBREGS +}; + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg AArch64RegDiffLists[] = { + /* 0 */ 65185, 1, 1, 1, 0, + /* 5 */ 65281, 1, 1, 1, 0, + /* 10 */ 5, 29, 1, 1, 0, + /* 15 */ 65153, 1, 1, 0, + /* 19 */ 65249, 1, 1, 0, + /* 23 */ 5, 1, 29, 1, 0, + /* 28 */ 5, 30, 1, 0, + /* 32 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0, + /* 47 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0, + /* 62 */ 65217, 1, 0, + /* 65 */ 65313, 1, 0, + /* 68 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, + /* 91 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, + /* 101 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, + /* 124 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, + /* 134 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0, + /* 146 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, + /* 169 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, + /* 179 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0, + /* 191 */ 65503, 1, 128, 65503, 1, 0, + /* 197 */ 3, 0, + /* 199 */ 4, 0, + /* 201 */ 5, 1, 1, 29, 0, + /* 206 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, + /* 229 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, + /* 239 */ 5, 1, 30, 0, + /* 243 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0, + /* 255 */ 5, 31, 0, + /* 258 */ 65504, 31, 97, 65504, 31, 0, + /* 264 */ 96, 0, + /* 266 */ 196, 0, + /* 268 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0, + /* 280 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0, + /* 292 */ 65339, 0, + /* 294 */ 65340, 0, + /* 296 */ 65374, 0, + /* 298 */ 65405, 0, + /* 300 */ 65437, 0, + /* 302 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0, + /* 323 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0, + /* 344 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0, + /* 365 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, + /* 397 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0, + /* 419 */ 65469, 0, + /* 421 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0, + /* 430 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0, + /* 439 */ 65472, 96, 65472, 65472, 0, + /* 444 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, + /* 476 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, + /* 508 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, + /* 540 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0, + /* 562 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0, + /* 584 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0, + /* 606 */ 65501, 0, + /* 608 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0, + /* 623 */ 65533, 0, + /* 625 */ 65535, 0, +}; + +static const uint16_t AArch64SubRegIdxLists[] = { + /* 0 */ 2, 14, 7, 1, 0, + /* 5 */ 15, 0, + /* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0, + /* 16 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 37, 39, 0, + /* 31 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 6, 21, 20, 19, 37, 38, 39, 40, 41, 0, + /* 53 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 42, 0, + /* 65 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 42, 44, 45, 47, 50, 0, + /* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0, +}; + +static MCRegisterDesc AArch64RegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 1518, 266, 4, 5, 10001, 26 }, + { 1525, 266, 4, 5, 10001, 26 }, + { 1536, 4, 4, 4, 10001, 0 }, + { 1522, 3, 4, 5, 3152, 26 }, + { 1521, 4, 625, 4, 3152, 0 }, + { 1528, 4, 3, 4, 3184, 0 }, + { 1532, 625, 4, 5, 3184, 26 }, + { 146, 4, 101, 4, 9969, 0 }, + { 335, 4, 146, 4, 9969, 0 }, + { 480, 4, 206, 4, 9969, 0 }, + { 625, 4, 68, 4, 9969, 0 }, + { 768, 4, 68, 4, 9969, 0 }, + { 911, 4, 68, 4, 9969, 0 }, + { 1054, 4, 68, 4, 9969, 0 }, + { 1197, 4, 68, 4, 9969, 0 }, + { 1340, 4, 68, 4, 9969, 0 }, + { 1479, 4, 68, 4, 9969, 0 }, + { 0, 4, 68, 4, 9969, 0 }, + { 191, 4, 68, 4, 9969, 0 }, + { 378, 4, 68, 4, 9969, 0 }, + { 521, 4, 68, 4, 9969, 0 }, + { 664, 4, 68, 4, 9969, 0 }, + { 807, 4, 68, 4, 9969, 0 }, + { 950, 4, 68, 4, 9969, 0 }, + { 1093, 4, 68, 4, 9969, 0 }, + { 1236, 4, 68, 4, 9969, 0 }, + { 1379, 4, 68, 4, 9969, 0 }, + { 46, 4, 68, 4, 9969, 0 }, + { 239, 4, 68, 4, 9969, 0 }, + { 428, 4, 68, 4, 9969, 0 }, + { 573, 4, 68, 4, 9969, 0 }, + { 716, 4, 68, 4, 9969, 0 }, + { 859, 4, 68, 4, 9969, 0 }, + { 1002, 4, 68, 4, 9969, 0 }, + { 1145, 4, 68, 4, 9969, 0 }, + { 1288, 4, 68, 4, 9969, 0 }, + { 1431, 4, 68, 4, 9969, 0 }, + { 98, 4, 68, 4, 9969, 0 }, + { 291, 4, 68, 4, 9969, 0 }, + { 161, 426, 104, 1, 9697, 3 }, + { 349, 426, 149, 1, 9697, 3 }, + { 493, 426, 209, 1, 9697, 3 }, + { 637, 426, 71, 1, 9697, 3 }, + { 780, 426, 71, 1, 9697, 3 }, + { 923, 426, 71, 1, 9697, 3 }, + { 1066, 426, 71, 1, 9697, 3 }, + { 1209, 426, 71, 1, 9697, 3 }, + { 1352, 426, 71, 1, 9697, 3 }, + { 1491, 426, 71, 1, 9697, 3 }, + { 13, 426, 71, 1, 9697, 3 }, + { 205, 426, 71, 1, 9697, 3 }, + { 393, 426, 71, 1, 9697, 3 }, + { 537, 426, 71, 1, 9697, 3 }, + { 680, 426, 71, 1, 9697, 3 }, + { 823, 426, 71, 1, 9697, 3 }, + { 966, 426, 71, 1, 9697, 3 }, + { 1109, 426, 71, 1, 9697, 3 }, + { 1252, 426, 71, 1, 9697, 3 }, + { 1395, 426, 71, 1, 9697, 3 }, + { 62, 426, 71, 1, 9697, 3 }, + { 255, 426, 71, 1, 9697, 3 }, + { 444, 426, 71, 1, 9697, 3 }, + { 589, 426, 71, 1, 9697, 3 }, + { 732, 426, 71, 1, 9697, 3 }, + { 875, 426, 71, 1, 9697, 3 }, + { 1018, 426, 71, 1, 9697, 3 }, + { 1161, 426, 71, 1, 9697, 3 }, + { 1304, 426, 71, 1, 9697, 3 }, + { 1447, 426, 71, 1, 9697, 3 }, + { 114, 426, 71, 1, 9697, 3 }, + { 307, 426, 71, 1, 9697, 3 }, + { 164, 428, 102, 3, 6705, 3 }, + { 352, 428, 147, 3, 6705, 3 }, + { 496, 428, 207, 3, 6705, 3 }, + { 640, 428, 69, 3, 6705, 3 }, + { 783, 428, 69, 3, 6705, 3 }, + { 926, 428, 69, 3, 6705, 3 }, + { 1069, 428, 69, 3, 6705, 3 }, + { 1212, 428, 69, 3, 6705, 3 }, + { 1355, 428, 69, 3, 6705, 3 }, + { 1494, 428, 69, 3, 6705, 3 }, + { 17, 428, 69, 3, 6705, 3 }, + { 209, 428, 69, 3, 6705, 3 }, + { 397, 428, 69, 3, 6705, 3 }, + { 541, 428, 69, 3, 6705, 3 }, + { 684, 428, 69, 3, 6705, 3 }, + { 827, 428, 69, 3, 6705, 3 }, + { 970, 428, 69, 3, 6705, 3 }, + { 1113, 428, 69, 3, 6705, 3 }, + { 1256, 428, 69, 3, 6705, 3 }, + { 1399, 428, 69, 3, 6705, 3 }, + { 66, 428, 69, 3, 6705, 3 }, + { 259, 428, 69, 3, 6705, 3 }, + { 448, 428, 69, 3, 6705, 3 }, + { 593, 428, 69, 3, 6705, 3 }, + { 736, 428, 69, 3, 6705, 3 }, + { 879, 428, 69, 3, 6705, 3 }, + { 1022, 428, 69, 3, 6705, 3 }, + { 1165, 428, 69, 3, 6705, 3 }, + { 1308, 428, 69, 3, 6705, 3 }, + { 1451, 428, 69, 3, 6705, 3 }, + { 118, 428, 69, 3, 6705, 3 }, + { 311, 428, 69, 3, 6705, 3 }, + { 179, 439, 124, 0, 4801, 3 }, + { 366, 439, 169, 0, 4801, 3 }, + { 509, 439, 229, 0, 4801, 3 }, + { 652, 439, 91, 0, 4801, 3 }, + { 795, 439, 91, 0, 4801, 3 }, + { 938, 439, 91, 0, 4801, 3 }, + { 1081, 439, 91, 0, 4801, 3 }, + { 1224, 439, 91, 0, 4801, 3 }, + { 1367, 439, 91, 0, 4801, 3 }, + { 1506, 439, 91, 0, 4801, 3 }, + { 30, 439, 91, 0, 4801, 3 }, + { 223, 439, 91, 0, 4801, 3 }, + { 412, 439, 91, 0, 4801, 3 }, + { 557, 439, 91, 0, 4801, 3 }, + { 700, 439, 91, 0, 4801, 3 }, + { 843, 439, 91, 0, 4801, 3 }, + { 986, 439, 91, 0, 4801, 3 }, + { 1129, 439, 91, 0, 4801, 3 }, + { 1272, 439, 91, 0, 4801, 3 }, + { 1415, 439, 91, 0, 4801, 3 }, + { 82, 439, 91, 0, 4801, 3 }, + { 275, 439, 91, 0, 4801, 3 }, + { 464, 439, 91, 0, 4801, 3 }, + { 609, 439, 91, 0, 4801, 3 }, + { 752, 439, 91, 0, 4801, 3 }, + { 895, 439, 91, 0, 4801, 3 }, + { 1038, 439, 91, 0, 4801, 3 }, + { 1181, 439, 91, 0, 4801, 3 }, + { 1324, 439, 91, 0, 4801, 3 }, + { 1467, 439, 91, 0, 4801, 3 }, + { 134, 439, 91, 0, 4801, 3 }, + { 327, 439, 91, 0, 4801, 3 }, + { 182, 427, 103, 2, 4769, 3 }, + { 369, 427, 148, 2, 4769, 3 }, + { 512, 427, 208, 2, 4769, 3 }, + { 655, 427, 70, 2, 4769, 3 }, + { 798, 427, 70, 2, 4769, 3 }, + { 941, 427, 70, 2, 4769, 3 }, + { 1084, 427, 70, 2, 4769, 3 }, + { 1227, 427, 70, 2, 4769, 3 }, + { 1370, 427, 70, 2, 4769, 3 }, + { 1509, 427, 70, 2, 4769, 3 }, + { 34, 427, 70, 2, 4769, 3 }, + { 227, 427, 70, 2, 4769, 3 }, + { 416, 427, 70, 2, 4769, 3 }, + { 561, 427, 70, 2, 4769, 3 }, + { 704, 427, 70, 2, 4769, 3 }, + { 847, 427, 70, 2, 4769, 3 }, + { 990, 427, 70, 2, 4769, 3 }, + { 1133, 427, 70, 2, 4769, 3 }, + { 1276, 427, 70, 2, 4769, 3 }, + { 1419, 427, 70, 2, 4769, 3 }, + { 86, 427, 70, 2, 4769, 3 }, + { 279, 427, 70, 2, 4769, 3 }, + { 468, 427, 70, 2, 4769, 3 }, + { 613, 427, 70, 2, 4769, 3 }, + { 756, 427, 70, 2, 4769, 3 }, + { 899, 427, 70, 2, 4769, 3 }, + { 1042, 427, 70, 2, 4769, 3 }, + { 1185, 427, 70, 2, 4769, 3 }, + { 1328, 427, 70, 2, 4769, 3 }, + { 1471, 427, 70, 2, 4769, 3 }, + { 138, 427, 70, 2, 4769, 3 }, + { 331, 427, 70, 2, 4769, 3 }, + { 185, 4, 256, 4, 4769, 0 }, + { 372, 4, 256, 4, 4769, 0 }, + { 515, 4, 256, 4, 4769, 0 }, + { 658, 4, 256, 4, 4769, 0 }, + { 801, 4, 256, 4, 4769, 0 }, + { 944, 4, 256, 4, 4769, 0 }, + { 1087, 4, 256, 4, 4769, 0 }, + { 1230, 4, 256, 4, 4769, 0 }, + { 1373, 4, 256, 4, 4769, 0 }, + { 1512, 4, 256, 4, 4769, 0 }, + { 38, 4, 256, 4, 4769, 0 }, + { 231, 4, 256, 4, 4769, 0 }, + { 420, 4, 256, 4, 4769, 0 }, + { 565, 4, 256, 4, 4769, 0 }, + { 708, 4, 256, 4, 4769, 0 }, + { 851, 4, 256, 4, 4769, 0 }, + { 994, 4, 256, 4, 4769, 0 }, + { 1137, 4, 256, 4, 4769, 0 }, + { 1280, 4, 256, 4, 4769, 0 }, + { 1423, 4, 256, 4, 4769, 0 }, + { 90, 4, 256, 4, 4769, 0 }, + { 283, 4, 256, 4, 4769, 0 }, + { 472, 4, 256, 4, 4769, 0 }, + { 617, 4, 256, 4, 4769, 0 }, + { 760, 4, 256, 4, 4769, 0 }, + { 903, 4, 256, 4, 4769, 0 }, + { 1046, 4, 256, 4, 4769, 0 }, + { 1189, 4, 256, 4, 4769, 0 }, + { 1332, 4, 256, 4, 4769, 0 }, + { 1475, 4, 294, 4, 4673, 0 }, + { 142, 4, 294, 4, 4673, 0 }, + { 188, 621, 4, 5, 4737, 26 }, + { 375, 621, 4, 5, 4737, 26 }, + { 518, 621, 4, 5, 4737, 26 }, + { 661, 621, 4, 5, 4737, 26 }, + { 804, 621, 4, 5, 4737, 26 }, + { 947, 621, 4, 5, 4737, 26 }, + { 1090, 621, 4, 5, 4737, 26 }, + { 1233, 621, 4, 5, 4737, 26 }, + { 1376, 621, 4, 5, 4737, 26 }, + { 1515, 621, 4, 5, 4737, 26 }, + { 42, 621, 4, 5, 4737, 26 }, + { 235, 621, 4, 5, 4737, 26 }, + { 424, 621, 4, 5, 4737, 26 }, + { 569, 621, 4, 5, 4737, 26 }, + { 712, 621, 4, 5, 4737, 26 }, + { 855, 621, 4, 5, 4737, 26 }, + { 998, 621, 4, 5, 4737, 26 }, + { 1141, 621, 4, 5, 4737, 26 }, + { 1284, 621, 4, 5, 4737, 26 }, + { 1427, 621, 4, 5, 4737, 26 }, + { 94, 621, 4, 5, 4737, 26 }, + { 287, 621, 4, 5, 4737, 26 }, + { 476, 621, 4, 5, 4737, 26 }, + { 621, 621, 4, 5, 4737, 26 }, + { 764, 621, 4, 5, 4737, 26 }, + { 907, 621, 4, 5, 4737, 26 }, + { 1050, 621, 4, 5, 4737, 26 }, + { 1193, 621, 4, 5, 4737, 26 }, + { 1336, 621, 4, 5, 4737, 26 }, + { 346, 430, 179, 7, 1041, 30 }, + { 490, 430, 243, 7, 1041, 30 }, + { 634, 430, 134, 7, 1041, 30 }, + { 777, 430, 134, 7, 1041, 30 }, + { 920, 430, 134, 7, 1041, 30 }, + { 1063, 430, 134, 7, 1041, 30 }, + { 1206, 430, 134, 7, 1041, 30 }, + { 1349, 430, 134, 7, 1041, 30 }, + { 1488, 430, 134, 7, 1041, 30 }, + { 10, 430, 134, 7, 1041, 30 }, + { 201, 430, 134, 7, 1041, 30 }, + { 389, 430, 134, 7, 1041, 30 }, + { 533, 430, 134, 7, 1041, 30 }, + { 676, 430, 134, 7, 1041, 30 }, + { 819, 430, 134, 7, 1041, 30 }, + { 962, 430, 134, 7, 1041, 30 }, + { 1105, 430, 134, 7, 1041, 30 }, + { 1248, 430, 134, 7, 1041, 30 }, + { 1391, 430, 134, 7, 1041, 30 }, + { 58, 430, 134, 7, 1041, 30 }, + { 251, 430, 134, 7, 1041, 30 }, + { 440, 430, 134, 7, 1041, 30 }, + { 585, 430, 134, 7, 1041, 30 }, + { 728, 430, 134, 7, 1041, 30 }, + { 871, 430, 134, 7, 1041, 30 }, + { 1014, 430, 134, 7, 1041, 30 }, + { 1157, 430, 134, 7, 1041, 30 }, + { 1300, 430, 134, 7, 1041, 30 }, + { 1443, 430, 134, 7, 1041, 30 }, + { 110, 430, 134, 7, 1041, 30 }, + { 303, 430, 134, 7, 1041, 30 }, + { 157, 421, 134, 7, 4080, 2 }, + { 628, 562, 264, 31, 81, 37 }, + { 771, 562, 264, 31, 81, 37 }, + { 914, 562, 264, 31, 81, 37 }, + { 1057, 562, 264, 31, 81, 37 }, + { 1200, 562, 264, 31, 81, 37 }, + { 1343, 562, 264, 31, 81, 37 }, + { 1482, 562, 264, 31, 81, 37 }, + { 4, 562, 264, 31, 81, 37 }, + { 195, 562, 264, 31, 81, 37 }, + { 382, 562, 264, 31, 81, 37 }, + { 525, 562, 264, 31, 81, 37 }, + { 668, 562, 264, 31, 81, 37 }, + { 811, 562, 264, 31, 81, 37 }, + { 954, 562, 264, 31, 81, 37 }, + { 1097, 562, 264, 31, 81, 37 }, + { 1240, 562, 264, 31, 81, 37 }, + { 1383, 562, 264, 31, 81, 37 }, + { 50, 562, 264, 31, 81, 37 }, + { 243, 562, 264, 31, 81, 37 }, + { 432, 562, 264, 31, 81, 37 }, + { 577, 562, 264, 31, 81, 37 }, + { 720, 562, 264, 31, 81, 37 }, + { 863, 562, 264, 31, 81, 37 }, + { 1006, 562, 264, 31, 81, 37 }, + { 1149, 562, 264, 31, 81, 37 }, + { 1292, 562, 264, 31, 81, 37 }, + { 1435, 562, 264, 31, 81, 37 }, + { 102, 562, 264, 31, 81, 37 }, + { 295, 562, 264, 31, 81, 37 }, + { 149, 584, 264, 31, 160, 42 }, + { 338, 397, 264, 31, 368, 28 }, + { 483, 540, 264, 31, 3216, 5 }, + { 487, 32, 258, 16, 305, 43 }, + { 631, 32, 191, 16, 305, 43 }, + { 774, 32, 191, 16, 305, 43 }, + { 917, 32, 191, 16, 305, 43 }, + { 1060, 32, 191, 16, 305, 43 }, + { 1203, 32, 191, 16, 305, 43 }, + { 1346, 32, 191, 16, 305, 43 }, + { 1485, 32, 191, 16, 305, 43 }, + { 7, 32, 191, 16, 305, 43 }, + { 198, 32, 191, 16, 305, 43 }, + { 385, 32, 191, 16, 305, 43 }, + { 529, 32, 191, 16, 305, 43 }, + { 672, 32, 191, 16, 305, 43 }, + { 815, 32, 191, 16, 305, 43 }, + { 958, 32, 191, 16, 305, 43 }, + { 1101, 32, 191, 16, 305, 43 }, + { 1244, 32, 191, 16, 305, 43 }, + { 1387, 32, 191, 16, 305, 43 }, + { 54, 32, 191, 16, 305, 43 }, + { 247, 32, 191, 16, 305, 43 }, + { 436, 32, 191, 16, 305, 43 }, + { 581, 32, 191, 16, 305, 43 }, + { 724, 32, 191, 16, 305, 43 }, + { 867, 32, 191, 16, 305, 43 }, + { 1010, 32, 191, 16, 305, 43 }, + { 1153, 32, 191, 16, 305, 43 }, + { 1296, 32, 191, 16, 305, 43 }, + { 1439, 32, 191, 16, 305, 43 }, + { 106, 32, 191, 16, 305, 43 }, + { 299, 32, 191, 16, 305, 43 }, + { 153, 47, 191, 16, 448, 33 }, + { 342, 608, 191, 16, 3824, 10 }, + { 363, 268, 185, 53, 993, 49 }, + { 506, 268, 249, 53, 993, 49 }, + { 649, 268, 140, 53, 993, 49 }, + { 792, 268, 140, 53, 993, 49 }, + { 935, 268, 140, 53, 993, 49 }, + { 1078, 268, 140, 53, 993, 49 }, + { 1221, 268, 140, 53, 993, 49 }, + { 1364, 268, 140, 53, 993, 49 }, + { 1503, 268, 140, 53, 993, 49 }, + { 27, 268, 140, 53, 993, 49 }, + { 219, 268, 140, 53, 993, 49 }, + { 408, 268, 140, 53, 993, 49 }, + { 553, 268, 140, 53, 993, 49 }, + { 696, 268, 140, 53, 993, 49 }, + { 839, 268, 140, 53, 993, 49 }, + { 982, 268, 140, 53, 993, 49 }, + { 1125, 268, 140, 53, 993, 49 }, + { 1268, 268, 140, 53, 993, 49 }, + { 1411, 268, 140, 53, 993, 49 }, + { 78, 268, 140, 53, 993, 49 }, + { 271, 268, 140, 53, 993, 49 }, + { 460, 268, 140, 53, 993, 49 }, + { 605, 268, 140, 53, 993, 49 }, + { 748, 268, 140, 53, 993, 49 }, + { 891, 268, 140, 53, 993, 49 }, + { 1034, 268, 140, 53, 993, 49 }, + { 1177, 268, 140, 53, 993, 49 }, + { 1320, 268, 140, 53, 993, 49 }, + { 1463, 268, 140, 53, 993, 49 }, + { 130, 268, 140, 53, 993, 49 }, + { 323, 268, 140, 53, 993, 49 }, + { 175, 280, 140, 53, 4080, 14 }, + { 643, 476, 4, 86, 1, 56 }, + { 786, 476, 4, 86, 1, 56 }, + { 929, 476, 4, 86, 1, 56 }, + { 1072, 476, 4, 86, 1, 56 }, + { 1215, 476, 4, 86, 1, 56 }, + { 1358, 476, 4, 86, 1, 56 }, + { 1497, 476, 4, 86, 1, 56 }, + { 21, 476, 4, 86, 1, 56 }, + { 213, 476, 4, 86, 1, 56 }, + { 401, 476, 4, 86, 1, 56 }, + { 545, 476, 4, 86, 1, 56 }, + { 688, 476, 4, 86, 1, 56 }, + { 831, 476, 4, 86, 1, 56 }, + { 974, 476, 4, 86, 1, 56 }, + { 1117, 476, 4, 86, 1, 56 }, + { 1260, 476, 4, 86, 1, 56 }, + { 1403, 476, 4, 86, 1, 56 }, + { 70, 476, 4, 86, 1, 56 }, + { 263, 476, 4, 86, 1, 56 }, + { 452, 476, 4, 86, 1, 56 }, + { 597, 476, 4, 86, 1, 56 }, + { 740, 476, 4, 86, 1, 56 }, + { 883, 476, 4, 86, 1, 56 }, + { 1026, 476, 4, 86, 1, 56 }, + { 1169, 476, 4, 86, 1, 56 }, + { 1312, 476, 4, 86, 1, 56 }, + { 1455, 476, 4, 86, 1, 56 }, + { 122, 476, 4, 86, 1, 56 }, + { 315, 476, 4, 86, 1, 56 }, + { 167, 508, 4, 86, 160, 61 }, + { 355, 365, 4, 86, 368, 47 }, + { 499, 444, 4, 86, 3216, 17 }, + { 503, 302, 261, 65, 241, 62 }, + { 646, 302, 88, 65, 241, 62 }, + { 789, 302, 88, 65, 241, 62 }, + { 932, 302, 88, 65, 241, 62 }, + { 1075, 302, 88, 65, 241, 62 }, + { 1218, 302, 88, 65, 241, 62 }, + { 1361, 302, 88, 65, 241, 62 }, + { 1500, 302, 88, 65, 241, 62 }, + { 24, 302, 88, 65, 241, 62 }, + { 216, 302, 88, 65, 241, 62 }, + { 404, 302, 88, 65, 241, 62 }, + { 549, 302, 88, 65, 241, 62 }, + { 692, 302, 88, 65, 241, 62 }, + { 835, 302, 88, 65, 241, 62 }, + { 978, 302, 88, 65, 241, 62 }, + { 1121, 302, 88, 65, 241, 62 }, + { 1264, 302, 88, 65, 241, 62 }, + { 1407, 302, 88, 65, 241, 62 }, + { 74, 302, 88, 65, 241, 62 }, + { 267, 302, 88, 65, 241, 62 }, + { 456, 302, 88, 65, 241, 62 }, + { 601, 302, 88, 65, 241, 62 }, + { 744, 302, 88, 65, 241, 62 }, + { 887, 302, 88, 65, 241, 62 }, + { 1030, 302, 88, 65, 241, 62 }, + { 1173, 302, 88, 65, 241, 62 }, + { 1316, 302, 88, 65, 241, 62 }, + { 1459, 302, 88, 65, 241, 62 }, + { 126, 302, 88, 65, 241, 62 }, + { 319, 302, 88, 65, 241, 62 }, + { 171, 323, 88, 65, 448, 52 }, + { 359, 344, 88, 65, 3824, 22 }, +}; + + // FPR8 Register Class... + static const MCPhysReg FPR8[] = { + AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31, + }; + + // FPR8 Bit set. + static const uint8_t FPR8Bits[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // FPR16 Register Class... + static const MCPhysReg FPR16[] = { + AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31, + }; + + // FPR16 Bit set. + static const uint8_t FPR16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // GPR32all Register Class... + static const MCPhysReg GPR32all[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP, + }; + + // GPR32all Bit set. + static const uint8_t GPR32allBits[] = { + 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // FPR32 Register Class... + static const MCPhysReg FPR32[] = { + AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31, + }; + + // FPR32 Bit set. + static const uint8_t FPR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // GPR32 Register Class... + static const MCPhysReg GPR32[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, + }; + + // GPR32 Bit set. + static const uint8_t GPR32Bits[] = { + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // GPR32sp Register Class... + static const MCPhysReg GPR32sp[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP, + }; + + // GPR32sp Bit set. + static const uint8_t GPR32spBits[] = { + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // GPR32common Register Class... + static const MCPhysReg GPR32common[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, + }; + + // GPR32common Bit set. + static const uint8_t GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // CCR Register Class... + static const MCPhysReg CCR[] = { + AArch64_NZCV, + }; + + // CCR Bit set. + static const uint8_t CCRBits[] = { + 0x08, + }; + + // GPR32sponly Register Class... + static const MCPhysReg GPR32sponly[] = { + AArch64_WSP, + }; + + // GPR32sponly Bit set. + static const uint8_t GPR32sponlyBits[] = { + 0x20, + }; + + // GPR64all Register Class... + static const MCPhysReg GPR64all[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP, + }; + + // GPR64all Bit set. + static const uint8_t GPR64allBits[] = { + 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + }; + + // FPR64 Register Class... + static const MCPhysReg FPR64[] = { + AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31, + }; + + // FPR64 Bit set. + static const uint8_t FPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // GPR64 Register Class... + static const MCPhysReg GPR64[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, + }; + + // GPR64 Bit set. + static const uint8_t GPR64Bits[] = { + 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + }; + + // GPR64sp Register Class... + static const MCPhysReg GPR64sp[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP, + }; + + // GPR64sp Bit set. + static const uint8_t GPR64spBits[] = { + 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + }; + + // GPR64common Register Class... + static const MCPhysReg GPR64common[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, + }; + + // GPR64common Bit set. + static const uint8_t GPR64commonBits[] = { + 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + }; + + // tcGPR64 Register Class... + static const MCPhysReg tcGPR64[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, + }; + + // tcGPR64 Bit set. + static const uint8_t tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, + }; + + // GPR64sponly Register Class... + static const MCPhysReg GPR64sponly[] = { + AArch64_SP, + }; + + // GPR64sponly Bit set. + static const uint8_t GPR64sponlyBits[] = { + 0x10, + }; + + // DD Register Class... + static const MCPhysReg DD[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0, + }; + + // DD Bit set. + static const uint8_t DDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // FPR128 Register Class... + static const MCPhysReg FPR128[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31, + }; + + // FPR128 Bit set. + static const uint8_t FPR128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // FPR128_lo Register Class... + static const MCPhysReg FPR128_lo[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, + }; + + // FPR128_lo Bit set. + static const uint8_t FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, + }; + + // DDD Register Class... + static const MCPhysReg DDD[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1, + }; + + // DDD Bit set. + static const uint8_t DDDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // DDDD Register Class... + static const MCPhysReg DDDD[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2, + }; + + // DDDD Bit set. + static const uint8_t DDDDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // QQ Register Class... + static const MCPhysReg QQ[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0, + }; + + // QQ Bit set. + static const uint8_t QQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // QQ_with_qsub0_in_FPR128_lo Register Class... + static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, + }; + + // QQ_with_qsub0_in_FPR128_lo Bit set. + static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + }; + + // QQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0, + }; + + // QQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + }; + + // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, + }; + + // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + }; + + // QQQ Register Class... + static const MCPhysReg QQQ[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, + }; + + // QQQ Bit set. + static const uint8_t QQQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // QQQ_with_qsub0_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, + }; + + // QQQ_with_qsub0_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + }; + + // QQQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1, + }; + + // QQQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + }; + + // QQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, + }; + + // QQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, + }; + + // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + }; + + // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + }; + + // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1, + }; + + // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, + }; + + // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, + }; + + // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, + }; + + // QQQQ Register Class... + static const MCPhysReg QQQQ[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ Bit set. + static const uint8_t QQQQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // QQQQ_with_qsub0_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, + }; + + // QQQQ_with_qsub0_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + }; + + // QQQQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + }; + + // QQQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, + }; + + // QQQQ_with_qsub3_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub3_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + }; + + // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, + }; + + // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, + }; + + // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2, + }; + + // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... + static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, + }; + + // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. + static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, + }; + +static MCRegisterClass AArch64MCRegisterClasses[] = { + { FPR8, FPR8Bits, 39, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 }, + { FPR16, FPR16Bits, 26, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 }, + { GPR32all, GPR32allBits, 58, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 }, + { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 }, + { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 }, + { GPR32sp, GPR32spBits, 739, 32, sizeof(GPR32spBits), AArch64_GPR32spRegClassID, 4, 4, 1, 1 }, + { GPR32common, GPR32commonBits, 76, 31, sizeof(GPR32commonBits), AArch64_GPR32commonRegClassID, 4, 4, 1, 1 }, + { CCR, CCRBits, 54, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 }, + { GPR32sponly, GPR32sponlyBits, 755, 1, sizeof(GPR32sponlyBits), AArch64_GPR32sponlyRegClassID, 4, 4, 1, 1 }, + { GPR64all, GPR64allBits, 67, 33, sizeof(GPR64allBits), AArch64_GPR64allRegClassID, 8, 8, 1, 1 }, + { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 }, + { GPR64, GPR64Bits, 20, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 }, + { GPR64sp, GPR64spBits, 747, 32, sizeof(GPR64spBits), AArch64_GPR64spRegClassID, 8, 8, 1, 1 }, + { GPR64common, GPR64commonBits, 88, 31, sizeof(GPR64commonBits), AArch64_GPR64commonRegClassID, 8, 8, 1, 1 }, + { tcGPR64, tcGPR64Bits, 18, 19, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 }, + { GPR64sponly, GPR64sponlyBits, 767, 1, sizeof(GPR64sponlyBits), AArch64_GPR64sponlyRegClassID, 8, 8, 1, 1 }, + { DD, DDBits, 46, 32, sizeof(DDBits), AArch64_DDRegClassID, 16, 8, 1, 1 }, + { FPR128, FPR128Bits, 32, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 }, + { FPR128_lo, FPR128_loBits, 119, 16, sizeof(FPR128_loBits), AArch64_FPR128_loRegClassID, 16, 16, 1, 1 }, + { DDD, DDDBits, 45, 32, sizeof(DDDBits), AArch64_DDDRegClassID, 24, 8, 1, 1 }, + { DDDD, DDDDBits, 44, 32, sizeof(DDDDBits), AArch64_DDDDRegClassID, 32, 8, 1, 1 }, + { QQ, QQBits, 51, 32, sizeof(QQBits), AArch64_QQRegClassID, 32, 16, 1, 1 }, + { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 102, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 }, + { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 164, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 }, + { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 251, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 }, + { QQQ, QQQBits, 50, 32, sizeof(QQQBits), AArch64_QQQRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 101, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 163, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 343, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 191, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 493, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 433, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, + { QQQQ, QQQQBits, 49, 32, sizeof(QQQQBits), AArch64_QQQQRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 100, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 162, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 342, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 586, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 129, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 371, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 677, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 309, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 615, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, + { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 553, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64GenSubtargetInfo.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenSubtargetInfo.inc new file mode 100644 index 0000000..d4fd4af --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64GenSubtargetInfo.inc @@ -0,0 +1,29 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + AArch64_FeatureCRC = 1ULL << 0, + AArch64_FeatureCrypto = 1ULL << 1, + AArch64_FeatureFPARMv8 = 1ULL << 2, + AArch64_FeatureNEON = 1ULL << 3, + AArch64_FeatureZCRegMove = 1ULL << 4, + AArch64_FeatureZCZeroing = 1ULL << 5, + AArch64_ProcA53 = 1ULL << 6, + AArch64_ProcA57 = 1ULL << 7, + AArch64_ProcCyclone = 1ULL << 8 +}; + +#endif // GET_SUBTARGETINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.c b/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.c new file mode 100644 index 0000000..cf6682d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.c @@ -0,0 +1,1942 @@ +//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an AArch64 MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2016 */ + +#ifdef CAPSTONE_HAS_ARM64 + +#include +#include +#include + +#include "AArch64InstPrinter.h" +#include "AArch64BaseInfo.h" +#include "../../utils.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" + +#include "AArch64Mapping.h" +#include "AArch64AddressingModes.h" + +#define GET_REGINFO_ENUM +#include "AArch64GenRegisterInfo.inc" + +#define GET_INSTRINFO_ENUM +#include "AArch64GenInstrInfo.inc" + + +static const char *getRegisterName(unsigned RegNo, int AltIdx); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static bool printSysAlias(MCInst *MI, SStream *O); +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info); +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); +static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); + +static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index) +{ +#ifndef CAPSTONE_DIET + uint8_t *arr = AArch64_get_op_access(h, id); + + if (arr[index] == CS_AC_IGNORE) + return 0; + + return arr[index]; +#else + return 0; +#endif +} + +static void set_mem_access(MCInst *MI, bool status) +{ + MI->csh->doing_mem = status; + + if (MI->csh->detail != CS_OPT_ON) + return; + + if (status) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->arm64.op_count++; + } +} + +void AArch64_printInst(MCInst *MI, SStream *O, void *Info) +{ + // Check for special encodings and print the canonical alias instead. + unsigned Opcode = MCInst_getOpcode(MI); + int LSB; + int Width; + char *mnem; + + if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) + return; + + // SBFM/UBFM should print to a nicer aliased form if possible. + if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || + Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { + MCOperand *Op0 = MCInst_getOperand(MI, 0); + MCOperand *Op1 = MCInst_getOperand(MI, 1); + MCOperand *Op2 = MCInst_getOperand(MI, 2); + MCOperand *Op3 = MCInst_getOperand(MI, 3); + + bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); + bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); + + if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { + const char *AsmMnemonic = NULL; + + switch (MCOperand_getImm(Op3)) { + default: + break; + case 7: + if (IsSigned) + AsmMnemonic = "sxtb"; + else if (!Is64Bit) + AsmMnemonic = "uxtb"; + break; + case 15: + if (IsSigned) + AsmMnemonic = "sxth"; + else if (!Is64Bit) + AsmMnemonic = "uxth"; + break; + case 31: + // *xtw is only valid for signed 64-bit operations. + if (Is64Bit && IsSigned) + AsmMnemonic = "sxtw"; + break; + } + + if (AsmMnemonic) { + SStream_concat(O, "%s\t%s, %s", AsmMnemonic, + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1)); + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); + + return; + } + } + + // All immediate shifts are aliases, implemented using the Bitfield + // instruction. In all cases the immediate shift amount shift must be in + // the range 0 to (reg.size -1). + if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { + const char *AsmMnemonic = NULL; + int shift = 0; + int immr = (int)MCOperand_getImm(Op2); + int imms = (int)MCOperand_getImm(Op3); + + if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { + AsmMnemonic = "lsl"; + shift = 31 - imms; + } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && + ((imms + 1 == immr))) { + AsmMnemonic = "lsl"; + shift = 63 - imms; + } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { + AsmMnemonic = "lsr"; + shift = immr; + } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { + AsmMnemonic = "lsr"; + shift = immr; + } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { + AsmMnemonic = "asr"; + shift = immr; + } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { + AsmMnemonic = "asr"; + shift = immr; + } + + if (AsmMnemonic) { + SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic, + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + + printInt32Bang(O, shift); + + MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + } + + // SBFIZ/UBFIZ aliases + if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { + SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); + SStream_concat0(O, ", "); + printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); + + MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + // Otherwise SBFX/UBFX is the preferred form + SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + printInt32Bang(O, (int)MCOperand_getImm(Op2)); + SStream_concat0(O, ", "); + printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); + + MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { + MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 + MCOperand *Op2 = MCInst_getOperand(MI, 2); + int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); + int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); + + // BFI alias + if (ImmS < ImmR) { + int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; + LSB = (BitWidth - ImmR) % BitWidth; + Width = ImmS + 1; + + SStream_concat(O, "bfi\t%s, %s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + LSB = ImmR; + Width = ImmS - ImmR + 1; + // Otherwise BFXIL the preferred form + SStream_concat(O, "bfxil\t%s, %s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + mnem = printAliasInstr(MI, O, Info); + if (mnem) { + MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); + cs_mem_free(mnem); + } else { + printInstruction(MI, O, Info); + } +} + +static bool printSysAlias(MCInst *MI, SStream *O) +{ + // unsigned Opcode = MCInst_getOpcode(MI); + //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); + + const char *Asm = NULL; + MCOperand *Op1 = MCInst_getOperand(MI, 0); + MCOperand *Cn = MCInst_getOperand(MI, 1); + MCOperand *Cm = MCInst_getOperand(MI, 2); + MCOperand *Op2 = MCInst_getOperand(MI, 3); + + unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); + unsigned CnVal = (unsigned)MCOperand_getImm(Cn); + unsigned CmVal = (unsigned)MCOperand_getImm(Cm); + unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); + unsigned insn_id = ARM64_INS_INVALID; + unsigned op_ic = 0, op_dc = 0, op_at = 0, op_tlbi = 0; + + if (CnVal == 7) { + switch (CmVal) { + default: + break; + + // IC aliases + case 1: + if (Op1Val == 0 && Op2Val == 0) { + Asm = "ic\tialluis"; + insn_id = ARM64_INS_IC; + op_ic = ARM64_IC_IALLUIS; + } + break; + case 5: + if (Op1Val == 0 && Op2Val == 0) { + Asm = "ic\tiallu"; + insn_id = ARM64_INS_IC; + op_ic = ARM64_IC_IALLU; + } else if (Op1Val == 3 && Op2Val == 1) { + Asm = "ic\tivau"; + insn_id = ARM64_INS_IC; + op_ic = ARM64_IC_IVAU; + } + break; + + // DC aliases + case 4: + if (Op1Val == 3 && Op2Val == 1) { + Asm = "dc\tzva"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_ZVA; + } + break; + case 6: + if (Op1Val == 0 && Op2Val == 1) { + Asm = "dc\tivac"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_IVAC; + } + if (Op1Val == 0 && Op2Val == 2) { + Asm = "dc\tisw"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_ISW; + } + break; + case 10: + if (Op1Val == 3 && Op2Val == 1) { + Asm = "dc\tcvac"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_CVAC; + } else if (Op1Val == 0 && Op2Val == 2) { + Asm = "dc\tcsw"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_CSW; + } + break; + case 11: + if (Op1Val == 3 && Op2Val == 1) { + Asm = "dc\tcvau"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_CVAU; + } + break; + case 14: + if (Op1Val == 3 && Op2Val == 1) { + Asm = "dc\tcivac"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_CIVAC; + } else if (Op1Val == 0 && Op2Val == 2) { + Asm = "dc\tcisw"; + insn_id = ARM64_INS_DC; + op_dc = ARM64_DC_CISW; + } + break; + + // AT aliases + case 8: + switch (Op1Val) { + default: + break; + case 0: + switch (Op2Val) { + default: + break; + case 0: Asm = "at\ts1e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; + case 1: Asm = "at\ts1e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; + case 2: Asm = "at\ts1e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; + case 3: Asm = "at\ts1e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; + } + break; + case 4: + switch (Op2Val) { + default: + break; + case 0: Asm = "at\ts1e2r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2R; break; + case 1: Asm = "at\ts1e2w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2W; break; + case 4: Asm = "at\ts12e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; + case 5: Asm = "at\ts12e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; + case 6: Asm = "at\ts12e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; + case 7: Asm = "at\ts12e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; + } + break; + case 6: + switch (Op2Val) { + default: + break; + case 0: Asm = "at\ts1e3r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3R; break; + case 1: Asm = "at\ts1e3w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3W; break; + } + break; + } + break; + } + } else if (CnVal == 8) { + // TLBI aliases + switch (CmVal) { + default: + break; + case 3: + switch (Op1Val) { + default: + break; + case 0: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\tvmalle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1IS; break; + case 1: Asm = "tlbi\tvae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1IS; break; + case 2: Asm = "tlbi\taside1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1IS; break; + case 3: Asm = "tlbi\tvaae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1IS; break; + case 5: Asm = "tlbi\tvale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1IS; break; + case 7: Asm = "tlbi\tvaale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1IS; break; + } + break; + case 4: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\talle2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2IS; break; + case 1: Asm = "tlbi\tvae2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2IS; break; + case 4: Asm = "tlbi\talle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1IS; break; + case 5: Asm = "tlbi\tvale2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2IS; break; + case 6: Asm = "tlbi\tvmalls12e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1IS; break; + } + break; + case 6: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\talle3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3IS; break; + case 1: Asm = "tlbi\tvae3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3IS; break; + case 5: Asm = "tlbi\tvale3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3IS; break; + } + break; + } + break; + case 0: + switch (Op1Val) { + default: + break; + case 4: + switch (Op2Val) { + default: + break; + case 1: Asm = "tlbi\tipas2e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1IS; break; + case 5: Asm = "tlbi\tipas2le1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1IS; break; + } + break; + } + break; + case 4: + switch (Op1Val) { + default: + break; + case 4: + switch (Op2Val) { + default: + break; + case 1: Asm = "tlbi\tipas2e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1; break; + case 5: Asm = "tlbi\tipas2le1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1; break; + } + break; + } + break; + case 7: + switch (Op1Val) { + default: + break; + case 0: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\tvmalle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1; break; + case 1: Asm = "tlbi\tvae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1; break; + case 2: Asm = "tlbi\taside1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1; break; + case 3: Asm = "tlbi\tvaae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1; break; + case 5: Asm = "tlbi\tvale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1; break; + case 7: Asm = "tlbi\tvaale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1; break; + } + break; + case 4: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\talle2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2; break; + case 1: Asm = "tlbi\tvae2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2; break; + case 4: Asm = "tlbi\talle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1; break; + case 5: Asm = "tlbi\tvale2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2; break; + case 6: Asm = "tlbi\tvmalls12e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1; break; + } + break; + case 6: + switch (Op2Val) { + default: + break; + case 0: Asm = "tlbi\talle3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3; break; + case 1: Asm = "tlbi\tvae3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3; break; + case 5: Asm = "tlbi\tvale3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3; break; + } + break; + } + break; + } + } + + if (Asm) { + MCInst_setOpcodePub(MI, insn_id); + SStream_concat0(O, Asm); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = op_ic + op_dc + op_at + op_tlbi; + MI->flat_insn->detail->arm64.op_count++; + } + + if (!strstr(Asm, "all")) { + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); + SStream_concat(O, ", %s", getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + } + } + + return Asm != NULL; +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; + } + else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; + } + } else { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op); + + if (MI->Opcode == AArch64_ADR) { + imm += MI->address; + printUInt64Bang(O, imm); + } else { + if (MI->csh->doing_mem) { + if (MI->csh->imm_unsigned) { + printUInt64Bang(O, imm); + } else { + printInt64Bang(O, imm); + } + } else + printUInt64Bang(O, imm); + } + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm; + } else { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + } + } +} + +static void printHexImm(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + SStream_concat(O, "#%#llx", MCOperand_getImm(Op)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printPostIncOperand(MCInst *MI, unsigned OpNo, + unsigned Imm, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + if (Reg == AArch64_XZR) { + printInt32Bang(O, Imm); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + } + } + //llvm_unreachable("unknown operand kind in printPostIncOperand64"); +} + +static void printPostIncOperand2(MCInst *MI, unsigned OpNo, SStream *O, int Amount) +{ + printPostIncOperand(MI, OpNo, Amount, O); +} + +static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + //assert(Op.isReg() && "Non-register vreg operand!"); + unsigned Reg = MCOperand_getReg(Op); + SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); + SStream_concat(O, "c%u", MCOperand_getImm(Op)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + if (MCOperand_isImm(MO)) { + unsigned Val = (MCOperand_getImm(MO) & 0xfff); + //assert(Val == MO.getImm() && "Add/sub immediate out of range!"); + unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); + + printInt32Bang(O, Val); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } + + if (Shift != 0) + printShifter(MI, OpNum + 1, O); + } +} + +static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) +{ + int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + Val = AArch64_AM_decodeLogicalImmediate(Val, 32); + printUInt32Bang(O, (int)Val); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) +{ + int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + Val = AArch64_AM_decodeLogicalImmediate(Val, 64); + + switch(MI->flat_insn->id) { + default: + printInt64Bang(O, Val); + break; + case ARM64_INS_ORR: + case ARM64_INS_AND: + case ARM64_INS_EOR: + case ARM64_INS_TST: + // do not print number in negative form + if (Val >= 0 && Val <= HEX_THRESHOLD) + SStream_concat(O, "#%u", (int)Val); + else + SStream_concat(O, "#0x%"PRIx64, Val); + break; + } + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + // LSL #0 should not be printed. + if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && + AArch64_AM_getShiftValue(Val) == 0) + return; + + SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); + printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); + if (MI->csh->detail) { + arm64_shifter shifter = ARM64_SFT_INVALID; + switch(AArch64_AM_getShiftType(Val)) { + default: // never reach + case AArch64_AM_LSL: + shifter = ARM64_SFT_LSL; + break; + case AArch64_AM_LSR: + shifter = ARM64_SFT_LSR; + break; + case AArch64_AM_ASR: + shifter = ARM64_SFT_ASR; + break; + case AArch64_AM_ROR: + shifter = ARM64_SFT_ROR; + break; + case AArch64_AM_MSL: + shifter = ARM64_SFT_MSL; + break; + } + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val); + } +} + +static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) +{ + SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + MI->flat_insn->detail->arm64.op_count++; + } + printShifter(MI, OpNum + 1, O); +} + +static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); + unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); + + // If the destination or first source register operand is [W]SP, print + // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at + // all. + if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { + unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); + unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); + if ( ((Dest == AArch64_SP || Src1 == AArch64_SP) && + ExtType == AArch64_AM_UXTX) || + ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && + ExtType == AArch64_AM_UXTW) ) { + if (ShiftVal != 0) { + SStream_concat0(O, ", lsl "); + printInt32Bang(O, ShiftVal); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; + } + } + + return; + } + } + + SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); + if (MI->csh->detail) { + arm64_extender ext = ARM64_EXT_INVALID; + switch(ExtType) { + default: // never reach + case AArch64_AM_UXTB: + ext = ARM64_EXT_UXTB; + break; + case AArch64_AM_UXTH: + ext = ARM64_EXT_UXTH; + break; + case AArch64_AM_UXTW: + ext = ARM64_EXT_UXTW; + break; + case AArch64_AM_UXTX: + ext = ARM64_EXT_UXTX; + break; + case AArch64_AM_SXTB: + ext = ARM64_EXT_SXTB; + break; + case AArch64_AM_SXTH: + ext = ARM64_EXT_SXTH; + break; + case AArch64_AM_SXTW: + ext = ARM64_EXT_SXTW; + break; + case AArch64_AM_SXTX: + ext = ARM64_EXT_SXTX; + break; + } + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; + } + + if (ShiftVal != 0) { + SStream_concat0(O, " "); + printInt32Bang(O, ShiftVal); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; + } + } +} + +static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + + printArithExtend(MI, OpNum + 1, O); +} + +static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width) +{ + unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + + // sxtw, sxtx, uxtw or lsl (== uxtx) + bool IsLSL = !SignExtend && SrcRegKind == 'x'; + if (IsLSL) { + SStream_concat0(O, "lsl"); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; + } + } else { + SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); + if (MI->csh->detail) { + if (!SignExtend) { + switch(SrcRegKind) { + default: break; + case 'b': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; + break; + case 'h': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; + break; + case 'w': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; + break; + } + } else { + switch(SrcRegKind) { + default: break; + case 'b': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; + break; + case 'h': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; + break; + case 'w': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; + break; + case 'x': + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; + break; + } + } + } + } + + if (DoShift || IsLSL) { + SStream_concat(O, " #%u", Log2_32(Width / 8)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); + } + } +} + +static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) +{ + A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getCondCodeName(CC)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); +} + +static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) +{ + A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); + } +} + +static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) +{ + int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printInt64Bang(O, val); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; + } else { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; + MI->flat_insn->detail->arm64.op_count++; + } + } +} + +static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + + if (MCOperand_isImm(MO)) { + int64_t val = Scale * MCOperand_getImm(MO); + printInt64Bang(O, val); + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; + } else { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val; + MI->flat_insn->detail->arm64.op_count++; + } + } + } +} + +static void printUImm12Offset2(MCInst *MI, unsigned OpNum, SStream *O, int Scale) +{ + printUImm12Offset(MI, OpNum, Scale, O); +} + +static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + bool Valid; + const char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid); + + if (Valid) { + SStream_concat0(O, Name); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PREFETCH; + // we have to plus 1 to prfop because 0 is a valid value of prfop + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].prefetch = prfop + 1; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + printInt32Bang(O, prfop); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; + MI->flat_insn->detail->arm64.op_count++; + } + } +} + +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + double FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); + + // 8 decimal places are enough to perfectly represent permitted floats. +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + SStream_concat(O, "#"); +#else + SStream_concat(O, "#%.8f", FPImm); +#endif + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; + MI->flat_insn->detail->arm64.op_count++; + } +} + +//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) +static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) +{ + while (Stride--) { + switch (Reg) { + default: + // llvm_unreachable("Vector register expected!"); + case AArch64_Q0: Reg = AArch64_Q1; break; + case AArch64_Q1: Reg = AArch64_Q2; break; + case AArch64_Q2: Reg = AArch64_Q3; break; + case AArch64_Q3: Reg = AArch64_Q4; break; + case AArch64_Q4: Reg = AArch64_Q5; break; + case AArch64_Q5: Reg = AArch64_Q6; break; + case AArch64_Q6: Reg = AArch64_Q7; break; + case AArch64_Q7: Reg = AArch64_Q8; break; + case AArch64_Q8: Reg = AArch64_Q9; break; + case AArch64_Q9: Reg = AArch64_Q10; break; + case AArch64_Q10: Reg = AArch64_Q11; break; + case AArch64_Q11: Reg = AArch64_Q12; break; + case AArch64_Q12: Reg = AArch64_Q13; break; + case AArch64_Q13: Reg = AArch64_Q14; break; + case AArch64_Q14: Reg = AArch64_Q15; break; + case AArch64_Q15: Reg = AArch64_Q16; break; + case AArch64_Q16: Reg = AArch64_Q17; break; + case AArch64_Q17: Reg = AArch64_Q18; break; + case AArch64_Q18: Reg = AArch64_Q19; break; + case AArch64_Q19: Reg = AArch64_Q20; break; + case AArch64_Q20: Reg = AArch64_Q21; break; + case AArch64_Q21: Reg = AArch64_Q22; break; + case AArch64_Q22: Reg = AArch64_Q23; break; + case AArch64_Q23: Reg = AArch64_Q24; break; + case AArch64_Q24: Reg = AArch64_Q25; break; + case AArch64_Q25: Reg = AArch64_Q26; break; + case AArch64_Q26: Reg = AArch64_Q27; break; + case AArch64_Q27: Reg = AArch64_Q28; break; + case AArch64_Q28: Reg = AArch64_Q29; break; + case AArch64_Q29: Reg = AArch64_Q30; break; + case AArch64_Q30: Reg = AArch64_Q31; break; + // Vector lists can wrap around. + case AArch64_Q31: Reg = AArch64_Q0; break; + } + } + + return Reg; +} + +static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess) +{ +#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) + + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned NumRegs = 1, FirstReg, i; + + SStream_concat0(O, "{"); + + // Work out how many registers there are in the list (if there is an actual + // list). + if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) + NumRegs = 2; + else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) + NumRegs = 3; + else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) + NumRegs = 4; + + // Now forget about the list and find out what the first register is. + if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) + Reg = FirstReg; + else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) + Reg = FirstReg; + + // If it's a D-reg, we need to promote it to the equivalent Q-reg before + // printing (otherwise getRegisterName fails). + if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { + const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); + Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); + } + + for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { + SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); + if (i + 1 != NumRegs) + SStream_concat0(O, ", "); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess; + MI->flat_insn->detail->arm64.op_count++; + } + } + + SStream_concat0(O, "}"); +} + +static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI) +{ + char Suffix[32]; + arm64_vas vas = 0; + arm64_vess vess = 0; + + if (NumLanes) { + cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); + switch(LaneKind) { + default: break; + case 'b': + switch(NumLanes) { + default: break; + case 8: + vas = ARM64_VAS_8B; + break; + case 16: + vas = ARM64_VAS_16B; + break; + } + break; + case 'h': + switch(NumLanes) { + default: break; + case 4: + vas = ARM64_VAS_4H; + break; + case 8: + vas = ARM64_VAS_8H; + break; + } + break; + case 's': + switch(NumLanes) { + default: break; + case 2: + vas = ARM64_VAS_2S; + break; + case 4: + vas = ARM64_VAS_4S; + break; + } + break; + case 'd': + switch(NumLanes) { + default: break; + case 1: + vas = ARM64_VAS_1D; + break; + case 2: + vas = ARM64_VAS_2D; + break; + } + break; + case 'q': + switch(NumLanes) { + default: break; + case 1: + vas = ARM64_VAS_1Q; + break; + } + break; + } + } else { + cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); + switch(LaneKind) { + default: break; + case 'b': + vess = ARM64_VESS_B; + break; + case 'h': + vess = ARM64_VESS_H; + break; + case 's': + vess = ARM64_VESS_S; + break; + case 'd': + vess = ARM64_VESS_D; + break; + } + } + + printVectorList(MI, OpNum, O, Suffix, MRI, vas, vess); +} + +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) +{ + SStream_concat0(O, "["); + printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); + SStream_concat0(O, "]"); + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + } +} + +static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + + // If the label has already been resolved to an immediate offset (say, when + // we're running the disassembler), just print the immediate. + if (MCOperand_isImm(Op)) { + uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; + printUInt64Bang(O, imm); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + return; + } +} + +static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + + if (MCOperand_isImm(Op)) { + // ADRP sign extends a 21-bit offset, shifts it left by 12 + // and adds it to the value of the PC with its bottom 12 bits cleared + uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff); + printUInt64Bang(O, imm); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + return; + } +} + +static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + unsigned Opcode = MCInst_getOpcode(MI); + bool Valid; + const char *Name; + + if (Opcode == AArch64_ISB) + Name = A64NamedImmMapper_toString(&A64ISB_ISBMapper, Val, &Valid); + else + Name = A64NamedImmMapper_toString(&A64DB_DBarrierMapper, Val, &Valid); + + if (Valid) { + SStream_concat0(O, Name); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + printUInt32Bang(O, Val); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } +} + +static void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + char Name[128]; + + A64SysRegMapper_toString(&AArch64_MRSMapper, Val, Name); + + SStream_concat0(O, Name); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + char Name[128]; + + A64SysRegMapper_toString(&AArch64_MSRMapper, Val, Name); + + SStream_concat0(O, Name); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MSR; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + bool Valid; + const char *Name; + + Name = A64NamedImmMapper_toString(&A64PState_PStateMapper, Val, &Valid); + if (Valid) { + SStream_concat0(O, Name); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } else { +#ifndef CAPSTONE_DIET + unsigned char access; +#endif + printInt32Bang(O, Val); +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + +static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O) +{ + uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); + SStream_concat(O, "#%#016llx", Val); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + unsigned char access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } +} + + +#define PRINT_ALIAS_INSTR +#include "AArch64GenAsmWriter.inc" + +void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) +{ + if (((cs_struct *)handle)->detail != CS_OPT_ON) + return; + + if (mci->csh->detail) { + unsigned opcode = MCInst_getOpcode(mci); + switch (opcode) { + default: + break; + case AArch64_LD1Fourv16b_POST: + case AArch64_LD1Fourv1d_POST: + case AArch64_LD1Fourv2d_POST: + case AArch64_LD1Fourv2s_POST: + case AArch64_LD1Fourv4h_POST: + case AArch64_LD1Fourv4s_POST: + case AArch64_LD1Fourv8b_POST: + case AArch64_LD1Fourv8h_POST: + case AArch64_LD1Onev16b_POST: + case AArch64_LD1Onev1d_POST: + case AArch64_LD1Onev2d_POST: + case AArch64_LD1Onev2s_POST: + case AArch64_LD1Onev4h_POST: + case AArch64_LD1Onev4s_POST: + case AArch64_LD1Onev8b_POST: + case AArch64_LD1Onev8h_POST: + case AArch64_LD1Rv16b_POST: + case AArch64_LD1Rv1d_POST: + case AArch64_LD1Rv2d_POST: + case AArch64_LD1Rv2s_POST: + case AArch64_LD1Rv4h_POST: + case AArch64_LD1Rv4s_POST: + case AArch64_LD1Rv8b_POST: + case AArch64_LD1Rv8h_POST: + case AArch64_LD1Threev16b_POST: + case AArch64_LD1Threev1d_POST: + case AArch64_LD1Threev2d_POST: + case AArch64_LD1Threev2s_POST: + case AArch64_LD1Threev4h_POST: + case AArch64_LD1Threev4s_POST: + case AArch64_LD1Threev8b_POST: + case AArch64_LD1Threev8h_POST: + case AArch64_LD1Twov16b_POST: + case AArch64_LD1Twov1d_POST: + case AArch64_LD1Twov2d_POST: + case AArch64_LD1Twov2s_POST: + case AArch64_LD1Twov4h_POST: + case AArch64_LD1Twov4s_POST: + case AArch64_LD1Twov8b_POST: + case AArch64_LD1Twov8h_POST: + case AArch64_LD1i16_POST: + case AArch64_LD1i32_POST: + case AArch64_LD1i64_POST: + case AArch64_LD1i8_POST: + case AArch64_LD2Rv16b_POST: + case AArch64_LD2Rv1d_POST: + case AArch64_LD2Rv2d_POST: + case AArch64_LD2Rv2s_POST: + case AArch64_LD2Rv4h_POST: + case AArch64_LD2Rv4s_POST: + case AArch64_LD2Rv8b_POST: + case AArch64_LD2Rv8h_POST: + case AArch64_LD2Twov16b_POST: + case AArch64_LD2Twov2d_POST: + case AArch64_LD2Twov2s_POST: + case AArch64_LD2Twov4h_POST: + case AArch64_LD2Twov4s_POST: + case AArch64_LD2Twov8b_POST: + case AArch64_LD2Twov8h_POST: + case AArch64_LD2i16_POST: + case AArch64_LD2i32_POST: + case AArch64_LD2i64_POST: + case AArch64_LD2i8_POST: + case AArch64_LD3Rv16b_POST: + case AArch64_LD3Rv1d_POST: + case AArch64_LD3Rv2d_POST: + case AArch64_LD3Rv2s_POST: + case AArch64_LD3Rv4h_POST: + case AArch64_LD3Rv4s_POST: + case AArch64_LD3Rv8b_POST: + case AArch64_LD3Rv8h_POST: + case AArch64_LD3Threev16b_POST: + case AArch64_LD3Threev2d_POST: + case AArch64_LD3Threev2s_POST: + case AArch64_LD3Threev4h_POST: + case AArch64_LD3Threev4s_POST: + case AArch64_LD3Threev8b_POST: + case AArch64_LD3Threev8h_POST: + case AArch64_LD3i16_POST: + case AArch64_LD3i32_POST: + case AArch64_LD3i64_POST: + case AArch64_LD3i8_POST: + case AArch64_LD4Fourv16b_POST: + case AArch64_LD4Fourv2d_POST: + case AArch64_LD4Fourv2s_POST: + case AArch64_LD4Fourv4h_POST: + case AArch64_LD4Fourv4s_POST: + case AArch64_LD4Fourv8b_POST: + case AArch64_LD4Fourv8h_POST: + case AArch64_LD4Rv16b_POST: + case AArch64_LD4Rv1d_POST: + case AArch64_LD4Rv2d_POST: + case AArch64_LD4Rv2s_POST: + case AArch64_LD4Rv4h_POST: + case AArch64_LD4Rv4s_POST: + case AArch64_LD4Rv8b_POST: + case AArch64_LD4Rv8h_POST: + case AArch64_LD4i16_POST: + case AArch64_LD4i32_POST: + case AArch64_LD4i64_POST: + case AArch64_LD4i8_POST: + case AArch64_LDPDpost: + case AArch64_LDPDpre: + case AArch64_LDPQpost: + case AArch64_LDPQpre: + case AArch64_LDPSWpost: + case AArch64_LDPSWpre: + case AArch64_LDPSpost: + case AArch64_LDPSpre: + case AArch64_LDPWpost: + case AArch64_LDPWpre: + case AArch64_LDPXpost: + case AArch64_LDPXpre: + case AArch64_LDRBBpost: + case AArch64_LDRBBpre: + case AArch64_LDRBpost: + case AArch64_LDRBpre: + case AArch64_LDRDpost: + case AArch64_LDRDpre: + case AArch64_LDRHHpost: + case AArch64_LDRHHpre: + case AArch64_LDRHpost: + case AArch64_LDRHpre: + case AArch64_LDRQpost: + case AArch64_LDRQpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSBWpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHWpost: + case AArch64_LDRSHWpre: + case AArch64_LDRSHXpost: + case AArch64_LDRSHXpre: + case AArch64_LDRSWpost: + case AArch64_LDRSWpre: + case AArch64_LDRSpost: + case AArch64_LDRSpre: + case AArch64_LDRWpost: + case AArch64_LDRWpre: + case AArch64_LDRXpost: + case AArch64_LDRXpre: + case AArch64_ST1Fourv16b_POST: + case AArch64_ST1Fourv1d_POST: + case AArch64_ST1Fourv2d_POST: + case AArch64_ST1Fourv2s_POST: + case AArch64_ST1Fourv4h_POST: + case AArch64_ST1Fourv4s_POST: + case AArch64_ST1Fourv8b_POST: + case AArch64_ST1Fourv8h_POST: + case AArch64_ST1Onev16b_POST: + case AArch64_ST1Onev1d_POST: + case AArch64_ST1Onev2d_POST: + case AArch64_ST1Onev2s_POST: + case AArch64_ST1Onev4h_POST: + case AArch64_ST1Onev4s_POST: + case AArch64_ST1Onev8b_POST: + case AArch64_ST1Onev8h_POST: + case AArch64_ST1Threev16b_POST: + case AArch64_ST1Threev1d_POST: + case AArch64_ST1Threev2d_POST: + case AArch64_ST1Threev2s_POST: + case AArch64_ST1Threev4h_POST: + case AArch64_ST1Threev4s_POST: + case AArch64_ST1Threev8b_POST: + case AArch64_ST1Threev8h_POST: + case AArch64_ST1Twov16b_POST: + case AArch64_ST1Twov1d_POST: + case AArch64_ST1Twov2d_POST: + case AArch64_ST1Twov2s_POST: + case AArch64_ST1Twov4h_POST: + case AArch64_ST1Twov4s_POST: + case AArch64_ST1Twov8b_POST: + case AArch64_ST1Twov8h_POST: + case AArch64_ST1i16_POST: + case AArch64_ST1i32_POST: + case AArch64_ST1i64_POST: + case AArch64_ST1i8_POST: + case AArch64_ST2Twov16b_POST: + case AArch64_ST2Twov2d_POST: + case AArch64_ST2Twov2s_POST: + case AArch64_ST2Twov4h_POST: + case AArch64_ST2Twov4s_POST: + case AArch64_ST2Twov8b_POST: + case AArch64_ST2Twov8h_POST: + case AArch64_ST2i16_POST: + case AArch64_ST2i32_POST: + case AArch64_ST2i64_POST: + case AArch64_ST2i8_POST: + case AArch64_ST3Threev16b_POST: + case AArch64_ST3Threev2d_POST: + case AArch64_ST3Threev2s_POST: + case AArch64_ST3Threev4h_POST: + case AArch64_ST3Threev4s_POST: + case AArch64_ST3Threev8b_POST: + case AArch64_ST3Threev8h_POST: + case AArch64_ST3i16_POST: + case AArch64_ST3i32_POST: + case AArch64_ST3i64_POST: + case AArch64_ST3i8_POST: + case AArch64_ST4Fourv16b_POST: + case AArch64_ST4Fourv2d_POST: + case AArch64_ST4Fourv2s_POST: + case AArch64_ST4Fourv4h_POST: + case AArch64_ST4Fourv4s_POST: + case AArch64_ST4Fourv8b_POST: + case AArch64_ST4Fourv8h_POST: + case AArch64_ST4i16_POST: + case AArch64_ST4i32_POST: + case AArch64_ST4i64_POST: + case AArch64_ST4i8_POST: + case AArch64_STPDpost: + case AArch64_STPDpre: + case AArch64_STPQpost: + case AArch64_STPQpre: + case AArch64_STPSpost: + case AArch64_STPSpre: + case AArch64_STPWpost: + case AArch64_STPWpre: + case AArch64_STPXpost: + case AArch64_STPXpre: + case AArch64_STRBBpost: + case AArch64_STRBBpre: + case AArch64_STRBpost: + case AArch64_STRBpre: + case AArch64_STRDpost: + case AArch64_STRDpre: + case AArch64_STRHHpost: + case AArch64_STRHHpre: + case AArch64_STRHpost: + case AArch64_STRHpre: + case AArch64_STRQpost: + case AArch64_STRQpre: + case AArch64_STRSpost: + case AArch64_STRSpre: + case AArch64_STRWpost: + case AArch64_STRWpre: + case AArch64_STRXpost: + case AArch64_STRXpre: + flat_insn->detail->arm64.writeback = true; + break; + } + } +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.h new file mode 100644 index 0000000..88b02bb --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64InstPrinter.h @@ -0,0 +1,28 @@ +//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an AArch64 MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_LLVM_AARCH64INSTPRINTER_H +#define CS_LLVM_AARCH64INSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void AArch64_printInst(MCInst *MI, SStream *O, void *); + +void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.c b/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.c new file mode 100644 index 0000000..4579a08 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.c @@ -0,0 +1,1079 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_ARM64 + +#include // debug +#include + +#include "../../utils.h" + +#include "AArch64Mapping.h" + +#define GET_INSTRINFO_ENUM +#include "AArch64GenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { ARM64_REG_INVALID, NULL }, + + { ARM64_REG_X29, "x29"}, + { ARM64_REG_X30, "x30"}, + { ARM64_REG_NZCV, "nzcv"}, + { ARM64_REG_SP, "sp"}, + { ARM64_REG_WSP, "wsp"}, + { ARM64_REG_WZR, "wzr"}, + { ARM64_REG_XZR, "xzr"}, + { ARM64_REG_B0, "b0"}, + { ARM64_REG_B1, "b1"}, + { ARM64_REG_B2, "b2"}, + { ARM64_REG_B3, "b3"}, + { ARM64_REG_B4, "b4"}, + { ARM64_REG_B5, "b5"}, + { ARM64_REG_B6, "b6"}, + { ARM64_REG_B7, "b7"}, + { ARM64_REG_B8, "b8"}, + { ARM64_REG_B9, "b9"}, + { ARM64_REG_B10, "b10"}, + { ARM64_REG_B11, "b11"}, + { ARM64_REG_B12, "b12"}, + { ARM64_REG_B13, "b13"}, + { ARM64_REG_B14, "b14"}, + { ARM64_REG_B15, "b15"}, + { ARM64_REG_B16, "b16"}, + { ARM64_REG_B17, "b17"}, + { ARM64_REG_B18, "b18"}, + { ARM64_REG_B19, "b19"}, + { ARM64_REG_B20, "b20"}, + { ARM64_REG_B21, "b21"}, + { ARM64_REG_B22, "b22"}, + { ARM64_REG_B23, "b23"}, + { ARM64_REG_B24, "b24"}, + { ARM64_REG_B25, "b25"}, + { ARM64_REG_B26, "b26"}, + { ARM64_REG_B27, "b27"}, + { ARM64_REG_B28, "b28"}, + { ARM64_REG_B29, "b29"}, + { ARM64_REG_B30, "b30"}, + { ARM64_REG_B31, "b31"}, + { ARM64_REG_D0, "d0"}, + { ARM64_REG_D1, "d1"}, + { ARM64_REG_D2, "d2"}, + { ARM64_REG_D3, "d3"}, + { ARM64_REG_D4, "d4"}, + { ARM64_REG_D5, "d5"}, + { ARM64_REG_D6, "d6"}, + { ARM64_REG_D7, "d7"}, + { ARM64_REG_D8, "d8"}, + { ARM64_REG_D9, "d9"}, + { ARM64_REG_D10, "d10"}, + { ARM64_REG_D11, "d11"}, + { ARM64_REG_D12, "d12"}, + { ARM64_REG_D13, "d13"}, + { ARM64_REG_D14, "d14"}, + { ARM64_REG_D15, "d15"}, + { ARM64_REG_D16, "d16"}, + { ARM64_REG_D17, "d17"}, + { ARM64_REG_D18, "d18"}, + { ARM64_REG_D19, "d19"}, + { ARM64_REG_D20, "d20"}, + { ARM64_REG_D21, "d21"}, + { ARM64_REG_D22, "d22"}, + { ARM64_REG_D23, "d23"}, + { ARM64_REG_D24, "d24"}, + { ARM64_REG_D25, "d25"}, + { ARM64_REG_D26, "d26"}, + { ARM64_REG_D27, "d27"}, + { ARM64_REG_D28, "d28"}, + { ARM64_REG_D29, "d29"}, + { ARM64_REG_D30, "d30"}, + { ARM64_REG_D31, "d31"}, + { ARM64_REG_H0, "h0"}, + { ARM64_REG_H1, "h1"}, + { ARM64_REG_H2, "h2"}, + { ARM64_REG_H3, "h3"}, + { ARM64_REG_H4, "h4"}, + { ARM64_REG_H5, "h5"}, + { ARM64_REG_H6, "h6"}, + { ARM64_REG_H7, "h7"}, + { ARM64_REG_H8, "h8"}, + { ARM64_REG_H9, "h9"}, + { ARM64_REG_H10, "h10"}, + { ARM64_REG_H11, "h11"}, + { ARM64_REG_H12, "h12"}, + { ARM64_REG_H13, "h13"}, + { ARM64_REG_H14, "h14"}, + { ARM64_REG_H15, "h15"}, + { ARM64_REG_H16, "h16"}, + { ARM64_REG_H17, "h17"}, + { ARM64_REG_H18, "h18"}, + { ARM64_REG_H19, "h19"}, + { ARM64_REG_H20, "h20"}, + { ARM64_REG_H21, "h21"}, + { ARM64_REG_H22, "h22"}, + { ARM64_REG_H23, "h23"}, + { ARM64_REG_H24, "h24"}, + { ARM64_REG_H25, "h25"}, + { ARM64_REG_H26, "h26"}, + { ARM64_REG_H27, "h27"}, + { ARM64_REG_H28, "h28"}, + { ARM64_REG_H29, "h29"}, + { ARM64_REG_H30, "h30"}, + { ARM64_REG_H31, "h31"}, + { ARM64_REG_Q0, "q0"}, + { ARM64_REG_Q1, "q1"}, + { ARM64_REG_Q2, "q2"}, + { ARM64_REG_Q3, "q3"}, + { ARM64_REG_Q4, "q4"}, + { ARM64_REG_Q5, "q5"}, + { ARM64_REG_Q6, "q6"}, + { ARM64_REG_Q7, "q7"}, + { ARM64_REG_Q8, "q8"}, + { ARM64_REG_Q9, "q9"}, + { ARM64_REG_Q10, "q10"}, + { ARM64_REG_Q11, "q11"}, + { ARM64_REG_Q12, "q12"}, + { ARM64_REG_Q13, "q13"}, + { ARM64_REG_Q14, "q14"}, + { ARM64_REG_Q15, "q15"}, + { ARM64_REG_Q16, "q16"}, + { ARM64_REG_Q17, "q17"}, + { ARM64_REG_Q18, "q18"}, + { ARM64_REG_Q19, "q19"}, + { ARM64_REG_Q20, "q20"}, + { ARM64_REG_Q21, "q21"}, + { ARM64_REG_Q22, "q22"}, + { ARM64_REG_Q23, "q23"}, + { ARM64_REG_Q24, "q24"}, + { ARM64_REG_Q25, "q25"}, + { ARM64_REG_Q26, "q26"}, + { ARM64_REG_Q27, "q27"}, + { ARM64_REG_Q28, "q28"}, + { ARM64_REG_Q29, "q29"}, + { ARM64_REG_Q30, "q30"}, + { ARM64_REG_Q31, "q31"}, + { ARM64_REG_S0, "s0"}, + { ARM64_REG_S1, "s1"}, + { ARM64_REG_S2, "s2"}, + { ARM64_REG_S3, "s3"}, + { ARM64_REG_S4, "s4"}, + { ARM64_REG_S5, "s5"}, + { ARM64_REG_S6, "s6"}, + { ARM64_REG_S7, "s7"}, + { ARM64_REG_S8, "s8"}, + { ARM64_REG_S9, "s9"}, + { ARM64_REG_S10, "s10"}, + { ARM64_REG_S11, "s11"}, + { ARM64_REG_S12, "s12"}, + { ARM64_REG_S13, "s13"}, + { ARM64_REG_S14, "s14"}, + { ARM64_REG_S15, "s15"}, + { ARM64_REG_S16, "s16"}, + { ARM64_REG_S17, "s17"}, + { ARM64_REG_S18, "s18"}, + { ARM64_REG_S19, "s19"}, + { ARM64_REG_S20, "s20"}, + { ARM64_REG_S21, "s21"}, + { ARM64_REG_S22, "s22"}, + { ARM64_REG_S23, "s23"}, + { ARM64_REG_S24, "s24"}, + { ARM64_REG_S25, "s25"}, + { ARM64_REG_S26, "s26"}, + { ARM64_REG_S27, "s27"}, + { ARM64_REG_S28, "s28"}, + { ARM64_REG_S29, "s29"}, + { ARM64_REG_S30, "s30"}, + { ARM64_REG_S31, "s31"}, + { ARM64_REG_W0, "w0"}, + { ARM64_REG_W1, "w1"}, + { ARM64_REG_W2, "w2"}, + { ARM64_REG_W3, "w3"}, + { ARM64_REG_W4, "w4"}, + { ARM64_REG_W5, "w5"}, + { ARM64_REG_W6, "w6"}, + { ARM64_REG_W7, "w7"}, + { ARM64_REG_W8, "w8"}, + { ARM64_REG_W9, "w9"}, + { ARM64_REG_W10, "w10"}, + { ARM64_REG_W11, "w11"}, + { ARM64_REG_W12, "w12"}, + { ARM64_REG_W13, "w13"}, + { ARM64_REG_W14, "w14"}, + { ARM64_REG_W15, "w15"}, + { ARM64_REG_W16, "w16"}, + { ARM64_REG_W17, "w17"}, + { ARM64_REG_W18, "w18"}, + { ARM64_REG_W19, "w19"}, + { ARM64_REG_W20, "w20"}, + { ARM64_REG_W21, "w21"}, + { ARM64_REG_W22, "w22"}, + { ARM64_REG_W23, "w23"}, + { ARM64_REG_W24, "w24"}, + { ARM64_REG_W25, "w25"}, + { ARM64_REG_W26, "w26"}, + { ARM64_REG_W27, "w27"}, + { ARM64_REG_W28, "w28"}, + { ARM64_REG_W29, "w29"}, + { ARM64_REG_W30, "w30"}, + { ARM64_REG_X0, "x0"}, + { ARM64_REG_X1, "x1"}, + { ARM64_REG_X2, "x2"}, + { ARM64_REG_X3, "x3"}, + { ARM64_REG_X4, "x4"}, + { ARM64_REG_X5, "x5"}, + { ARM64_REG_X6, "x6"}, + { ARM64_REG_X7, "x7"}, + { ARM64_REG_X8, "x8"}, + { ARM64_REG_X9, "x9"}, + { ARM64_REG_X10, "x10"}, + { ARM64_REG_X11, "x11"}, + { ARM64_REG_X12, "x12"}, + { ARM64_REG_X13, "x13"}, + { ARM64_REG_X14, "x14"}, + { ARM64_REG_X15, "x15"}, + { ARM64_REG_X16, "x16"}, + { ARM64_REG_X17, "x17"}, + { ARM64_REG_X18, "x18"}, + { ARM64_REG_X19, "x19"}, + { ARM64_REG_X20, "x20"}, + { ARM64_REG_X21, "x21"}, + { ARM64_REG_X22, "x22"}, + { ARM64_REG_X23, "x23"}, + { ARM64_REG_X24, "x24"}, + { ARM64_REG_X25, "x25"}, + { ARM64_REG_X26, "x26"}, + { ARM64_REG_X27, "x27"}, + { ARM64_REG_X28, "x28"}, + + { ARM64_REG_V0, "v0"}, + { ARM64_REG_V1, "v1"}, + { ARM64_REG_V2, "v2"}, + { ARM64_REG_V3, "v3"}, + { ARM64_REG_V4, "v4"}, + { ARM64_REG_V5, "v5"}, + { ARM64_REG_V6, "v6"}, + { ARM64_REG_V7, "v7"}, + { ARM64_REG_V8, "v8"}, + { ARM64_REG_V9, "v9"}, + { ARM64_REG_V10, "v10"}, + { ARM64_REG_V11, "v11"}, + { ARM64_REG_V12, "v12"}, + { ARM64_REG_V13, "v13"}, + { ARM64_REG_V14, "v14"}, + { ARM64_REG_V15, "v15"}, + { ARM64_REG_V16, "v16"}, + { ARM64_REG_V17, "v17"}, + { ARM64_REG_V18, "v18"}, + { ARM64_REG_V19, "v19"}, + { ARM64_REG_V20, "v20"}, + { ARM64_REG_V21, "v21"}, + { ARM64_REG_V22, "v22"}, + { ARM64_REG_V23, "v23"}, + { ARM64_REG_V24, "v24"}, + { ARM64_REG_V25, "v25"}, + { ARM64_REG_V26, "v26"}, + { ARM64_REG_V27, "v27"}, + { ARM64_REG_V28, "v28"}, + { ARM64_REG_V29, "v29"}, + { ARM64_REG_V30, "v30"}, + { ARM64_REG_V31, "v31"}, +}; +#endif + +const char *AArch64_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "AArch64MappingInsn.inc" +}; + +// given internal insn id, return public instruction info +void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); +#endif + } + } +} + +static const name_map insn_name_maps[] = { + { ARM64_INS_INVALID, NULL }, + + { ARM64_INS_ABS, "abs" }, + { ARM64_INS_ADC, "adc" }, + { ARM64_INS_ADDHN, "addhn" }, + { ARM64_INS_ADDHN2, "addhn2" }, + { ARM64_INS_ADDP, "addp" }, + { ARM64_INS_ADD, "add" }, + { ARM64_INS_ADDV, "addv" }, + { ARM64_INS_ADR, "adr" }, + { ARM64_INS_ADRP, "adrp" }, + { ARM64_INS_AESD, "aesd" }, + { ARM64_INS_AESE, "aese" }, + { ARM64_INS_AESIMC, "aesimc" }, + { ARM64_INS_AESMC, "aesmc" }, + { ARM64_INS_AND, "and" }, + { ARM64_INS_ASR, "asr" }, + { ARM64_INS_B, "b" }, + { ARM64_INS_BFM, "bfm" }, + { ARM64_INS_BIC, "bic" }, + { ARM64_INS_BIF, "bif" }, + { ARM64_INS_BIT, "bit" }, + { ARM64_INS_BL, "bl" }, + { ARM64_INS_BLR, "blr" }, + { ARM64_INS_BR, "br" }, + { ARM64_INS_BRK, "brk" }, + { ARM64_INS_BSL, "bsl" }, + { ARM64_INS_CBNZ, "cbnz" }, + { ARM64_INS_CBZ, "cbz" }, + { ARM64_INS_CCMN, "ccmn" }, + { ARM64_INS_CCMP, "ccmp" }, + { ARM64_INS_CLREX, "clrex" }, + { ARM64_INS_CLS, "cls" }, + { ARM64_INS_CLZ, "clz" }, + { ARM64_INS_CMEQ, "cmeq" }, + { ARM64_INS_CMGE, "cmge" }, + { ARM64_INS_CMGT, "cmgt" }, + { ARM64_INS_CMHI, "cmhi" }, + { ARM64_INS_CMHS, "cmhs" }, + { ARM64_INS_CMLE, "cmle" }, + { ARM64_INS_CMLT, "cmlt" }, + { ARM64_INS_CMTST, "cmtst" }, + { ARM64_INS_CNT, "cnt" }, + { ARM64_INS_MOV, "mov" }, + { ARM64_INS_CRC32B, "crc32b" }, + { ARM64_INS_CRC32CB, "crc32cb" }, + { ARM64_INS_CRC32CH, "crc32ch" }, + { ARM64_INS_CRC32CW, "crc32cw" }, + { ARM64_INS_CRC32CX, "crc32cx" }, + { ARM64_INS_CRC32H, "crc32h" }, + { ARM64_INS_CRC32W, "crc32w" }, + { ARM64_INS_CRC32X, "crc32x" }, + { ARM64_INS_CSEL, "csel" }, + { ARM64_INS_CSINC, "csinc" }, + { ARM64_INS_CSINV, "csinv" }, + { ARM64_INS_CSNEG, "csneg" }, + { ARM64_INS_DCPS1, "dcps1" }, + { ARM64_INS_DCPS2, "dcps2" }, + { ARM64_INS_DCPS3, "dcps3" }, + { ARM64_INS_DMB, "dmb" }, + { ARM64_INS_DRPS, "drps" }, + { ARM64_INS_DSB, "dsb" }, + { ARM64_INS_DUP, "dup" }, + { ARM64_INS_EON, "eon" }, + { ARM64_INS_EOR, "eor" }, + { ARM64_INS_ERET, "eret" }, + { ARM64_INS_EXTR, "extr" }, + { ARM64_INS_EXT, "ext" }, + { ARM64_INS_FABD, "fabd" }, + { ARM64_INS_FABS, "fabs" }, + { ARM64_INS_FACGE, "facge" }, + { ARM64_INS_FACGT, "facgt" }, + { ARM64_INS_FADD, "fadd" }, + { ARM64_INS_FADDP, "faddp" }, + { ARM64_INS_FCCMP, "fccmp" }, + { ARM64_INS_FCCMPE, "fccmpe" }, + { ARM64_INS_FCMEQ, "fcmeq" }, + { ARM64_INS_FCMGE, "fcmge" }, + { ARM64_INS_FCMGT, "fcmgt" }, + { ARM64_INS_FCMLE, "fcmle" }, + { ARM64_INS_FCMLT, "fcmlt" }, + { ARM64_INS_FCMP, "fcmp" }, + { ARM64_INS_FCMPE, "fcmpe" }, + { ARM64_INS_FCSEL, "fcsel" }, + { ARM64_INS_FCVTAS, "fcvtas" }, + { ARM64_INS_FCVTAU, "fcvtau" }, + { ARM64_INS_FCVT, "fcvt" }, + { ARM64_INS_FCVTL, "fcvtl" }, + { ARM64_INS_FCVTL2, "fcvtl2" }, + { ARM64_INS_FCVTMS, "fcvtms" }, + { ARM64_INS_FCVTMU, "fcvtmu" }, + { ARM64_INS_FCVTNS, "fcvtns" }, + { ARM64_INS_FCVTNU, "fcvtnu" }, + { ARM64_INS_FCVTN, "fcvtn" }, + { ARM64_INS_FCVTN2, "fcvtn2" }, + { ARM64_INS_FCVTPS, "fcvtps" }, + { ARM64_INS_FCVTPU, "fcvtpu" }, + { ARM64_INS_FCVTXN, "fcvtxn" }, + { ARM64_INS_FCVTXN2, "fcvtxn2" }, + { ARM64_INS_FCVTZS, "fcvtzs" }, + { ARM64_INS_FCVTZU, "fcvtzu" }, + { ARM64_INS_FDIV, "fdiv" }, + { ARM64_INS_FMADD, "fmadd" }, + { ARM64_INS_FMAX, "fmax" }, + { ARM64_INS_FMAXNM, "fmaxnm" }, + { ARM64_INS_FMAXNMP, "fmaxnmp" }, + { ARM64_INS_FMAXNMV, "fmaxnmv" }, + { ARM64_INS_FMAXP, "fmaxp" }, + { ARM64_INS_FMAXV, "fmaxv" }, + { ARM64_INS_FMIN, "fmin" }, + { ARM64_INS_FMINNM, "fminnm" }, + { ARM64_INS_FMINNMP, "fminnmp" }, + { ARM64_INS_FMINNMV, "fminnmv" }, + { ARM64_INS_FMINP, "fminp" }, + { ARM64_INS_FMINV, "fminv" }, + { ARM64_INS_FMLA, "fmla" }, + { ARM64_INS_FMLS, "fmls" }, + { ARM64_INS_FMOV, "fmov" }, + { ARM64_INS_FMSUB, "fmsub" }, + { ARM64_INS_FMUL, "fmul" }, + { ARM64_INS_FMULX, "fmulx" }, + { ARM64_INS_FNEG, "fneg" }, + { ARM64_INS_FNMADD, "fnmadd" }, + { ARM64_INS_FNMSUB, "fnmsub" }, + { ARM64_INS_FNMUL, "fnmul" }, + { ARM64_INS_FRECPE, "frecpe" }, + { ARM64_INS_FRECPS, "frecps" }, + { ARM64_INS_FRECPX, "frecpx" }, + { ARM64_INS_FRINTA, "frinta" }, + { ARM64_INS_FRINTI, "frinti" }, + { ARM64_INS_FRINTM, "frintm" }, + { ARM64_INS_FRINTN, "frintn" }, + { ARM64_INS_FRINTP, "frintp" }, + { ARM64_INS_FRINTX, "frintx" }, + { ARM64_INS_FRINTZ, "frintz" }, + { ARM64_INS_FRSQRTE, "frsqrte" }, + { ARM64_INS_FRSQRTS, "frsqrts" }, + { ARM64_INS_FSQRT, "fsqrt" }, + { ARM64_INS_FSUB, "fsub" }, + { ARM64_INS_HINT, "hint" }, + { ARM64_INS_HLT, "hlt" }, + { ARM64_INS_HVC, "hvc" }, + { ARM64_INS_INS, "ins" }, + { ARM64_INS_ISB, "isb" }, + { ARM64_INS_LD1, "ld1" }, + { ARM64_INS_LD1R, "ld1r" }, + { ARM64_INS_LD2R, "ld2r" }, + { ARM64_INS_LD2, "ld2" }, + { ARM64_INS_LD3R, "ld3r" }, + { ARM64_INS_LD3, "ld3" }, + { ARM64_INS_LD4, "ld4" }, + { ARM64_INS_LD4R, "ld4r" }, + { ARM64_INS_LDARB, "ldarb" }, + { ARM64_INS_LDARH, "ldarh" }, + { ARM64_INS_LDAR, "ldar" }, + { ARM64_INS_LDAXP, "ldaxp" }, + { ARM64_INS_LDAXRB, "ldaxrb" }, + { ARM64_INS_LDAXRH, "ldaxrh" }, + { ARM64_INS_LDAXR, "ldaxr" }, + { ARM64_INS_LDNP, "ldnp" }, + { ARM64_INS_LDP, "ldp" }, + { ARM64_INS_LDPSW, "ldpsw" }, + { ARM64_INS_LDRB, "ldrb" }, + { ARM64_INS_LDR, "ldr" }, + { ARM64_INS_LDRH, "ldrh" }, + { ARM64_INS_LDRSB, "ldrsb" }, + { ARM64_INS_LDRSH, "ldrsh" }, + { ARM64_INS_LDRSW, "ldrsw" }, + { ARM64_INS_LDTRB, "ldtrb" }, + { ARM64_INS_LDTRH, "ldtrh" }, + { ARM64_INS_LDTRSB, "ldtrsb" }, + { ARM64_INS_LDTRSH, "ldtrsh" }, + { ARM64_INS_LDTRSW, "ldtrsw" }, + { ARM64_INS_LDTR, "ldtr" }, + { ARM64_INS_LDURB, "ldurb" }, + { ARM64_INS_LDUR, "ldur" }, + { ARM64_INS_LDURH, "ldurh" }, + { ARM64_INS_LDURSB, "ldursb" }, + { ARM64_INS_LDURSH, "ldursh" }, + { ARM64_INS_LDURSW, "ldursw" }, + { ARM64_INS_LDXP, "ldxp" }, + { ARM64_INS_LDXRB, "ldxrb" }, + { ARM64_INS_LDXRH, "ldxrh" }, + { ARM64_INS_LDXR, "ldxr" }, + { ARM64_INS_LSL, "lsl" }, + { ARM64_INS_LSR, "lsr" }, + { ARM64_INS_MADD, "madd" }, + { ARM64_INS_MLA, "mla" }, + { ARM64_INS_MLS, "mls" }, + { ARM64_INS_MOVI, "movi" }, + { ARM64_INS_MOVK, "movk" }, + { ARM64_INS_MOVN, "movn" }, + { ARM64_INS_MOVZ, "movz" }, + { ARM64_INS_MRS, "mrs" }, + { ARM64_INS_MSR, "msr" }, + { ARM64_INS_MSUB, "msub" }, + { ARM64_INS_MUL, "mul" }, + { ARM64_INS_MVNI, "mvni" }, + { ARM64_INS_NEG, "neg" }, + { ARM64_INS_NOT, "not" }, + { ARM64_INS_ORN, "orn" }, + { ARM64_INS_ORR, "orr" }, + { ARM64_INS_PMULL2, "pmull2" }, + { ARM64_INS_PMULL, "pmull" }, + { ARM64_INS_PMUL, "pmul" }, + { ARM64_INS_PRFM, "prfm" }, + { ARM64_INS_PRFUM, "prfum" }, + { ARM64_INS_RADDHN, "raddhn" }, + { ARM64_INS_RADDHN2, "raddhn2" }, + { ARM64_INS_RBIT, "rbit" }, + { ARM64_INS_RET, "ret" }, + { ARM64_INS_REV16, "rev16" }, + { ARM64_INS_REV32, "rev32" }, + { ARM64_INS_REV64, "rev64" }, + { ARM64_INS_REV, "rev" }, + { ARM64_INS_ROR, "ror" }, + { ARM64_INS_RSHRN2, "rshrn2" }, + { ARM64_INS_RSHRN, "rshrn" }, + { ARM64_INS_RSUBHN, "rsubhn" }, + { ARM64_INS_RSUBHN2, "rsubhn2" }, + { ARM64_INS_SABAL2, "sabal2" }, + { ARM64_INS_SABAL, "sabal" }, + { ARM64_INS_SABA, "saba" }, + { ARM64_INS_SABDL2, "sabdl2" }, + { ARM64_INS_SABDL, "sabdl" }, + { ARM64_INS_SABD, "sabd" }, + { ARM64_INS_SADALP, "sadalp" }, + { ARM64_INS_SADDLP, "saddlp" }, + { ARM64_INS_SADDLV, "saddlv" }, + { ARM64_INS_SADDL2, "saddl2" }, + { ARM64_INS_SADDL, "saddl" }, + { ARM64_INS_SADDW2, "saddw2" }, + { ARM64_INS_SADDW, "saddw" }, + { ARM64_INS_SBC, "sbc" }, + { ARM64_INS_SBFM, "sbfm" }, + { ARM64_INS_SCVTF, "scvtf" }, + { ARM64_INS_SDIV, "sdiv" }, + { ARM64_INS_SHA1C, "sha1c" }, + { ARM64_INS_SHA1H, "sha1h" }, + { ARM64_INS_SHA1M, "sha1m" }, + { ARM64_INS_SHA1P, "sha1p" }, + { ARM64_INS_SHA1SU0, "sha1su0" }, + { ARM64_INS_SHA1SU1, "sha1su1" }, + { ARM64_INS_SHA256H2, "sha256h2" }, + { ARM64_INS_SHA256H, "sha256h" }, + { ARM64_INS_SHA256SU0, "sha256su0" }, + { ARM64_INS_SHA256SU1, "sha256su1" }, + { ARM64_INS_SHADD, "shadd" }, + { ARM64_INS_SHLL2, "shll2" }, + { ARM64_INS_SHLL, "shll" }, + { ARM64_INS_SHL, "shl" }, + { ARM64_INS_SHRN2, "shrn2" }, + { ARM64_INS_SHRN, "shrn" }, + { ARM64_INS_SHSUB, "shsub" }, + { ARM64_INS_SLI, "sli" }, + { ARM64_INS_SMADDL, "smaddl" }, + { ARM64_INS_SMAXP, "smaxp" }, + { ARM64_INS_SMAXV, "smaxv" }, + { ARM64_INS_SMAX, "smax" }, + { ARM64_INS_SMC, "smc" }, + { ARM64_INS_SMINP, "sminp" }, + { ARM64_INS_SMINV, "sminv" }, + { ARM64_INS_SMIN, "smin" }, + { ARM64_INS_SMLAL2, "smlal2" }, + { ARM64_INS_SMLAL, "smlal" }, + { ARM64_INS_SMLSL2, "smlsl2" }, + { ARM64_INS_SMLSL, "smlsl" }, + { ARM64_INS_SMOV, "smov" }, + { ARM64_INS_SMSUBL, "smsubl" }, + { ARM64_INS_SMULH, "smulh" }, + { ARM64_INS_SMULL2, "smull2" }, + { ARM64_INS_SMULL, "smull" }, + { ARM64_INS_SQABS, "sqabs" }, + { ARM64_INS_SQADD, "sqadd" }, + { ARM64_INS_SQDMLAL, "sqdmlal" }, + { ARM64_INS_SQDMLAL2, "sqdmlal2" }, + { ARM64_INS_SQDMLSL, "sqdmlsl" }, + { ARM64_INS_SQDMLSL2, "sqdmlsl2" }, + { ARM64_INS_SQDMULH, "sqdmulh" }, + { ARM64_INS_SQDMULL, "sqdmull" }, + { ARM64_INS_SQDMULL2, "sqdmull2" }, + { ARM64_INS_SQNEG, "sqneg" }, + { ARM64_INS_SQRDMULH, "sqrdmulh" }, + { ARM64_INS_SQRSHL, "sqrshl" }, + { ARM64_INS_SQRSHRN, "sqrshrn" }, + { ARM64_INS_SQRSHRN2, "sqrshrn2" }, + { ARM64_INS_SQRSHRUN, "sqrshrun" }, + { ARM64_INS_SQRSHRUN2, "sqrshrun2" }, + { ARM64_INS_SQSHLU, "sqshlu" }, + { ARM64_INS_SQSHL, "sqshl" }, + { ARM64_INS_SQSHRN, "sqshrn" }, + { ARM64_INS_SQSHRN2, "sqshrn2" }, + { ARM64_INS_SQSHRUN, "sqshrun" }, + { ARM64_INS_SQSHRUN2, "sqshrun2" }, + { ARM64_INS_SQSUB, "sqsub" }, + { ARM64_INS_SQXTN2, "sqxtn2" }, + { ARM64_INS_SQXTN, "sqxtn" }, + { ARM64_INS_SQXTUN2, "sqxtun2" }, + { ARM64_INS_SQXTUN, "sqxtun" }, + { ARM64_INS_SRHADD, "srhadd" }, + { ARM64_INS_SRI, "sri" }, + { ARM64_INS_SRSHL, "srshl" }, + { ARM64_INS_SRSHR, "srshr" }, + { ARM64_INS_SRSRA, "srsra" }, + { ARM64_INS_SSHLL2, "sshll2" }, + { ARM64_INS_SSHLL, "sshll" }, + { ARM64_INS_SSHL, "sshl" }, + { ARM64_INS_SSHR, "sshr" }, + { ARM64_INS_SSRA, "ssra" }, + { ARM64_INS_SSUBL2, "ssubl2" }, + { ARM64_INS_SSUBL, "ssubl" }, + { ARM64_INS_SSUBW2, "ssubw2" }, + { ARM64_INS_SSUBW, "ssubw" }, + { ARM64_INS_ST1, "st1" }, + { ARM64_INS_ST2, "st2" }, + { ARM64_INS_ST3, "st3" }, + { ARM64_INS_ST4, "st4" }, + { ARM64_INS_STLRB, "stlrb" }, + { ARM64_INS_STLRH, "stlrh" }, + { ARM64_INS_STLR, "stlr" }, + { ARM64_INS_STLXP, "stlxp" }, + { ARM64_INS_STLXRB, "stlxrb" }, + { ARM64_INS_STLXRH, "stlxrh" }, + { ARM64_INS_STLXR, "stlxr" }, + { ARM64_INS_STNP, "stnp" }, + { ARM64_INS_STP, "stp" }, + { ARM64_INS_STRB, "strb" }, + { ARM64_INS_STR, "str" }, + { ARM64_INS_STRH, "strh" }, + { ARM64_INS_STTRB, "sttrb" }, + { ARM64_INS_STTRH, "sttrh" }, + { ARM64_INS_STTR, "sttr" }, + { ARM64_INS_STURB, "sturb" }, + { ARM64_INS_STUR, "stur" }, + { ARM64_INS_STURH, "sturh" }, + { ARM64_INS_STXP, "stxp" }, + { ARM64_INS_STXRB, "stxrb" }, + { ARM64_INS_STXRH, "stxrh" }, + { ARM64_INS_STXR, "stxr" }, + { ARM64_INS_SUBHN, "subhn" }, + { ARM64_INS_SUBHN2, "subhn2" }, + { ARM64_INS_SUB, "sub" }, + { ARM64_INS_SUQADD, "suqadd" }, + { ARM64_INS_SVC, "svc" }, + { ARM64_INS_SYSL, "sysl" }, + { ARM64_INS_SYS, "sys" }, + { ARM64_INS_TBL, "tbl" }, + { ARM64_INS_TBNZ, "tbnz" }, + { ARM64_INS_TBX, "tbx" }, + { ARM64_INS_TBZ, "tbz" }, + { ARM64_INS_TRN1, "trn1" }, + { ARM64_INS_TRN2, "trn2" }, + { ARM64_INS_UABAL2, "uabal2" }, + { ARM64_INS_UABAL, "uabal" }, + { ARM64_INS_UABA, "uaba" }, + { ARM64_INS_UABDL2, "uabdl2" }, + { ARM64_INS_UABDL, "uabdl" }, + { ARM64_INS_UABD, "uabd" }, + { ARM64_INS_UADALP, "uadalp" }, + { ARM64_INS_UADDLP, "uaddlp" }, + { ARM64_INS_UADDLV, "uaddlv" }, + { ARM64_INS_UADDL2, "uaddl2" }, + { ARM64_INS_UADDL, "uaddl" }, + { ARM64_INS_UADDW2, "uaddw2" }, + { ARM64_INS_UADDW, "uaddw" }, + { ARM64_INS_UBFM, "ubfm" }, + { ARM64_INS_UCVTF, "ucvtf" }, + { ARM64_INS_UDIV, "udiv" }, + { ARM64_INS_UHADD, "uhadd" }, + { ARM64_INS_UHSUB, "uhsub" }, + { ARM64_INS_UMADDL, "umaddl" }, + { ARM64_INS_UMAXP, "umaxp" }, + { ARM64_INS_UMAXV, "umaxv" }, + { ARM64_INS_UMAX, "umax" }, + { ARM64_INS_UMINP, "uminp" }, + { ARM64_INS_UMINV, "uminv" }, + { ARM64_INS_UMIN, "umin" }, + { ARM64_INS_UMLAL2, "umlal2" }, + { ARM64_INS_UMLAL, "umlal" }, + { ARM64_INS_UMLSL2, "umlsl2" }, + { ARM64_INS_UMLSL, "umlsl" }, + { ARM64_INS_UMOV, "umov" }, + { ARM64_INS_UMSUBL, "umsubl" }, + { ARM64_INS_UMULH, "umulh" }, + { ARM64_INS_UMULL2, "umull2" }, + { ARM64_INS_UMULL, "umull" }, + { ARM64_INS_UQADD, "uqadd" }, + { ARM64_INS_UQRSHL, "uqrshl" }, + { ARM64_INS_UQRSHRN, "uqrshrn" }, + { ARM64_INS_UQRSHRN2, "uqrshrn2" }, + { ARM64_INS_UQSHL, "uqshl" }, + { ARM64_INS_UQSHRN, "uqshrn" }, + { ARM64_INS_UQSHRN2, "uqshrn2" }, + { ARM64_INS_UQSUB, "uqsub" }, + { ARM64_INS_UQXTN2, "uqxtn2" }, + { ARM64_INS_UQXTN, "uqxtn" }, + { ARM64_INS_URECPE, "urecpe" }, + { ARM64_INS_URHADD, "urhadd" }, + { ARM64_INS_URSHL, "urshl" }, + { ARM64_INS_URSHR, "urshr" }, + { ARM64_INS_URSQRTE, "ursqrte" }, + { ARM64_INS_URSRA, "ursra" }, + { ARM64_INS_USHLL2, "ushll2" }, + { ARM64_INS_USHLL, "ushll" }, + { ARM64_INS_USHL, "ushl" }, + { ARM64_INS_USHR, "ushr" }, + { ARM64_INS_USQADD, "usqadd" }, + { ARM64_INS_USRA, "usra" }, + { ARM64_INS_USUBL2, "usubl2" }, + { ARM64_INS_USUBL, "usubl" }, + { ARM64_INS_USUBW2, "usubw2" }, + { ARM64_INS_USUBW, "usubw" }, + { ARM64_INS_UZP1, "uzp1" }, + { ARM64_INS_UZP2, "uzp2" }, + { ARM64_INS_XTN2, "xtn2" }, + { ARM64_INS_XTN, "xtn" }, + { ARM64_INS_ZIP1, "zip1" }, + { ARM64_INS_ZIP2, "zip2" }, +}; + +// map *S & alias instructions back to original id +static const name_map alias_insn_name_maps[] = { + { ARM64_INS_ADC, "adcs" }, + { ARM64_INS_AND, "ands" }, + { ARM64_INS_ADD, "adds" }, + { ARM64_INS_BIC, "bics" }, + { ARM64_INS_SBC, "sbcs" }, + { ARM64_INS_SUB, "subs" }, + + // alias insn + { ARM64_INS_MNEG, "mneg" }, + { ARM64_INS_UMNEGL, "umnegl" }, + { ARM64_INS_SMNEGL, "smnegl" }, + { ARM64_INS_NOP, "nop" }, + { ARM64_INS_YIELD, "yield" }, + { ARM64_INS_WFE, "wfe" }, + { ARM64_INS_WFI, "wfi" }, + { ARM64_INS_SEV, "sev" }, + { ARM64_INS_SEVL, "sevl" }, + { ARM64_INS_NGC, "ngc" }, + { ARM64_INS_NGCS, "ngcs" }, + { ARM64_INS_NEGS, "negs" }, + + { ARM64_INS_SBFIZ, "sbfiz" }, + { ARM64_INS_UBFIZ, "ubfiz" }, + { ARM64_INS_SBFX, "sbfx" }, + { ARM64_INS_UBFX, "ubfx" }, + { ARM64_INS_BFI, "bfi" }, + { ARM64_INS_BFXIL, "bfxil" }, + { ARM64_INS_CMN, "cmn" }, + { ARM64_INS_MVN, "mvn" }, + { ARM64_INS_TST, "tst" }, + { ARM64_INS_CSET, "cset" }, + { ARM64_INS_CINC, "cinc" }, + { ARM64_INS_CSETM, "csetm" }, + { ARM64_INS_CINV, "cinv" }, + { ARM64_INS_CNEG, "cneg" }, + { ARM64_INS_SXTB, "sxtb" }, + { ARM64_INS_SXTH, "sxth" }, + { ARM64_INS_SXTW, "sxtw" }, + { ARM64_INS_CMP, "cmp" }, + { ARM64_INS_UXTB, "uxtb" }, + { ARM64_INS_UXTH, "uxth" }, + { ARM64_INS_UXTW, "uxtw" }, + + { ARM64_INS_IC, "ic" }, + { ARM64_INS_DC, "dc" }, + { ARM64_INS_AT, "at" }, + { ARM64_INS_TLBI, "tlbi" }, +}; + +const char *AArch64_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= ARM64_INS_ENDING) + return NULL; + + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id].name; + + // then find alias insn + for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { + if (alias_insn_name_maps[i].id == id) + return alias_insn_name_maps[i].name; + } + + // not found + return NULL; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { ARM64_GRP_INVALID, NULL }, + { ARM64_GRP_JUMP, "jump" }, + { ARM64_GRP_CALL, "call" }, + { ARM64_GRP_RET, "return" }, + { ARM64_GRP_PRIVILEGE, "privilege" }, + { ARM64_GRP_INT, "int" }, + { ARM64_GRP_BRANCH_RELATIVE, "branch_relative" }, + + // architecture-specific groups + { ARM64_GRP_CRYPTO, "crypto" }, + { ARM64_GRP_FPARMV8, "fparmv8" }, + { ARM64_GRP_NEON, "neon" }, + { ARM64_GRP_CRC, "crc" }, +}; +#endif + +const char *AArch64_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map instruction name to public instruction ID +arm64_reg AArch64_map_insn(const char *name) +{ + // NOTE: skip first NULL name in insn_name_maps + int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + + if (i == -1) + // try again with 'special' insn that is not available in insn_name_maps + i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); + + return (i != -1)? i : ARM64_REG_INVALID; +} + +// map internal raw vregister to 'public' register +arm64_reg AArch64_map_vregister(unsigned int r) +{ + // for some reasons different Arm64 can map different register number to + // the same register. this function handles the issue for exposing Mips + // operands by mapping internal registers to 'public' register. + static const unsigned int map[] = { 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, ARM64_REG_V0, + ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, + ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, + ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, + ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, + ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, + ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, + ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, + ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, + ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, + ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, + ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, + ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, + ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, + ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, + ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, + ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, + ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, + ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, + ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, + ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, + ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, + ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, + ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, + ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, + ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, + ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, + ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, + ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, + ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, + ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, + ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, + ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, + ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, + ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, + ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, + ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, + ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, + ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, + ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, + ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, + ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, + ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, + ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, + ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, + ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, + ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, + ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, + ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, + ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, + ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, + ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; + } +} + +void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp; + } +} + +void arm64_op_addFP(MCInst *MI, float fp) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; + MI->flat_insn->detail->arm64.op_count++; + } +} + +void arm64_op_addImm(MCInst *MI, int64_t imm) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; + MI->flat_insn->detail->arm64.op_count++; + } +} + +#ifndef CAPSTONE_DIET + +// map instruction to its characteristics +typedef struct insn_op { + unsigned int eflags_update; // how this instruction update status flags + uint8_t access[5]; +} insn_op; + +static insn_op insn_ops[] = { + { + /* NULL item */ + 0, { 0 } + }, + +#include "AArch64MappingInsnOp.inc" +}; + +// given internal insn id, return operand access info +uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id) +{ + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + return insn_ops[i].access; + } + + return NULL; +} + +void AArch64_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + uint8_t i; + uint8_t read_count, write_count; + cs_arm64 *arm64 = &(insn->detail->arm64); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < arm64->op_count; i++) { + cs_arm64_op *op = &(arm64->operands[i]); + switch((int)op->type) { + case ARM64_OP_REG: + if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case ARM_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = (uint16_t)op->mem.index; + read_count++; + } + if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.h new file mode 100644 index 0000000..3973754 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Mapping.h @@ -0,0 +1,41 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_ARM64_MAP_H +#define CS_ARM64_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *AArch64_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *AArch64_insn_name(csh handle, unsigned int id); + +const char *AArch64_group_name(csh handle, unsigned int id); + +// map instruction name to public instruction ID +arm64_reg AArch64_map_insn(const char *name); + +// map internal vregister to public register +arm64_reg AArch64_map_vregister(unsigned int r); + +void arm64_op_addReg(MCInst *MI, int reg); + +void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); + +void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp); + +void arm64_op_addFP(MCInst *MI, float fp); + +void arm64_op_addImm(MCInst *MI, int64_t imm); + +uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); + +void AArch64_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsn.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsn.inc new file mode 100644 index 0000000..02d07e7 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsn.inc @@ -0,0 +1,13965 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + AArch64_ABSv16i8, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv1i64, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv2i32, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv2i64, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv4i16, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv4i32, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv8i16, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ABSv8i8, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADCSWr, ARM64_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADCSXr, ARM64_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADCWr, ARM64_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADCXr, ARM64_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv16i8, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv2i32, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv2i64, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv2i64p, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv4i16, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv4i32, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv8i16, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDPv8i8, ARM64_INS_ADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSWri, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSWrs, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSWrx, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSXri, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSXrs, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSXrx, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDSXrx64, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDVv16i8v, ARM64_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDVv4i16v, ARM64_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDVv4i32v, ARM64_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDVv8i16v, ARM64_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDVv8i8v, ARM64_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDWri, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDWrs, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDWrx, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDXri, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDXrs, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDXrx, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDXrx64, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv16i8, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv1i64, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv2i32, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv2i64, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv4i16, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv4i32, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv8i16, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADDv8i8, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ADR, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ADRP, ARM64_INS_ADRP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_AESDrr, ARM64_INS_AESD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_AESErr, ARM64_INS_AESE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_AESIMCrr, ARM64_INS_AESIMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_AESMCrr, ARM64_INS_AESMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDSWri, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDSWrs, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDSXri, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDSXrs, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDWri, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDWrs, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDXri, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDXrs, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDv16i8, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ANDv8i8, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ASRVWr, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ASRVXr, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_B, ARM64_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_BFMWri, ARM64_INS_BFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BFMXri, ARM64_INS_BFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BICSWrs, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BICSXrs, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BICWrs, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BICXrs, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv16i8, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv2i32, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv4i16, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv4i32, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv8i16, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BICv8i8, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BIFv16i8, ARM64_INS_BIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BIFv8i8, ARM64_INS_BIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BITv16i8, ARM64_INS_BIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BITv8i8, ARM64_INS_BIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BL, ARM64_INS_BL, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_BLR, ARM64_INS_BLR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1 +#endif +}, +{ + AArch64_BR, ARM64_INS_BR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1 +#endif +}, +{ + AArch64_BRK, ARM64_INS_BRK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_BSLv16i8, ARM64_INS_BSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_BSLv8i8, ARM64_INS_BSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_Bcc, ARM64_INS_B, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_CBNZW, ARM64_INS_CBNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_CBNZX, ARM64_INS_CBNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_CBZW, ARM64_INS_CBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_CBZX, ARM64_INS_CBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_CCMNWi, ARM64_INS_CCMN, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMNWr, ARM64_INS_CCMN, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMNXi, ARM64_INS_CCMN, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMNXr, ARM64_INS_CCMN, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMPWi, ARM64_INS_CCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMPWr, ARM64_INS_CCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMPXi, ARM64_INS_CCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CCMPXr, ARM64_INS_CCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLREX, ARM64_INS_CLREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSWr, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSXr, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv16i8, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv2i32, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv4i16, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv4i32, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv8i16, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLSv8i8, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZWr, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZXr, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv16i8, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv2i32, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv4i16, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv4i32, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv8i16, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CLZv8i8, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv16i8, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv1i64, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv2i32, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv2i64, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv4i16, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv4i32, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv8i16, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv8i8, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv16i8, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv16i8rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv1i64, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv1i64rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv2i32, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv2i32rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv2i64, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv2i64rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv4i16, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv4i16rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv4i32, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv4i32rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv8i16, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv8i16rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv8i8, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGEv8i8rz, ARM64_INS_CMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv16i8, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv16i8rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv1i64, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv1i64rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv2i32, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv2i32rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv2i64, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv2i64rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv4i16, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv4i16rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv4i32, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv4i32rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv8i16, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv8i16rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv8i8, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMGTv8i8rz, ARM64_INS_CMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv16i8, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv1i64, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv2i32, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv2i64, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv4i16, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv4i32, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv8i16, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHIv8i8, ARM64_INS_CMHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv16i8, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv1i64, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv2i32, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv2i64, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv4i16, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv4i32, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv8i16, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMHSv8i8, ARM64_INS_CMHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv16i8rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv1i64rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv2i32rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv2i64rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv4i16rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv4i32rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv8i16rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLEv8i8rz, ARM64_INS_CMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv16i8rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv1i64rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv2i32rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv2i64rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv4i16rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv4i32rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv8i16rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMLTv8i8rz, ARM64_INS_CMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv16i8, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv1i64, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv2i32, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv2i64, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv4i16, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv4i32, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv8i16, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CMTSTv8i8, ARM64_INS_CMTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CNTv16i8, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CNTv8i8, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CPYi16, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CPYi32, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CPYi64, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CPYi8, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32Brr, ARM64_INS_CRC32B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32CBrr, ARM64_INS_CRC32CB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32CHrr, ARM64_INS_CRC32CH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32CWrr, ARM64_INS_CRC32CW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32CXrr, ARM64_INS_CRC32CX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32Hrr, ARM64_INS_CRC32H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32Wrr, ARM64_INS_CRC32W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CRC32Xrr, ARM64_INS_CRC32X, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 +#endif +}, +{ + AArch64_CSELWr, ARM64_INS_CSEL, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSELXr, ARM64_INS_CSEL, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSINCWr, ARM64_INS_CSINC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSINCXr, ARM64_INS_CSINC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSINVWr, ARM64_INS_CSINV, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSINVXr, ARM64_INS_CSINV, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSNEGWr, ARM64_INS_CSNEG, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_CSNEGXr, ARM64_INS_CSNEG, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DCPS1, ARM64_INS_DCPS1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DCPS2, ARM64_INS_DCPS2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DCPS3, ARM64_INS_DCPS3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DMB, ARM64_INS_DMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DRPS, ARM64_INS_DRPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DSB, ARM64_INS_DSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv16i8gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv16i8lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv2i32gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv2i32lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv2i64gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv2i64lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv4i16gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv4i16lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv4i32gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv4i32lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv8i16gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv8i16lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv8i8gpr, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_DUPv8i8lane, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_EONWrs, ARM64_INS_EON, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EONXrs, ARM64_INS_EON, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EORWri, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EORWrs, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EORXri, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EORXrs, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EORv16i8, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_EORv8i8, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ERET, ARM64_INS_ERET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EXTRWrri, ARM64_INS_EXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EXTRXrri, ARM64_INS_EXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_EXTv16i8, ARM64_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_EXTv8i8, ARM64_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABD32, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABD64, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABDv2f32, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABDv2f64, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABDv4f32, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABSDr, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABSSr, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABSv2f32, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABSv2f64, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FABSv4f32, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGE32, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGE64, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGEv2f32, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGEv2f64, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGEv4f32, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGT32, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGT64, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGTv2f32, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGTv2f64, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FACGTv4f32, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDDrr, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDPv2f32, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDPv2f64, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDPv2i32p, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDPv2i64p, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDPv4f32, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDSrr, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDv2f32, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDv2f64, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FADDv4f32, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCCMPDrr, ARM64_INS_FCCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCCMPESrr, ARM64_INS_FCCMPE, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCCMPSrr, ARM64_INS_FCCMP, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQ32, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQ64, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGE32, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGE64, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv2f32, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv2f64, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv4f32, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGT32, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGT64, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv2f32, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv2f64, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv4f32, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPDri, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPDrr, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPEDri, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPEDrr, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPESri, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPESrr, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPSri, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCMPSrr, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCSELDrrr, ARM64_INS_FCSEL, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCSELSrrr, ARM64_INS_FCSEL, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTDHr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTDSr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTHDr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTHSr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTLv2i32, ARM64_INS_FCVTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTLv4i16, ARM64_INS_FCVTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNv2i32, ARM64_INS_FCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNv4i16, ARM64_INS_FCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTSDr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTSHr, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSd, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSs, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUd, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUs, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FDIVDrr, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FDIVSrr, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FDIVv2f32, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FDIVv2f64, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FDIVv4f32, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMADDDrrr, ARM64_INS_FMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMADDSrrr, ARM64_INS_FMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXDrr, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMDrr, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMSrr, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXPv2f32, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXPv2f64, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXPv2i32p, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXPv2i64p, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXPv4f32, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXSrr, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXVv4i32v, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXv2f32, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXv2f64, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMAXv4f32, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINDrr, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMDrr, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMSrr, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMv2f32, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMv2f64, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINNMv4f32, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINPv2f32, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINPv2f64, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINPv2i32p, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINPv2i64p, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINPv4f32, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINSrr, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINVv4i32v, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINv2f32, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINv2f64, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMINv4f32, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv2f32, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv2f64, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv4f32, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv2f32, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv2f64, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv4f32, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVDXHighr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVDXr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVDi, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVDr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVSWr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVSi, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVSr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVWSr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVXDHighr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVXDr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVv2f32_ns, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVv2f64_ns, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMOVv4f32_ns, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMSUBDrrr, ARM64_INS_FMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMSUBSrrr, ARM64_INS_FMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULDrr, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULSrr, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULX32, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULX64, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv2f32, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv2f64, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv4f32, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv1i32_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv1i64_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv2f32, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv2f64, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv2i32_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv2i64_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv4f32, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FMULv4i32_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNEGDr, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNEGSr, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNEGv2f32, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNEGv2f64, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNEGv4f32, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMADDDrrr, ARM64_INS_FNMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMADDSrrr, ARM64_INS_FNMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMULDrr, ARM64_INS_FNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FNMULSrr, ARM64_INS_FNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPEv1i32, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPEv1i64, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPEv2f32, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPEv2f64, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPEv4f32, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPS32, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPS64, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPSv2f32, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPSv2f64, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPSv4f32, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPXv1i32, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRECPXv1i64, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTADr, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTASr, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTAv2f32, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTAv2f64, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTAv4f32, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTIDr, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTISr, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTIv2f32, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTIv2f64, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTIv4f32, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTMDr, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTMSr, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTMv2f32, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTMv2f64, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTMv4f32, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTNDr, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTNSr, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTNv2f32, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTNv2f64, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTNv4f32, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTPDr, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTPSr, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTPv2f32, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTPv2f64, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTPv4f32, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTXDr, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTXSr, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTXv2f32, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTXv2f64, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTXv4f32, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTZDr, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTZSr, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTZv2f32, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTZv2f64, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRINTZv4f32, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTS32, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTS64, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSQRTDr, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSQRTSr, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSQRTv2f32, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSQRTv2f64, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSQRTv4f32, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSUBDrr, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSUBSrr, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSUBv2f32, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSUBv2f64, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_FSUBv4f32, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_HINT, ARM64_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_HLT, ARM64_INS_HLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_HVC, ARM64_INS_HVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi16gpr, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi16lane, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi32gpr, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi32lane, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi64gpr, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi64lane, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi8gpr, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_INSvi8lane, ARM64_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ISB, ARM64_INS_ISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv16b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv16b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv1d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv1d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv2d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv2d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv2s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv2s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv4h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv4h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv4s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv4s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv8b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv8b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv8h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Fourv8h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev16b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev16b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev1d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev1d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev2d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev2d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev2s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev2s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev4h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev4h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev4s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev4s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev8b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev8b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev8h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Onev8h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv16b, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv16b_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv1d, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv1d_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv2d, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv2d_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv2s, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv2s_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv4h, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv4h_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv4s, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv4s_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv8b, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv8b_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv8h, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Rv8h_POST, ARM64_INS_LD1R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev16b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev16b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev1d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev1d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev2d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev2d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev2s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev2s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev4h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev4h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev4s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev4s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev8b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev8b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev8h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Threev8h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov16b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov16b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov1d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov1d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov2d, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov2d_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov2s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov2s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov4h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov4h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov4s, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov4s_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov8b, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov8b_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov8h, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1Twov8h_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i16, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i16_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i32, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i32_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i64, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i64_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i8, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD1i8_POST, ARM64_INS_LD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv16b, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv16b_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv1d, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv1d_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv2d, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv2d_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv2s, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv2s_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv4h, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv4h_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv4s, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv4s_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv8b, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv8b_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv8h, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Rv8h_POST, ARM64_INS_LD2R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov16b, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov16b_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov2d, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov2d_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov2s, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov2s_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov4h, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov4h_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov4s, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov4s_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov8b, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov8b_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov8h, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2Twov8h_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i16, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i16_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i32, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i32_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i64, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i64_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i8, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD2i8_POST, ARM64_INS_LD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv16b, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv16b_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv1d, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv1d_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv2d, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv2d_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv2s, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv2s_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv4h, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv4h_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv4s, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv4s_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv8b, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv8b_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv8h, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Rv8h_POST, ARM64_INS_LD3R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev16b, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev16b_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev2d, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev2d_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev2s, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev2s_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev4h, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev4h_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev4s, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev4s_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev8b, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev8b_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev8h, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3Threev8h_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i16, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i16_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i32, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i32_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i64, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i64_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i8, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD3i8_POST, ARM64_INS_LD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv16b, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv16b_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv2d, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv2d_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv2s, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv2s_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv4h, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv4h_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv4s, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv4s_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv8b, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv8b_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv8h, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Fourv8h_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv16b, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv16b_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv1d, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv1d_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv2d, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv2d_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv2s, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv2s_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv4h, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv4h_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv4s, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv4s_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv8b, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv8b_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv8h, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4Rv8h_POST, ARM64_INS_LD4R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i16, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i16_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i32, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i32_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i64, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i64_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i8, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LD4i8_POST, ARM64_INS_LD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_LDARB, ARM64_INS_LDARB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDARH, ARM64_INS_LDARH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDARW, ARM64_INS_LDAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDARX, ARM64_INS_LDAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXPW, ARM64_INS_LDAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXPX, ARM64_INS_LDAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXRB, ARM64_INS_LDAXRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXRH, ARM64_INS_LDAXRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXRW, ARM64_INS_LDAXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDAXRX, ARM64_INS_LDAXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDNPDi, ARM64_INS_LDNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDNPQi, ARM64_INS_LDNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDNPSi, ARM64_INS_LDNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDNPWi, ARM64_INS_LDNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDNPXi, ARM64_INS_LDNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPDi, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPDpost, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPDpre, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPQi, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPQpost, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPQpre, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSWi, ARM64_INS_LDPSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSWpost, ARM64_INS_LDPSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSWpre, ARM64_INS_LDPSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSi, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSpost, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPSpre, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPWi, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPWpost, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPWpre, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPXi, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPXpost, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDPXpre, ARM64_INS_LDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBBpost, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBBpre, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBBroW, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBBroX, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBBui, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRBui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDl, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRDui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHHpost, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHHpre, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHHroW, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHHroX, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHHui, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRHui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQl, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRQui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBWpost, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBWpre, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBWroW, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBWroX, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBWui, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBXpost, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBXpre, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBXroW, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBXroX, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSBXui, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHWpost, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHWpre, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHWroW, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHWroX, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHWui, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHXpost, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHXpre, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHXroW, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHXroX, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSHXui, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWl, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWpost, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWpre, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWroW, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWroX, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSWui, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSl, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRSui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWl, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRWui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXl, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXpost, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXpre, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXroW, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXroX, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDRXui, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRBi, ARM64_INS_LDTRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRHi, ARM64_INS_LDTRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRSBWi, ARM64_INS_LDTRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRSBXi, ARM64_INS_LDTRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRSHWi, ARM64_INS_LDTRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRSHXi, ARM64_INS_LDTRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRSWi, ARM64_INS_LDTRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRWi, ARM64_INS_LDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDTRXi, ARM64_INS_LDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURBBi, ARM64_INS_LDURB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURBi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURDi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURHHi, ARM64_INS_LDURH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURHi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURQi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSBWi, ARM64_INS_LDURSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSBXi, ARM64_INS_LDURSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSHWi, ARM64_INS_LDURSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSHXi, ARM64_INS_LDURSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSWi, ARM64_INS_LDURSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURSi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURWi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDURXi, ARM64_INS_LDUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXPW, ARM64_INS_LDXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXPX, ARM64_INS_LDXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXRB, ARM64_INS_LDXRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXRH, ARM64_INS_LDXRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXRW, ARM64_INS_LDXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LDXRX, ARM64_INS_LDXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LSLVWr, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LSLVXr, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LSRVWr, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_LSRVXr, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MADDWrrr, ARM64_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MADDXrrr, ARM64_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv16i8, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv2i32, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv2i32_indexed, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv4i16, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv4i16_indexed, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv4i32, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv4i32_indexed, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv8i16, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv8i16_indexed, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLAv8i8, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv16i8, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv2i32, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv2i32_indexed, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv4i16, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv4i16_indexed, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv4i32, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv4i32_indexed, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv8i16, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv8i16_indexed, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MLSv8i8, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVID, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv16b_ns, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv2d_ns, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv2i32, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv2s_msl, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv4i16, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv4i32, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv4s_msl, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv8b_ns, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVIv8i16, ARM64_INS_MOVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVKWi, ARM64_INS_MOVK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVKXi, ARM64_INS_MOVK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVNWi, ARM64_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVNXi, ARM64_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVZWi, ARM64_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MOVZXi, ARM64_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MRS, ARM64_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, +{ + AArch64_MSR, ARM64_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, +{ + AArch64_MSRpstate, ARM64_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, +{ + AArch64_MSUBWrrr, ARM64_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MSUBXrrr, ARM64_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv16i8, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv2i32, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv2i32_indexed, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv4i16, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv4i16_indexed, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv4i32, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv4i32_indexed, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv8i16, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv8i16_indexed, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MULv8i8, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv2i32, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv2s_msl, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv4i16, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv4i32, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv4s_msl, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_MVNIv8i16, ARM64_INS_MVNI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv16i8, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv1i64, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv2i32, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv2i64, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv4i16, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv4i32, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv8i16, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NEGv8i8, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NOTv16i8, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_NOTv8i8, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORNWrs, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORNXrs, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORNv16i8, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORNv8i8, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRWri, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRWrs, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRXri, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRXrs, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv16i8, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv2i32, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv4i16, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv4i32, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv8i16, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ORRv8i8, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULLv16i8, ARM64_INS_PMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULLv1i64, ARM64_INS_PMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULLv2i64, ARM64_INS_PMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULLv8i8, ARM64_INS_PMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULv16i8, ARM64_INS_PMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_PMULv8i8, ARM64_INS_PMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_PRFMl, ARM64_INS_PRFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_PRFMroW, ARM64_INS_PRFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_PRFMroX, ARM64_INS_PRFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_PRFMui, ARM64_INS_PRFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_PRFUMi, ARM64_INS_PRFUM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RBITWr, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RBITXr, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RBITv16i8, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RBITv8i8, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RET, ARM64_INS_RET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_RET, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV16Wr, ARM64_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_REV16Xr, ARM64_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_REV16v16i8, ARM64_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV16v8i8, ARM64_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV32Xr, ARM64_INS_REV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_REV32v16i8, ARM64_INS_REV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV32v4i16, ARM64_INS_REV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV32v8i16, ARM64_INS_REV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV32v8i8, ARM64_INS_REV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v16i8, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v2i32, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v4i16, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v4i32, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v8i16, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REV64v8i8, ARM64_INS_REV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_REVWr, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_REVXr, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RORVWr, ARM64_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RORVXr, ARM64_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv16i8, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv2i32, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv4i16, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv4i32, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv8i16, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABAv8i8, ARM64_INS_SABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv16i8, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv2i32, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv4i16, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv4i32, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv8i16, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SABDv8i8, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLVv16i8v, ARM64_INS_SADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLVv4i16v, ARM64_INS_SADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLVv4i32v, ARM64_INS_SADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLVv8i16v, ARM64_INS_SADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLVv8i8v, ARM64_INS_SADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SBCSWr, ARM64_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SBCSXr, ARM64_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SBCWr, ARM64_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SBCXr, ARM64_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SBFMWri, ARM64_INS_SBFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SBFMXri, ARM64_INS_SBFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFSWDri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFSWSri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFSXDri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFSXSri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFUWDri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFUWSri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFUXDri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFUXSri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFd, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFs, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv1i32, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv1i64, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv2f32, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv2f64, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv4f32, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SDIVWr, ARM64_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SDIVXr, ARM64_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SDIV_IntWr, ARM64_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SDIV_IntXr, ARM64_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1Crrr, ARM64_INS_SHA1C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1Hrr, ARM64_INS_SHA1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1Mrrr, ARM64_INS_SHA1M, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1Prrr, ARM64_INS_SHA1P, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA256H2rrr, ARM64_INS_SHA256H2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA256Hrrr, ARM64_INS_SHA256H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv16i8, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv2i32, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv4i16, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv4i32, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv8i16, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHADDv8i8, ARM64_INS_SHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv16i8, ARM64_INS_SHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv2i32, ARM64_INS_SHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv4i16, ARM64_INS_SHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv4i32, ARM64_INS_SHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv8i16, ARM64_INS_SHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLLv8i8, ARM64_INS_SHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLd, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv16i8_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv2i32_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv2i64_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv4i16_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv4i32_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv8i16_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHLv8i8_shift, ARM64_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv2i32_shift, ARM64_INS_SHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv4i16_shift, ARM64_INS_SHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHRNv8i8_shift, ARM64_INS_SHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv16i8, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv2i32, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv4i16, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv4i32, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv8i16, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SHSUBv8i8, ARM64_INS_SHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLId, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv16i8_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv2i32_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv2i64_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv4i16_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv4i32_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv8i16_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SLIv8i8_shift, ARM64_INS_SLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMADDLrrr, ARM64_INS_SMADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv16i8, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv2i32, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv4i16, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv4i32, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv8i16, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXPv8i8, ARM64_INS_SMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXVv16i8v, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXVv4i16v, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXVv4i32v, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXVv8i16v, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXVv8i8v, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv16i8, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv2i32, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv4i16, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv4i32, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv8i16, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMAXv8i8, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMC, ARM64_INS_SMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv16i8, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv2i32, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv4i16, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv4i32, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv8i16, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINPv8i8, ARM64_INS_SMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINVv16i8v, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINVv4i16v, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINVv4i32v, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINVv8i16v, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINVv8i8v, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv16i8, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv2i32, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv4i16, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv4i32, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv8i16, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMINv8i8, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMOVvi16to32, ARM64_INS_SMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMOVvi16to64, ARM64_INS_SMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMOVvi32to64, ARM64_INS_SMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMOVvi8to32, ARM64_INS_SMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMOVvi8to64, ARM64_INS_SMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMSUBLrrr, ARM64_INS_SMSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULHrr, ARM64_INS_SMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv16i8, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv1i16, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv1i32, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv1i64, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv1i8, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv2i32, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv2i64, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv4i16, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv4i32, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv8i16, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQABSv8i8, ARM64_INS_SQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv16i8, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv1i16, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv1i32, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv1i64, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv1i8, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv2i32, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv2i64, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv4i16, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv4i32, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv8i16, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQADDv8i8, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALi16, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALi32, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLi16, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLi32, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv16i8, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv1i16, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv1i32, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv1i64, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv1i8, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv2i32, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv2i64, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv4i16, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv4i32, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv8i16, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQNEGv8i8, ARM64_INS_SQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNb, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNh, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNs, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUb, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUd, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUh, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUs, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLb, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLd, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLh, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLs, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv16i8, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv1i16, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv1i32, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv1i64, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv1i8, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv2i32, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv2i64, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv4i16, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv4i32, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv8i16, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv8i8, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNb, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNh, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNs, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNb, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNh, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNs, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv16i8, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv1i16, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv1i32, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv1i64, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv1i8, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv2i32, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv2i64, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv4i16, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv4i32, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv8i16, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQSUBv8i8, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv16i8, ARM64_INS_SQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv1i16, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv1i32, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv1i8, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv2i32, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv4i16, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv4i32, ARM64_INS_SQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv8i16, ARM64_INS_SQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTNv8i8, ARM64_INS_SQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv16i8, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv2i32, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv4i16, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv4i32, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv8i16, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRHADDv8i8, ARM64_INS_SRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRId, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv16i8_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv2i32_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv2i64_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv4i16_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv4i32_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv8i16_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRIv8i8_shift, ARM64_INS_SRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv16i8, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv1i64, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv2i32, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv2i64, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv4i16, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv4i32, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv8i16, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHLv8i8, ARM64_INS_SRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRd, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAd, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv16i8, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv1i64, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv2i32, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv2i64, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv4i16, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv4i32, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv8i16, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHLv8i8, ARM64_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRd, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv16i8_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv2i32_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv2i64_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv4i16_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv4i32_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv8i16_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSHRv8i8_shift, ARM64_INS_SSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAd, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv16i8_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv2i32_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv2i64_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv4i16_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv4i32_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv8i16_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSRAv8i8_shift, ARM64_INS_SSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv16b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv16b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv1d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv1d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv2d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv2d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv2s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv2s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv4h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv4h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv4s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv4s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv8b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv8b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv8h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Fourv8h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev16b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev16b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev1d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev1d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev2d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev2d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev2s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev2s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev4h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev4h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev4s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev4s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev8b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev8b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev8h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Onev8h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev16b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev16b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev1d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev1d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev2d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev2d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev2s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev2s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev4h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev4h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev4s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev4s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev8b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev8b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev8h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Threev8h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov16b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov16b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov1d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov1d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov2d, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov2d_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov2s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov2s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov4h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov4h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov4s, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov4s_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov8b, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov8b_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov8h, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1Twov8h_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i16, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i16_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i32, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i32_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i64, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i64_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i8, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST1i8_POST, ARM64_INS_ST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov16b, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov16b_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov2d, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov2d_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov2s, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov2s_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov4h, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov4h_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov4s, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov4s_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov8b, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov8b_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov8h, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2Twov8h_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i16, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i16_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i32, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i32_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i64, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i64_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i8, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST2i8_POST, ARM64_INS_ST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev16b, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev16b_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev2d, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev2d_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev2s, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev2s_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev4h, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev4h_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev4s, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev4s_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev8b, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev8b_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev8h, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3Threev8h_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i16, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i16_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i32, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i32_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i64, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i64_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i8, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST3i8_POST, ARM64_INS_ST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv16b, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv16b_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv2d, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv2d_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv2s, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv2s_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv4h, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv4h_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv4s, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv4s_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv8b, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv8b_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv8h, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4Fourv8h_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i16, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i16_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i32, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i32_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i64, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i64_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i8, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ST4i8_POST, ARM64_INS_ST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_STLRB, ARM64_INS_STLRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLRH, ARM64_INS_STLRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLRW, ARM64_INS_STLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLRX, ARM64_INS_STLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXPW, ARM64_INS_STLXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXPX, ARM64_INS_STLXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXRB, ARM64_INS_STLXRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXRH, ARM64_INS_STLXRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXRW, ARM64_INS_STLXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STLXRX, ARM64_INS_STLXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STNPDi, ARM64_INS_STNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STNPQi, ARM64_INS_STNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STNPSi, ARM64_INS_STNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STNPWi, ARM64_INS_STNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STNPXi, ARM64_INS_STNP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPDi, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPDpost, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPDpre, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPQi, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPQpost, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPQpre, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPSi, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPSpost, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPSpre, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPWi, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPWpost, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPWpre, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPXi, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPXpost, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STPXpre, ARM64_INS_STP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBBpost, ARM64_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBBpre, ARM64_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBBroW, ARM64_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBBroX, ARM64_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBBui, ARM64_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRBui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRDpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRDpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRDroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRDroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRDui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHHpost, ARM64_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHHpre, ARM64_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHHroW, ARM64_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHHroX, ARM64_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHHui, ARM64_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRHui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRQpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRQpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRQroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRQroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRQui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRSpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRSpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRSroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRSroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRSui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRWpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRWpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRWroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRWroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRWui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRXpost, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRXpre, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRXroW, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRXroX, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STRXui, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STTRBi, ARM64_INS_STTRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STTRHi, ARM64_INS_STTRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STTRWi, ARM64_INS_STTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STTRXi, ARM64_INS_STTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURBBi, ARM64_INS_STURB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURBi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURDi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURHHi, ARM64_INS_STURH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURHi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURQi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURSi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURWi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STURXi, ARM64_INS_STUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXPW, ARM64_INS_STXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXPX, ARM64_INS_STXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXRB, ARM64_INS_STXRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXRH, ARM64_INS_STXRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXRW, ARM64_INS_STXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_STXRX, ARM64_INS_STXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSWri, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSWrs, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSWrx, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSXri, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSXrs, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSXrx, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBSXrx64, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBWri, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBWrs, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBWrx, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBXri, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBXrs, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBXrx, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBXrx64, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv16i8, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv1i64, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv2i32, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv2i64, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv4i16, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv4i32, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv8i16, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUBv8i8, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv16i8, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv1i16, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv1i32, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv1i64, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv1i8, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv2i32, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv2i64, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv4i16, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv4i32, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv8i16, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SUQADDv8i8, ARM64_INS_SUQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_SVC, ARM64_INS_SVC, +#ifndef CAPSTONE_DIET + { 0, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_INT, 0 }, 0, 0 +#endif +}, +{ + AArch64_SYSLxt, ARM64_INS_SYSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_SYSxt, ARM64_INS_SYS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv16i8Four, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv16i8One, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv16i8Three, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv16i8Two, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv8i8Four, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv8i8One, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv8i8Three, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBLv8i8Two, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBNZW, ARM64_INS_TBNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_TBNZX, ARM64_INS_TBNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_TBXv16i8Four, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv16i8One, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv16i8Three, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv16i8Two, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv8i8Four, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv8i8One, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv8i8Three, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBXv8i8Two, ARM64_INS_TBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TBZW, ARM64_INS_TBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_TBZX, ARM64_INS_TBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 +#endif +}, +{ + AArch64_TRN1v16i8, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v2i32, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v2i64, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v4i16, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v4i32, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v8i16, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN1v8i8, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v16i8, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v2i32, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v2i64, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v4i16, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v4i32, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v8i16, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_TRN2v8i8, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv16i8, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv2i32, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv4i16, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv4i32, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv8i16, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABAv8i8, ARM64_INS_UABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv16i8, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv2i32, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv4i16, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv4i32, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv8i16, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UABDv8i8, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLVv16i8v, ARM64_INS_UADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLVv4i16v, ARM64_INS_UADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLVv4i32v, ARM64_INS_UADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLVv8i16v, ARM64_INS_UADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLVv8i8v, ARM64_INS_UADDLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UBFMWri, ARM64_INS_UBFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UBFMXri, ARM64_INS_UBFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFSWDri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFSWSri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFSXDri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFSXSri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFUWDri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFUWSri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFUXDri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFUXSri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFd, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFs, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv1i32, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv1i64, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv2f32, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv2f64, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv4f32, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UDIVWr, ARM64_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UDIVXr, ARM64_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UDIV_IntWr, ARM64_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UDIV_IntXr, ARM64_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv16i8, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv2i32, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv4i16, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv4i32, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv8i16, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHADDv8i8, ARM64_INS_UHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv16i8, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv2i32, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv4i16, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv4i32, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv8i16, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UHSUBv8i8, ARM64_INS_UHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMADDLrrr, ARM64_INS_UMADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv16i8, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv2i32, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv4i16, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv4i32, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv8i16, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXPv8i8, ARM64_INS_UMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXVv16i8v, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXVv4i16v, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXVv4i32v, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXVv8i16v, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXVv8i8v, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv16i8, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv2i32, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv4i16, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv4i32, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv8i16, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMAXv8i8, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv16i8, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv2i32, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv4i16, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv4i32, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv8i16, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINPv8i8, ARM64_INS_UMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINVv16i8v, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINVv4i16v, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINVv4i32v, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINVv8i16v, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINVv8i8v, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv16i8, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv2i32, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv4i16, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv4i32, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv8i16, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMINv8i8, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMOVvi16, ARM64_INS_UMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMOVvi32, ARM64_INS_UMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMOVvi64, ARM64_INS_UMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMOVvi8, ARM64_INS_UMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMSUBLrrr, ARM64_INS_UMSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULHrr, ARM64_INS_UMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv16i8, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv1i16, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv1i32, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv1i64, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv1i8, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv2i32, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv2i64, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv4i16, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv4i32, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv8i16, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQADDv8i8, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNb, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNh, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNs, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLb, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLd, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLh, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLs, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv16i8, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv1i16, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv1i32, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv1i64, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv1i8, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv2i32, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv2i64, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv4i16, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv4i32, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv8i16, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv8i8, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNb, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNh, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNs, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv16i8, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv1i16, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv1i32, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv1i64, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv1i8, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv2i32, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv2i64, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv4i16, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv4i32, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv8i16, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQSUBv8i8, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv16i8, ARM64_INS_UQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv1i16, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv1i32, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv1i8, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv2i32, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv4i16, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv4i32, ARM64_INS_UQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv8i16, ARM64_INS_UQXTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UQXTNv8i8, ARM64_INS_UQXTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URECPEv2i32, ARM64_INS_URECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URECPEv4i32, ARM64_INS_URECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv16i8, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv2i32, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv4i16, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv4i32, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv8i16, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URHADDv8i8, ARM64_INS_URHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv16i8, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv1i64, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv2i32, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv2i64, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv4i16, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv4i32, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv8i16, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHLv8i8, ARM64_INS_URSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRd, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv16i8_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv2i32_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv2i64_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv4i16_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv4i32_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv8i16_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSHRv8i8_shift, ARM64_INS_URSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAd, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv16i8_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv2i32_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv2i64_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv4i16_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv4i32_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv8i16_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_URSRAv8i8_shift, ARM64_INS_URSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv2i32_shift, ARM64_INS_USHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv4i16_shift, ARM64_INS_USHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLLv8i8_shift, ARM64_INS_USHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv16i8, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv1i64, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv2i32, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv2i64, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv4i16, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv4i32, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv8i16, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHLv8i8, ARM64_INS_USHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRd, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv16i8_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv2i32_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv2i64_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv4i16_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv4i32_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv8i16_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USHRv8i8_shift, ARM64_INS_USHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv16i8, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv1i16, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv1i32, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv1i64, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv1i8, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv2i32, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv2i64, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv4i16, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv4i32, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv8i16, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USQADDv8i8, ARM64_INS_USQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAd, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv16i8_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv2i32_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv2i64_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv4i16_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv4i32_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv8i16_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USRAv8i8_shift, ARM64_INS_USRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v16i8, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v2i32, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v2i64, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v4i16, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v4i32, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v8i16, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP1v8i8, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v16i8, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v2i32, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v2i64, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v4i16, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v4i32, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v8i16, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_UZP2v8i8, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv16i8, ARM64_INS_XTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv2i32, ARM64_INS_XTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv4i16, ARM64_INS_XTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv4i32, ARM64_INS_XTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv8i16, ARM64_INS_XTN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_XTNv8i8, ARM64_INS_XTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v16i8, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v2i32, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v2i64, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v4i16, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v4i32, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v8i16, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP1v8i8, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v16i8, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v2i32, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v2i64, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v4i16, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v4i32, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v8i16, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, +{ + AArch64_ZIP2v8i8, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsnOp.inc b/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsnOp.inc new file mode 100644 index 0000000..15d5541 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64MappingInsnOp.inc @@ -0,0 +1,9308 @@ +{ /* AArch64_ABSv16i8, ARM64_INS_ABS: abs.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv1i64, ARM64_INS_ABS: abs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv2i32, ARM64_INS_ABS: abs.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv2i64, ARM64_INS_ABS: abs.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv4i16, ARM64_INS_ABS: abs.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv4i32, ARM64_INS_ABS: abs.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv8i16, ARM64_INS_ABS: abs.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ABSv8i8, ARM64_INS_ABS: abs.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADCWr, ARM64_INS_ADC: adc $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADCXr, ARM64_INS_ADC: adc $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN: addhn.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2: addhn2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN: addhn.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2: addhn2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2: addhn2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN: addhn.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv16i8, ARM64_INS_ADDP: addp.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv2i32, ARM64_INS_ADDP: addp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv2i64, ARM64_INS_ADDP: addp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv2i64p, ARM64_INS_ADDP: addp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv4i16, ARM64_INS_ADDP: addp.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv4i32, ARM64_INS_ADDP: addp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv8i16, ARM64_INS_ADDP: addp.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDPv8i8, ARM64_INS_ADDP: addp.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSWri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ,0 } +}, +{ /* AArch64_ADDSWrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSWrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSXri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSXrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSXrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDSXrx64, ARM64_INS_ADDS: adds $rd, $rn, $rm$ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDVv16i8v, ARM64_INS_ADDV: addv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDVv4i16v, ARM64_INS_ADDV: addv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDVv4i32v, ARM64_INS_ADDV: addv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDVv8i16v, ARM64_INS_ADDV: addv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDVv8i8v, ARM64_INS_ADDV: addv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDWri, ARM64_INS_ADD: add $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDWrs, ARM64_INS_ADD: add $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDWrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDXri, ARM64_INS_ADD: add $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDXrs, ARM64_INS_ADD: add $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDXrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDXrx64, ARM64_INS_ADD: add $rd, $rn, $rm$ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv16i8, ARM64_INS_ADD: add.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv1i64, ARM64_INS_ADD: add $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv2i32, ARM64_INS_ADD: add.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv2i64, ARM64_INS_ADD: add.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv4i16, ARM64_INS_ADD: add.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv4i32, ARM64_INS_ADD: add.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv8i16, ARM64_INS_ADD: add.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADDv8i8, ARM64_INS_ADD: add.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ADR, ARM64_INS_ADR: adr $xd, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ADRP, ARM64_INS_ADRP: adrp $xd, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_AESDrr, ARM64_INS_AESD: aesd.16b $rd, $rn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_AESErr, ARM64_INS_AESE: aese.16b $rd, $rn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_AESIMCrr, ARM64_INS_AESIMC: aesimc.16b $rd, $rn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_AESMCrr, ARM64_INS_AESMC: aesmc.16b $rd, $rn */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDSWri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDSWrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDSXri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDSXrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDWri, ARM64_INS_AND: and $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDWrs, ARM64_INS_AND: and $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDXri, ARM64_INS_AND: and $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDXrs, ARM64_INS_AND: and $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDv16i8, ARM64_INS_AND: and.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ANDv8i8, ARM64_INS_AND: and.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ASRVWr, ARM64_INS_ASR: asr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ASRVXr, ARM64_INS_ASR: asr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_B, ARM64_INS_B: b $addr */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_BFMWri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_BFMXri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_BICSWrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BICSXrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BICWrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BICXrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv16i8, ARM64_INS_BIC: bic.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv2i32, ARM64_INS_BIC: bic.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv4i16, ARM64_INS_BIC: bic.4h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv4i32, ARM64_INS_BIC: bic.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv8i16, ARM64_INS_BIC: bic.8h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_BICv8i8, ARM64_INS_BIC: bic.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_BIFv16i8, ARM64_INS_BIF: bif.16b $rd, $rn, $rm| */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BIFv8i8, ARM64_INS_BIF: bif.8b $rd, $rn, $rm| */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BITv16i8, ARM64_INS_BIT: bit.16b $rd, $rn, $rm */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BITv8i8, ARM64_INS_BIT: bit.8b $rd, $rn, $rm */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BL, ARM64_INS_BL: bl $addr */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_BLR, ARM64_INS_BLR: blr $rn */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_BR, ARM64_INS_BR: br $rn */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_BRK, ARM64_INS_BRK: brk $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_BSLv16i8, ARM64_INS_BSL: bsl.16b $rd, $rn, $rm */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_BSLv8i8, ARM64_INS_BSL: bsl.8b $rd, $rn, $rm */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_Bcc, ARM64_INS_B: b.$cond $target */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_CBNZW, ARM64_INS_CBNZ: cbnz $rt, $target */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CBNZX, ARM64_INS_CBNZ: cbnz $rt, $target */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CBZW, ARM64_INS_CBZ: cbz $rt, $target */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CBZX, ARM64_INS_CBZ: cbz $rt, $target */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CCMNWi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMNWr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMNXi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMNXr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMPWi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMPWr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMPXi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CCMPXr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CLREX, ARM64_INS_CLREX: clrex $crm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_CLSWr, ARM64_INS_CLS: cls $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSXr, ARM64_INS_CLS: cls $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv16i8, ARM64_INS_CLS: cls.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv2i32, ARM64_INS_CLS: cls.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv4i16, ARM64_INS_CLS: cls.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv4i32, ARM64_INS_CLS: cls.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv8i16, ARM64_INS_CLS: cls.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLSv8i8, ARM64_INS_CLS: cls.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZWr, ARM64_INS_CLZ: clz $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZXr, ARM64_INS_CLZ: clz $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv16i8, ARM64_INS_CLZ: clz.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv2i32, ARM64_INS_CLZ: clz.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv4i16, ARM64_INS_CLZ: clz.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv4i32, ARM64_INS_CLZ: clz.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv8i16, ARM64_INS_CLZ: clz.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CLZv8i8, ARM64_INS_CLZ: clz.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv16i8, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv16i8rz, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv1i64, ARM64_INS_CMEQ: cmeq $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv1i64rz, ARM64_INS_CMEQ: cmeq $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv2i32, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv2i32rz, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv2i64, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv2i64rz, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv4i16, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv4i16rz, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv4i32, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv4i32rz, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv8i16, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv8i16rz, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv8i8, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMEQv8i8rz, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv16i8, ARM64_INS_CMGE: cmge.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv16i8rz, ARM64_INS_CMGE: cmge.16b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv1i64, ARM64_INS_CMGE: cmge $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv1i64rz, ARM64_INS_CMGE: cmge $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv2i32, ARM64_INS_CMGE: cmge.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv2i32rz, ARM64_INS_CMGE: cmge.2s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv2i64, ARM64_INS_CMGE: cmge.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv2i64rz, ARM64_INS_CMGE: cmge.2d $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv4i16, ARM64_INS_CMGE: cmge.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv4i16rz, ARM64_INS_CMGE: cmge.4h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv4i32, ARM64_INS_CMGE: cmge.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv4i32rz, ARM64_INS_CMGE: cmge.4s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv8i16, ARM64_INS_CMGE: cmge.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv8i16rz, ARM64_INS_CMGE: cmge.8h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv8i8, ARM64_INS_CMGE: cmge.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGEv8i8rz, ARM64_INS_CMGE: cmge.8b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv16i8, ARM64_INS_CMGT: cmgt.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv16i8rz, ARM64_INS_CMGT: cmgt.16b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv1i64, ARM64_INS_CMGT: cmgt $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv1i64rz, ARM64_INS_CMGT: cmgt $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv2i32, ARM64_INS_CMGT: cmgt.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv2i32rz, ARM64_INS_CMGT: cmgt.2s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv2i64, ARM64_INS_CMGT: cmgt.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv2i64rz, ARM64_INS_CMGT: cmgt.2d $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv4i16, ARM64_INS_CMGT: cmgt.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv4i16rz, ARM64_INS_CMGT: cmgt.4h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv4i32, ARM64_INS_CMGT: cmgt.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv4i32rz, ARM64_INS_CMGT: cmgt.4s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv8i16, ARM64_INS_CMGT: cmgt.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv8i16rz, ARM64_INS_CMGT: cmgt.8h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv8i8, ARM64_INS_CMGT: cmgt.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMGTv8i8rz, ARM64_INS_CMGT: cmgt.8b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv16i8, ARM64_INS_CMHI: cmhi.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv1i64, ARM64_INS_CMHI: cmhi $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv2i32, ARM64_INS_CMHI: cmhi.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv2i64, ARM64_INS_CMHI: cmhi.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv4i16, ARM64_INS_CMHI: cmhi.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv4i32, ARM64_INS_CMHI: cmhi.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv8i16, ARM64_INS_CMHI: cmhi.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHIv8i8, ARM64_INS_CMHI: cmhi.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv16i8, ARM64_INS_CMHS: cmhs.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv1i64, ARM64_INS_CMHS: cmhs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv2i32, ARM64_INS_CMHS: cmhs.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv2i64, ARM64_INS_CMHS: cmhs.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv4i16, ARM64_INS_CMHS: cmhs.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv4i32, ARM64_INS_CMHS: cmhs.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv8i16, ARM64_INS_CMHS: cmhs.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMHSv8i8, ARM64_INS_CMHS: cmhs.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv16i8rz, ARM64_INS_CMLE: cmle.16b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv1i64rz, ARM64_INS_CMLE: cmle $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv2i32rz, ARM64_INS_CMLE: cmle.2s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv2i64rz, ARM64_INS_CMLE: cmle.2d $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv4i16rz, ARM64_INS_CMLE: cmle.4h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv4i32rz, ARM64_INS_CMLE: cmle.4s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv8i16rz, ARM64_INS_CMLE: cmle.8h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLEv8i8rz, ARM64_INS_CMLE: cmle.8b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv16i8rz, ARM64_INS_CMLT: cmlt.16b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv1i64rz, ARM64_INS_CMLT: cmlt $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv2i32rz, ARM64_INS_CMLT: cmlt.2s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv2i64rz, ARM64_INS_CMLT: cmlt.2d $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv4i16rz, ARM64_INS_CMLT: cmlt.4h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv4i32rz, ARM64_INS_CMLT: cmlt.4s $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv8i16rz, ARM64_INS_CMLT: cmlt.8h $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMLTv8i8rz, ARM64_INS_CMLT: cmlt.8b $rd, $rn, #0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv16i8, ARM64_INS_CMTST: cmtst.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv1i64, ARM64_INS_CMTST: cmtst $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv2i32, ARM64_INS_CMTST: cmtst.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv2i64, ARM64_INS_CMTST: cmtst.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv4i16, ARM64_INS_CMTST: cmtst.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv4i32, ARM64_INS_CMTST: cmtst.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv8i16, ARM64_INS_CMTST: cmtst.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CMTSTv8i8, ARM64_INS_CMTST: cmtst.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CNTv16i8, ARM64_INS_CNT: cnt.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CNTv8i8, ARM64_INS_CNT: cnt.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_CPYi16, ARM64_INS_MOV: mov $dst, $src$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CPYi32, ARM64_INS_MOV: mov $dst, $src$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CPYi64, ARM64_INS_MOV: mov $dst, $src$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CPYi8, ARM64_INS_MOV: mov $dst, $src$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32Brr, ARM64_INS_CRC32B: crc32b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32CBrr, ARM64_INS_CRC32CB: crc32cb $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32CHrr, ARM64_INS_CRC32CH: crc32ch $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32CWrr, ARM64_INS_CRC32CW: crc32cw $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32CXrr, ARM64_INS_CRC32CX: crc32cx $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32Hrr, ARM64_INS_CRC32H: crc32h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32Wrr, ARM64_INS_CRC32W: crc32w $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CRC32Xrr, ARM64_INS_CRC32X: crc32x $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_CSELWr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSELXr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSINCWr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSINCXr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSINVWr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSINVXr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSNEGWr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_CSNEGXr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_DCPS1, ARM64_INS_DCPS1: dcps1 $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_DCPS2, ARM64_INS_DCPS2: dcps2 $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_DCPS3, ARM64_INS_DCPS3: dcps3 $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_DMB, ARM64_INS_DMB: dmb $crm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_DRPS, ARM64_INS_DRPS: drps */ + 0, + { 0 } +}, +{ /* AArch64_DSB, ARM64_INS_DSB: dsb $crm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv16i8gpr, ARM64_INS_DUP: dup.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv16i8lane, ARM64_INS_DUP: dup.16b $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv2i32gpr, ARM64_INS_DUP: dup.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv2i32lane, ARM64_INS_DUP: dup.2s $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv2i64gpr, ARM64_INS_DUP: dup.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv2i64lane, ARM64_INS_DUP: dup.2d $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv4i16gpr, ARM64_INS_DUP: dup.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv4i16lane, ARM64_INS_DUP: dup.4h $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv4i32gpr, ARM64_INS_DUP: dup.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv4i32lane, ARM64_INS_DUP: dup.4s $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv8i16gpr, ARM64_INS_DUP: dup.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv8i16lane, ARM64_INS_DUP: dup.8h $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv8i8gpr, ARM64_INS_DUP: dup.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_DUPv8i8lane, ARM64_INS_DUP: dup.8b $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EONWrs, ARM64_INS_EON: eon $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EONXrs, ARM64_INS_EON: eon $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORWri, ARM64_INS_EOR: eor $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORWrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORXri, ARM64_INS_EOR: eor $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORXrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORv16i8, ARM64_INS_EOR: eor.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_EORv8i8, ARM64_INS_EOR: eor.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ERET, ARM64_INS_ERET: eret */ + 0, + { 0 } +}, +{ /* AArch64_EXTRWrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_EXTRXrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_EXTv16i8, ARM64_INS_EXT: ext.16b $rd, $rn, $rm, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_EXTv8i8, ARM64_INS_EXT: ext.8b $rd, $rn, $rm, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FABD32, ARM64_INS_FABD: fabd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FABD64, ARM64_INS_FABD: fabd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FABDv2f32, ARM64_INS_FABD: fabd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FABDv2f64, ARM64_INS_FABD: fabd.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FABDv4f32, ARM64_INS_FABD: fabd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FABSDr, ARM64_INS_FABS: fabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FABSSr, ARM64_INS_FABS: fabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FABSv2f32, ARM64_INS_FABS: fabs.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FABSv2f64, ARM64_INS_FABS: fabs.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FABSv4f32, ARM64_INS_FABS: fabs.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGE32, ARM64_INS_FACGE: facge $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGE64, ARM64_INS_FACGE: facge $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGEv2f32, ARM64_INS_FACGE: facge.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGEv2f64, ARM64_INS_FACGE: facge.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGEv4f32, ARM64_INS_FACGE: facge.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGT32, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGT64, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGTv2f32, ARM64_INS_FACGT: facgt.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGTv2f64, ARM64_INS_FACGT: facgt.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FACGTv4f32, ARM64_INS_FACGT: facgt.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDDrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDPv2f32, ARM64_INS_FADDP: faddp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDPv2f64, ARM64_INS_FADDP: faddp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDPv2i32p, ARM64_INS_FADDP: faddp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDPv2i64p, ARM64_INS_FADDP: faddp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDPv4f32, ARM64_INS_FADDP: faddp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDSrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDv2f32, ARM64_INS_FADD: fadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDv2f64, ARM64_INS_FADD: fadd.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FADDv4f32, ARM64_INS_FADD: fadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCCMPDrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } +}, +{ /* AArch64_FCCMPEDrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } +}, +{ /* AArch64_FCCMPESrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } +}, +{ /* AArch64_FCCMPSrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } +}, +{ /* AArch64_FCMEQ32, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQ64, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv2f32, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv2f64, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv4f32, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGE32, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGE64, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv2f32, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv2f64, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv4f32, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGT32, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGT64, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv2f32, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv2f64, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv4f32, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE: fcmle.2s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE: fcmle.2d $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE: fcmle.4s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT: fcmlt.2s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT: fcmlt.2d $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT: fcmlt.4s $rd, $rn, #0.0 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPDri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPDrr, ARM64_INS_FCMP: fcmp $rn, $rm */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPEDri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPEDrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPESri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPESrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPSri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCMPSrr, ARM64_INS_FCMP: fcmp $rn, $rm */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCSELDrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FCSELSrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FCVTASUWDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASUWSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASUXDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASUXSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASv1i32, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASv1i64, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASv2f32, ARM64_INS_FCVTAS: fcvtas.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASv2f64, ARM64_INS_FCVTAS: fcvtas.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTASv4f32, ARM64_INS_FCVTAS: fcvtas.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU: fcvtau.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU: fcvtau.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU: fcvtau.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTDHr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTDSr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTHDr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTHSr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTLv2i32, ARM64_INS_FCVTL: fcvtl $rd.2d, $rn.2s */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTLv4i16, ARM64_INS_FCVTL: fcvtl $rd.4s, $rn.4h */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTLv4i32, ARM64_INS_FCVTL2: fcvtl2 $rd.2d, $rn.4s */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTLv8i16, ARM64_INS_FCVTL2: fcvtl2 $rd.4s, $rn.8h */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS: fcvtms.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS: fcvtms.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS: fcvtms.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU: fcvtmu.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU: fcvtmu.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU: fcvtmu.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS: fcvtns.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS: fcvtns.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS: fcvtns.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU: fcvtnu.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU: fcvtnu.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU: fcvtnu.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNv2i32, ARM64_INS_FCVTN: fcvtn $rd.2s, $rn.2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNv4i16, ARM64_INS_FCVTN: fcvtn $rd.4h, $rn.4s */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNv4i32, ARM64_INS_FCVTN2: fcvtn2 $rd.4s, $rn.2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTNv8i16, ARM64_INS_FCVTN2: fcvtn2 $rd.8h, $rn.4s */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS: fcvtps.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS: fcvtps.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS: fcvtps.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU: fcvtpu.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU: fcvtpu.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU: fcvtpu.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTSDr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTSHr, ARM64_INS_FCVT: fcvt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN: fcvtxn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN: fcvtxn $rd.2s, $rn.2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2: fcvtxn2 $rd.4s, $rn.2d */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSd, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSs, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUd, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUs, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FDIVDrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FDIVSrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FDIVv2f32, ARM64_INS_FDIV: fdiv.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FDIVv2f64, ARM64_INS_FDIV: fdiv.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FDIVv4f32, ARM64_INS_FDIV: fdiv.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMADDDrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMADDSrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMAXDrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMDrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP: fmaxnmp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMSrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV: fmaxnmv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM: fmaxnm.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM: fmaxnm.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM: fmaxnm.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXPv2f32, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXPv2f64, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXPv2i32p, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXPv2i64p, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXPv4f32, ARM64_INS_FMAXP: fmaxp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXSrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXVv4i32v, ARM64_INS_FMAXV: fmaxv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXv2f32, ARM64_INS_FMAX: fmax.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXv2f64, ARM64_INS_FMAX: fmax.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMAXv4f32, ARM64_INS_FMAX: fmax.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINDrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMDrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP: fminnmp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMSrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV: fminnmv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMv2f32, ARM64_INS_FMINNM: fminnm.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMv2f64, ARM64_INS_FMINNM: fminnm.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINNMv4f32, ARM64_INS_FMINNM: fminnm.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINPv2f32, ARM64_INS_FMINP: fminp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINPv2f64, ARM64_INS_FMINP: fminp.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINPv2i32p, ARM64_INS_FMINP: fminp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINPv2i64p, ARM64_INS_FMINP: fminp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINPv4f32, ARM64_INS_FMINP: fminp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINSrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINVv4i32v, ARM64_INS_FMINV: fminv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINv2f32, ARM64_INS_FMIN: fmin.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINv2f64, ARM64_INS_FMIN: fmin.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMINv4f32, ARM64_INS_FMIN: fmin.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA: fmla.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA: fmla.d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLAv2f32, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLAv2f64, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLAv4f32, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS: fmls.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS: fmls.d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLSv2f32, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLSv2f64, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMLSv4f32, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMOVDXHighr, ARM64_INS_FMOV: fmov.d $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVDXr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVDi, ARM64_INS_FMOV: fmov $rd, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVDr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVSWr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVSi, ARM64_INS_FMOV: fmov $rd, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVSr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVWSr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVXDHighr, ARM64_INS_FMOV: fmov.d $rd$idx, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVXDr, ARM64_INS_FMOV: fmov $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FMOVv2f32_ns, ARM64_INS_FMOV: fmov.2s $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, +{ /* AArch64_FMOVv2f64_ns, ARM64_INS_FMOV: fmov.2d $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, +{ /* AArch64_FMOVv4f32_ns, ARM64_INS_FMOV: fmov.4s $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, +{ /* AArch64_FMSUBDrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMSUBSrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULDrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULSrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULX32, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULX64, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX: fmulx.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX: fmulx.d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULXv2f32, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULXv2f64, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULXv4f32, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULv1i32_indexed, ARM64_INS_FMUL: fmul.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULv1i64_indexed, ARM64_INS_FMUL: fmul.d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULv2f32, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULv2f64, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULv2i32_indexed, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULv2i64_indexed, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FMULv4f32, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FMULv4i32_indexed, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FNEGDr, ARM64_INS_FNEG: fneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FNEGSr, ARM64_INS_FNEG: fneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FNEGv2f32, ARM64_INS_FNEG: fneg.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FNEGv2f64, ARM64_INS_FNEG: fneg.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FNEGv4f32, ARM64_INS_FNEG: fneg.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FNMADDDrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FNMADDSrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_FNMULDrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FNMULSrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPEv1i32, ARM64_INS_FRECPE: frecpe $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPEv1i64, ARM64_INS_FRECPE: frecpe $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPEv2f32, ARM64_INS_FRECPE: frecpe.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPEv2f64, ARM64_INS_FRECPE: frecpe.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPEv4f32, ARM64_INS_FRECPE: frecpe.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPS32, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPS64, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPSv2f32, ARM64_INS_FRECPS: frecps.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPSv2f64, ARM64_INS_FRECPS: frecps.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPSv4f32, ARM64_INS_FRECPS: frecps.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPXv1i32, ARM64_INS_FRECPX: frecpx $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRECPXv1i64, ARM64_INS_FRECPX: frecpx $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTADr, ARM64_INS_FRINTA: frinta $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTASr, ARM64_INS_FRINTA: frinta $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTAv2f32, ARM64_INS_FRINTA: frinta.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTAv2f64, ARM64_INS_FRINTA: frinta.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTAv4f32, ARM64_INS_FRINTA: frinta.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTIDr, ARM64_INS_FRINTI: frinti $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTISr, ARM64_INS_FRINTI: frinti $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTIv2f32, ARM64_INS_FRINTI: frinti.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTIv2f64, ARM64_INS_FRINTI: frinti.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTIv4f32, ARM64_INS_FRINTI: frinti.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTMDr, ARM64_INS_FRINTM: frintm $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTMSr, ARM64_INS_FRINTM: frintm $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTMv2f32, ARM64_INS_FRINTM: frintm.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTMv2f64, ARM64_INS_FRINTM: frintm.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTMv4f32, ARM64_INS_FRINTM: frintm.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTNDr, ARM64_INS_FRINTN: frintn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTNSr, ARM64_INS_FRINTN: frintn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTNv2f32, ARM64_INS_FRINTN: frintn.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTNv2f64, ARM64_INS_FRINTN: frintn.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTNv4f32, ARM64_INS_FRINTN: frintn.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTPDr, ARM64_INS_FRINTP: frintp $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTPSr, ARM64_INS_FRINTP: frintp $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTPv2f32, ARM64_INS_FRINTP: frintp.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTPv2f64, ARM64_INS_FRINTP: frintp.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTPv4f32, ARM64_INS_FRINTP: frintp.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTXDr, ARM64_INS_FRINTX: frintx $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTXSr, ARM64_INS_FRINTX: frintx $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTXv2f32, ARM64_INS_FRINTX: frintx.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTXv2f64, ARM64_INS_FRINTX: frintx.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTXv4f32, ARM64_INS_FRINTX: frintx.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTZDr, ARM64_INS_FRINTZ: frintz $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTZSr, ARM64_INS_FRINTZ: frintz $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTZv2f32, ARM64_INS_FRINTZ: frintz.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTZv2f64, ARM64_INS_FRINTZ: frintz.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRINTZv4f32, ARM64_INS_FRINTZ: frintz.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE: frsqrte.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE: frsqrte.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE: frsqrte.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTS32, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTS64, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS: frsqrts.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS: frsqrts.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS: frsqrts.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FSQRTDr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FSQRTSr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FSQRTv2f32, ARM64_INS_FSQRT: fsqrt.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FSQRTv2f64, ARM64_INS_FSQRT: fsqrt.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FSQRTv4f32, ARM64_INS_FSQRT: fsqrt.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_FSUBDrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FSUBSrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FSUBv2f32, ARM64_INS_FSUB: fsub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FSUBv2f64, ARM64_INS_FSUB: fsub.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_FSUBv4f32, ARM64_INS_FSUB: fsub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_HINT, ARM64_INS_HINT: hint $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_HLT, ARM64_INS_HLT: hlt $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_HVC, ARM64_INS_HVC: hvc $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_INSvi16gpr, ARM64_INS_INS: ins.h $rd$idx, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_INSvi16lane, ARM64_INS_INS: ins.h $rd$idx, $rn$idx2 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_INSvi32gpr, ARM64_INS_INS: ins.s $rd$idx, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_INSvi32lane, ARM64_INS_INS: ins.s $rd$idx, $rn$idx2 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_INSvi64gpr, ARM64_INS_INS: ins.d $rd$idx, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_INSvi64lane, ARM64_INS_INS: ins.d $rd$idx, $rn$idx2 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_INSvi8gpr, ARM64_INS_INS: ins.b $rd$idx, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_INSvi8lane, ARM64_INS_INS: ins.b $rd$idx, $rn$idx2 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_ISB, ARM64_INS_ISB: isb $crm */ + 0, + { 0 } +}, +{ /* AArch64_LD1Fourv16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Fourv8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD1Onev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Onev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv16b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv16b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv1d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv1d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv2d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv2d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv2s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv2s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv4h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv4h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv4s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv4s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv8b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv8b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv8h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Rv8h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Threev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1Twov8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i16, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i16_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i32, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i32_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i64, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i64_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i8, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD1i8_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv16b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv16b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv1d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv1d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv2d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv2d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv2s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv2s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv4h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv4h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv4s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv4s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv8b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv8b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv8h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Rv8h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD2Twov16b, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov16b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov2d, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov2d_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov2s, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov2s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov4h, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov4h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov4s, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov4s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov8b, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov8b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov8h, ARM64_INS_LD2: ld2 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2Twov8h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2i16, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2i16_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2i32, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2i32_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2i64, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2i64_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD2i8, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} +}, +{ /* AArch64_LD2i8_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LD3Rv16b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv16b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv1d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv1d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv2d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv2d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv2s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv2s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv4h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv4h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv4s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv4s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv8b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv8b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv8h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Rv8h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev16b, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev16b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev2d, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev2d_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev2s, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev2s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev4h, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev4h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev4s, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev4s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev8b, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev8b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev8h, ARM64_INS_LD3: ld3 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3Threev8h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD3i16, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3i16_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD3i32, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3i32_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD3i64, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3i64_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD3i8, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD3i8_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD4Fourv16b, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv16b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv2d, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv2d_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv2s, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv2s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv4h, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv4h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv4s, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv4s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv8b, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv8b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv8h, ARM64_INS_LD4: ld4 $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Fourv8h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv16b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv16b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv1d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv1d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv2d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv2d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv2s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv2s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv4h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv4h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv4s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv4s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv8b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv8b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv8h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4Rv8h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LD4i16, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4i16_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD4i32, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4i32_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD4i64, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4i64_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LD4i8, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_LD4i8_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDARB, ARM64_INS_LDARB: ldarb $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDARH, ARM64_INS_LDARH: ldarh $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDARW, ARM64_INS_LDAR: ldar $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDARX, ARM64_INS_LDAR: ldar $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXPW, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXPX, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXRB, ARM64_INS_LDAXRB: ldaxrb $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXRH, ARM64_INS_LDAXRH: ldaxrh $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXRW, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDAXRX, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDNPDi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDNPQi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDNPSi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDNPWi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDNPXi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPDi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPDpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPDpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPQi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPQpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPQpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSWi, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSWpost, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSWpre, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPSpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPWi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPWpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPWpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPXi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPXpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDPXpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRBBpost, ARM64_INS_LDRB: ldrb $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRBBpre, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRBBroW, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRBBroX, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRBBui, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRBpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRBpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRBroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRBroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRBui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRDl, ARM64_INS_LDR: ldr $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRDpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRDpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRDroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 00, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRDroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRDui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHHpost, ARM64_INS_LDRH: ldrh $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHHpre, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHHroW, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHHroX, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHHui, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRHroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRHroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRHui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRQl, ARM64_INS_LDR: ldr $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRQpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRQpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRQroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRQroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRQui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBWpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBWpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBWroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSBWroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSBWui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBXpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBXpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSBXroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSBXroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSBXui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHWpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHWpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHWroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSHWroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSHWui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHXpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHXpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSHXroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSHXroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSHXui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSWl, ARM64_INS_LDRSW: ldrsw $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSWpost, ARM64_INS_LDRSW: ldrsw $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSWpre, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSWroW, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSWroX, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSWui, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSl, ARM64_INS_LDR: ldr $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRSroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRSui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRWl, ARM64_INS_LDR: ldr $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRWpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRWpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRWroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRWroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRWui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRXl, ARM64_INS_LDR: ldr $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRXpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRXpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDRXroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRXroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_LDRXui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LDTRBi, ARM64_INS_LDTRB: ldtrb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRHi, ARM64_INS_LDTRH: ldtrh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRSBWi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRSBXi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRSHWi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRSHXi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRSWi, ARM64_INS_LDTRSW: ldtrsw $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRWi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDTRXi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURBBi, ARM64_INS_LDURB: ldurb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURBi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURDi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURHHi, ARM64_INS_LDURH: ldurh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURHi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURQi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSBWi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSBXi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSHWi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSHXi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSWi, ARM64_INS_LDURSW: ldursw $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURSi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURWi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDURXi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_LDXPW, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDXPX, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDXRB, ARM64_INS_LDXRB: ldxrb $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDXRH, ARM64_INS_LDXRH: ldxrh $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDXRW, ARM64_INS_LDXR: ldxr $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LDXRX, ARM64_INS_LDXR: ldxr $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_LSLVWr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LSLVXr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LSRVWr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_LSRVXr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MADDWrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MADDXrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLAv16i8, ARM64_INS_MLA: mla.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLAv2i32, ARM64_INS_MLA: mla.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLAv2i32_indexed, ARM64_INS_MLA: mla.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLAv4i16, ARM64_INS_MLA: mla.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLAv4i16_indexed, ARM64_INS_MLA: mla.4h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLAv4i32, ARM64_INS_MLA: mla.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLAv4i32_indexed, ARM64_INS_MLA: mla.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLAv8i16, ARM64_INS_MLA: mla.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLAv8i16_indexed, ARM64_INS_MLA: mla.8h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLAv8i8, ARM64_INS_MLA: mla.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv16i8, ARM64_INS_MLS: mls.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv2i32, ARM64_INS_MLS: mls.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv2i32_indexed, ARM64_INS_MLS: mls.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLSv4i16, ARM64_INS_MLS: mls.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv4i16_indexed, ARM64_INS_MLS: mls.4h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLSv4i32, ARM64_INS_MLS: mls.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv4i32_indexed, ARM64_INS_MLS: mls.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLSv8i16, ARM64_INS_MLS: mls.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MLSv8i16_indexed, ARM64_INS_MLS: mls.8h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MLSv8i8, ARM64_INS_MLS: mls.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVID, ARM64_INS_MOVI: movi $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv16b_ns, ARM64_INS_MOVI: movi.16b $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv2d_ns, ARM64_INS_MOVI: movi.2d $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv2i32, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv2s_msl, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv4i16, ARM64_INS_MOVI: movi.4h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv4i32, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv4s_msl, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv8b_ns, ARM64_INS_MOVI: movi.8b $rd, $imm8 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVIv8i16, ARM64_INS_MOVI: movi.8h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVKWi, ARM64_INS_MOVK: movk $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVKXi, ARM64_INS_MOVK: movk $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVNWi, ARM64_INS_MOVN: movn $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVNXi, ARM64_INS_MOVN: movn $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVZWi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MOVZXi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MRS, ARM64_INS_MRS: mrs $rt, $systemreg */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_MSR, ARM64_INS_MSR: msr $systemreg, $rt */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_MSRpstate, ARM64_INS_MSR: msr $pstate_field, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MSUBWrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MSUBXrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MULv16i8, ARM64_INS_MUL: mul.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv2i32, ARM64_INS_MUL: mul.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv2i32_indexed, ARM64_INS_MUL: mul.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MULv4i16, ARM64_INS_MUL: mul.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv4i16_indexed, ARM64_INS_MUL: mul.4h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_MULv4i32, ARM64_INS_MUL: mul.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv4i32_indexed, ARM64_INS_MUL: mul.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv8i16, ARM64_INS_MUL: mul.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv8i16_indexed, ARM64_INS_MUL: mul.8h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MULv8i8, ARM64_INS_MUL: mul.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv2i32, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv2s_msl, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv4i16, ARM64_INS_MVNI: mvni.4h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv4i32, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv4s_msl, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_MVNIv8i16, ARM64_INS_MVNI: mvni.8h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv16i8, ARM64_INS_NEG: neg.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv1i64, ARM64_INS_NEG: neg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv2i32, ARM64_INS_NEG: neg.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv2i64, ARM64_INS_NEG: neg.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv4i16, ARM64_INS_NEG: neg.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv4i32, ARM64_INS_NEG: neg.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv8i16, ARM64_INS_NEG: neg.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NEGv8i8, ARM64_INS_NEG: neg.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NOTv16i8, ARM64_INS_NOT: not.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_NOTv8i8, ARM64_INS_NOT: not.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ORNWrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORNXrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORNv16i8, ARM64_INS_ORN: orn.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORNv8i8, ARM64_INS_ORN: orn.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRWri, ARM64_INS_ORR: orr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRWrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRXri, ARM64_INS_ORR: orr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRXrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv16i8, ARM64_INS_ORR: orr.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv2i32, ARM64_INS_ORR: orr.2s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv4i16, ARM64_INS_ORR: orr.4h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv4i32, ARM64_INS_ORR: orr.4s $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv8i16, ARM64_INS_ORR: orr.8h $rd, $imm8$shift */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ORRv8i8, ARM64_INS_ORR: orr.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_PMULLv16i8, ARM64_INS_PMULL2: pmull2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PMULLv1i64, ARM64_INS_PMULL: pmull.1q $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PMULLv2i64, ARM64_INS_PMULL2: pmull2.1q $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PMULLv8i8, ARM64_INS_PMULL: pmull.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PMULv16i8, ARM64_INS_PMUL: pmul.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PMULv8i8, ARM64_INS_PMUL: pmul.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_PRFMl, ARM64_INS_PRFM: prfm $rt, $label */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_PRFMroW, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_PRFMroX, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_PRFMui, ARM64_INS_PRFM: prfm $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_PRFUMi, ARM64_INS_PRFUM: prfum $rt, [$rn, $offset] */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN: raddhn.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2: raddhn2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN: raddhn.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2: raddhn2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2: raddhn2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN: raddhn.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RBITWr, ARM64_INS_RBIT: rbit $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_RBITXr, ARM64_INS_RBIT: rbit $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_RBITv16i8, ARM64_INS_RBIT: rbit.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_RBITv8i8, ARM64_INS_RBIT: rbit.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_RET, ARM64_INS_RET: ret $rn */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_REV16Wr, ARM64_INS_REV16: rev16 $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV16Xr, ARM64_INS_REV16: rev16 $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV16v16i8, ARM64_INS_REV16: rev16.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV16v8i8, ARM64_INS_REV16: rev16.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV32Xr, ARM64_INS_REV32: rev32 $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV32v16i8, ARM64_INS_REV32: rev32.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV32v4i16, ARM64_INS_REV32: rev32.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV32v8i16, ARM64_INS_REV32: rev32.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV32v8i8, ARM64_INS_REV32: rev32.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v16i8, ARM64_INS_REV64: rev64.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v2i32, ARM64_INS_REV64: rev64.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v4i16, ARM64_INS_REV64: rev64.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v4i32, ARM64_INS_REV64: rev64.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v8i16, ARM64_INS_REV64: rev64.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REV64v8i8, ARM64_INS_REV64: rev64.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REVWr, ARM64_INS_REV: rev $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_REVXr, ARM64_INS_REV: rev $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_RORVWr, ARM64_INS_ROR: ror $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RORVXr, ARM64_INS_ROR: ror $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2: rshrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN: rshrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN: rshrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2: rshrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2: rshrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN: rshrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN: rsubhn.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2: rsubhn2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN: rsubhn.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2: rsubhn2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2: rsubhn2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN: rsubhn.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2: sabal2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL: sabal.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL: sabal.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2: sabal2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2: sabal2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL: sabal.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv16i8, ARM64_INS_SABA: saba.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv2i32, ARM64_INS_SABA: saba.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv4i16, ARM64_INS_SABA: saba.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv4i32, ARM64_INS_SABA: saba.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv8i16, ARM64_INS_SABA: saba.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABAv8i8, ARM64_INS_SABA: saba.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2: sabdl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL: sabdl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL: sabdl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2: sabdl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2: sabdl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL: sabdl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv16i8, ARM64_INS_SABD: sabd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv2i32, ARM64_INS_SABD: sabd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv4i16, ARM64_INS_SABD: sabd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv4i32, ARM64_INS_SABD: sabd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv8i16, ARM64_INS_SABD: sabd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SABDv8i8, ARM64_INS_SABD: sabd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP: sadalp.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP: sadalp.1d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP: sadalp.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP: sadalp.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP: sadalp.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP: sadalp.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP: saddlp.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP: saddlp.1d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP: saddlp.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP: saddlp.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP: saddlp.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP: saddlp.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLVv16i8v, ARM64_INS_SADDLV: saddlv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLVv4i16v, ARM64_INS_SADDLV: saddlv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLVv4i32v, ARM64_INS_SADDLV: saddlv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLVv8i16v, ARM64_INS_SADDLV: saddlv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLVv8i8v, ARM64_INS_SADDLV: saddlv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2: saddl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL: saddl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL: saddl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2: saddl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2: saddl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL: saddl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2: saddw2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW: saddw.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW: saddw.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2: saddw2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2: saddw2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW: saddw.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SBCSWr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SBCSXr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SBCWr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SBCXr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SCVTFSWDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFSWSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFSXDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFSXSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFUWDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFUWSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFUXDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFUXSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFd, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFs, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv1i32, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv1i64, ARM64_INS_SCVTF: scvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv2f32, ARM64_INS_SCVTF: scvtf.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv2f64, ARM64_INS_SCVTF: scvtf.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF: scvtf.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF: scvtf.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv4f32, ARM64_INS_SCVTF: scvtf.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0} +}, +{ /* AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF: scvtf.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SDIVWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SDIVXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SDIV_IntWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SDIV_IntXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHA1Crrr, ARM64_INS_SHA1C: sha1c.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA1Hrr, ARM64_INS_SHA1H: sha1h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA1Mrrr, ARM64_INS_SHA1M: sha1m.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA1Prrr, ARM64_INS_SHA1P: sha1p.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0: sha1su0.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1: sha1su1.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA256H2rrr, ARM64_INS_SHA256H2: sha256h2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA256Hrrr, ARM64_INS_SHA256H: sha256h.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0: sha256su0.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1: sha256su1.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SHADDv16i8, ARM64_INS_SHADD: shadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHADDv2i32, ARM64_INS_SHADD: shadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHADDv4i16, ARM64_INS_SHADD: shadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHADDv4i32, ARM64_INS_SHADD: shadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHADDv8i16, ARM64_INS_SHADD: shadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHADDv8i8, ARM64_INS_SHADD: shadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv16i8, ARM64_INS_SHLL2: shll2.8h $rd, $rn, #8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv2i32, ARM64_INS_SHLL: shll.2d $rd, $rn, #32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv4i16, ARM64_INS_SHLL: shll.4s $rd, $rn, #16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv4i32, ARM64_INS_SHLL2: shll2.2d $rd, $rn, #32 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv8i16, ARM64_INS_SHLL2: shll2.4s $rd, $rn, #16 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLLv8i8, ARM64_INS_SHLL: shll.8h $rd, $rn, #8 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLd, ARM64_INS_SHL: shl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv16i8_shift, ARM64_INS_SHL: shl.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv2i32_shift, ARM64_INS_SHL: shl.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv2i64_shift, ARM64_INS_SHL: shl.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv4i16_shift, ARM64_INS_SHL: shl.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv4i32_shift, ARM64_INS_SHL: shl.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv8i16_shift, ARM64_INS_SHL: shl.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHLv8i8_shift, ARM64_INS_SHL: shl.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2: shrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv2i32_shift, ARM64_INS_SHRN: shrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv4i16_shift, ARM64_INS_SHRN: shrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2: shrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2: shrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHRNv8i8_shift, ARM64_INS_SHRN: shrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv16i8, ARM64_INS_SHSUB: shsub.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv2i32, ARM64_INS_SHSUB: shsub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv4i16, ARM64_INS_SHSUB: shsub.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv4i32, ARM64_INS_SHSUB: shsub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv8i16, ARM64_INS_SHSUB: shsub.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SHSUBv8i8, ARM64_INS_SHSUB: shsub.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLId, ARM64_INS_SLI: sli $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv16i8_shift, ARM64_INS_SLI: sli.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv2i32_shift, ARM64_INS_SLI: sli.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv2i64_shift, ARM64_INS_SLI: sli.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv4i16_shift, ARM64_INS_SLI: sli.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv4i32_shift, ARM64_INS_SLI: sli.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv8i16_shift, ARM64_INS_SLI: sli.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SLIv8i8_shift, ARM64_INS_SLI: sli.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} +}, +{ /* AArch64_SMADDLrrr, ARM64_INS_SMADDL: smaddl $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv16i8, ARM64_INS_SMAXP: smaxp.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv2i32, ARM64_INS_SMAXP: smaxp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv4i16, ARM64_INS_SMAXP: smaxp.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv4i32, ARM64_INS_SMAXP: smaxp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv8i16, ARM64_INS_SMAXP: smaxp.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXPv8i8, ARM64_INS_SMAXP: smaxp.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv16i8, ARM64_INS_SMAX: smax.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv2i32, ARM64_INS_SMAX: smax.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv4i16, ARM64_INS_SMAX: smax.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv4i32, ARM64_INS_SMAX: smax.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv8i16, ARM64_INS_SMAX: smax.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMAXv8i8, ARM64_INS_SMAX: smax.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMC, ARM64_INS_SMC: smc $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv16i8, ARM64_INS_SMINP: sminp.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv2i32, ARM64_INS_SMINP: sminp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv4i16, ARM64_INS_SMINP: sminp.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv4i32, ARM64_INS_SMINP: sminp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv8i16, ARM64_INS_SMINP: sminp.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINPv8i8, ARM64_INS_SMINP: sminp.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINVv16i8v, ARM64_INS_SMINV: sminv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINVv4i16v, ARM64_INS_SMINV: sminv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINVv4i32v, ARM64_INS_SMINV: sminv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINVv8i16v, ARM64_INS_SMINV: sminv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINVv8i8v, ARM64_INS_SMINV: sminv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv16i8, ARM64_INS_SMIN: smin.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv2i32, ARM64_INS_SMIN: smin.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv4i16, ARM64_INS_SMIN: smin.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv4i32, ARM64_INS_SMIN: smin.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv8i16, ARM64_INS_SMIN: smin.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMINv8i8, ARM64_INS_SMIN: smin.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2: smlal2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL: smlal.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2: smlsl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL: smlsl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMOVvi16to32, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMOVvi16to64, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMOVvi32to64, ARM64_INS_SMOV: smov.s $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMOVvi8to32, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMOVvi8to64, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMSUBLrrr, ARM64_INS_SMSUBL: smsubl $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULHrr, ARM64_INS_SMULH: smulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2: smull2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL: smull.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv16i8, ARM64_INS_SQABS: sqabs.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv1i16, ARM64_INS_SQABS: sqabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv1i32, ARM64_INS_SQABS: sqabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv1i64, ARM64_INS_SQABS: sqabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv1i8, ARM64_INS_SQABS: sqabs $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv2i32, ARM64_INS_SQABS: sqabs.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv2i64, ARM64_INS_SQABS: sqabs.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv4i16, ARM64_INS_SQABS: sqabs.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv4i32, ARM64_INS_SQABS: sqabs.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv8i16, ARM64_INS_SQABS: sqabs.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQABSv8i8, ARM64_INS_SQABS: sqabs.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv16i8, ARM64_INS_SQADD: sqadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv1i16, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv1i32, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv1i64, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv1i8, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv2i32, ARM64_INS_SQADD: sqadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv2i64, ARM64_INS_SQADD: sqadd.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv4i16, ARM64_INS_SQADD: sqadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv4i32, ARM64_INS_SQADD: sqadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv8i16, ARM64_INS_SQADD: sqadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQADDv8i8, ARM64_INS_SQADD: sqadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALi16, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALi32, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL: sqdmlal.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL: sqdmlsl.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH: sqdmulh.h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH: sqdmulh.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLi16, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLi32, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL: sqdmull.h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL: sqdmull.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv16i8, ARM64_INS_SQNEG: sqneg.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv1i16, ARM64_INS_SQNEG: sqneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv1i32, ARM64_INS_SQNEG: sqneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv1i64, ARM64_INS_SQNEG: sqneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv1i8, ARM64_INS_SQNEG: sqneg $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv2i32, ARM64_INS_SQNEG: sqneg.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv2i64, ARM64_INS_SQNEG: sqneg.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv4i16, ARM64_INS_SQNEG: sqneg.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv4i32, ARM64_INS_SQNEG: sqneg.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv8i16, ARM64_INS_SQNEG: sqneg.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQNEGv8i8, ARM64_INS_SQNEG: sqneg.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL: sqrshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL: sqrshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL: sqrshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL: sqrshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL: sqrshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL: sqrshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL: sqrshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNb, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNh, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNs, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2: sqrshrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN: sqrshrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN: sqrshrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2: sqrshrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2: sqrshrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN: sqrshrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN: sqrshrun.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN: sqrshrun.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN: sqrshrun.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUb, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUd, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUh, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUs, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU: sqshlu.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU: sqshlu.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU: sqshlu.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU: sqshlu.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU: sqshlu.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU: sqshlu.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU: sqshlu.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLb, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLd, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLh, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLs, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv16i8, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv1i16, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv1i32, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv1i64, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv1i8, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv2i32, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv2i64, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv4i16, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv4i32, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv8i16, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv8i8, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNb, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNh, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNs, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2: sqshrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN: sqshrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN: sqshrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2: sqshrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2: sqshrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN: sqshrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNb, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNh, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNs, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2: sqshrun2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN: sqshrun.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN: sqshrun.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2: sqshrun2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2: sqshrun2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN: sqshrun.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv16i8, ARM64_INS_SQSUB: sqsub.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv1i16, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv1i32, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv1i64, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv1i8, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv2i32, ARM64_INS_SQSUB: sqsub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv2i64, ARM64_INS_SQSUB: sqsub.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv4i16, ARM64_INS_SQSUB: sqsub.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv4i32, ARM64_INS_SQSUB: sqsub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv8i16, ARM64_INS_SQSUB: sqsub.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQSUBv8i8, ARM64_INS_SQSUB: sqsub.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv16i8, ARM64_INS_SQXTN2: sqxtn2.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv1i16, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv1i32, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv1i8, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv2i32, ARM64_INS_SQXTN: sqxtn.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv4i16, ARM64_INS_SQXTN: sqxtn.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv4i32, ARM64_INS_SQXTN2: sqxtn2.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv8i16, ARM64_INS_SQXTN2: sqxtn2.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTNv8i8, ARM64_INS_SQXTN: sqxtn.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2: sqxtun2.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN: sqxtun.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN: sqxtun.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2: sqxtun2.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2: sqxtun2.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN: sqxtun.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv16i8, ARM64_INS_SRHADD: srhadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv2i32, ARM64_INS_SRHADD: srhadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv4i16, ARM64_INS_SRHADD: srhadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv4i32, ARM64_INS_SRHADD: srhadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv8i16, ARM64_INS_SRHADD: srhadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRHADDv8i8, ARM64_INS_SRHADD: srhadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRId, ARM64_INS_SRI: sri $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv16i8_shift, ARM64_INS_SRI: sri.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv2i32_shift, ARM64_INS_SRI: sri.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv2i64_shift, ARM64_INS_SRI: sri.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv4i16_shift, ARM64_INS_SRI: sri.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv4i32_shift, ARM64_INS_SRI: sri.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv8i16_shift, ARM64_INS_SRI: sri.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRIv8i8_shift, ARM64_INS_SRI: sri.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv16i8, ARM64_INS_SRSHL: srshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv1i64, ARM64_INS_SRSHL: srshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv2i32, ARM64_INS_SRSHL: srshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv2i64, ARM64_INS_SRSHL: srshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv4i16, ARM64_INS_SRSHL: srshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv4i32, ARM64_INS_SRSHL: srshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv8i16, ARM64_INS_SRSHL: srshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHLv8i8, ARM64_INS_SRSHL: srshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRd, ARM64_INS_SRSHR: srshr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR: srshr.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR: srshr.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR: srshr.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR: srshr.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR: srshr.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR: srshr.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR: srshr.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAd, ARM64_INS_SRSRA: srsra $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA: srsra.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA: srsra.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA: srsra.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA: srsra.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA: srsra.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA: srsra.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA: srsra.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2: sshll2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL: sshll.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL: sshll.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2: sshll2.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2: sshll2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL: sshll.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv16i8, ARM64_INS_SSHL: sshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv1i64, ARM64_INS_SSHL: sshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv2i32, ARM64_INS_SSHL: sshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv2i64, ARM64_INS_SSHL: sshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv4i16, ARM64_INS_SSHL: sshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv4i32, ARM64_INS_SSHL: sshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv8i16, ARM64_INS_SSHL: sshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHLv8i8, ARM64_INS_SSHL: sshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRd, ARM64_INS_SSHR: sshr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv16i8_shift, ARM64_INS_SSHR: sshr.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv2i32_shift, ARM64_INS_SSHR: sshr.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv2i64_shift, ARM64_INS_SSHR: sshr.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv4i16_shift, ARM64_INS_SSHR: sshr.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv4i32_shift, ARM64_INS_SSHR: sshr.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv8i16_shift, ARM64_INS_SSHR: sshr.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSHRv8i8_shift, ARM64_INS_SSHR: sshr.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAd, ARM64_INS_SSRA: ssra $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv16i8_shift, ARM64_INS_SSRA: ssra.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv2i32_shift, ARM64_INS_SSRA: ssra.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv2i64_shift, ARM64_INS_SSRA: ssra.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv4i16_shift, ARM64_INS_SSRA: ssra.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv4i32_shift, ARM64_INS_SSRA: ssra.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv8i16_shift, ARM64_INS_SSRA: ssra.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSRAv8i8_shift, ARM64_INS_SSRA: ssra.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2: ssubl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL: ssubl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL: ssubl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2: ssubl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2: ssubl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL: ssubl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2: ssubw2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW: ssubw.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW: ssubw.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2: ssubw2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2: ssubw2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW: ssubw.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Fourv8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Onev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Threev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1Twov8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i16, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i16_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i32, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i32_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i64, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i64_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i8, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST1i8_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov16b, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov16b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov2d, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov2d_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov2s, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov2s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov4h, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov4h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov4s, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov4s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov8b, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov8b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov8h, ARM64_INS_ST2: st2 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2Twov8h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i16, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i16_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i32, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i32_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i64, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i64_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i8, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST2i8_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev16b, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev16b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev2d, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev2d_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev2s, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev2s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev4h, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev4h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev4s, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev4s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev8b, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev8b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev8h, ARM64_INS_ST3: st3 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3Threev8h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i16, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i16_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i32, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i32_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i64, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i64_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i8, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST3i8_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv16b, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv16b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv2d, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv2d_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv2s, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv2s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv4h, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv4h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv4s, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv4s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv8b, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv8b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv8h, ARM64_INS_ST4: st4 $vt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4Fourv8h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i16, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i16_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i32, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i32_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i64, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i64_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i8, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } +}, +{ /* AArch64_ST4i8_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLRB, ARM64_INS_STLRB: stlrb $rt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLRH, ARM64_INS_STLRH: stlrh $rt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLRW, ARM64_INS_STLR: stlr $rt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLRX, ARM64_INS_STLR: stlr $rt, [$rn] */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXPW, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXPX, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXRB, ARM64_INS_STLXRB: stlxrb $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXRH, ARM64_INS_STLXRH: stlxrh $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXRW, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STLXRX, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STNPDi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STNPQi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STNPSi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STNPWi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STNPXi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPDi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPDpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPDpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPQi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPQpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPQpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPSi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPSpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPSpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPWi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPWpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPWpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPXi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPXpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STPXpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRBBpost, ARM64_INS_STRB: strb $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRBBpre, ARM64_INS_STRB: strb $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRBBroW, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRBBroX, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRBBui, ARM64_INS_STRB: strb $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRBpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRBpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRBroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRBroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRBui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRDpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRDpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRDroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRDroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRDui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHHpost, ARM64_INS_STRH: strh $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHHpre, ARM64_INS_STRH: strh $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHHroW, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRHHroX, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRHHui, ARM64_INS_STRH: strh $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRHroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRHroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRHui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRQpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRQpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRQroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRQroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRQui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRSpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRSpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRSroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRSroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRSui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRWpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRWpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRWroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRWroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRWui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRXpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRXpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STRXroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRXroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STRXui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STTRBi, ARM64_INS_STTRB: sttrb $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STTRHi, ARM64_INS_STTRH: sttrh $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STTRWi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STTRXi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURBBi, ARM64_INS_STURB: sturb $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURBi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURDi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURHHi, ARM64_INS_STURH: sturh $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURHi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURQi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURSi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURWi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STURXi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + 0, + { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STXPW, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STXPX, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_STXRB, ARM64_INS_STXRB: stxrb $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STXRH, ARM64_INS_STXRH: stxrh $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STXRW, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_STXRX, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN: subhn.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2: subhn2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN: subhn.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2: subhn2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2: subhn2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN: subhn.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSWri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSWrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSWrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSXri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSXrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSXrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBSXrx64, ARM64_INS_SUBS: subs $rd, $rn, $rm$ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SUBWri, ARM64_INS_SUB: sub $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBWrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBWrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBXri, ARM64_INS_SUB: sub $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBXrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBXrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBXrx64, ARM64_INS_SUB: sub $rd, $rn, $rm$ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SUBv16i8, ARM64_INS_SUB: sub.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv1i64, ARM64_INS_SUB: sub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv2i32, ARM64_INS_SUB: sub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv2i64, ARM64_INS_SUB: sub.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv4i16, ARM64_INS_SUB: sub.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv4i32, ARM64_INS_SUB: sub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv8i16, ARM64_INS_SUB: sub.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUBv8i8, ARM64_INS_SUB: sub.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv16i8, ARM64_INS_SUQADD: suqadd.16b $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv1i16, ARM64_INS_SUQADD: suqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv1i32, ARM64_INS_SUQADD: suqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv1i64, ARM64_INS_SUQADD: suqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv1i8, ARM64_INS_SUQADD: suqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv2i32, ARM64_INS_SUQADD: suqadd.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv2i64, ARM64_INS_SUQADD: suqadd.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv4i16, ARM64_INS_SUQADD: suqadd.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv4i32, ARM64_INS_SUQADD: suqadd.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv8i16, ARM64_INS_SUQADD: suqadd.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SUQADDv8i8, ARM64_INS_SUQADD: suqadd.8b $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_SVC, ARM64_INS_SVC: svc $imm */ + 0, + { CS_AC_READ, 0 } +}, +{ /* AArch64_SYSLxt, ARM64_INS_SYSL: sysl $rt, $op1, $cn, $cm, $op2 */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, +{ /* AArch64_SYSxt, ARM64_INS_SYS: sys $op1, $cn, $cm, $op2, $rt */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ } +}, +{ /* AArch64_TBLv16i8Four, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv16i8One, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv16i8Three, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv16i8Two, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv8i8Four, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv8i8One, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv8i8Three, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBLv8i8Two, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBNZW, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBNZX, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv16i8Four, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv16i8One, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv16i8Three, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv16i8Two, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv8i8Four, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv8i8One, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv8i8Three, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBXv8i8Two, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBZW, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TBZX, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v16i8, ARM64_INS_TRN1: trn1.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v2i32, ARM64_INS_TRN1: trn1.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v2i64, ARM64_INS_TRN1: trn1.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v4i16, ARM64_INS_TRN1: trn1.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v4i32, ARM64_INS_TRN1: trn1.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v8i16, ARM64_INS_TRN1: trn1.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN1v8i8, ARM64_INS_TRN1: trn1.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v16i8, ARM64_INS_TRN2: trn2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v2i32, ARM64_INS_TRN2: trn2.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v2i64, ARM64_INS_TRN2: trn2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v4i16, ARM64_INS_TRN2: trn2.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v4i32, ARM64_INS_TRN2: trn2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v8i16, ARM64_INS_TRN2: trn2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_TRN2v8i8, ARM64_INS_TRN2: trn2.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2: uabal2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL: uabal.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL: uabal.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2: uabal2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2: uabal2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL: uabal.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv16i8, ARM64_INS_UABA: uaba.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv2i32, ARM64_INS_UABA: uaba.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv4i16, ARM64_INS_UABA: uaba.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv4i32, ARM64_INS_UABA: uaba.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv8i16, ARM64_INS_UABA: uaba.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABAv8i8, ARM64_INS_UABA: uaba.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2: uabdl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL: uabdl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL: uabdl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2: uabdl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2: uabdl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL: uabdl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv16i8, ARM64_INS_UABD: uabd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv2i32, ARM64_INS_UABD: uabd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv4i16, ARM64_INS_UABD: uabd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv4i32, ARM64_INS_UABD: uabd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv8i16, ARM64_INS_UABD: uabd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UABDv8i8, ARM64_INS_UABD: uabd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP: uadalp.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP: uadalp.1d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP: uadalp.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP: uadalp.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP: uadalp.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP: uadalp.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP: uaddlp.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP: uaddlp.1d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP: uaddlp.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP: uaddlp.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP: uaddlp.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP: uaddlp.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLVv16i8v, ARM64_INS_UADDLV: uaddlv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLVv4i16v, ARM64_INS_UADDLV: uaddlv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLVv4i32v, ARM64_INS_UADDLV: uaddlv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLVv8i16v, ARM64_INS_UADDLV: uaddlv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLVv8i8v, ARM64_INS_UADDLV: uaddlv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2: uaddl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL: uaddl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL: uaddl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2: uaddl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2: uaddl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL: uaddl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2: uaddw2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW: uaddw.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW: uaddw.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2: uaddw2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2: uaddw2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW: uaddw.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UBFMWri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UBFMXri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFSWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFSWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFSXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFSXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFUWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFUWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFUXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFUXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFd, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFs, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv1i32, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv1i64, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv2f32, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv2f64, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv4f32, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UDIVWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UDIVXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UDIV_IntWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UDIV_IntXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv16i8, ARM64_INS_UHADD: uhadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv2i32, ARM64_INS_UHADD: uhadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv4i16, ARM64_INS_UHADD: uhadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv4i32, ARM64_INS_UHADD: uhadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv8i16, ARM64_INS_UHADD: uhadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHADDv8i8, ARM64_INS_UHADD: uhadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv16i8, ARM64_INS_UHSUB: uhsub.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv2i32, ARM64_INS_UHSUB: uhsub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv4i16, ARM64_INS_UHSUB: uhsub.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv4i32, ARM64_INS_UHSUB: uhsub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv8i16, ARM64_INS_UHSUB: uhsub.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UHSUBv8i8, ARM64_INS_UHSUB: uhsub.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMADDLrrr, ARM64_INS_UMADDL: umaddl $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv16i8, ARM64_INS_UMAXP: umaxp.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv2i32, ARM64_INS_UMAXP: umaxp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv4i16, ARM64_INS_UMAXP: umaxp.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv4i32, ARM64_INS_UMAXP: umaxp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv8i16, ARM64_INS_UMAXP: umaxp.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXPv8i8, ARM64_INS_UMAXP: umaxp.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXVv16i8v, ARM64_INS_UMAXV: umaxv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXVv4i16v, ARM64_INS_UMAXV: umaxv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXVv4i32v, ARM64_INS_UMAXV: umaxv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXVv8i16v, ARM64_INS_UMAXV: umaxv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXVv8i8v, ARM64_INS_UMAXV: umaxv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv16i8, ARM64_INS_UMAX: umax.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv2i32, ARM64_INS_UMAX: umax.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv4i16, ARM64_INS_UMAX: umax.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv4i32, ARM64_INS_UMAX: umax.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv8i16, ARM64_INS_UMAX: umax.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMAXv8i8, ARM64_INS_UMAX: umax.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv16i8, ARM64_INS_UMINP: uminp.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv2i32, ARM64_INS_UMINP: uminp.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv4i16, ARM64_INS_UMINP: uminp.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv4i32, ARM64_INS_UMINP: uminp.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv8i16, ARM64_INS_UMINP: uminp.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINPv8i8, ARM64_INS_UMINP: uminp.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINVv16i8v, ARM64_INS_UMINV: uminv.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINVv4i16v, ARM64_INS_UMINV: uminv.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINVv4i32v, ARM64_INS_UMINV: uminv.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINVv8i16v, ARM64_INS_UMINV: uminv.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINVv8i8v, ARM64_INS_UMINV: uminv.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv16i8, ARM64_INS_UMIN: umin.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv2i32, ARM64_INS_UMIN: umin.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv4i16, ARM64_INS_UMIN: umin.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv4i32, ARM64_INS_UMIN: umin.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv8i16, ARM64_INS_UMIN: umin.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMINv8i8, ARM64_INS_UMIN: umin.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2: umlal2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL: umlal.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2: umlsl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL: umlsl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMOVvi16, ARM64_INS_UMOV: umov.h $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMOVvi32, ARM64_INS_UMOV: umov.s $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMOVvi64, ARM64_INS_UMOV: umov.d $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMOVvi8, ARM64_INS_UMOV: umov.b $rd, $rn$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMSUBLrrr, ARM64_INS_UMSUBL: umsubl $rd, $rn, $rm, $ra */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULHrr, ARM64_INS_UMULH: umulh $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2: umull2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm$idx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL: umull.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv16i8, ARM64_INS_UQADD: uqadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv1i16, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv1i32, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv1i64, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv1i8, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv2i32, ARM64_INS_UQADD: uqadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv2i64, ARM64_INS_UQADD: uqadd.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv4i16, ARM64_INS_UQADD: uqadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv4i32, ARM64_INS_UQADD: uqadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv8i16, ARM64_INS_UQADD: uqadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQADDv8i8, ARM64_INS_UQADD: uqadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL: uqrshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL: uqrshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL: uqrshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL: uqrshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL: uqrshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL: uqrshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL: uqrshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNb, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNh, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNs, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2: uqrshrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN: uqrshrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN: uqrshrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2: uqrshrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2: uqrshrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN: uqrshrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLb, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLd, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLh, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLs, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv16i8, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv1i16, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv1i32, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv1i64, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv1i8, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv2i32, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv2i64, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv4i16, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv4i32, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv8i16, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv8i8, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNb, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNh, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNs, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2: uqshrn2.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN: uqshrn.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN: uqshrn.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2: uqshrn2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2: uqshrn2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN: uqshrn.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv16i8, ARM64_INS_UQSUB: uqsub.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv1i16, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv1i32, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv1i64, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv1i8, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv2i32, ARM64_INS_UQSUB: uqsub.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv2i64, ARM64_INS_UQSUB: uqsub.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv4i16, ARM64_INS_UQSUB: uqsub.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv4i32, ARM64_INS_UQSUB: uqsub.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv8i16, ARM64_INS_UQSUB: uqsub.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQSUBv8i8, ARM64_INS_UQSUB: uqsub.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv16i8, ARM64_INS_UQXTN2: uqxtn2.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv1i16, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv1i32, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv1i8, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv2i32, ARM64_INS_UQXTN: uqxtn.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv4i16, ARM64_INS_UQXTN: uqxtn.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv4i32, ARM64_INS_UQXTN2: uqxtn2.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv8i16, ARM64_INS_UQXTN2: uqxtn2.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_UQXTNv8i8, ARM64_INS_UQXTN: uqxtn.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_URECPEv2i32, ARM64_INS_URECPE: urecpe.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_URECPEv4i32, ARM64_INS_URECPE: urecpe.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv16i8, ARM64_INS_URHADD: urhadd.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv2i32, ARM64_INS_URHADD: urhadd.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv4i16, ARM64_INS_URHADD: urhadd.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv4i32, ARM64_INS_URHADD: urhadd.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv8i16, ARM64_INS_URHADD: urhadd.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URHADDv8i8, ARM64_INS_URHADD: urhadd.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv16i8, ARM64_INS_URSHL: urshl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv1i64, ARM64_INS_URSHL: urshl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv2i32, ARM64_INS_URSHL: urshl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv2i64, ARM64_INS_URSHL: urshl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv4i16, ARM64_INS_URSHL: urshl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv4i32, ARM64_INS_URSHL: urshl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv8i16, ARM64_INS_URSHL: urshl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHLv8i8, ARM64_INS_URSHL: urshl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRd, ARM64_INS_URSHR: urshr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv16i8_shift, ARM64_INS_URSHR: urshr.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv2i32_shift, ARM64_INS_URSHR: urshr.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv2i64_shift, ARM64_INS_URSHR: urshr.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv4i16_shift, ARM64_INS_URSHR: urshr.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv4i32_shift, ARM64_INS_URSHR: urshr.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv8i16_shift, ARM64_INS_URSHR: urshr.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSHRv8i8_shift, ARM64_INS_URSHR: urshr.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE: ursqrte.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE: ursqrte.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAd, ARM64_INS_URSRA: ursra $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv16i8_shift, ARM64_INS_URSRA: ursra.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv2i32_shift, ARM64_INS_URSRA: ursra.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv2i64_shift, ARM64_INS_URSRA: ursra.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv4i16_shift, ARM64_INS_URSRA: ursra.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv4i32_shift, ARM64_INS_URSRA: ursra.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv8i16_shift, ARM64_INS_URSRA: ursra.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_URSRAv8i8_shift, ARM64_INS_URSRA: ursra.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2: ushll2.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv2i32_shift, ARM64_INS_USHLL: ushll.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv4i16_shift, ARM64_INS_USHLL: ushll.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2: ushll2.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2: ushll2.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLLv8i8_shift, ARM64_INS_USHLL: ushll.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv16i8, ARM64_INS_USHL: ushl.16b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv1i64, ARM64_INS_USHL: ushl $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv2i32, ARM64_INS_USHL: ushl.2s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv2i64, ARM64_INS_USHL: ushl.2d $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv4i16, ARM64_INS_USHL: ushl.4h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv4i32, ARM64_INS_USHL: ushl.4s $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv8i16, ARM64_INS_USHL: ushl.8h $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHLv8i8, ARM64_INS_USHL: ushl.8b $rd, $rn, $rm| */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRd, ARM64_INS_USHR: ushr $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv16i8_shift, ARM64_INS_USHR: ushr.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv2i32_shift, ARM64_INS_USHR: ushr.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv2i64_shift, ARM64_INS_USHR: ushr.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv4i16_shift, ARM64_INS_USHR: ushr.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv4i32_shift, ARM64_INS_USHR: ushr.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv8i16_shift, ARM64_INS_USHR: ushr.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USHRv8i8_shift, ARM64_INS_USHR: ushr.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv16i8, ARM64_INS_USQADD: usqadd.16b $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv1i16, ARM64_INS_USQADD: usqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv1i32, ARM64_INS_USQADD: usqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv1i64, ARM64_INS_USQADD: usqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv1i8, ARM64_INS_USQADD: usqadd $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv2i32, ARM64_INS_USQADD: usqadd.2s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv2i64, ARM64_INS_USQADD: usqadd.2d $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv4i16, ARM64_INS_USQADD: usqadd.4h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv4i32, ARM64_INS_USQADD: usqadd.4s $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv8i16, ARM64_INS_USQADD: usqadd.8h $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USQADDv8i8, ARM64_INS_USQADD: usqadd.8b $rd, $rn */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAd, ARM64_INS_USRA: usra $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv16i8_shift, ARM64_INS_USRA: usra.16b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv2i32_shift, ARM64_INS_USRA: usra.2s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv2i64_shift, ARM64_INS_USRA: usra.2d $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv4i16_shift, ARM64_INS_USRA: usra.4h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv4i32_shift, ARM64_INS_USRA: usra.4s $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv8i16_shift, ARM64_INS_USRA: usra.8h $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USRAv8i8_shift, ARM64_INS_USRA: usra.8b $rd, $rn, $imm */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2: usubl2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL: usubl.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL: usubl.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2: usubl2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2: usubl2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL: usubl.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2: usubw2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW: usubw.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW: usubw.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2: usubw2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2: usubw2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW: usubw.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v16i8, ARM64_INS_UZP1: uzp1.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v2i32, ARM64_INS_UZP1: uzp1.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v2i64, ARM64_INS_UZP1: uzp1.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v4i16, ARM64_INS_UZP1: uzp1.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v4i32, ARM64_INS_UZP1: uzp1.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v8i16, ARM64_INS_UZP1: uzp1.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP1v8i8, ARM64_INS_UZP1: uzp1.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v16i8, ARM64_INS_UZP2: uzp2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v2i32, ARM64_INS_UZP2: uzp2.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v2i64, ARM64_INS_UZP2: uzp2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v4i16, ARM64_INS_UZP2: uzp2.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v4i32, ARM64_INS_UZP2: uzp2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v8i16, ARM64_INS_UZP2: uzp2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_UZP2v8i8, ARM64_INS_UZP2: uzp2.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv16i8, ARM64_INS_XTN2: xtn2.16b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv2i32, ARM64_INS_XTN: xtn.2s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv4i16, ARM64_INS_XTN: xtn.4h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv4i32, ARM64_INS_XTN2: xtn2.4s $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv8i16, ARM64_INS_XTN2: xtn2.8h $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_XTNv8i8, ARM64_INS_XTN: xtn.8b $rd, $rn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v16i8, ARM64_INS_ZIP1: zip1.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v2i32, ARM64_INS_ZIP1: zip1.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v2i64, ARM64_INS_ZIP1: zip1.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v4i16, ARM64_INS_ZIP1: zip1.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v4i32, ARM64_INS_ZIP1: zip1.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v8i16, ARM64_INS_ZIP1: zip1.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP1v8i8, ARM64_INS_ZIP1: zip1.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v16i8, ARM64_INS_ZIP2: zip2.16b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v2i32, ARM64_INS_ZIP2: zip2.2s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v2i64, ARM64_INS_ZIP2: zip2.2d $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v4i16, ARM64_INS_ZIP2: zip2.4h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v4i32, ARM64_INS_ZIP2: zip2.4s $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v8i16, ARM64_INS_ZIP2: zip2.8h $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* AArch64_ZIP2v8i8, ARM64_INS_ZIP2: zip2.8b $rd, $rn, $rm */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +} diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.c b/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.c new file mode 100644 index 0000000..7fc5ddf --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.c @@ -0,0 +1,44 @@ +/* Capstone Disassembly Engine */ +/* By Dang Hoang Vu 2013 */ + +#ifdef CAPSTONE_HAS_ARM64 + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "AArch64Disassembler.h" +#include "AArch64InstPrinter.h" +#include "AArch64Mapping.h" +#include "AArch64Module.h" + +cs_err AArch64_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + AArch64_init(mri); + ud->printer = AArch64_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = AArch64_getInstruction; + ud->reg_name = AArch64_reg_name; + ud->insn_id = AArch64_get_insn_id; + ud->insn_name = AArch64_insn_name; + ud->group_name = AArch64_group_name; + ud->post_printer = AArch64_post_printer; +#ifndef CAPSTONE_DIET + ud->reg_access = AArch64_reg_access; +#endif + + return CS_ERR_OK; +} + +cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.h b/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.h new file mode 100644 index 0000000..73a132d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/AArch64Module.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_AARCH64_MODULE_H +#define CS_AARCH64_MODULE_H + +#include "../../utils.h" + +cs_err AArch64_global_init(cs_struct *ud); +cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/AArch64/ARMMappingInsnOp.inc b/white_patch_detect/capstone-master/arch/AArch64/ARMMappingInsnOp.inc new file mode 100644 index 0000000..dee436f --- /dev/null +++ b/white_patch_detect/capstone-master/arch/AArch64/ARMMappingInsnOp.inc @@ -0,0 +1,6657 @@ +// This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ADCrr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ADCrsi, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ADCrsr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ADDri, ARM_INS_ADD: add${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ADDrsi, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ADDrsr, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ADR, ARM_INS_ADR: adr${p} $rd, $label */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_AESD, ARM_INS_AESD: aesd.8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_AESE, ARM_INS_AESE: aese.8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_AESMC, ARM_INS_AESMC: aesmc.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ANDrr, ARM_INS_AND: and${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ANDrsi, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ANDrsr, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_BICrr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_BICrsi, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_BICrsr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_BKPT, ARM_INS_BKPT: bkpt $val */ + { 0 } +}, +{ /* ARM_BL, ARM_INS_BL: bl $func */ + { 0 } +}, +{ /* ARM_BLX, ARM_INS_BLX: blx $func */ + { CS_AC_READ, 0 } +}, +{ /* ARM_BLX_pred, ARM_INS_BLX: blx${p} $func */ + { CS_AC_READ, 0 } +}, +{ /* ARM_BLXi, ARM_INS_BLX: blx $target */ + { 0 } +}, +{ /* ARM_BL_pred, ARM_INS_BL: bl${p} $func */ + { 0 } +}, +{ /* ARM_BX, ARM_INS_BX: bx $dst */ + { CS_AC_READ, 0 } +}, +{ /* ARM_BXJ, ARM_INS_BXJ: bxj${p} $func */ + { CS_AC_READ, 0 } +}, +{ /* ARM_BX_RET, ARM_INS_BX: bx${p} lr */ + { 0 } +}, +{ /* ARM_BX_pred, ARM_INS_BX: bx${p} $dst */ + { CS_AC_READ, 0 } +}, +{ /* ARM_Bcc, ARM_INS_B: b${p} $target */ + { 0 } +}, +{ /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ + { 0 } +}, +{ /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_CMNri, ARM_INS_CMN: cmn${p} $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_CMNzrr, ARM_INS_CMN: cmn${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CMNzrsi, ARM_INS_CMN: cmn${p} $rn, $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_CMNzrsr, ARM_INS_CMN: cmn${p} $rn, $shift */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CMPri, ARM_INS_CMP: cmp${p} $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_CMPrr, ARM_INS_CMP: cmp${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CMPrsi, ARM_INS_CMP: cmp${p} $rn, $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_CMPrsr, ARM_INS_CMP: cmp${p} $rn, $shift */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CPS1p, ARM_INS_CPS: cps $mode */ + { 0 } +}, +{ /* ARM_CPS2p, ARM_INS_CPS: cps$imod $iflags */ + { 0 } +}, +{ /* ARM_CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ + { 0 } +}, +{ /* ARM_CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_DBG, ARM_INS_DBG: dbg${p} $opt */ + { 0 } +}, +{ /* ARM_DMB, ARM_INS_DMB: dmb $opt */ + { 0 } +}, +{ /* ARM_DSB, ARM_INS_DSB: dsb $opt */ + { 0 } +}, +{ /* ARM_EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_EORrr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_EORrsi, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_EORrsr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ERET, ARM_INS_ERET: eret${p} */ + { 0 } +}, +{ /* ARM_FCONSTD, ARM_INS_VMOV: vmov${p}.f64 $dd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_FCONSTS, ARM_INS_VMOV: vmov${p}.f32 $sd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_FMSTAT, ARM_INS_VMRS: vmrs${p} apsr_nzcv, fpscr */ + { 0 } +}, +{ /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_HINT, ARM_INS_HINT: hint${p} $imm */ + { 0 } +}, +{ /* ARM_HLT, ARM_INS_HLT: hlt $val */ + { 0 } +}, +{ /* ARM_HVC, ARM_INS_HVC: hvc $imm */ + { 0 } +}, +{ /* ARM_ISB, ARM_INS_ISB: isb $opt */ + { 0 } +}, +{ /* ARM_LDA, ARM_INS_LDA: lda${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRBi12, ARM_INS_LDRB: ldrb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRBrs, ARM_INS_LDRB: ldrb${p} $rt, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRD, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr, $offset */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRH, ARM_INS_LDRH: ldrh${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRi12, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_LDRrs, ARM_INS_LDR: ldr${p} $rt, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MLA, ARM_INS_MLA: mla${s}${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MOVPCLR, ARM_INS_MOV: mov${p} pc, lr */ + { 0 } +}, +{ /* ARM_MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_MOVi, ARM_INS_MOV: mov${s}${p} $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MOVr, ARM_INS_MOV: mov${s}${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_MOVr_TC, ARM_INS_MOV: mov${s}${p} $rd, $rm */ + { 0 } +}, +{ /* ARM_MOVsi, ARM_INS_MOV: mov${s}${p} $rd, $src */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MOVsr, ARM_INS_MOV: mov${s}${p} $rd, $src */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MRS, ARM_INS_MRS: mrs${p} $rd, apsr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MRSsys, ARM_INS_MRS: mrs${p} $rd, spsr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MSR, ARM_INS_MSR: msr${p} $mask, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_MSRi, ARM_INS_MSR: msr${p} $mask, $imm */ + { 0 } +}, +{ /* ARM_MUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MVNr, ARM_INS_MVN: mvn${s}${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_MVNsi, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_MVNsr, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ORRrr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_ORRrsi, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_ORRrsr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_PLDWi12, ARM_INS_PLDW: pldw $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_PLDWrs, ARM_INS_PLDW: pldw $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_PLDi12, ARM_INS_PLD: pld $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_PLDrs, ARM_INS_PLD: pld $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_PLIi12, ARM_INS_PLI: pli $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_PLIrs, ARM_INS_PLI: pli $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_REV, ARM_INS_REV: rev${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_REV16, ARM_INS_REV16: rev16${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_REVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_RFEDA, ARM_INS_RFEDA: rfeda $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEDB, ARM_INS_RFEDB: rfedb $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEIA, ARM_INS_RFEIA: rfeia $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEIB, ARM_INS_RFEIB: rfeib $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_RSBri, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_RSBrsi, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_RSBrsr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_RSCri, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_RSCrr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_RSCrsi, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_RSCrsr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SBCrr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SBCrsi, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SBCrsr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $width */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SETEND, ARM_INS_SETEND: setend $end */ + { 0 } +}, +{ /* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMC, ARM_INS_SMC: smc${p} $opt */ + { 0 } +}, +{ /* ARM_SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLAL, ARM_INS_SMLAL: smlal${s}${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALD, ARM_INS_SMLALD: smlald${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULL, ARM_INS_SMULL: smull${s}${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SRSDA, ARM_INS_SRSDA: srsda sp, $mode */ + { 0 } +}, +{ /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda sp!, $mode */ + { 0 } +}, +{ /* ARM_SRSDB, ARM_INS_SRSDB: srsdb sp, $mode */ + { 0 } +}, +{ /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb sp!, $mode */ + { 0 } +}, +{ /* ARM_SRSIA, ARM_INS_SRSIA: srsia sp, $mode */ + { 0 } +}, +{ /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia sp!, $mode */ + { 0 } +}, +{ /* ARM_SRSIB, ARM_INS_SRSIB: srsib sp, $mode */ + { 0 } +}, +{ /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib sp!, $mode */ + { 0 } +}, +{ /* ARM_SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STL, ARM_INS_STL: stl${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STMDA, ARM_INS_STMDA: stmda${p} $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_STMIA, ARM_INS_STM: stm${p} $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_STMIB, ARM_INS_STMIB: stmib${p} $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRB_POST_REG, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRBi12, ARM_INS_STRB: strb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRBrs, ARM_INS_STRB: strb${p} $rt, $shift */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRD, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRH, ARM_INS_STRH: strh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRHTi, ARM_INS_STRHT: strht${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRHTr, ARM_INS_STRHT: strht${p} $rt, $addr, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRH_POST, ARM_INS_STRH: strh${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRT_POST_REG, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STR_POST_IMM, ARM_INS_STR: str${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STR_POST_REG, ARM_INS_STR: str${p} $rt, $addr, $offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STR_PRE_IMM, ARM_INS_STR: str${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STR_PRE_REG, ARM_INS_STR: str${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRi12, ARM_INS_STR: str${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_STRrs, ARM_INS_STR: str${p} $rt, $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_SUBri, ARM_INS_SUB: sub${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SUBrsi, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SUBrsr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SVC, ARM_INS_SVC: svc${p} $svc */ + { 0 } +}, +{ /* ARM_SWP, ARM_INS_SWP: swp${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SWPB, ARM_INS_SWPB: swpb${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_SXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_SXTH, ARM_INS_SXTH: sxth${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_TEQri, ARM_INS_TEQ: teq${p} $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_TEQrr, ARM_INS_TEQ: teq${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_TEQrsi, ARM_INS_TEQ: teq${p} $rn, $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_TEQrsr, ARM_INS_TEQ: teq${p} $rn, $shift */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_TRAP, ARM_INS_TRAP: trap */ + { 0 } +}, +{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ + { 0 } +}, +{ /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_TSTrr, ARM_INS_TST: tst${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_TSTrsi, ARM_INS_TST: tst${p} $rn, $shift */ + { CS_AC_READ, 0 } +}, +{ /* ARM_TSTrsr, ARM_INS_TST: tst${p} $rn, $shift */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $width */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_UDF, ARM_INS_UDF: udf $imm16 */ + { 0 } +}, +{ /* ARM_UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UMLAL, ARM_INS_UMLAL: umlal${s}${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UMULL, ARM_INS_UMULL: umull${s}${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_UXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_UXTH, ARM_INS_UXTH: uxth${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VABSD, ARM_INS_VABS: vabs${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSS, ARM_INS_VABS: vabs${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDD, ARM_INS_VADD: vadd${p}.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDS, ARM_INS_VADD: vadd${p}.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VANDd, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VANDq, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBICd, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VBICq, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBIFd, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBIFq, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBITd, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBITq, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBSLd, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VBSLq, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCMPD, ARM_INS_VCMP: vcmp${p}.f64 $dd, $dm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, $dm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, $sm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, #0 */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, #0 */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VCMPS, ARM_INS_VCMP: vcmp${p}.f32 $sd, $sm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VCMPZD, ARM_INS_VCMP: vcmp${p}.f64 $dd, #0 */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VCMPZS, ARM_INS_VCMP: vcmp${p}.f32 $sd, #0 */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb${p}.f16.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb${p}.f64.f16 $dd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb${p}.f32.f16 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb${p}.f16.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTDS, ARM_INS_VCVT: vcvt${p}.f64.f32 $dd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTSD, ARM_INS_VCVT: vcvt${p}.f32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt${p}.f16.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt${p}.f64.f16 $dd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt${p}.f32.f16 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt${p}.f16.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDIVD, ARM_INS_VDIV: vdiv${p}.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VDIVS, ARM_INS_VDIV: vdiv${p}.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP16d, ARM_INS_VDUP: vdup${p}.16 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP16q, ARM_INS_VDUP: vdup${p}.16 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP32d, ARM_INS_VDUP: vdup${p}.32 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP32q, ARM_INS_VDUP: vdup${p}.32 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP8d, ARM_INS_VDUP: vdup${p}.8 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUP8q, ARM_INS_VDUP: vdup${p}.8 $v, $r */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VEORd, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEORq, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMAD, ARM_INS_VFMA: vfma${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMAS, ARM_INS_VFMA: vfma${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMSD, ARM_INS_VFMS: vfms${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMSS, ARM_INS_VFMS: vfms${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VGETLNi32, ARM_INS_VMOV: vmov${p}.32 $r, $v$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VGETLNs16, ARM_INS_VMOV: vmov${p}.s16 $r, $v$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VGETLNs8, ARM_INS_VMOV: vmov${p}.s8 $r, $v$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VGETLNu16, ARM_INS_VMOV: vmov${p}.u16 $r, $v$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VGETLNu8, ARM_INS_VMOV: vmov${p}.u8 $r, $v$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDRD, ARM_INS_VLDR: vldr${p} $dd, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VLDRS, ARM_INS_VLDR: vldr${p} $sd, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAD, ARM_INS_VMLA: vmla${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAS, ARM_INS_VMLA: vmla${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSD, ARM_INS_VMLS: vmls${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl${p}.u8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSS, ARM_INS_VMLS: vmls${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVD, ARM_INS_VMOV: vmov${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVDRR, ARM_INS_VMOV: vmov${p} $dm, $rt, $rt2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl${p}.u16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl${p}.u8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn${p}.i64 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn${p}.i32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn${p}.i16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVRRD, ARM_INS_VMOV: vmov${p} $rt, $rt2, $dm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVRRS, ARM_INS_VMOV: vmov${p} $rt, $rt2, $src1, $src2 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVRS, ARM_INS_VMOV: vmov${p} $rt, $sn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVS, ARM_INS_VMOV: vmov${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVSR, ARM_INS_VMOV: vmov${p} $sn, $rt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVSRR, ARM_INS_VMOV: vmov${p} $dst1, $dst2, $src1, $src2 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS, ARM_INS_VMRS: vmrs${p} $rt, fpscr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs${p} $rt, fpexc */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs${p} $rt, fpinst */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs${p} $rt, fpinst2 */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs${p} $rt, fpsid */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs${p} $rt, mvfr0 */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs${p} $rt, mvfr1 */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs${p} $rt, mvfr2 */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMSR, ARM_INS_VMSR: vmsr${p} fpscr, $src */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr${p} fpexc, $src */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr${p} fpinst, $src */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr${p} fpinst2, $src */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr${p} fpsid, $src */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULD, ARM_INS_VMUL: vmul${p}.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLp64, ARM_INS_VMULL: vmull.p64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLp8, ARM_INS_VMULL: vmull${p}.p8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULS, ARM_INS_VMUL: vmul${p}.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULpd, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULpq, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv16i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMULv8i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VMVNd, ARM_INS_VMVN: vmvn${p} $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMVNq, ARM_INS_VMVN: vmvn${p} $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VMVNv2i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMVNv4i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_VNEGD, ARM_INS_VNEG: vneg${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGS, ARM_INS_VNEG: vneg${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGf32q, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGfd, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs16d, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs16q, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs32d, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs32q, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs8d, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNEGs8q, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls${p}.f64 $dd, $dn, $dm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls${p}.f32 $sd, $sn, $sm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VNMULD, ARM_INS_VNMUL: vnmul${p}.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VNMULS, ARM_INS_VNMUL: vnmul${p}.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VORNd, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VORNq, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VORRd, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VORRiv2i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VORRiv4i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VORRiv4i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VORRiv8i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VORRq, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDf, ARM_INS_VPADD: vpadd${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDi16, ARM_INS_VPADD: vpadd${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDi32, ARM_INS_VPADD: vpadd${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPADDi8, ARM_INS_VPADD: vpadd${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINf, ARM_INS_VPMIN: vpmin${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun${p}.s64 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn${p}.s64 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn${p}.u64 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn${p}.u16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VREV16d8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV16q8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV32d16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV32d8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV32q16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV32q8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64d16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64d32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64d8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64q16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64q32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VREV64q8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTAND, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTANQ, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTMND, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTMNQ, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTND, ARM_INS_VRINTN: vrintn.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTNND, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTNNQ, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTPND, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTPNQ, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTXND, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTXNQ, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTZND, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTZNQ, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn${p}.i64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn${p}.i32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn${p}.i16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELGED, ARM_INS_VSELGE: vselge.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELGES, ARM_INS_VSELGE: vselge.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSETLNi16, ARM_INS_VMOV: vmov${p}.16 $v$lane, $r */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSETLNi32, ARM_INS_VMOV: vmov${p}.32 $v$lane, $r */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSETLNi8, ARM_INS_VMOV: vmov${p}.8 $v$lane, $r */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll${p}.i16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll${p}.i32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll${p}.i8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn${p}.i64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn${p}.i32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn${p}.i16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSITOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSITOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt${p}.f64 $dd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt${p}.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd16, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd32, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd8, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn$rm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16Q, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16T, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32Q, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32T, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64Q, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64T, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8Q, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8T, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSTMDDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSTMSDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VSTRD, ARM_INS_VSTR: vstr${p} $dd, $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VSTRS, ARM_INS_VSTR: vstr${p} $sd, $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_VSUBD, ARM_INS_VSUB: vsub${p}.f64 $dd, $dn, $dm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBS, ARM_INS_VSUB: vsub${p}.f32 $sd, $sn, $sm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw${p}.s32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw${p}.s16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw${p}.s8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw${p}.u32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw${p}.u16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw${p}.u8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBfd, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBfq, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VSWPd, ARM_INS_VSWP: vswp${p} $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VSWPq, ARM_INS_VSWP: vswp${p} $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTBL1, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBL2, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBL3, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBL4, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBX1, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBX2, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBX3, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTBX4, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr${p}.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr${p}.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt${p}.s32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt${p}.s32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr${p}.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr${p}.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt${p}.u32.f64 $sd, $dm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt${p}.u32.f32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VTOULD, ARM_INS_VCVT: vcvt${p}.u32.f64 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTOULS, ARM_INS_VCVT: vcvt${p}.u32.f32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNd16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNd32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNd8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNq16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNq32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTRNq8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VTSTv16i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTSTv2i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTSTv4i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTSTv4i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTSTv8i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VTSTv8i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_VUHTOD, ARM_INS_VCVT: vcvt${p}.f64.u16 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VUHTOS, ARM_INS_VCVT: vcvt${p}.f32.u16 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VUITOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VUITOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $sd, $sm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_VULTOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VULTOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $dst, $a, $fbits */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_VUZPd16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VUZPd8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VUZPq16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VUZPq32, ARM_INS_VUZP: vuzp${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VUZPq8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VZIPd16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VZIPd8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VZIPq16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VZIPq32, ARM_INS_VZIP: vzip${p}.32 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_VZIPq8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_sysSTMDA, ARM_INS_STMDA: stmda${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMIA, ARM_INS_STM: stm${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMIB, ARM_INS_STMIB: stmib${p} $rn, $regs ^ */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs ^ */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADCrr, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADCrs, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADDri, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADDri12, ARM_INS_ADDW: addw${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADDrr, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADDrs, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ADR, ARM_INS_ADR: adr{$p}.w $rd, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ANDrr, ARM_INS_AND: and${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2ANDrs, ARM_INS_AND: and${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ASRri, ARM_INS_ASR: asr${s}${p}.w $rd, $rm, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ASRrr, ARM_INS_ASR: asr${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2B, ARM_INS_B: b${p}.w $target */ + { 0 } +}, +{ /* ARM_t2BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_t2BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2BICrr, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2BICrs, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2BXJ, ARM_INS_BXJ: bxj${p} $func */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2Bcc, ARM_INS_B: b${p}.w $target */ + { 0 } +}, +{ /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex${p} */ + { 0 } +}, +{ /* ARM_t2CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2CMNri, ARM_INS_CMN: cmn${p}.w $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2CMNzrr, ARM_INS_CMN: cmn${p}.w $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CMNzrs, ARM_INS_CMN: cmn${p}.w $rn, $shiftedrm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2CMPri, ARM_INS_CMP: cmp${p}.w $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2CMPrr, ARM_INS_CMP: cmp${p}.w $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CMPrs, ARM_INS_CMP: cmp${p}.w $rn, $shiftedrm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2CPS1p, ARM_INS_CPS: cps $mode */ + { 0 } +}, +{ /* ARM_t2CPS2p, ARM_INS_CPS: cps$imod.w $iflags */ + { 0 } +}, +{ /* ARM_t2CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ + { 0 } +}, +{ /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2DBG, ARM_INS_DBG: dbg${p} $opt */ + { 0 } +}, +{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1${p} */ + { 0 } +}, +{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2${p} */ + { 0 } +}, +{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3${p} */ + { 0 } +}, +{ /* ARM_t2DMB, ARM_INS_DMB: dmb${p} $opt */ + { 0 } +}, +{ /* ARM_t2DSB, ARM_INS_DSB: dsb${p} $opt */ + { 0 } +}, +{ /* ARM_t2EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2EORrr, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2EORrs, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2HINT, ARM_INS_HINT: hint${p}.w $imm */ + { 0 } +}, +{ /* ARM_t2HVC, ARM_INS_HVC: hvc.w $imm16 */ + { 0 } +}, +{ /* ARM_t2ISB, ARM_INS_ISB: isb${p} $opt */ + { 0 } +}, +{ /* ARM_t2IT, ARM_INS_IT: it$mask $cc */ + { 0 } +}, +{ /* ARM_t2LDA, ARM_INS_LDA: lda${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDMIA, ARM_INS_LDM: ldm${p}.w $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm${p}.w $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb${p} $rt, $rn$offset */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr$imm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $rn$offset */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $rn$offset */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $rn$offset */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LDRT, ARM_INS_LDRT: ldrt${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDR_POST, ARM_INS_LDR: ldr${p} $rt, $rn$offset */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr${p} $rt, $addr! */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRi12, ARM_INS_LDR: ldr${p}.w $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRi8, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRpci, ARM_INS_LDR: ldr${p}.w $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2LDRs, ARM_INS_LDR: ldr${p}.w $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LSLri, ARM_INS_LSL: lsl${s}${p}.w $rd, $rm, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LSLrr, ARM_INS_LSL: lsl${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2LSRri, ARM_INS_LSR: lsr${s}${p}.w $rd, $rm, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2LSRrr, ARM_INS_LSR: lsr${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MLA, ARM_INS_MLA: mla${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MOVi, ARM_INS_MOV: mov${s}${p}.w $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MOVr, ARM_INS_MOV: mov${s}${p}.w $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd, $rm, #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd, $rm, #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2MRC2, ARM_INS_MRC2: mrc2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, +{ /* ARM_t2MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2${p} $cop, $opc1, $rt, $rt2, $crm */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MRS_AR, ARM_INS_MRS: mrs${p} $rd, apsr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MRS_M, ARM_INS_MRS: mrs${p} $rd, $sysm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs${p} $rd, spsr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MSR_AR, ARM_INS_MSR: msr${p} $mask, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2MSR_M, ARM_INS_MSR: msr${p} $sysm, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2MUL, ARM_INS_MUL: mul${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2MVNr, ARM_INS_MVN: mvn${s}${p}.w $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2MVNs, ARM_INS_MVN: mvn${s}${p}.w $rd, $shiftedrm */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2ORNri, ARM_INS_ORN: orn${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ORNrr, ARM_INS_ORN: orn${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2ORNrs, ARM_INS_ORN: orn${s}${p} $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2ORRrr, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2ORRrs, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDWs, ARM_INS_PLDW: pldw${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDi12, ARM_INS_PLD: pld${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDi8, ARM_INS_PLD: pld${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDpci, ARM_INS_PLD: pld${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLDs, ARM_INS_PLD: pld${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLIi12, ARM_INS_PLI: pli${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLIi8, ARM_INS_PLI: pli${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLIpci, ARM_INS_PLI: pli${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2PLIs, ARM_INS_PLI: pli${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2REV, ARM_INS_REV: rev${p}.w $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2REV16, ARM_INS_REV16: rev16${p}.w $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2REVSH, ARM_INS_REVSH: revsh${p}.w $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb${p} $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb${p} $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia${p} $rn */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia${p} $rn! */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2RORri, ARM_INS_ROR: ror${s}${p}.w $rd, $rm, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2RORrr, ARM_INS_ROR: ror${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2RRX, ARM_INS_RRX: rrx${s}${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2RSBri, ARM_INS_RSB: rsb${s}${p}.w $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2RSBrs, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SBCrr, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SBCrs, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $msb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMC, ARM_INS_SMC: smc${p} $opt */ + { 0 } +}, +{ /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $ra, $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULL, ARM_INS_SMULL: smull${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb${p} sp, $mode */ + { 0 } +}, +{ /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb${p} sp!, $mode */ + { 0 } +}, +{ /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia${p} sp, $mode */ + { 0 } +}, +{ /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia${p} sp!, $mode */ + { 0 } +}, +{ /* ARM_t2SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2_POST, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STL, ARM_INS_STL: stl${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2STMIA, ARM_INS_STM: stm${p}.w $rn, $regs */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STMIA_UPD, ARM_INS_STM: stm${p}.w $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2STRBT, ARM_INS_STRBT: strbt${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRB_POST, ARM_INS_STRB: strb${p} $rt, $rn$offset */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2STRB_PRE, ARM_INS_STRB: strb${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRBi12, ARM_INS_STRB: strb${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRBi8, ARM_INS_STRB: strb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRBs, ARM_INS_STRB: strb${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr$imm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STRDi8, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $rt2, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2STRHT, ARM_INS_STRHT: strht${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRH_POST, ARM_INS_STRH: strh${p} $rt, $rn$offset */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRHi12, ARM_INS_STRH: strh${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRHi8, ARM_INS_STRH: strh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRHs, ARM_INS_STRH: strh${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRT, ARM_INS_STRT: strt${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STR_POST, ARM_INS_STR: str${p} $rt, $rn$offset */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2STR_PRE, ARM_INS_STR: str${p} $rt, $addr! */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRi12, ARM_INS_STR: str${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRi8, ARM_INS_STR: str${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2STRs, ARM_INS_STR: str${p}.w $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_t2SUBS_PC_LR, ARM_INS_SUB: subs${p} pc, lr, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SUBri, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SUBri12, ARM_INS_SUBW: subw${p} $rd, $rn, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SUBrr, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2SUBrs, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $shiftedrm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTB, ARM_INS_SXTB: sxtb${p}.w $rd, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2SXTH, ARM_INS_SXTH: sxth${p}.w $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2TBB, ARM_INS_TBB: tbb${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2TBH, ARM_INS_TBH: tbh${p} $addr */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2TEQri, ARM_INS_TEQ: teq${p}.w $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2TEQrr, ARM_INS_TEQ: teq${p}.w $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2TEQrs, ARM_INS_TEQ: teq${p}.w $rn, $shiftedrm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2TSTri, ARM_INS_TST: tst${p}.w $rn, $imm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2TSTrr, ARM_INS_TST: tst${p}.w $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2TSTrs, ARM_INS_TST: tst${p}.w $rn, $shiftedrm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_t2UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $msb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2UDF, ARM_INS_UDF: udf.w $imm16 */ + { 0 } +}, +{ /* ARM_t2UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UMULL, ARM_INS_UMULL: umull${p} $rdlo, $rdhi, $rn, $rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, +{ /* ARM_t2USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_t2UXTB, ARM_INS_UXTB: uxtb${p}.w $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_t2UXTH, ARM_INS_UXTH: uxth${p}.w $rd, $rm$rot */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tADC, ARM_INS_ADC: adc${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tADDhirr, ARM_INS_ADD: add${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tADDi8, ARM_INS_ADD: add${s}${p} $rdn, $imm8 */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_tADDrSP, ARM_INS_ADD: add${p} $rdn, $sp, $rn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tADDrSPi, ARM_INS_ADD: add${p} $dst, $sp, $imm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tADDspi, ARM_INS_ADD: add${p} $rdn, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_tADDspr, ARM_INS_ADD: add${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tADR, ARM_INS_ADR: adr{$p} $rd, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tAND, ARM_INS_AND: and${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tASRri, ARM_INS_ASR: asr${s}${p} $rd, $rm, $imm5 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tASRrr, ARM_INS_ASR: asr${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tB, ARM_INS_B: b${p} $target */ + { 0 } +}, +{ /* ARM_tBIC, ARM_INS_BIC: bic${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tBKPT, ARM_INS_BKPT: bkpt $val */ + { 0 } +}, +{ /* ARM_tBL, ARM_INS_BL: bl${p} $func */ + { 0 } +}, +{ /* ARM_tBLXi, ARM_INS_BLX: blx${p} $func */ + { 0 } +}, +{ /* ARM_tBLXr, ARM_INS_BLX: blx${p} $func */ + { CS_AC_READ, 0 } +}, +{ /* ARM_tBX, ARM_INS_BX: bx${p} $rm */ + { CS_AC_READ, 0 } +}, +{ /* ARM_tBcc, ARM_INS_B: b${p} $target */ + { 0 } +}, +{ /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz $rn, $target */ + { CS_AC_READ, 0 } +}, +{ /* ARM_tCBZ, ARM_INS_CBZ: cbz $rn, $target */ + { CS_AC_READ, 0 } +}, +{ /* ARM_tCMNz, ARM_INS_CMN: cmn${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tCMPhir, ARM_INS_CMP: cmp${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tCMPi8, ARM_INS_CMP: cmp${p} $rn, $imm8 */ + { CS_AC_READ, 0 } +}, +{ /* ARM_tCMPr, ARM_INS_CMP: cmp${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tCPS, ARM_INS_CPS: cps$imod $iflags */ + { 0 } +}, +{ /* ARM_tEOR, ARM_INS_EOR: eor${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tHINT, ARM_INS_HINT: hint${p} $imm */ + { 0 } +}, +{ /* ARM_tHLT, ARM_INS_HLT: hlt $val */ + { 0 } +}, +{ /* ARM_tLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRBi, ARM_INS_LDRB: ldrb${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRBr, ARM_INS_LDRB: ldrb${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRHi, ARM_INS_LDRH: ldrh${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRHr, ARM_INS_LDRH: ldrh${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tLDRi, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLDRpci, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLDRr, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLDRspi, ARM_INS_LDR: ldr${p} $rt, $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLSLri, ARM_INS_LSL: lsl${s}${p} $rd, $rm, $imm5 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLSLrr, ARM_INS_LSL: lsl${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLSRri, ARM_INS_LSR: lsr${s}${p} $rd, $rm, $imm5 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tLSRrr, ARM_INS_LSR: lsr${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tMOVSr, ARM_INS_MOV: movs $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tMOVi8, ARM_INS_MOV: mov${s}${p} $rd, $imm8 */ + { CS_AC_WRITE, 0 } +}, +{ /* ARM_tMOVr, ARM_INS_MOV: mov${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tMUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_tMVN, ARM_INS_MVN: mvn${s}${p} $rd, $rn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tORR, ARM_INS_ORR: orr${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tPOP, ARM_INS_POP: pop${p} $regs */ + { 0 } +}, +{ /* ARM_tPUSH, ARM_INS_PUSH: push${p} $regs */ + { 0 } +}, +{ /* ARM_tREV, ARM_INS_REV: rev${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tREV16, ARM_INS_REV16: rev16${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tREVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tROR, ARM_INS_ROR: ror${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tRSB, ARM_INS_RSB: rsb${s}${p} $rd, $rn, #0 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tSBC, ARM_INS_SBC: sbc${s}${p} $rdn, $rm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tSETEND, ARM_INS_SETEND: setend $end */ + { 0 } +}, +{ /* ARM_tSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tSTRBi, ARM_INS_STRB: strb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRBr, ARM_INS_STRB: strb${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRHi, ARM_INS_STRH: strh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRHr, ARM_INS_STRH: strh${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRi, ARM_INS_STR: str${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRr, ARM_INS_STR: str${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSTRspi, ARM_INS_STR: str${p} $rt, $addr */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, +{ /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tSUBi8, ARM_INS_SUB: sub${s}${p} $rdn, $imm8 */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_tSUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tSUBspi, ARM_INS_SUB: sub${p} $rdn, $imm */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, +{ /* ARM_tSVC, ARM_INS_SVC: svc${p} $imm */ + { 0 } +}, +{ /* ARM_tSXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tSXTH, ARM_INS_SXTH: sxth${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ + { 0 } +}, +{ /* ARM_tTST, ARM_INS_TST: tst${p} $rn, $rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, +{ /* ARM_tUDF, ARM_INS_UDF: udf $imm8 */ + { 0 } +}, +{ /* ARM_tUXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, +{ /* ARM_tUXTH, ARM_INS_UXTH: uxth${p} $rd, $rm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.c b/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.c new file mode 100644 index 0000000..8f8c72d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.c @@ -0,0 +1,379 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#include +#include // offsetof macro + // alternatively #include "../../utils.h" like everyone else + +#include "EVMDisassembler.h" +#include "EVMMapping.h" + +static short opcodes[256] = { + EVM_INS_STOP, + EVM_INS_ADD, + EVM_INS_MUL, + EVM_INS_SUB, + EVM_INS_DIV, + EVM_INS_SDIV, + EVM_INS_MOD, + EVM_INS_SMOD, + EVM_INS_ADDMOD, + EVM_INS_MULMOD, + EVM_INS_EXP, + EVM_INS_SIGNEXTEND, + -1, + -1, + -1, + -1, + EVM_INS_LT, + EVM_INS_GT, + EVM_INS_SLT, + EVM_INS_SGT, + EVM_INS_EQ, + EVM_INS_ISZERO, + EVM_INS_AND, + EVM_INS_OR, + EVM_INS_XOR, + EVM_INS_NOT, + EVM_INS_BYTE, + -1, + -1, + -1, + -1, + -1, + EVM_INS_SHA3, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + EVM_INS_ADDRESS, + EVM_INS_BALANCE, + EVM_INS_ORIGIN, + EVM_INS_CALLER, + EVM_INS_CALLVALUE, + EVM_INS_CALLDATALOAD, + EVM_INS_CALLDATASIZE, + EVM_INS_CALLDATACOPY, + EVM_INS_CODESIZE, + EVM_INS_CODECOPY, + EVM_INS_GASPRICE, + EVM_INS_EXTCODESIZE, + EVM_INS_EXTCODECOPY, + EVM_INS_RETURNDATASIZE, + EVM_INS_RETURNDATACOPY, + -1, + EVM_INS_BLOCKHASH, + EVM_INS_COINBASE, + EVM_INS_TIMESTAMP, + EVM_INS_NUMBER, + EVM_INS_DIFFICULTY, + EVM_INS_GASLIMIT, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + EVM_INS_POP, + EVM_INS_MLOAD, + EVM_INS_MSTORE, + EVM_INS_MSTORE8, + EVM_INS_SLOAD, + EVM_INS_SSTORE, + EVM_INS_JUMP, + EVM_INS_JUMPI, + EVM_INS_PC, + EVM_INS_MSIZE, + EVM_INS_GAS, + EVM_INS_JUMPDEST, + -1, + -1, + -1, + -1, + EVM_INS_PUSH1, + EVM_INS_PUSH2, + EVM_INS_PUSH3, + EVM_INS_PUSH4, + EVM_INS_PUSH5, + EVM_INS_PUSH6, + EVM_INS_PUSH7, + EVM_INS_PUSH8, + EVM_INS_PUSH9, + EVM_INS_PUSH10, + EVM_INS_PUSH11, + EVM_INS_PUSH12, + EVM_INS_PUSH13, + EVM_INS_PUSH14, + EVM_INS_PUSH15, + EVM_INS_PUSH16, + EVM_INS_PUSH17, + EVM_INS_PUSH18, + EVM_INS_PUSH19, + EVM_INS_PUSH20, + EVM_INS_PUSH21, + EVM_INS_PUSH22, + EVM_INS_PUSH23, + EVM_INS_PUSH24, + EVM_INS_PUSH25, + EVM_INS_PUSH26, + EVM_INS_PUSH27, + EVM_INS_PUSH28, + EVM_INS_PUSH29, + EVM_INS_PUSH30, + EVM_INS_PUSH31, + EVM_INS_PUSH32, + EVM_INS_DUP1, + EVM_INS_DUP2, + EVM_INS_DUP3, + EVM_INS_DUP4, + EVM_INS_DUP5, + EVM_INS_DUP6, + EVM_INS_DUP7, + EVM_INS_DUP8, + EVM_INS_DUP9, + EVM_INS_DUP10, + EVM_INS_DUP11, + EVM_INS_DUP12, + EVM_INS_DUP13, + EVM_INS_DUP14, + EVM_INS_DUP15, + EVM_INS_DUP16, + EVM_INS_SWAP1, + EVM_INS_SWAP2, + EVM_INS_SWAP3, + EVM_INS_SWAP4, + EVM_INS_SWAP5, + EVM_INS_SWAP6, + EVM_INS_SWAP7, + EVM_INS_SWAP8, + EVM_INS_SWAP9, + EVM_INS_SWAP10, + EVM_INS_SWAP11, + EVM_INS_SWAP12, + EVM_INS_SWAP13, + EVM_INS_SWAP14, + EVM_INS_SWAP15, + EVM_INS_SWAP16, + EVM_INS_LOG0, + EVM_INS_LOG1, + EVM_INS_LOG2, + EVM_INS_LOG3, + EVM_INS_LOG4, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + EVM_INS_CREATE, + EVM_INS_CALL, + EVM_INS_CALLCODE, + EVM_INS_RETURN, + EVM_INS_DELEGATECALL, + EVM_INS_CALLBLACKBOX, + -1, + -1, + -1, + -1, + EVM_INS_STATICCALL, + -1, + -1, + EVM_INS_REVERT, + -1, + EVM_INS_SUICIDE, +}; + +bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) +{ + unsigned char opcode; + + if (code_len == 0) + return false; + + opcode = code[0]; + if (opcodes[opcode] == -1) { + // invalid opcode + return false; + } + + // valid opcode + MI->address = address; + MI->OpcodePub = MI->Opcode = opcode; + + if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) { + unsigned char len = (opcode - EVM_INS_PUSH1 + 1); + if (code_len < 1 + len) { + // not enough data + return false; + } + + *size = 1 + len; + memcpy(MI->evm_data, code + 1, len); + } else + *size = 1; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, evm)+sizeof(cs_evm)); + EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode); + + if (MI->flat_insn->detail->evm.pop) { + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_READ; + MI->flat_insn->detail->groups_count++; + } + + if (MI->flat_insn->detail->evm.push) { + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_WRITE; + MI->flat_insn->detail->groups_count++; + } + + // setup groups + switch(opcode) { + default: + break; + case EVM_INS_ADD: + case EVM_INS_MUL: + case EVM_INS_SUB: + case EVM_INS_DIV: + case EVM_INS_SDIV: + case EVM_INS_MOD: + case EVM_INS_SMOD: + case EVM_INS_ADDMOD: + case EVM_INS_MULMOD: + case EVM_INS_EXP: + case EVM_INS_SIGNEXTEND: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_MSTORE: + case EVM_INS_MSTORE8: + case EVM_INS_CALLDATACOPY: + case EVM_INS_CODECOPY: + case EVM_INS_EXTCODECOPY: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_MLOAD: + case EVM_INS_CREATE: + case EVM_INS_CALL: + case EVM_INS_CALLCODE: + case EVM_INS_RETURN: + case EVM_INS_DELEGATECALL: + case EVM_INS_REVERT: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_SSTORE: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_SLOAD: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_JUMP: + case EVM_INS_JUMPI: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_JUMP; + MI->flat_insn->detail->groups_count++; + break; + + case EVM_INS_STOP: + case EVM_INS_SUICIDE: + MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT; + MI->flat_insn->detail->groups_count++; + break; + + } + } + + return true; +} diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.h b/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.h new file mode 100644 index 0000000..afd7e46 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMDisassembler.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#ifndef CS_EVMDISASSEMBLER_H +#define CS_EVMDISASSEMBLER_H + +#include "../../MCInst.h" + +bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.c b/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.c new file mode 100644 index 0000000..7f45280 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.c @@ -0,0 +1,20 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#include "EVMInstPrinter.h" +#include "EVMMapping.h" + + +void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) +{ + SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode)); + + if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) { + unsigned int i; + + SStream_concat0(O, "\t"); + for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) { + SStream_concat(O, "%02x", MI->evm_data[i]); + } + } +} diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.h b/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.h new file mode 100644 index 0000000..2f1ac2c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMInstPrinter.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#ifndef CS_EVMINSTPRINTER_H +#define CS_EVMINSTPRINTER_H + + +#include "capstone/capstone.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../cs_priv.h" + +struct SStream; + +void EVM_printInst(MCInst *MI, struct SStream *O, void *Info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMMapping.c b/white_patch_detect/capstone-master/arch/EVM/EVMMapping.c new file mode 100644 index 0000000..d6e94b5 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMMapping.c @@ -0,0 +1,344 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#ifdef CAPSTONE_HAS_EVM + +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "EVMMapping.h" + +#ifndef CAPSTONE_DIET +static cs_evm insns[256] = { +#include "EVMMappingInsn.inc" +}; +#endif + +// look for @id in @insns, given its size in @max. +// return -1 if not found +static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id) +{ + if (id >= max) + return -1; + + if (insns[id].fee == 0xffffffff) + // unused opcode + return -1; + + return (int)id; +} + +// fill in details +void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + insn->id = id; +#ifndef CAPSTONE_DIET + if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) { + if (h->detail) { + memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id])); + } + } +#endif +} + +#ifndef CAPSTONE_DIET +static name_map insn_name_maps[256] = { + { EVM_INS_STOP, "stop" }, + { EVM_INS_ADD, "add" }, + { EVM_INS_MUL, "mul" }, + { EVM_INS_SUB, "sub" }, + { EVM_INS_DIV, "div" }, + { EVM_INS_SDIV, "sdiv" }, + { EVM_INS_MOD, "mod" }, + { EVM_INS_SMOD, "smod" }, + { EVM_INS_ADDMOD, "addmod" }, + { EVM_INS_MULMOD, "mulmod" }, + { EVM_INS_EXP, "exp" }, + { EVM_INS_SIGNEXTEND, "signextend" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_LT, "lt" }, + { EVM_INS_GT, "gt" }, + { EVM_INS_SLT, "slt" }, + { EVM_INS_SGT, "sgt" }, + { EVM_INS_EQ, "eq" }, + { EVM_INS_ISZERO, "iszero" }, + { EVM_INS_AND, "and" }, + { EVM_INS_OR, "or" }, + { EVM_INS_XOR, "xor" }, + { EVM_INS_NOT, "not" }, + { EVM_INS_BYTE, "byte" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_SHA3, "sha3" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_ADDRESS, "address" }, + { EVM_INS_BALANCE, "balance" }, + { EVM_INS_ORIGIN, "origin" }, + { EVM_INS_CALLER, "caller" }, + { EVM_INS_CALLVALUE, "callvalue" }, + { EVM_INS_CALLDATALOAD, "calldataload" }, + { EVM_INS_CALLDATASIZE, "calldatasize" }, + { EVM_INS_CALLDATACOPY, "calldatacopy" }, + { EVM_INS_CODESIZE, "codesize" }, + { EVM_INS_CODECOPY, "codecopy" }, + { EVM_INS_GASPRICE, "gasprice" }, + { EVM_INS_EXTCODESIZE, "extcodesize" }, + { EVM_INS_EXTCODECOPY, "extcodecopy" }, + { EVM_INS_RETURNDATASIZE, "returndatasize" }, + { EVM_INS_RETURNDATACOPY, "returndatacopy" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_BLOCKHASH, "blockhash" }, + { EVM_INS_COINBASE, "coinbase" }, + { EVM_INS_TIMESTAMP, "timestamp" }, + { EVM_INS_NUMBER, "number" }, + { EVM_INS_DIFFICULTY, "difficulty" }, + { EVM_INS_GASLIMIT, "gaslimit" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_POP, "pop" }, + { EVM_INS_MLOAD, "mload" }, + { EVM_INS_MSTORE, "mstore" }, + { EVM_INS_MSTORE8, "mstore8" }, + { EVM_INS_SLOAD, "sload" }, + { EVM_INS_SSTORE, "sstore" }, + { EVM_INS_JUMP, "jump" }, + { EVM_INS_JUMPI, "jumpi" }, + { EVM_INS_PC, "pc" }, + { EVM_INS_MSIZE, "msize" }, + { EVM_INS_GAS, "gas" }, + { EVM_INS_JUMPDEST, "jumpdest" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_PUSH1, "push1" }, + { EVM_INS_PUSH2, "push2" }, + { EVM_INS_PUSH3, "push3" }, + { EVM_INS_PUSH4, "push4" }, + { EVM_INS_PUSH5, "push5" }, + { EVM_INS_PUSH6, "push6" }, + { EVM_INS_PUSH7, "push7" }, + { EVM_INS_PUSH8, "push8" }, + { EVM_INS_PUSH9, "push9" }, + { EVM_INS_PUSH10, "push10" }, + { EVM_INS_PUSH11, "push11" }, + { EVM_INS_PUSH12, "push12" }, + { EVM_INS_PUSH13, "push13" }, + { EVM_INS_PUSH14, "push14" }, + { EVM_INS_PUSH15, "push15" }, + { EVM_INS_PUSH16, "push16" }, + { EVM_INS_PUSH17, "push17" }, + { EVM_INS_PUSH18, "push18" }, + { EVM_INS_PUSH19, "push19" }, + { EVM_INS_PUSH20, "push20" }, + { EVM_INS_PUSH21, "push21" }, + { EVM_INS_PUSH22, "push22" }, + { EVM_INS_PUSH23, "push23" }, + { EVM_INS_PUSH24, "push24" }, + { EVM_INS_PUSH25, "push25" }, + { EVM_INS_PUSH26, "push26" }, + { EVM_INS_PUSH27, "push27" }, + { EVM_INS_PUSH28, "push28" }, + { EVM_INS_PUSH29, "push29" }, + { EVM_INS_PUSH30, "push30" }, + { EVM_INS_PUSH31, "push31" }, + { EVM_INS_PUSH32, "push32" }, + { EVM_INS_DUP1, "dup1" }, + { EVM_INS_DUP2, "dup2" }, + { EVM_INS_DUP3, "dup3" }, + { EVM_INS_DUP4, "dup4" }, + { EVM_INS_DUP5, "dup5" }, + { EVM_INS_DUP6, "dup6" }, + { EVM_INS_DUP7, "dup7" }, + { EVM_INS_DUP8, "dup8" }, + { EVM_INS_DUP9, "dup9" }, + { EVM_INS_DUP10, "dup10" }, + { EVM_INS_DUP11, "dup11" }, + { EVM_INS_DUP12, "dup12" }, + { EVM_INS_DUP13, "dup13" }, + { EVM_INS_DUP14, "dup14" }, + { EVM_INS_DUP15, "dup15" }, + { EVM_INS_DUP16, "dup16" }, + { EVM_INS_SWAP1, "swap1" }, + { EVM_INS_SWAP2, "swap2" }, + { EVM_INS_SWAP3, "swap3" }, + { EVM_INS_SWAP4, "swap4" }, + { EVM_INS_SWAP5, "swap5" }, + { EVM_INS_SWAP6, "swap6" }, + { EVM_INS_SWAP7, "swap7" }, + { EVM_INS_SWAP8, "swap8" }, + { EVM_INS_SWAP9, "swap9" }, + { EVM_INS_SWAP10, "swap10" }, + { EVM_INS_SWAP11, "swap11" }, + { EVM_INS_SWAP12, "swap12" }, + { EVM_INS_SWAP13, "swap13" }, + { EVM_INS_SWAP14, "swap14" }, + { EVM_INS_SWAP15, "swap15" }, + { EVM_INS_SWAP16, "swap16" }, + { EVM_INS_LOG0, "log0" }, + { EVM_INS_LOG1, "log1" }, + { EVM_INS_LOG2, "log2" }, + { EVM_INS_LOG3, "log3" }, + { EVM_INS_LOG4, "log4" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_CREATE, "create" }, + { EVM_INS_CALL, "call" }, + { EVM_INS_CALLCODE, "callcode" }, + { EVM_INS_RETURN, "return" }, + { EVM_INS_DELEGATECALL, "delegatecall" }, + { EVM_INS_CALLBLACKBOX, "callblackbox" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_STATICCALL, "staticcall" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_REVERT, "revert" }, + { EVM_INS_INVALID, NULL }, + { EVM_INS_SUICIDE, "suicide" }, +}; +#endif + +const char *EVM_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= ARR_SIZE(insn_name_maps)) + return NULL; + else + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static name_map group_name_maps[] = { + // generic groups + { EVM_GRP_INVALID, NULL }, + { EVM_GRP_JUMP, "jump" }, + // special groups + { EVM_GRP_MATH, "math" }, + { EVM_GRP_STACK_WRITE, "stack_write" }, + { EVM_GRP_STACK_READ, "stack_read" }, + { EVM_GRP_MEM_WRITE, "mem_write" }, + { EVM_GRP_MEM_READ, "mem_read" }, + { EVM_GRP_STORE_WRITE, "store_write" }, + { EVM_GRP_STORE_READ, "store_read" }, + { EVM_GRP_HALT, "halt" }, +}; +#endif + +const char *EVM_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} +#endif diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMMapping.h b/white_patch_detect/capstone-master/arch/EVM/EVMMapping.h new file mode 100644 index 0000000..576e004 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMMapping.h @@ -0,0 +1,8 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#include + +void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); +const char *EVM_insn_name(csh handle, unsigned int id); +const char *EVM_group_name(csh handle, unsigned int id); diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMMappingInsn.inc b/white_patch_detect/capstone-master/arch/EVM/EVMMappingInsn.inc new file mode 100644 index 0000000..e106cca --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMMappingInsn.inc @@ -0,0 +1,259 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +{ 0, 0, 0 }, // STOP +{ 2, 1, 3 }, // ADD +{ 2, 1, 5 }, // MUL +{ 2, 1, 3 }, // SUB +{ 2, 1, 5 }, // DIV +{ 2, 1, 5 }, // SDIV +{ 2, 1, 5 }, // MOD +{ 2, 1, 5 }, // SMOD +{ 3, 1, 8 }, // ADDMOD +{ 3, 1, 8 }, // MULMOD +{ 2, 1, 10 }, // EXP +{ 2, 1, 5 }, // SIGNEXTEND +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 2, 1, 3 }, // LT +{ 2, 1, 3 }, // GT +{ 2, 1, 3 }, // SLT +{ 2, 1, 3 }, // SGT +{ 2, 1, 3 }, // EQ +{ 1, 1, 3 }, // ISZERO +{ 2, 1, 3 }, // AND +{ 2, 1, 3 }, // OR +{ 2, 1, 3 }, // XOR +{ 1, 1, 3 }, // NOT +{ 2, 1, 3 }, // BYTE +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 2, 1, 30 }, // SHA3 +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 1, 2 }, // ADDRESS +{ 1, 1, 20 }, // BALANCE +{ 0, 1, 2 }, // ORIGIN +{ 0, 1, 2 }, // CALLER +{ 0, 1, 2 }, // CALLVALUE +{ 1, 1, 3 }, // CALLDATALOAD +{ 0, 1, 2 }, // CALLDATASIZE +{ 3, 0, 3 }, // CALLDATACOPY +{ 0, 1, 2 }, // CODESIZE +{ 3, 0, 3 }, // CODECOPY +{ 0, 1, 2 }, // GASPRICE +{ 1, 1, 20 }, // EXTCODESIZE +{ 4, 0, 20 }, // EXTCODECOPY +{ 0, 1, 2 }, // RETURNDATASIZE +{ 3, 0, 3 }, // RETURNDATACOPY +{ 0, 0, 0xffffffff }, // unused +{ 1, 1, 20 }, // BLOCKHASH +{ 0, 1, 2 }, // COINBASE +{ 0, 1, 2 }, // TIMESTAMP +{ 0, 1, 2 }, // NUMBER +{ 0, 1, 2 }, // DIFFICULTY +{ 0, 1, 2 }, // GASLIMIT +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 1, 0, 2 }, // POP +{ 1, 1, 3 }, // MLOAD +{ 2, 0, 3 }, // MSTORE +{ 2, 0, 3 }, // MSTORE8 +{ 1, 1, 50 }, // SLOAD +{ 2, 0, 0 }, // SSTORE +{ 1, 0, 8 }, // JUMP +{ 2, 0, 10 }, // JUMPI +{ 0, 1, 2 }, // GETPC +{ 0, 1, 2 }, // MSIZE +{ 0, 1, 2 }, // GAS +{ 0, 0, 1 }, // JUMPDEST +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 1, 3 }, // PUSH1 +{ 0, 1, 3 }, // PUSH2 +{ 0, 1, 3 }, // PUSH3 +{ 0, 1, 3 }, // PUSH4 +{ 0, 1, 3 }, // PUSH5 +{ 0, 1, 3 }, // PUSH6 +{ 0, 1, 3 }, // PUSH7 +{ 0, 1, 3 }, // PUSH8 +{ 0, 1, 3 }, // PUSH9 +{ 0, 1, 3 }, // PUSH10 +{ 0, 1, 3 }, // PUSH11 +{ 0, 1, 3 }, // PUSH12 +{ 0, 1, 3 }, // PUSH13 +{ 0, 1, 3 }, // PUSH14 +{ 0, 1, 3 }, // PUSH15 +{ 0, 1, 3 }, // PUSH16 +{ 0, 1, 3 }, // PUSH17 +{ 0, 1, 3 }, // PUSH18 +{ 0, 1, 3 }, // PUSH19 +{ 0, 1, 3 }, // PUSH20 +{ 0, 1, 3 }, // PUSH21 +{ 0, 1, 3 }, // PUSH22 +{ 0, 1, 3 }, // PUSH23 +{ 0, 1, 3 }, // PUSH24 +{ 0, 1, 3 }, // PUSH25 +{ 0, 1, 3 }, // PUSH26 +{ 0, 1, 3 }, // PUSH27 +{ 0, 1, 3 }, // PUSH28 +{ 0, 1, 3 }, // PUSH29 +{ 0, 1, 3 }, // PUSH30 +{ 0, 1, 3 }, // PUSH31 +{ 0, 1, 3 }, // PUSH32 +{ 1, 2, 3 }, // DUP1 +{ 2, 3, 3 }, // DUP2 +{ 3, 4, 3 }, // DUP3 +{ 4, 5, 3 }, // DUP4 +{ 5, 6, 3 }, // DUP5 +{ 6, 7, 3 }, // DUP6 +{ 7, 8, 3 }, // DUP7 +{ 8, 9, 3 }, // DUP8 +{ 9, 10, 3 }, // DUP9 +{ 10, 11, 3 }, // DUP10 +{ 11, 12, 3 }, // DUP11 +{ 12, 13, 3 }, // DUP12 +{ 13, 14, 3 }, // DUP13 +{ 14, 15, 3 }, // DUP14 +{ 15, 16, 3 }, // DUP15 +{ 16, 17, 3 }, // DUP16 +{ 2, 2, 3 }, // SWAP1 +{ 3, 3, 3 }, // SWAP2 +{ 4, 4, 3 }, // SWAP3 +{ 5, 5, 3 }, // SWAP4 +{ 6, 6, 3 }, // SWAP5 +{ 7, 7, 3 }, // SWAP6 +{ 8, 8, 3 }, // SWAP7 +{ 9, 9, 3 }, // SWAP8 +{ 10, 10, 3 }, // SWAP9 +{ 11, 11, 3 }, // SWAP10 +{ 12, 12, 3 }, // SWAP11 +{ 13, 13, 3 }, // SWAP12 +{ 14, 14, 3 }, // SWAP13 +{ 15, 15, 3 }, // SWAP14 +{ 16, 16, 3 }, // SWAP15 +{ 17, 17, 3 }, // SWAP16 +{ 2, 0, 375 }, // LOG0 +{ 3, 0, 750 }, // LOG1 +{ 4, 0, 1125 }, // LOG2 +{ 5, 0, 1500 }, // LOG3 +{ 6, 0, 1875 }, // LOG4 +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 3, 1, 32000 }, // CREATE +{ 7, 1, 40 }, // CALL +{ 7, 1, 40 }, // CALLCODE +{ 2, 0, 0 }, // RETURN +{ 6, 1, 40 }, // DELEGATECALL +{ 7, 1, 40 }, // CALLBLACKBOX +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 6, 1, 40 }, // STATICCALL +{ 0, 0, 0xffffffff }, // unused +{ 0, 0, 0xffffffff }, // unused +{ 2, 0, 0 }, // REVERT +{ 0, 0, 0xffffffff }, // unused +{ 1, 0, 0 }, // SUICIDE diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMModule.c b/white_patch_detect/capstone-master/arch/EVM/EVMModule.c new file mode 100644 index 0000000..1ba5677 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMModule.c @@ -0,0 +1,33 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh, 2018 */ + +#ifdef CAPSTONE_HAS_EVM + +#include "../../cs_priv.h" +#include "EVMDisassembler.h" +#include "EVMInstPrinter.h" +#include "EVMMapping.h" +#include "EVMModule.h" + +cs_err EVM_global_init(cs_struct *ud) +{ + // verify if requested mode is valid + if (ud->mode) + return CS_ERR_MODE; + + ud->printer = EVM_printInst; + ud->printer_info = NULL; + ud->insn_id = EVM_get_insn_id; + ud->insn_name = EVM_insn_name; + ud->group_name = EVM_group_name; + ud->disasm = EVM_getInstruction; + + return CS_ERR_OK; +} + +cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/EVM/EVMModule.h b/white_patch_detect/capstone-master/arch/EVM/EVMModule.h new file mode 100644 index 0000000..0bc6d0a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/EVM/EVMModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_EVM_MODULE_H +#define CS_EVM_MODULE_H + +#include "../../utils.h" + +cs_err EVM_global_init(cs_struct *ud); +cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.c b/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.c new file mode 100644 index 0000000..7c191c2 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.c @@ -0,0 +1,2305 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCRegisterInfo.h" +#include "M680XInstPrinter.h" +#include "M680XDisassembler.h" +#include "M680XDisassemblerInternals.h" + +#ifdef CAPSTONE_HAS_M680X + +#ifndef DECL_SPEC +#ifdef _MSC_VER +#define DECL_SPEC __cdecl +#else +#define DECL_SPEC +#endif // _MSC_VER +#endif // DECL_SPEC + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +typedef enum insn_hdlr_id { + illgl_hid, + rel8_hid, + rel16_hid, + imm8_hid, + imm16_hid, + imm32_hid, + dir_hid, + ext_hid, + idxX_hid, + idxY_hid, + idx09_hid, + inh_hid, + rr09_hid, + rbits_hid, + bitmv_hid, + tfm_hid, + opidx_hid, + opidxdr_hid, + idxX0_hid, + idxX16_hid, + imm8rel_hid, + idxS_hid, + idxS16_hid, + idxXp_hid, + idxX0p_hid, + idx12_hid, + idx12s_hid, + rr12_hid, + loop_hid, + index_hid, + imm8i12x_hid, + imm16i12x_hid, + exti12x_hid, + HANDLER_ID_ENDING, +} insn_hdlr_id; + +// Access modes for the first 4 operands. If there are more than +// four operands they use the same access mode as the 4th operand. +// +// u: unchanged +// r: (r)read access +// w: (w)write access +// m: (m)odify access (= read + write) +// +typedef enum e_access_mode { + + uuuu, + rrrr, + wwww, + rwww, + rrrm, + rmmm, + wrrr, + mrrr, + mwww, + mmmm, + mwrr, + mmrr, + wmmm, + rruu, + muuu, + ACCESS_MODE_ENDING, +} e_access_mode; + +// Access type values are compatible with enum cs_ac_type: +typedef enum e_access { + UNCHANGED = CS_AC_INVALID, + READ = CS_AC_READ, + WRITE = CS_AC_WRITE, + MODIFY = (CS_AC_READ | CS_AC_WRITE), +} e_access; + +/* Properties of one instruction in PAGE1 (without prefix) */ +typedef struct inst_page1 { + m680x_insn insn : 9; + insn_hdlr_id handler_id1 : 6; /* first instruction handler id */ + insn_hdlr_id handler_id2 : 6; /* second instruction handler id */ +} inst_page1; + +/* Properties of one instruction in any other PAGE X */ +typedef struct inst_pageX { + unsigned opcode : 8; + m680x_insn insn : 9; + insn_hdlr_id handler_id1 : 6; /* first instruction handler id */ + insn_hdlr_id handler_id2 : 6; /* second instruction handler id */ +} inst_pageX; + +typedef struct insn_props { + unsigned group : 4; + e_access_mode access_mode : 5; + m680x_reg reg0 : 5; + m680x_reg reg1 : 5; + bool cc_modified : 1; + bool update_reg_access : 1; +} insn_props; + +#include "m6800.inc" +#include "m6801.inc" +#include "hd6301.inc" +#include "m6811.inc" +#include "cpu12.inc" +#include "m6805.inc" +#include "m6808.inc" +#include "hcs08.inc" +#include "m6809.inc" +#include "hd6309.inc" + +#include "insn_props.inc" + +////////////////////////////////////////////////////////////////////////////// + +// M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). +// A reader is needed to read a byte or word from a given memory address. +// See also X86 reader(...) +static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address) +{ + if (address - info->offset >= info->size) + // out of code buffer range + return false; + + *byte = info->code[address - info->offset]; + + return true; +} + +static bool read_byte_sign_extended(const m680x_info *info, int16_t *word, + uint16_t address) +{ + if (address - info->offset >= info->size) + // out of code buffer range + return false; + + *word = (int16_t) info->code[address - info->offset]; + + if (*word & 0x80) + *word |= 0xFF00; + + return true; +} + +static bool read_word(const m680x_info *info, uint16_t *word, uint16_t address) +{ + if (address + 1 - info->offset >= info->size) + // out of code buffer range + return false; + + *word = (uint16_t)info->code[address - info->offset] << 8; + *word |= (uint16_t)info->code[address + 1 - info->offset]; + + return true; +} + +static bool read_sdword(const m680x_info *info, int32_t *sdword, + uint16_t address) +{ + if (address + 3 - info->offset >= info->size) + // out of code buffer range + return false; + + *sdword = (uint32_t)info->code[address - info->offset] << 24; + *sdword |= (uint32_t)info->code[address + 1 - info->offset] << 16; + *sdword |= (uint32_t)info->code[address + 2 - info->offset] << 8; + *sdword |= (uint32_t)info->code[address + 3 - info->offset]; + + return true; +} + +// For PAGE2 and PAGE3 opcodes when using an an array of inst_page1 most +// entries have M680X_INS_ILLGL. To avoid wasting memory an inst_pageX is +// used which contains the opcode. Using a binary search for the right opcode +// is much faster (= O(log n) ) in comparison to a linear search ( = O(n) ). +static int binary_search(const inst_pageX *const inst_pageX_table, + int table_size, uint8_t opcode) +{ + int first = 0; + int last = table_size - 1; + int middle = (first + last) / 2; + + while (first <= last) { + if (inst_pageX_table[middle].opcode < opcode) { + first = middle + 1; + } + else if (inst_pageX_table[middle].opcode == opcode) { + return middle; /* item found */ + } + else + last = middle - 1; + + middle = (first + last) / 2; + } + + if (first > last) + return -1; /* item not found */ + + return -2; +} + +void M680X_get_insn_id(cs_struct *handle, cs_insn *insn, unsigned int id) +{ + const m680x_info *const info = (const m680x_info *)handle->printer_info; + const cpu_tables *cpu = info->cpu; + uint8_t insn_prefix = (id >> 8) & 0xff; + int index; + int i; + + insn->id = M680X_INS_ILLGL; + + for (i = 0; i < ARR_SIZE(cpu->pageX_prefix); ++i) { + if (cpu->pageX_table_size[i] == 0 || + (cpu->inst_pageX_table[i] == NULL)) + break; + + if (cpu->pageX_prefix[i] == insn_prefix) { + index = binary_search(cpu->inst_pageX_table[i], + cpu->pageX_table_size[i], id & 0xff); + insn->id = (index >= 0) ? + cpu->inst_pageX_table[i][index].insn : + M680X_INS_ILLGL; + return; + } + } + + if (insn_prefix != 0) + return; + + insn->id = cpu->inst_page1_table[id].insn; + + if (insn->id != M680X_INS_ILLGL) + return; + + // Check if opcode byte is present in an overlay table + for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) { + if (cpu->overlay_table_size[i] == 0 || + (cpu->inst_overlay_table[i] == NULL)) + break; + + if ((index = binary_search(cpu->inst_overlay_table[i], + cpu->overlay_table_size[i], + id & 0xff)) >= 0) { + insn->id = cpu->inst_overlay_table[i][index].insn; + return; + } + } +} + +static void add_insn_group(cs_detail *detail, m680x_group_type group) +{ + if (detail != NULL && + (group != M680X_GRP_INVALID) && (group != M680X_GRP_ENDING)) + detail->groups[detail->groups_count++] = (uint8_t)group; +} + +static bool exists_reg_list(uint16_t *regs, uint8_t count, m680x_reg reg) +{ + uint8_t i; + + for (i = 0; i < count; ++i) { + if (regs[i] == (uint16_t)reg) + return true; + } + + return false; +} + +static void add_reg_to_rw_list(MCInst *MI, m680x_reg reg, e_access access) +{ + cs_detail *detail = MI->flat_insn->detail; + + if (detail == NULL || (reg == M680X_REG_INVALID)) + return; + + switch (access) { + case MODIFY: + if (!exists_reg_list(detail->regs_read, + detail->regs_read_count, reg)) + detail->regs_read[detail->regs_read_count++] = + (uint16_t)reg; + + // intentionally fall through + + case WRITE: + if (!exists_reg_list(detail->regs_write, + detail->regs_write_count, reg)) + detail->regs_write[detail->regs_write_count++] = + (uint16_t)reg; + + break; + + case READ: + if (!exists_reg_list(detail->regs_read, + detail->regs_read_count, reg)) + detail->regs_read[detail->regs_read_count++] = + (uint16_t)reg; + + break; + + case UNCHANGED: + default: + break; + } +} + +static void update_am_reg_list(MCInst *MI, m680x_info *info, cs_m680x_op *op, + e_access access) +{ + if (MI->flat_insn->detail == NULL) + return; + + switch (op->type) { + case M680X_OP_REGISTER: + add_reg_to_rw_list(MI, op->reg, access); + break; + + case M680X_OP_INDEXED: + add_reg_to_rw_list(MI, op->idx.base_reg, READ); + + if (op->idx.base_reg == M680X_REG_X && + info->cpu->reg_byte_size[M680X_REG_H]) + add_reg_to_rw_list(MI, M680X_REG_H, READ); + + + if (op->idx.offset_reg != M680X_REG_INVALID) + add_reg_to_rw_list(MI, op->idx.offset_reg, READ); + + if (op->idx.inc_dec) { + add_reg_to_rw_list(MI, op->idx.base_reg, WRITE); + + if (op->idx.base_reg == M680X_REG_X && + info->cpu->reg_byte_size[M680X_REG_H]) + add_reg_to_rw_list(MI, M680X_REG_H, WRITE); + } + + break; + + default: + break; + } +} + +static const e_access g_access_mode_to_access[4][15] = { + { + UNCHANGED, READ, WRITE, READ, READ, READ, WRITE, MODIFY, + MODIFY, MODIFY, MODIFY, MODIFY, WRITE, READ, MODIFY, + }, + { + UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ, READ, + WRITE, MODIFY, WRITE, MODIFY, MODIFY, READ, UNCHANGED, + }, + { + UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ, READ, + WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED, + }, + { + UNCHANGED, READ, WRITE, WRITE, MODIFY, MODIFY, READ, READ, + WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED, + }, +}; + +static e_access get_access(int operator_index, e_access_mode access_mode) +{ + int idx = (operator_index > 3) ? 3 : operator_index; + + return g_access_mode_to_access[idx][access_mode]; +} + +static void build_regs_read_write_counts(MCInst *MI, m680x_info *info, + e_access_mode access_mode) +{ + cs_m680x *m680x = &info->m680x; + int i; + + if (MI->flat_insn->detail == NULL || (!m680x->op_count)) + return; + + for (i = 0; i < m680x->op_count; ++i) { + + e_access access = get_access(i, access_mode); + update_am_reg_list(MI, info, &m680x->operands[i], access); + } +} + +static void add_operators_access(MCInst *MI, m680x_info *info, + e_access_mode access_mode) +{ + cs_m680x *m680x = &info->m680x; + int offset = 0; + int i; + + if (MI->flat_insn->detail == NULL || (!m680x->op_count) || + (access_mode == uuuu)) + return; + + for (i = 0; i < m680x->op_count; ++i) { + e_access access; + + // Ugly fix: MULD has a register operand, an immediate operand + // AND an implicitly changed register W + if (info->insn == M680X_INS_MULD && (i == 1)) + offset = 1; + + access = get_access(i + offset, access_mode); + m680x->operands[i].access = access; + } +} + +typedef struct insn_to_changed_regs { + m680x_insn insn; + e_access_mode access_mode; + m680x_reg regs[10]; +} insn_to_changed_regs; + +static void set_changed_regs_read_write_counts(MCInst *MI, m680x_info *info) +{ + //TABLE +#define EOL M680X_REG_INVALID + static const insn_to_changed_regs changed_regs[] = { + { M680X_INS_BSR, mmmm, { M680X_REG_S, EOL } }, + { M680X_INS_CALL, mmmm, { M680X_REG_S, EOL } }, + { + M680X_INS_CWAI, mrrr, { + M680X_REG_S, M680X_REG_PC, M680X_REG_U, + M680X_REG_Y, M680X_REG_X, M680X_REG_DP, + M680X_REG_D, M680X_REG_CC, EOL + }, + }, + { M680X_INS_DAA, mrrr, { M680X_REG_A, EOL } }, + { + M680X_INS_DIV, mmrr, { + M680X_REG_A, M680X_REG_H, M680X_REG_X, EOL + } + }, + { + M680X_INS_EDIV, mmrr, { + M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL + } + }, + { + M680X_INS_EDIVS, mmrr, { + M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL + } + }, + { M680X_INS_EMACS, mrrr, { M680X_REG_X, M680X_REG_Y, EOL } }, + { M680X_INS_EMAXM, rrrr, { M680X_REG_D, EOL } }, + { M680X_INS_EMINM, rrrr, { M680X_REG_D, EOL } }, + { M680X_INS_EMUL, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } }, + { M680X_INS_EMULS, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } }, + { M680X_INS_ETBL, wmmm, { M680X_REG_A, M680X_REG_B, EOL } }, + { M680X_INS_FDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, + { M680X_INS_IDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, + { M680X_INS_IDIVS, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, + { M680X_INS_JSR, mmmm, { M680X_REG_S, EOL } }, + { M680X_INS_LBSR, mmmm, { M680X_REG_S, EOL } }, + { M680X_INS_MAXM, rrrr, { M680X_REG_A, EOL } }, + { M680X_INS_MINM, rrrr, { M680X_REG_A, EOL } }, + { + M680X_INS_MEM, mmrr, { + M680X_REG_X, M680X_REG_Y, M680X_REG_A, EOL + } + }, + { M680X_INS_MUL, mmmm, { M680X_REG_A, M680X_REG_B, EOL } }, + { M680X_INS_MULD, mwrr, { M680X_REG_D, M680X_REG_W, EOL } }, + { M680X_INS_PSHA, rmmm, { M680X_REG_A, M680X_REG_S, EOL } }, + { M680X_INS_PSHB, rmmm, { M680X_REG_B, M680X_REG_S, EOL } }, + { M680X_INS_PSHC, rmmm, { M680X_REG_CC, M680X_REG_S, EOL } }, + { M680X_INS_PSHD, rmmm, { M680X_REG_D, M680X_REG_S, EOL } }, + { M680X_INS_PSHH, rmmm, { M680X_REG_H, M680X_REG_S, EOL } }, + { M680X_INS_PSHX, rmmm, { M680X_REG_X, M680X_REG_S, EOL } }, + { M680X_INS_PSHY, rmmm, { M680X_REG_Y, M680X_REG_S, EOL } }, + { M680X_INS_PULA, wmmm, { M680X_REG_A, M680X_REG_S, EOL } }, + { M680X_INS_PULB, wmmm, { M680X_REG_B, M680X_REG_S, EOL } }, + { M680X_INS_PULC, wmmm, { M680X_REG_CC, M680X_REG_S, EOL } }, + { M680X_INS_PULD, wmmm, { M680X_REG_D, M680X_REG_S, EOL } }, + { M680X_INS_PULH, wmmm, { M680X_REG_H, M680X_REG_S, EOL } }, + { M680X_INS_PULX, wmmm, { M680X_REG_X, M680X_REG_S, EOL } }, + { M680X_INS_PULY, wmmm, { M680X_REG_Y, M680X_REG_S, EOL } }, + { + M680X_INS_REV, mmrr, { + M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL + } + }, + { + M680X_INS_REVW, mmmm, { + M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL + } + }, + { M680X_INS_RTC, mwww, { M680X_REG_S, M680X_REG_PC, EOL } }, + { + M680X_INS_RTI, mwww, { + M680X_REG_S, M680X_REG_CC, M680X_REG_B, + M680X_REG_A, M680X_REG_DP, M680X_REG_X, + M680X_REG_Y, M680X_REG_U, M680X_REG_PC, + EOL + }, + }, + { M680X_INS_RTS, mwww, { M680X_REG_S, M680X_REG_PC, EOL } }, + { M680X_INS_SEX, wrrr, { M680X_REG_A, M680X_REG_B, EOL } }, + { M680X_INS_SEXW, rwww, { M680X_REG_W, M680X_REG_D, EOL } }, + { + M680X_INS_SWI, mmrr, { + M680X_REG_S, M680X_REG_PC, M680X_REG_U, + M680X_REG_Y, M680X_REG_X, M680X_REG_DP, + M680X_REG_A, M680X_REG_B, M680X_REG_CC, + EOL + } + }, + { + M680X_INS_SWI2, mmrr, { + M680X_REG_S, M680X_REG_PC, M680X_REG_U, + M680X_REG_Y, M680X_REG_X, M680X_REG_DP, + M680X_REG_A, M680X_REG_B, M680X_REG_CC, + EOL + }, + }, + { + M680X_INS_SWI3, mmrr, { + M680X_REG_S, M680X_REG_PC, M680X_REG_U, + M680X_REG_Y, M680X_REG_X, M680X_REG_DP, + M680X_REG_A, M680X_REG_B, M680X_REG_CC, + EOL + }, + }, + { M680X_INS_TBL, wrrr, { M680X_REG_A, M680X_REG_B, EOL } }, + { + M680X_INS_WAI, mrrr, { + M680X_REG_S, M680X_REG_PC, M680X_REG_X, + M680X_REG_A, M680X_REG_B, M680X_REG_CC, + EOL + } + }, + { + M680X_INS_WAV, rmmm, { + M680X_REG_A, M680X_REG_B, M680X_REG_X, + M680X_REG_Y, EOL + } + }, + { + M680X_INS_WAVR, rmmm, { + M680X_REG_A, M680X_REG_B, M680X_REG_X, + M680X_REG_Y, EOL + } + }, + }; + + int i, j; + + if (MI->flat_insn->detail == NULL) + return; + + for (i = 0; i < ARR_SIZE(changed_regs); ++i) { + if (info->insn == changed_regs[i].insn) { + e_access_mode access_mode = changed_regs[i].access_mode; + + for (j = 0; changed_regs[i].regs[j] != EOL; ++j) { + e_access access; + + m680x_reg reg = changed_regs[i].regs[j]; + + if (!info->cpu->reg_byte_size[reg]) { + if (info->insn != M680X_INS_MUL) + continue; + + // Hack for M68HC05: MUL uses reg. A,X + reg = M680X_REG_X; + } + + access = get_access(j, access_mode); + add_reg_to_rw_list(MI, reg, access); + } + } + } + +#undef EOL +} + +typedef struct insn_desc { + uint32_t opcode; + m680x_insn insn; + insn_hdlr_id hid[2]; + uint16_t insn_size; +} insn_desc; + +static bool is_indexed09_post_byte_valid(const m680x_info *info, + uint16_t *address, uint8_t post_byte, insn_desc *insn_description) +{ + uint8_t ir = 0; + bool retval; + + switch (post_byte & 0x9F) { + case 0x87: + case 0x8A: + case 0x8E: + case 0x8F: + case 0x90: + case 0x92: + case 0x97: + case 0x9A: + case 0x9E: + return false; // illegal indexed post bytes + + case 0x88: // n8,R + case 0x8C: // n8,PCR + case 0x98: // [n8,R] + case 0x9C: // [n8,PCR] + insn_description->insn_size++; + return read_byte(info, &ir, (*address)++); + + case 0x89: // n16,R + case 0x8D: // n16,PCR + case 0x99: // [n16,R] + case 0x9D: // [n16,PCR] + insn_description->insn_size += 2; + retval = read_byte(info, &ir, *address + 1); + *address += 2; + return retval; + + case 0x9F: // [n] + insn_description->insn_size += 2; + retval = (post_byte & 0x60) == 0 && + read_byte(info, &ir, *address + 1); + *address += 2; + return retval; + } + + return true; // Any other indexed post byte is valid and + // no additional bytes have to be read. +} + +static bool is_indexed12_post_byte_valid(const m680x_info *info, + uint16_t *address, uint8_t post_byte, insn_desc *insn_description, + bool is_subset) +{ + uint8_t ir; + bool result; + + if (!(post_byte & 0x20)) // n5,R + return true; + + switch (post_byte & 0xe7) { + case 0xe0: + case 0xe1: // n9,R + if (is_subset) + return false; + + insn_description->insn_size++; + return read_byte(info, &ir, (*address)++); + + case 0xe2: // n16,R + case 0xe3: // [n16,R] + if (is_subset) + return false; + + insn_description->insn_size += 2; + result = read_byte(info, &ir, *address + 1); + *address += 2; + return result; + + case 0xe4: // A,R + case 0xe5: // B,R + case 0xe6: // D,R + case 0xe7: // [D,R] + default: // n,-r n,+r n,r- n,r+ + break; + } + + return true; +} + +// Check for M6809/HD6309 TFR/EXG instruction for valid register +static bool is_tfr09_reg_valid(const m680x_info *info, uint8_t reg_nibble) +{ + if (info->cpu->tfr_reg_valid != NULL) + return info->cpu->tfr_reg_valid[reg_nibble]; + + return true; // e.g. for the M6309 all registers are valid +} + +// Check for CPU12 TFR/EXG instruction for valid register +static bool is_exg_tfr12_post_byte_valid(const m680x_info *info, + uint8_t post_byte) +{ + return !(post_byte & 0x08); +} + +static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble) +{ + // HD6809 TFM instruction: Only register X,Y,U,S,D is allowed + return reg_nibble <= 4; +} + +static bool is_loop_post_byte_valid(const m680x_info *info, uint8_t post_byte) +{ + // According to documentation bit 3 is don't care and not checked here. + if (post_byte >= 0xc0) + return false; + + return ((post_byte & 0x07) != 2 && ((post_byte & 0x07) != 3)); +} + +static bool is_sufficient_code_size(const m680x_info *info, uint16_t address, + insn_desc *insn_description) +{ + int i; + bool retval; + + for (i = 0; i < 2; i++) { + uint8_t ir = 0; + bool is_subset = false; + + switch (insn_description->hid[i]) { + + case imm32_hid: + insn_description->insn_size += 4; + retval = read_byte(info, &ir, address + 3); + address += 4; + break; + + case ext_hid: + case imm16_hid: + case rel16_hid: + case imm8rel_hid: + case opidxdr_hid: + case idxX16_hid: + case idxS16_hid: + insn_description->insn_size += 2; + retval = read_byte(info, &ir, address + 1); + address += 2; + break; + + case rel8_hid: + case dir_hid: + case rbits_hid: + case imm8_hid: + case idxX_hid: + case idxXp_hid: + case idxY_hid: + case idxS_hid: + case index_hid: + insn_description->insn_size += 1; + retval = read_byte(info, &ir, address++); + break; + + case illgl_hid: + case inh_hid: + case idxX0_hid: + case idxX0p_hid: + case opidx_hid: + retval = true; + break; + + case idx09_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else + retval = is_indexed09_post_byte_valid(info, + &address, ir, insn_description); + + break; + + case idx12s_hid: + is_subset = true; + + // intentionally fall through + + case idx12_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else + retval = is_indexed12_post_byte_valid(info, + &address, ir, insn_description, + is_subset); + + break; + + case exti12x_hid: + case imm16i12x_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else if (!is_indexed12_post_byte_valid(info, &address, + ir, insn_description, false)) + retval = false; + else { + insn_description->insn_size += 2; + retval = read_byte(info, &ir, address + 1); + address += 2; + } + + break; + + case imm8i12x_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else if (!is_indexed12_post_byte_valid(info, &address, + ir, insn_description, false)) + retval = false; + else { + insn_description->insn_size += 1; + retval = read_byte(info, &ir, address++); + } + + break; + + case tfm_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else + retval = is_tfm_reg_valid(info, (ir >> 4) & 0x0F) && + is_tfm_reg_valid(info, ir & 0x0F); + + break; + + case rr09_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else + retval = is_tfr09_reg_valid(info, (ir >> 4) & 0x0F) && + is_tfr09_reg_valid(info, ir & 0x0F); + + break; + + case rr12_hid: + insn_description->insn_size += 1; + + if (!read_byte(info, &ir, address++)) + retval = false; + else + retval = is_exg_tfr12_post_byte_valid(info, ir); + + break; + + case bitmv_hid: + insn_description->insn_size += 2; + + if (!read_byte(info, &ir, address++)) + retval = false; + else if ((ir & 0xc0) == 0xc0) + retval = false; // Invalid register specified + else + retval = read_byte(info, &ir, address++); + + break; + + case loop_hid: + insn_description->insn_size += 2; + + if (!read_byte(info, &ir, address++)) + retval = false; + else if (!is_loop_post_byte_valid(info, ir)) + retval = false; + else + retval = read_byte(info, &ir, address++); + + break; + + default: + fprintf(stderr, "Internal error: Unexpected instruction " + "handler id %d\n", insn_description->hid[i]); + retval = false; + break; + } + + if (!retval) + return false; + } + + return retval; +} + +// Check for a valid M680X instruction AND for enough bytes in the code buffer +// Return an instruction description in insn_desc. +static bool decode_insn(const m680x_info *info, uint16_t address, + insn_desc *insn_description) +{ + const inst_pageX *inst_table = NULL; + const cpu_tables *cpu = info->cpu; + int table_size = 0; + uint16_t base_address = address; + uint8_t ir; // instruction register + int i; + int index; + + if (!read_byte(info, &ir, address++)) + return false; + + insn_description->insn = M680X_INS_ILLGL; + insn_description->opcode = ir; + + // Check if a page prefix byte is present + for (i = 0; i < ARR_SIZE(cpu->pageX_table_size); ++i) { + if (cpu->pageX_table_size[i] == 0 || + (cpu->inst_pageX_table[i] == NULL)) + break; + + if ((cpu->pageX_prefix[i] == ir)) { + // Get pageX instruction and handler id. + // Abort for illegal instr. + inst_table = cpu->inst_pageX_table[i]; + table_size = cpu->pageX_table_size[i]; + + if (!read_byte(info, &ir, address++)) + return false; + + insn_description->opcode = + (insn_description->opcode << 8) | ir; + + if ((index = binary_search(inst_table, table_size, ir)) < 0) + return false; + + insn_description->hid[0] = + inst_table[index].handler_id1; + insn_description->hid[1] = + inst_table[index].handler_id2; + insn_description->insn = inst_table[index].insn; + break; + } + } + + if (insn_description->insn == M680X_INS_ILLGL) { + // Get page1 insn description + insn_description->insn = cpu->inst_page1_table[ir].insn; + insn_description->hid[0] = + cpu->inst_page1_table[ir].handler_id1; + insn_description->hid[1] = + cpu->inst_page1_table[ir].handler_id2; + } + + if (insn_description->insn == M680X_INS_ILLGL) { + // Check if opcode byte is present in an overlay table + for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) { + if (cpu->overlay_table_size[i] == 0 || + (cpu->inst_overlay_table[i] == NULL)) + break; + + inst_table = cpu->inst_overlay_table[i]; + table_size = cpu->overlay_table_size[i]; + + if ((index = binary_search(inst_table, table_size, + ir)) >= 0) { + insn_description->hid[0] = + inst_table[index].handler_id1; + insn_description->hid[1] = + inst_table[index].handler_id2; + insn_description->insn = inst_table[index].insn; + break; + } + } + } + + insn_description->insn_size = address - base_address; + + return (insn_description->insn != M680X_INS_ILLGL) && + (insn_description->insn != M680X_INS_INVLD) && + is_sufficient_code_size(info, address, insn_description); +} + +static void illegal_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x_op *op0 = &info->m680x.operands[info->m680x.op_count++]; + uint8_t temp8 = 0; + + info->insn = M680X_INS_ILLGL; + read_byte(info, &temp8, (*address)++); + op0->imm = (int32_t)temp8 & 0xff; + op0->type = M680X_OP_IMMEDIATE; + op0->size = 1; +} + +static void inherent_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + // There is nothing to do here :-) +} + +static void add_reg_operand(m680x_info *info, m680x_reg reg) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_REGISTER; + op->reg = reg; + op->size = info->cpu->reg_byte_size[reg]; +} + +static void set_operand_size(m680x_info *info, cs_m680x_op *op, + uint8_t default_size) +{ + cs_m680x *m680x = &info->m680x; + + if (info->insn == M680X_INS_JMP || info->insn == M680X_INS_JSR) + op->size = 0; + else if (info->insn == M680X_INS_DIVD || + ((info->insn == M680X_INS_AIS || info->insn == M680X_INS_AIX) && + op->type != M680X_OP_REGISTER)) + op->size = 1; + else if (info->insn == M680X_INS_DIVQ || + info->insn == M680X_INS_MOVW) + op->size = 2; + else if (info->insn == M680X_INS_EMACS) + op->size = 4; + else if ((m680x->op_count > 0) && + (m680x->operands[0].type == M680X_OP_REGISTER)) + op->size = m680x->operands[0].size; + else + op->size = default_size; +} + +static const m680x_reg reg_s_reg_ids[] = { + M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP, + M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_PC, +}; + +static const m680x_reg reg_u_reg_ids[] = { + M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP, + M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC, +}; + +static void reg_bits_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x_op *op0 = &info->m680x.operands[0]; + uint8_t reg_bits = 0; + uint16_t bit_index; + const m680x_reg *reg_to_reg_ids; + + read_byte(info, ®_bits, (*address)++); + + switch (op0->reg) { + case M680X_REG_U: + reg_to_reg_ids = ®_u_reg_ids[0]; + break; + + case M680X_REG_S: + reg_to_reg_ids = ®_s_reg_ids[0]; + break; + + default: + fprintf(stderr, "Internal error: Unexpected operand0 register " + "%d\n", op0->reg); + abort(); + } + + if ((info->insn == M680X_INS_PULU || + (info->insn == M680X_INS_PULS)) && + ((reg_bits & 0x80) != 0)) + // PULS xxx,PC or PULU xxx,PC which is like return from + // subroutine (RTS) + add_insn_group(MI->flat_insn->detail, M680X_GRP_RET); + + for (bit_index = 0; bit_index < 8; ++bit_index) { + if (reg_bits & (1 << bit_index)) + add_reg_operand(info, reg_to_reg_ids[bit_index]); + } +} + +static const m680x_reg g_tfr_exg_reg_ids[] = { + /* 16-bit registers */ + M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_U, + M680X_REG_S, M680X_REG_PC, M680X_REG_W, M680X_REG_V, + /* 8-bit registers */ + M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_DP, + M680X_REG_0, M680X_REG_0, M680X_REG_E, M680X_REG_F, +}; + +static void reg_reg09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint8_t regs = 0; + + read_byte(info, ®s, (*address)++); + + add_reg_operand(info, g_tfr_exg_reg_ids[regs >> 4]); + add_reg_operand(info, g_tfr_exg_reg_ids[regs & 0x0f]); + + if ((regs & 0x0f) == 0x05) { + // EXG xxx,PC or TFR xxx,PC which is like a JMP + add_insn_group(MI->flat_insn->detail, M680X_GRP_JUMP); + } +} + + +static void reg_reg12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + static const m680x_reg g_tfr_exg12_reg0_ids[] = { + M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_TMP3, + M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, + }; + static const m680x_reg g_tfr_exg12_reg1_ids[] = { + M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_TMP2, + M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, + }; + uint8_t regs = 0; + + read_byte(info, ®s, (*address)++); + + // The opcode of this instruction depends on + // the msb of its post byte. + if (regs & 0x80) + info->insn = M680X_INS_EXG; + else + info->insn = M680X_INS_TFR; + + add_reg_operand(info, g_tfr_exg12_reg0_ids[(regs >> 4) & 0x07]); + add_reg_operand(info, g_tfr_exg12_reg1_ids[regs & 0x07]); +} + +static void add_rel_operand(m680x_info *info, int16_t offset, uint16_t address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_RELATIVE; + op->size = 0; + op->rel.offset = offset; + op->rel.address = address; +} + +static void relative8_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + int16_t offset = 0; + + read_byte_sign_extended(info, &offset, (*address)++); + add_rel_operand(info, offset, *address + offset); + add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); + + if ((info->insn != M680X_INS_BRA) && + (info->insn != M680X_INS_BSR) && + (info->insn != M680X_INS_BRN)) + add_reg_to_rw_list(MI, M680X_REG_CC, READ); +} + +static void relative16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint16_t offset = 0; + + read_word(info, &offset, *address); + *address += 2; + add_rel_operand(info, (int16_t)offset, *address + offset); + add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); + + if ((info->insn != M680X_INS_LBRA) && + (info->insn != M680X_INS_LBSR) && + (info->insn != M680X_INS_LBRN)) + add_reg_to_rw_list(MI, M680X_REG_CC, READ); +} + +static const m680x_reg g_rr5_to_reg_ids[] = { + M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_S, +}; + +static void add_indexed_operand(m680x_info *info, m680x_reg base_reg, + bool post_inc_dec, uint8_t inc_dec, uint8_t offset_bits, + uint16_t offset, bool no_comma) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_INDEXED; + set_operand_size(info, op, 1); + op->idx.base_reg = base_reg; + op->idx.offset_reg = M680X_REG_INVALID; + op->idx.inc_dec = inc_dec; + + if (inc_dec && post_inc_dec) + op->idx.flags |= M680X_IDX_POST_INC_DEC; + + if (offset_bits != M680X_OFFSET_NONE) { + op->idx.offset = offset; + op->idx.offset_addr = 0; + } + + op->idx.offset_bits = offset_bits; + op->idx.flags |= (no_comma ? M680X_IDX_NO_COMMA : 0); +} + +// M6800/1/2/3 indexed mode handler +static void indexedX_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint8_t offset = 0; + + read_byte(info, &offset, (*address)++); + + add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_8, + (uint16_t)offset, false); +} + +static void indexedY_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint8_t offset = 0; + + read_byte(info, &offset, (*address)++); + + add_indexed_operand(info, M680X_REG_Y, false, 0, M680X_OFFSET_BITS_8, + (uint16_t)offset, false); +} + +// M6809/M6309 indexed mode handler +static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + uint8_t post_byte = 0; + uint16_t offset = 0; + int16_t soffset = 0; + + read_byte(info, &post_byte, (*address)++); + + op->type = M680X_OP_INDEXED; + set_operand_size(info, op, 1); + op->idx.base_reg = g_rr5_to_reg_ids[(post_byte >> 5) & 0x03]; + op->idx.offset_reg = M680X_REG_INVALID; + + if (!(post_byte & 0x80)) { + // n5,R + if ((post_byte & 0x10) == 0x10) + op->idx.offset = post_byte | 0xfff0; + else + op->idx.offset = post_byte & 0x0f; + + op->idx.offset_addr = op->idx.offset + *address; + op->idx.offset_bits = M680X_OFFSET_BITS_5; + } + else { + if ((post_byte & 0x10) == 0x10) + op->idx.flags |= M680X_IDX_INDIRECT; + + // indexed addressing + switch (post_byte & 0x1f) { + case 0x00: // ,R+ + op->idx.inc_dec = 1; + op->idx.flags |= M680X_IDX_POST_INC_DEC; + break; + + case 0x11: // [,R++] + case 0x01: // ,R++ + op->idx.inc_dec = 2; + op->idx.flags |= M680X_IDX_POST_INC_DEC; + break; + + case 0x02: // ,-R + op->idx.inc_dec = -1; + break; + + case 0x13: // [,--R] + case 0x03: // ,--R + op->idx.inc_dec = -2; + break; + + case 0x14: // [,R] + case 0x04: // ,R + break; + + case 0x15: // [B,R] + case 0x05: // B,R + op->idx.offset_reg = M680X_REG_B; + break; + + case 0x16: // [A,R] + case 0x06: // A,R + op->idx.offset_reg = M680X_REG_A; + break; + + case 0x1c: // [n8,PCR] + case 0x0c: // n8,PCR + op->idx.base_reg = M680X_REG_PC; + read_byte_sign_extended(info, &soffset, (*address)++); + op->idx.offset_addr = offset + *address; + op->idx.offset = soffset; + op->idx.offset_bits = M680X_OFFSET_BITS_8; + break; + + case 0x18: // [n8,R] + case 0x08: // n8,R + read_byte_sign_extended(info, &soffset, (*address)++); + op->idx.offset = soffset; + op->idx.offset_bits = M680X_OFFSET_BITS_8; + break; + + case 0x1d: // [n16,PCR] + case 0x0d: // n16,PCR + op->idx.base_reg = M680X_REG_PC; + read_word(info, &offset, *address); + *address += 2; + op->idx.offset_addr = offset + *address; + op->idx.offset = (int16_t)offset; + op->idx.offset_bits = M680X_OFFSET_BITS_16; + break; + + case 0x19: // [n16,R] + case 0x09: // n16,R + read_word(info, &offset, *address); + *address += 2; + op->idx.offset = (int16_t)offset; + op->idx.offset_bits = M680X_OFFSET_BITS_16; + break; + + case 0x1b: // [D,R] + case 0x0b: // D,R + op->idx.offset_reg = M680X_REG_D; + break; + + case 0x1f: // [n16] + op->type = M680X_OP_EXTENDED; + op->ext.indirect = true; + read_word(info, &op->ext.address, *address); + *address += 2; + break; + + default: + op->idx.base_reg = M680X_REG_INVALID; + break; + } + } + + if (((info->insn == M680X_INS_LEAU) || + (info->insn == M680X_INS_LEAS) || + (info->insn == M680X_INS_LEAX) || + (info->insn == M680X_INS_LEAY)) && + (m680x->operands[0].reg == M680X_REG_X || + (m680x->operands[0].reg == M680X_REG_Y))) + // Only LEAX and LEAY modify CC register + add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); +} + + +m680x_reg g_idx12_to_reg_ids[4] = { + M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC, +}; + +m680x_reg g_or12_to_reg_ids[3] = { + M680X_REG_A, M680X_REG_B, M680X_REG_D +}; + +// CPU12 indexed mode handler +static void indexed12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + uint8_t post_byte = 0; + uint8_t offset8 = 0; + + read_byte(info, &post_byte, (*address)++); + + op->type = M680X_OP_INDEXED; + set_operand_size(info, op, 1); + op->idx.offset_reg = M680X_REG_INVALID; + + if (!(post_byte & 0x20)) { + // n5,R n5 is a 5-bit signed offset + op->idx.base_reg = g_idx12_to_reg_ids[(post_byte >> 6) & 0x03]; + + if ((post_byte & 0x10) == 0x10) + op->idx.offset = post_byte | 0xfff0; + else + op->idx.offset = post_byte & 0x0f; + + op->idx.offset_addr = op->idx.offset + *address; + op->idx.offset_bits = M680X_OFFSET_BITS_5; + } + else { + if ((post_byte & 0xe0) == 0xe0) + op->idx.base_reg = + g_idx12_to_reg_ids[(post_byte >> 3) & 0x03]; + + switch (post_byte & 0xe7) { + case 0xe0: + case 0xe1: // n9,R + read_byte(info, &offset8, (*address)++); + op->idx.offset = offset8; + + if (post_byte & 0x01) // sign extension + op->idx.offset |= 0xff00; + + op->idx.offset_bits = M680X_OFFSET_BITS_9; + + if (op->idx.base_reg == M680X_REG_PC) + op->idx.offset_addr = op->idx.offset + *address; + + break; + + case 0xe3: // [n16,R] + op->idx.flags |= M680X_IDX_INDIRECT; + + // intentionally fall through + case 0xe2: // n16,R + read_word(info, (uint16_t *)&op->idx.offset, *address); + (*address) += 2; + op->idx.offset_bits = M680X_OFFSET_BITS_16; + + if (op->idx.base_reg == M680X_REG_PC) + op->idx.offset_addr = op->idx.offset + *address; + + break; + + case 0xe4: // A,R + case 0xe5: // B,R + case 0xe6: // D,R + op->idx.offset_reg = + g_or12_to_reg_ids[post_byte & 0x03]; + break; + + case 0xe7: // [D,R] + op->idx.offset_reg = M680X_REG_D; + op->idx.flags |= M680X_IDX_INDIRECT; + break; + + default: // n,-r n,+r n,r- n,r+ + // PC is not allowed in this mode + op->idx.base_reg = + g_idx12_to_reg_ids[(post_byte >> 6) & 0x03]; + op->idx.inc_dec = post_byte & 0x0f; + + if (op->idx.inc_dec & 0x08) // evtl. sign extend value + op->idx.inc_dec |= 0xf0; + + if (op->idx.inc_dec >= 0) + op->idx.inc_dec++; + + if (post_byte & 0x10) + op->idx.flags |= M680X_IDX_POST_INC_DEC; + + break; + + } + } +} + +static void index_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_CONSTANT; + read_byte(info, &op->const_val, (*address)++); +}; + +static void direct_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_DIRECT; + set_operand_size(info, op, 1); + read_byte(info, &op->direct_addr, (*address)++); +}; + +static void extended_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_EXTENDED; + set_operand_size(info, op, 1); + read_word(info, &op->ext.address, *address); + *address += 2; +} + +static void immediate_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + uint16_t word = 0; + int16_t sword = 0; + + op->type = M680X_OP_IMMEDIATE; + set_operand_size(info, op, 1); + + switch (op->size) { + case 1: + read_byte_sign_extended(info, &sword, *address); + op->imm = sword; + break; + + case 2: + read_word(info, &word, *address); + op->imm = (int16_t)word; + break; + + case 4: + read_sdword(info, &op->imm, *address); + break; + + default: + op->imm = 0; + fprintf(stderr, "Internal error: Unexpected immediate byte " + "size %d.\n", op->size); + } + + *address += op->size; +} + +// handler for bit move instructions, e.g: BAND A,5,1,$40 Used by HD6309 +static void bit_move_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + static const m680x_reg m680x_reg[] = { + M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_INVALID, + }; + + uint8_t post_byte = 0; + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op; + + read_byte(info, &post_byte, *address); + (*address)++; + + // operand[0] = register + add_reg_operand(info, m680x_reg[post_byte >> 6]); + + // operand[1] = bit index in source operand + op = &m680x->operands[m680x->op_count++]; + op->type = M680X_OP_CONSTANT; + op->const_val = (post_byte >> 3) & 0x07; + + // operand[2] = bit index in destination operand + op = &m680x->operands[m680x->op_count++]; + op->type = M680X_OP_CONSTANT; + op->const_val = post_byte & 0x07; + + direct_hdlr(MI, info, address); +} + +// handler for TFM instruction, e.g: TFM X+,Y+ Used by HD6309 +static void tfm_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + static const uint8_t inc_dec_r0[] = { + 1, -1, 1, 0, + }; + static const uint8_t inc_dec_r1[] = { + 1, -1, 0, 1, + }; + uint8_t regs = 0; + uint8_t index = (MI->Opcode & 0xff) - 0x38; + + read_byte(info, ®s, *address); + + add_indexed_operand(info, g_tfr_exg_reg_ids[regs >> 4], true, + inc_dec_r0[index], M680X_OFFSET_NONE, 0, true); + add_indexed_operand(info, g_tfr_exg_reg_ids[regs & 0x0f], true, + inc_dec_r1[index], M680X_OFFSET_NONE, 0, true); + + add_reg_to_rw_list(MI, M680X_REG_W, READ | WRITE); +} + +static void opidx_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + // bit index is coded in Opcode + op->type = M680X_OP_CONSTANT; + op->const_val = (MI->Opcode & 0x0e) >> 1; +} + +// handler for bit test and branch instruction. Used by M6805. +// The bit index is part of the opcode. +// Example: BRSET 3,<$40,LOOP +static void opidx_dir_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + // bit index is coded in Opcode + op->type = M680X_OP_CONSTANT; + op->const_val = (MI->Opcode & 0x0e) >> 1; + direct_hdlr(MI, info, address); + relative8_hdlr(MI, info, address); + + add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); +} + +static void indexedX0_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_NONE, + 0, false); +} + +static void indexedX16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint16_t offset = 0; + + read_word(info, &offset, *address); + *address += 2; + add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_16, + offset, false); +} + +static void imm_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + immediate_hdlr(MI, info, address); + relative8_hdlr(MI, info, address); +} + +static void indexedS_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint8_t offset = 0; + + read_byte(info, &offset, (*address)++); + + add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_8, + (uint16_t)offset, false); +} + +static void indexedS16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint16_t offset = 0; + + read_word(info, &offset, *address); + address += 2; + + add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_16, + offset, false); +} + +static void indexedX0p_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_NONE, + 0, true); +} + +static void indexedXp_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + uint8_t offset = 0; + + read_byte(info, &offset, (*address)++); + + add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_BITS_8, + (uint16_t)offset, false); +} + +static void imm_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op = &m680x->operands[m680x->op_count++]; + + indexed12_hdlr(MI, info, address); + op->type = M680X_OP_IMMEDIATE; + + if (info->insn == M680X_INS_MOVW) { + uint16_t imm16 = 0; + + read_word(info, &imm16, *address); + op->imm = (int16_t)imm16; + op->size = 2; + } + else { + uint8_t imm8 = 0; + + read_byte(info, &imm8, *address); + op->imm = (int8_t)imm8; + op->size = 1; + } + + set_operand_size(info, op, 1); +} + +static void ext_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + cs_m680x *m680x = &info->m680x; + cs_m680x_op *op0 = &m680x->operands[m680x->op_count++]; + uint16_t imm16 = 0; + + indexed12_hdlr(MI, info, address); + read_word(info, &imm16, *address); + op0->type = M680X_OP_EXTENDED; + op0->ext.address = (int16_t)imm16; + set_operand_size(info, op0, 1); +} + +// handler for CPU12 DBEQ/DNBE/IBEQ/IBNE/TBEQ/TBNE instructions. +// Example: DBNE X,$1000 +static void loop_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) +{ + static const m680x_reg index_to_reg_id[] = { + M680X_REG_A, M680X_REG_B, M680X_REG_INVALID, M680X_REG_INVALID, + M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, + }; + static const m680x_insn index_to_insn_id[] = { + M680X_INS_DBEQ, M680X_INS_DBNE, M680X_INS_TBEQ, M680X_INS_TBNE, + M680X_INS_IBEQ, M680X_INS_IBNE, M680X_INS_ILLGL, M680X_INS_ILLGL + }; + cs_m680x *m680x = &info->m680x; + uint8_t post_byte = 0; + uint8_t rel = 0; + cs_m680x_op *op; + + read_byte(info, &post_byte, (*address)++); + + info->insn = index_to_insn_id[(post_byte >> 5) & 0x07]; + + if (info->insn == M680X_INS_ILLGL) { + fprintf(stderr, "Internal error: Unexpected post byte " + "in loop instruction %02X.\n", post_byte); + illegal_hdlr(MI, info, address); + }; + + read_byte(info, &rel, (*address)++); + + add_reg_operand(info, index_to_reg_id[post_byte & 0x07]); + + op = &m680x->operands[m680x->op_count++]; + + op->type = M680X_OP_RELATIVE; + + op->rel.offset = (post_byte & 0x10) ? 0xff00 | rel : rel; + + op->rel.address = *address + op->rel.offset; + + add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); +} + +static void (*const g_insn_handler[])(MCInst *, m680x_info *, uint16_t *) = { + illegal_hdlr, + relative8_hdlr, + relative16_hdlr, + immediate_hdlr, // 8-bit + immediate_hdlr, // 16-bit + immediate_hdlr, // 32-bit + direct_hdlr, + extended_hdlr, + indexedX_hdlr, + indexedY_hdlr, + indexed09_hdlr, + inherent_hdlr, + reg_reg09_hdlr, + reg_bits_hdlr, + bit_move_hdlr, + tfm_hdlr, + opidx_hdlr, + opidx_dir_rel_hdlr, + indexedX0_hdlr, + indexedX16_hdlr, + imm_rel_hdlr, + indexedS_hdlr, + indexedS16_hdlr, + indexedXp_hdlr, + indexedX0p_hdlr, + indexed12_hdlr, + indexed12_hdlr, // subset of indexed12 + reg_reg12_hdlr, + loop_hdlr, + index_hdlr, + imm_idx12_x_hdlr, + imm_idx12_x_hdlr, + ext_idx12_x_hdlr, +}; /* handler function pointers */ + +/* Disasemble one instruction at address and store in str_buff */ +static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info, + uint16_t address) +{ + cs_m680x *m680x = &info->m680x; + cs_detail *detail = MI->flat_insn->detail; + uint16_t base_address = address; + insn_desc insn_description; + e_access_mode access_mode; + + if (detail != NULL) { + memset(detail, 0, offsetof(cs_detail, m680x)+sizeof(cs_m680x)); + } + + memset(&insn_description, 0, sizeof(insn_description)); + memset(m680x, 0, sizeof(*m680x)); + info->insn_size = 1; + + if (decode_insn(info, address, &insn_description)) { + m680x_reg reg; + + if (insn_description.opcode > 0xff) + address += 2; // 8-bit opcode + page prefix + else + address++; // 8-bit opcode only + + info->insn = insn_description.insn; + + MCInst_setOpcode(MI, insn_description.opcode); + + reg = g_insn_props[info->insn].reg0; + + if (reg != M680X_REG_INVALID) { + if (reg == M680X_REG_HX && + (!info->cpu->reg_byte_size[reg])) + reg = M680X_REG_X; + + add_reg_operand(info, reg); + // First (or second) operand is a register which is + // part of the mnemonic + m680x->flags |= M680X_FIRST_OP_IN_MNEM; + reg = g_insn_props[info->insn].reg1; + + if (reg != M680X_REG_INVALID) { + if (reg == M680X_REG_HX && + (!info->cpu->reg_byte_size[reg])) + reg = M680X_REG_X; + + add_reg_operand(info, reg); + m680x->flags |= M680X_SECOND_OP_IN_MNEM; + } + } + + // Call addressing mode specific instruction handler + (g_insn_handler[insn_description.hid[0]])(MI, info, + &address); + (g_insn_handler[insn_description.hid[1]])(MI, info, + &address); + + add_insn_group(detail, g_insn_props[info->insn].group); + + if (g_insn_props[info->insn].cc_modified && + (info->cpu->insn_cc_not_modified[0] != info->insn) && + (info->cpu->insn_cc_not_modified[1] != info->insn)) + add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); + + access_mode = g_insn_props[info->insn].access_mode; + + // Fix for M6805 BSET/BCLR. It has a differnt operand order + // in comparison to the M6811 + if ((info->cpu->insn_cc_not_modified[0] == info->insn) || + (info->cpu->insn_cc_not_modified[1] == info->insn)) + access_mode = rmmm; + + build_regs_read_write_counts(MI, info, access_mode); + add_operators_access(MI, info, access_mode); + + if (g_insn_props[info->insn].update_reg_access) + set_changed_regs_read_write_counts(MI, info); + + info->insn_size = insn_description.insn_size; + + return info->insn_size; + } + else + MCInst_setOpcode(MI, insn_description.opcode); + + // Illegal instruction + address = base_address; + illegal_hdlr(MI, info, &address); + return 1; +} + +// Tables to get the byte size of a register on the CPU +// based on an enum m680x_reg value. +// Invalid registers return 0. +static const uint8_t g_m6800_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_m6805_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_m6808_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 1, 1, 0, 2, 0, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_m6801_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_m6811_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_cpu12_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 2, 2 +}; + +static const uint8_t g_m6809_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 2, 2, 2, 2, 0, 0, 2, 0, 0 +}; + +static const uint8_t g_hd6309_reg_byte_size[22] = { + // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 + 0, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 0, 0, 2, 2, 2, 2, 2, 4, 2, 0, 0 +}; + +// Table to check for a valid register nibble on the M6809 CPU +// used for TFR and EXG instruction. +static const bool m6809_tfr_reg_valid[16] = { + true, true, true, true, true, true, false, false, + true, true, true, true, false, false, false, false, +}; + +static const cpu_tables g_cpu_tables[] = { + { + // M680X_CPU_TYPE_INVALID + NULL, + { NULL, NULL }, + { 0, 0 }, + { 0x00, 0x00, 0x00 }, + { NULL, NULL, NULL }, + { 0, 0, 0 }, + NULL, + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6301 + &g_m6800_inst_page1_table[0], + { &g_m6801_inst_overlay_table[0], &g_hd6301_inst_overlay_table[0] }, + { + ARR_SIZE(g_m6801_inst_overlay_table), + ARR_SIZE(g_hd6301_inst_overlay_table) + }, + { 0x00, 0x00, 0x00 }, + { NULL, NULL, NULL }, + { 0, 0, 0 }, + &g_m6801_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6309 + &g_m6809_inst_page1_table[0], + { &g_hd6309_inst_overlay_table[0], NULL }, + { ARR_SIZE(g_hd6309_inst_overlay_table), 0 }, + { 0x10, 0x11, 0x00 }, + { &g_hd6309_inst_page2_table[0], &g_hd6309_inst_page3_table[0], NULL }, + { + ARR_SIZE(g_hd6309_inst_page2_table), + ARR_SIZE(g_hd6309_inst_page3_table), + 0 + }, + &g_hd6309_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6800 + &g_m6800_inst_page1_table[0], + { NULL, NULL }, + { 0, 0 }, + { 0x00, 0x00, 0x00 }, + { NULL, NULL, NULL }, + { 0, 0, 0 }, + &g_m6800_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6801 + &g_m6800_inst_page1_table[0], + { &g_m6801_inst_overlay_table[0], NULL }, + { ARR_SIZE(g_m6801_inst_overlay_table), 0 }, + { 0x00, 0x00, 0x00 }, + { NULL, NULL, NULL }, + { 0, 0, 0 }, + &g_m6801_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6805 + &g_m6805_inst_page1_table[0], + { NULL, NULL }, + { 0, 0 }, + { 0x00, 0x00, 0x00 }, + { NULL, NULL, NULL }, + { 0, 0, 0 }, + &g_m6805_reg_byte_size[0], + NULL, + { M680X_INS_BCLR, M680X_INS_BSET } + }, + { + // M680X_CPU_TYPE_6808 + &g_m6805_inst_page1_table[0], + { &g_m6808_inst_overlay_table[0], NULL }, + { ARR_SIZE(g_m6808_inst_overlay_table), 0 }, + { 0x9E, 0x00, 0x00 }, + { &g_m6808_inst_page2_table[0], NULL, NULL }, + { ARR_SIZE(g_m6808_inst_page2_table), 0, 0 }, + &g_m6808_reg_byte_size[0], + NULL, + { M680X_INS_BCLR, M680X_INS_BSET } + }, + { + // M680X_CPU_TYPE_6809 + &g_m6809_inst_page1_table[0], + { NULL, NULL }, + { 0, 0 }, + { 0x10, 0x11, 0x00 }, + { + &g_m6809_inst_page2_table[0], + &g_m6809_inst_page3_table[0], + NULL + }, + { + ARR_SIZE(g_m6809_inst_page2_table), + ARR_SIZE(g_m6809_inst_page3_table), + 0 + }, + &g_m6809_reg_byte_size[0], + &m6809_tfr_reg_valid[0], + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_6811 + &g_m6800_inst_page1_table[0], + { + &g_m6801_inst_overlay_table[0], + &g_m6811_inst_overlay_table[0] + }, + { + ARR_SIZE(g_m6801_inst_overlay_table), + ARR_SIZE(g_m6811_inst_overlay_table) + }, + { 0x18, 0x1A, 0xCD }, + { + &g_m6811_inst_page2_table[0], + &g_m6811_inst_page3_table[0], + &g_m6811_inst_page4_table[0] + }, + { + ARR_SIZE(g_m6811_inst_page2_table), + ARR_SIZE(g_m6811_inst_page3_table), + ARR_SIZE(g_m6811_inst_page4_table) + }, + &g_m6811_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_CPU12 + &g_cpu12_inst_page1_table[0], + { NULL, NULL }, + { 0, 0 }, + { 0x18, 0x00, 0x00 }, + { &g_cpu12_inst_page2_table[0], NULL, NULL }, + { ARR_SIZE(g_cpu12_inst_page2_table), 0, 0 }, + &g_cpu12_reg_byte_size[0], + NULL, + { M680X_INS_INVLD, M680X_INS_INVLD } + }, + { + // M680X_CPU_TYPE_HCS08 + &g_m6805_inst_page1_table[0], + { + &g_m6808_inst_overlay_table[0], + &g_hcs08_inst_overlay_table[0] + }, + { + ARR_SIZE(g_m6808_inst_overlay_table), + ARR_SIZE(g_hcs08_inst_overlay_table) + }, + { 0x9E, 0x00, 0x00 }, + { &g_hcs08_inst_page2_table[0], NULL, NULL }, + { ARR_SIZE(g_hcs08_inst_page2_table), 0, 0 }, + &g_m6808_reg_byte_size[0], + NULL, + { M680X_INS_BCLR, M680X_INS_BSET } + }, +}; + +static const char *s_cpu_type[] = { + "INVALID", "6301", "6309", "6800", "6801", "6805", "6808", + "6809", "6811", "CPU12", "HCS08", +}; + +static bool m680x_setup_internals(m680x_info *info, e_cpu_type cpu_type, + uint16_t address, + const uint8_t *code, uint16_t code_len) +{ + if (cpu_type == M680X_CPU_TYPE_INVALID) { + fprintf(stderr, "M680X_CPU_TYPE_%s is not suppported\n", + s_cpu_type[cpu_type]); + return false; + } + + info->code = code; + info->size = code_len; + info->offset = address; + info->cpu_type = cpu_type; + + info->cpu = &g_cpu_tables[info->cpu_type]; + + return true; +} + +bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) +{ + unsigned int insn_size = 0; + e_cpu_type cpu_type = M680X_CPU_TYPE_INVALID; // No default CPU type + cs_struct *handle = (cs_struct *)ud; + m680x_info *info = (m680x_info *)handle->printer_info; + + MCInst_clear(MI); + + if (handle->mode & CS_MODE_M680X_6800) + cpu_type = M680X_CPU_TYPE_6800; + + else if (handle->mode & CS_MODE_M680X_6801) + cpu_type = M680X_CPU_TYPE_6801; + + else if (handle->mode & CS_MODE_M680X_6805) + cpu_type = M680X_CPU_TYPE_6805; + + else if (handle->mode & CS_MODE_M680X_6808) + cpu_type = M680X_CPU_TYPE_6808; + + else if (handle->mode & CS_MODE_M680X_HCS08) + cpu_type = M680X_CPU_TYPE_HCS08; + + else if (handle->mode & CS_MODE_M680X_6809) + cpu_type = M680X_CPU_TYPE_6809; + + else if (handle->mode & CS_MODE_M680X_6301) + cpu_type = M680X_CPU_TYPE_6301; + + else if (handle->mode & CS_MODE_M680X_6309) + cpu_type = M680X_CPU_TYPE_6309; + + else if (handle->mode & CS_MODE_M680X_6811) + cpu_type = M680X_CPU_TYPE_6811; + + else if (handle->mode & CS_MODE_M680X_CPU12) + cpu_type = M680X_CPU_TYPE_CPU12; + + if (cpu_type != M680X_CPU_TYPE_INVALID && + m680x_setup_internals(info, cpu_type, (uint16_t)address, code, + code_len)) + insn_size = m680x_disassemble(MI, info, (uint16_t)address); + + if (insn_size == 0) { + *size = 1; + return false; + } + + // Make sure we always stay within range + if (insn_size > code_len) { + *size = (uint16_t)code_len; + return false; + } + else + *size = (uint16_t)insn_size; + + return true; +} + +cs_err M680X_disassembler_init(cs_struct *ud) +{ + if (M680X_REG_ENDING != ARR_SIZE(g_m6800_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6800_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_m6801_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6801_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_m6805_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6805_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_m6808_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6808_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_m6811_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6811_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_cpu12_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_cpu12_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_REG_ENDING != ARR_SIZE(g_m6809_reg_byte_size)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and g_m6809_reg_byte_size\n"); + + return CS_ERR_MODE; + } + + if (M680X_INS_ENDING != ARR_SIZE(g_insn_props)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_insn and g_insn_props\n"); + + return CS_ERR_MODE; + } + + if (M680X_CPU_TYPE_ENDING != ARR_SIZE(s_cpu_type)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "e_cpu_type and s_cpu_type\n"); + + return CS_ERR_MODE; + } + + if (M680X_CPU_TYPE_ENDING != ARR_SIZE(g_cpu_tables)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "e_cpu_type and g_cpu_tables\n"); + + return CS_ERR_MODE; + } + + if (HANDLER_ID_ENDING != ARR_SIZE(g_insn_handler)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "insn_hdlr_id and g_insn_handler\n"); + + return CS_ERR_MODE; + } + + if (ACCESS_MODE_ENDING != MATRIX_SIZE(g_access_mode_to_access)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "e_access_mode and g_access_mode_to_access\n"); + + return CS_ERR_MODE; + } + + return CS_ERR_OK; +} + +#ifndef CAPSTONE_DIET +void M680X_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + if (insn->detail == NULL) { + *regs_read_count = 0; + *regs_write_count = 0; + } + else { + *regs_read_count = insn->detail->regs_read_count; + *regs_write_count = insn->detail->regs_write_count; + + memcpy(regs_read, insn->detail->regs_read, + *regs_read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + *regs_write_count * + sizeof(insn->detail->regs_write[0])); + } +} +#endif + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.h b/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.h new file mode 100644 index 0000000..d85a3cc --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XDisassembler.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifndef CS_M680XDISASSEMBLER_H +#define CS_M680XDISASSEMBLER_H + +#include "../../MCInst.h" + +bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); +void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); +void M680X_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XDisassemblerInternals.h b/white_patch_detect/capstone-master/arch/M680X/M680XDisassemblerInternals.h new file mode 100644 index 0000000..2f59c3f --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XDisassemblerInternals.h @@ -0,0 +1,57 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifndef CS_M680XDISASSEMBLERINTERNALS_H +#define CS_M680XDISASSEMBLERINTERNALS_H + +#include "../../MCInst.h" +#include "../../include/capstone/m680x.h" + +typedef enum e_cpu_type { + M680X_CPU_TYPE_INVALID, + M680X_CPU_TYPE_6301, // M680X Hitachi HD6301,HD6303 mode + M680X_CPU_TYPE_6309, // M680X Hitachi HD6309 mode + M680X_CPU_TYPE_6800, // M680X Motorola 6800,6802 mode + M680X_CPU_TYPE_6801, // M680X Motorola 6801,6803 mode + M680X_CPU_TYPE_6805, // M680X Motorola/Freescale M68HC05 mode + M680X_CPU_TYPE_6808, // M680X Motorola/Freescale M68HC08 mode + M680X_CPU_TYPE_6809, // M680X Motorola 6809 mode + M680X_CPU_TYPE_6811, // M680X Motorola/Freescale M68HC11 mode + M680X_CPU_TYPE_CPU12, // M680X Motorola/Freescale CPU12 mode + // used on M68HC12/HCS12 + M680X_CPU_TYPE_HCS08, // M680X Freescale HCS08 mode + M680X_CPU_TYPE_ENDING, +} e_cpu_type; + +struct inst_page1; +struct inst_pageX; + +typedef struct { + const struct inst_page1 *inst_page1_table; + const struct inst_pageX *inst_overlay_table[2]; + size_t overlay_table_size[2]; + uint8_t pageX_prefix[3]; + const struct inst_pageX *inst_pageX_table[3]; + size_t pageX_table_size[3]; + const uint8_t *reg_byte_size; + const bool *tfr_reg_valid; + m680x_insn insn_cc_not_modified[2]; +} cpu_tables; + +/* Private, For internal use only */ +typedef struct m680x_info { + const uint8_t *code; // code buffer + uint32_t size; // byte size of code + uint16_t offset; // address offset of first byte in code buffer + e_cpu_type cpu_type; // The CPU type to be used for disassembling + cs_m680x m680x; // M680X specific properties + const cpu_tables *cpu; + m680x_insn insn; // Instruction ID + uint8_t insn_size; // byte size of instruction +} m680x_info; + +extern cs_err M680X_disassembler_init(cs_struct *ud); +extern cs_err M680X_instprinter_init(cs_struct *ud); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.c b/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.c new file mode 100644 index 0000000..3c3356b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.c @@ -0,0 +1,365 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifdef CAPSTONE_HAS_M680X +#include +#include +#include +#include + +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../utils.h" +#include "M680XInstPrinter.h" +#include "M680XDisassembler.h" +#include "M680XDisassemblerInternals.h" + +#ifndef CAPSTONE_DIET +static const char s_reg_names[][10] = { + "", "a", "b", "e", "f", "0", "d", "w", "cc", "dp", "md", + "hx", "h", "x", "y", "s", "u", "v", "q", "pc", "tmp2", "tmp3", +}; + +static const char s_instruction_names[][6] = { + "invld", "aba", "abx", "aby", "adc", "adca", "adcb", "adcd", "adcr", + "add", "adda", "addb", "addd", "adde", "addf", "addr", "addw", + "aim", "ais", "aix", "and", "anda", "andb", "andcc", "andd", "andr", + "asl", "asla", "aslb", "asld", + "asr", "asra", "asrb", "asrd", "asrx", + "band", + "bcc", "bclr", "bcs", "beor", "beq", "bge", "bgnd", "bgt", "bhcc", + "bhcs", "bhi", + "biand", "bieor", "bih", "bil", + "bior", "bit", "bita", "bitb", "bitd", "bitmd", "ble", "bls", "blt", + "bmc", + "bmi", "bms", + "bne", "bor", "bpl", "brclr", "brset", "bra", "brn", "bset", "bsr", + "bvc", "bvs", + "call", "cba", "cbeq", "cbeqa", "cbeqx", "clc", "cli", + "clr", "clra", "clrb", "clrd", "clre", "clrf", "clrh", "clrw", "clrx", + "clv", "cmp", + "cmpa", "cmpb", "cmpd", "cmpe", "cmpf", "cmpr", "cmps", "cmpu", "cmpw", + "cmpx", "cmpy", + "com", "coma", "comb", "comd", "come", "comf", "comw", "comx", "cpd", + "cphx", "cps", "cpx", "cpy", + "cwai", "daa", "dbeq", "dbne", "dbnz", "dbnza", "dbnzx", + "dec", "deca", "decb", "decd", "dece", "decf", "decw", + "decx", "des", "dex", "dey", + "div", "divd", "divq", "ediv", "edivs", "eim", "emacs", "emaxd", + "emaxm", "emind", "eminm", "emul", "emuls", + "eor", "eora", "eorb", "eord", "eorr", "etbl", + "exg", "fdiv", "ibeq", "ibne", "idiv", "idivs", "illgl", + "inc", "inca", "incb", "incd", "ince", "incf", "incw", "incx", + "ins", "inx", "iny", + "jmp", "jsr", + "lbcc", "lbcs", "lbeq", "lbge", "lbgt", "lbhi", "lble", "lbls", "lblt", + "lbmi", "lbne", "lbpl", "lbra", "lbrn", "lbsr", "lbvc", "lbvs", + "lda", "ldaa", "ldab", "ldb", "ldbt", "ldd", "lde", "ldf", "ldhx", + "ldmd", + "ldq", "lds", "ldu", "ldw", "ldx", "ldy", + "leas", "leau", "leax", "leay", + "lsl", "lsla", "lslb", "lsld", "lslx", + "lsr", "lsra", "lsrb", "lsrd", "lsrw", "lsrx", + "maxa", "maxm", "mem", "mina", "minm", "mov", "movb", "movw", "mul", + "muld", + "neg", "nega", "negb", "negd", "negx", + "nop", "nsa", "oim", "ora", "oraa", "orab", "orb", "orcc", "ord", "orr", + "psha", "pshb", "pshc", "pshd", "pshh", "pshs", "pshsw", "pshu", + "pshuw", "pshx", "pshy", + "pula", "pulb", "pulc", "puld", "pulh", "puls", "pulsw", "pulu", + "puluw", "pulx", "puly", "rev", "revw", + "rol", "rola", "rolb", "rold", "rolw", "rolx", + "ror", "rora", "rorb", "rord", "rorw", "rorx", + "rsp", "rtc", "rti", "rts", "sba", "sbc", "sbca", "sbcb", "sbcd", + "sbcr", + "sec", "sei", "sev", "sex", "sexw", "slp", "sta", "staa", "stab", "stb", + "stbt", "std", "ste", "stf", "stop", "sthx", + "stq", "sts", "stu", "stw", "stx", "sty", + "sub", "suba", "subb", "subd", "sube", "subf", "subr", "subw", + "swi", "swi2", "swi3", + "sync", "tab", "tap", "tax", "tba", "tbeq", "tbl", "tbne", "test", + "tfm", "tfr", + "tim", "tpa", + "tst", "tsta", "tstb", "tstd", "tste", "tstf", "tstw", "tstx", + "tsx", "tsy", "txa", "txs", "tys", "wai", "wait", "wav", "wavr", + "xgdx", "xgdy", +}; + +static name_map s_group_names[] = { + { M680X_GRP_INVALID, "" }, + { M680X_GRP_JUMP, "jump" }, + { M680X_GRP_CALL, "call" }, + { M680X_GRP_RET, "return" }, + { M680X_GRP_INT, "interrupt" }, + { M680X_GRP_IRET, "interrupt_return" }, + { M680X_GRP_PRIV, "privileged" }, + { M680X_GRP_BRAREL, "branch_relative" }, +}; +#endif + +static void printRegName(cs_struct *handle, SStream *OS, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + SStream_concat(OS, handle->reg_name((csh)handle, reg)); +#endif +} + +static void printInstructionName(cs_struct *handle, SStream *OS, + unsigned int insn) +{ +#ifndef CAPSTONE_DIET + SStream_concat(OS, handle->insn_name((csh)handle, insn)); +#endif +} + +static uint32_t get_unsigned(int32_t value, int byte_size) +{ + switch (byte_size) { + case 1: + return (uint32_t)(value & 0xff); + + case 2: + return (uint32_t)(value & 0xffff); + + default: + case 4: + return (uint32_t)value; + } +} + +static void printIncDec(bool isPost, SStream *O, m680x_info *info, + cs_m680x_op *op) +{ + static const char s_inc_dec[][3] = { "--", "-", "", "+", "++" }; + + if (!op->idx.inc_dec) + return; + + if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) || + (isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) { + const char *prePostfix = ""; + + if (info->cpu_type == M680X_CPU_TYPE_CPU12) + prePostfix = (op->idx.inc_dec < 0) ? "-" : "+"; + else if (op->idx.inc_dec >= -2 && (op->idx.inc_dec <= 2)) { + prePostfix = (char *)s_inc_dec[op->idx.inc_dec + 2]; + } + + SStream_concat(O, prePostfix); + } +} + +static void printOperand(MCInst *MI, SStream *O, m680x_info *info, + cs_m680x_op *op) +{ + switch (op->type) { + case M680X_OP_REGISTER: + printRegName(MI->csh, O, op->reg); + break; + + case M680X_OP_CONSTANT: + SStream_concat(O, "%u", op->const_val); + break; + + case M680X_OP_IMMEDIATE: + if (MI->csh->imm_unsigned) + SStream_concat(O, "#%u", + get_unsigned(op->imm, op->size)); + else + SStream_concat(O, "#%d", op->imm); + + break; + + case M680X_OP_INDEXED: + if (op->idx.flags & M680X_IDX_INDIRECT) + SStream_concat(O, "["); + + if (op->idx.offset_reg != M680X_REG_INVALID) + printRegName(MI->csh, O, op->idx.offset_reg); + else if (op->idx.offset_bits > 0) { + if (op->idx.base_reg == M680X_REG_PC) + SStream_concat(O, "$%04X", op->idx.offset_addr); + else + SStream_concat(O, "%d", op->idx.offset); + } + else if (op->idx.inc_dec != 0 && + info->cpu_type == M680X_CPU_TYPE_CPU12) + SStream_concat(O, "%d", abs(op->idx.inc_dec)); + + if (!(op->idx.flags & M680X_IDX_NO_COMMA)) + SStream_concat(O, ","); + + printIncDec(false, O, info, op); + + printRegName(MI->csh, O, op->idx.base_reg); + + if (op->idx.base_reg == M680X_REG_PC && + (op->idx.offset_bits > 0)) + SStream_concat(O, "R"); + + printIncDec(true, O, info, op); + + if (op->idx.flags & M680X_IDX_INDIRECT) + SStream_concat(O, "]"); + + break; + + case M680X_OP_RELATIVE: + SStream_concat(O, "$%04X", op->rel.address); + break; + + case M680X_OP_DIRECT: + SStream_concat(O, "$%02X", op->direct_addr); + break; + + case M680X_OP_EXTENDED: + if (op->ext.indirect) + SStream_concat(O, "[$%04X]", op->ext.address); + else { + if (op->ext.address < 256) { + SStream_concat(O, ">$%04X", op->ext.address); + } + else { + SStream_concat(O, "$%04X", op->ext.address); + } + } + + break; + + default: + SStream_concat(O, ""); + break; + } +} + +static const char *getDelimiter(m680x_info *info, cs_m680x *m680x) +{ + bool indexed = false; + int count = 0; + int i; + + if (info->insn == M680X_INS_TFM) + return ","; + + if (m680x->op_count > 1) { + for (i = 0; i < m680x->op_count; ++i) { + if (m680x->operands[i].type == M680X_OP_INDEXED) + indexed = true; + + if (m680x->operands[i].type != M680X_OP_REGISTER) + count++; + } + } + + return (indexed && (count >= 1)) ? ";" : ","; +}; + +void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo) +{ + m680x_info *info = (m680x_info *)PrinterInfo; + cs_m680x *m680x = &info->m680x; + cs_detail *detail = MI->flat_insn->detail; + int suppress_operands = 0; + const char *delimiter = getDelimiter(info, m680x); + int i; + + if (detail != NULL) + memcpy(&detail->m680x, m680x, sizeof(cs_m680x)); + + if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) { + if (m680x->op_count) + SStream_concat(O, "fcb $%02X", m680x->operands[0].imm); + else + SStream_concat(O, "fcb $"); + + return; + } + + printInstructionName(MI->csh, O, info->insn); + SStream_concat(O, " "); + + if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0) + suppress_operands++; + + if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0) + suppress_operands++; + + for (i = 0; i < m680x->op_count; ++i) { + if (i >= suppress_operands) { + printOperand(MI, O, info, &m680x->operands[i]); + + if ((i + 1) != m680x->op_count) + SStream_concat(O, delimiter); + } + } +} + +const char *M680X_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + + if (reg >= ARR_SIZE(s_reg_names)) + return NULL; + + return s_reg_names[(int)reg]; +#else + return NULL; +#endif +} + +const char *M680X_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + + if (id >= ARR_SIZE(s_instruction_names)) + return NULL; + else + return s_instruction_names[(int)id]; + +#else + return NULL; +#endif +} + +const char *M680X_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(s_group_names, ARR_SIZE(s_group_names), id); +#else + return NULL; +#endif +} + +cs_err M680X_instprinter_init(cs_struct *ud) +{ +#ifndef CAPSTONE_DIET + + if (M680X_REG_ENDING != ARR_SIZE(s_reg_names)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_reg and s_reg_names\n"); + + return CS_ERR_MODE; + } + + if (M680X_INS_ENDING != ARR_SIZE(s_instruction_names)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_insn and s_instruction_names\n"); + + return CS_ERR_MODE; + } + + if (M680X_GRP_ENDING != ARR_SIZE(s_group_names)) { + fprintf(stderr, "Internal error: Size mismatch in enum " + "m680x_group_type and s_group_names\n"); + + return CS_ERR_MODE; + } + +#endif + + return CS_ERR_OK; +} + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.h b/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.h new file mode 100644 index 0000000..6fa9f8d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XInstPrinter.h @@ -0,0 +1,25 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifndef CS_M680XINSTPRINTER_H +#define CS_M680XINSTPRINTER_H + + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +struct SStream; + +void M680X_init(MCRegisterInfo *MRI); + +void M680X_printInst(MCInst *MI, struct SStream *O, void *Info); +const char *M680X_reg_name(csh handle, unsigned int reg); +const char *M680X_insn_name(csh handle, unsigned int id); +const char *M680X_group_name(csh handle, unsigned int id); +void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, + MCInst *mci); + +#endif + + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XModule.c b/white_patch_detect/capstone-master/arch/M680X/M680XModule.c new file mode 100644 index 0000000..3b89463 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XModule.c @@ -0,0 +1,77 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifdef CAPSTONE_HAS_M680X + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "M680XDisassembler.h" +#include "M680XDisassemblerInternals.h" +#include "M680XInstPrinter.h" +#include "M680XModule.h" + +cs_err M680X_global_init(cs_struct *ud) +{ + m680x_info *info; + cs_err errcode; + + /* Do some validation checks */ + errcode = M680X_disassembler_init(ud); + + if (errcode != CS_ERR_OK) + return errcode; + + errcode = M680X_instprinter_init(ud); + + if (errcode != CS_ERR_OK) + return errcode; + + // verify if requested mode is valid + if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | + CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | + CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | + CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | + CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) { + // At least one mode is not supported by M680X + return CS_ERR_MODE; + } + + if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | + CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | + CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | + CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | + CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) { + // At least the cpu type has to be selected. No default. + return CS_ERR_MODE; + } + + info = cs_mem_malloc(sizeof(m680x_info)); + + if (!info) + return CS_ERR_MEM; + + ud->printer = M680X_printInst; + ud->printer_info = info; + ud->getinsn_info = NULL; + ud->disasm = M680X_getInstruction; + ud->reg_name = M680X_reg_name; + ud->insn_id = M680X_get_insn_id; + ud->insn_name = M680X_insn_name; + ud->group_name = M680X_group_name; + ud->skipdata_size = 1; + ud->post_printer = NULL; +#ifndef CAPSTONE_DIET + ud->reg_access = M680X_reg_access; +#endif + + return CS_ERR_OK; +} + +cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + //TODO + return CS_ERR_OK; +} + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M680X/M680XModule.h b/white_patch_detect/capstone-master/arch/M680X/M680XModule.h new file mode 100644 index 0000000..6672eb2 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/M680XModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_M680X_MODULE_H +#define CS_M680X_MODULE_H + +#include "../../utils.h" + +cs_err M680X_global_init(cs_struct *ud); +cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/M680X/cpu12.inc b/white_patch_detect/capstone-master/arch/M680X/cpu12.inc new file mode 100644 index 0000000..83f2e89 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/cpu12.inc @@ -0,0 +1,335 @@ + +// CPU12 instructions on PAGE1 +static const inst_page1 g_cpu12_inst_page1_table[256] = { + // 0x0x + { M680X_INS_BGND, inh_hid, inh_hid }, + { M680X_INS_MEM, inh_hid, inh_hid }, + { M680X_INS_INY, inh_hid, inh_hid }, + { M680X_INS_DEY, inh_hid, inh_hid }, + { M680X_INS_DBEQ, loop_hid, inh_hid }, // or DBNE/IBEQ/IBNE/TBEQ/TBNE + { M680X_INS_JMP, idx12_hid, inh_hid }, + { M680X_INS_JMP, ext_hid, inh_hid }, + { M680X_INS_BSR, rel8_hid, inh_hid }, + { M680X_INS_INX, inh_hid, inh_hid }, + { M680X_INS_DEX, inh_hid, inh_hid }, + { M680X_INS_RTC, inh_hid, inh_hid }, + { M680X_INS_RTI, inh_hid, inh_hid }, + { M680X_INS_BSET, idx12_hid, imm8_hid }, + { M680X_INS_BCLR, idx12_hid, imm8_hid }, + { M680X_INS_BRSET, idx12_hid, imm8rel_hid }, + { M680X_INS_BRCLR, idx12_hid, imm8rel_hid }, + // 0x1x + { M680X_INS_ANDCC, imm8_hid, inh_hid }, + { M680X_INS_EDIV, inh_hid, inh_hid }, + { M680X_INS_MUL, inh_hid, inh_hid }, + { M680X_INS_EMUL, inh_hid, inh_hid }, + { M680X_INS_ORCC, imm8_hid, inh_hid }, + { M680X_INS_JSR, idx12_hid, inh_hid }, + { M680X_INS_JSR, ext_hid, inh_hid }, + { M680X_INS_JSR, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LEAY, idx12_hid, inh_hid }, + { M680X_INS_LEAX, idx12_hid, inh_hid }, + { M680X_INS_LEAS, idx12_hid, inh_hid }, + { M680X_INS_BSET, ext_hid, imm8_hid }, + { M680X_INS_BCLR, ext_hid, imm8_hid }, + { M680X_INS_BRSET, ext_hid, imm8rel_hid }, + { M680X_INS_BRCLR, ext_hid, imm8rel_hid }, + // 0x2x, relative branch instructions + { M680X_INS_BRA, rel8_hid, inh_hid }, + { M680X_INS_BRN, rel8_hid, inh_hid }, + { M680X_INS_BHI, rel8_hid, inh_hid }, + { M680X_INS_BLS, rel8_hid, inh_hid }, + { M680X_INS_BCC, rel8_hid, inh_hid }, + { M680X_INS_BCS, rel8_hid, inh_hid }, + { M680X_INS_BNE, rel8_hid, inh_hid }, + { M680X_INS_BEQ, rel8_hid, inh_hid }, + { M680X_INS_BVC, rel8_hid, inh_hid }, + { M680X_INS_BVS, rel8_hid, inh_hid }, + { M680X_INS_BPL, rel8_hid, inh_hid }, + { M680X_INS_BMI, rel8_hid, inh_hid }, + { M680X_INS_BGE, rel8_hid, inh_hid }, + { M680X_INS_BLT, rel8_hid, inh_hid }, + { M680X_INS_BGT, rel8_hid, inh_hid }, + { M680X_INS_BLE, rel8_hid, inh_hid }, + // 0x3x + { M680X_INS_PULX, inh_hid, inh_hid }, + { M680X_INS_PULY, inh_hid, inh_hid }, + { M680X_INS_PULA, inh_hid, inh_hid }, + { M680X_INS_PULB, inh_hid, inh_hid }, + { M680X_INS_PSHX, inh_hid, inh_hid }, + { M680X_INS_PSHY, inh_hid, inh_hid }, + { M680X_INS_PSHA, inh_hid, inh_hid }, + { M680X_INS_PSHB, inh_hid, inh_hid }, + { M680X_INS_PULC, inh_hid, inh_hid }, + { M680X_INS_PSHC, inh_hid, inh_hid }, + { M680X_INS_PULD, inh_hid, inh_hid }, + { M680X_INS_PSHD, inh_hid, inh_hid }, + { M680X_INS_WAVR, inh_hid, inh_hid }, + { M680X_INS_RTS, inh_hid, inh_hid }, + { M680X_INS_WAI, inh_hid, inh_hid }, + { M680X_INS_SWI, inh_hid, inh_hid }, + // 0x4x + { M680X_INS_NEGA, inh_hid, inh_hid }, + { M680X_INS_COMA, inh_hid, inh_hid }, + { M680X_INS_INCA, inh_hid, inh_hid }, + { M680X_INS_DECA, inh_hid, inh_hid }, + { M680X_INS_LSRA, inh_hid, inh_hid }, + { M680X_INS_ROLA, inh_hid, inh_hid }, + { M680X_INS_RORA, inh_hid, inh_hid }, + { M680X_INS_ASRA, inh_hid, inh_hid }, + { M680X_INS_ASLA, inh_hid, inh_hid }, + { M680X_INS_LSRD, inh_hid, inh_hid }, + { M680X_INS_CALL, ext_hid, index_hid }, + { M680X_INS_CALL, idx12_hid, index_hid }, + { M680X_INS_BSET, dir_hid, imm8_hid }, + { M680X_INS_BCLR, dir_hid, imm8_hid }, + { M680X_INS_BRSET, dir_hid, imm8rel_hid }, + { M680X_INS_BRCLR, dir_hid, imm8rel_hid }, + // 0x5x + { M680X_INS_NEGB, inh_hid, inh_hid }, + { M680X_INS_COMB, inh_hid, inh_hid }, + { M680X_INS_INCB, inh_hid, inh_hid }, + { M680X_INS_DECB, inh_hid, inh_hid }, + { M680X_INS_LSRB, inh_hid, inh_hid }, + { M680X_INS_ROLB, inh_hid, inh_hid }, + { M680X_INS_RORB, inh_hid, inh_hid }, + { M680X_INS_ASRB, inh_hid, inh_hid }, + { M680X_INS_ASLB, inh_hid, inh_hid }, + { M680X_INS_ASLD, inh_hid, inh_hid }, + { M680X_INS_STAA, dir_hid, inh_hid }, + { M680X_INS_STAB, dir_hid, inh_hid }, + { M680X_INS_STD, dir_hid, inh_hid }, + { M680X_INS_STY, dir_hid, inh_hid }, + { M680X_INS_STX, dir_hid, inh_hid }, + { M680X_INS_STS, dir_hid, inh_hid }, + // 0x6x + { M680X_INS_NEG, idx12_hid, inh_hid }, + { M680X_INS_COM, idx12_hid, inh_hid }, + { M680X_INS_INC, idx12_hid, inh_hid }, + { M680X_INS_DEC, idx12_hid, inh_hid }, + { M680X_INS_LSR, idx12_hid, inh_hid }, + { M680X_INS_ROL, idx12_hid, inh_hid }, + { M680X_INS_ROR, idx12_hid, inh_hid }, + { M680X_INS_ASR, idx12_hid, inh_hid }, + { M680X_INS_ASL, idx12_hid, inh_hid }, + { M680X_INS_CLR, idx12_hid, inh_hid }, + { M680X_INS_STAA, idx12_hid, inh_hid }, + { M680X_INS_STAB, idx12_hid, inh_hid }, + { M680X_INS_STD, idx12_hid, inh_hid }, + { M680X_INS_STY, idx12_hid, inh_hid }, + { M680X_INS_STX, idx12_hid, inh_hid }, + { M680X_INS_STS, idx12_hid, inh_hid }, + // 0x7x + { M680X_INS_NEG, ext_hid, inh_hid }, + { M680X_INS_COM, ext_hid, inh_hid }, + { M680X_INS_INC, ext_hid, inh_hid }, + { M680X_INS_DEC, ext_hid, inh_hid }, + { M680X_INS_LSR, ext_hid, inh_hid }, + { M680X_INS_ROL, ext_hid, inh_hid }, + { M680X_INS_ROR, ext_hid, inh_hid }, + { M680X_INS_ASR, ext_hid, inh_hid }, + { M680X_INS_ASL, ext_hid, inh_hid }, + { M680X_INS_CLR, ext_hid, inh_hid }, + { M680X_INS_STAA, ext_hid, inh_hid }, + { M680X_INS_STAB, ext_hid, inh_hid }, + { M680X_INS_STD, ext_hid, inh_hid }, + { M680X_INS_STY, ext_hid, inh_hid }, + { M680X_INS_STX, ext_hid, inh_hid }, + { M680X_INS_STS, ext_hid, inh_hid }, + // 0x8x + { M680X_INS_SUBA, imm8_hid, inh_hid }, + { M680X_INS_CMPA, imm8_hid, inh_hid }, + { M680X_INS_SBCA, imm8_hid, inh_hid }, + { M680X_INS_SUBD, imm16_hid, inh_hid }, + { M680X_INS_ANDA, imm8_hid, inh_hid }, + { M680X_INS_BITA, imm8_hid, inh_hid }, + { M680X_INS_LDAA, imm8_hid, inh_hid }, + { M680X_INS_CLRA, inh_hid, inh_hid }, + { M680X_INS_EORA, imm8_hid, inh_hid }, + { M680X_INS_ADCA, imm8_hid, inh_hid }, + { M680X_INS_ORAA, imm8_hid, inh_hid }, + { M680X_INS_ADDA, imm8_hid, inh_hid }, + { M680X_INS_CPD, imm16_hid, inh_hid }, + { M680X_INS_CPY, imm16_hid, inh_hid }, + { M680X_INS_CPX, imm16_hid, inh_hid }, + { M680X_INS_CPS, imm16_hid, inh_hid }, + // 0x9x + { M680X_INS_SUBA, dir_hid, inh_hid }, + { M680X_INS_CMPA, dir_hid, inh_hid }, + { M680X_INS_SBCA, dir_hid, inh_hid }, + { M680X_INS_SUBD, dir_hid, inh_hid }, + { M680X_INS_ANDA, dir_hid, inh_hid }, + { M680X_INS_BITA, dir_hid, inh_hid }, + { M680X_INS_LDAA, dir_hid, inh_hid }, + { M680X_INS_TSTA, inh_hid, inh_hid }, + { M680X_INS_EORA, dir_hid, inh_hid }, + { M680X_INS_ADCA, dir_hid, inh_hid }, + { M680X_INS_ORAA, dir_hid, inh_hid }, + { M680X_INS_ADDA, dir_hid, inh_hid }, + { M680X_INS_CPD, dir_hid, inh_hid }, + { M680X_INS_CPY, dir_hid, inh_hid }, + { M680X_INS_CPX, dir_hid, inh_hid }, + { M680X_INS_CPS, dir_hid, inh_hid }, + // 0xAx + { M680X_INS_SUBA, idx12_hid, inh_hid }, + { M680X_INS_CMPA, idx12_hid, inh_hid }, + { M680X_INS_SBCA, idx12_hid, inh_hid }, + { M680X_INS_SUBD, idx12_hid, inh_hid }, + { M680X_INS_ANDA, idx12_hid, inh_hid }, + { M680X_INS_BITA, idx12_hid, inh_hid }, + { M680X_INS_LDAA, idx12_hid, inh_hid }, + { M680X_INS_NOP, inh_hid, inh_hid }, + { M680X_INS_EORA, idx12_hid, inh_hid }, + { M680X_INS_ADCA, idx12_hid, inh_hid }, + { M680X_INS_ORAA, idx12_hid, inh_hid }, + { M680X_INS_ADDA, idx12_hid, inh_hid }, + { M680X_INS_CPD, idx12_hid, inh_hid }, + { M680X_INS_CPY, idx12_hid, inh_hid }, + { M680X_INS_CPX, idx12_hid, inh_hid }, + { M680X_INS_CPS, idx12_hid, inh_hid }, + // 0xBx + { M680X_INS_SUBA, ext_hid, inh_hid }, + { M680X_INS_CMPA, ext_hid, inh_hid }, + { M680X_INS_SBCA, ext_hid, inh_hid }, + { M680X_INS_SUBD, ext_hid, inh_hid }, + { M680X_INS_ANDA, ext_hid, inh_hid }, + { M680X_INS_BITA, ext_hid, inh_hid }, + { M680X_INS_LDAA, ext_hid, inh_hid }, + { M680X_INS_TFR, rr12_hid, inh_hid }, // or EXG + { M680X_INS_EORA, ext_hid, inh_hid }, + { M680X_INS_ADCA, ext_hid, inh_hid }, + { M680X_INS_ORAA, ext_hid, inh_hid }, + { M680X_INS_ADDA, ext_hid, inh_hid }, + { M680X_INS_CPD, ext_hid, inh_hid }, + { M680X_INS_CPY, ext_hid, inh_hid }, + { M680X_INS_CPX, ext_hid, inh_hid }, + { M680X_INS_CPS, ext_hid, inh_hid }, + // 0xCx + { M680X_INS_SUBB, imm8_hid, inh_hid }, + { M680X_INS_CMPB, imm8_hid, inh_hid }, + { M680X_INS_SBCB, imm8_hid, inh_hid }, + { M680X_INS_ADDD, imm16_hid, inh_hid }, + { M680X_INS_ANDB, imm8_hid, inh_hid }, + { M680X_INS_BITB, imm8_hid, inh_hid }, + { M680X_INS_LDAB, imm8_hid, inh_hid }, + { M680X_INS_CLRB, inh_hid, inh_hid }, + { M680X_INS_EORB, imm8_hid, inh_hid }, + { M680X_INS_ADCB, imm8_hid, inh_hid }, + { M680X_INS_ORAB, imm8_hid, inh_hid }, + { M680X_INS_ADDB, imm8_hid, inh_hid }, + { M680X_INS_LDD, imm16_hid, inh_hid }, + { M680X_INS_LDY, imm16_hid, inh_hid }, + { M680X_INS_LDX, imm16_hid, inh_hid }, + { M680X_INS_LDS, imm16_hid, inh_hid }, + // 0xDx + { M680X_INS_SUBB, dir_hid, inh_hid }, + { M680X_INS_CMPB, dir_hid, inh_hid }, + { M680X_INS_SBCB, dir_hid, inh_hid }, + { M680X_INS_ADDD, dir_hid, inh_hid }, + { M680X_INS_ANDB, dir_hid, inh_hid }, + { M680X_INS_BITB, dir_hid, inh_hid }, + { M680X_INS_LDAB, dir_hid, inh_hid }, + { M680X_INS_TSTB, inh_hid, inh_hid }, + { M680X_INS_EORB, dir_hid, inh_hid }, + { M680X_INS_ADCB, dir_hid, inh_hid }, + { M680X_INS_ORAB, dir_hid, inh_hid }, + { M680X_INS_ADDB, dir_hid, inh_hid }, + { M680X_INS_LDD, dir_hid, inh_hid }, + { M680X_INS_LDY, dir_hid, inh_hid }, + { M680X_INS_LDX, dir_hid, inh_hid }, + { M680X_INS_LDS, dir_hid, inh_hid }, + // 0xEx + { M680X_INS_SUBB, idx12_hid, inh_hid }, + { M680X_INS_CMPB, idx12_hid, inh_hid }, + { M680X_INS_SBCB, idx12_hid, inh_hid }, + { M680X_INS_ADDD, idx12_hid, inh_hid }, + { M680X_INS_ANDB, idx12_hid, inh_hid }, + { M680X_INS_BITB, idx12_hid, inh_hid }, + { M680X_INS_LDAB, idx12_hid, inh_hid }, + { M680X_INS_TST, idx12_hid, inh_hid }, + { M680X_INS_EORB, idx12_hid, inh_hid }, + { M680X_INS_ADCB, idx12_hid, inh_hid }, + { M680X_INS_ORAB, idx12_hid, inh_hid }, + { M680X_INS_ADDB, idx12_hid, inh_hid }, + { M680X_INS_LDD, idx12_hid, inh_hid }, + { M680X_INS_LDY, idx12_hid, inh_hid }, + { M680X_INS_LDX, idx12_hid, inh_hid }, + { M680X_INS_LDS, idx12_hid, inh_hid }, + // 0xFx + { M680X_INS_SUBA, ext_hid, inh_hid }, + { M680X_INS_CMPA, ext_hid, inh_hid }, + { M680X_INS_SBCA, ext_hid, inh_hid }, + { M680X_INS_ADDD, ext_hid, inh_hid }, + { M680X_INS_ANDA, ext_hid, inh_hid }, + { M680X_INS_BITA, ext_hid, inh_hid }, + { M680X_INS_LDAA, ext_hid, inh_hid }, + { M680X_INS_TST, ext_hid, inh_hid }, + { M680X_INS_EORA, ext_hid, inh_hid }, + { M680X_INS_ADCA, ext_hid, inh_hid }, + { M680X_INS_ORAA, ext_hid, inh_hid }, + { M680X_INS_ADDA, ext_hid, inh_hid }, + { M680X_INS_LDD, ext_hid, inh_hid }, + { M680X_INS_LDY, ext_hid, inh_hid }, + { M680X_INS_LDX, ext_hid, inh_hid }, + { M680X_INS_LDS, ext_hid, inh_hid }, +}; + +// CPU12 instructions on PAGE2 +static const inst_pageX g_cpu12_inst_page2_table[] = { + { 0x00, M680X_INS_MOVW, imm16i12x_hid, inh_hid }, + { 0x01, M680X_INS_MOVW, exti12x_hid, inh_hid }, + { 0x02, M680X_INS_MOVW, idx12_hid, idx12_hid }, + { 0x03, M680X_INS_MOVW, imm16_hid, ext_hid }, + { 0x04, M680X_INS_MOVW, ext_hid, ext_hid }, + { 0x05, M680X_INS_MOVW, idx12_hid, ext_hid }, + { 0x06, M680X_INS_ABA, inh_hid, inh_hid }, + { 0x07, M680X_INS_DAA, inh_hid, inh_hid }, + { 0x08, M680X_INS_MOVB, imm8i12x_hid, inh_hid }, + { 0x09, M680X_INS_MOVB, exti12x_hid, inh_hid }, + { 0x0a, M680X_INS_MOVB, idx12_hid, idx12_hid }, + { 0x0b, M680X_INS_MOVB, imm8_hid, ext_hid }, + { 0x0c, M680X_INS_MOVB, ext_hid, ext_hid }, + { 0x0d, M680X_INS_MOVB, idx12_hid, ext_hid }, + { 0x0e, M680X_INS_TAB, inh_hid, inh_hid }, + { 0x0f, M680X_INS_TBA, inh_hid, inh_hid }, + { 0x10, M680X_INS_IDIV, inh_hid, inh_hid }, + { 0x11, M680X_INS_FDIV, inh_hid, inh_hid }, + { 0x12, M680X_INS_EMACS, ext_hid, inh_hid }, + { 0x13, M680X_INS_EMULS, inh_hid, inh_hid }, + { 0x14, M680X_INS_EDIVS, inh_hid, inh_hid }, + { 0x15, M680X_INS_IDIVS, inh_hid, inh_hid }, + { 0x16, M680X_INS_SBA, inh_hid, inh_hid }, + { 0x17, M680X_INS_CBA, inh_hid, inh_hid }, + { 0x18, M680X_INS_MAXA, idx12_hid, inh_hid }, + { 0x19, M680X_INS_MINA, idx12_hid, inh_hid }, + { 0x1a, M680X_INS_EMAXD, idx12_hid, inh_hid }, + { 0x1b, M680X_INS_EMIND, idx12_hid, inh_hid }, + { 0x1c, M680X_INS_MAXM, idx12_hid, inh_hid }, + { 0x1d, M680X_INS_MINM, idx12_hid, inh_hid }, + { 0x1e, M680X_INS_EMAXM, idx12_hid, inh_hid }, + { 0x1f, M680X_INS_EMINM, idx12_hid, inh_hid }, + { 0x20, M680X_INS_LBRA, rel16_hid, inh_hid }, + { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, + { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, + { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, + { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, + { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, + { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, + { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, + { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, + { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, + { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, + { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, + { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, + { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, + { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, + { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, + { 0x3a, M680X_INS_REV, inh_hid, inh_hid }, + { 0x3b, M680X_INS_REVW, inh_hid, inh_hid }, + { 0x3c, M680X_INS_WAV, inh_hid, inh_hid }, + { 0x3d, M680X_INS_TBL, idx12s_hid, inh_hid }, + { 0x3e, M680X_INS_STOP, inh_hid, inh_hid }, + { 0x3f, M680X_INS_ETBL, idx12s_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/hcs08.inc b/white_patch_detect/capstone-master/arch/M680X/hcs08.inc new file mode 100644 index 0000000..60f8af6 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/hcs08.inc @@ -0,0 +1,60 @@ + +// Additional instructions only supported on HCS08 +static const inst_pageX g_hcs08_inst_overlay_table[] = { + { 0x32, M680X_INS_LDHX, ext_hid, inh_hid }, + { 0x3e, M680X_INS_CPHX, ext_hid, inh_hid }, + { 0x82, M680X_INS_BGND, inh_hid, inh_hid }, + { 0x96, M680X_INS_STHX, ext_hid, inh_hid }, +}; + +// HCS08 PAGE2 instructions (prefix 0x9E) +static const inst_pageX g_hcs08_inst_page2_table[] = { + { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, + { 0x61, M680X_INS_CBEQ, idxS_hid,rel8_hid }, + { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, + { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, + { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, + { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, + { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, + { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, + { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, + { 0x6b, M680X_INS_DBNZ, idxS_hid,rel8_hid }, + { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, + { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, + { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, + { 0xae, M680X_INS_LDHX, idxX0_hid, inh_hid }, + { 0xbe, M680X_INS_LDHX, idxX16_hid, inh_hid }, + { 0xce, M680X_INS_LDHX, idxX_hid, inh_hid }, + { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, + { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, + { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, + { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, + { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, + { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, + { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, + { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, + { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, + { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, + { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, + { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, + { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, + { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, + { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, + { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, + { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, + { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, + { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, + { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, + { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, + { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, + { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, + { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, + { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, + { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, + { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, + { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, + { 0xf3, M680X_INS_CPHX, idxS_hid, inh_hid }, + { 0xfe, M680X_INS_LDHX, idxS_hid, inh_hid }, + { 0xff, M680X_INS_STHX, idxS_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/hd6301.inc b/white_patch_detect/capstone-master/arch/M680X/hd6301.inc new file mode 100644 index 0000000..63493ab --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/hd6301.inc @@ -0,0 +1,15 @@ + +// Additional instructions only supported on HD6301/3 +static const inst_pageX g_hd6301_inst_overlay_table[] = { + { 0x18, M680X_INS_XGDX, inh_hid, inh_hid }, + { 0x1a, M680X_INS_SLP, inh_hid, inh_hid }, + { 0x61, M680X_INS_AIM, imm8_hid, idxX_hid }, + { 0x62, M680X_INS_OIM, imm8_hid, idxX_hid }, + { 0x65, M680X_INS_EIM, imm8_hid, idxX_hid }, + { 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid }, + { 0x71, M680X_INS_AIM, imm8_hid, dir_hid }, + { 0x72, M680X_INS_OIM, imm8_hid, dir_hid }, + { 0x75, M680X_INS_EIM, imm8_hid, dir_hid }, + { 0x7B, M680X_INS_TIM, imm8_hid, dir_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/hd6309.inc b/white_patch_detect/capstone-master/arch/M680X/hd6309.inc new file mode 100644 index 0000000..69c0dec --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/hd6309.inc @@ -0,0 +1,259 @@ + +// The following array has to be sorted by increasing +// opcodes. Otherwise the binary_search will fail. +// +// Additional instructions only supported on HD6309 PAGE1 +static const inst_pageX g_hd6309_inst_overlay_table[] = { + { 0x01, M680X_INS_OIM, imm8_hid, dir_hid }, + { 0x02, M680X_INS_AIM, imm8_hid, dir_hid }, + { 0x05, M680X_INS_EIM, imm8_hid, dir_hid }, + { 0x0B, M680X_INS_TIM, imm8_hid, dir_hid }, + { 0x14, M680X_INS_SEXW, inh_hid, inh_hid }, + { 0x61, M680X_INS_OIM, imm8_hid, idx09_hid }, + { 0x62, M680X_INS_AIM, imm8_hid, idx09_hid }, + { 0x65, M680X_INS_EIM, imm8_hid, idx09_hid }, + { 0x6B, M680X_INS_TIM, imm8_hid, idx09_hid }, + { 0x71, M680X_INS_OIM, imm8_hid, ext_hid }, + { 0x72, M680X_INS_AIM, imm8_hid, ext_hid }, + { 0x75, M680X_INS_EIM, imm8_hid, ext_hid }, + { 0x7B, M680X_INS_TIM, imm8_hid, ext_hid }, + { 0xCD, M680X_INS_LDQ, imm32_hid, inh_hid }, +}; + +// The following array has to be sorted by increasing +// opcodes. Otherwise the binary_search will fail. +// +// HD6309 PAGE2 instructions (with prefix 0x10) +static const inst_pageX g_hd6309_inst_page2_table[] = { + // 0x2x, relative long branch instructions + { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, + { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, + { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, + { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, + { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, + { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, + { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, + { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, + { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, + { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, + { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, + { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, + { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, + { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, + { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, + // 0x3x + { 0x30, M680X_INS_ADDR, rr09_hid, inh_hid }, + { 0x31, M680X_INS_ADCR, rr09_hid, inh_hid }, + { 0x32, M680X_INS_SUBR, rr09_hid, inh_hid }, + { 0x33, M680X_INS_SBCR, rr09_hid, inh_hid }, + { 0x34, M680X_INS_ANDR, rr09_hid, inh_hid }, + { 0x35, M680X_INS_ORR, rr09_hid, inh_hid }, + { 0x36, M680X_INS_EORR, rr09_hid, inh_hid }, + { 0x37, M680X_INS_CMPR, rr09_hid, inh_hid }, + { 0x38, M680X_INS_PSHSW, inh_hid, inh_hid }, + { 0x39, M680X_INS_PULSW, inh_hid, inh_hid }, + { 0x3a, M680X_INS_PSHUW, inh_hid, inh_hid }, + { 0x3b, M680X_INS_PULUW, inh_hid, inh_hid }, + { 0x3f, M680X_INS_SWI2, inh_hid, inh_hid }, + // 0x4x, Register D instructions + { 0x40, M680X_INS_NEGD, inh_hid, inh_hid }, + { 0x43, M680X_INS_COMD, inh_hid, inh_hid }, + { 0x44, M680X_INS_LSRD, inh_hid, inh_hid }, + { 0x46, M680X_INS_RORD, inh_hid, inh_hid }, + { 0x47, M680X_INS_ASRD, inh_hid, inh_hid }, + { 0x48, M680X_INS_LSLD, inh_hid, inh_hid }, + { 0x49, M680X_INS_ROLD, inh_hid, inh_hid }, + { 0x4a, M680X_INS_DECD, inh_hid, inh_hid }, + { 0x4c, M680X_INS_INCD, inh_hid, inh_hid }, + { 0x4d, M680X_INS_TSTD, inh_hid, inh_hid }, + { 0x4f, M680X_INS_CLRD, inh_hid, inh_hid }, + // 0x5x, Register W instructions + { 0x53, M680X_INS_COMW, inh_hid, inh_hid }, + { 0x54, M680X_INS_LSRW, inh_hid, inh_hid }, + { 0x56, M680X_INS_RORW, inh_hid, inh_hid }, + { 0x59, M680X_INS_ROLW, inh_hid, inh_hid }, + { 0x5a, M680X_INS_DECW, inh_hid, inh_hid }, + { 0x5c, M680X_INS_INCW, inh_hid, inh_hid }, + { 0x5d, M680X_INS_TSTW, inh_hid, inh_hid }, + { 0x5f, M680X_INS_CLRW, inh_hid, inh_hid }, + // 0x8x, immediate instructionY with register D,W,Y + { 0x80, M680X_INS_SUBW, imm16_hid, inh_hid }, + { 0x81, M680X_INS_CMPW, imm16_hid, inh_hid }, + { 0x82, M680X_INS_SBCD, imm16_hid, inh_hid }, + { 0x83, M680X_INS_CMPD, imm16_hid, inh_hid }, + { 0x84, M680X_INS_ANDD, imm16_hid, inh_hid }, + { 0x85, M680X_INS_BITD, imm16_hid, inh_hid }, + { 0x86, M680X_INS_LDW, imm16_hid, inh_hid }, + { 0x88, M680X_INS_EORD, imm16_hid, inh_hid }, + { 0x89, M680X_INS_ADCD, imm16_hid, inh_hid }, + { 0x8a, M680X_INS_ORD, imm16_hid, inh_hid }, + { 0x8b, M680X_INS_ADDW, imm16_hid, inh_hid }, + { 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid }, + { 0x8e, M680X_INS_LDY, imm16_hid, inh_hid }, + // 0x9x, direct instructions with register D,W,Y + { 0x90, M680X_INS_SUBW, dir_hid, inh_hid }, + { 0x91, M680X_INS_CMPW, dir_hid, inh_hid }, + { 0x92, M680X_INS_SBCD, dir_hid, inh_hid }, + { 0x93, M680X_INS_CMPD, dir_hid, inh_hid }, + { 0x94, M680X_INS_ANDD, dir_hid, inh_hid }, + { 0x95, M680X_INS_BITD, dir_hid, inh_hid }, + { 0x96, M680X_INS_LDW, dir_hid, inh_hid }, + { 0x97, M680X_INS_STW, dir_hid, inh_hid }, + { 0x98, M680X_INS_EORD, dir_hid, inh_hid }, + { 0x99, M680X_INS_ADCD, dir_hid, inh_hid }, + { 0x9a, M680X_INS_ORD, dir_hid, inh_hid }, + { 0x9b, M680X_INS_ADDW, dir_hid, inh_hid }, + { 0x9c, M680X_INS_CMPY, dir_hid, inh_hid }, + { 0x9e, M680X_INS_LDY, dir_hid, inh_hid }, + { 0x9f, M680X_INS_STY, dir_hid, inh_hid }, + // 0xAx, indexed instructions with register D,W,Y + { 0xa0, M680X_INS_SUBW, idx09_hid, inh_hid }, + { 0xa1, M680X_INS_CMPW, idx09_hid, inh_hid }, + { 0xa2, M680X_INS_SBCD, idx09_hid, inh_hid }, + { 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid }, + { 0xa4, M680X_INS_ANDD, idx09_hid, inh_hid }, + { 0xa5, M680X_INS_BITD, idx09_hid, inh_hid }, + { 0xa6, M680X_INS_LDW, idx09_hid, inh_hid }, + { 0xa7, M680X_INS_STW, idx09_hid, inh_hid }, + { 0xa8, M680X_INS_EORD, idx09_hid, inh_hid }, + { 0xa9, M680X_INS_ADCD, idx09_hid, inh_hid }, + { 0xaa, M680X_INS_ORD, idx09_hid, inh_hid }, + { 0xab, M680X_INS_ADDW, idx09_hid, inh_hid }, + { 0xac, M680X_INS_CMPY, idx09_hid, inh_hid }, + { 0xae, M680X_INS_LDY, idx09_hid, inh_hid }, + { 0xaf, M680X_INS_STY, idx09_hid, inh_hid }, + // 0xBx, extended instructions with register D,W,Y + { 0xb0, M680X_INS_SUBW, ext_hid, inh_hid }, + { 0xb1, M680X_INS_CMPW, ext_hid, inh_hid }, + { 0xb2, M680X_INS_SBCD, ext_hid, inh_hid }, + { 0xb3, M680X_INS_CMPD, ext_hid, inh_hid }, + { 0xb4, M680X_INS_ANDD, ext_hid, inh_hid }, + { 0xb5, M680X_INS_BITD, ext_hid, inh_hid }, + { 0xb6, M680X_INS_LDW, ext_hid, inh_hid }, + { 0xb7, M680X_INS_STW, ext_hid, inh_hid }, + { 0xb8, M680X_INS_EORD, ext_hid, inh_hid }, + { 0xb9, M680X_INS_ADCD, ext_hid, inh_hid }, + { 0xba, M680X_INS_ORD, ext_hid, inh_hid }, + { 0xbb, M680X_INS_ADDW, ext_hid, inh_hid }, + { 0xbc, M680X_INS_CMPY, ext_hid, inh_hid }, + { 0xbe, M680X_INS_LDY, ext_hid, inh_hid }, + { 0xbf, M680X_INS_STY, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register S + { 0xce, M680X_INS_LDS, imm16_hid, inh_hid }, + // 0xDx, direct instructions with register S,Q + { 0xdc, M680X_INS_LDQ, dir_hid, inh_hid }, + { 0xdd, M680X_INS_STQ, dir_hid, inh_hid }, + { 0xde, M680X_INS_LDS, dir_hid, inh_hid }, + { 0xdf, M680X_INS_STS, dir_hid, inh_hid }, + // 0xEx, indexed instructions with register S,Q + { 0xec, M680X_INS_LDQ, idx09_hid, inh_hid }, + { 0xed, M680X_INS_STQ, idx09_hid, inh_hid }, + { 0xee, M680X_INS_LDS, idx09_hid, inh_hid }, + { 0xef, M680X_INS_STS, idx09_hid, inh_hid }, + // 0xFx, extended instructions with register S,Q + { 0xfc, M680X_INS_LDQ, ext_hid, inh_hid }, + { 0xfd, M680X_INS_STQ, ext_hid, inh_hid }, + { 0xfe, M680X_INS_LDS, ext_hid, inh_hid }, + { 0xff, M680X_INS_STS, ext_hid, inh_hid }, +}; + +// The following array has to be sorted by increasing +// opcodes. Otherwise the binary_search will fail. +// +// HD6309 PAGE3 instructions (with prefix 0x11) +static const inst_pageX g_hd6309_inst_page3_table[] = { + { 0x30, M680X_INS_BAND, bitmv_hid, inh_hid }, + { 0x31, M680X_INS_BIAND, bitmv_hid, inh_hid }, + { 0x32, M680X_INS_BOR, bitmv_hid, inh_hid }, + { 0x33, M680X_INS_BIOR, bitmv_hid, inh_hid }, + { 0x34, M680X_INS_BEOR, bitmv_hid, inh_hid }, + { 0x35, M680X_INS_BIEOR, bitmv_hid, inh_hid }, + { 0x36, M680X_INS_LDBT, bitmv_hid, inh_hid }, + { 0x37, M680X_INS_STBT, bitmv_hid, inh_hid }, + { 0x38, M680X_INS_TFM, tfm_hid, inh_hid }, + { 0x39, M680X_INS_TFM, tfm_hid, inh_hid }, + { 0x3a, M680X_INS_TFM, tfm_hid, inh_hid }, + { 0x3b, M680X_INS_TFM, tfm_hid, inh_hid }, + { 0x3c, M680X_INS_BITMD, imm8_hid, inh_hid }, + { 0x3d, M680X_INS_LDMD, imm8_hid, inh_hid }, + { 0x3f, M680X_INS_SWI3, inh_hid, inh_hid }, + // 0x4x, Register E instructions + { 0x43, M680X_INS_COME, inh_hid, inh_hid }, + { 0x4a, M680X_INS_DECE, inh_hid, inh_hid }, + { 0x4c, M680X_INS_INCE, inh_hid, inh_hid }, + { 0x4d, M680X_INS_TSTE, inh_hid, inh_hid }, + { 0x4f, M680X_INS_CLRE, inh_hid, inh_hid }, + // 0x5x, Register F instructions + { 0x53, M680X_INS_COMF, inh_hid, inh_hid }, + { 0x5a, M680X_INS_DECF, inh_hid, inh_hid }, + { 0x5c, M680X_INS_INCF, inh_hid, inh_hid }, + { 0x5d, M680X_INS_TSTF, inh_hid, inh_hid }, + { 0x5f, M680X_INS_CLRF, inh_hid, inh_hid }, + // 0x8x, immediate instructions with register U,S,E + { 0x80, M680X_INS_SUBE, imm8_hid, inh_hid }, + { 0x81, M680X_INS_CMPE, imm8_hid, inh_hid }, + { 0x83, M680X_INS_CMPU, imm16_hid, inh_hid }, + { 0x86, M680X_INS_LDE, imm8_hid, inh_hid }, + { 0x8b, M680X_INS_ADDE, imm8_hid, inh_hid }, + { 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid }, + { 0x8d, M680X_INS_DIVD, imm8_hid, inh_hid }, + { 0x8e, M680X_INS_DIVQ, imm16_hid, inh_hid }, + { 0x8f, M680X_INS_MULD, imm16_hid, inh_hid }, + // 0x9x, direct instructions with register U,S,E,Q + { 0x90, M680X_INS_SUBE, dir_hid, inh_hid }, + { 0x91, M680X_INS_CMPE, dir_hid, inh_hid }, + { 0x93, M680X_INS_CMPU, dir_hid, inh_hid }, + { 0x96, M680X_INS_LDE, dir_hid, inh_hid }, + { 0x97, M680X_INS_STE, dir_hid, inh_hid }, + { 0x9b, M680X_INS_ADDE, dir_hid, inh_hid }, + { 0x9c, M680X_INS_CMPS, dir_hid, inh_hid }, + { 0x9d, M680X_INS_DIVD, dir_hid, inh_hid }, + { 0x9e, M680X_INS_DIVQ, dir_hid, inh_hid }, + { 0x9f, M680X_INS_MULD, dir_hid, inh_hid }, + // 0xAx, indexed instructions with register U,S,D,Q + { 0xa0, M680X_INS_SUBE, idx09_hid, inh_hid }, + { 0xa1, M680X_INS_CMPE, idx09_hid, inh_hid }, + { 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid }, + { 0xa6, M680X_INS_LDE, idx09_hid, inh_hid }, + { 0xa7, M680X_INS_STE, idx09_hid, inh_hid }, + { 0xab, M680X_INS_ADDE, idx09_hid, inh_hid }, + { 0xac, M680X_INS_CMPS, idx09_hid, inh_hid }, + { 0xad, M680X_INS_DIVD, idx09_hid, inh_hid }, + { 0xae, M680X_INS_DIVQ, idx09_hid, inh_hid }, + { 0xaf, M680X_INS_MULD, idx09_hid, inh_hid }, + // 0xBx, extended instructions with register U,S,D,Q + { 0xb0, M680X_INS_SUBE, ext_hid, inh_hid }, + { 0xb1, M680X_INS_CMPE, ext_hid, inh_hid }, + { 0xb3, M680X_INS_CMPU, ext_hid, inh_hid }, + { 0xb6, M680X_INS_LDE, ext_hid, inh_hid }, + { 0xb7, M680X_INS_STE, ext_hid, inh_hid }, + { 0xbb, M680X_INS_ADDE, ext_hid, inh_hid }, + { 0xbc, M680X_INS_CMPS, ext_hid, inh_hid }, + { 0xbd, M680X_INS_DIVD, ext_hid, inh_hid }, + { 0xbe, M680X_INS_DIVQ, ext_hid, inh_hid }, + { 0xbf, M680X_INS_MULD, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register F + { 0xc0, M680X_INS_SUBF, imm8_hid, inh_hid }, + { 0xc1, M680X_INS_CMPF, imm8_hid, inh_hid }, + { 0xc6, M680X_INS_LDF, imm8_hid, inh_hid }, + { 0xcb, M680X_INS_ADDF, imm8_hid, inh_hid }, + // 0xDx, direct instructions with register F + { 0xd0, M680X_INS_SUBF, dir_hid, inh_hid }, + { 0xd1, M680X_INS_CMPF, dir_hid, inh_hid }, + { 0xd6, M680X_INS_LDF, dir_hid, inh_hid }, + { 0xd7, M680X_INS_STF, dir_hid, inh_hid }, + { 0xdb, M680X_INS_ADDF, dir_hid, inh_hid }, + // 0xEx, indexed instructions with register F + { 0xe0, M680X_INS_SUBF, idx09_hid, inh_hid }, + { 0xe1, M680X_INS_CMPF, idx09_hid, inh_hid }, + { 0xe6, M680X_INS_LDF, idx09_hid, inh_hid }, + { 0xe7, M680X_INS_STF, idx09_hid, inh_hid }, + { 0xeb, M680X_INS_ADDF, idx09_hid, inh_hid }, + // 0xFx, extended instructions with register F + { 0xf0, M680X_INS_SUBF, ext_hid, inh_hid }, + { 0xf1, M680X_INS_CMPF, ext_hid, inh_hid }, + { 0xf6, M680X_INS_LDF, ext_hid, inh_hid }, + { 0xf7, M680X_INS_STF, ext_hid, inh_hid }, + { 0xfb, M680X_INS_ADDF, ext_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/insn_props.inc b/white_patch_detect/capstone-master/arch/M680X/insn_props.inc new file mode 100644 index 0000000..813bffb --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/insn_props.inc @@ -0,0 +1,367 @@ + +// These temporary defines keep the following table short and handy. +#define NOG M680X_GRP_INVALID +#define NOR M680X_REG_INVALID + +static const insn_props g_insn_props[] = { + { NOG, uuuu, NOR, NOR, false, false }, // INVLD + { NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // ABA + { NOG, rmmm, M680X_REG_B, M680X_REG_X, false, false }, // ABX + { NOG, rmmm, M680X_REG_B, M680X_REG_Y, false, false }, // ABY + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADC + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADCA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADCB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADCD + { NOG, rmmm, NOR, NOR, true, false }, // ADCR + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADD + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADDA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADDB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADDD + { NOG, mrrr, M680X_REG_E, NOR, true, false }, // ADDE + { NOG, mrrr, M680X_REG_F, NOR, true, false }, // ADDF + { NOG, rmmm, NOR, NOR, true, false }, // ADDR + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // ADDW + { NOG, rmmm, NOR, NOR, true, false }, // AIM + { NOG, mrrr, M680X_REG_S, NOR, false, false }, // AIS + { NOG, mrrr, M680X_REG_HX, NOR, false, false }, // AIX + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // AND + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ANDA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ANDB + { NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ANDCC + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ANDD + { NOG, rmmm, NOR, NOR, true, false }, // ANDR + { NOG, mrrr, NOR, NOR, true, false }, // ASL + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASLA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASLB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASLD + { NOG, mrrr, NOR, NOR, true, false }, // ASR + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASRA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASRB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASRD + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // ASRX + { NOG, mrrr, NOR, NOR, false, false }, // BAND + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCC + { NOG, mrrr, NOR, NOR, true, false }, // BCLR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCS + { NOG, mrrr, NOR, NOR, false, false }, // BEOR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BEQ + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGE + { NOG, uuuu, NOR, NOR, false, false }, // BGND + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGT + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCC + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCS + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHI + { NOG, mrrr, NOR, NOR, false, false }, // BIAND + { NOG, mrrr, NOR, NOR, false, false }, // BIEOR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIH + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIL + { NOG, mrrr, NOR, NOR, false, false }, // BIOR + { NOG, rrrr, M680X_REG_A, NOR, true, false }, // BIT + { NOG, rrrr, M680X_REG_A, NOR, true, false }, // BITA + { NOG, rrrr, M680X_REG_B, NOR, true, false }, // BITB + { NOG, rrrr, M680X_REG_D, NOR, true, false }, // BITD + { NOG, rrrr, M680X_REG_MD, NOR, true, false }, // BITMD + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLE + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLS + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLT + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMC + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMI + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMS + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BNE + { NOG, mrrr, NOR, NOR, false, false }, // BOR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BPL + { M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRCLR + { M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRSET + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRA + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRN never branches + { NOG, mrrr, NOR, NOR, true, false }, // BSET + { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // BSR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVC + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVS + { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // CALL + { NOG, rrrr, M680X_REG_B, M680X_REG_A, true, false }, // CBA + { M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQ + { M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQA + { M680X_GRP_JUMP, rruu, M680X_REG_X, NOR, false, false }, // CBEQX + { NOG, uuuu, NOR, NOR, true, false }, // CLC + { NOG, uuuu, NOR, NOR, true, false }, // CLI + { NOG, wrrr, NOR, NOR, true, false }, // CLR + { NOG, wrrr, M680X_REG_A, NOR, true, false }, // CLRA + { NOG, wrrr, M680X_REG_B, NOR, true, false }, // CLRB + { NOG, wrrr, M680X_REG_D, NOR, true, false }, // CLRD + { NOG, wrrr, M680X_REG_E, NOR, true, false }, // CLRE + { NOG, wrrr, M680X_REG_F, NOR, true, false }, // CLRF + { NOG, wrrr, M680X_REG_H, NOR, true, false }, // CLRH + { NOG, wrrr, M680X_REG_W, NOR, true, false }, // CLRW + { NOG, wrrr, M680X_REG_X, NOR, true, false }, // CLRX + { NOG, uuuu, NOR, NOR, true, false }, // CLV + { NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMP + { NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMPA + { NOG, rrrr, M680X_REG_B, NOR, true, false }, // CMPB + { NOG, rrrr, M680X_REG_D, NOR, true, false }, // CMPD + { NOG, rrrr, M680X_REG_E, NOR, true, false }, // CMPE + { NOG, rrrr, M680X_REG_F, NOR, true, false }, // CMPF + { NOG, rrrr, NOR, NOR, true, false }, // CMPR + { NOG, rrrr, M680X_REG_S, NOR, true, false }, // CMPS + { NOG, rrrr, M680X_REG_U, NOR, true, false }, // CMPU + { NOG, rrrr, M680X_REG_W, NOR, true, false }, // CMPW + { NOG, rrrr, M680X_REG_X, NOR, true, false }, // CMPX + { NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CMPY + { NOG, mrrr, NOR, NOR, true, false }, // COM + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // COMA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // COMB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // COMD + { NOG, mrrr, M680X_REG_E, NOR, true, false }, // COME + { NOG, mrrr, M680X_REG_F, NOR, true, false }, // COMF + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // COMW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // COMX + { NOG, rrrr, M680X_REG_D, NOR, true, false }, // CPD + { NOG, rrrr, M680X_REG_HX, NOR, true, false }, // CPHX + { NOG, rrrr, M680X_REG_S, NOR, true, false }, // CPS + { NOG, rrrr, M680X_REG_X, NOR, true, false }, // CPX + { NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CPY + { NOG, mrrr, NOR, NOR, true, true }, // CWAI + { NOG, mrrr, NOR, NOR, true, true }, // DAA + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBEQ + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNE + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNZ + { M680X_GRP_JUMP, muuu, M680X_REG_A, NOR, false, false }, // DBNZA + { M680X_GRP_JUMP, muuu, M680X_REG_X, NOR, false, false }, // DBNZX + { NOG, mrrr, NOR, NOR, true, false }, // DEC + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // DECA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // DECB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // DECD + { NOG, mrrr, M680X_REG_E, NOR, true, false }, // DECE + { NOG, mrrr, M680X_REG_F, NOR, true, false }, // DECF + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // DECW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // DECX + { NOG, mrrr, M680X_REG_S, NOR, false, false }, // DES + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // DEX + { NOG, mrrr, M680X_REG_Y, NOR, true, false }, // DEY + { NOG, mmrr, NOR, NOR, true, true }, // DIV + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // DIVD + { NOG, mrrr, M680X_REG_Q, NOR, true, false }, // DIVQ + { NOG, mmrr, NOR, NOR, true, true }, // EDIV + { NOG, mmrr, NOR, NOR, true, true }, // EDIVS + { NOG, rmmm, NOR, NOR, true, false }, // EIM + { NOG, mrrr, NOR, NOR, true, true }, // EMACS + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMAXD + { NOG, mrrr, NOR, NOR, true, true }, // EMAXM + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMIND + { NOG, mrrr, NOR, NOR, true, true }, // EMINM + { NOG, mmrr, NOR, NOR, true, true }, // EMUL + { NOG, mmrr, NOR, NOR, true, true }, // EMULS + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // EOR + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // EORA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // EORB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EORD + { NOG, rmmm, NOR, NOR, true, false }, // EORR + { NOG, rmmm, NOR, NOR, true, true }, // ETBL + { NOG, mmmm, NOR, NOR, false, false }, // EXG + { NOG, mmmm, NOR, NOR, true, true }, // FDIV + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBEQ + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBNE + { NOG, mmmm, NOR, NOR, true, true }, // IDIV + { NOG, mmmm, NOR, NOR, true, true }, // IDIVS + { NOG, uuuu, NOR, NOR, false, false }, // ILLGL + { NOG, mrrr, NOR, NOR, true, false }, // INC + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // INCA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // INCB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // INCD + { NOG, mrrr, M680X_REG_E, NOR, true, false }, // INCE + { NOG, mrrr, M680X_REG_F, NOR, true, false }, // INCF + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // INCW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // INCX + { NOG, mrrr, M680X_REG_S, NOR, false, false }, // INS + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // INX + { NOG, mrrr, M680X_REG_Y, NOR, true, false }, // INY + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // JMP + { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // JSR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCC + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCS + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBEQ + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGE + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGT + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBHI + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLE + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLS + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLT + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBMI + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBNE + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBPL + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRA + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRN never branches + { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // LBSR + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVC + { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVS + { NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDA + { NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDAA + { NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDAB + { NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDB + { NOG, mrrr, NOR, NOR, false, false }, // LDBT + { NOG, wrrr, M680X_REG_D, NOR, true, false }, // LDD + { NOG, wrrr, M680X_REG_E, NOR, true, false }, // LDE + { NOG, wrrr, M680X_REG_F, NOR, true, false }, // LDF + { NOG, wrrr, M680X_REG_HX, NOR, true, false }, // LDHX + { NOG, mrrr, M680X_REG_MD, NOR, false, false }, // LDMD + { NOG, wrrr, M680X_REG_Q, NOR, true, false }, // LDQ + { NOG, wrrr, M680X_REG_S, NOR, true, false }, // LDS + { NOG, wrrr, M680X_REG_U, NOR, true, false }, // LDU + { NOG, wrrr, M680X_REG_W, NOR, true, false }, // LDW + { NOG, wrrr, M680X_REG_X, NOR, true, false }, // LDX + { NOG, wrrr, M680X_REG_Y, NOR, true, false }, // LDY + { NOG, wrrr, M680X_REG_S, NOR, false, false }, // LEAS + { NOG, wrrr, M680X_REG_U, NOR, false, false }, // LEAU + { NOG, wrrr, M680X_REG_X, NOR, false, false }, // LEAX + { NOG, wrrr, M680X_REG_Y, NOR, false, false }, // LEAY + { NOG, mrrr, NOR, NOR, true, false }, // LSL + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSLA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSLB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSLD + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSLX + { NOG, mrrr, NOR, NOR, true, false }, // LSR + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSRA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSRB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSRD + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // LSRW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSRX + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // MAXA + { NOG, mrrr, NOR, NOR, true, true }, // MAXM + { NOG, mmrr, NOR, NOR, true, true }, // MEM + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // MINA + { NOG, mrrr, NOR, NOR, true, true }, // MINM + { NOG, rwww, NOR, NOR, true, false }, // MOV + { NOG, rwww, NOR, NOR, false, false }, // MOVB + { NOG, rwww, NOR, NOR, false, false }, // MOVW + { NOG, mmmm, NOR, NOR, true, true }, // MUL + { NOG, mwrr, M680X_REG_D, NOR, true, true }, // MULD + { NOG, mrrr, NOR, NOR, true, false }, // NEG + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // NEGA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // NEGB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // NEGD + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // NEGX + { NOG, uuuu, NOR, NOR, false, false }, // NOP + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // NSA + { NOG, rmmm, NOR, NOR, true, false }, // OIM + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORA + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORAA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORAB + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORB + { NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ORCC + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ORD + { NOG, rmmm, NOR, NOR, true, false }, // ORR + { NOG, rmmm, M680X_REG_A, NOR, false, true }, // PSHA + { NOG, rmmm, M680X_REG_B, NOR, false, true }, // PSHB + { NOG, rmmm, M680X_REG_CC, NOR, false, true }, // PSHC + { NOG, rmmm, M680X_REG_D, NOR, false, true }, // PSHD + { NOG, rmmm, M680X_REG_H, NOR, false, true }, // PSHH + { NOG, mrrr, M680X_REG_S, NOR, false, false }, // PSHS + { NOG, mrrr, M680X_REG_S, M680X_REG_W, false, false }, // PSHSW + { NOG, mrrr, M680X_REG_U, NOR, false, false }, // PSHU + { NOG, mrrr, M680X_REG_U, M680X_REG_W, false, false }, // PSHUW + { NOG, rmmm, M680X_REG_X, NOR, false, true }, // PSHX + { NOG, rmmm, M680X_REG_Y, NOR, false, true }, // PSHY + { NOG, wmmm, M680X_REG_A, NOR, false, true }, // PULA + { NOG, wmmm, M680X_REG_B, NOR, false, true }, // PULB + { NOG, wmmm, M680X_REG_CC, NOR, false, true }, // PULC + { NOG, wmmm, M680X_REG_D, NOR, false, true }, // PULD + { NOG, wmmm, M680X_REG_H, NOR, false, true }, // PULH + { NOG, mwww, M680X_REG_S, NOR, false, false }, // PULS + { NOG, mwww, M680X_REG_S, M680X_REG_W, false, false }, // PULSW + { NOG, mwww, M680X_REG_U, NOR, false, false }, // PULU + { NOG, mwww, M680X_REG_U, M680X_REG_W, false, false }, // PULUW + { NOG, wmmm, M680X_REG_X, NOR, false, true }, // PULX + { NOG, wmmm, M680X_REG_Y, NOR, false, true }, // PULY + { NOG, mmrr, NOR, NOR, true, true }, // REV + { NOG, mmmm, NOR, NOR, true, true }, // REVW + { NOG, mrrr, NOR, NOR, true, false }, // ROL + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ROLA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ROLB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ROLD + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // ROLW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // ROLX + { NOG, mrrr, NOR, NOR, true, false }, // ROR + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // RORA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // RORB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // RORD + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // RORW + { NOG, mrrr, M680X_REG_X, NOR, true, false }, // RORX + { NOG, wrrr, M680X_REG_S, NOR, false, false }, // RSP + { M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTC + { M680X_GRP_IRET, mwww, NOR, NOR, false, true }, // RTI + { M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTS + { NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // SBA + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBC + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBCA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // SBCB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // SBCD + { NOG, rmmm, NOR, NOR, true, false }, // SBCR + { NOG, uuuu, NOR, NOR, true, false }, // SEC + { NOG, uuuu, NOR, NOR, true, false }, // SEI + { NOG, uuuu, NOR, NOR, true, false }, // SEV + { NOG, wrrr, NOR, NOR, true, true }, // SEX + { NOG, rwww, M680X_REG_W, NOR, true, true }, // SEXW + { NOG, uuuu, NOR, NOR, false, false }, // SLP + { NOG, rwww, M680X_REG_A, NOR, true, false }, // STA + { NOG, rwww, M680X_REG_A, NOR, true, false }, // STAA + { NOG, rwww, M680X_REG_B, NOR, true, false }, // STAB + { NOG, rwww, M680X_REG_B, NOR, true, false }, // STB + { NOG, rrrm, NOR, NOR, false, false }, // STBT + { NOG, rwww, M680X_REG_D, NOR, true, false }, // STD + { NOG, rwww, M680X_REG_E, NOR, true, false }, // STE + { NOG, rwww, M680X_REG_F, NOR, true, false }, // STF + { NOG, uuuu, NOR, NOR, false, false }, // STOP + { NOG, rwww, M680X_REG_HX, NOR, true, false }, // STHX + { NOG, rwww, M680X_REG_Q, NOR, true, false }, // STQ + { NOG, rwww, M680X_REG_S, NOR, true, false }, // STS + { NOG, rwww, M680X_REG_U, NOR, true, false }, // STU + { NOG, rwww, M680X_REG_W, NOR, true, false }, // STW + { NOG, rwww, M680X_REG_X, NOR, true, false }, // STX + { NOG, rwww, M680X_REG_Y, NOR, true, false }, // STY + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUB + { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUBA + { NOG, mrrr, M680X_REG_B, NOR, true, false }, // SUBB + { NOG, mrrr, M680X_REG_D, NOR, true, false }, // SUBD + { NOG, mrrr, M680X_REG_E, NOR, true, false }, // SUBE + { NOG, mrrr, M680X_REG_F, NOR, true, false }, // SUBF + { NOG, rmmm, NOR, NOR, true, false }, // SUBR + { NOG, mrrr, M680X_REG_W, NOR, true, false }, // SUBW + { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI + { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI2 + { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI3 + { NOG, uuuu, NOR, NOR, false, false }, // SYNC + { NOG, rwww, M680X_REG_A, M680X_REG_B, true, false }, // TAB + { NOG, rwww, M680X_REG_A, M680X_REG_CC, false, false }, // TAP + { NOG, rwww, M680X_REG_A, M680X_REG_X, false, false }, // TAX + { NOG, rwww, M680X_REG_B, M680X_REG_A, true, false }, // TBA + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBEQ + { NOG, rmmm, NOR, NOR, true, true }, // TBL + { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBNE + { NOG, uuuu, NOR, NOR, false, false }, // TEST + { NOG, rwww, NOR, NOR, false, false }, // TFM + { NOG, rwww, NOR, NOR, false, false }, // TFR + { NOG, rrrr, NOR, NOR, true, false }, // TIM + { NOG, rwww, M680X_REG_CC, M680X_REG_A, false, false }, // TPA + { NOG, rrrr, NOR, NOR, true, false }, // TST + { NOG, rrrr, M680X_REG_A, NOR, true, false }, // TSTA + { NOG, rrrr, M680X_REG_B, NOR, true, false }, // TSTB + { NOG, rrrr, M680X_REG_D, NOR, true, false }, // TSTD + { NOG, rrrr, M680X_REG_E, NOR, true, false }, // TSTE + { NOG, rrrr, M680X_REG_F, NOR, true, false }, // TSTF + { NOG, rrrr, M680X_REG_W, NOR, true, false }, // TSTW + { NOG, rrrr, M680X_REG_X, NOR, true, false }, // TSTX + { NOG, rwww, M680X_REG_S, M680X_REG_HX, false, false }, // TSX + { NOG, rwww, M680X_REG_S, M680X_REG_Y, false, false }, // TSY + { NOG, rwww, M680X_REG_X, M680X_REG_A, false, false }, // TXA + { NOG, rwww, M680X_REG_HX, M680X_REG_S, false, false }, // TXS + { NOG, rwww, M680X_REG_Y, M680X_REG_S, false, false }, // TYS + { NOG, mrrr, NOR, NOR, true, true }, // WAI + { NOG, uuuu, NOR, NOR, true, false }, // WAIT + { NOG, uuuu, NOR, NOR, true, true }, // WAV + { NOG, uuuu, NOR, NOR, true, true }, // WAVR + { NOG, mmmm, M680X_REG_D, M680X_REG_X, false, false }, // XGDX + { NOG, mmmm, M680X_REG_D, M680X_REG_Y, false, false }, // XGDY +}; +#undef NOR +#undef NOG + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6800.inc b/white_patch_detect/capstone-master/arch/M680X/m6800.inc new file mode 100644 index 0000000..b100aa3 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6800.inc @@ -0,0 +1,277 @@ + +// M6800/2 instructions +static const inst_page1 g_m6800_inst_page1_table[256] = { + // 0x0x, inherent instructions + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_NOP, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_TAP, inh_hid, inh_hid }, + { M680X_INS_TPA, inh_hid, inh_hid }, + { M680X_INS_INX, inh_hid, inh_hid }, + { M680X_INS_DEX, inh_hid, inh_hid }, + { M680X_INS_CLV, inh_hid, inh_hid }, + { M680X_INS_SEV, inh_hid, inh_hid }, + { M680X_INS_CLC, inh_hid, inh_hid }, + { M680X_INS_SEC, inh_hid, inh_hid }, + { M680X_INS_CLI, inh_hid, inh_hid }, + { M680X_INS_SEI, inh_hid, inh_hid }, + // 0x1x, inherent instructions + { M680X_INS_SBA, inh_hid, inh_hid }, + { M680X_INS_CBA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_TAB, inh_hid, inh_hid }, + { M680X_INS_TBA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_DAA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ABA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0x2x, relative branch instructions + { M680X_INS_BRA, rel8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_BHI, rel8_hid, inh_hid }, + { M680X_INS_BLS, rel8_hid, inh_hid }, + { M680X_INS_BCC, rel8_hid, inh_hid }, + { M680X_INS_BCS, rel8_hid, inh_hid }, + { M680X_INS_BNE, rel8_hid, inh_hid }, + { M680X_INS_BEQ, rel8_hid, inh_hid }, + { M680X_INS_BVC, rel8_hid, inh_hid }, + { M680X_INS_BVS, rel8_hid, inh_hid }, + { M680X_INS_BPL, rel8_hid, inh_hid }, + { M680X_INS_BMI, rel8_hid, inh_hid }, + { M680X_INS_BGE, rel8_hid, inh_hid }, + { M680X_INS_BLT, rel8_hid, inh_hid }, + { M680X_INS_BGT, rel8_hid, inh_hid }, + { M680X_INS_BLE, rel8_hid, inh_hid }, + // 0x3x, inherent instructions + { M680X_INS_TSX, inh_hid, inh_hid }, + { M680X_INS_INS, inh_hid, inh_hid }, + { M680X_INS_PULA, inh_hid, inh_hid }, + { M680X_INS_PULB, inh_hid, inh_hid }, + { M680X_INS_DES, inh_hid, inh_hid }, + { M680X_INS_TXS, inh_hid, inh_hid }, + { M680X_INS_PSHA, inh_hid, inh_hid }, + { M680X_INS_PSHB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RTS, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RTI, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_WAI, inh_hid, inh_hid }, + { M680X_INS_SWI, inh_hid, inh_hid }, + // 0x4x, Register A instructions + { M680X_INS_NEGA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COMA, inh_hid, inh_hid }, + { M680X_INS_LSRA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORA, inh_hid, inh_hid }, + { M680X_INS_ASRA, inh_hid, inh_hid }, + { M680X_INS_ASLA, inh_hid, inh_hid }, + { M680X_INS_ROLA, inh_hid, inh_hid }, + { M680X_INS_DECA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCA, inh_hid, inh_hid }, + { M680X_INS_TSTA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRA, inh_hid, inh_hid }, + // 0x5x, Register B instructions + { M680X_INS_NEGB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COMB, inh_hid, inh_hid }, + { M680X_INS_LSRB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORB, inh_hid, inh_hid }, + { M680X_INS_ASRB, inh_hid, inh_hid }, + { M680X_INS_ASLB, inh_hid, inh_hid }, + { M680X_INS_ROLB, inh_hid, inh_hid }, + { M680X_INS_DECB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCB, inh_hid, inh_hid }, + { M680X_INS_TSTB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRB, inh_hid, inh_hid }, + // 0x6x, indexed instructions + { M680X_INS_NEG, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, idxX_hid, inh_hid }, + { M680X_INS_LSR, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, idxX_hid, inh_hid }, + { M680X_INS_ASR, idxX_hid, inh_hid }, + { M680X_INS_ASL, idxX_hid, inh_hid }, + { M680X_INS_ROL, idxX_hid, inh_hid }, + { M680X_INS_DEC, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, idxX_hid, inh_hid }, + { M680X_INS_TST, idxX_hid, inh_hid }, + { M680X_INS_JMP, idxX_hid, inh_hid }, + { M680X_INS_CLR, idxX_hid, inh_hid }, + // 0x7x, extended instructions + { M680X_INS_NEG, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, ext_hid, inh_hid }, + { M680X_INS_LSR, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, ext_hid, inh_hid }, + { M680X_INS_ASR, ext_hid, inh_hid }, + { M680X_INS_ASL, ext_hid, inh_hid }, + { M680X_INS_ROL, ext_hid, inh_hid }, + { M680X_INS_DEC, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, ext_hid, inh_hid }, + { M680X_INS_TST, ext_hid, inh_hid }, + { M680X_INS_JMP, ext_hid, inh_hid }, + { M680X_INS_CLR, ext_hid, inh_hid }, + // 0x8x, immediate instructions with Register A,X,S + { M680X_INS_SUBA, imm8_hid, inh_hid }, + { M680X_INS_CMPA, imm8_hid, inh_hid }, + { M680X_INS_SBCA, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDA, imm8_hid, inh_hid }, + { M680X_INS_BITA, imm8_hid, inh_hid }, + { M680X_INS_LDAA, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_EORA, imm8_hid, inh_hid }, + { M680X_INS_ADCA, imm8_hid, inh_hid }, + { M680X_INS_ORAA, imm8_hid, inh_hid }, + { M680X_INS_ADDA, imm8_hid, inh_hid }, + { M680X_INS_CPX, imm16_hid, inh_hid }, + { M680X_INS_BSR, rel8_hid, inh_hid }, + { M680X_INS_LDS, imm16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0x9x, direct instructions with register A,X,S + { M680X_INS_SUBA, dir_hid, inh_hid }, + { M680X_INS_CMPA, dir_hid, inh_hid }, + { M680X_INS_SBCA, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDA, dir_hid, inh_hid }, + { M680X_INS_BITA, dir_hid, inh_hid }, + { M680X_INS_LDAA, dir_hid, inh_hid }, + { M680X_INS_STAA, dir_hid, inh_hid }, + { M680X_INS_EORA, dir_hid, inh_hid }, + { M680X_INS_ADCA, dir_hid, inh_hid }, + { M680X_INS_ORAA, dir_hid, inh_hid }, + { M680X_INS_ADDA, dir_hid, inh_hid }, + { M680X_INS_CPX, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDS, dir_hid, inh_hid }, + { M680X_INS_STS, dir_hid, inh_hid }, + // 0xAx, indexed instructions with Register A,X + { M680X_INS_SUBA, idxX_hid, inh_hid }, + { M680X_INS_CMPA, idxX_hid, inh_hid }, + { M680X_INS_SBCA, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDA, idxX_hid, inh_hid }, + { M680X_INS_BITA, idxX_hid, inh_hid }, + { M680X_INS_LDAA, idxX_hid, inh_hid }, + { M680X_INS_STAA, idxX_hid, inh_hid }, + { M680X_INS_EORA, idxX_hid, inh_hid }, + { M680X_INS_ADCA, idxX_hid, inh_hid }, + { M680X_INS_ORAA, idxX_hid, inh_hid }, + { M680X_INS_ADDA, idxX_hid, inh_hid }, + { M680X_INS_CPX, idxX_hid, inh_hid }, + { M680X_INS_JSR, idxX_hid, inh_hid }, + { M680X_INS_LDS, idxX_hid, inh_hid }, + { M680X_INS_STS, idxX_hid, inh_hid }, + // 0xBx, extended instructions with register A,X,S + { M680X_INS_SUBA, ext_hid, inh_hid }, + { M680X_INS_CMPA, ext_hid, inh_hid }, + { M680X_INS_SBCA, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDA, ext_hid, inh_hid }, + { M680X_INS_BITA, ext_hid, inh_hid }, + { M680X_INS_LDAA, ext_hid, inh_hid }, + { M680X_INS_STAA, ext_hid, inh_hid }, + { M680X_INS_EORA, ext_hid, inh_hid }, + { M680X_INS_ADCA, ext_hid, inh_hid }, + { M680X_INS_ORAA, ext_hid, inh_hid }, + { M680X_INS_ADDA, ext_hid, inh_hid }, + { M680X_INS_CPX, ext_hid, inh_hid }, + { M680X_INS_JSR, ext_hid, inh_hid }, + { M680X_INS_LDS, ext_hid, inh_hid }, + { M680X_INS_STS, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register B,X + { M680X_INS_SUBB, imm8_hid, inh_hid }, + { M680X_INS_CMPB, imm8_hid, inh_hid }, + { M680X_INS_SBCB, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDB, imm8_hid, inh_hid }, + { M680X_INS_BITB, imm8_hid, inh_hid }, + { M680X_INS_LDAB, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_EORB, imm8_hid, inh_hid }, + { M680X_INS_ADCB, imm8_hid, inh_hid }, + { M680X_INS_ORAB, imm8_hid, inh_hid }, + { M680X_INS_ADDB, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDX, imm16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0xDx direct instructions with register B,X + { M680X_INS_SUBB, dir_hid, inh_hid }, + { M680X_INS_CMPB, dir_hid, inh_hid }, + { M680X_INS_SBCB, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDB, dir_hid, inh_hid }, + { M680X_INS_BITB, dir_hid, inh_hid }, + { M680X_INS_LDAB, dir_hid, inh_hid }, + { M680X_INS_STAB, dir_hid, inh_hid }, + { M680X_INS_EORB, dir_hid, inh_hid }, + { M680X_INS_ADCB, dir_hid, inh_hid }, + { M680X_INS_ORAB, dir_hid, inh_hid }, + { M680X_INS_ADDB, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDX, dir_hid, inh_hid }, + { M680X_INS_STX, dir_hid, inh_hid }, + // 0xEx, indexed instruction with register B,X + { M680X_INS_SUBB, idxX_hid, inh_hid }, + { M680X_INS_CMPB, idxX_hid, inh_hid }, + { M680X_INS_SBCB, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDB, idxX_hid, inh_hid }, + { M680X_INS_BITB, idxX_hid, inh_hid }, + { M680X_INS_LDAB, idxX_hid, inh_hid }, + { M680X_INS_STAB, idxX_hid, inh_hid }, + { M680X_INS_EORB, idxX_hid, inh_hid }, + { M680X_INS_ADCB, idxX_hid, inh_hid }, + { M680X_INS_ORAB, idxX_hid, inh_hid }, + { M680X_INS_ADDB, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDX, idxX_hid, inh_hid }, + { M680X_INS_STX, idxX_hid, inh_hid }, + // 0xFx, extended instructions with register B,U + { M680X_INS_SUBB, ext_hid, inh_hid }, + { M680X_INS_CMPB, ext_hid, inh_hid }, + { M680X_INS_SBCB, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDB, ext_hid, inh_hid }, + { M680X_INS_BITB, ext_hid, inh_hid }, + { M680X_INS_LDAB, ext_hid, inh_hid }, + { M680X_INS_STAB, ext_hid, inh_hid }, + { M680X_INS_EORB, ext_hid, inh_hid }, + { M680X_INS_ADCB, ext_hid, inh_hid }, + { M680X_INS_ORAB, ext_hid, inh_hid }, + { M680X_INS_ADDB, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDX, ext_hid, inh_hid }, + { M680X_INS_STX, ext_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6801.inc b/white_patch_detect/capstone-master/arch/M680X/m6801.inc new file mode 100644 index 0000000..0fe4592 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6801.inc @@ -0,0 +1,39 @@ + +// Additional instructions only supported on M6801/3 +static const inst_pageX g_m6801_inst_overlay_table[] = { + // 0x0x, inherent instructions + { 0x04, M680X_INS_LSRD, inh_hid, inh_hid }, + { 0x05, M680X_INS_ASLD, inh_hid, inh_hid }, + // 0x2x, relative branch instructions + { 0x21, M680X_INS_BRN, rel8_hid, inh_hid }, + // 0x3x, inherent instructions + { 0x38, M680X_INS_PULX, inh_hid, inh_hid }, + { 0x3A, M680X_INS_ABX, inh_hid, inh_hid }, + { 0x3C, M680X_INS_PSHX, inh_hid, inh_hid }, + { 0x3D, M680X_INS_MUL, inh_hid, inh_hid }, + // 0x8x, immediate instructions with Register D + { 0x83, M680X_INS_SUBD, imm16_hid, inh_hid }, + // 0x9x, direct instructions with register D + { 0x93, M680X_INS_SUBD, dir_hid, inh_hid }, + { 0x9D, M680X_INS_JSR, dir_hid, inh_hid }, + // 0xAx, indexed instructions with Register D + { 0xA3, M680X_INS_SUBD, idxX_hid, inh_hid }, + // 0xBx, extended instructions with register D + { 0xB3, M680X_INS_SUBD, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register D + { 0xC3, M680X_INS_ADDD, imm16_hid, inh_hid }, + { 0xCC, M680X_INS_LDD, imm16_hid, inh_hid }, + // 0xDx direct instructions with register D + { 0xD3, M680X_INS_ADDD, dir_hid, inh_hid }, + { 0xDC, M680X_INS_LDD, dir_hid, inh_hid }, + { 0xDD, M680X_INS_STD, dir_hid, inh_hid }, + // 0xEx, indexed instruction with register D + { 0xE3, M680X_INS_ADDD, idxX_hid, inh_hid }, + { 0xEC, M680X_INS_LDD, idxX_hid, inh_hid }, + { 0xED, M680X_INS_STD, idxX_hid, inh_hid }, + // 0xFx, extended instructions with register D + { 0xF3, M680X_INS_ADDD, ext_hid, inh_hid }, + { 0xFC, M680X_INS_LDD, ext_hid, inh_hid }, + { 0xFD, M680X_INS_STD, ext_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6805.inc b/white_patch_detect/capstone-master/arch/M680X/m6805.inc new file mode 100644 index 0000000..080c140 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6805.inc @@ -0,0 +1,277 @@ + +// M68HC05 instructions +static const inst_page1 g_m6805_inst_page1_table[256] = { + // 0x0x, bit manipulation instructions + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + { M680X_INS_BRSET, opidxdr_hid, inh_hid }, + { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, + // 0x1x, bit set/clear instructions + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + { M680X_INS_BCLR, opidx_hid, dir_hid }, + { M680X_INS_BSET, opidx_hid, dir_hid }, + // 0x2x, relative branch instructions + { M680X_INS_BRA, rel8_hid, inh_hid }, + { M680X_INS_BRN, rel8_hid, inh_hid }, + { M680X_INS_BHI, rel8_hid, inh_hid }, + { M680X_INS_BLS, rel8_hid, inh_hid }, + { M680X_INS_BCC, rel8_hid, inh_hid }, + { M680X_INS_BCS, rel8_hid, inh_hid }, + { M680X_INS_BNE, rel8_hid, inh_hid }, + { M680X_INS_BEQ, rel8_hid, inh_hid }, + { M680X_INS_BHCC, rel8_hid, inh_hid }, + { M680X_INS_BHCS, rel8_hid, inh_hid }, + { M680X_INS_BPL, rel8_hid, inh_hid }, + { M680X_INS_BMI, rel8_hid, inh_hid }, + { M680X_INS_BMC, rel8_hid, inh_hid }, + { M680X_INS_BMS, rel8_hid, inh_hid }, + { M680X_INS_BIL, rel8_hid, inh_hid }, + { M680X_INS_BIH, rel8_hid, inh_hid }, + // 0x3x, direct instructions + { M680X_INS_NEG, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, dir_hid, inh_hid }, + { M680X_INS_LSR, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, dir_hid, inh_hid }, + { M680X_INS_ASR, dir_hid, inh_hid }, + { M680X_INS_LSL, dir_hid, inh_hid }, + { M680X_INS_ROL, dir_hid, inh_hid }, + { M680X_INS_DEC, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, dir_hid, inh_hid }, + { M680X_INS_TST, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLR, dir_hid, inh_hid }, + // 0x4x, inherent instructions + { M680X_INS_NEGA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_MUL, inh_hid, inh_hid }, + { M680X_INS_COMA, inh_hid, inh_hid }, + { M680X_INS_LSRA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORA, inh_hid, inh_hid }, + { M680X_INS_ASRA, inh_hid, inh_hid }, + { M680X_INS_LSLA, inh_hid, inh_hid }, + { M680X_INS_ROLA, inh_hid, inh_hid }, + { M680X_INS_DECA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCA, inh_hid, inh_hid }, + { M680X_INS_TSTA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRA, inh_hid, inh_hid }, + // 0x5x, inherent instructions + { M680X_INS_NEGX, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COMX, inh_hid, inh_hid }, + { M680X_INS_LSRX, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORX, inh_hid, inh_hid }, + { M680X_INS_ASRX, inh_hid, inh_hid }, + { M680X_INS_LSLX, inh_hid, inh_hid }, + { M680X_INS_ROLX, inh_hid, inh_hid }, + { M680X_INS_DECX, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCX, inh_hid, inh_hid }, + { M680X_INS_TSTX, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRX, inh_hid, inh_hid }, + // 0x6x, indexed, 1 byte offset instructions + { M680X_INS_NEG, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, idxX_hid, inh_hid }, + { M680X_INS_LSR, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, idxX_hid, inh_hid }, + { M680X_INS_ASR, idxX_hid, inh_hid }, + { M680X_INS_LSL, idxX_hid, inh_hid }, + { M680X_INS_ROL, idxX_hid, inh_hid }, + { M680X_INS_DEC, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, idxX_hid, inh_hid }, + { M680X_INS_TST, idxX_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLR, idxX_hid, inh_hid }, + // 0x7x, indexed, no offset instructions + { M680X_INS_NEG, idxX0_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, idxX0_hid, inh_hid }, + { M680X_INS_LSR, idxX0_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, idxX0_hid, inh_hid }, + { M680X_INS_ASR, idxX0_hid, inh_hid }, + { M680X_INS_LSL, idxX0_hid, inh_hid }, + { M680X_INS_ROL, idxX0_hid, inh_hid }, + { M680X_INS_DEC, idxX0_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, idxX0_hid, inh_hid }, + { M680X_INS_TST, idxX0_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLR, idxX0_hid, inh_hid }, + // 0x8x, inherent instructions + { M680X_INS_RTI, inh_hid, inh_hid }, + { M680X_INS_RTS, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_SWI, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_STOP, inh_hid, inh_hid }, + { M680X_INS_WAIT, inh_hid, inh_hid }, + // 0x9x, inherent instructions + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_TAX, inh_hid, inh_hid }, + { M680X_INS_CLC, inh_hid, inh_hid }, + { M680X_INS_SEC, inh_hid, inh_hid }, + { M680X_INS_CLI, inh_hid, inh_hid }, + { M680X_INS_SEI, inh_hid, inh_hid }, + { M680X_INS_RSP, inh_hid, inh_hid }, + { M680X_INS_NOP, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_TXA, inh_hid, inh_hid }, + // 0xAx, immediate instructions with reg. A + { M680X_INS_SUB, imm8_hid, inh_hid }, + { M680X_INS_CMP, imm8_hid, inh_hid }, + { M680X_INS_SBC, imm8_hid, inh_hid }, + { M680X_INS_CPX, imm8_hid, inh_hid }, + { M680X_INS_AND, imm8_hid, inh_hid }, + { M680X_INS_BIT, imm8_hid, inh_hid }, + { M680X_INS_LDA, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_EOR, imm8_hid, inh_hid }, + { M680X_INS_ADC, imm8_hid, inh_hid }, + { M680X_INS_ORA, imm8_hid, inh_hid }, + { M680X_INS_ADD, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_BSR, rel8_hid, inh_hid }, + { M680X_INS_LDX, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0xBx, direct instructions with reg. A + { M680X_INS_SUB, dir_hid, inh_hid }, + { M680X_INS_CMP, dir_hid, inh_hid }, + { M680X_INS_SBC, dir_hid, inh_hid }, + { M680X_INS_CPX, dir_hid, inh_hid }, + { M680X_INS_AND, dir_hid, inh_hid }, + { M680X_INS_BIT, dir_hid, inh_hid }, + { M680X_INS_LDA, dir_hid, inh_hid }, + { M680X_INS_STA, dir_hid, inh_hid }, + { M680X_INS_EOR, dir_hid, inh_hid }, + { M680X_INS_ADC, dir_hid, inh_hid }, + { M680X_INS_ORA, dir_hid, inh_hid }, + { M680X_INS_ADD, dir_hid, inh_hid }, + { M680X_INS_JMP, dir_hid, inh_hid }, + { M680X_INS_JSR, dir_hid, inh_hid }, + { M680X_INS_LDX, dir_hid, inh_hid }, + { M680X_INS_STX, dir_hid, inh_hid }, + // 0xCx, extended instructions with reg. A + { M680X_INS_SUB, ext_hid, inh_hid }, + { M680X_INS_CMP, ext_hid, inh_hid }, + { M680X_INS_SBC, ext_hid, inh_hid }, + { M680X_INS_CPX, ext_hid, inh_hid }, + { M680X_INS_AND, ext_hid, inh_hid }, + { M680X_INS_BIT, ext_hid, inh_hid }, + { M680X_INS_LDA, ext_hid, inh_hid }, + { M680X_INS_STA, ext_hid, inh_hid }, + { M680X_INS_EOR, ext_hid, inh_hid }, + { M680X_INS_ADC, ext_hid, inh_hid }, + { M680X_INS_ORA, ext_hid, inh_hid }, + { M680X_INS_ADD, ext_hid, inh_hid }, + { M680X_INS_JMP, ext_hid, inh_hid }, + { M680X_INS_JSR, ext_hid, inh_hid }, + { M680X_INS_LDX, ext_hid, inh_hid }, + { M680X_INS_STX, ext_hid, inh_hid }, + // 0xDx, indexed with 2 byte offset instructions with reg. A + { M680X_INS_SUB, idxX16_hid, inh_hid }, + { M680X_INS_CMP, idxX16_hid, inh_hid }, + { M680X_INS_SBC, idxX16_hid, inh_hid }, + { M680X_INS_CPX, idxX16_hid, inh_hid }, + { M680X_INS_AND, idxX16_hid, inh_hid }, + { M680X_INS_BIT, idxX16_hid, inh_hid }, + { M680X_INS_LDA, idxX16_hid, inh_hid }, + { M680X_INS_STA, idxX16_hid, inh_hid }, + { M680X_INS_EOR, idxX16_hid, inh_hid }, + { M680X_INS_ADC, idxX16_hid, inh_hid }, + { M680X_INS_ORA, idxX16_hid, inh_hid }, + { M680X_INS_ADD, idxX16_hid, inh_hid }, + { M680X_INS_JMP, idxX16_hid, inh_hid }, + { M680X_INS_JSR, idxX16_hid, inh_hid }, + { M680X_INS_LDX, idxX16_hid, inh_hid }, + { M680X_INS_STX, idxX16_hid, inh_hid }, + // 0xEx, indexed with 1 byte offset instructions with reg. A + { M680X_INS_SUB, idxX_hid, inh_hid }, + { M680X_INS_CMP, idxX_hid, inh_hid }, + { M680X_INS_SBC, idxX_hid, inh_hid }, + { M680X_INS_CPX, idxX_hid, inh_hid }, + { M680X_INS_AND, idxX_hid, inh_hid }, + { M680X_INS_BIT, idxX_hid, inh_hid }, + { M680X_INS_LDA, idxX_hid, inh_hid }, + { M680X_INS_STA, idxX_hid, inh_hid }, + { M680X_INS_EOR, idxX_hid, inh_hid }, + { M680X_INS_ADC, idxX_hid, inh_hid }, + { M680X_INS_ORA, idxX_hid, inh_hid }, + { M680X_INS_ADD, idxX_hid, inh_hid }, + { M680X_INS_JMP, idxX_hid, inh_hid }, + { M680X_INS_JSR, idxX_hid, inh_hid }, + { M680X_INS_LDX, idxX_hid, inh_hid }, + { M680X_INS_STX, idxX_hid, inh_hid }, + // 0xFx, indexed without offset instructions with reg. A + { M680X_INS_SUB, idxX0_hid, inh_hid }, + { M680X_INS_CMP, idxX0_hid, inh_hid }, + { M680X_INS_SBC, idxX0_hid, inh_hid }, + { M680X_INS_CPX, idxX0_hid, inh_hid }, + { M680X_INS_AND, idxX0_hid, inh_hid }, + { M680X_INS_BIT, idxX0_hid, inh_hid }, + { M680X_INS_LDA, idxX0_hid, inh_hid }, + { M680X_INS_STA, idxX0_hid, inh_hid }, + { M680X_INS_EOR, idxX0_hid, inh_hid }, + { M680X_INS_ADC, idxX0_hid, inh_hid }, + { M680X_INS_ORA, idxX0_hid, inh_hid }, + { M680X_INS_ADD, idxX0_hid, inh_hid }, + { M680X_INS_JMP, idxX0_hid, inh_hid }, + { M680X_INS_JSR, idxX0_hid, inh_hid }, + { M680X_INS_LDX, idxX0_hid, inh_hid }, + { M680X_INS_STX, idxX0_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6808.inc b/white_patch_detect/capstone-master/arch/M680X/m6808.inc new file mode 100644 index 0000000..6114f3c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6808.inc @@ -0,0 +1,91 @@ + +// Additional instructions only supported on M68HC08 +static const inst_pageX g_m6808_inst_overlay_table[] = { + { 0x31, M680X_INS_CBEQ, dir_hid, rel8_hid }, + { 0x35, M680X_INS_STHX, dir_hid, inh_hid }, + { 0x3b, M680X_INS_DBNZ, dir_hid, rel8_hid }, + { 0x41, M680X_INS_CBEQA, imm8rel_hid, inh_hid }, + { 0x45, M680X_INS_LDHX, imm16_hid, inh_hid }, + { 0x4b, M680X_INS_DBNZA, rel8_hid, inh_hid }, + { 0x4e, M680X_INS_MOV, dir_hid, dir_hid }, + { 0x51, M680X_INS_CBEQX, imm8rel_hid, inh_hid }, + { 0x52, M680X_INS_DIV, inh_hid, inh_hid }, + { 0x55, M680X_INS_LDHX, dir_hid, inh_hid }, + { 0x5b, M680X_INS_DBNZX, rel8_hid, inh_hid }, + { 0x5e, M680X_INS_MOV, dir_hid, idxX0p_hid }, + { 0x61, M680X_INS_CBEQ, idxXp_hid, rel8_hid }, + { 0x62, M680X_INS_NSA, inh_hid, inh_hid }, + { 0x65, M680X_INS_CPHX, imm16_hid, inh_hid }, + { 0x6b, M680X_INS_DBNZ, idxX_hid, rel8_hid }, + { 0x6e, M680X_INS_MOV, imm8_hid, dir_hid }, + { 0x71, M680X_INS_CBEQ, idxX0p_hid, rel8_hid }, + { 0x72, M680X_INS_DAA, inh_hid, inh_hid }, + { 0x75, M680X_INS_CPHX, dir_hid, inh_hid }, + { 0x7b, M680X_INS_DBNZ, idxX0_hid, rel8_hid }, + { 0x7e, M680X_INS_MOV, idxX0p_hid, dir_hid }, + { 0x84, M680X_INS_TAP, inh_hid, inh_hid }, + { 0x85, M680X_INS_TPA, inh_hid, inh_hid }, + { 0x86, M680X_INS_PULA, inh_hid, inh_hid }, + { 0x87, M680X_INS_PSHA, inh_hid, inh_hid }, + { 0x88, M680X_INS_PULX, inh_hid, inh_hid }, + { 0x89, M680X_INS_PSHX, inh_hid, inh_hid }, + { 0x8a, M680X_INS_PULH, inh_hid, inh_hid }, + { 0x8b, M680X_INS_PSHH, inh_hid, inh_hid }, + { 0x8c, M680X_INS_CLRH, inh_hid, inh_hid }, + { 0x90, M680X_INS_BGE, rel8_hid, inh_hid }, + { 0x91, M680X_INS_BLT, rel8_hid, inh_hid }, + { 0x92, M680X_INS_BGT, rel8_hid, inh_hid }, + { 0x93, M680X_INS_BLE, rel8_hid, inh_hid }, + { 0x94, M680X_INS_TXS, inh_hid, inh_hid }, + { 0x95, M680X_INS_TSX, inh_hid, inh_hid }, + { 0x97, M680X_INS_TAX, inh_hid, inh_hid }, + { 0x9f, M680X_INS_TXA, inh_hid, inh_hid }, + { 0xa7, M680X_INS_AIS, imm8_hid, inh_hid }, + { 0xaf, M680X_INS_AIX, imm8_hid, inh_hid }, +}; + +// M68HC08 PAGE2 instructions (prefix 0x9E) +static const inst_pageX g_m6808_inst_page2_table[] = { + { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, + { 0x61, M680X_INS_CBEQ, idxS_hid, rel8_hid }, + { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, + { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, + { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, + { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, + { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, + { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, + { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, + { 0x6b, M680X_INS_DBNZ, idxS_hid, rel8_hid }, + { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, + { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, + { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, + { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, + { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, + { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, + { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, + { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, + { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, + { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, + { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, + { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, + { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, + { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, + { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, + { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, + { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, + { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, + { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, + { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, + { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, + { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, + { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, + { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, + { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, + { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, + { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, + { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, + { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, + { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, + { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6809.inc b/white_patch_detect/capstone-master/arch/M680X/m6809.inc new file mode 100644 index 0000000..24f0260 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6809.inc @@ -0,0 +1,352 @@ + +// M6809/HD6309 PAGE1 instructions +static const inst_page1 g_m6809_inst_page1_table[256] = { + // 0x0x, direct instructions + { M680X_INS_NEG, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, dir_hid, inh_hid }, + { M680X_INS_LSR, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, dir_hid, inh_hid }, + { M680X_INS_ASR, dir_hid, inh_hid }, + { M680X_INS_LSL, dir_hid, inh_hid }, + { M680X_INS_ROL, dir_hid, inh_hid }, + { M680X_INS_DEC, dir_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, dir_hid, inh_hid }, + { M680X_INS_TST, dir_hid, inh_hid }, + { M680X_INS_JMP, dir_hid, inh_hid }, + { M680X_INS_CLR, dir_hid, inh_hid }, + // 0x1x, misc instructions + { M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE2 + { M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE3 + { M680X_INS_NOP, inh_hid, inh_hid }, + { M680X_INS_SYNC, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LBRA, rel16_hid, inh_hid }, + { M680X_INS_LBSR, rel16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_DAA, inh_hid, inh_hid }, + { M680X_INS_ORCC, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ANDCC, imm8_hid, inh_hid }, + { M680X_INS_SEX, inh_hid, inh_hid }, + { M680X_INS_EXG, rr09_hid, inh_hid }, + { M680X_INS_TFR, rr09_hid, inh_hid }, + // 0x2x, relative branch instructions + { M680X_INS_BRA, rel8_hid, inh_hid }, + { M680X_INS_BRN, rel8_hid, inh_hid }, + { M680X_INS_BHI, rel8_hid, inh_hid }, + { M680X_INS_BLS, rel8_hid, inh_hid }, + { M680X_INS_BCC, rel8_hid, inh_hid }, + { M680X_INS_BCS, rel8_hid, inh_hid }, + { M680X_INS_BNE, rel8_hid, inh_hid }, + { M680X_INS_BEQ, rel8_hid, inh_hid }, + { M680X_INS_BVC, rel8_hid, inh_hid }, + { M680X_INS_BVS, rel8_hid, inh_hid }, + { M680X_INS_BPL, rel8_hid, inh_hid }, + { M680X_INS_BMI, rel8_hid, inh_hid }, + { M680X_INS_BGE, rel8_hid, inh_hid }, + { M680X_INS_BLT, rel8_hid, inh_hid }, + { M680X_INS_BGT, rel8_hid, inh_hid }, + { M680X_INS_BLE, rel8_hid, inh_hid }, + // 0x3x, misc instructions + { M680X_INS_LEAX, idx09_hid, inh_hid }, + { M680X_INS_LEAY, idx09_hid, inh_hid }, + { M680X_INS_LEAS, idx09_hid, inh_hid }, + { M680X_INS_LEAU, idx09_hid, inh_hid }, + { M680X_INS_PSHS, rbits_hid, inh_hid }, + { M680X_INS_PULS, rbits_hid, inh_hid }, + { M680X_INS_PSHU, rbits_hid, inh_hid }, + { M680X_INS_PULU, rbits_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RTS, inh_hid, inh_hid }, + { M680X_INS_ABX, inh_hid, inh_hid }, + { M680X_INS_RTI, inh_hid, inh_hid }, + { M680X_INS_CWAI, imm8_hid, inh_hid }, + { M680X_INS_MUL, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_SWI, inh_hid, inh_hid }, + // 0x4x, Register A instructions + { M680X_INS_NEGA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COMA, inh_hid, inh_hid }, + { M680X_INS_LSRA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORA, inh_hid, inh_hid }, + { M680X_INS_ASRA, inh_hid, inh_hid }, + { M680X_INS_LSLA, inh_hid, inh_hid }, + { M680X_INS_ROLA, inh_hid, inh_hid }, + { M680X_INS_DECA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCA, inh_hid, inh_hid }, + { M680X_INS_TSTA, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRA, inh_hid, inh_hid }, + // 0x5x, Register B instructions + { M680X_INS_NEGB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COMB, inh_hid, inh_hid }, + { M680X_INS_LSRB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_RORB, inh_hid, inh_hid }, + { M680X_INS_ASRB, inh_hid, inh_hid }, + { M680X_INS_LSLB, inh_hid, inh_hid }, + { M680X_INS_ROLB, inh_hid, inh_hid }, + { M680X_INS_DECB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INCB, inh_hid, inh_hid }, + { M680X_INS_TSTB, inh_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_CLRB, inh_hid, inh_hid }, + // 0x6x, indexed instructions + { M680X_INS_NEG, idx09_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, idx09_hid, inh_hid }, + { M680X_INS_LSR, idx09_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, idx09_hid, inh_hid }, + { M680X_INS_ASR, idx09_hid, inh_hid }, + { M680X_INS_LSL, idx09_hid, inh_hid }, + { M680X_INS_ROL, idx09_hid, inh_hid }, + { M680X_INS_DEC, idx09_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, idx09_hid, inh_hid }, + { M680X_INS_TST, idx09_hid, inh_hid }, + { M680X_INS_JMP, idx09_hid, inh_hid }, + { M680X_INS_CLR, idx09_hid, inh_hid }, + // 0x7x, extended instructions + { M680X_INS_NEG, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_COM, ext_hid, inh_hid }, + { M680X_INS_LSR, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_ROR, ext_hid, inh_hid }, + { M680X_INS_ASR, ext_hid, inh_hid }, + { M680X_INS_LSL, ext_hid, inh_hid }, + { M680X_INS_ROL, ext_hid, inh_hid }, + { M680X_INS_DEC, ext_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_INC, ext_hid, inh_hid }, + { M680X_INS_TST, ext_hid, inh_hid }, + { M680X_INS_JMP, ext_hid, inh_hid }, + { M680X_INS_CLR, ext_hid, inh_hid }, + // 0x8x, immediate instructions with Register A,D,X + { M680X_INS_SUBA, imm8_hid, inh_hid }, + { M680X_INS_CMPA, imm8_hid, inh_hid }, + { M680X_INS_SBCA, imm8_hid, inh_hid }, + { M680X_INS_SUBD, imm16_hid, inh_hid }, + { M680X_INS_ANDA, imm8_hid, inh_hid }, + { M680X_INS_BITA, imm8_hid, inh_hid }, + { M680X_INS_LDA, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_EORA, imm8_hid, inh_hid }, + { M680X_INS_ADCA, imm8_hid, inh_hid }, + { M680X_INS_ORA, imm8_hid, inh_hid }, + { M680X_INS_ADDA, imm8_hid, inh_hid }, + { M680X_INS_CMPX, imm16_hid, inh_hid }, + { M680X_INS_BSR, rel8_hid, inh_hid }, + { M680X_INS_LDX, imm16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0x9x, direct instructions with register A,D,X + { M680X_INS_SUBA, dir_hid, inh_hid }, + { M680X_INS_CMPA, dir_hid, inh_hid }, + { M680X_INS_SBCA, dir_hid, inh_hid }, + { M680X_INS_SUBD, dir_hid, inh_hid }, + { M680X_INS_ANDA, dir_hid, inh_hid }, + { M680X_INS_BITA, dir_hid, inh_hid }, + { M680X_INS_LDA, dir_hid, inh_hid }, + { M680X_INS_STA, dir_hid, inh_hid }, + { M680X_INS_EORA, dir_hid, inh_hid }, + { M680X_INS_ADCA, dir_hid, inh_hid }, + { M680X_INS_ORA, dir_hid, inh_hid }, + { M680X_INS_ADDA, dir_hid, inh_hid }, + { M680X_INS_CMPX, dir_hid, inh_hid }, + { M680X_INS_JSR, dir_hid, inh_hid }, + { M680X_INS_LDX, dir_hid, inh_hid }, + { M680X_INS_STX, dir_hid, inh_hid }, + // 0xAx, indexed instructions with Register A,D,X + { M680X_INS_SUBA, idx09_hid, inh_hid }, + { M680X_INS_CMPA, idx09_hid, inh_hid }, + { M680X_INS_SBCA, idx09_hid, inh_hid }, + { M680X_INS_SUBD, idx09_hid, inh_hid }, + { M680X_INS_ANDA, idx09_hid, inh_hid }, + { M680X_INS_BITA, idx09_hid, inh_hid }, + { M680X_INS_LDA, idx09_hid, inh_hid }, + { M680X_INS_STA, idx09_hid, inh_hid }, + { M680X_INS_EORA, idx09_hid, inh_hid }, + { M680X_INS_ADCA, idx09_hid, inh_hid }, + { M680X_INS_ORA, idx09_hid, inh_hid }, + { M680X_INS_ADDA, idx09_hid, inh_hid }, + { M680X_INS_CMPX, idx09_hid, inh_hid }, + { M680X_INS_JSR, idx09_hid, inh_hid }, + { M680X_INS_LDX, idx09_hid, inh_hid }, + { M680X_INS_STX, idx09_hid, inh_hid }, + // 0xBx, extended instructions with register A,D,X + { M680X_INS_SUBA, ext_hid, inh_hid }, + { M680X_INS_CMPA, ext_hid, inh_hid }, + { M680X_INS_SBCA, ext_hid, inh_hid }, + { M680X_INS_SUBD, ext_hid, inh_hid }, + { M680X_INS_ANDA, ext_hid, inh_hid }, + { M680X_INS_BITA, ext_hid, inh_hid }, + { M680X_INS_LDA, ext_hid, inh_hid }, + { M680X_INS_STA, ext_hid, inh_hid }, + { M680X_INS_EORA, ext_hid, inh_hid }, + { M680X_INS_ADCA, ext_hid, inh_hid }, + { M680X_INS_ORA, ext_hid, inh_hid }, + { M680X_INS_ADDA, ext_hid, inh_hid }, + { M680X_INS_CMPX, ext_hid, inh_hid }, + { M680X_INS_JSR, ext_hid, inh_hid }, + { M680X_INS_LDX, ext_hid, inh_hid }, + { M680X_INS_STX, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register B,D,U + { M680X_INS_SUBB, imm8_hid, inh_hid }, + { M680X_INS_CMPB, imm8_hid, inh_hid }, + { M680X_INS_SBCB, imm8_hid, inh_hid }, + { M680X_INS_ADDD, imm16_hid, inh_hid }, + { M680X_INS_ANDB, imm8_hid, inh_hid }, + { M680X_INS_BITB, imm8_hid, inh_hid }, + { M680X_INS_LDB, imm8_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_EORB, imm8_hid, inh_hid }, + { M680X_INS_ADCB, imm8_hid, inh_hid }, + { M680X_INS_ORB, imm8_hid, inh_hid }, + { M680X_INS_ADDB, imm8_hid, inh_hid }, + { M680X_INS_LDD, imm16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + { M680X_INS_LDU, imm16_hid, inh_hid }, + { M680X_INS_ILLGL, illgl_hid, inh_hid }, + // 0xDx direct instructions with register B,D,U + { M680X_INS_SUBB, dir_hid, inh_hid }, + { M680X_INS_CMPB, dir_hid, inh_hid }, + { M680X_INS_SBCB, dir_hid, inh_hid }, + { M680X_INS_ADDD, dir_hid, inh_hid }, + { M680X_INS_ANDB, dir_hid, inh_hid }, + { M680X_INS_BITB, dir_hid, inh_hid }, + { M680X_INS_LDB, dir_hid, inh_hid }, + { M680X_INS_STB, dir_hid, inh_hid }, + { M680X_INS_EORB, dir_hid, inh_hid }, + { M680X_INS_ADCB, dir_hid, inh_hid }, + { M680X_INS_ORB, dir_hid, inh_hid }, + { M680X_INS_ADDB, dir_hid, inh_hid }, + { M680X_INS_LDD, dir_hid, inh_hid }, + { M680X_INS_STD, dir_hid, inh_hid }, + { M680X_INS_LDU, dir_hid, inh_hid }, + { M680X_INS_STU, dir_hid, inh_hid }, + // 0xEx, indexed instruction with register B,D,U + { M680X_INS_SUBB, idx09_hid, inh_hid }, + { M680X_INS_CMPB, idx09_hid, inh_hid }, + { M680X_INS_SBCB, idx09_hid, inh_hid }, + { M680X_INS_ADDD, idx09_hid, inh_hid }, + { M680X_INS_ANDB, idx09_hid, inh_hid }, + { M680X_INS_BITB, idx09_hid, inh_hid }, + { M680X_INS_LDB, idx09_hid, inh_hid }, + { M680X_INS_STB, idx09_hid, inh_hid }, + { M680X_INS_EORB, idx09_hid, inh_hid }, + { M680X_INS_ADCB, idx09_hid, inh_hid }, + { M680X_INS_ORB, idx09_hid, inh_hid }, + { M680X_INS_ADDB, idx09_hid, inh_hid }, + { M680X_INS_LDD, idx09_hid, inh_hid }, + { M680X_INS_STD, idx09_hid, inh_hid }, + { M680X_INS_LDU, idx09_hid, inh_hid }, + { M680X_INS_STU, idx09_hid, inh_hid }, + // 0xFx, extended instructions with register B,D,U + { M680X_INS_SUBB, ext_hid, inh_hid }, + { M680X_INS_CMPB, ext_hid, inh_hid }, + { M680X_INS_SBCB, ext_hid, inh_hid }, + { M680X_INS_ADDD, ext_hid, inh_hid }, + { M680X_INS_ANDB, ext_hid, inh_hid }, + { M680X_INS_BITB, ext_hid, inh_hid }, + { M680X_INS_LDB, ext_hid, inh_hid }, + { M680X_INS_STB, ext_hid, inh_hid }, + { M680X_INS_EORB, ext_hid, inh_hid }, + { M680X_INS_ADCB, ext_hid, inh_hid }, + { M680X_INS_ORB, ext_hid, inh_hid }, + { M680X_INS_ADDB, ext_hid, inh_hid }, + { M680X_INS_LDD, ext_hid, inh_hid }, + { M680X_INS_STD, ext_hid, inh_hid }, + { M680X_INS_LDU, ext_hid, inh_hid }, + { M680X_INS_STU, ext_hid, inh_hid }, +}; + +// The following array has to be sorted by increasing +// opcodes. Otherwise the binary_search will fail. +// +// M6809 PAGE2 instructions (with prefix 0x10) +static const inst_pageX g_m6809_inst_page2_table[] = { + // 0x2x, relative long branch instructions + { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, + { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, + { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, + { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, + { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, + { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, + { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, + { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, + { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, + { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, + { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, + { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, + { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, + { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, + { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, + // 0x3x + { 0x3f, M680X_INS_SWI2, inh_hid, inh_hid }, + // 0x8x, immediate instructions with register D,Y + { 0x83, M680X_INS_CMPD, imm16_hid, inh_hid }, + { 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid }, + { 0x8e, M680X_INS_LDY, imm16_hid, inh_hid }, + // 0x9x, direct instructions with register D,Y + { 0x93, M680X_INS_CMPD, dir_hid, inh_hid }, + { 0x9c, M680X_INS_CMPY, dir_hid, inh_hid }, + { 0x9e, M680X_INS_LDY, dir_hid, inh_hid }, + { 0x9f, M680X_INS_STY, dir_hid, inh_hid }, + // 0xAx, indexed instructions with register D,Y + { 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid }, + { 0xac, M680X_INS_CMPY, idx09_hid, inh_hid }, + { 0xae, M680X_INS_LDY, idx09_hid, inh_hid }, + { 0xaf, M680X_INS_STY, idx09_hid, inh_hid }, + // 0xBx, extended instructions with register D,Y + { 0xb3, M680X_INS_CMPD, ext_hid, inh_hid }, + { 0xbc, M680X_INS_CMPY, ext_hid, inh_hid }, + { 0xbe, M680X_INS_LDY, ext_hid, inh_hid }, + { 0xbf, M680X_INS_STY, ext_hid, inh_hid }, + // 0xCx, immediate instructions with register S + { 0xce, M680X_INS_LDS, imm16_hid, inh_hid }, + // 0xDx, direct instructions with register S + { 0xde, M680X_INS_LDS, dir_hid, inh_hid }, + { 0xdf, M680X_INS_STS, dir_hid, inh_hid }, + // 0xEx, indexed instructions with register S + { 0xee, M680X_INS_LDS, idx09_hid, inh_hid }, + { 0xef, M680X_INS_STS, idx09_hid, inh_hid }, + // 0xFx, extended instructions with register S + { 0xfe, M680X_INS_LDS, ext_hid, inh_hid }, + { 0xff, M680X_INS_STS, ext_hid, inh_hid }, +}; + +// The following array has to be sorted by increasing +// opcodes. Otherwise the binary_search will fail. +// +// M6809 PAGE3 instructions (with prefix 0x11) +static const inst_pageX g_m6809_inst_page3_table[] = { + { 0x3f, M680X_INS_SWI3, inh_hid, inh_hid }, + // 0x8x, immediate instructions with register U,S + { 0x83, M680X_INS_CMPU, imm16_hid, inh_hid }, + { 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid }, + // 0x9x, direct instructions with register U,S + { 0x93, M680X_INS_CMPU, dir_hid, inh_hid }, + { 0x9c, M680X_INS_CMPS, dir_hid, inh_hid }, + // 0xAx, indexed instructions with register U,S + { 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid }, + { 0xac, M680X_INS_CMPS, idx09_hid, inh_hid }, + // 0xBx, extended instructions with register U,S + { 0xb3, M680X_INS_CMPU, ext_hid, inh_hid }, + { 0xbc, M680X_INS_CMPS, ext_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M680X/m6811.inc b/white_patch_detect/capstone-master/arch/M680X/m6811.inc new file mode 100644 index 0000000..f26fb2c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M680X/m6811.inc @@ -0,0 +1,105 @@ + +// Additional instructions only supported on M68HC11 +static const inst_pageX g_m6811_inst_overlay_table[] = { + { 0x00, M680X_INS_TEST, inh_hid, inh_hid }, + { 0x02, M680X_INS_IDIV, inh_hid, inh_hid }, + { 0x03, M680X_INS_FDIV, inh_hid, inh_hid }, + { 0x12, M680X_INS_BRSET, dir_hid, imm8rel_hid }, + { 0x13, M680X_INS_BRCLR, dir_hid, imm8rel_hid }, + { 0x14, M680X_INS_BSET, dir_hid, imm8_hid }, + { 0x15, M680X_INS_BCLR, dir_hid, imm8_hid }, + { 0x1c, M680X_INS_BSET, idxX_hid, imm8_hid }, + { 0x1d, M680X_INS_BCLR, idxX_hid, imm8_hid }, + { 0x1e, M680X_INS_BRSET, idxX_hid, imm8rel_hid }, + { 0x1f, M680X_INS_BRCLR, idxX_hid, imm8rel_hid }, + { 0x8f, M680X_INS_XGDX, inh_hid, inh_hid }, + { 0xcf, M680X_INS_STOP, inh_hid, inh_hid }, +}; + +// M68HC11 PAGE2 instructions +static const inst_pageX g_m6811_inst_page2_table[] = { + { 0x08, M680X_INS_INY, inh_hid, inh_hid }, + { 0x09, M680X_INS_DEY, inh_hid, inh_hid }, + { 0x1c, M680X_INS_BSET, idxY_hid, imm8_hid }, + { 0x1d, M680X_INS_BCLR, idxY_hid, imm8_hid }, + { 0x1e, M680X_INS_BRSET, idxY_hid, imm8rel_hid }, + { 0x1f, M680X_INS_BRCLR, idxY_hid, imm8rel_hid }, + { 0x30, M680X_INS_TSY, inh_hid, inh_hid }, + { 0x35, M680X_INS_TYS, inh_hid, inh_hid }, + { 0x38, M680X_INS_PULY, inh_hid, inh_hid }, + { 0x3a, M680X_INS_ABY, inh_hid, inh_hid }, + { 0x3c, M680X_INS_PSHY, inh_hid, inh_hid }, + { 0x60, M680X_INS_NEG, idxY_hid, inh_hid }, + { 0x63, M680X_INS_COM, idxY_hid, inh_hid }, + { 0x64, M680X_INS_LSR, idxY_hid, inh_hid }, + { 0x66, M680X_INS_ROR, idxY_hid, inh_hid }, + { 0x67, M680X_INS_ASR, idxY_hid, inh_hid }, + { 0x68, M680X_INS_ASL, idxY_hid, inh_hid }, + { 0x69, M680X_INS_ROL, idxY_hid, inh_hid }, + { 0x6a, M680X_INS_DEC, idxY_hid, inh_hid }, + { 0x6c, M680X_INS_INC, idxY_hid, inh_hid }, + { 0x6d, M680X_INS_TST, idxY_hid, inh_hid }, + { 0x6e, M680X_INS_JMP, idxY_hid, inh_hid }, + { 0x6f, M680X_INS_CLR, idxY_hid, inh_hid }, + { 0x8c, M680X_INS_CPY, imm16_hid, inh_hid }, + { 0x8f, M680X_INS_XGDY, inh_hid, inh_hid }, + { 0x9c, M680X_INS_CPY, dir_hid, inh_hid }, + { 0xa0, M680X_INS_SUBA, idxY_hid, inh_hid }, + { 0xa1, M680X_INS_CMPA, idxY_hid, inh_hid }, + { 0xa2, M680X_INS_SBCA, idxY_hid, inh_hid }, + { 0xa3, M680X_INS_SUBD, idxY_hid, inh_hid }, + { 0xa4, M680X_INS_ANDA, idxY_hid, inh_hid }, + { 0xa5, M680X_INS_BITA, idxY_hid, inh_hid }, + { 0xa6, M680X_INS_LDAA, idxY_hid, inh_hid }, + { 0xa7, M680X_INS_STAA, idxY_hid, inh_hid }, + { 0xa8, M680X_INS_EORA, idxY_hid, inh_hid }, + { 0xa9, M680X_INS_ADCA, idxY_hid, inh_hid }, + { 0xaa, M680X_INS_ORAA, idxY_hid, inh_hid }, + { 0xab, M680X_INS_ADDA, idxY_hid, inh_hid }, + { 0xac, M680X_INS_CPY, idxY_hid, inh_hid }, + { 0xad, M680X_INS_JSR, idxY_hid, inh_hid }, + { 0xae, M680X_INS_LDS, idxY_hid, inh_hid }, + { 0xaf, M680X_INS_STS, idxY_hid, inh_hid }, + { 0xbc, M680X_INS_CPY, ext_hid, inh_hid }, + { 0xce, M680X_INS_LDY, imm16_hid, inh_hid }, + { 0xde, M680X_INS_LDY, dir_hid, inh_hid }, + { 0xdf, M680X_INS_STY, dir_hid, inh_hid }, + { 0xe0, M680X_INS_SUBB, idxY_hid, inh_hid }, + { 0xe1, M680X_INS_CMPB, idxY_hid, inh_hid }, + { 0xe2, M680X_INS_SBCB, idxY_hid, inh_hid }, + { 0xe3, M680X_INS_ADDD, idxY_hid, inh_hid }, + { 0xe4, M680X_INS_ANDB, idxY_hid, inh_hid }, + { 0xe5, M680X_INS_BITB, idxY_hid, inh_hid }, + { 0xe6, M680X_INS_LDAB, idxY_hid, inh_hid }, + { 0xe7, M680X_INS_STAB, idxY_hid, inh_hid }, + { 0xe8, M680X_INS_EORB, idxY_hid, inh_hid }, + { 0xe9, M680X_INS_ADCB, idxY_hid, inh_hid }, + { 0xea, M680X_INS_ORAB, idxY_hid, inh_hid }, + { 0xeb, M680X_INS_ADDB, idxY_hid, inh_hid }, + { 0xec, M680X_INS_LDD, idxY_hid, inh_hid }, + { 0xed, M680X_INS_STD, idxY_hid, inh_hid }, + { 0xee, M680X_INS_LDY, idxY_hid, inh_hid }, + { 0xef, M680X_INS_STY, idxY_hid, inh_hid }, + { 0xfe, M680X_INS_LDY, ext_hid, inh_hid }, + { 0xff, M680X_INS_STY, ext_hid, inh_hid }, +}; + +// M68HC11 PAGE3 instructions +static const inst_pageX g_m6811_inst_page3_table[] = { + { 0x83, M680X_INS_CPD, imm16_hid, inh_hid }, + { 0x93, M680X_INS_CPD, dir_hid, inh_hid }, + { 0xa3, M680X_INS_CPD, idxX_hid, inh_hid }, + { 0xac, M680X_INS_CPY, idxX_hid, inh_hid }, + { 0xb3, M680X_INS_CPD, ext_hid, inh_hid }, + { 0xee, M680X_INS_LDY, idxX_hid, inh_hid }, + { 0xef, M680X_INS_STY, idxX_hid, inh_hid }, +}; + +// M68HC11 PAGE4 instructions +static const inst_pageX g_m6811_inst_page4_table[] = { + { 0xa3, M680X_INS_CPD, idxY_hid, inh_hid }, + { 0xac, M680X_INS_CPX, idxY_hid, inh_hid }, + { 0xee, M680X_INS_LDX, idxY_hid, inh_hid }, + { 0xef, M680X_INS_STX, idxY_hid, inh_hid }, +}; + diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.c b/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.c new file mode 100644 index 0000000..78b7022 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.c @@ -0,0 +1,4115 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* The code bellow is based on MUSASHI but has been heavily modified for capstore by + * Daniel Collin 2015-2016 */ + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCRegisterInfo.h" +#include "M68KInstPrinter.h" +#include "M68KDisassembler.h" + +#ifndef DECL_SPEC +#ifdef _MSC_VER +#define DECL_SPEC __cdecl +#else +#define DECL_SPEC +#endif // _MSC_VER +#endif // DECL_SPEC + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* unsigned int and int must be at least 32 bits wide */ +#undef uint +#define uint unsigned int + +/* Bit Isolation Functions */ +#define BIT_0(A) ((A) & 0x00000001) +#define BIT_1(A) ((A) & 0x00000002) +#define BIT_2(A) ((A) & 0x00000004) +#define BIT_3(A) ((A) & 0x00000008) +#define BIT_4(A) ((A) & 0x00000010) +#define BIT_5(A) ((A) & 0x00000020) +#define BIT_6(A) ((A) & 0x00000040) +#define BIT_7(A) ((A) & 0x00000080) +#define BIT_8(A) ((A) & 0x00000100) +#define BIT_9(A) ((A) & 0x00000200) +#define BIT_A(A) ((A) & 0x00000400) +#define BIT_B(A) ((A) & 0x00000800) +#define BIT_C(A) ((A) & 0x00001000) +#define BIT_D(A) ((A) & 0x00002000) +#define BIT_E(A) ((A) & 0x00004000) +#define BIT_F(A) ((A) & 0x00008000) +#define BIT_10(A) ((A) & 0x00010000) +#define BIT_11(A) ((A) & 0x00020000) +#define BIT_12(A) ((A) & 0x00040000) +#define BIT_13(A) ((A) & 0x00080000) +#define BIT_14(A) ((A) & 0x00100000) +#define BIT_15(A) ((A) & 0x00200000) +#define BIT_16(A) ((A) & 0x00400000) +#define BIT_17(A) ((A) & 0x00800000) +#define BIT_18(A) ((A) & 0x01000000) +#define BIT_19(A) ((A) & 0x02000000) +#define BIT_1A(A) ((A) & 0x04000000) +#define BIT_1B(A) ((A) & 0x08000000) +#define BIT_1C(A) ((A) & 0x10000000) +#define BIT_1D(A) ((A) & 0x20000000) +#define BIT_1E(A) ((A) & 0x40000000) +#define BIT_1F(A) ((A) & 0x80000000) + +/* These are the CPU types understood by this disassembler */ +#define TYPE_68000 1 +#define TYPE_68010 2 +#define TYPE_68020 4 +#define TYPE_68030 8 +#define TYPE_68040 16 + +#define M68000_ONLY TYPE_68000 + +#define M68010_ONLY TYPE_68010 +#define M68010_LESS (TYPE_68000 | TYPE_68010) +#define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040) + +#define M68020_ONLY TYPE_68020 +#define M68020_LESS (TYPE_68010 | TYPE_68020) +#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040) + +#define M68030_ONLY TYPE_68030 +#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030) +#define M68030_PLUS (TYPE_68030 | TYPE_68040) + +#define M68040_PLUS TYPE_68040 + +enum { + M68K_CPU_TYPE_INVALID, + M68K_CPU_TYPE_68000, + M68K_CPU_TYPE_68010, + M68K_CPU_TYPE_68EC020, + M68K_CPU_TYPE_68020, + M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ + M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ +}; + +/* Extension word formats */ +#define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff) +#define EXT_FULL(A) BIT_8(A) +#define EXT_EFFECTIVE_ZERO(A) (((A)&0xe4) == 0xc4 || ((A)&0xe2) == 0xc0) +#define EXT_BASE_REGISTER_PRESENT(A) (!BIT_7(A)) +#define EXT_INDEX_REGISTER_PRESENT(A) (!BIT_6(A)) +#define EXT_INDEX_REGISTER(A) (((A)>>12)&7) +#define EXT_INDEX_PRE_POST(A) (EXT_INDEX_PRESENT(A) && (A)&3) +#define EXT_INDEX_PRE(A) (EXT_INDEX_PRESENT(A) && ((A)&7) < 4 && ((A)&7) != 0) +#define EXT_INDEX_POST(A) (EXT_INDEX_PRESENT(A) && ((A)&7) > 4) +#define EXT_INDEX_SCALE(A) (((A)>>9)&3) +#define EXT_INDEX_LONG(A) BIT_B(A) +#define EXT_INDEX_AR(A) BIT_F(A) +#define EXT_BASE_DISPLACEMENT_PRESENT(A) (((A)&0x30) > 0x10) +#define EXT_BASE_DISPLACEMENT_WORD(A) (((A)&0x30) == 0x20) +#define EXT_BASE_DISPLACEMENT_LONG(A) (((A)&0x30) == 0x30) +#define EXT_OUTER_DISPLACEMENT_PRESENT(A) (((A)&3) > 1 && ((A)&0x47) < 0x44) +#define EXT_OUTER_DISPLACEMENT_WORD(A) (((A)&3) == 2 && ((A)&0x47) < 0x44) +#define EXT_OUTER_DISPLACEMENT_LONG(A) (((A)&3) == 3 && ((A)&0x47) < 0x44) + +#define IS_BITSET(val,b) ((val) & (1 << (b))) +#define BITFIELD_MASK(sb,eb) (((1 << ((sb) + 1))-1) & (~((1 << (eb))-1))) +#define BITFIELD(val,sb,eb) ((BITFIELD_MASK(sb,eb) & (val)) >> (eb)) + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +static unsigned int m68k_read_disassembler_16(const m68k_info *info, const uint64_t addr) +{ + const uint16_t v0 = info->code[addr + 0]; + const uint16_t v1 = info->code[addr + 1]; + return (v0 << 8) | v1; +} + +static unsigned int m68k_read_disassembler_32(const m68k_info *info, const uint64_t addr) +{ + const uint32_t v0 = info->code[addr + 0]; + const uint32_t v1 = info->code[addr + 1]; + const uint32_t v2 = info->code[addr + 2]; + const uint32_t v3 = info->code[addr + 3]; + return (v0 << 24) | (v1 << 16) | (v2 << 8) | v3; +} + +static uint64_t m68k_read_disassembler_64(const m68k_info *info, const uint64_t addr) +{ + const uint64_t v0 = info->code[addr + 0]; + const uint64_t v1 = info->code[addr + 1]; + const uint64_t v2 = info->code[addr + 2]; + const uint64_t v3 = info->code[addr + 3]; + const uint64_t v4 = info->code[addr + 4]; + const uint64_t v5 = info->code[addr + 5]; + const uint64_t v6 = info->code[addr + 6]; + const uint64_t v7 = info->code[addr + 7]; + return (v0 << 56) | (v1 << 48) | (v2 << 40) | (v3 << 32) | (v4 << 24) | (v5 << 16) | (v6 << 8) | v7; +} + +static unsigned int m68k_read_safe_16(const m68k_info *info, const uint64_t address) +{ + const uint64_t addr = (address - info->baseAddress) & info->address_mask; + if (info->code_len < addr + 2) { + return 0xaaaa; + } + return m68k_read_disassembler_16(info, addr); +} + +static unsigned int m68k_read_safe_32(const m68k_info *info, const uint64_t address) +{ + const uint64_t addr = (address - info->baseAddress) & info->address_mask; + if (info->code_len < addr + 4) { + return 0xaaaaaaaa; + } + return m68k_read_disassembler_32(info, addr); +} + +static uint64_t m68k_read_safe_64(const m68k_info *info, const uint64_t address) +{ + const uint64_t addr = (address - info->baseAddress) & info->address_mask; + if (info->code_len < addr + 8) { + return 0xaaaaaaaaaaaaaaaaLL; + } + return m68k_read_disassembler_64(info, addr); +} + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +/* make signed integers 100% portably */ +static int make_int_8(int value); +static int make_int_16(int value); + +/* Stuff to build the opcode handler jump table */ +static void build_opcode_table(void); +static int valid_ea(uint opcode, uint mask); +static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr); +static void d68000_invalid(m68k_info *info); +static int instruction_is_valid(m68k_info *info, const unsigned int word_check); + +/* used to build opcode handler jump table */ +typedef struct { + void (*opcode_handler)(m68k_info *info); /* handler function */ + uint mask; /* mask on opcode */ + uint match; /* what to match after masking */ + uint ea_mask; /* what ea modes are allowed */ + uint mask2; /* mask the 2nd word */ + uint match2; /* what to match after masking */ +} opcode_struct; + +typedef struct { + void (*instruction)(m68k_info *info); /* handler function */ + uint word2_mask; /* mask the 2nd word */ + uint word2_match; /* what to match after masking */ +} instruction_struct; + +/* ======================================================================== */ +/* ================================= DATA ================================= */ +/* ======================================================================== */ + +/* Opcode handler jump table */ +static instruction_struct g_instruction_table[0x10000]; + +/* used by ops like asr, ror, addq, etc */ +static uint g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7}; + +static uint g_5bit_data_table[32] = { + 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; + +static m68k_insn s_branch_lut[] = { + M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS, + M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ, + M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI, + M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE, +}; + +static m68k_insn s_dbcc_lut[] = { + M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS, + M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ, + M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI, + M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE, +}; + +static m68k_insn s_scc_lut[] = { + M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS, + M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ, + M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI, + M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE, +}; + +static m68k_insn s_trap_lut[] = { + M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS, + M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ, + M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI, + M68K_INS_TRAPGE, M68K_INS_TRAPLT, M68K_INS_TRAPGT, M68K_INS_TRAPLE, +}; + +/* ======================================================================== */ +/* =========================== UTILITY FUNCTIONS ========================== */ +/* ======================================================================== */ + +#define LIMIT_CPU_TYPES(info, ALLOWED_CPU_TYPES) \ + do { \ + if (!(info->type & ALLOWED_CPU_TYPES)) { \ + d68000_invalid(info); \ + return; \ + } \ + } while (0) + +static unsigned int peek_imm_8(const m68k_info *info) { return (m68k_read_safe_16((info), (info)->pc)&0xff); } +static unsigned int peek_imm_16(const m68k_info *info) { return m68k_read_safe_16((info), (info)->pc); } +static unsigned int peek_imm_32(const m68k_info *info) { return m68k_read_safe_32((info), (info)->pc); } +static unsigned long long peek_imm_64(const m68k_info *info) { return m68k_read_safe_64((info), (info)->pc); } + +static unsigned int read_imm_8(m68k_info *info) { const unsigned int value = peek_imm_8(info); (info)->pc+=2; return value; } +static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value; } +static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value; } +static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value; } + +/* Fake a split interface */ +#define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0) +#define get_ea_mode_str_16(instruction) get_ea_mode_str(instruction, 1) +#define get_ea_mode_str_32(instruction) get_ea_mode_str(instruction, 2) + +#define get_imm_str_s8() get_imm_str_s(0) +#define get_imm_str_s16() get_imm_str_s(1) +#define get_imm_str_s32() get_imm_str_s(2) + +#define get_imm_str_u8() get_imm_str_u(0) +#define get_imm_str_u16() get_imm_str_u(1) +#define get_imm_str_u32() get_imm_str_u(2) + + +/* 100% portable signed int generators */ +static int make_int_8(int value) +{ + return (value & 0x80) ? value | ~0xff : value & 0xff; +} + +static int make_int_16(int value) +{ + return (value & 0x8000) ? value | ~0xffff : value & 0xffff; +} + +static void get_with_index_address_mode(m68k_info *info, cs_m68k_op* op, uint instruction, uint size, bool is_pc) +{ + uint extension = read_imm_16(info); + + op->address_mode = M68K_AM_AREGI_INDEX_BASE_DISP; + + if (EXT_FULL(extension)) { + uint preindex; + uint postindex; + + op->mem.base_reg = M68K_REG_INVALID; + op->mem.index_reg = M68K_REG_INVALID; + + /* Not sure how to deal with this? + if (EXT_EFFECTIVE_ZERO(extension)) { + strcpy(mode, "0"); + break; + } + */ + + op->mem.in_disp = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; + op->mem.out_disp = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; + + if (EXT_BASE_REGISTER_PRESENT(extension)) { + if (is_pc) { + op->mem.base_reg = M68K_REG_PC; + } else { + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); + } + } + + if (EXT_INDEX_REGISTER_PRESENT(extension)) { + if (EXT_INDEX_AR(extension)) { + op->mem.index_reg = M68K_REG_A0 + EXT_INDEX_REGISTER(extension); + } else { + op->mem.index_reg = M68K_REG_D0 + EXT_INDEX_REGISTER(extension); + } + + op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0; + + if (EXT_INDEX_SCALE(extension)) { + op->mem.scale = 1 << EXT_INDEX_SCALE(extension); + } + } + + preindex = (extension & 7) > 0 && (extension & 7) < 4; + postindex = (extension & 7) > 4; + + if (preindex) { + op->address_mode = is_pc ? M68K_AM_PC_MEMI_PRE_INDEX : M68K_AM_MEMI_PRE_INDEX; + } else if (postindex) { + op->address_mode = is_pc ? M68K_AM_PC_MEMI_POST_INDEX : M68K_AM_MEMI_POST_INDEX; + } + + return; + } + + op->mem.index_reg = (EXT_INDEX_AR(extension) ? M68K_REG_A0 : M68K_REG_D0) + EXT_INDEX_REGISTER(extension); + op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0; + + if (EXT_8BIT_DISPLACEMENT(extension) == 0) { + if (is_pc) { + op->mem.base_reg = M68K_REG_PC; + op->address_mode = M68K_AM_PCI_INDEX_BASE_DISP; + } else { + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); + } + } else { + if (is_pc) { + op->mem.base_reg = M68K_REG_PC; + op->address_mode = M68K_AM_PCI_INDEX_8_BIT_DISP; + } else { + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); + op->address_mode = M68K_AM_AREGI_INDEX_8_BIT_DISP; + } + + op->mem.disp = (int8_t)(extension & 0xff); + } + + if (EXT_INDEX_SCALE(extension)) { + op->mem.scale = 1 << EXT_INDEX_SCALE(extension); + } +} + +/* Make string of effective address mode */ +static void get_ea_mode_op(m68k_info *info, cs_m68k_op* op, uint instruction, uint size) +{ + // default to memory + + op->type = M68K_OP_MEM; + + switch (instruction & 0x3f) { + case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: + /* data register direct */ + op->address_mode = M68K_AM_REG_DIRECT_DATA; + op->reg = M68K_REG_D0 + (instruction & 7); + op->type = M68K_OP_REG; + break; + + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: + /* address register direct */ + op->address_mode = M68K_AM_REG_DIRECT_ADDR; + op->reg = M68K_REG_A0 + (instruction & 7); + op->type = M68K_OP_REG; + break; + + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: + /* address register indirect */ + op->address_mode = M68K_AM_REGI_ADDR; + op->reg = M68K_REG_A0 + (instruction & 7); + break; + + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: + /* address register indirect with postincrement */ + op->address_mode = M68K_AM_REGI_ADDR_POST_INC; + op->reg = M68K_REG_A0 + (instruction & 7); + break; + + case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: + /* address register indirect with predecrement */ + op->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; + op->reg = M68K_REG_A0 + (instruction & 7); + break; + + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: + /* address register indirect with displacement*/ + op->address_mode = M68K_AM_REGI_ADDR_DISP; + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); + op->mem.disp = (int16_t)read_imm_16(info); + break; + + case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: + /* address register indirect with index */ + get_with_index_address_mode(info, op, instruction, size, false); + break; + + case 0x38: + /* absolute short address */ + op->address_mode = M68K_AM_ABSOLUTE_DATA_SHORT; + op->imm = read_imm_16(info); + break; + + case 0x39: + /* absolute long address */ + op->address_mode = M68K_AM_ABSOLUTE_DATA_LONG; + op->imm = read_imm_32(info); + break; + + case 0x3a: + /* program counter with displacement */ + op->address_mode = M68K_AM_PCI_DISP; + op->mem.disp = (int16_t)read_imm_16(info); + break; + + case 0x3b: + /* program counter with index */ + get_with_index_address_mode(info, op, instruction, size, true); + break; + + case 0x3c: + op->address_mode = M68K_AM_IMMEDIATE; + op->type = M68K_OP_IMM; + + if (size == 1) + op->imm = read_imm_8(info) & 0xff; + else if (size == 2) + op->imm = read_imm_16(info) & 0xffff; + else if (size == 4) + op->imm = read_imm_32(info); + else + op->imm = read_imm_64(info); + + break; + + default: + break; + } +} + +static void set_insn_group(m68k_info *info, m68k_group_type group) +{ + info->groups[info->groups_count++] = (uint8_t)group; +} + +static cs_m68k* build_init_op(m68k_info *info, int opcode, int count, int size) +{ + cs_m68k* ext; + + MCInst_setOpcode(info->inst, opcode); + + ext = &info->extension; + + ext->op_count = (uint8_t)count; + ext->op_size.type = M68K_SIZE_TYPE_CPU; + ext->op_size.cpu_size = size; + + return ext; +} + +static void build_re_gen_1(m68k_info *info, bool isDreg, int opcode, uint8_t size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + if (isDreg) { + op0->address_mode = M68K_AM_REG_DIRECT_DATA; + op0->reg = M68K_REG_D0 + ((info->ir >> 9 ) & 7); + } else { + op0->address_mode = M68K_AM_REG_DIRECT_ADDR; + op0->reg = M68K_REG_A0 + ((info->ir >> 9 ) & 7); + } + + get_ea_mode_op(info, op1, info->ir, size); +} + +static void build_re_1(m68k_info *info, int opcode, uint8_t size) +{ + build_re_gen_1(info, true, opcode, size); +} + +static void build_er_gen_1(m68k_info *info, bool isDreg, int opcode, uint8_t size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, size); + + if (isDreg) { + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); + } else { + op1->address_mode = M68K_AM_REG_DIRECT_ADDR; + op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); + } +} + +static void build_rr(m68k_info *info, int opcode, uint8_t size, int imm) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k_op* op2; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + op2 = &ext->operands[2]; + + op0->address_mode = M68K_AM_REG_DIRECT_DATA; + op0->reg = M68K_REG_D0 + (info->ir & 7); + + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); + + if (imm > 0) { + ext->op_count = 3; + op2->type = M68K_OP_IMM; + op2->address_mode = M68K_AM_IMMEDIATE; + op2->imm = imm; + } +} + +static void build_r(m68k_info *info, int opcode, uint8_t size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_REG_DIRECT_DATA; + op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); + + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + (info->ir & 7); +} + +static void build_imm_ea(m68k_info *info, int opcode, uint8_t size, int imm) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_IMM; + op0->address_mode = M68K_AM_IMMEDIATE; + op0->imm = imm; + + get_ea_mode_op(info, op1, info->ir, size); +} + +static void build_3bit_d(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_IMM; + op0->address_mode = M68K_AM_IMMEDIATE; + op0->imm = g_3bit_qdata_table[(info->ir >> 9) & 7]; + + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + (info->ir & 7); +} + +static void build_3bit_ea(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_IMM; + op0->address_mode = M68K_AM_IMMEDIATE; + op0->imm = g_3bit_qdata_table[(info->ir >> 9) & 7]; + + get_ea_mode_op(info, op1, info->ir, size); +} + +static void build_mm(m68k_info *info, int opcode, uint8_t size, int imm) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k_op* op2; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + op2 = &ext->operands[2]; + + op0->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; + op0->reg = M68K_REG_A0 + (info->ir & 7); + + op1->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; + op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); + + if (imm > 0) { + ext->op_count = 3; + op2->type = M68K_OP_IMM; + op2->address_mode = M68K_AM_IMMEDIATE; + op2->imm = imm; + } +} + +static void build_ea(m68k_info *info, int opcode, uint8_t size) +{ + cs_m68k* ext = build_init_op(info, opcode, 1, size); + get_ea_mode_op(info, &ext->operands[0], info->ir, size); +} + +static void build_ea_a(m68k_info *info, int opcode, uint8_t size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, size); + + op1->address_mode = M68K_AM_REG_DIRECT_ADDR; + op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); +} + +static void build_ea_ea(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, size); + get_ea_mode_op(info, op1, (((info->ir>>9) & 7) | ((info->ir>>3) & 0x38)), size); +} + +static void build_pi_pi(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_REGI_ADDR_POST_INC; + op0->reg = M68K_REG_A0 + (info->ir & 7); + + op1->address_mode = M68K_AM_REGI_ADDR_POST_INC; + op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); +} + +static void build_imm_special_reg(m68k_info *info, int opcode, int imm, int size, m68k_reg reg) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_IMM; + op0->address_mode = M68K_AM_IMMEDIATE; + op0->imm = imm; + + op1->address_mode = M68K_AM_NONE; + op1->reg = reg; +} + +static void build_relative_branch(m68k_info *info, int opcode, int size, int displacement) +{ + cs_m68k_op* op; + cs_m68k* ext = build_init_op(info, opcode, 1, size); + + op = &ext->operands[0]; + + op->type = M68K_OP_BR_DISP; + op->address_mode = M68K_AM_BRANCH_DISPLACEMENT; + op->br_disp.disp = displacement; + op->br_disp.disp_size = size; + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static void build_absolute_jump_with_immediate(m68k_info *info, int opcode, int size, int immediate) +{ + cs_m68k_op* op; + cs_m68k* ext = build_init_op(info, opcode, 1, size); + + op = &ext->operands[0]; + + op->type = M68K_OP_IMM; + op->address_mode = M68K_AM_IMMEDIATE; + op->imm = immediate; + + set_insn_group(info, M68K_GRP_JUMP); +} + +static void build_bcc(m68k_info *info, int size, int displacement) +{ + build_relative_branch(info, s_branch_lut[(info->ir >> 8) & 0xf], size, displacement); +} + +static void build_trap(m68k_info *info, int size, int immediate) +{ + build_absolute_jump_with_immediate(info, s_trap_lut[(info->ir >> 8) & 0xf], size, immediate); +} + +static void build_dbxx(m68k_info *info, int opcode, int size, int displacement) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_REG_DIRECT_DATA; + op0->reg = M68K_REG_D0 + (info->ir & 7); + + op1->type = M68K_OP_BR_DISP; + op1->address_mode = M68K_AM_BRANCH_DISPLACEMENT; + op1->br_disp.disp = displacement; + op1->br_disp.disp_size = M68K_OP_BR_DISP_SIZE_LONG; + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static void build_dbcc(m68k_info *info, int size, int displacement) +{ + build_dbxx(info, s_dbcc_lut[(info->ir >> 8) & 0xf], size, displacement); +} + +static void build_d_d_ea(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k_op* op2; + uint extension = read_imm_16(info); + cs_m68k* ext = build_init_op(info, opcode, 3, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + op2 = &ext->operands[2]; + + op0->address_mode = M68K_AM_REG_DIRECT_DATA; + op0->reg = M68K_REG_D0 + (extension & 7); + + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + ((extension >> 6) & 7); + + get_ea_mode_op(info, op2, info->ir, size); +} + +static void build_bitfield_ins(m68k_info *info, int opcode, int has_d_arg) +{ + uint8_t offset; + uint8_t width; + cs_m68k_op* op_ea; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 1, 0); + uint extension = read_imm_16(info); + + op_ea = &ext->operands[0]; + op1 = &ext->operands[1]; + + if (BIT_B(extension)) + offset = (extension >> 6) & 7; + else + offset = (extension >> 6) & 31; + + if (BIT_5(extension)) + width = extension & 7; + else + width = (uint8_t)g_5bit_data_table[extension & 31]; + + if (has_d_arg) { + ext->op_count = 2; + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + ((extension >> 12) & 7); + } + + get_ea_mode_op(info, op_ea, info->ir, 1); + + op_ea->mem.bitfield = 1; + op_ea->mem.width = width; + op_ea->mem.offset = offset; +} + +static void build_d(m68k_info *info, int opcode, int size) +{ + cs_m68k* ext = build_init_op(info, opcode, 1, size); + cs_m68k_op* op; + + op = &ext->operands[0]; + + op->address_mode = M68K_AM_REG_DIRECT_DATA; + op->reg = M68K_REG_D0 + (info->ir & 7); +} + +static uint16_t reverse_bits(uint v) +{ + uint r = v; // r will be reversed bits of v; first get LSB of v + uint s = 16 - 1; // extra shift needed at end + + for (v >>= 1; v; v >>= 1) { + r <<= 1; + r |= v & 1; + s--; + } + + return r <<= s; // shift when v's highest bits are zero +} + +static uint8_t reverse_bits_8(uint v) +{ + uint r = v; // r will be reversed bits of v; first get LSB of v + uint s = 8 - 1; // extra shift needed at end + + for (v >>= 1; v; v >>= 1) { + r <<= 1; + r |= v & 1; + s--; + } + + return r <<= s; // shift when v's highest bits are zero +} + + +static void build_movem_re(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_REG_BITS; + op0->register_bits = read_imm_16(info); + + get_ea_mode_op(info, op1, info->ir, size); + + if (op1->address_mode == M68K_AM_REGI_ADDR_PRE_DEC) + op0->register_bits = reverse_bits(op0->register_bits); +} + +static void build_movem_er(m68k_info *info, int opcode, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, opcode, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op1->type = M68K_OP_REG_BITS; + op1->register_bits = read_imm_16(info); + + get_ea_mode_op(info, op0, info->ir, size); +} + +static void build_imm(m68k_info *info, int opcode, int data) +{ + cs_m68k_op* op; + cs_m68k* ext = build_init_op(info, opcode, 1, 0); + + MCInst_setOpcode(info->inst, opcode); + + op = &ext->operands[0]; + + op->type = M68K_OP_IMM; + op->address_mode = M68K_AM_IMMEDIATE; + op->imm = data; +} + +static void build_illegal(m68k_info *info, int data) +{ + build_imm(info, M68K_INS_ILLEGAL, data); +} + +static void build_invalid(m68k_info *info, int data) +{ + build_imm(info, M68K_INS_INVALID, data); +} + +static void build_cas2(m68k_info *info, int size) +{ + uint word3; + uint extension; + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k_op* op2; + cs_m68k* ext = build_init_op(info, M68K_INS_CAS2, 3, size); + int reg_0, reg_1; + + /* cas2 is the only 3 words instruction, word2 and word3 have the same motif bits to check */ + word3 = peek_imm_32(info) & 0xffff; + if (!instruction_is_valid(info, word3)) + return; + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + op2 = &ext->operands[2]; + + extension = read_imm_32(info); + + op0->address_mode = M68K_AM_NONE; + op0->type = M68K_OP_REG_PAIR; + op0->reg_pair.reg_0 = (extension >> 16) & 7; + op0->reg_pair.reg_1 = extension & 7; + + op1->address_mode = M68K_AM_NONE; + op1->type = M68K_OP_REG_PAIR; + op1->reg_pair.reg_0 = (extension >> 22) & 7; + op1->reg_pair.reg_1 = (extension >> 6) & 7; + + reg_0 = (extension >> 28) & 7; + reg_1 = (extension >> 12) & 7; + + op2->address_mode = M68K_AM_NONE; + op2->type = M68K_OP_REG_PAIR; + op2->reg_pair.reg_0 = reg_0 + (BIT_1F(extension) ? 8 : 0); + op2->reg_pair.reg_1 = reg_1 + (BIT_F(extension) ? 8 : 0); +} + +static void build_chk2_cmp2(m68k_info *info, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_CHK2, 2, size); + + uint extension = read_imm_16(info); + + if (BIT_B(extension)) + MCInst_setOpcode(info->inst, M68K_INS_CHK2); + else + MCInst_setOpcode(info->inst, M68K_INS_CMP2); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, size); + + op1->address_mode = M68K_AM_NONE; + op1->type = M68K_OP_REG; + op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); +} + +static void build_move16(m68k_info *info, int data[2], int modes[2]) +{ + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE16, 2, 0); + int i; + + for (i = 0; i < 2; ++i) { + cs_m68k_op* op = &ext->operands[i]; + const int d = data[i]; + const int m = modes[i]; + + op->type = M68K_OP_MEM; + + if (m == M68K_AM_REGI_ADDR_POST_INC || m == M68K_AM_REG_DIRECT_ADDR) { + op->address_mode = m; + op->reg = M68K_REG_A0 + d; + } else { + op->address_mode = m; + op->imm = d; + } + } +} + +static void build_link(m68k_info *info, int disp, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_LINK, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_A0 + (info->ir & 7); + + op1->address_mode = M68K_AM_IMMEDIATE; + op1->type = M68K_OP_IMM; + op1->imm = disp; +} + +static void build_cpush_cinv(m68k_info *info, int op_offset) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_INVALID, 2, 0); + + switch ((info->ir >> 3) & 3) { // scope + // Invalid + case 0: + d68000_invalid(info); + return; + // Line + case 1: + MCInst_setOpcode(info->inst, op_offset + 0); + break; + // Page + case 2: + MCInst_setOpcode(info->inst, op_offset + 1); + break; + // All + case 3: + ext->op_count = 1; + MCInst_setOpcode(info->inst, op_offset + 2); + break; + } + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_IMMEDIATE; + op0->type = M68K_OP_IMM; + op0->imm = (info->ir >> 6) & 3; + + op1->type = M68K_OP_MEM; + op1->address_mode = M68K_AM_REG_DIRECT_ADDR; + op1->imm = M68K_REG_A0 + (info->ir & 7); +} + +static void build_movep_re(m68k_info *info, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVEP, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); + + op1->address_mode = M68K_AM_REGI_ADDR_DISP; + op1->type = M68K_OP_MEM; + op1->mem.base_reg = M68K_REG_A0 + (info->ir & 7); + op1->mem.disp = (int16_t)read_imm_16(info); +} + +static void build_movep_er(m68k_info *info, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVEP, 2, size); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_REGI_ADDR_DISP; + op0->type = M68K_OP_MEM; + op0->mem.base_reg = M68K_REG_A0 + (info->ir & 7); + op0->mem.disp = (int16_t)read_imm_16(info); + + op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); +} + +static void build_moves(m68k_info *info, int size) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVES, 2, size); + uint extension = read_imm_16(info); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + if (BIT_B(extension)) { + op0->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); + get_ea_mode_op(info, op1, info->ir, size); + } else { + get_ea_mode_op(info, op0, info->ir, size); + op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); + } +} + +static void build_er_1(m68k_info *info, int opcode, uint8_t size) +{ + build_er_gen_1(info, true, opcode, size); +} + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ +/* Instruction handler function names follow this convention: + * + * d68000_NAME_EXTENSIONS(void) + * where NAME is the name of the opcode it handles and EXTENSIONS are any + * extensions for special instances of that opcode. + * + * Examples: + * d68000_add_er_8(): add opcode, from effective address to register, + * size = byte + * + * d68000_asr_s_8(): arithmetic shift right, static count, size = byte + * + * + * Common extensions: + * 8 : size = byte + * 16 : size = word + * 32 : size = long + * rr : register to register + * mm : memory to memory + * r : register + * s : static + * er : effective address -> register + * re : register -> effective address + * ea : using effective address mode of operation + * d : data register direct + * a : address register direct + * ai : address register indirect + * pi : address register indirect with postincrement + * pd : address register indirect with predecrement + * di : address register indirect with displacement + * ix : address register indirect with index + * aw : absolute word + * al : absolute long + */ + + +static void d68000_invalid(m68k_info *info) +{ + build_invalid(info, info->ir); +} + +static void d68000_illegal(m68k_info *info) +{ + build_illegal(info, info->ir); +} + +static void d68000_1010(m68k_info *info) +{ + build_invalid(info, info->ir); +} + +static void d68000_1111(m68k_info *info) +{ + build_invalid(info, info->ir); +} + +static void d68000_abcd_rr(m68k_info *info) +{ + build_rr(info, M68K_INS_ABCD, 1, 0); +} + +static void d68000_abcd_mm(m68k_info *info) +{ + build_mm(info, M68K_INS_ABCD, 1, 0); +} + +static void d68000_add_er_8(m68k_info *info) +{ + build_er_1(info, M68K_INS_ADD, 1); +} + +static void d68000_add_er_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_ADD, 2); +} + +static void d68000_add_er_32(m68k_info *info) +{ + build_er_1(info, M68K_INS_ADD, 4); +} + +static void d68000_add_re_8(m68k_info *info) +{ + build_re_1(info, M68K_INS_ADD, 1); +} + +static void d68000_add_re_16(m68k_info *info) +{ + build_re_1(info, M68K_INS_ADD, 2); +} + +static void d68000_add_re_32(m68k_info *info) +{ + build_re_1(info, M68K_INS_ADD, 4); +} + +static void d68000_adda_16(m68k_info *info) +{ + build_ea_a(info, M68K_INS_ADDA, 2); +} + +static void d68000_adda_32(m68k_info *info) +{ + build_ea_a(info, M68K_INS_ADDA, 4); +} + +static void d68000_addi_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ADDI, 1, read_imm_8(info)); +} + +static void d68000_addi_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ADDI, 2, read_imm_16(info)); +} + +static void d68000_addi_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ADDI, 4, read_imm_32(info)); +} + +static void d68000_addq_8(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_ADDQ, 1); +} + +static void d68000_addq_16(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_ADDQ, 2); +} + +static void d68000_addq_32(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_ADDQ, 4); +} + +static void d68000_addx_rr_8(m68k_info *info) +{ + build_rr(info, M68K_INS_ADDX, 1, 0); +} + +static void d68000_addx_rr_16(m68k_info *info) +{ + build_rr(info, M68K_INS_ADDX, 2, 0); +} + +static void d68000_addx_rr_32(m68k_info *info) +{ + build_rr(info, M68K_INS_ADDX, 4, 0); +} + +static void d68000_addx_mm_8(m68k_info *info) +{ + build_mm(info, M68K_INS_ADDX, 1, 0); +} + +static void d68000_addx_mm_16(m68k_info *info) +{ + build_mm(info, M68K_INS_ADDX, 2, 0); +} + +static void d68000_addx_mm_32(m68k_info *info) +{ + build_mm(info, M68K_INS_ADDX, 4, 0); +} + +static void d68000_and_er_8(m68k_info *info) +{ + build_er_1(info, M68K_INS_AND, 1); +} + +static void d68000_and_er_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_AND, 2); +} + +static void d68000_and_er_32(m68k_info *info) +{ + build_er_1(info, M68K_INS_AND, 4); +} + +static void d68000_and_re_8(m68k_info *info) +{ + build_re_1(info, M68K_INS_AND, 1); +} + +static void d68000_and_re_16(m68k_info *info) +{ + build_re_1(info, M68K_INS_AND, 2); +} + +static void d68000_and_re_32(m68k_info *info) +{ + build_re_1(info, M68K_INS_AND, 4); +} + +static void d68000_andi_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ANDI, 1, read_imm_8(info)); +} + +static void d68000_andi_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ANDI, 2, read_imm_16(info)); +} + +static void d68000_andi_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ANDI, 4, read_imm_32(info)); +} + +static void d68000_andi_to_ccr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_ANDI, read_imm_8(info), 1, M68K_REG_CCR); +} + +static void d68000_andi_to_sr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_ANDI, read_imm_16(info), 2, M68K_REG_SR); +} + +static void d68000_asr_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASR, 1); +} + +static void d68000_asr_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASR, 2); +} + +static void d68000_asr_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASR, 4); +} + +static void d68000_asr_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_ASR, 1); +} + +static void d68000_asr_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ASR, 2); +} + +static void d68000_asr_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ASR, 4); +} + +static void d68000_asr_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ASR, 2); +} + +static void d68000_asl_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASL, 1); +} + +static void d68000_asl_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASL, 2); +} + +static void d68000_asl_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ASL, 4); +} + +static void d68000_asl_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_ASL, 1); +} + +static void d68000_asl_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ASL, 2); +} + +static void d68000_asl_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ASL, 4); +} + +static void d68000_asl_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ASL, 2); +} + +static void d68000_bcc_8(m68k_info *info) +{ + build_bcc(info, 1, make_int_8(info->ir)); +} + +static void d68000_bcc_16(m68k_info *info) +{ + build_bcc(info, 2, make_int_16(read_imm_16(info))); +} + +static void d68020_bcc_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bcc(info, 4, read_imm_32(info)); +} + +static void d68000_bchg_r(m68k_info *info) +{ + build_re_1(info, M68K_INS_BCHG, 1); +} + +static void d68000_bchg_s(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_BCHG, 1, read_imm_8(info)); +} + +static void d68000_bclr_r(m68k_info *info) +{ + build_re_1(info, M68K_INS_BCLR, 1); +} + +static void d68000_bclr_s(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_BCLR, 1, read_imm_8(info)); +} + +static void d68010_bkpt(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_absolute_jump_with_immediate(info, M68K_INS_BKPT, 0, info->ir & 7); +} + +static void d68020_bfchg(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFCHG, false); +} + + +static void d68020_bfclr(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFCLR, false); +} + +static void d68020_bfexts(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFEXTS, true); +} + +static void d68020_bfextu(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFEXTU, true); +} + +static void d68020_bfffo(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFFFO, true); +} + +static void d68020_bfins(m68k_info *info) +{ + cs_m68k* ext = &info->extension; + cs_m68k_op temp; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFINS, true); + + // a bit hacky but we need to flip the args on only this instruction + + temp = ext->operands[0]; + ext->operands[0] = ext->operands[1]; + ext->operands[1] = temp; +} + +static void d68020_bfset(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_bitfield_ins(info, M68K_INS_BFSET, false); +} + +static void d68020_bftst(m68k_info *info) +{ + build_bitfield_ins(info, M68K_INS_BFTST, false); +} + +static void d68000_bra_8(m68k_info *info) +{ + build_relative_branch(info, M68K_INS_BRA, 1, make_int_8(info->ir)); +} + +static void d68000_bra_16(m68k_info *info) +{ + build_relative_branch(info, M68K_INS_BRA, 2, make_int_16(read_imm_16(info))); +} + +static void d68020_bra_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_relative_branch(info, M68K_INS_BRA, 4, read_imm_32(info)); +} + +static void d68000_bset_r(m68k_info *info) +{ + build_re_1(info, M68K_INS_BSET, 1); +} + +static void d68000_bset_s(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_BSET, 1, read_imm_8(info)); +} + +static void d68000_bsr_8(m68k_info *info) +{ + build_relative_branch(info, M68K_INS_BSR, 1, make_int_8(info->ir)); +} + +static void d68000_bsr_16(m68k_info *info) +{ + build_relative_branch(info, M68K_INS_BSR, 2, make_int_16(read_imm_16(info))); +} + +static void d68020_bsr_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_relative_branch(info, M68K_INS_BSR, 4, peek_imm_32(info)); +} + +static void d68000_btst_r(m68k_info *info) +{ + build_re_1(info, M68K_INS_BTST, 4); +} + +static void d68000_btst_s(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_BTST, 1, read_imm_8(info)); +} + +static void d68020_callm(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_ONLY); + build_imm_ea(info, M68K_INS_CALLM, 0, read_imm_8(info)); +} + +static void d68020_cas_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_d_d_ea(info, M68K_INS_CAS, 1); +} + +static void d68020_cas_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_d_d_ea(info, M68K_INS_CAS, 2); +} + +static void d68020_cas_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_d_d_ea(info, M68K_INS_CAS, 4); +} + +static void d68020_cas2_16(m68k_info *info) +{ + build_cas2(info, 2); +} + +static void d68020_cas2_32(m68k_info *info) +{ + build_cas2(info, 4); +} + +static void d68000_chk_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_CHK, 2); +} + +static void d68020_chk_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_er_1(info, M68K_INS_CHK, 4); +} + +static void d68020_chk2_cmp2_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_chk2_cmp2(info, 1); +} + +static void d68020_chk2_cmp2_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_chk2_cmp2(info, 2); +} + +static void d68020_chk2_cmp2_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_chk2_cmp2(info, 4); +} + +static void d68040_cinv(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68040_PLUS); + build_cpush_cinv(info, M68K_INS_CINVL); +} + +static void d68000_clr_8(m68k_info *info) +{ + build_ea(info, M68K_INS_CLR, 1); +} + +static void d68000_clr_16(m68k_info *info) +{ + build_ea(info, M68K_INS_CLR, 2); +} + +static void d68000_clr_32(m68k_info *info) +{ + build_ea(info, M68K_INS_CLR, 4); +} + +static void d68000_cmp_8(m68k_info *info) +{ + build_er_1(info, M68K_INS_CMP, 1); +} + +static void d68000_cmp_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_CMP, 2); +} + +static void d68000_cmp_32(m68k_info *info) +{ + build_er_1(info, M68K_INS_CMP, 4); +} + +static void d68000_cmpa_16(m68k_info *info) +{ + build_ea_a(info, M68K_INS_CMPA, 2); +} + +static void d68000_cmpa_32(m68k_info *info) +{ + build_ea_a(info, M68K_INS_CMPA, 4); +} + +static void d68000_cmpi_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); +} + +static void d68020_cmpi_pcdi_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); +} + +static void d68020_cmpi_pcix_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); +} + +static void d68000_cmpi_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); +} + +static void d68020_cmpi_pcdi_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); +} + +static void d68020_cmpi_pcix_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); +} + +static void d68000_cmpi_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); +} + +static void d68020_cmpi_pcdi_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); +} + +static void d68020_cmpi_pcix_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); +} + +static void d68000_cmpm_8(m68k_info *info) +{ + build_pi_pi(info, M68K_INS_CMPM, 1); +} + +static void d68000_cmpm_16(m68k_info *info) +{ + build_pi_pi(info, M68K_INS_CMPM, 2); +} + +static void d68000_cmpm_32(m68k_info *info) +{ + build_pi_pi(info, M68K_INS_CMPM, 4); +} + +static void make_cpbcc_operand(cs_m68k_op* op, int size, int displacement) +{ + op->address_mode = M68K_AM_BRANCH_DISPLACEMENT; + op->type = M68K_OP_BR_DISP; + op->br_disp.disp = displacement; + op->br_disp.disp_size = size; +} + +static void d68020_cpbcc_16(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k* ext; + LIMIT_CPU_TYPES(info, M68020_PLUS); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (info->ir & 0x2f); + + ext = build_init_op(info, M68K_INS_FBF, 1, 2); + op0 = &ext->operands[0]; + + make_cpbcc_operand(op0, M68K_OP_BR_DISP_SIZE_WORD, make_int_16(read_imm_16(info))); + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static void d68020_cpbcc_32(m68k_info *info) +{ + cs_m68k* ext; + cs_m68k_op* op0; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (info->ir & 0x2f); + + ext = build_init_op(info, M68K_INS_FBF, 1, 4); + op0 = &ext->operands[0]; + + make_cpbcc_operand(op0, M68K_OP_BR_DISP_SIZE_LONG, read_imm_32(info)); + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static void d68020_cpdbcc(m68k_info *info) +{ + cs_m68k* ext; + cs_m68k_op* op0; + cs_m68k_op* op1; + uint ext1, ext2; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + ext1 = read_imm_16(info); + ext2 = read_imm_16(info); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (ext1 & 0x2f); + + ext = build_init_op(info, M68K_INS_FDBF, 2, 0); + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->reg = M68K_REG_D0 + (info->ir & 7); + + make_cpbcc_operand(op1, M68K_OP_BR_DISP_SIZE_WORD, make_int_16(ext2) + 2); + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static void fmove_fpcr(m68k_info *info, uint extension) +{ + cs_m68k_op* special; + cs_m68k_op* op_ea; + + int regsel = (extension >> 10) & 0x7; + int dir = (extension >> 13) & 0x1; + + cs_m68k* ext = build_init_op(info, M68K_INS_FMOVE, 2, 4); + + special = &ext->operands[0]; + op_ea = &ext->operands[1]; + + if (!dir) { + cs_m68k_op* t = special; + special = op_ea; + op_ea = t; + } + + get_ea_mode_op(info, op_ea, info->ir, 4); + + if (regsel & 4) + special->reg = M68K_REG_FPCR; + else if (regsel & 2) + special->reg = M68K_REG_FPSR; + else if (regsel & 1) + special->reg = M68K_REG_FPIAR; +} + +static void fmovem(m68k_info *info, uint extension) +{ + cs_m68k_op* op_reglist; + cs_m68k_op* op_ea; + int dir = (extension >> 13) & 0x1; + int mode = (extension >> 11) & 0x3; + uint reglist = extension & 0xff; + cs_m68k* ext = build_init_op(info, M68K_INS_FMOVEM, 2, 0); + + op_reglist = &ext->operands[0]; + op_ea = &ext->operands[1]; + + // flip args around + + if (!dir) { + cs_m68k_op* t = op_reglist; + op_reglist = op_ea; + op_ea = t; + } + + get_ea_mode_op(info, op_ea, info->ir, 0); + + switch (mode) { + case 1 : // Dynamic list in dn register + op_reglist->reg = M68K_REG_D0 + ((reglist >> 4) & 7); + break; + + case 0 : + op_reglist->address_mode = M68K_AM_NONE; + op_reglist->type = M68K_OP_REG_BITS; + op_reglist->register_bits = reglist << 16; + break; + + case 2 : // Static list + op_reglist->address_mode = M68K_AM_NONE; + op_reglist->type = M68K_OP_REG_BITS; + op_reglist->register_bits = ((uint32_t)reverse_bits_8(reglist)) << 16; + break; + } +} + +static void d68020_cpgen(m68k_info *info) +{ + cs_m68k *ext; + cs_m68k_op* op0; + cs_m68k_op* op1; + bool supports_single_op; + uint next; + int rm, src, dst, opmode; + + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + supports_single_op = true; + + next = read_imm_16(info); + + rm = (next >> 14) & 0x1; + src = (next >> 10) & 0x7; + dst = (next >> 7) & 0x7; + opmode = next & 0x3f; + + // special handling for fmovecr + + if (BITFIELD(info->ir, 5, 0) == 0 && BITFIELD(next, 15, 10) == 0x17) { + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_IMMEDIATE; + op0->type = M68K_OP_IMM; + op0->imm = next & 0x3f; + + op1->reg = M68K_REG_FP0 + ((next >> 7) & 7); + + return; + } + + // deal with extended move stuff + + switch ((next >> 13) & 0x7) { + // fmovem fpcr + case 0x4: // FMOVEM ea, FPCR + case 0x5: // FMOVEM FPCR, ea + fmove_fpcr(info, next); + return; + + // fmovem list + case 0x6: + case 0x7: + fmovem(info, next); + return; + } + + // See comment bellow on why this is being done + + if ((next >> 6) & 1) + opmode &= ~4; + + // special handling of some instructions here + + switch (opmode) { + case 0x00: MCInst_setOpcode(info->inst, M68K_INS_FMOVE); supports_single_op = false; break; + case 0x01: MCInst_setOpcode(info->inst, M68K_INS_FINT); break; + case 0x02: MCInst_setOpcode(info->inst, M68K_INS_FSINH); break; + case 0x03: MCInst_setOpcode(info->inst, M68K_INS_FINTRZ); break; + case 0x04: MCInst_setOpcode(info->inst, M68K_INS_FSQRT); break; + case 0x06: MCInst_setOpcode(info->inst, M68K_INS_FLOGNP1); break; + case 0x08: MCInst_setOpcode(info->inst, M68K_INS_FETOXM1); break; + case 0x09: MCInst_setOpcode(info->inst, M68K_INS_FATANH); break; + case 0x0a: MCInst_setOpcode(info->inst, M68K_INS_FATAN); break; + case 0x0c: MCInst_setOpcode(info->inst, M68K_INS_FASIN); break; + case 0x0d: MCInst_setOpcode(info->inst, M68K_INS_FATANH); break; + case 0x0e: MCInst_setOpcode(info->inst, M68K_INS_FSIN); break; + case 0x0f: MCInst_setOpcode(info->inst, M68K_INS_FTAN); break; + case 0x10: MCInst_setOpcode(info->inst, M68K_INS_FETOX); break; + case 0x11: MCInst_setOpcode(info->inst, M68K_INS_FTWOTOX); break; + case 0x12: MCInst_setOpcode(info->inst, M68K_INS_FTENTOX); break; + case 0x14: MCInst_setOpcode(info->inst, M68K_INS_FLOGN); break; + case 0x15: MCInst_setOpcode(info->inst, M68K_INS_FLOG10); break; + case 0x16: MCInst_setOpcode(info->inst, M68K_INS_FLOG2); break; + case 0x18: MCInst_setOpcode(info->inst, M68K_INS_FABS); break; + case 0x19: MCInst_setOpcode(info->inst, M68K_INS_FCOSH); break; + case 0x1a: MCInst_setOpcode(info->inst, M68K_INS_FNEG); break; + case 0x1c: MCInst_setOpcode(info->inst, M68K_INS_FACOS); break; + case 0x1d: MCInst_setOpcode(info->inst, M68K_INS_FCOS); break; + case 0x1e: MCInst_setOpcode(info->inst, M68K_INS_FGETEXP); break; + case 0x1f: MCInst_setOpcode(info->inst, M68K_INS_FGETMAN); break; + case 0x20: MCInst_setOpcode(info->inst, M68K_INS_FDIV); supports_single_op = false; break; + case 0x21: MCInst_setOpcode(info->inst, M68K_INS_FMOD); supports_single_op = false; break; + case 0x22: MCInst_setOpcode(info->inst, M68K_INS_FADD); supports_single_op = false; break; + case 0x23: MCInst_setOpcode(info->inst, M68K_INS_FMUL); supports_single_op = false; break; + case 0x24: MCInst_setOpcode(info->inst, M68K_INS_FSGLDIV); supports_single_op = false; break; + case 0x25: MCInst_setOpcode(info->inst, M68K_INS_FREM); break; + case 0x26: MCInst_setOpcode(info->inst, M68K_INS_FSCALE); break; + case 0x27: MCInst_setOpcode(info->inst, M68K_INS_FSGLMUL); break; + case 0x28: MCInst_setOpcode(info->inst, M68K_INS_FSUB); supports_single_op = false; break; + case 0x38: MCInst_setOpcode(info->inst, M68K_INS_FCMP); supports_single_op = false; break; + case 0x3a: MCInst_setOpcode(info->inst, M68K_INS_FTST); break; + default: + break; + } + + // Some trickery here! It's not documented but if bit 6 is set this is a s/d opcode and then + // if bit 2 is set it's a d. As we already have set our opcode in the code above we can just + // offset it as the following 2 op codes (if s/d is supported) will always be directly after it + + if ((next >> 6) & 1) { + if ((next >> 2) & 1) + info->inst->Opcode += 2; + else + info->inst->Opcode += 1; + } + + ext = &info->extension; + + ext->op_count = 2; + ext->op_size.type = M68K_SIZE_TYPE_CPU; + ext->op_size.cpu_size = 0; + + // Special case - adjust direction of fmove + if ((opmode == 0x00) && ((next >> 13) & 0x1) != 0) { + op0 = &ext->operands[1]; + op1 = &ext->operands[0]; + } else { + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + } + + if (rm == 0 && supports_single_op && src == dst) { + ext->op_count = 1; + op0->reg = M68K_REG_FP0 + dst; + return; + } + + if (rm == 1) { + switch (src) { + case 0x00 : + ext->op_size.cpu_size = M68K_CPU_SIZE_LONG; + get_ea_mode_op(info, op0, info->ir, 4); + break; + + case 0x06 : + ext->op_size.cpu_size = M68K_CPU_SIZE_BYTE; + get_ea_mode_op(info, op0, info->ir, 1); + break; + + case 0x04 : + ext->op_size.cpu_size = M68K_CPU_SIZE_WORD; + get_ea_mode_op(info, op0, info->ir, 2); + break; + + case 0x01 : + ext->op_size.type = M68K_SIZE_TYPE_FPU; + ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE; + get_ea_mode_op(info, op0, info->ir, 4); + op0->type = M68K_OP_FP_SINGLE; + break; + + case 0x05: + ext->op_size.type = M68K_SIZE_TYPE_FPU; + ext->op_size.fpu_size = M68K_FPU_SIZE_DOUBLE; + get_ea_mode_op(info, op0, info->ir, 8); + op0->type = M68K_OP_FP_DOUBLE; + break; + + default : + ext->op_size.type = M68K_SIZE_TYPE_FPU; + ext->op_size.fpu_size = M68K_FPU_SIZE_EXTENDED; + break; + } + } else { + op0->reg = M68K_REG_FP0 + src; + } + + op1->reg = M68K_REG_FP0 + dst; +} + +static void d68020_cprestore(m68k_info *info) +{ + cs_m68k* ext; + LIMIT_CPU_TYPES(info, M68020_PLUS); + + ext = build_init_op(info, M68K_INS_FRESTORE, 1, 0); + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); +} + +static void d68020_cpsave(m68k_info *info) +{ + cs_m68k* ext; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + ext = build_init_op(info, M68K_INS_FSAVE, 1, 0); + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); +} + +static void d68020_cpscc(m68k_info *info) +{ + cs_m68k* ext; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + ext = build_init_op(info, M68K_INS_FSF, 1, 1); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (read_imm_16(info) & 0x2f); + + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); +} + +static void d68020_cptrapcc_0(m68k_info *info) +{ + uint extension1; + LIMIT_CPU_TYPES(info, M68020_PLUS); + + extension1 = read_imm_16(info); + + build_init_op(info, M68K_INS_FTRAPF, 0, 0); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (extension1 & 0x2f); +} + +static void d68020_cptrapcc_16(m68k_info *info) +{ + uint extension1, extension2; + cs_m68k_op* op0; + cs_m68k* ext; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + extension1 = read_imm_16(info); + extension2 = read_imm_16(info); + + ext = build_init_op(info, M68K_INS_FTRAPF, 1, 2); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (extension1 & 0x2f); + + op0 = &ext->operands[0]; + + op0->address_mode = M68K_AM_IMMEDIATE; + op0->type = M68K_OP_IMM; + op0->imm = extension2; +} + +static void d68020_cptrapcc_32(m68k_info *info) +{ + uint extension1, extension2; + cs_m68k* ext; + cs_m68k_op* op0; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + extension1 = read_imm_16(info); + extension2 = read_imm_32(info); + + ext = build_init_op(info, M68K_INS_FTRAPF, 1, 2); + + // these are all in row with the extension so just doing a add here is fine + info->inst->Opcode += (extension1 & 0x2f); + + op0 = &ext->operands[0]; + + op0->address_mode = M68K_AM_IMMEDIATE; + op0->type = M68K_OP_IMM; + op0->imm = extension2; +} + +static void d68040_cpush(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68040_PLUS); + build_cpush_cinv(info, M68K_INS_CPUSHL); +} + +static void d68000_dbra(m68k_info *info) +{ + build_dbxx(info, M68K_INS_DBRA, 0, make_int_16(read_imm_16(info))); +} + +static void d68000_dbcc(m68k_info *info) +{ + build_dbcc(info, 0, make_int_16(read_imm_16(info))); +} + +static void d68000_divs(m68k_info *info) +{ + build_er_1(info, M68K_INS_DIVS, 2); +} + +static void d68000_divu(m68k_info *info) +{ + build_er_1(info, M68K_INS_DIVU, 2); +} + +static void d68020_divl(m68k_info *info) +{ + uint extension, insn_signed; + cs_m68k* ext; + cs_m68k_op* op0; + cs_m68k_op* op1; + uint reg_0, reg_1; + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + extension = read_imm_16(info); + insn_signed = 0; + + if (BIT_B((extension))) + insn_signed = 1; + + ext = build_init_op(info, insn_signed ? M68K_INS_DIVS : M68K_INS_DIVU, 2, 4); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, 4); + + reg_0 = extension & 7; + reg_1 = (extension >> 12) & 7; + + op1->address_mode = M68K_AM_NONE; + op1->type = M68K_OP_REG_PAIR; + op1->reg_pair.reg_0 = reg_0; + op1->reg_pair.reg_1 = reg_1; + + if ((reg_0 == reg_1) || !BIT_A(extension)) { + op1->type = M68K_OP_REG; + op1->reg = M68K_REG_D0 + reg_1; + } +} + +static void d68000_eor_8(m68k_info *info) +{ + build_re_1(info, M68K_INS_EOR, 1); +} + +static void d68000_eor_16(m68k_info *info) +{ + build_re_1(info, M68K_INS_EOR, 2); +} + +static void d68000_eor_32(m68k_info *info) +{ + build_re_1(info, M68K_INS_EOR, 4); +} + +static void d68000_eori_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_EORI, 1, read_imm_8(info)); +} + +static void d68000_eori_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_EORI, 2, read_imm_16(info)); +} + +static void d68000_eori_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_EORI, 4, read_imm_32(info)); +} + +static void d68000_eori_to_ccr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_EORI, read_imm_8(info), 1, M68K_REG_CCR); +} + +static void d68000_eori_to_sr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_EORI, read_imm_16(info), 2, M68K_REG_SR); +} + +static void d68000_exg_dd(m68k_info *info) +{ + build_r(info, M68K_INS_EXG, 4); +} + +static void d68000_exg_aa(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_EXG, 2, 4); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_A0 + (info->ir & 7); +} + +static void d68000_exg_da(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_EXG, 2, 4); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_A0 + (info->ir & 7); +} + +static void d68000_ext_16(m68k_info *info) +{ + build_d(info, M68K_INS_EXT, 2); +} + +static void d68000_ext_32(m68k_info *info) +{ + build_d(info, M68K_INS_EXT, 4); +} + +static void d68020_extb_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_d(info, M68K_INS_EXTB, 4); +} + +static void d68000_jmp(m68k_info *info) +{ + cs_m68k* ext = build_init_op(info, M68K_INS_JMP, 1, 0); + set_insn_group(info, M68K_GRP_JUMP); + get_ea_mode_op(info, &ext->operands[0], info->ir, 4); +} + +static void d68000_jsr(m68k_info *info) +{ + cs_m68k* ext = build_init_op(info, M68K_INS_JSR, 1, 0); + set_insn_group(info, M68K_GRP_JUMP); + get_ea_mode_op(info, &ext->operands[0], info->ir, 4); +} + +static void d68000_lea(m68k_info *info) +{ + build_ea_a(info, M68K_INS_LEA, 4); +} + +static void d68000_link_16(m68k_info *info) +{ + build_link(info, read_imm_16(info), 2); +} + +static void d68020_link_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_link(info, read_imm_32(info), 4); +} + +static void d68000_lsr_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSR, 1); +} + +static void d68000_lsr_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSR, 2); +} + +static void d68000_lsr_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSR, 4); +} + +static void d68000_lsr_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_LSR, 1); +} + +static void d68000_lsr_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_LSR, 2); +} + +static void d68000_lsr_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_LSR, 4); +} + +static void d68000_lsr_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_LSR, 2); +} + +static void d68000_lsl_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSL, 1); +} + +static void d68000_lsl_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSL, 2); +} + +static void d68000_lsl_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_LSL, 4); +} + +static void d68000_lsl_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_LSL, 1); +} + +static void d68000_lsl_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_LSL, 2); +} + +static void d68000_lsl_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_LSL, 4); +} + +static void d68000_lsl_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_LSL, 2); +} + +static void d68000_move_8(m68k_info *info) +{ + build_ea_ea(info, M68K_INS_MOVE, 1); +} + +static void d68000_move_16(m68k_info *info) +{ + build_ea_ea(info, M68K_INS_MOVE, 2); +} + +static void d68000_move_32(m68k_info *info) +{ + build_ea_ea(info, M68K_INS_MOVE, 4); +} + +static void d68000_movea_16(m68k_info *info) +{ + build_ea_a(info, M68K_INS_MOVEA, 2); +} + +static void d68000_movea_32(m68k_info *info) +{ + build_ea_a(info, M68K_INS_MOVEA, 4); +} + +static void d68000_move_to_ccr(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, 1); + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_CCR; +} + +static void d68010_move_fr_ccr(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext; + + LIMIT_CPU_TYPES(info, M68010_PLUS); + + ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_CCR; + + get_ea_mode_op(info, op1, info->ir, 1); +} + +static void d68000_move_fr_sr(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_SR; + + get_ea_mode_op(info, op1, info->ir, 2); +} + +static void d68000_move_to_sr(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, 2); + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_SR; +} + +static void d68000_move_fr_usp(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 0); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_USP; + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_A0 + (info->ir & 7); +} + +static void d68000_move_to_usp(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 0); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->address_mode = M68K_AM_NONE; + op0->reg = M68K_REG_A0 + (info->ir & 7); + + op1->address_mode = M68K_AM_NONE; + op1->reg = M68K_REG_USP; +} + +static void d68010_movec(m68k_info *info) +{ + uint extension; + m68k_reg reg; + cs_m68k* ext; + cs_m68k_op* op0; + cs_m68k_op* op1; + + + LIMIT_CPU_TYPES(info, M68010_PLUS); + + extension = read_imm_16(info); + reg = M68K_REG_INVALID; + + ext = build_init_op(info, M68K_INS_MOVEC, 2, 0); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + switch (extension & 0xfff) { + case 0x000: reg = M68K_REG_SFC; break; + case 0x001: reg = M68K_REG_DFC; break; + case 0x800: reg = M68K_REG_USP; break; + case 0x801: reg = M68K_REG_VBR; break; + case 0x002: reg = M68K_REG_CACR; break; + case 0x802: reg = M68K_REG_CAAR; break; + case 0x803: reg = M68K_REG_MSP; break; + case 0x804: reg = M68K_REG_ISP; break; + case 0x003: reg = M68K_REG_TC; break; + case 0x004: reg = M68K_REG_ITT0; break; + case 0x005: reg = M68K_REG_ITT1; break; + case 0x006: reg = M68K_REG_DTT0; break; + case 0x007: reg = M68K_REG_DTT1; break; + case 0x805: reg = M68K_REG_MMUSR; break; + case 0x806: reg = M68K_REG_URP; break; + case 0x807: reg = M68K_REG_SRP; break; + } + + if (BIT_1(info->ir)) { + op0->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); + op1->reg = reg; + } else { + op0->reg = reg; + op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); + } +} + +static void d68000_movem_pd_16(m68k_info *info) +{ + build_movem_re(info, M68K_INS_MOVEM, 2); +} + +static void d68000_movem_pd_32(m68k_info *info) +{ + build_movem_re(info, M68K_INS_MOVEM, 4); +} + +static void d68000_movem_er_16(m68k_info *info) +{ + build_movem_er(info, M68K_INS_MOVEM, 2); +} + +static void d68000_movem_er_32(m68k_info *info) +{ + build_movem_er(info, M68K_INS_MOVEM, 4); +} + +static void d68000_movem_re_16(m68k_info *info) +{ + build_movem_re(info, M68K_INS_MOVEM, 2); +} + +static void d68000_movem_re_32(m68k_info *info) +{ + build_movem_re(info, M68K_INS_MOVEM, 4); +} + +static void d68000_movep_re_16(m68k_info *info) +{ + build_movep_re(info, 2); +} + +static void d68000_movep_re_32(m68k_info *info) +{ + build_movep_re(info, 4); +} + +static void d68000_movep_er_16(m68k_info *info) +{ + build_movep_er(info, 2); +} + +static void d68000_movep_er_32(m68k_info *info) +{ + build_movep_er(info, 4); +} + +static void d68010_moves_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_moves(info, 1); +} + +static void d68010_moves_16(m68k_info *info) +{ + //uint extension; + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_moves(info, 2); +} + +static void d68010_moves_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_moves(info, 4); +} + +static void d68000_moveq(m68k_info *info) +{ + cs_m68k_op* op0; + cs_m68k_op* op1; + + cs_m68k* ext = build_init_op(info, M68K_INS_MOVEQ, 2, 0); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + op0->type = M68K_OP_IMM; + op0->address_mode = M68K_AM_IMMEDIATE; + op0->imm = (info->ir & 0xff); + + op1->address_mode = M68K_AM_REG_DIRECT_DATA; + op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); +} + +static void d68040_move16_pi_pi(m68k_info *info) +{ + int data[] = { info->ir & 7, (read_imm_16(info) >> 12) & 7 }; + int modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_REGI_ADDR_POST_INC }; + + LIMIT_CPU_TYPES(info, M68040_PLUS); + + build_move16(info, data, modes); +} + +static void d68040_move16_pi_al(m68k_info *info) +{ + int data[] = { info->ir & 7, read_imm_32(info) }; + int modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_ABSOLUTE_DATA_LONG }; + + LIMIT_CPU_TYPES(info, M68040_PLUS); + + build_move16(info, data, modes); +} + +static void d68040_move16_al_pi(m68k_info *info) +{ + int data[] = { read_imm_32(info), info->ir & 7 }; + int modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REGI_ADDR_POST_INC }; + + LIMIT_CPU_TYPES(info, M68040_PLUS); + + build_move16(info, data, modes); +} + +static void d68040_move16_ai_al(m68k_info *info) +{ + int data[] = { info->ir & 7, read_imm_32(info) }; + int modes[] = { M68K_AM_REG_DIRECT_ADDR, M68K_AM_ABSOLUTE_DATA_LONG }; + + LIMIT_CPU_TYPES(info, M68040_PLUS); + + build_move16(info, data, modes); +} + +static void d68040_move16_al_ai(m68k_info *info) +{ + int data[] = { read_imm_32(info), info->ir & 7 }; + int modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REG_DIRECT_ADDR }; + + LIMIT_CPU_TYPES(info, M68040_PLUS); + + build_move16(info, data, modes); +} + +static void d68000_muls(m68k_info *info) +{ + build_er_1(info, M68K_INS_MULS, 2); +} + +static void d68000_mulu(m68k_info *info) +{ + build_er_1(info, M68K_INS_MULU, 2); +} + +static void d68020_mull(m68k_info *info) +{ + uint extension, insn_signed; + cs_m68k* ext; + cs_m68k_op* op0; + cs_m68k_op* op1; + uint reg_0, reg_1; + + + LIMIT_CPU_TYPES(info, M68020_PLUS); + + extension = read_imm_16(info); + insn_signed = 0; + + if (BIT_B((extension))) + insn_signed = 1; + + ext = build_init_op(info, insn_signed ? M68K_INS_MULS : M68K_INS_MULU, 2, 4); + + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + get_ea_mode_op(info, op0, info->ir, 4); + + reg_0 = extension & 7; + reg_1 = (extension >> 12) & 7; + + op1->address_mode = M68K_AM_NONE; + op1->type = M68K_OP_REG_PAIR; + op1->reg_pair.reg_0 = reg_0; + op1->reg_pair.reg_1 = reg_1; + + if (!BIT_A(extension)) { + op1->type = M68K_OP_REG; + op1->reg = M68K_REG_D0 + reg_1; + } +} + +static void d68000_nbcd(m68k_info *info) +{ + build_ea(info, M68K_INS_NBCD, 1); +} + +static void d68000_neg_8(m68k_info *info) +{ + build_ea(info, M68K_INS_NEG, 1); +} + +static void d68000_neg_16(m68k_info *info) +{ + build_ea(info, M68K_INS_NEG, 2); +} + +static void d68000_neg_32(m68k_info *info) +{ + build_ea(info, M68K_INS_NEG, 4); +} + +static void d68000_negx_8(m68k_info *info) +{ + build_ea(info, M68K_INS_NEGX, 1); +} + +static void d68000_negx_16(m68k_info *info) +{ + build_ea(info, M68K_INS_NEGX, 2); +} + +static void d68000_negx_32(m68k_info *info) +{ + build_ea(info, M68K_INS_NEGX, 4); +} + +static void d68000_nop(m68k_info *info) +{ + MCInst_setOpcode(info->inst, M68K_INS_NOP); +} + +static void d68000_not_8(m68k_info *info) +{ + build_ea(info, M68K_INS_NOT, 1); +} + +static void d68000_not_16(m68k_info *info) +{ + build_ea(info, M68K_INS_NOT, 2); +} + +static void d68000_not_32(m68k_info *info) +{ + build_ea(info, M68K_INS_NOT, 4); +} + +static void d68000_or_er_8(m68k_info *info) +{ + build_er_1(info, M68K_INS_OR, 1); +} + +static void d68000_or_er_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_OR, 2); +} + +static void d68000_or_er_32(m68k_info *info) +{ + build_er_1(info, M68K_INS_OR, 4); +} + +static void d68000_or_re_8(m68k_info *info) +{ + build_re_1(info, M68K_INS_OR, 1); +} + +static void d68000_or_re_16(m68k_info *info) +{ + build_re_1(info, M68K_INS_OR, 2); +} + +static void d68000_or_re_32(m68k_info *info) +{ + build_re_1(info, M68K_INS_OR, 4); +} + +static void d68000_ori_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ORI, 1, read_imm_8(info)); +} + +static void d68000_ori_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ORI, 2, read_imm_16(info)); +} + +static void d68000_ori_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_ORI, 4, read_imm_32(info)); +} + +static void d68000_ori_to_ccr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_ORI, read_imm_8(info), 1, M68K_REG_CCR); +} + +static void d68000_ori_to_sr(m68k_info *info) +{ + build_imm_special_reg(info, M68K_INS_ORI, read_imm_16(info), 2, M68K_REG_SR); +} + +static void d68020_pack_rr(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_rr(info, M68K_INS_PACK, 0, read_imm_16(info)); +} + +static void d68020_pack_mm(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_mm(info, M68K_INS_PACK, 0, read_imm_16(info)); +} + +static void d68000_pea(m68k_info *info) +{ + build_ea(info, M68K_INS_PEA, 4); +} + +static void d68000_reset(m68k_info *info) +{ + MCInst_setOpcode(info->inst, M68K_INS_RESET); +} + +static void d68000_ror_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROR, 1); +} + +static void d68000_ror_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROR, 2); +} + +static void d68000_ror_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROR, 4); +} + +static void d68000_ror_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_ROR, 1); +} + +static void d68000_ror_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ROR, 2); +} + +static void d68000_ror_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ROR, 4); +} + +static void d68000_ror_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ROR, 2); +} + +static void d68000_rol_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROL, 1); +} + +static void d68000_rol_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROL, 2); +} + +static void d68000_rol_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROL, 4); +} + +static void d68000_rol_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_ROL, 1); +} + +static void d68000_rol_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ROL, 2); +} + +static void d68000_rol_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ROL, 4); +} + +static void d68000_rol_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ROL, 2); +} + +static void d68000_roxr_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXR, 1); +} + +static void d68000_roxr_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXR, 2); +} + +static void d68000_roxr_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXR, 4); +} + +static void d68000_roxr_r_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXR, 4); +} + +static void d68000_roxr_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ROXR, 2); +} + +static void d68000_roxr_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ROXR, 4); +} + +static void d68000_roxr_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ROXR, 2); +} + +static void d68000_roxl_s_8(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXL, 1); +} + +static void d68000_roxl_s_16(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXL, 2); +} + +static void d68000_roxl_s_32(m68k_info *info) +{ + build_3bit_d(info, M68K_INS_ROXL, 4); +} + +static void d68000_roxl_r_8(m68k_info *info) +{ + build_r(info, M68K_INS_ROXL, 1); +} + +static void d68000_roxl_r_16(m68k_info *info) +{ + build_r(info, M68K_INS_ROXL, 2); +} + +static void d68000_roxl_r_32(m68k_info *info) +{ + build_r(info, M68K_INS_ROXL, 4); +} + +static void d68000_roxl_ea(m68k_info *info) +{ + build_ea(info, M68K_INS_ROXL, 2); +} + +static void d68010_rtd(m68k_info *info) +{ + set_insn_group(info, M68K_GRP_RET); + LIMIT_CPU_TYPES(info, M68010_PLUS); + build_absolute_jump_with_immediate(info, M68K_INS_RTD, 0, read_imm_16(info)); +} + +static void d68000_rte(m68k_info *info) +{ + set_insn_group(info, M68K_GRP_IRET); + MCInst_setOpcode(info->inst, M68K_INS_RTE); +} + +static void d68020_rtm(m68k_info *info) +{ + cs_m68k* ext; + cs_m68k_op* op; + + set_insn_group(info, M68K_GRP_RET); + + LIMIT_CPU_TYPES(info, M68020_ONLY); + + build_absolute_jump_with_immediate(info, M68K_INS_RTM, 0, 0); + + ext = &info->extension; + op = &ext->operands[0]; + + op->address_mode = M68K_AM_NONE; + op->type = M68K_OP_REG; + + if (BIT_3(info->ir)) { + op->reg = M68K_REG_A0 + (info->ir & 7); + } else { + op->reg = M68K_REG_D0 + (info->ir & 7); + } +} + +static void d68000_rtr(m68k_info *info) +{ + set_insn_group(info, M68K_GRP_RET); + MCInst_setOpcode(info->inst, M68K_INS_RTR); +} + +static void d68000_rts(m68k_info *info) +{ + set_insn_group(info, M68K_GRP_RET); + MCInst_setOpcode(info->inst, M68K_INS_RTS); +} + +static void d68000_sbcd_rr(m68k_info *info) +{ + build_rr(info, M68K_INS_SBCD, 1, 0); +} + +static void d68000_sbcd_mm(m68k_info *info) +{ + build_mm(info, M68K_INS_SBCD, 0, read_imm_16(info)); +} + +static void d68000_scc(m68k_info *info) +{ + cs_m68k* ext = build_init_op(info, s_scc_lut[(info->ir >> 8) & 0xf], 1, 1); + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); +} + +static void d68000_stop(m68k_info *info) +{ + build_absolute_jump_with_immediate(info, M68K_INS_STOP, 0, read_imm_16(info)); +} + +static void d68000_sub_er_8(m68k_info *info) +{ + build_er_1(info, M68K_INS_SUB, 1); +} + +static void d68000_sub_er_16(m68k_info *info) +{ + build_er_1(info, M68K_INS_SUB, 2); +} + +static void d68000_sub_er_32(m68k_info *info) +{ + build_er_1(info, M68K_INS_SUB, 4); +} + +static void d68000_sub_re_8(m68k_info *info) +{ + build_re_1(info, M68K_INS_SUB, 1); +} + +static void d68000_sub_re_16(m68k_info *info) +{ + build_re_1(info, M68K_INS_SUB, 2); +} + +static void d68000_sub_re_32(m68k_info *info) +{ + build_re_1(info, M68K_INS_SUB, 4); +} + +static void d68000_suba_16(m68k_info *info) +{ + build_ea_a(info, M68K_INS_SUBA, 2); +} + +static void d68000_suba_32(m68k_info *info) +{ + build_ea_a(info, M68K_INS_SUBA, 4); +} + +static void d68000_subi_8(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_SUBI, 1, read_imm_8(info)); +} + +static void d68000_subi_16(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_SUBI, 2, read_imm_16(info)); +} + +static void d68000_subi_32(m68k_info *info) +{ + build_imm_ea(info, M68K_INS_SUBI, 4, read_imm_32(info)); +} + +static void d68000_subq_8(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_SUBQ, 1); +} + +static void d68000_subq_16(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_SUBQ, 2); +} + +static void d68000_subq_32(m68k_info *info) +{ + build_3bit_ea(info, M68K_INS_SUBQ, 4); +} + +static void d68000_subx_rr_8(m68k_info *info) +{ + build_rr(info, M68K_INS_SUBX, 1, 0); +} + +static void d68000_subx_rr_16(m68k_info *info) +{ + build_rr(info, M68K_INS_SUBX, 2, 0); +} + +static void d68000_subx_rr_32(m68k_info *info) +{ + build_rr(info, M68K_INS_SUBX, 4, 0); +} + +static void d68000_subx_mm_8(m68k_info *info) +{ + build_mm(info, M68K_INS_SUBX, 1, 0); +} + +static void d68000_subx_mm_16(m68k_info *info) +{ + build_mm(info, M68K_INS_SUBX, 2, 0); +} + +static void d68000_subx_mm_32(m68k_info *info) +{ + build_mm(info, M68K_INS_SUBX, 4, 0); +} + +static void d68000_swap(m68k_info *info) +{ + build_d(info, M68K_INS_SWAP, 0); +} + +static void d68000_tas(m68k_info *info) +{ + build_ea(info, M68K_INS_TAS, 1); +} + +static void d68000_trap(m68k_info *info) +{ + build_absolute_jump_with_immediate(info, M68K_INS_TRAP, 0, info->ir&0xf); +} + +static void d68020_trapcc_0(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_trap(info, 0, 0); + + info->extension.op_count = 0; +} + +static void d68020_trapcc_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_trap(info, 2, read_imm_16(info)); +} + +static void d68020_trapcc_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_trap(info, 4, read_imm_32(info)); +} + +static void d68000_trapv(m68k_info *info) +{ + MCInst_setOpcode(info->inst, M68K_INS_TRAPV); +} + +static void d68000_tst_8(m68k_info *info) +{ + build_ea(info, M68K_INS_TST, 1); +} + +static void d68020_tst_pcdi_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 1); +} + +static void d68020_tst_pcix_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 1); +} + +static void d68020_tst_i_8(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 1); +} + +static void d68000_tst_16(m68k_info *info) +{ + build_ea(info, M68K_INS_TST, 2); +} + +static void d68020_tst_a_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 2); +} + +static void d68020_tst_pcdi_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 2); +} + +static void d68020_tst_pcix_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 2); +} + +static void d68020_tst_i_16(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 2); +} + +static void d68000_tst_32(m68k_info *info) +{ + build_ea(info, M68K_INS_TST, 4); +} + +static void d68020_tst_a_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 4); +} + +static void d68020_tst_pcdi_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 4); +} + +static void d68020_tst_pcix_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 4); +} + +static void d68020_tst_i_32(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_ea(info, M68K_INS_TST, 4); +} + +static void d68000_unlk(m68k_info *info) +{ + cs_m68k_op* op; + cs_m68k* ext = build_init_op(info, M68K_INS_UNLK, 1, 0); + + op = &ext->operands[0]; + + op->address_mode = M68K_AM_REG_DIRECT_ADDR; + op->reg = M68K_REG_A0 + (info->ir & 7); +} + +static void d68020_unpk_rr(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_rr(info, M68K_INS_UNPK, 0, read_imm_16(info)); +} + +static void d68020_unpk_mm(m68k_info *info) +{ + LIMIT_CPU_TYPES(info, M68020_PLUS); + build_mm(info, M68K_INS_UNPK, 0, read_imm_16(info)); +} + +/* ======================================================================== */ +/* ======================= INSTRUCTION TABLE BUILDER ====================== */ +/* ======================================================================== */ + +/* EA Masks: + 800 = data register direct + 400 = address register direct + 200 = address register indirect + 100 = ARI postincrement + 80 = ARI pre-decrement + 40 = ARI displacement + 20 = ARI index + 10 = absolute short + 8 = absolute long + 4 = immediate / sr + 2 = pc displacement + 1 = pc idx + */ + +static opcode_struct g_opcode_info[] = { + /* opcode handler mask match ea_mask mask2 match2*/ + {d68000_1010 , 0xf000, 0xa000, 0x000}, + {d68000_1111 , 0xf000, 0xf000, 0x000}, + {d68000_abcd_rr , 0xf1f8, 0xc100, 0x000}, + {d68000_abcd_mm , 0xf1f8, 0xc108, 0x000}, + {d68000_add_er_8 , 0xf1c0, 0xd000, 0xbff}, + {d68000_add_er_16 , 0xf1c0, 0xd040, 0xfff}, + {d68000_add_er_32 , 0xf1c0, 0xd080, 0xfff}, + {d68000_add_re_8 , 0xf1c0, 0xd100, 0x3f8}, + {d68000_add_re_16 , 0xf1c0, 0xd140, 0x3f8}, + {d68000_add_re_32 , 0xf1c0, 0xd180, 0x3f8}, + {d68000_adda_16 , 0xf1c0, 0xd0c0, 0xfff}, + {d68000_adda_32 , 0xf1c0, 0xd1c0, 0xfff}, + {d68000_addi_8 , 0xffc0, 0x0600, 0xbf8}, + {d68000_addi_16 , 0xffc0, 0x0640, 0xbf8}, + {d68000_addi_32 , 0xffc0, 0x0680, 0xbf8}, + {d68000_addq_8 , 0xf1c0, 0x5000, 0xbf8}, + {d68000_addq_16 , 0xf1c0, 0x5040, 0xff8}, + {d68000_addq_32 , 0xf1c0, 0x5080, 0xff8}, + {d68000_addx_rr_8 , 0xf1f8, 0xd100, 0x000}, + {d68000_addx_rr_16 , 0xf1f8, 0xd140, 0x000}, + {d68000_addx_rr_32 , 0xf1f8, 0xd180, 0x000}, + {d68000_addx_mm_8 , 0xf1f8, 0xd108, 0x000}, + {d68000_addx_mm_16 , 0xf1f8, 0xd148, 0x000}, + {d68000_addx_mm_32 , 0xf1f8, 0xd188, 0x000}, + {d68000_and_er_8 , 0xf1c0, 0xc000, 0xbff}, + {d68000_and_er_16 , 0xf1c0, 0xc040, 0xbff}, + {d68000_and_er_32 , 0xf1c0, 0xc080, 0xbff}, + {d68000_and_re_8 , 0xf1c0, 0xc100, 0x3f8}, + {d68000_and_re_16 , 0xf1c0, 0xc140, 0x3f8}, + {d68000_and_re_32 , 0xf1c0, 0xc180, 0x3f8}, + {d68000_andi_to_ccr , 0xffff, 0x023c, 0x000, 0xff00, 0x0000}, + {d68000_andi_to_sr , 0xffff, 0x027c, 0x000}, + {d68000_andi_8 , 0xffc0, 0x0200, 0xbf8}, + {d68000_andi_16 , 0xffc0, 0x0240, 0xbf8}, + {d68000_andi_32 , 0xffc0, 0x0280, 0xbf8}, + {d68000_asr_s_8 , 0xf1f8, 0xe000, 0x000}, + {d68000_asr_s_16 , 0xf1f8, 0xe040, 0x000}, + {d68000_asr_s_32 , 0xf1f8, 0xe080, 0x000}, + {d68000_asr_r_8 , 0xf1f8, 0xe020, 0x000}, + {d68000_asr_r_16 , 0xf1f8, 0xe060, 0x000}, + {d68000_asr_r_32 , 0xf1f8, 0xe0a0, 0x000}, + {d68000_asr_ea , 0xffc0, 0xe0c0, 0x3f8}, + {d68000_asl_s_8 , 0xf1f8, 0xe100, 0x000}, + {d68000_asl_s_16 , 0xf1f8, 0xe140, 0x000}, + {d68000_asl_s_32 , 0xf1f8, 0xe180, 0x000}, + {d68000_asl_r_8 , 0xf1f8, 0xe120, 0x000}, + {d68000_asl_r_16 , 0xf1f8, 0xe160, 0x000}, + {d68000_asl_r_32 , 0xf1f8, 0xe1a0, 0x000}, + {d68000_asl_ea , 0xffc0, 0xe1c0, 0x3f8}, + {d68000_bcc_8 , 0xf000, 0x6000, 0x000}, + {d68000_bcc_16 , 0xf0ff, 0x6000, 0x000}, + {d68020_bcc_32 , 0xf0ff, 0x60ff, 0x000}, + {d68000_bchg_r , 0xf1c0, 0x0140, 0xbf8}, + {d68000_bchg_s , 0xffc0, 0x0840, 0xbf8, 0xff00, 0x0000}, + {d68000_bclr_r , 0xf1c0, 0x0180, 0xbf8}, + {d68000_bclr_s , 0xffc0, 0x0880, 0xbf8, 0xff00, 0x0000}, + {d68020_bfchg , 0xffc0, 0xeac0, 0xa78, 0xf000, 0x0000}, + {d68020_bfclr , 0xffc0, 0xecc0, 0xa78, 0xf000, 0x0000}, + {d68020_bfexts , 0xffc0, 0xebc0, 0xa7b, 0x8000, 0x0000}, + {d68020_bfextu , 0xffc0, 0xe9c0, 0xa7b, 0x8000, 0x0000}, + {d68020_bfffo , 0xffc0, 0xedc0, 0xa7b, 0x8000, 0x0000}, + {d68020_bfins , 0xffc0, 0xefc0, 0xa78, 0x8000, 0x0000}, + {d68020_bfset , 0xffc0, 0xeec0, 0xa78, 0xf000, 0x0000}, + {d68020_bftst , 0xffc0, 0xe8c0, 0xa7b, 0xf000, 0x0000}, + {d68010_bkpt , 0xfff8, 0x4848, 0x000}, + {d68000_bra_8 , 0xff00, 0x6000, 0x000}, + {d68000_bra_16 , 0xffff, 0x6000, 0x000}, + {d68020_bra_32 , 0xffff, 0x60ff, 0x000}, + {d68000_bset_r , 0xf1c0, 0x01c0, 0xbf8}, + {d68000_bset_s , 0xffc0, 0x08c0, 0xbf8, 0xfe00, 0x0000 }, + {d68000_bsr_8 , 0xff00, 0x6100, 0x000}, + {d68000_bsr_16 , 0xffff, 0x6100, 0x000}, + {d68020_bsr_32 , 0xffff, 0x61ff, 0x000}, + {d68000_btst_r , 0xf1c0, 0x0100, 0xbff}, + {d68000_btst_s , 0xffc0, 0x0800, 0xbfb, 0xff00, 0x0000}, + {d68020_callm , 0xffc0, 0x06c0, 0x27b, 0xff00, 0x0000}, + {d68020_cas_8 , 0xffc0, 0x0ac0, 0x3f8, 0xfe38, 0x0000}, + {d68020_cas_16 , 0xffc0, 0x0cc0, 0x3f8, 0xfe38, 0x0000}, + {d68020_cas_32 , 0xffc0, 0x0ec0, 0x3f8, 0xfe38, 0x0000}, + {d68020_cas2_16 , 0xffff, 0x0cfc, 0x000, 0x0e38, 0x0000/*, 0x0e38, 0x0000 */}, + {d68020_cas2_32 , 0xffff, 0x0efc, 0x000, 0x0e38, 0x0000/*, 0x0e38, 0x0000 */}, + {d68000_chk_16 , 0xf1c0, 0x4180, 0xbff}, + {d68020_chk_32 , 0xf1c0, 0x4100, 0xbff}, + {d68020_chk2_cmp2_8 , 0xffc0, 0x00c0, 0x27b, 0x07ff, 0x0000}, + {d68020_chk2_cmp2_16 , 0xffc0, 0x02c0, 0x27b, 0x07ff, 0x0000}, + {d68020_chk2_cmp2_32 , 0xffc0, 0x04c0, 0x27b, 0x07ff, 0x0000}, + {d68040_cinv , 0xff20, 0xf400, 0x000}, + {d68000_clr_8 , 0xffc0, 0x4200, 0xbf8}, + {d68000_clr_16 , 0xffc0, 0x4240, 0xbf8}, + {d68000_clr_32 , 0xffc0, 0x4280, 0xbf8}, + {d68000_cmp_8 , 0xf1c0, 0xb000, 0xbff}, + {d68000_cmp_16 , 0xf1c0, 0xb040, 0xfff}, + {d68000_cmp_32 , 0xf1c0, 0xb080, 0xfff}, + {d68000_cmpa_16 , 0xf1c0, 0xb0c0, 0xfff}, + {d68000_cmpa_32 , 0xf1c0, 0xb1c0, 0xfff}, + {d68000_cmpi_8 , 0xffc0, 0x0c00, 0xbf8}, + {d68020_cmpi_pcdi_8 , 0xffff, 0x0c3a, 0x000}, + {d68020_cmpi_pcix_8 , 0xffff, 0x0c3b, 0x000}, + {d68000_cmpi_16 , 0xffc0, 0x0c40, 0xbf8}, + {d68020_cmpi_pcdi_16 , 0xffff, 0x0c7a, 0x000}, + {d68020_cmpi_pcix_16 , 0xffff, 0x0c7b, 0x000}, + {d68000_cmpi_32 , 0xffc0, 0x0c80, 0xbf8}, + {d68020_cmpi_pcdi_32 , 0xffff, 0x0cba, 0x000}, + {d68020_cmpi_pcix_32 , 0xffff, 0x0cbb, 0x000}, + {d68000_cmpm_8 , 0xf1f8, 0xb108, 0x000}, + {d68000_cmpm_16 , 0xf1f8, 0xb148, 0x000}, + {d68000_cmpm_32 , 0xf1f8, 0xb188, 0x000}, + {d68020_cpbcc_16 , 0xf1c0, 0xf080, 0x000}, + {d68020_cpbcc_32 , 0xf1c0, 0xf0c0, 0x000}, + {d68020_cpdbcc , 0xf1f8, 0xf048, 0x000}, + {d68020_cpgen , 0xf1c0, 0xf000, 0x000}, + {d68020_cprestore , 0xf1c0, 0xf140, 0x37f}, + {d68020_cpsave , 0xf1c0, 0xf100, 0x2f8}, + {d68020_cpscc , 0xf1c0, 0xf040, 0xbf8}, + {d68020_cptrapcc_0 , 0xf1ff, 0xf07c, 0x000}, + {d68020_cptrapcc_16 , 0xf1ff, 0xf07a, 0x000}, + {d68020_cptrapcc_32 , 0xf1ff, 0xf07b, 0x000}, + {d68040_cpush , 0xff20, 0xf420, 0x000}, + {d68000_dbcc , 0xf0f8, 0x50c8, 0x000}, + {d68000_dbra , 0xfff8, 0x51c8, 0x000}, + {d68000_divs , 0xf1c0, 0x81c0, 0xbff}, + {d68000_divu , 0xf1c0, 0x80c0, 0xbff}, + {d68020_divl , 0xff80, 0x4c00, 0xbff, 0x83f8, 0x0000}, + {d68000_eor_8 , 0xf1c0, 0xb100, 0xbf8}, + {d68000_eor_16 , 0xf1c0, 0xb140, 0xbf8}, + {d68000_eor_32 , 0xf1c0, 0xb180, 0xbf8}, + {d68000_eori_to_ccr , 0xffff, 0x0a3c, 0x000, 0xff00, 0x0000}, + {d68000_eori_to_sr , 0xffff, 0x0a7c, 0x000}, + {d68000_eori_8 , 0xffc0, 0x0a00, 0xbf8}, + {d68000_eori_16 , 0xffc0, 0x0a40, 0xbf8}, + {d68000_eori_32 , 0xffc0, 0x0a80, 0xbf8}, + {d68000_exg_dd , 0xf1f8, 0xc140, 0x000}, + {d68000_exg_aa , 0xf1f8, 0xc148, 0x000}, + {d68000_exg_da , 0xf1f8, 0xc188, 0x000}, + {d68020_extb_32 , 0xfff8, 0x49c0, 0x000}, + {d68000_ext_16 , 0xfff8, 0x4880, 0x000}, + {d68000_ext_32 , 0xfff8, 0x48c0, 0x000}, + {d68000_illegal , 0xffff, 0x4afc, 0x000}, + {d68000_jmp , 0xffc0, 0x4ec0, 0x27b}, + {d68000_jsr , 0xffc0, 0x4e80, 0x27b}, + {d68000_lea , 0xf1c0, 0x41c0, 0x27b}, + {d68000_link_16 , 0xfff8, 0x4e50, 0x000}, + {d68020_link_32 , 0xfff8, 0x4808, 0x000}, + {d68000_lsr_s_8 , 0xf1f8, 0xe008, 0x000}, + {d68000_lsr_s_16 , 0xf1f8, 0xe048, 0x000}, + {d68000_lsr_s_32 , 0xf1f8, 0xe088, 0x000}, + {d68000_lsr_r_8 , 0xf1f8, 0xe028, 0x000}, + {d68000_lsr_r_16 , 0xf1f8, 0xe068, 0x000}, + {d68000_lsr_r_32 , 0xf1f8, 0xe0a8, 0x000}, + {d68000_lsr_ea , 0xffc0, 0xe2c0, 0x3f8}, + {d68000_lsl_s_8 , 0xf1f8, 0xe108, 0x000}, + {d68000_lsl_s_16 , 0xf1f8, 0xe148, 0x000}, + {d68000_lsl_s_32 , 0xf1f8, 0xe188, 0x000}, + {d68000_lsl_r_8 , 0xf1f8, 0xe128, 0x000}, + {d68000_lsl_r_16 , 0xf1f8, 0xe168, 0x000}, + {d68000_lsl_r_32 , 0xf1f8, 0xe1a8, 0x000}, + {d68000_lsl_ea , 0xffc0, 0xe3c0, 0x3f8}, + {d68000_move_8 , 0xf000, 0x1000, 0xbff}, + {d68000_move_16 , 0xf000, 0x3000, 0xfff}, + {d68000_move_32 , 0xf000, 0x2000, 0xfff}, + {d68000_movea_16 , 0xf1c0, 0x3040, 0xfff}, + {d68000_movea_32 , 0xf1c0, 0x2040, 0xfff}, + {d68000_move_to_ccr , 0xffc0, 0x44c0, 0xbff}, + {d68010_move_fr_ccr , 0xffc0, 0x42c0, 0xbf8}, + {d68000_move_to_sr , 0xffc0, 0x46c0, 0xbff}, + {d68000_move_fr_sr , 0xffc0, 0x40c0, 0xbf8}, + {d68000_move_to_usp , 0xfff8, 0x4e60, 0x000}, + {d68000_move_fr_usp , 0xfff8, 0x4e68, 0x000}, + {d68010_movec , 0xfffe, 0x4e7a, 0x000}, + {d68000_movem_pd_16 , 0xfff8, 0x48a0, 0x000}, + {d68000_movem_pd_32 , 0xfff8, 0x48e0, 0x000}, + {d68000_movem_re_16 , 0xffc0, 0x4880, 0x2f8}, + {d68000_movem_re_32 , 0xffc0, 0x48c0, 0x2f8}, + {d68000_movem_er_16 , 0xffc0, 0x4c80, 0x37b}, + {d68000_movem_er_32 , 0xffc0, 0x4cc0, 0x37b}, + {d68000_movep_er_16 , 0xf1f8, 0x0108, 0x000}, + {d68000_movep_er_32 , 0xf1f8, 0x0148, 0x000}, + {d68000_movep_re_16 , 0xf1f8, 0x0188, 0x000}, + {d68000_movep_re_32 , 0xf1f8, 0x01c8, 0x000}, + {d68010_moves_8 , 0xffc0, 0x0e00, 0x3f8, 0x07ff, 0x0000}, + {d68010_moves_16 , 0xffc0, 0x0e40, 0x3f8, 0x07ff, 0x0000}, + {d68010_moves_32 , 0xffc0, 0x0e80, 0x3f8, 0x07ff, 0x0000}, + {d68000_moveq , 0xf100, 0x7000, 0x000}, + {d68040_move16_pi_pi , 0xfff8, 0xf620, 0x000, 0x8fff, 0x8000}, + {d68040_move16_pi_al , 0xfff8, 0xf600, 0x000}, + {d68040_move16_al_pi , 0xfff8, 0xf608, 0x000}, + {d68040_move16_ai_al , 0xfff8, 0xf610, 0x000}, + {d68040_move16_al_ai , 0xfff8, 0xf618, 0x000}, + {d68000_muls , 0xf1c0, 0xc1c0, 0xbff}, + {d68000_mulu , 0xf1c0, 0xc0c0, 0xbff}, + {d68020_mull , 0xffc0, 0x4c00, 0xbff, 0x83f8, 0x0000}, + {d68000_nbcd , 0xffc0, 0x4800, 0xbf8}, + {d68000_neg_8 , 0xffc0, 0x4400, 0xbf8}, + {d68000_neg_16 , 0xffc0, 0x4440, 0xbf8}, + {d68000_neg_32 , 0xffc0, 0x4480, 0xbf8}, + {d68000_negx_8 , 0xffc0, 0x4000, 0xbf8}, + {d68000_negx_16 , 0xffc0, 0x4040, 0xbf8}, + {d68000_negx_32 , 0xffc0, 0x4080, 0xbf8}, + {d68000_nop , 0xffff, 0x4e71, 0x000}, + {d68000_not_8 , 0xffc0, 0x4600, 0xbf8}, + {d68000_not_16 , 0xffc0, 0x4640, 0xbf8}, + {d68000_not_32 , 0xffc0, 0x4680, 0xbf8}, + {d68000_or_er_8 , 0xf1c0, 0x8000, 0xbff}, + {d68000_or_er_16 , 0xf1c0, 0x8040, 0xbff}, + {d68000_or_er_32 , 0xf1c0, 0x8080, 0xbff}, + {d68000_or_re_8 , 0xf1c0, 0x8100, 0x3f8}, + {d68000_or_re_16 , 0xf1c0, 0x8140, 0x3f8}, + {d68000_or_re_32 , 0xf1c0, 0x8180, 0x3f8}, + {d68000_ori_to_ccr , 0xffff, 0x003c, 0x000, 0xff00, 0x0000}, + {d68000_ori_to_sr , 0xffff, 0x007c, 0x000}, + {d68000_ori_8 , 0xffc0, 0x0000, 0xbf8}, + {d68000_ori_16 , 0xffc0, 0x0040, 0xbf8}, + {d68000_ori_32 , 0xffc0, 0x0080, 0xbf8}, + {d68020_pack_rr , 0xf1f8, 0x8140, 0x000}, + {d68020_pack_mm , 0xf1f8, 0x8148, 0x000}, + {d68000_pea , 0xffc0, 0x4840, 0x27b}, + {d68000_reset , 0xffff, 0x4e70, 0x000}, + {d68000_ror_s_8 , 0xf1f8, 0xe018, 0x000}, + {d68000_ror_s_16 , 0xf1f8, 0xe058, 0x000}, + {d68000_ror_s_32 , 0xf1f8, 0xe098, 0x000}, + {d68000_ror_r_8 , 0xf1f8, 0xe038, 0x000}, + {d68000_ror_r_16 , 0xf1f8, 0xe078, 0x000}, + {d68000_ror_r_32 , 0xf1f8, 0xe0b8, 0x000}, + {d68000_ror_ea , 0xffc0, 0xe6c0, 0x3f8}, + {d68000_rol_s_8 , 0xf1f8, 0xe118, 0x000}, + {d68000_rol_s_16 , 0xf1f8, 0xe158, 0x000}, + {d68000_rol_s_32 , 0xf1f8, 0xe198, 0x000}, + {d68000_rol_r_8 , 0xf1f8, 0xe138, 0x000}, + {d68000_rol_r_16 , 0xf1f8, 0xe178, 0x000}, + {d68000_rol_r_32 , 0xf1f8, 0xe1b8, 0x000}, + {d68000_rol_ea , 0xffc0, 0xe7c0, 0x3f8}, + {d68000_roxr_s_8 , 0xf1f8, 0xe010, 0x000}, + {d68000_roxr_s_16 , 0xf1f8, 0xe050, 0x000}, + {d68000_roxr_s_32 , 0xf1f8, 0xe090, 0x000}, + {d68000_roxr_r_8 , 0xf1f8, 0xe030, 0x000}, + {d68000_roxr_r_16 , 0xf1f8, 0xe070, 0x000}, + {d68000_roxr_r_32 , 0xf1f8, 0xe0b0, 0x000}, + {d68000_roxr_ea , 0xffc0, 0xe4c0, 0x3f8}, + {d68000_roxl_s_8 , 0xf1f8, 0xe110, 0x000}, + {d68000_roxl_s_16 , 0xf1f8, 0xe150, 0x000}, + {d68000_roxl_s_32 , 0xf1f8, 0xe190, 0x000}, + {d68000_roxl_r_8 , 0xf1f8, 0xe130, 0x000}, + {d68000_roxl_r_16 , 0xf1f8, 0xe170, 0x000}, + {d68000_roxl_r_32 , 0xf1f8, 0xe1b0, 0x000}, + {d68000_roxl_ea , 0xffc0, 0xe5c0, 0x3f8}, + {d68010_rtd , 0xffff, 0x4e74, 0x000}, + {d68000_rte , 0xffff, 0x4e73, 0x000}, + {d68020_rtm , 0xfff0, 0x06c0, 0x000}, + {d68000_rtr , 0xffff, 0x4e77, 0x000}, + {d68000_rts , 0xffff, 0x4e75, 0x000}, + {d68000_sbcd_rr , 0xf1f8, 0x8100, 0x000}, + {d68000_sbcd_mm , 0xf1f8, 0x8108, 0x000}, + {d68000_scc , 0xf0c0, 0x50c0, 0xbf8}, + {d68000_stop , 0xffff, 0x4e72, 0x000}, + {d68000_sub_er_8 , 0xf1c0, 0x9000, 0xbff}, + {d68000_sub_er_16 , 0xf1c0, 0x9040, 0xfff}, + {d68000_sub_er_32 , 0xf1c0, 0x9080, 0xfff}, + {d68000_sub_re_8 , 0xf1c0, 0x9100, 0x3f8}, + {d68000_sub_re_16 , 0xf1c0, 0x9140, 0x3f8}, + {d68000_sub_re_32 , 0xf1c0, 0x9180, 0x3f8}, + {d68000_suba_16 , 0xf1c0, 0x90c0, 0xfff}, + {d68000_suba_32 , 0xf1c0, 0x91c0, 0xfff}, + {d68000_subi_8 , 0xffc0, 0x0400, 0xbf8}, + {d68000_subi_16 , 0xffc0, 0x0440, 0xbf8}, + {d68000_subi_32 , 0xffc0, 0x0480, 0xbf8}, + {d68000_subq_8 , 0xf1c0, 0x5100, 0xbf8}, + {d68000_subq_16 , 0xf1c0, 0x5140, 0xff8}, + {d68000_subq_32 , 0xf1c0, 0x5180, 0xff8}, + {d68000_subx_rr_8 , 0xf1f8, 0x9100, 0x000}, + {d68000_subx_rr_16 , 0xf1f8, 0x9140, 0x000}, + {d68000_subx_rr_32 , 0xf1f8, 0x9180, 0x000}, + {d68000_subx_mm_8 , 0xf1f8, 0x9108, 0x000}, + {d68000_subx_mm_16 , 0xf1f8, 0x9148, 0x000}, + {d68000_subx_mm_32 , 0xf1f8, 0x9188, 0x000}, + {d68000_swap , 0xfff8, 0x4840, 0x000}, + {d68000_tas , 0xffc0, 0x4ac0, 0xbf8}, + {d68000_trap , 0xfff0, 0x4e40, 0x000}, + {d68020_trapcc_0 , 0xf0ff, 0x50fc, 0x000}, + {d68020_trapcc_16 , 0xf0ff, 0x50fa, 0x000}, + {d68020_trapcc_32 , 0xf0ff, 0x50fb, 0x000}, + {d68000_trapv , 0xffff, 0x4e76, 0x000}, + {d68000_tst_8 , 0xffc0, 0x4a00, 0xbf8}, + {d68020_tst_pcdi_8 , 0xffff, 0x4a3a, 0x000}, + {d68020_tst_pcix_8 , 0xffff, 0x4a3b, 0x000}, + {d68020_tst_i_8 , 0xffff, 0x4a3c, 0x000}, + {d68000_tst_16 , 0xffc0, 0x4a40, 0xbf8}, + {d68020_tst_a_16 , 0xfff8, 0x4a48, 0x000}, + {d68020_tst_pcdi_16 , 0xffff, 0x4a7a, 0x000}, + {d68020_tst_pcix_16 , 0xffff, 0x4a7b, 0x000}, + {d68020_tst_i_16 , 0xffff, 0x4a7c, 0x000}, + {d68000_tst_32 , 0xffc0, 0x4a80, 0xbf8}, + {d68020_tst_a_32 , 0xfff8, 0x4a88, 0x000}, + {d68020_tst_pcdi_32 , 0xffff, 0x4aba, 0x000}, + {d68020_tst_pcix_32 , 0xffff, 0x4abb, 0x000}, + {d68020_tst_i_32 , 0xffff, 0x4abc, 0x000}, + {d68000_unlk , 0xfff8, 0x4e58, 0x000}, + {d68020_unpk_rr , 0xf1f8, 0x8180, 0x000}, + {d68020_unpk_mm , 0xf1f8, 0x8188, 0x000}, + {0, 0, 0, 0} +}; + +/* Check if opcode is using a valid ea mode */ +static int valid_ea(uint opcode, uint mask) +{ + if (mask == 0) + return 1; + + switch(opcode & 0x3f) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x05: case 0x06: case 0x07: + return (mask & 0x800) != 0; + case 0x08: case 0x09: case 0x0a: case 0x0b: + case 0x0c: case 0x0d: case 0x0e: case 0x0f: + return (mask & 0x400) != 0; + case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x15: case 0x16: case 0x17: + return (mask & 0x200) != 0; + case 0x18: case 0x19: case 0x1a: case 0x1b: + case 0x1c: case 0x1d: case 0x1e: case 0x1f: + return (mask & 0x100) != 0; + case 0x20: case 0x21: case 0x22: case 0x23: + case 0x24: case 0x25: case 0x26: case 0x27: + return (mask & 0x080) != 0; + case 0x28: case 0x29: case 0x2a: case 0x2b: + case 0x2c: case 0x2d: case 0x2e: case 0x2f: + return (mask & 0x040) != 0; + case 0x30: case 0x31: case 0x32: case 0x33: + case 0x34: case 0x35: case 0x36: case 0x37: + return (mask & 0x020) != 0; + case 0x38: + return (mask & 0x010) != 0; + case 0x39: + return (mask & 0x008) != 0; + case 0x3a: + return (mask & 0x002) != 0; + case 0x3b: + return (mask & 0x001) != 0; + case 0x3c: + return (mask & 0x004) != 0; + } + return 0; + +} + +/* Used by qsort */ +static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr) +{ + uint a = ((const opcode_struct*)aptr)->mask; + uint b = ((const opcode_struct*)bptr)->mask; + + a = ((a & 0xAAAA) >> 1) + (a & 0x5555); + a = ((a & 0xCCCC) >> 2) + (a & 0x3333); + a = ((a & 0xF0F0) >> 4) + (a & 0x0F0F); + a = ((a & 0xFF00) >> 8) + (a & 0x00FF); + + b = ((b & 0xAAAA) >> 1) + (b & 0x5555); + b = ((b & 0xCCCC) >> 2) + (b & 0x3333); + b = ((b & 0xF0F0) >> 4) + (b & 0x0F0F); + b = ((b & 0xFF00) >> 8) + (b & 0x00FF); + + return b - a; /* reversed to get greatest to least sorting */ +} + +/* build the opcode handler jump table */ +static void build_opcode_table(void) +{ + uint i; + uint opcode; + opcode_struct* ostruct; + uint opcode_info_length = 0; + + /* Already initialized ? */ + if (g_instruction_table[0].instruction != NULL) { + return; + } + + for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++) + opcode_info_length++; + + qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits); + + for(i=0;i<0x10000;i++) { + g_instruction_table[i].instruction = d68000_invalid; /* default to invalid, undecoded opcode */ + opcode = i; + /* search through opcode info for a match */ + for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++) { + /* match opcode mask and allowed ea modes */ + if ((opcode & ostruct->mask) == ostruct->match) { + /* Handle destination ea for move instructions */ + if ((ostruct->opcode_handler == d68000_move_8 || + ostruct->opcode_handler == d68000_move_16 || + ostruct->opcode_handler == d68000_move_32) && + !valid_ea(((opcode>>9)&7) | ((opcode>>3)&0x38), 0xbf8)) + continue; + if (valid_ea(opcode, ostruct->ea_mask)) { + g_instruction_table[i].instruction = ostruct->opcode_handler; + g_instruction_table[i].word2_mask = ostruct->mask2; + g_instruction_table[i].word2_match = ostruct->match2; + break; + } + } + } + } +} + +static int instruction_is_valid(m68k_info *info, const unsigned int word_check) +{ + const unsigned int instruction = info->ir; + instruction_struct *i = &g_instruction_table[instruction]; + + if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) || + (i->instruction == d68000_invalid) ) { + d68000_invalid(info); + return 0; + } + + return 1; +} + +static int exists_reg_list(uint16_t *regs, uint8_t count, m68k_reg reg) +{ + uint8_t i; + + for (i = 0; i < count; ++i) { + if (regs[i] == (uint16_t)reg) + return 1; + } + + return 0; +} + +static void add_reg_to_rw_list(m68k_info *info, m68k_reg reg, int write) +{ + if (reg == M68K_REG_INVALID) + return; + + if (write) + { + if (exists_reg_list(info->regs_write, info->regs_write_count, reg)) + return; + + info->regs_write[info->regs_write_count] = (uint16_t)reg; + info->regs_write_count++; + } + else + { + if (exists_reg_list(info->regs_read, info->regs_read_count, reg)) + return; + + info->regs_read[info->regs_read_count] = (uint16_t)reg; + info->regs_read_count++; + } +} + +static void update_am_reg_list(m68k_info *info, cs_m68k_op *op, int write) +{ + switch (op->address_mode) { + case M68K_AM_REG_DIRECT_ADDR: + case M68K_AM_REG_DIRECT_DATA: + add_reg_to_rw_list(info, op->reg, write); + break; + + case M68K_AM_REGI_ADDR_POST_INC: + case M68K_AM_REGI_ADDR_PRE_DEC: + add_reg_to_rw_list(info, op->reg, 1); + break; + + case M68K_AM_REGI_ADDR: + case M68K_AM_REGI_ADDR_DISP: + add_reg_to_rw_list(info, op->reg, 0); + break; + + case M68K_AM_AREGI_INDEX_8_BIT_DISP: + case M68K_AM_AREGI_INDEX_BASE_DISP: + case M68K_AM_MEMI_POST_INDEX: + case M68K_AM_MEMI_PRE_INDEX: + case M68K_AM_PCI_INDEX_8_BIT_DISP: + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_PC_MEMI_POST_INDEX: + add_reg_to_rw_list(info, op->mem.index_reg, 0); + add_reg_to_rw_list(info, op->mem.base_reg, 0); + break; + + // no register(s) in the other addressing modes + default: + break; + } +} + +static void update_bits_range(m68k_info *info, m68k_reg reg_start, uint8_t bits, int write) +{ + int i; + + for (i = 0; i < 8; ++i) { + if (bits & (1 << i)) { + add_reg_to_rw_list(info, reg_start + i, write); + } + } +} + +static void update_reg_list_regbits(m68k_info *info, cs_m68k_op *op, int write) +{ + uint32_t bits = op->register_bits; + update_bits_range(info, M68K_REG_D0, bits & 0xff, write); + update_bits_range(info, M68K_REG_A0, (bits >> 8) & 0xff, write); + update_bits_range(info, M68K_REG_FP0, (bits >> 16) & 0xff, write); +} + +static void update_op_reg_list(m68k_info *info, cs_m68k_op *op, int write) +{ + switch ((int)op->type) { + case M68K_OP_REG: + add_reg_to_rw_list(info, op->reg, write); + break; + + case M68K_OP_MEM: + update_am_reg_list(info, op, write); + break; + + case M68K_OP_REG_BITS: + update_reg_list_regbits(info, op, write); + break; + + case M68K_OP_REG_PAIR: + add_reg_to_rw_list(info, M68K_REG_D0 + op->reg_pair.reg_0, write); + add_reg_to_rw_list(info, M68K_REG_D0 + op->reg_pair.reg_1, write); + break; + } +} + +static void build_regs_read_write_counts(m68k_info *info) +{ + int i; + + if (!info->extension.op_count) + return; + + if (info->extension.op_count == 1) { + update_op_reg_list(info, &info->extension.operands[0], 1); + } else { + // first operand is always read + update_op_reg_list(info, &info->extension.operands[0], 0); + + // remaning write + for (i = 1; i < info->extension.op_count; ++i) + update_op_reg_list(info, &info->extension.operands[i], 1); + } +} + +static void m68k_setup_internals(m68k_info* info, MCInst* inst, unsigned int pc, unsigned int cpu_type) +{ + info->inst = inst; + info->pc = pc; + info->ir = 0; + info->type = cpu_type; + info->address_mask = 0xffffffff; + + switch(info->type) { + case M68K_CPU_TYPE_68000: + info->type = TYPE_68000; + info->address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68010: + info->type = TYPE_68010; + info->address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68EC020: + info->type = TYPE_68020; + info->address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68020: + info->type = TYPE_68020; + info->address_mask = 0xffffffff; + break; + case M68K_CPU_TYPE_68030: + info->type = TYPE_68030; + info->address_mask = 0xffffffff; + break; + case M68K_CPU_TYPE_68040: + info->type = TYPE_68040; + info->address_mask = 0xffffffff; + break; + default: + info->address_mask = 0; + return; + } +} + +/* ======================================================================== */ +/* ================================= API ================================== */ +/* ======================================================================== */ + +/* Disasemble one instruction at pc and store in str_buff */ +static unsigned int m68k_disassemble(m68k_info *info, uint64_t pc) +{ + MCInst *inst = info->inst; + cs_m68k* ext = &info->extension; + int i; + unsigned int size; + + inst->Opcode = M68K_INS_INVALID; + + build_opcode_table(); + + memset(ext, 0, sizeof(cs_m68k)); + ext->op_size.type = M68K_SIZE_TYPE_CPU; + + for (i = 0; i < M68K_OPERAND_COUNT; ++i) + ext->operands[i].type = M68K_OP_REG; + + info->ir = peek_imm_16(info); + if (instruction_is_valid(info, peek_imm_32(info) & 0xffff)) { + info->ir = read_imm_16(info); + g_instruction_table[info->ir].instruction(info); + } + + size = info->pc - (unsigned int)pc; + info->pc = (unsigned int)pc; + + return size; +} + +bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* inst_info) +{ +#ifdef M68K_DEBUG + SStream ss; +#endif + int s; + int cpu_type = M68K_CPU_TYPE_68000; + cs_struct* handle = instr->csh; + m68k_info *info = (m68k_info*)handle->printer_info; + + // code len has to be at least 2 bytes to be valid m68k + + if (code_len < 2) { + *size = 0; + return false; + } + + if (instr->flat_insn->detail) { + memset(instr->flat_insn->detail, 0, offsetof(cs_detail, m68k)+sizeof(cs_m68k)); + } + + info->groups_count = 0; + info->regs_read_count = 0; + info->regs_write_count = 0; + info->code = code; + info->code_len = code_len; + info->baseAddress = address; + + if (handle->mode & CS_MODE_M68K_010) + cpu_type = M68K_CPU_TYPE_68010; + if (handle->mode & CS_MODE_M68K_020) + cpu_type = M68K_CPU_TYPE_68020; + if (handle->mode & CS_MODE_M68K_030) + cpu_type = M68K_CPU_TYPE_68030; + if (handle->mode & CS_MODE_M68K_040) + cpu_type = M68K_CPU_TYPE_68040; + if (handle->mode & CS_MODE_M68K_060) + cpu_type = M68K_CPU_TYPE_68040; // 060 = 040 for now + + m68k_setup_internals(info, instr, (unsigned int)address, cpu_type); + s = m68k_disassemble(info, address); + + if (s == 0) { + *size = 2; + return false; + } + + build_regs_read_write_counts(info); + +#ifdef M68K_DEBUG + SStream_Init(&ss); + M68K_printInst(instr, &ss, info); +#endif + + // Make sure we always stay within range + if (s > (int)code_len) + *size = (uint16_t)code_len; + else + *size = (uint16_t)s; + + return true; +} + diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.h b/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.h new file mode 100644 index 0000000..229545b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KDisassembler.h @@ -0,0 +1,30 @@ +/* Capstone Disassembly Engine */ +/* M68K Backend by Daniel Collin 2015-2016 */ + +#ifndef CS_M68KDISASSEMBLER_H +#define CS_M68KDISASSEMBLER_H + +#include "../../MCInst.h" + +/* Private, For internal use only */ +typedef struct m68k_info { + const uint8_t *code; + size_t code_len; + uint64_t baseAddress; + MCInst *inst; + unsigned int pc; /* program counter */ + unsigned int ir; /* instruction register */ + unsigned int type; + unsigned int address_mask; /* Address mask to simulate address lines */ + cs_m68k extension; + uint16_t regs_read[20]; // list of implicit registers read by this insn + uint8_t regs_read_count; // number of implicit registers read by this insn + uint16_t regs_write[20]; // list of implicit registers modified by this insn + uint8_t regs_write_count; // number of implicit registers modified by this insn + uint8_t groups[8]; + uint8_t groups_count; +} m68k_info; + +bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.c b/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.c new file mode 100644 index 0000000..4efcdea --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.c @@ -0,0 +1,387 @@ +/* Capstone Disassembly Engine */ +/* M68K Backend by Daniel Collin 2015-2016 */ + +#ifdef _MSC_VER +// Disable security warnings for strcat & sprintf +#ifndef _CRT_SECURE_NO_WARNINGS +#define _CRT_SECURE_NO_WARNINGS +#endif + +//Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for +//security purposes. +#pragma warning(disable:28719) +#endif + +#include // DEBUG +#include +#include + +#include "M68KInstPrinter.h" + +#include "M68KDisassembler.h" + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCRegisterInfo.h" + +#ifndef CAPSTONE_DIET +static const char* s_spacing = " "; + +static const char* s_reg_names[] = { + "invalid", + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", + "pc", + "sr", "ccr", "sfc", "dfc", "usp", "vbr", "cacr", + "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0", + "dtt1", "mmusr", "urp", "srp", + + "fpcr", "fpsr", "fpiar", +}; + +static const char* s_instruction_names[] = { + "invalid", + "abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", + "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins", + "bfset", "bftst", "bkpt", "callm", "cas", "cas2", "chk", "chk2", "clr", "cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl", "cinvp", "cinva", "cpushl", "cpushp", + "cpusha", "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra", + "divs", "divsl", "divu", "divul", "eor", "eori", "exg", "ext", "extb", "fabs", "fsabs", "fdabs", "facos", "fadd", "fsadd", "fdadd", "fasin", + "fatan", "fatanh", "fbf", "fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl", "fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult", "fbule", "fbne", "fbt", + "fbsf", "fbseq", "fbgt", "fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle", "fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne", "fbst", "fcmp", "fcos", + "fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne", + "fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne", + "fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove", + "fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv", + "fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq", + "fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle", + "fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt", + "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt", + "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge", + "ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec", + "movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha", + "pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror", + "roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi", + "sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls", + "trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk", +}; +#endif + + +#ifndef CAPSTONE_DIET +static const char* getRegName(m68k_reg reg) +{ + return s_reg_names[(int)reg]; +} + +static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix) +{ + unsigned int first = 0; + unsigned int run_length = 0; + int i; + + for (i = 0; i < 8; ++i) { + if (data & (1 << i)) { + first = i; + run_length = 0; + + while (i < 7 && (data & (1 << (i + 1)))) { + i++; + run_length++; + } + + if (buffer[0] != 0) + strcat(buffer, "/"); + + sprintf(buffer + strlen(buffer), "%s%d", prefix, first); + if (run_length > 0) + sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length); + } + } +} + +static void registerBits(SStream* O, const cs_m68k_op* op) +{ + char buffer[128]; + unsigned int data = op->register_bits; + + buffer[0] = 0; + + if (!data) { + SStream_concat(O, "%s", "#$0"); + return; + } + + printRegbitsRange(buffer, data & 0xff, "d"); + printRegbitsRange(buffer, (data >> 8) & 0xff, "a"); + printRegbitsRange(buffer, (data >> 16) & 0xff, "fp"); + + SStream_concat(O, "%s", buffer); +} + +static void registerPair(SStream* O, const cs_m68k_op* op) +{ + SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + op->reg_pair.reg_0], + s_reg_names[M68K_REG_D0 + op->reg_pair.reg_1]); +} + +static void printAddressingMode(SStream* O, unsigned int pc, const cs_m68k* inst, const cs_m68k_op* op) +{ + switch (op->address_mode) { + case M68K_AM_NONE: + switch (op->type) { + case M68K_OP_REG_BITS: + registerBits(O, op); + break; + case M68K_OP_REG_PAIR: + registerPair(O, op); + break; + case M68K_OP_REG: + SStream_concat(O, "%s", s_reg_names[op->reg]); + break; + default: + break; + } + break; + + case M68K_AM_REG_DIRECT_DATA: SStream_concat(O, "d%d", (op->reg - M68K_REG_D0)); break; + case M68K_AM_REG_DIRECT_ADDR: SStream_concat(O, "a%d", (op->reg - M68K_REG_A0)); break; + case M68K_AM_REGI_ADDR: SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0)); break; + case M68K_AM_REGI_ADDR_POST_INC: SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0)); break; + case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break; + case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break; + case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp); break; + case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break; + case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break; + case M68K_AM_IMMEDIATE: + if (inst->op_size.type == M68K_SIZE_TYPE_FPU) { +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + SStream_concat(O, "#"); + break; +#else + if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE) + SStream_concat(O, "#%f", op->simm); + else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE) + SStream_concat(O, "#%f", op->dimm); + else + SStream_concat(O, "#"); + break; +#endif + } + SStream_concat(O, "#$%x", op->imm); + break; + case M68K_AM_PCI_INDEX_8_BIT_DISP: + SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); + break; + case M68K_AM_AREGI_INDEX_8_BIT_DISP: + SStream_concat(O, "%s$%x(%s,%s%s.%c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); + break; + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_AREGI_INDEX_BASE_DISP: + + if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { + SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); + } else { + if (op->mem.in_disp > 0) + SStream_concat(O, "$%x", op->mem.in_disp); + } + + SStream_concat(O, "("); + + if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { + SStream_concat(O, "pc,%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); + } else { + if (op->mem.base_reg != M68K_REG_INVALID) + SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing); + SStream_concat(O, "%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); + } + + if (op->mem.scale > 0) + SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing, op->mem.scale); + else + SStream_concat(O, ")"); + break; + // It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code + // easier and that is what actually happens when the code is executed anyway. + + case M68K_AM_PC_MEMI_POST_INDEX: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_MEMI_PRE_INDEX: + case M68K_AM_MEMI_POST_INDEX: + SStream_concat(O, "(["); + + if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) { + SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); + } else { + if (op->mem.in_disp > 0) + SStream_concat(O, "$%x", op->mem.in_disp); + } + + if (op->mem.base_reg != M68K_REG_INVALID) { + if (op->mem.in_disp > 0) + SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg)); + else + SStream_concat(O, "%s", getRegName(op->mem.base_reg)); + } + + if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX) + SStream_concat(O, "]"); + + if (op->mem.index_reg != M68K_REG_INVALID) + SStream_concat(O, ",%s%s.%c", s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); + + if (op->mem.scale > 0) + SStream_concat(O, "%s*%s%d", s_spacing, s_spacing, op->mem.scale); + + if (op->address_mode == M68K_AM_MEMI_PRE_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) + SStream_concat(O, "]"); + + if (op->mem.out_disp > 0) + SStream_concat(O, ",%s$%x", s_spacing, op->mem.out_disp); + + SStream_concat(O, ")"); + break; + case M68K_AM_BRANCH_DISPLACEMENT: + SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp); + default: + break; + } + + if (op->mem.bitfield) + SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width); +} +#endif + +#define m68k_sizeof_array(array) (int)(sizeof(array)/sizeof(array[0])) +#define m68k_min(a, b) (a < b) ? a : b + +void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo) +{ +#ifndef CAPSTONE_DIET + m68k_info *info = (m68k_info *)PrinterInfo; + cs_m68k *ext = &info->extension; + cs_detail *detail = NULL; + int i = 0; + + detail = MI->flat_insn->detail; + if (detail) { + int regs_read_count = m68k_min(m68k_sizeof_array(detail->regs_read), info->regs_read_count); + int regs_write_count = m68k_min(m68k_sizeof_array(detail->regs_write), info->regs_write_count); + int groups_count = m68k_min(m68k_sizeof_array(detail->groups), info->groups_count); + + memcpy(&detail->m68k, ext, sizeof(cs_m68k)); + + memcpy(&detail->regs_read, &info->regs_read, regs_read_count * sizeof(uint16_t)); + detail->regs_read_count = regs_read_count; + + memcpy(&detail->regs_write, &info->regs_write, regs_write_count * sizeof(uint16_t)); + detail->regs_write_count = regs_write_count; + + memcpy(&detail->groups, &info->groups, groups_count); + detail->groups_count = groups_count; + } + + if (MI->Opcode == M68K_INS_INVALID) { + if (ext->op_count) + SStream_concat(O, "dc.w $%x", ext->operands[0].imm); + else + SStream_concat(O, "dc.w $"); + return; + } + + SStream_concat0(O, (char*)s_instruction_names[MI->Opcode]); + + switch (ext->op_size.type) { + case M68K_SIZE_TYPE_INVALID : + break; + + case M68K_SIZE_TYPE_CPU : + switch (ext->op_size.cpu_size) { + case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break; + case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break; + case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break; + case M68K_CPU_SIZE_NONE: break; + } + break; + + case M68K_SIZE_TYPE_FPU : + switch (ext->op_size.fpu_size) { + case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break; + case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break; + case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break; + case M68K_FPU_SIZE_NONE: break; + } + break; + } + + SStream_concat0(O, " "); + + // this one is a bit spacial so we do special things + + if (MI->Opcode == M68K_INS_CAS2) { + int reg_value_0, reg_value_1; + printAddressingMode(O, info->pc, ext, &ext->operands[0]); SStream_concat0(O, ","); + printAddressingMode(O, info->pc, ext, &ext->operands[1]); SStream_concat0(O, ","); + reg_value_0 = ext->operands[2].register_bits >> 4; + reg_value_1 = ext->operands[2].register_bits & 0xf; + SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]); + return; + } + + for (i = 0; i < ext->op_count; ++i) { + printAddressingMode(O, info->pc, ext, &ext->operands[i]); + if ((i + 1) != ext->op_count) + SStream_concat(O, ",%s", s_spacing); + } +#endif +} + +const char* M68K_reg_name(csh handle, unsigned int reg) +{ +#ifdef CAPSTONE_DIET + return NULL; +#else + if (reg >= ARR_SIZE(s_reg_names)) { + return NULL; + } + return s_reg_names[(int)reg]; +#endif +} + +void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id) +{ + insn->id = id; // These id's matches for 68k +} + +const char* M68K_insn_name(csh handle, unsigned int id) +{ +#ifdef CAPSTONE_DIET + return NULL; +#else + return s_instruction_names[id]; +#endif +} + +#ifndef CAPSTONE_DIET +static name_map group_name_maps[] = { + { M68K_GRP_INVALID , NULL }, + { M68K_GRP_JUMP, "jump" }, + { M68K_GRP_RET , "ret" }, + { M68K_GRP_IRET, "iret" }, + { M68K_GRP_BRANCH_RELATIVE, "branch_relative" }, +}; +#endif + +const char *M68K_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.h b/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.h new file mode 100644 index 0000000..45841ed --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KInstPrinter.h @@ -0,0 +1,21 @@ +/* Capstone Disassembly Engine */ +/* M68K Backend by Daniel Collin 2015 */ + +#ifndef CS_M68KINSTPRINTER_H +#define CS_M68KINSTPRINTER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +struct SStream; + +void M68K_init(MCRegisterInfo *MRI); +void M68K_printInst(MCInst* MI, struct SStream* O, void* Info); +const char* M68K_reg_name(csh handle, unsigned int reg); +void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); +const char *M68K_insn_name(csh handle, unsigned int id); +const char* M68K_group_name(csh handle, unsigned int id); +void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci); + +#endif diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KModule.c b/white_patch_detect/capstone-master/arch/M68K/M68KModule.c new file mode 100644 index 0000000..03e73f7 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KModule.c @@ -0,0 +1,42 @@ +/* Capstone Disassembly Engine */ +/* M68K Backend by Daniel Collin 2015 */ + +#ifdef CAPSTONE_HAS_M68K + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "M68KDisassembler.h" +#include "M68KInstPrinter.h" +#include "M68KModule.h" + +cs_err M68K_global_init(cs_struct *ud) +{ + m68k_info *info; + + info = cs_mem_malloc(sizeof(m68k_info)); + if (!info) { + return CS_ERR_MEM; + } + + ud->printer = M68K_printInst; + ud->printer_info = info; + ud->getinsn_info = NULL; + ud->disasm = M68K_getInstruction; + ud->skipdata_size = 2; + ud->post_printer = NULL; + + ud->reg_name = M68K_reg_name; + ud->insn_id = M68K_get_insn_id; + ud->insn_name = M68K_insn_name; + ud->group_name = M68K_group_name; + + return CS_ERR_OK; +} + +cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + return CS_ERR_OK; +} + +#endif + diff --git a/white_patch_detect/capstone-master/arch/M68K/M68KModule.h b/white_patch_detect/capstone-master/arch/M68K/M68KModule.h new file mode 100644 index 0000000..65b20bd --- /dev/null +++ b/white_patch_detect/capstone-master/arch/M68K/M68KModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_M68K_MODULE_H +#define CS_M68K_MODULE_H + +#include "../../utils.h" + +cs_err M68K_global_init(cs_struct *ud); +cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.c b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.c new file mode 100644 index 0000000..523f41e --- /dev/null +++ b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.c @@ -0,0 +1,596 @@ +/* Capstone Disassembly Engine */ +/* MOS65XX Backend by Sebastian Macke 2018 */ + +#include "capstone/mos65xx.h" +#include "MOS65XXDisassembler.h" + +typedef struct OpInfo { + mos65xx_insn ins; + mos65xx_address_mode am; +} OpInfo; + +static const struct OpInfo OpInfoTable[]= { + { MOS65XX_INS_BRK , MOS65XX_AM_IMP }, // 0x00 + { MOS65XX_INS_ORA , MOS65XX_AM_INDX }, // 0x01 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x02 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x03 + { MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x04 + { MOS65XX_INS_ORA , MOS65XX_AM_ZP }, // 0x05 + { MOS65XX_INS_ASL , MOS65XX_AM_ZP }, // 0x06 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x07 + { MOS65XX_INS_PHP , MOS65XX_AM_IMP }, // 0x08 + { MOS65XX_INS_ORA , MOS65XX_AM_IMM }, // 0x09 + { MOS65XX_INS_ASL , MOS65XX_AM_ACC }, // 0x0a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x0b + { MOS65XX_INS_NOP , MOS65XX_AM_ABS }, // 0x0c + { MOS65XX_INS_ORA , MOS65XX_AM_ABS }, // 0x0d + { MOS65XX_INS_ASL , MOS65XX_AM_ABS }, // 0x0e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x0f + { MOS65XX_INS_BPL , MOS65XX_AM_REL }, // 0x10 + { MOS65XX_INS_ORA , MOS65XX_AM_INDY }, // 0x11 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x12 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x13 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x14 + { MOS65XX_INS_ORA , MOS65XX_AM_ZPX }, // 0x15 + { MOS65XX_INS_ASL , MOS65XX_AM_ZPX }, // 0x16 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x17 + { MOS65XX_INS_CLC , MOS65XX_AM_IMP }, // 0x18 + { MOS65XX_INS_ORA , MOS65XX_AM_ABSY }, // 0x19 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x1a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x1b + { MOS65XX_INS_NOP , MOS65XX_AM_ABS }, // 0x1c + { MOS65XX_INS_ORA , MOS65XX_AM_ABSX }, // 0x1d + { MOS65XX_INS_ASL , MOS65XX_AM_ABSX }, // 0x1e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x1f + { MOS65XX_INS_JSR , MOS65XX_AM_ABS }, // 0x20 + { MOS65XX_INS_AND , MOS65XX_AM_INDX }, // 0x21 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x22 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x23 + { MOS65XX_INS_BIT , MOS65XX_AM_ZP }, // 0x24 + { MOS65XX_INS_AND , MOS65XX_AM_ZP }, // 0x25 + { MOS65XX_INS_ROL , MOS65XX_AM_ZP }, // 0x26 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x27 + { MOS65XX_INS_PLP , MOS65XX_AM_IMP }, // 0x28 + { MOS65XX_INS_AND , MOS65XX_AM_IMM }, // 0x29 + { MOS65XX_INS_ROL , MOS65XX_AM_ACC }, // 0x2a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x2b + { MOS65XX_INS_BIT , MOS65XX_AM_ABS }, // 0x2c + { MOS65XX_INS_AND , MOS65XX_AM_ABS }, // 0x2d + { MOS65XX_INS_ROL , MOS65XX_AM_ABS }, // 0x2e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x2f + { MOS65XX_INS_BMI , MOS65XX_AM_REL }, // 0x30 + { MOS65XX_INS_AND , MOS65XX_AM_INDY }, // 0x31 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x32 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x33 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x34 + { MOS65XX_INS_AND , MOS65XX_AM_ZPX }, // 0x35 + { MOS65XX_INS_ROL , MOS65XX_AM_ZPX }, // 0x36 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x37 + { MOS65XX_INS_SEC , MOS65XX_AM_IMP }, // 0x38 + { MOS65XX_INS_AND , MOS65XX_AM_ABSY }, // 0x39 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x3a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x3b + { MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x3c + { MOS65XX_INS_AND , MOS65XX_AM_ABSX }, // 0x3d + { MOS65XX_INS_ROL , MOS65XX_AM_ABSX }, // 0x3e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x3f + { MOS65XX_INS_RTI , MOS65XX_AM_IMP }, // 0x40 + { MOS65XX_INS_EOR , MOS65XX_AM_INDX }, // 0x41 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x42 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x43 + { MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x44 + { MOS65XX_INS_EOR , MOS65XX_AM_ZP }, // 0x45 + { MOS65XX_INS_LSR , MOS65XX_AM_ZP }, // 0x46 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x47 + { MOS65XX_INS_PHA , MOS65XX_AM_IMP }, // 0x48 + { MOS65XX_INS_EOR , MOS65XX_AM_IMM }, // 0x49 + { MOS65XX_INS_LSR , MOS65XX_AM_ACC }, // 0x4a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x4b + { MOS65XX_INS_JMP , MOS65XX_AM_ABS }, // 0x4c + { MOS65XX_INS_EOR , MOS65XX_AM_ABS }, // 0x4d + { MOS65XX_INS_LSR , MOS65XX_AM_ABS }, // 0x4e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x4f + { MOS65XX_INS_BVC , MOS65XX_AM_REL }, // 0x50 + { MOS65XX_INS_EOR , MOS65XX_AM_INDY }, // 0x51 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x52 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x53 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x54 + { MOS65XX_INS_EOR , MOS65XX_AM_ZPX }, // 0x55 + { MOS65XX_INS_LSR , MOS65XX_AM_ZPX }, // 0x56 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x57 + { MOS65XX_INS_CLI , MOS65XX_AM_IMP }, // 0x58 + { MOS65XX_INS_EOR , MOS65XX_AM_ABSY }, // 0x59 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x5a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x5b + { MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x5c + { MOS65XX_INS_EOR , MOS65XX_AM_ABSX }, // 0x5d + { MOS65XX_INS_LSR , MOS65XX_AM_ABSX }, // 0x5e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x5f + { MOS65XX_INS_RTS , MOS65XX_AM_IMP }, // 0x60 + { MOS65XX_INS_ADC , MOS65XX_AM_INDX }, // 0x61 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x62 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x63 + { MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x64 + { MOS65XX_INS_ADC , MOS65XX_AM_ZP }, // 0x65 + { MOS65XX_INS_ROR , MOS65XX_AM_ZP }, // 0x66 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x67 + { MOS65XX_INS_PLA , MOS65XX_AM_IMP }, // 0x68 + { MOS65XX_INS_ADC , MOS65XX_AM_IMM }, // 0x69 + { MOS65XX_INS_ROR , MOS65XX_AM_ACC }, // 0x6a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x6b + { MOS65XX_INS_JMP , MOS65XX_AM_IND }, // 0x6c + { MOS65XX_INS_ADC , MOS65XX_AM_ABS }, // 0x6d + { MOS65XX_INS_ROR , MOS65XX_AM_ABS }, // 0x6e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x6f + { MOS65XX_INS_BVS , MOS65XX_AM_REL }, // 0x70 + { MOS65XX_INS_ADC , MOS65XX_AM_INDY }, // 0x71 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x72 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x73 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x74 + { MOS65XX_INS_ADC , MOS65XX_AM_ZPX }, // 0x75 + { MOS65XX_INS_ROR , MOS65XX_AM_ZPX }, // 0x76 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x77 + { MOS65XX_INS_SEI , MOS65XX_AM_IMP }, // 0x78 + { MOS65XX_INS_ADC , MOS65XX_AM_ABSY }, // 0x79 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x7a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x7b + { MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x7c + { MOS65XX_INS_ADC , MOS65XX_AM_ABSX }, // 0x7d + { MOS65XX_INS_ROR , MOS65XX_AM_ABSX }, // 0x7e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x7f + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x80 + { MOS65XX_INS_STA , MOS65XX_AM_INDX }, // 0x81 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x82 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x83 + { MOS65XX_INS_STY , MOS65XX_AM_ZP }, // 0x84 + { MOS65XX_INS_STA , MOS65XX_AM_ZP }, // 0x85 + { MOS65XX_INS_STX , MOS65XX_AM_ZP }, // 0x86 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x87 + { MOS65XX_INS_DEY , MOS65XX_AM_IMP }, // 0x88 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x89 + { MOS65XX_INS_TXA , MOS65XX_AM_IMP }, // 0x8a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x8b + { MOS65XX_INS_STY , MOS65XX_AM_ABS }, // 0x8c + { MOS65XX_INS_STA , MOS65XX_AM_ABS }, // 0x8d + { MOS65XX_INS_STX , MOS65XX_AM_ABS }, // 0x8e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x8f + { MOS65XX_INS_BCC , MOS65XX_AM_REL }, // 0x90 + { MOS65XX_INS_STA , MOS65XX_AM_INDY }, // 0x91 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x92 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x93 + { MOS65XX_INS_STY , MOS65XX_AM_ZPX }, // 0x94 + { MOS65XX_INS_STA , MOS65XX_AM_ZPX }, // 0x95 + { MOS65XX_INS_STX , MOS65XX_AM_ZPY }, // 0x96 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x97 + { MOS65XX_INS_TYA , MOS65XX_AM_IMP }, // 0x98 + { MOS65XX_INS_STA , MOS65XX_AM_ABSY }, // 0x99 + { MOS65XX_INS_TXS , MOS65XX_AM_IMP }, // 0x9a + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9b + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9c + { MOS65XX_INS_STA , MOS65XX_AM_ABSX }, // 0x9d + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9e + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9f + { MOS65XX_INS_LDY , MOS65XX_AM_IMM }, // 0xa0 + { MOS65XX_INS_LDA , MOS65XX_AM_INDX }, // 0xa1 + { MOS65XX_INS_LDX , MOS65XX_AM_IMM }, // 0xa2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xa3 + { MOS65XX_INS_LDY , MOS65XX_AM_ZP }, // 0xa4 + { MOS65XX_INS_LDA , MOS65XX_AM_ZP }, // 0xa5 + { MOS65XX_INS_LDX , MOS65XX_AM_ZP }, // 0xa6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xa7 + { MOS65XX_INS_TAY , MOS65XX_AM_IMP }, // 0xa8 + { MOS65XX_INS_LDA , MOS65XX_AM_IMM }, // 0xa9 + { MOS65XX_INS_TAX , MOS65XX_AM_IMP }, // 0xaa + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xab + { MOS65XX_INS_LDY , MOS65XX_AM_ABS }, // 0xac + { MOS65XX_INS_LDA , MOS65XX_AM_ABS }, // 0xad + { MOS65XX_INS_LDX , MOS65XX_AM_ABS }, // 0xae + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xaf + { MOS65XX_INS_BCS , MOS65XX_AM_REL }, // 0xb0 + { MOS65XX_INS_LDA , MOS65XX_AM_INDY }, // 0xb1 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb3 + { MOS65XX_INS_LDY , MOS65XX_AM_ZPX }, // 0xb4 + { MOS65XX_INS_LDA , MOS65XX_AM_ZPX }, // 0xb5 + { MOS65XX_INS_LDX , MOS65XX_AM_ZPY }, // 0xb6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb7 + { MOS65XX_INS_CLV , MOS65XX_AM_IMP }, // 0xb8 + { MOS65XX_INS_LDA , MOS65XX_AM_ABSY }, // 0xb9 + { MOS65XX_INS_TSX , MOS65XX_AM_IMP }, // 0xba + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xbb + { MOS65XX_INS_LDY , MOS65XX_AM_ABSX }, // 0xbc + { MOS65XX_INS_LDA , MOS65XX_AM_ABSX }, // 0xbd + { MOS65XX_INS_LDX , MOS65XX_AM_ABSY }, // 0xbe + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xbf + { MOS65XX_INS_CPY , MOS65XX_AM_IMM }, // 0xc0 + { MOS65XX_INS_CMP , MOS65XX_AM_INDX }, // 0xc1 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xc2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xc3 + { MOS65XX_INS_CPY , MOS65XX_AM_ZP }, // 0xc4 + { MOS65XX_INS_CMP , MOS65XX_AM_ZP }, // 0xc5 + { MOS65XX_INS_DEC , MOS65XX_AM_ZP }, // 0xc6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xc7 + { MOS65XX_INS_INY , MOS65XX_AM_IMP }, // 0xc8 + { MOS65XX_INS_CMP , MOS65XX_AM_IMM }, // 0xc9 + { MOS65XX_INS_DEX , MOS65XX_AM_IMP }, // 0xca + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xcb + { MOS65XX_INS_CPY , MOS65XX_AM_ABS }, // 0xcc + { MOS65XX_INS_CMP , MOS65XX_AM_ABS }, // 0xcd + { MOS65XX_INS_DEC , MOS65XX_AM_ABS }, // 0xce + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xcf + { MOS65XX_INS_BNE , MOS65XX_AM_REL }, // 0xd0 + { MOS65XX_INS_CMP , MOS65XX_AM_INDY }, // 0xd1 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd3 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0xd4 + { MOS65XX_INS_CMP , MOS65XX_AM_ZPX }, // 0xd5 + { MOS65XX_INS_DEC , MOS65XX_AM_ZPX }, // 0xd6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd7 + { MOS65XX_INS_CLD , MOS65XX_AM_IMP }, // 0xd8 + { MOS65XX_INS_CMP , MOS65XX_AM_ABSY }, // 0xd9 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xda + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xdb + { MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0xdc + { MOS65XX_INS_CMP , MOS65XX_AM_ABSX }, // 0xdd + { MOS65XX_INS_DEC , MOS65XX_AM_ABSX }, // 0xde + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xdf + { MOS65XX_INS_CPX , MOS65XX_AM_IMM }, // 0xe0 + { MOS65XX_INS_SBC , MOS65XX_AM_INDX }, // 0xe1 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xe2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xe3 + { MOS65XX_INS_CPX , MOS65XX_AM_ZP }, // 0xe4 + { MOS65XX_INS_SBC , MOS65XX_AM_ZP }, // 0xe5 + { MOS65XX_INS_INC , MOS65XX_AM_ZP }, // 0xe6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xe7 + { MOS65XX_INS_INX , MOS65XX_AM_IMP }, // 0xe8 + { MOS65XX_INS_SBC , MOS65XX_AM_IMM }, // 0xe9 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xea + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xeb + { MOS65XX_INS_CPX , MOS65XX_AM_ABS }, // 0xec + { MOS65XX_INS_SBC , MOS65XX_AM_ABS }, // 0xed + { MOS65XX_INS_INC , MOS65XX_AM_ABS }, // 0xee + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xef + { MOS65XX_INS_BEQ , MOS65XX_AM_REL }, // 0xf0 + { MOS65XX_INS_SBC , MOS65XX_AM_INDY }, // 0xf1 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf2 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf3 + { MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0xf4 + { MOS65XX_INS_SBC , MOS65XX_AM_ZPX }, // 0xf5 + { MOS65XX_INS_INC , MOS65XX_AM_ZPX }, // 0xf6 + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf7 + { MOS65XX_INS_SED , MOS65XX_AM_IMP }, // 0xf8 + { MOS65XX_INS_SBC , MOS65XX_AM_ABSY }, // 0xf9 + { MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xfa + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xfb + { MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0xfc + { MOS65XX_INS_SBC , MOS65XX_AM_ABSX }, // 0xfd + { MOS65XX_INS_INC , MOS65XX_AM_ABSX }, // 0xfe + { MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xff +}; + +static const char* RegNames[] = { + "invalid", "A", "X", "Y", "P", "SP" +}; + +#ifndef CAPSTONE_DIET +static const char* GroupNames[] = { + NULL, + "jump", + "call", + "ret", + NULL, + "iret", + "branch_relative" +}; + +typedef struct InstructionInfo { + const char* name; + mos65xx_group_type group_type; + mos65xx_reg write, read; + bool modifies_status; +} InstructionInfo; + +static const struct InstructionInfo InstructionInfoTable[]= { + { "invalid", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, + { "adc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, + { "and", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, + { "asl", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "bcc", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "bcs", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "beq", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "bit", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "bmi", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "bne", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "bpl", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "brk", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_INVALID, false }, + { "bvc", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "bvs", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, + { "clc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "cld", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "cli", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "clv", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "cmp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true }, + { "cpx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, true }, + { "cpy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, true }, + { "dec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "dex", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true }, + { "dey", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true }, + { "eor", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "inc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "inx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true }, + { "iny", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true }, + { "jmp", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, + { "jsr", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, + { "lda", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, + { "ldx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true }, + { "ldy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true }, + { "lsr", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "nop", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, + { "ora", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, + { "pha", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_ACC, false }, + { "pla", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_SP, true }, + { "php", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_P, false }, + { "plp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_SP, true }, + { "rol", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "ror", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "rti", MOS65XX_GRP_IRET, MOS65XX_REG_SP, MOS65XX_REG_INVALID, true }, + { "rts", MOS65XX_GRP_RET, MOS65XX_REG_SP, MOS65XX_REG_INVALID, false }, + { "sbc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, + { "sec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "sed", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "sei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, + { "sta", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false }, + { "stx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false }, + { "sty", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false }, + { "tax", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_ACC, true }, + { "tay", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_ACC, true }, + { "tsx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_SP, true }, + { "txa", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_X, true }, + { "txs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_X, true }, + { "tya", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_Y, true }, +}; +#endif + +static int getInstructionLength(mos65xx_address_mode am) +{ + switch(am) { + case MOS65XX_AM_NONE: + case MOS65XX_AM_ACC: + case MOS65XX_AM_IMP: + return 1; + + case MOS65XX_AM_IMM: + case MOS65XX_AM_ZPX: + case MOS65XX_AM_ZPY: + case MOS65XX_AM_ZP: + case MOS65XX_AM_REL: + case MOS65XX_AM_INDX: + case MOS65XX_AM_INDY: + return 2; + + case MOS65XX_AM_ABS: + case MOS65XX_AM_ABSX: + case MOS65XX_AM_ABSY: + case MOS65XX_AM_IND: + return 3; + default: + return 1; + } +} + +#ifndef CAPSTONE_DIET +static void fillDetails(MCInst *MI, unsigned char opcode) +{ + cs_detail *detail = MI->flat_insn->detail; + mos65xx_insn ins = OpInfoTable[opcode].ins; + mos65xx_address_mode am = OpInfoTable[opcode].am; + + detail->mos65xx.am = am; + detail->mos65xx.modifies_flags = InstructionInfoTable[ins].modifies_status; + detail->groups_count = 0; + detail->regs_read_count = 0; + detail->regs_write_count = 0; + detail->mos65xx.op_count = 0; + + if (InstructionInfoTable[ins].group_type != MOS65XX_GRP_INVALID) { + detail->groups[0] = InstructionInfoTable[ins].group_type; + detail->groups_count++; + } + + if (InstructionInfoTable[ins].read != MOS65XX_REG_INVALID) { + detail->regs_read[detail->regs_read_count++] = InstructionInfoTable[ins].read; + } else if (OpInfoTable[opcode].am == MOS65XX_AM_ACC) { + detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC; + } else if (OpInfoTable[opcode].am == MOS65XX_AM_INDY || OpInfoTable[opcode].am == MOS65XX_AM_ABSY || OpInfoTable[opcode].am == MOS65XX_AM_ZPY) { + detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y; + } else if (OpInfoTable[opcode].am == MOS65XX_AM_INDX || OpInfoTable[opcode].am == MOS65XX_AM_ABSX || OpInfoTable[opcode].am == MOS65XX_AM_ZPX) { + detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X; + } + + if (InstructionInfoTable[ins].write != MOS65XX_REG_INVALID) { + detail->regs_write[detail->regs_write_count++] = InstructionInfoTable[ins].write; + } else if (OpInfoTable[opcode].am == MOS65XX_AM_ACC) { + detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC; + } + + if (InstructionInfoTable[ins].modifies_status) { + detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P; + } + + switch(am) { + case MOS65XX_AM_IMP: + case MOS65XX_AM_REL: + break; + case MOS65XX_AM_IMM: + detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM; + detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal; + detail->mos65xx.op_count++; + break; + case MOS65XX_AM_ACC: + detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_REG; + detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC; + detail->mos65xx.op_count++; + break; + default: + detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM; + detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal; + detail->mos65xx.op_count++; + break; + } +} +#endif + +void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) +{ +#ifndef CAPSTONE_DIET + unsigned char opcode = MI->Opcode; + unsigned int value = MI->Operands[0].ImmVal; + + SStream_concat0(O, InstructionInfoTable[OpInfoTable[MI->Opcode].ins].name); + + switch (OpInfoTable[opcode].am) { + default: + break; + + case MOS65XX_AM_IMP: + break; + + case MOS65XX_AM_ACC: + SStream_concat(O, " a"); + break; + + case MOS65XX_AM_ABS: + SStream_concat(O, " $0x%04x", value); + break; + + case MOS65XX_AM_IMM: + SStream_concat(O, " #$0x%02x", value); + break; + + case MOS65XX_AM_ZP: + SStream_concat(O, " $0x%02x", value); + break; + + case MOS65XX_AM_ABSX: + SStream_concat(O, " $0x%04x, x", value); + break; + + case MOS65XX_AM_ABSY: + SStream_concat(O, " $0x%04x, y", value); + break; + + case MOS65XX_AM_ZPX: + SStream_concat(O, " $0x%02x, x", value); + break; + + case MOS65XX_AM_ZPY: + SStream_concat(O, " $0x%02x, y", value); + break; + + case MOS65XX_AM_REL: + SStream_concat(O, " $0x%04x", MI->address + (signed char) value + 2); + break; + + case MOS65XX_AM_IND: + SStream_concat(O, " ($0x%04x)", value); + break; + + case MOS65XX_AM_INDX: + SStream_concat(O, " ($0x%02x, x)", value); + break; + + case MOS65XX_AM_INDY: + SStream_concat(O, " ($0x%02x), y", value); + break; + } +#endif +} + +bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) +{ + unsigned char opcode; + unsigned char len; + mos65xx_insn ins; + + if (code_len == 0) { + *size = 1; + return false; + } + + opcode = code[0]; + ins = OpInfoTable[opcode].ins; + if (ins == MOS65XX_INS_INVALID) { + *size = 1; + return false; + } + + len = getInstructionLength(OpInfoTable[opcode].am); + if (code_len < len) { + *size = 1; + return false; + } + + MI->address = address; + MI->Opcode = opcode; + MI->OpcodePub = ins; + MI->size = 0; + + *size = len; + if (len == 2) { + MCOperand_CreateImm0(MI, code[1]); + } else + if (len == 3) { + MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]); + } +#ifndef CAPSTONE_DIET + if (MI->flat_insn->detail) { + fillDetails(MI, opcode); + } +#endif + + return true; +} + +const char *MOS65XX_insn_name(csh handle, unsigned int id) +{ +#ifdef CAPSTONE_DIET + return NULL; +#else + if (id >= ARR_SIZE(InstructionInfoTable)) { + return NULL; + } + return InstructionInfoTable[id].name; +#endif +} + +const char* MOS65XX_reg_name(csh handle, unsigned int reg) +{ +#ifdef CAPSTONE_DIET + return NULL; +#else + if (reg >= ARR_SIZE(RegNames)) { + return NULL; + } + return RegNames[(int)reg]; +#endif +} + +void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + if (id < 256) { + insn->id = OpInfoTable[id].ins; + } +} + +const char *MOS65XX_group_name(csh handle, unsigned int id) +{ +#ifdef CAPSTONE_DIET + return NULL; +#else + if (id >= ARR_SIZE(GroupNames)) { + return NULL; + } + return GroupNames[(int)id]; +#endif +} diff --git a/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.h b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.h new file mode 100644 index 0000000..ad663cd --- /dev/null +++ b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXDisassembler.h @@ -0,0 +1,22 @@ +/* Capstone Disassembly Engine */ +/* MOS65XX Backend by Sebastian Macke 2018 */ + +#ifndef CAPSTONE_MOS65XXDISASSEMBLER_H +#define CAPSTONE_MOS65XXDISASSEMBLER_H + +#include "../../utils.h" + +void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo); + +void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *MOS65XX_insn_name(csh handle, unsigned int id); + +const char *MOS65XX_group_name(csh handle, unsigned int id); + +const char* MOS65XX_reg_name(csh handle, unsigned int reg); + +bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, void *inst_info); + +#endif //CAPSTONE_MOS65XXDISASSEMBLER_H diff --git a/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.c b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.c new file mode 100644 index 0000000..c535b4e --- /dev/null +++ b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.c @@ -0,0 +1,33 @@ +/* Capstone Disassembly Engine */ +/* MOS65XX Backend by Sebastian Macke 2018 */ + +#ifdef CAPSTONE_HAS_MOS65XX + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "MOS65XXDisassembler.h" +#include "MOS65XXModule.h" + +cs_err MOS65XX_global_init(cs_struct *ud) +{ + // verify if requested mode is valid + if (ud->mode) + return CS_ERR_MODE; + + ud->printer = MOS65XX_printInst; + ud->printer_info = NULL; + ud->insn_id = MOS65XX_get_insn_id; + ud->insn_name = MOS65XX_insn_name; + ud->group_name = MOS65XX_group_name; + ud->disasm = MOS65XX_getInstruction; + ud->reg_name = MOS65XX_reg_name; + + return CS_ERR_OK; +} + +cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.h b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.h new file mode 100644 index 0000000..1d1ad9d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/MOS65XX/MOS65XXModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Sebastian Macke , 2018 */ + +#ifndef CS_MOS65XX_MODULE_H +#define CS_MOS65XX_MODULE_H + +#include "../../utils.h" + +cs_err MOS65XX_global_init(cs_struct *ud); +cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.c b/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.c new file mode 100644 index 0000000..2940823 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.c @@ -0,0 +1,1794 @@ +//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is part of the Mips Disassembler. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_MIPS + +#include +#include + +#include "capstone/platform.h" + +#include "MipsDisassembler.h" + +#include "../../utils.h" + +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +#include "../../MathExtras.h" + +//#include "Mips.h" +//#include "MipsRegisterInfo.h" +//#include "MipsSubtarget.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCInst.h" +//#include "llvm/MC/MCSubtargetInfo.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" + +// Forward declare these because the autogenerated code will reference them. +// Definitions are further down. +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); + +// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, + unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); + +// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, + unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); + +// DecodeBranchTargetMM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); + +// DecodeJumpTargetMM - Decode microMIPS jump target, which is +// shifted left by 1 bit. +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMem(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCacheOp(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCacheOpR6(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSyncI(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, + uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeLiSimm7(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm4(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm16(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +// Decode the immediate field of an LSA instruction which +// is off by one. +static DecodeStatus DecodeLSAImm(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeInsSize(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeExtSize(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); + +/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't +/// handle. +static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, + uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, + uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, + uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); + +#define GET_SUBTARGETINFO_ENUM +#include "MipsGenSubtargetInfo.inc" + +// Hacky: enable all features for disassembler +static uint64_t getFeatureBits(int mode) +{ + uint64_t Bits = (uint64_t)-1; // include every features at first + + // By default we do not support Mips1 + Bits &= ~Mips_FeatureMips1; + + // No MicroMips + Bits &= ~Mips_FeatureMicroMips; + + // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() + // some features are mutually execlusive + if (mode & CS_MODE_16) { + //Bits &= ~Mips_FeatureMips32r2; + //Bits &= ~Mips_FeatureMips32; + //Bits &= ~Mips_FeatureFPIdx; + //Bits &= ~Mips_FeatureBitCount; + //Bits &= ~Mips_FeatureSwap; + //Bits &= ~Mips_FeatureSEInReg; + //Bits &= ~Mips_FeatureMips64r2; + //Bits &= ~Mips_FeatureFP64Bit; + } else if (mode & CS_MODE_32) { + Bits &= ~Mips_FeatureMips16; + Bits &= ~Mips_FeatureFP64Bit; + Bits &= ~Mips_FeatureMips64r2; + Bits &= ~Mips_FeatureMips32r6; + Bits &= ~Mips_FeatureMips64r6; + } else if (mode & CS_MODE_64) { + Bits &= ~Mips_FeatureMips16; + Bits &= ~Mips_FeatureMips64r6; + Bits &= ~Mips_FeatureMips32r6; + } else if (mode & CS_MODE_MIPS32R6) { + Bits |= Mips_FeatureMips32r6; + Bits &= ~Mips_FeatureMips16; + Bits &= ~Mips_FeatureFP64Bit; + Bits &= ~Mips_FeatureMips64r6; + Bits &= ~Mips_FeatureMips64r2; + } + + if (mode & CS_MODE_MICRO) { + Bits |= Mips_FeatureMicroMips; + Bits &= ~Mips_FeatureMips4_32r2; + Bits &= ~Mips_FeatureMips2; + } + + return Bits; +} + +#include "MipsGenDisassemblerTables.inc" + +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "MipsGenRegisterInfo.inc" + +#define GET_INSTRINFO_ENUM +#include "MipsGenInstrInfo.inc" + +void Mips_init(MCRegisterInfo *MRI) +{ + // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, + // MipsMCRegisterClasses, 62, + // MipsRegUnitRoots, + // 273, + // MipsRegDiffLists, + // MipsLaneMaskLists, + // MipsRegStrings, + // MipsRegClassStrings, + // MipsSubRegIdxLists, + // 12, + // MipsSubRegIdxRanges, + // MipsRegEncodingTable); + + + MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, + 0, 0, + MipsMCRegisterClasses, 62, + 0, 0, + MipsRegDiffLists, + 0, + MipsSubRegIdxLists, 12, + 0); +} + +/// Read two bytes from the ArrayRef and return 16 bit halfword sorted +/// according to the given endianess. +static void readInstruction16(unsigned char *code, uint32_t *insn, + bool isBigEndian) +{ + // We want to read exactly 2 Bytes of data. + if (isBigEndian) + *insn = (code[0] << 8) | code[1]; + else + *insn = (code[1] << 8) | code[0]; +} + +/// readInstruction - read four bytes from the MemoryObject +/// and return 32 bit word sorted according to the given endianess +static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) +{ + // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // microMIPS byte ordering: + // Big-endian: 0 | 1 | 2 | 3 + // Little-endian: 1 | 0 | 3 | 2 + + // We want to read exactly 4 Bytes of data. + if (isBigEndian) { + // Encoded as a big-endian 32-bit word in the stream. + *insn = + (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); + } else { + if (isMicroMips) { + *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | + ((uint32_t) code[1] << 24); + } else { + *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | + ((uint32_t) code[3] << 24); + } + } +} + +static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, + const uint8_t *code, size_t code_len, + uint16_t *Size, + uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) +{ + uint32_t Insn; + DecodeStatus Result; + + if (instr->flat_insn->detail) { + memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); + } + + if (mode & CS_MODE_MICRO) { + if (code_len < 2) + // not enough data + return MCDisassembler_Fail; + + readInstruction16((unsigned char*)code, &Insn, isBigEndian); + + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); + + //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + return MCDisassembler_Fail; + } + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); + + if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { + // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { + // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, + Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if (mode & CS_MODE_MIPS32R6) { + // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, + Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if (mode & CS_MODE_MIPS64) { + // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips6432, instr, Insn, + Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + return MCDisassembler_Fail; +} + +bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info) +{ + cs_struct *handle = (cs_struct *)(uintptr_t)ud; + + DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, + code, code_len, + size, + address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) +{ + const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); + return rc->RegsBegin[RegNo]; +} + +static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); + // The size of the n field depends on the element size + // The register class also depends on this. + uint32_t tmp = fieldFromInstruction(insn, 17, 5); + unsigned NSize = 0; + DecodeFN RegDecoder = NULL; + + if ((tmp & 0x18) == 0x00) { // INSVE_B + NSize = 4; + RegDecoder = DecodeMSA128BRegisterClass; + } else if ((tmp & 0x1c) == 0x10) { // INSVE_H + NSize = 3; + RegDecoder = DecodeMSA128HRegisterClass; + } else if ((tmp & 0x1e) == 0x18) { // INSVE_W + NSize = 2; + RegDecoder = DecodeMSA128WRegisterClass; + } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D + NSize = 1; + RegDecoder = DecodeMSA128DRegisterClass; + } //else llvm_unreachable("Invalid encoding"); + + //assert(NSize != 0 && RegDecoder != nullptr); + if (NSize == 0 || RegDecoder == NULL) + return MCDisassembler_Fail; + + // $wd + tmp = fieldFromInstruction(insn, 6, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + + // $wd_in + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + + // $n + tmp = fieldFromInstruction(insn, 16, NSize); + MCOperand_CreateImm0(MI, tmp); + + // $ws + tmp = fieldFromInstruction(insn, 11, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + + // $n2 + MCOperand_CreateImm0(MI, 0); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b001000 sssss ttttt iiiiiiiiiiiiiiii + // BOVC if rs >= rt + // BEQZALC if rs == 0 && rt != 0 + // BEQC if rs < rt && rs != 0 + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BOVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BEQC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BEQZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b011000 sssss ttttt iiiiiiiiiiiiiiii + // BNVC if rs >= rt + // BNEZALC if rs == 0 && rt != 0 + // BNEC if rs < rt && rs != 0 + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BNVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BNEC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BNEZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZC if rs == 0 && rt != 0 + // BGEZC if rs == rt && rt != 0 + // BGEC if rs != rt && rs != 0 && rt != 0 + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010111 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BGTZC if rs == 0 && rt != 0 + // BLTZC if rs == rt && rt != 0 + // BLTC if rs != rt && rs != 0 && rt != 0 + + bool HasRs = false; + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BGTZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BLTZC); + else { + MCInst_setOpcode(MI, Mips_BLTC); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZ instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000111 sssss ttttt iiiiiiiiiiiiiiii + // BGTZ if rt == 0 + // BGTZALC if rs == 0 && rt != 0 + // BLTZALC if rs != 0 && rs == rt + // BLTUC if rs != 0 && rs != rt + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) { + MCInst_setOpcode(MI, Mips_BGTZ); + HasRs = true; + } else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BGTZALC); + HasRt = true; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BLTZALC); + HasRs = true; + } else { + MCInst_setOpcode(MI, Mips_BLTUC); + HasRs = true; + HasRt = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + if (HasRt) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZALC if rs == 0 && rt != 0 + // BGEZALC if rs == rt && rt != 0 + // BGEUC if rs != rt && rs != 0 && rt != 0 + + uint32_t Rs = fieldFromInstruction(insn, 21, 5); + uint32_t Rt = fieldFromInstruction(insn, 16, 5); + uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZALC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZALC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEUC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + // if (static_cast(Decoder)->isGP64()) + if (Inst->csh->mode & CS_MODE_MIPS64) + return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMem(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + int opcode = MCInst_getOpcode(Inst); + + Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + if (opcode == Mips_SC || opcode == Mips_SCD) { + MCOperand_CreateReg0(Inst, Reg); + } + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCacheOp(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xfff, 12); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCacheOpR6(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = fieldFromInstruction(Insn, 7, 9); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSyncI(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); + unsigned Reg = fieldFromInstruction(Insn, 6, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + // MCOperand_CreateImm0(Inst, Offset); + + // The immediate field of an LD/ST instruction is scaled which means it must + // be multiplied (when decoding) by the size (in bytes) of the instructions' + // data format. + // .b - 1 byte + // .h - 2 bytes + // .w - 4 bytes + // .d - 8 bytes + switch(MCInst_getOpcode(Inst)) { + default: + //assert (0 && "Unexpected instruction"); + return MCDisassembler_Fail; + break; + case Mips_LD_B: + case Mips_ST_B: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LD_H: + case Mips_ST_H: + MCOperand_CreateImm0(Inst, Offset * 2); + break; + case Mips_LD_W: + case Mips_ST_W: + MCOperand_CreateImm0(Inst, Offset * 4); + break; + case Mips_LD_D: + case Mips_ST_D: + MCOperand_CreateImm0(Inst, Offset * 8); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Offset = Insn & 0xf; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned Base = fieldFromInstruction(Insn, 4, 3); + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + case Mips_LHU16_MM: + case Mips_LW16_MM: + if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) + == MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + case Mips_SB16_MM: + case Mips_SH16_MM: + case Mips_SW16_MM: + if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) + == MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + } + + if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) + == MCDisassembler_Fail) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + if (Offset == 0xf) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SB16_MM: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LHU16_MM: + case Mips_SH16_MM: + MCOperand_CreateImm0(Inst, Offset << 1); + break; + case Mips_LW16_MM: + case Mips_SW16_MM: + MCOperand_CreateImm0(Inst, Offset << 2); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Offset = Insn & 0x1F; + unsigned Reg = fieldFromInstruction(Insn, 5, 5); + + Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Offset = Insn & 0x7F; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + + Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_GP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xf, 4); + + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset * 4); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0x0fff, 12); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + switch (MCInst_getOpcode(Inst)) { + case Mips_SWM32_MM: + case Mips_LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) + == MCDisassembler_Fail) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SC_MM: + MCOperand_CreateReg0(Inst, Reg); + // fallthrough + default: + MCOperand_CreateReg0(Inst, Reg); + if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) + MCOperand_CreateReg0(Inst, Reg + 1); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMem(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMem2(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMem3(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, + unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) +{ + int Offset = SignExtend32(Insn & 0x07ff, 11); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); + Base = getReg(Decoder, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC_R6 || + MCInst_getOpcode(Inst) == Mips_SCD_R6) { + MCOperand_CreateReg0(Inst, Rt); + } + + MCOperand_CreateReg0(Inst, Rt); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + // Currently only hardware register 29 is supported. + if (RegNo != 29) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Mips_HWR29); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 30 || RegNo % 2) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo >= 4) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo >= 4) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo >= 4) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 7) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +{ + uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; + MCOperand_CreateImm0(Inst, TargetAddress); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); + MCOperand_CreateImm0(Inst, TargetAddress); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int32_t BranchOffset = SignExtend32(Offset, 21) * 4; + + MCOperand_CreateImm0(Inst, BranchOffset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int32_t BranchOffset = SignExtend32(Offset, 26) * 4; + + MCOperand_CreateImm0(Inst, BranchOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, + unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) +{ + int32_t BranchOffset = SignExtend32(Offset, 7) * 2; + MCOperand_CreateImm0(Inst, BranchOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, + unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) +{ + int32_t BranchOffset = SignExtend32(Offset, 10) * 2; + MCOperand_CreateImm0(Inst, BranchOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, + unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int32_t BranchOffset = SignExtend32(Offset, 16) * 2; + MCOperand_CreateImm0(Inst, BranchOffset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; + MCOperand_CreateImm0(Inst, JumpOffset); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +{ + if (Value == 0) + MCOperand_CreateImm0(Inst, 1); + else if (Value == 0x7) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, Value << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLiSimm7(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +{ + if (Value == 0x7F) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm4(MCInst *Inst, + unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm16(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLSAImm(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + // We add one to the immediate field as it was encoded as 'imm - 1'. + MCOperand_CreateImm0(Inst, Insn + 1); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeInsSize(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + // First we need to grab the pos(lsb) from MCInst. + int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); + int Size = (int) Insn - Pos + 1; + MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeExtSize(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + int Size = (int)Insn + 1; + + MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, + unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + int32_t DecodedValue; + + switch (Insn) { + case 0: DecodedValue = 256; break; + case 1: DecodedValue = 257; break; + case 510: DecodedValue = -258; break; + case 511: DecodedValue = -257; break; + default: DecodedValue = SignExtend32(Insn, 9); break; + } + MCOperand_CreateImm0(Inst, DecodedValue * 4); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + // Insn must be >= 0, since it is unsigned that condition is always true. + // assert(Insn < 16); + int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, + 255, 32768, 65535}; + + if (Insn >= 16) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, DecodedValues[Insn]); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, Insn << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const MCRegisterInfo *Decoder) +{ + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, + Mips_S6, Mips_FP}; + unsigned RegNum; + unsigned int i; + + unsigned RegLst = fieldFromInstruction(Insn, 21, 5); + // Empty register lists are not allowed. + if (RegLst == 0) + return MCDisassembler_Fail; + + RegNum = RegLst & 0xf; + for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + if (RegLst & 0x10) + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; + unsigned RegLst = fieldFromInstruction(Insn, 4, 2); + unsigned RegNum = RegLst & 0x3; + unsigned int i; + + for (i = 0; i <= RegNum; i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + + switch (RegPair) { + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 1: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 2: + MCOperand_CreateReg0(Inst, Mips_A2); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 3: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S5); + break; + case 4: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S6); + break; + case 5: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A1); + break; + case 6: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 7: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, MCRegisterInfo *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); + return MCDisassembler_Success; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.h b/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.h new file mode 100644 index 0000000..961c5f1 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsDisassembler.h @@ -0,0 +1,16 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_MIPSDISASSEMBLER_H +#define CS_MIPSDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" + +void Mips_init(MCRegisterInfo *MRI); + +bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/Mips/MipsGenAsmWriter.inc new file mode 100644 index 0000000..cd25213 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsGenAsmWriter.inc @@ -0,0 +1,5725 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 9396U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 9389U, // BUNDLE + 9406U, // LIFETIME_START + 9376U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 21660U, // ABSQ_S_PH + 18025U, // ABSQ_S_QB + 24850U, // ABSQ_S_W + 134237992U, // ADD + 18294U, // ADDIUPC + 18294U, // ADDIUPC_MM + 22527U, // ADDIUR1SP_MM + 134234410U, // ADDIUR2_MM + 8683851U, // ADDIUS5_MM + 546875U, // ADDIUSP_MM + 134239193U, // ADDQH_PH + 134239310U, // ADDQH_R_PH + 134242253U, // ADDQH_R_W + 134241856U, // ADDQH_W + 134239267U, // ADDQ_PH + 134239366U, // ADDQ_S_PH + 134242558U, // ADDQ_S_W + 134236055U, // ADDSC + 134234730U, // ADDS_A_B + 134236180U, // ADDS_A_D + 134238138U, // ADDS_A_H + 134241564U, // ADDS_A_W + 134235198U, // ADDS_S_B + 134237269U, // ADDS_S_D + 134238695U, // ADDS_S_H + 134242608U, // ADDS_S_W + 134235413U, // ADDS_U_B + 134237736U, // ADDS_U_D + 134238973U, // ADDS_U_H + 134243026U, // ADDS_U_W + 134234575U, // ADDU16_MM + 134235621U, // ADDUH_QB + 134235729U, // ADDUH_R_QB + 134239465U, // ADDU_PH + 134235834U, // ADDU_QB + 134239410U, // ADDU_S_PH + 134235775U, // ADDU_S_QB + 2281718627U, // ADDVI_B + 2281720348U, // ADDVI_D + 2281722002U, // ADDVI_H + 2281725637U, // ADDVI_W + 134235491U, // ADDV_B + 134237836U, // ADDV_D + 134239051U, // ADDV_H + 134243126U, // ADDV_W + 134236094U, // ADDWC + 134234712U, // ADD_A_B + 134236161U, // ADD_A_D + 134238120U, // ADD_A_H + 134241545U, // ADD_A_W + 134237992U, // ADD_MM + 134239685U, // ADDi + 134239685U, // ADDi_MM + 134241307U, // ADDiu + 134241307U, // ADDiu_MM + 134241261U, // ADDu + 134241261U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 134240158U, // ALIGN + 18286U, // ALUIPC + 134238014U, // AND + 835930U, // AND16_MM + 134238014U, // AND64 + 134234471U, // ANDI16_MM + 2281718486U, // ANDI_B + 134238014U, // AND_MM + 134241389U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 134239691U, // ANDi + 134239691U, // ANDi64 + 134239691U, // ANDi_MM + 134238028U, // APPEND + 134235092U, // ASUB_S_B + 134237099U, // ASUB_S_D + 134238527U, // ASUB_S_H + 134242388U, // ASUB_S_W + 134235307U, // ASUB_U_B + 134237566U, // ASUB_U_D + 134238815U, // ASUB_U_H + 134242856U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 134239795U, // AUI + 18279U, // AUIPC + 134235178U, // AVER_S_B + 134237249U, // AVER_S_D + 134238665U, // AVER_S_H + 134242588U, // AVER_S_W + 134235393U, // AVER_U_B + 134237716U, // AVER_U_D + 134238953U, // AVER_U_H + 134243006U, // AVER_U_W + 134235120U, // AVE_S_B + 134237181U, // AVE_S_D + 134238597U, // AVE_S_H + 134242470U, // AVE_S_W + 134235335U, // AVE_U_B + 134237648U, // AVE_U_D + 134238885U, // AVE_U_H + 134242938U, // AVE_U_W + 23579U, // AddiuRxImmX16 + 1072155U, // AddiuRxPcImmX16 + 285236251U, // AddiuRxRxImm16 + 16800795U, // AddiuRxRxImmX16 + 25189403U, // AddiuRxRyOffMemX16 + 1336343U, // AddiuSpImm16 + 549911U, // AddiuSpImmX16 + 134241261U, // AdduRxRyRz16 + 16797502U, // AndRxRxRy16 + 0U, // B + 541013U, // B16_MM + 134241260U, // BADDu + 546393U, // BAL + 542494U, // BALC + 134240157U, // BALIGN + 0U, // BAL_BR + 167788585U, // BBIT0 + 167788717U, // BBIT032 + 167788710U, // BBIT1 + 167788726U, // BBIT132 + 542473U, // BC + 20351U, // BC0F + 22218U, // BC0FL + 23455U, // BC0T + 22347U, // BC0TL + 25733U, // BC1EQZ + 20357U, // BC1F + 22225U, // BC1FL + 20357U, // BC1F_MM + 25717U, // BC1NEZ + 23461U, // BC1T + 22354U, // BC1TL + 23461U, // BC1T_MM + 25741U, // BC2EQZ + 20363U, // BC2F + 22232U, // BC2FL + 25725U, // BC2NEZ + 23467U, // BC2T + 22361U, // BC2TL + 20369U, // BC3F + 22239U, // BC3FL + 23473U, // BC3T + 22368U, // BC3TL + 2281718555U, // BCLRI_B + 2281720292U, // BCLRI_D + 2281721946U, // BCLRI_H + 2281725581U, // BCLRI_W + 134235059U, // BCLR_B + 134237023U, // BCLR_D + 134238494U, // BCLR_H + 134242304U, // BCLR_W + 134240340U, // BEQ + 134240340U, // BEQ64 + 134236044U, // BEQC + 134240063U, // BEQL + 16882U, // BEQZ16_MM + 18246U, // BEQZALC + 18394U, // BEQZC + 18394U, // BEQZC_MM + 134240340U, // BEQ_MM + 134235917U, // BGEC + 134236068U, // BGEUC + 25500U, // BGEZ + 25500U, // BGEZ64 + 22115U, // BGEZAL + 18219U, // BGEZALC + 22311U, // BGEZALL + 23424U, // BGEZALS_MM + 22115U, // BGEZAL_MM + 18373U, // BGEZC + 22391U, // BGEZL + 25500U, // BGEZ_MM + 25560U, // BGTZ + 25560U, // BGTZ64 + 18255U, // BGTZALC + 18401U, // BGTZC + 22405U, // BGTZL + 25560U, // BGTZ_MM + 2298495744U, // BINSLI_B + 2298497481U, // BINSLI_D + 2298499135U, // BINSLI_H + 2298502770U, // BINSLI_W + 151012243U, // BINSL_B + 151014033U, // BINSL_D + 151015601U, // BINSL_H + 151019280U, // BINSL_W + 2298495805U, // BINSRI_B + 2298497526U, // BINSRI_D + 2298499180U, // BINSRI_H + 2298502815U, // BINSRI_W + 151012291U, // BINSR_B + 151014289U, // BINSR_D + 151015726U, // BINSR_H + 151019570U, // BINSR_W + 23733U, // BITREV + 22477U, // BITSWAP + 25506U, // BLEZ + 25506U, // BLEZ64 + 18228U, // BLEZALC + 18380U, // BLEZC + 22398U, // BLEZL + 25506U, // BLEZ_MM + 134236062U, // BLTC + 134236075U, // BLTUC + 25566U, // BLTZ + 25566U, // BLTZ64 + 22123U, // BLTZAL + 18264U, // BLTZALC + 22320U, // BLTZALL + 23433U, // BLTZALS_MM + 22123U, // BLTZAL_MM + 18408U, // BLTZC + 22412U, // BLTZL + 25566U, // BLTZ_MM + 2298495860U, // BMNZI_B + 151018662U, // BMNZ_V + 2298495852U, // BMZI_B + 151018648U, // BMZ_V + 134238058U, // BNE + 134238058U, // BNE64 + 134235923U, // BNEC + 2281718494U, // BNEGI_B + 2281720240U, // BNEGI_D + 2281721894U, // BNEGI_H + 2281725529U, // BNEGI_W + 134234814U, // BNEG_B + 134236568U, // BNEG_D + 134238222U, // BNEG_H + 134241776U, // BNEG_W + 134239940U, // BNEL + 16874U, // BNEZ16_MM + 18237U, // BNEZALC + 18387U, // BNEZC + 18387U, // BNEZC_MM + 134238058U, // BNE_MM + 134236082U, // BNVC + 17803U, // BNZ_B + 20233U, // BNZ_D + 21363U, // BNZ_H + 23711U, // BNZ_V + 25463U, // BNZ_W + 134236088U, // BOVC + 540871U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 22080U, // BREAK + 65909U, // BREAK16_MM + 22080U, // BREAK_MM + 2298495719U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 151018620U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 2281718609U, // BSETI_B + 2281720330U, // BSETI_D + 2281721984U, // BSETI_H + 2281725619U, // BSETI_W + 134235275U, // BSET_B + 134237385U, // BSET_D + 134238783U, // BSET_H + 134242762U, // BSET_W + 17797U, // BZ_B + 20217U, // BZ_D + 21357U, // BZ_H + 23698U, // BZ_V + 25457U, // BZ_W + 541278U, // B_MM_Pseudo + 402678723U, // BeqzRxImm16 + 25539U, // BeqzRxImmX16 + 1327710U, // Bimm16 + 541278U, // BimmX16 + 402678696U, // BnezRxImm16 + 25512U, // BnezRxImmX16 + 9368U, // Break16 + 1598417U, // Bteqz16 + 536893428U, // BteqzT8CmpX16 + 536892936U, // BteqzT8CmpiX16 + 536894397U, // BteqzT8SltX16 + 536892966U, // BteqzT8SltiX16 + 536894505U, // BteqzT8SltiuX16 + 536894541U, // BteqzT8SltuX16 + 549841U, // BteqzX16 + 1598390U, // Btnez16 + 671111156U, // BtnezT8CmpX16 + 671110664U, // BtnezT8CmpiX16 + 671112125U, // BtnezT8SltX16 + 671110694U, // BtnezT8SltiX16 + 671112233U, // BtnezT8SltiuX16 + 671112269U, // BtnezT8SltuX16 + 549814U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 85859U, // CACHE + 85859U, // CACHE_MM + 85859U, // CACHE_R6 + 19003U, // CEIL_L_D64 + 23031U, // CEIL_L_S + 20179U, // CEIL_W_D32 + 20179U, // CEIL_W_D64 + 20179U, // CEIL_W_MM + 23353U, // CEIL_W_S + 23353U, // CEIL_W_S_MM + 134234890U, // CEQI_B + 134236627U, // CEQI_D + 134238281U, // CEQI_H + 134241916U, // CEQI_W + 134235044U, // CEQ_B + 134236930U, // CEQ_D + 134238472U, // CEQ_H + 134242192U, // CEQ_W + 16444U, // CFC1 + 16444U, // CFC1_MM + 16968U, // CFCMSA + 134243407U, // CINS + 134243363U, // CINS32 + 19639U, // CLASS_D + 23205U, // CLASS_S + 134235129U, // CLEI_S_B + 134237190U, // CLEI_S_D + 134238606U, // CLEI_S_H + 134242479U, // CLEI_S_W + 2281718992U, // CLEI_U_B + 2281721305U, // CLEI_U_D + 2281722542U, // CLEI_U_H + 2281726595U, // CLEI_U_W + 134235111U, // CLE_S_B + 134237172U, // CLE_S_D + 134238588U, // CLE_S_H + 134242461U, // CLE_S_W + 134235326U, // CLE_U_B + 134237639U, // CLE_U_D + 134238876U, // CLE_U_H + 134242929U, // CLE_U_W + 22452U, // CLO + 22452U, // CLO_MM + 22452U, // CLO_R6 + 134235149U, // CLTI_S_B + 134237210U, // CLTI_S_D + 134238626U, // CLTI_S_H + 134242499U, // CLTI_S_W + 2281719012U, // CLTI_U_B + 2281721325U, // CLTI_U_D + 2281722562U, // CLTI_U_H + 2281726615U, // CLTI_U_W + 134235217U, // CLT_S_B + 134237288U, // CLT_S_D + 134238714U, // CLT_S_H + 134242627U, // CLT_S_W + 134235444U, // CLT_U_B + 134237767U, // CLT_U_D + 134239004U, // CLT_U_H + 134243057U, // CLT_U_W + 25534U, // CLZ + 25534U, // CLZ_MM + 25534U, // CLZ_R6 + 134235667U, // CMPGDU_EQ_QB + 134235572U, // CMPGDU_LE_QB + 134235786U, // CMPGDU_LT_QB + 134235681U, // CMPGU_EQ_QB + 134235586U, // CMPGU_LE_QB + 134235800U, // CMPGU_LT_QB + 17966U, // CMPU_EQ_QB + 17871U, // CMPU_LE_QB + 18085U, // CMPU_LT_QB + 134236919U, // CMP_EQ_D + 21548U, // CMP_EQ_PH + 134240864U, // CMP_EQ_S + 134236489U, // CMP_F_D + 134240675U, // CMP_F_S + 134236333U, // CMP_LE_D + 21444U, // CMP_LE_PH + 134240596U, // CMP_LE_S + 134237410U, // CMP_LT_D + 21717U, // CMP_LT_PH + 134240959U, // CMP_LT_S + 134236507U, // CMP_SAF_D + 134240685U, // CMP_SAF_S + 134236946U, // CMP_SEQ_D + 134240883U, // CMP_SEQ_S + 134236370U, // CMP_SLE_D + 134240625U, // CMP_SLE_S + 134237437U, // CMP_SLT_D + 134240978U, // CMP_SLT_S + 134236994U, // CMP_SUEQ_D + 134240914U, // CMP_SUEQ_S + 134236418U, // CMP_SULE_D + 134240656U, // CMP_SULE_S + 134237485U, // CMP_SULT_D + 134241009U, // CMP_SULT_S + 134236876U, // CMP_SUN_D + 134240837U, // CMP_SUN_S + 134236974U, // CMP_UEQ_D + 134240903U, // CMP_UEQ_S + 134236398U, // CMP_ULE_D + 134240645U, // CMP_ULE_S + 134237465U, // CMP_ULT_D + 134240998U, // CMP_ULT_S + 134236858U, // CMP_UN_D + 134240827U, // CMP_UN_S + 9454U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 2952807544U, // COPY_S_B + 2952809637U, // COPY_S_D + 2952811052U, // COPY_S_H + 2952814987U, // COPY_S_W + 2952807759U, // COPY_U_B + 2952810104U, // COPY_U_D + 2952811319U, // COPY_U_H + 2952815394U, // COPY_U_W + 1867863U, // CTC1 + 1867863U, // CTC1_MM + 16976U, // CTCMSA + 22833U, // CVT_D32_S + 23896U, // CVT_D32_W + 23896U, // CVT_D32_W_MM + 22087U, // CVT_D64_L + 22833U, // CVT_D64_S + 23896U, // CVT_D64_W + 22833U, // CVT_D_S_MM + 19024U, // CVT_L_D64 + 19024U, // CVT_L_D64_MM + 23052U, // CVT_L_S + 23052U, // CVT_L_S_MM + 19362U, // CVT_S_D32 + 19362U, // CVT_S_D32_MM + 19362U, // CVT_S_D64 + 22096U, // CVT_S_L + 24651U, // CVT_S_W + 24651U, // CVT_S_W_MM + 20200U, // CVT_W_D32 + 20200U, // CVT_W_D64 + 20200U, // CVT_W_MM + 23374U, // CVT_W_S + 23374U, // CVT_W_S_MM + 19183U, // C_EQ_D32 + 19183U, // C_EQ_D64 + 23128U, // C_EQ_S + 18754U, // C_F_D32 + 18754U, // C_F_D64 + 22940U, // C_F_S + 18597U, // C_LE_D32 + 18597U, // C_LE_D64 + 22860U, // C_LE_S + 19674U, // C_LT_D32 + 19674U, // C_LT_D64 + 23223U, // C_LT_S + 18588U, // C_NGE_D32 + 18588U, // C_NGE_D64 + 22851U, // C_NGE_S + 18623U, // C_NGLE_D32 + 18623U, // C_NGLE_D64 + 22878U, // C_NGLE_S + 19040U, // C_NGL_D32 + 19040U, // C_NGL_D64 + 23068U, // C_NGL_S + 19665U, // C_NGT_D32 + 19665U, // C_NGT_D64 + 23214U, // C_NGT_S + 18633U, // C_OLE_D32 + 18633U, // C_OLE_D64 + 22888U, // C_OLE_S + 19700U, // C_OLT_D32 + 19700U, // C_OLT_D64 + 23241U, // C_OLT_S + 19209U, // C_SEQ_D32 + 19209U, // C_SEQ_D64 + 23146U, // C_SEQ_S + 18824U, // C_SF_D32 + 18824U, // C_SF_D64 + 22986U, // C_SF_S + 19237U, // C_UEQ_D32 + 19237U, // C_UEQ_D64 + 23166U, // C_UEQ_S + 18661U, // C_ULE_D32 + 18661U, // C_ULE_D64 + 22908U, // C_ULE_S + 19728U, // C_ULT_D32 + 19728U, // C_ULT_D64 + 23261U, // C_ULT_S + 19122U, // C_UN_D32 + 19122U, // C_UN_D64 + 23091U, // C_UN_S + 22516U, // CmpRxRy16 + 939546120U, // CmpiRxImm16 + 22024U, // CmpiRxImmX16 + 549945U, // Constant32 + 134237991U, // DADD + 134239684U, // DADDi + 134241306U, // DADDiu + 134241267U, // DADDu + 8689123U, // DAHI + 134240165U, // DALIGN + 8689184U, // DATI + 134239794U, // DAUI + 22476U, // DBITSWAP + 22451U, // DCLO + 22451U, // DCLO_R6 + 25533U, // DCLZ + 25533U, // DCLZ_R6 + 134241469U, // DDIV + 134241377U, // DDIVU + 9480U, // DERET + 9480U, // DERET_MM + 134243425U, // DEXT + 134243400U, // DEXTM + 134243438U, // DEXTU + 546247U, // DI + 134243413U, // DINS + 134243393U, // DINSM + 134243431U, // DINSU + 134241470U, // DIV + 134241378U, // DIVU + 134235238U, // DIV_S_B + 134237331U, // DIV_S_D + 134238735U, // DIV_S_H + 134242670U, // DIV_S_W + 134235453U, // DIV_U_B + 134237798U, // DIV_U_D + 134239013U, // DIV_U_H + 134243088U, // DIV_U_W + 546247U, // DI_MM + 134234690U, // DLSA + 134234690U, // DLSA_R6 + 134234121U, // DMFC0 + 16450U, // DMFC1 + 134234372U, // DMFC2 + 134238036U, // DMOD + 134241281U, // DMODU + 134234128U, // DMTC0 + 1867869U, // DMTC1 + 134234379U, // DMTC2 + 134239671U, // DMUH + 134241299U, // DMUHU + 134240103U, // DMUL + 23495U, // DMULT + 23641U, // DMULTu + 134241343U, // DMULU + 134240103U, // DMUL_R6 + 134237239U, // DOTP_S_D + 134238655U, // DOTP_S_H + 134242538U, // DOTP_S_W + 134237706U, // DOTP_U_D + 134238943U, // DOTP_U_H + 134242996U, // DOTP_U_W + 151014368U, // DPADD_S_D + 151015784U, // DPADD_S_H + 151019657U, // DPADD_S_W + 151014835U, // DPADD_U_D + 151016072U, // DPADD_U_H + 151020125U, // DPADD_U_W + 134239524U, // DPAQX_SA_W_PH + 134239607U, // DPAQX_S_W_PH + 134241998U, // DPAQ_SA_L_W + 134239566U, // DPAQ_S_W_PH + 134239859U, // DPAU_H_QBL + 134240355U, // DPAU_H_QBR + 134239645U, // DPAX_W_PH + 134239514U, // DPA_W_PH + 22521U, // DPOP + 134239539U, // DPSQX_SA_W_PH + 134239621U, // DPSQX_S_W_PH + 134242011U, // DPSQ_SA_L_W + 134239594U, // DPSQ_S_W_PH + 151014335U, // DPSUB_S_D + 151015763U, // DPSUB_S_H + 151019624U, // DPSUB_S_W + 151014802U, // DPSUB_U_D + 151016051U, // DPSUB_U_H + 151020092U, // DPSUB_U_W + 134239871U, // DPSU_H_QBL + 134240367U, // DPSU_H_QBR + 134239656U, // DPSX_W_PH + 134239635U, // DPS_W_PH + 134240512U, // DROTR + 134234351U, // DROTR32 + 134241513U, // DROTRV + 21370U, // DSBH + 25610U, // DSDIV + 20275U, // DSHD + 134240057U, // DSLL + 134234321U, // DSLL32 + 1073764153U, // DSLL64_32 + 134241475U, // DSLLV + 134234684U, // DSRA + 134234303U, // DSRA32 + 134241454U, // DSRAV + 134240069U, // DSRL + 134234329U, // DSRL32 + 134241482U, // DSRLV + 134235901U, // DSUB + 134241246U, // DSUBu + 25596U, // DUDIV + 25611U, // DivRxRy16 + 25597U, // DivuRxRy16 + 9438U, // EHB + 9438U, // EHB_MM + 546259U, // EI + 546259U, // EI_MM + 9481U, // ERET + 9481U, // ERET_MM + 134243426U, // EXT + 134240324U, // EXTP + 134240221U, // EXTPDP + 134241497U, // EXTPDPV + 134241506U, // EXTPV + 134242731U, // EXTRV_RS_W + 134242285U, // EXTRV_R_W + 134238744U, // EXTRV_S_H + 134243168U, // EXTRV_W + 134242720U, // EXTR_RS_W + 134242264U, // EXTR_R_W + 134238675U, // EXTR_S_H + 134242363U, // EXTR_W + 134243419U, // EXTS + 134243371U, // EXTS32 + 134243426U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 19631U, // FABS_D32 + 19631U, // FABS_D64 + 19631U, // FABS_MM + 23198U, // FABS_S + 23198U, // FABS_S_MM + 0U, // FABS_W + 134236265U, // FADD_D + 134236266U, // FADD_D32 + 134236266U, // FADD_D64 + 134236266U, // FADD_MM + 134240572U, // FADD_S + 134240572U, // FADD_S_MM + 134241633U, // FADD_W + 134236499U, // FCAF_D + 134241752U, // FCAF_W + 134236929U, // FCEQ_D + 134242191U, // FCEQ_W + 19638U, // FCLASS_D + 25015U, // FCLASS_W + 134236343U, // FCLE_D + 134241675U, // FCLE_W + 134237420U, // FCLT_D + 134242770U, // FCLT_W + 2204821U, // FCMP_D32 + 2204821U, // FCMP_D32_MM + 2204821U, // FCMP_D64 + 2466965U, // FCMP_S32 + 2466965U, // FCMP_S32_MM + 134236439U, // FCNE_D + 134241709U, // FCNE_W + 134237039U, // FCOR_D + 134242320U, // FCOR_W + 134236985U, // FCUEQ_D + 134242207U, // FCUEQ_W + 134236409U, // FCULE_D + 134241691U, // FCULE_W + 134237476U, // FCULT_D + 134242786U, // FCULT_W + 134236455U, // FCUNE_D + 134241725U, // FCUNE_W + 134236868U, // FCUN_D + 134242097U, // FCUN_W + 134237862U, // FDIV_D + 134237863U, // FDIV_D32 + 134237863U, // FDIV_D64 + 134237863U, // FDIV_MM + 134241045U, // FDIV_S + 134241045U, // FDIV_S_MM + 134243152U, // FDIV_W + 134238402U, // FEXDO_H + 134242113U, // FEXDO_W + 134236152U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 134241536U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 19064U, // FEXUPL_D + 24311U, // FEXUPL_W + 19327U, // FEXUPR_D + 24608U, // FEXUPR_W + 19569U, // FFINT_S_D + 24908U, // FFINT_S_W + 20048U, // FFINT_U_D + 25338U, // FFINT_U_W + 19074U, // FFQL_D + 24321U, // FFQL_W + 19337U, // FFQR_D + 24618U, // FFQR_W + 17277U, // FILL_B + 19049U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 20635U, // FILL_H + 24296U, // FILL_W + 18415U, // FLOG2_D + 23799U, // FLOG2_W + 19013U, // FLOOR_L_D64 + 23041U, // FLOOR_L_S + 20189U, // FLOOR_W_D32 + 20189U, // FLOOR_W_D64 + 20189U, // FLOOR_W_MM + 23363U, // FLOOR_W_S + 23363U, // FLOOR_W_S_MM + 151013489U, // FMADD_D + 151018857U, // FMADD_W + 134236190U, // FMAX_A_D + 134241574U, // FMAX_A_W + 134237937U, // FMAX_D + 134243177U, // FMAX_W + 134236170U, // FMIN_A_D + 134241554U, // FMIN_A_W + 134236842U, // FMIN_D + 134242089U, // FMIN_W + 20150U, // FMOV_D32 + 20150U, // FMOV_D32_MM + 20150U, // FMOV_D64 + 23324U, // FMOV_S + 23324U, // FMOV_S_MM + 151013447U, // FMSUB_D + 151018815U, // FMSUB_W + 134236826U, // FMUL_D + 134236827U, // FMUL_D32 + 134236827U, // FMUL_D64 + 134236827U, // FMUL_MM + 134240805U, // FMUL_S + 134240805U, // FMUL_S_MM + 134242073U, // FMUL_W + 18841U, // FNEG_D32 + 18841U, // FNEG_D64 + 18841U, // FNEG_MM + 23002U, // FNEG_S + 23002U, // FNEG_S_MM + 19175U, // FRCP_D + 24394U, // FRCP_W + 19786U, // FRINT_D + 25084U, // FRINT_W + 19814U, // FRSQRT_D + 25112U, // FRSQRT_W + 134236518U, // FSAF_D + 134241760U, // FSAF_W + 134236957U, // FSEQ_D + 134242199U, // FSEQ_W + 134236381U, // FSLE_D + 134241683U, // FSLE_W + 134237448U, // FSLT_D + 134242778U, // FSLT_W + 134236447U, // FSNE_D + 134241717U, // FSNE_W + 134237047U, // FSOR_D + 134242328U, // FSOR_W + 19805U, // FSQRT_D + 19806U, // FSQRT_D32 + 19806U, // FSQRT_D64 + 19806U, // FSQRT_MM + 23301U, // FSQRT_S + 23301U, // FSQRT_S_MM + 25103U, // FSQRT_W + 134236223U, // FSUB_D + 134236224U, // FSUB_D32 + 134236224U, // FSUB_D64 + 134236224U, // FSUB_MM + 134240554U, // FSUB_S + 134240554U, // FSUB_S_MM + 134241591U, // FSUB_W + 134237006U, // FSUEQ_D + 134242216U, // FSUEQ_W + 134236430U, // FSULE_D + 134241700U, // FSULE_W + 134237497U, // FSULT_D + 134242795U, // FSULT_W + 134236464U, // FSUNE_D + 134241734U, // FSUNE_W + 134236887U, // FSUN_D + 134242105U, // FSUN_W + 19580U, // FTINT_S_D + 24919U, // FTINT_S_W + 20059U, // FTINT_U_D + 25349U, // FTINT_U_W + 134238479U, // FTQ_H + 134242225U, // FTQ_W + 19402U, // FTRUNC_S_D + 24691U, // FTRUNC_S_W + 19869U, // FTRUNC_U_D + 25159U, // FTRUNC_U_W + 1224758783U, // GotPrologue16 + 134237142U, // HADD_S_D + 134238558U, // HADD_S_H + 134242431U, // HADD_S_W + 134237609U, // HADD_U_D + 134238846U, // HADD_U_H + 134242899U, // HADD_U_W + 134237109U, // HSUB_S_D + 134238537U, // HSUB_S_H + 134242398U, // HSUB_S_W + 134237576U, // HSUB_U_D + 134238825U, // HSUB_U_H + 134242866U, // HSUB_U_W + 134235508U, // ILVEV_B + 134237853U, // ILVEV_D + 134239068U, // ILVEV_H + 134243143U, // ILVEV_W + 134235036U, // ILVL_B + 134236834U, // ILVL_D + 134238394U, // ILVL_H + 134242081U, // ILVL_W + 134234788U, // ILVOD_B + 134236307U, // ILVOD_D + 134238196U, // ILVOD_H + 134241666U, // ILVOD_W + 134235084U, // ILVR_B + 134237082U, // ILVR_D + 134238519U, // ILVR_H + 134242371U, // ILVR_W + 134243408U, // INS + 44582043U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 44584275U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 44585551U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 44589573U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 16801009U, // INSV + 52970157U, // INSVE_B + 52971833U, // INSVE_D + 52973565U, // INSVE_H + 52977103U, // INSVE_W + 134243408U, // INS_MM + 546365U, // J + 546398U, // JAL + 22768U, // JALR + 547056U, // JALR16_MM + 22768U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 541104U, // JALRS16_MM + 23442U, // JALRS_MM + 17822U, // JALR_HB + 22768U, // JALR_MM + 547706U, // JALS_MM + 549771U, // JALX + 549771U, // JALX_MM + 546398U, // JAL_MM + 18212U, // JIALC + 18201U, // JIC + 547052U, // JR + 541091U, // JR16_MM + 547052U, // JR64 + 546873U, // JRADDIUSP + 542610U, // JRC16_MM + 542103U, // JR_HB + 542103U, // JR_HB_R6 + 547052U, // JR_MM + 546365U, // J_MM + 2905694U, // Jal16 + 3167838U, // JalB16 + 546398U, // JalOneReg + 22110U, // JalTwoReg + 9430U, // JrRa16 + 9421U, // JrcRa16 + 549872U, // JrcRx16 + 540673U, // JumpLinkReg16 + 58738087U, // LB + 58738087U, // LB64 + 58737088U, // LBU16_MM + 1358979985U, // LBUX + 58738087U, // LB_MM + 58743769U, // LBu + 58743769U, // LBu64 + 58743769U, // LBu_MM + 58740538U, // LD + 58736688U, // LDC1 + 58736688U, // LDC164 + 58736688U, // LDC1_MM + 58736888U, // LDC2 + 58736888U, // LDC2_R6 + 58736947U, // LDC3 + 17103U, // LDI_B + 18857U, // LDI_D + 20511U, // LDI_H + 24146U, // LDI_W + 58742458U, // LDL + 18273U, // LDPC + 58742954U, // LDR + 1358970992U, // LDXC1 + 1358970992U, // LDXC164 + 58737301U, // LD_B + 58738820U, // LD_D + 58740709U, // LD_H + 58744179U, // LD_W + 25189403U, // LEA_ADDiu + 25189402U, // LEA_ADDiu64 + 25189403U, // LEA_ADDiu_MM + 58741643U, // LH + 58741643U, // LH64 + 58737111U, // LHU16_MM + 1358979974U, // LHX + 58741643U, // LH_MM + 58743822U, // LHu + 58743822U, // LHu64 + 58743822U, // LHu_MM + 16751U, // LI16_MM + 58742563U, // LL + 58740537U, // LLD + 58740537U, // LLD_R6 + 58742563U, // LL_MM + 58742563U, // LL_R6 + 58736647U, // LOAD_ACC128 + 58736647U, // LOAD_ACC64 + 58736647U, // LOAD_ACC64DSP + 58742794U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 134234691U, // LSA + 134234691U, // LSA_R6 + 1358971006U, // LUXC1 + 1358971006U, // LUXC164 + 1358971006U, // LUXC1_MM + 33576504U, // LUi + 33576504U, // LUi64 + 33576504U, // LUi_MM + 58745726U, // LW + 58737118U, // LW16_MM + 58745726U, // LW64 + 58736740U, // LWC1 + 58736740U, // LWC1_MM + 58736914U, // LWC2 + 58736914U, // LWC2_R6 + 58736959U, // LWC3 + 58745726U, // LWGP_MM + 58742637U, // LWL + 58742637U, // LWL64 + 58742637U, // LWL_MM + 3522956U, // LWM16_MM + 3522785U, // LWM32_MM + 3528595U, // LWM_MM + 18310U, // LWPC + 137290U, // LWP_MM + 58743054U, // LWR + 58743054U, // LWR64 + 58743054U, // LWR_MM + 58745726U, // LWSP_MM + 18303U, // LWUPC + 58743912U, // LWU_MM + 1358979991U, // LWX + 1358971020U, // LWXC1 + 1358971020U, // LWXC1_MM + 1358977945U, // LWXS_MM + 58745726U, // LW_MM + 58743912U, // LWu + 58738087U, // LbRxRyOffMemX16 + 58743769U, // LbuRxRyOffMemX16 + 58741643U, // LhRxRyOffMemX16 + 58743822U, // LhuRxRyOffMemX16 + 939546111U, // LiRxImm16 + 22005U, // LiRxImmAlignX16 + 22015U, // LiRxImmX16 + 33571334U, // LoadAddr32Imm + 58737158U, // LoadAddr32Reg + 33576447U, // LoadImm32Reg + 22019U, // LoadImm64Reg + 3695486U, // LwConstant32 + 268460926U, // LwRxPcTcp16 + 25470U, // LwRxPcTcpX16 + 58745726U, // LwRxRyOffMemX16 + 1493197694U, // LwRxSpImmX16 + 20269U, // MADD + 151013751U, // MADDF_D + 151017921U, // MADDF_S + 151015667U, // MADDR_Q_H + 151019386U, // MADDR_Q_W + 23546U, // MADDU + 134241274U, // MADDU_DSP + 23546U, // MADDU_MM + 151012706U, // MADDV_B + 151015051U, // MADDV_D + 151016266U, // MADDV_H + 151020341U, // MADDV_W + 134236274U, // MADD_D32 + 134236274U, // MADD_D32_MM + 134236274U, // MADD_D64 + 134237997U, // MADD_DSP + 20269U, // MADD_MM + 151015637U, // MADD_Q_H + 151019356U, // MADD_Q_W + 134240571U, // MADD_S + 134240571U, // MADD_S_MM + 134239974U, // MAQ_SA_W_PHL + 134240436U, // MAQ_SA_W_PHR + 134240002U, // MAQ_S_W_PHL + 134240464U, // MAQ_S_W_PHR + 134236215U, // MAXA_D + 134240544U, // MAXA_S + 134235159U, // MAXI_S_B + 134237220U, // MAXI_S_D + 134238636U, // MAXI_S_H + 134242509U, // MAXI_S_W + 2281719022U, // MAXI_U_B + 2281721335U, // MAXI_U_D + 2281722572U, // MAXI_U_H + 2281726625U, // MAXI_U_W + 134234740U, // MAX_A_B + 134236191U, // MAX_A_D + 134238148U, // MAX_A_H + 134241575U, // MAX_A_W + 134237938U, // MAX_D + 134241111U, // MAX_S + 134235247U, // MAX_S_B + 134237340U, // MAX_S_D + 134238755U, // MAX_S_H + 134242690U, // MAX_S_W + 134235462U, // MAX_U_B + 134237807U, // MAX_U_D + 134239022U, // MAX_U_H + 134243097U, // MAX_U_W + 134234122U, // MFC0 + 16451U, // MFC1 + 16451U, // MFC1_MM + 134234373U, // MFC2 + 16457U, // MFHC1_D32 + 16457U, // MFHC1_D64 + 16457U, // MFHC1_MM + 546281U, // MFHI + 546281U, // MFHI16_MM + 546281U, // MFHI64 + 21993U, // MFHI_DSP + 546281U, // MFHI_MM + 546745U, // MFLO + 546745U, // MFLO16_MM + 546745U, // MFLO64 + 22457U, // MFLO_DSP + 546745U, // MFLO_MM + 134236200U, // MINA_D + 134240536U, // MINA_S + 134235139U, // MINI_S_B + 134237200U, // MINI_S_D + 134238616U, // MINI_S_H + 134242489U, // MINI_S_W + 2281719002U, // MINI_U_B + 2281721315U, // MINI_U_D + 2281722552U, // MINI_U_H + 2281726605U, // MINI_U_W + 134234721U, // MIN_A_B + 134236171U, // MIN_A_D + 134238129U, // MIN_A_H + 134241555U, // MIN_A_W + 134236843U, // MIN_D + 134240812U, // MIN_S + 134235169U, // MIN_S_B + 134237230U, // MIN_S_D + 134238646U, // MIN_S_H + 134242529U, // MIN_S_W + 134235384U, // MIN_U_B + 134237697U, // MIN_U_D + 134238934U, // MIN_U_H + 134242987U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 134238037U, // MOD + 134235899U, // MODSUB + 134241282U, // MODU + 134235102U, // MOD_S_B + 134237163U, // MOD_S_D + 134238579U, // MOD_S_H + 134242452U, // MOD_S_W + 134235317U, // MOD_U_B + 134237630U, // MOD_U_D + 134238867U, // MOD_U_H + 134242920U, // MOD_U_W + 20345U, // MOVE16_MM + 67491813U, // MOVEP_MM + 23668U, // MOVE_V + 134236560U, // MOVF_D32 + 134236560U, // MOVF_D32_MM + 134236560U, // MOVF_D64 + 134238109U, // MOVF_I + 134238109U, // MOVF_I64 + 134238109U, // MOVF_I_MM + 134240722U, // MOVF_S + 134240722U, // MOVF_S_MM + 134236895U, // MOVN_I64_D64 + 134240173U, // MOVN_I64_I + 134240173U, // MOVN_I64_I64 + 134240848U, // MOVN_I64_S + 134236895U, // MOVN_I_D32 + 134236895U, // MOVN_I_D32_MM + 134236895U, // MOVN_I_D64 + 134240173U, // MOVN_I_I + 134240173U, // MOVN_I_I64 + 134240173U, // MOVN_I_MM + 134240848U, // MOVN_I_S + 134240848U, // MOVN_I_S_MM + 134237558U, // MOVT_D32 + 134237558U, // MOVT_D32_MM + 134237558U, // MOVT_D64 + 134241235U, // MOVT_I + 134241235U, // MOVT_I64 + 134241235U, // MOVT_I_MM + 134241037U, // MOVT_S + 134241037U, // MOVT_S_MM + 134237978U, // MOVZ_I64_D64 + 134243300U, // MOVZ_I64_I + 134243300U, // MOVZ_I64_I64 + 134241138U, // MOVZ_I64_S + 134237978U, // MOVZ_I_D32 + 134237978U, // MOVZ_I_D32_MM + 134237978U, // MOVZ_I_D64 + 134243300U, // MOVZ_I_I + 134243300U, // MOVZ_I_I64 + 134243300U, // MOVZ_I_MM + 134241138U, // MOVZ_I_S + 134241138U, // MOVZ_I_S_MM + 18179U, // MSUB + 151013742U, // MSUBF_D + 151017912U, // MSUBF_S + 151015656U, // MSUBR_Q_H + 151019375U, // MSUBR_Q_W + 23525U, // MSUBU + 134241253U, // MSUBU_DSP + 23525U, // MSUBU_MM + 151012697U, // MSUBV_B + 151015042U, // MSUBV_D + 151016257U, // MSUBV_H + 151020332U, // MSUBV_W + 134236232U, // MSUB_D32 + 134236232U, // MSUB_D32_MM + 134236232U, // MSUB_D64 + 134235907U, // MSUB_DSP + 18179U, // MSUB_MM + 151015627U, // MSUB_Q_H + 151019346U, // MSUB_Q_W + 134240553U, // MSUB_S + 134240553U, // MSUB_S_MM + 134234129U, // MTC0 + 1867870U, // MTC1 + 1867870U, // MTC1_MM + 134234380U, // MTC2 + 1884240U, // MTHC1_D32 + 1884240U, // MTHC1_D64 + 1884240U, // MTHC1_MM + 546287U, // MTHI + 546287U, // MTHI64 + 1873391U, // MTHI_DSP + 546287U, // MTHI_MM + 1873900U, // MTHLIP + 546758U, // MTLO + 546758U, // MTLO64 + 1873862U, // MTLO_DSP + 546758U, // MTLO_MM + 540701U, // MTM0 + 540826U, // MTM1 + 540958U, // MTM2 + 540707U, // MTP0 + 540832U, // MTP1 + 540964U, // MTP2 + 134239672U, // MUH + 134241300U, // MUHU + 134240104U, // MUL + 134240015U, // MULEQ_S_W_PHL + 134240477U, // MULEQ_S_W_PHR + 134239883U, // MULEU_S_PH_QBL + 134240379U, // MULEU_S_PH_QBR + 134239433U, // MULQ_RS_PH + 134242709U, // MULQ_RS_W + 134239377U, // MULQ_S_PH + 134242568U, // MULQ_S_W + 134238462U, // MULR_Q_H + 134242181U, // MULR_Q_W + 134239579U, // MULSAQ_S_W_PH + 134239554U, // MULSA_W_PH + 23496U, // MULT + 134241370U, // MULTU_DSP + 134241224U, // MULT_DSP + 23496U, // MULT_MM + 23642U, // MULTu + 23642U, // MULTu_MM + 134241337U, // MULU + 134235517U, // MULV_B + 134237870U, // MULV_D + 134239077U, // MULV_H + 134243160U, // MULV_W + 134240104U, // MUL_MM + 134239250U, // MUL_PH + 134238431U, // MUL_Q_H + 134242150U, // MUL_Q_W + 134240104U, // MUL_R6 + 134239345U, // MUL_S_PH + 546281U, // Mfhi16 + 546745U, // Mflo16 + 20345U, // Move32R16 + 20345U, // MoveR3216 + 23496U, // MultRxRy16 + 75799496U, // MultRxRyRz16 + 23642U, // MultuRxRy16 + 75799642U, // MultuRxRyRz16 + 17028U, // NLOC_B + 18521U, // NLOC_D + 20436U, // NLOC_H + 23880U, // NLOC_W + 17036U, // NLZC_B + 18529U, // NLZC_D + 20444U, // NLZC_H + 23888U, // NLZC_W + 134236282U, // NMADD_D32 + 134236282U, // NMADD_D32_MM + 134236282U, // NMADD_D64 + 134240570U, // NMADD_S + 134240570U, // NMADD_S_MM + 134236240U, // NMSUB_D32 + 134236240U, // NMSUB_D32_MM + 134236240U, // NMSUB_D64 + 134240552U, // NMSUB_S + 134240552U, // NMSUB_S_MM + 0U, // NOP + 134240502U, // NOR + 134240502U, // NOR64 + 2281718573U, // NORI_B + 134240502U, // NOR_MM + 134241412U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 16825U, // NOT16_MM + 20387U, // NegRxRy16 + 23502U, // NotRxRy16 + 134240503U, // OR + 836010U, // OR16_MM + 134240503U, // OR64 + 2281718574U, // ORI_B + 134240503U, // OR_MM + 134241413U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 134239771U, // ORi + 134239771U, // ORi64 + 134239771U, // ORi_MM + 16799991U, // OrRxRxRy16 + 134239239U, // PACKRL_PH + 9442U, // PAUSE + 9442U, // PAUSE_MM + 134235499U, // PCKEV_B + 134237844U, // PCKEV_D + 134239059U, // PCKEV_H + 134243134U, // PCKEV_W + 134234779U, // PCKOD_B + 134236298U, // PCKOD_D + 134238187U, // PCKOD_H + 134241657U, // PCKOD_W + 17555U, // PCNT_B + 19778U, // PCNT_D + 21063U, // PCNT_H + 25076U, // PCNT_W + 134239203U, // PICK_PH + 134235631U, // PICK_QB + 22522U, // POP + 22186U, // PRECEQU_PH_QBL + 16906U, // PRECEQU_PH_QBLA + 22682U, // PRECEQU_PH_QBR + 16939U, // PRECEQU_PH_QBRA + 22260U, // PRECEQ_W_PHL + 22722U, // PRECEQ_W_PHR + 22171U, // PRECEU_PH_QBL + 16890U, // PRECEU_PH_QBLA + 22667U, // PRECEU_PH_QBR + 16923U, // PRECEU_PH_QBRA + 134239155U, // PRECRQU_S_QB_PH + 134241800U, // PRECRQ_PH_W + 134239128U, // PRECRQ_QB_PH + 134241831U, // PRECRQ_RS_PH_W + 134239142U, // PRECR_QB_PH + 134241784U, // PRECR_SRA_PH_W + 134241813U, // PRECR_SRA_R_PH_W + 85911U, // PREF + 85911U, // PREF_MM + 85911U, // PREF_R6 + 134238019U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 16391U, // PseudoCVT_D32_W + 16391U, // PseudoCVT_D64_L + 16391U, // PseudoCVT_D64_W + 16391U, // PseudoCVT_S_L + 16391U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 18155U, // RADDU_W_QB + 33577003U, // RDDSP + 22791U, // RDHWR + 22791U, // RDHWR64 + 22791U, // RDHWR_MM + 21766U, // REPLV_PH + 18135U, // REPLV_QB + 33575925U, // REPL_PH + 33572353U, // REPL_QB + 19787U, // RINT_D + 23293U, // RINT_S + 134240513U, // ROTR + 134241514U, // ROTRV + 134241514U, // ROTRV_MM + 134240513U, // ROTR_MM + 18992U, // ROUND_L_D64 + 23020U, // ROUND_L_S + 20168U, // ROUND_W_D32 + 20168U, // ROUND_W_D64 + 20168U, // ROUND_W_MM + 23342U, // ROUND_W_S + 23342U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 134235208U, // SAT_S_B + 134237279U, // SAT_S_D + 2281722353U, // SAT_S_H + 134242618U, // SAT_S_W + 134235435U, // SAT_U_B + 134237758U, // SAT_U_D + 2281722643U, // SAT_U_H + 134243048U, // SAT_U_W + 58738423U, // SB + 58736980U, // SB16_MM + 58738423U, // SB64 + 58738423U, // SB_MM + 3966874U, // SC + 3968802U, // SCD + 3968802U, // SCD_R6 + 3966874U, // SC_MM + 3966874U, // SC_R6 + 58740570U, // SD + 546774U, // SDBBP + 65946U, // SDBBP16_MM + 546774U, // SDBBP_MM + 546774U, // SDBBP_R6 + 58736694U, // SDC1 + 58736694U, // SDC164 + 58736694U, // SDC1_MM + 58736894U, // SDC2 + 58736894U, // SDC2_R6 + 58736953U, // SDC3 + 25611U, // SDIV + 25611U, // SDIV_MM + 58742463U, // SDL + 58742959U, // SDR + 1358970999U, // SDXC1 + 1358970999U, // SDXC164 + 17810U, // SEB + 17810U, // SEB64 + 17810U, // SEB_MM + 21382U, // SEH + 21382U, // SEH64 + 21382U, // SEH_MM + 134243273U, // SELEQZ + 134243273U, // SELEQZ64 + 134237968U, // SELEQZ_D + 134241128U, // SELEQZ_S + 134243246U, // SELNEZ + 134243246U, // SELNEZ64 + 134237951U, // SELNEZ_D + 134241118U, // SELNEZ_S + 151013977U, // SEL_D + 151018005U, // SEL_S + 134240345U, // SEQ + 134239758U, // SEQi + 58742195U, // SH + 58736993U, // SH16_MM + 58742195U, // SH64 + 2281718455U, // SHF_B + 2281721863U, // SHF_H + 2281725417U, // SHF_W + 22463U, // SHILO + 23761U, // SHILOV + 134239484U, // SHLLV_PH + 134235853U, // SHLLV_QB + 134239421U, // SHLLV_S_PH + 134242679U, // SHLLV_S_W + 134239212U, // SHLL_PH + 134235640U, // SHLL_QB + 134239334U, // SHLL_S_PH + 134242519U, // SHLL_S_W + 134239474U, // SHRAV_PH + 134235843U, // SHRAV_QB + 134239322U, // SHRAV_R_PH + 134235741U, // SHRAV_R_QB + 134242274U, // SHRAV_R_W + 134239119U, // SHRA_PH + 134235563U, // SHRA_QB + 134239287U, // SHRA_R_PH + 134235706U, // SHRA_R_QB + 134242232U, // SHRA_R_W + 134239504U, // SHRLV_PH + 134235873U, // SHRLV_QB + 134239230U, // SHRL_PH + 134235658U, // SHRL_QB + 58742195U, // SH_MM + 2969584334U, // SLDI_B + 2969586088U, // SLDI_D + 2969587742U, // SLDI_H + 2969591377U, // SLDI_W + 822100628U, // SLD_B + 822102147U, // SLD_D + 822104036U, // SLD_H + 822107506U, // SLD_W + 134240058U, // SLL + 134234494U, // SLL16_MM + 1610635066U, // SLL64_32 + 1610635066U, // SLL64_64 + 2281718512U, // SLLI_B + 2281720249U, // SLLI_D + 2281721903U, // SLLI_H + 2281725538U, // SLLI_W + 134241476U, // SLLV + 134241476U, // SLLV_MM + 134235013U, // SLL_B + 134236785U, // SLL_D + 134238371U, // SLL_H + 134240058U, // SLL_MM + 134242032U, // SLL_W + 134241213U, // SLT + 134241213U, // SLT64 + 134241213U, // SLT_MM + 134239782U, // SLTi + 134239782U, // SLTi64 + 134239782U, // SLTi_MM + 134241321U, // SLTiu + 134241321U, // SLTiu64 + 134241321U, // SLTiu_MM + 134241357U, // SLTu + 134241357U, // SLTu64 + 134241357U, // SLTu_MM + 134238063U, // SNE + 134239703U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 2952807239U, // SPLATI_B + 2952808960U, // SPLATI_D + 2952810614U, // SPLATI_H + 2952814249U, // SPLATI_W + 805323906U, // SPLAT_B + 805326016U, // SPLAT_D + 805327414U, // SPLAT_H + 805331393U, // SPLAT_W + 134234685U, // SRA + 2281718470U, // SRAI_B + 2281720224U, // SRAI_D + 2281721878U, // SRAI_H + 2281725513U, // SRAI_W + 134234898U, // SRARI_B + 134236635U, // SRARI_D + 2281721937U, // SRARI_H + 134241924U, // SRARI_W + 134235051U, // SRAR_B + 134237015U, // SRAR_D + 134238486U, // SRAR_H + 134242296U, // SRAR_W + 134241455U, // SRAV + 134241455U, // SRAV_MM + 134234749U, // SRA_B + 134236208U, // SRA_D + 134238157U, // SRA_H + 134234685U, // SRA_MM + 134241584U, // SRA_W + 134240070U, // SRL + 134234501U, // SRL16_MM + 2281718520U, // SRLI_B + 2281720257U, // SRLI_D + 2281721911U, // SRLI_H + 2281725546U, // SRLI_W + 134234916U, // SRLRI_B + 134236653U, // SRLRI_D + 2281721955U, // SRLRI_H + 134241942U, // SRLRI_W + 134235067U, // SRLR_B + 134237031U, // SRLR_D + 134238502U, // SRLR_H + 134242312U, // SRLR_W + 134241483U, // SRLV + 134241483U, // SRLV_MM + 134235020U, // SRL_B + 134236810U, // SRL_D + 134238378U, // SRL_H + 134240070U, // SRL_MM + 134242057U, // SRL_W + 9463U, // SSNOP + 9463U, // SSNOP_MM + 58736647U, // STORE_ACC128 + 58736647U, // STORE_ACC64 + 58736647U, // STORE_ACC64DSP + 58742810U, // STORE_CCOND_DSP + 58737829U, // ST_B + 58740080U, // ST_D + 58741337U, // ST_H + 58745378U, // ST_W + 134235902U, // SUB + 134239183U, // SUBQH_PH + 134239298U, // SUBQH_R_PH + 134242242U, // SUBQH_R_W + 134241847U, // SUBQH_W + 134239258U, // SUBQ_PH + 134239355U, // SUBQ_S_PH + 134242548U, // SUBQ_S_W + 134235423U, // SUBSUS_U_B + 134237746U, // SUBSUS_U_D + 134238983U, // SUBSUS_U_H + 134243036U, // SUBSUS_U_W + 134235226U, // SUBSUU_S_B + 134237319U, // SUBSUU_S_D + 134238723U, // SUBSUU_S_H + 134242658U, // SUBSUU_S_W + 134235188U, // SUBS_S_B + 134237259U, // SUBS_S_D + 134238685U, // SUBS_S_H + 134242598U, // SUBS_S_W + 134235403U, // SUBS_U_B + 134237726U, // SUBS_U_D + 134238963U, // SUBS_U_H + 134243016U, // SUBS_U_W + 134234567U, // SUBU16_MM + 134235611U, // SUBUH_QB + 134235717U, // SUBUH_R_QB + 134239456U, // SUBU_PH + 134235825U, // SUBU_QB + 134239399U, // SUBU_S_PH + 134235764U, // SUBU_S_QB + 2281718618U, // SUBVI_B + 2281720339U, // SUBVI_D + 2281721993U, // SUBVI_H + 2281725628U, // SUBVI_W + 134235482U, // SUBV_B + 134237827U, // SUBV_D + 134239042U, // SUBV_H + 134243117U, // SUBV_W + 134235902U, // SUB_MM + 134241247U, // SUBu + 134241247U, // SUBu_MM + 1358971013U, // SUXC1 + 1358971013U, // SUXC164 + 1358971013U, // SUXC1_MM + 58745730U, // SW + 58737124U, // SW16_MM + 58745730U, // SW64 + 58736746U, // SWC1 + 58736746U, // SWC1_MM + 58736920U, // SWC2 + 58736920U, // SWC2_R6 + 58736965U, // SWC3 + 58742642U, // SWL + 58742642U, // SWL64 + 58742642U, // SWL_MM + 3522963U, // SWM16_MM + 3522792U, // SWM32_MM + 3528600U, // SWM_MM + 137295U, // SWP_MM + 58743059U, // SWR + 58743059U, // SWR64 + 58743059U, // SWR_MM + 58745730U, // SWSP_MM + 1358971027U, // SWXC1 + 1358971027U, // SWXC1_MM + 58745730U, // SW_MM + 549939U, // SYNC + 153021U, // SYNCI + 549939U, // SYNC_MM + 546590U, // SYSCALL + 546590U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 58738423U, // SbRxRyOffMemX16 + 549866U, // SebRx16 + 549878U, // SehRx16 + 4367299U, // SelBeqZ + 4367272U, // SelBneZ + 1828886516U, // SelTBteqZCmp + 1828886024U, // SelTBteqZCmpi + 1828887485U, // SelTBteqZSlt + 1828886054U, // SelTBteqZSlti + 1828887593U, // SelTBteqZSltiu + 1828887629U, // SelTBteqZSltu + 1963104244U, // SelTBtneZCmp + 1963103752U, // SelTBtneZCmpi + 1963105213U, // SelTBtneZSlt + 1963103782U, // SelTBtneZSlti + 1963105321U, // SelTBtneZSltiu + 1963105357U, // SelTBtneZSltu + 58742195U, // ShRxRyOffMemX16 + 134240058U, // SllX16 + 16800964U, // SllvRxRy16 + 92576701U, // SltCCRxRy16 + 23485U, // SltRxRy16 + 92575270U, // SltiCCRxImmX16 + 939546150U, // SltiRxImm16 + 22054U, // SltiRxImmX16 + 92576809U, // SltiuCCRxImmX16 + 939547689U, // SltiuRxImm16 + 23593U, // SltiuRxImmX16 + 92576845U, // SltuCCRxRy16 + 23629U, // SltuRxRy16 + 92576845U, // SltuRxRyRz16 + 134234685U, // SraX16 + 16800943U, // SravRxRy16 + 134240070U, // SrlX16 + 16800971U, // SrlvRxRy16 + 134241247U, // SubuRxRyRz16 + 58745730U, // SwRxRyOffMemX16 + 1493197698U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 134240350U, // TEQ + 33576468U, // TEQI + 33576468U, // TEQI_MM + 134240350U, // TEQ_MM + 134238046U, // TGE + 33576401U, // TGEI + 33578018U, // TGEIU + 33578018U, // TGEIU_MM + 33576401U, // TGEI_MM + 134241288U, // TGEU + 134241288U, // TGEU_MM + 134238046U, // TGE_MM + 9458U, // TLBP + 9458U, // TLBP_MM + 9469U, // TLBR + 9469U, // TLBR_MM + 9448U, // TLBWI + 9448U, // TLBWI_MM + 9474U, // TLBWR + 9474U, // TLBWR_MM + 134241218U, // TLT + 33576492U, // TLTI + 33578032U, // TLTIU_MM + 33576492U, // TLTI_MM + 134241363U, // TLTU + 134241363U, // TLTU_MM + 134241218U, // TLT_MM + 134238068U, // TNE + 33576413U, // TNEI + 33576413U, // TNEI_MM + 134238068U, // TNE_MM + 0U, // TRAP + 18981U, // TRUNC_L_D64 + 23009U, // TRUNC_L_S + 20157U, // TRUNC_W_D32 + 20157U, // TRUNC_W_D64 + 20157U, // TRUNC_W_MM + 23331U, // TRUNC_W_S + 23331U, // TRUNC_W_S_MM + 33578032U, // TTLTIU + 25597U, // UDIV + 25597U, // UDIV_MM + 134241335U, // V3MULU + 134234135U, // VMM0 + 134241350U, // VMULU + 151012022U, // VSHF_B + 151013760U, // VSHF_D + 151015430U, // VSHF_H + 151018984U, // VSHF_W + 9486U, // WAIT + 547767U, // WAIT_MM + 33577010U, // WRDSP + 21376U, // WSBH + 21376U, // WSBH_MM + 134240507U, // XOR + 836009U, // XOR16_MM + 134240507U, // XOR64 + 2281718581U, // XORI_B + 134240507U, // XOR_MM + 134241419U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 134239770U, // XORi + 134239770U, // XORi64 + 134239770U, // XORi_MM + 16799995U, // XorRxRxRy16 + 0U + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_W + 0U, // ADD + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUR1SP_MM + 0U, // ADDIUR2_MM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 0U, // ADDQH_PH + 0U, // ADDQH_R_PH + 0U, // ADDQH_R_W + 0U, // ADDQH_W + 0U, // ADDQ_PH + 0U, // ADDQ_S_PH + 0U, // ADDQ_S_W + 0U, // ADDSC + 0U, // ADDS_A_B + 0U, // ADDS_A_D + 0U, // ADDS_A_H + 0U, // ADDS_A_W + 0U, // ADDS_S_B + 0U, // ADDS_S_D + 0U, // ADDS_S_H + 0U, // ADDS_S_W + 0U, // ADDS_U_B + 0U, // ADDS_U_D + 0U, // ADDS_U_H + 0U, // ADDS_U_W + 0U, // ADDU16_MM + 0U, // ADDUH_QB + 0U, // ADDUH_R_QB + 0U, // ADDU_PH + 0U, // ADDU_QB + 0U, // ADDU_S_PH + 0U, // ADDU_S_QB + 0U, // ADDVI_B + 0U, // ADDVI_D + 0U, // ADDVI_H + 0U, // ADDVI_W + 0U, // ADDV_B + 0U, // ADDV_D + 0U, // ADDV_H + 0U, // ADDV_W + 0U, // ADDWC + 0U, // ADD_A_B + 0U, // ADD_A_D + 0U, // ADD_A_H + 0U, // ADD_A_W + 0U, // ADD_MM + 0U, // ADDi + 0U, // ADDi_MM + 0U, // ADDiu + 0U, // ADDiu_MM + 0U, // ADDu + 0U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 4U, // ALIGN + 0U, // ALUIPC + 0U, // AND + 0U, // AND16_MM + 0U, // AND64 + 0U, // ANDI16_MM + 0U, // ANDI_B + 0U, // AND_MM + 0U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 1U, // ANDi + 1U, // ANDi64 + 1U, // ANDi_MM + 1U, // APPEND + 0U, // ASUB_S_B + 0U, // ASUB_S_D + 0U, // ASUB_S_H + 0U, // ASUB_S_W + 0U, // ASUB_U_B + 0U, // ASUB_U_D + 0U, // ASUB_U_H + 0U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // AUI + 0U, // AUIPC + 0U, // AVER_S_B + 0U, // AVER_S_D + 0U, // AVER_S_H + 0U, // AVER_S_W + 0U, // AVER_U_B + 0U, // AVER_U_D + 0U, // AVER_U_H + 0U, // AVER_U_W + 0U, // AVE_S_B + 0U, // AVE_S_D + 0U, // AVE_S_H + 0U, // AVE_S_W + 0U, // AVE_U_B + 0U, // AVE_U_D + 0U, // AVE_U_H + 0U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 0U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 0U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B + 0U, // B16_MM + 0U, // BADDu + 0U, // BAL + 0U, // BALC + 1U, // BALIGN + 0U, // BAL_BR + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 0U, // BC + 0U, // BC0F + 0U, // BC0FL + 0U, // BC0T + 0U, // BC0TL + 0U, // BC1EQZ + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2F + 0U, // BC2FL + 0U, // BC2NEZ + 0U, // BC2T + 0U, // BC2TL + 0U, // BC3F + 0U, // BC3FL + 0U, // BC3T + 0U, // BC3TL + 0U, // BCLRI_B + 0U, // BCLRI_D + 0U, // BCLRI_H + 0U, // BCLRI_W + 0U, // BCLR_B + 0U, // BCLR_D + 0U, // BCLR_H + 0U, // BCLR_W + 0U, // BEQ + 0U, // BEQ64 + 0U, // BEQC + 0U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZC + 0U, // BEQZC_MM + 0U, // BEQ_MM + 0U, // BGEC + 0U, // BGEUC + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZC + 0U, // BGTZL + 0U, // BGTZ_MM + 1U, // BINSLI_B + 1U, // BINSLI_D + 1U, // BINSLI_H + 1U, // BINSLI_W + 2U, // BINSL_B + 2U, // BINSL_D + 2U, // BINSL_H + 2U, // BINSL_W + 1U, // BINSRI_B + 1U, // BINSRI_D + 1U, // BINSRI_H + 1U, // BINSRI_W + 2U, // BINSR_B + 2U, // BINSR_D + 2U, // BINSR_H + 2U, // BINSR_W + 0U, // BITREV + 0U, // BITSWAP + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZC + 0U, // BLEZL + 0U, // BLEZ_MM + 0U, // BLTC + 0U, // BLTUC + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZL + 0U, // BLTZ_MM + 1U, // BMNZI_B + 2U, // BMNZ_V + 1U, // BMZI_B + 2U, // BMZ_V + 0U, // BNE + 0U, // BNE64 + 0U, // BNEC + 0U, // BNEGI_B + 0U, // BNEGI_D + 0U, // BNEGI_H + 0U, // BNEGI_W + 0U, // BNEG_B + 0U, // BNEG_D + 0U, // BNEG_H + 0U, // BNEG_W + 0U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZC + 0U, // BNEZC_MM + 0U, // BNE_MM + 0U, // BNVC + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 0U, // BOVC + 0U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK_MM + 1U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 2U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 0U, // BSETI_B + 0U, // BSETI_D + 0U, // BSETI_H + 0U, // BSETI_W + 0U, // BSET_B + 0U, // BSET_D + 0U, // BSET_H + 0U, // BSET_W + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 0U, // B_MM_Pseudo + 0U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 0U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CACHE + 0U, // CACHE_MM + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_S + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEQI_B + 0U, // CEQI_D + 0U, // CEQI_H + 0U, // CEQI_W + 0U, // CEQ_B + 0U, // CEQ_D + 0U, // CEQ_H + 0U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFCMSA + 5U, // CINS + 5U, // CINS32 + 0U, // CLASS_D + 0U, // CLASS_S + 0U, // CLEI_S_B + 0U, // CLEI_S_D + 0U, // CLEI_S_H + 0U, // CLEI_S_W + 0U, // CLEI_U_B + 0U, // CLEI_U_D + 0U, // CLEI_U_H + 0U, // CLEI_U_W + 0U, // CLE_S_B + 0U, // CLE_S_D + 0U, // CLE_S_H + 0U, // CLE_S_W + 0U, // CLE_U_B + 0U, // CLE_U_D + 0U, // CLE_U_H + 0U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_R6 + 0U, // CLTI_S_B + 0U, // CLTI_S_D + 0U, // CLTI_S_H + 0U, // CLTI_S_W + 0U, // CLTI_U_B + 0U, // CLTI_U_D + 0U, // CLTI_U_H + 0U, // CLTI_U_W + 0U, // CLT_S_B + 0U, // CLT_S_D + 0U, // CLT_S_H + 0U, // CLT_S_W + 0U, // CLT_U_B + 0U, // CLT_U_D + 0U, // CLT_U_H + 0U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_R6 + 0U, // CMPGDU_EQ_QB + 0U, // CMPGDU_LE_QB + 0U, // CMPGDU_LT_QB + 0U, // CMPGU_EQ_QB + 0U, // CMPGU_LE_QB + 0U, // CMPGU_LT_QB + 0U, // CMPU_EQ_QB + 0U, // CMPU_LE_QB + 0U, // CMPU_LT_QB + 0U, // CMP_EQ_D + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_S + 0U, // CMP_F_D + 0U, // CMP_F_S + 0U, // CMP_LE_D + 0U, // CMP_LE_PH + 0U, // CMP_LE_S + 0U, // CMP_LT_D + 0U, // CMP_LT_PH + 0U, // CMP_LT_S + 0U, // CMP_SAF_D + 0U, // CMP_SAF_S + 0U, // CMP_SEQ_D + 0U, // CMP_SEQ_S + 0U, // CMP_SLE_D + 0U, // CMP_SLE_S + 0U, // CMP_SLT_D + 0U, // CMP_SLT_S + 0U, // CMP_SUEQ_D + 0U, // CMP_SUEQ_S + 0U, // CMP_SULE_D + 0U, // CMP_SULE_S + 0U, // CMP_SULT_D + 0U, // CMP_SULT_S + 0U, // CMP_SUN_D + 0U, // CMP_SUN_S + 0U, // CMP_UEQ_D + 0U, // CMP_UEQ_S + 0U, // CMP_ULE_D + 0U, // CMP_ULE_S + 0U, // CMP_ULT_D + 0U, // CMP_ULT_S + 0U, // CMP_UN_D + 0U, // CMP_UN_S + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 8U, // COPY_S_B + 8U, // COPY_S_D + 8U, // COPY_S_H + 8U, // COPY_S_W + 8U, // COPY_U_B + 8U, // COPY_U_D + 8U, // COPY_U_H + 8U, // COPY_U_W + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_W + 0U, // CVT_D_S_MM + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_L + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_W_D32 + 0U, // CVT_W_D64 + 0U, // CVT_W_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // C_EQ_D32 + 0U, // C_EQ_D64 + 0U, // C_EQ_S + 0U, // C_F_D32 + 0U, // C_F_D64 + 0U, // C_F_S + 0U, // C_LE_D32 + 0U, // C_LE_D64 + 0U, // C_LE_S + 0U, // C_LT_D32 + 0U, // C_LT_D64 + 0U, // C_LT_S + 0U, // C_NGE_D32 + 0U, // C_NGE_D64 + 0U, // C_NGE_S + 0U, // C_NGLE_D32 + 0U, // C_NGLE_D64 + 0U, // C_NGLE_S + 0U, // C_NGL_D32 + 0U, // C_NGL_D64 + 0U, // C_NGL_S + 0U, // C_NGT_D32 + 0U, // C_NGT_D64 + 0U, // C_NGT_S + 0U, // C_OLE_D32 + 0U, // C_OLE_D64 + 0U, // C_OLE_S + 0U, // C_OLT_D32 + 0U, // C_OLT_D64 + 0U, // C_OLT_S + 0U, // C_SEQ_D32 + 0U, // C_SEQ_D64 + 0U, // C_SEQ_S + 0U, // C_SF_D32 + 0U, // C_SF_D64 + 0U, // C_SF_S + 0U, // C_UEQ_D32 + 0U, // C_UEQ_D64 + 0U, // C_UEQ_S + 0U, // C_ULE_D32 + 0U, // C_ULE_D64 + 0U, // C_ULE_S + 0U, // C_ULT_D32 + 0U, // C_ULT_D64 + 0U, // C_ULT_S + 0U, // C_UN_D32 + 0U, // C_UN_D64 + 0U, // C_UN_S + 0U, // CmpRxRy16 + 0U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 0U, // Constant32 + 0U, // DADD + 0U, // DADDi + 0U, // DADDiu + 0U, // DADDu + 0U, // DAHI + 4U, // DALIGN + 0U, // DATI + 0U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 0U, // DDIV + 0U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 21U, // DEXT + 21U, // DEXTM + 21U, // DEXTU + 0U, // DI + 21U, // DINS + 21U, // DINSM + 21U, // DINSU + 0U, // DIV + 0U, // DIVU + 0U, // DIV_S_B + 0U, // DIV_S_D + 0U, // DIV_S_H + 0U, // DIV_S_W + 0U, // DIV_U_B + 0U, // DIV_U_D + 0U, // DIV_U_H + 0U, // DIV_U_W + 0U, // DI_MM + 4U, // DLSA + 4U, // DLSA_R6 + 1U, // DMFC0 + 0U, // DMFC1 + 1U, // DMFC2 + 0U, // DMOD + 0U, // DMODU + 1U, // DMTC0 + 0U, // DMTC1 + 1U, // DMTC2 + 0U, // DMUH + 0U, // DMUHU + 0U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 0U, // DMULU + 0U, // DMUL_R6 + 0U, // DOTP_S_D + 0U, // DOTP_S_H + 0U, // DOTP_S_W + 0U, // DOTP_U_D + 0U, // DOTP_U_H + 0U, // DOTP_U_W + 2U, // DPADD_S_D + 2U, // DPADD_S_H + 2U, // DPADD_S_W + 2U, // DPADD_U_D + 2U, // DPADD_U_H + 2U, // DPADD_U_W + 0U, // DPAQX_SA_W_PH + 0U, // DPAQX_S_W_PH + 0U, // DPAQ_SA_L_W + 0U, // DPAQ_S_W_PH + 0U, // DPAU_H_QBL + 0U, // DPAU_H_QBR + 0U, // DPAX_W_PH + 0U, // DPA_W_PH + 0U, // DPOP + 0U, // DPSQX_SA_W_PH + 0U, // DPSQX_S_W_PH + 0U, // DPSQ_SA_L_W + 0U, // DPSQ_S_W_PH + 2U, // DPSUB_S_D + 2U, // DPSUB_S_H + 2U, // DPSUB_S_W + 2U, // DPSUB_U_D + 2U, // DPSUB_U_H + 2U, // DPSUB_U_W + 0U, // DPSU_H_QBL + 0U, // DPSU_H_QBR + 0U, // DPSX_W_PH + 0U, // DPS_W_PH + 1U, // DROTR + 1U, // DROTR32 + 0U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 1U, // DSLL + 1U, // DSLL32 + 0U, // DSLL64_32 + 0U, // DSLLV + 1U, // DSRA + 1U, // DSRA32 + 0U, // DSRAV + 1U, // DSRL + 1U, // DSRL32 + 0U, // DSRLV + 0U, // DSUB + 0U, // DSUBu + 0U, // DUDIV + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EI + 0U, // EI_MM + 0U, // ERET + 0U, // ERET_MM + 21U, // EXT + 1U, // EXTP + 1U, // EXTPDP + 0U, // EXTPDPV + 0U, // EXTPV + 0U, // EXTRV_RS_W + 0U, // EXTRV_R_W + 0U, // EXTRV_S_H + 0U, // EXTRV_W + 1U, // EXTR_RS_W + 1U, // EXTR_R_W + 1U, // EXTR_S_H + 1U, // EXTR_W + 5U, // EXTS + 5U, // EXTS32 + 21U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_D32 + 0U, // FABS_D64 + 0U, // FABS_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 0U, // FABS_W + 0U, // FADD_D + 0U, // FADD_D32 + 0U, // FADD_D64 + 0U, // FADD_MM + 0U, // FADD_S + 0U, // FADD_S_MM + 0U, // FADD_W + 0U, // FCAF_D + 0U, // FCAF_W + 0U, // FCEQ_D + 0U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 0U, // FCLE_D + 0U, // FCLE_W + 0U, // FCLT_D + 0U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 0U, // FCNE_D + 0U, // FCNE_W + 0U, // FCOR_D + 0U, // FCOR_W + 0U, // FCUEQ_D + 0U, // FCUEQ_W + 0U, // FCULE_D + 0U, // FCULE_W + 0U, // FCULT_D + 0U, // FCULT_W + 0U, // FCUNE_D + 0U, // FCUNE_W + 0U, // FCUN_D + 0U, // FCUN_W + 0U, // FDIV_D + 0U, // FDIV_D32 + 0U, // FDIV_D64 + 0U, // FDIV_MM + 0U, // FDIV_S + 0U, // FDIV_S_MM + 0U, // FDIV_W + 0U, // FEXDO_H + 0U, // FEXDO_W + 0U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_S + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 2U, // FMADD_D + 2U, // FMADD_W + 0U, // FMAX_A_D + 0U, // FMAX_A_W + 0U, // FMAX_D + 0U, // FMAX_W + 0U, // FMIN_A_D + 0U, // FMIN_A_W + 0U, // FMIN_D + 0U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 2U, // FMSUB_D + 2U, // FMSUB_W + 0U, // FMUL_D + 0U, // FMUL_D32 + 0U, // FMUL_D64 + 0U, // FMUL_MM + 0U, // FMUL_S + 0U, // FMUL_S_MM + 0U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D64 + 0U, // FNEG_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 0U, // FSAF_D + 0U, // FSAF_W + 0U, // FSEQ_D + 0U, // FSEQ_W + 0U, // FSLE_D + 0U, // FSLE_W + 0U, // FSLT_D + 0U, // FSLT_W + 0U, // FSNE_D + 0U, // FSNE_W + 0U, // FSOR_D + 0U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D64 + 0U, // FSQRT_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 0U, // FSUB_D + 0U, // FSUB_D32 + 0U, // FSUB_D64 + 0U, // FSUB_MM + 0U, // FSUB_S + 0U, // FSUB_S_MM + 0U, // FSUB_W + 0U, // FSUEQ_D + 0U, // FSUEQ_W + 0U, // FSULE_D + 0U, // FSULE_W + 0U, // FSULT_D + 0U, // FSULT_W + 0U, // FSUNE_D + 0U, // FSUNE_W + 0U, // FSUN_D + 0U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 0U, // FTQ_H + 0U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GotPrologue16 + 0U, // HADD_S_D + 0U, // HADD_S_H + 0U, // HADD_S_W + 0U, // HADD_U_D + 0U, // HADD_U_H + 0U, // HADD_U_W + 0U, // HSUB_S_D + 0U, // HSUB_S_H + 0U, // HSUB_S_W + 0U, // HSUB_U_D + 0U, // HSUB_U_H + 0U, // HSUB_U_W + 0U, // ILVEV_B + 0U, // ILVEV_D + 0U, // ILVEV_H + 0U, // ILVEV_W + 0U, // ILVL_B + 0U, // ILVL_D + 0U, // ILVL_H + 0U, // ILVL_W + 0U, // ILVOD_B + 0U, // ILVOD_D + 0U, // ILVOD_H + 0U, // ILVOD_W + 0U, // ILVR_B + 0U, // ILVR_D + 0U, // ILVR_H + 0U, // ILVR_W + 21U, // INS + 0U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 21U, // INS_MM + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIC + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JR_HB + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LB + 0U, // LB64 + 0U, // LBU16_MM + 0U, // LBUX + 0U, // LB_MM + 0U, // LBu + 0U, // LBu64 + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_MM + 0U, // LDC2 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 0U, // LDXC1 + 0U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH64 + 0U, // LHU16_MM + 0U, // LHX + 0U, // LH_MM + 0U, // LHu + 0U, // LHu64 + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LL + 0U, // LLD + 0U, // LLD_R6 + 0U, // LL_MM + 0U, // LL_R6 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 4U, // LSA + 4U, // LSA_R6 + 0U, // LUXC1 + 0U, // LUXC164 + 0U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWGP_MM + 0U, // LWL + 0U, // LWL64 + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM32_MM + 0U, // LWM_MM + 0U, // LWPC + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWR_MM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 0U, // LWX + 0U, // LWXC1 + 0U, // LWXC1_MM + 0U, // LWXS_MM + 0U, // LW_MM + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 0U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 0U, // LoadAddr32Imm + 0U, // LoadAddr32Reg + 0U, // LoadImm32Reg + 0U, // LoadImm64Reg + 0U, // LwConstant32 + 0U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 2U, // MADDF_D + 2U, // MADDF_S + 2U, // MADDR_Q_H + 2U, // MADDR_Q_W + 0U, // MADDU + 0U, // MADDU_DSP + 0U, // MADDU_MM + 2U, // MADDV_B + 2U, // MADDV_D + 2U, // MADDV_H + 2U, // MADDV_W + 20U, // MADD_D32 + 20U, // MADD_D32_MM + 20U, // MADD_D64 + 0U, // MADD_DSP + 0U, // MADD_MM + 2U, // MADD_Q_H + 2U, // MADD_Q_W + 20U, // MADD_S + 20U, // MADD_S_MM + 0U, // MAQ_SA_W_PHL + 0U, // MAQ_SA_W_PHR + 0U, // MAQ_S_W_PHL + 0U, // MAQ_S_W_PHR + 0U, // MAXA_D + 0U, // MAXA_S + 0U, // MAXI_S_B + 0U, // MAXI_S_D + 0U, // MAXI_S_H + 0U, // MAXI_S_W + 0U, // MAXI_U_B + 0U, // MAXI_U_D + 0U, // MAXI_U_H + 0U, // MAXI_U_W + 0U, // MAX_A_B + 0U, // MAX_A_D + 0U, // MAX_A_H + 0U, // MAX_A_W + 0U, // MAX_D + 0U, // MAX_S + 0U, // MAX_S_B + 0U, // MAX_S_D + 0U, // MAX_S_H + 0U, // MAX_S_W + 0U, // MAX_U_B + 0U, // MAX_U_D + 0U, // MAX_U_H + 0U, // MAX_U_W + 1U, // MFC0 + 0U, // MFC1 + 0U, // MFC1_MM + 1U, // MFC2 + 0U, // MFHC1_D32 + 0U, // MFHC1_D64 + 0U, // MFHC1_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_MM + 0U, // MINA_D + 0U, // MINA_S + 0U, // MINI_S_B + 0U, // MINI_S_D + 0U, // MINI_S_H + 0U, // MINI_S_W + 0U, // MINI_U_B + 0U, // MINI_U_D + 0U, // MINI_U_H + 0U, // MINI_U_W + 0U, // MIN_A_B + 0U, // MIN_A_D + 0U, // MIN_A_H + 0U, // MIN_A_W + 0U, // MIN_D + 0U, // MIN_S + 0U, // MIN_S_B + 0U, // MIN_S_D + 0U, // MIN_S_H + 0U, // MIN_S_W + 0U, // MIN_U_B + 0U, // MIN_U_D + 0U, // MIN_U_H + 0U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MOD + 0U, // MODSUB + 0U, // MODU + 0U, // MOD_S_B + 0U, // MOD_S_D + 0U, // MOD_S_H + 0U, // MOD_S_W + 0U, // MOD_U_B + 0U, // MOD_U_D + 0U, // MOD_U_H + 0U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVEP_MM + 0U, // MOVE_V + 0U, // MOVF_D32 + 0U, // MOVF_D32_MM + 0U, // MOVF_D64 + 0U, // MOVF_I + 0U, // MOVF_I64 + 0U, // MOVF_I_MM + 0U, // MOVF_S + 0U, // MOVF_S_MM + 0U, // MOVN_I64_D64 + 0U, // MOVN_I64_I + 0U, // MOVN_I64_I64 + 0U, // MOVN_I64_S + 0U, // MOVN_I_D32 + 0U, // MOVN_I_D32_MM + 0U, // MOVN_I_D64 + 0U, // MOVN_I_I + 0U, // MOVN_I_I64 + 0U, // MOVN_I_MM + 0U, // MOVN_I_S + 0U, // MOVN_I_S_MM + 0U, // MOVT_D32 + 0U, // MOVT_D32_MM + 0U, // MOVT_D64 + 0U, // MOVT_I + 0U, // MOVT_I64 + 0U, // MOVT_I_MM + 0U, // MOVT_S + 0U, // MOVT_S_MM + 0U, // MOVZ_I64_D64 + 0U, // MOVZ_I64_I + 0U, // MOVZ_I64_I64 + 0U, // MOVZ_I64_S + 0U, // MOVZ_I_D32 + 0U, // MOVZ_I_D32_MM + 0U, // MOVZ_I_D64 + 0U, // MOVZ_I_I + 0U, // MOVZ_I_I64 + 0U, // MOVZ_I_MM + 0U, // MOVZ_I_S + 0U, // MOVZ_I_S_MM + 0U, // MSUB + 2U, // MSUBF_D + 2U, // MSUBF_S + 2U, // MSUBR_Q_H + 2U, // MSUBR_Q_W + 0U, // MSUBU + 0U, // MSUBU_DSP + 0U, // MSUBU_MM + 2U, // MSUBV_B + 2U, // MSUBV_D + 2U, // MSUBV_H + 2U, // MSUBV_W + 20U, // MSUB_D32 + 20U, // MSUB_D32_MM + 20U, // MSUB_D64 + 0U, // MSUB_DSP + 0U, // MSUB_MM + 2U, // MSUB_Q_H + 2U, // MSUB_Q_W + 20U, // MSUB_S + 20U, // MSUB_S_MM + 1U, // MTC0 + 0U, // MTC1 + 0U, // MTC1_MM + 1U, // MTC2 + 0U, // MTHC1_D32 + 0U, // MTHC1_D64 + 0U, // MTHC1_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 0U, // MUH + 0U, // MUHU + 0U, // MUL + 0U, // MULEQ_S_W_PHL + 0U, // MULEQ_S_W_PHR + 0U, // MULEU_S_PH_QBL + 0U, // MULEU_S_PH_QBR + 0U, // MULQ_RS_PH + 0U, // MULQ_RS_W + 0U, // MULQ_S_PH + 0U, // MULQ_S_W + 0U, // MULR_Q_H + 0U, // MULR_Q_W + 0U, // MULSAQ_S_W_PH + 0U, // MULSA_W_PH + 0U, // MULT + 0U, // MULTU_DSP + 0U, // MULT_DSP + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 0U, // MULU + 0U, // MULV_B + 0U, // MULV_D + 0U, // MULV_H + 0U, // MULV_W + 0U, // MUL_MM + 0U, // MUL_PH + 0U, // MUL_Q_H + 0U, // MUL_Q_W + 0U, // MUL_R6 + 0U, // MUL_S_PH + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 20U, // NMADD_D32 + 20U, // NMADD_D32_MM + 20U, // NMADD_D64 + 20U, // NMADD_S + 20U, // NMADD_S_MM + 20U, // NMSUB_D32 + 20U, // NMSUB_D32_MM + 20U, // NMSUB_D64 + 20U, // NMSUB_S + 20U, // NMSUB_S_MM + 0U, // NOP + 0U, // NOR + 0U, // NOR64 + 0U, // NORI_B + 0U, // NOR_MM + 0U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // NOT16_MM + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 0U, // OR + 0U, // OR16_MM + 0U, // OR64 + 0U, // ORI_B + 0U, // OR_MM + 0U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 1U, // ORi + 1U, // ORi64 + 1U, // ORi_MM + 0U, // OrRxRxRy16 + 0U, // PACKRL_PH + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PCKEV_B + 0U, // PCKEV_D + 0U, // PCKEV_H + 0U, // PCKEV_W + 0U, // PCKOD_B + 0U, // PCKOD_D + 0U, // PCKOD_H + 0U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 0U, // PICK_PH + 0U, // PICK_QB + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHR + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECRQU_S_QB_PH + 0U, // PRECRQ_PH_W + 0U, // PRECRQ_QB_PH + 0U, // PRECRQ_RS_PH_W + 0U, // PRECR_QB_PH + 1U, // PRECR_SRA_PH_W + 1U, // PRECR_SRA_R_PH_W + 0U, // PREF + 0U, // PREF_MM + 0U, // PREF_R6 + 1U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 0U, // RADDU_W_QB + 0U, // RDDSP + 0U, // RDHWR + 0U, // RDHWR64 + 0U, // RDHWR_MM + 0U, // REPLV_PH + 0U, // REPLV_QB + 0U, // REPL_PH + 0U, // REPL_QB + 0U, // RINT_D + 0U, // RINT_S + 1U, // ROTR + 0U, // ROTRV + 0U, // ROTRV_MM + 1U, // ROTR_MM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_S + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 1U, // SAT_S_B + 1U, // SAT_S_D + 0U, // SAT_S_H + 1U, // SAT_S_W + 1U, // SAT_U_B + 1U, // SAT_U_D + 0U, // SAT_U_H + 1U, // SAT_U_W + 0U, // SB + 0U, // SB16_MM + 0U, // SB64 + 0U, // SB_MM + 0U, // SC + 0U, // SCD + 0U, // SCD_R6 + 0U, // SC_MM + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP_MM + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_MM + 0U, // SDC2 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 0U, // SDXC1 + 0U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SELEQZ + 0U, // SELEQZ64 + 0U, // SELEQZ_D + 0U, // SELEQZ_S + 0U, // SELNEZ + 0U, // SELNEZ64 + 0U, // SELNEZ_D + 0U, // SELNEZ_S + 2U, // SEL_D + 2U, // SEL_S + 0U, // SEQ + 0U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH64 + 0U, // SHF_B + 0U, // SHF_H + 0U, // SHF_W + 0U, // SHILO + 0U, // SHILOV + 0U, // SHLLV_PH + 0U, // SHLLV_QB + 0U, // SHLLV_S_PH + 0U, // SHLLV_S_W + 1U, // SHLL_PH + 1U, // SHLL_QB + 1U, // SHLL_S_PH + 1U, // SHLL_S_W + 0U, // SHRAV_PH + 0U, // SHRAV_QB + 0U, // SHRAV_R_PH + 0U, // SHRAV_R_QB + 0U, // SHRAV_R_W + 1U, // SHRA_PH + 1U, // SHRA_QB + 1U, // SHRA_R_PH + 1U, // SHRA_R_QB + 1U, // SHRA_R_W + 0U, // SHRLV_PH + 0U, // SHRLV_QB + 1U, // SHRL_PH + 1U, // SHRL_QB + 0U, // SH_MM + 9U, // SLDI_B + 9U, // SLDI_D + 9U, // SLDI_H + 9U, // SLDI_W + 10U, // SLD_B + 10U, // SLD_D + 10U, // SLD_H + 10U, // SLD_W + 1U, // SLL + 0U, // SLL16_MM + 0U, // SLL64_32 + 0U, // SLL64_64 + 0U, // SLLI_B + 0U, // SLLI_D + 0U, // SLLI_H + 0U, // SLLI_W + 0U, // SLLV + 0U, // SLLV_MM + 0U, // SLL_B + 0U, // SLL_D + 0U, // SLL_H + 1U, // SLL_MM + 0U, // SLL_W + 0U, // SLT + 0U, // SLT64 + 0U, // SLT_MM + 0U, // SLTi + 0U, // SLTi64 + 0U, // SLTi_MM + 0U, // SLTiu + 0U, // SLTiu64 + 0U, // SLTiu_MM + 0U, // SLTu + 0U, // SLTu64 + 0U, // SLTu_MM + 0U, // SNE + 0U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 8U, // SPLATI_B + 8U, // SPLATI_D + 8U, // SPLATI_H + 8U, // SPLATI_W + 8U, // SPLAT_B + 8U, // SPLAT_D + 8U, // SPLAT_H + 8U, // SPLAT_W + 1U, // SRA + 0U, // SRAI_B + 0U, // SRAI_D + 0U, // SRAI_H + 0U, // SRAI_W + 1U, // SRARI_B + 1U, // SRARI_D + 0U, // SRARI_H + 1U, // SRARI_W + 0U, // SRAR_B + 0U, // SRAR_D + 0U, // SRAR_H + 0U, // SRAR_W + 0U, // SRAV + 0U, // SRAV_MM + 0U, // SRA_B + 0U, // SRA_D + 0U, // SRA_H + 1U, // SRA_MM + 0U, // SRA_W + 1U, // SRL + 0U, // SRL16_MM + 0U, // SRLI_B + 0U, // SRLI_D + 0U, // SRLI_H + 0U, // SRLI_W + 1U, // SRLRI_B + 1U, // SRLRI_D + 0U, // SRLRI_H + 1U, // SRLRI_W + 0U, // SRLR_B + 0U, // SRLR_D + 0U, // SRLR_H + 0U, // SRLR_W + 0U, // SRLV + 0U, // SRLV_MM + 0U, // SRL_B + 0U, // SRL_D + 0U, // SRL_H + 1U, // SRL_MM + 0U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 0U, // SUB + 0U, // SUBQH_PH + 0U, // SUBQH_R_PH + 0U, // SUBQH_R_W + 0U, // SUBQH_W + 0U, // SUBQ_PH + 0U, // SUBQ_S_PH + 0U, // SUBQ_S_W + 0U, // SUBSUS_U_B + 0U, // SUBSUS_U_D + 0U, // SUBSUS_U_H + 0U, // SUBSUS_U_W + 0U, // SUBSUU_S_B + 0U, // SUBSUU_S_D + 0U, // SUBSUU_S_H + 0U, // SUBSUU_S_W + 0U, // SUBS_S_B + 0U, // SUBS_S_D + 0U, // SUBS_S_H + 0U, // SUBS_S_W + 0U, // SUBS_U_B + 0U, // SUBS_U_D + 0U, // SUBS_U_H + 0U, // SUBS_U_W + 0U, // SUBU16_MM + 0U, // SUBUH_QB + 0U, // SUBUH_R_QB + 0U, // SUBU_PH + 0U, // SUBU_QB + 0U, // SUBU_S_PH + 0U, // SUBU_S_QB + 0U, // SUBVI_B + 0U, // SUBVI_D + 0U, // SUBVI_H + 0U, // SUBVI_W + 0U, // SUBV_B + 0U, // SUBV_D + 0U, // SUBV_H + 0U, // SUBV_W + 0U, // SUB_MM + 0U, // SUBu + 0U, // SUBu_MM + 0U, // SUXC1 + 0U, // SUXC164 + 0U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWL + 0U, // SWL64 + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM32_MM + 0U, // SWM_MM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWR_MM + 0U, // SWSP_MM + 0U, // SWXC1 + 0U, // SWXC1_MM + 0U, // SW_MM + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNC_MM + 0U, // SYSCALL + 0U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // ShRxRyOffMemX16 + 1U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltCCRxRy16 + 0U, // SltRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRy16 + 0U, // SltuRxRyRz16 + 1U, // SraX16 + 0U, // SravRxRy16 + 1U, // SrlX16 + 0U, // SrlvRxRy16 + 0U, // SubuRxRyRz16 + 0U, // SwRxRyOffMemX16 + 0U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 1U, // TEQ + 0U, // TEQI + 0U, // TEQI_MM + 1U, // TEQ_MM + 1U, // TGE + 0U, // TGEI + 0U, // TGEIU + 0U, // TGEIU_MM + 0U, // TGEI_MM + 1U, // TGEU + 1U, // TGEU_MM + 1U, // TGE_MM + 0U, // TLBP + 0U, // TLBP_MM + 0U, // TLBR + 0U, // TLBR_MM + 0U, // TLBWI + 0U, // TLBWI_MM + 0U, // TLBWR + 0U, // TLBWR_MM + 1U, // TLT + 0U, // TLTI + 0U, // TLTIU_MM + 0U, // TLTI_MM + 1U, // TLTU + 1U, // TLTU_MM + 1U, // TLT_MM + 1U, // TNE + 0U, // TNEI + 0U, // TNEI_MM + 1U, // TNE_MM + 0U, // TRAP + 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_S + 0U, // TRUNC_W_D32 + 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_MM + 0U, // TRUNC_W_S + 0U, // TRUNC_W_S_MM + 0U, // TTLTIU + 0U, // UDIV + 0U, // UDIV_MM + 0U, // V3MULU + 0U, // VMM0 + 0U, // VMULU + 2U, // VSHF_B + 2U, // VSHF_D + 2U, // VSHF_H + 2U, // VSHF_W + 0U, // WAIT + 0U, // WAIT_MM + 0U, // WRDSP + 0U, // WSBH + 0U, // WSBH_MM + 0U, // XOR + 0U, // XOR16_MM + 0U, // XOR64 + 0U, // XORI_B + 0U, // XOR_MM + 0U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 1U, // XORi + 1U, // XORi64 + 1U, // XORi_MM + 0U, // XorRxRxRy16 + 0U + }; + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, + /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, + /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, + /* 22 */ 'v', 'm', 'm', '0', 9, 0, + /* 28 */ 'm', 't', 'm', '0', 9, 0, + /* 34 */ 'm', 't', 'p', '0', 9, 0, + /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, + /* 47 */ 'l', 'd', 'c', '1', 9, 0, + /* 53 */ 's', 'd', 'c', '1', 9, 0, + /* 59 */ 'c', 'f', 'c', '1', 9, 0, + /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, + /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, + /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, + /* 86 */ 'c', 't', 'c', '1', 9, 0, + /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, + /* 99 */ 'l', 'w', 'c', '1', 9, 0, + /* 105 */ 's', 'w', 'c', '1', 9, 0, + /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, + /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, + /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, + /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, + /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, + /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, + /* 153 */ 'm', 't', 'm', '1', 9, 0, + /* 159 */ 'm', 't', 'p', '1', 9, 0, + /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, + /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, + /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, + /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, + /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, + /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, + /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, + /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, + /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, + /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, + /* 247 */ 'l', 'd', 'c', '2', 9, 0, + /* 253 */ 's', 'd', 'c', '2', 9, 0, + /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, + /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, + /* 273 */ 'l', 'w', 'c', '2', 9, 0, + /* 279 */ 's', 'w', 'c', '2', 9, 0, + /* 285 */ 'm', 't', 'm', '2', 9, 0, + /* 291 */ 'm', 't', 'p', '2', 9, 0, + /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, + /* 306 */ 'l', 'd', 'c', '3', 9, 0, + /* 312 */ 's', 'd', 'c', '3', 9, 0, + /* 318 */ 'l', 'w', 'c', '3', 9, 0, + /* 324 */ 's', 'w', 'c', '3', 9, 0, + /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, + /* 339 */ 's', 'b', '1', '6', 9, 0, + /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, + /* 352 */ 's', 'h', '1', '6', 9, 0, + /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, + /* 366 */ 'l', 'i', '1', '6', 9, 0, + /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, + /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, + /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, + /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, + /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, + /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, + /* 418 */ 'j', 'r', '1', '6', 9, 0, + /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, + /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, + /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, + /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, + /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, + /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, + /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, + /* 477 */ 'l', 'w', '1', '6', 9, 0, + /* 483 */ 's', 'w', '1', '6', 9, 0, + /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, + /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, + /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, + /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, + /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, + /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, + /* 571 */ 'd', 's', 'r', 'a', 9, 0, + /* 577 */ 'd', 'l', 's', 'a', 9, 0, + /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, + /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, + /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, + /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, + /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, + /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, + /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, + /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, + /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, + /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, + /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, + /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, + /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, + /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, + /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, + /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, + /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, + /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, + /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, + /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, + /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, + /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, + /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, + /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, + /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, + /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, + /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, + /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, + /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, + /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, + /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, + /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, + /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, + /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, + /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, + /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, + /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, + /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, + /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, + /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, + /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, + /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, + /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, + /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, + /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, + /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, + /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, + /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, + /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, + /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, + /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, + /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, + /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, + /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, + /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, + /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, + /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, + /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, + /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, + /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, + /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, + /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, + /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, + /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, + /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, + /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, + /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, + /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, + /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, + /* 1188 */ 's', 't', '.', 'b', 9, 0, + /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, + /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, + /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, + /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, + /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, + /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, + /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, + /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, + /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, + /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, + /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, + /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, + /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, + /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, + /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, + /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, + /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, + /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, + /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, + /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, + /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, + /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, + /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, + /* 1412 */ 'b', 'z', '.', 'b', 9, 0, + /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0, + /* 1425 */ 's', 'e', 'b', 9, 0, + /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0, + /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, + /* 1446 */ 'l', 'b', 9, 0, + /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, + /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, + /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, + /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, + /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, + /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, + /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, + /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, + /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, + /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, + /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, + /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, + /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, + /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, + /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, + /* 1616 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, + /* 1628 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0, + /* 1640 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0, + /* 1651 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0, + /* 1662 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0, + /* 1673 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, + /* 1687 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, + /* 1700 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, + /* 1712 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0, + /* 1721 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0, + /* 1730 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0, + /* 1740 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0, + /* 1750 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0, + /* 1760 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0, + /* 1770 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0, + /* 1782 */ 's', 'b', 9, 0, + /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, + /* 1794 */ 'm', 's', 'u', 'b', 9, 0, + /* 1800 */ 'b', 'c', 9, 0, + /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, + /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, + /* 1816 */ 'j', 'i', 'c', 9, 0, + /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, + /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, + /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, + /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, + /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, + /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, + /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, + /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, + /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, + /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, + /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, + /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, + /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, + /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, + /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, + /* 1937 */ 'j', 'r', 'c', 9, 0, + /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, + /* 1949 */ 'b', 'l', 't', 'c', 9, 0, + /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, + /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, + /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, + /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, + /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, + /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, + /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, + /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, + /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, + /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, + /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, + /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, + /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, + /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, + /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, + /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, + /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, + /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, + /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, + /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, + /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, + /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, + /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, + /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, + /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, + /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, + /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0, + /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, + /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, + /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, + /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, + /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, + /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, + /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, + /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, + /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0, + /* 2268 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0, + /* 2276 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0, + /* 2285 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0, + /* 2296 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0, + /* 2305 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0, + /* 2317 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0, + /* 2326 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0, + /* 2334 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0, + /* 2342 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0, + /* 2351 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0, + /* 2360 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0, + /* 2369 */ 'c', '.', 'f', '.', 'd', 9, 0, + /* 2376 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0, + /* 2386 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0, + /* 2394 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0, + /* 2405 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0, + /* 2413 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0, + /* 2422 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0, + /* 2431 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0, + /* 2439 */ 'c', '.', 's', 'f', '.', 'd', 9, 0, + /* 2447 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0, + /* 2455 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0, + /* 2463 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0, + /* 2471 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0, + /* 2479 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0, + /* 2488 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0, + /* 2496 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0, + /* 2504 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0, + /* 2514 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0, + /* 2522 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0, + /* 2531 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0, + /* 2540 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0, + /* 2549 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0, + /* 2559 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0, + /* 2569 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0, + /* 2578 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0, + /* 2587 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0, + /* 2596 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0, + /* 2607 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0, + /* 2618 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0, + /* 2628 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0, + /* 2639 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, + /* 2648 */ 's', 'e', 'l', '.', 'd', 9, 0, + /* 2655 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0, + /* 2664 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0, + /* 2672 */ 's', 'l', 'l', '.', 'd', 9, 0, + /* 2679 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0, + /* 2689 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0, + /* 2697 */ 's', 'r', 'l', '.', 'd', 9, 0, + /* 2704 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0, + /* 2713 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, + /* 2721 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0, + /* 2729 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, + /* 2737 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0, + /* 2745 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0, + /* 2755 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0, + /* 2763 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0, + /* 2774 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0, + /* 2782 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0, + /* 2790 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0, + /* 2798 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0, + /* 2806 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0, + /* 2816 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0, + /* 2824 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0, + /* 2833 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0, + /* 2844 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0, + /* 2852 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0, + /* 2861 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0, + /* 2872 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0, + /* 2881 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0, + /* 2893 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0, + /* 2902 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0, + /* 2910 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0, + /* 2918 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0, + /* 2926 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0, + /* 2934 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0, + /* 2942 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0, + /* 2952 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0, + /* 2960 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0, + /* 2969 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0, + /* 2977 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, + /* 2986 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, + /* 2996 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, + /* 3006 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, + /* 3017 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0, + /* 3029 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, + /* 3039 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, + /* 3050 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0, + /* 3059 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0, + /* 3068 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0, + /* 3077 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0, + /* 3087 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0, + /* 3097 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0, + /* 3107 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0, + /* 3117 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0, + /* 3126 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0, + /* 3136 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0, + /* 3146 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0, + /* 3156 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0, + /* 3166 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0, + /* 3175 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0, + /* 3184 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, + /* 3195 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, + /* 3206 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0, + /* 3218 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0, + /* 3227 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0, + /* 3236 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0, + /* 3246 */ 'a', 'b', 's', '.', 'd', 9, 0, + /* 3253 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, + /* 3263 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0, + /* 3272 */ 'b', 's', 'e', 't', '.', 'd', 9, 0, + /* 3280 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0, + /* 3289 */ 'c', '.', 'l', 't', '.', 'd', 9, 0, + /* 3297 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0, + /* 3307 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0, + /* 3315 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0, + /* 3324 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0, + /* 3335 */ 'f', 's', 'l', 't', '.', 'd', 9, 0, + /* 3343 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0, + /* 3352 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0, + /* 3363 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0, + /* 3372 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0, + /* 3384 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0, + /* 3393 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0, + /* 3401 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0, + /* 3410 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0, + /* 3420 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, + /* 3429 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0, + /* 3439 */ 's', 't', '.', 'd', 9, 0, + /* 3445 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0, + /* 3453 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, + /* 3463 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, + /* 3473 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, + /* 3484 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0, + /* 3496 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, + /* 3506 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, + /* 3517 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0, + /* 3526 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0, + /* 3535 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0, + /* 3544 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0, + /* 3554 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0, + /* 3564 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0, + /* 3574 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0, + /* 3584 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0, + /* 3593 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0, + /* 3603 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0, + /* 3613 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0, + /* 3623 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0, + /* 3633 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0, + /* 3645 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0, + /* 3654 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0, + /* 3663 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, + /* 3674 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, + /* 3685 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0, + /* 3694 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0, + /* 3703 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'd', 9, 0, + /* 3713 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0, + /* 3722 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0, + /* 3731 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0, + /* 3740 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0, + /* 3749 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, + /* 3757 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0, + /* 3765 */ 'm', 'o', 'v', '.', 'd', 9, 0, + /* 3772 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0, + /* 3783 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0, + /* 3794 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0, + /* 3804 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0, + /* 3815 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, + /* 3824 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, + /* 3832 */ 'b', 'z', '.', 'd', 9, 0, + /* 3838 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0, + /* 3848 */ 'b', 'n', 'z', '.', 'd', 9, 0, + /* 3855 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0, + /* 3865 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0, + /* 3873 */ 's', 'c', 'd', 9, 0, + /* 3878 */ 'd', 'a', 'd', 'd', 9, 0, + /* 3884 */ 'm', 'a', 'd', 'd', 9, 0, + /* 3890 */ 'd', 's', 'h', 'd', 9, 0, + /* 3896 */ 'l', 'l', 'd', 9, 0, + /* 3901 */ 'a', 'n', 'd', 9, 0, + /* 3906 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0, + /* 3915 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0, + /* 3923 */ 'd', 'm', 'o', 'd', 9, 0, + /* 3929 */ 's', 'd', 9, 0, + /* 3933 */ 't', 'g', 'e', 9, 0, + /* 3938 */ 'c', 'a', 'c', 'h', 'e', 9, 0, + /* 3945 */ 'b', 'n', 'e', 9, 0, + /* 3950 */ 's', 'n', 'e', 9, 0, + /* 3955 */ 't', 'n', 'e', 9, 0, + /* 3960 */ 'm', 'o', 'v', 'e', 9, 0, + /* 3966 */ 'b', 'c', '0', 'f', 9, 0, + /* 3972 */ 'b', 'c', '1', 'f', 9, 0, + /* 3978 */ 'b', 'c', '2', 'f', 9, 0, + /* 3984 */ 'b', 'c', '3', 'f', 9, 0, + /* 3990 */ 'p', 'r', 'e', 'f', 9, 0, + /* 3996 */ 'm', 'o', 'v', 'f', 9, 0, + /* 4002 */ 'n', 'e', 'g', 9, 0, + /* 4007 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0, + /* 4016 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0, + /* 4025 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0, + /* 4035 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0, + /* 4044 */ 's', 'r', 'a', '.', 'h', 9, 0, + /* 4051 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0, + /* 4059 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0, + /* 4067 */ 's', 'l', 'd', '.', 'h', 9, 0, + /* 4074 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0, + /* 4083 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0, + /* 4092 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0, + /* 4101 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0, + /* 4109 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0, + /* 4117 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0, + /* 4125 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0, + /* 4133 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0, + /* 4142 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0, + /* 4150 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0, + /* 4158 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0, + /* 4168 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0, + /* 4176 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0, + /* 4185 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0, + /* 4194 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0, + /* 4203 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0, + /* 4213 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0, + /* 4223 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0, + /* 4232 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0, + /* 4241 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0, + /* 4250 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0, + /* 4258 */ 's', 'l', 'l', '.', 'h', 9, 0, + /* 4265 */ 's', 'r', 'l', '.', 'h', 9, 0, + /* 4272 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0, + /* 4281 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0, + /* 4289 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0, + /* 4298 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0, + /* 4308 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0, + /* 4318 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0, + /* 4327 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0, + /* 4338 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0, + /* 4349 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0, + /* 4359 */ 'c', 'e', 'q', '.', 'h', 9, 0, + /* 4366 */ 'f', 't', 'q', '.', 'h', 9, 0, + /* 4373 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0, + /* 4381 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0, + /* 4389 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0, + /* 4397 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0, + /* 4406 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0, + /* 4414 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, + /* 4424 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, + /* 4434 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, + /* 4445 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, + /* 4455 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, + /* 4466 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0, + /* 4475 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0, + /* 4484 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0, + /* 4493 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0, + /* 4503 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0, + /* 4513 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0, + /* 4523 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0, + /* 4533 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0, + /* 4542 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0, + /* 4552 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0, + /* 4562 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0, + /* 4572 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0, + /* 4582 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0, + /* 4592 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0, + /* 4601 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0, + /* 4610 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0, + /* 4622 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0, + /* 4631 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0, + /* 4642 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0, + /* 4651 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0, + /* 4661 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0, + /* 4670 */ 'b', 's', 'e', 't', '.', 'h', 9, 0, + /* 4678 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0, + /* 4686 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0, + /* 4696 */ 's', 't', '.', 'h', 9, 0, + /* 4702 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, + /* 4712 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, + /* 4722 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, + /* 4733 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, + /* 4743 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, + /* 4754 */ 'm', 'o', 'd', '_', 'u', '.', 'h', 9, 0, + /* 4763 */ 'c', 'l', 'e', '_', 'u', '.', 'h', 9, 0, + /* 4772 */ 'a', 'v', 'e', '_', 'u', '.', 'h', 9, 0, + /* 4781 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'h', 9, 0, + /* 4791 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'h', 9, 0, + /* 4801 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'h', 9, 0, + /* 4811 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'h', 9, 0, + /* 4821 */ 'm', 'i', 'n', '_', 'u', '.', 'h', 9, 0, + /* 4830 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'h', 9, 0, + /* 4840 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'h', 9, 0, + /* 4850 */ 's', 'u', 'b', 's', '_', 'u', '.', 'h', 9, 0, + /* 4860 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0, + /* 4870 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0, + /* 4882 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0, + /* 4891 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0, + /* 4900 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0, + /* 4909 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0, + /* 4918 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0, + /* 4928 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0, + /* 4937 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0, + /* 4946 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0, + /* 4955 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0, + /* 4964 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0, + /* 4972 */ 'b', 'z', '.', 'h', 9, 0, + /* 4978 */ 'b', 'n', 'z', '.', 'h', 9, 0, + /* 4985 */ 'd', 's', 'b', 'h', 9, 0, + /* 4991 */ 'w', 's', 'b', 'h', 9, 0, + /* 4997 */ 's', 'e', 'h', 9, 0, + /* 5002 */ 'l', 'h', 9, 0, + /* 5006 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0, + /* 5015 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0, + /* 5029 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0, + /* 5042 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0, + /* 5059 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0, + /* 5070 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0, + /* 5080 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0, + /* 5090 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0, + /* 5099 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0, + /* 5108 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0, + /* 5117 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0, + /* 5126 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0, + /* 5137 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0, + /* 5145 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0, + /* 5154 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0, + /* 5163 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0, + /* 5174 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0, + /* 5185 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, + /* 5197 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, + /* 5209 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0, + /* 5221 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0, + /* 5232 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0, + /* 5242 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0, + /* 5253 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0, + /* 5264 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0, + /* 5275 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0, + /* 5286 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0, + /* 5297 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0, + /* 5308 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0, + /* 5320 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0, + /* 5332 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0, + /* 5343 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0, + /* 5352 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0, + /* 5361 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0, + /* 5371 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0, + /* 5381 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0, + /* 5391 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0, + /* 5401 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5411 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5426 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5441 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5453 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5466 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5481 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5494 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5508 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5522 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5532 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5543 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0, + /* 5554 */ 's', 'h', 9, 0, + /* 5558 */ 'd', 'm', 'u', 'h', 9, 0, + /* 5564 */ 's', 'y', 'n', 'c', 'i', 9, 0, + /* 5571 */ 'd', 'a', 'd', 'd', 'i', 9, 0, + /* 5578 */ 'a', 'n', 'd', 'i', 9, 0, + /* 5584 */ 't', 'g', 'e', 'i', 9, 0, + /* 5590 */ 's', 'n', 'e', 'i', 9, 0, + /* 5596 */ 't', 'n', 'e', 'i', 9, 0, + /* 5602 */ 'd', 'a', 'h', 'i', 9, 0, + /* 5608 */ 'm', 'f', 'h', 'i', 9, 0, + /* 5614 */ 'm', 't', 'h', 'i', 9, 0, + /* 5620 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0, + /* 5634 */ 'd', 'l', 'i', 9, 0, + /* 5639 */ 'c', 'm', 'p', 'i', 9, 0, + /* 5645 */ 's', 'e', 'q', 'i', 9, 0, + /* 5651 */ 't', 'e', 'q', 'i', 9, 0, + /* 5657 */ 'x', 'o', 'r', 'i', 9, 0, + /* 5663 */ 'd', 'a', 't', 'i', 9, 0, + /* 5669 */ 's', 'l', 't', 'i', 9, 0, + /* 5675 */ 't', 'l', 't', 'i', 9, 0, + /* 5681 */ 'd', 'a', 'u', 'i', 9, 0, + /* 5687 */ 'l', 'u', 'i', 9, 0, + /* 5692 */ 'j', 9, 0, + /* 5695 */ 'b', 'r', 'e', 'a', 'k', 9, 0, + /* 5702 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, + /* 5711 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, + /* 5720 */ 'b', 'a', 'l', 9, 0, + /* 5725 */ 'j', 'a', 'l', 9, 0, + /* 5730 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0, + /* 5738 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0, + /* 5746 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, + /* 5758 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, + /* 5770 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, + /* 5786 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, + /* 5801 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, + /* 5817 */ 'l', 'd', 'l', 9, 0, + /* 5822 */ 's', 'd', 'l', 9, 0, + /* 5827 */ 'b', 'n', 'e', 'l', 9, 0, + /* 5833 */ 'b', 'c', '0', 'f', 'l', 9, 0, + /* 5840 */ 'b', 'c', '1', 'f', 'l', 9, 0, + /* 5847 */ 'b', 'c', '2', 'f', 'l', 9, 0, + /* 5854 */ 'b', 'c', '3', 'f', 'l', 9, 0, + /* 5861 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0, + /* 5875 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0, + /* 5889 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, + /* 5902 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, + /* 5917 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0, + /* 5926 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0, + /* 5935 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0, + /* 5944 */ 'd', 's', 'l', 'l', 9, 0, + /* 5950 */ 'b', 'e', 'q', 'l', 9, 0, + /* 5956 */ 'd', 's', 'r', 'l', 9, 0, + /* 5962 */ 'b', 'c', '0', 't', 'l', 9, 0, + /* 5969 */ 'b', 'c', '1', 't', 'l', 9, 0, + /* 5976 */ 'b', 'c', '2', 't', 'l', 9, 0, + /* 5983 */ 'b', 'c', '3', 't', 'l', 9, 0, + /* 5990 */ 'd', 'm', 'u', 'l', 9, 0, + /* 5996 */ 'l', 'w', 'l', 9, 0, + /* 6001 */ 's', 'w', 'l', 9, 0, + /* 6006 */ 'b', 'g', 'e', 'z', 'l', 9, 0, + /* 6013 */ 'b', 'l', 'e', 'z', 'l', 9, 0, + /* 6020 */ 'b', 'g', 't', 'z', 'l', 9, 0, + /* 6027 */ 'b', 'l', 't', 'z', 'l', 9, 0, + /* 6034 */ 'l', 'w', 'm', 9, 0, + /* 6039 */ 's', 'w', 'm', 9, 0, + /* 6044 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0, + /* 6052 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0, + /* 6060 */ 'm', 'o', 'v', 'n', 9, 0, + /* 6066 */ 'd', 'c', 'l', 'o', 9, 0, + /* 6072 */ 'm', 'f', 'l', 'o', 9, 0, + /* 6078 */ 's', 'h', 'i', 'l', 'o', 9, 0, + /* 6085 */ 'm', 't', 'l', 'o', 9, 0, + /* 6091 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0, + /* 6101 */ 's', 'd', 'b', 'b', 'p', 9, 0, + /* 6108 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0, + /* 6116 */ 'm', 'o', 'v', 'e', 'p', 9, 0, + /* 6123 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0, + /* 6131 */ 'c', 'm', 'p', 9, 0, + /* 6136 */ 'd', 'p', 'o', 'p', 9, 0, + /* 6142 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0, + /* 6153 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, + /* 6169 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, + /* 6186 */ 'r', 'd', 'd', 's', 'p', 9, 0, + /* 6193 */ 'w', 'r', 'd', 's', 'p', 9, 0, + /* 6200 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0, + /* 6211 */ 'e', 'x', 't', 'p', 9, 0, + /* 6217 */ 'l', 'w', 'p', 9, 0, + /* 6222 */ 's', 'w', 'p', 9, 0, + /* 6227 */ 'b', 'e', 'q', 9, 0, + /* 6232 */ 's', 'e', 'q', 9, 0, + /* 6237 */ 't', 'e', 'q', 9, 0, + /* 6242 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, + /* 6254 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, + /* 6266 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, + /* 6282 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, + /* 6297 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, + /* 6313 */ 'l', 'd', 'r', 9, 0, + /* 6318 */ 's', 'd', 'r', 9, 0, + /* 6323 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0, + /* 6337 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0, + /* 6351 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, + /* 6364 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, + /* 6379 */ 'j', 'r', 9, 0, + /* 6383 */ 'j', 'a', 'l', 'r', 9, 0, + /* 6389 */ 'n', 'o', 'r', 9, 0, + /* 6394 */ 'x', 'o', 'r', 9, 0, + /* 6399 */ 'd', 'r', 'o', 't', 'r', 9, 0, + /* 6406 */ 'r', 'd', 'h', 'w', 'r', 9, 0, + /* 6413 */ 'l', 'w', 'r', 9, 0, + /* 6418 */ 's', 'w', 'r', 9, 0, + /* 6423 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0, + /* 6431 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0, + /* 6439 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, + /* 6448 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, + /* 6457 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, + /* 6466 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0, + /* 6475 */ 'c', '.', 'l', 'e', '.', 's', 9, 0, + /* 6483 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0, + /* 6493 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0, + /* 6503 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0, + /* 6512 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0, + /* 6523 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0, + /* 6532 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0, + /* 6543 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0, + /* 6555 */ 'c', '.', 'f', '.', 's', 9, 0, + /* 6562 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0, + /* 6572 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0, + /* 6583 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0, + /* 6592 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0, + /* 6601 */ 'c', '.', 's', 'f', '.', 's', 9, 0, + /* 6609 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0, + /* 6617 */ 'n', 'e', 'g', '.', 's', 9, 0, + /* 6624 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0, + /* 6635 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0, + /* 6646 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0, + /* 6656 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0, + /* 6667 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, + /* 6676 */ 's', 'e', 'l', '.', 's', 9, 0, + /* 6683 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0, + /* 6692 */ 'm', 'u', 'l', '.', 's', 9, 0, + /* 6699 */ 'm', 'i', 'n', '.', 's', 9, 0, + /* 6706 */ 'c', '.', 'u', 'n', '.', 's', 9, 0, + /* 6714 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0, + /* 6724 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0, + /* 6735 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0, + /* 6743 */ 'c', '.', 'e', 'q', '.', 's', 9, 0, + /* 6751 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0, + /* 6761 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0, + /* 6770 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0, + /* 6781 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0, + /* 6790 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0, + /* 6801 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0, + /* 6813 */ 'a', 'b', 's', '.', 's', 9, 0, + /* 6820 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, + /* 6829 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0, + /* 6838 */ 'c', '.', 'l', 't', '.', 's', 9, 0, + /* 6846 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0, + /* 6856 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0, + /* 6865 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0, + /* 6876 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0, + /* 6885 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0, + /* 6896 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0, + /* 6908 */ 'r', 'i', 'n', 't', '.', 's', 9, 0, + /* 6916 */ 's', 'q', 'r', 't', '.', 's', 9, 0, + /* 6924 */ 'm', 'o', 'v', 't', '.', 's', 9, 0, + /* 6932 */ 'd', 'i', 'v', '.', 's', 9, 0, + /* 6939 */ 'm', 'o', 'v', '.', 's', 9, 0, + /* 6946 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0, + /* 6957 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0, + /* 6968 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0, + /* 6978 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0, + /* 6989 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, + /* 6998 */ 'm', 'a', 'x', '.', 's', 9, 0, + /* 7005 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0, + /* 7015 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0, + /* 7025 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0, + /* 7033 */ 'j', 'a', 'l', 's', 9, 0, + /* 7039 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0, + /* 7048 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0, + /* 7057 */ 'j', 'a', 'l', 'r', 's', 9, 0, + /* 7064 */ 'l', 'w', 'x', 's', 9, 0, + /* 7070 */ 'b', 'c', '0', 't', 9, 0, + /* 7076 */ 'b', 'c', '1', 't', 9, 0, + /* 7082 */ 'b', 'c', '2', 't', 9, 0, + /* 7088 */ 'b', 'c', '3', 't', 9, 0, + /* 7094 */ 'w', 'a', 'i', 't', 9, 0, + /* 7100 */ 's', 'l', 't', 9, 0, + /* 7105 */ 't', 'l', 't', 9, 0, + /* 7110 */ 'd', 'm', 'u', 'l', 't', 9, 0, + /* 7117 */ 'n', 'o', 't', 9, 0, + /* 7122 */ 'm', 'o', 'v', 't', 9, 0, + /* 7128 */ 'l', 'b', 'u', 9, 0, + /* 7133 */ 'd', 's', 'u', 'b', 'u', 9, 0, + /* 7140 */ 'm', 's', 'u', 'b', 'u', 9, 0, + /* 7147 */ 'b', 'a', 'd', 'd', 'u', 9, 0, + /* 7154 */ 'd', 'a', 'd', 'd', 'u', 9, 0, + /* 7161 */ 'm', 'a', 'd', 'd', 'u', 9, 0, + /* 7168 */ 'd', 'm', 'o', 'd', 'u', 9, 0, + /* 7175 */ 't', 'g', 'e', 'u', 9, 0, + /* 7181 */ 'l', 'h', 'u', 9, 0, + /* 7186 */ 'd', 'm', 'u', 'h', 'u', 9, 0, + /* 7193 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0, + /* 7201 */ 't', 'g', 'e', 'i', 'u', 9, 0, + /* 7208 */ 's', 'l', 't', 'i', 'u', 9, 0, + /* 7215 */ 't', 'l', 't', 'i', 'u', 9, 0, + /* 7222 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0, + /* 7230 */ 'd', 'm', 'u', 'l', 'u', 9, 0, + /* 7237 */ 'v', 'm', 'u', 'l', 'u', 9, 0, + /* 7244 */ 's', 'l', 't', 'u', 9, 0, + /* 7250 */ 't', 'l', 't', 'u', 9, 0, + /* 7256 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0, + /* 7264 */ 'd', 'd', 'i', 'v', 'u', 9, 0, + /* 7271 */ 'l', 'w', 'u', 9, 0, + /* 7276 */ 'a', 'n', 'd', '.', 'v', 9, 0, + /* 7283 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0, + /* 7291 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0, + /* 7299 */ 'n', 'o', 'r', '.', 'v', 9, 0, + /* 7306 */ 'x', 'o', 'r', '.', 'v', 9, 0, + /* 7313 */ 'b', 'z', '.', 'v', 9, 0, + /* 7319 */ 'b', 'm', 'z', '.', 'v', 9, 0, + /* 7326 */ 'b', 'n', 'z', '.', 'v', 9, 0, + /* 7333 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0, + /* 7341 */ 'd', 's', 'r', 'a', 'v', 9, 0, + /* 7348 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0, + /* 7356 */ 'd', 'd', 'i', 'v', 9, 0, + /* 7362 */ 'd', 's', 'l', 'l', 'v', 9, 0, + /* 7369 */ 'd', 's', 'r', 'l', 'v', 9, 0, + /* 7376 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0, + /* 7384 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0, + /* 7393 */ 'e', 'x', 't', 'p', 'v', 9, 0, + /* 7400 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0, + /* 7408 */ 'i', 'n', 's', 'v', 9, 0, + /* 7414 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0, + /* 7423 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0, + /* 7432 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0, + /* 7441 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0, + /* 7451 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0, + /* 7461 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0, + /* 7471 */ 's', 'r', 'a', '.', 'w', 9, 0, + /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, + /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, + /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, + /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, + /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, + /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, + /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, + /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0, + /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, + /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, + /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, + /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, + /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, + /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, + /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, + /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, + /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, + /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, + /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, + /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, + /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, + /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, + /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, + /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, + /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, + /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, + /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, + /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, + /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, + /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, + /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, + /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, + /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, + /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, + /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, + /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, + /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, + /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, + /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, + /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, + /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, + /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, + /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, + /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, + /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, + /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, + /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, + /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, + /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, + /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, + /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, + /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, + /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, + /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, + /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, + /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, + /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, + /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, + /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, + /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, + /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, + /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, + /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, + /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, + /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, + /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, + /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, + /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, + /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, + /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, + /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, + /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, + /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, + /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, + /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, + /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, + /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, + /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, + /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, + /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, + /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, + /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, + /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, + /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, + /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, + /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, + /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, + /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, + /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, + /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, + /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, + /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, + /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, + /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, + /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, + /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, + /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, + /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, + /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, + /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, + /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, + /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, + /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, + /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, + /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, + /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, + /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, + /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, + /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, + /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, + /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, + /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, + /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, + /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, + /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, + /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, + /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, + /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, + /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, + /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, + /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, + /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, + /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, + /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, + /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, + /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, + /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, + /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, + /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, + /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, + /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, + /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, + /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, + /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, + /* 8737 */ 's', 't', '.', 'w', 9, 0, + /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, + /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, + /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, + /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, + /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, + /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, + /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, + /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, + /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, + /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, + /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, + /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, + /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, + /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, + /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, + /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, + /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, + /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, + /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, + /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, + /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, + /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, + /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, + /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, + /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, + /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, + /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, + /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, + /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, + /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, + /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, + /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, + /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, + /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, + /* 9072 */ 'b', 'z', '.', 'w', 9, 0, + /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, + /* 9085 */ 'l', 'w', 9, 0, + /* 9089 */ 's', 'w', 9, 0, + /* 9093 */ 'l', 'h', 'x', 9, 0, + /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, + /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, + /* 9110 */ 'l', 'w', 'x', 9, 0, + /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, + /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, + /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, + /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, + /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, + /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, + /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, + /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, + /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, + /* 9175 */ 'b', 'g', 't', 'z', 9, 0, + /* 9181 */ 'b', 'l', 't', 'z', 9, 0, + /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, + /* 9193 */ 's', 'e', 'b', 9, 32, 0, + /* 9199 */ 'j', 'r', 'c', 9, 32, 0, + /* 9205 */ 's', 'e', 'h', 9, 32, 0, + /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, + /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, + /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, + /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, + /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, + /* 9266 */ 's', 'y', 'n', 'c', 32, 0, + /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, + /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, + /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, + /* 9294 */ 'c', 'i', 'n', 's', 32, 0, + /* 9300 */ 'd', 'i', 'n', 's', 32, 0, + /* 9306 */ 'e', 'x', 't', 's', 32, 0, + /* 9312 */ 'd', 'e', 'x', 't', 32, 0, + /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, + /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, + /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, + /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, + /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, + /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, + /* 9364 */ 'c', '.', 0, + /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, + /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, + /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, + /* 9437 */ 'e', 'h', 'b', 0, + /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, + /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, + /* 9453 */ 'f', 'o', 'o', 0, + /* 9457 */ 't', 'l', 'b', 'p', 0, + /* 9462 */ 's', 's', 'n', 'o', 'p', 0, + /* 9468 */ 't', 'l', 'b', 'r', 0, + /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, + /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, + /* 9485 */ 'w', 'a', 'i', 't', 0, + }; +#endif + + // Emit the opcode for the instruction. + uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; + uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; + uint64_t Bits = (Bits2 << 32) | Bits1; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 16383)-1); +#endif + + + // Fragment 0 encoded into 4 bits for 11 unique commands. + //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); + switch ((Bits >> 14) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... + return; + break; + case 1: + // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... + printOperand(MI, 0, O); + break; + case 2: + // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 3: + // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 4: + // BREAK16_MM, SDBBP16_MM + printUnsignedImm8(MI, 0, O); + return; + break; + case 5: + // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 + printUnsignedImm(MI, 2, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 0, O); + return; + break; + case 6: + // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM + printFCCOperand(MI, 2, O); + break; + case 7: + // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM + printRegisterList(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 8: + // LWP_MM, SWP_MM + printRegisterPair(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 2, O); + return; + break; + case 9: + // SYNCI + printMemOperand(MI, 0, O); + return; + break; + case 10: + // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... + printOperand(MI, 3, O); + break; + } + + + // Fragment 1 encoded into 5 bits for 17 unique commands. + //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); + switch ((Bits >> 18) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... + SStream_concat0(O, ", "); + break; + case 1: + // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... + printOperand(MI, 2, O); + break; + case 2: + // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... + return; + break; + case 3: + // AND16_MM, OR16_MM, XOR16_MM + printOperand(MI, 1, O); + return; + break; + case 4: + // AddiuRxPcImmX16 + SStream_concat0(O, ", $pc, "); + printOperand(MI, 1, O); + return; + break; + case 5: + // AddiuSpImm16, Bimm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 6: + // Bteqz16, Btnez16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 7: + // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... + printOperand(MI, 0, O); + return; + break; + case 8: + // FCMP_D32, FCMP_D32_MM, FCMP_D64 + SStream_concat0(O, ".d\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 9: + // FCMP_S32, FCMP_S32_MM + SStream_concat0(O, ".s\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 10: + // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... + SStream_concat0(O, "["); + break; + case 11: + // Jal16 + SStream_concat0(O, "\n\tnop"); + return; + break; + case 12: + // JalB16 + SStream_concat0(O, "\t# branch\n\tnop"); + return; + break; + case 13: + // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM + printMemOperand(MI, 1, O); + return; + break; + case 14: + // LwConstant32 + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand(MI, 1, O); + SStream_concat0(O, "\n2:"); + return; + break; + case 15: + // SC, SCD, SCD_R6, SC_MM, SC_R6 + printMemOperand(MI, 2, O); + return; + break; + case 16: + // SelBeqZ, SelBneZ + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 2 encoded into 4 bits for 12 unique commands. + //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); + switch ((Bits >> 23) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... + printOperand(MI, 1, O); + break; + case 1: + // ADDIUS5_MM, DAHI, DATI + return; + break; + case 2: + // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... + printOperand(MI, 2, O); + break; + case 3: + // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM + printMemOperandEA(MI, 1, O); + return; + break; + case 4: + // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... + printUnsignedImm(MI, 1, O); + break; + case 5: + // INSERT_B, INSERT_D, INSERT_H, INSERT_W + printUnsignedImm(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); + return; + break; + case 6: + // INSVE_B, INSVE_D, INSVE_H, INSVE_W + printUnsignedImm(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat0(O, "["); + printUnsignedImm(MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 7: + // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... + printMemOperand(MI, 1, O); + return; + break; + case 8: + // MOVEP_MM + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 9: + // MultRxRyRz16, MultuRxRyRz16 + SStream_concat0(O, "\n\tmflo\t"); + printOperand(MI, 0, O); + return; + break; + case 10: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + printOperand(MI, 4, O); + break; + case 11: + // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... + SStream_concat0(O, "\n\tmove\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", $t8"); + return; + break; + } + + + // Fragment 3 encoded into 4 bits for 15 unique commands. + //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); + switch ((Bits >> 27) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU... + return; + break; + case 1: + // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... + SStream_concat0(O, ", "); + break; + case 2: + // AddiuRxRxImm16, LwRxPcTcp16 + SStream_concat0(O, "\t# 16 bit inst"); + return; + break; + case 3: + // BeqzRxImm16, BnezRxImm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 4: + // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... + SStream_concat0(O, "\n\tbteqz\t"); + printOperand(MI, 2, O); + return; + break; + case 5: + // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... + SStream_concat0(O, "\n\tbtnez\t"); + printOperand(MI, 2, O); + return; + break; + case 6: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... + SStream_concat0(O, "["); + break; + case 7: + // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 + SStream_concat0(O, " \t# 16 bit inst"); + return; + break; + case 8: + // DSLL64_32 + SStream_concat0(O, ", 32"); + return; + break; + case 9: + // GotPrologue16 + SStream_concat0(O, "\n\taddiu\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 3, O); + SStream_concat0(O, "\n "); + return; + break; + case 10: + // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... + SStream_concat0(O, "("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 11: + // LwRxSpImmX16, SwRxSpImmX16 + SStream_concat0(O, " ( "); + printOperand(MI, 1, O); + SStream_concat0(O, " ); "); + return; + break; + case 12: + // SLL64_32, SLL64_64 + SStream_concat0(O, ", 0"); + return; + break; + case 13: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 14: + // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + } + + + // Fragment 4 encoded into 3 bits for 5 unique commands. + //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); + switch ((Bits >> 31) & 7) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... + printOperand(MI, 2, O); + break; + case 1: + // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... + printUnsignedImm8(MI, 2, O); + break; + case 2: + // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... + printUnsignedImm(MI, 2, O); + break; + case 3: + // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... + printUnsignedImm8(MI, 3, O); + break; + case 4: + // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... + printOperand(MI, 3, O); + break; + } + + + // Fragment 5 encoded into 2 bits for 3 unique commands. + //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); + switch ((Bits >> 34) & 3) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... + return; + break; + case 1: + // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... + SStream_concat0(O, ", "); + break; + case 2: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... + SStream_concat0(O, "]"); + return; + break; + } + + + // Fragment 6 encoded into 1 bits for 2 unique commands. + //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); + if ((Bits >> 36) & 1) { + // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... + printOperand(MI, 3, O); + return; + } else { + // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 + printUnsignedImm(MI, 3, O); + return; + } +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 394 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'w', '1', '0', 0, + /* 8 */ 'f', '2', '0', 0, + /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, + /* 25 */ 'w', '2', '0', 0, + /* 29 */ 'f', '3', '0', 0, + /* 33 */ 'w', '3', '0', 0, + /* 37 */ 'a', '0', 0, + /* 40 */ 'a', 'c', '0', 0, + /* 44 */ 'f', 'c', 'c', '0', 0, + /* 49 */ 'f', '0', 0, + /* 52 */ 'k', '0', 0, + /* 55 */ 'm', 'p', 'l', '0', 0, + /* 60 */ 'p', '0', 0, + /* 63 */ 's', '0', 0, + /* 66 */ 't', '0', 0, + /* 69 */ 'v', '0', 0, + /* 72 */ 'w', '0', 0, + /* 75 */ 'f', '1', '1', 0, + /* 79 */ 'w', '1', '1', 0, + /* 83 */ 'f', '2', '1', 0, + /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, + /* 100 */ 'w', '2', '1', 0, + /* 104 */ 'f', '3', '1', 0, + /* 108 */ 'w', '3', '1', 0, + /* 112 */ 'a', '1', 0, + /* 115 */ 'a', 'c', '1', 0, + /* 119 */ 'f', 'c', 'c', '1', 0, + /* 124 */ 'f', '1', 0, + /* 127 */ 'k', '1', 0, + /* 130 */ 'm', 'p', 'l', '1', 0, + /* 135 */ 'p', '1', 0, + /* 138 */ 's', '1', 0, + /* 141 */ 't', '1', 0, + /* 144 */ 'v', '1', 0, + /* 147 */ 'w', '1', 0, + /* 150 */ 'f', '1', '2', 0, + /* 154 */ 'w', '1', '2', 0, + /* 158 */ 'f', '2', '2', 0, + /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, + /* 175 */ 'w', '2', '2', 0, + /* 179 */ 'a', '2', 0, + /* 182 */ 'a', 'c', '2', 0, + /* 186 */ 'f', 'c', 'c', '2', 0, + /* 191 */ 'f', '2', 0, + /* 194 */ 'm', 'p', 'l', '2', 0, + /* 199 */ 'p', '2', 0, + /* 202 */ 's', '2', 0, + /* 205 */ 't', '2', 0, + /* 208 */ 'w', '2', 0, + /* 211 */ 'f', '1', '3', 0, + /* 215 */ 'w', '1', '3', 0, + /* 219 */ 'f', '2', '3', 0, + /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, + /* 236 */ 'w', '2', '3', 0, + /* 240 */ 'a', '3', 0, + /* 243 */ 'a', 'c', '3', 0, + /* 247 */ 'f', 'c', 'c', '3', 0, + /* 252 */ 'f', '3', 0, + /* 255 */ 's', '3', 0, + /* 258 */ 't', '3', 0, + /* 261 */ 'w', '3', 0, + /* 264 */ 'f', '1', '4', 0, + /* 268 */ 'w', '1', '4', 0, + /* 272 */ 'f', '2', '4', 0, + /* 276 */ 'w', '2', '4', 0, + /* 280 */ 'f', 'c', 'c', '4', 0, + /* 285 */ 'f', '4', 0, + /* 288 */ 's', '4', 0, + /* 291 */ 't', '4', 0, + /* 294 */ 'w', '4', 0, + /* 297 */ 'f', '1', '5', 0, + /* 301 */ 'w', '1', '5', 0, + /* 305 */ 'f', '2', '5', 0, + /* 309 */ 'w', '2', '5', 0, + /* 313 */ 'f', 'c', 'c', '5', 0, + /* 318 */ 'f', '5', 0, + /* 321 */ 's', '5', 0, + /* 324 */ 't', '5', 0, + /* 327 */ 'w', '5', 0, + /* 330 */ 'f', '1', '6', 0, + /* 334 */ 'w', '1', '6', 0, + /* 338 */ 'f', '2', '6', 0, + /* 342 */ 'w', '2', '6', 0, + /* 346 */ 'f', 'c', 'c', '6', 0, + /* 351 */ 'f', '6', 0, + /* 354 */ 's', '6', 0, + /* 357 */ 't', '6', 0, + /* 360 */ 'w', '6', 0, + /* 363 */ 'f', '1', '7', 0, + /* 367 */ 'w', '1', '7', 0, + /* 371 */ 'f', '2', '7', 0, + /* 375 */ 'w', '2', '7', 0, + /* 379 */ 'f', 'c', 'c', '7', 0, + /* 384 */ 'f', '7', 0, + /* 387 */ 's', '7', 0, + /* 390 */ 't', '7', 0, + /* 393 */ 'w', '7', 0, + /* 396 */ 'f', '1', '8', 0, + /* 400 */ 'w', '1', '8', 0, + /* 404 */ 'f', '2', '8', 0, + /* 408 */ 'w', '2', '8', 0, + /* 412 */ 'f', '8', 0, + /* 415 */ 't', '8', 0, + /* 418 */ 'w', '8', 0, + /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, + /* 437 */ 'f', '1', '9', 0, + /* 441 */ 'w', '1', '9', 0, + /* 445 */ 'f', '2', '9', 0, + /* 449 */ 'w', '2', '9', 0, + /* 453 */ 'f', '9', 0, + /* 456 */ 't', '9', 0, + /* 459 */ 'w', '9', 0, + /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, + /* 469 */ 'r', 'a', 0, + /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, + /* 479 */ 'p', 'c', 0, + /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, + /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, + /* 502 */ 'h', 'i', 0, + /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, + /* 516 */ 'l', 'o', 0, + /* 519 */ 'z', 'e', 'r', 'o', 0, + /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, + /* 539 */ 'f', 'p', 0, + /* 542 */ 'g', 'p', 0, + /* 545 */ 's', 'p', 0, + /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, + /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, + /* 565 */ 'a', 't', 0, + /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, + /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, + 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, + 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, + 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, + 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, + 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, + 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, + 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, + 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, + 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, + 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, + 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, + 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, + 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, + 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, + 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, + 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, + 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, + 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, + 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, + 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, + 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, + 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, + 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, + 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, + 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, + 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, + 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, + 144, + }; + + //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); + //int i; + //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("-------------------------\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) +{ +} + +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +{ + #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + const char *AsmString; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case Mips_ADDu: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { + // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) + AsmString = "move $\x01, $\x02"; + break; + } + return NULL; + case Mips_BC0F: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC0F CC0, brtarget:$offset) + AsmString = "bc0f $\x02"; + break; + } + return NULL; + case Mips_BC0FL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC0FL CC0, brtarget:$offset) + AsmString = "bc0fl $\x02"; + break; + } + return NULL; + case Mips_BC0T: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC0T CC0, brtarget:$offset) + AsmString = "bc0t $\x02"; + break; + } + return NULL; + case Mips_BC0TL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC0TL CC0, brtarget:$offset) + AsmString = "bc0tl $\x02"; + break; + } + return NULL; + case Mips_BC1F: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { + // (BC1F FCC0, brtarget:$offset) + AsmString = "bc1f $\x02"; + break; + } + return NULL; + case Mips_BC1FL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { + // (BC1FL FCC0, brtarget:$offset) + AsmString = "bc1fl $\x02"; + break; + } + return NULL; + case Mips_BC1T: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { + // (BC1T FCC0, brtarget:$offset) + AsmString = "bc1t $\x02"; + break; + } + return NULL; + case Mips_BC1TL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { + // (BC1TL FCC0, brtarget:$offset) + AsmString = "bc1tl $\x02"; + break; + } + return NULL; + case Mips_BC2F: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC2F CC0, brtarget:$offset) + AsmString = "bc2f $\x02"; + break; + } + return NULL; + case Mips_BC2FL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC2FL CC0, brtarget:$offset) + AsmString = "bc2fl $\x02"; + break; + } + return NULL; + case Mips_BC2T: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC2T CC0, brtarget:$offset) + AsmString = "bc2t $\x02"; + break; + } + return NULL; + case Mips_BC2TL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC2TL CC0, brtarget:$offset) + AsmString = "bc2tl $\x02"; + break; + } + return NULL; + case Mips_BC3F: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC3F CC0, brtarget:$offset) + AsmString = "bc3f $\x02"; + break; + } + return NULL; + case Mips_BC3FL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC3FL CC0, brtarget:$offset) + AsmString = "bc3fl $\x02"; + break; + } + return NULL; + case Mips_BC3T: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC3T CC0, brtarget:$offset) + AsmString = "bc3t $\x02"; + break; + } + return NULL; + case Mips_BC3TL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { + // (BC3TL CC0, brtarget:$offset) + AsmString = "bc3tl $\x02"; + break; + } + return NULL; + case Mips_BREAK: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BREAK 0, 0) + AsmString = "break"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BREAK uimm10:$imm, 0) + AsmString = "break $\x01"; + break; + } + return NULL; + case Mips_DADDu: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { + // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) + AsmString = "move $\x01, $\x02"; + break; + } + return NULL; + case Mips_DI: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { + // (DI ZERO) + AsmString = "di"; + break; + } + return NULL; + case Mips_EI: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { + // (EI ZERO) + AsmString = "ei"; + break; + } + return NULL; + case Mips_JALR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { + // (JALR ZERO, GPR32Opnd:$rs) + AsmString = "jr $\x02"; + break; + } + return NULL; + case Mips_JALR64: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { + // (JALR64 ZERO_64, GPR64Opnd:$rs) + AsmString = "jr $\x02"; + break; + } + return NULL; + case Mips_JALR_HB: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { + // (JALR_HB RA, GPR32Opnd:$rs) + AsmString = "jalr.hb $\x02"; + break; + } + return NULL; + case Mips_MOVE16_MM: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) { + // (MOVE16_MM ZERO, ZERO) + AsmString = "nop"; + break; + } + return NULL; + case Mips_SDBBP: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (SDBBP 0) + AsmString = "sdbbp"; + break; + } + return NULL; + case Mips_SDBBP_R6: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (SDBBP_R6 0) + AsmString = "sdbbp"; + break; + } + return NULL; + case Mips_SLL: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (SLL ZERO, ZERO, 0) + AsmString = "nop"; + break; + } + return NULL; + case Mips_SLL_MM: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (SLL_MM ZERO, ZERO, 0) + AsmString = "nop"; + break; + } + return NULL; + case Mips_SUB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) + AsmString = "neg $\x01, $\x03"; + break; + } + return NULL; + case Mips_SUBu: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) + AsmString = "negu $\x01, $\x03"; + break; + } + return NULL; + case Mips_SYNC: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (SYNC 0) + AsmString = "sync"; + break; + } + return NULL; + case Mips_SYSCALL: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (SYSCALL 0) + AsmString = "syscall"; + break; + } + return NULL; + case Mips_TEQ: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "teq $\x01, $\x02"; + break; + } + return NULL; + case Mips_TGE: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "tge $\x01, $\x02"; + break; + } + return NULL; + case Mips_TGEU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "tgeu $\x01, $\x02"; + break; + } + return NULL; + case Mips_TLT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "tlt $\x01, $\x02"; + break; + } + return NULL; + case Mips_TLTU: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "tltu $\x01, $\x02"; + break; + } + return NULL; + case Mips_TNE: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) + AsmString = "tne $\x01, $\x02"; + break; + } + return NULL; + case Mips_WAIT_MM: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (WAIT_MM 0) + AsmString = "wait"; + break; + } + return NULL; + } + + tmp = cs_strdup(AsmString); + AsmMnem = tmp; + for(AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + return tmp; +} + +#endif // PRINT_ALIAS_INSTR diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/Mips/MipsGenDisassemblerTables.inc new file mode 100644 index 0000000..5013293 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsGenDisassemblerTables.inc @@ -0,0 +1,6942 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * Mips Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static uint8_t DecoderTableCOP3_32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 +/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 +/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 +/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 +/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 +/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 +/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 +/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 +/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 +/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 +/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 +/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 +/* 51 */ MCD_OPC_Fail, + 0 +}; + +static uint8_t DecoderTableMicroMips16[] = { +/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 +/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 +/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 +/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM +/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 +/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 +/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM +/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 +/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 +/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM +/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 +/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 +/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM +/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 +/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 +/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 +/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM +/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 +/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 +/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM +/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 +/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 +/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM +/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 +/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 +/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM +/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 +/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 +/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 +/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM +/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 +/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 +/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM +/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 +/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 +/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM +/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 +/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 +/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM +/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 +/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 +/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM +/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 +/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 +/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM +/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 +/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 +/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 +/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM +/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 +/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 +/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM +/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 +/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 +/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 +/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM +/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 +/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 +/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM +/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 +/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 +/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 +/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM +/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 +/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 +/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 +/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM +/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 +/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 +/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 +/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM +/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 +/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 +/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 +/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM +/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 +/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 +/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 +/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP +/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 +/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 +/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM +/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 +/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 +/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 +/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM +/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 +/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 +/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM +/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 +/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 +/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM +/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 +/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 +/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM +/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 +/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 +/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 +/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM +/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 +/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 +/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM +/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 +/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 +/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 +/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM +/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 +/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 +/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM +/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 +/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 +/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM +/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 +/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 +/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM +/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 +/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 +/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM +/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 +/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 +/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM +/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 +/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 +/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM +/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 +/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 +/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM +/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 +/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 +/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM +/* 549 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMicroMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 +/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 +/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 +/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... +/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 +/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 +/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM +/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 +/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 +/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM +/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 +/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 +/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM +/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 +/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM +/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 +/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 +/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM +/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 +/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 +/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM +/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 +/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 +/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM +/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 +/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 +/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM +/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 +/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 +/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM +/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 +/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 +/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 +/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM +/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 +/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 +/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM +/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 +/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 +/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM +/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 +/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 +/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM +/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 +/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 +/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM +/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 +/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 +/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM +/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 +/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 +/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM +/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 +/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 +/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM +/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 +/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 +/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM +/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 +/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 +/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM +/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 +/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 +/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM +/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 +/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 +/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM +/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 +/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 +/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM +/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 +/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 +/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM +/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 +/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 +/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM +/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 +/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 +/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 +/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM +/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 +/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 +/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM +/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 +/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 +/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM +/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 +/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 +/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM +/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 +/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... +/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 +/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 +/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM +/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 +/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 +/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM +/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 +/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 +/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 +/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 +/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM +/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 +/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 +/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 +/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM +/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 +/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 +/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 +/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM +/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 +/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 +/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 +/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM +/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 +/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 +/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM +/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 +/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 +/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 +/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM +/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 +/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 +/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 +/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM +/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 +/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 +/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM +/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 +/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 +/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 +/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 +/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM +/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 +/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 +/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 +/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM +/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 +/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 +/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM +/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 +/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 +/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM +/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 +/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 +/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 +/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM +/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 +/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 +/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM +/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 +/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 +/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM +/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 +/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 +/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM +/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 +/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 +/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM +/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 +/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 +/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM +/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 +/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 +/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM +/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 +/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 +/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM +/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 +/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 +/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM +/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 +/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 +/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM +/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 +/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 +/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM +/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 +/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 +/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM +/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 +/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 +/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM +/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 +/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 +/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM +/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 +/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 +/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 +/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 +/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM +/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 +/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 +/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM +/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 +/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 +/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM +/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 +/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 +/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM +/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 +/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 +/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 +/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 +/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM +/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 +/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 +/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 +/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM +/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 +/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 +/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 +/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM +/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 +/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 +/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 +/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM +/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 +/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 +/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 +/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 +/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM +/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 +/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM +/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 +/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 +/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM +/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 +/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 +/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM +/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 +/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 +/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM +/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 +/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 +/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM +/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 +/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 +/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM +/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 +/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 +/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 +/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM +/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 +/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 +/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM +/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 +/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 +/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM +/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 +/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 +/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM +/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 +/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 +/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM +/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 +/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 +/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM +/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 +/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 +/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM +/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 +/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 +/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM +/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 +/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 +/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM +/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 +/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 +/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 +/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM +/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 +/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 +/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM +/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 +/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 +/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM +/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 +/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 +/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM +/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 +/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 +/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM +/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 +/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 +/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM +/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 +/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 +/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM +/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 +/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 +/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM +/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 +/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 +/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM +/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 +/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 +/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM +/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 +/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 +/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM +/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 +/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 +/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM +/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 +/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 +/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM +/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 +/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 +/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM +/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 +/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 +/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM +/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 +/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 +/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM +/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 +/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 +/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM +/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 +/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 +/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM +/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 +/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... +/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 +/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 +/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM +/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 +/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 +/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM +/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 +/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 +/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 +/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM +/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 +/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 +/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM +/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 +/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 +/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM +/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 +/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 +/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM +/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 +/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 +/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM +/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 +/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 +/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM +/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 +/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 +/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM +/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 +/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 +/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM +/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 +/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 +/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM +/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 +/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 +/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM +/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 +/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 +/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM +/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 +/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 +/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM +/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 +/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 +/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM +/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 +/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 +/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM +/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 +/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 +/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM +/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 +/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 +/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM +/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 +/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 +/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM +/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 +/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 +/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM +/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 +/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 +/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM +/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 +/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 +/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM +/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 +/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 +/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM +/* 1638 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 +/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 +/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 +/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 +/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 +/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP +/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 +/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 +/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB +/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 +/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 +/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE +/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 +/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL +/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 +/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 +/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 +/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 +/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I +/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 +/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 +/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 +/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I +/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 +/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 +/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 +/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL +/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 +/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 +/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR +/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 +/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 +/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 +/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA +/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 +/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 +/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 +/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV +/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 +/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 +/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 +/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA +/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 +/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 +/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 +/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV +/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 +/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 +/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV +/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 +/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 +/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 +/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV +/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 +/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... +/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 +/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 +/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR +/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 +/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 +/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB +/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 +/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 +/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 +/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 +/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR +/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 +/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 +/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 +/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB +/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 +/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 +/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 +/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I +/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 +/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 +/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 +/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I +/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 +/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 +/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL +/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 +/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 +/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK +/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 +/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 +/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC +/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 +/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 +/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 +/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 +/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 +/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 +/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI +/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 +/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP +/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 +/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 +/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... +/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 +/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 +/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 +/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI +/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 +/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP +/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 +/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 +/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 +/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 +/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 +/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 +/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO +/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 +/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP +/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 +/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 +/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... +/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 +/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 +/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 +/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO +/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 +/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP +/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 +/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 +/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 +/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA +/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 +/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 +/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 +/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 +/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 +/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT +/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 +/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP +/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 +/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 +/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 +/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 +/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 +/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu +/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 +/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP +/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 +/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 +/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 +/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV +/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 +/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 +/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 +/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV +/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 +/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 +/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 +/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD +/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 +/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 +/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 +/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu +/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 +/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 +/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 +/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB +/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 +/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 +/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 +/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu +/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 +/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 +/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 +/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND +/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 +/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 +/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 +/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR +/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 +/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 +/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 +/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR +/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 +/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 +/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 +/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR +/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 +/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 +/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 +/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT +/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 +/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 +/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 +/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu +/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 +/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 +/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE +/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 +/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 +/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU +/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 +/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 +/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT +/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 +/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 +/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU +/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 +/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 +/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ +/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 +/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 +/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE +/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 +/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 +/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 +/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ +/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 +/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 +/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ +/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 +/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 +/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL +/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 +/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 +/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL +/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 +/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 +/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI +/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 +/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 +/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU +/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 +/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 +/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI +/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 +/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 +/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU +/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 +/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 +/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI +/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 +/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 +/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI +/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 +/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 +/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL +/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 +/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 +/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL +/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 +/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 +/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL +/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 +/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 +/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL +/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 +/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 +/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 +/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 +/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 +/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 +/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI +/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 +/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 +/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J +/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 +/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 +/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL +/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 +/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 +/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ +/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 +/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 +/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE +/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 +/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 +/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 +/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ +/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 +/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 +/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 +/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ +/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 +/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 +/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi +/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 +/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 +/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu +/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 +/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 +/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi +/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 +/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 +/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu +/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 +/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 +/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi +/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 +/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 +/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi +/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 +/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 +/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi +/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 +/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 +/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 +/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi +/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 +/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 +/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 +/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 +/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 +/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 +/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 +/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 +/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 +/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 +/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 +/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 +/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F +/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 +/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 +/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T +/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 +/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 +/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL +/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 +/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 +/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL +/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 +/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... +/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 +/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 +/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI +/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 +/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 +/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI +/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 +/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... +/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 +/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 +/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR +/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 +/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 +/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI +/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 +/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 +/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR +/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 +/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 +/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP +/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 +/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 +/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET +/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 +/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 +/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET +/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 +/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 +/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT +/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 +/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 +/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 +/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 +/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 +/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 +/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 +/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 +/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 +/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 +/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 +/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 +/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 +/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 +/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 +/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 +/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 +/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 +/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 +/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 +/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 +/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 +/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 +/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 +/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 +/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 +/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 +/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 +/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 +/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 +/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 +/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 +/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 +/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 +/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 +/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 +/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F +/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 +/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 +/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T +/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 +/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 +/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL +/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 +/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 +/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL +/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 +/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 +/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V +/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 +/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 +/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V +/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 +/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 +/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 +/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S +/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 +/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 +/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S +/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 +/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 +/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S +/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 +/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 +/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S +/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 +/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 +/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 +/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S +/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 +/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 +/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 +/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S +/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 +/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 +/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 +/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S +/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 +/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 +/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 +/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S +/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 +/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 +/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 +/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S +/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 +/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 +/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 +/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S +/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 +/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 +/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 +/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S +/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 +/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 +/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 +/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S +/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 +/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 +/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 +/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S +/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 +/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 +/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S +/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 +/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 +/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S +/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 +/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 +/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S +/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 +/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 +/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 +/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S +/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 +/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 +/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 +/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S +/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 +/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 +/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 +/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S +/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 +/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 +/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 +/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S +/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 +/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 +/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 +/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S +/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 +/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 +/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 +/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S +/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 +/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 +/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 +/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S +/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 +/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 +/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 +/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S +/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 +/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 +/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 +/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S +/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 +/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 +/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 +/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S +/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 +/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 +/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 +/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S +/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 +/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 +/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 +/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S +/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 +/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 +/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 +/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S +/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 +/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 +/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 +/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S +/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 +/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 +/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 +/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S +/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 +/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 +/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 +/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S +/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 +/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 +/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 +/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S +/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 +/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 +/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 +/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S +/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 +/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 +/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 +/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S +/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 +/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 +/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 +/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 +/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 +/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 +/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 +/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 +/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 +/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 +/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 +/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 +/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 +/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 +/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 +/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 +/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 +/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 +/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 +/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 +/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 +/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 +/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 +/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 +/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 +/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 +/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 +/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 +/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 +/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 +/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 +/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 +/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 +/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 +/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 +/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 +/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 +/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 +/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 +/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 +/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 +/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 +/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 +/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 +/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 +/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 +/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 +/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 +/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 +/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 +/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 +/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 +/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 +/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 +/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 +/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 +/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 +/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 +/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 +/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 +/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 +/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 +/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 +/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 +/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 +/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 +/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 +/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 +/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 +/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 +/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 +/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 +/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 +/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 +/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 +/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 +/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 +/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 +/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 +/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 +/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 +/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 +/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 +/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 +/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 +/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 +/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 +/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 +/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 +/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 +/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 +/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 +/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 +/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 +/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 +/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 +/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 +/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 +/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 +/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 +/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 +/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 +/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 +/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 +/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 +/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 +/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 +/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 +/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 +/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 +/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 +/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 +/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 +/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 +/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 +/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 +/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 +/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 +/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 +/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 +/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 +/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 +/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 +/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 +/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 +/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 +/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 +/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 +/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 +/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 +/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 +/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 +/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 +/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 +/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 +/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 +/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 +/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 +/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W +/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 +/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 +/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 +/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W +/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 +/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 +/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B +/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 +/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 +/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H +/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 +/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 +/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W +/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 +/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 +/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D +/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 +/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 +/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B +/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 +/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 +/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H +/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 +/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 +/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W +/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 +/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 +/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D +/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 +/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 +/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 +/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 +/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 +/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 +/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 +/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 +/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 +/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 +/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 +/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 +/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F +/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 +/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 +/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T +/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 +/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 +/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL +/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 +/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 +/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL +/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 +/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 +/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 +/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 +/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F +/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 +/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 +/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T +/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 +/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 +/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL +/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 +/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 +/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL +/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 +/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 +/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 +/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 +/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 +/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 +/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 +/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 +/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 +/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 +/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 +/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 +/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 +/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 +/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 +/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 +/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 +/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 +/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 +/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 +/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 +/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 +/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 +/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 +/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 +/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 +/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S +/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 +/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 +/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 +/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 +/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 +/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S +/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 +/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 +/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 +/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 +/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 +/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S +/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 +/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 +/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 +/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 +/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 +/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S +/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 +/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 +/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 +/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 +/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 +/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL +/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 +/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 +/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL +/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 +/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 +/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 +/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL +/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 +/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 +/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 +/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL +/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 +/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 +/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 +/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 +/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 +/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 +/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD +/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 +/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP +/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 +/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 +/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 +/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 +/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 +/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU +/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 +/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP +/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 +/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 +/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 +/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL +/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 +/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 +/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 +/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 +/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 +/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB +/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 +/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP +/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 +/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 +/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 +/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 +/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 +/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU +/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 +/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP +/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 +/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 +/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 +/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ +/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 +/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 +/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 +/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO +/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 +/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 +/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP +/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 +/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 +/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX +/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 +/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 +/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 +/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 +/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B +/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 +/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 +/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B +/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 +/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 +/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B +/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 +/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 +/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B +/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 +/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 +/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 +/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B +/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 +/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 +/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B +/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 +/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 +/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B +/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 +/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 +/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 +/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B +/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 +/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 +/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H +/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 +/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 +/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W +/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 +/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 +/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 +/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B +/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 +/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 +/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H +/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 +/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 +/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W +/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 +/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 +/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D +/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 +/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 +/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B +/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 +/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 +/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H +/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 +/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 +/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W +/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 +/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 +/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D +/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 +/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 +/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B +/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 +/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 +/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H +/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 +/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 +/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W +/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 +/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 +/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D +/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 +/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 +/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B +/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 +/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 +/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H +/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 +/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 +/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W +/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 +/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 +/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D +/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 +/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 +/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B +/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 +/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 +/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H +/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 +/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 +/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W +/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 +/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 +/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D +/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 +/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 +/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B +/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 +/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 +/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H +/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 +/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 +/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W +/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 +/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 +/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D +/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 +/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 +/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 +/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B +/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 +/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 +/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H +/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 +/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 +/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W +/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 +/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 +/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D +/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 +/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 +/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B +/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 +/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 +/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H +/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 +/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 +/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W +/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 +/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 +/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D +/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 +/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 +/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B +/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 +/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 +/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H +/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 +/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 +/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W +/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 +/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 +/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D +/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 +/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 +/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B +/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 +/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 +/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H +/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 +/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 +/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W +/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 +/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 +/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D +/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 +/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 +/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B +/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 +/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 +/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H +/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 +/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 +/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W +/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 +/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 +/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D +/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 +/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 +/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B +/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 +/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 +/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H +/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 +/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 +/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W +/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 +/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 +/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D +/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 +/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 +/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 +/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D +/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 +/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 +/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 +/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W +/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 +/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 +/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 +/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H +/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 +/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 +/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 +/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B +/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 +/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 +/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D +/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 +/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 +/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 +/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W +/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 +/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 +/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 +/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H +/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 +/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 +/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 +/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B +/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 +/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 +/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D +/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 +/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 +/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 +/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W +/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 +/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 +/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 +/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H +/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 +/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 +/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 +/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B +/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 +/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 +/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D +/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 +/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 +/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 +/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W +/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 +/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 +/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 +/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H +/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 +/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 +/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 +/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B +/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 +/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 +/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D +/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 +/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 +/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 +/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W +/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 +/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 +/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 +/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H +/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 +/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 +/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 +/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B +/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 +/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 +/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D +/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 +/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 +/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 +/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W +/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 +/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 +/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 +/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H +/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 +/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 +/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 +/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B +/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 +/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 +/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D +/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 +/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 +/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 +/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W +/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 +/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 +/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 +/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H +/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 +/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 +/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 +/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B +/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 +/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 +/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D +/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 +/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 +/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 +/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W +/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 +/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 +/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 +/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H +/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 +/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 +/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 +/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B +/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 +/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 +/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 +/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D +/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 +/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 +/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 +/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W +/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 +/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 +/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 +/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H +/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 +/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 +/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 +/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B +/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 +/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 +/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D +/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 +/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 +/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 +/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W +/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 +/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 +/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 +/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H +/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 +/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 +/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 +/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B +/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 +/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 +/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D +/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 +/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 +/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 +/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W +/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 +/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 +/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 +/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H +/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 +/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 +/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 +/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B +/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 +/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 +/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D +/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 +/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 +/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 +/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W +/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 +/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 +/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 +/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H +/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 +/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 +/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 +/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B +/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 +/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 +/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 +/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B +/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 +/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 +/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H +/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 +/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 +/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W +/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 +/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 +/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D +/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 +/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 +/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B +/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 +/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 +/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H +/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 +/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 +/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W +/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 +/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 +/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D +/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 +/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 +/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B +/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 +/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 +/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H +/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 +/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 +/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W +/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 +/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 +/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D +/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 +/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 +/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B +/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 +/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 +/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H +/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 +/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 +/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W +/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 +/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 +/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D +/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 +/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 +/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B +/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 +/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 +/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H +/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 +/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 +/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W +/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 +/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 +/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D +/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 +/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 +/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B +/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 +/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 +/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H +/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 +/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 +/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W +/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 +/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 +/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D +/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 +/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 +/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B +/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 +/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 +/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H +/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 +/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 +/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W +/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 +/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 +/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D +/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 +/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 +/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B +/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 +/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 +/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H +/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 +/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 +/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W +/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 +/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 +/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D +/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 +/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 +/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 +/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B +/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 +/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 +/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H +/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 +/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 +/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W +/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 +/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 +/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D +/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 +/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 +/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B +/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 +/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 +/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H +/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 +/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 +/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W +/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 +/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 +/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D +/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 +/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 +/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B +/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 +/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 +/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H +/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 +/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 +/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W +/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 +/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 +/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D +/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 +/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 +/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B +/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 +/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 +/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H +/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 +/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 +/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W +/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 +/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 +/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D +/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 +/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 +/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B +/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 +/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 +/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H +/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 +/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 +/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W +/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 +/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 +/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D +/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 +/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 +/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B +/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 +/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 +/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H +/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 +/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 +/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W +/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 +/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 +/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D +/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 +/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 +/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B +/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 +/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 +/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H +/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 +/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 +/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W +/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 +/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 +/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D +/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 +/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 +/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B +/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 +/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 +/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H +/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 +/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 +/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W +/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 +/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 +/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D +/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 +/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 +/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 +/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B +/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 +/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 +/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H +/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 +/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 +/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W +/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 +/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 +/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D +/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 +/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 +/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B +/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 +/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 +/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H +/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 +/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 +/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W +/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 +/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 +/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D +/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 +/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 +/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B +/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 +/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 +/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H +/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 +/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 +/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W +/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 +/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 +/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D +/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 +/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 +/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B +/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 +/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 +/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H +/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 +/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 +/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W +/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 +/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 +/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D +/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 +/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 +/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B +/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 +/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 +/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H +/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 +/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 +/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W +/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 +/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 +/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D +/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 +/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 +/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 +/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B +/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 +/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 +/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H +/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 +/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 +/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W +/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 +/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 +/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D +/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 +/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 +/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B +/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 +/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 +/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H +/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 +/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 +/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W +/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 +/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 +/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D +/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 +/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 +/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B +/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 +/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 +/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H +/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 +/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 +/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W +/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 +/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 +/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D +/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 +/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 +/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B +/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 +/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 +/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H +/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 +/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 +/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W +/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 +/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 +/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D +/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 +/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 +/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B +/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 +/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 +/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H +/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 +/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 +/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W +/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 +/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 +/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D +/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 +/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 +/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B +/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 +/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 +/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H +/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 +/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 +/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W +/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 +/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 +/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D +/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 +/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 +/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B +/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 +/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 +/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H +/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 +/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 +/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W +/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 +/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 +/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D +/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 +/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 +/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B +/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 +/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 +/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H +/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 +/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 +/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W +/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 +/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 +/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D +/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 +/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 +/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 +/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B +/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 +/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 +/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H +/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 +/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 +/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W +/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 +/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 +/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D +/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 +/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 +/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B +/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 +/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 +/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H +/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 +/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 +/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W +/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 +/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 +/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D +/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 +/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 +/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B +/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 +/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 +/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H +/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 +/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 +/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W +/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 +/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 +/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D +/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 +/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 +/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B +/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 +/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 +/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H +/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 +/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 +/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W +/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 +/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 +/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D +/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 +/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 +/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B +/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 +/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 +/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H +/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 +/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 +/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W +/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 +/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 +/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D +/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 +/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 +/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B +/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 +/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 +/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H +/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 +/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 +/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W +/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 +/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 +/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D +/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 +/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 +/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 +/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B +/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 +/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 +/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H +/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 +/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 +/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W +/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 +/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 +/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D +/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 +/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 +/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B +/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 +/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 +/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H +/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 +/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 +/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W +/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 +/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 +/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D +/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 +/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 +/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B +/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 +/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 +/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H +/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 +/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 +/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W +/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 +/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 +/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D +/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 +/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 +/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B +/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 +/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 +/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H +/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 +/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 +/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W +/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 +/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 +/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D +/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 +/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 +/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B +/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 +/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 +/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H +/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 +/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 +/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W +/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 +/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 +/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D +/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 +/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 +/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B +/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 +/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 +/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H +/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 +/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 +/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W +/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 +/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 +/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D +/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 +/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 +/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B +/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 +/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 +/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H +/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 +/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 +/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W +/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 +/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 +/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D +/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 +/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 +/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 +/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H +/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 +/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 +/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W +/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 +/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 +/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D +/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 +/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 +/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H +/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 +/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 +/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W +/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 +/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 +/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D +/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 +/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 +/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H +/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 +/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 +/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W +/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 +/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 +/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D +/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 +/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 +/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H +/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 +/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 +/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W +/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 +/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 +/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D +/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 +/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 +/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H +/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 +/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 +/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W +/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 +/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 +/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D +/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 +/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 +/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H +/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 +/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 +/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W +/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 +/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 +/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D +/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 +/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 +/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 +/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B +/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 +/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 +/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H +/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 +/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 +/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W +/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 +/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 +/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D +/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 +/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 +/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B +/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 +/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 +/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H +/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 +/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 +/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W +/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 +/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 +/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D +/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 +/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 +/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B +/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 +/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 +/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H +/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 +/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 +/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W +/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 +/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 +/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D +/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 +/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 +/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B +/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 +/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 +/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H +/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 +/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 +/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W +/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 +/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 +/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D +/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 +/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 +/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B +/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 +/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 +/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H +/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 +/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 +/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W +/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 +/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 +/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D +/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 +/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 +/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B +/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 +/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 +/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H +/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 +/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 +/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W +/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 +/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 +/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D +/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 +/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 +/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B +/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 +/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 +/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H +/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 +/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 +/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W +/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 +/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 +/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D +/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 +/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 +/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B +/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 +/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 +/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H +/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 +/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 +/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W +/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 +/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 +/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D +/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 +/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 +/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 +/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B +/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 +/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 +/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H +/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 +/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 +/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W +/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 +/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 +/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D +/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 +/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 +/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B +/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 +/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 +/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H +/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 +/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 +/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W +/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 +/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 +/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D +/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 +/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 +/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B +/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 +/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 +/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H +/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 +/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 +/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W +/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 +/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 +/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D +/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 +/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 +/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H +/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 +/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 +/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W +/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 +/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 +/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D +/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 +/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 +/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H +/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 +/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 +/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W +/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 +/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 +/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D +/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 +/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 +/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H +/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 +/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 +/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W +/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 +/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 +/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D +/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 +/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 +/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H +/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 +/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 +/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W +/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 +/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 +/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D +/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 +/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... +/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 +/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 +/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B +/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 +/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 +/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 +/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H +/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 +/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 +/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 +/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W +/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 +/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 +/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 +/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D +/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 +/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 +/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 +/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA +/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 +/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 +/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B +/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 +/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 +/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 +/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H +/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 +/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 +/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 +/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W +/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 +/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 +/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 +/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D +/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 +/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 +/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 +/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA +/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 +/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 +/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B +/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 +/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 +/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 +/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H +/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 +/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 +/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 +/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W +/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 +/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 +/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 +/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D +/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 +/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 +/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 +/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V +/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 +/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 +/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B +/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 +/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 +/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 +/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H +/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 +/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 +/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 +/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W +/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 +/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 +/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 +/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D +/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 +/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 +/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B +/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 +/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 +/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 +/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H +/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 +/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 +/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 +/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W +/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 +/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 +/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 +/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D +/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 +/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 +/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B +/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 +/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 +/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 +/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H +/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 +/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... +/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 +/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 +/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W +/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 +/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 +/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 +/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D +/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 +/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 +/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 +/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W +/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 +/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 +/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D +/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 +/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 +/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W +/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 +/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 +/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D +/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 +/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 +/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W +/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 +/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 +/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D +/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 +/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 +/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W +/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 +/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 +/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D +/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 +/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 +/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W +/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 +/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 +/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D +/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 +/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 +/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W +/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 +/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 +/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D +/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 +/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 +/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W +/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 +/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 +/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D +/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 +/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 +/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W +/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 +/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 +/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D +/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 +/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 +/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W +/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 +/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 +/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D +/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 +/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 +/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W +/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 +/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 +/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D +/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 +/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 +/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W +/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 +/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 +/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D +/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 +/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 +/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W +/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 +/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 +/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D +/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 +/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 +/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W +/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 +/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 +/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D +/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 +/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 +/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W +/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 +/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 +/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D +/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 +/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 +/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W +/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 +/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 +/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D +/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 +/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 +/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W +/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 +/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 +/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D +/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 +/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 +/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 +/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W +/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 +/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 +/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D +/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 +/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 +/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W +/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 +/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 +/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D +/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 +/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 +/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W +/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 +/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 +/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D +/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 +/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 +/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W +/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 +/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 +/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D +/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 +/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 +/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W +/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 +/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 +/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D +/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 +/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 +/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W +/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 +/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 +/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D +/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 +/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 +/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W +/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 +/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 +/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D +/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 +/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 +/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H +/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 +/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 +/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W +/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 +/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 +/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H +/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 +/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 +/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W +/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 +/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 +/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W +/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 +/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 +/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D +/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 +/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 +/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W +/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 +/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 +/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D +/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 +/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 +/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W +/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 +/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 +/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D +/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 +/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 +/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W +/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 +/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 +/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D +/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 +/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 +/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 +/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W +/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 +/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 +/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D +/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 +/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 +/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W +/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 +/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 +/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D +/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 +/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 +/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W +/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 +/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 +/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D +/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 +/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 +/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H +/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 +/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 +/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W +/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 +/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 +/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H +/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 +/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 +/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W +/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 +/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 +/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H +/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 +/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 +/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W +/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 +/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 +/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W +/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 +/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 +/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D +/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 +/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 +/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W +/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 +/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 +/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D +/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 +/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 +/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W +/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 +/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 +/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D +/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 +/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 +/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H +/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 +/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 +/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W +/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 +/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 +/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H +/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 +/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 +/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W +/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 +/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 +/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H +/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 +/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 +/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W +/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 +/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 +/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 +/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V +/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 +/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 +/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V +/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 +/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 +/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V +/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 +/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 +/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V +/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 +/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 +/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V +/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 +/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 +/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V +/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 +/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 +/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V +/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 +/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 +/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 +/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B +/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 +/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 +/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H +/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 +/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 +/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W +/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 +/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 +/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D +/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 +/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 +/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B +/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 +/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 +/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H +/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 +/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 +/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W +/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 +/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 +/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D +/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 +/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 +/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B +/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 +/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 +/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H +/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 +/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 +/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W +/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 +/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 +/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D +/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 +/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 +/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B +/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 +/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 +/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H +/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 +/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 +/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W +/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 +/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 +/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D +/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 +/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 +/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 +/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W +/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 +/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 +/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D +/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 +/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 +/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W +/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 +/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 +/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D +/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 +/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 +/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W +/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 +/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 +/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D +/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 +/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 +/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W +/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 +/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 +/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D +/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 +/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 +/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W +/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 +/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 +/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D +/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 +/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 +/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W +/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 +/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 +/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D +/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 +/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 +/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W +/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 +/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 +/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D +/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 +/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 +/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W +/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 +/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 +/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D +/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 +/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 +/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W +/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 +/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 +/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D +/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 +/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 +/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W +/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 +/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 +/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D +/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 +/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 +/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W +/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 +/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 +/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D +/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 +/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 +/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W +/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 +/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 +/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D +/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 +/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 +/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W +/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 +/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 +/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D +/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 +/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 +/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W +/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 +/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 +/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D +/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 +/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 +/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W +/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 +/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 +/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D +/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 +/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 +/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W +/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 +/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 +/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D +/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 +/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 +/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B +/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 +/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 +/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H +/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 +/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 +/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W +/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 +/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 +/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D +/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 +/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 +/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B +/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 +/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 +/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H +/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 +/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 +/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W +/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 +/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 +/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D +/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 +/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 +/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 +/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT +/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 +/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 +/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS +/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 +/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 +/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 +/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX +/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 +/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 +/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX +/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 +/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 +/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX +/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 +/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 +/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 +/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV +/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 +/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 +/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 +/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB +/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 +/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 +/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB +/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 +/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 +/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB +/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 +/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 +/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB +/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 +/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 +/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL +/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 +/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 +/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR +/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 +/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 +/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH +/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 +/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 +/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH +/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 +/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 +/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH +/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 +/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 +/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH +/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 +/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 +/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH +/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 +/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 +/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH +/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 +/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 +/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH +/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 +/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 +/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH +/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 +/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 +/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC +/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 +/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 +/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC +/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 +/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 +/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB +/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 +/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 +/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 +/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB +/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 +/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 +/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W +/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 +/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 +/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W +/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 +/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 +/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL +/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 +/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 +/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR +/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 +/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 +/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH +/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 +/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 +/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH +/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 +/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 +/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 +/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 +/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB +/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 +/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 +/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 +/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB +/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 +/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 +/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 +/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB +/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 +/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 +/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB +/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 +/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 +/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB +/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 +/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 +/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB +/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 +/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 +/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB +/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 +/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 +/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 +/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH +/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 +/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 +/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 +/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH +/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 +/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 +/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 +/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH +/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 +/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 +/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH +/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 +/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 +/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH +/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 +/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 +/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH +/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 +/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 +/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH +/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 +/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 +/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH +/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 +/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 +/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W +/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 +/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 +/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W +/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 +/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 +/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB +/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 +/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 +/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB +/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 +/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 +/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB +/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 +/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 +/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W +/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 +/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 +/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W +/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 +/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 +/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 +/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 +/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB +/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 +/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 +/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB +/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 +/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 +/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 +/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB +/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 +/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 +/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 +/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL +/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 +/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 +/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 +/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR +/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 +/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 +/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 +/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA +/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 +/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 +/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 +/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA +/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 +/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 +/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 +/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH +/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 +/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 +/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH +/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 +/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 +/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 +/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH +/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 +/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 +/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 +/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL +/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 +/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 +/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 +/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR +/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 +/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 +/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 +/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W +/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 +/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 +/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 +/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV +/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 +/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 +/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 +/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL +/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 +/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 +/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 +/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR +/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 +/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 +/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 +/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA +/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 +/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 +/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 +/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA +/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 +/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 +/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 +/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB +/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 +/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 +/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB +/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 +/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 +/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB +/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 +/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 +/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB +/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 +/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 +/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB +/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 +/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 +/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB +/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 +/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 +/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB +/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 +/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 +/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB +/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 +/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 +/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH +/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 +/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 +/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH +/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 +/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 +/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH +/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 +/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 +/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH +/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 +/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 +/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH +/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 +/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 +/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH +/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 +/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 +/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH +/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 +/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 +/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH +/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 +/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 +/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W +/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 +/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 +/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W +/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 +/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 +/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W +/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 +/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 +/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W +/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 +/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 +/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH +/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 +/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 +/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH +/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 +/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 +/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 +/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB +/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 +/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 +/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB +/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 +/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 +/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB +/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 +/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 +/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB +/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 +/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 +/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH +/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 +/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 +/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH +/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 +/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 +/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH +/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 +/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 +/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH +/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 +/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 +/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH +/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 +/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 +/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH +/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 +/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 +/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W +/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 +/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 +/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W +/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 +/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 +/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W +/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 +/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 +/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W +/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 +/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 +/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W +/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 +/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 +/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W +/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 +/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 +/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 +/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 +/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH +/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 +/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 +/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 +/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB +/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 +/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 +/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 +/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH +/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 +/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 +/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 +/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 +/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH +/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 +/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 +/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 +/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH +/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 +/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 +/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 +/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH +/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 +/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 +/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 +/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL +/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 +/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 +/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 +/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH +/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 +/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 +/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 +/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH +/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 +/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 +/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 +/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH +/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 +/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 +/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 +/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR +/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 +/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 +/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 +/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH +/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 +/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 +/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 +/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH +/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 +/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 +/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 +/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL +/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 +/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 +/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 +/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W +/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 +/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 +/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 +/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W +/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 +/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 +/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 +/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR +/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 +/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 +/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 +/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL +/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 +/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 +/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 +/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR +/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 +/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 +/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 +/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL +/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 +/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 +/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 +/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR +/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 +/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 +/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 +/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH +/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 +/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 +/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 +/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH +/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 +/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 +/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 +/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH +/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 +/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 +/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 +/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH +/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 +/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 +/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 +/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND +/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 +/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 +/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND +/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 +/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 +/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN +/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 +/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 +/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 +/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 +/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W +/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 +/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 +/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 +/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W +/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 +/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 +/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 +/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP +/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 +/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 +/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 +/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV +/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 +/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 +/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 +/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W +/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 +/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 +/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 +/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W +/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 +/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 +/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 +/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W +/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 +/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 +/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 +/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W +/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 +/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 +/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 +/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP +/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 +/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 +/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 +/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV +/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 +/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 +/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 +/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H +/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 +/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 +/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 +/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H +/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 +/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 +/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP +/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 +/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 +/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP +/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 +/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 +/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 +/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO +/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 +/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 +/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 +/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV +/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 +/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 +/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 +/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP +/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 +/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 +/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 +/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 +/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR +/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 +/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 +/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB +/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 +/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 +/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH +/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 +/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 +/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL +/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 +/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 +/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW +/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 +/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 +/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu +/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 +/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 +/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu +/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 +/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 +/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR +/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 +/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 +/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB +/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 +/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 +/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH +/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 +/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 +/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL +/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 +/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 +/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW +/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 +/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 +/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR +/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 +/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 +/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE +/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 +/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 +/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL +/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 +/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 +/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 +/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 +/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 +/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 +/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 +/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 +/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF +/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 +/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 +/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 +/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 +/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 +/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 +/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 +/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 +/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC +/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 +/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 +/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 +/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 +/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 +/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 +/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 +/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 +/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 +/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 +/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 +/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 +/* 13726 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r632[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 +/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 +/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 +/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 +/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 +/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 +/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 +/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 +/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 +/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 +/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 +/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 +/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 +/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 +/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 +/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 +/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 +/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 +/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 +/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 +/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 +/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 +/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 +/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 +/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 +/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 +/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 +/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 +/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 +/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 +/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 +/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 +/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 +/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 +/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 +/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 +/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 +/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 +/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 +/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 +/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 +/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 +/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH +/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 +/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 +/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 +/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU +/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 +/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 +/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU +/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 +/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 +/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 +/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV +/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 +/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 +/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD +/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 +/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 +/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 +/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU +/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 +/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 +/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU +/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 +/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 +/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 +/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 +/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 +/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 +/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH +/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 +/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 +/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 +/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU +/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 +/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 +/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU +/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 +/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 +/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 +/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV +/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 +/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 +/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD +/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 +/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 +/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 +/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU +/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 +/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 +/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU +/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 +/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 +/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 +/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ +/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 +/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 +/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 +/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ +/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 +/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 +/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 +/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI +/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 +/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 +/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 +/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL +/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 +/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 +/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI +/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 +/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 +/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC +/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 +/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 +/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC +/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 +/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 +/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC +/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 +/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 +/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI +/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 +/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 +/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 +/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ +/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 +/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 +/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ +/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 +/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 +/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 +/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S +/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 +/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 +/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S +/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 +/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 +/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S +/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 +/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 +/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S +/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 +/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 +/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S +/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 +/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 +/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 +/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S +/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 +/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 +/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 +/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S +/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 +/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 +/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S +/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 +/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 +/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S +/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 +/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 +/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S +/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 +/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 +/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S +/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 +/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 +/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 +/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D +/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 +/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 +/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D +/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 +/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 +/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D +/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 +/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 +/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D +/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 +/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 +/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D +/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 +/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 +/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 +/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D +/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 +/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 +/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 +/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D +/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 +/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 +/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D +/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 +/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 +/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D +/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 +/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 +/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D +/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 +/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 +/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D +/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 +/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 +/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 +/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S +/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 +/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 +/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S +/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 +/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 +/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S +/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 +/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 +/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S +/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 +/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 +/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S +/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 +/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 +/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S +/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 +/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 +/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S +/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 +/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 +/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S +/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 +/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 +/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S +/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 +/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 +/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S +/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 +/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 +/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S +/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 +/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 +/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S +/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 +/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 +/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S +/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 +/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 +/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S +/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 +/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 +/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S +/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 +/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 +/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S +/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 +/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 +/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 +/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D +/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 +/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 +/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D +/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 +/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 +/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D +/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 +/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 +/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D +/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 +/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 +/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D +/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 +/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 +/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D +/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 +/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 +/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D +/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 +/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 +/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D +/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 +/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 +/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D +/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 +/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 +/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D +/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 +/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 +/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D +/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 +/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 +/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D +/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 +/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 +/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D +/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 +/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 +/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D +/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 +/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 +/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D +/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 +/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 +/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D +/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 +/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 +/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 +/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ +/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 +/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 +/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 +/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 +/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 +/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 +/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 +/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 +/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ +/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 +/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 +/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 +/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 +/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 +/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 +/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 +/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 +/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC +/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 +/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 +/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC +/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 +/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 +/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC +/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 +/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 +/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI +/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 +/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 +/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 +/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 +/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 +/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 +/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP +/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 +/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 +/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN +/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 +/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 +/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 +/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 +/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 +/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP +/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 +/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 +/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN +/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 +/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 +/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 +/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 +/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 +/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 +/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 +/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 +/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 +/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 +/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 +/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 +/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 +/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 +/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 +/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 +/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 +/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 +/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 +/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 +/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 +/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 +/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC +/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 +/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 +/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 +/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC +/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 +/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC +/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 +/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 +/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC +/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 +/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 +/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 +/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC +/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 +/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 +/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC +/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 +/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 +/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC +/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 +/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 +/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 +/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC +/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 +/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 +/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 +/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC +/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 +/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 +/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC +/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 +/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 +/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 +/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC +/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 +/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC +/* 1847 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 +/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 +/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 +/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 +/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 +/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 +/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 +/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 +/* 41 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableMips6432[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 +/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 +/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 +/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 +/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV +/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 +/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 +/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 +/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV +/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 +/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 +/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV +/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 +/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 +/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 +/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV +/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 +/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 +/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 +/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT +/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 +/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 +/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 +/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu +/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 +/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 +/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 +/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV +/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 +/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 +/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 +/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV +/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 +/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 +/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 +/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD +/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 +/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 +/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 +/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu +/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 +/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 +/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 +/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB +/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 +/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 +/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 +/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu +/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 +/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 +/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 +/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL +/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 +/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 +/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 +/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL +/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 +/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 +/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR +/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 +/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 +/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 +/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA +/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 +/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 +/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 +/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 +/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 +/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 +/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 +/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 +/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 +/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 +/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 +/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 +/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 +/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 +/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 +/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 +/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 +/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 +/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 +/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 +/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 +/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 +/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 +/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 +/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 +/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 +/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 +/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 +/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 +/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 +/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 +/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 +/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 +/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 +/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 +/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 +/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 +/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 +/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 +/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 +/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 +/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 +/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 +/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 +/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 +/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 +/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 +/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 +/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 +/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 +/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 +/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 +/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 +/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 +/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 +/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 +/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 +/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 +/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 +/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 +/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 +/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 +/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 +/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 +/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 +/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 +/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 +/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 +/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S +/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 +/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 +/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 +/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 +/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 +/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 +/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S +/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 +/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 +/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 +/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 +/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 +/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 +/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S +/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 +/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 +/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 +/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 +/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 +/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 +/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S +/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 +/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 +/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 +/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 +/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 +/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 +/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 +/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 +/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 +/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 +/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 +/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 +/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 +/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 +/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 +/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 +/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 +/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 +/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 +/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 +/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... +/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 +/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 +/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 +/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 +/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 +/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 +/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 +/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 +/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 +/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 +/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 +/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 +/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 +/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 +/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 +/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 +/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 +/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 +/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 +/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 +/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 +/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 +/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L +/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 +/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 +/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 +/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S +/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 +/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 +/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W +/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 +/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 +/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L +/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 +/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 +/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 +/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 +/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 +/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 +/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 +/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 +/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 +/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 +/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 +/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 +/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 +/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 +/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 +/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 +/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 +/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 +/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 +/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 +/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 +/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 +/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 +/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 +/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 +/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 +/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 +/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 +/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 +/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 +/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 +/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 +/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 +/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 +/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 +/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 +/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 +/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 +/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 +/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 +/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 +/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 +/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 +/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 +/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 +/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 +/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 +/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 +/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 +/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 +/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 +/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 +/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 +/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 +/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 +/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 +/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 +/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 +/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 +/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 +/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 +/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 +/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 +/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 +/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 +/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 +/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 +/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 +/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 +/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 +/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 +/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 +/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 +/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 +/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 +/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 +/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 +/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 +/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 +/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 +/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 +/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 +/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 +/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 +/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 +/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 +/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 +/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 +/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 +/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 +/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 +/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 +/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 +/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 +/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 +/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 +/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 +/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 +/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 +/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 +/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 +/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 +/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 +/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 +/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 +/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 +/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 +/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 +/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 +/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 +/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 +/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 +/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 +/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 +/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 +/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 +/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 +/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 +/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 +/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 +/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 +/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 +/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 +/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 +/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi +/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 +/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 +/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu +/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 +/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 +/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL +/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 +/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 +/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR +/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 +/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 +/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 +/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 +/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL +/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 +/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 +/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 +/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 +/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 +/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 +/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 +/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 +/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 +/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 +/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 +/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 +/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 +/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 +/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 +/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 +/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 +/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 +/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 +/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 +/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 +/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 +/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 +/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 +/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 +/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 +/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 +/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU +/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 +/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 +/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 +/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 +/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 +/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 +/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 +/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU +/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 +/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 +/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 +/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ +/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 +/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 +/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 +/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO +/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 +/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 +/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 +/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu +/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 +/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 +/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 +/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ +/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 +/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 +/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 +/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE +/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 +/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 +/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 +/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 +/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP +/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 +/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 +/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 +/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 +/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP +/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 +/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 +/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi +/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 +/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 +/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi +/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 +/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 +/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS +/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 +/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 +/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 +/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 +/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 +/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS +/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 +/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 +/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 +/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 +/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 +/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 +/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM +/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 +/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 +/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU +/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 +/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 +/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT +/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 +/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 +/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM +/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 +/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 +/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU +/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 +/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 +/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS +/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 +/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 +/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 +/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 +/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH +/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 +/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 +/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 +/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD +/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 +/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 +/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu +/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 +/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 +/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL +/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 +/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 +/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR +/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 +/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 +/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 +/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 +/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 +/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD +/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 +/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 +/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 +/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 +/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 +/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 +/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 +/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 +/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD +/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 +/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 +/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 +/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 +/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 +/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD +/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 +/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 +/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 +/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 +/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 +/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 +/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 +/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 +/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD +/* 2364 */ MCD_OPC_Fail, + 0 +}; + +static bool getbool(uint64_t b) +{ + return b != 0; +} + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + switch (Idx) { + default: // llvm_unreachable("Invalid index!"); + case 0: + return getbool((Bits & Mips_FeatureMips16)); + case 1: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); + case 2: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); + case 3: + return getbool((Bits & Mips_FeatureMicroMips)); + case 4: + return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); + case 5: + return getbool(!(Bits & Mips_FeatureMips16)); + case 6: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); + case 7: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 8: + return getbool((Bits & Mips_FeatureMSA)); + case 9: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 10: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); + case 11: + return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + case 12: + return getbool((Bits & Mips_FeatureDSP)); + case 13: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 14: + return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); + case 15: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); + case 16: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 17: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); + case 18: + return getbool(!(Bits & Mips_FeatureMicroMips)); + case 19: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); + case 20: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); + case 21: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); + case 22: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); + case 23: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); + case 24: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 25: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); + case 26: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 27: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + case 28: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 29: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 30: + return getbool((Bits & Mips_FeatureDSPR2)); + case 31: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 32: + return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + case 33: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + case 34: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + case 35: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + case 36: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); + case 37: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); + case 38: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + case 39: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + case 40: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); + case 41: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 42: + return getbool((Bits & Mips_FeatureMips64)); + case 43: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); + case 44: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); + case 45: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); + case 46: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 47: + return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); + case 48: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 49: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + case 50: + return getbool((Bits & Mips_FeatureCnMips)); + case 51: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); + case 52: + return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + } +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 2) << 3; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 12: \ + if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 15: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 19: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 20: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 21: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 4); \ + if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 1, 9); \ + if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 6); \ + if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 10); \ + if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 33: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 34: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 37: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 38: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 39: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 40: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 41: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 42: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 43: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 47: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 52: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 53: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 54: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 23); \ + if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 57: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 58: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 59: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 60: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + tmp = fieldname(insn, 6, 20); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 65: \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 66: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 69: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 70: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 71: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 72: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 73: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 74: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 75: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 76: \ + if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 77: \ + if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 78: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 79: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 82: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 83: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 84: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 85: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 86: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 87: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 88: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 89: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 90: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 91: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 92: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 93: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 94: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 95: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 96: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 97: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 98: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 99: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 100: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 101: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 102: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 103: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 104: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 105: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 106: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 107: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 108: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 109: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 110: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 111: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 112: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 113: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 114: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 115: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 116: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 117: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 118: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 119: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 120: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 121: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 122: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 123: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 124: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 125: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 126: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 127: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 128: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 129: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 130: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 131: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 132: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 133: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 134: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 135: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 136: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 137: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 138: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 139: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 140: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 141: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 142: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 143: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 144: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 145: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 146: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 147: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 148: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 149: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 150: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 151: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 152: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 153: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 154: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 155: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 156: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 157: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 158: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 159: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 160: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 161: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 162: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 163: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 164: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 165: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 166: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 167: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 168: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 169: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 170: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 171: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 172: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 173: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 174: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 175: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 176: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 177: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 178: \ + if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 179: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 180: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 181: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 182: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 183: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 184: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 185: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 186: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 187: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 188: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 189: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 190: \ + if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 191: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 192: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 193: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 194: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 195: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 196: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 197: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 198: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 199: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 200: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 201: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 202: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 203: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 204: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 205: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 206: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 207: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 208: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 209: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 210: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 211: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 212: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 213: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 214: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 6); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 215: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 216: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 217: \ + if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 218: \ + if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 219: \ + if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 220: \ + if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 221: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 222: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 223: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 224: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 225: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 226: \ + if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 227: \ + if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 228: \ + if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 229: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 230: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 231: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 232: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 233: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 234: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 235: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 236: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 237: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 238: \ + if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 239: \ + if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 240: \ + if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 241: \ + if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 242: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 243: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 244: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 245: \ + if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 246: \ + if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 247: \ + tmp = fieldname(insn, 0, 26); \ + if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 248: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 249: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 19); \ + if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 250: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 18); \ + if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 251: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 252: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 253: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 254: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 255: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 256: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 257: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 258: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 259: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 260: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 261: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 262: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 263: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 264: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 265: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 266: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 267: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 268: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 269: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 270: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 271: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 272: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction, uint32_t) +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) +DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/Mips/MipsGenInstrInfo.inc new file mode 100644 index 0000000..b6e8983 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsGenInstrInfo.inc @@ -0,0 +1,1805 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + Mips_PHI = 0, + Mips_INLINEASM = 1, + Mips_CFI_INSTRUCTION = 2, + Mips_EH_LABEL = 3, + Mips_GC_LABEL = 4, + Mips_KILL = 5, + Mips_EXTRACT_SUBREG = 6, + Mips_INSERT_SUBREG = 7, + Mips_IMPLICIT_DEF = 8, + Mips_SUBREG_TO_REG = 9, + Mips_COPY_TO_REGCLASS = 10, + Mips_DBG_VALUE = 11, + Mips_REG_SEQUENCE = 12, + Mips_COPY = 13, + Mips_BUNDLE = 14, + Mips_LIFETIME_START = 15, + Mips_LIFETIME_END = 16, + Mips_STACKMAP = 17, + Mips_PATCHPOINT = 18, + Mips_LOAD_STACK_GUARD = 19, + Mips_STATEPOINT = 20, + Mips_FRAME_ALLOC = 21, + Mips_ABSQ_S_PH = 22, + Mips_ABSQ_S_QB = 23, + Mips_ABSQ_S_W = 24, + Mips_ADD = 25, + Mips_ADDIUPC = 26, + Mips_ADDIUPC_MM = 27, + Mips_ADDIUR1SP_MM = 28, + Mips_ADDIUR2_MM = 29, + Mips_ADDIUS5_MM = 30, + Mips_ADDIUSP_MM = 31, + Mips_ADDQH_PH = 32, + Mips_ADDQH_R_PH = 33, + Mips_ADDQH_R_W = 34, + Mips_ADDQH_W = 35, + Mips_ADDQ_PH = 36, + Mips_ADDQ_S_PH = 37, + Mips_ADDQ_S_W = 38, + Mips_ADDSC = 39, + Mips_ADDS_A_B = 40, + Mips_ADDS_A_D = 41, + Mips_ADDS_A_H = 42, + Mips_ADDS_A_W = 43, + Mips_ADDS_S_B = 44, + Mips_ADDS_S_D = 45, + Mips_ADDS_S_H = 46, + Mips_ADDS_S_W = 47, + Mips_ADDS_U_B = 48, + Mips_ADDS_U_D = 49, + Mips_ADDS_U_H = 50, + Mips_ADDS_U_W = 51, + Mips_ADDU16_MM = 52, + Mips_ADDUH_QB = 53, + Mips_ADDUH_R_QB = 54, + Mips_ADDU_PH = 55, + Mips_ADDU_QB = 56, + Mips_ADDU_S_PH = 57, + Mips_ADDU_S_QB = 58, + Mips_ADDVI_B = 59, + Mips_ADDVI_D = 60, + Mips_ADDVI_H = 61, + Mips_ADDVI_W = 62, + Mips_ADDV_B = 63, + Mips_ADDV_D = 64, + Mips_ADDV_H = 65, + Mips_ADDV_W = 66, + Mips_ADDWC = 67, + Mips_ADD_A_B = 68, + Mips_ADD_A_D = 69, + Mips_ADD_A_H = 70, + Mips_ADD_A_W = 71, + Mips_ADD_MM = 72, + Mips_ADDi = 73, + Mips_ADDi_MM = 74, + Mips_ADDiu = 75, + Mips_ADDiu_MM = 76, + Mips_ADDu = 77, + Mips_ADDu_MM = 78, + Mips_ADJCALLSTACKDOWN = 79, + Mips_ADJCALLSTACKUP = 80, + Mips_ALIGN = 81, + Mips_ALUIPC = 82, + Mips_AND = 83, + Mips_AND16_MM = 84, + Mips_AND64 = 85, + Mips_ANDI16_MM = 86, + Mips_ANDI_B = 87, + Mips_AND_MM = 88, + Mips_AND_V = 89, + Mips_AND_V_D_PSEUDO = 90, + Mips_AND_V_H_PSEUDO = 91, + Mips_AND_V_W_PSEUDO = 92, + Mips_ANDi = 93, + Mips_ANDi64 = 94, + Mips_ANDi_MM = 95, + Mips_APPEND = 96, + Mips_ASUB_S_B = 97, + Mips_ASUB_S_D = 98, + Mips_ASUB_S_H = 99, + Mips_ASUB_S_W = 100, + Mips_ASUB_U_B = 101, + Mips_ASUB_U_D = 102, + Mips_ASUB_U_H = 103, + Mips_ASUB_U_W = 104, + Mips_ATOMIC_CMP_SWAP_I16 = 105, + Mips_ATOMIC_CMP_SWAP_I32 = 106, + Mips_ATOMIC_CMP_SWAP_I64 = 107, + Mips_ATOMIC_CMP_SWAP_I8 = 108, + Mips_ATOMIC_LOAD_ADD_I16 = 109, + Mips_ATOMIC_LOAD_ADD_I32 = 110, + Mips_ATOMIC_LOAD_ADD_I64 = 111, + Mips_ATOMIC_LOAD_ADD_I8 = 112, + Mips_ATOMIC_LOAD_AND_I16 = 113, + Mips_ATOMIC_LOAD_AND_I32 = 114, + Mips_ATOMIC_LOAD_AND_I64 = 115, + Mips_ATOMIC_LOAD_AND_I8 = 116, + Mips_ATOMIC_LOAD_NAND_I16 = 117, + Mips_ATOMIC_LOAD_NAND_I32 = 118, + Mips_ATOMIC_LOAD_NAND_I64 = 119, + Mips_ATOMIC_LOAD_NAND_I8 = 120, + Mips_ATOMIC_LOAD_OR_I16 = 121, + Mips_ATOMIC_LOAD_OR_I32 = 122, + Mips_ATOMIC_LOAD_OR_I64 = 123, + Mips_ATOMIC_LOAD_OR_I8 = 124, + Mips_ATOMIC_LOAD_SUB_I16 = 125, + Mips_ATOMIC_LOAD_SUB_I32 = 126, + Mips_ATOMIC_LOAD_SUB_I64 = 127, + Mips_ATOMIC_LOAD_SUB_I8 = 128, + Mips_ATOMIC_LOAD_XOR_I16 = 129, + Mips_ATOMIC_LOAD_XOR_I32 = 130, + Mips_ATOMIC_LOAD_XOR_I64 = 131, + Mips_ATOMIC_LOAD_XOR_I8 = 132, + Mips_ATOMIC_SWAP_I16 = 133, + Mips_ATOMIC_SWAP_I32 = 134, + Mips_ATOMIC_SWAP_I64 = 135, + Mips_ATOMIC_SWAP_I8 = 136, + Mips_AUI = 137, + Mips_AUIPC = 138, + Mips_AVER_S_B = 139, + Mips_AVER_S_D = 140, + Mips_AVER_S_H = 141, + Mips_AVER_S_W = 142, + Mips_AVER_U_B = 143, + Mips_AVER_U_D = 144, + Mips_AVER_U_H = 145, + Mips_AVER_U_W = 146, + Mips_AVE_S_B = 147, + Mips_AVE_S_D = 148, + Mips_AVE_S_H = 149, + Mips_AVE_S_W = 150, + Mips_AVE_U_B = 151, + Mips_AVE_U_D = 152, + Mips_AVE_U_H = 153, + Mips_AVE_U_W = 154, + Mips_AddiuRxImmX16 = 155, + Mips_AddiuRxPcImmX16 = 156, + Mips_AddiuRxRxImm16 = 157, + Mips_AddiuRxRxImmX16 = 158, + Mips_AddiuRxRyOffMemX16 = 159, + Mips_AddiuSpImm16 = 160, + Mips_AddiuSpImmX16 = 161, + Mips_AdduRxRyRz16 = 162, + Mips_AndRxRxRy16 = 163, + Mips_B = 164, + Mips_B16_MM = 165, + Mips_BADDu = 166, + Mips_BAL = 167, + Mips_BALC = 168, + Mips_BALIGN = 169, + Mips_BAL_BR = 170, + Mips_BBIT0 = 171, + Mips_BBIT032 = 172, + Mips_BBIT1 = 173, + Mips_BBIT132 = 174, + Mips_BC = 175, + Mips_BC0F = 176, + Mips_BC0FL = 177, + Mips_BC0T = 178, + Mips_BC0TL = 179, + Mips_BC1EQZ = 180, + Mips_BC1F = 181, + Mips_BC1FL = 182, + Mips_BC1F_MM = 183, + Mips_BC1NEZ = 184, + Mips_BC1T = 185, + Mips_BC1TL = 186, + Mips_BC1T_MM = 187, + Mips_BC2EQZ = 188, + Mips_BC2F = 189, + Mips_BC2FL = 190, + Mips_BC2NEZ = 191, + Mips_BC2T = 192, + Mips_BC2TL = 193, + Mips_BC3F = 194, + Mips_BC3FL = 195, + Mips_BC3T = 196, + Mips_BC3TL = 197, + Mips_BCLRI_B = 198, + Mips_BCLRI_D = 199, + Mips_BCLRI_H = 200, + Mips_BCLRI_W = 201, + Mips_BCLR_B = 202, + Mips_BCLR_D = 203, + Mips_BCLR_H = 204, + Mips_BCLR_W = 205, + Mips_BEQ = 206, + Mips_BEQ64 = 207, + Mips_BEQC = 208, + Mips_BEQL = 209, + Mips_BEQZ16_MM = 210, + Mips_BEQZALC = 211, + Mips_BEQZC = 212, + Mips_BEQZC_MM = 213, + Mips_BEQ_MM = 214, + Mips_BGEC = 215, + Mips_BGEUC = 216, + Mips_BGEZ = 217, + Mips_BGEZ64 = 218, + Mips_BGEZAL = 219, + Mips_BGEZALC = 220, + Mips_BGEZALL = 221, + Mips_BGEZALS_MM = 222, + Mips_BGEZAL_MM = 223, + Mips_BGEZC = 224, + Mips_BGEZL = 225, + Mips_BGEZ_MM = 226, + Mips_BGTZ = 227, + Mips_BGTZ64 = 228, + Mips_BGTZALC = 229, + Mips_BGTZC = 230, + Mips_BGTZL = 231, + Mips_BGTZ_MM = 232, + Mips_BINSLI_B = 233, + Mips_BINSLI_D = 234, + Mips_BINSLI_H = 235, + Mips_BINSLI_W = 236, + Mips_BINSL_B = 237, + Mips_BINSL_D = 238, + Mips_BINSL_H = 239, + Mips_BINSL_W = 240, + Mips_BINSRI_B = 241, + Mips_BINSRI_D = 242, + Mips_BINSRI_H = 243, + Mips_BINSRI_W = 244, + Mips_BINSR_B = 245, + Mips_BINSR_D = 246, + Mips_BINSR_H = 247, + Mips_BINSR_W = 248, + Mips_BITREV = 249, + Mips_BITSWAP = 250, + Mips_BLEZ = 251, + Mips_BLEZ64 = 252, + Mips_BLEZALC = 253, + Mips_BLEZC = 254, + Mips_BLEZL = 255, + Mips_BLEZ_MM = 256, + Mips_BLTC = 257, + Mips_BLTUC = 258, + Mips_BLTZ = 259, + Mips_BLTZ64 = 260, + Mips_BLTZAL = 261, + Mips_BLTZALC = 262, + Mips_BLTZALL = 263, + Mips_BLTZALS_MM = 264, + Mips_BLTZAL_MM = 265, + Mips_BLTZC = 266, + Mips_BLTZL = 267, + Mips_BLTZ_MM = 268, + Mips_BMNZI_B = 269, + Mips_BMNZ_V = 270, + Mips_BMZI_B = 271, + Mips_BMZ_V = 272, + Mips_BNE = 273, + Mips_BNE64 = 274, + Mips_BNEC = 275, + Mips_BNEGI_B = 276, + Mips_BNEGI_D = 277, + Mips_BNEGI_H = 278, + Mips_BNEGI_W = 279, + Mips_BNEG_B = 280, + Mips_BNEG_D = 281, + Mips_BNEG_H = 282, + Mips_BNEG_W = 283, + Mips_BNEL = 284, + Mips_BNEZ16_MM = 285, + Mips_BNEZALC = 286, + Mips_BNEZC = 287, + Mips_BNEZC_MM = 288, + Mips_BNE_MM = 289, + Mips_BNVC = 290, + Mips_BNZ_B = 291, + Mips_BNZ_D = 292, + Mips_BNZ_H = 293, + Mips_BNZ_V = 294, + Mips_BNZ_W = 295, + Mips_BOVC = 296, + Mips_BPOSGE32 = 297, + Mips_BPOSGE32_PSEUDO = 298, + Mips_BREAK = 299, + Mips_BREAK16_MM = 300, + Mips_BREAK_MM = 301, + Mips_BSELI_B = 302, + Mips_BSEL_D_PSEUDO = 303, + Mips_BSEL_FD_PSEUDO = 304, + Mips_BSEL_FW_PSEUDO = 305, + Mips_BSEL_H_PSEUDO = 306, + Mips_BSEL_V = 307, + Mips_BSEL_W_PSEUDO = 308, + Mips_BSETI_B = 309, + Mips_BSETI_D = 310, + Mips_BSETI_H = 311, + Mips_BSETI_W = 312, + Mips_BSET_B = 313, + Mips_BSET_D = 314, + Mips_BSET_H = 315, + Mips_BSET_W = 316, + Mips_BZ_B = 317, + Mips_BZ_D = 318, + Mips_BZ_H = 319, + Mips_BZ_V = 320, + Mips_BZ_W = 321, + Mips_B_MM_Pseudo = 322, + Mips_BeqzRxImm16 = 323, + Mips_BeqzRxImmX16 = 324, + Mips_Bimm16 = 325, + Mips_BimmX16 = 326, + Mips_BnezRxImm16 = 327, + Mips_BnezRxImmX16 = 328, + Mips_Break16 = 329, + Mips_Bteqz16 = 330, + Mips_BteqzT8CmpX16 = 331, + Mips_BteqzT8CmpiX16 = 332, + Mips_BteqzT8SltX16 = 333, + Mips_BteqzT8SltiX16 = 334, + Mips_BteqzT8SltiuX16 = 335, + Mips_BteqzT8SltuX16 = 336, + Mips_BteqzX16 = 337, + Mips_Btnez16 = 338, + Mips_BtnezT8CmpX16 = 339, + Mips_BtnezT8CmpiX16 = 340, + Mips_BtnezT8SltX16 = 341, + Mips_BtnezT8SltiX16 = 342, + Mips_BtnezT8SltiuX16 = 343, + Mips_BtnezT8SltuX16 = 344, + Mips_BtnezX16 = 345, + Mips_BuildPairF64 = 346, + Mips_BuildPairF64_64 = 347, + Mips_CACHE = 348, + Mips_CACHE_MM = 349, + Mips_CACHE_R6 = 350, + Mips_CEIL_L_D64 = 351, + Mips_CEIL_L_S = 352, + Mips_CEIL_W_D32 = 353, + Mips_CEIL_W_D64 = 354, + Mips_CEIL_W_MM = 355, + Mips_CEIL_W_S = 356, + Mips_CEIL_W_S_MM = 357, + Mips_CEQI_B = 358, + Mips_CEQI_D = 359, + Mips_CEQI_H = 360, + Mips_CEQI_W = 361, + Mips_CEQ_B = 362, + Mips_CEQ_D = 363, + Mips_CEQ_H = 364, + Mips_CEQ_W = 365, + Mips_CFC1 = 366, + Mips_CFC1_MM = 367, + Mips_CFCMSA = 368, + Mips_CINS = 369, + Mips_CINS32 = 370, + Mips_CLASS_D = 371, + Mips_CLASS_S = 372, + Mips_CLEI_S_B = 373, + Mips_CLEI_S_D = 374, + Mips_CLEI_S_H = 375, + Mips_CLEI_S_W = 376, + Mips_CLEI_U_B = 377, + Mips_CLEI_U_D = 378, + Mips_CLEI_U_H = 379, + Mips_CLEI_U_W = 380, + Mips_CLE_S_B = 381, + Mips_CLE_S_D = 382, + Mips_CLE_S_H = 383, + Mips_CLE_S_W = 384, + Mips_CLE_U_B = 385, + Mips_CLE_U_D = 386, + Mips_CLE_U_H = 387, + Mips_CLE_U_W = 388, + Mips_CLO = 389, + Mips_CLO_MM = 390, + Mips_CLO_R6 = 391, + Mips_CLTI_S_B = 392, + Mips_CLTI_S_D = 393, + Mips_CLTI_S_H = 394, + Mips_CLTI_S_W = 395, + Mips_CLTI_U_B = 396, + Mips_CLTI_U_D = 397, + Mips_CLTI_U_H = 398, + Mips_CLTI_U_W = 399, + Mips_CLT_S_B = 400, + Mips_CLT_S_D = 401, + Mips_CLT_S_H = 402, + Mips_CLT_S_W = 403, + Mips_CLT_U_B = 404, + Mips_CLT_U_D = 405, + Mips_CLT_U_H = 406, + Mips_CLT_U_W = 407, + Mips_CLZ = 408, + Mips_CLZ_MM = 409, + Mips_CLZ_R6 = 410, + Mips_CMPGDU_EQ_QB = 411, + Mips_CMPGDU_LE_QB = 412, + Mips_CMPGDU_LT_QB = 413, + Mips_CMPGU_EQ_QB = 414, + Mips_CMPGU_LE_QB = 415, + Mips_CMPGU_LT_QB = 416, + Mips_CMPU_EQ_QB = 417, + Mips_CMPU_LE_QB = 418, + Mips_CMPU_LT_QB = 419, + Mips_CMP_EQ_D = 420, + Mips_CMP_EQ_PH = 421, + Mips_CMP_EQ_S = 422, + Mips_CMP_F_D = 423, + Mips_CMP_F_S = 424, + Mips_CMP_LE_D = 425, + Mips_CMP_LE_PH = 426, + Mips_CMP_LE_S = 427, + Mips_CMP_LT_D = 428, + Mips_CMP_LT_PH = 429, + Mips_CMP_LT_S = 430, + Mips_CMP_SAF_D = 431, + Mips_CMP_SAF_S = 432, + Mips_CMP_SEQ_D = 433, + Mips_CMP_SEQ_S = 434, + Mips_CMP_SLE_D = 435, + Mips_CMP_SLE_S = 436, + Mips_CMP_SLT_D = 437, + Mips_CMP_SLT_S = 438, + Mips_CMP_SUEQ_D = 439, + Mips_CMP_SUEQ_S = 440, + Mips_CMP_SULE_D = 441, + Mips_CMP_SULE_S = 442, + Mips_CMP_SULT_D = 443, + Mips_CMP_SULT_S = 444, + Mips_CMP_SUN_D = 445, + Mips_CMP_SUN_S = 446, + Mips_CMP_UEQ_D = 447, + Mips_CMP_UEQ_S = 448, + Mips_CMP_ULE_D = 449, + Mips_CMP_ULE_S = 450, + Mips_CMP_ULT_D = 451, + Mips_CMP_ULT_S = 452, + Mips_CMP_UN_D = 453, + Mips_CMP_UN_S = 454, + Mips_CONSTPOOL_ENTRY = 455, + Mips_COPY_FD_PSEUDO = 456, + Mips_COPY_FW_PSEUDO = 457, + Mips_COPY_S_B = 458, + Mips_COPY_S_D = 459, + Mips_COPY_S_H = 460, + Mips_COPY_S_W = 461, + Mips_COPY_U_B = 462, + Mips_COPY_U_D = 463, + Mips_COPY_U_H = 464, + Mips_COPY_U_W = 465, + Mips_CTC1 = 466, + Mips_CTC1_MM = 467, + Mips_CTCMSA = 468, + Mips_CVT_D32_S = 469, + Mips_CVT_D32_W = 470, + Mips_CVT_D32_W_MM = 471, + Mips_CVT_D64_L = 472, + Mips_CVT_D64_S = 473, + Mips_CVT_D64_W = 474, + Mips_CVT_D_S_MM = 475, + Mips_CVT_L_D64 = 476, + Mips_CVT_L_D64_MM = 477, + Mips_CVT_L_S = 478, + Mips_CVT_L_S_MM = 479, + Mips_CVT_S_D32 = 480, + Mips_CVT_S_D32_MM = 481, + Mips_CVT_S_D64 = 482, + Mips_CVT_S_L = 483, + Mips_CVT_S_W = 484, + Mips_CVT_S_W_MM = 485, + Mips_CVT_W_D32 = 486, + Mips_CVT_W_D64 = 487, + Mips_CVT_W_MM = 488, + Mips_CVT_W_S = 489, + Mips_CVT_W_S_MM = 490, + Mips_C_EQ_D32 = 491, + Mips_C_EQ_D64 = 492, + Mips_C_EQ_S = 493, + Mips_C_F_D32 = 494, + Mips_C_F_D64 = 495, + Mips_C_F_S = 496, + Mips_C_LE_D32 = 497, + Mips_C_LE_D64 = 498, + Mips_C_LE_S = 499, + Mips_C_LT_D32 = 500, + Mips_C_LT_D64 = 501, + Mips_C_LT_S = 502, + Mips_C_NGE_D32 = 503, + Mips_C_NGE_D64 = 504, + Mips_C_NGE_S = 505, + Mips_C_NGLE_D32 = 506, + Mips_C_NGLE_D64 = 507, + Mips_C_NGLE_S = 508, + Mips_C_NGL_D32 = 509, + Mips_C_NGL_D64 = 510, + Mips_C_NGL_S = 511, + Mips_C_NGT_D32 = 512, + Mips_C_NGT_D64 = 513, + Mips_C_NGT_S = 514, + Mips_C_OLE_D32 = 515, + Mips_C_OLE_D64 = 516, + Mips_C_OLE_S = 517, + Mips_C_OLT_D32 = 518, + Mips_C_OLT_D64 = 519, + Mips_C_OLT_S = 520, + Mips_C_SEQ_D32 = 521, + Mips_C_SEQ_D64 = 522, + Mips_C_SEQ_S = 523, + Mips_C_SF_D32 = 524, + Mips_C_SF_D64 = 525, + Mips_C_SF_S = 526, + Mips_C_UEQ_D32 = 527, + Mips_C_UEQ_D64 = 528, + Mips_C_UEQ_S = 529, + Mips_C_ULE_D32 = 530, + Mips_C_ULE_D64 = 531, + Mips_C_ULE_S = 532, + Mips_C_ULT_D32 = 533, + Mips_C_ULT_D64 = 534, + Mips_C_ULT_S = 535, + Mips_C_UN_D32 = 536, + Mips_C_UN_D64 = 537, + Mips_C_UN_S = 538, + Mips_CmpRxRy16 = 539, + Mips_CmpiRxImm16 = 540, + Mips_CmpiRxImmX16 = 541, + Mips_Constant32 = 542, + Mips_DADD = 543, + Mips_DADDi = 544, + Mips_DADDiu = 545, + Mips_DADDu = 546, + Mips_DAHI = 547, + Mips_DALIGN = 548, + Mips_DATI = 549, + Mips_DAUI = 550, + Mips_DBITSWAP = 551, + Mips_DCLO = 552, + Mips_DCLO_R6 = 553, + Mips_DCLZ = 554, + Mips_DCLZ_R6 = 555, + Mips_DDIV = 556, + Mips_DDIVU = 557, + Mips_DERET = 558, + Mips_DERET_MM = 559, + Mips_DEXT = 560, + Mips_DEXTM = 561, + Mips_DEXTU = 562, + Mips_DI = 563, + Mips_DINS = 564, + Mips_DINSM = 565, + Mips_DINSU = 566, + Mips_DIV = 567, + Mips_DIVU = 568, + Mips_DIV_S_B = 569, + Mips_DIV_S_D = 570, + Mips_DIV_S_H = 571, + Mips_DIV_S_W = 572, + Mips_DIV_U_B = 573, + Mips_DIV_U_D = 574, + Mips_DIV_U_H = 575, + Mips_DIV_U_W = 576, + Mips_DI_MM = 577, + Mips_DLSA = 578, + Mips_DLSA_R6 = 579, + Mips_DMFC0 = 580, + Mips_DMFC1 = 581, + Mips_DMFC2 = 582, + Mips_DMOD = 583, + Mips_DMODU = 584, + Mips_DMTC0 = 585, + Mips_DMTC1 = 586, + Mips_DMTC2 = 587, + Mips_DMUH = 588, + Mips_DMUHU = 589, + Mips_DMUL = 590, + Mips_DMULT = 591, + Mips_DMULTu = 592, + Mips_DMULU = 593, + Mips_DMUL_R6 = 594, + Mips_DOTP_S_D = 595, + Mips_DOTP_S_H = 596, + Mips_DOTP_S_W = 597, + Mips_DOTP_U_D = 598, + Mips_DOTP_U_H = 599, + Mips_DOTP_U_W = 600, + Mips_DPADD_S_D = 601, + Mips_DPADD_S_H = 602, + Mips_DPADD_S_W = 603, + Mips_DPADD_U_D = 604, + Mips_DPADD_U_H = 605, + Mips_DPADD_U_W = 606, + Mips_DPAQX_SA_W_PH = 607, + Mips_DPAQX_S_W_PH = 608, + Mips_DPAQ_SA_L_W = 609, + Mips_DPAQ_S_W_PH = 610, + Mips_DPAU_H_QBL = 611, + Mips_DPAU_H_QBR = 612, + Mips_DPAX_W_PH = 613, + Mips_DPA_W_PH = 614, + Mips_DPOP = 615, + Mips_DPSQX_SA_W_PH = 616, + Mips_DPSQX_S_W_PH = 617, + Mips_DPSQ_SA_L_W = 618, + Mips_DPSQ_S_W_PH = 619, + Mips_DPSUB_S_D = 620, + Mips_DPSUB_S_H = 621, + Mips_DPSUB_S_W = 622, + Mips_DPSUB_U_D = 623, + Mips_DPSUB_U_H = 624, + Mips_DPSUB_U_W = 625, + Mips_DPSU_H_QBL = 626, + Mips_DPSU_H_QBR = 627, + Mips_DPSX_W_PH = 628, + Mips_DPS_W_PH = 629, + Mips_DROTR = 630, + Mips_DROTR32 = 631, + Mips_DROTRV = 632, + Mips_DSBH = 633, + Mips_DSDIV = 634, + Mips_DSHD = 635, + Mips_DSLL = 636, + Mips_DSLL32 = 637, + Mips_DSLL64_32 = 638, + Mips_DSLLV = 639, + Mips_DSRA = 640, + Mips_DSRA32 = 641, + Mips_DSRAV = 642, + Mips_DSRL = 643, + Mips_DSRL32 = 644, + Mips_DSRLV = 645, + Mips_DSUB = 646, + Mips_DSUBu = 647, + Mips_DUDIV = 648, + Mips_DivRxRy16 = 649, + Mips_DivuRxRy16 = 650, + Mips_EHB = 651, + Mips_EHB_MM = 652, + Mips_EI = 653, + Mips_EI_MM = 654, + Mips_ERET = 655, + Mips_ERET_MM = 656, + Mips_EXT = 657, + Mips_EXTP = 658, + Mips_EXTPDP = 659, + Mips_EXTPDPV = 660, + Mips_EXTPV = 661, + Mips_EXTRV_RS_W = 662, + Mips_EXTRV_R_W = 663, + Mips_EXTRV_S_H = 664, + Mips_EXTRV_W = 665, + Mips_EXTR_RS_W = 666, + Mips_EXTR_R_W = 667, + Mips_EXTR_S_H = 668, + Mips_EXTR_W = 669, + Mips_EXTS = 670, + Mips_EXTS32 = 671, + Mips_EXT_MM = 672, + Mips_ExtractElementF64 = 673, + Mips_ExtractElementF64_64 = 674, + Mips_FABS_D = 675, + Mips_FABS_D32 = 676, + Mips_FABS_D64 = 677, + Mips_FABS_MM = 678, + Mips_FABS_S = 679, + Mips_FABS_S_MM = 680, + Mips_FABS_W = 681, + Mips_FADD_D = 682, + Mips_FADD_D32 = 683, + Mips_FADD_D64 = 684, + Mips_FADD_MM = 685, + Mips_FADD_S = 686, + Mips_FADD_S_MM = 687, + Mips_FADD_W = 688, + Mips_FCAF_D = 689, + Mips_FCAF_W = 690, + Mips_FCEQ_D = 691, + Mips_FCEQ_W = 692, + Mips_FCLASS_D = 693, + Mips_FCLASS_W = 694, + Mips_FCLE_D = 695, + Mips_FCLE_W = 696, + Mips_FCLT_D = 697, + Mips_FCLT_W = 698, + Mips_FCMP_D32 = 699, + Mips_FCMP_D32_MM = 700, + Mips_FCMP_D64 = 701, + Mips_FCMP_S32 = 702, + Mips_FCMP_S32_MM = 703, + Mips_FCNE_D = 704, + Mips_FCNE_W = 705, + Mips_FCOR_D = 706, + Mips_FCOR_W = 707, + Mips_FCUEQ_D = 708, + Mips_FCUEQ_W = 709, + Mips_FCULE_D = 710, + Mips_FCULE_W = 711, + Mips_FCULT_D = 712, + Mips_FCULT_W = 713, + Mips_FCUNE_D = 714, + Mips_FCUNE_W = 715, + Mips_FCUN_D = 716, + Mips_FCUN_W = 717, + Mips_FDIV_D = 718, + Mips_FDIV_D32 = 719, + Mips_FDIV_D64 = 720, + Mips_FDIV_MM = 721, + Mips_FDIV_S = 722, + Mips_FDIV_S_MM = 723, + Mips_FDIV_W = 724, + Mips_FEXDO_H = 725, + Mips_FEXDO_W = 726, + Mips_FEXP2_D = 727, + Mips_FEXP2_D_1_PSEUDO = 728, + Mips_FEXP2_W = 729, + Mips_FEXP2_W_1_PSEUDO = 730, + Mips_FEXUPL_D = 731, + Mips_FEXUPL_W = 732, + Mips_FEXUPR_D = 733, + Mips_FEXUPR_W = 734, + Mips_FFINT_S_D = 735, + Mips_FFINT_S_W = 736, + Mips_FFINT_U_D = 737, + Mips_FFINT_U_W = 738, + Mips_FFQL_D = 739, + Mips_FFQL_W = 740, + Mips_FFQR_D = 741, + Mips_FFQR_W = 742, + Mips_FILL_B = 743, + Mips_FILL_D = 744, + Mips_FILL_FD_PSEUDO = 745, + Mips_FILL_FW_PSEUDO = 746, + Mips_FILL_H = 747, + Mips_FILL_W = 748, + Mips_FLOG2_D = 749, + Mips_FLOG2_W = 750, + Mips_FLOOR_L_D64 = 751, + Mips_FLOOR_L_S = 752, + Mips_FLOOR_W_D32 = 753, + Mips_FLOOR_W_D64 = 754, + Mips_FLOOR_W_MM = 755, + Mips_FLOOR_W_S = 756, + Mips_FLOOR_W_S_MM = 757, + Mips_FMADD_D = 758, + Mips_FMADD_W = 759, + Mips_FMAX_A_D = 760, + Mips_FMAX_A_W = 761, + Mips_FMAX_D = 762, + Mips_FMAX_W = 763, + Mips_FMIN_A_D = 764, + Mips_FMIN_A_W = 765, + Mips_FMIN_D = 766, + Mips_FMIN_W = 767, + Mips_FMOV_D32 = 768, + Mips_FMOV_D32_MM = 769, + Mips_FMOV_D64 = 770, + Mips_FMOV_S = 771, + Mips_FMOV_S_MM = 772, + Mips_FMSUB_D = 773, + Mips_FMSUB_W = 774, + Mips_FMUL_D = 775, + Mips_FMUL_D32 = 776, + Mips_FMUL_D64 = 777, + Mips_FMUL_MM = 778, + Mips_FMUL_S = 779, + Mips_FMUL_S_MM = 780, + Mips_FMUL_W = 781, + Mips_FNEG_D32 = 782, + Mips_FNEG_D64 = 783, + Mips_FNEG_MM = 784, + Mips_FNEG_S = 785, + Mips_FNEG_S_MM = 786, + Mips_FRCP_D = 787, + Mips_FRCP_W = 788, + Mips_FRINT_D = 789, + Mips_FRINT_W = 790, + Mips_FRSQRT_D = 791, + Mips_FRSQRT_W = 792, + Mips_FSAF_D = 793, + Mips_FSAF_W = 794, + Mips_FSEQ_D = 795, + Mips_FSEQ_W = 796, + Mips_FSLE_D = 797, + Mips_FSLE_W = 798, + Mips_FSLT_D = 799, + Mips_FSLT_W = 800, + Mips_FSNE_D = 801, + Mips_FSNE_W = 802, + Mips_FSOR_D = 803, + Mips_FSOR_W = 804, + Mips_FSQRT_D = 805, + Mips_FSQRT_D32 = 806, + Mips_FSQRT_D64 = 807, + Mips_FSQRT_MM = 808, + Mips_FSQRT_S = 809, + Mips_FSQRT_S_MM = 810, + Mips_FSQRT_W = 811, + Mips_FSUB_D = 812, + Mips_FSUB_D32 = 813, + Mips_FSUB_D64 = 814, + Mips_FSUB_MM = 815, + Mips_FSUB_S = 816, + Mips_FSUB_S_MM = 817, + Mips_FSUB_W = 818, + Mips_FSUEQ_D = 819, + Mips_FSUEQ_W = 820, + Mips_FSULE_D = 821, + Mips_FSULE_W = 822, + Mips_FSULT_D = 823, + Mips_FSULT_W = 824, + Mips_FSUNE_D = 825, + Mips_FSUNE_W = 826, + Mips_FSUN_D = 827, + Mips_FSUN_W = 828, + Mips_FTINT_S_D = 829, + Mips_FTINT_S_W = 830, + Mips_FTINT_U_D = 831, + Mips_FTINT_U_W = 832, + Mips_FTQ_H = 833, + Mips_FTQ_W = 834, + Mips_FTRUNC_S_D = 835, + Mips_FTRUNC_S_W = 836, + Mips_FTRUNC_U_D = 837, + Mips_FTRUNC_U_W = 838, + Mips_GotPrologue16 = 839, + Mips_HADD_S_D = 840, + Mips_HADD_S_H = 841, + Mips_HADD_S_W = 842, + Mips_HADD_U_D = 843, + Mips_HADD_U_H = 844, + Mips_HADD_U_W = 845, + Mips_HSUB_S_D = 846, + Mips_HSUB_S_H = 847, + Mips_HSUB_S_W = 848, + Mips_HSUB_U_D = 849, + Mips_HSUB_U_H = 850, + Mips_HSUB_U_W = 851, + Mips_ILVEV_B = 852, + Mips_ILVEV_D = 853, + Mips_ILVEV_H = 854, + Mips_ILVEV_W = 855, + Mips_ILVL_B = 856, + Mips_ILVL_D = 857, + Mips_ILVL_H = 858, + Mips_ILVL_W = 859, + Mips_ILVOD_B = 860, + Mips_ILVOD_D = 861, + Mips_ILVOD_H = 862, + Mips_ILVOD_W = 863, + Mips_ILVR_B = 864, + Mips_ILVR_D = 865, + Mips_ILVR_H = 866, + Mips_ILVR_W = 867, + Mips_INS = 868, + Mips_INSERT_B = 869, + Mips_INSERT_B_VIDX_PSEUDO = 870, + Mips_INSERT_D = 871, + Mips_INSERT_D_VIDX_PSEUDO = 872, + Mips_INSERT_FD_PSEUDO = 873, + Mips_INSERT_FD_VIDX_PSEUDO = 874, + Mips_INSERT_FW_PSEUDO = 875, + Mips_INSERT_FW_VIDX_PSEUDO = 876, + Mips_INSERT_H = 877, + Mips_INSERT_H_VIDX_PSEUDO = 878, + Mips_INSERT_W = 879, + Mips_INSERT_W_VIDX_PSEUDO = 880, + Mips_INSV = 881, + Mips_INSVE_B = 882, + Mips_INSVE_D = 883, + Mips_INSVE_H = 884, + Mips_INSVE_W = 885, + Mips_INS_MM = 886, + Mips_J = 887, + Mips_JAL = 888, + Mips_JALR = 889, + Mips_JALR16_MM = 890, + Mips_JALR64 = 891, + Mips_JALR64Pseudo = 892, + Mips_JALRPseudo = 893, + Mips_JALRS16_MM = 894, + Mips_JALRS_MM = 895, + Mips_JALR_HB = 896, + Mips_JALR_MM = 897, + Mips_JALS_MM = 898, + Mips_JALX = 899, + Mips_JALX_MM = 900, + Mips_JAL_MM = 901, + Mips_JIALC = 902, + Mips_JIC = 903, + Mips_JR = 904, + Mips_JR16_MM = 905, + Mips_JR64 = 906, + Mips_JRADDIUSP = 907, + Mips_JRC16_MM = 908, + Mips_JR_HB = 909, + Mips_JR_HB_R6 = 910, + Mips_JR_MM = 911, + Mips_J_MM = 912, + Mips_Jal16 = 913, + Mips_JalB16 = 914, + Mips_JalOneReg = 915, + Mips_JalTwoReg = 916, + Mips_JrRa16 = 917, + Mips_JrcRa16 = 918, + Mips_JrcRx16 = 919, + Mips_JumpLinkReg16 = 920, + Mips_LB = 921, + Mips_LB64 = 922, + Mips_LBU16_MM = 923, + Mips_LBUX = 924, + Mips_LB_MM = 925, + Mips_LBu = 926, + Mips_LBu64 = 927, + Mips_LBu_MM = 928, + Mips_LD = 929, + Mips_LDC1 = 930, + Mips_LDC164 = 931, + Mips_LDC1_MM = 932, + Mips_LDC2 = 933, + Mips_LDC2_R6 = 934, + Mips_LDC3 = 935, + Mips_LDI_B = 936, + Mips_LDI_D = 937, + Mips_LDI_H = 938, + Mips_LDI_W = 939, + Mips_LDL = 940, + Mips_LDPC = 941, + Mips_LDR = 942, + Mips_LDXC1 = 943, + Mips_LDXC164 = 944, + Mips_LD_B = 945, + Mips_LD_D = 946, + Mips_LD_H = 947, + Mips_LD_W = 948, + Mips_LEA_ADDiu = 949, + Mips_LEA_ADDiu64 = 950, + Mips_LEA_ADDiu_MM = 951, + Mips_LH = 952, + Mips_LH64 = 953, + Mips_LHU16_MM = 954, + Mips_LHX = 955, + Mips_LH_MM = 956, + Mips_LHu = 957, + Mips_LHu64 = 958, + Mips_LHu_MM = 959, + Mips_LI16_MM = 960, + Mips_LL = 961, + Mips_LLD = 962, + Mips_LLD_R6 = 963, + Mips_LL_MM = 964, + Mips_LL_R6 = 965, + Mips_LOAD_ACC128 = 966, + Mips_LOAD_ACC64 = 967, + Mips_LOAD_ACC64DSP = 968, + Mips_LOAD_CCOND_DSP = 969, + Mips_LONG_BRANCH_ADDiu = 970, + Mips_LONG_BRANCH_DADDiu = 971, + Mips_LONG_BRANCH_LUi = 972, + Mips_LSA = 973, + Mips_LSA_R6 = 974, + Mips_LUXC1 = 975, + Mips_LUXC164 = 976, + Mips_LUXC1_MM = 977, + Mips_LUi = 978, + Mips_LUi64 = 979, + Mips_LUi_MM = 980, + Mips_LW = 981, + Mips_LW16_MM = 982, + Mips_LW64 = 983, + Mips_LWC1 = 984, + Mips_LWC1_MM = 985, + Mips_LWC2 = 986, + Mips_LWC2_R6 = 987, + Mips_LWC3 = 988, + Mips_LWGP_MM = 989, + Mips_LWL = 990, + Mips_LWL64 = 991, + Mips_LWL_MM = 992, + Mips_LWM16_MM = 993, + Mips_LWM32_MM = 994, + Mips_LWM_MM = 995, + Mips_LWPC = 996, + Mips_LWP_MM = 997, + Mips_LWR = 998, + Mips_LWR64 = 999, + Mips_LWR_MM = 1000, + Mips_LWSP_MM = 1001, + Mips_LWUPC = 1002, + Mips_LWU_MM = 1003, + Mips_LWX = 1004, + Mips_LWXC1 = 1005, + Mips_LWXC1_MM = 1006, + Mips_LWXS_MM = 1007, + Mips_LW_MM = 1008, + Mips_LWu = 1009, + Mips_LbRxRyOffMemX16 = 1010, + Mips_LbuRxRyOffMemX16 = 1011, + Mips_LhRxRyOffMemX16 = 1012, + Mips_LhuRxRyOffMemX16 = 1013, + Mips_LiRxImm16 = 1014, + Mips_LiRxImmAlignX16 = 1015, + Mips_LiRxImmX16 = 1016, + Mips_LoadAddr32Imm = 1017, + Mips_LoadAddr32Reg = 1018, + Mips_LoadImm32Reg = 1019, + Mips_LoadImm64Reg = 1020, + Mips_LwConstant32 = 1021, + Mips_LwRxPcTcp16 = 1022, + Mips_LwRxPcTcpX16 = 1023, + Mips_LwRxRyOffMemX16 = 1024, + Mips_LwRxSpImmX16 = 1025, + Mips_MADD = 1026, + Mips_MADDF_D = 1027, + Mips_MADDF_S = 1028, + Mips_MADDR_Q_H = 1029, + Mips_MADDR_Q_W = 1030, + Mips_MADDU = 1031, + Mips_MADDU_DSP = 1032, + Mips_MADDU_MM = 1033, + Mips_MADDV_B = 1034, + Mips_MADDV_D = 1035, + Mips_MADDV_H = 1036, + Mips_MADDV_W = 1037, + Mips_MADD_D32 = 1038, + Mips_MADD_D32_MM = 1039, + Mips_MADD_D64 = 1040, + Mips_MADD_DSP = 1041, + Mips_MADD_MM = 1042, + Mips_MADD_Q_H = 1043, + Mips_MADD_Q_W = 1044, + Mips_MADD_S = 1045, + Mips_MADD_S_MM = 1046, + Mips_MAQ_SA_W_PHL = 1047, + Mips_MAQ_SA_W_PHR = 1048, + Mips_MAQ_S_W_PHL = 1049, + Mips_MAQ_S_W_PHR = 1050, + Mips_MAXA_D = 1051, + Mips_MAXA_S = 1052, + Mips_MAXI_S_B = 1053, + Mips_MAXI_S_D = 1054, + Mips_MAXI_S_H = 1055, + Mips_MAXI_S_W = 1056, + Mips_MAXI_U_B = 1057, + Mips_MAXI_U_D = 1058, + Mips_MAXI_U_H = 1059, + Mips_MAXI_U_W = 1060, + Mips_MAX_A_B = 1061, + Mips_MAX_A_D = 1062, + Mips_MAX_A_H = 1063, + Mips_MAX_A_W = 1064, + Mips_MAX_D = 1065, + Mips_MAX_S = 1066, + Mips_MAX_S_B = 1067, + Mips_MAX_S_D = 1068, + Mips_MAX_S_H = 1069, + Mips_MAX_S_W = 1070, + Mips_MAX_U_B = 1071, + Mips_MAX_U_D = 1072, + Mips_MAX_U_H = 1073, + Mips_MAX_U_W = 1074, + Mips_MFC0 = 1075, + Mips_MFC1 = 1076, + Mips_MFC1_MM = 1077, + Mips_MFC2 = 1078, + Mips_MFHC1_D32 = 1079, + Mips_MFHC1_D64 = 1080, + Mips_MFHC1_MM = 1081, + Mips_MFHI = 1082, + Mips_MFHI16_MM = 1083, + Mips_MFHI64 = 1084, + Mips_MFHI_DSP = 1085, + Mips_MFHI_MM = 1086, + Mips_MFLO = 1087, + Mips_MFLO16_MM = 1088, + Mips_MFLO64 = 1089, + Mips_MFLO_DSP = 1090, + Mips_MFLO_MM = 1091, + Mips_MINA_D = 1092, + Mips_MINA_S = 1093, + Mips_MINI_S_B = 1094, + Mips_MINI_S_D = 1095, + Mips_MINI_S_H = 1096, + Mips_MINI_S_W = 1097, + Mips_MINI_U_B = 1098, + Mips_MINI_U_D = 1099, + Mips_MINI_U_H = 1100, + Mips_MINI_U_W = 1101, + Mips_MIN_A_B = 1102, + Mips_MIN_A_D = 1103, + Mips_MIN_A_H = 1104, + Mips_MIN_A_W = 1105, + Mips_MIN_D = 1106, + Mips_MIN_S = 1107, + Mips_MIN_S_B = 1108, + Mips_MIN_S_D = 1109, + Mips_MIN_S_H = 1110, + Mips_MIN_S_W = 1111, + Mips_MIN_U_B = 1112, + Mips_MIN_U_D = 1113, + Mips_MIN_U_H = 1114, + Mips_MIN_U_W = 1115, + Mips_MIPSeh_return32 = 1116, + Mips_MIPSeh_return64 = 1117, + Mips_MOD = 1118, + Mips_MODSUB = 1119, + Mips_MODU = 1120, + Mips_MOD_S_B = 1121, + Mips_MOD_S_D = 1122, + Mips_MOD_S_H = 1123, + Mips_MOD_S_W = 1124, + Mips_MOD_U_B = 1125, + Mips_MOD_U_D = 1126, + Mips_MOD_U_H = 1127, + Mips_MOD_U_W = 1128, + Mips_MOVE16_MM = 1129, + Mips_MOVEP_MM = 1130, + Mips_MOVE_V = 1131, + Mips_MOVF_D32 = 1132, + Mips_MOVF_D32_MM = 1133, + Mips_MOVF_D64 = 1134, + Mips_MOVF_I = 1135, + Mips_MOVF_I64 = 1136, + Mips_MOVF_I_MM = 1137, + Mips_MOVF_S = 1138, + Mips_MOVF_S_MM = 1139, + Mips_MOVN_I64_D64 = 1140, + Mips_MOVN_I64_I = 1141, + Mips_MOVN_I64_I64 = 1142, + Mips_MOVN_I64_S = 1143, + Mips_MOVN_I_D32 = 1144, + Mips_MOVN_I_D32_MM = 1145, + Mips_MOVN_I_D64 = 1146, + Mips_MOVN_I_I = 1147, + Mips_MOVN_I_I64 = 1148, + Mips_MOVN_I_MM = 1149, + Mips_MOVN_I_S = 1150, + Mips_MOVN_I_S_MM = 1151, + Mips_MOVT_D32 = 1152, + Mips_MOVT_D32_MM = 1153, + Mips_MOVT_D64 = 1154, + Mips_MOVT_I = 1155, + Mips_MOVT_I64 = 1156, + Mips_MOVT_I_MM = 1157, + Mips_MOVT_S = 1158, + Mips_MOVT_S_MM = 1159, + Mips_MOVZ_I64_D64 = 1160, + Mips_MOVZ_I64_I = 1161, + Mips_MOVZ_I64_I64 = 1162, + Mips_MOVZ_I64_S = 1163, + Mips_MOVZ_I_D32 = 1164, + Mips_MOVZ_I_D32_MM = 1165, + Mips_MOVZ_I_D64 = 1166, + Mips_MOVZ_I_I = 1167, + Mips_MOVZ_I_I64 = 1168, + Mips_MOVZ_I_MM = 1169, + Mips_MOVZ_I_S = 1170, + Mips_MOVZ_I_S_MM = 1171, + Mips_MSUB = 1172, + Mips_MSUBF_D = 1173, + Mips_MSUBF_S = 1174, + Mips_MSUBR_Q_H = 1175, + Mips_MSUBR_Q_W = 1176, + Mips_MSUBU = 1177, + Mips_MSUBU_DSP = 1178, + Mips_MSUBU_MM = 1179, + Mips_MSUBV_B = 1180, + Mips_MSUBV_D = 1181, + Mips_MSUBV_H = 1182, + Mips_MSUBV_W = 1183, + Mips_MSUB_D32 = 1184, + Mips_MSUB_D32_MM = 1185, + Mips_MSUB_D64 = 1186, + Mips_MSUB_DSP = 1187, + Mips_MSUB_MM = 1188, + Mips_MSUB_Q_H = 1189, + Mips_MSUB_Q_W = 1190, + Mips_MSUB_S = 1191, + Mips_MSUB_S_MM = 1192, + Mips_MTC0 = 1193, + Mips_MTC1 = 1194, + Mips_MTC1_MM = 1195, + Mips_MTC2 = 1196, + Mips_MTHC1_D32 = 1197, + Mips_MTHC1_D64 = 1198, + Mips_MTHC1_MM = 1199, + Mips_MTHI = 1200, + Mips_MTHI64 = 1201, + Mips_MTHI_DSP = 1202, + Mips_MTHI_MM = 1203, + Mips_MTHLIP = 1204, + Mips_MTLO = 1205, + Mips_MTLO64 = 1206, + Mips_MTLO_DSP = 1207, + Mips_MTLO_MM = 1208, + Mips_MTM0 = 1209, + Mips_MTM1 = 1210, + Mips_MTM2 = 1211, + Mips_MTP0 = 1212, + Mips_MTP1 = 1213, + Mips_MTP2 = 1214, + Mips_MUH = 1215, + Mips_MUHU = 1216, + Mips_MUL = 1217, + Mips_MULEQ_S_W_PHL = 1218, + Mips_MULEQ_S_W_PHR = 1219, + Mips_MULEU_S_PH_QBL = 1220, + Mips_MULEU_S_PH_QBR = 1221, + Mips_MULQ_RS_PH = 1222, + Mips_MULQ_RS_W = 1223, + Mips_MULQ_S_PH = 1224, + Mips_MULQ_S_W = 1225, + Mips_MULR_Q_H = 1226, + Mips_MULR_Q_W = 1227, + Mips_MULSAQ_S_W_PH = 1228, + Mips_MULSA_W_PH = 1229, + Mips_MULT = 1230, + Mips_MULTU_DSP = 1231, + Mips_MULT_DSP = 1232, + Mips_MULT_MM = 1233, + Mips_MULTu = 1234, + Mips_MULTu_MM = 1235, + Mips_MULU = 1236, + Mips_MULV_B = 1237, + Mips_MULV_D = 1238, + Mips_MULV_H = 1239, + Mips_MULV_W = 1240, + Mips_MUL_MM = 1241, + Mips_MUL_PH = 1242, + Mips_MUL_Q_H = 1243, + Mips_MUL_Q_W = 1244, + Mips_MUL_R6 = 1245, + Mips_MUL_S_PH = 1246, + Mips_Mfhi16 = 1247, + Mips_Mflo16 = 1248, + Mips_Move32R16 = 1249, + Mips_MoveR3216 = 1250, + Mips_MultRxRy16 = 1251, + Mips_MultRxRyRz16 = 1252, + Mips_MultuRxRy16 = 1253, + Mips_MultuRxRyRz16 = 1254, + Mips_NLOC_B = 1255, + Mips_NLOC_D = 1256, + Mips_NLOC_H = 1257, + Mips_NLOC_W = 1258, + Mips_NLZC_B = 1259, + Mips_NLZC_D = 1260, + Mips_NLZC_H = 1261, + Mips_NLZC_W = 1262, + Mips_NMADD_D32 = 1263, + Mips_NMADD_D32_MM = 1264, + Mips_NMADD_D64 = 1265, + Mips_NMADD_S = 1266, + Mips_NMADD_S_MM = 1267, + Mips_NMSUB_D32 = 1268, + Mips_NMSUB_D32_MM = 1269, + Mips_NMSUB_D64 = 1270, + Mips_NMSUB_S = 1271, + Mips_NMSUB_S_MM = 1272, + Mips_NOP = 1273, + Mips_NOR = 1274, + Mips_NOR64 = 1275, + Mips_NORI_B = 1276, + Mips_NOR_MM = 1277, + Mips_NOR_V = 1278, + Mips_NOR_V_D_PSEUDO = 1279, + Mips_NOR_V_H_PSEUDO = 1280, + Mips_NOR_V_W_PSEUDO = 1281, + Mips_NOT16_MM = 1282, + Mips_NegRxRy16 = 1283, + Mips_NotRxRy16 = 1284, + Mips_OR = 1285, + Mips_OR16_MM = 1286, + Mips_OR64 = 1287, + Mips_ORI_B = 1288, + Mips_OR_MM = 1289, + Mips_OR_V = 1290, + Mips_OR_V_D_PSEUDO = 1291, + Mips_OR_V_H_PSEUDO = 1292, + Mips_OR_V_W_PSEUDO = 1293, + Mips_ORi = 1294, + Mips_ORi64 = 1295, + Mips_ORi_MM = 1296, + Mips_OrRxRxRy16 = 1297, + Mips_PACKRL_PH = 1298, + Mips_PAUSE = 1299, + Mips_PAUSE_MM = 1300, + Mips_PCKEV_B = 1301, + Mips_PCKEV_D = 1302, + Mips_PCKEV_H = 1303, + Mips_PCKEV_W = 1304, + Mips_PCKOD_B = 1305, + Mips_PCKOD_D = 1306, + Mips_PCKOD_H = 1307, + Mips_PCKOD_W = 1308, + Mips_PCNT_B = 1309, + Mips_PCNT_D = 1310, + Mips_PCNT_H = 1311, + Mips_PCNT_W = 1312, + Mips_PICK_PH = 1313, + Mips_PICK_QB = 1314, + Mips_POP = 1315, + Mips_PRECEQU_PH_QBL = 1316, + Mips_PRECEQU_PH_QBLA = 1317, + Mips_PRECEQU_PH_QBR = 1318, + Mips_PRECEQU_PH_QBRA = 1319, + Mips_PRECEQ_W_PHL = 1320, + Mips_PRECEQ_W_PHR = 1321, + Mips_PRECEU_PH_QBL = 1322, + Mips_PRECEU_PH_QBLA = 1323, + Mips_PRECEU_PH_QBR = 1324, + Mips_PRECEU_PH_QBRA = 1325, + Mips_PRECRQU_S_QB_PH = 1326, + Mips_PRECRQ_PH_W = 1327, + Mips_PRECRQ_QB_PH = 1328, + Mips_PRECRQ_RS_PH_W = 1329, + Mips_PRECR_QB_PH = 1330, + Mips_PRECR_SRA_PH_W = 1331, + Mips_PRECR_SRA_R_PH_W = 1332, + Mips_PREF = 1333, + Mips_PREF_MM = 1334, + Mips_PREF_R6 = 1335, + Mips_PREPEND = 1336, + Mips_PseudoCMPU_EQ_QB = 1337, + Mips_PseudoCMPU_LE_QB = 1338, + Mips_PseudoCMPU_LT_QB = 1339, + Mips_PseudoCMP_EQ_PH = 1340, + Mips_PseudoCMP_LE_PH = 1341, + Mips_PseudoCMP_LT_PH = 1342, + Mips_PseudoCVT_D32_W = 1343, + Mips_PseudoCVT_D64_L = 1344, + Mips_PseudoCVT_D64_W = 1345, + Mips_PseudoCVT_S_L = 1346, + Mips_PseudoCVT_S_W = 1347, + Mips_PseudoDMULT = 1348, + Mips_PseudoDMULTu = 1349, + Mips_PseudoDSDIV = 1350, + Mips_PseudoDUDIV = 1351, + Mips_PseudoIndirectBranch = 1352, + Mips_PseudoIndirectBranch64 = 1353, + Mips_PseudoMADD = 1354, + Mips_PseudoMADDU = 1355, + Mips_PseudoMFHI = 1356, + Mips_PseudoMFHI64 = 1357, + Mips_PseudoMFLO = 1358, + Mips_PseudoMFLO64 = 1359, + Mips_PseudoMSUB = 1360, + Mips_PseudoMSUBU = 1361, + Mips_PseudoMTLOHI = 1362, + Mips_PseudoMTLOHI64 = 1363, + Mips_PseudoMTLOHI_DSP = 1364, + Mips_PseudoMULT = 1365, + Mips_PseudoMULTu = 1366, + Mips_PseudoPICK_PH = 1367, + Mips_PseudoPICK_QB = 1368, + Mips_PseudoReturn = 1369, + Mips_PseudoReturn64 = 1370, + Mips_PseudoSDIV = 1371, + Mips_PseudoSELECTFP_F_D32 = 1372, + Mips_PseudoSELECTFP_F_D64 = 1373, + Mips_PseudoSELECTFP_F_I = 1374, + Mips_PseudoSELECTFP_F_I64 = 1375, + Mips_PseudoSELECTFP_F_S = 1376, + Mips_PseudoSELECTFP_T_D32 = 1377, + Mips_PseudoSELECTFP_T_D64 = 1378, + Mips_PseudoSELECTFP_T_I = 1379, + Mips_PseudoSELECTFP_T_I64 = 1380, + Mips_PseudoSELECTFP_T_S = 1381, + Mips_PseudoSELECT_D32 = 1382, + Mips_PseudoSELECT_D64 = 1383, + Mips_PseudoSELECT_I = 1384, + Mips_PseudoSELECT_I64 = 1385, + Mips_PseudoSELECT_S = 1386, + Mips_PseudoUDIV = 1387, + Mips_RADDU_W_QB = 1388, + Mips_RDDSP = 1389, + Mips_RDHWR = 1390, + Mips_RDHWR64 = 1391, + Mips_RDHWR_MM = 1392, + Mips_REPLV_PH = 1393, + Mips_REPLV_QB = 1394, + Mips_REPL_PH = 1395, + Mips_REPL_QB = 1396, + Mips_RINT_D = 1397, + Mips_RINT_S = 1398, + Mips_ROTR = 1399, + Mips_ROTRV = 1400, + Mips_ROTRV_MM = 1401, + Mips_ROTR_MM = 1402, + Mips_ROUND_L_D64 = 1403, + Mips_ROUND_L_S = 1404, + Mips_ROUND_W_D32 = 1405, + Mips_ROUND_W_D64 = 1406, + Mips_ROUND_W_MM = 1407, + Mips_ROUND_W_S = 1408, + Mips_ROUND_W_S_MM = 1409, + Mips_Restore16 = 1410, + Mips_RestoreX16 = 1411, + Mips_RetRA = 1412, + Mips_RetRA16 = 1413, + Mips_SAT_S_B = 1414, + Mips_SAT_S_D = 1415, + Mips_SAT_S_H = 1416, + Mips_SAT_S_W = 1417, + Mips_SAT_U_B = 1418, + Mips_SAT_U_D = 1419, + Mips_SAT_U_H = 1420, + Mips_SAT_U_W = 1421, + Mips_SB = 1422, + Mips_SB16_MM = 1423, + Mips_SB64 = 1424, + Mips_SB_MM = 1425, + Mips_SC = 1426, + Mips_SCD = 1427, + Mips_SCD_R6 = 1428, + Mips_SC_MM = 1429, + Mips_SC_R6 = 1430, + Mips_SD = 1431, + Mips_SDBBP = 1432, + Mips_SDBBP16_MM = 1433, + Mips_SDBBP_MM = 1434, + Mips_SDBBP_R6 = 1435, + Mips_SDC1 = 1436, + Mips_SDC164 = 1437, + Mips_SDC1_MM = 1438, + Mips_SDC2 = 1439, + Mips_SDC2_R6 = 1440, + Mips_SDC3 = 1441, + Mips_SDIV = 1442, + Mips_SDIV_MM = 1443, + Mips_SDL = 1444, + Mips_SDR = 1445, + Mips_SDXC1 = 1446, + Mips_SDXC164 = 1447, + Mips_SEB = 1448, + Mips_SEB64 = 1449, + Mips_SEB_MM = 1450, + Mips_SEH = 1451, + Mips_SEH64 = 1452, + Mips_SEH_MM = 1453, + Mips_SELEQZ = 1454, + Mips_SELEQZ64 = 1455, + Mips_SELEQZ_D = 1456, + Mips_SELEQZ_S = 1457, + Mips_SELNEZ = 1458, + Mips_SELNEZ64 = 1459, + Mips_SELNEZ_D = 1460, + Mips_SELNEZ_S = 1461, + Mips_SEL_D = 1462, + Mips_SEL_S = 1463, + Mips_SEQ = 1464, + Mips_SEQi = 1465, + Mips_SH = 1466, + Mips_SH16_MM = 1467, + Mips_SH64 = 1468, + Mips_SHF_B = 1469, + Mips_SHF_H = 1470, + Mips_SHF_W = 1471, + Mips_SHILO = 1472, + Mips_SHILOV = 1473, + Mips_SHLLV_PH = 1474, + Mips_SHLLV_QB = 1475, + Mips_SHLLV_S_PH = 1476, + Mips_SHLLV_S_W = 1477, + Mips_SHLL_PH = 1478, + Mips_SHLL_QB = 1479, + Mips_SHLL_S_PH = 1480, + Mips_SHLL_S_W = 1481, + Mips_SHRAV_PH = 1482, + Mips_SHRAV_QB = 1483, + Mips_SHRAV_R_PH = 1484, + Mips_SHRAV_R_QB = 1485, + Mips_SHRAV_R_W = 1486, + Mips_SHRA_PH = 1487, + Mips_SHRA_QB = 1488, + Mips_SHRA_R_PH = 1489, + Mips_SHRA_R_QB = 1490, + Mips_SHRA_R_W = 1491, + Mips_SHRLV_PH = 1492, + Mips_SHRLV_QB = 1493, + Mips_SHRL_PH = 1494, + Mips_SHRL_QB = 1495, + Mips_SH_MM = 1496, + Mips_SLDI_B = 1497, + Mips_SLDI_D = 1498, + Mips_SLDI_H = 1499, + Mips_SLDI_W = 1500, + Mips_SLD_B = 1501, + Mips_SLD_D = 1502, + Mips_SLD_H = 1503, + Mips_SLD_W = 1504, + Mips_SLL = 1505, + Mips_SLL16_MM = 1506, + Mips_SLL64_32 = 1507, + Mips_SLL64_64 = 1508, + Mips_SLLI_B = 1509, + Mips_SLLI_D = 1510, + Mips_SLLI_H = 1511, + Mips_SLLI_W = 1512, + Mips_SLLV = 1513, + Mips_SLLV_MM = 1514, + Mips_SLL_B = 1515, + Mips_SLL_D = 1516, + Mips_SLL_H = 1517, + Mips_SLL_MM = 1518, + Mips_SLL_W = 1519, + Mips_SLT = 1520, + Mips_SLT64 = 1521, + Mips_SLT_MM = 1522, + Mips_SLTi = 1523, + Mips_SLTi64 = 1524, + Mips_SLTi_MM = 1525, + Mips_SLTiu = 1526, + Mips_SLTiu64 = 1527, + Mips_SLTiu_MM = 1528, + Mips_SLTu = 1529, + Mips_SLTu64 = 1530, + Mips_SLTu_MM = 1531, + Mips_SNE = 1532, + Mips_SNEi = 1533, + Mips_SNZ_B_PSEUDO = 1534, + Mips_SNZ_D_PSEUDO = 1535, + Mips_SNZ_H_PSEUDO = 1536, + Mips_SNZ_V_PSEUDO = 1537, + Mips_SNZ_W_PSEUDO = 1538, + Mips_SPLATI_B = 1539, + Mips_SPLATI_D = 1540, + Mips_SPLATI_H = 1541, + Mips_SPLATI_W = 1542, + Mips_SPLAT_B = 1543, + Mips_SPLAT_D = 1544, + Mips_SPLAT_H = 1545, + Mips_SPLAT_W = 1546, + Mips_SRA = 1547, + Mips_SRAI_B = 1548, + Mips_SRAI_D = 1549, + Mips_SRAI_H = 1550, + Mips_SRAI_W = 1551, + Mips_SRARI_B = 1552, + Mips_SRARI_D = 1553, + Mips_SRARI_H = 1554, + Mips_SRARI_W = 1555, + Mips_SRAR_B = 1556, + Mips_SRAR_D = 1557, + Mips_SRAR_H = 1558, + Mips_SRAR_W = 1559, + Mips_SRAV = 1560, + Mips_SRAV_MM = 1561, + Mips_SRA_B = 1562, + Mips_SRA_D = 1563, + Mips_SRA_H = 1564, + Mips_SRA_MM = 1565, + Mips_SRA_W = 1566, + Mips_SRL = 1567, + Mips_SRL16_MM = 1568, + Mips_SRLI_B = 1569, + Mips_SRLI_D = 1570, + Mips_SRLI_H = 1571, + Mips_SRLI_W = 1572, + Mips_SRLRI_B = 1573, + Mips_SRLRI_D = 1574, + Mips_SRLRI_H = 1575, + Mips_SRLRI_W = 1576, + Mips_SRLR_B = 1577, + Mips_SRLR_D = 1578, + Mips_SRLR_H = 1579, + Mips_SRLR_W = 1580, + Mips_SRLV = 1581, + Mips_SRLV_MM = 1582, + Mips_SRL_B = 1583, + Mips_SRL_D = 1584, + Mips_SRL_H = 1585, + Mips_SRL_MM = 1586, + Mips_SRL_W = 1587, + Mips_SSNOP = 1588, + Mips_SSNOP_MM = 1589, + Mips_STORE_ACC128 = 1590, + Mips_STORE_ACC64 = 1591, + Mips_STORE_ACC64DSP = 1592, + Mips_STORE_CCOND_DSP = 1593, + Mips_ST_B = 1594, + Mips_ST_D = 1595, + Mips_ST_H = 1596, + Mips_ST_W = 1597, + Mips_SUB = 1598, + Mips_SUBQH_PH = 1599, + Mips_SUBQH_R_PH = 1600, + Mips_SUBQH_R_W = 1601, + Mips_SUBQH_W = 1602, + Mips_SUBQ_PH = 1603, + Mips_SUBQ_S_PH = 1604, + Mips_SUBQ_S_W = 1605, + Mips_SUBSUS_U_B = 1606, + Mips_SUBSUS_U_D = 1607, + Mips_SUBSUS_U_H = 1608, + Mips_SUBSUS_U_W = 1609, + Mips_SUBSUU_S_B = 1610, + Mips_SUBSUU_S_D = 1611, + Mips_SUBSUU_S_H = 1612, + Mips_SUBSUU_S_W = 1613, + Mips_SUBS_S_B = 1614, + Mips_SUBS_S_D = 1615, + Mips_SUBS_S_H = 1616, + Mips_SUBS_S_W = 1617, + Mips_SUBS_U_B = 1618, + Mips_SUBS_U_D = 1619, + Mips_SUBS_U_H = 1620, + Mips_SUBS_U_W = 1621, + Mips_SUBU16_MM = 1622, + Mips_SUBUH_QB = 1623, + Mips_SUBUH_R_QB = 1624, + Mips_SUBU_PH = 1625, + Mips_SUBU_QB = 1626, + Mips_SUBU_S_PH = 1627, + Mips_SUBU_S_QB = 1628, + Mips_SUBVI_B = 1629, + Mips_SUBVI_D = 1630, + Mips_SUBVI_H = 1631, + Mips_SUBVI_W = 1632, + Mips_SUBV_B = 1633, + Mips_SUBV_D = 1634, + Mips_SUBV_H = 1635, + Mips_SUBV_W = 1636, + Mips_SUB_MM = 1637, + Mips_SUBu = 1638, + Mips_SUBu_MM = 1639, + Mips_SUXC1 = 1640, + Mips_SUXC164 = 1641, + Mips_SUXC1_MM = 1642, + Mips_SW = 1643, + Mips_SW16_MM = 1644, + Mips_SW64 = 1645, + Mips_SWC1 = 1646, + Mips_SWC1_MM = 1647, + Mips_SWC2 = 1648, + Mips_SWC2_R6 = 1649, + Mips_SWC3 = 1650, + Mips_SWL = 1651, + Mips_SWL64 = 1652, + Mips_SWL_MM = 1653, + Mips_SWM16_MM = 1654, + Mips_SWM32_MM = 1655, + Mips_SWM_MM = 1656, + Mips_SWP_MM = 1657, + Mips_SWR = 1658, + Mips_SWR64 = 1659, + Mips_SWR_MM = 1660, + Mips_SWSP_MM = 1661, + Mips_SWXC1 = 1662, + Mips_SWXC1_MM = 1663, + Mips_SW_MM = 1664, + Mips_SYNC = 1665, + Mips_SYNCI = 1666, + Mips_SYNC_MM = 1667, + Mips_SYSCALL = 1668, + Mips_SYSCALL_MM = 1669, + Mips_SZ_B_PSEUDO = 1670, + Mips_SZ_D_PSEUDO = 1671, + Mips_SZ_H_PSEUDO = 1672, + Mips_SZ_V_PSEUDO = 1673, + Mips_SZ_W_PSEUDO = 1674, + Mips_Save16 = 1675, + Mips_SaveX16 = 1676, + Mips_SbRxRyOffMemX16 = 1677, + Mips_SebRx16 = 1678, + Mips_SehRx16 = 1679, + Mips_SelBeqZ = 1680, + Mips_SelBneZ = 1681, + Mips_SelTBteqZCmp = 1682, + Mips_SelTBteqZCmpi = 1683, + Mips_SelTBteqZSlt = 1684, + Mips_SelTBteqZSlti = 1685, + Mips_SelTBteqZSltiu = 1686, + Mips_SelTBteqZSltu = 1687, + Mips_SelTBtneZCmp = 1688, + Mips_SelTBtneZCmpi = 1689, + Mips_SelTBtneZSlt = 1690, + Mips_SelTBtneZSlti = 1691, + Mips_SelTBtneZSltiu = 1692, + Mips_SelTBtneZSltu = 1693, + Mips_ShRxRyOffMemX16 = 1694, + Mips_SllX16 = 1695, + Mips_SllvRxRy16 = 1696, + Mips_SltCCRxRy16 = 1697, + Mips_SltRxRy16 = 1698, + Mips_SltiCCRxImmX16 = 1699, + Mips_SltiRxImm16 = 1700, + Mips_SltiRxImmX16 = 1701, + Mips_SltiuCCRxImmX16 = 1702, + Mips_SltiuRxImm16 = 1703, + Mips_SltiuRxImmX16 = 1704, + Mips_SltuCCRxRy16 = 1705, + Mips_SltuRxRy16 = 1706, + Mips_SltuRxRyRz16 = 1707, + Mips_SraX16 = 1708, + Mips_SravRxRy16 = 1709, + Mips_SrlX16 = 1710, + Mips_SrlvRxRy16 = 1711, + Mips_SubuRxRyRz16 = 1712, + Mips_SwRxRyOffMemX16 = 1713, + Mips_SwRxSpImmX16 = 1714, + Mips_TAILCALL = 1715, + Mips_TAILCALL64_R = 1716, + Mips_TAILCALL_R = 1717, + Mips_TEQ = 1718, + Mips_TEQI = 1719, + Mips_TEQI_MM = 1720, + Mips_TEQ_MM = 1721, + Mips_TGE = 1722, + Mips_TGEI = 1723, + Mips_TGEIU = 1724, + Mips_TGEIU_MM = 1725, + Mips_TGEI_MM = 1726, + Mips_TGEU = 1727, + Mips_TGEU_MM = 1728, + Mips_TGE_MM = 1729, + Mips_TLBP = 1730, + Mips_TLBP_MM = 1731, + Mips_TLBR = 1732, + Mips_TLBR_MM = 1733, + Mips_TLBWI = 1734, + Mips_TLBWI_MM = 1735, + Mips_TLBWR = 1736, + Mips_TLBWR_MM = 1737, + Mips_TLT = 1738, + Mips_TLTI = 1739, + Mips_TLTIU_MM = 1740, + Mips_TLTI_MM = 1741, + Mips_TLTU = 1742, + Mips_TLTU_MM = 1743, + Mips_TLT_MM = 1744, + Mips_TNE = 1745, + Mips_TNEI = 1746, + Mips_TNEI_MM = 1747, + Mips_TNE_MM = 1748, + Mips_TRAP = 1749, + Mips_TRUNC_L_D64 = 1750, + Mips_TRUNC_L_S = 1751, + Mips_TRUNC_W_D32 = 1752, + Mips_TRUNC_W_D64 = 1753, + Mips_TRUNC_W_MM = 1754, + Mips_TRUNC_W_S = 1755, + Mips_TRUNC_W_S_MM = 1756, + Mips_TTLTIU = 1757, + Mips_UDIV = 1758, + Mips_UDIV_MM = 1759, + Mips_V3MULU = 1760, + Mips_VMM0 = 1761, + Mips_VMULU = 1762, + Mips_VSHF_B = 1763, + Mips_VSHF_D = 1764, + Mips_VSHF_H = 1765, + Mips_VSHF_W = 1766, + Mips_WAIT = 1767, + Mips_WAIT_MM = 1768, + Mips_WRDSP = 1769, + Mips_WSBH = 1770, + Mips_WSBH_MM = 1771, + Mips_XOR = 1772, + Mips_XOR16_MM = 1773, + Mips_XOR64 = 1774, + Mips_XORI_B = 1775, + Mips_XOR_MM = 1776, + Mips_XOR_V = 1777, + Mips_XOR_V_D_PSEUDO = 1778, + Mips_XOR_V_H_PSEUDO = 1779, + Mips_XOR_V_W_PSEUDO = 1780, + Mips_XORi = 1781, + Mips_XORi64 = 1782, + Mips_XORi_MM = 1783, + Mips_XorRxRxRy16 = 1784, + Mips_INSTRUCTION_LIST_END = 1785 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/Mips/MipsGenRegisterInfo.inc new file mode 100644 index 0000000..cdce182 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsGenRegisterInfo.inc @@ -0,0 +1,1679 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + Mips_NoRegister, + Mips_AT = 1, + Mips_DSPCCond = 2, + Mips_DSPCarry = 3, + Mips_DSPEFI = 4, + Mips_DSPOutFlag = 5, + Mips_DSPPos = 6, + Mips_DSPSCount = 7, + Mips_FP = 8, + Mips_GP = 9, + Mips_MSAAccess = 10, + Mips_MSACSR = 11, + Mips_MSAIR = 12, + Mips_MSAMap = 13, + Mips_MSAModify = 14, + Mips_MSARequest = 15, + Mips_MSASave = 16, + Mips_MSAUnmap = 17, + Mips_PC = 18, + Mips_RA = 19, + Mips_SP = 20, + Mips_ZERO = 21, + Mips_A0 = 22, + Mips_A1 = 23, + Mips_A2 = 24, + Mips_A3 = 25, + Mips_AC0 = 26, + Mips_AC1 = 27, + Mips_AC2 = 28, + Mips_AC3 = 29, + Mips_AT_64 = 30, + Mips_CC0 = 31, + Mips_CC1 = 32, + Mips_CC2 = 33, + Mips_CC3 = 34, + Mips_CC4 = 35, + Mips_CC5 = 36, + Mips_CC6 = 37, + Mips_CC7 = 38, + Mips_COP20 = 39, + Mips_COP21 = 40, + Mips_COP22 = 41, + Mips_COP23 = 42, + Mips_COP24 = 43, + Mips_COP25 = 44, + Mips_COP26 = 45, + Mips_COP27 = 46, + Mips_COP28 = 47, + Mips_COP29 = 48, + Mips_COP30 = 49, + Mips_COP31 = 50, + Mips_COP32 = 51, + Mips_COP33 = 52, + Mips_COP34 = 53, + Mips_COP35 = 54, + Mips_COP36 = 55, + Mips_COP37 = 56, + Mips_COP38 = 57, + Mips_COP39 = 58, + Mips_COP210 = 59, + Mips_COP211 = 60, + Mips_COP212 = 61, + Mips_COP213 = 62, + Mips_COP214 = 63, + Mips_COP215 = 64, + Mips_COP216 = 65, + Mips_COP217 = 66, + Mips_COP218 = 67, + Mips_COP219 = 68, + Mips_COP220 = 69, + Mips_COP221 = 70, + Mips_COP222 = 71, + Mips_COP223 = 72, + Mips_COP224 = 73, + Mips_COP225 = 74, + Mips_COP226 = 75, + Mips_COP227 = 76, + Mips_COP228 = 77, + Mips_COP229 = 78, + Mips_COP230 = 79, + Mips_COP231 = 80, + Mips_COP310 = 81, + Mips_COP311 = 82, + Mips_COP312 = 83, + Mips_COP313 = 84, + Mips_COP314 = 85, + Mips_COP315 = 86, + Mips_COP316 = 87, + Mips_COP317 = 88, + Mips_COP318 = 89, + Mips_COP319 = 90, + Mips_COP320 = 91, + Mips_COP321 = 92, + Mips_COP322 = 93, + Mips_COP323 = 94, + Mips_COP324 = 95, + Mips_COP325 = 96, + Mips_COP326 = 97, + Mips_COP327 = 98, + Mips_COP328 = 99, + Mips_COP329 = 100, + Mips_COP330 = 101, + Mips_COP331 = 102, + Mips_D0 = 103, + Mips_D1 = 104, + Mips_D2 = 105, + Mips_D3 = 106, + Mips_D4 = 107, + Mips_D5 = 108, + Mips_D6 = 109, + Mips_D7 = 110, + Mips_D8 = 111, + Mips_D9 = 112, + Mips_D10 = 113, + Mips_D11 = 114, + Mips_D12 = 115, + Mips_D13 = 116, + Mips_D14 = 117, + Mips_D15 = 118, + Mips_DSPOutFlag20 = 119, + Mips_DSPOutFlag21 = 120, + Mips_DSPOutFlag22 = 121, + Mips_DSPOutFlag23 = 122, + Mips_F0 = 123, + Mips_F1 = 124, + Mips_F2 = 125, + Mips_F3 = 126, + Mips_F4 = 127, + Mips_F5 = 128, + Mips_F6 = 129, + Mips_F7 = 130, + Mips_F8 = 131, + Mips_F9 = 132, + Mips_F10 = 133, + Mips_F11 = 134, + Mips_F12 = 135, + Mips_F13 = 136, + Mips_F14 = 137, + Mips_F15 = 138, + Mips_F16 = 139, + Mips_F17 = 140, + Mips_F18 = 141, + Mips_F19 = 142, + Mips_F20 = 143, + Mips_F21 = 144, + Mips_F22 = 145, + Mips_F23 = 146, + Mips_F24 = 147, + Mips_F25 = 148, + Mips_F26 = 149, + Mips_F27 = 150, + Mips_F28 = 151, + Mips_F29 = 152, + Mips_F30 = 153, + Mips_F31 = 154, + Mips_FCC0 = 155, + Mips_FCC1 = 156, + Mips_FCC2 = 157, + Mips_FCC3 = 158, + Mips_FCC4 = 159, + Mips_FCC5 = 160, + Mips_FCC6 = 161, + Mips_FCC7 = 162, + Mips_FCR0 = 163, + Mips_FCR1 = 164, + Mips_FCR2 = 165, + Mips_FCR3 = 166, + Mips_FCR4 = 167, + Mips_FCR5 = 168, + Mips_FCR6 = 169, + Mips_FCR7 = 170, + Mips_FCR8 = 171, + Mips_FCR9 = 172, + Mips_FCR10 = 173, + Mips_FCR11 = 174, + Mips_FCR12 = 175, + Mips_FCR13 = 176, + Mips_FCR14 = 177, + Mips_FCR15 = 178, + Mips_FCR16 = 179, + Mips_FCR17 = 180, + Mips_FCR18 = 181, + Mips_FCR19 = 182, + Mips_FCR20 = 183, + Mips_FCR21 = 184, + Mips_FCR22 = 185, + Mips_FCR23 = 186, + Mips_FCR24 = 187, + Mips_FCR25 = 188, + Mips_FCR26 = 189, + Mips_FCR27 = 190, + Mips_FCR28 = 191, + Mips_FCR29 = 192, + Mips_FCR30 = 193, + Mips_FCR31 = 194, + Mips_FP_64 = 195, + Mips_F_HI0 = 196, + Mips_F_HI1 = 197, + Mips_F_HI2 = 198, + Mips_F_HI3 = 199, + Mips_F_HI4 = 200, + Mips_F_HI5 = 201, + Mips_F_HI6 = 202, + Mips_F_HI7 = 203, + Mips_F_HI8 = 204, + Mips_F_HI9 = 205, + Mips_F_HI10 = 206, + Mips_F_HI11 = 207, + Mips_F_HI12 = 208, + Mips_F_HI13 = 209, + Mips_F_HI14 = 210, + Mips_F_HI15 = 211, + Mips_F_HI16 = 212, + Mips_F_HI17 = 213, + Mips_F_HI18 = 214, + Mips_F_HI19 = 215, + Mips_F_HI20 = 216, + Mips_F_HI21 = 217, + Mips_F_HI22 = 218, + Mips_F_HI23 = 219, + Mips_F_HI24 = 220, + Mips_F_HI25 = 221, + Mips_F_HI26 = 222, + Mips_F_HI27 = 223, + Mips_F_HI28 = 224, + Mips_F_HI29 = 225, + Mips_F_HI30 = 226, + Mips_F_HI31 = 227, + Mips_GP_64 = 228, + Mips_HI0 = 229, + Mips_HI1 = 230, + Mips_HI2 = 231, + Mips_HI3 = 232, + Mips_HWR0 = 233, + Mips_HWR1 = 234, + Mips_HWR2 = 235, + Mips_HWR3 = 236, + Mips_HWR4 = 237, + Mips_HWR5 = 238, + Mips_HWR6 = 239, + Mips_HWR7 = 240, + Mips_HWR8 = 241, + Mips_HWR9 = 242, + Mips_HWR10 = 243, + Mips_HWR11 = 244, + Mips_HWR12 = 245, + Mips_HWR13 = 246, + Mips_HWR14 = 247, + Mips_HWR15 = 248, + Mips_HWR16 = 249, + Mips_HWR17 = 250, + Mips_HWR18 = 251, + Mips_HWR19 = 252, + Mips_HWR20 = 253, + Mips_HWR21 = 254, + Mips_HWR22 = 255, + Mips_HWR23 = 256, + Mips_HWR24 = 257, + Mips_HWR25 = 258, + Mips_HWR26 = 259, + Mips_HWR27 = 260, + Mips_HWR28 = 261, + Mips_HWR29 = 262, + Mips_HWR30 = 263, + Mips_HWR31 = 264, + Mips_K0 = 265, + Mips_K1 = 266, + Mips_LO0 = 267, + Mips_LO1 = 268, + Mips_LO2 = 269, + Mips_LO3 = 270, + Mips_MPL0 = 271, + Mips_MPL1 = 272, + Mips_MPL2 = 273, + Mips_P0 = 274, + Mips_P1 = 275, + Mips_P2 = 276, + Mips_RA_64 = 277, + Mips_S0 = 278, + Mips_S1 = 279, + Mips_S2 = 280, + Mips_S3 = 281, + Mips_S4 = 282, + Mips_S5 = 283, + Mips_S6 = 284, + Mips_S7 = 285, + Mips_SP_64 = 286, + Mips_T0 = 287, + Mips_T1 = 288, + Mips_T2 = 289, + Mips_T3 = 290, + Mips_T4 = 291, + Mips_T5 = 292, + Mips_T6 = 293, + Mips_T7 = 294, + Mips_T8 = 295, + Mips_T9 = 296, + Mips_V0 = 297, + Mips_V1 = 298, + Mips_W0 = 299, + Mips_W1 = 300, + Mips_W2 = 301, + Mips_W3 = 302, + Mips_W4 = 303, + Mips_W5 = 304, + Mips_W6 = 305, + Mips_W7 = 306, + Mips_W8 = 307, + Mips_W9 = 308, + Mips_W10 = 309, + Mips_W11 = 310, + Mips_W12 = 311, + Mips_W13 = 312, + Mips_W14 = 313, + Mips_W15 = 314, + Mips_W16 = 315, + Mips_W17 = 316, + Mips_W18 = 317, + Mips_W19 = 318, + Mips_W20 = 319, + Mips_W21 = 320, + Mips_W22 = 321, + Mips_W23 = 322, + Mips_W24 = 323, + Mips_W25 = 324, + Mips_W26 = 325, + Mips_W27 = 326, + Mips_W28 = 327, + Mips_W29 = 328, + Mips_W30 = 329, + Mips_W31 = 330, + Mips_ZERO_64 = 331, + Mips_A0_64 = 332, + Mips_A1_64 = 333, + Mips_A2_64 = 334, + Mips_A3_64 = 335, + Mips_AC0_64 = 336, + Mips_D0_64 = 337, + Mips_D1_64 = 338, + Mips_D2_64 = 339, + Mips_D3_64 = 340, + Mips_D4_64 = 341, + Mips_D5_64 = 342, + Mips_D6_64 = 343, + Mips_D7_64 = 344, + Mips_D8_64 = 345, + Mips_D9_64 = 346, + Mips_D10_64 = 347, + Mips_D11_64 = 348, + Mips_D12_64 = 349, + Mips_D13_64 = 350, + Mips_D14_64 = 351, + Mips_D15_64 = 352, + Mips_D16_64 = 353, + Mips_D17_64 = 354, + Mips_D18_64 = 355, + Mips_D19_64 = 356, + Mips_D20_64 = 357, + Mips_D21_64 = 358, + Mips_D22_64 = 359, + Mips_D23_64 = 360, + Mips_D24_64 = 361, + Mips_D25_64 = 362, + Mips_D26_64 = 363, + Mips_D27_64 = 364, + Mips_D28_64 = 365, + Mips_D29_64 = 366, + Mips_D30_64 = 367, + Mips_D31_64 = 368, + Mips_DSPOutFlag16_19 = 369, + Mips_HI0_64 = 370, + Mips_K0_64 = 371, + Mips_K1_64 = 372, + Mips_LO0_64 = 373, + Mips_S0_64 = 374, + Mips_S1_64 = 375, + Mips_S2_64 = 376, + Mips_S3_64 = 377, + Mips_S4_64 = 378, + Mips_S5_64 = 379, + Mips_S6_64 = 380, + Mips_S7_64 = 381, + Mips_T0_64 = 382, + Mips_T1_64 = 383, + Mips_T2_64 = 384, + Mips_T3_64 = 385, + Mips_T4_64 = 386, + Mips_T5_64 = 387, + Mips_T6_64 = 388, + Mips_T7_64 = 389, + Mips_T8_64 = 390, + Mips_T9_64 = 391, + Mips_V0_64 = 392, + Mips_V1_64 = 393, + Mips_NUM_TARGET_REGS // 394 +}; + +// Register classes +enum { + Mips_OddSPRegClassID = 0, + Mips_CCRRegClassID = 1, + Mips_COP2RegClassID = 2, + Mips_COP3RegClassID = 3, + Mips_DSPRRegClassID = 4, + Mips_FGR32RegClassID = 5, + Mips_FGRCCRegClassID = 6, + Mips_FGRH32RegClassID = 7, + Mips_GPR32RegClassID = 8, + Mips_HWRegsRegClassID = 9, + Mips_OddSP_with_sub_hiRegClassID = 10, + Mips_FGR32_and_OddSPRegClassID = 11, + Mips_FGRH32_and_OddSPRegClassID = 12, + Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, + Mips_CPU16RegsPlusSPRegClassID = 14, + Mips_CCRegClassID = 15, + Mips_CPU16RegsRegClassID = 16, + Mips_FCCRegClassID = 17, + Mips_GPRMM16RegClassID = 18, + Mips_GPRMM16MovePRegClassID = 19, + Mips_GPRMM16ZeroRegClassID = 20, + Mips_MSACtrlRegClassID = 21, + Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, + Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, + Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, + Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, + Mips_HI32DSPRegClassID = 26, + Mips_LO32DSPRegClassID = 27, + Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, + Mips_CPURARegRegClassID = 29, + Mips_CPUSPRegRegClassID = 30, + Mips_DSPCCRegClassID = 31, + Mips_HI32RegClassID = 32, + Mips_LO32RegClassID = 33, + Mips_FGR64RegClassID = 34, + Mips_GPR64RegClassID = 35, + Mips_AFGR64RegClassID = 36, + Mips_FGR64_and_OddSPRegClassID = 37, + Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, + Mips_AFGR64_and_OddSPRegClassID = 39, + Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, + Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, + Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, + Mips_ACC64DSPRegClassID = 44, + Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, + Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, + Mips_OCTEON_MPLRegClassID = 48, + Mips_OCTEON_PRegClassID = 49, + Mips_ACC64RegClassID = 50, + Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, + Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, + Mips_HI64RegClassID = 53, + Mips_LO64RegClassID = 54, + Mips_MSA128BRegClassID = 55, + Mips_MSA128DRegClassID = 56, + Mips_MSA128HRegClassID = 57, + Mips_MSA128WRegClassID = 58, + Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, + Mips_MSA128WEvensRegClassID = 60, + Mips_ACC128RegClassID = 61, +}; + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static MCPhysReg MipsRegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 4, 1, 1, 1, 1, 0, + /* 8 */ 364, 65286, 1, 1, 1, 0, + /* 14 */ 20, 1, 0, + /* 17 */ 21, 1, 0, + /* 20 */ 22, 1, 0, + /* 23 */ 23, 1, 0, + /* 26 */ 24, 1, 0, + /* 29 */ 25, 1, 0, + /* 32 */ 26, 1, 0, + /* 35 */ 27, 1, 0, + /* 38 */ 28, 1, 0, + /* 41 */ 29, 1, 0, + /* 44 */ 30, 1, 0, + /* 47 */ 31, 1, 0, + /* 50 */ 32, 1, 0, + /* 53 */ 33, 1, 0, + /* 56 */ 34, 1, 0, + /* 59 */ 35, 1, 0, + /* 62 */ 65439, 1, 0, + /* 65 */ 65513, 1, 0, + /* 68 */ 3, 0, + /* 70 */ 4, 0, + /* 72 */ 6, 0, + /* 74 */ 11, 0, + /* 76 */ 12, 0, + /* 78 */ 22, 0, + /* 80 */ 23, 0, + /* 82 */ 29, 0, + /* 84 */ 30, 0, + /* 86 */ 65308, 72, 0, + /* 89 */ 65346, 72, 0, + /* 92 */ 38, 65322, 73, 0, + /* 96 */ 95, 0, + /* 98 */ 96, 0, + /* 100 */ 106, 0, + /* 102 */ 187, 0, + /* 104 */ 219, 0, + /* 106 */ 258, 0, + /* 108 */ 266, 0, + /* 110 */ 310, 0, + /* 112 */ 65031, 0, + /* 114 */ 65108, 0, + /* 116 */ 65172, 0, + /* 118 */ 65226, 0, + /* 120 */ 65229, 0, + /* 122 */ 65270, 0, + /* 124 */ 65278, 0, + /* 126 */ 65295, 0, + /* 128 */ 65317, 0, + /* 130 */ 37, 65430, 103, 65395, 65333, 0, + /* 136 */ 65349, 0, + /* 138 */ 65395, 0, + /* 140 */ 65410, 0, + /* 142 */ 65415, 0, + /* 144 */ 65419, 0, + /* 146 */ 65420, 0, + /* 148 */ 65421, 0, + /* 150 */ 65422, 0, + /* 152 */ 65430, 0, + /* 154 */ 65440, 0, + /* 156 */ 65441, 0, + /* 158 */ 141, 65498, 0, + /* 161 */ 65516, 234, 65498, 0, + /* 165 */ 65515, 235, 65498, 0, + /* 169 */ 65514, 236, 65498, 0, + /* 173 */ 65513, 237, 65498, 0, + /* 177 */ 65512, 238, 65498, 0, + /* 181 */ 65511, 239, 65498, 0, + /* 185 */ 65510, 240, 65498, 0, + /* 189 */ 65509, 241, 65498, 0, + /* 193 */ 65508, 242, 65498, 0, + /* 197 */ 65507, 243, 65498, 0, + /* 201 */ 65506, 244, 65498, 0, + /* 205 */ 65505, 245, 65498, 0, + /* 209 */ 65504, 246, 65498, 0, + /* 213 */ 65503, 247, 65498, 0, + /* 217 */ 65502, 248, 65498, 0, + /* 221 */ 65501, 249, 65498, 0, + /* 225 */ 65500, 250, 65498, 0, + /* 229 */ 65295, 347, 65499, 0, + /* 233 */ 65333, 344, 65502, 0, + /* 237 */ 65507, 0, + /* 239 */ 65510, 0, + /* 241 */ 65511, 0, + /* 243 */ 65512, 0, + /* 245 */ 65516, 0, + /* 247 */ 65521, 0, + /* 249 */ 65522, 0, + /* 251 */ 65535, 0, +}; + +static uint16_t MipsSubRegIdxLists[] = { + /* 0 */ 1, 0, + /* 2 */ 3, 4, 5, 6, 7, 0, + /* 8 */ 2, 9, 8, 0, + /* 12 */ 9, 1, 8, 10, 11, 0, +}; + +static MCRegisterDesc MipsRegDesc[] = { // Descriptors + { 6, 0, 0, 0, 0, 0 }, + { 2007, 1, 82, 1, 4017, 0 }, + { 2010, 1, 1, 1, 4017, 0 }, + { 2102, 1, 1, 1, 4017, 0 }, + { 1973, 1, 1, 1, 4017, 0 }, + { 2027, 8, 1, 2, 32, 4 }, + { 2054, 1, 1, 1, 1089, 0 }, + { 2071, 1, 1, 1, 1089, 0 }, + { 1985, 1, 102, 1, 1089, 0 }, + { 1988, 1, 104, 1, 1089, 0 }, + { 2061, 1, 1, 1, 1089, 0 }, + { 2000, 1, 1, 1, 1089, 0 }, + { 1994, 1, 1, 1, 1089, 0 }, + { 2038, 1, 1, 1, 1089, 0 }, + { 2092, 1, 1, 1, 1089, 0 }, + { 2081, 1, 1, 1, 1089, 0 }, + { 2019, 1, 1, 1, 1089, 0 }, + { 2045, 1, 1, 1, 1089, 0 }, + { 1970, 1, 1, 1, 1089, 0 }, + { 1967, 1, 106, 1, 1089, 0 }, + { 1991, 1, 108, 1, 1089, 0 }, + { 1980, 1, 110, 1, 1089, 0 }, + { 152, 1, 110, 1, 1089, 0 }, + { 365, 1, 110, 1, 1089, 0 }, + { 537, 1, 110, 1, 1089, 0 }, + { 703, 1, 110, 1, 1089, 0 }, + { 155, 190, 110, 9, 1042, 10 }, + { 368, 190, 1, 9, 1042, 10 }, + { 540, 190, 1, 9, 1042, 10 }, + { 706, 190, 1, 9, 1042, 10 }, + { 1271, 237, 1, 0, 0, 2 }, + { 160, 1, 1, 1, 1153, 0 }, + { 373, 1, 1, 1, 1153, 0 }, + { 545, 1, 1, 1, 1153, 0 }, + { 711, 1, 1, 1, 1153, 0 }, + { 1278, 1, 1, 1, 1153, 0 }, + { 1412, 1, 1, 1, 1153, 0 }, + { 1542, 1, 1, 1, 1153, 0 }, + { 1672, 1, 1, 1, 1153, 0 }, + { 70, 1, 1, 1, 1153, 0 }, + { 283, 1, 1, 1, 1153, 0 }, + { 496, 1, 1, 1, 1153, 0 }, + { 662, 1, 1, 1, 1153, 0 }, + { 820, 1, 1, 1, 1153, 0 }, + { 1383, 1, 1, 1, 1153, 0 }, + { 1513, 1, 1, 1, 1153, 0 }, + { 1643, 1, 1, 1, 1153, 0 }, + { 1773, 1, 1, 1, 1153, 0 }, + { 1911, 1, 1, 1, 1153, 0 }, + { 130, 1, 1, 1, 1153, 0 }, + { 343, 1, 1, 1, 1153, 0 }, + { 531, 1, 1, 1, 1153, 0 }, + { 697, 1, 1, 1, 1153, 0 }, + { 842, 1, 1, 1, 1153, 0 }, + { 1405, 1, 1, 1, 1153, 0 }, + { 1535, 1, 1, 1, 1153, 0 }, + { 1665, 1, 1, 1, 1153, 0 }, + { 1795, 1, 1, 1, 1153, 0 }, + { 1933, 1, 1, 1, 1153, 0 }, + { 0, 1, 1, 1, 1153, 0 }, + { 213, 1, 1, 1, 1153, 0 }, + { 426, 1, 1, 1, 1153, 0 }, + { 592, 1, 1, 1, 1153, 0 }, + { 750, 1, 1, 1, 1153, 0 }, + { 1313, 1, 1, 1, 1153, 0 }, + { 1447, 1, 1, 1, 1153, 0 }, + { 1577, 1, 1, 1, 1153, 0 }, + { 1707, 1, 1, 1, 1153, 0 }, + { 1829, 1, 1, 1, 1153, 0 }, + { 45, 1, 1, 1, 1153, 0 }, + { 258, 1, 1, 1, 1153, 0 }, + { 471, 1, 1, 1, 1153, 0 }, + { 637, 1, 1, 1, 1153, 0 }, + { 795, 1, 1, 1, 1153, 0 }, + { 1358, 1, 1, 1, 1153, 0 }, + { 1488, 1, 1, 1, 1153, 0 }, + { 1618, 1, 1, 1, 1153, 0 }, + { 1748, 1, 1, 1, 1153, 0 }, + { 1886, 1, 1, 1, 1153, 0 }, + { 105, 1, 1, 1, 1153, 0 }, + { 318, 1, 1, 1, 1153, 0 }, + { 7, 1, 1, 1, 1153, 0 }, + { 220, 1, 1, 1, 1153, 0 }, + { 433, 1, 1, 1, 1153, 0 }, + { 599, 1, 1, 1, 1153, 0 }, + { 757, 1, 1, 1, 1153, 0 }, + { 1320, 1, 1, 1, 1153, 0 }, + { 1454, 1, 1, 1, 1153, 0 }, + { 1584, 1, 1, 1, 1153, 0 }, + { 1714, 1, 1, 1, 1153, 0 }, + { 1836, 1, 1, 1, 1153, 0 }, + { 52, 1, 1, 1, 1153, 0 }, + { 265, 1, 1, 1, 1153, 0 }, + { 478, 1, 1, 1, 1153, 0 }, + { 644, 1, 1, 1, 1153, 0 }, + { 802, 1, 1, 1, 1153, 0 }, + { 1365, 1, 1, 1, 1153, 0 }, + { 1495, 1, 1, 1, 1153, 0 }, + { 1625, 1, 1, 1, 1153, 0 }, + { 1755, 1, 1, 1, 1153, 0 }, + { 1893, 1, 1, 1, 1153, 0 }, + { 112, 1, 1, 1, 1153, 0 }, + { 325, 1, 1, 1, 1153, 0 }, + { 164, 14, 1, 9, 994, 10 }, + { 377, 17, 1, 9, 994, 10 }, + { 549, 20, 1, 9, 994, 10 }, + { 715, 23, 1, 9, 994, 10 }, + { 1282, 26, 1, 9, 994, 10 }, + { 1416, 29, 1, 9, 994, 10 }, + { 1546, 32, 1, 9, 994, 10 }, + { 1676, 35, 1, 9, 994, 10 }, + { 1801, 38, 1, 9, 994, 10 }, + { 1939, 41, 1, 9, 994, 10 }, + { 14, 44, 1, 9, 994, 10 }, + { 227, 47, 1, 9, 994, 10 }, + { 440, 50, 1, 9, 994, 10 }, + { 606, 53, 1, 9, 994, 10 }, + { 764, 56, 1, 9, 994, 10 }, + { 1327, 59, 1, 9, 994, 10 }, + { 92, 1, 150, 1, 2401, 0 }, + { 305, 1, 148, 1, 2401, 0 }, + { 518, 1, 146, 1, 2401, 0 }, + { 684, 1, 144, 1, 2401, 0 }, + { 167, 1, 161, 1, 3985, 0 }, + { 380, 1, 165, 1, 3985, 0 }, + { 552, 1, 165, 1, 3985, 0 }, + { 718, 1, 169, 1, 3985, 0 }, + { 1285, 1, 169, 1, 3985, 0 }, + { 1419, 1, 173, 1, 3985, 0 }, + { 1549, 1, 173, 1, 3985, 0 }, + { 1679, 1, 177, 1, 3985, 0 }, + { 1804, 1, 177, 1, 3985, 0 }, + { 1942, 1, 181, 1, 3985, 0 }, + { 18, 1, 181, 1, 3985, 0 }, + { 231, 1, 185, 1, 3985, 0 }, + { 444, 1, 185, 1, 3985, 0 }, + { 610, 1, 189, 1, 3985, 0 }, + { 768, 1, 189, 1, 3985, 0 }, + { 1331, 1, 193, 1, 3985, 0 }, + { 1461, 1, 193, 1, 3985, 0 }, + { 1591, 1, 197, 1, 3985, 0 }, + { 1721, 1, 197, 1, 3985, 0 }, + { 1843, 1, 201, 1, 3985, 0 }, + { 59, 1, 201, 1, 3985, 0 }, + { 272, 1, 205, 1, 3985, 0 }, + { 485, 1, 205, 1, 3985, 0 }, + { 651, 1, 209, 1, 3985, 0 }, + { 809, 1, 209, 1, 3985, 0 }, + { 1372, 1, 213, 1, 3985, 0 }, + { 1502, 1, 213, 1, 3985, 0 }, + { 1632, 1, 217, 1, 3985, 0 }, + { 1762, 1, 217, 1, 3985, 0 }, + { 1900, 1, 221, 1, 3985, 0 }, + { 119, 1, 221, 1, 3985, 0 }, + { 332, 1, 225, 1, 3985, 0 }, + { 159, 1, 1, 1, 3985, 0 }, + { 372, 1, 1, 1, 3985, 0 }, + { 544, 1, 1, 1, 3985, 0 }, + { 710, 1, 1, 1, 3985, 0 }, + { 1277, 1, 1, 1, 3985, 0 }, + { 1411, 1, 1, 1, 3985, 0 }, + { 1541, 1, 1, 1, 3985, 0 }, + { 1671, 1, 1, 1, 3985, 0 }, + { 191, 1, 1, 1, 3985, 0 }, + { 404, 1, 1, 1, 3985, 0 }, + { 573, 1, 1, 1, 3985, 0 }, + { 731, 1, 1, 1, 3985, 0 }, + { 1294, 1, 1, 1, 3985, 0 }, + { 1428, 1, 1, 1, 3985, 0 }, + { 1558, 1, 1, 1, 3985, 0 }, + { 1688, 1, 1, 1, 3985, 0 }, + { 1813, 1, 1, 1, 3985, 0 }, + { 1951, 1, 1, 1, 3985, 0 }, + { 29, 1, 1, 1, 3985, 0 }, + { 242, 1, 1, 1, 3985, 0 }, + { 455, 1, 1, 1, 3985, 0 }, + { 621, 1, 1, 1, 3985, 0 }, + { 779, 1, 1, 1, 3985, 0 }, + { 1342, 1, 1, 1, 3985, 0 }, + { 1472, 1, 1, 1, 3985, 0 }, + { 1602, 1, 1, 1, 3985, 0 }, + { 1732, 1, 1, 1, 3985, 0 }, + { 1854, 1, 1, 1, 3985, 0 }, + { 76, 1, 1, 1, 3985, 0 }, + { 289, 1, 1, 1, 3985, 0 }, + { 502, 1, 1, 1, 3985, 0 }, + { 668, 1, 1, 1, 3985, 0 }, + { 826, 1, 1, 1, 3985, 0 }, + { 1389, 1, 1, 1, 3985, 0 }, + { 1519, 1, 1, 1, 3985, 0 }, + { 1649, 1, 1, 1, 3985, 0 }, + { 1779, 1, 1, 1, 3985, 0 }, + { 1917, 1, 1, 1, 3985, 0 }, + { 136, 1, 1, 1, 3985, 0 }, + { 349, 1, 1, 1, 3985, 0 }, + { 1253, 136, 1, 0, 1184, 2 }, + { 170, 1, 158, 1, 3953, 0 }, + { 383, 1, 158, 1, 3953, 0 }, + { 555, 1, 158, 1, 3953, 0 }, + { 721, 1, 158, 1, 3953, 0 }, + { 1288, 1, 158, 1, 3953, 0 }, + { 1422, 1, 158, 1, 3953, 0 }, + { 1552, 1, 158, 1, 3953, 0 }, + { 1682, 1, 158, 1, 3953, 0 }, + { 1807, 1, 158, 1, 3953, 0 }, + { 1945, 1, 158, 1, 3953, 0 }, + { 22, 1, 158, 1, 3953, 0 }, + { 235, 1, 158, 1, 3953, 0 }, + { 448, 1, 158, 1, 3953, 0 }, + { 614, 1, 158, 1, 3953, 0 }, + { 772, 1, 158, 1, 3953, 0 }, + { 1335, 1, 158, 1, 3953, 0 }, + { 1465, 1, 158, 1, 3953, 0 }, + { 1595, 1, 158, 1, 3953, 0 }, + { 1725, 1, 158, 1, 3953, 0 }, + { 1847, 1, 158, 1, 3953, 0 }, + { 63, 1, 158, 1, 3953, 0 }, + { 276, 1, 158, 1, 3953, 0 }, + { 489, 1, 158, 1, 3953, 0 }, + { 655, 1, 158, 1, 3953, 0 }, + { 813, 1, 158, 1, 3953, 0 }, + { 1376, 1, 158, 1, 3953, 0 }, + { 1506, 1, 158, 1, 3953, 0 }, + { 1636, 1, 158, 1, 3953, 0 }, + { 1766, 1, 158, 1, 3953, 0 }, + { 1904, 1, 158, 1, 3953, 0 }, + { 123, 1, 158, 1, 3953, 0 }, + { 336, 1, 158, 1, 3953, 0 }, + { 1259, 128, 1, 0, 1216, 2 }, + { 172, 1, 233, 1, 1826, 0 }, + { 385, 1, 134, 1, 1826, 0 }, + { 557, 1, 134, 1, 1826, 0 }, + { 723, 1, 134, 1, 1826, 0 }, + { 196, 1, 1, 1, 3921, 0 }, + { 409, 1, 1, 1, 3921, 0 }, + { 578, 1, 1, 1, 3921, 0 }, + { 736, 1, 1, 1, 3921, 0 }, + { 1299, 1, 1, 1, 3921, 0 }, + { 1433, 1, 1, 1, 3921, 0 }, + { 1563, 1, 1, 1, 3921, 0 }, + { 1693, 1, 1, 1, 3921, 0 }, + { 1818, 1, 1, 1, 3921, 0 }, + { 1956, 1, 1, 1, 3921, 0 }, + { 35, 1, 1, 1, 3921, 0 }, + { 248, 1, 1, 1, 3921, 0 }, + { 461, 1, 1, 1, 3921, 0 }, + { 627, 1, 1, 1, 3921, 0 }, + { 785, 1, 1, 1, 3921, 0 }, + { 1348, 1, 1, 1, 3921, 0 }, + { 1478, 1, 1, 1, 3921, 0 }, + { 1608, 1, 1, 1, 3921, 0 }, + { 1738, 1, 1, 1, 3921, 0 }, + { 1860, 1, 1, 1, 3921, 0 }, + { 82, 1, 1, 1, 3921, 0 }, + { 295, 1, 1, 1, 3921, 0 }, + { 508, 1, 1, 1, 3921, 0 }, + { 674, 1, 1, 1, 3921, 0 }, + { 832, 1, 1, 1, 3921, 0 }, + { 1395, 1, 1, 1, 3921, 0 }, + { 1525, 1, 1, 1, 3921, 0 }, + { 1655, 1, 1, 1, 3921, 0 }, + { 1785, 1, 1, 1, 3921, 0 }, + { 1923, 1, 1, 1, 3921, 0 }, + { 142, 1, 1, 1, 3921, 0 }, + { 355, 1, 1, 1, 3921, 0 }, + { 176, 1, 100, 1, 3921, 0 }, + { 389, 1, 100, 1, 3921, 0 }, + { 184, 1, 229, 1, 1794, 0 }, + { 397, 1, 126, 1, 1794, 0 }, + { 566, 1, 126, 1, 1794, 0 }, + { 727, 1, 126, 1, 1794, 0 }, + { 179, 1, 1, 1, 3889, 0 }, + { 392, 1, 1, 1, 3889, 0 }, + { 561, 1, 1, 1, 3889, 0 }, + { 188, 1, 1, 1, 3889, 0 }, + { 401, 1, 1, 1, 3889, 0 }, + { 570, 1, 1, 1, 3889, 0 }, + { 1239, 124, 1, 0, 1248, 2 }, + { 201, 1, 98, 1, 3857, 0 }, + { 414, 1, 98, 1, 3857, 0 }, + { 583, 1, 98, 1, 3857, 0 }, + { 741, 1, 98, 1, 3857, 0 }, + { 1304, 1, 98, 1, 3857, 0 }, + { 1438, 1, 98, 1, 3857, 0 }, + { 1568, 1, 98, 1, 3857, 0 }, + { 1698, 1, 98, 1, 3857, 0 }, + { 1265, 122, 1, 0, 1280, 2 }, + { 204, 1, 96, 1, 3825, 0 }, + { 417, 1, 96, 1, 3825, 0 }, + { 586, 1, 96, 1, 3825, 0 }, + { 744, 1, 96, 1, 3825, 0 }, + { 1307, 1, 96, 1, 3825, 0 }, + { 1441, 1, 96, 1, 3825, 0 }, + { 1571, 1, 96, 1, 3825, 0 }, + { 1701, 1, 96, 1, 3825, 0 }, + { 1823, 1, 96, 1, 3825, 0 }, + { 1961, 1, 96, 1, 3825, 0 }, + { 207, 1, 96, 1, 3825, 0 }, + { 420, 1, 96, 1, 3825, 0 }, + { 210, 92, 1, 8, 1425, 10 }, + { 423, 92, 1, 8, 1425, 10 }, + { 589, 92, 1, 8, 1425, 10 }, + { 747, 92, 1, 8, 1425, 10 }, + { 1310, 92, 1, 8, 1425, 10 }, + { 1444, 92, 1, 8, 1425, 10 }, + { 1574, 92, 1, 8, 1425, 10 }, + { 1704, 92, 1, 8, 1425, 10 }, + { 1826, 92, 1, 8, 1425, 10 }, + { 1964, 92, 1, 8, 1425, 10 }, + { 41, 92, 1, 8, 1425, 10 }, + { 254, 92, 1, 8, 1425, 10 }, + { 467, 92, 1, 8, 1425, 10 }, + { 633, 92, 1, 8, 1425, 10 }, + { 791, 92, 1, 8, 1425, 10 }, + { 1354, 92, 1, 8, 1425, 10 }, + { 1484, 92, 1, 8, 1425, 10 }, + { 1614, 92, 1, 8, 1425, 10 }, + { 1744, 92, 1, 8, 1425, 10 }, + { 1866, 92, 1, 8, 1425, 10 }, + { 88, 92, 1, 8, 1425, 10 }, + { 301, 92, 1, 8, 1425, 10 }, + { 514, 92, 1, 8, 1425, 10 }, + { 680, 92, 1, 8, 1425, 10 }, + { 838, 92, 1, 8, 1425, 10 }, + { 1401, 92, 1, 8, 1425, 10 }, + { 1531, 92, 1, 8, 1425, 10 }, + { 1661, 92, 1, 8, 1425, 10 }, + { 1791, 92, 1, 8, 1425, 10 }, + { 1929, 92, 1, 8, 1425, 10 }, + { 148, 92, 1, 8, 1425, 10 }, + { 361, 92, 1, 8, 1425, 10 }, + { 1245, 118, 1, 0, 1921, 2 }, + { 869, 118, 1, 0, 1921, 2 }, + { 947, 118, 1, 0, 1921, 2 }, + { 997, 118, 1, 0, 1921, 2 }, + { 1035, 118, 1, 0, 1921, 2 }, + { 875, 130, 1, 12, 656, 10 }, + { 882, 93, 159, 9, 1377, 10 }, + { 953, 93, 159, 9, 1377, 10 }, + { 1003, 93, 159, 9, 1377, 10 }, + { 1041, 93, 159, 9, 1377, 10 }, + { 1073, 93, 159, 9, 1377, 10 }, + { 1105, 93, 159, 9, 1377, 10 }, + { 1137, 93, 159, 9, 1377, 10 }, + { 1169, 93, 159, 9, 1377, 10 }, + { 1201, 93, 159, 9, 1377, 10 }, + { 1227, 93, 159, 9, 1377, 10 }, + { 848, 93, 159, 9, 1377, 10 }, + { 926, 93, 159, 9, 1377, 10 }, + { 983, 93, 159, 9, 1377, 10 }, + { 1021, 93, 159, 9, 1377, 10 }, + { 1059, 93, 159, 9, 1377, 10 }, + { 1091, 93, 159, 9, 1377, 10 }, + { 1123, 93, 159, 9, 1377, 10 }, + { 1155, 93, 159, 9, 1377, 10 }, + { 1187, 93, 159, 9, 1377, 10 }, + { 1213, 93, 159, 9, 1377, 10 }, + { 855, 93, 159, 9, 1377, 10 }, + { 933, 93, 159, 9, 1377, 10 }, + { 990, 93, 159, 9, 1377, 10 }, + { 1028, 93, 159, 9, 1377, 10 }, + { 1066, 93, 159, 9, 1377, 10 }, + { 1098, 93, 159, 9, 1377, 10 }, + { 1130, 93, 159, 9, 1377, 10 }, + { 1162, 93, 159, 9, 1377, 10 }, + { 1194, 93, 159, 9, 1377, 10 }, + { 1220, 93, 159, 9, 1377, 10 }, + { 862, 93, 159, 9, 1377, 10 }, + { 940, 93, 159, 9, 1377, 10 }, + { 1870, 1, 116, 1, 1120, 0 }, + { 888, 138, 235, 0, 1344, 2 }, + { 895, 152, 1, 0, 2241, 2 }, + { 959, 152, 1, 0, 2241, 2 }, + { 901, 152, 231, 0, 1312, 2 }, + { 908, 154, 1, 0, 2273, 2 }, + { 965, 154, 1, 0, 2273, 2 }, + { 1009, 154, 1, 0, 2273, 2 }, + { 1047, 154, 1, 0, 2273, 2 }, + { 1079, 154, 1, 0, 2273, 2 }, + { 1111, 154, 1, 0, 2273, 2 }, + { 1143, 154, 1, 0, 2273, 2 }, + { 1175, 154, 1, 0, 2273, 2 }, + { 914, 156, 1, 0, 2273, 2 }, + { 971, 156, 1, 0, 2273, 2 }, + { 1015, 156, 1, 0, 2273, 2 }, + { 1053, 156, 1, 0, 2273, 2 }, + { 1085, 156, 1, 0, 2273, 2 }, + { 1117, 156, 1, 0, 2273, 2 }, + { 1149, 156, 1, 0, 2273, 2 }, + { 1181, 156, 1, 0, 2273, 2 }, + { 1207, 156, 1, 0, 2273, 2 }, + { 1233, 156, 1, 0, 2273, 2 }, + { 920, 156, 1, 0, 2273, 2 }, + { 977, 156, 1, 0, 2273, 2 }, +}; + + // OddSP Register Class... + static MCPhysReg OddSP[] = { + Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + }; + + // OddSP Bit set. + static uint8_t OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + }; + + // CCR Register Class... + static MCPhysReg CCR[] = { + Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, + }; + + // CCR Bit set. + static uint8_t CCRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // COP2 Register Class... + static MCPhysReg COP2[] = { + Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, + }; + + // COP2 Bit set. + static uint8_t COP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, + }; + + // COP3 Register Class... + static MCPhysReg COP3[] = { + Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, + }; + + // COP3 Bit set. + static uint8_t COP3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, + }; + + // DSPR Register Class... + static MCPhysReg DSPR[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + }; + + // DSPR Bit set. + static uint8_t DSPRBits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + }; + + // FGR32 Register Class... + static MCPhysReg FGR32[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + }; + + // FGR32 Bit set. + static uint8_t FGR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // FGRCC Register Class... + static MCPhysReg FGRCC[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, + }; + + // FGRCC Bit set. + static uint8_t FGRCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // FGRH32 Register Class... + static MCPhysReg FGRH32[] = { + Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, + }; + + // FGRH32 Bit set. + static uint8_t FGRH32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + }; + + // GPR32 Register Class... + static MCPhysReg GPR32[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, + }; + + // GPR32 Bit set. + static uint8_t GPR32Bits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, + }; + + // HWRegs Register Class... + static MCPhysReg HWRegs[] = { + Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, + }; + + // HWRegs Bit set. + static uint8_t HWRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // OddSP_with_sub_hi Register Class... + static MCPhysReg OddSP_with_sub_hi[] = { + Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + }; + + // OddSP_with_sub_hi Bit set. + static uint8_t OddSP_with_sub_hiBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + }; + + // FGR32_and_OddSP Register Class... + static MCPhysReg FGR32_and_OddSP[] = { + Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, + }; + + // FGR32_and_OddSP Bit set. + static uint8_t FGR32_and_OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, + }; + + // FGRH32_and_OddSP Register Class... + static MCPhysReg FGRH32_and_OddSP[] = { + Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, + }; + + // FGRH32_and_OddSP Bit set. + static uint8_t FGRH32_and_OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, + }; + + // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... + static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { + Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + }; + + // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. + static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + }; + + // CPU16RegsPlusSP Register Class... + static MCPhysReg CPU16RegsPlusSP[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, + }; + + // CPU16RegsPlusSP Bit set. + static uint8_t CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + }; + + // CC Register Class... + static MCPhysReg CC[] = { + Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, + }; + + // CC Bit set. + static uint8_t CCBits[] = { + 0x00, 0x00, 0x00, 0x80, 0x7f, + }; + + // CPU16Regs Register Class... + static MCPhysReg CPU16Regs[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, + }; + + // CPU16Regs Bit set. + static uint8_t CPU16RegsBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + }; + + // FCC Register Class... + static MCPhysReg FCC[] = { + Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, + }; + + // FCC Bit set. + static uint8_t FCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, + }; + + // GPRMM16 Register Class... + static MCPhysReg GPRMM16[] = { + Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + }; + + // GPRMM16 Bit set. + static uint8_t GPRMM16Bits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + }; + + // GPRMM16MoveP Register Class... + static MCPhysReg GPRMM16MoveP[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, + }; + + // GPRMM16MoveP Bit set. + static uint8_t GPRMM16MovePBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, + }; + + // GPRMM16Zero Register Class... + static MCPhysReg GPRMM16Zero[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + }; + + // GPRMM16Zero Bit set. + static uint8_t GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + }; + + // MSACtrl Register Class... + static MCPhysReg MSACtrl[] = { + Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, + }; + + // MSACtrl Bit set. + static uint8_t MSACtrlBits[] = { + 0x00, 0xfc, 0x03, + }; + + // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... + static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { + Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, + }; + + // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. + static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + }; + + // CPU16Regs_and_GPRMM16Zero Register Class... + static MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + }; + + // CPU16Regs_and_GPRMM16Zero Bit set. + static uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + }; + + // CPU16Regs_and_GPRMM16MoveP Register Class... + static MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_S0, + }; + + // CPU16Regs_and_GPRMM16MoveP Bit set. + static uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, + }; + + // GPRMM16MoveP_and_GPRMM16Zero Register Class... + static MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, + }; + + // GPRMM16MoveP_and_GPRMM16Zero Bit set. + static uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + }; + + // HI32DSP Register Class... + static MCPhysReg HI32DSP[] = { + Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, + }; + + // HI32DSP Bit set. + static uint8_t HI32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + }; + + // LO32DSP Register Class... + static MCPhysReg LO32DSP[] = { + Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, + }; + + // LO32DSP Bit set. + static uint8_t LO32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + }; + + // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... + static MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, Mips_V0, Mips_V1, + }; + + // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. + static uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, + }; + + // CPURAReg Register Class... + static MCPhysReg CPURAReg[] = { + Mips_RA, + }; + + // CPURAReg Bit set. + static uint8_t CPURARegBits[] = { + 0x00, 0x00, 0x08, + }; + + // CPUSPReg Register Class... + static MCPhysReg CPUSPReg[] = { + Mips_SP, + }; + + // CPUSPReg Bit set. + static uint8_t CPUSPRegBits[] = { + 0x00, 0x00, 0x10, + }; + + // DSPCC Register Class... + static MCPhysReg DSPCC[] = { + Mips_DSPCCond, + }; + + // DSPCC Bit set. + static uint8_t DSPCCBits[] = { + 0x04, + }; + + // HI32 Register Class... + static MCPhysReg HI32[] = { + Mips_HI0, + }; + + // HI32 Bit set. + static uint8_t HI32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + + // LO32 Register Class... + static MCPhysReg LO32[] = { + Mips_LO0, + }; + + // LO32 Bit set. + static uint8_t LO32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + }; + + // FGR64 Register Class... + static MCPhysReg FGR64[] = { + Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, + }; + + // FGR64 Bit set. + static uint8_t FGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + + // GPR64 Register Class... + static MCPhysReg GPR64[] = { + Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, + }; + + // GPR64 Bit set. + static uint8_t GPR64Bits[] = { + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, + }; + + // AFGR64 Register Class... + static MCPhysReg AFGR64[] = { + Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, + }; + + // AFGR64 Bit set. + static uint8_t AFGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // FGR64_and_OddSP Register Class... + static MCPhysReg FGR64_and_OddSP[] = { + Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, + }; + + // FGR64_and_OddSP Bit set. + static uint8_t FGR64_and_OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, + }; + + // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, + }; + + // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. + static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + }; + + // AFGR64_and_OddSP Register Class... + static MCPhysReg AFGR64_and_OddSP[] = { + Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, + }; + + // AFGR64_and_OddSP Bit set. + static uint8_t AFGR64_and_OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + }; + + // GPR64_with_sub_32_in_CPU16Regs Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_CPU16Regs Bit set. + static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... + static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. + static uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16Zero Register Class... + static MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_GPRMM16Zero Bit set. + static uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. + static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // ACC64DSP Register Class... + static MCPhysReg ACC64DSP[] = { + Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, + }; + + // ACC64DSP Bit set. + static uint8_t ACC64DSPBits[] = { + 0x00, 0x00, 0x00, 0x3c, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. + static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... + static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. + static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... + static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, Mips_V1_64, Mips_S1_64, + }; + + // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. + static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, + }; + + // OCTEON_MPL Register Class... + static MCPhysReg OCTEON_MPL[] = { + Mips_MPL0, Mips_MPL1, Mips_MPL2, + }; + + // OCTEON_MPL Bit set. + static uint8_t OCTEON_MPLBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, + }; + + // OCTEON_P Register Class... + static MCPhysReg OCTEON_P[] = { + Mips_P0, Mips_P1, Mips_P2, + }; + + // OCTEON_P Bit set. + static uint8_t OCTEON_PBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, + }; + + // ACC64 Register Class... + static MCPhysReg ACC64[] = { + Mips_AC0, + }; + + // ACC64 Bit set. + static uint8_t ACC64Bits[] = { + 0x00, 0x00, 0x00, 0x04, + }; + + // GPR64_with_sub_32_in_CPURAReg Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { + Mips_RA_64, + }; + + // GPR64_with_sub_32_in_CPURAReg Bit set. + static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + + // GPR64_with_sub_32_in_CPUSPReg Register Class... + static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { + Mips_SP_64, + }; + + // GPR64_with_sub_32_in_CPUSPReg Bit set. + static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + }; + + // HI64 Register Class... + static MCPhysReg HI64[] = { + Mips_HI0_64, + }; + + // HI64 Bit set. + static uint8_t HI64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + }; + + // LO64 Register Class... + static MCPhysReg LO64[] = { + Mips_LO0_64, + }; + + // LO64 Bit set. + static uint8_t LO64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + }; + + // MSA128B Register Class... + static MCPhysReg MSA128B[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + }; + + // MSA128B Bit set. + static uint8_t MSA128BBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // MSA128D Register Class... + static MCPhysReg MSA128D[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + }; + + // MSA128D Bit set. + static uint8_t MSA128DBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // MSA128H Register Class... + static MCPhysReg MSA128H[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + }; + + // MSA128H Bit set. + static uint8_t MSA128HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // MSA128W Register Class... + static MCPhysReg MSA128W[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, + }; + + // MSA128W Bit set. + static uint8_t MSA128WBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // MSA128B_with_sub_64_in_OddSP Register Class... + static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { + Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, + }; + + // MSA128B_with_sub_64_in_OddSP Bit set. + static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, + }; + + // MSA128WEvens Register Class... + static MCPhysReg MSA128WEvens[] = { + Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, + }; + + // MSA128WEvens Bit set. + static uint8_t MSA128WEvensBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, + }; + + // ACC128 Register Class... + static MCPhysReg ACC128[] = { + Mips_AC0_64, + }; + + // ACC128 Bit set. + static uint8_t ACC128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + }; + +static MCRegisterClass MipsMCRegisterClasses[] = { + { OddSP, OddSPBits, 236, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 }, + { CCR, CCRBits, 432, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 }, + { COP2, COP2Bits, 95, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 }, + { COP3, COP3Bits, 100, 32, sizeof(COP3Bits), Mips_COP3RegClassID, 4, 4, 1, 0 }, + { DSPR, DSPRBits, 436, 32, sizeof(DSPRBits), Mips_DSPRRegClassID, 4, 4, 1, 1 }, + { FGR32, FGR32Bits, 83, 32, sizeof(FGR32Bits), Mips_FGR32RegClassID, 4, 4, 1, 1 }, + { FGRCC, FGRCCBits, 167, 32, sizeof(FGRCCBits), Mips_FGRCCRegClassID, 4, 4, 1, 1 }, + { FGRH32, FGRH32Bits, 33, 32, sizeof(FGRH32Bits), Mips_FGRH32RegClassID, 4, 4, 1, 0 }, + { GPR32, GPR32Bits, 89, 32, sizeof(GPR32Bits), Mips_GPR32RegClassID, 4, 4, 1, 1 }, + { HWRegs, HWRegsBits, 760, 32, sizeof(HWRegsBits), Mips_HWRegsRegClassID, 4, 4, 1, 0 }, + { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 509, 24, sizeof(OddSP_with_sub_hiBits), Mips_OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 }, + { FGR32_and_OddSP, FGR32_and_OddSPBits, 242, 16, sizeof(FGR32_and_OddSPBits), Mips_FGR32_and_OddSPRegClassID, 4, 4, 1, 1 }, + { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 225, 16, sizeof(FGRH32_and_OddSPBits), Mips_FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 }, + { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 0, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 }, + { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 325, 9, sizeof(CPU16RegsPlusSPBits), Mips_CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 }, + { CC, CCBits, 158, 8, sizeof(CCBits), Mips_CCRegClassID, 4, 4, 1, 0 }, + { CPU16Regs, CPU16RegsBits, 750, 8, sizeof(CPU16RegsBits), Mips_CPU16RegsRegClassID, 4, 4, 1, 1 }, + { FCC, FCCBits, 157, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 }, + { GPRMM16, GPRMM16Bits, 134, 8, sizeof(GPRMM16Bits), Mips_GPRMM16RegClassID, 4, 4, 1, 1 }, + { GPRMM16MoveP, GPRMM16MovePBits, 385, 8, sizeof(GPRMM16MovePBits), Mips_GPRMM16MovePRegClassID, 4, 4, 1, 1 }, + { GPRMM16Zero, GPRMM16ZeroBits, 573, 8, sizeof(GPRMM16ZeroBits), Mips_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, + { MSACtrl, MSACtrlBits, 527, 8, sizeof(MSACtrlBits), Mips_MSACtrlRegClassID, 4, 4, 1, 1 }, + { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 50, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 }, + { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 623, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, + { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 371, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips_CPU16Regs_and_GPRMM16MovePRegClassID, 4, 4, 1, 1 }, + { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 556, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, + { HI32DSP, HI32DSPBits, 200, 4, sizeof(HI32DSPBits), Mips_HI32DSPRegClassID, 4, 4, 1, 1 }, + { LO32DSP, LO32DSPBits, 208, 4, sizeof(LO32DSPBits), Mips_LO32DSPRegClassID, 4, 4, 1, 1 }, + { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 606, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, + { CPURAReg, CPURARegBits, 470, 1, sizeof(CPURARegBits), Mips_CPURARegRegClassID, 4, 4, 1, 0 }, + { CPUSPReg, CPUSPRegBits, 500, 1, sizeof(CPUSPRegBits), Mips_CPUSPRegRegClassID, 4, 4, 1, 0 }, + { DSPCC, DSPCCBits, 161, 1, sizeof(DSPCCBits), Mips_DSPCCRegClassID, 4, 4, 1, 1 }, + { HI32, HI32Bits, 40, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 }, + { LO32, LO32Bits, 45, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 }, + { FGR64, FGR64Bits, 122, 32, sizeof(FGR64Bits), Mips_FGR64RegClassID, 8, 8, 1, 1 }, + { GPR64, GPR64Bits, 128, 32, sizeof(GPR64Bits), Mips_GPR64RegClassID, 8, 8, 1, 1 }, + { AFGR64, AFGR64Bits, 121, 16, sizeof(AFGR64Bits), Mips_AFGR64RegClassID, 8, 8, 1, 1 }, + { FGR64_and_OddSP, FGR64_and_OddSPBits, 259, 16, sizeof(FGR64_and_OddSPBits), Mips_FGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 304, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 }, + { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 258, 8, sizeof(AFGR64_and_OddSPBits), Mips_AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 729, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 398, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 696, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 649, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, + { ACC64DSP, ACC64DSPBits, 216, 4, sizeof(ACC64DSPBits), Mips_ACC64DSPRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 350, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 535, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 585, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, + { OCTEON_MPL, OCTEON_MPLBits, 189, 3, sizeof(OCTEON_MPLBits), Mips_OCTEON_MPLRegClassID, 8, 8, 1, 0 }, + { OCTEON_P, OCTEON_PBits, 341, 3, sizeof(OCTEON_PBits), Mips_OCTEON_PRegClassID, 8, 8, 1, 0 }, + { ACC64, ACC64Bits, 105, 1, sizeof(ACC64Bits), Mips_ACC64RegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 449, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips_GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 }, + { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 479, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 }, + { HI64, HI64Bits, 111, 1, sizeof(HI64Bits), Mips_HI64RegClassID, 8, 8, 1, 1 }, + { LO64, LO64Bits, 116, 1, sizeof(LO64Bits), Mips_LO64RegClassID, 8, 8, 1, 1 }, + { MSA128B, MSA128BBits, 149, 32, sizeof(MSA128BBits), Mips_MSA128BRegClassID, 16, 16, 1, 1 }, + { MSA128D, MSA128DBits, 173, 32, sizeof(MSA128DBits), Mips_MSA128DRegClassID, 16, 16, 1, 1 }, + { MSA128H, MSA128HBits, 181, 32, sizeof(MSA128HBits), Mips_MSA128HRegClassID, 16, 16, 1, 1 }, + { MSA128W, MSA128WBits, 441, 32, sizeof(MSA128WBits), Mips_MSA128WRegClassID, 16, 16, 1, 1 }, + { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 275, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips_MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 }, + { MSA128WEvens, MSA128WEvensBits, 767, 16, sizeof(MSA128WEvensBits), Mips_MSA128WEvensRegClassID, 16, 16, 1, 1 }, + { ACC128, ACC128Bits, 142, 1, sizeof(ACC128Bits), Mips_ACC128RegClassID, 16, 16, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsGenSubtargetInfo.inc b/white_patch_detect/capstone-master/arch/Mips/MipsGenSubtargetInfo.inc new file mode 100644 index 0000000..36e7a7f --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsGenSubtargetInfo.inc @@ -0,0 +1,52 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +#define Mips_FeatureCnMips (1ULL << 0) +#define Mips_FeatureDSP (1ULL << 1) +#define Mips_FeatureDSPR2 (1ULL << 2) +#define Mips_FeatureFP64Bit (1ULL << 3) +#define Mips_FeatureFPXX (1ULL << 4) +#define Mips_FeatureGP64Bit (1ULL << 5) +#define Mips_FeatureMSA (1ULL << 6) +#define Mips_FeatureMicroMips (1ULL << 7) +#define Mips_FeatureMips1 (1ULL << 8) +#define Mips_FeatureMips2 (1ULL << 9) +#define Mips_FeatureMips3 (1ULL << 10) +#define Mips_FeatureMips3_32 (1ULL << 11) +#define Mips_FeatureMips3_32r2 (1ULL << 12) +#define Mips_FeatureMips4 (1ULL << 13) +#define Mips_FeatureMips4_32 (1ULL << 14) +#define Mips_FeatureMips4_32r2 (1ULL << 15) +#define Mips_FeatureMips5 (1ULL << 16) +#define Mips_FeatureMips5_32r2 (1ULL << 17) +#define Mips_FeatureMips16 (1ULL << 18) +#define Mips_FeatureMips32 (1ULL << 19) +#define Mips_FeatureMips32r2 (1ULL << 20) +#define Mips_FeatureMips32r3 (1ULL << 21) +#define Mips_FeatureMips32r5 (1ULL << 22) +#define Mips_FeatureMips32r6 (1ULL << 23) +#define Mips_FeatureMips64 (1ULL << 24) +#define Mips_FeatureMips64r2 (1ULL << 25) +#define Mips_FeatureMips64r3 (1ULL << 26) +#define Mips_FeatureMips64r5 (1ULL << 27) +#define Mips_FeatureMips64r6 (1ULL << 28) +#define Mips_FeatureNaN2008 (1ULL << 29) +#define Mips_FeatureNoABICalls (1ULL << 30) +#define Mips_FeatureNoOddSPReg (1ULL << 31) +#define Mips_FeatureSingleFloat (1ULL << 32) +#define Mips_FeatureVFPU (1ULL << 33) + +#endif // GET_SUBTARGETINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.c b/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.c new file mode 100644 index 0000000..9bbf4bc --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.c @@ -0,0 +1,424 @@ +//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an Mips MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_MIPS + +#include +#include +#include // debug +#include + +#include "MipsInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "MipsMapping.h" + +#include "MipsInstPrinter.h" + +static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); +static char *printAliasInstr(MCInst *MI, SStream *O, void *info); +static char *printAlias(MCInst *MI, SStream *OS); + +// These enumeration declarations were originally in MipsInstrInfo.h but +// had to be moved here to avoid circular dependencies between +// LLVMMipsCodeGen and LLVMMipsAsmPrinter. + +// Mips Condition Codes +typedef enum Mips_CondCode { + // To be used with float branch True + Mips_FCOND_F, + Mips_FCOND_UN, + Mips_FCOND_OEQ, + Mips_FCOND_UEQ, + Mips_FCOND_OLT, + Mips_FCOND_ULT, + Mips_FCOND_OLE, + Mips_FCOND_ULE, + Mips_FCOND_SF, + Mips_FCOND_NGLE, + Mips_FCOND_SEQ, + Mips_FCOND_NGL, + Mips_FCOND_LT, + Mips_FCOND_NGE, + Mips_FCOND_LE, + Mips_FCOND_NGT, + + // To be used with float branch False + // This conditions have the same mnemonic as the + // above ones, but are used with a branch False; + Mips_FCOND_T, + Mips_FCOND_OR, + Mips_FCOND_UNE, + Mips_FCOND_ONE, + Mips_FCOND_UGE, + Mips_FCOND_OGE, + Mips_FCOND_UGT, + Mips_FCOND_OGT, + Mips_FCOND_ST, + Mips_FCOND_GLE, + Mips_FCOND_SNE, + Mips_FCOND_GL, + Mips_FCOND_NLT, + Mips_FCOND_GE, + Mips_FCOND_NLE, + Mips_FCOND_GT +} Mips_CondCode; + +#define GET_INSTRINFO_ENUM +#include "MipsGenInstrInfo.inc" + +static const char *getRegisterName(unsigned RegNo); +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); + +static void set_mem_access(MCInst *MI, bool status) +{ + MI->csh->doing_mem = status; + + if (MI->csh->detail != CS_OPT_ON) + return; + + if (status) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->mips.op_count++; + } +} + +static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) +{ + return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && + MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); +} + +static const char* MipsFCCToString(Mips_CondCode CC) +{ + switch (CC) { + default: return 0; // never reach + case Mips_FCOND_F: + case Mips_FCOND_T: return "f"; + case Mips_FCOND_UN: + case Mips_FCOND_OR: return "un"; + case Mips_FCOND_OEQ: + case Mips_FCOND_UNE: return "eq"; + case Mips_FCOND_UEQ: + case Mips_FCOND_ONE: return "ueq"; + case Mips_FCOND_OLT: + case Mips_FCOND_UGE: return "olt"; + case Mips_FCOND_ULT: + case Mips_FCOND_OGE: return "ult"; + case Mips_FCOND_OLE: + case Mips_FCOND_UGT: return "ole"; + case Mips_FCOND_ULE: + case Mips_FCOND_OGT: return "ule"; + case Mips_FCOND_SF: + case Mips_FCOND_ST: return "sf"; + case Mips_FCOND_NGLE: + case Mips_FCOND_GLE: return "ngle"; + case Mips_FCOND_SEQ: + case Mips_FCOND_SNE: return "seq"; + case Mips_FCOND_NGL: + case Mips_FCOND_GL: return "ngl"; + case Mips_FCOND_LT: + case Mips_FCOND_NLT: return "lt"; + case Mips_FCOND_NGE: + case Mips_FCOND_GE: return "nge"; + case Mips_FCOND_LE: + case Mips_FCOND_NLE: return "le"; + case Mips_FCOND_NGT: + case Mips_FCOND_GT: return "ngt"; + } +} + +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat(OS, "$%s", getRegisterName(RegNo)); +} + +void Mips_printInst(MCInst *MI, SStream *O, void *info) +{ + char *mnem; + + switch (MCInst_getOpcode(MI)) { + default: break; + case Mips_Save16: + case Mips_SaveX16: + case Mips_Restore16: + case Mips_RestoreX16: + return; + } + + // Try to print any aliases first. + mnem = printAliasInstr(MI, O, info); + if (!mnem) { + mnem = printAlias(MI, O); + if (!mnem) { + printInstruction(MI, O, NULL); + } + } + + if (mnem) { + // fixup instruction id due to the change in alias instruction + MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); + cs_mem_free(mnem); + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op; + + if (OpNo >= MI->size) + return; + + Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + unsigned int reg = MCOperand_getReg(Op); + printRegName(O, reg); + reg = Mips_map_register(reg); + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; + } else { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; + MI->flat_insn->detail->mips.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op); + if (MI->csh->doing_mem) { + if (imm) { // only print Imm offset if it is not 0 + printInt64(O, imm); + } + if (MI->csh->detail) + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; + } else { + printInt64(O, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; + MI->flat_insn->detail->mips.op_count++; + } + } + } +} + +static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, opNum); + if (MCOperand_isImm(MO)) { + int64_t imm = MCOperand_getImm(MO); + printInt64(O, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; + MI->flat_insn->detail->mips.op_count++; + } + } else + printOperand(MI, opNum, O); +} + +static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, opNum); + if (MCOperand_isImm(MO)) { + uint8_t imm = (uint8_t)MCOperand_getImm(MO); + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", imm); + else + SStream_concat(O, "%u", imm); + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; + MI->flat_insn->detail->mips.op_count++; + } + } else + printOperand(MI, opNum, O); +} + +static void printMemOperand(MCInst *MI, int opNum, SStream *O) +{ + // Load/Store memory operands -- imm($reg) + // If PIC target the target is loaded as the + // pattern lw $25,%call16($28) + + // opNum can be invalid if instruction had reglist as operand. + // MemOperand is always last operand of instruction (base + offset). + switch (MCInst_getOpcode(MI)) { + default: + break; + case Mips_SWM32_MM: + case Mips_LWM32_MM: + case Mips_SWM16_MM: + case Mips_LWM16_MM: + opNum = MCInst_getNumOperands(MI) - 2; + break; + } + + set_mem_access(MI, true); + printOperand(MI, opNum + 1, O); + SStream_concat0(O, "("); + printOperand(MI, opNum, O); + SStream_concat0(O, ")"); + set_mem_access(MI, false); +} + +// TODO??? +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) +{ + // when using stack locations for not load/store instructions + // print the same way as all normal 3 operand instructions. + printOperand(MI, opNum, O); + SStream_concat0(O, ", "); + printOperand(MI, opNum + 1, O); + return; +} + +static void printFCCOperand(MCInst *MI, int opNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, opNum); + SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); +} + +static void printRegisterPair(MCInst *MI, int opNum, SStream *O) +{ + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); +} + +static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) +{ + SStream_concat(OS, "%s\t", Str); + printOperand(MI, OpNo, OS); + return cs_strdup(Str); +} + +static char *printAlias2(const char *Str, MCInst *MI, + unsigned OpNo0, unsigned OpNo1, SStream *OS) +{ + char *tmp; + + tmp = printAlias1(Str, MI, OpNo0, OS); + SStream_concat0(OS, ", "); + printOperand(MI, OpNo1, OS); + + return tmp; +} + +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" + +static char *printAlias(MCInst *MI, SStream *OS) +{ + switch (MCInst_getOpcode(MI)) { + case Mips_BEQ: + case Mips_BEQ_MM: + // beq $zero, $zero, $L2 => b $L2 + // beq $r0, $zero, $L2 => beqz $r0, $L2 + if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) + return printAlias1("b", MI, 2, OS); + if (isReg(MI, 1, Mips_ZERO)) + return printAlias2("beqz", MI, 0, 2, OS); + return NULL; + case Mips_BEQ64: + // beq $r0, $zero, $L2 => beqz $r0, $L2 + if (isReg(MI, 1, Mips_ZERO_64)) + return printAlias2("beqz", MI, 0, 2, OS); + return NULL; + case Mips_BNE: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + if (isReg(MI, 1, Mips_ZERO)) + return printAlias2("bnez", MI, 0, 2, OS); + return NULL; + case Mips_BNE64: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + if (isReg(MI, 1, Mips_ZERO_64)) + return printAlias2("bnez", MI, 0, 2, OS); + return NULL; + case Mips_BGEZAL: + // bgezal $zero, $L1 => bal $L1 + if (isReg(MI, 0, Mips_ZERO)) + return printAlias1("bal", MI, 1, OS); + return NULL; + case Mips_BC1T: + // bc1t $fcc0, $L1 => bc1t $L1 + if (isReg(MI, 0, Mips_FCC0)) + return printAlias1("bc1t", MI, 1, OS); + return NULL; + case Mips_BC1F: + // bc1f $fcc0, $L1 => bc1f $L1 + if (isReg(MI, 0, Mips_FCC0)) + return printAlias1("bc1f", MI, 1, OS); + return NULL; + case Mips_JALR: + // jalr $ra, $r1 => jalr $r1 + if (isReg(MI, 0, Mips_RA)) + return printAlias1("jalr", MI, 1, OS); + return NULL; + case Mips_JALR64: + // jalr $ra, $r1 => jalr $r1 + if (isReg(MI, 0, Mips_RA_64)) + return printAlias1("jalr", MI, 1, OS); + return NULL; + case Mips_NOR: + case Mips_NOR_MM: + // nor $r0, $r1, $zero => not $r0, $r1 + if (isReg(MI, 2, Mips_ZERO)) + return printAlias2("not", MI, 0, 1, OS); + return NULL; + case Mips_NOR64: + // nor $r0, $r1, $zero => not $r0, $r1 + if (isReg(MI, 2, Mips_ZERO_64)) + return printAlias2("not", MI, 0, 1, OS); + return NULL; + case Mips_OR: + // or $r0, $r1, $zero => move $r0, $r1 + if (isReg(MI, 2, Mips_ZERO)) + return printAlias2("move", MI, 0, 1, OS); + return NULL; + default: return NULL; + } +} + +static void printRegisterList(MCInst *MI, int opNum, SStream *O) +{ + int i, e, reg; + + // - 2 because register List is always first operand of instruction and it is + // always followed by memory operand (base + offset). + for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { + if (i != opNum) + SStream_concat0(O, ", "); + reg = MCOperand_getReg(MCInst_getOperand(MI, i)); + printRegName(O, reg); + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; + MI->flat_insn->detail->mips.op_count++; + } + } +} + +#define PRINT_ALIAS_INSTR +#include "MipsGenAsmWriter.inc" + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.h b/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.h new file mode 100644 index 0000000..659ef77 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsInstPrinter.h @@ -0,0 +1,25 @@ +//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints a Mips MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_MIPSINSTPRINTER_H +#define CS_MIPSINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../SStream.h" + +void Mips_printInst(MCInst *MI, SStream *O, void *info); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsMapping.c b/white_patch_detect/capstone-master/arch/Mips/MipsMapping.c new file mode 100644 index 0000000..9f50836 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsMapping.c @@ -0,0 +1,1070 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_MIPS + +#include // debug +#include + +#include "../../utils.h" + +#include "MipsMapping.h" + +#define GET_INSTRINFO_ENUM +#include "MipsGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { MIPS_REG_INVALID, NULL }, + + { MIPS_REG_PC, "pc"}, + + //{ MIPS_REG_0, "0"}, + { MIPS_REG_0, "zero"}, + { MIPS_REG_1, "at"}, + //{ MIPS_REG_1, "1"}, + { MIPS_REG_2, "v0"}, + //{ MIPS_REG_2, "2"}, + { MIPS_REG_3, "v1"}, + //{ MIPS_REG_3, "3"}, + { MIPS_REG_4, "a0"}, + //{ MIPS_REG_4, "4"}, + { MIPS_REG_5, "a1"}, + //{ MIPS_REG_5, "5"}, + { MIPS_REG_6, "a2"}, + //{ MIPS_REG_6, "6"}, + { MIPS_REG_7, "a3"}, + //{ MIPS_REG_7, "7"}, + { MIPS_REG_8, "t0"}, + //{ MIPS_REG_8, "8"}, + { MIPS_REG_9, "t1"}, + //{ MIPS_REG_9, "9"}, + { MIPS_REG_10, "t2"}, + //{ MIPS_REG_10, "10"}, + { MIPS_REG_11, "t3"}, + //{ MIPS_REG_11, "11"}, + { MIPS_REG_12, "t4"}, + //{ MIPS_REG_12, "12"}, + { MIPS_REG_13, "t5"}, + //{ MIPS_REG_13, "13"}, + { MIPS_REG_14, "t6"}, + //{ MIPS_REG_14, "14"}, + { MIPS_REG_15, "t7"}, + //{ MIPS_REG_15, "15"}, + { MIPS_REG_16, "s0"}, + //{ MIPS_REG_16, "16"}, + { MIPS_REG_17, "s1"}, + //{ MIPS_REG_17, "17"}, + { MIPS_REG_18, "s2"}, + //{ MIPS_REG_18, "18"}, + { MIPS_REG_19, "s3"}, + //{ MIPS_REG_19, "19"}, + { MIPS_REG_20, "s4"}, + //{ MIPS_REG_20, "20"}, + { MIPS_REG_21, "s5"}, + //{ MIPS_REG_21, "21"}, + { MIPS_REG_22, "s6"}, + //{ MIPS_REG_22, "22"}, + { MIPS_REG_23, "s7"}, + //{ MIPS_REG_23, "23"}, + { MIPS_REG_24, "t8"}, + //{ MIPS_REG_24, "24"}, + { MIPS_REG_25, "t9"}, + //{ MIPS_REG_25, "25"}, + { MIPS_REG_26, "k0"}, + //{ MIPS_REG_26, "26"}, + { MIPS_REG_27, "k1"}, + //{ MIPS_REG_27, "27"}, + { MIPS_REG_28, "gp"}, + //{ MIPS_REG_28, "28"}, + { MIPS_REG_29, "sp"}, + //{ MIPS_REG_29, "29"}, + { MIPS_REG_30, "fp"}, + //{ MIPS_REG_30, "30"}, + { MIPS_REG_31, "ra"}, + //{ MIPS_REG_31, "31"}, + + { MIPS_REG_DSPCCOND, "dspccond"}, + { MIPS_REG_DSPCARRY, "dspcarry"}, + { MIPS_REG_DSPEFI, "dspefi"}, + { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, + { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, + { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, + { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, + { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, + { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, + { MIPS_REG_DSPPOS, "dsppos"}, + { MIPS_REG_DSPSCOUNT, "dspscount"}, + + { MIPS_REG_AC0, "ac0"}, + { MIPS_REG_AC1, "ac1"}, + { MIPS_REG_AC2, "ac2"}, + { MIPS_REG_AC3, "ac3"}, + + { MIPS_REG_CC0, "cc0"}, + { MIPS_REG_CC1, "cc1"}, + { MIPS_REG_CC2, "cc2"}, + { MIPS_REG_CC3, "cc3"}, + { MIPS_REG_CC4, "cc4"}, + { MIPS_REG_CC5, "cc5"}, + { MIPS_REG_CC6, "cc6"}, + { MIPS_REG_CC7, "cc7"}, + + { MIPS_REG_F0, "f0"}, + { MIPS_REG_F1, "f1"}, + { MIPS_REG_F2, "f2"}, + { MIPS_REG_F3, "f3"}, + { MIPS_REG_F4, "f4"}, + { MIPS_REG_F5, "f5"}, + { MIPS_REG_F6, "f6"}, + { MIPS_REG_F7, "f7"}, + { MIPS_REG_F8, "f8"}, + { MIPS_REG_F9, "f9"}, + { MIPS_REG_F10, "f10"}, + { MIPS_REG_F11, "f11"}, + { MIPS_REG_F12, "f12"}, + { MIPS_REG_F13, "f13"}, + { MIPS_REG_F14, "f14"}, + { MIPS_REG_F15, "f15"}, + { MIPS_REG_F16, "f16"}, + { MIPS_REG_F17, "f17"}, + { MIPS_REG_F18, "f18"}, + { MIPS_REG_F19, "f19"}, + { MIPS_REG_F20, "f20"}, + { MIPS_REG_F21, "f21"}, + { MIPS_REG_F22, "f22"}, + { MIPS_REG_F23, "f23"}, + { MIPS_REG_F24, "f24"}, + { MIPS_REG_F25, "f25"}, + { MIPS_REG_F26, "f26"}, + { MIPS_REG_F27, "f27"}, + { MIPS_REG_F28, "f28"}, + { MIPS_REG_F29, "f29"}, + { MIPS_REG_F30, "f30"}, + { MIPS_REG_F31, "f31"}, + + { MIPS_REG_FCC0, "fcc0"}, + { MIPS_REG_FCC1, "fcc1"}, + { MIPS_REG_FCC2, "fcc2"}, + { MIPS_REG_FCC3, "fcc3"}, + { MIPS_REG_FCC4, "fcc4"}, + { MIPS_REG_FCC5, "fcc5"}, + { MIPS_REG_FCC6, "fcc6"}, + { MIPS_REG_FCC7, "fcc7"}, + + { MIPS_REG_W0, "w0"}, + { MIPS_REG_W1, "w1"}, + { MIPS_REG_W2, "w2"}, + { MIPS_REG_W3, "w3"}, + { MIPS_REG_W4, "w4"}, + { MIPS_REG_W5, "w5"}, + { MIPS_REG_W6, "w6"}, + { MIPS_REG_W7, "w7"}, + { MIPS_REG_W8, "w8"}, + { MIPS_REG_W9, "w9"}, + { MIPS_REG_W10, "w10"}, + { MIPS_REG_W11, "w11"}, + { MIPS_REG_W12, "w12"}, + { MIPS_REG_W13, "w13"}, + { MIPS_REG_W14, "w14"}, + { MIPS_REG_W15, "w15"}, + { MIPS_REG_W16, "w16"}, + { MIPS_REG_W17, "w17"}, + { MIPS_REG_W18, "w18"}, + { MIPS_REG_W19, "w19"}, + { MIPS_REG_W20, "w20"}, + { MIPS_REG_W21, "w21"}, + { MIPS_REG_W22, "w22"}, + { MIPS_REG_W23, "w23"}, + { MIPS_REG_W24, "w24"}, + { MIPS_REG_W25, "w25"}, + { MIPS_REG_W26, "w26"}, + { MIPS_REG_W27, "w27"}, + { MIPS_REG_W28, "w28"}, + { MIPS_REG_W29, "w29"}, + { MIPS_REG_W30, "w30"}, + { MIPS_REG_W31, "w31"}, + + { MIPS_REG_HI, "hi"}, + { MIPS_REG_LO, "lo"}, + + { MIPS_REG_P0, "p0"}, + { MIPS_REG_P1, "p1"}, + { MIPS_REG_P2, "p2"}, + + { MIPS_REG_MPL0, "mpl0"}, + { MIPS_REG_MPL1, "mpl1"}, + { MIPS_REG_MPL2, "mpl2"}, +}; +#endif + +const char *Mips_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "MipsMappingInsn.inc" +}; + +// given internal insn id, return public instruction info +void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned int i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + } + } +} + +static const name_map insn_name_maps[] = { + { MIPS_INS_INVALID, NULL }, + + { MIPS_INS_ABSQ_S, "absq_s" }, + { MIPS_INS_ADD, "add" }, + { MIPS_INS_ADDIUPC, "addiupc" }, + { MIPS_INS_ADDIUR1SP, "addiur1sp" }, + { MIPS_INS_ADDIUR2, "addiur2" }, + { MIPS_INS_ADDIUS5, "addius5" }, + { MIPS_INS_ADDIUSP, "addiusp" }, + { MIPS_INS_ADDQH, "addqh" }, + { MIPS_INS_ADDQH_R, "addqh_r" }, + { MIPS_INS_ADDQ, "addq" }, + { MIPS_INS_ADDQ_S, "addq_s" }, + { MIPS_INS_ADDSC, "addsc" }, + { MIPS_INS_ADDS_A, "adds_a" }, + { MIPS_INS_ADDS_S, "adds_s" }, + { MIPS_INS_ADDS_U, "adds_u" }, + { MIPS_INS_ADDU16, "addu16" }, + { MIPS_INS_ADDUH, "adduh" }, + { MIPS_INS_ADDUH_R, "adduh_r" }, + { MIPS_INS_ADDU, "addu" }, + { MIPS_INS_ADDU_S, "addu_s" }, + { MIPS_INS_ADDVI, "addvi" }, + { MIPS_INS_ADDV, "addv" }, + { MIPS_INS_ADDWC, "addwc" }, + { MIPS_INS_ADD_A, "add_a" }, + { MIPS_INS_ADDI, "addi" }, + { MIPS_INS_ADDIU, "addiu" }, + { MIPS_INS_ALIGN, "align" }, + { MIPS_INS_ALUIPC, "aluipc" }, + { MIPS_INS_AND, "and" }, + { MIPS_INS_AND16, "and16" }, + { MIPS_INS_ANDI16, "andi16" }, + { MIPS_INS_ANDI, "andi" }, + { MIPS_INS_APPEND, "append" }, + { MIPS_INS_ASUB_S, "asub_s" }, + { MIPS_INS_ASUB_U, "asub_u" }, + { MIPS_INS_AUI, "aui" }, + { MIPS_INS_AUIPC, "auipc" }, + { MIPS_INS_AVER_S, "aver_s" }, + { MIPS_INS_AVER_U, "aver_u" }, + { MIPS_INS_AVE_S, "ave_s" }, + { MIPS_INS_AVE_U, "ave_u" }, + { MIPS_INS_B16, "b16" }, + { MIPS_INS_BADDU, "baddu" }, + { MIPS_INS_BAL, "bal" }, + { MIPS_INS_BALC, "balc" }, + { MIPS_INS_BALIGN, "balign" }, + { MIPS_INS_BBIT0, "bbit0" }, + { MIPS_INS_BBIT032, "bbit032" }, + { MIPS_INS_BBIT1, "bbit1" }, + { MIPS_INS_BBIT132, "bbit132" }, + { MIPS_INS_BC, "bc" }, + { MIPS_INS_BC0F, "bc0f" }, + { MIPS_INS_BC0FL, "bc0fl" }, + { MIPS_INS_BC0T, "bc0t" }, + { MIPS_INS_BC0TL, "bc0tl" }, + { MIPS_INS_BC1EQZ, "bc1eqz" }, + { MIPS_INS_BC1F, "bc1f" }, + { MIPS_INS_BC1FL, "bc1fl" }, + { MIPS_INS_BC1NEZ, "bc1nez" }, + { MIPS_INS_BC1T, "bc1t" }, + { MIPS_INS_BC1TL, "bc1tl" }, + { MIPS_INS_BC2EQZ, "bc2eqz" }, + { MIPS_INS_BC2F, "bc2f" }, + { MIPS_INS_BC2FL, "bc2fl" }, + { MIPS_INS_BC2NEZ, "bc2nez" }, + { MIPS_INS_BC2T, "bc2t" }, + { MIPS_INS_BC2TL, "bc2tl" }, + { MIPS_INS_BC3F, "bc3f" }, + { MIPS_INS_BC3FL, "bc3fl" }, + { MIPS_INS_BC3T, "bc3t" }, + { MIPS_INS_BC3TL, "bc3tl" }, + { MIPS_INS_BCLRI, "bclri" }, + { MIPS_INS_BCLR, "bclr" }, + { MIPS_INS_BEQ, "beq" }, + { MIPS_INS_BEQC, "beqc" }, + { MIPS_INS_BEQL, "beql" }, + { MIPS_INS_BEQZ16, "beqz16" }, + { MIPS_INS_BEQZALC, "beqzalc" }, + { MIPS_INS_BEQZC, "beqzc" }, + { MIPS_INS_BGEC, "bgec" }, + { MIPS_INS_BGEUC, "bgeuc" }, + { MIPS_INS_BGEZ, "bgez" }, + { MIPS_INS_BGEZAL, "bgezal" }, + { MIPS_INS_BGEZALC, "bgezalc" }, + { MIPS_INS_BGEZALL, "bgezall" }, + { MIPS_INS_BGEZALS, "bgezals" }, + { MIPS_INS_BGEZC, "bgezc" }, + { MIPS_INS_BGEZL, "bgezl" }, + { MIPS_INS_BGTZ, "bgtz" }, + { MIPS_INS_BGTZALC, "bgtzalc" }, + { MIPS_INS_BGTZC, "bgtzc" }, + { MIPS_INS_BGTZL, "bgtzl" }, + { MIPS_INS_BINSLI, "binsli" }, + { MIPS_INS_BINSL, "binsl" }, + { MIPS_INS_BINSRI, "binsri" }, + { MIPS_INS_BINSR, "binsr" }, + { MIPS_INS_BITREV, "bitrev" }, + { MIPS_INS_BITSWAP, "bitswap" }, + { MIPS_INS_BLEZ, "blez" }, + { MIPS_INS_BLEZALC, "blezalc" }, + { MIPS_INS_BLEZC, "blezc" }, + { MIPS_INS_BLEZL, "blezl" }, + { MIPS_INS_BLTC, "bltc" }, + { MIPS_INS_BLTUC, "bltuc" }, + { MIPS_INS_BLTZ, "bltz" }, + { MIPS_INS_BLTZAL, "bltzal" }, + { MIPS_INS_BLTZALC, "bltzalc" }, + { MIPS_INS_BLTZALL, "bltzall" }, + { MIPS_INS_BLTZALS, "bltzals" }, + { MIPS_INS_BLTZC, "bltzc" }, + { MIPS_INS_BLTZL, "bltzl" }, + { MIPS_INS_BMNZI, "bmnzi" }, + { MIPS_INS_BMNZ, "bmnz" }, + { MIPS_INS_BMZI, "bmzi" }, + { MIPS_INS_BMZ, "bmz" }, + { MIPS_INS_BNE, "bne" }, + { MIPS_INS_BNEC, "bnec" }, + { MIPS_INS_BNEGI, "bnegi" }, + { MIPS_INS_BNEG, "bneg" }, + { MIPS_INS_BNEL, "bnel" }, + { MIPS_INS_BNEZ16, "bnez16" }, + { MIPS_INS_BNEZALC, "bnezalc" }, + { MIPS_INS_BNEZC, "bnezc" }, + { MIPS_INS_BNVC, "bnvc" }, + { MIPS_INS_BNZ, "bnz" }, + { MIPS_INS_BOVC, "bovc" }, + { MIPS_INS_BPOSGE32, "bposge32" }, + { MIPS_INS_BREAK, "break" }, + { MIPS_INS_BREAK16, "break16" }, + { MIPS_INS_BSELI, "bseli" }, + { MIPS_INS_BSEL, "bsel" }, + { MIPS_INS_BSETI, "bseti" }, + { MIPS_INS_BSET, "bset" }, + { MIPS_INS_BZ, "bz" }, + { MIPS_INS_BEQZ, "beqz" }, + { MIPS_INS_B, "b" }, + { MIPS_INS_BNEZ, "bnez" }, + { MIPS_INS_BTEQZ, "bteqz" }, + { MIPS_INS_BTNEZ, "btnez" }, + { MIPS_INS_CACHE, "cache" }, + { MIPS_INS_CEIL, "ceil" }, + { MIPS_INS_CEQI, "ceqi" }, + { MIPS_INS_CEQ, "ceq" }, + { MIPS_INS_CFC1, "cfc1" }, + { MIPS_INS_CFCMSA, "cfcmsa" }, + { MIPS_INS_CINS, "cins" }, + { MIPS_INS_CINS32, "cins32" }, + { MIPS_INS_CLASS, "class" }, + { MIPS_INS_CLEI_S, "clei_s" }, + { MIPS_INS_CLEI_U, "clei_u" }, + { MIPS_INS_CLE_S, "cle_s" }, + { MIPS_INS_CLE_U, "cle_u" }, + { MIPS_INS_CLO, "clo" }, + { MIPS_INS_CLTI_S, "clti_s" }, + { MIPS_INS_CLTI_U, "clti_u" }, + { MIPS_INS_CLT_S, "clt_s" }, + { MIPS_INS_CLT_U, "clt_u" }, + { MIPS_INS_CLZ, "clz" }, + { MIPS_INS_CMPGDU, "cmpgdu" }, + { MIPS_INS_CMPGU, "cmpgu" }, + { MIPS_INS_CMPU, "cmpu" }, + { MIPS_INS_CMP, "cmp" }, + { MIPS_INS_COPY_S, "copy_s" }, + { MIPS_INS_COPY_U, "copy_u" }, + { MIPS_INS_CTC1, "ctc1" }, + { MIPS_INS_CTCMSA, "ctcmsa" }, + { MIPS_INS_CVT, "cvt" }, + { MIPS_INS_C, "c" }, + { MIPS_INS_CMPI, "cmpi" }, + { MIPS_INS_DADD, "dadd" }, + { MIPS_INS_DADDI, "daddi" }, + { MIPS_INS_DADDIU, "daddiu" }, + { MIPS_INS_DADDU, "daddu" }, + { MIPS_INS_DAHI, "dahi" }, + { MIPS_INS_DALIGN, "dalign" }, + { MIPS_INS_DATI, "dati" }, + { MIPS_INS_DAUI, "daui" }, + { MIPS_INS_DBITSWAP, "dbitswap" }, + { MIPS_INS_DCLO, "dclo" }, + { MIPS_INS_DCLZ, "dclz" }, + { MIPS_INS_DDIV, "ddiv" }, + { MIPS_INS_DDIVU, "ddivu" }, + { MIPS_INS_DERET, "deret" }, + { MIPS_INS_DEXT, "dext" }, + { MIPS_INS_DEXTM, "dextm" }, + { MIPS_INS_DEXTU, "dextu" }, + { MIPS_INS_DI, "di" }, + { MIPS_INS_DINS, "dins" }, + { MIPS_INS_DINSM, "dinsm" }, + { MIPS_INS_DINSU, "dinsu" }, + { MIPS_INS_DIV, "div" }, + { MIPS_INS_DIVU, "divu" }, + { MIPS_INS_DIV_S, "div_s" }, + { MIPS_INS_DIV_U, "div_u" }, + { MIPS_INS_DLSA, "dlsa" }, + { MIPS_INS_DMFC0, "dmfc0" }, + { MIPS_INS_DMFC1, "dmfc1" }, + { MIPS_INS_DMFC2, "dmfc2" }, + { MIPS_INS_DMOD, "dmod" }, + { MIPS_INS_DMODU, "dmodu" }, + { MIPS_INS_DMTC0, "dmtc0" }, + { MIPS_INS_DMTC1, "dmtc1" }, + { MIPS_INS_DMTC2, "dmtc2" }, + { MIPS_INS_DMUH, "dmuh" }, + { MIPS_INS_DMUHU, "dmuhu" }, + { MIPS_INS_DMUL, "dmul" }, + { MIPS_INS_DMULT, "dmult" }, + { MIPS_INS_DMULTU, "dmultu" }, + { MIPS_INS_DMULU, "dmulu" }, + { MIPS_INS_DOTP_S, "dotp_s" }, + { MIPS_INS_DOTP_U, "dotp_u" }, + { MIPS_INS_DPADD_S, "dpadd_s" }, + { MIPS_INS_DPADD_U, "dpadd_u" }, + { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, + { MIPS_INS_DPAQX_S, "dpaqx_s" }, + { MIPS_INS_DPAQ_SA, "dpaq_sa" }, + { MIPS_INS_DPAQ_S, "dpaq_s" }, + { MIPS_INS_DPAU, "dpau" }, + { MIPS_INS_DPAX, "dpax" }, + { MIPS_INS_DPA, "dpa" }, + { MIPS_INS_DPOP, "dpop" }, + { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, + { MIPS_INS_DPSQX_S, "dpsqx_s" }, + { MIPS_INS_DPSQ_SA, "dpsq_sa" }, + { MIPS_INS_DPSQ_S, "dpsq_s" }, + { MIPS_INS_DPSUB_S, "dpsub_s" }, + { MIPS_INS_DPSUB_U, "dpsub_u" }, + { MIPS_INS_DPSU, "dpsu" }, + { MIPS_INS_DPSX, "dpsx" }, + { MIPS_INS_DPS, "dps" }, + { MIPS_INS_DROTR, "drotr" }, + { MIPS_INS_DROTR32, "drotr32" }, + { MIPS_INS_DROTRV, "drotrv" }, + { MIPS_INS_DSBH, "dsbh" }, + { MIPS_INS_DSHD, "dshd" }, + { MIPS_INS_DSLL, "dsll" }, + { MIPS_INS_DSLL32, "dsll32" }, + { MIPS_INS_DSLLV, "dsllv" }, + { MIPS_INS_DSRA, "dsra" }, + { MIPS_INS_DSRA32, "dsra32" }, + { MIPS_INS_DSRAV, "dsrav" }, + { MIPS_INS_DSRL, "dsrl" }, + { MIPS_INS_DSRL32, "dsrl32" }, + { MIPS_INS_DSRLV, "dsrlv" }, + { MIPS_INS_DSUB, "dsub" }, + { MIPS_INS_DSUBU, "dsubu" }, + { MIPS_INS_EHB, "ehb" }, + { MIPS_INS_EI, "ei" }, + { MIPS_INS_ERET, "eret" }, + { MIPS_INS_EXT, "ext" }, + { MIPS_INS_EXTP, "extp" }, + { MIPS_INS_EXTPDP, "extpdp" }, + { MIPS_INS_EXTPDPV, "extpdpv" }, + { MIPS_INS_EXTPV, "extpv" }, + { MIPS_INS_EXTRV_RS, "extrv_rs" }, + { MIPS_INS_EXTRV_R, "extrv_r" }, + { MIPS_INS_EXTRV_S, "extrv_s" }, + { MIPS_INS_EXTRV, "extrv" }, + { MIPS_INS_EXTR_RS, "extr_rs" }, + { MIPS_INS_EXTR_R, "extr_r" }, + { MIPS_INS_EXTR_S, "extr_s" }, + { MIPS_INS_EXTR, "extr" }, + { MIPS_INS_EXTS, "exts" }, + { MIPS_INS_EXTS32, "exts32" }, + { MIPS_INS_ABS, "abs" }, + { MIPS_INS_FADD, "fadd" }, + { MIPS_INS_FCAF, "fcaf" }, + { MIPS_INS_FCEQ, "fceq" }, + { MIPS_INS_FCLASS, "fclass" }, + { MIPS_INS_FCLE, "fcle" }, + { MIPS_INS_FCLT, "fclt" }, + { MIPS_INS_FCNE, "fcne" }, + { MIPS_INS_FCOR, "fcor" }, + { MIPS_INS_FCUEQ, "fcueq" }, + { MIPS_INS_FCULE, "fcule" }, + { MIPS_INS_FCULT, "fcult" }, + { MIPS_INS_FCUNE, "fcune" }, + { MIPS_INS_FCUN, "fcun" }, + { MIPS_INS_FDIV, "fdiv" }, + { MIPS_INS_FEXDO, "fexdo" }, + { MIPS_INS_FEXP2, "fexp2" }, + { MIPS_INS_FEXUPL, "fexupl" }, + { MIPS_INS_FEXUPR, "fexupr" }, + { MIPS_INS_FFINT_S, "ffint_s" }, + { MIPS_INS_FFINT_U, "ffint_u" }, + { MIPS_INS_FFQL, "ffql" }, + { MIPS_INS_FFQR, "ffqr" }, + { MIPS_INS_FILL, "fill" }, + { MIPS_INS_FLOG2, "flog2" }, + { MIPS_INS_FLOOR, "floor" }, + { MIPS_INS_FMADD, "fmadd" }, + { MIPS_INS_FMAX_A, "fmax_a" }, + { MIPS_INS_FMAX, "fmax" }, + { MIPS_INS_FMIN_A, "fmin_a" }, + { MIPS_INS_FMIN, "fmin" }, + { MIPS_INS_MOV, "mov" }, + { MIPS_INS_FMSUB, "fmsub" }, + { MIPS_INS_FMUL, "fmul" }, + { MIPS_INS_MUL, "mul" }, + { MIPS_INS_NEG, "neg" }, + { MIPS_INS_FRCP, "frcp" }, + { MIPS_INS_FRINT, "frint" }, + { MIPS_INS_FRSQRT, "frsqrt" }, + { MIPS_INS_FSAF, "fsaf" }, + { MIPS_INS_FSEQ, "fseq" }, + { MIPS_INS_FSLE, "fsle" }, + { MIPS_INS_FSLT, "fslt" }, + { MIPS_INS_FSNE, "fsne" }, + { MIPS_INS_FSOR, "fsor" }, + { MIPS_INS_FSQRT, "fsqrt" }, + { MIPS_INS_SQRT, "sqrt" }, + { MIPS_INS_FSUB, "fsub" }, + { MIPS_INS_SUB, "sub" }, + { MIPS_INS_FSUEQ, "fsueq" }, + { MIPS_INS_FSULE, "fsule" }, + { MIPS_INS_FSULT, "fsult" }, + { MIPS_INS_FSUNE, "fsune" }, + { MIPS_INS_FSUN, "fsun" }, + { MIPS_INS_FTINT_S, "ftint_s" }, + { MIPS_INS_FTINT_U, "ftint_u" }, + { MIPS_INS_FTQ, "ftq" }, + { MIPS_INS_FTRUNC_S, "ftrunc_s" }, + { MIPS_INS_FTRUNC_U, "ftrunc_u" }, + { MIPS_INS_HADD_S, "hadd_s" }, + { MIPS_INS_HADD_U, "hadd_u" }, + { MIPS_INS_HSUB_S, "hsub_s" }, + { MIPS_INS_HSUB_U, "hsub_u" }, + { MIPS_INS_ILVEV, "ilvev" }, + { MIPS_INS_ILVL, "ilvl" }, + { MIPS_INS_ILVOD, "ilvod" }, + { MIPS_INS_ILVR, "ilvr" }, + { MIPS_INS_INS, "ins" }, + { MIPS_INS_INSERT, "insert" }, + { MIPS_INS_INSV, "insv" }, + { MIPS_INS_INSVE, "insve" }, + { MIPS_INS_J, "j" }, + { MIPS_INS_JAL, "jal" }, + { MIPS_INS_JALR, "jalr" }, + { MIPS_INS_JALRS16, "jalrs16" }, + { MIPS_INS_JALRS, "jalrs" }, + { MIPS_INS_JALS, "jals" }, + { MIPS_INS_JALX, "jalx" }, + { MIPS_INS_JIALC, "jialc" }, + { MIPS_INS_JIC, "jic" }, + { MIPS_INS_JR, "jr" }, + { MIPS_INS_JR16, "jr16" }, + { MIPS_INS_JRADDIUSP, "jraddiusp" }, + { MIPS_INS_JRC, "jrc" }, + { MIPS_INS_JALRC, "jalrc" }, + { MIPS_INS_LB, "lb" }, + { MIPS_INS_LBU16, "lbu16" }, + { MIPS_INS_LBUX, "lbux" }, + { MIPS_INS_LBU, "lbu" }, + { MIPS_INS_LD, "ld" }, + { MIPS_INS_LDC1, "ldc1" }, + { MIPS_INS_LDC2, "ldc2" }, + { MIPS_INS_LDC3, "ldc3" }, + { MIPS_INS_LDI, "ldi" }, + { MIPS_INS_LDL, "ldl" }, + { MIPS_INS_LDPC, "ldpc" }, + { MIPS_INS_LDR, "ldr" }, + { MIPS_INS_LDXC1, "ldxc1" }, + { MIPS_INS_LH, "lh" }, + { MIPS_INS_LHU16, "lhu16" }, + { MIPS_INS_LHX, "lhx" }, + { MIPS_INS_LHU, "lhu" }, + { MIPS_INS_LI16, "li16" }, + { MIPS_INS_LL, "ll" }, + { MIPS_INS_LLD, "lld" }, + { MIPS_INS_LSA, "lsa" }, + { MIPS_INS_LUXC1, "luxc1" }, + { MIPS_INS_LUI, "lui" }, + { MIPS_INS_LW, "lw" }, + { MIPS_INS_LW16, "lw16" }, + { MIPS_INS_LWC1, "lwc1" }, + { MIPS_INS_LWC2, "lwc2" }, + { MIPS_INS_LWC3, "lwc3" }, + { MIPS_INS_LWL, "lwl" }, + { MIPS_INS_LWM16, "lwm16" }, + { MIPS_INS_LWM32, "lwm32" }, + { MIPS_INS_LWPC, "lwpc" }, + { MIPS_INS_LWP, "lwp" }, + { MIPS_INS_LWR, "lwr" }, + { MIPS_INS_LWUPC, "lwupc" }, + { MIPS_INS_LWU, "lwu" }, + { MIPS_INS_LWX, "lwx" }, + { MIPS_INS_LWXC1, "lwxc1" }, + { MIPS_INS_LWXS, "lwxs" }, + { MIPS_INS_LI, "li" }, + { MIPS_INS_MADD, "madd" }, + { MIPS_INS_MADDF, "maddf" }, + { MIPS_INS_MADDR_Q, "maddr_q" }, + { MIPS_INS_MADDU, "maddu" }, + { MIPS_INS_MADDV, "maddv" }, + { MIPS_INS_MADD_Q, "madd_q" }, + { MIPS_INS_MAQ_SA, "maq_sa" }, + { MIPS_INS_MAQ_S, "maq_s" }, + { MIPS_INS_MAXA, "maxa" }, + { MIPS_INS_MAXI_S, "maxi_s" }, + { MIPS_INS_MAXI_U, "maxi_u" }, + { MIPS_INS_MAX_A, "max_a" }, + { MIPS_INS_MAX, "max" }, + { MIPS_INS_MAX_S, "max_s" }, + { MIPS_INS_MAX_U, "max_u" }, + { MIPS_INS_MFC0, "mfc0" }, + { MIPS_INS_MFC1, "mfc1" }, + { MIPS_INS_MFC2, "mfc2" }, + { MIPS_INS_MFHC1, "mfhc1" }, + { MIPS_INS_MFHI, "mfhi" }, + { MIPS_INS_MFLO, "mflo" }, + { MIPS_INS_MINA, "mina" }, + { MIPS_INS_MINI_S, "mini_s" }, + { MIPS_INS_MINI_U, "mini_u" }, + { MIPS_INS_MIN_A, "min_a" }, + { MIPS_INS_MIN, "min" }, + { MIPS_INS_MIN_S, "min_s" }, + { MIPS_INS_MIN_U, "min_u" }, + { MIPS_INS_MOD, "mod" }, + { MIPS_INS_MODSUB, "modsub" }, + { MIPS_INS_MODU, "modu" }, + { MIPS_INS_MOD_S, "mod_s" }, + { MIPS_INS_MOD_U, "mod_u" }, + { MIPS_INS_MOVE, "move" }, + { MIPS_INS_MOVEP, "movep" }, + { MIPS_INS_MOVF, "movf" }, + { MIPS_INS_MOVN, "movn" }, + { MIPS_INS_MOVT, "movt" }, + { MIPS_INS_MOVZ, "movz" }, + { MIPS_INS_MSUB, "msub" }, + { MIPS_INS_MSUBF, "msubf" }, + { MIPS_INS_MSUBR_Q, "msubr_q" }, + { MIPS_INS_MSUBU, "msubu" }, + { MIPS_INS_MSUBV, "msubv" }, + { MIPS_INS_MSUB_Q, "msub_q" }, + { MIPS_INS_MTC0, "mtc0" }, + { MIPS_INS_MTC1, "mtc1" }, + { MIPS_INS_MTC2, "mtc2" }, + { MIPS_INS_MTHC1, "mthc1" }, + { MIPS_INS_MTHI, "mthi" }, + { MIPS_INS_MTHLIP, "mthlip" }, + { MIPS_INS_MTLO, "mtlo" }, + { MIPS_INS_MTM0, "mtm0" }, + { MIPS_INS_MTM1, "mtm1" }, + { MIPS_INS_MTM2, "mtm2" }, + { MIPS_INS_MTP0, "mtp0" }, + { MIPS_INS_MTP1, "mtp1" }, + { MIPS_INS_MTP2, "mtp2" }, + { MIPS_INS_MUH, "muh" }, + { MIPS_INS_MUHU, "muhu" }, + { MIPS_INS_MULEQ_S, "muleq_s" }, + { MIPS_INS_MULEU_S, "muleu_s" }, + { MIPS_INS_MULQ_RS, "mulq_rs" }, + { MIPS_INS_MULQ_S, "mulq_s" }, + { MIPS_INS_MULR_Q, "mulr_q" }, + { MIPS_INS_MULSAQ_S, "mulsaq_s" }, + { MIPS_INS_MULSA, "mulsa" }, + { MIPS_INS_MULT, "mult" }, + { MIPS_INS_MULTU, "multu" }, + { MIPS_INS_MULU, "mulu" }, + { MIPS_INS_MULV, "mulv" }, + { MIPS_INS_MUL_Q, "mul_q" }, + { MIPS_INS_MUL_S, "mul_s" }, + { MIPS_INS_NLOC, "nloc" }, + { MIPS_INS_NLZC, "nlzc" }, + { MIPS_INS_NMADD, "nmadd" }, + { MIPS_INS_NMSUB, "nmsub" }, + { MIPS_INS_NOR, "nor" }, + { MIPS_INS_NORI, "nori" }, + { MIPS_INS_NOT16, "not16" }, + { MIPS_INS_NOT, "not" }, + { MIPS_INS_OR, "or" }, + { MIPS_INS_OR16, "or16" }, + { MIPS_INS_ORI, "ori" }, + { MIPS_INS_PACKRL, "packrl" }, + { MIPS_INS_PAUSE, "pause" }, + { MIPS_INS_PCKEV, "pckev" }, + { MIPS_INS_PCKOD, "pckod" }, + { MIPS_INS_PCNT, "pcnt" }, + { MIPS_INS_PICK, "pick" }, + { MIPS_INS_POP, "pop" }, + { MIPS_INS_PRECEQU, "precequ" }, + { MIPS_INS_PRECEQ, "preceq" }, + { MIPS_INS_PRECEU, "preceu" }, + { MIPS_INS_PRECRQU_S, "precrqu_s" }, + { MIPS_INS_PRECRQ, "precrq" }, + { MIPS_INS_PRECRQ_RS, "precrq_rs" }, + { MIPS_INS_PRECR, "precr" }, + { MIPS_INS_PRECR_SRA, "precr_sra" }, + { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, + { MIPS_INS_PREF, "pref" }, + { MIPS_INS_PREPEND, "prepend" }, + { MIPS_INS_RADDU, "raddu" }, + { MIPS_INS_RDDSP, "rddsp" }, + { MIPS_INS_RDHWR, "rdhwr" }, + { MIPS_INS_REPLV, "replv" }, + { MIPS_INS_REPL, "repl" }, + { MIPS_INS_RINT, "rint" }, + { MIPS_INS_ROTR, "rotr" }, + { MIPS_INS_ROTRV, "rotrv" }, + { MIPS_INS_ROUND, "round" }, + { MIPS_INS_SAT_S, "sat_s" }, + { MIPS_INS_SAT_U, "sat_u" }, + { MIPS_INS_SB, "sb" }, + { MIPS_INS_SB16, "sb16" }, + { MIPS_INS_SC, "sc" }, + { MIPS_INS_SCD, "scd" }, + { MIPS_INS_SD, "sd" }, + { MIPS_INS_SDBBP, "sdbbp" }, + { MIPS_INS_SDBBP16, "sdbbp16" }, + { MIPS_INS_SDC1, "sdc1" }, + { MIPS_INS_SDC2, "sdc2" }, + { MIPS_INS_SDC3, "sdc3" }, + { MIPS_INS_SDL, "sdl" }, + { MIPS_INS_SDR, "sdr" }, + { MIPS_INS_SDXC1, "sdxc1" }, + { MIPS_INS_SEB, "seb" }, + { MIPS_INS_SEH, "seh" }, + { MIPS_INS_SELEQZ, "seleqz" }, + { MIPS_INS_SELNEZ, "selnez" }, + { MIPS_INS_SEL, "sel" }, + { MIPS_INS_SEQ, "seq" }, + { MIPS_INS_SEQI, "seqi" }, + { MIPS_INS_SH, "sh" }, + { MIPS_INS_SH16, "sh16" }, + { MIPS_INS_SHF, "shf" }, + { MIPS_INS_SHILO, "shilo" }, + { MIPS_INS_SHILOV, "shilov" }, + { MIPS_INS_SHLLV, "shllv" }, + { MIPS_INS_SHLLV_S, "shllv_s" }, + { MIPS_INS_SHLL, "shll" }, + { MIPS_INS_SHLL_S, "shll_s" }, + { MIPS_INS_SHRAV, "shrav" }, + { MIPS_INS_SHRAV_R, "shrav_r" }, + { MIPS_INS_SHRA, "shra" }, + { MIPS_INS_SHRA_R, "shra_r" }, + { MIPS_INS_SHRLV, "shrlv" }, + { MIPS_INS_SHRL, "shrl" }, + { MIPS_INS_SLDI, "sldi" }, + { MIPS_INS_SLD, "sld" }, + { MIPS_INS_SLL, "sll" }, + { MIPS_INS_SLL16, "sll16" }, + { MIPS_INS_SLLI, "slli" }, + { MIPS_INS_SLLV, "sllv" }, + { MIPS_INS_SLT, "slt" }, + { MIPS_INS_SLTI, "slti" }, + { MIPS_INS_SLTIU, "sltiu" }, + { MIPS_INS_SLTU, "sltu" }, + { MIPS_INS_SNE, "sne" }, + { MIPS_INS_SNEI, "snei" }, + { MIPS_INS_SPLATI, "splati" }, + { MIPS_INS_SPLAT, "splat" }, + { MIPS_INS_SRA, "sra" }, + { MIPS_INS_SRAI, "srai" }, + { MIPS_INS_SRARI, "srari" }, + { MIPS_INS_SRAR, "srar" }, + { MIPS_INS_SRAV, "srav" }, + { MIPS_INS_SRL, "srl" }, + { MIPS_INS_SRL16, "srl16" }, + { MIPS_INS_SRLI, "srli" }, + { MIPS_INS_SRLRI, "srlri" }, + { MIPS_INS_SRLR, "srlr" }, + { MIPS_INS_SRLV, "srlv" }, + { MIPS_INS_SSNOP, "ssnop" }, + { MIPS_INS_ST, "st" }, + { MIPS_INS_SUBQH, "subqh" }, + { MIPS_INS_SUBQH_R, "subqh_r" }, + { MIPS_INS_SUBQ, "subq" }, + { MIPS_INS_SUBQ_S, "subq_s" }, + { MIPS_INS_SUBSUS_U, "subsus_u" }, + { MIPS_INS_SUBSUU_S, "subsuu_s" }, + { MIPS_INS_SUBS_S, "subs_s" }, + { MIPS_INS_SUBS_U, "subs_u" }, + { MIPS_INS_SUBU16, "subu16" }, + { MIPS_INS_SUBUH, "subuh" }, + { MIPS_INS_SUBUH_R, "subuh_r" }, + { MIPS_INS_SUBU, "subu" }, + { MIPS_INS_SUBU_S, "subu_s" }, + { MIPS_INS_SUBVI, "subvi" }, + { MIPS_INS_SUBV, "subv" }, + { MIPS_INS_SUXC1, "suxc1" }, + { MIPS_INS_SW, "sw" }, + { MIPS_INS_SW16, "sw16" }, + { MIPS_INS_SWC1, "swc1" }, + { MIPS_INS_SWC2, "swc2" }, + { MIPS_INS_SWC3, "swc3" }, + { MIPS_INS_SWL, "swl" }, + { MIPS_INS_SWM16, "swm16" }, + { MIPS_INS_SWM32, "swm32" }, + { MIPS_INS_SWP, "swp" }, + { MIPS_INS_SWR, "swr" }, + { MIPS_INS_SWXC1, "swxc1" }, + { MIPS_INS_SYNC, "sync" }, + { MIPS_INS_SYNCI, "synci" }, + { MIPS_INS_SYSCALL, "syscall" }, + { MIPS_INS_TEQ, "teq" }, + { MIPS_INS_TEQI, "teqi" }, + { MIPS_INS_TGE, "tge" }, + { MIPS_INS_TGEI, "tgei" }, + { MIPS_INS_TGEIU, "tgeiu" }, + { MIPS_INS_TGEU, "tgeu" }, + { MIPS_INS_TLBP, "tlbp" }, + { MIPS_INS_TLBR, "tlbr" }, + { MIPS_INS_TLBWI, "tlbwi" }, + { MIPS_INS_TLBWR, "tlbwr" }, + { MIPS_INS_TLT, "tlt" }, + { MIPS_INS_TLTI, "tlti" }, + { MIPS_INS_TLTIU, "tltiu" }, + { MIPS_INS_TLTU, "tltu" }, + { MIPS_INS_TNE, "tne" }, + { MIPS_INS_TNEI, "tnei" }, + { MIPS_INS_TRUNC, "trunc" }, + { MIPS_INS_V3MULU, "v3mulu" }, + { MIPS_INS_VMM0, "vmm0" }, + { MIPS_INS_VMULU, "vmulu" }, + { MIPS_INS_VSHF, "vshf" }, + { MIPS_INS_WAIT, "wait" }, + { MIPS_INS_WRDSP, "wrdsp" }, + { MIPS_INS_WSBH, "wsbh" }, + { MIPS_INS_XOR, "xor" }, + { MIPS_INS_XOR16, "xor16" }, + { MIPS_INS_XORI, "xori" }, + + // alias instructions + { MIPS_INS_NOP, "nop" }, + { MIPS_INS_NEGU, "negu" }, + + { MIPS_INS_JALR_HB, "jalr.hb" }, + { MIPS_INS_JR_HB, "jr.hb" }, +}; + +const char *Mips_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= MIPS_INS_ENDING) + return NULL; + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { MIPS_GRP_INVALID, NULL }, + { MIPS_GRP_JUMP, "jump" }, + { MIPS_GRP_CALL, "call" }, + { MIPS_GRP_RET, "ret" }, + { MIPS_GRP_INT, "int" }, + { MIPS_GRP_IRET, "iret" }, + { MIPS_GRP_PRIVILEGE, "privileged" }, + { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, + + // architecture-specific groups + { MIPS_GRP_BITCOUNT, "bitcount" }, + { MIPS_GRP_DSP, "dsp" }, + { MIPS_GRP_DSPR2, "dspr2" }, + { MIPS_GRP_FPIDX, "fpidx" }, + { MIPS_GRP_MSA, "msa" }, + { MIPS_GRP_MIPS32R2, "mips32r2" }, + { MIPS_GRP_MIPS64, "mips64" }, + { MIPS_GRP_MIPS64R2, "mips64r2" }, + { MIPS_GRP_SEINREG, "seinreg" }, + { MIPS_GRP_STDENC, "stdenc" }, + { MIPS_GRP_SWAP, "swap" }, + { MIPS_GRP_MICROMIPS, "micromips" }, + { MIPS_GRP_MIPS16MODE, "mips16mode" }, + { MIPS_GRP_FP64BIT, "fp64bit" }, + { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, + { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, + { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, + { MIPS_GRP_NOTNACL, "notnacl" }, + + { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, + { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, + { MIPS_GRP_CNMIPS, "cnmips" }, + + { MIPS_GRP_MIPS32, "mips32" }, + { MIPS_GRP_MIPS32R6, "mips32r6" }, + { MIPS_GRP_MIPS64R6, "mips64r6" }, + + { MIPS_GRP_MIPS2, "mips2" }, + { MIPS_GRP_MIPS3, "mips3" }, + { MIPS_GRP_MIPS3_32, "mips3_32"}, + { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, + + { MIPS_GRP_MIPS4_32, "mips4_32" }, + { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, + { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, + + { MIPS_GRP_GP32BIT, "gp32bit" }, + { MIPS_GRP_GP64BIT, "gp64bit" }, +}; +#endif + +const char *Mips_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map instruction name to public instruction ID +mips_reg Mips_map_insn(const char *name) +{ + // handle special alias first + unsigned int i; + + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + + return (i != -1)? i : MIPS_REG_INVALID; +} + +// map internal raw register to 'public' register +mips_reg Mips_map_register(unsigned int r) +{ + // for some reasons different Mips modes can map different register number to + // the same Mips register. this function handles the issue for exposing Mips + // operands by mapping internal registers to 'public' register. + static const unsigned int map[] = { 0, + MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, + MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, + MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, + MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, + MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, + MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, + MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, + MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, + MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, + MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, + MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, + MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, + MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, + MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, + MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, + MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, + MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, + MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, + MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, + MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, + MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, + MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, + MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, + MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, + MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, + MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, + MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, + MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, + MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, + MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, + MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, + MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, + MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, + MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, + MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, + MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, + MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, + MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, + MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, + MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, + MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, + MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, + MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, + MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, + MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, + MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, + MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, + 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, + MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, + MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, + MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, + MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, + MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, + MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, + MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, + MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, + MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, + MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, + MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, + MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, + MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, + MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, + MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, + MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, + MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, + MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, + MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, + MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, + MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, + MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, + MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, + MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, + MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, + MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, + MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, + MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, + MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, + MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, + MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsMapping.h b/white_patch_detect/capstone-master/arch/Mips/MipsMapping.h new file mode 100644 index 0000000..42b86e6 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsMapping.h @@ -0,0 +1,25 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_MIPS_MAP_H +#define CS_MIPS_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *Mips_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *Mips_insn_name(csh handle, unsigned int id); + +const char *Mips_group_name(csh handle, unsigned int id); + +// map instruction name to instruction ID +mips_reg Mips_map_insn(const char *name); + +// map internal raw register to 'public' register +mips_reg Mips_map_register(unsigned int r); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsMappingInsn.inc b/white_patch_detect/capstone-master/arch/Mips/MipsMappingInsn.inc new file mode 100644 index 0000000..beb026c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsMappingInsn.inc @@ -0,0 +1,9315 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUPC, MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQH_PH, MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQH_W, MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQ_PH, MIPS_INS_ADDQ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDSC, MIPS_INS_ADDSC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_A_B, MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_A_D, MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_A_H, MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_A_W, MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_S_B, MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_S_D, MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_S_H, MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_S_W, MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_U_B, MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_U_D, MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_U_H, MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDS_U_W, MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDU16_MM, MIPS_INS_ADDU16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDUH_QB, MIPS_INS_ADDUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDU_PH, MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDU_QB, MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDU_S_PH, MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDU_S_QB, MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDVI_B, MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDVI_D, MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDVI_H, MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDVI_W, MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDV_B, MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDV_D, MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDV_H, MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDV_W, MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDWC, MIPS_INS_ADDWC, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD_A_B, MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD_A_D, MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD_A_H, MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD_A_W, MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ADD_MM, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDi, MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDi_MM, MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDiu, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDiu_MM, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDu, MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ADDu_MM, MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ALIGN, MIPS_INS_ALIGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_ALUIPC, MIPS_INS_ALUIPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_AND, MIPS_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_AND16_MM, MIPS_INS_AND16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_AND64, MIPS_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ANDI16_MM, MIPS_INS_ANDI16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ANDI_B, MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AND_MM, MIPS_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_AND_V, MIPS_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ANDi, MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ANDi64, MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ANDi_MM, MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_APPEND, MIPS_INS_APPEND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_S_B, MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_S_D, MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_S_H, MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_S_W, MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_U_B, MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_U_D, MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_U_H, MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ASUB_U_W, MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AUI, MIPS_INS_AUI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_AUIPC, MIPS_INS_AUIPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_S_B, MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_S_D, MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_S_H, MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_S_W, MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_U_B, MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_U_D, MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_U_H, MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVER_U_W, MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_S_B, MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_S_D, MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_S_H, MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_S_W, MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_U_B, MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_U_D, MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_U_H, MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AVE_U_W, MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuRxImmX16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuSpImm16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AddiuSpImmX16, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AdduRxRyRz16, MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_AndRxRxRy16, MIPS_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_B16_MM, MIPS_INS_B16, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BADDu, MIPS_INS_BADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BAL, MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BALC, MIPS_INS_BALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BALIGN, MIPS_INS_BALIGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_BBIT0, MIPS_INS_BBIT0, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BBIT032, MIPS_INS_BBIT032, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BBIT1, MIPS_INS_BBIT1, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BBIT132, MIPS_INS_BBIT132, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BC, MIPS_INS_BC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC0F, MIPS_INS_BC0F, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC0FL, MIPS_INS_BC0FL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC0T, MIPS_INS_BC0T, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC0TL, MIPS_INS_BC0TL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1EQZ, MIPS_INS_BC1EQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1F, MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1FL, MIPS_INS_BC1FL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1F_MM, MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1NEZ, MIPS_INS_BC1NEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1T, MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1TL, MIPS_INS_BC1TL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC1T_MM, MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2EQZ, MIPS_INS_BC2EQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2F, MIPS_INS_BC2F, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2FL, MIPS_INS_BC2FL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2NEZ, MIPS_INS_BC2NEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2T, MIPS_INS_BC2T, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC2TL, MIPS_INS_BC2TL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC3F, MIPS_INS_BC3F, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC3FL, MIPS_INS_BC3FL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC3T, MIPS_INS_BC3T, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BC3TL, MIPS_INS_BC3TL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BCLRI_B, MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLRI_D, MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLRI_H, MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLRI_W, MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLR_B, MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLR_D, MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLR_H, MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BCLR_W, MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BEQ, MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQ64, MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQC, MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQL, MIPS_INS_BEQL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQZ16_MM, MIPS_INS_BEQZ16, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQZALC, MIPS_INS_BEQZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQZC, MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQZC_MM, MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BEQ_MM, MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEC, MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEUC, MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZ, MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZ64, MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZAL, MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_BGEZALC, MIPS_INS_BGEZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZALL, MIPS_INS_BGEZALL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_BGEZALS_MM, MIPS_INS_BGEZALS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BGEZAL_MM, MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BGEZC, MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZL, MIPS_INS_BGEZL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGEZ_MM, MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZ, MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZ64, MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZALC, MIPS_INS_BGTZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZC, MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZL, MIPS_INS_BGTZL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BGTZ_MM, MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BINSLI_B, MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSLI_D, MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSLI_H, MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSLI_W, MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSL_B, MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSL_D, MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSL_H, MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSL_W, MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSRI_B, MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSRI_D, MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSRI_H, MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSRI_W, MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSR_B, MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSR_D, MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSR_H, MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BINSR_W, MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BITREV, MIPS_INS_BITREV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_BITSWAP, MIPS_INS_BITSWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_BLEZ, MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BLEZ64, MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BLEZALC, MIPS_INS_BLEZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLEZC, MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLEZL, MIPS_INS_BLEZL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLEZ_MM, MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTC, MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTUC, MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZ, MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZ64, MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZAL, MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_BLTZALC, MIPS_INS_BLTZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZALL, MIPS_INS_BLTZALL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_BLTZALS_MM, MIPS_INS_BLTZALS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BLTZAL_MM, MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BLTZC, MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZL, MIPS_INS_BLTZL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BLTZ_MM, MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BMNZI_B, MIPS_INS_BMNZI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BMNZ_V, MIPS_INS_BMNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BMZI_B, MIPS_INS_BMZI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BMZ_V, MIPS_INS_BMZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNE, MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BNE64, MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEC, MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEGI_B, MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEGI_D, MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEGI_H, MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEGI_W, MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEG_B, MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEG_D, MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEG_H, MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEG_W, MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BNEL, MIPS_INS_BNEL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEZ16_MM, MIPS_INS_BNEZ16, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEZALC, MIPS_INS_BNEZALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEZC, MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BNEZC_MM, MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BNE_MM, MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 +#endif +}, +{ + Mips_BNVC, MIPS_INS_BNVC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BNZ_B, MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BNZ_D, MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BNZ_H, MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BNZ_V, MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BNZ_W, MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BOVC, MIPS_INS_BOVC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 +#endif +}, +{ + Mips_BPOSGE32, MIPS_INS_BPOSGE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0 +#endif +}, +{ + Mips_BREAK, MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_BREAK16_MM, MIPS_INS_BREAK16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BREAK_MM, MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_BSELI_B, MIPS_INS_BSELI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSEL_V, MIPS_INS_BSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSETI_B, MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSETI_D, MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSETI_H, MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSETI_W, MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSET_B, MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSET_D, MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSET_H, MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BSET_W, MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_BZ_B, MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BZ_D, MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BZ_H, MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BZ_V, MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BZ_W, MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 +#endif +}, +{ + Mips_BeqzRxImm16, MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BeqzRxImmX16, MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_Bimm16, MIPS_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BimmX16, MIPS_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BnezRxImm16, MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BnezRxImmX16, MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_Break16, MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_Bteqz16, MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BteqzX16, MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_Btnez16, MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_BtnezX16, MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 +#endif +}, +{ + Mips_CACHE, MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CACHE_MM, MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CACHE_R6, MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_L_D64, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_L_S, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_W_D32, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_W_D64, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_W_MM, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_W_S, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_CEIL_W_S_MM, MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQI_B, MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQI_D, MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQI_H, MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQI_W, MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQ_B, MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQ_D, MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQ_H, MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CEQ_W, MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CFC1, MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_CFC1_MM, MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CFCMSA, MIPS_INS_CFCMSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CINS, MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CINS32, MIPS_INS_CINS32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CLASS_D, MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CLASS_S, MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_S_B, MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_S_D, MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_S_H, MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_S_W, MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_U_B, MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_U_D, MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_U_H, MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLEI_U_W, MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_S_B, MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_S_D, MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_S_H, MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_S_W, MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_U_B, MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_U_D, MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_U_H, MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLE_U_W, MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLO, MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CLO_MM, MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CLO_R6, MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_S_B, MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_S_D, MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_S_H, MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_S_W, MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_U_B, MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_U_D, MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_U_H, MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLTI_U_W, MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_S_B, MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_S_D, MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_S_H, MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_S_W, MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_U_B, MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_U_D, MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_U_H, MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLT_U_W, MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CLZ, MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CLZ_MM, MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CLZ_R6, MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPU_EQ_QB, MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPU_LE_QB, MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMPU_LT_QB, MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_EQ_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_EQ_PH, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_EQ_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_F_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_F_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LE_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LE_PH, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LE_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LT_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LT_PH, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_LT_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SAF_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SAF_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SEQ_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SEQ_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SLE_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SLE_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SLT_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SLT_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SUEQ_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SUEQ_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SULE_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SULE_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SULT_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SULT_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SUN_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_SUN_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_UEQ_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_UEQ_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_ULE_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_ULE_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_ULT_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_ULT_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_UN_D, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CMP_UN_S, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_S_B, MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_S_D, MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_S_H, MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_S_W, MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_U_B, MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_U_D, MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_U_H, MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_COPY_U_W, MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CTC1, MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_CTC1_MM, MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CTCMSA, MIPS_INS_CTCMSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D32_S, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D32_W, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D32_W_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D64_L, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D64_S, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D64_W, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_D_S_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_L_D64, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_L_D64_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_L_S, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_L_S_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_D32, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_D32_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_D64, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_L, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_W, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_S_W_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_W_D32, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_W_D64, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_W_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_W_S, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_CVT_W_S_MM, MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_C_EQ_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_EQ_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_EQ_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_F_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_F_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_F_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LE_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LE_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LE_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LT_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LT_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_LT_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGE_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGE_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGE_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGLE_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGLE_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGLE_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGL_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGL_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGL_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGT_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGT_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_NGT_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLE_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLE_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLE_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLT_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLT_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_OLT_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SEQ_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SEQ_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SEQ_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SF_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SF_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_SF_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UEQ_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UEQ_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UEQ_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULE_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULE_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULE_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULT_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULT_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_ULT_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UN_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UN_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_C_UN_S, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_CmpRxRy16, MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_CmpiRxImm16, MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_CmpiRxImmX16, MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_DADD, MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DADDi, MIPS_INS_DADDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DADDiu, MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DADDu, MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DAHI, MIPS_INS_DAHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DALIGN, MIPS_INS_DALIGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DATI, MIPS_INS_DATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DAUI, MIPS_INS_DAUI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DBITSWAP, MIPS_INS_DBITSWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DCLO, MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DCLO_R6, MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DCLZ, MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DCLZ_R6, MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DDIV, MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DDIVU, MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DERET, MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 +#endif +}, +{ + Mips_DERET_MM, MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_DEXT, MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DEXTM, MIPS_INS_DEXTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DEXTU, MIPS_INS_DEXTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DI, MIPS_INS_DI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DINS, MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DINSM, MIPS_INS_DINSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DINSU, MIPS_INS_DINSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DIVU, MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_S_B, MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_S_D, MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_S_H, MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_S_W, MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_U_B, MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_U_D, MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_U_H, MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DIV_U_W, MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DI_MM, MIPS_INS_DI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_DLSA, MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_DLSA_R6, MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMFC0, MIPS_INS_DMFC0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_DMFC1, MIPS_INS_DMFC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DMFC2, MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_DMOD, MIPS_INS_DMOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMODU, MIPS_INS_DMODU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMTC0, MIPS_INS_DMTC0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_DMTC1, MIPS_INS_DMTC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DMTC2, MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_DMUH, MIPS_INS_DMUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMUHU, MIPS_INS_DMUHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMUL, MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_DMULT, MIPS_INS_DMULT, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMULTu, MIPS_INS_DMULTU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMULU, MIPS_INS_DMULU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DMUL_R6, MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_S_D, MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_S_H, MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_S_W, MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_U_D, MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_U_H, MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DOTP_U_W, MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_S_D, MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_S_H, MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_S_W, MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_U_D, MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_U_H, MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPADD_U_W, MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAU_H_QBL, MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAU_H_QBR, MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPAX_W_PH, MIPS_INS_DPAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPA_W_PH, MIPS_INS_DPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPOP, MIPS_INS_DPOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSU_H_QBL, MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSU_H_QBR, MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_DPSX_W_PH, MIPS_INS_DPSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DPS_W_PH, MIPS_INS_DPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_DROTR, MIPS_INS_DROTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DROTR32, MIPS_INS_DROTR32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DROTRV, MIPS_INS_DROTRV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DSBH, MIPS_INS_DSBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DSDIV, MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DSHD, MIPS_INS_DSHD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 +#endif +}, +{ + Mips_DSLL, MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSLL32, MIPS_INS_DSLL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSLL64_32, MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_DSLLV, MIPS_INS_DSLLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRA, MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRA32, MIPS_INS_DSRA32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRAV, MIPS_INS_DSRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRL, MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRL32, MIPS_INS_DSRL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSRLV, MIPS_INS_DSRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSUB, MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DSUBu, MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_DUDIV, MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_DivRxRy16, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_DivuRxRy16, MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_EHB, MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_EHB_MM, MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_EI, MIPS_INS_EI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_EI_MM, MIPS_INS_EI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ERET, MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 +#endif +}, +{ + Mips_ERET_MM, MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_EXT, MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTP, MIPS_INS_EXTP, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTPDP, MIPS_INS_EXTPDP, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTPDPV, MIPS_INS_EXTPDPV, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTPV, MIPS_INS_EXTPV, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTRV_W, MIPS_INS_EXTRV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTR_R_W, MIPS_INS_EXTR_R, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTR_S_H, MIPS_INS_EXTR_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTR_W, MIPS_INS_EXTR, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTS, MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_EXTS32, MIPS_INS_EXTS32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_EXT_MM, MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FABS_D32, MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FABS_D64, MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FABS_MM, MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FABS_S, MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FABS_S_MM, MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_D, MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_D32, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_D64, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_MM, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_S, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_S_MM, MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FADD_W, MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCAF_D, MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCAF_W, MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCEQ_D, MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCEQ_W, MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLASS_D, MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLASS_W, MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLE_D, MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLE_W, MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLT_D, MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCLT_W, MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCMP_D32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FCMP_D32_MM, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FCMP_D64, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FCMP_S32, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_FCMP_S32_MM, MIPS_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FCNE_D, MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCNE_W, MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCOR_D, MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCOR_W, MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUEQ_D, MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUEQ_W, MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCULE_D, MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCULE_W, MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCULT_D, MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCULT_W, MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUNE_D, MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUNE_W, MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUN_D, MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FCUN_W, MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_D, MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_D32, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_D64, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_MM, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_S, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_S_MM, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FDIV_W, MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXDO_H, MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXDO_W, MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXP2_D, MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXP2_W, MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXUPL_D, MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXUPL_W, MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXUPR_D, MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FEXUPR_W, MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFINT_S_D, MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFINT_S_W, MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFINT_U_D, MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFINT_U_W, MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFQL_D, MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFQL_W, MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFQR_D, MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FFQR_W, MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FILL_B, MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FILL_D, MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_FILL_H, MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FILL_W, MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOG2_D, MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOG2_W, MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_L_D64, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_L_S, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_W_D32, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_W_D64, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_W_MM, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_W_S, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FMADD_D, MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMADD_W, MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMAX_A_D, MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMAX_A_W, MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMAX_D, MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMAX_W, MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMIN_A_D, MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMIN_A_W, MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMIN_D, MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMIN_W, MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMOV_D32, MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FMOV_D32_MM, MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FMOV_D64, MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FMOV_S, MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FMOV_S_MM, MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FMSUB_D, MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMSUB_W, MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_D, MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_D32, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_D64, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_MM, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_S, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_S_MM, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FMUL_W, MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FNEG_D32, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FNEG_D64, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FNEG_MM, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FNEG_S, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FNEG_S_MM, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FRCP_D, MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FRCP_W, MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FRINT_D, MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FRINT_W, MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FRSQRT_D, MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FRSQRT_W, MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSAF_D, MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSAF_W, MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSEQ_D, MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSEQ_W, MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSLE_D, MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSLE_W, MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSLT_D, MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSLT_W, MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSNE_D, MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSNE_W, MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSOR_D, MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSOR_W, MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_D, MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_D32, MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_D64, MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_MM, MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_S, MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_S_MM, MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FSQRT_W, MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_D, MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_D32, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_D64, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_MM, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_S, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_S_MM, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUB_W, MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUEQ_D, MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUEQ_W, MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSULE_D, MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSULE_W, MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSULT_D, MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSULT_W, MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUNE_D, MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUNE_W, MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUN_D, MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FSUN_W, MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTINT_S_D, MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTINT_S_W, MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTINT_U_D, MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTINT_U_W, MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTQ_H, MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTQ_W, MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_S_D, MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_S_H, MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_S_W, MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_U_D, MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_U_H, MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HADD_U_W, MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_S_D, MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_S_H, MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_S_W, MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_U_D, MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_U_H, MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_HSUB_U_W, MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVEV_B, MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVEV_D, MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVEV_H, MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVEV_W, MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVL_B, MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVL_D, MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVL_H, MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVL_W, MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVOD_B, MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVOD_D, MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVOD_H, MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVOD_W, MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVR_B, MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVR_D, MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVR_H, MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ILVR_W, MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INS, MIPS_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_INSERT_B, MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSERT_D, MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_INSERT_H, MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSERT_W, MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSV, MIPS_INS_INSV, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_INSVE_B, MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSVE_D, MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSVE_H, MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INSVE_W, MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_INS_MM, MIPS_INS_INS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_J, MIPS_INS_J, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 +#endif +}, +{ + Mips_JAL, MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_JALR, MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALR16_MM, MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALR64, MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALRS16_MM, MIPS_INS_JALRS16, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALRS_MM, MIPS_INS_JALRS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALR_HB, MIPS_INS_JALR_HB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1 +#endif +}, +{ + Mips_JALR_MM, MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_JALS_MM, MIPS_INS_JALS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_JALX, MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_JALX_MM, MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_JAL_MM, MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_JIALC, MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_JIC, MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_JR, MIPS_INS_JR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 +#endif +}, +{ + Mips_JR16_MM, MIPS_INS_JR16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 +#endif +}, +{ + Mips_JR64, MIPS_INS_JR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 +#endif +}, +{ + Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 +#endif +}, +{ + Mips_JRC16_MM, MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 +#endif +}, +{ + Mips_JR_HB, MIPS_INS_JR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 +#endif +}, +{ + Mips_JR_HB_R6, MIPS_INS_JR_HB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 +#endif +}, +{ + Mips_JR_MM, MIPS_INS_JR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 +#endif +}, +{ + Mips_J_MM, MIPS_INS_J, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_Jal16, MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_JrRa16, MIPS_INS_JR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 +#endif +}, +{ + Mips_JrcRa16, MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 +#endif +}, +{ + Mips_JrcRx16, MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 +#endif +}, +{ + Mips_JumpLinkReg16, MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0 +#endif +}, +{ + Mips_LB, MIPS_INS_LB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LB64, MIPS_INS_LB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LBU16_MM, MIPS_INS_LBU16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LBUX, MIPS_INS_LBUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_LB_MM, MIPS_INS_LB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LBu, MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LBu64, MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LBu_MM, MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LD, MIPS_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC1, MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC164, MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC1_MM, MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC2, MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC2_R6, MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LDC3, MIPS_INS_LDC3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LDI_B, MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LDI_D, MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LDI_H, MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LDI_W, MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LDL, MIPS_INS_LDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LDPC, MIPS_INS_LDPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LDR, MIPS_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LDXC1, MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_LDXC164, MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LD_B, MIPS_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LD_D, MIPS_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LD_H, MIPS_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LD_W, MIPS_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LEA_ADDiu, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LEA_ADDiu64, MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LH, MIPS_INS_LH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LH64, MIPS_INS_LH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LHU16_MM, MIPS_INS_LHU16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LHX, MIPS_INS_LHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_LH_MM, MIPS_INS_LH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LHu, MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LHu64, MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LHu_MM, MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LI16_MM, MIPS_INS_LI16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LL, MIPS_INS_LL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LLD, MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LLD_R6, MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LL_MM, MIPS_INS_LL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LL_R6, MIPS_INS_LL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LSA, MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_LSA_R6, MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LUXC1, MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_LUXC164, MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LUXC1_MM, MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LUi, MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LUi64, MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LUi_MM, MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LW, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LW16_MM, MIPS_INS_LW16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LW64, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LWC1, MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LWC1_MM, MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWC2, MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWC2_R6, MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LWC3, MIPS_INS_LWC3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWGP_MM, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWL, MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWL64, MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LWL_MM, MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWM16_MM, MIPS_INS_LWM16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWM32_MM, MIPS_INS_LWM32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWPC, MIPS_INS_LWPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LWP_MM, MIPS_INS_LWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWR, MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWR64, MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_LWR_MM, MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWSP_MM, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWUPC, MIPS_INS_LWUPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_LWU_MM, MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWX, MIPS_INS_LWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_LWXC1, MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_LWXC1_MM, MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWXS_MM, MIPS_INS_LWXS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LW_MM, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_LWu, MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_LbRxRyOffMemX16, MIPS_INS_LB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LhRxRyOffMemX16, MIPS_INS_LH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LiRxImm16, MIPS_INS_LI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LiRxImmX16, MIPS_INS_LI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LwRxPcTcp16, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LwRxPcTcpX16, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LwRxRyOffMemX16, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_LwRxSpImmX16, MIPS_INS_LW, +#ifndef CAPSTONE_DIET + { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDF_D, MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDF_S, MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDU, MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDU_DSP, MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDU_MM, MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDV_B, MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDV_D, MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDV_H, MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADDV_W, MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_D32, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_D32_MM, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_D64, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_DSP, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_MM, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_Q_H, MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_Q_W, MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_S, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MADD_S_MM, MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXA_D, MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXA_S, MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_S_B, MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_S_D, MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_S_H, MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_S_W, MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_U_B, MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_U_D, MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_U_H, MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAXI_U_W, MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_A_B, MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_A_D, MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_A_H, MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_A_W, MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_D, MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_S, MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_S_B, MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_S_D, MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_S_H, MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_S_W, MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_U_B, MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_U_D, MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_U_H, MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MAX_U_W, MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MFC0, MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 +#endif +}, +{ + Mips_MFC1, MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_MFC1_MM, MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFC2, MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHC1_D32, MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHC1_D64, MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHC1_MM, MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHI, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHI16_MM, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHI64, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHI_DSP, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MFHI_MM, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFLO, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFLO16_MM, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MFLO64, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MFLO_DSP, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MFLO_MM, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MINA_D, MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MINA_S, MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_S_B, MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_S_D, MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_S_H, MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_S_W, MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_U_B, MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_U_D, MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_U_H, MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MINI_U_W, MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_A_B, MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_A_D, MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_A_H, MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_A_W, MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_D, MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_S, MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_S_B, MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_S_D, MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_S_H, MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_S_W, MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_U_B, MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_U_D, MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_U_H, MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MIN_U_W, MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD, MIPS_INS_MOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MODSUB, MIPS_INS_MODSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MODU, MIPS_INS_MODU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_S_B, MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_S_D, MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_S_H, MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_S_W, MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_U_B, MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_U_D, MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_U_H, MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOD_U_W, MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVE16_MM, MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVEP_MM, MIPS_INS_MOVEP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVE_V, MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_D32, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_D32_MM, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_D64, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_I, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_I64, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_I_MM, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_S, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVF_S_MM, MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I64_D64, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I64_I, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I64_I64, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I64_S, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_D32, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_D64, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_I, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_I64, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_MM, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_S, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVN_I_S_MM, MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_D32, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_D32_MM, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_D64, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_I, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_I64, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_I_MM, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_S, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVT_S_MM, MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I64_I, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I64_S, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_D32, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_D64, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_I, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_I64, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_MM, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_S, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBF_D, MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBF_S, MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBU, MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBU_DSP, MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBU_MM, MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBV_B, MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBV_D, MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBV_H, MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUBV_W, MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_D32, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_D32_MM, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_D64, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_DSP, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_MM, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_S, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MSUB_S_MM, MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTC0, MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 +#endif +}, +{ + Mips_MTC1, MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_MTC1_MM, MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTC2, MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHC1_D32, MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHC1_D64, MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHC1_MM, MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHI, MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHI64, MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHI_DSP, MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHI_MM, MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTHLIP, MIPS_INS_MTHLIP, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MTLO, MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MTLO64, MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MTLO_DSP, MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MTLO_MM, MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTM0, MIPS_INS_MTM0, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTM1, MIPS_INS_MTM1, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTM2, MIPS_INS_MTM2, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTP0, MIPS_INS_MTP0, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTP1, MIPS_INS_MTP1, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MTP2, MIPS_INS_MTP2, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MUH, MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MUHU, MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_MULQ_S_PH, MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_MULQ_S_W, MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_MULR_Q_H, MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MULR_Q_W, MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULSA_W_PH, MIPS_INS_MULSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_MULT, MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MULTU_DSP, MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULT_DSP, MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_MULT_MM, MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MULTu, MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MULTu_MM, MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MULU, MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MULV_B, MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MULV_D, MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MULV_H, MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MULV_W, MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_MM, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_PH, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_Q_H, MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_Q_W, MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_R6, MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_MUL_S_PH, MIPS_INS_MUL_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_Mfhi16, MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_Mflo16, MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_Move32R16, MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_MoveR3216, MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_NLOC_B, MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLOC_D, MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLOC_H, MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLOC_W, MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLZC_B, MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLZC_D, MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLZC_H, MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NLZC_W, MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NMADD_D32, MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMADD_D32_MM, MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NMADD_D64, MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMADD_S, MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMADD_S_MM, MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NMSUB_D32, MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NMSUB_D64, MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMSUB_S, MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 +#endif +}, +{ + Mips_NMSUB_S_MM, MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NOR, MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_NOR64, MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_NORI_B, MIPS_INS_NORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NOR_MM, MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NOR_V, MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_NOT16_MM, MIPS_INS_NOT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_NegRxRy16, MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_NotRxRy16, MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_OR, MIPS_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_OR16_MM, MIPS_INS_OR16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_OR64, MIPS_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ORI_B, MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_OR_MM, MIPS_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_OR_V, MIPS_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ORi, MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ORi64, MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_ORi_MM, MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_OrRxRxRy16, MIPS_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_PACKRL_PH, MIPS_INS_PACKRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PAUSE, MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_PAUSE_MM, MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKEV_B, MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKEV_D, MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKEV_H, MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKEV_W, MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKOD_B, MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKOD_D, MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKOD_H, MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCKOD_W, MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCNT_B, MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCNT_D, MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCNT_H, MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PCNT_W, MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_PICK_PH, MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PICK_QB, MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_POP, MIPS_INS_POP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECR_QB_PH, MIPS_INS_PRECR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_PREF, MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_PREF_MM, MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_PREF_R6, MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_PREPEND, MIPS_INS_PREPEND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_RADDU_W_QB, MIPS_INS_RADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_RDDSP, MIPS_INS_RDDSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_RDHWR, MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_RDHWR64, MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_RDHWR_MM, MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_REPLV_PH, MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_REPLV_QB, MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_REPL_PH, MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_REPL_QB, MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_RINT_D, MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_RINT_S, MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_ROTR, MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_ROTRV, MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_ROTRV_MM, MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ROTR_MM, MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_L_D64, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_L_S, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_W_D32, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_W_D64, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_W_MM, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_W_S, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_ROUND_W_S_MM, MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_S_B, MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_S_D, MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_S_H, MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_S_W, MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_U_B, MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_U_D, MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_U_H, MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SAT_U_W, MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SB, MIPS_INS_SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SB16_MM, MIPS_INS_SB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SB64, MIPS_INS_SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SB_MM, MIPS_INS_SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SC, MIPS_INS_SC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SCD, MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SCD_R6, MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SC_MM, MIPS_INS_SC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SC_R6, MIPS_INS_SC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SD, MIPS_INS_SD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 +#endif +}, +{ + Mips_SDBBP, MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDBBP16_MM, MIPS_INS_SDBBP16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDBBP_MM, MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDBBP_R6, MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC1, MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC164, MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC1_MM, MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC2, MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC2_R6, MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDC3, MIPS_INS_SDC3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDIV, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDIV_MM, MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SDL, MIPS_INS_SDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDR, MIPS_INS_SDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SDXC1, MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_SDXC164, MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SEB, MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_SEB64, MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_SEB_MM, MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SEH, MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_SEH64, MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_SEH_MM, MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SELEQZ, MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELEQZ64, MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELEQZ_D, MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELEQZ_S, MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELNEZ, MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELNEZ64, MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELNEZ_D, MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SELNEZ_S, MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SEL_D, MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SEL_S, MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SEQ, MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SEQi, MIPS_INS_SEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SH, MIPS_INS_SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SH16_MM, MIPS_INS_SH16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SH64, MIPS_INS_SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SHF_B, MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SHF_H, MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SHF_W, MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SHILO, MIPS_INS_SHILO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHILOV, MIPS_INS_SHILOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLLV_PH, MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLLV_QB, MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLL_PH, MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLL_QB, MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLL_S_PH, MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHLL_S_W, MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRAV_PH, MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRAV_QB, MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRA_PH, MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRA_QB, MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRA_R_PH, MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRA_R_QB, MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRA_R_W, MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRLV_PH, MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRLV_QB, MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRL_PH, MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SHRL_QB, MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SH_MM, MIPS_INS_SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLDI_B, MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLDI_D, MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLDI_H, MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLDI_W, MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLD_B, MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLD_D, MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLD_H, MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLD_W, MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL16_MM, MIPS_INS_SLL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL64_32, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL64_64, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLI_B, MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLI_D, MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLI_H, MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLI_W, MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLV, MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLLV_MM, MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL_B, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL_D, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL_H, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL_MM, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLL_W, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SLT, MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLT64, MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLT_MM, MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTi, MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTi64, MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTi_MM, MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTiu, MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTiu64, MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTiu_MM, MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTu, MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTu64, MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SLTu_MM, MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SNE, MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SNEi, MIPS_INS_SNEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLATI_B, MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLATI_D, MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLATI_H, MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLATI_W, MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLAT_B, MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLAT_D, MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLAT_H, MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SPLAT_W, MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAI_B, MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAI_D, MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAI_H, MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAI_W, MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRARI_B, MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRARI_D, MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRARI_H, MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRARI_W, MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAR_B, MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAR_D, MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAR_H, MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAR_W, MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAV, MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SRAV_MM, MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA_B, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA_D, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA_H, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA_MM, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRA_W, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL16_MM, MIPS_INS_SRL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLI_B, MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLI_D, MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLI_H, MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLI_W, MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLRI_B, MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLRI_D, MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLRI_H, MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLRI_W, MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLR_B, MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLR_D, MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLR_H, MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLR_W, MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLV, MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SRLV_MM, MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL_B, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL_D, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL_H, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL_MM, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SRL_W, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SSNOP, MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SSNOP_MM, MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_ST_B, MIPS_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ST_D, MIPS_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ST_H, MIPS_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_ST_W, MIPS_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUB, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQH_PH, MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQH_W, MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQ_PH, MIPS_INS_SUBQ, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_S_B, MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_S_D, MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_S_H, MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_S_W, MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_U_B, MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_U_D, MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_U_H, MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBS_U_W, MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBU16_MM, MIPS_INS_SUBU16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBUH_QB, MIPS_INS_SUBUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBU_PH, MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBU_QB, MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBU_S_PH, MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBU_S_QB, MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBVI_B, MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBVI_D, MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBVI_H, MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBVI_W, MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBV_B, MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBV_D, MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBV_H, MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBV_W, MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_SUB_MM, MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBu, MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SUBu_MM, MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SUXC1, MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_SUXC164, MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SUXC1_MM, MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SW, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SW16_MM, MIPS_INS_SW16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SW64, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SWC1, MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SWC1_MM, MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWC2, MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWC2_R6, MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 +#endif +}, +{ + Mips_SWC3, MIPS_INS_SWC3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWL, MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWL64, MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SWL_MM, MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWM16_MM, MIPS_INS_SWM16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWM32_MM, MIPS_INS_SWM32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWP_MM, MIPS_INS_SWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWR, MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWR64, MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_SWR_MM, MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWSP_MM, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SWXC1, MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 +#endif +}, +{ + Mips_SWXC1_MM, MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SW_MM, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SYNC, MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 +#endif +}, +{ + Mips_SYNCI, MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_SYNC_MM, MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_SYSCALL, MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0 +#endif +}, +{ + Mips_SYSCALL_MM, MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0 +#endif +}, +{ + Mips_SbRxRyOffMemX16, MIPS_INS_SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SebRx16, MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SehRx16, MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_ShRxRyOffMemX16, MIPS_INS_SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SllX16, MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SllvRxRy16, MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltRxRy16, MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltiRxImm16, MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltiRxImmX16, MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltiuRxImm16, MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltiuRxImmX16, MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SltuRxRy16, MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SraX16, MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SravRxRy16, MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SrlX16, MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SrlvRxRy16, MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SubuRxRyRz16, MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SwRxRyOffMemX16, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_SwRxSpImmX16, MIPS_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, +{ + Mips_TEQ, MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TEQI, MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_TEQI_MM, MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TEQ_MM, MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TGE, MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEI, MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEIU, MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEIU_MM, MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEI_MM, MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEU, MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TGEU_MM, MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TGE_MM, MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBP, MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBP_MM, MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBR, MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBR_MM, MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBWI, MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBWI_MM, MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBWR, MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_TLBWR_MM, MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLT, MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TLTI, MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_TLTIU_MM, MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLTI_MM, MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLTU, MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TLTU_MM, MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TLT_MM, MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TNE, MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TNEI, MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_TNEI_MM, MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TNE_MM, MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_L_D64, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_L_S, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_W_D32, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_W_D64, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_W_MM, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_W_S, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 +#endif +}, +{ + Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_TTLTIU, MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_UDIV, MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 +#endif +}, +{ + Mips_UDIV_MM, MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_V3MULU, MIPS_INS_V3MULU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_VMM0, MIPS_INS_VMM0, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_VMULU, MIPS_INS_VMULU, +#ifndef CAPSTONE_DIET + { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_VSHF_B, MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_VSHF_D, MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_VSHF_H, MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_VSHF_W, MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_WAIT, MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_WAIT_MM, MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_WRDSP, MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 +#endif +}, +{ + Mips_WSBH, MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 +#endif +}, +{ + Mips_WSBH_MM, MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_XOR, MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_XOR16_MM, MIPS_INS_XOR16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_XOR64, MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_XORI_B, MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_XOR_MM, MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_XOR_V, MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 +#endif +}, +{ + Mips_XORi, MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_XORi64, MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 +#endif +}, +{ + Mips_XORi_MM, MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 +#endif +}, +{ + Mips_XorRxRxRy16, MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsModule.c b/white_patch_detect/capstone-master/arch/Mips/MipsModule.c new file mode 100644 index 0000000..2bafcb5 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsModule.c @@ -0,0 +1,51 @@ +/* Capstone Disassembly Engine */ +/* By Dang Hoang Vu 2013 */ + +#ifdef CAPSTONE_HAS_MIPS + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "MipsDisassembler.h" +#include "MipsInstPrinter.h" +#include "MipsMapping.h" +#include "MipsModule.h" + +// Returns mode value with implied bits set +static cs_mode updated_mode(cs_mode mode) +{ + if (mode & CS_MODE_MIPS32R6) { + mode |= CS_MODE_32; + } + + return mode; +} + +cs_err Mips_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + Mips_init(mri); + ud->printer = Mips_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->reg_name = Mips_reg_name; + ud->insn_id = Mips_get_insn_id; + ud->insn_name = Mips_insn_name; + ud->group_name = Mips_group_name; + + ud->disasm = Mips_getInstruction; + + return CS_ERR_OK; +} + +cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_MODE) { + handle->mode = updated_mode(value); + } + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Mips/MipsModule.h b/white_patch_detect/capstone-master/arch/Mips/MipsModule.h new file mode 100644 index 0000000..d1aa2cf --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Mips/MipsModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_MIPS_MODULE_H +#define CS_MIPS_MODULE_H + +#include "../../utils.h" + +cs_err Mips_global_init(cs_struct *ud); +cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.c b/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.c new file mode 100644 index 0000000..e4a7aa0 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.c @@ -0,0 +1,444 @@ +//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_POWERPC + +#include // DEBUG +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "PPCDisassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" + + +// FIXME: These can be generated by TableGen from the existing register +// encoding values! + +static const unsigned CRRegs[] = { + PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3, + PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7 +}; + +static const unsigned CRBITRegs[] = { + PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, + PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, + PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, + PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, + PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, + PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, + PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, + PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN +}; + +static const unsigned FRegs[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, + PPC_F4, PPC_F5, PPC_F6, PPC_F7, + PPC_F8, PPC_F9, PPC_F10, PPC_F11, + PPC_F12, PPC_F13, PPC_F14, PPC_F15, + PPC_F16, PPC_F17, PPC_F18, PPC_F19, + PPC_F20, PPC_F21, PPC_F22, PPC_F23, + PPC_F24, PPC_F25, PPC_F26, PPC_F27, + PPC_F28, PPC_F29, PPC_F30, PPC_F31 +}; + +static const unsigned VRegs[] = { + PPC_V0, PPC_V1, PPC_V2, PPC_V3, + PPC_V4, PPC_V5, PPC_V6, PPC_V7, + PPC_V8, PPC_V9, PPC_V10, PPC_V11, + PPC_V12, PPC_V13, PPC_V14, PPC_V15, + PPC_V16, PPC_V17, PPC_V18, PPC_V19, + PPC_V20, PPC_V21, PPC_V22, PPC_V23, + PPC_V24, PPC_V25, PPC_V26, PPC_V27, + PPC_V28, PPC_V29, PPC_V30, PPC_V31 +}; + +static const unsigned VSRegs[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, + PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, + PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, + PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15, + PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19, + PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23, + PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27, + PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31, + + PPC_VSH0, PPC_VSH1, PPC_VSH2, PPC_VSH3, + PPC_VSH4, PPC_VSH5, PPC_VSH6, PPC_VSH7, + PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, + PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, + PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, + PPC_VSH20, PPC_VSH21, PPC_VSH22, PPC_VSH23, + PPC_VSH24, PPC_VSH25, PPC_VSH26, PPC_VSH27, + PPC_VSH28, PPC_VSH29, PPC_VSH30, PPC_VSH31 +}; + +static const unsigned VSFRegs[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, + PPC_F4, PPC_F5, PPC_F6, PPC_F7, + PPC_F8, PPC_F9, PPC_F10, PPC_F11, + PPC_F12, PPC_F13, PPC_F14, PPC_F15, + PPC_F16, PPC_F17, PPC_F18, PPC_F19, + PPC_F20, PPC_F21, PPC_F22, PPC_F23, + PPC_F24, PPC_F25, PPC_F26, PPC_F27, + PPC_F28, PPC_F29, PPC_F30, PPC_F31, + + PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, + PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, + PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, + PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, + PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, + PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, + PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, + PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 +}; + +static const unsigned GPRegs[] = { + PPC_R0, PPC_R1, PPC_R2, PPC_R3, + PPC_R4, PPC_R5, PPC_R6, PPC_R7, + PPC_R8, PPC_R9, PPC_R10, PPC_R11, + PPC_R12, PPC_R13, PPC_R14, PPC_R15, + PPC_R16, PPC_R17, PPC_R18, PPC_R19, + PPC_R20, PPC_R21, PPC_R22, PPC_R23, + PPC_R24, PPC_R25, PPC_R26, PPC_R27, + PPC_R28, PPC_R29, PPC_R30, PPC_R31 +}; + +static const unsigned GP0Regs[] = { + PPC_ZERO, PPC_R1, PPC_R2, PPC_R3, + PPC_R4, PPC_R5, PPC_R6, PPC_R7, + PPC_R8, PPC_R9, PPC_R10, PPC_R11, + PPC_R12, PPC_R13, PPC_R14, PPC_R15, + PPC_R16, PPC_R17, PPC_R18, PPC_R19, + PPC_R20, PPC_R21, PPC_R22, PPC_R23, + PPC_R24, PPC_R25, PPC_R26, PPC_R27, + PPC_R28, PPC_R29, PPC_R30, PPC_R31 +}; + +static const unsigned G8Regs[] = { + PPC_X0, PPC_X1, PPC_X2, PPC_X3, + PPC_X4, PPC_X5, PPC_X6, PPC_X7, + PPC_X8, PPC_X9, PPC_X10, PPC_X11, + PPC_X12, PPC_X13, PPC_X14, PPC_X15, + PPC_X16, PPC_X17, PPC_X18, PPC_X19, + PPC_X20, PPC_X21, PPC_X22, PPC_X23, + PPC_X24, PPC_X25, PPC_X26, PPC_X27, + PPC_X28, PPC_X29, PPC_X30, PPC_X31 +}; + +static const unsigned QFRegs[] = { + PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, + PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, + PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, + PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15, + PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, + PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23, + PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27, + PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31 +}; + +static uint64_t getFeatureBits(int feature) +{ + // enable all features + return (uint64_t)-1; +} + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, + const unsigned *Regs, size_t RegsLen) +{ + if (RegNo >= RegsLen / sizeof(unsigned)) { + return MCDisassembler_Fail; + } + MCOperand_CreateReg0(Inst, Regs[RegNo]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs)); +} + +static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, CRBITRegs, sizeof(CRBITRegs)); +} + +static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); +} + +static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); +} + +static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, VRegs, sizeof(VRegs)); +} + +static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, VSRegs, sizeof(VSRegs)); +} + +static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, VSFRegs, sizeof(VSFRegs)); +} + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs)); +} + +static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, GP0Regs, sizeof(GP0Regs)); +} + +static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, G8Regs, sizeof(G8Regs)); +} + +#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass +#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass + +static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, QFRegs, sizeof(QFRegs)); +} + +#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass +#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, unsigned N) +{ + //assert(isUInt(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, unsigned N) +{ + // assert(isUInt(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); + return MCDisassembler_Success; +} + + +#define GET_INSTRINFO_ENUM +#include "PPCGenInstrInfo.inc" + +static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + // Decode the memri field (imm, reg), which has the low 16-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 16; + uint64_t Disp = Imm & 0xFFFF; + + // assert(Base < 32 && "Invalid base register"); + if (Base >= 32) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + default: break; + case PPC_LBZU: + case PPC_LHAU: + case PPC_LHZU: + case PPC_LWZU: + case PPC_LFSU: + case PPC_LFDU: + // Add the tied output operand. + MCOperand_CreateReg0(Inst, GP0Regs[Base]); + break; + case PPC_STBU: + case PPC_STHU: + case PPC_STWU: + case PPC_STFSU: + case PPC_STFDU: + MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); + break; + } + + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16)); + MCOperand_CreateReg0(Inst, GP0Regs[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + // Decode the memrix field (imm, reg), which has the low 14-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 14; + uint64_t Disp = Imm & 0x3FFF; + + // assert(Base < 32 && "Invalid base register"); + + if (MCInst_getOpcode(Inst) == PPC_LDU) + // Add the tied output operand. + MCOperand_CreateReg0(Inst, GP0Regs[Base]); + else if (MCInst_getOpcode(Inst) == PPC_STDU) + MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); + + MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16)); + MCOperand_CreateReg0(Inst, GP0Regs[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) +{ + // The cr bit encoding is 0x80 >> cr_reg_num. + + unsigned Zeros = CountTrailingZeros_64(Imm); + // assert(Zeros < 8 && "Invalid CR bit value"); + if (Zeros >=8) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); + return MCDisassembler_Success; +} + +#include "PPCGenDisassemblerTables.inc" + +static DecodeStatus getInstruction(MCInst *MI, + const uint8_t *code, size_t code_len, + uint16_t *Size, + uint64_t Address, MCRegisterInfo *MRI) +{ + uint32_t insn; + DecodeStatus result; + // Get the four bytes of the instruction. + if (code_len < 4) { + // not enough data + *Size = 0; + return MCDisassembler_Fail; + } + + // The instruction is big-endian encoded. + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + insn = ((uint32_t) code[0] << 24) | (code[1] << 16) | + (code[2] << 8) | (code[3] << 0); + else + insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | + (code[1] << 8) | (code[0] << 0); + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc)+sizeof(cs_ppc)); + } + + if (MI->csh->mode & CS_MODE_QPX) { + result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address, 4); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + } + + result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + // report error + MCInst_clear(MI); + *Size = 0; + return MCDisassembler_Fail; +} + +bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info) +{ + DecodeStatus status = getInstruction(instr, + code, code_len, + size, + address, (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +#define GET_REGINFO_MC_DESC +#include "PPCGenRegisterInfo.inc" +void PPC_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(PPCRegDesc, 310, RA, PC, + PPCMCRegisterClasses, 23, + PPCRegUnitRoots, + 138, + PPCRegDiffLists, + PPCLaneMaskLists, + PPCRegStrings, + PPCRegClassStrings, + PPCSubRegIdxLists, + 8, + PPCSubRegIdxRanges, + PPCRegEncodingTable); + */ + + + MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 310, + 0, 0, + PPCMCRegisterClasses, 23, + 0, 0, + PPCRegDiffLists, + 0, + PPCSubRegIdxLists, 8, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.h b/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.h new file mode 100644 index 0000000..5ffab28 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCDisassembler.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_PPCDISASSEMBLER_H +#define CS_PPCDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void PPC_init(MCRegisterInfo *MRI); + +bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenAsmWriter.inc new file mode 100644 index 0000000..7f71039 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenAsmWriter.inc @@ -0,0 +1,8939 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include // debug +#include + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 10419U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 10412U, // BUNDLE + 10746U, // LIFETIME_START + 10399U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 19093U, // ADD4 + 19093U, // ADD4TLS + 16801U, // ADD4o + 19093U, // ADD8 + 19093U, // ADD8TLS + 19093U, // ADD8TLS_ + 16801U, // ADD8o + 18937U, // ADDC + 18937U, // ADDC8 + 16741U, // ADDC8o + 16741U, // ADDCo + 19414U, // ADDE + 19414U, // ADDE8 + 16924U, // ADDE8o + 16924U, // ADDEo + 19978U, // ADDI + 19978U, // ADDI8 + 18982U, // ADDIC + 18982U, // ADDIC8 + 16771U, // ADDICo + 22885U, // ADDIS + 22885U, // ADDIS8 + 10190U, // ADDISdtprelHA + 9129U, // ADDISdtprelHA32 + 10173U, // ADDISgotTprelHA + 10145U, // ADDIStlsgdHA + 10159U, // ADDIStlsldHA + 10133U, // ADDIStocHA + 10524U, // ADDIdtprelL + 9332U, // ADDIdtprelL32 + 10487U, // ADDItlsgdL + 9289U, // ADDItlsgdL32 + 10570U, // ADDItlsgdLADDR + 9384U, // ADDItlsgdLADDR32 + 10499U, // ADDItlsldL + 9303U, // ADDItlsldL32 + 10586U, // ADDItlsldLADDR + 9402U, // ADDItlsldLADDR32 + 10477U, // ADDItocL + 268454930U, // ADDME + 268454930U, // ADDME8 + 268452395U, // ADDME8o + 268452395U, // ADDMEo + 268454994U, // ADDZE + 268454994U, // ADDZE8 + 268452428U, // ADDZE8o + 268452428U, // ADDZEo + 296482U, // ADJCALLSTACKDOWN + 8947253U, // ADJCALLSTACKUP + 19252U, // AND + 19252U, // AND8 + 16863U, // AND8o + 18946U, // ANDC + 18946U, // ANDC8 + 16748U, // ANDC8o + 16748U, // ANDCo + 17561U, // ANDISo + 17561U, // ANDISo8 + 17080U, // ANDIo + 17080U, // ANDIo8 + 10681U, // ANDIo_1_EQ_BIT + 10083U, // ANDIo_1_EQ_BIT8 + 10697U, // ANDIo_1_GT_BIT + 10100U, // ANDIo_1_GT_BIT8 + 16863U, // ANDo + 554190291U, // ATOMIC_CMP_SWAP_I16 + 554190269U, // ATOMIC_CMP_SWAP_I32 + 9529U, // ATOMIC_CMP_SWAP_I64 + 10001U, // ATOMIC_CMP_SWAP_I8 + 9748U, // ATOMIC_LOAD_ADD_I16 + 9167U, // ATOMIC_LOAD_ADD_I32 + 9469U, // ATOMIC_LOAD_ADD_I64 + 9940U, // ATOMIC_LOAD_ADD_I8 + 9791U, // ATOMIC_LOAD_AND_I16 + 9210U, // ATOMIC_LOAD_AND_I32 + 9628U, // ATOMIC_LOAD_AND_I64 + 9981U, // ATOMIC_LOAD_AND_I8 + 9769U, // ATOMIC_LOAD_NAND_I16 + 9188U, // ATOMIC_LOAD_NAND_I32 + 9490U, // ATOMIC_LOAD_NAND_I64 + 9960U, // ATOMIC_LOAD_NAND_I8 + 9850U, // ATOMIC_LOAD_OR_I16 + 9269U, // ATOMIC_LOAD_OR_I32 + 9571U, // ATOMIC_LOAD_OR_I64 + 10040U, // ATOMIC_LOAD_OR_I8 + 9727U, // ATOMIC_LOAD_SUB_I16 + 9146U, // ATOMIC_LOAD_SUB_I32 + 9448U, // ATOMIC_LOAD_SUB_I64 + 9906U, // ATOMIC_LOAD_SUB_I8 + 9829U, // ATOMIC_LOAD_XOR_I16 + 9248U, // ATOMIC_LOAD_XOR_I32 + 9550U, // ATOMIC_LOAD_XOR_I64 + 10021U, // ATOMIC_LOAD_XOR_I8 + 9812U, // ATOMIC_SWAP_I16 + 9231U, // ATOMIC_SWAP_I32 + 9512U, // ATOMIC_SWAP_I64 + 10117U, // ATOMIC_SWAP_I8 + 10880U, // ATTN + 313588U, // B + 329423U, // BA + 25182312U, // BC + 879125U, // BCC + 1141269U, // BCCA + 1403413U, // BCCCTR + 1403413U, // BCCCTR8 + 1665557U, // BCCCTRL + 1665557U, // BCCCTRL8 + 1927701U, // BCCL + 2189845U, // BCCLA + 2451989U, // BCCLR + 2714133U, // BCCLRL + 2900122U, // BCCTR + 2900122U, // BCCTR8 + 2900178U, // BCCTR8n + 2900100U, // BCCTRL + 2900100U, // BCCTRL8 + 2900158U, // BCCTRL8n + 2900158U, // BCCTRLn + 2900178U, // BCCTRn + 25182320U, // BCL + 2900112U, // BCLR + 2900089U, // BCLRL + 2900148U, // BCLRLn + 2900169U, // BCLRn + 311373U, // BCLalways + 25182380U, // BCLn + 10917U, // BCTR + 10917U, // BCTR8 + 10874U, // BCTRL + 10874U, // BCTRL8 + 98394U, // BCTRL8_LDinto_toc + 25182373U, // BCn + 320294U, // BDNZ + 320294U, // BDNZ8 + 329961U, // BDNZA + 327936U, // BDNZAm + 327721U, // BDNZAp + 315560U, // BDNZL + 329734U, // BDNZLA + 327920U, // BDNZLAm + 327705U, // BDNZLAp + 10910U, // BDNZLR + 10910U, // BDNZLR8 + 10866U, // BDNZLRL + 9081U, // BDNZLRLm + 9049U, // BDNZLRLp + 9097U, // BDNZLRm + 9065U, // BDNZLRp + 311567U, // BDNZLm + 311352U, // BDNZLp + 311581U, // BDNZm + 311366U, // BDNZp + 320232U, // BDZ + 320232U, // BDZ8 + 329955U, // BDZA + 327929U, // BDZAm + 327714U, // BDZAp + 315554U, // BDZL + 329727U, // BDZLA + 327912U, // BDZLAm + 327697U, // BDZLAp + 10904U, // BDZLR + 10904U, // BDZLR8 + 10859U, // BDZLRL + 9073U, // BDZLRLm + 9041U, // BDZLRLp + 9090U, // BDZLRm + 9058U, // BDZLRp + 311560U, // BDZLm + 311345U, // BDZLp + 311575U, // BDZm + 311360U, // BDZp + 315437U, // BL + 315437U, // BL8 + 3199021U, // BL8_NOP + 3264557U, // BL8_NOP_TLS + 380973U, // BL8_TLS + 380973U, // BL8_TLS_ + 329716U, // BLA + 329716U, // BLA8 + 3213300U, // BLA8_NOP + 10900U, // BLR + 10900U, // BLR8 + 10854U, // BLRL + 380973U, // BL_TLS + 19031U, // BRINC + 19992U, // CLRLSLDI + 17060U, // CLRLSLDIo + 20334U, // CLRLSLWI + 17158U, // CLRLSLWIo + 20027U, // CLRRDI + 17087U, // CLRRDIo + 20375U, // CLRRWI + 17187U, // CLRRWIo + 18707U, // CMPB + 18707U, // CMPB8 + 19296U, // CMPD + 20020U, // CMPDI + 19230U, // CMPLD + 19984U, // CMPLDI + 24018U, // CMPLW + 20318U, // CMPLWI + 24258U, // CMPW + 20368U, // CMPWI + 268454862U, // CNTLZD + 268452371U, // CNTLZDo + 268459932U, // CNTLZW + 268459932U, // CNTLZW8 + 268453215U, // CNTLZW8o + 268453215U, // CNTLZWo + 9713U, // CR6SET + 9699U, // CR6UNSET + 19282U, // CRAND + 18952U, // CRANDC + 23565U, // CREQV + 19266U, // CRNAND + 22356U, // CRNOR + 22370U, // CROR + 19052U, // CRORC + 33577997U, // CRSET + 33576822U, // CRUNSET + 22390U, // CRXOR + 132813U, // DCBA + 134241U, // DCBF + 134619U, // DCBI + 138004U, // DCBST + 137959U, // DCBT + 138016U, // DCBTST + 139997U, // DCBZ + 135323U, // DCBZL + 268455405U, // DCCCI + 19393U, // DIVD + 23421U, // DIVDU + 17630U, // DIVDUo + 16908U, // DIVDo + 24461U, // DIVW + 23526U, // DIVWU + 17647U, // DIVWUo + 17752U, // DIVWo + 416157U, // DSS + 10847U, // DSSALL + 847420187U, // DST + 847420187U, // DST64 + 847420200U, // DSTST + 847420200U, // DSTST64 + 847420213U, // DSTSTT + 847420213U, // DSTSTT64 + 847420207U, // DSTT + 847420207U, // DSTT64 + 10213U, // DYNALLOC + 9870U, // DYNALLOC8 + 9347U, // EH_SjLj_LongJmp32 + 9591U, // EH_SjLj_LongJmp64 + 9366U, // EH_SjLj_SetJmp32 + 9610U, // EH_SjLj_SetJmp64 + 311297U, // EH_SjLj_Setup + 23560U, // EQV + 23560U, // EQV8 + 17662U, // EQV8o + 17662U, // EQVo + 268457944U, // EVABS + 50355624U, // EVADDIW + 268459087U, // EVADDSMIAAW + 268459219U, // EVADDSSIAAW + 268459153U, // EVADDUMIAAW + 268459285U, // EVADDUSIAAW + 23902U, // EVADDW + 19289U, // EVAND + 18960U, // EVANDC + 22237U, // EVCMPEQ + 22964U, // EVCMPGTS + 23472U, // EVCMPGTU + 22974U, // EVCMPLTS + 23482U, // EVCMPLTU + 268459753U, // EVCNTLSW + 268459930U, // EVCNTLZW + 23109U, // EVDIVWS + 23524U, // EVDIVWU + 23572U, // EVEQV + 268454247U, // EVEXTSB + 268455278U, // EVEXTSH + 58739421U, // EVLDD + 24589U, // EVLDDX + 58739957U, // EVLDH + 24693U, // EVLDHX + 58744166U, // EVLDW + 25233U, // EVLDWX + 58743462U, // EVLHHESPLAT + 24986U, // EVLHHESPLATX + 58743487U, // EVLHHOSSPLAT + 25013U, // EVLHHOSSPLATX + 58743501U, // EVLHHOUSPLAT + 25028U, // EVLHHOUSPLATX + 58739699U, // EVLWHE + 24664U, // EVLWHEX + 58743188U, // EVLWHOS + 24966U, // EVLWHOSX + 58743699U, // EVLWHOU + 25144U, // EVLWHOUX + 58743475U, // EVLWHSPLAT + 25000U, // EVLWHSPLATX + 58743515U, // EVLWWSPLAT + 25043U, // EVLWWSPLATX + 20091U, // EVMERGEHI + 21072U, // EVMERGEHILO + 21061U, // EVMERGELO + 20102U, // EVMERGELOHI + 18003U, // EVMHEGSMFAA + 20878U, // EVMHEGSMFAN + 18051U, // EVMHEGSMIAA + 20926U, // EVMHEGSMIAN + 18088U, // EVMHEGUMIAA + 20963U, // EVMHEGUMIAN + 19565U, // EVMHESMF + 18136U, // EVMHESMFA + 23579U, // EVMHESMFAAW + 24050U, // EVMHESMFANW + 20145U, // EVMHESMI + 18227U, // EVMHESMIA + 23644U, // EVMHESMIAAW + 24102U, // EVMHESMIANW + 19640U, // EVMHESSF + 18179U, // EVMHESSFA + 23605U, // EVMHESSFAAW + 24076U, // EVMHESSFANW + 23776U, // EVMHESSIAAW + 24180U, // EVMHESSIANW + 20184U, // EVMHEUMI + 18270U, // EVMHEUMIA + 23710U, // EVMHEUMIAAW + 24141U, // EVMHEUMIANW + 23842U, // EVMHEUSIAAW + 24219U, // EVMHEUSIANW + 18016U, // EVMHOGSMFAA + 20891U, // EVMHOGSMFAN + 18064U, // EVMHOGSMIAA + 20939U, // EVMHOGSMIAN + 18101U, // EVMHOGUMIAA + 20976U, // EVMHOGUMIAN + 19585U, // EVMHOSMF + 18158U, // EVMHOSMFA + 23592U, // EVMHOSMFAAW + 24063U, // EVMHOSMFANW + 20165U, // EVMHOSMI + 18249U, // EVMHOSMIA + 23684U, // EVMHOSMIAAW + 24128U, // EVMHOSMIANW + 19660U, // EVMHOSSF + 18201U, // EVMHOSSFA + 23618U, // EVMHOSSFAAW + 24089U, // EVMHOSSFANW + 23816U, // EVMHOSSIAAW + 24206U, // EVMHOSSIANW + 20214U, // EVMHOUMI + 18303U, // EVMHOUMIA + 23750U, // EVMHOUMIAAW + 24167U, // EVMHOUMIANW + 23882U, // EVMHOUSIAAW + 24245U, // EVMHOUSIANW + 268453902U, // EVMRA + 19575U, // EVMWHSMF + 18147U, // EVMWHSMFA + 20155U, // EVMWHSMI + 18238U, // EVMWHSMIA + 19650U, // EVMWHSSF + 18190U, // EVMWHSSFA + 20194U, // EVMWHUMI + 18281U, // EVMWHUMIA + 23671U, // EVMWLSMIAAW + 24115U, // EVMWLSMIANW + 23803U, // EVMWLSSIAAW + 24193U, // EVMWLSSIANW + 20204U, // EVMWLUMI + 18292U, // EVMWLUMIA + 23737U, // EVMWLUMIAAW + 24154U, // EVMWLUMIANW + 23869U, // EVMWLUSIAAW + 24232U, // EVMWLUSIANW + 19595U, // EVMWSMF + 18169U, // EVMWSMFA + 18029U, // EVMWSMFAA + 20904U, // EVMWSMFAN + 20175U, // EVMWSMI + 18260U, // EVMWSMIA + 18077U, // EVMWSMIAA + 20952U, // EVMWSMIAN + 19670U, // EVMWSSF + 18212U, // EVMWSSFA + 18040U, // EVMWSSFAA + 20915U, // EVMWSSFAN + 20224U, // EVMWUMI + 18314U, // EVMWUMIA + 18114U, // EVMWUMIAA + 20989U, // EVMWUMIAN + 19274U, // EVNAND + 268455143U, // EVNEG + 22363U, // EVNOR + 22376U, // EVOR + 19059U, // EVORC + 24025U, // EVRLW + 20326U, // EVRLWI + 268459373U, // EVRNDW + 24032U, // EVSLW + 20352U, // EVSLWI + 268455536U, // EVSPLATFI + 268455748U, // EVSPLATI + 22904U, // EVSRWIS + 23434U, // EVSRWIU + 23046U, // EVSRWS + 23510U, // EVSRWU + 58739428U, // EVSTDD + 24597U, // EVSTDDX + 58739964U, // EVSTDH + 24701U, // EVSTDHX + 58744181U, // EVSTDW + 25241U, // EVSTDWX + 58739707U, // EVSTWHE + 24673U, // EVSTWHEX + 58741308U, // EVSTWHO + 24794U, // EVSTWHOX + 58739785U, // EVSTWWE + 24683U, // EVSTWWEX + 58741353U, // EVSTWWO + 24804U, // EVSTWWOX + 268459113U, // EVSUBFSMIAAW + 268459245U, // EVSUBFSSIAAW + 268459179U, // EVSUBFUMIAAW + 268459311U, // EVSUBFUSIAAW + 23933U, // EVSUBFW + 67132806U, // EVSUBIFW + 22397U, // EVXOR + 20002U, // EXTLDI + 17071U, // EXTLDIo + 20360U, // EXTLWI + 17178U, // EXTLWIo + 20051U, // EXTRDI + 17114U, // EXTRDIo + 20399U, // EXTRWI + 17214U, // EXTRWIo + 268454249U, // EXTSB + 268454249U, // EXTSB8 + 268454249U, // EXTSB8_32_64 + 268452143U, // EXTSB8o + 268452143U, // EXTSBo + 268455280U, // EXTSH + 268455280U, // EXTSH8 + 268455280U, // EXTSH8_32_64 + 268452478U, // EXTSH8o + 268452478U, // EXTSHo + 268459790U, // EXTSW + 268459790U, // EXTSW_32_64 + 268453178U, // EXTSW_32_64o + 268453178U, // EXTSWo + 10885U, // EnforceIEIO + 268457929U, // FABSD + 268452914U, // FABSDo + 268457929U, // FABSS + 268452914U, // FABSSo + 19092U, // FADD + 22583U, // FADDS + 17500U, // FADDSo + 16800U, // FADDo + 0U, // FADDrtz + 268454656U, // FCFID + 268458121U, // FCFIDS + 268452983U, // FCFIDSo + 268458848U, // FCFIDU + 268458450U, // FCFIDUS + 268453042U, // FCFIDUSo + 268453077U, // FCFIDUo + 268452288U, // FCFIDo + 23452U, // FCMPUD + 23452U, // FCMPUS + 21013U, // FCPSGND + 17278U, // FCPSGNDo + 21013U, // FCPSGNS + 17278U, // FCPSGNSo + 268454665U, // FCTID + 268460846U, // FCTIDUZ + 268453264U, // FCTIDUZo + 268460783U, // FCTIDZ + 268453248U, // FCTIDZo + 268452296U, // FCTIDo + 268459443U, // FCTIW + 268460857U, // FCTIWUZ + 268453274U, // FCTIWUZo + 268460868U, // FCTIWZ + 268453284U, // FCTIWZo + 268453139U, // FCTIWo + 23551U, // FDIV + 23039U, // FDIVS + 17596U, // FDIVSo + 17655U, // FDIVo + 19100U, // FMADD + 22592U, // FMADDS + 17508U, // FMADDSo + 16807U, // FMADDo + 268457792U, // FMR + 268452896U, // FMRo + 18891U, // FMSUB + 22562U, // FMSUBS + 17481U, // FMSUBSo + 16713U, // FMSUBo + 20607U, // FMUL + 22915U, // FMULS + 17569U, // FMULSo + 17247U, // FMULo + 268457937U, // FNABSD + 268452921U, // FNABSDo + 268457937U, // FNABSS + 268452921U, // FNABSSo + 268455137U, // FNEGD + 268452460U, // FNEGDo + 268455137U, // FNEGS + 268452460U, // FNEGSo + 19109U, // FNMADD + 22602U, // FNMADDS + 17517U, // FNMADDSo + 16815U, // FNMADDo + 18900U, // FNMSUB + 22572U, // FNMSUBS + 17490U, // FNMSUBSo + 16721U, // FNMSUBo + 268454954U, // FRE + 268458203U, // FRES + 268452992U, // FRESo + 268452412U, // FREo + 268456252U, // FRIMD + 268452710U, // FRIMDo + 268456252U, // FRIMS + 268452710U, // FRIMSo + 268456486U, // FRIND + 268452743U, // FRINDo + 268456486U, // FRINS + 268452743U, // FRINSo + 268457336U, // FRIPD + 268452829U, // FRIPDo + 268457336U, // FRIPS + 268452829U, // FRIPSo + 268460832U, // FRIZD + 268453257U, // FRIZDo + 268460832U, // FRIZS + 268453257U, // FRIZSo + 268457576U, // FRSP + 268452860U, // FRSPo + 268454969U, // FRSQRTE + 268458211U, // FRSQRTES + 268452999U, // FRSQRTESo + 268452418U, // FRSQRTEo + 20559U, // FSELD + 17240U, // FSELDo + 20559U, // FSELS + 17240U, // FSELSo + 268458765U, // FSQRT + 268458440U, // FSQRTS + 268453033U, // FSQRTSo + 268453060U, // FSQRTo + 18883U, // FSUB + 22553U, // FSUBS + 17473U, // FSUBSo + 16706U, // FSUBo + 10616U, // GETtlsADDR + 9435U, // GETtlsADDR32 + 10602U, // GETtlsldADDR + 9420U, // GETtlsldADDR32 + 134625U, // ICBI + 187117U, // ICBT + 268455412U, // ICCCI + 20344U, // INSLWI + 17169U, // INSLWIo + 20035U, // INSRDI + 17096U, // INSRDIo + 20383U, // INSRWI + 17196U, // INSRWIo + 20565U, // ISEL + 20565U, // ISEL8 + 10783U, // ISYNC + 75515893U, // LA + 58738677U, // LAx + 58745571U, // LBZ + 58745571U, // LBZ8 + 24770U, // LBZCIX + 83909613U, // LBZU + 83909613U, // LBZU8 + 92299889U, // LBZUX + 92299889U, // LBZUX8 + 285237953U, // LBZX + 285237953U, // LBZX8 + 58739475U, // LD + 285237511U, // LDARX + 285237525U, // LDBRX + 24739U, // LDCIX + 83909490U, // LDU + 92299805U, // LDUX + 285237300U, // LDX + 10511U, // LDgotTprelL + 9317U, // LDgotTprelL32 + 10795U, // LDtoc + 10736U, // LDtocBA + 10736U, // LDtocCPT + 10459U, // LDtocJTI + 10469U, // LDtocL + 58739436U, // LFD + 83909449U, // LFDU + 92299788U, // LFDUX + 285237280U, // LFDX + 285237207U, // LFIWAX + 285237967U, // LFIWZX + 58743027U, // LFS + 83909539U, // LFSU + 92299865U, // LFSUX + 285237613U, // LFSX + 58738478U, // LHA + 58738478U, // LHA8 + 83909437U, // LHAU + 83909437U, // LHAU8 + 92299744U, // LHAUX + 92299744U, // LHAUX8 + 285237190U, // LHAX + 285237190U, // LHAX8 + 285237540U, // LHBRX + 285237540U, // LHBRX8 + 58745591U, // LHZ + 58745591U, // LHZ8 + 24778U, // LHZCIX + 83909619U, // LHZU + 83909619U, // LHZU8 + 92299896U, // LHZUX + 92299896U, // LHZUX8 + 285237959U, // LHZX + 285237959U, // LHZX8 + 100683414U, // LI + 100683414U, // LI8 + 100686188U, // LIS + 100686188U, // LIS8 + 58744295U, // LMW + 20407U, // LSWI + 285237221U, // LVEBX + 285237382U, // LVEHX + 285237922U, // LVEWX + 285233271U, // LVSL + 285235116U, // LVSR + 285237894U, // LVX + 285233294U, // LVXL + 58738709U, // LWA + 285237518U, // LWARX + 92299751U, // LWAUX + 285237215U, // LWAX + 285237215U, // LWAX_32 + 58738709U, // LWA_32 + 285237555U, // LWBRX + 285237555U, // LWBRX8 + 58745676U, // LWZ + 58745676U, // LWZ8 + 24786U, // LWZCIX + 83909625U, // LWZU + 83909625U, // LWZU8 + 92299903U, // LWZUX + 92299903U, // LWZUX8 + 285237975U, // LWZX + 285237975U, // LWZX8 + 10802U, // LWZtoc + 285237315U, // LXSDX + 285237156U, // LXVD2X + 285237596U, // LXVDSX + 285237173U, // LXVW4X + 415475U, // MBAR + 268455060U, // MCRF + 268458232U, // MCRFS + 284430U, // MFCR + 284430U, // MFCR8 + 284601U, // MFCTR + 284601U, // MFCTR8 + 268457721U, // MFDCR + 284909U, // MFFS + 279698U, // MFFSo + 284466U, // MFLR + 284466U, // MFLR8 + 284568U, // MFMSR + 109071514U, // MFOCRF + 109071514U, // MFOCRF8 + 268457860U, // MFSPR + 117462930U, // MFSR + 268456492U, // MFSRIN + 268454264U, // MFTB + 3430276U, // MFTB8 + 3692420U, // MFVRSAVE + 3692420U, // MFVRSAVEv + 284444U, // MFVSCR + 10789U, // MSYNC + 268455082U, // MTCRF + 268455082U, // MTCRF8 + 284608U, // MTCTR + 284608U, // MTCTR8 + 284608U, // MTCTR8loop + 284608U, // MTCTRloop + 302159623U, // MTDCR + 411053U, // MTFSB0 + 411061U, // MTFSB1 + 19633U, // MTFSF + 20072U, // MTFSFI + 17123U, // MTFSFIo + 268455089U, // MTFSFb + 16996U, // MTFSFo + 284472U, // MTLR + 284472U, // MTLR8 + 268457887U, // MTMSR + 268454758U, // MTMSRD + 199842U, // MTOCRF + 199842U, // MTOCRF8 + 268457867U, // MTSPR + 219046U, // MTSR + 268456500U, // MTSRIN + 278748U, // MTVRSAVE + 426204U, // MTVRSAVEv + 284452U, // MTVSCR + 19191U, // MULHD + 23382U, // MULHDU + 17612U, // MULHDUo + 16824U, // MULHDo + 23969U, // MULHW + 23492U, // MULHWU + 17638U, // MULHWUo + 17675U, // MULHWo + 19223U, // MULLD + 16848U, // MULLDo + 20122U, // MULLI + 20122U, // MULLI8 + 24011U, // MULLW + 17691U, // MULLWo + 10640U, // MoveGOTtoLR + 10628U, // MovePCtoLR + 10070U, // MovePCtoLR8 + 19260U, // NAND + 19260U, // NAND8 + 16862U, // NAND8o + 16862U, // NANDo + 268455138U, // NEG + 268455138U, // NEG8 + 268452461U, // NEG8o + 268452461U, // NEGo + 10896U, // NOP + 9105U, // NOP_GT_PWR6 + 9117U, // NOP_GT_PWR7 + 22351U, // NOR + 22351U, // NOR8 + 17446U, // NOR8o + 17446U, // NORo + 22344U, // OR + 22344U, // OR8 + 17447U, // OR8o + 19047U, // ORC + 19047U, // ORC8 + 16787U, // ORC8o + 16787U, // ORCo + 20276U, // ORI + 20276U, // ORI8 + 22898U, // ORIS + 22898U, // ORIS8 + 17447U, // ORo + 268454799U, // POPCNTD + 268459823U, // POPCNTW + 10713U, // PPC32GOT + 10723U, // PPC32PICGOT + 20233U, // QVALIGNI + 20233U, // QVALIGNIb + 20233U, // QVALIGNIs + 20281U, // QVESPLATI + 20281U, // QVESPLATIb + 20281U, // QVESPLATIs + 268457927U, // QVFABS + 268457927U, // QVFABSs + 19090U, // QVFADD + 22581U, // QVFADDS + 22581U, // QVFADDSs + 268454654U, // QVFCFID + 268458119U, // QVFCFIDS + 268458846U, // QVFCFIDU + 268458448U, // QVFCFIDUS + 268454654U, // QVFCFIDb + 22227U, // QVFCMPEQ + 22227U, // QVFCMPEQb + 22227U, // QVFCMPEQbs + 23283U, // QVFCMPGT + 23283U, // QVFCMPGTb + 23283U, // QVFCMPGTbs + 23299U, // QVFCMPLT + 23299U, // QVFCMPLTb + 23299U, // QVFCMPLTbs + 21011U, // QVFCPSGN + 21011U, // QVFCPSGNs + 268454663U, // QVFCTID + 268458856U, // QVFCTIDU + 268460844U, // QVFCTIDUZ + 268460781U, // QVFCTIDZ + 268454663U, // QVFCTIDb + 268459441U, // QVFCTIW + 268458956U, // QVFCTIWU + 268460855U, // QVFCTIWUZ + 268460866U, // QVFCTIWZ + 20513U, // QVFLOGICAL + 20513U, // QVFLOGICALb + 20513U, // QVFLOGICALs + 19098U, // QVFMADD + 22590U, // QVFMADDS + 22590U, // QVFMADDSs + 268457790U, // QVFMR + 268457790U, // QVFMRb + 268457790U, // QVFMRs + 18889U, // QVFMSUB + 22560U, // QVFMSUBS + 22560U, // QVFMSUBSs + 20605U, // QVFMUL + 22913U, // QVFMULS + 22913U, // QVFMULSs + 268457935U, // QVFNABS + 268457935U, // QVFNABSs + 268455135U, // QVFNEG + 268455135U, // QVFNEGs + 19107U, // QVFNMADD + 22600U, // QVFNMADDS + 22600U, // QVFNMADDSs + 18898U, // QVFNMSUB + 22570U, // QVFNMSUBS + 22570U, // QVFNMSUBSs + 20817U, // QVFPERM + 20817U, // QVFPERMs + 268454952U, // QVFRE + 268458201U, // QVFRES + 268458201U, // QVFRESs + 268456250U, // QVFRIM + 268456250U, // QVFRIMs + 268456484U, // QVFRIN + 268456484U, // QVFRINs + 268457334U, // QVFRIP + 268457334U, // QVFRIPs + 268460830U, // QVFRIZ + 268460830U, // QVFRIZs + 268457574U, // QVFRSP + 268457574U, // QVFRSPs + 268454967U, // QVFRSQRTE + 268458209U, // QVFRSQRTES + 268458209U, // QVFRSQRTESs + 20557U, // QVFSEL + 20557U, // QVFSELb + 20557U, // QVFSELbb + 20557U, // QVFSELbs + 18881U, // QVFSUB + 22551U, // QVFSUBS + 22551U, // QVFSUBSs + 21000U, // QVFTSTNAN + 21000U, // QVFTSTNANb + 21000U, // QVFTSTNANbs + 19144U, // QVFXMADD + 22640U, // QVFXMADDS + 20613U, // QVFXMUL + 22922U, // QVFXMULS + 19117U, // QVFXXCPNMADD + 22611U, // QVFXXCPNMADDS + 19154U, // QVFXXMADD + 22651U, // QVFXXMADDS + 19131U, // QVFXXNPMADD + 22626U, // QVFXXNPMADDS + 125849083U, // QVGPCI + 285237749U, // QVLFCDUX + 285231221U, // QVLFCDUXA + 285237242U, // QVLFCDX + 285231141U, // QVLFCDXA + 285237826U, // QVLFCSUX + 285231265U, // QVLFCSUXA + 285237577U, // QVLFCSX + 285231181U, // QVLFCSXA + 285237577U, // QVLFCSXs + 92299786U, // QVLFDUX + 285231244U, // QVLFDUXA + 285237278U, // QVLFDX + 285231162U, // QVLFDXA + 285237278U, // QVLFDXb + 285237205U, // QVLFIWAX + 285231130U, // QVLFIWAXA + 285237965U, // QVLFIWZX + 285231320U, // QVLFIWZXA + 92299863U, // QVLFSUX + 285231288U, // QVLFSUXA + 285237611U, // QVLFSX + 285231202U, // QVLFSXA + 285237611U, // QVLFSXb + 285237611U, // QVLFSXs + 285237295U, // QVLPCLDX + 285237628U, // QVLPCLSX + 3957116U, // QVLPCLSXint + 285237305U, // QVLPCRDX + 285237648U, // QVLPCRSX + 285237759U, // QVSTFCDUX + 285231232U, // QVSTFCDUXA + 285233139U, // QVSTFCDUXI + 285231042U, // QVSTFCDUXIA + 285237251U, // QVSTFCDX + 285231151U, // QVSTFCDXA + 285233097U, // QVSTFCDXI + 285230996U, // QVSTFCDXIA + 285237836U, // QVSTFCSUX + 285231276U, // QVSTFCSUXA + 285233162U, // QVSTFCSUXI + 285231067U, // QVSTFCSUXIA + 285237586U, // QVSTFCSX + 285231191U, // QVSTFCSXA + 285233118U, // QVSTFCSXI + 285231019U, // QVSTFCSXIA + 285237586U, // QVSTFCSXs + 92447251U, // QVSTFDUX + 285231254U, // QVSTFDUXA + 285233151U, // QVSTFDUXI + 285231055U, // QVSTFDUXIA + 285237286U, // QVSTFDX + 285231171U, // QVSTFDXA + 285233108U, // QVSTFDXI + 285231008U, // QVSTFDXIA + 285237286U, // QVSTFDXb + 285237937U, // QVSTFIWX + 285231309U, // QVSTFIWXA + 92447328U, // QVSTFSUX + 285231298U, // QVSTFSUXA + 285233174U, // QVSTFSUXI + 285231080U, // QVSTFSUXIA + 92447328U, // QVSTFSUXs + 285237619U, // QVSTFSX + 285231211U, // QVSTFSXA + 285233129U, // QVSTFSXI + 285231031U, // QVSTFSXIA + 285237619U, // QVSTFSXs + 10548U, // RESTORE_CR + 10653U, // RESTORE_CRBIT + 10429U, // RESTORE_VRSAVE + 10827U, // RFCI + 10838U, // RFDI + 10843U, // RFI + 10810U, // RFID + 10832U, // RFMCI + 20534U, // RLDCL + 17223U, // RLDCLo + 22272U, // RLDCR + 17423U, // RLDCRo + 18989U, // RLDIC + 20541U, // RLDICL + 20541U, // RLDICL_32_64 + 17231U, // RLDICLo + 22292U, // RLDICR + 17431U, // RLDICRo + 16779U, // RLDICo + 1115704993U, // RLDIMI + 1115701996U, // RLDIMIo + 1384140457U, // RLWIMI + 1384140457U, // RLWIMI8 + 1384137461U, // RLWIMI8o + 1384137461U, // RLWIMIo + 20802U, // RLWINM + 20802U, // RLWINM8 + 17261U, // RLWINM8o + 17261U, // RLWINMo + 20810U, // RLWNM + 20810U, // RLWNM8 + 17270U, // RLWNM8o + 17270U, // RLWNMo + 20043U, // ROTRDI + 17105U, // ROTRDIo + 20391U, // ROTRWI + 17205U, // ROTRWIo + 10205U, // ReadTB + 281210U, // SC + 9649U, // SELECT_CC_F4 + 9881U, // SELECT_CC_F8 + 9674U, // SELECT_CC_I4 + 9926U, // SELECT_CC_I8 + 10223U, // SELECT_CC_QBRC + 10252U, // SELECT_CC_QFRC + 10341U, // SELECT_CC_QSRC + 10312U, // SELECT_CC_VRRC + 10281U, // SELECT_CC_VSFRC + 10370U, // SELECT_CC_VSRC + 9663U, // SELECT_F4 + 9895U, // SELECT_F8 + 9688U, // SELECT_I4 + 10059U, // SELECT_I8 + 10239U, // SELECT_QBRC + 10268U, // SELECT_QFRC + 10357U, // SELECT_QSRC + 10328U, // SELECT_VRRC + 10298U, // SELECT_VSFRC + 10386U, // SELECT_VSRC + 10761U, // SLBIA + 281604U, // SLBIE + 268454876U, // SLBMFEE + 268454959U, // SLBMTE + 19244U, // SLD + 19996U, // SLDI + 17064U, // SLDIo + 16856U, // SLDo + 24034U, // SLW + 24034U, // SLW8 + 17699U, // SLW8o + 20338U, // SLWI + 17162U, // SLWIo + 17699U, // SLWo + 10560U, // SPILL_CR + 10668U, // SPILL_CRBIT + 10445U, // SPILL_VRSAVE + 19084U, // SRAD + 19971U, // SRADI + 17052U, // SRADIo + 16793U, // SRADo + 23896U, // SRAW + 20302U, // SRAWI + 17150U, // SRAWIo + 17668U, // SRAWo + 19305U, // SRD + 20037U, // SRDI + 17098U, // SRDIo + 16869U, // SRDo + 24265U, // SRW + 24265U, // SRW8 + 17705U, // SRW8o + 20385U, // SRWI + 17198U, // SRWIo + 17705U, // SRWo + 58739088U, // STB + 58739088U, // STB8 + 24731U, // STBCIX + 84056899U, // STBU + 84056899U, // STBU8 + 92447214U, // STBUX + 92447214U, // STBUX8 + 285237236U, // STBX + 285237236U, // STBX8 + 58739608U, // STD + 285237532U, // STDBRX + 24746U, // STDCIX + 285230440U, // STDCX + 84056951U, // STDU + 92447267U, // STDUX + 285237330U, // STDX + 58739441U, // STFD + 84056911U, // STFDU + 92447253U, // STFDUX + 285237288U, // STFDX + 285237939U, // STFIWX + 58743039U, // STFS + 84057001U, // STFSU + 92447330U, // STFSUX + 285237621U, // STFSX + 58740113U, // STH + 58740113U, // STH8 + 285237547U, // STHBRX + 24754U, // STHCIX + 84056964U, // STHU + 84056964U, // STHU8 + 92447281U, // STHUX + 92447281U, // STHUX8 + 285237397U, // STHX + 285237397U, // STHX8 + 58744300U, // STMW + 20413U, // STSWI + 285237228U, // STVEBX + 285237389U, // STVEHX + 285237929U, // STVEWX + 285237899U, // STVX + 285233300U, // STVXL + 58744632U, // STW + 58744632U, // STW8 + 285237562U, // STWBRX + 24762U, // STWCIX + 285230448U, // STWCX + 84057054U, // STWU + 84057054U, // STWU8 + 92447338U, // STWUX + 92447338U, // STWUX8 + 285237947U, // STWX + 285237947U, // STWX8 + 285237322U, // STXSDX + 285237164U, // STXVD2X + 285237181U, // STXVW4X + 19559U, // SUBF + 19559U, // SUBF8 + 16989U, // SUBF8o + 18968U, // SUBFC + 18968U, // SUBFC8 + 16755U, // SUBFC8o + 16755U, // SUBFCo + 19436U, // SUBFE + 19436U, // SUBFE8 + 16931U, // SUBFE8o + 16931U, // SUBFEo + 18996U, // SUBFIC + 18996U, // SUBFIC8 + 268454937U, // SUBFME + 268454937U, // SUBFME8 + 268452403U, // SUBFME8o + 268452403U, // SUBFMEo + 268455001U, // SUBFZE + 268455001U, // SUBFZE8 + 268452436U, // SUBFZE8o + 268452436U, // SUBFZEo + 16989U, // SUBFo + 19943U, // SUBI + 18975U, // SUBIC + 16763U, // SUBICo + 22878U, // SUBIS + 281182U, // SYNC + 313588U, // TAILB + 313588U, // TAILB8 + 329423U, // TAILBA + 329423U, // TAILBA8 + 10917U, // TAILBCTR + 10917U, // TAILBCTR8 + 269026886U, // TCRETURNai + 269026793U, // TCRETURNai8 + 269011582U, // TCRETURNdi + 269010423U, // TCRETURNdi8 + 268981990U, // TCRETURNri + 268977669U, // TCRETURNri8 + 150420U, // TD + 151131U, // TDI + 10767U, // TLBIA + 4361227U, // TLBIE + 282693U, // TLBIEL + 268459980U, // TLBIVAX + 281360U, // TLBLD + 282259U, // TLBLI + 10815U, // TLBRE + 19489U, // TLBRE2 + 268460354U, // TLBSX + 24898U, // TLBSX2 + 17784U, // TLBSX2D + 10775U, // TLBSYNC + 10821U, // TLBWE + 19522U, // TLBWE2 + 10891U, // TRAP + 155425U, // TW + 151492U, // TWI + 268453395U, // UPDATE_VRSAVE + 10537U, // UpdateGBR + 24390U, // VADDCUW + 21753U, // VADDFP + 22514U, // VADDSBS + 22831U, // VADDSHS + 23073U, // VADDSWS + 20674U, // VADDUBM + 22542U, // VADDUBS + 20702U, // VADDUDM + 20741U, // VADDUHM + 22859U, // VADDUHS + 20860U, // VADDUWM + 23100U, // VADDUWS + 19290U, // VAND + 18961U, // VANDC + 18728U, // VAVGSB + 19759U, // VAVGSH + 24279U, // VAVGSW + 18846U, // VAVGUB + 19871U, // VAVGUH + 24408U, // VAVGUW + 1652580708U, // VCFSX + 1879073124U, // VCFSX_0 + 1652580906U, // VCFUX + 1879073322U, // VCFUX_0 + 268454382U, // VCLZB + 268454855U, // VCLZD + 268455380U, // VCLZH + 268459923U, // VCLZW + 21717U, // VCMPBFP + 17330U, // VCMPBFPo + 21816U, // VCMPEQFP + 17351U, // VCMPEQFPo + 18871U, // VCMPEQUB + 16695U, // VCMPEQUBo + 19365U, // VCMPEQUD + 16886U, // VCMPEQUDo + 19896U, // VCMPEQUH + 17030U, // VCMPEQUHo + 24433U, // VCMPEQUW + 17730U, // VCMPEQUWo + 21770U, // VCMPGEFP + 17340U, // VCMPGEFPo + 21826U, // VCMPGTFP + 17362U, // VCMPGTFPo + 18781U, // VCMPGTSB + 16676U, // VCMPGTSBo + 19324U, // VCMPGTSD + 16875U, // VCMPGTSDo + 19812U, // VCMPGTSH + 17011U, // VCMPGTSHo + 24324U, // VCMPGTSW + 17711U, // VCMPGTSWo + 18908U, // VCMPGTUB + 16730U, // VCMPGTUBo + 19375U, // VCMPGTUD + 16897U, // VCMPGTUDo + 19906U, // VCMPGTUH + 17041U, // VCMPGTUHo + 24443U, // VCMPGTUW + 17741U, // VCMPGTUWo + 1652578966U, // VCTSXS + 1879071382U, // VCTSXS_0 + 1652578974U, // VCTUXS + 1879071390U, // VCTUXS_0 + 23573U, // VEQV + 268457243U, // VEXPTEFP + 268457217U, // VLOGEFP + 21744U, // VMADDFP + 21836U, // VMAXFP + 18800U, // VMAXSB + 19334U, // VMAXSD + 19831U, // VMAXSH + 24341U, // VMAXSW + 18918U, // VMAXUB + 19385U, // VMAXUD + 19916U, // VMAXUH + 24453U, // VMAXUW + 22808U, // VMHADDSHS + 22819U, // VMHRADDSHS + 19357U, // VMIDUD + 21808U, // VMINFP + 18764U, // VMINSB + 19316U, // VMINSD + 19795U, // VMINSH + 24307U, // VMINSW + 18854U, // VMINUB + 19879U, // VMINUH + 24416U, // VMINUW + 20730U, // VMLADDUHM + 18679U, // VMRGHB + 19716U, // VMRGHH + 23952U, // VMRGHW + 18687U, // VMRGLB + 19724U, // VMRGLH + 23994U, // VMRGLW + 20655U, // VMSUMMBM + 20711U, // VMSUMSHM + 22840U, // VMSUMSHS + 20683U, // VMSUMUBM + 20750U, // VMSUMUHM + 22868U, // VMSUMUHS + 18719U, // VMULESB + 19750U, // VMULESH + 24270U, // VMULESW + 18837U, // VMULEUB + 19862U, // VMULEUH + 24399U, // VMULEUW + 18772U, // VMULOSB + 19803U, // VMULOSH + 24315U, // VMULOSW + 18862U, // VMULOUB + 19887U, // VMULOUH + 24424U, // VMULOUW + 20869U, // VMULUWM + 19275U, // VNAND + 21726U, // VNMSUBFP + 22364U, // VNOR + 22377U, // VOR + 19060U, // VORC + 20826U, // VPERM + 24823U, // VPKPX + 22946U, // VPKSHSS + 23003U, // VPKSHUS + 22955U, // VPKSWSS + 23021U, // VPKSWUS + 20833U, // VPKUHUM + 23012U, // VPKUHUS + 20842U, // VPKUWUM + 23030U, // VPKUWUS + 268454278U, // VPOPCNTB + 268454798U, // VPOPCNTD + 268455303U, // VPOPCNTH + 268459822U, // VPOPCNTW + 268457236U, // VREFP + 268456216U, // VRFIM + 268456477U, // VRFIN + 268457300U, // VRFIP + 268460796U, // VRFIZ + 18695U, // VRLB + 19237U, // VRLD + 19732U, // VRLH + 24026U, // VRLW + 268457253U, // VRSQRTEFP + 20571U, // VSEL + 20600U, // VSL + 18701U, // VSLB + 19243U, // VSLD + 20243U, // VSLDOI + 19738U, // VSLH + 21085U, // VSLO + 24033U, // VSLW + 1652574590U, // VSPLTB + 1652575615U, // VSPLTH + 134236473U, // VSPLTISB + 134237504U, // VSPLTISH + 134242015U, // VSPLTISW + 1652580125U, // VSPLTW + 22445U, // VSR + 18672U, // VSRAB + 19083U, // VSRAD + 19694U, // VSRAH + 23895U, // VSRAW + 18713U, // VSRB + 19310U, // VSRD + 19744U, // VSRH + 21091U, // VSRO + 24264U, // VSRW + 24381U, // VSUBCUW + 21736U, // VSUBFP + 22505U, // VSUBSBS + 22799U, // VSUBSHS + 23064U, // VSUBSWS + 20665U, // VSUBUBM + 22533U, // VSUBUBS + 20693U, // VSUBUDM + 20721U, // VSUBUHM + 22850U, // VSUBUHS + 20851U, // VSUBUWM + 23091U, // VSUBUWS + 23054U, // VSUM2SWS + 22495U, // VSUM4SBS + 22789U, // VSUM4SHS + 22523U, // VSUM4UBS + 23082U, // VSUMSWS + 268460270U, // VUPKHPX + 268454192U, // VUPKHSB + 268455223U, // VUPKHSH + 268460286U, // VUPKLPX + 268454211U, // VUPKLSB + 268455242U, // VUPKLSH + 22398U, // VXOR + 33576830U, // V_SET0 + 33576830U, // V_SET0B + 33576830U, // V_SET0H + 4480735U, // V_SETALLONES + 4480735U, // V_SETALLONESB + 4480735U, // V_SETALLONESH + 285437U, // WAIT + 281573U, // WRTEE + 282208U, // WRTEEI + 22385U, // XOR + 22385U, // XOR8 + 17452U, // XOR8o + 20275U, // XORI + 20275U, // XORI8 + 22897U, // XORIS + 22897U, // XORIS8 + 17452U, // XORo + 268457014U, // XSABSDP + 21216U, // XSADDDP + 21497U, // XSCMPODP + 21629U, // XSCMPUDP + 21457U, // XSCPSGNDP + 268457543U, // XSCVDPSP + 268458129U, // XSCVDPSXDS + 268458574U, // XSCVDPSXWS + 268458165U, // XSCVDPUXDS + 268458610U, // XSCVDPUXWS + 268456963U, // XSCVSPDP + 268456690U, // XSCVSXDDP + 268456712U, // XSCVUXDDP + 21639U, // XSDIVDP + 2189447864U, // XSMADDADP + 2189448123U, // XSMADDMDP + 21699U, // XSMAXDP + 21479U, // XSMINDP + 2189447818U, // XSMSUBADP + 2189448077U, // XSMSUBMDP + 21347U, // XSMULDP + 268456994U, // XSNABSDP + 268456785U, // XSNEGDP + 2189447840U, // XSNMADDADP + 2189448099U, // XSNMADDMDP + 2189447794U, // XSNMSUBADP + 2189448053U, // XSNMSUBMDP + 268455707U, // XSRDPI + 268454460U, // XSRDPIC + 268456223U, // XSRDPIM + 268457307U, // XSRDPIP + 268460803U, // XSRDPIZ + 268456745U, // XSREDP + 268456761U, // XSRSQRTEDP + 268457043U, // XSSQRTDP + 21198U, // XSSUBDP + 21648U, // XSTDIVDP + 268457053U, // XSTSQRTDP + 268457023U, // XVABSDP + 268457592U, // XVABSSP + 21225U, // XVADDDP + 21941U, // XVADDSP + 21527U, // XVCMPEQDP + 17306U, // XVCMPEQDPo + 22107U, // XVCMPEQSP + 17392U, // XVCMPEQSPo + 21278U, // XVCMPGEDP + 17294U, // XVCMPGEDPo + 21972U, // XVCMPGESP + 17380U, // XVCMPGESPo + 21576U, // XVCMPGTDP + 17318U, // XVCMPGTDPo + 22145U, // XVCMPGTSP + 17411U, // XVCMPGTSPo + 21468U, // XVCPSGNDP + 22067U, // XVCPSGNSP + 268457553U, // XVCVDPSP + 268458141U, // XVCVDPSXDS + 268458586U, // XVCVDPSXWS + 268458177U, // XVCVDPUXDS + 268458622U, // XVCVDPUXWS + 268456973U, // XVCVSPDP + 268458153U, // XVCVSPSXDS + 268458598U, // XVCVSPSXWS + 268458189U, // XVCVSPUXDS + 268458634U, // XVCVSPUXWS + 268456701U, // XVCVSXDDP + 268457406U, // XVCVSXDSP + 268457133U, // XVCVSXWDP + 268457652U, // XVCVSXWSP + 268456723U, // XVCVUXDDP + 268457417U, // XVCVUXDSP + 268457144U, // XVCVUXWDP + 268457663U, // XVCVUXWSP + 21668U, // XVDIVDP + 22187U, // XVDIVSP + 2189447875U, // XVMADDADP + 2189448609U, // XVMADDASP + 2189448134U, // XVMADDMDP + 2189448744U, // XVMADDMSP + 21708U, // XVMAXDP + 22218U, // XVMAXSP + 21488U, // XVMINDP + 22078U, // XVMINSP + 2189447829U, // XVMSUBADP + 2189448586U, // XVMSUBASP + 2189448088U, // XVMSUBMDP + 2189448721U, // XVMSUBMSP + 21356U, // XVMULDP + 22012U, // XVMULSP + 268457004U, // XVNABSDP + 268457582U, // XVNABSSP + 268456794U, // XVNEGDP + 268457459U, // XVNEGSP + 2189447852U, // XVNMADDADP + 2189448597U, // XVNMADDASP + 2189448111U, // XVNMADDMDP + 2189448732U, // XVNMADDMSP + 2189447806U, // XVNMSUBADP + 2189448574U, // XVNMSUBASP + 2189448065U, // XVNMSUBMDP + 2189448709U, // XVNMSUBMSP + 268455715U, // XVRDPI + 268454469U, // XVRDPIC + 268456232U, // XVRDPIM + 268457316U, // XVRDPIP + 268460812U, // XVRDPIZ + 268456753U, // XVREDP + 268457439U, // XVRESP + 268455723U, // XVRSPI + 268454478U, // XVRSPIC + 268456241U, // XVRSPIM + 268457325U, // XVRSPIP + 268460821U, // XVRSPIZ + 268456773U, // XVRSQRTEDP + 268457447U, // XVRSQRTESP + 268457075U, // XVSQRTDP + 268457623U, // XVSQRTSP + 21207U, // XVSUBDP + 21932U, // XVSUBSP + 21658U, // XVTDIVDP + 22177U, // XVTDIVSP + 268457064U, // XVTSQRTDP + 268457612U, // XVTSQRTSP + 19249U, // XXLAND + 18943U, // XXLANDC + 23557U, // XXLEQV + 19257U, // XXLNAND + 22348U, // XXLNOR + 22341U, // XXLOR + 19044U, // XXLORC + 22341U, // XXLORf + 22382U, // XXLXOR + 23960U, // XXMRGHW + 24002U, // XXMRGLW + 20010U, // XXPERMDI + 20577U, // XXSEL + 20309U, // XXSLDWI + 24357U, // XXSPLTW + 150005U, // gBC + 149203U, // gBCA + 153522U, // gBCCTR + 151663U, // gBCCTRL + 151601U, // gBCL + 149497U, // gBCLA + 153388U, // gBCLR + 151656U, // gBCLRL + 0U + }; + + static const uint16_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 0U, // ADD4 + 0U, // ADD4TLS + 0U, // ADD4o + 0U, // ADD8 + 0U, // ADD8TLS + 0U, // ADD8TLS_ + 0U, // ADD8o + 0U, // ADDC + 0U, // ADDC8 + 0U, // ADDC8o + 0U, // ADDCo + 0U, // ADDE + 0U, // ADDE8 + 0U, // ADDE8o + 0U, // ADDEo + 1U, // ADDI + 1U, // ADDI8 + 1U, // ADDIC + 1U, // ADDIC8 + 1U, // ADDICo + 1U, // ADDIS + 1U, // ADDIS8 + 0U, // ADDISdtprelHA + 0U, // ADDISdtprelHA32 + 0U, // ADDISgotTprelHA + 0U, // ADDIStlsgdHA + 0U, // ADDIStlsldHA + 0U, // ADDIStocHA + 0U, // ADDIdtprelL + 0U, // ADDIdtprelL32 + 0U, // ADDItlsgdL + 0U, // ADDItlsgdL32 + 0U, // ADDItlsgdLADDR + 0U, // ADDItlsgdLADDR32 + 0U, // ADDItlsldL + 0U, // ADDItlsldL32 + 0U, // ADDItlsldLADDR + 0U, // ADDItlsldLADDR32 + 0U, // ADDItocL + 0U, // ADDME + 0U, // ADDME8 + 0U, // ADDME8o + 0U, // ADDMEo + 0U, // ADDZE + 0U, // ADDZE8 + 0U, // ADDZE8o + 0U, // ADDZEo + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND + 0U, // AND8 + 0U, // AND8o + 0U, // ANDC + 0U, // ANDC8 + 0U, // ANDC8o + 0U, // ANDCo + 2U, // ANDISo + 2U, // ANDISo8 + 2U, // ANDIo + 2U, // ANDIo8 + 0U, // ANDIo_1_EQ_BIT + 0U, // ANDIo_1_EQ_BIT8 + 0U, // ANDIo_1_GT_BIT + 0U, // ANDIo_1_GT_BIT8 + 0U, // ANDo + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // ATTN + 0U, // B + 0U, // BA + 0U, // BC + 0U, // BCC + 0U, // BCCA + 0U, // BCCCTR + 0U, // BCCCTR8 + 0U, // BCCCTRL + 0U, // BCCCTRL8 + 0U, // BCCL + 0U, // BCCLA + 0U, // BCCLR + 0U, // BCCLRL + 0U, // BCCTR + 0U, // BCCTR8 + 0U, // BCCTR8n + 0U, // BCCTRL + 0U, // BCCTRL8 + 0U, // BCCTRL8n + 0U, // BCCTRLn + 0U, // BCCTRn + 0U, // BCL + 0U, // BCLR + 0U, // BCLRL + 0U, // BCLRLn + 0U, // BCLRn + 0U, // BCLalways + 0U, // BCLn + 0U, // BCTR + 0U, // BCTR8 + 0U, // BCTRL + 0U, // BCTRL8 + 0U, // BCTRL8_LDinto_toc + 0U, // BCn + 0U, // BDNZ + 0U, // BDNZ8 + 0U, // BDNZA + 0U, // BDNZAm + 0U, // BDNZAp + 0U, // BDNZL + 0U, // BDNZLA + 0U, // BDNZLAm + 0U, // BDNZLAp + 0U, // BDNZLR + 0U, // BDNZLR8 + 0U, // BDNZLRL + 0U, // BDNZLRLm + 0U, // BDNZLRLp + 0U, // BDNZLRm + 0U, // BDNZLRp + 0U, // BDNZLm + 0U, // BDNZLp + 0U, // BDNZm + 0U, // BDNZp + 0U, // BDZ + 0U, // BDZ8 + 0U, // BDZA + 0U, // BDZAm + 0U, // BDZAp + 0U, // BDZL + 0U, // BDZLA + 0U, // BDZLAm + 0U, // BDZLAp + 0U, // BDZLR + 0U, // BDZLR8 + 0U, // BDZLRL + 0U, // BDZLRLm + 0U, // BDZLRLp + 0U, // BDZLRm + 0U, // BDZLRp + 0U, // BDZLm + 0U, // BDZLp + 0U, // BDZm + 0U, // BDZp + 0U, // BL + 0U, // BL8 + 0U, // BL8_NOP + 0U, // BL8_NOP_TLS + 0U, // BL8_TLS + 0U, // BL8_TLS_ + 0U, // BLA + 0U, // BLA8 + 0U, // BLA8_NOP + 0U, // BLR + 0U, // BLR8 + 0U, // BLRL + 0U, // BL_TLS + 0U, // BRINC + 19U, // CLRLSLDI + 19U, // CLRLSLDIo + 52U, // CLRLSLWI + 52U, // CLRLSLWIo + 3U, // CLRRDI + 3U, // CLRRDIo + 4U, // CLRRWI + 4U, // CLRRWIo + 0U, // CMPB + 0U, // CMPB8 + 0U, // CMPD + 1U, // CMPDI + 0U, // CMPLD + 2U, // CMPLDI + 0U, // CMPLW + 2U, // CMPLWI + 0U, // CMPW + 1U, // CMPWI + 0U, // CNTLZD + 0U, // CNTLZDo + 0U, // CNTLZW + 0U, // CNTLZW8 + 0U, // CNTLZW8o + 0U, // CNTLZWo + 0U, // CR6SET + 0U, // CR6UNSET + 0U, // CRAND + 0U, // CRANDC + 0U, // CREQV + 0U, // CRNAND + 0U, // CRNOR + 0U, // CROR + 0U, // CRORC + 5U, // CRSET + 5U, // CRUNSET + 0U, // CRXOR + 0U, // DCBA + 0U, // DCBF + 0U, // DCBI + 0U, // DCBST + 0U, // DCBT + 0U, // DCBTST + 0U, // DCBZ + 0U, // DCBZL + 0U, // DCCCI + 0U, // DIVD + 0U, // DIVDU + 0U, // DIVDUo + 0U, // DIVDo + 0U, // DIVW + 0U, // DIVWU + 0U, // DIVWUo + 0U, // DIVWo + 0U, // DSS + 0U, // DSSALL + 0U, // DST + 0U, // DST64 + 0U, // DSTST + 0U, // DSTST64 + 0U, // DSTSTT + 0U, // DSTSTT64 + 0U, // DSTT + 0U, // DSTT64 + 0U, // DYNALLOC + 0U, // DYNALLOC8 + 0U, // EH_SjLj_LongJmp32 + 0U, // EH_SjLj_LongJmp64 + 0U, // EH_SjLj_SetJmp32 + 0U, // EH_SjLj_SetJmp64 + 0U, // EH_SjLj_Setup + 0U, // EQV + 0U, // EQV8 + 0U, // EQV8o + 0U, // EQVo + 0U, // EVABS + 0U, // EVADDIW + 0U, // EVADDSMIAAW + 0U, // EVADDSSIAAW + 0U, // EVADDUMIAAW + 0U, // EVADDUSIAAW + 0U, // EVADDW + 0U, // EVAND + 0U, // EVANDC + 0U, // EVCMPEQ + 0U, // EVCMPGTS + 0U, // EVCMPGTU + 0U, // EVCMPLTS + 0U, // EVCMPLTU + 0U, // EVCNTLSW + 0U, // EVCNTLZW + 0U, // EVDIVWS + 0U, // EVDIVWU + 0U, // EVEQV + 0U, // EVEXTSB + 0U, // EVEXTSH + 0U, // EVLDD + 0U, // EVLDDX + 0U, // EVLDH + 0U, // EVLDHX + 0U, // EVLDW + 0U, // EVLDWX + 0U, // EVLHHESPLAT + 0U, // EVLHHESPLATX + 0U, // EVLHHOSSPLAT + 0U, // EVLHHOSSPLATX + 0U, // EVLHHOUSPLAT + 0U, // EVLHHOUSPLATX + 0U, // EVLWHE + 0U, // EVLWHEX + 0U, // EVLWHOS + 0U, // EVLWHOSX + 0U, // EVLWHOU + 0U, // EVLWHOUX + 0U, // EVLWHSPLAT + 0U, // EVLWHSPLATX + 0U, // EVLWWSPLAT + 0U, // EVLWWSPLATX + 0U, // EVMERGEHI + 0U, // EVMERGEHILO + 0U, // EVMERGELO + 0U, // EVMERGELOHI + 0U, // EVMHEGSMFAA + 0U, // EVMHEGSMFAN + 0U, // EVMHEGSMIAA + 0U, // EVMHEGSMIAN + 0U, // EVMHEGUMIAA + 0U, // EVMHEGUMIAN + 0U, // EVMHESMF + 0U, // EVMHESMFA + 0U, // EVMHESMFAAW + 0U, // EVMHESMFANW + 0U, // EVMHESMI + 0U, // EVMHESMIA + 0U, // EVMHESMIAAW + 0U, // EVMHESMIANW + 0U, // EVMHESSF + 0U, // EVMHESSFA + 0U, // EVMHESSFAAW + 0U, // EVMHESSFANW + 0U, // EVMHESSIAAW + 0U, // EVMHESSIANW + 0U, // EVMHEUMI + 0U, // EVMHEUMIA + 0U, // EVMHEUMIAAW + 0U, // EVMHEUMIANW + 0U, // EVMHEUSIAAW + 0U, // EVMHEUSIANW + 0U, // EVMHOGSMFAA + 0U, // EVMHOGSMFAN + 0U, // EVMHOGSMIAA + 0U, // EVMHOGSMIAN + 0U, // EVMHOGUMIAA + 0U, // EVMHOGUMIAN + 0U, // EVMHOSMF + 0U, // EVMHOSMFA + 0U, // EVMHOSMFAAW + 0U, // EVMHOSMFANW + 0U, // EVMHOSMI + 0U, // EVMHOSMIA + 0U, // EVMHOSMIAAW + 0U, // EVMHOSMIANW + 0U, // EVMHOSSF + 0U, // EVMHOSSFA + 0U, // EVMHOSSFAAW + 0U, // EVMHOSSFANW + 0U, // EVMHOSSIAAW + 0U, // EVMHOSSIANW + 0U, // EVMHOUMI + 0U, // EVMHOUMIA + 0U, // EVMHOUMIAAW + 0U, // EVMHOUMIANW + 0U, // EVMHOUSIAAW + 0U, // EVMHOUSIANW + 0U, // EVMRA + 0U, // EVMWHSMF + 0U, // EVMWHSMFA + 0U, // EVMWHSMI + 0U, // EVMWHSMIA + 0U, // EVMWHSSF + 0U, // EVMWHSSFA + 0U, // EVMWHUMI + 0U, // EVMWHUMIA + 0U, // EVMWLSMIAAW + 0U, // EVMWLSMIANW + 0U, // EVMWLSSIAAW + 0U, // EVMWLSSIANW + 0U, // EVMWLUMI + 0U, // EVMWLUMIA + 0U, // EVMWLUMIAAW + 0U, // EVMWLUMIANW + 0U, // EVMWLUSIAAW + 0U, // EVMWLUSIANW + 0U, // EVMWSMF + 0U, // EVMWSMFA + 0U, // EVMWSMFAA + 0U, // EVMWSMFAN + 0U, // EVMWSMI + 0U, // EVMWSMIA + 0U, // EVMWSMIAA + 0U, // EVMWSMIAN + 0U, // EVMWSSF + 0U, // EVMWSSFA + 0U, // EVMWSSFAA + 0U, // EVMWSSFAN + 0U, // EVMWUMI + 0U, // EVMWUMIA + 0U, // EVMWUMIAA + 0U, // EVMWUMIAN + 0U, // EVNAND + 0U, // EVNEG + 0U, // EVNOR + 0U, // EVOR + 0U, // EVORC + 0U, // EVRLW + 4U, // EVRLWI + 0U, // EVRNDW + 0U, // EVSLW + 4U, // EVSLWI + 0U, // EVSPLATFI + 0U, // EVSPLATI + 4U, // EVSRWIS + 4U, // EVSRWIU + 0U, // EVSRWS + 0U, // EVSRWU + 0U, // EVSTDD + 0U, // EVSTDDX + 0U, // EVSTDH + 0U, // EVSTDHX + 0U, // EVSTDW + 0U, // EVSTDWX + 0U, // EVSTWHE + 0U, // EVSTWHEX + 0U, // EVSTWHO + 0U, // EVSTWHOX + 0U, // EVSTWWE + 0U, // EVSTWWEX + 0U, // EVSTWWO + 0U, // EVSTWWOX + 0U, // EVSUBFSMIAAW + 0U, // EVSUBFSSIAAW + 0U, // EVSUBFUMIAAW + 0U, // EVSUBFUSIAAW + 0U, // EVSUBFW + 0U, // EVSUBIFW + 0U, // EVXOR + 19U, // EXTLDI + 19U, // EXTLDIo + 52U, // EXTLWI + 52U, // EXTLWIo + 19U, // EXTRDI + 19U, // EXTRDIo + 52U, // EXTRWI + 52U, // EXTRWIo + 0U, // EXTSB + 0U, // EXTSB8 + 0U, // EXTSB8_32_64 + 0U, // EXTSB8o + 0U, // EXTSBo + 0U, // EXTSH + 0U, // EXTSH8 + 0U, // EXTSH8_32_64 + 0U, // EXTSH8o + 0U, // EXTSHo + 0U, // EXTSW + 0U, // EXTSW_32_64 + 0U, // EXTSW_32_64o + 0U, // EXTSWo + 0U, // EnforceIEIO + 0U, // FABSD + 0U, // FABSDo + 0U, // FABSS + 0U, // FABSSo + 0U, // FADD + 0U, // FADDS + 0U, // FADDSo + 0U, // FADDo + 0U, // FADDrtz + 0U, // FCFID + 0U, // FCFIDS + 0U, // FCFIDSo + 0U, // FCFIDU + 0U, // FCFIDUS + 0U, // FCFIDUSo + 0U, // FCFIDUo + 0U, // FCFIDo + 0U, // FCMPUD + 0U, // FCMPUS + 0U, // FCPSGND + 0U, // FCPSGNDo + 0U, // FCPSGNS + 0U, // FCPSGNSo + 0U, // FCTID + 0U, // FCTIDUZ + 0U, // FCTIDUZo + 0U, // FCTIDZ + 0U, // FCTIDZo + 0U, // FCTIDo + 0U, // FCTIW + 0U, // FCTIWUZ + 0U, // FCTIWUZo + 0U, // FCTIWZ + 0U, // FCTIWZo + 0U, // FCTIWo + 0U, // FDIV + 0U, // FDIVS + 0U, // FDIVSo + 0U, // FDIVo + 80U, // FMADD + 80U, // FMADDS + 80U, // FMADDSo + 80U, // FMADDo + 0U, // FMR + 0U, // FMRo + 80U, // FMSUB + 80U, // FMSUBS + 80U, // FMSUBSo + 80U, // FMSUBo + 0U, // FMUL + 0U, // FMULS + 0U, // FMULSo + 0U, // FMULo + 0U, // FNABSD + 0U, // FNABSDo + 0U, // FNABSS + 0U, // FNABSSo + 0U, // FNEGD + 0U, // FNEGDo + 0U, // FNEGS + 0U, // FNEGSo + 80U, // FNMADD + 80U, // FNMADDS + 80U, // FNMADDSo + 80U, // FNMADDo + 80U, // FNMSUB + 80U, // FNMSUBS + 80U, // FNMSUBSo + 80U, // FNMSUBo + 0U, // FRE + 0U, // FRES + 0U, // FRESo + 0U, // FREo + 0U, // FRIMD + 0U, // FRIMDo + 0U, // FRIMS + 0U, // FRIMSo + 0U, // FRIND + 0U, // FRINDo + 0U, // FRINS + 0U, // FRINSo + 0U, // FRIPD + 0U, // FRIPDo + 0U, // FRIPS + 0U, // FRIPSo + 0U, // FRIZD + 0U, // FRIZDo + 0U, // FRIZS + 0U, // FRIZSo + 0U, // FRSP + 0U, // FRSPo + 0U, // FRSQRTE + 0U, // FRSQRTES + 0U, // FRSQRTESo + 0U, // FRSQRTEo + 80U, // FSELD + 80U, // FSELDo + 80U, // FSELS + 80U, // FSELSo + 0U, // FSQRT + 0U, // FSQRTS + 0U, // FSQRTSo + 0U, // FSQRTo + 0U, // FSUB + 0U, // FSUBS + 0U, // FSUBSo + 0U, // FSUBo + 0U, // GETtlsADDR + 0U, // GETtlsADDR32 + 0U, // GETtlsldADDR + 0U, // GETtlsldADDR32 + 0U, // ICBI + 0U, // ICBT + 0U, // ICCCI + 52U, // INSLWI + 52U, // INSLWIo + 19U, // INSRDI + 19U, // INSRDIo + 52U, // INSRWI + 52U, // INSRWIo + 80U, // ISEL + 80U, // ISEL8 + 0U, // ISYNC + 0U, // LA + 0U, // LAx + 0U, // LBZ + 0U, // LBZ8 + 0U, // LBZCIX + 0U, // LBZU + 0U, // LBZU8 + 0U, // LBZUX + 0U, // LBZUX8 + 0U, // LBZX + 0U, // LBZX8 + 0U, // LD + 0U, // LDARX + 0U, // LDBRX + 0U, // LDCIX + 0U, // LDU + 0U, // LDUX + 0U, // LDX + 0U, // LDgotTprelL + 0U, // LDgotTprelL32 + 0U, // LDtoc + 0U, // LDtocBA + 0U, // LDtocCPT + 0U, // LDtocJTI + 0U, // LDtocL + 0U, // LFD + 0U, // LFDU + 0U, // LFDUX + 0U, // LFDX + 0U, // LFIWAX + 0U, // LFIWZX + 0U, // LFS + 0U, // LFSU + 0U, // LFSUX + 0U, // LFSX + 0U, // LHA + 0U, // LHA8 + 0U, // LHAU + 0U, // LHAU8 + 0U, // LHAUX + 0U, // LHAUX8 + 0U, // LHAX + 0U, // LHAX8 + 0U, // LHBRX + 0U, // LHBRX8 + 0U, // LHZ + 0U, // LHZ8 + 0U, // LHZCIX + 0U, // LHZU + 0U, // LHZU8 + 0U, // LHZUX + 0U, // LHZUX8 + 0U, // LHZX + 0U, // LHZX8 + 0U, // LI + 0U, // LI8 + 0U, // LIS + 0U, // LIS8 + 0U, // LMW + 4U, // LSWI + 0U, // LVEBX + 0U, // LVEHX + 0U, // LVEWX + 0U, // LVSL + 0U, // LVSR + 0U, // LVX + 0U, // LVXL + 0U, // LWA + 0U, // LWARX + 0U, // LWAUX + 0U, // LWAX + 0U, // LWAX_32 + 0U, // LWA_32 + 0U, // LWBRX + 0U, // LWBRX8 + 0U, // LWZ + 0U, // LWZ8 + 0U, // LWZCIX + 0U, // LWZU + 0U, // LWZU8 + 0U, // LWZUX + 0U, // LWZUX8 + 0U, // LWZX + 0U, // LWZX8 + 0U, // LWZtoc + 0U, // LXSDX + 0U, // LXVD2X + 0U, // LXVDSX + 0U, // LXVW4X + 0U, // MBAR + 0U, // MCRF + 0U, // MCRFS + 0U, // MFCR + 0U, // MFCR8 + 0U, // MFCTR + 0U, // MFCTR8 + 0U, // MFDCR + 0U, // MFFS + 0U, // MFFSo + 0U, // MFLR + 0U, // MFLR8 + 0U, // MFMSR + 0U, // MFOCRF + 0U, // MFOCRF8 + 0U, // MFSPR + 0U, // MFSR + 0U, // MFSRIN + 0U, // MFTB + 0U, // MFTB8 + 0U, // MFVRSAVE + 0U, // MFVRSAVEv + 0U, // MFVSCR + 0U, // MSYNC + 0U, // MTCRF + 0U, // MTCRF8 + 0U, // MTCTR + 0U, // MTCTR8 + 0U, // MTCTR8loop + 0U, // MTCTRloop + 0U, // MTDCR + 0U, // MTFSB0 + 0U, // MTFSB1 + 80U, // MTFSF + 0U, // MTFSFI + 0U, // MTFSFIo + 0U, // MTFSFb + 80U, // MTFSFo + 0U, // MTLR + 0U, // MTLR8 + 0U, // MTMSR + 0U, // MTMSRD + 0U, // MTOCRF + 0U, // MTOCRF8 + 0U, // MTSPR + 0U, // MTSR + 0U, // MTSRIN + 0U, // MTVRSAVE + 0U, // MTVRSAVEv + 0U, // MTVSCR + 0U, // MULHD + 0U, // MULHDU + 0U, // MULHDUo + 0U, // MULHDo + 0U, // MULHW + 0U, // MULHWU + 0U, // MULHWUo + 0U, // MULHWo + 0U, // MULLD + 0U, // MULLDo + 1U, // MULLI + 1U, // MULLI8 + 0U, // MULLW + 0U, // MULLWo + 0U, // MoveGOTtoLR + 0U, // MovePCtoLR + 0U, // MovePCtoLR8 + 0U, // NAND + 0U, // NAND8 + 0U, // NAND8o + 0U, // NANDo + 0U, // NEG + 0U, // NEG8 + 0U, // NEG8o + 0U, // NEGo + 0U, // NOP + 0U, // NOP_GT_PWR6 + 0U, // NOP_GT_PWR7 + 0U, // NOR + 0U, // NOR8 + 0U, // NOR8o + 0U, // NORo + 0U, // OR + 0U, // OR8 + 0U, // OR8o + 0U, // ORC + 0U, // ORC8 + 0U, // ORC8o + 0U, // ORCo + 2U, // ORI + 2U, // ORI8 + 2U, // ORIS + 2U, // ORIS8 + 0U, // ORo + 0U, // POPCNTD + 0U, // POPCNTW + 0U, // PPC32GOT + 0U, // PPC32PICGOT + 112U, // QVALIGNI + 112U, // QVALIGNIb + 112U, // QVALIGNIs + 6U, // QVESPLATI + 6U, // QVESPLATIb + 6U, // QVESPLATIs + 0U, // QVFABS + 0U, // QVFABSs + 0U, // QVFADD + 0U, // QVFADDS + 0U, // QVFADDSs + 0U, // QVFCFID + 0U, // QVFCFIDS + 0U, // QVFCFIDU + 0U, // QVFCFIDUS + 0U, // QVFCFIDb + 0U, // QVFCMPEQ + 0U, // QVFCMPEQb + 0U, // QVFCMPEQbs + 0U, // QVFCMPGT + 0U, // QVFCMPGTb + 0U, // QVFCMPGTbs + 0U, // QVFCMPLT + 0U, // QVFCMPLTb + 0U, // QVFCMPLTbs + 0U, // QVFCPSGN + 0U, // QVFCPSGNs + 0U, // QVFCTID + 0U, // QVFCTIDU + 0U, // QVFCTIDUZ + 0U, // QVFCTIDZ + 0U, // QVFCTIDb + 0U, // QVFCTIW + 0U, // QVFCTIWU + 0U, // QVFCTIWUZ + 0U, // QVFCTIWZ + 144U, // QVFLOGICAL + 144U, // QVFLOGICALb + 144U, // QVFLOGICALs + 7U, // QVFMADD + 7U, // QVFMADDS + 7U, // QVFMADDSs + 0U, // QVFMR + 0U, // QVFMRb + 0U, // QVFMRs + 7U, // QVFMSUB + 7U, // QVFMSUBS + 7U, // QVFMSUBSs + 0U, // QVFMUL + 0U, // QVFMULS + 0U, // QVFMULSs + 0U, // QVFNABS + 0U, // QVFNABSs + 0U, // QVFNEG + 0U, // QVFNEGs + 7U, // QVFNMADD + 7U, // QVFNMADDS + 7U, // QVFNMADDSs + 7U, // QVFNMSUB + 7U, // QVFNMSUBS + 7U, // QVFNMSUBSs + 80U, // QVFPERM + 80U, // QVFPERMs + 0U, // QVFRE + 0U, // QVFRES + 0U, // QVFRESs + 0U, // QVFRIM + 0U, // QVFRIMs + 0U, // QVFRIN + 0U, // QVFRINs + 0U, // QVFRIP + 0U, // QVFRIPs + 0U, // QVFRIZ + 0U, // QVFRIZs + 0U, // QVFRSP + 0U, // QVFRSPs + 0U, // QVFRSQRTE + 0U, // QVFRSQRTES + 0U, // QVFRSQRTESs + 7U, // QVFSEL + 7U, // QVFSELb + 7U, // QVFSELbb + 7U, // QVFSELbs + 0U, // QVFSUB + 0U, // QVFSUBS + 0U, // QVFSUBSs + 0U, // QVFTSTNAN + 0U, // QVFTSTNANb + 0U, // QVFTSTNANbs + 7U, // QVFXMADD + 7U, // QVFXMADDS + 0U, // QVFXMUL + 0U, // QVFXMULS + 7U, // QVFXXCPNMADD + 7U, // QVFXXCPNMADDS + 7U, // QVFXXMADD + 7U, // QVFXXMADDS + 7U, // QVFXXNPMADD + 7U, // QVFXXNPMADDS + 0U, // QVGPCI + 0U, // QVLFCDUX + 0U, // QVLFCDUXA + 0U, // QVLFCDX + 0U, // QVLFCDXA + 0U, // QVLFCSUX + 0U, // QVLFCSUXA + 0U, // QVLFCSX + 0U, // QVLFCSXA + 0U, // QVLFCSXs + 0U, // QVLFDUX + 0U, // QVLFDUXA + 0U, // QVLFDX + 0U, // QVLFDXA + 0U, // QVLFDXb + 0U, // QVLFIWAX + 0U, // QVLFIWAXA + 0U, // QVLFIWZX + 0U, // QVLFIWZXA + 0U, // QVLFSUX + 0U, // QVLFSUXA + 0U, // QVLFSX + 0U, // QVLFSXA + 0U, // QVLFSXb + 0U, // QVLFSXs + 0U, // QVLPCLDX + 0U, // QVLPCLSX + 0U, // QVLPCLSXint + 0U, // QVLPCRDX + 0U, // QVLPCRSX + 0U, // QVSTFCDUX + 0U, // QVSTFCDUXA + 0U, // QVSTFCDUXI + 0U, // QVSTFCDUXIA + 0U, // QVSTFCDX + 0U, // QVSTFCDXA + 0U, // QVSTFCDXI + 0U, // QVSTFCDXIA + 0U, // QVSTFCSUX + 0U, // QVSTFCSUXA + 0U, // QVSTFCSUXI + 0U, // QVSTFCSUXIA + 0U, // QVSTFCSX + 0U, // QVSTFCSXA + 0U, // QVSTFCSXI + 0U, // QVSTFCSXIA + 0U, // QVSTFCSXs + 0U, // QVSTFDUX + 0U, // QVSTFDUXA + 0U, // QVSTFDUXI + 0U, // QVSTFDUXIA + 0U, // QVSTFDX + 0U, // QVSTFDXA + 0U, // QVSTFDXI + 0U, // QVSTFDXIA + 0U, // QVSTFDXb + 0U, // QVSTFIWX + 0U, // QVSTFIWXA + 0U, // QVSTFSUX + 0U, // QVSTFSUXA + 0U, // QVSTFSUXI + 0U, // QVSTFSUXIA + 0U, // QVSTFSUXs + 0U, // QVSTFSX + 0U, // QVSTFSXA + 0U, // QVSTFSXI + 0U, // QVSTFSXIA + 0U, // QVSTFSXs + 0U, // RESTORE_CR + 0U, // RESTORE_CRBIT + 0U, // RESTORE_VRSAVE + 0U, // RFCI + 0U, // RFDI + 0U, // RFI + 0U, // RFID + 0U, // RFMCI + 16U, // RLDCL + 16U, // RLDCLo + 16U, // RLDCR + 16U, // RLDCRo + 19U, // RLDIC + 19U, // RLDICL + 19U, // RLDICL_32_64 + 19U, // RLDICLo + 19U, // RLDICR + 19U, // RLDICRo + 19U, // RLDICo + 0U, // RLDIMI + 0U, // RLDIMIo + 0U, // RLWIMI + 0U, // RLWIMI8 + 0U, // RLWIMI8o + 0U, // RLWIMIo + 308U, // RLWINM + 308U, // RLWINM8 + 308U, // RLWINM8o + 308U, // RLWINMo + 304U, // RLWNM + 304U, // RLWNM8 + 304U, // RLWNM8o + 304U, // RLWNMo + 3U, // ROTRDI + 3U, // ROTRDIo + 4U, // ROTRWI + 4U, // ROTRWIo + 0U, // ReadTB + 0U, // SC + 0U, // SELECT_CC_F4 + 0U, // SELECT_CC_F8 + 0U, // SELECT_CC_I4 + 0U, // SELECT_CC_I8 + 0U, // SELECT_CC_QBRC + 0U, // SELECT_CC_QFRC + 0U, // SELECT_CC_QSRC + 0U, // SELECT_CC_VRRC + 0U, // SELECT_CC_VSFRC + 0U, // SELECT_CC_VSRC + 0U, // SELECT_F4 + 0U, // SELECT_F8 + 0U, // SELECT_I4 + 0U, // SELECT_I8 + 0U, // SELECT_QBRC + 0U, // SELECT_QFRC + 0U, // SELECT_QSRC + 0U, // SELECT_VRRC + 0U, // SELECT_VSFRC + 0U, // SELECT_VSRC + 0U, // SLBIA + 0U, // SLBIE + 0U, // SLBMFEE + 0U, // SLBMTE + 0U, // SLD + 3U, // SLDI + 3U, // SLDIo + 0U, // SLDo + 0U, // SLW + 0U, // SLW8 + 0U, // SLW8o + 4U, // SLWI + 4U, // SLWIo + 0U, // SLWo + 0U, // SPILL_CR + 0U, // SPILL_CRBIT + 0U, // SPILL_VRSAVE + 0U, // SRAD + 3U, // SRADI + 3U, // SRADIo + 0U, // SRADo + 0U, // SRAW + 4U, // SRAWI + 4U, // SRAWIo + 0U, // SRAWo + 0U, // SRD + 3U, // SRDI + 3U, // SRDIo + 0U, // SRDo + 0U, // SRW + 0U, // SRW8 + 0U, // SRW8o + 4U, // SRWI + 4U, // SRWIo + 0U, // SRWo + 0U, // STB + 0U, // STB8 + 0U, // STBCIX + 0U, // STBU + 0U, // STBU8 + 0U, // STBUX + 0U, // STBUX8 + 0U, // STBX + 0U, // STBX8 + 0U, // STD + 0U, // STDBRX + 0U, // STDCIX + 0U, // STDCX + 0U, // STDU + 0U, // STDUX + 0U, // STDX + 0U, // STFD + 0U, // STFDU + 0U, // STFDUX + 0U, // STFDX + 0U, // STFIWX + 0U, // STFS + 0U, // STFSU + 0U, // STFSUX + 0U, // STFSX + 0U, // STH + 0U, // STH8 + 0U, // STHBRX + 0U, // STHCIX + 0U, // STHU + 0U, // STHU8 + 0U, // STHUX + 0U, // STHUX8 + 0U, // STHX + 0U, // STHX8 + 0U, // STMW + 4U, // STSWI + 0U, // STVEBX + 0U, // STVEHX + 0U, // STVEWX + 0U, // STVX + 0U, // STVXL + 0U, // STW + 0U, // STW8 + 0U, // STWBRX + 0U, // STWCIX + 0U, // STWCX + 0U, // STWU + 0U, // STWU8 + 0U, // STWUX + 0U, // STWUX8 + 0U, // STWX + 0U, // STWX8 + 0U, // STXSDX + 0U, // STXVD2X + 0U, // STXVW4X + 0U, // SUBF + 0U, // SUBF8 + 0U, // SUBF8o + 0U, // SUBFC + 0U, // SUBFC8 + 0U, // SUBFC8o + 0U, // SUBFCo + 0U, // SUBFE + 0U, // SUBFE8 + 0U, // SUBFE8o + 0U, // SUBFEo + 1U, // SUBFIC + 1U, // SUBFIC8 + 0U, // SUBFME + 0U, // SUBFME8 + 0U, // SUBFME8o + 0U, // SUBFMEo + 0U, // SUBFZE + 0U, // SUBFZE8 + 0U, // SUBFZE8o + 0U, // SUBFZEo + 0U, // SUBFo + 1U, // SUBI + 1U, // SUBIC + 1U, // SUBICo + 1U, // SUBIS + 0U, // SYNC + 0U, // TAILB + 0U, // TAILB8 + 0U, // TAILBA + 0U, // TAILBA8 + 0U, // TAILBCTR + 0U, // TAILBCTR8 + 0U, // TCRETURNai + 0U, // TCRETURNai8 + 0U, // TCRETURNdi + 0U, // TCRETURNdi8 + 0U, // TCRETURNri + 0U, // TCRETURNri8 + 0U, // TD + 1U, // TDI + 0U, // TLBIA + 0U, // TLBIE + 0U, // TLBIEL + 0U, // TLBIVAX + 0U, // TLBLD + 0U, // TLBLI + 0U, // TLBRE + 0U, // TLBRE2 + 0U, // TLBSX + 0U, // TLBSX2 + 0U, // TLBSX2D + 0U, // TLBSYNC + 0U, // TLBWE + 0U, // TLBWE2 + 0U, // TRAP + 0U, // TW + 1U, // TWI + 0U, // UPDATE_VRSAVE + 0U, // UpdateGBR + 0U, // VADDCUW + 0U, // VADDFP + 0U, // VADDSBS + 0U, // VADDSHS + 0U, // VADDSWS + 0U, // VADDUBM + 0U, // VADDUBS + 0U, // VADDUDM + 0U, // VADDUHM + 0U, // VADDUHS + 0U, // VADDUWM + 0U, // VADDUWS + 0U, // VAND + 0U, // VANDC + 0U, // VAVGSB + 0U, // VAVGSH + 0U, // VAVGSW + 0U, // VAVGUB + 0U, // VAVGUH + 0U, // VAVGUW + 0U, // VCFSX + 0U, // VCFSX_0 + 0U, // VCFUX + 0U, // VCFUX_0 + 0U, // VCLZB + 0U, // VCLZD + 0U, // VCLZH + 0U, // VCLZW + 0U, // VCMPBFP + 0U, // VCMPBFPo + 0U, // VCMPEQFP + 0U, // VCMPEQFPo + 0U, // VCMPEQUB + 0U, // VCMPEQUBo + 0U, // VCMPEQUD + 0U, // VCMPEQUDo + 0U, // VCMPEQUH + 0U, // VCMPEQUHo + 0U, // VCMPEQUW + 0U, // VCMPEQUWo + 0U, // VCMPGEFP + 0U, // VCMPGEFPo + 0U, // VCMPGTFP + 0U, // VCMPGTFPo + 0U, // VCMPGTSB + 0U, // VCMPGTSBo + 0U, // VCMPGTSD + 0U, // VCMPGTSDo + 0U, // VCMPGTSH + 0U, // VCMPGTSHo + 0U, // VCMPGTSW + 0U, // VCMPGTSWo + 0U, // VCMPGTUB + 0U, // VCMPGTUBo + 0U, // VCMPGTUD + 0U, // VCMPGTUDo + 0U, // VCMPGTUH + 0U, // VCMPGTUHo + 0U, // VCMPGTUW + 0U, // VCMPGTUWo + 0U, // VCTSXS + 0U, // VCTSXS_0 + 0U, // VCTUXS + 0U, // VCTUXS_0 + 0U, // VEQV + 0U, // VEXPTEFP + 0U, // VLOGEFP + 80U, // VMADDFP + 0U, // VMAXFP + 0U, // VMAXSB + 0U, // VMAXSD + 0U, // VMAXSH + 0U, // VMAXSW + 0U, // VMAXUB + 0U, // VMAXUD + 0U, // VMAXUH + 0U, // VMAXUW + 80U, // VMHADDSHS + 80U, // VMHRADDSHS + 0U, // VMIDUD + 0U, // VMINFP + 0U, // VMINSB + 0U, // VMINSD + 0U, // VMINSH + 0U, // VMINSW + 0U, // VMINUB + 0U, // VMINUH + 0U, // VMINUW + 80U, // VMLADDUHM + 0U, // VMRGHB + 0U, // VMRGHH + 0U, // VMRGHW + 0U, // VMRGLB + 0U, // VMRGLH + 0U, // VMRGLW + 80U, // VMSUMMBM + 80U, // VMSUMSHM + 80U, // VMSUMSHS + 80U, // VMSUMUBM + 80U, // VMSUMUHM + 80U, // VMSUMUHS + 0U, // VMULESB + 0U, // VMULESH + 0U, // VMULESW + 0U, // VMULEUB + 0U, // VMULEUH + 0U, // VMULEUW + 0U, // VMULOSB + 0U, // VMULOSH + 0U, // VMULOSW + 0U, // VMULOUB + 0U, // VMULOUH + 0U, // VMULOUW + 0U, // VMULUWM + 0U, // VNAND + 80U, // VNMSUBFP + 0U, // VNOR + 0U, // VOR + 0U, // VORC + 80U, // VPERM + 0U, // VPKPX + 0U, // VPKSHSS + 0U, // VPKSHUS + 0U, // VPKSWSS + 0U, // VPKSWUS + 0U, // VPKUHUM + 0U, // VPKUHUS + 0U, // VPKUWUM + 0U, // VPKUWUS + 0U, // VPOPCNTB + 0U, // VPOPCNTD + 0U, // VPOPCNTH + 0U, // VPOPCNTW + 0U, // VREFP + 0U, // VRFIM + 0U, // VRFIN + 0U, // VRFIP + 0U, // VRFIZ + 0U, // VRLB + 0U, // VRLD + 0U, // VRLH + 0U, // VRLW + 0U, // VRSQRTEFP + 80U, // VSEL + 0U, // VSL + 0U, // VSLB + 0U, // VSLD + 48U, // VSLDOI + 0U, // VSLH + 0U, // VSLO + 0U, // VSLW + 0U, // VSPLTB + 0U, // VSPLTH + 0U, // VSPLTISB + 0U, // VSPLTISH + 0U, // VSPLTISW + 0U, // VSPLTW + 0U, // VSR + 0U, // VSRAB + 0U, // VSRAD + 0U, // VSRAH + 0U, // VSRAW + 0U, // VSRB + 0U, // VSRD + 0U, // VSRH + 0U, // VSRO + 0U, // VSRW + 0U, // VSUBCUW + 0U, // VSUBFP + 0U, // VSUBSBS + 0U, // VSUBSHS + 0U, // VSUBSWS + 0U, // VSUBUBM + 0U, // VSUBUBS + 0U, // VSUBUDM + 0U, // VSUBUHM + 0U, // VSUBUHS + 0U, // VSUBUWM + 0U, // VSUBUWS + 0U, // VSUM2SWS + 0U, // VSUM4SBS + 0U, // VSUM4SHS + 0U, // VSUM4UBS + 0U, // VSUMSWS + 0U, // VUPKHPX + 0U, // VUPKHSB + 0U, // VUPKHSH + 0U, // VUPKLPX + 0U, // VUPKLSB + 0U, // VUPKLSH + 0U, // VXOR + 5U, // V_SET0 + 5U, // V_SET0B + 5U, // V_SET0H + 0U, // V_SETALLONES + 0U, // V_SETALLONESB + 0U, // V_SETALLONESH + 0U, // WAIT + 0U, // WRTEE + 0U, // WRTEEI + 0U, // XOR + 0U, // XOR8 + 0U, // XOR8o + 2U, // XORI + 2U, // XORI8 + 2U, // XORIS + 2U, // XORIS8 + 0U, // XORo + 0U, // XSABSDP + 0U, // XSADDDP + 0U, // XSCMPODP + 0U, // XSCMPUDP + 0U, // XSCPSGNDP + 0U, // XSCVDPSP + 0U, // XSCVDPSXDS + 0U, // XSCVDPSXWS + 0U, // XSCVDPUXDS + 0U, // XSCVDPUXWS + 0U, // XSCVSPDP + 0U, // XSCVSXDDP + 0U, // XSCVUXDDP + 0U, // XSDIVDP + 0U, // XSMADDADP + 0U, // XSMADDMDP + 0U, // XSMAXDP + 0U, // XSMINDP + 0U, // XSMSUBADP + 0U, // XSMSUBMDP + 0U, // XSMULDP + 0U, // XSNABSDP + 0U, // XSNEGDP + 0U, // XSNMADDADP + 0U, // XSNMADDMDP + 0U, // XSNMSUBADP + 0U, // XSNMSUBMDP + 0U, // XSRDPI + 0U, // XSRDPIC + 0U, // XSRDPIM + 0U, // XSRDPIP + 0U, // XSRDPIZ + 0U, // XSREDP + 0U, // XSRSQRTEDP + 0U, // XSSQRTDP + 0U, // XSSUBDP + 0U, // XSTDIVDP + 0U, // XSTSQRTDP + 0U, // XVABSDP + 0U, // XVABSSP + 0U, // XVADDDP + 0U, // XVADDSP + 0U, // XVCMPEQDP + 0U, // XVCMPEQDPo + 0U, // XVCMPEQSP + 0U, // XVCMPEQSPo + 0U, // XVCMPGEDP + 0U, // XVCMPGEDPo + 0U, // XVCMPGESP + 0U, // XVCMPGESPo + 0U, // XVCMPGTDP + 0U, // XVCMPGTDPo + 0U, // XVCMPGTSP + 0U, // XVCMPGTSPo + 0U, // XVCPSGNDP + 0U, // XVCPSGNSP + 0U, // XVCVDPSP + 0U, // XVCVDPSXDS + 0U, // XVCVDPSXWS + 0U, // XVCVDPUXDS + 0U, // XVCVDPUXWS + 0U, // XVCVSPDP + 0U, // XVCVSPSXDS + 0U, // XVCVSPSXWS + 0U, // XVCVSPUXDS + 0U, // XVCVSPUXWS + 0U, // XVCVSXDDP + 0U, // XVCVSXDSP + 0U, // XVCVSXWDP + 0U, // XVCVSXWSP + 0U, // XVCVUXDDP + 0U, // XVCVUXDSP + 0U, // XVCVUXWDP + 0U, // XVCVUXWSP + 0U, // XVDIVDP + 0U, // XVDIVSP + 0U, // XVMADDADP + 0U, // XVMADDASP + 0U, // XVMADDMDP + 0U, // XVMADDMSP + 0U, // XVMAXDP + 0U, // XVMAXSP + 0U, // XVMINDP + 0U, // XVMINSP + 0U, // XVMSUBADP + 0U, // XVMSUBASP + 0U, // XVMSUBMDP + 0U, // XVMSUBMSP + 0U, // XVMULDP + 0U, // XVMULSP + 0U, // XVNABSDP + 0U, // XVNABSSP + 0U, // XVNEGDP + 0U, // XVNEGSP + 0U, // XVNMADDADP + 0U, // XVNMADDASP + 0U, // XVNMADDMDP + 0U, // XVNMADDMSP + 0U, // XVNMSUBADP + 0U, // XVNMSUBASP + 0U, // XVNMSUBMDP + 0U, // XVNMSUBMSP + 0U, // XVRDPI + 0U, // XVRDPIC + 0U, // XVRDPIM + 0U, // XVRDPIP + 0U, // XVRDPIZ + 0U, // XVREDP + 0U, // XVRESP + 0U, // XVRSPI + 0U, // XVRSPIC + 0U, // XVRSPIM + 0U, // XVRSPIP + 0U, // XVRSPIZ + 0U, // XVRSQRTEDP + 0U, // XVRSQRTESP + 0U, // XVSQRTDP + 0U, // XVSQRTSP + 0U, // XVSUBDP + 0U, // XVSUBSP + 0U, // XVTDIVDP + 0U, // XVTDIVSP + 0U, // XVTSQRTDP + 0U, // XVTSQRTSP + 0U, // XXLAND + 0U, // XXLANDC + 0U, // XXLEQV + 0U, // XXLNAND + 0U, // XXLNOR + 0U, // XXLOR + 0U, // XXLORC + 0U, // XXLORf + 0U, // XXLXOR + 0U, // XXMRGHW + 0U, // XXMRGLW + 112U, // XXPERMDI + 80U, // XXSEL + 112U, // XXSLDWI + 6U, // XXSPLTW + 8U, // gBC + 9U, // gBCA + 0U, // gBCCTR + 0U, // gBCCTRL + 8U, // gBCL + 9U, // gBCLA + 0U, // gBCLR + 0U, // gBCLRL + 0U + }; + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, + /* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0, + /* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0, + /* 33 */ 'b', 'd', 'z', 'a', '+', 32, 0, + /* 40 */ 'b', 'd', 'n', 'z', 'a', '+', 32, 0, + /* 48 */ 'b', 'd', 'z', 'l', '+', 32, 0, + /* 55 */ 'b', 'd', 'n', 'z', 'l', '+', 32, 0, + /* 63 */ 'b', 'd', 'z', '+', 32, 0, + /* 69 */ 'b', 'd', 'n', 'z', '+', 32, 0, + /* 76 */ 'b', 'c', 'l', 32, '2', '0', ',', 32, '3', '1', ',', 32, 0, + /* 89 */ 'b', 'c', 't', 'r', 'l', 10, 9, 'l', 'd', 32, '2', ',', 32, 0, + /* 103 */ 'b', 'c', 32, '1', '2', ',', 32, 0, + /* 111 */ 'b', 'c', 'l', 32, '1', '2', ',', 32, 0, + /* 120 */ 'b', 'c', 'l', 'r', 'l', 32, '1', '2', ',', 32, 0, + /* 131 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '1', '2', ',', 32, 0, + /* 143 */ 'b', 'c', 'l', 'r', 32, '1', '2', ',', 32, 0, + /* 153 */ 'b', 'c', 'c', 't', 'r', 32, '1', '2', ',', 32, 0, + /* 164 */ 'b', 'c', 32, '4', ',', 32, 0, + /* 171 */ 'b', 'c', 'l', 32, '4', ',', 32, 0, + /* 179 */ 'b', 'c', 'l', 'r', 'l', 32, '4', ',', 32, 0, + /* 189 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '4', ',', 32, 0, + /* 200 */ 'b', 'c', 'l', 'r', 32, '4', ',', 32, 0, + /* 209 */ 'b', 'c', 'c', 't', 'r', 32, '4', ',', 32, 0, + /* 219 */ 'm', 't', 's', 'p', 'r', 32, '2', '5', '6', ',', 32, 0, + /* 231 */ 'b', 'd', 'z', 'l', 'a', '-', 32, 0, + /* 239 */ 'b', 'd', 'n', 'z', 'l', 'a', '-', 32, 0, + /* 248 */ 'b', 'd', 'z', 'a', '-', 32, 0, + /* 255 */ 'b', 'd', 'n', 'z', 'a', '-', 32, 0, + /* 263 */ 'b', 'd', 'z', 'l', '-', 32, 0, + /* 270 */ 'b', 'd', 'n', 'z', 'l', '-', 32, 0, + /* 278 */ 'b', 'd', 'z', '-', 32, 0, + /* 284 */ 'b', 'd', 'n', 'z', '-', 32, 0, + /* 291 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', '.', 32, 0, + /* 302 */ 'e', 'x', 't', 's', 'b', '.', 32, 0, + /* 310 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', '.', 32, 0, + /* 321 */ 'f', 's', 'u', 'b', '.', 32, 0, + /* 328 */ 'f', 'm', 's', 'u', 'b', '.', 32, 0, + /* 336 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 32, 0, + /* 345 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', '.', 32, 0, + /* 356 */ 'a', 'd', 'd', 'c', '.', 32, 0, + /* 363 */ 'a', 'n', 'd', 'c', '.', 32, 0, + /* 370 */ 's', 'u', 'b', 'f', 'c', '.', 32, 0, + /* 378 */ 's', 'u', 'b', 'i', 'c', '.', 32, 0, + /* 386 */ 'a', 'd', 'd', 'i', 'c', '.', 32, 0, + /* 394 */ 'r', 'l', 'd', 'i', 'c', '.', 32, 0, + /* 402 */ 'o', 'r', 'c', '.', 32, 0, + /* 408 */ 's', 'r', 'a', 'd', '.', 32, 0, + /* 415 */ 'f', 'a', 'd', 'd', '.', 32, 0, + /* 422 */ 'f', 'm', 'a', 'd', 'd', '.', 32, 0, + /* 430 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 32, 0, + /* 439 */ 'm', 'u', 'l', 'h', 'd', '.', 32, 0, + /* 447 */ 'f', 'c', 'f', 'i', 'd', '.', 32, 0, + /* 455 */ 'f', 'c', 't', 'i', 'd', '.', 32, 0, + /* 463 */ 'm', 'u', 'l', 'l', 'd', '.', 32, 0, + /* 471 */ 's', 'l', 'd', '.', 32, 0, + /* 477 */ 'n', 'a', 'n', 'd', '.', 32, 0, + /* 484 */ 's', 'r', 'd', '.', 32, 0, + /* 490 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', '.', 32, 0, + /* 501 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', '.', 32, 0, + /* 512 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', '.', 32, 0, + /* 523 */ 'd', 'i', 'v', 'd', '.', 32, 0, + /* 530 */ 'c', 'n', 't', 'l', 'z', 'd', '.', 32, 0, + /* 539 */ 'a', 'd', 'd', 'e', '.', 32, 0, + /* 546 */ 's', 'u', 'b', 'f', 'e', '.', 32, 0, + /* 554 */ 'a', 'd', 'd', 'm', 'e', '.', 32, 0, + /* 562 */ 's', 'u', 'b', 'f', 'm', 'e', '.', 32, 0, + /* 571 */ 'f', 'r', 'e', '.', 32, 0, + /* 577 */ 'f', 'r', 's', 'q', 'r', 't', 'e', '.', 32, 0, + /* 587 */ 'a', 'd', 'd', 'z', 'e', '.', 32, 0, + /* 595 */ 's', 'u', 'b', 'f', 'z', 'e', '.', 32, 0, + /* 604 */ 's', 'u', 'b', 'f', '.', 32, 0, + /* 611 */ 'm', 't', 'f', 's', 'f', '.', 32, 0, + /* 619 */ 'f', 'n', 'e', 'g', '.', 32, 0, + /* 626 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', '.', 32, 0, + /* 637 */ 'e', 'x', 't', 's', 'h', '.', 32, 0, + /* 645 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', '.', 32, 0, + /* 656 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', '.', 32, 0, + /* 667 */ 's', 'r', 'a', 'd', 'i', '.', 32, 0, + /* 675 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', '.', 32, 0, + /* 686 */ 'e', 'x', 't', 'l', 'd', 'i', '.', 32, 0, + /* 695 */ 'a', 'n', 'd', 'i', '.', 32, 0, + /* 702 */ 'c', 'l', 'r', 'r', 'd', 'i', '.', 32, 0, + /* 711 */ 'i', 'n', 's', 'r', 'd', 'i', '.', 32, 0, + /* 720 */ 'r', 'o', 't', 'r', 'd', 'i', '.', 32, 0, + /* 729 */ 'e', 'x', 't', 'r', 'd', 'i', '.', 32, 0, + /* 738 */ 'm', 't', 'f', 's', 'f', 'i', '.', 32, 0, + /* 747 */ 'r', 'l', 'd', 'i', 'm', 'i', '.', 32, 0, + /* 756 */ 'r', 'l', 'w', 'i', 'm', 'i', '.', 32, 0, + /* 765 */ 's', 'r', 'a', 'w', 'i', '.', 32, 0, + /* 773 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', '.', 32, 0, + /* 784 */ 'i', 'n', 's', 'l', 'w', 'i', '.', 32, 0, + /* 793 */ 'e', 'x', 't', 'l', 'w', 'i', '.', 32, 0, + /* 802 */ 'c', 'l', 'r', 'r', 'w', 'i', '.', 32, 0, + /* 811 */ 'i', 'n', 's', 'r', 'w', 'i', '.', 32, 0, + /* 820 */ 'r', 'o', 't', 'r', 'w', 'i', '.', 32, 0, + /* 829 */ 'e', 'x', 't', 'r', 'w', 'i', '.', 32, 0, + /* 838 */ 'r', 'l', 'd', 'c', 'l', '.', 32, 0, + /* 846 */ 'r', 'l', 'd', 'i', 'c', 'l', '.', 32, 0, + /* 855 */ 'f', 's', 'e', 'l', '.', 32, 0, + /* 862 */ 'f', 'm', 'u', 'l', '.', 32, 0, + /* 869 */ 'f', 'r', 'i', 'm', '.', 32, 0, + /* 876 */ 'r', 'l', 'w', 'i', 'n', 'm', '.', 32, 0, + /* 885 */ 'r', 'l', 'w', 'n', 'm', '.', 32, 0, + /* 893 */ 'f', 'c', 'p', 's', 'g', 'n', '.', 32, 0, + /* 902 */ 'f', 'r', 'i', 'n', '.', 32, 0, + /* 909 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', '.', 32, 0, + /* 921 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', '.', 32, 0, + /* 933 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', '.', 32, 0, + /* 945 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', '.', 32, 0, + /* 955 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', '.', 32, 0, + /* 966 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', '.', 32, 0, + /* 977 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', '.', 32, 0, + /* 988 */ 'f', 'r', 'i', 'p', '.', 32, 0, + /* 995 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', '.', 32, 0, + /* 1007 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', '.', 32, 0, + /* 1019 */ 'f', 'r', 's', 'p', '.', 32, 0, + /* 1026 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', '.', 32, 0, + /* 1038 */ 'r', 'l', 'd', 'c', 'r', '.', 32, 0, + /* 1046 */ 'r', 'l', 'd', 'i', 'c', 'r', '.', 32, 0, + /* 1055 */ 'f', 'm', 'r', '.', 32, 0, + /* 1061 */ 'n', 'o', 'r', '.', 32, 0, + /* 1067 */ 'x', 'o', 'r', '.', 32, 0, + /* 1073 */ 'f', 'a', 'b', 's', '.', 32, 0, + /* 1080 */ 'f', 'n', 'a', 'b', 's', '.', 32, 0, + /* 1088 */ 'f', 's', 'u', 'b', 's', '.', 32, 0, + /* 1096 */ 'f', 'm', 's', 'u', 'b', 's', '.', 32, 0, + /* 1105 */ 'f', 'n', 'm', 's', 'u', 'b', 's', '.', 32, 0, + /* 1115 */ 'f', 'a', 'd', 'd', 's', '.', 32, 0, + /* 1123 */ 'f', 'm', 'a', 'd', 'd', 's', '.', 32, 0, + /* 1132 */ 'f', 'n', 'm', 'a', 'd', 'd', 's', '.', 32, 0, + /* 1142 */ 'f', 'c', 'f', 'i', 'd', 's', '.', 32, 0, + /* 1151 */ 'f', 'r', 'e', 's', '.', 32, 0, + /* 1158 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 's', '.', 32, 0, + /* 1169 */ 'm', 'f', 'f', 's', '.', 32, 0, + /* 1176 */ 'a', 'n', 'd', 'i', 's', '.', 32, 0, + /* 1184 */ 'f', 'm', 'u', 'l', 's', '.', 32, 0, + /* 1192 */ 'f', 's', 'q', 'r', 't', 's', '.', 32, 0, + /* 1201 */ 'f', 'c', 'f', 'i', 'd', 'u', 's', '.', 32, 0, + /* 1211 */ 'f', 'd', 'i', 'v', 's', '.', 32, 0, + /* 1219 */ 'f', 's', 'q', 'r', 't', '.', 32, 0, + /* 1227 */ 'm', 'u', 'l', 'h', 'd', 'u', '.', 32, 0, + /* 1236 */ 'f', 'c', 'f', 'i', 'd', 'u', '.', 32, 0, + /* 1245 */ 'd', 'i', 'v', 'd', 'u', '.', 32, 0, + /* 1253 */ 'm', 'u', 'l', 'h', 'w', 'u', '.', 32, 0, + /* 1262 */ 'd', 'i', 'v', 'w', 'u', '.', 32, 0, + /* 1270 */ 'f', 'd', 'i', 'v', '.', 32, 0, + /* 1277 */ 'e', 'q', 'v', '.', 32, 0, + /* 1283 */ 's', 'r', 'a', 'w', '.', 32, 0, + /* 1290 */ 'm', 'u', 'l', 'h', 'w', '.', 32, 0, + /* 1298 */ 'f', 'c', 't', 'i', 'w', '.', 32, 0, + /* 1306 */ 'm', 'u', 'l', 'l', 'w', '.', 32, 0, + /* 1314 */ 's', 'l', 'w', '.', 32, 0, + /* 1320 */ 's', 'r', 'w', '.', 32, 0, + /* 1326 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', '.', 32, 0, + /* 1337 */ 'e', 'x', 't', 's', 'w', '.', 32, 0, + /* 1345 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', '.', 32, 0, + /* 1356 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', '.', 32, 0, + /* 1367 */ 'd', 'i', 'v', 'w', '.', 32, 0, + /* 1374 */ 'c', 'n', 't', 'l', 'z', 'w', '.', 32, 0, + /* 1383 */ 's', 't', 'd', 'c', 'x', '.', 32, 0, + /* 1391 */ 's', 't', 'w', 'c', 'x', '.', 32, 0, + /* 1399 */ 't', 'l', 'b', 's', 'x', '.', 32, 0, + /* 1407 */ 'f', 'c', 't', 'i', 'd', 'z', '.', 32, 0, + /* 1416 */ 'f', 'r', 'i', 'z', '.', 32, 0, + /* 1423 */ 'f', 'c', 't', 'i', 'd', 'u', 'z', '.', 32, 0, + /* 1433 */ 'f', 'c', 't', 'i', 'w', 'u', 'z', '.', 32, 0, + /* 1443 */ 'f', 'c', 't', 'i', 'w', 'z', '.', 32, 0, + /* 1452 */ 'm', 't', 'f', 's', 'b', '0', 32, 0, + /* 1460 */ 'm', 't', 'f', 's', 'b', '1', 32, 0, + /* 1468 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 32, 0, + /* 1490 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 32, 0, + /* 1512 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', '8', 32, 0, + /* 1526 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', '8', 32, 0, + /* 1540 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', '8', 32, 0, + /* 1554 */ 'U', 'P', 'D', 'A', 'T', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 32, 0, + /* 1569 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, + /* 1588 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, + /* 1605 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', 32, 0, + /* 1618 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'a', 32, 0, + /* 1631 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'a', 32, 0, + /* 1644 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'a', 32, 0, + /* 1655 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'a', 32, 0, + /* 1666 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'a', 32, 0, + /* 1679 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'a', 32, 0, + /* 1692 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'a', 32, 0, + /* 1703 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0, + /* 1716 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0, + /* 1729 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'a', 32, 0, + /* 1740 */ 'd', 'c', 'b', 'a', 32, 0, + /* 1746 */ 'b', 'c', 'a', 32, 0, + /* 1751 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 32, 0, + /* 1762 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 'a', 32, 0, + /* 1773 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 32, 0, + /* 1784 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 32, 0, + /* 1794 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 32, 0, + /* 1805 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 'a', 32, 0, + /* 1816 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 32, 0, + /* 1827 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 32, 0, + /* 1837 */ 'l', 'h', 'a', 32, 0, + /* 1842 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 32, 0, + /* 1853 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 'a', 32, 0, + /* 1864 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 32, 0, + /* 1875 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 32, 0, + /* 1885 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 32, 0, + /* 1896 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 'a', 32, 0, + /* 1907 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 32, 0, + /* 1918 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 32, 0, + /* 1929 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 32, 0, + /* 1939 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 'a', 32, 0, + /* 1951 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 'a', 32, 0, + /* 1962 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 'a', 32, 0, + /* 1974 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 'a', 32, 0, + /* 1985 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 'a', 32, 0, + /* 1998 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 'a', 32, 0, + /* 2010 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 'a', 32, 0, + /* 2023 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 'a', 32, 0, + /* 2035 */ 'b', 'l', 'a', 32, 0, + /* 2040 */ 'b', 'c', 'l', 'a', 32, 0, + /* 2046 */ 'b', 'd', 'z', 'l', 'a', 32, 0, + /* 2053 */ 'b', 'd', 'n', 'z', 'l', 'a', 32, 0, + /* 2061 */ 'e', 'v', 'm', 'r', 'a', 32, 0, + /* 2068 */ 'l', 'w', 'a', 32, 0, + /* 2073 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 'a', 32, 0, + /* 2084 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 'a', 32, 0, + /* 2094 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'a', 32, 0, + /* 2105 */ 'q', 'v', 'l', 'f', 'd', 'x', 'a', 32, 0, + /* 2114 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'a', 32, 0, + /* 2124 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 'a', 32, 0, + /* 2134 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'a', 32, 0, + /* 2145 */ 'q', 'v', 'l', 'f', 's', 'x', 'a', 32, 0, + /* 2154 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'a', 32, 0, + /* 2164 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0, + /* 2175 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0, + /* 2187 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 'a', 32, 0, + /* 2197 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'a', 32, 0, + /* 2208 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 'a', 32, 0, + /* 2219 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'a', 32, 0, + /* 2231 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 'a', 32, 0, + /* 2241 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'a', 32, 0, + /* 2252 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 'a', 32, 0, + /* 2263 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 'a', 32, 0, + /* 2274 */ 'b', 'd', 'z', 'a', 32, 0, + /* 2280 */ 'b', 'd', 'n', 'z', 'a', 32, 0, + /* 2287 */ 'v', 's', 'r', 'a', 'b', 32, 0, + /* 2294 */ 'v', 'm', 'r', 'g', 'h', 'b', 32, 0, + /* 2302 */ 'v', 'm', 'r', 'g', 'l', 'b', 32, 0, + /* 2310 */ 'v', 'r', 'l', 'b', 32, 0, + /* 2316 */ 'v', 's', 'l', 'b', 32, 0, + /* 2322 */ 'c', 'm', 'p', 'b', 32, 0, + /* 2328 */ 'v', 's', 'r', 'b', 32, 0, + /* 2334 */ 'v', 'm', 'u', 'l', 'e', 's', 'b', 32, 0, + /* 2343 */ 'v', 'a', 'v', 'g', 's', 'b', 32, 0, + /* 2351 */ 'v', 'u', 'p', 'k', 'h', 's', 'b', 32, 0, + /* 2360 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'b', 32, 0, + /* 2370 */ 'v', 'u', 'p', 'k', 'l', 's', 'b', 32, 0, + /* 2379 */ 'v', 'm', 'i', 'n', 's', 'b', 32, 0, + /* 2387 */ 'v', 'm', 'u', 'l', 'o', 's', 'b', 32, 0, + /* 2396 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', 32, 0, + /* 2406 */ 'e', 'v', 'e', 'x', 't', 's', 'b', 32, 0, + /* 2415 */ 'v', 'm', 'a', 'x', 's', 'b', 32, 0, + /* 2423 */ 'm', 'f', 't', 'b', 32, 0, + /* 2429 */ 'v', 's', 'p', 'l', 't', 'b', 32, 0, + /* 2437 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 32, 0, + /* 2447 */ 's', 't', 'b', 32, 0, + /* 2452 */ 'v', 'm', 'u', 'l', 'e', 'u', 'b', 32, 0, + /* 2461 */ 'v', 'a', 'v', 'g', 'u', 'b', 32, 0, + /* 2469 */ 'v', 'm', 'i', 'n', 'u', 'b', 32, 0, + /* 2477 */ 'v', 'm', 'u', 'l', 'o', 'u', 'b', 32, 0, + /* 2486 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', 32, 0, + /* 2496 */ 'q', 'v', 'f', 's', 'u', 'b', 32, 0, + /* 2504 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 32, 0, + /* 2513 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 32, 0, + /* 2523 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', 32, 0, + /* 2533 */ 'v', 'm', 'a', 'x', 'u', 'b', 32, 0, + /* 2541 */ 'v', 'c', 'l', 'z', 'b', 32, 0, + /* 2548 */ 'b', 'c', 32, 0, + /* 2552 */ 'a', 'd', 'd', 'c', 32, 0, + /* 2558 */ 'x', 'x', 'l', 'a', 'n', 'd', 'c', 32, 0, + /* 2567 */ 'c', 'r', 'a', 'n', 'd', 'c', 32, 0, + /* 2575 */ 'e', 'v', 'a', 'n', 'd', 'c', 32, 0, + /* 2583 */ 's', 'u', 'b', 'f', 'c', 32, 0, + /* 2590 */ 's', 'u', 'b', 'i', 'c', 32, 0, + /* 2597 */ 'a', 'd', 'd', 'i', 'c', 32, 0, + /* 2604 */ 'r', 'l', 'd', 'i', 'c', 32, 0, + /* 2611 */ 's', 'u', 'b', 'f', 'i', 'c', 32, 0, + /* 2619 */ 'x', 's', 'r', 'd', 'p', 'i', 'c', 32, 0, + /* 2628 */ 'x', 'v', 'r', 'd', 'p', 'i', 'c', 32, 0, + /* 2637 */ 'x', 'v', 'r', 's', 'p', 'i', 'c', 32, 0, + /* 2646 */ 'b', 'r', 'i', 'n', 'c', 32, 0, + /* 2653 */ 's', 'y', 'n', 'c', 32, 0, + /* 2659 */ 'x', 'x', 'l', 'o', 'r', 'c', 32, 0, + /* 2667 */ 'c', 'r', 'o', 'r', 'c', 32, 0, + /* 2674 */ 'e', 'v', 'o', 'r', 'c', 32, 0, + /* 2681 */ 's', 'c', 32, 0, + /* 2685 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', 32, 0, + /* 2698 */ 'v', 's', 'r', 'a', 'd', 32, 0, + /* 2705 */ 'q', 'v', 'f', 'a', 'd', 'd', 32, 0, + /* 2713 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 32, 0, + /* 2722 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 32, 0, + /* 2732 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 32, 0, + /* 2746 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 32, 0, + /* 2759 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 32, 0, + /* 2769 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 32, 0, + /* 2780 */ 'e', 'v', 'l', 'd', 'd', 32, 0, + /* 2787 */ 'e', 'v', 's', 't', 'd', 'd', 32, 0, + /* 2795 */ 'l', 'f', 'd', 32, 0, + /* 2800 */ 's', 't', 'f', 'd', 32, 0, + /* 2806 */ 'm', 'u', 'l', 'h', 'd', 32, 0, + /* 2813 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 32, 0, + /* 2822 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 32, 0, + /* 2831 */ 't', 'l', 'b', 'l', 'd', 32, 0, + /* 2838 */ 'm', 'u', 'l', 'l', 'd', 32, 0, + /* 2845 */ 'c', 'm', 'p', 'l', 'd', 32, 0, + /* 2852 */ 'v', 'r', 'l', 'd', 32, 0, + /* 2858 */ 'v', 's', 'l', 'd', 32, 0, + /* 2864 */ 'x', 'x', 'l', 'a', 'n', 'd', 32, 0, + /* 2872 */ 'x', 'x', 'l', 'n', 'a', 'n', 'd', 32, 0, + /* 2881 */ 'c', 'r', 'n', 'a', 'n', 'd', 32, 0, + /* 2889 */ 'e', 'v', 'n', 'a', 'n', 'd', 32, 0, + /* 2897 */ 'c', 'r', 'a', 'n', 'd', 32, 0, + /* 2904 */ 'e', 'v', 'a', 'n', 'd', 32, 0, + /* 2911 */ 'c', 'm', 'p', 'd', 32, 0, + /* 2917 */ 'm', 't', 'm', 's', 'r', 'd', 32, 0, + /* 2925 */ 'v', 's', 'r', 'd', 32, 0, + /* 2931 */ 'v', 'm', 'i', 'n', 's', 'd', 32, 0, + /* 2939 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', 32, 0, + /* 2949 */ 'v', 'm', 'a', 'x', 's', 'd', 32, 0, + /* 2957 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 32, 0, + /* 2967 */ 's', 't', 'd', 32, 0, + /* 2972 */ 'v', 'm', 'i', 'n', 'u', 'd', 32, 0, + /* 2980 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', 32, 0, + /* 2990 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', 32, 0, + /* 3000 */ 'v', 'm', 'a', 'x', 'u', 'd', 32, 0, + /* 3008 */ 'd', 'i', 'v', 'd', 32, 0, + /* 3014 */ 'v', 'c', 'l', 'z', 'd', 32, 0, + /* 3021 */ 'c', 'n', 't', 'l', 'z', 'd', 32, 0, + /* 3029 */ 'a', 'd', 'd', 'e', 32, 0, + /* 3035 */ 's', 'l', 'b', 'm', 'f', 'e', 'e', 32, 0, + /* 3044 */ 'w', 'r', 't', 'e', 'e', 32, 0, + /* 3051 */ 's', 'u', 'b', 'f', 'e', 32, 0, + /* 3058 */ 'e', 'v', 'l', 'w', 'h', 'e', 32, 0, + /* 3066 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 32, 0, + /* 3075 */ 's', 'l', 'b', 'i', 'e', 32, 0, + /* 3082 */ 't', 'l', 'b', 'i', 'e', 32, 0, + /* 3089 */ 'a', 'd', 'd', 'm', 'e', 32, 0, + /* 3096 */ 's', 'u', 'b', 'f', 'm', 'e', 32, 0, + /* 3104 */ 't', 'l', 'b', 'r', 'e', 32, 0, + /* 3111 */ 'q', 'v', 'f', 'r', 'e', 32, 0, + /* 3118 */ 's', 'l', 'b', 'm', 't', 'e', 32, 0, + /* 3126 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 32, 0, + /* 3137 */ 't', 'l', 'b', 'w', 'e', 32, 0, + /* 3144 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 32, 0, + /* 3153 */ 'a', 'd', 'd', 'z', 'e', 32, 0, + /* 3160 */ 's', 'u', 'b', 'f', 'z', 'e', 32, 0, + /* 3168 */ 'd', 'c', 'b', 'f', 32, 0, + /* 3174 */ 's', 'u', 'b', 'f', 32, 0, + /* 3180 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 32, 0, + /* 3190 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 32, 0, + /* 3200 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 32, 0, + /* 3210 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 32, 0, + /* 3219 */ 'm', 'c', 'r', 'f', 32, 0, + /* 3225 */ 'm', 'f', 'o', 'c', 'r', 'f', 32, 0, + /* 3233 */ 'm', 't', 'o', 'c', 'r', 'f', 32, 0, + /* 3241 */ 'm', 't', 'c', 'r', 'f', 32, 0, + /* 3248 */ 'm', 't', 'f', 's', 'f', 32, 0, + /* 3255 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 32, 0, + /* 3265 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 32, 0, + /* 3275 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 32, 0, + /* 3285 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 32, 0, + /* 3294 */ 'q', 'v', 'f', 'n', 'e', 'g', 32, 0, + /* 3302 */ 'e', 'v', 'n', 'e', 'g', 32, 0, + /* 3309 */ 'v', 's', 'r', 'a', 'h', 32, 0, + /* 3316 */ 'e', 'v', 'l', 'd', 'h', 32, 0, + /* 3323 */ 'e', 'v', 's', 't', 'd', 'h', 32, 0, + /* 3331 */ 'v', 'm', 'r', 'g', 'h', 'h', 32, 0, + /* 3339 */ 'v', 'm', 'r', 'g', 'l', 'h', 32, 0, + /* 3347 */ 'v', 'r', 'l', 'h', 32, 0, + /* 3353 */ 'v', 's', 'l', 'h', 32, 0, + /* 3359 */ 'v', 's', 'r', 'h', 32, 0, + /* 3365 */ 'v', 'm', 'u', 'l', 'e', 's', 'h', 32, 0, + /* 3374 */ 'v', 'a', 'v', 'g', 's', 'h', 32, 0, + /* 3382 */ 'v', 'u', 'p', 'k', 'h', 's', 'h', 32, 0, + /* 3391 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'h', 32, 0, + /* 3401 */ 'v', 'u', 'p', 'k', 'l', 's', 'h', 32, 0, + /* 3410 */ 'v', 'm', 'i', 'n', 's', 'h', 32, 0, + /* 3418 */ 'v', 'm', 'u', 'l', 'o', 's', 'h', 32, 0, + /* 3427 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', 32, 0, + /* 3437 */ 'e', 'v', 'e', 'x', 't', 's', 'h', 32, 0, + /* 3446 */ 'v', 'm', 'a', 'x', 's', 'h', 32, 0, + /* 3454 */ 'v', 's', 'p', 'l', 't', 'h', 32, 0, + /* 3462 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'h', 32, 0, + /* 3472 */ 's', 't', 'h', 32, 0, + /* 3477 */ 'v', 'm', 'u', 'l', 'e', 'u', 'h', 32, 0, + /* 3486 */ 'v', 'a', 'v', 'g', 'u', 'h', 32, 0, + /* 3494 */ 'v', 'm', 'i', 'n', 'u', 'h', 32, 0, + /* 3502 */ 'v', 'm', 'u', 'l', 'o', 'u', 'h', 32, 0, + /* 3511 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', 32, 0, + /* 3521 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', 32, 0, + /* 3531 */ 'v', 'm', 'a', 'x', 'u', 'h', 32, 0, + /* 3539 */ 'v', 'c', 'l', 'z', 'h', 32, 0, + /* 3546 */ 'd', 'c', 'b', 'i', 32, 0, + /* 3552 */ 'i', 'c', 'b', 'i', 32, 0, + /* 3558 */ 's', 'u', 'b', 'i', 32, 0, + /* 3564 */ 'd', 'c', 'c', 'c', 'i', 32, 0, + /* 3571 */ 'i', 'c', 'c', 'c', 'i', 32, 0, + /* 3578 */ 'q', 'v', 'g', 'p', 'c', 'i', 32, 0, + /* 3586 */ 's', 'r', 'a', 'd', 'i', 32, 0, + /* 3593 */ 'a', 'd', 'd', 'i', 32, 0, + /* 3599 */ 'c', 'm', 'p', 'l', 'd', 'i', 32, 0, + /* 3607 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', 32, 0, + /* 3617 */ 'e', 'x', 't', 'l', 'd', 'i', 32, 0, + /* 3625 */ 'x', 'x', 'p', 'e', 'r', 'm', 'd', 'i', 32, 0, + /* 3635 */ 'c', 'm', 'p', 'd', 'i', 32, 0, + /* 3642 */ 'c', 'l', 'r', 'r', 'd', 'i', 32, 0, + /* 3650 */ 'i', 'n', 's', 'r', 'd', 'i', 32, 0, + /* 3658 */ 'r', 'o', 't', 'r', 'd', 'i', 32, 0, + /* 3666 */ 'e', 'x', 't', 'r', 'd', 'i', 32, 0, + /* 3674 */ 't', 'd', 'i', 32, 0, + /* 3679 */ 'w', 'r', 't', 'e', 'e', 'i', 32, 0, + /* 3687 */ 'm', 't', 'f', 's', 'f', 'i', 32, 0, + /* 3695 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'f', 'i', 32, 0, + /* 3706 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 32, 0, + /* 3717 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 'h', 'i', 32, 0, + /* 3730 */ 't', 'l', 'b', 'l', 'i', 32, 0, + /* 3737 */ 'm', 'u', 'l', 'l', 'i', 32, 0, + /* 3744 */ 'r', 'l', 'd', 'i', 'm', 'i', 32, 0, + /* 3752 */ 'r', 'l', 'w', 'i', 'm', 'i', 32, 0, + /* 3760 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 32, 0, + /* 3770 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 32, 0, + /* 3780 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 32, 0, + /* 3790 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 32, 0, + /* 3799 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 32, 0, + /* 3809 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 32, 0, + /* 3819 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 32, 0, + /* 3829 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 32, 0, + /* 3839 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 32, 0, + /* 3848 */ 'q', 'v', 'a', 'l', 'i', 'g', 'n', 'i', 32, 0, + /* 3858 */ 'v', 's', 'l', 'd', 'o', 'i', 32, 0, + /* 3866 */ 'x', 's', 'r', 'd', 'p', 'i', 32, 0, + /* 3874 */ 'x', 'v', 'r', 'd', 'p', 'i', 32, 0, + /* 3882 */ 'x', 'v', 'r', 's', 'p', 'i', 32, 0, + /* 3890 */ 'x', 'o', 'r', 'i', 32, 0, + /* 3896 */ 'q', 'v', 'e', 's', 'p', 'l', 'a', 't', 'i', 32, 0, + /* 3907 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'i', 32, 0, + /* 3917 */ 's', 'r', 'a', 'w', 'i', 32, 0, + /* 3924 */ 'x', 'x', 's', 'l', 'd', 'w', 'i', 32, 0, + /* 3933 */ 'c', 'm', 'p', 'l', 'w', 'i', 32, 0, + /* 3941 */ 'e', 'v', 'r', 'l', 'w', 'i', 32, 0, + /* 3949 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', 32, 0, + /* 3959 */ 'i', 'n', 's', 'l', 'w', 'i', 32, 0, + /* 3967 */ 'e', 'v', 's', 'l', 'w', 'i', 32, 0, + /* 3975 */ 'e', 'x', 't', 'l', 'w', 'i', 32, 0, + /* 3983 */ 'c', 'm', 'p', 'w', 'i', 32, 0, + /* 3990 */ 'c', 'l', 'r', 'r', 'w', 'i', 32, 0, + /* 3998 */ 'i', 'n', 's', 'r', 'w', 'i', 32, 0, + /* 4006 */ 'r', 'o', 't', 'r', 'w', 'i', 32, 0, + /* 4014 */ 'e', 'x', 't', 'r', 'w', 'i', 32, 0, + /* 4022 */ 'l', 's', 'w', 'i', 32, 0, + /* 4028 */ 's', 't', 's', 'w', 'i', 32, 0, + /* 4035 */ 't', 'w', 'i', 32, 0, + /* 4040 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 32, 0, + /* 4051 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 32, 0, + /* 4061 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 32, 0, + /* 4072 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 32, 0, + /* 4082 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 32, 0, + /* 4094 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 32, 0, + /* 4105 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 32, 0, + /* 4117 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 32, 0, + /* 4128 */ 'q', 'v', 'f', 'l', 'o', 'g', 'i', 'c', 'a', 'l', 32, 0, + /* 4140 */ 'b', 'l', 32, 0, + /* 4144 */ 'b', 'c', 'l', 32, 0, + /* 4149 */ 'r', 'l', 'd', 'c', 'l', 32, 0, + /* 4156 */ 'r', 'l', 'd', 'i', 'c', 'l', 32, 0, + /* 4164 */ 't', 'l', 'b', 'i', 'e', 'l', 32, 0, + /* 4172 */ 'q', 'v', 'f', 's', 'e', 'l', 32, 0, + /* 4180 */ 'i', 's', 'e', 'l', 32, 0, + /* 4186 */ 'v', 's', 'e', 'l', 32, 0, + /* 4192 */ 'x', 'x', 's', 'e', 'l', 32, 0, + /* 4199 */ 'b', 'c', 'l', 'r', 'l', 32, 0, + /* 4206 */ 'b', 'c', 'c', 't', 'r', 'l', 32, 0, + /* 4214 */ 'l', 'v', 's', 'l', 32, 0, + /* 4220 */ 'q', 'v', 'f', 'm', 'u', 'l', 32, 0, + /* 4228 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 32, 0, + /* 4237 */ 'l', 'v', 'x', 'l', 32, 0, + /* 4243 */ 's', 't', 'v', 'x', 'l', 32, 0, + /* 4250 */ 'd', 'c', 'b', 'z', 'l', 32, 0, + /* 4257 */ 'b', 'd', 'z', 'l', 32, 0, + /* 4263 */ 'b', 'd', 'n', 'z', 'l', 32, 0, + /* 4270 */ 'v', 'm', 's', 'u', 'm', 'm', 'b', 'm', 32, 0, + /* 4280 */ 'v', 's', 'u', 'b', 'u', 'b', 'm', 32, 0, + /* 4289 */ 'v', 'a', 'd', 'd', 'u', 'b', 'm', 32, 0, + /* 4298 */ 'v', 'm', 's', 'u', 'm', 'u', 'b', 'm', 32, 0, + /* 4308 */ 'v', 's', 'u', 'b', 'u', 'd', 'm', 32, 0, + /* 4317 */ 'v', 'a', 'd', 'd', 'u', 'd', 'm', 32, 0, + /* 4326 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 'm', 32, 0, + /* 4336 */ 'v', 's', 'u', 'b', 'u', 'h', 'm', 32, 0, + /* 4345 */ 'v', 'm', 'l', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, + /* 4356 */ 'v', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, + /* 4365 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 'm', 32, 0, + /* 4375 */ 'v', 'r', 'f', 'i', 'm', 32, 0, + /* 4382 */ 'x', 's', 'r', 'd', 'p', 'i', 'm', 32, 0, + /* 4391 */ 'x', 'v', 'r', 'd', 'p', 'i', 'm', 32, 0, + /* 4400 */ 'x', 'v', 'r', 's', 'p', 'i', 'm', 32, 0, + /* 4409 */ 'q', 'v', 'f', 'r', 'i', 'm', 32, 0, + /* 4417 */ 'r', 'l', 'w', 'i', 'n', 'm', 32, 0, + /* 4425 */ 'r', 'l', 'w', 'n', 'm', 32, 0, + /* 4432 */ 'q', 'v', 'f', 'p', 'e', 'r', 'm', 32, 0, + /* 4441 */ 'v', 'p', 'e', 'r', 'm', 32, 0, + /* 4448 */ 'v', 'p', 'k', 'u', 'h', 'u', 'm', 32, 0, + /* 4457 */ 'v', 'p', 'k', 'u', 'w', 'u', 'm', 32, 0, + /* 4466 */ 'v', 's', 'u', 'b', 'u', 'w', 'm', 32, 0, + /* 4475 */ 'v', 'a', 'd', 'd', 'u', 'w', 'm', 32, 0, + /* 4484 */ 'v', 'm', 'u', 'l', 'u', 'w', 'm', 32, 0, + /* 4493 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, + /* 4506 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, + /* 4519 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'n', 32, 0, + /* 4530 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'n', 32, 0, + /* 4541 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, + /* 4554 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, + /* 4567 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'n', 32, 0, + /* 4578 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, + /* 4591 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, + /* 4604 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'n', 32, 0, + /* 4615 */ 'q', 'v', 'f', 't', 's', 't', 'n', 'a', 'n', 32, 0, + /* 4626 */ 'q', 'v', 'f', 'c', 'p', 's', 'g', 'n', 32, 0, + /* 4636 */ 'v', 'r', 'f', 'i', 'n', 32, 0, + /* 4643 */ 'q', 'v', 'f', 'r', 'i', 'n', 32, 0, + /* 4651 */ 'm', 'f', 's', 'r', 'i', 'n', 32, 0, + /* 4659 */ 'm', 't', 's', 'r', 'i', 'n', 32, 0, + /* 4667 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 32, 0, + /* 4676 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 32, 0, + /* 4687 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 'l', 'o', 32, 0, + /* 4700 */ 'v', 's', 'l', 'o', 32, 0, + /* 4706 */ 'v', 's', 'r', 'o', 32, 0, + /* 4712 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 32, 0, + /* 4721 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, + /* 4733 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, + /* 4745 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, + /* 4756 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, + /* 4767 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, + /* 4779 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, + /* 4791 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, + /* 4802 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, + /* 4813 */ 'x', 's', 's', 'u', 'b', 'd', 'p', 32, 0, + /* 4822 */ 'x', 'v', 's', 'u', 'b', 'd', 'p', 32, 0, + /* 4831 */ 'x', 's', 'a', 'd', 'd', 'd', 'p', 32, 0, + /* 4840 */ 'x', 'v', 'a', 'd', 'd', 'd', 'p', 32, 0, + /* 4849 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, + /* 4860 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, + /* 4871 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, + /* 4882 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, + /* 4893 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0, + /* 4904 */ 'x', 's', 'r', 'e', 'd', 'p', 32, 0, + /* 4912 */ 'x', 'v', 'r', 'e', 'd', 'p', 32, 0, + /* 4920 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, + /* 4932 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, + /* 4944 */ 'x', 's', 'n', 'e', 'g', 'd', 'p', 32, 0, + /* 4953 */ 'x', 'v', 'n', 'e', 'g', 'd', 'p', 32, 0, + /* 4962 */ 'x', 's', 'm', 'u', 'l', 'd', 'p', 32, 0, + /* 4971 */ 'x', 'v', 'm', 'u', 'l', 'd', 'p', 32, 0, + /* 4980 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, + /* 4992 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, + /* 5004 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, + /* 5015 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, + /* 5026 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, + /* 5038 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, + /* 5050 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, + /* 5061 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, + /* 5072 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, + /* 5083 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, + /* 5094 */ 'x', 's', 'm', 'i', 'n', 'd', 'p', 32, 0, + /* 5103 */ 'x', 'v', 'm', 'i', 'n', 'd', 'p', 32, 0, + /* 5112 */ 'x', 's', 'c', 'm', 'p', 'o', 'd', 'p', 32, 0, + /* 5122 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, + /* 5132 */ 'x', 'v', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, + /* 5142 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0, + /* 5153 */ 'x', 's', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, + /* 5163 */ 'x', 'v', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, + /* 5173 */ 'x', 's', 'a', 'b', 's', 'd', 'p', 32, 0, + /* 5182 */ 'x', 'v', 'a', 'b', 's', 'd', 'p', 32, 0, + /* 5191 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0, + /* 5202 */ 'x', 's', 's', 'q', 'r', 't', 'd', 'p', 32, 0, + /* 5212 */ 'x', 's', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, + /* 5223 */ 'x', 'v', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, + /* 5234 */ 'x', 'v', 's', 'q', 'r', 't', 'd', 'p', 32, 0, + /* 5244 */ 'x', 's', 'c', 'm', 'p', 'u', 'd', 'p', 32, 0, + /* 5254 */ 'x', 's', 'd', 'i', 'v', 'd', 'p', 32, 0, + /* 5263 */ 'x', 's', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, + /* 5273 */ 'x', 'v', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, + /* 5283 */ 'x', 'v', 'd', 'i', 'v', 'd', 'p', 32, 0, + /* 5292 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 'd', 'p', 32, 0, + /* 5303 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 'd', 'p', 32, 0, + /* 5314 */ 'x', 's', 'm', 'a', 'x', 'd', 'p', 32, 0, + /* 5323 */ 'x', 'v', 'm', 'a', 'x', 'd', 'p', 32, 0, + /* 5332 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', 32, 0, + /* 5341 */ 'v', 'n', 'm', 's', 'u', 'b', 'f', 'p', 32, 0, + /* 5351 */ 'v', 's', 'u', 'b', 'f', 'p', 32, 0, + /* 5359 */ 'v', 'm', 'a', 'd', 'd', 'f', 'p', 32, 0, + /* 5368 */ 'v', 'a', 'd', 'd', 'f', 'p', 32, 0, + /* 5376 */ 'v', 'l', 'o', 'g', 'e', 'f', 'p', 32, 0, + /* 5385 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', 32, 0, + /* 5395 */ 'v', 'r', 'e', 'f', 'p', 32, 0, + /* 5402 */ 'v', 'e', 'x', 'p', 't', 'e', 'f', 'p', 32, 0, + /* 5412 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 'f', 'p', 32, 0, + /* 5423 */ 'v', 'm', 'i', 'n', 'f', 'p', 32, 0, + /* 5431 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', 32, 0, + /* 5441 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', 32, 0, + /* 5451 */ 'v', 'm', 'a', 'x', 'f', 'p', 32, 0, + /* 5459 */ 'v', 'r', 'f', 'i', 'p', 32, 0, + /* 5466 */ 'x', 's', 'r', 'd', 'p', 'i', 'p', 32, 0, + /* 5475 */ 'x', 'v', 'r', 'd', 'p', 'i', 'p', 32, 0, + /* 5484 */ 'x', 'v', 'r', 's', 'p', 'i', 'p', 32, 0, + /* 5493 */ 'q', 'v', 'f', 'r', 'i', 'p', 32, 0, + /* 5501 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, + /* 5513 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, + /* 5524 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, + /* 5536 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, + /* 5547 */ 'x', 'v', 's', 'u', 'b', 's', 'p', 32, 0, + /* 5556 */ 'x', 'v', 'a', 'd', 'd', 's', 'p', 32, 0, + /* 5565 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0, + /* 5576 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0, + /* 5587 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', 32, 0, + /* 5598 */ 'x', 'v', 'r', 'e', 's', 'p', 32, 0, + /* 5606 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0, + /* 5618 */ 'x', 'v', 'n', 'e', 'g', 's', 'p', 32, 0, + /* 5627 */ 'x', 'v', 'm', 'u', 'l', 's', 'p', 32, 0, + /* 5636 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, + /* 5648 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, + /* 5659 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, + /* 5671 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, + /* 5682 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 's', 'p', 32, 0, + /* 5693 */ 'x', 'v', 'm', 'i', 'n', 's', 'p', 32, 0, + /* 5702 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, + /* 5712 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, + /* 5722 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', 32, 0, + /* 5733 */ 'q', 'v', 'f', 'r', 's', 'p', 32, 0, + /* 5741 */ 'x', 'v', 'n', 'a', 'b', 's', 's', 'p', 32, 0, + /* 5751 */ 'x', 'v', 'a', 'b', 's', 's', 'p', 32, 0, + /* 5760 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', 32, 0, + /* 5771 */ 'x', 'v', 't', 's', 'q', 'r', 't', 's', 'p', 32, 0, + /* 5782 */ 'x', 'v', 's', 'q', 'r', 't', 's', 'p', 32, 0, + /* 5792 */ 'x', 'v', 't', 'd', 'i', 'v', 's', 'p', 32, 0, + /* 5802 */ 'x', 'v', 'd', 'i', 'v', 's', 'p', 32, 0, + /* 5811 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 's', 'p', 32, 0, + /* 5822 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 's', 'p', 32, 0, + /* 5833 */ 'x', 'v', 'm', 'a', 'x', 's', 'p', 32, 0, + /* 5842 */ 'q', 'v', 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, + /* 5852 */ 'e', 'v', 'c', 'm', 'p', 'e', 'q', 32, 0, + /* 5861 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 32, 0, + /* 5874 */ 'm', 'b', 'a', 'r', 32, 0, + /* 5880 */ 'm', 'f', 'd', 'c', 'r', 32, 0, + /* 5887 */ 'r', 'l', 'd', 'c', 'r', 32, 0, + /* 5894 */ 'm', 't', 'd', 'c', 'r', 32, 0, + /* 5901 */ 'm', 'f', 'c', 'r', 32, 0, + /* 5907 */ 'r', 'l', 'd', 'i', 'c', 'r', 32, 0, + /* 5915 */ 'm', 'f', 'v', 's', 'c', 'r', 32, 0, + /* 5923 */ 'm', 't', 'v', 's', 'c', 'r', 32, 0, + /* 5931 */ 'b', 'c', 'l', 'r', 32, 0, + /* 5937 */ 'm', 'f', 'l', 'r', 32, 0, + /* 5943 */ 'm', 't', 'l', 'r', 32, 0, + /* 5949 */ 'q', 'v', 'f', 'm', 'r', 32, 0, + /* 5956 */ 'x', 'x', 'l', 'o', 'r', 32, 0, + /* 5963 */ 'x', 'x', 'l', 'n', 'o', 'r', 32, 0, + /* 5971 */ 'c', 'r', 'n', 'o', 'r', 32, 0, + /* 5978 */ 'e', 'v', 'n', 'o', 'r', 32, 0, + /* 5985 */ 'c', 'r', 'o', 'r', 32, 0, + /* 5991 */ 'e', 'v', 'o', 'r', 32, 0, + /* 5997 */ 'x', 'x', 'l', 'x', 'o', 'r', 32, 0, + /* 6005 */ 'c', 'r', 'x', 'o', 'r', 32, 0, + /* 6012 */ 'e', 'v', 'x', 'o', 'r', 32, 0, + /* 6019 */ 'm', 'f', 's', 'p', 'r', 32, 0, + /* 6026 */ 'm', 't', 's', 'p', 'r', 32, 0, + /* 6033 */ 'm', 'f', 's', 'r', 32, 0, + /* 6039 */ 'm', 'f', 'm', 's', 'r', 32, 0, + /* 6046 */ 'm', 't', 'm', 's', 'r', 32, 0, + /* 6053 */ 'm', 't', 's', 'r', 32, 0, + /* 6059 */ 'l', 'v', 's', 'r', 32, 0, + /* 6065 */ 'b', 'c', 'c', 't', 'r', 32, 0, + /* 6072 */ 'm', 'f', 'c', 't', 'r', 32, 0, + /* 6079 */ 'm', 't', 'c', 't', 'r', 32, 0, + /* 6086 */ 'q', 'v', 'f', 'a', 'b', 's', 32, 0, + /* 6094 */ 'q', 'v', 'f', 'n', 'a', 'b', 's', 32, 0, + /* 6103 */ 'e', 'v', 'a', 'b', 's', 32, 0, + /* 6110 */ 'v', 's', 'u', 'm', '4', 's', 'b', 's', 32, 0, + /* 6120 */ 'v', 's', 'u', 'b', 's', 'b', 's', 32, 0, + /* 6129 */ 'v', 'a', 'd', 'd', 's', 'b', 's', 32, 0, + /* 6138 */ 'v', 's', 'u', 'm', '4', 'u', 'b', 's', 32, 0, + /* 6148 */ 'v', 's', 'u', 'b', 'u', 'b', 's', 32, 0, + /* 6157 */ 'v', 'a', 'd', 'd', 'u', 'b', 's', 32, 0, + /* 6166 */ 'q', 'v', 'f', 's', 'u', 'b', 's', 32, 0, + /* 6175 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 's', 32, 0, + /* 6185 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 32, 0, + /* 6196 */ 'q', 'v', 'f', 'a', 'd', 'd', 's', 32, 0, + /* 6205 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6215 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6226 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6241 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6255 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6266 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, + /* 6278 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 's', 32, 0, + /* 6288 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, + /* 6300 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, + /* 6312 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'd', 's', 32, 0, + /* 6324 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, + /* 6336 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, + /* 6348 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'd', 's', 32, 0, + /* 6360 */ 'q', 'v', 'f', 'r', 'e', 's', 32, 0, + /* 6368 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 's', 32, 0, + /* 6380 */ 'm', 'f', 'f', 's', 32, 0, + /* 6386 */ 'l', 'f', 's', 32, 0, + /* 6391 */ 'm', 'c', 'r', 'f', 's', 32, 0, + /* 6398 */ 's', 't', 'f', 's', 32, 0, + /* 6404 */ 'v', 's', 'u', 'm', '4', 's', 'h', 's', 32, 0, + /* 6414 */ 'v', 's', 'u', 'b', 's', 'h', 's', 32, 0, + /* 6423 */ 'v', 'm', 'h', 'a', 'd', 'd', 's', 'h', 's', 32, 0, + /* 6434 */ 'v', 'm', 'h', 'r', 'a', 'd', 'd', 's', 'h', 's', 32, 0, + /* 6446 */ 'v', 'a', 'd', 'd', 's', 'h', 's', 32, 0, + /* 6455 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 's', 32, 0, + /* 6465 */ 'v', 's', 'u', 'b', 'u', 'h', 's', 32, 0, + /* 6474 */ 'v', 'a', 'd', 'd', 'u', 'h', 's', 32, 0, + /* 6483 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 's', 32, 0, + /* 6493 */ 's', 'u', 'b', 'i', 's', 32, 0, + /* 6500 */ 'a', 'd', 'd', 'i', 's', 32, 0, + /* 6507 */ 'l', 'i', 's', 32, 0, + /* 6512 */ 'x', 'o', 'r', 'i', 's', 32, 0, + /* 6519 */ 'e', 'v', 's', 'r', 'w', 'i', 's', 32, 0, + /* 6528 */ 'q', 'v', 'f', 'm', 'u', 'l', 's', 32, 0, + /* 6537 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 's', 32, 0, + /* 6547 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 32, 0, + /* 6556 */ 'd', 's', 's', 32, 0, + /* 6561 */ 'v', 'p', 'k', 's', 'h', 's', 's', 32, 0, + /* 6570 */ 'v', 'p', 'k', 's', 'w', 's', 's', 32, 0, + /* 6579 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 's', 32, 0, + /* 6589 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 's', 32, 0, + /* 6599 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, + /* 6607 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 's', 32, 0, + /* 6618 */ 'v', 'p', 'k', 's', 'h', 'u', 's', 32, 0, + /* 6627 */ 'v', 'p', 'k', 'u', 'h', 'u', 's', 32, 0, + /* 6636 */ 'v', 'p', 'k', 's', 'w', 'u', 's', 32, 0, + /* 6645 */ 'v', 'p', 'k', 'u', 'w', 'u', 's', 32, 0, + /* 6654 */ 'f', 'd', 'i', 'v', 's', 32, 0, + /* 6661 */ 'e', 'v', 's', 'r', 'w', 's', 32, 0, + /* 6669 */ 'v', 's', 'u', 'm', '2', 's', 'w', 's', 32, 0, + /* 6679 */ 'v', 's', 'u', 'b', 's', 'w', 's', 32, 0, + /* 6688 */ 'v', 'a', 'd', 'd', 's', 'w', 's', 32, 0, + /* 6697 */ 'v', 's', 'u', 'm', 's', 'w', 's', 32, 0, + /* 6706 */ 'v', 's', 'u', 'b', 'u', 'w', 's', 32, 0, + /* 6715 */ 'v', 'a', 'd', 'd', 'u', 'w', 's', 32, 0, + /* 6724 */ 'e', 'v', 'd', 'i', 'v', 'w', 's', 32, 0, + /* 6733 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, + /* 6745 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, + /* 6757 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'w', 's', 32, 0, + /* 6769 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, + /* 6781 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, + /* 6793 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'w', 's', 32, 0, + /* 6805 */ 'v', 'c', 't', 's', 'x', 's', 32, 0, + /* 6813 */ 'v', 'c', 't', 'u', 'x', 's', 32, 0, + /* 6821 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 32, 0, + /* 6834 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 32, 0, + /* 6846 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 32, 0, + /* 6860 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 32, 0, + /* 6874 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 32, 0, + /* 6886 */ 'd', 'c', 'b', 't', 32, 0, + /* 6892 */ 'i', 'c', 'b', 't', 32, 0, + /* 6898 */ 'q', 'v', 'f', 'c', 'm', 'p', 'g', 't', 32, 0, + /* 6908 */ 'w', 'a', 'i', 't', 32, 0, + /* 6914 */ 'q', 'v', 'f', 'c', 'm', 'p', 'l', 't', 32, 0, + /* 6924 */ 'f', 's', 'q', 'r', 't', 32, 0, + /* 6931 */ 'd', 'c', 'b', 's', 't', 32, 0, + /* 6938 */ 'd', 's', 't', 32, 0, + /* 6943 */ 'd', 'c', 'b', 't', 's', 't', 32, 0, + /* 6951 */ 'd', 's', 't', 's', 't', 32, 0, + /* 6958 */ 'd', 's', 't', 't', 32, 0, + /* 6964 */ 'd', 's', 't', 's', 't', 't', 32, 0, + /* 6972 */ 'l', 'h', 'a', 'u', 32, 0, + /* 6978 */ 's', 't', 'b', 'u', 32, 0, + /* 6984 */ 'l', 'f', 'd', 'u', 32, 0, + /* 6990 */ 's', 't', 'f', 'd', 'u', 32, 0, + /* 6997 */ 'm', 'u', 'l', 'h', 'd', 'u', 32, 0, + /* 7005 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 32, 0, + /* 7015 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 32, 0, + /* 7025 */ 'l', 'd', 'u', 32, 0, + /* 7030 */ 's', 't', 'd', 'u', 32, 0, + /* 7036 */ 'd', 'i', 'v', 'd', 'u', 32, 0, + /* 7043 */ 's', 't', 'h', 'u', 32, 0, + /* 7049 */ 'e', 'v', 's', 'r', 'w', 'i', 'u', 32, 0, + /* 7058 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 32, 0, + /* 7067 */ 'f', 'c', 'm', 'p', 'u', 32, 0, + /* 7074 */ 'l', 'f', 's', 'u', 32, 0, + /* 7080 */ 's', 't', 'f', 's', 'u', 32, 0, + /* 7087 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 'u', 32, 0, + /* 7097 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 'u', 32, 0, + /* 7107 */ 'm', 'u', 'l', 'h', 'w', 'u', 32, 0, + /* 7115 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 32, 0, + /* 7125 */ 'e', 'v', 's', 'r', 'w', 'u', 32, 0, + /* 7133 */ 's', 't', 'w', 'u', 32, 0, + /* 7139 */ 'e', 'v', 'd', 'i', 'v', 'w', 'u', 32, 0, + /* 7148 */ 'l', 'b', 'z', 'u', 32, 0, + /* 7154 */ 'l', 'h', 'z', 'u', 32, 0, + /* 7160 */ 'l', 'w', 'z', 'u', 32, 0, + /* 7166 */ 'f', 'd', 'i', 'v', 32, 0, + /* 7172 */ 'x', 'x', 'l', 'e', 'q', 'v', 32, 0, + /* 7180 */ 'c', 'r', 'e', 'q', 'v', 32, 0, + /* 7187 */ 'e', 'v', 'e', 'q', 'v', 32, 0, + /* 7194 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, + /* 7207 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, + /* 7220 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'a', 'w', 32, 0, + /* 7233 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'a', 'w', 32, 0, + /* 7246 */ 'e', 'v', 'a', 'd', 'd', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7259 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7272 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7286 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7299 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7312 */ 'e', 'v', 'a', 'd', 'd', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7325 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7338 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7352 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7365 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, + /* 7378 */ 'e', 'v', 'a', 'd', 'd', 's', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7391 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7404 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7418 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7431 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7444 */ 'e', 'v', 'a', 'd', 'd', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7457 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7470 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7484 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7497 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, + /* 7510 */ 'v', 's', 'r', 'a', 'w', 32, 0, + /* 7517 */ 'e', 'v', 'a', 'd', 'd', 'w', 32, 0, + /* 7525 */ 'e', 'v', 'l', 'd', 'w', 32, 0, + /* 7532 */ 'e', 'v', 'r', 'n', 'd', 'w', 32, 0, + /* 7540 */ 'e', 'v', 's', 't', 'd', 'w', 32, 0, + /* 7548 */ 'e', 'v', 's', 'u', 'b', 'f', 'w', 32, 0, + /* 7557 */ 'e', 'v', 's', 'u', 'b', 'i', 'f', 'w', 32, 0, + /* 7567 */ 'v', 'm', 'r', 'g', 'h', 'w', 32, 0, + /* 7575 */ 'x', 'x', 'm', 'r', 'g', 'h', 'w', 32, 0, + /* 7584 */ 'm', 'u', 'l', 'h', 'w', 32, 0, + /* 7591 */ 'e', 'v', 'a', 'd', 'd', 'i', 'w', 32, 0, + /* 7600 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 32, 0, + /* 7609 */ 'v', 'm', 'r', 'g', 'l', 'w', 32, 0, + /* 7617 */ 'x', 'x', 'm', 'r', 'g', 'l', 'w', 32, 0, + /* 7626 */ 'm', 'u', 'l', 'l', 'w', 32, 0, + /* 7633 */ 'c', 'm', 'p', 'l', 'w', 32, 0, + /* 7640 */ 'e', 'v', 'r', 'l', 'w', 32, 0, + /* 7647 */ 'e', 'v', 's', 'l', 'w', 32, 0, + /* 7654 */ 'l', 'm', 'w', 32, 0, + /* 7659 */ 's', 't', 'm', 'w', 32, 0, + /* 7665 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, + /* 7678 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, + /* 7691 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'n', 'w', 32, 0, + /* 7704 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'n', 'w', 32, 0, + /* 7717 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7730 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7743 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7756 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7769 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7782 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, + /* 7795 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7808 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7821 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7834 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7847 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7860 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, + /* 7873 */ 'c', 'm', 'p', 'w', 32, 0, + /* 7879 */ 'v', 's', 'r', 'w', 32, 0, + /* 7885 */ 'v', 'm', 'u', 'l', 'e', 's', 'w', 32, 0, + /* 7894 */ 'v', 'a', 'v', 'g', 's', 'w', 32, 0, + /* 7902 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'w', 32, 0, + /* 7912 */ 'e', 'v', 'c', 'n', 't', 'l', 's', 'w', 32, 0, + /* 7922 */ 'v', 'm', 'i', 'n', 's', 'w', 32, 0, + /* 7930 */ 'v', 'm', 'u', 'l', 'o', 's', 'w', 32, 0, + /* 7939 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', 32, 0, + /* 7949 */ 'e', 'x', 't', 's', 'w', 32, 0, + /* 7956 */ 'v', 'm', 'a', 'x', 's', 'w', 32, 0, + /* 7964 */ 'v', 's', 'p', 'l', 't', 'w', 32, 0, + /* 7972 */ 'x', 'x', 's', 'p', 'l', 't', 'w', 32, 0, + /* 7981 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 32, 0, + /* 7991 */ 's', 't', 'w', 32, 0, + /* 7996 */ 'v', 's', 'u', 'b', 'c', 'u', 'w', 32, 0, + /* 8005 */ 'v', 'a', 'd', 'd', 'c', 'u', 'w', 32, 0, + /* 8014 */ 'v', 'm', 'u', 'l', 'e', 'u', 'w', 32, 0, + /* 8023 */ 'v', 'a', 'v', 'g', 'u', 'w', 32, 0, + /* 8031 */ 'v', 'm', 'i', 'n', 'u', 'w', 32, 0, + /* 8039 */ 'v', 'm', 'u', 'l', 'o', 'u', 'w', 32, 0, + /* 8048 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', 32, 0, + /* 8058 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', 32, 0, + /* 8068 */ 'v', 'm', 'a', 'x', 'u', 'w', 32, 0, + /* 8076 */ 'd', 'i', 'v', 'w', 32, 0, + /* 8082 */ 'v', 'c', 'l', 'z', 'w', 32, 0, + /* 8089 */ 'e', 'v', 'c', 'n', 't', 'l', 'z', 'w', 32, 0, + /* 8099 */ 'l', 'x', 'v', 'd', '2', 'x', 32, 0, + /* 8107 */ 's', 't', 'x', 'v', 'd', '2', 'x', 32, 0, + /* 8116 */ 'l', 'x', 'v', 'w', '4', 'x', 32, 0, + /* 8124 */ 's', 't', 'x', 'v', 'w', '4', 'x', 32, 0, + /* 8133 */ 'l', 'h', 'a', 'x', 32, 0, + /* 8139 */ 't', 'l', 'b', 'i', 'v', 'a', 'x', 32, 0, + /* 8148 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 32, 0, + /* 8158 */ 'l', 'w', 'a', 'x', 32, 0, + /* 8164 */ 'l', 'v', 'e', 'b', 'x', 32, 0, + /* 8171 */ 's', 't', 'v', 'e', 'b', 'x', 32, 0, + /* 8179 */ 's', 't', 'b', 'x', 32, 0, + /* 8185 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 32, 0, + /* 8194 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 32, 0, + /* 8204 */ 'e', 'v', 'l', 'd', 'd', 'x', 32, 0, + /* 8212 */ 'e', 'v', 's', 't', 'd', 'd', 'x', 32, 0, + /* 8221 */ 'q', 'v', 'l', 'f', 'd', 'x', 32, 0, + /* 8229 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 32, 0, + /* 8238 */ 'q', 'v', 'l', 'p', 'c', 'l', 'd', 'x', 32, 0, + /* 8248 */ 'q', 'v', 'l', 'p', 'c', 'r', 'd', 'x', 32, 0, + /* 8258 */ 'l', 'x', 's', 'd', 'x', 32, 0, + /* 8265 */ 's', 't', 'x', 's', 'd', 'x', 32, 0, + /* 8273 */ 's', 't', 'd', 'x', 32, 0, + /* 8279 */ 'e', 'v', 'l', 'w', 'h', 'e', 'x', 32, 0, + /* 8288 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 'x', 32, 0, + /* 8298 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 'x', 32, 0, + /* 8308 */ 'e', 'v', 'l', 'd', 'h', 'x', 32, 0, + /* 8316 */ 'e', 'v', 's', 't', 'd', 'h', 'x', 32, 0, + /* 8325 */ 'l', 'v', 'e', 'h', 'x', 32, 0, + /* 8332 */ 's', 't', 'v', 'e', 'h', 'x', 32, 0, + /* 8340 */ 's', 't', 'h', 'x', 32, 0, + /* 8346 */ 's', 't', 'b', 'c', 'i', 'x', 32, 0, + /* 8354 */ 'l', 'd', 'c', 'i', 'x', 32, 0, + /* 8361 */ 's', 't', 'd', 'c', 'i', 'x', 32, 0, + /* 8369 */ 's', 't', 'h', 'c', 'i', 'x', 32, 0, + /* 8377 */ 's', 't', 'w', 'c', 'i', 'x', 32, 0, + /* 8385 */ 'l', 'b', 'z', 'c', 'i', 'x', 32, 0, + /* 8393 */ 'l', 'h', 'z', 'c', 'i', 'x', 32, 0, + /* 8401 */ 'l', 'w', 'z', 'c', 'i', 'x', 32, 0, + /* 8409 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 'x', 32, 0, + /* 8419 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 'x', 32, 0, + /* 8429 */ 'v', 'u', 'p', 'k', 'h', 'p', 'x', 32, 0, + /* 8438 */ 'v', 'p', 'k', 'p', 'x', 32, 0, + /* 8445 */ 'v', 'u', 'p', 'k', 'l', 'p', 'x', 32, 0, + /* 8454 */ 'l', 'd', 'a', 'r', 'x', 32, 0, + /* 8461 */ 'l', 'w', 'a', 'r', 'x', 32, 0, + /* 8468 */ 'l', 'd', 'b', 'r', 'x', 32, 0, + /* 8475 */ 's', 't', 'd', 'b', 'r', 'x', 32, 0, + /* 8483 */ 'l', 'h', 'b', 'r', 'x', 32, 0, + /* 8490 */ 's', 't', 'h', 'b', 'r', 'x', 32, 0, + /* 8498 */ 'l', 'w', 'b', 'r', 'x', 32, 0, + /* 8505 */ 's', 't', 'w', 'b', 'r', 'x', 32, 0, + /* 8513 */ 't', 'l', 'b', 's', 'x', 32, 0, + /* 8520 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 32, 0, + /* 8529 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 32, 0, + /* 8539 */ 'l', 'x', 'v', 'd', 's', 'x', 32, 0, + /* 8547 */ 'v', 'c', 'f', 's', 'x', 32, 0, + /* 8554 */ 'q', 'v', 'l', 'f', 's', 'x', 32, 0, + /* 8562 */ 'q', 'v', 's', 't', 'f', 's', 'x', 32, 0, + /* 8571 */ 'q', 'v', 'l', 'p', 'c', 'l', 's', 'x', 32, 0, + /* 8581 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 'x', 32, 0, + /* 8591 */ 'q', 'v', 'l', 'p', 'c', 'r', 's', 'x', 32, 0, + /* 8601 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 'x', 32, 0, + /* 8615 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 'x', 32, 0, + /* 8628 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 'x', 32, 0, + /* 8643 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 'x', 32, 0, + /* 8658 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 'x', 32, 0, + /* 8671 */ 'l', 'h', 'a', 'u', 'x', 32, 0, + /* 8678 */ 'l', 'w', 'a', 'u', 'x', 32, 0, + /* 8685 */ 's', 't', 'b', 'u', 'x', 32, 0, + /* 8692 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 32, 0, + /* 8702 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 32, 0, + /* 8713 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 32, 0, + /* 8722 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 32, 0, + /* 8732 */ 'l', 'd', 'u', 'x', 32, 0, + /* 8738 */ 's', 't', 'd', 'u', 'x', 32, 0, + /* 8745 */ 'v', 'c', 'f', 'u', 'x', 32, 0, + /* 8752 */ 's', 't', 'h', 'u', 'x', 32, 0, + /* 8759 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 'x', 32, 0, + /* 8769 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 32, 0, + /* 8779 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 32, 0, + /* 8790 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 32, 0, + /* 8799 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 32, 0, + /* 8809 */ 's', 't', 'w', 'u', 'x', 32, 0, + /* 8816 */ 'l', 'b', 'z', 'u', 'x', 32, 0, + /* 8823 */ 'l', 'h', 'z', 'u', 'x', 32, 0, + /* 8830 */ 'l', 'w', 'z', 'u', 'x', 32, 0, + /* 8837 */ 'l', 'v', 'x', 32, 0, + /* 8842 */ 's', 't', 'v', 'x', 32, 0, + /* 8848 */ 'e', 'v', 'l', 'd', 'w', 'x', 32, 0, + /* 8856 */ 'e', 'v', 's', 't', 'd', 'w', 'x', 32, 0, + /* 8865 */ 'l', 'v', 'e', 'w', 'x', 32, 0, + /* 8872 */ 's', 't', 'v', 'e', 'w', 'x', 32, 0, + /* 8880 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 32, 0, + /* 8890 */ 's', 't', 'w', 'x', 32, 0, + /* 8896 */ 'l', 'b', 'z', 'x', 32, 0, + /* 8902 */ 'l', 'h', 'z', 'x', 32, 0, + /* 8908 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 32, 0, + /* 8918 */ 'l', 'w', 'z', 'x', 32, 0, + /* 8924 */ 'd', 'c', 'b', 'z', 32, 0, + /* 8930 */ 'l', 'b', 'z', 32, 0, + /* 8935 */ 'b', 'd', 'z', 32, 0, + /* 8940 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'z', 32, 0, + /* 8950 */ 'l', 'h', 'z', 32, 0, + /* 8955 */ 'v', 'r', 'f', 'i', 'z', 32, 0, + /* 8962 */ 'x', 's', 'r', 'd', 'p', 'i', 'z', 32, 0, + /* 8971 */ 'x', 'v', 'r', 'd', 'p', 'i', 'z', 32, 0, + /* 8980 */ 'x', 'v', 'r', 's', 'p', 'i', 'z', 32, 0, + /* 8989 */ 'q', 'v', 'f', 'r', 'i', 'z', 32, 0, + /* 8997 */ 'b', 'd', 'n', 'z', 32, 0, + /* 9003 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 'z', 32, 0, + /* 9014 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 'z', 32, 0, + /* 9025 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'z', 32, 0, + /* 9035 */ 'l', 'w', 'z', 32, 0, + /* 9040 */ 'b', 'd', 'z', 'l', 'r', 'l', '+', 0, + /* 9048 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '+', 0, + /* 9057 */ 'b', 'd', 'z', 'l', 'r', '+', 0, + /* 9064 */ 'b', 'd', 'n', 'z', 'l', 'r', '+', 0, + /* 9072 */ 'b', 'd', 'z', 'l', 'r', 'l', '-', 0, + /* 9080 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '-', 0, + /* 9089 */ 'b', 'd', 'z', 'l', 'r', '-', 0, + /* 9096 */ 'b', 'd', 'n', 'z', 'l', 'r', '-', 0, + /* 9104 */ 'o', 'r', 'i', 32, '1', ',', 32, '1', ',', 32, '0', 0, + /* 9116 */ 'o', 'r', 'i', 32, '2', ',', 32, '2', ',', 32, '0', 0, + /* 9128 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', '3', '2', 0, + /* 9145 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, + /* 9166 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, + /* 9187 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, + /* 9209 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, + /* 9230 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, + /* 9247 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, + /* 9268 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, + /* 9288 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', '3', '2', 0, + /* 9302 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', '3', '2', 0, + /* 9316 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, + /* 9331 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, + /* 9346 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '3', '2', 0, + /* 9365 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '3', '2', 0, + /* 9383 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, + /* 9401 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, + /* 9419 */ 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', '3', '2', 0, + /* 9434 */ 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', '3', '2', 0, + /* 9447 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0, + /* 9468 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0, + /* 9489 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0, + /* 9511 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, + /* 9528 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, + /* 9549 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0, + /* 9570 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0, + /* 9590 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '6', '4', 0, + /* 9609 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '6', '4', 0, + /* 9627 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'i', '6', '4', 0, + /* 9648 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '4', 0, + /* 9662 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '4', 0, + /* 9673 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '4', 0, + /* 9687 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '4', 0, + /* 9698 */ 'c', 'r', 'x', 'o', 'r', 32, '6', ',', 32, '6', ',', 32, '6', 0, + /* 9712 */ 'c', 'r', 'e', 'q', 'v', 32, '6', ',', 32, '6', ',', 32, '6', 0, + /* 9726 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0, + /* 9747 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0, + /* 9768 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0, + /* 9790 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0, + /* 9811 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, + /* 9828 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0, + /* 9849 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0, + /* 9869 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', '8', 0, + /* 9880 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '8', 0, + /* 9894 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '8', 0, + /* 9905 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0, + /* 9925 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '8', 0, + /* 9939 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0, + /* 9959 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0, + /* 9980 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0, + /* 10000 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, + /* 10020 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, + /* 10039 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, + /* 10058 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '8', 0, + /* 10069 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', '8', 0, + /* 10082 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', '8', 0, + /* 10099 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', '8', 0, + /* 10116 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'i', '8', 0, + /* 10132 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', 0, + /* 10144 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'g', 'd', 'H', 'A', 0, + /* 10158 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'l', 'd', 'H', 'A', 0, + /* 10172 */ '#', 'A', 'D', 'D', 'I', 'S', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'H', 'A', 0, + /* 10189 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', 0, + /* 10204 */ '#', 'R', 'e', 'a', 'd', 'T', 'B', 0, + /* 10212 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0, + /* 10222 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'B', 'R', 'C', 0, + /* 10238 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'B', 'R', 'C', 0, + /* 10251 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'R', 'C', 0, + /* 10267 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'F', 'R', 'C', 0, + /* 10280 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'F', 'R', 'C', 0, + /* 10297 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'F', 'R', 'C', 0, + /* 10311 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'R', 'R', 'C', 0, + /* 10327 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'R', 'R', 'C', 0, + /* 10340 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'S', 'R', 'C', 0, + /* 10356 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'S', 'R', 'C', 0, + /* 10369 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'R', 'C', 0, + /* 10385 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'R', 'C', 0, + /* 10398 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 10411 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 10418 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 10428 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, + /* 10444 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, + /* 10458 */ '#', 'L', 'D', 't', 'o', 'c', 'J', 'T', 'I', 0, + /* 10468 */ '#', 'L', 'D', 't', 'o', 'c', 'L', 0, + /* 10476 */ '#', 'A', 'D', 'D', 'I', 't', 'o', 'c', 'L', 0, + /* 10486 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 0, + /* 10498 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 0, + /* 10510 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', 0, + /* 10523 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', 0, + /* 10536 */ '#', 'U', 'p', 'd', 'a', 't', 'e', 'G', 'B', 'R', 0, + /* 10547 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 0, + /* 10559 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 0, + /* 10569 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', 0, + /* 10585 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', 0, + /* 10601 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', 0, + /* 10615 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', 0, + /* 10627 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', 0, + /* 10639 */ '#', 'M', 'o', 'v', 'e', 'G', 'O', 'T', 't', 'o', 'L', 'R', 0, + /* 10652 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 'B', 'I', 'T', 0, + /* 10667 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 'B', 'I', 'T', 0, + /* 10680 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', 0, + /* 10696 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', 0, + /* 10712 */ '#', 'P', 'P', 'C', '3', '2', 'G', 'O', 'T', 0, + /* 10722 */ '#', 'P', 'P', 'C', '3', '2', 'P', 'I', 'C', 'G', 'O', 'T', 0, + /* 10735 */ '#', 'L', 'D', 't', 'o', 'c', 'C', 'P', 'T', 0, + /* 10745 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 10760 */ 's', 'l', 'b', 'i', 'a', 0, + /* 10766 */ 't', 'l', 'b', 'i', 'a', 0, + /* 10772 */ 'b', 0, + /* 10774 */ 't', 'l', 'b', 's', 'y', 'n', 'c', 0, + /* 10782 */ 'i', 's', 'y', 'n', 'c', 0, + /* 10788 */ 'm', 's', 'y', 'n', 'c', 0, + /* 10794 */ '#', 'L', 'D', 't', 'o', 'c', 0, + /* 10801 */ '#', 'L', 'W', 'Z', 't', 'o', 'c', 0, + /* 10809 */ 'r', 'f', 'i', 'd', 0, + /* 10814 */ 't', 'l', 'b', 'r', 'e', 0, + /* 10820 */ 't', 'l', 'b', 'w', 'e', 0, + /* 10826 */ 'r', 'f', 'c', 'i', 0, + /* 10831 */ 'r', 'f', 'm', 'c', 'i', 0, + /* 10837 */ 'r', 'f', 'd', 'i', 0, + /* 10842 */ 'r', 'f', 'i', 0, + /* 10846 */ 'd', 's', 's', 'a', 'l', 'l', 0, + /* 10853 */ 'b', 'l', 'r', 'l', 0, + /* 10858 */ 'b', 'd', 'z', 'l', 'r', 'l', 0, + /* 10865 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0, + /* 10873 */ 'b', 'c', 't', 'r', 'l', 0, + /* 10879 */ 'a', 't', 't', 'n', 0, + /* 10884 */ 'e', 'i', 'e', 'i', 'o', 0, + /* 10890 */ 't', 'r', 'a', 'p', 0, + /* 10895 */ 'n', 'o', 'p', 0, + /* 10899 */ 'b', 'l', 'r', 0, + /* 10903 */ 'b', 'd', 'z', 'l', 'r', 0, + /* 10909 */ 'b', 'd', 'n', 'z', 'l', 'r', 0, + /* 10916 */ 'b', 'c', 't', 'r', 0, + }; +#endif + + // Emit the opcode for the instruction. + unsigned int opcode = MCInst_getOpcode(MI); + uint64_t Bits1 = OpInfo[opcode]; + uint64_t Bits2 = OpInfo2[opcode]; + uint64_t Bits = (Bits2 << 32) | Bits1; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 16383)-1); +#endif + + // Fragment 0 encoded into 4 bits for 14 unique commands. + //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); + switch ((Bits >> 14) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, ADDISdtprelHA, ADDISd... + return; + break; + case 1: + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + printOperand(MI, 0, O); + break; + case 2: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP + printU16ImmOperand(MI, 0, O); + break; + case 3: + // B, BCLalways, BDNZ, BDNZ8, BDNZL, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ, B... + printBranchOperand(MI, 0, O); + break; + case 4: + // BA, BDNZA, BDNZAm, BDNZAp, BDNZLA, BDNZLAm, BDNZLAp, BDZA, BDZAm, BDZA... + printAbsBranchOperand(MI, 0, O); + break; + case 5: + // BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC... + printPredicateOperand(MI, 0, O, "cc"); + break; + case 6: + // BCTRL8_LDinto_toc + printMemRegImm(MI, 0, O); + return; + break; + case 7: + // BL8_NOP_TLS, BL8_TLS, BL8_TLS_, BL_TLS + printTLSCall(MI, 0, O); + break; + case 8: + // DCBA, DCBF, DCBI, DCBST, DCBT, DCBTST, DCBZ, DCBZL, ICBI + printMemRegReg(MI, 0, O); + return; + break; + case 9: + // DSS, MBAR, MTFSB0, MTFSB1, TD, TDI, TW, TWI, gBC, gBCA, gBCCTR, gBCCTR... + printU5ImmOperand(MI, 0, O); + break; + case 10: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTDCR, MTV... + printOperand(MI, 1, O); + break; + case 11: + // ICBT + printU4ImmOperand(MI, 0, O); + SStream_concat0(O, ", "); + printMemRegReg(MI, 1, O); + return; + break; + case 12: + // MTOCRF, MTOCRF8 + printcrbitm(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 13: + // MTSR + printU4ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 5 bits for 18 unique commands. + //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); + switch ((Bits >> 18) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + SStream_concat0(O, ", "); + break; + case 1: + // ADJCALLSTACKDOWN, B, BA, BCLalways, BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp... + return; + break; + case 2: + // ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, ... + SStream_concat0(O, " "); + break; + case 3: + // BCC + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printBranchOperand(MI, 2, O); + return; + break; + case 4: + // BCCA + SStream_concat0(O, "a"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printAbsBranchOperand(MI, 2, O); + return; + break; + case 5: + // BCCCTR, BCCCTR8 + SStream_concat0(O, "ctr"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + return; + break; + case 6: + // BCCCTRL, BCCCTRL8 + SStream_concat0(O, "ctrl"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + return; + break; + case 7: + // BCCL + SStream_concat0(O, "l"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printBranchOperand(MI, 2, O); + return; + break; + case 8: + // BCCLA + SStream_concat0(O, "la"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printAbsBranchOperand(MI, 2, O); + return; + break; + case 9: + // BCCLR + SStream_concat0(O, "lr"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + return; + break; + case 10: + // BCCLRL + SStream_concat0(O, "lrl"); + printPredicateOperand(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand(MI, 0, O, "reg"); + return; + break; + case 11: + // BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, BC... + SStream_concat0(O, ", 0"); + return; + break; + case 12: + // BL8_NOP, BL8_NOP_TLS, BLA8_NOP + SStream_concat0(O, "\n\tnop"); // qq + return; + break; + case 13: + // MFTB8 + SStream_concat0(O, ", 268"); + op_addImm(MI, 268); + return; + break; + case 14: + // MFVRSAVE, MFVRSAVEv + SStream_concat0(O, ", 256"); + op_addImm(MI, 256); + return; + break; + case 15: + // QVLPCLSXint + SStream_concat0(O, ", 0, "); + op_addImm(MI, 0); + printOperand(MI, 1, O); + return; + break; + case 16: + // TLBIE + SStream_concat0(O, ","); + printOperand(MI, 0, O); + return; + break; + case 17: + // V_SETALLONES, V_SETALLONESB, V_SETALLONESH + SStream_concat0(O, ", -1"); + op_addImm(MI, -1); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 17 unique commands. + //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 31); + switch ((Bits >> 23) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + printOperand(MI, 1, O); + break; + case 1: + // ADJCALLSTACKUP + printU16ImmOperand(MI, 1, O); + return; + break; + case 2: + // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, LBZX, LBZX8, LDARX, LDBRX, L... + printMemRegReg(MI, 1, O); + break; + case 3: + // BC, BCL, BCLn, BCn + printBranchOperand(MI, 1, O); + return; + break; + case 4: + // CRSET, CRUNSET, MTDCR, V_SET0, V_SET0B, V_SET0H + printOperand(MI, 0, O); + break; + case 5: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, RLDIMI, RL... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // EVADDIW + printU5ImmOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 7: + // EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVLWHE, ... + printMemRegImm(MI, 1, O); + return; + break; + case 8: + // EVSUBIFW + printU5ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 9: + // LA + printS16ImmOperand(MI, 2, O); + SStream_concat0(O, "("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 10: + // LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S... + printMemRegImm(MI, 2, O); + return; + break; + case 11: + // LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX... + printMemRegReg(MI, 2, O); + return; + break; + case 12: + // LI, LI8, LIS, LIS8 + printS16ImmOperand(MI, 1, O); + return; + break; + case 13: + // MFOCRF, MFOCRF8 + printcrbitm(MI, 1, O); + return; + break; + case 14: + // MFSR + printU4ImmOperand(MI, 1, O); + return; + break; + case 15: + // QVGPCI + printU12ImmOperand(MI, 1, O); + return; + break; + case 16: + // VSPLTISB, VSPLTISH, VSPLTISW + printS5ImmOperand(MI, 1, O); + return; + break; + } + + + // Fragment 3 encoded into 4 bits for 9 unique commands. + //printf("Frag-3: %"PRIu64"\n", (Bits >> 28) & 15); + switch ((Bits >> 28) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + SStream_concat0(O, ", "); + break; + case 1: + // ADDME, ADDME8, ADDME8o, ADDMEo, ADDZE, ADDZE8, ADDZE8o, ADDZEo, CNTLZD... + return; + break; + case 2: + // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32 + SStream_concat0(O, " "); + printOperand(MI, 3, O); + SStream_concat0(O, " "); + printOperand(MI, 4, O); + return; + break; + case 3: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64 + printU5ImmOperand(MI, 0, O); + return; + break; + case 4: + // RLDIMI, RLDIMIo + printU6ImmOperand(MI, 3, O); + SStream_concat0(O, ", "); + printU6ImmOperand(MI, 4, O); + return; + break; + case 5: + // RLWIMI, RLWIMI8, RLWIMI8o, RLWIMIo + printU5ImmOperand(MI, 3, O); + SStream_concat0(O, ", "); + printU5ImmOperand(MI, 4, O); + SStream_concat0(O, ", "); + printU5ImmOperand(MI, 5, O); + return; + break; + case 6: + // VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW + printU5ImmOperand(MI, 1, O); + return; + break; + case 7: + // VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0 + SStream_concat0(O, ", 0"); + return; + break; + case 8: + // XSMADDADP, XSMADDMDP, XSMSUBADP, XSMSUBMDP, XSNMADDADP, XSNMADDMDP, XS... + printOperand(MI, 3, O); + return; + break; + } + + + // Fragment 4 encoded into 4 bits for 10 unique commands. + //printf("Frag-4: %"PRIu64"\n", (Bits >> 32) & 15); + switch ((Bits >> 32) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + printOperand(MI, 2, O); + break; + case 1: + // ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, ADDIS, ADDIS8, CMPDI, CMPWI, MULLI... + printS16ImmOperand(MI, 2, O); + return; + break; + case 2: + // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8... + printU16ImmOperand(MI, 2, O); + return; + break; + case 3: + // CLRLSLDI, CLRLSLDIo, CLRRDI, CLRRDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo... + printU6ImmOperand(MI, 2, O); + break; + case 4: + // CLRLSLWI, CLRLSLWIo, CLRRWI, CLRRWIo, EVRLWI, EVSLWI, EVSRWIS, EVSRWIU... + printU5ImmOperand(MI, 2, O); + break; + case 5: + // CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H + printOperand(MI, 0, O); + return; + break; + case 6: + // QVESPLATI, QVESPLATIb, QVESPLATIs, XXSPLTW + printU2ImmOperand(MI, 2, O); + return; + break; + case 7: + // QVFMADD, QVFMADDS, QVFMADDSs, QVFMSUB, QVFMSUBS, QVFMSUBSs, QVFNMADD, ... + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 8: + // gBC, gBCL + printBranchOperand(MI, 2, O); + return; + break; + case 9: + // gBCA, gBCLA + printAbsBranchOperand(MI, 2, O); + return; + break; + } + + + // Fragment 5 encoded into 1 bits for 2 unique commands. + //printf("Frag-5: %"PRIu64"\n", (Bits >> 36) & 1); + if ((Bits >> 36) & 1) { + // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, EXTLDI, EXTLDIo, EXTLWI, EXT... + SStream_concat0(O, ", "); + } else { + // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... + return; + } + + + // Fragment 6 encoded into 3 bits for 5 unique commands. + //printf("Frag-6: %"PRIu64"\n", (Bits >> 37) & 7); + switch ((Bits >> 37) & 7) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // CLRLSLDI, CLRLSLDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo, INSRDI, INSRDIo... + printU6ImmOperand(MI, 3, O); + return; + break; + case 1: + // CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo... + printU5ImmOperand(MI, 3, O); + break; + case 2: + // FMADD, FMADDS, FMADDSo, FMADDo, FMSUB, FMSUBS, FMSUBSo, FMSUBo, FNMADD... + printOperand(MI, 3, O); + return; + break; + case 3: + // QVALIGNI, QVALIGNIb, QVALIGNIs, XXPERMDI, XXSLDWI + printU2ImmOperand(MI, 3, O); + return; + break; + case 4: + // QVFLOGICAL, QVFLOGICALb, QVFLOGICALs + printU12ImmOperand(MI, 3, O); + return; + break; + } + + + // Fragment 7 encoded into 1 bits for 2 unique commands. + //printf("Frag-7: %"PRIu64"\n", (Bits >> 40) & 1); + if ((Bits >> 40) & 1) { + // RLWINM, RLWINM8, RLWINM8o, RLWINMo, RLWNM, RLWNM8, RLWNM8o, RLWNMo + SStream_concat0(O, ", "); + printU5ImmOperand(MI, 4, O); + return; + } else { + // CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo... + return; + } +} + + +#ifndef CAPSTONE_DIET +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 310 && "Invalid register number!"); + + static const char AsmStrs[] = { + /* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0, + /* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0, + /* 36 */ '*', '*', 'B', 'A', 'S', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0, + /* 53 */ 'f', '1', '0', 0, + /* 57 */ 'q', '1', '0', 0, + /* 61 */ 'r', '1', '0', 0, + /* 65 */ 'v', 's', '1', '0', 0, + /* 70 */ 'v', '1', '0', 0, + /* 74 */ 'f', '2', '0', 0, + /* 78 */ 'q', '2', '0', 0, + /* 82 */ 'r', '2', '0', 0, + /* 86 */ 'v', 's', '2', '0', 0, + /* 91 */ 'v', '2', '0', 0, + /* 95 */ 'f', '3', '0', 0, + /* 99 */ 'q', '3', '0', 0, + /* 103 */ 'r', '3', '0', 0, + /* 107 */ 'v', 's', '3', '0', 0, + /* 112 */ 'v', '3', '0', 0, + /* 116 */ 'v', 's', '4', '0', 0, + /* 121 */ 'v', 's', '5', '0', 0, + /* 126 */ 'v', 's', '6', '0', 0, + /* 131 */ 'f', '0', 0, + /* 134 */ 'q', '0', 0, + /* 137 */ 'c', 'r', '0', 0, + /* 141 */ 'v', 's', '0', 0, + /* 145 */ 'v', '0', 0, + /* 148 */ 'f', '1', '1', 0, + /* 152 */ 'q', '1', '1', 0, + /* 156 */ 'r', '1', '1', 0, + /* 160 */ 'v', 's', '1', '1', 0, + /* 165 */ 'v', '1', '1', 0, + /* 169 */ 'f', '2', '1', 0, + /* 173 */ 'q', '2', '1', 0, + /* 177 */ 'r', '2', '1', 0, + /* 181 */ 'v', 's', '2', '1', 0, + /* 186 */ 'v', '2', '1', 0, + /* 190 */ 'f', '3', '1', 0, + /* 194 */ 'q', '3', '1', 0, + /* 198 */ 'r', '3', '1', 0, + /* 202 */ 'v', 's', '3', '1', 0, + /* 207 */ 'v', '3', '1', 0, + /* 211 */ 'v', 's', '4', '1', 0, + /* 216 */ 'v', 's', '5', '1', 0, + /* 221 */ 'v', 's', '6', '1', 0, + /* 226 */ 'f', '1', 0, + /* 229 */ 'q', '1', 0, + /* 232 */ 'c', 'r', '1', 0, + /* 236 */ 'v', 's', '1', 0, + /* 240 */ 'v', '1', 0, + /* 243 */ 'f', '1', '2', 0, + /* 247 */ 'q', '1', '2', 0, + /* 251 */ 'r', '1', '2', 0, + /* 255 */ 'v', 's', '1', '2', 0, + /* 260 */ 'v', '1', '2', 0, + /* 264 */ 'f', '2', '2', 0, + /* 268 */ 'q', '2', '2', 0, + /* 272 */ 'r', '2', '2', 0, + /* 276 */ 'v', 's', '2', '2', 0, + /* 281 */ 'v', '2', '2', 0, + /* 285 */ 'v', 's', '3', '2', 0, + /* 290 */ 'v', 's', '4', '2', 0, + /* 295 */ 'v', 's', '5', '2', 0, + /* 300 */ 'v', 's', '6', '2', 0, + /* 305 */ 'f', '2', 0, + /* 308 */ 'q', '2', 0, + /* 311 */ 'c', 'r', '2', 0, + /* 315 */ 'v', 's', '2', 0, + /* 319 */ 'v', '2', 0, + /* 322 */ 'f', '1', '3', 0, + /* 326 */ 'q', '1', '3', 0, + /* 330 */ 'r', '1', '3', 0, + /* 334 */ 'v', 's', '1', '3', 0, + /* 339 */ 'v', '1', '3', 0, + /* 343 */ 'f', '2', '3', 0, + /* 347 */ 'q', '2', '3', 0, + /* 351 */ 'r', '2', '3', 0, + /* 355 */ 'v', 's', '2', '3', 0, + /* 360 */ 'v', '2', '3', 0, + /* 364 */ 'v', 's', '3', '3', 0, + /* 369 */ 'v', 's', '4', '3', 0, + /* 374 */ 'v', 's', '5', '3', 0, + /* 379 */ 'v', 's', '6', '3', 0, + /* 384 */ 'f', '3', 0, + /* 387 */ 'q', '3', 0, + /* 390 */ 'c', 'r', '3', 0, + /* 394 */ 'v', 's', '3', 0, + /* 398 */ 'v', '3', 0, + /* 401 */ 'f', '1', '4', 0, + /* 405 */ 'q', '1', '4', 0, + /* 409 */ 'r', '1', '4', 0, + /* 413 */ 'v', 's', '1', '4', 0, + /* 418 */ 'v', '1', '4', 0, + /* 422 */ 'f', '2', '4', 0, + /* 426 */ 'q', '2', '4', 0, + /* 430 */ 'r', '2', '4', 0, + /* 434 */ 'v', 's', '2', '4', 0, + /* 439 */ 'v', '2', '4', 0, + /* 443 */ 'v', 's', '3', '4', 0, + /* 448 */ 'v', 's', '4', '4', 0, + /* 453 */ 'v', 's', '5', '4', 0, + /* 458 */ 'f', '4', 0, + /* 461 */ 'q', '4', 0, + /* 464 */ 'c', 'r', '4', 0, + /* 468 */ 'v', 's', '4', 0, + /* 472 */ 'v', '4', 0, + /* 475 */ 'f', '1', '5', 0, + /* 479 */ 'q', '1', '5', 0, + /* 483 */ 'r', '1', '5', 0, + /* 487 */ 'v', 's', '1', '5', 0, + /* 492 */ 'v', '1', '5', 0, + /* 496 */ 'f', '2', '5', 0, + /* 500 */ 'q', '2', '5', 0, + /* 504 */ 'r', '2', '5', 0, + /* 508 */ 'v', 's', '2', '5', 0, + /* 513 */ 'v', '2', '5', 0, + /* 517 */ 'v', 's', '3', '5', 0, + /* 522 */ 'v', 's', '4', '5', 0, + /* 527 */ 'v', 's', '5', '5', 0, + /* 532 */ 'f', '5', 0, + /* 535 */ 'q', '5', 0, + /* 538 */ 'c', 'r', '5', 0, + /* 542 */ 'v', 's', '5', 0, + /* 546 */ 'v', '5', 0, + /* 549 */ 'f', '1', '6', 0, + /* 553 */ 'q', '1', '6', 0, + /* 557 */ 'r', '1', '6', 0, + /* 561 */ 'v', 's', '1', '6', 0, + /* 566 */ 'v', '1', '6', 0, + /* 570 */ 'f', '2', '6', 0, + /* 574 */ 'q', '2', '6', 0, + /* 578 */ 'r', '2', '6', 0, + /* 582 */ 'v', 's', '2', '6', 0, + /* 587 */ 'v', '2', '6', 0, + /* 591 */ 'v', 's', '3', '6', 0, + /* 596 */ 'v', 's', '4', '6', 0, + /* 601 */ 'v', 's', '5', '6', 0, + /* 606 */ 'f', '6', 0, + /* 609 */ 'q', '6', 0, + /* 612 */ 'c', 'r', '6', 0, + /* 616 */ 'v', 's', '6', 0, + /* 620 */ 'v', '6', 0, + /* 623 */ 'f', '1', '7', 0, + /* 627 */ 'q', '1', '7', 0, + /* 631 */ 'r', '1', '7', 0, + /* 635 */ 'v', 's', '1', '7', 0, + /* 640 */ 'v', '1', '7', 0, + /* 644 */ 'f', '2', '7', 0, + /* 648 */ 'q', '2', '7', 0, + /* 652 */ 'r', '2', '7', 0, + /* 656 */ 'v', 's', '2', '7', 0, + /* 661 */ 'v', '2', '7', 0, + /* 665 */ 'v', 's', '3', '7', 0, + /* 670 */ 'v', 's', '4', '7', 0, + /* 675 */ 'v', 's', '5', '7', 0, + /* 680 */ 'f', '7', 0, + /* 683 */ 'q', '7', 0, + /* 686 */ 'c', 'r', '7', 0, + /* 690 */ 'v', 's', '7', 0, + /* 694 */ 'v', '7', 0, + /* 697 */ 'f', '1', '8', 0, + /* 701 */ 'q', '1', '8', 0, + /* 705 */ 'r', '1', '8', 0, + /* 709 */ 'v', 's', '1', '8', 0, + /* 714 */ 'v', '1', '8', 0, + /* 718 */ 'f', '2', '8', 0, + /* 722 */ 'q', '2', '8', 0, + /* 726 */ 'r', '2', '8', 0, + /* 730 */ 'v', 's', '2', '8', 0, + /* 735 */ 'v', '2', '8', 0, + /* 739 */ 'v', 's', '3', '8', 0, + /* 744 */ 'v', 's', '4', '8', 0, + /* 749 */ 'v', 's', '5', '8', 0, + /* 754 */ 'f', '8', 0, + /* 757 */ 'q', '8', 0, + /* 760 */ 'r', '8', 0, + /* 763 */ 'v', 's', '8', 0, + /* 767 */ 'v', '8', 0, + /* 770 */ 'f', '1', '9', 0, + /* 774 */ 'q', '1', '9', 0, + /* 778 */ 'r', '1', '9', 0, + /* 782 */ 'v', 's', '1', '9', 0, + /* 787 */ 'v', '1', '9', 0, + /* 791 */ 'f', '2', '9', 0, + /* 795 */ 'q', '2', '9', 0, + /* 799 */ 'r', '2', '9', 0, + /* 803 */ 'v', 's', '2', '9', 0, + /* 808 */ 'v', '2', '9', 0, + /* 812 */ 'v', 's', '3', '9', 0, + /* 817 */ 'v', 's', '4', '9', 0, + /* 822 */ 'v', 's', '5', '9', 0, + /* 827 */ 'f', '9', 0, + /* 830 */ 'q', '9', 0, + /* 833 */ 'r', '9', 0, + /* 836 */ 'v', 's', '9', 0, + /* 840 */ 'v', '9', 0, + /* 843 */ 'c', 'a', 0, + /* 846 */ 'v', 'r', 's', 'a', 'v', 'e', 0, + /* 853 */ 'l', 'r', 0, + /* 856 */ 'c', 't', 'r', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 36, 843, 856, 18, 853, 0, 846, 55, 36, 137, 232, 311, 390, 464, + 538, 612, 686, 856, 131, 226, 305, 384, 458, 532, 606, 680, 754, 827, + 53, 148, 243, 322, 401, 475, 549, 623, 697, 770, 74, 169, 264, 343, + 422, 496, 570, 644, 718, 791, 95, 190, 18, 853, 134, 229, 308, 387, + 461, 535, 609, 683, 757, 830, 57, 152, 247, 326, 405, 479, 553, 627, + 701, 774, 78, 173, 268, 347, 426, 500, 574, 648, 722, 795, 99, 194, + 138, 233, 312, 391, 465, 539, 613, 687, 760, 833, 61, 156, 251, 330, + 409, 483, 557, 631, 705, 778, 82, 177, 272, 351, 430, 504, 578, 652, + 726, 799, 103, 198, 145, 240, 319, 398, 472, 546, 620, 694, 767, 840, + 70, 165, 260, 339, 418, 492, 566, 640, 714, 787, 91, 186, 281, 360, + 439, 513, 587, 661, 735, 808, 112, 207, 285, 364, 443, 517, 591, 665, + 739, 812, 116, 211, 290, 369, 448, 522, 596, 670, 744, 817, 121, 216, + 295, 374, 453, 527, 601, 675, 749, 822, 126, 221, 300, 379, 285, 364, + 443, 517, 591, 665, 739, 812, 116, 211, 290, 369, 448, 522, 596, 670, + 744, 817, 121, 216, 295, 374, 453, 527, 601, 675, 749, 822, 126, 221, + 300, 379, 141, 236, 315, 394, 468, 542, 616, 690, 763, 836, 65, 160, + 255, 334, 413, 487, 561, 635, 709, 782, 86, 181, 276, 355, 434, 508, + 582, 656, 730, 803, 107, 202, 138, 233, 312, 391, 465, 539, 613, 687, + 760, 833, 61, 156, 251, 330, 409, 483, 557, 631, 705, 778, 82, 177, + 272, 351, 430, 504, 578, 652, 726, 799, 103, 198, 55, 245, 551, 54, + 402, 698, 265, 571, 96, 150, 477, 772, 323, 624, 170, 497, 792, 55, + 403, 699, 244, 550, 75, 423, 719, 324, 625, 149, 476, 771, 344, 645, + 191, + }; + + //assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + // "Invalid alt name index for register!"); + //int i; + //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("*************************\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +} +#endif + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) +{ + switch (PrintMethodIdx) { + default: + // llvm_unreachable("Unknown PrintMethod kind"); + break; + case 0: + printBranchOperand(MI, OpIdx, OS); + break; + case 1: + printAbsBranchOperand(MI, OpIdx, OS); + break; + case 2: + printS16ImmOperand(MI, OpIdx, OS); + break; + case 3: + printU16ImmOperand(MI, OpIdx, OS); + break; + case 4: + printU6ImmOperand(MI, OpIdx, OS); + break; + case 5: + printU5ImmOperand(MI, OpIdx, OS); + break; + } +} + +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +{ + #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + const char *AsmString; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case PPC_BCC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 12, crrc:$cc, condbrtarget:$dst) + AsmString = "blt $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 12, CR0, condbrtarget:$dst) + AsmString = "blt $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 14, crrc:$cc, condbrtarget:$dst) + AsmString = "blt- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 14, CR0, condbrtarget:$dst) + AsmString = "blt- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 15, crrc:$cc, condbrtarget:$dst) + AsmString = "blt+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 15, CR0, condbrtarget:$dst) + AsmString = "blt+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 44, crrc:$cc, condbrtarget:$dst) + AsmString = "bgt $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 44, CR0, condbrtarget:$dst) + AsmString = "bgt $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 46, crrc:$cc, condbrtarget:$dst) + AsmString = "bgt- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 46, CR0, condbrtarget:$dst) + AsmString = "bgt- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 47, crrc:$cc, condbrtarget:$dst) + AsmString = "bgt+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 47, CR0, condbrtarget:$dst) + AsmString = "bgt+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 76, crrc:$cc, condbrtarget:$dst) + AsmString = "beq $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 76, CR0, condbrtarget:$dst) + AsmString = "beq $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 78, crrc:$cc, condbrtarget:$dst) + AsmString = "beq- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 78, CR0, condbrtarget:$dst) + AsmString = "beq- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 79, crrc:$cc, condbrtarget:$dst) + AsmString = "beq+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 79, CR0, condbrtarget:$dst) + AsmString = "beq+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 68, crrc:$cc, condbrtarget:$dst) + AsmString = "bne $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 68, CR0, condbrtarget:$dst) + AsmString = "bne $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 70, crrc:$cc, condbrtarget:$dst) + AsmString = "bne- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 70, CR0, condbrtarget:$dst) + AsmString = "bne- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCC 71, crrc:$cc, condbrtarget:$dst) + AsmString = "bne+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCC 71, CR0, condbrtarget:$dst) + AsmString = "bne+ $\xFF\x03\x01"; + break; + } + return NULL; + case PPC_BCCA: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 12, crrc:$cc, abscondbrtarget:$dst) + AsmString = "blta $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 12, CR0, abscondbrtarget:$dst) + AsmString = "blta $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 14, crrc:$cc, abscondbrtarget:$dst) + AsmString = "blta- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 14, CR0, abscondbrtarget:$dst) + AsmString = "blta- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 15, crrc:$cc, abscondbrtarget:$dst) + AsmString = "blta+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 15, CR0, abscondbrtarget:$dst) + AsmString = "blta+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 44, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgta $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 44, CR0, abscondbrtarget:$dst) + AsmString = "bgta $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 46, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgta- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 46, CR0, abscondbrtarget:$dst) + AsmString = "bgta- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 47, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgta+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 47, CR0, abscondbrtarget:$dst) + AsmString = "bgta+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 76, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqa $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 76, CR0, abscondbrtarget:$dst) + AsmString = "beqa $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 78, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqa- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 78, CR0, abscondbrtarget:$dst) + AsmString = "beqa- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 79, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqa+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 79, CR0, abscondbrtarget:$dst) + AsmString = "beqa+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 68, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnea $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 68, CR0, abscondbrtarget:$dst) + AsmString = "bnea $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 70, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnea- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 70, CR0, abscondbrtarget:$dst) + AsmString = "bnea- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCA 71, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnea+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCA 71, CR0, abscondbrtarget:$dst) + AsmString = "bnea+ $\xFF\x03\x02"; + break; + } + return NULL; + case PPC_BCCCTR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 12, crrc:$cc) + AsmString = "bltctr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 12, CR0) + AsmString = "bltctr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 14, crrc:$cc) + AsmString = "bltctr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 14, CR0) + AsmString = "bltctr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 15, crrc:$cc) + AsmString = "bltctr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 15, CR0) + AsmString = "bltctr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 44, crrc:$cc) + AsmString = "bgtctr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 44, CR0) + AsmString = "bgtctr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 46, crrc:$cc) + AsmString = "bgtctr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 46, CR0) + AsmString = "bgtctr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 47, crrc:$cc) + AsmString = "bgtctr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 47, CR0) + AsmString = "bgtctr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 76, crrc:$cc) + AsmString = "beqctr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 76, CR0) + AsmString = "beqctr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 78, crrc:$cc) + AsmString = "beqctr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 78, CR0) + AsmString = "beqctr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 79, crrc:$cc) + AsmString = "beqctr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 79, CR0) + AsmString = "beqctr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 68, crrc:$cc) + AsmString = "bnectr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 68, CR0) + AsmString = "bnectr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 70, crrc:$cc) + AsmString = "bnectr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 70, CR0) + AsmString = "bnectr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTR 71, crrc:$cc) + AsmString = "bnectr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTR 71, CR0) + AsmString = "bnectr+"; + break; + } + return NULL; + case PPC_BCCCTRL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 12, crrc:$cc) + AsmString = "bltctrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 12, CR0) + AsmString = "bltctrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 14, crrc:$cc) + AsmString = "bltctrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 14, CR0) + AsmString = "bltctrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 15, crrc:$cc) + AsmString = "bltctrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 15, CR0) + AsmString = "bltctrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 44, crrc:$cc) + AsmString = "bgtctrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 44, CR0) + AsmString = "bgtctrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 46, crrc:$cc) + AsmString = "bgtctrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 46, CR0) + AsmString = "bgtctrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 47, crrc:$cc) + AsmString = "bgtctrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 47, CR0) + AsmString = "bgtctrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 76, crrc:$cc) + AsmString = "beqctrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 76, CR0) + AsmString = "beqctrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 78, crrc:$cc) + AsmString = "beqctrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 78, CR0) + AsmString = "beqctrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 79, crrc:$cc) + AsmString = "beqctrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 79, CR0) + AsmString = "beqctrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 68, crrc:$cc) + AsmString = "bnectrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 68, CR0) + AsmString = "bnectrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 70, crrc:$cc) + AsmString = "bnectrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 70, CR0) + AsmString = "bnectrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCCTRL 71, crrc:$cc) + AsmString = "bnectrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCCTRL 71, CR0) + AsmString = "bnectrl+"; + break; + } + return NULL; + case PPC_BCCL: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 12, crrc:$cc, condbrtarget:$dst) + AsmString = "bltl $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 12, CR0, condbrtarget:$dst) + AsmString = "bltl $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 14, crrc:$cc, condbrtarget:$dst) + AsmString = "bltl- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 14, CR0, condbrtarget:$dst) + AsmString = "bltl- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 15, crrc:$cc, condbrtarget:$dst) + AsmString = "bltl+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 15, CR0, condbrtarget:$dst) + AsmString = "bltl+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 44, crrc:$cc, condbrtarget:$dst) + AsmString = "bgtl $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 44, CR0, condbrtarget:$dst) + AsmString = "bgtl $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 46, crrc:$cc, condbrtarget:$dst) + AsmString = "bgtl- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 46, CR0, condbrtarget:$dst) + AsmString = "bgtl- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 47, crrc:$cc, condbrtarget:$dst) + AsmString = "bgtl+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 47, CR0, condbrtarget:$dst) + AsmString = "bgtl+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 76, crrc:$cc, condbrtarget:$dst) + AsmString = "beql $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 76, CR0, condbrtarget:$dst) + AsmString = "beql $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 78, crrc:$cc, condbrtarget:$dst) + AsmString = "beql- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 78, CR0, condbrtarget:$dst) + AsmString = "beql- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 79, crrc:$cc, condbrtarget:$dst) + AsmString = "beql+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 79, CR0, condbrtarget:$dst) + AsmString = "beql+ $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 68, crrc:$cc, condbrtarget:$dst) + AsmString = "bnel $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 68, CR0, condbrtarget:$dst) + AsmString = "bnel $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 70, crrc:$cc, condbrtarget:$dst) + AsmString = "bnel- $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 70, CR0, condbrtarget:$dst) + AsmString = "bnel- $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCL 71, crrc:$cc, condbrtarget:$dst) + AsmString = "bnel+ $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCL 71, CR0, condbrtarget:$dst) + AsmString = "bnel+ $\xFF\x03\x01"; + break; + } + return NULL; + case PPC_BCCLA: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 12, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bltla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 12, CR0, abscondbrtarget:$dst) + AsmString = "bltla $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 14, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bltla- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 14, CR0, abscondbrtarget:$dst) + AsmString = "bltla- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 15, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bltla+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 15, CR0, abscondbrtarget:$dst) + AsmString = "bltla+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 44, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgtla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 44, CR0, abscondbrtarget:$dst) + AsmString = "bgtla $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 46, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgtla- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 46, CR0, abscondbrtarget:$dst) + AsmString = "bgtla- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 47, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bgtla+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 47, CR0, abscondbrtarget:$dst) + AsmString = "bgtla+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 76, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 76, CR0, abscondbrtarget:$dst) + AsmString = "beqla $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 78, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqla- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 78, CR0, abscondbrtarget:$dst) + AsmString = "beqla- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 79, crrc:$cc, abscondbrtarget:$dst) + AsmString = "beqla+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 79, CR0, abscondbrtarget:$dst) + AsmString = "beqla+ $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 68, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnela $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 68, CR0, abscondbrtarget:$dst) + AsmString = "bnela $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 70, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnela- $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 70, CR0, abscondbrtarget:$dst) + AsmString = "bnela- $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLA 71, crrc:$cc, abscondbrtarget:$dst) + AsmString = "bnela+ $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLA 71, CR0, abscondbrtarget:$dst) + AsmString = "bnela+ $\xFF\x03\x02"; + break; + } + return NULL; + case PPC_BCCLR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 12, crrc:$cc) + AsmString = "bltlr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 12, CR0) + AsmString = "bltlr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 14, crrc:$cc) + AsmString = "bltlr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 14, CR0) + AsmString = "bltlr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 15, crrc:$cc) + AsmString = "bltlr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 15, CR0) + AsmString = "bltlr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 44, crrc:$cc) + AsmString = "bgtlr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 44, CR0) + AsmString = "bgtlr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 46, crrc:$cc) + AsmString = "bgtlr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 46, CR0) + AsmString = "bgtlr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 47, crrc:$cc) + AsmString = "bgtlr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 47, CR0) + AsmString = "bgtlr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 76, crrc:$cc) + AsmString = "beqlr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 76, CR0) + AsmString = "beqlr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 78, crrc:$cc) + AsmString = "beqlr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 78, CR0) + AsmString = "beqlr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 79, crrc:$cc) + AsmString = "beqlr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 79, CR0) + AsmString = "beqlr+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 68, crrc:$cc) + AsmString = "bnelr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 68, CR0) + AsmString = "bnelr"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 70, crrc:$cc) + AsmString = "bnelr- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 70, CR0) + AsmString = "bnelr-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLR 71, crrc:$cc) + AsmString = "bnelr+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLR 71, CR0) + AsmString = "bnelr+"; + break; + } + return NULL; + case PPC_BCCLRL: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 12, crrc:$cc) + AsmString = "bltlrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 12, CR0) + AsmString = "bltlrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 14, crrc:$cc) + AsmString = "bltlrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 14, CR0) + AsmString = "bltlrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 15, crrc:$cc) + AsmString = "bltlrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 15, CR0) + AsmString = "bltlrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 44, crrc:$cc) + AsmString = "bgtlrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 44, CR0) + AsmString = "bgtlrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 46, crrc:$cc) + AsmString = "bgtlrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 46, CR0) + AsmString = "bgtlrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 47, crrc:$cc) + AsmString = "bgtlrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 47, CR0) + AsmString = "bgtlrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 76, crrc:$cc) + AsmString = "beqlrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 76, CR0) + AsmString = "beqlrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 78, crrc:$cc) + AsmString = "beqlrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 78, CR0) + AsmString = "beqlrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 79, crrc:$cc) + AsmString = "beqlrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 79, CR0) + AsmString = "beqlrl+"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 68, crrc:$cc) + AsmString = "bnelrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 68, CR0) + AsmString = "bnelrl"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 70, crrc:$cc) + AsmString = "bnelrl- $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 70, CR0) + AsmString = "bnelrl-"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { + // (BCCLRL 71, crrc:$cc) + AsmString = "bnelrl+ $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { + // (BCCLRL 71, CR0) + AsmString = "bnelrl+"; + break; + } + return NULL; + case PPC_CMPD: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (CMPD CR0, g8rc:$rA, g8rc:$rB) + AsmString = "cmpd $\x02, $\x03"; + break; + } + return NULL; + case PPC_CMPDI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (CMPDI CR0, g8rc:$rA, s16imm64:$imm) + AsmString = "cmpdi $\x02, $\xFF\x03\x03"; + break; + } + return NULL; + case PPC_CMPLD: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (CMPLD CR0, g8rc:$rA, g8rc:$rB) + AsmString = "cmpld $\x02, $\x03"; + break; + } + return NULL; + case PPC_CMPLDI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) + AsmString = "cmpldi $\x02, $\xFF\x03\x04"; + break; + } + return NULL; + case PPC_CMPLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (CMPLW CR0, gprc:$rA, gprc:$rB) + AsmString = "cmplw $\x02, $\x03"; + break; + } + return NULL; + case PPC_CMPLWI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (CMPLWI CR0, gprc:$rA, u16imm:$imm) + AsmString = "cmplwi $\x02, $\xFF\x03\x04"; + break; + } + return NULL; + case PPC_CMPW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (CMPW CR0, gprc:$rA, gprc:$rB) + AsmString = "cmpw $\x02, $\x03"; + break; + } + return NULL; + case PPC_CMPWI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (CMPWI CR0, gprc:$rA, s16imm:$imm) + AsmString = "cmpwi $\x02, $\xFF\x03\x03"; + break; + } + return NULL; + case PPC_CNTLZW: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (CNTLZW gprc:$rA, gprc:$rS) + AsmString = "cntlz $\x01, $\x02"; + break; + } + return NULL; + case PPC_CNTLZWo: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (CNTLZWo gprc:$rA, gprc:$rS) + AsmString = "cntlz. $\x01, $\x02"; + break; + } + return NULL; + case PPC_CREQV: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { + // (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) + AsmString = "crset $\x01"; + break; + } + return NULL; + case PPC_CRNOR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) + AsmString = "crnot $\x01, $\x02"; + break; + } + return NULL; + case PPC_CROR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) + AsmString = "crmove $\x01, $\x02"; + break; + } + return NULL; + case PPC_CRXOR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { + // (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) + AsmString = "crclr $\x01"; + break; + } + return NULL; + case PPC_MBAR: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (MBAR 0) + AsmString = "mbar"; + break; + } + return NULL; + case PPC_MFDCR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) { + // (MFDCR gprc:$Rx, 128) + AsmString = "mfbr0 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) { + // (MFDCR gprc:$Rx, 129) + AsmString = "mfbr1 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) { + // (MFDCR gprc:$Rx, 130) + AsmString = "mfbr2 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) { + // (MFDCR gprc:$Rx, 131) + AsmString = "mfbr3 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) { + // (MFDCR gprc:$Rx, 132) + AsmString = "mfbr4 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) { + // (MFDCR gprc:$Rx, 133) + AsmString = "mfbr5 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) { + // (MFDCR gprc:$Rx, 134) + AsmString = "mfbr6 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) { + // (MFDCR gprc:$Rx, 135) + AsmString = "mfbr7 $\x01"; + break; + } + return NULL; + case PPC_MFSPR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (MFSPR gprc:$Rx, 1) + AsmString = "mfxer $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (MFSPR gprc:$Rx, 4) + AsmString = "mfrtcu $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (MFSPR gprc:$Rx, 5) + AsmString = "mfrtcl $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 17) { + // (MFSPR gprc:$Rx, 17) + AsmString = "mfdscr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 18) { + // (MFSPR gprc:$Rx, 18) + AsmString = "mfdsisr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 19) { + // (MFSPR gprc:$Rx, 19) + AsmString = "mfdar $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 990) { + // (MFSPR gprc:$Rx, 990) + AsmString = "mfsrr2 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 991) { + // (MFSPR gprc:$Rx, 991) + AsmString = "mfsrr3 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 28) { + // (MFSPR gprc:$Rx, 28) + AsmString = "mfcfar $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 29) { + // (MFSPR gprc:$Rx, 29) + AsmString = "mfamr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 48) { + // (MFSPR gprc:$Rx, 48) + AsmString = "mfpid $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 989) { + // (MFSPR gprc:$Rx, 989) + AsmString = "mftblo $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 988) { + // (MFSPR gprc:$Rx, 988) + AsmString = "mftbhi $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 536) { + // (MFSPR gprc:$Rx, 536) + AsmString = "mfdbatu $\x01, 0"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 538) { + // (MFSPR gprc:$Rx, 538) + AsmString = "mfdbatu $\x01, 1"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 540) { + // (MFSPR gprc:$Rx, 540) + AsmString = "mfdbatu $\x01, 2"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 542) { + // (MFSPR gprc:$Rx, 542) + AsmString = "mfdbatu $\x01, 3"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 537) { + // (MFSPR gprc:$Rx, 537) + AsmString = "mfdbatl $\x01, 0"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 539) { + // (MFSPR gprc:$Rx, 539) + AsmString = "mfdbatl $\x01, 1"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 541) { + // (MFSPR gprc:$Rx, 541) + AsmString = "mfdbatl $\x01, 2"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 543) { + // (MFSPR gprc:$Rx, 543) + AsmString = "mfdbatl $\x01, 3"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 528) { + // (MFSPR gprc:$Rx, 528) + AsmString = "mfibatu $\x01, 0"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 530) { + // (MFSPR gprc:$Rx, 530) + AsmString = "mfibatu $\x01, 1"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 532) { + // (MFSPR gprc:$Rx, 532) + AsmString = "mfibatu $\x01, 2"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 534) { + // (MFSPR gprc:$Rx, 534) + AsmString = "mfibatu $\x01, 3"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 529) { + // (MFSPR gprc:$Rx, 529) + AsmString = "mfibatl $\x01, 0"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 531) { + // (MFSPR gprc:$Rx, 531) + AsmString = "mfibatl $\x01, 1"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 533) { + // (MFSPR gprc:$Rx, 533) + AsmString = "mfibatl $\x01, 2"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 535) { + // (MFSPR gprc:$Rx, 535) + AsmString = "mfibatl $\x01, 3"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1018) { + // (MFSPR gprc:$Rx, 1018) + AsmString = "mfdccr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1019) { + // (MFSPR gprc:$Rx, 1019) + AsmString = "mficcr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 981) { + // (MFSPR gprc:$Rx, 981) + AsmString = "mfdear $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 980) { + // (MFSPR gprc:$Rx, 980) + AsmString = "mfesr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 512) { + // (MFSPR gprc:$Rx, 512) + AsmString = "mfspefscr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 986) { + // (MFSPR gprc:$Rx, 986) + AsmString = "mftcr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 280) { + // (MFSPR gprc:$RT, 280) + AsmString = "mfasr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 287) { + // (MFSPR gprc:$RT, 287) + AsmString = "mfpvr $\x01"; + break; + } + return NULL; + case PPC_MFTB: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 269) { + // (MFTB gprc:$Rx, 269) + AsmString = "mftbu $\x01"; + break; + } + return NULL; + case PPC_MTCRF8: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 255 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (MTCRF8 255, g8rc:$rA) + AsmString = "mtcr $\x02"; + break; + } + return NULL; + case PPC_MTDCR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) { + // (MTDCR gprc:$Rx, 128) + AsmString = "mtbr0 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) { + // (MTDCR gprc:$Rx, 129) + AsmString = "mtbr1 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) { + // (MTDCR gprc:$Rx, 130) + AsmString = "mtbr2 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) { + // (MTDCR gprc:$Rx, 131) + AsmString = "mtbr3 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) { + // (MTDCR gprc:$Rx, 132) + AsmString = "mtbr4 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) { + // (MTDCR gprc:$Rx, 133) + AsmString = "mtbr5 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) { + // (MTDCR gprc:$Rx, 134) + AsmString = "mtbr6 $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) { + // (MTDCR gprc:$Rx, 135) + AsmString = "mtbr7 $\x01"; + break; + } + return NULL; + case PPC_MTFSF: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0) + AsmString = "mtfsf $\x01, $\x02"; + break; + } + return NULL; + case PPC_MTFSFI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MTFSFI crrc:$BF, i32imm:$U, 0) + AsmString = "mtfsfi $\x01, $\x02"; + break; + } + return NULL; + case PPC_MTFSFIo: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MTFSFIo crrc:$BF, i32imm:$U, 0) + AsmString = "mtfsfi. $\x01, $\x02"; + break; + } + return NULL; + case PPC_MTFSFo: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0) + AsmString = "mtfsf. $\x01, $\x02"; + break; + } + return NULL; + case PPC_MTMSR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (MTMSR gprc:$RS, 0) + AsmString = "mtmsr $\x01"; + break; + } + return NULL; + case PPC_MTMSRD: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (MTMSRD gprc:$RS, 0) + AsmString = "mtmsrd $\x01"; + break; + } + return NULL; + case PPC_MTSPR: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 1, gprc:$Rx) + AsmString = "mtxer $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 17 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 17, gprc:$Rx) + AsmString = "mtdscr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 18 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 18, gprc:$Rx) + AsmString = "mtdsisr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 19 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 19, gprc:$Rx) + AsmString = "mtdar $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 990 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 990, gprc:$Rx) + AsmString = "mtsrr2 $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 991 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 991, gprc:$Rx) + AsmString = "mtsrr3 $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 28 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 28, gprc:$Rx) + AsmString = "mtcfar $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 29 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 29, gprc:$Rx) + AsmString = "mtamr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 48 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 48, gprc:$Rx) + AsmString = "mtpid $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 284 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 284, gprc:$Rx) + AsmString = "mttbl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 285 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 285, gprc:$Rx) + AsmString = "mttbu $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 989 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 989, gprc:$Rx) + AsmString = "mttblo $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 988 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 988, gprc:$Rx) + AsmString = "mttbhi $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 536 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 536, gprc:$Rx) + AsmString = "mtdbatu 0, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 538 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 538, gprc:$Rx) + AsmString = "mtdbatu 1, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 540 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 540, gprc:$Rx) + AsmString = "mtdbatu 2, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 542 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 542, gprc:$Rx) + AsmString = "mtdbatu 3, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 537 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 537, gprc:$Rx) + AsmString = "mtdbatl 0, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 539 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 539, gprc:$Rx) + AsmString = "mtdbatl 1, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 541 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 541, gprc:$Rx) + AsmString = "mtdbatl 2, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 543 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 543, gprc:$Rx) + AsmString = "mtdbatl 3, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 528 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 528, gprc:$Rx) + AsmString = "mtibatu 0, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 530 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 530, gprc:$Rx) + AsmString = "mtibatu 1, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 532 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 532, gprc:$Rx) + AsmString = "mtibatu 2, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 534 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 534, gprc:$Rx) + AsmString = "mtibatu 3, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 529 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 529, gprc:$Rx) + AsmString = "mtibatl 0, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 531 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 531, gprc:$Rx) + AsmString = "mtibatl 1, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 533 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 533, gprc:$Rx) + AsmString = "mtibatl 2, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 535 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 535, gprc:$Rx) + AsmString = "mtibatl 3, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1018 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 1018, gprc:$Rx) + AsmString = "mtdccr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1019 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 1019, gprc:$Rx) + AsmString = "mticcr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 981 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 981, gprc:$Rx) + AsmString = "mtdear $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 980 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 980, gprc:$Rx) + AsmString = "mtesr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 512 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 512, gprc:$Rx) + AsmString = "mtspefscr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 986 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (MTSPR 986, gprc:$Rx) + AsmString = "mttcr $\x02"; + break; + } + return NULL; + case PPC_NOR8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) + AsmString = "not $\x01, $\x02"; + break; + } + return NULL; + case PPC_NOR8o: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) + AsmString = "not. $\x01, $\x02"; + break; + } + return NULL; + case PPC_OR8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) + AsmString = "mr $\x01, $\x02"; + break; + } + return NULL; + case PPC_OR8o: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) + AsmString = "mr. $\x01, $\x02"; + break; + } + return NULL; + case PPC_QVFLOGICALb: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 0) + AsmString = "qvfclr $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 1) + AsmString = "qvfand $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 4) + AsmString = "qvfandc $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 5) + AsmString = "qvfctfb $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 6) + AsmString = "qvfxor $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 7) + AsmString = "qvfor $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 8) + AsmString = "qvfnor $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 9) + AsmString = "qvfequ $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 10) + AsmString = "qvfnot $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 13) + AsmString = "qvforc $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 14) + AsmString = "qvfnand $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 15) + AsmString = "qvfset $\x01"; + break; + } + return NULL; + case PPC_RLDCL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0) + AsmString = "rotld $\x01, $\x02, $\x03"; + break; + } + return NULL; + case PPC_RLDCLo: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0) + AsmString = "rotld. $\x01, $\x02, $\x03"; + break; + } + return NULL; + case PPC_RLDICL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0) + AsmString = "rotldi $\x01, $\x02, $\xFF\x03\x05"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n) + AsmString = "clrldi $\x01, $\x02, $\xFF\x04\x05"; + break; + } + return NULL; + case PPC_RLDICLo: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0) + AsmString = "rotldi. $\x01, $\x02, $\xFF\x03\x05"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n) + AsmString = "clrldi. $\x01, $\x02, $\xFF\x04\x05"; + break; + } + return NULL; + case PPC_RLWINM: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) + AsmString = "rotlwi $\x01, $\x02, $\xFF\x03\x06"; + break; + } + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) + AsmString = "clrlwi $\x01, $\x02, $\xFF\x04\x06"; + break; + } + return NULL; + case PPC_RLWINMo: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) + AsmString = "rotlwi. $\x01, $\x02, $\xFF\x03\x06"; + break; + } + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) + AsmString = "clrlwi. $\x01, $\x02, $\xFF\x04\x06"; + break; + } + return NULL; + case PPC_RLWNM: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) + AsmString = "rotlw $\x01, $\x02, $\x03"; + break; + } + return NULL; + case PPC_RLWNMo: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 4)) && + MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { + // (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) + AsmString = "rotlw. $\x01, $\x02, $\x03"; + break; + } + return NULL; + case PPC_SC: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (SC 0) + AsmString = "sc"; + break; + } + return NULL; + case PPC_SUBF8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB) + AsmString = "sub $\x01, $\x03, $\x02"; + break; + } + return NULL; + case PPC_SUBF8o: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB) + AsmString = "sub. $\x01, $\x03, $\x02"; + break; + } + return NULL; + case PPC_SUBFC8: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB) + AsmString = "subc $\x01, $\x03, $\x02"; + break; + } + return NULL; + case PPC_SUBFC8o: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB) + AsmString = "subc. $\x01, $\x03, $\x02"; + break; + } + return NULL; + case PPC_SYNC: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { + // (SYNC 1) + AsmString = "lwsync"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { + // (SYNC 2) + AsmString = "ptesync"; + break; + } + return NULL; + case PPC_TD: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 16, g8rc:$rA, g8rc:$rB) + AsmString = "tdlt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 4, g8rc:$rA, g8rc:$rB) + AsmString = "tdeq $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 8, g8rc:$rA, g8rc:$rB) + AsmString = "tdgt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 24, g8rc:$rA, g8rc:$rB) + AsmString = "tdne $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 2, g8rc:$rA, g8rc:$rB) + AsmString = "tdllt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 1, g8rc:$rA, g8rc:$rB) + AsmString = "tdlgt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { + // (TD 31, g8rc:$rA, g8rc:$rB) + AsmString = "tdu $\x02, $\x03"; + break; + } + return NULL; + case PPC_TDI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 16, g8rc:$rA, s16imm:$imm) + AsmString = "tdlti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 4, g8rc:$rA, s16imm:$imm) + AsmString = "tdeqi $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 8, g8rc:$rA, s16imm:$imm) + AsmString = "tdgti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 24, g8rc:$rA, s16imm:$imm) + AsmString = "tdnei $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 2, g8rc:$rA, s16imm:$imm) + AsmString = "tdllti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 1, g8rc:$rA, s16imm:$imm) + AsmString = "tdlgti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { + // (TDI 31, g8rc:$rA, s16imm:$imm) + AsmString = "tdui $\x02, $\xFF\x03\x03"; + break; + } + return NULL; + case PPC_TLBIE: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TLBIE R0, gprc:$RB) + AsmString = "tlbie $\x02"; + break; + } + return NULL; + case PPC_TLBRE2: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TLBRE2 gprc:$RS, gprc:$A, 0) + AsmString = "tlbrehi $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TLBRE2 gprc:$RS, gprc:$A, 1) + AsmString = "tlbrelo $\x01, $\x02"; + break; + } + return NULL; + case PPC_TLBWE2: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TLBWE2 gprc:$RS, gprc:$A, 0) + AsmString = "tlbwehi $\x01, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TLBWE2 gprc:$RS, gprc:$A, 1) + AsmString = "tlbwelo $\x01, $\x02"; + break; + } + return NULL; + case PPC_TW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 16, gprc:$rA, gprc:$rB) + AsmString = "twlt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 4, gprc:$rA, gprc:$rB) + AsmString = "tweq $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 8, gprc:$rA, gprc:$rB) + AsmString = "twgt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 24, gprc:$rA, gprc:$rB) + AsmString = "twne $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 2, gprc:$rA, gprc:$rB) + AsmString = "twllt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 1, gprc:$rA, gprc:$rB) + AsmString = "twlgt $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { + // (TW 31, gprc:$rA, gprc:$rB) + AsmString = "twu $\x02, $\x03"; + break; + } + return NULL; + case PPC_TWI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 16, gprc:$rA, s16imm:$imm) + AsmString = "twlti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 4, gprc:$rA, s16imm:$imm) + AsmString = "tweqi $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 8, gprc:$rA, s16imm:$imm) + AsmString = "twgti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 24, gprc:$rA, s16imm:$imm) + AsmString = "twnei $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 2, gprc:$rA, s16imm:$imm) + AsmString = "twllti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 1, gprc:$rA, s16imm:$imm) + AsmString = "twlgti $\x02, $\xFF\x03\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { + // (TWI 31, gprc:$rA, s16imm:$imm) + AsmString = "twui $\x02, $\xFF\x03\x03"; + break; + } + return NULL; + case PPC_WAIT: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { + // (WAIT 0) + AsmString = "wait"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { + // (WAIT 1) + AsmString = "waitrsv"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { + // (WAIT 2) + AsmString = "waitimpl"; + break; + } + return NULL; + case PPC_XORI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_R0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (XORI R0, R0, 0) + AsmString = "xnop"; + break; + } + return NULL; + case PPC_XVCPSGNDP: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) + AsmString = "xvmovdp $\x01, $\x02"; + break; + } + return NULL; + case PPC_XVCPSGNSP: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + // (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) + AsmString = "xvmovsp $\x01, $\x02"; + break; + } + return NULL; + case PPC_XXPERMDI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) + AsmString = "xxspltd $\x01, $\x02, 0"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) + AsmString = "xxspltd $\x01, $\x02, 1"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0) + AsmString = "xxmrghd $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3) + AsmString = "xxmrgld $\x01, $\x02, $\x03"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) + AsmString = "xxswapd $\x01, $\x02"; + break; + } + return NULL; + case PPC_gBC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBC 8, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdnzt $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBC 0, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdnzf $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBC 10, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdzt $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBC 2, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdzf $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case PPC_gBCA: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdnzta $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdnzfa $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdzta $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdzfa $\x02, $\xFF\x03\x02"; + break; + } + return NULL; + case PPC_gBCCTR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCCTR u5imm:$bo, crbitrc:$bi, 0) + AsmString = "bcctr $\xFF\x01\x06, $\x02"; + break; + } + return NULL; + case PPC_gBCCTRL: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCCTRL u5imm:$bo, crbitrc:$bi, 0) + AsmString = "bcctrl $\xFF\x01\x06, $\x02"; + break; + } + return NULL; + case PPC_gBCL: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCL 8, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdnztl $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCL 0, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdnzfl $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCL 10, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdztl $\x02, $\xFF\x03\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCL 2, crbitrc:$bi, condbrtarget:$dst) + AsmString = "bdzfl $\x02, $\xFF\x03\x01"; + break; + } + return NULL; + case PPC_gBCLA: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdnztla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdnzfla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdztla $\x02, $\xFF\x03\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + // (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst) + AsmString = "bdzfla $\x02, $\xFF\x03\x02"; + break; + } + return NULL; + case PPC_gBCLR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLR u5imm:$bo, crbitrc:$bi, 0) + AsmString = "bclr $\xFF\x01\x06, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLR 8, crbitrc:$bi, 0) + AsmString = "bdnztlr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLR 0, crbitrc:$bi, 0) + AsmString = "bdnzflr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLR 10, crbitrc:$bi, 0) + AsmString = "bdztlr $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLR 2, crbitrc:$bi, 0) + AsmString = "bdzflr $\x02"; + break; + } + return NULL; + case PPC_gBCLRL: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLRL u5imm:$bo, crbitrc:$bi, 0) + AsmString = "bclrl $\xFF\x01\x06, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLRL 8, crbitrc:$bi, 0) + AsmString = "bdnztlrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLRL 0, crbitrc:$bi, 0) + AsmString = "bdnzflrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLRL 10, crbitrc:$bi, 0) + AsmString = "bdztlrl $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (gBCLRL 2, crbitrc:$bi, 0) + AsmString = "bdzflrl $\x02"; + break; + } + return NULL; + } + + tmp = cs_strdup(AsmString); + AsmMnem = tmp; + for(AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + return tmp; +} + +#endif // PRINT_ALIAS_INSTR diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenDisassemblerTables.inc new file mode 100644 index 0000000..cd34bbd --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenDisassemblerTables.inc @@ -0,0 +1,4006 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * PPC Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, \ + unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +// FieldFromInstruction(fieldFromInstruction_2, uint16_t) +FieldFromInstruction(fieldFromInstruction_4, uint32_t) + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 3 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 17 +/* 7 */ MCD_OPC_CheckField, 1, 10, 128, 2, 231, 38, // Skip to: 9973 +/* 14 */ MCD_OPC_Decode, 119, 0, // Opcode: ATTN +/* 17 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 25 +/* 21 */ MCD_OPC_Decode, 247, 8, 1, // Opcode: TDI +/* 25 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 33 +/* 29 */ MCD_OPC_Decode, 136, 9, 2, // Opcode: TWI +/* 33 */ MCD_OPC_FilterValue, 4, 223, 6, // Skip to: 1796 +/* 37 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 40 */ MCD_OPC_FilterValue, 0, 179, 0, // Skip to: 223 +/* 44 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 47 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 55 +/* 51 */ MCD_OPC_Decode, 144, 9, 3, // Opcode: VADDUBM +/* 55 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 63 +/* 59 */ MCD_OPC_Decode, 147, 9, 3, // Opcode: VADDUHM +/* 63 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 71 +/* 67 */ MCD_OPC_Decode, 149, 9, 3, // Opcode: VADDUWM +/* 71 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 79 +/* 75 */ MCD_OPC_Decode, 146, 9, 3, // Opcode: VADDUDM +/* 79 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 87 +/* 83 */ MCD_OPC_Decode, 139, 9, 3, // Opcode: VADDCUW +/* 87 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 95 +/* 91 */ MCD_OPC_Decode, 145, 9, 3, // Opcode: VADDUBS +/* 95 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 103 +/* 99 */ MCD_OPC_Decode, 148, 9, 3, // Opcode: VADDUHS +/* 103 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 111 +/* 107 */ MCD_OPC_Decode, 150, 9, 3, // Opcode: VADDUWS +/* 111 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 119 +/* 115 */ MCD_OPC_Decode, 141, 9, 3, // Opcode: VADDSBS +/* 119 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 127 +/* 123 */ MCD_OPC_Decode, 142, 9, 3, // Opcode: VADDSHS +/* 127 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 135 +/* 131 */ MCD_OPC_Decode, 143, 9, 3, // Opcode: VADDSWS +/* 135 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 143 +/* 139 */ MCD_OPC_Decode, 183, 10, 3, // Opcode: VSUBUBM +/* 143 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 151 +/* 147 */ MCD_OPC_Decode, 186, 10, 3, // Opcode: VSUBUHM +/* 151 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 159 +/* 155 */ MCD_OPC_Decode, 188, 10, 3, // Opcode: VSUBUWM +/* 159 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 167 +/* 163 */ MCD_OPC_Decode, 185, 10, 3, // Opcode: VSUBUDM +/* 167 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 175 +/* 171 */ MCD_OPC_Decode, 178, 10, 3, // Opcode: VSUBCUW +/* 175 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 183 +/* 179 */ MCD_OPC_Decode, 184, 10, 3, // Opcode: VSUBUBS +/* 183 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 191 +/* 187 */ MCD_OPC_Decode, 187, 10, 3, // Opcode: VSUBUHS +/* 191 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 199 +/* 195 */ MCD_OPC_Decode, 189, 10, 3, // Opcode: VSUBUWS +/* 199 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 207 +/* 203 */ MCD_OPC_Decode, 180, 10, 3, // Opcode: VSUBSBS +/* 207 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 215 +/* 211 */ MCD_OPC_Decode, 181, 10, 3, // Opcode: VSUBSHS +/* 215 */ MCD_OPC_FilterValue, 30, 26, 38, // Skip to: 9973 +/* 219 */ MCD_OPC_Decode, 182, 10, 3, // Opcode: VSUBSWS +/* 223 */ MCD_OPC_FilterValue, 2, 235, 0, // Skip to: 462 +/* 227 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 230 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 238 +/* 234 */ MCD_OPC_Decode, 212, 9, 3, // Opcode: VMAXUB +/* 238 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 246 +/* 242 */ MCD_OPC_Decode, 214, 9, 3, // Opcode: VMAXUH +/* 246 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 254 +/* 250 */ MCD_OPC_Decode, 215, 9, 3, // Opcode: VMAXUW +/* 254 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 262 +/* 258 */ MCD_OPC_Decode, 213, 9, 3, // Opcode: VMAXUD +/* 262 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 270 +/* 266 */ MCD_OPC_Decode, 208, 9, 3, // Opcode: VMAXSB +/* 270 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 278 +/* 274 */ MCD_OPC_Decode, 210, 9, 3, // Opcode: VMAXSH +/* 278 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 286 +/* 282 */ MCD_OPC_Decode, 211, 9, 3, // Opcode: VMAXSW +/* 286 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 294 +/* 290 */ MCD_OPC_Decode, 209, 9, 3, // Opcode: VMAXSD +/* 294 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 302 +/* 298 */ MCD_OPC_Decode, 224, 9, 3, // Opcode: VMINUB +/* 302 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 310 +/* 306 */ MCD_OPC_Decode, 225, 9, 3, // Opcode: VMINUH +/* 310 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 318 +/* 314 */ MCD_OPC_Decode, 226, 9, 3, // Opcode: VMINUW +/* 318 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 326 +/* 322 */ MCD_OPC_Decode, 218, 9, 3, // Opcode: VMIDUD +/* 326 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 334 +/* 330 */ MCD_OPC_Decode, 220, 9, 3, // Opcode: VMINSB +/* 334 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 342 +/* 338 */ MCD_OPC_Decode, 222, 9, 3, // Opcode: VMINSH +/* 342 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 350 +/* 346 */ MCD_OPC_Decode, 223, 9, 3, // Opcode: VMINSW +/* 350 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 358 +/* 354 */ MCD_OPC_Decode, 221, 9, 3, // Opcode: VMINSD +/* 358 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 366 +/* 362 */ MCD_OPC_Decode, 156, 9, 3, // Opcode: VAVGUB +/* 366 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 374 +/* 370 */ MCD_OPC_Decode, 157, 9, 3, // Opcode: VAVGUH +/* 374 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 382 +/* 378 */ MCD_OPC_Decode, 158, 9, 3, // Opcode: VAVGUW +/* 382 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 390 +/* 386 */ MCD_OPC_Decode, 153, 9, 3, // Opcode: VAVGSB +/* 390 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 398 +/* 394 */ MCD_OPC_Decode, 154, 9, 3, // Opcode: VAVGSH +/* 398 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 406 +/* 402 */ MCD_OPC_Decode, 155, 9, 3, // Opcode: VAVGSW +/* 406 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 420 +/* 410 */ MCD_OPC_CheckField, 16, 5, 0, 85, 37, // Skip to: 9973 +/* 416 */ MCD_OPC_Decode, 163, 9, 4, // Opcode: VCLZB +/* 420 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 434 +/* 424 */ MCD_OPC_CheckField, 16, 5, 0, 71, 37, // Skip to: 9973 +/* 430 */ MCD_OPC_Decode, 165, 9, 4, // Opcode: VCLZH +/* 434 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 448 +/* 438 */ MCD_OPC_CheckField, 16, 5, 0, 57, 37, // Skip to: 9973 +/* 444 */ MCD_OPC_Decode, 166, 9, 4, // Opcode: VCLZW +/* 448 */ MCD_OPC_FilterValue, 31, 49, 37, // Skip to: 9973 +/* 452 */ MCD_OPC_CheckField, 16, 5, 0, 43, 37, // Skip to: 9973 +/* 458 */ MCD_OPC_Decode, 164, 9, 4, // Opcode: VCLZD +/* 462 */ MCD_OPC_FilterValue, 3, 59, 0, // Skip to: 525 +/* 466 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 469 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 483 +/* 473 */ MCD_OPC_CheckField, 16, 5, 0, 22, 37, // Skip to: 9973 +/* 479 */ MCD_OPC_Decode, 140, 10, 4, // Opcode: VPOPCNTB +/* 483 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 497 +/* 487 */ MCD_OPC_CheckField, 16, 5, 0, 8, 37, // Skip to: 9973 +/* 493 */ MCD_OPC_Decode, 142, 10, 4, // Opcode: VPOPCNTH +/* 497 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 511 +/* 501 */ MCD_OPC_CheckField, 16, 5, 0, 250, 36, // Skip to: 9973 +/* 507 */ MCD_OPC_Decode, 143, 10, 4, // Opcode: VPOPCNTW +/* 511 */ MCD_OPC_FilterValue, 31, 242, 36, // Skip to: 9973 +/* 515 */ MCD_OPC_CheckField, 16, 5, 0, 236, 36, // Skip to: 9973 +/* 521 */ MCD_OPC_Decode, 141, 10, 4, // Opcode: VPOPCNTD +/* 525 */ MCD_OPC_FilterValue, 4, 239, 0, // Skip to: 768 +/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 532 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 540 +/* 536 */ MCD_OPC_Decode, 149, 10, 3, // Opcode: VRLB +/* 540 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 548 +/* 544 */ MCD_OPC_Decode, 151, 10, 3, // Opcode: VRLH +/* 548 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 556 +/* 552 */ MCD_OPC_Decode, 152, 10, 3, // Opcode: VRLW +/* 556 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 564 +/* 560 */ MCD_OPC_Decode, 150, 10, 3, // Opcode: VRLD +/* 564 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 572 +/* 568 */ MCD_OPC_Decode, 156, 10, 3, // Opcode: VSLB +/* 572 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 580 +/* 576 */ MCD_OPC_Decode, 159, 10, 3, // Opcode: VSLH +/* 580 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 588 +/* 584 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: VSLW +/* 588 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 596 +/* 592 */ MCD_OPC_Decode, 155, 10, 3, // Opcode: VSL +/* 596 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 604 +/* 600 */ MCD_OPC_Decode, 173, 10, 3, // Opcode: VSRB +/* 604 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 612 +/* 608 */ MCD_OPC_Decode, 175, 10, 3, // Opcode: VSRH +/* 612 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 620 +/* 616 */ MCD_OPC_Decode, 177, 10, 3, // Opcode: VSRW +/* 620 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 628 +/* 624 */ MCD_OPC_Decode, 168, 10, 3, // Opcode: VSR +/* 628 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 636 +/* 632 */ MCD_OPC_Decode, 169, 10, 3, // Opcode: VSRAB +/* 636 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 644 +/* 640 */ MCD_OPC_Decode, 171, 10, 3, // Opcode: VSRAH +/* 644 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 652 +/* 648 */ MCD_OPC_Decode, 172, 10, 3, // Opcode: VSRAW +/* 652 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 660 +/* 656 */ MCD_OPC_Decode, 170, 10, 3, // Opcode: VSRAD +/* 660 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 668 +/* 664 */ MCD_OPC_Decode, 151, 9, 3, // Opcode: VAND +/* 668 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 676 +/* 672 */ MCD_OPC_Decode, 152, 9, 3, // Opcode: VANDC +/* 676 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 684 +/* 680 */ MCD_OPC_Decode, 128, 10, 3, // Opcode: VOR +/* 684 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 692 +/* 688 */ MCD_OPC_Decode, 201, 10, 3, // Opcode: VXOR +/* 692 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 700 +/* 696 */ MCD_OPC_Decode, 255, 9, 3, // Opcode: VNOR +/* 700 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 708 +/* 704 */ MCD_OPC_Decode, 129, 10, 3, // Opcode: VORC +/* 708 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 716 +/* 712 */ MCD_OPC_Decode, 253, 9, 3, // Opcode: VNAND +/* 716 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 724 +/* 720 */ MCD_OPC_Decode, 157, 10, 3, // Opcode: VSLD +/* 724 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 738 +/* 728 */ MCD_OPC_CheckField, 11, 10, 0, 23, 36, // Skip to: 9973 +/* 734 */ MCD_OPC_Decode, 198, 5, 5, // Opcode: MFVSCR +/* 738 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 752 +/* 742 */ MCD_OPC_CheckField, 16, 10, 0, 9, 36, // Skip to: 9973 +/* 748 */ MCD_OPC_Decode, 225, 5, 6, // Opcode: MTVSCR +/* 752 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 760 +/* 756 */ MCD_OPC_Decode, 203, 9, 3, // Opcode: VEQV +/* 760 */ MCD_OPC_FilterValue, 27, 249, 35, // Skip to: 9973 +/* 764 */ MCD_OPC_Decode, 174, 10, 3, // Opcode: VSRD +/* 768 */ MCD_OPC_FilterValue, 6, 211, 0, // Skip to: 983 +/* 772 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 775 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 783 +/* 779 */ MCD_OPC_Decode, 171, 9, 3, // Opcode: VCMPEQUB +/* 783 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 791 +/* 787 */ MCD_OPC_Decode, 175, 9, 3, // Opcode: VCMPEQUH +/* 791 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 799 +/* 795 */ MCD_OPC_Decode, 177, 9, 3, // Opcode: VCMPEQUW +/* 799 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 807 +/* 803 */ MCD_OPC_Decode, 169, 9, 3, // Opcode: VCMPEQFP +/* 807 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 815 +/* 811 */ MCD_OPC_Decode, 179, 9, 3, // Opcode: VCMPGEFP +/* 815 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 823 +/* 819 */ MCD_OPC_Decode, 191, 9, 3, // Opcode: VCMPGTUB +/* 823 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 831 +/* 827 */ MCD_OPC_Decode, 195, 9, 3, // Opcode: VCMPGTUH +/* 831 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 839 +/* 835 */ MCD_OPC_Decode, 197, 9, 3, // Opcode: VCMPGTUW +/* 839 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 847 +/* 843 */ MCD_OPC_Decode, 181, 9, 3, // Opcode: VCMPGTFP +/* 847 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 855 +/* 851 */ MCD_OPC_Decode, 183, 9, 3, // Opcode: VCMPGTSB +/* 855 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 863 +/* 859 */ MCD_OPC_Decode, 187, 9, 3, // Opcode: VCMPGTSH +/* 863 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 871 +/* 867 */ MCD_OPC_Decode, 189, 9, 3, // Opcode: VCMPGTSW +/* 871 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 879 +/* 875 */ MCD_OPC_Decode, 167, 9, 3, // Opcode: VCMPBFP +/* 879 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 887 +/* 883 */ MCD_OPC_Decode, 172, 9, 3, // Opcode: VCMPEQUBo +/* 887 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 895 +/* 891 */ MCD_OPC_Decode, 176, 9, 3, // Opcode: VCMPEQUHo +/* 895 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 903 +/* 899 */ MCD_OPC_Decode, 178, 9, 3, // Opcode: VCMPEQUWo +/* 903 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 911 +/* 907 */ MCD_OPC_Decode, 170, 9, 3, // Opcode: VCMPEQFPo +/* 911 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 919 +/* 915 */ MCD_OPC_Decode, 180, 9, 3, // Opcode: VCMPGEFPo +/* 919 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 927 +/* 923 */ MCD_OPC_Decode, 192, 9, 3, // Opcode: VCMPGTUBo +/* 927 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 935 +/* 931 */ MCD_OPC_Decode, 196, 9, 3, // Opcode: VCMPGTUHo +/* 935 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 943 +/* 939 */ MCD_OPC_Decode, 198, 9, 3, // Opcode: VCMPGTUWo +/* 943 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 951 +/* 947 */ MCD_OPC_Decode, 182, 9, 3, // Opcode: VCMPGTFPo +/* 951 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 959 +/* 955 */ MCD_OPC_Decode, 184, 9, 3, // Opcode: VCMPGTSBo +/* 959 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 967 +/* 963 */ MCD_OPC_Decode, 188, 9, 3, // Opcode: VCMPGTSHo +/* 967 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 975 +/* 971 */ MCD_OPC_Decode, 190, 9, 3, // Opcode: VCMPGTSWo +/* 975 */ MCD_OPC_FilterValue, 31, 34, 35, // Skip to: 9973 +/* 979 */ MCD_OPC_Decode, 168, 9, 3, // Opcode: VCMPBFPo +/* 983 */ MCD_OPC_FilterValue, 7, 51, 0, // Skip to: 1038 +/* 987 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 990 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 998 +/* 994 */ MCD_OPC_Decode, 173, 9, 3, // Opcode: VCMPEQUD +/* 998 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1006 +/* 1002 */ MCD_OPC_Decode, 193, 9, 3, // Opcode: VCMPGTUD +/* 1006 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1014 +/* 1010 */ MCD_OPC_Decode, 185, 9, 3, // Opcode: VCMPGTSD +/* 1014 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1022 +/* 1018 */ MCD_OPC_Decode, 174, 9, 3, // Opcode: VCMPEQUDo +/* 1022 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1030 +/* 1026 */ MCD_OPC_Decode, 194, 9, 3, // Opcode: VCMPGTUDo +/* 1030 */ MCD_OPC_FilterValue, 31, 235, 34, // Skip to: 9973 +/* 1034 */ MCD_OPC_Decode, 186, 9, 3, // Opcode: VCMPGTSDo +/* 1038 */ MCD_OPC_FilterValue, 8, 139, 0, // Skip to: 1181 +/* 1042 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1045 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1053 +/* 1049 */ MCD_OPC_Decode, 249, 9, 3, // Opcode: VMULOUB +/* 1053 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1061 +/* 1057 */ MCD_OPC_Decode, 250, 9, 3, // Opcode: VMULOUH +/* 1061 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1069 +/* 1065 */ MCD_OPC_Decode, 251, 9, 3, // Opcode: VMULOUW +/* 1069 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1077 +/* 1073 */ MCD_OPC_Decode, 246, 9, 3, // Opcode: VMULOSB +/* 1077 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1085 +/* 1081 */ MCD_OPC_Decode, 247, 9, 3, // Opcode: VMULOSH +/* 1085 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1093 +/* 1089 */ MCD_OPC_Decode, 248, 9, 3, // Opcode: VMULOSW +/* 1093 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1101 +/* 1097 */ MCD_OPC_Decode, 243, 9, 3, // Opcode: VMULEUB +/* 1101 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1109 +/* 1105 */ MCD_OPC_Decode, 244, 9, 3, // Opcode: VMULEUH +/* 1109 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1117 +/* 1113 */ MCD_OPC_Decode, 245, 9, 3, // Opcode: VMULEUW +/* 1117 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1125 +/* 1121 */ MCD_OPC_Decode, 240, 9, 3, // Opcode: VMULESB +/* 1125 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1133 +/* 1129 */ MCD_OPC_Decode, 241, 9, 3, // Opcode: VMULESH +/* 1133 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1141 +/* 1137 */ MCD_OPC_Decode, 242, 9, 3, // Opcode: VMULESW +/* 1141 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1149 +/* 1145 */ MCD_OPC_Decode, 193, 10, 3, // Opcode: VSUM4UBS +/* 1149 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1157 +/* 1153 */ MCD_OPC_Decode, 192, 10, 3, // Opcode: VSUM4SHS +/* 1157 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1165 +/* 1161 */ MCD_OPC_Decode, 190, 10, 3, // Opcode: VSUM2SWS +/* 1165 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1173 +/* 1169 */ MCD_OPC_Decode, 191, 10, 3, // Opcode: VSUM4SBS +/* 1173 */ MCD_OPC_FilterValue, 30, 92, 34, // Skip to: 9973 +/* 1177 */ MCD_OPC_Decode, 194, 10, 3, // Opcode: VSUMSWS +/* 1181 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 1195 +/* 1185 */ MCD_OPC_CheckField, 6, 5, 2, 78, 34, // Skip to: 9973 +/* 1191 */ MCD_OPC_Decode, 252, 9, 3, // Opcode: VMULUWM +/* 1195 */ MCD_OPC_FilterValue, 10, 179, 0, // Skip to: 1378 +/* 1199 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1202 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1210 +/* 1206 */ MCD_OPC_Decode, 140, 9, 3, // Opcode: VADDFP +/* 1210 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1218 +/* 1214 */ MCD_OPC_Decode, 179, 10, 3, // Opcode: VSUBFP +/* 1218 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 1232 +/* 1222 */ MCD_OPC_CheckField, 16, 5, 0, 41, 34, // Skip to: 9973 +/* 1228 */ MCD_OPC_Decode, 144, 10, 4, // Opcode: VREFP +/* 1232 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 1246 +/* 1236 */ MCD_OPC_CheckField, 16, 5, 0, 27, 34, // Skip to: 9973 +/* 1242 */ MCD_OPC_Decode, 153, 10, 4, // Opcode: VRSQRTEFP +/* 1246 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 1260 +/* 1250 */ MCD_OPC_CheckField, 16, 5, 0, 13, 34, // Skip to: 9973 +/* 1256 */ MCD_OPC_Decode, 204, 9, 4, // Opcode: VEXPTEFP +/* 1260 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 1274 +/* 1264 */ MCD_OPC_CheckField, 16, 5, 0, 255, 33, // Skip to: 9973 +/* 1270 */ MCD_OPC_Decode, 205, 9, 4, // Opcode: VLOGEFP +/* 1274 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 1288 +/* 1278 */ MCD_OPC_CheckField, 16, 5, 0, 241, 33, // Skip to: 9973 +/* 1284 */ MCD_OPC_Decode, 146, 10, 4, // Opcode: VRFIN +/* 1288 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 1302 +/* 1292 */ MCD_OPC_CheckField, 16, 5, 0, 227, 33, // Skip to: 9973 +/* 1298 */ MCD_OPC_Decode, 148, 10, 4, // Opcode: VRFIZ +/* 1302 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 1316 +/* 1306 */ MCD_OPC_CheckField, 16, 5, 0, 213, 33, // Skip to: 9973 +/* 1312 */ MCD_OPC_Decode, 147, 10, 4, // Opcode: VRFIP +/* 1316 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1330 +/* 1320 */ MCD_OPC_CheckField, 16, 5, 0, 199, 33, // Skip to: 9973 +/* 1326 */ MCD_OPC_Decode, 145, 10, 4, // Opcode: VRFIM +/* 1330 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1338 +/* 1334 */ MCD_OPC_Decode, 161, 9, 7, // Opcode: VCFUX +/* 1338 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1346 +/* 1342 */ MCD_OPC_Decode, 159, 9, 7, // Opcode: VCFSX +/* 1346 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1354 +/* 1350 */ MCD_OPC_Decode, 201, 9, 7, // Opcode: VCTUXS +/* 1354 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1362 +/* 1358 */ MCD_OPC_Decode, 199, 9, 7, // Opcode: VCTSXS +/* 1362 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1370 +/* 1366 */ MCD_OPC_Decode, 207, 9, 3, // Opcode: VMAXFP +/* 1370 */ MCD_OPC_FilterValue, 17, 151, 33, // Skip to: 9973 +/* 1374 */ MCD_OPC_Decode, 219, 9, 3, // Opcode: VMINFP +/* 1378 */ MCD_OPC_FilterValue, 12, 133, 0, // Skip to: 1515 +/* 1382 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1385 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1393 +/* 1389 */ MCD_OPC_Decode, 228, 9, 3, // Opcode: VMRGHB +/* 1393 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1401 +/* 1397 */ MCD_OPC_Decode, 229, 9, 3, // Opcode: VMRGHH +/* 1401 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1409 +/* 1405 */ MCD_OPC_Decode, 230, 9, 3, // Opcode: VMRGHW +/* 1409 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1417 +/* 1413 */ MCD_OPC_Decode, 231, 9, 3, // Opcode: VMRGLB +/* 1417 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1425 +/* 1421 */ MCD_OPC_Decode, 232, 9, 3, // Opcode: VMRGLH +/* 1425 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1433 +/* 1429 */ MCD_OPC_Decode, 233, 9, 3, // Opcode: VMRGLW +/* 1433 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1441 +/* 1437 */ MCD_OPC_Decode, 162, 10, 7, // Opcode: VSPLTB +/* 1441 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1449 +/* 1445 */ MCD_OPC_Decode, 163, 10, 7, // Opcode: VSPLTH +/* 1449 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1457 +/* 1453 */ MCD_OPC_Decode, 167, 10, 7, // Opcode: VSPLTW +/* 1457 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 1471 +/* 1461 */ MCD_OPC_CheckField, 11, 5, 0, 58, 33, // Skip to: 9973 +/* 1467 */ MCD_OPC_Decode, 164, 10, 8, // Opcode: VSPLTISB +/* 1471 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1485 +/* 1475 */ MCD_OPC_CheckField, 11, 5, 0, 44, 33, // Skip to: 9973 +/* 1481 */ MCD_OPC_Decode, 165, 10, 8, // Opcode: VSPLTISH +/* 1485 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 1499 +/* 1489 */ MCD_OPC_CheckField, 11, 5, 0, 30, 33, // Skip to: 9973 +/* 1495 */ MCD_OPC_Decode, 166, 10, 8, // Opcode: VSPLTISW +/* 1499 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1507 +/* 1503 */ MCD_OPC_Decode, 160, 10, 3, // Opcode: VSLO +/* 1507 */ MCD_OPC_FilterValue, 17, 14, 33, // Skip to: 9973 +/* 1511 */ MCD_OPC_Decode, 176, 10, 3, // Opcode: VSRO +/* 1515 */ MCD_OPC_FilterValue, 14, 159, 0, // Skip to: 1678 +/* 1519 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1522 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1530 +/* 1526 */ MCD_OPC_Decode, 136, 10, 3, // Opcode: VPKUHUM +/* 1530 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1538 +/* 1534 */ MCD_OPC_Decode, 138, 10, 3, // Opcode: VPKUWUM +/* 1538 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1546 +/* 1542 */ MCD_OPC_Decode, 137, 10, 3, // Opcode: VPKUHUS +/* 1546 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1554 +/* 1550 */ MCD_OPC_Decode, 139, 10, 3, // Opcode: VPKUWUS +/* 1554 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1562 +/* 1558 */ MCD_OPC_Decode, 133, 10, 3, // Opcode: VPKSHUS +/* 1562 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1570 +/* 1566 */ MCD_OPC_Decode, 135, 10, 3, // Opcode: VPKSWUS +/* 1570 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1578 +/* 1574 */ MCD_OPC_Decode, 132, 10, 3, // Opcode: VPKSHSS +/* 1578 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1586 +/* 1582 */ MCD_OPC_Decode, 134, 10, 3, // Opcode: VPKSWSS +/* 1586 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 1600 +/* 1590 */ MCD_OPC_CheckField, 16, 5, 0, 185, 32, // Skip to: 9973 +/* 1596 */ MCD_OPC_Decode, 196, 10, 4, // Opcode: VUPKHSB +/* 1600 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 1614 +/* 1604 */ MCD_OPC_CheckField, 16, 5, 0, 171, 32, // Skip to: 9973 +/* 1610 */ MCD_OPC_Decode, 197, 10, 4, // Opcode: VUPKHSH +/* 1614 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 1628 +/* 1618 */ MCD_OPC_CheckField, 16, 5, 0, 157, 32, // Skip to: 9973 +/* 1624 */ MCD_OPC_Decode, 199, 10, 4, // Opcode: VUPKLSB +/* 1628 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1642 +/* 1632 */ MCD_OPC_CheckField, 16, 5, 0, 143, 32, // Skip to: 9973 +/* 1638 */ MCD_OPC_Decode, 200, 10, 4, // Opcode: VUPKLSH +/* 1642 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1650 +/* 1646 */ MCD_OPC_Decode, 131, 10, 3, // Opcode: VPKPX +/* 1650 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1664 +/* 1654 */ MCD_OPC_CheckField, 16, 5, 0, 121, 32, // Skip to: 9973 +/* 1660 */ MCD_OPC_Decode, 195, 10, 4, // Opcode: VUPKHPX +/* 1664 */ MCD_OPC_FilterValue, 15, 113, 32, // Skip to: 9973 +/* 1668 */ MCD_OPC_CheckField, 16, 5, 0, 107, 32, // Skip to: 9973 +/* 1674 */ MCD_OPC_Decode, 198, 10, 4, // Opcode: VUPKLPX +/* 1678 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 1686 +/* 1682 */ MCD_OPC_Decode, 216, 9, 9, // Opcode: VMHADDSHS +/* 1686 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 1694 +/* 1690 */ MCD_OPC_Decode, 217, 9, 9, // Opcode: VMHRADDSHS +/* 1694 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 1702 +/* 1698 */ MCD_OPC_Decode, 227, 9, 9, // Opcode: VMLADDUHM +/* 1702 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 1710 +/* 1706 */ MCD_OPC_Decode, 237, 9, 9, // Opcode: VMSUMUBM +/* 1710 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 1718 +/* 1714 */ MCD_OPC_Decode, 234, 9, 9, // Opcode: VMSUMMBM +/* 1718 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 1726 +/* 1722 */ MCD_OPC_Decode, 238, 9, 9, // Opcode: VMSUMUHM +/* 1726 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 1734 +/* 1730 */ MCD_OPC_Decode, 239, 9, 9, // Opcode: VMSUMUHS +/* 1734 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 1742 +/* 1738 */ MCD_OPC_Decode, 235, 9, 9, // Opcode: VMSUMSHM +/* 1742 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 1750 +/* 1746 */ MCD_OPC_Decode, 236, 9, 9, // Opcode: VMSUMSHS +/* 1750 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 1758 +/* 1754 */ MCD_OPC_Decode, 154, 10, 9, // Opcode: VSEL +/* 1758 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 1766 +/* 1762 */ MCD_OPC_Decode, 130, 10, 9, // Opcode: VPERM +/* 1766 */ MCD_OPC_FilterValue, 44, 10, 0, // Skip to: 1780 +/* 1770 */ MCD_OPC_CheckField, 10, 1, 0, 5, 32, // Skip to: 9973 +/* 1776 */ MCD_OPC_Decode, 158, 10, 10, // Opcode: VSLDOI +/* 1780 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 1788 +/* 1784 */ MCD_OPC_Decode, 206, 9, 11, // Opcode: VMADDFP +/* 1788 */ MCD_OPC_FilterValue, 47, 245, 31, // Skip to: 9973 +/* 1792 */ MCD_OPC_Decode, 254, 9, 11, // Opcode: VNMSUBFP +/* 1796 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1804 +/* 1800 */ MCD_OPC_Decode, 236, 5, 12, // Opcode: MULLI +/* 1804 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1812 +/* 1808 */ MCD_OPC_Decode, 218, 8, 12, // Opcode: SUBFIC +/* 1812 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 1835 +/* 1816 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 1819 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1827 +/* 1823 */ MCD_OPC_Decode, 223, 1, 13, // Opcode: CMPLWI +/* 1827 */ MCD_OPC_FilterValue, 1, 206, 31, // Skip to: 9973 +/* 1831 */ MCD_OPC_Decode, 221, 1, 14, // Opcode: CMPLDI +/* 1835 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 1858 +/* 1839 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 1842 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1850 +/* 1846 */ MCD_OPC_Decode, 225, 1, 15, // Opcode: CMPWI +/* 1850 */ MCD_OPC_FilterValue, 1, 183, 31, // Skip to: 9973 +/* 1854 */ MCD_OPC_Decode, 219, 1, 16, // Opcode: CMPDI +/* 1858 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 1865 +/* 1862 */ MCD_OPC_Decode, 39, 12, // Opcode: ADDIC +/* 1865 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 1872 +/* 1869 */ MCD_OPC_Decode, 41, 12, // Opcode: ADDICo +/* 1872 */ MCD_OPC_FilterValue, 14, 13, 0, // Skip to: 1889 +/* 1876 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, // Skip to: 1886 +/* 1882 */ MCD_OPC_Decode, 141, 5, 17, // Opcode: LI +/* 1886 */ MCD_OPC_Decode, 37, 18, // Opcode: ADDI +/* 1889 */ MCD_OPC_FilterValue, 15, 13, 0, // Skip to: 1906 +/* 1893 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, // Skip to: 1903 +/* 1899 */ MCD_OPC_Decode, 143, 5, 17, // Opcode: LIS +/* 1903 */ MCD_OPC_Decode, 42, 18, // Opcode: ADDIS +/* 1906 */ MCD_OPC_FilterValue, 16, 7, 1, // Skip to: 2173 +/* 1910 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 1913 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 1978 +/* 1917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 1920 */ MCD_OPC_FilterValue, 128, 4, 4, 0, // Skip to: 1929 +/* 1925 */ MCD_OPC_Decode, 154, 1, 19, // Opcode: BDNZ +/* 1929 */ MCD_OPC_FilterValue, 192, 4, 4, 0, // Skip to: 1938 +/* 1934 */ MCD_OPC_Decode, 174, 1, 19, // Opcode: BDZ +/* 1938 */ MCD_OPC_FilterValue, 128, 6, 4, 0, // Skip to: 1947 +/* 1943 */ MCD_OPC_Decode, 172, 1, 19, // Opcode: BDNZm +/* 1947 */ MCD_OPC_FilterValue, 160, 6, 4, 0, // Skip to: 1956 +/* 1952 */ MCD_OPC_Decode, 173, 1, 19, // Opcode: BDNZp +/* 1956 */ MCD_OPC_FilterValue, 192, 6, 4, 0, // Skip to: 1965 +/* 1961 */ MCD_OPC_Decode, 192, 1, 19, // Opcode: BDZm +/* 1965 */ MCD_OPC_FilterValue, 224, 6, 4, 0, // Skip to: 1974 +/* 1970 */ MCD_OPC_Decode, 193, 1, 19, // Opcode: BDZp +/* 1974 */ MCD_OPC_Decode, 230, 11, 20, // Opcode: gBC +/* 1978 */ MCD_OPC_FilterValue, 1, 61, 0, // Skip to: 2043 +/* 1982 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 1985 */ MCD_OPC_FilterValue, 128, 4, 4, 0, // Skip to: 1994 +/* 1990 */ MCD_OPC_Decode, 159, 1, 19, // Opcode: BDNZL +/* 1994 */ MCD_OPC_FilterValue, 192, 4, 4, 0, // Skip to: 2003 +/* 1999 */ MCD_OPC_Decode, 179, 1, 19, // Opcode: BDZL +/* 2003 */ MCD_OPC_FilterValue, 128, 6, 4, 0, // Skip to: 2012 +/* 2008 */ MCD_OPC_Decode, 170, 1, 19, // Opcode: BDNZLm +/* 2012 */ MCD_OPC_FilterValue, 160, 6, 4, 0, // Skip to: 2021 +/* 2017 */ MCD_OPC_Decode, 171, 1, 19, // Opcode: BDNZLp +/* 2021 */ MCD_OPC_FilterValue, 192, 6, 4, 0, // Skip to: 2030 +/* 2026 */ MCD_OPC_Decode, 190, 1, 19, // Opcode: BDZLm +/* 2030 */ MCD_OPC_FilterValue, 224, 6, 4, 0, // Skip to: 2039 +/* 2035 */ MCD_OPC_Decode, 191, 1, 19, // Opcode: BDZLp +/* 2039 */ MCD_OPC_Decode, 234, 11, 20, // Opcode: gBCL +/* 2043 */ MCD_OPC_FilterValue, 2, 61, 0, // Skip to: 2108 +/* 2047 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 2050 */ MCD_OPC_FilterValue, 128, 4, 4, 0, // Skip to: 2059 +/* 2055 */ MCD_OPC_Decode, 156, 1, 19, // Opcode: BDNZA +/* 2059 */ MCD_OPC_FilterValue, 192, 4, 4, 0, // Skip to: 2068 +/* 2064 */ MCD_OPC_Decode, 176, 1, 19, // Opcode: BDZA +/* 2068 */ MCD_OPC_FilterValue, 128, 6, 4, 0, // Skip to: 2077 +/* 2073 */ MCD_OPC_Decode, 157, 1, 19, // Opcode: BDNZAm +/* 2077 */ MCD_OPC_FilterValue, 160, 6, 4, 0, // Skip to: 2086 +/* 2082 */ MCD_OPC_Decode, 158, 1, 19, // Opcode: BDNZAp +/* 2086 */ MCD_OPC_FilterValue, 192, 6, 4, 0, // Skip to: 2095 +/* 2091 */ MCD_OPC_Decode, 177, 1, 19, // Opcode: BDZAm +/* 2095 */ MCD_OPC_FilterValue, 224, 6, 4, 0, // Skip to: 2104 +/* 2100 */ MCD_OPC_Decode, 178, 1, 19, // Opcode: BDZAp +/* 2104 */ MCD_OPC_Decode, 231, 11, 20, // Opcode: gBCA +/* 2108 */ MCD_OPC_FilterValue, 3, 181, 30, // Skip to: 9973 +/* 2112 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 2115 */ MCD_OPC_FilterValue, 128, 4, 4, 0, // Skip to: 2124 +/* 2120 */ MCD_OPC_Decode, 160, 1, 19, // Opcode: BDNZLA +/* 2124 */ MCD_OPC_FilterValue, 192, 4, 4, 0, // Skip to: 2133 +/* 2129 */ MCD_OPC_Decode, 180, 1, 19, // Opcode: BDZLA +/* 2133 */ MCD_OPC_FilterValue, 128, 6, 4, 0, // Skip to: 2142 +/* 2138 */ MCD_OPC_Decode, 161, 1, 19, // Opcode: BDNZLAm +/* 2142 */ MCD_OPC_FilterValue, 160, 6, 4, 0, // Skip to: 2151 +/* 2147 */ MCD_OPC_Decode, 162, 1, 19, // Opcode: BDNZLAp +/* 2151 */ MCD_OPC_FilterValue, 192, 6, 4, 0, // Skip to: 2160 +/* 2156 */ MCD_OPC_Decode, 181, 1, 19, // Opcode: BDZLAm +/* 2160 */ MCD_OPC_FilterValue, 224, 6, 4, 0, // Skip to: 2169 +/* 2165 */ MCD_OPC_Decode, 182, 1, 19, // Opcode: BDZLAp +/* 2169 */ MCD_OPC_Decode, 235, 11, 20, // Opcode: gBCLA +/* 2173 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 2187 +/* 2177 */ MCD_OPC_CheckField, 1, 1, 1, 110, 30, // Skip to: 9973 +/* 2183 */ MCD_OPC_Decode, 223, 7, 21, // Opcode: SC +/* 2187 */ MCD_OPC_FilterValue, 18, 33, 0, // Skip to: 2224 +/* 2191 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2194 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2201 +/* 2198 */ MCD_OPC_Decode, 120, 22, // Opcode: B +/* 2201 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2209 +/* 2205 */ MCD_OPC_Decode, 194, 1, 22, // Opcode: BL +/* 2209 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 2216 +/* 2213 */ MCD_OPC_Decode, 121, 22, // Opcode: BA +/* 2216 */ MCD_OPC_FilterValue, 3, 73, 30, // Skip to: 9973 +/* 2220 */ MCD_OPC_Decode, 200, 1, 22, // Opcode: BLA +/* 2224 */ MCD_OPC_FilterValue, 19, 235, 1, // Skip to: 2719 +/* 2228 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 2231 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 2251 +/* 2235 */ MCD_OPC_CheckField, 21, 2, 0, 52, 30, // Skip to: 9973 +/* 2241 */ MCD_OPC_CheckField, 11, 7, 0, 46, 30, // Skip to: 9973 +/* 2247 */ MCD_OPC_Decode, 177, 5, 23, // Opcode: MCRF +/* 2251 */ MCD_OPC_FilterValue, 32, 119, 0, // Skip to: 2374 +/* 2255 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 2258 */ MCD_OPC_FilterValue, 0, 31, 30, // Skip to: 9973 +/* 2262 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 2265 */ MCD_OPC_FilterValue, 128, 4, 10, 0, // Skip to: 2280 +/* 2270 */ MCD_OPC_CheckField, 11, 2, 0, 94, 0, // Skip to: 2370 +/* 2276 */ MCD_OPC_Decode, 163, 1, 0, // Opcode: BDNZLR +/* 2280 */ MCD_OPC_FilterValue, 192, 4, 10, 0, // Skip to: 2295 +/* 2285 */ MCD_OPC_CheckField, 11, 2, 0, 79, 0, // Skip to: 2370 +/* 2291 */ MCD_OPC_Decode, 183, 1, 0, // Opcode: BDZLR +/* 2295 */ MCD_OPC_FilterValue, 128, 5, 10, 0, // Skip to: 2310 +/* 2300 */ MCD_OPC_CheckField, 11, 2, 0, 64, 0, // Skip to: 2370 +/* 2306 */ MCD_OPC_Decode, 203, 1, 0, // Opcode: BLR +/* 2310 */ MCD_OPC_FilterValue, 128, 6, 10, 0, // Skip to: 2325 +/* 2315 */ MCD_OPC_CheckField, 11, 2, 0, 49, 0, // Skip to: 2370 +/* 2321 */ MCD_OPC_Decode, 168, 1, 0, // Opcode: BDNZLRm +/* 2325 */ MCD_OPC_FilterValue, 160, 6, 10, 0, // Skip to: 2340 +/* 2330 */ MCD_OPC_CheckField, 11, 2, 0, 34, 0, // Skip to: 2370 +/* 2336 */ MCD_OPC_Decode, 169, 1, 0, // Opcode: BDNZLRp +/* 2340 */ MCD_OPC_FilterValue, 192, 6, 10, 0, // Skip to: 2355 +/* 2345 */ MCD_OPC_CheckField, 11, 2, 0, 19, 0, // Skip to: 2370 +/* 2351 */ MCD_OPC_Decode, 188, 1, 0, // Opcode: BDZLRm +/* 2355 */ MCD_OPC_FilterValue, 224, 6, 10, 0, // Skip to: 2370 +/* 2360 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2370 +/* 2366 */ MCD_OPC_Decode, 189, 1, 0, // Opcode: BDZLRp +/* 2370 */ MCD_OPC_Decode, 236, 11, 24, // Opcode: gBCLR +/* 2374 */ MCD_OPC_FilterValue, 33, 119, 0, // Skip to: 2497 +/* 2378 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 2381 */ MCD_OPC_FilterValue, 0, 164, 29, // Skip to: 9973 +/* 2385 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 2388 */ MCD_OPC_FilterValue, 128, 4, 10, 0, // Skip to: 2403 +/* 2393 */ MCD_OPC_CheckField, 11, 2, 0, 94, 0, // Skip to: 2493 +/* 2399 */ MCD_OPC_Decode, 165, 1, 0, // Opcode: BDNZLRL +/* 2403 */ MCD_OPC_FilterValue, 192, 4, 10, 0, // Skip to: 2418 +/* 2408 */ MCD_OPC_CheckField, 11, 2, 0, 79, 0, // Skip to: 2493 +/* 2414 */ MCD_OPC_Decode, 185, 1, 0, // Opcode: BDZLRL +/* 2418 */ MCD_OPC_FilterValue, 128, 5, 10, 0, // Skip to: 2433 +/* 2423 */ MCD_OPC_CheckField, 11, 2, 0, 64, 0, // Skip to: 2493 +/* 2429 */ MCD_OPC_Decode, 205, 1, 0, // Opcode: BLRL +/* 2433 */ MCD_OPC_FilterValue, 128, 6, 10, 0, // Skip to: 2448 +/* 2438 */ MCD_OPC_CheckField, 11, 2, 0, 49, 0, // Skip to: 2493 +/* 2444 */ MCD_OPC_Decode, 166, 1, 0, // Opcode: BDNZLRLm +/* 2448 */ MCD_OPC_FilterValue, 160, 6, 10, 0, // Skip to: 2463 +/* 2453 */ MCD_OPC_CheckField, 11, 2, 0, 34, 0, // Skip to: 2493 +/* 2459 */ MCD_OPC_Decode, 167, 1, 0, // Opcode: BDNZLRLp +/* 2463 */ MCD_OPC_FilterValue, 192, 6, 10, 0, // Skip to: 2478 +/* 2468 */ MCD_OPC_CheckField, 11, 2, 0, 19, 0, // Skip to: 2493 +/* 2474 */ MCD_OPC_Decode, 186, 1, 0, // Opcode: BDZLRLm +/* 2478 */ MCD_OPC_FilterValue, 224, 6, 10, 0, // Skip to: 2493 +/* 2483 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2493 +/* 2489 */ MCD_OPC_Decode, 187, 1, 0, // Opcode: BDZLRLp +/* 2493 */ MCD_OPC_Decode, 237, 11, 24, // Opcode: gBCLRL +/* 2497 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 2511 +/* 2501 */ MCD_OPC_CheckField, 11, 15, 0, 42, 29, // Skip to: 9973 +/* 2507 */ MCD_OPC_Decode, 191, 7, 0, // Opcode: RFID +/* 2511 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 2519 +/* 2515 */ MCD_OPC_Decode, 238, 1, 25, // Opcode: CRNOR +/* 2519 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 2533 +/* 2523 */ MCD_OPC_CheckField, 11, 15, 0, 20, 29, // Skip to: 9973 +/* 2529 */ MCD_OPC_Decode, 192, 7, 0, // Opcode: RFMCI +/* 2533 */ MCD_OPC_FilterValue, 78, 10, 0, // Skip to: 2547 +/* 2537 */ MCD_OPC_CheckField, 11, 15, 0, 6, 29, // Skip to: 9973 +/* 2543 */ MCD_OPC_Decode, 189, 7, 0, // Opcode: RFDI +/* 2547 */ MCD_OPC_FilterValue, 100, 10, 0, // Skip to: 2561 +/* 2551 */ MCD_OPC_CheckField, 11, 15, 0, 248, 28, // Skip to: 9973 +/* 2557 */ MCD_OPC_Decode, 190, 7, 0, // Opcode: RFI +/* 2561 */ MCD_OPC_FilterValue, 102, 10, 0, // Skip to: 2575 +/* 2565 */ MCD_OPC_CheckField, 11, 15, 0, 234, 28, // Skip to: 9973 +/* 2571 */ MCD_OPC_Decode, 188, 7, 0, // Opcode: RFCI +/* 2575 */ MCD_OPC_FilterValue, 130, 2, 4, 0, // Skip to: 2584 +/* 2580 */ MCD_OPC_Decode, 235, 1, 25, // Opcode: CRANDC +/* 2584 */ MCD_OPC_FilterValue, 172, 2, 10, 0, // Skip to: 2599 +/* 2589 */ MCD_OPC_CheckField, 11, 15, 0, 210, 28, // Skip to: 9973 +/* 2595 */ MCD_OPC_Decode, 214, 4, 0, // Opcode: ISYNC +/* 2599 */ MCD_OPC_FilterValue, 130, 3, 4, 0, // Skip to: 2608 +/* 2604 */ MCD_OPC_Decode, 243, 1, 25, // Opcode: CRXOR +/* 2608 */ MCD_OPC_FilterValue, 194, 3, 4, 0, // Skip to: 2617 +/* 2613 */ MCD_OPC_Decode, 237, 1, 25, // Opcode: CRNAND +/* 2617 */ MCD_OPC_FilterValue, 130, 4, 4, 0, // Skip to: 2626 +/* 2622 */ MCD_OPC_Decode, 234, 1, 25, // Opcode: CRAND +/* 2626 */ MCD_OPC_FilterValue, 194, 4, 4, 0, // Skip to: 2635 +/* 2631 */ MCD_OPC_Decode, 236, 1, 25, // Opcode: CREQV +/* 2635 */ MCD_OPC_FilterValue, 194, 6, 4, 0, // Skip to: 2644 +/* 2640 */ MCD_OPC_Decode, 240, 1, 25, // Opcode: CRORC +/* 2644 */ MCD_OPC_FilterValue, 130, 7, 4, 0, // Skip to: 2653 +/* 2649 */ MCD_OPC_Decode, 239, 1, 25, // Opcode: CROR +/* 2653 */ MCD_OPC_FilterValue, 160, 8, 28, 0, // Skip to: 2686 +/* 2658 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 2661 */ MCD_OPC_FilterValue, 0, 140, 28, // Skip to: 9973 +/* 2665 */ MCD_OPC_CheckField, 16, 10, 128, 5, 10, 0, // Skip to: 2682 +/* 2672 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2682 +/* 2678 */ MCD_OPC_Decode, 148, 1, 0, // Opcode: BCTR +/* 2682 */ MCD_OPC_Decode, 232, 11, 24, // Opcode: gBCCTR +/* 2686 */ MCD_OPC_FilterValue, 161, 8, 114, 28, // Skip to: 9973 +/* 2691 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 2694 */ MCD_OPC_FilterValue, 0, 107, 28, // Skip to: 9973 +/* 2698 */ MCD_OPC_CheckField, 16, 10, 128, 5, 10, 0, // Skip to: 2715 +/* 2705 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2715 +/* 2711 */ MCD_OPC_Decode, 150, 1, 0, // Opcode: BCTRL +/* 2715 */ MCD_OPC_Decode, 233, 11, 24, // Opcode: gBCCTRL +/* 2719 */ MCD_OPC_FilterValue, 20, 19, 0, // Skip to: 2742 +/* 2723 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2726 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2734 +/* 2730 */ MCD_OPC_Decode, 206, 7, 26, // Opcode: RLWIMI +/* 2734 */ MCD_OPC_FilterValue, 1, 67, 28, // Skip to: 9973 +/* 2738 */ MCD_OPC_Decode, 209, 7, 26, // Opcode: RLWIMIo +/* 2742 */ MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 2765 +/* 2746 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2749 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2757 +/* 2753 */ MCD_OPC_Decode, 210, 7, 27, // Opcode: RLWINM +/* 2757 */ MCD_OPC_FilterValue, 1, 44, 28, // Skip to: 9973 +/* 2761 */ MCD_OPC_Decode, 213, 7, 27, // Opcode: RLWINMo +/* 2765 */ MCD_OPC_FilterValue, 23, 19, 0, // Skip to: 2788 +/* 2769 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2772 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2780 +/* 2776 */ MCD_OPC_Decode, 214, 7, 28, // Opcode: RLWNM +/* 2780 */ MCD_OPC_FilterValue, 1, 21, 28, // Skip to: 9973 +/* 2784 */ MCD_OPC_Decode, 217, 7, 28, // Opcode: RLWNMo +/* 2788 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 2806 +/* 2792 */ MCD_OPC_CheckField, 0, 26, 0, 4, 0, // Skip to: 2802 +/* 2798 */ MCD_OPC_Decode, 251, 5, 0, // Opcode: NOP +/* 2802 */ MCD_OPC_Decode, 137, 6, 29, // Opcode: ORI +/* 2806 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 2814 +/* 2810 */ MCD_OPC_Decode, 139, 6, 29, // Opcode: ORIS +/* 2814 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 2822 +/* 2818 */ MCD_OPC_Decode, 214, 10, 29, // Opcode: XORI +/* 2822 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 2830 +/* 2826 */ MCD_OPC_Decode, 216, 10, 29, // Opcode: XORIS +/* 2830 */ MCD_OPC_FilterValue, 28, 3, 0, // Skip to: 2837 +/* 2834 */ MCD_OPC_Decode, 80, 29, // Opcode: ANDIo +/* 2837 */ MCD_OPC_FilterValue, 29, 3, 0, // Skip to: 2844 +/* 2841 */ MCD_OPC_Decode, 78, 29, // Opcode: ANDISo +/* 2844 */ MCD_OPC_FilterValue, 30, 134, 0, // Skip to: 2982 +/* 2848 */ MCD_OPC_ExtractField, 2, 3, // Inst{4-2} ... +/* 2851 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 2874 +/* 2855 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2858 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2866 +/* 2862 */ MCD_OPC_Decode, 198, 7, 30, // Opcode: RLDICL +/* 2866 */ MCD_OPC_FilterValue, 1, 191, 27, // Skip to: 9973 +/* 2870 */ MCD_OPC_Decode, 200, 7, 30, // Opcode: RLDICLo +/* 2874 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 2897 +/* 2878 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2881 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2889 +/* 2885 */ MCD_OPC_Decode, 201, 7, 30, // Opcode: RLDICR +/* 2889 */ MCD_OPC_FilterValue, 1, 168, 27, // Skip to: 9973 +/* 2893 */ MCD_OPC_Decode, 202, 7, 30, // Opcode: RLDICRo +/* 2897 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 2920 +/* 2901 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2904 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2912 +/* 2908 */ MCD_OPC_Decode, 197, 7, 30, // Opcode: RLDIC +/* 2912 */ MCD_OPC_FilterValue, 1, 145, 27, // Skip to: 9973 +/* 2916 */ MCD_OPC_Decode, 203, 7, 30, // Opcode: RLDICo +/* 2920 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 2943 +/* 2924 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2927 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2935 +/* 2931 */ MCD_OPC_Decode, 204, 7, 31, // Opcode: RLDIMI +/* 2935 */ MCD_OPC_FilterValue, 1, 122, 27, // Skip to: 9973 +/* 2939 */ MCD_OPC_Decode, 205, 7, 31, // Opcode: RLDIMIo +/* 2943 */ MCD_OPC_FilterValue, 4, 114, 27, // Skip to: 9973 +/* 2947 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 2950 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2958 +/* 2954 */ MCD_OPC_Decode, 193, 7, 32, // Opcode: RLDCL +/* 2958 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2966 +/* 2962 */ MCD_OPC_Decode, 194, 7, 32, // Opcode: RLDCLo +/* 2966 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 2974 +/* 2970 */ MCD_OPC_Decode, 195, 7, 32, // Opcode: RLDCR +/* 2974 */ MCD_OPC_FilterValue, 3, 83, 27, // Skip to: 9973 +/* 2978 */ MCD_OPC_Decode, 196, 7, 32, // Opcode: RLDCRo +/* 2982 */ MCD_OPC_FilterValue, 31, 179, 12, // Skip to: 6237 +/* 2986 */ MCD_OPC_ExtractField, 2, 4, // Inst{5-2} ... +/* 2989 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 3066 +/* 2993 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 2996 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3031 +/* 3000 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 3003 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 3017 +/* 3007 */ MCD_OPC_CheckField, 0, 2, 0, 48, 27, // Skip to: 9973 +/* 3013 */ MCD_OPC_Decode, 224, 1, 33, // Opcode: CMPW +/* 3017 */ MCD_OPC_FilterValue, 1, 40, 27, // Skip to: 9973 +/* 3021 */ MCD_OPC_CheckField, 0, 2, 0, 34, 27, // Skip to: 9973 +/* 3027 */ MCD_OPC_Decode, 218, 1, 34, // Opcode: CMPD +/* 3031 */ MCD_OPC_FilterValue, 1, 26, 27, // Skip to: 9973 +/* 3035 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 3038 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 3052 +/* 3042 */ MCD_OPC_CheckField, 0, 2, 0, 13, 27, // Skip to: 9973 +/* 3048 */ MCD_OPC_Decode, 222, 1, 33, // Opcode: CMPLW +/* 3052 */ MCD_OPC_FilterValue, 1, 5, 27, // Skip to: 9973 +/* 3056 */ MCD_OPC_CheckField, 0, 2, 0, 255, 26, // Skip to: 9973 +/* 3062 */ MCD_OPC_Decode, 220, 1, 34, // Opcode: CMPLD +/* 3066 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 3135 +/* 3070 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3073 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 3093 +/* 3077 */ MCD_OPC_CheckField, 16, 1, 0, 234, 26, // Skip to: 9973 +/* 3083 */ MCD_OPC_CheckField, 1, 1, 1, 228, 26, // Skip to: 9973 +/* 3089 */ MCD_OPC_Decode, 209, 10, 35, // Opcode: WRTEE +/* 3093 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 3107 +/* 3097 */ MCD_OPC_CheckField, 1, 1, 1, 214, 26, // Skip to: 9973 +/* 3103 */ MCD_OPC_Decode, 210, 10, 36, // Opcode: WRTEEI +/* 3107 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 3121 +/* 3111 */ MCD_OPC_CheckField, 0, 2, 2, 200, 26, // Skip to: 9973 +/* 3117 */ MCD_OPC_Decode, 183, 5, 37, // Opcode: MFDCR +/* 3121 */ MCD_OPC_FilterValue, 14, 192, 26, // Skip to: 9973 +/* 3125 */ MCD_OPC_CheckField, 0, 2, 2, 186, 26, // Skip to: 9973 +/* 3131 */ MCD_OPC_Decode, 206, 5, 37, // Opcode: MTDCR +/* 3135 */ MCD_OPC_FilterValue, 2, 44, 0, // Skip to: 3183 +/* 3139 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3142 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 3169 +/* 3146 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3149 */ MCD_OPC_FilterValue, 0, 164, 26, // Skip to: 9973 +/* 3153 */ MCD_OPC_CheckField, 11, 15, 128, 248, 1, 4, 0, // Skip to: 3165 +/* 3161 */ MCD_OPC_Decode, 134, 9, 0, // Opcode: TRAP +/* 3165 */ MCD_OPC_Decode, 135, 9, 38, // Opcode: TW +/* 3169 */ MCD_OPC_FilterValue, 2, 144, 26, // Skip to: 9973 +/* 3173 */ MCD_OPC_CheckField, 0, 2, 0, 138, 26, // Skip to: 9973 +/* 3179 */ MCD_OPC_Decode, 246, 8, 39, // Opcode: TD +/* 3183 */ MCD_OPC_FilterValue, 3, 201, 0, // Skip to: 3388 +/* 3187 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3190 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 3213 +/* 3194 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3197 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 3205 +/* 3201 */ MCD_OPC_Decode, 150, 5, 40, // Opcode: LVSL +/* 3205 */ MCD_OPC_FilterValue, 2, 108, 26, // Skip to: 9973 +/* 3209 */ MCD_OPC_Decode, 147, 5, 40, // Opcode: LVEBX +/* 3213 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 3236 +/* 3217 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3220 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 3228 +/* 3224 */ MCD_OPC_Decode, 151, 5, 40, // Opcode: LVSR +/* 3228 */ MCD_OPC_FilterValue, 2, 85, 26, // Skip to: 9973 +/* 3232 */ MCD_OPC_Decode, 148, 5, 40, // Opcode: LVEHX +/* 3236 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 3250 +/* 3240 */ MCD_OPC_CheckField, 0, 2, 2, 71, 26, // Skip to: 9973 +/* 3246 */ MCD_OPC_Decode, 149, 5, 40, // Opcode: LVEWX +/* 3250 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 3264 +/* 3254 */ MCD_OPC_CheckField, 0, 2, 2, 57, 26, // Skip to: 9973 +/* 3260 */ MCD_OPC_Decode, 152, 5, 40, // Opcode: LVX +/* 3264 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 3278 +/* 3268 */ MCD_OPC_CheckField, 0, 2, 2, 43, 26, // Skip to: 9973 +/* 3274 */ MCD_OPC_Decode, 188, 8, 40, // Opcode: STVEBX +/* 3278 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 3292 +/* 3282 */ MCD_OPC_CheckField, 0, 2, 2, 29, 26, // Skip to: 9973 +/* 3288 */ MCD_OPC_Decode, 189, 8, 40, // Opcode: STVEHX +/* 3292 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 3306 +/* 3296 */ MCD_OPC_CheckField, 0, 2, 2, 15, 26, // Skip to: 9973 +/* 3302 */ MCD_OPC_Decode, 190, 8, 40, // Opcode: STVEWX +/* 3306 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 3320 +/* 3310 */ MCD_OPC_CheckField, 0, 2, 2, 1, 26, // Skip to: 9973 +/* 3316 */ MCD_OPC_Decode, 191, 8, 40, // Opcode: STVX +/* 3320 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 3334 +/* 3324 */ MCD_OPC_CheckField, 0, 2, 2, 243, 25, // Skip to: 9973 +/* 3330 */ MCD_OPC_Decode, 153, 5, 40, // Opcode: LVXL +/* 3334 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 3354 +/* 3338 */ MCD_OPC_CheckField, 21, 5, 0, 229, 25, // Skip to: 9973 +/* 3344 */ MCD_OPC_CheckField, 0, 2, 0, 223, 25, // Skip to: 9973 +/* 3350 */ MCD_OPC_Decode, 252, 1, 41, // Opcode: DCCCI +/* 3354 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 3368 +/* 3358 */ MCD_OPC_CheckField, 0, 2, 2, 209, 25, // Skip to: 9973 +/* 3364 */ MCD_OPC_Decode, 192, 8, 40, // Opcode: STVXL +/* 3368 */ MCD_OPC_FilterValue, 30, 201, 25, // Skip to: 9973 +/* 3372 */ MCD_OPC_CheckField, 21, 5, 0, 195, 25, // Skip to: 9973 +/* 3378 */ MCD_OPC_CheckField, 0, 2, 0, 189, 25, // Skip to: 9973 +/* 3384 */ MCD_OPC_Decode, 205, 4, 41, // Opcode: ICCCI +/* 3388 */ MCD_OPC_FilterValue, 4, 22, 1, // Skip to: 3670 +/* 3392 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3395 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 3434 +/* 3399 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3402 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 3410 +/* 3406 */ MCD_OPC_Decode, 210, 8, 42, // Opcode: SUBFC +/* 3410 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3418 +/* 3414 */ MCD_OPC_Decode, 213, 8, 42, // Opcode: SUBFCo +/* 3418 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3426 +/* 3422 */ MCD_OPC_Decode, 227, 5, 43, // Opcode: MULHDU +/* 3426 */ MCD_OPC_FilterValue, 3, 143, 25, // Skip to: 9973 +/* 3430 */ MCD_OPC_Decode, 228, 5, 43, // Opcode: MULHDUo +/* 3434 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 3457 +/* 3438 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3441 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 3449 +/* 3445 */ MCD_OPC_Decode, 207, 8, 42, // Opcode: SUBF +/* 3449 */ MCD_OPC_FilterValue, 1, 120, 25, // Skip to: 9973 +/* 3453 */ MCD_OPC_Decode, 228, 8, 42, // Opcode: SUBFo +/* 3457 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 3480 +/* 3461 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3464 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3472 +/* 3468 */ MCD_OPC_Decode, 226, 5, 43, // Opcode: MULHD +/* 3472 */ MCD_OPC_FilterValue, 3, 97, 25, // Skip to: 9973 +/* 3476 */ MCD_OPC_Decode, 229, 5, 43, // Opcode: MULHDo +/* 3480 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 3515 +/* 3484 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3487 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 3501 +/* 3491 */ MCD_OPC_CheckField, 11, 5, 0, 76, 25, // Skip to: 9973 +/* 3497 */ MCD_OPC_Decode, 247, 5, 44, // Opcode: NEG +/* 3501 */ MCD_OPC_FilterValue, 1, 68, 25, // Skip to: 9973 +/* 3505 */ MCD_OPC_CheckField, 11, 5, 0, 62, 25, // Skip to: 9973 +/* 3511 */ MCD_OPC_Decode, 250, 5, 44, // Opcode: NEGo +/* 3515 */ MCD_OPC_FilterValue, 4, 19, 0, // Skip to: 3538 +/* 3519 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3522 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 3530 +/* 3526 */ MCD_OPC_Decode, 214, 8, 42, // Opcode: SUBFE +/* 3530 */ MCD_OPC_FilterValue, 1, 39, 25, // Skip to: 9973 +/* 3534 */ MCD_OPC_Decode, 217, 8, 42, // Opcode: SUBFEo +/* 3538 */ MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 3573 +/* 3542 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3545 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 3559 +/* 3549 */ MCD_OPC_CheckField, 11, 5, 0, 18, 25, // Skip to: 9973 +/* 3555 */ MCD_OPC_Decode, 224, 8, 44, // Opcode: SUBFZE +/* 3559 */ MCD_OPC_FilterValue, 1, 10, 25, // Skip to: 9973 +/* 3563 */ MCD_OPC_CheckField, 11, 5, 0, 4, 25, // Skip to: 9973 +/* 3569 */ MCD_OPC_Decode, 227, 8, 44, // Opcode: SUBFZEo +/* 3573 */ MCD_OPC_FilterValue, 7, 47, 0, // Skip to: 3624 +/* 3577 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3580 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 3594 +/* 3584 */ MCD_OPC_CheckField, 11, 5, 0, 239, 24, // Skip to: 9973 +/* 3590 */ MCD_OPC_Decode, 220, 8, 44, // Opcode: SUBFME +/* 3594 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 3608 +/* 3598 */ MCD_OPC_CheckField, 11, 5, 0, 225, 24, // Skip to: 9973 +/* 3604 */ MCD_OPC_Decode, 223, 8, 44, // Opcode: SUBFMEo +/* 3608 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3616 +/* 3612 */ MCD_OPC_Decode, 234, 5, 43, // Opcode: MULLD +/* 3616 */ MCD_OPC_FilterValue, 3, 209, 24, // Skip to: 9973 +/* 3620 */ MCD_OPC_Decode, 235, 5, 43, // Opcode: MULLDo +/* 3624 */ MCD_OPC_FilterValue, 14, 19, 0, // Skip to: 3647 +/* 3628 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3631 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3639 +/* 3635 */ MCD_OPC_Decode, 254, 1, 43, // Opcode: DIVDU +/* 3639 */ MCD_OPC_FilterValue, 3, 186, 24, // Skip to: 9973 +/* 3643 */ MCD_OPC_Decode, 255, 1, 43, // Opcode: DIVDUo +/* 3647 */ MCD_OPC_FilterValue, 15, 178, 24, // Skip to: 9973 +/* 3651 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3654 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3662 +/* 3658 */ MCD_OPC_Decode, 253, 1, 43, // Opcode: DIVD +/* 3662 */ MCD_OPC_FilterValue, 3, 163, 24, // Skip to: 9973 +/* 3666 */ MCD_OPC_Decode, 128, 2, 43, // Opcode: DIVDo +/* 3670 */ MCD_OPC_FilterValue, 5, 233, 0, // Skip to: 3907 +/* 3674 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3677 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 3714 +/* 3681 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3684 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 3691 +/* 3688 */ MCD_OPC_Decode, 29, 42, // Opcode: ADDC +/* 3691 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 3698 +/* 3695 */ MCD_OPC_Decode, 32, 42, // Opcode: ADDCo +/* 3698 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3706 +/* 3702 */ MCD_OPC_Decode, 231, 5, 42, // Opcode: MULHWU +/* 3706 */ MCD_OPC_FilterValue, 3, 119, 24, // Skip to: 9973 +/* 3710 */ MCD_OPC_Decode, 232, 5, 42, // Opcode: MULHWUo +/* 3714 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 3737 +/* 3718 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3721 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3729 +/* 3725 */ MCD_OPC_Decode, 230, 5, 42, // Opcode: MULHW +/* 3729 */ MCD_OPC_FilterValue, 3, 96, 24, // Skip to: 9973 +/* 3733 */ MCD_OPC_Decode, 233, 5, 42, // Opcode: MULHWo +/* 3737 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 3758 +/* 3741 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3744 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 3751 +/* 3748 */ MCD_OPC_Decode, 33, 42, // Opcode: ADDE +/* 3751 */ MCD_OPC_FilterValue, 1, 74, 24, // Skip to: 9973 +/* 3755 */ MCD_OPC_Decode, 36, 42, // Opcode: ADDEo +/* 3758 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 3791 +/* 3762 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3765 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3778 +/* 3769 */ MCD_OPC_CheckField, 11, 5, 0, 54, 24, // Skip to: 9973 +/* 3775 */ MCD_OPC_Decode, 65, 44, // Opcode: ADDZE +/* 3778 */ MCD_OPC_FilterValue, 1, 47, 24, // Skip to: 9973 +/* 3782 */ MCD_OPC_CheckField, 11, 5, 0, 41, 24, // Skip to: 9973 +/* 3788 */ MCD_OPC_Decode, 68, 44, // Opcode: ADDZEo +/* 3791 */ MCD_OPC_FilterValue, 7, 45, 0, // Skip to: 3840 +/* 3795 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3798 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3811 +/* 3802 */ MCD_OPC_CheckField, 11, 5, 0, 21, 24, // Skip to: 9973 +/* 3808 */ MCD_OPC_Decode, 61, 44, // Opcode: ADDME +/* 3811 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3824 +/* 3815 */ MCD_OPC_CheckField, 11, 5, 0, 8, 24, // Skip to: 9973 +/* 3821 */ MCD_OPC_Decode, 64, 44, // Opcode: ADDMEo +/* 3824 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3832 +/* 3828 */ MCD_OPC_Decode, 238, 5, 42, // Opcode: MULLW +/* 3832 */ MCD_OPC_FilterValue, 3, 249, 23, // Skip to: 9973 +/* 3836 */ MCD_OPC_Decode, 239, 5, 42, // Opcode: MULLWo +/* 3840 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 3861 +/* 3844 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3847 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 3854 +/* 3851 */ MCD_OPC_Decode, 22, 42, // Opcode: ADD4 +/* 3854 */ MCD_OPC_FilterValue, 1, 227, 23, // Skip to: 9973 +/* 3858 */ MCD_OPC_Decode, 24, 42, // Opcode: ADD4o +/* 3861 */ MCD_OPC_FilterValue, 14, 19, 0, // Skip to: 3884 +/* 3865 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3868 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3876 +/* 3872 */ MCD_OPC_Decode, 130, 2, 42, // Opcode: DIVWU +/* 3876 */ MCD_OPC_FilterValue, 3, 205, 23, // Skip to: 9973 +/* 3880 */ MCD_OPC_Decode, 131, 2, 42, // Opcode: DIVWUo +/* 3884 */ MCD_OPC_FilterValue, 15, 197, 23, // Skip to: 9973 +/* 3888 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 3891 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 3899 +/* 3895 */ MCD_OPC_Decode, 129, 2, 42, // Opcode: DIVW +/* 3899 */ MCD_OPC_FilterValue, 3, 182, 23, // Skip to: 9973 +/* 3903 */ MCD_OPC_Decode, 132, 2, 42, // Opcode: DIVWo +/* 3907 */ MCD_OPC_FilterValue, 6, 101, 0, // Skip to: 4012 +/* 3911 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3914 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 3928 +/* 3918 */ MCD_OPC_CheckField, 1, 1, 0, 161, 23, // Skip to: 9973 +/* 3924 */ MCD_OPC_Decode, 174, 5, 45, // Opcode: LXVDSX +/* 3928 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 3942 +/* 3932 */ MCD_OPC_CheckField, 1, 1, 0, 147, 23, // Skip to: 9973 +/* 3938 */ MCD_OPC_Decode, 172, 5, 46, // Opcode: LXSDX +/* 3942 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 3956 +/* 3946 */ MCD_OPC_CheckField, 1, 1, 0, 133, 23, // Skip to: 9973 +/* 3952 */ MCD_OPC_Decode, 204, 8, 46, // Opcode: STXSDX +/* 3956 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 3970 +/* 3960 */ MCD_OPC_CheckField, 1, 1, 0, 119, 23, // Skip to: 9973 +/* 3966 */ MCD_OPC_Decode, 175, 5, 45, // Opcode: LXVW4X +/* 3970 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 3984 +/* 3974 */ MCD_OPC_CheckField, 1, 1, 0, 105, 23, // Skip to: 9973 +/* 3980 */ MCD_OPC_Decode, 173, 5, 45, // Opcode: LXVD2X +/* 3984 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 3998 +/* 3988 */ MCD_OPC_CheckField, 1, 1, 0, 91, 23, // Skip to: 9973 +/* 3994 */ MCD_OPC_Decode, 206, 8, 45, // Opcode: STXVW4X +/* 3998 */ MCD_OPC_FilterValue, 30, 83, 23, // Skip to: 9973 +/* 4002 */ MCD_OPC_CheckField, 1, 1, 0, 77, 23, // Skip to: 9973 +/* 4008 */ MCD_OPC_Decode, 205, 8, 45, // Opcode: STXVD2X +/* 4012 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 4026 +/* 4016 */ MCD_OPC_CheckField, 0, 2, 2, 63, 23, // Skip to: 9973 +/* 4022 */ MCD_OPC_Decode, 212, 4, 47, // Opcode: ISEL +/* 4026 */ MCD_OPC_FilterValue, 8, 43, 0, // Skip to: 4073 +/* 4030 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4033 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 4053 +/* 4037 */ MCD_OPC_CheckField, 6, 6, 4, 42, 23, // Skip to: 9973 +/* 4043 */ MCD_OPC_CheckField, 0, 2, 0, 36, 23, // Skip to: 9973 +/* 4049 */ MCD_OPC_Decode, 200, 5, 48, // Opcode: MTCRF +/* 4053 */ MCD_OPC_FilterValue, 1, 28, 23, // Skip to: 9973 +/* 4057 */ MCD_OPC_CheckField, 6, 6, 4, 22, 23, // Skip to: 9973 +/* 4063 */ MCD_OPC_CheckField, 0, 2, 0, 16, 23, // Skip to: 9973 +/* 4069 */ MCD_OPC_Decode, 218, 5, 49, // Opcode: MTOCRF +/* 4073 */ MCD_OPC_FilterValue, 9, 246, 1, // Skip to: 4579 +/* 4077 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4080 */ MCD_OPC_FilterValue, 0, 43, 0, // Skip to: 4127 +/* 4084 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4087 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 4107 +/* 4091 */ MCD_OPC_CheckField, 11, 9, 0, 244, 22, // Skip to: 9973 +/* 4097 */ MCD_OPC_CheckField, 0, 2, 2, 238, 22, // Skip to: 9973 +/* 4103 */ MCD_OPC_Decode, 179, 5, 35, // Opcode: MFCR +/* 4107 */ MCD_OPC_FilterValue, 1, 230, 22, // Skip to: 9973 +/* 4111 */ MCD_OPC_CheckField, 11, 1, 0, 224, 22, // Skip to: 9973 +/* 4117 */ MCD_OPC_CheckField, 0, 2, 2, 218, 22, // Skip to: 9973 +/* 4123 */ MCD_OPC_Decode, 189, 5, 50, // Opcode: MFOCRF +/* 4127 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 4147 +/* 4131 */ MCD_OPC_CheckField, 11, 10, 0, 204, 22, // Skip to: 9973 +/* 4137 */ MCD_OPC_CheckField, 0, 2, 2, 198, 22, // Skip to: 9973 +/* 4143 */ MCD_OPC_Decode, 188, 5, 35, // Opcode: MFMSR +/* 4147 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 4161 +/* 4151 */ MCD_OPC_CheckField, 1, 1, 0, 184, 22, // Skip to: 9973 +/* 4157 */ MCD_OPC_Decode, 216, 5, 51, // Opcode: MTMSR +/* 4161 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 4175 +/* 4165 */ MCD_OPC_CheckField, 1, 1, 0, 170, 22, // Skip to: 9973 +/* 4171 */ MCD_OPC_Decode, 217, 5, 51, // Opcode: MTMSRD +/* 4175 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 4189 +/* 4179 */ MCD_OPC_CheckField, 1, 1, 0, 156, 22, // Skip to: 9973 +/* 4185 */ MCD_OPC_Decode, 221, 5, 52, // Opcode: MTSR +/* 4189 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 4203 +/* 4193 */ MCD_OPC_CheckField, 1, 1, 0, 142, 22, // Skip to: 9973 +/* 4199 */ MCD_OPC_Decode, 222, 5, 53, // Opcode: MTSRIN +/* 4203 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 4223 +/* 4207 */ MCD_OPC_CheckField, 16, 10, 0, 128, 22, // Skip to: 9973 +/* 4213 */ MCD_OPC_CheckField, 0, 2, 0, 122, 22, // Skip to: 9973 +/* 4219 */ MCD_OPC_Decode, 250, 8, 54, // Opcode: TLBIEL +/* 4223 */ MCD_OPC_FilterValue, 9, 16, 0, // Skip to: 4243 +/* 4227 */ MCD_OPC_CheckField, 16, 5, 0, 108, 22, // Skip to: 9973 +/* 4233 */ MCD_OPC_CheckField, 0, 2, 0, 102, 22, // Skip to: 9973 +/* 4239 */ MCD_OPC_Decode, 249, 8, 53, // Opcode: TLBIE +/* 4243 */ MCD_OPC_FilterValue, 10, 32, 0, // Skip to: 4279 +/* 4247 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4250 */ MCD_OPC_FilterValue, 2, 87, 22, // Skip to: 9973 +/* 4254 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... +/* 4257 */ MCD_OPC_FilterValue, 128, 2, 4, 0, // Skip to: 4266 +/* 4262 */ MCD_OPC_Decode, 186, 5, 35, // Opcode: MFLR +/* 4266 */ MCD_OPC_FilterValue, 160, 2, 4, 0, // Skip to: 4275 +/* 4271 */ MCD_OPC_Decode, 181, 5, 35, // Opcode: MFCTR +/* 4275 */ MCD_OPC_Decode, 191, 5, 37, // Opcode: MFSPR +/* 4279 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 4308 +/* 4283 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4286 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 4300 +/* 4290 */ MCD_OPC_CheckField, 11, 15, 0, 45, 22, // Skip to: 9973 +/* 4296 */ MCD_OPC_Decode, 248, 8, 0, // Opcode: TLBIA +/* 4300 */ MCD_OPC_FilterValue, 2, 37, 22, // Skip to: 9973 +/* 4304 */ MCD_OPC_Decode, 194, 5, 37, // Opcode: MFTB +/* 4308 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 4328 +/* 4312 */ MCD_OPC_CheckField, 16, 5, 0, 23, 22, // Skip to: 9973 +/* 4318 */ MCD_OPC_CheckField, 0, 2, 0, 17, 22, // Skip to: 9973 +/* 4324 */ MCD_OPC_Decode, 247, 7, 53, // Opcode: SLBMTE +/* 4328 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 4348 +/* 4332 */ MCD_OPC_CheckField, 16, 10, 0, 3, 22, // Skip to: 9973 +/* 4338 */ MCD_OPC_CheckField, 0, 2, 0, 253, 21, // Skip to: 9973 +/* 4344 */ MCD_OPC_Decode, 245, 7, 54, // Opcode: SLBIE +/* 4348 */ MCD_OPC_FilterValue, 14, 32, 0, // Skip to: 4384 +/* 4352 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4355 */ MCD_OPC_FilterValue, 2, 238, 21, // Skip to: 9973 +/* 4359 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... +/* 4362 */ MCD_OPC_FilterValue, 128, 2, 4, 0, // Skip to: 4371 +/* 4367 */ MCD_OPC_Decode, 214, 5, 35, // Opcode: MTLR +/* 4371 */ MCD_OPC_FilterValue, 160, 2, 4, 0, // Skip to: 4380 +/* 4376 */ MCD_OPC_Decode, 202, 5, 35, // Opcode: MTCTR +/* 4380 */ MCD_OPC_Decode, 220, 5, 55, // Opcode: MTSPR +/* 4384 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 4404 +/* 4388 */ MCD_OPC_CheckField, 11, 15, 0, 203, 21, // Skip to: 9973 +/* 4394 */ MCD_OPC_CheckField, 0, 2, 0, 197, 21, // Skip to: 9973 +/* 4400 */ MCD_OPC_Decode, 244, 7, 0, // Opcode: SLBIA +/* 4404 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 4418 +/* 4408 */ MCD_OPC_CheckField, 1, 1, 1, 183, 21, // Skip to: 9973 +/* 4414 */ MCD_OPC_Decode, 192, 5, 52, // Opcode: MFSR +/* 4418 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 4432 +/* 4422 */ MCD_OPC_CheckField, 1, 1, 1, 169, 21, // Skip to: 9973 +/* 4428 */ MCD_OPC_Decode, 193, 5, 53, // Opcode: MFSRIN +/* 4432 */ MCD_OPC_FilterValue, 24, 16, 0, // Skip to: 4452 +/* 4436 */ MCD_OPC_CheckField, 21, 5, 0, 155, 21, // Skip to: 9973 +/* 4442 */ MCD_OPC_CheckField, 0, 2, 0, 149, 21, // Skip to: 9973 +/* 4448 */ MCD_OPC_Decode, 251, 8, 41, // Opcode: TLBIVAX +/* 4452 */ MCD_OPC_FilterValue, 28, 43, 0, // Skip to: 4499 +/* 4456 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4459 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4477 +/* 4463 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 4473 +/* 4469 */ MCD_OPC_Decode, 128, 9, 41, // Opcode: TLBSX +/* 4473 */ MCD_OPC_Decode, 129, 9, 42, // Opcode: TLBSX2 +/* 4477 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 4485 +/* 4481 */ MCD_OPC_Decode, 130, 9, 42, // Opcode: TLBSX2D +/* 4485 */ MCD_OPC_FilterValue, 2, 108, 21, // Skip to: 9973 +/* 4489 */ MCD_OPC_CheckField, 16, 5, 0, 102, 21, // Skip to: 9973 +/* 4495 */ MCD_OPC_Decode, 246, 7, 53, // Opcode: SLBMFEE +/* 4499 */ MCD_OPC_FilterValue, 29, 21, 0, // Skip to: 4524 +/* 4503 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4506 */ MCD_OPC_FilterValue, 0, 87, 21, // Skip to: 9973 +/* 4510 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, // Skip to: 4520 +/* 4516 */ MCD_OPC_Decode, 254, 8, 0, // Opcode: TLBRE +/* 4520 */ MCD_OPC_Decode, 255, 8, 56, // Opcode: TLBRE2 +/* 4524 */ MCD_OPC_FilterValue, 30, 31, 0, // Skip to: 4559 +/* 4528 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4531 */ MCD_OPC_FilterValue, 0, 62, 21, // Skip to: 9973 +/* 4535 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, // Skip to: 4545 +/* 4541 */ MCD_OPC_Decode, 132, 9, 0, // Opcode: TLBWE +/* 4545 */ MCD_OPC_CheckField, 16, 10, 0, 4, 0, // Skip to: 4555 +/* 4551 */ MCD_OPC_Decode, 252, 8, 54, // Opcode: TLBLD +/* 4555 */ MCD_OPC_Decode, 133, 9, 56, // Opcode: TLBWE2 +/* 4559 */ MCD_OPC_FilterValue, 31, 34, 21, // Skip to: 9973 +/* 4563 */ MCD_OPC_CheckField, 16, 10, 0, 28, 21, // Skip to: 9973 +/* 4569 */ MCD_OPC_CheckField, 0, 2, 0, 22, 21, // Skip to: 9973 +/* 4575 */ MCD_OPC_Decode, 253, 8, 54, // Opcode: TLBLI +/* 4579 */ MCD_OPC_FilterValue, 10, 22, 1, // Skip to: 4861 +/* 4583 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4586 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 4609 +/* 4590 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4593 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 4601 +/* 4597 */ MCD_OPC_Decode, 155, 5, 57, // Opcode: LWARX +/* 4601 */ MCD_OPC_FilterValue, 2, 248, 20, // Skip to: 9973 +/* 4605 */ MCD_OPC_Decode, 232, 4, 58, // Opcode: LDX +/* 4609 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 4623 +/* 4613 */ MCD_OPC_CheckField, 0, 2, 2, 234, 20, // Skip to: 9973 +/* 4619 */ MCD_OPC_Decode, 231, 4, 59, // Opcode: LDUX +/* 4623 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 4637 +/* 4627 */ MCD_OPC_CheckField, 0, 2, 0, 220, 20, // Skip to: 9973 +/* 4633 */ MCD_OPC_Decode, 227, 4, 58, // Opcode: LDARX +/* 4637 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 4651 +/* 4641 */ MCD_OPC_CheckField, 0, 2, 2, 206, 20, // Skip to: 9973 +/* 4647 */ MCD_OPC_Decode, 166, 8, 58, // Opcode: STDX +/* 4651 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 4665 +/* 4655 */ MCD_OPC_CheckField, 0, 2, 2, 192, 20, // Skip to: 9973 +/* 4661 */ MCD_OPC_Decode, 165, 8, 60, // Opcode: STDUX +/* 4665 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 4679 +/* 4669 */ MCD_OPC_CheckField, 0, 2, 2, 178, 20, // Skip to: 9973 +/* 4675 */ MCD_OPC_Decode, 157, 5, 58, // Opcode: LWAX +/* 4679 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 4693 +/* 4683 */ MCD_OPC_CheckField, 0, 2, 2, 164, 20, // Skip to: 9973 +/* 4689 */ MCD_OPC_Decode, 156, 5, 59, // Opcode: LWAUX +/* 4693 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 4707 +/* 4697 */ MCD_OPC_CheckField, 0, 2, 0, 150, 20, // Skip to: 9973 +/* 4703 */ MCD_OPC_Decode, 228, 4, 58, // Opcode: LDBRX +/* 4707 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 4721 +/* 4711 */ MCD_OPC_CheckField, 0, 2, 2, 136, 20, // Skip to: 9973 +/* 4717 */ MCD_OPC_Decode, 146, 5, 61, // Opcode: LSWI +/* 4721 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 4735 +/* 4725 */ MCD_OPC_CheckField, 0, 2, 0, 122, 20, // Skip to: 9973 +/* 4731 */ MCD_OPC_Decode, 161, 8, 58, // Opcode: STDBRX +/* 4735 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 4749 +/* 4739 */ MCD_OPC_CheckField, 0, 2, 2, 108, 20, // Skip to: 9973 +/* 4745 */ MCD_OPC_Decode, 187, 8, 61, // Opcode: STSWI +/* 4749 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 4763 +/* 4753 */ MCD_OPC_CheckField, 0, 2, 2, 94, 20, // Skip to: 9973 +/* 4759 */ MCD_OPC_Decode, 164, 5, 42, // Opcode: LWZCIX +/* 4763 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 4777 +/* 4767 */ MCD_OPC_CheckField, 0, 2, 2, 80, 20, // Skip to: 9973 +/* 4773 */ MCD_OPC_Decode, 134, 5, 42, // Opcode: LHZCIX +/* 4777 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 4791 +/* 4781 */ MCD_OPC_CheckField, 0, 2, 2, 66, 20, // Skip to: 9973 +/* 4787 */ MCD_OPC_Decode, 219, 4, 42, // Opcode: LBZCIX +/* 4791 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 4805 +/* 4795 */ MCD_OPC_CheckField, 0, 2, 2, 52, 20, // Skip to: 9973 +/* 4801 */ MCD_OPC_Decode, 229, 4, 42, // Opcode: LDCIX +/* 4805 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 4819 +/* 4809 */ MCD_OPC_CheckField, 0, 2, 2, 38, 20, // Skip to: 9973 +/* 4815 */ MCD_OPC_Decode, 196, 8, 42, // Opcode: STWCIX +/* 4819 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 4833 +/* 4823 */ MCD_OPC_CheckField, 0, 2, 2, 24, 20, // Skip to: 9973 +/* 4829 */ MCD_OPC_Decode, 179, 8, 42, // Opcode: STHCIX +/* 4833 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 4847 +/* 4837 */ MCD_OPC_CheckField, 0, 2, 2, 10, 20, // Skip to: 9973 +/* 4843 */ MCD_OPC_Decode, 153, 8, 42, // Opcode: STBCIX +/* 4847 */ MCD_OPC_FilterValue, 31, 2, 20, // Skip to: 9973 +/* 4851 */ MCD_OPC_CheckField, 0, 2, 2, 252, 19, // Skip to: 9973 +/* 4857 */ MCD_OPC_Decode, 162, 8, 42, // Opcode: STDCIX +/* 4861 */ MCD_OPC_FilterValue, 11, 227, 2, // Skip to: 5604 +/* 4865 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4868 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 4897 +/* 4872 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4875 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 4889 +/* 4879 */ MCD_OPC_CheckField, 25, 1, 0, 224, 19, // Skip to: 9973 +/* 4885 */ MCD_OPC_Decode, 204, 4, 62, // Opcode: ICBT +/* 4889 */ MCD_OPC_FilterValue, 2, 216, 19, // Skip to: 9973 +/* 4893 */ MCD_OPC_Decode, 169, 5, 57, // Opcode: LWZX +/* 4897 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 4926 +/* 4901 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4904 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 4918 +/* 4908 */ MCD_OPC_CheckField, 21, 5, 0, 195, 19, // Skip to: 9973 +/* 4914 */ MCD_OPC_Decode, 247, 1, 63, // Opcode: DCBST +/* 4918 */ MCD_OPC_FilterValue, 2, 187, 19, // Skip to: 9973 +/* 4922 */ MCD_OPC_Decode, 167, 5, 64, // Opcode: LWZUX +/* 4926 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 4955 +/* 4930 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4933 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 4947 +/* 4937 */ MCD_OPC_CheckField, 21, 5, 0, 166, 19, // Skip to: 9973 +/* 4943 */ MCD_OPC_Decode, 245, 1, 63, // Opcode: DCBF +/* 4947 */ MCD_OPC_FilterValue, 2, 158, 19, // Skip to: 9973 +/* 4951 */ MCD_OPC_Decode, 224, 4, 57, // Opcode: LBZX +/* 4955 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 4969 +/* 4959 */ MCD_OPC_CheckField, 0, 2, 2, 144, 19, // Skip to: 9973 +/* 4965 */ MCD_OPC_Decode, 222, 4, 64, // Opcode: LBZUX +/* 4969 */ MCD_OPC_FilterValue, 4, 19, 0, // Skip to: 4992 +/* 4973 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 4976 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 4984 +/* 4980 */ MCD_OPC_Decode, 197, 8, 57, // Opcode: STWCX +/* 4984 */ MCD_OPC_FilterValue, 2, 121, 19, // Skip to: 9973 +/* 4988 */ MCD_OPC_Decode, 202, 8, 57, // Opcode: STWX +/* 4992 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 5006 +/* 4996 */ MCD_OPC_CheckField, 0, 2, 2, 107, 19, // Skip to: 9973 +/* 5002 */ MCD_OPC_Decode, 200, 8, 65, // Opcode: STWUX +/* 5006 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 5029 +/* 5010 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5013 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 5021 +/* 5017 */ MCD_OPC_Decode, 163, 8, 58, // Opcode: STDCX +/* 5021 */ MCD_OPC_FilterValue, 2, 84, 19, // Skip to: 9973 +/* 5025 */ MCD_OPC_Decode, 158, 8, 57, // Opcode: STBX +/* 5029 */ MCD_OPC_FilterValue, 7, 25, 0, // Skip to: 5058 +/* 5033 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5036 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5050 +/* 5040 */ MCD_OPC_CheckField, 21, 5, 0, 63, 19, // Skip to: 9973 +/* 5046 */ MCD_OPC_Decode, 249, 1, 63, // Opcode: DCBTST +/* 5050 */ MCD_OPC_FilterValue, 2, 55, 19, // Skip to: 9973 +/* 5054 */ MCD_OPC_Decode, 156, 8, 65, // Opcode: STBUX +/* 5058 */ MCD_OPC_FilterValue, 8, 25, 0, // Skip to: 5087 +/* 5062 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5065 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5079 +/* 5069 */ MCD_OPC_CheckField, 21, 5, 0, 34, 19, // Skip to: 9973 +/* 5075 */ MCD_OPC_Decode, 248, 1, 63, // Opcode: DCBT +/* 5079 */ MCD_OPC_FilterValue, 2, 26, 19, // Skip to: 9973 +/* 5083 */ MCD_OPC_Decode, 139, 5, 57, // Opcode: LHZX +/* 5087 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 5101 +/* 5091 */ MCD_OPC_CheckField, 0, 2, 2, 12, 19, // Skip to: 9973 +/* 5097 */ MCD_OPC_Decode, 137, 5, 64, // Opcode: LHZUX +/* 5101 */ MCD_OPC_FilterValue, 10, 34, 0, // Skip to: 5139 +/* 5105 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5108 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 5131 +/* 5112 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 5115 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5123 +/* 5119 */ MCD_OPC_Decode, 135, 2, 66, // Opcode: DST +/* 5123 */ MCD_OPC_FilterValue, 4, 238, 18, // Skip to: 9973 +/* 5127 */ MCD_OPC_Decode, 141, 2, 66, // Opcode: DSTT +/* 5131 */ MCD_OPC_FilterValue, 2, 230, 18, // Skip to: 9973 +/* 5135 */ MCD_OPC_Decode, 128, 5, 57, // Opcode: LHAX +/* 5139 */ MCD_OPC_FilterValue, 11, 34, 0, // Skip to: 5177 +/* 5143 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5146 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 5169 +/* 5150 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 5153 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5161 +/* 5157 */ MCD_OPC_Decode, 137, 2, 66, // Opcode: DSTST +/* 5161 */ MCD_OPC_FilterValue, 4, 200, 18, // Skip to: 9973 +/* 5165 */ MCD_OPC_Decode, 139, 2, 66, // Opcode: DSTSTT +/* 5169 */ MCD_OPC_FilterValue, 2, 192, 18, // Skip to: 9973 +/* 5173 */ MCD_OPC_Decode, 254, 4, 64, // Opcode: LHAUX +/* 5177 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 5191 +/* 5181 */ MCD_OPC_CheckField, 0, 2, 2, 178, 18, // Skip to: 9973 +/* 5187 */ MCD_OPC_Decode, 184, 8, 57, // Opcode: STHX +/* 5191 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 5205 +/* 5195 */ MCD_OPC_CheckField, 0, 2, 2, 164, 18, // Skip to: 9973 +/* 5201 */ MCD_OPC_Decode, 182, 8, 65, // Opcode: STHUX +/* 5205 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 5225 +/* 5209 */ MCD_OPC_CheckField, 21, 5, 0, 150, 18, // Skip to: 9973 +/* 5215 */ MCD_OPC_CheckField, 0, 2, 0, 144, 18, // Skip to: 9973 +/* 5221 */ MCD_OPC_Decode, 246, 1, 63, // Opcode: DCBI +/* 5225 */ MCD_OPC_FilterValue, 16, 19, 0, // Skip to: 5248 +/* 5229 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5232 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5240 +/* 5236 */ MCD_OPC_Decode, 160, 5, 57, // Opcode: LWBRX +/* 5240 */ MCD_OPC_FilterValue, 2, 121, 18, // Skip to: 9973 +/* 5244 */ MCD_OPC_Decode, 249, 4, 67, // Opcode: LFSX +/* 5248 */ MCD_OPC_FilterValue, 17, 25, 0, // Skip to: 5277 +/* 5252 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5255 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5269 +/* 5259 */ MCD_OPC_CheckField, 11, 15, 0, 100, 18, // Skip to: 9973 +/* 5265 */ MCD_OPC_Decode, 131, 9, 0, // Opcode: TLBSYNC +/* 5269 */ MCD_OPC_FilterValue, 2, 92, 18, // Skip to: 9973 +/* 5273 */ MCD_OPC_Decode, 248, 4, 68, // Opcode: LFSUX +/* 5277 */ MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 5312 +/* 5281 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5284 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5304 +/* 5288 */ MCD_OPC_CheckField, 23, 3, 0, 71, 18, // Skip to: 9973 +/* 5294 */ MCD_OPC_CheckField, 11, 10, 0, 65, 18, // Skip to: 9973 +/* 5300 */ MCD_OPC_Decode, 233, 8, 69, // Opcode: SYNC +/* 5304 */ MCD_OPC_FilterValue, 2, 57, 18, // Skip to: 9973 +/* 5308 */ MCD_OPC_Decode, 243, 4, 70, // Opcode: LFDX +/* 5312 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 5326 +/* 5316 */ MCD_OPC_CheckField, 0, 2, 2, 43, 18, // Skip to: 9973 +/* 5322 */ MCD_OPC_Decode, 242, 4, 71, // Opcode: LFDUX +/* 5326 */ MCD_OPC_FilterValue, 20, 19, 0, // Skip to: 5349 +/* 5330 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5333 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5341 +/* 5337 */ MCD_OPC_Decode, 195, 8, 57, // Opcode: STWBRX +/* 5341 */ MCD_OPC_FilterValue, 2, 20, 18, // Skip to: 9973 +/* 5345 */ MCD_OPC_Decode, 175, 8, 67, // Opcode: STFSX +/* 5349 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 5363 +/* 5353 */ MCD_OPC_CheckField, 0, 2, 2, 6, 18, // Skip to: 9973 +/* 5359 */ MCD_OPC_Decode, 174, 8, 72, // Opcode: STFSUX +/* 5363 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 5377 +/* 5367 */ MCD_OPC_CheckField, 0, 2, 2, 248, 17, // Skip to: 9973 +/* 5373 */ MCD_OPC_Decode, 170, 8, 70, // Opcode: STFDX +/* 5377 */ MCD_OPC_FilterValue, 23, 25, 0, // Skip to: 5406 +/* 5381 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5384 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5398 +/* 5388 */ MCD_OPC_CheckField, 21, 5, 0, 227, 17, // Skip to: 9973 +/* 5394 */ MCD_OPC_Decode, 244, 1, 63, // Opcode: DCBA +/* 5398 */ MCD_OPC_FilterValue, 2, 219, 17, // Skip to: 9973 +/* 5402 */ MCD_OPC_Decode, 169, 8, 73, // Opcode: STFDUX +/* 5406 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 5420 +/* 5410 */ MCD_OPC_CheckField, 0, 2, 0, 205, 17, // Skip to: 9973 +/* 5416 */ MCD_OPC_Decode, 130, 5, 57, // Opcode: LHBRX +/* 5420 */ MCD_OPC_FilterValue, 25, 43, 0, // Skip to: 5467 +/* 5424 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 5427 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5447 +/* 5431 */ MCD_OPC_CheckField, 11, 10, 0, 184, 17, // Skip to: 9973 +/* 5437 */ MCD_OPC_CheckField, 0, 2, 0, 178, 17, // Skip to: 9973 +/* 5443 */ MCD_OPC_Decode, 133, 2, 74, // Opcode: DSS +/* 5447 */ MCD_OPC_FilterValue, 4, 170, 17, // Skip to: 9973 +/* 5451 */ MCD_OPC_CheckField, 11, 12, 0, 164, 17, // Skip to: 9973 +/* 5457 */ MCD_OPC_CheckField, 0, 2, 0, 158, 17, // Skip to: 9973 +/* 5463 */ MCD_OPC_Decode, 134, 2, 0, // Opcode: DSSALL +/* 5467 */ MCD_OPC_FilterValue, 26, 41, 0, // Skip to: 5512 +/* 5471 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 5474 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5498 +/* 5478 */ MCD_OPC_CheckField, 11, 15, 0, 10, 0, // Skip to: 5494 +/* 5484 */ MCD_OPC_CheckField, 0, 1, 0, 4, 0, // Skip to: 5494 +/* 5490 */ MCD_OPC_Decode, 219, 3, 0, // Opcode: EnforceIEIO +/* 5494 */ MCD_OPC_Decode, 176, 5, 75, // Opcode: MBAR +/* 5498 */ MCD_OPC_FilterValue, 1, 119, 17, // Skip to: 9973 +/* 5502 */ MCD_OPC_CheckField, 0, 1, 0, 113, 17, // Skip to: 9973 +/* 5508 */ MCD_OPC_Decode, 244, 4, 70, // Opcode: LFIWAX +/* 5512 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 5526 +/* 5516 */ MCD_OPC_CheckField, 0, 2, 2, 99, 17, // Skip to: 9973 +/* 5522 */ MCD_OPC_Decode, 245, 4, 70, // Opcode: LFIWZX +/* 5526 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 5540 +/* 5530 */ MCD_OPC_CheckField, 0, 2, 0, 85, 17, // Skip to: 9973 +/* 5536 */ MCD_OPC_Decode, 178, 8, 57, // Opcode: STHBRX +/* 5540 */ MCD_OPC_FilterValue, 30, 25, 0, // Skip to: 5569 +/* 5544 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5547 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5561 +/* 5551 */ MCD_OPC_CheckField, 21, 5, 0, 64, 17, // Skip to: 9973 +/* 5557 */ MCD_OPC_Decode, 203, 4, 63, // Opcode: ICBI +/* 5561 */ MCD_OPC_FilterValue, 2, 56, 17, // Skip to: 9973 +/* 5565 */ MCD_OPC_Decode, 171, 8, 70, // Opcode: STFIWX +/* 5569 */ MCD_OPC_FilterValue, 31, 48, 17, // Skip to: 9973 +/* 5573 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 5576 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5590 +/* 5580 */ MCD_OPC_CheckField, 0, 2, 0, 35, 17, // Skip to: 9973 +/* 5586 */ MCD_OPC_Decode, 250, 1, 63, // Opcode: DCBZ +/* 5590 */ MCD_OPC_FilterValue, 1, 27, 17, // Skip to: 9973 +/* 5594 */ MCD_OPC_CheckField, 0, 2, 0, 21, 17, // Skip to: 9973 +/* 5600 */ MCD_OPC_Decode, 251, 1, 63, // Opcode: DCBZL +/* 5604 */ MCD_OPC_FilterValue, 12, 95, 0, // Skip to: 5703 +/* 5608 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 5611 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 5634 +/* 5615 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5618 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5626 +/* 5622 */ MCD_OPC_Decode, 252, 7, 76, // Opcode: SLW +/* 5626 */ MCD_OPC_FilterValue, 1, 247, 16, // Skip to: 9973 +/* 5630 */ MCD_OPC_Decode, 129, 8, 76, // Opcode: SLWo +/* 5634 */ MCD_OPC_FilterValue, 16, 19, 0, // Skip to: 5657 +/* 5638 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5641 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5649 +/* 5645 */ MCD_OPC_Decode, 145, 8, 76, // Opcode: SRW +/* 5649 */ MCD_OPC_FilterValue, 1, 224, 16, // Skip to: 9973 +/* 5653 */ MCD_OPC_Decode, 150, 8, 76, // Opcode: SRWo +/* 5657 */ MCD_OPC_FilterValue, 24, 19, 0, // Skip to: 5680 +/* 5661 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5664 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5672 +/* 5668 */ MCD_OPC_Decode, 137, 8, 76, // Opcode: SRAW +/* 5672 */ MCD_OPC_FilterValue, 1, 201, 16, // Skip to: 9973 +/* 5676 */ MCD_OPC_Decode, 140, 8, 76, // Opcode: SRAWo +/* 5680 */ MCD_OPC_FilterValue, 25, 193, 16, // Skip to: 9973 +/* 5684 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5687 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5695 +/* 5691 */ MCD_OPC_Decode, 138, 8, 77, // Opcode: SRAWI +/* 5695 */ MCD_OPC_FilterValue, 1, 178, 16, // Skip to: 9973 +/* 5699 */ MCD_OPC_Decode, 139, 8, 77, // Opcode: SRAWIo +/* 5703 */ MCD_OPC_FilterValue, 13, 47, 1, // Skip to: 6010 +/* 5707 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 5710 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 5761 +/* 5714 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5717 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5731 +/* 5721 */ MCD_OPC_CheckField, 11, 5, 0, 150, 16, // Skip to: 9973 +/* 5727 */ MCD_OPC_Decode, 228, 1, 78, // Opcode: CNTLZW +/* 5731 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 5745 +/* 5735 */ MCD_OPC_CheckField, 11, 5, 0, 136, 16, // Skip to: 9973 +/* 5741 */ MCD_OPC_Decode, 231, 1, 78, // Opcode: CNTLZWo +/* 5745 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 5753 +/* 5749 */ MCD_OPC_Decode, 248, 7, 79, // Opcode: SLD +/* 5753 */ MCD_OPC_FilterValue, 3, 120, 16, // Skip to: 9973 +/* 5757 */ MCD_OPC_Decode, 251, 7, 79, // Opcode: SLDo +/* 5761 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 5796 +/* 5765 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5768 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5782 +/* 5772 */ MCD_OPC_CheckField, 11, 5, 0, 99, 16, // Skip to: 9973 +/* 5778 */ MCD_OPC_Decode, 226, 1, 80, // Opcode: CNTLZD +/* 5782 */ MCD_OPC_FilterValue, 1, 91, 16, // Skip to: 9973 +/* 5786 */ MCD_OPC_CheckField, 11, 5, 0, 85, 16, // Skip to: 9973 +/* 5792 */ MCD_OPC_Decode, 227, 1, 80, // Opcode: CNTLZDo +/* 5796 */ MCD_OPC_FilterValue, 11, 16, 0, // Skip to: 5816 +/* 5800 */ MCD_OPC_CheckField, 11, 5, 0, 71, 16, // Skip to: 9973 +/* 5806 */ MCD_OPC_CheckField, 0, 2, 0, 65, 16, // Skip to: 9973 +/* 5812 */ MCD_OPC_Decode, 143, 6, 78, // Opcode: POPCNTW +/* 5816 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 5836 +/* 5820 */ MCD_OPC_CheckField, 11, 5, 0, 51, 16, // Skip to: 9973 +/* 5826 */ MCD_OPC_CheckField, 0, 2, 0, 45, 16, // Skip to: 9973 +/* 5832 */ MCD_OPC_Decode, 142, 6, 80, // Opcode: POPCNTD +/* 5836 */ MCD_OPC_FilterValue, 16, 19, 0, // Skip to: 5859 +/* 5840 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5843 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 5851 +/* 5847 */ MCD_OPC_Decode, 141, 8, 79, // Opcode: SRD +/* 5851 */ MCD_OPC_FilterValue, 3, 22, 16, // Skip to: 9973 +/* 5855 */ MCD_OPC_Decode, 144, 8, 79, // Opcode: SRDo +/* 5859 */ MCD_OPC_FilterValue, 24, 19, 0, // Skip to: 5882 +/* 5863 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5866 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5874 +/* 5870 */ MCD_OPC_Decode, 133, 8, 79, // Opcode: SRAD +/* 5874 */ MCD_OPC_FilterValue, 1, 255, 15, // Skip to: 9973 +/* 5878 */ MCD_OPC_Decode, 136, 8, 79, // Opcode: SRADo +/* 5882 */ MCD_OPC_FilterValue, 25, 19, 0, // Skip to: 5905 +/* 5886 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5889 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5897 +/* 5893 */ MCD_OPC_Decode, 134, 8, 81, // Opcode: SRADI +/* 5897 */ MCD_OPC_FilterValue, 1, 232, 15, // Skip to: 9973 +/* 5901 */ MCD_OPC_Decode, 135, 8, 81, // Opcode: SRADIo +/* 5905 */ MCD_OPC_FilterValue, 28, 31, 0, // Skip to: 5940 +/* 5909 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5912 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5926 +/* 5916 */ MCD_OPC_CheckField, 11, 5, 0, 211, 15, // Skip to: 9973 +/* 5922 */ MCD_OPC_Decode, 210, 3, 78, // Opcode: EXTSH +/* 5926 */ MCD_OPC_FilterValue, 1, 203, 15, // Skip to: 9973 +/* 5930 */ MCD_OPC_CheckField, 11, 5, 0, 197, 15, // Skip to: 9973 +/* 5936 */ MCD_OPC_Decode, 214, 3, 78, // Opcode: EXTSHo +/* 5940 */ MCD_OPC_FilterValue, 29, 31, 0, // Skip to: 5975 +/* 5944 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5947 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5961 +/* 5951 */ MCD_OPC_CheckField, 11, 5, 0, 176, 15, // Skip to: 9973 +/* 5957 */ MCD_OPC_Decode, 205, 3, 78, // Opcode: EXTSB +/* 5961 */ MCD_OPC_FilterValue, 1, 168, 15, // Skip to: 9973 +/* 5965 */ MCD_OPC_CheckField, 11, 5, 0, 162, 15, // Skip to: 9973 +/* 5971 */ MCD_OPC_Decode, 209, 3, 78, // Opcode: EXTSBo +/* 5975 */ MCD_OPC_FilterValue, 30, 154, 15, // Skip to: 9973 +/* 5979 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 5982 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5996 +/* 5986 */ MCD_OPC_CheckField, 11, 5, 0, 141, 15, // Skip to: 9973 +/* 5992 */ MCD_OPC_Decode, 215, 3, 80, // Opcode: EXTSW +/* 5996 */ MCD_OPC_FilterValue, 1, 133, 15, // Skip to: 9973 +/* 6000 */ MCD_OPC_CheckField, 11, 5, 0, 127, 15, // Skip to: 9973 +/* 6006 */ MCD_OPC_Decode, 218, 3, 80, // Opcode: EXTSWo +/* 6010 */ MCD_OPC_FilterValue, 14, 197, 0, // Skip to: 6211 +/* 6014 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6017 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 6038 +/* 6021 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6024 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 6031 +/* 6028 */ MCD_OPC_Decode, 71, 76, // Opcode: AND +/* 6031 */ MCD_OPC_FilterValue, 1, 98, 15, // Skip to: 9973 +/* 6035 */ MCD_OPC_Decode, 86, 76, // Opcode: ANDo +/* 6038 */ MCD_OPC_FilterValue, 1, 17, 0, // Skip to: 6059 +/* 6042 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6045 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 6052 +/* 6049 */ MCD_OPC_Decode, 74, 76, // Opcode: ANDC +/* 6052 */ MCD_OPC_FilterValue, 1, 77, 15, // Skip to: 9973 +/* 6056 */ MCD_OPC_Decode, 77, 76, // Opcode: ANDCo +/* 6059 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 6082 +/* 6063 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6066 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6074 +/* 6070 */ MCD_OPC_Decode, 254, 5, 76, // Opcode: NOR +/* 6074 */ MCD_OPC_FilterValue, 1, 55, 15, // Skip to: 9973 +/* 6078 */ MCD_OPC_Decode, 129, 6, 76, // Opcode: NORo +/* 6082 */ MCD_OPC_FilterValue, 8, 19, 0, // Skip to: 6105 +/* 6086 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6089 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6097 +/* 6093 */ MCD_OPC_Decode, 150, 2, 76, // Opcode: EQV +/* 6097 */ MCD_OPC_FilterValue, 1, 32, 15, // Skip to: 9973 +/* 6101 */ MCD_OPC_Decode, 153, 2, 76, // Opcode: EQVo +/* 6105 */ MCD_OPC_FilterValue, 9, 19, 0, // Skip to: 6128 +/* 6109 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6112 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6120 +/* 6116 */ MCD_OPC_Decode, 211, 10, 76, // Opcode: XOR +/* 6120 */ MCD_OPC_FilterValue, 1, 9, 15, // Skip to: 9973 +/* 6124 */ MCD_OPC_Decode, 218, 10, 76, // Opcode: XORo +/* 6128 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 6151 +/* 6132 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6135 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6143 +/* 6139 */ MCD_OPC_Decode, 133, 6, 76, // Opcode: ORC +/* 6143 */ MCD_OPC_FilterValue, 1, 242, 14, // Skip to: 9973 +/* 6147 */ MCD_OPC_Decode, 136, 6, 76, // Opcode: ORCo +/* 6151 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 6174 +/* 6155 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6158 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6166 +/* 6162 */ MCD_OPC_Decode, 130, 6, 76, // Opcode: OR +/* 6166 */ MCD_OPC_FilterValue, 1, 219, 14, // Skip to: 9973 +/* 6170 */ MCD_OPC_Decode, 141, 6, 76, // Opcode: ORo +/* 6174 */ MCD_OPC_FilterValue, 14, 19, 0, // Skip to: 6197 +/* 6178 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6181 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6189 +/* 6185 */ MCD_OPC_Decode, 243, 5, 76, // Opcode: NAND +/* 6189 */ MCD_OPC_FilterValue, 1, 196, 14, // Skip to: 9973 +/* 6193 */ MCD_OPC_Decode, 246, 5, 76, // Opcode: NANDo +/* 6197 */ MCD_OPC_FilterValue, 15, 188, 14, // Skip to: 9973 +/* 6201 */ MCD_OPC_CheckField, 0, 2, 0, 182, 14, // Skip to: 9973 +/* 6207 */ MCD_OPC_Decode, 216, 1, 76, // Opcode: CMPB +/* 6211 */ MCD_OPC_FilterValue, 15, 174, 14, // Skip to: 9973 +/* 6215 */ MCD_OPC_CheckField, 23, 3, 0, 168, 14, // Skip to: 9973 +/* 6221 */ MCD_OPC_CheckField, 6, 15, 1, 162, 14, // Skip to: 9973 +/* 6227 */ MCD_OPC_CheckField, 0, 2, 0, 156, 14, // Skip to: 9973 +/* 6233 */ MCD_OPC_Decode, 208, 10, 69, // Opcode: WAIT +/* 6237 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 6245 +/* 6241 */ MCD_OPC_Decode, 162, 5, 82, // Opcode: LWZ +/* 6245 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 6253 +/* 6249 */ MCD_OPC_Decode, 165, 5, 82, // Opcode: LWZU +/* 6253 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 6261 +/* 6257 */ MCD_OPC_Decode, 217, 4, 82, // Opcode: LBZ +/* 6261 */ MCD_OPC_FilterValue, 35, 4, 0, // Skip to: 6269 +/* 6265 */ MCD_OPC_Decode, 220, 4, 82, // Opcode: LBZU +/* 6269 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 6277 +/* 6273 */ MCD_OPC_Decode, 193, 8, 82, // Opcode: STW +/* 6277 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 6285 +/* 6281 */ MCD_OPC_Decode, 198, 8, 82, // Opcode: STWU +/* 6285 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 6293 +/* 6289 */ MCD_OPC_Decode, 151, 8, 82, // Opcode: STB +/* 6293 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 6301 +/* 6297 */ MCD_OPC_Decode, 154, 8, 82, // Opcode: STBU +/* 6301 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 6309 +/* 6305 */ MCD_OPC_Decode, 132, 5, 82, // Opcode: LHZ +/* 6309 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 6317 +/* 6313 */ MCD_OPC_Decode, 135, 5, 82, // Opcode: LHZU +/* 6317 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 6325 +/* 6321 */ MCD_OPC_Decode, 250, 4, 82, // Opcode: LHA +/* 6325 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 6333 +/* 6329 */ MCD_OPC_Decode, 252, 4, 82, // Opcode: LHAU +/* 6333 */ MCD_OPC_FilterValue, 44, 4, 0, // Skip to: 6341 +/* 6337 */ MCD_OPC_Decode, 176, 8, 82, // Opcode: STH +/* 6341 */ MCD_OPC_FilterValue, 45, 4, 0, // Skip to: 6349 +/* 6345 */ MCD_OPC_Decode, 180, 8, 82, // Opcode: STHU +/* 6349 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 6357 +/* 6353 */ MCD_OPC_Decode, 145, 5, 82, // Opcode: LMW +/* 6357 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 6365 +/* 6361 */ MCD_OPC_Decode, 186, 8, 82, // Opcode: STMW +/* 6365 */ MCD_OPC_FilterValue, 48, 4, 0, // Skip to: 6373 +/* 6369 */ MCD_OPC_Decode, 246, 4, 83, // Opcode: LFS +/* 6373 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 6381 +/* 6377 */ MCD_OPC_Decode, 247, 4, 83, // Opcode: LFSU +/* 6381 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 6389 +/* 6385 */ MCD_OPC_Decode, 240, 4, 84, // Opcode: LFD +/* 6389 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 6397 +/* 6393 */ MCD_OPC_Decode, 241, 4, 84, // Opcode: LFDU +/* 6397 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 6405 +/* 6401 */ MCD_OPC_Decode, 172, 8, 83, // Opcode: STFS +/* 6405 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 6413 +/* 6409 */ MCD_OPC_Decode, 173, 8, 83, // Opcode: STFSU +/* 6413 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 6421 +/* 6417 */ MCD_OPC_Decode, 167, 8, 84, // Opcode: STFD +/* 6421 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 6429 +/* 6425 */ MCD_OPC_Decode, 168, 8, 84, // Opcode: STFDU +/* 6429 */ MCD_OPC_FilterValue, 58, 27, 0, // Skip to: 6460 +/* 6433 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6436 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6444 +/* 6440 */ MCD_OPC_Decode, 226, 4, 85, // Opcode: LD +/* 6444 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 6452 +/* 6448 */ MCD_OPC_Decode, 230, 4, 85, // Opcode: LDU +/* 6452 */ MCD_OPC_FilterValue, 2, 189, 13, // Skip to: 9973 +/* 6456 */ MCD_OPC_Decode, 154, 5, 85, // Opcode: LWA +/* 6460 */ MCD_OPC_FilterValue, 59, 113, 1, // Skip to: 6833 +/* 6464 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 6467 */ MCD_OPC_FilterValue, 28, 31, 0, // Skip to: 6502 +/* 6471 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6474 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 6488 +/* 6478 */ MCD_OPC_CheckField, 16, 5, 0, 161, 13, // Skip to: 9973 +/* 6484 */ MCD_OPC_Decode, 230, 3, 86, // Opcode: FCFIDS +/* 6488 */ MCD_OPC_FilterValue, 30, 153, 13, // Skip to: 9973 +/* 6492 */ MCD_OPC_CheckField, 16, 5, 0, 147, 13, // Skip to: 9973 +/* 6498 */ MCD_OPC_Decode, 233, 3, 86, // Opcode: FCFIDUS +/* 6502 */ MCD_OPC_FilterValue, 29, 31, 0, // Skip to: 6537 +/* 6506 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6509 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 6523 +/* 6513 */ MCD_OPC_CheckField, 16, 5, 0, 126, 13, // Skip to: 9973 +/* 6519 */ MCD_OPC_Decode, 231, 3, 86, // Opcode: FCFIDSo +/* 6523 */ MCD_OPC_FilterValue, 30, 118, 13, // Skip to: 9973 +/* 6527 */ MCD_OPC_CheckField, 16, 5, 0, 112, 13, // Skip to: 9973 +/* 6533 */ MCD_OPC_Decode, 234, 3, 86, // Opcode: FCFIDUSo +/* 6537 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 6551 +/* 6541 */ MCD_OPC_CheckField, 6, 5, 0, 98, 13, // Skip to: 9973 +/* 6547 */ MCD_OPC_Decode, 128, 4, 87, // Opcode: FDIVS +/* 6551 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 6565 +/* 6555 */ MCD_OPC_CheckField, 6, 5, 0, 84, 13, // Skip to: 9973 +/* 6561 */ MCD_OPC_Decode, 129, 4, 87, // Opcode: FDIVSo +/* 6565 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 6579 +/* 6569 */ MCD_OPC_CheckField, 6, 5, 0, 70, 13, // Skip to: 9973 +/* 6575 */ MCD_OPC_Decode, 196, 4, 87, // Opcode: FSUBS +/* 6579 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 6593 +/* 6583 */ MCD_OPC_CheckField, 6, 5, 0, 56, 13, // Skip to: 9973 +/* 6589 */ MCD_OPC_Decode, 197, 4, 87, // Opcode: FSUBSo +/* 6593 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 6607 +/* 6597 */ MCD_OPC_CheckField, 6, 5, 0, 42, 13, // Skip to: 9973 +/* 6603 */ MCD_OPC_Decode, 225, 3, 87, // Opcode: FADDS +/* 6607 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 6621 +/* 6611 */ MCD_OPC_CheckField, 6, 5, 0, 28, 13, // Skip to: 9973 +/* 6617 */ MCD_OPC_Decode, 226, 3, 87, // Opcode: FADDSo +/* 6621 */ MCD_OPC_FilterValue, 44, 16, 0, // Skip to: 6641 +/* 6625 */ MCD_OPC_CheckField, 16, 5, 0, 14, 13, // Skip to: 9973 +/* 6631 */ MCD_OPC_CheckField, 6, 5, 0, 8, 13, // Skip to: 9973 +/* 6637 */ MCD_OPC_Decode, 192, 4, 88, // Opcode: FSQRTS +/* 6641 */ MCD_OPC_FilterValue, 45, 16, 0, // Skip to: 6661 +/* 6645 */ MCD_OPC_CheckField, 16, 5, 0, 250, 12, // Skip to: 9973 +/* 6651 */ MCD_OPC_CheckField, 6, 5, 0, 244, 12, // Skip to: 9973 +/* 6657 */ MCD_OPC_Decode, 193, 4, 88, // Opcode: FSQRTSo +/* 6661 */ MCD_OPC_FilterValue, 48, 16, 0, // Skip to: 6681 +/* 6665 */ MCD_OPC_CheckField, 16, 5, 0, 230, 12, // Skip to: 9973 +/* 6671 */ MCD_OPC_CheckField, 6, 5, 0, 224, 12, // Skip to: 9973 +/* 6677 */ MCD_OPC_Decode, 162, 4, 88, // Opcode: FRES +/* 6681 */ MCD_OPC_FilterValue, 49, 16, 0, // Skip to: 6701 +/* 6685 */ MCD_OPC_CheckField, 16, 5, 0, 210, 12, // Skip to: 9973 +/* 6691 */ MCD_OPC_CheckField, 6, 5, 0, 204, 12, // Skip to: 9973 +/* 6697 */ MCD_OPC_Decode, 163, 4, 88, // Opcode: FRESo +/* 6701 */ MCD_OPC_FilterValue, 50, 10, 0, // Skip to: 6715 +/* 6705 */ MCD_OPC_CheckField, 11, 5, 0, 190, 12, // Skip to: 9973 +/* 6711 */ MCD_OPC_Decode, 142, 4, 89, // Opcode: FMULS +/* 6715 */ MCD_OPC_FilterValue, 51, 10, 0, // Skip to: 6729 +/* 6719 */ MCD_OPC_CheckField, 11, 5, 0, 176, 12, // Skip to: 9973 +/* 6725 */ MCD_OPC_Decode, 143, 4, 89, // Opcode: FMULSo +/* 6729 */ MCD_OPC_FilterValue, 52, 16, 0, // Skip to: 6749 +/* 6733 */ MCD_OPC_CheckField, 16, 5, 0, 162, 12, // Skip to: 9973 +/* 6739 */ MCD_OPC_CheckField, 6, 5, 0, 156, 12, // Skip to: 9973 +/* 6745 */ MCD_OPC_Decode, 184, 4, 88, // Opcode: FRSQRTES +/* 6749 */ MCD_OPC_FilterValue, 53, 16, 0, // Skip to: 6769 +/* 6753 */ MCD_OPC_CheckField, 16, 5, 0, 142, 12, // Skip to: 9973 +/* 6759 */ MCD_OPC_CheckField, 6, 5, 0, 136, 12, // Skip to: 9973 +/* 6765 */ MCD_OPC_Decode, 185, 4, 88, // Opcode: FRSQRTESo +/* 6769 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 6777 +/* 6773 */ MCD_OPC_Decode, 138, 4, 90, // Opcode: FMSUBS +/* 6777 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 6785 +/* 6781 */ MCD_OPC_Decode, 139, 4, 90, // Opcode: FMSUBSo +/* 6785 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 6793 +/* 6789 */ MCD_OPC_Decode, 132, 4, 90, // Opcode: FMADDS +/* 6793 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 6801 +/* 6797 */ MCD_OPC_Decode, 133, 4, 90, // Opcode: FMADDSo +/* 6801 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 6809 +/* 6805 */ MCD_OPC_Decode, 158, 4, 90, // Opcode: FNMSUBS +/* 6809 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 6817 +/* 6813 */ MCD_OPC_Decode, 159, 4, 90, // Opcode: FNMSUBSo +/* 6817 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 6825 +/* 6821 */ MCD_OPC_Decode, 154, 4, 90, // Opcode: FNMADDS +/* 6825 */ MCD_OPC_FilterValue, 63, 72, 12, // Skip to: 9973 +/* 6829 */ MCD_OPC_Decode, 155, 4, 90, // Opcode: FNMADDSo +/* 6833 */ MCD_OPC_FilterValue, 60, 32, 8, // Skip to: 8917 +/* 6837 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 6840 */ MCD_OPC_FilterValue, 0, 16, 2, // Skip to: 7372 +/* 6844 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6847 */ MCD_OPC_FilterValue, 4, 19, 0, // Skip to: 6870 +/* 6851 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6854 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6862 +/* 6858 */ MCD_OPC_Decode, 220, 10, 91, // Opcode: XSADDDP +/* 6862 */ MCD_OPC_FilterValue, 1, 35, 12, // Skip to: 9973 +/* 6866 */ MCD_OPC_Decode, 233, 10, 92, // Opcode: XSMADDADP +/* 6870 */ MCD_OPC_FilterValue, 5, 19, 0, // Skip to: 6893 +/* 6874 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6877 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6885 +/* 6881 */ MCD_OPC_Decode, 254, 10, 91, // Opcode: XSSUBDP +/* 6885 */ MCD_OPC_FilterValue, 1, 12, 12, // Skip to: 9973 +/* 6889 */ MCD_OPC_Decode, 234, 10, 92, // Opcode: XSMADDMDP +/* 6893 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 6916 +/* 6897 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6900 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6908 +/* 6904 */ MCD_OPC_Decode, 239, 10, 91, // Opcode: XSMULDP +/* 6908 */ MCD_OPC_FilterValue, 1, 245, 11, // Skip to: 9973 +/* 6912 */ MCD_OPC_Decode, 237, 10, 92, // Opcode: XSMSUBADP +/* 6916 */ MCD_OPC_FilterValue, 7, 19, 0, // Skip to: 6939 +/* 6920 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6923 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6931 +/* 6927 */ MCD_OPC_Decode, 232, 10, 91, // Opcode: XSDIVDP +/* 6931 */ MCD_OPC_FilterValue, 1, 222, 11, // Skip to: 9973 +/* 6935 */ MCD_OPC_Decode, 238, 10, 92, // Opcode: XSMSUBMDP +/* 6939 */ MCD_OPC_FilterValue, 8, 19, 0, // Skip to: 6962 +/* 6943 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6946 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6954 +/* 6950 */ MCD_OPC_Decode, 132, 11, 93, // Opcode: XVADDSP +/* 6954 */ MCD_OPC_FilterValue, 1, 199, 11, // Skip to: 9973 +/* 6958 */ MCD_OPC_Decode, 168, 11, 94, // Opcode: XVMADDASP +/* 6962 */ MCD_OPC_FilterValue, 9, 19, 0, // Skip to: 6985 +/* 6966 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6969 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6977 +/* 6973 */ MCD_OPC_Decode, 210, 11, 93, // Opcode: XVSUBSP +/* 6977 */ MCD_OPC_FilterValue, 1, 176, 11, // Skip to: 9973 +/* 6981 */ MCD_OPC_Decode, 170, 11, 94, // Opcode: XVMADDMSP +/* 6985 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 7008 +/* 6989 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 6992 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7000 +/* 6996 */ MCD_OPC_Decode, 180, 11, 93, // Opcode: XVMULSP +/* 7000 */ MCD_OPC_FilterValue, 1, 153, 11, // Skip to: 9973 +/* 7004 */ MCD_OPC_Decode, 176, 11, 94, // Opcode: XVMSUBASP +/* 7008 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 7031 +/* 7012 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7015 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7023 +/* 7019 */ MCD_OPC_Decode, 166, 11, 93, // Opcode: XVDIVSP +/* 7023 */ MCD_OPC_FilterValue, 1, 130, 11, // Skip to: 9973 +/* 7027 */ MCD_OPC_Decode, 178, 11, 94, // Opcode: XVMSUBMSP +/* 7031 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 7054 +/* 7035 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7038 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7046 +/* 7042 */ MCD_OPC_Decode, 131, 11, 93, // Opcode: XVADDDP +/* 7046 */ MCD_OPC_FilterValue, 1, 107, 11, // Skip to: 9973 +/* 7050 */ MCD_OPC_Decode, 167, 11, 94, // Opcode: XVMADDADP +/* 7054 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 7077 +/* 7058 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7061 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7069 +/* 7065 */ MCD_OPC_Decode, 209, 11, 93, // Opcode: XVSUBDP +/* 7069 */ MCD_OPC_FilterValue, 1, 84, 11, // Skip to: 9973 +/* 7073 */ MCD_OPC_Decode, 169, 11, 94, // Opcode: XVMADDMDP +/* 7077 */ MCD_OPC_FilterValue, 14, 19, 0, // Skip to: 7100 +/* 7081 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7084 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7092 +/* 7088 */ MCD_OPC_Decode, 179, 11, 93, // Opcode: XVMULDP +/* 7092 */ MCD_OPC_FilterValue, 1, 61, 11, // Skip to: 9973 +/* 7096 */ MCD_OPC_Decode, 175, 11, 94, // Opcode: XVMSUBADP +/* 7100 */ MCD_OPC_FilterValue, 15, 19, 0, // Skip to: 7123 +/* 7104 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7107 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7115 +/* 7111 */ MCD_OPC_Decode, 165, 11, 93, // Opcode: XVDIVDP +/* 7115 */ MCD_OPC_FilterValue, 1, 38, 11, // Skip to: 9973 +/* 7119 */ MCD_OPC_Decode, 177, 11, 94, // Opcode: XVMSUBMDP +/* 7123 */ MCD_OPC_FilterValue, 20, 19, 0, // Skip to: 7146 +/* 7127 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7130 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7138 +/* 7134 */ MCD_OPC_Decode, 235, 10, 91, // Opcode: XSMAXDP +/* 7138 */ MCD_OPC_FilterValue, 1, 15, 11, // Skip to: 9973 +/* 7142 */ MCD_OPC_Decode, 242, 10, 92, // Opcode: XSNMADDADP +/* 7146 */ MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 7169 +/* 7150 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7153 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7161 +/* 7157 */ MCD_OPC_Decode, 236, 10, 91, // Opcode: XSMINDP +/* 7161 */ MCD_OPC_FilterValue, 1, 248, 10, // Skip to: 9973 +/* 7165 */ MCD_OPC_Decode, 243, 10, 92, // Opcode: XSNMADDMDP +/* 7169 */ MCD_OPC_FilterValue, 22, 19, 0, // Skip to: 7192 +/* 7173 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7176 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7184 +/* 7180 */ MCD_OPC_Decode, 223, 10, 91, // Opcode: XSCPSGNDP +/* 7184 */ MCD_OPC_FilterValue, 1, 225, 10, // Skip to: 9973 +/* 7188 */ MCD_OPC_Decode, 244, 10, 92, // Opcode: XSNMSUBADP +/* 7192 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 7206 +/* 7196 */ MCD_OPC_CheckField, 3, 1, 1, 211, 10, // Skip to: 9973 +/* 7202 */ MCD_OPC_Decode, 245, 10, 92, // Opcode: XSNMSUBMDP +/* 7206 */ MCD_OPC_FilterValue, 24, 19, 0, // Skip to: 7229 +/* 7210 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7213 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7221 +/* 7217 */ MCD_OPC_Decode, 172, 11, 93, // Opcode: XVMAXSP +/* 7221 */ MCD_OPC_FilterValue, 1, 188, 10, // Skip to: 9973 +/* 7225 */ MCD_OPC_Decode, 186, 11, 94, // Opcode: XVNMADDASP +/* 7229 */ MCD_OPC_FilterValue, 25, 19, 0, // Skip to: 7252 +/* 7233 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7236 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7244 +/* 7240 */ MCD_OPC_Decode, 174, 11, 93, // Opcode: XVMINSP +/* 7244 */ MCD_OPC_FilterValue, 1, 165, 10, // Skip to: 9973 +/* 7248 */ MCD_OPC_Decode, 188, 11, 94, // Opcode: XVNMADDMSP +/* 7252 */ MCD_OPC_FilterValue, 26, 19, 0, // Skip to: 7275 +/* 7256 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7259 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7267 +/* 7263 */ MCD_OPC_Decode, 146, 11, 93, // Opcode: XVCPSGNSP +/* 7267 */ MCD_OPC_FilterValue, 1, 142, 10, // Skip to: 9973 +/* 7271 */ MCD_OPC_Decode, 190, 11, 94, // Opcode: XVNMSUBASP +/* 7275 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 7289 +/* 7279 */ MCD_OPC_CheckField, 3, 1, 1, 128, 10, // Skip to: 9973 +/* 7285 */ MCD_OPC_Decode, 192, 11, 94, // Opcode: XVNMSUBMSP +/* 7289 */ MCD_OPC_FilterValue, 28, 19, 0, // Skip to: 7312 +/* 7293 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7296 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7304 +/* 7300 */ MCD_OPC_Decode, 171, 11, 93, // Opcode: XVMAXDP +/* 7304 */ MCD_OPC_FilterValue, 1, 105, 10, // Skip to: 9973 +/* 7308 */ MCD_OPC_Decode, 185, 11, 94, // Opcode: XVNMADDADP +/* 7312 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 7335 +/* 7316 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7319 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7327 +/* 7323 */ MCD_OPC_Decode, 173, 11, 93, // Opcode: XVMINDP +/* 7327 */ MCD_OPC_FilterValue, 1, 82, 10, // Skip to: 9973 +/* 7331 */ MCD_OPC_Decode, 187, 11, 94, // Opcode: XVNMADDMDP +/* 7335 */ MCD_OPC_FilterValue, 30, 19, 0, // Skip to: 7358 +/* 7339 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7342 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7350 +/* 7346 */ MCD_OPC_Decode, 145, 11, 93, // Opcode: XVCPSGNDP +/* 7350 */ MCD_OPC_FilterValue, 1, 59, 10, // Skip to: 9973 +/* 7354 */ MCD_OPC_Decode, 189, 11, 94, // Opcode: XVNMSUBADP +/* 7358 */ MCD_OPC_FilterValue, 31, 51, 10, // Skip to: 9973 +/* 7362 */ MCD_OPC_CheckField, 3, 1, 1, 45, 10, // Skip to: 9973 +/* 7368 */ MCD_OPC_Decode, 191, 11, 94, // Opcode: XVNMSUBMDP +/* 7372 */ MCD_OPC_FilterValue, 1, 130, 1, // Skip to: 7762 +/* 7376 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7379 */ MCD_OPC_FilterValue, 0, 100, 0, // Skip to: 7483 +/* 7383 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7386 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 7424 +/* 7390 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 7393 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7401 +/* 7397 */ MCD_OPC_Decode, 228, 11, 95, // Opcode: XXSLDWI +/* 7401 */ MCD_OPC_FilterValue, 1, 8, 10, // Skip to: 9973 +/* 7405 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 7408 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7416 +/* 7412 */ MCD_OPC_Decode, 215, 11, 93, // Opcode: XXLAND +/* 7416 */ MCD_OPC_FilterValue, 1, 249, 9, // Skip to: 9973 +/* 7420 */ MCD_OPC_Decode, 219, 11, 93, // Opcode: XXLNOR +/* 7424 */ MCD_OPC_FilterValue, 1, 241, 9, // Skip to: 9973 +/* 7428 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 7431 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 7451 +/* 7435 */ MCD_OPC_CheckField, 21, 2, 0, 228, 9, // Skip to: 9973 +/* 7441 */ MCD_OPC_CheckField, 0, 1, 0, 222, 9, // Skip to: 9973 +/* 7447 */ MCD_OPC_Decode, 222, 10, 96, // Opcode: XSCMPUDP +/* 7451 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 7459 +/* 7455 */ MCD_OPC_Decode, 135, 11, 93, // Opcode: XVCMPEQSP +/* 7459 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 7467 +/* 7463 */ MCD_OPC_Decode, 133, 11, 93, // Opcode: XVCMPEQDP +/* 7467 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 7475 +/* 7471 */ MCD_OPC_Decode, 136, 11, 93, // Opcode: XVCMPEQSPo +/* 7475 */ MCD_OPC_FilterValue, 7, 190, 9, // Skip to: 9973 +/* 7479 */ MCD_OPC_Decode, 134, 11, 93, // Opcode: XVCMPEQDPo +/* 7483 */ MCD_OPC_FilterValue, 1, 100, 0, // Skip to: 7587 +/* 7487 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7490 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 7528 +/* 7494 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 7497 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7505 +/* 7501 */ MCD_OPC_Decode, 226, 11, 95, // Opcode: XXPERMDI +/* 7505 */ MCD_OPC_FilterValue, 1, 160, 9, // Skip to: 9973 +/* 7509 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 7512 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7520 +/* 7516 */ MCD_OPC_Decode, 216, 11, 93, // Opcode: XXLANDC +/* 7520 */ MCD_OPC_FilterValue, 1, 145, 9, // Skip to: 9973 +/* 7524 */ MCD_OPC_Decode, 221, 11, 93, // Opcode: XXLORC +/* 7528 */ MCD_OPC_FilterValue, 1, 137, 9, // Skip to: 9973 +/* 7532 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 7535 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 7555 +/* 7539 */ MCD_OPC_CheckField, 21, 2, 0, 124, 9, // Skip to: 9973 +/* 7545 */ MCD_OPC_CheckField, 0, 1, 0, 118, 9, // Skip to: 9973 +/* 7551 */ MCD_OPC_Decode, 221, 10, 96, // Opcode: XSCMPODP +/* 7555 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 7563 +/* 7559 */ MCD_OPC_Decode, 143, 11, 93, // Opcode: XVCMPGTSP +/* 7563 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 7571 +/* 7567 */ MCD_OPC_Decode, 141, 11, 93, // Opcode: XVCMPGTDP +/* 7571 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 7579 +/* 7575 */ MCD_OPC_Decode, 144, 11, 93, // Opcode: XVCMPGTSPo +/* 7579 */ MCD_OPC_FilterValue, 7, 86, 9, // Skip to: 9973 +/* 7583 */ MCD_OPC_Decode, 142, 11, 93, // Opcode: XVCMPGTDPo +/* 7587 */ MCD_OPC_FilterValue, 2, 136, 0, // Skip to: 7727 +/* 7591 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 7594 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 7608 +/* 7598 */ MCD_OPC_CheckField, 3, 1, 0, 65, 9, // Skip to: 9973 +/* 7604 */ MCD_OPC_Decode, 224, 11, 93, // Opcode: XXMRGHW +/* 7608 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 7622 +/* 7612 */ MCD_OPC_CheckField, 3, 1, 0, 51, 9, // Skip to: 9973 +/* 7618 */ MCD_OPC_Decode, 225, 11, 93, // Opcode: XXMRGLW +/* 7622 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 7657 +/* 7626 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7629 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 7649 +/* 7633 */ MCD_OPC_CheckField, 18, 3, 0, 30, 9, // Skip to: 9973 +/* 7639 */ MCD_OPC_CheckField, 2, 1, 0, 24, 9, // Skip to: 9973 +/* 7645 */ MCD_OPC_Decode, 229, 11, 97, // Opcode: XXSPLTW +/* 7649 */ MCD_OPC_FilterValue, 1, 16, 9, // Skip to: 9973 +/* 7653 */ MCD_OPC_Decode, 139, 11, 93, // Opcode: XVCMPGESP +/* 7657 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 7671 +/* 7661 */ MCD_OPC_CheckField, 3, 1, 1, 2, 9, // Skip to: 9973 +/* 7667 */ MCD_OPC_Decode, 137, 11, 93, // Opcode: XVCMPGEDP +/* 7671 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 7685 +/* 7675 */ MCD_OPC_CheckField, 3, 1, 0, 244, 8, // Skip to: 9973 +/* 7681 */ MCD_OPC_Decode, 220, 11, 93, // Opcode: XXLOR +/* 7685 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 7699 +/* 7689 */ MCD_OPC_CheckField, 3, 1, 0, 230, 8, // Skip to: 9973 +/* 7695 */ MCD_OPC_Decode, 218, 11, 93, // Opcode: XXLNAND +/* 7699 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 7713 +/* 7703 */ MCD_OPC_CheckField, 3, 1, 1, 216, 8, // Skip to: 9973 +/* 7709 */ MCD_OPC_Decode, 140, 11, 93, // Opcode: XVCMPGESPo +/* 7713 */ MCD_OPC_FilterValue, 7, 208, 8, // Skip to: 9973 +/* 7717 */ MCD_OPC_CheckField, 3, 1, 1, 202, 8, // Skip to: 9973 +/* 7723 */ MCD_OPC_Decode, 138, 11, 93, // Opcode: XVCMPGEDPo +/* 7727 */ MCD_OPC_FilterValue, 3, 194, 8, // Skip to: 9973 +/* 7731 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 7734 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 7748 +/* 7738 */ MCD_OPC_CheckField, 3, 1, 0, 181, 8, // Skip to: 9973 +/* 7744 */ MCD_OPC_Decode, 223, 11, 93, // Opcode: XXLXOR +/* 7748 */ MCD_OPC_FilterValue, 5, 173, 8, // Skip to: 9973 +/* 7752 */ MCD_OPC_CheckField, 3, 1, 0, 167, 8, // Skip to: 9973 +/* 7758 */ MCD_OPC_Decode, 217, 11, 93, // Opcode: XXLEQV +/* 7762 */ MCD_OPC_FilterValue, 2, 119, 4, // Skip to: 8909 +/* 7766 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 7769 */ MCD_OPC_FilterValue, 4, 59, 0, // Skip to: 7832 +/* 7773 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 7776 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 7790 +/* 7780 */ MCD_OPC_CheckField, 16, 5, 0, 139, 8, // Skip to: 9973 +/* 7786 */ MCD_OPC_Decode, 228, 10, 98, // Opcode: XSCVDPUXWS +/* 7790 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 7804 +/* 7794 */ MCD_OPC_CheckField, 16, 5, 0, 125, 8, // Skip to: 9973 +/* 7800 */ MCD_OPC_Decode, 246, 10, 98, // Opcode: XSRDPI +/* 7804 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 7818 +/* 7808 */ MCD_OPC_CheckField, 16, 5, 0, 111, 8, // Skip to: 9973 +/* 7814 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: XSRSQRTEDP +/* 7818 */ MCD_OPC_FilterValue, 3, 103, 8, // Skip to: 9973 +/* 7822 */ MCD_OPC_CheckField, 16, 5, 0, 97, 8, // Skip to: 9973 +/* 7828 */ MCD_OPC_Decode, 253, 10, 98, // Opcode: XSSQRTDP +/* 7832 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 7881 +/* 7836 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 7839 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 7853 +/* 7843 */ MCD_OPC_CheckField, 16, 5, 0, 76, 8, // Skip to: 9973 +/* 7849 */ MCD_OPC_Decode, 226, 10, 98, // Opcode: XSCVDPSXWS +/* 7853 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 7867 +/* 7857 */ MCD_OPC_CheckField, 16, 5, 0, 62, 8, // Skip to: 9973 +/* 7863 */ MCD_OPC_Decode, 250, 10, 98, // Opcode: XSRDPIZ +/* 7867 */ MCD_OPC_FilterValue, 2, 54, 8, // Skip to: 9973 +/* 7871 */ MCD_OPC_CheckField, 16, 5, 0, 48, 8, // Skip to: 9973 +/* 7877 */ MCD_OPC_Decode, 251, 10, 98, // Opcode: XSREDP +/* 7881 */ MCD_OPC_FilterValue, 6, 51, 0, // Skip to: 7936 +/* 7885 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 7888 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 7902 +/* 7892 */ MCD_OPC_CheckField, 16, 5, 0, 27, 8, // Skip to: 9973 +/* 7898 */ MCD_OPC_Decode, 249, 10, 98, // Opcode: XSRDPIP +/* 7902 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 7922 +/* 7906 */ MCD_OPC_CheckField, 16, 7, 0, 13, 8, // Skip to: 9973 +/* 7912 */ MCD_OPC_CheckField, 0, 1, 0, 7, 8, // Skip to: 9973 +/* 7918 */ MCD_OPC_Decode, 128, 11, 99, // Opcode: XSTSQRTDP +/* 7922 */ MCD_OPC_FilterValue, 3, 255, 7, // Skip to: 9973 +/* 7926 */ MCD_OPC_CheckField, 16, 5, 0, 249, 7, // Skip to: 9973 +/* 7932 */ MCD_OPC_Decode, 247, 10, 98, // Opcode: XSRDPIC +/* 7936 */ MCD_OPC_FilterValue, 7, 43, 0, // Skip to: 7983 +/* 7940 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 7943 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 7963 +/* 7947 */ MCD_OPC_CheckField, 16, 5, 0, 228, 7, // Skip to: 9973 +/* 7953 */ MCD_OPC_CheckField, 2, 1, 1, 222, 7, // Skip to: 9973 +/* 7959 */ MCD_OPC_Decode, 248, 10, 98, // Opcode: XSRDPIM +/* 7963 */ MCD_OPC_FilterValue, 1, 214, 7, // Skip to: 9973 +/* 7967 */ MCD_OPC_CheckField, 21, 2, 0, 208, 7, // Skip to: 9973 +/* 7973 */ MCD_OPC_CheckField, 0, 1, 0, 202, 7, // Skip to: 9973 +/* 7979 */ MCD_OPC_Decode, 255, 10, 96, // Opcode: XSTDIVDP +/* 7983 */ MCD_OPC_FilterValue, 8, 59, 0, // Skip to: 8046 +/* 7987 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 7990 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8004 +/* 7994 */ MCD_OPC_CheckField, 16, 5, 0, 181, 7, // Skip to: 9973 +/* 8000 */ MCD_OPC_Decode, 156, 11, 100, // Opcode: XVCVSPUXWS +/* 8004 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8018 +/* 8008 */ MCD_OPC_CheckField, 16, 5, 0, 167, 7, // Skip to: 9973 +/* 8014 */ MCD_OPC_Decode, 200, 11, 100, // Opcode: XVRSPI +/* 8018 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 8032 +/* 8022 */ MCD_OPC_CheckField, 16, 5, 0, 153, 7, // Skip to: 9973 +/* 8028 */ MCD_OPC_Decode, 206, 11, 100, // Opcode: XVRSQRTESP +/* 8032 */ MCD_OPC_FilterValue, 3, 145, 7, // Skip to: 9973 +/* 8036 */ MCD_OPC_CheckField, 16, 5, 0, 139, 7, // Skip to: 9973 +/* 8042 */ MCD_OPC_Decode, 208, 11, 100, // Opcode: XVSQRTSP +/* 8046 */ MCD_OPC_FilterValue, 9, 45, 0, // Skip to: 8095 +/* 8050 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8053 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8067 +/* 8057 */ MCD_OPC_CheckField, 16, 5, 0, 118, 7, // Skip to: 9973 +/* 8063 */ MCD_OPC_Decode, 154, 11, 100, // Opcode: XVCVSPSXWS +/* 8067 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8081 +/* 8071 */ MCD_OPC_CheckField, 16, 5, 0, 104, 7, // Skip to: 9973 +/* 8077 */ MCD_OPC_Decode, 204, 11, 100, // Opcode: XVRSPIZ +/* 8081 */ MCD_OPC_FilterValue, 2, 96, 7, // Skip to: 9973 +/* 8085 */ MCD_OPC_CheckField, 16, 5, 0, 90, 7, // Skip to: 9973 +/* 8091 */ MCD_OPC_Decode, 199, 11, 100, // Opcode: XVRESP +/* 8095 */ MCD_OPC_FilterValue, 10, 65, 0, // Skip to: 8164 +/* 8099 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8102 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8116 +/* 8106 */ MCD_OPC_CheckField, 16, 5, 0, 69, 7, // Skip to: 9973 +/* 8112 */ MCD_OPC_Decode, 164, 11, 100, // Opcode: XVCVUXWSP +/* 8116 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8130 +/* 8120 */ MCD_OPC_CheckField, 16, 5, 0, 55, 7, // Skip to: 9973 +/* 8126 */ MCD_OPC_Decode, 203, 11, 100, // Opcode: XVRSPIP +/* 8130 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 8150 +/* 8134 */ MCD_OPC_CheckField, 16, 7, 0, 41, 7, // Skip to: 9973 +/* 8140 */ MCD_OPC_CheckField, 0, 1, 0, 35, 7, // Skip to: 9973 +/* 8146 */ MCD_OPC_Decode, 214, 11, 101, // Opcode: XVTSQRTSP +/* 8150 */ MCD_OPC_FilterValue, 3, 27, 7, // Skip to: 9973 +/* 8154 */ MCD_OPC_CheckField, 16, 5, 0, 21, 7, // Skip to: 9973 +/* 8160 */ MCD_OPC_Decode, 201, 11, 100, // Opcode: XVRSPIC +/* 8164 */ MCD_OPC_FilterValue, 11, 58, 0, // Skip to: 8226 +/* 8168 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 8171 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 8206 +/* 8175 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 8178 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8192 +/* 8182 */ MCD_OPC_CheckField, 16, 5, 0, 249, 6, // Skip to: 9973 +/* 8188 */ MCD_OPC_Decode, 160, 11, 100, // Opcode: XVCVSXWSP +/* 8192 */ MCD_OPC_FilterValue, 1, 241, 6, // Skip to: 9973 +/* 8196 */ MCD_OPC_CheckField, 16, 5, 0, 235, 6, // Skip to: 9973 +/* 8202 */ MCD_OPC_Decode, 202, 11, 100, // Opcode: XVRSPIM +/* 8206 */ MCD_OPC_FilterValue, 1, 227, 6, // Skip to: 9973 +/* 8210 */ MCD_OPC_CheckField, 21, 2, 0, 221, 6, // Skip to: 9973 +/* 8216 */ MCD_OPC_CheckField, 0, 1, 0, 215, 6, // Skip to: 9973 +/* 8222 */ MCD_OPC_Decode, 212, 11, 102, // Opcode: XVTDIVSP +/* 8226 */ MCD_OPC_FilterValue, 12, 59, 0, // Skip to: 8289 +/* 8230 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8233 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8247 +/* 8237 */ MCD_OPC_CheckField, 16, 5, 0, 194, 6, // Skip to: 9973 +/* 8243 */ MCD_OPC_Decode, 151, 11, 100, // Opcode: XVCVDPUXWS +/* 8247 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8261 +/* 8251 */ MCD_OPC_CheckField, 16, 5, 0, 180, 6, // Skip to: 9973 +/* 8257 */ MCD_OPC_Decode, 193, 11, 100, // Opcode: XVRDPI +/* 8261 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 8275 +/* 8265 */ MCD_OPC_CheckField, 16, 5, 0, 166, 6, // Skip to: 9973 +/* 8271 */ MCD_OPC_Decode, 205, 11, 100, // Opcode: XVRSQRTEDP +/* 8275 */ MCD_OPC_FilterValue, 3, 158, 6, // Skip to: 9973 +/* 8279 */ MCD_OPC_CheckField, 16, 5, 0, 152, 6, // Skip to: 9973 +/* 8285 */ MCD_OPC_Decode, 207, 11, 100, // Opcode: XVSQRTDP +/* 8289 */ MCD_OPC_FilterValue, 13, 45, 0, // Skip to: 8338 +/* 8293 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8296 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8310 +/* 8300 */ MCD_OPC_CheckField, 16, 5, 0, 131, 6, // Skip to: 9973 +/* 8306 */ MCD_OPC_Decode, 149, 11, 100, // Opcode: XVCVDPSXWS +/* 8310 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8324 +/* 8314 */ MCD_OPC_CheckField, 16, 5, 0, 117, 6, // Skip to: 9973 +/* 8320 */ MCD_OPC_Decode, 197, 11, 100, // Opcode: XVRDPIZ +/* 8324 */ MCD_OPC_FilterValue, 2, 109, 6, // Skip to: 9973 +/* 8328 */ MCD_OPC_CheckField, 16, 5, 0, 103, 6, // Skip to: 9973 +/* 8334 */ MCD_OPC_Decode, 198, 11, 100, // Opcode: XVREDP +/* 8338 */ MCD_OPC_FilterValue, 14, 65, 0, // Skip to: 8407 +/* 8342 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8345 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8359 +/* 8349 */ MCD_OPC_CheckField, 16, 5, 0, 82, 6, // Skip to: 9973 +/* 8355 */ MCD_OPC_Decode, 163, 11, 100, // Opcode: XVCVUXWDP +/* 8359 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 8373 +/* 8363 */ MCD_OPC_CheckField, 16, 5, 0, 68, 6, // Skip to: 9973 +/* 8369 */ MCD_OPC_Decode, 196, 11, 100, // Opcode: XVRDPIP +/* 8373 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 8393 +/* 8377 */ MCD_OPC_CheckField, 16, 7, 0, 54, 6, // Skip to: 9973 +/* 8383 */ MCD_OPC_CheckField, 0, 1, 0, 48, 6, // Skip to: 9973 +/* 8389 */ MCD_OPC_Decode, 213, 11, 101, // Opcode: XVTSQRTDP +/* 8393 */ MCD_OPC_FilterValue, 3, 40, 6, // Skip to: 9973 +/* 8397 */ MCD_OPC_CheckField, 16, 5, 0, 34, 6, // Skip to: 9973 +/* 8403 */ MCD_OPC_Decode, 194, 11, 100, // Opcode: XVRDPIC +/* 8407 */ MCD_OPC_FilterValue, 15, 58, 0, // Skip to: 8469 +/* 8411 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 8414 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 8449 +/* 8418 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 8421 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8435 +/* 8425 */ MCD_OPC_CheckField, 16, 5, 0, 6, 6, // Skip to: 9973 +/* 8431 */ MCD_OPC_Decode, 159, 11, 100, // Opcode: XVCVSXWDP +/* 8435 */ MCD_OPC_FilterValue, 1, 254, 5, // Skip to: 9973 +/* 8439 */ MCD_OPC_CheckField, 16, 5, 0, 248, 5, // Skip to: 9973 +/* 8445 */ MCD_OPC_Decode, 195, 11, 100, // Opcode: XVRDPIM +/* 8449 */ MCD_OPC_FilterValue, 1, 240, 5, // Skip to: 9973 +/* 8453 */ MCD_OPC_CheckField, 21, 2, 0, 234, 5, // Skip to: 9973 +/* 8459 */ MCD_OPC_CheckField, 0, 1, 0, 228, 5, // Skip to: 9973 +/* 8465 */ MCD_OPC_Decode, 211, 11, 102, // Opcode: XVTDIVDP +/* 8469 */ MCD_OPC_FilterValue, 16, 16, 0, // Skip to: 8489 +/* 8473 */ MCD_OPC_CheckField, 16, 5, 0, 214, 5, // Skip to: 9973 +/* 8479 */ MCD_OPC_CheckField, 2, 2, 1, 208, 5, // Skip to: 9973 +/* 8485 */ MCD_OPC_Decode, 224, 10, 98, // Opcode: XSCVDPSP +/* 8489 */ MCD_OPC_FilterValue, 20, 31, 0, // Skip to: 8524 +/* 8493 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8496 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8510 +/* 8500 */ MCD_OPC_CheckField, 16, 5, 0, 187, 5, // Skip to: 9973 +/* 8506 */ MCD_OPC_Decode, 227, 10, 98, // Opcode: XSCVDPUXDS +/* 8510 */ MCD_OPC_FilterValue, 1, 179, 5, // Skip to: 9973 +/* 8514 */ MCD_OPC_CheckField, 16, 5, 0, 173, 5, // Skip to: 9973 +/* 8520 */ MCD_OPC_Decode, 229, 10, 98, // Opcode: XSCVSPDP +/* 8524 */ MCD_OPC_FilterValue, 21, 31, 0, // Skip to: 8559 +/* 8528 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8531 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8545 +/* 8535 */ MCD_OPC_CheckField, 16, 5, 0, 152, 5, // Skip to: 9973 +/* 8541 */ MCD_OPC_Decode, 225, 10, 98, // Opcode: XSCVDPSXDS +/* 8545 */ MCD_OPC_FilterValue, 1, 144, 5, // Skip to: 9973 +/* 8549 */ MCD_OPC_CheckField, 16, 5, 0, 138, 5, // Skip to: 9973 +/* 8555 */ MCD_OPC_Decode, 219, 10, 98, // Opcode: XSABSDP +/* 8559 */ MCD_OPC_FilterValue, 22, 31, 0, // Skip to: 8594 +/* 8563 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8566 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8580 +/* 8570 */ MCD_OPC_CheckField, 16, 5, 0, 117, 5, // Skip to: 9973 +/* 8576 */ MCD_OPC_Decode, 231, 10, 98, // Opcode: XSCVUXDDP +/* 8580 */ MCD_OPC_FilterValue, 1, 109, 5, // Skip to: 9973 +/* 8584 */ MCD_OPC_CheckField, 16, 5, 0, 103, 5, // Skip to: 9973 +/* 8590 */ MCD_OPC_Decode, 240, 10, 98, // Opcode: XSNABSDP +/* 8594 */ MCD_OPC_FilterValue, 23, 31, 0, // Skip to: 8629 +/* 8598 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8601 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8615 +/* 8605 */ MCD_OPC_CheckField, 16, 5, 0, 82, 5, // Skip to: 9973 +/* 8611 */ MCD_OPC_Decode, 230, 10, 98, // Opcode: XSCVSXDDP +/* 8615 */ MCD_OPC_FilterValue, 1, 74, 5, // Skip to: 9973 +/* 8619 */ MCD_OPC_CheckField, 16, 5, 0, 68, 5, // Skip to: 9973 +/* 8625 */ MCD_OPC_Decode, 241, 10, 98, // Opcode: XSNEGDP +/* 8629 */ MCD_OPC_FilterValue, 24, 31, 0, // Skip to: 8664 +/* 8633 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8650 +/* 8640 */ MCD_OPC_CheckField, 16, 5, 0, 47, 5, // Skip to: 9973 +/* 8646 */ MCD_OPC_Decode, 155, 11, 100, // Opcode: XVCVSPUXDS +/* 8650 */ MCD_OPC_FilterValue, 1, 39, 5, // Skip to: 9973 +/* 8654 */ MCD_OPC_CheckField, 16, 5, 0, 33, 5, // Skip to: 9973 +/* 8660 */ MCD_OPC_Decode, 147, 11, 100, // Opcode: XVCVDPSP +/* 8664 */ MCD_OPC_FilterValue, 25, 31, 0, // Skip to: 8699 +/* 8668 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8671 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8685 +/* 8675 */ MCD_OPC_CheckField, 16, 5, 0, 12, 5, // Skip to: 9973 +/* 8681 */ MCD_OPC_Decode, 153, 11, 100, // Opcode: XVCVSPSXDS +/* 8685 */ MCD_OPC_FilterValue, 1, 4, 5, // Skip to: 9973 +/* 8689 */ MCD_OPC_CheckField, 16, 5, 0, 254, 4, // Skip to: 9973 +/* 8695 */ MCD_OPC_Decode, 130, 11, 100, // Opcode: XVABSSP +/* 8699 */ MCD_OPC_FilterValue, 26, 31, 0, // Skip to: 8734 +/* 8703 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8706 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8720 +/* 8710 */ MCD_OPC_CheckField, 16, 5, 0, 233, 4, // Skip to: 9973 +/* 8716 */ MCD_OPC_Decode, 162, 11, 100, // Opcode: XVCVUXDSP +/* 8720 */ MCD_OPC_FilterValue, 1, 225, 4, // Skip to: 9973 +/* 8724 */ MCD_OPC_CheckField, 16, 5, 0, 219, 4, // Skip to: 9973 +/* 8730 */ MCD_OPC_Decode, 182, 11, 100, // Opcode: XVNABSSP +/* 8734 */ MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 8769 +/* 8738 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8741 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8755 +/* 8745 */ MCD_OPC_CheckField, 16, 5, 0, 198, 4, // Skip to: 9973 +/* 8751 */ MCD_OPC_Decode, 158, 11, 100, // Opcode: XVCVSXDSP +/* 8755 */ MCD_OPC_FilterValue, 1, 190, 4, // Skip to: 9973 +/* 8759 */ MCD_OPC_CheckField, 16, 5, 0, 184, 4, // Skip to: 9973 +/* 8765 */ MCD_OPC_Decode, 184, 11, 100, // Opcode: XVNEGSP +/* 8769 */ MCD_OPC_FilterValue, 28, 31, 0, // Skip to: 8804 +/* 8773 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8776 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8790 +/* 8780 */ MCD_OPC_CheckField, 16, 5, 0, 163, 4, // Skip to: 9973 +/* 8786 */ MCD_OPC_Decode, 150, 11, 100, // Opcode: XVCVDPUXDS +/* 8790 */ MCD_OPC_FilterValue, 1, 155, 4, // Skip to: 9973 +/* 8794 */ MCD_OPC_CheckField, 16, 5, 0, 149, 4, // Skip to: 9973 +/* 8800 */ MCD_OPC_Decode, 152, 11, 100, // Opcode: XVCVSPDP +/* 8804 */ MCD_OPC_FilterValue, 29, 31, 0, // Skip to: 8839 +/* 8808 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8811 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8825 +/* 8815 */ MCD_OPC_CheckField, 16, 5, 0, 128, 4, // Skip to: 9973 +/* 8821 */ MCD_OPC_Decode, 148, 11, 100, // Opcode: XVCVDPSXDS +/* 8825 */ MCD_OPC_FilterValue, 1, 120, 4, // Skip to: 9973 +/* 8829 */ MCD_OPC_CheckField, 16, 5, 0, 114, 4, // Skip to: 9973 +/* 8835 */ MCD_OPC_Decode, 129, 11, 100, // Opcode: XVABSDP +/* 8839 */ MCD_OPC_FilterValue, 30, 31, 0, // Skip to: 8874 +/* 8843 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8846 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8860 +/* 8850 */ MCD_OPC_CheckField, 16, 5, 0, 93, 4, // Skip to: 9973 +/* 8856 */ MCD_OPC_Decode, 161, 11, 100, // Opcode: XVCVUXDDP +/* 8860 */ MCD_OPC_FilterValue, 1, 85, 4, // Skip to: 9973 +/* 8864 */ MCD_OPC_CheckField, 16, 5, 0, 79, 4, // Skip to: 9973 +/* 8870 */ MCD_OPC_Decode, 181, 11, 100, // Opcode: XVNABSDP +/* 8874 */ MCD_OPC_FilterValue, 31, 71, 4, // Skip to: 9973 +/* 8878 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 8881 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8895 +/* 8885 */ MCD_OPC_CheckField, 16, 5, 0, 58, 4, // Skip to: 9973 +/* 8891 */ MCD_OPC_Decode, 157, 11, 100, // Opcode: XVCVSXDDP +/* 8895 */ MCD_OPC_FilterValue, 1, 50, 4, // Skip to: 9973 +/* 8899 */ MCD_OPC_CheckField, 16, 5, 0, 44, 4, // Skip to: 9973 +/* 8905 */ MCD_OPC_Decode, 183, 11, 100, // Opcode: XVNEGDP +/* 8909 */ MCD_OPC_FilterValue, 3, 36, 4, // Skip to: 9973 +/* 8913 */ MCD_OPC_Decode, 227, 11, 103, // Opcode: XXSEL +/* 8917 */ MCD_OPC_FilterValue, 62, 19, 0, // Skip to: 8940 +/* 8921 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8924 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 8932 +/* 8928 */ MCD_OPC_Decode, 160, 8, 85, // Opcode: STD +/* 8932 */ MCD_OPC_FilterValue, 1, 13, 4, // Skip to: 9973 +/* 8936 */ MCD_OPC_Decode, 164, 8, 85, // Opcode: STDU +/* 8940 */ MCD_OPC_FilterValue, 63, 5, 4, // Skip to: 9973 +/* 8944 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 8947 */ MCD_OPC_FilterValue, 0, 37, 0, // Skip to: 8988 +/* 8951 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 8954 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 8968 +/* 8958 */ MCD_OPC_CheckField, 21, 2, 0, 241, 3, // Skip to: 9973 +/* 8964 */ MCD_OPC_Decode, 238, 3, 104, // Opcode: FCMPUS +/* 8968 */ MCD_OPC_FilterValue, 2, 233, 3, // Skip to: 9973 +/* 8972 */ MCD_OPC_CheckField, 21, 2, 0, 227, 3, // Skip to: 9973 +/* 8978 */ MCD_OPC_CheckField, 11, 7, 0, 221, 3, // Skip to: 9973 +/* 8984 */ MCD_OPC_Decode, 178, 5, 23, // Opcode: MCRFS +/* 8988 */ MCD_OPC_FilterValue, 12, 45, 0, // Skip to: 9037 +/* 8992 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... +/* 8995 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 9009 +/* 8999 */ MCD_OPC_CheckField, 12, 9, 0, 200, 3, // Skip to: 9973 +/* 9005 */ MCD_OPC_Decode, 208, 5, 75, // Opcode: MTFSB1 +/* 9009 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 9023 +/* 9013 */ MCD_OPC_CheckField, 12, 9, 0, 186, 3, // Skip to: 9973 +/* 9019 */ MCD_OPC_Decode, 207, 5, 75, // Opcode: MTFSB0 +/* 9023 */ MCD_OPC_FilterValue, 4, 178, 3, // Skip to: 9973 +/* 9027 */ MCD_OPC_CheckField, 17, 6, 0, 172, 3, // Skip to: 9973 +/* 9033 */ MCD_OPC_Decode, 210, 5, 105, // Opcode: MTFSFI +/* 9037 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 9057 +/* 9041 */ MCD_OPC_CheckField, 17, 6, 0, 158, 3, // Skip to: 9973 +/* 9047 */ MCD_OPC_CheckField, 6, 6, 4, 152, 3, // Skip to: 9973 +/* 9053 */ MCD_OPC_Decode, 211, 5, 105, // Opcode: MTFSFIo +/* 9057 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 9086 +/* 9061 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9064 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 9078 +/* 9068 */ MCD_OPC_CheckField, 11, 10, 0, 131, 3, // Skip to: 9973 +/* 9074 */ MCD_OPC_Decode, 184, 5, 106, // Opcode: MFFS +/* 9078 */ MCD_OPC_FilterValue, 22, 123, 3, // Skip to: 9973 +/* 9082 */ MCD_OPC_Decode, 209, 5, 107, // Opcode: MTFSF +/* 9086 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 9115 +/* 9090 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9093 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 9107 +/* 9097 */ MCD_OPC_CheckField, 11, 10, 0, 102, 3, // Skip to: 9973 +/* 9103 */ MCD_OPC_Decode, 185, 5, 106, // Opcode: MFFSo +/* 9107 */ MCD_OPC_FilterValue, 22, 94, 3, // Skip to: 9973 +/* 9111 */ MCD_OPC_Decode, 213, 5, 107, // Opcode: MTFSFo +/* 9115 */ MCD_OPC_FilterValue, 16, 123, 0, // Skip to: 9242 +/* 9119 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9122 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 9130 +/* 9126 */ MCD_OPC_Decode, 241, 3, 87, // Opcode: FCPSGNS +/* 9130 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 9144 +/* 9134 */ MCD_OPC_CheckField, 16, 5, 0, 65, 3, // Skip to: 9973 +/* 9140 */ MCD_OPC_Decode, 151, 4, 88, // Opcode: FNEGS +/* 9144 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 9158 +/* 9148 */ MCD_OPC_CheckField, 16, 5, 0, 51, 3, // Skip to: 9973 +/* 9154 */ MCD_OPC_Decode, 135, 4, 88, // Opcode: FMR +/* 9158 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 9172 +/* 9162 */ MCD_OPC_CheckField, 16, 5, 0, 37, 3, // Skip to: 9973 +/* 9168 */ MCD_OPC_Decode, 147, 4, 88, // Opcode: FNABSS +/* 9172 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 9186 +/* 9176 */ MCD_OPC_CheckField, 16, 5, 0, 23, 3, // Skip to: 9973 +/* 9182 */ MCD_OPC_Decode, 222, 3, 88, // Opcode: FABSS +/* 9186 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 9200 +/* 9190 */ MCD_OPC_CheckField, 16, 5, 0, 9, 3, // Skip to: 9973 +/* 9196 */ MCD_OPC_Decode, 171, 4, 88, // Opcode: FRINS +/* 9200 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 9214 +/* 9204 */ MCD_OPC_CheckField, 16, 5, 0, 251, 2, // Skip to: 9973 +/* 9210 */ MCD_OPC_Decode, 179, 4, 88, // Opcode: FRIZS +/* 9214 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 9228 +/* 9218 */ MCD_OPC_CheckField, 16, 5, 0, 237, 2, // Skip to: 9973 +/* 9224 */ MCD_OPC_Decode, 175, 4, 88, // Opcode: FRIPS +/* 9228 */ MCD_OPC_FilterValue, 15, 229, 2, // Skip to: 9973 +/* 9232 */ MCD_OPC_CheckField, 16, 5, 0, 223, 2, // Skip to: 9973 +/* 9238 */ MCD_OPC_Decode, 167, 4, 88, // Opcode: FRIMS +/* 9242 */ MCD_OPC_FilterValue, 17, 123, 0, // Skip to: 9369 +/* 9246 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9249 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 9257 +/* 9253 */ MCD_OPC_Decode, 242, 3, 87, // Opcode: FCPSGNSo +/* 9257 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 9271 +/* 9261 */ MCD_OPC_CheckField, 16, 5, 0, 194, 2, // Skip to: 9973 +/* 9267 */ MCD_OPC_Decode, 152, 4, 88, // Opcode: FNEGSo +/* 9271 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 9285 +/* 9275 */ MCD_OPC_CheckField, 16, 5, 0, 180, 2, // Skip to: 9973 +/* 9281 */ MCD_OPC_Decode, 136, 4, 88, // Opcode: FMRo +/* 9285 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 9299 +/* 9289 */ MCD_OPC_CheckField, 16, 5, 0, 166, 2, // Skip to: 9973 +/* 9295 */ MCD_OPC_Decode, 148, 4, 88, // Opcode: FNABSSo +/* 9299 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 9313 +/* 9303 */ MCD_OPC_CheckField, 16, 5, 0, 152, 2, // Skip to: 9973 +/* 9309 */ MCD_OPC_Decode, 223, 3, 88, // Opcode: FABSSo +/* 9313 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 9327 +/* 9317 */ MCD_OPC_CheckField, 16, 5, 0, 138, 2, // Skip to: 9973 +/* 9323 */ MCD_OPC_Decode, 172, 4, 88, // Opcode: FRINSo +/* 9327 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 9341 +/* 9331 */ MCD_OPC_CheckField, 16, 5, 0, 124, 2, // Skip to: 9973 +/* 9337 */ MCD_OPC_Decode, 180, 4, 88, // Opcode: FRIZSo +/* 9341 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 9355 +/* 9345 */ MCD_OPC_CheckField, 16, 5, 0, 110, 2, // Skip to: 9973 +/* 9351 */ MCD_OPC_Decode, 176, 4, 88, // Opcode: FRIPSo +/* 9355 */ MCD_OPC_FilterValue, 15, 102, 2, // Skip to: 9973 +/* 9359 */ MCD_OPC_CheckField, 16, 5, 0, 96, 2, // Skip to: 9973 +/* 9365 */ MCD_OPC_Decode, 168, 4, 88, // Opcode: FRIMSo +/* 9369 */ MCD_OPC_FilterValue, 24, 16, 0, // Skip to: 9389 +/* 9373 */ MCD_OPC_CheckField, 16, 5, 0, 82, 2, // Skip to: 9973 +/* 9379 */ MCD_OPC_CheckField, 6, 5, 0, 76, 2, // Skip to: 9973 +/* 9385 */ MCD_OPC_Decode, 181, 4, 86, // Opcode: FRSP +/* 9389 */ MCD_OPC_FilterValue, 25, 16, 0, // Skip to: 9409 +/* 9393 */ MCD_OPC_CheckField, 16, 5, 0, 62, 2, // Skip to: 9973 +/* 9399 */ MCD_OPC_CheckField, 6, 5, 0, 56, 2, // Skip to: 9973 +/* 9405 */ MCD_OPC_Decode, 182, 4, 86, // Opcode: FRSPo +/* 9409 */ MCD_OPC_FilterValue, 28, 59, 0, // Skip to: 9472 +/* 9413 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9416 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 9430 +/* 9420 */ MCD_OPC_CheckField, 16, 5, 0, 35, 2, // Skip to: 9973 +/* 9426 */ MCD_OPC_Decode, 249, 3, 108, // Opcode: FCTIW +/* 9430 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 9444 +/* 9434 */ MCD_OPC_CheckField, 16, 5, 0, 21, 2, // Skip to: 9973 +/* 9440 */ MCD_OPC_Decode, 243, 3, 108, // Opcode: FCTID +/* 9444 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 9458 +/* 9448 */ MCD_OPC_CheckField, 16, 5, 0, 7, 2, // Skip to: 9973 +/* 9454 */ MCD_OPC_Decode, 229, 3, 108, // Opcode: FCFID +/* 9458 */ MCD_OPC_FilterValue, 30, 255, 1, // Skip to: 9973 +/* 9462 */ MCD_OPC_CheckField, 16, 5, 0, 249, 1, // Skip to: 9973 +/* 9468 */ MCD_OPC_Decode, 232, 3, 108, // Opcode: FCFIDU +/* 9472 */ MCD_OPC_FilterValue, 29, 59, 0, // Skip to: 9535 +/* 9476 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9479 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 9493 +/* 9483 */ MCD_OPC_CheckField, 16, 5, 0, 228, 1, // Skip to: 9973 +/* 9489 */ MCD_OPC_Decode, 254, 3, 108, // Opcode: FCTIWo +/* 9493 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 9507 +/* 9497 */ MCD_OPC_CheckField, 16, 5, 0, 214, 1, // Skip to: 9973 +/* 9503 */ MCD_OPC_Decode, 248, 3, 108, // Opcode: FCTIDo +/* 9507 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 9521 +/* 9511 */ MCD_OPC_CheckField, 16, 5, 0, 200, 1, // Skip to: 9973 +/* 9517 */ MCD_OPC_Decode, 236, 3, 108, // Opcode: FCFIDo +/* 9521 */ MCD_OPC_FilterValue, 30, 192, 1, // Skip to: 9973 +/* 9525 */ MCD_OPC_CheckField, 16, 5, 0, 186, 1, // Skip to: 9973 +/* 9531 */ MCD_OPC_Decode, 235, 3, 108, // Opcode: FCFIDUo +/* 9535 */ MCD_OPC_FilterValue, 30, 59, 0, // Skip to: 9598 +/* 9539 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9542 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 9556 +/* 9546 */ MCD_OPC_CheckField, 16, 5, 0, 165, 1, // Skip to: 9973 +/* 9552 */ MCD_OPC_Decode, 252, 3, 108, // Opcode: FCTIWZ +/* 9556 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 9570 +/* 9560 */ MCD_OPC_CheckField, 16, 5, 0, 151, 1, // Skip to: 9973 +/* 9566 */ MCD_OPC_Decode, 250, 3, 108, // Opcode: FCTIWUZ +/* 9570 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 9584 +/* 9574 */ MCD_OPC_CheckField, 16, 5, 0, 137, 1, // Skip to: 9973 +/* 9580 */ MCD_OPC_Decode, 246, 3, 108, // Opcode: FCTIDZ +/* 9584 */ MCD_OPC_FilterValue, 29, 129, 1, // Skip to: 9973 +/* 9588 */ MCD_OPC_CheckField, 16, 5, 0, 123, 1, // Skip to: 9973 +/* 9594 */ MCD_OPC_Decode, 244, 3, 108, // Opcode: FCTIDUZ +/* 9598 */ MCD_OPC_FilterValue, 31, 59, 0, // Skip to: 9661 +/* 9602 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9605 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 9619 +/* 9609 */ MCD_OPC_CheckField, 16, 5, 0, 102, 1, // Skip to: 9973 +/* 9615 */ MCD_OPC_Decode, 253, 3, 108, // Opcode: FCTIWZo +/* 9619 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 9633 +/* 9623 */ MCD_OPC_CheckField, 16, 5, 0, 88, 1, // Skip to: 9973 +/* 9629 */ MCD_OPC_Decode, 251, 3, 108, // Opcode: FCTIWUZo +/* 9633 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 9647 +/* 9637 */ MCD_OPC_CheckField, 16, 5, 0, 74, 1, // Skip to: 9973 +/* 9643 */ MCD_OPC_Decode, 247, 3, 108, // Opcode: FCTIDZo +/* 9647 */ MCD_OPC_FilterValue, 29, 66, 1, // Skip to: 9973 +/* 9651 */ MCD_OPC_CheckField, 16, 5, 0, 60, 1, // Skip to: 9973 +/* 9657 */ MCD_OPC_Decode, 245, 3, 108, // Opcode: FCTIDUZo +/* 9661 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 9675 +/* 9665 */ MCD_OPC_CheckField, 6, 5, 0, 46, 1, // Skip to: 9973 +/* 9671 */ MCD_OPC_Decode, 255, 3, 109, // Opcode: FDIV +/* 9675 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 9689 +/* 9679 */ MCD_OPC_CheckField, 6, 5, 0, 32, 1, // Skip to: 9973 +/* 9685 */ MCD_OPC_Decode, 130, 4, 109, // Opcode: FDIVo +/* 9689 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 9703 +/* 9693 */ MCD_OPC_CheckField, 6, 5, 0, 18, 1, // Skip to: 9973 +/* 9699 */ MCD_OPC_Decode, 195, 4, 109, // Opcode: FSUB +/* 9703 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 9717 +/* 9707 */ MCD_OPC_CheckField, 6, 5, 0, 4, 1, // Skip to: 9973 +/* 9713 */ MCD_OPC_Decode, 198, 4, 109, // Opcode: FSUBo +/* 9717 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 9731 +/* 9721 */ MCD_OPC_CheckField, 6, 5, 0, 246, 0, // Skip to: 9973 +/* 9727 */ MCD_OPC_Decode, 224, 3, 109, // Opcode: FADD +/* 9731 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 9745 +/* 9735 */ MCD_OPC_CheckField, 6, 5, 0, 232, 0, // Skip to: 9973 +/* 9741 */ MCD_OPC_Decode, 227, 3, 109, // Opcode: FADDo +/* 9745 */ MCD_OPC_FilterValue, 44, 16, 0, // Skip to: 9765 +/* 9749 */ MCD_OPC_CheckField, 16, 5, 0, 218, 0, // Skip to: 9973 +/* 9755 */ MCD_OPC_CheckField, 6, 5, 0, 212, 0, // Skip to: 9973 +/* 9761 */ MCD_OPC_Decode, 191, 4, 108, // Opcode: FSQRT +/* 9765 */ MCD_OPC_FilterValue, 45, 16, 0, // Skip to: 9785 +/* 9769 */ MCD_OPC_CheckField, 16, 5, 0, 198, 0, // Skip to: 9973 +/* 9775 */ MCD_OPC_CheckField, 6, 5, 0, 192, 0, // Skip to: 9973 +/* 9781 */ MCD_OPC_Decode, 194, 4, 108, // Opcode: FSQRTo +/* 9785 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 9793 +/* 9789 */ MCD_OPC_Decode, 189, 4, 110, // Opcode: FSELS +/* 9793 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 9801 +/* 9797 */ MCD_OPC_Decode, 190, 4, 110, // Opcode: FSELSo +/* 9801 */ MCD_OPC_FilterValue, 48, 16, 0, // Skip to: 9821 +/* 9805 */ MCD_OPC_CheckField, 16, 5, 0, 162, 0, // Skip to: 9973 +/* 9811 */ MCD_OPC_CheckField, 6, 5, 0, 156, 0, // Skip to: 9973 +/* 9817 */ MCD_OPC_Decode, 161, 4, 108, // Opcode: FRE +/* 9821 */ MCD_OPC_FilterValue, 49, 16, 0, // Skip to: 9841 +/* 9825 */ MCD_OPC_CheckField, 16, 5, 0, 142, 0, // Skip to: 9973 +/* 9831 */ MCD_OPC_CheckField, 6, 5, 0, 136, 0, // Skip to: 9973 +/* 9837 */ MCD_OPC_Decode, 164, 4, 108, // Opcode: FREo +/* 9841 */ MCD_OPC_FilterValue, 50, 10, 0, // Skip to: 9855 +/* 9845 */ MCD_OPC_CheckField, 11, 5, 0, 122, 0, // Skip to: 9973 +/* 9851 */ MCD_OPC_Decode, 141, 4, 111, // Opcode: FMUL +/* 9855 */ MCD_OPC_FilterValue, 51, 10, 0, // Skip to: 9869 +/* 9859 */ MCD_OPC_CheckField, 11, 5, 0, 108, 0, // Skip to: 9973 +/* 9865 */ MCD_OPC_Decode, 144, 4, 111, // Opcode: FMULo +/* 9869 */ MCD_OPC_FilterValue, 52, 16, 0, // Skip to: 9889 +/* 9873 */ MCD_OPC_CheckField, 16, 5, 0, 94, 0, // Skip to: 9973 +/* 9879 */ MCD_OPC_CheckField, 6, 5, 0, 88, 0, // Skip to: 9973 +/* 9885 */ MCD_OPC_Decode, 183, 4, 108, // Opcode: FRSQRTE +/* 9889 */ MCD_OPC_FilterValue, 53, 16, 0, // Skip to: 9909 +/* 9893 */ MCD_OPC_CheckField, 16, 5, 0, 74, 0, // Skip to: 9973 +/* 9899 */ MCD_OPC_CheckField, 6, 5, 0, 68, 0, // Skip to: 9973 +/* 9905 */ MCD_OPC_Decode, 186, 4, 108, // Opcode: FRSQRTEo +/* 9909 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 9917 +/* 9913 */ MCD_OPC_Decode, 137, 4, 112, // Opcode: FMSUB +/* 9917 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 9925 +/* 9921 */ MCD_OPC_Decode, 140, 4, 112, // Opcode: FMSUBo +/* 9925 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 9933 +/* 9929 */ MCD_OPC_Decode, 131, 4, 112, // Opcode: FMADD +/* 9933 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 9941 +/* 9937 */ MCD_OPC_Decode, 134, 4, 112, // Opcode: FMADDo +/* 9941 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 9949 +/* 9945 */ MCD_OPC_Decode, 157, 4, 112, // Opcode: FNMSUB +/* 9949 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 9957 +/* 9953 */ MCD_OPC_Decode, 160, 4, 112, // Opcode: FNMSUBo +/* 9957 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 9965 +/* 9961 */ MCD_OPC_Decode, 153, 4, 112, // Opcode: FNMADD +/* 9965 */ MCD_OPC_FilterValue, 63, 4, 0, // Skip to: 9973 +/* 9969 */ MCD_OPC_Decode, 156, 4, 112, // Opcode: FNMADDo +/* 9973 */ MCD_OPC_Fail, + 0 +}; + +static uint8_t DecoderTableQPX32[] = { +/* 0 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 3 */ MCD_OPC_FilterValue, 0, 59, 0, // Skip to: 66 +/* 7 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 10 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 24 +/* 14 */ MCD_OPC_CheckField, 26, 6, 4, 68, 7, // Skip to: 1880 +/* 20 */ MCD_OPC_Decode, 163, 6, 113, // Opcode: QVFCMPEQb +/* 24 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 38 +/* 28 */ MCD_OPC_CheckField, 26, 6, 4, 54, 7, // Skip to: 1880 +/* 34 */ MCD_OPC_Decode, 166, 6, 113, // Opcode: QVFCMPGTb +/* 38 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 52 +/* 42 */ MCD_OPC_CheckField, 26, 6, 4, 40, 7, // Skip to: 1880 +/* 48 */ MCD_OPC_Decode, 233, 6, 113, // Opcode: QVFTSTNANb +/* 52 */ MCD_OPC_FilterValue, 3, 32, 7, // Skip to: 1880 +/* 56 */ MCD_OPC_CheckField, 26, 6, 4, 26, 7, // Skip to: 1880 +/* 62 */ MCD_OPC_Decode, 169, 6, 113, // Opcode: QVFCMPLTb +/* 66 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 89 +/* 70 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 73 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 81 +/* 77 */ MCD_OPC_Decode, 242, 6, 114, // Opcode: QVFXXMADDS +/* 81 */ MCD_OPC_FilterValue, 4, 3, 7, // Skip to: 1880 +/* 85 */ MCD_OPC_Decode, 241, 6, 114, // Opcode: QVFXXMADD +/* 89 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 112 +/* 93 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 96 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 104 +/* 100 */ MCD_OPC_Decode, 240, 6, 114, // Opcode: QVFXXCPNMADDS +/* 104 */ MCD_OPC_FilterValue, 4, 236, 6, // Skip to: 1880 +/* 108 */ MCD_OPC_Decode, 239, 6, 114, // Opcode: QVFXXCPNMADD +/* 112 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 132 +/* 116 */ MCD_OPC_CheckField, 26, 6, 4, 222, 6, // Skip to: 1880 +/* 122 */ MCD_OPC_CheckField, 6, 1, 0, 216, 6, // Skip to: 1880 +/* 128 */ MCD_OPC_Decode, 183, 6, 115, // Opcode: QVFLOGICALb +/* 132 */ MCD_OPC_FilterValue, 10, 180, 0, // Skip to: 316 +/* 136 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... +/* 139 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 153 +/* 143 */ MCD_OPC_CheckField, 26, 6, 4, 195, 6, // Skip to: 1880 +/* 149 */ MCD_OPC_Decode, 146, 6, 116, // Opcode: QVALIGNI +/* 153 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 173 +/* 157 */ MCD_OPC_CheckField, 26, 6, 4, 181, 6, // Skip to: 1880 +/* 163 */ MCD_OPC_CheckField, 11, 5, 0, 175, 6, // Skip to: 1880 +/* 169 */ MCD_OPC_Decode, 149, 6, 117, // Opcode: QVESPLATI +/* 173 */ MCD_OPC_FilterValue, 4, 34, 0, // Skip to: 211 +/* 177 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 180 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 188 +/* 184 */ MCD_OPC_Decode, 245, 6, 118, // Opcode: QVGPCI +/* 188 */ MCD_OPC_FilterValue, 31, 152, 6, // Skip to: 1880 +/* 192 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 195 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 203 +/* 199 */ MCD_OPC_Decode, 161, 7, 119, // Opcode: QVSTFCSXI +/* 203 */ MCD_OPC_FilterValue, 2, 137, 6, // Skip to: 1880 +/* 207 */ MCD_OPC_Decode, 182, 7, 119, // Opcode: QVSTFSXI +/* 211 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 246 +/* 215 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 218 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 232 +/* 222 */ MCD_OPC_CheckField, 26, 6, 31, 116, 6, // Skip to: 1880 +/* 228 */ MCD_OPC_Decode, 157, 7, 119, // Opcode: QVSTFCSUXI +/* 232 */ MCD_OPC_FilterValue, 2, 108, 6, // Skip to: 1880 +/* 236 */ MCD_OPC_CheckField, 26, 6, 31, 102, 6, // Skip to: 1880 +/* 242 */ MCD_OPC_Decode, 177, 7, 119, // Opcode: QVSTFSUXI +/* 246 */ MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 281 +/* 250 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 253 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 267 +/* 257 */ MCD_OPC_CheckField, 26, 6, 31, 81, 6, // Skip to: 1880 +/* 263 */ MCD_OPC_Decode, 153, 7, 119, // Opcode: QVSTFCDXI +/* 267 */ MCD_OPC_FilterValue, 2, 73, 6, // Skip to: 1880 +/* 271 */ MCD_OPC_CheckField, 26, 6, 31, 67, 6, // Skip to: 1880 +/* 277 */ MCD_OPC_Decode, 170, 7, 119, // Opcode: QVSTFDXI +/* 281 */ MCD_OPC_FilterValue, 7, 59, 6, // Skip to: 1880 +/* 285 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 288 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 302 +/* 292 */ MCD_OPC_CheckField, 26, 6, 31, 46, 6, // Skip to: 1880 +/* 298 */ MCD_OPC_Decode, 149, 7, 119, // Opcode: QVSTFCDUXI +/* 302 */ MCD_OPC_FilterValue, 2, 38, 6, // Skip to: 1880 +/* 306 */ MCD_OPC_CheckField, 26, 6, 31, 32, 6, // Skip to: 1880 +/* 312 */ MCD_OPC_Decode, 166, 7, 119, // Opcode: QVSTFDUXI +/* 316 */ MCD_OPC_FilterValue, 11, 115, 0, // Skip to: 435 +/* 320 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 323 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 337 +/* 327 */ MCD_OPC_CheckField, 26, 6, 31, 11, 6, // Skip to: 1880 +/* 333 */ MCD_OPC_Decode, 162, 7, 119, // Opcode: QVSTFCSXIA +/* 337 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 351 +/* 341 */ MCD_OPC_CheckField, 26, 6, 31, 253, 5, // Skip to: 1880 +/* 347 */ MCD_OPC_Decode, 158, 7, 119, // Opcode: QVSTFCSUXIA +/* 351 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 365 +/* 355 */ MCD_OPC_CheckField, 26, 6, 31, 239, 5, // Skip to: 1880 +/* 361 */ MCD_OPC_Decode, 154, 7, 119, // Opcode: QVSTFCDXIA +/* 365 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 379 +/* 369 */ MCD_OPC_CheckField, 26, 6, 31, 225, 5, // Skip to: 1880 +/* 375 */ MCD_OPC_Decode, 150, 7, 119, // Opcode: QVSTFCDUXIA +/* 379 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 393 +/* 383 */ MCD_OPC_CheckField, 26, 6, 31, 211, 5, // Skip to: 1880 +/* 389 */ MCD_OPC_Decode, 183, 7, 119, // Opcode: QVSTFSXIA +/* 393 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 407 +/* 397 */ MCD_OPC_CheckField, 26, 6, 31, 197, 5, // Skip to: 1880 +/* 403 */ MCD_OPC_Decode, 178, 7, 119, // Opcode: QVSTFSUXIA +/* 407 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 421 +/* 411 */ MCD_OPC_CheckField, 26, 6, 31, 183, 5, // Skip to: 1880 +/* 417 */ MCD_OPC_Decode, 171, 7, 119, // Opcode: QVSTFDXIA +/* 421 */ MCD_OPC_FilterValue, 23, 175, 5, // Skip to: 1880 +/* 425 */ MCD_OPC_CheckField, 26, 6, 31, 169, 5, // Skip to: 1880 +/* 431 */ MCD_OPC_Decode, 167, 7, 119, // Opcode: QVSTFDUXIA +/* 435 */ MCD_OPC_FilterValue, 12, 50, 0, // Skip to: 489 +/* 439 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 442 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 450 +/* 446 */ MCD_OPC_Decode, 207, 6, 114, // Opcode: QVFPERM +/* 450 */ MCD_OPC_FilterValue, 31, 146, 5, // Skip to: 1880 +/* 454 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 457 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 465 +/* 461 */ MCD_OPC_Decode, 146, 7, 119, // Opcode: QVLPCRSX +/* 465 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 473 +/* 469 */ MCD_OPC_Decode, 145, 7, 119, // Opcode: QVLPCRDX +/* 473 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 481 +/* 477 */ MCD_OPC_Decode, 143, 7, 119, // Opcode: QVLPCLSX +/* 481 */ MCD_OPC_FilterValue, 18, 115, 5, // Skip to: 1880 +/* 485 */ MCD_OPC_Decode, 142, 7, 119, // Opcode: QVLPCLDX +/* 489 */ MCD_OPC_FilterValue, 14, 13, 1, // Skip to: 762 +/* 493 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 496 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 510 +/* 500 */ MCD_OPC_CheckField, 26, 6, 31, 94, 5, // Skip to: 1880 +/* 506 */ MCD_OPC_Decode, 252, 6, 119, // Opcode: QVLFCSX +/* 510 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 524 +/* 514 */ MCD_OPC_CheckField, 26, 6, 31, 80, 5, // Skip to: 1880 +/* 520 */ MCD_OPC_Decode, 250, 6, 119, // Opcode: QVLFCSUX +/* 524 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 538 +/* 528 */ MCD_OPC_CheckField, 26, 6, 31, 66, 5, // Skip to: 1880 +/* 534 */ MCD_OPC_Decode, 248, 6, 119, // Opcode: QVLFCDX +/* 538 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 552 +/* 542 */ MCD_OPC_CheckField, 26, 6, 31, 52, 5, // Skip to: 1880 +/* 548 */ MCD_OPC_Decode, 246, 6, 119, // Opcode: QVLFCDUX +/* 552 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 566 +/* 556 */ MCD_OPC_CheckField, 26, 6, 31, 38, 5, // Skip to: 1880 +/* 562 */ MCD_OPC_Decode, 159, 7, 119, // Opcode: QVSTFCSX +/* 566 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 580 +/* 570 */ MCD_OPC_CheckField, 26, 6, 31, 24, 5, // Skip to: 1880 +/* 576 */ MCD_OPC_Decode, 155, 7, 119, // Opcode: QVSTFCSUX +/* 580 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 594 +/* 584 */ MCD_OPC_CheckField, 26, 6, 31, 10, 5, // Skip to: 1880 +/* 590 */ MCD_OPC_Decode, 151, 7, 119, // Opcode: QVSTFCDX +/* 594 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 608 +/* 598 */ MCD_OPC_CheckField, 26, 6, 31, 252, 4, // Skip to: 1880 +/* 604 */ MCD_OPC_Decode, 147, 7, 119, // Opcode: QVSTFCDUX +/* 608 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 622 +/* 612 */ MCD_OPC_CheckField, 26, 6, 31, 238, 4, // Skip to: 1880 +/* 618 */ MCD_OPC_Decode, 138, 7, 119, // Opcode: QVLFSX +/* 622 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 636 +/* 626 */ MCD_OPC_CheckField, 26, 6, 31, 224, 4, // Skip to: 1880 +/* 632 */ MCD_OPC_Decode, 136, 7, 120, // Opcode: QVLFSUX +/* 636 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 650 +/* 640 */ MCD_OPC_CheckField, 26, 6, 31, 210, 4, // Skip to: 1880 +/* 646 */ MCD_OPC_Decode, 129, 7, 119, // Opcode: QVLFDX +/* 650 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 664 +/* 654 */ MCD_OPC_CheckField, 26, 6, 31, 196, 4, // Skip to: 1880 +/* 660 */ MCD_OPC_Decode, 255, 6, 121, // Opcode: QVLFDUX +/* 664 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 678 +/* 668 */ MCD_OPC_CheckField, 26, 6, 31, 182, 4, // Skip to: 1880 +/* 674 */ MCD_OPC_Decode, 180, 7, 119, // Opcode: QVSTFSX +/* 678 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 692 +/* 682 */ MCD_OPC_CheckField, 26, 6, 31, 168, 4, // Skip to: 1880 +/* 688 */ MCD_OPC_Decode, 175, 7, 122, // Opcode: QVSTFSUX +/* 692 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 706 +/* 696 */ MCD_OPC_CheckField, 26, 6, 31, 154, 4, // Skip to: 1880 +/* 702 */ MCD_OPC_Decode, 168, 7, 119, // Opcode: QVSTFDX +/* 706 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 720 +/* 710 */ MCD_OPC_CheckField, 26, 6, 31, 140, 4, // Skip to: 1880 +/* 716 */ MCD_OPC_Decode, 164, 7, 123, // Opcode: QVSTFDUX +/* 720 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 734 +/* 724 */ MCD_OPC_CheckField, 26, 6, 31, 126, 4, // Skip to: 1880 +/* 730 */ MCD_OPC_Decode, 134, 7, 119, // Opcode: QVLFIWZX +/* 734 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 748 +/* 738 */ MCD_OPC_CheckField, 26, 6, 31, 112, 4, // Skip to: 1880 +/* 744 */ MCD_OPC_Decode, 132, 7, 119, // Opcode: QVLFIWAX +/* 748 */ MCD_OPC_FilterValue, 30, 104, 4, // Skip to: 1880 +/* 752 */ MCD_OPC_CheckField, 26, 6, 31, 98, 4, // Skip to: 1880 +/* 758 */ MCD_OPC_Decode, 173, 7, 119, // Opcode: QVSTFIWX +/* 762 */ MCD_OPC_FilterValue, 15, 13, 1, // Skip to: 1035 +/* 766 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 769 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 783 +/* 773 */ MCD_OPC_CheckField, 26, 6, 31, 77, 4, // Skip to: 1880 +/* 779 */ MCD_OPC_Decode, 253, 6, 119, // Opcode: QVLFCSXA +/* 783 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 797 +/* 787 */ MCD_OPC_CheckField, 26, 6, 31, 63, 4, // Skip to: 1880 +/* 793 */ MCD_OPC_Decode, 251, 6, 119, // Opcode: QVLFCSUXA +/* 797 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 811 +/* 801 */ MCD_OPC_CheckField, 26, 6, 31, 49, 4, // Skip to: 1880 +/* 807 */ MCD_OPC_Decode, 249, 6, 119, // Opcode: QVLFCDXA +/* 811 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 825 +/* 815 */ MCD_OPC_CheckField, 26, 6, 31, 35, 4, // Skip to: 1880 +/* 821 */ MCD_OPC_Decode, 247, 6, 119, // Opcode: QVLFCDUXA +/* 825 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 839 +/* 829 */ MCD_OPC_CheckField, 26, 6, 31, 21, 4, // Skip to: 1880 +/* 835 */ MCD_OPC_Decode, 160, 7, 119, // Opcode: QVSTFCSXA +/* 839 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 853 +/* 843 */ MCD_OPC_CheckField, 26, 6, 31, 7, 4, // Skip to: 1880 +/* 849 */ MCD_OPC_Decode, 156, 7, 119, // Opcode: QVSTFCSUXA +/* 853 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 867 +/* 857 */ MCD_OPC_CheckField, 26, 6, 31, 249, 3, // Skip to: 1880 +/* 863 */ MCD_OPC_Decode, 152, 7, 119, // Opcode: QVSTFCDXA +/* 867 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 881 +/* 871 */ MCD_OPC_CheckField, 26, 6, 31, 235, 3, // Skip to: 1880 +/* 877 */ MCD_OPC_Decode, 148, 7, 119, // Opcode: QVSTFCDUXA +/* 881 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 895 +/* 885 */ MCD_OPC_CheckField, 26, 6, 31, 221, 3, // Skip to: 1880 +/* 891 */ MCD_OPC_Decode, 139, 7, 119, // Opcode: QVLFSXA +/* 895 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 909 +/* 899 */ MCD_OPC_CheckField, 26, 6, 31, 207, 3, // Skip to: 1880 +/* 905 */ MCD_OPC_Decode, 137, 7, 119, // Opcode: QVLFSUXA +/* 909 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 923 +/* 913 */ MCD_OPC_CheckField, 26, 6, 31, 193, 3, // Skip to: 1880 +/* 919 */ MCD_OPC_Decode, 130, 7, 119, // Opcode: QVLFDXA +/* 923 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 937 +/* 927 */ MCD_OPC_CheckField, 26, 6, 31, 179, 3, // Skip to: 1880 +/* 933 */ MCD_OPC_Decode, 128, 7, 119, // Opcode: QVLFDUXA +/* 937 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 951 +/* 941 */ MCD_OPC_CheckField, 26, 6, 31, 165, 3, // Skip to: 1880 +/* 947 */ MCD_OPC_Decode, 181, 7, 119, // Opcode: QVSTFSXA +/* 951 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 965 +/* 955 */ MCD_OPC_CheckField, 26, 6, 31, 151, 3, // Skip to: 1880 +/* 961 */ MCD_OPC_Decode, 176, 7, 119, // Opcode: QVSTFSUXA +/* 965 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 979 +/* 969 */ MCD_OPC_CheckField, 26, 6, 31, 137, 3, // Skip to: 1880 +/* 975 */ MCD_OPC_Decode, 169, 7, 119, // Opcode: QVSTFDXA +/* 979 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 993 +/* 983 */ MCD_OPC_CheckField, 26, 6, 31, 123, 3, // Skip to: 1880 +/* 989 */ MCD_OPC_Decode, 165, 7, 119, // Opcode: QVSTFDUXA +/* 993 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 1007 +/* 997 */ MCD_OPC_CheckField, 26, 6, 31, 109, 3, // Skip to: 1880 +/* 1003 */ MCD_OPC_Decode, 135, 7, 119, // Opcode: QVLFIWZXA +/* 1007 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 1021 +/* 1011 */ MCD_OPC_CheckField, 26, 6, 31, 95, 3, // Skip to: 1880 +/* 1017 */ MCD_OPC_Decode, 133, 7, 119, // Opcode: QVLFIWAXA +/* 1021 */ MCD_OPC_FilterValue, 30, 87, 3, // Skip to: 1880 +/* 1025 */ MCD_OPC_CheckField, 26, 6, 31, 81, 3, // Skip to: 1880 +/* 1031 */ MCD_OPC_Decode, 174, 7, 119, // Opcode: QVSTFIWXA +/* 1035 */ MCD_OPC_FilterValue, 16, 177, 0, // Skip to: 1216 +/* 1039 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1042 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1056 +/* 1046 */ MCD_OPC_CheckField, 26, 6, 4, 60, 3, // Skip to: 1880 +/* 1052 */ MCD_OPC_Decode, 171, 6, 124, // Opcode: QVFCPSGN +/* 1056 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 1076 +/* 1060 */ MCD_OPC_CheckField, 26, 6, 4, 46, 3, // Skip to: 1880 +/* 1066 */ MCD_OPC_CheckField, 16, 5, 0, 40, 3, // Skip to: 1880 +/* 1072 */ MCD_OPC_Decode, 199, 6, 125, // Opcode: QVFNEG +/* 1076 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 1096 +/* 1080 */ MCD_OPC_CheckField, 26, 6, 4, 26, 3, // Skip to: 1880 +/* 1086 */ MCD_OPC_CheckField, 16, 5, 0, 20, 3, // Skip to: 1880 +/* 1092 */ MCD_OPC_Decode, 188, 6, 125, // Opcode: QVFMR +/* 1096 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 1116 +/* 1100 */ MCD_OPC_CheckField, 26, 6, 4, 6, 3, // Skip to: 1880 +/* 1106 */ MCD_OPC_CheckField, 16, 5, 0, 0, 3, // Skip to: 1880 +/* 1112 */ MCD_OPC_Decode, 197, 6, 125, // Opcode: QVFNABS +/* 1116 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 1136 +/* 1120 */ MCD_OPC_CheckField, 26, 6, 4, 242, 2, // Skip to: 1880 +/* 1126 */ MCD_OPC_CheckField, 16, 5, 0, 236, 2, // Skip to: 1880 +/* 1132 */ MCD_OPC_Decode, 152, 6, 125, // Opcode: QVFABS +/* 1136 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 1156 +/* 1140 */ MCD_OPC_CheckField, 26, 6, 4, 222, 2, // Skip to: 1880 +/* 1146 */ MCD_OPC_CheckField, 16, 5, 0, 216, 2, // Skip to: 1880 +/* 1152 */ MCD_OPC_Decode, 214, 6, 125, // Opcode: QVFRIN +/* 1156 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 1176 +/* 1160 */ MCD_OPC_CheckField, 26, 6, 4, 202, 2, // Skip to: 1880 +/* 1166 */ MCD_OPC_CheckField, 16, 5, 0, 196, 2, // Skip to: 1880 +/* 1172 */ MCD_OPC_Decode, 218, 6, 125, // Opcode: QVFRIZ +/* 1176 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 1196 +/* 1180 */ MCD_OPC_CheckField, 26, 6, 4, 182, 2, // Skip to: 1880 +/* 1186 */ MCD_OPC_CheckField, 16, 5, 0, 176, 2, // Skip to: 1880 +/* 1192 */ MCD_OPC_Decode, 216, 6, 125, // Opcode: QVFRIP +/* 1196 */ MCD_OPC_FilterValue, 15, 168, 2, // Skip to: 1880 +/* 1200 */ MCD_OPC_CheckField, 26, 6, 4, 162, 2, // Skip to: 1880 +/* 1206 */ MCD_OPC_CheckField, 16, 5, 0, 156, 2, // Skip to: 1880 +/* 1212 */ MCD_OPC_Decode, 212, 6, 125, // Opcode: QVFRIM +/* 1216 */ MCD_OPC_FilterValue, 18, 19, 0, // Skip to: 1239 +/* 1220 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1223 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1231 +/* 1227 */ MCD_OPC_Decode, 236, 6, 114, // Opcode: QVFXMADDS +/* 1231 */ MCD_OPC_FilterValue, 4, 133, 2, // Skip to: 1880 +/* 1235 */ MCD_OPC_Decode, 235, 6, 114, // Opcode: QVFXMADD +/* 1239 */ MCD_OPC_FilterValue, 22, 19, 0, // Skip to: 1262 +/* 1243 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1246 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1254 +/* 1250 */ MCD_OPC_Decode, 244, 6, 114, // Opcode: QVFXXNPMADDS +/* 1254 */ MCD_OPC_FilterValue, 4, 110, 2, // Skip to: 1880 +/* 1258 */ MCD_OPC_Decode, 243, 6, 114, // Opcode: QVFXXNPMADD +/* 1262 */ MCD_OPC_FilterValue, 24, 22, 0, // Skip to: 1288 +/* 1266 */ MCD_OPC_CheckField, 26, 6, 4, 96, 2, // Skip to: 1880 +/* 1272 */ MCD_OPC_CheckField, 16, 5, 0, 90, 2, // Skip to: 1880 +/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 84, 2, // Skip to: 1880 +/* 1284 */ MCD_OPC_Decode, 221, 6, 126, // Opcode: QVFRSPs +/* 1288 */ MCD_OPC_FilterValue, 28, 153, 0, // Skip to: 1445 +/* 1292 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1295 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 1315 +/* 1299 */ MCD_OPC_CheckField, 26, 6, 4, 63, 2, // Skip to: 1880 +/* 1305 */ MCD_OPC_CheckField, 16, 5, 0, 57, 2, // Skip to: 1880 +/* 1311 */ MCD_OPC_Decode, 178, 6, 125, // Opcode: QVFCTIW +/* 1315 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 1335 +/* 1319 */ MCD_OPC_CheckField, 26, 6, 4, 43, 2, // Skip to: 1880 +/* 1325 */ MCD_OPC_CheckField, 16, 5, 0, 37, 2, // Skip to: 1880 +/* 1331 */ MCD_OPC_Decode, 179, 6, 125, // Opcode: QVFCTIWU +/* 1335 */ MCD_OPC_FilterValue, 25, 16, 0, // Skip to: 1355 +/* 1339 */ MCD_OPC_CheckField, 26, 6, 4, 23, 2, // Skip to: 1880 +/* 1345 */ MCD_OPC_CheckField, 16, 5, 0, 17, 2, // Skip to: 1880 +/* 1351 */ MCD_OPC_Decode, 173, 6, 125, // Opcode: QVFCTID +/* 1355 */ MCD_OPC_FilterValue, 26, 31, 0, // Skip to: 1390 +/* 1359 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1362 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1376 +/* 1366 */ MCD_OPC_CheckField, 16, 5, 0, 252, 1, // Skip to: 1880 +/* 1372 */ MCD_OPC_Decode, 158, 6, 125, // Opcode: QVFCFIDS +/* 1376 */ MCD_OPC_FilterValue, 4, 244, 1, // Skip to: 1880 +/* 1380 */ MCD_OPC_CheckField, 16, 5, 0, 238, 1, // Skip to: 1880 +/* 1386 */ MCD_OPC_Decode, 157, 6, 125, // Opcode: QVFCFID +/* 1390 */ MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 1410 +/* 1394 */ MCD_OPC_CheckField, 26, 6, 4, 224, 1, // Skip to: 1880 +/* 1400 */ MCD_OPC_CheckField, 16, 5, 0, 218, 1, // Skip to: 1880 +/* 1406 */ MCD_OPC_Decode, 174, 6, 125, // Opcode: QVFCTIDU +/* 1410 */ MCD_OPC_FilterValue, 30, 210, 1, // Skip to: 1880 +/* 1414 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1417 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1431 +/* 1421 */ MCD_OPC_CheckField, 16, 5, 0, 197, 1, // Skip to: 1880 +/* 1427 */ MCD_OPC_Decode, 160, 6, 125, // Opcode: QVFCFIDUS +/* 1431 */ MCD_OPC_FilterValue, 4, 189, 1, // Skip to: 1880 +/* 1435 */ MCD_OPC_CheckField, 16, 5, 0, 183, 1, // Skip to: 1880 +/* 1441 */ MCD_OPC_Decode, 159, 6, 125, // Opcode: QVFCFIDU +/* 1445 */ MCD_OPC_FilterValue, 30, 83, 0, // Skip to: 1532 +/* 1449 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 1452 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 1472 +/* 1456 */ MCD_OPC_CheckField, 26, 6, 4, 162, 1, // Skip to: 1880 +/* 1462 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 1880 +/* 1468 */ MCD_OPC_Decode, 181, 6, 125, // Opcode: QVFCTIWZ +/* 1472 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 1492 +/* 1476 */ MCD_OPC_CheckField, 26, 6, 4, 142, 1, // Skip to: 1880 +/* 1482 */ MCD_OPC_CheckField, 16, 5, 0, 136, 1, // Skip to: 1880 +/* 1488 */ MCD_OPC_Decode, 180, 6, 125, // Opcode: QVFCTIWUZ +/* 1492 */ MCD_OPC_FilterValue, 25, 16, 0, // Skip to: 1512 +/* 1496 */ MCD_OPC_CheckField, 26, 6, 4, 122, 1, // Skip to: 1880 +/* 1502 */ MCD_OPC_CheckField, 16, 5, 0, 116, 1, // Skip to: 1880 +/* 1508 */ MCD_OPC_Decode, 176, 6, 125, // Opcode: QVFCTIDZ +/* 1512 */ MCD_OPC_FilterValue, 29, 108, 1, // Skip to: 1880 +/* 1516 */ MCD_OPC_CheckField, 26, 6, 4, 102, 1, // Skip to: 1880 +/* 1522 */ MCD_OPC_CheckField, 16, 5, 0, 96, 1, // Skip to: 1880 +/* 1528 */ MCD_OPC_Decode, 175, 6, 125, // Opcode: QVFCTIDUZ +/* 1532 */ MCD_OPC_FilterValue, 34, 31, 0, // Skip to: 1567 +/* 1536 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1539 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1553 +/* 1543 */ MCD_OPC_CheckField, 11, 5, 0, 75, 1, // Skip to: 1880 +/* 1549 */ MCD_OPC_Decode, 238, 6, 127, // Opcode: QVFXMULS +/* 1553 */ MCD_OPC_FilterValue, 4, 67, 1, // Skip to: 1880 +/* 1557 */ MCD_OPC_CheckField, 11, 5, 0, 61, 1, // Skip to: 1880 +/* 1563 */ MCD_OPC_Decode, 237, 6, 127, // Opcode: QVFXMUL +/* 1567 */ MCD_OPC_FilterValue, 40, 32, 0, // Skip to: 1603 +/* 1571 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1574 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 1589 +/* 1578 */ MCD_OPC_CheckField, 6, 5, 0, 40, 1, // Skip to: 1880 +/* 1584 */ MCD_OPC_Decode, 231, 6, 128, 1, // Opcode: QVFSUBSs +/* 1589 */ MCD_OPC_FilterValue, 4, 31, 1, // Skip to: 1880 +/* 1593 */ MCD_OPC_CheckField, 6, 5, 0, 25, 1, // Skip to: 1880 +/* 1599 */ MCD_OPC_Decode, 229, 6, 124, // Opcode: QVFSUB +/* 1603 */ MCD_OPC_FilterValue, 42, 32, 0, // Skip to: 1639 +/* 1607 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1610 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 1625 +/* 1614 */ MCD_OPC_CheckField, 6, 5, 0, 4, 1, // Skip to: 1880 +/* 1620 */ MCD_OPC_Decode, 156, 6, 128, 1, // Opcode: QVFADDSs +/* 1625 */ MCD_OPC_FilterValue, 4, 251, 0, // Skip to: 1880 +/* 1629 */ MCD_OPC_CheckField, 6, 5, 0, 245, 0, // Skip to: 1880 +/* 1635 */ MCD_OPC_Decode, 154, 6, 124, // Opcode: QVFADD +/* 1639 */ MCD_OPC_FilterValue, 46, 11, 0, // Skip to: 1654 +/* 1643 */ MCD_OPC_CheckField, 26, 6, 4, 231, 0, // Skip to: 1880 +/* 1649 */ MCD_OPC_Decode, 226, 6, 129, 1, // Opcode: QVFSELb +/* 1654 */ MCD_OPC_FilterValue, 48, 43, 0, // Skip to: 1701 +/* 1658 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1661 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 1681 +/* 1665 */ MCD_OPC_CheckField, 16, 5, 0, 209, 0, // Skip to: 1880 +/* 1671 */ MCD_OPC_CheckField, 6, 5, 0, 203, 0, // Skip to: 1880 +/* 1677 */ MCD_OPC_Decode, 210, 6, 125, // Opcode: QVFRES +/* 1681 */ MCD_OPC_FilterValue, 4, 195, 0, // Skip to: 1880 +/* 1685 */ MCD_OPC_CheckField, 16, 5, 0, 189, 0, // Skip to: 1880 +/* 1691 */ MCD_OPC_CheckField, 6, 5, 0, 183, 0, // Skip to: 1880 +/* 1697 */ MCD_OPC_Decode, 209, 6, 125, // Opcode: QVFRE +/* 1701 */ MCD_OPC_FilterValue, 50, 32, 0, // Skip to: 1737 +/* 1705 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1708 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 1723 +/* 1712 */ MCD_OPC_CheckField, 11, 5, 0, 162, 0, // Skip to: 1880 +/* 1718 */ MCD_OPC_Decode, 196, 6, 130, 1, // Opcode: QVFMULSs +/* 1723 */ MCD_OPC_FilterValue, 4, 153, 0, // Skip to: 1880 +/* 1727 */ MCD_OPC_CheckField, 11, 5, 0, 147, 0, // Skip to: 1880 +/* 1733 */ MCD_OPC_Decode, 194, 6, 127, // Opcode: QVFMUL +/* 1737 */ MCD_OPC_FilterValue, 52, 43, 0, // Skip to: 1784 +/* 1741 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1744 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 1764 +/* 1748 */ MCD_OPC_CheckField, 16, 5, 0, 126, 0, // Skip to: 1880 +/* 1754 */ MCD_OPC_CheckField, 6, 5, 0, 120, 0, // Skip to: 1880 +/* 1760 */ MCD_OPC_Decode, 223, 6, 125, // Opcode: QVFRSQRTES +/* 1764 */ MCD_OPC_FilterValue, 4, 112, 0, // Skip to: 1880 +/* 1768 */ MCD_OPC_CheckField, 16, 5, 0, 106, 0, // Skip to: 1880 +/* 1774 */ MCD_OPC_CheckField, 6, 5, 0, 100, 0, // Skip to: 1880 +/* 1780 */ MCD_OPC_Decode, 222, 6, 125, // Opcode: QVFRSQRTE +/* 1784 */ MCD_OPC_FilterValue, 56, 20, 0, // Skip to: 1808 +/* 1788 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1791 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 1800 +/* 1795 */ MCD_OPC_Decode, 193, 6, 131, 1, // Opcode: QVFMSUBSs +/* 1800 */ MCD_OPC_FilterValue, 4, 76, 0, // Skip to: 1880 +/* 1804 */ MCD_OPC_Decode, 191, 6, 114, // Opcode: QVFMSUB +/* 1808 */ MCD_OPC_FilterValue, 58, 20, 0, // Skip to: 1832 +/* 1812 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1815 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 1824 +/* 1819 */ MCD_OPC_Decode, 187, 6, 131, 1, // Opcode: QVFMADDSs +/* 1824 */ MCD_OPC_FilterValue, 4, 52, 0, // Skip to: 1880 +/* 1828 */ MCD_OPC_Decode, 185, 6, 114, // Opcode: QVFMADD +/* 1832 */ MCD_OPC_FilterValue, 60, 20, 0, // Skip to: 1856 +/* 1836 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1839 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 1848 +/* 1843 */ MCD_OPC_Decode, 206, 6, 131, 1, // Opcode: QVFNMSUBSs +/* 1848 */ MCD_OPC_FilterValue, 4, 28, 0, // Skip to: 1880 +/* 1852 */ MCD_OPC_Decode, 204, 6, 114, // Opcode: QVFNMSUB +/* 1856 */ MCD_OPC_FilterValue, 62, 20, 0, // Skip to: 1880 +/* 1860 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... +/* 1863 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 1872 +/* 1867 */ MCD_OPC_Decode, 203, 6, 131, 1, // Opcode: QVFNMADDSs +/* 1872 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1880 +/* 1876 */ MCD_OPC_Decode, 201, 6, 114, // Opcode: QVFNMADD +/* 1880 */ MCD_OPC_Fail, + 0 +}; +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + //llvm_unreachable("Invalid index!"); + return true; +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 4); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 12: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 19: \ + tmp = fieldname(insn, 2, 14); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 20: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 2, 14); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 21: \ + tmp = fieldname(insn, 5, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 22: \ + tmp = fieldname(insn, 2, 24); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 23: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 25: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 1) << 5; \ + tmp |= fieldname(insn, 6, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 1) << 5; \ + tmp |= fieldname(insn, 6, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 1) << 5; \ + tmp |= fieldname(insn, 6, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 15, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 37: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 5) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 38: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 39: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 40: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 41: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 42: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 43: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 47: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + tmp = fieldname(insn, 12, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + tmp = fieldname(insn, 12, 8); \ + if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 8); \ + if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 52: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 53: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 54: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 5) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 57: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 58: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 59: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 60: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + tmp = fieldname(insn, 21, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 65: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 66: \ + tmp = fieldname(insn, 21, 2); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 69: \ + tmp = fieldname(insn, 21, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 70: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 71: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 72: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 73: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 74: \ + tmp = fieldname(insn, 21, 2); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 75: \ + tmp = fieldname(insn, 21, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 76: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 77: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 78: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 79: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 82: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 21); \ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 83: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 21); \ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 84: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 21); \ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 85: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 2, 19); \ + if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 86: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 87: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 88: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 89: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 90: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 91: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 92: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 93: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 94: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 95: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 96: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 97: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 98: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 99: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 100: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 101: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 102: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 103: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 1) << 5; \ + tmp |= fieldname(insn, 21, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 1) << 5; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 5; \ + tmp |= fieldname(insn, 6, 5) << 0; \ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 104: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 105: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 106: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 107: \ + tmp = fieldname(insn, 17, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 108: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 109: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 110: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 111: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 112: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 113: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 114: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 115: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 4); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 116: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 117: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 118: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 9, 12); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 119: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 120: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 121: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 122: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 123: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 124: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 125: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 126: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 127: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 128: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 129: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 130: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 131: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +// DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +//DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) + +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenInstrInfo.inc new file mode 100644 index 0000000..3cfce3c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenInstrInfo.inc @@ -0,0 +1,1538 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + PPC_PHI = 0, + PPC_INLINEASM = 1, + PPC_CFI_INSTRUCTION = 2, + PPC_EH_LABEL = 3, + PPC_GC_LABEL = 4, + PPC_KILL = 5, + PPC_EXTRACT_SUBREG = 6, + PPC_INSERT_SUBREG = 7, + PPC_IMPLICIT_DEF = 8, + PPC_SUBREG_TO_REG = 9, + PPC_COPY_TO_REGCLASS = 10, + PPC_DBG_VALUE = 11, + PPC_REG_SEQUENCE = 12, + PPC_COPY = 13, + PPC_BUNDLE = 14, + PPC_LIFETIME_START = 15, + PPC_LIFETIME_END = 16, + PPC_STACKMAP = 17, + PPC_PATCHPOINT = 18, + PPC_LOAD_STACK_GUARD = 19, + PPC_STATEPOINT = 20, + PPC_FRAME_ALLOC = 21, + PPC_ADD4 = 22, + PPC_ADD4TLS = 23, + PPC_ADD4o = 24, + PPC_ADD8 = 25, + PPC_ADD8TLS = 26, + PPC_ADD8TLS_ = 27, + PPC_ADD8o = 28, + PPC_ADDC = 29, + PPC_ADDC8 = 30, + PPC_ADDC8o = 31, + PPC_ADDCo = 32, + PPC_ADDE = 33, + PPC_ADDE8 = 34, + PPC_ADDE8o = 35, + PPC_ADDEo = 36, + PPC_ADDI = 37, + PPC_ADDI8 = 38, + PPC_ADDIC = 39, + PPC_ADDIC8 = 40, + PPC_ADDICo = 41, + PPC_ADDIS = 42, + PPC_ADDIS8 = 43, + PPC_ADDISdtprelHA = 44, + PPC_ADDISdtprelHA32 = 45, + PPC_ADDISgotTprelHA = 46, + PPC_ADDIStlsgdHA = 47, + PPC_ADDIStlsldHA = 48, + PPC_ADDIStocHA = 49, + PPC_ADDIdtprelL = 50, + PPC_ADDIdtprelL32 = 51, + PPC_ADDItlsgdL = 52, + PPC_ADDItlsgdL32 = 53, + PPC_ADDItlsgdLADDR = 54, + PPC_ADDItlsgdLADDR32 = 55, + PPC_ADDItlsldL = 56, + PPC_ADDItlsldL32 = 57, + PPC_ADDItlsldLADDR = 58, + PPC_ADDItlsldLADDR32 = 59, + PPC_ADDItocL = 60, + PPC_ADDME = 61, + PPC_ADDME8 = 62, + PPC_ADDME8o = 63, + PPC_ADDMEo = 64, + PPC_ADDZE = 65, + PPC_ADDZE8 = 66, + PPC_ADDZE8o = 67, + PPC_ADDZEo = 68, + PPC_ADJCALLSTACKDOWN = 69, + PPC_ADJCALLSTACKUP = 70, + PPC_AND = 71, + PPC_AND8 = 72, + PPC_AND8o = 73, + PPC_ANDC = 74, + PPC_ANDC8 = 75, + PPC_ANDC8o = 76, + PPC_ANDCo = 77, + PPC_ANDISo = 78, + PPC_ANDISo8 = 79, + PPC_ANDIo = 80, + PPC_ANDIo8 = 81, + PPC_ANDIo_1_EQ_BIT = 82, + PPC_ANDIo_1_EQ_BIT8 = 83, + PPC_ANDIo_1_GT_BIT = 84, + PPC_ANDIo_1_GT_BIT8 = 85, + PPC_ANDo = 86, + PPC_ATOMIC_CMP_SWAP_I16 = 87, + PPC_ATOMIC_CMP_SWAP_I32 = 88, + PPC_ATOMIC_CMP_SWAP_I64 = 89, + PPC_ATOMIC_CMP_SWAP_I8 = 90, + PPC_ATOMIC_LOAD_ADD_I16 = 91, + PPC_ATOMIC_LOAD_ADD_I32 = 92, + PPC_ATOMIC_LOAD_ADD_I64 = 93, + PPC_ATOMIC_LOAD_ADD_I8 = 94, + PPC_ATOMIC_LOAD_AND_I16 = 95, + PPC_ATOMIC_LOAD_AND_I32 = 96, + PPC_ATOMIC_LOAD_AND_I64 = 97, + PPC_ATOMIC_LOAD_AND_I8 = 98, + PPC_ATOMIC_LOAD_NAND_I16 = 99, + PPC_ATOMIC_LOAD_NAND_I32 = 100, + PPC_ATOMIC_LOAD_NAND_I64 = 101, + PPC_ATOMIC_LOAD_NAND_I8 = 102, + PPC_ATOMIC_LOAD_OR_I16 = 103, + PPC_ATOMIC_LOAD_OR_I32 = 104, + PPC_ATOMIC_LOAD_OR_I64 = 105, + PPC_ATOMIC_LOAD_OR_I8 = 106, + PPC_ATOMIC_LOAD_SUB_I16 = 107, + PPC_ATOMIC_LOAD_SUB_I32 = 108, + PPC_ATOMIC_LOAD_SUB_I64 = 109, + PPC_ATOMIC_LOAD_SUB_I8 = 110, + PPC_ATOMIC_LOAD_XOR_I16 = 111, + PPC_ATOMIC_LOAD_XOR_I32 = 112, + PPC_ATOMIC_LOAD_XOR_I64 = 113, + PPC_ATOMIC_LOAD_XOR_I8 = 114, + PPC_ATOMIC_SWAP_I16 = 115, + PPC_ATOMIC_SWAP_I32 = 116, + PPC_ATOMIC_SWAP_I64 = 117, + PPC_ATOMIC_SWAP_I8 = 118, + PPC_ATTN = 119, + PPC_B = 120, + PPC_BA = 121, + PPC_BC = 122, + PPC_BCC = 123, + PPC_BCCA = 124, + PPC_BCCCTR = 125, + PPC_BCCCTR8 = 126, + PPC_BCCCTRL = 127, + PPC_BCCCTRL8 = 128, + PPC_BCCL = 129, + PPC_BCCLA = 130, + PPC_BCCLR = 131, + PPC_BCCLRL = 132, + PPC_BCCTR = 133, + PPC_BCCTR8 = 134, + PPC_BCCTR8n = 135, + PPC_BCCTRL = 136, + PPC_BCCTRL8 = 137, + PPC_BCCTRL8n = 138, + PPC_BCCTRLn = 139, + PPC_BCCTRn = 140, + PPC_BCL = 141, + PPC_BCLR = 142, + PPC_BCLRL = 143, + PPC_BCLRLn = 144, + PPC_BCLRn = 145, + PPC_BCLalways = 146, + PPC_BCLn = 147, + PPC_BCTR = 148, + PPC_BCTR8 = 149, + PPC_BCTRL = 150, + PPC_BCTRL8 = 151, + PPC_BCTRL8_LDinto_toc = 152, + PPC_BCn = 153, + PPC_BDNZ = 154, + PPC_BDNZ8 = 155, + PPC_BDNZA = 156, + PPC_BDNZAm = 157, + PPC_BDNZAp = 158, + PPC_BDNZL = 159, + PPC_BDNZLA = 160, + PPC_BDNZLAm = 161, + PPC_BDNZLAp = 162, + PPC_BDNZLR = 163, + PPC_BDNZLR8 = 164, + PPC_BDNZLRL = 165, + PPC_BDNZLRLm = 166, + PPC_BDNZLRLp = 167, + PPC_BDNZLRm = 168, + PPC_BDNZLRp = 169, + PPC_BDNZLm = 170, + PPC_BDNZLp = 171, + PPC_BDNZm = 172, + PPC_BDNZp = 173, + PPC_BDZ = 174, + PPC_BDZ8 = 175, + PPC_BDZA = 176, + PPC_BDZAm = 177, + PPC_BDZAp = 178, + PPC_BDZL = 179, + PPC_BDZLA = 180, + PPC_BDZLAm = 181, + PPC_BDZLAp = 182, + PPC_BDZLR = 183, + PPC_BDZLR8 = 184, + PPC_BDZLRL = 185, + PPC_BDZLRLm = 186, + PPC_BDZLRLp = 187, + PPC_BDZLRm = 188, + PPC_BDZLRp = 189, + PPC_BDZLm = 190, + PPC_BDZLp = 191, + PPC_BDZm = 192, + PPC_BDZp = 193, + PPC_BL = 194, + PPC_BL8 = 195, + PPC_BL8_NOP = 196, + PPC_BL8_NOP_TLS = 197, + PPC_BL8_TLS = 198, + PPC_BL8_TLS_ = 199, + PPC_BLA = 200, + PPC_BLA8 = 201, + PPC_BLA8_NOP = 202, + PPC_BLR = 203, + PPC_BLR8 = 204, + PPC_BLRL = 205, + PPC_BL_TLS = 206, + PPC_BRINC = 207, + PPC_CLRLSLDI = 208, + PPC_CLRLSLDIo = 209, + PPC_CLRLSLWI = 210, + PPC_CLRLSLWIo = 211, + PPC_CLRRDI = 212, + PPC_CLRRDIo = 213, + PPC_CLRRWI = 214, + PPC_CLRRWIo = 215, + PPC_CMPB = 216, + PPC_CMPB8 = 217, + PPC_CMPD = 218, + PPC_CMPDI = 219, + PPC_CMPLD = 220, + PPC_CMPLDI = 221, + PPC_CMPLW = 222, + PPC_CMPLWI = 223, + PPC_CMPW = 224, + PPC_CMPWI = 225, + PPC_CNTLZD = 226, + PPC_CNTLZDo = 227, + PPC_CNTLZW = 228, + PPC_CNTLZW8 = 229, + PPC_CNTLZW8o = 230, + PPC_CNTLZWo = 231, + PPC_CR6SET = 232, + PPC_CR6UNSET = 233, + PPC_CRAND = 234, + PPC_CRANDC = 235, + PPC_CREQV = 236, + PPC_CRNAND = 237, + PPC_CRNOR = 238, + PPC_CROR = 239, + PPC_CRORC = 240, + PPC_CRSET = 241, + PPC_CRUNSET = 242, + PPC_CRXOR = 243, + PPC_DCBA = 244, + PPC_DCBF = 245, + PPC_DCBI = 246, + PPC_DCBST = 247, + PPC_DCBT = 248, + PPC_DCBTST = 249, + PPC_DCBZ = 250, + PPC_DCBZL = 251, + PPC_DCCCI = 252, + PPC_DIVD = 253, + PPC_DIVDU = 254, + PPC_DIVDUo = 255, + PPC_DIVDo = 256, + PPC_DIVW = 257, + PPC_DIVWU = 258, + PPC_DIVWUo = 259, + PPC_DIVWo = 260, + PPC_DSS = 261, + PPC_DSSALL = 262, + PPC_DST = 263, + PPC_DST64 = 264, + PPC_DSTST = 265, + PPC_DSTST64 = 266, + PPC_DSTSTT = 267, + PPC_DSTSTT64 = 268, + PPC_DSTT = 269, + PPC_DSTT64 = 270, + PPC_DYNALLOC = 271, + PPC_DYNALLOC8 = 272, + PPC_EH_SjLj_LongJmp32 = 273, + PPC_EH_SjLj_LongJmp64 = 274, + PPC_EH_SjLj_SetJmp32 = 275, + PPC_EH_SjLj_SetJmp64 = 276, + PPC_EH_SjLj_Setup = 277, + PPC_EQV = 278, + PPC_EQV8 = 279, + PPC_EQV8o = 280, + PPC_EQVo = 281, + PPC_EVABS = 282, + PPC_EVADDIW = 283, + PPC_EVADDSMIAAW = 284, + PPC_EVADDSSIAAW = 285, + PPC_EVADDUMIAAW = 286, + PPC_EVADDUSIAAW = 287, + PPC_EVADDW = 288, + PPC_EVAND = 289, + PPC_EVANDC = 290, + PPC_EVCMPEQ = 291, + PPC_EVCMPGTS = 292, + PPC_EVCMPGTU = 293, + PPC_EVCMPLTS = 294, + PPC_EVCMPLTU = 295, + PPC_EVCNTLSW = 296, + PPC_EVCNTLZW = 297, + PPC_EVDIVWS = 298, + PPC_EVDIVWU = 299, + PPC_EVEQV = 300, + PPC_EVEXTSB = 301, + PPC_EVEXTSH = 302, + PPC_EVLDD = 303, + PPC_EVLDDX = 304, + PPC_EVLDH = 305, + PPC_EVLDHX = 306, + PPC_EVLDW = 307, + PPC_EVLDWX = 308, + PPC_EVLHHESPLAT = 309, + PPC_EVLHHESPLATX = 310, + PPC_EVLHHOSSPLAT = 311, + PPC_EVLHHOSSPLATX = 312, + PPC_EVLHHOUSPLAT = 313, + PPC_EVLHHOUSPLATX = 314, + PPC_EVLWHE = 315, + PPC_EVLWHEX = 316, + PPC_EVLWHOS = 317, + PPC_EVLWHOSX = 318, + PPC_EVLWHOU = 319, + PPC_EVLWHOUX = 320, + PPC_EVLWHSPLAT = 321, + PPC_EVLWHSPLATX = 322, + PPC_EVLWWSPLAT = 323, + PPC_EVLWWSPLATX = 324, + PPC_EVMERGEHI = 325, + PPC_EVMERGEHILO = 326, + PPC_EVMERGELO = 327, + PPC_EVMERGELOHI = 328, + PPC_EVMHEGSMFAA = 329, + PPC_EVMHEGSMFAN = 330, + PPC_EVMHEGSMIAA = 331, + PPC_EVMHEGSMIAN = 332, + PPC_EVMHEGUMIAA = 333, + PPC_EVMHEGUMIAN = 334, + PPC_EVMHESMF = 335, + PPC_EVMHESMFA = 336, + PPC_EVMHESMFAAW = 337, + PPC_EVMHESMFANW = 338, + PPC_EVMHESMI = 339, + PPC_EVMHESMIA = 340, + PPC_EVMHESMIAAW = 341, + PPC_EVMHESMIANW = 342, + PPC_EVMHESSF = 343, + PPC_EVMHESSFA = 344, + PPC_EVMHESSFAAW = 345, + PPC_EVMHESSFANW = 346, + PPC_EVMHESSIAAW = 347, + PPC_EVMHESSIANW = 348, + PPC_EVMHEUMI = 349, + PPC_EVMHEUMIA = 350, + PPC_EVMHEUMIAAW = 351, + PPC_EVMHEUMIANW = 352, + PPC_EVMHEUSIAAW = 353, + PPC_EVMHEUSIANW = 354, + PPC_EVMHOGSMFAA = 355, + PPC_EVMHOGSMFAN = 356, + PPC_EVMHOGSMIAA = 357, + PPC_EVMHOGSMIAN = 358, + PPC_EVMHOGUMIAA = 359, + PPC_EVMHOGUMIAN = 360, + PPC_EVMHOSMF = 361, + PPC_EVMHOSMFA = 362, + PPC_EVMHOSMFAAW = 363, + PPC_EVMHOSMFANW = 364, + PPC_EVMHOSMI = 365, + PPC_EVMHOSMIA = 366, + PPC_EVMHOSMIAAW = 367, + PPC_EVMHOSMIANW = 368, + PPC_EVMHOSSF = 369, + PPC_EVMHOSSFA = 370, + PPC_EVMHOSSFAAW = 371, + PPC_EVMHOSSFANW = 372, + PPC_EVMHOSSIAAW = 373, + PPC_EVMHOSSIANW = 374, + PPC_EVMHOUMI = 375, + PPC_EVMHOUMIA = 376, + PPC_EVMHOUMIAAW = 377, + PPC_EVMHOUMIANW = 378, + PPC_EVMHOUSIAAW = 379, + PPC_EVMHOUSIANW = 380, + PPC_EVMRA = 381, + PPC_EVMWHSMF = 382, + PPC_EVMWHSMFA = 383, + PPC_EVMWHSMI = 384, + PPC_EVMWHSMIA = 385, + PPC_EVMWHSSF = 386, + PPC_EVMWHSSFA = 387, + PPC_EVMWHUMI = 388, + PPC_EVMWHUMIA = 389, + PPC_EVMWLSMIAAW = 390, + PPC_EVMWLSMIANW = 391, + PPC_EVMWLSSIAAW = 392, + PPC_EVMWLSSIANW = 393, + PPC_EVMWLUMI = 394, + PPC_EVMWLUMIA = 395, + PPC_EVMWLUMIAAW = 396, + PPC_EVMWLUMIANW = 397, + PPC_EVMWLUSIAAW = 398, + PPC_EVMWLUSIANW = 399, + PPC_EVMWSMF = 400, + PPC_EVMWSMFA = 401, + PPC_EVMWSMFAA = 402, + PPC_EVMWSMFAN = 403, + PPC_EVMWSMI = 404, + PPC_EVMWSMIA = 405, + PPC_EVMWSMIAA = 406, + PPC_EVMWSMIAN = 407, + PPC_EVMWSSF = 408, + PPC_EVMWSSFA = 409, + PPC_EVMWSSFAA = 410, + PPC_EVMWSSFAN = 411, + PPC_EVMWUMI = 412, + PPC_EVMWUMIA = 413, + PPC_EVMWUMIAA = 414, + PPC_EVMWUMIAN = 415, + PPC_EVNAND = 416, + PPC_EVNEG = 417, + PPC_EVNOR = 418, + PPC_EVOR = 419, + PPC_EVORC = 420, + PPC_EVRLW = 421, + PPC_EVRLWI = 422, + PPC_EVRNDW = 423, + PPC_EVSLW = 424, + PPC_EVSLWI = 425, + PPC_EVSPLATFI = 426, + PPC_EVSPLATI = 427, + PPC_EVSRWIS = 428, + PPC_EVSRWIU = 429, + PPC_EVSRWS = 430, + PPC_EVSRWU = 431, + PPC_EVSTDD = 432, + PPC_EVSTDDX = 433, + PPC_EVSTDH = 434, + PPC_EVSTDHX = 435, + PPC_EVSTDW = 436, + PPC_EVSTDWX = 437, + PPC_EVSTWHE = 438, + PPC_EVSTWHEX = 439, + PPC_EVSTWHO = 440, + PPC_EVSTWHOX = 441, + PPC_EVSTWWE = 442, + PPC_EVSTWWEX = 443, + PPC_EVSTWWO = 444, + PPC_EVSTWWOX = 445, + PPC_EVSUBFSMIAAW = 446, + PPC_EVSUBFSSIAAW = 447, + PPC_EVSUBFUMIAAW = 448, + PPC_EVSUBFUSIAAW = 449, + PPC_EVSUBFW = 450, + PPC_EVSUBIFW = 451, + PPC_EVXOR = 452, + PPC_EXTLDI = 453, + PPC_EXTLDIo = 454, + PPC_EXTLWI = 455, + PPC_EXTLWIo = 456, + PPC_EXTRDI = 457, + PPC_EXTRDIo = 458, + PPC_EXTRWI = 459, + PPC_EXTRWIo = 460, + PPC_EXTSB = 461, + PPC_EXTSB8 = 462, + PPC_EXTSB8_32_64 = 463, + PPC_EXTSB8o = 464, + PPC_EXTSBo = 465, + PPC_EXTSH = 466, + PPC_EXTSH8 = 467, + PPC_EXTSH8_32_64 = 468, + PPC_EXTSH8o = 469, + PPC_EXTSHo = 470, + PPC_EXTSW = 471, + PPC_EXTSW_32_64 = 472, + PPC_EXTSW_32_64o = 473, + PPC_EXTSWo = 474, + PPC_EnforceIEIO = 475, + PPC_FABSD = 476, + PPC_FABSDo = 477, + PPC_FABSS = 478, + PPC_FABSSo = 479, + PPC_FADD = 480, + PPC_FADDS = 481, + PPC_FADDSo = 482, + PPC_FADDo = 483, + PPC_FADDrtz = 484, + PPC_FCFID = 485, + PPC_FCFIDS = 486, + PPC_FCFIDSo = 487, + PPC_FCFIDU = 488, + PPC_FCFIDUS = 489, + PPC_FCFIDUSo = 490, + PPC_FCFIDUo = 491, + PPC_FCFIDo = 492, + PPC_FCMPUD = 493, + PPC_FCMPUS = 494, + PPC_FCPSGND = 495, + PPC_FCPSGNDo = 496, + PPC_FCPSGNS = 497, + PPC_FCPSGNSo = 498, + PPC_FCTID = 499, + PPC_FCTIDUZ = 500, + PPC_FCTIDUZo = 501, + PPC_FCTIDZ = 502, + PPC_FCTIDZo = 503, + PPC_FCTIDo = 504, + PPC_FCTIW = 505, + PPC_FCTIWUZ = 506, + PPC_FCTIWUZo = 507, + PPC_FCTIWZ = 508, + PPC_FCTIWZo = 509, + PPC_FCTIWo = 510, + PPC_FDIV = 511, + PPC_FDIVS = 512, + PPC_FDIVSo = 513, + PPC_FDIVo = 514, + PPC_FMADD = 515, + PPC_FMADDS = 516, + PPC_FMADDSo = 517, + PPC_FMADDo = 518, + PPC_FMR = 519, + PPC_FMRo = 520, + PPC_FMSUB = 521, + PPC_FMSUBS = 522, + PPC_FMSUBSo = 523, + PPC_FMSUBo = 524, + PPC_FMUL = 525, + PPC_FMULS = 526, + PPC_FMULSo = 527, + PPC_FMULo = 528, + PPC_FNABSD = 529, + PPC_FNABSDo = 530, + PPC_FNABSS = 531, + PPC_FNABSSo = 532, + PPC_FNEGD = 533, + PPC_FNEGDo = 534, + PPC_FNEGS = 535, + PPC_FNEGSo = 536, + PPC_FNMADD = 537, + PPC_FNMADDS = 538, + PPC_FNMADDSo = 539, + PPC_FNMADDo = 540, + PPC_FNMSUB = 541, + PPC_FNMSUBS = 542, + PPC_FNMSUBSo = 543, + PPC_FNMSUBo = 544, + PPC_FRE = 545, + PPC_FRES = 546, + PPC_FRESo = 547, + PPC_FREo = 548, + PPC_FRIMD = 549, + PPC_FRIMDo = 550, + PPC_FRIMS = 551, + PPC_FRIMSo = 552, + PPC_FRIND = 553, + PPC_FRINDo = 554, + PPC_FRINS = 555, + PPC_FRINSo = 556, + PPC_FRIPD = 557, + PPC_FRIPDo = 558, + PPC_FRIPS = 559, + PPC_FRIPSo = 560, + PPC_FRIZD = 561, + PPC_FRIZDo = 562, + PPC_FRIZS = 563, + PPC_FRIZSo = 564, + PPC_FRSP = 565, + PPC_FRSPo = 566, + PPC_FRSQRTE = 567, + PPC_FRSQRTES = 568, + PPC_FRSQRTESo = 569, + PPC_FRSQRTEo = 570, + PPC_FSELD = 571, + PPC_FSELDo = 572, + PPC_FSELS = 573, + PPC_FSELSo = 574, + PPC_FSQRT = 575, + PPC_FSQRTS = 576, + PPC_FSQRTSo = 577, + PPC_FSQRTo = 578, + PPC_FSUB = 579, + PPC_FSUBS = 580, + PPC_FSUBSo = 581, + PPC_FSUBo = 582, + PPC_GETtlsADDR = 583, + PPC_GETtlsADDR32 = 584, + PPC_GETtlsldADDR = 585, + PPC_GETtlsldADDR32 = 586, + PPC_ICBI = 587, + PPC_ICBT = 588, + PPC_ICCCI = 589, + PPC_INSLWI = 590, + PPC_INSLWIo = 591, + PPC_INSRDI = 592, + PPC_INSRDIo = 593, + PPC_INSRWI = 594, + PPC_INSRWIo = 595, + PPC_ISEL = 596, + PPC_ISEL8 = 597, + PPC_ISYNC = 598, + PPC_LA = 599, + PPC_LAx = 600, + PPC_LBZ = 601, + PPC_LBZ8 = 602, + PPC_LBZCIX = 603, + PPC_LBZU = 604, + PPC_LBZU8 = 605, + PPC_LBZUX = 606, + PPC_LBZUX8 = 607, + PPC_LBZX = 608, + PPC_LBZX8 = 609, + PPC_LD = 610, + PPC_LDARX = 611, + PPC_LDBRX = 612, + PPC_LDCIX = 613, + PPC_LDU = 614, + PPC_LDUX = 615, + PPC_LDX = 616, + PPC_LDgotTprelL = 617, + PPC_LDgotTprelL32 = 618, + PPC_LDtoc = 619, + PPC_LDtocBA = 620, + PPC_LDtocCPT = 621, + PPC_LDtocJTI = 622, + PPC_LDtocL = 623, + PPC_LFD = 624, + PPC_LFDU = 625, + PPC_LFDUX = 626, + PPC_LFDX = 627, + PPC_LFIWAX = 628, + PPC_LFIWZX = 629, + PPC_LFS = 630, + PPC_LFSU = 631, + PPC_LFSUX = 632, + PPC_LFSX = 633, + PPC_LHA = 634, + PPC_LHA8 = 635, + PPC_LHAU = 636, + PPC_LHAU8 = 637, + PPC_LHAUX = 638, + PPC_LHAUX8 = 639, + PPC_LHAX = 640, + PPC_LHAX8 = 641, + PPC_LHBRX = 642, + PPC_LHBRX8 = 643, + PPC_LHZ = 644, + PPC_LHZ8 = 645, + PPC_LHZCIX = 646, + PPC_LHZU = 647, + PPC_LHZU8 = 648, + PPC_LHZUX = 649, + PPC_LHZUX8 = 650, + PPC_LHZX = 651, + PPC_LHZX8 = 652, + PPC_LI = 653, + PPC_LI8 = 654, + PPC_LIS = 655, + PPC_LIS8 = 656, + PPC_LMW = 657, + PPC_LSWI = 658, + PPC_LVEBX = 659, + PPC_LVEHX = 660, + PPC_LVEWX = 661, + PPC_LVSL = 662, + PPC_LVSR = 663, + PPC_LVX = 664, + PPC_LVXL = 665, + PPC_LWA = 666, + PPC_LWARX = 667, + PPC_LWAUX = 668, + PPC_LWAX = 669, + PPC_LWAX_32 = 670, + PPC_LWA_32 = 671, + PPC_LWBRX = 672, + PPC_LWBRX8 = 673, + PPC_LWZ = 674, + PPC_LWZ8 = 675, + PPC_LWZCIX = 676, + PPC_LWZU = 677, + PPC_LWZU8 = 678, + PPC_LWZUX = 679, + PPC_LWZUX8 = 680, + PPC_LWZX = 681, + PPC_LWZX8 = 682, + PPC_LWZtoc = 683, + PPC_LXSDX = 684, + PPC_LXVD2X = 685, + PPC_LXVDSX = 686, + PPC_LXVW4X = 687, + PPC_MBAR = 688, + PPC_MCRF = 689, + PPC_MCRFS = 690, + PPC_MFCR = 691, + PPC_MFCR8 = 692, + PPC_MFCTR = 693, + PPC_MFCTR8 = 694, + PPC_MFDCR = 695, + PPC_MFFS = 696, + PPC_MFFSo = 697, + PPC_MFLR = 698, + PPC_MFLR8 = 699, + PPC_MFMSR = 700, + PPC_MFOCRF = 701, + PPC_MFOCRF8 = 702, + PPC_MFSPR = 703, + PPC_MFSR = 704, + PPC_MFSRIN = 705, + PPC_MFTB = 706, + PPC_MFTB8 = 707, + PPC_MFVRSAVE = 708, + PPC_MFVRSAVEv = 709, + PPC_MFVSCR = 710, + PPC_MSYNC = 711, + PPC_MTCRF = 712, + PPC_MTCRF8 = 713, + PPC_MTCTR = 714, + PPC_MTCTR8 = 715, + PPC_MTCTR8loop = 716, + PPC_MTCTRloop = 717, + PPC_MTDCR = 718, + PPC_MTFSB0 = 719, + PPC_MTFSB1 = 720, + PPC_MTFSF = 721, + PPC_MTFSFI = 722, + PPC_MTFSFIo = 723, + PPC_MTFSFb = 724, + PPC_MTFSFo = 725, + PPC_MTLR = 726, + PPC_MTLR8 = 727, + PPC_MTMSR = 728, + PPC_MTMSRD = 729, + PPC_MTOCRF = 730, + PPC_MTOCRF8 = 731, + PPC_MTSPR = 732, + PPC_MTSR = 733, + PPC_MTSRIN = 734, + PPC_MTVRSAVE = 735, + PPC_MTVRSAVEv = 736, + PPC_MTVSCR = 737, + PPC_MULHD = 738, + PPC_MULHDU = 739, + PPC_MULHDUo = 740, + PPC_MULHDo = 741, + PPC_MULHW = 742, + PPC_MULHWU = 743, + PPC_MULHWUo = 744, + PPC_MULHWo = 745, + PPC_MULLD = 746, + PPC_MULLDo = 747, + PPC_MULLI = 748, + PPC_MULLI8 = 749, + PPC_MULLW = 750, + PPC_MULLWo = 751, + PPC_MoveGOTtoLR = 752, + PPC_MovePCtoLR = 753, + PPC_MovePCtoLR8 = 754, + PPC_NAND = 755, + PPC_NAND8 = 756, + PPC_NAND8o = 757, + PPC_NANDo = 758, + PPC_NEG = 759, + PPC_NEG8 = 760, + PPC_NEG8o = 761, + PPC_NEGo = 762, + PPC_NOP = 763, + PPC_NOP_GT_PWR6 = 764, + PPC_NOP_GT_PWR7 = 765, + PPC_NOR = 766, + PPC_NOR8 = 767, + PPC_NOR8o = 768, + PPC_NORo = 769, + PPC_OR = 770, + PPC_OR8 = 771, + PPC_OR8o = 772, + PPC_ORC = 773, + PPC_ORC8 = 774, + PPC_ORC8o = 775, + PPC_ORCo = 776, + PPC_ORI = 777, + PPC_ORI8 = 778, + PPC_ORIS = 779, + PPC_ORIS8 = 780, + PPC_ORo = 781, + PPC_POPCNTD = 782, + PPC_POPCNTW = 783, + PPC_PPC32GOT = 784, + PPC_PPC32PICGOT = 785, + PPC_QVALIGNI = 786, + PPC_QVALIGNIb = 787, + PPC_QVALIGNIs = 788, + PPC_QVESPLATI = 789, + PPC_QVESPLATIb = 790, + PPC_QVESPLATIs = 791, + PPC_QVFABS = 792, + PPC_QVFABSs = 793, + PPC_QVFADD = 794, + PPC_QVFADDS = 795, + PPC_QVFADDSs = 796, + PPC_QVFCFID = 797, + PPC_QVFCFIDS = 798, + PPC_QVFCFIDU = 799, + PPC_QVFCFIDUS = 800, + PPC_QVFCFIDb = 801, + PPC_QVFCMPEQ = 802, + PPC_QVFCMPEQb = 803, + PPC_QVFCMPEQbs = 804, + PPC_QVFCMPGT = 805, + PPC_QVFCMPGTb = 806, + PPC_QVFCMPGTbs = 807, + PPC_QVFCMPLT = 808, + PPC_QVFCMPLTb = 809, + PPC_QVFCMPLTbs = 810, + PPC_QVFCPSGN = 811, + PPC_QVFCPSGNs = 812, + PPC_QVFCTID = 813, + PPC_QVFCTIDU = 814, + PPC_QVFCTIDUZ = 815, + PPC_QVFCTIDZ = 816, + PPC_QVFCTIDb = 817, + PPC_QVFCTIW = 818, + PPC_QVFCTIWU = 819, + PPC_QVFCTIWUZ = 820, + PPC_QVFCTIWZ = 821, + PPC_QVFLOGICAL = 822, + PPC_QVFLOGICALb = 823, + PPC_QVFLOGICALs = 824, + PPC_QVFMADD = 825, + PPC_QVFMADDS = 826, + PPC_QVFMADDSs = 827, + PPC_QVFMR = 828, + PPC_QVFMRb = 829, + PPC_QVFMRs = 830, + PPC_QVFMSUB = 831, + PPC_QVFMSUBS = 832, + PPC_QVFMSUBSs = 833, + PPC_QVFMUL = 834, + PPC_QVFMULS = 835, + PPC_QVFMULSs = 836, + PPC_QVFNABS = 837, + PPC_QVFNABSs = 838, + PPC_QVFNEG = 839, + PPC_QVFNEGs = 840, + PPC_QVFNMADD = 841, + PPC_QVFNMADDS = 842, + PPC_QVFNMADDSs = 843, + PPC_QVFNMSUB = 844, + PPC_QVFNMSUBS = 845, + PPC_QVFNMSUBSs = 846, + PPC_QVFPERM = 847, + PPC_QVFPERMs = 848, + PPC_QVFRE = 849, + PPC_QVFRES = 850, + PPC_QVFRESs = 851, + PPC_QVFRIM = 852, + PPC_QVFRIMs = 853, + PPC_QVFRIN = 854, + PPC_QVFRINs = 855, + PPC_QVFRIP = 856, + PPC_QVFRIPs = 857, + PPC_QVFRIZ = 858, + PPC_QVFRIZs = 859, + PPC_QVFRSP = 860, + PPC_QVFRSPs = 861, + PPC_QVFRSQRTE = 862, + PPC_QVFRSQRTES = 863, + PPC_QVFRSQRTESs = 864, + PPC_QVFSEL = 865, + PPC_QVFSELb = 866, + PPC_QVFSELbb = 867, + PPC_QVFSELbs = 868, + PPC_QVFSUB = 869, + PPC_QVFSUBS = 870, + PPC_QVFSUBSs = 871, + PPC_QVFTSTNAN = 872, + PPC_QVFTSTNANb = 873, + PPC_QVFTSTNANbs = 874, + PPC_QVFXMADD = 875, + PPC_QVFXMADDS = 876, + PPC_QVFXMUL = 877, + PPC_QVFXMULS = 878, + PPC_QVFXXCPNMADD = 879, + PPC_QVFXXCPNMADDS = 880, + PPC_QVFXXMADD = 881, + PPC_QVFXXMADDS = 882, + PPC_QVFXXNPMADD = 883, + PPC_QVFXXNPMADDS = 884, + PPC_QVGPCI = 885, + PPC_QVLFCDUX = 886, + PPC_QVLFCDUXA = 887, + PPC_QVLFCDX = 888, + PPC_QVLFCDXA = 889, + PPC_QVLFCSUX = 890, + PPC_QVLFCSUXA = 891, + PPC_QVLFCSX = 892, + PPC_QVLFCSXA = 893, + PPC_QVLFCSXs = 894, + PPC_QVLFDUX = 895, + PPC_QVLFDUXA = 896, + PPC_QVLFDX = 897, + PPC_QVLFDXA = 898, + PPC_QVLFDXb = 899, + PPC_QVLFIWAX = 900, + PPC_QVLFIWAXA = 901, + PPC_QVLFIWZX = 902, + PPC_QVLFIWZXA = 903, + PPC_QVLFSUX = 904, + PPC_QVLFSUXA = 905, + PPC_QVLFSX = 906, + PPC_QVLFSXA = 907, + PPC_QVLFSXb = 908, + PPC_QVLFSXs = 909, + PPC_QVLPCLDX = 910, + PPC_QVLPCLSX = 911, + PPC_QVLPCLSXint = 912, + PPC_QVLPCRDX = 913, + PPC_QVLPCRSX = 914, + PPC_QVSTFCDUX = 915, + PPC_QVSTFCDUXA = 916, + PPC_QVSTFCDUXI = 917, + PPC_QVSTFCDUXIA = 918, + PPC_QVSTFCDX = 919, + PPC_QVSTFCDXA = 920, + PPC_QVSTFCDXI = 921, + PPC_QVSTFCDXIA = 922, + PPC_QVSTFCSUX = 923, + PPC_QVSTFCSUXA = 924, + PPC_QVSTFCSUXI = 925, + PPC_QVSTFCSUXIA = 926, + PPC_QVSTFCSX = 927, + PPC_QVSTFCSXA = 928, + PPC_QVSTFCSXI = 929, + PPC_QVSTFCSXIA = 930, + PPC_QVSTFCSXs = 931, + PPC_QVSTFDUX = 932, + PPC_QVSTFDUXA = 933, + PPC_QVSTFDUXI = 934, + PPC_QVSTFDUXIA = 935, + PPC_QVSTFDX = 936, + PPC_QVSTFDXA = 937, + PPC_QVSTFDXI = 938, + PPC_QVSTFDXIA = 939, + PPC_QVSTFDXb = 940, + PPC_QVSTFIWX = 941, + PPC_QVSTFIWXA = 942, + PPC_QVSTFSUX = 943, + PPC_QVSTFSUXA = 944, + PPC_QVSTFSUXI = 945, + PPC_QVSTFSUXIA = 946, + PPC_QVSTFSUXs = 947, + PPC_QVSTFSX = 948, + PPC_QVSTFSXA = 949, + PPC_QVSTFSXI = 950, + PPC_QVSTFSXIA = 951, + PPC_QVSTFSXs = 952, + PPC_RESTORE_CR = 953, + PPC_RESTORE_CRBIT = 954, + PPC_RESTORE_VRSAVE = 955, + PPC_RFCI = 956, + PPC_RFDI = 957, + PPC_RFI = 958, + PPC_RFID = 959, + PPC_RFMCI = 960, + PPC_RLDCL = 961, + PPC_RLDCLo = 962, + PPC_RLDCR = 963, + PPC_RLDCRo = 964, + PPC_RLDIC = 965, + PPC_RLDICL = 966, + PPC_RLDICL_32_64 = 967, + PPC_RLDICLo = 968, + PPC_RLDICR = 969, + PPC_RLDICRo = 970, + PPC_RLDICo = 971, + PPC_RLDIMI = 972, + PPC_RLDIMIo = 973, + PPC_RLWIMI = 974, + PPC_RLWIMI8 = 975, + PPC_RLWIMI8o = 976, + PPC_RLWIMIo = 977, + PPC_RLWINM = 978, + PPC_RLWINM8 = 979, + PPC_RLWINM8o = 980, + PPC_RLWINMo = 981, + PPC_RLWNM = 982, + PPC_RLWNM8 = 983, + PPC_RLWNM8o = 984, + PPC_RLWNMo = 985, + PPC_ROTRDI = 986, + PPC_ROTRDIo = 987, + PPC_ROTRWI = 988, + PPC_ROTRWIo = 989, + PPC_ReadTB = 990, + PPC_SC = 991, + PPC_SELECT_CC_F4 = 992, + PPC_SELECT_CC_F8 = 993, + PPC_SELECT_CC_I4 = 994, + PPC_SELECT_CC_I8 = 995, + PPC_SELECT_CC_QBRC = 996, + PPC_SELECT_CC_QFRC = 997, + PPC_SELECT_CC_QSRC = 998, + PPC_SELECT_CC_VRRC = 999, + PPC_SELECT_CC_VSFRC = 1000, + PPC_SELECT_CC_VSRC = 1001, + PPC_SELECT_F4 = 1002, + PPC_SELECT_F8 = 1003, + PPC_SELECT_I4 = 1004, + PPC_SELECT_I8 = 1005, + PPC_SELECT_QBRC = 1006, + PPC_SELECT_QFRC = 1007, + PPC_SELECT_QSRC = 1008, + PPC_SELECT_VRRC = 1009, + PPC_SELECT_VSFRC = 1010, + PPC_SELECT_VSRC = 1011, + PPC_SLBIA = 1012, + PPC_SLBIE = 1013, + PPC_SLBMFEE = 1014, + PPC_SLBMTE = 1015, + PPC_SLD = 1016, + PPC_SLDI = 1017, + PPC_SLDIo = 1018, + PPC_SLDo = 1019, + PPC_SLW = 1020, + PPC_SLW8 = 1021, + PPC_SLW8o = 1022, + PPC_SLWI = 1023, + PPC_SLWIo = 1024, + PPC_SLWo = 1025, + PPC_SPILL_CR = 1026, + PPC_SPILL_CRBIT = 1027, + PPC_SPILL_VRSAVE = 1028, + PPC_SRAD = 1029, + PPC_SRADI = 1030, + PPC_SRADIo = 1031, + PPC_SRADo = 1032, + PPC_SRAW = 1033, + PPC_SRAWI = 1034, + PPC_SRAWIo = 1035, + PPC_SRAWo = 1036, + PPC_SRD = 1037, + PPC_SRDI = 1038, + PPC_SRDIo = 1039, + PPC_SRDo = 1040, + PPC_SRW = 1041, + PPC_SRW8 = 1042, + PPC_SRW8o = 1043, + PPC_SRWI = 1044, + PPC_SRWIo = 1045, + PPC_SRWo = 1046, + PPC_STB = 1047, + PPC_STB8 = 1048, + PPC_STBCIX = 1049, + PPC_STBU = 1050, + PPC_STBU8 = 1051, + PPC_STBUX = 1052, + PPC_STBUX8 = 1053, + PPC_STBX = 1054, + PPC_STBX8 = 1055, + PPC_STD = 1056, + PPC_STDBRX = 1057, + PPC_STDCIX = 1058, + PPC_STDCX = 1059, + PPC_STDU = 1060, + PPC_STDUX = 1061, + PPC_STDX = 1062, + PPC_STFD = 1063, + PPC_STFDU = 1064, + PPC_STFDUX = 1065, + PPC_STFDX = 1066, + PPC_STFIWX = 1067, + PPC_STFS = 1068, + PPC_STFSU = 1069, + PPC_STFSUX = 1070, + PPC_STFSX = 1071, + PPC_STH = 1072, + PPC_STH8 = 1073, + PPC_STHBRX = 1074, + PPC_STHCIX = 1075, + PPC_STHU = 1076, + PPC_STHU8 = 1077, + PPC_STHUX = 1078, + PPC_STHUX8 = 1079, + PPC_STHX = 1080, + PPC_STHX8 = 1081, + PPC_STMW = 1082, + PPC_STSWI = 1083, + PPC_STVEBX = 1084, + PPC_STVEHX = 1085, + PPC_STVEWX = 1086, + PPC_STVX = 1087, + PPC_STVXL = 1088, + PPC_STW = 1089, + PPC_STW8 = 1090, + PPC_STWBRX = 1091, + PPC_STWCIX = 1092, + PPC_STWCX = 1093, + PPC_STWU = 1094, + PPC_STWU8 = 1095, + PPC_STWUX = 1096, + PPC_STWUX8 = 1097, + PPC_STWX = 1098, + PPC_STWX8 = 1099, + PPC_STXSDX = 1100, + PPC_STXVD2X = 1101, + PPC_STXVW4X = 1102, + PPC_SUBF = 1103, + PPC_SUBF8 = 1104, + PPC_SUBF8o = 1105, + PPC_SUBFC = 1106, + PPC_SUBFC8 = 1107, + PPC_SUBFC8o = 1108, + PPC_SUBFCo = 1109, + PPC_SUBFE = 1110, + PPC_SUBFE8 = 1111, + PPC_SUBFE8o = 1112, + PPC_SUBFEo = 1113, + PPC_SUBFIC = 1114, + PPC_SUBFIC8 = 1115, + PPC_SUBFME = 1116, + PPC_SUBFME8 = 1117, + PPC_SUBFME8o = 1118, + PPC_SUBFMEo = 1119, + PPC_SUBFZE = 1120, + PPC_SUBFZE8 = 1121, + PPC_SUBFZE8o = 1122, + PPC_SUBFZEo = 1123, + PPC_SUBFo = 1124, + PPC_SUBI = 1125, + PPC_SUBIC = 1126, + PPC_SUBICo = 1127, + PPC_SUBIS = 1128, + PPC_SYNC = 1129, + PPC_TAILB = 1130, + PPC_TAILB8 = 1131, + PPC_TAILBA = 1132, + PPC_TAILBA8 = 1133, + PPC_TAILBCTR = 1134, + PPC_TAILBCTR8 = 1135, + PPC_TCRETURNai = 1136, + PPC_TCRETURNai8 = 1137, + PPC_TCRETURNdi = 1138, + PPC_TCRETURNdi8 = 1139, + PPC_TCRETURNri = 1140, + PPC_TCRETURNri8 = 1141, + PPC_TD = 1142, + PPC_TDI = 1143, + PPC_TLBIA = 1144, + PPC_TLBIE = 1145, + PPC_TLBIEL = 1146, + PPC_TLBIVAX = 1147, + PPC_TLBLD = 1148, + PPC_TLBLI = 1149, + PPC_TLBRE = 1150, + PPC_TLBRE2 = 1151, + PPC_TLBSX = 1152, + PPC_TLBSX2 = 1153, + PPC_TLBSX2D = 1154, + PPC_TLBSYNC = 1155, + PPC_TLBWE = 1156, + PPC_TLBWE2 = 1157, + PPC_TRAP = 1158, + PPC_TW = 1159, + PPC_TWI = 1160, + PPC_UPDATE_VRSAVE = 1161, + PPC_UpdateGBR = 1162, + PPC_VADDCUW = 1163, + PPC_VADDFP = 1164, + PPC_VADDSBS = 1165, + PPC_VADDSHS = 1166, + PPC_VADDSWS = 1167, + PPC_VADDUBM = 1168, + PPC_VADDUBS = 1169, + PPC_VADDUDM = 1170, + PPC_VADDUHM = 1171, + PPC_VADDUHS = 1172, + PPC_VADDUWM = 1173, + PPC_VADDUWS = 1174, + PPC_VAND = 1175, + PPC_VANDC = 1176, + PPC_VAVGSB = 1177, + PPC_VAVGSH = 1178, + PPC_VAVGSW = 1179, + PPC_VAVGUB = 1180, + PPC_VAVGUH = 1181, + PPC_VAVGUW = 1182, + PPC_VCFSX = 1183, + PPC_VCFSX_0 = 1184, + PPC_VCFUX = 1185, + PPC_VCFUX_0 = 1186, + PPC_VCLZB = 1187, + PPC_VCLZD = 1188, + PPC_VCLZH = 1189, + PPC_VCLZW = 1190, + PPC_VCMPBFP = 1191, + PPC_VCMPBFPo = 1192, + PPC_VCMPEQFP = 1193, + PPC_VCMPEQFPo = 1194, + PPC_VCMPEQUB = 1195, + PPC_VCMPEQUBo = 1196, + PPC_VCMPEQUD = 1197, + PPC_VCMPEQUDo = 1198, + PPC_VCMPEQUH = 1199, + PPC_VCMPEQUHo = 1200, + PPC_VCMPEQUW = 1201, + PPC_VCMPEQUWo = 1202, + PPC_VCMPGEFP = 1203, + PPC_VCMPGEFPo = 1204, + PPC_VCMPGTFP = 1205, + PPC_VCMPGTFPo = 1206, + PPC_VCMPGTSB = 1207, + PPC_VCMPGTSBo = 1208, + PPC_VCMPGTSD = 1209, + PPC_VCMPGTSDo = 1210, + PPC_VCMPGTSH = 1211, + PPC_VCMPGTSHo = 1212, + PPC_VCMPGTSW = 1213, + PPC_VCMPGTSWo = 1214, + PPC_VCMPGTUB = 1215, + PPC_VCMPGTUBo = 1216, + PPC_VCMPGTUD = 1217, + PPC_VCMPGTUDo = 1218, + PPC_VCMPGTUH = 1219, + PPC_VCMPGTUHo = 1220, + PPC_VCMPGTUW = 1221, + PPC_VCMPGTUWo = 1222, + PPC_VCTSXS = 1223, + PPC_VCTSXS_0 = 1224, + PPC_VCTUXS = 1225, + PPC_VCTUXS_0 = 1226, + PPC_VEQV = 1227, + PPC_VEXPTEFP = 1228, + PPC_VLOGEFP = 1229, + PPC_VMADDFP = 1230, + PPC_VMAXFP = 1231, + PPC_VMAXSB = 1232, + PPC_VMAXSD = 1233, + PPC_VMAXSH = 1234, + PPC_VMAXSW = 1235, + PPC_VMAXUB = 1236, + PPC_VMAXUD = 1237, + PPC_VMAXUH = 1238, + PPC_VMAXUW = 1239, + PPC_VMHADDSHS = 1240, + PPC_VMHRADDSHS = 1241, + PPC_VMIDUD = 1242, + PPC_VMINFP = 1243, + PPC_VMINSB = 1244, + PPC_VMINSD = 1245, + PPC_VMINSH = 1246, + PPC_VMINSW = 1247, + PPC_VMINUB = 1248, + PPC_VMINUH = 1249, + PPC_VMINUW = 1250, + PPC_VMLADDUHM = 1251, + PPC_VMRGHB = 1252, + PPC_VMRGHH = 1253, + PPC_VMRGHW = 1254, + PPC_VMRGLB = 1255, + PPC_VMRGLH = 1256, + PPC_VMRGLW = 1257, + PPC_VMSUMMBM = 1258, + PPC_VMSUMSHM = 1259, + PPC_VMSUMSHS = 1260, + PPC_VMSUMUBM = 1261, + PPC_VMSUMUHM = 1262, + PPC_VMSUMUHS = 1263, + PPC_VMULESB = 1264, + PPC_VMULESH = 1265, + PPC_VMULESW = 1266, + PPC_VMULEUB = 1267, + PPC_VMULEUH = 1268, + PPC_VMULEUW = 1269, + PPC_VMULOSB = 1270, + PPC_VMULOSH = 1271, + PPC_VMULOSW = 1272, + PPC_VMULOUB = 1273, + PPC_VMULOUH = 1274, + PPC_VMULOUW = 1275, + PPC_VMULUWM = 1276, + PPC_VNAND = 1277, + PPC_VNMSUBFP = 1278, + PPC_VNOR = 1279, + PPC_VOR = 1280, + PPC_VORC = 1281, + PPC_VPERM = 1282, + PPC_VPKPX = 1283, + PPC_VPKSHSS = 1284, + PPC_VPKSHUS = 1285, + PPC_VPKSWSS = 1286, + PPC_VPKSWUS = 1287, + PPC_VPKUHUM = 1288, + PPC_VPKUHUS = 1289, + PPC_VPKUWUM = 1290, + PPC_VPKUWUS = 1291, + PPC_VPOPCNTB = 1292, + PPC_VPOPCNTD = 1293, + PPC_VPOPCNTH = 1294, + PPC_VPOPCNTW = 1295, + PPC_VREFP = 1296, + PPC_VRFIM = 1297, + PPC_VRFIN = 1298, + PPC_VRFIP = 1299, + PPC_VRFIZ = 1300, + PPC_VRLB = 1301, + PPC_VRLD = 1302, + PPC_VRLH = 1303, + PPC_VRLW = 1304, + PPC_VRSQRTEFP = 1305, + PPC_VSEL = 1306, + PPC_VSL = 1307, + PPC_VSLB = 1308, + PPC_VSLD = 1309, + PPC_VSLDOI = 1310, + PPC_VSLH = 1311, + PPC_VSLO = 1312, + PPC_VSLW = 1313, + PPC_VSPLTB = 1314, + PPC_VSPLTH = 1315, + PPC_VSPLTISB = 1316, + PPC_VSPLTISH = 1317, + PPC_VSPLTISW = 1318, + PPC_VSPLTW = 1319, + PPC_VSR = 1320, + PPC_VSRAB = 1321, + PPC_VSRAD = 1322, + PPC_VSRAH = 1323, + PPC_VSRAW = 1324, + PPC_VSRB = 1325, + PPC_VSRD = 1326, + PPC_VSRH = 1327, + PPC_VSRO = 1328, + PPC_VSRW = 1329, + PPC_VSUBCUW = 1330, + PPC_VSUBFP = 1331, + PPC_VSUBSBS = 1332, + PPC_VSUBSHS = 1333, + PPC_VSUBSWS = 1334, + PPC_VSUBUBM = 1335, + PPC_VSUBUBS = 1336, + PPC_VSUBUDM = 1337, + PPC_VSUBUHM = 1338, + PPC_VSUBUHS = 1339, + PPC_VSUBUWM = 1340, + PPC_VSUBUWS = 1341, + PPC_VSUM2SWS = 1342, + PPC_VSUM4SBS = 1343, + PPC_VSUM4SHS = 1344, + PPC_VSUM4UBS = 1345, + PPC_VSUMSWS = 1346, + PPC_VUPKHPX = 1347, + PPC_VUPKHSB = 1348, + PPC_VUPKHSH = 1349, + PPC_VUPKLPX = 1350, + PPC_VUPKLSB = 1351, + PPC_VUPKLSH = 1352, + PPC_VXOR = 1353, + PPC_V_SET0 = 1354, + PPC_V_SET0B = 1355, + PPC_V_SET0H = 1356, + PPC_V_SETALLONES = 1357, + PPC_V_SETALLONESB = 1358, + PPC_V_SETALLONESH = 1359, + PPC_WAIT = 1360, + PPC_WRTEE = 1361, + PPC_WRTEEI = 1362, + PPC_XOR = 1363, + PPC_XOR8 = 1364, + PPC_XOR8o = 1365, + PPC_XORI = 1366, + PPC_XORI8 = 1367, + PPC_XORIS = 1368, + PPC_XORIS8 = 1369, + PPC_XORo = 1370, + PPC_XSABSDP = 1371, + PPC_XSADDDP = 1372, + PPC_XSCMPODP = 1373, + PPC_XSCMPUDP = 1374, + PPC_XSCPSGNDP = 1375, + PPC_XSCVDPSP = 1376, + PPC_XSCVDPSXDS = 1377, + PPC_XSCVDPSXWS = 1378, + PPC_XSCVDPUXDS = 1379, + PPC_XSCVDPUXWS = 1380, + PPC_XSCVSPDP = 1381, + PPC_XSCVSXDDP = 1382, + PPC_XSCVUXDDP = 1383, + PPC_XSDIVDP = 1384, + PPC_XSMADDADP = 1385, + PPC_XSMADDMDP = 1386, + PPC_XSMAXDP = 1387, + PPC_XSMINDP = 1388, + PPC_XSMSUBADP = 1389, + PPC_XSMSUBMDP = 1390, + PPC_XSMULDP = 1391, + PPC_XSNABSDP = 1392, + PPC_XSNEGDP = 1393, + PPC_XSNMADDADP = 1394, + PPC_XSNMADDMDP = 1395, + PPC_XSNMSUBADP = 1396, + PPC_XSNMSUBMDP = 1397, + PPC_XSRDPI = 1398, + PPC_XSRDPIC = 1399, + PPC_XSRDPIM = 1400, + PPC_XSRDPIP = 1401, + PPC_XSRDPIZ = 1402, + PPC_XSREDP = 1403, + PPC_XSRSQRTEDP = 1404, + PPC_XSSQRTDP = 1405, + PPC_XSSUBDP = 1406, + PPC_XSTDIVDP = 1407, + PPC_XSTSQRTDP = 1408, + PPC_XVABSDP = 1409, + PPC_XVABSSP = 1410, + PPC_XVADDDP = 1411, + PPC_XVADDSP = 1412, + PPC_XVCMPEQDP = 1413, + PPC_XVCMPEQDPo = 1414, + PPC_XVCMPEQSP = 1415, + PPC_XVCMPEQSPo = 1416, + PPC_XVCMPGEDP = 1417, + PPC_XVCMPGEDPo = 1418, + PPC_XVCMPGESP = 1419, + PPC_XVCMPGESPo = 1420, + PPC_XVCMPGTDP = 1421, + PPC_XVCMPGTDPo = 1422, + PPC_XVCMPGTSP = 1423, + PPC_XVCMPGTSPo = 1424, + PPC_XVCPSGNDP = 1425, + PPC_XVCPSGNSP = 1426, + PPC_XVCVDPSP = 1427, + PPC_XVCVDPSXDS = 1428, + PPC_XVCVDPSXWS = 1429, + PPC_XVCVDPUXDS = 1430, + PPC_XVCVDPUXWS = 1431, + PPC_XVCVSPDP = 1432, + PPC_XVCVSPSXDS = 1433, + PPC_XVCVSPSXWS = 1434, + PPC_XVCVSPUXDS = 1435, + PPC_XVCVSPUXWS = 1436, + PPC_XVCVSXDDP = 1437, + PPC_XVCVSXDSP = 1438, + PPC_XVCVSXWDP = 1439, + PPC_XVCVSXWSP = 1440, + PPC_XVCVUXDDP = 1441, + PPC_XVCVUXDSP = 1442, + PPC_XVCVUXWDP = 1443, + PPC_XVCVUXWSP = 1444, + PPC_XVDIVDP = 1445, + PPC_XVDIVSP = 1446, + PPC_XVMADDADP = 1447, + PPC_XVMADDASP = 1448, + PPC_XVMADDMDP = 1449, + PPC_XVMADDMSP = 1450, + PPC_XVMAXDP = 1451, + PPC_XVMAXSP = 1452, + PPC_XVMINDP = 1453, + PPC_XVMINSP = 1454, + PPC_XVMSUBADP = 1455, + PPC_XVMSUBASP = 1456, + PPC_XVMSUBMDP = 1457, + PPC_XVMSUBMSP = 1458, + PPC_XVMULDP = 1459, + PPC_XVMULSP = 1460, + PPC_XVNABSDP = 1461, + PPC_XVNABSSP = 1462, + PPC_XVNEGDP = 1463, + PPC_XVNEGSP = 1464, + PPC_XVNMADDADP = 1465, + PPC_XVNMADDASP = 1466, + PPC_XVNMADDMDP = 1467, + PPC_XVNMADDMSP = 1468, + PPC_XVNMSUBADP = 1469, + PPC_XVNMSUBASP = 1470, + PPC_XVNMSUBMDP = 1471, + PPC_XVNMSUBMSP = 1472, + PPC_XVRDPI = 1473, + PPC_XVRDPIC = 1474, + PPC_XVRDPIM = 1475, + PPC_XVRDPIP = 1476, + PPC_XVRDPIZ = 1477, + PPC_XVREDP = 1478, + PPC_XVRESP = 1479, + PPC_XVRSPI = 1480, + PPC_XVRSPIC = 1481, + PPC_XVRSPIM = 1482, + PPC_XVRSPIP = 1483, + PPC_XVRSPIZ = 1484, + PPC_XVRSQRTEDP = 1485, + PPC_XVRSQRTESP = 1486, + PPC_XVSQRTDP = 1487, + PPC_XVSQRTSP = 1488, + PPC_XVSUBDP = 1489, + PPC_XVSUBSP = 1490, + PPC_XVTDIVDP = 1491, + PPC_XVTDIVSP = 1492, + PPC_XVTSQRTDP = 1493, + PPC_XVTSQRTSP = 1494, + PPC_XXLAND = 1495, + PPC_XXLANDC = 1496, + PPC_XXLEQV = 1497, + PPC_XXLNAND = 1498, + PPC_XXLNOR = 1499, + PPC_XXLOR = 1500, + PPC_XXLORC = 1501, + PPC_XXLORf = 1502, + PPC_XXLXOR = 1503, + PPC_XXMRGHW = 1504, + PPC_XXMRGLW = 1505, + PPC_XXPERMDI = 1506, + PPC_XXSEL = 1507, + PPC_XXSLDWI = 1508, + PPC_XXSPLTW = 1509, + PPC_gBC = 1510, + PPC_gBCA = 1511, + PPC_gBCCTR = 1512, + PPC_gBCCTRL = 1513, + PPC_gBCL = 1514, + PPC_gBCLA = 1515, + PPC_gBCLR = 1516, + PPC_gBCLRL = 1517, + PPC_INSTRUCTION_LIST_END = 1518 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenRegisterInfo.inc new file mode 100644 index 0000000..d05d658 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenRegisterInfo.inc @@ -0,0 +1,985 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + PPC_NoRegister, + PPC_BP = 1, + PPC_CARRY = 2, + PPC_CTR = 3, + PPC_FP = 4, + PPC_LR = 5, + PPC_RM = 6, + PPC_VRSAVE = 7, + PPC_ZERO = 8, + PPC_BP8 = 9, + PPC_CR0 = 10, + PPC_CR1 = 11, + PPC_CR2 = 12, + PPC_CR3 = 13, + PPC_CR4 = 14, + PPC_CR5 = 15, + PPC_CR6 = 16, + PPC_CR7 = 17, + PPC_CTR8 = 18, + PPC_F0 = 19, + PPC_F1 = 20, + PPC_F2 = 21, + PPC_F3 = 22, + PPC_F4 = 23, + PPC_F5 = 24, + PPC_F6 = 25, + PPC_F7 = 26, + PPC_F8 = 27, + PPC_F9 = 28, + PPC_F10 = 29, + PPC_F11 = 30, + PPC_F12 = 31, + PPC_F13 = 32, + PPC_F14 = 33, + PPC_F15 = 34, + PPC_F16 = 35, + PPC_F17 = 36, + PPC_F18 = 37, + PPC_F19 = 38, + PPC_F20 = 39, + PPC_F21 = 40, + PPC_F22 = 41, + PPC_F23 = 42, + PPC_F24 = 43, + PPC_F25 = 44, + PPC_F26 = 45, + PPC_F27 = 46, + PPC_F28 = 47, + PPC_F29 = 48, + PPC_F30 = 49, + PPC_F31 = 50, + PPC_FP8 = 51, + PPC_LR8 = 52, + PPC_QF0 = 53, + PPC_QF1 = 54, + PPC_QF2 = 55, + PPC_QF3 = 56, + PPC_QF4 = 57, + PPC_QF5 = 58, + PPC_QF6 = 59, + PPC_QF7 = 60, + PPC_QF8 = 61, + PPC_QF9 = 62, + PPC_QF10 = 63, + PPC_QF11 = 64, + PPC_QF12 = 65, + PPC_QF13 = 66, + PPC_QF14 = 67, + PPC_QF15 = 68, + PPC_QF16 = 69, + PPC_QF17 = 70, + PPC_QF18 = 71, + PPC_QF19 = 72, + PPC_QF20 = 73, + PPC_QF21 = 74, + PPC_QF22 = 75, + PPC_QF23 = 76, + PPC_QF24 = 77, + PPC_QF25 = 78, + PPC_QF26 = 79, + PPC_QF27 = 80, + PPC_QF28 = 81, + PPC_QF29 = 82, + PPC_QF30 = 83, + PPC_QF31 = 84, + PPC_R0 = 85, + PPC_R1 = 86, + PPC_R2 = 87, + PPC_R3 = 88, + PPC_R4 = 89, + PPC_R5 = 90, + PPC_R6 = 91, + PPC_R7 = 92, + PPC_R8 = 93, + PPC_R9 = 94, + PPC_R10 = 95, + PPC_R11 = 96, + PPC_R12 = 97, + PPC_R13 = 98, + PPC_R14 = 99, + PPC_R15 = 100, + PPC_R16 = 101, + PPC_R17 = 102, + PPC_R18 = 103, + PPC_R19 = 104, + PPC_R20 = 105, + PPC_R21 = 106, + PPC_R22 = 107, + PPC_R23 = 108, + PPC_R24 = 109, + PPC_R25 = 110, + PPC_R26 = 111, + PPC_R27 = 112, + PPC_R28 = 113, + PPC_R29 = 114, + PPC_R30 = 115, + PPC_R31 = 116, + PPC_V0 = 117, + PPC_V1 = 118, + PPC_V2 = 119, + PPC_V3 = 120, + PPC_V4 = 121, + PPC_V5 = 122, + PPC_V6 = 123, + PPC_V7 = 124, + PPC_V8 = 125, + PPC_V9 = 126, + PPC_V10 = 127, + PPC_V11 = 128, + PPC_V12 = 129, + PPC_V13 = 130, + PPC_V14 = 131, + PPC_V15 = 132, + PPC_V16 = 133, + PPC_V17 = 134, + PPC_V18 = 135, + PPC_V19 = 136, + PPC_V20 = 137, + PPC_V21 = 138, + PPC_V22 = 139, + PPC_V23 = 140, + PPC_V24 = 141, + PPC_V25 = 142, + PPC_V26 = 143, + PPC_V27 = 144, + PPC_V28 = 145, + PPC_V29 = 146, + PPC_V30 = 147, + PPC_V31 = 148, + PPC_VF0 = 149, + PPC_VF1 = 150, + PPC_VF2 = 151, + PPC_VF3 = 152, + PPC_VF4 = 153, + PPC_VF5 = 154, + PPC_VF6 = 155, + PPC_VF7 = 156, + PPC_VF8 = 157, + PPC_VF9 = 158, + PPC_VF10 = 159, + PPC_VF11 = 160, + PPC_VF12 = 161, + PPC_VF13 = 162, + PPC_VF14 = 163, + PPC_VF15 = 164, + PPC_VF16 = 165, + PPC_VF17 = 166, + PPC_VF18 = 167, + PPC_VF19 = 168, + PPC_VF20 = 169, + PPC_VF21 = 170, + PPC_VF22 = 171, + PPC_VF23 = 172, + PPC_VF24 = 173, + PPC_VF25 = 174, + PPC_VF26 = 175, + PPC_VF27 = 176, + PPC_VF28 = 177, + PPC_VF29 = 178, + PPC_VF30 = 179, + PPC_VF31 = 180, + PPC_VSH0 = 181, + PPC_VSH1 = 182, + PPC_VSH2 = 183, + PPC_VSH3 = 184, + PPC_VSH4 = 185, + PPC_VSH5 = 186, + PPC_VSH6 = 187, + PPC_VSH7 = 188, + PPC_VSH8 = 189, + PPC_VSH9 = 190, + PPC_VSH10 = 191, + PPC_VSH11 = 192, + PPC_VSH12 = 193, + PPC_VSH13 = 194, + PPC_VSH14 = 195, + PPC_VSH15 = 196, + PPC_VSH16 = 197, + PPC_VSH17 = 198, + PPC_VSH18 = 199, + PPC_VSH19 = 200, + PPC_VSH20 = 201, + PPC_VSH21 = 202, + PPC_VSH22 = 203, + PPC_VSH23 = 204, + PPC_VSH24 = 205, + PPC_VSH25 = 206, + PPC_VSH26 = 207, + PPC_VSH27 = 208, + PPC_VSH28 = 209, + PPC_VSH29 = 210, + PPC_VSH30 = 211, + PPC_VSH31 = 212, + PPC_VSL0 = 213, + PPC_VSL1 = 214, + PPC_VSL2 = 215, + PPC_VSL3 = 216, + PPC_VSL4 = 217, + PPC_VSL5 = 218, + PPC_VSL6 = 219, + PPC_VSL7 = 220, + PPC_VSL8 = 221, + PPC_VSL9 = 222, + PPC_VSL10 = 223, + PPC_VSL11 = 224, + PPC_VSL12 = 225, + PPC_VSL13 = 226, + PPC_VSL14 = 227, + PPC_VSL15 = 228, + PPC_VSL16 = 229, + PPC_VSL17 = 230, + PPC_VSL18 = 231, + PPC_VSL19 = 232, + PPC_VSL20 = 233, + PPC_VSL21 = 234, + PPC_VSL22 = 235, + PPC_VSL23 = 236, + PPC_VSL24 = 237, + PPC_VSL25 = 238, + PPC_VSL26 = 239, + PPC_VSL27 = 240, + PPC_VSL28 = 241, + PPC_VSL29 = 242, + PPC_VSL30 = 243, + PPC_VSL31 = 244, + PPC_X0 = 245, + PPC_X1 = 246, + PPC_X2 = 247, + PPC_X3 = 248, + PPC_X4 = 249, + PPC_X5 = 250, + PPC_X6 = 251, + PPC_X7 = 252, + PPC_X8 = 253, + PPC_X9 = 254, + PPC_X10 = 255, + PPC_X11 = 256, + PPC_X12 = 257, + PPC_X13 = 258, + PPC_X14 = 259, + PPC_X15 = 260, + PPC_X16 = 261, + PPC_X17 = 262, + PPC_X18 = 263, + PPC_X19 = 264, + PPC_X20 = 265, + PPC_X21 = 266, + PPC_X22 = 267, + PPC_X23 = 268, + PPC_X24 = 269, + PPC_X25 = 270, + PPC_X26 = 271, + PPC_X27 = 272, + PPC_X28 = 273, + PPC_X29 = 274, + PPC_X30 = 275, + PPC_X31 = 276, + PPC_ZERO8 = 277, + PPC_CR0EQ = 278, + PPC_CR1EQ = 279, + PPC_CR2EQ = 280, + PPC_CR3EQ = 281, + PPC_CR4EQ = 282, + PPC_CR5EQ = 283, + PPC_CR6EQ = 284, + PPC_CR7EQ = 285, + PPC_CR0GT = 286, + PPC_CR1GT = 287, + PPC_CR2GT = 288, + PPC_CR3GT = 289, + PPC_CR4GT = 290, + PPC_CR5GT = 291, + PPC_CR6GT = 292, + PPC_CR7GT = 293, + PPC_CR0LT = 294, + PPC_CR1LT = 295, + PPC_CR2LT = 296, + PPC_CR3LT = 297, + PPC_CR4LT = 298, + PPC_CR5LT = 299, + PPC_CR6LT = 300, + PPC_CR7LT = 301, + PPC_CR0UN = 302, + PPC_CR1UN = 303, + PPC_CR2UN = 304, + PPC_CR3UN = 305, + PPC_CR4UN = 306, + PPC_CR5UN = 307, + PPC_CR6UN = 308, + PPC_CR7UN = 309, + PPC_NUM_TARGET_REGS // 310 +}; + +// Register classes +enum { + PPC_GPRCRegClassID = 0, + PPC_GPRC_NOR0RegClassID = 1, + PPC_GPRC_and_GPRC_NOR0RegClassID = 2, + PPC_CRBITRCRegClassID = 3, + PPC_F4RCRegClassID = 4, + PPC_CRRCRegClassID = 5, + PPC_CARRYRCRegClassID = 6, + PPC_CTRRCRegClassID = 7, + PPC_VRSAVERCRegClassID = 8, + PPC_VSFRCRegClassID = 9, + PPC_G8RCRegClassID = 10, + PPC_G8RC_NOX0RegClassID = 11, + PPC_G8RC_and_G8RC_NOX0RegClassID = 12, + PPC_F8RCRegClassID = 13, + PPC_VFRCRegClassID = 14, + PPC_CTRRC8RegClassID = 15, + PPC_VSRCRegClassID = 16, + PPC_QSRCRegClassID = 17, + PPC_VRRCRegClassID = 18, + PPC_VSHRCRegClassID = 19, + PPC_VSLRCRegClassID = 20, + PPC_QBRCRegClassID = 21, + PPC_QFRCRegClassID = 22, +}; + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg PPCRegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 65504, 1, 1, 1, 0, + /* 7 */ 3, 0, + /* 9 */ 8, 0, + /* 11 */ 22, 0, + /* 13 */ 284, 65528, 65528, 24, 0, + /* 18 */ 65472, 32, 0, + /* 21 */ 47, 0, + /* 23 */ 65504, 64, 0, + /* 26 */ 73, 0, + /* 28 */ 34, 160, 0, + /* 31 */ 269, 0, + /* 33 */ 64339, 0, + /* 35 */ 64368, 0, + /* 37 */ 64401, 0, + /* 39 */ 64434, 0, + /* 41 */ 64712, 0, + /* 43 */ 65244, 0, + /* 45 */ 65252, 0, + /* 47 */ 65260, 0, + /* 49 */ 65267, 0, + /* 51 */ 65268, 0, + /* 53 */ 65342, 0, + /* 55 */ 65364, 0, + /* 57 */ 65365, 0, + /* 59 */ 65376, 0, + /* 61 */ 65461, 0, + /* 63 */ 65489, 0, + /* 65 */ 65493, 0, + /* 67 */ 65502, 0, + /* 69 */ 65524, 0, + /* 71 */ 65525, 0, + /* 73 */ 65528, 0, + /* 75 */ 65535, 0, +}; + +static const uint16_t PPCSubRegIdxLists[] = { + /* 0 */ 1, 0, + /* 2 */ 3, 2, 0, + /* 5 */ 6, 5, 4, 7, 0, +}; + +static MCRegisterDesc PPCRegDesc[] = { // Descriptors + { 4, 0, 0, 0, 0, 0 }, + { 1109, 1, 9, 1, 1201, 0 }, + { 1266, 1, 1, 1, 1201, 0 }, + { 1166, 1, 1, 1, 1201, 0 }, + { 1112, 1, 21, 1, 1201, 0 }, + { 1163, 1, 1, 1, 1201, 0 }, + { 1053, 1, 1, 1, 1201, 0 }, + { 1046, 1, 1, 1, 1201, 0 }, + { 1104, 1, 31, 1, 1201, 0 }, + { 928, 73, 1, 0, 0, 2 }, + { 120, 13, 1, 5, 36, 6 }, + { 250, 13, 1, 5, 36, 6 }, + { 346, 13, 1, 5, 36, 6 }, + { 442, 13, 1, 5, 36, 6 }, + { 538, 13, 1, 5, 36, 6 }, + { 634, 13, 1, 5, 36, 6 }, + { 730, 13, 1, 5, 36, 6 }, + { 826, 13, 1, 5, 36, 6 }, + { 940, 1, 1, 1, 177, 0 }, + { 103, 1, 28, 1, 177, 0 }, + { 233, 1, 28, 1, 177, 0 }, + { 329, 1, 28, 1, 177, 0 }, + { 425, 1, 28, 1, 177, 0 }, + { 521, 1, 28, 1, 177, 0 }, + { 617, 1, 28, 1, 177, 0 }, + { 713, 1, 28, 1, 177, 0 }, + { 809, 1, 28, 1, 177, 0 }, + { 905, 1, 28, 1, 177, 0 }, + { 1020, 1, 28, 1, 177, 0 }, + { 1, 1, 28, 1, 177, 0 }, + { 131, 1, 28, 1, 177, 0 }, + { 261, 1, 28, 1, 177, 0 }, + { 357, 1, 28, 1, 177, 0 }, + { 453, 1, 28, 1, 177, 0 }, + { 549, 1, 28, 1, 177, 0 }, + { 645, 1, 28, 1, 177, 0 }, + { 741, 1, 28, 1, 177, 0 }, + { 837, 1, 28, 1, 177, 0 }, + { 952, 1, 28, 1, 177, 0 }, + { 35, 1, 28, 1, 177, 0 }, + { 165, 1, 28, 1, 177, 0 }, + { 295, 1, 28, 1, 177, 0 }, + { 391, 1, 28, 1, 177, 0 }, + { 487, 1, 28, 1, 177, 0 }, + { 583, 1, 28, 1, 177, 0 }, + { 679, 1, 28, 1, 177, 0 }, + { 775, 1, 28, 1, 177, 0 }, + { 871, 1, 28, 1, 177, 0 }, + { 986, 1, 28, 1, 177, 0 }, + { 69, 1, 28, 1, 177, 0 }, + { 199, 1, 28, 1, 177, 0 }, + { 932, 63, 1, 0, 112, 2 }, + { 936, 1, 1, 1, 416, 0 }, + { 102, 67, 1, 3, 1105, 4 }, + { 232, 67, 1, 3, 1105, 4 }, + { 328, 67, 1, 3, 1105, 4 }, + { 424, 67, 1, 3, 1105, 4 }, + { 520, 67, 1, 3, 1105, 4 }, + { 616, 67, 1, 3, 1105, 4 }, + { 712, 67, 1, 3, 1105, 4 }, + { 808, 67, 1, 3, 1105, 4 }, + { 904, 67, 1, 3, 1105, 4 }, + { 1019, 67, 1, 3, 1105, 4 }, + { 0, 67, 1, 3, 1105, 4 }, + { 130, 67, 1, 3, 1105, 4 }, + { 260, 67, 1, 3, 1105, 4 }, + { 356, 67, 1, 3, 1105, 4 }, + { 452, 67, 1, 3, 1105, 4 }, + { 548, 67, 1, 3, 1105, 4 }, + { 644, 67, 1, 3, 1105, 4 }, + { 740, 67, 1, 3, 1105, 4 }, + { 836, 67, 1, 3, 1105, 4 }, + { 951, 67, 1, 3, 1105, 4 }, + { 34, 67, 1, 3, 1105, 4 }, + { 164, 67, 1, 3, 1105, 4 }, + { 294, 67, 1, 3, 1105, 4 }, + { 390, 67, 1, 3, 1105, 4 }, + { 486, 67, 1, 3, 1105, 4 }, + { 582, 67, 1, 3, 1105, 4 }, + { 678, 67, 1, 3, 1105, 4 }, + { 774, 67, 1, 3, 1105, 4 }, + { 870, 67, 1, 3, 1105, 4 }, + { 985, 67, 1, 3, 1105, 4 }, + { 68, 67, 1, 3, 1105, 4 }, + { 198, 67, 1, 3, 1105, 4 }, + { 121, 1, 29, 1, 1137, 0 }, + { 251, 1, 29, 1, 1137, 0 }, + { 347, 1, 29, 1, 1137, 0 }, + { 443, 1, 29, 1, 1137, 0 }, + { 539, 1, 29, 1, 1137, 0 }, + { 635, 1, 29, 1, 1137, 0 }, + { 731, 1, 29, 1, 1137, 0 }, + { 827, 1, 29, 1, 1137, 0 }, + { 937, 1, 29, 1, 1137, 0 }, + { 1037, 1, 29, 1, 1137, 0 }, + { 22, 1, 29, 1, 1137, 0 }, + { 152, 1, 29, 1, 1137, 0 }, + { 282, 1, 29, 1, 1137, 0 }, + { 378, 1, 29, 1, 1137, 0 }, + { 474, 1, 29, 1, 1137, 0 }, + { 570, 1, 29, 1, 1137, 0 }, + { 666, 1, 29, 1, 1137, 0 }, + { 762, 1, 29, 1, 1137, 0 }, + { 858, 1, 29, 1, 1137, 0 }, + { 973, 1, 29, 1, 1137, 0 }, + { 56, 1, 29, 1, 1137, 0 }, + { 186, 1, 29, 1, 1137, 0 }, + { 316, 1, 29, 1, 1137, 0 }, + { 412, 1, 29, 1, 1137, 0 }, + { 508, 1, 29, 1, 1137, 0 }, + { 604, 1, 29, 1, 1137, 0 }, + { 700, 1, 29, 1, 1137, 0 }, + { 796, 1, 29, 1, 1137, 0 }, + { 892, 1, 29, 1, 1137, 0 }, + { 1007, 1, 29, 1, 1137, 0 }, + { 90, 1, 29, 1, 1137, 0 }, + { 220, 1, 29, 1, 1137, 0 }, + { 124, 19, 24, 3, 1137, 4 }, + { 254, 19, 24, 3, 1137, 4 }, + { 350, 19, 24, 3, 1137, 4 }, + { 446, 19, 24, 3, 1137, 4 }, + { 542, 19, 24, 3, 1137, 4 }, + { 638, 19, 24, 3, 1137, 4 }, + { 734, 19, 24, 3, 1137, 4 }, + { 830, 19, 24, 3, 1137, 4 }, + { 945, 19, 24, 3, 1137, 4 }, + { 1040, 19, 24, 3, 1137, 4 }, + { 26, 19, 24, 3, 1137, 4 }, + { 156, 19, 24, 3, 1137, 4 }, + { 286, 19, 24, 3, 1137, 4 }, + { 382, 19, 24, 3, 1137, 4 }, + { 478, 19, 24, 3, 1137, 4 }, + { 574, 19, 24, 3, 1137, 4 }, + { 670, 19, 24, 3, 1137, 4 }, + { 766, 19, 24, 3, 1137, 4 }, + { 862, 19, 24, 3, 1137, 4 }, + { 977, 19, 24, 3, 1137, 4 }, + { 60, 19, 24, 3, 1137, 4 }, + { 190, 19, 24, 3, 1137, 4 }, + { 320, 19, 24, 3, 1137, 4 }, + { 416, 19, 24, 3, 1137, 4 }, + { 512, 19, 24, 3, 1137, 4 }, + { 608, 19, 24, 3, 1137, 4 }, + { 704, 19, 24, 3, 1137, 4 }, + { 800, 19, 24, 3, 1137, 4 }, + { 896, 19, 24, 3, 1137, 4 }, + { 1011, 19, 24, 3, 1137, 4 }, + { 94, 19, 24, 3, 1137, 4 }, + { 224, 19, 24, 3, 1137, 4 }, + { 106, 1, 23, 1, 1041, 0 }, + { 236, 1, 23, 1, 1041, 0 }, + { 332, 1, 23, 1, 1041, 0 }, + { 428, 1, 23, 1, 1041, 0 }, + { 524, 1, 23, 1, 1041, 0 }, + { 620, 1, 23, 1, 1041, 0 }, + { 716, 1, 23, 1, 1041, 0 }, + { 812, 1, 23, 1, 1041, 0 }, + { 908, 1, 23, 1, 1041, 0 }, + { 1023, 1, 23, 1, 1041, 0 }, + { 5, 1, 23, 1, 1041, 0 }, + { 135, 1, 23, 1, 1041, 0 }, + { 265, 1, 23, 1, 1041, 0 }, + { 361, 1, 23, 1, 1041, 0 }, + { 457, 1, 23, 1, 1041, 0 }, + { 553, 1, 23, 1, 1041, 0 }, + { 649, 1, 23, 1, 1041, 0 }, + { 745, 1, 23, 1, 1041, 0 }, + { 841, 1, 23, 1, 1041, 0 }, + { 956, 1, 23, 1, 1041, 0 }, + { 39, 1, 23, 1, 1041, 0 }, + { 169, 1, 23, 1, 1041, 0 }, + { 299, 1, 23, 1, 1041, 0 }, + { 395, 1, 23, 1, 1041, 0 }, + { 491, 1, 23, 1, 1041, 0 }, + { 587, 1, 23, 1, 1041, 0 }, + { 683, 1, 23, 1, 1041, 0 }, + { 779, 1, 23, 1, 1041, 0 }, + { 875, 1, 23, 1, 1041, 0 }, + { 990, 1, 23, 1, 1041, 0 }, + { 73, 1, 23, 1, 1041, 0 }, + { 203, 1, 23, 1, 1041, 0 }, + { 110, 18, 1, 2, 977, 4 }, + { 240, 18, 1, 2, 977, 4 }, + { 336, 18, 1, 2, 977, 4 }, + { 432, 18, 1, 2, 977, 4 }, + { 528, 18, 1, 2, 977, 4 }, + { 624, 18, 1, 2, 977, 4 }, + { 720, 18, 1, 2, 977, 4 }, + { 816, 18, 1, 2, 977, 4 }, + { 912, 18, 1, 2, 977, 4 }, + { 1027, 18, 1, 2, 977, 4 }, + { 10, 18, 1, 2, 977, 4 }, + { 140, 18, 1, 2, 977, 4 }, + { 270, 18, 1, 2, 977, 4 }, + { 366, 18, 1, 2, 977, 4 }, + { 462, 18, 1, 2, 977, 4 }, + { 558, 18, 1, 2, 977, 4 }, + { 654, 18, 1, 2, 977, 4 }, + { 750, 18, 1, 2, 977, 4 }, + { 846, 18, 1, 2, 977, 4 }, + { 961, 18, 1, 2, 977, 4 }, + { 44, 18, 1, 2, 977, 4 }, + { 174, 18, 1, 2, 977, 4 }, + { 304, 18, 1, 2, 977, 4 }, + { 400, 18, 1, 2, 977, 4 }, + { 496, 18, 1, 2, 977, 4 }, + { 592, 18, 1, 2, 977, 4 }, + { 688, 18, 1, 2, 977, 4 }, + { 784, 18, 1, 2, 977, 4 }, + { 880, 18, 1, 2, 977, 4 }, + { 995, 18, 1, 2, 977, 4 }, + { 78, 18, 1, 2, 977, 4 }, + { 208, 18, 1, 2, 977, 4 }, + { 115, 53, 1, 3, 881, 4 }, + { 245, 53, 1, 3, 881, 4 }, + { 341, 53, 1, 3, 881, 4 }, + { 437, 53, 1, 3, 881, 4 }, + { 533, 53, 1, 3, 881, 4 }, + { 629, 53, 1, 3, 881, 4 }, + { 725, 53, 1, 3, 881, 4 }, + { 821, 53, 1, 3, 881, 4 }, + { 917, 53, 1, 3, 881, 4 }, + { 1032, 53, 1, 3, 881, 4 }, + { 16, 53, 1, 3, 881, 4 }, + { 146, 53, 1, 3, 881, 4 }, + { 276, 53, 1, 3, 881, 4 }, + { 372, 53, 1, 3, 881, 4 }, + { 468, 53, 1, 3, 881, 4 }, + { 564, 53, 1, 3, 881, 4 }, + { 660, 53, 1, 3, 881, 4 }, + { 756, 53, 1, 3, 881, 4 }, + { 852, 53, 1, 3, 881, 4 }, + { 967, 53, 1, 3, 881, 4 }, + { 50, 53, 1, 3, 881, 4 }, + { 180, 53, 1, 3, 881, 4 }, + { 310, 53, 1, 3, 881, 4 }, + { 406, 53, 1, 3, 881, 4 }, + { 502, 53, 1, 3, 881, 4 }, + { 598, 53, 1, 3, 881, 4 }, + { 694, 53, 1, 3, 881, 4 }, + { 790, 53, 1, 3, 881, 4 }, + { 886, 53, 1, 3, 881, 4 }, + { 1001, 53, 1, 3, 881, 4 }, + { 84, 53, 1, 3, 881, 4 }, + { 214, 53, 1, 3, 881, 4 }, + { 127, 59, 1, 0, 913, 2 }, + { 257, 59, 1, 0, 913, 2 }, + { 353, 59, 1, 0, 913, 2 }, + { 449, 59, 1, 0, 913, 2 }, + { 545, 59, 1, 0, 913, 2 }, + { 641, 59, 1, 0, 913, 2 }, + { 737, 59, 1, 0, 913, 2 }, + { 833, 59, 1, 0, 913, 2 }, + { 948, 59, 1, 0, 913, 2 }, + { 1043, 59, 1, 0, 913, 2 }, + { 30, 59, 1, 0, 913, 2 }, + { 160, 59, 1, 0, 913, 2 }, + { 290, 59, 1, 0, 913, 2 }, + { 386, 59, 1, 0, 913, 2 }, + { 482, 59, 1, 0, 913, 2 }, + { 578, 59, 1, 0, 913, 2 }, + { 674, 59, 1, 0, 913, 2 }, + { 770, 59, 1, 0, 913, 2 }, + { 866, 59, 1, 0, 913, 2 }, + { 981, 59, 1, 0, 913, 2 }, + { 64, 59, 1, 0, 913, 2 }, + { 194, 59, 1, 0, 913, 2 }, + { 324, 59, 1, 0, 913, 2 }, + { 420, 59, 1, 0, 913, 2 }, + { 516, 59, 1, 0, 913, 2 }, + { 612, 59, 1, 0, 913, 2 }, + { 708, 59, 1, 0, 913, 2 }, + { 804, 59, 1, 0, 913, 2 }, + { 900, 59, 1, 0, 913, 2 }, + { 1015, 59, 1, 0, 913, 2 }, + { 98, 59, 1, 0, 913, 2 }, + { 228, 59, 1, 0, 913, 2 }, + { 922, 49, 1, 0, 659, 2 }, + { 1115, 1, 51, 1, 659, 0 }, + { 1121, 1, 51, 1, 628, 0 }, + { 1127, 1, 51, 1, 628, 0 }, + { 1133, 1, 51, 1, 628, 0 }, + { 1139, 1, 51, 1, 628, 0 }, + { 1145, 1, 51, 1, 628, 0 }, + { 1151, 1, 51, 1, 628, 0 }, + { 1157, 1, 51, 1, 628, 0 }, + { 1170, 1, 47, 1, 596, 0 }, + { 1176, 1, 47, 1, 596, 0 }, + { 1182, 1, 47, 1, 596, 0 }, + { 1188, 1, 47, 1, 596, 0 }, + { 1194, 1, 47, 1, 596, 0 }, + { 1200, 1, 47, 1, 596, 0 }, + { 1206, 1, 47, 1, 596, 0 }, + { 1212, 1, 47, 1, 596, 0 }, + { 1218, 1, 45, 1, 564, 0 }, + { 1224, 1, 45, 1, 564, 0 }, + { 1230, 1, 45, 1, 564, 0 }, + { 1236, 1, 45, 1, 564, 0 }, + { 1242, 1, 45, 1, 564, 0 }, + { 1248, 1, 45, 1, 564, 0 }, + { 1254, 1, 45, 1, 564, 0 }, + { 1260, 1, 45, 1, 564, 0 }, + { 1056, 1, 43, 1, 532, 0 }, + { 1062, 1, 43, 1, 532, 0 }, + { 1068, 1, 43, 1, 532, 0 }, + { 1074, 1, 43, 1, 532, 0 }, + { 1080, 1, 43, 1, 532, 0 }, + { 1086, 1, 43, 1, 532, 0 }, + { 1092, 1, 43, 1, 532, 0 }, + { 1098, 1, 43, 1, 532, 0 }, +}; + + + // GPRC Register Class... + static const MCPhysReg GPRC[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP, + }; + + // GPRC Bit set. + static uint8_t GPRCBits[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // GPRC_NOR0 Register Class... + static const MCPhysReg GPRC_NOR0[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO, + }; + + // GPRC_NOR0 Bit set. + static uint8_t GPRC_NOR0Bits[] = { + 0x12, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, + }; + + // GPRC_and_GPRC_NOR0 Register Class... + static const MCPhysReg GPRC_and_GPRC_NOR0[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, + }; + + // GPRC_and_GPRC_NOR0 Bit set. + static uint8_t GPRC_and_GPRC_NOR0Bits[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, + }; + + // CRBITRC Register Class... + static const MCPhysReg CRBITRC[] = { + PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, + }; + + // CRBITRC Bit set. + static uint8_t CRBITRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, + }; + + // F4RC Register Class... + static const MCPhysReg F4RC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, + }; + + // F4RC Bit set. + static uint8_t F4RCBits[] = { + 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // CRRC Register Class... + static const MCPhysReg CRRC[] = { + PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4, + }; + + // CRRC Bit set. + static uint8_t CRRCBits[] = { + 0x00, 0xfc, 0x03, + }; + + // CARRYRC Register Class... + static const MCPhysReg CARRYRC[] = { + PPC_CARRY, + }; + + // CARRYRC Bit set. + static const uint8_t CARRYRCBits[] = { + 0x04, + }; + + // CTRRC Register Class... + static const MCPhysReg CTRRC[] = { + PPC_CTR, + }; + + // CTRRC Bit set. + static uint8_t CTRRCBits[] = { + 0x08, + }; + + // VRSAVERC Register Class... + static const MCPhysReg VRSAVERC[] = { + PPC_VRSAVE, + }; + + // VRSAVERC Bit set. + static uint8_t VRSAVERCBits[] = { + 0x80, + }; + + // VSFRC Register Class... + static const MCPhysReg VSFRC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, + }; + + // VSFRC Bit set. + static uint8_t VSFRCBits[] = { + 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // G8RC Register Class... + static const MCPhysReg G8RC[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, + }; + + // G8RC Bit set. + static uint8_t G8RCBits[] = { + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // G8RC_NOX0 Register Class... + static const MCPhysReg G8RC_NOX0[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8, + }; + + // G8RC_NOX0 Bit set. + static uint8_t G8RC_NOX0Bits[] = { + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, + }; + + // G8RC_and_G8RC_NOX0 Register Class... + static const MCPhysReg G8RC_and_G8RC_NOX0[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, + }; + + // G8RC_and_G8RC_NOX0 Bit set. + static uint8_t G8RC_and_G8RC_NOX0Bits[] = { + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, + }; + + // F8RC Register Class... + static const MCPhysReg F8RC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, + }; + + // F8RC Bit set. + static uint8_t F8RCBits[] = { + 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // VFRC Register Class... + static const MCPhysReg VFRC[] = { + PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, + }; + + // VFRC Bit set. + static uint8_t VFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // CTRRC8 Register Class... + static const MCPhysReg CTRRC8[] = { + PPC_CTR8, + }; + + // CTRRC8 Bit set. + static uint8_t CTRRC8Bits[] = { + 0x00, 0x00, 0x04, + }; + + // VSRC Register Class... + static const MCPhysReg VSRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20, + }; + + // VSRC Bit set. + static uint8_t VSRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, + }; + + // QSRC Register Class... + static MCPhysReg QSRC[] = { + PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, + }; + + // QSRC Bit set. + static uint8_t QSRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // VRRC Register Class... + static const MCPhysReg VRRC[] = { + PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, + }; + + // VRRC Bit set. + static uint8_t VRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // VSHRC Register Class... + static const MCPhysReg VSHRC[] = { + PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20, + }; + + // VSHRC Bit set. + static uint8_t VSHRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // VSLRC Register Class... + static const MCPhysReg VSLRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, + }; + + // VSLRC Bit set. + static uint8_t VSLRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // QBRC Register Class... + static MCPhysReg QBRC[] = { + PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, + }; + + // QBRC Bit set. + static uint8_t QBRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // QFRC Register Class... + static MCPhysReg QFRC[] = { + PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, + }; + + // QFRC Bit set. + static uint8_t QFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + +static MCRegisterClass PPCMCRegisterClasses[] = { + { GPRC, GPRCBits, 102, 34, sizeof(GPRCBits), PPC_GPRCRegClassID, 4, 4, 1, 1 }, + { GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC_GPRC_NOR0RegClassID, 4, 4, 1, 1 }, + { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC_GPRC_and_GPRC_NOR0RegClassID, 4, 4, 1, 1 }, + { CRBITRC, CRBITRCBits, 133, 32, sizeof(CRBITRCBits), PPC_CRBITRCRegClassID, 4, 4, 1, 1 }, + { F4RC, F4RCBits, 45, 32, sizeof(F4RCBits), PPC_F4RCRegClassID, 4, 4, 1, 1 }, + { CRRC, CRRCBits, 107, 8, sizeof(CRRCBits), PPC_CRRCRegClassID, 4, 4, 1, 1 }, + { CARRYRC, CARRYRCBits, 141, 1, sizeof(CARRYRCBits), PPC_CARRYRCRegClassID, 4, 4, -1, 1 }, + { CTRRC, CTRRCBits, 112, 1, sizeof(CTRRCBits), PPC_CTRRCRegClassID, 4, 4, 1, 0 }, + { VRSAVERC, VRSAVERCBits, 65, 1, sizeof(VRSAVERCBits), PPC_VRSAVERCRegClassID, 4, 4, 1, 1 }, + { VSFRC, VSFRCBits, 79, 64, sizeof(VSFRCBits), PPC_VSFRCRegClassID, 8, 8, 1, 1 }, + { G8RC, G8RCBits, 55, 34, sizeof(G8RCBits), PPC_G8RCRegClassID, 8, 8, 1, 1 }, + { G8RC_NOX0, G8RC_NOX0Bits, 28, 34, sizeof(G8RC_NOX0Bits), PPC_G8RC_NOX0RegClassID, 8, 8, 1, 1 }, + { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 19, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC_G8RC_and_G8RC_NOX0RegClassID, 8, 8, 1, 1 }, + { F8RC, F8RCBits, 50, 32, sizeof(F8RCBits), PPC_F8RCRegClassID, 8, 8, 1, 1 }, + { VFRC, VFRCBits, 85, 32, sizeof(VFRCBits), PPC_VFRCRegClassID, 8, 8, 1, 1 }, + { CTRRC8, CTRRC8Bits, 38, 1, sizeof(CTRRC8Bits), PPC_CTRRC8RegClassID, 8, 8, 1, 0 }, + { VSRC, VSRCBits, 128, 64, sizeof(VSRCBits), PPC_VSRCRegClassID, 16, 16, 1, 1 }, + { QSRC, QSRCBits, 123, 32, sizeof(QSRCBits), PPC_QSRCRegClassID, 16, 16, 1, 1 }, + { VRRC, VRRCBits, 118, 32, sizeof(VRRCBits), PPC_VRRCRegClassID, 16, 16, 1, 1 }, + { VSHRC, VSHRCBits, 90, 32, sizeof(VSHRCBits), PPC_VSHRCRegClassID, 16, 16, 1, 1 }, + { VSLRC, VSLRCBits, 96, 32, sizeof(VSLRCBits), PPC_VSLRCRegClassID, 16, 16, 1, 1 }, + { QBRC, QBRCBits, 60, 32, sizeof(QBRCBits), PPC_QBRCRegClassID, 32, 32, 1, 1 }, + { QFRC, QFRCBits, 74, 32, sizeof(QFRCBits), PPC_QFRCRegClassID, 32, 32, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCGenSubtargetInfo.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenSubtargetInfo.inc new file mode 100644 index 0000000..176e029 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCGenSubtargetInfo.inc @@ -0,0 +1,73 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +#define PPC_DeprecatedDST (1ULL << 0) +#define PPC_DeprecatedMFTB (1ULL << 1) +#define PPC_Directive32 (1ULL << 2) +#define PPC_Directive64 (1ULL << 3) +#define PPC_Directive440 (1ULL << 4) +#define PPC_Directive601 (1ULL << 5) +#define PPC_Directive602 (1ULL << 6) +#define PPC_Directive603 (1ULL << 7) +#define PPC_Directive604 (1ULL << 8) +#define PPC_Directive620 (1ULL << 9) +#define PPC_Directive750 (1ULL << 10) +#define PPC_Directive970 (1ULL << 11) +#define PPC_Directive7400 (1ULL << 12) +#define PPC_DirectiveA2 (1ULL << 13) +#define PPC_DirectiveE500mc (1ULL << 14) +#define PPC_DirectiveE5500 (1ULL << 15) +#define PPC_DirectivePwr3 (1ULL << 16) +#define PPC_DirectivePwr4 (1ULL << 17) +#define PPC_DirectivePwr5 (1ULL << 18) +#define PPC_DirectivePwr5x (1ULL << 19) +#define PPC_DirectivePwr6 (1ULL << 20) +#define PPC_DirectivePwr6x (1ULL << 21) +#define PPC_DirectivePwr7 (1ULL << 22) +#define PPC_DirectivePwr8 (1ULL << 23) +#define PPC_Feature64Bit (1ULL << 24) +#define PPC_Feature64BitRegs (1ULL << 25) +#define PPC_FeatureAltivec (1ULL << 26) +#define PPC_FeatureBookE (1ULL << 27) +#define PPC_FeatureCMPB (1ULL << 28) +#define PPC_FeatureCRBits (1ULL << 29) +#define PPC_FeatureE500 (1ULL << 30) +#define PPC_FeatureFCPSGN (1ULL << 31) +#define PPC_FeatureFPCVT (1ULL << 32) +#define PPC_FeatureFPRND (1ULL << 33) +#define PPC_FeatureFRE (1ULL << 34) +#define PPC_FeatureFRES (1ULL << 35) +#define PPC_FeatureFRSQRTE (1ULL << 36) +#define PPC_FeatureFRSQRTES (1ULL << 37) +#define PPC_FeatureFSqrt (1ULL << 38) +#define PPC_FeatureICBT (1ULL << 39) +#define PPC_FeatureISEL (1ULL << 40) +#define PPC_FeatureInvariantFunctionDescriptors (1ULL << 41) +#define PPC_FeatureLDBRX (1ULL << 42) +#define PPC_FeatureLFIWAX (1ULL << 43) +#define PPC_FeatureMFOCRF (1ULL << 44) +#define PPC_FeatureMSYNC (1ULL << 45) +#define PPC_FeatureP8Altivec (1ULL << 46) +#define PPC_FeatureP8Vector (1ULL << 47) +#define PPC_FeaturePOPCNTD (1ULL << 48) +#define PPC_FeaturePPC4xx (1ULL << 49) +#define PPC_FeaturePPC6xx (1ULL << 50) +#define PPC_FeatureQPX (1ULL << 51) +#define PPC_FeatureRecipPrec (1ULL << 52) +#define PPC_FeatureSPE (1ULL << 53) +#define PPC_FeatureSTFIWX (1ULL << 54) +#define PPC_FeatureVSX (1ULL << 55) + +#endif // GET_SUBTARGETINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.c b/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.c new file mode 100644 index 0000000..c46d067 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.c @@ -0,0 +1,1002 @@ +//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an PPC MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_POWERPC + +#include +#include +#include + +#include "PPCInstPrinter.h" +#include "PPCPredicates.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "PPCMapping.h" + +#ifndef CAPSTONE_DIET +static const char *getRegisterName(unsigned RegNo); +#endif + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); +static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O); +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info); +static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info); +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +#if 0 +static void printRegName(SStream *OS, unsigned RegNo) +{ + char *RegName = getRegisterName(RegNo); + + if (RegName[0] == 'q' /* QPX */) { + // The system toolchain on the BG/Q does not understand QPX register names + // in .cfi_* directives, so print the name of the floating-point + // subregister instead. + RegName[0] = 'f'; + } + + SStream_concat0(OS, RegName); +} +#endif + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + + if (status) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->ppc.op_count++; + } +} + +void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // check if this insn has branch hint + if (strrchr(insn_asm, '+') != NULL && !strstr(insn_asm, ".+")) { + insn->detail->ppc.bh = PPC_BH_PLUS; + } else if (strrchr(insn_asm, '-') != NULL) { + insn->detail->ppc.bh = PPC_BH_MINUS; + } +} + +#define GET_INSTRINFO_ENUM +#include "PPCGenInstrInfo.inc" + +static int isBOCTRBranch(unsigned int op) +{ + return ((op >= PPC_BDNZ) && (op <= PPC_BDZp)); +} + +void PPC_printInst(MCInst *MI, SStream *O, void *Info) +{ + char *mnem; + + // Check for slwi/srwi mnemonics. + if (MCInst_getOpcode(MI) == PPC_RLWINM) { + unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); + unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); + unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4)); + bool useSubstituteMnemonic = false; + + if (SH <= 31 && MB == 0 && ME == (31-SH)) { + SStream_concat0(O, "slwi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SLWI); + useSubstituteMnemonic = true; + } + + if (SH <= 31 && MB == (32-SH) && ME == 31) { + SStream_concat0(O, "srwi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SRWI); + useSubstituteMnemonic = true; + SH = 32-SH; + } + + if (useSubstituteMnemonic) { + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + if (SH > HEX_THRESHOLD) + SStream_concat(O, ", 0x%x", (unsigned int)SH); + else + SStream_concat(O, ", %u", (unsigned int)SH); + + if (MI->csh->detail) { + cs_ppc *ppc = &MI->flat_insn->detail->ppc; + + ppc->operands[ppc->op_count].type = PPC_OP_IMM; + ppc->operands[ppc->op_count].imm = SH; + ++ppc->op_count; + } + + return; + } + } + + if ((MCInst_getOpcode(MI) == PPC_OR || MCInst_getOpcode(MI) == PPC_OR8) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) { + SStream_concat0(O, "mr\t"); + MCInst_setOpcodePub(MI, PPC_INS_MR); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + } + + if (MCInst_getOpcode(MI) == PPC_RLDICR) { + unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); + unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); + // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH + if (63-SH == ME) { + SStream_concat0(O, "sldi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SLDI); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + if (SH > HEX_THRESHOLD) + SStream_concat(O, ", 0x%x", (unsigned int)SH); + else + SStream_concat(O, ", %u", (unsigned int)SH); + + return; + } + } + + if ((MCInst_getOpcode(MI) == PPC_gBC)||(MCInst_getOpcode(MI) == PPC_gBCA)|| + (MCInst_getOpcode(MI) == PPC_gBCL)||(MCInst_getOpcode(MI) == PPC_gBCLA)) { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2)); + bd = SignExtend64(bd, 14); + MCOperand_setImm(MCInst_getOperand(MI, 2),bd); + } + + if (isBOCTRBranch(MCInst_getOpcode(MI))) { + if (MCOperand_isImm(MCInst_getOperand(MI,0))) + { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); + bd = SignExtend64(bd, 14); + MCOperand_setImm(MCInst_getOperand(MI, 0),bd); + } + } + + if ((MCInst_getOpcode(MI) == PPC_B)||(MCInst_getOpcode(MI) == PPC_BA)|| + (MCInst_getOpcode(MI) == PPC_BL)||(MCInst_getOpcode(MI) == PPC_BLA)) { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); + bd = SignExtend64(bd, 24); + MCOperand_setImm(MCInst_getOperand(MI, 0),bd); + } + + // consider our own alias instructions first + mnem = printAliasInstrEx(MI, O, Info); + if (!mnem) + mnem = printAliasInstr(MI, O, Info); + + if (mnem != NULL) { + if (strlen(mnem) > 0) { + struct ppc_alias alias; + // check to remove the last letter of ('.', '-', '+') + if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.') + mnem[strlen(mnem) - 1] = '\0'; + + if (PPC_alias_insn(mnem, &alias)) { + MCInst_setOpcodePub(MI, alias.id); + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc; + } + } + } + + cs_mem_free(mnem); + } else + printInstruction(MI, O, NULL); +} + +enum ppc_bc_hint { + PPC_BC_LT_MINUS = (0 << 5) | 14, + PPC_BC_LE_MINUS = (1 << 5) | 6, + PPC_BC_EQ_MINUS = (2 << 5) | 14, + PPC_BC_GE_MINUS = (0 << 5) | 6, + PPC_BC_GT_MINUS = (1 << 5) | 14, + PPC_BC_NE_MINUS = (2 << 5) | 6, + PPC_BC_UN_MINUS = (3 << 5) | 14, + PPC_BC_NU_MINUS = (3 << 5) | 6, + PPC_BC_LT_PLUS = (0 << 5) | 15, + PPC_BC_LE_PLUS = (1 << 5) | 7, + PPC_BC_EQ_PLUS = (2 << 5) | 15, + PPC_BC_GE_PLUS = (0 << 5) | 7, + PPC_BC_GT_PLUS = (1 << 5) | 15, + PPC_BC_NE_PLUS = (2 << 5) | 7, + PPC_BC_UN_PLUS = (3 << 5) | 15, + PPC_BC_NU_PLUS = (3 << 5) | 7, +}; + +// normalize CC to remove _MINUS & _PLUS +static int cc_normalize(int cc) +{ + switch(cc) { + default: return cc; + case PPC_BC_LT_MINUS: return PPC_BC_LT; + case PPC_BC_LE_MINUS: return PPC_BC_LE; + case PPC_BC_EQ_MINUS: return PPC_BC_EQ; + case PPC_BC_GE_MINUS: return PPC_BC_GE; + case PPC_BC_GT_MINUS: return PPC_BC_GT; + case PPC_BC_NE_MINUS: return PPC_BC_NE; + case PPC_BC_UN_MINUS: return PPC_BC_UN; + case PPC_BC_NU_MINUS: return PPC_BC_NU; + case PPC_BC_LT_PLUS : return PPC_BC_LT; + case PPC_BC_LE_PLUS : return PPC_BC_LE; + case PPC_BC_EQ_PLUS : return PPC_BC_EQ; + case PPC_BC_GE_PLUS : return PPC_BC_GE; + case PPC_BC_GT_PLUS : return PPC_BC_GT; + case PPC_BC_NE_PLUS : return PPC_BC_NE; + case PPC_BC_UN_PLUS : return PPC_BC_UN; + case PPC_BC_NU_PLUS : return PPC_BC_NU; + } +} + +static void printPredicateOperand(MCInst *MI, unsigned OpNo, + SStream *O, const char *Modifier) +{ + unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + + MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code); + + if (!strcmp(Modifier, "cc")) { + switch ((ppc_predicate)Code) { + default: // unreachable + case PPC_PRED_LT_MINUS: + case PPC_PRED_LT_PLUS: + case PPC_PRED_LT: + SStream_concat0(O, "lt"); + return; + case PPC_PRED_LE_MINUS: + case PPC_PRED_LE_PLUS: + case PPC_PRED_LE: + SStream_concat0(O, "le"); + return; + case PPC_PRED_EQ_MINUS: + case PPC_PRED_EQ_PLUS: + case PPC_PRED_EQ: + SStream_concat0(O, "eq"); + return; + case PPC_PRED_GE_MINUS: + case PPC_PRED_GE_PLUS: + case PPC_PRED_GE: + SStream_concat0(O, "ge"); + return; + case PPC_PRED_GT_MINUS: + case PPC_PRED_GT_PLUS: + case PPC_PRED_GT: + SStream_concat0(O, "gt"); + return; + case PPC_PRED_NE_MINUS: + case PPC_PRED_NE_PLUS: + case PPC_PRED_NE: + SStream_concat0(O, "ne"); + return; + case PPC_PRED_UN_MINUS: + case PPC_PRED_UN_PLUS: + case PPC_PRED_UN: + SStream_concat0(O, "un"); + return; + case PPC_PRED_NU_MINUS: + case PPC_PRED_NU_PLUS: + case PPC_PRED_NU: + SStream_concat0(O, "nu"); + return; + case PPC_PRED_BIT_SET: + case PPC_PRED_BIT_UNSET: + // llvm_unreachable("Invalid use of bit predicate code"); + SStream_concat0(O, "invalid-predicate"); + return; + } + } + + if (!strcmp(Modifier, "pm")) { + switch ((ppc_predicate)Code) { + case PPC_PRED_LT: + case PPC_PRED_LE: + case PPC_PRED_EQ: + case PPC_PRED_GE: + case PPC_PRED_GT: + case PPC_PRED_NE: + case PPC_PRED_UN: + case PPC_PRED_NU: + return; + case PPC_PRED_LT_MINUS: + case PPC_PRED_LE_MINUS: + case PPC_PRED_EQ_MINUS: + case PPC_PRED_GE_MINUS: + case PPC_PRED_GT_MINUS: + case PPC_PRED_NE_MINUS: + case PPC_PRED_UN_MINUS: + case PPC_PRED_NU_MINUS: + SStream_concat0(O, "-"); + return; + case PPC_PRED_LT_PLUS: + case PPC_PRED_LE_PLUS: + case PPC_PRED_EQ_PLUS: + case PPC_PRED_GE_PLUS: + case PPC_PRED_GT_PLUS: + case PPC_PRED_NE_PLUS: + case PPC_PRED_UN_PLUS: + case PPC_PRED_NU_PLUS: + SStream_concat0(O, "+"); + return; + case PPC_PRED_BIT_SET: + case PPC_PRED_BIT_UNSET: + // llvm_unreachable("Invalid use of bit predicate code"); + SStream_concat0(O, "invalid-predicate"); + return; + default: // unreachable + return; + } + // llvm_unreachable("Invalid predicate code"); + } + + //assert(StringRef(Modifier) == "reg" && + // "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!"); + printOperand(MI, OpNo + 1, O); +} + +static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + //assert(Value <= 3 && "Invalid u2imm argument!"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + //assert(Value <= 15 && "Invalid u4imm argument!"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + Value = SignExtend32(Value, 5); + + printInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + //assert(Value <= 31 && "Invalid u5imm argument!"); + printUInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + //assert(Value <= 63 && "Invalid u6imm argument!"); + printUInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + + // assert(Value <= 4095 && "Invalid u12imm argument!"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Imm); + else + SStream_concat(O, "%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; + MI->flat_insn->detail->ppc.op_count++; + } + } else + printOperand(MI, OpNo, O); +} + +static void printS16ImmOperand_Mem(MCInst *MI, unsigned OpNo, SStream *O) +{ + if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + + if (Imm >= 0) { + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Imm); + else + SStream_concat(O, "%u", Imm); + } else { + if (Imm < -HEX_THRESHOLD) + SStream_concat(O, "-0x%x", -Imm); + else + SStream_concat(O, "-%u", -Imm); + } + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; + MI->flat_insn->detail->ppc.op_count++; + } + } + } else + printOperand(MI, OpNo, O); +} + +static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Imm); + else + SStream_concat(O, "%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; + MI->flat_insn->detail->ppc.op_count++; + } + } else + printOperand(MI, OpNo, O); +} + +static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + printOperand(MI, OpNo, O); + return; + } + + // Branches can take an immediate operand. This is used by the branch + // selection pass to print .+8, an eight byte displacement from the PC. + printAbsBranchOperand(MI, OpNo, O); +} + +static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + int64_t imm; + + if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + printOperand(MI, OpNo, O); + return; + } + + imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4; + + if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) { + imm = MI->address + imm; + } + + SStream_concat(O, "0x%"PRIx64, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; + MI->flat_insn->detail->ppc.op_count++; + } +} + + +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" + +static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O) +{ + unsigned RegNo, tmp; + unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo)); + + switch (CCReg) { + default: // llvm_unreachable("Unknown CR register"); + case PPC_CR0: RegNo = 0; break; + case PPC_CR1: RegNo = 1; break; + case PPC_CR2: RegNo = 2; break; + case PPC_CR3: RegNo = 3; break; + case PPC_CR4: RegNo = 4; break; + case PPC_CR5: RegNo = 5; break; + case PPC_CR6: RegNo = 6; break; + case PPC_CR7: RegNo = 7; break; + } + + tmp = 0x80 >> RegNo; + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "0x%x", tmp); + else + SStream_concat(O, "%u", tmp); +} + +static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O) +{ + set_mem_access(MI, true); + + printS16ImmOperand_Mem(MI, OpNo, O); + + SStream_concat0(O, "("); + + if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0) + SStream_concat0(O, "0"); + else + printOperand(MI, OpNo + 1, O); + + SStream_concat0(O, ")"); + set_mem_access(MI, false); +} + +static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O) +{ + // When used as the base register, r0 reads constant zero rather than + // the value contained in the register. For this reason, the darwin + // assembler requires that we print r0 as 0 (no r) when used as the base. + if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0) + SStream_concat0(O, "0"); + else + printOperand(MI, OpNo, O); + SStream_concat0(O, ", "); + + printOperand(MI, OpNo + 1, O); +} + +static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) +{ + set_mem_access(MI, true); + //printBranchOperand(MI, OpNo, O); + + // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must + // come at the _end_ of the expression. + + SStream_concat0(O, "("); + printOperand(MI, OpNo + 1, O); + SStream_concat0(O, ")"); + set_mem_access(MI, false); +} + +#ifndef CAPSTONE_DIET +/// stripRegisterPrefix - This method strips the character prefix from a +/// register name so that only the number is left. Used by for linux asm. +static const char *stripRegisterPrefix(const char *RegName) +{ + switch (RegName[0]) { + case 'r': + case 'f': + case 'q': // for QPX + case 'v': + if (RegName[1] == 's') + return RegName + 2; + return RegName + 1; + case 'c': + if (RegName[1] == 'r') + return RegName + 2; + } + + return RegName; +} +#endif + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + unsigned reg = MCOperand_getReg(Op); +#ifndef CAPSTONE_DIET + const char *RegName = getRegisterName(reg); +#endif + // map to public register + reg = PPC_map_register(reg); +#ifndef CAPSTONE_DIET + // The linux and AIX assembler does not take register prefixes. + if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) + RegName = stripRegisterPrefix(RegName); + + SStream_concat0(O, RegName); +#endif + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; + MI->flat_insn->detail->ppc.op_count++; + } + } + + return; + } + + if (MCOperand_isImm(Op)) { + int32_t imm = (int32_t)MCOperand_getImm(Op); + printInt32(O, imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; + MI->flat_insn->detail->ppc.op_count++; + } + } + } +} + +static void op_addImm(MCInst *MI, int v) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void op_addReg(MCInst *MI, unsigned int reg) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; + MI->flat_insn->detail->ppc.op_count++; + } +} + +static void op_addBC(MCInst *MI, unsigned int bc) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.bc = (ppc_bc)bc; + } +} + +#define CREQ (0) +#define CRGT (1) +#define CRLT (2) +#define CRUN (3) + +static int getBICRCond(int bi) +{ + return (bi-PPC_CR0EQ) >> 3; +} + +static int getBICR(int bi) +{ + return ((bi - PPC_CR0EQ) & 7) + PPC_CR0; +} + +static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info) +{ +#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + SStream ss; + const char *opCode; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + int decCtr = false, needComma = false; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + + SStream_Init(&ss); + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case PPC_gBC: + opCode = "b%s"; + break; + case PPC_gBCA: + opCode = "b%sa"; + break; + case PPC_gBCCTR: + opCode = "b%sctr"; + break; + case PPC_gBCCTRL: + opCode = "b%sctrl"; + break; + case PPC_gBCL: + opCode = "b%sl"; + break; + case PPC_gBCLA: + opCode = "b%sla"; + break; + case PPC_gBCLR: + opCode = "b%slr"; + break; + case PPC_gBCLRL: + opCode = "b%slrl"; + break; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) { + SStream_concat(&ss, opCode, "dnzf"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) { + SStream_concat(&ss, opCode, "dzf"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + switch(cr) { + case CREQ: + SStream_concat(&ss, opCode, "ne"); + break; + case CRGT: + SStream_concat(&ss, opCode, "le"); + break; + case CRLT: + SStream_concat(&ss, opCode, "ge"); + break; + case CRUN: + SStream_concat(&ss, opCode, "ns"); + break; + } + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7) + SStream_concat0(&ss, "+"); + + decCtr = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) { + SStream_concat(&ss, opCode, "dnzt"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) { + SStream_concat(&ss, opCode, "dzt"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + switch(cr) { + case CREQ: + SStream_concat(&ss, opCode, "eq"); + break; + case CRGT: + SStream_concat(&ss, opCode, "gt"); + break; + case CRLT: + SStream_concat(&ss, opCode, "lt"); + break; + case CRUN: + SStream_concat(&ss, opCode, "so"); + break; + } + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) + SStream_concat0(&ss, "+"); + + decCtr = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) { + SStream_concat(&ss, opCode, "dnz"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25) + SStream_concat0(&ss, "+"); + + needComma = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) { + SStream_concat(&ss, opCode, "dz"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27) + SStream_concat0(&ss, "+"); + + needComma = false; + } + + if (MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) { + int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1))); + + if (decCtr) { + needComma = true; + SStream_concat0(&ss, " "); + + if (cr > PPC_CR0) { + SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0); + } + + cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + switch(cr) { + case CREQ: + SStream_concat0(&ss, "eq"); + op_addBC(MI, PPC_BC_EQ); + break; + case CRGT: + SStream_concat0(&ss, "gt"); + op_addBC(MI, PPC_BC_GT); + break; + case CRLT: + SStream_concat0(&ss, "lt"); + op_addBC(MI, PPC_BC_LT); + break; + case CRUN: + SStream_concat0(&ss, "so"); + op_addBC(MI, PPC_BC_SO); + break; + } + + cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1))); + if (cr > PPC_CR0) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_CRX; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.scale = 4; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.reg = PPC_REG_CR0 + cr - PPC_CR0; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.cond = MI->flat_insn->detail->ppc.bc; + MI->flat_insn->detail->ppc.op_count++; + } + } + } else { + if (cr > PPC_CR0) { + needComma = true; + SStream_concat(&ss, " cr%d", cr - PPC_CR0); + op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0); + } + } + } + + if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) { + if (needComma) + SStream_concat0(&ss, ","); + + SStream_concat0(&ss, " $\xFF\x03\x01"); + } + + tmp = cs_strdup(ss.buffer); + AsmMnem = tmp; + for(AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + + return tmp; +} + +#define PRINT_ALIAS_INSTR +#include "PPCGenAsmWriter.inc" + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.h b/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.h new file mode 100644 index 0000000..3ab6c8a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCInstPrinter.h @@ -0,0 +1,15 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_PPCINSTPRINTER_H +#define CS_PPCINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void PPC_printInst(MCInst *MI, SStream *O, void *Info); + +void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.c b/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.c new file mode 100644 index 0000000..ddfcc80 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.c @@ -0,0 +1,1703 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_POWERPC + +#include // debug +#include + +#include "../../utils.h" + +#include "PPCMapping.h" + +#define GET_INSTRINFO_ENUM +#include "PPCGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { PPC_REG_INVALID, NULL }, + + { PPC_REG_CARRY, "ca" }, + { PPC_REG_CR0, "cr0" }, + { PPC_REG_CR1, "cr1" }, + { PPC_REG_CR2, "cr2" }, + { PPC_REG_CR3, "cr3" }, + { PPC_REG_CR4, "cr4" }, + { PPC_REG_CR5, "cr5" }, + { PPC_REG_CR6, "cr6" }, + { PPC_REG_CR7, "cr7" }, + { PPC_REG_CTR, "ctr" }, + { PPC_REG_F0, "f0" }, + { PPC_REG_F1, "f1" }, + { PPC_REG_F2, "f2" }, + { PPC_REG_F3, "f3" }, + { PPC_REG_F4, "f4" }, + { PPC_REG_F5, "f5" }, + { PPC_REG_F6, "f6" }, + { PPC_REG_F7, "f7" }, + { PPC_REG_F8, "f8" }, + { PPC_REG_F9, "f9" }, + { PPC_REG_F10, "f10" }, + { PPC_REG_F11, "f11" }, + { PPC_REG_F12, "f12" }, + { PPC_REG_F13, "f13" }, + { PPC_REG_F14, "f14" }, + { PPC_REG_F15, "f15" }, + { PPC_REG_F16, "f16" }, + { PPC_REG_F17, "f17" }, + { PPC_REG_F18, "f18" }, + { PPC_REG_F19, "f19" }, + { PPC_REG_F20, "f20" }, + { PPC_REG_F21, "f21" }, + { PPC_REG_F22, "f22" }, + { PPC_REG_F23, "f23" }, + { PPC_REG_F24, "f24" }, + { PPC_REG_F25, "f25" }, + { PPC_REG_F26, "f26" }, + { PPC_REG_F27, "f27" }, + { PPC_REG_F28, "f28" }, + { PPC_REG_F29, "f29" }, + { PPC_REG_F30, "f30" }, + { PPC_REG_F31, "f31" }, + { PPC_REG_LR, "lr" }, + { PPC_REG_R0, "r0" }, + { PPC_REG_R1, "r1" }, + { PPC_REG_R2, "r2" }, + { PPC_REG_R3, "r3" }, + { PPC_REG_R4, "r4" }, + { PPC_REG_R5, "r5" }, + { PPC_REG_R6, "r6" }, + { PPC_REG_R7, "r7" }, + { PPC_REG_R8, "r8" }, + { PPC_REG_R9, "r9" }, + { PPC_REG_R10, "r10" }, + { PPC_REG_R11, "r11" }, + { PPC_REG_R12, "r12" }, + { PPC_REG_R13, "r13" }, + { PPC_REG_R14, "r14" }, + { PPC_REG_R15, "r15" }, + { PPC_REG_R16, "r16" }, + { PPC_REG_R17, "r17" }, + { PPC_REG_R18, "r18" }, + { PPC_REG_R19, "r19" }, + { PPC_REG_R20, "r20" }, + { PPC_REG_R21, "r21" }, + { PPC_REG_R22, "r22" }, + { PPC_REG_R23, "r23" }, + { PPC_REG_R24, "r24" }, + { PPC_REG_R25, "r25" }, + { PPC_REG_R26, "r26" }, + { PPC_REG_R27, "r27" }, + { PPC_REG_R28, "r28" }, + { PPC_REG_R29, "r29" }, + { PPC_REG_R30, "r30" }, + { PPC_REG_R31, "r31" }, + { PPC_REG_V0, "v0" }, + { PPC_REG_V1, "v1" }, + { PPC_REG_V2, "v2" }, + { PPC_REG_V3, "v3" }, + { PPC_REG_V4, "v4" }, + { PPC_REG_V5, "v5" }, + { PPC_REG_V6, "v6" }, + { PPC_REG_V7, "v7" }, + { PPC_REG_V8, "v8" }, + { PPC_REG_V9, "v9" }, + { PPC_REG_V10, "v10" }, + { PPC_REG_V11, "v11" }, + { PPC_REG_V12, "v12" }, + { PPC_REG_V13, "v13" }, + { PPC_REG_V14, "v14" }, + { PPC_REG_V15, "v15" }, + { PPC_REG_V16, "v16" }, + { PPC_REG_V17, "v17" }, + { PPC_REG_V18, "v18" }, + { PPC_REG_V19, "v19" }, + { PPC_REG_V20, "v20" }, + { PPC_REG_V21, "v21" }, + { PPC_REG_V22, "v22" }, + { PPC_REG_V23, "v23" }, + { PPC_REG_V24, "v24" }, + { PPC_REG_V25, "v25" }, + { PPC_REG_V26, "v26" }, + { PPC_REG_V27, "v27" }, + { PPC_REG_V28, "v28" }, + { PPC_REG_V29, "v29" }, + { PPC_REG_V30, "v30" }, + { PPC_REG_V31, "v31" }, + { PPC_REG_VRSAVE, "vrsave" }, + { PPC_REG_VS0, "vs0"}, + { PPC_REG_VS1, "vs1"}, + { PPC_REG_VS2, "vs2"}, + { PPC_REG_VS3, "vs3"}, + { PPC_REG_VS4, "vs4"}, + { PPC_REG_VS5, "vs5"}, + { PPC_REG_VS6, "vs6"}, + { PPC_REG_VS7, "vs7"}, + { PPC_REG_VS8, "vs8"}, + { PPC_REG_VS9, "vs9"}, + { PPC_REG_VS10, "vs10"}, + { PPC_REG_VS11, "vs11"}, + { PPC_REG_VS12, "vs12"}, + { PPC_REG_VS13, "vs13"}, + { PPC_REG_VS14, "vs14"}, + { PPC_REG_VS15, "vs15"}, + { PPC_REG_VS16, "vs16"}, + { PPC_REG_VS17, "vs17"}, + { PPC_REG_VS18, "vs18"}, + { PPC_REG_VS19, "vs19"}, + { PPC_REG_VS20, "vs20"}, + { PPC_REG_VS21, "vs21"}, + { PPC_REG_VS22, "vs22"}, + { PPC_REG_VS23, "vs23"}, + { PPC_REG_VS24, "vs24"}, + { PPC_REG_VS25, "vs25"}, + { PPC_REG_VS26, "vs26"}, + { PPC_REG_VS27, "vs27"}, + { PPC_REG_VS28, "vs28"}, + { PPC_REG_VS29, "vs29"}, + { PPC_REG_VS30, "vs30"}, + { PPC_REG_VS31, "vs31"}, + { PPC_REG_VS32, "vs32"}, + { PPC_REG_VS33, "vs33"}, + { PPC_REG_VS34, "vs34"}, + { PPC_REG_VS35, "vs35"}, + { PPC_REG_VS36, "vs36"}, + { PPC_REG_VS37, "vs37"}, + { PPC_REG_VS38, "vs38"}, + { PPC_REG_VS39, "vs39"}, + { PPC_REG_VS40, "vs40"}, + { PPC_REG_VS41, "vs41"}, + { PPC_REG_VS42, "vs42"}, + { PPC_REG_VS43, "vs43"}, + { PPC_REG_VS44, "vs44"}, + { PPC_REG_VS45, "vs45"}, + { PPC_REG_VS46, "vs46"}, + { PPC_REG_VS47, "vs47"}, + { PPC_REG_VS48, "vs48"}, + { PPC_REG_VS49, "vs49"}, + { PPC_REG_VS50, "vs50"}, + { PPC_REG_VS51, "vs51"}, + { PPC_REG_VS52, "vs52"}, + { PPC_REG_VS53, "vs53"}, + { PPC_REG_VS54, "vs54"}, + { PPC_REG_VS55, "vs55"}, + { PPC_REG_VS56, "vs56"}, + { PPC_REG_VS57, "vs57"}, + { PPC_REG_VS58, "vs58"}, + { PPC_REG_VS59, "vs59"}, + { PPC_REG_VS60, "vs60"}, + { PPC_REG_VS61, "vs61"}, + { PPC_REG_VS62, "vs62"}, + { PPC_REG_VS63, "vs63"}, + { PPC_REG_Q0, "q0" }, + { PPC_REG_Q1, "q1" }, + { PPC_REG_Q2, "q2" }, + { PPC_REG_Q3, "q3" }, + { PPC_REG_Q4, "q4" }, + { PPC_REG_Q5, "q5" }, + { PPC_REG_Q6, "q6" }, + { PPC_REG_Q7, "q7" }, + { PPC_REG_Q8, "q8" }, + { PPC_REG_Q9, "q9" }, + { PPC_REG_Q10, "q10" }, + { PPC_REG_Q11, "q11" }, + { PPC_REG_Q12, "q12" }, + { PPC_REG_Q13, "q13" }, + { PPC_REG_Q14, "q14" }, + { PPC_REG_Q15, "q15" }, + { PPC_REG_Q16, "q16" }, + { PPC_REG_Q17, "q17" }, + { PPC_REG_Q18, "q18" }, + { PPC_REG_Q19, "q19" }, + { PPC_REG_Q20, "q20" }, + { PPC_REG_Q21, "q21" }, + { PPC_REG_Q22, "q22" }, + { PPC_REG_Q23, "q23" }, + { PPC_REG_Q24, "q24" }, + { PPC_REG_Q25, "q25" }, + { PPC_REG_Q26, "q26" }, + { PPC_REG_Q27, "q27" }, + { PPC_REG_Q28, "q28" }, + { PPC_REG_Q29, "q29" }, + { PPC_REG_Q30, "q30" }, + { PPC_REG_Q31, "q31" }, + + // extras + { PPC_REG_RM, "rm" }, + { PPC_REG_CTR8, "ctr8" }, + { PPC_REG_LR8, "lr8" }, + { PPC_REG_CR1EQ, "cr1eq" }, + { PPC_REG_X2, "x2" }, +}; +#endif + +const char *PPC_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "PPCMappingInsn.inc" +}; + +// given internal insn id, return public instruction info +void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + int i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = PPC_GRP_JUMP; + insn->detail->groups_count++; + } + + insn->detail->ppc.update_cr0 = cs_reg_write((csh)&handle, insn, PPC_REG_CR0); +#endif + } + } +} + +#ifndef CAPSTONE_DIET +static const name_map insn_name_maps[] = { + { PPC_INS_INVALID, NULL }, + + { PPC_INS_ADD, "add" }, + { PPC_INS_ADDC, "addc" }, + { PPC_INS_ADDE, "adde" }, + { PPC_INS_ADDI, "addi" }, + { PPC_INS_ADDIC, "addic" }, + { PPC_INS_ADDIS, "addis" }, + { PPC_INS_ADDME, "addme" }, + { PPC_INS_ADDZE, "addze" }, + { PPC_INS_AND, "and" }, + { PPC_INS_ANDC, "andc" }, + { PPC_INS_ANDIS, "andis" }, + { PPC_INS_ANDI, "andi" }, + { PPC_INS_ATTN, "attn" }, + { PPC_INS_B, "b" }, + { PPC_INS_BA, "ba" }, + { PPC_INS_BC, "bc" }, + { PPC_INS_BCCTR, "bcctr" }, + { PPC_INS_BCCTRL, "bcctrl" }, + { PPC_INS_BCL, "bcl" }, + { PPC_INS_BCLR, "bclr" }, + { PPC_INS_BCLRL, "bclrl" }, + { PPC_INS_BCTR, "bctr" }, + { PPC_INS_BCTRL, "bctrl" }, + { PPC_INS_BCT, "bct" }, + { PPC_INS_BDNZ, "bdnz" }, + { PPC_INS_BDNZA, "bdnza" }, + { PPC_INS_BDNZL, "bdnzl" }, + { PPC_INS_BDNZLA, "bdnzla" }, + { PPC_INS_BDNZLR, "bdnzlr" }, + { PPC_INS_BDNZLRL, "bdnzlrl" }, + { PPC_INS_BDZ, "bdz" }, + { PPC_INS_BDZA, "bdza" }, + { PPC_INS_BDZL, "bdzl" }, + { PPC_INS_BDZLA, "bdzla" }, + { PPC_INS_BDZLR, "bdzlr" }, + { PPC_INS_BDZLRL, "bdzlrl" }, + { PPC_INS_BL, "bl" }, + { PPC_INS_BLA, "bla" }, + { PPC_INS_BLR, "blr" }, + { PPC_INS_BLRL, "blrl" }, + { PPC_INS_BRINC, "brinc" }, + { PPC_INS_CMPB, "cmpb" }, + { PPC_INS_CMPD, "cmpd" }, + { PPC_INS_CMPDI, "cmpdi" }, + { PPC_INS_CMPLD, "cmpld" }, + { PPC_INS_CMPLDI, "cmpldi" }, + { PPC_INS_CMPLW, "cmplw" }, + { PPC_INS_CMPLWI, "cmplwi" }, + { PPC_INS_CMPW, "cmpw" }, + { PPC_INS_CMPWI, "cmpwi" }, + { PPC_INS_CNTLZD, "cntlzd" }, + { PPC_INS_CNTLZW, "cntlzw" }, + { PPC_INS_CREQV, "creqv" }, + { PPC_INS_CRXOR, "crxor" }, + { PPC_INS_CRAND, "crand" }, + { PPC_INS_CRANDC, "crandc" }, + { PPC_INS_CRNAND, "crnand" }, + { PPC_INS_CRNOR, "crnor" }, + { PPC_INS_CROR, "cror" }, + { PPC_INS_CRORC, "crorc" }, + { PPC_INS_DCBA, "dcba" }, + { PPC_INS_DCBF, "dcbf" }, + { PPC_INS_DCBI, "dcbi" }, + { PPC_INS_DCBST, "dcbst" }, + { PPC_INS_DCBT, "dcbt" }, + { PPC_INS_DCBTST, "dcbtst" }, + { PPC_INS_DCBZ, "dcbz" }, + { PPC_INS_DCBZL, "dcbzl" }, + { PPC_INS_DCCCI, "dccci" }, + { PPC_INS_DIVD, "divd" }, + { PPC_INS_DIVDU, "divdu" }, + { PPC_INS_DIVW, "divw" }, + { PPC_INS_DIVWU, "divwu" }, + { PPC_INS_DSS, "dss" }, + { PPC_INS_DSSALL, "dssall" }, + { PPC_INS_DST, "dst" }, + { PPC_INS_DSTST, "dstst" }, + { PPC_INS_DSTSTT, "dststt" }, + { PPC_INS_DSTT, "dstt" }, + { PPC_INS_EQV, "eqv" }, + { PPC_INS_EVABS, "evabs" }, + { PPC_INS_EVADDIW, "evaddiw" }, + { PPC_INS_EVADDSMIAAW, "evaddsmiaaw" }, + { PPC_INS_EVADDSSIAAW, "evaddssiaaw" }, + { PPC_INS_EVADDUMIAAW, "evaddumiaaw" }, + { PPC_INS_EVADDUSIAAW, "evaddusiaaw" }, + { PPC_INS_EVADDW, "evaddw" }, + { PPC_INS_EVAND, "evand" }, + { PPC_INS_EVANDC, "evandc" }, + { PPC_INS_EVCMPEQ, "evcmpeq" }, + { PPC_INS_EVCMPGTS, "evcmpgts" }, + { PPC_INS_EVCMPGTU, "evcmpgtu" }, + { PPC_INS_EVCMPLTS, "evcmplts" }, + { PPC_INS_EVCMPLTU, "evcmpltu" }, + { PPC_INS_EVCNTLSW, "evcntlsw" }, + { PPC_INS_EVCNTLZW, "evcntlzw" }, + { PPC_INS_EVDIVWS, "evdivws" }, + { PPC_INS_EVDIVWU, "evdivwu" }, + { PPC_INS_EVEQV, "eveqv" }, + { PPC_INS_EVEXTSB, "evextsb" }, + { PPC_INS_EVEXTSH, "evextsh" }, + { PPC_INS_EVLDD, "evldd" }, + { PPC_INS_EVLDDX, "evlddx" }, + { PPC_INS_EVLDH, "evldh" }, + { PPC_INS_EVLDHX, "evldhx" }, + { PPC_INS_EVLDW, "evldw" }, + { PPC_INS_EVLDWX, "evldwx" }, + { PPC_INS_EVLHHESPLAT, "evlhhesplat" }, + { PPC_INS_EVLHHESPLATX, "evlhhesplatx" }, + { PPC_INS_EVLHHOSSPLAT, "evlhhossplat" }, + { PPC_INS_EVLHHOSSPLATX, "evlhhossplatx" }, + { PPC_INS_EVLHHOUSPLAT, "evlhhousplat" }, + { PPC_INS_EVLHHOUSPLATX, "evlhhousplatx" }, + { PPC_INS_EVLWHE, "evlwhe" }, + { PPC_INS_EVLWHEX, "evlwhex" }, + { PPC_INS_EVLWHOS, "evlwhos" }, + { PPC_INS_EVLWHOSX, "evlwhosx" }, + { PPC_INS_EVLWHOU, "evlwhou" }, + { PPC_INS_EVLWHOUX, "evlwhoux" }, + { PPC_INS_EVLWHSPLAT, "evlwhsplat" }, + { PPC_INS_EVLWHSPLATX, "evlwhsplatx" }, + { PPC_INS_EVLWWSPLAT, "evlwwsplat" }, + { PPC_INS_EVLWWSPLATX, "evlwwsplatx" }, + { PPC_INS_EVMERGEHI, "evmergehi" }, + { PPC_INS_EVMERGEHILO, "evmergehilo" }, + { PPC_INS_EVMERGELO, "evmergelo" }, + { PPC_INS_EVMERGELOHI, "evmergelohi" }, + { PPC_INS_EVMHEGSMFAA, "evmhegsmfaa" }, + { PPC_INS_EVMHEGSMFAN, "evmhegsmfan" }, + { PPC_INS_EVMHEGSMIAA, "evmhegsmiaa" }, + { PPC_INS_EVMHEGSMIAN, "evmhegsmian" }, + { PPC_INS_EVMHEGUMIAA, "evmhegumiaa" }, + { PPC_INS_EVMHEGUMIAN, "evmhegumian" }, + { PPC_INS_EVMHESMF, "evmhesmf" }, + { PPC_INS_EVMHESMFA, "evmhesmfa" }, + { PPC_INS_EVMHESMFAAW, "evmhesmfaaw" }, + { PPC_INS_EVMHESMFANW, "evmhesmfanw" }, + { PPC_INS_EVMHESMI, "evmhesmi" }, + { PPC_INS_EVMHESMIA, "evmhesmia" }, + { PPC_INS_EVMHESMIAAW, "evmhesmiaaw" }, + { PPC_INS_EVMHESMIANW, "evmhesmianw" }, + { PPC_INS_EVMHESSF, "evmhessf" }, + { PPC_INS_EVMHESSFA, "evmhessfa" }, + { PPC_INS_EVMHESSFAAW, "evmhessfaaw" }, + { PPC_INS_EVMHESSFANW, "evmhessfanw" }, + { PPC_INS_EVMHESSIAAW, "evmhessiaaw" }, + { PPC_INS_EVMHESSIANW, "evmhessianw" }, + { PPC_INS_EVMHEUMI, "evmheumi" }, + { PPC_INS_EVMHEUMIA, "evmheumia" }, + { PPC_INS_EVMHEUMIAAW, "evmheumiaaw" }, + { PPC_INS_EVMHEUMIANW, "evmheumianw" }, + { PPC_INS_EVMHEUSIAAW, "evmheusiaaw" }, + { PPC_INS_EVMHEUSIANW, "evmheusianw" }, + { PPC_INS_EVMHOGSMFAA, "evmhogsmfaa" }, + { PPC_INS_EVMHOGSMFAN, "evmhogsmfan" }, + { PPC_INS_EVMHOGSMIAA, "evmhogsmiaa" }, + { PPC_INS_EVMHOGSMIAN, "evmhogsmian" }, + { PPC_INS_EVMHOGUMIAA, "evmhogumiaa" }, + { PPC_INS_EVMHOGUMIAN, "evmhogumian" }, + { PPC_INS_EVMHOSMF, "evmhosmf" }, + { PPC_INS_EVMHOSMFA, "evmhosmfa" }, + { PPC_INS_EVMHOSMFAAW, "evmhosmfaaw" }, + { PPC_INS_EVMHOSMFANW, "evmhosmfanw" }, + { PPC_INS_EVMHOSMI, "evmhosmi" }, + { PPC_INS_EVMHOSMIA, "evmhosmia" }, + { PPC_INS_EVMHOSMIAAW, "evmhosmiaaw" }, + { PPC_INS_EVMHOSMIANW, "evmhosmianw" }, + { PPC_INS_EVMHOSSF, "evmhossf" }, + { PPC_INS_EVMHOSSFA, "evmhossfa" }, + { PPC_INS_EVMHOSSFAAW, "evmhossfaaw" }, + { PPC_INS_EVMHOSSFANW, "evmhossfanw" }, + { PPC_INS_EVMHOSSIAAW, "evmhossiaaw" }, + { PPC_INS_EVMHOSSIANW, "evmhossianw" }, + { PPC_INS_EVMHOUMI, "evmhoumi" }, + { PPC_INS_EVMHOUMIA, "evmhoumia" }, + { PPC_INS_EVMHOUMIAAW, "evmhoumiaaw" }, + { PPC_INS_EVMHOUMIANW, "evmhoumianw" }, + { PPC_INS_EVMHOUSIAAW, "evmhousiaaw" }, + { PPC_INS_EVMHOUSIANW, "evmhousianw" }, + { PPC_INS_EVMRA, "evmra" }, + { PPC_INS_EVMWHSMF, "evmwhsmf" }, + { PPC_INS_EVMWHSMFA, "evmwhsmfa" }, + { PPC_INS_EVMWHSMI, "evmwhsmi" }, + { PPC_INS_EVMWHSMIA, "evmwhsmia" }, + { PPC_INS_EVMWHSSF, "evmwhssf" }, + { PPC_INS_EVMWHSSFA, "evmwhssfa" }, + { PPC_INS_EVMWHUMI, "evmwhumi" }, + { PPC_INS_EVMWHUMIA, "evmwhumia" }, + { PPC_INS_EVMWLSMIAAW, "evmwlsmiaaw" }, + { PPC_INS_EVMWLSMIANW, "evmwlsmianw" }, + { PPC_INS_EVMWLSSIAAW, "evmwlssiaaw" }, + { PPC_INS_EVMWLSSIANW, "evmwlssianw" }, + { PPC_INS_EVMWLUMI, "evmwlumi" }, + { PPC_INS_EVMWLUMIA, "evmwlumia" }, + { PPC_INS_EVMWLUMIAAW, "evmwlumiaaw" }, + { PPC_INS_EVMWLUMIANW, "evmwlumianw" }, + { PPC_INS_EVMWLUSIAAW, "evmwlusiaaw" }, + { PPC_INS_EVMWLUSIANW, "evmwlusianw" }, + { PPC_INS_EVMWSMF, "evmwsmf" }, + { PPC_INS_EVMWSMFA, "evmwsmfa" }, + { PPC_INS_EVMWSMFAA, "evmwsmfaa" }, + { PPC_INS_EVMWSMFAN, "evmwsmfan" }, + { PPC_INS_EVMWSMI, "evmwsmi" }, + { PPC_INS_EVMWSMIA, "evmwsmia" }, + { PPC_INS_EVMWSMIAA, "evmwsmiaa" }, + { PPC_INS_EVMWSMIAN, "evmwsmian" }, + { PPC_INS_EVMWSSF, "evmwssf" }, + { PPC_INS_EVMWSSFA, "evmwssfa" }, + { PPC_INS_EVMWSSFAA, "evmwssfaa" }, + { PPC_INS_EVMWSSFAN, "evmwssfan" }, + { PPC_INS_EVMWUMI, "evmwumi" }, + { PPC_INS_EVMWUMIA, "evmwumia" }, + { PPC_INS_EVMWUMIAA, "evmwumiaa" }, + { PPC_INS_EVMWUMIAN, "evmwumian" }, + { PPC_INS_EVNAND, "evnand" }, + { PPC_INS_EVNEG, "evneg" }, + { PPC_INS_EVNOR, "evnor" }, + { PPC_INS_EVOR, "evor" }, + { PPC_INS_EVORC, "evorc" }, + { PPC_INS_EVRLW, "evrlw" }, + { PPC_INS_EVRLWI, "evrlwi" }, + { PPC_INS_EVRNDW, "evrndw" }, + { PPC_INS_EVSLW, "evslw" }, + { PPC_INS_EVSLWI, "evslwi" }, + { PPC_INS_EVSPLATFI, "evsplatfi" }, + { PPC_INS_EVSPLATI, "evsplati" }, + { PPC_INS_EVSRWIS, "evsrwis" }, + { PPC_INS_EVSRWIU, "evsrwiu" }, + { PPC_INS_EVSRWS, "evsrws" }, + { PPC_INS_EVSRWU, "evsrwu" }, + { PPC_INS_EVSTDD, "evstdd" }, + { PPC_INS_EVSTDDX, "evstddx" }, + { PPC_INS_EVSTDH, "evstdh" }, + { PPC_INS_EVSTDHX, "evstdhx" }, + { PPC_INS_EVSTDW, "evstdw" }, + { PPC_INS_EVSTDWX, "evstdwx" }, + { PPC_INS_EVSTWHE, "evstwhe" }, + { PPC_INS_EVSTWHEX, "evstwhex" }, + { PPC_INS_EVSTWHO, "evstwho" }, + { PPC_INS_EVSTWHOX, "evstwhox" }, + { PPC_INS_EVSTWWE, "evstwwe" }, + { PPC_INS_EVSTWWEX, "evstwwex" }, + { PPC_INS_EVSTWWO, "evstwwo" }, + { PPC_INS_EVSTWWOX, "evstwwox" }, + { PPC_INS_EVSUBFSMIAAW, "evsubfsmiaaw" }, + { PPC_INS_EVSUBFSSIAAW, "evsubfssiaaw" }, + { PPC_INS_EVSUBFUMIAAW, "evsubfumiaaw" }, + { PPC_INS_EVSUBFUSIAAW, "evsubfusiaaw" }, + { PPC_INS_EVSUBFW, "evsubfw" }, + { PPC_INS_EVSUBIFW, "evsubifw" }, + { PPC_INS_EVXOR, "evxor" }, + { PPC_INS_EXTSB, "extsb" }, + { PPC_INS_EXTSH, "extsh" }, + { PPC_INS_EXTSW, "extsw" }, + { PPC_INS_EIEIO, "eieio" }, + { PPC_INS_FABS, "fabs" }, + { PPC_INS_FADD, "fadd" }, + { PPC_INS_FADDS, "fadds" }, + { PPC_INS_FCFID, "fcfid" }, + { PPC_INS_FCFIDS, "fcfids" }, + { PPC_INS_FCFIDU, "fcfidu" }, + { PPC_INS_FCFIDUS, "fcfidus" }, + { PPC_INS_FCMPU, "fcmpu" }, + { PPC_INS_FCPSGN, "fcpsgn" }, + { PPC_INS_FCTID, "fctid" }, + { PPC_INS_FCTIDUZ, "fctiduz" }, + { PPC_INS_FCTIDZ, "fctidz" }, + { PPC_INS_FCTIW, "fctiw" }, + { PPC_INS_FCTIWUZ, "fctiwuz" }, + { PPC_INS_FCTIWZ, "fctiwz" }, + { PPC_INS_FDIV, "fdiv" }, + { PPC_INS_FDIVS, "fdivs" }, + { PPC_INS_FMADD, "fmadd" }, + { PPC_INS_FMADDS, "fmadds" }, + { PPC_INS_FMR, "fmr" }, + { PPC_INS_FMSUB, "fmsub" }, + { PPC_INS_FMSUBS, "fmsubs" }, + { PPC_INS_FMUL, "fmul" }, + { PPC_INS_FMULS, "fmuls" }, + { PPC_INS_FNABS, "fnabs" }, + { PPC_INS_FNEG, "fneg" }, + { PPC_INS_FNMADD, "fnmadd" }, + { PPC_INS_FNMADDS, "fnmadds" }, + { PPC_INS_FNMSUB, "fnmsub" }, + { PPC_INS_FNMSUBS, "fnmsubs" }, + { PPC_INS_FRE, "fre" }, + { PPC_INS_FRES, "fres" }, + { PPC_INS_FRIM, "frim" }, + { PPC_INS_FRIN, "frin" }, + { PPC_INS_FRIP, "frip" }, + { PPC_INS_FRIZ, "friz" }, + { PPC_INS_FRSP, "frsp" }, + { PPC_INS_FRSQRTE, "frsqrte" }, + { PPC_INS_FRSQRTES, "frsqrtes" }, + { PPC_INS_FSEL, "fsel" }, + { PPC_INS_FSQRT, "fsqrt" }, + { PPC_INS_FSQRTS, "fsqrts" }, + { PPC_INS_FSUB, "fsub" }, + { PPC_INS_FSUBS, "fsubs" }, + { PPC_INS_ICBI, "icbi" }, + { PPC_INS_ICBT, "icbt" }, + { PPC_INS_ICCCI, "iccci" }, + { PPC_INS_ISEL, "isel" }, + { PPC_INS_ISYNC, "isync" }, + { PPC_INS_LA, "la" }, + { PPC_INS_LBZ, "lbz" }, + { PPC_INS_LBZCIX, "lbzcix" }, + { PPC_INS_LBZU, "lbzu" }, + { PPC_INS_LBZUX, "lbzux" }, + { PPC_INS_LBZX, "lbzx" }, + { PPC_INS_LD, "ld" }, + { PPC_INS_LDARX, "ldarx" }, + { PPC_INS_LDBRX, "ldbrx" }, + { PPC_INS_LDCIX, "ldcix" }, + { PPC_INS_LDU, "ldu" }, + { PPC_INS_LDUX, "ldux" }, + { PPC_INS_LDX, "ldx" }, + { PPC_INS_LFD, "lfd" }, + { PPC_INS_LFDU, "lfdu" }, + { PPC_INS_LFDUX, "lfdux" }, + { PPC_INS_LFDX, "lfdx" }, + { PPC_INS_LFIWAX, "lfiwax" }, + { PPC_INS_LFIWZX, "lfiwzx" }, + { PPC_INS_LFS, "lfs" }, + { PPC_INS_LFSU, "lfsu" }, + { PPC_INS_LFSUX, "lfsux" }, + { PPC_INS_LFSX, "lfsx" }, + { PPC_INS_LHA, "lha" }, + { PPC_INS_LHAU, "lhau" }, + { PPC_INS_LHAUX, "lhaux" }, + { PPC_INS_LHAX, "lhax" }, + { PPC_INS_LHBRX, "lhbrx" }, + { PPC_INS_LHZ, "lhz" }, + { PPC_INS_LHZCIX, "lhzcix" }, + { PPC_INS_LHZU, "lhzu" }, + { PPC_INS_LHZUX, "lhzux" }, + { PPC_INS_LHZX, "lhzx" }, + { PPC_INS_LI, "li" }, + { PPC_INS_LIS, "lis" }, + { PPC_INS_LMW, "lmw" }, + { PPC_INS_LSWI, "lswi" }, + { PPC_INS_LVEBX, "lvebx" }, + { PPC_INS_LVEHX, "lvehx" }, + { PPC_INS_LVEWX, "lvewx" }, + { PPC_INS_LVSL, "lvsl" }, + { PPC_INS_LVSR, "lvsr" }, + { PPC_INS_LVX, "lvx" }, + { PPC_INS_LVXL, "lvxl" }, + { PPC_INS_LWA, "lwa" }, + { PPC_INS_LWARX, "lwarx" }, + { PPC_INS_LWAUX, "lwaux" }, + { PPC_INS_LWAX, "lwax" }, + { PPC_INS_LWBRX, "lwbrx" }, + { PPC_INS_LWZ, "lwz" }, + { PPC_INS_LWZCIX, "lwzcix" }, + { PPC_INS_LWZU, "lwzu" }, + { PPC_INS_LWZUX, "lwzux" }, + { PPC_INS_LWZX, "lwzx" }, + { PPC_INS_LXSDX, "lxsdx" }, + { PPC_INS_LXVD2X, "lxvd2x" }, + { PPC_INS_LXVDSX, "lxvdsx" }, + { PPC_INS_LXVW4X, "lxvw4x" }, + { PPC_INS_MBAR, "mbar" }, + { PPC_INS_MCRF, "mcrf" }, + { PPC_INS_MCRFS, "mcrfs" }, + { PPC_INS_MFCR, "mfcr" }, + { PPC_INS_MFCTR, "mfctr" }, + { PPC_INS_MFDCR, "mfdcr" }, + { PPC_INS_MFFS, "mffs" }, + { PPC_INS_MFLR, "mflr" }, + { PPC_INS_MFMSR, "mfmsr" }, + { PPC_INS_MFOCRF, "mfocrf" }, + { PPC_INS_MFSPR, "mfspr" }, + { PPC_INS_MFSR, "mfsr" }, + { PPC_INS_MFSRIN, "mfsrin" }, + { PPC_INS_MFTB, "mftb" }, + { PPC_INS_MFVSCR, "mfvscr" }, + { PPC_INS_MSYNC, "msync" }, + { PPC_INS_MTCRF, "mtcrf" }, + { PPC_INS_MTCTR, "mtctr" }, + { PPC_INS_MTDCR, "mtdcr" }, + { PPC_INS_MTFSB0, "mtfsb0" }, + { PPC_INS_MTFSB1, "mtfsb1" }, + { PPC_INS_MTFSF, "mtfsf" }, + { PPC_INS_MTFSFI, "mtfsfi" }, + { PPC_INS_MTLR, "mtlr" }, + { PPC_INS_MTMSR, "mtmsr" }, + { PPC_INS_MTMSRD, "mtmsrd" }, + { PPC_INS_MTOCRF, "mtocrf" }, + { PPC_INS_MTSPR, "mtspr" }, + { PPC_INS_MTSR, "mtsr" }, + { PPC_INS_MTSRIN, "mtsrin" }, + { PPC_INS_MTVSCR, "mtvscr" }, + { PPC_INS_MULHD, "mulhd" }, + { PPC_INS_MULHDU, "mulhdu" }, + { PPC_INS_MULHW, "mulhw" }, + { PPC_INS_MULHWU, "mulhwu" }, + { PPC_INS_MULLD, "mulld" }, + { PPC_INS_MULLI, "mulli" }, + { PPC_INS_MULLW, "mullw" }, + { PPC_INS_NAND, "nand" }, + { PPC_INS_NEG, "neg" }, + { PPC_INS_NOP, "nop" }, + { PPC_INS_ORI, "ori" }, + { PPC_INS_NOR, "nor" }, + { PPC_INS_OR, "or" }, + { PPC_INS_ORC, "orc" }, + { PPC_INS_ORIS, "oris" }, + { PPC_INS_POPCNTD, "popcntd" }, + { PPC_INS_POPCNTW, "popcntw" }, + { PPC_INS_QVALIGNI, "qvaligni" }, + { PPC_INS_QVESPLATI, "qvesplati" }, + { PPC_INS_QVFABS, "qvfabs" }, + { PPC_INS_QVFADD, "qvfadd" }, + { PPC_INS_QVFADDS, "qvfadds" }, + { PPC_INS_QVFCFID, "qvfcfid" }, + { PPC_INS_QVFCFIDS, "qvfcfids" }, + { PPC_INS_QVFCFIDU, "qvfcfidu" }, + { PPC_INS_QVFCFIDUS, "qvfcfidus" }, + { PPC_INS_QVFCMPEQ, "qvfcmpeq" }, + { PPC_INS_QVFCMPGT, "qvfcmpgt" }, + { PPC_INS_QVFCMPLT, "qvfcmplt" }, + { PPC_INS_QVFCPSGN, "qvfcpsgn" }, + { PPC_INS_QVFCTID, "qvfctid" }, + { PPC_INS_QVFCTIDU, "qvfctidu" }, + { PPC_INS_QVFCTIDUZ, "qvfctiduz" }, + { PPC_INS_QVFCTIDZ, "qvfctidz" }, + { PPC_INS_QVFCTIW, "qvfctiw" }, + { PPC_INS_QVFCTIWU, "qvfctiwu" }, + { PPC_INS_QVFCTIWUZ, "qvfctiwuz" }, + { PPC_INS_QVFCTIWZ, "qvfctiwz" }, + { PPC_INS_QVFLOGICAL, "qvflogical" }, + { PPC_INS_QVFMADD, "qvfmadd" }, + { PPC_INS_QVFMADDS, "qvfmadds" }, + { PPC_INS_QVFMR, "qvfmr" }, + { PPC_INS_QVFMSUB, "qvfmsub" }, + { PPC_INS_QVFMSUBS, "qvfmsubs" }, + { PPC_INS_QVFMUL, "qvfmul" }, + { PPC_INS_QVFMULS, "qvfmuls" }, + { PPC_INS_QVFNABS, "qvfnabs" }, + { PPC_INS_QVFNEG, "qvfneg" }, + { PPC_INS_QVFNMADD, "qvfnmadd" }, + { PPC_INS_QVFNMADDS, "qvfnmadds" }, + { PPC_INS_QVFNMSUB, "qvfnmsub" }, + { PPC_INS_QVFNMSUBS, "qvfnmsubs" }, + { PPC_INS_QVFPERM, "qvfperm" }, + { PPC_INS_QVFRE, "qvfre" }, + { PPC_INS_QVFRES, "qvfres" }, + { PPC_INS_QVFRIM, "qvfrim" }, + { PPC_INS_QVFRIN, "qvfrin" }, + { PPC_INS_QVFRIP, "qvfrip" }, + { PPC_INS_QVFRIZ, "qvfriz" }, + { PPC_INS_QVFRSP, "qvfrsp" }, + { PPC_INS_QVFRSQRTE, "qvfrsqrte" }, + { PPC_INS_QVFRSQRTES, "qvfrsqrtes" }, + { PPC_INS_QVFSEL, "qvfsel" }, + { PPC_INS_QVFSUB, "qvfsub" }, + { PPC_INS_QVFSUBS, "qvfsubs" }, + { PPC_INS_QVFTSTNAN, "qvftstnan" }, + { PPC_INS_QVFXMADD, "qvfxmadd" }, + { PPC_INS_QVFXMADDS, "qvfxmadds" }, + { PPC_INS_QVFXMUL, "qvfxmul" }, + { PPC_INS_QVFXMULS, "qvfxmuls" }, + { PPC_INS_QVFXXCPNMADD, "qvfxxcpnmadd" }, + { PPC_INS_QVFXXCPNMADDS, "qvfxxcpnmadds" }, + { PPC_INS_QVFXXMADD, "qvfxxmadd" }, + { PPC_INS_QVFXXMADDS, "qvfxxmadds" }, + { PPC_INS_QVFXXNPMADD, "qvfxxnpmadd" }, + { PPC_INS_QVFXXNPMADDS, "qvfxxnpmadds" }, + { PPC_INS_QVGPCI, "qvgpci" }, + { PPC_INS_QVLFCDUX, "qvlfcdux" }, + { PPC_INS_QVLFCDUXA, "qvlfcduxa" }, + { PPC_INS_QVLFCDX, "qvlfcdx" }, + { PPC_INS_QVLFCDXA, "qvlfcdxa" }, + { PPC_INS_QVLFCSUX, "qvlfcsux" }, + { PPC_INS_QVLFCSUXA, "qvlfcsuxa" }, + { PPC_INS_QVLFCSX, "qvlfcsx" }, + { PPC_INS_QVLFCSXA, "qvlfcsxa" }, + { PPC_INS_QVLFDUX, "qvlfdux" }, + { PPC_INS_QVLFDUXA, "qvlfduxa" }, + { PPC_INS_QVLFDX, "qvlfdx" }, + { PPC_INS_QVLFDXA, "qvlfdxa" }, + { PPC_INS_QVLFIWAX, "qvlfiwax" }, + { PPC_INS_QVLFIWAXA, "qvlfiwaxa" }, + { PPC_INS_QVLFIWZX, "qvlfiwzx" }, + { PPC_INS_QVLFIWZXA, "qvlfiwzxa" }, + { PPC_INS_QVLFSUX, "qvlfsux" }, + { PPC_INS_QVLFSUXA, "qvlfsuxa" }, + { PPC_INS_QVLFSX, "qvlfsx" }, + { PPC_INS_QVLFSXA, "qvlfsxa" }, + { PPC_INS_QVLPCLDX, "qvlpcldx" }, + { PPC_INS_QVLPCLSX, "qvlpclsx" }, + { PPC_INS_QVLPCRDX, "qvlpcrdx" }, + { PPC_INS_QVLPCRSX, "qvlpcrsx" }, + { PPC_INS_QVSTFCDUX, "qvstfcdux" }, + { PPC_INS_QVSTFCDUXA, "qvstfcduxa" }, + { PPC_INS_QVSTFCDUXI, "qvstfcduxi" }, + { PPC_INS_QVSTFCDUXIA, "qvstfcduxia" }, + { PPC_INS_QVSTFCDX, "qvstfcdx" }, + { PPC_INS_QVSTFCDXA, "qvstfcdxa" }, + { PPC_INS_QVSTFCDXI, "qvstfcdxi" }, + { PPC_INS_QVSTFCDXIA, "qvstfcdxia" }, + { PPC_INS_QVSTFCSUX, "qvstfcsux" }, + { PPC_INS_QVSTFCSUXA, "qvstfcsuxa" }, + { PPC_INS_QVSTFCSUXI, "qvstfcsuxi" }, + { PPC_INS_QVSTFCSUXIA, "qvstfcsuxia" }, + { PPC_INS_QVSTFCSX, "qvstfcsx" }, + { PPC_INS_QVSTFCSXA, "qvstfcsxa" }, + { PPC_INS_QVSTFCSXI, "qvstfcsxi" }, + { PPC_INS_QVSTFCSXIA, "qvstfcsxia" }, + { PPC_INS_QVSTFDUX, "qvstfdux" }, + { PPC_INS_QVSTFDUXA, "qvstfduxa" }, + { PPC_INS_QVSTFDUXI, "qvstfduxi" }, + { PPC_INS_QVSTFDUXIA, "qvstfduxia" }, + { PPC_INS_QVSTFDX, "qvstfdx" }, + { PPC_INS_QVSTFDXA, "qvstfdxa" }, + { PPC_INS_QVSTFDXI, "qvstfdxi" }, + { PPC_INS_QVSTFDXIA, "qvstfdxia" }, + { PPC_INS_QVSTFIWX, "qvstfiwx" }, + { PPC_INS_QVSTFIWXA, "qvstfiwxa" }, + { PPC_INS_QVSTFSUX, "qvstfsux" }, + { PPC_INS_QVSTFSUXA, "qvstfsuxa" }, + { PPC_INS_QVSTFSUXI, "qvstfsuxi" }, + { PPC_INS_QVSTFSUXIA, "qvstfsuxia" }, + { PPC_INS_QVSTFSX, "qvstfsx" }, + { PPC_INS_QVSTFSXA, "qvstfsxa" }, + { PPC_INS_QVSTFSXI, "qvstfsxi" }, + { PPC_INS_QVSTFSXIA, "qvstfsxia" }, + { PPC_INS_RFCI, "rfci" }, + { PPC_INS_RFDI, "rfdi" }, + { PPC_INS_RFI, "rfi" }, + { PPC_INS_RFID, "rfid" }, + { PPC_INS_RFMCI, "rfmci" }, + { PPC_INS_RLDCL, "rldcl" }, + { PPC_INS_RLDCR, "rldcr" }, + { PPC_INS_RLDIC, "rldic" }, + { PPC_INS_RLDICL, "rldicl" }, + { PPC_INS_RLDICR, "rldicr" }, + { PPC_INS_RLDIMI, "rldimi" }, + { PPC_INS_RLWIMI, "rlwimi" }, + { PPC_INS_RLWINM, "rlwinm" }, + { PPC_INS_RLWNM, "rlwnm" }, + { PPC_INS_SC, "sc" }, + { PPC_INS_SLBIA, "slbia" }, + { PPC_INS_SLBIE, "slbie" }, + { PPC_INS_SLBMFEE, "slbmfee" }, + { PPC_INS_SLBMTE, "slbmte" }, + { PPC_INS_SLD, "sld" }, + { PPC_INS_SLW, "slw" }, + { PPC_INS_SRAD, "srad" }, + { PPC_INS_SRADI, "sradi" }, + { PPC_INS_SRAW, "sraw" }, + { PPC_INS_SRAWI, "srawi" }, + { PPC_INS_SRD, "srd" }, + { PPC_INS_SRW, "srw" }, + { PPC_INS_STB, "stb" }, + { PPC_INS_STBCIX, "stbcix" }, + { PPC_INS_STBU, "stbu" }, + { PPC_INS_STBUX, "stbux" }, + { PPC_INS_STBX, "stbx" }, + { PPC_INS_STD, "std" }, + { PPC_INS_STDBRX, "stdbrx" }, + { PPC_INS_STDCIX, "stdcix" }, + { PPC_INS_STDCX, "stdcx" }, + { PPC_INS_STDU, "stdu" }, + { PPC_INS_STDUX, "stdux" }, + { PPC_INS_STDX, "stdx" }, + { PPC_INS_STFD, "stfd" }, + { PPC_INS_STFDU, "stfdu" }, + { PPC_INS_STFDUX, "stfdux" }, + { PPC_INS_STFDX, "stfdx" }, + { PPC_INS_STFIWX, "stfiwx" }, + { PPC_INS_STFS, "stfs" }, + { PPC_INS_STFSU, "stfsu" }, + { PPC_INS_STFSUX, "stfsux" }, + { PPC_INS_STFSX, "stfsx" }, + { PPC_INS_STH, "sth" }, + { PPC_INS_STHBRX, "sthbrx" }, + { PPC_INS_STHCIX, "sthcix" }, + { PPC_INS_STHU, "sthu" }, + { PPC_INS_STHUX, "sthux" }, + { PPC_INS_STHX, "sthx" }, + { PPC_INS_STMW, "stmw" }, + { PPC_INS_STSWI, "stswi" }, + { PPC_INS_STVEBX, "stvebx" }, + { PPC_INS_STVEHX, "stvehx" }, + { PPC_INS_STVEWX, "stvewx" }, + { PPC_INS_STVX, "stvx" }, + { PPC_INS_STVXL, "stvxl" }, + { PPC_INS_STW, "stw" }, + { PPC_INS_STWBRX, "stwbrx" }, + { PPC_INS_STWCIX, "stwcix" }, + { PPC_INS_STWCX, "stwcx" }, + { PPC_INS_STWU, "stwu" }, + { PPC_INS_STWUX, "stwux" }, + { PPC_INS_STWX, "stwx" }, + { PPC_INS_STXSDX, "stxsdx" }, + { PPC_INS_STXVD2X, "stxvd2x" }, + { PPC_INS_STXVW4X, "stxvw4x" }, + { PPC_INS_SUBF, "subf" }, + { PPC_INS_SUBFC, "subfc" }, + { PPC_INS_SUBFE, "subfe" }, + { PPC_INS_SUBFIC, "subfic" }, + { PPC_INS_SUBFME, "subfme" }, + { PPC_INS_SUBFZE, "subfze" }, + { PPC_INS_SYNC, "sync" }, + { PPC_INS_TD, "td" }, + { PPC_INS_TDI, "tdi" }, + { PPC_INS_TLBIA, "tlbia" }, + { PPC_INS_TLBIE, "tlbie" }, + { PPC_INS_TLBIEL, "tlbiel" }, + { PPC_INS_TLBIVAX, "tlbivax" }, + { PPC_INS_TLBLD, "tlbld" }, + { PPC_INS_TLBLI, "tlbli" }, + { PPC_INS_TLBRE, "tlbre" }, + { PPC_INS_TLBSX, "tlbsx" }, + { PPC_INS_TLBSYNC, "tlbsync" }, + { PPC_INS_TLBWE, "tlbwe" }, + { PPC_INS_TRAP, "trap" }, + { PPC_INS_TW, "tw" }, + { PPC_INS_TWI, "twi" }, + { PPC_INS_VADDCUW, "vaddcuw" }, + { PPC_INS_VADDFP, "vaddfp" }, + { PPC_INS_VADDSBS, "vaddsbs" }, + { PPC_INS_VADDSHS, "vaddshs" }, + { PPC_INS_VADDSWS, "vaddsws" }, + { PPC_INS_VADDUBM, "vaddubm" }, + { PPC_INS_VADDUBS, "vaddubs" }, + { PPC_INS_VADDUDM, "vaddudm" }, + { PPC_INS_VADDUHM, "vadduhm" }, + { PPC_INS_VADDUHS, "vadduhs" }, + { PPC_INS_VADDUWM, "vadduwm" }, + { PPC_INS_VADDUWS, "vadduws" }, + { PPC_INS_VAND, "vand" }, + { PPC_INS_VANDC, "vandc" }, + { PPC_INS_VAVGSB, "vavgsb" }, + { PPC_INS_VAVGSH, "vavgsh" }, + { PPC_INS_VAVGSW, "vavgsw" }, + { PPC_INS_VAVGUB, "vavgub" }, + { PPC_INS_VAVGUH, "vavguh" }, + { PPC_INS_VAVGUW, "vavguw" }, + { PPC_INS_VCFSX, "vcfsx" }, + { PPC_INS_VCFUX, "vcfux" }, + { PPC_INS_VCLZB, "vclzb" }, + { PPC_INS_VCLZD, "vclzd" }, + { PPC_INS_VCLZH, "vclzh" }, + { PPC_INS_VCLZW, "vclzw" }, + { PPC_INS_VCMPBFP, "vcmpbfp" }, + { PPC_INS_VCMPEQFP, "vcmpeqfp" }, + { PPC_INS_VCMPEQUB, "vcmpequb" }, + { PPC_INS_VCMPEQUD, "vcmpequd" }, + { PPC_INS_VCMPEQUH, "vcmpequh" }, + { PPC_INS_VCMPEQUW, "vcmpequw" }, + { PPC_INS_VCMPGEFP, "vcmpgefp" }, + { PPC_INS_VCMPGTFP, "vcmpgtfp" }, + { PPC_INS_VCMPGTSB, "vcmpgtsb" }, + { PPC_INS_VCMPGTSD, "vcmpgtsd" }, + { PPC_INS_VCMPGTSH, "vcmpgtsh" }, + { PPC_INS_VCMPGTSW, "vcmpgtsw" }, + { PPC_INS_VCMPGTUB, "vcmpgtub" }, + { PPC_INS_VCMPGTUD, "vcmpgtud" }, + { PPC_INS_VCMPGTUH, "vcmpgtuh" }, + { PPC_INS_VCMPGTUW, "vcmpgtuw" }, + { PPC_INS_VCTSXS, "vctsxs" }, + { PPC_INS_VCTUXS, "vctuxs" }, + { PPC_INS_VEQV, "veqv" }, + { PPC_INS_VEXPTEFP, "vexptefp" }, + { PPC_INS_VLOGEFP, "vlogefp" }, + { PPC_INS_VMADDFP, "vmaddfp" }, + { PPC_INS_VMAXFP, "vmaxfp" }, + { PPC_INS_VMAXSB, "vmaxsb" }, + { PPC_INS_VMAXSD, "vmaxsd" }, + { PPC_INS_VMAXSH, "vmaxsh" }, + { PPC_INS_VMAXSW, "vmaxsw" }, + { PPC_INS_VMAXUB, "vmaxub" }, + { PPC_INS_VMAXUD, "vmaxud" }, + { PPC_INS_VMAXUH, "vmaxuh" }, + { PPC_INS_VMAXUW, "vmaxuw" }, + { PPC_INS_VMHADDSHS, "vmhaddshs" }, + { PPC_INS_VMHRADDSHS, "vmhraddshs" }, + { PPC_INS_VMINUD, "vminud" }, + { PPC_INS_VMINFP, "vminfp" }, + { PPC_INS_VMINSB, "vminsb" }, + { PPC_INS_VMINSD, "vminsd" }, + { PPC_INS_VMINSH, "vminsh" }, + { PPC_INS_VMINSW, "vminsw" }, + { PPC_INS_VMINUB, "vminub" }, + { PPC_INS_VMINUH, "vminuh" }, + { PPC_INS_VMINUW, "vminuw" }, + { PPC_INS_VMLADDUHM, "vmladduhm" }, + { PPC_INS_VMRGHB, "vmrghb" }, + { PPC_INS_VMRGHH, "vmrghh" }, + { PPC_INS_VMRGHW, "vmrghw" }, + { PPC_INS_VMRGLB, "vmrglb" }, + { PPC_INS_VMRGLH, "vmrglh" }, + { PPC_INS_VMRGLW, "vmrglw" }, + { PPC_INS_VMSUMMBM, "vmsummbm" }, + { PPC_INS_VMSUMSHM, "vmsumshm" }, + { PPC_INS_VMSUMSHS, "vmsumshs" }, + { PPC_INS_VMSUMUBM, "vmsumubm" }, + { PPC_INS_VMSUMUHM, "vmsumuhm" }, + { PPC_INS_VMSUMUHS, "vmsumuhs" }, + { PPC_INS_VMULESB, "vmulesb" }, + { PPC_INS_VMULESH, "vmulesh" }, + { PPC_INS_VMULESW, "vmulesw" }, + { PPC_INS_VMULEUB, "vmuleub" }, + { PPC_INS_VMULEUH, "vmuleuh" }, + { PPC_INS_VMULEUW, "vmuleuw" }, + { PPC_INS_VMULOSB, "vmulosb" }, + { PPC_INS_VMULOSH, "vmulosh" }, + { PPC_INS_VMULOSW, "vmulosw" }, + { PPC_INS_VMULOUB, "vmuloub" }, + { PPC_INS_VMULOUH, "vmulouh" }, + { PPC_INS_VMULOUW, "vmulouw" }, + { PPC_INS_VMULUWM, "vmuluwm" }, + { PPC_INS_VNAND, "vnand" }, + { PPC_INS_VNMSUBFP, "vnmsubfp" }, + { PPC_INS_VNOR, "vnor" }, + { PPC_INS_VOR, "vor" }, + { PPC_INS_VORC, "vorc" }, + { PPC_INS_VPERM, "vperm" }, + { PPC_INS_VPKPX, "vpkpx" }, + { PPC_INS_VPKSHSS, "vpkshss" }, + { PPC_INS_VPKSHUS, "vpkshus" }, + { PPC_INS_VPKSWSS, "vpkswss" }, + { PPC_INS_VPKSWUS, "vpkswus" }, + { PPC_INS_VPKUHUM, "vpkuhum" }, + { PPC_INS_VPKUHUS, "vpkuhus" }, + { PPC_INS_VPKUWUM, "vpkuwum" }, + { PPC_INS_VPKUWUS, "vpkuwus" }, + { PPC_INS_VPOPCNTB, "vpopcntb" }, + { PPC_INS_VPOPCNTD, "vpopcntd" }, + { PPC_INS_VPOPCNTH, "vpopcnth" }, + { PPC_INS_VPOPCNTW, "vpopcntw" }, + { PPC_INS_VREFP, "vrefp" }, + { PPC_INS_VRFIM, "vrfim" }, + { PPC_INS_VRFIN, "vrfin" }, + { PPC_INS_VRFIP, "vrfip" }, + { PPC_INS_VRFIZ, "vrfiz" }, + { PPC_INS_VRLB, "vrlb" }, + { PPC_INS_VRLD, "vrld" }, + { PPC_INS_VRLH, "vrlh" }, + { PPC_INS_VRLW, "vrlw" }, + { PPC_INS_VRSQRTEFP, "vrsqrtefp" }, + { PPC_INS_VSEL, "vsel" }, + { PPC_INS_VSL, "vsl" }, + { PPC_INS_VSLB, "vslb" }, + { PPC_INS_VSLD, "vsld" }, + { PPC_INS_VSLDOI, "vsldoi" }, + { PPC_INS_VSLH, "vslh" }, + { PPC_INS_VSLO, "vslo" }, + { PPC_INS_VSLW, "vslw" }, + { PPC_INS_VSPLTB, "vspltb" }, + { PPC_INS_VSPLTH, "vsplth" }, + { PPC_INS_VSPLTISB, "vspltisb" }, + { PPC_INS_VSPLTISH, "vspltish" }, + { PPC_INS_VSPLTISW, "vspltisw" }, + { PPC_INS_VSPLTW, "vspltw" }, + { PPC_INS_VSR, "vsr" }, + { PPC_INS_VSRAB, "vsrab" }, + { PPC_INS_VSRAD, "vsrad" }, + { PPC_INS_VSRAH, "vsrah" }, + { PPC_INS_VSRAW, "vsraw" }, + { PPC_INS_VSRB, "vsrb" }, + { PPC_INS_VSRD, "vsrd" }, + { PPC_INS_VSRH, "vsrh" }, + { PPC_INS_VSRO, "vsro" }, + { PPC_INS_VSRW, "vsrw" }, + { PPC_INS_VSUBCUW, "vsubcuw" }, + { PPC_INS_VSUBFP, "vsubfp" }, + { PPC_INS_VSUBSBS, "vsubsbs" }, + { PPC_INS_VSUBSHS, "vsubshs" }, + { PPC_INS_VSUBSWS, "vsubsws" }, + { PPC_INS_VSUBUBM, "vsububm" }, + { PPC_INS_VSUBUBS, "vsububs" }, + { PPC_INS_VSUBUDM, "vsubudm" }, + { PPC_INS_VSUBUHM, "vsubuhm" }, + { PPC_INS_VSUBUHS, "vsubuhs" }, + { PPC_INS_VSUBUWM, "vsubuwm" }, + { PPC_INS_VSUBUWS, "vsubuws" }, + { PPC_INS_VSUM2SWS, "vsum2sws" }, + { PPC_INS_VSUM4SBS, "vsum4sbs" }, + { PPC_INS_VSUM4SHS, "vsum4shs" }, + { PPC_INS_VSUM4UBS, "vsum4ubs" }, + { PPC_INS_VSUMSWS, "vsumsws" }, + { PPC_INS_VUPKHPX, "vupkhpx" }, + { PPC_INS_VUPKHSB, "vupkhsb" }, + { PPC_INS_VUPKHSH, "vupkhsh" }, + { PPC_INS_VUPKLPX, "vupklpx" }, + { PPC_INS_VUPKLSB, "vupklsb" }, + { PPC_INS_VUPKLSH, "vupklsh" }, + { PPC_INS_VXOR, "vxor" }, + { PPC_INS_WAIT, "wait" }, + { PPC_INS_WRTEE, "wrtee" }, + { PPC_INS_WRTEEI, "wrteei" }, + { PPC_INS_XOR, "xor" }, + { PPC_INS_XORI, "xori" }, + { PPC_INS_XORIS, "xoris" }, + { PPC_INS_XSABSDP, "xsabsdp" }, + { PPC_INS_XSADDDP, "xsadddp" }, + { PPC_INS_XSCMPODP, "xscmpodp" }, + { PPC_INS_XSCMPUDP, "xscmpudp" }, + { PPC_INS_XSCPSGNDP, "xscpsgndp" }, + { PPC_INS_XSCVDPSP, "xscvdpsp" }, + { PPC_INS_XSCVDPSXDS, "xscvdpsxds" }, + { PPC_INS_XSCVDPSXWS, "xscvdpsxws" }, + { PPC_INS_XSCVDPUXDS, "xscvdpuxds" }, + { PPC_INS_XSCVDPUXWS, "xscvdpuxws" }, + { PPC_INS_XSCVSPDP, "xscvspdp" }, + { PPC_INS_XSCVSXDDP, "xscvsxddp" }, + { PPC_INS_XSCVUXDDP, "xscvuxddp" }, + { PPC_INS_XSDIVDP, "xsdivdp" }, + { PPC_INS_XSMADDADP, "xsmaddadp" }, + { PPC_INS_XSMADDMDP, "xsmaddmdp" }, + { PPC_INS_XSMAXDP, "xsmaxdp" }, + { PPC_INS_XSMINDP, "xsmindp" }, + { PPC_INS_XSMSUBADP, "xsmsubadp" }, + { PPC_INS_XSMSUBMDP, "xsmsubmdp" }, + { PPC_INS_XSMULDP, "xsmuldp" }, + { PPC_INS_XSNABSDP, "xsnabsdp" }, + { PPC_INS_XSNEGDP, "xsnegdp" }, + { PPC_INS_XSNMADDADP, "xsnmaddadp" }, + { PPC_INS_XSNMADDMDP, "xsnmaddmdp" }, + { PPC_INS_XSNMSUBADP, "xsnmsubadp" }, + { PPC_INS_XSNMSUBMDP, "xsnmsubmdp" }, + { PPC_INS_XSRDPI, "xsrdpi" }, + { PPC_INS_XSRDPIC, "xsrdpic" }, + { PPC_INS_XSRDPIM, "xsrdpim" }, + { PPC_INS_XSRDPIP, "xsrdpip" }, + { PPC_INS_XSRDPIZ, "xsrdpiz" }, + { PPC_INS_XSREDP, "xsredp" }, + { PPC_INS_XSRSQRTEDP, "xsrsqrtedp" }, + { PPC_INS_XSSQRTDP, "xssqrtdp" }, + { PPC_INS_XSSUBDP, "xssubdp" }, + { PPC_INS_XSTDIVDP, "xstdivdp" }, + { PPC_INS_XSTSQRTDP, "xstsqrtdp" }, + { PPC_INS_XVABSDP, "xvabsdp" }, + { PPC_INS_XVABSSP, "xvabssp" }, + { PPC_INS_XVADDDP, "xvadddp" }, + { PPC_INS_XVADDSP, "xvaddsp" }, + { PPC_INS_XVCMPEQDP, "xvcmpeqdp" }, + { PPC_INS_XVCMPEQSP, "xvcmpeqsp" }, + { PPC_INS_XVCMPGEDP, "xvcmpgedp" }, + { PPC_INS_XVCMPGESP, "xvcmpgesp" }, + { PPC_INS_XVCMPGTDP, "xvcmpgtdp" }, + { PPC_INS_XVCMPGTSP, "xvcmpgtsp" }, + { PPC_INS_XVCPSGNDP, "xvcpsgndp" }, + { PPC_INS_XVCPSGNSP, "xvcpsgnsp" }, + { PPC_INS_XVCVDPSP, "xvcvdpsp" }, + { PPC_INS_XVCVDPSXDS, "xvcvdpsxds" }, + { PPC_INS_XVCVDPSXWS, "xvcvdpsxws" }, + { PPC_INS_XVCVDPUXDS, "xvcvdpuxds" }, + { PPC_INS_XVCVDPUXWS, "xvcvdpuxws" }, + { PPC_INS_XVCVSPDP, "xvcvspdp" }, + { PPC_INS_XVCVSPSXDS, "xvcvspsxds" }, + { PPC_INS_XVCVSPSXWS, "xvcvspsxws" }, + { PPC_INS_XVCVSPUXDS, "xvcvspuxds" }, + { PPC_INS_XVCVSPUXWS, "xvcvspuxws" }, + { PPC_INS_XVCVSXDDP, "xvcvsxddp" }, + { PPC_INS_XVCVSXDSP, "xvcvsxdsp" }, + { PPC_INS_XVCVSXWDP, "xvcvsxwdp" }, + { PPC_INS_XVCVSXWSP, "xvcvsxwsp" }, + { PPC_INS_XVCVUXDDP, "xvcvuxddp" }, + { PPC_INS_XVCVUXDSP, "xvcvuxdsp" }, + { PPC_INS_XVCVUXWDP, "xvcvuxwdp" }, + { PPC_INS_XVCVUXWSP, "xvcvuxwsp" }, + { PPC_INS_XVDIVDP, "xvdivdp" }, + { PPC_INS_XVDIVSP, "xvdivsp" }, + { PPC_INS_XVMADDADP, "xvmaddadp" }, + { PPC_INS_XVMADDASP, "xvmaddasp" }, + { PPC_INS_XVMADDMDP, "xvmaddmdp" }, + { PPC_INS_XVMADDMSP, "xvmaddmsp" }, + { PPC_INS_XVMAXDP, "xvmaxdp" }, + { PPC_INS_XVMAXSP, "xvmaxsp" }, + { PPC_INS_XVMINDP, "xvmindp" }, + { PPC_INS_XVMINSP, "xvminsp" }, + { PPC_INS_XVMSUBADP, "xvmsubadp" }, + { PPC_INS_XVMSUBASP, "xvmsubasp" }, + { PPC_INS_XVMSUBMDP, "xvmsubmdp" }, + { PPC_INS_XVMSUBMSP, "xvmsubmsp" }, + { PPC_INS_XVMULDP, "xvmuldp" }, + { PPC_INS_XVMULSP, "xvmulsp" }, + { PPC_INS_XVNABSDP, "xvnabsdp" }, + { PPC_INS_XVNABSSP, "xvnabssp" }, + { PPC_INS_XVNEGDP, "xvnegdp" }, + { PPC_INS_XVNEGSP, "xvnegsp" }, + { PPC_INS_XVNMADDADP, "xvnmaddadp" }, + { PPC_INS_XVNMADDASP, "xvnmaddasp" }, + { PPC_INS_XVNMADDMDP, "xvnmaddmdp" }, + { PPC_INS_XVNMADDMSP, "xvnmaddmsp" }, + { PPC_INS_XVNMSUBADP, "xvnmsubadp" }, + { PPC_INS_XVNMSUBASP, "xvnmsubasp" }, + { PPC_INS_XVNMSUBMDP, "xvnmsubmdp" }, + { PPC_INS_XVNMSUBMSP, "xvnmsubmsp" }, + { PPC_INS_XVRDPI, "xvrdpi" }, + { PPC_INS_XVRDPIC, "xvrdpic" }, + { PPC_INS_XVRDPIM, "xvrdpim" }, + { PPC_INS_XVRDPIP, "xvrdpip" }, + { PPC_INS_XVRDPIZ, "xvrdpiz" }, + { PPC_INS_XVREDP, "xvredp" }, + { PPC_INS_XVRESP, "xvresp" }, + { PPC_INS_XVRSPI, "xvrspi" }, + { PPC_INS_XVRSPIC, "xvrspic" }, + { PPC_INS_XVRSPIM, "xvrspim" }, + { PPC_INS_XVRSPIP, "xvrspip" }, + { PPC_INS_XVRSPIZ, "xvrspiz" }, + { PPC_INS_XVRSQRTEDP, "xvrsqrtedp" }, + { PPC_INS_XVRSQRTESP, "xvrsqrtesp" }, + { PPC_INS_XVSQRTDP, "xvsqrtdp" }, + { PPC_INS_XVSQRTSP, "xvsqrtsp" }, + { PPC_INS_XVSUBDP, "xvsubdp" }, + { PPC_INS_XVSUBSP, "xvsubsp" }, + { PPC_INS_XVTDIVDP, "xvtdivdp" }, + { PPC_INS_XVTDIVSP, "xvtdivsp" }, + { PPC_INS_XVTSQRTDP, "xvtsqrtdp" }, + { PPC_INS_XVTSQRTSP, "xvtsqrtsp" }, + { PPC_INS_XXLAND, "xxland" }, + { PPC_INS_XXLANDC, "xxlandc" }, + { PPC_INS_XXLEQV, "xxleqv" }, + { PPC_INS_XXLNAND, "xxlnand" }, + { PPC_INS_XXLNOR, "xxlnor" }, + { PPC_INS_XXLOR, "xxlor" }, + { PPC_INS_XXLORC, "xxlorc" }, + { PPC_INS_XXLXOR, "xxlxor" }, + { PPC_INS_XXMRGHW, "xxmrghw" }, + { PPC_INS_XXMRGLW, "xxmrglw" }, + { PPC_INS_XXPERMDI, "xxpermdi" }, + { PPC_INS_XXSEL, "xxsel" }, + { PPC_INS_XXSLDWI, "xxsldwi" }, + { PPC_INS_XXSPLTW, "xxspltw" }, + { PPC_INS_BCA, "bca" }, + { PPC_INS_BCLA, "bcla" }, + + // extra & alias instructions + { PPC_INS_SLWI, "slwi" }, + { PPC_INS_SRWI, "srwi" }, + { PPC_INS_SLDI, "sldi" }, + { PPC_INS_BTA, "bta" }, + { PPC_INS_CRSET, "crset" }, + { PPC_INS_CRNOT, "crnot" }, + { PPC_INS_CRMOVE, "crmove" }, + { PPC_INS_CRCLR, "crclr" }, + { PPC_INS_MFBR0, "mfbr0" }, + { PPC_INS_MFBR1, "mfbr1" }, + { PPC_INS_MFBR2, "mfbr2" }, + { PPC_INS_MFBR3, "mfbr3" }, + { PPC_INS_MFBR4, "mfbr4" }, + { PPC_INS_MFBR5, "mfbr5" }, + { PPC_INS_MFBR6, "mfbr6" }, + { PPC_INS_MFBR7, "mfbr7" }, + { PPC_INS_MFXER, "mfxer" }, + { PPC_INS_MFRTCU, "mfrtcu" }, + { PPC_INS_MFRTCL, "mfrtcl" }, + { PPC_INS_MFDSCR, "mfdscr" }, + { PPC_INS_MFDSISR, "mfdsisr" }, + { PPC_INS_MFDAR, "mfdar" }, + { PPC_INS_MFSRR2, "mfsrr2" }, + { PPC_INS_MFSRR3, "mfsrr3" }, + { PPC_INS_MFCFAR, "mfcfar" }, + { PPC_INS_MFAMR, "mfamr" }, + { PPC_INS_MFPID, "mfpid" }, + { PPC_INS_MFTBLO, "mftblo" }, + { PPC_INS_MFTBHI, "mftbhi" }, + { PPC_INS_MFDBATU, "mfdbatu" }, + { PPC_INS_MFDBATL, "mfdbatl" }, + { PPC_INS_MFIBATU, "mfibatu" }, + { PPC_INS_MFIBATL, "mfibatl" }, + { PPC_INS_MFDCCR, "mfdccr" }, + { PPC_INS_MFICCR, "mficcr" }, + { PPC_INS_MFDEAR, "mfdear" }, + { PPC_INS_MFESR, "mfesr" }, + { PPC_INS_MFSPEFSCR, "mfspefscr" }, + { PPC_INS_MFTCR, "mftcr" }, + { PPC_INS_MFASR, "mfasr" }, + { PPC_INS_MFPVR, "mfpvr" }, + { PPC_INS_MFTBU, "mftbu" }, + { PPC_INS_MTCR, "mtcr" }, + { PPC_INS_MTBR0, "mtbr0" }, + { PPC_INS_MTBR1, "mtbr1" }, + { PPC_INS_MTBR2, "mtbr2" }, + { PPC_INS_MTBR3, "mtbr3" }, + { PPC_INS_MTBR4, "mtbr4" }, + { PPC_INS_MTBR5, "mtbr5" }, + { PPC_INS_MTBR6, "mtbr6" }, + { PPC_INS_MTBR7, "mtbr7" }, + { PPC_INS_MTXER, "mtxer" }, + { PPC_INS_MTDSCR, "mtdscr" }, + { PPC_INS_MTDSISR, "mtdsisr" }, + { PPC_INS_MTDAR, "mtdar" }, + { PPC_INS_MTSRR2, "mtsrr2" }, + { PPC_INS_MTSRR3, "mtsrr3" }, + { PPC_INS_MTCFAR, "mtcfar" }, + { PPC_INS_MTAMR, "mtamr" }, + { PPC_INS_MTPID, "mtpid" }, + { PPC_INS_MTTBL, "mttbl" }, + { PPC_INS_MTTBU, "mttbu" }, + { PPC_INS_MTTBLO, "mttblo" }, + { PPC_INS_MTTBHI, "mttbhi" }, + { PPC_INS_MTDBATU, "mtdbatu" }, + { PPC_INS_MTDBATL, "mtdbatl" }, + { PPC_INS_MTIBATU, "mtibatu" }, + { PPC_INS_MTIBATL, "mtibatl" }, + { PPC_INS_MTDCCR, "mtdccr" }, + { PPC_INS_MTICCR, "mticcr" }, + { PPC_INS_MTDEAR, "mtdear" }, + { PPC_INS_MTESR, "mtesr" }, + { PPC_INS_MTSPEFSCR, "mtspefscr" }, + { PPC_INS_MTTCR, "mttcr" }, + { PPC_INS_NOT, "not" }, + { PPC_INS_MR, "mr" }, + { PPC_INS_ROTLD, "rotld" }, + { PPC_INS_ROTLDI, "rotldi" }, + { PPC_INS_CLRLDI, "clrldi" }, + { PPC_INS_ROTLWI, "rotlwi" }, + { PPC_INS_CLRLWI, "clrlwi" }, + { PPC_INS_ROTLW, "rotlw" }, + { PPC_INS_SUB, "sub" }, + { PPC_INS_SUBC, "subc" }, + { PPC_INS_LWSYNC, "lwsync" }, + { PPC_INS_PTESYNC, "ptesync" }, + { PPC_INS_TDLT, "tdlt" }, + { PPC_INS_TDEQ, "tdeq" }, + { PPC_INS_TDGT, "tdgt" }, + { PPC_INS_TDNE, "tdne" }, + { PPC_INS_TDLLT, "tdllt" }, + { PPC_INS_TDLGT, "tdlgt" }, + { PPC_INS_TDU, "tdu" }, + { PPC_INS_TDLTI, "tdlti" }, + { PPC_INS_TDEQI, "tdeqi" }, + { PPC_INS_TDGTI, "tdgti" }, + { PPC_INS_TDNEI, "tdnei" }, + { PPC_INS_TDLLTI, "tdllti" }, + { PPC_INS_TDLGTI, "tdlgti" }, + { PPC_INS_TDUI, "tdui" }, + { PPC_INS_TLBREHI, "tlbrehi" }, + { PPC_INS_TLBRELO, "tlbrelo" }, + { PPC_INS_TLBWEHI, "tlbwehi" }, + { PPC_INS_TLBWELO, "tlbwelo" }, + { PPC_INS_TWLT, "twlt" }, + { PPC_INS_TWEQ, "tweq" }, + { PPC_INS_TWGT, "twgt" }, + { PPC_INS_TWNE, "twne" }, + { PPC_INS_TWLLT, "twllt" }, + { PPC_INS_TWLGT, "twlgt" }, + { PPC_INS_TWU, "twu" }, + { PPC_INS_TWLTI, "twlti" }, + { PPC_INS_TWEQI, "tweqi" }, + { PPC_INS_TWGTI, "twgti" }, + { PPC_INS_TWNEI, "twnei" }, + { PPC_INS_TWLLTI, "twllti" }, + { PPC_INS_TWLGTI, "twlgti" }, + { PPC_INS_TWUI, "twui" }, + { PPC_INS_WAITRSV, "waitrsv" }, + { PPC_INS_WAITIMPL, "waitimpl" }, + { PPC_INS_XNOP, "xnop" }, + { PPC_INS_XVMOVDP, "xvmovdp" }, + { PPC_INS_XVMOVSP, "xvmovsp" }, + { PPC_INS_XXSPLTD, "xxspltd" }, + { PPC_INS_XXMRGHD, "xxmrghd" }, + { PPC_INS_XXMRGLD, "xxmrgld" }, + { PPC_INS_XXSWAPD, "xxswapd" }, + { PPC_INS_BT, "bt" }, + { PPC_INS_BF, "bf" }, + { PPC_INS_BDNZT, "bdnzt" }, + { PPC_INS_BDNZF, "bdnzf" }, + { PPC_INS_BDZF, "bdzf" }, + { PPC_INS_BDZT, "bdzt" }, + { PPC_INS_BFA, "bfa" }, + { PPC_INS_BDNZTA, "bdnzta" }, + { PPC_INS_BDNZFA, "bdnzfa" }, + { PPC_INS_BDZTA, "bdzta" }, + { PPC_INS_BDZFA, "bdzfa" }, + { PPC_INS_BTCTR, "btctr" }, + { PPC_INS_BFCTR, "bfctr" }, + { PPC_INS_BTCTRL, "btctrl" }, + { PPC_INS_BFCTRL, "bfctrl" }, + { PPC_INS_BTL, "btl" }, + { PPC_INS_BFL, "bfl" }, + { PPC_INS_BDNZTL, "bdnztl" }, + { PPC_INS_BDNZFL, "bdnzfl" }, + { PPC_INS_BDZTL, "bdztl" }, + { PPC_INS_BDZFL, "bdzfl" }, + { PPC_INS_BTLA, "btla" }, + { PPC_INS_BFLA, "bfla" }, + { PPC_INS_BDNZTLA, "bdnztla" }, + { PPC_INS_BDNZFLA, "bdnzfla" }, + { PPC_INS_BDZTLA, "bdztla" }, + { PPC_INS_BDZFLA, "bdzfla" }, + { PPC_INS_BTLR, "btlr" }, + { PPC_INS_BFLR, "bflr" }, + { PPC_INS_BDNZTLR, "bdnztlr" }, + { PPC_INS_BDZTLR, "bdztlr" }, + { PPC_INS_BDZFLR, "bdzflr" }, + { PPC_INS_BTLRL, "btlrl" }, + { PPC_INS_BFLRL, "bflrl" }, + { PPC_INS_BDNZTLRL, "bdnztlrl" }, + { PPC_INS_BDNZFLRL, "bdnzflrl" }, + { PPC_INS_BDZTLRL, "bdztlrl" }, + { PPC_INS_BDZFLRL, "bdzflrl" }, + + // QPX + { PPC_INS_QVFAND, "qvfand" }, + { PPC_INS_QVFCLR, "qvfclr" }, + { PPC_INS_QVFANDC, "qvfandc" }, + { PPC_INS_QVFCTFB, "qvfctfb" }, + { PPC_INS_QVFXOR, "qvfxor" }, + { PPC_INS_QVFOR, "qvfor" }, + { PPC_INS_QVFNOR, "qvfnor" }, + { PPC_INS_QVFEQU, "qvfequ" }, + { PPC_INS_QVFNOT, "qvfnot" }, + { PPC_INS_QVFORC, "qvforc" }, + { PPC_INS_QVFNAND, "qvfnand" }, + { PPC_INS_QVFSET, "qvfset" }, +}; + +// special alias insn +static const name_map alias_insn_names[] = { + { 0, NULL } +}; +#endif + +const char *PPC_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= PPC_INS_ENDING) + return NULL; + + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { PPC_GRP_INVALID, NULL }, + { PPC_GRP_JUMP, "jump" }, + + // architecture-specific groups + { PPC_GRP_ALTIVEC, "altivec" }, + { PPC_GRP_MODE32, "mode32" }, + { PPC_GRP_MODE64, "mode64" }, + { PPC_GRP_BOOKE, "booke" }, + { PPC_GRP_NOTBOOKE, "notbooke" }, + { PPC_GRP_SPE, "spe" }, + { PPC_GRP_VSX, "vsx" }, + { PPC_GRP_E500, "e500" }, + { PPC_GRP_PPC4XX, "ppc4xx" }, + { PPC_GRP_PPC6XX, "ppc6xx" }, + { PPC_GRP_ICBT, "icbt" }, + { PPC_GRP_P8ALTIVEC, "p8altivec" }, + { PPC_GRP_P8VECTOR, "p8vector" }, + { PPC_GRP_QPX, "qpx" }, +}; +#endif + +const char *PPC_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map internal raw register to 'public' register +ppc_reg PPC_map_register(unsigned int r) +{ + static unsigned int map[] = { 0, + 0, PPC_REG_CARRY, PPC_REG_CTR, 0, PPC_REG_LR, + 0, PPC_REG_VRSAVE, PPC_REG_R0, 0, PPC_REG_CR0, + PPC_REG_CR1, PPC_REG_CR2, PPC_REG_CR3, PPC_REG_CR4, PPC_REG_CR5, + PPC_REG_CR6, PPC_REG_CR7, PPC_REG_CTR, PPC_REG_F0, PPC_REG_F1, + PPC_REG_F2, PPC_REG_F3, PPC_REG_F4, PPC_REG_F5, PPC_REG_F6, + PPC_REG_F7, PPC_REG_F8, PPC_REG_F9, PPC_REG_F10, PPC_REG_F11, + PPC_REG_F12, PPC_REG_F13, PPC_REG_F14, PPC_REG_F15, PPC_REG_F16, + PPC_REG_F17, PPC_REG_F18, PPC_REG_F19, PPC_REG_F20, PPC_REG_F21, + PPC_REG_F22, PPC_REG_F23, PPC_REG_F24, PPC_REG_F25, PPC_REG_F26, + PPC_REG_F27, PPC_REG_F28, PPC_REG_F29, PPC_REG_F30, PPC_REG_F31, + 0, PPC_REG_LR, PPC_REG_Q0, PPC_REG_Q1, PPC_REG_Q2, + PPC_REG_Q3, PPC_REG_Q4, PPC_REG_Q5, PPC_REG_Q6, PPC_REG_Q7, + PPC_REG_Q8, PPC_REG_Q9, PPC_REG_Q10, PPC_REG_Q11, PPC_REG_Q12, + PPC_REG_Q13, PPC_REG_Q14, PPC_REG_Q15, PPC_REG_Q16, PPC_REG_Q17, + PPC_REG_Q18, PPC_REG_Q19, PPC_REG_Q20, PPC_REG_Q21, PPC_REG_Q22, + PPC_REG_Q23, PPC_REG_Q24, PPC_REG_Q25, PPC_REG_Q26, PPC_REG_Q27, + PPC_REG_Q28, PPC_REG_Q29, PPC_REG_Q30, PPC_REG_Q31, PPC_REG_R0, + PPC_REG_R1, PPC_REG_R2, PPC_REG_R3, PPC_REG_R4, PPC_REG_R5, + PPC_REG_R6, PPC_REG_R7, PPC_REG_R8, PPC_REG_R9, PPC_REG_R10, + PPC_REG_R11, PPC_REG_R12, PPC_REG_R13, PPC_REG_R14, PPC_REG_R15, + PPC_REG_R16, PPC_REG_R17, PPC_REG_R18, PPC_REG_R19, PPC_REG_R20, + PPC_REG_R21, PPC_REG_R22, PPC_REG_R23, PPC_REG_R24, PPC_REG_R25, + PPC_REG_R26, PPC_REG_R27, PPC_REG_R28, PPC_REG_R29, PPC_REG_R30, + PPC_REG_R31, PPC_REG_V0, PPC_REG_V1, PPC_REG_V2, PPC_REG_V3, + PPC_REG_V4, PPC_REG_V5, PPC_REG_V6, PPC_REG_V7, PPC_REG_V8, + PPC_REG_V9, PPC_REG_V10, PPC_REG_V11, PPC_REG_V12, PPC_REG_V13, + PPC_REG_V14, PPC_REG_V15, PPC_REG_V16, PPC_REG_V17, PPC_REG_V18, + PPC_REG_V19, PPC_REG_V20, PPC_REG_V21, PPC_REG_V22, PPC_REG_V23, + PPC_REG_V24, PPC_REG_V25, PPC_REG_V26, PPC_REG_V27, PPC_REG_V28, + PPC_REG_V29, PPC_REG_V30, PPC_REG_V31, PPC_REG_VS32, PPC_REG_VS33, + PPC_REG_VS34, PPC_REG_VS35, PPC_REG_VS36, PPC_REG_VS37, PPC_REG_VS38, + PPC_REG_VS39, PPC_REG_VS40, PPC_REG_VS41, PPC_REG_VS42, PPC_REG_VS43, + PPC_REG_VS44, PPC_REG_VS45, PPC_REG_VS46, PPC_REG_VS47, PPC_REG_VS48, + PPC_REG_VS49, PPC_REG_VS50, PPC_REG_VS51, PPC_REG_VS52, PPC_REG_VS53, + PPC_REG_VS54, PPC_REG_VS55, PPC_REG_VS56, PPC_REG_VS57, PPC_REG_VS58, + PPC_REG_VS59, PPC_REG_VS60, PPC_REG_VS61, PPC_REG_VS62, PPC_REG_VS63, + PPC_REG_VS32, PPC_REG_VS33, PPC_REG_VS34, PPC_REG_VS35, PPC_REG_VS36, + PPC_REG_VS37, PPC_REG_VS38, PPC_REG_VS39, PPC_REG_VS40, PPC_REG_VS41, + PPC_REG_VS42, PPC_REG_VS43, PPC_REG_VS44, PPC_REG_VS45, PPC_REG_VS46, + PPC_REG_VS47, PPC_REG_VS48, PPC_REG_VS49, PPC_REG_VS50, PPC_REG_VS51, + PPC_REG_VS52, PPC_REG_VS53, PPC_REG_VS54, PPC_REG_VS55, PPC_REG_VS56, + PPC_REG_VS57, PPC_REG_VS58, PPC_REG_VS59, PPC_REG_VS60, PPC_REG_VS61, + PPC_REG_VS62, PPC_REG_VS63, PPC_REG_VS0, PPC_REG_VS1, PPC_REG_VS2, + PPC_REG_VS3, PPC_REG_VS4, PPC_REG_VS5, PPC_REG_VS6, PPC_REG_VS7, + PPC_REG_VS8, PPC_REG_VS9, PPC_REG_VS10, PPC_REG_VS11, PPC_REG_VS12, + PPC_REG_VS13, PPC_REG_VS14, PPC_REG_VS15, PPC_REG_VS16, PPC_REG_VS17, + PPC_REG_VS18, PPC_REG_VS19, PPC_REG_VS20, PPC_REG_VS21, PPC_REG_VS22, + PPC_REG_VS23, PPC_REG_VS24, PPC_REG_VS25, PPC_REG_VS26, PPC_REG_VS27, + PPC_REG_VS28, PPC_REG_VS29, PPC_REG_VS30, PPC_REG_VS31, PPC_REG_R0, + PPC_REG_R1, PPC_REG_R2, PPC_REG_R3, PPC_REG_R4, PPC_REG_R5, + PPC_REG_R6, PPC_REG_R7, PPC_REG_R8, PPC_REG_R9, PPC_REG_R10, + PPC_REG_R11, PPC_REG_R12, PPC_REG_R13, PPC_REG_R14, PPC_REG_R15, + PPC_REG_R16, PPC_REG_R17, PPC_REG_R18, PPC_REG_R19, PPC_REG_R20, + PPC_REG_R21, PPC_REG_R22, PPC_REG_R23, PPC_REG_R24, PPC_REG_R25, + PPC_REG_R26, PPC_REG_R27, PPC_REG_R28, PPC_REG_R29, PPC_REG_R30, + PPC_REG_R31, PPC_REG_R0, PPC_REG_R2, PPC_REG_R6, PPC_REG_R10, + PPC_REG_R14, PPC_REG_R18, PPC_REG_R22, PPC_REG_R26, PPC_REG_R30, + PPC_REG_R1, PPC_REG_R5, PPC_REG_R9, PPC_REG_R13, PPC_REG_R17, + PPC_REG_R21, PPC_REG_R25, PPC_REG_R29, PPC_REG_R0, PPC_REG_R4, + PPC_REG_R8, PPC_REG_R12, PPC_REG_R16, PPC_REG_R20, PPC_REG_R24, + PPC_REG_R28, PPC_REG_R3, PPC_REG_R7, PPC_REG_R11, PPC_REG_R15, + PPC_REG_R19, PPC_REG_R23, PPC_REG_R27, PPC_REG_R31 }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +static const struct ppc_alias alias_insn_name_maps[] = { + //{ PPC_INS_BTA, "bta" }, + { PPC_INS_B, PPC_BC_LT, "blt" }, + { PPC_INS_B, PPC_BC_LE, "ble" }, + { PPC_INS_B, PPC_BC_EQ, "beq" }, + { PPC_INS_B, PPC_BC_GE, "bge" }, + { PPC_INS_B, PPC_BC_GT, "bgt" }, + { PPC_INS_B, PPC_BC_NE, "bne" }, + { PPC_INS_B, PPC_BC_UN, "bun" }, + { PPC_INS_B, PPC_BC_NU, "bnu" }, + { PPC_INS_B, PPC_BC_SO, "bso" }, + { PPC_INS_B, PPC_BC_NS, "bns" }, + + { PPC_INS_BA, PPC_BC_LT, "blta" }, + { PPC_INS_BA, PPC_BC_LE, "blea" }, + { PPC_INS_BA, PPC_BC_EQ, "beqa" }, + { PPC_INS_BA, PPC_BC_GE, "bgea" }, + { PPC_INS_BA, PPC_BC_GT, "bgta" }, + { PPC_INS_BA, PPC_BC_NE, "bnea" }, + { PPC_INS_BA, PPC_BC_UN, "buna" }, + { PPC_INS_BA, PPC_BC_NU, "bnua" }, + { PPC_INS_BA, PPC_BC_SO, "bsoa" }, + { PPC_INS_BA, PPC_BC_NS, "bnsa" }, + + { PPC_INS_BCTR, PPC_BC_LT, "bltctr" }, + { PPC_INS_BCTR, PPC_BC_LE, "blectr" }, + { PPC_INS_BCTR, PPC_BC_EQ, "beqctr" }, + { PPC_INS_BCTR, PPC_BC_GE, "bgectr" }, + { PPC_INS_BCTR, PPC_BC_GT, "bgtctr" }, + { PPC_INS_BCTR, PPC_BC_NE, "bnectr" }, + { PPC_INS_BCTR, PPC_BC_UN, "bunctr" }, + { PPC_INS_BCTR, PPC_BC_NU, "bnuctr" }, + { PPC_INS_BCTR, PPC_BC_SO, "bsoctr" }, + { PPC_INS_BCTR, PPC_BC_NS, "bnsctr" }, + + { PPC_INS_BCTRL, PPC_BC_LT, "bltctrl" }, + { PPC_INS_BCTRL, PPC_BC_LE, "blectrl" }, + { PPC_INS_BCTRL, PPC_BC_EQ, "beqctrl" }, + { PPC_INS_BCTRL, PPC_BC_GE, "bgectrl" }, + { PPC_INS_BCTRL, PPC_BC_GT, "bgtctrl" }, + { PPC_INS_BCTRL, PPC_BC_NE, "bnectrl" }, + { PPC_INS_BCTRL, PPC_BC_UN, "bunctrl" }, + { PPC_INS_BCTRL, PPC_BC_NU, "bnuctrl" }, + { PPC_INS_BCTRL, PPC_BC_SO, "bsoctrl" }, + { PPC_INS_BCTRL, PPC_BC_NS, "bnsctrl" }, + + { PPC_INS_BL, PPC_BC_LT, "bltl" }, + { PPC_INS_BL, PPC_BC_LE, "blel" }, + { PPC_INS_BL, PPC_BC_EQ, "beql" }, + { PPC_INS_BL, PPC_BC_GE, "bgel" }, + { PPC_INS_BL, PPC_BC_GT, "bgtl" }, + { PPC_INS_BL, PPC_BC_NE, "bnel" }, + { PPC_INS_BL, PPC_BC_UN, "bunl" }, + { PPC_INS_BL, PPC_BC_NU, "bnul" }, + { PPC_INS_BL, PPC_BC_SO, "bsol" }, + { PPC_INS_BL, PPC_BC_NS, "bnsl" }, + + { PPC_INS_BLA, PPC_BC_LT, "bltla" }, + { PPC_INS_BLA, PPC_BC_LE, "blela" }, + { PPC_INS_BLA, PPC_BC_EQ, "beqla" }, + { PPC_INS_BLA, PPC_BC_GE, "bgela" }, + { PPC_INS_BLA, PPC_BC_GT, "bgtla" }, + { PPC_INS_BLA, PPC_BC_NE, "bnela" }, + { PPC_INS_BLA, PPC_BC_UN, "bunla" }, + { PPC_INS_BLA, PPC_BC_NU, "bnula" }, + { PPC_INS_BLA, PPC_BC_SO, "bsola" }, + { PPC_INS_BLA, PPC_BC_NS, "bnsla" }, + + { PPC_INS_BLR, PPC_BC_LT, "bltlr" }, + { PPC_INS_BLR, PPC_BC_LE, "blelr" }, + { PPC_INS_BLR, PPC_BC_EQ, "beqlr" }, + { PPC_INS_BLR, PPC_BC_GE, "bgelr" }, + { PPC_INS_BLR, PPC_BC_GT, "bgtlr" }, + { PPC_INS_BLR, PPC_BC_NE, "bnelr" }, + { PPC_INS_BLR, PPC_BC_UN, "bunlr" }, + { PPC_INS_BLR, PPC_BC_NU, "bnulr" }, + { PPC_INS_BLR, PPC_BC_SO, "bsolr" }, + { PPC_INS_BLR, PPC_BC_NS, "bnslr" }, + + { PPC_INS_BLRL, PPC_BC_LT, "bltlrl" }, + { PPC_INS_BLRL, PPC_BC_LE, "blelrl" }, + { PPC_INS_BLRL, PPC_BC_EQ, "beqlrl" }, + { PPC_INS_BLRL, PPC_BC_GE, "bgelrl" }, + { PPC_INS_BLRL, PPC_BC_GT, "bgtlrl" }, + { PPC_INS_BLRL, PPC_BC_NE, "bnelrl" }, + { PPC_INS_BLRL, PPC_BC_UN, "bunlrl" }, + { PPC_INS_BLRL, PPC_BC_NU, "bnulrl" }, + { PPC_INS_BLRL, PPC_BC_SO, "bsolrl" }, + { PPC_INS_BLRL, PPC_BC_NS, "bnslrl" }, +}; + +// given alias mnemonic, return instruction ID & CC +bool PPC_alias_insn(const char *name, struct ppc_alias *alias) +{ + size_t i; +#ifndef CAPSTONE_DIET + int x; +#endif + + for(i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { + if (!strcmp(name, alias_insn_name_maps[i].mnem)) { + alias->id = alias_insn_name_maps[i].id; + alias->cc = alias_insn_name_maps[i].cc; + return true; + } + } + +#ifndef CAPSTONE_DIET + // not really an alias insn + x = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + if (x != -1) { + alias->id = insn_name_maps[x].id; + alias->cc = PPC_BC_INVALID; + return true; + } +#endif + + // not found + return false; +} + +// list all relative branch instructions +static const unsigned int insn_abs[] = { + PPC_BA, + PPC_BCCA, + PPC_BCCLA, + PPC_BDNZA, + PPC_BDNZAm, + PPC_BDNZAp, + PPC_BDNZLA, + PPC_BDNZLAm, + PPC_BDNZLAp, + PPC_BDZA, + PPC_BDZAm, + PPC_BDZAp, + PPC_BDZLAm, + PPC_BDZLAp, + PPC_BLA, + PPC_gBCA, + PPC_gBCLA, + 0 +}; + +// check if this insn is relative branch +bool PPC_abs_branch(cs_struct *h, unsigned int id) +{ + int i; + + for (i = 0; insn_abs[i]; i++) { + if (id == insn_abs[i]) { + return true; + } + } + + // not found + return false; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.h b/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.h new file mode 100644 index 0000000..2e2fa4f --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCMapping.h @@ -0,0 +1,34 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_PPC_MAP_H +#define CS_PPC_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *PPC_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *PPC_insn_name(csh handle, unsigned int id); +const char *PPC_group_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +ppc_reg PPC_map_register(unsigned int r); + +struct ppc_alias { + unsigned int id; // instruction id + int cc; // code condition + const char *mnem; +}; + +// given alias mnemonic, return instruction ID & CC +bool PPC_alias_insn(const char *name, struct ppc_alias *alias); + +// check if this insn is relative branch +bool PPC_abs_branch(cs_struct *h, unsigned int id); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCMappingInsn.inc b/white_patch_detect/capstone-master/arch/PowerPC/PPCMappingInsn.inc new file mode 100644 index 0000000..9252a95 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCMappingInsn.inc @@ -0,0 +1,8055 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + PPC_ADD4, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD4TLS, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD4o, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD8, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD8TLS, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD8TLS_, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADD8o, PPC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDC, PPC_INS_ADDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDC8, PPC_INS_ADDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDC8o, PPC_INS_ADDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDCo, PPC_INS_ADDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDE, PPC_INS_ADDE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDE8, PPC_INS_ADDE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDE8o, PPC_INS_ADDE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDEo, PPC_INS_ADDE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDI, PPC_INS_ADDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDI8, PPC_INS_ADDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDIC, PPC_INS_ADDIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDIC8, PPC_INS_ADDIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDICo, PPC_INS_ADDIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDIS, PPC_INS_ADDIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDIS8, PPC_INS_ADDIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDME, PPC_INS_ADDME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDME8, PPC_INS_ADDME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDME8o, PPC_INS_ADDME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDMEo, PPC_INS_ADDME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDZE, PPC_INS_ADDZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDZE8, PPC_INS_ADDZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDZE8o, PPC_INS_ADDZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ADDZEo, PPC_INS_ADDZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_AND, PPC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_AND8, PPC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_AND8o, PPC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDC, PPC_INS_ANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDC8, PPC_INS_ANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDC8o, PPC_INS_ANDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDCo, PPC_INS_ANDC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDISo, PPC_INS_ANDIS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDISo8, PPC_INS_ANDIS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDIo, PPC_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDIo8, PPC_INS_ANDI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ANDo, PPC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ATTN, PPC_INS_ATTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_B, PPC_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BA, PPC_INS_BA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BC, PPC_INS_BC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCC, PPC_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCCA, PPC_INS_BA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCCCTR, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + PPC_BCCCTR8, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 +#endif +}, +{ + PPC_BCCCTRL, PPC_INS_BCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCCTRL8, PPC_INS_BCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BCCL, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCLA, PPC_INS_BLA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCLR, PPC_INS_BLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCCLRL, PPC_INS_BLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCTR, PPC_INS_BCCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + PPC_BCCTR8, PPC_INS_BCCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 +#endif +}, +{ + PPC_BCCTR8n, PPC_INS_BCCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 +#endif +}, +{ + PPC_BCCTRL, PPC_INS_BCCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCTRL8, PPC_INS_BCCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BCCTRL8n, PPC_INS_BCCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BCCTRLn, PPC_INS_BCCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCCTRn, PPC_INS_BCCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + PPC_BCL, PPC_INS_BCL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCLR, PPC_INS_BCLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCLRL, PPC_INS_BCLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCLRLn, PPC_INS_BCLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCLRn, PPC_INS_BCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BCLalways, PPC_INS_BCL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCLn, PPC_INS_BCL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BCTR, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + PPC_BCTR8, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 +#endif +}, +{ + PPC_BCTRL, PPC_INS_BCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { PPC_GRP_MODE32, 0 }, 0, 0 +#endif +}, +{ + PPC_BCTRL8, PPC_INS_BCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BCTRL8_LDinto_toc, PPC_INS_BCT, // FIXME +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, PPC_REG_X2, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BCn, PPC_INS_BC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZ, PPC_INS_BDNZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZ8, PPC_INS_BDNZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZA, PPC_INS_BDNZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZAm, PPC_INS_BDNZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZAp, PPC_INS_BDNZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZL, PPC_INS_BDNZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLA, PPC_INS_BDNZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLAm, PPC_INS_BDNZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLAp, PPC_INS_BDNZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLR, PPC_INS_BDNZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZLR8, PPC_INS_BDNZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZLRL, PPC_INS_BDNZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLRLm, PPC_INS_BDNZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLRLp, PPC_INS_BDNZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLRm, PPC_INS_BDNZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZLRp, PPC_INS_BDNZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZLm, PPC_INS_BDNZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZLp, PPC_INS_BDNZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDNZm, PPC_INS_BDNZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDNZp, PPC_INS_BDNZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZ, PPC_INS_BDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZ8, PPC_INS_BDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZA, PPC_INS_BDZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZAm, PPC_INS_BDZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZAp, PPC_INS_BDZA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZL, PPC_INS_BDZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLA, PPC_INS_BDZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLAm, PPC_INS_BDZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLAp, PPC_INS_BDZLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLR, PPC_INS_BDZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZLR8, PPC_INS_BDZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZLRL, PPC_INS_BDZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLRLm, PPC_INS_BDZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLRLp, PPC_INS_BDZLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLRm, PPC_INS_BDZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZLRp, PPC_INS_BDZLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZLm, PPC_INS_BDZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZLp, PPC_INS_BDZL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BDZm, PPC_INS_BDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BDZp, PPC_INS_BDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_BL, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL8, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL8_NOP, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL8_NOP_TLS, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL8_TLS, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL8_TLS_, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BLA, PPC_INS_BLA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BLA8, PPC_INS_BLA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BLA8_NOP, PPC_INS_BLA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BLR, PPC_INS_BLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 0, 0 +#endif +}, +{ + PPC_BLR8, PPC_INS_BLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 +#endif +}, +{ + PPC_BLRL, PPC_INS_BLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BL_TLS, PPC_INS_BL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_BRINC, PPC_INS_BRINC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_CMPB, PPC_INS_CMPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPB8, PPC_INS_CMPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPD, PPC_INS_CMPD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPDI, PPC_INS_CMPDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPLD, PPC_INS_CMPLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPLDI, PPC_INS_CMPLDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPLW, PPC_INS_CMPLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPLWI, PPC_INS_CMPLWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPW, PPC_INS_CMPW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CMPWI, PPC_INS_CMPWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZD, PPC_INS_CNTLZD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZDo, PPC_INS_CNTLZD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZW, PPC_INS_CNTLZW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZW8, PPC_INS_CNTLZW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZW8o, PPC_INS_CNTLZW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CNTLZWo, PPC_INS_CNTLZW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CR6SET, PPC_INS_CREQV, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CR6UNSET, PPC_INS_CRXOR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRAND, PPC_INS_CRAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRANDC, PPC_INS_CRANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CREQV, PPC_INS_CREQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRNAND, PPC_INS_CRNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRNOR, PPC_INS_CRNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CROR, PPC_INS_CROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRORC, PPC_INS_CRORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRSET, PPC_INS_CREQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRUNSET, PPC_INS_CRXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_CRXOR, PPC_INS_CRXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBA, PPC_INS_DCBA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBF, PPC_INS_DCBF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBI, PPC_INS_DCBI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBST, PPC_INS_DCBST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBT, PPC_INS_DCBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBTST, PPC_INS_DCBTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBZ, PPC_INS_DCBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCBZL, PPC_INS_DCBZL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DCCCI, PPC_INS_DCCCI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_DIVD, PPC_INS_DIVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVDU, PPC_INS_DIVDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVDUo, PPC_INS_DIVDU, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVDo, PPC_INS_DIVD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVW, PPC_INS_DIVW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVWU, PPC_INS_DIVWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVWUo, PPC_INS_DIVWU, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DIVWo, PPC_INS_DIVW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_DSS, PPC_INS_DSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSSALL, PPC_INS_DSSALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DST, PPC_INS_DST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DST64, PPC_INS_DST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTST, PPC_INS_DSTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTST64, PPC_INS_DSTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTSTT, PPC_INS_DSTSTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTSTT64, PPC_INS_DSTSTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTT, PPC_INS_DSTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_DSTT64, PPC_INS_DSTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_EQV, PPC_INS_EQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EQV8, PPC_INS_EQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EQV8o, PPC_INS_EQV, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EQVo, PPC_INS_EQV, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EVABS, PPC_INS_EVABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDIW, PPC_INS_EVADDIW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDSMIAAW, PPC_INS_EVADDSMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDSSIAAW, PPC_INS_EVADDSSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDUMIAAW, PPC_INS_EVADDUMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDUSIAAW, PPC_INS_EVADDUSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVADDW, PPC_INS_EVADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVAND, PPC_INS_EVAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVANDC, PPC_INS_EVANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCMPEQ, PPC_INS_EVCMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCMPGTS, PPC_INS_EVCMPGTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCMPGTU, PPC_INS_EVCMPGTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCMPLTS, PPC_INS_EVCMPLTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCMPLTU, PPC_INS_EVCMPLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCNTLSW, PPC_INS_EVCNTLSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVCNTLZW, PPC_INS_EVCNTLZW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVDIVWS, PPC_INS_EVDIVWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVDIVWU, PPC_INS_EVDIVWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVEQV, PPC_INS_EVEQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVEXTSB, PPC_INS_EVEXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVEXTSH, PPC_INS_EVEXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDD, PPC_INS_EVLDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDDX, PPC_INS_EVLDDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDH, PPC_INS_EVLDH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDHX, PPC_INS_EVLDHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDW, PPC_INS_EVLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLDWX, PPC_INS_EVLDWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHESPLAT, PPC_INS_EVLHHESPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHESPLATX, PPC_INS_EVLHHESPLATX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHOSSPLAT, PPC_INS_EVLHHOSSPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHOSSPLATX, PPC_INS_EVLHHOSSPLATX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHOUSPLAT, PPC_INS_EVLHHOUSPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLHHOUSPLATX, PPC_INS_EVLHHOUSPLATX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHE, PPC_INS_EVLWHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHEX, PPC_INS_EVLWHEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHOS, PPC_INS_EVLWHOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHOSX, PPC_INS_EVLWHOSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHOU, PPC_INS_EVLWHOU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHOUX, PPC_INS_EVLWHOUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHSPLAT, PPC_INS_EVLWHSPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWHSPLATX, PPC_INS_EVLWHSPLATX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWWSPLAT, PPC_INS_EVLWWSPLAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVLWWSPLATX, PPC_INS_EVLWWSPLATX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMERGEHI, PPC_INS_EVMERGEHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMERGEHILO, PPC_INS_EVMERGEHILO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMERGELO, PPC_INS_EVMERGELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMERGELOHI, PPC_INS_EVMERGELOHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGSMFAA, PPC_INS_EVMHEGSMFAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGSMFAN, PPC_INS_EVMHEGSMFAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGSMIAA, PPC_INS_EVMHEGSMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGSMIAN, PPC_INS_EVMHEGSMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGUMIAA, PPC_INS_EVMHEGUMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEGUMIAN, PPC_INS_EVMHEGUMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMF, PPC_INS_EVMHESMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMFA, PPC_INS_EVMHESMFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMFAAW, PPC_INS_EVMHESMFAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMFANW, PPC_INS_EVMHESMFANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMI, PPC_INS_EVMHESMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMIA, PPC_INS_EVMHESMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMIAAW, PPC_INS_EVMHESMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESMIANW, PPC_INS_EVMHESMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSF, PPC_INS_EVMHESSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSFA, PPC_INS_EVMHESSFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSFAAW, PPC_INS_EVMHESSFAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSFANW, PPC_INS_EVMHESSFANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSIAAW, PPC_INS_EVMHESSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHESSIANW, PPC_INS_EVMHESSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUMI, PPC_INS_EVMHEUMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUMIA, PPC_INS_EVMHEUMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUMIAAW, PPC_INS_EVMHEUMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUMIANW, PPC_INS_EVMHEUMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUSIAAW, PPC_INS_EVMHEUSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHEUSIANW, PPC_INS_EVMHEUSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGSMFAA, PPC_INS_EVMHOGSMFAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGSMFAN, PPC_INS_EVMHOGSMFAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGSMIAA, PPC_INS_EVMHOGSMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGSMIAN, PPC_INS_EVMHOGSMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGUMIAA, PPC_INS_EVMHOGUMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOGUMIAN, PPC_INS_EVMHOGUMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMF, PPC_INS_EVMHOSMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMFA, PPC_INS_EVMHOSMFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMFAAW, PPC_INS_EVMHOSMFAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMFANW, PPC_INS_EVMHOSMFANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMI, PPC_INS_EVMHOSMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMIA, PPC_INS_EVMHOSMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMIAAW, PPC_INS_EVMHOSMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSMIANW, PPC_INS_EVMHOSMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSF, PPC_INS_EVMHOSSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSFA, PPC_INS_EVMHOSSFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSFAAW, PPC_INS_EVMHOSSFAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSFANW, PPC_INS_EVMHOSSFANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSIAAW, PPC_INS_EVMHOSSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOSSIANW, PPC_INS_EVMHOSSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUMI, PPC_INS_EVMHOUMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUMIA, PPC_INS_EVMHOUMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUMIAAW, PPC_INS_EVMHOUMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUMIANW, PPC_INS_EVMHOUMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUSIAAW, PPC_INS_EVMHOUSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMHOUSIANW, PPC_INS_EVMHOUSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMRA, PPC_INS_EVMRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSMF, PPC_INS_EVMWHSMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSMFA, PPC_INS_EVMWHSMFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSMI, PPC_INS_EVMWHSMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSMIA, PPC_INS_EVMWHSMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSSF, PPC_INS_EVMWHSSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHSSFA, PPC_INS_EVMWHSSFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHUMI, PPC_INS_EVMWHUMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWHUMIA, PPC_INS_EVMWHUMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLSMIAAW, PPC_INS_EVMWLSMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLSMIANW, PPC_INS_EVMWLSMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLSSIAAW, PPC_INS_EVMWLSSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLSSIANW, PPC_INS_EVMWLSSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUMI, PPC_INS_EVMWLUMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUMIA, PPC_INS_EVMWLUMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUMIAAW, PPC_INS_EVMWLUMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUMIANW, PPC_INS_EVMWLUMIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUSIAAW, PPC_INS_EVMWLUSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWLUSIANW, PPC_INS_EVMWLUSIANW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMF, PPC_INS_EVMWSMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMFA, PPC_INS_EVMWSMFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMFAA, PPC_INS_EVMWSMFAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMFAN, PPC_INS_EVMWSMFAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMI, PPC_INS_EVMWSMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMIA, PPC_INS_EVMWSMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMIAA, PPC_INS_EVMWSMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSMIAN, PPC_INS_EVMWSMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSSF, PPC_INS_EVMWSSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSSFA, PPC_INS_EVMWSSFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSSFAA, PPC_INS_EVMWSSFAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWSSFAN, PPC_INS_EVMWSSFAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWUMI, PPC_INS_EVMWUMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWUMIA, PPC_INS_EVMWUMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWUMIAA, PPC_INS_EVMWUMIAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVMWUMIAN, PPC_INS_EVMWUMIAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVNAND, PPC_INS_EVNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVNEG, PPC_INS_EVNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVNOR, PPC_INS_EVNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVOR, PPC_INS_EVOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVORC, PPC_INS_EVORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVRLW, PPC_INS_EVRLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVRLWI, PPC_INS_EVRLWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVRNDW, PPC_INS_EVRNDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSLW, PPC_INS_EVSLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSLWI, PPC_INS_EVSLWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSPLATFI, PPC_INS_EVSPLATFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSPLATI, PPC_INS_EVSPLATI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSRWIS, PPC_INS_EVSRWIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSRWIU, PPC_INS_EVSRWIU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSRWS, PPC_INS_EVSRWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSRWU, PPC_INS_EVSRWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDD, PPC_INS_EVSTDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDDX, PPC_INS_EVSTDDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDH, PPC_INS_EVSTDH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDHX, PPC_INS_EVSTDHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDW, PPC_INS_EVSTDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTDWX, PPC_INS_EVSTDWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWHE, PPC_INS_EVSTWHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWHEX, PPC_INS_EVSTWHEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWHO, PPC_INS_EVSTWHO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWHOX, PPC_INS_EVSTWHOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWWE, PPC_INS_EVSTWWE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWWEX, PPC_INS_EVSTWWEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWWO, PPC_INS_EVSTWWO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSTWWOX, PPC_INS_EVSTWWOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBFSMIAAW, PPC_INS_EVSUBFSMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBFSSIAAW, PPC_INS_EVSUBFSSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBFUMIAAW, PPC_INS_EVSUBFUMIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBFUSIAAW, PPC_INS_EVSUBFUSIAAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBFW, PPC_INS_EVSUBFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVSUBIFW, PPC_INS_EVSUBIFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EVXOR, PPC_INS_EVXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSB, PPC_INS_EXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSB8, PPC_INS_EXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSB8_32_64, PPC_INS_EXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSB8o, PPC_INS_EXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSBo, PPC_INS_EXTSB, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSH, PPC_INS_EXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSH8, PPC_INS_EXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSH8_32_64, PPC_INS_EXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSH8o, PPC_INS_EXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSHo, PPC_INS_EXTSH, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSW, PPC_INS_EXTSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSW_32_64, PPC_INS_EXTSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSW_32_64o, PPC_INS_EXTSW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EXTSWo, PPC_INS_EXTSW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_EnforceIEIO, PPC_INS_EIEIO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FABSD, PPC_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FABSDo, PPC_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FABSS, PPC_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FABSSo, PPC_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FADD, PPC_INS_FADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FADDS, PPC_INS_FADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FADDSo, PPC_INS_FADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FADDo, PPC_INS_FADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFID, PPC_INS_FCFID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDS, PPC_INS_FCFIDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDSo, PPC_INS_FCFIDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDU, PPC_INS_FCFIDU, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDUS, PPC_INS_FCFIDUS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDUSo, PPC_INS_FCFIDUS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDUo, PPC_INS_FCFIDU, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCFIDo, PPC_INS_FCFID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCMPUD, PPC_INS_FCMPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCMPUS, PPC_INS_FCMPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCPSGND, PPC_INS_FCPSGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCPSGNDo, PPC_INS_FCPSGN, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCPSGNS, PPC_INS_FCPSGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCPSGNSo, PPC_INS_FCPSGN, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTID, PPC_INS_FCTID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIDUZ, PPC_INS_FCTIDUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIDUZo, PPC_INS_FCTIDUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIDZ, PPC_INS_FCTIDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIDZo, PPC_INS_FCTIDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIDo, PPC_INS_FCTID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIW, PPC_INS_FCTIW, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIWUZ, PPC_INS_FCTIWUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIWUZo, PPC_INS_FCTIWUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIWZ, PPC_INS_FCTIWZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIWZo, PPC_INS_FCTIWZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FCTIWo, PPC_INS_FCTIW, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FDIV, PPC_INS_FDIV, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FDIVS, PPC_INS_FDIVS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FDIVSo, PPC_INS_FDIVS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FDIVo, PPC_INS_FDIV, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMADD, PPC_INS_FMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMADDS, PPC_INS_FMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMADDSo, PPC_INS_FMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMADDo, PPC_INS_FMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMR, PPC_INS_FMR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMRo, PPC_INS_FMR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMSUB, PPC_INS_FMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMSUBS, PPC_INS_FMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMSUBSo, PPC_INS_FMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMSUBo, PPC_INS_FMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMUL, PPC_INS_FMUL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMULS, PPC_INS_FMULS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMULSo, PPC_INS_FMULS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FMULo, PPC_INS_FMUL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNABSD, PPC_INS_FNABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNABSDo, PPC_INS_FNABS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNABSS, PPC_INS_FNABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNABSSo, PPC_INS_FNABS, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNEGD, PPC_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNEGDo, PPC_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNEGS, PPC_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNEGSo, PPC_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMADD, PPC_INS_FNMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMADDS, PPC_INS_FNMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMADDSo, PPC_INS_FNMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMADDo, PPC_INS_FNMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMSUB, PPC_INS_FNMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMSUBS, PPC_INS_FNMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMSUBSo, PPC_INS_FNMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FNMSUBo, PPC_INS_FNMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRE, PPC_INS_FRE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRES, PPC_INS_FRES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRESo, PPC_INS_FRES, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FREo, PPC_INS_FRE, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIMD, PPC_INS_FRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIMDo, PPC_INS_FRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIMS, PPC_INS_FRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIMSo, PPC_INS_FRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIND, PPC_INS_FRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRINDo, PPC_INS_FRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRINS, PPC_INS_FRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRINSo, PPC_INS_FRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIPD, PPC_INS_FRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIPDo, PPC_INS_FRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIPS, PPC_INS_FRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIPSo, PPC_INS_FRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIZD, PPC_INS_FRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIZDo, PPC_INS_FRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIZS, PPC_INS_FRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRIZSo, PPC_INS_FRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSP, PPC_INS_FRSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSPo, PPC_INS_FRSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSQRTE, PPC_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSQRTES, PPC_INS_FRSQRTES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSQRTESo, PPC_INS_FRSQRTES, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FRSQRTEo, PPC_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSELD, PPC_INS_FSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSELDo, PPC_INS_FSEL, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSELS, PPC_INS_FSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSELSo, PPC_INS_FSEL, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSQRT, PPC_INS_FSQRT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSQRTS, PPC_INS_FSQRTS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSQRTSo, PPC_INS_FSQRTS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSQRTo, PPC_INS_FSQRT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSUB, PPC_INS_FSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSUBS, PPC_INS_FSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSUBSo, PPC_INS_FSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_FSUBo, PPC_INS_FSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ICBI, PPC_INS_ICBI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ICBT, PPC_INS_ICBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ICBT, 0 }, 0, 0 +#endif +}, +{ + PPC_ICCCI, PPC_INS_ICCCI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_ISEL, PPC_INS_ISEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ISEL8, PPC_INS_ISEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ISYNC, PPC_INS_ISYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LA, PPC_INS_LA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZ, PPC_INS_LBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZ8, PPC_INS_LBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZCIX, PPC_INS_LBZCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZU, PPC_INS_LBZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZU8, PPC_INS_LBZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZUX, PPC_INS_LBZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZUX8, PPC_INS_LBZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZX, PPC_INS_LBZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LBZX8, PPC_INS_LBZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LD, PPC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDARX, PPC_INS_LDARX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDBRX, PPC_INS_LDBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDCIX, PPC_INS_LDCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDU, PPC_INS_LDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDUX, PPC_INS_LDUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LDX, PPC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFD, PPC_INS_LFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFDU, PPC_INS_LFDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFDUX, PPC_INS_LFDUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFDX, PPC_INS_LFDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFIWAX, PPC_INS_LFIWAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFIWZX, PPC_INS_LFIWZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFS, PPC_INS_LFS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFSU, PPC_INS_LFSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFSUX, PPC_INS_LFSUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LFSX, PPC_INS_LFSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHA, PPC_INS_LHA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHA8, PPC_INS_LHA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAU, PPC_INS_LHAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAU8, PPC_INS_LHAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAUX, PPC_INS_LHAUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAUX8, PPC_INS_LHAUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAX, PPC_INS_LHAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHAX8, PPC_INS_LHAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHBRX, PPC_INS_LHBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHBRX8, PPC_INS_LHBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZ, PPC_INS_LHZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZ8, PPC_INS_LHZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZCIX, PPC_INS_LHZCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZU, PPC_INS_LHZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZU8, PPC_INS_LHZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZUX, PPC_INS_LHZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZUX8, PPC_INS_LHZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZX, PPC_INS_LHZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LHZX8, PPC_INS_LHZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LI, PPC_INS_LI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LI8, PPC_INS_LI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LIS, PPC_INS_LIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LIS8, PPC_INS_LIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LMW, PPC_INS_LMW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LSWI, PPC_INS_LSWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LVEBX, PPC_INS_LVEBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVEHX, PPC_INS_LVEHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVEWX, PPC_INS_LVEWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVSL, PPC_INS_LVSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVSR, PPC_INS_LVSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVX, PPC_INS_LVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LVXL, PPC_INS_LVXL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_LWA, PPC_INS_LWA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWARX, PPC_INS_LWARX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWAUX, PPC_INS_LWAUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWAX, PPC_INS_LWAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWAX_32, PPC_INS_LWAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWA_32, PPC_INS_LWA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWBRX, PPC_INS_LWBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWBRX8, PPC_INS_LWBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZ, PPC_INS_LWZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZ8, PPC_INS_LWZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZCIX, PPC_INS_LWZCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZU, PPC_INS_LWZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZU8, PPC_INS_LWZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZUX, PPC_INS_LWZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZUX8, PPC_INS_LWZUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZX, PPC_INS_LWZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LWZX8, PPC_INS_LWZX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_LXSDX, PPC_INS_LXSDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_LXVD2X, PPC_INS_LXVD2X, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_LXVDSX, PPC_INS_LXVDSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_LXVW4X, PPC_INS_LXVW4X, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_MBAR, PPC_INS_MBAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_MCRF, PPC_INS_MCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MCRFS, PPC_INS_MCRFS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFCR, PPC_INS_MFCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFCR8, PPC_INS_MFCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFCTR, PPC_INS_MFCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFCTR8, PPC_INS_MFCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFDCR, PPC_INS_MFDCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_MFFS, PPC_INS_MFFS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFFSo, PPC_INS_MFFS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFLR, PPC_INS_MFLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFLR8, PPC_INS_MFLR, +#ifndef CAPSTONE_DIET + { PPC_REG_LR8, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFMSR, PPC_INS_MFMSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFOCRF, PPC_INS_MFOCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFOCRF8, PPC_INS_MFOCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFSPR, PPC_INS_MFSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFSR, PPC_INS_MFSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFSRIN, PPC_INS_MFSRIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFTB, PPC_INS_MFTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFTB8, PPC_INS_MFSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFVRSAVE, PPC_INS_MFSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFVRSAVEv, PPC_INS_MFSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MFVSCR, PPC_INS_MFVSCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_MSYNC, PPC_INS_MSYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCRF, PPC_INS_MTCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCRF8, PPC_INS_MTCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCTR, PPC_INS_MTCTR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCTR8, PPC_INS_MTCTR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCTR8loop, PPC_INS_MTCTR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTCTRloop, PPC_INS_MTCTR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTDCR, PPC_INS_MTDCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSB0, PPC_INS_MTFSB0, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSB1, PPC_INS_MTFSB1, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSF, PPC_INS_MTFSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSFI, PPC_INS_MTFSFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSFIo, PPC_INS_MTFSFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSFb, PPC_INS_MTFSF, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTFSFo, PPC_INS_MTFSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTLR, PPC_INS_MTLR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTLR8, PPC_INS_MTLR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTMSR, PPC_INS_MTMSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTMSRD, PPC_INS_MTMSRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTOCRF, PPC_INS_MTOCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTOCRF8, PPC_INS_MTOCRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTSPR, PPC_INS_MTSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTSR, PPC_INS_MTSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTSRIN, PPC_INS_MTSRIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTVRSAVE, PPC_INS_MTSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTVRSAVEv, PPC_INS_MTSPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MTVSCR, PPC_INS_MTVSCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_MULHD, PPC_INS_MULHD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHDU, PPC_INS_MULHDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHDUo, PPC_INS_MULHDU, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHDo, PPC_INS_MULHD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHW, PPC_INS_MULHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHWU, PPC_INS_MULHWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHWUo, PPC_INS_MULHWU, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULHWo, PPC_INS_MULHW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLD, PPC_INS_MULLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLDo, PPC_INS_MULLD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLI, PPC_INS_MULLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLI8, PPC_INS_MULLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLW, PPC_INS_MULLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_MULLWo, PPC_INS_MULLW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NAND, PPC_INS_NAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NAND8, PPC_INS_NAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NAND8o, PPC_INS_NAND, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NANDo, PPC_INS_NAND, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NEG, PPC_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NEG8, PPC_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NEG8o, PPC_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NEGo, PPC_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOP, PPC_INS_NOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOP_GT_PWR6, PPC_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOP_GT_PWR7, PPC_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOR, PPC_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOR8, PPC_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NOR8o, PPC_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_NORo, PPC_INS_NOR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_OR, PPC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_OR8, PPC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_OR8o, PPC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORC, PPC_INS_ORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORC8, PPC_INS_ORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORC8o, PPC_INS_ORC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORCo, PPC_INS_ORC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORI, PPC_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORI8, PPC_INS_ORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORIS, PPC_INS_ORIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORIS8, PPC_INS_ORIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_ORo, PPC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_POPCNTD, PPC_INS_POPCNTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_POPCNTW, PPC_INS_POPCNTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_QVALIGNI, PPC_INS_QVALIGNI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVALIGNIb, PPC_INS_QVALIGNI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVALIGNIs, PPC_INS_QVALIGNI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVESPLATI, PPC_INS_QVESPLATI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVESPLATIb, PPC_INS_QVESPLATI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVESPLATIs, PPC_INS_QVESPLATI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFABS, PPC_INS_QVFABS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFABSs, PPC_INS_QVFABS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFADD, PPC_INS_QVFADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFADDS, PPC_INS_QVFADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFADDSs, PPC_INS_QVFADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCFID, PPC_INS_QVFCFID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCFIDS, PPC_INS_QVFCFIDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCFIDU, PPC_INS_QVFCFIDU, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCFIDUS, PPC_INS_QVFCFIDUS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCFIDb, PPC_INS_QVFCFID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPEQ, PPC_INS_QVFCMPEQ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPEQb, PPC_INS_QVFCMPEQ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPEQbs, PPC_INS_QVFCMPEQ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPGT, PPC_INS_QVFCMPGT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPGTb, PPC_INS_QVFCMPGT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPGTbs, PPC_INS_QVFCMPGT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPLT, PPC_INS_QVFCMPLT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPLTb, PPC_INS_QVFCMPLT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCMPLTbs, PPC_INS_QVFCMPLT, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCPSGN, PPC_INS_QVFCPSGN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCPSGNs, PPC_INS_QVFCPSGN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTID, PPC_INS_QVFCTID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIDU, PPC_INS_QVFCTIDU, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIDUZ, PPC_INS_QVFCTIDUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIDZ, PPC_INS_QVFCTIDZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIDb, PPC_INS_QVFCTID, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIW, PPC_INS_QVFCTIW, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIWU, PPC_INS_QVFCTIWU, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIWUZ, PPC_INS_QVFCTIWUZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFCTIWZ, PPC_INS_QVFCTIWZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFLOGICAL, PPC_INS_QVFLOGICAL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFLOGICALb, PPC_INS_QVFLOGICAL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFLOGICALs, PPC_INS_QVFLOGICAL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMADD, PPC_INS_QVFMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMADDS, PPC_INS_QVFMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMADDSs, PPC_INS_QVFMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMR, PPC_INS_QVFMR, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMRb, PPC_INS_QVFMR, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMRs, PPC_INS_QVFMR, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMSUB, PPC_INS_QVFMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMSUBS, PPC_INS_QVFMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMSUBSs, PPC_INS_QVFMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMUL, PPC_INS_QVFMUL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMULS, PPC_INS_QVFMULS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFMULSs, PPC_INS_QVFMULS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNABS, PPC_INS_QVFNABS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNABSs, PPC_INS_QVFNABS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNEG, PPC_INS_QVFNEG, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNEGs, PPC_INS_QVFNEG, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMADD, PPC_INS_QVFNMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMADDS, PPC_INS_QVFNMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMADDSs, PPC_INS_QVFNMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMSUB, PPC_INS_QVFNMSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMSUBS, PPC_INS_QVFNMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFNMSUBSs, PPC_INS_QVFNMSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFPERM, PPC_INS_QVFPERM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFPERMs, PPC_INS_QVFPERM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRE, PPC_INS_QVFRE, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRES, PPC_INS_QVFRES, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRESs, PPC_INS_QVFRES, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIM, PPC_INS_QVFRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIMs, PPC_INS_QVFRIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIN, PPC_INS_QVFRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRINs, PPC_INS_QVFRIN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIP, PPC_INS_QVFRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIPs, PPC_INS_QVFRIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIZ, PPC_INS_QVFRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRIZs, PPC_INS_QVFRIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRSP, PPC_INS_QVFRSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRSPs, PPC_INS_QVFRSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRSQRTE, PPC_INS_QVFRSQRTE, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRSQRTES, PPC_INS_QVFRSQRTES, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFRSQRTESs, PPC_INS_QVFRSQRTES, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSEL, PPC_INS_QVFSEL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSELb, PPC_INS_QVFSEL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSELbb, PPC_INS_QVFSEL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSELbs, PPC_INS_QVFSEL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSUB, PPC_INS_QVFSUB, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSUBS, PPC_INS_QVFSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFSUBSs, PPC_INS_QVFSUBS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFTSTNAN, PPC_INS_QVFTSTNAN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFTSTNANb, PPC_INS_QVFTSTNAN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFTSTNANbs, PPC_INS_QVFTSTNAN, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXMADD, PPC_INS_QVFXMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXMADDS, PPC_INS_QVFXMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXMUL, PPC_INS_QVFXMUL, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXMULS, PPC_INS_QVFXMULS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXCPNMADD, PPC_INS_QVFXXCPNMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXCPNMADDS, PPC_INS_QVFXXCPNMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXMADD, PPC_INS_QVFXXMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXMADDS, PPC_INS_QVFXXMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXNPMADD, PPC_INS_QVFXXNPMADD, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVFXXNPMADDS, PPC_INS_QVFXXNPMADDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVGPCI, PPC_INS_QVGPCI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCDUX, PPC_INS_QVLFCDUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCDUXA, PPC_INS_QVLFCDUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCDX, PPC_INS_QVLFCDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCDXA, PPC_INS_QVLFCDXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCSUX, PPC_INS_QVLFCSUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCSUXA, PPC_INS_QVLFCSUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCSX, PPC_INS_QVLFCSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCSXA, PPC_INS_QVLFCSXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFCSXs, PPC_INS_QVLFCSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFDUX, PPC_INS_QVLFDUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFDUXA, PPC_INS_QVLFDUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFDX, PPC_INS_QVLFDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFDXA, PPC_INS_QVLFDXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFDXb, PPC_INS_QVLFDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFIWAX, PPC_INS_QVLFIWAX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFIWAXA, PPC_INS_QVLFIWAXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFIWZX, PPC_INS_QVLFIWZX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFIWZXA, PPC_INS_QVLFIWZXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSUX, PPC_INS_QVLFSUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSUXA, PPC_INS_QVLFSUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSX, PPC_INS_QVLFSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSXA, PPC_INS_QVLFSXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSXb, PPC_INS_QVLFSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLFSXs, PPC_INS_QVLFSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLPCLDX, PPC_INS_QVLPCLDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLPCLSX, PPC_INS_QVLPCLSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLPCLSXint, PPC_INS_QVLPCLSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLPCRDX, PPC_INS_QVLPCRDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVLPCRSX, PPC_INS_QVLPCRSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDUX, PPC_INS_QVSTFCDUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDUXA, PPC_INS_QVSTFCDUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDUXI, PPC_INS_QVSTFCDUXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDUXIA, PPC_INS_QVSTFCDUXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDX, PPC_INS_QVSTFCDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDXA, PPC_INS_QVSTFCDXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDXI, PPC_INS_QVSTFCDXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCDXIA, PPC_INS_QVSTFCDXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSUX, PPC_INS_QVSTFCSUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSUXA, PPC_INS_QVSTFCSUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSUXI, PPC_INS_QVSTFCSUXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSUXIA, PPC_INS_QVSTFCSUXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSX, PPC_INS_QVSTFCSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSXA, PPC_INS_QVSTFCSXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSXI, PPC_INS_QVSTFCSXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSXIA, PPC_INS_QVSTFCSXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFCSXs, PPC_INS_QVSTFCSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDUX, PPC_INS_QVSTFDUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDUXA, PPC_INS_QVSTFDUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDUXI, PPC_INS_QVSTFDUXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDUXIA, PPC_INS_QVSTFDUXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDX, PPC_INS_QVSTFDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDXA, PPC_INS_QVSTFDXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDXI, PPC_INS_QVSTFDXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDXIA, PPC_INS_QVSTFDXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFDXb, PPC_INS_QVSTFDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFIWX, PPC_INS_QVSTFIWX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFIWXA, PPC_INS_QVSTFIWXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSUX, PPC_INS_QVSTFSUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSUXA, PPC_INS_QVSTFSUXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSUXI, PPC_INS_QVSTFSUXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSUXIA, PPC_INS_QVSTFSUXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSUXs, PPC_INS_QVSTFSUX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSX, PPC_INS_QVSTFSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSXA, PPC_INS_QVSTFSXA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSXI, PPC_INS_QVSTFSXI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSXIA, PPC_INS_QVSTFSXIA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_QVSTFSXs, PPC_INS_QVSTFSX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 +#endif +}, +{ + PPC_RFCI, PPC_INS_RFCI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_RFDI, PPC_INS_RFDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 +#endif +}, +{ + PPC_RFI, PPC_INS_RFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_RFID, PPC_INS_RFID, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RFMCI, PPC_INS_RFMCI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 +#endif +}, +{ + PPC_RLDCL, PPC_INS_RLDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDCLo, PPC_INS_RLDCL, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDCR, PPC_INS_RLDCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDCRo, PPC_INS_RLDCR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDIC, PPC_INS_RLDIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICL, PPC_INS_RLDICL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICL_32_64, PPC_INS_RLDICL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICLo, PPC_INS_RLDICL, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICR, PPC_INS_RLDICR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICRo, PPC_INS_RLDICR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDICo, PPC_INS_RLDIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDIMI, PPC_INS_RLDIMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLDIMIo, PPC_INS_RLDIMI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWIMI, PPC_INS_RLWIMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWIMI8, PPC_INS_RLWIMI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWIMI8o, PPC_INS_RLWIMI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWIMIo, PPC_INS_RLWIMI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWINM, PPC_INS_RLWINM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWINM8, PPC_INS_RLWINM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWINM8o, PPC_INS_RLWINM, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWINMo, PPC_INS_RLWINM, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWNM, PPC_INS_RLWNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWNM8, PPC_INS_RLWNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWNM8o, PPC_INS_RLWNM, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_RLWNMo, PPC_INS_RLWNM, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SC, PPC_INS_SC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLBIA, PPC_INS_SLBIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLBIE, PPC_INS_SLBIE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLBMFEE, PPC_INS_SLBMFEE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLBMTE, PPC_INS_SLBMTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLD, PPC_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLDo, PPC_INS_SLD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLW, PPC_INS_SLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLW8, PPC_INS_SLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLW8o, PPC_INS_SLW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SLWo, PPC_INS_SLW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRAD, PPC_INS_SRAD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRADI, PPC_INS_SRADI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRADIo, PPC_INS_SRADI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRADo, PPC_INS_SRAD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRAW, PPC_INS_SRAW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRAWI, PPC_INS_SRAWI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRAWIo, PPC_INS_SRAWI, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRAWo, PPC_INS_SRAW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRD, PPC_INS_SRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRDo, PPC_INS_SRD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRW, PPC_INS_SRW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRW8, PPC_INS_SRW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRW8o, PPC_INS_SRW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SRWo, PPC_INS_SRW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STB, PPC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STB8, PPC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBCIX, PPC_INS_STBCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBU, PPC_INS_STBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBU8, PPC_INS_STBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBUX, PPC_INS_STBUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBUX8, PPC_INS_STBUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBX, PPC_INS_STBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STBX8, PPC_INS_STBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STD, PPC_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDBRX, PPC_INS_STDBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDCIX, PPC_INS_STDCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDCX, PPC_INS_STDCX, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDU, PPC_INS_STDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDUX, PPC_INS_STDUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STDX, PPC_INS_STDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFD, PPC_INS_STFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFDU, PPC_INS_STFDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFDUX, PPC_INS_STFDUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFDX, PPC_INS_STFDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFIWX, PPC_INS_STFIWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFS, PPC_INS_STFS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFSU, PPC_INS_STFSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFSUX, PPC_INS_STFSUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STFSX, PPC_INS_STFSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STH, PPC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STH8, PPC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHBRX, PPC_INS_STHBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHCIX, PPC_INS_STHCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHU, PPC_INS_STHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHU8, PPC_INS_STHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHUX, PPC_INS_STHUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHUX8, PPC_INS_STHUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHX, PPC_INS_STHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STHX8, PPC_INS_STHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STMW, PPC_INS_STMW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STSWI, PPC_INS_STSWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STVEBX, PPC_INS_STVEBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_STVEHX, PPC_INS_STVEHX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_STVEWX, PPC_INS_STVEWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_STVX, PPC_INS_STVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_STVXL, PPC_INS_STVXL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_STW, PPC_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STW8, PPC_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWBRX, PPC_INS_STWBRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWCIX, PPC_INS_STWCIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWCX, PPC_INS_STWCX, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWU, PPC_INS_STWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWU8, PPC_INS_STWU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWUX, PPC_INS_STWUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWUX8, PPC_INS_STWUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWX, PPC_INS_STWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STWX8, PPC_INS_STWX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_STXSDX, PPC_INS_STXSDX, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_STXVD2X, PPC_INS_STXVD2X, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_STXVW4X, PPC_INS_STXVW4X, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_SUBF, PPC_INS_SUBF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBF8, PPC_INS_SUBF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBF8o, PPC_INS_SUBF, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFC, PPC_INS_SUBFC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFC8, PPC_INS_SUBFC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFC8o, PPC_INS_SUBFC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFCo, PPC_INS_SUBFC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFE, PPC_INS_SUBFE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFE8, PPC_INS_SUBFE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFE8o, PPC_INS_SUBFE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFEo, PPC_INS_SUBFE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFIC, PPC_INS_SUBFIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFIC8, PPC_INS_SUBFIC, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFME, PPC_INS_SUBFME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFME8, PPC_INS_SUBFME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFME8o, PPC_INS_SUBFME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFMEo, PPC_INS_SUBFME, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFZE, PPC_INS_SUBFZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFZE8, PPC_INS_SUBFZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFZE8o, PPC_INS_SUBFZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFZEo, PPC_INS_SUBFZE, +#ifndef CAPSTONE_DIET + { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SUBFo, PPC_INS_SUBF, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_SYNC, PPC_INS_SYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TAILB, PPC_INS_B, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_TAILB8, PPC_INS_B, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_TAILBA, PPC_INS_BA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_TAILBA8, PPC_INS_BA, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + PPC_TAILBCTR, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 1 +#endif +}, +{ + PPC_TAILBCTR8, PPC_INS_BCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 +#endif +}, +{ + PPC_TD, PPC_INS_TD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TDI, PPC_INS_TDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TLBIA, PPC_INS_TLBIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TLBIE, PPC_INS_TLBIE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TLBIEL, PPC_INS_TLBIEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TLBIVAX, PPC_INS_TLBIVAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBLD, PPC_INS_TLBLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBLI, PPC_INS_TLBLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBRE, PPC_INS_TLBRE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBRE2, PPC_INS_TLBRE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBSX, PPC_INS_TLBSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBSX2, PPC_INS_TLBSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBSX2D, PPC_INS_TLBSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBSYNC, PPC_INS_TLBSYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TLBWE, PPC_INS_TLBWE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_TLBWE2, PPC_INS_TLBWE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 +#endif +}, +{ + PPC_TRAP, PPC_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TW, PPC_INS_TW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_TWI, PPC_INS_TWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_VADDCUW, PPC_INS_VADDCUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDFP, PPC_INS_VADDFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDSBS, PPC_INS_VADDSBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDSHS, PPC_INS_VADDSHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDSWS, PPC_INS_VADDSWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUBM, PPC_INS_VADDUBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUBS, PPC_INS_VADDUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUDM, PPC_INS_VADDUDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUHM, PPC_INS_VADDUHM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUHS, PPC_INS_VADDUHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUWM, PPC_INS_VADDUWM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VADDUWS, PPC_INS_VADDUWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAND, PPC_INS_VAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VANDC, PPC_INS_VANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGSB, PPC_INS_VAVGSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGSH, PPC_INS_VAVGSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGSW, PPC_INS_VAVGSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGUB, PPC_INS_VAVGUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGUH, PPC_INS_VAVGUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VAVGUW, PPC_INS_VAVGUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCFSX, PPC_INS_VCFSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCFSX_0, PPC_INS_VCFSX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCFUX, PPC_INS_VCFUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCFUX_0, PPC_INS_VCFUX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCLZB, PPC_INS_VCLZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCLZD, PPC_INS_VCLZD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCLZH, PPC_INS_VCLZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCLZW, PPC_INS_VCLZW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPBFP, PPC_INS_VCMPBFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPBFPo, PPC_INS_VCMPBFP, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQFP, PPC_INS_VCMPEQFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQFPo, PPC_INS_VCMPEQFP, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUB, PPC_INS_VCMPEQUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUBo, PPC_INS_VCMPEQUB, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUD, PPC_INS_VCMPEQUD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUDo, PPC_INS_VCMPEQUD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUH, PPC_INS_VCMPEQUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUHo, PPC_INS_VCMPEQUH, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUW, PPC_INS_VCMPEQUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPEQUWo, PPC_INS_VCMPEQUW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGEFP, PPC_INS_VCMPGEFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGEFPo, PPC_INS_VCMPGEFP, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTFP, PPC_INS_VCMPGTFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTFPo, PPC_INS_VCMPGTFP, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSB, PPC_INS_VCMPGTSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSBo, PPC_INS_VCMPGTSB, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSD, PPC_INS_VCMPGTSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSDo, PPC_INS_VCMPGTSD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSH, PPC_INS_VCMPGTSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSHo, PPC_INS_VCMPGTSH, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSW, PPC_INS_VCMPGTSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTSWo, PPC_INS_VCMPGTSW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUB, PPC_INS_VCMPGTUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUBo, PPC_INS_VCMPGTUB, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUD, PPC_INS_VCMPGTUD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUDo, PPC_INS_VCMPGTUD, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUH, PPC_INS_VCMPGTUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUHo, PPC_INS_VCMPGTUH, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUW, PPC_INS_VCMPGTUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCMPGTUWo, PPC_INS_VCMPGTUW, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCTSXS, PPC_INS_VCTSXS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCTSXS_0, PPC_INS_VCTSXS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCTUXS, PPC_INS_VCTUXS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VCTUXS_0, PPC_INS_VCTUXS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VEQV, PPC_INS_VEQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VEXPTEFP, PPC_INS_VEXPTEFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VLOGEFP, PPC_INS_VLOGEFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMADDFP, PPC_INS_VMADDFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXFP, PPC_INS_VMAXFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXSB, PPC_INS_VMAXSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXSD, PPC_INS_VMAXSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXSH, PPC_INS_VMAXSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXSW, PPC_INS_VMAXSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXUB, PPC_INS_VMAXUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXUD, PPC_INS_VMAXUD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXUH, PPC_INS_VMAXUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMAXUW, PPC_INS_VMAXUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMHADDSHS, PPC_INS_VMHADDSHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMHRADDSHS, PPC_INS_VMHRADDSHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMIDUD, PPC_INS_VMINUD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINFP, PPC_INS_VMINFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINSB, PPC_INS_VMINSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINSD, PPC_INS_VMINSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINSH, PPC_INS_VMINSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINSW, PPC_INS_VMINSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINUB, PPC_INS_VMINUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINUH, PPC_INS_VMINUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMINUW, PPC_INS_VMINUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMLADDUHM, PPC_INS_VMLADDUHM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGHB, PPC_INS_VMRGHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGHH, PPC_INS_VMRGHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGHW, PPC_INS_VMRGHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGLB, PPC_INS_VMRGLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGLH, PPC_INS_VMRGLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMRGLW, PPC_INS_VMRGLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMMBM, PPC_INS_VMSUMMBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMSHM, PPC_INS_VMSUMSHM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMSHS, PPC_INS_VMSUMSHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMUBM, PPC_INS_VMSUMUBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMUHM, PPC_INS_VMSUMUHM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMSUMUHS, PPC_INS_VMSUMUHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULESB, PPC_INS_VMULESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULESH, PPC_INS_VMULESH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULESW, PPC_INS_VMULESW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULEUB, PPC_INS_VMULEUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULEUH, PPC_INS_VMULEUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULEUW, PPC_INS_VMULEUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOSB, PPC_INS_VMULOSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOSH, PPC_INS_VMULOSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOSW, PPC_INS_VMULOSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOUB, PPC_INS_VMULOUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOUH, PPC_INS_VMULOUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULOUW, PPC_INS_VMULOUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VMULUWM, PPC_INS_VMULUWM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VNAND, PPC_INS_VNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VNMSUBFP, PPC_INS_VNMSUBFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VNOR, PPC_INS_VNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VOR, PPC_INS_VOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VORC, PPC_INS_VORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPERM, PPC_INS_VPERM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKPX, PPC_INS_VPKPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKSHSS, PPC_INS_VPKSHSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKSHUS, PPC_INS_VPKSHUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKSWSS, PPC_INS_VPKSWSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKSWUS, PPC_INS_VPKSWUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKUHUM, PPC_INS_VPKUHUM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKUHUS, PPC_INS_VPKUHUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKUWUM, PPC_INS_VPKUWUM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPKUWUS, PPC_INS_VPKUWUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPOPCNTB, PPC_INS_VPOPCNTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPOPCNTD, PPC_INS_VPOPCNTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPOPCNTH, PPC_INS_VPOPCNTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VPOPCNTW, PPC_INS_VPOPCNTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VREFP, PPC_INS_VREFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRFIM, PPC_INS_VRFIM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRFIN, PPC_INS_VRFIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRFIP, PPC_INS_VRFIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRFIZ, PPC_INS_VRFIZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRLB, PPC_INS_VRLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRLD, PPC_INS_VRLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRLH, PPC_INS_VRLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRLW, PPC_INS_VRLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VRSQRTEFP, PPC_INS_VRSQRTEFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSEL, PPC_INS_VSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSL, PPC_INS_VSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLB, PPC_INS_VSLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLD, PPC_INS_VSLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLDOI, PPC_INS_VSLDOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLH, PPC_INS_VSLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLO, PPC_INS_VSLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSLW, PPC_INS_VSLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTB, PPC_INS_VSPLTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTH, PPC_INS_VSPLTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTISB, PPC_INS_VSPLTISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTISH, PPC_INS_VSPLTISH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTISW, PPC_INS_VSPLTISW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSPLTW, PPC_INS_VSPLTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSR, PPC_INS_VSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRAB, PPC_INS_VSRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRAD, PPC_INS_VSRAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRAH, PPC_INS_VSRAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRAW, PPC_INS_VSRAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRB, PPC_INS_VSRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRD, PPC_INS_VSRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRH, PPC_INS_VSRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRO, PPC_INS_VSRO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSRW, PPC_INS_VSRW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBCUW, PPC_INS_VSUBCUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBFP, PPC_INS_VSUBFP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBSBS, PPC_INS_VSUBSBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBSHS, PPC_INS_VSUBSHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBSWS, PPC_INS_VSUBSWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUBM, PPC_INS_VSUBUBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUBS, PPC_INS_VSUBUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUDM, PPC_INS_VSUBUDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUHM, PPC_INS_VSUBUHM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUHS, PPC_INS_VSUBUHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUWM, PPC_INS_VSUBUWM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUBUWS, PPC_INS_VSUBUWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUM2SWS, PPC_INS_VSUM2SWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUM4SBS, PPC_INS_VSUM4SBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUM4SHS, PPC_INS_VSUM4SHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUM4UBS, PPC_INS_VSUM4UBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VSUMSWS, PPC_INS_VSUMSWS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKHPX, PPC_INS_VUPKHPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKHSB, PPC_INS_VUPKHSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKHSH, PPC_INS_VUPKHSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKLPX, PPC_INS_VUPKLPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKLSB, PPC_INS_VUPKLSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VUPKLSH, PPC_INS_VUPKLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_VXOR, PPC_INS_VXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SET0, PPC_INS_VXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SET0B, PPC_INS_VXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SET0H, PPC_INS_VXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SETALLONES, PPC_INS_VSPLTISW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SETALLONESB, PPC_INS_VSPLTISW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_V_SETALLONESH, PPC_INS_VSPLTISW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 +#endif +}, +{ + PPC_WAIT, PPC_INS_WAIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_WRTEE, PPC_INS_WRTEE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_WRTEEI, PPC_INS_WRTEEI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 +#endif +}, +{ + PPC_XOR, PPC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XOR8, PPC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XOR8o, PPC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XORI, PPC_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XORI8, PPC_INS_XORI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XORIS, PPC_INS_XORIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XORIS8, PPC_INS_XORIS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XORo, PPC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_XSABSDP, PPC_INS_XSABSDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSADDDP, PPC_INS_XSADDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCMPODP, PPC_INS_XSCMPODP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCMPUDP, PPC_INS_XSCMPUDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCPSGNDP, PPC_INS_XSCPSGNDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVDPSP, PPC_INS_XSCVDPSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVDPSXDS, PPC_INS_XSCVDPSXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVDPSXWS, PPC_INS_XSCVDPSXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVDPUXDS, PPC_INS_XSCVDPUXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVDPUXWS, PPC_INS_XSCVDPUXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVSPDP, PPC_INS_XSCVSPDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVSXDDP, PPC_INS_XSCVSXDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSCVUXDDP, PPC_INS_XSCVUXDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSDIVDP, PPC_INS_XSDIVDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMADDADP, PPC_INS_XSMADDADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMADDMDP, PPC_INS_XSMADDMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMAXDP, PPC_INS_XSMAXDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMINDP, PPC_INS_XSMINDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMSUBADP, PPC_INS_XSMSUBADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMSUBMDP, PPC_INS_XSMSUBMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSMULDP, PPC_INS_XSMULDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNABSDP, PPC_INS_XSNABSDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNEGDP, PPC_INS_XSNEGDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNMADDADP, PPC_INS_XSNMADDADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNMADDMDP, PPC_INS_XSNMADDMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNMSUBADP, PPC_INS_XSNMSUBADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSNMSUBMDP, PPC_INS_XSNMSUBMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRDPI, PPC_INS_XSRDPI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRDPIC, PPC_INS_XSRDPIC, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRDPIM, PPC_INS_XSRDPIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRDPIP, PPC_INS_XSRDPIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRDPIZ, PPC_INS_XSRDPIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSREDP, PPC_INS_XSREDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSRSQRTEDP, PPC_INS_XSRSQRTEDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSSQRTDP, PPC_INS_XSSQRTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSSUBDP, PPC_INS_XSSUBDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSTDIVDP, PPC_INS_XSTDIVDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XSTSQRTDP, PPC_INS_XSTSQRTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVABSDP, PPC_INS_XVABSDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVABSSP, PPC_INS_XVABSSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVADDDP, PPC_INS_XVADDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVADDSP, PPC_INS_XVADDSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPEQDP, PPC_INS_XVCMPEQDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPEQDPo, PPC_INS_XVCMPEQDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPEQSP, PPC_INS_XVCMPEQSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPEQSPo, PPC_INS_XVCMPEQSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGEDP, PPC_INS_XVCMPGEDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGEDPo, PPC_INS_XVCMPGEDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGESP, PPC_INS_XVCMPGESP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGESPo, PPC_INS_XVCMPGESP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGTDP, PPC_INS_XVCMPGTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGTDPo, PPC_INS_XVCMPGTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGTSP, PPC_INS_XVCMPGTSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCMPGTSPo, PPC_INS_XVCMPGTSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCPSGNDP, PPC_INS_XVCPSGNDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCPSGNSP, PPC_INS_XVCPSGNSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVDPSP, PPC_INS_XVCVDPSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVDPSXDS, PPC_INS_XVCVDPSXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVDPSXWS, PPC_INS_XVCVDPSXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVDPUXDS, PPC_INS_XVCVDPUXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVDPUXWS, PPC_INS_XVCVDPUXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSPDP, PPC_INS_XVCVSPDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSPSXDS, PPC_INS_XVCVSPSXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSPSXWS, PPC_INS_XVCVSPSXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSPUXDS, PPC_INS_XVCVSPUXDS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSPUXWS, PPC_INS_XVCVSPUXWS, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSXDDP, PPC_INS_XVCVSXDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSXDSP, PPC_INS_XVCVSXDSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSXWDP, PPC_INS_XVCVSXWDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVSXWSP, PPC_INS_XVCVSXWSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVUXDDP, PPC_INS_XVCVUXDDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVUXDSP, PPC_INS_XVCVUXDSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVUXWDP, PPC_INS_XVCVUXWDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVCVUXWSP, PPC_INS_XVCVUXWSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVDIVDP, PPC_INS_XVDIVDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVDIVSP, PPC_INS_XVDIVSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMADDADP, PPC_INS_XVMADDADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMADDASP, PPC_INS_XVMADDASP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMADDMDP, PPC_INS_XVMADDMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMADDMSP, PPC_INS_XVMADDMSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMAXDP, PPC_INS_XVMAXDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMAXSP, PPC_INS_XVMAXSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMINDP, PPC_INS_XVMINDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMINSP, PPC_INS_XVMINSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMSUBADP, PPC_INS_XVMSUBADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMSUBASP, PPC_INS_XVMSUBASP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMSUBMDP, PPC_INS_XVMSUBMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMSUBMSP, PPC_INS_XVMSUBMSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMULDP, PPC_INS_XVMULDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVMULSP, PPC_INS_XVMULSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNABSDP, PPC_INS_XVNABSDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNABSSP, PPC_INS_XVNABSSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNEGDP, PPC_INS_XVNEGDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNEGSP, PPC_INS_XVNEGSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMADDADP, PPC_INS_XVNMADDADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMADDASP, PPC_INS_XVNMADDASP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMADDMDP, PPC_INS_XVNMADDMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMADDMSP, PPC_INS_XVNMADDMSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMSUBADP, PPC_INS_XVNMSUBADP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMSUBASP, PPC_INS_XVNMSUBASP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMSUBMDP, PPC_INS_XVNMSUBMDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVNMSUBMSP, PPC_INS_XVNMSUBMSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRDPI, PPC_INS_XVRDPI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRDPIC, PPC_INS_XVRDPIC, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRDPIM, PPC_INS_XVRDPIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRDPIP, PPC_INS_XVRDPIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRDPIZ, PPC_INS_XVRDPIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVREDP, PPC_INS_XVREDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRESP, PPC_INS_XVRESP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSPI, PPC_INS_XVRSPI, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSPIC, PPC_INS_XVRSPIC, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSPIM, PPC_INS_XVRSPIM, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSPIP, PPC_INS_XVRSPIP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSPIZ, PPC_INS_XVRSPIZ, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSQRTEDP, PPC_INS_XVRSQRTEDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVRSQRTESP, PPC_INS_XVRSQRTESP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVSQRTDP, PPC_INS_XVSQRTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVSQRTSP, PPC_INS_XVSQRTSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVSUBDP, PPC_INS_XVSUBDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVSUBSP, PPC_INS_XVSUBSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVTDIVDP, PPC_INS_XVTDIVDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVTDIVSP, PPC_INS_XVTDIVSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVTSQRTDP, PPC_INS_XVTSQRTDP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XVTSQRTSP, PPC_INS_XVTSQRTSP, +#ifndef CAPSTONE_DIET + { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLAND, PPC_INS_XXLAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLANDC, PPC_INS_XXLANDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLEQV, PPC_INS_XXLEQV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLNAND, PPC_INS_XXLNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLNOR, PPC_INS_XXLNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLOR, PPC_INS_XXLOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLORC, PPC_INS_XXLORC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLORf, PPC_INS_XXLOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXLXOR, PPC_INS_XXLXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXMRGHW, PPC_INS_XXMRGHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXMRGLW, PPC_INS_XXMRGLW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXPERMDI, PPC_INS_XXPERMDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXSEL, PPC_INS_XXSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXSLDWI, PPC_INS_XXSLDWI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_XXSPLTW, PPC_INS_XXSPLTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 +#endif +}, +{ + PPC_gBC, PPC_INS_BC, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCA, PPC_INS_BCA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCCTR, PPC_INS_BCCTR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCCTRL, PPC_INS_BCCTRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCL, PPC_INS_BCL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCLA, PPC_INS_BCLA, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCLR, PPC_INS_BCLR, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + PPC_gBCLRL, PPC_INS_BCLRL, +#ifndef CAPSTONE_DIET + { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.c b/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.c new file mode 100644 index 0000000..794b9a8 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.c @@ -0,0 +1,45 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_POWERPC + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "PPCDisassembler.h" +#include "PPCInstPrinter.h" +#include "PPCMapping.h" +#include "PPCModule.h" + +cs_err PPC_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri)); + + PPC_init(mri); + ud->printer = PPC_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = PPC_getInstruction; + ud->post_printer = PPC_post_printer; + + ud->reg_name = PPC_reg_name; + ud->insn_id = PPC_get_insn_id; + ud->insn_name = PPC_insn_name; + ud->group_name = PPC_group_name; + + return CS_ERR_OK; +} + +cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_SYNTAX) + handle->syntax = (int) value; + + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.h b/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.h new file mode 100644 index 0000000..079cf60 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_POWERPC_MODULE_H +#define CS_POWERPC_MODULE_H + +#include "../../utils.h" + +cs_err PPC_global_init(cs_struct *ud); +cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/PowerPC/PPCPredicates.h b/white_patch_detect/capstone-master/arch/PowerPC/PPCPredicates.h new file mode 100644 index 0000000..03d5566 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/PowerPC/PPCPredicates.h @@ -0,0 +1,62 @@ +//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the PowerPC branch predicates. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_POWERPC_PPCPREDICATES_H +#define CS_POWERPC_PPCPREDICATES_H + +#include "capstone/ppc.h" + +// NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM +typedef enum ppc_predicate { + PPC_PRED_LT = (0 << 5) | 12, + PPC_PRED_LE = (1 << 5) | 4, + PPC_PRED_EQ = (2 << 5) | 12, + PPC_PRED_GE = (0 << 5) | 4, + PPC_PRED_GT = (1 << 5) | 12, + PPC_PRED_NE = (2 << 5) | 4, + PPC_PRED_UN = (3 << 5) | 12, + PPC_PRED_NU = (3 << 5) | 4, + PPC_PRED_LT_MINUS = (0 << 5) | 14, + PPC_PRED_LE_MINUS = (1 << 5) | 6, + PPC_PRED_EQ_MINUS = (2 << 5) | 14, + PPC_PRED_GE_MINUS = (0 << 5) | 6, + PPC_PRED_GT_MINUS = (1 << 5) | 14, + PPC_PRED_NE_MINUS = (2 << 5) | 6, + PPC_PRED_UN_MINUS = (3 << 5) | 14, + PPC_PRED_NU_MINUS = (3 << 5) | 6, + PPC_PRED_LT_PLUS = (0 << 5) | 15, + PPC_PRED_LE_PLUS = (1 << 5) | 7, + PPC_PRED_EQ_PLUS = (2 << 5) | 15, + PPC_PRED_GE_PLUS = (0 << 5) | 7, + PPC_PRED_GT_PLUS = (1 << 5) | 15, + PPC_PRED_NE_PLUS = (2 << 5) | 7, + PPC_PRED_UN_PLUS = (3 << 5) | 15, + PPC_PRED_NU_PLUS = (3 << 5) | 7, + + // When dealing with individual condition-register bits, we have simple set + // and unset predicates. + PPC_PRED_BIT_SET = 1024, + PPC_PRED_BIT_UNSET = 1025 +} ppc_predicate; + +/// Invert the specified predicate. != -> ==, < -> >=. +ppc_predicate InvertPredicate(ppc_predicate Opcode); + +/// Assume the condition register is set by MI(a,b), return the predicate if +/// we modify the instructions such that condition register is set by MI(b,a). +ppc_predicate getSwappedPredicate(ppc_predicate Opcode); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/Sparc.h b/white_patch_detect/capstone-master/arch/Sparc/Sparc.h new file mode 100644 index 0000000..1f77362 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/Sparc.h @@ -0,0 +1,63 @@ +//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in the LLVM +// Sparc back-end. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SPARC_TARGET_SPARC_H +#define CS_SPARC_TARGET_SPARC_H + +#include "capstone/sparc.h" + +inline static const char *SPARCCondCodeToString(sparc_cc CC) +{ + switch (CC) { + default: return NULL; // unreachable + case SPARC_CC_ICC_A: return "a"; + case SPARC_CC_ICC_N: return "n"; + case SPARC_CC_ICC_NE: return "ne"; + case SPARC_CC_ICC_E: return "e"; + case SPARC_CC_ICC_G: return "g"; + case SPARC_CC_ICC_LE: return "le"; + case SPARC_CC_ICC_GE: return "ge"; + case SPARC_CC_ICC_L: return "l"; + case SPARC_CC_ICC_GU: return "gu"; + case SPARC_CC_ICC_LEU: return "leu"; + case SPARC_CC_ICC_CC: return "cc"; + case SPARC_CC_ICC_CS: return "cs"; + case SPARC_CC_ICC_POS: return "pos"; + case SPARC_CC_ICC_NEG: return "neg"; + case SPARC_CC_ICC_VC: return "vc"; + case SPARC_CC_ICC_VS: return "vs"; + + case SPARC_CC_FCC_A: return "a"; + case SPARC_CC_FCC_N: return "n"; + case SPARC_CC_FCC_U: return "u"; + case SPARC_CC_FCC_G: return "g"; + case SPARC_CC_FCC_UG: return "ug"; + case SPARC_CC_FCC_L: return "l"; + case SPARC_CC_FCC_UL: return "ul"; + case SPARC_CC_FCC_LG: return "lg"; + case SPARC_CC_FCC_NE: return "ne"; + case SPARC_CC_FCC_E: return "e"; + case SPARC_CC_FCC_UE: return "ue"; + case SPARC_CC_FCC_GE: return "ge"; + case SPARC_CC_FCC_UGE: return "uge"; + case SPARC_CC_FCC_LE: return "le"; + case SPARC_CC_FCC_ULE: return "ule"; + case SPARC_CC_FCC_O: return "o"; + } +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.c b/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.c new file mode 100644 index 0000000..3e6d0e0 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.c @@ -0,0 +1,500 @@ +//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SPARC + +#include // DEBUG +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "SparcDisassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" +static const unsigned IntRegDecoderTable[] = { + SP_G0, SP_G1, SP_G2, SP_G3, + SP_G4, SP_G5, SP_G6, SP_G7, + SP_O0, SP_O1, SP_O2, SP_O3, + SP_O4, SP_O5, SP_O6, SP_O7, + SP_L0, SP_L1, SP_L2, SP_L3, + SP_L4, SP_L5, SP_L6, SP_L7, + SP_I0, SP_I1, SP_I2, SP_I3, + SP_I4, SP_I5, SP_I6, SP_I7 +}; + +static const unsigned FPRegDecoderTable[] = { + SP_F0, SP_F1, SP_F2, SP_F3, + SP_F4, SP_F5, SP_F6, SP_F7, + SP_F8, SP_F9, SP_F10, SP_F11, + SP_F12, SP_F13, SP_F14, SP_F15, + SP_F16, SP_F17, SP_F18, SP_F19, + SP_F20, SP_F21, SP_F22, SP_F23, + SP_F24, SP_F25, SP_F26, SP_F27, + SP_F28, SP_F29, SP_F30, SP_F31 +}; + +static const unsigned DFPRegDecoderTable[] = { + SP_D0, SP_D16, SP_D1, SP_D17, + SP_D2, SP_D18, SP_D3, SP_D19, + SP_D4, SP_D20, SP_D5, SP_D21, + SP_D6, SP_D22, SP_D7, SP_D23, + SP_D8, SP_D24, SP_D9, SP_D25, + SP_D10, SP_D26, SP_D11, SP_D27, + SP_D12, SP_D28, SP_D13, SP_D29, + SP_D14, SP_D30, SP_D15, SP_D31 +}; + +static const unsigned QFPRegDecoderTable[] = { + SP_Q0, SP_Q8, ~0U, ~0U, + SP_Q1, SP_Q9, ~0U, ~0U, + SP_Q2, SP_Q10, ~0U, ~0U, + SP_Q3, SP_Q11, ~0U, ~0U, + SP_Q4, SP_Q12, ~0U, ~0U, + SP_Q5, SP_Q13, ~0U, ~0U, + SP_Q6, SP_Q14, ~0U, ~0U, + SP_Q7, SP_Q15, ~0U, ~0U +}; + +static const unsigned FCCRegDecoderTable[] = { + SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3 +}; + +static uint64_t getFeatureBits(int mode) +{ + // support everything + return (uint64_t)-1; +} + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = IntRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = IntRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = FPRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = DFPRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Reg = QFPRegDecoderTable[RegNo]; + if (Reg == ~0U) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 3) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]); + + return MCDisassembler_Success; +} + + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder); + + +#define GET_SUBTARGETINFO_ENUM +#include "SparcGenSubtargetInfo.inc" +#include "SparcGenDisassemblerTables.inc" + +/// readInstruction - read four bytes and return 32 bit word. +static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn) +{ + if (len < 4) + // not enough data + return MCDisassembler_Fail; + + // Encoded as a big-endian 32-bit word in the stream. + *Insn = (code[3] << 0) | + (code[2] << 8) | + (code[1] << 16) | + ((uint32_t) code[0] << 24); + + return MCDisassembler_Success; +} + +bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, + uint16_t *size, uint64_t address, void *info) +{ + uint32_t Insn; + DecodeStatus Result; + + Result = readInstruction32(code, code_len, &Insn); + if (Result == MCDisassembler_Fail) + return false; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc)); + } + + Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, + (MCRegisterInfo *)info, 0); + if (Result != MCDisassembler_Fail) { + *size = 4; + return true; + } + + return false; +} + +typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder, + bool isLoad, DecodeFunc DecodeRD) +{ + DecodeStatus status; + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0; + unsigned rs2 = 0; + unsigned simm13 = 0; + + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + if (isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + // Decode rs1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode imm|rs2. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + if (!isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeQFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, + const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, const void *Decoder) +{ + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeQFPRegsRegisterClass); +} + +static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, + uint64_t Address, const void *Decoder) +{ + unsigned tgt = fieldFromInstruction_4(insn, 0, 30); + tgt <<= 2; + + MCOperand_CreateImm0(MI, tgt); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, + uint64_t Address, const void *Decoder) +{ + unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + + MCOperand_CreateImm0(MI, tgt); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus status; + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RD. + status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus status; + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS2 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address, + const void *Decoder) +{ + DecodeStatus status; + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RD. + status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + return MCDisassembler_Success; +} + +void Sparc_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, + SparcMCRegisterClasses, 8, + SparcRegUnitRoots, + 86, + SparcRegDiffLists, + SparcRegStrings, + SparcSubRegIdxLists, + 7, + SparcSubRegIdxRanges, + SparcRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119, + 0, 0, + SparcMCRegisterClasses, 8, + 0, 0, + SparcRegDiffLists, + 0, + SparcSubRegIdxLists, 7, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.h b/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.h new file mode 100644 index 0000000..eccb3cb --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcDisassembler.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SPARCDISASSEMBLER_H +#define CS_SPARCDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void Sparc_init(MCRegisterInfo *MRI); + +bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcGenAsmWriter.inc new file mode 100644 index 0000000..d290d3b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcGenAsmWriter.inc @@ -0,0 +1,5709 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include // debug +#include + + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2452U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 2445U, // BUNDLE + 2462U, // LIFETIME_START + 2432U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 4688U, // ADDCCri + 4688U, // ADDCCrr + 5925U, // ADDCri + 5925U, // ADDCrr + 4772U, // ADDEri + 4772U, // ADDErr + 4786U, // ADDXC + 4678U, // ADDXCCC + 4808U, // ADDXri + 4808U, // ADDXrr + 4808U, // ADDri + 4808U, // ADDrr + 74166U, // ADJCALLSTACKDOWN + 74185U, // ADJCALLSTACKUP + 5497U, // ALIGNADDR + 5127U, // ALIGNADDRL + 4695U, // ANDCCri + 4695U, // ANDCCrr + 4718U, // ANDNCCri + 4718U, // ANDNCCrr + 5182U, // ANDNri + 5182U, // ANDNrr + 5182U, // ANDXNrr + 4876U, // ANDXri + 4876U, // ANDXrr + 4876U, // ANDri + 4876U, // ANDrr + 4502U, // ARRAY16 + 4255U, // ARRAY32 + 4526U, // ARRAY8 + 0U, // ATOMIC_LOAD_ADD_32 + 0U, // ATOMIC_LOAD_ADD_64 + 0U, // ATOMIC_LOAD_AND_32 + 0U, // ATOMIC_LOAD_AND_64 + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NAND_32 + 0U, // ATOMIC_LOAD_NAND_64 + 0U, // ATOMIC_LOAD_OR_32 + 0U, // ATOMIC_LOAD_OR_64 + 0U, // ATOMIC_LOAD_SUB_32 + 0U, // ATOMIC_LOAD_SUB_64 + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XOR_32 + 0U, // ATOMIC_LOAD_XOR_64 + 0U, // ATOMIC_SWAP_64 + 74271U, // BA + 1194492U, // BCOND + 1260028U, // BCONDA + 17659U, // BINDri + 17659U, // BINDrr + 5065U, // BMASK + 145915U, // BPFCC + 211451U, // BPFCCA + 276987U, // BPFCCANT + 342523U, // BPFCCNT + 2106465U, // BPGEZapn + 2105838U, // BPGEZapt + 2106532U, // BPGEZnapn + 2107288U, // BPGEZnapt + 2106489U, // BPGZapn + 2105856U, // BPGZapt + 2106552U, // BPGZnapn + 2107384U, // BPGZnapt + 1456636U, // BPICC + 473596U, // BPICCA + 539132U, // BPICCANT + 604668U, // BPICCNT + 2106477U, // BPLEZapn + 2105847U, // BPLEZapt + 2106542U, // BPLEZnapn + 2107337U, // BPLEZnapt + 2106500U, // BPLZapn + 2105864U, // BPLZapt + 2106561U, // BPLZnapn + 2107428U, // BPLZnapt + 2106511U, // BPNZapn + 2105872U, // BPNZapt + 2106570U, // BPNZnapn + 2107472U, // BPNZnapt + 1718780U, // BPXCC + 735740U, // BPXCCA + 801276U, // BPXCCANT + 866812U, // BPXCCNT + 2106522U, // BPZapn + 2105880U, // BPZapt + 2106579U, // BPZnapn + 2107505U, // BPZnapt + 4983U, // BSHUFFLE + 74742U, // CALL + 17398U, // CALLri + 17398U, // CALLrr + 924148U, // CASXrr + 924129U, // CASrr + 74001U, // CMASK16 + 73833U, // CMASK32 + 74150U, // CMASK8 + 2106607U, // CMPri + 2106607U, // CMPrr + 4332U, // EDGE16 + 5081U, // EDGE16L + 5198U, // EDGE16LN + 5165U, // EDGE16N + 4164U, // EDGE32 + 5072U, // EDGE32L + 5188U, // EDGE32LN + 5156U, // EDGE32N + 4511U, // EDGE8 + 5090U, // EDGE8L + 5208U, // EDGE8LN + 5174U, // EDGE8N + 1053516U, // FABSD + 1054031U, // FABSQ + 1054376U, // FABSS + 4813U, // FADDD + 5383U, // FADDQ + 5645U, // FADDS + 4648U, // FALIGNADATA + 4875U, // FAND + 4112U, // FANDNOT1 + 5544U, // FANDNOT1S + 4271U, // FANDNOT2 + 5591U, // FANDNOT2S + 5677U, // FANDS + 1194491U, // FBCOND + 1260027U, // FBCONDA + 4394U, // FCHKSM16 + 2106173U, // FCMPD + 4413U, // FCMPEQ16 + 4226U, // FCMPEQ32 + 4432U, // FCMPGT16 + 4245U, // FCMPGT32 + 4340U, // FCMPLE16 + 4172U, // FCMPLE32 + 4350U, // FCMPNE16 + 4182U, // FCMPNE32 + 2106696U, // FCMPQ + 2107005U, // FCMPS + 4960U, // FDIVD + 5475U, // FDIVQ + 5815U, // FDIVS + 5405U, // FDMULQ + 1053620U, // FDTOI + 1053996U, // FDTOQ + 1054305U, // FDTOS + 1054536U, // FDTOX + 1053464U, // FEXPAND + 4820U, // FHADDD + 5652U, // FHADDS + 4800U, // FHSUBD + 5637U, // FHSUBS + 1053473U, // FITOD + 1054003U, // FITOQ + 1054312U, // FITOS + 6300484U, // FLCMPD + 6301316U, // FLCMPS + 2606U, // FLUSHW + 4404U, // FMEAN16 + 1053543U, // FMOVD + 1006078U, // FMOVD_FCC + 23484926U, // FMOVD_ICC + 23747070U, // FMOVD_XCC + 1054058U, // FMOVQ + 1006102U, // FMOVQ_FCC + 23484950U, // FMOVQ_ICC + 23747094U, // FMOVQ_XCC + 6018U, // FMOVRGEZD + 6029U, // FMOVRGEZQ + 6056U, // FMOVRGEZS + 6116U, // FMOVRGZD + 6126U, // FMOVRGZQ + 6150U, // FMOVRGZS + 6067U, // FMOVRLEZD + 6078U, // FMOVRLEZQ + 6105U, // FMOVRLEZS + 6160U, // FMOVRLZD + 6170U, // FMOVRLZQ + 6194U, // FMOVRLZS + 6204U, // FMOVRNZD + 6214U, // FMOVRNZQ + 6238U, // FMOVRNZS + 6009U, // FMOVRZD + 6248U, // FMOVRZQ + 6269U, // FMOVRZS + 1054398U, // FMOVS + 1006114U, // FMOVS_FCC + 23484962U, // FMOVS_ICC + 23747106U, // FMOVS_XCC + 4490U, // FMUL8SUX16 + 4465U, // FMUL8ULX16 + 4442U, // FMUL8X16 + 5098U, // FMUL8X16AL + 5849U, // FMUL8X16AU + 4860U, // FMULD + 4477U, // FMULD8SUX16 + 4452U, // FMULD8ULX16 + 5413U, // FMULQ + 5714U, // FMULS + 4837U, // FNADDD + 5669U, // FNADDS + 4881U, // FNAND + 5684U, // FNANDS + 1053429U, // FNEGD + 1053974U, // FNEGQ + 1054283U, // FNEGS + 4828U, // FNHADDD + 5660U, // FNHADDS + 4828U, // FNMULD + 5660U, // FNMULS + 5513U, // FNOR + 5778U, // FNORS + 1052698U, // FNOT1 + 1054131U, // FNOT1S + 1052857U, // FNOT2 + 1054178U, // FNOT2S + 5660U, // FNSMULD + 74625U, // FONE + 75324U, // FONES + 5508U, // FOR + 4129U, // FORNOT1 + 5563U, // FORNOT1S + 4288U, // FORNOT2 + 5610U, // FORNOT2S + 5772U, // FORS + 1052936U, // FPACK16 + 4192U, // FPACK32 + 1054507U, // FPACKFIX + 4323U, // FPADD16 + 5620U, // FPADD16S + 4155U, // FPADD32 + 5573U, // FPADD32S + 4297U, // FPADD64 + 4974U, // FPMERGE + 4314U, // FPSUB16 + 4580U, // FPSUB16S + 4146U, // FPSUB32 + 4570U, // FPSUB32S + 1053480U, // FQTOD + 1053627U, // FQTOI + 1054319U, // FQTOS + 1054552U, // FQTOX + 4423U, // FSLAS16 + 4236U, // FSLAS32 + 4378U, // FSLL16 + 4210U, // FSLL32 + 4867U, // FSMULD + 1053523U, // FSQRTD + 1054038U, // FSQRTQ + 1054383U, // FSQRTS + 4306U, // FSRA16 + 4138U, // FSRA32 + 1052681U, // FSRC1 + 1054112U, // FSRC1S + 1052840U, // FSRC2 + 1054159U, // FSRC2S + 4386U, // FSRL16 + 4218U, // FSRL32 + 1053487U, // FSTOD + 1053634U, // FSTOI + 1054010U, // FSTOQ + 1054559U, // FSTOX + 4793U, // FSUBD + 5376U, // FSUBQ + 5630U, // FSUBS + 5519U, // FXNOR + 5785U, // FXNORS + 5526U, // FXOR + 5793U, // FXORS + 1053494U, // FXTOD + 1054017U, // FXTOQ + 1054326U, // FXTOS + 74984U, // FZERO + 75353U, // FZEROS + 24584U, // GETPCX + 1078273U, // JMPLri + 1078273U, // JMPLrr + 1997243U, // LDDFri + 1997243U, // LDDFrr + 1997249U, // LDFri + 1997249U, // LDFrr + 1997275U, // LDQFri + 1997275U, // LDQFrr + 1997229U, // LDSBri + 1997229U, // LDSBrr + 1997254U, // LDSHri + 1997254U, // LDSHrr + 1997287U, // LDSWri + 1997287U, // LDSWrr + 1997236U, // LDUBri + 1997236U, // LDUBrr + 1997261U, // LDUHri + 1997261U, // LDUHrr + 1997294U, // LDXri + 1997294U, // LDXrr + 1997249U, // LDri + 1997249U, // LDrr + 33480U, // LEAX_ADDri + 33480U, // LEA_ADDri + 1054405U, // LZCNT + 75121U, // MEMBARi + 1054543U, // MOVDTOX + 1006122U, // MOVFCCri + 1006122U, // MOVFCCrr + 23484970U, // MOVICCri + 23484970U, // MOVICCrr + 6047U, // MOVRGEZri + 6047U, // MOVRGEZrr + 6142U, // MOVRGZri + 6142U, // MOVRGZrr + 6096U, // MOVRLEZri + 6096U, // MOVRLEZrr + 6186U, // MOVRLZri + 6186U, // MOVRLZrr + 6230U, // MOVRNZri + 6230U, // MOVRNZrr + 6262U, // MOVRRZri + 6262U, // MOVRRZrr + 1054469U, // MOVSTOSW + 1054479U, // MOVSTOUW + 1054543U, // MOVWTOS + 23747114U, // MOVXCCri + 23747114U, // MOVXCCrr + 1054543U, // MOVXTOD + 5954U, // MULXri + 5954U, // MULXrr + 2578U, // NOP + 4735U, // ORCCri + 4735U, // ORCCrr + 4726U, // ORNCCri + 4726U, // ORNCCrr + 5339U, // ORNri + 5339U, // ORNrr + 5339U, // ORXNrr + 5509U, // ORXri + 5509U, // ORXrr + 5509U, // ORri + 5509U, // ORrr + 5836U, // PDIST + 5344U, // PDISTN + 1053356U, // POPCrr + 73729U, // RDY + 4999U, // RESTOREri + 4999U, // RESTORErr + 76132U, // RET + 76141U, // RETL + 18131U, // RETTri + 18131U, // RETTrr + 5008U, // SAVEri + 5008U, // SAVErr + 4748U, // SDIVCCri + 4748U, // SDIVCCrr + 5995U, // SDIVXri + 5995U, // SDIVXrr + 5861U, // SDIVri + 5861U, // SDIVrr + 2182U, // SELECT_CC_DFP_FCC + 2293U, // SELECT_CC_DFP_ICC + 2238U, // SELECT_CC_FP_FCC + 2349U, // SELECT_CC_FP_ICC + 2265U, // SELECT_CC_Int_FCC + 2376U, // SELECT_CC_Int_ICC + 2210U, // SELECT_CC_QFP_FCC + 2321U, // SELECT_CC_QFP_ICC + 1053595U, // SETHIXi + 1053595U, // SETHIi + 2569U, // SHUTDOWN + 2564U, // SIAM + 5941U, // SLLXri + 5941U, // SLLXrr + 5116U, // SLLri + 5116U, // SLLrr + 4702U, // SMULCCri + 4702U, // SMULCCrr + 5144U, // SMULri + 5144U, // SMULrr + 5913U, // SRAXri + 5913U, // SRAXrr + 4643U, // SRAri + 4643U, // SRArr + 5947U, // SRLXri + 5947U, // SRLXrr + 5139U, // SRLri + 5139U, // SRLrr + 2588U, // STBAR + 37428U, // STBri + 37428U, // STBrr + 37723U, // STDFri + 37723U, // STDFrr + 38607U, // STFri + 38607U, // STFrr + 37782U, // STHri + 37782U, // STHrr + 38238U, // STQFri + 38238U, // STQFrr + 38758U, // STXri + 38758U, // STXrr + 38607U, // STri + 38607U, // STrr + 4671U, // SUBCCri + 4671U, // SUBCCrr + 5919U, // SUBCri + 5919U, // SUBCrr + 4764U, // SUBEri + 4764U, // SUBErr + 4665U, // SUBXri + 4665U, // SUBXrr + 4665U, // SUBri + 4665U, // SUBrr + 1997268U, // SWAPri + 1997268U, // SWAPrr + 2422U, // TA3 + 2427U, // TA5 + 5883U, // TADDCCTVri + 5883U, // TADDCCTVrr + 4687U, // TADDCCri + 4687U, // TADDCCrr + 9873960U, // TICCri + 9873960U, // TICCrr + 37753544U, // TLS_ADDXrr + 37753544U, // TLS_ADDrr + 2106358U, // TLS_CALL + 39746030U, // TLS_LDXrr + 39745985U, // TLS_LDrr + 5873U, // TSUBCCTVri + 5873U, // TSUBCCTVrr + 4670U, // TSUBCCri + 4670U, // TSUBCCrr + 10136104U, // TXCCri + 10136104U, // TXCCrr + 4756U, // UDIVCCri + 4756U, // UDIVCCrr + 6002U, // UDIVXri + 6002U, // UDIVXrr + 5867U, // UDIVri + 5867U, // UDIVrr + 4710U, // UMULCCri + 4710U, // UMULCCrr + 5026U, // UMULXHI + 5150U, // UMULri + 5150U, // UMULrr + 74996U, // UNIMP + 6300477U, // V9FCMPD + 6300397U, // V9FCMPED + 6300942U, // V9FCMPEQ + 6301251U, // V9FCMPES + 6301000U, // V9FCMPQ + 6301309U, // V9FCMPS + 47614U, // V9FMOVD_FCC + 47638U, // V9FMOVQ_FCC + 47650U, // V9FMOVS_FCC + 47658U, // V9MOVFCCri + 47658U, // V9MOVFCCrr + 14689692U, // WRYri + 14689692U, // WRYrr + 5953U, // XMULX + 5035U, // XMULXHI + 4733U, // XNORCCri + 4733U, // XNORCCrr + 5520U, // XNORXrr + 5520U, // XNORri + 5520U, // XNORrr + 4741U, // XORCCri + 4741U, // XORCCrr + 5527U, // XORXri + 5527U, // XORXrr + 5527U, // XORri + 5527U, // XORrr + 0U + }; + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0, + /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0, + /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0, + /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0, + /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0, + /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0, + /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0, + /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0, + /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0, + /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0, + /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0, + /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0, + /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0, + /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0, + /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0, + /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0, + /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0, + /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0, + /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0, + /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0, + /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0, + /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0, + /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0, + /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0, + /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0, + /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0, + /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0, + /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0, + /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0, + /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0, + /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0, + /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0, + /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0, + /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0, + /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0, + /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0, + /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0, + /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0, + /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0, + /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0, + /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0, + /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0, + /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0, + /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0, + /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0, + /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0, + /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0, + /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0, + /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, + /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, + /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0, + /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0, + /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0, + /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0, + /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0, + /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0, + /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0, + /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0, + /* 542 */ 'b', 'a', 32, 0, + /* 546 */ 's', 'r', 'a', 32, 0, + /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0, + /* 563 */ 's', 't', 'b', 32, 0, + /* 568 */ 's', 'u', 'b', 32, 0, + /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0, + /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0, + /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0, + /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0, + /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0, + /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0, + /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0, + /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0, + /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0, + /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0, + /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0, + /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0, + /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0, + /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0, + /* 683 */ 'p', 'o', 'p', 'c', 32, 0, + /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0, + /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0, + /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0, + /* 711 */ 'a', 'd', 'd', 32, 0, + /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0, + /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0, + /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0, + /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0, + /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0, + /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0, + /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0, + /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0, + /* 778 */ 'f', 'a', 'n', 'd', 32, 0, + /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0, + /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0, + /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0, + /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0, + /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0, + /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0, + /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0, + /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0, + /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0, + /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0, + /* 858 */ 's', 't', 'd', 32, 0, + /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0, + /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0, + /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0, + /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0, + /* 896 */ 'f', 'o', 'n', 'e', 32, 0, + /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0, + /* 911 */ 's', 'a', 'v', 'e', 32, 0, + /* 917 */ 's', 't', 'h', 32, 0, + /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0, + /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, + /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, + /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0, + /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0, + /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0, + /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0, + /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0, + /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0, + /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0, + /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0, + /* 1013 */ 'c', 'a', 'l', 'l', 32, 0, + /* 1019 */ 's', 'l', 'l', 32, 0, + /* 1024 */ 'j', 'm', 'p', 'l', 32, 0, + /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0, + /* 1042 */ 's', 'r', 'l', 32, 0, + /* 1047 */ 's', 'm', 'u', 'l', 32, 0, + /* 1053 */ 'u', 'm', 'u', 'l', 32, 0, + /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0, + /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0, + /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0, + /* 1085 */ 'a', 'n', 'd', 'n', 32, 0, + /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0, + /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0, + /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0, + /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0, + /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0, + /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0, + /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0, + /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0, + /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0, + /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0, + /* 1242 */ 'o', 'r', 'n', 32, 0, + /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0, + /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0, + /* 1262 */ 'c', 'm', 'p', 32, 0, + /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0, + /* 1274 */ 'j', 'm', 'p', 32, 0, + /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0, + /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0, + /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, + /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0, + /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0, + /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0, + /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0, + /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0, + /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0, + /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0, + /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0, + /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0, + /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0, + /* 1373 */ 's', 't', 'q', 32, 0, + /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0, + /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0, + /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0, + /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0, + /* 1411 */ 'f', 'o', 'r', 32, 0, + /* 1416 */ 'f', 'n', 'o', 'r', 32, 0, + /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0, + /* 1429 */ 'f', 'x', 'o', 'r', 32, 0, + /* 1435 */ 'w', 'r', 32, 0, + /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0, + /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0, + /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0, + /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0, + /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0, + /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0, + /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0, + /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0, + /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0, + /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0, + /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0, + /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0, + /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0, + /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0, + /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0, + /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0, + /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0, + /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0, + /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0, + /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0, + /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0, + /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0, + /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0, + /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0, + /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0, + /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0, + /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0, + /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0, + /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0, + /* 1675 */ 'f', 'o', 'r', 's', 32, 0, + /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0, + /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0, + /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0, + /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0, + /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, + /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0, + /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0, + /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0, + /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0, + /* 1746 */ 'r', 'e', 't', 't', 32, 0, + /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0, + /* 1764 */ 's', 'd', 'i', 'v', 32, 0, + /* 1770 */ 'u', 'd', 'i', 'v', 32, 0, + /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0, + /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0, + /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0, + /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0, + /* 1816 */ 's', 'r', 'a', 'x', 32, 0, + /* 1822 */ 's', 'u', 'b', 'x', 32, 0, + /* 1828 */ 'a', 'd', 'd', 'x', 32, 0, + /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0, + /* 1844 */ 's', 'l', 'l', 'x', 32, 0, + /* 1850 */ 's', 'r', 'l', 'x', 32, 0, + /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0, + /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0, + /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0, + /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0, + /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0, + /* 1893 */ 's', 't', 'x', 32, 0, + /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0, + /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0, + /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0, + /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0, + /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0, + /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0, + /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0, + /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0, + /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0, + /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0, + /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0, + /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0, + /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0, + /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0, + /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0, + /* 2039 */ 'b', 'r', 'g', 'z', 32, 0, + /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0, + /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0, + /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0, + /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0, + /* 2083 */ 'b', 'r', 'l', 'z', 32, 0, + /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0, + /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0, + /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0, + /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0, + /* 2127 */ 'b', 'r', 'n', 'z', 32, 0, + /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0, + /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0, + /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0, + /* 2160 */ 'b', 'r', 'z', 32, 0, + /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0, + /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0, + /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0, + /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0, + /* 2421 */ 't', 'a', 32, '3', 0, + /* 2426 */ 't', 'a', 32, '5', 0, + /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0, + /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0, + /* 2490 */ 'l', 'd', 'd', 32, '[', 0, + /* 2496 */ 'l', 'd', 32, '[', 0, + /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0, + /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0, + /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0, + /* 2522 */ 'l', 'd', 'q', 32, '[', 0, + /* 2528 */ 'c', 'a', 's', 32, '[', 0, + /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0, + /* 2541 */ 'l', 'd', 'x', 32, '[', 0, + /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0, + /* 2554 */ 'f', 'b', 0, + /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0, + /* 2563 */ 's', 'i', 'a', 'm', 0, + /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0, + /* 2577 */ 'n', 'o', 'p', 0, + /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0, + /* 2587 */ 's', 't', 'b', 'a', 'r', 0, + /* 2593 */ 'f', 'm', 'o', 'v', 's', 0, + /* 2599 */ 't', 0, + /* 2601 */ 'm', 'o', 'v', 0, + /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0, + }; +#endif + + // Emit the opcode for the instruction. + uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; +#ifndef CAPSTONE_DIET + // assert(Bits != 0 && "Cannot print this instruction."); + SStream_concat0(O, AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 4 bits for 12 unique commands. + // printf("Frag-0: %u\n", (Bits >> 12) & 15); + switch ((Bits >> 12) & 15) { + default: // unreachable. + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C... + return; + break; + case 1: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand(MI, 1, O); + break; + case 2: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... + printOperand(MI, 0, O); + break; + case 3: + // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... + printCCOperand(MI, 1, O); + break; + case 4: + // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr + printMemOperand(MI, 0, O, NULL); + return; + break; + case 5: + // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... + printCCOperand(MI, 3, O); + break; + case 6: + // GETPCX + printGetPCX(MI, 0, O); + return; + break; + case 7: + // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ... + printMemOperand(MI, 1, O, NULL); + break; + case 8: + // LEAX_ADDri, LEA_ADDri + printMemOperand(MI, 1, O, "arith"); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 9: + // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF... + printOperand(MI, 2, O); + SStream_concat0(O, ", ["); + printMemOperand(MI, 0, O, NULL); + SStream_concat0(O, "]"); + return; + break; + case 10: + // TICCri, TICCrr, TXCCri, TXCCrr + printCCOperand(MI, 2, O); + break; + case 11: + // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr + printCCOperand(MI, 4, O); + SStream_concat0(O, " "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 4 bits for 16 unique commands. + // printf("Frag-1: %u\n", (Bits >> 16) & 15); + switch ((Bits >> 16) & 15) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + SStream_concat0(O, ", "); + break; + case 1: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ... + return; + break; + case 2: + // BCOND, BPFCC, FBCOND + SStream_concat0(O, " "); + break; + case 3: + // BCONDA, BPFCCA, FBCONDA + SStream_concat0(O, ",a "); + Sparc_add_hint(MI, SPARC_HINT_A); + break; + case 4: + // BPFCCANT + SStream_concat0(O, ",a,pn "); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 5: + // BPFCCNT + SStream_concat0(O, ",pn "); + Sparc_add_hint(MI, SPARC_HINT_PN); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 6: + // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... + SStream_concat0(O, " %icc, "); + Sparc_add_reg(MI, SPARC_REG_ICC); + break; + case 7: + // BPICCA + SStream_concat0(O, ",a %icc, "); + Sparc_add_hint(MI, SPARC_HINT_A); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); + return; + break; + case 8: + // BPICCANT + SStream_concat0(O, ",a,pn %icc, "); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); + return; + break; + case 9: + // BPICCNT + SStream_concat0(O, ",pn %icc, "); + Sparc_add_hint(MI, SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); + return; + break; + case 10: + // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... + SStream_concat0(O, " %xcc, "); + Sparc_add_reg(MI, SPARC_REG_XCC); + break; + case 11: + // BPXCCA + SStream_concat0(O, ",a %xcc, "); + Sparc_add_hint(MI, SPARC_HINT_A); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); + return; + break; + case 12: + // BPXCCANT + SStream_concat0(O, ",a,pn %xcc, "); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); + return; + break; + case 13: + // BPXCCNT + SStream_concat0(O, ",pn %xcc, "); + Sparc_add_hint(MI, SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); + return; + break; + case 14: + // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L... + SStream_concat0(O, "], "); + break; + case 15: + // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr + SStream_concat0(O, " %fcc0, "); + Sparc_add_reg(MI, SPARC_REG_FCC0); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + } + + + // Fragment 2 encoded into 2 bits for 3 unique commands. + // printf("Frag-2: %u\n", (Bits >> 20) & 3); + switch ((Bits >> 20) & 3) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + break; + case 1: + // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT... + printOperand(MI, 0, O); + break; + case 2: + // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ... + printOperand(MI, 1, O); + break; + } + + + // Fragment 3 encoded into 2 bits for 4 unique commands. + // printf("Frag-3: %u\n", (Bits >> 22) & 3); + switch ((Bits >> 22) & 3) { + default: // unreachable. + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + return; + break; + case 1: + // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,... + SStream_concat0(O, ", "); + break; + case 2: + // TICCri, TICCrr, TXCCri, TXCCrr + SStream_concat0(O, " + "); // qq + printOperand(MI, 1, O); + return; + break; + case 3: + // WRYri, WRYrr + SStream_concat0(O, ", %y"); + Sparc_add_reg(MI, SPARC_REG_Y); + return; + break; + } + + + // Fragment 4 encoded into 2 bits for 3 unique commands. + // printf("Frag-4: %u\n", (Bits >> 24) & 3); + switch ((Bits >> 24) & 3) { + default: // unreachable. + case 0: + // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... + printOperand(MI, 2, O); + return; + break; + case 1: + // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI... + printOperand(MI, 0, O); + return; + break; + case 2: + // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr + printOperand(MI, 3, O); + return; + break; + } +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 119 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'f', '2', '0', 0, + /* 8 */ 'f', '3', '0', 0, + /* 12 */ 'f', '4', '0', 0, + /* 16 */ 'f', '5', '0', 0, + /* 20 */ 'f', '6', '0', 0, + /* 24 */ 'f', 'c', 'c', '0', 0, + /* 29 */ 'f', '0', 0, + /* 32 */ 'g', '0', 0, + /* 35 */ 'i', '0', 0, + /* 38 */ 'l', '0', 0, + /* 41 */ 'o', '0', 0, + /* 44 */ 'f', '1', '1', 0, + /* 48 */ 'f', '2', '1', 0, + /* 52 */ 'f', '3', '1', 0, + /* 56 */ 'f', 'c', 'c', '1', 0, + /* 61 */ 'f', '1', 0, + /* 64 */ 'g', '1', 0, + /* 67 */ 'i', '1', 0, + /* 70 */ 'l', '1', 0, + /* 73 */ 'o', '1', 0, + /* 76 */ 'f', '1', '2', 0, + /* 80 */ 'f', '2', '2', 0, + /* 84 */ 'f', '3', '2', 0, + /* 88 */ 'f', '4', '2', 0, + /* 92 */ 'f', '5', '2', 0, + /* 96 */ 'f', '6', '2', 0, + /* 100 */ 'f', 'c', 'c', '2', 0, + /* 105 */ 'f', '2', 0, + /* 108 */ 'g', '2', 0, + /* 111 */ 'i', '2', 0, + /* 114 */ 'l', '2', 0, + /* 117 */ 'o', '2', 0, + /* 120 */ 'f', '1', '3', 0, + /* 124 */ 'f', '2', '3', 0, + /* 128 */ 'f', 'c', 'c', '3', 0, + /* 133 */ 'f', '3', 0, + /* 136 */ 'g', '3', 0, + /* 139 */ 'i', '3', 0, + /* 142 */ 'l', '3', 0, + /* 145 */ 'o', '3', 0, + /* 148 */ 'f', '1', '4', 0, + /* 152 */ 'f', '2', '4', 0, + /* 156 */ 'f', '3', '4', 0, + /* 160 */ 'f', '4', '4', 0, + /* 164 */ 'f', '5', '4', 0, + /* 168 */ 'f', '4', 0, + /* 171 */ 'g', '4', 0, + /* 174 */ 'i', '4', 0, + /* 177 */ 'l', '4', 0, + /* 180 */ 'o', '4', 0, + /* 183 */ 'f', '1', '5', 0, + /* 187 */ 'f', '2', '5', 0, + /* 191 */ 'f', '5', 0, + /* 194 */ 'g', '5', 0, + /* 197 */ 'i', '5', 0, + /* 200 */ 'l', '5', 0, + /* 203 */ 'o', '5', 0, + /* 206 */ 'f', '1', '6', 0, + /* 210 */ 'f', '2', '6', 0, + /* 214 */ 'f', '3', '6', 0, + /* 218 */ 'f', '4', '6', 0, + /* 222 */ 'f', '5', '6', 0, + /* 226 */ 'f', '6', 0, + /* 229 */ 'g', '6', 0, + /* 232 */ 'l', '6', 0, + /* 235 */ 'f', '1', '7', 0, + /* 239 */ 'f', '2', '7', 0, + /* 243 */ 'f', '7', 0, + /* 246 */ 'g', '7', 0, + /* 249 */ 'i', '7', 0, + /* 252 */ 'l', '7', 0, + /* 255 */ 'o', '7', 0, + /* 258 */ 'f', '1', '8', 0, + /* 262 */ 'f', '2', '8', 0, + /* 266 */ 'f', '3', '8', 0, + /* 270 */ 'f', '4', '8', 0, + /* 274 */ 'f', '5', '8', 0, + /* 278 */ 'f', '8', 0, + /* 281 */ 'f', '1', '9', 0, + /* 285 */ 'f', '2', '9', 0, + /* 289 */ 'f', '9', 0, + /* 292 */ 'i', 'c', 'c', 0, + /* 296 */ 'f', 'p', 0, + /* 299 */ 's', 'p', 0, + /* 302 */ 'y', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, + 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, + 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, + 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, + 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, + 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, + 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, + 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, + 12, 160, 270, 92, 222, 20, + }; + + //int i; + //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("*************************\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) +{ +} + +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +{ + #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + const char *AsmString; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + switch (MCInst_getOpcode(MI)) { + default: return NULL; + case SP_BCOND: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BCOND brtarget:$imm, 8) + AsmString = "ba $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BCOND brtarget:$imm, 0) + AsmString = "bn $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BCOND brtarget:$imm, 9) + AsmString = "bne $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BCOND brtarget:$imm, 1) + AsmString = "be $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BCOND brtarget:$imm, 10) + AsmString = "bg $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BCOND brtarget:$imm, 2) + AsmString = "ble $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BCOND brtarget:$imm, 11) + AsmString = "bge $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BCOND brtarget:$imm, 3) + AsmString = "bl $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BCOND brtarget:$imm, 12) + AsmString = "bgu $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BCOND brtarget:$imm, 4) + AsmString = "bleu $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BCOND brtarget:$imm, 13) + AsmString = "bcc $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BCOND brtarget:$imm, 5) + AsmString = "bcs $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BCOND brtarget:$imm, 14) + AsmString = "bpos $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BCOND brtarget:$imm, 6) + AsmString = "bneg $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BCOND brtarget:$imm, 15) + AsmString = "bvc $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BCOND brtarget:$imm, 7) + AsmString = "bvs $\x01"; + break; + } + return NULL; + case SP_BCONDA: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BCONDA brtarget:$imm, 8) + AsmString = "ba,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BCONDA brtarget:$imm, 0) + AsmString = "bn,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BCONDA brtarget:$imm, 9) + AsmString = "bne,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BCONDA brtarget:$imm, 1) + AsmString = "be,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BCONDA brtarget:$imm, 10) + AsmString = "bg,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BCONDA brtarget:$imm, 2) + AsmString = "ble,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BCONDA brtarget:$imm, 11) + AsmString = "bge,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BCONDA brtarget:$imm, 3) + AsmString = "bl,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BCONDA brtarget:$imm, 12) + AsmString = "bgu,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BCONDA brtarget:$imm, 4) + AsmString = "bleu,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BCONDA brtarget:$imm, 13) + AsmString = "bcc,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BCONDA brtarget:$imm, 5) + AsmString = "bcs,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BCONDA brtarget:$imm, 14) + AsmString = "bpos,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BCONDA brtarget:$imm, 6) + AsmString = "bneg,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BCONDA brtarget:$imm, 15) + AsmString = "bvc,a $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BCONDA brtarget:$imm, 7) + AsmString = "bvs,a $\x01"; + break; + } + return NULL; + case SP_BPFCCANT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) + AsmString = "fba,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) + AsmString = "fbn,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) + AsmString = "fbu,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) + AsmString = "fbg,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) + AsmString = "fbug,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) + AsmString = "fbl,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) + AsmString = "fbul,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) + AsmString = "fblg,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) + AsmString = "fbne,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) + AsmString = "fbe,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) + AsmString = "fbue,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) + AsmString = "fbge,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) + AsmString = "fbuge,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) + AsmString = "fble,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) + AsmString = "fbule,a,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) + AsmString = "fbo,a,pn $\x03, $\x01"; + break; + } + return NULL; + case SP_BPFCCNT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) + AsmString = "fba,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) + AsmString = "fbn,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) + AsmString = "fbu,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) + AsmString = "fbg,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) + AsmString = "fbug,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) + AsmString = "fbl,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) + AsmString = "fbul,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) + AsmString = "fblg,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) + AsmString = "fbne,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) + AsmString = "fbe,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) + AsmString = "fbue,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) + AsmString = "fbge,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) + AsmString = "fbuge,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) + AsmString = "fble,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) + AsmString = "fbule,pn $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { + // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) + AsmString = "fbo,pn $\x03, $\x01"; + break; + } + return NULL; + case SP_BPICCANT: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BPICCANT brtarget:$imm, 8) + AsmString = "ba,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BPICCANT brtarget:$imm, 0) + AsmString = "bn,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BPICCANT brtarget:$imm, 9) + AsmString = "bne,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BPICCANT brtarget:$imm, 1) + AsmString = "be,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BPICCANT brtarget:$imm, 10) + AsmString = "bg,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BPICCANT brtarget:$imm, 2) + AsmString = "ble,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BPICCANT brtarget:$imm, 11) + AsmString = "bge,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BPICCANT brtarget:$imm, 3) + AsmString = "bl,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BPICCANT brtarget:$imm, 12) + AsmString = "bgu,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BPICCANT brtarget:$imm, 4) + AsmString = "bleu,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BPICCANT brtarget:$imm, 13) + AsmString = "bcc,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BPICCANT brtarget:$imm, 5) + AsmString = "bcs,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BPICCANT brtarget:$imm, 14) + AsmString = "bpos,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BPICCANT brtarget:$imm, 6) + AsmString = "bneg,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BPICCANT brtarget:$imm, 15) + AsmString = "bvc,a,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BPICCANT brtarget:$imm, 7) + AsmString = "bvs,a,pn %icc, $\x01"; + break; + } + return NULL; + case SP_BPICCNT: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BPICCNT brtarget:$imm, 8) + AsmString = "ba,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BPICCNT brtarget:$imm, 0) + AsmString = "bn,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BPICCNT brtarget:$imm, 9) + AsmString = "bne,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BPICCNT brtarget:$imm, 1) + AsmString = "be,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BPICCNT brtarget:$imm, 10) + AsmString = "bg,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BPICCNT brtarget:$imm, 2) + AsmString = "ble,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BPICCNT brtarget:$imm, 11) + AsmString = "bge,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BPICCNT brtarget:$imm, 3) + AsmString = "bl,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BPICCNT brtarget:$imm, 12) + AsmString = "bgu,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BPICCNT brtarget:$imm, 4) + AsmString = "bleu,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BPICCNT brtarget:$imm, 13) + AsmString = "bcc,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BPICCNT brtarget:$imm, 5) + AsmString = "bcs,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BPICCNT brtarget:$imm, 14) + AsmString = "bpos,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BPICCNT brtarget:$imm, 6) + AsmString = "bneg,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BPICCNT brtarget:$imm, 15) + AsmString = "bvc,pn %icc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BPICCNT brtarget:$imm, 7) + AsmString = "bvs,pn %icc, $\x01"; + break; + } + return NULL; + case SP_BPXCCANT: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BPXCCANT brtarget:$imm, 8) + AsmString = "ba,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BPXCCANT brtarget:$imm, 0) + AsmString = "bn,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BPXCCANT brtarget:$imm, 9) + AsmString = "bne,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BPXCCANT brtarget:$imm, 1) + AsmString = "be,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BPXCCANT brtarget:$imm, 10) + AsmString = "bg,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BPXCCANT brtarget:$imm, 2) + AsmString = "ble,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BPXCCANT brtarget:$imm, 11) + AsmString = "bge,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BPXCCANT brtarget:$imm, 3) + AsmString = "bl,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BPXCCANT brtarget:$imm, 12) + AsmString = "bgu,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BPXCCANT brtarget:$imm, 4) + AsmString = "bleu,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BPXCCANT brtarget:$imm, 13) + AsmString = "bcc,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BPXCCANT brtarget:$imm, 5) + AsmString = "bcs,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BPXCCANT brtarget:$imm, 14) + AsmString = "bpos,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BPXCCANT brtarget:$imm, 6) + AsmString = "bneg,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BPXCCANT brtarget:$imm, 15) + AsmString = "bvc,a,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BPXCCANT brtarget:$imm, 7) + AsmString = "bvs,a,pn %xcc, $\x01"; + break; + } + return NULL; + case SP_BPXCCNT: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { + // (BPXCCNT brtarget:$imm, 8) + AsmString = "ba,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { + // (BPXCCNT brtarget:$imm, 0) + AsmString = "bn,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { + // (BPXCCNT brtarget:$imm, 9) + AsmString = "bne,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { + // (BPXCCNT brtarget:$imm, 1) + AsmString = "be,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { + // (BPXCCNT brtarget:$imm, 10) + AsmString = "bg,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { + // (BPXCCNT brtarget:$imm, 2) + AsmString = "ble,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { + // (BPXCCNT brtarget:$imm, 11) + AsmString = "bge,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { + // (BPXCCNT brtarget:$imm, 3) + AsmString = "bl,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { + // (BPXCCNT brtarget:$imm, 12) + AsmString = "bgu,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { + // (BPXCCNT brtarget:$imm, 4) + AsmString = "bleu,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { + // (BPXCCNT brtarget:$imm, 13) + AsmString = "bcc,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { + // (BPXCCNT brtarget:$imm, 5) + AsmString = "bcs,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { + // (BPXCCNT brtarget:$imm, 14) + AsmString = "bpos,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { + // (BPXCCNT brtarget:$imm, 6) + AsmString = "bneg,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { + // (BPXCCNT brtarget:$imm, 15) + AsmString = "bvc,pn %xcc, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { + // (BPXCCNT brtarget:$imm, 7) + AsmString = "bvs,pn %xcc, $\x01"; + break; + } + return NULL; + case SP_FMOVD_ICC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) + AsmString = "fmovda %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) + AsmString = "fmovdn %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) + AsmString = "fmovdne %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) + AsmString = "fmovde %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) + AsmString = "fmovdg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) + AsmString = "fmovdle %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) + AsmString = "fmovdge %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) + AsmString = "fmovdl %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) + AsmString = "fmovdgu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) + AsmString = "fmovdleu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) + AsmString = "fmovdcc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) + AsmString = "fmovdcs %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) + AsmString = "fmovdpos %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) + AsmString = "fmovdneg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) + AsmString = "fmovdvc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) + AsmString = "fmovdvs %icc, $\x02, $\x01"; + break; + } + return NULL; + case SP_FMOVD_XCC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) + AsmString = "fmovda %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) + AsmString = "fmovdn %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) + AsmString = "fmovdne %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) + AsmString = "fmovde %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) + AsmString = "fmovdg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) + AsmString = "fmovdle %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) + AsmString = "fmovdge %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) + AsmString = "fmovdl %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) + AsmString = "fmovdgu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) + AsmString = "fmovdleu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) + AsmString = "fmovdcc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) + AsmString = "fmovdcs %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) + AsmString = "fmovdpos %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) + AsmString = "fmovdneg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) + AsmString = "fmovdvc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) + AsmString = "fmovdvs %xcc, $\x02, $\x01"; + break; + } + return NULL; + case SP_FMOVQ_ICC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) + AsmString = "fmovqa %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) + AsmString = "fmovqn %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) + AsmString = "fmovqne %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) + AsmString = "fmovqe %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) + AsmString = "fmovqg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) + AsmString = "fmovqle %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) + AsmString = "fmovqge %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) + AsmString = "fmovql %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) + AsmString = "fmovqgu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) + AsmString = "fmovqleu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) + AsmString = "fmovqcc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) + AsmString = "fmovqcs %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) + AsmString = "fmovqpos %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) + AsmString = "fmovqneg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) + AsmString = "fmovqvc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) + AsmString = "fmovqvs %icc, $\x02, $\x01"; + break; + } + return NULL; + case SP_FMOVQ_XCC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) + AsmString = "fmovqa %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) + AsmString = "fmovqn %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) + AsmString = "fmovqne %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) + AsmString = "fmovqe %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) + AsmString = "fmovqg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) + AsmString = "fmovqle %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) + AsmString = "fmovqge %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) + AsmString = "fmovql %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) + AsmString = "fmovqgu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) + AsmString = "fmovqleu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) + AsmString = "fmovqcc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) + AsmString = "fmovqcs %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) + AsmString = "fmovqpos %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) + AsmString = "fmovqneg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) + AsmString = "fmovqvc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) + AsmString = "fmovqvs %xcc, $\x02, $\x01"; + break; + } + return NULL; + case SP_FMOVS_ICC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) + AsmString = "fmovsa %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) + AsmString = "fmovsn %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) + AsmString = "fmovsne %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) + AsmString = "fmovse %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) + AsmString = "fmovsg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) + AsmString = "fmovsle %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) + AsmString = "fmovsge %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) + AsmString = "fmovsl %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) + AsmString = "fmovsgu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) + AsmString = "fmovsleu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) + AsmString = "fmovscc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) + AsmString = "fmovscs %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) + AsmString = "fmovspos %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) + AsmString = "fmovsneg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) + AsmString = "fmovsvc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) + AsmString = "fmovsvs %icc, $\x02, $\x01"; + break; + } + return NULL; + case SP_FMOVS_XCC: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) + AsmString = "fmovsa %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) + AsmString = "fmovsn %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) + AsmString = "fmovsne %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) + AsmString = "fmovse %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) + AsmString = "fmovsg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) + AsmString = "fmovsle %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) + AsmString = "fmovsge %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) + AsmString = "fmovsl %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) + AsmString = "fmovsgu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) + AsmString = "fmovsleu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) + AsmString = "fmovscc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) + AsmString = "fmovscs %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) + AsmString = "fmovspos %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) + AsmString = "fmovsneg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) + AsmString = "fmovsvc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) + AsmString = "fmovsvs %xcc, $\x02, $\x01"; + break; + } + return NULL; + case SP_MOVICCri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) + AsmString = "mova %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) + AsmString = "movn %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) + AsmString = "movne %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) + AsmString = "move %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) + AsmString = "movg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) + AsmString = "movle %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) + AsmString = "movge %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) + AsmString = "movl %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) + AsmString = "movgu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) + AsmString = "movleu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) + AsmString = "movcc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) + AsmString = "movcs %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) + AsmString = "movpos %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) + AsmString = "movneg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) + AsmString = "movvc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) + AsmString = "movvs %icc, $\x02, $\x01"; + break; + } + return NULL; + case SP_MOVICCrr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) + AsmString = "mova %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) + AsmString = "movn %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) + AsmString = "movne %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) + AsmString = "move %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) + AsmString = "movg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) + AsmString = "movle %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) + AsmString = "movge %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) + AsmString = "movl %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) + AsmString = "movgu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) + AsmString = "movleu %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) + AsmString = "movcc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) + AsmString = "movcs %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) + AsmString = "movpos %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) + AsmString = "movneg %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) + AsmString = "movvc %icc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) + AsmString = "movvs %icc, $\x02, $\x01"; + break; + } + return NULL; + case SP_MOVXCCri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) + AsmString = "mova %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) + AsmString = "movn %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) + AsmString = "movne %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) + AsmString = "move %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) + AsmString = "movg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) + AsmString = "movle %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) + AsmString = "movge %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) + AsmString = "movl %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) + AsmString = "movgu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) + AsmString = "movleu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) + AsmString = "movcc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) + AsmString = "movcs %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) + AsmString = "movpos %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) + AsmString = "movneg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) + AsmString = "movvc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) + AsmString = "movvs %xcc, $\x02, $\x01"; + break; + } + return NULL; + case SP_MOVXCCrr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) + AsmString = "mova %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) + AsmString = "movn %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) + AsmString = "movne %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) + AsmString = "move %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) + AsmString = "movg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) + AsmString = "movle %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) + AsmString = "movge %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) + AsmString = "movl %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) + AsmString = "movgu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) + AsmString = "movleu %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) + AsmString = "movcc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) + AsmString = "movcs %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) + AsmString = "movpos %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) + AsmString = "movneg %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) + AsmString = "movvc %xcc, $\x02, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) + AsmString = "movvs %xcc, $\x02, $\x01"; + break; + } + return NULL; + case SP_ORri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) { + // (ORri IntRegs:$rd, G0, i32imm:$simm13) + AsmString = "mov $\x03, $\x01"; + break; + } + return NULL; + case SP_ORrr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) { + // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) + AsmString = "mov $\x03, $\x01"; + break; + } + return NULL; + case SP_RESTORErr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) { + // (RESTORErr G0, G0, G0) + AsmString = "restore"; + break; + } + return NULL; + case SP_RET: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { + // (RET 8) + AsmString = "ret"; + break; + } + return NULL; + case SP_RETL: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { + // (RETL 8) + AsmString = "retl"; + break; + } + return NULL; + case SP_TXCCri: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) + AsmString = "ta %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (TXCCri G0, i32imm:$imm, 8) + AsmString = "ta %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) + AsmString = "tn %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TXCCri G0, i32imm:$imm, 0) + AsmString = "tn %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) + AsmString = "tne %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (TXCCri G0, i32imm:$imm, 9) + AsmString = "tne %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) + AsmString = "te %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TXCCri G0, i32imm:$imm, 1) + AsmString = "te %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) + AsmString = "tg %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (TXCCri G0, i32imm:$imm, 10) + AsmString = "tg %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) + AsmString = "tle %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (TXCCri G0, i32imm:$imm, 2) + AsmString = "tle %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) + AsmString = "tge %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (TXCCri G0, i32imm:$imm, 11) + AsmString = "tge %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) + AsmString = "tl %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (TXCCri G0, i32imm:$imm, 3) + AsmString = "tl %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) + AsmString = "tgu %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (TXCCri G0, i32imm:$imm, 12) + AsmString = "tgu %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) + AsmString = "tleu %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (TXCCri G0, i32imm:$imm, 4) + AsmString = "tleu %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) + AsmString = "tcc %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (TXCCri G0, i32imm:$imm, 13) + AsmString = "tcc %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) + AsmString = "tcs %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (TXCCri G0, i32imm:$imm, 5) + AsmString = "tcs %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) + AsmString = "tpos %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (TXCCri G0, i32imm:$imm, 14) + AsmString = "tpos %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) + AsmString = "tneg %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (TXCCri G0, i32imm:$imm, 6) + AsmString = "tneg %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) + AsmString = "tvc %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (TXCCri G0, i32imm:$imm, 15) + AsmString = "tvc %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) + AsmString = "tvs %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (TXCCri G0, i32imm:$imm, 7) + AsmString = "tvs %xcc, $\x02"; + break; + } + return NULL; + case SP_TXCCrr: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) + AsmString = "ta %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + // (TXCCrr G0, IntRegs:$rs2, 8) + AsmString = "ta %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) + AsmString = "tn %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { + // (TXCCrr G0, IntRegs:$rs2, 0) + AsmString = "tn %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) + AsmString = "tne %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { + // (TXCCrr G0, IntRegs:$rs2, 9) + AsmString = "tne %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) + AsmString = "te %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { + // (TXCCrr G0, IntRegs:$rs2, 1) + AsmString = "te %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) + AsmString = "tg %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { + // (TXCCrr G0, IntRegs:$rs2, 10) + AsmString = "tg %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) + AsmString = "tle %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { + // (TXCCrr G0, IntRegs:$rs2, 2) + AsmString = "tle %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) + AsmString = "tge %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { + // (TXCCrr G0, IntRegs:$rs2, 11) + AsmString = "tge %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) + AsmString = "tl %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { + // (TXCCrr G0, IntRegs:$rs2, 3) + AsmString = "tl %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) + AsmString = "tgu %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { + // (TXCCrr G0, IntRegs:$rs2, 12) + AsmString = "tgu %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) + AsmString = "tleu %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { + // (TXCCrr G0, IntRegs:$rs2, 4) + AsmString = "tleu %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) + AsmString = "tcc %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { + // (TXCCrr G0, IntRegs:$rs2, 13) + AsmString = "tcc %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) + AsmString = "tcs %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { + // (TXCCrr G0, IntRegs:$rs2, 5) + AsmString = "tcs %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) + AsmString = "tpos %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { + // (TXCCrr G0, IntRegs:$rs2, 14) + AsmString = "tpos %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) + AsmString = "tneg %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { + // (TXCCrr G0, IntRegs:$rs2, 6) + AsmString = "tneg %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) + AsmString = "tvc %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { + // (TXCCrr G0, IntRegs:$rs2, 15) + AsmString = "tvc %xcc, $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) + AsmString = "tvs %xcc, $\x01 + $\x02"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { + // (TXCCrr G0, IntRegs:$rs2, 7) + AsmString = "tvs %xcc, $\x02"; + break; + } + return NULL; + case SP_V9FCMPD: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { + // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) + AsmString = "fcmpd $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FCMPED: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { + // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) + AsmString = "fcmped $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FCMPEQ: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { + // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) + AsmString = "fcmpeq $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FCMPES: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { + // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) + AsmString = "fcmpes $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FCMPQ: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { + // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) + AsmString = "fcmpq $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FCMPS: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { + // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) + AsmString = "fcmps $\x02, $\x03"; + break; + } + return NULL; + case SP_V9FMOVD_FCC: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) + AsmString = "fmovda $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) + AsmString = "fmovdn $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) + AsmString = "fmovdu $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) + AsmString = "fmovdg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) + AsmString = "fmovdug $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) + AsmString = "fmovdl $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) + AsmString = "fmovdul $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) + AsmString = "fmovdlg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) + AsmString = "fmovdne $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) + AsmString = "fmovde $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) + AsmString = "fmovdue $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) + AsmString = "fmovdge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) + AsmString = "fmovduge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) + AsmString = "fmovdle $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) + AsmString = "fmovdule $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) + AsmString = "fmovdo $\x02, $\x03, $\x01"; + break; + } + return NULL; + case SP_V9FMOVQ_FCC: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) + AsmString = "fmovqa $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) + AsmString = "fmovqn $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) + AsmString = "fmovqu $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) + AsmString = "fmovqg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) + AsmString = "fmovqug $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) + AsmString = "fmovql $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) + AsmString = "fmovqul $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) + AsmString = "fmovqlg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) + AsmString = "fmovqne $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) + AsmString = "fmovqe $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) + AsmString = "fmovque $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) + AsmString = "fmovqge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) + AsmString = "fmovquge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) + AsmString = "fmovqle $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) + AsmString = "fmovqule $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) + AsmString = "fmovqo $\x02, $\x03, $\x01"; + break; + } + return NULL; + case SP_V9FMOVS_FCC: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) + AsmString = "fmovsa $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) + AsmString = "fmovsn $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) + AsmString = "fmovsu $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) + AsmString = "fmovsg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) + AsmString = "fmovsug $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) + AsmString = "fmovsl $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) + AsmString = "fmovsul $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) + AsmString = "fmovslg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) + AsmString = "fmovsne $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) + AsmString = "fmovse $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) + AsmString = "fmovsue $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) + AsmString = "fmovsge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) + AsmString = "fmovsuge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) + AsmString = "fmovsle $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) + AsmString = "fmovsule $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) + AsmString = "fmovso $\x02, $\x03, $\x01"; + break; + } + return NULL; + case SP_V9MOVFCCri: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) + AsmString = "mova $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) + AsmString = "movn $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) + AsmString = "movu $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) + AsmString = "movg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) + AsmString = "movug $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) + AsmString = "movl $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) + AsmString = "movul $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) + AsmString = "movlg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) + AsmString = "movne $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) + AsmString = "move $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) + AsmString = "movue $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) + AsmString = "movge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) + AsmString = "movuge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) + AsmString = "movle $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) + AsmString = "movule $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) + AsmString = "movo $\x02, $\x03, $\x01"; + break; + } + return NULL; + case SP_V9MOVFCCrr: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) + AsmString = "mova $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) + AsmString = "movn $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) + AsmString = "movu $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) + AsmString = "movg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) + AsmString = "movug $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) + AsmString = "movl $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) + AsmString = "movul $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) + AsmString = "movlg $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) + AsmString = "movne $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) + AsmString = "move $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) + AsmString = "movue $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) + AsmString = "movge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) + AsmString = "movuge $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) + AsmString = "movle $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) + AsmString = "movule $\x02, $\x03, $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) + AsmString = "movo $\x02, $\x03, $\x01"; + break; + } + return NULL; + } + + tmp = cs_strdup(AsmString); + AsmMnem = tmp; + for(AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + if (strstr(AsmOps, "icc")) + Sparc_addReg(MI, SPARC_REG_ICC); + if (strstr(AsmOps, "xcc")) + Sparc_addReg(MI, SPARC_REG_XCC); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat(OS, "%c", *c); + } + } + } + return tmp; +} + +#endif // PRINT_ALIAS_INSTR diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcGenDisassemblerTables.inc new file mode 100644 index 0000000..8a69a13 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcGenDisassemblerTables.inc @@ -0,0 +1,2028 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * Sparc Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTableSparc32[] = { +/* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532 +/* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... +/* 10 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 24 +/* 14 */ MCD_OPC_CheckField, 25, 5, 0, 163, 22, // Skip to: 5815 +/* 20 */ MCD_OPC_Decode, 211, 3, 0, // Opcode: UNIMP +/* 24 */ MCD_OPC_FilterValue, 1, 103, 0, // Skip to: 131 +/* 28 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 31 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 60 +/* 35 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 38 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 49 +/* 42 */ MCD_OPC_CheckPredicate, 0, 137, 22, // Skip to: 5815 +/* 46 */ MCD_OPC_Decode, 94, 1, // Opcode: BPICCNT +/* 49 */ MCD_OPC_FilterValue, 1, 130, 22, // Skip to: 5815 +/* 53 */ MCD_OPC_CheckPredicate, 0, 126, 22, // Skip to: 5815 +/* 57 */ MCD_OPC_Decode, 93, 1, // Opcode: BPICCANT +/* 60 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 89 +/* 64 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 67 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 78 +/* 71 */ MCD_OPC_CheckPredicate, 0, 108, 22, // Skip to: 5815 +/* 75 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICC +/* 78 */ MCD_OPC_FilterValue, 1, 101, 22, // Skip to: 5815 +/* 82 */ MCD_OPC_CheckPredicate, 0, 97, 22, // Skip to: 5815 +/* 86 */ MCD_OPC_Decode, 92, 1, // Opcode: BPICCA +/* 89 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 110 +/* 93 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 96 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 103 +/* 100 */ MCD_OPC_Decode, 110, 1, // Opcode: BPXCCNT +/* 103 */ MCD_OPC_FilterValue, 1, 76, 22, // Skip to: 5815 +/* 107 */ MCD_OPC_Decode, 109, 1, // Opcode: BPXCCANT +/* 110 */ MCD_OPC_FilterValue, 5, 69, 22, // Skip to: 5815 +/* 114 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 117 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 124 +/* 121 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCC +/* 124 */ MCD_OPC_FilterValue, 1, 55, 22, // Skip to: 5815 +/* 128 */ MCD_OPC_Decode, 108, 1, // Opcode: BPXCCA +/* 131 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 161 +/* 135 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 138 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 154 +/* 142 */ MCD_OPC_CheckField, 25, 4, 8, 3, 0, // Skip to: 151 +/* 148 */ MCD_OPC_Decode, 73, 0, // Opcode: BA +/* 151 */ MCD_OPC_Decode, 74, 2, // Opcode: BCOND +/* 154 */ MCD_OPC_FilterValue, 1, 25, 22, // Skip to: 5815 +/* 158 */ MCD_OPC_Decode, 75, 2, // Opcode: BCONDA +/* 161 */ MCD_OPC_FilterValue, 3, 255, 0, // Skip to: 420 +/* 165 */ MCD_OPC_ExtractField, 25, 5, // Inst{29-25} ... +/* 168 */ MCD_OPC_FilterValue, 1, 17, 0, // Skip to: 189 +/* 172 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 175 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 182 +/* 179 */ MCD_OPC_Decode, 113, 3, // Opcode: BPZnapn +/* 182 */ MCD_OPC_FilterValue, 1, 253, 21, // Skip to: 5815 +/* 186 */ MCD_OPC_Decode, 114, 3, // Opcode: BPZnapt +/* 189 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 210 +/* 193 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 196 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 203 +/* 200 */ MCD_OPC_Decode, 97, 3, // Opcode: BPLEZnapn +/* 203 */ MCD_OPC_FilterValue, 1, 232, 21, // Skip to: 5815 +/* 207 */ MCD_OPC_Decode, 98, 3, // Opcode: BPLEZnapt +/* 210 */ MCD_OPC_FilterValue, 3, 17, 0, // Skip to: 231 +/* 214 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 217 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 224 +/* 221 */ MCD_OPC_Decode, 101, 3, // Opcode: BPLZnapn +/* 224 */ MCD_OPC_FilterValue, 1, 211, 21, // Skip to: 5815 +/* 228 */ MCD_OPC_Decode, 102, 3, // Opcode: BPLZnapt +/* 231 */ MCD_OPC_FilterValue, 5, 17, 0, // Skip to: 252 +/* 235 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 238 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 245 +/* 242 */ MCD_OPC_Decode, 105, 3, // Opcode: BPNZnapn +/* 245 */ MCD_OPC_FilterValue, 1, 190, 21, // Skip to: 5815 +/* 249 */ MCD_OPC_Decode, 106, 3, // Opcode: BPNZnapt +/* 252 */ MCD_OPC_FilterValue, 6, 17, 0, // Skip to: 273 +/* 256 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 259 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 266 +/* 263 */ MCD_OPC_Decode, 89, 3, // Opcode: BPGZnapn +/* 266 */ MCD_OPC_FilterValue, 1, 169, 21, // Skip to: 5815 +/* 270 */ MCD_OPC_Decode, 90, 3, // Opcode: BPGZnapt +/* 273 */ MCD_OPC_FilterValue, 7, 17, 0, // Skip to: 294 +/* 277 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 280 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 287 +/* 284 */ MCD_OPC_Decode, 85, 3, // Opcode: BPGEZnapn +/* 287 */ MCD_OPC_FilterValue, 1, 148, 21, // Skip to: 5815 +/* 291 */ MCD_OPC_Decode, 86, 3, // Opcode: BPGEZnapt +/* 294 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 315 +/* 298 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 301 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 308 +/* 305 */ MCD_OPC_Decode, 111, 3, // Opcode: BPZapn +/* 308 */ MCD_OPC_FilterValue, 1, 127, 21, // Skip to: 5815 +/* 312 */ MCD_OPC_Decode, 112, 3, // Opcode: BPZapt +/* 315 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 336 +/* 319 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 322 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 329 +/* 326 */ MCD_OPC_Decode, 95, 3, // Opcode: BPLEZapn +/* 329 */ MCD_OPC_FilterValue, 1, 106, 21, // Skip to: 5815 +/* 333 */ MCD_OPC_Decode, 96, 3, // Opcode: BPLEZapt +/* 336 */ MCD_OPC_FilterValue, 19, 17, 0, // Skip to: 357 +/* 340 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 343 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 350 +/* 347 */ MCD_OPC_Decode, 99, 3, // Opcode: BPLZapn +/* 350 */ MCD_OPC_FilterValue, 1, 85, 21, // Skip to: 5815 +/* 354 */ MCD_OPC_Decode, 100, 3, // Opcode: BPLZapt +/* 357 */ MCD_OPC_FilterValue, 21, 17, 0, // Skip to: 378 +/* 361 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 364 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 371 +/* 368 */ MCD_OPC_Decode, 103, 3, // Opcode: BPNZapn +/* 371 */ MCD_OPC_FilterValue, 1, 64, 21, // Skip to: 5815 +/* 375 */ MCD_OPC_Decode, 104, 3, // Opcode: BPNZapt +/* 378 */ MCD_OPC_FilterValue, 22, 17, 0, // Skip to: 399 +/* 382 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 385 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 392 +/* 389 */ MCD_OPC_Decode, 87, 3, // Opcode: BPGZapn +/* 392 */ MCD_OPC_FilterValue, 1, 43, 21, // Skip to: 5815 +/* 396 */ MCD_OPC_Decode, 88, 3, // Opcode: BPGZapt +/* 399 */ MCD_OPC_FilterValue, 23, 36, 21, // Skip to: 5815 +/* 403 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 406 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 413 +/* 410 */ MCD_OPC_Decode, 83, 3, // Opcode: BPGEZapn +/* 413 */ MCD_OPC_FilterValue, 1, 22, 21, // Skip to: 5815 +/* 417 */ MCD_OPC_Decode, 84, 3, // Opcode: BPGEZapt +/* 420 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 444 +/* 424 */ MCD_OPC_CheckField, 25, 5, 0, 10, 0, // Skip to: 440 +/* 430 */ MCD_OPC_CheckField, 0, 22, 0, 4, 0, // Skip to: 440 +/* 436 */ MCD_OPC_Decode, 224, 2, 4, // Opcode: NOP +/* 440 */ MCD_OPC_Decode, 135, 3, 5, // Opcode: SETHIi +/* 444 */ MCD_OPC_FilterValue, 5, 61, 0, // Skip to: 509 +/* 448 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 451 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 480 +/* 455 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 458 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 469 +/* 462 */ MCD_OPC_CheckPredicate, 0, 229, 20, // Skip to: 5815 +/* 466 */ MCD_OPC_Decode, 82, 6, // Opcode: BPFCCNT +/* 469 */ MCD_OPC_FilterValue, 1, 222, 20, // Skip to: 5815 +/* 473 */ MCD_OPC_CheckPredicate, 0, 218, 20, // Skip to: 5815 +/* 477 */ MCD_OPC_Decode, 81, 6, // Opcode: BPFCCANT +/* 480 */ MCD_OPC_FilterValue, 1, 211, 20, // Skip to: 5815 +/* 484 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 487 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 498 +/* 491 */ MCD_OPC_CheckPredicate, 0, 200, 20, // Skip to: 5815 +/* 495 */ MCD_OPC_Decode, 79, 6, // Opcode: BPFCC +/* 498 */ MCD_OPC_FilterValue, 1, 193, 20, // Skip to: 5815 +/* 502 */ MCD_OPC_CheckPredicate, 0, 189, 20, // Skip to: 5815 +/* 506 */ MCD_OPC_Decode, 80, 6, // Opcode: BPFCCA +/* 509 */ MCD_OPC_FilterValue, 6, 182, 20, // Skip to: 5815 +/* 513 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 516 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 524 +/* 520 */ MCD_OPC_Decode, 151, 1, 2, // Opcode: FBCOND +/* 524 */ MCD_OPC_FilterValue, 1, 167, 20, // Skip to: 5815 +/* 528 */ MCD_OPC_Decode, 152, 1, 2, // Opcode: FBCONDA +/* 532 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 539 +/* 536 */ MCD_OPC_Decode, 116, 7, // Opcode: CALL +/* 539 */ MCD_OPC_FilterValue, 2, 87, 18, // Skip to: 5238 +/* 543 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... +/* 546 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 573 +/* 550 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 553 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 566 +/* 557 */ MCD_OPC_CheckField, 5, 8, 0, 132, 20, // Skip to: 5815 +/* 563 */ MCD_OPC_Decode, 33, 8, // Opcode: ADDrr +/* 566 */ MCD_OPC_FilterValue, 1, 125, 20, // Skip to: 5815 +/* 570 */ MCD_OPC_Decode, 32, 9, // Opcode: ADDri +/* 573 */ MCD_OPC_FilterValue, 1, 23, 0, // Skip to: 600 +/* 577 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 580 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 593 +/* 584 */ MCD_OPC_CheckField, 5, 8, 0, 105, 20, // Skip to: 5815 +/* 590 */ MCD_OPC_Decode, 48, 8, // Opcode: ANDrr +/* 593 */ MCD_OPC_FilterValue, 1, 98, 20, // Skip to: 5815 +/* 597 */ MCD_OPC_Decode, 47, 9, // Opcode: ANDri +/* 600 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 629 +/* 604 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 607 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 621 +/* 611 */ MCD_OPC_CheckField, 5, 8, 0, 78, 20, // Skip to: 5815 +/* 617 */ MCD_OPC_Decode, 235, 2, 8, // Opcode: ORrr +/* 621 */ MCD_OPC_FilterValue, 1, 70, 20, // Skip to: 5815 +/* 625 */ MCD_OPC_Decode, 234, 2, 9, // Opcode: ORri +/* 629 */ MCD_OPC_FilterValue, 3, 25, 0, // Skip to: 658 +/* 633 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 650 +/* 640 */ MCD_OPC_CheckField, 5, 8, 0, 49, 20, // Skip to: 5815 +/* 646 */ MCD_OPC_Decode, 237, 3, 8, // Opcode: XORrr +/* 650 */ MCD_OPC_FilterValue, 1, 41, 20, // Skip to: 5815 +/* 654 */ MCD_OPC_Decode, 236, 3, 9, // Opcode: XORri +/* 658 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 687 +/* 662 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 665 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 679 +/* 669 */ MCD_OPC_CheckField, 5, 8, 0, 20, 20, // Skip to: 5815 +/* 675 */ MCD_OPC_Decode, 178, 3, 8, // Opcode: SUBrr +/* 679 */ MCD_OPC_FilterValue, 1, 12, 20, // Skip to: 5815 +/* 683 */ MCD_OPC_Decode, 177, 3, 9, // Opcode: SUBri +/* 687 */ MCD_OPC_FilterValue, 5, 23, 0, // Skip to: 714 +/* 691 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 694 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 707 +/* 698 */ MCD_OPC_CheckField, 5, 8, 0, 247, 19, // Skip to: 5815 +/* 704 */ MCD_OPC_Decode, 43, 8, // Opcode: ANDNrr +/* 707 */ MCD_OPC_FilterValue, 1, 240, 19, // Skip to: 5815 +/* 711 */ MCD_OPC_Decode, 42, 9, // Opcode: ANDNri +/* 714 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 743 +/* 718 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 721 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 735 +/* 725 */ MCD_OPC_CheckField, 5, 8, 0, 220, 19, // Skip to: 5815 +/* 731 */ MCD_OPC_Decode, 230, 2, 8, // Opcode: ORNrr +/* 735 */ MCD_OPC_FilterValue, 1, 212, 19, // Skip to: 5815 +/* 739 */ MCD_OPC_Decode, 229, 2, 9, // Opcode: ORNri +/* 743 */ MCD_OPC_FilterValue, 7, 25, 0, // Skip to: 772 +/* 747 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 750 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 764 +/* 754 */ MCD_OPC_CheckField, 5, 8, 0, 191, 19, // Skip to: 5815 +/* 760 */ MCD_OPC_Decode, 231, 3, 8, // Opcode: XNORrr +/* 764 */ MCD_OPC_FilterValue, 1, 183, 19, // Skip to: 5815 +/* 768 */ MCD_OPC_Decode, 230, 3, 9, // Opcode: XNORri +/* 772 */ MCD_OPC_FilterValue, 8, 23, 0, // Skip to: 799 +/* 776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 779 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 792 +/* 783 */ MCD_OPC_CheckField, 5, 8, 0, 162, 19, // Skip to: 5815 +/* 789 */ MCD_OPC_Decode, 25, 8, // Opcode: ADDCrr +/* 792 */ MCD_OPC_FilterValue, 1, 155, 19, // Skip to: 5815 +/* 796 */ MCD_OPC_Decode, 24, 9, // Opcode: ADDCri +/* 799 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 828 +/* 803 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 806 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 820 +/* 810 */ MCD_OPC_CheckField, 5, 8, 0, 135, 19, // Skip to: 5815 +/* 816 */ MCD_OPC_Decode, 223, 2, 10, // Opcode: MULXrr +/* 820 */ MCD_OPC_FilterValue, 1, 127, 19, // Skip to: 5815 +/* 824 */ MCD_OPC_Decode, 222, 2, 11, // Opcode: MULXri +/* 828 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 857 +/* 832 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 835 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 849 +/* 839 */ MCD_OPC_CheckField, 5, 8, 0, 106, 19, // Skip to: 5815 +/* 845 */ MCD_OPC_Decode, 210, 3, 8, // Opcode: UMULrr +/* 849 */ MCD_OPC_FilterValue, 1, 98, 19, // Skip to: 5815 +/* 853 */ MCD_OPC_Decode, 209, 3, 9, // Opcode: UMULri +/* 857 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 886 +/* 861 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 864 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 878 +/* 868 */ MCD_OPC_CheckField, 5, 8, 0, 77, 19, // Skip to: 5815 +/* 874 */ MCD_OPC_Decode, 145, 3, 8, // Opcode: SMULrr +/* 878 */ MCD_OPC_FilterValue, 1, 69, 19, // Skip to: 5815 +/* 882 */ MCD_OPC_Decode, 144, 3, 9, // Opcode: SMULri +/* 886 */ MCD_OPC_FilterValue, 12, 25, 0, // Skip to: 915 +/* 890 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 893 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 907 +/* 897 */ MCD_OPC_CheckField, 5, 8, 0, 48, 19, // Skip to: 5815 +/* 903 */ MCD_OPC_Decode, 172, 3, 8, // Opcode: SUBCrr +/* 907 */ MCD_OPC_FilterValue, 1, 40, 19, // Skip to: 5815 +/* 911 */ MCD_OPC_Decode, 171, 3, 9, // Opcode: SUBCri +/* 915 */ MCD_OPC_FilterValue, 13, 25, 0, // Skip to: 944 +/* 919 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 922 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 936 +/* 926 */ MCD_OPC_CheckField, 5, 8, 0, 19, 19, // Skip to: 5815 +/* 932 */ MCD_OPC_Decode, 203, 3, 10, // Opcode: UDIVXrr +/* 936 */ MCD_OPC_FilterValue, 1, 11, 19, // Skip to: 5815 +/* 940 */ MCD_OPC_Decode, 202, 3, 11, // Opcode: UDIVXri +/* 944 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 973 +/* 948 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 951 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 965 +/* 955 */ MCD_OPC_CheckField, 5, 8, 0, 246, 18, // Skip to: 5815 +/* 961 */ MCD_OPC_Decode, 205, 3, 8, // Opcode: UDIVrr +/* 965 */ MCD_OPC_FilterValue, 1, 238, 18, // Skip to: 5815 +/* 969 */ MCD_OPC_Decode, 204, 3, 9, // Opcode: UDIVri +/* 973 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 1002 +/* 977 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 980 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 994 +/* 984 */ MCD_OPC_CheckField, 5, 8, 0, 217, 18, // Skip to: 5815 +/* 990 */ MCD_OPC_Decode, 253, 2, 8, // Opcode: SDIVrr +/* 994 */ MCD_OPC_FilterValue, 1, 209, 18, // Skip to: 5815 +/* 998 */ MCD_OPC_Decode, 252, 2, 9, // Opcode: SDIVri +/* 1002 */ MCD_OPC_FilterValue, 16, 23, 0, // Skip to: 1029 +/* 1006 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1009 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1022 +/* 1013 */ MCD_OPC_CheckField, 5, 8, 0, 188, 18, // Skip to: 5815 +/* 1019 */ MCD_OPC_Decode, 23, 8, // Opcode: ADDCCrr +/* 1022 */ MCD_OPC_FilterValue, 1, 181, 18, // Skip to: 5815 +/* 1026 */ MCD_OPC_Decode, 22, 9, // Opcode: ADDCCri +/* 1029 */ MCD_OPC_FilterValue, 17, 23, 0, // Skip to: 1056 +/* 1033 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1036 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1049 +/* 1040 */ MCD_OPC_CheckField, 5, 8, 0, 161, 18, // Skip to: 5815 +/* 1046 */ MCD_OPC_Decode, 39, 8, // Opcode: ANDCCrr +/* 1049 */ MCD_OPC_FilterValue, 1, 154, 18, // Skip to: 5815 +/* 1053 */ MCD_OPC_Decode, 38, 9, // Opcode: ANDCCri +/* 1056 */ MCD_OPC_FilterValue, 18, 25, 0, // Skip to: 1085 +/* 1060 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1063 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1077 +/* 1067 */ MCD_OPC_CheckField, 5, 8, 0, 134, 18, // Skip to: 5815 +/* 1073 */ MCD_OPC_Decode, 226, 2, 8, // Opcode: ORCCrr +/* 1077 */ MCD_OPC_FilterValue, 1, 126, 18, // Skip to: 5815 +/* 1081 */ MCD_OPC_Decode, 225, 2, 9, // Opcode: ORCCri +/* 1085 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 1114 +/* 1089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1092 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1106 +/* 1096 */ MCD_OPC_CheckField, 5, 8, 0, 105, 18, // Skip to: 5815 +/* 1102 */ MCD_OPC_Decode, 233, 3, 8, // Opcode: XORCCrr +/* 1106 */ MCD_OPC_FilterValue, 1, 97, 18, // Skip to: 5815 +/* 1110 */ MCD_OPC_Decode, 232, 3, 9, // Opcode: XORCCri +/* 1114 */ MCD_OPC_FilterValue, 20, 44, 0, // Skip to: 1162 +/* 1118 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1121 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1145 +/* 1125 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... +/* 1128 */ MCD_OPC_FilterValue, 0, 75, 18, // Skip to: 5815 +/* 1132 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1141 +/* 1138 */ MCD_OPC_Decode, 125, 12, // Opcode: CMPrr +/* 1141 */ MCD_OPC_Decode, 170, 3, 8, // Opcode: SUBCCrr +/* 1145 */ MCD_OPC_FilterValue, 1, 58, 18, // Skip to: 5815 +/* 1149 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1158 +/* 1155 */ MCD_OPC_Decode, 124, 13, // Opcode: CMPri +/* 1158 */ MCD_OPC_Decode, 169, 3, 9, // Opcode: SUBCCri +/* 1162 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1189 +/* 1166 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1169 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1182 +/* 1173 */ MCD_OPC_CheckField, 5, 8, 0, 28, 18, // Skip to: 5815 +/* 1179 */ MCD_OPC_Decode, 41, 8, // Opcode: ANDNCCrr +/* 1182 */ MCD_OPC_FilterValue, 1, 21, 18, // Skip to: 5815 +/* 1186 */ MCD_OPC_Decode, 40, 9, // Opcode: ANDNCCri +/* 1189 */ MCD_OPC_FilterValue, 22, 25, 0, // Skip to: 1218 +/* 1193 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1196 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1210 +/* 1200 */ MCD_OPC_CheckField, 5, 8, 0, 1, 18, // Skip to: 5815 +/* 1206 */ MCD_OPC_Decode, 228, 2, 8, // Opcode: ORNCCrr +/* 1210 */ MCD_OPC_FilterValue, 1, 249, 17, // Skip to: 5815 +/* 1214 */ MCD_OPC_Decode, 227, 2, 9, // Opcode: ORNCCri +/* 1218 */ MCD_OPC_FilterValue, 23, 25, 0, // Skip to: 1247 +/* 1222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1225 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1239 +/* 1229 */ MCD_OPC_CheckField, 5, 8, 0, 228, 17, // Skip to: 5815 +/* 1235 */ MCD_OPC_Decode, 228, 3, 8, // Opcode: XNORCCrr +/* 1239 */ MCD_OPC_FilterValue, 1, 220, 17, // Skip to: 5815 +/* 1243 */ MCD_OPC_Decode, 227, 3, 9, // Opcode: XNORCCri +/* 1247 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1274 +/* 1251 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1254 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1267 +/* 1258 */ MCD_OPC_CheckField, 5, 8, 0, 199, 17, // Skip to: 5815 +/* 1264 */ MCD_OPC_Decode, 27, 8, // Opcode: ADDErr +/* 1267 */ MCD_OPC_FilterValue, 1, 192, 17, // Skip to: 5815 +/* 1271 */ MCD_OPC_Decode, 26, 9, // Opcode: ADDEri +/* 1274 */ MCD_OPC_FilterValue, 26, 25, 0, // Skip to: 1303 +/* 1278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1295 +/* 1285 */ MCD_OPC_CheckField, 5, 8, 0, 172, 17, // Skip to: 5815 +/* 1291 */ MCD_OPC_Decode, 207, 3, 8, // Opcode: UMULCCrr +/* 1295 */ MCD_OPC_FilterValue, 1, 164, 17, // Skip to: 5815 +/* 1299 */ MCD_OPC_Decode, 206, 3, 9, // Opcode: UMULCCri +/* 1303 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 1332 +/* 1307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1324 +/* 1314 */ MCD_OPC_CheckField, 5, 8, 0, 143, 17, // Skip to: 5815 +/* 1320 */ MCD_OPC_Decode, 143, 3, 8, // Opcode: SMULCCrr +/* 1324 */ MCD_OPC_FilterValue, 1, 135, 17, // Skip to: 5815 +/* 1328 */ MCD_OPC_Decode, 142, 3, 9, // Opcode: SMULCCri +/* 1332 */ MCD_OPC_FilterValue, 28, 25, 0, // Skip to: 1361 +/* 1336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1353 +/* 1343 */ MCD_OPC_CheckField, 5, 8, 0, 114, 17, // Skip to: 5815 +/* 1349 */ MCD_OPC_Decode, 174, 3, 8, // Opcode: SUBErr +/* 1353 */ MCD_OPC_FilterValue, 1, 106, 17, // Skip to: 5815 +/* 1357 */ MCD_OPC_Decode, 173, 3, 9, // Opcode: SUBEri +/* 1361 */ MCD_OPC_FilterValue, 30, 25, 0, // Skip to: 1390 +/* 1365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1382 +/* 1372 */ MCD_OPC_CheckField, 5, 8, 0, 85, 17, // Skip to: 5815 +/* 1378 */ MCD_OPC_Decode, 201, 3, 8, // Opcode: UDIVCCrr +/* 1382 */ MCD_OPC_FilterValue, 1, 77, 17, // Skip to: 5815 +/* 1386 */ MCD_OPC_Decode, 200, 3, 9, // Opcode: UDIVCCri +/* 1390 */ MCD_OPC_FilterValue, 31, 25, 0, // Skip to: 1419 +/* 1394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1411 +/* 1401 */ MCD_OPC_CheckField, 5, 8, 0, 56, 17, // Skip to: 5815 +/* 1407 */ MCD_OPC_Decode, 249, 2, 8, // Opcode: SDIVCCrr +/* 1411 */ MCD_OPC_FilterValue, 1, 48, 17, // Skip to: 5815 +/* 1415 */ MCD_OPC_Decode, 248, 2, 9, // Opcode: SDIVCCri +/* 1419 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 1448 +/* 1423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1440 +/* 1430 */ MCD_OPC_CheckField, 5, 8, 0, 27, 17, // Skip to: 5815 +/* 1436 */ MCD_OPC_Decode, 186, 3, 8, // Opcode: TADDCCrr +/* 1440 */ MCD_OPC_FilterValue, 1, 19, 17, // Skip to: 5815 +/* 1444 */ MCD_OPC_Decode, 185, 3, 9, // Opcode: TADDCCri +/* 1448 */ MCD_OPC_FilterValue, 33, 25, 0, // Skip to: 1477 +/* 1452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1469 +/* 1459 */ MCD_OPC_CheckField, 5, 8, 0, 254, 16, // Skip to: 5815 +/* 1465 */ MCD_OPC_Decode, 197, 3, 8, // Opcode: TSUBCCrr +/* 1469 */ MCD_OPC_FilterValue, 1, 246, 16, // Skip to: 5815 +/* 1473 */ MCD_OPC_Decode, 196, 3, 9, // Opcode: TSUBCCri +/* 1477 */ MCD_OPC_FilterValue, 34, 25, 0, // Skip to: 1506 +/* 1481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1498 +/* 1488 */ MCD_OPC_CheckField, 5, 8, 0, 225, 16, // Skip to: 5815 +/* 1494 */ MCD_OPC_Decode, 184, 3, 8, // Opcode: TADDCCTVrr +/* 1498 */ MCD_OPC_FilterValue, 1, 217, 16, // Skip to: 5815 +/* 1502 */ MCD_OPC_Decode, 183, 3, 9, // Opcode: TADDCCTVri +/* 1506 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 1535 +/* 1510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1527 +/* 1517 */ MCD_OPC_CheckField, 5, 8, 0, 196, 16, // Skip to: 5815 +/* 1523 */ MCD_OPC_Decode, 195, 3, 8, // Opcode: TSUBCCTVrr +/* 1527 */ MCD_OPC_FilterValue, 1, 188, 16, // Skip to: 5815 +/* 1531 */ MCD_OPC_Decode, 194, 3, 9, // Opcode: TSUBCCTVri +/* 1535 */ MCD_OPC_FilterValue, 37, 50, 0, // Skip to: 1589 +/* 1539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1542 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1571 +/* 1546 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1549 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1563 +/* 1553 */ MCD_OPC_CheckField, 5, 7, 0, 160, 16, // Skip to: 5815 +/* 1559 */ MCD_OPC_Decode, 141, 3, 8, // Opcode: SLLrr +/* 1563 */ MCD_OPC_FilterValue, 1, 152, 16, // Skip to: 5815 +/* 1567 */ MCD_OPC_Decode, 139, 3, 14, // Opcode: SLLXrr +/* 1571 */ MCD_OPC_FilterValue, 1, 144, 16, // Skip to: 5815 +/* 1575 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1585 +/* 1581 */ MCD_OPC_Decode, 138, 3, 15, // Opcode: SLLXri +/* 1585 */ MCD_OPC_Decode, 140, 3, 9, // Opcode: SLLri +/* 1589 */ MCD_OPC_FilterValue, 38, 50, 0, // Skip to: 1643 +/* 1593 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1596 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1625 +/* 1600 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1603 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1617 +/* 1607 */ MCD_OPC_CheckField, 5, 7, 0, 106, 16, // Skip to: 5815 +/* 1613 */ MCD_OPC_Decode, 153, 3, 8, // Opcode: SRLrr +/* 1617 */ MCD_OPC_FilterValue, 1, 98, 16, // Skip to: 5815 +/* 1621 */ MCD_OPC_Decode, 151, 3, 14, // Opcode: SRLXrr +/* 1625 */ MCD_OPC_FilterValue, 1, 90, 16, // Skip to: 5815 +/* 1629 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1639 +/* 1635 */ MCD_OPC_Decode, 150, 3, 15, // Opcode: SRLXri +/* 1639 */ MCD_OPC_Decode, 152, 3, 9, // Opcode: SRLri +/* 1643 */ MCD_OPC_FilterValue, 39, 50, 0, // Skip to: 1697 +/* 1647 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1650 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1679 +/* 1654 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 1657 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1671 +/* 1661 */ MCD_OPC_CheckField, 5, 7, 0, 52, 16, // Skip to: 5815 +/* 1667 */ MCD_OPC_Decode, 149, 3, 8, // Opcode: SRArr +/* 1671 */ MCD_OPC_FilterValue, 1, 44, 16, // Skip to: 5815 +/* 1675 */ MCD_OPC_Decode, 147, 3, 14, // Opcode: SRAXrr +/* 1679 */ MCD_OPC_FilterValue, 1, 36, 16, // Skip to: 5815 +/* 1683 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1693 +/* 1689 */ MCD_OPC_Decode, 146, 3, 15, // Opcode: SRAXri +/* 1693 */ MCD_OPC_Decode, 148, 3, 9, // Opcode: SRAri +/* 1697 */ MCD_OPC_FilterValue, 40, 55, 0, // Skip to: 1756 +/* 1701 */ MCD_OPC_ExtractField, 13, 6, // Inst{18-13} ... +/* 1704 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1718 +/* 1708 */ MCD_OPC_CheckField, 0, 13, 0, 5, 16, // Skip to: 5815 +/* 1714 */ MCD_OPC_Decode, 239, 2, 4, // Opcode: RDY +/* 1718 */ MCD_OPC_FilterValue, 30, 16, 0, // Skip to: 1738 +/* 1722 */ MCD_OPC_CheckField, 25, 5, 0, 247, 15, // Skip to: 5815 +/* 1728 */ MCD_OPC_CheckField, 0, 13, 0, 241, 15, // Skip to: 5815 +/* 1734 */ MCD_OPC_Decode, 154, 3, 4, // Opcode: STBAR +/* 1738 */ MCD_OPC_FilterValue, 31, 233, 15, // Skip to: 5815 +/* 1742 */ MCD_OPC_CheckPredicate, 0, 229, 15, // Skip to: 5815 +/* 1746 */ MCD_OPC_CheckField, 25, 5, 0, 223, 15, // Skip to: 5815 +/* 1752 */ MCD_OPC_Decode, 198, 2, 16, // Opcode: MEMBARi +/* 1756 */ MCD_OPC_FilterValue, 43, 20, 0, // Skip to: 1780 +/* 1760 */ MCD_OPC_CheckPredicate, 0, 211, 15, // Skip to: 5815 +/* 1764 */ MCD_OPC_CheckField, 25, 5, 0, 205, 15, // Skip to: 5815 +/* 1770 */ MCD_OPC_CheckField, 0, 19, 0, 199, 15, // Skip to: 5815 +/* 1776 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: FLUSHW +/* 1780 */ MCD_OPC_FilterValue, 44, 123, 0, // Skip to: 1907 +/* 1784 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1787 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 1847 +/* 1791 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 1794 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1820 +/* 1798 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1812 +/* 1802 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1812 +/* 1808 */ MCD_OPC_Decode, 201, 2, 17, // Opcode: MOVFCCrr +/* 1812 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 5815 +/* 1816 */ MCD_OPC_Decode, 222, 3, 18, // Opcode: V9MOVFCCrr +/* 1820 */ MCD_OPC_FilterValue, 1, 151, 15, // Skip to: 5815 +/* 1824 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1839 +/* 1831 */ MCD_OPC_CheckPredicate, 0, 140, 15, // Skip to: 5815 +/* 1835 */ MCD_OPC_Decode, 203, 2, 17, // Opcode: MOVICCrr +/* 1839 */ MCD_OPC_FilterValue, 2, 132, 15, // Skip to: 5815 +/* 1843 */ MCD_OPC_Decode, 220, 2, 17, // Opcode: MOVXCCrr +/* 1847 */ MCD_OPC_FilterValue, 1, 124, 15, // Skip to: 5815 +/* 1851 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 1854 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1880 +/* 1858 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1872 +/* 1862 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1872 +/* 1868 */ MCD_OPC_Decode, 200, 2, 19, // Opcode: MOVFCCri +/* 1872 */ MCD_OPC_CheckPredicate, 0, 99, 15, // Skip to: 5815 +/* 1876 */ MCD_OPC_Decode, 221, 3, 20, // Opcode: V9MOVFCCri +/* 1880 */ MCD_OPC_FilterValue, 1, 91, 15, // Skip to: 5815 +/* 1884 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 1887 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1899 +/* 1891 */ MCD_OPC_CheckPredicate, 0, 80, 15, // Skip to: 5815 +/* 1895 */ MCD_OPC_Decode, 202, 2, 19, // Opcode: MOVICCri +/* 1899 */ MCD_OPC_FilterValue, 2, 72, 15, // Skip to: 5815 +/* 1903 */ MCD_OPC_Decode, 219, 2, 19, // Opcode: MOVXCCri +/* 1907 */ MCD_OPC_FilterValue, 45, 25, 0, // Skip to: 1936 +/* 1911 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 1914 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1928 +/* 1918 */ MCD_OPC_CheckField, 5, 8, 0, 51, 15, // Skip to: 5815 +/* 1924 */ MCD_OPC_Decode, 251, 2, 10, // Opcode: SDIVXrr +/* 1928 */ MCD_OPC_FilterValue, 1, 43, 15, // Skip to: 5815 +/* 1932 */ MCD_OPC_Decode, 250, 2, 11, // Opcode: SDIVXri +/* 1936 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 1954 +/* 1940 */ MCD_OPC_CheckPredicate, 0, 31, 15, // Skip to: 5815 +/* 1944 */ MCD_OPC_CheckField, 5, 14, 0, 25, 15, // Skip to: 5815 +/* 1950 */ MCD_OPC_Decode, 238, 2, 21, // Opcode: POPCrr +/* 1954 */ MCD_OPC_FilterValue, 47, 135, 0, // Skip to: 2093 +/* 1958 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 1961 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 1975 +/* 1965 */ MCD_OPC_CheckField, 5, 5, 0, 4, 15, // Skip to: 5815 +/* 1971 */ MCD_OPC_Decode, 215, 2, 14, // Opcode: MOVRRZrr +/* 1975 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 1989 +/* 1979 */ MCD_OPC_CheckField, 5, 5, 0, 246, 14, // Skip to: 5815 +/* 1985 */ MCD_OPC_Decode, 209, 2, 14, // Opcode: MOVRLEZrr +/* 1989 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2003 +/* 1993 */ MCD_OPC_CheckField, 5, 5, 0, 232, 14, // Skip to: 5815 +/* 1999 */ MCD_OPC_Decode, 211, 2, 14, // Opcode: MOVRLZrr +/* 2003 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2017 +/* 2007 */ MCD_OPC_CheckField, 5, 5, 0, 218, 14, // Skip to: 5815 +/* 2013 */ MCD_OPC_Decode, 213, 2, 14, // Opcode: MOVRNZrr +/* 2017 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2031 +/* 2021 */ MCD_OPC_CheckField, 5, 5, 0, 204, 14, // Skip to: 5815 +/* 2027 */ MCD_OPC_Decode, 207, 2, 14, // Opcode: MOVRGZrr +/* 2031 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2045 +/* 2035 */ MCD_OPC_CheckField, 5, 5, 0, 190, 14, // Skip to: 5815 +/* 2041 */ MCD_OPC_Decode, 205, 2, 14, // Opcode: MOVRGEZrr +/* 2045 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2053 +/* 2049 */ MCD_OPC_Decode, 214, 2, 22, // Opcode: MOVRRZri +/* 2053 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 2061 +/* 2057 */ MCD_OPC_Decode, 208, 2, 22, // Opcode: MOVRLEZri +/* 2061 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2069 +/* 2065 */ MCD_OPC_Decode, 210, 2, 22, // Opcode: MOVRLZri +/* 2069 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2077 +/* 2073 */ MCD_OPC_Decode, 212, 2, 22, // Opcode: MOVRNZri +/* 2077 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 2085 +/* 2081 */ MCD_OPC_Decode, 206, 2, 22, // Opcode: MOVRGZri +/* 2085 */ MCD_OPC_FilterValue, 15, 142, 14, // Skip to: 5815 +/* 2089 */ MCD_OPC_Decode, 204, 2, 22, // Opcode: MOVRGEZri +/* 2093 */ MCD_OPC_FilterValue, 48, 37, 0, // Skip to: 2134 +/* 2097 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2100 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 2120 +/* 2104 */ MCD_OPC_CheckField, 25, 5, 0, 121, 14, // Skip to: 5815 +/* 2110 */ MCD_OPC_CheckField, 5, 8, 0, 115, 14, // Skip to: 5815 +/* 2116 */ MCD_OPC_Decode, 224, 3, 12, // Opcode: WRYrr +/* 2120 */ MCD_OPC_FilterValue, 1, 107, 14, // Skip to: 5815 +/* 2124 */ MCD_OPC_CheckField, 25, 5, 0, 101, 14, // Skip to: 5815 +/* 2130 */ MCD_OPC_Decode, 223, 3, 13, // Opcode: WRYri +/* 2134 */ MCD_OPC_FilterValue, 52, 197, 2, // Skip to: 2847 +/* 2138 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... +/* 2141 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2155 +/* 2145 */ MCD_OPC_CheckField, 14, 5, 0, 80, 14, // Skip to: 5815 +/* 2151 */ MCD_OPC_Decode, 211, 1, 23, // Opcode: FMOVS +/* 2155 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2173 +/* 2159 */ MCD_OPC_CheckPredicate, 0, 68, 14, // Skip to: 5815 +/* 2163 */ MCD_OPC_CheckField, 14, 5, 0, 62, 14, // Skip to: 5815 +/* 2169 */ MCD_OPC_Decode, 185, 1, 24, // Opcode: FMOVD +/* 2173 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2191 +/* 2177 */ MCD_OPC_CheckPredicate, 0, 50, 14, // Skip to: 5815 +/* 2181 */ MCD_OPC_CheckField, 14, 5, 0, 44, 14, // Skip to: 5815 +/* 2187 */ MCD_OPC_Decode, 189, 1, 25, // Opcode: FMOVQ +/* 2191 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2205 +/* 2195 */ MCD_OPC_CheckField, 14, 5, 0, 30, 14, // Skip to: 5815 +/* 2201 */ MCD_OPC_Decode, 231, 1, 23, // Opcode: FNEGS +/* 2205 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2223 +/* 2209 */ MCD_OPC_CheckPredicate, 0, 18, 14, // Skip to: 5815 +/* 2213 */ MCD_OPC_CheckField, 14, 5, 0, 12, 14, // Skip to: 5815 +/* 2219 */ MCD_OPC_Decode, 229, 1, 24, // Opcode: FNEGD +/* 2223 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2241 +/* 2227 */ MCD_OPC_CheckPredicate, 0, 0, 14, // Skip to: 5815 +/* 2231 */ MCD_OPC_CheckField, 14, 5, 0, 250, 13, // Skip to: 5815 +/* 2237 */ MCD_OPC_Decode, 230, 1, 25, // Opcode: FNEGQ +/* 2241 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2255 +/* 2245 */ MCD_OPC_CheckField, 14, 5, 0, 236, 13, // Skip to: 5815 +/* 2251 */ MCD_OPC_Decode, 140, 1, 23, // Opcode: FABSS +/* 2255 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2273 +/* 2259 */ MCD_OPC_CheckPredicate, 0, 224, 13, // Skip to: 5815 +/* 2263 */ MCD_OPC_CheckField, 14, 5, 0, 218, 13, // Skip to: 5815 +/* 2269 */ MCD_OPC_Decode, 138, 1, 24, // Opcode: FABSD +/* 2273 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2291 +/* 2277 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 5815 +/* 2281 */ MCD_OPC_CheckField, 14, 5, 0, 200, 13, // Skip to: 5815 +/* 2287 */ MCD_OPC_Decode, 139, 1, 25, // Opcode: FABSQ +/* 2291 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 2305 +/* 2295 */ MCD_OPC_CheckField, 14, 5, 0, 186, 13, // Skip to: 5815 +/* 2301 */ MCD_OPC_Decode, 147, 2, 23, // Opcode: FSQRTS +/* 2305 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 2319 +/* 2309 */ MCD_OPC_CheckField, 14, 5, 0, 172, 13, // Skip to: 5815 +/* 2315 */ MCD_OPC_Decode, 145, 2, 24, // Opcode: FSQRTD +/* 2319 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 2333 +/* 2323 */ MCD_OPC_CheckField, 14, 5, 0, 158, 13, // Skip to: 5815 +/* 2329 */ MCD_OPC_Decode, 146, 2, 25, // Opcode: FSQRTQ +/* 2333 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 2341 +/* 2337 */ MCD_OPC_Decode, 143, 1, 26, // Opcode: FADDS +/* 2341 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 2349 +/* 2345 */ MCD_OPC_Decode, 141, 1, 27, // Opcode: FADDD +/* 2349 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 2357 +/* 2353 */ MCD_OPC_Decode, 142, 1, 28, // Opcode: FADDQ +/* 2357 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 2365 +/* 2361 */ MCD_OPC_Decode, 162, 2, 26, // Opcode: FSUBS +/* 2365 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 2373 +/* 2369 */ MCD_OPC_Decode, 160, 2, 27, // Opcode: FSUBD +/* 2373 */ MCD_OPC_FilterValue, 71, 4, 0, // Skip to: 2381 +/* 2377 */ MCD_OPC_Decode, 161, 2, 28, // Opcode: FSUBQ +/* 2381 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 2389 +/* 2385 */ MCD_OPC_Decode, 224, 1, 26, // Opcode: FMULS +/* 2389 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 2397 +/* 2393 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: FMULD +/* 2397 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 2405 +/* 2401 */ MCD_OPC_Decode, 223, 1, 28, // Opcode: FMULQ +/* 2405 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 2413 +/* 2409 */ MCD_OPC_Decode, 167, 1, 26, // Opcode: FDIVS +/* 2413 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 2421 +/* 2417 */ MCD_OPC_Decode, 165, 1, 27, // Opcode: FDIVD +/* 2421 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 2429 +/* 2425 */ MCD_OPC_Decode, 166, 1, 28, // Opcode: FDIVQ +/* 2429 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 2441 +/* 2433 */ MCD_OPC_CheckPredicate, 1, 50, 13, // Skip to: 5815 +/* 2437 */ MCD_OPC_Decode, 226, 1, 27, // Opcode: FNADDS +/* 2441 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 2453 +/* 2445 */ MCD_OPC_CheckPredicate, 1, 38, 13, // Skip to: 5815 +/* 2449 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: FNADDD +/* 2453 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 2465 +/* 2457 */ MCD_OPC_CheckPredicate, 1, 26, 13, // Skip to: 5815 +/* 2461 */ MCD_OPC_Decode, 235, 1, 27, // Opcode: FNMULS +/* 2465 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 2477 +/* 2469 */ MCD_OPC_CheckPredicate, 1, 14, 13, // Skip to: 5815 +/* 2473 */ MCD_OPC_Decode, 234, 1, 27, // Opcode: FNMULD +/* 2477 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 2489 +/* 2481 */ MCD_OPC_CheckPredicate, 1, 2, 13, // Skip to: 5815 +/* 2485 */ MCD_OPC_Decode, 175, 1, 27, // Opcode: FHADDS +/* 2489 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 2501 +/* 2493 */ MCD_OPC_CheckPredicate, 1, 246, 12, // Skip to: 5815 +/* 2497 */ MCD_OPC_Decode, 174, 1, 27, // Opcode: FHADDD +/* 2501 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 2513 +/* 2505 */ MCD_OPC_CheckPredicate, 1, 234, 12, // Skip to: 5815 +/* 2509 */ MCD_OPC_Decode, 177, 1, 27, // Opcode: FHSUBS +/* 2513 */ MCD_OPC_FilterValue, 102, 8, 0, // Skip to: 2525 +/* 2517 */ MCD_OPC_CheckPredicate, 1, 222, 12, // Skip to: 5815 +/* 2521 */ MCD_OPC_Decode, 176, 1, 27, // Opcode: FHSUBD +/* 2525 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 2533 +/* 2529 */ MCD_OPC_Decode, 144, 2, 29, // Opcode: FSMULD +/* 2533 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 2541 +/* 2537 */ MCD_OPC_Decode, 168, 1, 30, // Opcode: FDMULQ +/* 2541 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 2553 +/* 2545 */ MCD_OPC_CheckPredicate, 1, 194, 12, // Skip to: 5815 +/* 2549 */ MCD_OPC_Decode, 233, 1, 27, // Opcode: FNHADDS +/* 2553 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 2565 +/* 2557 */ MCD_OPC_CheckPredicate, 1, 182, 12, // Skip to: 5815 +/* 2561 */ MCD_OPC_Decode, 232, 1, 27, // Opcode: FNHADDD +/* 2565 */ MCD_OPC_FilterValue, 121, 8, 0, // Skip to: 2577 +/* 2569 */ MCD_OPC_CheckPredicate, 1, 170, 12, // Skip to: 5815 +/* 2573 */ MCD_OPC_Decode, 242, 1, 27, // Opcode: FNSMULD +/* 2577 */ MCD_OPC_FilterValue, 129, 1, 10, 0, // Skip to: 2592 +/* 2582 */ MCD_OPC_CheckField, 14, 5, 0, 155, 12, // Skip to: 5815 +/* 2588 */ MCD_OPC_Decode, 159, 2, 31, // Opcode: FSTOX +/* 2592 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 2607 +/* 2597 */ MCD_OPC_CheckField, 14, 5, 0, 140, 12, // Skip to: 5815 +/* 2603 */ MCD_OPC_Decode, 172, 1, 24, // Opcode: FDTOX +/* 2607 */ MCD_OPC_FilterValue, 131, 1, 10, 0, // Skip to: 2622 +/* 2612 */ MCD_OPC_CheckField, 14, 5, 0, 125, 12, // Skip to: 5815 +/* 2618 */ MCD_OPC_Decode, 139, 2, 32, // Opcode: FQTOX +/* 2622 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 2637 +/* 2627 */ MCD_OPC_CheckField, 14, 5, 0, 110, 12, // Skip to: 5815 +/* 2633 */ MCD_OPC_Decode, 169, 2, 33, // Opcode: FXTOS +/* 2637 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 2652 +/* 2642 */ MCD_OPC_CheckField, 14, 5, 0, 95, 12, // Skip to: 5815 +/* 2648 */ MCD_OPC_Decode, 167, 2, 24, // Opcode: FXTOD +/* 2652 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 2667 +/* 2657 */ MCD_OPC_CheckField, 14, 5, 0, 80, 12, // Skip to: 5815 +/* 2663 */ MCD_OPC_Decode, 168, 2, 34, // Opcode: FXTOQ +/* 2667 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 2682 +/* 2672 */ MCD_OPC_CheckField, 14, 5, 0, 65, 12, // Skip to: 5815 +/* 2678 */ MCD_OPC_Decode, 180, 1, 23, // Opcode: FITOS +/* 2682 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 2697 +/* 2687 */ MCD_OPC_CheckField, 14, 5, 0, 50, 12, // Skip to: 5815 +/* 2693 */ MCD_OPC_Decode, 171, 1, 33, // Opcode: FDTOS +/* 2697 */ MCD_OPC_FilterValue, 199, 1, 10, 0, // Skip to: 2712 +/* 2702 */ MCD_OPC_CheckField, 14, 5, 0, 35, 12, // Skip to: 5815 +/* 2708 */ MCD_OPC_Decode, 138, 2, 35, // Opcode: FQTOS +/* 2712 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 2727 +/* 2717 */ MCD_OPC_CheckField, 14, 5, 0, 20, 12, // Skip to: 5815 +/* 2723 */ MCD_OPC_Decode, 178, 1, 31, // Opcode: FITOD +/* 2727 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 2742 +/* 2732 */ MCD_OPC_CheckField, 14, 5, 0, 5, 12, // Skip to: 5815 +/* 2738 */ MCD_OPC_Decode, 156, 2, 31, // Opcode: FSTOD +/* 2742 */ MCD_OPC_FilterValue, 203, 1, 10, 0, // Skip to: 2757 +/* 2747 */ MCD_OPC_CheckField, 14, 5, 0, 246, 11, // Skip to: 5815 +/* 2753 */ MCD_OPC_Decode, 136, 2, 32, // Opcode: FQTOD +/* 2757 */ MCD_OPC_FilterValue, 204, 1, 10, 0, // Skip to: 2772 +/* 2762 */ MCD_OPC_CheckField, 14, 5, 0, 231, 11, // Skip to: 5815 +/* 2768 */ MCD_OPC_Decode, 179, 1, 36, // Opcode: FITOQ +/* 2772 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 2787 +/* 2777 */ MCD_OPC_CheckField, 14, 5, 0, 216, 11, // Skip to: 5815 +/* 2783 */ MCD_OPC_Decode, 158, 2, 36, // Opcode: FSTOQ +/* 2787 */ MCD_OPC_FilterValue, 206, 1, 10, 0, // Skip to: 2802 +/* 2792 */ MCD_OPC_CheckField, 14, 5, 0, 201, 11, // Skip to: 5815 +/* 2798 */ MCD_OPC_Decode, 170, 1, 34, // Opcode: FDTOQ +/* 2802 */ MCD_OPC_FilterValue, 209, 1, 10, 0, // Skip to: 2817 +/* 2807 */ MCD_OPC_CheckField, 14, 5, 0, 186, 11, // Skip to: 5815 +/* 2813 */ MCD_OPC_Decode, 157, 2, 23, // Opcode: FSTOI +/* 2817 */ MCD_OPC_FilterValue, 210, 1, 10, 0, // Skip to: 2832 +/* 2822 */ MCD_OPC_CheckField, 14, 5, 0, 171, 11, // Skip to: 5815 +/* 2828 */ MCD_OPC_Decode, 169, 1, 33, // Opcode: FDTOI +/* 2832 */ MCD_OPC_FilterValue, 211, 1, 162, 11, // Skip to: 5815 +/* 2837 */ MCD_OPC_CheckField, 14, 5, 0, 156, 11, // Skip to: 5815 +/* 2843 */ MCD_OPC_Decode, 137, 2, 35, // Opcode: FQTOI +/* 2847 */ MCD_OPC_FilterValue, 53, 70, 2, // Skip to: 3433 +/* 2851 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... +/* 2854 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 2933 +/* 2858 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2861 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2894 +/* 2865 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2868 */ MCD_OPC_FilterValue, 0, 127, 11, // Skip to: 5815 +/* 2872 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2886 +/* 2876 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2886 +/* 2882 */ MCD_OPC_Decode, 212, 1, 37, // Opcode: FMOVS_FCC +/* 2886 */ MCD_OPC_CheckPredicate, 0, 109, 11, // Skip to: 5815 +/* 2890 */ MCD_OPC_Decode, 220, 3, 38, // Opcode: V9FMOVS_FCC +/* 2894 */ MCD_OPC_FilterValue, 1, 101, 11, // Skip to: 5815 +/* 2898 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2919 +/* 2905 */ MCD_OPC_CheckPredicate, 0, 90, 11, // Skip to: 5815 +/* 2909 */ MCD_OPC_CheckField, 18, 1, 0, 84, 11, // Skip to: 5815 +/* 2915 */ MCD_OPC_Decode, 213, 1, 37, // Opcode: FMOVS_ICC +/* 2919 */ MCD_OPC_FilterValue, 2, 76, 11, // Skip to: 5815 +/* 2923 */ MCD_OPC_CheckField, 18, 1, 0, 70, 11, // Skip to: 5815 +/* 2929 */ MCD_OPC_Decode, 214, 1, 37, // Opcode: FMOVS_XCC +/* 2933 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 3012 +/* 2937 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 2940 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2973 +/* 2944 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 2947 */ MCD_OPC_FilterValue, 0, 48, 11, // Skip to: 5815 +/* 2951 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2965 +/* 2955 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2965 +/* 2961 */ MCD_OPC_Decode, 186, 1, 39, // Opcode: FMOVD_FCC +/* 2965 */ MCD_OPC_CheckPredicate, 0, 30, 11, // Skip to: 5815 +/* 2969 */ MCD_OPC_Decode, 218, 3, 40, // Opcode: V9FMOVD_FCC +/* 2973 */ MCD_OPC_FilterValue, 1, 22, 11, // Skip to: 5815 +/* 2977 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 2980 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2998 +/* 2984 */ MCD_OPC_CheckPredicate, 0, 11, 11, // Skip to: 5815 +/* 2988 */ MCD_OPC_CheckField, 18, 1, 0, 5, 11, // Skip to: 5815 +/* 2994 */ MCD_OPC_Decode, 187, 1, 39, // Opcode: FMOVD_ICC +/* 2998 */ MCD_OPC_FilterValue, 2, 253, 10, // Skip to: 5815 +/* 3002 */ MCD_OPC_CheckField, 18, 1, 0, 247, 10, // Skip to: 5815 +/* 3008 */ MCD_OPC_Decode, 188, 1, 39, // Opcode: FMOVD_XCC +/* 3012 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 3091 +/* 3016 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 3052 +/* 3023 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 3026 */ MCD_OPC_FilterValue, 0, 225, 10, // Skip to: 5815 +/* 3030 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 3044 +/* 3034 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3044 +/* 3040 */ MCD_OPC_Decode, 190, 1, 41, // Opcode: FMOVQ_FCC +/* 3044 */ MCD_OPC_CheckPredicate, 0, 207, 10, // Skip to: 5815 +/* 3048 */ MCD_OPC_Decode, 219, 3, 42, // Opcode: V9FMOVQ_FCC +/* 3052 */ MCD_OPC_FilterValue, 1, 199, 10, // Skip to: 5815 +/* 3056 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 3059 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3077 +/* 3063 */ MCD_OPC_CheckPredicate, 0, 188, 10, // Skip to: 5815 +/* 3067 */ MCD_OPC_CheckField, 18, 1, 0, 182, 10, // Skip to: 5815 +/* 3073 */ MCD_OPC_Decode, 191, 1, 41, // Opcode: FMOVQ_ICC +/* 3077 */ MCD_OPC_FilterValue, 2, 174, 10, // Skip to: 5815 +/* 3081 */ MCD_OPC_CheckField, 18, 1, 0, 168, 10, // Skip to: 5815 +/* 3087 */ MCD_OPC_Decode, 192, 1, 41, // Opcode: FMOVQ_XCC +/* 3091 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 3122 +/* 3095 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3098 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3110 +/* 3102 */ MCD_OPC_CheckPredicate, 0, 149, 10, // Skip to: 5815 +/* 3106 */ MCD_OPC_Decode, 201, 1, 43, // Opcode: FMOVRLEZS +/* 3110 */ MCD_OPC_FilterValue, 3, 141, 10, // Skip to: 5815 +/* 3114 */ MCD_OPC_CheckPredicate, 0, 137, 10, // Skip to: 5815 +/* 3118 */ MCD_OPC_Decode, 198, 1, 43, // Opcode: FMOVRGZS +/* 3122 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3153 +/* 3126 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3129 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3141 +/* 3133 */ MCD_OPC_CheckPredicate, 0, 118, 10, // Skip to: 5815 +/* 3137 */ MCD_OPC_Decode, 199, 1, 43, // Opcode: FMOVRLEZD +/* 3141 */ MCD_OPC_FilterValue, 3, 110, 10, // Skip to: 5815 +/* 3145 */ MCD_OPC_CheckPredicate, 0, 106, 10, // Skip to: 5815 +/* 3149 */ MCD_OPC_Decode, 196, 1, 43, // Opcode: FMOVRGZD +/* 3153 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 3184 +/* 3157 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3160 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3172 +/* 3164 */ MCD_OPC_CheckPredicate, 0, 87, 10, // Skip to: 5815 +/* 3168 */ MCD_OPC_Decode, 200, 1, 43, // Opcode: FMOVRLEZQ +/* 3172 */ MCD_OPC_FilterValue, 3, 79, 10, // Skip to: 5815 +/* 3176 */ MCD_OPC_CheckPredicate, 0, 75, 10, // Skip to: 5815 +/* 3180 */ MCD_OPC_Decode, 197, 1, 43, // Opcode: FMOVRGZQ +/* 3184 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 3198 +/* 3188 */ MCD_OPC_CheckField, 11, 3, 1, 61, 10, // Skip to: 5815 +/* 3194 */ MCD_OPC_Decode, 217, 3, 44, // Opcode: V9FCMPS +/* 3198 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 3212 +/* 3202 */ MCD_OPC_CheckField, 11, 3, 1, 47, 10, // Skip to: 5815 +/* 3208 */ MCD_OPC_Decode, 212, 3, 45, // Opcode: V9FCMPD +/* 3212 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 3226 +/* 3216 */ MCD_OPC_CheckField, 11, 3, 1, 33, 10, // Skip to: 5815 +/* 3222 */ MCD_OPC_Decode, 216, 3, 46, // Opcode: V9FCMPQ +/* 3226 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 3240 +/* 3230 */ MCD_OPC_CheckField, 11, 3, 1, 19, 10, // Skip to: 5815 +/* 3236 */ MCD_OPC_Decode, 215, 3, 44, // Opcode: V9FCMPES +/* 3240 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 3254 +/* 3244 */ MCD_OPC_CheckField, 11, 3, 1, 5, 10, // Skip to: 5815 +/* 3250 */ MCD_OPC_Decode, 213, 3, 45, // Opcode: V9FCMPED +/* 3254 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 3268 +/* 3258 */ MCD_OPC_CheckField, 11, 3, 1, 247, 9, // Skip to: 5815 +/* 3264 */ MCD_OPC_Decode, 214, 3, 46, // Opcode: V9FCMPEQ +/* 3268 */ MCD_OPC_FilterValue, 37, 51, 0, // Skip to: 3323 +/* 3272 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3275 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3287 +/* 3279 */ MCD_OPC_CheckPredicate, 0, 228, 9, // Skip to: 5815 +/* 3283 */ MCD_OPC_Decode, 210, 1, 43, // Opcode: FMOVRZS +/* 3287 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3299 +/* 3291 */ MCD_OPC_CheckPredicate, 0, 216, 9, // Skip to: 5815 +/* 3295 */ MCD_OPC_Decode, 204, 1, 43, // Opcode: FMOVRLZS +/* 3299 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3311 +/* 3303 */ MCD_OPC_CheckPredicate, 0, 204, 9, // Skip to: 5815 +/* 3307 */ MCD_OPC_Decode, 207, 1, 43, // Opcode: FMOVRNZS +/* 3311 */ MCD_OPC_FilterValue, 3, 196, 9, // Skip to: 5815 +/* 3315 */ MCD_OPC_CheckPredicate, 0, 192, 9, // Skip to: 5815 +/* 3319 */ MCD_OPC_Decode, 195, 1, 43, // Opcode: FMOVRGEZS +/* 3323 */ MCD_OPC_FilterValue, 38, 51, 0, // Skip to: 3378 +/* 3327 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3330 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3342 +/* 3334 */ MCD_OPC_CheckPredicate, 0, 173, 9, // Skip to: 5815 +/* 3338 */ MCD_OPC_Decode, 208, 1, 43, // Opcode: FMOVRZD +/* 3342 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3354 +/* 3346 */ MCD_OPC_CheckPredicate, 0, 161, 9, // Skip to: 5815 +/* 3350 */ MCD_OPC_Decode, 202, 1, 43, // Opcode: FMOVRLZD +/* 3354 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3366 +/* 3358 */ MCD_OPC_CheckPredicate, 0, 149, 9, // Skip to: 5815 +/* 3362 */ MCD_OPC_Decode, 205, 1, 43, // Opcode: FMOVRNZD +/* 3366 */ MCD_OPC_FilterValue, 3, 141, 9, // Skip to: 5815 +/* 3370 */ MCD_OPC_CheckPredicate, 0, 137, 9, // Skip to: 5815 +/* 3374 */ MCD_OPC_Decode, 193, 1, 43, // Opcode: FMOVRGEZD +/* 3378 */ MCD_OPC_FilterValue, 39, 129, 9, // Skip to: 5815 +/* 3382 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 3385 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3397 +/* 3389 */ MCD_OPC_CheckPredicate, 0, 118, 9, // Skip to: 5815 +/* 3393 */ MCD_OPC_Decode, 209, 1, 43, // Opcode: FMOVRZQ +/* 3397 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3409 +/* 3401 */ MCD_OPC_CheckPredicate, 0, 106, 9, // Skip to: 5815 +/* 3405 */ MCD_OPC_Decode, 203, 1, 43, // Opcode: FMOVRLZQ +/* 3409 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3421 +/* 3413 */ MCD_OPC_CheckPredicate, 0, 94, 9, // Skip to: 5815 +/* 3417 */ MCD_OPC_Decode, 206, 1, 43, // Opcode: FMOVRNZQ +/* 3421 */ MCD_OPC_FilterValue, 3, 86, 9, // Skip to: 5815 +/* 3425 */ MCD_OPC_CheckPredicate, 0, 82, 9, // Skip to: 5815 +/* 3429 */ MCD_OPC_Decode, 194, 1, 43, // Opcode: FMOVRGEZQ +/* 3433 */ MCD_OPC_FilterValue, 54, 18, 6, // Skip to: 4991 +/* 3437 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... +/* 3440 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3452 +/* 3444 */ MCD_OPC_CheckPredicate, 2, 63, 9, // Skip to: 5815 +/* 3448 */ MCD_OPC_Decode, 134, 1, 10, // Opcode: EDGE8 +/* 3452 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3464 +/* 3456 */ MCD_OPC_CheckPredicate, 3, 51, 9, // Skip to: 5815 +/* 3460 */ MCD_OPC_Decode, 137, 1, 10, // Opcode: EDGE8N +/* 3464 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3476 +/* 3468 */ MCD_OPC_CheckPredicate, 2, 39, 9, // Skip to: 5815 +/* 3472 */ MCD_OPC_Decode, 135, 1, 10, // Opcode: EDGE8L +/* 3476 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3488 +/* 3480 */ MCD_OPC_CheckPredicate, 3, 27, 9, // Skip to: 5815 +/* 3484 */ MCD_OPC_Decode, 136, 1, 10, // Opcode: EDGE8LN +/* 3488 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 3499 +/* 3492 */ MCD_OPC_CheckPredicate, 2, 15, 9, // Skip to: 5815 +/* 3496 */ MCD_OPC_Decode, 126, 10, // Opcode: EDGE16 +/* 3499 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 3511 +/* 3503 */ MCD_OPC_CheckPredicate, 3, 4, 9, // Skip to: 5815 +/* 3507 */ MCD_OPC_Decode, 129, 1, 10, // Opcode: EDGE16N +/* 3511 */ MCD_OPC_FilterValue, 6, 7, 0, // Skip to: 3522 +/* 3515 */ MCD_OPC_CheckPredicate, 2, 248, 8, // Skip to: 5815 +/* 3519 */ MCD_OPC_Decode, 127, 10, // Opcode: EDGE16L +/* 3522 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 3534 +/* 3526 */ MCD_OPC_CheckPredicate, 3, 237, 8, // Skip to: 5815 +/* 3530 */ MCD_OPC_Decode, 128, 1, 10, // Opcode: EDGE16LN +/* 3534 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 3546 +/* 3538 */ MCD_OPC_CheckPredicate, 2, 225, 8, // Skip to: 5815 +/* 3542 */ MCD_OPC_Decode, 130, 1, 10, // Opcode: EDGE32 +/* 3546 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 3558 +/* 3550 */ MCD_OPC_CheckPredicate, 3, 213, 8, // Skip to: 5815 +/* 3554 */ MCD_OPC_Decode, 133, 1, 10, // Opcode: EDGE32N +/* 3558 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 3570 +/* 3562 */ MCD_OPC_CheckPredicate, 2, 201, 8, // Skip to: 5815 +/* 3566 */ MCD_OPC_Decode, 131, 1, 10, // Opcode: EDGE32L +/* 3570 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 3582 +/* 3574 */ MCD_OPC_CheckPredicate, 3, 189, 8, // Skip to: 5815 +/* 3578 */ MCD_OPC_Decode, 132, 1, 10, // Opcode: EDGE32LN +/* 3582 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 3593 +/* 3586 */ MCD_OPC_CheckPredicate, 2, 177, 8, // Skip to: 5815 +/* 3590 */ MCD_OPC_Decode, 51, 10, // Opcode: ARRAY8 +/* 3593 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 3604 +/* 3597 */ MCD_OPC_CheckPredicate, 1, 166, 8, // Skip to: 5815 +/* 3601 */ MCD_OPC_Decode, 28, 10, // Opcode: ADDXC +/* 3604 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 3615 +/* 3608 */ MCD_OPC_CheckPredicate, 2, 155, 8, // Skip to: 5815 +/* 3612 */ MCD_OPC_Decode, 49, 10, // Opcode: ARRAY16 +/* 3615 */ MCD_OPC_FilterValue, 19, 7, 0, // Skip to: 3626 +/* 3619 */ MCD_OPC_CheckPredicate, 1, 144, 8, // Skip to: 5815 +/* 3623 */ MCD_OPC_Decode, 29, 10, // Opcode: ADDXCCC +/* 3626 */ MCD_OPC_FilterValue, 20, 7, 0, // Skip to: 3637 +/* 3630 */ MCD_OPC_CheckPredicate, 2, 133, 8, // Skip to: 5815 +/* 3634 */ MCD_OPC_Decode, 50, 10, // Opcode: ARRAY32 +/* 3637 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 3649 +/* 3641 */ MCD_OPC_CheckPredicate, 1, 122, 8, // Skip to: 5815 +/* 3645 */ MCD_OPC_Decode, 208, 3, 10, // Opcode: UMULXHI +/* 3649 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3667 +/* 3653 */ MCD_OPC_CheckPredicate, 1, 110, 8, // Skip to: 5815 +/* 3657 */ MCD_OPC_CheckField, 14, 5, 0, 104, 8, // Skip to: 5815 +/* 3663 */ MCD_OPC_Decode, 197, 2, 47, // Opcode: LZCNT +/* 3667 */ MCD_OPC_FilterValue, 24, 7, 0, // Skip to: 3678 +/* 3671 */ MCD_OPC_CheckPredicate, 2, 92, 8, // Skip to: 5815 +/* 3675 */ MCD_OPC_Decode, 36, 10, // Opcode: ALIGNADDR +/* 3678 */ MCD_OPC_FilterValue, 25, 7, 0, // Skip to: 3689 +/* 3682 */ MCD_OPC_CheckPredicate, 3, 81, 8, // Skip to: 5815 +/* 3686 */ MCD_OPC_Decode, 78, 10, // Opcode: BMASK +/* 3689 */ MCD_OPC_FilterValue, 26, 7, 0, // Skip to: 3700 +/* 3693 */ MCD_OPC_CheckPredicate, 2, 70, 8, // Skip to: 5815 +/* 3697 */ MCD_OPC_Decode, 37, 10, // Opcode: ALIGNADDRL +/* 3700 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 3723 +/* 3704 */ MCD_OPC_CheckPredicate, 1, 59, 8, // Skip to: 5815 +/* 3708 */ MCD_OPC_CheckField, 25, 5, 0, 53, 8, // Skip to: 5815 +/* 3714 */ MCD_OPC_CheckField, 14, 5, 0, 47, 8, // Skip to: 5815 +/* 3720 */ MCD_OPC_Decode, 123, 48, // Opcode: CMASK8 +/* 3723 */ MCD_OPC_FilterValue, 28, 7, 0, // Skip to: 3734 +/* 3727 */ MCD_OPC_CheckPredicate, 3, 36, 8, // Skip to: 5815 +/* 3731 */ MCD_OPC_Decode, 115, 27, // Opcode: BSHUFFLE +/* 3734 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 3757 +/* 3738 */ MCD_OPC_CheckPredicate, 1, 25, 8, // Skip to: 5815 +/* 3742 */ MCD_OPC_CheckField, 25, 5, 0, 19, 8, // Skip to: 5815 +/* 3748 */ MCD_OPC_CheckField, 14, 5, 0, 13, 8, // Skip to: 5815 +/* 3754 */ MCD_OPC_Decode, 121, 48, // Opcode: CMASK16 +/* 3757 */ MCD_OPC_FilterValue, 31, 19, 0, // Skip to: 3780 +/* 3761 */ MCD_OPC_CheckPredicate, 1, 2, 8, // Skip to: 5815 +/* 3765 */ MCD_OPC_CheckField, 25, 5, 0, 252, 7, // Skip to: 5815 +/* 3771 */ MCD_OPC_CheckField, 14, 5, 0, 246, 7, // Skip to: 5815 +/* 3777 */ MCD_OPC_Decode, 122, 48, // Opcode: CMASK32 +/* 3780 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3792 +/* 3784 */ MCD_OPC_CheckPredicate, 2, 235, 7, // Skip to: 5815 +/* 3788 */ MCD_OPC_Decode, 159, 1, 49, // Opcode: FCMPLE16 +/* 3792 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3804 +/* 3796 */ MCD_OPC_CheckPredicate, 1, 223, 7, // Skip to: 5815 +/* 3800 */ MCD_OPC_Decode, 142, 2, 27, // Opcode: FSLL16 +/* 3804 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 3816 +/* 3808 */ MCD_OPC_CheckPredicate, 2, 211, 7, // Skip to: 5815 +/* 3812 */ MCD_OPC_Decode, 161, 1, 49, // Opcode: FCMPNE16 +/* 3816 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 3828 +/* 3820 */ MCD_OPC_CheckPredicate, 1, 199, 7, // Skip to: 5815 +/* 3824 */ MCD_OPC_Decode, 154, 2, 27, // Opcode: FSRL16 +/* 3828 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 3840 +/* 3832 */ MCD_OPC_CheckPredicate, 2, 187, 7, // Skip to: 5815 +/* 3836 */ MCD_OPC_Decode, 160, 1, 49, // Opcode: FCMPLE32 +/* 3840 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 3852 +/* 3844 */ MCD_OPC_CheckPredicate, 1, 175, 7, // Skip to: 5815 +/* 3848 */ MCD_OPC_Decode, 143, 2, 27, // Opcode: FSLL32 +/* 3852 */ MCD_OPC_FilterValue, 38, 8, 0, // Skip to: 3864 +/* 3856 */ MCD_OPC_CheckPredicate, 2, 163, 7, // Skip to: 5815 +/* 3860 */ MCD_OPC_Decode, 162, 1, 49, // Opcode: FCMPNE32 +/* 3864 */ MCD_OPC_FilterValue, 39, 8, 0, // Skip to: 3876 +/* 3868 */ MCD_OPC_CheckPredicate, 1, 151, 7, // Skip to: 5815 +/* 3872 */ MCD_OPC_Decode, 155, 2, 27, // Opcode: FSRL32 +/* 3876 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3888 +/* 3880 */ MCD_OPC_CheckPredicate, 2, 139, 7, // Skip to: 5815 +/* 3884 */ MCD_OPC_Decode, 157, 1, 49, // Opcode: FCMPGT16 +/* 3888 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3900 +/* 3892 */ MCD_OPC_CheckPredicate, 1, 127, 7, // Skip to: 5815 +/* 3896 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: FSLAS16 +/* 3900 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 3912 +/* 3904 */ MCD_OPC_CheckPredicate, 2, 115, 7, // Skip to: 5815 +/* 3908 */ MCD_OPC_Decode, 155, 1, 49, // Opcode: FCMPEQ16 +/* 3912 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 3924 +/* 3916 */ MCD_OPC_CheckPredicate, 1, 103, 7, // Skip to: 5815 +/* 3920 */ MCD_OPC_Decode, 148, 2, 27, // Opcode: FSRA16 +/* 3924 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 3936 +/* 3928 */ MCD_OPC_CheckPredicate, 2, 91, 7, // Skip to: 5815 +/* 3932 */ MCD_OPC_Decode, 158, 1, 49, // Opcode: FCMPGT32 +/* 3936 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 3948 +/* 3940 */ MCD_OPC_CheckPredicate, 1, 79, 7, // Skip to: 5815 +/* 3944 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: FSLAS32 +/* 3948 */ MCD_OPC_FilterValue, 46, 8, 0, // Skip to: 3960 +/* 3952 */ MCD_OPC_CheckPredicate, 2, 67, 7, // Skip to: 5815 +/* 3956 */ MCD_OPC_Decode, 156, 1, 49, // Opcode: FCMPEQ32 +/* 3960 */ MCD_OPC_FilterValue, 47, 8, 0, // Skip to: 3972 +/* 3964 */ MCD_OPC_CheckPredicate, 1, 55, 7, // Skip to: 5815 +/* 3968 */ MCD_OPC_Decode, 149, 2, 27, // Opcode: FSRA32 +/* 3972 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3984 +/* 3976 */ MCD_OPC_CheckPredicate, 2, 43, 7, // Skip to: 5815 +/* 3980 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: FMUL8X16 +/* 3984 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 3996 +/* 3988 */ MCD_OPC_CheckPredicate, 2, 31, 7, // Skip to: 5815 +/* 3992 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: FMUL8X16AU +/* 3996 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 4008 +/* 4000 */ MCD_OPC_CheckPredicate, 2, 19, 7, // Skip to: 5815 +/* 4004 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: FMUL8X16AL +/* 4008 */ MCD_OPC_FilterValue, 54, 8, 0, // Skip to: 4020 +/* 4012 */ MCD_OPC_CheckPredicate, 2, 7, 7, // Skip to: 5815 +/* 4016 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: FMUL8SUX16 +/* 4020 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 4032 +/* 4024 */ MCD_OPC_CheckPredicate, 2, 251, 6, // Skip to: 5815 +/* 4028 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: FMUL8ULX16 +/* 4032 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 4044 +/* 4036 */ MCD_OPC_CheckPredicate, 2, 239, 6, // Skip to: 5815 +/* 4040 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: FMULD8SUX16 +/* 4044 */ MCD_OPC_FilterValue, 57, 8, 0, // Skip to: 4056 +/* 4048 */ MCD_OPC_CheckPredicate, 2, 227, 6, // Skip to: 5815 +/* 4052 */ MCD_OPC_Decode, 222, 1, 27, // Opcode: FMULD8ULX16 +/* 4056 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 4068 +/* 4060 */ MCD_OPC_CheckPredicate, 2, 215, 6, // Skip to: 5815 +/* 4064 */ MCD_OPC_Decode, 252, 1, 27, // Opcode: FPACK32 +/* 4068 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 4086 +/* 4072 */ MCD_OPC_CheckPredicate, 2, 203, 6, // Skip to: 5815 +/* 4076 */ MCD_OPC_CheckField, 14, 5, 0, 197, 6, // Skip to: 5815 +/* 4082 */ MCD_OPC_Decode, 251, 1, 24, // Opcode: FPACK16 +/* 4086 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4104 +/* 4090 */ MCD_OPC_CheckPredicate, 2, 185, 6, // Skip to: 5815 +/* 4094 */ MCD_OPC_CheckField, 14, 5, 0, 179, 6, // Skip to: 5815 +/* 4100 */ MCD_OPC_Decode, 253, 1, 24, // Opcode: FPACKFIX +/* 4104 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 4116 +/* 4108 */ MCD_OPC_CheckPredicate, 2, 167, 6, // Skip to: 5815 +/* 4112 */ MCD_OPC_Decode, 236, 2, 27, // Opcode: PDIST +/* 4116 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 4128 +/* 4120 */ MCD_OPC_CheckPredicate, 1, 155, 6, // Skip to: 5815 +/* 4124 */ MCD_OPC_Decode, 237, 2, 27, // Opcode: PDISTN +/* 4128 */ MCD_OPC_FilterValue, 64, 8, 0, // Skip to: 4140 +/* 4132 */ MCD_OPC_CheckPredicate, 1, 143, 6, // Skip to: 5815 +/* 4136 */ MCD_OPC_Decode, 184, 1, 27, // Opcode: FMEAN16 +/* 4140 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 4152 +/* 4144 */ MCD_OPC_CheckPredicate, 1, 131, 6, // Skip to: 5815 +/* 4148 */ MCD_OPC_Decode, 130, 2, 27, // Opcode: FPADD64 +/* 4152 */ MCD_OPC_FilterValue, 68, 8, 0, // Skip to: 4164 +/* 4156 */ MCD_OPC_CheckPredicate, 1, 119, 6, // Skip to: 5815 +/* 4160 */ MCD_OPC_Decode, 153, 1, 27, // Opcode: FCHKSM16 +/* 4164 */ MCD_OPC_FilterValue, 72, 8, 0, // Skip to: 4176 +/* 4168 */ MCD_OPC_CheckPredicate, 2, 107, 6, // Skip to: 5815 +/* 4172 */ MCD_OPC_Decode, 144, 1, 27, // Opcode: FALIGNADATA +/* 4176 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 4188 +/* 4180 */ MCD_OPC_CheckPredicate, 2, 95, 6, // Skip to: 5815 +/* 4184 */ MCD_OPC_Decode, 131, 2, 27, // Opcode: FPMERGE +/* 4188 */ MCD_OPC_FilterValue, 77, 14, 0, // Skip to: 4206 +/* 4192 */ MCD_OPC_CheckPredicate, 2, 83, 6, // Skip to: 5815 +/* 4196 */ MCD_OPC_CheckField, 14, 5, 0, 77, 6, // Skip to: 5815 +/* 4202 */ MCD_OPC_Decode, 173, 1, 24, // Opcode: FEXPAND +/* 4206 */ MCD_OPC_FilterValue, 80, 8, 0, // Skip to: 4218 +/* 4210 */ MCD_OPC_CheckPredicate, 2, 65, 6, // Skip to: 5815 +/* 4214 */ MCD_OPC_Decode, 254, 1, 27, // Opcode: FPADD16 +/* 4218 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 4230 +/* 4222 */ MCD_OPC_CheckPredicate, 2, 53, 6, // Skip to: 5815 +/* 4226 */ MCD_OPC_Decode, 255, 1, 27, // Opcode: FPADD16S +/* 4230 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 4242 +/* 4234 */ MCD_OPC_CheckPredicate, 2, 41, 6, // Skip to: 5815 +/* 4238 */ MCD_OPC_Decode, 128, 2, 27, // Opcode: FPADD32 +/* 4242 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 4254 +/* 4246 */ MCD_OPC_CheckPredicate, 2, 29, 6, // Skip to: 5815 +/* 4250 */ MCD_OPC_Decode, 129, 2, 27, // Opcode: FPADD32S +/* 4254 */ MCD_OPC_FilterValue, 84, 8, 0, // Skip to: 4266 +/* 4258 */ MCD_OPC_CheckPredicate, 2, 17, 6, // Skip to: 5815 +/* 4262 */ MCD_OPC_Decode, 132, 2, 27, // Opcode: FPSUB16 +/* 4266 */ MCD_OPC_FilterValue, 85, 8, 0, // Skip to: 4278 +/* 4270 */ MCD_OPC_CheckPredicate, 2, 5, 6, // Skip to: 5815 +/* 4274 */ MCD_OPC_Decode, 133, 2, 27, // Opcode: FPSUB16S +/* 4278 */ MCD_OPC_FilterValue, 86, 8, 0, // Skip to: 4290 +/* 4282 */ MCD_OPC_CheckPredicate, 2, 249, 5, // Skip to: 5815 +/* 4286 */ MCD_OPC_Decode, 134, 2, 27, // Opcode: FPSUB32 +/* 4290 */ MCD_OPC_FilterValue, 87, 8, 0, // Skip to: 4302 +/* 4294 */ MCD_OPC_CheckPredicate, 2, 237, 5, // Skip to: 5815 +/* 4298 */ MCD_OPC_Decode, 135, 2, 27, // Opcode: FPSUB32S +/* 4302 */ MCD_OPC_FilterValue, 96, 20, 0, // Skip to: 4326 +/* 4306 */ MCD_OPC_CheckPredicate, 2, 225, 5, // Skip to: 5815 +/* 4310 */ MCD_OPC_CheckField, 14, 5, 0, 219, 5, // Skip to: 5815 +/* 4316 */ MCD_OPC_CheckField, 0, 5, 0, 213, 5, // Skip to: 5815 +/* 4322 */ MCD_OPC_Decode, 170, 2, 50, // Opcode: FZERO +/* 4326 */ MCD_OPC_FilterValue, 97, 20, 0, // Skip to: 4350 +/* 4330 */ MCD_OPC_CheckPredicate, 2, 201, 5, // Skip to: 5815 +/* 4334 */ MCD_OPC_CheckField, 14, 5, 0, 195, 5, // Skip to: 5815 +/* 4340 */ MCD_OPC_CheckField, 0, 5, 0, 189, 5, // Skip to: 5815 +/* 4346 */ MCD_OPC_Decode, 171, 2, 51, // Opcode: FZEROS +/* 4350 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 4362 +/* 4354 */ MCD_OPC_CheckPredicate, 2, 177, 5, // Skip to: 5815 +/* 4358 */ MCD_OPC_Decode, 236, 1, 27, // Opcode: FNOR +/* 4362 */ MCD_OPC_FilterValue, 99, 8, 0, // Skip to: 4374 +/* 4366 */ MCD_OPC_CheckPredicate, 2, 165, 5, // Skip to: 5815 +/* 4370 */ MCD_OPC_Decode, 237, 1, 26, // Opcode: FNORS +/* 4374 */ MCD_OPC_FilterValue, 100, 8, 0, // Skip to: 4386 +/* 4378 */ MCD_OPC_CheckPredicate, 2, 153, 5, // Skip to: 5815 +/* 4382 */ MCD_OPC_Decode, 148, 1, 27, // Opcode: FANDNOT2 +/* 4386 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 4398 +/* 4390 */ MCD_OPC_CheckPredicate, 2, 141, 5, // Skip to: 5815 +/* 4394 */ MCD_OPC_Decode, 149, 1, 26, // Opcode: FANDNOT2S +/* 4398 */ MCD_OPC_FilterValue, 102, 14, 0, // Skip to: 4416 +/* 4402 */ MCD_OPC_CheckPredicate, 2, 129, 5, // Skip to: 5815 +/* 4406 */ MCD_OPC_CheckField, 14, 5, 0, 123, 5, // Skip to: 5815 +/* 4412 */ MCD_OPC_Decode, 240, 1, 24, // Opcode: FNOT2 +/* 4416 */ MCD_OPC_FilterValue, 103, 14, 0, // Skip to: 4434 +/* 4420 */ MCD_OPC_CheckPredicate, 2, 111, 5, // Skip to: 5815 +/* 4424 */ MCD_OPC_CheckField, 14, 5, 0, 105, 5, // Skip to: 5815 +/* 4430 */ MCD_OPC_Decode, 241, 1, 23, // Opcode: FNOT2S +/* 4434 */ MCD_OPC_FilterValue, 104, 8, 0, // Skip to: 4446 +/* 4438 */ MCD_OPC_CheckPredicate, 2, 93, 5, // Skip to: 5815 +/* 4442 */ MCD_OPC_Decode, 146, 1, 27, // Opcode: FANDNOT1 +/* 4446 */ MCD_OPC_FilterValue, 105, 8, 0, // Skip to: 4458 +/* 4450 */ MCD_OPC_CheckPredicate, 2, 81, 5, // Skip to: 5815 +/* 4454 */ MCD_OPC_Decode, 147, 1, 26, // Opcode: FANDNOT1S +/* 4458 */ MCD_OPC_FilterValue, 106, 14, 0, // Skip to: 4476 +/* 4462 */ MCD_OPC_CheckPredicate, 2, 69, 5, // Skip to: 5815 +/* 4466 */ MCD_OPC_CheckField, 0, 5, 0, 63, 5, // Skip to: 5815 +/* 4472 */ MCD_OPC_Decode, 238, 1, 52, // Opcode: FNOT1 +/* 4476 */ MCD_OPC_FilterValue, 107, 14, 0, // Skip to: 4494 +/* 4480 */ MCD_OPC_CheckPredicate, 2, 51, 5, // Skip to: 5815 +/* 4484 */ MCD_OPC_CheckField, 0, 5, 0, 45, 5, // Skip to: 5815 +/* 4490 */ MCD_OPC_Decode, 239, 1, 53, // Opcode: FNOT1S +/* 4494 */ MCD_OPC_FilterValue, 108, 8, 0, // Skip to: 4506 +/* 4498 */ MCD_OPC_CheckPredicate, 2, 33, 5, // Skip to: 5815 +/* 4502 */ MCD_OPC_Decode, 165, 2, 27, // Opcode: FXOR +/* 4506 */ MCD_OPC_FilterValue, 109, 8, 0, // Skip to: 4518 +/* 4510 */ MCD_OPC_CheckPredicate, 2, 21, 5, // Skip to: 5815 +/* 4514 */ MCD_OPC_Decode, 166, 2, 26, // Opcode: FXORS +/* 4518 */ MCD_OPC_FilterValue, 110, 8, 0, // Skip to: 4530 +/* 4522 */ MCD_OPC_CheckPredicate, 2, 9, 5, // Skip to: 5815 +/* 4526 */ MCD_OPC_Decode, 227, 1, 27, // Opcode: FNAND +/* 4530 */ MCD_OPC_FilterValue, 111, 8, 0, // Skip to: 4542 +/* 4534 */ MCD_OPC_CheckPredicate, 2, 253, 4, // Skip to: 5815 +/* 4538 */ MCD_OPC_Decode, 228, 1, 26, // Opcode: FNANDS +/* 4542 */ MCD_OPC_FilterValue, 112, 8, 0, // Skip to: 4554 +/* 4546 */ MCD_OPC_CheckPredicate, 2, 241, 4, // Skip to: 5815 +/* 4550 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: FAND +/* 4554 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 4566 +/* 4558 */ MCD_OPC_CheckPredicate, 2, 229, 4, // Skip to: 5815 +/* 4562 */ MCD_OPC_Decode, 150, 1, 26, // Opcode: FANDS +/* 4566 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 4578 +/* 4570 */ MCD_OPC_CheckPredicate, 2, 217, 4, // Skip to: 5815 +/* 4574 */ MCD_OPC_Decode, 163, 2, 27, // Opcode: FXNOR +/* 4578 */ MCD_OPC_FilterValue, 115, 8, 0, // Skip to: 4590 +/* 4582 */ MCD_OPC_CheckPredicate, 2, 205, 4, // Skip to: 5815 +/* 4586 */ MCD_OPC_Decode, 164, 2, 26, // Opcode: FXNORS +/* 4590 */ MCD_OPC_FilterValue, 116, 14, 0, // Skip to: 4608 +/* 4594 */ MCD_OPC_CheckPredicate, 2, 193, 4, // Skip to: 5815 +/* 4598 */ MCD_OPC_CheckField, 0, 5, 0, 187, 4, // Skip to: 5815 +/* 4604 */ MCD_OPC_Decode, 150, 2, 52, // Opcode: FSRC1 +/* 4608 */ MCD_OPC_FilterValue, 117, 14, 0, // Skip to: 4626 +/* 4612 */ MCD_OPC_CheckPredicate, 2, 175, 4, // Skip to: 5815 +/* 4616 */ MCD_OPC_CheckField, 0, 5, 0, 169, 4, // Skip to: 5815 +/* 4622 */ MCD_OPC_Decode, 151, 2, 53, // Opcode: FSRC1S +/* 4626 */ MCD_OPC_FilterValue, 118, 8, 0, // Skip to: 4638 +/* 4630 */ MCD_OPC_CheckPredicate, 2, 157, 4, // Skip to: 5815 +/* 4634 */ MCD_OPC_Decode, 248, 1, 27, // Opcode: FORNOT2 +/* 4638 */ MCD_OPC_FilterValue, 119, 8, 0, // Skip to: 4650 +/* 4642 */ MCD_OPC_CheckPredicate, 2, 145, 4, // Skip to: 5815 +/* 4646 */ MCD_OPC_Decode, 249, 1, 26, // Opcode: FORNOT2S +/* 4650 */ MCD_OPC_FilterValue, 120, 14, 0, // Skip to: 4668 +/* 4654 */ MCD_OPC_CheckPredicate, 2, 133, 4, // Skip to: 5815 +/* 4658 */ MCD_OPC_CheckField, 14, 5, 0, 127, 4, // Skip to: 5815 +/* 4664 */ MCD_OPC_Decode, 152, 2, 24, // Opcode: FSRC2 +/* 4668 */ MCD_OPC_FilterValue, 121, 14, 0, // Skip to: 4686 +/* 4672 */ MCD_OPC_CheckPredicate, 2, 115, 4, // Skip to: 5815 +/* 4676 */ MCD_OPC_CheckField, 14, 5, 0, 109, 4, // Skip to: 5815 +/* 4682 */ MCD_OPC_Decode, 153, 2, 23, // Opcode: FSRC2S +/* 4686 */ MCD_OPC_FilterValue, 122, 8, 0, // Skip to: 4698 +/* 4690 */ MCD_OPC_CheckPredicate, 2, 97, 4, // Skip to: 5815 +/* 4694 */ MCD_OPC_Decode, 246, 1, 27, // Opcode: FORNOT1 +/* 4698 */ MCD_OPC_FilterValue, 123, 8, 0, // Skip to: 4710 +/* 4702 */ MCD_OPC_CheckPredicate, 2, 85, 4, // Skip to: 5815 +/* 4706 */ MCD_OPC_Decode, 247, 1, 26, // Opcode: FORNOT1S +/* 4710 */ MCD_OPC_FilterValue, 124, 8, 0, // Skip to: 4722 +/* 4714 */ MCD_OPC_CheckPredicate, 2, 73, 4, // Skip to: 5815 +/* 4718 */ MCD_OPC_Decode, 245, 1, 27, // Opcode: FOR +/* 4722 */ MCD_OPC_FilterValue, 125, 8, 0, // Skip to: 4734 +/* 4726 */ MCD_OPC_CheckPredicate, 2, 61, 4, // Skip to: 5815 +/* 4730 */ MCD_OPC_Decode, 250, 1, 26, // Opcode: FORS +/* 4734 */ MCD_OPC_FilterValue, 126, 20, 0, // Skip to: 4758 +/* 4738 */ MCD_OPC_CheckPredicate, 2, 49, 4, // Skip to: 5815 +/* 4742 */ MCD_OPC_CheckField, 14, 5, 0, 43, 4, // Skip to: 5815 +/* 4748 */ MCD_OPC_CheckField, 0, 5, 0, 37, 4, // Skip to: 5815 +/* 4754 */ MCD_OPC_Decode, 243, 1, 50, // Opcode: FONE +/* 4758 */ MCD_OPC_FilterValue, 127, 20, 0, // Skip to: 4782 +/* 4762 */ MCD_OPC_CheckPredicate, 2, 25, 4, // Skip to: 5815 +/* 4766 */ MCD_OPC_CheckField, 14, 5, 0, 19, 4, // Skip to: 5815 +/* 4772 */ MCD_OPC_CheckField, 0, 5, 0, 13, 4, // Skip to: 5815 +/* 4778 */ MCD_OPC_Decode, 244, 1, 51, // Opcode: FONES +/* 4782 */ MCD_OPC_FilterValue, 128, 1, 26, 0, // Skip to: 4813 +/* 4787 */ MCD_OPC_CheckPredicate, 2, 0, 4, // Skip to: 5815 +/* 4791 */ MCD_OPC_CheckField, 25, 5, 0, 250, 3, // Skip to: 5815 +/* 4797 */ MCD_OPC_CheckField, 14, 5, 0, 244, 3, // Skip to: 5815 +/* 4803 */ MCD_OPC_CheckField, 0, 5, 0, 238, 3, // Skip to: 5815 +/* 4809 */ MCD_OPC_Decode, 136, 3, 4, // Opcode: SHUTDOWN +/* 4813 */ MCD_OPC_FilterValue, 129, 1, 26, 0, // Skip to: 4844 +/* 4818 */ MCD_OPC_CheckPredicate, 3, 225, 3, // Skip to: 5815 +/* 4822 */ MCD_OPC_CheckField, 25, 5, 0, 219, 3, // Skip to: 5815 +/* 4828 */ MCD_OPC_CheckField, 14, 5, 0, 213, 3, // Skip to: 5815 +/* 4834 */ MCD_OPC_CheckField, 0, 5, 0, 207, 3, // Skip to: 5815 +/* 4840 */ MCD_OPC_Decode, 137, 3, 4, // Opcode: SIAM +/* 4844 */ MCD_OPC_FilterValue, 144, 2, 14, 0, // Skip to: 4863 +/* 4849 */ MCD_OPC_CheckPredicate, 1, 194, 3, // Skip to: 5815 +/* 4853 */ MCD_OPC_CheckField, 14, 5, 0, 188, 3, // Skip to: 5815 +/* 4859 */ MCD_OPC_Decode, 199, 2, 54, // Opcode: MOVDTOX +/* 4863 */ MCD_OPC_FilterValue, 145, 2, 14, 0, // Skip to: 4882 +/* 4868 */ MCD_OPC_CheckPredicate, 1, 175, 3, // Skip to: 5815 +/* 4872 */ MCD_OPC_CheckField, 14, 5, 0, 169, 3, // Skip to: 5815 +/* 4878 */ MCD_OPC_Decode, 217, 2, 54, // Opcode: MOVSTOUW +/* 4882 */ MCD_OPC_FilterValue, 147, 2, 14, 0, // Skip to: 4901 +/* 4887 */ MCD_OPC_CheckPredicate, 1, 156, 3, // Skip to: 5815 +/* 4891 */ MCD_OPC_CheckField, 14, 5, 0, 150, 3, // Skip to: 5815 +/* 4897 */ MCD_OPC_Decode, 216, 2, 54, // Opcode: MOVSTOSW +/* 4901 */ MCD_OPC_FilterValue, 149, 2, 8, 0, // Skip to: 4914 +/* 4906 */ MCD_OPC_CheckPredicate, 1, 137, 3, // Skip to: 5815 +/* 4910 */ MCD_OPC_Decode, 225, 3, 10, // Opcode: XMULX +/* 4914 */ MCD_OPC_FilterValue, 151, 2, 8, 0, // Skip to: 4927 +/* 4919 */ MCD_OPC_CheckPredicate, 1, 124, 3, // Skip to: 5815 +/* 4923 */ MCD_OPC_Decode, 226, 3, 10, // Opcode: XMULXHI +/* 4927 */ MCD_OPC_FilterValue, 152, 2, 14, 0, // Skip to: 4946 +/* 4932 */ MCD_OPC_CheckPredicate, 1, 111, 3, // Skip to: 5815 +/* 4936 */ MCD_OPC_CheckField, 14, 5, 0, 105, 3, // Skip to: 5815 +/* 4942 */ MCD_OPC_Decode, 221, 2, 55, // Opcode: MOVXTOD +/* 4946 */ MCD_OPC_FilterValue, 153, 2, 14, 0, // Skip to: 4965 +/* 4951 */ MCD_OPC_CheckPredicate, 1, 92, 3, // Skip to: 5815 +/* 4955 */ MCD_OPC_CheckField, 14, 5, 0, 86, 3, // Skip to: 5815 +/* 4961 */ MCD_OPC_Decode, 218, 2, 55, // Opcode: MOVWTOS +/* 4965 */ MCD_OPC_FilterValue, 209, 2, 8, 0, // Skip to: 4978 +/* 4970 */ MCD_OPC_CheckPredicate, 1, 73, 3, // Skip to: 5815 +/* 4974 */ MCD_OPC_Decode, 182, 1, 45, // Opcode: FLCMPS +/* 4978 */ MCD_OPC_FilterValue, 210, 2, 64, 3, // Skip to: 5815 +/* 4983 */ MCD_OPC_CheckPredicate, 1, 60, 3, // Skip to: 5815 +/* 4987 */ MCD_OPC_Decode, 181, 1, 45, // Opcode: FLCMPD +/* 4991 */ MCD_OPC_FilterValue, 56, 25, 0, // Skip to: 5020 +/* 4995 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 4998 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5012 +/* 5002 */ MCD_OPC_CheckField, 5, 8, 0, 39, 3, // Skip to: 5815 +/* 5008 */ MCD_OPC_Decode, 174, 2, 56, // Opcode: JMPLrr +/* 5012 */ MCD_OPC_FilterValue, 1, 31, 3, // Skip to: 5815 +/* 5016 */ MCD_OPC_Decode, 173, 2, 56, // Opcode: JMPLri +/* 5020 */ MCD_OPC_FilterValue, 57, 37, 0, // Skip to: 5061 +/* 5024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5027 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5047 +/* 5031 */ MCD_OPC_CheckField, 25, 5, 0, 10, 3, // Skip to: 5815 +/* 5037 */ MCD_OPC_CheckField, 5, 8, 0, 4, 3, // Skip to: 5815 +/* 5043 */ MCD_OPC_Decode, 245, 2, 57, // Opcode: RETTrr +/* 5047 */ MCD_OPC_FilterValue, 1, 252, 2, // Skip to: 5815 +/* 5051 */ MCD_OPC_CheckField, 25, 5, 0, 246, 2, // Skip to: 5815 +/* 5057 */ MCD_OPC_Decode, 244, 2, 57, // Opcode: RETTri +/* 5061 */ MCD_OPC_FilterValue, 58, 115, 0, // Skip to: 5180 +/* 5065 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... +/* 5068 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5088 +/* 5072 */ MCD_OPC_CheckField, 29, 1, 0, 225, 2, // Skip to: 5815 +/* 5078 */ MCD_OPC_CheckField, 5, 3, 0, 219, 2, // Skip to: 5815 +/* 5084 */ MCD_OPC_Decode, 188, 3, 58, // Opcode: TICCrr +/* 5088 */ MCD_OPC_FilterValue, 16, 16, 0, // Skip to: 5108 +/* 5092 */ MCD_OPC_CheckField, 29, 1, 0, 205, 2, // Skip to: 5815 +/* 5098 */ MCD_OPC_CheckField, 5, 3, 0, 199, 2, // Skip to: 5815 +/* 5104 */ MCD_OPC_Decode, 199, 3, 58, // Opcode: TXCCrr +/* 5108 */ MCD_OPC_FilterValue, 32, 54, 0, // Skip to: 5166 +/* 5112 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 5115 */ MCD_OPC_FilterValue, 0, 184, 2, // Skip to: 5815 +/* 5119 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 5122 */ MCD_OPC_FilterValue, 3, 16, 0, // Skip to: 5142 +/* 5126 */ MCD_OPC_CheckField, 25, 4, 0, 30, 0, // Skip to: 5162 +/* 5132 */ MCD_OPC_CheckField, 14, 5, 1, 24, 0, // Skip to: 5162 +/* 5138 */ MCD_OPC_Decode, 181, 3, 4, // Opcode: TA3 +/* 5142 */ MCD_OPC_FilterValue, 5, 16, 0, // Skip to: 5162 +/* 5146 */ MCD_OPC_CheckField, 25, 4, 8, 10, 0, // Skip to: 5162 +/* 5152 */ MCD_OPC_CheckField, 14, 5, 0, 4, 0, // Skip to: 5162 +/* 5158 */ MCD_OPC_Decode, 182, 3, 4, // Opcode: TA5 +/* 5162 */ MCD_OPC_Decode, 187, 3, 59, // Opcode: TICCri +/* 5166 */ MCD_OPC_FilterValue, 48, 133, 2, // Skip to: 5815 +/* 5170 */ MCD_OPC_CheckField, 29, 1, 0, 127, 2, // Skip to: 5815 +/* 5176 */ MCD_OPC_Decode, 198, 3, 59, // Opcode: TXCCri +/* 5180 */ MCD_OPC_FilterValue, 60, 25, 0, // Skip to: 5209 +/* 5184 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5187 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5201 +/* 5191 */ MCD_OPC_CheckField, 5, 8, 0, 106, 2, // Skip to: 5815 +/* 5197 */ MCD_OPC_Decode, 247, 2, 8, // Opcode: SAVErr +/* 5201 */ MCD_OPC_FilterValue, 1, 98, 2, // Skip to: 5815 +/* 5205 */ MCD_OPC_Decode, 246, 2, 9, // Opcode: SAVEri +/* 5209 */ MCD_OPC_FilterValue, 61, 90, 2, // Skip to: 5815 +/* 5213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5216 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5230 +/* 5220 */ MCD_OPC_CheckField, 5, 8, 0, 77, 2, // Skip to: 5815 +/* 5226 */ MCD_OPC_Decode, 241, 2, 8, // Opcode: RESTORErr +/* 5230 */ MCD_OPC_FilterValue, 1, 69, 2, // Skip to: 5815 +/* 5234 */ MCD_OPC_Decode, 240, 2, 9, // Opcode: RESTOREri +/* 5238 */ MCD_OPC_FilterValue, 3, 61, 2, // Skip to: 5815 +/* 5242 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... +/* 5245 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 5274 +/* 5249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5252 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5266 +/* 5256 */ MCD_OPC_CheckField, 5, 8, 0, 41, 2, // Skip to: 5815 +/* 5262 */ MCD_OPC_Decode, 194, 2, 60, // Opcode: LDrr +/* 5266 */ MCD_OPC_FilterValue, 1, 33, 2, // Skip to: 5815 +/* 5270 */ MCD_OPC_Decode, 193, 2, 60, // Opcode: LDri +/* 5274 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 5303 +/* 5278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5295 +/* 5285 */ MCD_OPC_CheckField, 5, 8, 0, 12, 2, // Skip to: 5815 +/* 5291 */ MCD_OPC_Decode, 188, 2, 60, // Opcode: LDUBrr +/* 5295 */ MCD_OPC_FilterValue, 1, 4, 2, // Skip to: 5815 +/* 5299 */ MCD_OPC_Decode, 187, 2, 60, // Opcode: LDUBri +/* 5303 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 5332 +/* 5307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5324 +/* 5314 */ MCD_OPC_CheckField, 5, 8, 0, 239, 1, // Skip to: 5815 +/* 5320 */ MCD_OPC_Decode, 190, 2, 60, // Opcode: LDUHrr +/* 5324 */ MCD_OPC_FilterValue, 1, 231, 1, // Skip to: 5815 +/* 5328 */ MCD_OPC_Decode, 189, 2, 60, // Opcode: LDUHri +/* 5332 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 5361 +/* 5336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5353 +/* 5343 */ MCD_OPC_CheckField, 5, 8, 0, 210, 1, // Skip to: 5815 +/* 5349 */ MCD_OPC_Decode, 168, 3, 61, // Opcode: STrr +/* 5353 */ MCD_OPC_FilterValue, 1, 202, 1, // Skip to: 5815 +/* 5357 */ MCD_OPC_Decode, 167, 3, 61, // Opcode: STri +/* 5361 */ MCD_OPC_FilterValue, 5, 25, 0, // Skip to: 5390 +/* 5365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5382 +/* 5372 */ MCD_OPC_CheckField, 5, 8, 0, 181, 1, // Skip to: 5815 +/* 5378 */ MCD_OPC_Decode, 156, 3, 61, // Opcode: STBrr +/* 5382 */ MCD_OPC_FilterValue, 1, 173, 1, // Skip to: 5815 +/* 5386 */ MCD_OPC_Decode, 155, 3, 61, // Opcode: STBri +/* 5390 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 5419 +/* 5394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5411 +/* 5401 */ MCD_OPC_CheckField, 5, 8, 0, 152, 1, // Skip to: 5815 +/* 5407 */ MCD_OPC_Decode, 162, 3, 61, // Opcode: STHrr +/* 5411 */ MCD_OPC_FilterValue, 1, 144, 1, // Skip to: 5815 +/* 5415 */ MCD_OPC_Decode, 161, 3, 61, // Opcode: STHri +/* 5419 */ MCD_OPC_FilterValue, 8, 25, 0, // Skip to: 5448 +/* 5423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5440 +/* 5430 */ MCD_OPC_CheckField, 5, 8, 0, 123, 1, // Skip to: 5815 +/* 5436 */ MCD_OPC_Decode, 186, 2, 60, // Opcode: LDSWrr +/* 5440 */ MCD_OPC_FilterValue, 1, 115, 1, // Skip to: 5815 +/* 5444 */ MCD_OPC_Decode, 185, 2, 60, // Opcode: LDSWri +/* 5448 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 5477 +/* 5452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5469 +/* 5459 */ MCD_OPC_CheckField, 5, 8, 0, 94, 1, // Skip to: 5815 +/* 5465 */ MCD_OPC_Decode, 182, 2, 60, // Opcode: LDSBrr +/* 5469 */ MCD_OPC_FilterValue, 1, 86, 1, // Skip to: 5815 +/* 5473 */ MCD_OPC_Decode, 181, 2, 60, // Opcode: LDSBri +/* 5477 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 5506 +/* 5481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5498 +/* 5488 */ MCD_OPC_CheckField, 5, 8, 0, 65, 1, // Skip to: 5815 +/* 5494 */ MCD_OPC_Decode, 184, 2, 60, // Opcode: LDSHrr +/* 5498 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 5815 +/* 5502 */ MCD_OPC_Decode, 183, 2, 60, // Opcode: LDSHri +/* 5506 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 5535 +/* 5510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5527 +/* 5517 */ MCD_OPC_CheckField, 5, 8, 0, 36, 1, // Skip to: 5815 +/* 5523 */ MCD_OPC_Decode, 192, 2, 60, // Opcode: LDXrr +/* 5527 */ MCD_OPC_FilterValue, 1, 28, 1, // Skip to: 5815 +/* 5531 */ MCD_OPC_Decode, 191, 2, 60, // Opcode: LDXri +/* 5535 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 5564 +/* 5539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5542 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5556 +/* 5546 */ MCD_OPC_CheckField, 5, 8, 0, 7, 1, // Skip to: 5815 +/* 5552 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: STXrr +/* 5556 */ MCD_OPC_FilterValue, 1, 255, 0, // Skip to: 5815 +/* 5560 */ MCD_OPC_Decode, 165, 3, 61, // Opcode: STXri +/* 5564 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 5593 +/* 5568 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5571 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5585 +/* 5575 */ MCD_OPC_CheckField, 5, 8, 0, 234, 0, // Skip to: 5815 +/* 5581 */ MCD_OPC_Decode, 180, 3, 62, // Opcode: SWAPrr +/* 5585 */ MCD_OPC_FilterValue, 1, 226, 0, // Skip to: 5815 +/* 5589 */ MCD_OPC_Decode, 179, 3, 62, // Opcode: SWAPri +/* 5593 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 5622 +/* 5597 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5600 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5614 +/* 5604 */ MCD_OPC_CheckField, 5, 8, 0, 205, 0, // Skip to: 5815 +/* 5610 */ MCD_OPC_Decode, 178, 2, 63, // Opcode: LDFrr +/* 5614 */ MCD_OPC_FilterValue, 1, 197, 0, // Skip to: 5815 +/* 5618 */ MCD_OPC_Decode, 177, 2, 63, // Opcode: LDFri +/* 5622 */ MCD_OPC_FilterValue, 34, 33, 0, // Skip to: 5659 +/* 5626 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5629 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5647 +/* 5633 */ MCD_OPC_CheckPredicate, 0, 178, 0, // Skip to: 5815 +/* 5637 */ MCD_OPC_CheckField, 5, 8, 0, 172, 0, // Skip to: 5815 +/* 5643 */ MCD_OPC_Decode, 180, 2, 64, // Opcode: LDQFrr +/* 5647 */ MCD_OPC_FilterValue, 1, 164, 0, // Skip to: 5815 +/* 5651 */ MCD_OPC_CheckPredicate, 0, 160, 0, // Skip to: 5815 +/* 5655 */ MCD_OPC_Decode, 179, 2, 64, // Opcode: LDQFri +/* 5659 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 5688 +/* 5663 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5666 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5680 +/* 5670 */ MCD_OPC_CheckField, 5, 8, 0, 139, 0, // Skip to: 5815 +/* 5676 */ MCD_OPC_Decode, 176, 2, 65, // Opcode: LDDFrr +/* 5680 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 5815 +/* 5684 */ MCD_OPC_Decode, 175, 2, 65, // Opcode: LDDFri +/* 5688 */ MCD_OPC_FilterValue, 36, 25, 0, // Skip to: 5717 +/* 5692 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5695 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5709 +/* 5699 */ MCD_OPC_CheckField, 5, 8, 0, 110, 0, // Skip to: 5815 +/* 5705 */ MCD_OPC_Decode, 160, 3, 66, // Opcode: STFrr +/* 5709 */ MCD_OPC_FilterValue, 1, 102, 0, // Skip to: 5815 +/* 5713 */ MCD_OPC_Decode, 159, 3, 66, // Opcode: STFri +/* 5717 */ MCD_OPC_FilterValue, 38, 33, 0, // Skip to: 5754 +/* 5721 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5742 +/* 5728 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 5815 +/* 5732 */ MCD_OPC_CheckField, 5, 8, 0, 77, 0, // Skip to: 5815 +/* 5738 */ MCD_OPC_Decode, 164, 3, 67, // Opcode: STQFrr +/* 5742 */ MCD_OPC_FilterValue, 1, 69, 0, // Skip to: 5815 +/* 5746 */ MCD_OPC_CheckPredicate, 0, 65, 0, // Skip to: 5815 +/* 5750 */ MCD_OPC_Decode, 163, 3, 67, // Opcode: STQFri +/* 5754 */ MCD_OPC_FilterValue, 39, 25, 0, // Skip to: 5783 +/* 5758 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 5761 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5775 +/* 5765 */ MCD_OPC_CheckField, 5, 8, 0, 44, 0, // Skip to: 5815 +/* 5771 */ MCD_OPC_Decode, 158, 3, 68, // Opcode: STDFrr +/* 5775 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 5815 +/* 5779 */ MCD_OPC_Decode, 157, 3, 68, // Opcode: STDFri +/* 5783 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 5801 +/* 5787 */ MCD_OPC_CheckPredicate, 0, 24, 0, // Skip to: 5815 +/* 5791 */ MCD_OPC_CheckField, 5, 9, 128, 1, 17, 0, // Skip to: 5815 +/* 5798 */ MCD_OPC_Decode, 120, 69, // Opcode: CASrr +/* 5801 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 5815 +/* 5805 */ MCD_OPC_CheckField, 5, 9, 128, 1, 3, 0, // Skip to: 5815 +/* 5812 */ MCD_OPC_Decode, 119, 70, // Opcode: CASXrr +/* 5815 */ MCD_OPC_Fail, + 0 +}; + +static bool getbool(uint64_t b) +{ + return b != 0; +} + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + switch (Idx) { + default: // llvm_unreachable("Invalid index!"); + case 0: + return getbool(Bits & Sparc_FeatureV9); + case 1: + return getbool(Bits & Sparc_FeatureVIS3); + case 2: + return getbool(Bits & Sparc_FeatureVIS); + case 3: + return getbool(Bits & Sparc_FeatureVIS2); + } +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 1: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 2: \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 3: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 14) << 0; \ + tmp |= fieldname(insn, 20, 2) << 14; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 4: \ + return S; \ + case 5: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 0, 30); \ + if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 16: \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 18: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 19: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 11); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 20: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 11); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 21: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 23: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 37: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 38: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 39: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 40: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 41: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 42: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 43: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 47: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 52: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 53: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 54: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + if (DecodeJMPL(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 57: \ + if (DecodeReturn(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 58: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 59: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 60: \ + if (DecodeLoadInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + if (DecodeStoreInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + if (DecodeSWAP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + if (DecodeLoadFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + if (DecodeLoadQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 65: \ + if (DecodeLoadDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 66: \ + if (DecodeStoreFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + if (DecodeStoreQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + if (DecodeStoreDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 69: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 70: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcGenInstrInfo.inc new file mode 100644 index 0000000..89bf034 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcGenInstrInfo.inc @@ -0,0 +1,514 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + SP_PHI = 0, + SP_INLINEASM = 1, + SP_CFI_INSTRUCTION = 2, + SP_EH_LABEL = 3, + SP_GC_LABEL = 4, + SP_KILL = 5, + SP_EXTRACT_SUBREG = 6, + SP_INSERT_SUBREG = 7, + SP_IMPLICIT_DEF = 8, + SP_SUBREG_TO_REG = 9, + SP_COPY_TO_REGCLASS = 10, + SP_DBG_VALUE = 11, + SP_REG_SEQUENCE = 12, + SP_COPY = 13, + SP_BUNDLE = 14, + SP_LIFETIME_START = 15, + SP_LIFETIME_END = 16, + SP_STACKMAP = 17, + SP_PATCHPOINT = 18, + SP_LOAD_STACK_GUARD = 19, + SP_STATEPOINT = 20, + SP_FRAME_ALLOC = 21, + SP_ADDCCri = 22, + SP_ADDCCrr = 23, + SP_ADDCri = 24, + SP_ADDCrr = 25, + SP_ADDEri = 26, + SP_ADDErr = 27, + SP_ADDXC = 28, + SP_ADDXCCC = 29, + SP_ADDXri = 30, + SP_ADDXrr = 31, + SP_ADDri = 32, + SP_ADDrr = 33, + SP_ADJCALLSTACKDOWN = 34, + SP_ADJCALLSTACKUP = 35, + SP_ALIGNADDR = 36, + SP_ALIGNADDRL = 37, + SP_ANDCCri = 38, + SP_ANDCCrr = 39, + SP_ANDNCCri = 40, + SP_ANDNCCrr = 41, + SP_ANDNri = 42, + SP_ANDNrr = 43, + SP_ANDXNrr = 44, + SP_ANDXri = 45, + SP_ANDXrr = 46, + SP_ANDri = 47, + SP_ANDrr = 48, + SP_ARRAY16 = 49, + SP_ARRAY32 = 50, + SP_ARRAY8 = 51, + SP_ATOMIC_LOAD_ADD_32 = 52, + SP_ATOMIC_LOAD_ADD_64 = 53, + SP_ATOMIC_LOAD_AND_32 = 54, + SP_ATOMIC_LOAD_AND_64 = 55, + SP_ATOMIC_LOAD_MAX_32 = 56, + SP_ATOMIC_LOAD_MAX_64 = 57, + SP_ATOMIC_LOAD_MIN_32 = 58, + SP_ATOMIC_LOAD_MIN_64 = 59, + SP_ATOMIC_LOAD_NAND_32 = 60, + SP_ATOMIC_LOAD_NAND_64 = 61, + SP_ATOMIC_LOAD_OR_32 = 62, + SP_ATOMIC_LOAD_OR_64 = 63, + SP_ATOMIC_LOAD_SUB_32 = 64, + SP_ATOMIC_LOAD_SUB_64 = 65, + SP_ATOMIC_LOAD_UMAX_32 = 66, + SP_ATOMIC_LOAD_UMAX_64 = 67, + SP_ATOMIC_LOAD_UMIN_32 = 68, + SP_ATOMIC_LOAD_UMIN_64 = 69, + SP_ATOMIC_LOAD_XOR_32 = 70, + SP_ATOMIC_LOAD_XOR_64 = 71, + SP_ATOMIC_SWAP_64 = 72, + SP_BA = 73, + SP_BCOND = 74, + SP_BCONDA = 75, + SP_BINDri = 76, + SP_BINDrr = 77, + SP_BMASK = 78, + SP_BPFCC = 79, + SP_BPFCCA = 80, + SP_BPFCCANT = 81, + SP_BPFCCNT = 82, + SP_BPGEZapn = 83, + SP_BPGEZapt = 84, + SP_BPGEZnapn = 85, + SP_BPGEZnapt = 86, + SP_BPGZapn = 87, + SP_BPGZapt = 88, + SP_BPGZnapn = 89, + SP_BPGZnapt = 90, + SP_BPICC = 91, + SP_BPICCA = 92, + SP_BPICCANT = 93, + SP_BPICCNT = 94, + SP_BPLEZapn = 95, + SP_BPLEZapt = 96, + SP_BPLEZnapn = 97, + SP_BPLEZnapt = 98, + SP_BPLZapn = 99, + SP_BPLZapt = 100, + SP_BPLZnapn = 101, + SP_BPLZnapt = 102, + SP_BPNZapn = 103, + SP_BPNZapt = 104, + SP_BPNZnapn = 105, + SP_BPNZnapt = 106, + SP_BPXCC = 107, + SP_BPXCCA = 108, + SP_BPXCCANT = 109, + SP_BPXCCNT = 110, + SP_BPZapn = 111, + SP_BPZapt = 112, + SP_BPZnapn = 113, + SP_BPZnapt = 114, + SP_BSHUFFLE = 115, + SP_CALL = 116, + SP_CALLri = 117, + SP_CALLrr = 118, + SP_CASXrr = 119, + SP_CASrr = 120, + SP_CMASK16 = 121, + SP_CMASK32 = 122, + SP_CMASK8 = 123, + SP_CMPri = 124, + SP_CMPrr = 125, + SP_EDGE16 = 126, + SP_EDGE16L = 127, + SP_EDGE16LN = 128, + SP_EDGE16N = 129, + SP_EDGE32 = 130, + SP_EDGE32L = 131, + SP_EDGE32LN = 132, + SP_EDGE32N = 133, + SP_EDGE8 = 134, + SP_EDGE8L = 135, + SP_EDGE8LN = 136, + SP_EDGE8N = 137, + SP_FABSD = 138, + SP_FABSQ = 139, + SP_FABSS = 140, + SP_FADDD = 141, + SP_FADDQ = 142, + SP_FADDS = 143, + SP_FALIGNADATA = 144, + SP_FAND = 145, + SP_FANDNOT1 = 146, + SP_FANDNOT1S = 147, + SP_FANDNOT2 = 148, + SP_FANDNOT2S = 149, + SP_FANDS = 150, + SP_FBCOND = 151, + SP_FBCONDA = 152, + SP_FCHKSM16 = 153, + SP_FCMPD = 154, + SP_FCMPEQ16 = 155, + SP_FCMPEQ32 = 156, + SP_FCMPGT16 = 157, + SP_FCMPGT32 = 158, + SP_FCMPLE16 = 159, + SP_FCMPLE32 = 160, + SP_FCMPNE16 = 161, + SP_FCMPNE32 = 162, + SP_FCMPQ = 163, + SP_FCMPS = 164, + SP_FDIVD = 165, + SP_FDIVQ = 166, + SP_FDIVS = 167, + SP_FDMULQ = 168, + SP_FDTOI = 169, + SP_FDTOQ = 170, + SP_FDTOS = 171, + SP_FDTOX = 172, + SP_FEXPAND = 173, + SP_FHADDD = 174, + SP_FHADDS = 175, + SP_FHSUBD = 176, + SP_FHSUBS = 177, + SP_FITOD = 178, + SP_FITOQ = 179, + SP_FITOS = 180, + SP_FLCMPD = 181, + SP_FLCMPS = 182, + SP_FLUSHW = 183, + SP_FMEAN16 = 184, + SP_FMOVD = 185, + SP_FMOVD_FCC = 186, + SP_FMOVD_ICC = 187, + SP_FMOVD_XCC = 188, + SP_FMOVQ = 189, + SP_FMOVQ_FCC = 190, + SP_FMOVQ_ICC = 191, + SP_FMOVQ_XCC = 192, + SP_FMOVRGEZD = 193, + SP_FMOVRGEZQ = 194, + SP_FMOVRGEZS = 195, + SP_FMOVRGZD = 196, + SP_FMOVRGZQ = 197, + SP_FMOVRGZS = 198, + SP_FMOVRLEZD = 199, + SP_FMOVRLEZQ = 200, + SP_FMOVRLEZS = 201, + SP_FMOVRLZD = 202, + SP_FMOVRLZQ = 203, + SP_FMOVRLZS = 204, + SP_FMOVRNZD = 205, + SP_FMOVRNZQ = 206, + SP_FMOVRNZS = 207, + SP_FMOVRZD = 208, + SP_FMOVRZQ = 209, + SP_FMOVRZS = 210, + SP_FMOVS = 211, + SP_FMOVS_FCC = 212, + SP_FMOVS_ICC = 213, + SP_FMOVS_XCC = 214, + SP_FMUL8SUX16 = 215, + SP_FMUL8ULX16 = 216, + SP_FMUL8X16 = 217, + SP_FMUL8X16AL = 218, + SP_FMUL8X16AU = 219, + SP_FMULD = 220, + SP_FMULD8SUX16 = 221, + SP_FMULD8ULX16 = 222, + SP_FMULQ = 223, + SP_FMULS = 224, + SP_FNADDD = 225, + SP_FNADDS = 226, + SP_FNAND = 227, + SP_FNANDS = 228, + SP_FNEGD = 229, + SP_FNEGQ = 230, + SP_FNEGS = 231, + SP_FNHADDD = 232, + SP_FNHADDS = 233, + SP_FNMULD = 234, + SP_FNMULS = 235, + SP_FNOR = 236, + SP_FNORS = 237, + SP_FNOT1 = 238, + SP_FNOT1S = 239, + SP_FNOT2 = 240, + SP_FNOT2S = 241, + SP_FNSMULD = 242, + SP_FONE = 243, + SP_FONES = 244, + SP_FOR = 245, + SP_FORNOT1 = 246, + SP_FORNOT1S = 247, + SP_FORNOT2 = 248, + SP_FORNOT2S = 249, + SP_FORS = 250, + SP_FPACK16 = 251, + SP_FPACK32 = 252, + SP_FPACKFIX = 253, + SP_FPADD16 = 254, + SP_FPADD16S = 255, + SP_FPADD32 = 256, + SP_FPADD32S = 257, + SP_FPADD64 = 258, + SP_FPMERGE = 259, + SP_FPSUB16 = 260, + SP_FPSUB16S = 261, + SP_FPSUB32 = 262, + SP_FPSUB32S = 263, + SP_FQTOD = 264, + SP_FQTOI = 265, + SP_FQTOS = 266, + SP_FQTOX = 267, + SP_FSLAS16 = 268, + SP_FSLAS32 = 269, + SP_FSLL16 = 270, + SP_FSLL32 = 271, + SP_FSMULD = 272, + SP_FSQRTD = 273, + SP_FSQRTQ = 274, + SP_FSQRTS = 275, + SP_FSRA16 = 276, + SP_FSRA32 = 277, + SP_FSRC1 = 278, + SP_FSRC1S = 279, + SP_FSRC2 = 280, + SP_FSRC2S = 281, + SP_FSRL16 = 282, + SP_FSRL32 = 283, + SP_FSTOD = 284, + SP_FSTOI = 285, + SP_FSTOQ = 286, + SP_FSTOX = 287, + SP_FSUBD = 288, + SP_FSUBQ = 289, + SP_FSUBS = 290, + SP_FXNOR = 291, + SP_FXNORS = 292, + SP_FXOR = 293, + SP_FXORS = 294, + SP_FXTOD = 295, + SP_FXTOQ = 296, + SP_FXTOS = 297, + SP_FZERO = 298, + SP_FZEROS = 299, + SP_GETPCX = 300, + SP_JMPLri = 301, + SP_JMPLrr = 302, + SP_LDDFri = 303, + SP_LDDFrr = 304, + SP_LDFri = 305, + SP_LDFrr = 306, + SP_LDQFri = 307, + SP_LDQFrr = 308, + SP_LDSBri = 309, + SP_LDSBrr = 310, + SP_LDSHri = 311, + SP_LDSHrr = 312, + SP_LDSWri = 313, + SP_LDSWrr = 314, + SP_LDUBri = 315, + SP_LDUBrr = 316, + SP_LDUHri = 317, + SP_LDUHrr = 318, + SP_LDXri = 319, + SP_LDXrr = 320, + SP_LDri = 321, + SP_LDrr = 322, + SP_LEAX_ADDri = 323, + SP_LEA_ADDri = 324, + SP_LZCNT = 325, + SP_MEMBARi = 326, + SP_MOVDTOX = 327, + SP_MOVFCCri = 328, + SP_MOVFCCrr = 329, + SP_MOVICCri = 330, + SP_MOVICCrr = 331, + SP_MOVRGEZri = 332, + SP_MOVRGEZrr = 333, + SP_MOVRGZri = 334, + SP_MOVRGZrr = 335, + SP_MOVRLEZri = 336, + SP_MOVRLEZrr = 337, + SP_MOVRLZri = 338, + SP_MOVRLZrr = 339, + SP_MOVRNZri = 340, + SP_MOVRNZrr = 341, + SP_MOVRRZri = 342, + SP_MOVRRZrr = 343, + SP_MOVSTOSW = 344, + SP_MOVSTOUW = 345, + SP_MOVWTOS = 346, + SP_MOVXCCri = 347, + SP_MOVXCCrr = 348, + SP_MOVXTOD = 349, + SP_MULXri = 350, + SP_MULXrr = 351, + SP_NOP = 352, + SP_ORCCri = 353, + SP_ORCCrr = 354, + SP_ORNCCri = 355, + SP_ORNCCrr = 356, + SP_ORNri = 357, + SP_ORNrr = 358, + SP_ORXNrr = 359, + SP_ORXri = 360, + SP_ORXrr = 361, + SP_ORri = 362, + SP_ORrr = 363, + SP_PDIST = 364, + SP_PDISTN = 365, + SP_POPCrr = 366, + SP_RDY = 367, + SP_RESTOREri = 368, + SP_RESTORErr = 369, + SP_RET = 370, + SP_RETL = 371, + SP_RETTri = 372, + SP_RETTrr = 373, + SP_SAVEri = 374, + SP_SAVErr = 375, + SP_SDIVCCri = 376, + SP_SDIVCCrr = 377, + SP_SDIVXri = 378, + SP_SDIVXrr = 379, + SP_SDIVri = 380, + SP_SDIVrr = 381, + SP_SELECT_CC_DFP_FCC = 382, + SP_SELECT_CC_DFP_ICC = 383, + SP_SELECT_CC_FP_FCC = 384, + SP_SELECT_CC_FP_ICC = 385, + SP_SELECT_CC_Int_FCC = 386, + SP_SELECT_CC_Int_ICC = 387, + SP_SELECT_CC_QFP_FCC = 388, + SP_SELECT_CC_QFP_ICC = 389, + SP_SETHIXi = 390, + SP_SETHIi = 391, + SP_SHUTDOWN = 392, + SP_SIAM = 393, + SP_SLLXri = 394, + SP_SLLXrr = 395, + SP_SLLri = 396, + SP_SLLrr = 397, + SP_SMULCCri = 398, + SP_SMULCCrr = 399, + SP_SMULri = 400, + SP_SMULrr = 401, + SP_SRAXri = 402, + SP_SRAXrr = 403, + SP_SRAri = 404, + SP_SRArr = 405, + SP_SRLXri = 406, + SP_SRLXrr = 407, + SP_SRLri = 408, + SP_SRLrr = 409, + SP_STBAR = 410, + SP_STBri = 411, + SP_STBrr = 412, + SP_STDFri = 413, + SP_STDFrr = 414, + SP_STFri = 415, + SP_STFrr = 416, + SP_STHri = 417, + SP_STHrr = 418, + SP_STQFri = 419, + SP_STQFrr = 420, + SP_STXri = 421, + SP_STXrr = 422, + SP_STri = 423, + SP_STrr = 424, + SP_SUBCCri = 425, + SP_SUBCCrr = 426, + SP_SUBCri = 427, + SP_SUBCrr = 428, + SP_SUBEri = 429, + SP_SUBErr = 430, + SP_SUBXri = 431, + SP_SUBXrr = 432, + SP_SUBri = 433, + SP_SUBrr = 434, + SP_SWAPri = 435, + SP_SWAPrr = 436, + SP_TA3 = 437, + SP_TA5 = 438, + SP_TADDCCTVri = 439, + SP_TADDCCTVrr = 440, + SP_TADDCCri = 441, + SP_TADDCCrr = 442, + SP_TICCri = 443, + SP_TICCrr = 444, + SP_TLS_ADDXrr = 445, + SP_TLS_ADDrr = 446, + SP_TLS_CALL = 447, + SP_TLS_LDXrr = 448, + SP_TLS_LDrr = 449, + SP_TSUBCCTVri = 450, + SP_TSUBCCTVrr = 451, + SP_TSUBCCri = 452, + SP_TSUBCCrr = 453, + SP_TXCCri = 454, + SP_TXCCrr = 455, + SP_UDIVCCri = 456, + SP_UDIVCCrr = 457, + SP_UDIVXri = 458, + SP_UDIVXrr = 459, + SP_UDIVri = 460, + SP_UDIVrr = 461, + SP_UMULCCri = 462, + SP_UMULCCrr = 463, + SP_UMULXHI = 464, + SP_UMULri = 465, + SP_UMULrr = 466, + SP_UNIMP = 467, + SP_V9FCMPD = 468, + SP_V9FCMPED = 469, + SP_V9FCMPEQ = 470, + SP_V9FCMPES = 471, + SP_V9FCMPQ = 472, + SP_V9FCMPS = 473, + SP_V9FMOVD_FCC = 474, + SP_V9FMOVQ_FCC = 475, + SP_V9FMOVS_FCC = 476, + SP_V9MOVFCCri = 477, + SP_V9MOVFCCrr = 478, + SP_WRYri = 479, + SP_WRYrr = 480, + SP_XMULX = 481, + SP_XMULXHI = 482, + SP_XNORCCri = 483, + SP_XNORCCrr = 484, + SP_XNORXrr = 485, + SP_XNORri = 486, + SP_XNORrr = 487, + SP_XORCCri = 488, + SP_XORCCrr = 489, + SP_XORXri = 490, + SP_XORXrr = 491, + SP_XORri = 492, + SP_XORrr = 493, + SP_INSTRUCTION_LIST_END = 494 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcGenRegisterInfo.inc new file mode 100644 index 0000000..a59c852 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcGenRegisterInfo.inc @@ -0,0 +1,451 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + SP_NoRegister, + SP_ICC = 1, + SP_Y = 2, + SP_D0 = 3, + SP_D1 = 4, + SP_D2 = 5, + SP_D3 = 6, + SP_D4 = 7, + SP_D5 = 8, + SP_D6 = 9, + SP_D7 = 10, + SP_D8 = 11, + SP_D9 = 12, + SP_D10 = 13, + SP_D11 = 14, + SP_D12 = 15, + SP_D13 = 16, + SP_D14 = 17, + SP_D15 = 18, + SP_D16 = 19, + SP_D17 = 20, + SP_D18 = 21, + SP_D19 = 22, + SP_D20 = 23, + SP_D21 = 24, + SP_D22 = 25, + SP_D23 = 26, + SP_D24 = 27, + SP_D25 = 28, + SP_D26 = 29, + SP_D27 = 30, + SP_D28 = 31, + SP_D29 = 32, + SP_D30 = 33, + SP_D31 = 34, + SP_F0 = 35, + SP_F1 = 36, + SP_F2 = 37, + SP_F3 = 38, + SP_F4 = 39, + SP_F5 = 40, + SP_F6 = 41, + SP_F7 = 42, + SP_F8 = 43, + SP_F9 = 44, + SP_F10 = 45, + SP_F11 = 46, + SP_F12 = 47, + SP_F13 = 48, + SP_F14 = 49, + SP_F15 = 50, + SP_F16 = 51, + SP_F17 = 52, + SP_F18 = 53, + SP_F19 = 54, + SP_F20 = 55, + SP_F21 = 56, + SP_F22 = 57, + SP_F23 = 58, + SP_F24 = 59, + SP_F25 = 60, + SP_F26 = 61, + SP_F27 = 62, + SP_F28 = 63, + SP_F29 = 64, + SP_F30 = 65, + SP_F31 = 66, + SP_FCC0 = 67, + SP_FCC1 = 68, + SP_FCC2 = 69, + SP_FCC3 = 70, + SP_G0 = 71, + SP_G1 = 72, + SP_G2 = 73, + SP_G3 = 74, + SP_G4 = 75, + SP_G5 = 76, + SP_G6 = 77, + SP_G7 = 78, + SP_I0 = 79, + SP_I1 = 80, + SP_I2 = 81, + SP_I3 = 82, + SP_I4 = 83, + SP_I5 = 84, + SP_I6 = 85, + SP_I7 = 86, + SP_L0 = 87, + SP_L1 = 88, + SP_L2 = 89, + SP_L3 = 90, + SP_L4 = 91, + SP_L5 = 92, + SP_L6 = 93, + SP_L7 = 94, + SP_O0 = 95, + SP_O1 = 96, + SP_O2 = 97, + SP_O3 = 98, + SP_O4 = 99, + SP_O5 = 100, + SP_O6 = 101, + SP_O7 = 102, + SP_Q0 = 103, + SP_Q1 = 104, + SP_Q2 = 105, + SP_Q3 = 106, + SP_Q4 = 107, + SP_Q5 = 108, + SP_Q6 = 109, + SP_Q7 = 110, + SP_Q8 = 111, + SP_Q9 = 112, + SP_Q10 = 113, + SP_Q11 = 114, + SP_Q12 = 115, + SP_Q13 = 116, + SP_Q14 = 117, + SP_Q15 = 118, + SP_NUM_TARGET_REGS // 119 +}; + +// Register classes +enum { + SP_FCCRegsRegClassID = 0, + SP_FPRegsRegClassID = 1, + SP_IntRegsRegClassID = 2, + SP_DFPRegsRegClassID = 3, + SP_I64RegsRegClassID = 4, + SP_DFPRegs_with_sub_evenRegClassID = 5, + SP_QFPRegsRegClassID = 6, + SP_QFPRegs_with_sub_evenRegClassID = 7 +}; + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg SparcRegDiffLists[] = { + /* 0 */ 65126, 1, 1, 1, 0, + /* 5 */ 32, 1, 0, + /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, + /* 15 */ 34, 1, 0, + /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, + /* 25 */ 36, 1, 0, + /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, + /* 35 */ 38, 1, 0, + /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, + /* 45 */ 40, 1, 0, + /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, + /* 55 */ 42, 1, 0, + /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, + /* 65 */ 44, 1, 0, + /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, + /* 75 */ 46, 1, 0, + /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, + /* 85 */ 65348, 1, 0, + /* 88 */ 65444, 1, 0, + /* 91 */ 65445, 1, 0, + /* 94 */ 65446, 1, 0, + /* 97 */ 65447, 1, 0, + /* 100 */ 65448, 1, 0, + /* 103 */ 65449, 1, 0, + /* 106 */ 65450, 1, 0, + /* 109 */ 65451, 1, 0, + /* 112 */ 65532, 1, 0, + /* 115 */ 15, 0, + /* 117 */ 84, 0, + /* 119 */ 85, 0, + /* 121 */ 86, 0, + /* 123 */ 87, 0, + /* 125 */ 88, 0, + /* 127 */ 89, 0, + /* 129 */ 90, 0, + /* 131 */ 91, 0, + /* 133 */ 65488, 92, 0, + /* 136 */ 65489, 92, 0, + /* 139 */ 65489, 93, 0, + /* 142 */ 65490, 93, 0, + /* 145 */ 65491, 93, 0, + /* 148 */ 65491, 94, 0, + /* 151 */ 65492, 94, 0, + /* 154 */ 65493, 94, 0, + /* 157 */ 65493, 95, 0, + /* 160 */ 65494, 95, 0, + /* 163 */ 65495, 95, 0, + /* 166 */ 65495, 96, 0, + /* 169 */ 65496, 96, 0, + /* 172 */ 65497, 96, 0, + /* 175 */ 65497, 97, 0, + /* 178 */ 65498, 97, 0, + /* 181 */ 65499, 97, 0, + /* 184 */ 65499, 98, 0, + /* 187 */ 65500, 98, 0, + /* 190 */ 65501, 98, 0, + /* 193 */ 65501, 99, 0, + /* 196 */ 65502, 99, 0, + /* 199 */ 65503, 99, 0, + /* 202 */ 65503, 100, 0, + /* 205 */ 65504, 100, 0, + /* 208 */ 65503, 0, + /* 210 */ 65519, 0, + /* 212 */ 65535, 0, +}; + +static const uint16_t SparcSubRegIdxLists[] = { + /* 0 */ 1, 3, 0, + /* 3 */ 2, 4, 0, + /* 6 */ 2, 1, 3, 4, 5, 6, 0, +}; + +static MCRegisterDesc SparcRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 406, 4, 4, 2, 3393, 0 }, + { 410, 4, 4, 2, 3393, 0 }, + { 33, 5, 203, 0, 1794, 2 }, + { 87, 12, 194, 0, 1794, 2 }, + { 133, 15, 194, 0, 1794, 2 }, + { 179, 22, 185, 0, 1794, 2 }, + { 220, 25, 185, 0, 1794, 2 }, + { 261, 32, 176, 0, 1794, 2 }, + { 298, 35, 176, 0, 1794, 2 }, + { 335, 42, 167, 0, 1794, 2 }, + { 372, 45, 167, 0, 1794, 2 }, + { 397, 52, 158, 0, 1794, 2 }, + { 0, 55, 158, 0, 1794, 2 }, + { 54, 62, 149, 0, 1794, 2 }, + { 108, 65, 149, 0, 1794, 2 }, + { 154, 72, 140, 0, 1794, 2 }, + { 200, 75, 140, 0, 1794, 2 }, + { 241, 82, 134, 0, 1794, 2 }, + { 282, 4, 134, 2, 1841, 0 }, + { 319, 4, 131, 2, 1841, 0 }, + { 356, 4, 131, 2, 1841, 0 }, + { 381, 4, 129, 2, 1841, 0 }, + { 12, 4, 129, 2, 1841, 0 }, + { 66, 4, 127, 2, 1841, 0 }, + { 120, 4, 127, 2, 1841, 0 }, + { 166, 4, 125, 2, 1841, 0 }, + { 212, 4, 125, 2, 1841, 0 }, + { 253, 4, 123, 2, 1841, 0 }, + { 290, 4, 123, 2, 1841, 0 }, + { 327, 4, 121, 2, 1841, 0 }, + { 364, 4, 121, 2, 1841, 0 }, + { 389, 4, 119, 2, 1841, 0 }, + { 20, 4, 119, 2, 1841, 0 }, + { 74, 4, 117, 2, 1841, 0 }, + { 36, 4, 205, 2, 3329, 0 }, + { 90, 4, 202, 2, 3329, 0 }, + { 136, 4, 199, 2, 3329, 0 }, + { 182, 4, 196, 2, 3329, 0 }, + { 223, 4, 196, 2, 3329, 0 }, + { 264, 4, 193, 2, 3329, 0 }, + { 301, 4, 190, 2, 3329, 0 }, + { 338, 4, 187, 2, 3329, 0 }, + { 375, 4, 187, 2, 3329, 0 }, + { 400, 4, 184, 2, 3329, 0 }, + { 4, 4, 181, 2, 3329, 0 }, + { 58, 4, 178, 2, 3329, 0 }, + { 112, 4, 178, 2, 3329, 0 }, + { 158, 4, 175, 2, 3329, 0 }, + { 204, 4, 172, 2, 3329, 0 }, + { 245, 4, 169, 2, 3329, 0 }, + { 286, 4, 169, 2, 3329, 0 }, + { 323, 4, 166, 2, 3329, 0 }, + { 360, 4, 163, 2, 3329, 0 }, + { 385, 4, 160, 2, 3329, 0 }, + { 16, 4, 160, 2, 3329, 0 }, + { 70, 4, 157, 2, 3329, 0 }, + { 124, 4, 154, 2, 3329, 0 }, + { 170, 4, 151, 2, 3329, 0 }, + { 216, 4, 151, 2, 3329, 0 }, + { 257, 4, 148, 2, 3329, 0 }, + { 294, 4, 145, 2, 3329, 0 }, + { 331, 4, 142, 2, 3329, 0 }, + { 368, 4, 142, 2, 3329, 0 }, + { 393, 4, 139, 2, 3329, 0 }, + { 24, 4, 136, 2, 3329, 0 }, + { 78, 4, 133, 2, 3329, 0 }, + { 28, 4, 4, 2, 3361, 0 }, + { 82, 4, 4, 2, 3361, 0 }, + { 128, 4, 4, 2, 3361, 0 }, + { 174, 4, 4, 2, 3361, 0 }, + { 39, 4, 4, 2, 3361, 0 }, + { 93, 4, 4, 2, 3361, 0 }, + { 139, 4, 4, 2, 3361, 0 }, + { 185, 4, 4, 2, 3361, 0 }, + { 226, 4, 4, 2, 3361, 0 }, + { 267, 4, 4, 2, 3361, 0 }, + { 304, 4, 4, 2, 3361, 0 }, + { 341, 4, 4, 2, 3361, 0 }, + { 42, 4, 4, 2, 3361, 0 }, + { 96, 4, 4, 2, 3361, 0 }, + { 142, 4, 4, 2, 3361, 0 }, + { 188, 4, 4, 2, 3361, 0 }, + { 229, 4, 4, 2, 3361, 0 }, + { 270, 4, 4, 2, 3361, 0 }, + { 307, 4, 4, 2, 3361, 0 }, + { 344, 4, 4, 2, 3361, 0 }, + { 45, 4, 4, 2, 3361, 0 }, + { 99, 4, 4, 2, 3361, 0 }, + { 145, 4, 4, 2, 3361, 0 }, + { 191, 4, 4, 2, 3361, 0 }, + { 232, 4, 4, 2, 3361, 0 }, + { 273, 4, 4, 2, 3361, 0 }, + { 310, 4, 4, 2, 3361, 0 }, + { 347, 4, 4, 2, 3361, 0 }, + { 48, 4, 4, 2, 3361, 0 }, + { 102, 4, 4, 2, 3361, 0 }, + { 148, 4, 4, 2, 3361, 0 }, + { 194, 4, 4, 2, 3361, 0 }, + { 235, 4, 4, 2, 3361, 0 }, + { 276, 4, 4, 2, 3361, 0 }, + { 313, 4, 4, 2, 3361, 0 }, + { 350, 4, 4, 2, 3361, 0 }, + { 51, 8, 4, 6, 4, 5 }, + { 105, 18, 4, 6, 4, 5 }, + { 151, 28, 4, 6, 4, 5 }, + { 197, 38, 4, 6, 4, 5 }, + { 238, 48, 4, 6, 4, 5 }, + { 279, 58, 4, 6, 4, 5 }, + { 316, 68, 4, 6, 4, 5 }, + { 353, 78, 4, 6, 4, 5 }, + { 378, 88, 4, 3, 1362, 10 }, + { 403, 91, 4, 3, 1362, 10 }, + { 8, 94, 4, 3, 1362, 10 }, + { 62, 97, 4, 3, 1362, 10 }, + { 116, 100, 4, 3, 1362, 10 }, + { 162, 103, 4, 3, 1362, 10 }, + { 208, 106, 4, 3, 1362, 10 }, + { 249, 109, 4, 3, 1362, 10 }, +}; + + // FCCRegs Register Class... + static const MCPhysReg FCCRegs[] = { + SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3, + }; + + // FCCRegs Bit set. + static const uint8_t FCCRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + }; + + // FPRegs Register Class... + static const MCPhysReg FPRegs[] = { + SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, + }; + + // FPRegs Bit set. + static const uint8_t FPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // IntRegs Register Class... + static const MCPhysReg IntRegs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, + }; + + // IntRegs Bit set. + static const uint8_t IntRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // DFPRegs Register Class... + static const MCPhysReg DFPRegs[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, + }; + + // DFPRegs Bit set. + static const uint8_t DFPRegsBits[] = { + 0xf8, 0xff, 0xff, 0xff, 0x07, + }; + + // I64Regs Register Class... + static const MCPhysReg I64Regs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, + }; + + // I64Regs Bit set. + static const uint8_t I64RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // DFPRegs_with_sub_even Register Class... + static const MCPhysReg DFPRegs_with_sub_even[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, + }; + + // DFPRegs_with_sub_even Bit set. + static const uint8_t DFPRegs_with_sub_evenBits[] = { + 0xf8, 0xff, 0x07, + }; + + // QFPRegs Register Class... + static const MCPhysReg QFPRegs[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, + }; + + // QFPRegs Bit set. + static const uint8_t QFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // QFPRegs_with_sub_even Register Class... + static const MCPhysReg QFPRegs_with_sub_even[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, + }; + + // QFPRegs_with_sub_even Bit set. + static const uint8_t QFPRegs_with_sub_evenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, + }; + +static MCRegisterClass SparcMCRegisterClasses[] = { + { FCCRegs, FCCRegsBits, 52, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 }, + { FPRegs, FPRegsBits, 61, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 }, + { IntRegs, IntRegsBits, 76, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 }, + { DFPRegs, DFPRegsBits, 60, 32, sizeof(DFPRegsBits), SP_DFPRegsRegClassID, 8, 8, 1, 1 }, + { I64Regs, I64RegsBits, 44, 32, sizeof(I64RegsBits), SP_I64RegsRegClassID, 8, 8, 1, 1 }, + { DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 0, 16, sizeof(DFPRegs_with_sub_evenBits), SP_DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 }, + { QFPRegs, QFPRegsBits, 68, 16, sizeof(QFPRegsBits), SP_QFPRegsRegClassID, 16, 16, 1, 1 }, + { QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 22, 8, sizeof(QFPRegs_with_sub_evenBits), SP_QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcGenSubtargetInfo.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcGenSubtargetInfo.inc new file mode 100644 index 0000000..e7bd53a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcGenSubtargetInfo.inc @@ -0,0 +1,27 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + Sparc_FeatureHardQuad = 1ULL << 0, + Sparc_FeatureV8Deprecated = 1ULL << 1, + Sparc_FeatureV9 = 1ULL << 2, + Sparc_FeatureVIS = 1ULL << 3, + Sparc_FeatureVIS2 = 1ULL << 4, + Sparc_FeatureVIS3 = 1ULL << 5, + Sparc_UsePopc = 1ULL << 6 +}; + +#endif // GET_SUBTARGETINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.c b/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.c new file mode 100644 index 0000000..4ca0155 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.c @@ -0,0 +1,449 @@ +//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an Sparc MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SPARC + +#ifdef _MSC_VER +#define _CRT_SECURE_NO_WARNINGS +#endif + +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#endif + +#include +#include +#include +#include + +#include "SparcInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "SparcMapping.h" + +#include "Sparc.h" + +static const char *getRegisterName(unsigned RegNo); +static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier); +static void printOperand(MCInst *MI, int opNum, SStream *O); + +static void Sparc_add_hint(MCInst *MI, unsigned int hint) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.hint = hint; + } +} + +static void Sparc_add_reg(MCInst *MI, unsigned int reg) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } +} + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + + if (status) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->sparc.op_count++; + } +} + +void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // fix up some instructions + if (insn->id == SPARC_INS_CASX) { + // first op is actually a memop, not regop + insn->detail->sparc.operands[0].type = SPARC_OP_MEM; + insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg; + insn->detail->sparc.operands[0].mem.disp = 0; + } +} + +static void printRegName(SStream *OS, unsigned RegNo) +{ + SStream_concat0(OS, "%"); + SStream_concat0(OS, getRegisterName(RegNo)); +} + +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" + +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" + +static bool printSparcAliasInstr(MCInst *MI, SStream *O) +{ + switch (MCInst_getOpcode(MI)) { + default: return false; + case SP_JMPLrr: + case SP_JMPLri: + if (MCInst_getNumOperands(MI) != 3) + return false; + if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) + return false; + + switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { + default: return false; + case SP_G0: // jmp $addr | ret | retl + if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) { + default: break; + case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true; + case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true; + } + } + + SStream_concat0(O, "jmp\t"); + MCInst_setOpcodePub(MI, SPARC_INS_JMP); + printMemOperand(MI, 1, O, NULL); + return true; + case SP_O7: // call $addr + SStream_concat0(O, "call "); + MCInst_setOpcodePub(MI, SPARC_INS_CALL); + printMemOperand(MI, 1, O, NULL); + return true; + } + case SP_V9FCMPS: + case SP_V9FCMPD: + case SP_V9FCMPQ: + case SP_V9FCMPES: + case SP_V9FCMPED: + case SP_V9FCMPEQ: + if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || + (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || + (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) + return false; + // if V8, skip printing %fcc0. + switch(MCInst_getOpcode(MI)) { + default: + case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break; + case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break; + case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break; + case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break; + case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break; + case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break; + } + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return true; + } +} + +static void printOperand(MCInst *MI, int opNum, SStream *O) +{ + int64_t Imm; + unsigned reg; + MCOperand *MO = MCInst_getOperand(MI, opNum); + + if (MCOperand_isReg(MO)) { + reg = MCOperand_getReg(MO); + printRegName(O, reg); + reg = Sparc_map_register(reg); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base) + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg; + else + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg; + } else { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } + } + + return; + } + + if (MCOperand_isImm(MO)) { + Imm = (int)MCOperand_getImm(MO); + + // Conditional branches displacements needs to be signextended to be + // able to jump backwards. + // + // Displacements are measured as the number of instructions forward or + // backward, so they need to be multiplied by 4 + switch (MI->Opcode) { + case SP_CALL: + // Imm = SignExtend32(Imm, 30); + Imm += MI->address; + break; + + // Branch on integer condition with prediction (BPcc) + // Branch on floating point condition with prediction (FBPfcc) + case SP_BPICC: + case SP_BPICCA: + case SP_BPICCANT: + case SP_BPICCNT: + case SP_BPXCC: + case SP_BPXCCA: + case SP_BPXCCANT: + case SP_BPXCCNT: + case SP_BPFCC: + case SP_BPFCCA: + case SP_BPFCCANT: + case SP_BPFCCNT: + Imm = SignExtend32((uint32_t)Imm, 19); + Imm = MI->address + Imm * 4; + break; + + // Branch on integer condition (Bicc) + // Branch on floating point condition (FBfcc) + case SP_BA: + case SP_BCOND: + case SP_BCONDA: + case SP_FBCOND: + case SP_FBCONDA: + Imm = SignExtend32((uint32_t)Imm, 22); + Imm = MI->address + Imm * 4; + break; + + // Branch on integer register with prediction (BPr) + case SP_BPGEZapn: + case SP_BPGEZapt: + case SP_BPGEZnapn: + case SP_BPGEZnapt: + case SP_BPGZapn: + case SP_BPGZapt: + case SP_BPGZnapn: + case SP_BPGZnapt: + case SP_BPLEZapn: + case SP_BPLEZapt: + case SP_BPLEZnapn: + case SP_BPLEZnapt: + case SP_BPLZapn: + case SP_BPLZapt: + case SP_BPLZnapn: + case SP_BPLZnapt: + case SP_BPNZapn: + case SP_BPNZapt: + case SP_BPNZnapn: + case SP_BPNZnapt: + case SP_BPZapn: + case SP_BPZapt: + case SP_BPZnapn: + case SP_BPZnapt: + Imm = SignExtend32((uint32_t)Imm, 16); + Imm = MI->address + Imm * 4; + break; + } + + printInt64(O, Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = (uint32_t)Imm; + } else { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm; + MI->flat_insn->detail->sparc.op_count++; + } + } + } + + return; +} + +static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier) +{ + MCOperand *MO; + + set_mem_access(MI, true); + printOperand(MI, opNum, O); + + // If this is an ADD operand, emit it like normal operands. + if (Modifier && !strcmp(Modifier, "arith")) { + SStream_concat0(O, ", "); + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); + return; + } + + MO = MCInst_getOperand(MI, opNum + 1); + + if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { + set_mem_access(MI, false); + return; // don't print "+%g0" + } + + if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { + set_mem_access(MI, false); + return; // don't print "+0" + } + + SStream_concat0(O, "+"); // qq + + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); +} + +static void printCCOperand(MCInst *MI, int opNum, SStream *O) +{ + int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256; + + switch (MCInst_getOpcode(MI)) { + default: break; + case SP_FBCOND: + case SP_FBCONDA: + case SP_BPFCC: + case SP_BPFCCA: + case SP_BPFCCNT: + case SP_BPFCCANT: + case SP_MOVFCCrr: case SP_V9MOVFCCrr: + case SP_MOVFCCri: case SP_V9MOVFCCri: + case SP_FMOVS_FCC: case SP_V9FMOVS_FCC: + case SP_FMOVD_FCC: case SP_V9FMOVD_FCC: + case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC: + // Make sure CC is a fp conditional flag. + CC = (CC < 16+256) ? (CC + 16) : CC; + break; + } + + SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); + + if (MI->csh->detail) + MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; +} + + +static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) +{ + return true; +} + + +#define PRINT_ALIAS_INSTR +#include "SparcGenAsmWriter.inc" + +void Sparc_printInst(MCInst *MI, SStream *O, void *Info) +{ + char *mnem, *p; + char instr[64]; // Sparc has no instruction this long + + mnem = printAliasInstr(MI, O, Info); + if (mnem) { + // fixup instruction id due to the change in alias instruction + strncpy(instr, mnem, sizeof(instr)); + instr[sizeof(instr) - 1] = '\0'; + // does this contains hint with a coma? + p = strchr(instr, ','); + if (p) + *p = '\0'; // now instr only has instruction mnemonic + MCInst_setOpcodePub(MI, Sparc_map_insn(instr)); + switch(MCInst_getOpcode(MI)) { + case SP_BCOND: + case SP_BCONDA: + case SP_BPICCANT: + case SP_BPICCNT: + case SP_BPXCCANT: + case SP_BPXCCNT: + case SP_TXCCri: + case SP_TXCCrr: + if (MI->csh->detail) { + // skip 'b', 't' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_BPFCCANT: + case SP_BPFCCNT: + if (MI->csh->detail) { + // skip 'fb' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_FMOVD_ICC: + case SP_FMOVD_XCC: + case SP_FMOVQ_ICC: + case SP_FMOVQ_XCC: + case SP_FMOVS_ICC: + case SP_FMOVS_XCC: + if (MI->csh->detail) { + // skip 'fmovd', 'fmovq', 'fmovs' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_MOVICCri: + case SP_MOVICCrr: + case SP_MOVXCCri: + case SP_MOVXCCrr: + if (MI->csh->detail) { + // skip 'mov' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_V9FMOVD_FCC: + case SP_V9FMOVQ_FCC: + case SP_V9FMOVS_FCC: + if (MI->csh->detail) { + // skip 'fmovd', 'fmovq', 'fmovs' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_V9MOVFCCri: + case SP_V9MOVFCCrr: + if (MI->csh->detail) { + // skip 'mov' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + default: + break; + } + cs_mem_free(mnem); + } else { + if (!printSparcAliasInstr(MI, O)) + printInstruction(MI, O, NULL); + } +} + +void Sparc_addReg(MCInst *MI, int reg) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.h b/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.h new file mode 100644 index 0000000..4cd891e --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcInstPrinter.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SPARCINSTPRINTER_H +#define CS_SPARCINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void Sparc_printInst(MCInst *MI, SStream *O, void *Info); + +void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); + +void Sparc_addReg(MCInst *MI, int reg); + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.c b/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.c new file mode 100644 index 0000000..f86fb33 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.c @@ -0,0 +1,665 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SPARC + +#include // debug +#include + +#include "../../utils.h" + +#include "SparcMapping.h" + +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { SPARC_REG_INVALID, NULL }, + + { SPARC_REG_F0, "f0"}, + { SPARC_REG_F1, "f1"}, + { SPARC_REG_F2, "f2"}, + { SPARC_REG_F3, "f3"}, + { SPARC_REG_F4, "f4"}, + { SPARC_REG_F5, "f5"}, + { SPARC_REG_F6, "f6"}, + { SPARC_REG_F7, "f7"}, + { SPARC_REG_F8, "f8"}, + { SPARC_REG_F9, "f9"}, + { SPARC_REG_F10, "f10"}, + { SPARC_REG_F11, "f11"}, + { SPARC_REG_F12, "f12"}, + { SPARC_REG_F13, "f13"}, + { SPARC_REG_F14, "f14"}, + { SPARC_REG_F15, "f15"}, + { SPARC_REG_F16, "f16"}, + { SPARC_REG_F17, "f17"}, + { SPARC_REG_F18, "f18"}, + { SPARC_REG_F19, "f19"}, + { SPARC_REG_F20, "f20"}, + { SPARC_REG_F21, "f21"}, + { SPARC_REG_F22, "f22"}, + { SPARC_REG_F23, "f23"}, + { SPARC_REG_F24, "f24"}, + { SPARC_REG_F25, "f25"}, + { SPARC_REG_F26, "f26"}, + { SPARC_REG_F27, "f27"}, + { SPARC_REG_F28, "f28"}, + { SPARC_REG_F29, "f29"}, + { SPARC_REG_F30, "f30"}, + { SPARC_REG_F31, "f31"}, + { SPARC_REG_F32, "f32"}, + { SPARC_REG_F34, "f34"}, + { SPARC_REG_F36, "f36"}, + { SPARC_REG_F38, "f38"}, + { SPARC_REG_F40, "f40"}, + { SPARC_REG_F42, "f42"}, + { SPARC_REG_F44, "f44"}, + { SPARC_REG_F46, "f46"}, + { SPARC_REG_F48, "f48"}, + { SPARC_REG_F50, "f50"}, + { SPARC_REG_F52, "f52"}, + { SPARC_REG_F54, "f54"}, + { SPARC_REG_F56, "f56"}, + { SPARC_REG_F58, "f58"}, + { SPARC_REG_F60, "f60"}, + { SPARC_REG_F62, "f62"}, + { SPARC_REG_FCC0, "fcc0"}, + { SPARC_REG_FCC1, "fcc1"}, + { SPARC_REG_FCC2, "fcc2"}, + { SPARC_REG_FCC3, "fcc3"}, + { SPARC_REG_FP, "fp"}, + { SPARC_REG_G0, "g0"}, + { SPARC_REG_G1, "g1"}, + { SPARC_REG_G2, "g2"}, + { SPARC_REG_G3, "g3"}, + { SPARC_REG_G4, "g4"}, + { SPARC_REG_G5, "g5"}, + { SPARC_REG_G6, "g6"}, + { SPARC_REG_G7, "g7"}, + { SPARC_REG_I0, "i0"}, + { SPARC_REG_I1, "i1"}, + { SPARC_REG_I2, "i2"}, + { SPARC_REG_I3, "i3"}, + { SPARC_REG_I4, "i4"}, + { SPARC_REG_I5, "i5"}, + { SPARC_REG_I7, "i7"}, + { SPARC_REG_ICC, "icc"}, + { SPARC_REG_L0, "l0"}, + { SPARC_REG_L1, "l1"}, + { SPARC_REG_L2, "l2"}, + { SPARC_REG_L3, "l3"}, + { SPARC_REG_L4, "l4"}, + { SPARC_REG_L5, "l5"}, + { SPARC_REG_L6, "l6"}, + { SPARC_REG_L7, "l7"}, + { SPARC_REG_O0, "o0"}, + { SPARC_REG_O1, "o1"}, + { SPARC_REG_O2, "o2"}, + { SPARC_REG_O3, "o3"}, + { SPARC_REG_O4, "o4"}, + { SPARC_REG_O5, "o5"}, + { SPARC_REG_O7, "o7"}, + { SPARC_REG_SP, "sp"}, + { SPARC_REG_Y, "y"}, + + // special registers + { SPARC_REG_XCC, "xcc"}, +}; +#endif + +const char *Sparc_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "SparcMappingInsn.inc" +}; + +static struct hint_map { + unsigned int id; + uint8_t hints; +} const insn_hints[] = { + { SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPGEZnapn, SPARC_HINT_PN }, + { SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPGZnapn, SPARC_HINT_PN }, + { SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPLEZnapn, SPARC_HINT_PN }, + { SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPLZnapn, SPARC_HINT_PN }, + { SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPNZnapn, SPARC_HINT_PN }, + { SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN }, + { SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT }, + { SP_BPZnapn, SPARC_HINT_PN }, +}; + +// given internal insn id, return public instruction info +void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + // hint code + for (i = 0; i < ARR_SIZE(insn_hints); i++) { + if (id == insn_hints[i].id) { + insn->detail->sparc.hint = insn_hints[i].hints; + break; + } + } + } + } +} + +static const name_map insn_name_maps[] = { + { SPARC_INS_INVALID, NULL }, + + { SPARC_INS_ADDCC, "addcc" }, + { SPARC_INS_ADDX, "addx" }, + { SPARC_INS_ADDXCC, "addxcc" }, + { SPARC_INS_ADDXC, "addxc" }, + { SPARC_INS_ADDXCCC, "addxccc" }, + { SPARC_INS_ADD, "add" }, + { SPARC_INS_ALIGNADDR, "alignaddr" }, + { SPARC_INS_ALIGNADDRL, "alignaddrl" }, + { SPARC_INS_ANDCC, "andcc" }, + { SPARC_INS_ANDNCC, "andncc" }, + { SPARC_INS_ANDN, "andn" }, + { SPARC_INS_AND, "and" }, + { SPARC_INS_ARRAY16, "array16" }, + { SPARC_INS_ARRAY32, "array32" }, + { SPARC_INS_ARRAY8, "array8" }, + { SPARC_INS_B, "b" }, + { SPARC_INS_JMP, "jmp" }, + { SPARC_INS_BMASK, "bmask" }, + { SPARC_INS_FB, "fb" }, + { SPARC_INS_BRGEZ, "brgez" }, + { SPARC_INS_BRGZ, "brgz" }, + { SPARC_INS_BRLEZ, "brlez" }, + { SPARC_INS_BRLZ, "brlz" }, + { SPARC_INS_BRNZ, "brnz" }, + { SPARC_INS_BRZ, "brz" }, + { SPARC_INS_BSHUFFLE, "bshuffle" }, + { SPARC_INS_CALL, "call" }, + { SPARC_INS_CASX, "casx" }, + { SPARC_INS_CAS, "cas" }, + { SPARC_INS_CMASK16, "cmask16" }, + { SPARC_INS_CMASK32, "cmask32" }, + { SPARC_INS_CMASK8, "cmask8" }, + { SPARC_INS_CMP, "cmp" }, + { SPARC_INS_EDGE16, "edge16" }, + { SPARC_INS_EDGE16L, "edge16l" }, + { SPARC_INS_EDGE16LN, "edge16ln" }, + { SPARC_INS_EDGE16N, "edge16n" }, + { SPARC_INS_EDGE32, "edge32" }, + { SPARC_INS_EDGE32L, "edge32l" }, + { SPARC_INS_EDGE32LN, "edge32ln" }, + { SPARC_INS_EDGE32N, "edge32n" }, + { SPARC_INS_EDGE8, "edge8" }, + { SPARC_INS_EDGE8L, "edge8l" }, + { SPARC_INS_EDGE8LN, "edge8ln" }, + { SPARC_INS_EDGE8N, "edge8n" }, + { SPARC_INS_FABSD, "fabsd" }, + { SPARC_INS_FABSQ, "fabsq" }, + { SPARC_INS_FABSS, "fabss" }, + { SPARC_INS_FADDD, "faddd" }, + { SPARC_INS_FADDQ, "faddq" }, + { SPARC_INS_FADDS, "fadds" }, + { SPARC_INS_FALIGNDATA, "faligndata" }, + { SPARC_INS_FAND, "fand" }, + { SPARC_INS_FANDNOT1, "fandnot1" }, + { SPARC_INS_FANDNOT1S, "fandnot1s" }, + { SPARC_INS_FANDNOT2, "fandnot2" }, + { SPARC_INS_FANDNOT2S, "fandnot2s" }, + { SPARC_INS_FANDS, "fands" }, + { SPARC_INS_FCHKSM16, "fchksm16" }, + { SPARC_INS_FCMPD, "fcmpd" }, + { SPARC_INS_FCMPEQ16, "fcmpeq16" }, + { SPARC_INS_FCMPEQ32, "fcmpeq32" }, + { SPARC_INS_FCMPGT16, "fcmpgt16" }, + { SPARC_INS_FCMPGT32, "fcmpgt32" }, + { SPARC_INS_FCMPLE16, "fcmple16" }, + { SPARC_INS_FCMPLE32, "fcmple32" }, + { SPARC_INS_FCMPNE16, "fcmpne16" }, + { SPARC_INS_FCMPNE32, "fcmpne32" }, + { SPARC_INS_FCMPQ, "fcmpq" }, + { SPARC_INS_FCMPS, "fcmps" }, + { SPARC_INS_FDIVD, "fdivd" }, + { SPARC_INS_FDIVQ, "fdivq" }, + { SPARC_INS_FDIVS, "fdivs" }, + { SPARC_INS_FDMULQ, "fdmulq" }, + { SPARC_INS_FDTOI, "fdtoi" }, + { SPARC_INS_FDTOQ, "fdtoq" }, + { SPARC_INS_FDTOS, "fdtos" }, + { SPARC_INS_FDTOX, "fdtox" }, + { SPARC_INS_FEXPAND, "fexpand" }, + { SPARC_INS_FHADDD, "fhaddd" }, + { SPARC_INS_FHADDS, "fhadds" }, + { SPARC_INS_FHSUBD, "fhsubd" }, + { SPARC_INS_FHSUBS, "fhsubs" }, + { SPARC_INS_FITOD, "fitod" }, + { SPARC_INS_FITOQ, "fitoq" }, + { SPARC_INS_FITOS, "fitos" }, + { SPARC_INS_FLCMPD, "flcmpd" }, + { SPARC_INS_FLCMPS, "flcmps" }, + { SPARC_INS_FLUSHW, "flushw" }, + { SPARC_INS_FMEAN16, "fmean16" }, + { SPARC_INS_FMOVD, "fmovd" }, + { SPARC_INS_FMOVQ, "fmovq" }, + { SPARC_INS_FMOVRDGEZ, "fmovrdgez" }, + { SPARC_INS_FMOVRQGEZ, "fmovrqgez" }, + { SPARC_INS_FMOVRSGEZ, "fmovrsgez" }, + { SPARC_INS_FMOVRDGZ, "fmovrdgz" }, + { SPARC_INS_FMOVRQGZ, "fmovrqgz" }, + { SPARC_INS_FMOVRSGZ, "fmovrsgz" }, + { SPARC_INS_FMOVRDLEZ, "fmovrdlez" }, + { SPARC_INS_FMOVRQLEZ, "fmovrqlez" }, + { SPARC_INS_FMOVRSLEZ, "fmovrslez" }, + { SPARC_INS_FMOVRDLZ, "fmovrdlz" }, + { SPARC_INS_FMOVRQLZ, "fmovrqlz" }, + { SPARC_INS_FMOVRSLZ, "fmovrslz" }, + { SPARC_INS_FMOVRDNZ, "fmovrdnz" }, + { SPARC_INS_FMOVRQNZ, "fmovrqnz" }, + { SPARC_INS_FMOVRSNZ, "fmovrsnz" }, + { SPARC_INS_FMOVRDZ, "fmovrdz" }, + { SPARC_INS_FMOVRQZ, "fmovrqz" }, + { SPARC_INS_FMOVRSZ, "fmovrsz" }, + { SPARC_INS_FMOVS, "fmovs" }, + { SPARC_INS_FMUL8SUX16, "fmul8sux16" }, + { SPARC_INS_FMUL8ULX16, "fmul8ulx16" }, + { SPARC_INS_FMUL8X16, "fmul8x16" }, + { SPARC_INS_FMUL8X16AL, "fmul8x16al" }, + { SPARC_INS_FMUL8X16AU, "fmul8x16au" }, + { SPARC_INS_FMULD, "fmuld" }, + { SPARC_INS_FMULD8SUX16, "fmuld8sux16" }, + { SPARC_INS_FMULD8ULX16, "fmuld8ulx16" }, + { SPARC_INS_FMULQ, "fmulq" }, + { SPARC_INS_FMULS, "fmuls" }, + { SPARC_INS_FNADDD, "fnaddd" }, + { SPARC_INS_FNADDS, "fnadds" }, + { SPARC_INS_FNAND, "fnand" }, + { SPARC_INS_FNANDS, "fnands" }, + { SPARC_INS_FNEGD, "fnegd" }, + { SPARC_INS_FNEGQ, "fnegq" }, + { SPARC_INS_FNEGS, "fnegs" }, + { SPARC_INS_FNHADDD, "fnhaddd" }, + { SPARC_INS_FNHADDS, "fnhadds" }, + { SPARC_INS_FNOR, "fnor" }, + { SPARC_INS_FNORS, "fnors" }, + { SPARC_INS_FNOT1, "fnot1" }, + { SPARC_INS_FNOT1S, "fnot1s" }, + { SPARC_INS_FNOT2, "fnot2" }, + { SPARC_INS_FNOT2S, "fnot2s" }, + { SPARC_INS_FONE, "fone" }, + { SPARC_INS_FONES, "fones" }, + { SPARC_INS_FOR, "for" }, + { SPARC_INS_FORNOT1, "fornot1" }, + { SPARC_INS_FORNOT1S, "fornot1s" }, + { SPARC_INS_FORNOT2, "fornot2" }, + { SPARC_INS_FORNOT2S, "fornot2s" }, + { SPARC_INS_FORS, "fors" }, + { SPARC_INS_FPACK16, "fpack16" }, + { SPARC_INS_FPACK32, "fpack32" }, + { SPARC_INS_FPACKFIX, "fpackfix" }, + { SPARC_INS_FPADD16, "fpadd16" }, + { SPARC_INS_FPADD16S, "fpadd16s" }, + { SPARC_INS_FPADD32, "fpadd32" }, + { SPARC_INS_FPADD32S, "fpadd32s" }, + { SPARC_INS_FPADD64, "fpadd64" }, + { SPARC_INS_FPMERGE, "fpmerge" }, + { SPARC_INS_FPSUB16, "fpsub16" }, + { SPARC_INS_FPSUB16S, "fpsub16s" }, + { SPARC_INS_FPSUB32, "fpsub32" }, + { SPARC_INS_FPSUB32S, "fpsub32s" }, + { SPARC_INS_FQTOD, "fqtod" }, + { SPARC_INS_FQTOI, "fqtoi" }, + { SPARC_INS_FQTOS, "fqtos" }, + { SPARC_INS_FQTOX, "fqtox" }, + { SPARC_INS_FSLAS16, "fslas16" }, + { SPARC_INS_FSLAS32, "fslas32" }, + { SPARC_INS_FSLL16, "fsll16" }, + { SPARC_INS_FSLL32, "fsll32" }, + { SPARC_INS_FSMULD, "fsmuld" }, + { SPARC_INS_FSQRTD, "fsqrtd" }, + { SPARC_INS_FSQRTQ, "fsqrtq" }, + { SPARC_INS_FSQRTS, "fsqrts" }, + { SPARC_INS_FSRA16, "fsra16" }, + { SPARC_INS_FSRA32, "fsra32" }, + { SPARC_INS_FSRC1, "fsrc1" }, + { SPARC_INS_FSRC1S, "fsrc1s" }, + { SPARC_INS_FSRC2, "fsrc2" }, + { SPARC_INS_FSRC2S, "fsrc2s" }, + { SPARC_INS_FSRL16, "fsrl16" }, + { SPARC_INS_FSRL32, "fsrl32" }, + { SPARC_INS_FSTOD, "fstod" }, + { SPARC_INS_FSTOI, "fstoi" }, + { SPARC_INS_FSTOQ, "fstoq" }, + { SPARC_INS_FSTOX, "fstox" }, + { SPARC_INS_FSUBD, "fsubd" }, + { SPARC_INS_FSUBQ, "fsubq" }, + { SPARC_INS_FSUBS, "fsubs" }, + { SPARC_INS_FXNOR, "fxnor" }, + { SPARC_INS_FXNORS, "fxnors" }, + { SPARC_INS_FXOR, "fxor" }, + { SPARC_INS_FXORS, "fxors" }, + { SPARC_INS_FXTOD, "fxtod" }, + { SPARC_INS_FXTOQ, "fxtoq" }, + { SPARC_INS_FXTOS, "fxtos" }, + { SPARC_INS_FZERO, "fzero" }, + { SPARC_INS_FZEROS, "fzeros" }, + { SPARC_INS_JMPL, "jmpl" }, + { SPARC_INS_LDD, "ldd" }, + { SPARC_INS_LD, "ld" }, + { SPARC_INS_LDQ, "ldq" }, + { SPARC_INS_LDSB, "ldsb" }, + { SPARC_INS_LDSH, "ldsh" }, + { SPARC_INS_LDSW, "ldsw" }, + { SPARC_INS_LDUB, "ldub" }, + { SPARC_INS_LDUH, "lduh" }, + { SPARC_INS_LDX, "ldx" }, + { SPARC_INS_LZCNT, "lzcnt" }, + { SPARC_INS_MEMBAR, "membar" }, + { SPARC_INS_MOVDTOX, "movdtox" }, + { SPARC_INS_MOV, "mov" }, + { SPARC_INS_MOVRGEZ, "movrgez" }, + { SPARC_INS_MOVRGZ, "movrgz" }, + { SPARC_INS_MOVRLEZ, "movrlez" }, + { SPARC_INS_MOVRLZ, "movrlz" }, + { SPARC_INS_MOVRNZ, "movrnz" }, + { SPARC_INS_MOVRZ, "movrz" }, + { SPARC_INS_MOVSTOSW, "movstosw" }, + { SPARC_INS_MOVSTOUW, "movstouw" }, + { SPARC_INS_MULX, "mulx" }, + { SPARC_INS_NOP, "nop" }, + { SPARC_INS_ORCC, "orcc" }, + { SPARC_INS_ORNCC, "orncc" }, + { SPARC_INS_ORN, "orn" }, + { SPARC_INS_OR, "or" }, + { SPARC_INS_PDIST, "pdist" }, + { SPARC_INS_PDISTN, "pdistn" }, + { SPARC_INS_POPC, "popc" }, + { SPARC_INS_RD, "rd" }, + { SPARC_INS_RESTORE, "restore" }, + { SPARC_INS_RETT, "rett" }, + { SPARC_INS_SAVE, "save" }, + { SPARC_INS_SDIVCC, "sdivcc" }, + { SPARC_INS_SDIVX, "sdivx" }, + { SPARC_INS_SDIV, "sdiv" }, + { SPARC_INS_SETHI, "sethi" }, + { SPARC_INS_SHUTDOWN, "shutdown" }, + { SPARC_INS_SIAM, "siam" }, + { SPARC_INS_SLLX, "sllx" }, + { SPARC_INS_SLL, "sll" }, + { SPARC_INS_SMULCC, "smulcc" }, + { SPARC_INS_SMUL, "smul" }, + { SPARC_INS_SRAX, "srax" }, + { SPARC_INS_SRA, "sra" }, + { SPARC_INS_SRLX, "srlx" }, + { SPARC_INS_SRL, "srl" }, + { SPARC_INS_STBAR, "stbar" }, + { SPARC_INS_STB, "stb" }, + { SPARC_INS_STD, "std" }, + { SPARC_INS_ST, "st" }, + { SPARC_INS_STH, "sth" }, + { SPARC_INS_STQ, "stq" }, + { SPARC_INS_STX, "stx" }, + { SPARC_INS_SUBCC, "subcc" }, + { SPARC_INS_SUBX, "subx" }, + { SPARC_INS_SUBXCC, "subxcc" }, + { SPARC_INS_SUB, "sub" }, + { SPARC_INS_SWAP, "swap" }, + { SPARC_INS_TADDCCTV, "taddcctv" }, + { SPARC_INS_TADDCC, "taddcc" }, + { SPARC_INS_T, "t" }, + { SPARC_INS_TSUBCCTV, "tsubcctv" }, + { SPARC_INS_TSUBCC, "tsubcc" }, + { SPARC_INS_UDIVCC, "udivcc" }, + { SPARC_INS_UDIVX, "udivx" }, + { SPARC_INS_UDIV, "udiv" }, + { SPARC_INS_UMULCC, "umulcc" }, + { SPARC_INS_UMULXHI, "umulxhi" }, + { SPARC_INS_UMUL, "umul" }, + { SPARC_INS_UNIMP, "unimp" }, + { SPARC_INS_FCMPED, "fcmped" }, + { SPARC_INS_FCMPEQ, "fcmpeq" }, + { SPARC_INS_FCMPES, "fcmpes" }, + { SPARC_INS_WR, "wr" }, + { SPARC_INS_XMULX, "xmulx" }, + { SPARC_INS_XMULXHI, "xmulxhi" }, + { SPARC_INS_XNORCC, "xnorcc" }, + { SPARC_INS_XNOR, "xnor" }, + { SPARC_INS_XORCC, "xorcc" }, + { SPARC_INS_XOR, "xor" }, + + // alias instructions + { SPARC_INS_RET, "ret" }, + { SPARC_INS_RETL, "retl" }, +}; + +#ifndef CAPSTONE_DIET +// special alias insn +static const name_map alias_insn_names[] = { + { 0, NULL } +}; +#endif + +const char *Sparc_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= SPARC_INS_ENDING) + return NULL; + + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { SPARC_GRP_INVALID, NULL }, + { SPARC_GRP_JUMP, "jump" }, + + // architecture-specific groups + { SPARC_GRP_HARDQUAD, "hardquad" }, + { SPARC_GRP_V9, "v9" }, + { SPARC_GRP_VIS, "vis" }, + { SPARC_GRP_VIS2, "vis2" }, + { SPARC_GRP_VIS3, "vis3" }, + { SPARC_GRP_32BIT, "32bit" }, + { SPARC_GRP_64BIT, "64bit" }, +}; +#endif + +const char *Sparc_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map internal raw register to 'public' register +sparc_reg Sparc_map_register(unsigned int r) +{ + static const unsigned int map[] = { 0, + SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4, + SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14, + SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24, + SPARC_REG_F26, SPARC_REG_F28, SPARC_REG_F30, SPARC_REG_F32, SPARC_REG_F34, + SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44, + SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54, + SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_F0, + SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5, + SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10, + SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15, + SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20, + SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25, + SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30, + SPARC_REG_F31, SPARC_REG_FCC0, SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3, + SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4, + SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1, + SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_FP, + SPARC_REG_I7, SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3, + SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0, + SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5, + SPARC_REG_SP, SPARC_REG_O7, SPARC_REG_F0, SPARC_REG_F4, SPARC_REG_F8, + SPARC_REG_F12, SPARC_REG_F16, SPARC_REG_F20, SPARC_REG_F24, SPARC_REG_F28, + SPARC_REG_F32, SPARC_REG_F36, SPARC_REG_F40, SPARC_REG_F44, SPARC_REG_F48, + SPARC_REG_F52, SPARC_REG_F56, SPARC_REG_F60, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +// map instruction name to instruction ID (public) +sparc_reg Sparc_map_insn(const char *name) +{ + unsigned int i; + + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + + return (i != -1)? i : SPARC_REG_INVALID; +} + +// NOTE: put strings in the order of string length since +// we are going to compare with mnemonic to find out CC +static const name_map alias_icc_maps[] = { + { SPARC_CC_ICC_LEU, "leu" }, + { SPARC_CC_ICC_POS, "pos" }, + { SPARC_CC_ICC_NEG, "neg" }, + { SPARC_CC_ICC_NE, "ne" }, + { SPARC_CC_ICC_LE, "le" }, + { SPARC_CC_ICC_GE, "ge" }, + { SPARC_CC_ICC_GU, "gu" }, + { SPARC_CC_ICC_CC, "cc" }, + { SPARC_CC_ICC_CS, "cs" }, + { SPARC_CC_ICC_VC, "vc" }, + { SPARC_CC_ICC_VS, "vs" }, + { SPARC_CC_ICC_A, "a" }, + { SPARC_CC_ICC_N, "n" }, + { SPARC_CC_ICC_E, "e" }, + { SPARC_CC_ICC_G, "g" }, + { SPARC_CC_ICC_L, "l" }, +}; + +static const name_map alias_fcc_maps[] = { + { SPARC_CC_FCC_UGE, "uge" }, + { SPARC_CC_FCC_ULE, "ule" }, + { SPARC_CC_FCC_UG, "ug" }, + { SPARC_CC_FCC_UL, "ul" }, + { SPARC_CC_FCC_LG, "lg" }, + { SPARC_CC_FCC_NE, "ne" }, + { SPARC_CC_FCC_UE, "ue" }, + { SPARC_CC_FCC_GE, "ge" }, + { SPARC_CC_FCC_LE, "le" }, + { SPARC_CC_FCC_A, "a" }, + { SPARC_CC_FCC_N, "n" }, + { SPARC_CC_FCC_U, "u" }, + { SPARC_CC_FCC_G, "g" }, + { SPARC_CC_FCC_L, "l" }, + { SPARC_CC_FCC_E, "e" }, + { SPARC_CC_FCC_O, "o" }, +}; + +// map CC string to CC id +sparc_cc Sparc_map_ICC(const char *name) +{ + unsigned int i; + + i = name2id(alias_icc_maps, ARR_SIZE(alias_icc_maps), name); + + return (i != -1)? i : SPARC_CC_INVALID; +} + +sparc_cc Sparc_map_FCC(const char *name) +{ + unsigned int i; + + i = name2id(alias_fcc_maps, ARR_SIZE(alias_fcc_maps), name); + + return (i != -1)? i : SPARC_CC_INVALID; +} + +static const name_map hint_maps[] = { + { SPARC_HINT_A, ",a" }, + { SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" }, + { SPARC_HINT_PN, ",pn" }, +}; + +sparc_hint Sparc_map_hint(const char *name) +{ + size_t i, l1, l2; + + l1 = strlen(name); + for(i = 0; i < ARR_SIZE(hint_maps); i++) { + l2 = strlen(hint_maps[i].name); + if (l1 > l2) { + // compare the last part of @name with this hint string + if (!strcmp(hint_maps[i].name, name + (l1 - l2))) + return hint_maps[i].id; + } + } + + return SPARC_HINT_INVALID; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.h b/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.h new file mode 100644 index 0000000..1c8c1b1 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcMapping.h @@ -0,0 +1,34 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SPARC_MAP_H +#define CS_SPARC_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *Sparc_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *Sparc_insn_name(csh handle, unsigned int id); + +const char *Sparc_group_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +sparc_reg Sparc_map_register(unsigned int r); + +// map instruction name to instruction ID (public) +// this is for alias instructions only +sparc_reg Sparc_map_insn(const char *name); + +// map CC string to CC id +sparc_cc Sparc_map_ICC(const char *name); + +sparc_cc Sparc_map_FCC(const char *name); + +sparc_hint Sparc_map_hint(const char *name); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcMappingInsn.inc b/white_patch_detect/capstone-master/arch/Sparc/SparcMappingInsn.inc new file mode 100644 index 0000000..6c97afc --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcMappingInsn.inc @@ -0,0 +1,2643 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + SP_ADDCCri, SPARC_INS_ADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDCCrr, SPARC_INS_ADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDCri, SPARC_INS_ADDX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDCrr, SPARC_INS_ADDX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDEri, SPARC_INS_ADDXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDErr, SPARC_INS_ADDXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDXC, SPARC_INS_ADDXC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_ADDXCCC, SPARC_INS_ADDXCCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_ADDXri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ADDXrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ADDrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ALIGNADDR, SPARC_INS_ALIGNADDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_ALIGNADDRL, SPARC_INS_ALIGNADDRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_ANDCCri, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDCCrr, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDNCCri, SPARC_INS_ANDNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDNCCrr, SPARC_INS_ANDNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDNri, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDNrr, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDXNrr, SPARC_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ANDXri, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ANDXrr, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ANDri, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ANDrr, SPARC_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ARRAY16, SPARC_INS_ARRAY16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_ARRAY32, SPARC_INS_ARRAY32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_ARRAY8, SPARC_INS_ARRAY8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_BA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SP_BCOND, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SP_BCONDA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SP_BINDri, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SP_BINDrr, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SP_BMASK, SPARC_INS_BMASK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_BPFCC, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPFCCA, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPFCCANT, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPFCCNT, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPGEZapn, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGEZapt, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGEZnapn, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGEZnapt, SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGZapn, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGZapt, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGZnapn, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPGZnapt, SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPICC, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPICCA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPICCANT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPICCNT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 +#endif +}, +{ + SP_BPLEZapn, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLEZapt, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLEZnapn, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLEZnapt, SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLZapn, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLZapt, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLZnapn, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPLZnapt, SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPNZapn, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPNZapt, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPNZnapn, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPNZnapt, SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPXCC, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPXCCA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPXCCANT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPXCCNT, SPARC_INS_B, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPZapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPZapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPZnapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BPZnapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 +#endif +}, +{ + SP_BSHUFFLE, SPARC_INS_BSHUFFLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_CALL, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_CALLri, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_CALLrr, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_CASXrr, SPARC_INS_CASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_CASrr, SPARC_INS_CAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_CMASK16, SPARC_INS_CMASK16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_CMASK32, SPARC_INS_CMASK32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_CMASK8, SPARC_INS_CMASK8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_CMPri, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_CMPrr, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_EDGE16, SPARC_INS_EDGE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE16L, SPARC_INS_EDGE16L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE16LN, SPARC_INS_EDGE16LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE16N, SPARC_INS_EDGE16N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE32, SPARC_INS_EDGE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE32L, SPARC_INS_EDGE32L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE32LN, SPARC_INS_EDGE32LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE32N, SPARC_INS_EDGE32N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE8, SPARC_INS_EDGE8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE8L, SPARC_INS_EDGE8L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE8LN, SPARC_INS_EDGE8LN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_EDGE8N, SPARC_INS_EDGE8N, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_FABSD, SPARC_INS_FABSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FABSQ, SPARC_INS_FABSQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FABSS, SPARC_INS_FABSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FADDD, SPARC_INS_FADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FADDQ, SPARC_INS_FADDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FADDS, SPARC_INS_FADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FALIGNADATA, SPARC_INS_FALIGNDATA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FAND, SPARC_INS_FAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FANDNOT1, SPARC_INS_FANDNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FANDNOT1S, SPARC_INS_FANDNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FANDNOT2, SPARC_INS_FANDNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FANDNOT2S, SPARC_INS_FANDNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FANDS, SPARC_INS_FANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FBCOND, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SP_FBCONDA, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SP_FCHKSM16, SPARC_INS_FCHKSM16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FCMPEQ16, SPARC_INS_FCMPEQ16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPEQ32, SPARC_INS_FCMPEQ32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPGT16, SPARC_INS_FCMPGT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPGT32, SPARC_INS_FCMPGT32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPLE16, SPARC_INS_FCMPLE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPLE32, SPARC_INS_FCMPLE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPNE16, SPARC_INS_FCMPNE16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPNE32, SPARC_INS_FCMPNE32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPQ, SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FDIVD, SPARC_INS_FDIVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FDIVQ, SPARC_INS_FDIVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FDIVS, SPARC_INS_FDIVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FDMULQ, SPARC_INS_FDMULQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FDTOI, SPARC_INS_FDTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FDTOQ, SPARC_INS_FDTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FDTOS, SPARC_INS_FDTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FDTOX, SPARC_INS_FDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FEXPAND, SPARC_INS_FEXPAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FHADDD, SPARC_INS_FHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FHADDS, SPARC_INS_FHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FHSUBD, SPARC_INS_FHSUBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FHSUBS, SPARC_INS_FHSUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FITOD, SPARC_INS_FITOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FITOQ, SPARC_INS_FITOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FITOS, SPARC_INS_FITOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FLCMPD, SPARC_INS_FLCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FLCMPS, SPARC_INS_FLCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FLUSHW, SPARC_INS_FLUSHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMEAN16, SPARC_INS_FMEAN16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVD, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVD_FCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVD_ICC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVD_XCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVQ, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVQ_FCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVQ_ICC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVQ_XCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGEZD, SPARC_INS_FMOVRDGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGEZQ, SPARC_INS_FMOVRQGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGEZS, SPARC_INS_FMOVRSGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGZD, SPARC_INS_FMOVRDGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGZQ, SPARC_INS_FMOVRQGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRGZS, SPARC_INS_FMOVRSGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLEZD, SPARC_INS_FMOVRDLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLEZQ, SPARC_INS_FMOVRQLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLEZS, SPARC_INS_FMOVRSLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLZD, SPARC_INS_FMOVRDLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLZQ, SPARC_INS_FMOVRQLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRLZS, SPARC_INS_FMOVRSLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRNZD, SPARC_INS_FMOVRDNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRNZQ, SPARC_INS_FMOVRQNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRNZS, SPARC_INS_FMOVRSNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRZD, SPARC_INS_FMOVRDZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRZQ, SPARC_INS_FMOVRQZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVRZS, SPARC_INS_FMOVRSZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVS, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FMOVS_FCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVS_ICC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FMOVS_XCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FMUL8SUX16, SPARC_INS_FMUL8SUX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMUL8ULX16, SPARC_INS_FMUL8ULX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMUL8X16, SPARC_INS_FMUL8X16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMUL8X16AL, SPARC_INS_FMUL8X16AL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMUL8X16AU, SPARC_INS_FMUL8X16AU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMULD, SPARC_INS_FMULD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FMULD8SUX16, SPARC_INS_FMULD8SUX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMULD8ULX16, SPARC_INS_FMULD8ULX16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FMULQ, SPARC_INS_FMULQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FMULS, SPARC_INS_FMULS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FNADDD, SPARC_INS_FNADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNADDS, SPARC_INS_FNADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNAND, SPARC_INS_FNAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNANDS, SPARC_INS_FNANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNEGD, SPARC_INS_FNEGD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FNEGQ, SPARC_INS_FNEGQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_FNEGS, SPARC_INS_FNEGS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FNHADDD, SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNHADDS, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNMULD, SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNMULS, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FNOR, SPARC_INS_FNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNORS, SPARC_INS_FNORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNOT1, SPARC_INS_FNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNOT1S, SPARC_INS_FNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNOT2, SPARC_INS_FNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNOT2S, SPARC_INS_FNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FNSMULD, SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FONE, SPARC_INS_FONE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FONES, SPARC_INS_FONES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FOR, SPARC_INS_FOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FORNOT1, SPARC_INS_FORNOT1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FORNOT1S, SPARC_INS_FORNOT1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FORNOT2, SPARC_INS_FORNOT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FORNOT2S, SPARC_INS_FORNOT2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FORS, SPARC_INS_FORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPACK16, SPARC_INS_FPACK16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPACK32, SPARC_INS_FPACK32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPACKFIX, SPARC_INS_FPACKFIX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPADD16, SPARC_INS_FPADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPADD16S, SPARC_INS_FPADD16S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPADD32, SPARC_INS_FPADD32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPADD32S, SPARC_INS_FPADD32S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPADD64, SPARC_INS_FPADD64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FPMERGE, SPARC_INS_FPMERGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPSUB16, SPARC_INS_FPSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPSUB16S, SPARC_INS_FPSUB16S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPSUB32, SPARC_INS_FPSUB32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FPSUB32S, SPARC_INS_FPSUB32S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FQTOD, SPARC_INS_FQTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FQTOI, SPARC_INS_FQTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FQTOS, SPARC_INS_FQTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FQTOX, SPARC_INS_FQTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FSLAS16, SPARC_INS_FSLAS16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSLAS32, SPARC_INS_FSLAS32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSLL16, SPARC_INS_FSLL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSLL32, SPARC_INS_FSLL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSMULD, SPARC_INS_FSMULD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSQRTD, SPARC_INS_FSQRTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSQRTQ, SPARC_INS_FSQRTQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FSQRTS, SPARC_INS_FSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSRA16, SPARC_INS_FSRA16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSRA32, SPARC_INS_FSRA32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSRC1, SPARC_INS_FSRC1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FSRC1S, SPARC_INS_FSRC1S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FSRC2, SPARC_INS_FSRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FSRC2S, SPARC_INS_FSRC2S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FSRL16, SPARC_INS_FSRL16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSRL32, SPARC_INS_FSRL32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_FSTOD, SPARC_INS_FSTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSTOI, SPARC_INS_FSTOI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSTOQ, SPARC_INS_FSTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FSTOX, SPARC_INS_FSTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FSUBD, SPARC_INS_FSUBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FSUBQ, SPARC_INS_FSUBQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_FSUBS, SPARC_INS_FSUBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_FXNOR, SPARC_INS_FXNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FXNORS, SPARC_INS_FXNORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FXOR, SPARC_INS_FXOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FXORS, SPARC_INS_FXORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FXTOD, SPARC_INS_FXTOD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FXTOQ, SPARC_INS_FXTOQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FXTOS, SPARC_INS_FXTOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_FZERO, SPARC_INS_FZERO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_FZEROS, SPARC_INS_FZEROS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_JMPLri, SPARC_INS_JMPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_JMPLrr, SPARC_INS_JMPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDDFri, SPARC_INS_LDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDDFrr, SPARC_INS_LDD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDFri, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDFrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDQFri, SPARC_INS_LDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_LDQFrr, SPARC_INS_LDQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_LDSBri, SPARC_INS_LDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDSBrr, SPARC_INS_LDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDSHri, SPARC_INS_LDSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDSHrr, SPARC_INS_LDSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDSWri, SPARC_INS_LDSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LDSWrr, SPARC_INS_LDSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LDUBri, SPARC_INS_LDUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDUBrr, SPARC_INS_LDUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDUHri, SPARC_INS_LDUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDUHrr, SPARC_INS_LDUH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDXri, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LDXrr, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LDri, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LDrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_LEAX_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LEA_ADDri, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_32BIT, 0 }, 0, 0 +#endif +}, +{ + SP_LZCNT, SPARC_INS_LZCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MEMBARi, SPARC_INS_MEMBAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_MOVDTOX, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MOVFCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_MOVFCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_MOVICCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_MOVICCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRGEZri, SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRGEZrr, SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRGZri, SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRGZrr, SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRLEZri, SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRLEZrr, SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRLZri, SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRLZrr, SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRNZri, SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRNZrr, SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRRZri, SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVRRZrr, SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVSTOSW, SPARC_INS_MOVSTOSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MOVSTOUW, SPARC_INS_MOVSTOUW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MOVWTOS, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MOVXCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVXCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MOVXTOD, SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_MULXri, SPARC_INS_MULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_MULXrr, SPARC_INS_MULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_NOP, SPARC_INS_NOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORCCri, SPARC_INS_ORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORCCrr, SPARC_INS_ORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORNCCri, SPARC_INS_ORNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORNCCrr, SPARC_INS_ORNCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORNri, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORNrr, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORXNrr, SPARC_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ORXri, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ORXrr, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_ORri, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_ORrr, SPARC_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_PDIST, SPARC_INS_PDIST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_PDISTN, SPARC_INS_PDISTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_POPCrr, SPARC_INS_POPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_RDY, SPARC_INS_RD, +#ifndef CAPSTONE_DIET + { SPARC_REG_Y, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RESTOREri, SPARC_INS_RESTORE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RESTORErr, SPARC_INS_RESTORE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RET, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RETL, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RETTri, SPARC_INS_RETT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_RETTrr, SPARC_INS_RETT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SAVEri, SPARC_INS_SAVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SAVErr, SPARC_INS_SAVE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SDIVCCri, SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SDIVCCrr, SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SDIVXri, SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SDIVXrr, SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SDIVri, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SDIVrr, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SETHIXi, SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SETHIi, SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SHUTDOWN, SPARC_INS_SHUTDOWN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 +#endif +}, +{ + SP_SIAM, SPARC_INS_SIAM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 +#endif +}, +{ + SP_SLLXri, SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SLLXrr, SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SLLri, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SLLrr, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SMULCCri, SPARC_INS_SMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SMULCCrr, SPARC_INS_SMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SMULri, SPARC_INS_SMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SMULrr, SPARC_INS_SMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SRAXri, SPARC_INS_SRAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SRAXrr, SPARC_INS_SRAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SRAri, SPARC_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SRArr, SPARC_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SRLXri, SPARC_INS_SRLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SRLXrr, SPARC_INS_SRLX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SRLri, SPARC_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SRLrr, SPARC_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STBAR, SPARC_INS_STBAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STBri, SPARC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STBrr, SPARC_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STDFri, SPARC_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STDFrr, SPARC_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STFri, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STFrr, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STHri, SPARC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STHrr, SPARC_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STQFri, SPARC_INS_STQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_STQFrr, SPARC_INS_STQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_STXri, SPARC_INS_STX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_STXrr, SPARC_INS_STX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_STri, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_STrr, SPARC_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBCCri, SPARC_INS_SUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBCCrr, SPARC_INS_SUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBCri, SPARC_INS_SUBX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBCrr, SPARC_INS_SUBX, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBEri, SPARC_INS_SUBXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBErr, SPARC_INS_SUBXCC, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBXri, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SUBXrr, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_SUBri, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SUBrr, SPARC_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SWAPri, SPARC_INS_SWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_SWAPrr, SPARC_INS_SWAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TA3, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TA5, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TADDCCTVri, SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TADDCCTVrr, SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TADDCCri, SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TADDCCrr, SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TICCri, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TICCrr, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TLS_ADDXrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_TLS_ADDrr, SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TLS_CALL, SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TLS_LDXrr, SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_TLS_LDrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TSUBCCTVri, SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TSUBCCTVrr, SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TSUBCCri, SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TSUBCCrr, SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_TXCCri, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_TXCCrr, SPARC_INS_T, +#ifndef CAPSTONE_DIET + { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_UDIVCCri, SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UDIVCCrr, SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UDIVXri, SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_UDIVXrr, SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_UDIVri, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UDIVrr, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UMULCCri, SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UMULCCrr, SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UMULXHI, SPARC_INS_UMULXHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_UMULri, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UMULrr, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_UNIMP, SPARC_INS_UNIMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPED, SPARC_INS_FCMPED, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPEQ, SPARC_INS_FCMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPES, SPARC_INS_FCMPES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPQ, SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 +#endif +}, +{ + SP_V9FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_V9FMOVD_FCC, SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_V9FMOVQ_FCC, SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_V9FMOVS_FCC, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_V9MOVFCCri, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_V9MOVFCCrr, SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 +#endif +}, +{ + SP_WRYri, SPARC_INS_WR, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_WRYrr, SPARC_INS_WR, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XMULX, SPARC_INS_XMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_XMULXHI, SPARC_INS_XMULXHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 +#endif +}, +{ + SP_XNORCCri, SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XNORCCrr, SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XNORXrr, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_XNORri, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XNORrr, SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XORCCri, SPARC_INS_XORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XORCCrr, SPARC_INS_XORCC, +#ifndef CAPSTONE_DIET + { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XORXri, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_XORXrr, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 +#endif +}, +{ + SP_XORri, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SP_XORrr, SPARC_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcModule.c b/white_patch_detect/capstone-master/arch/Sparc/SparcModule.c new file mode 100644 index 0000000..88a0a9e --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcModule.c @@ -0,0 +1,45 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SPARC + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "SparcDisassembler.h" +#include "SparcInstPrinter.h" +#include "SparcMapping.h" +#include "SparcModule.h" + +cs_err Sparc_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + Sparc_init(mri); + ud->printer = Sparc_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = Sparc_getInstruction; + ud->post_printer = Sparc_post_printer; + + ud->reg_name = Sparc_reg_name; + ud->insn_id = Sparc_get_insn_id; + ud->insn_name = Sparc_insn_name; + ud->group_name = Sparc_group_name; + + return CS_ERR_OK; +} + +cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_SYNTAX) + handle->syntax = (int) value; + + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/Sparc/SparcModule.h b/white_patch_detect/capstone-master/arch/Sparc/SparcModule.h new file mode 100644 index 0000000..1caaac1 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/Sparc/SparcModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_SPARC_MODULE_H +#define CS_SPARC_MODULE_H + +#include "../../utils.h" + +cs_err Sparc_global_init(cs_struct *ud); +cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.c b/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.c new file mode 100644 index 0000000..a64a85c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.c @@ -0,0 +1,484 @@ +//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SYSZ + +#include // DEBUG +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "SystemZDisassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + +#include "SystemZMCTargetDesc.h" + +static uint64_t getFeatureBits(int mode) +{ + // support everything + return (uint64_t)-1; +} + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) +{ + //assert(RegNo < 16 && "Invalid register"); + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, (unsigned)RegNo); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); +} + +static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); +} + +static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); +} + +static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); +} + +static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); +} + +static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs); +} + +static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs); +} + +static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs); +} + +static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs); +} + +static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs); +} + +static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs); +} + +static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs); +} + +static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) +{ + return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs); +} + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) +{ + //assert(isUInt(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) +{ + //assert(isUInt(Imm) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeUImmOperand(Inst, Imm); +} + +static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeSImmOperand(Inst, Imm, 8); +} + +static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeSImmOperand(Inst, Imm, 16); +} + +static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) +{ + return decodeSImmOperand(Inst, Imm, 32); +} + +static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, unsigned N) +{ + //assert(isUInt(Imm) && "Invalid PC-relative offset"); + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address); + return MCDisassembler_Success; +} + +static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) +{ + return decodePCDBLOperand(Inst, Imm, Address, 12); +} + +static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) +{ + return decodePCDBLOperand(Inst, Imm, Address, 16); +} + +static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) +{ + return decodePCDBLOperand(Inst, Imm, Address, 24); +} + +static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) +{ + return decodePCDBLOperand(Inst, Imm, Address, 32); +} + +static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + const void *Decoder) +{ + return decodePCDBLOperand(Inst, Imm, Address, 32); +} + +static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Base = Field >> 12; + uint64_t Disp = Field & 0xfff; + //assert(Base < 16 && "Invalid BDAddr12"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Base = Field >> 20; + uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); + //assert(Base < 16 && "Invalid BDAddr20"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + + //assert(Index < 16 && "Invalid BDXAddr12"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Index = Field >> 24; + uint64_t Base = (Field >> 20) & 0xf; + uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); + + //assert(Index < 16 && "Invalid BDXAddr20"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); + MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Length = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + //assert(Length < 256 && "Invalid BDLAddr12Len8"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateImm0(Inst, Length + 1); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Length = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + //assert(Length < 16 && "Invalid BDRAddr12"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, Regs[Length]); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) +{ + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + //assert(Index < 32 && "Invalid BDVAddr12"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); + + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); +} + +static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); +} + +static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, const void *Decoder) +{ + return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + + +#define GET_SUBTARGETINFO_ENUM +#include "SystemZGenSubtargetInfo.inc" +#include "SystemZGenDisassemblerTables.inc" +bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, + uint16_t *size, uint64_t address, void *info) +{ + uint64_t Inst; + const uint8_t *Table; + uint16_t I; + + // The top 2 bits of the first byte specify the size. + if (*code < 0x40) { + *size = 2; + Table = DecoderTable16; + } else if (*code < 0xc0) { + *size = 4; + Table = DecoderTable32; + } else { + *size = 6; + Table = DecoderTable48; + } + + if (code_len < *size) + // short of input data + return false; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz)); + } + + // Construct the instruction. + Inst = 0; + for (I = 0; I < *size; ++I) + Inst = (Inst << 8) | code[I]; + + return decodeInstruction(Table, MI, Inst, address, info, 0); +} + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "SystemZGenRegisterInfo.inc" +void SystemZ_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, + SystemZMCRegisterClasses, 12, + SystemZRegUnitRoots, + 49, + SystemZRegDiffLists, + SystemZRegStrings, + SystemZSubRegIdxLists, + 7, + SystemZSubRegIdxRanges, + SystemZRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194, + 0, 0, + SystemZMCRegisterClasses, 21, + 0, 0, + SystemZRegDiffLists, + 0, + SystemZSubRegIdxLists, 7, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.h b/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.h new file mode 100644 index 0000000..8b6e540 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZDisassembler.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SYSZDISASSEMBLER_H +#define CS_SYSZDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void SystemZ_init(MCRegisterInfo *MRI); + +bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenAsmWriter.inc new file mode 100644 index 0000000..bdc3a5a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenAsmWriter.inc @@ -0,0 +1,11565 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include // debug +#include + + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'c', 'u', '2', '1', 9, 0, + /* 6 */ 'c', 'u', '4', '1', 9, 0, + /* 12 */ 'c', 'u', '1', '2', 9, 0, + /* 18 */ 'c', 'u', '4', '2', 9, 0, + /* 24 */ 'c', 'u', '1', '4', 9, 0, + /* 30 */ 'c', 'u', '2', '4', 9, 0, + /* 36 */ 't', 'r', 'a', 'p', '4', 9, 0, + /* 43 */ 'l', 'a', 'a', 9, 0, + /* 48 */ 's', 'l', 'd', 'a', 9, 0, + /* 54 */ 's', 'r', 'd', 'a', 9, 0, + /* 60 */ 'e', 's', 'e', 'a', 9, 0, + /* 66 */ 'l', 'p', 't', 'e', 'a', 9, 0, + /* 73 */ 'v', 'f', 'a', 9, 0, + /* 78 */ 's', 'i', 'g', 'a', 9, 0, + /* 84 */ 'e', 'c', 'p', 'g', 'a', 9, 0, + /* 91 */ 'u', 'n', 'p', 'k', 'a', 9, 0, + /* 98 */ 's', 'p', 'k', 'a', 9, 0, + /* 104 */ 's', 'l', 'a', 9, 0, + /* 109 */ 'v', 'g', 'f', 'm', 'a', 9, 0, + /* 116 */ 'v', 'f', 'm', 'a', 9, 0, + /* 122 */ 'k', 'm', 'a', 9, 0, + /* 127 */ 'v', 'f', 'n', 'm', 'a', 9, 0, + /* 134 */ 'p', 'p', 'a', 9, 0, + /* 139 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0, + /* 147 */ 'c', 'f', 'd', 'b', 'r', 'a', 9, 0, + /* 155 */ 'c', 'g', 'd', 'b', 'r', 'a', 9, 0, + /* 163 */ 'f', 'i', 'd', 'b', 'r', 'a', 9, 0, + /* 171 */ 'c', 'f', 'e', 'b', 'r', 'a', 9, 0, + /* 179 */ 'c', 'g', 'e', 'b', 'r', 'a', 9, 0, + /* 187 */ 'f', 'i', 'e', 'b', 'r', 'a', 9, 0, + /* 195 */ 'c', 'd', 'f', 'b', 'r', 'a', 9, 0, + /* 203 */ 'c', 'e', 'f', 'b', 'r', 'a', 9, 0, + /* 211 */ 'c', 'x', 'f', 'b', 'r', 'a', 9, 0, + /* 219 */ 'c', 'd', 'g', 'b', 'r', 'a', 9, 0, + /* 227 */ 'c', 'e', 'g', 'b', 'r', 'a', 9, 0, + /* 235 */ 'c', 'x', 'g', 'b', 'r', 'a', 9, 0, + /* 243 */ 'l', 'd', 'x', 'b', 'r', 'a', 9, 0, + /* 251 */ 'l', 'e', 'x', 'b', 'r', 'a', 9, 0, + /* 259 */ 'c', 'f', 'x', 'b', 'r', 'a', 9, 0, + /* 267 */ 'c', 'g', 'x', 'b', 'r', 'a', 9, 0, + /* 275 */ 'f', 'i', 'x', 'b', 'r', 'a', 9, 0, + /* 283 */ 'l', 'r', 'a', 9, 0, + /* 288 */ 'v', 'e', 's', 'r', 'a', 9, 0, + /* 295 */ 'v', 's', 'r', 'a', 9, 0, + /* 301 */ 'a', 'd', 't', 'r', 'a', 9, 0, + /* 308 */ 'd', 'd', 't', 'r', 'a', 9, 0, + /* 315 */ 'c', 'g', 'd', 't', 'r', 'a', 9, 0, + /* 323 */ 'm', 'd', 't', 'r', 'a', 9, 0, + /* 330 */ 's', 'd', 't', 'r', 'a', 9, 0, + /* 337 */ 'c', 'd', 'g', 't', 'r', 'a', 9, 0, + /* 345 */ 'c', 'x', 'g', 't', 'r', 'a', 9, 0, + /* 353 */ 'a', 'x', 't', 'r', 'a', 9, 0, + /* 360 */ 'd', 'x', 't', 'r', 'a', 9, 0, + /* 367 */ 'c', 'g', 'x', 't', 'r', 'a', 9, 0, + /* 375 */ 'm', 'x', 't', 'r', 'a', 9, 0, + /* 382 */ 's', 'x', 't', 'r', 'a', 9, 0, + /* 389 */ 'l', 'u', 'r', 'a', 9, 0, + /* 395 */ 's', 't', 'u', 'r', 'a', 9, 0, + /* 402 */ 'b', 's', 'a', 9, 0, + /* 407 */ 'e', 's', 't', 'a', 9, 0, + /* 413 */ 'm', 's', 't', 'a', 9, 0, + /* 419 */ 'v', 'a', 9, 0, + /* 423 */ 'c', 'p', 'y', 'a', 9, 0, + /* 429 */ 'v', 'g', 'f', 'm', 'a', 'b', 9, 0, + /* 437 */ 'v', 'e', 's', 'r', 'a', 'b', 9, 0, + /* 445 */ 'v', 's', 'r', 'a', 'b', 9, 0, + /* 452 */ 'v', 'a', 'b', 9, 0, + /* 457 */ 'l', 'c', 'b', 'b', 9, 0, + /* 463 */ 'v', 'l', 'b', 'b', 9, 0, + /* 469 */ 'v', 'a', 'c', 'c', 'b', 9, 0, + /* 476 */ 'v', 'e', 'c', 'b', 9, 0, + /* 482 */ 'v', 'l', 'c', 'b', 9, 0, + /* 488 */ 'v', 's', 't', 'r', 'c', 'b', 9, 0, + /* 496 */ 'v', 'f', 'a', 'd', 'b', 9, 0, + /* 503 */ 'w', 'f', 'a', 'd', 'b', 9, 0, + /* 510 */ 'v', 'f', 'm', 'a', 'd', 'b', 9, 0, + /* 518 */ 'w', 'f', 'm', 'a', 'd', 'b', 9, 0, + /* 526 */ 'v', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, + /* 535 */ 'w', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, + /* 544 */ 'w', 'f', 'c', 'd', 'b', 9, 0, + /* 551 */ 'v', 'f', 'l', 'c', 'd', 'b', 9, 0, + /* 559 */ 'w', 'f', 'l', 'c', 'd', 'b', 9, 0, + /* 567 */ 't', 'c', 'd', 'b', 9, 0, + /* 573 */ 'v', 'f', 'd', 'd', 'b', 9, 0, + /* 580 */ 'w', 'f', 'd', 'd', 'b', 9, 0, + /* 587 */ 'v', 'f', 'c', 'e', 'd', 'b', 9, 0, + /* 595 */ 'w', 'f', 'c', 'e', 'd', 'b', 9, 0, + /* 603 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, + /* 612 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, + /* 621 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, + /* 630 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, + /* 639 */ 'v', 'f', 'k', 'e', 'd', 'b', 9, 0, + /* 647 */ 'w', 'f', 'k', 'e', 'd', 'b', 9, 0, + /* 655 */ 'v', 'l', 'e', 'd', 'b', 9, 0, + /* 662 */ 'w', 'l', 'e', 'd', 'b', 9, 0, + /* 669 */ 'v', 'c', 'g', 'd', 'b', 9, 0, + /* 676 */ 'w', 'c', 'g', 'd', 'b', 9, 0, + /* 683 */ 'v', 'c', 'l', 'g', 'd', 'b', 9, 0, + /* 691 */ 'w', 'c', 'l', 'g', 'd', 'b', 9, 0, + /* 699 */ 'v', 'f', 'c', 'h', 'd', 'b', 9, 0, + /* 707 */ 'w', 'f', 'c', 'h', 'd', 'b', 9, 0, + /* 715 */ 'v', 'f', 'k', 'h', 'd', 'b', 9, 0, + /* 723 */ 'w', 'f', 'k', 'h', 'd', 'b', 9, 0, + /* 731 */ 'v', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, + /* 740 */ 'w', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, + /* 749 */ 'v', 'f', 'i', 'd', 'b', 9, 0, + /* 756 */ 'w', 'f', 'i', 'd', 'b', 9, 0, + /* 763 */ 'w', 'f', 'k', 'd', 'b', 9, 0, + /* 770 */ 'v', 's', 'l', 'd', 'b', 9, 0, + /* 777 */ 'v', 'f', 'm', 'd', 'b', 9, 0, + /* 784 */ 'w', 'f', 'm', 'd', 'b', 9, 0, + /* 791 */ 'v', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, + /* 800 */ 'w', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, + /* 809 */ 'v', 'f', 'l', 'n', 'd', 'b', 9, 0, + /* 817 */ 'w', 'f', 'l', 'n', 'd', 'b', 9, 0, + /* 825 */ 'v', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, + /* 834 */ 'w', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, + /* 843 */ 'v', 'f', 'l', 'p', 'd', 'b', 9, 0, + /* 851 */ 'w', 'f', 'l', 'p', 'd', 'b', 9, 0, + /* 859 */ 'v', 'f', 's', 'q', 'd', 'b', 9, 0, + /* 867 */ 'w', 'f', 's', 'q', 'd', 'b', 9, 0, + /* 875 */ 'v', 'f', 's', 'd', 'b', 9, 0, + /* 882 */ 'w', 'f', 's', 'd', 'b', 9, 0, + /* 889 */ 'v', 'f', 'm', 's', 'd', 'b', 9, 0, + /* 897 */ 'w', 'f', 'm', 's', 'd', 'b', 9, 0, + /* 905 */ 'v', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, + /* 914 */ 'w', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, + /* 923 */ 'v', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, + /* 932 */ 'w', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, + /* 941 */ 'l', 'x', 'd', 'b', 9, 0, + /* 947 */ 'm', 'x', 'd', 'b', 9, 0, + /* 953 */ 'v', 'f', 'a', 'e', 'b', 9, 0, + /* 960 */ 'v', 'm', 'a', 'e', 'b', 9, 0, + /* 967 */ 't', 'c', 'e', 'b', 9, 0, + /* 973 */ 'v', 'l', 'd', 'e', 'b', 9, 0, + /* 980 */ 'w', 'l', 'd', 'e', 'b', 9, 0, + /* 987 */ 'm', 'd', 'e', 'b', 9, 0, + /* 993 */ 'v', 'f', 'e', 'e', 'b', 9, 0, + /* 1000 */ 'm', 'e', 'e', 'b', 9, 0, + /* 1006 */ 'k', 'e', 'b', 9, 0, + /* 1011 */ 'v', 'm', 'a', 'l', 'e', 'b', 9, 0, + /* 1019 */ 'v', 'm', 'l', 'e', 'b', 9, 0, + /* 1026 */ 'v', 'l', 'e', 'b', 9, 0, + /* 1032 */ 'v', 'm', 'e', 'b', 9, 0, + /* 1038 */ 'v', 'f', 'e', 'n', 'e', 'b', 9, 0, + /* 1046 */ 's', 'q', 'e', 'b', 9, 0, + /* 1052 */ 'm', 's', 'e', 'b', 9, 0, + /* 1058 */ 'v', 's', 't', 'e', 'b', 9, 0, + /* 1065 */ 'l', 'x', 'e', 'b', 9, 0, + /* 1071 */ 'v', 'c', 'd', 'g', 'b', 9, 0, + /* 1078 */ 'w', 'c', 'd', 'g', 'b', 9, 0, + /* 1085 */ 'v', 's', 'e', 'g', 'b', 9, 0, + /* 1092 */ 'v', 'c', 'd', 'l', 'g', 'b', 9, 0, + /* 1100 */ 'w', 'c', 'd', 'l', 'g', 'b', 9, 0, + /* 1108 */ 'v', 'a', 'v', 'g', 'b', 9, 0, + /* 1115 */ 'v', 'l', 'v', 'g', 'b', 9, 0, + /* 1122 */ 'v', 'm', 'a', 'h', 'b', 9, 0, + /* 1129 */ 'v', 'c', 'h', 'b', 9, 0, + /* 1135 */ 'v', 'm', 'a', 'l', 'h', 'b', 9, 0, + /* 1143 */ 'v', 'm', 'l', 'h', 'b', 9, 0, + /* 1150 */ 'v', 'u', 'p', 'l', 'h', 'b', 9, 0, + /* 1158 */ 'v', 'm', 'h', 'b', 9, 0, + /* 1164 */ 'v', 'u', 'p', 'h', 'b', 9, 0, + /* 1171 */ 'v', 'm', 'r', 'h', 'b', 9, 0, + /* 1178 */ 'v', 's', 'c', 'b', 'i', 'b', 9, 0, + /* 1186 */ 'c', 'i', 'b', 9, 0, + /* 1191 */ 'v', 'l', 'e', 'i', 'b', 9, 0, + /* 1198 */ 'c', 'g', 'i', 'b', 9, 0, + /* 1204 */ 'c', 'l', 'g', 'i', 'b', 9, 0, + /* 1211 */ 'c', 'l', 'i', 'b', 9, 0, + /* 1217 */ 'v', 'r', 'e', 'p', 'i', 'b', 9, 0, + /* 1225 */ 'v', 'm', 'a', 'l', 'b', 9, 0, + /* 1232 */ 'v', 'e', 'c', 'l', 'b', 9, 0, + /* 1239 */ 'v', 'a', 'v', 'g', 'l', 'b', 9, 0, + /* 1247 */ 'v', 'c', 'h', 'l', 'b', 9, 0, + /* 1254 */ 'v', 'u', 'p', 'l', 'l', 'b', 9, 0, + /* 1262 */ 'v', 'e', 'r', 'l', 'l', 'b', 9, 0, + /* 1270 */ 'v', 'm', 'l', 'b', 9, 0, + /* 1276 */ 'v', 'm', 'n', 'l', 'b', 9, 0, + /* 1283 */ 'v', 'u', 'p', 'l', 'b', 9, 0, + /* 1290 */ 'v', 'm', 'r', 'l', 'b', 9, 0, + /* 1297 */ 'v', 'e', 's', 'r', 'l', 'b', 9, 0, + /* 1305 */ 'v', 's', 'r', 'l', 'b', 9, 0, + /* 1312 */ 'v', 'e', 's', 'l', 'b', 9, 0, + /* 1319 */ 'v', 's', 'l', 'b', 9, 0, + /* 1325 */ 'v', 'm', 'x', 'l', 'b', 9, 0, + /* 1332 */ 'v', 'g', 'f', 'm', 'b', 9, 0, + /* 1339 */ 'v', 'g', 'm', 'b', 9, 0, + /* 1345 */ 'v', 'e', 'r', 'i', 'm', 'b', 9, 0, + /* 1353 */ 's', 'r', 'n', 'm', 'b', 9, 0, + /* 1360 */ 'v', 's', 'u', 'm', 'b', 9, 0, + /* 1367 */ 'v', 'm', 'n', 'b', 9, 0, + /* 1373 */ 'v', 'm', 'a', 'o', 'b', 9, 0, + /* 1380 */ 'v', 'm', 'a', 'l', 'o', 'b', 9, 0, + /* 1388 */ 'v', 'm', 'l', 'o', 'b', 9, 0, + /* 1395 */ 'v', 'm', 'o', 'b', 9, 0, + /* 1401 */ 'v', 'l', 'r', 'e', 'p', 'b', 9, 0, + /* 1409 */ 'v', 'r', 'e', 'p', 'b', 9, 0, + /* 1416 */ 'v', 'l', 'p', 'b', 9, 0, + /* 1422 */ 'v', 'c', 'e', 'q', 'b', 9, 0, + /* 1429 */ 'c', 'r', 'b', 9, 0, + /* 1434 */ 'c', 'g', 'r', 'b', 9, 0, + /* 1440 */ 'c', 'l', 'g', 'r', 'b', 9, 0, + /* 1447 */ 'c', 'l', 'r', 'b', 9, 0, + /* 1453 */ 'v', 'i', 's', 't', 'r', 'b', 9, 0, + /* 1461 */ 'v', 'f', 'a', 's', 'b', 9, 0, + /* 1468 */ 'w', 'f', 'a', 's', 'b', 9, 0, + /* 1475 */ 'v', 'f', 'm', 'a', 's', 'b', 9, 0, + /* 1483 */ 'w', 'f', 'm', 'a', 's', 'b', 9, 0, + /* 1491 */ 'v', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, + /* 1500 */ 'w', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, + /* 1509 */ 'w', 'f', 'c', 's', 'b', 9, 0, + /* 1516 */ 'v', 'f', 'l', 'c', 's', 'b', 9, 0, + /* 1524 */ 'w', 'f', 'l', 'c', 's', 'b', 9, 0, + /* 1532 */ 'v', 'f', 'd', 's', 'b', 9, 0, + /* 1539 */ 'w', 'f', 'd', 's', 'b', 9, 0, + /* 1546 */ 'v', 'f', 'c', 'e', 's', 'b', 9, 0, + /* 1554 */ 'w', 'f', 'c', 'e', 's', 'b', 9, 0, + /* 1562 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, + /* 1571 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, + /* 1580 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, + /* 1589 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, + /* 1598 */ 'v', 'f', 'k', 'e', 's', 'b', 9, 0, + /* 1606 */ 'w', 'f', 'k', 'e', 's', 'b', 9, 0, + /* 1614 */ 'v', 'f', 'c', 'h', 's', 'b', 9, 0, + /* 1622 */ 'w', 'f', 'c', 'h', 's', 'b', 9, 0, + /* 1630 */ 'v', 'f', 'k', 'h', 's', 'b', 9, 0, + /* 1638 */ 'w', 'f', 'k', 'h', 's', 'b', 9, 0, + /* 1646 */ 'v', 'f', 't', 'c', 'i', 's', 'b', 9, 0, + /* 1655 */ 'w', 'f', 't', 'c', 'i', 's', 'b', 9, 0, + /* 1664 */ 'v', 'f', 'i', 's', 'b', 9, 0, + /* 1671 */ 'w', 'f', 'i', 's', 'b', 9, 0, + /* 1678 */ 'w', 'f', 'k', 's', 'b', 9, 0, + /* 1685 */ 'v', 'f', 'm', 's', 'b', 9, 0, + /* 1692 */ 'w', 'f', 'm', 's', 'b', 9, 0, + /* 1699 */ 'v', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, + /* 1708 */ 'w', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, + /* 1717 */ 'v', 'f', 'l', 'n', 's', 'b', 9, 0, + /* 1725 */ 'w', 'f', 'l', 'n', 's', 'b', 9, 0, + /* 1733 */ 'v', 'f', 'p', 's', 'o', 's', 'b', 9, 0, + /* 1742 */ 'w', 'f', 'p', 's', 'o', 's', 'b', 9, 0, + /* 1751 */ 'v', 'f', 'l', 'p', 's', 'b', 9, 0, + /* 1759 */ 'w', 'f', 'l', 'p', 's', 'b', 9, 0, + /* 1767 */ 'v', 'f', 's', 'q', 's', 'b', 9, 0, + /* 1775 */ 'w', 'f', 's', 'q', 's', 'b', 9, 0, + /* 1783 */ 'v', 'f', 's', 's', 'b', 9, 0, + /* 1790 */ 'w', 'f', 's', 's', 'b', 9, 0, + /* 1797 */ 'v', 'f', 'm', 's', 's', 'b', 9, 0, + /* 1805 */ 'w', 'f', 'm', 's', 's', 'b', 9, 0, + /* 1813 */ 'v', 'f', 'n', 'm', 's', 's', 'b', 9, 0, + /* 1822 */ 'w', 'f', 'n', 'm', 's', 's', 'b', 9, 0, + /* 1831 */ 'v', 's', 'b', 9, 0, + /* 1836 */ 'v', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, + /* 1845 */ 'w', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, + /* 1854 */ 'v', 'p', 'o', 'p', 'c', 't', 'b', 9, 0, + /* 1863 */ 'v', 'e', 's', 'r', 'a', 'v', 'b', 9, 0, + /* 1872 */ 'v', 'c', 'v', 'b', 9, 0, + /* 1878 */ 'v', 'l', 'g', 'v', 'b', 9, 0, + /* 1885 */ 'v', 'e', 'r', 'l', 'l', 'v', 'b', 9, 0, + /* 1894 */ 'v', 'e', 's', 'r', 'l', 'v', 'b', 9, 0, + /* 1903 */ 'v', 'e', 's', 'l', 'v', 'b', 9, 0, + /* 1911 */ 'w', 'f', 'a', 'x', 'b', 9, 0, + /* 1918 */ 'w', 'f', 'm', 'a', 'x', 'b', 9, 0, + /* 1926 */ 'w', 'f', 'n', 'm', 'a', 'x', 'b', 9, 0, + /* 1935 */ 'w', 'f', 'c', 'x', 'b', 9, 0, + /* 1942 */ 'w', 'f', 'l', 'c', 'x', 'b', 9, 0, + /* 1950 */ 't', 'c', 'x', 'b', 9, 0, + /* 1956 */ 'w', 'f', 'd', 'x', 'b', 9, 0, + /* 1963 */ 'w', 'f', 'c', 'e', 'x', 'b', 9, 0, + /* 1971 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 9, 0, + /* 1980 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 9, 0, + /* 1989 */ 'w', 'f', 'k', 'e', 'x', 'b', 9, 0, + /* 1997 */ 'w', 'f', 'c', 'h', 'x', 'b', 9, 0, + /* 2005 */ 'w', 'f', 'k', 'h', 'x', 'b', 9, 0, + /* 2013 */ 'w', 'f', 't', 'c', 'i', 'x', 'b', 9, 0, + /* 2022 */ 'w', 'f', 'i', 'x', 'b', 9, 0, + /* 2029 */ 'w', 'f', 'k', 'x', 'b', 9, 0, + /* 2036 */ 'w', 'f', 'm', 'x', 'b', 9, 0, + /* 2043 */ 'v', 'm', 'x', 'b', 9, 0, + /* 2049 */ 'w', 'f', 'm', 'i', 'n', 'x', 'b', 9, 0, + /* 2058 */ 'w', 'f', 'l', 'n', 'x', 'b', 9, 0, + /* 2066 */ 'w', 'f', 'p', 's', 'o', 'x', 'b', 9, 0, + /* 2075 */ 'w', 'f', 'l', 'p', 'x', 'b', 9, 0, + /* 2083 */ 'w', 'f', 's', 'q', 'x', 'b', 9, 0, + /* 2091 */ 'w', 'f', 's', 'x', 'b', 9, 0, + /* 2098 */ 'w', 'f', 'm', 's', 'x', 'b', 9, 0, + /* 2106 */ 'w', 'f', 'n', 'm', 's', 'x', 'b', 9, 0, + /* 2115 */ 'w', 'f', 'm', 'a', 'x', 'x', 'b', 9, 0, + /* 2124 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 9, 0, + /* 2133 */ 'v', 'f', 'a', 'e', 'z', 'b', 9, 0, + /* 2141 */ 'v', 'f', 'e', 'e', 'z', 'b', 9, 0, + /* 2149 */ 'v', 'l', 'l', 'e', 'z', 'b', 9, 0, + /* 2157 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 9, 0, + /* 2166 */ 'v', 'c', 'l', 'z', 'b', 9, 0, + /* 2173 */ 'v', 'c', 't', 'z', 'b', 9, 0, + /* 2180 */ 'i', 'a', 'c', 9, 0, + /* 2185 */ 'k', 'm', 'a', 'c', 9, 0, + /* 2191 */ 's', 'a', 'c', 9, 0, + /* 2196 */ 'v', 'a', 'c', 9, 0, + /* 2201 */ 'b', 'c', 9, 0, + /* 2205 */ 'v', 'a', 'c', 'c', 9, 0, + /* 2211 */ 'v', 'a', 'c', 'c', 'c', 9, 0, + /* 2218 */ 'v', 'e', 'c', 9, 0, + /* 2223 */ 'c', 'f', 'c', 9, 0, + /* 2228 */ 'w', 'f', 'c', 9, 0, + /* 2233 */ 'l', 'l', 'g', 'c', 9, 0, + /* 2239 */ 'm', 's', 'g', 'c', 9, 0, + /* 2245 */ 'b', 'i', 'c', 9, 0, + /* 2250 */ 's', 'c', 'k', 'c', 9, 0, + /* 2256 */ 's', 't', 'c', 'k', 'c', 9, 0, + /* 2263 */ 'm', 's', 'g', 'r', 'k', 'c', 9, 0, + /* 2271 */ 'm', 's', 'r', 'k', 'c', 9, 0, + /* 2278 */ 'a', 'l', 'c', 9, 0, + /* 2283 */ 'c', 'l', 'c', 9, 0, + /* 2288 */ 'l', 'l', 'c', 9, 0, + /* 2293 */ 'v', 'l', 'c', 9, 0, + /* 2298 */ 'k', 'm', 'c', 9, 0, + /* 2303 */ 't', 'b', 'e', 'g', 'i', 'n', 'c', 9, 0, + /* 2312 */ 'v', 'n', 'c', 9, 0, + /* 2317 */ 'l', 'o', 'c', 9, 0, + /* 2322 */ 's', 't', 'o', 'c', 9, 0, + /* 2328 */ 'v', 'o', 'c', 9, 0, + /* 2333 */ 'e', 'f', 'p', 'c', 9, 0, + /* 2339 */ 'l', 'f', 'p', 'c', 9, 0, + /* 2345 */ 's', 'f', 'p', 'c', 9, 0, + /* 2351 */ 's', 't', 'f', 'p', 'c', 9, 0, + /* 2358 */ 'b', 'r', 'c', 9, 0, + /* 2363 */ 'v', 's', 't', 'r', 'c', 9, 0, + /* 2370 */ 'l', 'g', 's', 'c', 9, 0, + /* 2376 */ 's', 't', 'g', 's', 'c', 9, 0, + /* 2383 */ 'm', 's', 'c', 9, 0, + /* 2388 */ 'c', 'm', 'p', 's', 'c', 9, 0, + /* 2395 */ 's', 't', 'c', 9, 0, + /* 2400 */ 'm', 'v', 'c', 9, 0, + /* 2405 */ 's', 'v', 'c', 9, 0, + /* 2410 */ 'x', 'c', 9, 0, + /* 2414 */ 'm', 'a', 'd', 9, 0, + /* 2419 */ 'c', 'd', 9, 0, + /* 2423 */ 'd', 'd', 9, 0, + /* 2427 */ 'v', 'l', 'e', 'd', 9, 0, + /* 2433 */ 'p', 'f', 'd', 9, 0, + /* 2438 */ 'v', 'f', 'd', 9, 0, + /* 2443 */ 'v', 'c', 'g', 'd', 9, 0, + /* 2449 */ 'v', 'c', 'l', 'g', 'd', 9, 0, + /* 2456 */ 'w', 'f', 'l', 'l', 'd', 9, 0, + /* 2463 */ 'k', 'i', 'm', 'd', 9, 0, + /* 2469 */ 'k', 'l', 'm', 'd', 9, 0, + /* 2475 */ 'e', 't', 'n', 'd', 9, 0, + /* 2481 */ 'l', 'p', 'd', 9, 0, + /* 2486 */ 's', 'q', 'd', 9, 0, + /* 2491 */ 'v', 'f', 'l', 'r', 'd', 9, 0, + /* 2498 */ 'w', 'f', 'l', 'r', 'd', 9, 0, + /* 2505 */ 'm', 's', 'd', 9, 0, + /* 2510 */ 's', 't', 'd', 9, 0, + /* 2515 */ 'v', 'c', 'v', 'd', 9, 0, + /* 2521 */ 'l', 'x', 'd', 9, 0, + /* 2526 */ 'm', 'x', 'd', 9, 0, + /* 2531 */ 'v', 'f', 'a', 'e', 9, 0, + /* 2537 */ 'l', 'a', 'e', 9, 0, + /* 2542 */ 'v', 'm', 'a', 'e', 9, 0, + /* 2548 */ 'c', 'i', 'b', 'e', 9, 0, + /* 2554 */ 'c', 'g', 'i', 'b', 'e', 9, 0, + /* 2561 */ 'c', 'l', 'g', 'i', 'b', 'e', 9, 0, + /* 2569 */ 'c', 'l', 'i', 'b', 'e', 9, 0, + /* 2576 */ 'c', 'r', 'b', 'e', 9, 0, + /* 2582 */ 'c', 'g', 'r', 'b', 'e', 9, 0, + /* 2589 */ 'c', 'l', 'g', 'r', 'b', 'e', 9, 0, + /* 2597 */ 'c', 'l', 'r', 'b', 'e', 9, 0, + /* 2604 */ 'r', 'r', 'b', 'e', 9, 0, + /* 2610 */ 't', 'r', 'a', 'c', 'e', 9, 0, + /* 2617 */ 'v', 'f', 'c', 'e', 9, 0, + /* 2623 */ 'l', 'o', 'c', 'e', 9, 0, + /* 2629 */ 's', 't', 'o', 'c', 'e', 9, 0, + /* 2636 */ 'v', 'l', 'd', 'e', 9, 0, + /* 2642 */ 'm', 'd', 'e', 9, 0, + /* 2647 */ 'v', 'f', 'e', 'e', 9, 0, + /* 2653 */ 'm', 'e', 'e', 9, 0, + /* 2658 */ 'l', 'o', 'c', 'g', 'e', 9, 0, + /* 2665 */ 's', 't', 'o', 'c', 'g', 'e', 9, 0, + /* 2673 */ 'j', 'g', 'e', 9, 0, + /* 2678 */ 'c', 'i', 'b', 'h', 'e', 9, 0, + /* 2685 */ 'c', 'g', 'i', 'b', 'h', 'e', 9, 0, + /* 2693 */ 'c', 'l', 'g', 'i', 'b', 'h', 'e', 9, 0, + /* 2702 */ 'c', 'l', 'i', 'b', 'h', 'e', 9, 0, + /* 2710 */ 'c', 'r', 'b', 'h', 'e', 9, 0, + /* 2717 */ 'c', 'g', 'r', 'b', 'h', 'e', 9, 0, + /* 2725 */ 'c', 'l', 'g', 'r', 'b', 'h', 'e', 9, 0, + /* 2734 */ 'c', 'l', 'r', 'b', 'h', 'e', 9, 0, + /* 2742 */ 'v', 'f', 'c', 'h', 'e', 9, 0, + /* 2749 */ 'l', 'o', 'c', 'h', 'e', 9, 0, + /* 2756 */ 's', 't', 'o', 'c', 'h', 'e', 9, 0, + /* 2764 */ 'l', 'o', 'c', 'f', 'h', 'e', 9, 0, + /* 2772 */ 's', 't', 'o', 'c', 'f', 'h', 'e', 9, 0, + /* 2781 */ 'l', 'o', 'c', 'g', 'h', 'e', 9, 0, + /* 2789 */ 's', 't', 'o', 'c', 'g', 'h', 'e', 9, 0, + /* 2798 */ 'j', 'g', 'h', 'e', 9, 0, + /* 2804 */ 'l', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, + /* 2813 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, + /* 2823 */ 'b', 'i', 'h', 'e', 9, 0, + /* 2829 */ 'l', 'o', 'c', 'h', 'i', 'h', 'e', 9, 0, + /* 2838 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 'e', 9, 0, + /* 2848 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 'e', 9, 0, + /* 2858 */ 'c', 'i', 'j', 'h', 'e', 9, 0, + /* 2865 */ 'c', 'g', 'i', 'j', 'h', 'e', 9, 0, + /* 2873 */ 'c', 'l', 'g', 'i', 'j', 'h', 'e', 9, 0, + /* 2882 */ 'c', 'l', 'i', 'j', 'h', 'e', 9, 0, + /* 2890 */ 'c', 'r', 'j', 'h', 'e', 9, 0, + /* 2897 */ 'c', 'g', 'r', 'j', 'h', 'e', 9, 0, + /* 2905 */ 'c', 'l', 'g', 'r', 'j', 'h', 'e', 9, 0, + /* 2914 */ 'c', 'l', 'r', 'j', 'h', 'e', 9, 0, + /* 2922 */ 'c', 'i', 'b', 'n', 'h', 'e', 9, 0, + /* 2930 */ 'c', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, + /* 2939 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, + /* 2949 */ 'c', 'l', 'i', 'b', 'n', 'h', 'e', 9, 0, + /* 2958 */ 'c', 'r', 'b', 'n', 'h', 'e', 9, 0, + /* 2966 */ 'c', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, + /* 2975 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, + /* 2985 */ 'c', 'l', 'r', 'b', 'n', 'h', 'e', 9, 0, + /* 2994 */ 'l', 'o', 'c', 'n', 'h', 'e', 9, 0, + /* 3002 */ 's', 't', 'o', 'c', 'n', 'h', 'e', 9, 0, + /* 3011 */ 'l', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, + /* 3020 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, + /* 3030 */ 'j', 'g', 'n', 'h', 'e', 9, 0, + /* 3037 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, + /* 3047 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, + /* 3058 */ 'b', 'i', 'n', 'h', 'e', 9, 0, + /* 3065 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 'e', 9, 0, + /* 3075 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 'e', 9, 0, + /* 3086 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 'e', 9, 0, + /* 3097 */ 'c', 'i', 'j', 'n', 'h', 'e', 9, 0, + /* 3105 */ 'c', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, + /* 3114 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, + /* 3124 */ 'c', 'l', 'i', 'j', 'n', 'h', 'e', 9, 0, + /* 3133 */ 'c', 'r', 'j', 'n', 'h', 'e', 9, 0, + /* 3141 */ 'c', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, + /* 3150 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, + /* 3160 */ 'c', 'l', 'r', 'j', 'n', 'h', 'e', 9, 0, + /* 3169 */ 'l', 'o', 'c', 'r', 'n', 'h', 'e', 9, 0, + /* 3178 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 'e', 9, 0, + /* 3188 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 'e', 9, 0, + /* 3199 */ 'c', 'l', 'g', 't', 'n', 'h', 'e', 9, 0, + /* 3208 */ 'c', 'i', 't', 'n', 'h', 'e', 9, 0, + /* 3216 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 'e', 9, 0, + /* 3226 */ 'c', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, + /* 3235 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, + /* 3245 */ 'c', 'l', 't', 'n', 'h', 'e', 9, 0, + /* 3253 */ 'c', 'r', 't', 'n', 'h', 'e', 9, 0, + /* 3261 */ 'c', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, + /* 3270 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, + /* 3280 */ 'c', 'l', 'r', 't', 'n', 'h', 'e', 9, 0, + /* 3289 */ 'l', 'o', 'c', 'r', 'h', 'e', 9, 0, + /* 3297 */ 'l', 'o', 'c', 'g', 'r', 'h', 'e', 9, 0, + /* 3306 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 'e', 9, 0, + /* 3316 */ 'c', 'l', 'g', 't', 'h', 'e', 9, 0, + /* 3324 */ 'c', 'i', 't', 'h', 'e', 9, 0, + /* 3331 */ 'c', 'l', 'f', 'i', 't', 'h', 'e', 9, 0, + /* 3340 */ 'c', 'g', 'i', 't', 'h', 'e', 9, 0, + /* 3348 */ 'c', 'l', 'g', 'i', 't', 'h', 'e', 9, 0, + /* 3357 */ 'c', 'l', 't', 'h', 'e', 9, 0, + /* 3364 */ 'c', 'r', 't', 'h', 'e', 9, 0, + /* 3371 */ 'c', 'g', 'r', 't', 'h', 'e', 9, 0, + /* 3379 */ 'c', 'l', 'g', 'r', 't', 'h', 'e', 9, 0, + /* 3388 */ 'c', 'l', 'r', 't', 'h', 'e', 9, 0, + /* 3396 */ 'b', 'i', 'e', 9, 0, + /* 3401 */ 'l', 'o', 'c', 'h', 'i', 'e', 9, 0, + /* 3409 */ 'l', 'o', 'c', 'g', 'h', 'i', 'e', 9, 0, + /* 3418 */ 'l', 'o', 'c', 'h', 'h', 'i', 'e', 9, 0, + /* 3427 */ 's', 'i', 'e', 9, 0, + /* 3432 */ 'c', 'i', 'j', 'e', 9, 0, + /* 3438 */ 'c', 'g', 'i', 'j', 'e', 9, 0, + /* 3445 */ 'c', 'l', 'g', 'i', 'j', 'e', 9, 0, + /* 3453 */ 'c', 'l', 'i', 'j', 'e', 9, 0, + /* 3460 */ 'c', 'r', 'j', 'e', 9, 0, + /* 3466 */ 'c', 'g', 'r', 'j', 'e', 9, 0, + /* 3473 */ 'c', 'l', 'g', 'r', 'j', 'e', 9, 0, + /* 3481 */ 'c', 'l', 'r', 'j', 'e', 9, 0, + /* 3488 */ 's', 't', 'c', 'k', 'e', 9, 0, + /* 3495 */ 'i', 's', 'k', 'e', 9, 0, + /* 3501 */ 's', 's', 'k', 'e', 9, 0, + /* 3507 */ 'v', 'm', 'a', 'l', 'e', 9, 0, + /* 3514 */ 'c', 'i', 'b', 'l', 'e', 9, 0, + /* 3521 */ 'c', 'g', 'i', 'b', 'l', 'e', 9, 0, + /* 3529 */ 'c', 'l', 'g', 'i', 'b', 'l', 'e', 9, 0, + /* 3538 */ 'c', 'l', 'i', 'b', 'l', 'e', 9, 0, + /* 3546 */ 'c', 'r', 'b', 'l', 'e', 9, 0, + /* 3553 */ 'c', 'g', 'r', 'b', 'l', 'e', 9, 0, + /* 3561 */ 'c', 'l', 'g', 'r', 'b', 'l', 'e', 9, 0, + /* 3570 */ 'c', 'l', 'r', 'b', 'l', 'e', 9, 0, + /* 3578 */ 'c', 'l', 'c', 'l', 'e', 9, 0, + /* 3585 */ 'l', 'o', 'c', 'l', 'e', 9, 0, + /* 3592 */ 's', 't', 'o', 'c', 'l', 'e', 9, 0, + /* 3600 */ 'm', 'v', 'c', 'l', 'e', 9, 0, + /* 3607 */ 's', 't', 'f', 'l', 'e', 9, 0, + /* 3614 */ 'l', 'o', 'c', 'g', 'l', 'e', 9, 0, + /* 3622 */ 's', 't', 'o', 'c', 'g', 'l', 'e', 9, 0, + /* 3631 */ 'j', 'g', 'l', 'e', 9, 0, + /* 3637 */ 'l', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, + /* 3646 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, + /* 3656 */ 'b', 'i', 'l', 'e', 9, 0, + /* 3662 */ 'l', 'o', 'c', 'h', 'i', 'l', 'e', 9, 0, + /* 3671 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'e', 9, 0, + /* 3681 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'e', 9, 0, + /* 3691 */ 'c', 'i', 'j', 'l', 'e', 9, 0, + /* 3698 */ 'c', 'g', 'i', 'j', 'l', 'e', 9, 0, + /* 3706 */ 'c', 'l', 'g', 'i', 'j', 'l', 'e', 9, 0, + /* 3715 */ 'c', 'l', 'i', 'j', 'l', 'e', 9, 0, + /* 3723 */ 'c', 'r', 'j', 'l', 'e', 9, 0, + /* 3730 */ 'c', 'g', 'r', 'j', 'l', 'e', 9, 0, + /* 3738 */ 'c', 'l', 'g', 'r', 'j', 'l', 'e', 9, 0, + /* 3747 */ 'c', 'l', 'r', 'j', 'l', 'e', 9, 0, + /* 3755 */ 'v', 'm', 'l', 'e', 9, 0, + /* 3761 */ 'c', 'i', 'b', 'n', 'l', 'e', 9, 0, + /* 3769 */ 'c', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, + /* 3778 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, + /* 3788 */ 'c', 'l', 'i', 'b', 'n', 'l', 'e', 9, 0, + /* 3797 */ 'c', 'r', 'b', 'n', 'l', 'e', 9, 0, + /* 3805 */ 'c', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, + /* 3814 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, + /* 3824 */ 'c', 'l', 'r', 'b', 'n', 'l', 'e', 9, 0, + /* 3833 */ 'l', 'o', 'c', 'n', 'l', 'e', 9, 0, + /* 3841 */ 's', 't', 'o', 'c', 'n', 'l', 'e', 9, 0, + /* 3850 */ 'l', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, + /* 3859 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, + /* 3869 */ 'j', 'g', 'n', 'l', 'e', 9, 0, + /* 3876 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, + /* 3886 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, + /* 3897 */ 'b', 'i', 'n', 'l', 'e', 9, 0, + /* 3904 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'e', 9, 0, + /* 3914 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'e', 9, 0, + /* 3925 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'e', 9, 0, + /* 3936 */ 'c', 'i', 'j', 'n', 'l', 'e', 9, 0, + /* 3944 */ 'c', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, + /* 3953 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, + /* 3963 */ 'c', 'l', 'i', 'j', 'n', 'l', 'e', 9, 0, + /* 3972 */ 'c', 'r', 'j', 'n', 'l', 'e', 9, 0, + /* 3980 */ 'c', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, + /* 3989 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, + /* 3999 */ 'c', 'l', 'r', 'j', 'n', 'l', 'e', 9, 0, + /* 4008 */ 'l', 'o', 'c', 'r', 'n', 'l', 'e', 9, 0, + /* 4017 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'e', 9, 0, + /* 4027 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'e', 9, 0, + /* 4038 */ 'c', 'l', 'g', 't', 'n', 'l', 'e', 9, 0, + /* 4047 */ 'c', 'i', 't', 'n', 'l', 'e', 9, 0, + /* 4055 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'e', 9, 0, + /* 4065 */ 'c', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, + /* 4074 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, + /* 4084 */ 'c', 'l', 't', 'n', 'l', 'e', 9, 0, + /* 4092 */ 'c', 'r', 't', 'n', 'l', 'e', 9, 0, + /* 4100 */ 'c', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, + /* 4109 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, + /* 4119 */ 'c', 'l', 'r', 't', 'n', 'l', 'e', 9, 0, + /* 4128 */ 'l', 'o', 'c', 'r', 'l', 'e', 9, 0, + /* 4136 */ 'l', 'o', 'c', 'g', 'r', 'l', 'e', 9, 0, + /* 4145 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'e', 9, 0, + /* 4155 */ 'c', 'l', 'g', 't', 'l', 'e', 9, 0, + /* 4163 */ 'c', 'i', 't', 'l', 'e', 9, 0, + /* 4170 */ 'c', 'l', 'f', 'i', 't', 'l', 'e', 9, 0, + /* 4179 */ 'c', 'g', 'i', 't', 'l', 'e', 9, 0, + /* 4187 */ 'c', 'l', 'g', 'i', 't', 'l', 'e', 9, 0, + /* 4196 */ 'c', 'l', 't', 'l', 'e', 9, 0, + /* 4203 */ 'c', 'r', 't', 'l', 'e', 9, 0, + /* 4210 */ 'c', 'g', 'r', 't', 'l', 'e', 9, 0, + /* 4218 */ 'c', 'l', 'g', 'r', 't', 'l', 'e', 9, 0, + /* 4227 */ 'c', 'l', 'r', 't', 'l', 'e', 9, 0, + /* 4235 */ 'b', 'x', 'l', 'e', 9, 0, + /* 4241 */ 'b', 'r', 'x', 'l', 'e', 9, 0, + /* 4248 */ 'v', 'm', 'e', 9, 0, + /* 4253 */ 'c', 'i', 'b', 'n', 'e', 9, 0, + /* 4260 */ 'c', 'g', 'i', 'b', 'n', 'e', 9, 0, + /* 4268 */ 'c', 'l', 'g', 'i', 'b', 'n', 'e', 9, 0, + /* 4277 */ 'c', 'l', 'i', 'b', 'n', 'e', 9, 0, + /* 4285 */ 'c', 'r', 'b', 'n', 'e', 9, 0, + /* 4292 */ 'c', 'g', 'r', 'b', 'n', 'e', 9, 0, + /* 4300 */ 'c', 'l', 'g', 'r', 'b', 'n', 'e', 9, 0, + /* 4309 */ 'c', 'l', 'r', 'b', 'n', 'e', 9, 0, + /* 4317 */ 'l', 'o', 'c', 'n', 'e', 9, 0, + /* 4324 */ 's', 't', 'o', 'c', 'n', 'e', 9, 0, + /* 4332 */ 'v', 'f', 'e', 'n', 'e', 9, 0, + /* 4339 */ 'l', 'o', 'c', 'g', 'n', 'e', 9, 0, + /* 4347 */ 's', 't', 'o', 'c', 'g', 'n', 'e', 9, 0, + /* 4356 */ 'j', 'g', 'n', 'e', 9, 0, + /* 4362 */ 'l', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, + /* 4371 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, + /* 4381 */ 'b', 'i', 'n', 'e', 9, 0, + /* 4387 */ 'l', 'o', 'c', 'h', 'i', 'n', 'e', 9, 0, + /* 4396 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'e', 9, 0, + /* 4406 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'e', 9, 0, + /* 4416 */ 'c', 'i', 'j', 'n', 'e', 9, 0, + /* 4423 */ 'c', 'g', 'i', 'j', 'n', 'e', 9, 0, + /* 4431 */ 'c', 'l', 'g', 'i', 'j', 'n', 'e', 9, 0, + /* 4440 */ 'c', 'l', 'i', 'j', 'n', 'e', 9, 0, + /* 4448 */ 'c', 'r', 'j', 'n', 'e', 9, 0, + /* 4455 */ 'c', 'g', 'r', 'j', 'n', 'e', 9, 0, + /* 4463 */ 'c', 'l', 'g', 'r', 'j', 'n', 'e', 9, 0, + /* 4472 */ 'c', 'l', 'r', 'j', 'n', 'e', 9, 0, + /* 4480 */ 'v', 'o', 'n', 'e', 9, 0, + /* 4486 */ 'l', 'o', 'c', 'r', 'n', 'e', 9, 0, + /* 4494 */ 'l', 'o', 'c', 'g', 'r', 'n', 'e', 9, 0, + /* 4503 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'e', 9, 0, + /* 4513 */ 'c', 'l', 'g', 't', 'n', 'e', 9, 0, + /* 4521 */ 'c', 'i', 't', 'n', 'e', 9, 0, + /* 4528 */ 'c', 'l', 'f', 'i', 't', 'n', 'e', 9, 0, + /* 4537 */ 'c', 'g', 'i', 't', 'n', 'e', 9, 0, + /* 4545 */ 'c', 'l', 'g', 'i', 't', 'n', 'e', 9, 0, + /* 4554 */ 'c', 'l', 't', 'n', 'e', 9, 0, + /* 4561 */ 'c', 'r', 't', 'n', 'e', 9, 0, + /* 4568 */ 'c', 'g', 'r', 't', 'n', 'e', 9, 0, + /* 4576 */ 'c', 'l', 'g', 'r', 't', 'n', 'e', 9, 0, + /* 4585 */ 'c', 'l', 'r', 't', 'n', 'e', 9, 0, + /* 4593 */ 's', 'q', 'e', 9, 0, + /* 4598 */ 'l', 'o', 'c', 'r', 'e', 9, 0, + /* 4605 */ 'l', 'o', 'c', 'g', 'r', 'e', 9, 0, + /* 4613 */ 'l', 'o', 'c', 'f', 'h', 'r', 'e', 9, 0, + /* 4622 */ 't', 'r', 't', 'r', 'e', 9, 0, + /* 4629 */ 'm', 's', 'e', 9, 0, + /* 4634 */ 'c', 'u', 's', 'e', 9, 0, + /* 4640 */ 'i', 'd', 't', 'e', 9, 0, + /* 4646 */ 'c', 'r', 'd', 't', 'e', 9, 0, + /* 4653 */ 'c', 'l', 'g', 't', 'e', 9, 0, + /* 4660 */ 'c', 'i', 't', 'e', 9, 0, + /* 4666 */ 'c', 'l', 'f', 'i', 't', 'e', 9, 0, + /* 4674 */ 'c', 'g', 'i', 't', 'e', 9, 0, + /* 4681 */ 'c', 'l', 'g', 'i', 't', 'e', 9, 0, + /* 4689 */ 'c', 'l', 't', 'e', 9, 0, + /* 4695 */ 'i', 'p', 't', 'e', 9, 0, + /* 4701 */ 'c', 'r', 't', 'e', 9, 0, + /* 4707 */ 'c', 'g', 'r', 't', 'e', 9, 0, + /* 4714 */ 'c', 'l', 'g', 'r', 't', 'e', 9, 0, + /* 4722 */ 'c', 'l', 'r', 't', 'e', 9, 0, + /* 4729 */ 't', 'r', 't', 'e', 9, 0, + /* 4735 */ 's', 't', 'e', 9, 0, + /* 4740 */ 'l', 'p', 's', 'w', 'e', 9, 0, + /* 4747 */ 'l', 'x', 'e', 9, 0, + /* 4752 */ 'v', 'g', 'f', 'm', 'a', 'f', 9, 0, + /* 4760 */ 'v', 'e', 's', 'r', 'a', 'f', 9, 0, + /* 4768 */ 'v', 'a', 'f', 9, 0, + /* 4773 */ 's', 'a', 'c', 'f', 9, 0, + /* 4779 */ 'v', 'a', 'c', 'c', 'f', 9, 0, + /* 4786 */ 'v', 'e', 'c', 'f', 9, 0, + /* 4792 */ 'v', 'l', 'c', 'f', 9, 0, + /* 4798 */ 'v', 's', 't', 'r', 'c', 'f', 9, 0, + /* 4806 */ 'v', 'f', 'a', 'e', 'f', 9, 0, + /* 4813 */ 'v', 'm', 'a', 'e', 'f', 9, 0, + /* 4820 */ 'v', 's', 'c', 'e', 'f', 9, 0, + /* 4827 */ 'v', 'f', 'e', 'e', 'f', 9, 0, + /* 4834 */ 'v', 'g', 'e', 'f', 9, 0, + /* 4840 */ 'v', 'm', 'a', 'l', 'e', 'f', 9, 0, + /* 4848 */ 'v', 'm', 'l', 'e', 'f', 9, 0, + /* 4855 */ 'v', 'l', 'e', 'f', 9, 0, + /* 4861 */ 'v', 'm', 'e', 'f', 9, 0, + /* 4867 */ 'v', 'f', 'e', 'n', 'e', 'f', 9, 0, + /* 4875 */ 'v', 's', 't', 'e', 'f', 9, 0, + /* 4882 */ 'a', 'g', 'f', 9, 0, + /* 4887 */ 'c', 'g', 'f', 9, 0, + /* 4892 */ 'v', 's', 'e', 'g', 'f', 9, 0, + /* 4899 */ 'a', 'l', 'g', 'f', 9, 0, + /* 4905 */ 'c', 'l', 'g', 'f', 9, 0, + /* 4911 */ 'l', 'l', 'g', 'f', 9, 0, + /* 4917 */ 's', 'l', 'g', 'f', 9, 0, + /* 4923 */ 'v', 's', 'u', 'm', 'g', 'f', 9, 0, + /* 4931 */ 'l', 'l', 'z', 'r', 'g', 'f', 9, 0, + /* 4939 */ 'd', 's', 'g', 'f', 9, 0, + /* 4945 */ 'm', 's', 'g', 'f', 9, 0, + /* 4951 */ 'l', 't', 'g', 'f', 9, 0, + /* 4957 */ 'v', 'a', 'v', 'g', 'f', 9, 0, + /* 4964 */ 'v', 'l', 'v', 'g', 'f', 9, 0, + /* 4971 */ 'v', 'm', 'a', 'h', 'f', 9, 0, + /* 4978 */ 'v', 'c', 'h', 'f', 9, 0, + /* 4984 */ 'i', 'i', 'h', 'f', 9, 0, + /* 4990 */ 'l', 'l', 'i', 'h', 'f', 9, 0, + /* 4997 */ 'n', 'i', 'h', 'f', 9, 0, + /* 5003 */ 'o', 'i', 'h', 'f', 9, 0, + /* 5009 */ 'x', 'i', 'h', 'f', 9, 0, + /* 5015 */ 'v', 'm', 'a', 'l', 'h', 'f', 9, 0, + /* 5023 */ 'c', 'l', 'h', 'f', 9, 0, + /* 5029 */ 'v', 'm', 'l', 'h', 'f', 9, 0, + /* 5036 */ 'v', 'u', 'p', 'l', 'h', 'f', 9, 0, + /* 5044 */ 'v', 'm', 'h', 'f', 9, 0, + /* 5050 */ 'v', 'u', 'p', 'h', 'f', 9, 0, + /* 5057 */ 'v', 'm', 'r', 'h', 'f', 9, 0, + /* 5064 */ 'v', 's', 'c', 'b', 'i', 'f', 9, 0, + /* 5072 */ 'v', 'l', 'e', 'i', 'f', 9, 0, + /* 5079 */ 'v', 'r', 'e', 'p', 'i', 'f', 9, 0, + /* 5087 */ 's', 't', 'c', 'k', 'f', 9, 0, + /* 5094 */ 'v', 'p', 'k', 'f', 9, 0, + /* 5100 */ 'v', 'm', 'a', 'l', 'f', 9, 0, + /* 5107 */ 'v', 'e', 'c', 'l', 'f', 9, 0, + /* 5114 */ 'v', 'a', 'v', 'g', 'l', 'f', 9, 0, + /* 5122 */ 'v', 'c', 'h', 'l', 'f', 9, 0, + /* 5129 */ 'i', 'i', 'l', 'f', 9, 0, + /* 5135 */ 'l', 'l', 'i', 'l', 'f', 9, 0, + /* 5142 */ 'n', 'i', 'l', 'f', 9, 0, + /* 5148 */ 'o', 'i', 'l', 'f', 9, 0, + /* 5154 */ 'x', 'i', 'l', 'f', 9, 0, + /* 5160 */ 'v', 'u', 'p', 'l', 'l', 'f', 9, 0, + /* 5168 */ 'v', 'e', 'r', 'l', 'l', 'f', 9, 0, + /* 5176 */ 'v', 'm', 'l', 'f', 9, 0, + /* 5182 */ 'v', 'm', 'n', 'l', 'f', 9, 0, + /* 5189 */ 'v', 'u', 'p', 'l', 'f', 9, 0, + /* 5196 */ 'v', 'm', 'r', 'l', 'f', 9, 0, + /* 5203 */ 'v', 'e', 's', 'r', 'l', 'f', 9, 0, + /* 5211 */ 'v', 'e', 's', 'l', 'f', 9, 0, + /* 5218 */ 'v', 'm', 'x', 'l', 'f', 9, 0, + /* 5225 */ 'v', 'l', 'l', 'e', 'z', 'l', 'f', 9, 0, + /* 5234 */ 'v', 'g', 'f', 'm', 'f', 9, 0, + /* 5241 */ 'p', 'f', 'm', 'f', 9, 0, + /* 5247 */ 'v', 'g', 'm', 'f', 9, 0, + /* 5253 */ 'v', 'e', 'r', 'i', 'm', 'f', 9, 0, + /* 5261 */ 'k', 'm', 'f', 9, 0, + /* 5266 */ 'v', 'm', 'n', 'f', 9, 0, + /* 5272 */ 'v', 'm', 'a', 'o', 'f', 9, 0, + /* 5279 */ 'v', 'm', 'a', 'l', 'o', 'f', 9, 0, + /* 5287 */ 'v', 'm', 'l', 'o', 'f', 9, 0, + /* 5294 */ 'v', 'm', 'o', 'f', 9, 0, + /* 5300 */ 'v', 'l', 'r', 'e', 'p', 'f', 9, 0, + /* 5308 */ 'v', 'r', 'e', 'p', 'f', 9, 0, + /* 5315 */ 'v', 'l', 'p', 'f', 9, 0, + /* 5321 */ 'v', 'c', 'e', 'q', 'f', 9, 0, + /* 5328 */ 'v', 's', 'u', 'm', 'q', 'f', 9, 0, + /* 5336 */ 'v', 'i', 's', 't', 'r', 'f', 9, 0, + /* 5344 */ 'l', 'z', 'r', 'f', 9, 0, + /* 5350 */ 'v', 'p', 'k', 's', 'f', 9, 0, + /* 5357 */ 'v', 'p', 'k', 'l', 's', 'f', 9, 0, + /* 5365 */ 'v', 's', 'f', 9, 0, + /* 5370 */ 'v', 'p', 'o', 'p', 'c', 't', 'f', 9, 0, + /* 5379 */ 'p', 't', 'f', 9, 0, + /* 5384 */ 'c', 'u', 'u', 't', 'f', 9, 0, + /* 5391 */ 'v', 'e', 's', 'r', 'a', 'v', 'f', 9, 0, + /* 5400 */ 'v', 'l', 'g', 'v', 'f', 9, 0, + /* 5407 */ 'v', 'e', 'r', 'l', 'l', 'v', 'f', 9, 0, + /* 5416 */ 'v', 'e', 's', 'r', 'l', 'v', 'f', 9, 0, + /* 5425 */ 'v', 'e', 's', 'l', 'v', 'f', 9, 0, + /* 5433 */ 'v', 'm', 'x', 'f', 9, 0, + /* 5439 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 9, 0, + /* 5448 */ 'v', 'f', 'a', 'e', 'z', 'f', 9, 0, + /* 5456 */ 'v', 'f', 'e', 'e', 'z', 'f', 9, 0, + /* 5464 */ 'v', 'l', 'l', 'e', 'z', 'f', 9, 0, + /* 5472 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 9, 0, + /* 5481 */ 'v', 'c', 'l', 'z', 'f', 9, 0, + /* 5488 */ 'v', 'c', 't', 'z', 'f', 9, 0, + /* 5495 */ 'l', 'a', 'a', 'g', 9, 0, + /* 5501 */ 'e', 'c', 'a', 'g', 9, 0, + /* 5507 */ 'd', 'i', 'a', 'g', 9, 0, + /* 5513 */ 's', 'l', 'a', 'g', 9, 0, + /* 5519 */ 'v', 'g', 'f', 'm', 'a', 'g', 9, 0, + /* 5527 */ 'l', 'r', 'a', 'g', 9, 0, + /* 5533 */ 'v', 'e', 's', 'r', 'a', 'g', 9, 0, + /* 5541 */ 's', 't', 'r', 'a', 'g', 9, 0, + /* 5548 */ 'l', 'u', 'r', 'a', 'g', 9, 0, + /* 5555 */ 'v', 'a', 'g', 9, 0, + /* 5560 */ 's', 'l', 'b', 'g', 9, 0, + /* 5566 */ 'r', 'i', 's', 'b', 'g', 9, 0, + /* 5573 */ 'r', 'n', 's', 'b', 'g', 9, 0, + /* 5580 */ 'r', 'o', 's', 'b', 'g', 9, 0, + /* 5587 */ 'r', 'x', 's', 'b', 'g', 9, 0, + /* 5594 */ 'v', 'c', 'v', 'b', 'g', 9, 0, + /* 5601 */ 't', 'r', 'a', 'c', 'g', 9, 0, + /* 5608 */ 'v', 'a', 'c', 'c', 'g', 9, 0, + /* 5615 */ 'v', 'e', 'c', 'g', 9, 0, + /* 5621 */ 'a', 'l', 'c', 'g', 9, 0, + /* 5627 */ 'v', 'l', 'c', 'g', 9, 0, + /* 5633 */ 'l', 'o', 'c', 'g', 9, 0, + /* 5639 */ 's', 't', 'o', 'c', 'g', 9, 0, + /* 5646 */ 'v', 'c', 'd', 'g', 9, 0, + /* 5652 */ 'l', 'p', 'd', 'g', 9, 0, + /* 5658 */ 'v', 'c', 'v', 'd', 'g', 9, 0, + /* 5665 */ 'v', 's', 'c', 'e', 'g', 9, 0, + /* 5672 */ 'v', 'g', 'e', 'g', 9, 0, + /* 5678 */ 'v', 'l', 'e', 'g', 9, 0, + /* 5684 */ 'b', 'x', 'l', 'e', 'g', 9, 0, + /* 5691 */ 'e', 'r', 'e', 'g', 9, 0, + /* 5697 */ 'v', 's', 'e', 'g', 9, 0, + /* 5703 */ 'v', 's', 't', 'e', 'g', 9, 0, + /* 5710 */ 'e', 'r', 'e', 'g', 'g', 9, 0, + /* 5717 */ 'l', 'g', 'g', 9, 0, + /* 5722 */ 'v', 'a', 'v', 'g', 'g', 9, 0, + /* 5729 */ 'v', 'l', 'v', 'g', 'g', 9, 0, + /* 5736 */ 'r', 'i', 's', 'b', 'h', 'g', 9, 0, + /* 5744 */ 'v', 'c', 'h', 'g', 9, 0, + /* 5750 */ 'v', 'm', 'r', 'h', 'g', 9, 0, + /* 5757 */ 'b', 'x', 'h', 'g', 9, 0, + /* 5763 */ 'b', 'r', 'x', 'h', 'g', 9, 0, + /* 5770 */ 'v', 's', 'c', 'b', 'i', 'g', 9, 0, + /* 5778 */ 'v', 'l', 'e', 'i', 'g', 9, 0, + /* 5785 */ 'v', 'r', 'e', 'p', 'i', 'g', 9, 0, + /* 5793 */ 'j', 'g', 9, 0, + /* 5797 */ 'v', 'p', 'k', 'g', 9, 0, + /* 5803 */ 'l', 'a', 'a', 'l', 'g', 9, 0, + /* 5810 */ 'r', 'i', 's', 'b', 'l', 'g', 9, 0, + /* 5818 */ 'v', 'e', 'c', 'l', 'g', 9, 0, + /* 5825 */ 'v', 'c', 'd', 'l', 'g', 9, 0, + /* 5832 */ 'v', 'a', 'v', 'g', 'l', 'g', 9, 0, + /* 5840 */ 'v', 'c', 'h', 'l', 'g', 9, 0, + /* 5847 */ 'v', 'e', 'r', 'l', 'l', 'g', 9, 0, + /* 5855 */ 's', 'l', 'l', 'g', 9, 0, + /* 5861 */ 'm', 'l', 'g', 9, 0, + /* 5866 */ 'v', 'm', 'n', 'l', 'g', 9, 0, + /* 5873 */ 'v', 'm', 'r', 'l', 'g', 9, 0, + /* 5880 */ 'v', 'e', 's', 'r', 'l', 'g', 9, 0, + /* 5888 */ 'v', 'e', 's', 'l', 'g', 9, 0, + /* 5895 */ 'v', 'm', 's', 'l', 'g', 9, 0, + /* 5902 */ 'l', 'c', 't', 'l', 'g', 9, 0, + /* 5909 */ 'v', 'm', 'x', 'l', 'g', 9, 0, + /* 5916 */ 'b', 'r', 'x', 'l', 'g', 9, 0, + /* 5923 */ 'v', 'g', 'f', 'm', 'g', 9, 0, + /* 5930 */ 'v', 'g', 'm', 'g', 9, 0, + /* 5936 */ 'v', 'e', 'r', 'i', 'm', 'g', 9, 0, + /* 5944 */ 'l', 'm', 'g', 9, 0, + /* 5949 */ 's', 't', 'm', 'g', 9, 0, + /* 5955 */ 'v', 's', 'u', 'm', 'g', 9, 0, + /* 5962 */ 'l', 'a', 'n', 'g', 9, 0, + /* 5968 */ 'v', 'm', 'n', 'g', 9, 0, + /* 5974 */ 'l', 'a', 'o', 'g', 9, 0, + /* 5980 */ 'v', 'l', 'r', 'e', 'p', 'g', 9, 0, + /* 5988 */ 'v', 'r', 'e', 'p', 'g', 9, 0, + /* 5995 */ 'v', 'l', 'p', 'g', 9, 0, + /* 6001 */ 'c', 's', 'p', 'g', 9, 0, + /* 6007 */ 'm', 'v', 'p', 'g', 9, 0, + /* 6013 */ 'v', 'c', 'e', 'q', 'g', 9, 0, + /* 6020 */ 'v', 's', 'u', 'm', 'q', 'g', 9, 0, + /* 6028 */ 's', 't', 'u', 'r', 'g', 9, 0, + /* 6035 */ 'l', 'z', 'r', 'g', 9, 0, + /* 6041 */ 'b', 's', 'g', 9, 0, + /* 6046 */ 'c', 's', 'g', 9, 0, + /* 6051 */ 'c', 'd', 's', 'g', 9, 0, + /* 6057 */ 'l', 'l', 'g', 'f', 's', 'g', 9, 0, + /* 6065 */ 'v', 'p', 'k', 's', 'g', 9, 0, + /* 6072 */ 'v', 'p', 'k', 'l', 's', 'g', 9, 0, + /* 6080 */ 'm', 's', 'g', 9, 0, + /* 6085 */ 'v', 's', 'g', 9, 0, + /* 6090 */ 'b', 'c', 't', 'g', 9, 0, + /* 6096 */ 'e', 'c', 't', 'g', 9, 0, + /* 6102 */ 'v', 'p', 'o', 'p', 'c', 't', 'g', 9, 0, + /* 6111 */ 'b', 'r', 'c', 't', 'g', 9, 0, + /* 6118 */ 's', 't', 'c', 't', 'g', 9, 0, + /* 6125 */ 'l', 't', 'g', 9, 0, + /* 6130 */ 'n', 't', 's', 't', 'g', 9, 0, + /* 6137 */ 'v', 'e', 's', 'r', 'a', 'v', 'g', 9, 0, + /* 6146 */ 'v', 'a', 'v', 'g', 9, 0, + /* 6152 */ 'v', 'l', 'g', 'v', 'g', 9, 0, + /* 6159 */ 'v', 'e', 'r', 'l', 'l', 'v', 'g', 9, 0, + /* 6168 */ 'v', 'e', 's', 'r', 'l', 'v', 'g', 9, 0, + /* 6177 */ 'v', 'e', 's', 'l', 'v', 'g', 9, 0, + /* 6185 */ 'v', 'l', 'v', 'g', 9, 0, + /* 6191 */ 'l', 'r', 'v', 'g', 9, 0, + /* 6197 */ 's', 't', 'r', 'v', 'g', 9, 0, + /* 6204 */ 'l', 'a', 'x', 'g', 9, 0, + /* 6210 */ 'v', 'm', 'x', 'g', 9, 0, + /* 6216 */ 'v', 'l', 'l', 'e', 'z', 'g', 9, 0, + /* 6224 */ 'v', 'c', 'l', 'z', 'g', 9, 0, + /* 6231 */ 'v', 'c', 't', 'z', 'g', 9, 0, + /* 6238 */ 'v', 'g', 'f', 'm', 'a', 'h', 9, 0, + /* 6246 */ 'v', 'm', 'a', 'h', 9, 0, + /* 6252 */ 'v', 'e', 's', 'r', 'a', 'h', 9, 0, + /* 6260 */ 'v', 'a', 'h', 9, 0, + /* 6265 */ 'c', 'i', 'b', 'h', 9, 0, + /* 6271 */ 'c', 'g', 'i', 'b', 'h', 9, 0, + /* 6278 */ 'c', 'l', 'g', 'i', 'b', 'h', 9, 0, + /* 6286 */ 'c', 'l', 'i', 'b', 'h', 9, 0, + /* 6293 */ 'l', 'b', 'h', 9, 0, + /* 6298 */ 'c', 'r', 'b', 'h', 9, 0, + /* 6304 */ 'c', 'g', 'r', 'b', 'h', 9, 0, + /* 6311 */ 'c', 'l', 'g', 'r', 'b', 'h', 9, 0, + /* 6319 */ 'c', 'l', 'r', 'b', 'h', 9, 0, + /* 6326 */ 'v', 'a', 'c', 'c', 'h', 9, 0, + /* 6333 */ 'v', 'e', 'c', 'h', 9, 0, + /* 6339 */ 'v', 'f', 'c', 'h', 9, 0, + /* 6345 */ 'l', 'l', 'c', 'h', 9, 0, + /* 6351 */ 'v', 'l', 'c', 'h', 9, 0, + /* 6357 */ 'l', 'o', 'c', 'h', 9, 0, + /* 6363 */ 's', 't', 'o', 'c', 'h', 9, 0, + /* 6370 */ 'v', 's', 't', 'r', 'c', 'h', 9, 0, + /* 6378 */ 'm', 's', 'c', 'h', 9, 0, + /* 6384 */ 's', 's', 'c', 'h', 9, 0, + /* 6390 */ 's', 't', 's', 'c', 'h', 9, 0, + /* 6397 */ 's', 't', 'c', 'h', 9, 0, + /* 6403 */ 'v', 'c', 'h', 9, 0, + /* 6408 */ 'v', 'f', 'a', 'e', 'h', 9, 0, + /* 6415 */ 'v', 'm', 'a', 'e', 'h', 9, 0, + /* 6422 */ 'v', 'f', 'e', 'e', 'h', 9, 0, + /* 6429 */ 'v', 'm', 'a', 'l', 'e', 'h', 9, 0, + /* 6437 */ 'v', 'm', 'l', 'e', 'h', 9, 0, + /* 6444 */ 'v', 'l', 'e', 'h', 9, 0, + /* 6450 */ 'v', 'm', 'e', 'h', 9, 0, + /* 6456 */ 'v', 'f', 'e', 'n', 'e', 'h', 9, 0, + /* 6464 */ 'v', 's', 't', 'e', 'h', 9, 0, + /* 6471 */ 'l', 'o', 'c', 'f', 'h', 9, 0, + /* 6478 */ 's', 't', 'o', 'c', 'f', 'h', 9, 0, + /* 6486 */ 'l', 'f', 'h', 9, 0, + /* 6491 */ 's', 't', 'f', 'h', 9, 0, + /* 6497 */ 'a', 'g', 'h', 9, 0, + /* 6502 */ 'l', 'o', 'c', 'g', 'h', 9, 0, + /* 6509 */ 's', 't', 'o', 'c', 'g', 'h', 9, 0, + /* 6517 */ 'v', 's', 'e', 'g', 'h', 9, 0, + /* 6524 */ 'j', 'g', 'h', 9, 0, + /* 6529 */ 'l', 'l', 'g', 'h', 9, 0, + /* 6535 */ 'v', 's', 'u', 'm', 'g', 'h', 9, 0, + /* 6543 */ 's', 'g', 'h', 9, 0, + /* 6548 */ 'v', 'a', 'v', 'g', 'h', 9, 0, + /* 6555 */ 'v', 'l', 'v', 'g', 'h', 9, 0, + /* 6562 */ 'v', 'm', 'a', 'h', 'h', 9, 0, + /* 6569 */ 'v', 'c', 'h', 'h', 9, 0, + /* 6575 */ 'l', 'o', 'c', 'f', 'h', 'h', 9, 0, + /* 6583 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 9, 0, + /* 6592 */ 'i', 'i', 'h', 'h', 9, 0, + /* 6598 */ 'l', 'l', 'i', 'h', 'h', 9, 0, + /* 6605 */ 'n', 'i', 'h', 'h', 9, 0, + /* 6611 */ 'o', 'i', 'h', 'h', 9, 0, + /* 6617 */ 'v', 'm', 'a', 'l', 'h', 'h', 9, 0, + /* 6625 */ 'l', 'l', 'h', 'h', 9, 0, + /* 6631 */ 'v', 'm', 'l', 'h', 'h', 9, 0, + /* 6638 */ 'v', 'u', 'p', 'l', 'h', 'h', 9, 0, + /* 6646 */ 't', 'm', 'h', 'h', 9, 0, + /* 6652 */ 'v', 'm', 'h', 'h', 9, 0, + /* 6658 */ 'v', 'u', 'p', 'h', 'h', 9, 0, + /* 6665 */ 'v', 'm', 'r', 'h', 'h', 9, 0, + /* 6672 */ 's', 't', 'h', 'h', 9, 0, + /* 6678 */ 'a', 'i', 'h', 9, 0, + /* 6683 */ 'v', 's', 'c', 'b', 'i', 'h', 9, 0, + /* 6691 */ 'c', 'i', 'h', 9, 0, + /* 6696 */ 'v', 'l', 'e', 'i', 'h', 9, 0, + /* 6703 */ 'l', 'o', 'c', 'h', 'i', 'h', 9, 0, + /* 6711 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 9, 0, + /* 6720 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 9, 0, + /* 6729 */ 'c', 'l', 'i', 'h', 9, 0, + /* 6735 */ 'v', 'r', 'e', 'p', 'i', 'h', 9, 0, + /* 6743 */ 'a', 'l', 's', 'i', 'h', 9, 0, + /* 6750 */ 'c', 'i', 'j', 'h', 9, 0, + /* 6756 */ 'c', 'g', 'i', 'j', 'h', 9, 0, + /* 6763 */ 'c', 'l', 'g', 'i', 'j', 'h', 9, 0, + /* 6771 */ 'c', 'l', 'i', 'j', 'h', 9, 0, + /* 6778 */ 'c', 'r', 'j', 'h', 9, 0, + /* 6784 */ 'c', 'g', 'r', 'j', 'h', 9, 0, + /* 6791 */ 'c', 'l', 'g', 'r', 'j', 'h', 9, 0, + /* 6799 */ 'c', 'l', 'r', 'j', 'h', 9, 0, + /* 6806 */ 'v', 'p', 'k', 'h', 9, 0, + /* 6812 */ 'v', 'm', 'a', 'l', 'h', 9, 0, + /* 6819 */ 'c', 'i', 'b', 'l', 'h', 9, 0, + /* 6826 */ 'c', 'g', 'i', 'b', 'l', 'h', 9, 0, + /* 6834 */ 'c', 'l', 'g', 'i', 'b', 'l', 'h', 9, 0, + /* 6843 */ 'c', 'l', 'i', 'b', 'l', 'h', 9, 0, + /* 6851 */ 'c', 'r', 'b', 'l', 'h', 9, 0, + /* 6858 */ 'c', 'g', 'r', 'b', 'l', 'h', 9, 0, + /* 6866 */ 'c', 'l', 'g', 'r', 'b', 'l', 'h', 9, 0, + /* 6875 */ 'c', 'l', 'r', 'b', 'l', 'h', 9, 0, + /* 6883 */ 'v', 'e', 'c', 'l', 'h', 9, 0, + /* 6890 */ 'l', 'o', 'c', 'l', 'h', 9, 0, + /* 6897 */ 's', 't', 'o', 'c', 'l', 'h', 9, 0, + /* 6905 */ 'l', 'o', 'c', 'g', 'l', 'h', 9, 0, + /* 6913 */ 's', 't', 'o', 'c', 'g', 'l', 'h', 9, 0, + /* 6922 */ 'j', 'g', 'l', 'h', 9, 0, + /* 6928 */ 'v', 'a', 'v', 'g', 'l', 'h', 9, 0, + /* 6936 */ 'v', 'c', 'h', 'l', 'h', 9, 0, + /* 6943 */ 'l', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, + /* 6952 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, + /* 6962 */ 'b', 'i', 'l', 'h', 9, 0, + /* 6968 */ 'l', 'o', 'c', 'h', 'i', 'l', 'h', 9, 0, + /* 6977 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'h', 9, 0, + /* 6987 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'h', 9, 0, + /* 6997 */ 'i', 'i', 'l', 'h', 9, 0, + /* 7003 */ 'l', 'l', 'i', 'l', 'h', 9, 0, + /* 7010 */ 'n', 'i', 'l', 'h', 9, 0, + /* 7016 */ 'o', 'i', 'l', 'h', 9, 0, + /* 7022 */ 'c', 'i', 'j', 'l', 'h', 9, 0, + /* 7029 */ 'c', 'g', 'i', 'j', 'l', 'h', 9, 0, + /* 7037 */ 'c', 'l', 'g', 'i', 'j', 'l', 'h', 9, 0, + /* 7046 */ 'c', 'l', 'i', 'j', 'l', 'h', 9, 0, + /* 7054 */ 'c', 'r', 'j', 'l', 'h', 9, 0, + /* 7061 */ 'c', 'g', 'r', 'j', 'l', 'h', 9, 0, + /* 7069 */ 'c', 'l', 'g', 'r', 'j', 'l', 'h', 9, 0, + /* 7078 */ 'c', 'l', 'r', 'j', 'l', 'h', 9, 0, + /* 7086 */ 'v', 'u', 'p', 'l', 'l', 'h', 9, 0, + /* 7094 */ 'v', 'e', 'r', 'l', 'l', 'h', 9, 0, + /* 7102 */ 't', 'm', 'l', 'h', 9, 0, + /* 7108 */ 'v', 'm', 'l', 'h', 9, 0, + /* 7114 */ 'c', 'i', 'b', 'n', 'l', 'h', 9, 0, + /* 7122 */ 'c', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, + /* 7131 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, + /* 7141 */ 'c', 'l', 'i', 'b', 'n', 'l', 'h', 9, 0, + /* 7150 */ 'c', 'r', 'b', 'n', 'l', 'h', 9, 0, + /* 7158 */ 'c', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, + /* 7167 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, + /* 7177 */ 'c', 'l', 'r', 'b', 'n', 'l', 'h', 9, 0, + /* 7186 */ 'l', 'o', 'c', 'n', 'l', 'h', 9, 0, + /* 7194 */ 's', 't', 'o', 'c', 'n', 'l', 'h', 9, 0, + /* 7203 */ 'l', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, + /* 7212 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, + /* 7222 */ 'j', 'g', 'n', 'l', 'h', 9, 0, + /* 7229 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, + /* 7239 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, + /* 7250 */ 'b', 'i', 'n', 'l', 'h', 9, 0, + /* 7257 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'h', 9, 0, + /* 7267 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'h', 9, 0, + /* 7278 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'h', 9, 0, + /* 7289 */ 'c', 'i', 'j', 'n', 'l', 'h', 9, 0, + /* 7297 */ 'c', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, + /* 7306 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, + /* 7316 */ 'c', 'l', 'i', 'j', 'n', 'l', 'h', 9, 0, + /* 7325 */ 'c', 'r', 'j', 'n', 'l', 'h', 9, 0, + /* 7333 */ 'c', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, + /* 7342 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, + /* 7352 */ 'c', 'l', 'r', 'j', 'n', 'l', 'h', 9, 0, + /* 7361 */ 'v', 'm', 'n', 'l', 'h', 9, 0, + /* 7368 */ 'l', 'o', 'c', 'r', 'n', 'l', 'h', 9, 0, + /* 7377 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'h', 9, 0, + /* 7387 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'h', 9, 0, + /* 7398 */ 'c', 'l', 'g', 't', 'n', 'l', 'h', 9, 0, + /* 7407 */ 'c', 'i', 't', 'n', 'l', 'h', 9, 0, + /* 7415 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'h', 9, 0, + /* 7425 */ 'c', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, + /* 7434 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, + /* 7444 */ 'c', 'l', 't', 'n', 'l', 'h', 9, 0, + /* 7452 */ 'c', 'r', 't', 'n', 'l', 'h', 9, 0, + /* 7460 */ 'c', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, + /* 7469 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, + /* 7479 */ 'c', 'l', 'r', 't', 'n', 'l', 'h', 9, 0, + /* 7488 */ 'v', 'u', 'p', 'l', 'h', 9, 0, + /* 7495 */ 'l', 'o', 'c', 'r', 'l', 'h', 9, 0, + /* 7503 */ 'l', 'o', 'c', 'g', 'r', 'l', 'h', 9, 0, + /* 7512 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'h', 9, 0, + /* 7522 */ 'v', 'm', 'r', 'l', 'h', 9, 0, + /* 7529 */ 'v', 'e', 's', 'r', 'l', 'h', 9, 0, + /* 7537 */ 'v', 'e', 's', 'l', 'h', 9, 0, + /* 7544 */ 'c', 'l', 'g', 't', 'l', 'h', 9, 0, + /* 7552 */ 'c', 'i', 't', 'l', 'h', 9, 0, + /* 7559 */ 'c', 'l', 'f', 'i', 't', 'l', 'h', 9, 0, + /* 7568 */ 'c', 'g', 'i', 't', 'l', 'h', 9, 0, + /* 7576 */ 'c', 'l', 'g', 'i', 't', 'l', 'h', 9, 0, + /* 7585 */ 'c', 'l', 't', 'l', 'h', 9, 0, + /* 7592 */ 'c', 'r', 't', 'l', 'h', 9, 0, + /* 7599 */ 'c', 'g', 'r', 't', 'l', 'h', 9, 0, + /* 7607 */ 'c', 'l', 'g', 'r', 't', 'l', 'h', 9, 0, + /* 7616 */ 'c', 'l', 'r', 't', 'l', 'h', 9, 0, + /* 7624 */ 'v', 'm', 'x', 'l', 'h', 9, 0, + /* 7631 */ 'i', 'c', 'm', 'h', 9, 0, + /* 7637 */ 's', 't', 'c', 'm', 'h', 9, 0, + /* 7644 */ 'v', 'g', 'f', 'm', 'h', 9, 0, + /* 7651 */ 'v', 'g', 'm', 'h', 9, 0, + /* 7657 */ 'v', 'e', 'r', 'i', 'm', 'h', 9, 0, + /* 7665 */ 'c', 'l', 'm', 'h', 9, 0, + /* 7671 */ 's', 't', 'm', 'h', 9, 0, + /* 7677 */ 'v', 's', 'u', 'm', 'h', 9, 0, + /* 7684 */ 'v', 'm', 'h', 9, 0, + /* 7689 */ 'c', 'i', 'b', 'n', 'h', 9, 0, + /* 7696 */ 'c', 'g', 'i', 'b', 'n', 'h', 9, 0, + /* 7704 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 9, 0, + /* 7713 */ 'c', 'l', 'i', 'b', 'n', 'h', 9, 0, + /* 7721 */ 'c', 'r', 'b', 'n', 'h', 9, 0, + /* 7728 */ 'c', 'g', 'r', 'b', 'n', 'h', 9, 0, + /* 7736 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 9, 0, + /* 7745 */ 'c', 'l', 'r', 'b', 'n', 'h', 9, 0, + /* 7753 */ 'l', 'o', 'c', 'n', 'h', 9, 0, + /* 7760 */ 's', 't', 'o', 'c', 'n', 'h', 9, 0, + /* 7768 */ 'l', 'o', 'c', 'g', 'n', 'h', 9, 0, + /* 7776 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 9, 0, + /* 7785 */ 'j', 'g', 'n', 'h', 9, 0, + /* 7791 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, + /* 7800 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, + /* 7810 */ 'b', 'i', 'n', 'h', 9, 0, + /* 7816 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 9, 0, + /* 7825 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 9, 0, + /* 7835 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 9, 0, + /* 7845 */ 'c', 'i', 'j', 'n', 'h', 9, 0, + /* 7852 */ 'c', 'g', 'i', 'j', 'n', 'h', 9, 0, + /* 7860 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 9, 0, + /* 7869 */ 'c', 'l', 'i', 'j', 'n', 'h', 9, 0, + /* 7877 */ 'c', 'r', 'j', 'n', 'h', 9, 0, + /* 7884 */ 'c', 'g', 'r', 'j', 'n', 'h', 9, 0, + /* 7892 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 9, 0, + /* 7901 */ 'c', 'l', 'r', 'j', 'n', 'h', 9, 0, + /* 7909 */ 'v', 'm', 'n', 'h', 9, 0, + /* 7915 */ 'l', 'o', 'c', 'r', 'n', 'h', 9, 0, + /* 7923 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 9, 0, + /* 7932 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 9, 0, + /* 7942 */ 'c', 'l', 'g', 't', 'n', 'h', 9, 0, + /* 7950 */ 'c', 'i', 't', 'n', 'h', 9, 0, + /* 7957 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 9, 0, + /* 7966 */ 'c', 'g', 'i', 't', 'n', 'h', 9, 0, + /* 7974 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 9, 0, + /* 7983 */ 'c', 'l', 't', 'n', 'h', 9, 0, + /* 7990 */ 'c', 'r', 't', 'n', 'h', 9, 0, + /* 7997 */ 'c', 'g', 'r', 't', 'n', 'h', 9, 0, + /* 8005 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 9, 0, + /* 8014 */ 'c', 'l', 'r', 't', 'n', 'h', 9, 0, + /* 8022 */ 'v', 'm', 'a', 'o', 'h', 9, 0, + /* 8029 */ 'v', 'm', 'a', 'l', 'o', 'h', 9, 0, + /* 8037 */ 'v', 'm', 'l', 'o', 'h', 9, 0, + /* 8044 */ 'v', 'm', 'o', 'h', 9, 0, + /* 8050 */ 'v', 'l', 'r', 'e', 'p', 'h', 9, 0, + /* 8058 */ 'v', 'r', 'e', 'p', 'h', 9, 0, + /* 8065 */ 'v', 'l', 'p', 'h', 9, 0, + /* 8071 */ 'v', 'u', 'p', 'h', 9, 0, + /* 8077 */ 'v', 'c', 'e', 'q', 'h', 9, 0, + /* 8084 */ 'l', 'o', 'c', 'r', 'h', 9, 0, + /* 8091 */ 'l', 'o', 'c', 'g', 'r', 'h', 9, 0, + /* 8099 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 9, 0, + /* 8108 */ 'v', 'm', 'r', 'h', 9, 0, + /* 8114 */ 'v', 'i', 's', 't', 'r', 'h', 9, 0, + /* 8122 */ 'v', 'p', 'k', 's', 'h', 9, 0, + /* 8129 */ 'v', 'p', 'k', 'l', 's', 'h', 9, 0, + /* 8137 */ 'v', 's', 'h', 9, 0, + /* 8142 */ 'v', 'p', 'o', 'p', 'c', 't', 'h', 9, 0, + /* 8151 */ 'b', 'r', 'c', 't', 'h', 9, 0, + /* 8158 */ 'c', 'l', 'g', 't', 'h', 9, 0, + /* 8165 */ 'c', 'i', 't', 'h', 9, 0, + /* 8171 */ 'c', 'l', 'f', 'i', 't', 'h', 9, 0, + /* 8179 */ 'c', 'g', 'i', 't', 'h', 9, 0, + /* 8186 */ 'c', 'l', 'g', 'i', 't', 'h', 9, 0, + /* 8194 */ 'c', 'l', 't', 'h', 9, 0, + /* 8200 */ 'c', 'r', 't', 'h', 9, 0, + /* 8206 */ 'c', 'g', 'r', 't', 'h', 9, 0, + /* 8213 */ 'c', 'l', 'g', 'r', 't', 'h', 9, 0, + /* 8221 */ 'c', 'l', 'r', 't', 'h', 9, 0, + /* 8228 */ 's', 't', 'h', 9, 0, + /* 8233 */ 'v', 'e', 's', 'r', 'a', 'v', 'h', 9, 0, + /* 8242 */ 'v', 'l', 'g', 'v', 'h', 9, 0, + /* 8249 */ 'v', 'e', 'r', 'l', 'l', 'v', 'h', 9, 0, + /* 8258 */ 'v', 'e', 's', 'r', 'l', 'v', 'h', 9, 0, + /* 8267 */ 'v', 'e', 's', 'l', 'v', 'h', 9, 0, + /* 8275 */ 'l', 'r', 'v', 'h', 9, 0, + /* 8281 */ 's', 't', 'r', 'v', 'h', 9, 0, + /* 8288 */ 'b', 'x', 'h', 9, 0, + /* 8293 */ 'v', 'm', 'x', 'h', 9, 0, + /* 8299 */ 'b', 'r', 'x', 'h', 9, 0, + /* 8305 */ 'm', 'a', 'y', 'h', 9, 0, + /* 8311 */ 'm', 'y', 'h', 9, 0, + /* 8316 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 9, 0, + /* 8325 */ 'v', 'f', 'a', 'e', 'z', 'h', 9, 0, + /* 8333 */ 'v', 'f', 'e', 'e', 'z', 'h', 9, 0, + /* 8341 */ 'v', 'l', 'l', 'e', 'z', 'h', 9, 0, + /* 8349 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 9, 0, + /* 8358 */ 'v', 'c', 'l', 'z', 'h', 9, 0, + /* 8365 */ 'v', 'c', 't', 'z', 'h', 9, 0, + /* 8372 */ 'n', 'i', 'a', 'i', 9, 0, + /* 8378 */ 'v', 's', 'b', 'c', 'b', 'i', 9, 0, + /* 8386 */ 'v', 's', 'c', 'b', 'i', 9, 0, + /* 8393 */ 'v', 's', 'b', 'i', 9, 0, + /* 8399 */ 'v', 'f', 't', 'c', 'i', 9, 0, + /* 8406 */ 'v', 'p', 'd', 'i', 9, 0, + /* 8412 */ 'a', 'f', 'i', 9, 0, + /* 8417 */ 'c', 'f', 'i', 9, 0, + /* 8422 */ 'a', 'g', 'f', 'i', 9, 0, + /* 8428 */ 'c', 'g', 'f', 'i', 9, 0, + /* 8434 */ 'a', 'l', 'g', 'f', 'i', 9, 0, + /* 8441 */ 'c', 'l', 'g', 'f', 'i', 9, 0, + /* 8448 */ 's', 'l', 'g', 'f', 'i', 9, 0, + /* 8455 */ 'm', 's', 'g', 'f', 'i', 9, 0, + /* 8462 */ 'a', 'l', 'f', 'i', 9, 0, + /* 8468 */ 'c', 'l', 'f', 'i', 9, 0, + /* 8474 */ 's', 'l', 'f', 'i', 9, 0, + /* 8480 */ 'm', 's', 'f', 'i', 9, 0, + /* 8486 */ 'v', 'f', 'i', 9, 0, + /* 8491 */ 'a', 'h', 'i', 9, 0, + /* 8496 */ 'l', 'o', 'c', 'h', 'i', 9, 0, + /* 8503 */ 'a', 'g', 'h', 'i', 9, 0, + /* 8509 */ 'l', 'o', 'c', 'g', 'h', 'i', 9, 0, + /* 8517 */ 'l', 'g', 'h', 'i', 9, 0, + /* 8523 */ 'm', 'g', 'h', 'i', 9, 0, + /* 8529 */ 'm', 'v', 'g', 'h', 'i', 9, 0, + /* 8536 */ 'l', 'o', 'c', 'h', 'h', 'i', 9, 0, + /* 8544 */ 'm', 'v', 'h', 'h', 'i', 9, 0, + /* 8551 */ 'l', 'h', 'i', 9, 0, + /* 8556 */ 'm', 'h', 'i', 9, 0, + /* 8561 */ 'm', 'v', 'h', 'i', 9, 0, + /* 8567 */ 'c', 'l', 'i', 9, 0, + /* 8572 */ 'n', 'i', 9, 0, + /* 8576 */ 'o', 'i', 9, 0, + /* 8580 */ 'v', 'r', 'e', 'p', 'i', 9, 0, + /* 8587 */ 't', 'p', 'i', 9, 0, + /* 8592 */ 'q', 'c', 't', 'r', 'i', 9, 0, + /* 8599 */ 'a', 's', 'i', 9, 0, + /* 8604 */ 'a', 'g', 's', 'i', 9, 0, + /* 8610 */ 'a', 'l', 'g', 's', 'i', 9, 0, + /* 8617 */ 'c', 'h', 's', 'i', 9, 0, + /* 8623 */ 'c', 'l', 'f', 'h', 's', 'i', 9, 0, + /* 8631 */ 'c', 'g', 'h', 's', 'i', 9, 0, + /* 8638 */ 'c', 'l', 'g', 'h', 's', 'i', 9, 0, + /* 8646 */ 'c', 'h', 'h', 's', 'i', 9, 0, + /* 8653 */ 'c', 'l', 'h', 'h', 's', 'i', 9, 0, + /* 8661 */ 'a', 'l', 's', 'i', 9, 0, + /* 8667 */ 'q', 's', 'i', 9, 0, + /* 8672 */ 's', 't', 's', 'i', 9, 0, + /* 8678 */ 'p', 't', 'i', 9, 0, + /* 8683 */ 'm', 'v', 'i', 9, 0, + /* 8688 */ 'x', 'i', 9, 0, + /* 8692 */ 'c', 'i', 'j', 9, 0, + /* 8697 */ 'c', 'g', 'i', 'j', 9, 0, + /* 8703 */ 'c', 'l', 'g', 'i', 'j', 9, 0, + /* 8710 */ 'c', 'l', 'i', 'j', 9, 0, + /* 8716 */ 'c', 'r', 'j', 9, 0, + /* 8721 */ 'c', 'g', 'r', 'j', 9, 0, + /* 8727 */ 'c', 'l', 'g', 'r', 'j', 9, 0, + /* 8734 */ 'c', 'l', 'r', 'j', 9, 0, + /* 8740 */ 's', 'l', 'a', 'k', 9, 0, + /* 8746 */ 's', 'r', 'a', 'k', 9, 0, + /* 8752 */ 'p', 'a', 'c', 'k', 9, 0, + /* 8758 */ 's', 'c', 'k', 9, 0, + /* 8763 */ 's', 't', 'c', 'k', 9, 0, + /* 8769 */ 'm', 'v', 'c', 'k', 9, 0, + /* 8775 */ 'm', 'v', 'c', 'd', 'k', 9, 0, + /* 8782 */ 'w', 'f', 'k', 9, 0, + /* 8787 */ 'a', 'h', 'i', 'k', 9, 0, + /* 8793 */ 'a', 'g', 'h', 'i', 'k', 9, 0, + /* 8800 */ 'a', 'l', 'g', 'h', 's', 'i', 'k', 9, 0, + /* 8809 */ 'a', 'l', 'h', 's', 'i', 'k', 9, 0, + /* 8817 */ 's', 'l', 'l', 'k', 9, 0, + /* 8823 */ 's', 'r', 'l', 'k', 9, 0, + /* 8829 */ 'e', 'd', 'm', 'k', 9, 0, + /* 8835 */ 'u', 'n', 'p', 'k', 9, 0, + /* 8841 */ 'v', 'p', 'k', 9, 0, + /* 8846 */ 'a', 'r', 'k', 9, 0, + /* 8851 */ 'a', 'g', 'r', 'k', 9, 0, + /* 8857 */ 'a', 'l', 'g', 'r', 'k', 9, 0, + /* 8864 */ 's', 'l', 'g', 'r', 'k', 9, 0, + /* 8871 */ 'm', 'g', 'r', 'k', 9, 0, + /* 8877 */ 'n', 'g', 'r', 'k', 9, 0, + /* 8883 */ 'o', 'g', 'r', 'k', 9, 0, + /* 8889 */ 's', 'g', 'r', 'k', 9, 0, + /* 8895 */ 'x', 'g', 'r', 'k', 9, 0, + /* 8901 */ 'a', 'l', 'r', 'k', 9, 0, + /* 8907 */ 's', 'l', 'r', 'k', 9, 0, + /* 8913 */ 'n', 'r', 'k', 9, 0, + /* 8918 */ 'o', 'r', 'k', 9, 0, + /* 8923 */ 's', 'r', 'k', 9, 0, + /* 8928 */ 'x', 'r', 'k', 9, 0, + /* 8933 */ 'm', 'v', 'c', 's', 'k', 9, 0, + /* 8940 */ 'i', 'v', 's', 'k', 9, 0, + /* 8946 */ 'l', 'a', 'a', 'l', 9, 0, + /* 8952 */ 'b', 'a', 'l', 9, 0, + /* 8957 */ 'v', 'm', 'a', 'l', 9, 0, + /* 8963 */ 'c', 'i', 'b', 'l', 9, 0, + /* 8969 */ 'c', 'g', 'i', 'b', 'l', 9, 0, + /* 8976 */ 'c', 'l', 'g', 'i', 'b', 'l', 9, 0, + /* 8984 */ 'c', 'l', 'i', 'b', 'l', 9, 0, + /* 8991 */ 'c', 'r', 'b', 'l', 9, 0, + /* 8997 */ 'c', 'g', 'r', 'b', 'l', 9, 0, + /* 9004 */ 'c', 'l', 'g', 'r', 'b', 'l', 9, 0, + /* 9012 */ 'c', 'l', 'r', 'b', 'l', 9, 0, + /* 9019 */ 'v', 'e', 'c', 'l', 9, 0, + /* 9025 */ 'c', 'l', 'c', 'l', 9, 0, + /* 9031 */ 'l', 'o', 'c', 'l', 9, 0, + /* 9037 */ 's', 't', 'o', 'c', 'l', 9, 0, + /* 9044 */ 'b', 'r', 'c', 'l', 9, 0, + /* 9050 */ 'm', 'v', 'c', 'l', 9, 0, + /* 9056 */ 's', 'l', 'd', 'l', 9, 0, + /* 9062 */ 's', 'r', 'd', 'l', 9, 0, + /* 9068 */ 'v', 's', 'e', 'l', 9, 0, + /* 9074 */ 's', 't', 'f', 'l', 9, 0, + /* 9080 */ 'l', 'o', 'c', 'g', 'l', 9, 0, + /* 9087 */ 's', 't', 'o', 'c', 'g', 'l', 9, 0, + /* 9095 */ 'j', 'g', 'l', 9, 0, + /* 9100 */ 'v', 'a', 'v', 'g', 'l', 9, 0, + /* 9107 */ 'v', 'c', 'h', 'l', 9, 0, + /* 9113 */ 'l', 'o', 'c', 'f', 'h', 'l', 9, 0, + /* 9121 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 9, 0, + /* 9130 */ 'i', 'i', 'h', 'l', 9, 0, + /* 9136 */ 'l', 'l', 'i', 'h', 'l', 9, 0, + /* 9143 */ 'n', 'i', 'h', 'l', 9, 0, + /* 9149 */ 'o', 'i', 'h', 'l', 9, 0, + /* 9155 */ 't', 'm', 'h', 'l', 9, 0, + /* 9161 */ 'b', 'i', 'l', 9, 0, + /* 9166 */ 'l', 'o', 'c', 'h', 'i', 'l', 9, 0, + /* 9174 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 9, 0, + /* 9183 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 9, 0, + /* 9192 */ 'c', 'i', 'j', 'l', 9, 0, + /* 9198 */ 'c', 'g', 'i', 'j', 'l', 9, 0, + /* 9205 */ 'c', 'l', 'g', 'i', 'j', 'l', 9, 0, + /* 9213 */ 'c', 'l', 'i', 'j', 'l', 9, 0, + /* 9220 */ 'c', 'r', 'j', 'l', 9, 0, + /* 9226 */ 'c', 'g', 'r', 'j', 'l', 9, 0, + /* 9233 */ 'c', 'l', 'g', 'r', 'j', 'l', 9, 0, + /* 9241 */ 'c', 'l', 'r', 'j', 'l', 9, 0, + /* 9248 */ 'v', 'f', 'l', 'l', 9, 0, + /* 9254 */ 'i', 'i', 'l', 'l', 9, 0, + /* 9260 */ 'l', 'l', 'i', 'l', 'l', 9, 0, + /* 9267 */ 'n', 'i', 'l', 'l', 9, 0, + /* 9273 */ 'o', 'i', 'l', 'l', 9, 0, + /* 9279 */ 't', 'm', 'l', 'l', 9, 0, + /* 9285 */ 'v', 'u', 'p', 'l', 'l', 9, 0, + /* 9292 */ 'v', 'e', 'r', 'l', 'l', 9, 0, + /* 9299 */ 's', 'l', 'l', 9, 0, + /* 9304 */ 'v', 'l', 'l', 9, 0, + /* 9309 */ 'v', 'm', 'l', 9, 0, + /* 9314 */ 'c', 'i', 'b', 'n', 'l', 9, 0, + /* 9321 */ 'c', 'g', 'i', 'b', 'n', 'l', 9, 0, + /* 9329 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 9, 0, + /* 9338 */ 'c', 'l', 'i', 'b', 'n', 'l', 9, 0, + /* 9346 */ 'c', 'r', 'b', 'n', 'l', 9, 0, + /* 9353 */ 'c', 'g', 'r', 'b', 'n', 'l', 9, 0, + /* 9361 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 9, 0, + /* 9370 */ 'c', 'l', 'r', 'b', 'n', 'l', 9, 0, + /* 9378 */ 'l', 'o', 'c', 'n', 'l', 9, 0, + /* 9385 */ 's', 't', 'o', 'c', 'n', 'l', 9, 0, + /* 9393 */ 'l', 'o', 'c', 'g', 'n', 'l', 9, 0, + /* 9401 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 9, 0, + /* 9410 */ 'j', 'g', 'n', 'l', 9, 0, + /* 9416 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, + /* 9425 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, + /* 9435 */ 'b', 'i', 'n', 'l', 9, 0, + /* 9441 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 9, 0, + /* 9450 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 9, 0, + /* 9460 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 9, 0, + /* 9470 */ 'c', 'i', 'j', 'n', 'l', 9, 0, + /* 9477 */ 'c', 'g', 'i', 'j', 'n', 'l', 9, 0, + /* 9485 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 9, 0, + /* 9494 */ 'c', 'l', 'i', 'j', 'n', 'l', 9, 0, + /* 9502 */ 'c', 'r', 'j', 'n', 'l', 9, 0, + /* 9509 */ 'c', 'g', 'r', 'j', 'n', 'l', 9, 0, + /* 9517 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 9, 0, + /* 9526 */ 'c', 'l', 'r', 'j', 'n', 'l', 9, 0, + /* 9534 */ 'v', 'm', 'n', 'l', 9, 0, + /* 9540 */ 'l', 'o', 'c', 'r', 'n', 'l', 9, 0, + /* 9548 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 9, 0, + /* 9557 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 9, 0, + /* 9567 */ 'c', 'l', 'g', 't', 'n', 'l', 9, 0, + /* 9575 */ 'c', 'i', 't', 'n', 'l', 9, 0, + /* 9582 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 9, 0, + /* 9591 */ 'c', 'g', 'i', 't', 'n', 'l', 9, 0, + /* 9599 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 9, 0, + /* 9608 */ 'c', 'l', 't', 'n', 'l', 9, 0, + /* 9615 */ 'c', 'r', 't', 'n', 'l', 9, 0, + /* 9622 */ 'c', 'g', 'r', 't', 'n', 'l', 9, 0, + /* 9630 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 9, 0, + /* 9639 */ 'c', 'l', 'r', 't', 'n', 'l', 9, 0, + /* 9647 */ 'v', 'u', 'p', 'l', 9, 0, + /* 9653 */ 'l', 'a', 'r', 'l', 9, 0, + /* 9659 */ 'l', 'o', 'c', 'r', 'l', 9, 0, + /* 9666 */ 'p', 'f', 'd', 'r', 'l', 9, 0, + /* 9673 */ 'c', 'g', 'f', 'r', 'l', 9, 0, + /* 9680 */ 'c', 'l', 'g', 'f', 'r', 'l', 9, 0, + /* 9688 */ 'l', 'l', 'g', 'f', 'r', 'l', 9, 0, + /* 9696 */ 'l', 'o', 'c', 'g', 'r', 'l', 9, 0, + /* 9704 */ 'c', 'l', 'g', 'r', 'l', 9, 0, + /* 9711 */ 's', 't', 'g', 'r', 'l', 9, 0, + /* 9718 */ 'c', 'h', 'r', 'l', 9, 0, + /* 9724 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 9, 0, + /* 9733 */ 'c', 'g', 'h', 'r', 'l', 9, 0, + /* 9740 */ 'c', 'l', 'g', 'h', 'r', 'l', 9, 0, + /* 9748 */ 'l', 'l', 'g', 'h', 'r', 'l', 9, 0, + /* 9756 */ 'c', 'l', 'h', 'r', 'l', 9, 0, + /* 9763 */ 'l', 'l', 'h', 'r', 'l', 9, 0, + /* 9770 */ 's', 't', 'h', 'r', 'l', 9, 0, + /* 9777 */ 'c', 'l', 'r', 'l', 9, 0, + /* 9783 */ 'v', 'l', 'r', 'l', 9, 0, + /* 9789 */ 'v', 'm', 'r', 'l', 9, 0, + /* 9795 */ 'v', 'e', 's', 'r', 'l', 9, 0, + /* 9802 */ 'v', 's', 'r', 'l', 9, 0, + /* 9808 */ 'v', 's', 't', 'r', 'l', 9, 0, + /* 9815 */ 'e', 'x', 'r', 'l', 9, 0, + /* 9821 */ 'b', 'r', 'a', 's', 'l', 9, 0, + /* 9828 */ 'v', 'e', 's', 'l', 9, 0, + /* 9834 */ 'v', 'm', 's', 'l', 9, 0, + /* 9840 */ 'v', 's', 'l', 9, 0, + /* 9845 */ 'l', 'c', 'c', 't', 'l', 9, 0, + /* 9852 */ 'l', 'c', 't', 'l', 9, 0, + /* 9858 */ 'l', 'p', 'c', 't', 'l', 9, 0, + /* 9865 */ 'l', 's', 'c', 't', 'l', 9, 0, + /* 9872 */ 's', 't', 'c', 't', 'l', 9, 0, + /* 9879 */ 'c', 'l', 'g', 't', 'l', 9, 0, + /* 9886 */ 'c', 'i', 't', 'l', 9, 0, + /* 9892 */ 'c', 'l', 'f', 'i', 't', 'l', 9, 0, + /* 9900 */ 'c', 'g', 'i', 't', 'l', 9, 0, + /* 9907 */ 'c', 'l', 'g', 'i', 't', 'l', 9, 0, + /* 9915 */ 'c', 'l', 't', 'l', 9, 0, + /* 9921 */ 'c', 'r', 't', 'l', 9, 0, + /* 9927 */ 'c', 'g', 'r', 't', 'l', 9, 0, + /* 9934 */ 'c', 'l', 'g', 'r', 't', 'l', 9, 0, + /* 9942 */ 'c', 'l', 'r', 't', 'l', 9, 0, + /* 9949 */ 'v', 's', 't', 'l', 9, 0, + /* 9955 */ 'v', 'l', 9, 0, + /* 9959 */ 'v', 'm', 'x', 'l', 9, 0, + /* 9965 */ 'm', 'a', 'y', 'l', 9, 0, + /* 9971 */ 'm', 'y', 'l', 9, 0, + /* 9976 */ 'l', 'a', 'm', 9, 0, + /* 9981 */ 's', 't', 'a', 'm', 9, 0, + /* 9987 */ 'v', 'g', 'b', 'm', 9, 0, + /* 9993 */ 'i', 'r', 'b', 'm', 9, 0, + /* 9999 */ 'r', 'r', 'b', 'm', 9, 0, + /* 10005 */ 'i', 'c', 'm', 9, 0, + /* 10010 */ 'l', 'o', 'c', 'm', 9, 0, + /* 10016 */ 's', 't', 'o', 'c', 'm', 9, 0, + /* 10023 */ 's', 't', 'c', 'm', 9, 0, + /* 10029 */ 'v', 'g', 'f', 'm', 9, 0, + /* 10035 */ 'v', 'f', 'm', 9, 0, + /* 10040 */ 'l', 'o', 'c', 'g', 'm', 9, 0, + /* 10047 */ 's', 't', 'o', 'c', 'g', 'm', 9, 0, + /* 10055 */ 'j', 'g', 'm', 9, 0, + /* 10060 */ 'v', 'g', 'm', 9, 0, + /* 10065 */ 'l', 'o', 'c', 'f', 'h', 'm', 9, 0, + /* 10073 */ 's', 't', 'o', 'c', 'f', 'h', 'm', 9, 0, + /* 10082 */ 'b', 'i', 'm', 9, 0, + /* 10087 */ 'l', 'o', 'c', 'h', 'i', 'm', 9, 0, + /* 10095 */ 'l', 'o', 'c', 'g', 'h', 'i', 'm', 9, 0, + /* 10104 */ 'l', 'o', 'c', 'h', 'h', 'i', 'm', 9, 0, + /* 10113 */ 'v', 'e', 'r', 'i', 'm', 9, 0, + /* 10120 */ 'j', 'm', 9, 0, + /* 10124 */ 'k', 'm', 9, 0, + /* 10128 */ 'c', 'l', 'm', 9, 0, + /* 10133 */ 'v', 'l', 'm', 9, 0, + /* 10138 */ 'b', 'n', 'm', 9, 0, + /* 10143 */ 'l', 'o', 'c', 'n', 'm', 9, 0, + /* 10150 */ 's', 't', 'o', 'c', 'n', 'm', 9, 0, + /* 10158 */ 'l', 'o', 'c', 'g', 'n', 'm', 9, 0, + /* 10166 */ 's', 't', 'o', 'c', 'g', 'n', 'm', 9, 0, + /* 10175 */ 'j', 'g', 'n', 'm', 9, 0, + /* 10181 */ 'l', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, + /* 10190 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, + /* 10200 */ 'b', 'i', 'n', 'm', 9, 0, + /* 10206 */ 'l', 'o', 'c', 'h', 'i', 'n', 'm', 9, 0, + /* 10215 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'm', 9, 0, + /* 10225 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'm', 9, 0, + /* 10235 */ 'j', 'n', 'm', 9, 0, + /* 10240 */ 'l', 'o', 'c', 'r', 'n', 'm', 9, 0, + /* 10248 */ 'l', 'o', 'c', 'g', 'r', 'n', 'm', 9, 0, + /* 10257 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'm', 9, 0, + /* 10267 */ 's', 'r', 'n', 'm', 9, 0, + /* 10273 */ 'i', 'p', 'm', 9, 0, + /* 10278 */ 's', 'p', 'm', 9, 0, + /* 10283 */ 'l', 'o', 'c', 'r', 'm', 9, 0, + /* 10290 */ 'v', 'b', 'p', 'e', 'r', 'm', 9, 0, + /* 10298 */ 'v', 'p', 'e', 'r', 'm', 9, 0, + /* 10305 */ 'l', 'o', 'c', 'g', 'r', 'm', 9, 0, + /* 10313 */ 'l', 'o', 'c', 'f', 'h', 'r', 'm', 9, 0, + /* 10322 */ 'b', 's', 'm', 9, 0, + /* 10327 */ 'v', 'c', 'k', 's', 'm', 9, 0, + /* 10334 */ 's', 't', 'n', 's', 'm', 9, 0, + /* 10341 */ 's', 't', 'o', 's', 'm', 9, 0, + /* 10348 */ 'b', 'a', 's', 's', 'm', 9, 0, + /* 10355 */ 'v', 's', 't', 'm', 9, 0, + /* 10361 */ 'v', 't', 'm', 9, 0, + /* 10366 */ 'v', 's', 'u', 'm', 9, 0, + /* 10372 */ 'l', 'a', 'n', 9, 0, + /* 10377 */ 'r', 'i', 's', 'b', 'g', 'n', 9, 0, + /* 10385 */ 'a', 'l', 's', 'i', 'h', 'n', 9, 0, + /* 10393 */ 'm', 'v', 'c', 'i', 'n', 9, 0, + /* 10400 */ 't', 'b', 'e', 'g', 'i', 'n', 9, 0, + /* 10408 */ 'p', 'g', 'i', 'n', 9, 0, + /* 10414 */ 'v', 'f', 'm', 'i', 'n', 9, 0, + /* 10421 */ 'v', 'm', 'n', 9, 0, + /* 10426 */ 'v', 'n', 'n', 9, 0, + /* 10431 */ 'm', 'v', 'n', 9, 0, + /* 10436 */ 'l', 'a', 'o', 9, 0, + /* 10441 */ 'v', 'm', 'a', 'o', 9, 0, + /* 10447 */ 'b', 'o', 9, 0, + /* 10451 */ 'l', 'o', 'c', 'o', 9, 0, + /* 10457 */ 's', 't', 'o', 'c', 'o', 9, 0, + /* 10464 */ 'l', 'o', 'c', 'g', 'o', 9, 0, + /* 10471 */ 's', 't', 'o', 'c', 'g', 'o', 9, 0, + /* 10479 */ 'j', 'g', 'o', 9, 0, + /* 10484 */ 'l', 'o', 'c', 'f', 'h', 'o', 9, 0, + /* 10492 */ 's', 't', 'o', 'c', 'f', 'h', 'o', 9, 0, + /* 10501 */ 'b', 'i', 'o', 9, 0, + /* 10506 */ 'l', 'o', 'c', 'h', 'i', 'o', 9, 0, + /* 10514 */ 'l', 'o', 'c', 'g', 'h', 'i', 'o', 9, 0, + /* 10523 */ 'l', 'o', 'c', 'h', 'h', 'i', 'o', 9, 0, + /* 10532 */ 'j', 'o', 9, 0, + /* 10536 */ 'v', 'm', 'a', 'l', 'o', 9, 0, + /* 10543 */ 'v', 'm', 'l', 'o', 9, 0, + /* 10549 */ 'p', 'l', 'o', 9, 0, + /* 10554 */ 'k', 'm', 'o', 9, 0, + /* 10559 */ 'v', 'm', 'o', 9, 0, + /* 10564 */ 'b', 'n', 'o', 9, 0, + /* 10569 */ 'l', 'o', 'c', 'n', 'o', 9, 0, + /* 10576 */ 's', 't', 'o', 'c', 'n', 'o', 9, 0, + /* 10584 */ 'l', 'o', 'c', 'g', 'n', 'o', 9, 0, + /* 10592 */ 's', 't', 'o', 'c', 'g', 'n', 'o', 9, 0, + /* 10601 */ 'j', 'g', 'n', 'o', 9, 0, + /* 10607 */ 'l', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, + /* 10616 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, + /* 10626 */ 'b', 'i', 'n', 'o', 9, 0, + /* 10632 */ 'l', 'o', 'c', 'h', 'i', 'n', 'o', 9, 0, + /* 10641 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'o', 9, 0, + /* 10651 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'o', 9, 0, + /* 10661 */ 'j', 'n', 'o', 9, 0, + /* 10666 */ 'p', 'p', 'n', 'o', 9, 0, + /* 10672 */ 'l', 'o', 'c', 'r', 'n', 'o', 9, 0, + /* 10680 */ 'l', 'o', 'c', 'g', 'r', 'n', 'o', 9, 0, + /* 10689 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'o', 9, 0, + /* 10699 */ 'p', 'r', 'n', 'o', 9, 0, + /* 10705 */ 'v', 'n', 'o', 9, 0, + /* 10710 */ 't', 'r', 'o', 'o', 9, 0, + /* 10716 */ 'l', 'o', 'c', 'r', 'o', 9, 0, + /* 10723 */ 'v', 'z', 'e', 'r', 'o', 9, 0, + /* 10730 */ 'l', 'o', 'c', 'g', 'r', 'o', 9, 0, + /* 10738 */ 'l', 'o', 'c', 'f', 'h', 'r', 'o', 9, 0, + /* 10747 */ 'v', 'f', 'p', 's', 'o', 9, 0, + /* 10754 */ 't', 'r', 't', 'o', 9, 0, + /* 10760 */ 'm', 'v', 'o', 9, 0, + /* 10765 */ 's', 't', 'a', 'p', 9, 0, + /* 10771 */ 'v', 'a', 'p', 9, 0, + /* 10776 */ 'z', 'a', 'p', 9, 0, + /* 10781 */ 'b', 'p', 9, 0, + /* 10785 */ 'l', 'o', 'c', 'p', 9, 0, + /* 10791 */ 's', 't', 'o', 'c', 'p', 9, 0, + /* 10798 */ 'm', 'v', 'c', 'p', 9, 0, + /* 10804 */ 's', 't', 'i', 'd', 'p', 9, 0, + /* 10811 */ 'v', 's', 'd', 'p', 9, 0, + /* 10817 */ 'v', 'd', 'p', 9, 0, + /* 10822 */ 'v', 'l', 'r', 'e', 'p', 9, 0, + /* 10829 */ 'v', 'r', 'e', 'p', 9, 0, + /* 10835 */ 'l', 'o', 'c', 'g', 'p', 9, 0, + /* 10842 */ 's', 't', 'o', 'c', 'g', 'p', 9, 0, + /* 10850 */ 's', 'i', 'g', 'p', 9, 0, + /* 10856 */ 'j', 'g', 'p', 9, 0, + /* 10861 */ 'v', 'l', 'v', 'g', 'p', 9, 0, + /* 10868 */ 'l', 'o', 'c', 'f', 'h', 'p', 9, 0, + /* 10876 */ 's', 't', 'o', 'c', 'f', 'h', 'p', 9, 0, + /* 10885 */ 'b', 'i', 'p', 9, 0, + /* 10890 */ 'l', 'o', 'c', 'h', 'i', 'p', 9, 0, + /* 10898 */ 'l', 'o', 'c', 'g', 'h', 'i', 'p', 9, 0, + /* 10907 */ 'l', 'o', 'c', 'h', 'h', 'i', 'p', 9, 0, + /* 10916 */ 'v', 'l', 'i', 'p', 9, 0, + /* 10922 */ 'j', 'p', 9, 0, + /* 10926 */ 'v', 'l', 'p', 9, 0, + /* 10931 */ 'v', 'm', 'p', 9, 0, + /* 10936 */ 'b', 'n', 'p', 9, 0, + /* 10941 */ 'l', 'o', 'c', 'n', 'p', 9, 0, + /* 10948 */ 's', 't', 'o', 'c', 'n', 'p', 9, 0, + /* 10956 */ 'l', 'o', 'c', 'g', 'n', 'p', 9, 0, + /* 10964 */ 's', 't', 'o', 'c', 'g', 'n', 'p', 9, 0, + /* 10973 */ 'j', 'g', 'n', 'p', 9, 0, + /* 10979 */ 'l', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, + /* 10988 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, + /* 10998 */ 'b', 'i', 'n', 'p', 9, 0, + /* 11004 */ 'l', 'o', 'c', 'h', 'i', 'n', 'p', 9, 0, + /* 11013 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'p', 9, 0, + /* 11023 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'p', 9, 0, + /* 11033 */ 'j', 'n', 'p', 9, 0, + /* 11038 */ 'l', 'o', 'c', 'r', 'n', 'p', 9, 0, + /* 11046 */ 'l', 'o', 'c', 'g', 'r', 'n', 'p', 9, 0, + /* 11055 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'p', 9, 0, + /* 11065 */ 'v', 'p', 's', 'o', 'p', 9, 0, + /* 11072 */ 'b', 'p', 'p', 9, 0, + /* 11077 */ 'l', 'p', 'p', 9, 0, + /* 11082 */ 'l', 'o', 'c', 'r', 'p', 9, 0, + /* 11089 */ 'l', 'o', 'c', 'g', 'r', 'p', 9, 0, + /* 11097 */ 'l', 'o', 'c', 'f', 'h', 'r', 'p', 9, 0, + /* 11106 */ 'b', 'p', 'r', 'p', 9, 0, + /* 11112 */ 'v', 's', 'r', 'p', 9, 0, + /* 11118 */ 'v', 'r', 'p', 9, 0, + /* 11123 */ 'l', 'a', 's', 'p', 9, 0, + /* 11129 */ 'c', 's', 'p', 9, 0, + /* 11134 */ 'v', 'm', 's', 'p', 9, 0, + /* 11140 */ 'v', 's', 'p', 9, 0, + /* 11145 */ 'v', 't', 'p', 9, 0, + /* 11150 */ 'v', 'a', 'q', 9, 0, + /* 11155 */ 'v', 'a', 'c', 'q', 9, 0, + /* 11161 */ 'v', 'a', 'c', 'c', 'q', 9, 0, + /* 11168 */ 'v', 'a', 'c', 'c', 'c', 'q', 9, 0, + /* 11176 */ 'v', 'c', 'e', 'q', 9, 0, + /* 11182 */ 'v', 's', 'b', 'c', 'b', 'i', 'q', 9, 0, + /* 11191 */ 'v', 's', 'c', 'b', 'i', 'q', 9, 0, + /* 11199 */ 'v', 's', 'b', 'i', 'q', 9, 0, + /* 11206 */ 'v', 's', 'u', 'm', 'q', 9, 0, + /* 11213 */ 'l', 'p', 'q', 9, 0, + /* 11218 */ 's', 't', 'p', 'q', 9, 0, + /* 11224 */ 'v', 'f', 's', 'q', 9, 0, + /* 11230 */ 'v', 's', 'q', 9, 0, + /* 11235 */ 'e', 'a', 'r', 9, 0, + /* 11240 */ 'e', 'p', 'a', 'r', 9, 0, + /* 11246 */ 'e', 's', 'a', 'r', 9, 0, + /* 11252 */ 's', 's', 'a', 'r', 9, 0, + /* 11258 */ 't', 'a', 'r', 9, 0, + /* 11263 */ 'm', 'a', 'd', 'b', 'r', 9, 0, + /* 11270 */ 'l', 'c', 'd', 'b', 'r', 9, 0, + /* 11277 */ 'd', 'd', 'b', 'r', 9, 0, + /* 11283 */ 'l', 'e', 'd', 'b', 'r', 9, 0, + /* 11290 */ 'c', 'f', 'd', 'b', 'r', 9, 0, + /* 11297 */ 'c', 'l', 'f', 'd', 'b', 'r', 9, 0, + /* 11305 */ 'c', 'g', 'd', 'b', 'r', 9, 0, + /* 11312 */ 'c', 'l', 'g', 'd', 'b', 'r', 9, 0, + /* 11320 */ 'd', 'i', 'd', 'b', 'r', 9, 0, + /* 11327 */ 'f', 'i', 'd', 'b', 'r', 9, 0, + /* 11334 */ 'k', 'd', 'b', 'r', 9, 0, + /* 11340 */ 'm', 'd', 'b', 'r', 9, 0, + /* 11346 */ 'l', 'n', 'd', 'b', 'r', 9, 0, + /* 11353 */ 'l', 'p', 'd', 'b', 'r', 9, 0, + /* 11360 */ 's', 'q', 'd', 'b', 'r', 9, 0, + /* 11367 */ 'm', 's', 'd', 'b', 'r', 9, 0, + /* 11374 */ 'l', 't', 'd', 'b', 'r', 9, 0, + /* 11381 */ 'l', 'x', 'd', 'b', 'r', 9, 0, + /* 11388 */ 'm', 'x', 'd', 'b', 'r', 9, 0, + /* 11395 */ 'm', 'a', 'e', 'b', 'r', 9, 0, + /* 11402 */ 'l', 'c', 'e', 'b', 'r', 9, 0, + /* 11409 */ 'l', 'd', 'e', 'b', 'r', 9, 0, + /* 11416 */ 'm', 'd', 'e', 'b', 'r', 9, 0, + /* 11423 */ 'm', 'e', 'e', 'b', 'r', 9, 0, + /* 11430 */ 'c', 'f', 'e', 'b', 'r', 9, 0, + /* 11437 */ 'c', 'l', 'f', 'e', 'b', 'r', 9, 0, + /* 11445 */ 'c', 'g', 'e', 'b', 'r', 9, 0, + /* 11452 */ 'c', 'l', 'g', 'e', 'b', 'r', 9, 0, + /* 11460 */ 'd', 'i', 'e', 'b', 'r', 9, 0, + /* 11467 */ 'f', 'i', 'e', 'b', 'r', 9, 0, + /* 11474 */ 'k', 'e', 'b', 'r', 9, 0, + /* 11480 */ 'l', 'n', 'e', 'b', 'r', 9, 0, + /* 11487 */ 'l', 'p', 'e', 'b', 'r', 9, 0, + /* 11494 */ 's', 'q', 'e', 'b', 'r', 9, 0, + /* 11501 */ 'm', 's', 'e', 'b', 'r', 9, 0, + /* 11508 */ 'l', 't', 'e', 'b', 'r', 9, 0, + /* 11515 */ 'l', 'x', 'e', 'b', 'r', 9, 0, + /* 11522 */ 'c', 'd', 'f', 'b', 'r', 9, 0, + /* 11529 */ 'c', 'e', 'f', 'b', 'r', 9, 0, + /* 11536 */ 'c', 'd', 'l', 'f', 'b', 'r', 9, 0, + /* 11544 */ 'c', 'e', 'l', 'f', 'b', 'r', 9, 0, + /* 11552 */ 'c', 'x', 'l', 'f', 'b', 'r', 9, 0, + /* 11560 */ 'c', 'x', 'f', 'b', 'r', 9, 0, + /* 11567 */ 'c', 'd', 'g', 'b', 'r', 9, 0, + /* 11574 */ 'c', 'e', 'g', 'b', 'r', 9, 0, + /* 11581 */ 'c', 'd', 'l', 'g', 'b', 'r', 9, 0, + /* 11589 */ 'c', 'e', 'l', 'g', 'b', 'r', 9, 0, + /* 11597 */ 'c', 'x', 'l', 'g', 'b', 'r', 9, 0, + /* 11605 */ 'c', 'x', 'g', 'b', 'r', 9, 0, + /* 11612 */ 's', 'l', 'b', 'r', 9, 0, + /* 11618 */ 'a', 'x', 'b', 'r', 9, 0, + /* 11624 */ 'l', 'c', 'x', 'b', 'r', 9, 0, + /* 11631 */ 'l', 'd', 'x', 'b', 'r', 9, 0, + /* 11638 */ 'l', 'e', 'x', 'b', 'r', 9, 0, + /* 11645 */ 'c', 'f', 'x', 'b', 'r', 9, 0, + /* 11652 */ 'c', 'l', 'f', 'x', 'b', 'r', 9, 0, + /* 11660 */ 'c', 'g', 'x', 'b', 'r', 9, 0, + /* 11667 */ 'c', 'l', 'g', 'x', 'b', 'r', 9, 0, + /* 11675 */ 'f', 'i', 'x', 'b', 'r', 9, 0, + /* 11682 */ 'k', 'x', 'b', 'r', 9, 0, + /* 11688 */ 'm', 'x', 'b', 'r', 9, 0, + /* 11694 */ 'l', 'n', 'x', 'b', 'r', 9, 0, + /* 11701 */ 'l', 'p', 'x', 'b', 'r', 9, 0, + /* 11708 */ 's', 'q', 'x', 'b', 'r', 9, 0, + /* 11715 */ 's', 'x', 'b', 'r', 9, 0, + /* 11721 */ 'l', 't', 'x', 'b', 'r', 9, 0, + /* 11728 */ 'b', 'c', 'r', 9, 0, + /* 11733 */ 'l', 'l', 'g', 'c', 'r', 9, 0, + /* 11740 */ 'a', 'l', 'c', 'r', 9, 0, + /* 11746 */ 'l', 'l', 'c', 'r', 9, 0, + /* 11752 */ 'l', 'o', 'c', 'r', 9, 0, + /* 11758 */ 'm', 'a', 'd', 'r', 9, 0, + /* 11764 */ 't', 'b', 'd', 'r', 9, 0, + /* 11770 */ 'l', 'c', 'd', 'r', 9, 0, + /* 11776 */ 'd', 'd', 'r', 9, 0, + /* 11781 */ 't', 'b', 'e', 'd', 'r', 9, 0, + /* 11788 */ 'l', 'e', 'd', 'r', 9, 0, + /* 11794 */ 'c', 'f', 'd', 'r', 9, 0, + /* 11800 */ 'c', 'g', 'd', 'r', 9, 0, + /* 11806 */ 'l', 'g', 'd', 'r', 9, 0, + /* 11812 */ 't', 'h', 'd', 'r', 9, 0, + /* 11818 */ 'f', 'i', 'd', 'r', 9, 0, + /* 11824 */ 'l', 'd', 'r', 9, 0, + /* 11829 */ 'm', 'd', 'r', 9, 0, + /* 11834 */ 'l', 'n', 'd', 'r', 9, 0, + /* 11840 */ 'l', 'p', 'd', 'r', 9, 0, + /* 11846 */ 's', 'q', 'd', 'r', 9, 0, + /* 11852 */ 'l', 'r', 'd', 'r', 9, 0, + /* 11858 */ 'm', 's', 'd', 'r', 9, 0, + /* 11864 */ 'c', 'p', 's', 'd', 'r', 9, 0, + /* 11871 */ 'l', 't', 'd', 'r', 9, 0, + /* 11877 */ 'l', 'x', 'd', 'r', 9, 0, + /* 11883 */ 'm', 'x', 'd', 'r', 9, 0, + /* 11889 */ 'l', 'z', 'd', 'r', 9, 0, + /* 11895 */ 'm', 'a', 'e', 'r', 9, 0, + /* 11901 */ 'b', 'e', 'r', 9, 0, + /* 11906 */ 'l', 'c', 'e', 'r', 9, 0, + /* 11912 */ 't', 'h', 'd', 'e', 'r', 9, 0, + /* 11919 */ 'l', 'd', 'e', 'r', 9, 0, + /* 11925 */ 'm', 'd', 'e', 'r', 9, 0, + /* 11931 */ 'm', 'e', 'e', 'r', 9, 0, + /* 11937 */ 'c', 'f', 'e', 'r', 9, 0, + /* 11943 */ 'c', 'g', 'e', 'r', 9, 0, + /* 11949 */ 'b', 'h', 'e', 'r', 9, 0, + /* 11955 */ 'b', 'n', 'h', 'e', 'r', 9, 0, + /* 11962 */ 'f', 'i', 'e', 'r', 9, 0, + /* 11968 */ 'b', 'l', 'e', 'r', 9, 0, + /* 11974 */ 'b', 'n', 'l', 'e', 'r', 9, 0, + /* 11981 */ 'm', 'e', 'r', 9, 0, + /* 11986 */ 'b', 'n', 'e', 'r', 9, 0, + /* 11992 */ 'l', 'n', 'e', 'r', 9, 0, + /* 11998 */ 'l', 'p', 'e', 'r', 9, 0, + /* 12004 */ 's', 'q', 'e', 'r', 9, 0, + /* 12010 */ 'l', 'r', 'e', 'r', 9, 0, + /* 12016 */ 'm', 's', 'e', 'r', 9, 0, + /* 12022 */ 'l', 't', 'e', 'r', 9, 0, + /* 12028 */ 'l', 'x', 'e', 'r', 9, 0, + /* 12034 */ 'l', 'z', 'e', 'r', 9, 0, + /* 12040 */ 'l', 'c', 'd', 'f', 'r', 9, 0, + /* 12047 */ 'l', 'n', 'd', 'f', 'r', 9, 0, + /* 12054 */ 'l', 'p', 'd', 'f', 'r', 9, 0, + /* 12061 */ 'c', 'e', 'f', 'r', 9, 0, + /* 12067 */ 'a', 'g', 'f', 'r', 9, 0, + /* 12073 */ 'l', 'c', 'g', 'f', 'r', 9, 0, + /* 12080 */ 'a', 'l', 'g', 'f', 'r', 9, 0, + /* 12087 */ 'c', 'l', 'g', 'f', 'r', 9, 0, + /* 12094 */ 'l', 'l', 'g', 'f', 'r', 9, 0, + /* 12101 */ 's', 'l', 'g', 'f', 'r', 9, 0, + /* 12108 */ 'l', 'n', 'g', 'f', 'r', 9, 0, + /* 12115 */ 'l', 'p', 'g', 'f', 'r', 9, 0, + /* 12122 */ 'd', 's', 'g', 'f', 'r', 9, 0, + /* 12129 */ 'm', 's', 'g', 'f', 'r', 9, 0, + /* 12136 */ 'l', 't', 'g', 'f', 'r', 9, 0, + /* 12143 */ 'c', 'x', 'f', 'r', 9, 0, + /* 12149 */ 'a', 'g', 'r', 9, 0, + /* 12154 */ 's', 'l', 'b', 'g', 'r', 9, 0, + /* 12161 */ 'a', 'l', 'c', 'g', 'r', 9, 0, + /* 12168 */ 'l', 'o', 'c', 'g', 'r', 9, 0, + /* 12175 */ 'c', 'd', 'g', 'r', 9, 0, + /* 12181 */ 'l', 'd', 'g', 'r', 9, 0, + /* 12187 */ 'c', 'e', 'g', 'r', 9, 0, + /* 12193 */ 'a', 'l', 'g', 'r', 9, 0, + /* 12199 */ 'c', 'l', 'g', 'r', 9, 0, + /* 12205 */ 'd', 'l', 'g', 'r', 9, 0, + /* 12211 */ 'm', 'l', 'g', 'r', 9, 0, + /* 12217 */ 's', 'l', 'g', 'r', 9, 0, + /* 12223 */ 'l', 'n', 'g', 'r', 9, 0, + /* 12229 */ 'f', 'l', 'o', 'g', 'r', 9, 0, + /* 12236 */ 'l', 'p', 'g', 'r', 9, 0, + /* 12242 */ 'd', 's', 'g', 'r', 9, 0, + /* 12248 */ 'm', 's', 'g', 'r', 9, 0, + /* 12254 */ 'b', 'c', 't', 'g', 'r', 9, 0, + /* 12261 */ 'l', 't', 'g', 'r', 9, 0, + /* 12267 */ 'l', 'r', 'v', 'g', 'r', 9, 0, + /* 12274 */ 'c', 'x', 'g', 'r', 9, 0, + /* 12280 */ 'b', 'h', 'r', 9, 0, + /* 12285 */ 'l', 'o', 'c', 'f', 'h', 'r', 9, 0, + /* 12293 */ 'l', 'l', 'g', 'h', 'r', 9, 0, + /* 12300 */ 'c', 'h', 'h', 'r', 9, 0, + /* 12306 */ 'a', 'h', 'h', 'h', 'r', 9, 0, + /* 12313 */ 'a', 'l', 'h', 'h', 'h', 'r', 9, 0, + /* 12321 */ 's', 'l', 'h', 'h', 'h', 'r', 9, 0, + /* 12329 */ 's', 'h', 'h', 'h', 'r', 9, 0, + /* 12336 */ 'c', 'l', 'h', 'h', 'r', 9, 0, + /* 12343 */ 'b', 'l', 'h', 'r', 9, 0, + /* 12349 */ 'l', 'l', 'h', 'r', 9, 0, + /* 12355 */ 'b', 'n', 'l', 'h', 'r', 9, 0, + /* 12362 */ 'b', 'n', 'h', 'r', 9, 0, + /* 12368 */ 'm', 'a', 'y', 'h', 'r', 9, 0, + /* 12375 */ 'm', 'y', 'h', 'r', 9, 0, + /* 12381 */ 'e', 'p', 'a', 'i', 'r', 9, 0, + /* 12388 */ 'e', 's', 'a', 'i', 'r', 9, 0, + /* 12395 */ 's', 's', 'a', 'i', 'r', 9, 0, + /* 12402 */ 'b', 'a', 'k', 'r', 9, 0, + /* 12408 */ 'b', 'a', 'l', 'r', 9, 0, + /* 12414 */ 'b', 'l', 'r', 9, 0, + /* 12419 */ 'c', 'l', 'r', 9, 0, + /* 12424 */ 'd', 'l', 'r', 9, 0, + /* 12429 */ 'v', 'f', 'l', 'r', 9, 0, + /* 12435 */ 'c', 'h', 'l', 'r', 9, 0, + /* 12441 */ 'a', 'h', 'h', 'l', 'r', 9, 0, + /* 12448 */ 'a', 'l', 'h', 'h', 'l', 'r', 9, 0, + /* 12456 */ 's', 'l', 'h', 'h', 'l', 'r', 9, 0, + /* 12464 */ 's', 'h', 'h', 'l', 'r', 9, 0, + /* 12471 */ 'c', 'l', 'h', 'l', 'r', 9, 0, + /* 12478 */ 'm', 'l', 'r', 9, 0, + /* 12483 */ 'b', 'n', 'l', 'r', 9, 0, + /* 12489 */ 'v', 'l', 'r', 'l', 'r', 9, 0, + /* 12496 */ 'v', 's', 't', 'r', 'l', 'r', 9, 0, + /* 12504 */ 's', 'l', 'r', 9, 0, + /* 12509 */ 'v', 'l', 'r', 9, 0, + /* 12514 */ 'm', 'a', 'y', 'l', 'r', 9, 0, + /* 12521 */ 'm', 'y', 'l', 'r', 9, 0, + /* 12527 */ 'b', 'm', 'r', 9, 0, + /* 12532 */ 'b', 'n', 'm', 'r', 9, 0, + /* 12538 */ 'l', 'n', 'r', 9, 0, + /* 12543 */ 'b', 'o', 'r', 9, 0, + /* 12548 */ 'b', 'n', 'o', 'r', 9, 0, + /* 12554 */ 'b', 'p', 'r', 9, 0, + /* 12559 */ 'l', 'p', 'r', 9, 0, + /* 12564 */ 'b', 'n', 'p', 'r', 9, 0, + /* 12570 */ 'b', 'a', 's', 'r', 9, 0, + /* 12576 */ 's', 'f', 'a', 's', 'r', 9, 0, + /* 12583 */ 'm', 's', 'r', 9, 0, + /* 12588 */ 'b', 'c', 't', 'r', 9, 0, + /* 12594 */ 'e', 'c', 'c', 't', 'r', 9, 0, + /* 12601 */ 's', 'c', 'c', 't', 'r', 9, 0, + /* 12608 */ 'k', 'm', 'c', 't', 'r', 9, 0, + /* 12615 */ 'e', 'p', 'c', 't', 'r', 9, 0, + /* 12622 */ 's', 'p', 'c', 't', 'r', 9, 0, + /* 12629 */ 'q', 'a', 'd', 't', 'r', 9, 0, + /* 12636 */ 'c', 'd', 't', 'r', 9, 0, + /* 12642 */ 'd', 'd', 't', 'r', 9, 0, + /* 12648 */ 'c', 'e', 'd', 't', 'r', 9, 0, + /* 12655 */ 'e', 'e', 'd', 't', 'r', 9, 0, + /* 12662 */ 'i', 'e', 'd', 't', 'r', 9, 0, + /* 12669 */ 'l', 'e', 'd', 't', 'r', 9, 0, + /* 12676 */ 'c', 'f', 'd', 't', 'r', 9, 0, + /* 12683 */ 'c', 'l', 'f', 'd', 't', 'r', 9, 0, + /* 12691 */ 'c', 'g', 'd', 't', 'r', 9, 0, + /* 12698 */ 'c', 'l', 'g', 'd', 't', 'r', 9, 0, + /* 12706 */ 'f', 'i', 'd', 't', 'r', 9, 0, + /* 12713 */ 'k', 'd', 't', 'r', 9, 0, + /* 12719 */ 'm', 'd', 't', 'r', 9, 0, + /* 12725 */ 'r', 'r', 'd', 't', 'r', 9, 0, + /* 12732 */ 'c', 's', 'd', 't', 'r', 9, 0, + /* 12739 */ 'e', 's', 'd', 't', 'r', 9, 0, + /* 12746 */ 'l', 't', 'd', 't', 'r', 9, 0, + /* 12753 */ 'c', 'u', 'd', 't', 'r', 9, 0, + /* 12760 */ 'l', 'x', 'd', 't', 'r', 9, 0, + /* 12767 */ 'l', 'd', 'e', 't', 'r', 9, 0, + /* 12774 */ 'c', 'd', 'f', 't', 'r', 9, 0, + /* 12781 */ 'c', 'd', 'l', 'f', 't', 'r', 9, 0, + /* 12789 */ 'c', 'x', 'l', 'f', 't', 'r', 9, 0, + /* 12797 */ 'c', 'x', 'f', 't', 'r', 9, 0, + /* 12804 */ 'c', 'd', 'g', 't', 'r', 9, 0, + /* 12811 */ 'c', 'd', 'l', 'g', 't', 'r', 9, 0, + /* 12819 */ 'l', 'l', 'g', 't', 'r', 9, 0, + /* 12826 */ 'c', 'x', 'l', 'g', 't', 'r', 9, 0, + /* 12834 */ 'c', 'x', 'g', 't', 'r', 9, 0, + /* 12841 */ 'l', 't', 'r', 9, 0, + /* 12846 */ 't', 'r', 't', 'r', 9, 0, + /* 12852 */ 'c', 'd', 's', 't', 'r', 9, 0, + /* 12859 */ 'v', 'i', 's', 't', 'r', 9, 0, + /* 12866 */ 'c', 'x', 's', 't', 'r', 9, 0, + /* 12873 */ 'c', 'd', 'u', 't', 'r', 9, 0, + /* 12880 */ 'c', 'x', 'u', 't', 'r', 9, 0, + /* 12887 */ 'q', 'a', 'x', 't', 'r', 9, 0, + /* 12894 */ 'c', 'x', 't', 'r', 9, 0, + /* 12900 */ 'l', 'd', 'x', 't', 'r', 9, 0, + /* 12907 */ 'c', 'e', 'x', 't', 'r', 9, 0, + /* 12914 */ 'e', 'e', 'x', 't', 'r', 9, 0, + /* 12921 */ 'i', 'e', 'x', 't', 'r', 9, 0, + /* 12928 */ 'c', 'f', 'x', 't', 'r', 9, 0, + /* 12935 */ 'c', 'l', 'f', 'x', 't', 'r', 9, 0, + /* 12943 */ 'c', 'g', 'x', 't', 'r', 9, 0, + /* 12950 */ 'c', 'l', 'g', 'x', 't', 'r', 9, 0, + /* 12958 */ 'f', 'i', 'x', 't', 'r', 9, 0, + /* 12965 */ 'k', 'x', 't', 'r', 9, 0, + /* 12971 */ 'm', 'x', 't', 'r', 9, 0, + /* 12977 */ 'r', 'r', 'x', 't', 'r', 9, 0, + /* 12984 */ 'c', 's', 'x', 't', 'r', 9, 0, + /* 12991 */ 'e', 's', 'x', 't', 'r', 9, 0, + /* 12998 */ 'l', 't', 'x', 't', 'r', 9, 0, + /* 13005 */ 'c', 'u', 'x', 't', 'r', 9, 0, + /* 13012 */ 'a', 'u', 'r', 9, 0, + /* 13017 */ 's', 'u', 'r', 9, 0, + /* 13022 */ 'l', 'r', 'v', 'r', 9, 0, + /* 13028 */ 'a', 'w', 'r', 9, 0, + /* 13033 */ 's', 'w', 'r', 9, 0, + /* 13038 */ 'a', 'x', 'r', 9, 0, + /* 13043 */ 'l', 'c', 'x', 'r', 9, 0, + /* 13049 */ 'l', 'd', 'x', 'r', 9, 0, + /* 13055 */ 'l', 'e', 'x', 'r', 9, 0, + /* 13061 */ 'c', 'f', 'x', 'r', 9, 0, + /* 13067 */ 'c', 'g', 'x', 'r', 9, 0, + /* 13073 */ 'f', 'i', 'x', 'r', 9, 0, + /* 13079 */ 'l', 'x', 'r', 9, 0, + /* 13084 */ 'm', 'x', 'r', 9, 0, + /* 13089 */ 'l', 'n', 'x', 'r', 9, 0, + /* 13095 */ 'l', 'p', 'x', 'r', 9, 0, + /* 13101 */ 's', 'q', 'x', 'r', 9, 0, + /* 13107 */ 's', 'x', 'r', 9, 0, + /* 13112 */ 'l', 't', 'x', 'r', 9, 0, + /* 13118 */ 'l', 'z', 'x', 'r', 9, 0, + /* 13124 */ 'm', 'a', 'y', 'r', 9, 0, + /* 13130 */ 'm', 'y', 'r', 9, 0, + /* 13135 */ 'b', 'z', 'r', 9, 0, + /* 13140 */ 'b', 'n', 'z', 'r', 9, 0, + /* 13146 */ 'b', 'a', 's', 9, 0, + /* 13151 */ 'l', 'f', 'a', 's', 9, 0, + /* 13157 */ 'b', 'r', 'a', 's', 9, 0, + /* 13163 */ 'v', 's', 't', 'r', 'c', 'b', 's', 9, 0, + /* 13172 */ 'v', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, + /* 13181 */ 'w', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, + /* 13190 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, + /* 13200 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, + /* 13210 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, + /* 13220 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, + /* 13230 */ 'v', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, + /* 13239 */ 'w', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, + /* 13248 */ 'v', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, + /* 13257 */ 'w', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, + /* 13266 */ 'v', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, + /* 13275 */ 'w', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, + /* 13284 */ 'v', 'f', 'a', 'e', 'b', 's', 9, 0, + /* 13292 */ 'v', 'f', 'e', 'e', 'b', 's', 9, 0, + /* 13300 */ 'v', 'f', 'e', 'n', 'e', 'b', 's', 9, 0, + /* 13309 */ 'v', 'c', 'h', 'b', 's', 9, 0, + /* 13316 */ 'v', 'c', 'h', 'l', 'b', 's', 9, 0, + /* 13324 */ 'v', 'c', 'e', 'q', 'b', 's', 9, 0, + /* 13332 */ 'v', 'i', 's', 't', 'r', 'b', 's', 9, 0, + /* 13341 */ 'v', 'f', 'c', 'e', 's', 'b', 's', 9, 0, + /* 13350 */ 'w', 'f', 'c', 'e', 's', 'b', 's', 9, 0, + /* 13359 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, + /* 13369 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, + /* 13379 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, + /* 13389 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, + /* 13399 */ 'v', 'f', 'k', 'e', 's', 'b', 's', 9, 0, + /* 13408 */ 'w', 'f', 'k', 'e', 's', 'b', 's', 9, 0, + /* 13417 */ 'v', 'f', 'c', 'h', 's', 'b', 's', 9, 0, + /* 13426 */ 'w', 'f', 'c', 'h', 's', 'b', 's', 9, 0, + /* 13435 */ 'v', 'f', 'k', 'h', 's', 'b', 's', 9, 0, + /* 13444 */ 'w', 'f', 'k', 'h', 's', 'b', 's', 9, 0, + /* 13453 */ 'w', 'f', 'c', 'e', 'x', 'b', 's', 9, 0, + /* 13462 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 's', 9, 0, + /* 13472 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 's', 9, 0, + /* 13482 */ 'w', 'f', 'k', 'e', 'x', 'b', 's', 9, 0, + /* 13491 */ 'w', 'f', 'c', 'h', 'x', 'b', 's', 9, 0, + /* 13500 */ 'w', 'f', 'k', 'h', 'x', 'b', 's', 9, 0, + /* 13509 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 's', 9, 0, + /* 13519 */ 'v', 'f', 'a', 'e', 'z', 'b', 's', 9, 0, + /* 13528 */ 'v', 'f', 'e', 'e', 'z', 'b', 's', 9, 0, + /* 13537 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 's', 9, 0, + /* 13547 */ 'm', 'v', 'c', 's', 9, 0, + /* 13553 */ 'c', 'd', 's', 9, 0, + /* 13558 */ 'v', 's', 't', 'r', 'c', 'f', 's', 9, 0, + /* 13567 */ 'v', 'f', 'a', 'e', 'f', 's', 9, 0, + /* 13575 */ 'v', 'f', 'e', 'e', 'f', 's', 9, 0, + /* 13583 */ 'v', 'f', 'e', 'n', 'e', 'f', 's', 9, 0, + /* 13592 */ 'v', 'c', 'h', 'f', 's', 9, 0, + /* 13599 */ 'v', 'c', 'h', 'l', 'f', 's', 9, 0, + /* 13607 */ 'v', 'c', 'e', 'q', 'f', 's', 9, 0, + /* 13615 */ 'v', 'i', 's', 't', 'r', 'f', 's', 9, 0, + /* 13624 */ 'v', 'p', 'k', 's', 'f', 's', 9, 0, + /* 13632 */ 'v', 'p', 'k', 'l', 's', 'f', 's', 9, 0, + /* 13641 */ 'v', 'f', 's', 9, 0, + /* 13646 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 's', 9, 0, + /* 13656 */ 'v', 'f', 'a', 'e', 'z', 'f', 's', 9, 0, + /* 13665 */ 'v', 'f', 'e', 'e', 'z', 'f', 's', 9, 0, + /* 13674 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 's', 9, 0, + /* 13684 */ 'v', 'c', 'h', 'g', 's', 9, 0, + /* 13691 */ 'v', 'c', 'h', 'l', 'g', 's', 9, 0, + /* 13699 */ 'v', 'c', 'e', 'q', 'g', 's', 9, 0, + /* 13707 */ 'v', 'p', 'k', 's', 'g', 's', 9, 0, + /* 13715 */ 'v', 'p', 'k', 'l', 's', 'g', 's', 9, 0, + /* 13724 */ 'v', 's', 't', 'r', 'c', 'h', 's', 9, 0, + /* 13733 */ 'v', 'f', 'a', 'e', 'h', 's', 9, 0, + /* 13741 */ 'v', 'f', 'e', 'e', 'h', 's', 9, 0, + /* 13749 */ 'v', 'f', 'e', 'n', 'e', 'h', 's', 9, 0, + /* 13758 */ 'v', 'c', 'h', 'h', 's', 9, 0, + /* 13765 */ 'v', 'c', 'h', 'l', 'h', 's', 9, 0, + /* 13773 */ 'v', 'c', 'e', 'q', 'h', 's', 9, 0, + /* 13781 */ 'v', 'i', 's', 't', 'r', 'h', 's', 9, 0, + /* 13790 */ 'v', 'p', 'k', 's', 'h', 's', 9, 0, + /* 13798 */ 'v', 'p', 'k', 'l', 's', 'h', 's', 9, 0, + /* 13807 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 's', 9, 0, + /* 13817 */ 'v', 'f', 'a', 'e', 'z', 'h', 's', 9, 0, + /* 13826 */ 'v', 'f', 'e', 'e', 'z', 'h', 's', 9, 0, + /* 13835 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 's', 9, 0, + /* 13845 */ 'v', 'p', 'k', 's', 9, 0, + /* 13851 */ 'v', 'p', 'k', 'l', 's', 9, 0, + /* 13858 */ 'v', 'f', 'l', 'l', 's', 9, 0, + /* 13865 */ 'w', 'f', 'l', 'l', 's', 9, 0, + /* 13872 */ 'v', 'f', 'm', 's', 9, 0, + /* 13878 */ 'v', 'f', 'n', 'm', 's', 9, 0, + /* 13885 */ 'm', 'v', 'c', 'o', 's', 9, 0, + /* 13892 */ 's', 't', 'c', 'p', 's', 9, 0, + /* 13899 */ 't', 's', 9, 0, + /* 13903 */ 'v', 's', 9, 0, + /* 13907 */ 'l', 'l', 'g', 'f', 'a', 't', 9, 0, + /* 13915 */ 'l', 'g', 'a', 't', 9, 0, + /* 13921 */ 'l', 'f', 'h', 'a', 't', 9, 0, + /* 13928 */ 'l', 'a', 't', 9, 0, + /* 13933 */ 'l', 'l', 'g', 't', 'a', 't', 9, 0, + /* 13941 */ 'b', 'c', 't', 9, 0, + /* 13946 */ 'v', 'p', 'o', 'p', 'c', 't', 9, 0, + /* 13954 */ 'b', 'r', 'c', 't', 9, 0, + /* 13960 */ 't', 'd', 'c', 'd', 't', 9, 0, + /* 13967 */ 't', 'd', 'g', 'd', 't', 9, 0, + /* 13974 */ 's', 'l', 'd', 't', 9, 0, + /* 13980 */ 'c', 'p', 'd', 't', 9, 0, + /* 13986 */ 's', 'r', 'd', 't', 9, 0, + /* 13992 */ 'c', 'z', 'd', 't', 9, 0, + /* 13998 */ 't', 'd', 'c', 'e', 't', 9, 0, + /* 14005 */ 't', 'd', 'g', 'e', 't', 9, 0, + /* 14012 */ 'c', 'l', 'g', 't', 9, 0, + /* 14018 */ 'l', 'l', 'g', 't', 9, 0, + /* 14024 */ 'c', 'i', 't', 9, 0, + /* 14029 */ 'c', 'l', 'f', 'i', 't', 9, 0, + /* 14036 */ 'c', 'g', 'i', 't', 9, 0, + /* 14042 */ 'c', 'l', 'g', 'i', 't', 9, 0, + /* 14049 */ 'c', 'l', 't', 9, 0, + /* 14054 */ 's', 'r', 'n', 'm', 't', 9, 0, + /* 14061 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, + /* 14069 */ 't', 'p', 'r', 'o', 't', 9, 0, + /* 14076 */ 't', 'r', 'o', 't', 9, 0, + /* 14082 */ 'c', 'd', 'p', 't', 9, 0, + /* 14088 */ 's', 'p', 't', 9, 0, + /* 14093 */ 's', 't', 'p', 't', 9, 0, + /* 14099 */ 'c', 'x', 'p', 't', 9, 0, + /* 14105 */ 'c', 'r', 't', 9, 0, + /* 14110 */ 'c', 'g', 'r', 't', 9, 0, + /* 14116 */ 'c', 'l', 'g', 'r', 't', 9, 0, + /* 14123 */ 'c', 'l', 'r', 't', 9, 0, + /* 14129 */ 't', 'a', 'b', 'o', 'r', 't', 9, 0, + /* 14137 */ 't', 'r', 't', 9, 0, + /* 14142 */ 'c', 'l', 's', 't', 9, 0, + /* 14148 */ 's', 'r', 's', 't', 9, 0, + /* 14154 */ 'c', 's', 's', 't', 9, 0, + /* 14160 */ 'm', 'v', 's', 't', 9, 0, + /* 14166 */ 't', 'r', 't', 't', 9, 0, + /* 14172 */ 'p', 'g', 'o', 'u', 't', 9, 0, + /* 14179 */ 't', 'd', 'c', 'x', 't', 9, 0, + /* 14186 */ 't', 'd', 'g', 'x', 't', 9, 0, + /* 14193 */ 's', 'l', 'x', 't', 9, 0, + /* 14199 */ 'c', 'p', 'x', 't', 9, 0, + /* 14205 */ 's', 'r', 'x', 't', 9, 0, + /* 14211 */ 'c', 'z', 'x', 't', 9, 0, + /* 14217 */ 'c', 'd', 'z', 't', 9, 0, + /* 14223 */ 'c', 'x', 'z', 't', 9, 0, + /* 14229 */ 'a', 'u', 9, 0, + /* 14233 */ 'c', 'u', 't', 'f', 'u', 9, 0, + /* 14240 */ 'u', 'n', 'p', 'k', 'u', 9, 0, + /* 14247 */ 'c', 'l', 'c', 'l', 'u', 9, 0, + /* 14254 */ 'm', 'v', 'c', 'l', 'u', 9, 0, + /* 14261 */ 's', 'u', 9, 0, + /* 14265 */ 's', 'r', 's', 't', 'u', 9, 0, + /* 14272 */ 'v', 'e', 's', 'r', 'a', 'v', 9, 0, + /* 14280 */ 'v', 'l', 'g', 'v', 9, 0, + /* 14286 */ 'v', 'e', 'r', 'l', 'l', 'v', 9, 0, + /* 14294 */ 'v', 'e', 's', 'r', 'l', 'v', 9, 0, + /* 14302 */ 'v', 'e', 's', 'l', 'v', 9, 0, + /* 14309 */ 'l', 'r', 'v', 9, 0, + /* 14314 */ 's', 't', 'r', 'v', 9, 0, + /* 14320 */ 'a', 'w', 9, 0, + /* 14324 */ 'v', 'm', 'a', 'l', 'h', 'w', 9, 0, + /* 14332 */ 'v', 'm', 'l', 'h', 'w', 9, 0, + /* 14339 */ 'v', 'u', 'p', 'l', 'h', 'w', 9, 0, + /* 14347 */ 's', 't', 'c', 'r', 'w', 9, 0, + /* 14354 */ 'e', 'p', 's', 'w', 9, 0, + /* 14360 */ 'l', 'p', 's', 'w', 9, 0, + /* 14366 */ 'l', 'a', 'x', 9, 0, + /* 14371 */ 'v', 'f', 'm', 'a', 'x', 9, 0, + /* 14378 */ 'e', 'x', 9, 0, + /* 14382 */ 'v', 'm', 'x', 9, 0, + /* 14387 */ 'v', 'n', 'x', 9, 0, + /* 14392 */ 's', 'p', 'x', 9, 0, + /* 14397 */ 's', 't', 'p', 'x', 9, 0, + /* 14403 */ 'w', 'f', 'l', 'r', 'x', 9, 0, + /* 14410 */ 'v', 'x', 9, 0, + /* 14414 */ 'l', 'a', 'y', 9, 0, + /* 14419 */ 'm', 'a', 'y', 9, 0, + /* 14424 */ 'l', 'r', 'a', 'y', 9, 0, + /* 14430 */ 'c', 'v', 'b', 'y', 9, 0, + /* 14436 */ 'i', 'c', 'y', 9, 0, + /* 14441 */ 's', 't', 'c', 'y', 9, 0, + /* 14447 */ 'l', 'd', 'y', 9, 0, + /* 14452 */ 's', 't', 'd', 'y', 9, 0, + /* 14458 */ 'c', 'v', 'd', 'y', 9, 0, + /* 14464 */ 'l', 'a', 'e', 'y', 9, 0, + /* 14470 */ 'l', 'e', 'y', 9, 0, + /* 14475 */ 's', 't', 'e', 'y', 9, 0, + /* 14481 */ 'm', 'f', 'y', 9, 0, + /* 14486 */ 'a', 'h', 'y', 9, 0, + /* 14491 */ 'c', 'h', 'y', 9, 0, + /* 14496 */ 'l', 'h', 'y', 9, 0, + /* 14501 */ 'm', 'h', 'y', 9, 0, + /* 14506 */ 's', 'h', 'y', 9, 0, + /* 14511 */ 's', 't', 'h', 'y', 9, 0, + /* 14517 */ 'c', 'l', 'i', 'y', 9, 0, + /* 14523 */ 'n', 'i', 'y', 9, 0, + /* 14528 */ 'o', 'i', 'y', 9, 0, + /* 14533 */ 'm', 'v', 'i', 'y', 9, 0, + /* 14539 */ 'x', 'i', 'y', 9, 0, + /* 14544 */ 'a', 'l', 'y', 9, 0, + /* 14549 */ 'c', 'l', 'y', 9, 0, + /* 14554 */ 's', 'l', 'y', 9, 0, + /* 14559 */ 'l', 'a', 'm', 'y', 9, 0, + /* 14565 */ 's', 't', 'a', 'm', 'y', 9, 0, + /* 14572 */ 'i', 'c', 'm', 'y', 9, 0, + /* 14578 */ 's', 't', 'c', 'm', 'y', 9, 0, + /* 14585 */ 'c', 'l', 'm', 'y', 9, 0, + /* 14591 */ 's', 't', 'm', 'y', 9, 0, + /* 14597 */ 'n', 'y', 9, 0, + /* 14601 */ 'o', 'y', 9, 0, + /* 14605 */ 'c', 's', 'y', 9, 0, + /* 14610 */ 'c', 'd', 's', 'y', 9, 0, + /* 14616 */ 'm', 's', 'y', 9, 0, + /* 14621 */ 's', 't', 'y', 9, 0, + /* 14626 */ 'x', 'y', 9, 0, + /* 14630 */ 'b', 'z', 9, 0, + /* 14634 */ 'l', 'o', 'c', 'z', 9, 0, + /* 14640 */ 's', 't', 'o', 'c', 'z', 9, 0, + /* 14647 */ 'v', 'l', 'l', 'e', 'z', 9, 0, + /* 14654 */ 'l', 'o', 'c', 'g', 'z', 9, 0, + /* 14661 */ 's', 't', 'o', 'c', 'g', 'z', 9, 0, + /* 14669 */ 'j', 'g', 'z', 9, 0, + /* 14674 */ 'l', 'o', 'c', 'f', 'h', 'z', 9, 0, + /* 14682 */ 's', 't', 'o', 'c', 'f', 'h', 'z', 9, 0, + /* 14691 */ 'b', 'i', 'z', 9, 0, + /* 14696 */ 'l', 'o', 'c', 'h', 'i', 'z', 9, 0, + /* 14704 */ 'l', 'o', 'c', 'g', 'h', 'i', 'z', 9, 0, + /* 14713 */ 'l', 'o', 'c', 'h', 'h', 'i', 'z', 9, 0, + /* 14722 */ 'j', 'z', 9, 0, + /* 14726 */ 'v', 'u', 'p', 'k', 'z', 9, 0, + /* 14733 */ 'v', 'p', 'k', 'z', 9, 0, + /* 14739 */ 'v', 'c', 'l', 'z', 9, 0, + /* 14745 */ 'b', 'n', 'z', 9, 0, + /* 14750 */ 'l', 'o', 'c', 'n', 'z', 9, 0, + /* 14757 */ 's', 't', 'o', 'c', 'n', 'z', 9, 0, + /* 14765 */ 'l', 'o', 'c', 'g', 'n', 'z', 9, 0, + /* 14773 */ 's', 't', 'o', 'c', 'g', 'n', 'z', 9, 0, + /* 14782 */ 'j', 'g', 'n', 'z', 9, 0, + /* 14788 */ 'l', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, + /* 14797 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, + /* 14807 */ 'b', 'i', 'n', 'z', 9, 0, + /* 14813 */ 'l', 'o', 'c', 'h', 'i', 'n', 'z', 9, 0, + /* 14822 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'z', 9, 0, + /* 14832 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'z', 9, 0, + /* 14842 */ 'j', 'n', 'z', 9, 0, + /* 14847 */ 'l', 'o', 'c', 'r', 'n', 'z', 9, 0, + /* 14855 */ 'l', 'o', 'c', 'g', 'r', 'n', 'z', 9, 0, + /* 14864 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'z', 9, 0, + /* 14874 */ 'l', 'o', 'c', 'r', 'z', 9, 0, + /* 14881 */ 'l', 'o', 'c', 'g', 'r', 'z', 9, 0, + /* 14889 */ 'l', 'o', 'c', 'f', 'h', 'r', 'z', 9, 0, + /* 14898 */ 'v', 'c', 't', 'z', 9, 0, + /* 14904 */ 'm', 'v', 'z', 9, 0, + /* 14909 */ '.', 'i', 'n', 's', 'n', 32, 'e', ',', 0, + /* 14918 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'e', ',', 0, + /* 14929 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'e', ',', 0, + /* 14940 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'e', ',', 0, + /* 14951 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'e', ',', 0, + /* 14962 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'e', ',', 0, + /* 14973 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'f', ',', 0, + /* 14984 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'f', ',', 0, + /* 14995 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'f', ',', 0, + /* 15006 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', ',', 0, + /* 15016 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', ',', 0, + /* 15026 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'i', ',', 0, + /* 15037 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', ',', 0, + /* 15048 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'l', ',', 0, + /* 15059 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', ',', 0, + /* 15069 */ '.', 'i', 'n', 's', 'n', 32, 's', ',', 0, + /* 15078 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 's', ',', 0, + /* 15089 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', ',', 0, + /* 15099 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 's', ',', 0, + /* 15110 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', ',', 0, + /* 15120 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', 'u', ',', 0, + /* 15132 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', ',', 0, + /* 15142 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'y', ',', 0, + /* 15153 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'y', ',', 0, + /* 15164 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'y', ',', 0, + /* 15175 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 15206 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 15230 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 15255 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 15278 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 15301 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 15323 */ 's', 'a', 'm', '3', '1', 0, + /* 15329 */ 't', 'r', 'a', 'p', '2', 0, + /* 15335 */ 's', 'a', 'm', '2', '4', 0, + /* 15341 */ 's', 'a', 'm', '6', '4', 0, + /* 15347 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 15360 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 15367 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 15377 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 15387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 15402 */ 'c', 'i', 'b', 0, + /* 15406 */ 'c', 'g', 'i', 'b', 0, + /* 15411 */ 'c', 'l', 'g', 'i', 'b', 0, + /* 15417 */ 'c', 'l', 'i', 'b', 0, + /* 15422 */ 'p', 'a', 'l', 'b', 0, + /* 15427 */ 'p', 't', 'l', 'b', 0, + /* 15432 */ 'c', 'r', 'b', 0, + /* 15436 */ 'c', 'g', 'r', 'b', 0, + /* 15441 */ 'c', 'l', 'g', 'r', 'b', 0, + /* 15447 */ 'c', 'l', 'r', 'b', 0, + /* 15452 */ 'p', 'c', 'c', 0, + /* 15456 */ 'l', 'o', 'c', 0, + /* 15460 */ 's', 't', 'o', 'c', 0, + /* 15465 */ 't', 'e', 'n', 'd', 0, + /* 15470 */ 'p', 't', 'f', 'f', 0, + /* 15475 */ 's', 'c', 'k', 'p', 'f', 0, + /* 15481 */ 'l', 'o', 'c', 'g', 0, + /* 15486 */ 's', 't', 'o', 'c', 'g', 0, + /* 15492 */ 'j', 'g', 0, + /* 15495 */ 'c', 's', 'c', 'h', 0, + /* 15500 */ 'h', 's', 'c', 'h', 0, + /* 15505 */ 'r', 's', 'c', 'h', 0, + /* 15510 */ 'x', 's', 'c', 'h', 0, + /* 15515 */ 'l', 'o', 'c', 'f', 'h', 0, + /* 15521 */ 's', 't', 'o', 'c', 'f', 'h', 0, + /* 15528 */ 'b', 'i', 0, + /* 15531 */ 'l', 'o', 'c', 'h', 'i', 0, + /* 15537 */ 'l', 'o', 'c', 'g', 'h', 'i', 0, + /* 15544 */ 'l', 'o', 'c', 'h', 'h', 'i', 0, + /* 15551 */ 'c', 'i', 'j', 0, + /* 15555 */ 'c', 'g', 'i', 'j', 0, + /* 15560 */ 'c', 'l', 'g', 'i', 'j', 0, + /* 15566 */ 'c', 'l', 'i', 'j', 0, + /* 15571 */ 'c', 'r', 'j', 0, + /* 15575 */ 'c', 'g', 'r', 'j', 0, + /* 15580 */ 'c', 'l', 'g', 'r', 'j', 0, + /* 15586 */ 'c', 'l', 'r', 'j', 0, + /* 15591 */ 'i', 'p', 'k', 0, + /* 15595 */ 's', 'a', 'l', 0, + /* 15599 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 15613 */ 't', 'a', 'm', 0, + /* 15617 */ 's', 'c', 'h', 'm', 0, + /* 15622 */ 'p', 'c', 'k', 'm', 'o', 0, + /* 15628 */ 'p', 'f', 'p', 'o', 0, + /* 15633 */ 'r', 'c', 'h', 'p', 0, + /* 15638 */ 'l', 'o', 'c', 'r', 0, + /* 15643 */ 'l', 'o', 'c', 'g', 'r', 0, + /* 15649 */ 'l', 'o', 'c', 'f', 'h', 'r', 0, + /* 15656 */ 'p', 'r', 0, + /* 15659 */ 'c', 'l', 'g', 't', 0, + /* 15664 */ 'c', 'i', 't', 0, + /* 15668 */ 'c', 'l', 'f', 'i', 't', 0, + /* 15674 */ 'c', 'g', 'i', 't', 0, + /* 15679 */ 'c', 'l', 'g', 'i', 't', 0, + /* 15685 */ 'c', 'l', 't', 0, + /* 15689 */ 'u', 'p', 't', 0, + /* 15693 */ 'c', 'r', 't', 0, + /* 15697 */ 'c', 'g', 'r', 't', 0, + /* 15702 */ 'c', 'l', 'g', 'r', 't', 0, + /* 15708 */ 'c', 'l', 'r', 't', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 15368U, // DBG_VALUE + 15378U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 15361U, // BUNDLE + 15388U, // LIFETIME_START + 15348U, // LIFETIME_END + 0U, // STACKMAP + 15600U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 15256U, // PATCHABLE_FUNCTION_ENTER + 15176U, // PATCHABLE_RET + 15302U, // PATCHABLE_FUNCTION_EXIT + 15279U, // PATCHABLE_TAIL_CALL + 15231U, // PATCHABLE_EVENT_CALL + 15207U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 16430U, // A + 18800U, // AD + 16883U, // ADB + 16804865U, // ADBR + 16805360U, // ADR + 1107325271U, // ADTR + 1107312942U, // ADTRA + 18918U, // AE + 17340U, // AEB + 16804997U, // AEBR + 16805497U, // AER + 50356445U, // AFI + 21882U, // AG + 21267U, // AGF + 50356455U, // AGFI + 16805668U, // AGFR + 22882U, // AGH + 67133752U, // AGHI + 1107321434U, // AGHIK + 16805750U, // AGR + 1107321492U, // AGRK + 83927453U, // AGSI + 22627U, // AH + 1107324947U, // AHHHR + 1107325082U, // AHHLR + 67133740U, // AHI + 1107321428U, // AHIK + 30871U, // AHY + 50354711U, // AIH + 25333U, // AL + 18663U, // ALC + 22006U, // ALCG + 16805762U, // ALCGR + 16805341U, // ALCR + 100688143U, // ALFI + 22190U, // ALG + 21284U, // ALGF + 100688115U, // ALGFI + 16805681U, // ALGFR + 1107321441U, // ALGHSIK + 16805794U, // ALGR + 1107321498U, // ALGRK + 83927459U, // ALGSI + 1107324954U, // ALHHHR + 1107325089U, // ALHHLR + 1107321450U, // ALHSIK + 16806010U, // ALR + 1107321542U, // ALRK + 83927510U, // ALSI + 50354776U, // ALSIH + 50358418U, // ALSIHN + 30929U, // ALY + 117500432U, // AP + 16804837U, // AR + 1107321487U, // ARK + 83927448U, // ASI + 30614U, // AU + 16806613U, // AUR + 30705U, // AW + 16806629U, // AWR + 16805219U, // AXBR + 16806639U, // AXR + 1107325529U, // AXTR + 1107312994U, // AXTRA + 30800U, // AY + 65971U, // B + 33583219U, // BAKR + 134243065U, // BAL + 33583225U, // BALR + 134247259U, // BAS + 33583387U, // BASR + 33581165U, // BASSM + 68087U, // BAsmE + 71804U, // BAsmH + 68217U, // BAsmHE + 74502U, // BAsmL + 69053U, // BAsmLE + 72358U, // BAsmLH + 75526U, // BAsmM + 69792U, // BAsmNE + 73228U, // BAsmNH + 68461U, // BAsmNHE + 74853U, // BAsmNL + 69300U, // BAsmNLE + 72653U, // BAsmNLH + 75675U, // BAsmNM + 76101U, // BAsmNO + 76473U, // BAsmNP + 80282U, // BAsmNZ + 75984U, // BAsmO + 76318U, // BAsmP + 80167U, // BAsmZ + 621613U, // BC + 1149082U, // BCAsm + 1670189U, // BCR + 153202129U, // BCRAsm + 30326U, // BCT + 22475U, // BCTG + 16805855U, // BCTGR + 16806189U, // BCTR + 73919U, // BI + 68933U, // BIAsmE + 72223U, // BIAsmH + 68360U, // BIAsmHE + 74698U, // BIAsmL + 69193U, // BIAsmLE + 72499U, // BIAsmLH + 75619U, // BIAsmM + 69918U, // BIAsmNE + 73347U, // BIAsmNH + 68595U, // BIAsmNHE + 74972U, // BIAsmNL + 69434U, // BIAsmNLE + 72787U, // BIAsmNLH + 75737U, // BIAsmNM + 76163U, // BIAsmNO + 76535U, // BIAsmNP + 80344U, // BIAsmNZ + 76038U, // BIAsmO + 76422U, // BIAsmP + 80228U, // BIAsmZ + 621737U, // BIC + 1149126U, // BICAsm + 2317986625U, // BPP + 3391728483U, // BPRP + 3173379U, // BR + 184578918U, // BRAS + 184575582U, // BRASL + 3174014U, // BRAsmE + 3174393U, // BRAsmH + 3174062U, // BRAsmHE + 3174527U, // BRAsmL + 3174081U, // BRAsmLE + 3174456U, // BRAsmLH + 3174640U, // BRAsmM + 3174099U, // BRAsmNE + 3174475U, // BRAsmNH + 3174068U, // BRAsmNHE + 3174596U, // BRAsmNL + 3174087U, // BRAsmNLE + 3174468U, // BRAsmNLH + 3174645U, // BRAsmNM + 3174661U, // BRAsmNO + 3174677U, // BRAsmNP + 3175253U, // BRAsmNZ + 3174656U, // BRAsmO + 3174667U, // BRAsmP + 3175248U, // BRAsmZ + 201948354U, // BRC + 153717047U, // BRCAsm + 201948293U, // BRCL + 153723733U, // BRCLAsm + 201356931U, // BRCT + 201349088U, // BRCTG + 201351128U, // BRCTH + 1090543724U, // BRXH + 1090541188U, // BRXHG + 1090539666U, // BRXLE + 1090541341U, // BRXLG + 33571219U, // BSA + 33576858U, // BSG + 33581139U, // BSM + 1090543713U, // BXH + 1090541182U, // BXHG + 1090539660U, // BXLE + 1090541109U, // BXLEG + 134236295U, // C + 134236532U, // CD + 134234659U, // CDB + 33582088U, // CDBR + 33582339U, // CDFBR + 218120388U, // CDFBRA + 33582858U, // CDFR + 218132967U, // CDFTR + 33582384U, // CDGBR + 218120412U, // CDGBRA + 33582992U, // CDGR + 33583621U, // CDGTR + 218120530U, // CDGTRA + 218131729U, // CDLFBR + 218132974U, // CDLFTR + 218131774U, // CDLGBR + 218133004U, // CDLGTR + 234911491U, // CDPT + 33582588U, // CDR + 1090548978U, // CDS + 1090541476U, // CDSG + 33583669U, // CDSTR + 1090550035U, // CDSY + 33583453U, // CDTR + 33583690U, // CDUTR + 234911626U, // CDZT + 134236726U, // CE + 134235081U, // CEB + 33582220U, // CEBR + 33583465U, // CEDTR + 33582346U, // CEFBR + 218120396U, // CEFBRA + 33582878U, // CEFR + 33582391U, // CEGBR + 218120420U, // CEGBRA + 33583004U, // CEGR + 218131737U, // CELFBR + 218131782U, // CELGBR + 33582724U, // CER + 33583724U, // CEXTR + 3180720U, // CFC + 218131483U, // CFDBR + 218120340U, // CFDBRA + 218131987U, // CFDR + 218132869U, // CFDTR + 218131623U, // CFEBR + 218120364U, // CFEBRA + 218132130U, // CFER + 251683042U, // CFI + 218131838U, // CFXBR + 218120452U, // CFXBRA + 218133254U, // CFXR + 218133121U, // CFXTR + 134239717U, // CG + 218131498U, // CGDBR + 218120348U, // CGDBRA + 218131993U, // CGDR + 218132884U, // CGDTR + 218120508U, // CGDTRA + 218131638U, // CGEBR + 218120372U, // CGEBRA + 218132136U, // CGER + 134239000U, // CGF + 251683053U, // CGFI + 33582891U, // CGFR + 268461514U, // CGFRL + 134240617U, // CGH + 285237568U, // CGHI + 268461574U, // CGHRL + 67150264U, // CGHSI + 305789999U, // CGIB + 1392526511U, // CGIBAsm + 2466269691U, // CGIBAsmE + 2466273408U, // CGIBAsmH + 2466269822U, // CGIBAsmHE + 2466276106U, // CGIBAsmL + 2466270658U, // CGIBAsmLE + 2466273963U, // CGIBAsmLH + 2466271397U, // CGIBAsmNE + 2466274833U, // CGIBAsmNH + 2466270067U, // CGIBAsmNHE + 2466276458U, // CGIBAsmNL + 2466270906U, // CGIBAsmNLE + 2466274259U, // CGIBAsmNLH + 339344580U, // CGIJ + 1392534010U, // CGIJAsm + 3540012399U, // CGIJAsmE + 3540015717U, // CGIJAsmH + 3540011826U, // CGIJAsmHE + 3540018159U, // CGIJAsmL + 3540012659U, // CGIJAsmLE + 3540015990U, // CGIJAsmLH + 3540013384U, // CGIJAsmNE + 3540016813U, // CGIJAsmNH + 3540012066U, // CGIJAsmNHE + 3540018438U, // CGIJAsmNL + 3540012905U, // CGIJAsmNLE + 3540016258U, // CGIJAsmNLH + 4324667U, // CGIT + 1358984917U, // CGITAsm + 285233731U, // CGITAsmE + 285237236U, // CGITAsmH + 285232397U, // CGITAsmHE + 285238957U, // CGITAsmL + 285233236U, // CGITAsmLE + 285236625U, // CGITAsmLH + 285233594U, // CGITAsmNE + 285237023U, // CGITAsmNH + 285232283U, // CGITAsmNHE + 285238648U, // CGITAsmNL + 285233122U, // CGITAsmNLE + 285236482U, // CGITAsmNLH + 33582980U, // CGR + 3391224909U, // CGRB + 1107314075U, // CGRBAsm + 1107315223U, // CGRBAsmE + 1107318945U, // CGRBAsmH + 1107315358U, // CGRBAsmHE + 1107321638U, // CGRBAsmL + 1107316194U, // CGRBAsmLE + 1107319499U, // CGRBAsmLH + 1107316933U, // CGRBAsmNE + 1107320369U, // CGRBAsmNH + 1107315607U, // CGRBAsmNHE + 1107321994U, // CGRBAsmNL + 1107316446U, // CGRBAsmNLE + 1107319799U, // CGRBAsmNLH + 169999576U, // CGRJ + 1107321362U, // CGRJAsm + 1107316107U, // CGRJAsmE + 1107319425U, // CGRJAsmH + 1107315538U, // CGRJAsmHE + 1107321867U, // CGRJAsmL + 1107316371U, // CGRJAsmLE + 1107319702U, // CGRJAsmLH + 1107317096U, // CGRJAsmNE + 1107320525U, // CGRJAsmNH + 1107315782U, // CGRJAsmNHE + 1107322150U, // CGRJAsmNL + 1107316621U, // CGRJAsmNLE + 1107319974U, // CGRJAsmNLH + 268461539U, // CGRL + 153222482U, // CGRT + 1107326751U, // CGRTAsm + 33575524U, // CGRTAsmE + 33579023U, // CGRTAsmH + 33574188U, // CGRTAsmHE + 33580744U, // CGRTAsmL + 33575027U, // CGRTAsmLE + 33578416U, // CGRTAsmLH + 33575385U, // CGRTAsmNE + 33578814U, // CGRTAsmNH + 33574078U, // CGRTAsmNHE + 33580439U, // CGRTAsmNL + 33574917U, // CGRTAsmNLE + 33578277U, // CGRTAsmNLH + 218131853U, // CGXBR + 218120460U, // CGXBRA + 218133260U, // CGXR + 218133136U, // CGXTR + 218120560U, // CGXTRA + 134240442U, // CH + 134239092U, // CHF + 33583117U, // CHHR + 67150279U, // CHHSI + 285237555U, // CHI + 33583252U, // CHLR + 268461559U, // CHRL + 67150250U, // CHSI + 134248604U, // CHY + 305789995U, // CIB + 1392526499U, // CIBAsm + 2466269685U, // CIBAsmE + 2466273402U, // CIBAsmH + 2466269815U, // CIBAsmHE + 2466276100U, // CIBAsmL + 2466270651U, // CIBAsmLE + 2466273956U, // CIBAsmLH + 2466271390U, // CIBAsmNE + 2466274826U, // CIBAsmNH + 2466270059U, // CIBAsmNHE + 2466276451U, // CIBAsmNL + 2466270898U, // CIBAsmNLE + 2466274251U, // CIBAsmNLH + 251681316U, // CIH + 339344576U, // CIJ + 1392534005U, // CIJAsm + 3540012393U, // CIJAsmE + 3540015711U, // CIJAsmH + 3540011819U, // CIJAsmHE + 3540018153U, // CIJAsmL + 3540012652U, // CIJAsmLE + 3540015983U, // CIJAsmLH + 3540013377U, // CIJAsmNE + 3540016806U, // CIJAsmNH + 3540012058U, // CIJAsmNHE + 3540018431U, // CIJAsmNL + 3540012897U, // CIJAsmNLE + 3540016250U, // CIJAsmNLH + 4324657U, // CIT + 1358984905U, // CITAsm + 285233717U, // CITAsmE + 285237222U, // CITAsmH + 285232381U, // CITAsmHE + 285238943U, // CITAsmL + 285233220U, // CITAsmLE + 285236609U, // CITAsmLH + 285233578U, // CITAsmNE + 285237007U, // CITAsmNH + 285232265U, // CITAsmNHE + 285238632U, // CITAsmNL + 285233104U, // CITAsmNLE + 285236464U, // CITAsmNLH + 33581145U, // CKSM + 134243134U, // CL + 302041324U, // CLC + 33579842U, // CLCL + 1107316219U, // CLCLE + 1107326888U, // CLCLU + 218131490U, // CLFDBR + 218132876U, // CLFDTR + 218131630U, // CLFEBR + 352362928U, // CLFHSI + 369123605U, // CLFI + 4848949U, // CLFIT + 1459648206U, // CLFITAsm + 385897019U, // CLFITAsmE + 385900524U, // CLFITAsmH + 385895684U, // CLFITAsmHE + 385902245U, // CLFITAsmL + 385896523U, // CLFITAsmLE + 385899912U, // CLFITAsmLH + 385896881U, // CLFITAsmNE + 385900310U, // CLFITAsmNH + 385895569U, // CLFITAsmNHE + 385901935U, // CLFITAsmNL + 385896408U, // CLFITAsmNLE + 385899768U, // CLFITAsmNLH + 218131845U, // CLFXBR + 218133128U, // CLFXTR + 134239933U, // CLG + 218131505U, // CLGDBR + 218132891U, // CLGDTR + 218131645U, // CLGEBR + 134239018U, // CLGF + 369123578U, // CLGFI + 33582904U, // CLGFR + 268461521U, // CLGFRL + 268461581U, // CLGHRL + 352362943U, // CLGHSI + 307362868U, // CLGIB + 1476412597U, // CLGIBAsm + 2550155778U, // CLGIBAsmE + 2550159495U, // CLGIBAsmH + 2550155910U, // CLGIBAsmHE + 2550162193U, // CLGIBAsmL + 2550156746U, // CLGIBAsmLE + 2550160051U, // CLGIBAsmLH + 2550157485U, // CLGIBAsmNE + 2550160921U, // CLGIBAsmNH + 2550156156U, // CLGIBAsmNHE + 2550162546U, // CLGIBAsmNL + 2550156995U, // CLGIBAsmNLE + 2550160348U, // CLGIBAsmNLH + 340917449U, // CLGIJ + 1476420096U, // CLGIJAsm + 3623898486U, // CLGIJAsmE + 3623901804U, // CLGIJAsmH + 3623897914U, // CLGIJAsmHE + 3623904246U, // CLGIJAsmL + 3623898747U, // CLGIJAsmLE + 3623902078U, // CLGIJAsmLH + 3623899472U, // CLGIJAsmNE + 3623902901U, // CLGIJAsmNH + 3623898155U, // CLGIJAsmNHE + 3623904526U, // CLGIJAsmNL + 3623898994U, // CLGIJAsmNLE + 3623902347U, // CLGIJAsmNLH + 4848960U, // CLGIT + 1459648219U, // CLGITAsm + 385897034U, // CLGITAsmE + 385900539U, // CLGITAsmH + 385895701U, // CLGITAsmHE + 385902260U, // CLGITAsmL + 385896540U, // CLGITAsmLE + 385899929U, // CLGITAsmLH + 385896898U, // CLGITAsmNE + 385900327U, // CLGITAsmNH + 385895588U, // CLGITAsmNHE + 385901952U, // CLGITAsmNL + 385896427U, // CLGITAsmNLE + 385899787U, // CLGITAsmNLH + 33583016U, // CLGR + 3391224914U, // CLGRB + 1107314081U, // CLGRBAsm + 1107315230U, // CLGRBAsmE + 1107318952U, // CLGRBAsmH + 1107315366U, // CLGRBAsmHE + 1107321645U, // CLGRBAsmL + 1107316202U, // CLGRBAsmLE + 1107319507U, // CLGRBAsmLH + 1107316941U, // CLGRBAsmNE + 1107320377U, // CLGRBAsmNH + 1107315616U, // CLGRBAsmNHE + 1107322002U, // CLGRBAsmNL + 1107316455U, // CLGRBAsmNLE + 1107319808U, // CLGRBAsmNLH + 169999581U, // CLGRJ + 1107321368U, // CLGRJAsm + 1107316114U, // CLGRJAsmE + 1107319432U, // CLGRJAsmH + 1107315546U, // CLGRJAsmHE + 1107321874U, // CLGRJAsmL + 1107316379U, // CLGRJAsmLE + 1107319710U, // CLGRJAsmLH + 1107317104U, // CLGRJAsmNE + 1107320533U, // CLGRJAsmNH + 1107315791U, // CLGRJAsmNHE + 1107322158U, // CLGRJAsmNL + 1107316630U, // CLGRJAsmNLE + 1107319983U, // CLGRJAsmNLH + 268461545U, // CLGRL + 153222487U, // CLGRT + 1107326757U, // CLGRTAsm + 33575531U, // CLGRTAsmE + 33579030U, // CLGRTAsmH + 33574196U, // CLGRTAsmHE + 33580751U, // CLGRTAsmL + 33575035U, // CLGRTAsmLE + 33578424U, // CLGRTAsmLH + 33575393U, // CLGRTAsmNE + 33578822U, // CLGRTAsmNH + 33574087U, // CLGRTAsmNHE + 33580447U, // CLGRTAsmNL + 33574926U, // CLGRTAsmNLE + 33578286U, // CLGRTAsmNLH + 146732U, // CLGT + 1493202621U, // CLGTAsm + 436228654U, // CLGTAsmE + 436232159U, // CLGTAsmH + 436227317U, // CLGTAsmHE + 436233880U, // CLGTAsmL + 436228156U, // CLGTAsmLE + 436231545U, // CLGTAsmLH + 436228514U, // CLGTAsmNE + 436231943U, // CLGTAsmNH + 436227200U, // CLGTAsmNHE + 436233568U, // CLGTAsmNL + 436228039U, // CLGTAsmNLE + 436231399U, // CLGTAsmNLH + 218131860U, // CLGXBR + 218133143U, // CLGXTR + 134239136U, // CLHF + 33583153U, // CLHHR + 352362958U, // CLHHSI + 33583288U, // CLHLR + 268461597U, // CLHRL + 453026168U, // CLI + 307362874U, // CLIB + 1476412604U, // CLIBAsm + 2550155786U, // CLIBAsmE + 2550159503U, // CLIBAsmH + 2550155919U, // CLIBAsmHE + 2550162201U, // CLIBAsmL + 2550156755U, // CLIBAsmLE + 2550160060U, // CLIBAsmLH + 2550157494U, // CLIBAsmNE + 2550160930U, // CLIBAsmNH + 2550156166U, // CLIBAsmNHE + 2550162555U, // CLIBAsmNL + 2550157005U, // CLIBAsmNLE + 2550160358U, // CLIBAsmNLH + 369121866U, // CLIH + 340917455U, // CLIJ + 1476420103U, // CLIJAsm + 3623898494U, // CLIJAsmE + 3623901812U, // CLIJAsmH + 3623897923U, // CLIJAsmHE + 3623904254U, // CLIJAsmL + 3623898756U, // CLIJAsmLE + 3623902087U, // CLIJAsmLH + 3623899481U, // CLIJAsmNE + 3623902910U, // CLIJAsmNH + 3623898165U, // CLIJAsmNHE + 3623904535U, // CLIJAsmNL + 3623899004U, // CLIJAsmNLE + 3623902357U, // CLIJAsmNLH + 453032118U, // CLIY + 2365613969U, // CLM + 2365611506U, // CLMH + 2365618426U, // CLMY + 33583236U, // CLR + 3391224920U, // CLRB + 1107314088U, // CLRBAsm + 1107315238U, // CLRBAsmE + 1107318960U, // CLRBAsmH + 1107315375U, // CLRBAsmHE + 1107321653U, // CLRBAsmL + 1107316211U, // CLRBAsmLE + 1107319516U, // CLRBAsmLH + 1107316950U, // CLRBAsmNE + 1107320386U, // CLRBAsmNH + 1107315626U, // CLRBAsmNHE + 1107322011U, // CLRBAsmNL + 1107316465U, // CLRBAsmNLE + 1107319818U, // CLRBAsmNLH + 169999587U, // CLRJ + 1107321375U, // CLRJAsm + 1107316122U, // CLRJAsmE + 1107319440U, // CLRJAsmH + 1107315555U, // CLRJAsmHE + 1107321882U, // CLRJAsmL + 1107316388U, // CLRJAsmLE + 1107319719U, // CLRJAsmLH + 1107317113U, // CLRJAsmNE + 1107320542U, // CLRJAsmNH + 1107315801U, // CLRJAsmNHE + 1107322167U, // CLRJAsmNL + 1107316640U, // CLRJAsmNLE + 1107319993U, // CLRJAsmNLH + 268461618U, // CLRL + 153222493U, // CLRT + 1107326764U, // CLRTAsm + 33575539U, // CLRTAsmE + 33579038U, // CLRTAsmH + 33574205U, // CLRTAsmHE + 33580759U, // CLRTAsmL + 33575044U, // CLRTAsmLE + 33578433U, // CLRTAsmLH + 33575402U, // CLRTAsmNE + 33578831U, // CLRTAsmNH + 33574097U, // CLRTAsmNHE + 33580456U, // CLRTAsmNL + 33574936U, // CLRTAsmNLE + 33578296U, // CLRTAsmNLH + 33584959U, // CLST + 146758U, // CLT + 1493202658U, // CLTAsm + 436228690U, // CLTAsmE + 436232195U, // CLTAsmH + 436227358U, // CLTAsmHE + 436233916U, // CLTAsmL + 436228197U, // CLTAsmLE + 436231586U, // CLTAsmLH + 436228555U, // CLTAsmNE + 436231984U, // CLTAsmNH + 436227246U, // CLTAsmNHE + 436233609U, // CLTAsmNL + 436228085U, // CLTAsmNLE + 436231445U, // CLTAsmNLH + 134248662U, // CLY + 33573205U, // CMPSC + 117500452U, // CP + 234911389U, // CPDT + 1090547289U, // CPSDRdd + 1090547289U, // CPSDRds + 1090547289U, // CPSDRsd + 1090547289U, // CPSDRss + 234911608U, // CPXT + 33571240U, // CPYA + 33582546U, // CR + 3391224905U, // CRB + 1107314070U, // CRBAsm + 1107315217U, // CRBAsmE + 1107318939U, // CRBAsmH + 1107315351U, // CRBAsmHE + 1107321632U, // CRBAsmL + 1107316187U, // CRBAsmLE + 1107319492U, // CRBAsmLH + 1107316926U, // CRBAsmNE + 1107320362U, // CRBAsmNH + 1107315599U, // CRBAsmNHE + 1107321987U, // CRBAsmNL + 1107316438U, // CRBAsmNLE + 1107319791U, // CRBAsmNLH + 1090540071U, // CRDTE + 1090540071U, // CRDTEOpt + 169999572U, // CRJ + 1107321357U, // CRJAsm + 1107316101U, // CRJAsmE + 1107319419U, // CRJAsmH + 1107315531U, // CRJAsmHE + 1107321861U, // CRJAsmL + 1107316364U, // CRJAsmLE + 1107319695U, // CRJAsmLH + 1107317089U, // CRJAsmNE + 1107320518U, // CRJAsmNH + 1107315774U, // CRJAsmNHE + 1107322143U, // CRJAsmNL + 1107316613U, // CRJAsmNLE + 1107319966U, // CRJAsmNLH + 268461502U, // CRL + 153222478U, // CRT + 1107326746U, // CRTAsm + 33575518U, // CRTAsmE + 33579017U, // CRTAsmH + 33574181U, // CRTAsmHE + 33580738U, // CRTAsmL + 33575020U, // CRTAsmLE + 33578409U, // CRTAsmLH + 33575378U, // CRTAsmNE + 33578807U, // CRTAsmNH + 33574070U, // CRTAsmNHE + 33580432U, // CRTAsmNL + 33574909U, // CRTAsmNLE + 33578269U, // CRTAsmNLH + 1090548974U, // CS + 15496U, // CSCH + 1107325373U, // CSDTR + 1090541471U, // CSG + 16804730U, // CSP + 16799602U, // CSPG + 1543550795U, // CSST + 1107325625U, // CSXTR + 1090550030U, // CSY + 1107312653U, // CU12 + 33570829U, // CU12Opt + 1107312665U, // CU14 + 33570841U, // CU14Opt + 1107312641U, // CU21 + 33570817U, // CU21Opt + 1107312671U, // CU24 + 33570847U, // CU24Opt + 33570823U, // CU41 + 33570835U, // CU42 + 33583570U, // CUDTR + 33575451U, // CUSE + 1107326874U, // CUTFU + 33585050U, // CUTFUOpt + 1107318025U, // CUUTF + 33576201U, // CUUTFOpt + 33583822U, // CUXTR + 18258U, // CVB + 21980U, // CVBG + 30815U, // CVBY + 134236629U, // CVD + 134239772U, // CVDG + 134248571U, // CVDY + 33582442U, // CXBR + 33582377U, // CXFBR + 218120404U, // CXFBRA + 33582960U, // CXFR + 218132990U, // CXFTR + 33582422U, // CXGBR + 218120428U, // CXGBRA + 33583091U, // CXGR + 33583651U, // CXGTR + 218120538U, // CXGTRA + 218131745U, // CXLFBR + 218132982U, // CXLFTR + 218131790U, // CXLGBR + 218133019U, // CXLGTR + 234911508U, // CXPT + 33583861U, // CXR + 33583683U, // CXSTR + 33583711U, // CXTR + 33583697U, // CXUTR + 234911632U, // CXZT + 134248550U, // CY + 234911401U, // CZDT + 234911620U, // CZXT + 18801U, // D + 18808U, // DD + 16960U, // DDB + 16804878U, // DDBR + 16805377U, // DDR + 1107325283U, // DDTR + 1107312949U, // DDTRA + 19023U, // DE + 17360U, // DEB + 16805011U, // DEBR + 16805515U, // DER + 1107318148U, // DIAG + 1107323961U, // DIDBR + 1107324101U, // DIEBR + 25443U, // DL + 22212U, // DLG + 16805806U, // DLGR + 16806025U, // DLR + 117500472U, // DP + 16805361U, // DR + 22437U, // DSG + 21324U, // DSGF + 16805723U, // DSGFR + 16805843U, // DSGR + 16805233U, // DXBR + 16806651U, // DXR + 1107325542U, // DXTR + 1107313001U, // DXTRA + 33582052U, // EAR + 1107318142U, // ECAG + 33583411U, // ECCTR + 33570901U, // ECPGA + 1543542737U, // ECTG + 302041470U, // ED + 302047870U, // EDMK + 33583472U, // EEDTR + 33583731U, // EEXTR + 3164446U, // EFPC + 3174494U, // EPAIR + 3173353U, // EPAR + 33583432U, // EPCTR + 33585171U, // EPSW + 33576508U, // EREG + 33576527U, // EREGG + 3174501U, // ESAIR + 3173359U, // ESAR + 33583556U, // ESDTR + 3162173U, // ESEA + 33571224U, // ESTA + 33583808U, // ESXTR + 3164588U, // ETND + 134248491U, // EX + 268461656U, // EXRL + 218131520U, // FIDBR + 218120356U, // FIDBRA + 33582635U, // FIDR + 218132899U, // FIDTR + 218131660U, // FIEBR + 218120380U, // FIEBRA + 33582779U, // FIER + 218131868U, // FIXBR + 218120468U, // FIXBRA + 33583890U, // FIXR + 218133151U, // FIXTR + 33583046U, // FLOGR + 33582630U, // HDR + 33582767U, // HER + 15501U, // HSCH + 3164293U, // IAC + 18631U, // IC + 18631U, // IC32 + 30821U, // IC32Y + 486565654U, // ICM + 486563280U, // ICMH + 486570221U, // ICMY + 30821U, // ICY + 1090540065U, // IDTE + 1090540065U, // IDTEOpt + 1090548087U, // IEDTR + 1090548346U, // IEXTR + 369120121U, // IIHF + 352344513U, // IIHH + 352347051U, // IIHL + 369120266U, // IILF + 352344918U, // IILH + 352347175U, // IILL + 15592U, // IPK + 3172386U, // IPM + 1107317336U, // IPTE + 1107317336U, // IPTEOpt + 33575512U, // IPTEOptOpt + 33580810U, // IRBM + 16797096U, // ISKE + 16802541U, // IVSK + 3308094U, // InsnE + 1579334303U, // InsnRI + 505608775U, // InsnRIE + 3726834366U, // InsnRIL + 2653092625U, // InsnRILU + 3726834407U, // InsnRIS + 5929684U, // InsnRR + 505592402U, // InsnRRE + 505592446U, // InsnRRF + 505608956U, // InsnRRS + 505592562U, // InsnRS + 505608797U, // InsnRSE + 505608883U, // InsnRSI + 505609010U, // InsnRSY + 2653076253U, // InsnRX + 2653092467U, // InsnRXE + 505608852U, // InsnRXF + 2653092669U, // InsnRXY + 157465310U, // InsnS + 509786793U, // InsnSI + 1583545033U, // InsnSIL + 2657286951U, // InsnSIY + 7011079U, // InsnSS + 3731028584U, // InsnSSE + 3731028617U, // InsnSSF + 205303U, // J + 200043U, // JAsmE + 203361U, // JAsmH + 199469U, // JAsmHE + 205803U, // JAsmL + 200302U, // JAsmLE + 203633U, // JAsmLH + 206729U, // JAsmM + 201027U, // JAsmNE + 204456U, // JAsmNH + 199708U, // JAsmNHE + 206081U, // JAsmNL + 200547U, // JAsmNLE + 203900U, // JAsmNLH + 206844U, // JAsmNM + 207270U, // JAsmNO + 207642U, // JAsmNP + 211451U, // JAsmNZ + 207141U, // JAsmO + 207531U, // JAsmP + 211331U, // JAsmZ + 202402U, // JG + 199282U, // JGAsmE + 203133U, // JGAsmH + 199407U, // JGAsmHE + 205704U, // JGAsmL + 200240U, // JGAsmLE + 203531U, // JGAsmLH + 206664U, // JGAsmM + 200965U, // JGAsmNE + 204394U, // JGAsmNH + 199639U, // JGAsmNHE + 206019U, // JGAsmNL + 200478U, // JGAsmNLE + 203831U, // JGAsmNLH + 206784U, // JGAsmNM + 207210U, // JGAsmNO + 207582U, // JGAsmNP + 211391U, // JGAsmNZ + 207088U, // JGAsmO + 207465U, // JGAsmP + 211278U, // JGAsmZ + 134234878U, // KDB + 33582151U, // KDBR + 33583530U, // KDTR + 134235119U, // KEB + 33582291U, // KEBR + 3361184U, // KIMD + 3361190U, // KLMD + 33580941U, // KM + 1090535547U, // KMA + 3360906U, // KMAC + 33573115U, // KMC + 1090548033U, // KMCTR + 33576078U, // KMF + 33581371U, // KMO + 33582499U, // KXBR + 33583782U, // KXTR + 134243062U, // L + 134234218U, // LA + 1107312684U, // LAA + 1107318136U, // LAAG + 1107321587U, // LAAL + 1107318444U, // LAALG + 134236650U, // LAE + 134248577U, // LAEY + 1107322617U, // LAM + 1107327200U, // LAMY + 1107323013U, // LAN + 1107318603U, // LANG + 1107323077U, // LAO + 1107318615U, // LAOG + 268461494U, // LARL + 469805940U, // LASP + 134248041U, // LAT + 1107327007U, // LAX + 1107318845U, // LAXG + 134248527U, // LAY + 134235341U, // LB + 134240406U, // LBH + 33582430U, // LBR + 1207976394U, // LCBB + 3188342U, // LCCTL + 33582087U, // LCDBR + 33582857U, // LCDFR + 33582857U, // LCDFR_32 + 33582587U, // LCDR + 33582219U, // LCEBR + 33582723U, // LCER + 33582890U, // LCGFR + 33582979U, // LCGR + 33582558U, // LCR + 1107322493U, // LCTL + 1107318543U, // LCTLG + 33582441U, // LCXBR + 33583860U, // LCXR + 134236572U, // LD + 134236750U, // LDE + 134236750U, // LDE32 + 134235087U, // LDEB + 33582226U, // LDEBR + 33582736U, // LDER + 1107325408U, // LDETR + 33582998U, // LDGR + 33582641U, // LDR + 33582641U, // LDR32 + 33582448U, // LDXBR + 218120436U, // LDXBRA + 33583866U, // LDXR + 218133093U, // LDXTR + 134248560U, // LDY + 134237623U, // LE + 33582100U, // LEDBR + 218120332U, // LEDBRA + 33582605U, // LEDR + 218132862U, // LEDTR + 33582786U, // LER + 33582455U, // LEXBR + 218120444U, // LEXBRA + 33583872U, // LEXR + 134248583U, // LEY + 3191648U, // LFAS + 134240599U, // LFH + 134248034U, // LFHAT + 3180836U, // LFPC + 134239919U, // LG + 134248028U, // LGAT + 134235208U, // LGB + 33582400U, // LGBR + 33582623U, // LGDR + 134239013U, // LGF + 251683060U, // LGFI + 33582898U, // LGFR + 268461522U, // LGFRL + 134239830U, // LGG + 134240643U, // LGH + 285237574U, // LGHI + 33583111U, // LGHR + 268461582U, // LGHRL + 33583011U, // LGR + 268461546U, // LGRL + 134236483U, // LGSC + 134240928U, // LH + 134240733U, // LHH + 285237608U, // LHI + 33583161U, // LHR + 268461598U, // LHRL + 134248609U, // LHY + 134236401U, // LLC + 134240458U, // LLCH + 33582563U, // LLCR + 134236346U, // LLGC + 33582550U, // LLGCR + 134239024U, // LLGF + 134248020U, // LLGFAT + 33582911U, // LLGFR + 268461529U, // LLGFRL + 134240170U, // LLGFSG + 134240642U, // LLGH + 33583110U, // LLGHR + 268461589U, // LLGHRL + 134248131U, // LLGT + 134248046U, // LLGTAT + 33583636U, // LLGTR + 134241202U, // LLH + 134240738U, // LLHH + 33583166U, // LLHR + 268461604U, // LLHRL + 369120127U, // LLIHF + 385898951U, // LLIHH + 385901489U, // LLIHL + 369120272U, // LLILF + 385899356U, // LLILH + 385901613U, // LLILL + 134239044U, // LLZRGF + 1107322770U, // LM + 1107315111U, // LMD + 1107318585U, // LMG + 1107320307U, // LMH + 1107327227U, // LMY + 33582163U, // LNDBR + 33582864U, // LNDFR + 33582864U, // LNDFR_32 + 33582651U, // LNDR + 33582297U, // LNEBR + 33582809U, // LNER + 33582925U, // LNGFR + 33583040U, // LNGR + 33583355U, // LNR + 33582511U, // LNXBR + 33583906U, // LNXR + 244833U, // LOC + 1543522574U, // LOCAsm + 469781056U, // LOCAsmE + 469784790U, // LOCAsmH + 469781182U, // LOCAsmHE + 469787464U, // LOCAsmL + 469782018U, // LOCAsmLE + 469785323U, // LOCAsmLH + 469788443U, // LOCAsmM + 469782750U, // LOCAsmNE + 469786186U, // LOCAsmNH + 469781427U, // LOCAsmNHE + 469787811U, // LOCAsmNL + 469782266U, // LOCAsmNLE + 469785619U, // LOCAsmNLH + 469788576U, // LOCAsmNM + 469789002U, // LOCAsmNO + 469789374U, // LOCAsmNP + 469793183U, // LOCAsmNZ + 469788884U, // LOCAsmO + 469789218U, // LOCAsmP + 469793067U, // LOCAsmZ + 244892U, // LOCFH + 1543526728U, // LOCFHAsm + 469781197U, // LOCFHAsmE + 469785008U, // LOCFHAsmH + 469781237U, // LOCFHAsmHE + 469787546U, // LOCFHAsmL + 469782070U, // LOCFHAsmLE + 469785376U, // LOCFHAsmLH + 469788498U, // LOCFHAsmM + 469782795U, // LOCFHAsmNE + 469786224U, // LOCFHAsmNH + 469781470U, // LOCFHAsmNHE + 469787849U, // LOCFHAsmNL + 469782309U, // LOCFHAsmNLE + 469785662U, // LOCFHAsmNLH + 469788614U, // LOCFHAsmNM + 469789040U, // LOCFHAsmNO + 469789412U, // LOCFHAsmNP + 469793221U, // LOCFHAsmNZ + 469788917U, // LOCFHAsmO + 469789301U, // LOCFHAsmP + 469793107U, // LOCFHAsmZ + 7601442U, // LOCFHR + 1090547710U, // LOCFHRAsm + 16798214U, // LOCFHRAsmE + 16801700U, // LOCFHRAsmH + 16796907U, // LOCFHRAsmHE + 16803325U, // LOCFHRAsmL + 16797746U, // LOCFHRAsmLE + 16801113U, // LOCFHRAsmLH + 16803914U, // LOCFHRAsmM + 16798104U, // LOCFHRAsmNE + 16801533U, // LOCFHRAsmNH + 16796789U, // LOCFHRAsmNHE + 16803158U, // LOCFHRAsmNL + 16797628U, // LOCFHRAsmNLE + 16800988U, // LOCFHRAsmNLH + 16803858U, // LOCFHRAsmNM + 16804290U, // LOCFHRAsmNO + 16804656U, // LOCFHRAsmNP + 16808465U, // LOCFHRAsmNZ + 16804339U, // LOCFHRAsmO + 16804698U, // LOCFHRAsmP + 16808490U, // LOCFHRAsmZ + 244858U, // LOCG + 1543525890U, // LOCGAsm + 469781091U, // LOCGAsmE + 469784935U, // LOCGAsmH + 469781214U, // LOCGAsmHE + 469787513U, // LOCGAsmL + 469782047U, // LOCGAsmLE + 469785338U, // LOCGAsmLH + 469788473U, // LOCGAsmM + 469782772U, // LOCGAsmNE + 469786201U, // LOCGAsmNH + 469781444U, // LOCGAsmNHE + 469787826U, // LOCGAsmNL + 469782283U, // LOCGAsmNLE + 469785636U, // LOCGAsmNLH + 469788591U, // LOCGAsmNM + 469789017U, // LOCGAsmNO + 469789389U, // LOCGAsmNP + 469793198U, // LOCGAsmNZ + 469788897U, // LOCGAsmO + 469789268U, // LOCGAsmP + 469793087U, // LOCGAsmZ + 8125618U, // LOCGHI + 1140875582U, // LOCGHIAsm + 67128658U, // LOCGHIAsmE + 67131960U, // LOCGHIAsmH + 67128087U, // LOCGHIAsmHE + 67134423U, // LOCGHIAsmL + 67128920U, // LOCGHIAsmLE + 67132226U, // LOCGHIAsmLH + 67135344U, // LOCGHIAsmM + 67129645U, // LOCGHIAsmNE + 67133074U, // LOCGHIAsmNH + 67128324U, // LOCGHIAsmNHE + 67134699U, // LOCGHIAsmNL + 67129163U, // LOCGHIAsmNLE + 67132516U, // LOCGHIAsmNLH + 67135464U, // LOCGHIAsmNM + 67135890U, // LOCGHIAsmNO + 67136262U, // LOCGHIAsmNP + 67140071U, // LOCGHIAsmNZ + 67135763U, // LOCGHIAsmO + 67136147U, // LOCGHIAsmP + 67139953U, // LOCGHIAsmZ + 7601436U, // LOCGR + 1090547593U, // LOCGRAsm + 16798206U, // LOCGRAsmE + 16801692U, // LOCGRAsmH + 16796898U, // LOCGRAsmHE + 16803297U, // LOCGRAsmL + 16797737U, // LOCGRAsmLE + 16801104U, // LOCGRAsmLH + 16803906U, // LOCGRAsmM + 16798095U, // LOCGRAsmNE + 16801524U, // LOCGRAsmNH + 16796779U, // LOCGRAsmNHE + 16803149U, // LOCGRAsmNL + 16797618U, // LOCGRAsmNLE + 16800978U, // LOCGRAsmNLH + 16803849U, // LOCGRAsmNM + 16804281U, // LOCGRAsmNO + 16804647U, // LOCGRAsmNP + 16808456U, // LOCGRAsmNZ + 16804331U, // LOCGRAsmO + 16804690U, // LOCGRAsmP + 16808482U, // LOCGRAsmZ + 8125625U, // LOCHHI + 1140875609U, // LOCHHIAsm + 67128667U, // LOCHHIAsmE + 67131969U, // LOCHHIAsmH + 67128097U, // LOCHHIAsmHE + 67134432U, // LOCHHIAsmL + 67128930U, // LOCHHIAsmLE + 67132236U, // LOCHHIAsmLH + 67135353U, // LOCHHIAsmM + 67129655U, // LOCHHIAsmNE + 67133084U, // LOCHHIAsmNH + 67128335U, // LOCHHIAsmNHE + 67134709U, // LOCHHIAsmNL + 67129174U, // LOCHHIAsmNLE + 67132527U, // LOCHHIAsmNLH + 67135474U, // LOCHHIAsmNM + 67135900U, // LOCHHIAsmNO + 67136272U, // LOCHHIAsmNP + 67140081U, // LOCHHIAsmNZ + 67135772U, // LOCHHIAsmO + 67136156U, // LOCHHIAsmP + 67139962U, // LOCHHIAsmZ + 8125612U, // LOCHI + 1140875569U, // LOCHIAsm + 67128650U, // LOCHIAsmE + 67131952U, // LOCHIAsmH + 67128078U, // LOCHIAsmHE + 67134415U, // LOCHIAsmL + 67128911U, // LOCHIAsmLE + 67132217U, // LOCHIAsmLH + 67135336U, // LOCHIAsmM + 67129636U, // LOCHIAsmNE + 67133065U, // LOCHIAsmNH + 67128314U, // LOCHIAsmNHE + 67134690U, // LOCHIAsmNL + 67129153U, // LOCHIAsmNLE + 67132506U, // LOCHIAsmNLH + 67135455U, // LOCHIAsmNM + 67135881U, // LOCHIAsmNO + 67136253U, // LOCHIAsmNP + 67140062U, // LOCHIAsmNZ + 67135755U, // LOCHIAsmO + 67136139U, // LOCHIAsmP + 67139945U, // LOCHIAsmZ + 7601431U, // LOCR + 1090547177U, // LOCRAsm + 16798199U, // LOCRAsmE + 16801685U, // LOCRAsmH + 16796890U, // LOCRAsmHE + 16803260U, // LOCRAsmL + 16797729U, // LOCRAsmLE + 16801096U, // LOCRAsmLH + 16803884U, // LOCRAsmM + 16798087U, // LOCRAsmNE + 16801516U, // LOCRAsmNH + 16796770U, // LOCRAsmNHE + 16803141U, // LOCRAsmNL + 16797609U, // LOCRAsmNLE + 16800969U, // LOCRAsmNLH + 16803841U, // LOCRAsmNM + 16804273U, // LOCRAsmNO + 16804639U, // LOCRAsmNP + 16808448U, // LOCRAsmNZ + 16804317U, // LOCRAsmO + 16804683U, // LOCRAsmP + 16808475U, // LOCRAsmZ + 3188355U, // LPCTL + 1509968306U, // LPD + 33582170U, // LPDBR + 33582871U, // LPDFR + 33582871U, // LPDFR_32 + 1509971477U, // LPDG + 33582657U, // LPDR + 33582304U, // LPEBR + 33582815U, // LPER + 33582932U, // LPGFR + 33583053U, // LPGR + 3189574U, // LPP + 134245326U, // LPQ + 33583376U, // LPR + 3192857U, // LPSW + 3183237U, // LPSWE + 1107312707U, // LPTEA + 33582518U, // LPXBR + 33583912U, // LPXR + 33583227U, // LR + 134234396U, // LRA + 134239640U, // LRAG + 134248537U, // LRAY + 33582669U, // LRDR + 33582827U, // LRER + 268461619U, // LRL + 134248422U, // LRV + 134240304U, // LRVG + 33583084U, // LRVGR + 134242388U, // LRVH + 33583839U, // LRVR + 3188362U, // LSCTL + 134248163U, // LT + 33582191U, // LTDBR + 33582191U, // LTDBRCompare + 33582688U, // LTDR + 33583563U, // LTDTR + 33582325U, // LTEBR + 33582325U, // LTEBRCompare + 33582839U, // LTER + 134240238U, // LTG + 134239064U, // LTGF + 33582953U, // LTGFR + 33583078U, // LTGR + 33583658U, // LTR + 33582538U, // LTXBR + 33582538U, // LTXBRCompare + 33583929U, // LTXR + 33583815U, // LTXTR + 33571206U, // LURA + 33576365U, // LURAG + 134236634U, // LXD + 134235054U, // LXDB + 33582198U, // LXDBR + 33582694U, // LXDR + 1107325401U, // LXDTR + 134238860U, // LXE + 134235178U, // LXEB + 33582332U, // LXEBR + 33582845U, // LXER + 33583896U, // LXR + 134248658U, // LY + 3174002U, // LZDR + 3174147U, // LZER + 134239457U, // LZRF + 134240148U, // LZRG + 3175231U, // LZXR + 26363U, // M + 1090537839U, // MAD + 1090535937U, // MADB + 1090546688U, // MADBR + 1090547183U, // MADR + 1090537968U, // MAE + 1090536386U, // MAEB + 1090546820U, // MAEBR + 1090547320U, // MAER + 1090549844U, // MAY + 1090543730U, // MAYH + 1090547793U, // MAYHR + 1090545390U, // MAYL + 1090547939U, // MAYLR + 1090548549U, // MAYR + 453019900U, // MC + 18850U, // MD + 17164U, // MDB + 16804941U, // MDBR + 19027U, // MDE + 17372U, // MDEB + 16805017U, // MDEBR + 16805526U, // MDER + 16805430U, // MDR + 1107325360U, // MDTR + 1107312964U, // MDTRA + 20634U, // ME + 19038U, // MEE + 17385U, // MEEB + 16805024U, // MEEBR + 16805532U, // MEER + 16805582U, // MER + 30866U, // MFY + 22311U, // MG + 22923U, // MGH + 67133772U, // MGHI + 1107321512U, // MGRK + 24018U, // MH + 67133805U, // MHI + 30886U, // MHY + 25695U, // ML + 22246U, // MLG + 16805812U, // MLGR + 16806079U, // MLR + 117500597U, // MP + 16806129U, // MR + 30259U, // MS + 18768U, // MSC + 3184875U, // MSCH + 1090537930U, // MSD + 1090536316U, // MSDB + 1090546792U, // MSDBR + 1090547283U, // MSDR + 1090540054U, // MSE + 1090536477U, // MSEB + 1090546926U, // MSEBR + 1090547441U, // MSER + 50356513U, // MSFI + 22465U, // MSG + 18624U, // MSGC + 21330U, // MSGF + 50356488U, // MSGFI + 16805730U, // MSGFR + 16805849U, // MSGR + 1107314904U, // MSGRKC + 16806184U, // MSR + 1107314912U, // MSRKC + 3162526U, // MSTA + 31001U, // MSY + 302041441U, // MVC + 469803592U, // MVCDK + 302049434U, // MVCIN + 270914U, // MVCK + 33579867U, // MVCL + 1107316241U, // MVCLE + 1107326895U, // MVCLU + 1543550526U, // MVCOS + 272943U, // MVCP + 275692U, // MVCS + 469803750U, // MVCSK + 67150162U, // MVGHI + 67150177U, // MVHHI + 67150194U, // MVHI + 453026284U, // MVI + 453032134U, // MVIY + 302049472U, // MVN + 117500425U, // MVO + 33576824U, // MVPG + 33584977U, // MVST + 302053945U, // MVZ + 16805289U, // MXBR + 18911U, // MXD + 17332U, // MXDB + 16804989U, // MXDBR + 16805484U, // MXDR + 16806685U, // MXR + 1107325612U, // MXTR + 1107313016U, // MXTRA + 1107327202U, // MY + 1107320952U, // MYH + 1107325016U, // MYHR + 1107322612U, // MYL + 1107325162U, // MYLR + 1107325771U, // MYR + 26759U, // N + 302041349U, // NC + 22349U, // NG + 16805825U, // NGR + 1107321518U, // NGRK + 453026173U, // NI + 8495285U, // NIAI + 100684678U, // NIHF + 352344526U, // NIHH + 352347064U, // NIHL + 100684823U, // NILF + 352344931U, // NILH + 352347188U, // NILL + 453032124U, // NIY + 16806140U, // NR + 1107321554U, // NRK + 134240243U, // NTSTG + 30982U, // NY + 26823U, // O + 302041359U, // OC + 22361U, // OG + 16805832U, // OGR + 1107321524U, // OGRK + 453026177U, // OI + 100684684U, // OIHF + 352344532U, // OIHH + 352347070U, // OIHL + 100684829U, // OILF + 352344937U, // OILH + 352347194U, // OILL + 453032129U, // OIY + 16806145U, // OR + 1107321559U, // ORK + 30986U, // OY + 117498417U, // PACK + 15423U, // PALB + 3180832U, // PC + 15453U, // PCC + 15623U, // PCKMO + 1149314U, // PFD + 153724355U, // PFDRL + 3363962U, // PFMF + 15629U, // PFPO + 33581225U, // PGIN + 33584989U, // PGOUT + 520126558U, // PKA + 520140707U, // PKU + 1509976374U, // PLO + 33584878U, // POPCNT + 1107312775U, // PPA + 33581483U, // PPNO + 15657U, // PR + 33581516U, // PRNO + 33584901U, // PT + 3167492U, // PTF + 15471U, // PTFF + 33579495U, // PTI + 15428U, // PTLB + 1107325270U, // QADTR + 1107325528U, // QAXTR + 3187089U, // QCTRI + 3187164U, // QSI + 15634U, // RCHP + 1090540991U, // RISBG + 1090540991U, // RISBG32 + 1090545802U, // RISBGN + 1090541161U, // RISBHG + 1090541235U, // RISBLG + 1107321935U, // RLL + 1107318490U, // RLLG + 1090540998U, // RNSBG + 1090541005U, // ROSBG + 3189582U, // RP + 33573421U, // RRBE + 33580816U, // RRBM + 1107325366U, // RRDTR + 1107325618U, // RRXTR + 15506U, // RSCH + 1090541012U, // RXSBG + 29533U, // S + 3180688U, // SAC + 3183270U, // SACF + 15596U, // SAL + 15336U, // SAM24 + 15324U, // SAM31 + 15342U, // SAM64 + 33582064U, // SAR + 33583418U, // SCCTR + 15618U, // SCHM + 3187255U, // SCK + 3180747U, // SCKC + 15476U, // SCKPF + 18891U, // SD + 17262U, // SDB + 16804969U, // SDBR + 16805460U, // SDR + 1107325374U, // SDTR + 1107312971U, // SDTRA + 21015U, // SE + 17438U, // SEB + 16805103U, // SEBR + 16805618U, // SER + 3174689U, // SFASR + 3164458U, // SFPC + 22427U, // SG + 21325U, // SGF + 16805724U, // SGFR + 22928U, // SGH + 16805844U, // SGR + 1107321530U, // SGRK + 24510U, // SH + 1107324970U, // SHHHR + 1107325105U, // SHHLR + 30891U, // SHY + 3181924U, // SIE + 3178575U, // SIGA + 1107323491U, // SIGP + 26209U, // SL + 469778537U, // SLA + 1107318154U, // SLAG + 1107321381U, // SLAK + 17699U, // SLB + 21945U, // SLBG + 16805755U, // SLBGR + 16805213U, // SLBR + 469778481U, // SLDA + 469787489U, // SLDL + 1107326615U, // SLDT + 100688155U, // SLFI + 22275U, // SLG + 21302U, // SLGF + 100688129U, // SLGFI + 16805702U, // SLGFR + 16805818U, // SLGR + 1107321505U, // SLGRK + 1107324962U, // SLHHHR + 1107325097U, // SLHHLR + 469787732U, // SLL + 1107318496U, // SLLG + 1107321458U, // SLLK + 16806105U, // SLR + 1107321548U, // SLRK + 1107326834U, // SLXT + 30939U, // SLY + 117500790U, // SP + 33583439U, // SPCTR + 3178595U, // SPKA + 3172391U, // SPM + 3192585U, // SPT + 3192889U, // SPX + 134236599U, // SQD + 134234974U, // SQDB + 33582177U, // SQDBR + 33582663U, // SQDR + 134238706U, // SQE + 134235159U, // SQEB + 33582311U, // SQEBR + 33582821U, // SQER + 33582525U, // SQXBR + 33583918U, // SQXR + 16806173U, // SR + 469778723U, // SRA + 1107318176U, // SRAG + 1107321387U, // SRAK + 469778487U, // SRDA + 469787495U, // SRDL + 1107326627U, // SRDT + 1107321564U, // SRK + 469788230U, // SRL + 1107318523U, // SRLG + 1107321464U, // SRLK + 3188764U, // SRNM + 3179850U, // SRNMB + 3192551U, // SRNMT + 1375791978U, // SRP + 33584965U, // SRST + 33585082U, // SRSTU + 1107326846U, // SRXT + 3174508U, // SSAIR + 3173365U, // SSAR + 3184881U, // SSCH + 1107316142U, // SSKE + 33574318U, // SSKEOpt + 3188847U, // SSM + 134248257U, // ST + 1107322622U, // STAM + 1107327206U, // STAMY + 3189262U, // STAP + 134236508U, // STC + 134240510U, // STCH + 3187260U, // STCK + 3180753U, // STCKC + 3181985U, // STCKE + 3183584U, // STCKF + 2365613864U, // STCM + 2365611478U, // STCMH + 2365618419U, // STCMY + 3192389U, // STCPS + 3192844U, // STCRW + 1107318759U, // STCTG + 1107322513U, // STCTL + 134248554U, // STCY + 134236623U, // STD + 134248565U, // STDY + 134238848U, // STE + 134248588U, // STEY + 134240604U, // STFH + 3187571U, // STFL + 3182104U, // STFLE + 3180848U, // STFPC + 134240245U, // STG + 268461552U, // STGRL + 134236489U, // STGSC + 134242341U, // STH + 134240785U, // STHH + 268461611U, // STHRL + 134248624U, // STHY + 3189301U, // STIDP + 1107322997U, // STM + 1107318590U, // STMG + 1107320312U, // STMH + 1107327232U, // STMY + 453027935U, // STNSM + 157547621U, // STOC + 1509968147U, // STOCAsm + 436226630U, // STOCAsmE + 436230364U, // STOCAsmH + 436226757U, // STOCAsmHE + 436233038U, // STOCAsmL + 436227593U, // STOCAsmLE + 436230898U, // STOCAsmLH + 436234017U, // STOCAsmM + 436228325U, // STOCAsmNE + 436231761U, // STOCAsmNH + 436227003U, // STOCAsmNHE + 436233386U, // STOCAsmNL + 436227842U, // STOCAsmNLE + 436231195U, // STOCAsmNLH + 436234151U, // STOCAsmNM + 436234577U, // STOCAsmNO + 436234949U, // STOCAsmNP + 436238758U, // STOCAsmNZ + 436234458U, // STOCAsmO + 436234792U, // STOCAsmP + 436238641U, // STOCAsmZ + 157547682U, // STOCFH + 1509972303U, // STOCFHAsm + 436226773U, // STOCFHAsmE + 436230584U, // STOCFHAsmH + 436226814U, // STOCFHAsmHE + 436233122U, // STOCFHAsmL + 436227647U, // STOCFHAsmLE + 436230953U, // STOCFHAsmLH + 436234074U, // STOCFHAsmM + 436228372U, // STOCFHAsmNE + 436231801U, // STOCFHAsmNH + 436227048U, // STOCFHAsmNHE + 436233426U, // STOCFHAsmNL + 436227887U, // STOCFHAsmNLE + 436231240U, // STOCFHAsmNLH + 436234191U, // STOCFHAsmNM + 436234617U, // STOCFHAsmNO + 436234989U, // STOCFHAsmNP + 436238798U, // STOCFHAsmNZ + 436234493U, // STOCFHAsmO + 436234877U, // STOCFHAsmP + 436238683U, // STOCFHAsmZ + 157547647U, // STOCG + 1509971464U, // STOCGAsm + 436226666U, // STOCGAsmE + 436230510U, // STOCGAsmH + 436226790U, // STOCGAsmHE + 436233088U, // STOCGAsmL + 436227623U, // STOCGAsmLE + 436230914U, // STOCGAsmLH + 436234048U, // STOCGAsmM + 436228348U, // STOCGAsmNE + 436231777U, // STOCGAsmNH + 436227021U, // STOCGAsmNHE + 436233402U, // STOCGAsmNL + 436227860U, // STOCGAsmNLE + 436231213U, // STOCGAsmNLH + 436234167U, // STOCGAsmNM + 436234593U, // STOCGAsmNO + 436234965U, // STOCGAsmNP + 436238774U, // STOCGAsmNZ + 436234472U, // STOCGAsmO + 436234843U, // STOCGAsmP + 436238662U, // STOCGAsmZ + 453027942U, // STOSM + 134245331U, // STPQ + 3192590U, // STPT + 3192894U, // STPX + 469800358U, // STRAG + 268461650U, // STRL + 134248427U, // STRV + 134240310U, // STRVG + 134242394U, // STRVH + 3184887U, // STSCH + 3187169U, // STSI + 33571212U, // STURA + 33576845U, // STURG + 134248734U, // STY + 30646U, // SU + 16806618U, // SUR + 280934U, // SVC + 30741U, // SW + 16806634U, // SWR + 16805316U, // SXBR + 16806708U, // SXR + 1107325626U, // SXTR + 1107313023U, // SXTRA + 30991U, // SY + 3192626U, // TABORT + 15614U, // TAM + 33582075U, // TAR + 33572676U, // TB + 218131957U, // TBDR + 218131974U, // TBEDR + 352364705U, // TBEGIN + 352356608U, // TBEGINC + 134234680U, // TCDB + 134235080U, // TCEB + 134236063U, // TCXB + 134248073U, // TDCDT + 134248111U, // TDCET + 134248292U, // TDCXT + 134248080U, // TDGDT + 134248118U, // TDGET + 134248299U, // TDGXT + 15466U, // TEND + 33582729U, // THDER + 33582629U, // THDR + 453027958U, // TM + 385898999U, // TMHH + 385901508U, // TMHL + 385899455U, // TMLH + 385901632U, // TMLL + 453032193U, // TMY + 3206027U, // TP + 3187084U, // TPI + 469808886U, // TPROT + 302051631U, // TR + 1107315251U, // TRACE + 1107318242U, // TRACG + 15330U, // TRAP2 + 3178533U, // TRAP4 + 33575441U, // TRE + 1107323351U, // TROO + 33581527U, // TROOOpt + 1107326717U, // TROT + 33584893U, // TROTOpt + 302053178U, // TRT + 419648122U, // TRTE + 3363450U, // TRTEOpt + 1107323395U, // TRTO + 33581571U, // TRTOOpt + 302051887U, // TRTR + 419648015U, // TRTRE + 3363343U, // TRTREOpt + 1107326807U, // TRTT + 33584983U, // TRTTOpt + 3192396U, // TS + 3184888U, // TSCH + 117498500U, // UNPK + 302039132U, // UNPKA + 302053281U, // UNPKU + 15690U, // UPT + 1107313060U, // VA + 1107313093U, // VAB + 1107314837U, // VAC + 1107314846U, // VACC + 1107313110U, // VACCB + 1107314852U, // VACCC + 1107323809U, // VACCCQ + 1107317420U, // VACCF + 1107318249U, // VACCG + 1107318967U, // VACCH + 1107323802U, // VACCQ + 1107323796U, // VACQ + 1107317409U, // VAF + 1107318196U, // VAG + 1107318901U, // VAH + 1107323412U, // VAP + 1107323791U, // VAQ + 1107318787U, // VAVG + 1107313749U, // VAVGB + 1107317598U, // VAVGF + 1107318363U, // VAVGG + 1107319189U, // VAVGH + 1107321741U, // VAVGL + 1107313880U, // VAVGLB + 1107317755U, // VAVGLF + 1107318473U, // VAVGLG + 1107319569U, // VAVGLH + 1107322931U, // VBPERM + 1107318287U, // VCDG + 1107313712U, // VCDGB + 1107318466U, // VCDLG + 1107313733U, // VCDLGB + 1107323817U, // VCEQ + 1107314063U, // VCEQB + 1107325965U, // VCEQBS + 1107317962U, // VCEQF + 1107326248U, // VCEQFS + 1107318654U, // VCEQG + 1107326340U, // VCEQGS + 1107320718U, // VCEQH + 1107326414U, // VCEQHS + 1107315084U, // VCGD + 1107313310U, // VCGDB + 1107319044U, // VCH + 1107313770U, // VCHB + 1107325950U, // VCHBS + 1107317619U, // VCHF + 1107326233U, // VCHFS + 1107318385U, // VCHG + 1107326325U, // VCHGS + 1107319210U, // VCHH + 1107326399U, // VCHHS + 1107321748U, // VCHL + 1107313888U, // VCHLB + 1107325957U, // VCHLBS + 1107317763U, // VCHLF + 1107326240U, // VCHLFS + 1107318481U, // VCHLG + 1107326332U, // VCHLGS + 1107319577U, // VCHLH + 1107326406U, // VCHLHS + 1107322968U, // VCKSM + 1107315090U, // VCLGD + 1107313324U, // VCLGDB + 1107327380U, // VCLZ + 33572983U, // VCLZB + 33576298U, // VCLZF + 33577041U, // VCLZG + 33579175U, // VCLZH + 1107323440U, // VCP + 1107327539U, // VCTZ + 33572990U, // VCTZB + 33576305U, // VCTZF + 33577048U, // VCTZG + 33579182U, // VCTZH + 1107314513U, // VCVB + 1107318235U, // VCVBG + 1107315156U, // VCVD + 1107318299U, // VCVDG + 1107323458U, // VDP + 1107314859U, // VEC + 33571293U, // VECB + 33575603U, // VECF + 33576432U, // VECG + 33577150U, // VECH + 1107321660U, // VECL + 33572049U, // VECLB + 33575924U, // VECLF + 33576635U, // VECLG + 33577700U, // VECLH + 1090545538U, // VERIM + 1090536770U, // VERIMB + 1090540678U, // VERIMF + 1090541361U, // VERIMG + 1090543082U, // VERIMH + 1107321933U, // VERLL + 1107313903U, // VERLLB + 1107317809U, // VERLLF + 1107318488U, // VERLLG + 1107319735U, // VERLLH + 1107326927U, // VERLLV + 1107314526U, // VERLLVB + 1107318048U, // VERLLVF + 1107318800U, // VERLLVG + 1107320890U, // VERLLVH + 1107322469U, // VESL + 1107313953U, // VESLB + 1107317852U, // VESLF + 1107318529U, // VESLG + 1107320178U, // VESLH + 1107326943U, // VESLV + 1107314544U, // VESLVB + 1107318066U, // VESLVF + 1107318818U, // VESLVG + 1107320908U, // VESLVH + 1107312929U, // VESRA + 1107313078U, // VESRAB + 1107317401U, // VESRAF + 1107318174U, // VESRAG + 1107318893U, // VESRAH + 1107326913U, // VESRAV + 1107314504U, // VESRAVB + 1107318032U, // VESRAVF + 1107318778U, // VESRAVG + 1107320874U, // VESRAVH + 1107322436U, // VESRL + 1107313938U, // VESRLB + 1107317844U, // VESRLF + 1107318521U, // VESRLG + 1107320170U, // VESRLH + 1107326935U, // VESRLV + 1107314535U, // VESRLVB + 1107318057U, // VESRLVF + 1107318809U, // VESRLVG + 1107320899U, // VESRLVH + 1107312714U, // VFA + 1107313137U, // VFADB + 1107315172U, // VFAE + 1107313594U, // VFAEB + 1107325925U, // VFAEBS + 1107317447U, // VFAEF + 1107326208U, // VFAEFS + 1107319049U, // VFAEH + 1107326374U, // VFAEHS + 1107314774U, // VFAEZB + 1107326160U, // VFAEZBS + 1107318089U, // VFAEZF + 1107326297U, // VFAEZFS + 1107320966U, // VFAEZH + 1107326458U, // VFAEZHS + 1107314102U, // VFASB + 1107315258U, // VFCE + 1107313228U, // VFCEDB + 1107325813U, // VFCEDBS + 1107314187U, // VFCESB + 1107325982U, // VFCESBS + 1107318980U, // VFCH + 1107313340U, // VFCHDB + 1107325889U, // VFCHDBS + 1107315383U, // VFCHE + 1107313244U, // VFCHEDB + 1107325831U, // VFCHEDBS + 1107314203U, // VFCHESB + 1107326000U, // VFCHESBS + 1107314255U, // VFCHSB + 1107326058U, // VFCHSBS + 1107315079U, // VFD + 1107313214U, // VFDDB + 1107314173U, // VFDSB + 1107315288U, // VFEE + 1107313634U, // VFEEB + 1107325933U, // VFEEBS + 1107317468U, // VFEEF + 1107326216U, // VFEEFS + 1107319063U, // VFEEH + 1107326382U, // VFEEHS + 1107314782U, // VFEEZB + 1107326169U, // VFEEZBS + 1107318097U, // VFEEZF + 1107326306U, // VFEEZFS + 1107320974U, // VFEEZH + 1107326467U, // VFEEZHS + 1107316973U, // VFENE + 1107313679U, // VFENEB + 1107325941U, // VFENEBS + 1107317508U, // VFENEF + 1107326224U, // VFENEFS + 1107319097U, // VFENEH + 1107326390U, // VFENEHS + 1107314798U, // VFENEZB + 1107326178U, // VFENEZBS + 1107318113U, // VFENEZF + 1107326315U, // VFENEZFS + 1107320990U, // VFENEZH + 1107326476U, // VFENEZHS + 1107321127U, // VFI + 1107313390U, // VFIDB + 1107314305U, // VFISB + 1107313280U, // VFKEDB + 1107325871U, // VFKEDBS + 1107314239U, // VFKESB + 1107326040U, // VFKESBS + 1107313356U, // VFKHDB + 1107325907U, // VFKHDBS + 1107313262U, // VFKHEDB + 1107325851U, // VFKHEDBS + 1107314221U, // VFKHESB + 1107326020U, // VFKHESBS + 1107314271U, // VFKHSB + 1107326076U, // VFKHSBS + 33571368U, // VFLCDB + 33572333U, // VFLCSB + 1107321889U, // VFLL + 33584675U, // VFLLS + 33571626U, // VFLNDB + 33572534U, // VFLNSB + 33571660U, // VFLPDB + 33572568U, // VFLPSB + 1107325070U, // VFLR + 1107315132U, // VFLRD + 1107322676U, // VFM + 1107312757U, // VFMA + 1107313151U, // VFMADB + 1107314116U, // VFMASB + 1107327012U, // VFMAX + 1107313564U, // VFMAXDB + 1107314477U, // VFMAXSB + 1107313418U, // VFMDB + 1107323055U, // VFMIN + 1107313432U, // VFMINDB + 1107314340U, // VFMINSB + 1107326513U, // VFMS + 1107314326U, // VFMSB + 1107313530U, // VFMSDB + 1107314438U, // VFMSSB + 1107312768U, // VFNMA + 1107313167U, // VFNMADB + 1107314132U, // VFNMASB + 1107326519U, // VFNMS + 1107313546U, // VFNMSDB + 1107314454U, // VFNMSSB + 1107323388U, // VFPSO + 1107313466U, // VFPSODB + 1107314374U, // VFPSOSB + 1107326282U, // VFS + 1107313516U, // VFSDB + 1107323865U, // VFSQ + 33571676U, // VFSQDB + 33572584U, // VFSQSB + 1107314424U, // VFSSB + 1107321040U, // VFTCI + 1107313372U, // VFTCIDB + 1107314287U, // VFTCISB + 385902340U, // VGBM + 3758117603U, // VGEF + 536892969U, // VGEG + 1107322670U, // VGFM + 1107312750U, // VGFMA + 1107313070U, // VGFMAB + 1107317393U, // VGFMAF + 1107318160U, // VGFMAG + 1107318879U, // VGFMAH + 1107313973U, // VGFMB + 1107317875U, // VGFMF + 1107318564U, // VGFMG + 1107320285U, // VGFMH + 1476421453U, // VGM + 1476412732U, // VGMB + 1476416640U, // VGMF + 1476417323U, // VGMG + 1476419044U, // VGMH + 1107325500U, // VISTR + 1107314094U, // VISTRB + 33584149U, // VISTRBS + 1107317977U, // VISTRF + 33584432U, // VISTRFS + 1107320755U, // VISTRH + 33584598U, // VISTRHS + 134244068U, // VL + 1207976400U, // VLBB + 1107314934U, // VLC + 33571299U, // VLCB + 33575609U, // VLCF + 33576444U, // VLCG + 33577168U, // VLCH + 1107315277U, // VLDE + 33571790U, // VLDEB + 1073759235U, // VLEB + 1107315068U, // VLED + 1107313296U, // VLEDB + 1073763064U, // VLEF + 1073763887U, // VLEG + 1073764653U, // VLEH + 1140868264U, // VLEIB + 1140872145U, // VLEIF + 1140872851U, // VLEIG + 1140873769U, // VLEIH + 1107326921U, // VLGV + 1107314519U, // VLGVB + 1107318041U, // VLGVF + 1107318793U, // VLGVG + 1107320883U, // VLGVH + 1459645093U, // VLIP + 1107321945U, // VLL + 1207990584U, // VLLEZ + 134236262U, // VLLEZB + 134239577U, // VLLEZF + 134240329U, // VLLEZG + 134242454U, // VLLEZH + 134239338U, // VLLEZLF + 1107322774U, // VLM + 1107323567U, // VLP + 33572233U, // VLPB + 33576132U, // VLPF + 33576812U, // VLPG + 33578882U, // VLPH + 33583326U, // VLR + 1207986759U, // VLREP + 134235514U, // VLREPB + 134239413U, // VLREPF + 134240093U, // VLREPG + 134242163U, // VLREPH + 1509975608U, // VLRL + 1107325130U, // VLRLR + 1090541610U, // VLVG + 1090536540U, // VLVGB + 1090540389U, // VLVGF + 1090541154U, // VLVGG + 1090541980U, // VLVGH + 1107323502U, // VLVGP + 1107315183U, // VMAE + 1107313601U, // VMAEB + 1107317454U, // VMAEF + 1107319056U, // VMAEH + 1107318887U, // VMAH + 1107313763U, // VMAHB + 1107317612U, // VMAHF + 1107319203U, // VMAHH + 1107321598U, // VMAL + 1107313866U, // VMALB + 1107316148U, // VMALE + 1107313652U, // VMALEB + 1107317481U, // VMALEF + 1107319070U, // VMALEH + 1107317741U, // VMALF + 1107319453U, // VMALH + 1107313776U, // VMALHB + 1107317656U, // VMALHF + 1107319258U, // VMALHH + 1107326965U, // VMALHW + 1107323177U, // VMALO + 1107314021U, // VMALOB + 1107317920U, // VMALOF + 1107320670U, // VMALOH + 1107323082U, // VMAO + 1107314014U, // VMAOB + 1107317913U, // VMAOF + 1107320663U, // VMAOH + 1107316889U, // VME + 1107313673U, // VMEB + 1107317502U, // VMEF + 1107319091U, // VMEH + 1107320325U, // VMH + 1107313799U, // VMHB + 1107317685U, // VMHF + 1107319293U, // VMHH + 1107321950U, // VML + 1107313911U, // VMLB + 1107316396U, // VMLE + 1107313660U, // VMLEB + 1107317489U, // VMLEF + 1107319078U, // VMLEH + 1107317817U, // VMLF + 1107319749U, // VMLH + 1107313784U, // VMLHB + 1107317670U, // VMLHF + 1107319272U, // VMLHH + 1107326973U, // VMLHW + 1107323184U, // VMLO + 1107314029U, // VMLOB + 1107317928U, // VMLOF + 1107320678U, // VMLOH + 1107323062U, // VMN + 1107314008U, // VMNB + 1107317907U, // VMNF + 1107318609U, // VMNG + 1107320550U, // VMNH + 1107322175U, // VMNL + 1107313917U, // VMNLB + 1107317823U, // VMNLF + 1107318507U, // VMNLG + 1107320002U, // VMNLH + 1107323200U, // VMO + 1107314036U, // VMOB + 1107317935U, // VMOF + 1107320685U, // VMOH + 1107323572U, // VMP + 1107320749U, // VMRH + 1107313812U, // VMRHB + 1107317698U, // VMRHF + 1107318391U, // VMRHG + 1107319306U, // VMRHH + 1107322430U, // VMRL + 1107313931U, // VMRLB + 1107317837U, // VMRLF + 1107318514U, // VMRLG + 1107320163U, // VMRLH + 1107322475U, // VMSL + 1107318536U, // VMSLG + 1107323775U, // VMSP + 1107327023U, // VMX + 1107314684U, // VMXB + 1107318074U, // VMXF + 1107318851U, // VMXG + 1107320934U, // VMXH + 1107322600U, // VMXL + 1107313966U, // VMXLB + 1107317859U, // VMXLF + 1107318550U, // VMXLG + 1107320265U, // VMXLH + 1107323073U, // VN + 1107314953U, // VNC + 1107323067U, // VNN + 1107323346U, // VNO + 1107327028U, // VNX + 1107323402U, // VO + 1107314969U, // VOC + 3166593U, // VONE + 1107321047U, // VPDI + 1107322939U, // VPERM + 1107321482U, // VPK + 1107317735U, // VPKF + 1107318438U, // VPKG + 1107319447U, // VPKH + 1107326492U, // VPKLS + 1107317998U, // VPKLSF + 1107326273U, // VPKLSFS + 1107318713U, // VPKLSG + 1107326356U, // VPKLSGS + 1107320770U, // VPKLSH + 1107326439U, // VPKLSHS + 1107326486U, // VPKS + 1107317991U, // VPKSF + 1107326265U, // VPKSFS + 1107318706U, // VPKSG + 1107326348U, // VPKSGS + 1107320763U, // VPKSH + 1107326431U, // VPKSHS + 1509980558U, // VPKZ + 1107326587U, // VPOPCT + 33572671U, // VPOPCTB + 33576187U, // VPOPCTF + 33576919U, // VPOPCTG + 33578959U, // VPOPCTH + 1107323706U, // VPSOP + 1107323470U, // VREP + 1107314050U, // VREPB + 1107317949U, // VREPF + 1107318629U, // VREPG + 1107320699U, // VREPH + 1358979461U, // VREPI + 285230274U, // VREPIB + 285234136U, // VREPIF + 285234842U, // VREPIG + 285235792U, // VREPIH + 1107323759U, // VRP + 1107326544U, // VS + 1107314472U, // VSB + 1107321019U, // VSBCBI + 1107323823U, // VSBCBIQ + 1107321034U, // VSBI + 1107323840U, // VSBIQ + 1107321027U, // VSCBI + 1107313819U, // VSCBIB + 1107317705U, // VSCBIF + 1107318411U, // VSCBIG + 1107319324U, // VSCBIH + 1107323832U, // VSCBIQ + 2701152981U, // VSCEF + 3774895650U, // VSCEG + 1107323452U, // VSDP + 1107318338U, // VSEG + 33571902U, // VSEGB + 33575709U, // VSEGF + 33577334U, // VSEGH + 1107321709U, // VSEL + 1107318006U, // VSF + 1107318726U, // VSG + 1107320778U, // VSH + 1107322481U, // VSL + 1107313960U, // VSLB + 1107313411U, // VSLDB + 1107323781U, // VSP + 1107323871U, // VSQ + 1107312936U, // VSRA + 1107313086U, // VSRAB + 1107322443U, // VSRL + 1107313946U, // VSRLB + 1107323753U, // VSRP + 134248274U, // VST + 1207976995U, // VSTEB + 1207980812U, // VSTEF + 1207981640U, // VSTEG + 1207982401U, // VSTEH + 1107322590U, // VSTL + 1107322996U, // VSTM + 1107315004U, // VSTRC + 1107313129U, // VSTRCB + 1107325804U, // VSTRCBS + 1107317439U, // VSTRCF + 1107326199U, // VSTRCFS + 1107319011U, // VSTRCH + 1107326365U, // VSTRCHS + 1107314765U, // VSTRCZB + 1107326150U, // VSTRCZBS + 1107318080U, // VSTRCZF + 1107326287U, // VSTRCZFS + 1107320957U, // VSTRCZH + 1107326448U, // VSTRCZHS + 1509975633U, // VSTRL + 1107325137U, // VSTRLR + 1107323007U, // VSUM + 1107314001U, // VSUMB + 1107318596U, // VSUMG + 1107317564U, // VSUMGF + 1107319176U, // VSUMGH + 1107320318U, // VSUMH + 1107323847U, // VSUMQ + 1107317969U, // VSUMQF + 1107318661U, // VSUMQG + 33581178U, // VTM + 3173258U, // VTP + 1107320712U, // VUPH + 33571981U, // VUPHB + 33575867U, // VUPHF + 33577475U, // VUPHH + 1509980551U, // VUPKZ + 1107322288U, // VUPL + 33572100U, // VUPLB + 33576006U, // VUPLF + 1107320129U, // VUPLH + 33571967U, // VUPLHB + 33575853U, // VUPLHF + 33577455U, // VUPLHH + 33585156U, // VUPLHW + 1107321926U, // VUPLL + 33572071U, // VUPLLB + 33575977U, // VUPLLF + 33577903U, // VUPLLH + 1107327051U, // VX + 3172836U, // VZERO + 1107313719U, // WCDGB + 1107313741U, // WCDLGB + 1107313317U, // WCGDB + 1107313332U, // WCLGDB + 1107313144U, // WFADB + 1107314109U, // WFASB + 1107314552U, // WFAXB + 1107314869U, // WFC + 33571361U, // WFCDB + 1107313236U, // WFCEDB + 1107325822U, // WFCEDBS + 1107314195U, // WFCESB + 1107325991U, // WFCESBS + 1107314604U, // WFCEXB + 1107326094U, // WFCEXBS + 1107313348U, // WFCHDB + 1107325898U, // WFCHDBS + 1107313253U, // WFCHEDB + 1107325841U, // WFCHEDBS + 1107314212U, // WFCHESB + 1107326010U, // WFCHESBS + 1107314612U, // WFCHEXB + 1107326103U, // WFCHEXBS + 1107314263U, // WFCHSB + 1107326067U, // WFCHSBS + 1107314638U, // WFCHXB + 1107326132U, // WFCHXBS + 33572326U, // WFCSB + 33572752U, // WFCXB + 1107313221U, // WFDDB + 1107314180U, // WFDSB + 1107314597U, // WFDXB + 1107313397U, // WFIDB + 1107314312U, // WFISB + 1107314663U, // WFIXB + 1107321423U, // WFK + 33571580U, // WFKDB + 1107313288U, // WFKEDB + 1107325880U, // WFKEDBS + 1107314247U, // WFKESB + 1107326049U, // WFKESBS + 1107314630U, // WFKEXB + 1107326123U, // WFKEXBS + 1107313364U, // WFKHDB + 1107325916U, // WFKHDBS + 1107313271U, // WFKHEDB + 1107325861U, // WFKHEDBS + 1107314230U, // WFKHESB + 1107326030U, // WFKHESBS + 1107314621U, // WFKHEXB + 1107326113U, // WFKHEXBS + 1107314279U, // WFKHSB + 1107326085U, // WFKHSBS + 1107314646U, // WFKHXB + 1107326141U, // WFKHXBS + 33572495U, // WFKSB + 33572846U, // WFKXB + 33571376U, // WFLCDB + 33572341U, // WFLCSB + 33572759U, // WFLCXB + 33573273U, // WFLLD + 33584682U, // WFLLS + 33571634U, // WFLNDB + 33572542U, // WFLNSB + 33572875U, // WFLNXB + 33571668U, // WFLPDB + 33572576U, // WFLPSB + 33572892U, // WFLPXB + 1107315139U, // WFLRD + 1107327044U, // WFLRX + 1107313159U, // WFMADB + 1107314124U, // WFMASB + 1107314559U, // WFMAXB + 1107313573U, // WFMAXDB + 1107314486U, // WFMAXSB + 1107314756U, // WFMAXXB + 1107313425U, // WFMDB + 1107313441U, // WFMINDB + 1107314349U, // WFMINSB + 1107314690U, // WFMINXB + 1107314333U, // WFMSB + 1107313538U, // WFMSDB + 1107314446U, // WFMSSB + 1107314739U, // WFMSXB + 1107314677U, // WFMXB + 1107313176U, // WFNMADB + 1107314141U, // WFNMASB + 1107314567U, // WFNMAXB + 1107313555U, // WFNMSDB + 1107314463U, // WFNMSSB + 1107314747U, // WFNMSXB + 1107313475U, // WFPSODB + 1107314383U, // WFPSOSB + 1107314707U, // WFPSOXB + 1107313523U, // WFSDB + 33571684U, // WFSQDB + 33572592U, // WFSQSB + 33572900U, // WFSQXB + 1107314431U, // WFSSB + 1107314732U, // WFSXB + 1107313381U, // WFTCIDB + 1107314296U, // WFTCISB + 1107314654U, // WFTCIXB + 33571797U, // WLDEB + 1107313303U, // WLEDB + 30753U, // X + 302041451U, // XC + 22591U, // XG + 16805876U, // XGR + 1107321536U, // XGRK + 453026289U, // XI + 100684690U, // XIHF + 100684835U, // XILF + 453032140U, // XIY + 16806640U, // XR + 1107321569U, // XRK + 15511U, // XSCH + 31011U, // XY + 117500441U, // ZAP + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 512U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 8U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 8U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 8U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 8U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 512U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 0U, // BPP + 0U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 16U, // BRXH + 16U, // BRXHG + 16U, // BRXLE + 16U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 24U, // BXH + 24U, // BXHG + 24U, // BXLE + 24U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 33U, // CDFBRA + 0U, // CDFR + 33U, // CDFTR + 0U, // CDGBR + 33U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 33U, // CDGTRA + 33U, // CDLFBR + 33U, // CDLFTR + 33U, // CDLGBR + 33U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 24U, // CDS + 24U, // CDSG + 0U, // CDSTR + 24U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 33U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 33U, // CEGBRA + 0U, // CEGR + 33U, // CELFBR + 33U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 41U, // CFDBR + 33U, // CFDBRA + 41U, // CFDR + 33U, // CFDTR + 41U, // CFEBR + 33U, // CFEBRA + 41U, // CFER + 0U, // CFI + 41U, // CFXBR + 33U, // CFXBRA + 41U, // CFXR + 33U, // CFXTR + 0U, // CG + 41U, // CGDBR + 33U, // CGDBRA + 41U, // CGDR + 41U, // CGDTR + 33U, // CGDTRA + 41U, // CGEBR + 33U, // CGEBRA + 41U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 25U, // CGIBAsm + 1U, // CGIBAsmE + 1U, // CGIBAsmH + 1U, // CGIBAsmHE + 1U, // CGIBAsmL + 1U, // CGIBAsmLE + 1U, // CGIBAsmLH + 1U, // CGIBAsmNE + 1U, // CGIBAsmNH + 1U, // CGIBAsmNHE + 1U, // CGIBAsmNL + 1U, // CGIBAsmNLE + 1U, // CGIBAsmNLH + 0U, // CGIJ + 17U, // CGIJAsm + 0U, // CGIJAsmE + 0U, // CGIJAsmH + 0U, // CGIJAsmHE + 0U, // CGIJAsmL + 0U, // CGIJAsmLE + 0U, // CGIJAsmLH + 0U, // CGIJAsmNE + 0U, // CGIJAsmNH + 0U, // CGIJAsmNHE + 0U, // CGIJAsmNL + 0U, // CGIJAsmNLE + 0U, // CGIJAsmNLH + 0U, // CGIT + 48U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 41U, // CGRB + 8752U, // CGRBAsm + 56U, // CGRBAsmE + 56U, // CGRBAsmH + 56U, // CGRBAsmHE + 56U, // CGRBAsmL + 56U, // CGRBAsmLE + 56U, // CGRBAsmLH + 56U, // CGRBAsmNE + 56U, // CGRBAsmNH + 56U, // CGRBAsmNHE + 56U, // CGRBAsmNL + 56U, // CGRBAsmNLE + 56U, // CGRBAsmNLH + 2U, // CGRJ + 16944U, // CGRJAsm + 64U, // CGRJAsmE + 64U, // CGRJAsmH + 64U, // CGRJAsmHE + 64U, // CGRJAsmL + 64U, // CGRJAsmLE + 64U, // CGRJAsmLH + 64U, // CGRJAsmNE + 64U, // CGRJAsmNH + 64U, // CGRJAsmNHE + 64U, // CGRJAsmNL + 64U, // CGRJAsmNLE + 64U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 48U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 41U, // CGXBR + 33U, // CGXBRA + 41U, // CGXR + 41U, // CGXTR + 33U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 25U, // CIBAsm + 1U, // CIBAsmE + 1U, // CIBAsmH + 1U, // CIBAsmHE + 1U, // CIBAsmL + 1U, // CIBAsmLE + 1U, // CIBAsmLH + 1U, // CIBAsmNE + 1U, // CIBAsmNH + 1U, // CIBAsmNHE + 1U, // CIBAsmNL + 1U, // CIBAsmNLE + 1U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 17U, // CIJAsm + 0U, // CIJAsmE + 0U, // CIJAsmH + 0U, // CIJAsmHE + 0U, // CIJAsmL + 0U, // CIJAsmLE + 0U, // CIJAsmLH + 0U, // CIJAsmNE + 0U, // CIJAsmNH + 0U, // CIJAsmNHE + 0U, // CIJAsmNL + 0U, // CIJAsmNLE + 0U, // CIJAsmNLH + 0U, // CIT + 48U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 72U, // CLCLE + 72U, // CLCLU + 33U, // CLFDBR + 33U, // CLFDTR + 33U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 48U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 33U, // CLFXBR + 33U, // CLFXTR + 0U, // CLG + 33U, // CLGDBR + 33U, // CLGDTR + 33U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 25U, // CLGIBAsm + 1U, // CLGIBAsmE + 1U, // CLGIBAsmH + 1U, // CLGIBAsmHE + 1U, // CLGIBAsmL + 1U, // CLGIBAsmLE + 1U, // CLGIBAsmLH + 1U, // CLGIBAsmNE + 1U, // CLGIBAsmNH + 1U, // CLGIBAsmNHE + 1U, // CLGIBAsmNL + 1U, // CLGIBAsmNLE + 1U, // CLGIBAsmNLH + 0U, // CLGIJ + 17U, // CLGIJAsm + 0U, // CLGIJAsmE + 0U, // CLGIJAsmH + 0U, // CLGIJAsmHE + 0U, // CLGIJAsmL + 0U, // CLGIJAsmLE + 0U, // CLGIJAsmLH + 0U, // CLGIJAsmNE + 0U, // CLGIJAsmNH + 0U, // CLGIJAsmNHE + 0U, // CLGIJAsmNL + 0U, // CLGIJAsmNLE + 0U, // CLGIJAsmNLH + 0U, // CLGIT + 48U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 41U, // CLGRB + 8752U, // CLGRBAsm + 56U, // CLGRBAsmE + 56U, // CLGRBAsmH + 56U, // CLGRBAsmHE + 56U, // CLGRBAsmL + 56U, // CLGRBAsmLE + 56U, // CLGRBAsmLH + 56U, // CLGRBAsmNE + 56U, // CLGRBAsmNH + 56U, // CLGRBAsmNHE + 56U, // CLGRBAsmNL + 56U, // CLGRBAsmNLE + 56U, // CLGRBAsmNLH + 2U, // CLGRJ + 16944U, // CLGRJAsm + 64U, // CLGRJAsmE + 64U, // CLGRJAsmH + 64U, // CLGRJAsmHE + 64U, // CLGRJAsmL + 64U, // CLGRJAsmLE + 64U, // CLGRJAsmLH + 64U, // CLGRJAsmNE + 64U, // CLGRJAsmNH + 64U, // CLGRJAsmNHE + 64U, // CLGRJAsmNL + 64U, // CLGRJAsmNLE + 64U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 48U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 80U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 33U, // CLGXBR + 33U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 25U, // CLIBAsm + 1U, // CLIBAsmE + 1U, // CLIBAsmH + 1U, // CLIBAsmHE + 1U, // CLIBAsmL + 1U, // CLIBAsmLE + 1U, // CLIBAsmLH + 1U, // CLIBAsmNE + 1U, // CLIBAsmNH + 1U, // CLIBAsmNHE + 1U, // CLIBAsmNL + 1U, // CLIBAsmNLE + 1U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 17U, // CLIJAsm + 0U, // CLIJAsmE + 0U, // CLIJAsmH + 0U, // CLIJAsmHE + 0U, // CLIJAsmL + 0U, // CLIJAsmLE + 0U, // CLIJAsmLH + 0U, // CLIJAsmNE + 0U, // CLIJAsmNH + 0U, // CLIJAsmNHE + 0U, // CLIJAsmNL + 0U, // CLIJAsmNLE + 0U, // CLIJAsmNLH + 0U, // CLIY + 1U, // CLM + 1U, // CLMH + 1U, // CLMY + 0U, // CLR + 41U, // CLRB + 8752U, // CLRBAsm + 56U, // CLRBAsmE + 56U, // CLRBAsmH + 56U, // CLRBAsmHE + 56U, // CLRBAsmL + 56U, // CLRBAsmLE + 56U, // CLRBAsmLH + 56U, // CLRBAsmNE + 56U, // CLRBAsmNH + 56U, // CLRBAsmNHE + 56U, // CLRBAsmNL + 56U, // CLRBAsmNLE + 56U, // CLRBAsmNLH + 2U, // CLRJ + 16944U, // CLRJAsm + 64U, // CLRJAsmE + 64U, // CLRJAsmH + 64U, // CLRJAsmHE + 64U, // CLRJAsmL + 64U, // CLRJAsmLE + 64U, // CLRJAsmLH + 64U, // CLRJAsmNE + 64U, // CLRJAsmNH + 64U, // CLRJAsmNHE + 64U, // CLRJAsmNL + 64U, // CLRJAsmNLE + 64U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 48U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 80U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 88U, // CPSDRdd + 88U, // CPSDRds + 88U, // CPSDRsd + 88U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 41U, // CRB + 8752U, // CRBAsm + 56U, // CRBAsmE + 56U, // CRBAsmH + 56U, // CRBAsmHE + 56U, // CRBAsmL + 56U, // CRBAsmLE + 56U, // CRBAsmLH + 56U, // CRBAsmNE + 56U, // CRBAsmNH + 56U, // CRBAsmNHE + 56U, // CRBAsmNL + 56U, // CRBAsmNLE + 56U, // CRBAsmNLH + 600U, // CRDTE + 88U, // CRDTEOpt + 2U, // CRJ + 16944U, // CRJAsm + 64U, // CRJAsmE + 64U, // CRJAsmH + 64U, // CRJAsmHE + 64U, // CRJAsmL + 64U, // CRJAsmLE + 64U, // CRJAsmLH + 64U, // CRJAsmNE + 64U, // CRJAsmNH + 64U, // CRJAsmNHE + 64U, // CRJAsmNL + 64U, // CRJAsmNLE + 64U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 48U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 24U, // CS + 0U, // CSCH + 48U, // CSDTR + 24U, // CSG + 0U, // CSP + 0U, // CSPG + 96U, // CSST + 48U, // CSXTR + 24U, // CSY + 104U, // CU12 + 0U, // CU12Opt + 104U, // CU14 + 0U, // CU14Opt + 104U, // CU21 + 0U, // CU21Opt + 104U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 104U, // CUTFU + 0U, // CUTFUOpt + 104U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 33U, // CXFBRA + 0U, // CXFR + 33U, // CXFTR + 0U, // CXGBR + 33U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 33U, // CXGTRA + 33U, // CXLFBR + 33U, // CXLFTR + 33U, // CXLGBR + 33U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 512U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 56U, // DIAG + 25200U, // DIDBR + 25200U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 512U, // DXTRA + 0U, // EAR + 56U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 96U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 41U, // FIDBR + 33U, // FIDBRA + 0U, // FIDR + 33U, // FIDTR + 41U, // FIEBR + 33U, // FIEBRA + 0U, // FIER + 41U, // FIXBR + 33U, // FIXBRA + 0U, // FIXR + 33U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 600U, // IDTE + 88U, // IDTEOpt + 88U, // IEDTR + 88U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 512U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 2U, // InsnRI + 1145U, // InsnRIE + 0U, // InsnRIL + 2U, // InsnRILU + 2U, // InsnRIS + 0U, // InsnRR + 41U, // InsnRRE + 1657U, // InsnRRF + 34937U, // InsnRRS + 2681U, // InsnRS + 2681U, // InsnRSE + 1145U, // InsnRSI + 2681U, // InsnRSY + 0U, // InsnRX + 0U, // InsnRXE + 3193U, // InsnRXF + 0U, // InsnRXY + 0U, // InsnS + 3U, // InsnSI + 3U, // InsnSIL + 3U, // InsnSIY + 0U, // InsnSS + 41U, // InsnSSE + 3705U, // InsnSSF + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 88U, // KMA + 0U, // KMAC + 0U, // KMC + 88U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 56U, // LAA + 56U, // LAAG + 56U, // LAAL + 56U, // LAALG + 0U, // LAE + 0U, // LAEY + 56U, // LAM + 56U, // LAMY + 56U, // LAN + 56U, // LANG + 56U, // LAO + 56U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 56U, // LAX + 56U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBH + 0U, // LBR + 104U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 56U, // LCTL + 56U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 48U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 33U, // LDXBRA + 0U, // LDXR + 33U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 33U, // LEDBRA + 0U, // LEDR + 33U, // LEDTR + 0U, // LER + 0U, // LEXBR + 33U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 56U, // LM + 41528U, // LMD + 56U, // LMG + 56U, // LMH + 56U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 104U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 104U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 128U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 104U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 128U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 128U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 128U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 128U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 128U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 24U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 24U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 25200U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 48U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 136U, // MAD + 136U, // MADB + 112U, // MADBR + 112U, // MADR + 136U, // MAE + 136U, // MAEB + 112U, // MAEBR + 112U, // MAER + 136U, // MAY + 136U, // MAYH + 112U, // MAYHR + 136U, // MAYL + 112U, // MAYLR + 112U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 512U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 136U, // MSD + 136U, // MSDB + 112U, // MSDBR + 112U, // MSDR + 136U, // MSE + 136U, // MSEB + 112U, // MSEBR + 112U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 72U, // MVCLE + 72U, // MVCLU + 96U, // MVCOS + 0U, // MVCP + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 512U, // MXTRA + 144U, // MY + 144U, // MYH + 0U, // MYHR + 144U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 41584U, // PLO + 0U, // POPCNT + 48U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 25200U, // QADTR + 25200U, // QAXTR + 0U, // QCTRI + 0U, // QSI + 0U, // RCHP + 49816U, // RISBG + 49816U, // RISBG32 + 49816U, // RISBGN + 49816U, // RISBHG + 49816U, // RISBLG + 56U, // RLL + 56U, // RLLG + 49816U, // RNSBG + 49816U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 25200U, // RRDTR + 25200U, // RRXTR + 0U, // RSCH + 49816U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 512U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 56U, // SIGP + 0U, // SL + 0U, // SLA + 56U, // SLAG + 56U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 144U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 56U, // SLLG + 56U, // SLLK + 0U, // SLR + 0U, // SLRK + 144U, // SLXT + 0U, // SLY + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 56U, // SRAG + 56U, // SRAK + 0U, // SRDA + 0U, // SRDL + 144U, // SRDT + 0U, // SRK + 0U, // SRL + 56U, // SRLG + 56U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 160U, // SRP + 0U, // SRST + 0U, // SRSTU + 144U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 48U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 56U, // STAM + 56U, // STAMY + 0U, // STAP + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 1U, // STCM + 1U, // STCMH + 1U, // STCMY + 0U, // STCPS + 0U, // STCRW + 56U, // STCTG + 56U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 56U, // STM + 56U, // STMG + 56U, // STMH + 56U, // STMY + 0U, // STNSM + 0U, // STOC + 128U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 128U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 128U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 512U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 41U, // TBDR + 41U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 56U, // TRACE + 56U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 104U, // TROO + 0U, // TROOOpt + 104U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 104U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 104U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 512U, // VA + 0U, // VAB + 57856U, // VAC + 512U, // VACC + 0U, // VACCB + 57856U, // VACCC + 57856U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 57856U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 512U, // VAP + 0U, // VAQ + 512U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 512U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 560U, // VCDG + 560U, // VCDGB + 560U, // VCDLG + 560U, // VCDLGB + 512U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 560U, // VCGD + 560U, // VCGDB + 512U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 512U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 560U, // VCLGD + 560U, // VCLGDB + 48U, // VCLZ + 0U, // VCLZB + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 48U, // VCP + 48U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 48U, // VCVB + 48U, // VCVBG + 10408U, // VCVD + 10408U, // VCVDG + 512U, // VDP + 48U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 48U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 49776U, // VERIM + 49776U, // VERIMB + 49776U, // VERIMF + 49776U, // VERIMG + 49776U, // VERIMH + 25144U, // VERLL + 56U, // VERLLB + 56U, // VERLLF + 56U, // VERLLG + 56U, // VERLLH + 512U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 25144U, // VESL + 56U, // VESLB + 56U, // VESLF + 56U, // VESLG + 56U, // VESLH + 512U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 25144U, // VESRA + 56U, // VESRAB + 56U, // VESRAF + 56U, // VESRAG + 56U, // VESRAH + 512U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 25144U, // VESRL + 56U, // VESRLB + 56U, // VESRLF + 56U, // VESRLG + 56U, // VESRLH + 512U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 512U, // VFA + 0U, // VFADB + 512U, // VFAE + 512U, // VFAEB + 512U, // VFAEBS + 512U, // VFAEF + 512U, // VFAEFS + 512U, // VFAEH + 512U, // VFAEHS + 512U, // VFAEZB + 512U, // VFAEZBS + 512U, // VFAEZF + 512U, // VFAEZFS + 512U, // VFAEZH + 512U, // VFAEZHS + 0U, // VFASB + 512U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 512U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 512U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 512U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 512U, // VFEE + 512U, // VFEEB + 0U, // VFEEBS + 512U, // VFEEF + 0U, // VFEEFS + 512U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 512U, // VFENE + 512U, // VFENEB + 0U, // VFENEBS + 512U, // VFENEF + 0U, // VFENEFS + 512U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 560U, // VFI + 560U, // VFIDB + 560U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 560U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 560U, // VFLR + 560U, // VFLRD + 512U, // VFM + 57856U, // VFMA + 57856U, // VFMADB + 57856U, // VFMASB + 512U, // VFMAX + 512U, // VFMAXDB + 512U, // VFMAXSB + 0U, // VFMDB + 512U, // VFMIN + 512U, // VFMINDB + 512U, // VFMINSB + 57856U, // VFMS + 0U, // VFMSB + 57856U, // VFMSDB + 57856U, // VFMSSB + 57856U, // VFNMA + 57856U, // VFNMADB + 57856U, // VFNMASB + 57856U, // VFNMS + 57856U, // VFNMSDB + 57856U, // VFNMSSB + 560U, // VFPSO + 48U, // VFPSODB + 48U, // VFPSOSB + 512U, // VFS + 0U, // VFSDB + 560U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 688U, // VFTCI + 176U, // VFTCIDB + 176U, // VFTCISB + 0U, // VGBM + 3U, // VGEF + 4U, // VGEG + 512U, // VGFM + 57856U, // VGFMA + 57856U, // VGFMAB + 57856U, // VGFMAF + 57856U, // VGFMAG + 57856U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 36U, // VGM + 44U, // VGMB + 44U, // VGMF + 44U, // VGMG + 44U, // VGMH + 560U, // VISTR + 48U, // VISTRB + 0U, // VISTRBS + 48U, // VISTRF + 0U, // VISTRFS + 48U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 104U, // VLBB + 48U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 560U, // VLDE + 0U, // VLDEB + 160U, // VLEB + 560U, // VLED + 560U, // VLEDB + 184U, // VLEF + 192U, // VLEG + 200U, // VLEH + 128U, // VLEIB + 208U, // VLEIF + 216U, // VLEIG + 224U, // VLEIH + 25144U, // VLGV + 56U, // VLGVB + 56U, // VLGVF + 56U, // VLGVG + 56U, // VLGVH + 48U, // VLIP + 56U, // VLL + 104U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 56U, // VLM + 48U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 104U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 152U, // VLRL + 56U, // VLRLR + 16920U, // VLVG + 24U, // VLVGB + 24U, // VLVGF + 24U, // VLVGG + 24U, // VLVGH + 0U, // VLVGP + 57856U, // VMAE + 57856U, // VMAEB + 57856U, // VMAEF + 57856U, // VMAEH + 57856U, // VMAH + 57856U, // VMAHB + 57856U, // VMAHF + 57856U, // VMAHH + 57856U, // VMAL + 57856U, // VMALB + 57856U, // VMALE + 57856U, // VMALEB + 57856U, // VMALEF + 57856U, // VMALEH + 57856U, // VMALF + 57856U, // VMALH + 57856U, // VMALHB + 57856U, // VMALHF + 57856U, // VMALHH + 57856U, // VMALHW + 57856U, // VMALO + 57856U, // VMALOB + 57856U, // VMALOF + 57856U, // VMALOH + 57856U, // VMAO + 57856U, // VMAOB + 57856U, // VMAOF + 57856U, // VMAOH + 512U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 512U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 512U, // VML + 0U, // VMLB + 512U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 512U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 512U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 512U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 512U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 512U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 512U, // VMP + 512U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 512U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 57856U, // VMSL + 57856U, // VMSLG + 512U, // VMSP + 512U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 512U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 512U, // VPDI + 57856U, // VPERM + 512U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 512U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 512U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 152U, // VPKZ + 48U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 4264U, // VPSOP + 744U, // VREP + 232U, // VREPB + 232U, // VREPF + 232U, // VREPG + 232U, // VREPH + 48U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 512U, // VRP + 512U, // VS + 0U, // VSB + 57856U, // VSBCBI + 57856U, // VSBCBIQ + 57856U, // VSBI + 57856U, // VSBIQ + 512U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 4U, // VSCEF + 4U, // VSCEG + 512U, // VSDP + 48U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 57856U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 512U, // VSLDB + 512U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 0U, // VSRL + 0U, // VSRLB + 4264U, // VSRP + 0U, // VST + 104U, // VSTEB + 240U, // VSTEF + 248U, // VSTEG + 256U, // VSTEH + 56U, // VSTL + 56U, // VSTM + 57856U, // VSTRC + 57856U, // VSTRCB + 57856U, // VSTRCBS + 57856U, // VSTRCF + 57856U, // VSTRCFS + 57856U, // VSTRCH + 57856U, // VSTRCHS + 57856U, // VSTRCZB + 57856U, // VSTRCZBS + 57856U, // VSTRCZF + 57856U, // VSTRCZFS + 57856U, // VSTRCZH + 57856U, // VSTRCZHS + 152U, // VSTRL + 56U, // VSTRLR + 512U, // VSUM + 0U, // VSUMB + 512U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 512U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 48U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 152U, // VUPKZ + 48U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 48U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 48U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 560U, // WCDGB + 560U, // WCDLGB + 560U, // WCGDB + 560U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 560U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 560U, // WFIDB + 560U, // WFISB + 560U, // WFIXB + 560U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 560U, // WFLRD + 560U, // WFLRX + 57856U, // WFMADB + 57856U, // WFMASB + 57856U, // WFMAXB + 512U, // WFMAXDB + 512U, // WFMAXSB + 512U, // WFMAXXB + 0U, // WFMDB + 512U, // WFMINDB + 512U, // WFMINSB + 512U, // WFMINXB + 0U, // WFMSB + 57856U, // WFMSDB + 57856U, // WFMSSB + 57856U, // WFMSXB + 0U, // WFMXB + 57856U, // WFNMADB + 57856U, // WFNMASB + 57856U, // WFNMAXB + 57856U, // WFNMSDB + 57856U, // WFNMSSB + 57856U, // WFNMSXB + 48U, // WFPSODB + 48U, // WFPSOSB + 48U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 176U, // WFTCIDB + 176U, // WFTCISB + 176U, // WFTCIXB + 0U, // WLDEB + 560U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 0U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 0U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 0U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 0U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 0U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 0U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 0U, // BPP + 0U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 0U, // BRXH + 0U, // BRXHG + 0U, // BRXLE + 0U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 0U, // BXH + 0U, // BXHG + 0U, // BXLE + 0U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 0U, // CDFBRA + 0U, // CDFR + 0U, // CDFTR + 0U, // CDGBR + 0U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 0U, // CDGTRA + 0U, // CDLFBR + 0U, // CDLFTR + 0U, // CDLGBR + 0U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 0U, // CDS + 0U, // CDSG + 0U, // CDSTR + 0U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 0U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 0U, // CEGBRA + 0U, // CEGR + 0U, // CELFBR + 0U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 0U, // CFDBR + 0U, // CFDBRA + 0U, // CFDR + 0U, // CFDTR + 0U, // CFEBR + 0U, // CFEBRA + 0U, // CFER + 0U, // CFI + 0U, // CFXBR + 0U, // CFXBRA + 0U, // CFXR + 0U, // CFXTR + 0U, // CG + 0U, // CGDBR + 0U, // CGDBRA + 0U, // CGDR + 0U, // CGDTR + 0U, // CGDTRA + 0U, // CGEBR + 0U, // CGEBRA + 0U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 0U, // CGIBAsm + 0U, // CGIBAsmE + 0U, // CGIBAsmH + 0U, // CGIBAsmHE + 0U, // CGIBAsmL + 0U, // CGIBAsmLE + 0U, // CGIBAsmLH + 0U, // CGIBAsmNE + 0U, // CGIBAsmNH + 0U, // CGIBAsmNHE + 0U, // CGIBAsmNL + 0U, // CGIBAsmNLE + 0U, // CGIBAsmNLH + 0U, // CGIJ + 0U, // CGIJAsm + 0U, // CGIJAsmE + 0U, // CGIJAsmH + 0U, // CGIJAsmHE + 0U, // CGIJAsmL + 0U, // CGIJAsmLE + 0U, // CGIJAsmLH + 0U, // CGIJAsmNE + 0U, // CGIJAsmNH + 0U, // CGIJAsmNHE + 0U, // CGIJAsmNL + 0U, // CGIJAsmNLE + 0U, // CGIJAsmNLH + 0U, // CGIT + 0U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 0U, // CGRB + 0U, // CGRBAsm + 0U, // CGRBAsmE + 0U, // CGRBAsmH + 0U, // CGRBAsmHE + 0U, // CGRBAsmL + 0U, // CGRBAsmLE + 0U, // CGRBAsmLH + 0U, // CGRBAsmNE + 0U, // CGRBAsmNH + 0U, // CGRBAsmNHE + 0U, // CGRBAsmNL + 0U, // CGRBAsmNLE + 0U, // CGRBAsmNLH + 0U, // CGRJ + 0U, // CGRJAsm + 0U, // CGRJAsmE + 0U, // CGRJAsmH + 0U, // CGRJAsmHE + 0U, // CGRJAsmL + 0U, // CGRJAsmLE + 0U, // CGRJAsmLH + 0U, // CGRJAsmNE + 0U, // CGRJAsmNH + 0U, // CGRJAsmNHE + 0U, // CGRJAsmNL + 0U, // CGRJAsmNLE + 0U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 0U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 0U, // CGXBR + 0U, // CGXBRA + 0U, // CGXR + 0U, // CGXTR + 0U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 0U, // CIBAsm + 0U, // CIBAsmE + 0U, // CIBAsmH + 0U, // CIBAsmHE + 0U, // CIBAsmL + 0U, // CIBAsmLE + 0U, // CIBAsmLH + 0U, // CIBAsmNE + 0U, // CIBAsmNH + 0U, // CIBAsmNHE + 0U, // CIBAsmNL + 0U, // CIBAsmNLE + 0U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 0U, // CIJAsm + 0U, // CIJAsmE + 0U, // CIJAsmH + 0U, // CIJAsmHE + 0U, // CIJAsmL + 0U, // CIJAsmLE + 0U, // CIJAsmLH + 0U, // CIJAsmNE + 0U, // CIJAsmNH + 0U, // CIJAsmNHE + 0U, // CIJAsmNL + 0U, // CIJAsmNLE + 0U, // CIJAsmNLH + 0U, // CIT + 0U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 0U, // CLCLE + 0U, // CLCLU + 0U, // CLFDBR + 0U, // CLFDTR + 0U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 0U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 0U, // CLFXBR + 0U, // CLFXTR + 0U, // CLG + 0U, // CLGDBR + 0U, // CLGDTR + 0U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 0U, // CLGIBAsm + 0U, // CLGIBAsmE + 0U, // CLGIBAsmH + 0U, // CLGIBAsmHE + 0U, // CLGIBAsmL + 0U, // CLGIBAsmLE + 0U, // CLGIBAsmLH + 0U, // CLGIBAsmNE + 0U, // CLGIBAsmNH + 0U, // CLGIBAsmNHE + 0U, // CLGIBAsmNL + 0U, // CLGIBAsmNLE + 0U, // CLGIBAsmNLH + 0U, // CLGIJ + 0U, // CLGIJAsm + 0U, // CLGIJAsmE + 0U, // CLGIJAsmH + 0U, // CLGIJAsmHE + 0U, // CLGIJAsmL + 0U, // CLGIJAsmLE + 0U, // CLGIJAsmLH + 0U, // CLGIJAsmNE + 0U, // CLGIJAsmNH + 0U, // CLGIJAsmNHE + 0U, // CLGIJAsmNL + 0U, // CLGIJAsmNLE + 0U, // CLGIJAsmNLH + 0U, // CLGIT + 0U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 0U, // CLGRB + 0U, // CLGRBAsm + 0U, // CLGRBAsmE + 0U, // CLGRBAsmH + 0U, // CLGRBAsmHE + 0U, // CLGRBAsmL + 0U, // CLGRBAsmLE + 0U, // CLGRBAsmLH + 0U, // CLGRBAsmNE + 0U, // CLGRBAsmNH + 0U, // CLGRBAsmNHE + 0U, // CLGRBAsmNL + 0U, // CLGRBAsmNLE + 0U, // CLGRBAsmNLH + 0U, // CLGRJ + 0U, // CLGRJAsm + 0U, // CLGRJAsmE + 0U, // CLGRJAsmH + 0U, // CLGRJAsmHE + 0U, // CLGRJAsmL + 0U, // CLGRJAsmLE + 0U, // CLGRJAsmLH + 0U, // CLGRJAsmNE + 0U, // CLGRJAsmNH + 0U, // CLGRJAsmNHE + 0U, // CLGRJAsmNL + 0U, // CLGRJAsmNLE + 0U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 0U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 0U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 0U, // CLGXBR + 0U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 0U, // CLIBAsm + 0U, // CLIBAsmE + 0U, // CLIBAsmH + 0U, // CLIBAsmHE + 0U, // CLIBAsmL + 0U, // CLIBAsmLE + 0U, // CLIBAsmLH + 0U, // CLIBAsmNE + 0U, // CLIBAsmNH + 0U, // CLIBAsmNHE + 0U, // CLIBAsmNL + 0U, // CLIBAsmNLE + 0U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 0U, // CLIJAsm + 0U, // CLIJAsmE + 0U, // CLIJAsmH + 0U, // CLIJAsmHE + 0U, // CLIJAsmL + 0U, // CLIJAsmLE + 0U, // CLIJAsmLH + 0U, // CLIJAsmNE + 0U, // CLIJAsmNH + 0U, // CLIJAsmNHE + 0U, // CLIJAsmNL + 0U, // CLIJAsmNLE + 0U, // CLIJAsmNLH + 0U, // CLIY + 0U, // CLM + 0U, // CLMH + 0U, // CLMY + 0U, // CLR + 0U, // CLRB + 0U, // CLRBAsm + 0U, // CLRBAsmE + 0U, // CLRBAsmH + 0U, // CLRBAsmHE + 0U, // CLRBAsmL + 0U, // CLRBAsmLE + 0U, // CLRBAsmLH + 0U, // CLRBAsmNE + 0U, // CLRBAsmNH + 0U, // CLRBAsmNHE + 0U, // CLRBAsmNL + 0U, // CLRBAsmNLE + 0U, // CLRBAsmNLH + 0U, // CLRJ + 0U, // CLRJAsm + 0U, // CLRJAsmE + 0U, // CLRJAsmH + 0U, // CLRJAsmHE + 0U, // CLRJAsmL + 0U, // CLRJAsmLE + 0U, // CLRJAsmLH + 0U, // CLRJAsmNE + 0U, // CLRJAsmNH + 0U, // CLRJAsmNHE + 0U, // CLRJAsmNL + 0U, // CLRJAsmNLE + 0U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 0U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 0U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 0U, // CPSDRdd + 0U, // CPSDRds + 0U, // CPSDRsd + 0U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 0U, // CRB + 0U, // CRBAsm + 0U, // CRBAsmE + 0U, // CRBAsmH + 0U, // CRBAsmHE + 0U, // CRBAsmL + 0U, // CRBAsmLE + 0U, // CRBAsmLH + 0U, // CRBAsmNE + 0U, // CRBAsmNH + 0U, // CRBAsmNHE + 0U, // CRBAsmNL + 0U, // CRBAsmNLE + 0U, // CRBAsmNLH + 0U, // CRDTE + 0U, // CRDTEOpt + 0U, // CRJ + 0U, // CRJAsm + 0U, // CRJAsmE + 0U, // CRJAsmH + 0U, // CRJAsmHE + 0U, // CRJAsmL + 0U, // CRJAsmLE + 0U, // CRJAsmLH + 0U, // CRJAsmNE + 0U, // CRJAsmNH + 0U, // CRJAsmNHE + 0U, // CRJAsmNL + 0U, // CRJAsmNLE + 0U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 0U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 0U, // CS + 0U, // CSCH + 0U, // CSDTR + 0U, // CSG + 0U, // CSP + 0U, // CSPG + 0U, // CSST + 0U, // CSXTR + 0U, // CSY + 0U, // CU12 + 0U, // CU12Opt + 0U, // CU14 + 0U, // CU14Opt + 0U, // CU21 + 0U, // CU21Opt + 0U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 0U, // CUTFU + 0U, // CUTFUOpt + 0U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 0U, // CXFBRA + 0U, // CXFR + 0U, // CXFTR + 0U, // CXGBR + 0U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 0U, // CXGTRA + 0U, // CXLFBR + 0U, // CXLFTR + 0U, // CXLGBR + 0U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 0U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 0U, // DIAG + 0U, // DIDBR + 0U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 0U, // DXTRA + 0U, // EAR + 0U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 0U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 0U, // FIDBR + 0U, // FIDBRA + 0U, // FIDR + 0U, // FIDTR + 0U, // FIEBR + 0U, // FIEBRA + 0U, // FIER + 0U, // FIXBR + 0U, // FIXBRA + 0U, // FIXR + 0U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 0U, // IDTE + 0U, // IDTEOpt + 0U, // IEDTR + 0U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 0U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 0U, // InsnRI + 0U, // InsnRIE + 0U, // InsnRIL + 0U, // InsnRILU + 0U, // InsnRIS + 0U, // InsnRR + 0U, // InsnRRE + 0U, // InsnRRF + 0U, // InsnRRS + 0U, // InsnRS + 0U, // InsnRSE + 0U, // InsnRSI + 0U, // InsnRSY + 0U, // InsnRX + 0U, // InsnRXE + 0U, // InsnRXF + 0U, // InsnRXY + 0U, // InsnS + 0U, // InsnSI + 0U, // InsnSIL + 0U, // InsnSIY + 0U, // InsnSS + 0U, // InsnSSE + 0U, // InsnSSF + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 0U, // KMA + 0U, // KMAC + 0U, // KMC + 0U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 0U, // LAA + 0U, // LAAG + 0U, // LAAL + 0U, // LAALG + 0U, // LAE + 0U, // LAEY + 0U, // LAM + 0U, // LAMY + 0U, // LAN + 0U, // LANG + 0U, // LAO + 0U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 0U, // LAX + 0U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBH + 0U, // LBR + 0U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 0U, // LCTL + 0U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 0U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 0U, // LDXBRA + 0U, // LDXR + 0U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 0U, // LEDBRA + 0U, // LEDR + 0U, // LEDTR + 0U, // LER + 0U, // LEXBR + 0U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 0U, // LM + 0U, // LMD + 0U, // LMG + 0U, // LMH + 0U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 0U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 0U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 0U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 0U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 0U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 0U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 0U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 0U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 0U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 0U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 0U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 0U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 0U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 0U, // MAD + 0U, // MADB + 0U, // MADBR + 0U, // MADR + 0U, // MAE + 0U, // MAEB + 0U, // MAEBR + 0U, // MAER + 0U, // MAY + 0U, // MAYH + 0U, // MAYHR + 0U, // MAYL + 0U, // MAYLR + 0U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 0U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 0U, // MSD + 0U, // MSDB + 0U, // MSDBR + 0U, // MSDR + 0U, // MSE + 0U, // MSEB + 0U, // MSEBR + 0U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 0U, // MVCLE + 0U, // MVCLU + 0U, // MVCOS + 0U, // MVCP + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 0U, // MXTRA + 0U, // MY + 0U, // MYH + 0U, // MYHR + 0U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 0U, // PLO + 0U, // POPCNT + 0U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 0U, // QADTR + 0U, // QAXTR + 0U, // QCTRI + 0U, // QSI + 0U, // RCHP + 2U, // RISBG + 2U, // RISBG32 + 2U, // RISBGN + 2U, // RISBHG + 2U, // RISBLG + 0U, // RLL + 0U, // RLLG + 2U, // RNSBG + 2U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 0U, // RRDTR + 0U, // RRXTR + 0U, // RSCH + 2U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 0U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 0U, // SIGP + 0U, // SL + 0U, // SLA + 0U, // SLAG + 0U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 0U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 0U, // SLLG + 0U, // SLLK + 0U, // SLR + 0U, // SLRK + 0U, // SLXT + 0U, // SLY + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 0U, // SRAG + 0U, // SRAK + 0U, // SRDA + 0U, // SRDL + 0U, // SRDT + 0U, // SRK + 0U, // SRL + 0U, // SRLG + 0U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 0U, // SRP + 0U, // SRST + 0U, // SRSTU + 0U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 0U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 0U, // STAM + 0U, // STAMY + 0U, // STAP + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 0U, // STCM + 0U, // STCMH + 0U, // STCMY + 0U, // STCPS + 0U, // STCRW + 0U, // STCTG + 0U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 0U, // STM + 0U, // STMG + 0U, // STMH + 0U, // STMY + 0U, // STNSM + 0U, // STOC + 0U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 0U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 0U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 0U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 0U, // TBDR + 0U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 0U, // TRACE + 0U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 0U, // TROO + 0U, // TROOOpt + 0U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 0U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 0U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 0U, // VA + 0U, // VAB + 6U, // VAC + 0U, // VACC + 0U, // VACCB + 6U, // VACCC + 0U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 0U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 7U, // VAP + 0U, // VAQ + 0U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 0U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 6U, // VCDG + 0U, // VCDGB + 6U, // VCDLG + 0U, // VCDLGB + 6U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 6U, // VCGD + 0U, // VCGDB + 6U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 6U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 6U, // VCLGD + 0U, // VCLGDB + 0U, // VCLZ + 0U, // VCLZB + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 0U, // VCP + 0U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 0U, // VCVB + 0U, // VCVBG + 1U, // VCVD + 1U, // VCVDG + 7U, // VDP + 0U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 0U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 10U, // VERIM + 0U, // VERIMB + 0U, // VERIMF + 0U, // VERIMG + 0U, // VERIMH + 0U, // VERLL + 0U, // VERLLB + 0U, // VERLLF + 0U, // VERLLG + 0U, // VERLLH + 0U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 0U, // VESL + 0U, // VESLB + 0U, // VESLF + 0U, // VESLG + 0U, // VESLH + 0U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 0U, // VESRA + 0U, // VESRAB + 0U, // VESRAF + 0U, // VESRAG + 0U, // VESRAH + 0U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 0U, // VESRL + 0U, // VESRLB + 0U, // VESRLF + 0U, // VESRLG + 0U, // VESRLH + 0U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 6U, // VFA + 0U, // VFADB + 6U, // VFAE + 0U, // VFAEB + 0U, // VFAEBS + 0U, // VFAEF + 0U, // VFAEFS + 0U, // VFAEH + 0U, // VFAEHS + 0U, // VFAEZB + 0U, // VFAEZBS + 0U, // VFAEZF + 0U, // VFAEZFS + 0U, // VFAEZH + 0U, // VFAEZHS + 0U, // VFASB + 22U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 22U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 22U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 6U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 6U, // VFEE + 0U, // VFEEB + 0U, // VFEEBS + 0U, // VFEEF + 0U, // VFEEFS + 0U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 6U, // VFENE + 0U, // VFENEB + 0U, // VFENEBS + 0U, // VFENEF + 0U, // VFENEFS + 0U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 6U, // VFI + 0U, // VFIDB + 0U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 0U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 6U, // VFLR + 0U, // VFLRD + 6U, // VFM + 22U, // VFMA + 0U, // VFMADB + 0U, // VFMASB + 22U, // VFMAX + 0U, // VFMAXDB + 0U, // VFMAXSB + 0U, // VFMDB + 22U, // VFMIN + 0U, // VFMINDB + 0U, // VFMINSB + 22U, // VFMS + 0U, // VFMSB + 0U, // VFMSDB + 0U, // VFMSSB + 22U, // VFNMA + 0U, // VFNMADB + 0U, // VFNMASB + 22U, // VFNMS + 0U, // VFNMSDB + 0U, // VFNMSSB + 6U, // VFPSO + 0U, // VFPSODB + 0U, // VFPSOSB + 6U, // VFS + 0U, // VFSDB + 0U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 6U, // VFTCI + 0U, // VFTCIDB + 0U, // VFTCISB + 0U, // VGBM + 0U, // VGEF + 0U, // VGEG + 0U, // VGFM + 6U, // VGFMA + 0U, // VGFMAB + 0U, // VGFMAF + 0U, // VGFMAG + 0U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 0U, // VGM + 0U, // VGMB + 0U, // VGMF + 0U, // VGMG + 0U, // VGMH + 0U, // VISTR + 0U, // VISTRB + 0U, // VISTRBS + 0U, // VISTRF + 0U, // VISTRFS + 0U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 0U, // VLBB + 0U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 0U, // VLDE + 0U, // VLDEB + 0U, // VLEB + 6U, // VLED + 0U, // VLEDB + 0U, // VLEF + 0U, // VLEG + 0U, // VLEH + 0U, // VLEIB + 0U, // VLEIF + 0U, // VLEIG + 0U, // VLEIH + 0U, // VLGV + 0U, // VLGVB + 0U, // VLGVF + 0U, // VLGVG + 0U, // VLGVH + 0U, // VLIP + 0U, // VLL + 0U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 0U, // VLM + 0U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 0U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 0U, // VLRL + 0U, // VLRLR + 1U, // VLVG + 0U, // VLVGB + 0U, // VLVGF + 0U, // VLVGG + 0U, // VLVGH + 0U, // VLVGP + 6U, // VMAE + 0U, // VMAEB + 0U, // VMAEF + 0U, // VMAEH + 6U, // VMAH + 0U, // VMAHB + 0U, // VMAHF + 0U, // VMAHH + 6U, // VMAL + 0U, // VMALB + 6U, // VMALE + 0U, // VMALEB + 0U, // VMALEF + 0U, // VMALEH + 0U, // VMALF + 6U, // VMALH + 0U, // VMALHB + 0U, // VMALHF + 0U, // VMALHH + 0U, // VMALHW + 6U, // VMALO + 0U, // VMALOB + 0U, // VMALOF + 0U, // VMALOH + 6U, // VMAO + 0U, // VMAOB + 0U, // VMAOF + 0U, // VMAOH + 0U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 0U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 0U, // VML + 0U, // VMLB + 0U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 0U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 0U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 0U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 0U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 0U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 7U, // VMP + 0U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 0U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 22U, // VMSL + 6U, // VMSLG + 7U, // VMSP + 0U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 0U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 0U, // VPDI + 0U, // VPERM + 0U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 6U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 6U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 0U, // VPKZ + 0U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 0U, // VPSOP + 0U, // VREP + 0U, // VREPB + 0U, // VREPF + 0U, // VREPG + 0U, // VREPH + 0U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 7U, // VRP + 0U, // VS + 0U, // VSB + 6U, // VSBCBI + 0U, // VSBCBIQ + 6U, // VSBI + 0U, // VSBIQ + 0U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 0U, // VSCEF + 0U, // VSCEG + 7U, // VSDP + 0U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 0U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 1U, // VSLDB + 7U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 0U, // VSRL + 0U, // VSRLB + 0U, // VSRP + 0U, // VST + 0U, // VSTEB + 0U, // VSTEF + 0U, // VSTEG + 0U, // VSTEH + 0U, // VSTL + 0U, // VSTM + 22U, // VSTRC + 6U, // VSTRCB + 6U, // VSTRCBS + 6U, // VSTRCF + 6U, // VSTRCFS + 6U, // VSTRCH + 6U, // VSTRCHS + 6U, // VSTRCZB + 6U, // VSTRCZBS + 6U, // VSTRCZF + 6U, // VSTRCZFS + 6U, // VSTRCZH + 6U, // VSTRCZHS + 0U, // VSTRL + 0U, // VSTRLR + 0U, // VSUM + 0U, // VSUMB + 0U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 0U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 0U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 0U, // VUPKZ + 0U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 0U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 0U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 0U, // WCDGB + 0U, // WCDLGB + 0U, // WCGDB + 0U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 0U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 0U, // WFIDB + 0U, // WFISB + 0U, // WFIXB + 0U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 0U, // WFLRD + 0U, // WFLRX + 0U, // WFMADB + 0U, // WFMASB + 0U, // WFMAXB + 0U, // WFMAXDB + 0U, // WFMAXSB + 0U, // WFMAXXB + 0U, // WFMDB + 0U, // WFMINDB + 0U, // WFMINSB + 0U, // WFMINXB + 0U, // WFMSB + 0U, // WFMSDB + 0U, // WFMSSB + 0U, // WFMSXB + 0U, // WFMXB + 0U, // WFNMADB + 0U, // WFNMASB + 0U, // WFNMAXB + 0U, // WFNMSDB + 0U, // WFNMSSB + 0U, // WFNMSXB + 0U, // WFPSODB + 0U, // WFPSOSB + 0U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 0U, // WFTCIDB + 0U, // WFTCISB + 0U, // WFTCIXB + 0U, // WLDEB + 0U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 16383)-1); +#endif + + + // Fragment 0 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 14) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... + printOperand(MI, 0, O); + break; + case 2: + // AGSI, ALGSI, ALSI, ASI, CFC, CGHSI, CHHSI, CHSI, CLFHSI, CLGHSI, CLHHS... + printBDAddrOperand(MI, 0, O); + break; + case 3: + // AP, CLC, CP, DP, ED, EDMK, MP, MVC, MVCIN, MVN, MVO, MVZ, NC, OC, PACK... + printBDLAddrOperand(MI, 0, O); + break; + case 4: + // B, BAsmE, BAsmH, BAsmHE, BAsmL, BAsmLE, BAsmLH, BAsmM, BAsmNE, BAsmNH,... + printBDXAddrOperand(MI, 0, O); + return; + break; + case 5: + // BC, BCR, BIC, BRC, BRCL + printCond4Operand(MI, 1, O); + break; + case 6: + // BCAsm, BCRAsm, BICAsm, BPP, BPRP, BRCAsm, BRCLAsm, NIAI, PFD, PFDRL + printU4ImmOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 7: + // CGIB, CGIJ, CGIT, CGRB, CGRJ, CGRT, CIB, CIJ, CIT, CLFIT, CLGIB, CLGIJ... + printCond4Operand(MI, 2, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 8: + // CLGT, CLT + printCond4Operand(MI, 3, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand(MI, 1, O); + return; + break; + case 9: + // InsnE, InsnRR + printU16ImmOperand(MI, 0, O); + break; + case 10: + // InsnRI, InsnRRE, InsnRRF, InsnRS, InsnRX, InsnS, InsnSI + printU32ImmOperand(MI, 0, O); + SStream_concat0(O, ","); + break; + case 11: + // InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRS, InsnRSE, InsnRSI, InsnRS... + printU48ImmOperand(MI, 0, O); + SStream_concat0(O, ","); + break; + case 12: + // J, JAsmE, JAsmH, JAsmHE, JAsmL, JAsmLE, JAsmLH, JAsmM, JAsmNE, JAsmNH,... + printPCRelOperand(MI, 0, O); + return; + break; + case 13: + // KIMD, KLMD, KMAC, PFMF, TRTE, TRTEOpt, TRTRE, TRTREOpt + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + break; + case 14: + // LOC, LOCFH, LOCG + printCond4Operand(MI, 5, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand(MI, 2, O); + return; + break; + case 15: + // LOCFHR, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, STOC, STOCFH, STOCG + printCond4Operand(MI, 4, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 16: + // MVCK, MVCP, MVCS + printBDRAddrOperand(MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 17: + // SVC + printU8ImmOperand(MI, 0, O); + return; + break; + } + + + // Fragment 1 encoded into 5 bits for 17 unique commands. + switch ((Bits >> 19) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... + SStream_concat0(O, ", "); + break; + case 1: + // BC, BIC, BRC, BRCL + SStream_concat0(O, "\t"); + break; + case 2: + // BCAsm, BICAsm, PFD + printBDXAddrOperand(MI, 1, O); + return; + break; + case 3: + // BCR + SStream_concat0(O, "r\t"); + printOperand(MI, 2, O); + return; + break; + case 4: + // BCRAsm, CGRB, CGRJ, CGRT, CLGRB, CLGRJ, CLGRT, CLRB, CLRJ, CLRT, CRB, ... + printOperand(MI, 1, O); + break; + case 5: + // BPP, BPRP, BRCAsm, BRCLAsm, PFDRL + printPCRelOperand(MI, 1, O); + break; + case 6: + // BR, BRAsmE, BRAsmH, BRAsmHE, BRAsmL, BRAsmLE, BRAsmLH, BRAsmM, BRAsmNE... + return; + break; + case 7: + // CGIB, CGIJ, CIB, CIJ + printS8ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 8: + // CGIT, CIT + printS16ImmOperand(MI, 1, O); + return; + break; + case 9: + // CLFIT, CLGIT + printU16ImmOperand(MI, 1, O); + return; + break; + case 10: + // CLGIB, CLGIJ, CLIB, CLIJ + printU8ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 11: + // InsnRR + SStream_concat0(O, ","); + printOperand(MI, 1, O); + SStream_concat0(O, ","); + printOperand(MI, 2, O); + return; + break; + case 12: + // InsnS, InsnSI, InsnSIL, InsnSIY, InsnSSE, InsnSSF, STOC, STOCFH, STOCG + printBDAddrOperand(MI, 1, O); + break; + case 13: + // InsnSS + printBDRAddrOperand(MI, 1, O); + SStream_concat0(O, ","); + printBDAddrOperand(MI, 4, O); + SStream_concat0(O, ","); + printOperand(MI, 6, O); + return; + break; + case 14: + // LOCFHR, LOCGR, LOCR + printOperand(MI, 2, O); + return; + break; + case 15: + // LOCGHI, LOCHHI, LOCHI + printS16ImmOperand(MI, 2, O); + return; + break; + case 16: + // NIAI + printU4ImmOperand(MI, 1, O); + return; + break; + } + + + // Fragment 2 encoded into 6 bits for 34 unique commands. + switch ((Bits >> 24) & 63) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, AE, AEB, AG, AGF, AGH, AH, AHY, AL, ALC, ALCG, ALG, ALGF, ... + printBDXAddrOperand(MI, 2, O); + break; + case 1: + // ADBR, ADR, AEBR, AER, AGFR, AGR, ALCGR, ALCR, ALGFR, ALGR, ALR, AR, AU... + printOperand(MI, 2, O); + break; + case 2: + // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... + printOperand(MI, 1, O); + break; + case 3: + // AFI, AGFI, AIH, ALSIH, ALSIHN, MSFI, MSGFI + printS32ImmOperand(MI, 2, O); + return; + break; + case 4: + // AGHI, AHI, CGHSI, CHHSI, CHSI, LOCGHIAsm, LOCGHIAsmE, LOCGHIAsmH, LOCG... + printS16ImmOperand(MI, 2, O); + break; + case 5: + // AGSI, ALGSI, ALSI, ASI + printS8ImmOperand(MI, 2, O); + return; + break; + case 6: + // ALFI, ALGFI, NIHF, NILF, OIHF, OILF, SLFI, SLGFI, XIHF, XILF + printU32ImmOperand(MI, 2, O); + return; + break; + case 7: + // AP, CP, DP, MP, MVO, PACK, SP, UNPK, ZAP + printBDLAddrOperand(MI, 3, O); + return; + break; + case 8: + // BAL, BAS, C, CD, CDB, CE, CEB, CG, CGF, CGH, CH, CHF, CHY, CL, CLG, CL... + printBDXAddrOperand(MI, 1, O); + break; + case 9: + // BCRAsm, BRCAsm, BRCLAsm, CGRT, CLGRT, CLRT, CRT, InsnS, PFDRL, STOC, S... + return; + break; + case 10: + // BPP, BPRP, CGRB, CGRJ, CLGRB, CLGRJ, CLRB, CLRJ, CRB, CRJ + SStream_concat0(O, ", "); + break; + case 11: + // BRAS, BRASL + printPCRelTLSOperand(MI, 1, O); + return; + break; + case 12: + // BRC, BRCL, BRCT, BRCTG, BRCTH + printPCRelOperand(MI, 2, O); + return; + break; + case 13: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + printU4ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 14: + // CDPT, CDZT, CPDT, CPXT, CXPT, CXZT, CZDT, CZXT + printBDLAddrOperand(MI, 1, O); + SStream_concat0(O, ", "); + printU4ImmOperand(MI, 4, O); + return; + break; + case 15: + // CFI, CGFI, CIH, LGFI + printS32ImmOperand(MI, 1, O); + return; + break; + case 16: + // CGFRL, CGHRL, CGRL, CHRL, CLGFRL, CLGHRL, CLGRL, CLHRL, CLRL, CRL, EXR... + printPCRelOperand(MI, 1, O); + return; + break; + case 17: + // CGHI, CGITAsm, CGITAsmE, CGITAsmH, CGITAsmHE, CGITAsmL, CGITAsmLE, CGI... + printS16ImmOperand(MI, 1, O); + break; + case 18: + // CGIB, CIB, CLC, CLGIB, CLIB, ED, EDMK, MVC, MVCIN, MVN, MVZ, NC, OC, S... + printBDAddrOperand(MI, 3, O); + break; + case 19: + // CGIBAsm, CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH... + printS8ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 20: + // CGIJ, CIJ, CLGIJ, CLIJ + printPCRelOperand(MI, 3, O); + return; + break; + case 21: + // CLFHSI, CLGHSI, CLHHSI, IIHH, IIHL, IILH, IILL, NIHH, NIHL, NILH, NILL... + printU16ImmOperand(MI, 2, O); + return; + break; + case 22: + // CLFI, CLGFI, CLIH, IIHF, IILF, LLIHF, LLILF + printU32ImmOperand(MI, 1, O); + return; + break; + case 23: + // CLFITAsm, CLFITAsmE, CLFITAsmH, CLFITAsmHE, CLFITAsmL, CLFITAsmLE, CLF... + printU16ImmOperand(MI, 1, O); + break; + case 24: + // CLGIBAsm, CLGIBAsmE, CLGIBAsmH, CLGIBAsmHE, CLGIBAsmL, CLGIBAsmLE, CLG... + printU8ImmOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 25: + // CLGTAsm, CLTAsm, TRTE, TRTRE + printU4ImmOperand(MI, 3, O); + break; + case 26: + // CLGTAsmE, CLGTAsmH, CLGTAsmHE, CLGTAsmL, CLGTAsmLE, CLGTAsmLH, CLGTAsm... + printBDAddrOperand(MI, 1, O); + break; + case 27: + // CLI, CLIY, MC, MVI, MVIY, NI, NIY, OI, OIY, STNSM, STOSM, TM, TMY, XI,... + printU8ImmOperand(MI, 2, O); + return; + break; + case 28: + // CSST, ECTG, LASP, LOCAsm, LOCAsmE, LOCAsmH, LOCAsmHE, LOCAsmL, LOCAsmL... + printBDAddrOperand(MI, 2, O); + break; + case 29: + // ICM, ICMH, ICMY + printU4ImmOperand(MI, 2, O); + SStream_concat0(O, ", "); + printBDAddrOperand(MI, 3, O); + return; + break; + case 30: + // InsnRI, InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRE, InsnRRF, InsnRRS... + SStream_concat0(O, ","); + break; + case 31: + // PKA, PKU + printBDLAddrOperand(MI, 2, O); + return; + break; + case 32: + // VGEF, VGEG + printBDVAddrOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 33: + // VSCEF, VSCEG + printBDVAddrOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + } + + + // Fragment 3 encoded into 5 bits for 20 unique commands. + switch ((Bits >> 30) & 31) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, ADBR, ADR, AE, AEB, AEBR, AER, AG, AGF, AGFR, AGH, AGHI, A... + return; + break; + case 1: + // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... + SStream_concat0(O, ", "); + break; + case 2: + // BPP, InsnRX, InsnRXE, InsnRXY + printBDXAddrOperand(MI, 2, O); + return; + break; + case 3: + // BPRP, CGIJAsmE, CGIJAsmH, CGIJAsmHE, CGIJAsmL, CGIJAsmLE, CGIJAsmLH, C... + printPCRelOperand(MI, 2, O); + return; + break; + case 4: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + printOperand(MI, 2, O); + break; + case 5: + // CGIBAsm, CGIJAsm, CIBAsm, CIJAsm, CLGIBAsm, CLGIJAsm, CLIBAsm, CLIJAsm + printU4ImmOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH, CGIBAsm... + printBDAddrOperand(MI, 2, O); + return; + break; + case 7: + // CGRB, CLGRB, CLRB, CRB, InsnSSE, InsnSSF + printBDAddrOperand(MI, 3, O); + break; + case 8: + // CGRJ, CLGRJ, CLRJ, CRJ + printPCRelOperand(MI, 3, O); + return; + break; + case 9: + // InsnRI + printS16ImmOperand(MI, 2, O); + return; + break; + case 10: + // InsnRILU + printU32ImmOperand(MI, 2, O); + return; + break; + case 11: + // InsnRIS + printS8ImmOperand(MI, 2, O); + SStream_concat0(O, ","); + printU4ImmOperand(MI, 3, O); + SStream_concat0(O, ","); + printBDAddrOperand(MI, 4, O); + return; + break; + case 12: + // InsnSI + printS8ImmOperand(MI, 3, O); + return; + break; + case 13: + // InsnSIL + printU16ImmOperand(MI, 3, O); + return; + break; + case 14: + // InsnSIY + printU8ImmOperand(MI, 3, O); + return; + break; + case 15: + // VGEF + printU2ImmOperand(MI, 5, O); + return; + break; + case 16: + // VGEG + printU1ImmOperand(MI, 5, O); + return; + break; + case 17: + // VGM, VGMB, VGMF, VGMG, VGMH + printU8ImmOperand(MI, 2, O); + break; + case 18: + // VSCEF + printU2ImmOperand(MI, 4, O); + return; + break; + case 19: + // VSCEG + printU1ImmOperand(MI, 4, O); + return; + break; + } + + + // Fragment 4 encoded into 6 bits for 33 unique commands. + switch ((Bits >> 35) & 63) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADTR, ADTRA, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXT... + printOperand(MI, 2, O); + break; + case 1: + // AGHIK, AHIK, ALGHSIK, ALHSIK + printS16ImmOperand(MI, 2, O); + return; + break; + case 2: + // BRXH, BRXHG, BRXLE, BRXLG, CGIJAsm, CIJAsm, CLGIJAsm, CLIJAsm + printPCRelOperand(MI, 3, O); + return; + break; + case 3: + // BXH, BXHG, BXLE, BXLEG, CDS, CDSG, CDSY, CGIBAsm, CIBAsm, CLGIBAsm, CL... + printBDAddrOperand(MI, 3, O); + break; + case 4: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + SStream_concat0(O, ", "); + printU4ImmOperand(MI, 3, O); + return; + break; + case 5: + // CFDBR, CFDR, CFEBR, CFER, CFXBR, CFXR, CGDBR, CGDR, CGDTR, CGEBR, CGER... + return; + break; + case 6: + // CGITAsm, CGRBAsm, CGRJAsm, CGRTAsm, CITAsm, CLFITAsm, CLGITAsm, CLGRBA... + printU4ImmOperand(MI, 2, O); + break; + case 7: + // CGRBAsmE, CGRBAsmH, CGRBAsmHE, CGRBAsmL, CGRBAsmLE, CGRBAsmLH, CGRBAsm... + printBDAddrOperand(MI, 2, O); + break; + case 8: + // CGRJAsmE, CGRJAsmH, CGRJAsmHE, CGRJAsmL, CGRJAsmLE, CGRJAsmLH, CGRJAsm... + printPCRelOperand(MI, 2, O); + return; + break; + case 9: + // CLCLE, CLCLU, MVCLE, MVCLU + printBDAddrOperand(MI, 4, O); + return; + break; + case 10: + // CLGTAsm, CLTAsm + printBDAddrOperand(MI, 1, O); + return; + break; + case 11: + // CPSDRdd, CPSDRds, CPSDRsd, CPSDRss, CRDTE, CRDTEOpt, IDTE, IDTEOpt, IE... + printOperand(MI, 1, O); + break; + case 12: + // CSST, ECTG, MVCOS + printOperand(MI, 4, O); + return; + break; + case 13: + // CU12, CU14, CU21, CU24, CUTFU, CUUTF, LCBB, LOCAsm, LOCFHAsm, LOCGAsm,... + printU4ImmOperand(MI, 4, O); + return; + break; + case 14: + // DIDBR, DIEBR, LPTEA, MADBR, MADR, MAEBR, MAER, MAYHR, MAYLR, MAYR, MSD... + printOperand(MI, 3, O); + break; + case 15: + // InsnRIE, InsnRRF, InsnRRS, InsnRS, InsnRSE, InsnRSI, InsnRSY, InsnRXF,... + SStream_concat0(O, ","); + break; + case 16: + // LOCFHRAsm, LOCGHIAsm, LOCGRAsm, LOCHHIAsm, LOCHIAsm, LOCRAsm, STOCAsm,... + printU4ImmOperand(MI, 3, O); + return; + break; + case 17: + // MAD, MADB, MAE, MAEB, MAY, MAYH, MAYL, MSD, MSDB, MSE, MSEB + printBDXAddrOperand(MI, 3, O); + return; + break; + case 18: + // MY, MYH, MYL, SLDT, SLXT, SRDT, SRXT + printBDXAddrOperand(MI, 2, O); + return; + break; + case 19: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VLRL, VPK... + printU8ImmOperand(MI, 3, O); + break; + case 20: + // SRP, VLEB + printU4ImmOperand(MI, 5, O); + return; + break; + case 21: + // VCVD, VCVDG, VPSOP, VSRP + printU8ImmOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 22: + // VFTCI, VFTCIDB, VFTCISB, WFTCIDB, WFTCISB, WFTCIXB + printU12ImmOperand(MI, 2, O); + break; + case 23: + // VLEF + printU2ImmOperand(MI, 5, O); + return; + break; + case 24: + // VLEG + printU1ImmOperand(MI, 5, O); + return; + break; + case 25: + // VLEH + printU3ImmOperand(MI, 5, O); + return; + break; + case 26: + // VLEIF + printU2ImmOperand(MI, 3, O); + return; + break; + case 27: + // VLEIG + printU1ImmOperand(MI, 3, O); + return; + break; + case 28: + // VLEIH + printU3ImmOperand(MI, 3, O); + return; + break; + case 29: + // VREP, VREPB, VREPF, VREPG, VREPH + printU16ImmOperand(MI, 2, O); + break; + case 30: + // VSTEF + printU2ImmOperand(MI, 4, O); + return; + break; + case 31: + // VSTEG + printU1ImmOperand(MI, 4, O); + return; + break; + case 32: + // VSTEH + printU3ImmOperand(MI, 4, O); + return; + break; + } + + + // Fragment 5 encoded into 4 bits for 9 unique commands. + switch ((Bits >> 41) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADTR, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXTR, BXH,... + return; + break; + case 1: + // ADTRA, AXTRA, CGRBAsm, CGRJAsm, CLGRBAsm, CLGRJAsm, CLRBAsm, CLRJAsm, ... + SStream_concat0(O, ", "); + break; + case 2: + // InsnRIE, InsnRSI + printPCRelOperand(MI, 3, O); + return; + break; + case 3: + // InsnRRF + printOperand(MI, 3, O); + SStream_concat0(O, ","); + printU4ImmOperand(MI, 4, O); + return; + break; + case 4: + // InsnRRS, VCVD, VCVDG + printU4ImmOperand(MI, 3, O); + break; + case 5: + // InsnRS, InsnRSE, InsnRSY + printBDAddrOperand(MI, 3, O); + return; + break; + case 6: + // InsnRXF + printBDXAddrOperand(MI, 3, O); + return; + break; + case 7: + // InsnSSF + printOperand(MI, 5, O); + return; + break; + case 8: + // VPSOP, VSRP + printU8ImmOperand(MI, 3, O); + SStream_concat0(O, ", "); + printU4ImmOperand(MI, 4, O); + return; + break; + } + + + // Fragment 6 encoded into 4 bits for 11 unique commands. + switch ((Bits >> 45) & 15) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... + printU4ImmOperand(MI, 3, O); + break; + case 1: + // CGRBAsm, CLGRBAsm, CLRBAsm, CRBAsm + printBDAddrOperand(MI, 3, O); + return; + break; + case 2: + // CGRJAsm, CLGRJAsm, CLRJAsm, CRJAsm + printPCRelOperand(MI, 3, O); + return; + break; + case 3: + // DIDBR, DIEBR, LPTEA, QADTR, QAXTR, RRDTR, RRXTR, VERLL, VESL, VESRA, V... + printU4ImmOperand(MI, 4, O); + return; + break; + case 4: + // InsnRRS + SStream_concat0(O, ","); + printBDAddrOperand(MI, 4, O); + return; + break; + case 5: + // LMD, PLO + printBDAddrOperand(MI, 4, O); + return; + break; + case 6: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VERIM, VE... + printU8ImmOperand(MI, 4, O); + break; + case 7: + // VAC, VACCC, VACCCQ, VACQ, VFMA, VFMADB, VFMASB, VFMS, VFMSDB, VFMSSB, ... + printOperand(MI, 3, O); + break; + case 8: + // VAP, VDP, VMP, VMSP, VRP, VSDP, VSLDB, VSP + printU8ImmOperand(MI, 3, O); + break; + case 9: + // VCVD, VCVDG + return; + break; + case 10: + // VLVG + printU4ImmOperand(MI, 5, O); + return; + break; + } + + + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 49) & 1) { + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VAC, VACC... + SStream_concat0(O, ", "); + } else { + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... + return; + } + + + // Fragment 8 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 50) & 3) { + default: // llvm_unreachable("Invalid command number."); + case 0: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG + printU6ImmOperand(MI, 5, O); + return; + break; + case 1: + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... + printU4ImmOperand(MI, 4, O); + break; + case 2: + // VERIM + printU4ImmOperand(MI, 5, O); + return; + break; + } + + + // Fragment 9 encoded into 1 bits for 2 unique commands. + if ((Bits >> 52) & 1) { + // VFCE, VFCH, VFCHE, VFMA, VFMAX, VFMIN, VFMS, VFNMA, VFNMS, VMSL, VSTRC + SStream_concat0(O, ", "); + printU4ImmOperand(MI, 5, O); + return; + } else { + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... + return; + } + +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 194 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'a', '1', '0', 0, + /* 4 */ 'c', '1', '0', 0, + /* 8 */ 'f', '1', '0', 0, + /* 12 */ 'r', '1', '0', 0, + /* 16 */ 'v', '1', '0', 0, + /* 20 */ 'v', '2', '0', 0, + /* 24 */ 'v', '3', '0', 0, + /* 28 */ 'a', '0', 0, + /* 31 */ 'c', '0', 0, + /* 34 */ 'f', '0', 0, + /* 37 */ 'r', '0', 0, + /* 40 */ 'v', '0', 0, + /* 43 */ 'a', '1', '1', 0, + /* 47 */ 'c', '1', '1', 0, + /* 51 */ 'f', '1', '1', 0, + /* 55 */ 'r', '1', '1', 0, + /* 59 */ 'v', '1', '1', 0, + /* 63 */ 'v', '2', '1', 0, + /* 67 */ 'v', '3', '1', 0, + /* 71 */ 'a', '1', 0, + /* 74 */ 'c', '1', 0, + /* 77 */ 'f', '1', 0, + /* 80 */ 'r', '1', 0, + /* 83 */ 'v', '1', 0, + /* 86 */ 'a', '1', '2', 0, + /* 90 */ 'c', '1', '2', 0, + /* 94 */ 'f', '1', '2', 0, + /* 98 */ 'r', '1', '2', 0, + /* 102 */ 'v', '1', '2', 0, + /* 106 */ 'v', '2', '2', 0, + /* 110 */ 'a', '2', 0, + /* 113 */ 'c', '2', 0, + /* 116 */ 'f', '2', 0, + /* 119 */ 'r', '2', 0, + /* 122 */ 'v', '2', 0, + /* 125 */ 'a', '1', '3', 0, + /* 129 */ 'c', '1', '3', 0, + /* 133 */ 'f', '1', '3', 0, + /* 137 */ 'r', '1', '3', 0, + /* 141 */ 'v', '1', '3', 0, + /* 145 */ 'v', '2', '3', 0, + /* 149 */ 'a', '3', 0, + /* 152 */ 'c', '3', 0, + /* 155 */ 'f', '3', 0, + /* 158 */ 'r', '3', 0, + /* 161 */ 'v', '3', 0, + /* 164 */ 'a', '1', '4', 0, + /* 168 */ 'c', '1', '4', 0, + /* 172 */ 'f', '1', '4', 0, + /* 176 */ 'r', '1', '4', 0, + /* 180 */ 'v', '1', '4', 0, + /* 184 */ 'v', '2', '4', 0, + /* 188 */ 'a', '4', 0, + /* 191 */ 'c', '4', 0, + /* 194 */ 'f', '4', 0, + /* 197 */ 'r', '4', 0, + /* 200 */ 'v', '4', 0, + /* 203 */ 'a', '1', '5', 0, + /* 207 */ 'c', '1', '5', 0, + /* 211 */ 'f', '1', '5', 0, + /* 215 */ 'r', '1', '5', 0, + /* 219 */ 'v', '1', '5', 0, + /* 223 */ 'v', '2', '5', 0, + /* 227 */ 'a', '5', 0, + /* 230 */ 'c', '5', 0, + /* 233 */ 'f', '5', 0, + /* 236 */ 'r', '5', 0, + /* 239 */ 'v', '5', 0, + /* 242 */ 'v', '1', '6', 0, + /* 246 */ 'v', '2', '6', 0, + /* 250 */ 'a', '6', 0, + /* 253 */ 'c', '6', 0, + /* 256 */ 'f', '6', 0, + /* 259 */ 'r', '6', 0, + /* 262 */ 'v', '6', 0, + /* 265 */ 'v', '1', '7', 0, + /* 269 */ 'v', '2', '7', 0, + /* 273 */ 'a', '7', 0, + /* 276 */ 'c', '7', 0, + /* 279 */ 'f', '7', 0, + /* 282 */ 'r', '7', 0, + /* 285 */ 'v', '7', 0, + /* 288 */ 'v', '1', '8', 0, + /* 292 */ 'v', '2', '8', 0, + /* 296 */ 'a', '8', 0, + /* 299 */ 'c', '8', 0, + /* 302 */ 'f', '8', 0, + /* 305 */ 'r', '8', 0, + /* 308 */ 'v', '8', 0, + /* 311 */ 'v', '1', '9', 0, + /* 315 */ 'v', '2', '9', 0, + /* 319 */ 'a', '9', 0, + /* 322 */ 'c', '9', 0, + /* 325 */ 'f', '9', 0, + /* 328 */ 'r', '9', 0, + /* 331 */ 'v', '9', 0, + /* 334 */ 'c', 'c', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 334, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, + 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, + 47, 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, + 331, 16, 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, + 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, + 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, + 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, + 77, 194, 233, 302, 325, 94, 133, 34, 77, 116, 155, 194, 233, 256, + 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, + 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 37, 80, 119, + 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, + 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, + 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, + 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, + }; + + //int i; + //for (i = 0; i < sizeof(RegAsmOffset); i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("*************************\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenDisassemblerTables.inc new file mode 100644 index 0000000..b90664c --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenDisassemblerTables.inc @@ -0,0 +1,10262 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * SystemZ Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTable16[] = { +/* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 3 */ MCD_OPC_FilterValue, 1, 84, 0, // Skip to: 91 +/* 7 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 10 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 18 +/* 14 */ MCD_OPC_Decode, 149, 14, 0, // Opcode: PR +/* 18 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 26 +/* 22 */ MCD_OPC_Decode, 209, 16, 0, // Opcode: UPT +/* 26 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 34 +/* 30 */ MCD_OPC_Decode, 153, 14, 0, // Opcode: PTFF +/* 34 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 42 +/* 38 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: SCKPF +/* 42 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 50 +/* 46 */ MCD_OPC_Decode, 140, 14, 0, // Opcode: PFPO +/* 50 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 58 +/* 54 */ MCD_OPC_Decode, 156, 16, 0, // Opcode: TAM +/* 58 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 66 +/* 62 */ MCD_OPC_Decode, 181, 14, 0, // Opcode: SAM24 +/* 66 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 74 +/* 70 */ MCD_OPC_Decode, 182, 14, 0, // Opcode: SAM31 +/* 74 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 82 +/* 78 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: SAM64 +/* 82 */ MCD_OPC_FilterValue, 255, 1, 85, 2, // Skip to: 684 +/* 87 */ MCD_OPC_Decode, 187, 16, 0, // Opcode: TRAP2 +/* 91 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 105 +/* 95 */ MCD_OPC_CheckField, 0, 4, 0, 71, 2, // Skip to: 684 +/* 101 */ MCD_OPC_Decode, 245, 14, 1, // Opcode: SPM +/* 105 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 113 +/* 109 */ MCD_OPC_Decode, 168, 3, 2, // Opcode: BALR +/* 113 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 121 +/* 117 */ MCD_OPC_Decode, 199, 3, 3, // Opcode: BCTR +/* 121 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 252 +/* 125 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 128 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 136 +/* 132 */ MCD_OPC_Decode, 245, 3, 4, // Opcode: BRAsmO +/* 136 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 144 +/* 140 */ MCD_OPC_Decode, 229, 3, 4, // Opcode: BRAsmH +/* 144 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 152 +/* 148 */ MCD_OPC_Decode, 239, 3, 4, // Opcode: BRAsmNLE +/* 152 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 160 +/* 156 */ MCD_OPC_Decode, 231, 3, 4, // Opcode: BRAsmL +/* 160 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 168 +/* 164 */ MCD_OPC_Decode, 237, 3, 4, // Opcode: BRAsmNHE +/* 168 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 176 +/* 172 */ MCD_OPC_Decode, 233, 3, 4, // Opcode: BRAsmLH +/* 176 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 184 +/* 180 */ MCD_OPC_Decode, 235, 3, 4, // Opcode: BRAsmNE +/* 184 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 192 +/* 188 */ MCD_OPC_Decode, 228, 3, 4, // Opcode: BRAsmE +/* 192 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 200 +/* 196 */ MCD_OPC_Decode, 240, 3, 4, // Opcode: BRAsmNLH +/* 200 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 208 +/* 204 */ MCD_OPC_Decode, 230, 3, 4, // Opcode: BRAsmHE +/* 208 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 216 +/* 212 */ MCD_OPC_Decode, 238, 3, 4, // Opcode: BRAsmNL +/* 216 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 224 +/* 220 */ MCD_OPC_Decode, 232, 3, 4, // Opcode: BRAsmLE +/* 224 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 232 +/* 228 */ MCD_OPC_Decode, 236, 3, 4, // Opcode: BRAsmNH +/* 232 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 240 +/* 236 */ MCD_OPC_Decode, 242, 3, 4, // Opcode: BRAsmNO +/* 240 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 248 +/* 244 */ MCD_OPC_Decode, 225, 3, 4, // Opcode: BR +/* 248 */ MCD_OPC_Decode, 195, 3, 5, // Opcode: BCRAsm +/* 252 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 260 +/* 256 */ MCD_OPC_Decode, 147, 16, 6, // Opcode: SVC +/* 260 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 268 +/* 264 */ MCD_OPC_Decode, 133, 4, 2, // Opcode: BSM +/* 268 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 276 +/* 272 */ MCD_OPC_Decode, 171, 3, 2, // Opcode: BASSM +/* 276 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 284 +/* 280 */ MCD_OPC_Decode, 170, 3, 2, // Opcode: BASR +/* 284 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 292 +/* 288 */ MCD_OPC_Decode, 195, 13, 7, // Opcode: MVCL +/* 292 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 300 +/* 296 */ MCD_OPC_Decode, 226, 5, 7, // Opcode: CLCL +/* 300 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 308 +/* 304 */ MCD_OPC_Decode, 196, 12, 8, // Opcode: LPR +/* 308 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 316 +/* 312 */ MCD_OPC_Decode, 238, 10, 8, // Opcode: LNR +/* 316 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 324 +/* 320 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: LTR +/* 324 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 332 +/* 328 */ MCD_OPC_Decode, 141, 10, 8, // Opcode: LCR +/* 332 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 340 +/* 336 */ MCD_OPC_Decode, 240, 13, 9, // Opcode: NR +/* 340 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 348 +/* 344 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: CLR +/* 348 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 356 +/* 352 */ MCD_OPC_Decode, 129, 14, 9, // Opcode: OR +/* 356 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 364 +/* 360 */ MCD_OPC_Decode, 235, 21, 9, // Opcode: XR +/* 364 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 372 +/* 368 */ MCD_OPC_Decode, 202, 12, 8, // Opcode: LR +/* 372 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 380 +/* 376 */ MCD_OPC_Decode, 214, 7, 8, // Opcode: CR +/* 380 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 388 +/* 384 */ MCD_OPC_Decode, 153, 3, 9, // Opcode: AR +/* 388 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 396 +/* 392 */ MCD_OPC_Decode, 130, 15, 9, // Opcode: SR +/* 396 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 404 +/* 400 */ MCD_OPC_Decode, 167, 13, 10, // Opcode: MR +/* 404 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 412 +/* 408 */ MCD_OPC_Decode, 206, 8, 10, // Opcode: DR +/* 412 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 420 +/* 416 */ MCD_OPC_Decode, 146, 3, 9, // Opcode: ALR +/* 420 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 428 +/* 424 */ MCD_OPC_Decode, 238, 14, 9, // Opcode: SLR +/* 428 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 436 +/* 432 */ MCD_OPC_Decode, 189, 12, 11, // Opcode: LPDR +/* 436 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 444 +/* 440 */ MCD_OPC_Decode, 233, 10, 11, // Opcode: LNDR +/* 444 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 452 +/* 448 */ MCD_OPC_Decode, 218, 12, 11, // Opcode: LTDR +/* 452 */ MCD_OPC_FilterValue, 35, 4, 0, // Skip to: 460 +/* 456 */ MCD_OPC_Decode, 136, 10, 11, // Opcode: LCDR +/* 460 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 468 +/* 464 */ MCD_OPC_Decode, 252, 8, 11, // Opcode: HDR +/* 468 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 476 +/* 472 */ MCD_OPC_Decode, 158, 10, 12, // Opcode: LDXR +/* 476 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 484 +/* 480 */ MCD_OPC_Decode, 217, 13, 13, // Opcode: MXR +/* 484 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 492 +/* 488 */ MCD_OPC_Decode, 216, 13, 14, // Opcode: MXDR +/* 492 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 500 +/* 496 */ MCD_OPC_Decode, 154, 10, 11, // Opcode: LDR +/* 500 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 508 +/* 504 */ MCD_OPC_Decode, 156, 4, 11, // Opcode: CDR +/* 508 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 516 +/* 512 */ MCD_OPC_Decode, 232, 2, 15, // Opcode: ADR +/* 516 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 524 +/* 520 */ MCD_OPC_Decode, 193, 14, 15, // Opcode: SDR +/* 524 */ MCD_OPC_FilterValue, 44, 4, 0, // Skip to: 532 +/* 528 */ MCD_OPC_Decode, 145, 13, 15, // Opcode: MDR +/* 532 */ MCD_OPC_FilterValue, 45, 4, 0, // Skip to: 540 +/* 536 */ MCD_OPC_Decode, 191, 8, 15, // Opcode: DDR +/* 540 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 548 +/* 544 */ MCD_OPC_Decode, 159, 3, 15, // Opcode: AWR +/* 548 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 556 +/* 552 */ MCD_OPC_Decode, 149, 16, 15, // Opcode: SWR +/* 556 */ MCD_OPC_FilterValue, 48, 4, 0, // Skip to: 564 +/* 560 */ MCD_OPC_Decode, 191, 12, 16, // Opcode: LPER +/* 564 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 572 +/* 568 */ MCD_OPC_Decode, 235, 10, 16, // Opcode: LNER +/* 572 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 580 +/* 576 */ MCD_OPC_Decode, 222, 12, 16, // Opcode: LTER +/* 580 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 588 +/* 584 */ MCD_OPC_Decode, 138, 10, 16, // Opcode: LCER +/* 588 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 596 +/* 592 */ MCD_OPC_Decode, 253, 8, 16, // Opcode: HER +/* 596 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 604 +/* 600 */ MCD_OPC_Decode, 164, 10, 17, // Opcode: LEDR +/* 604 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 612 +/* 608 */ MCD_OPC_Decode, 161, 3, 13, // Opcode: AXR +/* 612 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 620 +/* 616 */ MCD_OPC_Decode, 151, 16, 13, // Opcode: SXR +/* 620 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 628 +/* 624 */ MCD_OPC_Decode, 166, 10, 16, // Opcode: LER +/* 628 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 636 +/* 632 */ MCD_OPC_Decode, 176, 4, 16, // Opcode: CER +/* 636 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 644 +/* 640 */ MCD_OPC_Decode, 238, 2, 18, // Opcode: AER +/* 644 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 652 +/* 648 */ MCD_OPC_Decode, 199, 14, 18, // Opcode: SER +/* 652 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 660 +/* 656 */ MCD_OPC_Decode, 144, 13, 19, // Opcode: MDER +/* 660 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 668 +/* 664 */ MCD_OPC_Decode, 197, 8, 18, // Opcode: DER +/* 668 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 676 +/* 672 */ MCD_OPC_Decode, 157, 3, 18, // Opcode: AUR +/* 676 */ MCD_OPC_FilterValue, 63, 4, 0, // Skip to: 684 +/* 680 */ MCD_OPC_Decode, 146, 16, 18, // Opcode: SUR +/* 684 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11 +/* 7 */ MCD_OPC_Decode, 183, 15, 20, // Opcode: STH +/* 11 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 19 +/* 15 */ MCD_OPC_Decode, 237, 9, 21, // Opcode: LA +/* 19 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 27 +/* 23 */ MCD_OPC_Decode, 158, 15, 20, // Opcode: STC +/* 27 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 35 +/* 31 */ MCD_OPC_Decode, 128, 9, 22, // Opcode: IC +/* 35 */ MCD_OPC_FilterValue, 68, 4, 0, // Skip to: 43 +/* 39 */ MCD_OPC_Decode, 238, 8, 21, // Opcode: EX +/* 43 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 51 +/* 47 */ MCD_OPC_Decode, 167, 3, 21, // Opcode: BAL +/* 51 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 59 +/* 55 */ MCD_OPC_Decode, 196, 3, 23, // Opcode: BCT +/* 59 */ MCD_OPC_FilterValue, 71, 127, 0, // Skip to: 190 +/* 63 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 66 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 74 +/* 70 */ MCD_OPC_Decode, 189, 3, 24, // Opcode: BAsmO +/* 74 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 82 +/* 78 */ MCD_OPC_Decode, 173, 3, 24, // Opcode: BAsmH +/* 82 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 90 +/* 86 */ MCD_OPC_Decode, 183, 3, 24, // Opcode: BAsmNLE +/* 90 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 98 +/* 94 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: BAsmL +/* 98 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 106 +/* 102 */ MCD_OPC_Decode, 181, 3, 24, // Opcode: BAsmNHE +/* 106 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 114 +/* 110 */ MCD_OPC_Decode, 177, 3, 24, // Opcode: BAsmLH +/* 114 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 122 +/* 118 */ MCD_OPC_Decode, 179, 3, 24, // Opcode: BAsmNE +/* 122 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 130 +/* 126 */ MCD_OPC_Decode, 172, 3, 24, // Opcode: BAsmE +/* 130 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 138 +/* 134 */ MCD_OPC_Decode, 184, 3, 24, // Opcode: BAsmNLH +/* 138 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 146 +/* 142 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: BAsmHE +/* 146 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 154 +/* 150 */ MCD_OPC_Decode, 182, 3, 24, // Opcode: BAsmNL +/* 154 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 162 +/* 158 */ MCD_OPC_Decode, 176, 3, 24, // Opcode: BAsmLE +/* 162 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 170 +/* 166 */ MCD_OPC_Decode, 180, 3, 24, // Opcode: BAsmNH +/* 170 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 178 +/* 174 */ MCD_OPC_Decode, 186, 3, 24, // Opcode: BAsmNO +/* 178 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 186 +/* 182 */ MCD_OPC_Decode, 165, 3, 24, // Opcode: B +/* 186 */ MCD_OPC_Decode, 193, 3, 25, // Opcode: BCAsm +/* 190 */ MCD_OPC_FilterValue, 72, 4, 0, // Skip to: 198 +/* 194 */ MCD_OPC_Decode, 192, 10, 20, // Opcode: LH +/* 198 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 206 +/* 202 */ MCD_OPC_Decode, 171, 5, 20, // Opcode: CH +/* 206 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 214 +/* 210 */ MCD_OPC_Decode, 250, 2, 23, // Opcode: AH +/* 214 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 222 +/* 218 */ MCD_OPC_Decode, 208, 14, 23, // Opcode: SH +/* 222 */ MCD_OPC_FilterValue, 76, 4, 0, // Skip to: 230 +/* 226 */ MCD_OPC_Decode, 159, 13, 23, // Opcode: MH +/* 230 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 238 +/* 234 */ MCD_OPC_Decode, 169, 3, 21, // Opcode: BAS +/* 238 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 246 +/* 242 */ MCD_OPC_Decode, 161, 8, 20, // Opcode: CVD +/* 246 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 254 +/* 250 */ MCD_OPC_Decode, 158, 8, 23, // Opcode: CVB +/* 254 */ MCD_OPC_FilterValue, 80, 4, 0, // Skip to: 262 +/* 258 */ MCD_OPC_Decode, 154, 15, 20, // Opcode: ST +/* 262 */ MCD_OPC_FilterValue, 81, 4, 0, // Skip to: 270 +/* 266 */ MCD_OPC_Decode, 242, 9, 21, // Opcode: LAE +/* 270 */ MCD_OPC_FilterValue, 84, 4, 0, // Skip to: 278 +/* 274 */ MCD_OPC_Decode, 226, 13, 23, // Opcode: N +/* 278 */ MCD_OPC_FilterValue, 85, 4, 0, // Skip to: 286 +/* 282 */ MCD_OPC_Decode, 224, 5, 20, // Opcode: CL +/* 286 */ MCD_OPC_FilterValue, 86, 4, 0, // Skip to: 294 +/* 290 */ MCD_OPC_Decode, 244, 13, 23, // Opcode: O +/* 294 */ MCD_OPC_FilterValue, 87, 4, 0, // Skip to: 302 +/* 298 */ MCD_OPC_Decode, 226, 21, 23, // Opcode: X +/* 302 */ MCD_OPC_FilterValue, 88, 4, 0, // Skip to: 310 +/* 306 */ MCD_OPC_Decode, 236, 9, 20, // Opcode: L +/* 310 */ MCD_OPC_FilterValue, 89, 4, 0, // Skip to: 318 +/* 314 */ MCD_OPC_Decode, 138, 4, 20, // Opcode: C +/* 318 */ MCD_OPC_FilterValue, 90, 4, 0, // Skip to: 326 +/* 322 */ MCD_OPC_Decode, 228, 2, 23, // Opcode: A +/* 326 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 334 +/* 330 */ MCD_OPC_Decode, 177, 14, 23, // Opcode: S +/* 334 */ MCD_OPC_FilterValue, 92, 4, 0, // Skip to: 342 +/* 338 */ MCD_OPC_Decode, 250, 12, 26, // Opcode: M +/* 342 */ MCD_OPC_FilterValue, 93, 4, 0, // Skip to: 350 +/* 346 */ MCD_OPC_Decode, 187, 8, 26, // Opcode: D +/* 350 */ MCD_OPC_FilterValue, 94, 4, 0, // Skip to: 358 +/* 354 */ MCD_OPC_Decode, 129, 3, 23, // Opcode: AL +/* 358 */ MCD_OPC_FilterValue, 95, 4, 0, // Skip to: 366 +/* 362 */ MCD_OPC_Decode, 215, 14, 23, // Opcode: SL +/* 366 */ MCD_OPC_FilterValue, 96, 4, 0, // Skip to: 374 +/* 370 */ MCD_OPC_Decode, 172, 15, 27, // Opcode: STD +/* 374 */ MCD_OPC_FilterValue, 103, 4, 0, // Skip to: 382 +/* 378 */ MCD_OPC_Decode, 213, 13, 28, // Opcode: MXD +/* 382 */ MCD_OPC_FilterValue, 104, 4, 0, // Skip to: 390 +/* 386 */ MCD_OPC_Decode, 146, 10, 27, // Opcode: LD +/* 390 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 398 +/* 394 */ MCD_OPC_Decode, 139, 4, 27, // Opcode: CD +/* 398 */ MCD_OPC_FilterValue, 106, 4, 0, // Skip to: 406 +/* 402 */ MCD_OPC_Decode, 229, 2, 29, // Opcode: AD +/* 406 */ MCD_OPC_FilterValue, 107, 4, 0, // Skip to: 414 +/* 410 */ MCD_OPC_Decode, 190, 14, 29, // Opcode: SD +/* 414 */ MCD_OPC_FilterValue, 108, 4, 0, // Skip to: 422 +/* 418 */ MCD_OPC_Decode, 138, 13, 29, // Opcode: MD +/* 422 */ MCD_OPC_FilterValue, 109, 4, 0, // Skip to: 430 +/* 426 */ MCD_OPC_Decode, 188, 8, 29, // Opcode: DD +/* 430 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 438 +/* 434 */ MCD_OPC_Decode, 158, 3, 29, // Opcode: AW +/* 438 */ MCD_OPC_FilterValue, 111, 4, 0, // Skip to: 446 +/* 442 */ MCD_OPC_Decode, 148, 16, 29, // Opcode: SW +/* 446 */ MCD_OPC_FilterValue, 112, 4, 0, // Skip to: 454 +/* 450 */ MCD_OPC_Decode, 174, 15, 30, // Opcode: STE +/* 454 */ MCD_OPC_FilterValue, 113, 4, 0, // Skip to: 462 +/* 458 */ MCD_OPC_Decode, 168, 13, 23, // Opcode: MS +/* 462 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 470 +/* 466 */ MCD_OPC_Decode, 161, 10, 30, // Opcode: LE +/* 470 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 478 +/* 474 */ MCD_OPC_Decode, 164, 4, 30, // Opcode: CE +/* 478 */ MCD_OPC_FilterValue, 122, 4, 0, // Skip to: 486 +/* 482 */ MCD_OPC_Decode, 235, 2, 31, // Opcode: AE +/* 486 */ MCD_OPC_FilterValue, 123, 4, 0, // Skip to: 494 +/* 490 */ MCD_OPC_Decode, 196, 14, 31, // Opcode: SE +/* 494 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 502 +/* 498 */ MCD_OPC_Decode, 141, 13, 29, // Opcode: MDE +/* 502 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 510 +/* 506 */ MCD_OPC_Decode, 194, 8, 31, // Opcode: DE +/* 510 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 518 +/* 514 */ MCD_OPC_Decode, 156, 3, 31, // Opcode: AU +/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 +/* 522 */ MCD_OPC_Decode, 145, 16, 31, // Opcode: SU +/* 526 */ MCD_OPC_FilterValue, 128, 1, 10, 0, // Skip to: 541 +/* 531 */ MCD_OPC_CheckField, 16, 8, 0, 67, 31, // Skip to: 8540 +/* 537 */ MCD_OPC_Decode, 153, 15, 32, // Opcode: SSM +/* 541 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 556 +/* 546 */ MCD_OPC_CheckField, 16, 8, 0, 52, 31, // Skip to: 8540 +/* 552 */ MCD_OPC_Decode, 197, 12, 32, // Opcode: LPSW +/* 556 */ MCD_OPC_FilterValue, 131, 1, 4, 0, // Skip to: 565 +/* 561 */ MCD_OPC_Decode, 198, 8, 33, // Opcode: DIAG +/* 565 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 574 +/* 570 */ MCD_OPC_Decode, 255, 3, 34, // Opcode: BRXH +/* 574 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 583 +/* 579 */ MCD_OPC_Decode, 129, 4, 34, // Opcode: BRXLE +/* 583 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 592 +/* 588 */ MCD_OPC_Decode, 134, 4, 35, // Opcode: BXH +/* 592 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 601 +/* 597 */ MCD_OPC_Decode, 136, 4, 35, // Opcode: BXLE +/* 601 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 616 +/* 606 */ MCD_OPC_CheckField, 16, 4, 0, 248, 30, // Skip to: 8540 +/* 612 */ MCD_OPC_Decode, 138, 15, 36, // Opcode: SRL +/* 616 */ MCD_OPC_FilterValue, 137, 1, 10, 0, // Skip to: 631 +/* 621 */ MCD_OPC_CheckField, 16, 4, 0, 233, 30, // Skip to: 8540 +/* 627 */ MCD_OPC_Decode, 235, 14, 36, // Opcode: SLL +/* 631 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 646 +/* 636 */ MCD_OPC_CheckField, 16, 4, 0, 218, 30, // Skip to: 8540 +/* 642 */ MCD_OPC_Decode, 131, 15, 36, // Opcode: SRA +/* 646 */ MCD_OPC_FilterValue, 139, 1, 10, 0, // Skip to: 661 +/* 651 */ MCD_OPC_CheckField, 16, 4, 0, 203, 30, // Skip to: 8540 +/* 657 */ MCD_OPC_Decode, 216, 14, 36, // Opcode: SLA +/* 661 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 676 +/* 666 */ MCD_OPC_CheckField, 16, 4, 0, 188, 30, // Skip to: 8540 +/* 672 */ MCD_OPC_Decode, 135, 15, 37, // Opcode: SRDL +/* 676 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 691 +/* 681 */ MCD_OPC_CheckField, 16, 4, 0, 173, 30, // Skip to: 8540 +/* 687 */ MCD_OPC_Decode, 224, 14, 37, // Opcode: SLDL +/* 691 */ MCD_OPC_FilterValue, 142, 1, 10, 0, // Skip to: 706 +/* 696 */ MCD_OPC_CheckField, 16, 4, 0, 158, 30, // Skip to: 8540 +/* 702 */ MCD_OPC_Decode, 134, 15, 37, // Opcode: SRDA +/* 706 */ MCD_OPC_FilterValue, 143, 1, 10, 0, // Skip to: 721 +/* 711 */ MCD_OPC_CheckField, 16, 4, 0, 143, 30, // Skip to: 8540 +/* 717 */ MCD_OPC_Decode, 223, 14, 37, // Opcode: SLDA +/* 721 */ MCD_OPC_FilterValue, 144, 1, 4, 0, // Skip to: 730 +/* 726 */ MCD_OPC_Decode, 188, 15, 33, // Opcode: STM +/* 730 */ MCD_OPC_FilterValue, 145, 1, 4, 0, // Skip to: 739 +/* 735 */ MCD_OPC_Decode, 175, 16, 38, // Opcode: TM +/* 739 */ MCD_OPC_FilterValue, 146, 1, 4, 0, // Skip to: 748 +/* 744 */ MCD_OPC_Decode, 205, 13, 38, // Opcode: MVI +/* 748 */ MCD_OPC_FilterValue, 147, 1, 10, 0, // Skip to: 763 +/* 753 */ MCD_OPC_CheckField, 16, 8, 0, 101, 30, // Skip to: 8540 +/* 759 */ MCD_OPC_Decode, 204, 16, 32, // Opcode: TS +/* 763 */ MCD_OPC_FilterValue, 148, 1, 4, 0, // Skip to: 772 +/* 768 */ MCD_OPC_Decode, 231, 13, 38, // Opcode: NI +/* 772 */ MCD_OPC_FilterValue, 149, 1, 4, 0, // Skip to: 781 +/* 777 */ MCD_OPC_Decode, 239, 6, 38, // Opcode: CLI +/* 781 */ MCD_OPC_FilterValue, 150, 1, 4, 0, // Skip to: 790 +/* 786 */ MCD_OPC_Decode, 249, 13, 38, // Opcode: OI +/* 790 */ MCD_OPC_FilterValue, 151, 1, 4, 0, // Skip to: 799 +/* 795 */ MCD_OPC_Decode, 231, 21, 38, // Opcode: XI +/* 799 */ MCD_OPC_FilterValue, 152, 1, 4, 0, // Skip to: 808 +/* 804 */ MCD_OPC_Decode, 225, 10, 33, // Opcode: LM +/* 808 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 817 +/* 813 */ MCD_OPC_Decode, 185, 16, 33, // Opcode: TRACE +/* 817 */ MCD_OPC_FilterValue, 154, 1, 4, 0, // Skip to: 826 +/* 822 */ MCD_OPC_Decode, 244, 9, 39, // Opcode: LAM +/* 826 */ MCD_OPC_FilterValue, 155, 1, 4, 0, // Skip to: 835 +/* 831 */ MCD_OPC_Decode, 155, 15, 39, // Opcode: STAM +/* 835 */ MCD_OPC_FilterValue, 165, 1, 131, 0, // Skip to: 971 +/* 840 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 843 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 851 +/* 847 */ MCD_OPC_Decode, 140, 9, 40, // Opcode: IIHH +/* 851 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 859 +/* 855 */ MCD_OPC_Decode, 141, 9, 40, // Opcode: IIHL +/* 859 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 867 +/* 863 */ MCD_OPC_Decode, 143, 9, 41, // Opcode: IILH +/* 867 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 875 +/* 871 */ MCD_OPC_Decode, 144, 9, 41, // Opcode: IILL +/* 875 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 883 +/* 879 */ MCD_OPC_Decode, 234, 13, 40, // Opcode: NIHH +/* 883 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 891 +/* 887 */ MCD_OPC_Decode, 235, 13, 40, // Opcode: NIHL +/* 891 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 899 +/* 895 */ MCD_OPC_Decode, 237, 13, 41, // Opcode: NILH +/* 899 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 907 +/* 903 */ MCD_OPC_Decode, 238, 13, 41, // Opcode: NILL +/* 907 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 915 +/* 911 */ MCD_OPC_Decode, 251, 13, 40, // Opcode: OIHH +/* 915 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 923 +/* 919 */ MCD_OPC_Decode, 252, 13, 40, // Opcode: OIHL +/* 923 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 931 +/* 927 */ MCD_OPC_Decode, 254, 13, 41, // Opcode: OILH +/* 931 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 939 +/* 935 */ MCD_OPC_Decode, 255, 13, 41, // Opcode: OILL +/* 939 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 947 +/* 943 */ MCD_OPC_Decode, 219, 10, 42, // Opcode: LLIHH +/* 947 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 955 +/* 951 */ MCD_OPC_Decode, 220, 10, 42, // Opcode: LLIHL +/* 955 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 963 +/* 959 */ MCD_OPC_Decode, 222, 10, 42, // Opcode: LLILH +/* 963 */ MCD_OPC_FilterValue, 15, 149, 29, // Skip to: 8540 +/* 967 */ MCD_OPC_Decode, 223, 10, 42, // Opcode: LLILL +/* 971 */ MCD_OPC_FilterValue, 167, 1, 254, 0, // Skip to: 1230 +/* 976 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 979 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 987 +/* 983 */ MCD_OPC_Decode, 178, 16, 43, // Opcode: TMLH +/* 987 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 995 +/* 991 */ MCD_OPC_Decode, 179, 16, 43, // Opcode: TMLL +/* 995 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1003 +/* 999 */ MCD_OPC_Decode, 176, 16, 44, // Opcode: TMHH +/* 1003 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1011 +/* 1007 */ MCD_OPC_Decode, 177, 16, 44, // Opcode: TMHL +/* 1011 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 1142 +/* 1015 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 1018 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1026 +/* 1022 */ MCD_OPC_Decode, 196, 9, 45, // Opcode: JAsmO +/* 1026 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1034 +/* 1030 */ MCD_OPC_Decode, 180, 9, 45, // Opcode: JAsmH +/* 1034 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1042 +/* 1038 */ MCD_OPC_Decode, 190, 9, 45, // Opcode: JAsmNLE +/* 1042 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1050 +/* 1046 */ MCD_OPC_Decode, 182, 9, 45, // Opcode: JAsmL +/* 1050 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1058 +/* 1054 */ MCD_OPC_Decode, 188, 9, 45, // Opcode: JAsmNHE +/* 1058 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1066 +/* 1062 */ MCD_OPC_Decode, 184, 9, 45, // Opcode: JAsmLH +/* 1066 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1074 +/* 1070 */ MCD_OPC_Decode, 186, 9, 45, // Opcode: JAsmNE +/* 1074 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1082 +/* 1078 */ MCD_OPC_Decode, 179, 9, 45, // Opcode: JAsmE +/* 1082 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1090 +/* 1086 */ MCD_OPC_Decode, 191, 9, 45, // Opcode: JAsmNLH +/* 1090 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1098 +/* 1094 */ MCD_OPC_Decode, 181, 9, 45, // Opcode: JAsmHE +/* 1098 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1106 +/* 1102 */ MCD_OPC_Decode, 189, 9, 45, // Opcode: JAsmNL +/* 1106 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1114 +/* 1110 */ MCD_OPC_Decode, 183, 9, 45, // Opcode: JAsmLE +/* 1114 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1122 +/* 1118 */ MCD_OPC_Decode, 187, 9, 45, // Opcode: JAsmNH +/* 1122 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1130 +/* 1126 */ MCD_OPC_Decode, 193, 9, 45, // Opcode: JAsmNO +/* 1130 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1138 +/* 1134 */ MCD_OPC_Decode, 178, 9, 45, // Opcode: J +/* 1138 */ MCD_OPC_Decode, 249, 3, 46, // Opcode: BRCAsm +/* 1142 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1150 +/* 1146 */ MCD_OPC_Decode, 226, 3, 47, // Opcode: BRAS +/* 1150 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1158 +/* 1154 */ MCD_OPC_Decode, 252, 3, 48, // Opcode: BRCT +/* 1158 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1166 +/* 1162 */ MCD_OPC_Decode, 253, 3, 49, // Opcode: BRCTG +/* 1166 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1174 +/* 1170 */ MCD_OPC_Decode, 194, 10, 50, // Opcode: LHI +/* 1174 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1182 +/* 1178 */ MCD_OPC_Decode, 186, 10, 51, // Opcode: LGHI +/* 1182 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1190 +/* 1186 */ MCD_OPC_Decode, 253, 2, 52, // Opcode: AHI +/* 1190 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1198 +/* 1194 */ MCD_OPC_Decode, 245, 2, 53, // Opcode: AGHI +/* 1198 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1206 +/* 1202 */ MCD_OPC_Decode, 160, 13, 52, // Opcode: MHI +/* 1206 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1214 +/* 1210 */ MCD_OPC_Decode, 157, 13, 53, // Opcode: MGHI +/* 1214 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1222 +/* 1218 */ MCD_OPC_Decode, 175, 5, 50, // Opcode: CHI +/* 1222 */ MCD_OPC_FilterValue, 15, 146, 28, // Skip to: 8540 +/* 1226 */ MCD_OPC_Decode, 205, 4, 51, // Opcode: CGHI +/* 1230 */ MCD_OPC_FilterValue, 168, 1, 4, 0, // Skip to: 1239 +/* 1235 */ MCD_OPC_Decode, 196, 13, 54, // Opcode: MVCLE +/* 1239 */ MCD_OPC_FilterValue, 169, 1, 4, 0, // Skip to: 1248 +/* 1244 */ MCD_OPC_Decode, 227, 5, 54, // Opcode: CLCLE +/* 1248 */ MCD_OPC_FilterValue, 172, 1, 4, 0, // Skip to: 1257 +/* 1253 */ MCD_OPC_Decode, 192, 15, 38, // Opcode: STNSM +/* 1257 */ MCD_OPC_FilterValue, 173, 1, 4, 0, // Skip to: 1266 +/* 1262 */ MCD_OPC_Decode, 131, 16, 38, // Opcode: STOSM +/* 1266 */ MCD_OPC_FilterValue, 174, 1, 4, 0, // Skip to: 1275 +/* 1271 */ MCD_OPC_Decode, 214, 14, 55, // Opcode: SIGP +/* 1275 */ MCD_OPC_FilterValue, 175, 1, 4, 0, // Skip to: 1284 +/* 1280 */ MCD_OPC_Decode, 137, 13, 38, // Opcode: MC +/* 1284 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 1293 +/* 1289 */ MCD_OPC_Decode, 203, 12, 21, // Opcode: LRA +/* 1293 */ MCD_OPC_FilterValue, 178, 1, 65, 5, // Skip to: 2643 +/* 1298 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 1301 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1309 +/* 1305 */ MCD_OPC_Decode, 187, 15, 32, // Opcode: STIDP +/* 1309 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1317 +/* 1313 */ MCD_OPC_Decode, 187, 14, 32, // Opcode: SCK +/* 1317 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1325 +/* 1321 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: STCK +/* 1325 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1333 +/* 1329 */ MCD_OPC_Decode, 188, 14, 32, // Opcode: SCKC +/* 1333 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1341 +/* 1337 */ MCD_OPC_Decode, 161, 15, 32, // Opcode: STCKC +/* 1341 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1349 +/* 1345 */ MCD_OPC_Decode, 246, 14, 32, // Opcode: SPT +/* 1349 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1357 +/* 1353 */ MCD_OPC_Decode, 133, 16, 32, // Opcode: STPT +/* 1357 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1365 +/* 1361 */ MCD_OPC_Decode, 244, 14, 32, // Opcode: SPKA +/* 1365 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1379 +/* 1369 */ MCD_OPC_CheckField, 0, 16, 0, 253, 27, // Skip to: 8540 +/* 1375 */ MCD_OPC_Decode, 145, 9, 0, // Opcode: IPK +/* 1379 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1393 +/* 1383 */ MCD_OPC_CheckField, 0, 16, 0, 239, 27, // Skip to: 8540 +/* 1389 */ MCD_OPC_Decode, 155, 14, 0, // Opcode: PTLB +/* 1393 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1401 +/* 1397 */ MCD_OPC_Decode, 247, 14, 32, // Opcode: SPX +/* 1401 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1409 +/* 1405 */ MCD_OPC_Decode, 134, 16, 32, // Opcode: STPX +/* 1409 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1417 +/* 1413 */ MCD_OPC_Decode, 157, 15, 32, // Opcode: STAP +/* 1417 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 1425 +/* 1421 */ MCD_OPC_Decode, 212, 14, 32, // Opcode: SIE +/* 1425 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1433 +/* 1429 */ MCD_OPC_Decode, 134, 14, 32, // Opcode: PC +/* 1433 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1441 +/* 1437 */ MCD_OPC_Decode, 178, 14, 32, // Opcode: SAC +/* 1441 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1449 +/* 1445 */ MCD_OPC_Decode, 178, 4, 32, // Opcode: CFC +/* 1449 */ MCD_OPC_FilterValue, 33, 24, 0, // Skip to: 1477 +/* 1453 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 1463 +/* 1459 */ MCD_OPC_Decode, 149, 9, 56, // Opcode: IPTEOptOpt +/* 1463 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 1473 +/* 1469 */ MCD_OPC_Decode, 148, 9, 57, // Opcode: IPTEOpt +/* 1473 */ MCD_OPC_Decode, 147, 9, 58, // Opcode: IPTE +/* 1477 */ MCD_OPC_FilterValue, 34, 16, 0, // Skip to: 1497 +/* 1481 */ MCD_OPC_CheckField, 8, 8, 0, 141, 27, // Skip to: 8540 +/* 1487 */ MCD_OPC_CheckField, 0, 4, 0, 135, 27, // Skip to: 8540 +/* 1493 */ MCD_OPC_Decode, 146, 9, 1, // Opcode: IPM +/* 1497 */ MCD_OPC_FilterValue, 35, 10, 0, // Skip to: 1511 +/* 1501 */ MCD_OPC_CheckField, 8, 8, 0, 121, 27, // Skip to: 8540 +/* 1507 */ MCD_OPC_Decode, 152, 9, 3, // Opcode: IVSK +/* 1511 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1531 +/* 1515 */ MCD_OPC_CheckField, 8, 8, 0, 107, 27, // Skip to: 8540 +/* 1521 */ MCD_OPC_CheckField, 0, 4, 0, 101, 27, // Skip to: 8540 +/* 1527 */ MCD_OPC_Decode, 255, 8, 1, // Opcode: IAC +/* 1531 */ MCD_OPC_FilterValue, 37, 16, 0, // Skip to: 1551 +/* 1535 */ MCD_OPC_CheckField, 8, 8, 0, 87, 27, // Skip to: 8540 +/* 1541 */ MCD_OPC_CheckField, 0, 4, 0, 81, 27, // Skip to: 8540 +/* 1547 */ MCD_OPC_Decode, 149, 15, 1, // Opcode: SSAR +/* 1551 */ MCD_OPC_FilterValue, 38, 16, 0, // Skip to: 1571 +/* 1555 */ MCD_OPC_CheckField, 8, 8, 0, 67, 27, // Skip to: 8540 +/* 1561 */ MCD_OPC_CheckField, 0, 4, 0, 61, 27, // Skip to: 8540 +/* 1567 */ MCD_OPC_Decode, 226, 8, 1, // Opcode: EPAR +/* 1571 */ MCD_OPC_FilterValue, 39, 16, 0, // Skip to: 1591 +/* 1575 */ MCD_OPC_CheckField, 8, 8, 0, 47, 27, // Skip to: 8540 +/* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 41, 27, // Skip to: 8540 +/* 1587 */ MCD_OPC_Decode, 232, 8, 1, // Opcode: ESAR +/* 1591 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 1605 +/* 1595 */ MCD_OPC_CheckField, 8, 8, 0, 27, 27, // Skip to: 8540 +/* 1601 */ MCD_OPC_Decode, 151, 14, 59, // Opcode: PT +/* 1605 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 1619 +/* 1609 */ MCD_OPC_CheckField, 8, 8, 0, 13, 27, // Skip to: 8540 +/* 1615 */ MCD_OPC_Decode, 151, 9, 3, // Opcode: ISKE +/* 1619 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 1633 +/* 1623 */ MCD_OPC_CheckField, 8, 8, 0, 255, 26, // Skip to: 8540 +/* 1629 */ MCD_OPC_Decode, 171, 14, 59, // Opcode: RRBE +/* 1633 */ MCD_OPC_FilterValue, 43, 21, 0, // Skip to: 1658 +/* 1637 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1640 */ MCD_OPC_FilterValue, 0, 240, 26, // Skip to: 8540 +/* 1644 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 1654 +/* 1650 */ MCD_OPC_Decode, 152, 15, 59, // Opcode: SSKEOpt +/* 1654 */ MCD_OPC_Decode, 151, 15, 60, // Opcode: SSKE +/* 1658 */ MCD_OPC_FilterValue, 44, 10, 0, // Skip to: 1672 +/* 1662 */ MCD_OPC_CheckField, 8, 8, 0, 216, 26, // Skip to: 8540 +/* 1668 */ MCD_OPC_Decode, 158, 16, 61, // Opcode: TB +/* 1672 */ MCD_OPC_FilterValue, 45, 10, 0, // Skip to: 1686 +/* 1676 */ MCD_OPC_CheckField, 8, 8, 0, 202, 26, // Skip to: 8540 +/* 1682 */ MCD_OPC_Decode, 212, 8, 13, // Opcode: DXR +/* 1686 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 1700 +/* 1690 */ MCD_OPC_CheckField, 8, 8, 0, 188, 26, // Skip to: 8540 +/* 1696 */ MCD_OPC_Decode, 141, 14, 61, // Opcode: PGIN +/* 1700 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 1714 +/* 1704 */ MCD_OPC_CheckField, 8, 8, 0, 174, 26, // Skip to: 8540 +/* 1710 */ MCD_OPC_Decode, 142, 14, 61, // Opcode: PGOUT +/* 1714 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 1728 +/* 1718 */ MCD_OPC_CheckField, 0, 16, 0, 160, 26, // Skip to: 8540 +/* 1724 */ MCD_OPC_Decode, 133, 8, 0, // Opcode: CSCH +/* 1728 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 1742 +/* 1732 */ MCD_OPC_CheckField, 0, 16, 0, 146, 26, // Skip to: 8540 +/* 1738 */ MCD_OPC_Decode, 254, 8, 0, // Opcode: HSCH +/* 1742 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 1750 +/* 1746 */ MCD_OPC_Decode, 170, 13, 32, // Opcode: MSCH +/* 1750 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1758 +/* 1754 */ MCD_OPC_Decode, 150, 15, 32, // Opcode: SSCH +/* 1758 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 1766 +/* 1762 */ MCD_OPC_Decode, 140, 16, 32, // Opcode: STSCH +/* 1766 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1774 +/* 1770 */ MCD_OPC_Decode, 205, 16, 32, // Opcode: TSCH +/* 1774 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 1782 +/* 1778 */ MCD_OPC_Decode, 182, 16, 32, // Opcode: TPI +/* 1782 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 1796 +/* 1786 */ MCD_OPC_CheckField, 0, 16, 0, 92, 26, // Skip to: 8540 +/* 1792 */ MCD_OPC_Decode, 180, 14, 0, // Opcode: SAL +/* 1796 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 1810 +/* 1800 */ MCD_OPC_CheckField, 0, 16, 0, 78, 26, // Skip to: 8540 +/* 1806 */ MCD_OPC_Decode, 175, 14, 0, // Opcode: RSCH +/* 1810 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1818 +/* 1814 */ MCD_OPC_Decode, 168, 15, 32, // Opcode: STCRW +/* 1818 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 1826 +/* 1822 */ MCD_OPC_Decode, 167, 15, 32, // Opcode: STCPS +/* 1826 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 1840 +/* 1830 */ MCD_OPC_CheckField, 0, 16, 0, 48, 26, // Skip to: 8540 +/* 1836 */ MCD_OPC_Decode, 160, 14, 0, // Opcode: RCHP +/* 1840 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 1854 +/* 1844 */ MCD_OPC_CheckField, 0, 16, 0, 34, 26, // Skip to: 8540 +/* 1850 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: SCHM +/* 1854 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 1868 +/* 1858 */ MCD_OPC_CheckField, 8, 8, 0, 20, 26, // Skip to: 8540 +/* 1864 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: BAKR +/* 1868 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 1882 +/* 1872 */ MCD_OPC_CheckField, 8, 8, 0, 6, 26, // Skip to: 8540 +/* 1878 */ MCD_OPC_Decode, 223, 5, 62, // Opcode: CKSM +/* 1882 */ MCD_OPC_FilterValue, 68, 10, 0, // Skip to: 1896 +/* 1886 */ MCD_OPC_CheckField, 8, 8, 0, 248, 25, // Skip to: 8540 +/* 1892 */ MCD_OPC_Decode, 251, 14, 11, // Opcode: SQDR +/* 1896 */ MCD_OPC_FilterValue, 69, 10, 0, // Skip to: 1910 +/* 1900 */ MCD_OPC_CheckField, 8, 8, 0, 234, 25, // Skip to: 8540 +/* 1906 */ MCD_OPC_Decode, 255, 14, 16, // Opcode: SQER +/* 1910 */ MCD_OPC_FilterValue, 70, 10, 0, // Skip to: 1924 +/* 1914 */ MCD_OPC_CheckField, 8, 8, 0, 220, 25, // Skip to: 8540 +/* 1920 */ MCD_OPC_Decode, 142, 16, 59, // Opcode: STURA +/* 1924 */ MCD_OPC_FilterValue, 71, 16, 0, // Skip to: 1944 +/* 1928 */ MCD_OPC_CheckField, 8, 8, 0, 206, 25, // Skip to: 8540 +/* 1934 */ MCD_OPC_CheckField, 0, 4, 0, 200, 25, // Skip to: 8540 +/* 1940 */ MCD_OPC_Decode, 189, 13, 63, // Opcode: MSTA +/* 1944 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 1958 +/* 1948 */ MCD_OPC_CheckField, 0, 16, 0, 186, 25, // Skip to: 8540 +/* 1954 */ MCD_OPC_Decode, 133, 14, 0, // Opcode: PALB +/* 1958 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 1972 +/* 1962 */ MCD_OPC_CheckField, 8, 8, 0, 172, 25, // Skip to: 8540 +/* 1968 */ MCD_OPC_Decode, 229, 8, 8, // Opcode: EREG +/* 1972 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 1986 +/* 1976 */ MCD_OPC_CheckField, 8, 8, 0, 158, 25, // Skip to: 8540 +/* 1982 */ MCD_OPC_Decode, 235, 8, 64, // Opcode: ESTA +/* 1986 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 2000 +/* 1990 */ MCD_OPC_CheckField, 8, 8, 0, 144, 25, // Skip to: 8540 +/* 1996 */ MCD_OPC_Decode, 232, 12, 59, // Opcode: LURA +/* 2000 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 2014 +/* 2004 */ MCD_OPC_CheckField, 8, 8, 0, 130, 25, // Skip to: 8540 +/* 2010 */ MCD_OPC_Decode, 157, 16, 65, // Opcode: TAR +/* 2014 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 2028 +/* 2018 */ MCD_OPC_CheckField, 8, 8, 0, 116, 25, // Skip to: 8540 +/* 2024 */ MCD_OPC_Decode, 213, 7, 66, // Opcode: CPYA +/* 2028 */ MCD_OPC_FilterValue, 78, 10, 0, // Skip to: 2042 +/* 2032 */ MCD_OPC_CheckField, 8, 8, 0, 102, 25, // Skip to: 8540 +/* 2038 */ MCD_OPC_Decode, 184, 14, 65, // Opcode: SAR +/* 2042 */ MCD_OPC_FilterValue, 79, 10, 0, // Skip to: 2056 +/* 2046 */ MCD_OPC_CheckField, 8, 8, 0, 88, 25, // Skip to: 8540 +/* 2052 */ MCD_OPC_Decode, 215, 8, 67, // Opcode: EAR +/* 2056 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 2070 +/* 2060 */ MCD_OPC_CheckField, 8, 8, 0, 74, 25, // Skip to: 8540 +/* 2066 */ MCD_OPC_Decode, 136, 8, 68, // Opcode: CSP +/* 2070 */ MCD_OPC_FilterValue, 82, 10, 0, // Skip to: 2084 +/* 2074 */ MCD_OPC_CheckField, 8, 8, 0, 60, 25, // Skip to: 8540 +/* 2080 */ MCD_OPC_Decode, 187, 13, 9, // Opcode: MSR +/* 2084 */ MCD_OPC_FilterValue, 84, 10, 0, // Skip to: 2098 +/* 2088 */ MCD_OPC_CheckField, 8, 8, 0, 46, 25, // Skip to: 8540 +/* 2094 */ MCD_OPC_Decode, 209, 13, 61, // Opcode: MVPG +/* 2098 */ MCD_OPC_FilterValue, 85, 10, 0, // Skip to: 2112 +/* 2102 */ MCD_OPC_CheckField, 8, 8, 0, 32, 25, // Skip to: 8540 +/* 2108 */ MCD_OPC_Decode, 210, 13, 69, // Opcode: MVST +/* 2112 */ MCD_OPC_FilterValue, 87, 10, 0, // Skip to: 2126 +/* 2116 */ MCD_OPC_CheckField, 8, 8, 0, 18, 25, // Skip to: 8540 +/* 2122 */ MCD_OPC_Decode, 152, 8, 7, // Opcode: CUSE +/* 2126 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 2140 +/* 2130 */ MCD_OPC_CheckField, 8, 8, 0, 4, 25, // Skip to: 8540 +/* 2136 */ MCD_OPC_Decode, 132, 4, 61, // Opcode: BSG +/* 2140 */ MCD_OPC_FilterValue, 90, 10, 0, // Skip to: 2154 +/* 2144 */ MCD_OPC_CheckField, 8, 8, 0, 246, 24, // Skip to: 8540 +/* 2150 */ MCD_OPC_Decode, 131, 4, 61, // Opcode: BSA +/* 2154 */ MCD_OPC_FilterValue, 93, 10, 0, // Skip to: 2168 +/* 2158 */ MCD_OPC_CheckField, 8, 8, 0, 232, 24, // Skip to: 8540 +/* 2164 */ MCD_OPC_Decode, 189, 7, 69, // Opcode: CLST +/* 2168 */ MCD_OPC_FilterValue, 94, 10, 0, // Skip to: 2182 +/* 2172 */ MCD_OPC_CheckField, 8, 8, 0, 218, 24, // Skip to: 8540 +/* 2178 */ MCD_OPC_Decode, 145, 15, 69, // Opcode: SRST +/* 2182 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 2196 +/* 2186 */ MCD_OPC_CheckField, 8, 8, 0, 204, 24, // Skip to: 8540 +/* 2192 */ MCD_OPC_Decode, 205, 7, 7, // Opcode: CMPSC +/* 2196 */ MCD_OPC_FilterValue, 116, 4, 0, // Skip to: 2204 +/* 2200 */ MCD_OPC_Decode, 213, 14, 32, // Opcode: SIGA +/* 2204 */ MCD_OPC_FilterValue, 118, 10, 0, // Skip to: 2218 +/* 2208 */ MCD_OPC_CheckField, 0, 16, 0, 182, 24, // Skip to: 8540 +/* 2214 */ MCD_OPC_Decode, 237, 21, 0, // Opcode: XSCH +/* 2218 */ MCD_OPC_FilterValue, 119, 4, 0, // Skip to: 2226 +/* 2222 */ MCD_OPC_Decode, 170, 14, 32, // Opcode: RP +/* 2226 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 2234 +/* 2230 */ MCD_OPC_Decode, 162, 15, 32, // Opcode: STCKE +/* 2234 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 2242 +/* 2238 */ MCD_OPC_Decode, 179, 14, 32, // Opcode: SACF +/* 2242 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 2250 +/* 2246 */ MCD_OPC_Decode, 163, 15, 32, // Opcode: STCKF +/* 2250 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 2258 +/* 2254 */ MCD_OPC_Decode, 141, 16, 32, // Opcode: STSI +/* 2258 */ MCD_OPC_FilterValue, 128, 1, 4, 0, // Skip to: 2267 +/* 2263 */ MCD_OPC_Decode, 194, 12, 32, // Opcode: LPP +/* 2267 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 2276 +/* 2272 */ MCD_OPC_Decode, 132, 10, 32, // Opcode: LCCTL +/* 2276 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 2285 +/* 2281 */ MCD_OPC_Decode, 183, 12, 32, // Opcode: LPCTL +/* 2285 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 2294 +/* 2290 */ MCD_OPC_Decode, 159, 14, 32, // Opcode: QSI +/* 2294 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 2303 +/* 2299 */ MCD_OPC_Decode, 214, 12, 32, // Opcode: LSCTL +/* 2303 */ MCD_OPC_FilterValue, 142, 1, 4, 0, // Skip to: 2312 +/* 2308 */ MCD_OPC_Decode, 158, 14, 32, // Opcode: QCTRI +/* 2312 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 2321 +/* 2317 */ MCD_OPC_Decode, 141, 15, 70, // Opcode: SRNM +/* 2321 */ MCD_OPC_FilterValue, 156, 1, 4, 0, // Skip to: 2330 +/* 2326 */ MCD_OPC_Decode, 179, 15, 32, // Opcode: STFPC +/* 2330 */ MCD_OPC_FilterValue, 157, 1, 4, 0, // Skip to: 2339 +/* 2335 */ MCD_OPC_Decode, 174, 10, 32, // Opcode: LFPC +/* 2339 */ MCD_OPC_FilterValue, 165, 1, 10, 0, // Skip to: 2354 +/* 2344 */ MCD_OPC_CheckField, 8, 8, 0, 46, 24, // Skip to: 8540 +/* 2350 */ MCD_OPC_Decode, 189, 16, 71, // Opcode: TRE +/* 2354 */ MCD_OPC_FilterValue, 166, 1, 21, 0, // Skip to: 2380 +/* 2359 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2362 */ MCD_OPC_FilterValue, 0, 30, 24, // Skip to: 8540 +/* 2366 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2376 +/* 2372 */ MCD_OPC_Decode, 146, 8, 7, // Opcode: CU21Opt +/* 2376 */ MCD_OPC_Decode, 145, 8, 72, // Opcode: CU21 +/* 2380 */ MCD_OPC_FilterValue, 167, 1, 21, 0, // Skip to: 2406 +/* 2385 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 2388 */ MCD_OPC_FilterValue, 0, 4, 24, // Skip to: 8540 +/* 2392 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2402 +/* 2398 */ MCD_OPC_Decode, 142, 8, 7, // Opcode: CU12Opt +/* 2402 */ MCD_OPC_Decode, 141, 8, 72, // Opcode: CU12 +/* 2406 */ MCD_OPC_FilterValue, 176, 1, 4, 0, // Skip to: 2415 +/* 2411 */ MCD_OPC_Decode, 178, 15, 32, // Opcode: STFLE +/* 2415 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 2424 +/* 2420 */ MCD_OPC_Decode, 177, 15, 32, // Opcode: STFL +/* 2424 */ MCD_OPC_FilterValue, 178, 1, 4, 0, // Skip to: 2433 +/* 2429 */ MCD_OPC_Decode, 198, 12, 32, // Opcode: LPSWE +/* 2433 */ MCD_OPC_FilterValue, 184, 1, 8, 0, // Skip to: 2446 +/* 2438 */ MCD_OPC_CheckPredicate, 0, 210, 23, // Skip to: 8540 +/* 2442 */ MCD_OPC_Decode, 142, 15, 70, // Opcode: SRNMB +/* 2446 */ MCD_OPC_FilterValue, 185, 1, 4, 0, // Skip to: 2455 +/* 2451 */ MCD_OPC_Decode, 143, 15, 70, // Opcode: SRNMT +/* 2455 */ MCD_OPC_FilterValue, 189, 1, 4, 0, // Skip to: 2464 +/* 2460 */ MCD_OPC_Decode, 171, 10, 32, // Opcode: LFAS +/* 2464 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 2479 +/* 2469 */ MCD_OPC_CheckField, 8, 8, 0, 177, 23, // Skip to: 8540 +/* 2475 */ MCD_OPC_Decode, 185, 14, 61, // Opcode: SCCTR +/* 2479 */ MCD_OPC_FilterValue, 225, 1, 10, 0, // Skip to: 2494 +/* 2484 */ MCD_OPC_CheckField, 8, 8, 0, 162, 23, // Skip to: 8540 +/* 2490 */ MCD_OPC_Decode, 243, 14, 61, // Opcode: SPCTR +/* 2494 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 2509 +/* 2499 */ MCD_OPC_CheckField, 8, 8, 0, 147, 23, // Skip to: 8540 +/* 2505 */ MCD_OPC_Decode, 217, 8, 61, // Opcode: ECCTR +/* 2509 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 2524 +/* 2514 */ MCD_OPC_CheckField, 8, 8, 0, 132, 23, // Skip to: 8540 +/* 2520 */ MCD_OPC_Decode, 227, 8, 61, // Opcode: EPCTR +/* 2524 */ MCD_OPC_FilterValue, 232, 1, 14, 0, // Skip to: 2543 +/* 2529 */ MCD_OPC_CheckPredicate, 1, 119, 23, // Skip to: 8540 +/* 2533 */ MCD_OPC_CheckField, 8, 4, 0, 113, 23, // Skip to: 8540 +/* 2539 */ MCD_OPC_Decode, 147, 14, 73, // Opcode: PPA +/* 2543 */ MCD_OPC_FilterValue, 236, 1, 20, 0, // Skip to: 2568 +/* 2548 */ MCD_OPC_CheckPredicate, 2, 100, 23, // Skip to: 8540 +/* 2552 */ MCD_OPC_CheckField, 8, 8, 0, 94, 23, // Skip to: 8540 +/* 2558 */ MCD_OPC_CheckField, 0, 4, 0, 88, 23, // Skip to: 8540 +/* 2564 */ MCD_OPC_Decode, 237, 8, 1, // Opcode: ETND +/* 2568 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 2583 +/* 2573 */ MCD_OPC_CheckField, 8, 8, 0, 73, 23, // Skip to: 8540 +/* 2579 */ MCD_OPC_Decode, 218, 8, 59, // Opcode: ECPGA +/* 2583 */ MCD_OPC_FilterValue, 248, 1, 14, 0, // Skip to: 2602 +/* 2588 */ MCD_OPC_CheckPredicate, 2, 60, 23, // Skip to: 8540 +/* 2592 */ MCD_OPC_CheckField, 0, 16, 0, 54, 23, // Skip to: 8540 +/* 2598 */ MCD_OPC_Decode, 172, 16, 0, // Opcode: TEND +/* 2602 */ MCD_OPC_FilterValue, 250, 1, 14, 0, // Skip to: 2621 +/* 2607 */ MCD_OPC_CheckPredicate, 3, 41, 23, // Skip to: 8540 +/* 2611 */ MCD_OPC_CheckField, 8, 8, 0, 35, 23, // Skip to: 8540 +/* 2617 */ MCD_OPC_Decode, 232, 13, 74, // Opcode: NIAI +/* 2621 */ MCD_OPC_FilterValue, 252, 1, 8, 0, // Skip to: 2634 +/* 2626 */ MCD_OPC_CheckPredicate, 2, 22, 23, // Skip to: 8540 +/* 2630 */ MCD_OPC_Decode, 155, 16, 32, // Opcode: TABORT +/* 2634 */ MCD_OPC_FilterValue, 255, 1, 13, 23, // Skip to: 8540 +/* 2639 */ MCD_OPC_Decode, 188, 16, 32, // Opcode: TRAP4 +/* 2643 */ MCD_OPC_FilterValue, 179, 1, 122, 10, // Skip to: 5330 +/* 2648 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 2651 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 2665 +/* 2655 */ MCD_OPC_CheckField, 8, 8, 0, 247, 22, // Skip to: 8540 +/* 2661 */ MCD_OPC_Decode, 190, 12, 16, // Opcode: LPEBR +/* 2665 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2679 +/* 2669 */ MCD_OPC_CheckField, 8, 8, 0, 233, 22, // Skip to: 8540 +/* 2675 */ MCD_OPC_Decode, 234, 10, 16, // Opcode: LNEBR +/* 2679 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2693 +/* 2683 */ MCD_OPC_CheckField, 8, 8, 0, 219, 22, // Skip to: 8540 +/* 2689 */ MCD_OPC_Decode, 220, 12, 16, // Opcode: LTEBR +/* 2693 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2707 +/* 2697 */ MCD_OPC_CheckField, 8, 8, 0, 205, 22, // Skip to: 8540 +/* 2703 */ MCD_OPC_Decode, 137, 10, 16, // Opcode: LCEBR +/* 2707 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 2721 +/* 2711 */ MCD_OPC_CheckField, 8, 8, 0, 191, 22, // Skip to: 8540 +/* 2717 */ MCD_OPC_Decode, 150, 10, 75, // Opcode: LDEBR +/* 2721 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2735 +/* 2725 */ MCD_OPC_CheckField, 8, 8, 0, 177, 22, // Skip to: 8540 +/* 2731 */ MCD_OPC_Decode, 236, 12, 76, // Opcode: LXDBR +/* 2735 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2749 +/* 2739 */ MCD_OPC_CheckField, 8, 8, 0, 163, 22, // Skip to: 8540 +/* 2745 */ MCD_OPC_Decode, 241, 12, 77, // Opcode: LXEBR +/* 2749 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2763 +/* 2753 */ MCD_OPC_CheckField, 8, 8, 0, 149, 22, // Skip to: 8540 +/* 2759 */ MCD_OPC_Decode, 215, 13, 14, // Opcode: MXDBR +/* 2763 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 2777 +/* 2767 */ MCD_OPC_CheckField, 8, 8, 0, 135, 22, // Skip to: 8540 +/* 2773 */ MCD_OPC_Decode, 224, 9, 16, // Opcode: KEBR +/* 2777 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2791 +/* 2781 */ MCD_OPC_CheckField, 8, 8, 0, 121, 22, // Skip to: 8540 +/* 2787 */ MCD_OPC_Decode, 166, 4, 16, // Opcode: CEBR +/* 2791 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 2805 +/* 2795 */ MCD_OPC_CheckField, 8, 8, 0, 107, 22, // Skip to: 8540 +/* 2801 */ MCD_OPC_Decode, 237, 2, 18, // Opcode: AEBR +/* 2805 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 2819 +/* 2809 */ MCD_OPC_CheckField, 8, 8, 0, 93, 22, // Skip to: 8540 +/* 2815 */ MCD_OPC_Decode, 198, 14, 18, // Opcode: SEBR +/* 2819 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 2833 +/* 2823 */ MCD_OPC_CheckField, 8, 8, 0, 79, 22, // Skip to: 8540 +/* 2829 */ MCD_OPC_Decode, 143, 13, 19, // Opcode: MDEBR +/* 2833 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 2847 +/* 2837 */ MCD_OPC_CheckField, 8, 8, 0, 65, 22, // Skip to: 8540 +/* 2843 */ MCD_OPC_Decode, 196, 8, 18, // Opcode: DEBR +/* 2847 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 2861 +/* 2851 */ MCD_OPC_CheckField, 8, 4, 0, 51, 22, // Skip to: 8540 +/* 2857 */ MCD_OPC_Decode, 129, 13, 78, // Opcode: MAEBR +/* 2861 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 2875 +/* 2865 */ MCD_OPC_CheckField, 8, 4, 0, 37, 22, // Skip to: 8540 +/* 2871 */ MCD_OPC_Decode, 177, 13, 78, // Opcode: MSEBR +/* 2875 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 2889 +/* 2879 */ MCD_OPC_CheckField, 8, 8, 0, 23, 22, // Skip to: 8540 +/* 2885 */ MCD_OPC_Decode, 185, 12, 11, // Opcode: LPDBR +/* 2889 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 2903 +/* 2893 */ MCD_OPC_CheckField, 8, 8, 0, 9, 22, // Skip to: 8540 +/* 2899 */ MCD_OPC_Decode, 230, 10, 11, // Opcode: LNDBR +/* 2903 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 2917 +/* 2907 */ MCD_OPC_CheckField, 8, 8, 0, 251, 21, // Skip to: 8540 +/* 2913 */ MCD_OPC_Decode, 216, 12, 11, // Opcode: LTDBR +/* 2917 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 2931 +/* 2921 */ MCD_OPC_CheckField, 8, 8, 0, 237, 21, // Skip to: 8540 +/* 2927 */ MCD_OPC_Decode, 133, 10, 11, // Opcode: LCDBR +/* 2931 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 2945 +/* 2935 */ MCD_OPC_CheckField, 8, 8, 0, 223, 21, // Skip to: 8540 +/* 2941 */ MCD_OPC_Decode, 254, 14, 16, // Opcode: SQEBR +/* 2945 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 2959 +/* 2949 */ MCD_OPC_CheckField, 8, 8, 0, 209, 21, // Skip to: 8540 +/* 2955 */ MCD_OPC_Decode, 250, 14, 11, // Opcode: SQDBR +/* 2959 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 2973 +/* 2963 */ MCD_OPC_CheckField, 8, 8, 0, 195, 21, // Skip to: 8540 +/* 2969 */ MCD_OPC_Decode, 128, 15, 79, // Opcode: SQXBR +/* 2973 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 2987 +/* 2977 */ MCD_OPC_CheckField, 8, 8, 0, 181, 21, // Skip to: 8540 +/* 2983 */ MCD_OPC_Decode, 151, 13, 18, // Opcode: MEEBR +/* 2987 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 3001 +/* 2991 */ MCD_OPC_CheckField, 8, 8, 0, 167, 21, // Skip to: 8540 +/* 2997 */ MCD_OPC_Decode, 221, 9, 11, // Opcode: KDBR +/* 3001 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 3015 +/* 3005 */ MCD_OPC_CheckField, 8, 8, 0, 153, 21, // Skip to: 8540 +/* 3011 */ MCD_OPC_Decode, 141, 4, 11, // Opcode: CDBR +/* 3015 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 3029 +/* 3019 */ MCD_OPC_CheckField, 8, 8, 0, 139, 21, // Skip to: 8540 +/* 3025 */ MCD_OPC_Decode, 231, 2, 15, // Opcode: ADBR +/* 3029 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 3043 +/* 3033 */ MCD_OPC_CheckField, 8, 8, 0, 125, 21, // Skip to: 8540 +/* 3039 */ MCD_OPC_Decode, 192, 14, 15, // Opcode: SDBR +/* 3043 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 3057 +/* 3047 */ MCD_OPC_CheckField, 8, 8, 0, 111, 21, // Skip to: 8540 +/* 3053 */ MCD_OPC_Decode, 140, 13, 15, // Opcode: MDBR +/* 3057 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 3071 +/* 3061 */ MCD_OPC_CheckField, 8, 8, 0, 97, 21, // Skip to: 8540 +/* 3067 */ MCD_OPC_Decode, 190, 8, 15, // Opcode: DDBR +/* 3071 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 3085 +/* 3075 */ MCD_OPC_CheckField, 8, 4, 0, 83, 21, // Skip to: 8540 +/* 3081 */ MCD_OPC_Decode, 253, 12, 80, // Opcode: MADBR +/* 3085 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 3099 +/* 3089 */ MCD_OPC_CheckField, 8, 4, 0, 69, 21, // Skip to: 8540 +/* 3095 */ MCD_OPC_Decode, 173, 13, 80, // Opcode: MSDBR +/* 3099 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 3113 +/* 3103 */ MCD_OPC_CheckField, 8, 8, 0, 55, 21, // Skip to: 8540 +/* 3109 */ MCD_OPC_Decode, 151, 10, 75, // Opcode: LDER +/* 3113 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 3127 +/* 3117 */ MCD_OPC_CheckField, 8, 8, 0, 41, 21, // Skip to: 8540 +/* 3123 */ MCD_OPC_Decode, 237, 12, 76, // Opcode: LXDR +/* 3127 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 3141 +/* 3131 */ MCD_OPC_CheckField, 8, 8, 0, 27, 21, // Skip to: 8540 +/* 3137 */ MCD_OPC_Decode, 242, 12, 77, // Opcode: LXER +/* 3141 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 3155 +/* 3145 */ MCD_OPC_CheckField, 8, 4, 0, 13, 21, // Skip to: 8540 +/* 3151 */ MCD_OPC_Decode, 130, 13, 78, // Opcode: MAER +/* 3155 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 3169 +/* 3159 */ MCD_OPC_CheckField, 8, 4, 0, 255, 20, // Skip to: 8540 +/* 3165 */ MCD_OPC_Decode, 178, 13, 78, // Opcode: MSER +/* 3169 */ MCD_OPC_FilterValue, 54, 10, 0, // Skip to: 3183 +/* 3173 */ MCD_OPC_CheckField, 8, 8, 0, 241, 20, // Skip to: 8540 +/* 3179 */ MCD_OPC_Decode, 129, 15, 79, // Opcode: SQXR +/* 3183 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 3197 +/* 3187 */ MCD_OPC_CheckField, 8, 8, 0, 227, 20, // Skip to: 8540 +/* 3193 */ MCD_OPC_Decode, 152, 13, 18, // Opcode: MEER +/* 3197 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 3211 +/* 3201 */ MCD_OPC_CheckField, 8, 4, 0, 213, 20, // Skip to: 8540 +/* 3207 */ MCD_OPC_Decode, 135, 13, 80, // Opcode: MAYLR +/* 3211 */ MCD_OPC_FilterValue, 57, 10, 0, // Skip to: 3225 +/* 3215 */ MCD_OPC_CheckField, 8, 4, 0, 199, 20, // Skip to: 8540 +/* 3221 */ MCD_OPC_Decode, 224, 13, 81, // Opcode: MYLR +/* 3225 */ MCD_OPC_FilterValue, 58, 10, 0, // Skip to: 3239 +/* 3229 */ MCD_OPC_CheckField, 8, 4, 0, 185, 20, // Skip to: 8540 +/* 3235 */ MCD_OPC_Decode, 136, 13, 82, // Opcode: MAYR +/* 3239 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 3253 +/* 3243 */ MCD_OPC_CheckField, 8, 4, 0, 171, 20, // Skip to: 8540 +/* 3249 */ MCD_OPC_Decode, 225, 13, 83, // Opcode: MYR +/* 3253 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 3267 +/* 3257 */ MCD_OPC_CheckField, 8, 4, 0, 157, 20, // Skip to: 8540 +/* 3263 */ MCD_OPC_Decode, 133, 13, 80, // Opcode: MAYHR +/* 3267 */ MCD_OPC_FilterValue, 61, 10, 0, // Skip to: 3281 +/* 3271 */ MCD_OPC_CheckField, 8, 4, 0, 143, 20, // Skip to: 8540 +/* 3277 */ MCD_OPC_Decode, 222, 13, 81, // Opcode: MYHR +/* 3281 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 3295 +/* 3285 */ MCD_OPC_CheckField, 8, 4, 0, 129, 20, // Skip to: 8540 +/* 3291 */ MCD_OPC_Decode, 254, 12, 80, // Opcode: MADR +/* 3295 */ MCD_OPC_FilterValue, 63, 10, 0, // Skip to: 3309 +/* 3299 */ MCD_OPC_CheckField, 8, 4, 0, 115, 20, // Skip to: 8540 +/* 3305 */ MCD_OPC_Decode, 174, 13, 80, // Opcode: MSDR +/* 3309 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 3323 +/* 3313 */ MCD_OPC_CheckField, 8, 8, 0, 101, 20, // Skip to: 8540 +/* 3319 */ MCD_OPC_Decode, 200, 12, 79, // Opcode: LPXBR +/* 3323 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 3337 +/* 3327 */ MCD_OPC_CheckField, 8, 8, 0, 87, 20, // Skip to: 8540 +/* 3333 */ MCD_OPC_Decode, 239, 10, 79, // Opcode: LNXBR +/* 3337 */ MCD_OPC_FilterValue, 66, 10, 0, // Skip to: 3351 +/* 3341 */ MCD_OPC_CheckField, 8, 8, 0, 73, 20, // Skip to: 8540 +/* 3347 */ MCD_OPC_Decode, 228, 12, 79, // Opcode: LTXBR +/* 3351 */ MCD_OPC_FilterValue, 67, 10, 0, // Skip to: 3365 +/* 3355 */ MCD_OPC_CheckField, 8, 8, 0, 59, 20, // Skip to: 8540 +/* 3361 */ MCD_OPC_Decode, 144, 10, 79, // Opcode: LCXBR +/* 3365 */ MCD_OPC_FilterValue, 68, 18, 0, // Skip to: 3387 +/* 3369 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3379 +/* 3375 */ MCD_OPC_Decode, 162, 10, 17, // Opcode: LEDBR +/* 3379 */ MCD_OPC_CheckPredicate, 0, 37, 20, // Skip to: 8540 +/* 3383 */ MCD_OPC_Decode, 163, 10, 84, // Opcode: LEDBRA +/* 3387 */ MCD_OPC_FilterValue, 69, 18, 0, // Skip to: 3409 +/* 3391 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3401 +/* 3397 */ MCD_OPC_Decode, 156, 10, 79, // Opcode: LDXBR +/* 3401 */ MCD_OPC_CheckPredicate, 0, 15, 20, // Skip to: 8540 +/* 3405 */ MCD_OPC_Decode, 157, 10, 85, // Opcode: LDXBRA +/* 3409 */ MCD_OPC_FilterValue, 70, 18, 0, // Skip to: 3431 +/* 3413 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3423 +/* 3419 */ MCD_OPC_Decode, 167, 10, 79, // Opcode: LEXBR +/* 3423 */ MCD_OPC_CheckPredicate, 0, 249, 19, // Skip to: 8540 +/* 3427 */ MCD_OPC_Decode, 168, 10, 85, // Opcode: LEXBRA +/* 3431 */ MCD_OPC_FilterValue, 71, 18, 0, // Skip to: 3453 +/* 3435 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3445 +/* 3441 */ MCD_OPC_Decode, 247, 8, 86, // Opcode: FIXBR +/* 3445 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 8540 +/* 3449 */ MCD_OPC_Decode, 248, 8, 85, // Opcode: FIXBRA +/* 3453 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 3467 +/* 3457 */ MCD_OPC_CheckField, 8, 8, 0, 213, 19, // Skip to: 8540 +/* 3463 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: KXBR +/* 3467 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 3481 +/* 3471 */ MCD_OPC_CheckField, 8, 8, 0, 199, 19, // Skip to: 8540 +/* 3477 */ MCD_OPC_Decode, 164, 8, 79, // Opcode: CXBR +/* 3481 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 3495 +/* 3485 */ MCD_OPC_CheckField, 8, 8, 0, 185, 19, // Skip to: 8540 +/* 3491 */ MCD_OPC_Decode, 160, 3, 13, // Opcode: AXBR +/* 3495 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 3509 +/* 3499 */ MCD_OPC_CheckField, 8, 8, 0, 171, 19, // Skip to: 8540 +/* 3505 */ MCD_OPC_Decode, 150, 16, 13, // Opcode: SXBR +/* 3509 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 3523 +/* 3513 */ MCD_OPC_CheckField, 8, 8, 0, 157, 19, // Skip to: 8540 +/* 3519 */ MCD_OPC_Decode, 212, 13, 13, // Opcode: MXBR +/* 3523 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 3537 +/* 3527 */ MCD_OPC_CheckField, 8, 8, 0, 143, 19, // Skip to: 8540 +/* 3533 */ MCD_OPC_Decode, 211, 8, 13, // Opcode: DXBR +/* 3537 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 3551 +/* 3541 */ MCD_OPC_CheckField, 8, 4, 0, 129, 19, // Skip to: 8540 +/* 3547 */ MCD_OPC_Decode, 160, 16, 87, // Opcode: TBEDR +/* 3551 */ MCD_OPC_FilterValue, 81, 10, 0, // Skip to: 3565 +/* 3555 */ MCD_OPC_CheckField, 8, 4, 0, 115, 19, // Skip to: 8540 +/* 3561 */ MCD_OPC_Decode, 159, 16, 88, // Opcode: TBDR +/* 3565 */ MCD_OPC_FilterValue, 83, 4, 0, // Skip to: 3573 +/* 3569 */ MCD_OPC_Decode, 200, 8, 89, // Opcode: DIEBR +/* 3573 */ MCD_OPC_FilterValue, 87, 18, 0, // Skip to: 3595 +/* 3577 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3587 +/* 3583 */ MCD_OPC_Decode, 244, 8, 90, // Opcode: FIEBR +/* 3587 */ MCD_OPC_CheckPredicate, 0, 85, 19, // Skip to: 8540 +/* 3591 */ MCD_OPC_Decode, 245, 8, 91, // Opcode: FIEBRA +/* 3595 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 3609 +/* 3599 */ MCD_OPC_CheckField, 8, 8, 0, 71, 19, // Skip to: 8540 +/* 3605 */ MCD_OPC_Decode, 173, 16, 75, // Opcode: THDER +/* 3609 */ MCD_OPC_FilterValue, 89, 10, 0, // Skip to: 3623 +/* 3613 */ MCD_OPC_CheckField, 8, 8, 0, 57, 19, // Skip to: 8540 +/* 3619 */ MCD_OPC_Decode, 174, 16, 11, // Opcode: THDR +/* 3623 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 3631 +/* 3627 */ MCD_OPC_Decode, 199, 8, 92, // Opcode: DIDBR +/* 3631 */ MCD_OPC_FilterValue, 95, 18, 0, // Skip to: 3653 +/* 3635 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3645 +/* 3641 */ MCD_OPC_Decode, 240, 8, 88, // Opcode: FIDBR +/* 3645 */ MCD_OPC_CheckPredicate, 0, 27, 19, // Skip to: 8540 +/* 3649 */ MCD_OPC_Decode, 241, 8, 93, // Opcode: FIDBRA +/* 3653 */ MCD_OPC_FilterValue, 96, 10, 0, // Skip to: 3667 +/* 3657 */ MCD_OPC_CheckField, 8, 8, 0, 13, 19, // Skip to: 8540 +/* 3663 */ MCD_OPC_Decode, 201, 12, 79, // Opcode: LPXR +/* 3667 */ MCD_OPC_FilterValue, 97, 10, 0, // Skip to: 3681 +/* 3671 */ MCD_OPC_CheckField, 8, 8, 0, 255, 18, // Skip to: 8540 +/* 3677 */ MCD_OPC_Decode, 240, 10, 79, // Opcode: LNXR +/* 3681 */ MCD_OPC_FilterValue, 98, 10, 0, // Skip to: 3695 +/* 3685 */ MCD_OPC_CheckField, 8, 8, 0, 241, 18, // Skip to: 8540 +/* 3691 */ MCD_OPC_Decode, 230, 12, 79, // Opcode: LTXR +/* 3695 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 3709 +/* 3699 */ MCD_OPC_CheckField, 8, 8, 0, 227, 18, // Skip to: 8540 +/* 3705 */ MCD_OPC_Decode, 145, 10, 79, // Opcode: LCXR +/* 3709 */ MCD_OPC_FilterValue, 101, 10, 0, // Skip to: 3723 +/* 3713 */ MCD_OPC_CheckField, 8, 8, 0, 213, 18, // Skip to: 8540 +/* 3719 */ MCD_OPC_Decode, 243, 12, 79, // Opcode: LXR +/* 3723 */ MCD_OPC_FilterValue, 102, 10, 0, // Skip to: 3737 +/* 3727 */ MCD_OPC_CheckField, 8, 8, 0, 199, 18, // Skip to: 8540 +/* 3733 */ MCD_OPC_Decode, 169, 10, 94, // Opcode: LEXR +/* 3737 */ MCD_OPC_FilterValue, 103, 10, 0, // Skip to: 3751 +/* 3741 */ MCD_OPC_CheckField, 8, 8, 0, 185, 18, // Skip to: 8540 +/* 3747 */ MCD_OPC_Decode, 249, 8, 79, // Opcode: FIXR +/* 3751 */ MCD_OPC_FilterValue, 105, 10, 0, // Skip to: 3765 +/* 3755 */ MCD_OPC_CheckField, 8, 8, 0, 171, 18, // Skip to: 8540 +/* 3761 */ MCD_OPC_Decode, 179, 8, 79, // Opcode: CXR +/* 3765 */ MCD_OPC_FilterValue, 112, 10, 0, // Skip to: 3779 +/* 3769 */ MCD_OPC_CheckField, 8, 8, 0, 157, 18, // Skip to: 8540 +/* 3775 */ MCD_OPC_Decode, 186, 12, 11, // Opcode: LPDFR +/* 3779 */ MCD_OPC_FilterValue, 113, 10, 0, // Skip to: 3793 +/* 3783 */ MCD_OPC_CheckField, 8, 8, 0, 143, 18, // Skip to: 8540 +/* 3789 */ MCD_OPC_Decode, 231, 10, 11, // Opcode: LNDFR +/* 3793 */ MCD_OPC_FilterValue, 114, 10, 0, // Skip to: 3807 +/* 3797 */ MCD_OPC_CheckField, 8, 4, 0, 129, 18, // Skip to: 8540 +/* 3803 */ MCD_OPC_Decode, 208, 7, 95, // Opcode: CPSDRdd +/* 3807 */ MCD_OPC_FilterValue, 115, 10, 0, // Skip to: 3821 +/* 3811 */ MCD_OPC_CheckField, 8, 8, 0, 115, 18, // Skip to: 8540 +/* 3817 */ MCD_OPC_Decode, 134, 10, 11, // Opcode: LCDFR +/* 3821 */ MCD_OPC_FilterValue, 116, 16, 0, // Skip to: 3841 +/* 3825 */ MCD_OPC_CheckField, 8, 8, 0, 101, 18, // Skip to: 8540 +/* 3831 */ MCD_OPC_CheckField, 0, 4, 0, 95, 18, // Skip to: 8540 +/* 3837 */ MCD_OPC_Decode, 246, 12, 96, // Opcode: LZER +/* 3841 */ MCD_OPC_FilterValue, 117, 16, 0, // Skip to: 3861 +/* 3845 */ MCD_OPC_CheckField, 8, 8, 0, 81, 18, // Skip to: 8540 +/* 3851 */ MCD_OPC_CheckField, 0, 4, 0, 75, 18, // Skip to: 8540 +/* 3857 */ MCD_OPC_Decode, 245, 12, 97, // Opcode: LZDR +/* 3861 */ MCD_OPC_FilterValue, 118, 16, 0, // Skip to: 3881 +/* 3865 */ MCD_OPC_CheckField, 8, 8, 0, 61, 18, // Skip to: 8540 +/* 3871 */ MCD_OPC_CheckField, 0, 4, 0, 55, 18, // Skip to: 8540 +/* 3877 */ MCD_OPC_Decode, 249, 12, 98, // Opcode: LZXR +/* 3881 */ MCD_OPC_FilterValue, 119, 10, 0, // Skip to: 3895 +/* 3885 */ MCD_OPC_CheckField, 8, 8, 0, 41, 18, // Skip to: 8540 +/* 3891 */ MCD_OPC_Decode, 246, 8, 16, // Opcode: FIER +/* 3895 */ MCD_OPC_FilterValue, 127, 10, 0, // Skip to: 3909 +/* 3899 */ MCD_OPC_CheckField, 8, 8, 0, 27, 18, // Skip to: 8540 +/* 3905 */ MCD_OPC_Decode, 242, 8, 11, // Opcode: FIDR +/* 3909 */ MCD_OPC_FilterValue, 132, 1, 16, 0, // Skip to: 3930 +/* 3914 */ MCD_OPC_CheckField, 8, 8, 0, 12, 18, // Skip to: 8540 +/* 3920 */ MCD_OPC_CheckField, 0, 4, 0, 6, 18, // Skip to: 8540 +/* 3926 */ MCD_OPC_Decode, 201, 14, 1, // Opcode: SFPC +/* 3930 */ MCD_OPC_FilterValue, 133, 1, 16, 0, // Skip to: 3951 +/* 3935 */ MCD_OPC_CheckField, 8, 8, 0, 247, 17, // Skip to: 8540 +/* 3941 */ MCD_OPC_CheckField, 0, 4, 0, 241, 17, // Skip to: 8540 +/* 3947 */ MCD_OPC_Decode, 200, 14, 1, // Opcode: SFASR +/* 3951 */ MCD_OPC_FilterValue, 140, 1, 16, 0, // Skip to: 3972 +/* 3956 */ MCD_OPC_CheckField, 8, 8, 0, 226, 17, // Skip to: 8540 +/* 3962 */ MCD_OPC_CheckField, 0, 4, 0, 220, 17, // Skip to: 8540 +/* 3968 */ MCD_OPC_Decode, 224, 8, 1, // Opcode: EFPC +/* 3972 */ MCD_OPC_FilterValue, 144, 1, 8, 0, // Skip to: 3985 +/* 3977 */ MCD_OPC_CheckPredicate, 0, 207, 17, // Skip to: 8540 +/* 3981 */ MCD_OPC_Decode, 174, 4, 99, // Opcode: CELFBR +/* 3985 */ MCD_OPC_FilterValue, 145, 1, 8, 0, // Skip to: 3998 +/* 3990 */ MCD_OPC_CheckPredicate, 0, 194, 17, // Skip to: 8540 +/* 3994 */ MCD_OPC_Decode, 151, 4, 100, // Opcode: CDLFBR +/* 3998 */ MCD_OPC_FilterValue, 146, 1, 8, 0, // Skip to: 4011 +/* 4003 */ MCD_OPC_CheckPredicate, 0, 181, 17, // Skip to: 8540 +/* 4007 */ MCD_OPC_Decode, 174, 8, 101, // Opcode: CXLFBR +/* 4011 */ MCD_OPC_FilterValue, 148, 1, 18, 0, // Skip to: 4034 +/* 4016 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4026 +/* 4022 */ MCD_OPC_Decode, 168, 4, 102, // Opcode: CEFBR +/* 4026 */ MCD_OPC_CheckPredicate, 0, 158, 17, // Skip to: 8540 +/* 4030 */ MCD_OPC_Decode, 169, 4, 99, // Opcode: CEFBRA +/* 4034 */ MCD_OPC_FilterValue, 149, 1, 18, 0, // Skip to: 4057 +/* 4039 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4049 +/* 4045 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: CDFBR +/* 4049 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 8540 +/* 4053 */ MCD_OPC_Decode, 143, 4, 100, // Opcode: CDFBRA +/* 4057 */ MCD_OPC_FilterValue, 150, 1, 18, 0, // Skip to: 4080 +/* 4062 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4072 +/* 4068 */ MCD_OPC_Decode, 165, 8, 104, // Opcode: CXFBR +/* 4072 */ MCD_OPC_CheckPredicate, 0, 112, 17, // Skip to: 8540 +/* 4076 */ MCD_OPC_Decode, 166, 8, 101, // Opcode: CXFBRA +/* 4080 */ MCD_OPC_FilterValue, 152, 1, 18, 0, // Skip to: 4103 +/* 4085 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4095 +/* 4091 */ MCD_OPC_Decode, 183, 4, 105, // Opcode: CFEBR +/* 4095 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 8540 +/* 4099 */ MCD_OPC_Decode, 184, 4, 106, // Opcode: CFEBRA +/* 4103 */ MCD_OPC_FilterValue, 153, 1, 18, 0, // Skip to: 4126 +/* 4108 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4118 +/* 4114 */ MCD_OPC_Decode, 179, 4, 107, // Opcode: CFDBR +/* 4118 */ MCD_OPC_CheckPredicate, 0, 66, 17, // Skip to: 8540 +/* 4122 */ MCD_OPC_Decode, 180, 4, 108, // Opcode: CFDBRA +/* 4126 */ MCD_OPC_FilterValue, 154, 1, 18, 0, // Skip to: 4149 +/* 4131 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4141 +/* 4137 */ MCD_OPC_Decode, 187, 4, 109, // Opcode: CFXBR +/* 4141 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 8540 +/* 4145 */ MCD_OPC_Decode, 188, 4, 110, // Opcode: CFXBRA +/* 4149 */ MCD_OPC_FilterValue, 156, 1, 8, 0, // Skip to: 4162 +/* 4154 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 8540 +/* 4158 */ MCD_OPC_Decode, 231, 5, 106, // Opcode: CLFEBR +/* 4162 */ MCD_OPC_FilterValue, 157, 1, 8, 0, // Skip to: 4175 +/* 4167 */ MCD_OPC_CheckPredicate, 0, 17, 17, // Skip to: 8540 +/* 4171 */ MCD_OPC_Decode, 229, 5, 108, // Opcode: CLFDBR +/* 4175 */ MCD_OPC_FilterValue, 158, 1, 8, 0, // Skip to: 4188 +/* 4180 */ MCD_OPC_CheckPredicate, 0, 4, 17, // Skip to: 8540 +/* 4184 */ MCD_OPC_Decode, 248, 5, 110, // Opcode: CLFXBR +/* 4188 */ MCD_OPC_FilterValue, 160, 1, 8, 0, // Skip to: 4201 +/* 4193 */ MCD_OPC_CheckPredicate, 0, 247, 16, // Skip to: 8540 +/* 4197 */ MCD_OPC_Decode, 175, 4, 111, // Opcode: CELGBR +/* 4201 */ MCD_OPC_FilterValue, 161, 1, 8, 0, // Skip to: 4214 +/* 4206 */ MCD_OPC_CheckPredicate, 0, 234, 16, // Skip to: 8540 +/* 4210 */ MCD_OPC_Decode, 153, 4, 112, // Opcode: CDLGBR +/* 4214 */ MCD_OPC_FilterValue, 162, 1, 8, 0, // Skip to: 4227 +/* 4219 */ MCD_OPC_CheckPredicate, 0, 221, 16, // Skip to: 8540 +/* 4223 */ MCD_OPC_Decode, 176, 8, 113, // Opcode: CXLGBR +/* 4227 */ MCD_OPC_FilterValue, 164, 1, 18, 0, // Skip to: 4250 +/* 4232 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4242 +/* 4238 */ MCD_OPC_Decode, 171, 4, 114, // Opcode: CEGBR +/* 4242 */ MCD_OPC_CheckPredicate, 0, 198, 16, // Skip to: 8540 +/* 4246 */ MCD_OPC_Decode, 172, 4, 111, // Opcode: CEGBRA +/* 4250 */ MCD_OPC_FilterValue, 165, 1, 18, 0, // Skip to: 4273 +/* 4255 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4265 +/* 4261 */ MCD_OPC_Decode, 146, 4, 115, // Opcode: CDGBR +/* 4265 */ MCD_OPC_CheckPredicate, 0, 175, 16, // Skip to: 8540 +/* 4269 */ MCD_OPC_Decode, 147, 4, 112, // Opcode: CDGBRA +/* 4273 */ MCD_OPC_FilterValue, 166, 1, 18, 0, // Skip to: 4296 +/* 4278 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4288 +/* 4284 */ MCD_OPC_Decode, 169, 8, 116, // Opcode: CXGBR +/* 4288 */ MCD_OPC_CheckPredicate, 0, 152, 16, // Skip to: 8540 +/* 4292 */ MCD_OPC_Decode, 170, 8, 113, // Opcode: CXGBRA +/* 4296 */ MCD_OPC_FilterValue, 168, 1, 18, 0, // Skip to: 4319 +/* 4301 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4311 +/* 4307 */ MCD_OPC_Decode, 197, 4, 117, // Opcode: CGEBR +/* 4311 */ MCD_OPC_CheckPredicate, 0, 129, 16, // Skip to: 8540 +/* 4315 */ MCD_OPC_Decode, 198, 4, 118, // Opcode: CGEBRA +/* 4319 */ MCD_OPC_FilterValue, 169, 1, 18, 0, // Skip to: 4342 +/* 4324 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4334 +/* 4330 */ MCD_OPC_Decode, 192, 4, 119, // Opcode: CGDBR +/* 4334 */ MCD_OPC_CheckPredicate, 0, 106, 16, // Skip to: 8540 +/* 4338 */ MCD_OPC_Decode, 193, 4, 120, // Opcode: CGDBRA +/* 4342 */ MCD_OPC_FilterValue, 170, 1, 18, 0, // Skip to: 4365 +/* 4347 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4357 +/* 4353 */ MCD_OPC_Decode, 166, 5, 121, // Opcode: CGXBR +/* 4357 */ MCD_OPC_CheckPredicate, 0, 83, 16, // Skip to: 8540 +/* 4361 */ MCD_OPC_Decode, 167, 5, 122, // Opcode: CGXBRA +/* 4365 */ MCD_OPC_FilterValue, 172, 1, 8, 0, // Skip to: 4378 +/* 4370 */ MCD_OPC_CheckPredicate, 0, 70, 16, // Skip to: 8540 +/* 4374 */ MCD_OPC_Decode, 253, 5, 118, // Opcode: CLGEBR +/* 4378 */ MCD_OPC_FilterValue, 173, 1, 8, 0, // Skip to: 4391 +/* 4383 */ MCD_OPC_CheckPredicate, 0, 57, 16, // Skip to: 8540 +/* 4387 */ MCD_OPC_Decode, 251, 5, 120, // Opcode: CLGDBR +/* 4391 */ MCD_OPC_FilterValue, 174, 1, 8, 0, // Skip to: 4404 +/* 4396 */ MCD_OPC_CheckPredicate, 0, 44, 16, // Skip to: 8540 +/* 4400 */ MCD_OPC_Decode, 232, 6, 122, // Opcode: CLGXBR +/* 4404 */ MCD_OPC_FilterValue, 180, 1, 10, 0, // Skip to: 4419 +/* 4409 */ MCD_OPC_CheckField, 8, 8, 0, 29, 16, // Skip to: 8540 +/* 4415 */ MCD_OPC_Decode, 170, 4, 102, // Opcode: CEFR +/* 4419 */ MCD_OPC_FilterValue, 181, 1, 10, 0, // Skip to: 4434 +/* 4424 */ MCD_OPC_CheckField, 8, 8, 0, 14, 16, // Skip to: 8540 +/* 4430 */ MCD_OPC_Decode, 144, 4, 103, // Opcode: CDFR +/* 4434 */ MCD_OPC_FilterValue, 182, 1, 10, 0, // Skip to: 4449 +/* 4439 */ MCD_OPC_CheckField, 8, 8, 0, 255, 15, // Skip to: 8540 +/* 4445 */ MCD_OPC_Decode, 167, 8, 104, // Opcode: CXFR +/* 4449 */ MCD_OPC_FilterValue, 184, 1, 10, 0, // Skip to: 4464 +/* 4454 */ MCD_OPC_CheckField, 8, 4, 0, 240, 15, // Skip to: 8540 +/* 4460 */ MCD_OPC_Decode, 185, 4, 105, // Opcode: CFER +/* 4464 */ MCD_OPC_FilterValue, 185, 1, 10, 0, // Skip to: 4479 +/* 4469 */ MCD_OPC_CheckField, 8, 4, 0, 225, 15, // Skip to: 8540 +/* 4475 */ MCD_OPC_Decode, 181, 4, 107, // Opcode: CFDR +/* 4479 */ MCD_OPC_FilterValue, 186, 1, 10, 0, // Skip to: 4494 +/* 4484 */ MCD_OPC_CheckField, 8, 4, 0, 210, 15, // Skip to: 8540 +/* 4490 */ MCD_OPC_Decode, 189, 4, 109, // Opcode: CFXR +/* 4494 */ MCD_OPC_FilterValue, 193, 1, 10, 0, // Skip to: 4509 +/* 4499 */ MCD_OPC_CheckField, 8, 8, 0, 195, 15, // Skip to: 8540 +/* 4505 */ MCD_OPC_Decode, 153, 10, 115, // Opcode: LDGR +/* 4509 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 4524 +/* 4514 */ MCD_OPC_CheckField, 8, 8, 0, 180, 15, // Skip to: 8540 +/* 4520 */ MCD_OPC_Decode, 173, 4, 114, // Opcode: CEGR +/* 4524 */ MCD_OPC_FilterValue, 197, 1, 10, 0, // Skip to: 4539 +/* 4529 */ MCD_OPC_CheckField, 8, 8, 0, 165, 15, // Skip to: 8540 +/* 4535 */ MCD_OPC_Decode, 148, 4, 115, // Opcode: CDGR +/* 4539 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 4554 +/* 4544 */ MCD_OPC_CheckField, 8, 8, 0, 150, 15, // Skip to: 8540 +/* 4550 */ MCD_OPC_Decode, 171, 8, 116, // Opcode: CXGR +/* 4554 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 4569 +/* 4559 */ MCD_OPC_CheckField, 8, 4, 0, 135, 15, // Skip to: 8540 +/* 4565 */ MCD_OPC_Decode, 199, 4, 117, // Opcode: CGER +/* 4569 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 4584 +/* 4574 */ MCD_OPC_CheckField, 8, 4, 0, 120, 15, // Skip to: 8540 +/* 4580 */ MCD_OPC_Decode, 194, 4, 119, // Opcode: CGDR +/* 4584 */ MCD_OPC_FilterValue, 202, 1, 10, 0, // Skip to: 4599 +/* 4589 */ MCD_OPC_CheckField, 8, 4, 0, 105, 15, // Skip to: 8540 +/* 4595 */ MCD_OPC_Decode, 168, 5, 121, // Opcode: CGXR +/* 4599 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 4614 +/* 4604 */ MCD_OPC_CheckField, 8, 8, 0, 90, 15, // Skip to: 8540 +/* 4610 */ MCD_OPC_Decode, 179, 10, 123, // Opcode: LGDR +/* 4614 */ MCD_OPC_FilterValue, 208, 1, 18, 0, // Skip to: 4637 +/* 4619 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4629 +/* 4625 */ MCD_OPC_Decode, 146, 13, 95, // Opcode: MDTR +/* 4629 */ MCD_OPC_CheckPredicate, 0, 67, 15, // Skip to: 8540 +/* 4633 */ MCD_OPC_Decode, 147, 13, 124, // Opcode: MDTRA +/* 4637 */ MCD_OPC_FilterValue, 209, 1, 18, 0, // Skip to: 4660 +/* 4642 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4652 +/* 4648 */ MCD_OPC_Decode, 192, 8, 95, // Opcode: DDTR +/* 4652 */ MCD_OPC_CheckPredicate, 0, 44, 15, // Skip to: 8540 +/* 4656 */ MCD_OPC_Decode, 193, 8, 124, // Opcode: DDTRA +/* 4660 */ MCD_OPC_FilterValue, 210, 1, 18, 0, // Skip to: 4683 +/* 4665 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4675 +/* 4671 */ MCD_OPC_Decode, 233, 2, 95, // Opcode: ADTR +/* 4675 */ MCD_OPC_CheckPredicate, 0, 21, 15, // Skip to: 8540 +/* 4679 */ MCD_OPC_Decode, 234, 2, 124, // Opcode: ADTRA +/* 4683 */ MCD_OPC_FilterValue, 211, 1, 18, 0, // Skip to: 4706 +/* 4688 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4698 +/* 4694 */ MCD_OPC_Decode, 194, 14, 95, // Opcode: SDTR +/* 4698 */ MCD_OPC_CheckPredicate, 0, 254, 14, // Skip to: 8540 +/* 4702 */ MCD_OPC_Decode, 195, 14, 124, // Opcode: SDTRA +/* 4706 */ MCD_OPC_FilterValue, 212, 1, 10, 0, // Skip to: 4721 +/* 4711 */ MCD_OPC_CheckField, 12, 4, 0, 239, 14, // Skip to: 8540 +/* 4717 */ MCD_OPC_Decode, 152, 10, 125, // Opcode: LDETR +/* 4721 */ MCD_OPC_FilterValue, 213, 1, 4, 0, // Skip to: 4730 +/* 4726 */ MCD_OPC_Decode, 165, 10, 84, // Opcode: LEDTR +/* 4730 */ MCD_OPC_FilterValue, 214, 1, 10, 0, // Skip to: 4745 +/* 4735 */ MCD_OPC_CheckField, 8, 8, 0, 215, 14, // Skip to: 8540 +/* 4741 */ MCD_OPC_Decode, 219, 12, 11, // Opcode: LTDTR +/* 4745 */ MCD_OPC_FilterValue, 215, 1, 4, 0, // Skip to: 4754 +/* 4750 */ MCD_OPC_Decode, 243, 8, 93, // Opcode: FIDTR +/* 4754 */ MCD_OPC_FilterValue, 216, 1, 18, 0, // Skip to: 4777 +/* 4759 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4769 +/* 4765 */ MCD_OPC_Decode, 218, 13, 126, // Opcode: MXTR +/* 4769 */ MCD_OPC_CheckPredicate, 0, 183, 14, // Skip to: 8540 +/* 4773 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: MXTRA +/* 4777 */ MCD_OPC_FilterValue, 217, 1, 18, 0, // Skip to: 4800 +/* 4782 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4792 +/* 4788 */ MCD_OPC_Decode, 213, 8, 126, // Opcode: DXTR +/* 4792 */ MCD_OPC_CheckPredicate, 0, 160, 14, // Skip to: 8540 +/* 4796 */ MCD_OPC_Decode, 214, 8, 127, // Opcode: DXTRA +/* 4800 */ MCD_OPC_FilterValue, 218, 1, 18, 0, // Skip to: 4823 +/* 4805 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4815 +/* 4811 */ MCD_OPC_Decode, 162, 3, 126, // Opcode: AXTR +/* 4815 */ MCD_OPC_CheckPredicate, 0, 137, 14, // Skip to: 8540 +/* 4819 */ MCD_OPC_Decode, 163, 3, 127, // Opcode: AXTRA +/* 4823 */ MCD_OPC_FilterValue, 219, 1, 18, 0, // Skip to: 4846 +/* 4828 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4838 +/* 4834 */ MCD_OPC_Decode, 152, 16, 126, // Opcode: SXTR +/* 4838 */ MCD_OPC_CheckPredicate, 0, 114, 14, // Skip to: 8540 +/* 4842 */ MCD_OPC_Decode, 153, 16, 127, // Opcode: SXTRA +/* 4846 */ MCD_OPC_FilterValue, 220, 1, 11, 0, // Skip to: 4862 +/* 4851 */ MCD_OPC_CheckField, 12, 4, 0, 99, 14, // Skip to: 8540 +/* 4857 */ MCD_OPC_Decode, 238, 12, 128, 1, // Opcode: LXDTR +/* 4862 */ MCD_OPC_FilterValue, 221, 1, 4, 0, // Skip to: 4871 +/* 4867 */ MCD_OPC_Decode, 159, 10, 85, // Opcode: LDXTR +/* 4871 */ MCD_OPC_FilterValue, 222, 1, 10, 0, // Skip to: 4886 +/* 4876 */ MCD_OPC_CheckField, 8, 8, 0, 74, 14, // Skip to: 8540 +/* 4882 */ MCD_OPC_Decode, 231, 12, 79, // Opcode: LTXTR +/* 4886 */ MCD_OPC_FilterValue, 223, 1, 4, 0, // Skip to: 4895 +/* 4891 */ MCD_OPC_Decode, 250, 8, 85, // Opcode: FIXTR +/* 4895 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 4910 +/* 4900 */ MCD_OPC_CheckField, 8, 8, 0, 50, 14, // Skip to: 8540 +/* 4906 */ MCD_OPC_Decode, 222, 9, 11, // Opcode: KDTR +/* 4910 */ MCD_OPC_FilterValue, 225, 1, 18, 0, // Skip to: 4933 +/* 4915 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4925 +/* 4921 */ MCD_OPC_Decode, 195, 4, 119, // Opcode: CGDTR +/* 4925 */ MCD_OPC_CheckPredicate, 0, 27, 14, // Skip to: 8540 +/* 4929 */ MCD_OPC_Decode, 196, 4, 120, // Opcode: CGDTRA +/* 4933 */ MCD_OPC_FilterValue, 226, 1, 10, 0, // Skip to: 4948 +/* 4938 */ MCD_OPC_CheckField, 8, 8, 0, 12, 14, // Skip to: 8540 +/* 4944 */ MCD_OPC_Decode, 151, 8, 123, // Opcode: CUDTR +/* 4948 */ MCD_OPC_FilterValue, 227, 1, 11, 0, // Skip to: 4964 +/* 4953 */ MCD_OPC_CheckField, 12, 4, 0, 253, 13, // Skip to: 8540 +/* 4959 */ MCD_OPC_Decode, 134, 8, 129, 1, // Opcode: CSDTR +/* 4964 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 4979 +/* 4969 */ MCD_OPC_CheckField, 8, 8, 0, 237, 13, // Skip to: 8540 +/* 4975 */ MCD_OPC_Decode, 161, 4, 11, // Opcode: CDTR +/* 4979 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 4994 +/* 4984 */ MCD_OPC_CheckField, 8, 8, 0, 222, 13, // Skip to: 8540 +/* 4990 */ MCD_OPC_Decode, 222, 8, 11, // Opcode: EEDTR +/* 4994 */ MCD_OPC_FilterValue, 231, 1, 10, 0, // Skip to: 5009 +/* 4999 */ MCD_OPC_CheckField, 8, 8, 0, 207, 13, // Skip to: 8540 +/* 5005 */ MCD_OPC_Decode, 233, 8, 11, // Opcode: ESDTR +/* 5009 */ MCD_OPC_FilterValue, 232, 1, 10, 0, // Skip to: 5024 +/* 5014 */ MCD_OPC_CheckField, 8, 8, 0, 192, 13, // Skip to: 8540 +/* 5020 */ MCD_OPC_Decode, 235, 9, 79, // Opcode: KXTR +/* 5024 */ MCD_OPC_FilterValue, 233, 1, 18, 0, // Skip to: 5047 +/* 5029 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 5039 +/* 5035 */ MCD_OPC_Decode, 169, 5, 121, // Opcode: CGXTR +/* 5039 */ MCD_OPC_CheckPredicate, 0, 169, 13, // Skip to: 8540 +/* 5043 */ MCD_OPC_Decode, 170, 5, 122, // Opcode: CGXTRA +/* 5047 */ MCD_OPC_FilterValue, 234, 1, 11, 0, // Skip to: 5063 +/* 5052 */ MCD_OPC_CheckField, 8, 8, 0, 154, 13, // Skip to: 8540 +/* 5058 */ MCD_OPC_Decode, 157, 8, 130, 1, // Opcode: CUXTR +/* 5063 */ MCD_OPC_FilterValue, 235, 1, 11, 0, // Skip to: 5079 +/* 5068 */ MCD_OPC_CheckField, 12, 4, 0, 138, 13, // Skip to: 8540 +/* 5074 */ MCD_OPC_Decode, 139, 8, 131, 1, // Opcode: CSXTR +/* 5079 */ MCD_OPC_FilterValue, 236, 1, 10, 0, // Skip to: 5094 +/* 5084 */ MCD_OPC_CheckField, 8, 8, 0, 122, 13, // Skip to: 8540 +/* 5090 */ MCD_OPC_Decode, 181, 8, 79, // Opcode: CXTR +/* 5094 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 5109 +/* 5099 */ MCD_OPC_CheckField, 8, 8, 0, 107, 13, // Skip to: 8540 +/* 5105 */ MCD_OPC_Decode, 223, 8, 79, // Opcode: EEXTR +/* 5109 */ MCD_OPC_FilterValue, 239, 1, 10, 0, // Skip to: 5124 +/* 5114 */ MCD_OPC_CheckField, 8, 8, 0, 92, 13, // Skip to: 8540 +/* 5120 */ MCD_OPC_Decode, 236, 8, 79, // Opcode: ESXTR +/* 5124 */ MCD_OPC_FilterValue, 241, 1, 18, 0, // Skip to: 5147 +/* 5129 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5139 +/* 5135 */ MCD_OPC_Decode, 149, 4, 115, // Opcode: CDGTR +/* 5139 */ MCD_OPC_CheckPredicate, 0, 69, 13, // Skip to: 8540 +/* 5143 */ MCD_OPC_Decode, 150, 4, 112, // Opcode: CDGTRA +/* 5147 */ MCD_OPC_FilterValue, 242, 1, 10, 0, // Skip to: 5162 +/* 5152 */ MCD_OPC_CheckField, 8, 8, 0, 54, 13, // Skip to: 8540 +/* 5158 */ MCD_OPC_Decode, 162, 4, 115, // Opcode: CDUTR +/* 5162 */ MCD_OPC_FilterValue, 243, 1, 10, 0, // Skip to: 5177 +/* 5167 */ MCD_OPC_CheckField, 8, 8, 0, 39, 13, // Skip to: 8540 +/* 5173 */ MCD_OPC_Decode, 159, 4, 115, // Opcode: CDSTR +/* 5177 */ MCD_OPC_FilterValue, 244, 1, 10, 0, // Skip to: 5192 +/* 5182 */ MCD_OPC_CheckField, 8, 8, 0, 24, 13, // Skip to: 8540 +/* 5188 */ MCD_OPC_Decode, 167, 4, 11, // Opcode: CEDTR +/* 5192 */ MCD_OPC_FilterValue, 245, 1, 4, 0, // Skip to: 5201 +/* 5197 */ MCD_OPC_Decode, 156, 14, 92, // Opcode: QADTR +/* 5201 */ MCD_OPC_FilterValue, 246, 1, 10, 0, // Skip to: 5216 +/* 5206 */ MCD_OPC_CheckField, 8, 4, 0, 0, 13, // Skip to: 8540 +/* 5212 */ MCD_OPC_Decode, 137, 9, 95, // Opcode: IEDTR +/* 5216 */ MCD_OPC_FilterValue, 247, 1, 4, 0, // Skip to: 5225 +/* 5221 */ MCD_OPC_Decode, 173, 14, 92, // Opcode: RRDTR +/* 5225 */ MCD_OPC_FilterValue, 249, 1, 18, 0, // Skip to: 5248 +/* 5230 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5240 +/* 5236 */ MCD_OPC_Decode, 172, 8, 116, // Opcode: CXGTR +/* 5240 */ MCD_OPC_CheckPredicate, 0, 224, 12, // Skip to: 8540 +/* 5244 */ MCD_OPC_Decode, 173, 8, 113, // Opcode: CXGTRA +/* 5248 */ MCD_OPC_FilterValue, 250, 1, 11, 0, // Skip to: 5264 +/* 5253 */ MCD_OPC_CheckField, 8, 8, 0, 209, 12, // Skip to: 8540 +/* 5259 */ MCD_OPC_Decode, 182, 8, 132, 1, // Opcode: CXUTR +/* 5264 */ MCD_OPC_FilterValue, 251, 1, 11, 0, // Skip to: 5280 +/* 5269 */ MCD_OPC_CheckField, 8, 8, 0, 193, 12, // Skip to: 8540 +/* 5275 */ MCD_OPC_Decode, 180, 8, 132, 1, // Opcode: CXSTR +/* 5280 */ MCD_OPC_FilterValue, 252, 1, 10, 0, // Skip to: 5295 +/* 5285 */ MCD_OPC_CheckField, 8, 8, 0, 177, 12, // Skip to: 8540 +/* 5291 */ MCD_OPC_Decode, 177, 4, 79, // Opcode: CEXTR +/* 5295 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 5305 +/* 5300 */ MCD_OPC_Decode, 157, 14, 133, 1, // Opcode: QAXTR +/* 5305 */ MCD_OPC_FilterValue, 254, 1, 10, 0, // Skip to: 5320 +/* 5310 */ MCD_OPC_CheckField, 8, 4, 0, 152, 12, // Skip to: 8540 +/* 5316 */ MCD_OPC_Decode, 138, 9, 126, // Opcode: IEXTR +/* 5320 */ MCD_OPC_FilterValue, 255, 1, 143, 12, // Skip to: 8540 +/* 5325 */ MCD_OPC_Decode, 174, 14, 133, 1, // Opcode: RRXTR +/* 5330 */ MCD_OPC_FilterValue, 182, 1, 5, 0, // Skip to: 5340 +/* 5335 */ MCD_OPC_Decode, 170, 15, 134, 1, // Opcode: STCTL +/* 5340 */ MCD_OPC_FilterValue, 183, 1, 5, 0, // Skip to: 5350 +/* 5345 */ MCD_OPC_Decode, 142, 10, 134, 1, // Opcode: LCTL +/* 5350 */ MCD_OPC_FilterValue, 185, 1, 64, 12, // Skip to: 8491 +/* 5355 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 5358 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5372 +/* 5362 */ MCD_OPC_CheckField, 8, 8, 0, 100, 12, // Skip to: 8540 +/* 5368 */ MCD_OPC_Decode, 193, 12, 61, // Opcode: LPGR +/* 5372 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 5386 +/* 5376 */ MCD_OPC_CheckField, 8, 8, 0, 86, 12, // Skip to: 8540 +/* 5382 */ MCD_OPC_Decode, 237, 10, 61, // Opcode: LNGR +/* 5386 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 5400 +/* 5390 */ MCD_OPC_CheckField, 8, 8, 0, 72, 12, // Skip to: 8540 +/* 5396 */ MCD_OPC_Decode, 226, 12, 61, // Opcode: LTGR +/* 5400 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 5414 +/* 5404 */ MCD_OPC_CheckField, 8, 8, 0, 58, 12, // Skip to: 8540 +/* 5410 */ MCD_OPC_Decode, 140, 10, 61, // Opcode: LCGR +/* 5414 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 5428 +/* 5418 */ MCD_OPC_CheckField, 8, 8, 0, 44, 12, // Skip to: 8540 +/* 5424 */ MCD_OPC_Decode, 189, 10, 61, // Opcode: LGR +/* 5428 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 5442 +/* 5432 */ MCD_OPC_CheckField, 8, 8, 0, 30, 12, // Skip to: 8540 +/* 5438 */ MCD_OPC_Decode, 233, 12, 61, // Opcode: LURAG +/* 5442 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 5456 +/* 5446 */ MCD_OPC_CheckField, 8, 8, 0, 16, 12, // Skip to: 8540 +/* 5452 */ MCD_OPC_Decode, 178, 10, 61, // Opcode: LGBR +/* 5456 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 5470 +/* 5460 */ MCD_OPC_CheckField, 8, 8, 0, 2, 12, // Skip to: 8540 +/* 5466 */ MCD_OPC_Decode, 187, 10, 61, // Opcode: LGHR +/* 5470 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 5485 +/* 5474 */ MCD_OPC_CheckField, 8, 8, 0, 244, 11, // Skip to: 8540 +/* 5480 */ MCD_OPC_Decode, 247, 2, 135, 1, // Opcode: AGR +/* 5485 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 5500 +/* 5489 */ MCD_OPC_CheckField, 8, 8, 0, 229, 11, // Skip to: 8540 +/* 5495 */ MCD_OPC_Decode, 206, 14, 135, 1, // Opcode: SGR +/* 5500 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 5515 +/* 5504 */ MCD_OPC_CheckField, 8, 8, 0, 214, 11, // Skip to: 8540 +/* 5510 */ MCD_OPC_Decode, 140, 3, 135, 1, // Opcode: ALGR +/* 5515 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 5530 +/* 5519 */ MCD_OPC_CheckField, 8, 8, 0, 199, 11, // Skip to: 8540 +/* 5525 */ MCD_OPC_Decode, 231, 14, 135, 1, // Opcode: SLGR +/* 5530 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 5545 +/* 5534 */ MCD_OPC_CheckField, 8, 8, 0, 184, 11, // Skip to: 8540 +/* 5540 */ MCD_OPC_Decode, 185, 13, 135, 1, // Opcode: MSGR +/* 5545 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 5559 +/* 5549 */ MCD_OPC_CheckField, 8, 8, 0, 169, 11, // Skip to: 8540 +/* 5555 */ MCD_OPC_Decode, 210, 8, 68, // Opcode: DSGR +/* 5559 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 5573 +/* 5563 */ MCD_OPC_CheckField, 8, 8, 0, 155, 11, // Skip to: 8540 +/* 5569 */ MCD_OPC_Decode, 230, 8, 61, // Opcode: EREGG +/* 5573 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 5587 +/* 5577 */ MCD_OPC_CheckField, 8, 8, 0, 141, 11, // Skip to: 8540 +/* 5583 */ MCD_OPC_Decode, 211, 12, 61, // Opcode: LRVGR +/* 5587 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 5601 +/* 5591 */ MCD_OPC_CheckField, 8, 8, 0, 127, 11, // Skip to: 8540 +/* 5597 */ MCD_OPC_Decode, 192, 12, 56, // Opcode: LPGFR +/* 5601 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 5615 +/* 5605 */ MCD_OPC_CheckField, 8, 8, 0, 113, 11, // Skip to: 8540 +/* 5611 */ MCD_OPC_Decode, 236, 10, 56, // Opcode: LNGFR +/* 5615 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 5629 +/* 5619 */ MCD_OPC_CheckField, 8, 8, 0, 99, 11, // Skip to: 8540 +/* 5625 */ MCD_OPC_Decode, 225, 12, 56, // Opcode: LTGFR +/* 5629 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 5643 +/* 5633 */ MCD_OPC_CheckField, 8, 8, 0, 85, 11, // Skip to: 8540 +/* 5639 */ MCD_OPC_Decode, 139, 10, 56, // Opcode: LCGFR +/* 5643 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 5657 +/* 5647 */ MCD_OPC_CheckField, 8, 8, 0, 71, 11, // Skip to: 8540 +/* 5653 */ MCD_OPC_Decode, 182, 10, 56, // Opcode: LGFR +/* 5657 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 5671 +/* 5661 */ MCD_OPC_CheckField, 8, 8, 0, 57, 11, // Skip to: 8540 +/* 5667 */ MCD_OPC_Decode, 205, 10, 56, // Opcode: LLGFR +/* 5671 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 5685 +/* 5675 */ MCD_OPC_CheckField, 8, 8, 0, 43, 11, // Skip to: 8540 +/* 5681 */ MCD_OPC_Decode, 213, 10, 61, // Opcode: LLGTR +/* 5685 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 5700 +/* 5689 */ MCD_OPC_CheckField, 8, 8, 0, 29, 11, // Skip to: 8540 +/* 5695 */ MCD_OPC_Decode, 243, 2, 136, 1, // Opcode: AGFR +/* 5700 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 5715 +/* 5704 */ MCD_OPC_CheckField, 8, 8, 0, 14, 11, // Skip to: 8540 +/* 5710 */ MCD_OPC_Decode, 204, 14, 136, 1, // Opcode: SGFR +/* 5715 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 5730 +/* 5719 */ MCD_OPC_CheckField, 8, 8, 0, 255, 10, // Skip to: 8540 +/* 5725 */ MCD_OPC_Decode, 138, 3, 136, 1, // Opcode: ALGFR +/* 5730 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 5745 +/* 5734 */ MCD_OPC_CheckField, 8, 8, 0, 240, 10, // Skip to: 8540 +/* 5740 */ MCD_OPC_Decode, 230, 14, 136, 1, // Opcode: SLGFR +/* 5745 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 5760 +/* 5749 */ MCD_OPC_CheckField, 8, 8, 0, 225, 10, // Skip to: 8540 +/* 5755 */ MCD_OPC_Decode, 184, 13, 136, 1, // Opcode: MSGFR +/* 5760 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 5774 +/* 5764 */ MCD_OPC_CheckField, 8, 8, 0, 210, 10, // Skip to: 8540 +/* 5770 */ MCD_OPC_Decode, 209, 8, 10, // Opcode: DSGFR +/* 5774 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 5789 +/* 5778 */ MCD_OPC_CheckField, 8, 8, 0, 196, 10, // Skip to: 8540 +/* 5784 */ MCD_OPC_Decode, 229, 9, 137, 1, // Opcode: KMAC +/* 5789 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 5803 +/* 5793 */ MCD_OPC_CheckField, 8, 8, 0, 181, 10, // Skip to: 8540 +/* 5799 */ MCD_OPC_Decode, 213, 12, 8, // Opcode: LRVR +/* 5803 */ MCD_OPC_FilterValue, 32, 10, 0, // Skip to: 5817 +/* 5807 */ MCD_OPC_CheckField, 8, 8, 0, 167, 10, // Skip to: 8540 +/* 5813 */ MCD_OPC_Decode, 250, 4, 61, // Opcode: CGR +/* 5817 */ MCD_OPC_FilterValue, 33, 10, 0, // Skip to: 5831 +/* 5821 */ MCD_OPC_CheckField, 8, 8, 0, 153, 10, // Skip to: 8540 +/* 5827 */ MCD_OPC_Decode, 174, 6, 61, // Opcode: CLGR +/* 5831 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 5845 +/* 5835 */ MCD_OPC_CheckField, 8, 8, 0, 139, 10, // Skip to: 8540 +/* 5841 */ MCD_OPC_Decode, 143, 16, 61, // Opcode: STURG +/* 5845 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 5859 +/* 5849 */ MCD_OPC_CheckField, 8, 8, 0, 125, 10, // Skip to: 8540 +/* 5855 */ MCD_OPC_Decode, 130, 10, 8, // Opcode: LBR +/* 5859 */ MCD_OPC_FilterValue, 39, 10, 0, // Skip to: 5873 +/* 5863 */ MCD_OPC_CheckField, 8, 8, 0, 111, 10, // Skip to: 8540 +/* 5869 */ MCD_OPC_Decode, 195, 10, 8, // Opcode: LHR +/* 5873 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 5891 +/* 5877 */ MCD_OPC_CheckPredicate, 4, 99, 10, // Skip to: 8540 +/* 5881 */ MCD_OPC_CheckField, 0, 16, 0, 93, 10, // Skip to: 8540 +/* 5887 */ MCD_OPC_Decode, 136, 14, 0, // Opcode: PCKMO +/* 5891 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 5910 +/* 5895 */ MCD_OPC_CheckPredicate, 5, 81, 10, // Skip to: 8540 +/* 5899 */ MCD_OPC_CheckField, 8, 4, 0, 75, 10, // Skip to: 8540 +/* 5905 */ MCD_OPC_Decode, 228, 9, 138, 1, // Opcode: KMA +/* 5910 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 5928 +/* 5914 */ MCD_OPC_CheckPredicate, 6, 62, 10, // Skip to: 8540 +/* 5918 */ MCD_OPC_CheckField, 8, 8, 0, 56, 10, // Skip to: 8540 +/* 5924 */ MCD_OPC_Decode, 232, 9, 7, // Opcode: KMF +/* 5928 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 5946 +/* 5932 */ MCD_OPC_CheckPredicate, 6, 44, 10, // Skip to: 8540 +/* 5936 */ MCD_OPC_CheckField, 8, 8, 0, 38, 10, // Skip to: 8540 +/* 5942 */ MCD_OPC_Decode, 233, 9, 7, // Opcode: KMO +/* 5946 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 5964 +/* 5950 */ MCD_OPC_CheckPredicate, 6, 26, 10, // Skip to: 8540 +/* 5954 */ MCD_OPC_CheckField, 0, 16, 0, 20, 10, // Skip to: 8540 +/* 5960 */ MCD_OPC_Decode, 135, 14, 0, // Opcode: PCC +/* 5964 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 5983 +/* 5968 */ MCD_OPC_CheckPredicate, 6, 8, 10, // Skip to: 8540 +/* 5972 */ MCD_OPC_CheckField, 8, 4, 0, 2, 10, // Skip to: 8540 +/* 5978 */ MCD_OPC_Decode, 231, 9, 138, 1, // Opcode: KMCTR +/* 5983 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 5997 +/* 5987 */ MCD_OPC_CheckField, 8, 8, 0, 243, 9, // Skip to: 8540 +/* 5993 */ MCD_OPC_Decode, 227, 9, 7, // Opcode: KM +/* 5997 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 6011 +/* 6001 */ MCD_OPC_CheckField, 8, 8, 0, 229, 9, // Skip to: 8540 +/* 6007 */ MCD_OPC_Decode, 230, 9, 7, // Opcode: KMC +/* 6011 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 6025 +/* 6015 */ MCD_OPC_CheckField, 8, 8, 0, 215, 9, // Skip to: 8540 +/* 6021 */ MCD_OPC_Decode, 202, 4, 56, // Opcode: CGFR +/* 6025 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 6039 +/* 6029 */ MCD_OPC_CheckField, 8, 8, 0, 201, 9, // Skip to: 8540 +/* 6035 */ MCD_OPC_Decode, 128, 6, 56, // Opcode: CLGFR +/* 6039 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 6057 +/* 6043 */ MCD_OPC_CheckPredicate, 7, 189, 9, // Skip to: 8540 +/* 6047 */ MCD_OPC_CheckField, 8, 8, 0, 183, 9, // Skip to: 8540 +/* 6053 */ MCD_OPC_Decode, 148, 14, 7, // Opcode: PPNO +/* 6057 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 6072 +/* 6061 */ MCD_OPC_CheckField, 8, 8, 0, 169, 9, // Skip to: 8540 +/* 6067 */ MCD_OPC_Decode, 225, 9, 137, 1, // Opcode: KIMD +/* 6072 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 6087 +/* 6076 */ MCD_OPC_CheckField, 8, 8, 0, 154, 9, // Skip to: 8540 +/* 6082 */ MCD_OPC_Decode, 226, 9, 137, 1, // Opcode: KLMD +/* 6087 */ MCD_OPC_FilterValue, 65, 8, 0, // Skip to: 6099 +/* 6091 */ MCD_OPC_CheckPredicate, 0, 141, 9, // Skip to: 8540 +/* 6095 */ MCD_OPC_Decode, 182, 4, 108, // Opcode: CFDTR +/* 6099 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 6111 +/* 6103 */ MCD_OPC_CheckPredicate, 0, 129, 9, // Skip to: 8540 +/* 6107 */ MCD_OPC_Decode, 252, 5, 120, // Opcode: CLGDTR +/* 6111 */ MCD_OPC_FilterValue, 67, 8, 0, // Skip to: 6123 +/* 6115 */ MCD_OPC_CheckPredicate, 0, 117, 9, // Skip to: 8540 +/* 6119 */ MCD_OPC_Decode, 230, 5, 108, // Opcode: CLFDTR +/* 6123 */ MCD_OPC_FilterValue, 70, 11, 0, // Skip to: 6138 +/* 6127 */ MCD_OPC_CheckField, 8, 8, 0, 103, 9, // Skip to: 8540 +/* 6133 */ MCD_OPC_Decode, 198, 3, 135, 1, // Opcode: BCTGR +/* 6138 */ MCD_OPC_FilterValue, 73, 8, 0, // Skip to: 6150 +/* 6142 */ MCD_OPC_CheckPredicate, 0, 90, 9, // Skip to: 8540 +/* 6146 */ MCD_OPC_Decode, 190, 4, 110, // Opcode: CFXTR +/* 6150 */ MCD_OPC_FilterValue, 74, 8, 0, // Skip to: 6162 +/* 6154 */ MCD_OPC_CheckPredicate, 0, 78, 9, // Skip to: 8540 +/* 6158 */ MCD_OPC_Decode, 233, 6, 122, // Opcode: CLGXTR +/* 6162 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 6174 +/* 6166 */ MCD_OPC_CheckPredicate, 0, 66, 9, // Skip to: 8540 +/* 6170 */ MCD_OPC_Decode, 249, 5, 110, // Opcode: CLFXTR +/* 6174 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 6186 +/* 6178 */ MCD_OPC_CheckPredicate, 0, 54, 9, // Skip to: 8540 +/* 6182 */ MCD_OPC_Decode, 145, 4, 100, // Opcode: CDFTR +/* 6186 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 6198 +/* 6190 */ MCD_OPC_CheckPredicate, 0, 42, 9, // Skip to: 8540 +/* 6194 */ MCD_OPC_Decode, 154, 4, 112, // Opcode: CDLGTR +/* 6198 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 6210 +/* 6202 */ MCD_OPC_CheckPredicate, 0, 30, 9, // Skip to: 8540 +/* 6206 */ MCD_OPC_Decode, 152, 4, 100, // Opcode: CDLFTR +/* 6210 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 6222 +/* 6214 */ MCD_OPC_CheckPredicate, 0, 18, 9, // Skip to: 8540 +/* 6218 */ MCD_OPC_Decode, 168, 8, 101, // Opcode: CXFTR +/* 6222 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 6234 +/* 6226 */ MCD_OPC_CheckPredicate, 0, 6, 9, // Skip to: 8540 +/* 6230 */ MCD_OPC_Decode, 177, 8, 113, // Opcode: CXLGTR +/* 6234 */ MCD_OPC_FilterValue, 91, 8, 0, // Skip to: 6246 +/* 6238 */ MCD_OPC_CheckPredicate, 0, 250, 8, // Skip to: 8540 +/* 6242 */ MCD_OPC_Decode, 175, 8, 101, // Opcode: CXLFTR +/* 6246 */ MCD_OPC_FilterValue, 96, 62, 0, // Skip to: 6312 +/* 6250 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6253 */ MCD_OPC_FilterValue, 0, 235, 8, // Skip to: 8540 +/* 6257 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6260 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6268 +/* 6264 */ MCD_OPC_Decode, 155, 5, 61, // Opcode: CGRTAsmH +/* 6268 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6276 +/* 6272 */ MCD_OPC_Decode, 157, 5, 61, // Opcode: CGRTAsmL +/* 6276 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6284 +/* 6280 */ MCD_OPC_Decode, 159, 5, 61, // Opcode: CGRTAsmLH +/* 6284 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6292 +/* 6288 */ MCD_OPC_Decode, 154, 5, 61, // Opcode: CGRTAsmE +/* 6292 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6300 +/* 6296 */ MCD_OPC_Decode, 156, 5, 61, // Opcode: CGRTAsmHE +/* 6300 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6308 +/* 6304 */ MCD_OPC_Decode, 158, 5, 61, // Opcode: CGRTAsmLE +/* 6308 */ MCD_OPC_Decode, 153, 5, 73, // Opcode: CGRTAsm +/* 6312 */ MCD_OPC_FilterValue, 97, 62, 0, // Skip to: 6378 +/* 6316 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6319 */ MCD_OPC_FilterValue, 0, 169, 8, // Skip to: 8540 +/* 6323 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6326 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6334 +/* 6330 */ MCD_OPC_Decode, 207, 6, 61, // Opcode: CLGRTAsmH +/* 6334 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6342 +/* 6338 */ MCD_OPC_Decode, 209, 6, 61, // Opcode: CLGRTAsmL +/* 6342 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6350 +/* 6346 */ MCD_OPC_Decode, 211, 6, 61, // Opcode: CLGRTAsmLH +/* 6350 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6358 +/* 6354 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: CLGRTAsmE +/* 6358 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6366 +/* 6362 */ MCD_OPC_Decode, 208, 6, 61, // Opcode: CLGRTAsmHE +/* 6366 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6374 +/* 6370 */ MCD_OPC_Decode, 210, 6, 61, // Opcode: CLGRTAsmLE +/* 6374 */ MCD_OPC_Decode, 205, 6, 73, // Opcode: CLGRTAsm +/* 6378 */ MCD_OPC_FilterValue, 114, 63, 0, // Skip to: 6445 +/* 6382 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6385 */ MCD_OPC_FilterValue, 0, 103, 8, // Skip to: 8540 +/* 6389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6392 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6400 +/* 6396 */ MCD_OPC_Decode, 249, 7, 8, // Opcode: CRTAsmH +/* 6400 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6408 +/* 6404 */ MCD_OPC_Decode, 251, 7, 8, // Opcode: CRTAsmL +/* 6408 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6416 +/* 6412 */ MCD_OPC_Decode, 253, 7, 8, // Opcode: CRTAsmLH +/* 6416 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6424 +/* 6420 */ MCD_OPC_Decode, 248, 7, 8, // Opcode: CRTAsmE +/* 6424 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6432 +/* 6428 */ MCD_OPC_Decode, 250, 7, 8, // Opcode: CRTAsmHE +/* 6432 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6440 +/* 6436 */ MCD_OPC_Decode, 252, 7, 8, // Opcode: CRTAsmLE +/* 6440 */ MCD_OPC_Decode, 247, 7, 139, 1, // Opcode: CRTAsm +/* 6445 */ MCD_OPC_FilterValue, 115, 63, 0, // Skip to: 6512 +/* 6449 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6452 */ MCD_OPC_FilterValue, 0, 36, 8, // Skip to: 8540 +/* 6456 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6459 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6467 +/* 6463 */ MCD_OPC_Decode, 178, 7, 8, // Opcode: CLRTAsmH +/* 6467 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6475 +/* 6471 */ MCD_OPC_Decode, 180, 7, 8, // Opcode: CLRTAsmL +/* 6475 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6483 +/* 6479 */ MCD_OPC_Decode, 182, 7, 8, // Opcode: CLRTAsmLH +/* 6483 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6491 +/* 6487 */ MCD_OPC_Decode, 177, 7, 8, // Opcode: CLRTAsmE +/* 6491 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6499 +/* 6495 */ MCD_OPC_Decode, 179, 7, 8, // Opcode: CLRTAsmHE +/* 6499 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6507 +/* 6503 */ MCD_OPC_Decode, 181, 7, 8, // Opcode: CLRTAsmLE +/* 6507 */ MCD_OPC_Decode, 176, 7, 139, 1, // Opcode: CLRTAsm +/* 6512 */ MCD_OPC_FilterValue, 128, 1, 11, 0, // Skip to: 6528 +/* 6517 */ MCD_OPC_CheckField, 8, 8, 0, 225, 7, // Skip to: 8540 +/* 6523 */ MCD_OPC_Decode, 229, 13, 135, 1, // Opcode: NGR +/* 6528 */ MCD_OPC_FilterValue, 129, 1, 11, 0, // Skip to: 6544 +/* 6533 */ MCD_OPC_CheckField, 8, 8, 0, 209, 7, // Skip to: 8540 +/* 6539 */ MCD_OPC_Decode, 247, 13, 135, 1, // Opcode: OGR +/* 6544 */ MCD_OPC_FilterValue, 130, 1, 11, 0, // Skip to: 6560 +/* 6549 */ MCD_OPC_CheckField, 8, 8, 0, 193, 7, // Skip to: 8540 +/* 6555 */ MCD_OPC_Decode, 229, 21, 135, 1, // Opcode: XGR +/* 6560 */ MCD_OPC_FilterValue, 131, 1, 11, 0, // Skip to: 6576 +/* 6565 */ MCD_OPC_CheckField, 8, 8, 0, 177, 7, // Skip to: 8540 +/* 6571 */ MCD_OPC_Decode, 251, 8, 140, 1, // Opcode: FLOGR +/* 6576 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 6591 +/* 6581 */ MCD_OPC_CheckField, 8, 8, 0, 161, 7, // Skip to: 8540 +/* 6587 */ MCD_OPC_Decode, 202, 10, 61, // Opcode: LLGCR +/* 6591 */ MCD_OPC_FilterValue, 133, 1, 10, 0, // Skip to: 6606 +/* 6596 */ MCD_OPC_CheckField, 8, 8, 0, 146, 7, // Skip to: 8540 +/* 6602 */ MCD_OPC_Decode, 209, 10, 61, // Opcode: LLGHR +/* 6606 */ MCD_OPC_FilterValue, 134, 1, 10, 0, // Skip to: 6621 +/* 6611 */ MCD_OPC_CheckField, 8, 8, 0, 131, 7, // Skip to: 8540 +/* 6617 */ MCD_OPC_Decode, 164, 13, 68, // Opcode: MLGR +/* 6621 */ MCD_OPC_FilterValue, 135, 1, 10, 0, // Skip to: 6636 +/* 6626 */ MCD_OPC_CheckField, 8, 8, 0, 116, 7, // Skip to: 8540 +/* 6632 */ MCD_OPC_Decode, 203, 8, 68, // Opcode: DLGR +/* 6636 */ MCD_OPC_FilterValue, 136, 1, 11, 0, // Skip to: 6652 +/* 6641 */ MCD_OPC_CheckField, 8, 8, 0, 101, 7, // Skip to: 8540 +/* 6647 */ MCD_OPC_Decode, 132, 3, 135, 1, // Opcode: ALCGR +/* 6652 */ MCD_OPC_FilterValue, 137, 1, 11, 0, // Skip to: 6668 +/* 6657 */ MCD_OPC_CheckField, 8, 8, 0, 85, 7, // Skip to: 8540 +/* 6663 */ MCD_OPC_Decode, 221, 14, 135, 1, // Opcode: SLBGR +/* 6668 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 6683 +/* 6673 */ MCD_OPC_CheckField, 8, 8, 0, 69, 7, // Skip to: 8540 +/* 6679 */ MCD_OPC_Decode, 137, 8, 68, // Opcode: CSPG +/* 6683 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 6698 +/* 6688 */ MCD_OPC_CheckField, 8, 8, 0, 54, 7, // Skip to: 8540 +/* 6694 */ MCD_OPC_Decode, 228, 8, 8, // Opcode: EPSW +/* 6698 */ MCD_OPC_FilterValue, 142, 1, 16, 0, // Skip to: 6719 +/* 6703 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6714 +/* 6709 */ MCD_OPC_Decode, 136, 9, 141, 1, // Opcode: IDTEOpt +/* 6714 */ MCD_OPC_Decode, 135, 9, 142, 1, // Opcode: IDTE +/* 6719 */ MCD_OPC_FilterValue, 143, 1, 24, 0, // Skip to: 6748 +/* 6724 */ MCD_OPC_CheckPredicate, 8, 11, 0, // Skip to: 6739 +/* 6728 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6739 +/* 6734 */ MCD_OPC_Decode, 230, 7, 143, 1, // Opcode: CRDTEOpt +/* 6739 */ MCD_OPC_CheckPredicate, 8, 5, 7, // Skip to: 8540 +/* 6743 */ MCD_OPC_Decode, 229, 7, 144, 1, // Opcode: CRDTE +/* 6748 */ MCD_OPC_FilterValue, 144, 1, 22, 0, // Skip to: 6775 +/* 6753 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6756 */ MCD_OPC_FilterValue, 0, 244, 6, // Skip to: 8540 +/* 6760 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6770 +/* 6766 */ MCD_OPC_Decode, 203, 16, 71, // Opcode: TRTTOpt +/* 6770 */ MCD_OPC_Decode, 202, 16, 145, 1, // Opcode: TRTT +/* 6775 */ MCD_OPC_FilterValue, 145, 1, 22, 0, // Skip to: 6802 +/* 6780 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6783 */ MCD_OPC_FilterValue, 0, 217, 6, // Skip to: 8540 +/* 6787 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6797 +/* 6793 */ MCD_OPC_Decode, 198, 16, 71, // Opcode: TRTOOpt +/* 6797 */ MCD_OPC_Decode, 197, 16, 145, 1, // Opcode: TRTO +/* 6802 */ MCD_OPC_FilterValue, 146, 1, 22, 0, // Skip to: 6829 +/* 6807 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6810 */ MCD_OPC_FilterValue, 0, 190, 6, // Skip to: 8540 +/* 6814 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6824 +/* 6820 */ MCD_OPC_Decode, 193, 16, 71, // Opcode: TROTOpt +/* 6824 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: TROT +/* 6829 */ MCD_OPC_FilterValue, 147, 1, 22, 0, // Skip to: 6856 +/* 6834 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6837 */ MCD_OPC_FilterValue, 0, 163, 6, // Skip to: 8540 +/* 6841 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6851 +/* 6847 */ MCD_OPC_Decode, 191, 16, 71, // Opcode: TROOOpt +/* 6851 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: TROO +/* 6856 */ MCD_OPC_FilterValue, 148, 1, 10, 0, // Skip to: 6871 +/* 6861 */ MCD_OPC_CheckField, 8, 8, 0, 137, 6, // Skip to: 8540 +/* 6867 */ MCD_OPC_Decode, 200, 10, 8, // Opcode: LLCR +/* 6871 */ MCD_OPC_FilterValue, 149, 1, 10, 0, // Skip to: 6886 +/* 6876 */ MCD_OPC_CheckField, 8, 8, 0, 122, 6, // Skip to: 8540 +/* 6882 */ MCD_OPC_Decode, 216, 10, 8, // Opcode: LLHR +/* 6886 */ MCD_OPC_FilterValue, 150, 1, 10, 0, // Skip to: 6901 +/* 6891 */ MCD_OPC_CheckField, 8, 8, 0, 107, 6, // Skip to: 8540 +/* 6897 */ MCD_OPC_Decode, 165, 13, 10, // Opcode: MLR +/* 6901 */ MCD_OPC_FilterValue, 151, 1, 10, 0, // Skip to: 6916 +/* 6906 */ MCD_OPC_CheckField, 8, 8, 0, 92, 6, // Skip to: 8540 +/* 6912 */ MCD_OPC_Decode, 204, 8, 10, // Opcode: DLR +/* 6916 */ MCD_OPC_FilterValue, 152, 1, 10, 0, // Skip to: 6931 +/* 6921 */ MCD_OPC_CheckField, 8, 8, 0, 77, 6, // Skip to: 8540 +/* 6927 */ MCD_OPC_Decode, 133, 3, 9, // Opcode: ALCR +/* 6931 */ MCD_OPC_FilterValue, 153, 1, 10, 0, // Skip to: 6946 +/* 6936 */ MCD_OPC_CheckField, 8, 8, 0, 62, 6, // Skip to: 8540 +/* 6942 */ MCD_OPC_Decode, 222, 14, 9, // Opcode: SLBR +/* 6946 */ MCD_OPC_FilterValue, 154, 1, 17, 0, // Skip to: 6968 +/* 6951 */ MCD_OPC_CheckField, 8, 8, 0, 47, 6, // Skip to: 8540 +/* 6957 */ MCD_OPC_CheckField, 0, 4, 0, 41, 6, // Skip to: 8540 +/* 6963 */ MCD_OPC_Decode, 225, 8, 146, 1, // Opcode: EPAIR +/* 6968 */ MCD_OPC_FilterValue, 155, 1, 17, 0, // Skip to: 6990 +/* 6973 */ MCD_OPC_CheckField, 8, 8, 0, 25, 6, // Skip to: 8540 +/* 6979 */ MCD_OPC_CheckField, 0, 4, 0, 19, 6, // Skip to: 8540 +/* 6985 */ MCD_OPC_Decode, 231, 8, 146, 1, // Opcode: ESAIR +/* 6990 */ MCD_OPC_FilterValue, 157, 1, 17, 0, // Skip to: 7012 +/* 6995 */ MCD_OPC_CheckField, 8, 8, 0, 3, 6, // Skip to: 8540 +/* 7001 */ MCD_OPC_CheckField, 0, 4, 0, 253, 5, // Skip to: 8540 +/* 7007 */ MCD_OPC_Decode, 234, 8, 147, 1, // Opcode: ESEA +/* 7012 */ MCD_OPC_FilterValue, 158, 1, 10, 0, // Skip to: 7027 +/* 7017 */ MCD_OPC_CheckField, 8, 8, 0, 237, 5, // Skip to: 8540 +/* 7023 */ MCD_OPC_Decode, 154, 14, 61, // Opcode: PTI +/* 7027 */ MCD_OPC_FilterValue, 159, 1, 17, 0, // Skip to: 7049 +/* 7032 */ MCD_OPC_CheckField, 8, 8, 0, 222, 5, // Skip to: 8540 +/* 7038 */ MCD_OPC_CheckField, 0, 4, 0, 216, 5, // Skip to: 8540 +/* 7044 */ MCD_OPC_Decode, 148, 15, 146, 1, // Opcode: SSAIR +/* 7049 */ MCD_OPC_FilterValue, 162, 1, 17, 0, // Skip to: 7071 +/* 7054 */ MCD_OPC_CheckField, 8, 8, 0, 200, 5, // Skip to: 8540 +/* 7060 */ MCD_OPC_CheckField, 0, 4, 0, 194, 5, // Skip to: 8540 +/* 7066 */ MCD_OPC_Decode, 152, 14, 148, 1, // Opcode: PTF +/* 7071 */ MCD_OPC_FilterValue, 170, 1, 5, 0, // Skip to: 7081 +/* 7076 */ MCD_OPC_Decode, 199, 12, 149, 1, // Opcode: LPTEA +/* 7081 */ MCD_OPC_FilterValue, 172, 1, 14, 0, // Skip to: 7100 +/* 7086 */ MCD_OPC_CheckPredicate, 9, 170, 5, // Skip to: 8540 +/* 7090 */ MCD_OPC_CheckField, 8, 8, 0, 164, 5, // Skip to: 8540 +/* 7096 */ MCD_OPC_Decode, 150, 9, 61, // Opcode: IRBM +/* 7100 */ MCD_OPC_FilterValue, 174, 1, 14, 0, // Skip to: 7119 +/* 7105 */ MCD_OPC_CheckPredicate, 10, 151, 5, // Skip to: 8540 +/* 7109 */ MCD_OPC_CheckField, 8, 8, 0, 145, 5, // Skip to: 8540 +/* 7115 */ MCD_OPC_Decode, 172, 14, 61, // Opcode: RRBM +/* 7119 */ MCD_OPC_FilterValue, 175, 1, 11, 0, // Skip to: 7135 +/* 7124 */ MCD_OPC_CheckField, 8, 8, 0, 130, 5, // Skip to: 8540 +/* 7130 */ MCD_OPC_Decode, 139, 14, 150, 1, // Opcode: PFMF +/* 7135 */ MCD_OPC_FilterValue, 176, 1, 21, 0, // Skip to: 7161 +/* 7140 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7143 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 8540 +/* 7147 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7157 +/* 7153 */ MCD_OPC_Decode, 144, 8, 7, // Opcode: CU14Opt +/* 7157 */ MCD_OPC_Decode, 143, 8, 72, // Opcode: CU14 +/* 7161 */ MCD_OPC_FilterValue, 177, 1, 21, 0, // Skip to: 7187 +/* 7166 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7169 */ MCD_OPC_FilterValue, 0, 87, 5, // Skip to: 8540 +/* 7173 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7183 +/* 7179 */ MCD_OPC_Decode, 148, 8, 7, // Opcode: CU24Opt +/* 7183 */ MCD_OPC_Decode, 147, 8, 72, // Opcode: CU24 +/* 7187 */ MCD_OPC_FilterValue, 178, 1, 10, 0, // Skip to: 7202 +/* 7192 */ MCD_OPC_CheckField, 8, 8, 0, 62, 5, // Skip to: 8540 +/* 7198 */ MCD_OPC_Decode, 149, 8, 7, // Opcode: CU41 +/* 7202 */ MCD_OPC_FilterValue, 179, 1, 10, 0, // Skip to: 7217 +/* 7207 */ MCD_OPC_CheckField, 8, 8, 0, 47, 5, // Skip to: 8540 +/* 7213 */ MCD_OPC_Decode, 150, 8, 7, // Opcode: CU42 +/* 7217 */ MCD_OPC_FilterValue, 189, 1, 23, 0, // Skip to: 7245 +/* 7222 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7225 */ MCD_OPC_FilterValue, 0, 31, 5, // Skip to: 8540 +/* 7229 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7240 +/* 7235 */ MCD_OPC_Decode, 201, 16, 151, 1, // Opcode: TRTREOpt +/* 7240 */ MCD_OPC_Decode, 200, 16, 152, 1, // Opcode: TRTRE +/* 7245 */ MCD_OPC_FilterValue, 190, 1, 10, 0, // Skip to: 7260 +/* 7250 */ MCD_OPC_CheckField, 8, 8, 0, 4, 5, // Skip to: 8540 +/* 7256 */ MCD_OPC_Decode, 146, 15, 69, // Opcode: SRSTU +/* 7260 */ MCD_OPC_FilterValue, 191, 1, 23, 0, // Skip to: 7288 +/* 7265 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7268 */ MCD_OPC_FilterValue, 0, 244, 4, // Skip to: 8540 +/* 7272 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7283 +/* 7278 */ MCD_OPC_Decode, 196, 16, 151, 1, // Opcode: TRTEOpt +/* 7283 */ MCD_OPC_Decode, 195, 16, 152, 1, // Opcode: TRTE +/* 7288 */ MCD_OPC_FilterValue, 200, 1, 15, 0, // Skip to: 7308 +/* 7293 */ MCD_OPC_CheckPredicate, 11, 219, 4, // Skip to: 8540 +/* 7297 */ MCD_OPC_CheckField, 8, 4, 0, 213, 4, // Skip to: 8540 +/* 7303 */ MCD_OPC_Decode, 251, 2, 153, 1, // Opcode: AHHHR +/* 7308 */ MCD_OPC_FilterValue, 201, 1, 15, 0, // Skip to: 7328 +/* 7313 */ MCD_OPC_CheckPredicate, 11, 199, 4, // Skip to: 8540 +/* 7317 */ MCD_OPC_CheckField, 8, 4, 0, 193, 4, // Skip to: 8540 +/* 7323 */ MCD_OPC_Decode, 209, 14, 153, 1, // Opcode: SHHHR +/* 7328 */ MCD_OPC_FilterValue, 202, 1, 15, 0, // Skip to: 7348 +/* 7333 */ MCD_OPC_CheckPredicate, 11, 179, 4, // Skip to: 8540 +/* 7337 */ MCD_OPC_CheckField, 8, 4, 0, 173, 4, // Skip to: 8540 +/* 7343 */ MCD_OPC_Decode, 143, 3, 153, 1, // Opcode: ALHHHR +/* 7348 */ MCD_OPC_FilterValue, 203, 1, 15, 0, // Skip to: 7368 +/* 7353 */ MCD_OPC_CheckPredicate, 11, 159, 4, // Skip to: 8540 +/* 7357 */ MCD_OPC_CheckField, 8, 4, 0, 153, 4, // Skip to: 8540 +/* 7363 */ MCD_OPC_Decode, 233, 14, 153, 1, // Opcode: SLHHHR +/* 7368 */ MCD_OPC_FilterValue, 205, 1, 15, 0, // Skip to: 7388 +/* 7373 */ MCD_OPC_CheckPredicate, 11, 139, 4, // Skip to: 8540 +/* 7377 */ MCD_OPC_CheckField, 8, 8, 0, 133, 4, // Skip to: 8540 +/* 7383 */ MCD_OPC_Decode, 173, 5, 154, 1, // Opcode: CHHR +/* 7388 */ MCD_OPC_FilterValue, 207, 1, 15, 0, // Skip to: 7408 +/* 7393 */ MCD_OPC_CheckPredicate, 11, 119, 4, // Skip to: 8540 +/* 7397 */ MCD_OPC_CheckField, 8, 8, 0, 113, 4, // Skip to: 8540 +/* 7403 */ MCD_OPC_Decode, 235, 6, 154, 1, // Opcode: CLHHR +/* 7408 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 7428 +/* 7413 */ MCD_OPC_CheckPredicate, 11, 99, 4, // Skip to: 8540 +/* 7417 */ MCD_OPC_CheckField, 8, 4, 0, 93, 4, // Skip to: 8540 +/* 7423 */ MCD_OPC_Decode, 252, 2, 155, 1, // Opcode: AHHLR +/* 7428 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 7448 +/* 7433 */ MCD_OPC_CheckPredicate, 11, 79, 4, // Skip to: 8540 +/* 7437 */ MCD_OPC_CheckField, 8, 4, 0, 73, 4, // Skip to: 8540 +/* 7443 */ MCD_OPC_Decode, 210, 14, 155, 1, // Opcode: SHHLR +/* 7448 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 7468 +/* 7453 */ MCD_OPC_CheckPredicate, 11, 59, 4, // Skip to: 8540 +/* 7457 */ MCD_OPC_CheckField, 8, 4, 0, 53, 4, // Skip to: 8540 +/* 7463 */ MCD_OPC_Decode, 144, 3, 155, 1, // Opcode: ALHHLR +/* 7468 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 7488 +/* 7473 */ MCD_OPC_CheckPredicate, 11, 39, 4, // Skip to: 8540 +/* 7477 */ MCD_OPC_CheckField, 8, 4, 0, 33, 4, // Skip to: 8540 +/* 7483 */ MCD_OPC_Decode, 234, 14, 155, 1, // Opcode: SLHHLR +/* 7488 */ MCD_OPC_FilterValue, 221, 1, 15, 0, // Skip to: 7508 +/* 7493 */ MCD_OPC_CheckPredicate, 11, 19, 4, // Skip to: 8540 +/* 7497 */ MCD_OPC_CheckField, 8, 8, 0, 13, 4, // Skip to: 8540 +/* 7503 */ MCD_OPC_Decode, 176, 5, 156, 1, // Opcode: CHLR +/* 7508 */ MCD_OPC_FilterValue, 223, 1, 15, 0, // Skip to: 7528 +/* 7513 */ MCD_OPC_CheckPredicate, 11, 255, 3, // Skip to: 8540 +/* 7517 */ MCD_OPC_CheckField, 8, 8, 0, 249, 3, // Skip to: 8540 +/* 7523 */ MCD_OPC_Decode, 237, 6, 156, 1, // Opcode: CLHLR +/* 7528 */ MCD_OPC_FilterValue, 224, 1, 201, 0, // Skip to: 7734 +/* 7533 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7536 */ MCD_OPC_FilterValue, 0, 232, 3, // Skip to: 8540 +/* 7540 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7543 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7556 +/* 7547 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 7725 +/* 7551 */ MCD_OPC_Decode, 176, 11, 157, 1, // Opcode: LOCFHRAsmO +/* 7556 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7569 +/* 7560 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 7725 +/* 7564 */ MCD_OPC_Decode, 160, 11, 157, 1, // Opcode: LOCFHRAsmH +/* 7569 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7582 +/* 7573 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 7725 +/* 7577 */ MCD_OPC_Decode, 170, 11, 157, 1, // Opcode: LOCFHRAsmNLE +/* 7582 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7595 +/* 7586 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 7725 +/* 7590 */ MCD_OPC_Decode, 162, 11, 157, 1, // Opcode: LOCFHRAsmL +/* 7595 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7608 +/* 7599 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 7725 +/* 7603 */ MCD_OPC_Decode, 168, 11, 157, 1, // Opcode: LOCFHRAsmNHE +/* 7608 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7621 +/* 7612 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 7725 +/* 7616 */ MCD_OPC_Decode, 164, 11, 157, 1, // Opcode: LOCFHRAsmLH +/* 7621 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7634 +/* 7625 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 7725 +/* 7629 */ MCD_OPC_Decode, 166, 11, 157, 1, // Opcode: LOCFHRAsmNE +/* 7634 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7647 +/* 7638 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 7725 +/* 7642 */ MCD_OPC_Decode, 159, 11, 157, 1, // Opcode: LOCFHRAsmE +/* 7647 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7660 +/* 7651 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 7725 +/* 7655 */ MCD_OPC_Decode, 171, 11, 157, 1, // Opcode: LOCFHRAsmNLH +/* 7660 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7673 +/* 7664 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 7725 +/* 7668 */ MCD_OPC_Decode, 161, 11, 157, 1, // Opcode: LOCFHRAsmHE +/* 7673 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7686 +/* 7677 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 7725 +/* 7681 */ MCD_OPC_Decode, 169, 11, 157, 1, // Opcode: LOCFHRAsmNL +/* 7686 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7699 +/* 7690 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 7725 +/* 7694 */ MCD_OPC_Decode, 163, 11, 157, 1, // Opcode: LOCFHRAsmLE +/* 7699 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7712 +/* 7703 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 7725 +/* 7707 */ MCD_OPC_Decode, 167, 11, 157, 1, // Opcode: LOCFHRAsmNH +/* 7712 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7725 +/* 7716 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 7725 +/* 7720 */ MCD_OPC_Decode, 173, 11, 157, 1, // Opcode: LOCFHRAsmNO +/* 7725 */ MCD_OPC_CheckPredicate, 12, 43, 3, // Skip to: 8540 +/* 7729 */ MCD_OPC_Decode, 158, 11, 158, 1, // Opcode: LOCFHRAsm +/* 7734 */ MCD_OPC_FilterValue, 225, 1, 14, 0, // Skip to: 7753 +/* 7739 */ MCD_OPC_CheckPredicate, 13, 29, 3, // Skip to: 8540 +/* 7743 */ MCD_OPC_CheckField, 8, 8, 0, 23, 3, // Skip to: 8540 +/* 7749 */ MCD_OPC_Decode, 146, 14, 61, // Opcode: POPCNT +/* 7753 */ MCD_OPC_FilterValue, 226, 1, 201, 0, // Skip to: 7959 +/* 7758 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 7761 */ MCD_OPC_FilterValue, 0, 7, 3, // Skip to: 8540 +/* 7765 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7768 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7781 +/* 7772 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 7950 +/* 7776 */ MCD_OPC_Decode, 242, 11, 135, 1, // Opcode: LOCGRAsmO +/* 7781 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7794 +/* 7785 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 7950 +/* 7789 */ MCD_OPC_Decode, 226, 11, 135, 1, // Opcode: LOCGRAsmH +/* 7794 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7807 +/* 7798 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 7950 +/* 7802 */ MCD_OPC_Decode, 236, 11, 135, 1, // Opcode: LOCGRAsmNLE +/* 7807 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7820 +/* 7811 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 7950 +/* 7815 */ MCD_OPC_Decode, 228, 11, 135, 1, // Opcode: LOCGRAsmL +/* 7820 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7833 +/* 7824 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 7950 +/* 7828 */ MCD_OPC_Decode, 234, 11, 135, 1, // Opcode: LOCGRAsmNHE +/* 7833 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7846 +/* 7837 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 7950 +/* 7841 */ MCD_OPC_Decode, 230, 11, 135, 1, // Opcode: LOCGRAsmLH +/* 7846 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7859 +/* 7850 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 7950 +/* 7854 */ MCD_OPC_Decode, 232, 11, 135, 1, // Opcode: LOCGRAsmNE +/* 7859 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7872 +/* 7863 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 7950 +/* 7867 */ MCD_OPC_Decode, 225, 11, 135, 1, // Opcode: LOCGRAsmE +/* 7872 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7885 +/* 7876 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 7950 +/* 7880 */ MCD_OPC_Decode, 237, 11, 135, 1, // Opcode: LOCGRAsmNLH +/* 7885 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7898 +/* 7889 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 7950 +/* 7893 */ MCD_OPC_Decode, 227, 11, 135, 1, // Opcode: LOCGRAsmHE +/* 7898 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7911 +/* 7902 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 7950 +/* 7906 */ MCD_OPC_Decode, 235, 11, 135, 1, // Opcode: LOCGRAsmNL +/* 7911 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7924 +/* 7915 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 7950 +/* 7919 */ MCD_OPC_Decode, 229, 11, 135, 1, // Opcode: LOCGRAsmLE +/* 7924 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7937 +/* 7928 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 7950 +/* 7932 */ MCD_OPC_Decode, 233, 11, 135, 1, // Opcode: LOCGRAsmNH +/* 7937 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7950 +/* 7941 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 7950 +/* 7945 */ MCD_OPC_Decode, 239, 11, 135, 1, // Opcode: LOCGRAsmNO +/* 7950 */ MCD_OPC_CheckPredicate, 14, 74, 2, // Skip to: 8540 +/* 7954 */ MCD_OPC_Decode, 224, 11, 159, 1, // Opcode: LOCGRAsm +/* 7959 */ MCD_OPC_FilterValue, 228, 1, 15, 0, // Skip to: 7979 +/* 7964 */ MCD_OPC_CheckPredicate, 15, 60, 2, // Skip to: 8540 +/* 7968 */ MCD_OPC_CheckField, 8, 4, 0, 54, 2, // Skip to: 8540 +/* 7974 */ MCD_OPC_Decode, 230, 13, 141, 1, // Opcode: NGRK +/* 7979 */ MCD_OPC_FilterValue, 230, 1, 15, 0, // Skip to: 7999 +/* 7984 */ MCD_OPC_CheckPredicate, 15, 40, 2, // Skip to: 8540 +/* 7988 */ MCD_OPC_CheckField, 8, 4, 0, 34, 2, // Skip to: 8540 +/* 7994 */ MCD_OPC_Decode, 248, 13, 141, 1, // Opcode: OGRK +/* 7999 */ MCD_OPC_FilterValue, 231, 1, 15, 0, // Skip to: 8019 +/* 8004 */ MCD_OPC_CheckPredicate, 15, 20, 2, // Skip to: 8540 +/* 8008 */ MCD_OPC_CheckField, 8, 4, 0, 14, 2, // Skip to: 8540 +/* 8014 */ MCD_OPC_Decode, 230, 21, 141, 1, // Opcode: XGRK +/* 8019 */ MCD_OPC_FilterValue, 232, 1, 15, 0, // Skip to: 8039 +/* 8024 */ MCD_OPC_CheckPredicate, 15, 0, 2, // Skip to: 8540 +/* 8028 */ MCD_OPC_CheckField, 8, 4, 0, 250, 1, // Skip to: 8540 +/* 8034 */ MCD_OPC_Decode, 248, 2, 141, 1, // Opcode: AGRK +/* 8039 */ MCD_OPC_FilterValue, 233, 1, 15, 0, // Skip to: 8059 +/* 8044 */ MCD_OPC_CheckPredicate, 15, 236, 1, // Skip to: 8540 +/* 8048 */ MCD_OPC_CheckField, 8, 4, 0, 230, 1, // Skip to: 8540 +/* 8054 */ MCD_OPC_Decode, 207, 14, 141, 1, // Opcode: SGRK +/* 8059 */ MCD_OPC_FilterValue, 234, 1, 15, 0, // Skip to: 8079 +/* 8064 */ MCD_OPC_CheckPredicate, 15, 216, 1, // Skip to: 8540 +/* 8068 */ MCD_OPC_CheckField, 8, 4, 0, 210, 1, // Skip to: 8540 +/* 8074 */ MCD_OPC_Decode, 141, 3, 141, 1, // Opcode: ALGRK +/* 8079 */ MCD_OPC_FilterValue, 235, 1, 15, 0, // Skip to: 8099 +/* 8084 */ MCD_OPC_CheckPredicate, 15, 196, 1, // Skip to: 8540 +/* 8088 */ MCD_OPC_CheckField, 8, 4, 0, 190, 1, // Skip to: 8540 +/* 8094 */ MCD_OPC_Decode, 232, 14, 141, 1, // Opcode: SLGRK +/* 8099 */ MCD_OPC_FilterValue, 236, 1, 15, 0, // Skip to: 8119 +/* 8104 */ MCD_OPC_CheckPredicate, 16, 176, 1, // Skip to: 8540 +/* 8108 */ MCD_OPC_CheckField, 8, 4, 0, 170, 1, // Skip to: 8540 +/* 8114 */ MCD_OPC_Decode, 158, 13, 160, 1, // Opcode: MGRK +/* 8119 */ MCD_OPC_FilterValue, 237, 1, 15, 0, // Skip to: 8139 +/* 8124 */ MCD_OPC_CheckPredicate, 16, 156, 1, // Skip to: 8540 +/* 8128 */ MCD_OPC_CheckField, 8, 4, 0, 150, 1, // Skip to: 8540 +/* 8134 */ MCD_OPC_Decode, 186, 13, 141, 1, // Opcode: MSGRKC +/* 8139 */ MCD_OPC_FilterValue, 242, 1, 187, 0, // Skip to: 8331 +/* 8144 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 8147 */ MCD_OPC_FilterValue, 0, 133, 1, // Skip to: 8540 +/* 8151 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8154 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8166 +/* 8158 */ MCD_OPC_CheckPredicate, 14, 160, 0, // Skip to: 8322 +/* 8162 */ MCD_OPC_Decode, 180, 12, 9, // Opcode: LOCRAsmO +/* 8166 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8178 +/* 8170 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 8322 +/* 8174 */ MCD_OPC_Decode, 164, 12, 9, // Opcode: LOCRAsmH +/* 8178 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8190 +/* 8182 */ MCD_OPC_CheckPredicate, 14, 136, 0, // Skip to: 8322 +/* 8186 */ MCD_OPC_Decode, 174, 12, 9, // Opcode: LOCRAsmNLE +/* 8190 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8202 +/* 8194 */ MCD_OPC_CheckPredicate, 14, 124, 0, // Skip to: 8322 +/* 8198 */ MCD_OPC_Decode, 166, 12, 9, // Opcode: LOCRAsmL +/* 8202 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8214 +/* 8206 */ MCD_OPC_CheckPredicate, 14, 112, 0, // Skip to: 8322 +/* 8210 */ MCD_OPC_Decode, 172, 12, 9, // Opcode: LOCRAsmNHE +/* 8214 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8226 +/* 8218 */ MCD_OPC_CheckPredicate, 14, 100, 0, // Skip to: 8322 +/* 8222 */ MCD_OPC_Decode, 168, 12, 9, // Opcode: LOCRAsmLH +/* 8226 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8238 +/* 8230 */ MCD_OPC_CheckPredicate, 14, 88, 0, // Skip to: 8322 +/* 8234 */ MCD_OPC_Decode, 170, 12, 9, // Opcode: LOCRAsmNE +/* 8238 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8250 +/* 8242 */ MCD_OPC_CheckPredicate, 14, 76, 0, // Skip to: 8322 +/* 8246 */ MCD_OPC_Decode, 163, 12, 9, // Opcode: LOCRAsmE +/* 8250 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8262 +/* 8254 */ MCD_OPC_CheckPredicate, 14, 64, 0, // Skip to: 8322 +/* 8258 */ MCD_OPC_Decode, 175, 12, 9, // Opcode: LOCRAsmNLH +/* 8262 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8274 +/* 8266 */ MCD_OPC_CheckPredicate, 14, 52, 0, // Skip to: 8322 +/* 8270 */ MCD_OPC_Decode, 165, 12, 9, // Opcode: LOCRAsmHE +/* 8274 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8286 +/* 8278 */ MCD_OPC_CheckPredicate, 14, 40, 0, // Skip to: 8322 +/* 8282 */ MCD_OPC_Decode, 173, 12, 9, // Opcode: LOCRAsmNL +/* 8286 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 8298 +/* 8290 */ MCD_OPC_CheckPredicate, 14, 28, 0, // Skip to: 8322 +/* 8294 */ MCD_OPC_Decode, 167, 12, 9, // Opcode: LOCRAsmLE +/* 8298 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 8310 +/* 8302 */ MCD_OPC_CheckPredicate, 14, 16, 0, // Skip to: 8322 +/* 8306 */ MCD_OPC_Decode, 171, 12, 9, // Opcode: LOCRAsmNH +/* 8310 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 8322 +/* 8314 */ MCD_OPC_CheckPredicate, 14, 4, 0, // Skip to: 8322 +/* 8318 */ MCD_OPC_Decode, 177, 12, 9, // Opcode: LOCRAsmNO +/* 8322 */ MCD_OPC_CheckPredicate, 14, 214, 0, // Skip to: 8540 +/* 8326 */ MCD_OPC_Decode, 162, 12, 161, 1, // Opcode: LOCRAsm +/* 8331 */ MCD_OPC_FilterValue, 244, 1, 15, 0, // Skip to: 8351 +/* 8336 */ MCD_OPC_CheckPredicate, 15, 200, 0, // Skip to: 8540 +/* 8340 */ MCD_OPC_CheckField, 8, 4, 0, 194, 0, // Skip to: 8540 +/* 8346 */ MCD_OPC_Decode, 241, 13, 162, 1, // Opcode: NRK +/* 8351 */ MCD_OPC_FilterValue, 246, 1, 15, 0, // Skip to: 8371 +/* 8356 */ MCD_OPC_CheckPredicate, 15, 180, 0, // Skip to: 8540 +/* 8360 */ MCD_OPC_CheckField, 8, 4, 0, 174, 0, // Skip to: 8540 +/* 8366 */ MCD_OPC_Decode, 130, 14, 162, 1, // Opcode: ORK +/* 8371 */ MCD_OPC_FilterValue, 247, 1, 15, 0, // Skip to: 8391 +/* 8376 */ MCD_OPC_CheckPredicate, 15, 160, 0, // Skip to: 8540 +/* 8380 */ MCD_OPC_CheckField, 8, 4, 0, 154, 0, // Skip to: 8540 +/* 8386 */ MCD_OPC_Decode, 236, 21, 162, 1, // Opcode: XRK +/* 8391 */ MCD_OPC_FilterValue, 248, 1, 15, 0, // Skip to: 8411 +/* 8396 */ MCD_OPC_CheckPredicate, 15, 140, 0, // Skip to: 8540 +/* 8400 */ MCD_OPC_CheckField, 8, 4, 0, 134, 0, // Skip to: 8540 +/* 8406 */ MCD_OPC_Decode, 154, 3, 162, 1, // Opcode: ARK +/* 8411 */ MCD_OPC_FilterValue, 249, 1, 15, 0, // Skip to: 8431 +/* 8416 */ MCD_OPC_CheckPredicate, 15, 120, 0, // Skip to: 8540 +/* 8420 */ MCD_OPC_CheckField, 8, 4, 0, 114, 0, // Skip to: 8540 +/* 8426 */ MCD_OPC_Decode, 137, 15, 162, 1, // Opcode: SRK +/* 8431 */ MCD_OPC_FilterValue, 250, 1, 15, 0, // Skip to: 8451 +/* 8436 */ MCD_OPC_CheckPredicate, 15, 100, 0, // Skip to: 8540 +/* 8440 */ MCD_OPC_CheckField, 8, 4, 0, 94, 0, // Skip to: 8540 +/* 8446 */ MCD_OPC_Decode, 147, 3, 162, 1, // Opcode: ALRK +/* 8451 */ MCD_OPC_FilterValue, 251, 1, 15, 0, // Skip to: 8471 +/* 8456 */ MCD_OPC_CheckPredicate, 15, 80, 0, // Skip to: 8540 +/* 8460 */ MCD_OPC_CheckField, 8, 4, 0, 74, 0, // Skip to: 8540 +/* 8466 */ MCD_OPC_Decode, 239, 14, 162, 1, // Opcode: SLRK +/* 8471 */ MCD_OPC_FilterValue, 253, 1, 64, 0, // Skip to: 8540 +/* 8476 */ MCD_OPC_CheckPredicate, 16, 60, 0, // Skip to: 8540 +/* 8480 */ MCD_OPC_CheckField, 8, 4, 0, 54, 0, // Skip to: 8540 +/* 8486 */ MCD_OPC_Decode, 188, 13, 162, 1, // Opcode: MSRKC +/* 8491 */ MCD_OPC_FilterValue, 186, 1, 4, 0, // Skip to: 8500 +/* 8496 */ MCD_OPC_Decode, 132, 8, 35, // Opcode: CS +/* 8500 */ MCD_OPC_FilterValue, 187, 1, 5, 0, // Skip to: 8510 +/* 8505 */ MCD_OPC_Decode, 157, 4, 163, 1, // Opcode: CDS +/* 8510 */ MCD_OPC_FilterValue, 189, 1, 5, 0, // Skip to: 8520 +/* 8515 */ MCD_OPC_Decode, 142, 7, 164, 1, // Opcode: CLM +/* 8520 */ MCD_OPC_FilterValue, 190, 1, 5, 0, // Skip to: 8530 +/* 8525 */ MCD_OPC_Decode, 164, 15, 164, 1, // Opcode: STCM +/* 8530 */ MCD_OPC_FilterValue, 191, 1, 5, 0, // Skip to: 8540 +/* 8535 */ MCD_OPC_Decode, 131, 9, 165, 1, // Opcode: ICM +/* 8540 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTable48[] = { +/* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ... +/* 3 */ MCD_OPC_FilterValue, 192, 1, 11, 1, // Skip to: 275 +/* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 11 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20 +/* 15 */ MCD_OPC_Decode, 250, 9, 166, 1, // Opcode: LARL +/* 20 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29 +/* 24 */ MCD_OPC_Decode, 181, 10, 167, 1, // Opcode: LGFI +/* 29 */ MCD_OPC_FilterValue, 4, 143, 0, // Skip to: 176 +/* 33 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... +/* 36 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 45 +/* 40 */ MCD_OPC_Decode, 217, 9, 168, 1, // Opcode: JGAsmO +/* 45 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 54 +/* 49 */ MCD_OPC_Decode, 201, 9, 168, 1, // Opcode: JGAsmH +/* 54 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 63 +/* 58 */ MCD_OPC_Decode, 211, 9, 168, 1, // Opcode: JGAsmNLE +/* 63 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 72 +/* 67 */ MCD_OPC_Decode, 203, 9, 168, 1, // Opcode: JGAsmL +/* 72 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 81 +/* 76 */ MCD_OPC_Decode, 209, 9, 168, 1, // Opcode: JGAsmNHE +/* 81 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 90 +/* 85 */ MCD_OPC_Decode, 205, 9, 168, 1, // Opcode: JGAsmLH +/* 90 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 99 +/* 94 */ MCD_OPC_Decode, 207, 9, 168, 1, // Opcode: JGAsmNE +/* 99 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 108 +/* 103 */ MCD_OPC_Decode, 200, 9, 168, 1, // Opcode: JGAsmE +/* 108 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 117 +/* 112 */ MCD_OPC_Decode, 212, 9, 168, 1, // Opcode: JGAsmNLH +/* 117 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 126 +/* 121 */ MCD_OPC_Decode, 202, 9, 168, 1, // Opcode: JGAsmHE +/* 126 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 135 +/* 130 */ MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: JGAsmNL +/* 135 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 144 +/* 139 */ MCD_OPC_Decode, 204, 9, 168, 1, // Opcode: JGAsmLE +/* 144 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 153 +/* 148 */ MCD_OPC_Decode, 208, 9, 168, 1, // Opcode: JGAsmNH +/* 153 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 162 +/* 157 */ MCD_OPC_Decode, 214, 9, 168, 1, // Opcode: JGAsmNO +/* 162 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 171 +/* 166 */ MCD_OPC_Decode, 199, 9, 168, 1, // Opcode: JG +/* 171 */ MCD_OPC_Decode, 251, 3, 169, 1, // Opcode: BRCLAsm +/* 176 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 185 +/* 180 */ MCD_OPC_Decode, 227, 3, 170, 1, // Opcode: BRASL +/* 185 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 194 +/* 189 */ MCD_OPC_Decode, 232, 21, 171, 1, // Opcode: XIHF +/* 194 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 203 +/* 198 */ MCD_OPC_Decode, 233, 21, 172, 1, // Opcode: XILF +/* 203 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 212 +/* 207 */ MCD_OPC_Decode, 139, 9, 173, 1, // Opcode: IIHF +/* 212 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 221 +/* 216 */ MCD_OPC_Decode, 142, 9, 174, 1, // Opcode: IILF +/* 221 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 230 +/* 225 */ MCD_OPC_Decode, 233, 13, 171, 1, // Opcode: NIHF +/* 230 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 239 +/* 234 */ MCD_OPC_Decode, 236, 13, 172, 1, // Opcode: NILF +/* 239 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 248 +/* 243 */ MCD_OPC_Decode, 250, 13, 171, 1, // Opcode: OIHF +/* 248 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 257 +/* 252 */ MCD_OPC_Decode, 253, 13, 172, 1, // Opcode: OILF +/* 257 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 266 +/* 261 */ MCD_OPC_Decode, 218, 10, 175, 1, // Opcode: LLIHF +/* 266 */ MCD_OPC_FilterValue, 15, 133, 73, // Skip to: 19091 +/* 270 */ MCD_OPC_Decode, 221, 10, 175, 1, // Opcode: LLILF +/* 275 */ MCD_OPC_FilterValue, 194, 1, 111, 0, // Skip to: 391 +/* 280 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 283 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 292 +/* 287 */ MCD_OPC_Decode, 183, 13, 176, 1, // Opcode: MSGFI +/* 292 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 301 +/* 296 */ MCD_OPC_Decode, 179, 13, 177, 1, // Opcode: MSFI +/* 301 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 310 +/* 305 */ MCD_OPC_Decode, 229, 14, 178, 1, // Opcode: SLGFI +/* 310 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 319 +/* 314 */ MCD_OPC_Decode, 226, 14, 172, 1, // Opcode: SLFI +/* 319 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 328 +/* 323 */ MCD_OPC_Decode, 242, 2, 176, 1, // Opcode: AGFI +/* 328 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 337 +/* 332 */ MCD_OPC_Decode, 239, 2, 177, 1, // Opcode: AFI +/* 337 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 346 +/* 341 */ MCD_OPC_Decode, 137, 3, 178, 1, // Opcode: ALGFI +/* 346 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 355 +/* 350 */ MCD_OPC_Decode, 134, 3, 172, 1, // Opcode: ALFI +/* 355 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 364 +/* 359 */ MCD_OPC_Decode, 201, 4, 167, 1, // Opcode: CGFI +/* 364 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 373 +/* 368 */ MCD_OPC_Decode, 186, 4, 179, 1, // Opcode: CFI +/* 373 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 382 +/* 377 */ MCD_OPC_Decode, 255, 5, 175, 1, // Opcode: CLGFI +/* 382 */ MCD_OPC_FilterValue, 15, 17, 73, // Skip to: 19091 +/* 386 */ MCD_OPC_Decode, 233, 5, 174, 1, // Opcode: CLFI +/* 391 */ MCD_OPC_FilterValue, 196, 1, 102, 0, // Skip to: 498 +/* 396 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 399 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 408 +/* 403 */ MCD_OPC_Decode, 217, 10, 180, 1, // Opcode: LLHRL +/* 408 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 417 +/* 412 */ MCD_OPC_Decode, 188, 10, 166, 1, // Opcode: LGHRL +/* 417 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 426 +/* 421 */ MCD_OPC_Decode, 196, 10, 180, 1, // Opcode: LHRL +/* 426 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 435 +/* 430 */ MCD_OPC_Decode, 210, 10, 166, 1, // Opcode: LLGHRL +/* 435 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 444 +/* 439 */ MCD_OPC_Decode, 185, 15, 180, 1, // Opcode: STHRL +/* 444 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 453 +/* 448 */ MCD_OPC_Decode, 190, 10, 166, 1, // Opcode: LGRL +/* 453 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 462 +/* 457 */ MCD_OPC_Decode, 181, 15, 166, 1, // Opcode: STGRL +/* 462 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 471 +/* 466 */ MCD_OPC_Decode, 183, 10, 166, 1, // Opcode: LGFRL +/* 471 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 480 +/* 475 */ MCD_OPC_Decode, 208, 12, 180, 1, // Opcode: LRL +/* 480 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 489 +/* 484 */ MCD_OPC_Decode, 206, 10, 166, 1, // Opcode: LLGFRL +/* 489 */ MCD_OPC_FilterValue, 15, 166, 72, // Skip to: 19091 +/* 493 */ MCD_OPC_Decode, 136, 16, 180, 1, // Opcode: STRL +/* 498 */ MCD_OPC_FilterValue, 197, 1, 9, 0, // Skip to: 512 +/* 503 */ MCD_OPC_CheckPredicate, 3, 152, 72, // Skip to: 19091 +/* 507 */ MCD_OPC_Decode, 224, 3, 181, 1, // Opcode: BPRP +/* 512 */ MCD_OPC_FilterValue, 198, 1, 111, 0, // Skip to: 628 +/* 517 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 520 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 529 +/* 524 */ MCD_OPC_Decode, 239, 8, 166, 1, // Opcode: EXRL +/* 529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 538 +/* 533 */ MCD_OPC_Decode, 138, 14, 182, 1, // Opcode: PFDRL +/* 538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 547 +/* 542 */ MCD_OPC_Decode, 206, 4, 166, 1, // Opcode: CGHRL +/* 547 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 556 +/* 551 */ MCD_OPC_Decode, 177, 5, 180, 1, // Opcode: CHRL +/* 556 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 565 +/* 560 */ MCD_OPC_Decode, 130, 6, 166, 1, // Opcode: CLGHRL +/* 565 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 574 +/* 569 */ MCD_OPC_Decode, 238, 6, 180, 1, // Opcode: CLHRL +/* 574 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 583 +/* 578 */ MCD_OPC_Decode, 151, 5, 166, 1, // Opcode: CGRL +/* 583 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 592 +/* 587 */ MCD_OPC_Decode, 203, 6, 166, 1, // Opcode: CLGRL +/* 592 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 601 +/* 596 */ MCD_OPC_Decode, 203, 4, 166, 1, // Opcode: CGFRL +/* 601 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 610 +/* 605 */ MCD_OPC_Decode, 245, 7, 180, 1, // Opcode: CRL +/* 610 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 619 +/* 614 */ MCD_OPC_Decode, 129, 6, 166, 1, // Opcode: CLGFRL +/* 619 */ MCD_OPC_FilterValue, 15, 36, 72, // Skip to: 19091 +/* 623 */ MCD_OPC_Decode, 174, 7, 180, 1, // Opcode: CLRL +/* 628 */ MCD_OPC_FilterValue, 199, 1, 15, 0, // Skip to: 648 +/* 633 */ MCD_OPC_CheckPredicate, 3, 22, 72, // Skip to: 19091 +/* 637 */ MCD_OPC_CheckField, 32, 4, 0, 16, 72, // Skip to: 19091 +/* 643 */ MCD_OPC_Decode, 223, 3, 183, 1, // Opcode: BPP +/* 648 */ MCD_OPC_FilterValue, 200, 1, 56, 0, // Skip to: 709 +/* 653 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 656 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 665 +/* 660 */ MCD_OPC_Decode, 198, 13, 184, 1, // Opcode: MVCOS +/* 665 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 674 +/* 669 */ MCD_OPC_Decode, 219, 8, 184, 1, // Opcode: ECTG +/* 674 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 683 +/* 678 */ MCD_OPC_Decode, 138, 8, 184, 1, // Opcode: CSST +/* 683 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 696 +/* 687 */ MCD_OPC_CheckPredicate, 17, 224, 71, // Skip to: 19091 +/* 691 */ MCD_OPC_Decode, 184, 12, 185, 1, // Opcode: LPD +/* 696 */ MCD_OPC_FilterValue, 5, 215, 71, // Skip to: 19091 +/* 700 */ MCD_OPC_CheckPredicate, 17, 211, 71, // Skip to: 19091 +/* 704 */ MCD_OPC_Decode, 188, 12, 185, 1, // Opcode: LPDG +/* 709 */ MCD_OPC_FilterValue, 204, 1, 81, 0, // Skip to: 795 +/* 714 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 717 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 730 +/* 721 */ MCD_OPC_CheckPredicate, 11, 190, 71, // Skip to: 19091 +/* 725 */ MCD_OPC_Decode, 254, 3, 186, 1, // Opcode: BRCTH +/* 730 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 743 +/* 734 */ MCD_OPC_CheckPredicate, 11, 177, 71, // Skip to: 19091 +/* 738 */ MCD_OPC_Decode, 128, 3, 187, 1, // Opcode: AIH +/* 743 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 756 +/* 747 */ MCD_OPC_CheckPredicate, 11, 164, 71, // Skip to: 19091 +/* 751 */ MCD_OPC_Decode, 149, 3, 187, 1, // Opcode: ALSIH +/* 756 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 769 +/* 760 */ MCD_OPC_CheckPredicate, 11, 151, 71, // Skip to: 19091 +/* 764 */ MCD_OPC_Decode, 150, 3, 187, 1, // Opcode: ALSIHN +/* 769 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 782 +/* 773 */ MCD_OPC_CheckPredicate, 11, 138, 71, // Skip to: 19091 +/* 777 */ MCD_OPC_Decode, 194, 5, 188, 1, // Opcode: CIH +/* 782 */ MCD_OPC_FilterValue, 15, 129, 71, // Skip to: 19091 +/* 786 */ MCD_OPC_CheckPredicate, 11, 125, 71, // Skip to: 19091 +/* 790 */ MCD_OPC_Decode, 254, 6, 173, 1, // Opcode: CLIH +/* 795 */ MCD_OPC_FilterValue, 208, 1, 5, 0, // Skip to: 805 +/* 800 */ MCD_OPC_Decode, 199, 16, 189, 1, // Opcode: TRTR +/* 805 */ MCD_OPC_FilterValue, 209, 1, 5, 0, // Skip to: 815 +/* 810 */ MCD_OPC_Decode, 207, 13, 189, 1, // Opcode: MVN +/* 815 */ MCD_OPC_FilterValue, 210, 1, 5, 0, // Skip to: 825 +/* 820 */ MCD_OPC_Decode, 191, 13, 189, 1, // Opcode: MVC +/* 825 */ MCD_OPC_FilterValue, 211, 1, 5, 0, // Skip to: 835 +/* 830 */ MCD_OPC_Decode, 211, 13, 189, 1, // Opcode: MVZ +/* 835 */ MCD_OPC_FilterValue, 212, 1, 5, 0, // Skip to: 845 +/* 840 */ MCD_OPC_Decode, 227, 13, 189, 1, // Opcode: NC +/* 845 */ MCD_OPC_FilterValue, 213, 1, 5, 0, // Skip to: 855 +/* 850 */ MCD_OPC_Decode, 225, 5, 189, 1, // Opcode: CLC +/* 855 */ MCD_OPC_FilterValue, 214, 1, 5, 0, // Skip to: 865 +/* 860 */ MCD_OPC_Decode, 245, 13, 189, 1, // Opcode: OC +/* 865 */ MCD_OPC_FilterValue, 215, 1, 5, 0, // Skip to: 875 +/* 870 */ MCD_OPC_Decode, 227, 21, 189, 1, // Opcode: XC +/* 875 */ MCD_OPC_FilterValue, 217, 1, 5, 0, // Skip to: 885 +/* 880 */ MCD_OPC_Decode, 194, 13, 190, 1, // Opcode: MVCK +/* 885 */ MCD_OPC_FilterValue, 218, 1, 5, 0, // Skip to: 895 +/* 890 */ MCD_OPC_Decode, 199, 13, 190, 1, // Opcode: MVCP +/* 895 */ MCD_OPC_FilterValue, 219, 1, 5, 0, // Skip to: 905 +/* 900 */ MCD_OPC_Decode, 200, 13, 190, 1, // Opcode: MVCS +/* 905 */ MCD_OPC_FilterValue, 220, 1, 5, 0, // Skip to: 915 +/* 910 */ MCD_OPC_Decode, 184, 16, 189, 1, // Opcode: TR +/* 915 */ MCD_OPC_FilterValue, 221, 1, 5, 0, // Skip to: 925 +/* 920 */ MCD_OPC_Decode, 194, 16, 189, 1, // Opcode: TRT +/* 925 */ MCD_OPC_FilterValue, 222, 1, 5, 0, // Skip to: 935 +/* 930 */ MCD_OPC_Decode, 220, 8, 189, 1, // Opcode: ED +/* 935 */ MCD_OPC_FilterValue, 223, 1, 5, 0, // Skip to: 945 +/* 940 */ MCD_OPC_Decode, 221, 8, 189, 1, // Opcode: EDMK +/* 945 */ MCD_OPC_FilterValue, 225, 1, 5, 0, // Skip to: 955 +/* 950 */ MCD_OPC_Decode, 144, 14, 191, 1, // Opcode: PKU +/* 955 */ MCD_OPC_FilterValue, 226, 1, 5, 0, // Skip to: 965 +/* 960 */ MCD_OPC_Decode, 208, 16, 189, 1, // Opcode: UNPKU +/* 965 */ MCD_OPC_FilterValue, 227, 1, 83, 5, // Skip to: 2333 +/* 970 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 973 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 982 +/* 977 */ MCD_OPC_Decode, 223, 12, 192, 1, // Opcode: LTG +/* 982 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 991 +/* 986 */ MCD_OPC_Decode, 204, 12, 192, 1, // Opcode: LRAG +/* 991 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 1000 +/* 995 */ MCD_OPC_Decode, 175, 10, 192, 1, // Opcode: LG +/* 1000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 1009 +/* 1004 */ MCD_OPC_Decode, 160, 8, 193, 1, // Opcode: CVBY +/* 1009 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 1018 +/* 1013 */ MCD_OPC_Decode, 240, 2, 194, 1, // Opcode: AG +/* 1018 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 1027 +/* 1022 */ MCD_OPC_Decode, 202, 14, 194, 1, // Opcode: SG +/* 1027 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 1036 +/* 1031 */ MCD_OPC_Decode, 135, 3, 194, 1, // Opcode: ALG +/* 1036 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 1045 +/* 1040 */ MCD_OPC_Decode, 227, 14, 194, 1, // Opcode: SLG +/* 1045 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 1054 +/* 1049 */ MCD_OPC_Decode, 180, 13, 194, 1, // Opcode: MSG +/* 1054 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 1063 +/* 1058 */ MCD_OPC_Decode, 207, 8, 195, 1, // Opcode: DSG +/* 1063 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 1072 +/* 1067 */ MCD_OPC_Decode, 159, 8, 194, 1, // Opcode: CVBG +/* 1072 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 1081 +/* 1076 */ MCD_OPC_Decode, 210, 12, 192, 1, // Opcode: LRVG +/* 1081 */ MCD_OPC_FilterValue, 18, 5, 0, // Skip to: 1090 +/* 1085 */ MCD_OPC_Decode, 215, 12, 196, 1, // Opcode: LT +/* 1090 */ MCD_OPC_FilterValue, 19, 5, 0, // Skip to: 1099 +/* 1094 */ MCD_OPC_Decode, 205, 12, 192, 1, // Opcode: LRAY +/* 1099 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 1108 +/* 1103 */ MCD_OPC_Decode, 180, 10, 192, 1, // Opcode: LGF +/* 1108 */ MCD_OPC_FilterValue, 21, 5, 0, // Skip to: 1117 +/* 1112 */ MCD_OPC_Decode, 185, 10, 192, 1, // Opcode: LGH +/* 1117 */ MCD_OPC_FilterValue, 22, 5, 0, // Skip to: 1126 +/* 1121 */ MCD_OPC_Decode, 203, 10, 192, 1, // Opcode: LLGF +/* 1126 */ MCD_OPC_FilterValue, 23, 5, 0, // Skip to: 1135 +/* 1130 */ MCD_OPC_Decode, 211, 10, 192, 1, // Opcode: LLGT +/* 1135 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 1144 +/* 1139 */ MCD_OPC_Decode, 241, 2, 194, 1, // Opcode: AGF +/* 1144 */ MCD_OPC_FilterValue, 25, 5, 0, // Skip to: 1153 +/* 1148 */ MCD_OPC_Decode, 203, 14, 194, 1, // Opcode: SGF +/* 1153 */ MCD_OPC_FilterValue, 26, 5, 0, // Skip to: 1162 +/* 1157 */ MCD_OPC_Decode, 136, 3, 194, 1, // Opcode: ALGF +/* 1162 */ MCD_OPC_FilterValue, 27, 5, 0, // Skip to: 1171 +/* 1166 */ MCD_OPC_Decode, 228, 14, 194, 1, // Opcode: SLGF +/* 1171 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 1180 +/* 1175 */ MCD_OPC_Decode, 182, 13, 194, 1, // Opcode: MSGF +/* 1180 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 1189 +/* 1184 */ MCD_OPC_Decode, 208, 8, 195, 1, // Opcode: DSGF +/* 1189 */ MCD_OPC_FilterValue, 30, 5, 0, // Skip to: 1198 +/* 1193 */ MCD_OPC_Decode, 209, 12, 196, 1, // Opcode: LRV +/* 1198 */ MCD_OPC_FilterValue, 31, 5, 0, // Skip to: 1207 +/* 1202 */ MCD_OPC_Decode, 212, 12, 196, 1, // Opcode: LRVH +/* 1207 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 1216 +/* 1211 */ MCD_OPC_Decode, 191, 4, 192, 1, // Opcode: CG +/* 1216 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 1225 +/* 1220 */ MCD_OPC_Decode, 250, 5, 192, 1, // Opcode: CLG +/* 1225 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 1234 +/* 1229 */ MCD_OPC_Decode, 180, 15, 192, 1, // Opcode: STG +/* 1234 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 1247 +/* 1238 */ MCD_OPC_CheckPredicate, 2, 185, 69, // Skip to: 19091 +/* 1242 */ MCD_OPC_Decode, 242, 13, 192, 1, // Opcode: NTSTG +/* 1247 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 1256 +/* 1251 */ MCD_OPC_Decode, 163, 8, 196, 1, // Opcode: CVDY +/* 1256 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 1269 +/* 1260 */ MCD_OPC_CheckPredicate, 18, 163, 69, // Skip to: 19091 +/* 1264 */ MCD_OPC_Decode, 248, 12, 192, 1, // Opcode: LZRG +/* 1269 */ MCD_OPC_FilterValue, 46, 5, 0, // Skip to: 1278 +/* 1273 */ MCD_OPC_Decode, 162, 8, 192, 1, // Opcode: CVDG +/* 1278 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 1287 +/* 1282 */ MCD_OPC_Decode, 138, 16, 192, 1, // Opcode: STRVG +/* 1287 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 1296 +/* 1291 */ MCD_OPC_Decode, 200, 4, 192, 1, // Opcode: CGF +/* 1296 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 1305 +/* 1300 */ MCD_OPC_Decode, 254, 5, 192, 1, // Opcode: CLGF +/* 1305 */ MCD_OPC_FilterValue, 50, 5, 0, // Skip to: 1314 +/* 1309 */ MCD_OPC_Decode, 224, 12, 192, 1, // Opcode: LTGF +/* 1314 */ MCD_OPC_FilterValue, 52, 5, 0, // Skip to: 1323 +/* 1318 */ MCD_OPC_Decode, 204, 4, 192, 1, // Opcode: CGH +/* 1323 */ MCD_OPC_FilterValue, 54, 5, 0, // Skip to: 1332 +/* 1327 */ MCD_OPC_Decode, 137, 14, 197, 1, // Opcode: PFD +/* 1332 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 1345 +/* 1336 */ MCD_OPC_CheckPredicate, 16, 87, 69, // Skip to: 19091 +/* 1340 */ MCD_OPC_Decode, 244, 2, 194, 1, // Opcode: AGH +/* 1345 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 1358 +/* 1349 */ MCD_OPC_CheckPredicate, 16, 74, 69, // Skip to: 19091 +/* 1353 */ MCD_OPC_Decode, 205, 14, 194, 1, // Opcode: SGH +/* 1358 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1371 +/* 1362 */ MCD_OPC_CheckPredicate, 18, 61, 69, // Skip to: 19091 +/* 1366 */ MCD_OPC_Decode, 224, 10, 192, 1, // Opcode: LLZRGF +/* 1371 */ MCD_OPC_FilterValue, 59, 9, 0, // Skip to: 1384 +/* 1375 */ MCD_OPC_CheckPredicate, 18, 48, 69, // Skip to: 19091 +/* 1379 */ MCD_OPC_Decode, 247, 12, 196, 1, // Opcode: LZRF +/* 1384 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 1397 +/* 1388 */ MCD_OPC_CheckPredicate, 16, 35, 69, // Skip to: 19091 +/* 1392 */ MCD_OPC_Decode, 156, 13, 194, 1, // Opcode: MGH +/* 1397 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 1406 +/* 1401 */ MCD_OPC_Decode, 137, 16, 196, 1, // Opcode: STRV +/* 1406 */ MCD_OPC_FilterValue, 63, 5, 0, // Skip to: 1415 +/* 1410 */ MCD_OPC_Decode, 139, 16, 196, 1, // Opcode: STRVH +/* 1415 */ MCD_OPC_FilterValue, 70, 5, 0, // Skip to: 1424 +/* 1419 */ MCD_OPC_Decode, 197, 3, 194, 1, // Opcode: BCTG +/* 1424 */ MCD_OPC_FilterValue, 71, 207, 0, // Skip to: 1635 +/* 1428 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... +/* 1431 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1444 +/* 1435 */ MCD_OPC_CheckPredicate, 16, 187, 0, // Skip to: 1626 +/* 1439 */ MCD_OPC_Decode, 218, 3, 198, 1, // Opcode: BIAsmO +/* 1444 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1457 +/* 1448 */ MCD_OPC_CheckPredicate, 16, 174, 0, // Skip to: 1626 +/* 1452 */ MCD_OPC_Decode, 202, 3, 198, 1, // Opcode: BIAsmH +/* 1457 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1470 +/* 1461 */ MCD_OPC_CheckPredicate, 16, 161, 0, // Skip to: 1626 +/* 1465 */ MCD_OPC_Decode, 212, 3, 198, 1, // Opcode: BIAsmNLE +/* 1470 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1483 +/* 1474 */ MCD_OPC_CheckPredicate, 16, 148, 0, // Skip to: 1626 +/* 1478 */ MCD_OPC_Decode, 204, 3, 198, 1, // Opcode: BIAsmL +/* 1483 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1496 +/* 1487 */ MCD_OPC_CheckPredicate, 16, 135, 0, // Skip to: 1626 +/* 1491 */ MCD_OPC_Decode, 210, 3, 198, 1, // Opcode: BIAsmNHE +/* 1496 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1509 +/* 1500 */ MCD_OPC_CheckPredicate, 16, 122, 0, // Skip to: 1626 +/* 1504 */ MCD_OPC_Decode, 206, 3, 198, 1, // Opcode: BIAsmLH +/* 1509 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1522 +/* 1513 */ MCD_OPC_CheckPredicate, 16, 109, 0, // Skip to: 1626 +/* 1517 */ MCD_OPC_Decode, 208, 3, 198, 1, // Opcode: BIAsmNE +/* 1522 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1535 +/* 1526 */ MCD_OPC_CheckPredicate, 16, 96, 0, // Skip to: 1626 +/* 1530 */ MCD_OPC_Decode, 201, 3, 198, 1, // Opcode: BIAsmE +/* 1535 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1548 +/* 1539 */ MCD_OPC_CheckPredicate, 16, 83, 0, // Skip to: 1626 +/* 1543 */ MCD_OPC_Decode, 213, 3, 198, 1, // Opcode: BIAsmNLH +/* 1548 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1561 +/* 1552 */ MCD_OPC_CheckPredicate, 16, 70, 0, // Skip to: 1626 +/* 1556 */ MCD_OPC_Decode, 203, 3, 198, 1, // Opcode: BIAsmHE +/* 1561 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1574 +/* 1565 */ MCD_OPC_CheckPredicate, 16, 57, 0, // Skip to: 1626 +/* 1569 */ MCD_OPC_Decode, 211, 3, 198, 1, // Opcode: BIAsmNL +/* 1574 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1587 +/* 1578 */ MCD_OPC_CheckPredicate, 16, 44, 0, // Skip to: 1626 +/* 1582 */ MCD_OPC_Decode, 205, 3, 198, 1, // Opcode: BIAsmLE +/* 1587 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1600 +/* 1591 */ MCD_OPC_CheckPredicate, 16, 31, 0, // Skip to: 1626 +/* 1595 */ MCD_OPC_Decode, 209, 3, 198, 1, // Opcode: BIAsmNH +/* 1600 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1613 +/* 1604 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1626 +/* 1608 */ MCD_OPC_Decode, 215, 3, 198, 1, // Opcode: BIAsmNO +/* 1613 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1626 +/* 1617 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1626 +/* 1621 */ MCD_OPC_Decode, 200, 3, 198, 1, // Opcode: BI +/* 1626 */ MCD_OPC_CheckPredicate, 16, 53, 68, // Skip to: 19091 +/* 1630 */ MCD_OPC_Decode, 222, 3, 197, 1, // Opcode: BICAsm +/* 1635 */ MCD_OPC_FilterValue, 72, 9, 0, // Skip to: 1648 +/* 1639 */ MCD_OPC_CheckPredicate, 19, 40, 68, // Skip to: 19091 +/* 1643 */ MCD_OPC_Decode, 207, 10, 192, 1, // Opcode: LLGFSG +/* 1648 */ MCD_OPC_FilterValue, 73, 9, 0, // Skip to: 1661 +/* 1652 */ MCD_OPC_CheckPredicate, 19, 27, 68, // Skip to: 19091 +/* 1656 */ MCD_OPC_Decode, 182, 15, 192, 1, // Opcode: STGSC +/* 1661 */ MCD_OPC_FilterValue, 76, 9, 0, // Skip to: 1674 +/* 1665 */ MCD_OPC_CheckPredicate, 19, 14, 68, // Skip to: 19091 +/* 1669 */ MCD_OPC_Decode, 184, 10, 192, 1, // Opcode: LGG +/* 1674 */ MCD_OPC_FilterValue, 77, 9, 0, // Skip to: 1687 +/* 1678 */ MCD_OPC_CheckPredicate, 19, 1, 68, // Skip to: 19091 +/* 1682 */ MCD_OPC_Decode, 191, 10, 192, 1, // Opcode: LGSC +/* 1687 */ MCD_OPC_FilterValue, 80, 5, 0, // Skip to: 1696 +/* 1691 */ MCD_OPC_Decode, 144, 16, 196, 1, // Opcode: STY +/* 1696 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 1705 +/* 1700 */ MCD_OPC_Decode, 190, 13, 193, 1, // Opcode: MSY +/* 1705 */ MCD_OPC_FilterValue, 83, 9, 0, // Skip to: 1718 +/* 1709 */ MCD_OPC_CheckPredicate, 16, 226, 67, // Skip to: 19091 +/* 1713 */ MCD_OPC_Decode, 169, 13, 193, 1, // Opcode: MSC +/* 1718 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 1727 +/* 1722 */ MCD_OPC_Decode, 243, 13, 193, 1, // Opcode: NY +/* 1727 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 1736 +/* 1731 */ MCD_OPC_Decode, 204, 7, 196, 1, // Opcode: CLY +/* 1736 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 1745 +/* 1740 */ MCD_OPC_Decode, 131, 14, 193, 1, // Opcode: OY +/* 1745 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 1754 +/* 1749 */ MCD_OPC_Decode, 238, 21, 193, 1, // Opcode: XY +/* 1754 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 1763 +/* 1758 */ MCD_OPC_Decode, 244, 12, 196, 1, // Opcode: LY +/* 1763 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 1772 +/* 1767 */ MCD_OPC_Decode, 184, 8, 196, 1, // Opcode: CY +/* 1772 */ MCD_OPC_FilterValue, 90, 5, 0, // Skip to: 1781 +/* 1776 */ MCD_OPC_Decode, 164, 3, 193, 1, // Opcode: AY +/* 1781 */ MCD_OPC_FilterValue, 91, 5, 0, // Skip to: 1790 +/* 1785 */ MCD_OPC_Decode, 154, 16, 193, 1, // Opcode: SY +/* 1790 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 1799 +/* 1794 */ MCD_OPC_Decode, 154, 13, 195, 1, // Opcode: MFY +/* 1799 */ MCD_OPC_FilterValue, 94, 5, 0, // Skip to: 1808 +/* 1803 */ MCD_OPC_Decode, 151, 3, 193, 1, // Opcode: ALY +/* 1808 */ MCD_OPC_FilterValue, 95, 5, 0, // Skip to: 1817 +/* 1812 */ MCD_OPC_Decode, 241, 14, 193, 1, // Opcode: SLY +/* 1817 */ MCD_OPC_FilterValue, 112, 5, 0, // Skip to: 1826 +/* 1821 */ MCD_OPC_Decode, 186, 15, 196, 1, // Opcode: STHY +/* 1826 */ MCD_OPC_FilterValue, 113, 5, 0, // Skip to: 1835 +/* 1830 */ MCD_OPC_Decode, 255, 9, 192, 1, // Opcode: LAY +/* 1835 */ MCD_OPC_FilterValue, 114, 5, 0, // Skip to: 1844 +/* 1839 */ MCD_OPC_Decode, 171, 15, 196, 1, // Opcode: STCY +/* 1844 */ MCD_OPC_FilterValue, 115, 5, 0, // Skip to: 1853 +/* 1848 */ MCD_OPC_Decode, 134, 9, 194, 1, // Opcode: ICY +/* 1853 */ MCD_OPC_FilterValue, 117, 5, 0, // Skip to: 1862 +/* 1857 */ MCD_OPC_Decode, 243, 9, 192, 1, // Opcode: LAEY +/* 1862 */ MCD_OPC_FilterValue, 118, 5, 0, // Skip to: 1871 +/* 1866 */ MCD_OPC_Decode, 128, 10, 196, 1, // Opcode: LB +/* 1871 */ MCD_OPC_FilterValue, 119, 5, 0, // Skip to: 1880 +/* 1875 */ MCD_OPC_Decode, 177, 10, 192, 1, // Opcode: LGB +/* 1880 */ MCD_OPC_FilterValue, 120, 5, 0, // Skip to: 1889 +/* 1884 */ MCD_OPC_Decode, 197, 10, 196, 1, // Opcode: LHY +/* 1889 */ MCD_OPC_FilterValue, 121, 5, 0, // Skip to: 1898 +/* 1893 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: CHY +/* 1898 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 1907 +/* 1902 */ MCD_OPC_Decode, 255, 2, 193, 1, // Opcode: AHY +/* 1907 */ MCD_OPC_FilterValue, 123, 5, 0, // Skip to: 1916 +/* 1911 */ MCD_OPC_Decode, 211, 14, 193, 1, // Opcode: SHY +/* 1916 */ MCD_OPC_FilterValue, 124, 5, 0, // Skip to: 1925 +/* 1920 */ MCD_OPC_Decode, 161, 13, 193, 1, // Opcode: MHY +/* 1925 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 1935 +/* 1930 */ MCD_OPC_Decode, 228, 13, 194, 1, // Opcode: NG +/* 1935 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 1945 +/* 1940 */ MCD_OPC_Decode, 246, 13, 194, 1, // Opcode: OG +/* 1945 */ MCD_OPC_FilterValue, 130, 1, 5, 0, // Skip to: 1955 +/* 1950 */ MCD_OPC_Decode, 228, 21, 194, 1, // Opcode: XG +/* 1955 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 1969 +/* 1960 */ MCD_OPC_CheckPredicate, 16, 231, 66, // Skip to: 19091 +/* 1964 */ MCD_OPC_Decode, 181, 13, 194, 1, // Opcode: MSGC +/* 1969 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 1983 +/* 1974 */ MCD_OPC_CheckPredicate, 16, 217, 66, // Skip to: 19091 +/* 1978 */ MCD_OPC_Decode, 155, 13, 195, 1, // Opcode: MG +/* 1983 */ MCD_OPC_FilterValue, 133, 1, 9, 0, // Skip to: 1997 +/* 1988 */ MCD_OPC_CheckPredicate, 20, 203, 66, // Skip to: 19091 +/* 1992 */ MCD_OPC_Decode, 176, 10, 192, 1, // Opcode: LGAT +/* 1997 */ MCD_OPC_FilterValue, 134, 1, 5, 0, // Skip to: 2007 +/* 2002 */ MCD_OPC_Decode, 163, 13, 195, 1, // Opcode: MLG +/* 2007 */ MCD_OPC_FilterValue, 135, 1, 5, 0, // Skip to: 2017 +/* 2012 */ MCD_OPC_Decode, 202, 8, 195, 1, // Opcode: DLG +/* 2017 */ MCD_OPC_FilterValue, 136, 1, 5, 0, // Skip to: 2027 +/* 2022 */ MCD_OPC_Decode, 131, 3, 194, 1, // Opcode: ALCG +/* 2027 */ MCD_OPC_FilterValue, 137, 1, 5, 0, // Skip to: 2037 +/* 2032 */ MCD_OPC_Decode, 220, 14, 194, 1, // Opcode: SLBG +/* 2037 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 2047 +/* 2042 */ MCD_OPC_Decode, 132, 16, 199, 1, // Opcode: STPQ +/* 2047 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 2057 +/* 2052 */ MCD_OPC_Decode, 195, 12, 199, 1, // Opcode: LPQ +/* 2057 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 2067 +/* 2062 */ MCD_OPC_Decode, 201, 10, 192, 1, // Opcode: LLGC +/* 2067 */ MCD_OPC_FilterValue, 145, 1, 5, 0, // Skip to: 2077 +/* 2072 */ MCD_OPC_Decode, 208, 10, 192, 1, // Opcode: LLGH +/* 2077 */ MCD_OPC_FilterValue, 148, 1, 5, 0, // Skip to: 2087 +/* 2082 */ MCD_OPC_Decode, 198, 10, 196, 1, // Opcode: LLC +/* 2087 */ MCD_OPC_FilterValue, 149, 1, 5, 0, // Skip to: 2097 +/* 2092 */ MCD_OPC_Decode, 214, 10, 196, 1, // Opcode: LLH +/* 2097 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 2107 +/* 2102 */ MCD_OPC_Decode, 162, 13, 195, 1, // Opcode: ML +/* 2107 */ MCD_OPC_FilterValue, 151, 1, 5, 0, // Skip to: 2117 +/* 2112 */ MCD_OPC_Decode, 201, 8, 195, 1, // Opcode: DL +/* 2117 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 2127 +/* 2122 */ MCD_OPC_Decode, 130, 3, 193, 1, // Opcode: ALC +/* 2127 */ MCD_OPC_FilterValue, 153, 1, 5, 0, // Skip to: 2137 +/* 2132 */ MCD_OPC_Decode, 219, 14, 193, 1, // Opcode: SLB +/* 2137 */ MCD_OPC_FilterValue, 156, 1, 9, 0, // Skip to: 2151 +/* 2142 */ MCD_OPC_CheckPredicate, 20, 49, 66, // Skip to: 19091 +/* 2146 */ MCD_OPC_Decode, 212, 10, 192, 1, // Opcode: LLGTAT +/* 2151 */ MCD_OPC_FilterValue, 157, 1, 9, 0, // Skip to: 2165 +/* 2156 */ MCD_OPC_CheckPredicate, 20, 35, 66, // Skip to: 19091 +/* 2160 */ MCD_OPC_Decode, 204, 10, 192, 1, // Opcode: LLGFAT +/* 2165 */ MCD_OPC_FilterValue, 159, 1, 9, 0, // Skip to: 2179 +/* 2170 */ MCD_OPC_CheckPredicate, 20, 21, 66, // Skip to: 19091 +/* 2174 */ MCD_OPC_Decode, 252, 9, 196, 1, // Opcode: LAT +/* 2179 */ MCD_OPC_FilterValue, 192, 1, 9, 0, // Skip to: 2193 +/* 2184 */ MCD_OPC_CheckPredicate, 11, 7, 66, // Skip to: 19091 +/* 2188 */ MCD_OPC_Decode, 129, 10, 200, 1, // Opcode: LBH +/* 2193 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 2207 +/* 2198 */ MCD_OPC_CheckPredicate, 11, 249, 65, // Skip to: 19091 +/* 2202 */ MCD_OPC_Decode, 199, 10, 200, 1, // Opcode: LLCH +/* 2207 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 2221 +/* 2212 */ MCD_OPC_CheckPredicate, 11, 235, 65, // Skip to: 19091 +/* 2216 */ MCD_OPC_Decode, 159, 15, 200, 1, // Opcode: STCH +/* 2221 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 2235 +/* 2226 */ MCD_OPC_CheckPredicate, 11, 221, 65, // Skip to: 19091 +/* 2230 */ MCD_OPC_Decode, 193, 10, 200, 1, // Opcode: LHH +/* 2235 */ MCD_OPC_FilterValue, 198, 1, 9, 0, // Skip to: 2249 +/* 2240 */ MCD_OPC_CheckPredicate, 11, 207, 65, // Skip to: 19091 +/* 2244 */ MCD_OPC_Decode, 215, 10, 200, 1, // Opcode: LLHH +/* 2249 */ MCD_OPC_FilterValue, 199, 1, 9, 0, // Skip to: 2263 +/* 2254 */ MCD_OPC_CheckPredicate, 11, 193, 65, // Skip to: 19091 +/* 2258 */ MCD_OPC_Decode, 184, 15, 200, 1, // Opcode: STHH +/* 2263 */ MCD_OPC_FilterValue, 200, 1, 9, 0, // Skip to: 2277 +/* 2268 */ MCD_OPC_CheckPredicate, 20, 179, 65, // Skip to: 19091 +/* 2272 */ MCD_OPC_Decode, 173, 10, 200, 1, // Opcode: LFHAT +/* 2277 */ MCD_OPC_FilterValue, 202, 1, 9, 0, // Skip to: 2291 +/* 2282 */ MCD_OPC_CheckPredicate, 11, 165, 65, // Skip to: 19091 +/* 2286 */ MCD_OPC_Decode, 172, 10, 200, 1, // Opcode: LFH +/* 2291 */ MCD_OPC_FilterValue, 203, 1, 9, 0, // Skip to: 2305 +/* 2296 */ MCD_OPC_CheckPredicate, 11, 151, 65, // Skip to: 19091 +/* 2300 */ MCD_OPC_Decode, 176, 15, 200, 1, // Opcode: STFH +/* 2305 */ MCD_OPC_FilterValue, 205, 1, 9, 0, // Skip to: 2319 +/* 2310 */ MCD_OPC_CheckPredicate, 11, 137, 65, // Skip to: 19091 +/* 2314 */ MCD_OPC_Decode, 172, 5, 200, 1, // Opcode: CHF +/* 2319 */ MCD_OPC_FilterValue, 207, 1, 127, 65, // Skip to: 19091 +/* 2324 */ MCD_OPC_CheckPredicate, 11, 123, 65, // Skip to: 19091 +/* 2328 */ MCD_OPC_Decode, 234, 6, 200, 1, // Opcode: CLHF +/* 2333 */ MCD_OPC_FilterValue, 229, 1, 155, 0, // Skip to: 2493 +/* 2338 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... +/* 2341 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 2350 +/* 2345 */ MCD_OPC_Decode, 251, 9, 201, 1, // Opcode: LASP +/* 2350 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 2359 +/* 2354 */ MCD_OPC_Decode, 183, 16, 201, 1, // Opcode: TPROT +/* 2359 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 2368 +/* 2363 */ MCD_OPC_Decode, 135, 16, 201, 1, // Opcode: STRAG +/* 2368 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 2377 +/* 2372 */ MCD_OPC_Decode, 201, 13, 201, 1, // Opcode: MVCSK +/* 2377 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 2386 +/* 2381 */ MCD_OPC_Decode, 192, 13, 201, 1, // Opcode: MVCDK +/* 2386 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 2395 +/* 2390 */ MCD_OPC_Decode, 203, 13, 202, 1, // Opcode: MVHHI +/* 2395 */ MCD_OPC_FilterValue, 72, 5, 0, // Skip to: 2404 +/* 2399 */ MCD_OPC_Decode, 202, 13, 202, 1, // Opcode: MVGHI +/* 2404 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 2413 +/* 2408 */ MCD_OPC_Decode, 204, 13, 202, 1, // Opcode: MVHI +/* 2413 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 2422 +/* 2417 */ MCD_OPC_Decode, 174, 5, 202, 1, // Opcode: CHHSI +/* 2422 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 2431 +/* 2426 */ MCD_OPC_Decode, 236, 6, 203, 1, // Opcode: CLHHSI +/* 2431 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 2440 +/* 2435 */ MCD_OPC_Decode, 207, 4, 202, 1, // Opcode: CGHSI +/* 2440 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 2449 +/* 2444 */ MCD_OPC_Decode, 131, 6, 203, 1, // Opcode: CLGHSI +/* 2449 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 2458 +/* 2453 */ MCD_OPC_Decode, 178, 5, 202, 1, // Opcode: CHSI +/* 2458 */ MCD_OPC_FilterValue, 93, 5, 0, // Skip to: 2467 +/* 2462 */ MCD_OPC_Decode, 232, 5, 203, 1, // Opcode: CLFHSI +/* 2467 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 2480 +/* 2471 */ MCD_OPC_CheckPredicate, 2, 232, 64, // Skip to: 19091 +/* 2475 */ MCD_OPC_Decode, 161, 16, 203, 1, // Opcode: TBEGIN +/* 2480 */ MCD_OPC_FilterValue, 97, 223, 64, // Skip to: 19091 +/* 2484 */ MCD_OPC_CheckPredicate, 2, 219, 64, // Skip to: 19091 +/* 2488 */ MCD_OPC_Decode, 162, 16, 203, 1, // Opcode: TBEGINC +/* 2493 */ MCD_OPC_FilterValue, 230, 1, 35, 2, // Skip to: 3045 +/* 2498 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 2501 */ MCD_OPC_FilterValue, 52, 15, 0, // Skip to: 2520 +/* 2505 */ MCD_OPC_CheckPredicate, 21, 198, 64, // Skip to: 19091 +/* 2509 */ MCD_OPC_CheckField, 9, 3, 0, 192, 64, // Skip to: 19091 +/* 2515 */ MCD_OPC_Decode, 146, 20, 204, 1, // Opcode: VPKZ +/* 2520 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 2539 +/* 2524 */ MCD_OPC_CheckPredicate, 21, 179, 64, // Skip to: 19091 +/* 2528 */ MCD_OPC_CheckField, 9, 3, 0, 173, 64, // Skip to: 19091 +/* 2534 */ MCD_OPC_Decode, 148, 19, 204, 1, // Opcode: VLRL +/* 2539 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 2564 +/* 2543 */ MCD_OPC_CheckPredicate, 21, 160, 64, // Skip to: 19091 +/* 2547 */ MCD_OPC_CheckField, 36, 4, 0, 154, 64, // Skip to: 19091 +/* 2553 */ MCD_OPC_CheckField, 9, 3, 0, 148, 64, // Skip to: 19091 +/* 2559 */ MCD_OPC_Decode, 149, 19, 205, 1, // Opcode: VLRLR +/* 2564 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 2583 +/* 2568 */ MCD_OPC_CheckPredicate, 21, 135, 64, // Skip to: 19091 +/* 2572 */ MCD_OPC_CheckField, 9, 3, 0, 129, 64, // Skip to: 19091 +/* 2578 */ MCD_OPC_Decode, 234, 20, 204, 1, // Opcode: VUPKZ +/* 2583 */ MCD_OPC_FilterValue, 61, 15, 0, // Skip to: 2602 +/* 2587 */ MCD_OPC_CheckPredicate, 21, 116, 64, // Skip to: 19091 +/* 2591 */ MCD_OPC_CheckField, 9, 3, 0, 110, 64, // Skip to: 19091 +/* 2597 */ MCD_OPC_Decode, 217, 20, 204, 1, // Opcode: VSTRL +/* 2602 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 2627 +/* 2606 */ MCD_OPC_CheckPredicate, 21, 97, 64, // Skip to: 19091 +/* 2610 */ MCD_OPC_CheckField, 36, 4, 0, 91, 64, // Skip to: 19091 +/* 2616 */ MCD_OPC_CheckField, 9, 3, 0, 85, 64, // Skip to: 19091 +/* 2622 */ MCD_OPC_Decode, 218, 20, 205, 1, // Opcode: VSTRLR +/* 2627 */ MCD_OPC_FilterValue, 73, 21, 0, // Skip to: 2652 +/* 2631 */ MCD_OPC_CheckPredicate, 21, 72, 64, // Skip to: 19091 +/* 2635 */ MCD_OPC_CheckField, 32, 4, 0, 66, 64, // Skip to: 19091 +/* 2641 */ MCD_OPC_CheckField, 8, 3, 0, 60, 64, // Skip to: 19091 +/* 2647 */ MCD_OPC_Decode, 128, 19, 206, 1, // Opcode: VLIP +/* 2652 */ MCD_OPC_FilterValue, 80, 27, 0, // Skip to: 2683 +/* 2656 */ MCD_OPC_CheckPredicate, 21, 47, 64, // Skip to: 19091 +/* 2660 */ MCD_OPC_CheckField, 24, 8, 0, 41, 64, // Skip to: 19091 +/* 2666 */ MCD_OPC_CheckField, 11, 9, 0, 35, 64, // Skip to: 19091 +/* 2672 */ MCD_OPC_CheckField, 8, 2, 0, 29, 64, // Skip to: 19091 +/* 2678 */ MCD_OPC_Decode, 157, 17, 207, 1, // Opcode: VCVB +/* 2683 */ MCD_OPC_FilterValue, 82, 27, 0, // Skip to: 2714 +/* 2687 */ MCD_OPC_CheckPredicate, 21, 16, 64, // Skip to: 19091 +/* 2691 */ MCD_OPC_CheckField, 24, 8, 0, 10, 64, // Skip to: 19091 +/* 2697 */ MCD_OPC_CheckField, 11, 9, 0, 4, 64, // Skip to: 19091 +/* 2703 */ MCD_OPC_CheckField, 8, 2, 0, 254, 63, // Skip to: 19091 +/* 2709 */ MCD_OPC_Decode, 158, 17, 208, 1, // Opcode: VCVBG +/* 2714 */ MCD_OPC_FilterValue, 88, 21, 0, // Skip to: 2739 +/* 2718 */ MCD_OPC_CheckPredicate, 21, 241, 63, // Skip to: 19091 +/* 2722 */ MCD_OPC_CheckField, 24, 8, 0, 235, 63, // Skip to: 19091 +/* 2728 */ MCD_OPC_CheckField, 8, 3, 0, 229, 63, // Skip to: 19091 +/* 2734 */ MCD_OPC_Decode, 159, 17, 209, 1, // Opcode: VCVD +/* 2739 */ MCD_OPC_FilterValue, 89, 15, 0, // Skip to: 2758 +/* 2743 */ MCD_OPC_CheckPredicate, 21, 216, 63, // Skip to: 19091 +/* 2747 */ MCD_OPC_CheckField, 8, 2, 0, 210, 63, // Skip to: 19091 +/* 2753 */ MCD_OPC_Decode, 196, 20, 210, 1, // Opcode: VSRP +/* 2758 */ MCD_OPC_FilterValue, 90, 21, 0, // Skip to: 2783 +/* 2762 */ MCD_OPC_CheckPredicate, 21, 197, 63, // Skip to: 19091 +/* 2766 */ MCD_OPC_CheckField, 24, 8, 0, 191, 63, // Skip to: 19091 +/* 2772 */ MCD_OPC_CheckField, 8, 3, 0, 185, 63, // Skip to: 19091 +/* 2778 */ MCD_OPC_Decode, 160, 17, 211, 1, // Opcode: VCVDG +/* 2783 */ MCD_OPC_FilterValue, 91, 15, 0, // Skip to: 2802 +/* 2787 */ MCD_OPC_CheckPredicate, 21, 172, 63, // Skip to: 19091 +/* 2791 */ MCD_OPC_CheckField, 8, 2, 0, 166, 63, // Skip to: 19091 +/* 2797 */ MCD_OPC_Decode, 152, 20, 210, 1, // Opcode: VPSOP +/* 2802 */ MCD_OPC_FilterValue, 95, 27, 0, // Skip to: 2833 +/* 2806 */ MCD_OPC_CheckPredicate, 21, 153, 63, // Skip to: 19091 +/* 2810 */ MCD_OPC_CheckField, 36, 4, 0, 147, 63, // Skip to: 19091 +/* 2816 */ MCD_OPC_CheckField, 11, 21, 0, 141, 63, // Skip to: 19091 +/* 2822 */ MCD_OPC_CheckField, 8, 2, 0, 135, 63, // Skip to: 19091 +/* 2828 */ MCD_OPC_Decode, 229, 20, 212, 1, // Opcode: VTP +/* 2833 */ MCD_OPC_FilterValue, 113, 21, 0, // Skip to: 2858 +/* 2837 */ MCD_OPC_CheckPredicate, 21, 122, 63, // Skip to: 19091 +/* 2841 */ MCD_OPC_CheckField, 24, 4, 0, 116, 63, // Skip to: 19091 +/* 2847 */ MCD_OPC_CheckField, 8, 1, 0, 110, 63, // Skip to: 19091 +/* 2853 */ MCD_OPC_Decode, 225, 16, 213, 1, // Opcode: VAP +/* 2858 */ MCD_OPC_FilterValue, 115, 21, 0, // Skip to: 2883 +/* 2862 */ MCD_OPC_CheckPredicate, 21, 97, 63, // Skip to: 19091 +/* 2866 */ MCD_OPC_CheckField, 24, 4, 0, 91, 63, // Skip to: 19091 +/* 2872 */ MCD_OPC_CheckField, 8, 1, 0, 85, 63, // Skip to: 19091 +/* 2878 */ MCD_OPC_Decode, 190, 20, 213, 1, // Opcode: VSP +/* 2883 */ MCD_OPC_FilterValue, 119, 33, 0, // Skip to: 2920 +/* 2887 */ MCD_OPC_CheckPredicate, 21, 72, 63, // Skip to: 19091 +/* 2891 */ MCD_OPC_CheckField, 36, 4, 0, 66, 63, // Skip to: 19091 +/* 2897 */ MCD_OPC_CheckField, 24, 4, 0, 60, 63, // Skip to: 19091 +/* 2903 */ MCD_OPC_CheckField, 11, 9, 0, 54, 63, // Skip to: 19091 +/* 2909 */ MCD_OPC_CheckField, 8, 1, 0, 48, 63, // Skip to: 19091 +/* 2915 */ MCD_OPC_Decode, 151, 17, 214, 1, // Opcode: VCP +/* 2920 */ MCD_OPC_FilterValue, 120, 21, 0, // Skip to: 2945 +/* 2924 */ MCD_OPC_CheckPredicate, 21, 35, 63, // Skip to: 19091 +/* 2928 */ MCD_OPC_CheckField, 24, 4, 0, 29, 63, // Skip to: 19091 +/* 2934 */ MCD_OPC_CheckField, 8, 1, 0, 23, 63, // Skip to: 19091 +/* 2940 */ MCD_OPC_Decode, 222, 19, 213, 1, // Opcode: VMP +/* 2945 */ MCD_OPC_FilterValue, 121, 21, 0, // Skip to: 2970 +/* 2949 */ MCD_OPC_CheckPredicate, 21, 10, 63, // Skip to: 19091 +/* 2953 */ MCD_OPC_CheckField, 24, 4, 0, 4, 63, // Skip to: 19091 +/* 2959 */ MCD_OPC_CheckField, 8, 1, 0, 254, 62, // Skip to: 19091 +/* 2965 */ MCD_OPC_Decode, 235, 19, 213, 1, // Opcode: VMSP +/* 2970 */ MCD_OPC_FilterValue, 122, 21, 0, // Skip to: 2995 +/* 2974 */ MCD_OPC_CheckPredicate, 21, 241, 62, // Skip to: 19091 +/* 2978 */ MCD_OPC_CheckField, 24, 4, 0, 235, 62, // Skip to: 19091 +/* 2984 */ MCD_OPC_CheckField, 8, 1, 0, 229, 62, // Skip to: 19091 +/* 2990 */ MCD_OPC_Decode, 161, 17, 213, 1, // Opcode: VDP +/* 2995 */ MCD_OPC_FilterValue, 123, 21, 0, // Skip to: 3020 +/* 2999 */ MCD_OPC_CheckPredicate, 21, 216, 62, // Skip to: 19091 +/* 3003 */ MCD_OPC_CheckField, 24, 4, 0, 210, 62, // Skip to: 19091 +/* 3009 */ MCD_OPC_CheckField, 8, 1, 0, 204, 62, // Skip to: 19091 +/* 3015 */ MCD_OPC_Decode, 163, 20, 213, 1, // Opcode: VRP +/* 3020 */ MCD_OPC_FilterValue, 126, 195, 62, // Skip to: 19091 +/* 3024 */ MCD_OPC_CheckPredicate, 21, 191, 62, // Skip to: 19091 +/* 3028 */ MCD_OPC_CheckField, 24, 4, 0, 185, 62, // Skip to: 19091 +/* 3034 */ MCD_OPC_CheckField, 8, 1, 0, 179, 62, // Skip to: 19091 +/* 3040 */ MCD_OPC_Decode, 178, 20, 213, 1, // Opcode: VSDP +/* 3045 */ MCD_OPC_FilterValue, 231, 1, 216, 41, // Skip to: 13762 +/* 3050 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 3053 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3072 +/* 3057 */ MCD_OPC_CheckPredicate, 22, 158, 62, // Skip to: 19091 +/* 3061 */ MCD_OPC_CheckField, 8, 3, 0, 152, 62, // Skip to: 19091 +/* 3067 */ MCD_OPC_Decode, 241, 18, 215, 1, // Opcode: VLEB +/* 3072 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 3091 +/* 3076 */ MCD_OPC_CheckPredicate, 22, 139, 62, // Skip to: 19091 +/* 3080 */ MCD_OPC_CheckField, 8, 3, 0, 133, 62, // Skip to: 19091 +/* 3086 */ MCD_OPC_Decode, 246, 18, 216, 1, // Opcode: VLEH +/* 3091 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3110 +/* 3095 */ MCD_OPC_CheckPredicate, 22, 120, 62, // Skip to: 19091 +/* 3099 */ MCD_OPC_CheckField, 8, 3, 0, 114, 62, // Skip to: 19091 +/* 3105 */ MCD_OPC_Decode, 245, 18, 217, 1, // Opcode: VLEG +/* 3110 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 3129 +/* 3114 */ MCD_OPC_CheckPredicate, 22, 101, 62, // Skip to: 19091 +/* 3118 */ MCD_OPC_CheckField, 8, 3, 0, 95, 62, // Skip to: 19091 +/* 3124 */ MCD_OPC_Decode, 244, 18, 218, 1, // Opcode: VLEF +/* 3129 */ MCD_OPC_FilterValue, 4, 84, 0, // Skip to: 3217 +/* 3133 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3136 */ MCD_OPC_FilterValue, 0, 79, 62, // Skip to: 19091 +/* 3140 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3156 +/* 3147 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 3208 +/* 3151 */ MCD_OPC_Decode, 131, 19, 219, 1, // Opcode: VLLEZB +/* 3156 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3169 +/* 3160 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3208 +/* 3164 */ MCD_OPC_Decode, 134, 19, 219, 1, // Opcode: VLLEZH +/* 3169 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3182 +/* 3173 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3208 +/* 3177 */ MCD_OPC_Decode, 132, 19, 219, 1, // Opcode: VLLEZF +/* 3182 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3195 +/* 3186 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3208 +/* 3190 */ MCD_OPC_Decode, 133, 19, 219, 1, // Opcode: VLLEZG +/* 3195 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 3208 +/* 3199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 3208 +/* 3203 */ MCD_OPC_Decode, 135, 19, 219, 1, // Opcode: VLLEZLF +/* 3208 */ MCD_OPC_CheckPredicate, 22, 7, 62, // Skip to: 19091 +/* 3212 */ MCD_OPC_Decode, 130, 19, 220, 1, // Opcode: VLLEZ +/* 3217 */ MCD_OPC_FilterValue, 5, 71, 0, // Skip to: 3292 +/* 3221 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3224 */ MCD_OPC_FilterValue, 0, 247, 61, // Skip to: 19091 +/* 3228 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3231 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3244 +/* 3235 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3283 +/* 3239 */ MCD_OPC_Decode, 144, 19, 219, 1, // Opcode: VLREPB +/* 3244 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3257 +/* 3248 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3283 +/* 3252 */ MCD_OPC_Decode, 147, 19, 219, 1, // Opcode: VLREPH +/* 3257 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3270 +/* 3261 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3283 +/* 3265 */ MCD_OPC_Decode, 145, 19, 219, 1, // Opcode: VLREPF +/* 3270 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3283 +/* 3274 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3283 +/* 3278 */ MCD_OPC_Decode, 146, 19, 219, 1, // Opcode: VLREPG +/* 3283 */ MCD_OPC_CheckPredicate, 22, 188, 61, // Skip to: 19091 +/* 3287 */ MCD_OPC_Decode, 143, 19, 220, 1, // Opcode: VLREP +/* 3292 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 3317 +/* 3296 */ MCD_OPC_CheckPredicate, 22, 175, 61, // Skip to: 19091 +/* 3300 */ MCD_OPC_CheckField, 12, 4, 0, 169, 61, // Skip to: 19091 +/* 3306 */ MCD_OPC_CheckField, 8, 3, 0, 163, 61, // Skip to: 19091 +/* 3312 */ MCD_OPC_Decode, 232, 18, 219, 1, // Opcode: VL +/* 3317 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 3336 +/* 3321 */ MCD_OPC_CheckPredicate, 22, 150, 61, // Skip to: 19091 +/* 3325 */ MCD_OPC_CheckField, 8, 3, 0, 144, 61, // Skip to: 19091 +/* 3331 */ MCD_OPC_Decode, 233, 18, 220, 1, // Opcode: VLBB +/* 3336 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 3355 +/* 3340 */ MCD_OPC_CheckPredicate, 22, 131, 61, // Skip to: 19091 +/* 3344 */ MCD_OPC_CheckField, 8, 3, 0, 125, 61, // Skip to: 19091 +/* 3350 */ MCD_OPC_Decode, 198, 20, 220, 1, // Opcode: VSTEB +/* 3355 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 3374 +/* 3359 */ MCD_OPC_CheckPredicate, 22, 112, 61, // Skip to: 19091 +/* 3363 */ MCD_OPC_CheckField, 8, 3, 0, 106, 61, // Skip to: 19091 +/* 3369 */ MCD_OPC_Decode, 201, 20, 221, 1, // Opcode: VSTEH +/* 3374 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 3393 +/* 3378 */ MCD_OPC_CheckPredicate, 22, 93, 61, // Skip to: 19091 +/* 3382 */ MCD_OPC_CheckField, 8, 3, 0, 87, 61, // Skip to: 19091 +/* 3388 */ MCD_OPC_Decode, 200, 20, 222, 1, // Opcode: VSTEG +/* 3393 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 3412 +/* 3397 */ MCD_OPC_CheckPredicate, 22, 74, 61, // Skip to: 19091 +/* 3401 */ MCD_OPC_CheckField, 8, 3, 0, 68, 61, // Skip to: 19091 +/* 3407 */ MCD_OPC_Decode, 199, 20, 223, 1, // Opcode: VSTEF +/* 3412 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 3437 +/* 3416 */ MCD_OPC_CheckPredicate, 22, 55, 61, // Skip to: 19091 +/* 3420 */ MCD_OPC_CheckField, 12, 4, 0, 49, 61, // Skip to: 19091 +/* 3426 */ MCD_OPC_CheckField, 8, 3, 0, 43, 61, // Skip to: 19091 +/* 3432 */ MCD_OPC_Decode, 197, 20, 219, 1, // Opcode: VST +/* 3437 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 3456 +/* 3441 */ MCD_OPC_CheckPredicate, 22, 30, 61, // Skip to: 19091 +/* 3445 */ MCD_OPC_CheckField, 8, 2, 0, 24, 61, // Skip to: 19091 +/* 3451 */ MCD_OPC_Decode, 209, 18, 224, 1, // Opcode: VGEG +/* 3456 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 3475 +/* 3460 */ MCD_OPC_CheckPredicate, 22, 11, 61, // Skip to: 19091 +/* 3464 */ MCD_OPC_CheckField, 8, 2, 0, 5, 61, // Skip to: 19091 +/* 3470 */ MCD_OPC_Decode, 208, 18, 225, 1, // Opcode: VGEF +/* 3475 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 3494 +/* 3479 */ MCD_OPC_CheckPredicate, 22, 248, 60, // Skip to: 19091 +/* 3483 */ MCD_OPC_CheckField, 8, 2, 0, 242, 60, // Skip to: 19091 +/* 3489 */ MCD_OPC_Decode, 177, 20, 226, 1, // Opcode: VSCEG +/* 3494 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 3513 +/* 3498 */ MCD_OPC_CheckPredicate, 22, 229, 60, // Skip to: 19091 +/* 3502 */ MCD_OPC_CheckField, 8, 2, 0, 223, 60, // Skip to: 19091 +/* 3508 */ MCD_OPC_Decode, 176, 20, 227, 1, // Opcode: VSCEF +/* 3513 */ MCD_OPC_FilterValue, 33, 78, 0, // Skip to: 3595 +/* 3517 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3520 */ MCD_OPC_FilterValue, 0, 207, 60, // Skip to: 19091 +/* 3524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 3527 */ MCD_OPC_FilterValue, 0, 200, 60, // Skip to: 19091 +/* 3531 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3534 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3547 +/* 3538 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3586 +/* 3542 */ MCD_OPC_Decode, 252, 18, 228, 1, // Opcode: VLGVB +/* 3547 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3560 +/* 3551 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3586 +/* 3555 */ MCD_OPC_Decode, 255, 18, 228, 1, // Opcode: VLGVH +/* 3560 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3573 +/* 3564 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3586 +/* 3568 */ MCD_OPC_Decode, 253, 18, 228, 1, // Opcode: VLGVF +/* 3573 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3586 +/* 3577 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3586 +/* 3581 */ MCD_OPC_Decode, 254, 18, 228, 1, // Opcode: VLGVG +/* 3586 */ MCD_OPC_CheckPredicate, 22, 141, 60, // Skip to: 19091 +/* 3590 */ MCD_OPC_Decode, 251, 18, 229, 1, // Opcode: VLGV +/* 3595 */ MCD_OPC_FilterValue, 34, 71, 0, // Skip to: 3670 +/* 3599 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 3602 */ MCD_OPC_FilterValue, 0, 125, 60, // Skip to: 19091 +/* 3606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3609 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3622 +/* 3613 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3661 +/* 3617 */ MCD_OPC_Decode, 151, 19, 230, 1, // Opcode: VLVGB +/* 3622 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3635 +/* 3626 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3661 +/* 3630 */ MCD_OPC_Decode, 154, 19, 230, 1, // Opcode: VLVGH +/* 3635 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3648 +/* 3639 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3661 +/* 3643 */ MCD_OPC_Decode, 152, 19, 230, 1, // Opcode: VLVGF +/* 3648 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3661 +/* 3652 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3661 +/* 3656 */ MCD_OPC_Decode, 153, 19, 231, 1, // Opcode: VLVGG +/* 3661 */ MCD_OPC_CheckPredicate, 22, 66, 60, // Skip to: 19091 +/* 3665 */ MCD_OPC_Decode, 150, 19, 232, 1, // Opcode: VLVG +/* 3670 */ MCD_OPC_FilterValue, 39, 15, 0, // Skip to: 3689 +/* 3674 */ MCD_OPC_CheckPredicate, 22, 53, 60, // Skip to: 19091 +/* 3678 */ MCD_OPC_CheckField, 8, 4, 0, 47, 60, // Skip to: 19091 +/* 3684 */ MCD_OPC_Decode, 131, 10, 233, 1, // Opcode: LCBB +/* 3689 */ MCD_OPC_FilterValue, 48, 71, 0, // Skip to: 3764 +/* 3693 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3696 */ MCD_OPC_FilterValue, 0, 31, 60, // Skip to: 19091 +/* 3700 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3703 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3716 +/* 3707 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3755 +/* 3711 */ MCD_OPC_Decode, 188, 17, 234, 1, // Opcode: VESLB +/* 3716 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3729 +/* 3720 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3755 +/* 3724 */ MCD_OPC_Decode, 191, 17, 234, 1, // Opcode: VESLH +/* 3729 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3742 +/* 3733 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3755 +/* 3737 */ MCD_OPC_Decode, 189, 17, 234, 1, // Opcode: VESLF +/* 3742 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3755 +/* 3746 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3755 +/* 3750 */ MCD_OPC_Decode, 190, 17, 234, 1, // Opcode: VESLG +/* 3755 */ MCD_OPC_CheckPredicate, 22, 228, 59, // Skip to: 19091 +/* 3759 */ MCD_OPC_Decode, 187, 17, 235, 1, // Opcode: VESL +/* 3764 */ MCD_OPC_FilterValue, 51, 71, 0, // Skip to: 3839 +/* 3768 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3771 */ MCD_OPC_FilterValue, 0, 212, 59, // Skip to: 19091 +/* 3775 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3778 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3791 +/* 3782 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3830 +/* 3786 */ MCD_OPC_Decode, 178, 17, 234, 1, // Opcode: VERLLB +/* 3791 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3804 +/* 3795 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3830 +/* 3799 */ MCD_OPC_Decode, 181, 17, 234, 1, // Opcode: VERLLH +/* 3804 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3817 +/* 3808 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3830 +/* 3812 */ MCD_OPC_Decode, 179, 17, 234, 1, // Opcode: VERLLF +/* 3817 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3830 +/* 3821 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3830 +/* 3825 */ MCD_OPC_Decode, 180, 17, 234, 1, // Opcode: VERLLG +/* 3830 */ MCD_OPC_CheckPredicate, 22, 153, 59, // Skip to: 19091 +/* 3834 */ MCD_OPC_Decode, 177, 17, 235, 1, // Opcode: VERLL +/* 3839 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 3864 +/* 3843 */ MCD_OPC_CheckPredicate, 22, 140, 59, // Skip to: 19091 +/* 3847 */ MCD_OPC_CheckField, 12, 4, 0, 134, 59, // Skip to: 19091 +/* 3853 */ MCD_OPC_CheckField, 8, 2, 0, 128, 59, // Skip to: 19091 +/* 3859 */ MCD_OPC_Decode, 136, 19, 236, 1, // Opcode: VLM +/* 3864 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 3889 +/* 3868 */ MCD_OPC_CheckPredicate, 22, 115, 59, // Skip to: 19091 +/* 3872 */ MCD_OPC_CheckField, 12, 4, 0, 109, 59, // Skip to: 19091 +/* 3878 */ MCD_OPC_CheckField, 8, 3, 0, 103, 59, // Skip to: 19091 +/* 3884 */ MCD_OPC_Decode, 129, 19, 237, 1, // Opcode: VLL +/* 3889 */ MCD_OPC_FilterValue, 56, 71, 0, // Skip to: 3964 +/* 3893 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3896 */ MCD_OPC_FilterValue, 0, 87, 59, // Skip to: 19091 +/* 3900 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3903 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3916 +/* 3907 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3955 +/* 3911 */ MCD_OPC_Decode, 208, 17, 234, 1, // Opcode: VESRLB +/* 3916 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3929 +/* 3920 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3955 +/* 3924 */ MCD_OPC_Decode, 211, 17, 234, 1, // Opcode: VESRLH +/* 3929 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3942 +/* 3933 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3955 +/* 3937 */ MCD_OPC_Decode, 209, 17, 234, 1, // Opcode: VESRLF +/* 3942 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3955 +/* 3946 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3955 +/* 3950 */ MCD_OPC_Decode, 210, 17, 234, 1, // Opcode: VESRLG +/* 3955 */ MCD_OPC_CheckPredicate, 22, 28, 59, // Skip to: 19091 +/* 3959 */ MCD_OPC_Decode, 207, 17, 235, 1, // Opcode: VESRL +/* 3964 */ MCD_OPC_FilterValue, 58, 71, 0, // Skip to: 4039 +/* 3968 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 3971 */ MCD_OPC_FilterValue, 0, 12, 59, // Skip to: 19091 +/* 3975 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3978 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3991 +/* 3982 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4030 +/* 3986 */ MCD_OPC_Decode, 198, 17, 234, 1, // Opcode: VESRAB +/* 3991 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4004 +/* 3995 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4030 +/* 3999 */ MCD_OPC_Decode, 201, 17, 234, 1, // Opcode: VESRAH +/* 4004 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4017 +/* 4008 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4030 +/* 4012 */ MCD_OPC_Decode, 199, 17, 234, 1, // Opcode: VESRAF +/* 4017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4030 +/* 4021 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4030 +/* 4025 */ MCD_OPC_Decode, 200, 17, 234, 1, // Opcode: VESRAG +/* 4030 */ MCD_OPC_CheckPredicate, 22, 209, 58, // Skip to: 19091 +/* 4034 */ MCD_OPC_Decode, 197, 17, 235, 1, // Opcode: VESRA +/* 4039 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 4064 +/* 4043 */ MCD_OPC_CheckPredicate, 22, 196, 58, // Skip to: 19091 +/* 4047 */ MCD_OPC_CheckField, 12, 4, 0, 190, 58, // Skip to: 19091 +/* 4053 */ MCD_OPC_CheckField, 8, 2, 0, 184, 58, // Skip to: 19091 +/* 4059 */ MCD_OPC_Decode, 203, 20, 236, 1, // Opcode: VSTM +/* 4064 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 4089 +/* 4068 */ MCD_OPC_CheckPredicate, 22, 171, 58, // Skip to: 19091 +/* 4072 */ MCD_OPC_CheckField, 12, 4, 0, 165, 58, // Skip to: 19091 +/* 4078 */ MCD_OPC_CheckField, 8, 3, 0, 159, 58, // Skip to: 19091 +/* 4084 */ MCD_OPC_Decode, 202, 20, 237, 1, // Opcode: VSTL +/* 4089 */ MCD_OPC_FilterValue, 64, 21, 0, // Skip to: 4114 +/* 4093 */ MCD_OPC_CheckPredicate, 22, 146, 58, // Skip to: 19091 +/* 4097 */ MCD_OPC_CheckField, 32, 4, 0, 140, 58, // Skip to: 19091 +/* 4103 */ MCD_OPC_CheckField, 8, 3, 0, 134, 58, // Skip to: 19091 +/* 4109 */ MCD_OPC_Decode, 247, 18, 238, 1, // Opcode: VLEIB +/* 4114 */ MCD_OPC_FilterValue, 65, 21, 0, // Skip to: 4139 +/* 4118 */ MCD_OPC_CheckPredicate, 22, 121, 58, // Skip to: 19091 +/* 4122 */ MCD_OPC_CheckField, 32, 4, 0, 115, 58, // Skip to: 19091 +/* 4128 */ MCD_OPC_CheckField, 8, 3, 0, 109, 58, // Skip to: 19091 +/* 4134 */ MCD_OPC_Decode, 250, 18, 239, 1, // Opcode: VLEIH +/* 4139 */ MCD_OPC_FilterValue, 66, 21, 0, // Skip to: 4164 +/* 4143 */ MCD_OPC_CheckPredicate, 22, 96, 58, // Skip to: 19091 +/* 4147 */ MCD_OPC_CheckField, 32, 4, 0, 90, 58, // Skip to: 19091 +/* 4153 */ MCD_OPC_CheckField, 8, 3, 0, 84, 58, // Skip to: 19091 +/* 4159 */ MCD_OPC_Decode, 249, 18, 240, 1, // Opcode: VLEIG +/* 4164 */ MCD_OPC_FilterValue, 67, 21, 0, // Skip to: 4189 +/* 4168 */ MCD_OPC_CheckPredicate, 22, 71, 58, // Skip to: 19091 +/* 4172 */ MCD_OPC_CheckField, 32, 4, 0, 65, 58, // Skip to: 19091 +/* 4178 */ MCD_OPC_CheckField, 8, 3, 0, 59, 58, // Skip to: 19091 +/* 4184 */ MCD_OPC_Decode, 248, 18, 241, 1, // Opcode: VLEIF +/* 4189 */ MCD_OPC_FilterValue, 68, 61, 0, // Skip to: 4254 +/* 4193 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4196 */ MCD_OPC_FilterValue, 0, 43, 58, // Skip to: 19091 +/* 4200 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4203 */ MCD_OPC_FilterValue, 0, 36, 58, // Skip to: 19091 +/* 4207 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 4210 */ MCD_OPC_FilterValue, 0, 29, 58, // Skip to: 19091 +/* 4214 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 4217 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4230 +/* 4221 */ MCD_OPC_CheckPredicate, 22, 20, 0, // Skip to: 4245 +/* 4225 */ MCD_OPC_Decode, 248, 20, 242, 1, // Opcode: VZERO +/* 4230 */ MCD_OPC_FilterValue, 255, 255, 3, 9, 0, // Skip to: 4245 +/* 4236 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4245 +/* 4240 */ MCD_OPC_Decode, 253, 19, 242, 1, // Opcode: VONE +/* 4245 */ MCD_OPC_CheckPredicate, 22, 250, 57, // Skip to: 19091 +/* 4249 */ MCD_OPC_Decode, 207, 18, 243, 1, // Opcode: VGBM +/* 4254 */ MCD_OPC_FilterValue, 69, 78, 0, // Skip to: 4336 +/* 4258 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4261 */ MCD_OPC_FilterValue, 0, 234, 57, // Skip to: 19091 +/* 4265 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 4268 */ MCD_OPC_FilterValue, 0, 227, 57, // Skip to: 19091 +/* 4272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4275 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4288 +/* 4279 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4327 +/* 4283 */ MCD_OPC_Decode, 159, 20, 244, 1, // Opcode: VREPIB +/* 4288 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4301 +/* 4292 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4327 +/* 4296 */ MCD_OPC_Decode, 162, 20, 244, 1, // Opcode: VREPIH +/* 4301 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4314 +/* 4305 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4327 +/* 4309 */ MCD_OPC_Decode, 160, 20, 244, 1, // Opcode: VREPIF +/* 4314 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4327 +/* 4318 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4327 +/* 4322 */ MCD_OPC_Decode, 161, 20, 244, 1, // Opcode: VREPIG +/* 4327 */ MCD_OPC_CheckPredicate, 22, 168, 57, // Skip to: 19091 +/* 4331 */ MCD_OPC_Decode, 158, 20, 245, 1, // Opcode: VREPI +/* 4336 */ MCD_OPC_FilterValue, 70, 78, 0, // Skip to: 4418 +/* 4340 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 4343 */ MCD_OPC_FilterValue, 0, 152, 57, // Skip to: 19091 +/* 4347 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 4350 */ MCD_OPC_FilterValue, 0, 145, 57, // Skip to: 19091 +/* 4354 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4357 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4370 +/* 4361 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4409 +/* 4365 */ MCD_OPC_Decode, 221, 18, 246, 1, // Opcode: VGMB +/* 4370 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4383 +/* 4374 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4409 +/* 4378 */ MCD_OPC_Decode, 224, 18, 246, 1, // Opcode: VGMH +/* 4383 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4396 +/* 4387 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4409 +/* 4391 */ MCD_OPC_Decode, 222, 18, 246, 1, // Opcode: VGMF +/* 4396 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4409 +/* 4400 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4409 +/* 4404 */ MCD_OPC_Decode, 223, 18, 246, 1, // Opcode: VGMG +/* 4409 */ MCD_OPC_CheckPredicate, 22, 86, 57, // Skip to: 19091 +/* 4413 */ MCD_OPC_Decode, 220, 18, 247, 1, // Opcode: VGM +/* 4418 */ MCD_OPC_FilterValue, 74, 87, 0, // Skip to: 4509 +/* 4422 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4425 */ MCD_OPC_FilterValue, 0, 70, 57, // Skip to: 19091 +/* 4429 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 4432 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4445 +/* 4436 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 4500 +/* 4440 */ MCD_OPC_Decode, 206, 18, 248, 1, // Opcode: VFTCISB +/* 4445 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4458 +/* 4449 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 4500 +/* 4453 */ MCD_OPC_Decode, 205, 18, 248, 1, // Opcode: VFTCIDB +/* 4458 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 4472 +/* 4463 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 4500 +/* 4467 */ MCD_OPC_Decode, 222, 21, 249, 1, // Opcode: WFTCISB +/* 4472 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 4486 +/* 4477 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 4500 +/* 4481 */ MCD_OPC_Decode, 221, 21, 250, 1, // Opcode: WFTCIDB +/* 4486 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 4500 +/* 4491 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4500 +/* 4495 */ MCD_OPC_Decode, 223, 21, 248, 1, // Opcode: WFTCIXB +/* 4500 */ MCD_OPC_CheckPredicate, 22, 251, 56, // Skip to: 19091 +/* 4504 */ MCD_OPC_Decode, 204, 18, 251, 1, // Opcode: VFTCI +/* 4509 */ MCD_OPC_FilterValue, 77, 71, 0, // Skip to: 4584 +/* 4513 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4516 */ MCD_OPC_FilterValue, 0, 235, 56, // Skip to: 19091 +/* 4520 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4523 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4536 +/* 4527 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4575 +/* 4531 */ MCD_OPC_Decode, 154, 20, 252, 1, // Opcode: VREPB +/* 4536 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4549 +/* 4540 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4575 +/* 4544 */ MCD_OPC_Decode, 157, 20, 252, 1, // Opcode: VREPH +/* 4549 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4562 +/* 4553 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4575 +/* 4557 */ MCD_OPC_Decode, 155, 20, 252, 1, // Opcode: VREPF +/* 4562 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4575 +/* 4566 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4575 +/* 4570 */ MCD_OPC_Decode, 156, 20, 252, 1, // Opcode: VREPG +/* 4575 */ MCD_OPC_CheckPredicate, 22, 176, 56, // Skip to: 19091 +/* 4579 */ MCD_OPC_Decode, 153, 20, 253, 1, // Opcode: VREP +/* 4584 */ MCD_OPC_FilterValue, 80, 78, 0, // Skip to: 4666 +/* 4588 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4591 */ MCD_OPC_FilterValue, 0, 160, 56, // Skip to: 19091 +/* 4595 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 4598 */ MCD_OPC_FilterValue, 0, 153, 56, // Skip to: 19091 +/* 4602 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4618 +/* 4609 */ MCD_OPC_CheckPredicate, 23, 44, 0, // Skip to: 4657 +/* 4613 */ MCD_OPC_Decode, 148, 20, 254, 1, // Opcode: VPOPCTB +/* 4618 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4631 +/* 4622 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 4657 +/* 4626 */ MCD_OPC_Decode, 151, 20, 254, 1, // Opcode: VPOPCTH +/* 4631 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4644 +/* 4635 */ MCD_OPC_CheckPredicate, 23, 18, 0, // Skip to: 4657 +/* 4639 */ MCD_OPC_Decode, 149, 20, 254, 1, // Opcode: VPOPCTF +/* 4644 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4657 +/* 4648 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4657 +/* 4652 */ MCD_OPC_Decode, 150, 20, 254, 1, // Opcode: VPOPCTG +/* 4657 */ MCD_OPC_CheckPredicate, 22, 94, 56, // Skip to: 19091 +/* 4661 */ MCD_OPC_Decode, 147, 20, 255, 1, // Opcode: VPOPCT +/* 4666 */ MCD_OPC_FilterValue, 82, 78, 0, // Skip to: 4748 +/* 4670 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4673 */ MCD_OPC_FilterValue, 0, 78, 56, // Skip to: 19091 +/* 4677 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 4680 */ MCD_OPC_FilterValue, 0, 71, 56, // Skip to: 19091 +/* 4684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4687 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4700 +/* 4691 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4739 +/* 4695 */ MCD_OPC_Decode, 153, 17, 254, 1, // Opcode: VCTZB +/* 4700 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4713 +/* 4704 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4739 +/* 4708 */ MCD_OPC_Decode, 156, 17, 254, 1, // Opcode: VCTZH +/* 4713 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4726 +/* 4717 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4739 +/* 4721 */ MCD_OPC_Decode, 154, 17, 254, 1, // Opcode: VCTZF +/* 4726 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4739 +/* 4730 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4739 +/* 4734 */ MCD_OPC_Decode, 155, 17, 254, 1, // Opcode: VCTZG +/* 4739 */ MCD_OPC_CheckPredicate, 22, 12, 56, // Skip to: 19091 +/* 4743 */ MCD_OPC_Decode, 152, 17, 255, 1, // Opcode: VCTZ +/* 4748 */ MCD_OPC_FilterValue, 83, 78, 0, // Skip to: 4830 +/* 4752 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4755 */ MCD_OPC_FilterValue, 0, 252, 55, // Skip to: 19091 +/* 4759 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 4762 */ MCD_OPC_FilterValue, 0, 245, 55, // Skip to: 19091 +/* 4766 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4769 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4782 +/* 4773 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4821 +/* 4777 */ MCD_OPC_Decode, 147, 17, 254, 1, // Opcode: VCLZB +/* 4782 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4795 +/* 4786 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4821 +/* 4790 */ MCD_OPC_Decode, 150, 17, 254, 1, // Opcode: VCLZH +/* 4795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4808 +/* 4799 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4821 +/* 4803 */ MCD_OPC_Decode, 148, 17, 254, 1, // Opcode: VCLZF +/* 4808 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4821 +/* 4812 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4821 +/* 4816 */ MCD_OPC_Decode, 149, 17, 254, 1, // Opcode: VCLZG +/* 4821 */ MCD_OPC_CheckPredicate, 22, 186, 55, // Skip to: 19091 +/* 4825 */ MCD_OPC_Decode, 146, 17, 255, 1, // Opcode: VCLZ +/* 4830 */ MCD_OPC_FilterValue, 86, 21, 0, // Skip to: 4855 +/* 4834 */ MCD_OPC_CheckPredicate, 22, 173, 55, // Skip to: 19091 +/* 4838 */ MCD_OPC_CheckField, 12, 20, 0, 167, 55, // Skip to: 19091 +/* 4844 */ MCD_OPC_CheckField, 8, 2, 0, 161, 55, // Skip to: 19091 +/* 4850 */ MCD_OPC_Decode, 142, 19, 254, 1, // Opcode: VLR +/* 4855 */ MCD_OPC_FilterValue, 92, 117, 0, // Skip to: 4976 +/* 4859 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4862 */ MCD_OPC_FilterValue, 0, 145, 55, // Skip to: 19091 +/* 4866 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4869 */ MCD_OPC_FilterValue, 0, 138, 55, // Skip to: 19091 +/* 4873 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 4876 */ MCD_OPC_FilterValue, 0, 131, 55, // Skip to: 19091 +/* 4880 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4883 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4911 +/* 4887 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4902 +/* 4891 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4902 +/* 4897 */ MCD_OPC_Decode, 227, 18, 254, 1, // Opcode: VISTRBS +/* 4902 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 4967 +/* 4906 */ MCD_OPC_Decode, 226, 18, 128, 2, // Opcode: VISTRB +/* 4911 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4939 +/* 4915 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4930 +/* 4919 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4930 +/* 4925 */ MCD_OPC_Decode, 231, 18, 254, 1, // Opcode: VISTRHS +/* 4930 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 4967 +/* 4934 */ MCD_OPC_Decode, 230, 18, 128, 2, // Opcode: VISTRH +/* 4939 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 4967 +/* 4943 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4958 +/* 4947 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4958 +/* 4953 */ MCD_OPC_Decode, 229, 18, 254, 1, // Opcode: VISTRFS +/* 4958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4967 +/* 4962 */ MCD_OPC_Decode, 228, 18, 128, 2, // Opcode: VISTRF +/* 4967 */ MCD_OPC_CheckPredicate, 22, 40, 55, // Skip to: 19091 +/* 4971 */ MCD_OPC_Decode, 225, 18, 129, 2, // Opcode: VISTR +/* 4976 */ MCD_OPC_FilterValue, 95, 65, 0, // Skip to: 5045 +/* 4980 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 4983 */ MCD_OPC_FilterValue, 0, 24, 55, // Skip to: 19091 +/* 4987 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 4990 */ MCD_OPC_FilterValue, 0, 17, 55, // Skip to: 19091 +/* 4994 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5010 +/* 5001 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5036 +/* 5005 */ MCD_OPC_Decode, 180, 20, 254, 1, // Opcode: VSEGB +/* 5010 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5023 +/* 5014 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5036 +/* 5018 */ MCD_OPC_Decode, 182, 20, 254, 1, // Opcode: VSEGH +/* 5023 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5036 +/* 5027 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5036 +/* 5031 */ MCD_OPC_Decode, 181, 20, 254, 1, // Opcode: VSEGF +/* 5036 */ MCD_OPC_CheckPredicate, 22, 227, 54, // Skip to: 19091 +/* 5040 */ MCD_OPC_Decode, 179, 20, 255, 1, // Opcode: VSEG +/* 5045 */ MCD_OPC_FilterValue, 96, 78, 0, // Skip to: 5127 +/* 5049 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5052 */ MCD_OPC_FilterValue, 0, 211, 54, // Skip to: 19091 +/* 5056 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5059 */ MCD_OPC_FilterValue, 0, 204, 54, // Skip to: 19091 +/* 5063 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5066 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5079 +/* 5070 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5118 +/* 5074 */ MCD_OPC_Decode, 229, 19, 130, 2, // Opcode: VMRLB +/* 5079 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5092 +/* 5083 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5118 +/* 5087 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: VMRLH +/* 5092 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5105 +/* 5096 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5118 +/* 5100 */ MCD_OPC_Decode, 230, 19, 130, 2, // Opcode: VMRLF +/* 5105 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5118 +/* 5109 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5118 +/* 5113 */ MCD_OPC_Decode, 231, 19, 130, 2, // Opcode: VMRLG +/* 5118 */ MCD_OPC_CheckPredicate, 22, 145, 54, // Skip to: 19091 +/* 5122 */ MCD_OPC_Decode, 228, 19, 131, 2, // Opcode: VMRL +/* 5127 */ MCD_OPC_FilterValue, 97, 78, 0, // Skip to: 5209 +/* 5131 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5134 */ MCD_OPC_FilterValue, 0, 129, 54, // Skip to: 19091 +/* 5138 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5141 */ MCD_OPC_FilterValue, 0, 122, 54, // Skip to: 19091 +/* 5145 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5161 +/* 5152 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5200 +/* 5156 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: VMRHB +/* 5161 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5174 +/* 5165 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5200 +/* 5169 */ MCD_OPC_Decode, 227, 19, 130, 2, // Opcode: VMRHH +/* 5174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5187 +/* 5178 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5200 +/* 5182 */ MCD_OPC_Decode, 225, 19, 130, 2, // Opcode: VMRHF +/* 5187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5200 +/* 5191 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5200 +/* 5195 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: VMRHG +/* 5200 */ MCD_OPC_CheckPredicate, 22, 63, 54, // Skip to: 19091 +/* 5204 */ MCD_OPC_Decode, 223, 19, 131, 2, // Opcode: VMRH +/* 5209 */ MCD_OPC_FilterValue, 98, 21, 0, // Skip to: 5234 +/* 5213 */ MCD_OPC_CheckPredicate, 22, 50, 54, // Skip to: 19091 +/* 5217 */ MCD_OPC_CheckField, 12, 16, 0, 44, 54, // Skip to: 19091 +/* 5223 */ MCD_OPC_CheckField, 8, 3, 0, 38, 54, // Skip to: 19091 +/* 5229 */ MCD_OPC_Decode, 155, 19, 132, 2, // Opcode: VLVGP +/* 5234 */ MCD_OPC_FilterValue, 100, 52, 0, // Skip to: 5290 +/* 5238 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5241 */ MCD_OPC_FilterValue, 0, 22, 54, // Skip to: 19091 +/* 5245 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5248 */ MCD_OPC_FilterValue, 0, 15, 54, // Skip to: 19091 +/* 5252 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5255 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5268 +/* 5259 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5281 +/* 5263 */ MCD_OPC_Decode, 220, 20, 130, 2, // Opcode: VSUMB +/* 5268 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5281 +/* 5272 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5281 +/* 5276 */ MCD_OPC_Decode, 224, 20, 130, 2, // Opcode: VSUMH +/* 5281 */ MCD_OPC_CheckPredicate, 22, 238, 53, // Skip to: 19091 +/* 5285 */ MCD_OPC_Decode, 219, 20, 131, 2, // Opcode: VSUM +/* 5290 */ MCD_OPC_FilterValue, 101, 52, 0, // Skip to: 5346 +/* 5294 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5297 */ MCD_OPC_FilterValue, 0, 222, 53, // Skip to: 19091 +/* 5301 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5304 */ MCD_OPC_FilterValue, 0, 215, 53, // Skip to: 19091 +/* 5308 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5324 +/* 5315 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5337 +/* 5319 */ MCD_OPC_Decode, 223, 20, 130, 2, // Opcode: VSUMGH +/* 5324 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5337 +/* 5328 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5337 +/* 5332 */ MCD_OPC_Decode, 222, 20, 130, 2, // Opcode: VSUMGF +/* 5337 */ MCD_OPC_CheckPredicate, 22, 182, 53, // Skip to: 19091 +/* 5341 */ MCD_OPC_Decode, 221, 20, 131, 2, // Opcode: VSUMG +/* 5346 */ MCD_OPC_FilterValue, 102, 21, 0, // Skip to: 5371 +/* 5350 */ MCD_OPC_CheckPredicate, 22, 169, 53, // Skip to: 19091 +/* 5354 */ MCD_OPC_CheckField, 12, 16, 0, 163, 53, // Skip to: 19091 +/* 5360 */ MCD_OPC_CheckField, 8, 1, 0, 157, 53, // Skip to: 19091 +/* 5366 */ MCD_OPC_Decode, 143, 17, 130, 2, // Opcode: VCKSM +/* 5371 */ MCD_OPC_FilterValue, 103, 52, 0, // Skip to: 5427 +/* 5375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5378 */ MCD_OPC_FilterValue, 0, 141, 53, // Skip to: 19091 +/* 5382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5385 */ MCD_OPC_FilterValue, 0, 134, 53, // Skip to: 19091 +/* 5389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5392 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5405 +/* 5396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5418 +/* 5400 */ MCD_OPC_Decode, 226, 20, 130, 2, // Opcode: VSUMQF +/* 5405 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5418 +/* 5409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5418 +/* 5413 */ MCD_OPC_Decode, 227, 20, 130, 2, // Opcode: VSUMQG +/* 5418 */ MCD_OPC_CheckPredicate, 22, 101, 53, // Skip to: 19091 +/* 5422 */ MCD_OPC_Decode, 225, 20, 131, 2, // Opcode: VSUMQ +/* 5427 */ MCD_OPC_FilterValue, 104, 21, 0, // Skip to: 5452 +/* 5431 */ MCD_OPC_CheckPredicate, 22, 88, 53, // Skip to: 19091 +/* 5435 */ MCD_OPC_CheckField, 12, 16, 0, 82, 53, // Skip to: 19091 +/* 5441 */ MCD_OPC_CheckField, 8, 1, 0, 76, 53, // Skip to: 19091 +/* 5447 */ MCD_OPC_Decode, 246, 19, 130, 2, // Opcode: VN +/* 5452 */ MCD_OPC_FilterValue, 105, 21, 0, // Skip to: 5477 +/* 5456 */ MCD_OPC_CheckPredicate, 22, 63, 53, // Skip to: 19091 +/* 5460 */ MCD_OPC_CheckField, 12, 16, 0, 57, 53, // Skip to: 19091 +/* 5466 */ MCD_OPC_CheckField, 8, 1, 0, 51, 53, // Skip to: 19091 +/* 5472 */ MCD_OPC_Decode, 247, 19, 130, 2, // Opcode: VNC +/* 5477 */ MCD_OPC_FilterValue, 106, 21, 0, // Skip to: 5502 +/* 5481 */ MCD_OPC_CheckPredicate, 22, 38, 53, // Skip to: 19091 +/* 5485 */ MCD_OPC_CheckField, 12, 16, 0, 32, 53, // Skip to: 19091 +/* 5491 */ MCD_OPC_CheckField, 8, 1, 0, 26, 53, // Skip to: 19091 +/* 5497 */ MCD_OPC_Decode, 251, 19, 130, 2, // Opcode: VO +/* 5502 */ MCD_OPC_FilterValue, 107, 21, 0, // Skip to: 5527 +/* 5506 */ MCD_OPC_CheckPredicate, 22, 13, 53, // Skip to: 19091 +/* 5510 */ MCD_OPC_CheckField, 12, 16, 0, 7, 53, // Skip to: 19091 +/* 5516 */ MCD_OPC_CheckField, 8, 1, 0, 1, 53, // Skip to: 19091 +/* 5522 */ MCD_OPC_Decode, 249, 19, 130, 2, // Opcode: VNO +/* 5527 */ MCD_OPC_FilterValue, 108, 21, 0, // Skip to: 5552 +/* 5531 */ MCD_OPC_CheckPredicate, 23, 244, 52, // Skip to: 19091 +/* 5535 */ MCD_OPC_CheckField, 12, 16, 0, 238, 52, // Skip to: 19091 +/* 5541 */ MCD_OPC_CheckField, 8, 1, 0, 232, 52, // Skip to: 19091 +/* 5547 */ MCD_OPC_Decode, 250, 19, 130, 2, // Opcode: VNX +/* 5552 */ MCD_OPC_FilterValue, 109, 21, 0, // Skip to: 5577 +/* 5556 */ MCD_OPC_CheckPredicate, 22, 219, 52, // Skip to: 19091 +/* 5560 */ MCD_OPC_CheckField, 12, 16, 0, 213, 52, // Skip to: 19091 +/* 5566 */ MCD_OPC_CheckField, 8, 1, 0, 207, 52, // Skip to: 19091 +/* 5572 */ MCD_OPC_Decode, 247, 20, 130, 2, // Opcode: VX +/* 5577 */ MCD_OPC_FilterValue, 110, 21, 0, // Skip to: 5602 +/* 5581 */ MCD_OPC_CheckPredicate, 23, 194, 52, // Skip to: 19091 +/* 5585 */ MCD_OPC_CheckField, 12, 16, 0, 188, 52, // Skip to: 19091 +/* 5591 */ MCD_OPC_CheckField, 8, 1, 0, 182, 52, // Skip to: 19091 +/* 5597 */ MCD_OPC_Decode, 248, 19, 130, 2, // Opcode: VNN +/* 5602 */ MCD_OPC_FilterValue, 111, 21, 0, // Skip to: 5627 +/* 5606 */ MCD_OPC_CheckPredicate, 23, 169, 52, // Skip to: 19091 +/* 5610 */ MCD_OPC_CheckField, 12, 16, 0, 163, 52, // Skip to: 19091 +/* 5616 */ MCD_OPC_CheckField, 8, 1, 0, 157, 52, // Skip to: 19091 +/* 5622 */ MCD_OPC_Decode, 252, 19, 130, 2, // Opcode: VOC +/* 5627 */ MCD_OPC_FilterValue, 112, 78, 0, // Skip to: 5709 +/* 5631 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5634 */ MCD_OPC_FilterValue, 0, 141, 52, // Skip to: 19091 +/* 5638 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5641 */ MCD_OPC_FilterValue, 0, 134, 52, // Skip to: 19091 +/* 5645 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5648 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5661 +/* 5652 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5700 +/* 5656 */ MCD_OPC_Decode, 193, 17, 130, 2, // Opcode: VESLVB +/* 5661 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5674 +/* 5665 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5700 +/* 5669 */ MCD_OPC_Decode, 196, 17, 130, 2, // Opcode: VESLVH +/* 5674 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5687 +/* 5678 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5700 +/* 5682 */ MCD_OPC_Decode, 194, 17, 130, 2, // Opcode: VESLVF +/* 5687 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5700 +/* 5691 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5700 +/* 5695 */ MCD_OPC_Decode, 195, 17, 130, 2, // Opcode: VESLVG +/* 5700 */ MCD_OPC_CheckPredicate, 22, 75, 52, // Skip to: 19091 +/* 5704 */ MCD_OPC_Decode, 192, 17, 131, 2, // Opcode: VESLV +/* 5709 */ MCD_OPC_FilterValue, 114, 78, 0, // Skip to: 5791 +/* 5713 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5716 */ MCD_OPC_FilterValue, 0, 59, 52, // Skip to: 19091 +/* 5720 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 5723 */ MCD_OPC_FilterValue, 0, 52, 52, // Skip to: 19091 +/* 5727 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5730 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5743 +/* 5734 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5782 +/* 5738 */ MCD_OPC_Decode, 173, 17, 133, 2, // Opcode: VERIMB +/* 5743 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5756 +/* 5747 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5782 +/* 5751 */ MCD_OPC_Decode, 176, 17, 133, 2, // Opcode: VERIMH +/* 5756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5769 +/* 5760 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5782 +/* 5764 */ MCD_OPC_Decode, 174, 17, 133, 2, // Opcode: VERIMF +/* 5769 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5782 +/* 5773 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5782 +/* 5777 */ MCD_OPC_Decode, 175, 17, 133, 2, // Opcode: VERIMG +/* 5782 */ MCD_OPC_CheckPredicate, 22, 249, 51, // Skip to: 19091 +/* 5786 */ MCD_OPC_Decode, 172, 17, 134, 2, // Opcode: VERIM +/* 5791 */ MCD_OPC_FilterValue, 115, 78, 0, // Skip to: 5873 +/* 5795 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5798 */ MCD_OPC_FilterValue, 0, 233, 51, // Skip to: 19091 +/* 5802 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5805 */ MCD_OPC_FilterValue, 0, 226, 51, // Skip to: 19091 +/* 5809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5812 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5825 +/* 5816 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5864 +/* 5820 */ MCD_OPC_Decode, 183, 17, 130, 2, // Opcode: VERLLVB +/* 5825 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5838 +/* 5829 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5864 +/* 5833 */ MCD_OPC_Decode, 186, 17, 130, 2, // Opcode: VERLLVH +/* 5838 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5851 +/* 5842 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5864 +/* 5846 */ MCD_OPC_Decode, 184, 17, 130, 2, // Opcode: VERLLVF +/* 5851 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5864 +/* 5855 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5864 +/* 5859 */ MCD_OPC_Decode, 185, 17, 130, 2, // Opcode: VERLLVG +/* 5864 */ MCD_OPC_CheckPredicate, 22, 167, 51, // Skip to: 19091 +/* 5868 */ MCD_OPC_Decode, 182, 17, 131, 2, // Opcode: VERLLV +/* 5873 */ MCD_OPC_FilterValue, 116, 21, 0, // Skip to: 5898 +/* 5877 */ MCD_OPC_CheckPredicate, 22, 154, 51, // Skip to: 19091 +/* 5881 */ MCD_OPC_CheckField, 12, 16, 0, 148, 51, // Skip to: 19091 +/* 5887 */ MCD_OPC_CheckField, 8, 1, 0, 142, 51, // Skip to: 19091 +/* 5893 */ MCD_OPC_Decode, 187, 20, 130, 2, // Opcode: VSL +/* 5898 */ MCD_OPC_FilterValue, 117, 21, 0, // Skip to: 5923 +/* 5902 */ MCD_OPC_CheckPredicate, 22, 129, 51, // Skip to: 19091 +/* 5906 */ MCD_OPC_CheckField, 12, 16, 0, 123, 51, // Skip to: 19091 +/* 5912 */ MCD_OPC_CheckField, 8, 1, 0, 117, 51, // Skip to: 19091 +/* 5918 */ MCD_OPC_Decode, 188, 20, 130, 2, // Opcode: VSLB +/* 5923 */ MCD_OPC_FilterValue, 119, 27, 0, // Skip to: 5954 +/* 5927 */ MCD_OPC_CheckPredicate, 22, 104, 51, // Skip to: 19091 +/* 5931 */ MCD_OPC_CheckField, 24, 4, 0, 98, 51, // Skip to: 19091 +/* 5937 */ MCD_OPC_CheckField, 12, 4, 0, 92, 51, // Skip to: 19091 +/* 5943 */ MCD_OPC_CheckField, 8, 1, 0, 86, 51, // Skip to: 19091 +/* 5949 */ MCD_OPC_Decode, 189, 20, 135, 2, // Opcode: VSLDB +/* 5954 */ MCD_OPC_FilterValue, 120, 78, 0, // Skip to: 6036 +/* 5958 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5961 */ MCD_OPC_FilterValue, 0, 70, 51, // Skip to: 19091 +/* 5965 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 5968 */ MCD_OPC_FilterValue, 0, 63, 51, // Skip to: 19091 +/* 5972 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5988 +/* 5979 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6027 +/* 5983 */ MCD_OPC_Decode, 213, 17, 130, 2, // Opcode: VESRLVB +/* 5988 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6001 +/* 5992 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6027 +/* 5996 */ MCD_OPC_Decode, 216, 17, 130, 2, // Opcode: VESRLVH +/* 6001 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6014 +/* 6005 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6027 +/* 6009 */ MCD_OPC_Decode, 214, 17, 130, 2, // Opcode: VESRLVF +/* 6014 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6027 +/* 6018 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6027 +/* 6022 */ MCD_OPC_Decode, 215, 17, 130, 2, // Opcode: VESRLVG +/* 6027 */ MCD_OPC_CheckPredicate, 22, 4, 51, // Skip to: 19091 +/* 6031 */ MCD_OPC_Decode, 212, 17, 131, 2, // Opcode: VESRLV +/* 6036 */ MCD_OPC_FilterValue, 122, 78, 0, // Skip to: 6118 +/* 6040 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6043 */ MCD_OPC_FilterValue, 0, 244, 50, // Skip to: 19091 +/* 6047 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 6050 */ MCD_OPC_FilterValue, 0, 237, 50, // Skip to: 19091 +/* 6054 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6057 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6070 +/* 6061 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6109 +/* 6065 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: VESRAVB +/* 6070 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6083 +/* 6074 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6109 +/* 6078 */ MCD_OPC_Decode, 206, 17, 130, 2, // Opcode: VESRAVH +/* 6083 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6096 +/* 6087 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6109 +/* 6091 */ MCD_OPC_Decode, 204, 17, 130, 2, // Opcode: VESRAVF +/* 6096 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6109 +/* 6100 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6109 +/* 6104 */ MCD_OPC_Decode, 205, 17, 130, 2, // Opcode: VESRAVG +/* 6109 */ MCD_OPC_CheckPredicate, 22, 178, 50, // Skip to: 19091 +/* 6113 */ MCD_OPC_Decode, 202, 17, 131, 2, // Opcode: VESRAV +/* 6118 */ MCD_OPC_FilterValue, 124, 21, 0, // Skip to: 6143 +/* 6122 */ MCD_OPC_CheckPredicate, 22, 165, 50, // Skip to: 19091 +/* 6126 */ MCD_OPC_CheckField, 12, 16, 0, 159, 50, // Skip to: 19091 +/* 6132 */ MCD_OPC_CheckField, 8, 1, 0, 153, 50, // Skip to: 19091 +/* 6138 */ MCD_OPC_Decode, 194, 20, 130, 2, // Opcode: VSRL +/* 6143 */ MCD_OPC_FilterValue, 125, 21, 0, // Skip to: 6168 +/* 6147 */ MCD_OPC_CheckPredicate, 22, 140, 50, // Skip to: 19091 +/* 6151 */ MCD_OPC_CheckField, 12, 16, 0, 134, 50, // Skip to: 19091 +/* 6157 */ MCD_OPC_CheckField, 8, 1, 0, 128, 50, // Skip to: 19091 +/* 6163 */ MCD_OPC_Decode, 195, 20, 130, 2, // Opcode: VSRLB +/* 6168 */ MCD_OPC_FilterValue, 126, 21, 0, // Skip to: 6193 +/* 6172 */ MCD_OPC_CheckPredicate, 22, 115, 50, // Skip to: 19091 +/* 6176 */ MCD_OPC_CheckField, 12, 16, 0, 109, 50, // Skip to: 19091 +/* 6182 */ MCD_OPC_CheckField, 8, 1, 0, 103, 50, // Skip to: 19091 +/* 6188 */ MCD_OPC_Decode, 192, 20, 130, 2, // Opcode: VSRA +/* 6193 */ MCD_OPC_FilterValue, 127, 21, 0, // Skip to: 6218 +/* 6197 */ MCD_OPC_CheckPredicate, 22, 90, 50, // Skip to: 19091 +/* 6201 */ MCD_OPC_CheckField, 12, 16, 0, 84, 50, // Skip to: 19091 +/* 6207 */ MCD_OPC_CheckField, 8, 1, 0, 78, 50, // Skip to: 19091 +/* 6213 */ MCD_OPC_Decode, 193, 20, 130, 2, // Opcode: VSRAB +/* 6218 */ MCD_OPC_FilterValue, 128, 1, 198, 0, // Skip to: 6421 +/* 6223 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6226 */ MCD_OPC_FilterValue, 0, 61, 50, // Skip to: 19091 +/* 6230 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6233 */ MCD_OPC_FilterValue, 0, 54, 50, // Skip to: 19091 +/* 6237 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 6240 */ MCD_OPC_FilterValue, 0, 47, 50, // Skip to: 19091 +/* 6244 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6247 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6302 +/* 6251 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6254 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6267 +/* 6258 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6293 +/* 6262 */ MCD_OPC_Decode, 253, 17, 130, 2, // Opcode: VFEEBS +/* 6267 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6280 +/* 6271 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6293 +/* 6275 */ MCD_OPC_Decode, 130, 18, 130, 2, // Opcode: VFEEZB +/* 6280 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6293 +/* 6284 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6293 +/* 6288 */ MCD_OPC_Decode, 131, 18, 130, 2, // Opcode: VFEEZBS +/* 6293 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6412 +/* 6297 */ MCD_OPC_Decode, 252, 17, 136, 2, // Opcode: VFEEB +/* 6302 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6357 +/* 6306 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6309 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6322 +/* 6313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6348 +/* 6317 */ MCD_OPC_Decode, 129, 18, 130, 2, // Opcode: VFEEHS +/* 6322 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6335 +/* 6326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6348 +/* 6330 */ MCD_OPC_Decode, 134, 18, 130, 2, // Opcode: VFEEZH +/* 6335 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6348 +/* 6339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6348 +/* 6343 */ MCD_OPC_Decode, 135, 18, 130, 2, // Opcode: VFEEZHS +/* 6348 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6412 +/* 6352 */ MCD_OPC_Decode, 128, 18, 136, 2, // Opcode: VFEEH +/* 6357 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6412 +/* 6361 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6364 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6377 +/* 6368 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6403 +/* 6372 */ MCD_OPC_Decode, 255, 17, 130, 2, // Opcode: VFEEFS +/* 6377 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6390 +/* 6381 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6403 +/* 6385 */ MCD_OPC_Decode, 132, 18, 130, 2, // Opcode: VFEEZF +/* 6390 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6403 +/* 6394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6403 +/* 6398 */ MCD_OPC_Decode, 133, 18, 130, 2, // Opcode: VFEEZFS +/* 6403 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6412 +/* 6407 */ MCD_OPC_Decode, 254, 17, 136, 2, // Opcode: VFEEF +/* 6412 */ MCD_OPC_CheckPredicate, 22, 131, 49, // Skip to: 19091 +/* 6416 */ MCD_OPC_Decode, 251, 17, 137, 2, // Opcode: VFEE +/* 6421 */ MCD_OPC_FilterValue, 129, 1, 198, 0, // Skip to: 6624 +/* 6426 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6429 */ MCD_OPC_FilterValue, 0, 114, 49, // Skip to: 19091 +/* 6433 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6436 */ MCD_OPC_FilterValue, 0, 107, 49, // Skip to: 19091 +/* 6440 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 6443 */ MCD_OPC_FilterValue, 0, 100, 49, // Skip to: 19091 +/* 6447 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6450 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6505 +/* 6454 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6457 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6470 +/* 6461 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6496 +/* 6465 */ MCD_OPC_Decode, 138, 18, 130, 2, // Opcode: VFENEBS +/* 6470 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6483 +/* 6474 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6496 +/* 6478 */ MCD_OPC_Decode, 143, 18, 130, 2, // Opcode: VFENEZB +/* 6483 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6496 +/* 6487 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6496 +/* 6491 */ MCD_OPC_Decode, 144, 18, 130, 2, // Opcode: VFENEZBS +/* 6496 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6615 +/* 6500 */ MCD_OPC_Decode, 137, 18, 136, 2, // Opcode: VFENEB +/* 6505 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6560 +/* 6509 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6512 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6525 +/* 6516 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6551 +/* 6520 */ MCD_OPC_Decode, 142, 18, 130, 2, // Opcode: VFENEHS +/* 6525 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6538 +/* 6529 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6551 +/* 6533 */ MCD_OPC_Decode, 147, 18, 130, 2, // Opcode: VFENEZH +/* 6538 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6551 +/* 6542 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6551 +/* 6546 */ MCD_OPC_Decode, 148, 18, 130, 2, // Opcode: VFENEZHS +/* 6551 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6615 +/* 6555 */ MCD_OPC_Decode, 141, 18, 136, 2, // Opcode: VFENEH +/* 6560 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6615 +/* 6564 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 6567 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6580 +/* 6571 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6606 +/* 6575 */ MCD_OPC_Decode, 140, 18, 130, 2, // Opcode: VFENEFS +/* 6580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6593 +/* 6584 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6606 +/* 6588 */ MCD_OPC_Decode, 145, 18, 130, 2, // Opcode: VFENEZF +/* 6593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6606 +/* 6597 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6606 +/* 6601 */ MCD_OPC_Decode, 146, 18, 130, 2, // Opcode: VFENEZFS +/* 6606 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6615 +/* 6610 */ MCD_OPC_Decode, 139, 18, 136, 2, // Opcode: VFENEF +/* 6615 */ MCD_OPC_CheckPredicate, 22, 184, 48, // Skip to: 19091 +/* 6619 */ MCD_OPC_Decode, 136, 18, 137, 2, // Opcode: VFENE +/* 6624 */ MCD_OPC_FilterValue, 130, 1, 207, 0, // Skip to: 6836 +/* 6629 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6632 */ MCD_OPC_FilterValue, 0, 167, 48, // Skip to: 19091 +/* 6636 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6639 */ MCD_OPC_FilterValue, 0, 160, 48, // Skip to: 19091 +/* 6643 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 6646 */ MCD_OPC_FilterValue, 0, 153, 48, // Skip to: 19091 +/* 6650 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6653 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6711 +/* 6657 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6672 +/* 6661 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6672 +/* 6667 */ MCD_OPC_Decode, 227, 17, 138, 2, // Opcode: VFAEZBS +/* 6672 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6687 +/* 6676 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6687 +/* 6682 */ MCD_OPC_Decode, 221, 17, 139, 2, // Opcode: VFAEBS +/* 6687 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6702 +/* 6691 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6702 +/* 6697 */ MCD_OPC_Decode, 226, 17, 140, 2, // Opcode: VFAEZB +/* 6702 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 6827 +/* 6706 */ MCD_OPC_Decode, 220, 17, 136, 2, // Opcode: VFAEB +/* 6711 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 6769 +/* 6715 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6730 +/* 6719 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6730 +/* 6725 */ MCD_OPC_Decode, 231, 17, 138, 2, // Opcode: VFAEZHS +/* 6730 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6745 +/* 6734 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6745 +/* 6740 */ MCD_OPC_Decode, 225, 17, 139, 2, // Opcode: VFAEHS +/* 6745 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6760 +/* 6749 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6760 +/* 6755 */ MCD_OPC_Decode, 230, 17, 140, 2, // Opcode: VFAEZH +/* 6760 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 6827 +/* 6764 */ MCD_OPC_Decode, 224, 17, 136, 2, // Opcode: VFAEH +/* 6769 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 6827 +/* 6773 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6788 +/* 6777 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6788 +/* 6783 */ MCD_OPC_Decode, 229, 17, 138, 2, // Opcode: VFAEZFS +/* 6788 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6803 +/* 6792 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6803 +/* 6798 */ MCD_OPC_Decode, 223, 17, 139, 2, // Opcode: VFAEFS +/* 6803 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6818 +/* 6807 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6818 +/* 6813 */ MCD_OPC_Decode, 228, 17, 140, 2, // Opcode: VFAEZF +/* 6818 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6827 +/* 6822 */ MCD_OPC_Decode, 222, 17, 136, 2, // Opcode: VFAEF +/* 6827 */ MCD_OPC_CheckPredicate, 22, 228, 47, // Skip to: 19091 +/* 6831 */ MCD_OPC_Decode, 219, 17, 137, 2, // Opcode: VFAE +/* 6836 */ MCD_OPC_FilterValue, 132, 1, 21, 0, // Skip to: 6862 +/* 6841 */ MCD_OPC_CheckPredicate, 22, 214, 47, // Skip to: 19091 +/* 6845 */ MCD_OPC_CheckField, 16, 12, 0, 208, 47, // Skip to: 19091 +/* 6851 */ MCD_OPC_CheckField, 8, 1, 0, 202, 47, // Skip to: 19091 +/* 6857 */ MCD_OPC_Decode, 254, 19, 131, 2, // Opcode: VPDI +/* 6862 */ MCD_OPC_FilterValue, 133, 1, 21, 0, // Skip to: 6888 +/* 6867 */ MCD_OPC_CheckPredicate, 23, 188, 47, // Skip to: 19091 +/* 6871 */ MCD_OPC_CheckField, 12, 16, 0, 182, 47, // Skip to: 19091 +/* 6877 */ MCD_OPC_CheckField, 8, 1, 0, 176, 47, // Skip to: 19091 +/* 6883 */ MCD_OPC_Decode, 237, 16, 130, 2, // Opcode: VBPERM +/* 6888 */ MCD_OPC_FilterValue, 138, 1, 193, 0, // Skip to: 7086 +/* 6893 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6896 */ MCD_OPC_FilterValue, 0, 159, 47, // Skip to: 19091 +/* 6900 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 6903 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6961 +/* 6907 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6922 +/* 6911 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6922 +/* 6917 */ MCD_OPC_Decode, 212, 20, 141, 2, // Opcode: VSTRCZBS +/* 6922 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6937 +/* 6926 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6937 +/* 6932 */ MCD_OPC_Decode, 206, 20, 142, 2, // Opcode: VSTRCBS +/* 6937 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6952 +/* 6941 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6952 +/* 6947 */ MCD_OPC_Decode, 211, 20, 143, 2, // Opcode: VSTRCZB +/* 6952 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 7077 +/* 6956 */ MCD_OPC_Decode, 205, 20, 144, 2, // Opcode: VSTRCB +/* 6961 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 7019 +/* 6965 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6980 +/* 6969 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6980 +/* 6975 */ MCD_OPC_Decode, 216, 20, 141, 2, // Opcode: VSTRCZHS +/* 6980 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6995 +/* 6984 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6995 +/* 6990 */ MCD_OPC_Decode, 210, 20, 142, 2, // Opcode: VSTRCHS +/* 6995 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7010 +/* 6999 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7010 +/* 7005 */ MCD_OPC_Decode, 215, 20, 143, 2, // Opcode: VSTRCZH +/* 7010 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 7077 +/* 7014 */ MCD_OPC_Decode, 209, 20, 144, 2, // Opcode: VSTRCH +/* 7019 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 7077 +/* 7023 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7038 +/* 7027 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 7038 +/* 7033 */ MCD_OPC_Decode, 214, 20, 141, 2, // Opcode: VSTRCZFS +/* 7038 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7053 +/* 7042 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 7053 +/* 7048 */ MCD_OPC_Decode, 208, 20, 142, 2, // Opcode: VSTRCFS +/* 7053 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7068 +/* 7057 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7068 +/* 7063 */ MCD_OPC_Decode, 213, 20, 143, 2, // Opcode: VSTRCZF +/* 7068 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7077 +/* 7072 */ MCD_OPC_Decode, 207, 20, 144, 2, // Opcode: VSTRCF +/* 7077 */ MCD_OPC_CheckPredicate, 22, 234, 46, // Skip to: 19091 +/* 7081 */ MCD_OPC_Decode, 204, 20, 145, 2, // Opcode: VSTRC +/* 7086 */ MCD_OPC_FilterValue, 140, 1, 15, 0, // Skip to: 7106 +/* 7091 */ MCD_OPC_CheckPredicate, 22, 220, 46, // Skip to: 19091 +/* 7095 */ MCD_OPC_CheckField, 16, 12, 0, 214, 46, // Skip to: 19091 +/* 7101 */ MCD_OPC_Decode, 255, 19, 146, 2, // Opcode: VPERM +/* 7106 */ MCD_OPC_FilterValue, 141, 1, 15, 0, // Skip to: 7126 +/* 7111 */ MCD_OPC_CheckPredicate, 22, 200, 46, // Skip to: 19091 +/* 7115 */ MCD_OPC_CheckField, 16, 12, 0, 194, 46, // Skip to: 19091 +/* 7121 */ MCD_OPC_Decode, 183, 20, 146, 2, // Opcode: VSEL +/* 7126 */ MCD_OPC_FilterValue, 142, 1, 104, 0, // Skip to: 7235 +/* 7131 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7134 */ MCD_OPC_FilterValue, 0, 177, 46, // Skip to: 19091 +/* 7138 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7141 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7174 +/* 7145 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7161 +/* 7152 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7226 +/* 7156 */ MCD_OPC_Decode, 188, 18, 146, 2, // Opcode: VFMSSB +/* 7161 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7226 +/* 7165 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7226 +/* 7169 */ MCD_OPC_Decode, 203, 21, 147, 2, // Opcode: WFMSSB +/* 7174 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7207 +/* 7178 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7194 +/* 7185 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7226 +/* 7189 */ MCD_OPC_Decode, 187, 18, 146, 2, // Opcode: VFMSDB +/* 7194 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7226 +/* 7198 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7226 +/* 7202 */ MCD_OPC_Decode, 202, 21, 148, 2, // Opcode: WFMSDB +/* 7207 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7226 +/* 7211 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7226 +/* 7215 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7226 +/* 7221 */ MCD_OPC_Decode, 204, 21, 146, 2, // Opcode: WFMSXB +/* 7226 */ MCD_OPC_CheckPredicate, 22, 85, 46, // Skip to: 19091 +/* 7230 */ MCD_OPC_Decode, 185, 18, 149, 2, // Opcode: VFMS +/* 7235 */ MCD_OPC_FilterValue, 143, 1, 104, 0, // Skip to: 7344 +/* 7240 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7243 */ MCD_OPC_FilterValue, 0, 68, 46, // Skip to: 19091 +/* 7247 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7250 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7283 +/* 7254 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7270 +/* 7261 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7335 +/* 7265 */ MCD_OPC_Decode, 177, 18, 146, 2, // Opcode: VFMASB +/* 7270 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7335 +/* 7274 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7335 +/* 7278 */ MCD_OPC_Decode, 192, 21, 147, 2, // Opcode: WFMASB +/* 7283 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7316 +/* 7287 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7290 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7303 +/* 7294 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7335 +/* 7298 */ MCD_OPC_Decode, 176, 18, 146, 2, // Opcode: VFMADB +/* 7303 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7335 +/* 7307 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7335 +/* 7311 */ MCD_OPC_Decode, 191, 21, 148, 2, // Opcode: WFMADB +/* 7316 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7335 +/* 7320 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7335 +/* 7324 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7335 +/* 7330 */ MCD_OPC_Decode, 193, 21, 146, 2, // Opcode: WFMAXB +/* 7335 */ MCD_OPC_CheckPredicate, 22, 232, 45, // Skip to: 19091 +/* 7339 */ MCD_OPC_Decode, 175, 18, 149, 2, // Opcode: VFMA +/* 7344 */ MCD_OPC_FilterValue, 148, 1, 65, 0, // Skip to: 7414 +/* 7349 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7352 */ MCD_OPC_FilterValue, 0, 215, 45, // Skip to: 19091 +/* 7356 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7359 */ MCD_OPC_FilterValue, 0, 208, 45, // Skip to: 19091 +/* 7363 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7366 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7379 +/* 7370 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7405 +/* 7374 */ MCD_OPC_Decode, 131, 20, 130, 2, // Opcode: VPKH +/* 7379 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7392 +/* 7383 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7405 +/* 7387 */ MCD_OPC_Decode, 129, 20, 130, 2, // Opcode: VPKF +/* 7392 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7405 +/* 7396 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7405 +/* 7400 */ MCD_OPC_Decode, 130, 20, 130, 2, // Opcode: VPKG +/* 7405 */ MCD_OPC_CheckPredicate, 22, 162, 45, // Skip to: 19091 +/* 7409 */ MCD_OPC_Decode, 128, 20, 131, 2, // Opcode: VPK +/* 7414 */ MCD_OPC_FilterValue, 149, 1, 132, 0, // Skip to: 7551 +/* 7419 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7422 */ MCD_OPC_FilterValue, 0, 145, 45, // Skip to: 19091 +/* 7426 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7429 */ MCD_OPC_FilterValue, 0, 138, 45, // Skip to: 19091 +/* 7433 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7436 */ MCD_OPC_FilterValue, 0, 131, 45, // Skip to: 19091 +/* 7440 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7443 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7476 +/* 7447 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7450 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7463 +/* 7454 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7542 +/* 7458 */ MCD_OPC_Decode, 137, 20, 130, 2, // Opcode: VPKLSH +/* 7463 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7542 +/* 7467 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7542 +/* 7471 */ MCD_OPC_Decode, 138, 20, 130, 2, // Opcode: VPKLSHS +/* 7476 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7509 +/* 7480 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7483 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7496 +/* 7487 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7542 +/* 7491 */ MCD_OPC_Decode, 133, 20, 130, 2, // Opcode: VPKLSF +/* 7496 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7542 +/* 7500 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7542 +/* 7504 */ MCD_OPC_Decode, 134, 20, 130, 2, // Opcode: VPKLSFS +/* 7509 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7542 +/* 7513 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7516 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7529 +/* 7520 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7542 +/* 7524 */ MCD_OPC_Decode, 135, 20, 130, 2, // Opcode: VPKLSG +/* 7529 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7542 +/* 7533 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7542 +/* 7537 */ MCD_OPC_Decode, 136, 20, 130, 2, // Opcode: VPKLSGS +/* 7542 */ MCD_OPC_CheckPredicate, 22, 25, 45, // Skip to: 19091 +/* 7546 */ MCD_OPC_Decode, 132, 20, 137, 2, // Opcode: VPKLS +/* 7551 */ MCD_OPC_FilterValue, 151, 1, 132, 0, // Skip to: 7688 +/* 7556 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7559 */ MCD_OPC_FilterValue, 0, 8, 45, // Skip to: 19091 +/* 7563 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7566 */ MCD_OPC_FilterValue, 0, 1, 45, // Skip to: 19091 +/* 7570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7573 */ MCD_OPC_FilterValue, 0, 250, 44, // Skip to: 19091 +/* 7577 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7580 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7613 +/* 7584 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7600 +/* 7591 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7679 +/* 7595 */ MCD_OPC_Decode, 144, 20, 130, 2, // Opcode: VPKSH +/* 7600 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7679 +/* 7604 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7679 +/* 7608 */ MCD_OPC_Decode, 145, 20, 130, 2, // Opcode: VPKSHS +/* 7613 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7646 +/* 7617 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7620 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7633 +/* 7624 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7679 +/* 7628 */ MCD_OPC_Decode, 140, 20, 130, 2, // Opcode: VPKSF +/* 7633 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7679 +/* 7637 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7679 +/* 7641 */ MCD_OPC_Decode, 141, 20, 130, 2, // Opcode: VPKSFS +/* 7646 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7679 +/* 7650 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7653 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7666 +/* 7657 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7679 +/* 7661 */ MCD_OPC_Decode, 142, 20, 130, 2, // Opcode: VPKSG +/* 7666 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7679 +/* 7670 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7679 +/* 7674 */ MCD_OPC_Decode, 143, 20, 130, 2, // Opcode: VPKSGS +/* 7679 */ MCD_OPC_CheckPredicate, 22, 144, 44, // Skip to: 19091 +/* 7683 */ MCD_OPC_Decode, 139, 20, 137, 2, // Opcode: VPKS +/* 7688 */ MCD_OPC_FilterValue, 158, 1, 104, 0, // Skip to: 7797 +/* 7693 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7696 */ MCD_OPC_FilterValue, 0, 127, 44, // Skip to: 19091 +/* 7700 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7703 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7736 +/* 7707 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7710 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7723 +/* 7714 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7788 +/* 7718 */ MCD_OPC_Decode, 194, 18, 146, 2, // Opcode: VFNMSSB +/* 7723 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7788 +/* 7727 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7788 +/* 7731 */ MCD_OPC_Decode, 210, 21, 147, 2, // Opcode: WFNMSSB +/* 7736 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7769 +/* 7740 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7743 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7756 +/* 7747 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7788 +/* 7751 */ MCD_OPC_Decode, 193, 18, 146, 2, // Opcode: VFNMSDB +/* 7756 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7788 +/* 7760 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7788 +/* 7764 */ MCD_OPC_Decode, 209, 21, 148, 2, // Opcode: WFNMSDB +/* 7769 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7788 +/* 7773 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7788 +/* 7777 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7788 +/* 7783 */ MCD_OPC_Decode, 211, 21, 146, 2, // Opcode: WFNMSXB +/* 7788 */ MCD_OPC_CheckPredicate, 23, 35, 44, // Skip to: 19091 +/* 7792 */ MCD_OPC_Decode, 192, 18, 149, 2, // Opcode: VFNMS +/* 7797 */ MCD_OPC_FilterValue, 159, 1, 104, 0, // Skip to: 7906 +/* 7802 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 7805 */ MCD_OPC_FilterValue, 0, 18, 44, // Skip to: 19091 +/* 7809 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 7812 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7845 +/* 7816 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7819 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7832 +/* 7823 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7897 +/* 7827 */ MCD_OPC_Decode, 191, 18, 146, 2, // Opcode: VFNMASB +/* 7832 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7897 +/* 7836 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7897 +/* 7840 */ MCD_OPC_Decode, 207, 21, 147, 2, // Opcode: WFNMASB +/* 7845 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7878 +/* 7849 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7852 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7865 +/* 7856 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7897 +/* 7860 */ MCD_OPC_Decode, 190, 18, 146, 2, // Opcode: VFNMADB +/* 7865 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7897 +/* 7869 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7897 +/* 7873 */ MCD_OPC_Decode, 206, 21, 148, 2, // Opcode: WFNMADB +/* 7878 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7897 +/* 7882 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7897 +/* 7886 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7897 +/* 7892 */ MCD_OPC_Decode, 208, 21, 146, 2, // Opcode: WFNMAXB +/* 7897 */ MCD_OPC_CheckPredicate, 23, 182, 43, // Skip to: 19091 +/* 7901 */ MCD_OPC_Decode, 189, 18, 149, 2, // Opcode: VFNMA +/* 7906 */ MCD_OPC_FilterValue, 161, 1, 65, 0, // Skip to: 7976 +/* 7911 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7914 */ MCD_OPC_FilterValue, 0, 165, 43, // Skip to: 19091 +/* 7918 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7921 */ MCD_OPC_FilterValue, 0, 158, 43, // Skip to: 19091 +/* 7925 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7928 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7941 +/* 7932 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7967 +/* 7936 */ MCD_OPC_Decode, 200, 19, 130, 2, // Opcode: VMLHB +/* 7941 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7954 +/* 7945 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7967 +/* 7949 */ MCD_OPC_Decode, 202, 19, 130, 2, // Opcode: VMLHH +/* 7954 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7967 +/* 7958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7967 +/* 7962 */ MCD_OPC_Decode, 201, 19, 130, 2, // Opcode: VMLHF +/* 7967 */ MCD_OPC_CheckPredicate, 22, 112, 43, // Skip to: 19091 +/* 7971 */ MCD_OPC_Decode, 199, 19, 131, 2, // Opcode: VMLH +/* 7976 */ MCD_OPC_FilterValue, 162, 1, 65, 0, // Skip to: 8046 +/* 7981 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 7984 */ MCD_OPC_FilterValue, 0, 95, 43, // Skip to: 19091 +/* 7988 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 7991 */ MCD_OPC_FilterValue, 0, 88, 43, // Skip to: 19091 +/* 7995 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7998 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8011 +/* 8002 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8037 +/* 8006 */ MCD_OPC_Decode, 193, 19, 130, 2, // Opcode: VMLB +/* 8011 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8024 +/* 8015 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8037 +/* 8019 */ MCD_OPC_Decode, 203, 19, 130, 2, // Opcode: VMLHW +/* 8024 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8037 +/* 8028 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8037 +/* 8032 */ MCD_OPC_Decode, 198, 19, 130, 2, // Opcode: VMLF +/* 8037 */ MCD_OPC_CheckPredicate, 22, 42, 43, // Skip to: 19091 +/* 8041 */ MCD_OPC_Decode, 192, 19, 131, 2, // Opcode: VML +/* 8046 */ MCD_OPC_FilterValue, 163, 1, 65, 0, // Skip to: 8116 +/* 8051 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8054 */ MCD_OPC_FilterValue, 0, 25, 43, // Skip to: 19091 +/* 8058 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8061 */ MCD_OPC_FilterValue, 0, 18, 43, // Skip to: 19091 +/* 8065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8068 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8081 +/* 8072 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8107 +/* 8076 */ MCD_OPC_Decode, 189, 19, 130, 2, // Opcode: VMHB +/* 8081 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8094 +/* 8085 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8107 +/* 8089 */ MCD_OPC_Decode, 191, 19, 130, 2, // Opcode: VMHH +/* 8094 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8107 +/* 8098 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8107 +/* 8102 */ MCD_OPC_Decode, 190, 19, 130, 2, // Opcode: VMHF +/* 8107 */ MCD_OPC_CheckPredicate, 22, 228, 42, // Skip to: 19091 +/* 8111 */ MCD_OPC_Decode, 188, 19, 131, 2, // Opcode: VMH +/* 8116 */ MCD_OPC_FilterValue, 164, 1, 65, 0, // Skip to: 8186 +/* 8121 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8124 */ MCD_OPC_FilterValue, 0, 211, 42, // Skip to: 19091 +/* 8128 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8131 */ MCD_OPC_FilterValue, 0, 204, 42, // Skip to: 19091 +/* 8135 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8138 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8151 +/* 8142 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8177 +/* 8146 */ MCD_OPC_Decode, 195, 19, 130, 2, // Opcode: VMLEB +/* 8151 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8164 +/* 8155 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8177 +/* 8159 */ MCD_OPC_Decode, 197, 19, 130, 2, // Opcode: VMLEH +/* 8164 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8177 +/* 8168 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8177 +/* 8172 */ MCD_OPC_Decode, 196, 19, 130, 2, // Opcode: VMLEF +/* 8177 */ MCD_OPC_CheckPredicate, 22, 158, 42, // Skip to: 19091 +/* 8181 */ MCD_OPC_Decode, 194, 19, 131, 2, // Opcode: VMLE +/* 8186 */ MCD_OPC_FilterValue, 165, 1, 65, 0, // Skip to: 8256 +/* 8191 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8194 */ MCD_OPC_FilterValue, 0, 141, 42, // Skip to: 19091 +/* 8198 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8201 */ MCD_OPC_FilterValue, 0, 134, 42, // Skip to: 19091 +/* 8205 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8208 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8221 +/* 8212 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8247 +/* 8216 */ MCD_OPC_Decode, 205, 19, 130, 2, // Opcode: VMLOB +/* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8234 +/* 8225 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8247 +/* 8229 */ MCD_OPC_Decode, 207, 19, 130, 2, // Opcode: VMLOH +/* 8234 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8247 +/* 8238 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8247 +/* 8242 */ MCD_OPC_Decode, 206, 19, 130, 2, // Opcode: VMLOF +/* 8247 */ MCD_OPC_CheckPredicate, 22, 88, 42, // Skip to: 19091 +/* 8251 */ MCD_OPC_Decode, 204, 19, 131, 2, // Opcode: VMLO +/* 8256 */ MCD_OPC_FilterValue, 166, 1, 65, 0, // Skip to: 8326 +/* 8261 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8264 */ MCD_OPC_FilterValue, 0, 71, 42, // Skip to: 19091 +/* 8268 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8271 */ MCD_OPC_FilterValue, 0, 64, 42, // Skip to: 19091 +/* 8275 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8278 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8291 +/* 8282 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8317 +/* 8286 */ MCD_OPC_Decode, 185, 19, 130, 2, // Opcode: VMEB +/* 8291 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8304 +/* 8295 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8317 +/* 8299 */ MCD_OPC_Decode, 187, 19, 130, 2, // Opcode: VMEH +/* 8304 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8317 +/* 8308 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8317 +/* 8312 */ MCD_OPC_Decode, 186, 19, 130, 2, // Opcode: VMEF +/* 8317 */ MCD_OPC_CheckPredicate, 22, 18, 42, // Skip to: 19091 +/* 8321 */ MCD_OPC_Decode, 184, 19, 131, 2, // Opcode: VME +/* 8326 */ MCD_OPC_FilterValue, 167, 1, 65, 0, // Skip to: 8396 +/* 8331 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8334 */ MCD_OPC_FilterValue, 0, 1, 42, // Skip to: 19091 +/* 8338 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8341 */ MCD_OPC_FilterValue, 0, 250, 41, // Skip to: 19091 +/* 8345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8348 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8361 +/* 8352 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8387 +/* 8356 */ MCD_OPC_Decode, 219, 19, 130, 2, // Opcode: VMOB +/* 8361 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8374 +/* 8365 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8387 +/* 8369 */ MCD_OPC_Decode, 221, 19, 130, 2, // Opcode: VMOH +/* 8374 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8387 +/* 8378 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8387 +/* 8382 */ MCD_OPC_Decode, 220, 19, 130, 2, // Opcode: VMOF +/* 8387 */ MCD_OPC_CheckPredicate, 22, 204, 41, // Skip to: 19091 +/* 8391 */ MCD_OPC_Decode, 218, 19, 131, 2, // Opcode: VMO +/* 8396 */ MCD_OPC_FilterValue, 169, 1, 58, 0, // Skip to: 8459 +/* 8401 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8404 */ MCD_OPC_FilterValue, 0, 187, 41, // Skip to: 19091 +/* 8408 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8411 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8424 +/* 8415 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8450 +/* 8419 */ MCD_OPC_Decode, 172, 19, 146, 2, // Opcode: VMALHB +/* 8424 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8437 +/* 8428 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8450 +/* 8432 */ MCD_OPC_Decode, 174, 19, 146, 2, // Opcode: VMALHH +/* 8437 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8450 +/* 8441 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8450 +/* 8445 */ MCD_OPC_Decode, 173, 19, 146, 2, // Opcode: VMALHF +/* 8450 */ MCD_OPC_CheckPredicate, 22, 141, 41, // Skip to: 19091 +/* 8454 */ MCD_OPC_Decode, 171, 19, 150, 2, // Opcode: VMALH +/* 8459 */ MCD_OPC_FilterValue, 170, 1, 58, 0, // Skip to: 8522 +/* 8464 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8467 */ MCD_OPC_FilterValue, 0, 124, 41, // Skip to: 19091 +/* 8471 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8474 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8487 +/* 8478 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8513 +/* 8482 */ MCD_OPC_Decode, 165, 19, 146, 2, // Opcode: VMALB +/* 8487 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8500 +/* 8491 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8513 +/* 8495 */ MCD_OPC_Decode, 175, 19, 146, 2, // Opcode: VMALHW +/* 8500 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8513 +/* 8504 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8513 +/* 8508 */ MCD_OPC_Decode, 170, 19, 146, 2, // Opcode: VMALF +/* 8513 */ MCD_OPC_CheckPredicate, 22, 78, 41, // Skip to: 19091 +/* 8517 */ MCD_OPC_Decode, 164, 19, 150, 2, // Opcode: VMAL +/* 8522 */ MCD_OPC_FilterValue, 171, 1, 58, 0, // Skip to: 8585 +/* 8527 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8530 */ MCD_OPC_FilterValue, 0, 61, 41, // Skip to: 19091 +/* 8534 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8537 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8550 +/* 8541 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8576 +/* 8545 */ MCD_OPC_Decode, 161, 19, 146, 2, // Opcode: VMAHB +/* 8550 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8563 +/* 8554 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8576 +/* 8558 */ MCD_OPC_Decode, 163, 19, 146, 2, // Opcode: VMAHH +/* 8563 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8576 +/* 8567 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8576 +/* 8571 */ MCD_OPC_Decode, 162, 19, 146, 2, // Opcode: VMAHF +/* 8576 */ MCD_OPC_CheckPredicate, 22, 15, 41, // Skip to: 19091 +/* 8580 */ MCD_OPC_Decode, 160, 19, 150, 2, // Opcode: VMAH +/* 8585 */ MCD_OPC_FilterValue, 172, 1, 58, 0, // Skip to: 8648 +/* 8590 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8593 */ MCD_OPC_FilterValue, 0, 254, 40, // Skip to: 19091 +/* 8597 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8600 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8613 +/* 8604 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8639 +/* 8608 */ MCD_OPC_Decode, 167, 19, 146, 2, // Opcode: VMALEB +/* 8613 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8626 +/* 8617 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8639 +/* 8621 */ MCD_OPC_Decode, 169, 19, 146, 2, // Opcode: VMALEH +/* 8626 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8639 +/* 8630 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8639 +/* 8634 */ MCD_OPC_Decode, 168, 19, 146, 2, // Opcode: VMALEF +/* 8639 */ MCD_OPC_CheckPredicate, 22, 208, 40, // Skip to: 19091 +/* 8643 */ MCD_OPC_Decode, 166, 19, 150, 2, // Opcode: VMALE +/* 8648 */ MCD_OPC_FilterValue, 173, 1, 58, 0, // Skip to: 8711 +/* 8653 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8656 */ MCD_OPC_FilterValue, 0, 191, 40, // Skip to: 19091 +/* 8660 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8663 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8676 +/* 8667 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8702 +/* 8671 */ MCD_OPC_Decode, 177, 19, 146, 2, // Opcode: VMALOB +/* 8676 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8689 +/* 8680 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8702 +/* 8684 */ MCD_OPC_Decode, 179, 19, 146, 2, // Opcode: VMALOH +/* 8689 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8702 +/* 8693 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8702 +/* 8697 */ MCD_OPC_Decode, 178, 19, 146, 2, // Opcode: VMALOF +/* 8702 */ MCD_OPC_CheckPredicate, 22, 145, 40, // Skip to: 19091 +/* 8706 */ MCD_OPC_Decode, 176, 19, 150, 2, // Opcode: VMALO +/* 8711 */ MCD_OPC_FilterValue, 174, 1, 58, 0, // Skip to: 8774 +/* 8716 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8719 */ MCD_OPC_FilterValue, 0, 128, 40, // Skip to: 19091 +/* 8723 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8726 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8739 +/* 8730 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8765 +/* 8734 */ MCD_OPC_Decode, 157, 19, 146, 2, // Opcode: VMAEB +/* 8739 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8752 +/* 8743 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8765 +/* 8747 */ MCD_OPC_Decode, 159, 19, 146, 2, // Opcode: VMAEH +/* 8752 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8765 +/* 8756 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8765 +/* 8760 */ MCD_OPC_Decode, 158, 19, 146, 2, // Opcode: VMAEF +/* 8765 */ MCD_OPC_CheckPredicate, 22, 82, 40, // Skip to: 19091 +/* 8769 */ MCD_OPC_Decode, 156, 19, 150, 2, // Opcode: VMAE +/* 8774 */ MCD_OPC_FilterValue, 175, 1, 58, 0, // Skip to: 8837 +/* 8779 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8782 */ MCD_OPC_FilterValue, 0, 65, 40, // Skip to: 19091 +/* 8786 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 8789 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8802 +/* 8793 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8828 +/* 8797 */ MCD_OPC_Decode, 181, 19, 146, 2, // Opcode: VMAOB +/* 8802 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8815 +/* 8806 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8828 +/* 8810 */ MCD_OPC_Decode, 183, 19, 146, 2, // Opcode: VMAOH +/* 8815 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8828 +/* 8819 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8828 +/* 8823 */ MCD_OPC_Decode, 182, 19, 146, 2, // Opcode: VMAOF +/* 8828 */ MCD_OPC_CheckPredicate, 22, 19, 40, // Skip to: 19091 +/* 8832 */ MCD_OPC_Decode, 180, 19, 150, 2, // Opcode: VMAO +/* 8837 */ MCD_OPC_FilterValue, 180, 1, 78, 0, // Skip to: 8920 +/* 8842 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 8845 */ MCD_OPC_FilterValue, 0, 2, 40, // Skip to: 19091 +/* 8849 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 8852 */ MCD_OPC_FilterValue, 0, 251, 39, // Skip to: 19091 +/* 8856 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 8859 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8872 +/* 8863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 8911 +/* 8867 */ MCD_OPC_Decode, 216, 18, 130, 2, // Opcode: VGFMB +/* 8872 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8885 +/* 8876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8911 +/* 8880 */ MCD_OPC_Decode, 219, 18, 130, 2, // Opcode: VGFMH +/* 8885 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8898 +/* 8889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8911 +/* 8893 */ MCD_OPC_Decode, 217, 18, 130, 2, // Opcode: VGFMF +/* 8898 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8911 +/* 8902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8911 +/* 8906 */ MCD_OPC_Decode, 218, 18, 130, 2, // Opcode: VGFMG +/* 8911 */ MCD_OPC_CheckPredicate, 22, 192, 39, // Skip to: 19091 +/* 8915 */ MCD_OPC_Decode, 210, 18, 131, 2, // Opcode: VGFM +/* 8920 */ MCD_OPC_FilterValue, 184, 1, 31, 0, // Skip to: 8956 +/* 8925 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8928 */ MCD_OPC_FilterValue, 0, 175, 39, // Skip to: 19091 +/* 8932 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 8947 +/* 8936 */ MCD_OPC_CheckField, 24, 4, 3, 5, 0, // Skip to: 8947 +/* 8942 */ MCD_OPC_Decode, 234, 19, 144, 2, // Opcode: VMSLG +/* 8947 */ MCD_OPC_CheckPredicate, 23, 156, 39, // Skip to: 19091 +/* 8951 */ MCD_OPC_Decode, 233, 19, 145, 2, // Opcode: VMSL +/* 8956 */ MCD_OPC_FilterValue, 185, 1, 31, 0, // Skip to: 8992 +/* 8961 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 8964 */ MCD_OPC_FilterValue, 0, 139, 39, // Skip to: 19091 +/* 8968 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 8983 +/* 8972 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 8983 +/* 8978 */ MCD_OPC_Decode, 216, 16, 146, 2, // Opcode: VACCCQ +/* 8983 */ MCD_OPC_CheckPredicate, 22, 120, 39, // Skip to: 19091 +/* 8987 */ MCD_OPC_Decode, 215, 16, 150, 2, // Opcode: VACCC +/* 8992 */ MCD_OPC_FilterValue, 187, 1, 31, 0, // Skip to: 9028 +/* 8997 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 9000 */ MCD_OPC_FilterValue, 0, 103, 39, // Skip to: 19091 +/* 9004 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9019 +/* 9008 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9019 +/* 9014 */ MCD_OPC_Decode, 221, 16, 146, 2, // Opcode: VACQ +/* 9019 */ MCD_OPC_CheckPredicate, 22, 84, 39, // Skip to: 19091 +/* 9023 */ MCD_OPC_Decode, 212, 16, 150, 2, // Opcode: VAC +/* 9028 */ MCD_OPC_FilterValue, 188, 1, 71, 0, // Skip to: 9104 +/* 9033 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 9036 */ MCD_OPC_FilterValue, 0, 67, 39, // Skip to: 19091 +/* 9040 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 9043 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9056 +/* 9047 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 9095 +/* 9051 */ MCD_OPC_Decode, 212, 18, 146, 2, // Opcode: VGFMAB +/* 9056 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9069 +/* 9060 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 9095 +/* 9064 */ MCD_OPC_Decode, 215, 18, 146, 2, // Opcode: VGFMAH +/* 9069 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9082 +/* 9073 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9095 +/* 9077 */ MCD_OPC_Decode, 213, 18, 146, 2, // Opcode: VGFMAF +/* 9082 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9095 +/* 9086 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9095 +/* 9090 */ MCD_OPC_Decode, 214, 18, 146, 2, // Opcode: VGFMAG +/* 9095 */ MCD_OPC_CheckPredicate, 22, 8, 39, // Skip to: 19091 +/* 9099 */ MCD_OPC_Decode, 211, 18, 150, 2, // Opcode: VGFMA +/* 9104 */ MCD_OPC_FilterValue, 189, 1, 31, 0, // Skip to: 9140 +/* 9109 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 9112 */ MCD_OPC_FilterValue, 0, 247, 38, // Skip to: 19091 +/* 9116 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9131 +/* 9120 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9131 +/* 9126 */ MCD_OPC_Decode, 167, 20, 146, 2, // Opcode: VSBCBIQ +/* 9131 */ MCD_OPC_CheckPredicate, 22, 228, 38, // Skip to: 19091 +/* 9135 */ MCD_OPC_Decode, 166, 20, 150, 2, // Opcode: VSBCBI +/* 9140 */ MCD_OPC_FilterValue, 191, 1, 31, 0, // Skip to: 9176 +/* 9145 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 9148 */ MCD_OPC_FilterValue, 0, 211, 38, // Skip to: 19091 +/* 9152 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9167 +/* 9156 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9167 +/* 9162 */ MCD_OPC_Decode, 169, 20, 146, 2, // Opcode: VSBIQ +/* 9167 */ MCD_OPC_CheckPredicate, 22, 192, 38, // Skip to: 19091 +/* 9171 */ MCD_OPC_Decode, 168, 20, 150, 2, // Opcode: VSBI +/* 9176 */ MCD_OPC_FilterValue, 192, 1, 54, 0, // Skip to: 9235 +/* 9181 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9184 */ MCD_OPC_FilterValue, 0, 175, 38, // Skip to: 19091 +/* 9188 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9191 */ MCD_OPC_FilterValue, 0, 168, 38, // Skip to: 19091 +/* 9195 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9198 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9226 +/* 9202 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9217 +/* 9206 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9217 +/* 9212 */ MCD_OPC_Decode, 252, 20, 151, 2, // Opcode: WCLGDB +/* 9217 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9226 +/* 9221 */ MCD_OPC_Decode, 145, 17, 152, 2, // Opcode: VCLGDB +/* 9226 */ MCD_OPC_CheckPredicate, 22, 133, 38, // Skip to: 19091 +/* 9230 */ MCD_OPC_Decode, 144, 17, 153, 2, // Opcode: VCLGD +/* 9235 */ MCD_OPC_FilterValue, 193, 1, 54, 0, // Skip to: 9294 +/* 9240 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9243 */ MCD_OPC_FilterValue, 0, 116, 38, // Skip to: 19091 +/* 9247 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9250 */ MCD_OPC_FilterValue, 0, 109, 38, // Skip to: 19091 +/* 9254 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9257 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9285 +/* 9261 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9276 +/* 9265 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9276 +/* 9271 */ MCD_OPC_Decode, 250, 20, 151, 2, // Opcode: WCDLGB +/* 9276 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9285 +/* 9280 */ MCD_OPC_Decode, 241, 16, 152, 2, // Opcode: VCDLGB +/* 9285 */ MCD_OPC_CheckPredicate, 22, 74, 38, // Skip to: 19091 +/* 9289 */ MCD_OPC_Decode, 240, 16, 153, 2, // Opcode: VCDLG +/* 9294 */ MCD_OPC_FilterValue, 194, 1, 54, 0, // Skip to: 9353 +/* 9299 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9302 */ MCD_OPC_FilterValue, 0, 57, 38, // Skip to: 19091 +/* 9306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9309 */ MCD_OPC_FilterValue, 0, 50, 38, // Skip to: 19091 +/* 9313 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9316 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9344 +/* 9320 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9335 +/* 9324 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9335 +/* 9330 */ MCD_OPC_Decode, 251, 20, 151, 2, // Opcode: WCGDB +/* 9335 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9344 +/* 9339 */ MCD_OPC_Decode, 252, 16, 152, 2, // Opcode: VCGDB +/* 9344 */ MCD_OPC_CheckPredicate, 22, 15, 38, // Skip to: 19091 +/* 9348 */ MCD_OPC_Decode, 251, 16, 153, 2, // Opcode: VCGD +/* 9353 */ MCD_OPC_FilterValue, 195, 1, 54, 0, // Skip to: 9412 +/* 9358 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9361 */ MCD_OPC_FilterValue, 0, 254, 37, // Skip to: 19091 +/* 9365 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9368 */ MCD_OPC_FilterValue, 0, 247, 37, // Skip to: 19091 +/* 9372 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9375 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9403 +/* 9379 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9394 +/* 9383 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9394 +/* 9389 */ MCD_OPC_Decode, 249, 20, 151, 2, // Opcode: WCDGB +/* 9394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9403 +/* 9398 */ MCD_OPC_Decode, 239, 16, 152, 2, // Opcode: VCDGB +/* 9403 */ MCD_OPC_CheckPredicate, 22, 212, 37, // Skip to: 19091 +/* 9407 */ MCD_OPC_Decode, 238, 16, 153, 2, // Opcode: VCDG +/* 9412 */ MCD_OPC_FilterValue, 196, 1, 67, 0, // Skip to: 9484 +/* 9417 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9420 */ MCD_OPC_FilterValue, 0, 195, 37, // Skip to: 19091 +/* 9424 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 9427 */ MCD_OPC_FilterValue, 0, 188, 37, // Skip to: 19091 +/* 9431 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 9434 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9447 +/* 9438 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 9475 +/* 9442 */ MCD_OPC_Decode, 240, 18, 254, 1, // Opcode: VLDEB +/* 9447 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9461 +/* 9452 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 9475 +/* 9456 */ MCD_OPC_Decode, 224, 21, 154, 2, // Opcode: WLDEB +/* 9461 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9475 +/* 9466 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9475 +/* 9470 */ MCD_OPC_Decode, 181, 21, 155, 2, // Opcode: WFLLD +/* 9475 */ MCD_OPC_CheckPredicate, 22, 140, 37, // Skip to: 19091 +/* 9479 */ MCD_OPC_Decode, 239, 18, 156, 2, // Opcode: VLDE +/* 9484 */ MCD_OPC_FilterValue, 197, 1, 73, 0, // Skip to: 9562 +/* 9489 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9492 */ MCD_OPC_FilterValue, 0, 123, 37, // Skip to: 19091 +/* 9496 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9499 */ MCD_OPC_FilterValue, 0, 116, 37, // Skip to: 19091 +/* 9503 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9506 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9534 +/* 9510 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9525 +/* 9514 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9525 +/* 9520 */ MCD_OPC_Decode, 225, 21, 157, 2, // Opcode: WLEDB +/* 9525 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9553 +/* 9529 */ MCD_OPC_Decode, 243, 18, 152, 2, // Opcode: VLEDB +/* 9534 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9553 +/* 9538 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9553 +/* 9542 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9553 +/* 9548 */ MCD_OPC_Decode, 190, 21, 158, 2, // Opcode: WFLRX +/* 9553 */ MCD_OPC_CheckPredicate, 22, 62, 37, // Skip to: 19091 +/* 9557 */ MCD_OPC_Decode, 242, 18, 153, 2, // Opcode: VLED +/* 9562 */ MCD_OPC_FilterValue, 199, 1, 101, 0, // Skip to: 9668 +/* 9567 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9570 */ MCD_OPC_FilterValue, 0, 45, 37, // Skip to: 19091 +/* 9574 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9577 */ MCD_OPC_FilterValue, 0, 38, 37, // Skip to: 19091 +/* 9581 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 9584 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 9612 +/* 9588 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9603 +/* 9592 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9603 +/* 9598 */ MCD_OPC_Decode, 154, 21, 159, 2, // Opcode: WFISB +/* 9603 */ MCD_OPC_CheckPredicate, 23, 52, 0, // Skip to: 9659 +/* 9607 */ MCD_OPC_Decode, 151, 18, 152, 2, // Opcode: VFISB +/* 9612 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9640 +/* 9616 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9631 +/* 9620 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9631 +/* 9626 */ MCD_OPC_Decode, 153, 21, 151, 2, // Opcode: WFIDB +/* 9631 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9659 +/* 9635 */ MCD_OPC_Decode, 150, 18, 152, 2, // Opcode: VFIDB +/* 9640 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9659 +/* 9644 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9659 +/* 9648 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9659 +/* 9654 */ MCD_OPC_Decode, 155, 21, 160, 2, // Opcode: WFIXB +/* 9659 */ MCD_OPC_CheckPredicate, 22, 212, 36, // Skip to: 19091 +/* 9663 */ MCD_OPC_Decode, 149, 18, 153, 2, // Opcode: VFI +/* 9668 */ MCD_OPC_FilterValue, 202, 1, 65, 0, // Skip to: 9738 +/* 9673 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9676 */ MCD_OPC_FilterValue, 0, 195, 36, // Skip to: 19091 +/* 9680 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 9683 */ MCD_OPC_FilterValue, 0, 188, 36, // Skip to: 19091 +/* 9687 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 9690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9703 +/* 9694 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9729 +/* 9698 */ MCD_OPC_Decode, 176, 21, 161, 2, // Opcode: WFKSB +/* 9703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9716 +/* 9707 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9729 +/* 9711 */ MCD_OPC_Decode, 157, 21, 162, 2, // Opcode: WFKDB +/* 9716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9729 +/* 9720 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9729 +/* 9724 */ MCD_OPC_Decode, 177, 21, 254, 1, // Opcode: WFKXB +/* 9729 */ MCD_OPC_CheckPredicate, 22, 142, 36, // Skip to: 19091 +/* 9733 */ MCD_OPC_Decode, 156, 21, 163, 2, // Opcode: WFK +/* 9738 */ MCD_OPC_FilterValue, 203, 1, 65, 0, // Skip to: 9808 +/* 9743 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9746 */ MCD_OPC_FilterValue, 0, 125, 36, // Skip to: 19091 +/* 9750 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 9753 */ MCD_OPC_FilterValue, 0, 118, 36, // Skip to: 19091 +/* 9757 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 9760 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9773 +/* 9764 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9799 +/* 9768 */ MCD_OPC_Decode, 148, 21, 161, 2, // Opcode: WFCSB +/* 9773 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9786 +/* 9777 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9799 +/* 9781 */ MCD_OPC_Decode, 129, 21, 162, 2, // Opcode: WFCDB +/* 9786 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9799 +/* 9790 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9799 +/* 9794 */ MCD_OPC_Decode, 149, 21, 254, 1, // Opcode: WFCXB +/* 9799 */ MCD_OPC_CheckPredicate, 22, 72, 36, // Skip to: 19091 +/* 9803 */ MCD_OPC_Decode, 128, 21, 163, 2, // Opcode: WFC +/* 9808 */ MCD_OPC_FilterValue, 204, 1, 49, 1, // Skip to: 10118 +/* 9813 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 9816 */ MCD_OPC_FilterValue, 0, 55, 36, // Skip to: 19091 +/* 9820 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 9823 */ MCD_OPC_FilterValue, 0, 48, 36, // Skip to: 19091 +/* 9827 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 9830 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9843 +/* 9834 */ MCD_OPC_CheckPredicate, 23, 200, 0, // Skip to: 10038 +/* 9838 */ MCD_OPC_Decode, 165, 18, 254, 1, // Opcode: VFLCSB +/* 9843 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9856 +/* 9847 */ MCD_OPC_CheckPredicate, 22, 187, 0, // Skip to: 10038 +/* 9851 */ MCD_OPC_Decode, 164, 18, 254, 1, // Opcode: VFLCDB +/* 9856 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9870 +/* 9861 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 10038 +/* 9865 */ MCD_OPC_Decode, 179, 21, 161, 2, // Opcode: WFLCSB +/* 9870 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9884 +/* 9875 */ MCD_OPC_CheckPredicate, 22, 159, 0, // Skip to: 10038 +/* 9879 */ MCD_OPC_Decode, 178, 21, 162, 2, // Opcode: WFLCDB +/* 9884 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 9898 +/* 9889 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 10038 +/* 9893 */ MCD_OPC_Decode, 180, 21, 254, 1, // Opcode: WFLCXB +/* 9898 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 9912 +/* 9903 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 10038 +/* 9907 */ MCD_OPC_Decode, 169, 18, 254, 1, // Opcode: VFLNSB +/* 9912 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 9926 +/* 9917 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 10038 +/* 9921 */ MCD_OPC_Decode, 168, 18, 254, 1, // Opcode: VFLNDB +/* 9926 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 9940 +/* 9931 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 10038 +/* 9935 */ MCD_OPC_Decode, 184, 21, 161, 2, // Opcode: WFLNSB +/* 9940 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 9954 +/* 9945 */ MCD_OPC_CheckPredicate, 22, 89, 0, // Skip to: 10038 +/* 9949 */ MCD_OPC_Decode, 183, 21, 162, 2, // Opcode: WFLNDB +/* 9954 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 9968 +/* 9959 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 10038 +/* 9963 */ MCD_OPC_Decode, 185, 21, 254, 1, // Opcode: WFLNXB +/* 9968 */ MCD_OPC_FilterValue, 130, 4, 9, 0, // Skip to: 9982 +/* 9973 */ MCD_OPC_CheckPredicate, 23, 61, 0, // Skip to: 10038 +/* 9977 */ MCD_OPC_Decode, 171, 18, 254, 1, // Opcode: VFLPSB +/* 9982 */ MCD_OPC_FilterValue, 131, 4, 9, 0, // Skip to: 9996 +/* 9987 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10038 +/* 9991 */ MCD_OPC_Decode, 170, 18, 254, 1, // Opcode: VFLPDB +/* 9996 */ MCD_OPC_FilterValue, 130, 5, 9, 0, // Skip to: 10010 +/* 10001 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10038 +/* 10005 */ MCD_OPC_Decode, 187, 21, 161, 2, // Opcode: WFLPSB +/* 10010 */ MCD_OPC_FilterValue, 131, 5, 9, 0, // Skip to: 10024 +/* 10015 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10038 +/* 10019 */ MCD_OPC_Decode, 186, 21, 162, 2, // Opcode: WFLPDB +/* 10024 */ MCD_OPC_FilterValue, 132, 5, 9, 0, // Skip to: 10038 +/* 10029 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10038 +/* 10033 */ MCD_OPC_Decode, 188, 21, 254, 1, // Opcode: WFLPXB +/* 10038 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 10041 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10054 +/* 10045 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10109 +/* 10049 */ MCD_OPC_Decode, 197, 18, 128, 2, // Opcode: VFPSOSB +/* 10054 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10067 +/* 10058 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10109 +/* 10062 */ MCD_OPC_Decode, 196, 18, 128, 2, // Opcode: VFPSODB +/* 10067 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10081 +/* 10072 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10109 +/* 10076 */ MCD_OPC_Decode, 213, 21, 164, 2, // Opcode: WFPSOSB +/* 10081 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10095 +/* 10086 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10109 +/* 10090 */ MCD_OPC_Decode, 212, 21, 165, 2, // Opcode: WFPSODB +/* 10095 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10109 +/* 10100 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10109 +/* 10104 */ MCD_OPC_Decode, 214, 21, 128, 2, // Opcode: WFPSOXB +/* 10109 */ MCD_OPC_CheckPredicate, 22, 18, 35, // Skip to: 19091 +/* 10113 */ MCD_OPC_Decode, 195, 18, 153, 2, // Opcode: VFPSO +/* 10118 */ MCD_OPC_FilterValue, 206, 1, 94, 0, // Skip to: 10217 +/* 10123 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10126 */ MCD_OPC_FilterValue, 0, 1, 35, // Skip to: 19091 +/* 10130 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... +/* 10133 */ MCD_OPC_FilterValue, 0, 250, 34, // Skip to: 19091 +/* 10137 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 10140 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10153 +/* 10144 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10208 +/* 10148 */ MCD_OPC_Decode, 202, 18, 254, 1, // Opcode: VFSQSB +/* 10153 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10166 +/* 10157 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10208 +/* 10161 */ MCD_OPC_Decode, 201, 18, 254, 1, // Opcode: VFSQDB +/* 10166 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10180 +/* 10171 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10208 +/* 10175 */ MCD_OPC_Decode, 217, 21, 161, 2, // Opcode: WFSQSB +/* 10180 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10194 +/* 10185 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10208 +/* 10189 */ MCD_OPC_Decode, 216, 21, 162, 2, // Opcode: WFSQDB +/* 10194 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10208 +/* 10199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10208 +/* 10203 */ MCD_OPC_Decode, 218, 21, 254, 1, // Opcode: WFSQXB +/* 10208 */ MCD_OPC_CheckPredicate, 22, 175, 34, // Skip to: 19091 +/* 10212 */ MCD_OPC_Decode, 200, 18, 156, 2, // Opcode: VFSQ +/* 10217 */ MCD_OPC_FilterValue, 212, 1, 65, 0, // Skip to: 10287 +/* 10222 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10225 */ MCD_OPC_FilterValue, 0, 158, 34, // Skip to: 19091 +/* 10229 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10232 */ MCD_OPC_FilterValue, 0, 151, 34, // Skip to: 19091 +/* 10236 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10239 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10252 +/* 10243 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10278 +/* 10247 */ MCD_OPC_Decode, 244, 20, 254, 1, // Opcode: VUPLLB +/* 10252 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10265 +/* 10256 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10278 +/* 10260 */ MCD_OPC_Decode, 246, 20, 254, 1, // Opcode: VUPLLH +/* 10265 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10278 +/* 10269 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10278 +/* 10273 */ MCD_OPC_Decode, 245, 20, 254, 1, // Opcode: VUPLLF +/* 10278 */ MCD_OPC_CheckPredicate, 22, 105, 34, // Skip to: 19091 +/* 10282 */ MCD_OPC_Decode, 243, 20, 255, 1, // Opcode: VUPLL +/* 10287 */ MCD_OPC_FilterValue, 213, 1, 65, 0, // Skip to: 10357 +/* 10292 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10295 */ MCD_OPC_FilterValue, 0, 88, 34, // Skip to: 19091 +/* 10299 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10302 */ MCD_OPC_FilterValue, 0, 81, 34, // Skip to: 19091 +/* 10306 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10309 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10322 +/* 10313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10348 +/* 10317 */ MCD_OPC_Decode, 239, 20, 254, 1, // Opcode: VUPLHB +/* 10322 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10335 +/* 10326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10348 +/* 10330 */ MCD_OPC_Decode, 241, 20, 254, 1, // Opcode: VUPLHH +/* 10335 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10348 +/* 10339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10348 +/* 10343 */ MCD_OPC_Decode, 240, 20, 254, 1, // Opcode: VUPLHF +/* 10348 */ MCD_OPC_CheckPredicate, 22, 35, 34, // Skip to: 19091 +/* 10352 */ MCD_OPC_Decode, 238, 20, 255, 1, // Opcode: VUPLH +/* 10357 */ MCD_OPC_FilterValue, 214, 1, 65, 0, // Skip to: 10427 +/* 10362 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10365 */ MCD_OPC_FilterValue, 0, 18, 34, // Skip to: 19091 +/* 10369 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10372 */ MCD_OPC_FilterValue, 0, 11, 34, // Skip to: 19091 +/* 10376 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10379 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10392 +/* 10383 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10418 +/* 10387 */ MCD_OPC_Decode, 236, 20, 254, 1, // Opcode: VUPLB +/* 10392 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10405 +/* 10396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10418 +/* 10400 */ MCD_OPC_Decode, 242, 20, 254, 1, // Opcode: VUPLHW +/* 10405 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10418 +/* 10409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10418 +/* 10413 */ MCD_OPC_Decode, 237, 20, 254, 1, // Opcode: VUPLF +/* 10418 */ MCD_OPC_CheckPredicate, 22, 221, 33, // Skip to: 19091 +/* 10422 */ MCD_OPC_Decode, 235, 20, 255, 1, // Opcode: VUPL +/* 10427 */ MCD_OPC_FilterValue, 215, 1, 65, 0, // Skip to: 10497 +/* 10432 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10435 */ MCD_OPC_FilterValue, 0, 204, 33, // Skip to: 19091 +/* 10439 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10442 */ MCD_OPC_FilterValue, 0, 197, 33, // Skip to: 19091 +/* 10446 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10449 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10462 +/* 10453 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10488 +/* 10457 */ MCD_OPC_Decode, 231, 20, 254, 1, // Opcode: VUPHB +/* 10462 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10475 +/* 10466 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10488 +/* 10470 */ MCD_OPC_Decode, 233, 20, 254, 1, // Opcode: VUPHH +/* 10475 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10488 +/* 10479 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10488 +/* 10483 */ MCD_OPC_Decode, 232, 20, 254, 1, // Opcode: VUPHF +/* 10488 */ MCD_OPC_CheckPredicate, 22, 151, 33, // Skip to: 19091 +/* 10492 */ MCD_OPC_Decode, 230, 20, 255, 1, // Opcode: VUPH +/* 10497 */ MCD_OPC_FilterValue, 216, 1, 21, 0, // Skip to: 10523 +/* 10502 */ MCD_OPC_CheckPredicate, 22, 137, 33, // Skip to: 19091 +/* 10506 */ MCD_OPC_CheckField, 12, 20, 0, 131, 33, // Skip to: 19091 +/* 10512 */ MCD_OPC_CheckField, 8, 2, 0, 125, 33, // Skip to: 19091 +/* 10518 */ MCD_OPC_Decode, 228, 20, 254, 1, // Opcode: VTM +/* 10523 */ MCD_OPC_FilterValue, 217, 1, 78, 0, // Skip to: 10606 +/* 10528 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10531 */ MCD_OPC_FilterValue, 0, 108, 33, // Skip to: 19091 +/* 10535 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10538 */ MCD_OPC_FilterValue, 0, 101, 33, // Skip to: 19091 +/* 10542 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10558 +/* 10549 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10597 +/* 10553 */ MCD_OPC_Decode, 168, 17, 254, 1, // Opcode: VECLB +/* 10558 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10571 +/* 10562 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10597 +/* 10566 */ MCD_OPC_Decode, 171, 17, 254, 1, // Opcode: VECLH +/* 10571 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10584 +/* 10575 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10597 +/* 10579 */ MCD_OPC_Decode, 169, 17, 254, 1, // Opcode: VECLF +/* 10584 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10597 +/* 10588 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10597 +/* 10592 */ MCD_OPC_Decode, 170, 17, 254, 1, // Opcode: VECLG +/* 10597 */ MCD_OPC_CheckPredicate, 22, 42, 33, // Skip to: 19091 +/* 10601 */ MCD_OPC_Decode, 167, 17, 255, 1, // Opcode: VECL +/* 10606 */ MCD_OPC_FilterValue, 219, 1, 78, 0, // Skip to: 10689 +/* 10611 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10614 */ MCD_OPC_FilterValue, 0, 25, 33, // Skip to: 19091 +/* 10618 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10621 */ MCD_OPC_FilterValue, 0, 18, 33, // Skip to: 19091 +/* 10625 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10628 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10641 +/* 10632 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10680 +/* 10636 */ MCD_OPC_Decode, 163, 17, 254, 1, // Opcode: VECB +/* 10641 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10654 +/* 10645 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10680 +/* 10649 */ MCD_OPC_Decode, 166, 17, 254, 1, // Opcode: VECH +/* 10654 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10667 +/* 10658 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10680 +/* 10662 */ MCD_OPC_Decode, 164, 17, 254, 1, // Opcode: VECF +/* 10667 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10680 +/* 10671 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10680 +/* 10675 */ MCD_OPC_Decode, 165, 17, 254, 1, // Opcode: VECG +/* 10680 */ MCD_OPC_CheckPredicate, 22, 215, 32, // Skip to: 19091 +/* 10684 */ MCD_OPC_Decode, 162, 17, 255, 1, // Opcode: VEC +/* 10689 */ MCD_OPC_FilterValue, 222, 1, 78, 0, // Skip to: 10772 +/* 10694 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10697 */ MCD_OPC_FilterValue, 0, 198, 32, // Skip to: 19091 +/* 10701 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10704 */ MCD_OPC_FilterValue, 0, 191, 32, // Skip to: 19091 +/* 10708 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10711 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10724 +/* 10715 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10763 +/* 10719 */ MCD_OPC_Decode, 235, 18, 254, 1, // Opcode: VLCB +/* 10724 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10737 +/* 10728 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10763 +/* 10732 */ MCD_OPC_Decode, 238, 18, 254, 1, // Opcode: VLCH +/* 10737 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10750 +/* 10741 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10763 +/* 10745 */ MCD_OPC_Decode, 236, 18, 254, 1, // Opcode: VLCF +/* 10750 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10763 +/* 10754 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10763 +/* 10758 */ MCD_OPC_Decode, 237, 18, 254, 1, // Opcode: VLCG +/* 10763 */ MCD_OPC_CheckPredicate, 22, 132, 32, // Skip to: 19091 +/* 10767 */ MCD_OPC_Decode, 234, 18, 255, 1, // Opcode: VLC +/* 10772 */ MCD_OPC_FilterValue, 223, 1, 78, 0, // Skip to: 10855 +/* 10777 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 10780 */ MCD_OPC_FilterValue, 0, 115, 32, // Skip to: 19091 +/* 10784 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... +/* 10787 */ MCD_OPC_FilterValue, 0, 108, 32, // Skip to: 19091 +/* 10791 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 10794 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10807 +/* 10798 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10846 +/* 10802 */ MCD_OPC_Decode, 138, 19, 254, 1, // Opcode: VLPB +/* 10807 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10820 +/* 10811 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10846 +/* 10815 */ MCD_OPC_Decode, 141, 19, 254, 1, // Opcode: VLPH +/* 10820 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10833 +/* 10824 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10846 +/* 10828 */ MCD_OPC_Decode, 139, 19, 254, 1, // Opcode: VLPF +/* 10833 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10846 +/* 10837 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10846 +/* 10841 */ MCD_OPC_Decode, 140, 19, 254, 1, // Opcode: VLPG +/* 10846 */ MCD_OPC_CheckPredicate, 22, 49, 32, // Skip to: 19091 +/* 10850 */ MCD_OPC_Decode, 137, 19, 255, 1, // Opcode: VLP +/* 10855 */ MCD_OPC_FilterValue, 226, 1, 94, 0, // Skip to: 10954 +/* 10860 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10863 */ MCD_OPC_FilterValue, 0, 32, 32, // Skip to: 19091 +/* 10867 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 10870 */ MCD_OPC_FilterValue, 0, 25, 32, // Skip to: 19091 +/* 10874 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 10877 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10890 +/* 10881 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10945 +/* 10885 */ MCD_OPC_Decode, 203, 18, 130, 2, // Opcode: VFSSB +/* 10890 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10903 +/* 10894 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10945 +/* 10898 */ MCD_OPC_Decode, 199, 18, 130, 2, // Opcode: VFSDB +/* 10903 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10917 +/* 10908 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10945 +/* 10912 */ MCD_OPC_Decode, 219, 21, 166, 2, // Opcode: WFSSB +/* 10917 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10931 +/* 10922 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10945 +/* 10926 */ MCD_OPC_Decode, 215, 21, 167, 2, // Opcode: WFSDB +/* 10931 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10945 +/* 10936 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10945 +/* 10940 */ MCD_OPC_Decode, 220, 21, 130, 2, // Opcode: WFSXB +/* 10945 */ MCD_OPC_CheckPredicate, 22, 206, 31, // Skip to: 19091 +/* 10949 */ MCD_OPC_Decode, 198, 18, 168, 2, // Opcode: VFS +/* 10954 */ MCD_OPC_FilterValue, 227, 1, 94, 0, // Skip to: 11053 +/* 10959 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 10962 */ MCD_OPC_FilterValue, 0, 189, 31, // Skip to: 19091 +/* 10966 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 10969 */ MCD_OPC_FilterValue, 0, 182, 31, // Skip to: 19091 +/* 10973 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 10976 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10989 +/* 10980 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11044 +/* 10984 */ MCD_OPC_Decode, 232, 17, 130, 2, // Opcode: VFASB +/* 10989 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11002 +/* 10993 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11044 +/* 10997 */ MCD_OPC_Decode, 218, 17, 130, 2, // Opcode: VFADB +/* 11002 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11016 +/* 11007 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11044 +/* 11011 */ MCD_OPC_Decode, 254, 20, 166, 2, // Opcode: WFASB +/* 11016 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11030 +/* 11021 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11044 +/* 11025 */ MCD_OPC_Decode, 253, 20, 167, 2, // Opcode: WFADB +/* 11030 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11044 +/* 11035 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11044 +/* 11039 */ MCD_OPC_Decode, 255, 20, 130, 2, // Opcode: WFAXB +/* 11044 */ MCD_OPC_CheckPredicate, 22, 107, 31, // Skip to: 19091 +/* 11048 */ MCD_OPC_Decode, 217, 17, 168, 2, // Opcode: VFA +/* 11053 */ MCD_OPC_FilterValue, 229, 1, 94, 0, // Skip to: 11152 +/* 11058 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11061 */ MCD_OPC_FilterValue, 0, 90, 31, // Skip to: 19091 +/* 11065 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 11068 */ MCD_OPC_FilterValue, 0, 83, 31, // Skip to: 19091 +/* 11072 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 11075 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11088 +/* 11079 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11143 +/* 11083 */ MCD_OPC_Decode, 250, 17, 130, 2, // Opcode: VFDSB +/* 11088 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11101 +/* 11092 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11143 +/* 11096 */ MCD_OPC_Decode, 249, 17, 130, 2, // Opcode: VFDDB +/* 11101 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11115 +/* 11106 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11143 +/* 11110 */ MCD_OPC_Decode, 151, 21, 166, 2, // Opcode: WFDSB +/* 11115 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11129 +/* 11120 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11143 +/* 11124 */ MCD_OPC_Decode, 150, 21, 167, 2, // Opcode: WFDDB +/* 11129 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11143 +/* 11134 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11143 +/* 11138 */ MCD_OPC_Decode, 152, 21, 130, 2, // Opcode: WFDXB +/* 11143 */ MCD_OPC_CheckPredicate, 22, 8, 31, // Skip to: 19091 +/* 11147 */ MCD_OPC_Decode, 248, 17, 168, 2, // Opcode: VFD +/* 11152 */ MCD_OPC_FilterValue, 231, 1, 94, 0, // Skip to: 11251 +/* 11157 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11160 */ MCD_OPC_FilterValue, 0, 247, 30, // Skip to: 19091 +/* 11164 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... +/* 11167 */ MCD_OPC_FilterValue, 0, 240, 30, // Skip to: 19091 +/* 11171 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 11174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11187 +/* 11178 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11242 +/* 11182 */ MCD_OPC_Decode, 186, 18, 130, 2, // Opcode: VFMSB +/* 11187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11200 +/* 11191 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11242 +/* 11195 */ MCD_OPC_Decode, 181, 18, 130, 2, // Opcode: VFMDB +/* 11200 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11214 +/* 11205 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11242 +/* 11209 */ MCD_OPC_Decode, 201, 21, 166, 2, // Opcode: WFMSB +/* 11214 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11228 +/* 11219 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11242 +/* 11223 */ MCD_OPC_Decode, 197, 21, 167, 2, // Opcode: WFMDB +/* 11228 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11242 +/* 11233 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11242 +/* 11237 */ MCD_OPC_Decode, 205, 21, 130, 2, // Opcode: WFMXB +/* 11242 */ MCD_OPC_CheckPredicate, 22, 165, 30, // Skip to: 19091 +/* 11246 */ MCD_OPC_Decode, 174, 18, 168, 2, // Opcode: VFM +/* 11251 */ MCD_OPC_FilterValue, 232, 1, 46, 1, // Skip to: 11558 +/* 11256 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11259 */ MCD_OPC_FilterValue, 0, 148, 30, // Skip to: 19091 +/* 11263 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11266 */ MCD_OPC_FilterValue, 0, 141, 30, // Skip to: 19091 +/* 11270 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 11273 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11286 +/* 11277 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11549 +/* 11281 */ MCD_OPC_Decode, 236, 17, 130, 2, // Opcode: VFCESB +/* 11286 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11299 +/* 11290 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11549 +/* 11294 */ MCD_OPC_Decode, 234, 17, 130, 2, // Opcode: VFCEDB +/* 11299 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11312 +/* 11303 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11549 +/* 11307 */ MCD_OPC_Decode, 154, 18, 130, 2, // Opcode: VFKESB +/* 11312 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11325 +/* 11316 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11549 +/* 11320 */ MCD_OPC_Decode, 152, 18, 130, 2, // Opcode: VFKEDB +/* 11325 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11339 +/* 11330 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11549 +/* 11334 */ MCD_OPC_Decode, 132, 21, 166, 2, // Opcode: WFCESB +/* 11339 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11353 +/* 11344 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11549 +/* 11348 */ MCD_OPC_Decode, 130, 21, 167, 2, // Opcode: WFCEDB +/* 11353 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11367 +/* 11358 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11549 +/* 11362 */ MCD_OPC_Decode, 134, 21, 130, 2, // Opcode: WFCEXB +/* 11367 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11381 +/* 11372 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11549 +/* 11376 */ MCD_OPC_Decode, 160, 21, 166, 2, // Opcode: WFKESB +/* 11381 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11395 +/* 11386 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11549 +/* 11390 */ MCD_OPC_Decode, 158, 21, 167, 2, // Opcode: WFKEDB +/* 11395 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11409 +/* 11400 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11549 +/* 11404 */ MCD_OPC_Decode, 162, 21, 130, 2, // Opcode: WFKEXB +/* 11409 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11423 +/* 11414 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11549 +/* 11418 */ MCD_OPC_Decode, 237, 17, 130, 2, // Opcode: VFCESBS +/* 11423 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11437 +/* 11428 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11549 +/* 11432 */ MCD_OPC_Decode, 235, 17, 130, 2, // Opcode: VFCEDBS +/* 11437 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11451 +/* 11442 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11549 +/* 11446 */ MCD_OPC_Decode, 155, 18, 130, 2, // Opcode: VFKESBS +/* 11451 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11465 +/* 11456 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11549 +/* 11460 */ MCD_OPC_Decode, 153, 18, 130, 2, // Opcode: VFKEDBS +/* 11465 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11479 +/* 11470 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11549 +/* 11474 */ MCD_OPC_Decode, 133, 21, 166, 2, // Opcode: WFCESBS +/* 11479 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11493 +/* 11484 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11549 +/* 11488 */ MCD_OPC_Decode, 131, 21, 167, 2, // Opcode: WFCEDBS +/* 11493 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11507 +/* 11498 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11549 +/* 11502 */ MCD_OPC_Decode, 135, 21, 130, 2, // Opcode: WFCEXBS +/* 11507 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11521 +/* 11512 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11549 +/* 11516 */ MCD_OPC_Decode, 161, 21, 166, 2, // Opcode: WFKESBS +/* 11521 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11535 +/* 11526 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11549 +/* 11530 */ MCD_OPC_Decode, 159, 21, 167, 2, // Opcode: WFKEDBS +/* 11535 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11549 +/* 11540 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11549 +/* 11544 */ MCD_OPC_Decode, 163, 21, 130, 2, // Opcode: WFKEXBS +/* 11549 */ MCD_OPC_CheckPredicate, 22, 114, 29, // Skip to: 19091 +/* 11553 */ MCD_OPC_Decode, 233, 17, 169, 2, // Opcode: VFCE +/* 11558 */ MCD_OPC_FilterValue, 234, 1, 46, 1, // Skip to: 11865 +/* 11563 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11566 */ MCD_OPC_FilterValue, 0, 97, 29, // Skip to: 19091 +/* 11570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11573 */ MCD_OPC_FilterValue, 0, 90, 29, // Skip to: 19091 +/* 11577 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 11580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11593 +/* 11584 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11856 +/* 11588 */ MCD_OPC_Decode, 244, 17, 130, 2, // Opcode: VFCHESB +/* 11593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11606 +/* 11597 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11856 +/* 11601 */ MCD_OPC_Decode, 242, 17, 130, 2, // Opcode: VFCHEDB +/* 11606 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11619 +/* 11610 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11856 +/* 11614 */ MCD_OPC_Decode, 160, 18, 130, 2, // Opcode: VFKHESB +/* 11619 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11632 +/* 11623 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11856 +/* 11627 */ MCD_OPC_Decode, 158, 18, 130, 2, // Opcode: VFKHEDB +/* 11632 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11646 +/* 11637 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11856 +/* 11641 */ MCD_OPC_Decode, 140, 21, 166, 2, // Opcode: WFCHESB +/* 11646 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11660 +/* 11651 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11856 +/* 11655 */ MCD_OPC_Decode, 138, 21, 167, 2, // Opcode: WFCHEDB +/* 11660 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11674 +/* 11665 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11856 +/* 11669 */ MCD_OPC_Decode, 142, 21, 130, 2, // Opcode: WFCHEXB +/* 11674 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11688 +/* 11679 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11856 +/* 11683 */ MCD_OPC_Decode, 168, 21, 166, 2, // Opcode: WFKHESB +/* 11688 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11702 +/* 11693 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11856 +/* 11697 */ MCD_OPC_Decode, 166, 21, 167, 2, // Opcode: WFKHEDB +/* 11702 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11716 +/* 11707 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11856 +/* 11711 */ MCD_OPC_Decode, 170, 21, 130, 2, // Opcode: WFKHEXB +/* 11716 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11730 +/* 11721 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11856 +/* 11725 */ MCD_OPC_Decode, 245, 17, 130, 2, // Opcode: VFCHESBS +/* 11730 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11744 +/* 11735 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11856 +/* 11739 */ MCD_OPC_Decode, 243, 17, 130, 2, // Opcode: VFCHEDBS +/* 11744 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11758 +/* 11749 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11856 +/* 11753 */ MCD_OPC_Decode, 161, 18, 130, 2, // Opcode: VFKHESBS +/* 11758 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11772 +/* 11763 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11856 +/* 11767 */ MCD_OPC_Decode, 159, 18, 130, 2, // Opcode: VFKHEDBS +/* 11772 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11786 +/* 11777 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11856 +/* 11781 */ MCD_OPC_Decode, 141, 21, 166, 2, // Opcode: WFCHESBS +/* 11786 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11800 +/* 11791 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11856 +/* 11795 */ MCD_OPC_Decode, 139, 21, 167, 2, // Opcode: WFCHEDBS +/* 11800 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11814 +/* 11805 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11856 +/* 11809 */ MCD_OPC_Decode, 143, 21, 130, 2, // Opcode: WFCHEXBS +/* 11814 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11828 +/* 11819 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11856 +/* 11823 */ MCD_OPC_Decode, 169, 21, 166, 2, // Opcode: WFKHESBS +/* 11828 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11842 +/* 11833 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11856 +/* 11837 */ MCD_OPC_Decode, 167, 21, 167, 2, // Opcode: WFKHEDBS +/* 11842 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11856 +/* 11847 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11856 +/* 11851 */ MCD_OPC_Decode, 171, 21, 130, 2, // Opcode: WFKHEXBS +/* 11856 */ MCD_OPC_CheckPredicate, 22, 63, 28, // Skip to: 19091 +/* 11860 */ MCD_OPC_Decode, 241, 17, 169, 2, // Opcode: VFCHE +/* 11865 */ MCD_OPC_FilterValue, 235, 1, 46, 1, // Skip to: 12172 +/* 11870 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 11873 */ MCD_OPC_FilterValue, 0, 46, 28, // Skip to: 19091 +/* 11877 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 11880 */ MCD_OPC_FilterValue, 0, 39, 28, // Skip to: 19091 +/* 11884 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 11887 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11900 +/* 11891 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 12163 +/* 11895 */ MCD_OPC_Decode, 246, 17, 130, 2, // Opcode: VFCHSB +/* 11900 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11913 +/* 11904 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 12163 +/* 11908 */ MCD_OPC_Decode, 239, 17, 130, 2, // Opcode: VFCHDB +/* 11913 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11926 +/* 11917 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 12163 +/* 11921 */ MCD_OPC_Decode, 162, 18, 130, 2, // Opcode: VFKHSB +/* 11926 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11939 +/* 11930 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 12163 +/* 11934 */ MCD_OPC_Decode, 156, 18, 130, 2, // Opcode: VFKHDB +/* 11939 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11953 +/* 11944 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 12163 +/* 11948 */ MCD_OPC_Decode, 144, 21, 166, 2, // Opcode: WFCHSB +/* 11953 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11967 +/* 11958 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 12163 +/* 11962 */ MCD_OPC_Decode, 136, 21, 167, 2, // Opcode: WFCHDB +/* 11967 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11981 +/* 11972 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 12163 +/* 11976 */ MCD_OPC_Decode, 146, 21, 130, 2, // Opcode: WFCHXB +/* 11981 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11995 +/* 11986 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 12163 +/* 11990 */ MCD_OPC_Decode, 172, 21, 166, 2, // Opcode: WFKHSB +/* 11995 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 12009 +/* 12000 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 12163 +/* 12004 */ MCD_OPC_Decode, 164, 21, 167, 2, // Opcode: WFKHDB +/* 12009 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 12023 +/* 12014 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 12163 +/* 12018 */ MCD_OPC_Decode, 174, 21, 130, 2, // Opcode: WFKHXB +/* 12023 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 12037 +/* 12028 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 12163 +/* 12032 */ MCD_OPC_Decode, 247, 17, 130, 2, // Opcode: VFCHSBS +/* 12037 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 12051 +/* 12042 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 12163 +/* 12046 */ MCD_OPC_Decode, 240, 17, 130, 2, // Opcode: VFCHDBS +/* 12051 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 12065 +/* 12056 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 12163 +/* 12060 */ MCD_OPC_Decode, 163, 18, 130, 2, // Opcode: VFKHSBS +/* 12065 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 12079 +/* 12070 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 12163 +/* 12074 */ MCD_OPC_Decode, 157, 18, 130, 2, // Opcode: VFKHDBS +/* 12079 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 12093 +/* 12084 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 12163 +/* 12088 */ MCD_OPC_Decode, 145, 21, 166, 2, // Opcode: WFCHSBS +/* 12093 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 12107 +/* 12098 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 12163 +/* 12102 */ MCD_OPC_Decode, 137, 21, 167, 2, // Opcode: WFCHDBS +/* 12107 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 12121 +/* 12112 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12163 +/* 12116 */ MCD_OPC_Decode, 147, 21, 130, 2, // Opcode: WFCHXBS +/* 12121 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 12135 +/* 12126 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12163 +/* 12130 */ MCD_OPC_Decode, 173, 21, 166, 2, // Opcode: WFKHSBS +/* 12135 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 12149 +/* 12140 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12163 +/* 12144 */ MCD_OPC_Decode, 165, 21, 167, 2, // Opcode: WFKHDBS +/* 12149 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 12163 +/* 12154 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12163 +/* 12158 */ MCD_OPC_Decode, 175, 21, 130, 2, // Opcode: WFKHXBS +/* 12163 */ MCD_OPC_CheckPredicate, 22, 12, 27, // Skip to: 19091 +/* 12167 */ MCD_OPC_Decode, 238, 17, 169, 2, // Opcode: VFCH +/* 12172 */ MCD_OPC_FilterValue, 238, 1, 94, 0, // Skip to: 12271 +/* 12177 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12180 */ MCD_OPC_FilterValue, 0, 251, 26, // Skip to: 19091 +/* 12184 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 12187 */ MCD_OPC_FilterValue, 0, 244, 26, // Skip to: 19091 +/* 12191 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12194 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12207 +/* 12198 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12262 +/* 12202 */ MCD_OPC_Decode, 184, 18, 136, 2, // Opcode: VFMINSB +/* 12207 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12220 +/* 12211 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12262 +/* 12215 */ MCD_OPC_Decode, 183, 18, 136, 2, // Opcode: VFMINDB +/* 12220 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12234 +/* 12225 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12262 +/* 12229 */ MCD_OPC_Decode, 199, 21, 170, 2, // Opcode: WFMINSB +/* 12234 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12248 +/* 12239 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12262 +/* 12243 */ MCD_OPC_Decode, 198, 21, 171, 2, // Opcode: WFMINDB +/* 12248 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12262 +/* 12253 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12262 +/* 12257 */ MCD_OPC_Decode, 200, 21, 136, 2, // Opcode: WFMINXB +/* 12262 */ MCD_OPC_CheckPredicate, 23, 169, 26, // Skip to: 19091 +/* 12266 */ MCD_OPC_Decode, 182, 18, 169, 2, // Opcode: VFMIN +/* 12271 */ MCD_OPC_FilterValue, 239, 1, 94, 0, // Skip to: 12370 +/* 12276 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12279 */ MCD_OPC_FilterValue, 0, 152, 26, // Skip to: 19091 +/* 12283 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 12286 */ MCD_OPC_FilterValue, 0, 145, 26, // Skip to: 19091 +/* 12290 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... +/* 12293 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12306 +/* 12297 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12361 +/* 12301 */ MCD_OPC_Decode, 180, 18, 136, 2, // Opcode: VFMAXSB +/* 12306 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12319 +/* 12310 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12361 +/* 12314 */ MCD_OPC_Decode, 179, 18, 136, 2, // Opcode: VFMAXDB +/* 12319 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12333 +/* 12324 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12361 +/* 12328 */ MCD_OPC_Decode, 195, 21, 170, 2, // Opcode: WFMAXSB +/* 12333 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12347 +/* 12338 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12361 +/* 12342 */ MCD_OPC_Decode, 194, 21, 171, 2, // Opcode: WFMAXDB +/* 12347 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12361 +/* 12352 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12361 +/* 12356 */ MCD_OPC_Decode, 196, 21, 136, 2, // Opcode: WFMAXXB +/* 12361 */ MCD_OPC_CheckPredicate, 23, 70, 26, // Skip to: 19091 +/* 12365 */ MCD_OPC_Decode, 178, 18, 169, 2, // Opcode: VFMAX +/* 12370 */ MCD_OPC_FilterValue, 240, 1, 78, 0, // Skip to: 12453 +/* 12375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12378 */ MCD_OPC_FilterValue, 0, 53, 26, // Skip to: 19091 +/* 12382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12385 */ MCD_OPC_FilterValue, 0, 46, 26, // Skip to: 19091 +/* 12389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12392 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12405 +/* 12396 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12444 +/* 12400 */ MCD_OPC_Decode, 233, 16, 130, 2, // Opcode: VAVGLB +/* 12405 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12418 +/* 12409 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12444 +/* 12413 */ MCD_OPC_Decode, 236, 16, 130, 2, // Opcode: VAVGLH +/* 12418 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12431 +/* 12422 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12444 +/* 12426 */ MCD_OPC_Decode, 234, 16, 130, 2, // Opcode: VAVGLF +/* 12431 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12444 +/* 12435 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12444 +/* 12439 */ MCD_OPC_Decode, 235, 16, 130, 2, // Opcode: VAVGLG +/* 12444 */ MCD_OPC_CheckPredicate, 22, 243, 25, // Skip to: 19091 +/* 12448 */ MCD_OPC_Decode, 232, 16, 131, 2, // Opcode: VAVGL +/* 12453 */ MCD_OPC_FilterValue, 241, 1, 91, 0, // Skip to: 12549 +/* 12458 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12461 */ MCD_OPC_FilterValue, 0, 226, 25, // Skip to: 19091 +/* 12465 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12468 */ MCD_OPC_FilterValue, 0, 219, 25, // Skip to: 19091 +/* 12472 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12475 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12488 +/* 12479 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12540 +/* 12483 */ MCD_OPC_Decode, 214, 16, 130, 2, // Opcode: VACCB +/* 12488 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12501 +/* 12492 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12540 +/* 12496 */ MCD_OPC_Decode, 219, 16, 130, 2, // Opcode: VACCH +/* 12501 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12514 +/* 12505 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12540 +/* 12509 */ MCD_OPC_Decode, 217, 16, 130, 2, // Opcode: VACCF +/* 12514 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12527 +/* 12518 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12540 +/* 12522 */ MCD_OPC_Decode, 218, 16, 130, 2, // Opcode: VACCG +/* 12527 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12540 +/* 12531 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12540 +/* 12535 */ MCD_OPC_Decode, 220, 16, 130, 2, // Opcode: VACCQ +/* 12540 */ MCD_OPC_CheckPredicate, 22, 147, 25, // Skip to: 19091 +/* 12544 */ MCD_OPC_Decode, 213, 16, 131, 2, // Opcode: VACC +/* 12549 */ MCD_OPC_FilterValue, 242, 1, 78, 0, // Skip to: 12632 +/* 12554 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12557 */ MCD_OPC_FilterValue, 0, 130, 25, // Skip to: 19091 +/* 12561 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12564 */ MCD_OPC_FilterValue, 0, 123, 25, // Skip to: 19091 +/* 12568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12571 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12584 +/* 12575 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12623 +/* 12579 */ MCD_OPC_Decode, 228, 16, 130, 2, // Opcode: VAVGB +/* 12584 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12597 +/* 12588 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12623 +/* 12592 */ MCD_OPC_Decode, 231, 16, 130, 2, // Opcode: VAVGH +/* 12597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12610 +/* 12601 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12623 +/* 12605 */ MCD_OPC_Decode, 229, 16, 130, 2, // Opcode: VAVGF +/* 12610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12623 +/* 12614 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12623 +/* 12618 */ MCD_OPC_Decode, 230, 16, 130, 2, // Opcode: VAVGG +/* 12623 */ MCD_OPC_CheckPredicate, 22, 64, 25, // Skip to: 19091 +/* 12627 */ MCD_OPC_Decode, 227, 16, 131, 2, // Opcode: VAVG +/* 12632 */ MCD_OPC_FilterValue, 243, 1, 91, 0, // Skip to: 12728 +/* 12637 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12640 */ MCD_OPC_FilterValue, 0, 47, 25, // Skip to: 19091 +/* 12644 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12647 */ MCD_OPC_FilterValue, 0, 40, 25, // Skip to: 19091 +/* 12651 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12667 +/* 12658 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12719 +/* 12662 */ MCD_OPC_Decode, 211, 16, 130, 2, // Opcode: VAB +/* 12667 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12680 +/* 12671 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12719 +/* 12675 */ MCD_OPC_Decode, 224, 16, 130, 2, // Opcode: VAH +/* 12680 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12693 +/* 12684 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12719 +/* 12688 */ MCD_OPC_Decode, 222, 16, 130, 2, // Opcode: VAF +/* 12693 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12706 +/* 12697 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12719 +/* 12701 */ MCD_OPC_Decode, 223, 16, 130, 2, // Opcode: VAG +/* 12706 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12719 +/* 12710 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12719 +/* 12714 */ MCD_OPC_Decode, 226, 16, 130, 2, // Opcode: VAQ +/* 12719 */ MCD_OPC_CheckPredicate, 22, 224, 24, // Skip to: 19091 +/* 12723 */ MCD_OPC_Decode, 210, 16, 131, 2, // Opcode: VA +/* 12728 */ MCD_OPC_FilterValue, 245, 1, 91, 0, // Skip to: 12824 +/* 12733 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12736 */ MCD_OPC_FilterValue, 0, 207, 24, // Skip to: 19091 +/* 12740 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12743 */ MCD_OPC_FilterValue, 0, 200, 24, // Skip to: 19091 +/* 12747 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12750 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12763 +/* 12754 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12815 +/* 12758 */ MCD_OPC_Decode, 171, 20, 130, 2, // Opcode: VSCBIB +/* 12763 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12776 +/* 12767 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12815 +/* 12771 */ MCD_OPC_Decode, 174, 20, 130, 2, // Opcode: VSCBIH +/* 12776 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12789 +/* 12780 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12815 +/* 12784 */ MCD_OPC_Decode, 172, 20, 130, 2, // Opcode: VSCBIF +/* 12789 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12802 +/* 12793 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12815 +/* 12797 */ MCD_OPC_Decode, 173, 20, 130, 2, // Opcode: VSCBIG +/* 12802 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12815 +/* 12806 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12815 +/* 12810 */ MCD_OPC_Decode, 175, 20, 130, 2, // Opcode: VSCBIQ +/* 12815 */ MCD_OPC_CheckPredicate, 22, 128, 24, // Skip to: 19091 +/* 12819 */ MCD_OPC_Decode, 170, 20, 131, 2, // Opcode: VSCBI +/* 12824 */ MCD_OPC_FilterValue, 247, 1, 91, 0, // Skip to: 12920 +/* 12829 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12832 */ MCD_OPC_FilterValue, 0, 111, 24, // Skip to: 19091 +/* 12836 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 12839 */ MCD_OPC_FilterValue, 0, 104, 24, // Skip to: 19091 +/* 12843 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12859 +/* 12850 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12911 +/* 12854 */ MCD_OPC_Decode, 165, 20, 130, 2, // Opcode: VSB +/* 12859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12872 +/* 12863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12911 +/* 12867 */ MCD_OPC_Decode, 186, 20, 130, 2, // Opcode: VSH +/* 12872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12885 +/* 12876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12911 +/* 12880 */ MCD_OPC_Decode, 184, 20, 130, 2, // Opcode: VSF +/* 12885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12898 +/* 12889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12911 +/* 12893 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: VSG +/* 12898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12911 +/* 12902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12911 +/* 12906 */ MCD_OPC_Decode, 191, 20, 130, 2, // Opcode: VSQ +/* 12911 */ MCD_OPC_CheckPredicate, 22, 32, 24, // Skip to: 19091 +/* 12915 */ MCD_OPC_Decode, 164, 20, 131, 2, // Opcode: VS +/* 12920 */ MCD_OPC_FilterValue, 248, 1, 165, 0, // Skip to: 13090 +/* 12925 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 12928 */ MCD_OPC_FilterValue, 0, 15, 24, // Skip to: 19091 +/* 12932 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 12935 */ MCD_OPC_FilterValue, 0, 8, 24, // Skip to: 19091 +/* 12939 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 12942 */ MCD_OPC_FilterValue, 0, 1, 24, // Skip to: 19091 +/* 12946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 12949 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12982 +/* 12953 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 12956 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12969 +/* 12960 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13081 +/* 12964 */ MCD_OPC_Decode, 243, 16, 130, 2, // Opcode: VCEQB +/* 12969 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13081 +/* 12973 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13081 +/* 12977 */ MCD_OPC_Decode, 244, 16, 130, 2, // Opcode: VCEQBS +/* 12982 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13015 +/* 12986 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 12989 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13002 +/* 12993 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13081 +/* 12997 */ MCD_OPC_Decode, 249, 16, 130, 2, // Opcode: VCEQH +/* 13002 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13081 +/* 13006 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13081 +/* 13010 */ MCD_OPC_Decode, 250, 16, 130, 2, // Opcode: VCEQHS +/* 13015 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13048 +/* 13019 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13022 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13035 +/* 13026 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13081 +/* 13030 */ MCD_OPC_Decode, 245, 16, 130, 2, // Opcode: VCEQF +/* 13035 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13081 +/* 13039 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13081 +/* 13043 */ MCD_OPC_Decode, 246, 16, 130, 2, // Opcode: VCEQFS +/* 13048 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13081 +/* 13052 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13055 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13068 +/* 13059 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13081 +/* 13063 */ MCD_OPC_Decode, 247, 16, 130, 2, // Opcode: VCEQG +/* 13068 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13081 +/* 13072 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13081 +/* 13076 */ MCD_OPC_Decode, 248, 16, 130, 2, // Opcode: VCEQGS +/* 13081 */ MCD_OPC_CheckPredicate, 22, 118, 23, // Skip to: 19091 +/* 13085 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: VCEQ +/* 13090 */ MCD_OPC_FilterValue, 249, 1, 165, 0, // Skip to: 13260 +/* 13095 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13098 */ MCD_OPC_FilterValue, 0, 101, 23, // Skip to: 19091 +/* 13102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 13105 */ MCD_OPC_FilterValue, 0, 94, 23, // Skip to: 19091 +/* 13109 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 13112 */ MCD_OPC_FilterValue, 0, 87, 23, // Skip to: 19091 +/* 13116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13119 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13152 +/* 13123 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13126 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13139 +/* 13130 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13251 +/* 13134 */ MCD_OPC_Decode, 135, 17, 130, 2, // Opcode: VCHLB +/* 13139 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13251 +/* 13143 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13251 +/* 13147 */ MCD_OPC_Decode, 136, 17, 130, 2, // Opcode: VCHLBS +/* 13152 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13185 +/* 13156 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13159 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13172 +/* 13163 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13251 +/* 13167 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: VCHLH +/* 13172 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13251 +/* 13176 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13251 +/* 13180 */ MCD_OPC_Decode, 142, 17, 130, 2, // Opcode: VCHLHS +/* 13185 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13218 +/* 13189 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13205 +/* 13196 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13251 +/* 13200 */ MCD_OPC_Decode, 137, 17, 130, 2, // Opcode: VCHLF +/* 13205 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13251 +/* 13209 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13251 +/* 13213 */ MCD_OPC_Decode, 138, 17, 130, 2, // Opcode: VCHLFS +/* 13218 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13251 +/* 13222 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13238 +/* 13229 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13251 +/* 13233 */ MCD_OPC_Decode, 139, 17, 130, 2, // Opcode: VCHLG +/* 13238 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13251 +/* 13242 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13251 +/* 13246 */ MCD_OPC_Decode, 140, 17, 130, 2, // Opcode: VCHLGS +/* 13251 */ MCD_OPC_CheckPredicate, 22, 204, 22, // Skip to: 19091 +/* 13255 */ MCD_OPC_Decode, 134, 17, 137, 2, // Opcode: VCHL +/* 13260 */ MCD_OPC_FilterValue, 251, 1, 165, 0, // Skip to: 13430 +/* 13265 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13268 */ MCD_OPC_FilterValue, 0, 187, 22, // Skip to: 19091 +/* 13272 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 13275 */ MCD_OPC_FilterValue, 0, 180, 22, // Skip to: 19091 +/* 13279 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 13282 */ MCD_OPC_FilterValue, 0, 173, 22, // Skip to: 19091 +/* 13286 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13289 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13322 +/* 13293 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13296 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13309 +/* 13300 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13421 +/* 13304 */ MCD_OPC_Decode, 254, 16, 130, 2, // Opcode: VCHB +/* 13309 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13421 +/* 13313 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13421 +/* 13317 */ MCD_OPC_Decode, 255, 16, 130, 2, // Opcode: VCHBS +/* 13322 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13355 +/* 13326 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13329 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13342 +/* 13333 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13421 +/* 13337 */ MCD_OPC_Decode, 132, 17, 130, 2, // Opcode: VCHH +/* 13342 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13421 +/* 13346 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13421 +/* 13350 */ MCD_OPC_Decode, 133, 17, 130, 2, // Opcode: VCHHS +/* 13355 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13388 +/* 13359 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13362 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13375 +/* 13366 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13421 +/* 13370 */ MCD_OPC_Decode, 128, 17, 130, 2, // Opcode: VCHF +/* 13375 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13421 +/* 13379 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13421 +/* 13383 */ MCD_OPC_Decode, 129, 17, 130, 2, // Opcode: VCHFS +/* 13388 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13421 +/* 13392 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... +/* 13395 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13408 +/* 13399 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13421 +/* 13403 */ MCD_OPC_Decode, 130, 17, 130, 2, // Opcode: VCHG +/* 13408 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13421 +/* 13412 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13421 +/* 13416 */ MCD_OPC_Decode, 131, 17, 130, 2, // Opcode: VCHGS +/* 13421 */ MCD_OPC_CheckPredicate, 22, 34, 22, // Skip to: 19091 +/* 13425 */ MCD_OPC_Decode, 253, 16, 137, 2, // Opcode: VCH +/* 13430 */ MCD_OPC_FilterValue, 252, 1, 78, 0, // Skip to: 13513 +/* 13435 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13438 */ MCD_OPC_FilterValue, 0, 17, 22, // Skip to: 19091 +/* 13442 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 13445 */ MCD_OPC_FilterValue, 0, 10, 22, // Skip to: 19091 +/* 13449 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13452 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13465 +/* 13456 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13504 +/* 13460 */ MCD_OPC_Decode, 214, 19, 130, 2, // Opcode: VMNLB +/* 13465 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13478 +/* 13469 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13504 +/* 13473 */ MCD_OPC_Decode, 217, 19, 130, 2, // Opcode: VMNLH +/* 13478 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13491 +/* 13482 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13504 +/* 13486 */ MCD_OPC_Decode, 215, 19, 130, 2, // Opcode: VMNLF +/* 13491 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13504 +/* 13495 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13504 +/* 13499 */ MCD_OPC_Decode, 216, 19, 130, 2, // Opcode: VMNLG +/* 13504 */ MCD_OPC_CheckPredicate, 22, 207, 21, // Skip to: 19091 +/* 13508 */ MCD_OPC_Decode, 213, 19, 131, 2, // Opcode: VMNL +/* 13513 */ MCD_OPC_FilterValue, 253, 1, 78, 0, // Skip to: 13596 +/* 13518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13521 */ MCD_OPC_FilterValue, 0, 190, 21, // Skip to: 19091 +/* 13525 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 13528 */ MCD_OPC_FilterValue, 0, 183, 21, // Skip to: 19091 +/* 13532 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13548 +/* 13539 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13587 +/* 13543 */ MCD_OPC_Decode, 242, 19, 130, 2, // Opcode: VMXLB +/* 13548 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13561 +/* 13552 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13587 +/* 13556 */ MCD_OPC_Decode, 245, 19, 130, 2, // Opcode: VMXLH +/* 13561 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13574 +/* 13565 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13587 +/* 13569 */ MCD_OPC_Decode, 243, 19, 130, 2, // Opcode: VMXLF +/* 13574 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13587 +/* 13578 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13587 +/* 13582 */ MCD_OPC_Decode, 244, 19, 130, 2, // Opcode: VMXLG +/* 13587 */ MCD_OPC_CheckPredicate, 22, 124, 21, // Skip to: 19091 +/* 13591 */ MCD_OPC_Decode, 241, 19, 131, 2, // Opcode: VMXL +/* 13596 */ MCD_OPC_FilterValue, 254, 1, 78, 0, // Skip to: 13679 +/* 13601 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13604 */ MCD_OPC_FilterValue, 0, 107, 21, // Skip to: 19091 +/* 13608 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 13611 */ MCD_OPC_FilterValue, 0, 100, 21, // Skip to: 19091 +/* 13615 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13618 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13631 +/* 13622 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13670 +/* 13626 */ MCD_OPC_Decode, 209, 19, 130, 2, // Opcode: VMNB +/* 13631 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13644 +/* 13635 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13670 +/* 13639 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: VMNH +/* 13644 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13657 +/* 13648 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13670 +/* 13652 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: VMNF +/* 13657 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13670 +/* 13661 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13670 +/* 13665 */ MCD_OPC_Decode, 211, 19, 130, 2, // Opcode: VMNG +/* 13670 */ MCD_OPC_CheckPredicate, 22, 41, 21, // Skip to: 19091 +/* 13674 */ MCD_OPC_Decode, 208, 19, 131, 2, // Opcode: VMN +/* 13679 */ MCD_OPC_FilterValue, 255, 1, 31, 21, // Skip to: 19091 +/* 13684 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 13687 */ MCD_OPC_FilterValue, 0, 24, 21, // Skip to: 19091 +/* 13691 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... +/* 13694 */ MCD_OPC_FilterValue, 0, 17, 21, // Skip to: 19091 +/* 13698 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 13701 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13714 +/* 13705 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13753 +/* 13709 */ MCD_OPC_Decode, 237, 19, 130, 2, // Opcode: VMXB +/* 13714 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13727 +/* 13718 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13753 +/* 13722 */ MCD_OPC_Decode, 240, 19, 130, 2, // Opcode: VMXH +/* 13727 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13740 +/* 13731 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13753 +/* 13735 */ MCD_OPC_Decode, 238, 19, 130, 2, // Opcode: VMXF +/* 13740 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13753 +/* 13744 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13753 +/* 13748 */ MCD_OPC_Decode, 239, 19, 130, 2, // Opcode: VMXG +/* 13753 */ MCD_OPC_CheckPredicate, 22, 214, 20, // Skip to: 19091 +/* 13757 */ MCD_OPC_Decode, 236, 19, 131, 2, // Opcode: VMX +/* 13762 */ MCD_OPC_FilterValue, 232, 1, 5, 0, // Skip to: 13772 +/* 13767 */ MCD_OPC_Decode, 193, 13, 189, 1, // Opcode: MVCIN +/* 13772 */ MCD_OPC_FilterValue, 233, 1, 5, 0, // Skip to: 13782 +/* 13777 */ MCD_OPC_Decode, 143, 14, 191, 1, // Opcode: PKA +/* 13782 */ MCD_OPC_FilterValue, 234, 1, 5, 0, // Skip to: 13792 +/* 13787 */ MCD_OPC_Decode, 207, 16, 189, 1, // Opcode: UNPKA +/* 13792 */ MCD_OPC_FilterValue, 235, 1, 198, 7, // Skip to: 15787 +/* 13797 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 13800 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 13809 +/* 13804 */ MCD_OPC_Decode, 227, 10, 172, 2, // Opcode: LMG +/* 13809 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 13818 +/* 13813 */ MCD_OPC_Decode, 132, 15, 173, 2, // Opcode: SRAG +/* 13818 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 13827 +/* 13822 */ MCD_OPC_Decode, 217, 14, 173, 2, // Opcode: SLAG +/* 13827 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 13836 +/* 13831 */ MCD_OPC_Decode, 139, 15, 173, 2, // Opcode: SRLG +/* 13836 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 13845 +/* 13840 */ MCD_OPC_Decode, 236, 14, 173, 2, // Opcode: SLLG +/* 13845 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 13854 +/* 13849 */ MCD_OPC_Decode, 186, 16, 172, 2, // Opcode: TRACG +/* 13854 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 13863 +/* 13858 */ MCD_OPC_Decode, 140, 8, 174, 2, // Opcode: CSY +/* 13863 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 13872 +/* 13867 */ MCD_OPC_Decode, 167, 14, 173, 2, // Opcode: RLLG +/* 13872 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 13881 +/* 13876 */ MCD_OPC_Decode, 166, 14, 175, 2, // Opcode: RLL +/* 13881 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 13890 +/* 13885 */ MCD_OPC_Decode, 143, 7, 176, 2, // Opcode: CLMH +/* 13890 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 13899 +/* 13894 */ MCD_OPC_Decode, 144, 7, 177, 2, // Opcode: CLMY +/* 13899 */ MCD_OPC_FilterValue, 35, 90, 0, // Skip to: 13993 +/* 13903 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 13906 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13919 +/* 13910 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 13984 +/* 13914 */ MCD_OPC_Decode, 193, 7, 178, 2, // Opcode: CLTAsmH +/* 13919 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 13932 +/* 13923 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 13984 +/* 13927 */ MCD_OPC_Decode, 195, 7, 178, 2, // Opcode: CLTAsmL +/* 13932 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 13945 +/* 13936 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 13984 +/* 13940 */ MCD_OPC_Decode, 197, 7, 178, 2, // Opcode: CLTAsmLH +/* 13945 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 13958 +/* 13949 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 13984 +/* 13953 */ MCD_OPC_Decode, 192, 7, 178, 2, // Opcode: CLTAsmE +/* 13958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 13971 +/* 13962 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 13984 +/* 13966 */ MCD_OPC_Decode, 194, 7, 178, 2, // Opcode: CLTAsmHE +/* 13971 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 13984 +/* 13975 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 13984 +/* 13979 */ MCD_OPC_Decode, 196, 7, 178, 2, // Opcode: CLTAsmLE +/* 13984 */ MCD_OPC_CheckPredicate, 24, 239, 19, // Skip to: 19091 +/* 13988 */ MCD_OPC_Decode, 191, 7, 179, 2, // Opcode: CLTAsm +/* 13993 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 14002 +/* 13997 */ MCD_OPC_Decode, 189, 15, 172, 2, // Opcode: STMG +/* 14002 */ MCD_OPC_FilterValue, 37, 5, 0, // Skip to: 14011 +/* 14006 */ MCD_OPC_Decode, 169, 15, 180, 2, // Opcode: STCTG +/* 14011 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 14020 +/* 14015 */ MCD_OPC_Decode, 190, 15, 181, 2, // Opcode: STMH +/* 14020 */ MCD_OPC_FilterValue, 43, 90, 0, // Skip to: 14114 +/* 14024 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 14027 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14040 +/* 14031 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 14105 +/* 14035 */ MCD_OPC_Decode, 221, 6, 182, 2, // Opcode: CLGTAsmH +/* 14040 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14053 +/* 14044 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 14105 +/* 14048 */ MCD_OPC_Decode, 223, 6, 182, 2, // Opcode: CLGTAsmL +/* 14053 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14066 +/* 14057 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 14105 +/* 14061 */ MCD_OPC_Decode, 225, 6, 182, 2, // Opcode: CLGTAsmLH +/* 14066 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14079 +/* 14070 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 14105 +/* 14074 */ MCD_OPC_Decode, 220, 6, 182, 2, // Opcode: CLGTAsmE +/* 14079 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14092 +/* 14083 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 14105 +/* 14087 */ MCD_OPC_Decode, 222, 6, 182, 2, // Opcode: CLGTAsmHE +/* 14092 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14105 +/* 14096 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 14105 +/* 14100 */ MCD_OPC_Decode, 224, 6, 182, 2, // Opcode: CLGTAsmLE +/* 14105 */ MCD_OPC_CheckPredicate, 24, 118, 19, // Skip to: 19091 +/* 14109 */ MCD_OPC_Decode, 219, 6, 183, 2, // Opcode: CLGTAsm +/* 14114 */ MCD_OPC_FilterValue, 44, 5, 0, // Skip to: 14123 +/* 14118 */ MCD_OPC_Decode, 165, 15, 176, 2, // Opcode: STCMH +/* 14123 */ MCD_OPC_FilterValue, 45, 5, 0, // Skip to: 14132 +/* 14127 */ MCD_OPC_Decode, 166, 15, 177, 2, // Opcode: STCMY +/* 14132 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 14141 +/* 14136 */ MCD_OPC_Decode, 143, 10, 180, 2, // Opcode: LCTLG +/* 14141 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 14150 +/* 14145 */ MCD_OPC_Decode, 135, 8, 184, 2, // Opcode: CSG +/* 14150 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 14159 +/* 14154 */ MCD_OPC_Decode, 160, 4, 185, 2, // Opcode: CDSY +/* 14159 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 14168 +/* 14163 */ MCD_OPC_Decode, 158, 4, 185, 2, // Opcode: CDSG +/* 14168 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 14177 +/* 14172 */ MCD_OPC_Decode, 135, 4, 184, 2, // Opcode: BXHG +/* 14177 */ MCD_OPC_FilterValue, 69, 5, 0, // Skip to: 14186 +/* 14181 */ MCD_OPC_Decode, 137, 4, 184, 2, // Opcode: BXLEG +/* 14186 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 14195 +/* 14190 */ MCD_OPC_Decode, 216, 8, 173, 2, // Opcode: ECAG +/* 14195 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 14204 +/* 14199 */ MCD_OPC_Decode, 180, 16, 186, 2, // Opcode: TMY +/* 14204 */ MCD_OPC_FilterValue, 82, 5, 0, // Skip to: 14213 +/* 14208 */ MCD_OPC_Decode, 206, 13, 186, 2, // Opcode: MVIY +/* 14213 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 14222 +/* 14217 */ MCD_OPC_Decode, 239, 13, 186, 2, // Opcode: NIY +/* 14222 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 14231 +/* 14226 */ MCD_OPC_Decode, 141, 7, 186, 2, // Opcode: CLIY +/* 14231 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 14240 +/* 14235 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: OIY +/* 14240 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 14249 +/* 14244 */ MCD_OPC_Decode, 234, 21, 186, 2, // Opcode: XIY +/* 14249 */ MCD_OPC_FilterValue, 106, 5, 0, // Skip to: 14258 +/* 14253 */ MCD_OPC_Decode, 155, 3, 187, 2, // Opcode: ASI +/* 14258 */ MCD_OPC_FilterValue, 110, 5, 0, // Skip to: 14267 +/* 14262 */ MCD_OPC_Decode, 148, 3, 187, 2, // Opcode: ALSI +/* 14267 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 14276 +/* 14271 */ MCD_OPC_Decode, 249, 2, 187, 2, // Opcode: AGSI +/* 14276 */ MCD_OPC_FilterValue, 126, 5, 0, // Skip to: 14285 +/* 14280 */ MCD_OPC_Decode, 142, 3, 187, 2, // Opcode: ALGSI +/* 14285 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 14295 +/* 14290 */ MCD_OPC_Decode, 132, 9, 188, 2, // Opcode: ICMH +/* 14295 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 14305 +/* 14300 */ MCD_OPC_Decode, 133, 9, 189, 2, // Opcode: ICMY +/* 14305 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 14315 +/* 14310 */ MCD_OPC_Decode, 197, 13, 190, 2, // Opcode: MVCLU +/* 14315 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 14325 +/* 14320 */ MCD_OPC_Decode, 228, 5, 190, 2, // Opcode: CLCLU +/* 14325 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 14335 +/* 14330 */ MCD_OPC_Decode, 191, 15, 191, 2, // Opcode: STMY +/* 14335 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 14345 +/* 14340 */ MCD_OPC_Decode, 228, 10, 181, 2, // Opcode: LMH +/* 14345 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 14355 +/* 14350 */ MCD_OPC_Decode, 229, 10, 191, 2, // Opcode: LMY +/* 14355 */ MCD_OPC_FilterValue, 154, 1, 5, 0, // Skip to: 14365 +/* 14360 */ MCD_OPC_Decode, 245, 9, 192, 2, // Opcode: LAMY +/* 14365 */ MCD_OPC_FilterValue, 155, 1, 5, 0, // Skip to: 14375 +/* 14370 */ MCD_OPC_Decode, 156, 15, 192, 2, // Opcode: STAMY +/* 14375 */ MCD_OPC_FilterValue, 192, 1, 17, 0, // Skip to: 14397 +/* 14380 */ MCD_OPC_CheckField, 32, 4, 0, 97, 18, // Skip to: 19091 +/* 14386 */ MCD_OPC_CheckField, 8, 8, 0, 91, 18, // Skip to: 19091 +/* 14392 */ MCD_OPC_Decode, 181, 16, 193, 2, // Opcode: TP +/* 14397 */ MCD_OPC_FilterValue, 220, 1, 9, 0, // Skip to: 14411 +/* 14402 */ MCD_OPC_CheckPredicate, 15, 77, 18, // Skip to: 19091 +/* 14406 */ MCD_OPC_Decode, 133, 15, 175, 2, // Opcode: SRAK +/* 14411 */ MCD_OPC_FilterValue, 221, 1, 9, 0, // Skip to: 14425 +/* 14416 */ MCD_OPC_CheckPredicate, 15, 63, 18, // Skip to: 19091 +/* 14420 */ MCD_OPC_Decode, 218, 14, 175, 2, // Opcode: SLAK +/* 14425 */ MCD_OPC_FilterValue, 222, 1, 9, 0, // Skip to: 14439 +/* 14430 */ MCD_OPC_CheckPredicate, 15, 49, 18, // Skip to: 19091 +/* 14434 */ MCD_OPC_Decode, 140, 15, 175, 2, // Opcode: SRLK +/* 14439 */ MCD_OPC_FilterValue, 223, 1, 9, 0, // Skip to: 14453 +/* 14444 */ MCD_OPC_CheckPredicate, 15, 35, 18, // Skip to: 19091 +/* 14448 */ MCD_OPC_Decode, 237, 14, 175, 2, // Opcode: SLLK +/* 14453 */ MCD_OPC_FilterValue, 224, 1, 194, 0, // Skip to: 14652 +/* 14458 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 14461 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14474 +/* 14465 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14643 +/* 14469 */ MCD_OPC_Decode, 154, 11, 194, 2, // Opcode: LOCFHAsmO +/* 14474 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14487 +/* 14478 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14643 +/* 14482 */ MCD_OPC_Decode, 138, 11, 194, 2, // Opcode: LOCFHAsmH +/* 14487 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14500 +/* 14491 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14643 +/* 14495 */ MCD_OPC_Decode, 148, 11, 194, 2, // Opcode: LOCFHAsmNLE +/* 14500 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14513 +/* 14504 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14643 +/* 14508 */ MCD_OPC_Decode, 140, 11, 194, 2, // Opcode: LOCFHAsmL +/* 14513 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14526 +/* 14517 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14643 +/* 14521 */ MCD_OPC_Decode, 146, 11, 194, 2, // Opcode: LOCFHAsmNHE +/* 14526 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14539 +/* 14530 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14643 +/* 14534 */ MCD_OPC_Decode, 142, 11, 194, 2, // Opcode: LOCFHAsmLH +/* 14539 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14552 +/* 14543 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14643 +/* 14547 */ MCD_OPC_Decode, 144, 11, 194, 2, // Opcode: LOCFHAsmNE +/* 14552 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14565 +/* 14556 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14643 +/* 14560 */ MCD_OPC_Decode, 137, 11, 194, 2, // Opcode: LOCFHAsmE +/* 14565 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14578 +/* 14569 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14643 +/* 14573 */ MCD_OPC_Decode, 149, 11, 194, 2, // Opcode: LOCFHAsmNLH +/* 14578 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14591 +/* 14582 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14643 +/* 14586 */ MCD_OPC_Decode, 139, 11, 194, 2, // Opcode: LOCFHAsmHE +/* 14591 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14604 +/* 14595 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14643 +/* 14599 */ MCD_OPC_Decode, 147, 11, 194, 2, // Opcode: LOCFHAsmNL +/* 14604 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14617 +/* 14608 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14643 +/* 14612 */ MCD_OPC_Decode, 141, 11, 194, 2, // Opcode: LOCFHAsmLE +/* 14617 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14630 +/* 14621 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14643 +/* 14625 */ MCD_OPC_Decode, 145, 11, 194, 2, // Opcode: LOCFHAsmNH +/* 14630 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14643 +/* 14634 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14643 +/* 14638 */ MCD_OPC_Decode, 151, 11, 194, 2, // Opcode: LOCFHAsmNO +/* 14643 */ MCD_OPC_CheckPredicate, 12, 92, 17, // Skip to: 19091 +/* 14647 */ MCD_OPC_Decode, 136, 11, 195, 2, // Opcode: LOCFHAsm +/* 14652 */ MCD_OPC_FilterValue, 225, 1, 194, 0, // Skip to: 14851 +/* 14657 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 14660 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14673 +/* 14664 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14842 +/* 14668 */ MCD_OPC_Decode, 234, 15, 196, 2, // Opcode: STOCFHAsmO +/* 14673 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14686 +/* 14677 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14842 +/* 14681 */ MCD_OPC_Decode, 218, 15, 196, 2, // Opcode: STOCFHAsmH +/* 14686 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14699 +/* 14690 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14842 +/* 14694 */ MCD_OPC_Decode, 228, 15, 196, 2, // Opcode: STOCFHAsmNLE +/* 14699 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14712 +/* 14703 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14842 +/* 14707 */ MCD_OPC_Decode, 220, 15, 196, 2, // Opcode: STOCFHAsmL +/* 14712 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14725 +/* 14716 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14842 +/* 14720 */ MCD_OPC_Decode, 226, 15, 196, 2, // Opcode: STOCFHAsmNHE +/* 14725 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14738 +/* 14729 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14842 +/* 14733 */ MCD_OPC_Decode, 222, 15, 196, 2, // Opcode: STOCFHAsmLH +/* 14738 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14751 +/* 14742 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14842 +/* 14746 */ MCD_OPC_Decode, 224, 15, 196, 2, // Opcode: STOCFHAsmNE +/* 14751 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14764 +/* 14755 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14842 +/* 14759 */ MCD_OPC_Decode, 217, 15, 196, 2, // Opcode: STOCFHAsmE +/* 14764 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14777 +/* 14768 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14842 +/* 14772 */ MCD_OPC_Decode, 229, 15, 196, 2, // Opcode: STOCFHAsmNLH +/* 14777 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14790 +/* 14781 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14842 +/* 14785 */ MCD_OPC_Decode, 219, 15, 196, 2, // Opcode: STOCFHAsmHE +/* 14790 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14803 +/* 14794 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14842 +/* 14798 */ MCD_OPC_Decode, 227, 15, 196, 2, // Opcode: STOCFHAsmNL +/* 14803 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14816 +/* 14807 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14842 +/* 14811 */ MCD_OPC_Decode, 221, 15, 196, 2, // Opcode: STOCFHAsmLE +/* 14816 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14829 +/* 14820 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14842 +/* 14824 */ MCD_OPC_Decode, 225, 15, 196, 2, // Opcode: STOCFHAsmNH +/* 14829 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14842 +/* 14833 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14842 +/* 14837 */ MCD_OPC_Decode, 231, 15, 196, 2, // Opcode: STOCFHAsmNO +/* 14842 */ MCD_OPC_CheckPredicate, 12, 149, 16, // Skip to: 19091 +/* 14846 */ MCD_OPC_Decode, 216, 15, 197, 2, // Opcode: STOCFHAsm +/* 14851 */ MCD_OPC_FilterValue, 226, 1, 194, 0, // Skip to: 15050 +/* 14856 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 14859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14872 +/* 14863 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15041 +/* 14867 */ MCD_OPC_Decode, 198, 11, 198, 2, // Opcode: LOCGAsmO +/* 14872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14885 +/* 14876 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15041 +/* 14880 */ MCD_OPC_Decode, 182, 11, 198, 2, // Opcode: LOCGAsmH +/* 14885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14898 +/* 14889 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15041 +/* 14893 */ MCD_OPC_Decode, 192, 11, 198, 2, // Opcode: LOCGAsmNLE +/* 14898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14911 +/* 14902 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15041 +/* 14906 */ MCD_OPC_Decode, 184, 11, 198, 2, // Opcode: LOCGAsmL +/* 14911 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14924 +/* 14915 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15041 +/* 14919 */ MCD_OPC_Decode, 190, 11, 198, 2, // Opcode: LOCGAsmNHE +/* 14924 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14937 +/* 14928 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15041 +/* 14932 */ MCD_OPC_Decode, 186, 11, 198, 2, // Opcode: LOCGAsmLH +/* 14937 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14950 +/* 14941 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15041 +/* 14945 */ MCD_OPC_Decode, 188, 11, 198, 2, // Opcode: LOCGAsmNE +/* 14950 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14963 +/* 14954 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15041 +/* 14958 */ MCD_OPC_Decode, 181, 11, 198, 2, // Opcode: LOCGAsmE +/* 14963 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14976 +/* 14967 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15041 +/* 14971 */ MCD_OPC_Decode, 193, 11, 198, 2, // Opcode: LOCGAsmNLH +/* 14976 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14989 +/* 14980 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15041 +/* 14984 */ MCD_OPC_Decode, 183, 11, 198, 2, // Opcode: LOCGAsmHE +/* 14989 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15002 +/* 14993 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15041 +/* 14997 */ MCD_OPC_Decode, 191, 11, 198, 2, // Opcode: LOCGAsmNL +/* 15002 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15015 +/* 15006 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15041 +/* 15010 */ MCD_OPC_Decode, 185, 11, 198, 2, // Opcode: LOCGAsmLE +/* 15015 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15028 +/* 15019 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15041 +/* 15023 */ MCD_OPC_Decode, 189, 11, 198, 2, // Opcode: LOCGAsmNH +/* 15028 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15041 +/* 15032 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15041 +/* 15036 */ MCD_OPC_Decode, 195, 11, 198, 2, // Opcode: LOCGAsmNO +/* 15041 */ MCD_OPC_CheckPredicate, 14, 206, 15, // Skip to: 19091 +/* 15045 */ MCD_OPC_Decode, 180, 11, 199, 2, // Opcode: LOCGAsm +/* 15050 */ MCD_OPC_FilterValue, 227, 1, 194, 0, // Skip to: 15249 +/* 15055 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 15058 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15071 +/* 15062 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15240 +/* 15066 */ MCD_OPC_Decode, 128, 16, 182, 2, // Opcode: STOCGAsmO +/* 15071 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15084 +/* 15075 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15240 +/* 15079 */ MCD_OPC_Decode, 240, 15, 182, 2, // Opcode: STOCGAsmH +/* 15084 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15097 +/* 15088 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15240 +/* 15092 */ MCD_OPC_Decode, 250, 15, 182, 2, // Opcode: STOCGAsmNLE +/* 15097 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15110 +/* 15101 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15240 +/* 15105 */ MCD_OPC_Decode, 242, 15, 182, 2, // Opcode: STOCGAsmL +/* 15110 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15123 +/* 15114 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15240 +/* 15118 */ MCD_OPC_Decode, 248, 15, 182, 2, // Opcode: STOCGAsmNHE +/* 15123 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15136 +/* 15127 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15240 +/* 15131 */ MCD_OPC_Decode, 244, 15, 182, 2, // Opcode: STOCGAsmLH +/* 15136 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15149 +/* 15140 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15240 +/* 15144 */ MCD_OPC_Decode, 246, 15, 182, 2, // Opcode: STOCGAsmNE +/* 15149 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15162 +/* 15153 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15240 +/* 15157 */ MCD_OPC_Decode, 239, 15, 182, 2, // Opcode: STOCGAsmE +/* 15162 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15175 +/* 15166 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15240 +/* 15170 */ MCD_OPC_Decode, 251, 15, 182, 2, // Opcode: STOCGAsmNLH +/* 15175 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15188 +/* 15179 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15240 +/* 15183 */ MCD_OPC_Decode, 241, 15, 182, 2, // Opcode: STOCGAsmHE +/* 15188 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15201 +/* 15192 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15240 +/* 15196 */ MCD_OPC_Decode, 249, 15, 182, 2, // Opcode: STOCGAsmNL +/* 15201 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15214 +/* 15205 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15240 +/* 15209 */ MCD_OPC_Decode, 243, 15, 182, 2, // Opcode: STOCGAsmLE +/* 15214 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15227 +/* 15218 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15240 +/* 15222 */ MCD_OPC_Decode, 247, 15, 182, 2, // Opcode: STOCGAsmNH +/* 15227 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15240 +/* 15231 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15240 +/* 15235 */ MCD_OPC_Decode, 253, 15, 182, 2, // Opcode: STOCGAsmNO +/* 15240 */ MCD_OPC_CheckPredicate, 14, 7, 15, // Skip to: 19091 +/* 15244 */ MCD_OPC_Decode, 238, 15, 183, 2, // Opcode: STOCGAsm +/* 15249 */ MCD_OPC_FilterValue, 228, 1, 9, 0, // Skip to: 15263 +/* 15254 */ MCD_OPC_CheckPredicate, 17, 249, 14, // Skip to: 19091 +/* 15258 */ MCD_OPC_Decode, 247, 9, 172, 2, // Opcode: LANG +/* 15263 */ MCD_OPC_FilterValue, 230, 1, 9, 0, // Skip to: 15277 +/* 15268 */ MCD_OPC_CheckPredicate, 17, 235, 14, // Skip to: 19091 +/* 15272 */ MCD_OPC_Decode, 249, 9, 172, 2, // Opcode: LAOG +/* 15277 */ MCD_OPC_FilterValue, 231, 1, 9, 0, // Skip to: 15291 +/* 15282 */ MCD_OPC_CheckPredicate, 17, 221, 14, // Skip to: 19091 +/* 15286 */ MCD_OPC_Decode, 254, 9, 172, 2, // Opcode: LAXG +/* 15291 */ MCD_OPC_FilterValue, 232, 1, 9, 0, // Skip to: 15305 +/* 15296 */ MCD_OPC_CheckPredicate, 17, 207, 14, // Skip to: 19091 +/* 15300 */ MCD_OPC_Decode, 239, 9, 172, 2, // Opcode: LAAG +/* 15305 */ MCD_OPC_FilterValue, 234, 1, 9, 0, // Skip to: 15319 +/* 15310 */ MCD_OPC_CheckPredicate, 17, 193, 14, // Skip to: 19091 +/* 15314 */ MCD_OPC_Decode, 241, 9, 172, 2, // Opcode: LAALG +/* 15319 */ MCD_OPC_FilterValue, 242, 1, 194, 0, // Skip to: 15518 +/* 15324 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 15327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15340 +/* 15331 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15509 +/* 15335 */ MCD_OPC_Decode, 132, 11, 200, 2, // Opcode: LOCAsmO +/* 15340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15353 +/* 15344 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15509 +/* 15348 */ MCD_OPC_Decode, 244, 10, 200, 2, // Opcode: LOCAsmH +/* 15353 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15366 +/* 15357 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15509 +/* 15361 */ MCD_OPC_Decode, 254, 10, 200, 2, // Opcode: LOCAsmNLE +/* 15366 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15379 +/* 15370 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15509 +/* 15374 */ MCD_OPC_Decode, 246, 10, 200, 2, // Opcode: LOCAsmL +/* 15379 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15392 +/* 15383 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15509 +/* 15387 */ MCD_OPC_Decode, 252, 10, 200, 2, // Opcode: LOCAsmNHE +/* 15392 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15405 +/* 15396 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15509 +/* 15400 */ MCD_OPC_Decode, 248, 10, 200, 2, // Opcode: LOCAsmLH +/* 15405 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15418 +/* 15409 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15509 +/* 15413 */ MCD_OPC_Decode, 250, 10, 200, 2, // Opcode: LOCAsmNE +/* 15418 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15431 +/* 15422 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15509 +/* 15426 */ MCD_OPC_Decode, 243, 10, 200, 2, // Opcode: LOCAsmE +/* 15431 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15444 +/* 15435 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15509 +/* 15439 */ MCD_OPC_Decode, 255, 10, 200, 2, // Opcode: LOCAsmNLH +/* 15444 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15457 +/* 15448 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15509 +/* 15452 */ MCD_OPC_Decode, 245, 10, 200, 2, // Opcode: LOCAsmHE +/* 15457 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15470 +/* 15461 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15509 +/* 15465 */ MCD_OPC_Decode, 253, 10, 200, 2, // Opcode: LOCAsmNL +/* 15470 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15483 +/* 15474 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15509 +/* 15478 */ MCD_OPC_Decode, 247, 10, 200, 2, // Opcode: LOCAsmLE +/* 15483 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15496 +/* 15487 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15509 +/* 15491 */ MCD_OPC_Decode, 251, 10, 200, 2, // Opcode: LOCAsmNH +/* 15496 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15509 +/* 15500 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15509 +/* 15504 */ MCD_OPC_Decode, 129, 11, 200, 2, // Opcode: LOCAsmNO +/* 15509 */ MCD_OPC_CheckPredicate, 14, 250, 13, // Skip to: 19091 +/* 15513 */ MCD_OPC_Decode, 242, 10, 201, 2, // Opcode: LOCAsm +/* 15518 */ MCD_OPC_FilterValue, 243, 1, 194, 0, // Skip to: 15717 +/* 15523 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 15526 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15539 +/* 15530 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15708 +/* 15534 */ MCD_OPC_Decode, 212, 15, 178, 2, // Opcode: STOCAsmO +/* 15539 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15552 +/* 15543 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15708 +/* 15547 */ MCD_OPC_Decode, 196, 15, 178, 2, // Opcode: STOCAsmH +/* 15552 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15565 +/* 15556 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15708 +/* 15560 */ MCD_OPC_Decode, 206, 15, 178, 2, // Opcode: STOCAsmNLE +/* 15565 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15578 +/* 15569 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15708 +/* 15573 */ MCD_OPC_Decode, 198, 15, 178, 2, // Opcode: STOCAsmL +/* 15578 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15591 +/* 15582 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15708 +/* 15586 */ MCD_OPC_Decode, 204, 15, 178, 2, // Opcode: STOCAsmNHE +/* 15591 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15604 +/* 15595 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15708 +/* 15599 */ MCD_OPC_Decode, 200, 15, 178, 2, // Opcode: STOCAsmLH +/* 15604 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15617 +/* 15608 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15708 +/* 15612 */ MCD_OPC_Decode, 202, 15, 178, 2, // Opcode: STOCAsmNE +/* 15617 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15630 +/* 15621 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15708 +/* 15625 */ MCD_OPC_Decode, 195, 15, 178, 2, // Opcode: STOCAsmE +/* 15630 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15643 +/* 15634 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15708 +/* 15638 */ MCD_OPC_Decode, 207, 15, 178, 2, // Opcode: STOCAsmNLH +/* 15643 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15656 +/* 15647 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15708 +/* 15651 */ MCD_OPC_Decode, 197, 15, 178, 2, // Opcode: STOCAsmHE +/* 15656 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15669 +/* 15660 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15708 +/* 15664 */ MCD_OPC_Decode, 205, 15, 178, 2, // Opcode: STOCAsmNL +/* 15669 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15682 +/* 15673 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15708 +/* 15677 */ MCD_OPC_Decode, 199, 15, 178, 2, // Opcode: STOCAsmLE +/* 15682 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15695 +/* 15686 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15708 +/* 15690 */ MCD_OPC_Decode, 203, 15, 178, 2, // Opcode: STOCAsmNH +/* 15695 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15708 +/* 15699 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15708 +/* 15703 */ MCD_OPC_Decode, 209, 15, 178, 2, // Opcode: STOCAsmNO +/* 15708 */ MCD_OPC_CheckPredicate, 14, 51, 13, // Skip to: 19091 +/* 15712 */ MCD_OPC_Decode, 194, 15, 179, 2, // Opcode: STOCAsm +/* 15717 */ MCD_OPC_FilterValue, 244, 1, 9, 0, // Skip to: 15731 +/* 15722 */ MCD_OPC_CheckPredicate, 17, 37, 13, // Skip to: 19091 +/* 15726 */ MCD_OPC_Decode, 246, 9, 191, 2, // Opcode: LAN +/* 15731 */ MCD_OPC_FilterValue, 246, 1, 9, 0, // Skip to: 15745 +/* 15736 */ MCD_OPC_CheckPredicate, 17, 23, 13, // Skip to: 19091 +/* 15740 */ MCD_OPC_Decode, 248, 9, 191, 2, // Opcode: LAO +/* 15745 */ MCD_OPC_FilterValue, 247, 1, 9, 0, // Skip to: 15759 +/* 15750 */ MCD_OPC_CheckPredicate, 17, 9, 13, // Skip to: 19091 +/* 15754 */ MCD_OPC_Decode, 253, 9, 191, 2, // Opcode: LAX +/* 15759 */ MCD_OPC_FilterValue, 248, 1, 9, 0, // Skip to: 15773 +/* 15764 */ MCD_OPC_CheckPredicate, 17, 251, 12, // Skip to: 19091 +/* 15768 */ MCD_OPC_Decode, 238, 9, 191, 2, // Opcode: LAA +/* 15773 */ MCD_OPC_FilterValue, 250, 1, 241, 12, // Skip to: 19091 +/* 15778 */ MCD_OPC_CheckPredicate, 17, 237, 12, // Skip to: 19091 +/* 15782 */ MCD_OPC_Decode, 240, 9, 191, 2, // Opcode: LAAL +/* 15787 */ MCD_OPC_FilterValue, 236, 1, 195, 8, // Skip to: 18035 +/* 15792 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 15795 */ MCD_OPC_FilterValue, 66, 201, 0, // Skip to: 16000 +/* 15799 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 15802 */ MCD_OPC_FilterValue, 0, 213, 12, // Skip to: 19091 +/* 15806 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 15809 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15822 +/* 15813 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 15991 +/* 15817 */ MCD_OPC_Decode, 158, 12, 202, 2, // Opcode: LOCHIAsmO +/* 15822 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15835 +/* 15826 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 15991 +/* 15830 */ MCD_OPC_Decode, 142, 12, 202, 2, // Opcode: LOCHIAsmH +/* 15835 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15848 +/* 15839 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 15991 +/* 15843 */ MCD_OPC_Decode, 152, 12, 202, 2, // Opcode: LOCHIAsmNLE +/* 15848 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15861 +/* 15852 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 15991 +/* 15856 */ MCD_OPC_Decode, 144, 12, 202, 2, // Opcode: LOCHIAsmL +/* 15861 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15874 +/* 15865 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 15991 +/* 15869 */ MCD_OPC_Decode, 150, 12, 202, 2, // Opcode: LOCHIAsmNHE +/* 15874 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15887 +/* 15878 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 15991 +/* 15882 */ MCD_OPC_Decode, 146, 12, 202, 2, // Opcode: LOCHIAsmLH +/* 15887 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15900 +/* 15891 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 15991 +/* 15895 */ MCD_OPC_Decode, 148, 12, 202, 2, // Opcode: LOCHIAsmNE +/* 15900 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15913 +/* 15904 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 15991 +/* 15908 */ MCD_OPC_Decode, 141, 12, 202, 2, // Opcode: LOCHIAsmE +/* 15913 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15926 +/* 15917 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 15991 +/* 15921 */ MCD_OPC_Decode, 153, 12, 202, 2, // Opcode: LOCHIAsmNLH +/* 15926 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15939 +/* 15930 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 15991 +/* 15934 */ MCD_OPC_Decode, 143, 12, 202, 2, // Opcode: LOCHIAsmHE +/* 15939 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15952 +/* 15943 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 15991 +/* 15947 */ MCD_OPC_Decode, 151, 12, 202, 2, // Opcode: LOCHIAsmNL +/* 15952 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15965 +/* 15956 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 15991 +/* 15960 */ MCD_OPC_Decode, 145, 12, 202, 2, // Opcode: LOCHIAsmLE +/* 15965 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15978 +/* 15969 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 15991 +/* 15973 */ MCD_OPC_Decode, 149, 12, 202, 2, // Opcode: LOCHIAsmNH +/* 15978 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15991 +/* 15982 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 15991 +/* 15986 */ MCD_OPC_Decode, 155, 12, 202, 2, // Opcode: LOCHIAsmNO +/* 15991 */ MCD_OPC_CheckPredicate, 12, 24, 12, // Skip to: 19091 +/* 15995 */ MCD_OPC_Decode, 140, 12, 203, 2, // Opcode: LOCHIAsm +/* 16000 */ MCD_OPC_FilterValue, 68, 11, 0, // Skip to: 16015 +/* 16004 */ MCD_OPC_CheckField, 8, 8, 0, 9, 12, // Skip to: 19091 +/* 16010 */ MCD_OPC_Decode, 128, 4, 204, 2, // Opcode: BRXHG +/* 16015 */ MCD_OPC_FilterValue, 69, 11, 0, // Skip to: 16030 +/* 16019 */ MCD_OPC_CheckField, 8, 8, 0, 250, 11, // Skip to: 19091 +/* 16025 */ MCD_OPC_Decode, 130, 4, 204, 2, // Opcode: BRXLG +/* 16030 */ MCD_OPC_FilterValue, 70, 201, 0, // Skip to: 16235 +/* 16034 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 16037 */ MCD_OPC_FilterValue, 0, 234, 11, // Skip to: 19091 +/* 16041 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16044 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16057 +/* 16048 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16226 +/* 16052 */ MCD_OPC_Decode, 220, 11, 205, 2, // Opcode: LOCGHIAsmO +/* 16057 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16070 +/* 16061 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16226 +/* 16065 */ MCD_OPC_Decode, 204, 11, 205, 2, // Opcode: LOCGHIAsmH +/* 16070 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16083 +/* 16074 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16226 +/* 16078 */ MCD_OPC_Decode, 214, 11, 205, 2, // Opcode: LOCGHIAsmNLE +/* 16083 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16096 +/* 16087 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16226 +/* 16091 */ MCD_OPC_Decode, 206, 11, 205, 2, // Opcode: LOCGHIAsmL +/* 16096 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16109 +/* 16100 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16226 +/* 16104 */ MCD_OPC_Decode, 212, 11, 205, 2, // Opcode: LOCGHIAsmNHE +/* 16109 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16122 +/* 16113 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16226 +/* 16117 */ MCD_OPC_Decode, 208, 11, 205, 2, // Opcode: LOCGHIAsmLH +/* 16122 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16135 +/* 16126 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16226 +/* 16130 */ MCD_OPC_Decode, 210, 11, 205, 2, // Opcode: LOCGHIAsmNE +/* 16135 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16148 +/* 16139 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16226 +/* 16143 */ MCD_OPC_Decode, 203, 11, 205, 2, // Opcode: LOCGHIAsmE +/* 16148 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16161 +/* 16152 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16226 +/* 16156 */ MCD_OPC_Decode, 215, 11, 205, 2, // Opcode: LOCGHIAsmNLH +/* 16161 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16174 +/* 16165 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16226 +/* 16169 */ MCD_OPC_Decode, 205, 11, 205, 2, // Opcode: LOCGHIAsmHE +/* 16174 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16187 +/* 16178 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16226 +/* 16182 */ MCD_OPC_Decode, 213, 11, 205, 2, // Opcode: LOCGHIAsmNL +/* 16187 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16200 +/* 16191 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16226 +/* 16195 */ MCD_OPC_Decode, 207, 11, 205, 2, // Opcode: LOCGHIAsmLE +/* 16200 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16213 +/* 16204 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16226 +/* 16208 */ MCD_OPC_Decode, 211, 11, 205, 2, // Opcode: LOCGHIAsmNH +/* 16213 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16226 +/* 16217 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16226 +/* 16221 */ MCD_OPC_Decode, 217, 11, 205, 2, // Opcode: LOCGHIAsmNO +/* 16226 */ MCD_OPC_CheckPredicate, 12, 45, 11, // Skip to: 19091 +/* 16230 */ MCD_OPC_Decode, 202, 11, 206, 2, // Opcode: LOCGHIAsm +/* 16235 */ MCD_OPC_FilterValue, 78, 201, 0, // Skip to: 16440 +/* 16239 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... +/* 16242 */ MCD_OPC_FilterValue, 0, 29, 11, // Skip to: 19091 +/* 16246 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16249 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16262 +/* 16253 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16431 +/* 16257 */ MCD_OPC_Decode, 136, 12, 207, 2, // Opcode: LOCHHIAsmO +/* 16262 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16275 +/* 16266 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16431 +/* 16270 */ MCD_OPC_Decode, 248, 11, 207, 2, // Opcode: LOCHHIAsmH +/* 16275 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16288 +/* 16279 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16431 +/* 16283 */ MCD_OPC_Decode, 130, 12, 207, 2, // Opcode: LOCHHIAsmNLE +/* 16288 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16301 +/* 16292 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16431 +/* 16296 */ MCD_OPC_Decode, 250, 11, 207, 2, // Opcode: LOCHHIAsmL +/* 16301 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16314 +/* 16305 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16431 +/* 16309 */ MCD_OPC_Decode, 128, 12, 207, 2, // Opcode: LOCHHIAsmNHE +/* 16314 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16327 +/* 16318 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16431 +/* 16322 */ MCD_OPC_Decode, 252, 11, 207, 2, // Opcode: LOCHHIAsmLH +/* 16327 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16340 +/* 16331 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16431 +/* 16335 */ MCD_OPC_Decode, 254, 11, 207, 2, // Opcode: LOCHHIAsmNE +/* 16340 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16353 +/* 16344 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16431 +/* 16348 */ MCD_OPC_Decode, 247, 11, 207, 2, // Opcode: LOCHHIAsmE +/* 16353 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16366 +/* 16357 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16431 +/* 16361 */ MCD_OPC_Decode, 131, 12, 207, 2, // Opcode: LOCHHIAsmNLH +/* 16366 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16379 +/* 16370 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16431 +/* 16374 */ MCD_OPC_Decode, 249, 11, 207, 2, // Opcode: LOCHHIAsmHE +/* 16379 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16392 +/* 16383 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16431 +/* 16387 */ MCD_OPC_Decode, 129, 12, 207, 2, // Opcode: LOCHHIAsmNL +/* 16392 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16405 +/* 16396 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16431 +/* 16400 */ MCD_OPC_Decode, 251, 11, 207, 2, // Opcode: LOCHHIAsmLE +/* 16405 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16418 +/* 16409 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16431 +/* 16413 */ MCD_OPC_Decode, 255, 11, 207, 2, // Opcode: LOCHHIAsmNH +/* 16418 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16431 +/* 16422 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16431 +/* 16426 */ MCD_OPC_Decode, 133, 12, 207, 2, // Opcode: LOCHHIAsmNO +/* 16431 */ MCD_OPC_CheckPredicate, 12, 96, 10, // Skip to: 19091 +/* 16435 */ MCD_OPC_Decode, 246, 11, 208, 2, // Opcode: LOCHHIAsm +/* 16440 */ MCD_OPC_FilterValue, 81, 9, 0, // Skip to: 16453 +/* 16444 */ MCD_OPC_CheckPredicate, 11, 83, 10, // Skip to: 19091 +/* 16448 */ MCD_OPC_Decode, 165, 14, 209, 2, // Opcode: RISBLG +/* 16453 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 16462 +/* 16457 */ MCD_OPC_Decode, 168, 14, 210, 2, // Opcode: RNSBG +/* 16462 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 16471 +/* 16466 */ MCD_OPC_Decode, 161, 14, 210, 2, // Opcode: RISBG +/* 16471 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 16480 +/* 16475 */ MCD_OPC_Decode, 169, 14, 210, 2, // Opcode: ROSBG +/* 16480 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 16489 +/* 16484 */ MCD_OPC_Decode, 176, 14, 210, 2, // Opcode: RXSBG +/* 16489 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 16502 +/* 16493 */ MCD_OPC_CheckPredicate, 24, 34, 10, // Skip to: 19091 +/* 16497 */ MCD_OPC_Decode, 163, 14, 210, 2, // Opcode: RISBGN +/* 16502 */ MCD_OPC_FilterValue, 93, 9, 0, // Skip to: 16515 +/* 16506 */ MCD_OPC_CheckPredicate, 11, 21, 10, // Skip to: 19091 +/* 16510 */ MCD_OPC_Decode, 164, 14, 211, 2, // Opcode: RISBHG +/* 16515 */ MCD_OPC_FilterValue, 100, 69, 0, // Skip to: 16588 +/* 16519 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16522 */ MCD_OPC_FilterValue, 0, 5, 10, // Skip to: 19091 +/* 16526 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16538 +/* 16533 */ MCD_OPC_Decode, 140, 5, 212, 2, // Opcode: CGRJAsmH +/* 16538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16547 +/* 16542 */ MCD_OPC_Decode, 142, 5, 212, 2, // Opcode: CGRJAsmL +/* 16547 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16556 +/* 16551 */ MCD_OPC_Decode, 144, 5, 212, 2, // Opcode: CGRJAsmLH +/* 16556 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16565 +/* 16560 */ MCD_OPC_Decode, 139, 5, 212, 2, // Opcode: CGRJAsmE +/* 16565 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16574 +/* 16569 */ MCD_OPC_Decode, 141, 5, 212, 2, // Opcode: CGRJAsmHE +/* 16574 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16583 +/* 16578 */ MCD_OPC_Decode, 143, 5, 212, 2, // Opcode: CGRJAsmLE +/* 16583 */ MCD_OPC_Decode, 138, 5, 213, 2, // Opcode: CGRJAsm +/* 16588 */ MCD_OPC_FilterValue, 101, 69, 0, // Skip to: 16661 +/* 16592 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16595 */ MCD_OPC_FilterValue, 0, 188, 9, // Skip to: 19091 +/* 16599 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16602 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16611 +/* 16606 */ MCD_OPC_Decode, 192, 6, 212, 2, // Opcode: CLGRJAsmH +/* 16611 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16620 +/* 16615 */ MCD_OPC_Decode, 194, 6, 212, 2, // Opcode: CLGRJAsmL +/* 16620 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16629 +/* 16624 */ MCD_OPC_Decode, 196, 6, 212, 2, // Opcode: CLGRJAsmLH +/* 16629 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16638 +/* 16633 */ MCD_OPC_Decode, 191, 6, 212, 2, // Opcode: CLGRJAsmE +/* 16638 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16647 +/* 16642 */ MCD_OPC_Decode, 193, 6, 212, 2, // Opcode: CLGRJAsmHE +/* 16647 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16656 +/* 16651 */ MCD_OPC_Decode, 195, 6, 212, 2, // Opcode: CLGRJAsmLE +/* 16656 */ MCD_OPC_Decode, 190, 6, 213, 2, // Opcode: CLGRJAsm +/* 16661 */ MCD_OPC_FilterValue, 112, 76, 0, // Skip to: 16741 +/* 16665 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16668 */ MCD_OPC_FilterValue, 0, 115, 9, // Skip to: 19091 +/* 16672 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16675 */ MCD_OPC_FilterValue, 0, 108, 9, // Skip to: 19091 +/* 16679 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16682 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16691 +/* 16686 */ MCD_OPC_Decode, 239, 4, 214, 2, // Opcode: CGITAsmH +/* 16691 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16700 +/* 16695 */ MCD_OPC_Decode, 241, 4, 214, 2, // Opcode: CGITAsmL +/* 16700 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16709 +/* 16704 */ MCD_OPC_Decode, 243, 4, 214, 2, // Opcode: CGITAsmLH +/* 16709 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16718 +/* 16713 */ MCD_OPC_Decode, 238, 4, 214, 2, // Opcode: CGITAsmE +/* 16718 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16727 +/* 16722 */ MCD_OPC_Decode, 240, 4, 214, 2, // Opcode: CGITAsmHE +/* 16727 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16736 +/* 16731 */ MCD_OPC_Decode, 242, 4, 214, 2, // Opcode: CGITAsmLE +/* 16736 */ MCD_OPC_Decode, 237, 4, 215, 2, // Opcode: CGITAsm +/* 16741 */ MCD_OPC_FilterValue, 113, 76, 0, // Skip to: 16821 +/* 16745 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16748 */ MCD_OPC_FilterValue, 0, 35, 9, // Skip to: 19091 +/* 16752 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16755 */ MCD_OPC_FilterValue, 0, 28, 9, // Skip to: 19091 +/* 16759 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16762 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16771 +/* 16766 */ MCD_OPC_Decode, 163, 6, 216, 2, // Opcode: CLGITAsmH +/* 16771 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16780 +/* 16775 */ MCD_OPC_Decode, 165, 6, 216, 2, // Opcode: CLGITAsmL +/* 16780 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16789 +/* 16784 */ MCD_OPC_Decode, 167, 6, 216, 2, // Opcode: CLGITAsmLH +/* 16789 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16798 +/* 16793 */ MCD_OPC_Decode, 162, 6, 216, 2, // Opcode: CLGITAsmE +/* 16798 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16807 +/* 16802 */ MCD_OPC_Decode, 164, 6, 216, 2, // Opcode: CLGITAsmHE +/* 16807 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16816 +/* 16811 */ MCD_OPC_Decode, 166, 6, 216, 2, // Opcode: CLGITAsmLE +/* 16816 */ MCD_OPC_Decode, 161, 6, 217, 2, // Opcode: CLGITAsm +/* 16821 */ MCD_OPC_FilterValue, 114, 76, 0, // Skip to: 16901 +/* 16825 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16828 */ MCD_OPC_FilterValue, 0, 211, 8, // Skip to: 19091 +/* 16832 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16835 */ MCD_OPC_FilterValue, 0, 204, 8, // Skip to: 19091 +/* 16839 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16851 +/* 16846 */ MCD_OPC_Decode, 212, 5, 218, 2, // Opcode: CITAsmH +/* 16851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16860 +/* 16855 */ MCD_OPC_Decode, 214, 5, 218, 2, // Opcode: CITAsmL +/* 16860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16869 +/* 16864 */ MCD_OPC_Decode, 216, 5, 218, 2, // Opcode: CITAsmLH +/* 16869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16878 +/* 16873 */ MCD_OPC_Decode, 211, 5, 218, 2, // Opcode: CITAsmE +/* 16878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16887 +/* 16882 */ MCD_OPC_Decode, 213, 5, 218, 2, // Opcode: CITAsmHE +/* 16887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16896 +/* 16891 */ MCD_OPC_Decode, 215, 5, 218, 2, // Opcode: CITAsmLE +/* 16896 */ MCD_OPC_Decode, 210, 5, 219, 2, // Opcode: CITAsm +/* 16901 */ MCD_OPC_FilterValue, 115, 76, 0, // Skip to: 16981 +/* 16905 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16908 */ MCD_OPC_FilterValue, 0, 131, 8, // Skip to: 19091 +/* 16912 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 16915 */ MCD_OPC_FilterValue, 0, 124, 8, // Skip to: 19091 +/* 16919 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16922 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16931 +/* 16926 */ MCD_OPC_Decode, 237, 5, 220, 2, // Opcode: CLFITAsmH +/* 16931 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16940 +/* 16935 */ MCD_OPC_Decode, 239, 5, 220, 2, // Opcode: CLFITAsmL +/* 16940 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16949 +/* 16944 */ MCD_OPC_Decode, 241, 5, 220, 2, // Opcode: CLFITAsmLH +/* 16949 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16958 +/* 16953 */ MCD_OPC_Decode, 236, 5, 220, 2, // Opcode: CLFITAsmE +/* 16958 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16967 +/* 16962 */ MCD_OPC_Decode, 238, 5, 220, 2, // Opcode: CLFITAsmHE +/* 16967 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16976 +/* 16971 */ MCD_OPC_Decode, 240, 5, 220, 2, // Opcode: CLFITAsmLE +/* 16976 */ MCD_OPC_Decode, 235, 5, 221, 2, // Opcode: CLFITAsm +/* 16981 */ MCD_OPC_FilterValue, 118, 69, 0, // Skip to: 17054 +/* 16985 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16988 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 19091 +/* 16992 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 16995 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17004 +/* 16999 */ MCD_OPC_Decode, 234, 7, 222, 2, // Opcode: CRJAsmH +/* 17004 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17013 +/* 17008 */ MCD_OPC_Decode, 236, 7, 222, 2, // Opcode: CRJAsmL +/* 17013 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17022 +/* 17017 */ MCD_OPC_Decode, 238, 7, 222, 2, // Opcode: CRJAsmLH +/* 17022 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17031 +/* 17026 */ MCD_OPC_Decode, 233, 7, 222, 2, // Opcode: CRJAsmE +/* 17031 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17040 +/* 17035 */ MCD_OPC_Decode, 235, 7, 222, 2, // Opcode: CRJAsmHE +/* 17040 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17049 +/* 17044 */ MCD_OPC_Decode, 237, 7, 222, 2, // Opcode: CRJAsmLE +/* 17049 */ MCD_OPC_Decode, 232, 7, 223, 2, // Opcode: CRJAsm +/* 17054 */ MCD_OPC_FilterValue, 119, 69, 0, // Skip to: 17127 +/* 17058 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 17061 */ MCD_OPC_FilterValue, 0, 234, 7, // Skip to: 19091 +/* 17065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17068 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17077 +/* 17072 */ MCD_OPC_Decode, 163, 7, 222, 2, // Opcode: CLRJAsmH +/* 17077 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17086 +/* 17081 */ MCD_OPC_Decode, 165, 7, 222, 2, // Opcode: CLRJAsmL +/* 17086 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17095 +/* 17090 */ MCD_OPC_Decode, 167, 7, 222, 2, // Opcode: CLRJAsmLH +/* 17095 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17104 +/* 17099 */ MCD_OPC_Decode, 162, 7, 222, 2, // Opcode: CLRJAsmE +/* 17104 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17113 +/* 17108 */ MCD_OPC_Decode, 164, 7, 222, 2, // Opcode: CLRJAsmHE +/* 17113 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17122 +/* 17117 */ MCD_OPC_Decode, 166, 7, 222, 2, // Opcode: CLRJAsmLE +/* 17122 */ MCD_OPC_Decode, 161, 7, 223, 2, // Opcode: CLRJAsm +/* 17127 */ MCD_OPC_FilterValue, 124, 62, 0, // Skip to: 17193 +/* 17131 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17134 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17143 +/* 17138 */ MCD_OPC_Decode, 225, 4, 224, 2, // Opcode: CGIJAsmH +/* 17143 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17152 +/* 17147 */ MCD_OPC_Decode, 227, 4, 224, 2, // Opcode: CGIJAsmL +/* 17152 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17161 +/* 17156 */ MCD_OPC_Decode, 229, 4, 224, 2, // Opcode: CGIJAsmLH +/* 17161 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17170 +/* 17165 */ MCD_OPC_Decode, 224, 4, 224, 2, // Opcode: CGIJAsmE +/* 17170 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17179 +/* 17174 */ MCD_OPC_Decode, 226, 4, 224, 2, // Opcode: CGIJAsmHE +/* 17179 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17188 +/* 17183 */ MCD_OPC_Decode, 228, 4, 224, 2, // Opcode: CGIJAsmLE +/* 17188 */ MCD_OPC_Decode, 223, 4, 225, 2, // Opcode: CGIJAsm +/* 17193 */ MCD_OPC_FilterValue, 125, 62, 0, // Skip to: 17259 +/* 17197 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17200 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17209 +/* 17204 */ MCD_OPC_Decode, 149, 6, 226, 2, // Opcode: CLGIJAsmH +/* 17209 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17218 +/* 17213 */ MCD_OPC_Decode, 151, 6, 226, 2, // Opcode: CLGIJAsmL +/* 17218 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17227 +/* 17222 */ MCD_OPC_Decode, 153, 6, 226, 2, // Opcode: CLGIJAsmLH +/* 17227 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17236 +/* 17231 */ MCD_OPC_Decode, 148, 6, 226, 2, // Opcode: CLGIJAsmE +/* 17236 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17245 +/* 17240 */ MCD_OPC_Decode, 150, 6, 226, 2, // Opcode: CLGIJAsmHE +/* 17245 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17254 +/* 17249 */ MCD_OPC_Decode, 152, 6, 226, 2, // Opcode: CLGIJAsmLE +/* 17254 */ MCD_OPC_Decode, 147, 6, 227, 2, // Opcode: CLGIJAsm +/* 17259 */ MCD_OPC_FilterValue, 126, 62, 0, // Skip to: 17325 +/* 17263 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17266 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17275 +/* 17270 */ MCD_OPC_Decode, 198, 5, 228, 2, // Opcode: CIJAsmH +/* 17275 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17284 +/* 17279 */ MCD_OPC_Decode, 200, 5, 228, 2, // Opcode: CIJAsmL +/* 17284 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17293 +/* 17288 */ MCD_OPC_Decode, 202, 5, 228, 2, // Opcode: CIJAsmLH +/* 17293 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17302 +/* 17297 */ MCD_OPC_Decode, 197, 5, 228, 2, // Opcode: CIJAsmE +/* 17302 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17311 +/* 17306 */ MCD_OPC_Decode, 199, 5, 228, 2, // Opcode: CIJAsmHE +/* 17311 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17320 +/* 17315 */ MCD_OPC_Decode, 201, 5, 228, 2, // Opcode: CIJAsmLE +/* 17320 */ MCD_OPC_Decode, 196, 5, 229, 2, // Opcode: CIJAsm +/* 17325 */ MCD_OPC_FilterValue, 127, 62, 0, // Skip to: 17391 +/* 17329 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17332 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17341 +/* 17336 */ MCD_OPC_Decode, 130, 7, 230, 2, // Opcode: CLIJAsmH +/* 17341 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17350 +/* 17345 */ MCD_OPC_Decode, 132, 7, 230, 2, // Opcode: CLIJAsmL +/* 17350 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17359 +/* 17354 */ MCD_OPC_Decode, 134, 7, 230, 2, // Opcode: CLIJAsmLH +/* 17359 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17368 +/* 17363 */ MCD_OPC_Decode, 129, 7, 230, 2, // Opcode: CLIJAsmE +/* 17368 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17377 +/* 17372 */ MCD_OPC_Decode, 131, 7, 230, 2, // Opcode: CLIJAsmHE +/* 17377 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17386 +/* 17381 */ MCD_OPC_Decode, 133, 7, 230, 2, // Opcode: CLIJAsmLE +/* 17386 */ MCD_OPC_Decode, 128, 7, 231, 2, // Opcode: CLIJAsm +/* 17391 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 17411 +/* 17396 */ MCD_OPC_CheckPredicate, 15, 155, 6, // Skip to: 19091 +/* 17400 */ MCD_OPC_CheckField, 8, 8, 0, 149, 6, // Skip to: 19091 +/* 17406 */ MCD_OPC_Decode, 254, 2, 232, 2, // Opcode: AHIK +/* 17411 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 17431 +/* 17416 */ MCD_OPC_CheckPredicate, 15, 135, 6, // Skip to: 19091 +/* 17420 */ MCD_OPC_CheckField, 8, 8, 0, 129, 6, // Skip to: 19091 +/* 17426 */ MCD_OPC_Decode, 246, 2, 233, 2, // Opcode: AGHIK +/* 17431 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 17451 +/* 17436 */ MCD_OPC_CheckPredicate, 15, 115, 6, // Skip to: 19091 +/* 17440 */ MCD_OPC_CheckField, 8, 8, 0, 109, 6, // Skip to: 19091 +/* 17446 */ MCD_OPC_Decode, 145, 3, 232, 2, // Opcode: ALHSIK +/* 17451 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 17471 +/* 17456 */ MCD_OPC_CheckPredicate, 15, 95, 6, // Skip to: 19091 +/* 17460 */ MCD_OPC_CheckField, 8, 8, 0, 89, 6, // Skip to: 19091 +/* 17466 */ MCD_OPC_Decode, 139, 3, 233, 2, // Opcode: ALGHSIK +/* 17471 */ MCD_OPC_FilterValue, 228, 1, 69, 0, // Skip to: 17545 +/* 17476 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 17479 */ MCD_OPC_FilterValue, 0, 72, 6, // Skip to: 19091 +/* 17483 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17486 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17495 +/* 17490 */ MCD_OPC_Decode, 254, 4, 234, 2, // Opcode: CGRBAsmH +/* 17495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17504 +/* 17499 */ MCD_OPC_Decode, 128, 5, 234, 2, // Opcode: CGRBAsmL +/* 17504 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17513 +/* 17508 */ MCD_OPC_Decode, 130, 5, 234, 2, // Opcode: CGRBAsmLH +/* 17513 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17522 +/* 17517 */ MCD_OPC_Decode, 253, 4, 234, 2, // Opcode: CGRBAsmE +/* 17522 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17531 +/* 17526 */ MCD_OPC_Decode, 255, 4, 234, 2, // Opcode: CGRBAsmHE +/* 17531 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17540 +/* 17535 */ MCD_OPC_Decode, 129, 5, 234, 2, // Opcode: CGRBAsmLE +/* 17540 */ MCD_OPC_Decode, 252, 4, 235, 2, // Opcode: CGRBAsm +/* 17545 */ MCD_OPC_FilterValue, 229, 1, 69, 0, // Skip to: 17619 +/* 17550 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 17553 */ MCD_OPC_FilterValue, 0, 254, 5, // Skip to: 19091 +/* 17557 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17560 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17569 +/* 17564 */ MCD_OPC_Decode, 178, 6, 234, 2, // Opcode: CLGRBAsmH +/* 17569 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17578 +/* 17573 */ MCD_OPC_Decode, 180, 6, 234, 2, // Opcode: CLGRBAsmL +/* 17578 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17587 +/* 17582 */ MCD_OPC_Decode, 182, 6, 234, 2, // Opcode: CLGRBAsmLH +/* 17587 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17596 +/* 17591 */ MCD_OPC_Decode, 177, 6, 234, 2, // Opcode: CLGRBAsmE +/* 17596 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17605 +/* 17600 */ MCD_OPC_Decode, 179, 6, 234, 2, // Opcode: CLGRBAsmHE +/* 17605 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17614 +/* 17609 */ MCD_OPC_Decode, 181, 6, 234, 2, // Opcode: CLGRBAsmLE +/* 17614 */ MCD_OPC_Decode, 176, 6, 235, 2, // Opcode: CLGRBAsm +/* 17619 */ MCD_OPC_FilterValue, 246, 1, 69, 0, // Skip to: 17693 +/* 17624 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 17627 */ MCD_OPC_FilterValue, 0, 180, 5, // Skip to: 19091 +/* 17631 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17634 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17643 +/* 17638 */ MCD_OPC_Decode, 218, 7, 236, 2, // Opcode: CRBAsmH +/* 17643 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17652 +/* 17647 */ MCD_OPC_Decode, 220, 7, 236, 2, // Opcode: CRBAsmL +/* 17652 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17661 +/* 17656 */ MCD_OPC_Decode, 222, 7, 236, 2, // Opcode: CRBAsmLH +/* 17661 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17670 +/* 17665 */ MCD_OPC_Decode, 217, 7, 236, 2, // Opcode: CRBAsmE +/* 17670 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17679 +/* 17674 */ MCD_OPC_Decode, 219, 7, 236, 2, // Opcode: CRBAsmHE +/* 17679 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17688 +/* 17683 */ MCD_OPC_Decode, 221, 7, 236, 2, // Opcode: CRBAsmLE +/* 17688 */ MCD_OPC_Decode, 216, 7, 237, 2, // Opcode: CRBAsm +/* 17693 */ MCD_OPC_FilterValue, 247, 1, 69, 0, // Skip to: 17767 +/* 17698 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 17701 */ MCD_OPC_FilterValue, 0, 106, 5, // Skip to: 19091 +/* 17705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17708 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17717 +/* 17712 */ MCD_OPC_Decode, 149, 7, 236, 2, // Opcode: CLRBAsmH +/* 17717 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17726 +/* 17721 */ MCD_OPC_Decode, 151, 7, 236, 2, // Opcode: CLRBAsmL +/* 17726 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17735 +/* 17730 */ MCD_OPC_Decode, 153, 7, 236, 2, // Opcode: CLRBAsmLH +/* 17735 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17744 +/* 17739 */ MCD_OPC_Decode, 148, 7, 236, 2, // Opcode: CLRBAsmE +/* 17744 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17753 +/* 17748 */ MCD_OPC_Decode, 150, 7, 236, 2, // Opcode: CLRBAsmHE +/* 17753 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17762 +/* 17757 */ MCD_OPC_Decode, 152, 7, 236, 2, // Opcode: CLRBAsmLE +/* 17762 */ MCD_OPC_Decode, 147, 7, 237, 2, // Opcode: CLRBAsm +/* 17767 */ MCD_OPC_FilterValue, 252, 1, 62, 0, // Skip to: 17834 +/* 17772 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17775 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17784 +/* 17779 */ MCD_OPC_Decode, 211, 4, 238, 2, // Opcode: CGIBAsmH +/* 17784 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17793 +/* 17788 */ MCD_OPC_Decode, 213, 4, 238, 2, // Opcode: CGIBAsmL +/* 17793 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17802 +/* 17797 */ MCD_OPC_Decode, 215, 4, 238, 2, // Opcode: CGIBAsmLH +/* 17802 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17811 +/* 17806 */ MCD_OPC_Decode, 210, 4, 238, 2, // Opcode: CGIBAsmE +/* 17811 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17820 +/* 17815 */ MCD_OPC_Decode, 212, 4, 238, 2, // Opcode: CGIBAsmHE +/* 17820 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17829 +/* 17824 */ MCD_OPC_Decode, 214, 4, 238, 2, // Opcode: CGIBAsmLE +/* 17829 */ MCD_OPC_Decode, 209, 4, 239, 2, // Opcode: CGIBAsm +/* 17834 */ MCD_OPC_FilterValue, 253, 1, 62, 0, // Skip to: 17901 +/* 17839 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17851 +/* 17846 */ MCD_OPC_Decode, 135, 6, 240, 2, // Opcode: CLGIBAsmH +/* 17851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17860 +/* 17855 */ MCD_OPC_Decode, 137, 6, 240, 2, // Opcode: CLGIBAsmL +/* 17860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17869 +/* 17864 */ MCD_OPC_Decode, 139, 6, 240, 2, // Opcode: CLGIBAsmLH +/* 17869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17878 +/* 17873 */ MCD_OPC_Decode, 134, 6, 240, 2, // Opcode: CLGIBAsmE +/* 17878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17887 +/* 17882 */ MCD_OPC_Decode, 136, 6, 240, 2, // Opcode: CLGIBAsmHE +/* 17887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17896 +/* 17891 */ MCD_OPC_Decode, 138, 6, 240, 2, // Opcode: CLGIBAsmLE +/* 17896 */ MCD_OPC_Decode, 133, 6, 241, 2, // Opcode: CLGIBAsm +/* 17901 */ MCD_OPC_FilterValue, 254, 1, 62, 0, // Skip to: 17968 +/* 17906 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17909 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17918 +/* 17913 */ MCD_OPC_Decode, 183, 5, 242, 2, // Opcode: CIBAsmH +/* 17918 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17927 +/* 17922 */ MCD_OPC_Decode, 185, 5, 242, 2, // Opcode: CIBAsmL +/* 17927 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17936 +/* 17931 */ MCD_OPC_Decode, 187, 5, 242, 2, // Opcode: CIBAsmLH +/* 17936 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17945 +/* 17940 */ MCD_OPC_Decode, 182, 5, 242, 2, // Opcode: CIBAsmE +/* 17945 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17954 +/* 17949 */ MCD_OPC_Decode, 184, 5, 242, 2, // Opcode: CIBAsmHE +/* 17954 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17963 +/* 17958 */ MCD_OPC_Decode, 186, 5, 242, 2, // Opcode: CIBAsmLE +/* 17963 */ MCD_OPC_Decode, 181, 5, 243, 2, // Opcode: CIBAsm +/* 17968 */ MCD_OPC_FilterValue, 255, 1, 94, 4, // Skip to: 19091 +/* 17973 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... +/* 17976 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17985 +/* 17980 */ MCD_OPC_Decode, 243, 6, 244, 2, // Opcode: CLIBAsmH +/* 17985 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17994 +/* 17989 */ MCD_OPC_Decode, 245, 6, 244, 2, // Opcode: CLIBAsmL +/* 17994 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 18003 +/* 17998 */ MCD_OPC_Decode, 247, 6, 244, 2, // Opcode: CLIBAsmLH +/* 18003 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 18012 +/* 18007 */ MCD_OPC_Decode, 242, 6, 244, 2, // Opcode: CLIBAsmE +/* 18012 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 18021 +/* 18016 */ MCD_OPC_Decode, 244, 6, 244, 2, // Opcode: CLIBAsmHE +/* 18021 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 18030 +/* 18025 */ MCD_OPC_Decode, 246, 6, 244, 2, // Opcode: CLIBAsmLE +/* 18030 */ MCD_OPC_Decode, 241, 6, 245, 2, // Opcode: CLIBAsm +/* 18035 */ MCD_OPC_FilterValue, 237, 1, 163, 3, // Skip to: 18971 +/* 18040 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 18043 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 18058 +/* 18047 */ MCD_OPC_CheckField, 8, 8, 0, 14, 4, // Skip to: 19091 +/* 18053 */ MCD_OPC_Decode, 149, 10, 246, 2, // Opcode: LDEB +/* 18058 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 18073 +/* 18062 */ MCD_OPC_CheckField, 8, 8, 0, 255, 3, // Skip to: 19091 +/* 18068 */ MCD_OPC_Decode, 235, 12, 247, 2, // Opcode: LXDB +/* 18073 */ MCD_OPC_FilterValue, 6, 11, 0, // Skip to: 18088 +/* 18077 */ MCD_OPC_CheckField, 8, 8, 0, 240, 3, // Skip to: 19091 +/* 18083 */ MCD_OPC_Decode, 240, 12, 247, 2, // Opcode: LXEB +/* 18088 */ MCD_OPC_FilterValue, 7, 11, 0, // Skip to: 18103 +/* 18092 */ MCD_OPC_CheckField, 8, 8, 0, 225, 3, // Skip to: 19091 +/* 18098 */ MCD_OPC_Decode, 214, 13, 248, 2, // Opcode: MXDB +/* 18103 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 18118 +/* 18107 */ MCD_OPC_CheckField, 8, 8, 0, 210, 3, // Skip to: 19091 +/* 18113 */ MCD_OPC_Decode, 223, 9, 249, 2, // Opcode: KEB +/* 18118 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 18133 +/* 18122 */ MCD_OPC_CheckField, 8, 8, 0, 195, 3, // Skip to: 19091 +/* 18128 */ MCD_OPC_Decode, 165, 4, 249, 2, // Opcode: CEB +/* 18133 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 18148 +/* 18137 */ MCD_OPC_CheckField, 8, 8, 0, 180, 3, // Skip to: 19091 +/* 18143 */ MCD_OPC_Decode, 236, 2, 250, 2, // Opcode: AEB +/* 18148 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 18163 +/* 18152 */ MCD_OPC_CheckField, 8, 8, 0, 165, 3, // Skip to: 19091 +/* 18158 */ MCD_OPC_Decode, 197, 14, 250, 2, // Opcode: SEB +/* 18163 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 18178 +/* 18167 */ MCD_OPC_CheckField, 8, 8, 0, 150, 3, // Skip to: 19091 +/* 18173 */ MCD_OPC_Decode, 142, 13, 251, 2, // Opcode: MDEB +/* 18178 */ MCD_OPC_FilterValue, 13, 11, 0, // Skip to: 18193 +/* 18182 */ MCD_OPC_CheckField, 8, 8, 0, 135, 3, // Skip to: 19091 +/* 18188 */ MCD_OPC_Decode, 195, 8, 250, 2, // Opcode: DEB +/* 18193 */ MCD_OPC_FilterValue, 14, 11, 0, // Skip to: 18208 +/* 18197 */ MCD_OPC_CheckField, 8, 4, 0, 120, 3, // Skip to: 19091 +/* 18203 */ MCD_OPC_Decode, 128, 13, 252, 2, // Opcode: MAEB +/* 18208 */ MCD_OPC_FilterValue, 15, 11, 0, // Skip to: 18223 +/* 18212 */ MCD_OPC_CheckField, 8, 4, 0, 105, 3, // Skip to: 19091 +/* 18218 */ MCD_OPC_Decode, 176, 13, 252, 2, // Opcode: MSEB +/* 18223 */ MCD_OPC_FilterValue, 16, 11, 0, // Skip to: 18238 +/* 18227 */ MCD_OPC_CheckField, 8, 8, 0, 90, 3, // Skip to: 19091 +/* 18233 */ MCD_OPC_Decode, 164, 16, 249, 2, // Opcode: TCEB +/* 18238 */ MCD_OPC_FilterValue, 17, 11, 0, // Skip to: 18253 +/* 18242 */ MCD_OPC_CheckField, 8, 8, 0, 75, 3, // Skip to: 19091 +/* 18248 */ MCD_OPC_Decode, 163, 16, 246, 2, // Opcode: TCDB +/* 18253 */ MCD_OPC_FilterValue, 18, 11, 0, // Skip to: 18268 +/* 18257 */ MCD_OPC_CheckField, 8, 8, 0, 60, 3, // Skip to: 19091 +/* 18263 */ MCD_OPC_Decode, 165, 16, 247, 2, // Opcode: TCXB +/* 18268 */ MCD_OPC_FilterValue, 20, 11, 0, // Skip to: 18283 +/* 18272 */ MCD_OPC_CheckField, 8, 8, 0, 45, 3, // Skip to: 19091 +/* 18278 */ MCD_OPC_Decode, 253, 14, 249, 2, // Opcode: SQEB +/* 18283 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 18298 +/* 18287 */ MCD_OPC_CheckField, 8, 8, 0, 30, 3, // Skip to: 19091 +/* 18293 */ MCD_OPC_Decode, 249, 14, 246, 2, // Opcode: SQDB +/* 18298 */ MCD_OPC_FilterValue, 23, 11, 0, // Skip to: 18313 +/* 18302 */ MCD_OPC_CheckField, 8, 8, 0, 15, 3, // Skip to: 19091 +/* 18308 */ MCD_OPC_Decode, 150, 13, 250, 2, // Opcode: MEEB +/* 18313 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 18328 +/* 18317 */ MCD_OPC_CheckField, 8, 8, 0, 0, 3, // Skip to: 19091 +/* 18323 */ MCD_OPC_Decode, 220, 9, 246, 2, // Opcode: KDB +/* 18328 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 18343 +/* 18332 */ MCD_OPC_CheckField, 8, 8, 0, 241, 2, // Skip to: 19091 +/* 18338 */ MCD_OPC_Decode, 140, 4, 246, 2, // Opcode: CDB +/* 18343 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 18358 +/* 18347 */ MCD_OPC_CheckField, 8, 8, 0, 226, 2, // Skip to: 19091 +/* 18353 */ MCD_OPC_Decode, 230, 2, 251, 2, // Opcode: ADB +/* 18358 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 18373 +/* 18362 */ MCD_OPC_CheckField, 8, 8, 0, 211, 2, // Skip to: 19091 +/* 18368 */ MCD_OPC_Decode, 191, 14, 251, 2, // Opcode: SDB +/* 18373 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 18388 +/* 18377 */ MCD_OPC_CheckField, 8, 8, 0, 196, 2, // Skip to: 19091 +/* 18383 */ MCD_OPC_Decode, 139, 13, 251, 2, // Opcode: MDB +/* 18388 */ MCD_OPC_FilterValue, 29, 11, 0, // Skip to: 18403 +/* 18392 */ MCD_OPC_CheckField, 8, 8, 0, 181, 2, // Skip to: 19091 +/* 18398 */ MCD_OPC_Decode, 189, 8, 251, 2, // Opcode: DDB +/* 18403 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 18418 +/* 18407 */ MCD_OPC_CheckField, 8, 4, 0, 166, 2, // Skip to: 19091 +/* 18413 */ MCD_OPC_Decode, 252, 12, 253, 2, // Opcode: MADB +/* 18418 */ MCD_OPC_FilterValue, 31, 11, 0, // Skip to: 18433 +/* 18422 */ MCD_OPC_CheckField, 8, 4, 0, 151, 2, // Skip to: 19091 +/* 18428 */ MCD_OPC_Decode, 172, 13, 253, 2, // Opcode: MSDB +/* 18433 */ MCD_OPC_FilterValue, 36, 11, 0, // Skip to: 18448 +/* 18437 */ MCD_OPC_CheckField, 8, 8, 0, 136, 2, // Skip to: 19091 +/* 18443 */ MCD_OPC_Decode, 147, 10, 246, 2, // Opcode: LDE +/* 18448 */ MCD_OPC_FilterValue, 37, 11, 0, // Skip to: 18463 +/* 18452 */ MCD_OPC_CheckField, 8, 8, 0, 121, 2, // Skip to: 19091 +/* 18458 */ MCD_OPC_Decode, 234, 12, 247, 2, // Opcode: LXD +/* 18463 */ MCD_OPC_FilterValue, 38, 11, 0, // Skip to: 18478 +/* 18467 */ MCD_OPC_CheckField, 8, 8, 0, 106, 2, // Skip to: 19091 +/* 18473 */ MCD_OPC_Decode, 239, 12, 247, 2, // Opcode: LXE +/* 18478 */ MCD_OPC_FilterValue, 46, 11, 0, // Skip to: 18493 +/* 18482 */ MCD_OPC_CheckField, 8, 4, 0, 91, 2, // Skip to: 19091 +/* 18488 */ MCD_OPC_Decode, 255, 12, 252, 2, // Opcode: MAE +/* 18493 */ MCD_OPC_FilterValue, 47, 11, 0, // Skip to: 18508 +/* 18497 */ MCD_OPC_CheckField, 8, 4, 0, 76, 2, // Skip to: 19091 +/* 18503 */ MCD_OPC_Decode, 175, 13, 252, 2, // Opcode: MSE +/* 18508 */ MCD_OPC_FilterValue, 52, 11, 0, // Skip to: 18523 +/* 18512 */ MCD_OPC_CheckField, 8, 8, 0, 61, 2, // Skip to: 19091 +/* 18518 */ MCD_OPC_Decode, 252, 14, 249, 2, // Opcode: SQE +/* 18523 */ MCD_OPC_FilterValue, 53, 11, 0, // Skip to: 18538 +/* 18527 */ MCD_OPC_CheckField, 8, 8, 0, 46, 2, // Skip to: 19091 +/* 18533 */ MCD_OPC_Decode, 248, 14, 246, 2, // Opcode: SQD +/* 18538 */ MCD_OPC_FilterValue, 55, 11, 0, // Skip to: 18553 +/* 18542 */ MCD_OPC_CheckField, 8, 8, 0, 31, 2, // Skip to: 19091 +/* 18548 */ MCD_OPC_Decode, 149, 13, 250, 2, // Opcode: MEE +/* 18553 */ MCD_OPC_FilterValue, 56, 11, 0, // Skip to: 18568 +/* 18557 */ MCD_OPC_CheckField, 8, 4, 0, 16, 2, // Skip to: 19091 +/* 18563 */ MCD_OPC_Decode, 134, 13, 253, 2, // Opcode: MAYL +/* 18568 */ MCD_OPC_FilterValue, 57, 11, 0, // Skip to: 18583 +/* 18572 */ MCD_OPC_CheckField, 8, 4, 0, 1, 2, // Skip to: 19091 +/* 18578 */ MCD_OPC_Decode, 223, 13, 254, 2, // Opcode: MYL +/* 18583 */ MCD_OPC_FilterValue, 58, 11, 0, // Skip to: 18598 +/* 18587 */ MCD_OPC_CheckField, 8, 4, 0, 242, 1, // Skip to: 19091 +/* 18593 */ MCD_OPC_Decode, 131, 13, 255, 2, // Opcode: MAY +/* 18598 */ MCD_OPC_FilterValue, 59, 11, 0, // Skip to: 18613 +/* 18602 */ MCD_OPC_CheckField, 8, 4, 0, 227, 1, // Skip to: 19091 +/* 18608 */ MCD_OPC_Decode, 220, 13, 128, 3, // Opcode: MY +/* 18613 */ MCD_OPC_FilterValue, 60, 11, 0, // Skip to: 18628 +/* 18617 */ MCD_OPC_CheckField, 8, 4, 0, 212, 1, // Skip to: 19091 +/* 18623 */ MCD_OPC_Decode, 132, 13, 253, 2, // Opcode: MAYH +/* 18628 */ MCD_OPC_FilterValue, 61, 11, 0, // Skip to: 18643 +/* 18632 */ MCD_OPC_CheckField, 8, 4, 0, 197, 1, // Skip to: 19091 +/* 18638 */ MCD_OPC_Decode, 221, 13, 254, 2, // Opcode: MYH +/* 18643 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 18658 +/* 18647 */ MCD_OPC_CheckField, 8, 4, 0, 182, 1, // Skip to: 19091 +/* 18653 */ MCD_OPC_Decode, 251, 12, 253, 2, // Opcode: MAD +/* 18658 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 18673 +/* 18662 */ MCD_OPC_CheckField, 8, 4, 0, 167, 1, // Skip to: 19091 +/* 18668 */ MCD_OPC_Decode, 171, 13, 253, 2, // Opcode: MSD +/* 18673 */ MCD_OPC_FilterValue, 64, 11, 0, // Skip to: 18688 +/* 18677 */ MCD_OPC_CheckField, 8, 4, 0, 152, 1, // Skip to: 19091 +/* 18683 */ MCD_OPC_Decode, 225, 14, 254, 2, // Opcode: SLDT +/* 18688 */ MCD_OPC_FilterValue, 65, 11, 0, // Skip to: 18703 +/* 18692 */ MCD_OPC_CheckField, 8, 4, 0, 137, 1, // Skip to: 19091 +/* 18698 */ MCD_OPC_Decode, 136, 15, 254, 2, // Opcode: SRDT +/* 18703 */ MCD_OPC_FilterValue, 72, 11, 0, // Skip to: 18718 +/* 18707 */ MCD_OPC_CheckField, 8, 4, 0, 122, 1, // Skip to: 19091 +/* 18713 */ MCD_OPC_Decode, 240, 14, 129, 3, // Opcode: SLXT +/* 18718 */ MCD_OPC_FilterValue, 73, 11, 0, // Skip to: 18733 +/* 18722 */ MCD_OPC_CheckField, 8, 4, 0, 107, 1, // Skip to: 19091 +/* 18728 */ MCD_OPC_Decode, 147, 15, 129, 3, // Opcode: SRXT +/* 18733 */ MCD_OPC_FilterValue, 80, 11, 0, // Skip to: 18748 +/* 18737 */ MCD_OPC_CheckField, 8, 8, 0, 92, 1, // Skip to: 19091 +/* 18743 */ MCD_OPC_Decode, 167, 16, 249, 2, // Opcode: TDCET +/* 18748 */ MCD_OPC_FilterValue, 81, 11, 0, // Skip to: 18763 +/* 18752 */ MCD_OPC_CheckField, 8, 8, 0, 77, 1, // Skip to: 19091 +/* 18758 */ MCD_OPC_Decode, 170, 16, 249, 2, // Opcode: TDGET +/* 18763 */ MCD_OPC_FilterValue, 84, 11, 0, // Skip to: 18778 +/* 18767 */ MCD_OPC_CheckField, 8, 8, 0, 62, 1, // Skip to: 19091 +/* 18773 */ MCD_OPC_Decode, 166, 16, 246, 2, // Opcode: TDCDT +/* 18778 */ MCD_OPC_FilterValue, 85, 11, 0, // Skip to: 18793 +/* 18782 */ MCD_OPC_CheckField, 8, 8, 0, 47, 1, // Skip to: 19091 +/* 18788 */ MCD_OPC_Decode, 169, 16, 246, 2, // Opcode: TDGDT +/* 18793 */ MCD_OPC_FilterValue, 88, 11, 0, // Skip to: 18808 +/* 18797 */ MCD_OPC_CheckField, 8, 8, 0, 32, 1, // Skip to: 19091 +/* 18803 */ MCD_OPC_Decode, 168, 16, 247, 2, // Opcode: TDCXT +/* 18808 */ MCD_OPC_FilterValue, 89, 11, 0, // Skip to: 18823 +/* 18812 */ MCD_OPC_CheckField, 8, 8, 0, 17, 1, // Skip to: 19091 +/* 18818 */ MCD_OPC_Decode, 171, 16, 247, 2, // Opcode: TDGXT +/* 18823 */ MCD_OPC_FilterValue, 100, 5, 0, // Skip to: 18832 +/* 18827 */ MCD_OPC_Decode, 170, 10, 130, 3, // Opcode: LEY +/* 18832 */ MCD_OPC_FilterValue, 101, 5, 0, // Skip to: 18841 +/* 18836 */ MCD_OPC_Decode, 160, 10, 131, 3, // Opcode: LDY +/* 18841 */ MCD_OPC_FilterValue, 102, 5, 0, // Skip to: 18850 +/* 18845 */ MCD_OPC_Decode, 175, 15, 130, 3, // Opcode: STEY +/* 18850 */ MCD_OPC_FilterValue, 103, 5, 0, // Skip to: 18859 +/* 18854 */ MCD_OPC_Decode, 173, 15, 131, 3, // Opcode: STDY +/* 18859 */ MCD_OPC_FilterValue, 168, 1, 9, 0, // Skip to: 18873 +/* 18864 */ MCD_OPC_CheckPredicate, 25, 223, 0, // Skip to: 19091 +/* 18868 */ MCD_OPC_Decode, 185, 8, 132, 3, // Opcode: CZDT +/* 18873 */ MCD_OPC_FilterValue, 169, 1, 9, 0, // Skip to: 18887 +/* 18878 */ MCD_OPC_CheckPredicate, 25, 209, 0, // Skip to: 19091 +/* 18882 */ MCD_OPC_Decode, 186, 8, 133, 3, // Opcode: CZXT +/* 18887 */ MCD_OPC_FilterValue, 170, 1, 9, 0, // Skip to: 18901 +/* 18892 */ MCD_OPC_CheckPredicate, 25, 195, 0, // Skip to: 19091 +/* 18896 */ MCD_OPC_Decode, 163, 4, 132, 3, // Opcode: CDZT +/* 18901 */ MCD_OPC_FilterValue, 171, 1, 9, 0, // Skip to: 18915 +/* 18906 */ MCD_OPC_CheckPredicate, 25, 181, 0, // Skip to: 19091 +/* 18910 */ MCD_OPC_Decode, 183, 8, 133, 3, // Opcode: CXZT +/* 18915 */ MCD_OPC_FilterValue, 172, 1, 9, 0, // Skip to: 18929 +/* 18920 */ MCD_OPC_CheckPredicate, 26, 167, 0, // Skip to: 19091 +/* 18924 */ MCD_OPC_Decode, 207, 7, 132, 3, // Opcode: CPDT +/* 18929 */ MCD_OPC_FilterValue, 173, 1, 9, 0, // Skip to: 18943 +/* 18934 */ MCD_OPC_CheckPredicate, 26, 153, 0, // Skip to: 19091 +/* 18938 */ MCD_OPC_Decode, 212, 7, 133, 3, // Opcode: CPXT +/* 18943 */ MCD_OPC_FilterValue, 174, 1, 9, 0, // Skip to: 18957 +/* 18948 */ MCD_OPC_CheckPredicate, 26, 139, 0, // Skip to: 19091 +/* 18952 */ MCD_OPC_Decode, 155, 4, 132, 3, // Opcode: CDPT +/* 18957 */ MCD_OPC_FilterValue, 175, 1, 129, 0, // Skip to: 19091 +/* 18962 */ MCD_OPC_CheckPredicate, 26, 125, 0, // Skip to: 19091 +/* 18966 */ MCD_OPC_Decode, 178, 8, 133, 3, // Opcode: CXPT +/* 18971 */ MCD_OPC_FilterValue, 238, 1, 5, 0, // Skip to: 18981 +/* 18976 */ MCD_OPC_Decode, 145, 14, 134, 3, // Opcode: PLO +/* 18981 */ MCD_OPC_FilterValue, 239, 1, 5, 0, // Skip to: 18991 +/* 18986 */ MCD_OPC_Decode, 226, 10, 135, 3, // Opcode: LMD +/* 18991 */ MCD_OPC_FilterValue, 240, 1, 5, 0, // Skip to: 19001 +/* 18996 */ MCD_OPC_Decode, 144, 15, 136, 3, // Opcode: SRP +/* 19001 */ MCD_OPC_FilterValue, 241, 1, 5, 0, // Skip to: 19011 +/* 19006 */ MCD_OPC_Decode, 208, 13, 137, 3, // Opcode: MVO +/* 19011 */ MCD_OPC_FilterValue, 242, 1, 5, 0, // Skip to: 19021 +/* 19016 */ MCD_OPC_Decode, 132, 14, 137, 3, // Opcode: PACK +/* 19021 */ MCD_OPC_FilterValue, 243, 1, 5, 0, // Skip to: 19031 +/* 19026 */ MCD_OPC_Decode, 206, 16, 137, 3, // Opcode: UNPK +/* 19031 */ MCD_OPC_FilterValue, 248, 1, 5, 0, // Skip to: 19041 +/* 19036 */ MCD_OPC_Decode, 239, 21, 137, 3, // Opcode: ZAP +/* 19041 */ MCD_OPC_FilterValue, 249, 1, 5, 0, // Skip to: 19051 +/* 19046 */ MCD_OPC_Decode, 206, 7, 137, 3, // Opcode: CP +/* 19051 */ MCD_OPC_FilterValue, 250, 1, 5, 0, // Skip to: 19061 +/* 19056 */ MCD_OPC_Decode, 152, 3, 137, 3, // Opcode: AP +/* 19061 */ MCD_OPC_FilterValue, 251, 1, 5, 0, // Skip to: 19071 +/* 19066 */ MCD_OPC_Decode, 242, 14, 137, 3, // Opcode: SP +/* 19071 */ MCD_OPC_FilterValue, 252, 1, 5, 0, // Skip to: 19081 +/* 19076 */ MCD_OPC_Decode, 166, 13, 137, 3, // Opcode: MP +/* 19081 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 19091 +/* 19086 */ MCD_OPC_Decode, 205, 8, 137, 3, // Opcode: DP +/* 19091 */ MCD_OPC_Fail, + 0 +}; + +static bool getbool(uint64_t b) +{ + return b != 0; +} + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + switch (Idx) { + default: // llvm_unreachable("Invalid index!"); + case 0: + return getbool((Bits & SystemZ_FeatureFPExtension)); + case 1: + return getbool((Bits & SystemZ_FeatureProcessorAssist)); + case 2: + return getbool((Bits & SystemZ_FeatureTransactionalExecution)); + case 3: + return getbool((Bits & SystemZ_FeatureExecutionHint)); + case 4: + return getbool((Bits & SystemZ_FeatureMessageSecurityAssist3)); + case 5: + return getbool((Bits & SystemZ_FeatureMessageSecurityAssist8)); + case 6: + return getbool((Bits & SystemZ_FeatureMessageSecurityAssist4)); + case 7: + return getbool((Bits & SystemZ_FeatureMessageSecurityAssist5)); + case 8: + return getbool((Bits & SystemZ_FeatureEnhancedDAT2)); + case 9: + return getbool((Bits & SystemZ_FeatureInsertReferenceBitsMultiple)); + case 10: + return getbool((Bits & SystemZ_FeatureResetReferenceBitsMultiple)); + case 11: + return getbool((Bits & SystemZ_FeatureHighWord)); + case 12: + return getbool((Bits & SystemZ_FeatureLoadStoreOnCond2)); + case 13: + return getbool((Bits & SystemZ_FeaturePopulationCount)); + case 14: + return getbool((Bits & SystemZ_FeatureLoadStoreOnCond)); + case 15: + return getbool((Bits & SystemZ_FeatureDistinctOps)); + case 16: + return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions2)); + case 17: + return getbool((Bits & SystemZ_FeatureInterlockedAccess1)); + case 18: + return getbool((Bits & SystemZ_FeatureLoadAndZeroRightmostByte)); + case 19: + return getbool((Bits & SystemZ_FeatureGuardedStorage)); + case 20: + return getbool((Bits & SystemZ_FeatureLoadAndTrap)); + case 21: + return getbool((Bits & SystemZ_FeatureVectorPackedDecimal)); + case 22: + return getbool((Bits & SystemZ_FeatureVector)); + case 23: + return getbool((Bits & SystemZ_FeatureVectorEnhancements1)); + case 24: + return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions)); + case 25: + return getbool((Bits & SystemZ_FeatureDFPZonedConversion)); + case 26: + return getbool((Bits & SystemZ_FeatureDFPPackedConversion)); + } +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + tmp = fieldname(insn, 4, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 12: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 19: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 20: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 21: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 37: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 38: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 39: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 40: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 41: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 42: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 43: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 44: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 45: \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 46: \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 47: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 48: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 49: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 50: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 51: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 52: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 53: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 54: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 55: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 56: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 57: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 58: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 59: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 60: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 61: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 62: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 63: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 64: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 65: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 66: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 67: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 68: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 69: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 70: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 71: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 72: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 73: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 74: \ + tmp = fieldname(insn, 4, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 75: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 76: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 77: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 78: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 79: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 80: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 81: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 82: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 83: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 84: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 85: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 86: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 87: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 88: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 89: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 90: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 91: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 92: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 93: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 94: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 95: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 96: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 97: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 98: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 99: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 100: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 101: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 102: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 103: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 104: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 105: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 106: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 107: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 108: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 109: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 110: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 111: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 112: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 113: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 114: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 115: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 116: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 117: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 118: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 119: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 120: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 121: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 122: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 123: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 124: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 125: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 126: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 127: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 128: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 129: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 130: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 131: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 132: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 133: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 134: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 135: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 136: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 137: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 138: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 139: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 140: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 141: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 142: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 143: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 144: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 145: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 146: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 147: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 148: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 149: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 150: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 151: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 152: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 153: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 154: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 155: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 156: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 157: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 158: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 159: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 160: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 161: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 162: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 163: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 164: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 165: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 166: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 167: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 168: \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 169: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 170: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 171: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 172: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 173: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 174: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 175: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 176: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 177: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 178: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 179: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 180: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 181: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 12); \ + if (decodePC12DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 24); \ + if (decodePC24DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 182: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 183: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 184: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 185: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 186: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 187: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 188: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 189: \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 190: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDRAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 191: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 16) << 0; \ + tmp |= fieldname(insn, 32, 8) << 16; \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 192: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 193: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 194: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 195: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 196: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 197: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 198: \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 199: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 200: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 201: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 202: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 203: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 204: \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 205: \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 206: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 207: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 208: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 209: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 210: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 211: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 212: \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 213: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 214: \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 215: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 216: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 217: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 218: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 219: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 220: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 221: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 222: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 223: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 224: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 225: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 226: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 227: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 228: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 229: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 230: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 231: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 232: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 233: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 234: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 235: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 236: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 237: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 238: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 239: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 240: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 241: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 242: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 243: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 244: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 245: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 246: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 247: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 248: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 249: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 250: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 251: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 252: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 253: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 254: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 255: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 256: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 257: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 258: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 259: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 260: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 261: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 262: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 263: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 264: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 265: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 266: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 267: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 3) << 1; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 268: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 269: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 270: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 21, 3) << 1; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 271: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 272: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 273: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 274: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 275: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 276: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 277: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 278: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 279: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 280: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 281: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 282: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 283: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 284: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 285: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 286: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 287: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 288: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 289: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 290: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 291: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 292: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 293: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 294: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 295: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 296: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 297: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 298: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 299: \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 300: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 301: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 302: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 303: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 304: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 305: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 306: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 307: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 308: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 309: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 310: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 311: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 312: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 313: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 314: \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 315: \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 316: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 317: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 318: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 319: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 320: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 321: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 322: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 323: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 324: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 325: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 326: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 327: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 328: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 329: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 330: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 331: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 332: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 333: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 334: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 335: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 336: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 337: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 338: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 339: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 340: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 341: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 342: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 343: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 344: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 345: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 346: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 347: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 348: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 349: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 350: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 351: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 352: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 353: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 354: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 355: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 356: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 357: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 358: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 359: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 360: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 361: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 362: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 363: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 364: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 365: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 366: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 367: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 368: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 369: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 370: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 371: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 372: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 373: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 374: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 375: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 376: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 377: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 378: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 379: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 380: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 381: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 382: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 383: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 384: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 385: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 386: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 387: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 388: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 389: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 390: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 391: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 392: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 393: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 16) << 0; \ + tmp |= fieldname(insn, 32, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction, uint64_t) +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t) +DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t) diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInsnNameMaps.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInsnNameMaps.inc new file mode 100644 index 0000000..c4d605a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInsnNameMaps.inc @@ -0,0 +1,2348 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + + { SYSZ_INS_A, "a" }, + { SYSZ_INS_ADB, "adb" }, + { SYSZ_INS_ADBR, "adbr" }, + { SYSZ_INS_AEB, "aeb" }, + { SYSZ_INS_AEBR, "aebr" }, + { SYSZ_INS_AFI, "afi" }, + { SYSZ_INS_AG, "ag" }, + { SYSZ_INS_AGF, "agf" }, + { SYSZ_INS_AGFI, "agfi" }, + { SYSZ_INS_AGFR, "agfr" }, + { SYSZ_INS_AGHI, "aghi" }, + { SYSZ_INS_AGHIK, "aghik" }, + { SYSZ_INS_AGR, "agr" }, + { SYSZ_INS_AGRK, "agrk" }, + { SYSZ_INS_AGSI, "agsi" }, + { SYSZ_INS_AH, "ah" }, + { SYSZ_INS_AHI, "ahi" }, + { SYSZ_INS_AHIK, "ahik" }, + { SYSZ_INS_AHY, "ahy" }, + { SYSZ_INS_AIH, "aih" }, + { SYSZ_INS_AL, "al" }, + { SYSZ_INS_ALC, "alc" }, + { SYSZ_INS_ALCG, "alcg" }, + { SYSZ_INS_ALCGR, "alcgr" }, + { SYSZ_INS_ALCR, "alcr" }, + { SYSZ_INS_ALFI, "alfi" }, + { SYSZ_INS_ALG, "alg" }, + { SYSZ_INS_ALGF, "algf" }, + { SYSZ_INS_ALGFI, "algfi" }, + { SYSZ_INS_ALGFR, "algfr" }, + { SYSZ_INS_ALGHSIK, "alghsik" }, + { SYSZ_INS_ALGR, "algr" }, + { SYSZ_INS_ALGRK, "algrk" }, + { SYSZ_INS_ALHSIK, "alhsik" }, + { SYSZ_INS_ALR, "alr" }, + { SYSZ_INS_ALRK, "alrk" }, + { SYSZ_INS_ALY, "aly" }, + { SYSZ_INS_AR, "ar" }, + { SYSZ_INS_ARK, "ark" }, + { SYSZ_INS_ASI, "asi" }, + { SYSZ_INS_AXBR, "axbr" }, + { SYSZ_INS_AY, "ay" }, + { SYSZ_INS_BCR, "bcr" }, + { SYSZ_INS_BRC, "brc" }, + { SYSZ_INS_BRCL, "brcl" }, + { SYSZ_INS_CGIJ, "cgij" }, + { SYSZ_INS_CGRJ, "cgrj" }, + { SYSZ_INS_CIJ, "cij" }, + { SYSZ_INS_CLGIJ, "clgij" }, + { SYSZ_INS_CLGRJ, "clgrj" }, + { SYSZ_INS_CLIJ, "clij" }, + { SYSZ_INS_CLRJ, "clrj" }, + { SYSZ_INS_CRJ, "crj" }, + { SYSZ_INS_BER, "ber" }, + { SYSZ_INS_JE, "je" }, + { SYSZ_INS_JGE, "jge" }, + { SYSZ_INS_LOCE, "loce" }, + { SYSZ_INS_LOCGE, "locge" }, + { SYSZ_INS_LOCGRE, "locgre" }, + { SYSZ_INS_LOCRE, "locre" }, + { SYSZ_INS_STOCE, "stoce" }, + { SYSZ_INS_STOCGE, "stocge" }, + { SYSZ_INS_BHR, "bhr" }, + { SYSZ_INS_BHER, "bher" }, + { SYSZ_INS_JHE, "jhe" }, + { SYSZ_INS_JGHE, "jghe" }, + { SYSZ_INS_LOCHE, "loche" }, + { SYSZ_INS_LOCGHE, "locghe" }, + { SYSZ_INS_LOCGRHE, "locgrhe" }, + { SYSZ_INS_LOCRHE, "locrhe" }, + { SYSZ_INS_STOCHE, "stoche" }, + { SYSZ_INS_STOCGHE, "stocghe" }, + { SYSZ_INS_JH, "jh" }, + { SYSZ_INS_JGH, "jgh" }, + { SYSZ_INS_LOCH, "loch" }, + { SYSZ_INS_LOCGH, "locgh" }, + { SYSZ_INS_LOCGRH, "locgrh" }, + { SYSZ_INS_LOCRH, "locrh" }, + { SYSZ_INS_STOCH, "stoch" }, + { SYSZ_INS_STOCGH, "stocgh" }, + { SYSZ_INS_CGIJNLH, "cgijnlh" }, + { SYSZ_INS_CGRJNLH, "cgrjnlh" }, + { SYSZ_INS_CIJNLH, "cijnlh" }, + { SYSZ_INS_CLGIJNLH, "clgijnlh" }, + { SYSZ_INS_CLGRJNLH, "clgrjnlh" }, + { SYSZ_INS_CLIJNLH, "clijnlh" }, + { SYSZ_INS_CLRJNLH, "clrjnlh" }, + { SYSZ_INS_CRJNLH, "crjnlh" }, + { SYSZ_INS_CGIJE, "cgije" }, + { SYSZ_INS_CGRJE, "cgrje" }, + { SYSZ_INS_CIJE, "cije" }, + { SYSZ_INS_CLGIJE, "clgije" }, + { SYSZ_INS_CLGRJE, "clgrje" }, + { SYSZ_INS_CLIJE, "clije" }, + { SYSZ_INS_CLRJE, "clrje" }, + { SYSZ_INS_CRJE, "crje" }, + { SYSZ_INS_CGIJNLE, "cgijnle" }, + { SYSZ_INS_CGRJNLE, "cgrjnle" }, + { SYSZ_INS_CIJNLE, "cijnle" }, + { SYSZ_INS_CLGIJNLE, "clgijnle" }, + { SYSZ_INS_CLGRJNLE, "clgrjnle" }, + { SYSZ_INS_CLIJNLE, "clijnle" }, + { SYSZ_INS_CLRJNLE, "clrjnle" }, + { SYSZ_INS_CRJNLE, "crjnle" }, + { SYSZ_INS_CGIJH, "cgijh" }, + { SYSZ_INS_CGRJH, "cgrjh" }, + { SYSZ_INS_CIJH, "cijh" }, + { SYSZ_INS_CLGIJH, "clgijh" }, + { SYSZ_INS_CLGRJH, "clgrjh" }, + { SYSZ_INS_CLIJH, "clijh" }, + { SYSZ_INS_CLRJH, "clrjh" }, + { SYSZ_INS_CRJH, "crjh" }, + { SYSZ_INS_CGIJNL, "cgijnl" }, + { SYSZ_INS_CGRJNL, "cgrjnl" }, + { SYSZ_INS_CIJNL, "cijnl" }, + { SYSZ_INS_CLGIJNL, "clgijnl" }, + { SYSZ_INS_CLGRJNL, "clgrjnl" }, + { SYSZ_INS_CLIJNL, "clijnl" }, + { SYSZ_INS_CLRJNL, "clrjnl" }, + { SYSZ_INS_CRJNL, "crjnl" }, + { SYSZ_INS_CGIJHE, "cgijhe" }, + { SYSZ_INS_CGRJHE, "cgrjhe" }, + { SYSZ_INS_CIJHE, "cijhe" }, + { SYSZ_INS_CLGIJHE, "clgijhe" }, + { SYSZ_INS_CLGRJHE, "clgrjhe" }, + { SYSZ_INS_CLIJHE, "clijhe" }, + { SYSZ_INS_CLRJHE, "clrjhe" }, + { SYSZ_INS_CRJHE, "crjhe" }, + { SYSZ_INS_CGIJNHE, "cgijnhe" }, + { SYSZ_INS_CGRJNHE, "cgrjnhe" }, + { SYSZ_INS_CIJNHE, "cijnhe" }, + { SYSZ_INS_CLGIJNHE, "clgijnhe" }, + { SYSZ_INS_CLGRJNHE, "clgrjnhe" }, + { SYSZ_INS_CLIJNHE, "clijnhe" }, + { SYSZ_INS_CLRJNHE, "clrjnhe" }, + { SYSZ_INS_CRJNHE, "crjnhe" }, + { SYSZ_INS_CGIJL, "cgijl" }, + { SYSZ_INS_CGRJL, "cgrjl" }, + { SYSZ_INS_CIJL, "cijl" }, + { SYSZ_INS_CLGIJL, "clgijl" }, + { SYSZ_INS_CLGRJL, "clgrjl" }, + { SYSZ_INS_CLIJL, "clijl" }, + { SYSZ_INS_CLRJL, "clrjl" }, + { SYSZ_INS_CRJL, "crjl" }, + { SYSZ_INS_CGIJNH, "cgijnh" }, + { SYSZ_INS_CGRJNH, "cgrjnh" }, + { SYSZ_INS_CIJNH, "cijnh" }, + { SYSZ_INS_CLGIJNH, "clgijnh" }, + { SYSZ_INS_CLGRJNH, "clgrjnh" }, + { SYSZ_INS_CLIJNH, "clijnh" }, + { SYSZ_INS_CLRJNH, "clrjnh" }, + { SYSZ_INS_CRJNH, "crjnh" }, + { SYSZ_INS_CGIJLE, "cgijle" }, + { SYSZ_INS_CGRJLE, "cgrjle" }, + { SYSZ_INS_CIJLE, "cijle" }, + { SYSZ_INS_CLGIJLE, "clgijle" }, + { SYSZ_INS_CLGRJLE, "clgrjle" }, + { SYSZ_INS_CLIJLE, "clijle" }, + { SYSZ_INS_CLRJLE, "clrjle" }, + { SYSZ_INS_CRJLE, "crjle" }, + { SYSZ_INS_CGIJNE, "cgijne" }, + { SYSZ_INS_CGRJNE, "cgrjne" }, + { SYSZ_INS_CIJNE, "cijne" }, + { SYSZ_INS_CLGIJNE, "clgijne" }, + { SYSZ_INS_CLGRJNE, "clgrjne" }, + { SYSZ_INS_CLIJNE, "clijne" }, + { SYSZ_INS_CLRJNE, "clrjne" }, + { SYSZ_INS_CRJNE, "crjne" }, + { SYSZ_INS_CGIJLH, "cgijlh" }, + { SYSZ_INS_CGRJLH, "cgrjlh" }, + { SYSZ_INS_CIJLH, "cijlh" }, + { SYSZ_INS_CLGIJLH, "clgijlh" }, + { SYSZ_INS_CLGRJLH, "clgrjlh" }, + { SYSZ_INS_CLIJLH, "clijlh" }, + { SYSZ_INS_CLRJLH, "clrjlh" }, + { SYSZ_INS_CRJLH, "crjlh" }, + { SYSZ_INS_BLR, "blr" }, + { SYSZ_INS_BLER, "bler" }, + { SYSZ_INS_JLE, "jle" }, + { SYSZ_INS_JGLE, "jgle" }, + { SYSZ_INS_LOCLE, "locle" }, + { SYSZ_INS_LOCGLE, "locgle" }, + { SYSZ_INS_LOCGRLE, "locgrle" }, + { SYSZ_INS_LOCRLE, "locrle" }, + { SYSZ_INS_STOCLE, "stocle" }, + { SYSZ_INS_STOCGLE, "stocgle" }, + { SYSZ_INS_BLHR, "blhr" }, + { SYSZ_INS_JLH, "jlh" }, + { SYSZ_INS_JGLH, "jglh" }, + { SYSZ_INS_LOCLH, "loclh" }, + { SYSZ_INS_LOCGLH, "locglh" }, + { SYSZ_INS_LOCGRLH, "locgrlh" }, + { SYSZ_INS_LOCRLH, "locrlh" }, + { SYSZ_INS_STOCLH, "stoclh" }, + { SYSZ_INS_STOCGLH, "stocglh" }, + { SYSZ_INS_JL, "jl" }, + { SYSZ_INS_JGL, "jgl" }, + { SYSZ_INS_LOCL, "locl" }, + { SYSZ_INS_LOCGL, "locgl" }, + { SYSZ_INS_LOCGRL, "locgrl" }, + { SYSZ_INS_LOCRL, "locrl" }, + { SYSZ_INS_LOC, "loc" }, + { SYSZ_INS_LOCG, "locg" }, + { SYSZ_INS_LOCGR, "locgr" }, + { SYSZ_INS_LOCR, "locr" }, + { SYSZ_INS_STOCL, "stocl" }, + { SYSZ_INS_STOCGL, "stocgl" }, + { SYSZ_INS_BNER, "bner" }, + { SYSZ_INS_JNE, "jne" }, + { SYSZ_INS_JGNE, "jgne" }, + { SYSZ_INS_LOCNE, "locne" }, + { SYSZ_INS_LOCGNE, "locgne" }, + { SYSZ_INS_LOCGRNE, "locgrne" }, + { SYSZ_INS_LOCRNE, "locrne" }, + { SYSZ_INS_STOCNE, "stocne" }, + { SYSZ_INS_STOCGNE, "stocgne" }, + { SYSZ_INS_BNHR, "bnhr" }, + { SYSZ_INS_BNHER, "bnher" }, + { SYSZ_INS_JNHE, "jnhe" }, + { SYSZ_INS_JGNHE, "jgnhe" }, + { SYSZ_INS_LOCNHE, "locnhe" }, + { SYSZ_INS_LOCGNHE, "locgnhe" }, + { SYSZ_INS_LOCGRNHE, "locgrnhe" }, + { SYSZ_INS_LOCRNHE, "locrnhe" }, + { SYSZ_INS_STOCNHE, "stocnhe" }, + { SYSZ_INS_STOCGNHE, "stocgnhe" }, + { SYSZ_INS_JNH, "jnh" }, + { SYSZ_INS_JGNH, "jgnh" }, + { SYSZ_INS_LOCNH, "locnh" }, + { SYSZ_INS_LOCGNH, "locgnh" }, + { SYSZ_INS_LOCGRNH, "locgrnh" }, + { SYSZ_INS_LOCRNH, "locrnh" }, + { SYSZ_INS_STOCNH, "stocnh" }, + { SYSZ_INS_STOCGNH, "stocgnh" }, + { SYSZ_INS_BNLR, "bnlr" }, + { SYSZ_INS_BNLER, "bnler" }, + { SYSZ_INS_JNLE, "jnle" }, + { SYSZ_INS_JGNLE, "jgnle" }, + { SYSZ_INS_LOCNLE, "locnle" }, + { SYSZ_INS_LOCGNLE, "locgnle" }, + { SYSZ_INS_LOCGRNLE, "locgrnle" }, + { SYSZ_INS_LOCRNLE, "locrnle" }, + { SYSZ_INS_STOCNLE, "stocnle" }, + { SYSZ_INS_STOCGNLE, "stocgnle" }, + { SYSZ_INS_BNLHR, "bnlhr" }, + { SYSZ_INS_JNLH, "jnlh" }, + { SYSZ_INS_JGNLH, "jgnlh" }, + { SYSZ_INS_LOCNLH, "locnlh" }, + { SYSZ_INS_LOCGNLH, "locgnlh" }, + { SYSZ_INS_LOCGRNLH, "locgrnlh" }, + { SYSZ_INS_LOCRNLH, "locrnlh" }, + { SYSZ_INS_STOCNLH, "stocnlh" }, + { SYSZ_INS_STOCGNLH, "stocgnlh" }, + { SYSZ_INS_JNL, "jnl" }, + { SYSZ_INS_JGNL, "jgnl" }, + { SYSZ_INS_LOCNL, "locnl" }, + { SYSZ_INS_LOCGNL, "locgnl" }, + { SYSZ_INS_LOCGRNL, "locgrnl" }, + { SYSZ_INS_LOCRNL, "locrnl" }, + { SYSZ_INS_STOCNL, "stocnl" }, + { SYSZ_INS_STOCGNL, "stocgnl" }, + { SYSZ_INS_BNOR, "bnor" }, + { SYSZ_INS_JNO, "jno" }, + { SYSZ_INS_JGNO, "jgno" }, + { SYSZ_INS_LOCNO, "locno" }, + { SYSZ_INS_LOCGNO, "locgno" }, + { SYSZ_INS_LOCGRNO, "locgrno" }, + { SYSZ_INS_LOCRNO, "locrno" }, + { SYSZ_INS_STOCNO, "stocno" }, + { SYSZ_INS_STOCGNO, "stocgno" }, + { SYSZ_INS_BOR, "bor" }, + { SYSZ_INS_JO, "jo" }, + { SYSZ_INS_JGO, "jgo" }, + { SYSZ_INS_LOCO, "loco" }, + { SYSZ_INS_LOCGO, "locgo" }, + { SYSZ_INS_LOCGRO, "locgro" }, + { SYSZ_INS_LOCRO, "locro" }, + { SYSZ_INS_STOCO, "stoco" }, + { SYSZ_INS_STOCGO, "stocgo" }, + { SYSZ_INS_STOC, "stoc" }, + { SYSZ_INS_STOCG, "stocg" }, + { SYSZ_INS_BASR, "basr" }, + { SYSZ_INS_BR, "br" }, + { SYSZ_INS_BRAS, "bras" }, + { SYSZ_INS_BRASL, "brasl" }, + { SYSZ_INS_J, "j" }, + { SYSZ_INS_JG, "jg" }, + { SYSZ_INS_BRCT, "brct" }, + { SYSZ_INS_BRCTG, "brctg" }, + { SYSZ_INS_C, "c" }, + { SYSZ_INS_CDB, "cdb" }, + { SYSZ_INS_CDBR, "cdbr" }, + { SYSZ_INS_CDFBR, "cdfbr" }, + { SYSZ_INS_CDGBR, "cdgbr" }, + { SYSZ_INS_CDLFBR, "cdlfbr" }, + { SYSZ_INS_CDLGBR, "cdlgbr" }, + { SYSZ_INS_CEB, "ceb" }, + { SYSZ_INS_CEBR, "cebr" }, + { SYSZ_INS_CEFBR, "cefbr" }, + { SYSZ_INS_CEGBR, "cegbr" }, + { SYSZ_INS_CELFBR, "celfbr" }, + { SYSZ_INS_CELGBR, "celgbr" }, + { SYSZ_INS_CFDBR, "cfdbr" }, + { SYSZ_INS_CFEBR, "cfebr" }, + { SYSZ_INS_CFI, "cfi" }, + { SYSZ_INS_CFXBR, "cfxbr" }, + { SYSZ_INS_CG, "cg" }, + { SYSZ_INS_CGDBR, "cgdbr" }, + { SYSZ_INS_CGEBR, "cgebr" }, + { SYSZ_INS_CGF, "cgf" }, + { SYSZ_INS_CGFI, "cgfi" }, + { SYSZ_INS_CGFR, "cgfr" }, + { SYSZ_INS_CGFRL, "cgfrl" }, + { SYSZ_INS_CGH, "cgh" }, + { SYSZ_INS_CGHI, "cghi" }, + { SYSZ_INS_CGHRL, "cghrl" }, + { SYSZ_INS_CGHSI, "cghsi" }, + { SYSZ_INS_CGR, "cgr" }, + { SYSZ_INS_CGRL, "cgrl" }, + { SYSZ_INS_CGXBR, "cgxbr" }, + { SYSZ_INS_CH, "ch" }, + { SYSZ_INS_CHF, "chf" }, + { SYSZ_INS_CHHSI, "chhsi" }, + { SYSZ_INS_CHI, "chi" }, + { SYSZ_INS_CHRL, "chrl" }, + { SYSZ_INS_CHSI, "chsi" }, + { SYSZ_INS_CHY, "chy" }, + { SYSZ_INS_CIH, "cih" }, + { SYSZ_INS_CL, "cl" }, + { SYSZ_INS_CLC, "clc" }, + { SYSZ_INS_CLFDBR, "clfdbr" }, + { SYSZ_INS_CLFEBR, "clfebr" }, + { SYSZ_INS_CLFHSI, "clfhsi" }, + { SYSZ_INS_CLFI, "clfi" }, + { SYSZ_INS_CLFXBR, "clfxbr" }, + { SYSZ_INS_CLG, "clg" }, + { SYSZ_INS_CLGDBR, "clgdbr" }, + { SYSZ_INS_CLGEBR, "clgebr" }, + { SYSZ_INS_CLGF, "clgf" }, + { SYSZ_INS_CLGFI, "clgfi" }, + { SYSZ_INS_CLGFR, "clgfr" }, + { SYSZ_INS_CLGFRL, "clgfrl" }, + { SYSZ_INS_CLGHRL, "clghrl" }, + { SYSZ_INS_CLGHSI, "clghsi" }, + { SYSZ_INS_CLGR, "clgr" }, + { SYSZ_INS_CLGRL, "clgrl" }, + { SYSZ_INS_CLGXBR, "clgxbr" }, + { SYSZ_INS_CLHF, "clhf" }, + { SYSZ_INS_CLHHSI, "clhhsi" }, + { SYSZ_INS_CLHRL, "clhrl" }, + { SYSZ_INS_CLI, "cli" }, + { SYSZ_INS_CLIH, "clih" }, + { SYSZ_INS_CLIY, "cliy" }, + { SYSZ_INS_CLR, "clr" }, + { SYSZ_INS_CLRL, "clrl" }, + { SYSZ_INS_CLST, "clst" }, + { SYSZ_INS_CLY, "cly" }, + { SYSZ_INS_CPSDR, "cpsdr" }, + { SYSZ_INS_CR, "cr" }, + { SYSZ_INS_CRL, "crl" }, + { SYSZ_INS_CS, "cs" }, + { SYSZ_INS_CSG, "csg" }, + { SYSZ_INS_CSY, "csy" }, + { SYSZ_INS_CXBR, "cxbr" }, + { SYSZ_INS_CXFBR, "cxfbr" }, + { SYSZ_INS_CXGBR, "cxgbr" }, + { SYSZ_INS_CXLFBR, "cxlfbr" }, + { SYSZ_INS_CXLGBR, "cxlgbr" }, + { SYSZ_INS_CY, "cy" }, + { SYSZ_INS_DDB, "ddb" }, + { SYSZ_INS_DDBR, "ddbr" }, + { SYSZ_INS_DEB, "deb" }, + { SYSZ_INS_DEBR, "debr" }, + { SYSZ_INS_DL, "dl" }, + { SYSZ_INS_DLG, "dlg" }, + { SYSZ_INS_DLGR, "dlgr" }, + { SYSZ_INS_DLR, "dlr" }, + { SYSZ_INS_DSG, "dsg" }, + { SYSZ_INS_DSGF, "dsgf" }, + { SYSZ_INS_DSGFR, "dsgfr" }, + { SYSZ_INS_DSGR, "dsgr" }, + { SYSZ_INS_DXBR, "dxbr" }, + { SYSZ_INS_EAR, "ear" }, + { SYSZ_INS_FIDBR, "fidbr" }, + { SYSZ_INS_FIDBRA, "fidbra" }, + { SYSZ_INS_FIEBR, "fiebr" }, + { SYSZ_INS_FIEBRA, "fiebra" }, + { SYSZ_INS_FIXBR, "fixbr" }, + { SYSZ_INS_FIXBRA, "fixbra" }, + { SYSZ_INS_FLOGR, "flogr" }, + { SYSZ_INS_IC, "ic" }, + { SYSZ_INS_ICY, "icy" }, + { SYSZ_INS_IIHF, "iihf" }, + { SYSZ_INS_IIHH, "iihh" }, + { SYSZ_INS_IIHL, "iihl" }, + { SYSZ_INS_IILF, "iilf" }, + { SYSZ_INS_IILH, "iilh" }, + { SYSZ_INS_IILL, "iill" }, + { SYSZ_INS_IPM, "ipm" }, + { SYSZ_INS_L, "l" }, + { SYSZ_INS_LA, "la" }, + { SYSZ_INS_LAA, "laa" }, + { SYSZ_INS_LAAG, "laag" }, + { SYSZ_INS_LAAL, "laal" }, + { SYSZ_INS_LAALG, "laalg" }, + { SYSZ_INS_LAN, "lan" }, + { SYSZ_INS_LANG, "lang" }, + { SYSZ_INS_LAO, "lao" }, + { SYSZ_INS_LAOG, "laog" }, + { SYSZ_INS_LARL, "larl" }, + { SYSZ_INS_LAX, "lax" }, + { SYSZ_INS_LAXG, "laxg" }, + { SYSZ_INS_LAY, "lay" }, + { SYSZ_INS_LB, "lb" }, + { SYSZ_INS_LBH, "lbh" }, + { SYSZ_INS_LBR, "lbr" }, + { SYSZ_INS_LCDBR, "lcdbr" }, + { SYSZ_INS_LCEBR, "lcebr" }, + { SYSZ_INS_LCGFR, "lcgfr" }, + { SYSZ_INS_LCGR, "lcgr" }, + { SYSZ_INS_LCR, "lcr" }, + { SYSZ_INS_LCXBR, "lcxbr" }, + { SYSZ_INS_LD, "ld" }, + { SYSZ_INS_LDEB, "ldeb" }, + { SYSZ_INS_LDEBR, "ldebr" }, + { SYSZ_INS_LDGR, "ldgr" }, + { SYSZ_INS_LDR, "ldr" }, + { SYSZ_INS_LDXBR, "ldxbr" }, + { SYSZ_INS_LDXBRA, "ldxbra" }, + { SYSZ_INS_LDY, "ldy" }, + { SYSZ_INS_LE, "le" }, + { SYSZ_INS_LEDBR, "ledbr" }, + { SYSZ_INS_LEDBRA, "ledbra" }, + { SYSZ_INS_LER, "ler" }, + { SYSZ_INS_LEXBR, "lexbr" }, + { SYSZ_INS_LEXBRA, "lexbra" }, + { SYSZ_INS_LEY, "ley" }, + { SYSZ_INS_LFH, "lfh" }, + { SYSZ_INS_LG, "lg" }, + { SYSZ_INS_LGB, "lgb" }, + { SYSZ_INS_LGBR, "lgbr" }, + { SYSZ_INS_LGDR, "lgdr" }, + { SYSZ_INS_LGF, "lgf" }, + { SYSZ_INS_LGFI, "lgfi" }, + { SYSZ_INS_LGFR, "lgfr" }, + { SYSZ_INS_LGFRL, "lgfrl" }, + { SYSZ_INS_LGH, "lgh" }, + { SYSZ_INS_LGHI, "lghi" }, + { SYSZ_INS_LGHR, "lghr" }, + { SYSZ_INS_LGHRL, "lghrl" }, + { SYSZ_INS_LGR, "lgr" }, + { SYSZ_INS_LGRL, "lgrl" }, + { SYSZ_INS_LH, "lh" }, + { SYSZ_INS_LHH, "lhh" }, + { SYSZ_INS_LHI, "lhi" }, + { SYSZ_INS_LHR, "lhr" }, + { SYSZ_INS_LHRL, "lhrl" }, + { SYSZ_INS_LHY, "lhy" }, + { SYSZ_INS_LLC, "llc" }, + { SYSZ_INS_LLCH, "llch" }, + { SYSZ_INS_LLCR, "llcr" }, + { SYSZ_INS_LLGC, "llgc" }, + { SYSZ_INS_LLGCR, "llgcr" }, + { SYSZ_INS_LLGF, "llgf" }, + { SYSZ_INS_LLGFR, "llgfr" }, + { SYSZ_INS_LLGFRL, "llgfrl" }, + { SYSZ_INS_LLGH, "llgh" }, + { SYSZ_INS_LLGHR, "llghr" }, + { SYSZ_INS_LLGHRL, "llghrl" }, + { SYSZ_INS_LLH, "llh" }, + { SYSZ_INS_LLHH, "llhh" }, + { SYSZ_INS_LLHR, "llhr" }, + { SYSZ_INS_LLHRL, "llhrl" }, + { SYSZ_INS_LLIHF, "llihf" }, + { SYSZ_INS_LLIHH, "llihh" }, + { SYSZ_INS_LLIHL, "llihl" }, + { SYSZ_INS_LLILF, "llilf" }, + { SYSZ_INS_LLILH, "llilh" }, + { SYSZ_INS_LLILL, "llill" }, + { SYSZ_INS_LMG, "lmg" }, + { SYSZ_INS_LNDBR, "lndbr" }, + { SYSZ_INS_LNEBR, "lnebr" }, + { SYSZ_INS_LNGFR, "lngfr" }, + { SYSZ_INS_LNGR, "lngr" }, + { SYSZ_INS_LNR, "lnr" }, + { SYSZ_INS_LNXBR, "lnxbr" }, + { SYSZ_INS_LPDBR, "lpdbr" }, + { SYSZ_INS_LPEBR, "lpebr" }, + { SYSZ_INS_LPGFR, "lpgfr" }, + { SYSZ_INS_LPGR, "lpgr" }, + { SYSZ_INS_LPR, "lpr" }, + { SYSZ_INS_LPXBR, "lpxbr" }, + { SYSZ_INS_LR, "lr" }, + { SYSZ_INS_LRL, "lrl" }, + { SYSZ_INS_LRV, "lrv" }, + { SYSZ_INS_LRVG, "lrvg" }, + { SYSZ_INS_LRVGR, "lrvgr" }, + { SYSZ_INS_LRVR, "lrvr" }, + { SYSZ_INS_LT, "lt" }, + { SYSZ_INS_LTDBR, "ltdbr" }, + { SYSZ_INS_LTEBR, "ltebr" }, + { SYSZ_INS_LTG, "ltg" }, + { SYSZ_INS_LTGF, "ltgf" }, + { SYSZ_INS_LTGFR, "ltgfr" }, + { SYSZ_INS_LTGR, "ltgr" }, + { SYSZ_INS_LTR, "ltr" }, + { SYSZ_INS_LTXBR, "ltxbr" }, + { SYSZ_INS_LXDB, "lxdb" }, + { SYSZ_INS_LXDBR, "lxdbr" }, + { SYSZ_INS_LXEB, "lxeb" }, + { SYSZ_INS_LXEBR, "lxebr" }, + { SYSZ_INS_LXR, "lxr" }, + { SYSZ_INS_LY, "ly" }, + { SYSZ_INS_LZDR, "lzdr" }, + { SYSZ_INS_LZER, "lzer" }, + { SYSZ_INS_LZXR, "lzxr" }, + { SYSZ_INS_MADB, "madb" }, + { SYSZ_INS_MADBR, "madbr" }, + { SYSZ_INS_MAEB, "maeb" }, + { SYSZ_INS_MAEBR, "maebr" }, + { SYSZ_INS_MDB, "mdb" }, + { SYSZ_INS_MDBR, "mdbr" }, + { SYSZ_INS_MDEB, "mdeb" }, + { SYSZ_INS_MDEBR, "mdebr" }, + { SYSZ_INS_MEEB, "meeb" }, + { SYSZ_INS_MEEBR, "meebr" }, + { SYSZ_INS_MGHI, "mghi" }, + { SYSZ_INS_MH, "mh" }, + { SYSZ_INS_MHI, "mhi" }, + { SYSZ_INS_MHY, "mhy" }, + { SYSZ_INS_MLG, "mlg" }, + { SYSZ_INS_MLGR, "mlgr" }, + { SYSZ_INS_MS, "ms" }, + { SYSZ_INS_MSDB, "msdb" }, + { SYSZ_INS_MSDBR, "msdbr" }, + { SYSZ_INS_MSEB, "mseb" }, + { SYSZ_INS_MSEBR, "msebr" }, + { SYSZ_INS_MSFI, "msfi" }, + { SYSZ_INS_MSG, "msg" }, + { SYSZ_INS_MSGF, "msgf" }, + { SYSZ_INS_MSGFI, "msgfi" }, + { SYSZ_INS_MSGFR, "msgfr" }, + { SYSZ_INS_MSGR, "msgr" }, + { SYSZ_INS_MSR, "msr" }, + { SYSZ_INS_MSY, "msy" }, + { SYSZ_INS_MVC, "mvc" }, + { SYSZ_INS_MVGHI, "mvghi" }, + { SYSZ_INS_MVHHI, "mvhhi" }, + { SYSZ_INS_MVHI, "mvhi" }, + { SYSZ_INS_MVI, "mvi" }, + { SYSZ_INS_MVIY, "mviy" }, + { SYSZ_INS_MVST, "mvst" }, + { SYSZ_INS_MXBR, "mxbr" }, + { SYSZ_INS_MXDB, "mxdb" }, + { SYSZ_INS_MXDBR, "mxdbr" }, + { SYSZ_INS_N, "n" }, + { SYSZ_INS_NC, "nc" }, + { SYSZ_INS_NG, "ng" }, + { SYSZ_INS_NGR, "ngr" }, + { SYSZ_INS_NGRK, "ngrk" }, + { SYSZ_INS_NI, "ni" }, + { SYSZ_INS_NIHF, "nihf" }, + { SYSZ_INS_NIHH, "nihh" }, + { SYSZ_INS_NIHL, "nihl" }, + { SYSZ_INS_NILF, "nilf" }, + { SYSZ_INS_NILH, "nilh" }, + { SYSZ_INS_NILL, "nill" }, + { SYSZ_INS_NIY, "niy" }, + { SYSZ_INS_NR, "nr" }, + { SYSZ_INS_NRK, "nrk" }, + { SYSZ_INS_NY, "ny" }, + { SYSZ_INS_O, "o" }, + { SYSZ_INS_OC, "oc" }, + { SYSZ_INS_OG, "og" }, + { SYSZ_INS_OGR, "ogr" }, + { SYSZ_INS_OGRK, "ogrk" }, + { SYSZ_INS_OI, "oi" }, + { SYSZ_INS_OIHF, "oihf" }, + { SYSZ_INS_OIHH, "oihh" }, + { SYSZ_INS_OIHL, "oihl" }, + { SYSZ_INS_OILF, "oilf" }, + { SYSZ_INS_OILH, "oilh" }, + { SYSZ_INS_OILL, "oill" }, + { SYSZ_INS_OIY, "oiy" }, + { SYSZ_INS_OR, "or" }, + { SYSZ_INS_ORK, "ork" }, + { SYSZ_INS_OY, "oy" }, + { SYSZ_INS_PFD, "pfd" }, + { SYSZ_INS_PFDRL, "pfdrl" }, + { SYSZ_INS_RISBG, "risbg" }, + { SYSZ_INS_RISBHG, "risbhg" }, + { SYSZ_INS_RISBLG, "risblg" }, + { SYSZ_INS_RLL, "rll" }, + { SYSZ_INS_RLLG, "rllg" }, + { SYSZ_INS_RNSBG, "rnsbg" }, + { SYSZ_INS_ROSBG, "rosbg" }, + { SYSZ_INS_RXSBG, "rxsbg" }, + { SYSZ_INS_S, "s" }, + { SYSZ_INS_SDB, "sdb" }, + { SYSZ_INS_SDBR, "sdbr" }, + { SYSZ_INS_SEB, "seb" }, + { SYSZ_INS_SEBR, "sebr" }, + { SYSZ_INS_SG, "sg" }, + { SYSZ_INS_SGF, "sgf" }, + { SYSZ_INS_SGFR, "sgfr" }, + { SYSZ_INS_SGR, "sgr" }, + { SYSZ_INS_SGRK, "sgrk" }, + { SYSZ_INS_SH, "sh" }, + { SYSZ_INS_SHY, "shy" }, + { SYSZ_INS_SL, "sl" }, + { SYSZ_INS_SLB, "slb" }, + { SYSZ_INS_SLBG, "slbg" }, + { SYSZ_INS_SLBR, "slbr" }, + { SYSZ_INS_SLFI, "slfi" }, + { SYSZ_INS_SLG, "slg" }, + { SYSZ_INS_SLBGR, "slbgr" }, + { SYSZ_INS_SLGF, "slgf" }, + { SYSZ_INS_SLGFI, "slgfi" }, + { SYSZ_INS_SLGFR, "slgfr" }, + { SYSZ_INS_SLGR, "slgr" }, + { SYSZ_INS_SLGRK, "slgrk" }, + { SYSZ_INS_SLL, "sll" }, + { SYSZ_INS_SLLG, "sllg" }, + { SYSZ_INS_SLLK, "sllk" }, + { SYSZ_INS_SLR, "slr" }, + { SYSZ_INS_SLRK, "slrk" }, + { SYSZ_INS_SLY, "sly" }, + { SYSZ_INS_SQDB, "sqdb" }, + { SYSZ_INS_SQDBR, "sqdbr" }, + { SYSZ_INS_SQEB, "sqeb" }, + { SYSZ_INS_SQEBR, "sqebr" }, + { SYSZ_INS_SQXBR, "sqxbr" }, + { SYSZ_INS_SR, "sr" }, + { SYSZ_INS_SRA, "sra" }, + { SYSZ_INS_SRAG, "srag" }, + { SYSZ_INS_SRAK, "srak" }, + { SYSZ_INS_SRK, "srk" }, + { SYSZ_INS_SRL, "srl" }, + { SYSZ_INS_SRLG, "srlg" }, + { SYSZ_INS_SRLK, "srlk" }, + { SYSZ_INS_SRST, "srst" }, + { SYSZ_INS_ST, "st" }, + { SYSZ_INS_STC, "stc" }, + { SYSZ_INS_STCH, "stch" }, + { SYSZ_INS_STCY, "stcy" }, + { SYSZ_INS_STD, "std" }, + { SYSZ_INS_STDY, "stdy" }, + { SYSZ_INS_STE, "ste" }, + { SYSZ_INS_STEY, "stey" }, + { SYSZ_INS_STFH, "stfh" }, + { SYSZ_INS_STG, "stg" }, + { SYSZ_INS_STGRL, "stgrl" }, + { SYSZ_INS_STH, "sth" }, + { SYSZ_INS_STHH, "sthh" }, + { SYSZ_INS_STHRL, "sthrl" }, + { SYSZ_INS_STHY, "sthy" }, + { SYSZ_INS_STMG, "stmg" }, + { SYSZ_INS_STRL, "strl" }, + { SYSZ_INS_STRV, "strv" }, + { SYSZ_INS_STRVG, "strvg" }, + { SYSZ_INS_STY, "sty" }, + { SYSZ_INS_SXBR, "sxbr" }, + { SYSZ_INS_SY, "sy" }, + { SYSZ_INS_TM, "tm" }, + { SYSZ_INS_TMHH, "tmhh" }, + { SYSZ_INS_TMHL, "tmhl" }, + { SYSZ_INS_TMLH, "tmlh" }, + { SYSZ_INS_TMLL, "tmll" }, + { SYSZ_INS_TMY, "tmy" }, + { SYSZ_INS_X, "x" }, + { SYSZ_INS_XC, "xc" }, + { SYSZ_INS_XG, "xg" }, + { SYSZ_INS_XGR, "xgr" }, + { SYSZ_INS_XGRK, "xgrk" }, + { SYSZ_INS_XI, "xi" }, + { SYSZ_INS_XIHF, "xihf" }, + { SYSZ_INS_XILF, "xilf" }, + { SYSZ_INS_XIY, "xiy" }, + { SYSZ_INS_XR, "xr" }, + { SYSZ_INS_XRK, "xrk" }, + { SYSZ_INS_XY, "xy" }, + { SYSZ_INS_AD, "ad" }, + { SYSZ_INS_ADR, "adr" }, + { SYSZ_INS_ADTR, "adtr" }, + { SYSZ_INS_ADTRA, "adtra" }, + { SYSZ_INS_AE, "ae" }, + { SYSZ_INS_AER, "aer" }, + { SYSZ_INS_AGH, "agh" }, + { SYSZ_INS_AHHHR, "ahhhr" }, + { SYSZ_INS_AHHLR, "ahhlr" }, + { SYSZ_INS_ALGSI, "algsi" }, + { SYSZ_INS_ALHHHR, "alhhhr" }, + { SYSZ_INS_ALHHLR, "alhhlr" }, + { SYSZ_INS_ALSI, "alsi" }, + { SYSZ_INS_ALSIH, "alsih" }, + { SYSZ_INS_ALSIHN, "alsihn" }, + { SYSZ_INS_AP, "ap" }, + { SYSZ_INS_AU, "au" }, + { SYSZ_INS_AUR, "aur" }, + { SYSZ_INS_AW, "aw" }, + { SYSZ_INS_AWR, "awr" }, + { SYSZ_INS_AXR, "axr" }, + { SYSZ_INS_AXTR, "axtr" }, + { SYSZ_INS_AXTRA, "axtra" }, + { SYSZ_INS_B, "b" }, + { SYSZ_INS_BAKR, "bakr" }, + { SYSZ_INS_BAL, "bal" }, + { SYSZ_INS_BALR, "balr" }, + { SYSZ_INS_BAS, "bas" }, + { SYSZ_INS_BASSM, "bassm" }, + { SYSZ_INS_BC, "bc" }, + { SYSZ_INS_BCT, "bct" }, + { SYSZ_INS_BCTG, "bctg" }, + { SYSZ_INS_BCTGR, "bctgr" }, + { SYSZ_INS_BCTR, "bctr" }, + { SYSZ_INS_BE, "be" }, + { SYSZ_INS_BH, "bh" }, + { SYSZ_INS_BHE, "bhe" }, + { SYSZ_INS_BI, "bi" }, + { SYSZ_INS_BIC, "bic" }, + { SYSZ_INS_BIE, "bie" }, + { SYSZ_INS_BIH, "bih" }, + { SYSZ_INS_BIHE, "bihe" }, + { SYSZ_INS_BIL, "bil" }, + { SYSZ_INS_BILE, "bile" }, + { SYSZ_INS_BILH, "bilh" }, + { SYSZ_INS_BIM, "bim" }, + { SYSZ_INS_BINE, "bine" }, + { SYSZ_INS_BINH, "binh" }, + { SYSZ_INS_BINHE, "binhe" }, + { SYSZ_INS_BINL, "binl" }, + { SYSZ_INS_BINLE, "binle" }, + { SYSZ_INS_BINLH, "binlh" }, + { SYSZ_INS_BINM, "binm" }, + { SYSZ_INS_BINO, "bino" }, + { SYSZ_INS_BINP, "binp" }, + { SYSZ_INS_BINZ, "binz" }, + { SYSZ_INS_BIO, "bio" }, + { SYSZ_INS_BIP, "bip" }, + { SYSZ_INS_BIZ, "biz" }, + { SYSZ_INS_BL, "bl" }, + { SYSZ_INS_BLE, "ble" }, + { SYSZ_INS_BLH, "blh" }, + { SYSZ_INS_BM, "bm" }, + { SYSZ_INS_BMR, "bmr" }, + { SYSZ_INS_BNE, "bne" }, + { SYSZ_INS_BNH, "bnh" }, + { SYSZ_INS_BNHE, "bnhe" }, + { SYSZ_INS_BNL, "bnl" }, + { SYSZ_INS_BNLE, "bnle" }, + { SYSZ_INS_BNLH, "bnlh" }, + { SYSZ_INS_BNM, "bnm" }, + { SYSZ_INS_BNMR, "bnmr" }, + { SYSZ_INS_BNO, "bno" }, + { SYSZ_INS_BNP, "bnp" }, + { SYSZ_INS_BNPR, "bnpr" }, + { SYSZ_INS_BNZ, "bnz" }, + { SYSZ_INS_BNZR, "bnzr" }, + { SYSZ_INS_BO, "bo" }, + { SYSZ_INS_BP, "bp" }, + { SYSZ_INS_BPP, "bpp" }, + { SYSZ_INS_BPR, "bpr" }, + { SYSZ_INS_BPRP, "bprp" }, + { SYSZ_INS_BRCTH, "brcth" }, + { SYSZ_INS_BRXH, "brxh" }, + { SYSZ_INS_BRXHG, "brxhg" }, + { SYSZ_INS_BRXLE, "brxle" }, + { SYSZ_INS_BRXLG, "brxlg" }, + { SYSZ_INS_BSA, "bsa" }, + { SYSZ_INS_BSG, "bsg" }, + { SYSZ_INS_BSM, "bsm" }, + { SYSZ_INS_BXH, "bxh" }, + { SYSZ_INS_BXHG, "bxhg" }, + { SYSZ_INS_BXLE, "bxle" }, + { SYSZ_INS_BXLEG, "bxleg" }, + { SYSZ_INS_BZ, "bz" }, + { SYSZ_INS_BZR, "bzr" }, + { SYSZ_INS_CD, "cd" }, + { SYSZ_INS_CDFBRA, "cdfbra" }, + { SYSZ_INS_CDFR, "cdfr" }, + { SYSZ_INS_CDFTR, "cdftr" }, + { SYSZ_INS_CDGBRA, "cdgbra" }, + { SYSZ_INS_CDGR, "cdgr" }, + { SYSZ_INS_CDGTR, "cdgtr" }, + { SYSZ_INS_CDGTRA, "cdgtra" }, + { SYSZ_INS_CDLFTR, "cdlftr" }, + { SYSZ_INS_CDLGTR, "cdlgtr" }, + { SYSZ_INS_CDPT, "cdpt" }, + { SYSZ_INS_CDR, "cdr" }, + { SYSZ_INS_CDS, "cds" }, + { SYSZ_INS_CDSG, "cdsg" }, + { SYSZ_INS_CDSTR, "cdstr" }, + { SYSZ_INS_CDSY, "cdsy" }, + { SYSZ_INS_CDTR, "cdtr" }, + { SYSZ_INS_CDUTR, "cdutr" }, + { SYSZ_INS_CDZT, "cdzt" }, + { SYSZ_INS_CE, "ce" }, + { SYSZ_INS_CEDTR, "cedtr" }, + { SYSZ_INS_CEFBRA, "cefbra" }, + { SYSZ_INS_CEFR, "cefr" }, + { SYSZ_INS_CEGBRA, "cegbra" }, + { SYSZ_INS_CEGR, "cegr" }, + { SYSZ_INS_CER, "cer" }, + { SYSZ_INS_CEXTR, "cextr" }, + { SYSZ_INS_CFC, "cfc" }, + { SYSZ_INS_CFDBRA, "cfdbra" }, + { SYSZ_INS_CFDR, "cfdr" }, + { SYSZ_INS_CFDTR, "cfdtr" }, + { SYSZ_INS_CFEBRA, "cfebra" }, + { SYSZ_INS_CFER, "cfer" }, + { SYSZ_INS_CFXBRA, "cfxbra" }, + { SYSZ_INS_CFXR, "cfxr" }, + { SYSZ_INS_CFXTR, "cfxtr" }, + { SYSZ_INS_CGDBRA, "cgdbra" }, + { SYSZ_INS_CGDR, "cgdr" }, + { SYSZ_INS_CGDTR, "cgdtr" }, + { SYSZ_INS_CGDTRA, "cgdtra" }, + { SYSZ_INS_CGEBRA, "cgebra" }, + { SYSZ_INS_CGER, "cger" }, + { SYSZ_INS_CGIB, "cgib" }, + { SYSZ_INS_CGIBE, "cgibe" }, + { SYSZ_INS_CGIBH, "cgibh" }, + { SYSZ_INS_CGIBHE, "cgibhe" }, + { SYSZ_INS_CGIBL, "cgibl" }, + { SYSZ_INS_CGIBLE, "cgible" }, + { SYSZ_INS_CGIBLH, "cgiblh" }, + { SYSZ_INS_CGIBNE, "cgibne" }, + { SYSZ_INS_CGIBNH, "cgibnh" }, + { SYSZ_INS_CGIBNHE, "cgibnhe" }, + { SYSZ_INS_CGIBNL, "cgibnl" }, + { SYSZ_INS_CGIBNLE, "cgibnle" }, + { SYSZ_INS_CGIBNLH, "cgibnlh" }, + { SYSZ_INS_CGIT, "cgit" }, + { SYSZ_INS_CGITE, "cgite" }, + { SYSZ_INS_CGITH, "cgith" }, + { SYSZ_INS_CGITHE, "cgithe" }, + { SYSZ_INS_CGITL, "cgitl" }, + { SYSZ_INS_CGITLE, "cgitle" }, + { SYSZ_INS_CGITLH, "cgitlh" }, + { SYSZ_INS_CGITNE, "cgitne" }, + { SYSZ_INS_CGITNH, "cgitnh" }, + { SYSZ_INS_CGITNHE, "cgitnhe" }, + { SYSZ_INS_CGITNL, "cgitnl" }, + { SYSZ_INS_CGITNLE, "cgitnle" }, + { SYSZ_INS_CGITNLH, "cgitnlh" }, + { SYSZ_INS_CGRB, "cgrb" }, + { SYSZ_INS_CGRBE, "cgrbe" }, + { SYSZ_INS_CGRBH, "cgrbh" }, + { SYSZ_INS_CGRBHE, "cgrbhe" }, + { SYSZ_INS_CGRBL, "cgrbl" }, + { SYSZ_INS_CGRBLE, "cgrble" }, + { SYSZ_INS_CGRBLH, "cgrblh" }, + { SYSZ_INS_CGRBNE, "cgrbne" }, + { SYSZ_INS_CGRBNH, "cgrbnh" }, + { SYSZ_INS_CGRBNHE, "cgrbnhe" }, + { SYSZ_INS_CGRBNL, "cgrbnl" }, + { SYSZ_INS_CGRBNLE, "cgrbnle" }, + { SYSZ_INS_CGRBNLH, "cgrbnlh" }, + { SYSZ_INS_CGRT, "cgrt" }, + { SYSZ_INS_CGRTE, "cgrte" }, + { SYSZ_INS_CGRTH, "cgrth" }, + { SYSZ_INS_CGRTHE, "cgrthe" }, + { SYSZ_INS_CGRTL, "cgrtl" }, + { SYSZ_INS_CGRTLE, "cgrtle" }, + { SYSZ_INS_CGRTLH, "cgrtlh" }, + { SYSZ_INS_CGRTNE, "cgrtne" }, + { SYSZ_INS_CGRTNH, "cgrtnh" }, + { SYSZ_INS_CGRTNHE, "cgrtnhe" }, + { SYSZ_INS_CGRTNL, "cgrtnl" }, + { SYSZ_INS_CGRTNLE, "cgrtnle" }, + { SYSZ_INS_CGRTNLH, "cgrtnlh" }, + { SYSZ_INS_CGXBRA, "cgxbra" }, + { SYSZ_INS_CGXR, "cgxr" }, + { SYSZ_INS_CGXTR, "cgxtr" }, + { SYSZ_INS_CGXTRA, "cgxtra" }, + { SYSZ_INS_CHHR, "chhr" }, + { SYSZ_INS_CHLR, "chlr" }, + { SYSZ_INS_CIB, "cib" }, + { SYSZ_INS_CIBE, "cibe" }, + { SYSZ_INS_CIBH, "cibh" }, + { SYSZ_INS_CIBHE, "cibhe" }, + { SYSZ_INS_CIBL, "cibl" }, + { SYSZ_INS_CIBLE, "cible" }, + { SYSZ_INS_CIBLH, "ciblh" }, + { SYSZ_INS_CIBNE, "cibne" }, + { SYSZ_INS_CIBNH, "cibnh" }, + { SYSZ_INS_CIBNHE, "cibnhe" }, + { SYSZ_INS_CIBNL, "cibnl" }, + { SYSZ_INS_CIBNLE, "cibnle" }, + { SYSZ_INS_CIBNLH, "cibnlh" }, + { SYSZ_INS_CIT, "cit" }, + { SYSZ_INS_CITE, "cite" }, + { SYSZ_INS_CITH, "cith" }, + { SYSZ_INS_CITHE, "cithe" }, + { SYSZ_INS_CITL, "citl" }, + { SYSZ_INS_CITLE, "citle" }, + { SYSZ_INS_CITLH, "citlh" }, + { SYSZ_INS_CITNE, "citne" }, + { SYSZ_INS_CITNH, "citnh" }, + { SYSZ_INS_CITNHE, "citnhe" }, + { SYSZ_INS_CITNL, "citnl" }, + { SYSZ_INS_CITNLE, "citnle" }, + { SYSZ_INS_CITNLH, "citnlh" }, + { SYSZ_INS_CKSM, "cksm" }, + { SYSZ_INS_CLCL, "clcl" }, + { SYSZ_INS_CLCLE, "clcle" }, + { SYSZ_INS_CLCLU, "clclu" }, + { SYSZ_INS_CLFDTR, "clfdtr" }, + { SYSZ_INS_CLFIT, "clfit" }, + { SYSZ_INS_CLFITE, "clfite" }, + { SYSZ_INS_CLFITH, "clfith" }, + { SYSZ_INS_CLFITHE, "clfithe" }, + { SYSZ_INS_CLFITL, "clfitl" }, + { SYSZ_INS_CLFITLE, "clfitle" }, + { SYSZ_INS_CLFITLH, "clfitlh" }, + { SYSZ_INS_CLFITNE, "clfitne" }, + { SYSZ_INS_CLFITNH, "clfitnh" }, + { SYSZ_INS_CLFITNHE, "clfitnhe" }, + { SYSZ_INS_CLFITNL, "clfitnl" }, + { SYSZ_INS_CLFITNLE, "clfitnle" }, + { SYSZ_INS_CLFITNLH, "clfitnlh" }, + { SYSZ_INS_CLFXTR, "clfxtr" }, + { SYSZ_INS_CLGDTR, "clgdtr" }, + { SYSZ_INS_CLGIB, "clgib" }, + { SYSZ_INS_CLGIBE, "clgibe" }, + { SYSZ_INS_CLGIBH, "clgibh" }, + { SYSZ_INS_CLGIBHE, "clgibhe" }, + { SYSZ_INS_CLGIBL, "clgibl" }, + { SYSZ_INS_CLGIBLE, "clgible" }, + { SYSZ_INS_CLGIBLH, "clgiblh" }, + { SYSZ_INS_CLGIBNE, "clgibne" }, + { SYSZ_INS_CLGIBNH, "clgibnh" }, + { SYSZ_INS_CLGIBNHE, "clgibnhe" }, + { SYSZ_INS_CLGIBNL, "clgibnl" }, + { SYSZ_INS_CLGIBNLE, "clgibnle" }, + { SYSZ_INS_CLGIBNLH, "clgibnlh" }, + { SYSZ_INS_CLGIT, "clgit" }, + { SYSZ_INS_CLGITE, "clgite" }, + { SYSZ_INS_CLGITH, "clgith" }, + { SYSZ_INS_CLGITHE, "clgithe" }, + { SYSZ_INS_CLGITL, "clgitl" }, + { SYSZ_INS_CLGITLE, "clgitle" }, + { SYSZ_INS_CLGITLH, "clgitlh" }, + { SYSZ_INS_CLGITNE, "clgitne" }, + { SYSZ_INS_CLGITNH, "clgitnh" }, + { SYSZ_INS_CLGITNHE, "clgitnhe" }, + { SYSZ_INS_CLGITNL, "clgitnl" }, + { SYSZ_INS_CLGITNLE, "clgitnle" }, + { SYSZ_INS_CLGITNLH, "clgitnlh" }, + { SYSZ_INS_CLGRB, "clgrb" }, + { SYSZ_INS_CLGRBE, "clgrbe" }, + { SYSZ_INS_CLGRBH, "clgrbh" }, + { SYSZ_INS_CLGRBHE, "clgrbhe" }, + { SYSZ_INS_CLGRBL, "clgrbl" }, + { SYSZ_INS_CLGRBLE, "clgrble" }, + { SYSZ_INS_CLGRBLH, "clgrblh" }, + { SYSZ_INS_CLGRBNE, "clgrbne" }, + { SYSZ_INS_CLGRBNH, "clgrbnh" }, + { SYSZ_INS_CLGRBNHE, "clgrbnhe" }, + { SYSZ_INS_CLGRBNL, "clgrbnl" }, + { SYSZ_INS_CLGRBNLE, "clgrbnle" }, + { SYSZ_INS_CLGRBNLH, "clgrbnlh" }, + { SYSZ_INS_CLGRT, "clgrt" }, + { SYSZ_INS_CLGRTE, "clgrte" }, + { SYSZ_INS_CLGRTH, "clgrth" }, + { SYSZ_INS_CLGRTHE, "clgrthe" }, + { SYSZ_INS_CLGRTL, "clgrtl" }, + { SYSZ_INS_CLGRTLE, "clgrtle" }, + { SYSZ_INS_CLGRTLH, "clgrtlh" }, + { SYSZ_INS_CLGRTNE, "clgrtne" }, + { SYSZ_INS_CLGRTNH, "clgrtnh" }, + { SYSZ_INS_CLGRTNHE, "clgrtnhe" }, + { SYSZ_INS_CLGRTNL, "clgrtnl" }, + { SYSZ_INS_CLGRTNLE, "clgrtnle" }, + { SYSZ_INS_CLGRTNLH, "clgrtnlh" }, + { SYSZ_INS_CLGT, "clgt" }, + { SYSZ_INS_CLGTE, "clgte" }, + { SYSZ_INS_CLGTH, "clgth" }, + { SYSZ_INS_CLGTHE, "clgthe" }, + { SYSZ_INS_CLGTL, "clgtl" }, + { SYSZ_INS_CLGTLE, "clgtle" }, + { SYSZ_INS_CLGTLH, "clgtlh" }, + { SYSZ_INS_CLGTNE, "clgtne" }, + { SYSZ_INS_CLGTNH, "clgtnh" }, + { SYSZ_INS_CLGTNHE, "clgtnhe" }, + { SYSZ_INS_CLGTNL, "clgtnl" }, + { SYSZ_INS_CLGTNLE, "clgtnle" }, + { SYSZ_INS_CLGTNLH, "clgtnlh" }, + { SYSZ_INS_CLGXTR, "clgxtr" }, + { SYSZ_INS_CLHHR, "clhhr" }, + { SYSZ_INS_CLHLR, "clhlr" }, + { SYSZ_INS_CLIB, "clib" }, + { SYSZ_INS_CLIBE, "clibe" }, + { SYSZ_INS_CLIBH, "clibh" }, + { SYSZ_INS_CLIBHE, "clibhe" }, + { SYSZ_INS_CLIBL, "clibl" }, + { SYSZ_INS_CLIBLE, "clible" }, + { SYSZ_INS_CLIBLH, "cliblh" }, + { SYSZ_INS_CLIBNE, "clibne" }, + { SYSZ_INS_CLIBNH, "clibnh" }, + { SYSZ_INS_CLIBNHE, "clibnhe" }, + { SYSZ_INS_CLIBNL, "clibnl" }, + { SYSZ_INS_CLIBNLE, "clibnle" }, + { SYSZ_INS_CLIBNLH, "clibnlh" }, + { SYSZ_INS_CLM, "clm" }, + { SYSZ_INS_CLMH, "clmh" }, + { SYSZ_INS_CLMY, "clmy" }, + { SYSZ_INS_CLRB, "clrb" }, + { SYSZ_INS_CLRBE, "clrbe" }, + { SYSZ_INS_CLRBH, "clrbh" }, + { SYSZ_INS_CLRBHE, "clrbhe" }, + { SYSZ_INS_CLRBL, "clrbl" }, + { SYSZ_INS_CLRBLE, "clrble" }, + { SYSZ_INS_CLRBLH, "clrblh" }, + { SYSZ_INS_CLRBNE, "clrbne" }, + { SYSZ_INS_CLRBNH, "clrbnh" }, + { SYSZ_INS_CLRBNHE, "clrbnhe" }, + { SYSZ_INS_CLRBNL, "clrbnl" }, + { SYSZ_INS_CLRBNLE, "clrbnle" }, + { SYSZ_INS_CLRBNLH, "clrbnlh" }, + { SYSZ_INS_CLRT, "clrt" }, + { SYSZ_INS_CLRTE, "clrte" }, + { SYSZ_INS_CLRTH, "clrth" }, + { SYSZ_INS_CLRTHE, "clrthe" }, + { SYSZ_INS_CLRTL, "clrtl" }, + { SYSZ_INS_CLRTLE, "clrtle" }, + { SYSZ_INS_CLRTLH, "clrtlh" }, + { SYSZ_INS_CLRTNE, "clrtne" }, + { SYSZ_INS_CLRTNH, "clrtnh" }, + { SYSZ_INS_CLRTNHE, "clrtnhe" }, + { SYSZ_INS_CLRTNL, "clrtnl" }, + { SYSZ_INS_CLRTNLE, "clrtnle" }, + { SYSZ_INS_CLRTNLH, "clrtnlh" }, + { SYSZ_INS_CLT, "clt" }, + { SYSZ_INS_CLTE, "clte" }, + { SYSZ_INS_CLTH, "clth" }, + { SYSZ_INS_CLTHE, "clthe" }, + { SYSZ_INS_CLTL, "cltl" }, + { SYSZ_INS_CLTLE, "cltle" }, + { SYSZ_INS_CLTLH, "cltlh" }, + { SYSZ_INS_CLTNE, "cltne" }, + { SYSZ_INS_CLTNH, "cltnh" }, + { SYSZ_INS_CLTNHE, "cltnhe" }, + { SYSZ_INS_CLTNL, "cltnl" }, + { SYSZ_INS_CLTNLE, "cltnle" }, + { SYSZ_INS_CLTNLH, "cltnlh" }, + { SYSZ_INS_CMPSC, "cmpsc" }, + { SYSZ_INS_CP, "cp" }, + { SYSZ_INS_CPDT, "cpdt" }, + { SYSZ_INS_CPXT, "cpxt" }, + { SYSZ_INS_CPYA, "cpya" }, + { SYSZ_INS_CRB, "crb" }, + { SYSZ_INS_CRBE, "crbe" }, + { SYSZ_INS_CRBH, "crbh" }, + { SYSZ_INS_CRBHE, "crbhe" }, + { SYSZ_INS_CRBL, "crbl" }, + { SYSZ_INS_CRBLE, "crble" }, + { SYSZ_INS_CRBLH, "crblh" }, + { SYSZ_INS_CRBNE, "crbne" }, + { SYSZ_INS_CRBNH, "crbnh" }, + { SYSZ_INS_CRBNHE, "crbnhe" }, + { SYSZ_INS_CRBNL, "crbnl" }, + { SYSZ_INS_CRBNLE, "crbnle" }, + { SYSZ_INS_CRBNLH, "crbnlh" }, + { SYSZ_INS_CRDTE, "crdte" }, + { SYSZ_INS_CRT, "crt" }, + { SYSZ_INS_CRTE, "crte" }, + { SYSZ_INS_CRTH, "crth" }, + { SYSZ_INS_CRTHE, "crthe" }, + { SYSZ_INS_CRTL, "crtl" }, + { SYSZ_INS_CRTLE, "crtle" }, + { SYSZ_INS_CRTLH, "crtlh" }, + { SYSZ_INS_CRTNE, "crtne" }, + { SYSZ_INS_CRTNH, "crtnh" }, + { SYSZ_INS_CRTNHE, "crtnhe" }, + { SYSZ_INS_CRTNL, "crtnl" }, + { SYSZ_INS_CRTNLE, "crtnle" }, + { SYSZ_INS_CRTNLH, "crtnlh" }, + { SYSZ_INS_CSCH, "csch" }, + { SYSZ_INS_CSDTR, "csdtr" }, + { SYSZ_INS_CSP, "csp" }, + { SYSZ_INS_CSPG, "cspg" }, + { SYSZ_INS_CSST, "csst" }, + { SYSZ_INS_CSXTR, "csxtr" }, + { SYSZ_INS_CU12, "cu12" }, + { SYSZ_INS_CU14, "cu14" }, + { SYSZ_INS_CU21, "cu21" }, + { SYSZ_INS_CU24, "cu24" }, + { SYSZ_INS_CU41, "cu41" }, + { SYSZ_INS_CU42, "cu42" }, + { SYSZ_INS_CUDTR, "cudtr" }, + { SYSZ_INS_CUSE, "cuse" }, + { SYSZ_INS_CUTFU, "cutfu" }, + { SYSZ_INS_CUUTF, "cuutf" }, + { SYSZ_INS_CUXTR, "cuxtr" }, + { SYSZ_INS_CVB, "cvb" }, + { SYSZ_INS_CVBG, "cvbg" }, + { SYSZ_INS_CVBY, "cvby" }, + { SYSZ_INS_CVD, "cvd" }, + { SYSZ_INS_CVDG, "cvdg" }, + { SYSZ_INS_CVDY, "cvdy" }, + { SYSZ_INS_CXFBRA, "cxfbra" }, + { SYSZ_INS_CXFR, "cxfr" }, + { SYSZ_INS_CXFTR, "cxftr" }, + { SYSZ_INS_CXGBRA, "cxgbra" }, + { SYSZ_INS_CXGR, "cxgr" }, + { SYSZ_INS_CXGTR, "cxgtr" }, + { SYSZ_INS_CXGTRA, "cxgtra" }, + { SYSZ_INS_CXLFTR, "cxlftr" }, + { SYSZ_INS_CXLGTR, "cxlgtr" }, + { SYSZ_INS_CXPT, "cxpt" }, + { SYSZ_INS_CXR, "cxr" }, + { SYSZ_INS_CXSTR, "cxstr" }, + { SYSZ_INS_CXTR, "cxtr" }, + { SYSZ_INS_CXUTR, "cxutr" }, + { SYSZ_INS_CXZT, "cxzt" }, + { SYSZ_INS_CZDT, "czdt" }, + { SYSZ_INS_CZXT, "czxt" }, + { SYSZ_INS_D, "d" }, + { SYSZ_INS_DD, "dd" }, + { SYSZ_INS_DDR, "ddr" }, + { SYSZ_INS_DDTR, "ddtr" }, + { SYSZ_INS_DDTRA, "ddtra" }, + { SYSZ_INS_DE, "de" }, + { SYSZ_INS_DER, "der" }, + { SYSZ_INS_DIAG, "diag" }, + { SYSZ_INS_DIDBR, "didbr" }, + { SYSZ_INS_DIEBR, "diebr" }, + { SYSZ_INS_DP, "dp" }, + { SYSZ_INS_DR, "dr" }, + { SYSZ_INS_DXR, "dxr" }, + { SYSZ_INS_DXTR, "dxtr" }, + { SYSZ_INS_DXTRA, "dxtra" }, + { SYSZ_INS_ECAG, "ecag" }, + { SYSZ_INS_ECCTR, "ecctr" }, + { SYSZ_INS_ECPGA, "ecpga" }, + { SYSZ_INS_ECTG, "ectg" }, + { SYSZ_INS_ED, "ed" }, + { SYSZ_INS_EDMK, "edmk" }, + { SYSZ_INS_EEDTR, "eedtr" }, + { SYSZ_INS_EEXTR, "eextr" }, + { SYSZ_INS_EFPC, "efpc" }, + { SYSZ_INS_EPAIR, "epair" }, + { SYSZ_INS_EPAR, "epar" }, + { SYSZ_INS_EPCTR, "epctr" }, + { SYSZ_INS_EPSW, "epsw" }, + { SYSZ_INS_EREG, "ereg" }, + { SYSZ_INS_EREGG, "eregg" }, + { SYSZ_INS_ESAIR, "esair" }, + { SYSZ_INS_ESAR, "esar" }, + { SYSZ_INS_ESDTR, "esdtr" }, + { SYSZ_INS_ESEA, "esea" }, + { SYSZ_INS_ESTA, "esta" }, + { SYSZ_INS_ESXTR, "esxtr" }, + { SYSZ_INS_ETND, "etnd" }, + { SYSZ_INS_EX, "ex" }, + { SYSZ_INS_EXRL, "exrl" }, + { SYSZ_INS_FIDR, "fidr" }, + { SYSZ_INS_FIDTR, "fidtr" }, + { SYSZ_INS_FIER, "fier" }, + { SYSZ_INS_FIXR, "fixr" }, + { SYSZ_INS_FIXTR, "fixtr" }, + { SYSZ_INS_HDR, "hdr" }, + { SYSZ_INS_HER, "her" }, + { SYSZ_INS_HSCH, "hsch" }, + { SYSZ_INS_IAC, "iac" }, + { SYSZ_INS_ICM, "icm" }, + { SYSZ_INS_ICMH, "icmh" }, + { SYSZ_INS_ICMY, "icmy" }, + { SYSZ_INS_IDTE, "idte" }, + { SYSZ_INS_IEDTR, "iedtr" }, + { SYSZ_INS_IEXTR, "iextr" }, + { SYSZ_INS_IPK, "ipk" }, + { SYSZ_INS_IPTE, "ipte" }, + { SYSZ_INS_IRBM, "irbm" }, + { SYSZ_INS_ISKE, "iske" }, + { SYSZ_INS_IVSK, "ivsk" }, + { SYSZ_INS_JGM, "jgm" }, + { SYSZ_INS_JGNM, "jgnm" }, + { SYSZ_INS_JGNP, "jgnp" }, + { SYSZ_INS_JGNZ, "jgnz" }, + { SYSZ_INS_JGP, "jgp" }, + { SYSZ_INS_JGZ, "jgz" }, + { SYSZ_INS_JM, "jm" }, + { SYSZ_INS_JNM, "jnm" }, + { SYSZ_INS_JNP, "jnp" }, + { SYSZ_INS_JNZ, "jnz" }, + { SYSZ_INS_JP, "jp" }, + { SYSZ_INS_JZ, "jz" }, + { SYSZ_INS_KDB, "kdb" }, + { SYSZ_INS_KDBR, "kdbr" }, + { SYSZ_INS_KDTR, "kdtr" }, + { SYSZ_INS_KEB, "keb" }, + { SYSZ_INS_KEBR, "kebr" }, + { SYSZ_INS_KIMD, "kimd" }, + { SYSZ_INS_KLMD, "klmd" }, + { SYSZ_INS_KM, "km" }, + { SYSZ_INS_KMA, "kma" }, + { SYSZ_INS_KMAC, "kmac" }, + { SYSZ_INS_KMC, "kmc" }, + { SYSZ_INS_KMCTR, "kmctr" }, + { SYSZ_INS_KMF, "kmf" }, + { SYSZ_INS_KMO, "kmo" }, + { SYSZ_INS_KXBR, "kxbr" }, + { SYSZ_INS_KXTR, "kxtr" }, + { SYSZ_INS_LAE, "lae" }, + { SYSZ_INS_LAEY, "laey" }, + { SYSZ_INS_LAM, "lam" }, + { SYSZ_INS_LAMY, "lamy" }, + { SYSZ_INS_LASP, "lasp" }, + { SYSZ_INS_LAT, "lat" }, + { SYSZ_INS_LCBB, "lcbb" }, + { SYSZ_INS_LCCTL, "lcctl" }, + { SYSZ_INS_LCDFR, "lcdfr" }, + { SYSZ_INS_LCDR, "lcdr" }, + { SYSZ_INS_LCER, "lcer" }, + { SYSZ_INS_LCTL, "lctl" }, + { SYSZ_INS_LCTLG, "lctlg" }, + { SYSZ_INS_LCXR, "lcxr" }, + { SYSZ_INS_LDE, "lde" }, + { SYSZ_INS_LDER, "lder" }, + { SYSZ_INS_LDETR, "ldetr" }, + { SYSZ_INS_LDXR, "ldxr" }, + { SYSZ_INS_LDXTR, "ldxtr" }, + { SYSZ_INS_LEDR, "ledr" }, + { SYSZ_INS_LEDTR, "ledtr" }, + { SYSZ_INS_LEXR, "lexr" }, + { SYSZ_INS_LFAS, "lfas" }, + { SYSZ_INS_LFHAT, "lfhat" }, + { SYSZ_INS_LFPC, "lfpc" }, + { SYSZ_INS_LGAT, "lgat" }, + { SYSZ_INS_LGG, "lgg" }, + { SYSZ_INS_LGSC, "lgsc" }, + { SYSZ_INS_LLGFAT, "llgfat" }, + { SYSZ_INS_LLGFSG, "llgfsg" }, + { SYSZ_INS_LLGT, "llgt" }, + { SYSZ_INS_LLGTAT, "llgtat" }, + { SYSZ_INS_LLGTR, "llgtr" }, + { SYSZ_INS_LLZRGF, "llzrgf" }, + { SYSZ_INS_LM, "lm" }, + { SYSZ_INS_LMD, "lmd" }, + { SYSZ_INS_LMH, "lmh" }, + { SYSZ_INS_LMY, "lmy" }, + { SYSZ_INS_LNDFR, "lndfr" }, + { SYSZ_INS_LNDR, "lndr" }, + { SYSZ_INS_LNER, "lner" }, + { SYSZ_INS_LNXR, "lnxr" }, + { SYSZ_INS_LOCFH, "locfh" }, + { SYSZ_INS_LOCFHE, "locfhe" }, + { SYSZ_INS_LOCFHH, "locfhh" }, + { SYSZ_INS_LOCFHHE, "locfhhe" }, + { SYSZ_INS_LOCFHL, "locfhl" }, + { SYSZ_INS_LOCFHLE, "locfhle" }, + { SYSZ_INS_LOCFHLH, "locfhlh" }, + { SYSZ_INS_LOCFHM, "locfhm" }, + { SYSZ_INS_LOCFHNE, "locfhne" }, + { SYSZ_INS_LOCFHNH, "locfhnh" }, + { SYSZ_INS_LOCFHNHE, "locfhnhe" }, + { SYSZ_INS_LOCFHNL, "locfhnl" }, + { SYSZ_INS_LOCFHNLE, "locfhnle" }, + { SYSZ_INS_LOCFHNLH, "locfhnlh" }, + { SYSZ_INS_LOCFHNM, "locfhnm" }, + { SYSZ_INS_LOCFHNO, "locfhno" }, + { SYSZ_INS_LOCFHNP, "locfhnp" }, + { SYSZ_INS_LOCFHNZ, "locfhnz" }, + { SYSZ_INS_LOCFHO, "locfho" }, + { SYSZ_INS_LOCFHP, "locfhp" }, + { SYSZ_INS_LOCFHR, "locfhr" }, + { SYSZ_INS_LOCFHRE, "locfhre" }, + { SYSZ_INS_LOCFHRH, "locfhrh" }, + { SYSZ_INS_LOCFHRHE, "locfhrhe" }, + { SYSZ_INS_LOCFHRL, "locfhrl" }, + { SYSZ_INS_LOCFHRLE, "locfhrle" }, + { SYSZ_INS_LOCFHRLH, "locfhrlh" }, + { SYSZ_INS_LOCFHRM, "locfhrm" }, + { SYSZ_INS_LOCFHRNE, "locfhrne" }, + { SYSZ_INS_LOCFHRNH, "locfhrnh" }, + { SYSZ_INS_LOCFHRNHE, "locfhrnhe" }, + { SYSZ_INS_LOCFHRNL, "locfhrnl" }, + { SYSZ_INS_LOCFHRNLE, "locfhrnle" }, + { SYSZ_INS_LOCFHRNLH, "locfhrnlh" }, + { SYSZ_INS_LOCFHRNM, "locfhrnm" }, + { SYSZ_INS_LOCFHRNO, "locfhrno" }, + { SYSZ_INS_LOCFHRNP, "locfhrnp" }, + { SYSZ_INS_LOCFHRNZ, "locfhrnz" }, + { SYSZ_INS_LOCFHRO, "locfhro" }, + { SYSZ_INS_LOCFHRP, "locfhrp" }, + { SYSZ_INS_LOCFHRZ, "locfhrz" }, + { SYSZ_INS_LOCFHZ, "locfhz" }, + { SYSZ_INS_LOCGHI, "locghi" }, + { SYSZ_INS_LOCGHIE, "locghie" }, + { SYSZ_INS_LOCGHIH, "locghih" }, + { SYSZ_INS_LOCGHIHE, "locghihe" }, + { SYSZ_INS_LOCGHIL, "locghil" }, + { SYSZ_INS_LOCGHILE, "locghile" }, + { SYSZ_INS_LOCGHILH, "locghilh" }, + { SYSZ_INS_LOCGHIM, "locghim" }, + { SYSZ_INS_LOCGHINE, "locghine" }, + { SYSZ_INS_LOCGHINH, "locghinh" }, + { SYSZ_INS_LOCGHINHE, "locghinhe" }, + { SYSZ_INS_LOCGHINL, "locghinl" }, + { SYSZ_INS_LOCGHINLE, "locghinle" }, + { SYSZ_INS_LOCGHINLH, "locghinlh" }, + { SYSZ_INS_LOCGHINM, "locghinm" }, + { SYSZ_INS_LOCGHINO, "locghino" }, + { SYSZ_INS_LOCGHINP, "locghinp" }, + { SYSZ_INS_LOCGHINZ, "locghinz" }, + { SYSZ_INS_LOCGHIO, "locghio" }, + { SYSZ_INS_LOCGHIP, "locghip" }, + { SYSZ_INS_LOCGHIZ, "locghiz" }, + { SYSZ_INS_LOCGM, "locgm" }, + { SYSZ_INS_LOCGNM, "locgnm" }, + { SYSZ_INS_LOCGNP, "locgnp" }, + { SYSZ_INS_LOCGNZ, "locgnz" }, + { SYSZ_INS_LOCGP, "locgp" }, + { SYSZ_INS_LOCGRM, "locgrm" }, + { SYSZ_INS_LOCGRNM, "locgrnm" }, + { SYSZ_INS_LOCGRNP, "locgrnp" }, + { SYSZ_INS_LOCGRNZ, "locgrnz" }, + { SYSZ_INS_LOCGRP, "locgrp" }, + { SYSZ_INS_LOCGRZ, "locgrz" }, + { SYSZ_INS_LOCGZ, "locgz" }, + { SYSZ_INS_LOCHHI, "lochhi" }, + { SYSZ_INS_LOCHHIE, "lochhie" }, + { SYSZ_INS_LOCHHIH, "lochhih" }, + { SYSZ_INS_LOCHHIHE, "lochhihe" }, + { SYSZ_INS_LOCHHIL, "lochhil" }, + { SYSZ_INS_LOCHHILE, "lochhile" }, + { SYSZ_INS_LOCHHILH, "lochhilh" }, + { SYSZ_INS_LOCHHIM, "lochhim" }, + { SYSZ_INS_LOCHHINE, "lochhine" }, + { SYSZ_INS_LOCHHINH, "lochhinh" }, + { SYSZ_INS_LOCHHINHE, "lochhinhe" }, + { SYSZ_INS_LOCHHINL, "lochhinl" }, + { SYSZ_INS_LOCHHINLE, "lochhinle" }, + { SYSZ_INS_LOCHHINLH, "lochhinlh" }, + { SYSZ_INS_LOCHHINM, "lochhinm" }, + { SYSZ_INS_LOCHHINO, "lochhino" }, + { SYSZ_INS_LOCHHINP, "lochhinp" }, + { SYSZ_INS_LOCHHINZ, "lochhinz" }, + { SYSZ_INS_LOCHHIO, "lochhio" }, + { SYSZ_INS_LOCHHIP, "lochhip" }, + { SYSZ_INS_LOCHHIZ, "lochhiz" }, + { SYSZ_INS_LOCHI, "lochi" }, + { SYSZ_INS_LOCHIE, "lochie" }, + { SYSZ_INS_LOCHIH, "lochih" }, + { SYSZ_INS_LOCHIHE, "lochihe" }, + { SYSZ_INS_LOCHIL, "lochil" }, + { SYSZ_INS_LOCHILE, "lochile" }, + { SYSZ_INS_LOCHILH, "lochilh" }, + { SYSZ_INS_LOCHIM, "lochim" }, + { SYSZ_INS_LOCHINE, "lochine" }, + { SYSZ_INS_LOCHINH, "lochinh" }, + { SYSZ_INS_LOCHINHE, "lochinhe" }, + { SYSZ_INS_LOCHINL, "lochinl" }, + { SYSZ_INS_LOCHINLE, "lochinle" }, + { SYSZ_INS_LOCHINLH, "lochinlh" }, + { SYSZ_INS_LOCHINM, "lochinm" }, + { SYSZ_INS_LOCHINO, "lochino" }, + { SYSZ_INS_LOCHINP, "lochinp" }, + { SYSZ_INS_LOCHINZ, "lochinz" }, + { SYSZ_INS_LOCHIO, "lochio" }, + { SYSZ_INS_LOCHIP, "lochip" }, + { SYSZ_INS_LOCHIZ, "lochiz" }, + { SYSZ_INS_LOCM, "locm" }, + { SYSZ_INS_LOCNM, "locnm" }, + { SYSZ_INS_LOCNP, "locnp" }, + { SYSZ_INS_LOCNZ, "locnz" }, + { SYSZ_INS_LOCP, "locp" }, + { SYSZ_INS_LOCRM, "locrm" }, + { SYSZ_INS_LOCRNM, "locrnm" }, + { SYSZ_INS_LOCRNP, "locrnp" }, + { SYSZ_INS_LOCRNZ, "locrnz" }, + { SYSZ_INS_LOCRP, "locrp" }, + { SYSZ_INS_LOCRZ, "locrz" }, + { SYSZ_INS_LOCZ, "locz" }, + { SYSZ_INS_LPCTL, "lpctl" }, + { SYSZ_INS_LPD, "lpd" }, + { SYSZ_INS_LPDFR, "lpdfr" }, + { SYSZ_INS_LPDG, "lpdg" }, + { SYSZ_INS_LPDR, "lpdr" }, + { SYSZ_INS_LPER, "lper" }, + { SYSZ_INS_LPP, "lpp" }, + { SYSZ_INS_LPQ, "lpq" }, + { SYSZ_INS_LPSW, "lpsw" }, + { SYSZ_INS_LPSWE, "lpswe" }, + { SYSZ_INS_LPTEA, "lptea" }, + { SYSZ_INS_LPXR, "lpxr" }, + { SYSZ_INS_LRA, "lra" }, + { SYSZ_INS_LRAG, "lrag" }, + { SYSZ_INS_LRAY, "lray" }, + { SYSZ_INS_LRDR, "lrdr" }, + { SYSZ_INS_LRER, "lrer" }, + { SYSZ_INS_LRVH, "lrvh" }, + { SYSZ_INS_LSCTL, "lsctl" }, + { SYSZ_INS_LTDR, "ltdr" }, + { SYSZ_INS_LTDTR, "ltdtr" }, + { SYSZ_INS_LTER, "lter" }, + { SYSZ_INS_LTXR, "ltxr" }, + { SYSZ_INS_LTXTR, "ltxtr" }, + { SYSZ_INS_LURA, "lura" }, + { SYSZ_INS_LURAG, "lurag" }, + { SYSZ_INS_LXD, "lxd" }, + { SYSZ_INS_LXDR, "lxdr" }, + { SYSZ_INS_LXDTR, "lxdtr" }, + { SYSZ_INS_LXE, "lxe" }, + { SYSZ_INS_LXER, "lxer" }, + { SYSZ_INS_LZRF, "lzrf" }, + { SYSZ_INS_LZRG, "lzrg" }, + { SYSZ_INS_M, "m" }, + { SYSZ_INS_MAD, "mad" }, + { SYSZ_INS_MADR, "madr" }, + { SYSZ_INS_MAE, "mae" }, + { SYSZ_INS_MAER, "maer" }, + { SYSZ_INS_MAY, "may" }, + { SYSZ_INS_MAYH, "mayh" }, + { SYSZ_INS_MAYHR, "mayhr" }, + { SYSZ_INS_MAYL, "mayl" }, + { SYSZ_INS_MAYLR, "maylr" }, + { SYSZ_INS_MAYR, "mayr" }, + { SYSZ_INS_MC, "mc" }, + { SYSZ_INS_MD, "md" }, + { SYSZ_INS_MDE, "mde" }, + { SYSZ_INS_MDER, "mder" }, + { SYSZ_INS_MDR, "mdr" }, + { SYSZ_INS_MDTR, "mdtr" }, + { SYSZ_INS_MDTRA, "mdtra" }, + { SYSZ_INS_ME, "me" }, + { SYSZ_INS_MEE, "mee" }, + { SYSZ_INS_MEER, "meer" }, + { SYSZ_INS_MER, "mer" }, + { SYSZ_INS_MFY, "mfy" }, + { SYSZ_INS_MG, "mg" }, + { SYSZ_INS_MGH, "mgh" }, + { SYSZ_INS_MGRK, "mgrk" }, + { SYSZ_INS_ML, "ml" }, + { SYSZ_INS_MLR, "mlr" }, + { SYSZ_INS_MP, "mp" }, + { SYSZ_INS_MR, "mr" }, + { SYSZ_INS_MSC, "msc" }, + { SYSZ_INS_MSCH, "msch" }, + { SYSZ_INS_MSD, "msd" }, + { SYSZ_INS_MSDR, "msdr" }, + { SYSZ_INS_MSE, "mse" }, + { SYSZ_INS_MSER, "mser" }, + { SYSZ_INS_MSGC, "msgc" }, + { SYSZ_INS_MSGRKC, "msgrkc" }, + { SYSZ_INS_MSRKC, "msrkc" }, + { SYSZ_INS_MSTA, "msta" }, + { SYSZ_INS_MVCDK, "mvcdk" }, + { SYSZ_INS_MVCIN, "mvcin" }, + { SYSZ_INS_MVCK, "mvck" }, + { SYSZ_INS_MVCL, "mvcl" }, + { SYSZ_INS_MVCLE, "mvcle" }, + { SYSZ_INS_MVCLU, "mvclu" }, + { SYSZ_INS_MVCOS, "mvcos" }, + { SYSZ_INS_MVCP, "mvcp" }, + { SYSZ_INS_MVCS, "mvcs" }, + { SYSZ_INS_MVCSK, "mvcsk" }, + { SYSZ_INS_MVN, "mvn" }, + { SYSZ_INS_MVO, "mvo" }, + { SYSZ_INS_MVPG, "mvpg" }, + { SYSZ_INS_MVZ, "mvz" }, + { SYSZ_INS_MXD, "mxd" }, + { SYSZ_INS_MXDR, "mxdr" }, + { SYSZ_INS_MXR, "mxr" }, + { SYSZ_INS_MXTR, "mxtr" }, + { SYSZ_INS_MXTRA, "mxtra" }, + { SYSZ_INS_MY, "my" }, + { SYSZ_INS_MYH, "myh" }, + { SYSZ_INS_MYHR, "myhr" }, + { SYSZ_INS_MYL, "myl" }, + { SYSZ_INS_MYLR, "mylr" }, + { SYSZ_INS_MYR, "myr" }, + { SYSZ_INS_NIAI, "niai" }, + { SYSZ_INS_NTSTG, "ntstg" }, + { SYSZ_INS_PACK, "pack" }, + { SYSZ_INS_PALB, "palb" }, + { SYSZ_INS_PC, "pc" }, + { SYSZ_INS_PCC, "pcc" }, + { SYSZ_INS_PCKMO, "pckmo" }, + { SYSZ_INS_PFMF, "pfmf" }, + { SYSZ_INS_PFPO, "pfpo" }, + { SYSZ_INS_PGIN, "pgin" }, + { SYSZ_INS_PGOUT, "pgout" }, + { SYSZ_INS_PKA, "pka" }, + { SYSZ_INS_PKU, "pku" }, + { SYSZ_INS_PLO, "plo" }, + { SYSZ_INS_POPCNT, "popcnt" }, + { SYSZ_INS_PPA, "ppa" }, + { SYSZ_INS_PPNO, "ppno" }, + { SYSZ_INS_PR, "pr" }, + { SYSZ_INS_PRNO, "prno" }, + { SYSZ_INS_PT, "pt" }, + { SYSZ_INS_PTF, "ptf" }, + { SYSZ_INS_PTFF, "ptff" }, + { SYSZ_INS_PTI, "pti" }, + { SYSZ_INS_PTLB, "ptlb" }, + { SYSZ_INS_QADTR, "qadtr" }, + { SYSZ_INS_QAXTR, "qaxtr" }, + { SYSZ_INS_QCTRI, "qctri" }, + { SYSZ_INS_QSI, "qsi" }, + { SYSZ_INS_RCHP, "rchp" }, + { SYSZ_INS_RISBGN, "risbgn" }, + { SYSZ_INS_RP, "rp" }, + { SYSZ_INS_RRBE, "rrbe" }, + { SYSZ_INS_RRBM, "rrbm" }, + { SYSZ_INS_RRDTR, "rrdtr" }, + { SYSZ_INS_RRXTR, "rrxtr" }, + { SYSZ_INS_RSCH, "rsch" }, + { SYSZ_INS_SAC, "sac" }, + { SYSZ_INS_SACF, "sacf" }, + { SYSZ_INS_SAL, "sal" }, + { SYSZ_INS_SAM24, "sam24" }, + { SYSZ_INS_SAM31, "sam31" }, + { SYSZ_INS_SAM64, "sam64" }, + { SYSZ_INS_SAR, "sar" }, + { SYSZ_INS_SCCTR, "scctr" }, + { SYSZ_INS_SCHM, "schm" }, + { SYSZ_INS_SCK, "sck" }, + { SYSZ_INS_SCKC, "sckc" }, + { SYSZ_INS_SCKPF, "sckpf" }, + { SYSZ_INS_SD, "sd" }, + { SYSZ_INS_SDR, "sdr" }, + { SYSZ_INS_SDTR, "sdtr" }, + { SYSZ_INS_SDTRA, "sdtra" }, + { SYSZ_INS_SE, "se" }, + { SYSZ_INS_SER, "ser" }, + { SYSZ_INS_SFASR, "sfasr" }, + { SYSZ_INS_SFPC, "sfpc" }, + { SYSZ_INS_SGH, "sgh" }, + { SYSZ_INS_SHHHR, "shhhr" }, + { SYSZ_INS_SHHLR, "shhlr" }, + { SYSZ_INS_SIE, "sie" }, + { SYSZ_INS_SIGA, "siga" }, + { SYSZ_INS_SIGP, "sigp" }, + { SYSZ_INS_SLA, "sla" }, + { SYSZ_INS_SLAG, "slag" }, + { SYSZ_INS_SLAK, "slak" }, + { SYSZ_INS_SLDA, "slda" }, + { SYSZ_INS_SLDL, "sldl" }, + { SYSZ_INS_SLDT, "sldt" }, + { SYSZ_INS_SLHHHR, "slhhhr" }, + { SYSZ_INS_SLHHLR, "slhhlr" }, + { SYSZ_INS_SLXT, "slxt" }, + { SYSZ_INS_SP, "sp" }, + { SYSZ_INS_SPCTR, "spctr" }, + { SYSZ_INS_SPKA, "spka" }, + { SYSZ_INS_SPM, "spm" }, + { SYSZ_INS_SPT, "spt" }, + { SYSZ_INS_SPX, "spx" }, + { SYSZ_INS_SQD, "sqd" }, + { SYSZ_INS_SQDR, "sqdr" }, + { SYSZ_INS_SQE, "sqe" }, + { SYSZ_INS_SQER, "sqer" }, + { SYSZ_INS_SQXR, "sqxr" }, + { SYSZ_INS_SRDA, "srda" }, + { SYSZ_INS_SRDL, "srdl" }, + { SYSZ_INS_SRDT, "srdt" }, + { SYSZ_INS_SRNM, "srnm" }, + { SYSZ_INS_SRNMB, "srnmb" }, + { SYSZ_INS_SRNMT, "srnmt" }, + { SYSZ_INS_SRP, "srp" }, + { SYSZ_INS_SRSTU, "srstu" }, + { SYSZ_INS_SRXT, "srxt" }, + { SYSZ_INS_SSAIR, "ssair" }, + { SYSZ_INS_SSAR, "ssar" }, + { SYSZ_INS_SSCH, "ssch" }, + { SYSZ_INS_SSKE, "sske" }, + { SYSZ_INS_SSM, "ssm" }, + { SYSZ_INS_STAM, "stam" }, + { SYSZ_INS_STAMY, "stamy" }, + { SYSZ_INS_STAP, "stap" }, + { SYSZ_INS_STCK, "stck" }, + { SYSZ_INS_STCKC, "stckc" }, + { SYSZ_INS_STCKE, "stcke" }, + { SYSZ_INS_STCKF, "stckf" }, + { SYSZ_INS_STCM, "stcm" }, + { SYSZ_INS_STCMH, "stcmh" }, + { SYSZ_INS_STCMY, "stcmy" }, + { SYSZ_INS_STCPS, "stcps" }, + { SYSZ_INS_STCRW, "stcrw" }, + { SYSZ_INS_STCTG, "stctg" }, + { SYSZ_INS_STCTL, "stctl" }, + { SYSZ_INS_STFL, "stfl" }, + { SYSZ_INS_STFLE, "stfle" }, + { SYSZ_INS_STFPC, "stfpc" }, + { SYSZ_INS_STGSC, "stgsc" }, + { SYSZ_INS_STIDP, "stidp" }, + { SYSZ_INS_STM, "stm" }, + { SYSZ_INS_STMH, "stmh" }, + { SYSZ_INS_STMY, "stmy" }, + { SYSZ_INS_STNSM, "stnsm" }, + { SYSZ_INS_STOCFH, "stocfh" }, + { SYSZ_INS_STOCFHE, "stocfhe" }, + { SYSZ_INS_STOCFHH, "stocfhh" }, + { SYSZ_INS_STOCFHHE, "stocfhhe" }, + { SYSZ_INS_STOCFHL, "stocfhl" }, + { SYSZ_INS_STOCFHLE, "stocfhle" }, + { SYSZ_INS_STOCFHLH, "stocfhlh" }, + { SYSZ_INS_STOCFHM, "stocfhm" }, + { SYSZ_INS_STOCFHNE, "stocfhne" }, + { SYSZ_INS_STOCFHNH, "stocfhnh" }, + { SYSZ_INS_STOCFHNHE, "stocfhnhe" }, + { SYSZ_INS_STOCFHNL, "stocfhnl" }, + { SYSZ_INS_STOCFHNLE, "stocfhnle" }, + { SYSZ_INS_STOCFHNLH, "stocfhnlh" }, + { SYSZ_INS_STOCFHNM, "stocfhnm" }, + { SYSZ_INS_STOCFHNO, "stocfhno" }, + { SYSZ_INS_STOCFHNP, "stocfhnp" }, + { SYSZ_INS_STOCFHNZ, "stocfhnz" }, + { SYSZ_INS_STOCFHO, "stocfho" }, + { SYSZ_INS_STOCFHP, "stocfhp" }, + { SYSZ_INS_STOCFHZ, "stocfhz" }, + { SYSZ_INS_STOCGM, "stocgm" }, + { SYSZ_INS_STOCGNM, "stocgnm" }, + { SYSZ_INS_STOCGNP, "stocgnp" }, + { SYSZ_INS_STOCGNZ, "stocgnz" }, + { SYSZ_INS_STOCGP, "stocgp" }, + { SYSZ_INS_STOCGZ, "stocgz" }, + { SYSZ_INS_STOCM, "stocm" }, + { SYSZ_INS_STOCNM, "stocnm" }, + { SYSZ_INS_STOCNP, "stocnp" }, + { SYSZ_INS_STOCNZ, "stocnz" }, + { SYSZ_INS_STOCP, "stocp" }, + { SYSZ_INS_STOCZ, "stocz" }, + { SYSZ_INS_STOSM, "stosm" }, + { SYSZ_INS_STPQ, "stpq" }, + { SYSZ_INS_STPT, "stpt" }, + { SYSZ_INS_STPX, "stpx" }, + { SYSZ_INS_STRAG, "strag" }, + { SYSZ_INS_STRVH, "strvh" }, + { SYSZ_INS_STSCH, "stsch" }, + { SYSZ_INS_STSI, "stsi" }, + { SYSZ_INS_STURA, "stura" }, + { SYSZ_INS_STURG, "sturg" }, + { SYSZ_INS_SU, "su" }, + { SYSZ_INS_SUR, "sur" }, + { SYSZ_INS_SVC, "svc" }, + { SYSZ_INS_SW, "sw" }, + { SYSZ_INS_SWR, "swr" }, + { SYSZ_INS_SXR, "sxr" }, + { SYSZ_INS_SXTR, "sxtr" }, + { SYSZ_INS_SXTRA, "sxtra" }, + { SYSZ_INS_TABORT, "tabort" }, + { SYSZ_INS_TAM, "tam" }, + { SYSZ_INS_TAR, "tar" }, + { SYSZ_INS_TB, "tb" }, + { SYSZ_INS_TBDR, "tbdr" }, + { SYSZ_INS_TBEDR, "tbedr" }, + { SYSZ_INS_TBEGIN, "tbegin" }, + { SYSZ_INS_TBEGINC, "tbeginc" }, + { SYSZ_INS_TCDB, "tcdb" }, + { SYSZ_INS_TCEB, "tceb" }, + { SYSZ_INS_TCXB, "tcxb" }, + { SYSZ_INS_TDCDT, "tdcdt" }, + { SYSZ_INS_TDCET, "tdcet" }, + { SYSZ_INS_TDCXT, "tdcxt" }, + { SYSZ_INS_TDGDT, "tdgdt" }, + { SYSZ_INS_TDGET, "tdget" }, + { SYSZ_INS_TDGXT, "tdgxt" }, + { SYSZ_INS_TEND, "tend" }, + { SYSZ_INS_THDER, "thder" }, + { SYSZ_INS_THDR, "thdr" }, + { SYSZ_INS_TP, "tp" }, + { SYSZ_INS_TPI, "tpi" }, + { SYSZ_INS_TPROT, "tprot" }, + { SYSZ_INS_TR, "tr" }, + { SYSZ_INS_TRACE, "trace" }, + { SYSZ_INS_TRACG, "tracg" }, + { SYSZ_INS_TRAP2, "trap2" }, + { SYSZ_INS_TRAP4, "trap4" }, + { SYSZ_INS_TRE, "tre" }, + { SYSZ_INS_TROO, "troo" }, + { SYSZ_INS_TROT, "trot" }, + { SYSZ_INS_TRT, "trt" }, + { SYSZ_INS_TRTE, "trte" }, + { SYSZ_INS_TRTO, "trto" }, + { SYSZ_INS_TRTR, "trtr" }, + { SYSZ_INS_TRTRE, "trtre" }, + { SYSZ_INS_TRTT, "trtt" }, + { SYSZ_INS_TS, "ts" }, + { SYSZ_INS_TSCH, "tsch" }, + { SYSZ_INS_UNPK, "unpk" }, + { SYSZ_INS_UNPKA, "unpka" }, + { SYSZ_INS_UNPKU, "unpku" }, + { SYSZ_INS_UPT, "upt" }, + { SYSZ_INS_VA, "va" }, + { SYSZ_INS_VAB, "vab" }, + { SYSZ_INS_VAC, "vac" }, + { SYSZ_INS_VACC, "vacc" }, + { SYSZ_INS_VACCB, "vaccb" }, + { SYSZ_INS_VACCC, "vaccc" }, + { SYSZ_INS_VACCCQ, "vacccq" }, + { SYSZ_INS_VACCF, "vaccf" }, + { SYSZ_INS_VACCG, "vaccg" }, + { SYSZ_INS_VACCH, "vacch" }, + { SYSZ_INS_VACCQ, "vaccq" }, + { SYSZ_INS_VACQ, "vacq" }, + { SYSZ_INS_VAF, "vaf" }, + { SYSZ_INS_VAG, "vag" }, + { SYSZ_INS_VAH, "vah" }, + { SYSZ_INS_VAP, "vap" }, + { SYSZ_INS_VAQ, "vaq" }, + { SYSZ_INS_VAVG, "vavg" }, + { SYSZ_INS_VAVGB, "vavgb" }, + { SYSZ_INS_VAVGF, "vavgf" }, + { SYSZ_INS_VAVGG, "vavgg" }, + { SYSZ_INS_VAVGH, "vavgh" }, + { SYSZ_INS_VAVGL, "vavgl" }, + { SYSZ_INS_VAVGLB, "vavglb" }, + { SYSZ_INS_VAVGLF, "vavglf" }, + { SYSZ_INS_VAVGLG, "vavglg" }, + { SYSZ_INS_VAVGLH, "vavglh" }, + { SYSZ_INS_VBPERM, "vbperm" }, + { SYSZ_INS_VCDG, "vcdg" }, + { SYSZ_INS_VCDGB, "vcdgb" }, + { SYSZ_INS_VCDLG, "vcdlg" }, + { SYSZ_INS_VCDLGB, "vcdlgb" }, + { SYSZ_INS_VCEQ, "vceq" }, + { SYSZ_INS_VCEQB, "vceqb" }, + { SYSZ_INS_VCEQBS, "vceqbs" }, + { SYSZ_INS_VCEQF, "vceqf" }, + { SYSZ_INS_VCEQFS, "vceqfs" }, + { SYSZ_INS_VCEQG, "vceqg" }, + { SYSZ_INS_VCEQGS, "vceqgs" }, + { SYSZ_INS_VCEQH, "vceqh" }, + { SYSZ_INS_VCEQHS, "vceqhs" }, + { SYSZ_INS_VCGD, "vcgd" }, + { SYSZ_INS_VCGDB, "vcgdb" }, + { SYSZ_INS_VCH, "vch" }, + { SYSZ_INS_VCHB, "vchb" }, + { SYSZ_INS_VCHBS, "vchbs" }, + { SYSZ_INS_VCHF, "vchf" }, + { SYSZ_INS_VCHFS, "vchfs" }, + { SYSZ_INS_VCHG, "vchg" }, + { SYSZ_INS_VCHGS, "vchgs" }, + { SYSZ_INS_VCHH, "vchh" }, + { SYSZ_INS_VCHHS, "vchhs" }, + { SYSZ_INS_VCHL, "vchl" }, + { SYSZ_INS_VCHLB, "vchlb" }, + { SYSZ_INS_VCHLBS, "vchlbs" }, + { SYSZ_INS_VCHLF, "vchlf" }, + { SYSZ_INS_VCHLFS, "vchlfs" }, + { SYSZ_INS_VCHLG, "vchlg" }, + { SYSZ_INS_VCHLGS, "vchlgs" }, + { SYSZ_INS_VCHLH, "vchlh" }, + { SYSZ_INS_VCHLHS, "vchlhs" }, + { SYSZ_INS_VCKSM, "vcksm" }, + { SYSZ_INS_VCLGD, "vclgd" }, + { SYSZ_INS_VCLGDB, "vclgdb" }, + { SYSZ_INS_VCLZ, "vclz" }, + { SYSZ_INS_VCLZB, "vclzb" }, + { SYSZ_INS_VCLZF, "vclzf" }, + { SYSZ_INS_VCLZG, "vclzg" }, + { SYSZ_INS_VCLZH, "vclzh" }, + { SYSZ_INS_VCP, "vcp" }, + { SYSZ_INS_VCTZ, "vctz" }, + { SYSZ_INS_VCTZB, "vctzb" }, + { SYSZ_INS_VCTZF, "vctzf" }, + { SYSZ_INS_VCTZG, "vctzg" }, + { SYSZ_INS_VCTZH, "vctzh" }, + { SYSZ_INS_VCVB, "vcvb" }, + { SYSZ_INS_VCVBG, "vcvbg" }, + { SYSZ_INS_VCVD, "vcvd" }, + { SYSZ_INS_VCVDG, "vcvdg" }, + { SYSZ_INS_VDP, "vdp" }, + { SYSZ_INS_VEC, "vec" }, + { SYSZ_INS_VECB, "vecb" }, + { SYSZ_INS_VECF, "vecf" }, + { SYSZ_INS_VECG, "vecg" }, + { SYSZ_INS_VECH, "vech" }, + { SYSZ_INS_VECL, "vecl" }, + { SYSZ_INS_VECLB, "veclb" }, + { SYSZ_INS_VECLF, "veclf" }, + { SYSZ_INS_VECLG, "veclg" }, + { SYSZ_INS_VECLH, "veclh" }, + { SYSZ_INS_VERIM, "verim" }, + { SYSZ_INS_VERIMB, "verimb" }, + { SYSZ_INS_VERIMF, "verimf" }, + { SYSZ_INS_VERIMG, "verimg" }, + { SYSZ_INS_VERIMH, "verimh" }, + { SYSZ_INS_VERLL, "verll" }, + { SYSZ_INS_VERLLB, "verllb" }, + { SYSZ_INS_VERLLF, "verllf" }, + { SYSZ_INS_VERLLG, "verllg" }, + { SYSZ_INS_VERLLH, "verllh" }, + { SYSZ_INS_VERLLV, "verllv" }, + { SYSZ_INS_VERLLVB, "verllvb" }, + { SYSZ_INS_VERLLVF, "verllvf" }, + { SYSZ_INS_VERLLVG, "verllvg" }, + { SYSZ_INS_VERLLVH, "verllvh" }, + { SYSZ_INS_VESL, "vesl" }, + { SYSZ_INS_VESLB, "veslb" }, + { SYSZ_INS_VESLF, "veslf" }, + { SYSZ_INS_VESLG, "veslg" }, + { SYSZ_INS_VESLH, "veslh" }, + { SYSZ_INS_VESLV, "veslv" }, + { SYSZ_INS_VESLVB, "veslvb" }, + { SYSZ_INS_VESLVF, "veslvf" }, + { SYSZ_INS_VESLVG, "veslvg" }, + { SYSZ_INS_VESLVH, "veslvh" }, + { SYSZ_INS_VESRA, "vesra" }, + { SYSZ_INS_VESRAB, "vesrab" }, + { SYSZ_INS_VESRAF, "vesraf" }, + { SYSZ_INS_VESRAG, "vesrag" }, + { SYSZ_INS_VESRAH, "vesrah" }, + { SYSZ_INS_VESRAV, "vesrav" }, + { SYSZ_INS_VESRAVB, "vesravb" }, + { SYSZ_INS_VESRAVF, "vesravf" }, + { SYSZ_INS_VESRAVG, "vesravg" }, + { SYSZ_INS_VESRAVH, "vesravh" }, + { SYSZ_INS_VESRL, "vesrl" }, + { SYSZ_INS_VESRLB, "vesrlb" }, + { SYSZ_INS_VESRLF, "vesrlf" }, + { SYSZ_INS_VESRLG, "vesrlg" }, + { SYSZ_INS_VESRLH, "vesrlh" }, + { SYSZ_INS_VESRLV, "vesrlv" }, + { SYSZ_INS_VESRLVB, "vesrlvb" }, + { SYSZ_INS_VESRLVF, "vesrlvf" }, + { SYSZ_INS_VESRLVG, "vesrlvg" }, + { SYSZ_INS_VESRLVH, "vesrlvh" }, + { SYSZ_INS_VFA, "vfa" }, + { SYSZ_INS_VFADB, "vfadb" }, + { SYSZ_INS_VFAE, "vfae" }, + { SYSZ_INS_VFAEB, "vfaeb" }, + { SYSZ_INS_VFAEBS, "vfaebs" }, + { SYSZ_INS_VFAEF, "vfaef" }, + { SYSZ_INS_VFAEFS, "vfaefs" }, + { SYSZ_INS_VFAEH, "vfaeh" }, + { SYSZ_INS_VFAEHS, "vfaehs" }, + { SYSZ_INS_VFAEZB, "vfaezb" }, + { SYSZ_INS_VFAEZBS, "vfaezbs" }, + { SYSZ_INS_VFAEZF, "vfaezf" }, + { SYSZ_INS_VFAEZFS, "vfaezfs" }, + { SYSZ_INS_VFAEZH, "vfaezh" }, + { SYSZ_INS_VFAEZHS, "vfaezhs" }, + { SYSZ_INS_VFASB, "vfasb" }, + { SYSZ_INS_VFCE, "vfce" }, + { SYSZ_INS_VFCEDB, "vfcedb" }, + { SYSZ_INS_VFCEDBS, "vfcedbs" }, + { SYSZ_INS_VFCESB, "vfcesb" }, + { SYSZ_INS_VFCESBS, "vfcesbs" }, + { SYSZ_INS_VFCH, "vfch" }, + { SYSZ_INS_VFCHDB, "vfchdb" }, + { SYSZ_INS_VFCHDBS, "vfchdbs" }, + { SYSZ_INS_VFCHE, "vfche" }, + { SYSZ_INS_VFCHEDB, "vfchedb" }, + { SYSZ_INS_VFCHEDBS, "vfchedbs" }, + { SYSZ_INS_VFCHESB, "vfchesb" }, + { SYSZ_INS_VFCHESBS, "vfchesbs" }, + { SYSZ_INS_VFCHSB, "vfchsb" }, + { SYSZ_INS_VFCHSBS, "vfchsbs" }, + { SYSZ_INS_VFD, "vfd" }, + { SYSZ_INS_VFDDB, "vfddb" }, + { SYSZ_INS_VFDSB, "vfdsb" }, + { SYSZ_INS_VFEE, "vfee" }, + { SYSZ_INS_VFEEB, "vfeeb" }, + { SYSZ_INS_VFEEBS, "vfeebs" }, + { SYSZ_INS_VFEEF, "vfeef" }, + { SYSZ_INS_VFEEFS, "vfeefs" }, + { SYSZ_INS_VFEEH, "vfeeh" }, + { SYSZ_INS_VFEEHS, "vfeehs" }, + { SYSZ_INS_VFEEZB, "vfeezb" }, + { SYSZ_INS_VFEEZBS, "vfeezbs" }, + { SYSZ_INS_VFEEZF, "vfeezf" }, + { SYSZ_INS_VFEEZFS, "vfeezfs" }, + { SYSZ_INS_VFEEZH, "vfeezh" }, + { SYSZ_INS_VFEEZHS, "vfeezhs" }, + { SYSZ_INS_VFENE, "vfene" }, + { SYSZ_INS_VFENEB, "vfeneb" }, + { SYSZ_INS_VFENEBS, "vfenebs" }, + { SYSZ_INS_VFENEF, "vfenef" }, + { SYSZ_INS_VFENEFS, "vfenefs" }, + { SYSZ_INS_VFENEH, "vfeneh" }, + { SYSZ_INS_VFENEHS, "vfenehs" }, + { SYSZ_INS_VFENEZB, "vfenezb" }, + { SYSZ_INS_VFENEZBS, "vfenezbs" }, + { SYSZ_INS_VFENEZF, "vfenezf" }, + { SYSZ_INS_VFENEZFS, "vfenezfs" }, + { SYSZ_INS_VFENEZH, "vfenezh" }, + { SYSZ_INS_VFENEZHS, "vfenezhs" }, + { SYSZ_INS_VFI, "vfi" }, + { SYSZ_INS_VFIDB, "vfidb" }, + { SYSZ_INS_VFISB, "vfisb" }, + { SYSZ_INS_VFKEDB, "vfkedb" }, + { SYSZ_INS_VFKEDBS, "vfkedbs" }, + { SYSZ_INS_VFKESB, "vfkesb" }, + { SYSZ_INS_VFKESBS, "vfkesbs" }, + { SYSZ_INS_VFKHDB, "vfkhdb" }, + { SYSZ_INS_VFKHDBS, "vfkhdbs" }, + { SYSZ_INS_VFKHEDB, "vfkhedb" }, + { SYSZ_INS_VFKHEDBS, "vfkhedbs" }, + { SYSZ_INS_VFKHESB, "vfkhesb" }, + { SYSZ_INS_VFKHESBS, "vfkhesbs" }, + { SYSZ_INS_VFKHSB, "vfkhsb" }, + { SYSZ_INS_VFKHSBS, "vfkhsbs" }, + { SYSZ_INS_VFLCDB, "vflcdb" }, + { SYSZ_INS_VFLCSB, "vflcsb" }, + { SYSZ_INS_VFLL, "vfll" }, + { SYSZ_INS_VFLLS, "vflls" }, + { SYSZ_INS_VFLNDB, "vflndb" }, + { SYSZ_INS_VFLNSB, "vflnsb" }, + { SYSZ_INS_VFLPDB, "vflpdb" }, + { SYSZ_INS_VFLPSB, "vflpsb" }, + { SYSZ_INS_VFLR, "vflr" }, + { SYSZ_INS_VFLRD, "vflrd" }, + { SYSZ_INS_VFM, "vfm" }, + { SYSZ_INS_VFMA, "vfma" }, + { SYSZ_INS_VFMADB, "vfmadb" }, + { SYSZ_INS_VFMASB, "vfmasb" }, + { SYSZ_INS_VFMAX, "vfmax" }, + { SYSZ_INS_VFMAXDB, "vfmaxdb" }, + { SYSZ_INS_VFMAXSB, "vfmaxsb" }, + { SYSZ_INS_VFMDB, "vfmdb" }, + { SYSZ_INS_VFMIN, "vfmin" }, + { SYSZ_INS_VFMINDB, "vfmindb" }, + { SYSZ_INS_VFMINSB, "vfminsb" }, + { SYSZ_INS_VFMS, "vfms" }, + { SYSZ_INS_VFMSB, "vfmsb" }, + { SYSZ_INS_VFMSDB, "vfmsdb" }, + { SYSZ_INS_VFMSSB, "vfmssb" }, + { SYSZ_INS_VFNMA, "vfnma" }, + { SYSZ_INS_VFNMADB, "vfnmadb" }, + { SYSZ_INS_VFNMASB, "vfnmasb" }, + { SYSZ_INS_VFNMS, "vfnms" }, + { SYSZ_INS_VFNMSDB, "vfnmsdb" }, + { SYSZ_INS_VFNMSSB, "vfnmssb" }, + { SYSZ_INS_VFPSO, "vfpso" }, + { SYSZ_INS_VFPSODB, "vfpsodb" }, + { SYSZ_INS_VFPSOSB, "vfpsosb" }, + { SYSZ_INS_VFS, "vfs" }, + { SYSZ_INS_VFSDB, "vfsdb" }, + { SYSZ_INS_VFSQ, "vfsq" }, + { SYSZ_INS_VFSQDB, "vfsqdb" }, + { SYSZ_INS_VFSQSB, "vfsqsb" }, + { SYSZ_INS_VFSSB, "vfssb" }, + { SYSZ_INS_VFTCI, "vftci" }, + { SYSZ_INS_VFTCIDB, "vftcidb" }, + { SYSZ_INS_VFTCISB, "vftcisb" }, + { SYSZ_INS_VGBM, "vgbm" }, + { SYSZ_INS_VGEF, "vgef" }, + { SYSZ_INS_VGEG, "vgeg" }, + { SYSZ_INS_VGFM, "vgfm" }, + { SYSZ_INS_VGFMA, "vgfma" }, + { SYSZ_INS_VGFMAB, "vgfmab" }, + { SYSZ_INS_VGFMAF, "vgfmaf" }, + { SYSZ_INS_VGFMAG, "vgfmag" }, + { SYSZ_INS_VGFMAH, "vgfmah" }, + { SYSZ_INS_VGFMB, "vgfmb" }, + { SYSZ_INS_VGFMF, "vgfmf" }, + { SYSZ_INS_VGFMG, "vgfmg" }, + { SYSZ_INS_VGFMH, "vgfmh" }, + { SYSZ_INS_VGM, "vgm" }, + { SYSZ_INS_VGMB, "vgmb" }, + { SYSZ_INS_VGMF, "vgmf" }, + { SYSZ_INS_VGMG, "vgmg" }, + { SYSZ_INS_VGMH, "vgmh" }, + { SYSZ_INS_VISTR, "vistr" }, + { SYSZ_INS_VISTRB, "vistrb" }, + { SYSZ_INS_VISTRBS, "vistrbs" }, + { SYSZ_INS_VISTRF, "vistrf" }, + { SYSZ_INS_VISTRFS, "vistrfs" }, + { SYSZ_INS_VISTRH, "vistrh" }, + { SYSZ_INS_VISTRHS, "vistrhs" }, + { SYSZ_INS_VL, "vl" }, + { SYSZ_INS_VLBB, "vlbb" }, + { SYSZ_INS_VLC, "vlc" }, + { SYSZ_INS_VLCB, "vlcb" }, + { SYSZ_INS_VLCF, "vlcf" }, + { SYSZ_INS_VLCG, "vlcg" }, + { SYSZ_INS_VLCH, "vlch" }, + { SYSZ_INS_VLDE, "vlde" }, + { SYSZ_INS_VLDEB, "vldeb" }, + { SYSZ_INS_VLEB, "vleb" }, + { SYSZ_INS_VLED, "vled" }, + { SYSZ_INS_VLEDB, "vledb" }, + { SYSZ_INS_VLEF, "vlef" }, + { SYSZ_INS_VLEG, "vleg" }, + { SYSZ_INS_VLEH, "vleh" }, + { SYSZ_INS_VLEIB, "vleib" }, + { SYSZ_INS_VLEIF, "vleif" }, + { SYSZ_INS_VLEIG, "vleig" }, + { SYSZ_INS_VLEIH, "vleih" }, + { SYSZ_INS_VLGV, "vlgv" }, + { SYSZ_INS_VLGVB, "vlgvb" }, + { SYSZ_INS_VLGVF, "vlgvf" }, + { SYSZ_INS_VLGVG, "vlgvg" }, + { SYSZ_INS_VLGVH, "vlgvh" }, + { SYSZ_INS_VLIP, "vlip" }, + { SYSZ_INS_VLL, "vll" }, + { SYSZ_INS_VLLEZ, "vllez" }, + { SYSZ_INS_VLLEZB, "vllezb" }, + { SYSZ_INS_VLLEZF, "vllezf" }, + { SYSZ_INS_VLLEZG, "vllezg" }, + { SYSZ_INS_VLLEZH, "vllezh" }, + { SYSZ_INS_VLLEZLF, "vllezlf" }, + { SYSZ_INS_VLM, "vlm" }, + { SYSZ_INS_VLP, "vlp" }, + { SYSZ_INS_VLPB, "vlpb" }, + { SYSZ_INS_VLPF, "vlpf" }, + { SYSZ_INS_VLPG, "vlpg" }, + { SYSZ_INS_VLPH, "vlph" }, + { SYSZ_INS_VLR, "vlr" }, + { SYSZ_INS_VLREP, "vlrep" }, + { SYSZ_INS_VLREPB, "vlrepb" }, + { SYSZ_INS_VLREPF, "vlrepf" }, + { SYSZ_INS_VLREPG, "vlrepg" }, + { SYSZ_INS_VLREPH, "vlreph" }, + { SYSZ_INS_VLRL, "vlrl" }, + { SYSZ_INS_VLRLR, "vlrlr" }, + { SYSZ_INS_VLVG, "vlvg" }, + { SYSZ_INS_VLVGB, "vlvgb" }, + { SYSZ_INS_VLVGF, "vlvgf" }, + { SYSZ_INS_VLVGG, "vlvgg" }, + { SYSZ_INS_VLVGH, "vlvgh" }, + { SYSZ_INS_VLVGP, "vlvgp" }, + { SYSZ_INS_VMAE, "vmae" }, + { SYSZ_INS_VMAEB, "vmaeb" }, + { SYSZ_INS_VMAEF, "vmaef" }, + { SYSZ_INS_VMAEH, "vmaeh" }, + { SYSZ_INS_VMAH, "vmah" }, + { SYSZ_INS_VMAHB, "vmahb" }, + { SYSZ_INS_VMAHF, "vmahf" }, + { SYSZ_INS_VMAHH, "vmahh" }, + { SYSZ_INS_VMAL, "vmal" }, + { SYSZ_INS_VMALB, "vmalb" }, + { SYSZ_INS_VMALE, "vmale" }, + { SYSZ_INS_VMALEB, "vmaleb" }, + { SYSZ_INS_VMALEF, "vmalef" }, + { SYSZ_INS_VMALEH, "vmaleh" }, + { SYSZ_INS_VMALF, "vmalf" }, + { SYSZ_INS_VMALH, "vmalh" }, + { SYSZ_INS_VMALHB, "vmalhb" }, + { SYSZ_INS_VMALHF, "vmalhf" }, + { SYSZ_INS_VMALHH, "vmalhh" }, + { SYSZ_INS_VMALHW, "vmalhw" }, + { SYSZ_INS_VMALO, "vmalo" }, + { SYSZ_INS_VMALOB, "vmalob" }, + { SYSZ_INS_VMALOF, "vmalof" }, + { SYSZ_INS_VMALOH, "vmaloh" }, + { SYSZ_INS_VMAO, "vmao" }, + { SYSZ_INS_VMAOB, "vmaob" }, + { SYSZ_INS_VMAOF, "vmaof" }, + { SYSZ_INS_VMAOH, "vmaoh" }, + { SYSZ_INS_VME, "vme" }, + { SYSZ_INS_VMEB, "vmeb" }, + { SYSZ_INS_VMEF, "vmef" }, + { SYSZ_INS_VMEH, "vmeh" }, + { SYSZ_INS_VMH, "vmh" }, + { SYSZ_INS_VMHB, "vmhb" }, + { SYSZ_INS_VMHF, "vmhf" }, + { SYSZ_INS_VMHH, "vmhh" }, + { SYSZ_INS_VML, "vml" }, + { SYSZ_INS_VMLB, "vmlb" }, + { SYSZ_INS_VMLE, "vmle" }, + { SYSZ_INS_VMLEB, "vmleb" }, + { SYSZ_INS_VMLEF, "vmlef" }, + { SYSZ_INS_VMLEH, "vmleh" }, + { SYSZ_INS_VMLF, "vmlf" }, + { SYSZ_INS_VMLH, "vmlh" }, + { SYSZ_INS_VMLHB, "vmlhb" }, + { SYSZ_INS_VMLHF, "vmlhf" }, + { SYSZ_INS_VMLHH, "vmlhh" }, + { SYSZ_INS_VMLHW, "vmlhw" }, + { SYSZ_INS_VMLO, "vmlo" }, + { SYSZ_INS_VMLOB, "vmlob" }, + { SYSZ_INS_VMLOF, "vmlof" }, + { SYSZ_INS_VMLOH, "vmloh" }, + { SYSZ_INS_VMN, "vmn" }, + { SYSZ_INS_VMNB, "vmnb" }, + { SYSZ_INS_VMNF, "vmnf" }, + { SYSZ_INS_VMNG, "vmng" }, + { SYSZ_INS_VMNH, "vmnh" }, + { SYSZ_INS_VMNL, "vmnl" }, + { SYSZ_INS_VMNLB, "vmnlb" }, + { SYSZ_INS_VMNLF, "vmnlf" }, + { SYSZ_INS_VMNLG, "vmnlg" }, + { SYSZ_INS_VMNLH, "vmnlh" }, + { SYSZ_INS_VMO, "vmo" }, + { SYSZ_INS_VMOB, "vmob" }, + { SYSZ_INS_VMOF, "vmof" }, + { SYSZ_INS_VMOH, "vmoh" }, + { SYSZ_INS_VMP, "vmp" }, + { SYSZ_INS_VMRH, "vmrh" }, + { SYSZ_INS_VMRHB, "vmrhb" }, + { SYSZ_INS_VMRHF, "vmrhf" }, + { SYSZ_INS_VMRHG, "vmrhg" }, + { SYSZ_INS_VMRHH, "vmrhh" }, + { SYSZ_INS_VMRL, "vmrl" }, + { SYSZ_INS_VMRLB, "vmrlb" }, + { SYSZ_INS_VMRLF, "vmrlf" }, + { SYSZ_INS_VMRLG, "vmrlg" }, + { SYSZ_INS_VMRLH, "vmrlh" }, + { SYSZ_INS_VMSL, "vmsl" }, + { SYSZ_INS_VMSLG, "vmslg" }, + { SYSZ_INS_VMSP, "vmsp" }, + { SYSZ_INS_VMX, "vmx" }, + { SYSZ_INS_VMXB, "vmxb" }, + { SYSZ_INS_VMXF, "vmxf" }, + { SYSZ_INS_VMXG, "vmxg" }, + { SYSZ_INS_VMXH, "vmxh" }, + { SYSZ_INS_VMXL, "vmxl" }, + { SYSZ_INS_VMXLB, "vmxlb" }, + { SYSZ_INS_VMXLF, "vmxlf" }, + { SYSZ_INS_VMXLG, "vmxlg" }, + { SYSZ_INS_VMXLH, "vmxlh" }, + { SYSZ_INS_VN, "vn" }, + { SYSZ_INS_VNC, "vnc" }, + { SYSZ_INS_VNN, "vnn" }, + { SYSZ_INS_VNO, "vno" }, + { SYSZ_INS_VNX, "vnx" }, + { SYSZ_INS_VO, "vo" }, + { SYSZ_INS_VOC, "voc" }, + { SYSZ_INS_VONE, "vone" }, + { SYSZ_INS_VPDI, "vpdi" }, + { SYSZ_INS_VPERM, "vperm" }, + { SYSZ_INS_VPK, "vpk" }, + { SYSZ_INS_VPKF, "vpkf" }, + { SYSZ_INS_VPKG, "vpkg" }, + { SYSZ_INS_VPKH, "vpkh" }, + { SYSZ_INS_VPKLS, "vpkls" }, + { SYSZ_INS_VPKLSF, "vpklsf" }, + { SYSZ_INS_VPKLSFS, "vpklsfs" }, + { SYSZ_INS_VPKLSG, "vpklsg" }, + { SYSZ_INS_VPKLSGS, "vpklsgs" }, + { SYSZ_INS_VPKLSH, "vpklsh" }, + { SYSZ_INS_VPKLSHS, "vpklshs" }, + { SYSZ_INS_VPKS, "vpks" }, + { SYSZ_INS_VPKSF, "vpksf" }, + { SYSZ_INS_VPKSFS, "vpksfs" }, + { SYSZ_INS_VPKSG, "vpksg" }, + { SYSZ_INS_VPKSGS, "vpksgs" }, + { SYSZ_INS_VPKSH, "vpksh" }, + { SYSZ_INS_VPKSHS, "vpkshs" }, + { SYSZ_INS_VPKZ, "vpkz" }, + { SYSZ_INS_VPOPCT, "vpopct" }, + { SYSZ_INS_VPOPCTB, "vpopctb" }, + { SYSZ_INS_VPOPCTF, "vpopctf" }, + { SYSZ_INS_VPOPCTG, "vpopctg" }, + { SYSZ_INS_VPOPCTH, "vpopcth" }, + { SYSZ_INS_VPSOP, "vpsop" }, + { SYSZ_INS_VREP, "vrep" }, + { SYSZ_INS_VREPB, "vrepb" }, + { SYSZ_INS_VREPF, "vrepf" }, + { SYSZ_INS_VREPG, "vrepg" }, + { SYSZ_INS_VREPH, "vreph" }, + { SYSZ_INS_VREPI, "vrepi" }, + { SYSZ_INS_VREPIB, "vrepib" }, + { SYSZ_INS_VREPIF, "vrepif" }, + { SYSZ_INS_VREPIG, "vrepig" }, + { SYSZ_INS_VREPIH, "vrepih" }, + { SYSZ_INS_VRP, "vrp" }, + { SYSZ_INS_VS, "vs" }, + { SYSZ_INS_VSB, "vsb" }, + { SYSZ_INS_VSBCBI, "vsbcbi" }, + { SYSZ_INS_VSBCBIQ, "vsbcbiq" }, + { SYSZ_INS_VSBI, "vsbi" }, + { SYSZ_INS_VSBIQ, "vsbiq" }, + { SYSZ_INS_VSCBI, "vscbi" }, + { SYSZ_INS_VSCBIB, "vscbib" }, + { SYSZ_INS_VSCBIF, "vscbif" }, + { SYSZ_INS_VSCBIG, "vscbig" }, + { SYSZ_INS_VSCBIH, "vscbih" }, + { SYSZ_INS_VSCBIQ, "vscbiq" }, + { SYSZ_INS_VSCEF, "vscef" }, + { SYSZ_INS_VSCEG, "vsceg" }, + { SYSZ_INS_VSDP, "vsdp" }, + { SYSZ_INS_VSEG, "vseg" }, + { SYSZ_INS_VSEGB, "vsegb" }, + { SYSZ_INS_VSEGF, "vsegf" }, + { SYSZ_INS_VSEGH, "vsegh" }, + { SYSZ_INS_VSEL, "vsel" }, + { SYSZ_INS_VSF, "vsf" }, + { SYSZ_INS_VSG, "vsg" }, + { SYSZ_INS_VSH, "vsh" }, + { SYSZ_INS_VSL, "vsl" }, + { SYSZ_INS_VSLB, "vslb" }, + { SYSZ_INS_VSLDB, "vsldb" }, + { SYSZ_INS_VSP, "vsp" }, + { SYSZ_INS_VSQ, "vsq" }, + { SYSZ_INS_VSRA, "vsra" }, + { SYSZ_INS_VSRAB, "vsrab" }, + { SYSZ_INS_VSRL, "vsrl" }, + { SYSZ_INS_VSRLB, "vsrlb" }, + { SYSZ_INS_VSRP, "vsrp" }, + { SYSZ_INS_VST, "vst" }, + { SYSZ_INS_VSTEB, "vsteb" }, + { SYSZ_INS_VSTEF, "vstef" }, + { SYSZ_INS_VSTEG, "vsteg" }, + { SYSZ_INS_VSTEH, "vsteh" }, + { SYSZ_INS_VSTL, "vstl" }, + { SYSZ_INS_VSTM, "vstm" }, + { SYSZ_INS_VSTRC, "vstrc" }, + { SYSZ_INS_VSTRCB, "vstrcb" }, + { SYSZ_INS_VSTRCBS, "vstrcbs" }, + { SYSZ_INS_VSTRCF, "vstrcf" }, + { SYSZ_INS_VSTRCFS, "vstrcfs" }, + { SYSZ_INS_VSTRCH, "vstrch" }, + { SYSZ_INS_VSTRCHS, "vstrchs" }, + { SYSZ_INS_VSTRCZB, "vstrczb" }, + { SYSZ_INS_VSTRCZBS, "vstrczbs" }, + { SYSZ_INS_VSTRCZF, "vstrczf" }, + { SYSZ_INS_VSTRCZFS, "vstrczfs" }, + { SYSZ_INS_VSTRCZH, "vstrczh" }, + { SYSZ_INS_VSTRCZHS, "vstrczhs" }, + { SYSZ_INS_VSTRL, "vstrl" }, + { SYSZ_INS_VSTRLR, "vstrlr" }, + { SYSZ_INS_VSUM, "vsum" }, + { SYSZ_INS_VSUMB, "vsumb" }, + { SYSZ_INS_VSUMG, "vsumg" }, + { SYSZ_INS_VSUMGF, "vsumgf" }, + { SYSZ_INS_VSUMGH, "vsumgh" }, + { SYSZ_INS_VSUMH, "vsumh" }, + { SYSZ_INS_VSUMQ, "vsumq" }, + { SYSZ_INS_VSUMQF, "vsumqf" }, + { SYSZ_INS_VSUMQG, "vsumqg" }, + { SYSZ_INS_VTM, "vtm" }, + { SYSZ_INS_VTP, "vtp" }, + { SYSZ_INS_VUPH, "vuph" }, + { SYSZ_INS_VUPHB, "vuphb" }, + { SYSZ_INS_VUPHF, "vuphf" }, + { SYSZ_INS_VUPHH, "vuphh" }, + { SYSZ_INS_VUPKZ, "vupkz" }, + { SYSZ_INS_VUPL, "vupl" }, + { SYSZ_INS_VUPLB, "vuplb" }, + { SYSZ_INS_VUPLF, "vuplf" }, + { SYSZ_INS_VUPLH, "vuplh" }, + { SYSZ_INS_VUPLHB, "vuplhb" }, + { SYSZ_INS_VUPLHF, "vuplhf" }, + { SYSZ_INS_VUPLHH, "vuplhh" }, + { SYSZ_INS_VUPLHW, "vuplhw" }, + { SYSZ_INS_VUPLL, "vupll" }, + { SYSZ_INS_VUPLLB, "vupllb" }, + { SYSZ_INS_VUPLLF, "vupllf" }, + { SYSZ_INS_VUPLLH, "vupllh" }, + { SYSZ_INS_VX, "vx" }, + { SYSZ_INS_VZERO, "vzero" }, + { SYSZ_INS_WCDGB, "wcdgb" }, + { SYSZ_INS_WCDLGB, "wcdlgb" }, + { SYSZ_INS_WCGDB, "wcgdb" }, + { SYSZ_INS_WCLGDB, "wclgdb" }, + { SYSZ_INS_WFADB, "wfadb" }, + { SYSZ_INS_WFASB, "wfasb" }, + { SYSZ_INS_WFAXB, "wfaxb" }, + { SYSZ_INS_WFC, "wfc" }, + { SYSZ_INS_WFCDB, "wfcdb" }, + { SYSZ_INS_WFCEDB, "wfcedb" }, + { SYSZ_INS_WFCEDBS, "wfcedbs" }, + { SYSZ_INS_WFCESB, "wfcesb" }, + { SYSZ_INS_WFCESBS, "wfcesbs" }, + { SYSZ_INS_WFCEXB, "wfcexb" }, + { SYSZ_INS_WFCEXBS, "wfcexbs" }, + { SYSZ_INS_WFCHDB, "wfchdb" }, + { SYSZ_INS_WFCHDBS, "wfchdbs" }, + { SYSZ_INS_WFCHEDB, "wfchedb" }, + { SYSZ_INS_WFCHEDBS, "wfchedbs" }, + { SYSZ_INS_WFCHESB, "wfchesb" }, + { SYSZ_INS_WFCHESBS, "wfchesbs" }, + { SYSZ_INS_WFCHEXB, "wfchexb" }, + { SYSZ_INS_WFCHEXBS, "wfchexbs" }, + { SYSZ_INS_WFCHSB, "wfchsb" }, + { SYSZ_INS_WFCHSBS, "wfchsbs" }, + { SYSZ_INS_WFCHXB, "wfchxb" }, + { SYSZ_INS_WFCHXBS, "wfchxbs" }, + { SYSZ_INS_WFCSB, "wfcsb" }, + { SYSZ_INS_WFCXB, "wfcxb" }, + { SYSZ_INS_WFDDB, "wfddb" }, + { SYSZ_INS_WFDSB, "wfdsb" }, + { SYSZ_INS_WFDXB, "wfdxb" }, + { SYSZ_INS_WFIDB, "wfidb" }, + { SYSZ_INS_WFISB, "wfisb" }, + { SYSZ_INS_WFIXB, "wfixb" }, + { SYSZ_INS_WFK, "wfk" }, + { SYSZ_INS_WFKDB, "wfkdb" }, + { SYSZ_INS_WFKEDB, "wfkedb" }, + { SYSZ_INS_WFKEDBS, "wfkedbs" }, + { SYSZ_INS_WFKESB, "wfkesb" }, + { SYSZ_INS_WFKESBS, "wfkesbs" }, + { SYSZ_INS_WFKEXB, "wfkexb" }, + { SYSZ_INS_WFKEXBS, "wfkexbs" }, + { SYSZ_INS_WFKHDB, "wfkhdb" }, + { SYSZ_INS_WFKHDBS, "wfkhdbs" }, + { SYSZ_INS_WFKHEDB, "wfkhedb" }, + { SYSZ_INS_WFKHEDBS, "wfkhedbs" }, + { SYSZ_INS_WFKHESB, "wfkhesb" }, + { SYSZ_INS_WFKHESBS, "wfkhesbs" }, + { SYSZ_INS_WFKHEXB, "wfkhexb" }, + { SYSZ_INS_WFKHEXBS, "wfkhexbs" }, + { SYSZ_INS_WFKHSB, "wfkhsb" }, + { SYSZ_INS_WFKHSBS, "wfkhsbs" }, + { SYSZ_INS_WFKHXB, "wfkhxb" }, + { SYSZ_INS_WFKHXBS, "wfkhxbs" }, + { SYSZ_INS_WFKSB, "wfksb" }, + { SYSZ_INS_WFKXB, "wfkxb" }, + { SYSZ_INS_WFLCDB, "wflcdb" }, + { SYSZ_INS_WFLCSB, "wflcsb" }, + { SYSZ_INS_WFLCXB, "wflcxb" }, + { SYSZ_INS_WFLLD, "wflld" }, + { SYSZ_INS_WFLLS, "wflls" }, + { SYSZ_INS_WFLNDB, "wflndb" }, + { SYSZ_INS_WFLNSB, "wflnsb" }, + { SYSZ_INS_WFLNXB, "wflnxb" }, + { SYSZ_INS_WFLPDB, "wflpdb" }, + { SYSZ_INS_WFLPSB, "wflpsb" }, + { SYSZ_INS_WFLPXB, "wflpxb" }, + { SYSZ_INS_WFLRD, "wflrd" }, + { SYSZ_INS_WFLRX, "wflrx" }, + { SYSZ_INS_WFMADB, "wfmadb" }, + { SYSZ_INS_WFMASB, "wfmasb" }, + { SYSZ_INS_WFMAXB, "wfmaxb" }, + { SYSZ_INS_WFMAXDB, "wfmaxdb" }, + { SYSZ_INS_WFMAXSB, "wfmaxsb" }, + { SYSZ_INS_WFMAXXB, "wfmaxxb" }, + { SYSZ_INS_WFMDB, "wfmdb" }, + { SYSZ_INS_WFMINDB, "wfmindb" }, + { SYSZ_INS_WFMINSB, "wfminsb" }, + { SYSZ_INS_WFMINXB, "wfminxb" }, + { SYSZ_INS_WFMSB, "wfmsb" }, + { SYSZ_INS_WFMSDB, "wfmsdb" }, + { SYSZ_INS_WFMSSB, "wfmssb" }, + { SYSZ_INS_WFMSXB, "wfmsxb" }, + { SYSZ_INS_WFMXB, "wfmxb" }, + { SYSZ_INS_WFNMADB, "wfnmadb" }, + { SYSZ_INS_WFNMASB, "wfnmasb" }, + { SYSZ_INS_WFNMAXB, "wfnmaxb" }, + { SYSZ_INS_WFNMSDB, "wfnmsdb" }, + { SYSZ_INS_WFNMSSB, "wfnmssb" }, + { SYSZ_INS_WFNMSXB, "wfnmsxb" }, + { SYSZ_INS_WFPSODB, "wfpsodb" }, + { SYSZ_INS_WFPSOSB, "wfpsosb" }, + { SYSZ_INS_WFPSOXB, "wfpsoxb" }, + { SYSZ_INS_WFSDB, "wfsdb" }, + { SYSZ_INS_WFSQDB, "wfsqdb" }, + { SYSZ_INS_WFSQSB, "wfsqsb" }, + { SYSZ_INS_WFSQXB, "wfsqxb" }, + { SYSZ_INS_WFSSB, "wfssb" }, + { SYSZ_INS_WFSXB, "wfsxb" }, + { SYSZ_INS_WFTCIDB, "wftcidb" }, + { SYSZ_INS_WFTCISB, "wftcisb" }, + { SYSZ_INS_WFTCIXB, "wftcixb" }, + { SYSZ_INS_WLDEB, "wldeb" }, + { SYSZ_INS_WLEDB, "wledb" }, + { SYSZ_INS_XSCH, "xsch" }, + { SYSZ_INS_ZAP, "zap" }, diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInstrInfo.inc new file mode 100644 index 0000000..0f23556 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenInstrInfo.inc @@ -0,0 +1,2820 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Instruction Enum Values and Descriptors *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + SystemZ_PHI = 0, + SystemZ_INLINEASM = 1, + SystemZ_CFI_INSTRUCTION = 2, + SystemZ_EH_LABEL = 3, + SystemZ_GC_LABEL = 4, + SystemZ_ANNOTATION_LABEL = 5, + SystemZ_KILL = 6, + SystemZ_EXTRACT_SUBREG = 7, + SystemZ_INSERT_SUBREG = 8, + SystemZ_IMPLICIT_DEF = 9, + SystemZ_SUBREG_TO_REG = 10, + SystemZ_COPY_TO_REGCLASS = 11, + SystemZ_DBG_VALUE = 12, + SystemZ_DBG_LABEL = 13, + SystemZ_REG_SEQUENCE = 14, + SystemZ_COPY = 15, + SystemZ_BUNDLE = 16, + SystemZ_LIFETIME_START = 17, + SystemZ_LIFETIME_END = 18, + SystemZ_STACKMAP = 19, + SystemZ_FENTRY_CALL = 20, + SystemZ_PATCHPOINT = 21, + SystemZ_LOAD_STACK_GUARD = 22, + SystemZ_STATEPOINT = 23, + SystemZ_LOCAL_ESCAPE = 24, + SystemZ_FAULTING_OP = 25, + SystemZ_PATCHABLE_OP = 26, + SystemZ_PATCHABLE_FUNCTION_ENTER = 27, + SystemZ_PATCHABLE_RET = 28, + SystemZ_PATCHABLE_FUNCTION_EXIT = 29, + SystemZ_PATCHABLE_TAIL_CALL = 30, + SystemZ_PATCHABLE_EVENT_CALL = 31, + SystemZ_PATCHABLE_TYPED_EVENT_CALL = 32, + SystemZ_ICALL_BRANCH_FUNNEL = 33, + SystemZ_G_ADD = 34, + SystemZ_G_SUB = 35, + SystemZ_G_MUL = 36, + SystemZ_G_SDIV = 37, + SystemZ_G_UDIV = 38, + SystemZ_G_SREM = 39, + SystemZ_G_UREM = 40, + SystemZ_G_AND = 41, + SystemZ_G_OR = 42, + SystemZ_G_XOR = 43, + SystemZ_G_IMPLICIT_DEF = 44, + SystemZ_G_PHI = 45, + SystemZ_G_FRAME_INDEX = 46, + SystemZ_G_GLOBAL_VALUE = 47, + SystemZ_G_EXTRACT = 48, + SystemZ_G_UNMERGE_VALUES = 49, + SystemZ_G_INSERT = 50, + SystemZ_G_MERGE_VALUES = 51, + SystemZ_G_PTRTOINT = 52, + SystemZ_G_INTTOPTR = 53, + SystemZ_G_BITCAST = 54, + SystemZ_G_LOAD = 55, + SystemZ_G_SEXTLOAD = 56, + SystemZ_G_ZEXTLOAD = 57, + SystemZ_G_STORE = 58, + SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + SystemZ_G_ATOMIC_CMPXCHG = 60, + SystemZ_G_ATOMICRMW_XCHG = 61, + SystemZ_G_ATOMICRMW_ADD = 62, + SystemZ_G_ATOMICRMW_SUB = 63, + SystemZ_G_ATOMICRMW_AND = 64, + SystemZ_G_ATOMICRMW_NAND = 65, + SystemZ_G_ATOMICRMW_OR = 66, + SystemZ_G_ATOMICRMW_XOR = 67, + SystemZ_G_ATOMICRMW_MAX = 68, + SystemZ_G_ATOMICRMW_MIN = 69, + SystemZ_G_ATOMICRMW_UMAX = 70, + SystemZ_G_ATOMICRMW_UMIN = 71, + SystemZ_G_BRCOND = 72, + SystemZ_G_BRINDIRECT = 73, + SystemZ_G_INTRINSIC = 74, + SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 75, + SystemZ_G_ANYEXT = 76, + SystemZ_G_TRUNC = 77, + SystemZ_G_CONSTANT = 78, + SystemZ_G_FCONSTANT = 79, + SystemZ_G_VASTART = 80, + SystemZ_G_VAARG = 81, + SystemZ_G_SEXT = 82, + SystemZ_G_ZEXT = 83, + SystemZ_G_SHL = 84, + SystemZ_G_LSHR = 85, + SystemZ_G_ASHR = 86, + SystemZ_G_ICMP = 87, + SystemZ_G_FCMP = 88, + SystemZ_G_SELECT = 89, + SystemZ_G_UADDE = 90, + SystemZ_G_USUBE = 91, + SystemZ_G_SADDO = 92, + SystemZ_G_SSUBO = 93, + SystemZ_G_UMULO = 94, + SystemZ_G_SMULO = 95, + SystemZ_G_UMULH = 96, + SystemZ_G_SMULH = 97, + SystemZ_G_FADD = 98, + SystemZ_G_FSUB = 99, + SystemZ_G_FMUL = 100, + SystemZ_G_FMA = 101, + SystemZ_G_FDIV = 102, + SystemZ_G_FREM = 103, + SystemZ_G_FPOW = 104, + SystemZ_G_FEXP = 105, + SystemZ_G_FEXP2 = 106, + SystemZ_G_FLOG = 107, + SystemZ_G_FLOG2 = 108, + SystemZ_G_FNEG = 109, + SystemZ_G_FPEXT = 110, + SystemZ_G_FPTRUNC = 111, + SystemZ_G_FPTOSI = 112, + SystemZ_G_FPTOUI = 113, + SystemZ_G_SITOFP = 114, + SystemZ_G_UITOFP = 115, + SystemZ_G_FABS = 116, + SystemZ_G_GEP = 117, + SystemZ_G_PTR_MASK = 118, + SystemZ_G_BR = 119, + SystemZ_G_INSERT_VECTOR_ELT = 120, + SystemZ_G_EXTRACT_VECTOR_ELT = 121, + SystemZ_G_SHUFFLE_VECTOR = 122, + SystemZ_G_BSWAP = 123, + SystemZ_G_ADDRSPACE_CAST = 124, + SystemZ_ADJCALLSTACKDOWN = 125, + SystemZ_ADJCALLSTACKUP = 126, + SystemZ_ADJDYNALLOC = 127, + SystemZ_AEXT128 = 128, + SystemZ_AFIMux = 129, + SystemZ_AHIMux = 130, + SystemZ_AHIMuxK = 131, + SystemZ_ATOMIC_CMP_SWAPW = 132, + SystemZ_ATOMIC_LOADW_AFI = 133, + SystemZ_ATOMIC_LOADW_AR = 134, + SystemZ_ATOMIC_LOADW_MAX = 135, + SystemZ_ATOMIC_LOADW_MIN = 136, + SystemZ_ATOMIC_LOADW_NILH = 137, + SystemZ_ATOMIC_LOADW_NILHi = 138, + SystemZ_ATOMIC_LOADW_NR = 139, + SystemZ_ATOMIC_LOADW_NRi = 140, + SystemZ_ATOMIC_LOADW_OILH = 141, + SystemZ_ATOMIC_LOADW_OR = 142, + SystemZ_ATOMIC_LOADW_SR = 143, + SystemZ_ATOMIC_LOADW_UMAX = 144, + SystemZ_ATOMIC_LOADW_UMIN = 145, + SystemZ_ATOMIC_LOADW_XILF = 146, + SystemZ_ATOMIC_LOADW_XR = 147, + SystemZ_ATOMIC_LOAD_AFI = 148, + SystemZ_ATOMIC_LOAD_AGFI = 149, + SystemZ_ATOMIC_LOAD_AGHI = 150, + SystemZ_ATOMIC_LOAD_AGR = 151, + SystemZ_ATOMIC_LOAD_AHI = 152, + SystemZ_ATOMIC_LOAD_AR = 153, + SystemZ_ATOMIC_LOAD_MAX_32 = 154, + SystemZ_ATOMIC_LOAD_MAX_64 = 155, + SystemZ_ATOMIC_LOAD_MIN_32 = 156, + SystemZ_ATOMIC_LOAD_MIN_64 = 157, + SystemZ_ATOMIC_LOAD_NGR = 158, + SystemZ_ATOMIC_LOAD_NGRi = 159, + SystemZ_ATOMIC_LOAD_NIHF64 = 160, + SystemZ_ATOMIC_LOAD_NIHF64i = 161, + SystemZ_ATOMIC_LOAD_NIHH64 = 162, + SystemZ_ATOMIC_LOAD_NIHH64i = 163, + SystemZ_ATOMIC_LOAD_NIHL64 = 164, + SystemZ_ATOMIC_LOAD_NIHL64i = 165, + SystemZ_ATOMIC_LOAD_NILF = 166, + SystemZ_ATOMIC_LOAD_NILF64 = 167, + SystemZ_ATOMIC_LOAD_NILF64i = 168, + SystemZ_ATOMIC_LOAD_NILFi = 169, + SystemZ_ATOMIC_LOAD_NILH = 170, + SystemZ_ATOMIC_LOAD_NILH64 = 171, + SystemZ_ATOMIC_LOAD_NILH64i = 172, + SystemZ_ATOMIC_LOAD_NILHi = 173, + SystemZ_ATOMIC_LOAD_NILL = 174, + SystemZ_ATOMIC_LOAD_NILL64 = 175, + SystemZ_ATOMIC_LOAD_NILL64i = 176, + SystemZ_ATOMIC_LOAD_NILLi = 177, + SystemZ_ATOMIC_LOAD_NR = 178, + SystemZ_ATOMIC_LOAD_NRi = 179, + SystemZ_ATOMIC_LOAD_OGR = 180, + SystemZ_ATOMIC_LOAD_OIHF64 = 181, + SystemZ_ATOMIC_LOAD_OIHH64 = 182, + SystemZ_ATOMIC_LOAD_OIHL64 = 183, + SystemZ_ATOMIC_LOAD_OILF = 184, + SystemZ_ATOMIC_LOAD_OILF64 = 185, + SystemZ_ATOMIC_LOAD_OILH = 186, + SystemZ_ATOMIC_LOAD_OILH64 = 187, + SystemZ_ATOMIC_LOAD_OILL = 188, + SystemZ_ATOMIC_LOAD_OILL64 = 189, + SystemZ_ATOMIC_LOAD_OR = 190, + SystemZ_ATOMIC_LOAD_SGR = 191, + SystemZ_ATOMIC_LOAD_SR = 192, + SystemZ_ATOMIC_LOAD_UMAX_32 = 193, + SystemZ_ATOMIC_LOAD_UMAX_64 = 194, + SystemZ_ATOMIC_LOAD_UMIN_32 = 195, + SystemZ_ATOMIC_LOAD_UMIN_64 = 196, + SystemZ_ATOMIC_LOAD_XGR = 197, + SystemZ_ATOMIC_LOAD_XIHF64 = 198, + SystemZ_ATOMIC_LOAD_XILF = 199, + SystemZ_ATOMIC_LOAD_XILF64 = 200, + SystemZ_ATOMIC_LOAD_XR = 201, + SystemZ_ATOMIC_SWAPW = 202, + SystemZ_ATOMIC_SWAP_32 = 203, + SystemZ_ATOMIC_SWAP_64 = 204, + SystemZ_CFIMux = 205, + SystemZ_CGIBCall = 206, + SystemZ_CGIBReturn = 207, + SystemZ_CGRBCall = 208, + SystemZ_CGRBReturn = 209, + SystemZ_CHIMux = 210, + SystemZ_CIBCall = 211, + SystemZ_CIBReturn = 212, + SystemZ_CLCLoop = 213, + SystemZ_CLCSequence = 214, + SystemZ_CLFIMux = 215, + SystemZ_CLGIBCall = 216, + SystemZ_CLGIBReturn = 217, + SystemZ_CLGRBCall = 218, + SystemZ_CLGRBReturn = 219, + SystemZ_CLIBCall = 220, + SystemZ_CLIBReturn = 221, + SystemZ_CLMux = 222, + SystemZ_CLRBCall = 223, + SystemZ_CLRBReturn = 224, + SystemZ_CLSTLoop = 225, + SystemZ_CMux = 226, + SystemZ_CRBCall = 227, + SystemZ_CRBReturn = 228, + SystemZ_CallBASR = 229, + SystemZ_CallBCR = 230, + SystemZ_CallBR = 231, + SystemZ_CallBRASL = 232, + SystemZ_CallBRCL = 233, + SystemZ_CallJG = 234, + SystemZ_CondReturn = 235, + SystemZ_CondStore16 = 236, + SystemZ_CondStore16Inv = 237, + SystemZ_CondStore16Mux = 238, + SystemZ_CondStore16MuxInv = 239, + SystemZ_CondStore32 = 240, + SystemZ_CondStore32Inv = 241, + SystemZ_CondStore32Mux = 242, + SystemZ_CondStore32MuxInv = 243, + SystemZ_CondStore64 = 244, + SystemZ_CondStore64Inv = 245, + SystemZ_CondStore8 = 246, + SystemZ_CondStore8Inv = 247, + SystemZ_CondStore8Mux = 248, + SystemZ_CondStore8MuxInv = 249, + SystemZ_CondStoreF32 = 250, + SystemZ_CondStoreF32Inv = 251, + SystemZ_CondStoreF64 = 252, + SystemZ_CondStoreF64Inv = 253, + SystemZ_CondTrap = 254, + SystemZ_GOT = 255, + SystemZ_IIFMux = 256, + SystemZ_IIHF64 = 257, + SystemZ_IIHH64 = 258, + SystemZ_IIHL64 = 259, + SystemZ_IIHMux = 260, + SystemZ_IILF64 = 261, + SystemZ_IILH64 = 262, + SystemZ_IILL64 = 263, + SystemZ_IILMux = 264, + SystemZ_L128 = 265, + SystemZ_LBMux = 266, + SystemZ_LEFR = 267, + SystemZ_LFER = 268, + SystemZ_LHIMux = 269, + SystemZ_LHMux = 270, + SystemZ_LLCMux = 271, + SystemZ_LLCRMux = 272, + SystemZ_LLHMux = 273, + SystemZ_LLHRMux = 274, + SystemZ_LMux = 275, + SystemZ_LOCHIMux = 276, + SystemZ_LOCMux = 277, + SystemZ_LOCRMux = 278, + SystemZ_LRMux = 279, + SystemZ_LTDBRCompare_VecPseudo = 280, + SystemZ_LTEBRCompare_VecPseudo = 281, + SystemZ_LTXBRCompare_VecPseudo = 282, + SystemZ_LX = 283, + SystemZ_MVCLoop = 284, + SystemZ_MVCSequence = 285, + SystemZ_MVSTLoop = 286, + SystemZ_MemBarrier = 287, + SystemZ_NCLoop = 288, + SystemZ_NCSequence = 289, + SystemZ_NIFMux = 290, + SystemZ_NIHF64 = 291, + SystemZ_NIHH64 = 292, + SystemZ_NIHL64 = 293, + SystemZ_NIHMux = 294, + SystemZ_NILF64 = 295, + SystemZ_NILH64 = 296, + SystemZ_NILL64 = 297, + SystemZ_NILMux = 298, + SystemZ_OCLoop = 299, + SystemZ_OCSequence = 300, + SystemZ_OIFMux = 301, + SystemZ_OIHF64 = 302, + SystemZ_OIHH64 = 303, + SystemZ_OIHL64 = 304, + SystemZ_OIHMux = 305, + SystemZ_OILF64 = 306, + SystemZ_OILH64 = 307, + SystemZ_OILL64 = 308, + SystemZ_OILMux = 309, + SystemZ_PAIR128 = 310, + SystemZ_RISBHH = 311, + SystemZ_RISBHL = 312, + SystemZ_RISBLH = 313, + SystemZ_RISBLL = 314, + SystemZ_RISBMux = 315, + SystemZ_Return = 316, + SystemZ_SRSTLoop = 317, + SystemZ_ST128 = 318, + SystemZ_STCMux = 319, + SystemZ_STHMux = 320, + SystemZ_STMux = 321, + SystemZ_STOCMux = 322, + SystemZ_STX = 323, + SystemZ_Select32 = 324, + SystemZ_Select64 = 325, + SystemZ_SelectF128 = 326, + SystemZ_SelectF32 = 327, + SystemZ_SelectF64 = 328, + SystemZ_SelectVR128 = 329, + SystemZ_SelectVR32 = 330, + SystemZ_SelectVR64 = 331, + SystemZ_Serialize = 332, + SystemZ_TBEGIN_nofloat = 333, + SystemZ_TLS_GDCALL = 334, + SystemZ_TLS_LDCALL = 335, + SystemZ_TMHH64 = 336, + SystemZ_TMHL64 = 337, + SystemZ_TMHMux = 338, + SystemZ_TMLH64 = 339, + SystemZ_TMLL64 = 340, + SystemZ_TMLMux = 341, + SystemZ_Trap = 342, + SystemZ_VL32 = 343, + SystemZ_VL64 = 344, + SystemZ_VLR32 = 345, + SystemZ_VLR64 = 346, + SystemZ_VLVGP32 = 347, + SystemZ_VST32 = 348, + SystemZ_VST64 = 349, + SystemZ_XCLoop = 350, + SystemZ_XCSequence = 351, + SystemZ_XIFMux = 352, + SystemZ_XIHF64 = 353, + SystemZ_XILF64 = 354, + SystemZ_ZEXT128 = 355, + SystemZ_A = 356, + SystemZ_AD = 357, + SystemZ_ADB = 358, + SystemZ_ADBR = 359, + SystemZ_ADR = 360, + SystemZ_ADTR = 361, + SystemZ_ADTRA = 362, + SystemZ_AE = 363, + SystemZ_AEB = 364, + SystemZ_AEBR = 365, + SystemZ_AER = 366, + SystemZ_AFI = 367, + SystemZ_AG = 368, + SystemZ_AGF = 369, + SystemZ_AGFI = 370, + SystemZ_AGFR = 371, + SystemZ_AGH = 372, + SystemZ_AGHI = 373, + SystemZ_AGHIK = 374, + SystemZ_AGR = 375, + SystemZ_AGRK = 376, + SystemZ_AGSI = 377, + SystemZ_AH = 378, + SystemZ_AHHHR = 379, + SystemZ_AHHLR = 380, + SystemZ_AHI = 381, + SystemZ_AHIK = 382, + SystemZ_AHY = 383, + SystemZ_AIH = 384, + SystemZ_AL = 385, + SystemZ_ALC = 386, + SystemZ_ALCG = 387, + SystemZ_ALCGR = 388, + SystemZ_ALCR = 389, + SystemZ_ALFI = 390, + SystemZ_ALG = 391, + SystemZ_ALGF = 392, + SystemZ_ALGFI = 393, + SystemZ_ALGFR = 394, + SystemZ_ALGHSIK = 395, + SystemZ_ALGR = 396, + SystemZ_ALGRK = 397, + SystemZ_ALGSI = 398, + SystemZ_ALHHHR = 399, + SystemZ_ALHHLR = 400, + SystemZ_ALHSIK = 401, + SystemZ_ALR = 402, + SystemZ_ALRK = 403, + SystemZ_ALSI = 404, + SystemZ_ALSIH = 405, + SystemZ_ALSIHN = 406, + SystemZ_ALY = 407, + SystemZ_AP = 408, + SystemZ_AR = 409, + SystemZ_ARK = 410, + SystemZ_ASI = 411, + SystemZ_AU = 412, + SystemZ_AUR = 413, + SystemZ_AW = 414, + SystemZ_AWR = 415, + SystemZ_AXBR = 416, + SystemZ_AXR = 417, + SystemZ_AXTR = 418, + SystemZ_AXTRA = 419, + SystemZ_AY = 420, + SystemZ_B = 421, + SystemZ_BAKR = 422, + SystemZ_BAL = 423, + SystemZ_BALR = 424, + SystemZ_BAS = 425, + SystemZ_BASR = 426, + SystemZ_BASSM = 427, + SystemZ_BAsmE = 428, + SystemZ_BAsmH = 429, + SystemZ_BAsmHE = 430, + SystemZ_BAsmL = 431, + SystemZ_BAsmLE = 432, + SystemZ_BAsmLH = 433, + SystemZ_BAsmM = 434, + SystemZ_BAsmNE = 435, + SystemZ_BAsmNH = 436, + SystemZ_BAsmNHE = 437, + SystemZ_BAsmNL = 438, + SystemZ_BAsmNLE = 439, + SystemZ_BAsmNLH = 440, + SystemZ_BAsmNM = 441, + SystemZ_BAsmNO = 442, + SystemZ_BAsmNP = 443, + SystemZ_BAsmNZ = 444, + SystemZ_BAsmO = 445, + SystemZ_BAsmP = 446, + SystemZ_BAsmZ = 447, + SystemZ_BC = 448, + SystemZ_BCAsm = 449, + SystemZ_BCR = 450, + SystemZ_BCRAsm = 451, + SystemZ_BCT = 452, + SystemZ_BCTG = 453, + SystemZ_BCTGR = 454, + SystemZ_BCTR = 455, + SystemZ_BI = 456, + SystemZ_BIAsmE = 457, + SystemZ_BIAsmH = 458, + SystemZ_BIAsmHE = 459, + SystemZ_BIAsmL = 460, + SystemZ_BIAsmLE = 461, + SystemZ_BIAsmLH = 462, + SystemZ_BIAsmM = 463, + SystemZ_BIAsmNE = 464, + SystemZ_BIAsmNH = 465, + SystemZ_BIAsmNHE = 466, + SystemZ_BIAsmNL = 467, + SystemZ_BIAsmNLE = 468, + SystemZ_BIAsmNLH = 469, + SystemZ_BIAsmNM = 470, + SystemZ_BIAsmNO = 471, + SystemZ_BIAsmNP = 472, + SystemZ_BIAsmNZ = 473, + SystemZ_BIAsmO = 474, + SystemZ_BIAsmP = 475, + SystemZ_BIAsmZ = 476, + SystemZ_BIC = 477, + SystemZ_BICAsm = 478, + SystemZ_BPP = 479, + SystemZ_BPRP = 480, + SystemZ_BR = 481, + SystemZ_BRAS = 482, + SystemZ_BRASL = 483, + SystemZ_BRAsmE = 484, + SystemZ_BRAsmH = 485, + SystemZ_BRAsmHE = 486, + SystemZ_BRAsmL = 487, + SystemZ_BRAsmLE = 488, + SystemZ_BRAsmLH = 489, + SystemZ_BRAsmM = 490, + SystemZ_BRAsmNE = 491, + SystemZ_BRAsmNH = 492, + SystemZ_BRAsmNHE = 493, + SystemZ_BRAsmNL = 494, + SystemZ_BRAsmNLE = 495, + SystemZ_BRAsmNLH = 496, + SystemZ_BRAsmNM = 497, + SystemZ_BRAsmNO = 498, + SystemZ_BRAsmNP = 499, + SystemZ_BRAsmNZ = 500, + SystemZ_BRAsmO = 501, + SystemZ_BRAsmP = 502, + SystemZ_BRAsmZ = 503, + SystemZ_BRC = 504, + SystemZ_BRCAsm = 505, + SystemZ_BRCL = 506, + SystemZ_BRCLAsm = 507, + SystemZ_BRCT = 508, + SystemZ_BRCTG = 509, + SystemZ_BRCTH = 510, + SystemZ_BRXH = 511, + SystemZ_BRXHG = 512, + SystemZ_BRXLE = 513, + SystemZ_BRXLG = 514, + SystemZ_BSA = 515, + SystemZ_BSG = 516, + SystemZ_BSM = 517, + SystemZ_BXH = 518, + SystemZ_BXHG = 519, + SystemZ_BXLE = 520, + SystemZ_BXLEG = 521, + SystemZ_C = 522, + SystemZ_CD = 523, + SystemZ_CDB = 524, + SystemZ_CDBR = 525, + SystemZ_CDFBR = 526, + SystemZ_CDFBRA = 527, + SystemZ_CDFR = 528, + SystemZ_CDFTR = 529, + SystemZ_CDGBR = 530, + SystemZ_CDGBRA = 531, + SystemZ_CDGR = 532, + SystemZ_CDGTR = 533, + SystemZ_CDGTRA = 534, + SystemZ_CDLFBR = 535, + SystemZ_CDLFTR = 536, + SystemZ_CDLGBR = 537, + SystemZ_CDLGTR = 538, + SystemZ_CDPT = 539, + SystemZ_CDR = 540, + SystemZ_CDS = 541, + SystemZ_CDSG = 542, + SystemZ_CDSTR = 543, + SystemZ_CDSY = 544, + SystemZ_CDTR = 545, + SystemZ_CDUTR = 546, + SystemZ_CDZT = 547, + SystemZ_CE = 548, + SystemZ_CEB = 549, + SystemZ_CEBR = 550, + SystemZ_CEDTR = 551, + SystemZ_CEFBR = 552, + SystemZ_CEFBRA = 553, + SystemZ_CEFR = 554, + SystemZ_CEGBR = 555, + SystemZ_CEGBRA = 556, + SystemZ_CEGR = 557, + SystemZ_CELFBR = 558, + SystemZ_CELGBR = 559, + SystemZ_CER = 560, + SystemZ_CEXTR = 561, + SystemZ_CFC = 562, + SystemZ_CFDBR = 563, + SystemZ_CFDBRA = 564, + SystemZ_CFDR = 565, + SystemZ_CFDTR = 566, + SystemZ_CFEBR = 567, + SystemZ_CFEBRA = 568, + SystemZ_CFER = 569, + SystemZ_CFI = 570, + SystemZ_CFXBR = 571, + SystemZ_CFXBRA = 572, + SystemZ_CFXR = 573, + SystemZ_CFXTR = 574, + SystemZ_CG = 575, + SystemZ_CGDBR = 576, + SystemZ_CGDBRA = 577, + SystemZ_CGDR = 578, + SystemZ_CGDTR = 579, + SystemZ_CGDTRA = 580, + SystemZ_CGEBR = 581, + SystemZ_CGEBRA = 582, + SystemZ_CGER = 583, + SystemZ_CGF = 584, + SystemZ_CGFI = 585, + SystemZ_CGFR = 586, + SystemZ_CGFRL = 587, + SystemZ_CGH = 588, + SystemZ_CGHI = 589, + SystemZ_CGHRL = 590, + SystemZ_CGHSI = 591, + SystemZ_CGIB = 592, + SystemZ_CGIBAsm = 593, + SystemZ_CGIBAsmE = 594, + SystemZ_CGIBAsmH = 595, + SystemZ_CGIBAsmHE = 596, + SystemZ_CGIBAsmL = 597, + SystemZ_CGIBAsmLE = 598, + SystemZ_CGIBAsmLH = 599, + SystemZ_CGIBAsmNE = 600, + SystemZ_CGIBAsmNH = 601, + SystemZ_CGIBAsmNHE = 602, + SystemZ_CGIBAsmNL = 603, + SystemZ_CGIBAsmNLE = 604, + SystemZ_CGIBAsmNLH = 605, + SystemZ_CGIJ = 606, + SystemZ_CGIJAsm = 607, + SystemZ_CGIJAsmE = 608, + SystemZ_CGIJAsmH = 609, + SystemZ_CGIJAsmHE = 610, + SystemZ_CGIJAsmL = 611, + SystemZ_CGIJAsmLE = 612, + SystemZ_CGIJAsmLH = 613, + SystemZ_CGIJAsmNE = 614, + SystemZ_CGIJAsmNH = 615, + SystemZ_CGIJAsmNHE = 616, + SystemZ_CGIJAsmNL = 617, + SystemZ_CGIJAsmNLE = 618, + SystemZ_CGIJAsmNLH = 619, + SystemZ_CGIT = 620, + SystemZ_CGITAsm = 621, + SystemZ_CGITAsmE = 622, + SystemZ_CGITAsmH = 623, + SystemZ_CGITAsmHE = 624, + SystemZ_CGITAsmL = 625, + SystemZ_CGITAsmLE = 626, + SystemZ_CGITAsmLH = 627, + SystemZ_CGITAsmNE = 628, + SystemZ_CGITAsmNH = 629, + SystemZ_CGITAsmNHE = 630, + SystemZ_CGITAsmNL = 631, + SystemZ_CGITAsmNLE = 632, + SystemZ_CGITAsmNLH = 633, + SystemZ_CGR = 634, + SystemZ_CGRB = 635, + SystemZ_CGRBAsm = 636, + SystemZ_CGRBAsmE = 637, + SystemZ_CGRBAsmH = 638, + SystemZ_CGRBAsmHE = 639, + SystemZ_CGRBAsmL = 640, + SystemZ_CGRBAsmLE = 641, + SystemZ_CGRBAsmLH = 642, + SystemZ_CGRBAsmNE = 643, + SystemZ_CGRBAsmNH = 644, + SystemZ_CGRBAsmNHE = 645, + SystemZ_CGRBAsmNL = 646, + SystemZ_CGRBAsmNLE = 647, + SystemZ_CGRBAsmNLH = 648, + SystemZ_CGRJ = 649, + SystemZ_CGRJAsm = 650, + SystemZ_CGRJAsmE = 651, + SystemZ_CGRJAsmH = 652, + SystemZ_CGRJAsmHE = 653, + SystemZ_CGRJAsmL = 654, + SystemZ_CGRJAsmLE = 655, + SystemZ_CGRJAsmLH = 656, + SystemZ_CGRJAsmNE = 657, + SystemZ_CGRJAsmNH = 658, + SystemZ_CGRJAsmNHE = 659, + SystemZ_CGRJAsmNL = 660, + SystemZ_CGRJAsmNLE = 661, + SystemZ_CGRJAsmNLH = 662, + SystemZ_CGRL = 663, + SystemZ_CGRT = 664, + SystemZ_CGRTAsm = 665, + SystemZ_CGRTAsmE = 666, + SystemZ_CGRTAsmH = 667, + SystemZ_CGRTAsmHE = 668, + SystemZ_CGRTAsmL = 669, + SystemZ_CGRTAsmLE = 670, + SystemZ_CGRTAsmLH = 671, + SystemZ_CGRTAsmNE = 672, + SystemZ_CGRTAsmNH = 673, + SystemZ_CGRTAsmNHE = 674, + SystemZ_CGRTAsmNL = 675, + SystemZ_CGRTAsmNLE = 676, + SystemZ_CGRTAsmNLH = 677, + SystemZ_CGXBR = 678, + SystemZ_CGXBRA = 679, + SystemZ_CGXR = 680, + SystemZ_CGXTR = 681, + SystemZ_CGXTRA = 682, + SystemZ_CH = 683, + SystemZ_CHF = 684, + SystemZ_CHHR = 685, + SystemZ_CHHSI = 686, + SystemZ_CHI = 687, + SystemZ_CHLR = 688, + SystemZ_CHRL = 689, + SystemZ_CHSI = 690, + SystemZ_CHY = 691, + SystemZ_CIB = 692, + SystemZ_CIBAsm = 693, + SystemZ_CIBAsmE = 694, + SystemZ_CIBAsmH = 695, + SystemZ_CIBAsmHE = 696, + SystemZ_CIBAsmL = 697, + SystemZ_CIBAsmLE = 698, + SystemZ_CIBAsmLH = 699, + SystemZ_CIBAsmNE = 700, + SystemZ_CIBAsmNH = 701, + SystemZ_CIBAsmNHE = 702, + SystemZ_CIBAsmNL = 703, + SystemZ_CIBAsmNLE = 704, + SystemZ_CIBAsmNLH = 705, + SystemZ_CIH = 706, + SystemZ_CIJ = 707, + SystemZ_CIJAsm = 708, + SystemZ_CIJAsmE = 709, + SystemZ_CIJAsmH = 710, + SystemZ_CIJAsmHE = 711, + SystemZ_CIJAsmL = 712, + SystemZ_CIJAsmLE = 713, + SystemZ_CIJAsmLH = 714, + SystemZ_CIJAsmNE = 715, + SystemZ_CIJAsmNH = 716, + SystemZ_CIJAsmNHE = 717, + SystemZ_CIJAsmNL = 718, + SystemZ_CIJAsmNLE = 719, + SystemZ_CIJAsmNLH = 720, + SystemZ_CIT = 721, + SystemZ_CITAsm = 722, + SystemZ_CITAsmE = 723, + SystemZ_CITAsmH = 724, + SystemZ_CITAsmHE = 725, + SystemZ_CITAsmL = 726, + SystemZ_CITAsmLE = 727, + SystemZ_CITAsmLH = 728, + SystemZ_CITAsmNE = 729, + SystemZ_CITAsmNH = 730, + SystemZ_CITAsmNHE = 731, + SystemZ_CITAsmNL = 732, + SystemZ_CITAsmNLE = 733, + SystemZ_CITAsmNLH = 734, + SystemZ_CKSM = 735, + SystemZ_CL = 736, + SystemZ_CLC = 737, + SystemZ_CLCL = 738, + SystemZ_CLCLE = 739, + SystemZ_CLCLU = 740, + SystemZ_CLFDBR = 741, + SystemZ_CLFDTR = 742, + SystemZ_CLFEBR = 743, + SystemZ_CLFHSI = 744, + SystemZ_CLFI = 745, + SystemZ_CLFIT = 746, + SystemZ_CLFITAsm = 747, + SystemZ_CLFITAsmE = 748, + SystemZ_CLFITAsmH = 749, + SystemZ_CLFITAsmHE = 750, + SystemZ_CLFITAsmL = 751, + SystemZ_CLFITAsmLE = 752, + SystemZ_CLFITAsmLH = 753, + SystemZ_CLFITAsmNE = 754, + SystemZ_CLFITAsmNH = 755, + SystemZ_CLFITAsmNHE = 756, + SystemZ_CLFITAsmNL = 757, + SystemZ_CLFITAsmNLE = 758, + SystemZ_CLFITAsmNLH = 759, + SystemZ_CLFXBR = 760, + SystemZ_CLFXTR = 761, + SystemZ_CLG = 762, + SystemZ_CLGDBR = 763, + SystemZ_CLGDTR = 764, + SystemZ_CLGEBR = 765, + SystemZ_CLGF = 766, + SystemZ_CLGFI = 767, + SystemZ_CLGFR = 768, + SystemZ_CLGFRL = 769, + SystemZ_CLGHRL = 770, + SystemZ_CLGHSI = 771, + SystemZ_CLGIB = 772, + SystemZ_CLGIBAsm = 773, + SystemZ_CLGIBAsmE = 774, + SystemZ_CLGIBAsmH = 775, + SystemZ_CLGIBAsmHE = 776, + SystemZ_CLGIBAsmL = 777, + SystemZ_CLGIBAsmLE = 778, + SystemZ_CLGIBAsmLH = 779, + SystemZ_CLGIBAsmNE = 780, + SystemZ_CLGIBAsmNH = 781, + SystemZ_CLGIBAsmNHE = 782, + SystemZ_CLGIBAsmNL = 783, + SystemZ_CLGIBAsmNLE = 784, + SystemZ_CLGIBAsmNLH = 785, + SystemZ_CLGIJ = 786, + SystemZ_CLGIJAsm = 787, + SystemZ_CLGIJAsmE = 788, + SystemZ_CLGIJAsmH = 789, + SystemZ_CLGIJAsmHE = 790, + SystemZ_CLGIJAsmL = 791, + SystemZ_CLGIJAsmLE = 792, + SystemZ_CLGIJAsmLH = 793, + SystemZ_CLGIJAsmNE = 794, + SystemZ_CLGIJAsmNH = 795, + SystemZ_CLGIJAsmNHE = 796, + SystemZ_CLGIJAsmNL = 797, + SystemZ_CLGIJAsmNLE = 798, + SystemZ_CLGIJAsmNLH = 799, + SystemZ_CLGIT = 800, + SystemZ_CLGITAsm = 801, + SystemZ_CLGITAsmE = 802, + SystemZ_CLGITAsmH = 803, + SystemZ_CLGITAsmHE = 804, + SystemZ_CLGITAsmL = 805, + SystemZ_CLGITAsmLE = 806, + SystemZ_CLGITAsmLH = 807, + SystemZ_CLGITAsmNE = 808, + SystemZ_CLGITAsmNH = 809, + SystemZ_CLGITAsmNHE = 810, + SystemZ_CLGITAsmNL = 811, + SystemZ_CLGITAsmNLE = 812, + SystemZ_CLGITAsmNLH = 813, + SystemZ_CLGR = 814, + SystemZ_CLGRB = 815, + SystemZ_CLGRBAsm = 816, + SystemZ_CLGRBAsmE = 817, + SystemZ_CLGRBAsmH = 818, + SystemZ_CLGRBAsmHE = 819, + SystemZ_CLGRBAsmL = 820, + SystemZ_CLGRBAsmLE = 821, + SystemZ_CLGRBAsmLH = 822, + SystemZ_CLGRBAsmNE = 823, + SystemZ_CLGRBAsmNH = 824, + SystemZ_CLGRBAsmNHE = 825, + SystemZ_CLGRBAsmNL = 826, + SystemZ_CLGRBAsmNLE = 827, + SystemZ_CLGRBAsmNLH = 828, + SystemZ_CLGRJ = 829, + SystemZ_CLGRJAsm = 830, + SystemZ_CLGRJAsmE = 831, + SystemZ_CLGRJAsmH = 832, + SystemZ_CLGRJAsmHE = 833, + SystemZ_CLGRJAsmL = 834, + SystemZ_CLGRJAsmLE = 835, + SystemZ_CLGRJAsmLH = 836, + SystemZ_CLGRJAsmNE = 837, + SystemZ_CLGRJAsmNH = 838, + SystemZ_CLGRJAsmNHE = 839, + SystemZ_CLGRJAsmNL = 840, + SystemZ_CLGRJAsmNLE = 841, + SystemZ_CLGRJAsmNLH = 842, + SystemZ_CLGRL = 843, + SystemZ_CLGRT = 844, + SystemZ_CLGRTAsm = 845, + SystemZ_CLGRTAsmE = 846, + SystemZ_CLGRTAsmH = 847, + SystemZ_CLGRTAsmHE = 848, + SystemZ_CLGRTAsmL = 849, + SystemZ_CLGRTAsmLE = 850, + SystemZ_CLGRTAsmLH = 851, + SystemZ_CLGRTAsmNE = 852, + SystemZ_CLGRTAsmNH = 853, + SystemZ_CLGRTAsmNHE = 854, + SystemZ_CLGRTAsmNL = 855, + SystemZ_CLGRTAsmNLE = 856, + SystemZ_CLGRTAsmNLH = 857, + SystemZ_CLGT = 858, + SystemZ_CLGTAsm = 859, + SystemZ_CLGTAsmE = 860, + SystemZ_CLGTAsmH = 861, + SystemZ_CLGTAsmHE = 862, + SystemZ_CLGTAsmL = 863, + SystemZ_CLGTAsmLE = 864, + SystemZ_CLGTAsmLH = 865, + SystemZ_CLGTAsmNE = 866, + SystemZ_CLGTAsmNH = 867, + SystemZ_CLGTAsmNHE = 868, + SystemZ_CLGTAsmNL = 869, + SystemZ_CLGTAsmNLE = 870, + SystemZ_CLGTAsmNLH = 871, + SystemZ_CLGXBR = 872, + SystemZ_CLGXTR = 873, + SystemZ_CLHF = 874, + SystemZ_CLHHR = 875, + SystemZ_CLHHSI = 876, + SystemZ_CLHLR = 877, + SystemZ_CLHRL = 878, + SystemZ_CLI = 879, + SystemZ_CLIB = 880, + SystemZ_CLIBAsm = 881, + SystemZ_CLIBAsmE = 882, + SystemZ_CLIBAsmH = 883, + SystemZ_CLIBAsmHE = 884, + SystemZ_CLIBAsmL = 885, + SystemZ_CLIBAsmLE = 886, + SystemZ_CLIBAsmLH = 887, + SystemZ_CLIBAsmNE = 888, + SystemZ_CLIBAsmNH = 889, + SystemZ_CLIBAsmNHE = 890, + SystemZ_CLIBAsmNL = 891, + SystemZ_CLIBAsmNLE = 892, + SystemZ_CLIBAsmNLH = 893, + SystemZ_CLIH = 894, + SystemZ_CLIJ = 895, + SystemZ_CLIJAsm = 896, + SystemZ_CLIJAsmE = 897, + SystemZ_CLIJAsmH = 898, + SystemZ_CLIJAsmHE = 899, + SystemZ_CLIJAsmL = 900, + SystemZ_CLIJAsmLE = 901, + SystemZ_CLIJAsmLH = 902, + SystemZ_CLIJAsmNE = 903, + SystemZ_CLIJAsmNH = 904, + SystemZ_CLIJAsmNHE = 905, + SystemZ_CLIJAsmNL = 906, + SystemZ_CLIJAsmNLE = 907, + SystemZ_CLIJAsmNLH = 908, + SystemZ_CLIY = 909, + SystemZ_CLM = 910, + SystemZ_CLMH = 911, + SystemZ_CLMY = 912, + SystemZ_CLR = 913, + SystemZ_CLRB = 914, + SystemZ_CLRBAsm = 915, + SystemZ_CLRBAsmE = 916, + SystemZ_CLRBAsmH = 917, + SystemZ_CLRBAsmHE = 918, + SystemZ_CLRBAsmL = 919, + SystemZ_CLRBAsmLE = 920, + SystemZ_CLRBAsmLH = 921, + SystemZ_CLRBAsmNE = 922, + SystemZ_CLRBAsmNH = 923, + SystemZ_CLRBAsmNHE = 924, + SystemZ_CLRBAsmNL = 925, + SystemZ_CLRBAsmNLE = 926, + SystemZ_CLRBAsmNLH = 927, + SystemZ_CLRJ = 928, + SystemZ_CLRJAsm = 929, + SystemZ_CLRJAsmE = 930, + SystemZ_CLRJAsmH = 931, + SystemZ_CLRJAsmHE = 932, + SystemZ_CLRJAsmL = 933, + SystemZ_CLRJAsmLE = 934, + SystemZ_CLRJAsmLH = 935, + SystemZ_CLRJAsmNE = 936, + SystemZ_CLRJAsmNH = 937, + SystemZ_CLRJAsmNHE = 938, + SystemZ_CLRJAsmNL = 939, + SystemZ_CLRJAsmNLE = 940, + SystemZ_CLRJAsmNLH = 941, + SystemZ_CLRL = 942, + SystemZ_CLRT = 943, + SystemZ_CLRTAsm = 944, + SystemZ_CLRTAsmE = 945, + SystemZ_CLRTAsmH = 946, + SystemZ_CLRTAsmHE = 947, + SystemZ_CLRTAsmL = 948, + SystemZ_CLRTAsmLE = 949, + SystemZ_CLRTAsmLH = 950, + SystemZ_CLRTAsmNE = 951, + SystemZ_CLRTAsmNH = 952, + SystemZ_CLRTAsmNHE = 953, + SystemZ_CLRTAsmNL = 954, + SystemZ_CLRTAsmNLE = 955, + SystemZ_CLRTAsmNLH = 956, + SystemZ_CLST = 957, + SystemZ_CLT = 958, + SystemZ_CLTAsm = 959, + SystemZ_CLTAsmE = 960, + SystemZ_CLTAsmH = 961, + SystemZ_CLTAsmHE = 962, + SystemZ_CLTAsmL = 963, + SystemZ_CLTAsmLE = 964, + SystemZ_CLTAsmLH = 965, + SystemZ_CLTAsmNE = 966, + SystemZ_CLTAsmNH = 967, + SystemZ_CLTAsmNHE = 968, + SystemZ_CLTAsmNL = 969, + SystemZ_CLTAsmNLE = 970, + SystemZ_CLTAsmNLH = 971, + SystemZ_CLY = 972, + SystemZ_CMPSC = 973, + SystemZ_CP = 974, + SystemZ_CPDT = 975, + SystemZ_CPSDRdd = 976, + SystemZ_CPSDRds = 977, + SystemZ_CPSDRsd = 978, + SystemZ_CPSDRss = 979, + SystemZ_CPXT = 980, + SystemZ_CPYA = 981, + SystemZ_CR = 982, + SystemZ_CRB = 983, + SystemZ_CRBAsm = 984, + SystemZ_CRBAsmE = 985, + SystemZ_CRBAsmH = 986, + SystemZ_CRBAsmHE = 987, + SystemZ_CRBAsmL = 988, + SystemZ_CRBAsmLE = 989, + SystemZ_CRBAsmLH = 990, + SystemZ_CRBAsmNE = 991, + SystemZ_CRBAsmNH = 992, + SystemZ_CRBAsmNHE = 993, + SystemZ_CRBAsmNL = 994, + SystemZ_CRBAsmNLE = 995, + SystemZ_CRBAsmNLH = 996, + SystemZ_CRDTE = 997, + SystemZ_CRDTEOpt = 998, + SystemZ_CRJ = 999, + SystemZ_CRJAsm = 1000, + SystemZ_CRJAsmE = 1001, + SystemZ_CRJAsmH = 1002, + SystemZ_CRJAsmHE = 1003, + SystemZ_CRJAsmL = 1004, + SystemZ_CRJAsmLE = 1005, + SystemZ_CRJAsmLH = 1006, + SystemZ_CRJAsmNE = 1007, + SystemZ_CRJAsmNH = 1008, + SystemZ_CRJAsmNHE = 1009, + SystemZ_CRJAsmNL = 1010, + SystemZ_CRJAsmNLE = 1011, + SystemZ_CRJAsmNLH = 1012, + SystemZ_CRL = 1013, + SystemZ_CRT = 1014, + SystemZ_CRTAsm = 1015, + SystemZ_CRTAsmE = 1016, + SystemZ_CRTAsmH = 1017, + SystemZ_CRTAsmHE = 1018, + SystemZ_CRTAsmL = 1019, + SystemZ_CRTAsmLE = 1020, + SystemZ_CRTAsmLH = 1021, + SystemZ_CRTAsmNE = 1022, + SystemZ_CRTAsmNH = 1023, + SystemZ_CRTAsmNHE = 1024, + SystemZ_CRTAsmNL = 1025, + SystemZ_CRTAsmNLE = 1026, + SystemZ_CRTAsmNLH = 1027, + SystemZ_CS = 1028, + SystemZ_CSCH = 1029, + SystemZ_CSDTR = 1030, + SystemZ_CSG = 1031, + SystemZ_CSP = 1032, + SystemZ_CSPG = 1033, + SystemZ_CSST = 1034, + SystemZ_CSXTR = 1035, + SystemZ_CSY = 1036, + SystemZ_CU12 = 1037, + SystemZ_CU12Opt = 1038, + SystemZ_CU14 = 1039, + SystemZ_CU14Opt = 1040, + SystemZ_CU21 = 1041, + SystemZ_CU21Opt = 1042, + SystemZ_CU24 = 1043, + SystemZ_CU24Opt = 1044, + SystemZ_CU41 = 1045, + SystemZ_CU42 = 1046, + SystemZ_CUDTR = 1047, + SystemZ_CUSE = 1048, + SystemZ_CUTFU = 1049, + SystemZ_CUTFUOpt = 1050, + SystemZ_CUUTF = 1051, + SystemZ_CUUTFOpt = 1052, + SystemZ_CUXTR = 1053, + SystemZ_CVB = 1054, + SystemZ_CVBG = 1055, + SystemZ_CVBY = 1056, + SystemZ_CVD = 1057, + SystemZ_CVDG = 1058, + SystemZ_CVDY = 1059, + SystemZ_CXBR = 1060, + SystemZ_CXFBR = 1061, + SystemZ_CXFBRA = 1062, + SystemZ_CXFR = 1063, + SystemZ_CXFTR = 1064, + SystemZ_CXGBR = 1065, + SystemZ_CXGBRA = 1066, + SystemZ_CXGR = 1067, + SystemZ_CXGTR = 1068, + SystemZ_CXGTRA = 1069, + SystemZ_CXLFBR = 1070, + SystemZ_CXLFTR = 1071, + SystemZ_CXLGBR = 1072, + SystemZ_CXLGTR = 1073, + SystemZ_CXPT = 1074, + SystemZ_CXR = 1075, + SystemZ_CXSTR = 1076, + SystemZ_CXTR = 1077, + SystemZ_CXUTR = 1078, + SystemZ_CXZT = 1079, + SystemZ_CY = 1080, + SystemZ_CZDT = 1081, + SystemZ_CZXT = 1082, + SystemZ_D = 1083, + SystemZ_DD = 1084, + SystemZ_DDB = 1085, + SystemZ_DDBR = 1086, + SystemZ_DDR = 1087, + SystemZ_DDTR = 1088, + SystemZ_DDTRA = 1089, + SystemZ_DE = 1090, + SystemZ_DEB = 1091, + SystemZ_DEBR = 1092, + SystemZ_DER = 1093, + SystemZ_DIAG = 1094, + SystemZ_DIDBR = 1095, + SystemZ_DIEBR = 1096, + SystemZ_DL = 1097, + SystemZ_DLG = 1098, + SystemZ_DLGR = 1099, + SystemZ_DLR = 1100, + SystemZ_DP = 1101, + SystemZ_DR = 1102, + SystemZ_DSG = 1103, + SystemZ_DSGF = 1104, + SystemZ_DSGFR = 1105, + SystemZ_DSGR = 1106, + SystemZ_DXBR = 1107, + SystemZ_DXR = 1108, + SystemZ_DXTR = 1109, + SystemZ_DXTRA = 1110, + SystemZ_EAR = 1111, + SystemZ_ECAG = 1112, + SystemZ_ECCTR = 1113, + SystemZ_ECPGA = 1114, + SystemZ_ECTG = 1115, + SystemZ_ED = 1116, + SystemZ_EDMK = 1117, + SystemZ_EEDTR = 1118, + SystemZ_EEXTR = 1119, + SystemZ_EFPC = 1120, + SystemZ_EPAIR = 1121, + SystemZ_EPAR = 1122, + SystemZ_EPCTR = 1123, + SystemZ_EPSW = 1124, + SystemZ_EREG = 1125, + SystemZ_EREGG = 1126, + SystemZ_ESAIR = 1127, + SystemZ_ESAR = 1128, + SystemZ_ESDTR = 1129, + SystemZ_ESEA = 1130, + SystemZ_ESTA = 1131, + SystemZ_ESXTR = 1132, + SystemZ_ETND = 1133, + SystemZ_EX = 1134, + SystemZ_EXRL = 1135, + SystemZ_FIDBR = 1136, + SystemZ_FIDBRA = 1137, + SystemZ_FIDR = 1138, + SystemZ_FIDTR = 1139, + SystemZ_FIEBR = 1140, + SystemZ_FIEBRA = 1141, + SystemZ_FIER = 1142, + SystemZ_FIXBR = 1143, + SystemZ_FIXBRA = 1144, + SystemZ_FIXR = 1145, + SystemZ_FIXTR = 1146, + SystemZ_FLOGR = 1147, + SystemZ_HDR = 1148, + SystemZ_HER = 1149, + SystemZ_HSCH = 1150, + SystemZ_IAC = 1151, + SystemZ_IC = 1152, + SystemZ_IC32 = 1153, + SystemZ_IC32Y = 1154, + SystemZ_ICM = 1155, + SystemZ_ICMH = 1156, + SystemZ_ICMY = 1157, + SystemZ_ICY = 1158, + SystemZ_IDTE = 1159, + SystemZ_IDTEOpt = 1160, + SystemZ_IEDTR = 1161, + SystemZ_IEXTR = 1162, + SystemZ_IIHF = 1163, + SystemZ_IIHH = 1164, + SystemZ_IIHL = 1165, + SystemZ_IILF = 1166, + SystemZ_IILH = 1167, + SystemZ_IILL = 1168, + SystemZ_IPK = 1169, + SystemZ_IPM = 1170, + SystemZ_IPTE = 1171, + SystemZ_IPTEOpt = 1172, + SystemZ_IPTEOptOpt = 1173, + SystemZ_IRBM = 1174, + SystemZ_ISKE = 1175, + SystemZ_IVSK = 1176, + SystemZ_InsnE = 1177, + SystemZ_InsnRI = 1178, + SystemZ_InsnRIE = 1179, + SystemZ_InsnRIL = 1180, + SystemZ_InsnRILU = 1181, + SystemZ_InsnRIS = 1182, + SystemZ_InsnRR = 1183, + SystemZ_InsnRRE = 1184, + SystemZ_InsnRRF = 1185, + SystemZ_InsnRRS = 1186, + SystemZ_InsnRS = 1187, + SystemZ_InsnRSE = 1188, + SystemZ_InsnRSI = 1189, + SystemZ_InsnRSY = 1190, + SystemZ_InsnRX = 1191, + SystemZ_InsnRXE = 1192, + SystemZ_InsnRXF = 1193, + SystemZ_InsnRXY = 1194, + SystemZ_InsnS = 1195, + SystemZ_InsnSI = 1196, + SystemZ_InsnSIL = 1197, + SystemZ_InsnSIY = 1198, + SystemZ_InsnSS = 1199, + SystemZ_InsnSSE = 1200, + SystemZ_InsnSSF = 1201, + SystemZ_J = 1202, + SystemZ_JAsmE = 1203, + SystemZ_JAsmH = 1204, + SystemZ_JAsmHE = 1205, + SystemZ_JAsmL = 1206, + SystemZ_JAsmLE = 1207, + SystemZ_JAsmLH = 1208, + SystemZ_JAsmM = 1209, + SystemZ_JAsmNE = 1210, + SystemZ_JAsmNH = 1211, + SystemZ_JAsmNHE = 1212, + SystemZ_JAsmNL = 1213, + SystemZ_JAsmNLE = 1214, + SystemZ_JAsmNLH = 1215, + SystemZ_JAsmNM = 1216, + SystemZ_JAsmNO = 1217, + SystemZ_JAsmNP = 1218, + SystemZ_JAsmNZ = 1219, + SystemZ_JAsmO = 1220, + SystemZ_JAsmP = 1221, + SystemZ_JAsmZ = 1222, + SystemZ_JG = 1223, + SystemZ_JGAsmE = 1224, + SystemZ_JGAsmH = 1225, + SystemZ_JGAsmHE = 1226, + SystemZ_JGAsmL = 1227, + SystemZ_JGAsmLE = 1228, + SystemZ_JGAsmLH = 1229, + SystemZ_JGAsmM = 1230, + SystemZ_JGAsmNE = 1231, + SystemZ_JGAsmNH = 1232, + SystemZ_JGAsmNHE = 1233, + SystemZ_JGAsmNL = 1234, + SystemZ_JGAsmNLE = 1235, + SystemZ_JGAsmNLH = 1236, + SystemZ_JGAsmNM = 1237, + SystemZ_JGAsmNO = 1238, + SystemZ_JGAsmNP = 1239, + SystemZ_JGAsmNZ = 1240, + SystemZ_JGAsmO = 1241, + SystemZ_JGAsmP = 1242, + SystemZ_JGAsmZ = 1243, + SystemZ_KDB = 1244, + SystemZ_KDBR = 1245, + SystemZ_KDTR = 1246, + SystemZ_KEB = 1247, + SystemZ_KEBR = 1248, + SystemZ_KIMD = 1249, + SystemZ_KLMD = 1250, + SystemZ_KM = 1251, + SystemZ_KMA = 1252, + SystemZ_KMAC = 1253, + SystemZ_KMC = 1254, + SystemZ_KMCTR = 1255, + SystemZ_KMF = 1256, + SystemZ_KMO = 1257, + SystemZ_KXBR = 1258, + SystemZ_KXTR = 1259, + SystemZ_L = 1260, + SystemZ_LA = 1261, + SystemZ_LAA = 1262, + SystemZ_LAAG = 1263, + SystemZ_LAAL = 1264, + SystemZ_LAALG = 1265, + SystemZ_LAE = 1266, + SystemZ_LAEY = 1267, + SystemZ_LAM = 1268, + SystemZ_LAMY = 1269, + SystemZ_LAN = 1270, + SystemZ_LANG = 1271, + SystemZ_LAO = 1272, + SystemZ_LAOG = 1273, + SystemZ_LARL = 1274, + SystemZ_LASP = 1275, + SystemZ_LAT = 1276, + SystemZ_LAX = 1277, + SystemZ_LAXG = 1278, + SystemZ_LAY = 1279, + SystemZ_LB = 1280, + SystemZ_LBH = 1281, + SystemZ_LBR = 1282, + SystemZ_LCBB = 1283, + SystemZ_LCCTL = 1284, + SystemZ_LCDBR = 1285, + SystemZ_LCDFR = 1286, + SystemZ_LCDFR_32 = 1287, + SystemZ_LCDR = 1288, + SystemZ_LCEBR = 1289, + SystemZ_LCER = 1290, + SystemZ_LCGFR = 1291, + SystemZ_LCGR = 1292, + SystemZ_LCR = 1293, + SystemZ_LCTL = 1294, + SystemZ_LCTLG = 1295, + SystemZ_LCXBR = 1296, + SystemZ_LCXR = 1297, + SystemZ_LD = 1298, + SystemZ_LDE = 1299, + SystemZ_LDE32 = 1300, + SystemZ_LDEB = 1301, + SystemZ_LDEBR = 1302, + SystemZ_LDER = 1303, + SystemZ_LDETR = 1304, + SystemZ_LDGR = 1305, + SystemZ_LDR = 1306, + SystemZ_LDR32 = 1307, + SystemZ_LDXBR = 1308, + SystemZ_LDXBRA = 1309, + SystemZ_LDXR = 1310, + SystemZ_LDXTR = 1311, + SystemZ_LDY = 1312, + SystemZ_LE = 1313, + SystemZ_LEDBR = 1314, + SystemZ_LEDBRA = 1315, + SystemZ_LEDR = 1316, + SystemZ_LEDTR = 1317, + SystemZ_LER = 1318, + SystemZ_LEXBR = 1319, + SystemZ_LEXBRA = 1320, + SystemZ_LEXR = 1321, + SystemZ_LEY = 1322, + SystemZ_LFAS = 1323, + SystemZ_LFH = 1324, + SystemZ_LFHAT = 1325, + SystemZ_LFPC = 1326, + SystemZ_LG = 1327, + SystemZ_LGAT = 1328, + SystemZ_LGB = 1329, + SystemZ_LGBR = 1330, + SystemZ_LGDR = 1331, + SystemZ_LGF = 1332, + SystemZ_LGFI = 1333, + SystemZ_LGFR = 1334, + SystemZ_LGFRL = 1335, + SystemZ_LGG = 1336, + SystemZ_LGH = 1337, + SystemZ_LGHI = 1338, + SystemZ_LGHR = 1339, + SystemZ_LGHRL = 1340, + SystemZ_LGR = 1341, + SystemZ_LGRL = 1342, + SystemZ_LGSC = 1343, + SystemZ_LH = 1344, + SystemZ_LHH = 1345, + SystemZ_LHI = 1346, + SystemZ_LHR = 1347, + SystemZ_LHRL = 1348, + SystemZ_LHY = 1349, + SystemZ_LLC = 1350, + SystemZ_LLCH = 1351, + SystemZ_LLCR = 1352, + SystemZ_LLGC = 1353, + SystemZ_LLGCR = 1354, + SystemZ_LLGF = 1355, + SystemZ_LLGFAT = 1356, + SystemZ_LLGFR = 1357, + SystemZ_LLGFRL = 1358, + SystemZ_LLGFSG = 1359, + SystemZ_LLGH = 1360, + SystemZ_LLGHR = 1361, + SystemZ_LLGHRL = 1362, + SystemZ_LLGT = 1363, + SystemZ_LLGTAT = 1364, + SystemZ_LLGTR = 1365, + SystemZ_LLH = 1366, + SystemZ_LLHH = 1367, + SystemZ_LLHR = 1368, + SystemZ_LLHRL = 1369, + SystemZ_LLIHF = 1370, + SystemZ_LLIHH = 1371, + SystemZ_LLIHL = 1372, + SystemZ_LLILF = 1373, + SystemZ_LLILH = 1374, + SystemZ_LLILL = 1375, + SystemZ_LLZRGF = 1376, + SystemZ_LM = 1377, + SystemZ_LMD = 1378, + SystemZ_LMG = 1379, + SystemZ_LMH = 1380, + SystemZ_LMY = 1381, + SystemZ_LNDBR = 1382, + SystemZ_LNDFR = 1383, + SystemZ_LNDFR_32 = 1384, + SystemZ_LNDR = 1385, + SystemZ_LNEBR = 1386, + SystemZ_LNER = 1387, + SystemZ_LNGFR = 1388, + SystemZ_LNGR = 1389, + SystemZ_LNR = 1390, + SystemZ_LNXBR = 1391, + SystemZ_LNXR = 1392, + SystemZ_LOC = 1393, + SystemZ_LOCAsm = 1394, + SystemZ_LOCAsmE = 1395, + SystemZ_LOCAsmH = 1396, + SystemZ_LOCAsmHE = 1397, + SystemZ_LOCAsmL = 1398, + SystemZ_LOCAsmLE = 1399, + SystemZ_LOCAsmLH = 1400, + SystemZ_LOCAsmM = 1401, + SystemZ_LOCAsmNE = 1402, + SystemZ_LOCAsmNH = 1403, + SystemZ_LOCAsmNHE = 1404, + SystemZ_LOCAsmNL = 1405, + SystemZ_LOCAsmNLE = 1406, + SystemZ_LOCAsmNLH = 1407, + SystemZ_LOCAsmNM = 1408, + SystemZ_LOCAsmNO = 1409, + SystemZ_LOCAsmNP = 1410, + SystemZ_LOCAsmNZ = 1411, + SystemZ_LOCAsmO = 1412, + SystemZ_LOCAsmP = 1413, + SystemZ_LOCAsmZ = 1414, + SystemZ_LOCFH = 1415, + SystemZ_LOCFHAsm = 1416, + SystemZ_LOCFHAsmE = 1417, + SystemZ_LOCFHAsmH = 1418, + SystemZ_LOCFHAsmHE = 1419, + SystemZ_LOCFHAsmL = 1420, + SystemZ_LOCFHAsmLE = 1421, + SystemZ_LOCFHAsmLH = 1422, + SystemZ_LOCFHAsmM = 1423, + SystemZ_LOCFHAsmNE = 1424, + SystemZ_LOCFHAsmNH = 1425, + SystemZ_LOCFHAsmNHE = 1426, + SystemZ_LOCFHAsmNL = 1427, + SystemZ_LOCFHAsmNLE = 1428, + SystemZ_LOCFHAsmNLH = 1429, + SystemZ_LOCFHAsmNM = 1430, + SystemZ_LOCFHAsmNO = 1431, + SystemZ_LOCFHAsmNP = 1432, + SystemZ_LOCFHAsmNZ = 1433, + SystemZ_LOCFHAsmO = 1434, + SystemZ_LOCFHAsmP = 1435, + SystemZ_LOCFHAsmZ = 1436, + SystemZ_LOCFHR = 1437, + SystemZ_LOCFHRAsm = 1438, + SystemZ_LOCFHRAsmE = 1439, + SystemZ_LOCFHRAsmH = 1440, + SystemZ_LOCFHRAsmHE = 1441, + SystemZ_LOCFHRAsmL = 1442, + SystemZ_LOCFHRAsmLE = 1443, + SystemZ_LOCFHRAsmLH = 1444, + SystemZ_LOCFHRAsmM = 1445, + SystemZ_LOCFHRAsmNE = 1446, + SystemZ_LOCFHRAsmNH = 1447, + SystemZ_LOCFHRAsmNHE = 1448, + SystemZ_LOCFHRAsmNL = 1449, + SystemZ_LOCFHRAsmNLE = 1450, + SystemZ_LOCFHRAsmNLH = 1451, + SystemZ_LOCFHRAsmNM = 1452, + SystemZ_LOCFHRAsmNO = 1453, + SystemZ_LOCFHRAsmNP = 1454, + SystemZ_LOCFHRAsmNZ = 1455, + SystemZ_LOCFHRAsmO = 1456, + SystemZ_LOCFHRAsmP = 1457, + SystemZ_LOCFHRAsmZ = 1458, + SystemZ_LOCG = 1459, + SystemZ_LOCGAsm = 1460, + SystemZ_LOCGAsmE = 1461, + SystemZ_LOCGAsmH = 1462, + SystemZ_LOCGAsmHE = 1463, + SystemZ_LOCGAsmL = 1464, + SystemZ_LOCGAsmLE = 1465, + SystemZ_LOCGAsmLH = 1466, + SystemZ_LOCGAsmM = 1467, + SystemZ_LOCGAsmNE = 1468, + SystemZ_LOCGAsmNH = 1469, + SystemZ_LOCGAsmNHE = 1470, + SystemZ_LOCGAsmNL = 1471, + SystemZ_LOCGAsmNLE = 1472, + SystemZ_LOCGAsmNLH = 1473, + SystemZ_LOCGAsmNM = 1474, + SystemZ_LOCGAsmNO = 1475, + SystemZ_LOCGAsmNP = 1476, + SystemZ_LOCGAsmNZ = 1477, + SystemZ_LOCGAsmO = 1478, + SystemZ_LOCGAsmP = 1479, + SystemZ_LOCGAsmZ = 1480, + SystemZ_LOCGHI = 1481, + SystemZ_LOCGHIAsm = 1482, + SystemZ_LOCGHIAsmE = 1483, + SystemZ_LOCGHIAsmH = 1484, + SystemZ_LOCGHIAsmHE = 1485, + SystemZ_LOCGHIAsmL = 1486, + SystemZ_LOCGHIAsmLE = 1487, + SystemZ_LOCGHIAsmLH = 1488, + SystemZ_LOCGHIAsmM = 1489, + SystemZ_LOCGHIAsmNE = 1490, + SystemZ_LOCGHIAsmNH = 1491, + SystemZ_LOCGHIAsmNHE = 1492, + SystemZ_LOCGHIAsmNL = 1493, + SystemZ_LOCGHIAsmNLE = 1494, + SystemZ_LOCGHIAsmNLH = 1495, + SystemZ_LOCGHIAsmNM = 1496, + SystemZ_LOCGHIAsmNO = 1497, + SystemZ_LOCGHIAsmNP = 1498, + SystemZ_LOCGHIAsmNZ = 1499, + SystemZ_LOCGHIAsmO = 1500, + SystemZ_LOCGHIAsmP = 1501, + SystemZ_LOCGHIAsmZ = 1502, + SystemZ_LOCGR = 1503, + SystemZ_LOCGRAsm = 1504, + SystemZ_LOCGRAsmE = 1505, + SystemZ_LOCGRAsmH = 1506, + SystemZ_LOCGRAsmHE = 1507, + SystemZ_LOCGRAsmL = 1508, + SystemZ_LOCGRAsmLE = 1509, + SystemZ_LOCGRAsmLH = 1510, + SystemZ_LOCGRAsmM = 1511, + SystemZ_LOCGRAsmNE = 1512, + SystemZ_LOCGRAsmNH = 1513, + SystemZ_LOCGRAsmNHE = 1514, + SystemZ_LOCGRAsmNL = 1515, + SystemZ_LOCGRAsmNLE = 1516, + SystemZ_LOCGRAsmNLH = 1517, + SystemZ_LOCGRAsmNM = 1518, + SystemZ_LOCGRAsmNO = 1519, + SystemZ_LOCGRAsmNP = 1520, + SystemZ_LOCGRAsmNZ = 1521, + SystemZ_LOCGRAsmO = 1522, + SystemZ_LOCGRAsmP = 1523, + SystemZ_LOCGRAsmZ = 1524, + SystemZ_LOCHHI = 1525, + SystemZ_LOCHHIAsm = 1526, + SystemZ_LOCHHIAsmE = 1527, + SystemZ_LOCHHIAsmH = 1528, + SystemZ_LOCHHIAsmHE = 1529, + SystemZ_LOCHHIAsmL = 1530, + SystemZ_LOCHHIAsmLE = 1531, + SystemZ_LOCHHIAsmLH = 1532, + SystemZ_LOCHHIAsmM = 1533, + SystemZ_LOCHHIAsmNE = 1534, + SystemZ_LOCHHIAsmNH = 1535, + SystemZ_LOCHHIAsmNHE = 1536, + SystemZ_LOCHHIAsmNL = 1537, + SystemZ_LOCHHIAsmNLE = 1538, + SystemZ_LOCHHIAsmNLH = 1539, + SystemZ_LOCHHIAsmNM = 1540, + SystemZ_LOCHHIAsmNO = 1541, + SystemZ_LOCHHIAsmNP = 1542, + SystemZ_LOCHHIAsmNZ = 1543, + SystemZ_LOCHHIAsmO = 1544, + SystemZ_LOCHHIAsmP = 1545, + SystemZ_LOCHHIAsmZ = 1546, + SystemZ_LOCHI = 1547, + SystemZ_LOCHIAsm = 1548, + SystemZ_LOCHIAsmE = 1549, + SystemZ_LOCHIAsmH = 1550, + SystemZ_LOCHIAsmHE = 1551, + SystemZ_LOCHIAsmL = 1552, + SystemZ_LOCHIAsmLE = 1553, + SystemZ_LOCHIAsmLH = 1554, + SystemZ_LOCHIAsmM = 1555, + SystemZ_LOCHIAsmNE = 1556, + SystemZ_LOCHIAsmNH = 1557, + SystemZ_LOCHIAsmNHE = 1558, + SystemZ_LOCHIAsmNL = 1559, + SystemZ_LOCHIAsmNLE = 1560, + SystemZ_LOCHIAsmNLH = 1561, + SystemZ_LOCHIAsmNM = 1562, + SystemZ_LOCHIAsmNO = 1563, + SystemZ_LOCHIAsmNP = 1564, + SystemZ_LOCHIAsmNZ = 1565, + SystemZ_LOCHIAsmO = 1566, + SystemZ_LOCHIAsmP = 1567, + SystemZ_LOCHIAsmZ = 1568, + SystemZ_LOCR = 1569, + SystemZ_LOCRAsm = 1570, + SystemZ_LOCRAsmE = 1571, + SystemZ_LOCRAsmH = 1572, + SystemZ_LOCRAsmHE = 1573, + SystemZ_LOCRAsmL = 1574, + SystemZ_LOCRAsmLE = 1575, + SystemZ_LOCRAsmLH = 1576, + SystemZ_LOCRAsmM = 1577, + SystemZ_LOCRAsmNE = 1578, + SystemZ_LOCRAsmNH = 1579, + SystemZ_LOCRAsmNHE = 1580, + SystemZ_LOCRAsmNL = 1581, + SystemZ_LOCRAsmNLE = 1582, + SystemZ_LOCRAsmNLH = 1583, + SystemZ_LOCRAsmNM = 1584, + SystemZ_LOCRAsmNO = 1585, + SystemZ_LOCRAsmNP = 1586, + SystemZ_LOCRAsmNZ = 1587, + SystemZ_LOCRAsmO = 1588, + SystemZ_LOCRAsmP = 1589, + SystemZ_LOCRAsmZ = 1590, + SystemZ_LPCTL = 1591, + SystemZ_LPD = 1592, + SystemZ_LPDBR = 1593, + SystemZ_LPDFR = 1594, + SystemZ_LPDFR_32 = 1595, + SystemZ_LPDG = 1596, + SystemZ_LPDR = 1597, + SystemZ_LPEBR = 1598, + SystemZ_LPER = 1599, + SystemZ_LPGFR = 1600, + SystemZ_LPGR = 1601, + SystemZ_LPP = 1602, + SystemZ_LPQ = 1603, + SystemZ_LPR = 1604, + SystemZ_LPSW = 1605, + SystemZ_LPSWE = 1606, + SystemZ_LPTEA = 1607, + SystemZ_LPXBR = 1608, + SystemZ_LPXR = 1609, + SystemZ_LR = 1610, + SystemZ_LRA = 1611, + SystemZ_LRAG = 1612, + SystemZ_LRAY = 1613, + SystemZ_LRDR = 1614, + SystemZ_LRER = 1615, + SystemZ_LRL = 1616, + SystemZ_LRV = 1617, + SystemZ_LRVG = 1618, + SystemZ_LRVGR = 1619, + SystemZ_LRVH = 1620, + SystemZ_LRVR = 1621, + SystemZ_LSCTL = 1622, + SystemZ_LT = 1623, + SystemZ_LTDBR = 1624, + SystemZ_LTDBRCompare = 1625, + SystemZ_LTDR = 1626, + SystemZ_LTDTR = 1627, + SystemZ_LTEBR = 1628, + SystemZ_LTEBRCompare = 1629, + SystemZ_LTER = 1630, + SystemZ_LTG = 1631, + SystemZ_LTGF = 1632, + SystemZ_LTGFR = 1633, + SystemZ_LTGR = 1634, + SystemZ_LTR = 1635, + SystemZ_LTXBR = 1636, + SystemZ_LTXBRCompare = 1637, + SystemZ_LTXR = 1638, + SystemZ_LTXTR = 1639, + SystemZ_LURA = 1640, + SystemZ_LURAG = 1641, + SystemZ_LXD = 1642, + SystemZ_LXDB = 1643, + SystemZ_LXDBR = 1644, + SystemZ_LXDR = 1645, + SystemZ_LXDTR = 1646, + SystemZ_LXE = 1647, + SystemZ_LXEB = 1648, + SystemZ_LXEBR = 1649, + SystemZ_LXER = 1650, + SystemZ_LXR = 1651, + SystemZ_LY = 1652, + SystemZ_LZDR = 1653, + SystemZ_LZER = 1654, + SystemZ_LZRF = 1655, + SystemZ_LZRG = 1656, + SystemZ_LZXR = 1657, + SystemZ_M = 1658, + SystemZ_MAD = 1659, + SystemZ_MADB = 1660, + SystemZ_MADBR = 1661, + SystemZ_MADR = 1662, + SystemZ_MAE = 1663, + SystemZ_MAEB = 1664, + SystemZ_MAEBR = 1665, + SystemZ_MAER = 1666, + SystemZ_MAY = 1667, + SystemZ_MAYH = 1668, + SystemZ_MAYHR = 1669, + SystemZ_MAYL = 1670, + SystemZ_MAYLR = 1671, + SystemZ_MAYR = 1672, + SystemZ_MC = 1673, + SystemZ_MD = 1674, + SystemZ_MDB = 1675, + SystemZ_MDBR = 1676, + SystemZ_MDE = 1677, + SystemZ_MDEB = 1678, + SystemZ_MDEBR = 1679, + SystemZ_MDER = 1680, + SystemZ_MDR = 1681, + SystemZ_MDTR = 1682, + SystemZ_MDTRA = 1683, + SystemZ_ME = 1684, + SystemZ_MEE = 1685, + SystemZ_MEEB = 1686, + SystemZ_MEEBR = 1687, + SystemZ_MEER = 1688, + SystemZ_MER = 1689, + SystemZ_MFY = 1690, + SystemZ_MG = 1691, + SystemZ_MGH = 1692, + SystemZ_MGHI = 1693, + SystemZ_MGRK = 1694, + SystemZ_MH = 1695, + SystemZ_MHI = 1696, + SystemZ_MHY = 1697, + SystemZ_ML = 1698, + SystemZ_MLG = 1699, + SystemZ_MLGR = 1700, + SystemZ_MLR = 1701, + SystemZ_MP = 1702, + SystemZ_MR = 1703, + SystemZ_MS = 1704, + SystemZ_MSC = 1705, + SystemZ_MSCH = 1706, + SystemZ_MSD = 1707, + SystemZ_MSDB = 1708, + SystemZ_MSDBR = 1709, + SystemZ_MSDR = 1710, + SystemZ_MSE = 1711, + SystemZ_MSEB = 1712, + SystemZ_MSEBR = 1713, + SystemZ_MSER = 1714, + SystemZ_MSFI = 1715, + SystemZ_MSG = 1716, + SystemZ_MSGC = 1717, + SystemZ_MSGF = 1718, + SystemZ_MSGFI = 1719, + SystemZ_MSGFR = 1720, + SystemZ_MSGR = 1721, + SystemZ_MSGRKC = 1722, + SystemZ_MSR = 1723, + SystemZ_MSRKC = 1724, + SystemZ_MSTA = 1725, + SystemZ_MSY = 1726, + SystemZ_MVC = 1727, + SystemZ_MVCDK = 1728, + SystemZ_MVCIN = 1729, + SystemZ_MVCK = 1730, + SystemZ_MVCL = 1731, + SystemZ_MVCLE = 1732, + SystemZ_MVCLU = 1733, + SystemZ_MVCOS = 1734, + SystemZ_MVCP = 1735, + SystemZ_MVCS = 1736, + SystemZ_MVCSK = 1737, + SystemZ_MVGHI = 1738, + SystemZ_MVHHI = 1739, + SystemZ_MVHI = 1740, + SystemZ_MVI = 1741, + SystemZ_MVIY = 1742, + SystemZ_MVN = 1743, + SystemZ_MVO = 1744, + SystemZ_MVPG = 1745, + SystemZ_MVST = 1746, + SystemZ_MVZ = 1747, + SystemZ_MXBR = 1748, + SystemZ_MXD = 1749, + SystemZ_MXDB = 1750, + SystemZ_MXDBR = 1751, + SystemZ_MXDR = 1752, + SystemZ_MXR = 1753, + SystemZ_MXTR = 1754, + SystemZ_MXTRA = 1755, + SystemZ_MY = 1756, + SystemZ_MYH = 1757, + SystemZ_MYHR = 1758, + SystemZ_MYL = 1759, + SystemZ_MYLR = 1760, + SystemZ_MYR = 1761, + SystemZ_N = 1762, + SystemZ_NC = 1763, + SystemZ_NG = 1764, + SystemZ_NGR = 1765, + SystemZ_NGRK = 1766, + SystemZ_NI = 1767, + SystemZ_NIAI = 1768, + SystemZ_NIHF = 1769, + SystemZ_NIHH = 1770, + SystemZ_NIHL = 1771, + SystemZ_NILF = 1772, + SystemZ_NILH = 1773, + SystemZ_NILL = 1774, + SystemZ_NIY = 1775, + SystemZ_NR = 1776, + SystemZ_NRK = 1777, + SystemZ_NTSTG = 1778, + SystemZ_NY = 1779, + SystemZ_O = 1780, + SystemZ_OC = 1781, + SystemZ_OG = 1782, + SystemZ_OGR = 1783, + SystemZ_OGRK = 1784, + SystemZ_OI = 1785, + SystemZ_OIHF = 1786, + SystemZ_OIHH = 1787, + SystemZ_OIHL = 1788, + SystemZ_OILF = 1789, + SystemZ_OILH = 1790, + SystemZ_OILL = 1791, + SystemZ_OIY = 1792, + SystemZ_OR = 1793, + SystemZ_ORK = 1794, + SystemZ_OY = 1795, + SystemZ_PACK = 1796, + SystemZ_PALB = 1797, + SystemZ_PC = 1798, + SystemZ_PCC = 1799, + SystemZ_PCKMO = 1800, + SystemZ_PFD = 1801, + SystemZ_PFDRL = 1802, + SystemZ_PFMF = 1803, + SystemZ_PFPO = 1804, + SystemZ_PGIN = 1805, + SystemZ_PGOUT = 1806, + SystemZ_PKA = 1807, + SystemZ_PKU = 1808, + SystemZ_PLO = 1809, + SystemZ_POPCNT = 1810, + SystemZ_PPA = 1811, + SystemZ_PPNO = 1812, + SystemZ_PR = 1813, + SystemZ_PRNO = 1814, + SystemZ_PT = 1815, + SystemZ_PTF = 1816, + SystemZ_PTFF = 1817, + SystemZ_PTI = 1818, + SystemZ_PTLB = 1819, + SystemZ_QADTR = 1820, + SystemZ_QAXTR = 1821, + SystemZ_QCTRI = 1822, + SystemZ_QSI = 1823, + SystemZ_RCHP = 1824, + SystemZ_RISBG = 1825, + SystemZ_RISBG32 = 1826, + SystemZ_RISBGN = 1827, + SystemZ_RISBHG = 1828, + SystemZ_RISBLG = 1829, + SystemZ_RLL = 1830, + SystemZ_RLLG = 1831, + SystemZ_RNSBG = 1832, + SystemZ_ROSBG = 1833, + SystemZ_RP = 1834, + SystemZ_RRBE = 1835, + SystemZ_RRBM = 1836, + SystemZ_RRDTR = 1837, + SystemZ_RRXTR = 1838, + SystemZ_RSCH = 1839, + SystemZ_RXSBG = 1840, + SystemZ_S = 1841, + SystemZ_SAC = 1842, + SystemZ_SACF = 1843, + SystemZ_SAL = 1844, + SystemZ_SAM24 = 1845, + SystemZ_SAM31 = 1846, + SystemZ_SAM64 = 1847, + SystemZ_SAR = 1848, + SystemZ_SCCTR = 1849, + SystemZ_SCHM = 1850, + SystemZ_SCK = 1851, + SystemZ_SCKC = 1852, + SystemZ_SCKPF = 1853, + SystemZ_SD = 1854, + SystemZ_SDB = 1855, + SystemZ_SDBR = 1856, + SystemZ_SDR = 1857, + SystemZ_SDTR = 1858, + SystemZ_SDTRA = 1859, + SystemZ_SE = 1860, + SystemZ_SEB = 1861, + SystemZ_SEBR = 1862, + SystemZ_SER = 1863, + SystemZ_SFASR = 1864, + SystemZ_SFPC = 1865, + SystemZ_SG = 1866, + SystemZ_SGF = 1867, + SystemZ_SGFR = 1868, + SystemZ_SGH = 1869, + SystemZ_SGR = 1870, + SystemZ_SGRK = 1871, + SystemZ_SH = 1872, + SystemZ_SHHHR = 1873, + SystemZ_SHHLR = 1874, + SystemZ_SHY = 1875, + SystemZ_SIE = 1876, + SystemZ_SIGA = 1877, + SystemZ_SIGP = 1878, + SystemZ_SL = 1879, + SystemZ_SLA = 1880, + SystemZ_SLAG = 1881, + SystemZ_SLAK = 1882, + SystemZ_SLB = 1883, + SystemZ_SLBG = 1884, + SystemZ_SLBGR = 1885, + SystemZ_SLBR = 1886, + SystemZ_SLDA = 1887, + SystemZ_SLDL = 1888, + SystemZ_SLDT = 1889, + SystemZ_SLFI = 1890, + SystemZ_SLG = 1891, + SystemZ_SLGF = 1892, + SystemZ_SLGFI = 1893, + SystemZ_SLGFR = 1894, + SystemZ_SLGR = 1895, + SystemZ_SLGRK = 1896, + SystemZ_SLHHHR = 1897, + SystemZ_SLHHLR = 1898, + SystemZ_SLL = 1899, + SystemZ_SLLG = 1900, + SystemZ_SLLK = 1901, + SystemZ_SLR = 1902, + SystemZ_SLRK = 1903, + SystemZ_SLXT = 1904, + SystemZ_SLY = 1905, + SystemZ_SP = 1906, + SystemZ_SPCTR = 1907, + SystemZ_SPKA = 1908, + SystemZ_SPM = 1909, + SystemZ_SPT = 1910, + SystemZ_SPX = 1911, + SystemZ_SQD = 1912, + SystemZ_SQDB = 1913, + SystemZ_SQDBR = 1914, + SystemZ_SQDR = 1915, + SystemZ_SQE = 1916, + SystemZ_SQEB = 1917, + SystemZ_SQEBR = 1918, + SystemZ_SQER = 1919, + SystemZ_SQXBR = 1920, + SystemZ_SQXR = 1921, + SystemZ_SR = 1922, + SystemZ_SRA = 1923, + SystemZ_SRAG = 1924, + SystemZ_SRAK = 1925, + SystemZ_SRDA = 1926, + SystemZ_SRDL = 1927, + SystemZ_SRDT = 1928, + SystemZ_SRK = 1929, + SystemZ_SRL = 1930, + SystemZ_SRLG = 1931, + SystemZ_SRLK = 1932, + SystemZ_SRNM = 1933, + SystemZ_SRNMB = 1934, + SystemZ_SRNMT = 1935, + SystemZ_SRP = 1936, + SystemZ_SRST = 1937, + SystemZ_SRSTU = 1938, + SystemZ_SRXT = 1939, + SystemZ_SSAIR = 1940, + SystemZ_SSAR = 1941, + SystemZ_SSCH = 1942, + SystemZ_SSKE = 1943, + SystemZ_SSKEOpt = 1944, + SystemZ_SSM = 1945, + SystemZ_ST = 1946, + SystemZ_STAM = 1947, + SystemZ_STAMY = 1948, + SystemZ_STAP = 1949, + SystemZ_STC = 1950, + SystemZ_STCH = 1951, + SystemZ_STCK = 1952, + SystemZ_STCKC = 1953, + SystemZ_STCKE = 1954, + SystemZ_STCKF = 1955, + SystemZ_STCM = 1956, + SystemZ_STCMH = 1957, + SystemZ_STCMY = 1958, + SystemZ_STCPS = 1959, + SystemZ_STCRW = 1960, + SystemZ_STCTG = 1961, + SystemZ_STCTL = 1962, + SystemZ_STCY = 1963, + SystemZ_STD = 1964, + SystemZ_STDY = 1965, + SystemZ_STE = 1966, + SystemZ_STEY = 1967, + SystemZ_STFH = 1968, + SystemZ_STFL = 1969, + SystemZ_STFLE = 1970, + SystemZ_STFPC = 1971, + SystemZ_STG = 1972, + SystemZ_STGRL = 1973, + SystemZ_STGSC = 1974, + SystemZ_STH = 1975, + SystemZ_STHH = 1976, + SystemZ_STHRL = 1977, + SystemZ_STHY = 1978, + SystemZ_STIDP = 1979, + SystemZ_STM = 1980, + SystemZ_STMG = 1981, + SystemZ_STMH = 1982, + SystemZ_STMY = 1983, + SystemZ_STNSM = 1984, + SystemZ_STOC = 1985, + SystemZ_STOCAsm = 1986, + SystemZ_STOCAsmE = 1987, + SystemZ_STOCAsmH = 1988, + SystemZ_STOCAsmHE = 1989, + SystemZ_STOCAsmL = 1990, + SystemZ_STOCAsmLE = 1991, + SystemZ_STOCAsmLH = 1992, + SystemZ_STOCAsmM = 1993, + SystemZ_STOCAsmNE = 1994, + SystemZ_STOCAsmNH = 1995, + SystemZ_STOCAsmNHE = 1996, + SystemZ_STOCAsmNL = 1997, + SystemZ_STOCAsmNLE = 1998, + SystemZ_STOCAsmNLH = 1999, + SystemZ_STOCAsmNM = 2000, + SystemZ_STOCAsmNO = 2001, + SystemZ_STOCAsmNP = 2002, + SystemZ_STOCAsmNZ = 2003, + SystemZ_STOCAsmO = 2004, + SystemZ_STOCAsmP = 2005, + SystemZ_STOCAsmZ = 2006, + SystemZ_STOCFH = 2007, + SystemZ_STOCFHAsm = 2008, + SystemZ_STOCFHAsmE = 2009, + SystemZ_STOCFHAsmH = 2010, + SystemZ_STOCFHAsmHE = 2011, + SystemZ_STOCFHAsmL = 2012, + SystemZ_STOCFHAsmLE = 2013, + SystemZ_STOCFHAsmLH = 2014, + SystemZ_STOCFHAsmM = 2015, + SystemZ_STOCFHAsmNE = 2016, + SystemZ_STOCFHAsmNH = 2017, + SystemZ_STOCFHAsmNHE = 2018, + SystemZ_STOCFHAsmNL = 2019, + SystemZ_STOCFHAsmNLE = 2020, + SystemZ_STOCFHAsmNLH = 2021, + SystemZ_STOCFHAsmNM = 2022, + SystemZ_STOCFHAsmNO = 2023, + SystemZ_STOCFHAsmNP = 2024, + SystemZ_STOCFHAsmNZ = 2025, + SystemZ_STOCFHAsmO = 2026, + SystemZ_STOCFHAsmP = 2027, + SystemZ_STOCFHAsmZ = 2028, + SystemZ_STOCG = 2029, + SystemZ_STOCGAsm = 2030, + SystemZ_STOCGAsmE = 2031, + SystemZ_STOCGAsmH = 2032, + SystemZ_STOCGAsmHE = 2033, + SystemZ_STOCGAsmL = 2034, + SystemZ_STOCGAsmLE = 2035, + SystemZ_STOCGAsmLH = 2036, + SystemZ_STOCGAsmM = 2037, + SystemZ_STOCGAsmNE = 2038, + SystemZ_STOCGAsmNH = 2039, + SystemZ_STOCGAsmNHE = 2040, + SystemZ_STOCGAsmNL = 2041, + SystemZ_STOCGAsmNLE = 2042, + SystemZ_STOCGAsmNLH = 2043, + SystemZ_STOCGAsmNM = 2044, + SystemZ_STOCGAsmNO = 2045, + SystemZ_STOCGAsmNP = 2046, + SystemZ_STOCGAsmNZ = 2047, + SystemZ_STOCGAsmO = 2048, + SystemZ_STOCGAsmP = 2049, + SystemZ_STOCGAsmZ = 2050, + SystemZ_STOSM = 2051, + SystemZ_STPQ = 2052, + SystemZ_STPT = 2053, + SystemZ_STPX = 2054, + SystemZ_STRAG = 2055, + SystemZ_STRL = 2056, + SystemZ_STRV = 2057, + SystemZ_STRVG = 2058, + SystemZ_STRVH = 2059, + SystemZ_STSCH = 2060, + SystemZ_STSI = 2061, + SystemZ_STURA = 2062, + SystemZ_STURG = 2063, + SystemZ_STY = 2064, + SystemZ_SU = 2065, + SystemZ_SUR = 2066, + SystemZ_SVC = 2067, + SystemZ_SW = 2068, + SystemZ_SWR = 2069, + SystemZ_SXBR = 2070, + SystemZ_SXR = 2071, + SystemZ_SXTR = 2072, + SystemZ_SXTRA = 2073, + SystemZ_SY = 2074, + SystemZ_TABORT = 2075, + SystemZ_TAM = 2076, + SystemZ_TAR = 2077, + SystemZ_TB = 2078, + SystemZ_TBDR = 2079, + SystemZ_TBEDR = 2080, + SystemZ_TBEGIN = 2081, + SystemZ_TBEGINC = 2082, + SystemZ_TCDB = 2083, + SystemZ_TCEB = 2084, + SystemZ_TCXB = 2085, + SystemZ_TDCDT = 2086, + SystemZ_TDCET = 2087, + SystemZ_TDCXT = 2088, + SystemZ_TDGDT = 2089, + SystemZ_TDGET = 2090, + SystemZ_TDGXT = 2091, + SystemZ_TEND = 2092, + SystemZ_THDER = 2093, + SystemZ_THDR = 2094, + SystemZ_TM = 2095, + SystemZ_TMHH = 2096, + SystemZ_TMHL = 2097, + SystemZ_TMLH = 2098, + SystemZ_TMLL = 2099, + SystemZ_TMY = 2100, + SystemZ_TP = 2101, + SystemZ_TPI = 2102, + SystemZ_TPROT = 2103, + SystemZ_TR = 2104, + SystemZ_TRACE = 2105, + SystemZ_TRACG = 2106, + SystemZ_TRAP2 = 2107, + SystemZ_TRAP4 = 2108, + SystemZ_TRE = 2109, + SystemZ_TROO = 2110, + SystemZ_TROOOpt = 2111, + SystemZ_TROT = 2112, + SystemZ_TROTOpt = 2113, + SystemZ_TRT = 2114, + SystemZ_TRTE = 2115, + SystemZ_TRTEOpt = 2116, + SystemZ_TRTO = 2117, + SystemZ_TRTOOpt = 2118, + SystemZ_TRTR = 2119, + SystemZ_TRTRE = 2120, + SystemZ_TRTREOpt = 2121, + SystemZ_TRTT = 2122, + SystemZ_TRTTOpt = 2123, + SystemZ_TS = 2124, + SystemZ_TSCH = 2125, + SystemZ_UNPK = 2126, + SystemZ_UNPKA = 2127, + SystemZ_UNPKU = 2128, + SystemZ_UPT = 2129, + SystemZ_VA = 2130, + SystemZ_VAB = 2131, + SystemZ_VAC = 2132, + SystemZ_VACC = 2133, + SystemZ_VACCB = 2134, + SystemZ_VACCC = 2135, + SystemZ_VACCCQ = 2136, + SystemZ_VACCF = 2137, + SystemZ_VACCG = 2138, + SystemZ_VACCH = 2139, + SystemZ_VACCQ = 2140, + SystemZ_VACQ = 2141, + SystemZ_VAF = 2142, + SystemZ_VAG = 2143, + SystemZ_VAH = 2144, + SystemZ_VAP = 2145, + SystemZ_VAQ = 2146, + SystemZ_VAVG = 2147, + SystemZ_VAVGB = 2148, + SystemZ_VAVGF = 2149, + SystemZ_VAVGG = 2150, + SystemZ_VAVGH = 2151, + SystemZ_VAVGL = 2152, + SystemZ_VAVGLB = 2153, + SystemZ_VAVGLF = 2154, + SystemZ_VAVGLG = 2155, + SystemZ_VAVGLH = 2156, + SystemZ_VBPERM = 2157, + SystemZ_VCDG = 2158, + SystemZ_VCDGB = 2159, + SystemZ_VCDLG = 2160, + SystemZ_VCDLGB = 2161, + SystemZ_VCEQ = 2162, + SystemZ_VCEQB = 2163, + SystemZ_VCEQBS = 2164, + SystemZ_VCEQF = 2165, + SystemZ_VCEQFS = 2166, + SystemZ_VCEQG = 2167, + SystemZ_VCEQGS = 2168, + SystemZ_VCEQH = 2169, + SystemZ_VCEQHS = 2170, + SystemZ_VCGD = 2171, + SystemZ_VCGDB = 2172, + SystemZ_VCH = 2173, + SystemZ_VCHB = 2174, + SystemZ_VCHBS = 2175, + SystemZ_VCHF = 2176, + SystemZ_VCHFS = 2177, + SystemZ_VCHG = 2178, + SystemZ_VCHGS = 2179, + SystemZ_VCHH = 2180, + SystemZ_VCHHS = 2181, + SystemZ_VCHL = 2182, + SystemZ_VCHLB = 2183, + SystemZ_VCHLBS = 2184, + SystemZ_VCHLF = 2185, + SystemZ_VCHLFS = 2186, + SystemZ_VCHLG = 2187, + SystemZ_VCHLGS = 2188, + SystemZ_VCHLH = 2189, + SystemZ_VCHLHS = 2190, + SystemZ_VCKSM = 2191, + SystemZ_VCLGD = 2192, + SystemZ_VCLGDB = 2193, + SystemZ_VCLZ = 2194, + SystemZ_VCLZB = 2195, + SystemZ_VCLZF = 2196, + SystemZ_VCLZG = 2197, + SystemZ_VCLZH = 2198, + SystemZ_VCP = 2199, + SystemZ_VCTZ = 2200, + SystemZ_VCTZB = 2201, + SystemZ_VCTZF = 2202, + SystemZ_VCTZG = 2203, + SystemZ_VCTZH = 2204, + SystemZ_VCVB = 2205, + SystemZ_VCVBG = 2206, + SystemZ_VCVD = 2207, + SystemZ_VCVDG = 2208, + SystemZ_VDP = 2209, + SystemZ_VEC = 2210, + SystemZ_VECB = 2211, + SystemZ_VECF = 2212, + SystemZ_VECG = 2213, + SystemZ_VECH = 2214, + SystemZ_VECL = 2215, + SystemZ_VECLB = 2216, + SystemZ_VECLF = 2217, + SystemZ_VECLG = 2218, + SystemZ_VECLH = 2219, + SystemZ_VERIM = 2220, + SystemZ_VERIMB = 2221, + SystemZ_VERIMF = 2222, + SystemZ_VERIMG = 2223, + SystemZ_VERIMH = 2224, + SystemZ_VERLL = 2225, + SystemZ_VERLLB = 2226, + SystemZ_VERLLF = 2227, + SystemZ_VERLLG = 2228, + SystemZ_VERLLH = 2229, + SystemZ_VERLLV = 2230, + SystemZ_VERLLVB = 2231, + SystemZ_VERLLVF = 2232, + SystemZ_VERLLVG = 2233, + SystemZ_VERLLVH = 2234, + SystemZ_VESL = 2235, + SystemZ_VESLB = 2236, + SystemZ_VESLF = 2237, + SystemZ_VESLG = 2238, + SystemZ_VESLH = 2239, + SystemZ_VESLV = 2240, + SystemZ_VESLVB = 2241, + SystemZ_VESLVF = 2242, + SystemZ_VESLVG = 2243, + SystemZ_VESLVH = 2244, + SystemZ_VESRA = 2245, + SystemZ_VESRAB = 2246, + SystemZ_VESRAF = 2247, + SystemZ_VESRAG = 2248, + SystemZ_VESRAH = 2249, + SystemZ_VESRAV = 2250, + SystemZ_VESRAVB = 2251, + SystemZ_VESRAVF = 2252, + SystemZ_VESRAVG = 2253, + SystemZ_VESRAVH = 2254, + SystemZ_VESRL = 2255, + SystemZ_VESRLB = 2256, + SystemZ_VESRLF = 2257, + SystemZ_VESRLG = 2258, + SystemZ_VESRLH = 2259, + SystemZ_VESRLV = 2260, + SystemZ_VESRLVB = 2261, + SystemZ_VESRLVF = 2262, + SystemZ_VESRLVG = 2263, + SystemZ_VESRLVH = 2264, + SystemZ_VFA = 2265, + SystemZ_VFADB = 2266, + SystemZ_VFAE = 2267, + SystemZ_VFAEB = 2268, + SystemZ_VFAEBS = 2269, + SystemZ_VFAEF = 2270, + SystemZ_VFAEFS = 2271, + SystemZ_VFAEH = 2272, + SystemZ_VFAEHS = 2273, + SystemZ_VFAEZB = 2274, + SystemZ_VFAEZBS = 2275, + SystemZ_VFAEZF = 2276, + SystemZ_VFAEZFS = 2277, + SystemZ_VFAEZH = 2278, + SystemZ_VFAEZHS = 2279, + SystemZ_VFASB = 2280, + SystemZ_VFCE = 2281, + SystemZ_VFCEDB = 2282, + SystemZ_VFCEDBS = 2283, + SystemZ_VFCESB = 2284, + SystemZ_VFCESBS = 2285, + SystemZ_VFCH = 2286, + SystemZ_VFCHDB = 2287, + SystemZ_VFCHDBS = 2288, + SystemZ_VFCHE = 2289, + SystemZ_VFCHEDB = 2290, + SystemZ_VFCHEDBS = 2291, + SystemZ_VFCHESB = 2292, + SystemZ_VFCHESBS = 2293, + SystemZ_VFCHSB = 2294, + SystemZ_VFCHSBS = 2295, + SystemZ_VFD = 2296, + SystemZ_VFDDB = 2297, + SystemZ_VFDSB = 2298, + SystemZ_VFEE = 2299, + SystemZ_VFEEB = 2300, + SystemZ_VFEEBS = 2301, + SystemZ_VFEEF = 2302, + SystemZ_VFEEFS = 2303, + SystemZ_VFEEH = 2304, + SystemZ_VFEEHS = 2305, + SystemZ_VFEEZB = 2306, + SystemZ_VFEEZBS = 2307, + SystemZ_VFEEZF = 2308, + SystemZ_VFEEZFS = 2309, + SystemZ_VFEEZH = 2310, + SystemZ_VFEEZHS = 2311, + SystemZ_VFENE = 2312, + SystemZ_VFENEB = 2313, + SystemZ_VFENEBS = 2314, + SystemZ_VFENEF = 2315, + SystemZ_VFENEFS = 2316, + SystemZ_VFENEH = 2317, + SystemZ_VFENEHS = 2318, + SystemZ_VFENEZB = 2319, + SystemZ_VFENEZBS = 2320, + SystemZ_VFENEZF = 2321, + SystemZ_VFENEZFS = 2322, + SystemZ_VFENEZH = 2323, + SystemZ_VFENEZHS = 2324, + SystemZ_VFI = 2325, + SystemZ_VFIDB = 2326, + SystemZ_VFISB = 2327, + SystemZ_VFKEDB = 2328, + SystemZ_VFKEDBS = 2329, + SystemZ_VFKESB = 2330, + SystemZ_VFKESBS = 2331, + SystemZ_VFKHDB = 2332, + SystemZ_VFKHDBS = 2333, + SystemZ_VFKHEDB = 2334, + SystemZ_VFKHEDBS = 2335, + SystemZ_VFKHESB = 2336, + SystemZ_VFKHESBS = 2337, + SystemZ_VFKHSB = 2338, + SystemZ_VFKHSBS = 2339, + SystemZ_VFLCDB = 2340, + SystemZ_VFLCSB = 2341, + SystemZ_VFLL = 2342, + SystemZ_VFLLS = 2343, + SystemZ_VFLNDB = 2344, + SystemZ_VFLNSB = 2345, + SystemZ_VFLPDB = 2346, + SystemZ_VFLPSB = 2347, + SystemZ_VFLR = 2348, + SystemZ_VFLRD = 2349, + SystemZ_VFM = 2350, + SystemZ_VFMA = 2351, + SystemZ_VFMADB = 2352, + SystemZ_VFMASB = 2353, + SystemZ_VFMAX = 2354, + SystemZ_VFMAXDB = 2355, + SystemZ_VFMAXSB = 2356, + SystemZ_VFMDB = 2357, + SystemZ_VFMIN = 2358, + SystemZ_VFMINDB = 2359, + SystemZ_VFMINSB = 2360, + SystemZ_VFMS = 2361, + SystemZ_VFMSB = 2362, + SystemZ_VFMSDB = 2363, + SystemZ_VFMSSB = 2364, + SystemZ_VFNMA = 2365, + SystemZ_VFNMADB = 2366, + SystemZ_VFNMASB = 2367, + SystemZ_VFNMS = 2368, + SystemZ_VFNMSDB = 2369, + SystemZ_VFNMSSB = 2370, + SystemZ_VFPSO = 2371, + SystemZ_VFPSODB = 2372, + SystemZ_VFPSOSB = 2373, + SystemZ_VFS = 2374, + SystemZ_VFSDB = 2375, + SystemZ_VFSQ = 2376, + SystemZ_VFSQDB = 2377, + SystemZ_VFSQSB = 2378, + SystemZ_VFSSB = 2379, + SystemZ_VFTCI = 2380, + SystemZ_VFTCIDB = 2381, + SystemZ_VFTCISB = 2382, + SystemZ_VGBM = 2383, + SystemZ_VGEF = 2384, + SystemZ_VGEG = 2385, + SystemZ_VGFM = 2386, + SystemZ_VGFMA = 2387, + SystemZ_VGFMAB = 2388, + SystemZ_VGFMAF = 2389, + SystemZ_VGFMAG = 2390, + SystemZ_VGFMAH = 2391, + SystemZ_VGFMB = 2392, + SystemZ_VGFMF = 2393, + SystemZ_VGFMG = 2394, + SystemZ_VGFMH = 2395, + SystemZ_VGM = 2396, + SystemZ_VGMB = 2397, + SystemZ_VGMF = 2398, + SystemZ_VGMG = 2399, + SystemZ_VGMH = 2400, + SystemZ_VISTR = 2401, + SystemZ_VISTRB = 2402, + SystemZ_VISTRBS = 2403, + SystemZ_VISTRF = 2404, + SystemZ_VISTRFS = 2405, + SystemZ_VISTRH = 2406, + SystemZ_VISTRHS = 2407, + SystemZ_VL = 2408, + SystemZ_VLBB = 2409, + SystemZ_VLC = 2410, + SystemZ_VLCB = 2411, + SystemZ_VLCF = 2412, + SystemZ_VLCG = 2413, + SystemZ_VLCH = 2414, + SystemZ_VLDE = 2415, + SystemZ_VLDEB = 2416, + SystemZ_VLEB = 2417, + SystemZ_VLED = 2418, + SystemZ_VLEDB = 2419, + SystemZ_VLEF = 2420, + SystemZ_VLEG = 2421, + SystemZ_VLEH = 2422, + SystemZ_VLEIB = 2423, + SystemZ_VLEIF = 2424, + SystemZ_VLEIG = 2425, + SystemZ_VLEIH = 2426, + SystemZ_VLGV = 2427, + SystemZ_VLGVB = 2428, + SystemZ_VLGVF = 2429, + SystemZ_VLGVG = 2430, + SystemZ_VLGVH = 2431, + SystemZ_VLIP = 2432, + SystemZ_VLL = 2433, + SystemZ_VLLEZ = 2434, + SystemZ_VLLEZB = 2435, + SystemZ_VLLEZF = 2436, + SystemZ_VLLEZG = 2437, + SystemZ_VLLEZH = 2438, + SystemZ_VLLEZLF = 2439, + SystemZ_VLM = 2440, + SystemZ_VLP = 2441, + SystemZ_VLPB = 2442, + SystemZ_VLPF = 2443, + SystemZ_VLPG = 2444, + SystemZ_VLPH = 2445, + SystemZ_VLR = 2446, + SystemZ_VLREP = 2447, + SystemZ_VLREPB = 2448, + SystemZ_VLREPF = 2449, + SystemZ_VLREPG = 2450, + SystemZ_VLREPH = 2451, + SystemZ_VLRL = 2452, + SystemZ_VLRLR = 2453, + SystemZ_VLVG = 2454, + SystemZ_VLVGB = 2455, + SystemZ_VLVGF = 2456, + SystemZ_VLVGG = 2457, + SystemZ_VLVGH = 2458, + SystemZ_VLVGP = 2459, + SystemZ_VMAE = 2460, + SystemZ_VMAEB = 2461, + SystemZ_VMAEF = 2462, + SystemZ_VMAEH = 2463, + SystemZ_VMAH = 2464, + SystemZ_VMAHB = 2465, + SystemZ_VMAHF = 2466, + SystemZ_VMAHH = 2467, + SystemZ_VMAL = 2468, + SystemZ_VMALB = 2469, + SystemZ_VMALE = 2470, + SystemZ_VMALEB = 2471, + SystemZ_VMALEF = 2472, + SystemZ_VMALEH = 2473, + SystemZ_VMALF = 2474, + SystemZ_VMALH = 2475, + SystemZ_VMALHB = 2476, + SystemZ_VMALHF = 2477, + SystemZ_VMALHH = 2478, + SystemZ_VMALHW = 2479, + SystemZ_VMALO = 2480, + SystemZ_VMALOB = 2481, + SystemZ_VMALOF = 2482, + SystemZ_VMALOH = 2483, + SystemZ_VMAO = 2484, + SystemZ_VMAOB = 2485, + SystemZ_VMAOF = 2486, + SystemZ_VMAOH = 2487, + SystemZ_VME = 2488, + SystemZ_VMEB = 2489, + SystemZ_VMEF = 2490, + SystemZ_VMEH = 2491, + SystemZ_VMH = 2492, + SystemZ_VMHB = 2493, + SystemZ_VMHF = 2494, + SystemZ_VMHH = 2495, + SystemZ_VML = 2496, + SystemZ_VMLB = 2497, + SystemZ_VMLE = 2498, + SystemZ_VMLEB = 2499, + SystemZ_VMLEF = 2500, + SystemZ_VMLEH = 2501, + SystemZ_VMLF = 2502, + SystemZ_VMLH = 2503, + SystemZ_VMLHB = 2504, + SystemZ_VMLHF = 2505, + SystemZ_VMLHH = 2506, + SystemZ_VMLHW = 2507, + SystemZ_VMLO = 2508, + SystemZ_VMLOB = 2509, + SystemZ_VMLOF = 2510, + SystemZ_VMLOH = 2511, + SystemZ_VMN = 2512, + SystemZ_VMNB = 2513, + SystemZ_VMNF = 2514, + SystemZ_VMNG = 2515, + SystemZ_VMNH = 2516, + SystemZ_VMNL = 2517, + SystemZ_VMNLB = 2518, + SystemZ_VMNLF = 2519, + SystemZ_VMNLG = 2520, + SystemZ_VMNLH = 2521, + SystemZ_VMO = 2522, + SystemZ_VMOB = 2523, + SystemZ_VMOF = 2524, + SystemZ_VMOH = 2525, + SystemZ_VMP = 2526, + SystemZ_VMRH = 2527, + SystemZ_VMRHB = 2528, + SystemZ_VMRHF = 2529, + SystemZ_VMRHG = 2530, + SystemZ_VMRHH = 2531, + SystemZ_VMRL = 2532, + SystemZ_VMRLB = 2533, + SystemZ_VMRLF = 2534, + SystemZ_VMRLG = 2535, + SystemZ_VMRLH = 2536, + SystemZ_VMSL = 2537, + SystemZ_VMSLG = 2538, + SystemZ_VMSP = 2539, + SystemZ_VMX = 2540, + SystemZ_VMXB = 2541, + SystemZ_VMXF = 2542, + SystemZ_VMXG = 2543, + SystemZ_VMXH = 2544, + SystemZ_VMXL = 2545, + SystemZ_VMXLB = 2546, + SystemZ_VMXLF = 2547, + SystemZ_VMXLG = 2548, + SystemZ_VMXLH = 2549, + SystemZ_VN = 2550, + SystemZ_VNC = 2551, + SystemZ_VNN = 2552, + SystemZ_VNO = 2553, + SystemZ_VNX = 2554, + SystemZ_VO = 2555, + SystemZ_VOC = 2556, + SystemZ_VONE = 2557, + SystemZ_VPDI = 2558, + SystemZ_VPERM = 2559, + SystemZ_VPK = 2560, + SystemZ_VPKF = 2561, + SystemZ_VPKG = 2562, + SystemZ_VPKH = 2563, + SystemZ_VPKLS = 2564, + SystemZ_VPKLSF = 2565, + SystemZ_VPKLSFS = 2566, + SystemZ_VPKLSG = 2567, + SystemZ_VPKLSGS = 2568, + SystemZ_VPKLSH = 2569, + SystemZ_VPKLSHS = 2570, + SystemZ_VPKS = 2571, + SystemZ_VPKSF = 2572, + SystemZ_VPKSFS = 2573, + SystemZ_VPKSG = 2574, + SystemZ_VPKSGS = 2575, + SystemZ_VPKSH = 2576, + SystemZ_VPKSHS = 2577, + SystemZ_VPKZ = 2578, + SystemZ_VPOPCT = 2579, + SystemZ_VPOPCTB = 2580, + SystemZ_VPOPCTF = 2581, + SystemZ_VPOPCTG = 2582, + SystemZ_VPOPCTH = 2583, + SystemZ_VPSOP = 2584, + SystemZ_VREP = 2585, + SystemZ_VREPB = 2586, + SystemZ_VREPF = 2587, + SystemZ_VREPG = 2588, + SystemZ_VREPH = 2589, + SystemZ_VREPI = 2590, + SystemZ_VREPIB = 2591, + SystemZ_VREPIF = 2592, + SystemZ_VREPIG = 2593, + SystemZ_VREPIH = 2594, + SystemZ_VRP = 2595, + SystemZ_VS = 2596, + SystemZ_VSB = 2597, + SystemZ_VSBCBI = 2598, + SystemZ_VSBCBIQ = 2599, + SystemZ_VSBI = 2600, + SystemZ_VSBIQ = 2601, + SystemZ_VSCBI = 2602, + SystemZ_VSCBIB = 2603, + SystemZ_VSCBIF = 2604, + SystemZ_VSCBIG = 2605, + SystemZ_VSCBIH = 2606, + SystemZ_VSCBIQ = 2607, + SystemZ_VSCEF = 2608, + SystemZ_VSCEG = 2609, + SystemZ_VSDP = 2610, + SystemZ_VSEG = 2611, + SystemZ_VSEGB = 2612, + SystemZ_VSEGF = 2613, + SystemZ_VSEGH = 2614, + SystemZ_VSEL = 2615, + SystemZ_VSF = 2616, + SystemZ_VSG = 2617, + SystemZ_VSH = 2618, + SystemZ_VSL = 2619, + SystemZ_VSLB = 2620, + SystemZ_VSLDB = 2621, + SystemZ_VSP = 2622, + SystemZ_VSQ = 2623, + SystemZ_VSRA = 2624, + SystemZ_VSRAB = 2625, + SystemZ_VSRL = 2626, + SystemZ_VSRLB = 2627, + SystemZ_VSRP = 2628, + SystemZ_VST = 2629, + SystemZ_VSTEB = 2630, + SystemZ_VSTEF = 2631, + SystemZ_VSTEG = 2632, + SystemZ_VSTEH = 2633, + SystemZ_VSTL = 2634, + SystemZ_VSTM = 2635, + SystemZ_VSTRC = 2636, + SystemZ_VSTRCB = 2637, + SystemZ_VSTRCBS = 2638, + SystemZ_VSTRCF = 2639, + SystemZ_VSTRCFS = 2640, + SystemZ_VSTRCH = 2641, + SystemZ_VSTRCHS = 2642, + SystemZ_VSTRCZB = 2643, + SystemZ_VSTRCZBS = 2644, + SystemZ_VSTRCZF = 2645, + SystemZ_VSTRCZFS = 2646, + SystemZ_VSTRCZH = 2647, + SystemZ_VSTRCZHS = 2648, + SystemZ_VSTRL = 2649, + SystemZ_VSTRLR = 2650, + SystemZ_VSUM = 2651, + SystemZ_VSUMB = 2652, + SystemZ_VSUMG = 2653, + SystemZ_VSUMGF = 2654, + SystemZ_VSUMGH = 2655, + SystemZ_VSUMH = 2656, + SystemZ_VSUMQ = 2657, + SystemZ_VSUMQF = 2658, + SystemZ_VSUMQG = 2659, + SystemZ_VTM = 2660, + SystemZ_VTP = 2661, + SystemZ_VUPH = 2662, + SystemZ_VUPHB = 2663, + SystemZ_VUPHF = 2664, + SystemZ_VUPHH = 2665, + SystemZ_VUPKZ = 2666, + SystemZ_VUPL = 2667, + SystemZ_VUPLB = 2668, + SystemZ_VUPLF = 2669, + SystemZ_VUPLH = 2670, + SystemZ_VUPLHB = 2671, + SystemZ_VUPLHF = 2672, + SystemZ_VUPLHH = 2673, + SystemZ_VUPLHW = 2674, + SystemZ_VUPLL = 2675, + SystemZ_VUPLLB = 2676, + SystemZ_VUPLLF = 2677, + SystemZ_VUPLLH = 2678, + SystemZ_VX = 2679, + SystemZ_VZERO = 2680, + SystemZ_WCDGB = 2681, + SystemZ_WCDLGB = 2682, + SystemZ_WCGDB = 2683, + SystemZ_WCLGDB = 2684, + SystemZ_WFADB = 2685, + SystemZ_WFASB = 2686, + SystemZ_WFAXB = 2687, + SystemZ_WFC = 2688, + SystemZ_WFCDB = 2689, + SystemZ_WFCEDB = 2690, + SystemZ_WFCEDBS = 2691, + SystemZ_WFCESB = 2692, + SystemZ_WFCESBS = 2693, + SystemZ_WFCEXB = 2694, + SystemZ_WFCEXBS = 2695, + SystemZ_WFCHDB = 2696, + SystemZ_WFCHDBS = 2697, + SystemZ_WFCHEDB = 2698, + SystemZ_WFCHEDBS = 2699, + SystemZ_WFCHESB = 2700, + SystemZ_WFCHESBS = 2701, + SystemZ_WFCHEXB = 2702, + SystemZ_WFCHEXBS = 2703, + SystemZ_WFCHSB = 2704, + SystemZ_WFCHSBS = 2705, + SystemZ_WFCHXB = 2706, + SystemZ_WFCHXBS = 2707, + SystemZ_WFCSB = 2708, + SystemZ_WFCXB = 2709, + SystemZ_WFDDB = 2710, + SystemZ_WFDSB = 2711, + SystemZ_WFDXB = 2712, + SystemZ_WFIDB = 2713, + SystemZ_WFISB = 2714, + SystemZ_WFIXB = 2715, + SystemZ_WFK = 2716, + SystemZ_WFKDB = 2717, + SystemZ_WFKEDB = 2718, + SystemZ_WFKEDBS = 2719, + SystemZ_WFKESB = 2720, + SystemZ_WFKESBS = 2721, + SystemZ_WFKEXB = 2722, + SystemZ_WFKEXBS = 2723, + SystemZ_WFKHDB = 2724, + SystemZ_WFKHDBS = 2725, + SystemZ_WFKHEDB = 2726, + SystemZ_WFKHEDBS = 2727, + SystemZ_WFKHESB = 2728, + SystemZ_WFKHESBS = 2729, + SystemZ_WFKHEXB = 2730, + SystemZ_WFKHEXBS = 2731, + SystemZ_WFKHSB = 2732, + SystemZ_WFKHSBS = 2733, + SystemZ_WFKHXB = 2734, + SystemZ_WFKHXBS = 2735, + SystemZ_WFKSB = 2736, + SystemZ_WFKXB = 2737, + SystemZ_WFLCDB = 2738, + SystemZ_WFLCSB = 2739, + SystemZ_WFLCXB = 2740, + SystemZ_WFLLD = 2741, + SystemZ_WFLLS = 2742, + SystemZ_WFLNDB = 2743, + SystemZ_WFLNSB = 2744, + SystemZ_WFLNXB = 2745, + SystemZ_WFLPDB = 2746, + SystemZ_WFLPSB = 2747, + SystemZ_WFLPXB = 2748, + SystemZ_WFLRD = 2749, + SystemZ_WFLRX = 2750, + SystemZ_WFMADB = 2751, + SystemZ_WFMASB = 2752, + SystemZ_WFMAXB = 2753, + SystemZ_WFMAXDB = 2754, + SystemZ_WFMAXSB = 2755, + SystemZ_WFMAXXB = 2756, + SystemZ_WFMDB = 2757, + SystemZ_WFMINDB = 2758, + SystemZ_WFMINSB = 2759, + SystemZ_WFMINXB = 2760, + SystemZ_WFMSB = 2761, + SystemZ_WFMSDB = 2762, + SystemZ_WFMSSB = 2763, + SystemZ_WFMSXB = 2764, + SystemZ_WFMXB = 2765, + SystemZ_WFNMADB = 2766, + SystemZ_WFNMASB = 2767, + SystemZ_WFNMAXB = 2768, + SystemZ_WFNMSDB = 2769, + SystemZ_WFNMSSB = 2770, + SystemZ_WFNMSXB = 2771, + SystemZ_WFPSODB = 2772, + SystemZ_WFPSOSB = 2773, + SystemZ_WFPSOXB = 2774, + SystemZ_WFSDB = 2775, + SystemZ_WFSQDB = 2776, + SystemZ_WFSQSB = 2777, + SystemZ_WFSQXB = 2778, + SystemZ_WFSSB = 2779, + SystemZ_WFSXB = 2780, + SystemZ_WFTCIDB = 2781, + SystemZ_WFTCISB = 2782, + SystemZ_WFTCIXB = 2783, + SystemZ_WLDEB = 2784, + SystemZ_WLEDB = 2785, + SystemZ_X = 2786, + SystemZ_XC = 2787, + SystemZ_XG = 2788, + SystemZ_XGR = 2789, + SystemZ_XGRK = 2790, + SystemZ_XI = 2791, + SystemZ_XIHF = 2792, + SystemZ_XILF = 2793, + SystemZ_XIY = 2794, + SystemZ_XR = 2795, + SystemZ_XRK = 2796, + SystemZ_XSCH = 2797, + SystemZ_XY = 2798, + SystemZ_ZAP = 2799, + SystemZ_INSTRUCTION_LIST_END = 2800 + }; + +#endif // GET_INSTRINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenRegisterInfo.inc new file mode 100644 index 0000000..4a1bf9d --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenRegisterInfo.inc @@ -0,0 +1,741 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + SystemZ_NoRegister, + SystemZ_CC = 1, + SystemZ_A0 = 2, + SystemZ_A1 = 3, + SystemZ_A2 = 4, + SystemZ_A3 = 5, + SystemZ_A4 = 6, + SystemZ_A5 = 7, + SystemZ_A6 = 8, + SystemZ_A7 = 9, + SystemZ_A8 = 10, + SystemZ_A9 = 11, + SystemZ_A10 = 12, + SystemZ_A11 = 13, + SystemZ_A12 = 14, + SystemZ_A13 = 15, + SystemZ_A14 = 16, + SystemZ_A15 = 17, + SystemZ_C0 = 18, + SystemZ_C1 = 19, + SystemZ_C2 = 20, + SystemZ_C3 = 21, + SystemZ_C4 = 22, + SystemZ_C5 = 23, + SystemZ_C6 = 24, + SystemZ_C7 = 25, + SystemZ_C8 = 26, + SystemZ_C9 = 27, + SystemZ_C10 = 28, + SystemZ_C11 = 29, + SystemZ_C12 = 30, + SystemZ_C13 = 31, + SystemZ_C14 = 32, + SystemZ_C15 = 33, + SystemZ_V0 = 34, + SystemZ_V1 = 35, + SystemZ_V2 = 36, + SystemZ_V3 = 37, + SystemZ_V4 = 38, + SystemZ_V5 = 39, + SystemZ_V6 = 40, + SystemZ_V7 = 41, + SystemZ_V8 = 42, + SystemZ_V9 = 43, + SystemZ_V10 = 44, + SystemZ_V11 = 45, + SystemZ_V12 = 46, + SystemZ_V13 = 47, + SystemZ_V14 = 48, + SystemZ_V15 = 49, + SystemZ_V16 = 50, + SystemZ_V17 = 51, + SystemZ_V18 = 52, + SystemZ_V19 = 53, + SystemZ_V20 = 54, + SystemZ_V21 = 55, + SystemZ_V22 = 56, + SystemZ_V23 = 57, + SystemZ_V24 = 58, + SystemZ_V25 = 59, + SystemZ_V26 = 60, + SystemZ_V27 = 61, + SystemZ_V28 = 62, + SystemZ_V29 = 63, + SystemZ_V30 = 64, + SystemZ_V31 = 65, + SystemZ_F0D = 66, + SystemZ_F1D = 67, + SystemZ_F2D = 68, + SystemZ_F3D = 69, + SystemZ_F4D = 70, + SystemZ_F5D = 71, + SystemZ_F6D = 72, + SystemZ_F7D = 73, + SystemZ_F8D = 74, + SystemZ_F9D = 75, + SystemZ_F10D = 76, + SystemZ_F11D = 77, + SystemZ_F12D = 78, + SystemZ_F13D = 79, + SystemZ_F14D = 80, + SystemZ_F15D = 81, + SystemZ_F16D = 82, + SystemZ_F17D = 83, + SystemZ_F18D = 84, + SystemZ_F19D = 85, + SystemZ_F20D = 86, + SystemZ_F21D = 87, + SystemZ_F22D = 88, + SystemZ_F23D = 89, + SystemZ_F24D = 90, + SystemZ_F25D = 91, + SystemZ_F26D = 92, + SystemZ_F27D = 93, + SystemZ_F28D = 94, + SystemZ_F29D = 95, + SystemZ_F30D = 96, + SystemZ_F31D = 97, + SystemZ_F0Q = 98, + SystemZ_F1Q = 99, + SystemZ_F4Q = 100, + SystemZ_F5Q = 101, + SystemZ_F8Q = 102, + SystemZ_F9Q = 103, + SystemZ_F12Q = 104, + SystemZ_F13Q = 105, + SystemZ_F0S = 106, + SystemZ_F1S = 107, + SystemZ_F2S = 108, + SystemZ_F3S = 109, + SystemZ_F4S = 110, + SystemZ_F5S = 111, + SystemZ_F6S = 112, + SystemZ_F7S = 113, + SystemZ_F8S = 114, + SystemZ_F9S = 115, + SystemZ_F10S = 116, + SystemZ_F11S = 117, + SystemZ_F12S = 118, + SystemZ_F13S = 119, + SystemZ_F14S = 120, + SystemZ_F15S = 121, + SystemZ_F16S = 122, + SystemZ_F17S = 123, + SystemZ_F18S = 124, + SystemZ_F19S = 125, + SystemZ_F20S = 126, + SystemZ_F21S = 127, + SystemZ_F22S = 128, + SystemZ_F23S = 129, + SystemZ_F24S = 130, + SystemZ_F25S = 131, + SystemZ_F26S = 132, + SystemZ_F27S = 133, + SystemZ_F28S = 134, + SystemZ_F29S = 135, + SystemZ_F30S = 136, + SystemZ_F31S = 137, + SystemZ_R0D = 138, + SystemZ_R1D = 139, + SystemZ_R2D = 140, + SystemZ_R3D = 141, + SystemZ_R4D = 142, + SystemZ_R5D = 143, + SystemZ_R6D = 144, + SystemZ_R7D = 145, + SystemZ_R8D = 146, + SystemZ_R9D = 147, + SystemZ_R10D = 148, + SystemZ_R11D = 149, + SystemZ_R12D = 150, + SystemZ_R13D = 151, + SystemZ_R14D = 152, + SystemZ_R15D = 153, + SystemZ_R0H = 154, + SystemZ_R1H = 155, + SystemZ_R2H = 156, + SystemZ_R3H = 157, + SystemZ_R4H = 158, + SystemZ_R5H = 159, + SystemZ_R6H = 160, + SystemZ_R7H = 161, + SystemZ_R8H = 162, + SystemZ_R9H = 163, + SystemZ_R10H = 164, + SystemZ_R11H = 165, + SystemZ_R12H = 166, + SystemZ_R13H = 167, + SystemZ_R14H = 168, + SystemZ_R15H = 169, + SystemZ_R0L = 170, + SystemZ_R1L = 171, + SystemZ_R2L = 172, + SystemZ_R3L = 173, + SystemZ_R4L = 174, + SystemZ_R5L = 175, + SystemZ_R6L = 176, + SystemZ_R7L = 177, + SystemZ_R8L = 178, + SystemZ_R9L = 179, + SystemZ_R10L = 180, + SystemZ_R11L = 181, + SystemZ_R12L = 182, + SystemZ_R13L = 183, + SystemZ_R14L = 184, + SystemZ_R15L = 185, + SystemZ_R0Q = 186, + SystemZ_R2Q = 187, + SystemZ_R4Q = 188, + SystemZ_R6Q = 189, + SystemZ_R8Q = 190, + SystemZ_R10Q = 191, + SystemZ_R12Q = 192, + SystemZ_R14Q = 193, + SystemZ_NUM_TARGET_REGS // 194 +}; + +// Register classes +enum { + SystemZ_GRX32BitRegClassID = 0, + SystemZ_VR32BitRegClassID = 1, + SystemZ_AR32BitRegClassID = 2, + SystemZ_FP32BitRegClassID = 3, + SystemZ_GR32BitRegClassID = 4, + SystemZ_GRH32BitRegClassID = 5, + SystemZ_ADDR32BitRegClassID = 6, + SystemZ_CCRRegClassID = 7, + SystemZ_AnyRegBitRegClassID = 8, + SystemZ_AnyRegBit_with_subreg_r32RegClassID = 9, + SystemZ_VR64BitRegClassID = 10, + SystemZ_AnyRegBit_with_subreg_r64RegClassID = 11, + SystemZ_CR64BitRegClassID = 12, + SystemZ_FP64BitRegClassID = 13, + SystemZ_GR64BitRegClassID = 14, + SystemZ_ADDR64BitRegClassID = 15, + SystemZ_VR128BitRegClassID = 16, + SystemZ_VF128BitRegClassID = 17, + SystemZ_FP128BitRegClassID = 18, + SystemZ_GR128BitRegClassID = 19, + SystemZ_ADDR128BitRegClassID = 20, +}; +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg SystemZRegDiffLists[] = { + /* 0 */ 64857, 1, 1, 1, 0, + /* 5 */ 65325, 1, 0, + /* 8 */ 65471, 2, 0, + /* 11 */ 65473, 2, 0, + /* 14 */ 65475, 2, 0, + /* 17 */ 65477, 2, 0, + /* 20 */ 32, 40, 0, + /* 23 */ 65506, 40, 65494, 40, 0, + /* 28 */ 65508, 40, 65494, 40, 0, + /* 33 */ 65510, 40, 65494, 40, 0, + /* 38 */ 65512, 40, 65494, 40, 0, + /* 43 */ 65504, 40, 0, + /* 46 */ 65520, 40, 0, + /* 49 */ 65504, 41, 0, + /* 52 */ 65520, 41, 0, + /* 55 */ 65504, 42, 0, + /* 58 */ 65520, 42, 0, + /* 61 */ 65504, 43, 0, + /* 64 */ 65520, 43, 0, + /* 67 */ 65504, 44, 0, + /* 70 */ 65520, 44, 0, + /* 73 */ 65504, 45, 0, + /* 76 */ 65520, 45, 0, + /* 79 */ 65504, 46, 0, + /* 82 */ 65520, 46, 0, + /* 85 */ 65504, 47, 0, + /* 88 */ 65520, 47, 0, + /* 91 */ 65504, 48, 0, + /* 94 */ 65520, 48, 0, + /* 97 */ 65496, 65504, 56, 0, + /* 101 */ 65496, 65504, 58, 0, + /* 105 */ 65496, 65504, 60, 0, + /* 109 */ 65496, 65504, 62, 0, + /* 113 */ 65496, 65504, 64, 0, + /* 117 */ 65261, 0, + /* 119 */ 65294, 0, + /* 121 */ 65463, 0, + /* 123 */ 65503, 0, + /* 125 */ 65496, 65504, 0, + /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, + /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, + /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, + /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, + /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, + /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, + /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, + /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, + /* 184 */ 65535, 0, +}; + +static const uint16_t SystemZSubRegIdxLists[] = { + /* 0 */ 6, 1, 0, + /* 3 */ 7, 6, 1, 2, 4, 3, 0, + /* 10 */ 7, 8, 2, 5, 0, + /* 15 */ 9, 8, 0, +}; + +static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 226, 4, 4, 2, 2945, 0 }, + { 20, 4, 4, 2, 2945, 0 }, + { 49, 4, 4, 2, 2945, 0 }, + { 74, 4, 4, 2, 2945, 0 }, + { 99, 4, 4, 2, 2945, 0 }, + { 124, 4, 4, 2, 2945, 0 }, + { 149, 4, 4, 2, 2945, 0 }, + { 166, 4, 4, 2, 2945, 0 }, + { 183, 4, 4, 2, 2945, 0 }, + { 200, 4, 4, 2, 2945, 0 }, + { 217, 4, 4, 2, 2945, 0 }, + { 0, 4, 4, 2, 2945, 0 }, + { 29, 4, 4, 2, 2945, 0 }, + { 58, 4, 4, 2, 2945, 0 }, + { 83, 4, 4, 2, 2945, 0 }, + { 108, 4, 4, 2, 2945, 0 }, + { 133, 4, 4, 2, 2945, 0 }, + { 23, 4, 4, 2, 2945, 0 }, + { 52, 4, 4, 2, 2945, 0 }, + { 77, 4, 4, 2, 2945, 0 }, + { 102, 4, 4, 2, 2945, 0 }, + { 127, 4, 4, 2, 2945, 0 }, + { 152, 4, 4, 2, 2945, 0 }, + { 169, 4, 4, 2, 2945, 0 }, + { 186, 4, 4, 2, 2945, 0 }, + { 203, 4, 4, 2, 2945, 0 }, + { 220, 4, 4, 2, 2945, 0 }, + { 4, 4, 4, 2, 2945, 0 }, + { 33, 4, 4, 2, 2945, 0 }, + { 62, 4, 4, 2, 2945, 0 }, + { 87, 4, 4, 2, 2945, 0 }, + { 112, 4, 4, 2, 2945, 0 }, + { 137, 4, 4, 2, 2945, 0 }, + { 26, 20, 4, 15, 2945, 8 }, + { 55, 20, 4, 15, 2945, 8 }, + { 80, 20, 4, 15, 2945, 8 }, + { 105, 20, 4, 15, 2945, 8 }, + { 130, 20, 4, 15, 2945, 8 }, + { 155, 20, 4, 15, 2945, 8 }, + { 172, 20, 4, 15, 2945, 8 }, + { 189, 20, 4, 15, 2945, 8 }, + { 206, 20, 4, 15, 2945, 8 }, + { 223, 20, 4, 15, 2945, 8 }, + { 8, 20, 4, 15, 2945, 8 }, + { 37, 20, 4, 15, 2945, 8 }, + { 66, 20, 4, 15, 2945, 8 }, + { 91, 20, 4, 15, 2945, 8 }, + { 116, 20, 4, 15, 2945, 8 }, + { 141, 20, 4, 15, 2945, 8 }, + { 158, 20, 4, 15, 2945, 8 }, + { 175, 20, 4, 15, 2945, 8 }, + { 192, 20, 4, 15, 2945, 8 }, + { 209, 20, 4, 15, 2945, 8 }, + { 12, 20, 4, 15, 2945, 8 }, + { 41, 20, 4, 15, 2945, 8 }, + { 70, 20, 4, 15, 2945, 8 }, + { 95, 20, 4, 15, 2945, 8 }, + { 120, 20, 4, 15, 2945, 8 }, + { 145, 20, 4, 15, 2945, 8 }, + { 162, 20, 4, 15, 2945, 8 }, + { 179, 20, 4, 15, 2945, 8 }, + { 196, 20, 4, 15, 2945, 8 }, + { 213, 20, 4, 15, 2945, 8 }, + { 16, 20, 4, 15, 2945, 8 }, + { 45, 20, 4, 15, 2945, 8 }, + { 249, 21, 114, 16, 1969, 8 }, + { 277, 21, 114, 16, 1969, 8 }, + { 300, 21, 110, 16, 1969, 8 }, + { 323, 21, 110, 16, 1969, 8 }, + { 346, 21, 110, 16, 1969, 8 }, + { 369, 21, 110, 16, 1969, 8 }, + { 387, 21, 106, 16, 1969, 8 }, + { 405, 21, 106, 16, 1969, 8 }, + { 423, 21, 106, 16, 1969, 8 }, + { 441, 21, 106, 16, 1969, 8 }, + { 229, 21, 102, 16, 1969, 8 }, + { 257, 21, 102, 16, 1969, 8 }, + { 285, 21, 102, 16, 1969, 8 }, + { 308, 21, 102, 16, 1969, 8 }, + { 331, 21, 98, 16, 1969, 8 }, + { 354, 21, 98, 16, 1969, 8 }, + { 377, 21, 126, 16, 1969, 8 }, + { 395, 21, 126, 16, 1969, 8 }, + { 413, 21, 126, 16, 1969, 8 }, + { 431, 21, 126, 16, 1969, 8 }, + { 239, 21, 126, 16, 1969, 8 }, + { 267, 21, 126, 16, 1969, 8 }, + { 295, 21, 126, 16, 1969, 8 }, + { 318, 21, 126, 16, 1969, 8 }, + { 341, 21, 126, 16, 1969, 8 }, + { 364, 21, 126, 16, 1969, 8 }, + { 382, 21, 126, 16, 1969, 8 }, + { 400, 21, 126, 16, 1969, 8 }, + { 418, 21, 126, 16, 1969, 8 }, + { 436, 21, 126, 16, 1969, 8 }, + { 244, 21, 126, 16, 1969, 8 }, + { 272, 21, 126, 16, 1969, 8 }, + { 594, 23, 4, 10, 129, 7 }, + { 602, 23, 4, 10, 129, 7 }, + { 630, 28, 4, 10, 177, 7 }, + { 638, 28, 4, 10, 177, 7 }, + { 646, 33, 4, 10, 225, 7 }, + { 654, 33, 4, 10, 225, 7 }, + { 606, 38, 4, 10, 273, 7 }, + { 620, 38, 4, 10, 273, 7 }, + { 673, 4, 113, 2, 1937, 0 }, + { 692, 4, 113, 2, 1937, 0 }, + { 706, 4, 109, 2, 1937, 0 }, + { 720, 4, 109, 2, 1937, 0 }, + { 734, 4, 109, 2, 1937, 0 }, + { 748, 4, 109, 2, 1937, 0 }, + { 762, 4, 105, 2, 1937, 0 }, + { 776, 4, 105, 2, 1937, 0 }, + { 790, 4, 105, 2, 1937, 0 }, + { 804, 4, 105, 2, 1937, 0 }, + { 658, 4, 101, 2, 1937, 0 }, + { 677, 4, 101, 2, 1937, 0 }, + { 696, 4, 101, 2, 1937, 0 }, + { 710, 4, 101, 2, 1937, 0 }, + { 724, 4, 97, 2, 1937, 0 }, + { 738, 4, 97, 2, 1937, 0 }, + { 752, 4, 125, 2, 1937, 0 }, + { 766, 4, 125, 2, 1937, 0 }, + { 780, 4, 125, 2, 1937, 0 }, + { 794, 4, 125, 2, 1937, 0 }, + { 663, 4, 125, 2, 1937, 0 }, + { 682, 4, 125, 2, 1937, 0 }, + { 701, 4, 125, 2, 1937, 0 }, + { 715, 4, 125, 2, 1937, 0 }, + { 729, 4, 125, 2, 1937, 0 }, + { 743, 4, 125, 2, 1937, 0 }, + { 757, 4, 125, 2, 1937, 0 }, + { 771, 4, 125, 2, 1937, 0 }, + { 785, 4, 125, 2, 1937, 0 }, + { 799, 4, 125, 2, 1937, 0 }, + { 668, 4, 125, 2, 1937, 0 }, + { 687, 4, 125, 2, 1937, 0 }, + { 253, 132, 92, 0, 82, 4 }, + { 281, 132, 86, 0, 82, 4 }, + { 304, 132, 86, 0, 82, 4 }, + { 327, 132, 80, 0, 82, 4 }, + { 350, 132, 80, 0, 82, 4 }, + { 373, 132, 74, 0, 82, 4 }, + { 391, 132, 74, 0, 82, 4 }, + { 409, 132, 68, 0, 82, 4 }, + { 427, 132, 68, 0, 82, 4 }, + { 445, 132, 62, 0, 82, 4 }, + { 234, 132, 62, 0, 82, 4 }, + { 262, 132, 56, 0, 82, 4 }, + { 290, 132, 56, 0, 82, 4 }, + { 313, 132, 50, 0, 82, 4 }, + { 336, 132, 50, 0, 82, 4 }, + { 359, 132, 21, 0, 82, 4 }, + { 454, 4, 94, 2, 1906, 0 }, + { 463, 4, 88, 2, 1906, 0 }, + { 472, 4, 88, 2, 1906, 0 }, + { 481, 4, 82, 2, 1906, 0 }, + { 490, 4, 82, 2, 1906, 0 }, + { 499, 4, 76, 2, 1906, 0 }, + { 503, 4, 76, 2, 1906, 0 }, + { 507, 4, 70, 2, 1906, 0 }, + { 511, 4, 70, 2, 1906, 0 }, + { 515, 4, 64, 2, 1906, 0 }, + { 449, 4, 64, 2, 1906, 0 }, + { 458, 4, 58, 2, 1906, 0 }, + { 467, 4, 58, 2, 1906, 0 }, + { 476, 4, 52, 2, 1906, 0 }, + { 485, 4, 52, 2, 1906, 0 }, + { 494, 4, 46, 2, 1906, 0 }, + { 524, 4, 91, 2, 1874, 0 }, + { 533, 4, 85, 2, 1874, 0 }, + { 542, 4, 85, 2, 1874, 0 }, + { 551, 4, 79, 2, 1874, 0 }, + { 560, 4, 79, 2, 1874, 0 }, + { 569, 4, 73, 2, 1874, 0 }, + { 573, 4, 73, 2, 1874, 0 }, + { 577, 4, 67, 2, 1874, 0 }, + { 581, 4, 67, 2, 1874, 0 }, + { 585, 4, 61, 2, 1874, 0 }, + { 519, 4, 61, 2, 1874, 0 }, + { 528, 4, 55, 2, 1874, 0 }, + { 537, 4, 55, 2, 1874, 0 }, + { 546, 4, 49, 2, 1874, 0 }, + { 555, 4, 49, 2, 1874, 0 }, + { 564, 4, 43, 2, 1874, 0 }, + { 598, 128, 4, 3, 4, 2 }, + { 616, 135, 4, 3, 4, 2 }, + { 634, 142, 4, 3, 4, 2 }, + { 642, 149, 4, 3, 4, 2 }, + { 650, 156, 4, 3, 4, 2 }, + { 589, 163, 4, 3, 4, 2 }, + { 611, 170, 4, 3, 4, 2 }, + { 625, 177, 4, 3, 4, 2 }, +}; + + // GRX32Bit Register Class... + static const MCPhysReg GRX32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H, + }; + + // GRX32Bit Bit set. + static const uint8_t GRX32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + }; + + // VR32Bit Register Class... + static const MCPhysReg VR32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, + }; + + // VR32Bit Bit set. + static const uint8_t VR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + }; + + // AR32Bit Register Class... + static const MCPhysReg AR32Bit[] = { + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, + }; + + // AR32Bit Bit set. + static const uint8_t AR32BitBits[] = { + 0xfc, 0xff, 0x03, + }; + + // FP32Bit Register Class... + static const MCPhysReg FP32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, + }; + + // FP32Bit Bit set. + static const uint8_t FP32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // GR32Bit Register Class... + static const MCPhysReg GR32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, + }; + + // GR32Bit Bit set. + static const uint8_t GR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // GRH32Bit Register Class... + static const MCPhysReg GRH32Bit[] = { + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, + }; + + // GRH32Bit Bit set. + static const uint8_t GRH32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // ADDR32Bit Register Class... + static const MCPhysReg ADDR32Bit[] = { + SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, + }; + + // ADDR32Bit Bit set. + static const uint8_t ADDR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, + }; + + // CCR Register Class... + static const MCPhysReg CCR[] = { + SystemZ_CC, + }; + + // CCR Bit set. + static const uint8_t CCRBits[] = { + 0x02, + }; + + // AnyRegBit Register Class... + static const MCPhysReg AnyRegBit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + }; + + // AnyRegBit Bit set. + static const uint8_t AnyRegBitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // AnyRegBit_with_subreg_r32 Register Class... + static const MCPhysReg AnyRegBit_with_subreg_r32[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + }; + + // AnyRegBit_with_subreg_r32 Bit set. + static const uint8_t AnyRegBit_with_subreg_r32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, + }; + + // VR64Bit Register Class... + static const MCPhysReg VR64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, + }; + + // VR64Bit Bit set. + static const uint8_t VR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + }; + + // AnyRegBit_with_subreg_r64 Register Class... + static const MCPhysReg AnyRegBit_with_subreg_r64[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + }; + + // AnyRegBit_with_subreg_r64 Bit set. + static const uint8_t AnyRegBit_with_subreg_r64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // CR64Bit Register Class... + static const MCPhysReg CR64Bit[] = { + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, + }; + + // CR64Bit Bit set. + static const uint8_t CR64BitBits[] = { + 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // FP64Bit Register Class... + static const MCPhysReg FP64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, + }; + + // FP64Bit Bit set. + static const uint8_t FP64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // GR64Bit Register Class... + static const MCPhysReg GR64Bit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, + }; + + // GR64Bit Bit set. + static const uint8_t GR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // ADDR64Bit Register Class... + static const MCPhysReg ADDR64Bit[] = { + SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, + }; + + // ADDR64Bit Bit set. + static const uint8_t ADDR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, + }; + + // VR128Bit Register Class... + static const MCPhysReg VR128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + }; + + // VR128Bit Bit set. + static const uint8_t VR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, + }; + + // VF128Bit Register Class... + static const MCPhysReg VF128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + }; + + // VF128Bit Bit set. + static const uint8_t VF128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + + // FP128Bit Register Class... + static const MCPhysReg FP128Bit[] = { + SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, + }; + + // FP128Bit Bit set. + static const uint8_t FP128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + + // GR128Bit Register Class... + static const MCPhysReg GR128Bit[] = { + SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, + }; + + // GR128Bit Bit set. + static const uint8_t GR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + + // ADDR128Bit Register Class... + static const MCPhysReg ADDR128Bit[] = { + SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, + }; + + // ADDR128Bit Bit set. + static const uint8_t ADDR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, + }; + +static const MCRegisterClass SystemZMCRegisterClasses[] = { + { GRX32Bit, GRX32BitBits, 107, 32, sizeof(GRX32BitBits), SystemZ_GRX32BitRegClassID, 4, 1, true }, + { VR32Bit, VR32BitBits, 99, 32, sizeof(VR32BitBits), SystemZ_VR32BitRegClassID, 4, 1, true }, + { AR32Bit, AR32BitBits, 73, 16, sizeof(AR32BitBits), SystemZ_AR32BitRegClassID, 4, 1, false }, + { FP32Bit, FP32BitBits, 65, 16, sizeof(FP32BitBits), SystemZ_FP32BitRegClassID, 4, 1, true }, + { GR32Bit, GR32BitBits, 91, 16, sizeof(GR32BitBits), SystemZ_GR32BitRegClassID, 4, 1, true }, + { GRH32Bit, GRH32BitBits, 56, 16, sizeof(GRH32BitBits), SystemZ_GRH32BitRegClassID, 4, 1, true }, + { ADDR32Bit, ADDR32BitBits, 81, 15, sizeof(ADDR32BitBits), SystemZ_ADDR32BitRegClassID, 4, 1, true }, + { CCR, CCRBits, 52, 1, sizeof(CCRBits), SystemZ_CCRRegClassID, 4, -1, false }, + { AnyRegBit, AnyRegBitBits, 205, 48, sizeof(AnyRegBitBits), SystemZ_AnyRegBitRegClassID, 8, 1, false }, + { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, 0, 32, sizeof(AnyRegBit_with_subreg_r32Bits), SystemZ_AnyRegBit_with_subreg_r32RegClassID, 8, 1, false }, + { VR64Bit, VR64BitBits, 150, 32, sizeof(VR64BitBits), SystemZ_VR64BitRegClassID, 8, 1, true }, + { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, 26, 16, sizeof(AnyRegBit_with_subreg_r64Bits), SystemZ_AnyRegBit_with_subreg_r64RegClassID, 8, 1, false }, + { CR64Bit, CR64BitBits, 124, 16, sizeof(CR64BitBits), SystemZ_CR64BitRegClassID, 8, 1, false }, + { FP64Bit, FP64BitBits, 116, 16, sizeof(FP64BitBits), SystemZ_FP64BitRegClassID, 8, 1, true }, + { GR64Bit, GR64BitBits, 142, 16, sizeof(GR64BitBits), SystemZ_GR64BitRegClassID, 8, 1, true }, + { ADDR64Bit, ADDR64BitBits, 132, 15, sizeof(ADDR64BitBits), SystemZ_ADDR64BitRegClassID, 8, 1, true }, + { VR128Bit, VR128BitBits, 196, 32, sizeof(VR128BitBits), SystemZ_VR128BitRegClassID, 16, 1, true }, + { VF128Bit, VF128BitBits, 158, 16, sizeof(VF128BitBits), SystemZ_VF128BitRegClassID, 16, 1, true }, + { FP128Bit, FP128BitBits, 167, 8, sizeof(FP128BitBits), SystemZ_FP128BitRegClassID, 16, 1, true }, + { GR128Bit, GR128BitBits, 187, 8, sizeof(GR128BitBits), SystemZ_GR128BitRegClassID, 16, 1, true }, + { ADDR128Bit, ADDR128BitBits, 176, 7, sizeof(ADDR128BitBits), SystemZ_ADDR128BitRegClassID, 16, 1, true }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenSubtargetInfo.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenSubtargetInfo.inc new file mode 100644 index 0000000..4d62b72 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZGenSubtargetInfo.inc @@ -0,0 +1,49 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_SUBTARGETINFO_ENUM +#undef GET_SUBTARGETINFO_ENUM + +enum { + SystemZ_FeatureDFPPackedConversion = 1ULL << 0, + SystemZ_FeatureDFPZonedConversion = 1ULL << 1, + SystemZ_FeatureDistinctOps = 1ULL << 2, + SystemZ_FeatureEnhancedDAT2 = 1ULL << 3, + SystemZ_FeatureExecutionHint = 1ULL << 4, + SystemZ_FeatureFPExtension = 1ULL << 5, + SystemZ_FeatureFastSerialization = 1ULL << 6, + SystemZ_FeatureGuardedStorage = 1ULL << 7, + SystemZ_FeatureHighWord = 1ULL << 8, + SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9, + SystemZ_FeatureInterlockedAccess1 = 1ULL << 10, + SystemZ_FeatureLoadAndTrap = 1ULL << 11, + SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12, + SystemZ_FeatureLoadStoreOnCond = 1ULL << 13, + SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14, + SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15, + SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16, + SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17, + SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18, + SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19, + SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20, + SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21, + SystemZ_FeaturePopulationCount = 1ULL << 22, + SystemZ_FeatureProcessorAssist = 1ULL << 23, + SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24, + SystemZ_FeatureTransactionalExecution = 1ULL << 25, + SystemZ_FeatureVector = 1ULL << 26, + SystemZ_FeatureVectorEnhancements1 = 1ULL << 27, + SystemZ_FeatureVectorPackedDecimal = 1ULL << 28, +}; + +#endif // GET_SUBTARGETINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.c b/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.c new file mode 100644 index 0000000..b722a41 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.c @@ -0,0 +1,434 @@ +//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an SystemZ MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SYSZ + +#include +#include +#include +#include + +#include "SystemZInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "SystemZMapping.h" + +static const char *getRegisterName(unsigned RegNo); + +void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + /* + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + */ +} + +static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) +{ + printInt64(O, Disp); + + if (Base) { + SStream_concat0(O, "("); + if (Index) + SStream_concat(O, "%%%s, ", getRegisterName(Index)); + SStream_concat(O, "%%%s)", getRegisterName(Base)); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } else if (!Index) { + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } else { + SStream_concat(O, "(%%%s)", getRegisterName(Index)); + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } +} + +static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) +{ + if (MCOperand_isReg(MO)) { + unsigned reg; + + reg = MCOperand_getReg(MO); + SStream_concat(O, "%%%s", getRegisterName(reg)); + reg = SystemZ_map_register(reg); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg; + MI->flat_insn->detail->sysz.op_count++; + } + } else if (MCOperand_isImm(MO)) { + int64_t Imm = MCOperand_getImm(MO); + + printInt64(O, Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm; + MI->flat_insn->detail->sysz.op_count++; + } + } +} + +static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<1>(Value) && "Invalid u1imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<2>(Value) && "Invalid u2imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<3>(Value) && "Invalid u4imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<4>(Value) && "Invalid u4imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<6>(Value) && "Invalid u6imm argument"); + + printUInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<8>(Value) && "Invalid s8imm argument"); + + if (Value >= 0) { + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + } else { + if (Value < -HEX_THRESHOLD) + SStream_concat(O, "-0x%x", -Value); + else + SStream_concat(O, "-%u", -Value); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<8>(Value) && "Invalid u8imm argument"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<12>(Value) && "Invalid u12imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<16>(Value) && "Invalid s16imm argument"); + + if (Value >= 0) { + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + } else { + if (Value < -HEX_THRESHOLD) + SStream_concat(O, "-0x%x", -Value); + else + SStream_concat(O, "-%u", -Value); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<16>(Value) && "Invalid u16imm argument"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<32>(Value) && "Invalid s32imm argument"); + + printInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<32>(Value) && "Invalid u32imm argument"); + + printUInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) +{ + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<48>(Value) && "Invalid u48imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + int32_t imm; + + if (MCOperand_isImm(MO)) { + imm = (int32_t)MCOperand_getImm(MO); + + printInt32(O, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)imm; + MI->flat_insn->detail->sysz.op_count++; + } + } +} + +static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O) +{ + // Output the PC-relative operand. + printPCRelOperand(MI, OpNum, O); +} + +static void printOperand(MCInst *MI, int OpNum, SStream *O) +{ + _printOperand(MI, MCInst_getOperand(MI, OpNum), O); +} + +static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) +{ + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O); +} + +static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) +{ + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); +} + +static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) +{ + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); + + if (Disp > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, Disp); + else + SStream_concat(O, "%"PRIu64, Disp); + + if (Length > HEX_THRESHOLD) + SStream_concat(O, "(0x%"PRIx64, Length); + else + SStream_concat(O, "(%"PRIu64, Length); + + if (Base) + SStream_concat(O, ", %%%s", getRegisterName(Base)); + SStream_concat0(O, ")"); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) +{ + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)); + + if (Disp > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, Disp); + else + SStream_concat(O, "%"PRIu64, Disp); + + SStream_concat0(O, "("); + SStream_concat(O, "%%%s", getRegisterName((unsigned int)Length)); + + if (Base) + SStream_concat(O, ", %%%s", getRegisterName(Base)); + SStream_concat0(O, ")"); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register((unsigned int)Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register((unsigned int)Length); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; + MI->flat_insn->detail->sysz.op_count++; + } +} + +static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) +{ + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); +} + +static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) +{ + static const char *const CondNames[] = { + "o", "h", "nle", "l", "nhe", "lh", "ne", + "e", "nlh", "he", "nl", "le", "nh", "no" + }; + + uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(Imm > 0 && Imm < 15 && "Invalid condition"); + SStream_concat0(O, CondNames[Imm - 1]); + + if (MI->csh->detail) + MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm; +} + +#define PRINT_ALIAS_INSTR +#include "SystemZGenAsmWriter.inc" + +void SystemZ_printInst(MCInst *MI, SStream *O, void *Info) +{ + printInstruction(MI, O, Info); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.h b/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.h new file mode 100644 index 0000000..68367ac --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZInstPrinter.h @@ -0,0 +1,15 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SYSZINSTPRINTER_H +#define CS_SYSZINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); + +void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.c b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.c new file mode 100644 index 0000000..37b852f --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.c @@ -0,0 +1,144 @@ +//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SYSZ + +#include "SystemZMCTargetDesc.h" + +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" + +const unsigned SystemZMC_GR32Regs[16] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, + SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, + SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, + SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L +}; + +const unsigned SystemZMC_GRH32Regs[16] = { + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, + SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, + SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H +}; + +const unsigned SystemZMC_GR64Regs[16] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, + SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, + SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, + SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D +}; + +const unsigned SystemZMC_GR128Regs[16] = { + SystemZ_R0Q, 0, SystemZ_R2Q, 0, + SystemZ_R4Q, 0, SystemZ_R6Q, 0, + SystemZ_R8Q, 0, SystemZ_R10Q, 0, + SystemZ_R12Q, 0, SystemZ_R14Q, 0 +}; + +const unsigned SystemZMC_FP32Regs[16] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S +}; + +const unsigned SystemZMC_FP64Regs[16] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D +}; + +const unsigned SystemZMC_FP128Regs[16] = { + SystemZ_F0Q, SystemZ_F1Q, 0, 0, + SystemZ_F4Q, SystemZ_F5Q, 0, 0, + SystemZ_F8Q, SystemZ_F9Q, 0, 0, + SystemZ_F12Q, SystemZ_F13Q, 0, 0 +}; + +const unsigned SystemZMC_VR32Regs[32] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, + SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, + SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, + SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, + SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S +}; + +const unsigned SystemZMC_VR64Regs[32] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, + SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, + SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, + SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, + SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D +}; + +const unsigned SystemZMC_VR128Regs[32] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, + SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, + SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, + SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, + SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, + SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31 +}; + +const unsigned SystemZMC_AR32Regs[16] = { + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, + SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, + SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, + SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15 +}; + +const unsigned SystemZMC_CR64Regs[16] = { + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, + SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, + SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, + SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15 +}; + +unsigned SystemZMC_getFirstReg(unsigned Reg) +{ + static unsigned Map[SystemZ_NUM_TARGET_REGS]; + static int Initialized = 0; + unsigned I; + + if (!Initialized) { + Initialized = 1; + for (I = 0; I < 16; ++I) { + Map[SystemZMC_GR32Regs[I]] = I; + Map[SystemZMC_GRH32Regs[I]] = I; + Map[SystemZMC_GR64Regs[I]] = I; + Map[SystemZMC_GR128Regs[I]] = I; + Map[SystemZMC_FP32Regs[I]] = I; + Map[SystemZMC_FP64Regs[I]] = I; + Map[SystemZMC_FP128Regs[I]] = I; + Map[SystemZMC_VR32Regs[I]] = I; + Map[SystemZMC_VR64Regs[I]] = I; + Map[SystemZMC_VR128Regs[I]] = I; + Map[SystemZMC_AR32Regs[I]] = I; + Map[SystemZMC_CR64Regs[I]] = I; + } + } + + // assert(Reg < SystemZ_NUM_TARGET_REGS); + return Map[Reg]; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.h b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.h new file mode 100644 index 0000000..972a7e2 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMCTargetDesc.h @@ -0,0 +1,51 @@ +//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SYSTEMZMCTARGETDESC_H +#define CS_SYSTEMZMCTARGETDESC_H + +// Maps of asm register numbers to LLVM register numbers, with 0 indicating +// an invalid register. In principle we could use 32-bit and 64-bit register +// classes directly, provided that we relegated the GPR allocation order +// in SystemZRegisterInfo.td to an AltOrder and left the default order +// as %r0-%r15. It seems better to provide the same interface for +// all classes though. +extern const unsigned SystemZMC_GR32Regs[16]; +extern const unsigned SystemZMC_GRH32Regs[16]; +extern const unsigned SystemZMC_GR64Regs[16]; +extern const unsigned SystemZMC_GR128Regs[16]; +extern const unsigned SystemZMC_FP32Regs[16]; +extern const unsigned SystemZMC_FP64Regs[16]; +extern const unsigned SystemZMC_FP128Regs[16]; +extern const unsigned SystemZMC_VR32Regs[32]; +extern const unsigned SystemZMC_VR64Regs[32]; +extern const unsigned SystemZMC_VR128Regs[32]; +extern const unsigned SystemZMC_AR32Regs[16]; +extern const unsigned SystemZMC_CR64Regs[16]; + +// Return the 0-based number of the first architectural register that +// contains the given LLVM register. E.g. R1D -> 1. +unsigned SystemZMC_getFirstReg(unsigned Reg); + +// Defines symbolic names for SystemZ registers. +// This defines a mapping from register name to register number. +//#define GET_REGINFO_ENUM +//#include "SystemZGenRegisterInfo.inc" + +// Defines symbolic names for the SystemZ instructions. +//#define GET_INSTRINFO_ENUM +//#include "SystemZGenInstrInfo.inc" + +//#define GET_SUBTARGETINFO_ENUM +//#include "SystemZGenSubtargetInfo.inc" + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.c b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.c new file mode 100644 index 0000000..90b4ff3 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.c @@ -0,0 +1,479 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SYSZ + +#include // debug +#include + +#include "../../utils.h" + +#include "SystemZMapping.h" + +#define GET_INSTRINFO_ENUM +#include "SystemZGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { SYSZ_REG_INVALID, NULL }, + + { SYSZ_REG_0, "0" }, + { SYSZ_REG_1, "1" }, + { SYSZ_REG_2, "2" }, + { SYSZ_REG_3, "3" }, + { SYSZ_REG_4, "4" }, + { SYSZ_REG_5, "5" }, + { SYSZ_REG_6, "6" }, + { SYSZ_REG_7, "7" }, + { SYSZ_REG_8, "8" }, + { SYSZ_REG_9, "9" }, + { SYSZ_REG_10, "10" }, + { SYSZ_REG_11, "11" }, + { SYSZ_REG_12, "12" }, + { SYSZ_REG_13, "13" }, + { SYSZ_REG_14, "14" }, + { SYSZ_REG_15, "15" }, + { SYSZ_REG_CC, "cc"}, + { SYSZ_REG_F0, "f0" }, + { SYSZ_REG_F1, "f1" }, + { SYSZ_REG_F2, "f2" }, + { SYSZ_REG_F3, "f3" }, + { SYSZ_REG_F4, "f4" }, + { SYSZ_REG_F5, "f5" }, + { SYSZ_REG_F6, "f6" }, + { SYSZ_REG_F7, "f7" }, + { SYSZ_REG_F8, "f8" }, + { SYSZ_REG_F9, "f9" }, + { SYSZ_REG_F10, "f10" }, + { SYSZ_REG_F11, "f11" }, + { SYSZ_REG_F12, "f12" }, + { SYSZ_REG_F13, "f13" }, + { SYSZ_REG_F14, "f14" }, + { SYSZ_REG_F15, "f15" }, + { SYSZ_REG_R0L, "r0l" }, + { SYSZ_REG_A0, "a0" }, + { SYSZ_REG_A1, "a1" }, + { SYSZ_REG_A2, "a2" }, + { SYSZ_REG_A3, "a3" }, + { SYSZ_REG_A4, "a4" }, + { SYSZ_REG_A5, "a5" }, + { SYSZ_REG_A6, "a6" }, + { SYSZ_REG_A7, "a7" }, + { SYSZ_REG_A8, "a8" }, + { SYSZ_REG_A9, "a9" }, + { SYSZ_REG_A10, "a10" }, + { SYSZ_REG_A11, "a11" }, + { SYSZ_REG_A12, "a12" }, + { SYSZ_REG_A13, "a13" }, + { SYSZ_REG_A14, "a14" }, + { SYSZ_REG_A15, "a15" }, + { SYSZ_REG_C0, "c0" }, + { SYSZ_REG_C1, "c1" }, + { SYSZ_REG_C2, "c2" }, + { SYSZ_REG_C3, "c3" }, + { SYSZ_REG_C4, "c4" }, + { SYSZ_REG_C5, "c5" }, + { SYSZ_REG_C6, "c6" }, + { SYSZ_REG_C7, "c7" }, + { SYSZ_REG_C8, "c8" }, + { SYSZ_REG_C9, "c9" }, + { SYSZ_REG_C10, "c10" }, + { SYSZ_REG_C11, "c11" }, + { SYSZ_REG_C12, "c12" }, + { SYSZ_REG_C13, "c13" }, + { SYSZ_REG_C14, "c14" }, + { SYSZ_REG_C15, "c15" }, + { SYSZ_REG_V0, "v0" }, + { SYSZ_REG_V1, "v1" }, + { SYSZ_REG_V2, "v2" }, + { SYSZ_REG_V3, "v3" }, + { SYSZ_REG_V4, "v4" }, + { SYSZ_REG_V5, "v5" }, + { SYSZ_REG_V6, "v6" }, + { SYSZ_REG_V7, "v7" }, + { SYSZ_REG_V8, "v8" }, + { SYSZ_REG_V9, "v9" }, + { SYSZ_REG_V10, "v10" }, + { SYSZ_REG_V11, "v11" }, + { SYSZ_REG_V12, "v12" }, + { SYSZ_REG_V13, "v13" }, + { SYSZ_REG_V14, "v14" }, + { SYSZ_REG_V15, "v15" }, + { SYSZ_REG_V16, "v16" }, + { SYSZ_REG_V17, "v17" }, + { SYSZ_REG_V18, "v18" }, + { SYSZ_REG_V19, "v19" }, + { SYSZ_REG_V20, "v20" }, + { SYSZ_REG_V21, "v21" }, + { SYSZ_REG_V22, "v22" }, + { SYSZ_REG_V23, "v23" }, + { SYSZ_REG_V24, "v24" }, + { SYSZ_REG_V25, "v25" }, + { SYSZ_REG_V26, "v26" }, + { SYSZ_REG_V27, "v27" }, + { SYSZ_REG_V28, "v28" }, + { SYSZ_REG_V29, "v29" }, + { SYSZ_REG_V30, "v30" }, + { SYSZ_REG_V31, "v31" }, + { SYSZ_REG_F16, "f16" }, + { SYSZ_REG_F17, "f17" }, + { SYSZ_REG_F18, "f18" }, + { SYSZ_REG_F19, "f19" }, + { SYSZ_REG_F20, "f20" }, + { SYSZ_REG_F21, "f21" }, + { SYSZ_REG_F22, "f22" }, + { SYSZ_REG_F23, "f23" }, + { SYSZ_REG_F24, "f24" }, + { SYSZ_REG_F25, "f25" }, + { SYSZ_REG_F26, "f26" }, + { SYSZ_REG_F27, "f27" }, + { SYSZ_REG_F28, "f28" }, + { SYSZ_REG_F29, "f29" }, + { SYSZ_REG_F30, "f30" }, + { SYSZ_REG_F31, "f31" }, + { SYSZ_REG_F0Q, "f0q" }, + { SYSZ_REG_F4Q, "f4q" }, +}; +#endif + +const char *SystemZ_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "SystemZMappingInsn.inc" +}; + +// given internal insn id, return public instruction info +void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + } + } +} + +#ifndef CAPSTONE_DIET +static const name_map insn_name_maps[] = { + { SYSZ_INS_INVALID, NULL }, + +#include "SystemZGenInsnNameMaps.inc" +}; + +// special alias insn +static const name_map alias_insn_names[] = { + { 0, NULL } +}; +#endif + +const char *SystemZ_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= SYSZ_INS_ENDING) + return NULL; + + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { SYSZ_GRP_INVALID, NULL }, + { SYSZ_GRP_JUMP, "jump" }, + + // architecture-specific groups + { SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion" }, + { SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion" }, + { SYSZ_GRP_DISTINCTOPS, "distinctops" }, + { SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2" }, + { SYSZ_GRP_EXECUTIONHINT, "executionhint" }, + { SYSZ_GRP_FPEXTENSION, "fpextension" }, + { SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage" }, + { SYSZ_GRP_HIGHWORD, "highword" }, + { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple" }, + { SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1" }, + { SYSZ_GRP_LOADANDTRAP, "loadandtrap" }, + { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte" }, + { SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond" }, + { SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2" }, + { SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3" }, + { SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4" }, + { SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5" }, + { SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7" }, + { SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8" }, + { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions" }, + { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2" }, + { SYSZ_GRP_POPULATIONCOUNT, "populationcount" }, + { SYSZ_GRP_PROCESSORASSIST, "processorassist" }, + { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple" }, + { SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution" }, + { SYSZ_GRP_VECTOR, "vector" }, + { SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1" }, + { SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal" }, +}; +#endif + +const char *SystemZ_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map internal raw register to 'public' register +sysz_reg SystemZ_map_register(unsigned int r) +{ + static const unsigned int map[] = { 0, + /* SystemZ_CC = 1 */ SYSZ_REG_CC, + /* SystemZ_A0 = 2 */ SYSZ_REG_A0, + /* SystemZ_A1 = 3 */ SYSZ_REG_A1, + /* SystemZ_A2 = 4 */ SYSZ_REG_A2, + /* SystemZ_A3 = 5 */ SYSZ_REG_A3, + /* SystemZ_A4 = 6 */ SYSZ_REG_A4, + /* SystemZ_A5 = 7 */ SYSZ_REG_A5, + /* SystemZ_A6 = 8 */ SYSZ_REG_A6, + /* SystemZ_A7 = 9 */ SYSZ_REG_A7, + /* SystemZ_A8 = 10 */ SYSZ_REG_A8, + /* SystemZ_A9 = 11 */ SYSZ_REG_A9, + /* SystemZ_A10 = 12 */ SYSZ_REG_A10, + /* SystemZ_A11 = 13 */ SYSZ_REG_A11, + /* SystemZ_A12 = 14 */ SYSZ_REG_A12, + /* SystemZ_A13 = 15 */ SYSZ_REG_A13, + /* SystemZ_A14 = 16 */ SYSZ_REG_A14, + /* SystemZ_A15 = 17 */ SYSZ_REG_A15, + /* SystemZ_C0 = 18 */ SYSZ_REG_C0, + /* SystemZ_C1 = 19 */ SYSZ_REG_C1, + /* SystemZ_C2 = 20 */ SYSZ_REG_C2, + /* SystemZ_C3 = 21 */ SYSZ_REG_C3, + /* SystemZ_C4 = 22 */ SYSZ_REG_C4, + /* SystemZ_C5 = 23 */ SYSZ_REG_C5, + /* SystemZ_C6 = 24 */ SYSZ_REG_C6, + /* SystemZ_C7 = 25 */ SYSZ_REG_C7, + /* SystemZ_C8 = 26 */ SYSZ_REG_C8, + /* SystemZ_C9 = 27 */ SYSZ_REG_C9, + /* SystemZ_C10 = 28 */ SYSZ_REG_C10, + /* SystemZ_C11 = 29 */ SYSZ_REG_C11, + /* SystemZ_C12 = 30 */ SYSZ_REG_C12, + /* SystemZ_C13 = 31 */ SYSZ_REG_C13, + /* SystemZ_C14 = 32 */ SYSZ_REG_C14, + /* SystemZ_C15 = 33 */ SYSZ_REG_C15, + /* SystemZ_V0 = 34 */ SYSZ_REG_V0, + /* SystemZ_V1 = 35 */ SYSZ_REG_V1, + /* SystemZ_V2 = 36 */ SYSZ_REG_V2, + /* SystemZ_V3 = 37 */ SYSZ_REG_V3, + /* SystemZ_V4 = 38 */ SYSZ_REG_V4, + /* SystemZ_V5 = 39 */ SYSZ_REG_V5, + /* SystemZ_V6 = 40 */ SYSZ_REG_V6, + /* SystemZ_V7 = 41 */ SYSZ_REG_V7, + /* SystemZ_V8 = 42 */ SYSZ_REG_V8, + /* SystemZ_V9 = 43 */ SYSZ_REG_V9, + /* SystemZ_V10 = 44 */ SYSZ_REG_V10, + /* SystemZ_V11 = 45 */ SYSZ_REG_V11, + /* SystemZ_V12 = 46 */ SYSZ_REG_V12, + /* SystemZ_V13 = 47 */ SYSZ_REG_V13, + /* SystemZ_V14 = 48 */ SYSZ_REG_V14, + /* SystemZ_V15 = 49 */ SYSZ_REG_V15, + /* SystemZ_V16 = 50 */ SYSZ_REG_V16, + /* SystemZ_V17 = 51 */ SYSZ_REG_V17, + /* SystemZ_V18 = 52 */ SYSZ_REG_V18, + /* SystemZ_V19 = 53 */ SYSZ_REG_V19, + /* SystemZ_V20 = 54 */ SYSZ_REG_V20, + /* SystemZ_V21 = 55 */ SYSZ_REG_V21, + /* SystemZ_V22 = 56 */ SYSZ_REG_V22, + /* SystemZ_V23 = 57 */ SYSZ_REG_V23, + /* SystemZ_V24 = 58 */ SYSZ_REG_V24, + /* SystemZ_V25 = 59 */ SYSZ_REG_V25, + /* SystemZ_V26 = 60 */ SYSZ_REG_V26, + /* SystemZ_V27 = 61 */ SYSZ_REG_V27, + /* SystemZ_V28 = 62 */ SYSZ_REG_V28, + /* SystemZ_V29 = 63 */ SYSZ_REG_V29, + /* SystemZ_V30 = 64 */ SYSZ_REG_V30, + /* SystemZ_V31 = 65 */ SYSZ_REG_V31, + /* SystemZ_F0D = 66 */ SYSZ_REG_F0, + /* SystemZ_F1D = 67 */ SYSZ_REG_F1, + /* SystemZ_F2D = 68 */ SYSZ_REG_F2, + /* SystemZ_F3D = 69 */ SYSZ_REG_F3, + /* SystemZ_F4D = 70 */ SYSZ_REG_F4, + /* SystemZ_F5D = 71 */ SYSZ_REG_F5, + /* SystemZ_F6D = 72 */ SYSZ_REG_F6, + /* SystemZ_F7D = 73 */ SYSZ_REG_F7, + /* SystemZ_F8D = 74 */ SYSZ_REG_F8, + /* SystemZ_F9D = 75 */ SYSZ_REG_F9, + /* SystemZ_F10D = 76 */ SYSZ_REG_F10, + /* SystemZ_F11D = 77 */ SYSZ_REG_F11, + /* SystemZ_F12D = 78 */ SYSZ_REG_F12, + /* SystemZ_F13D = 79 */ SYSZ_REG_F13, + /* SystemZ_F14D = 80 */ SYSZ_REG_F14, + /* SystemZ_F15D = 81 */ SYSZ_REG_F15, + /* SystemZ_F16D = 82 */ SYSZ_REG_F16, + /* SystemZ_F17D = 83 */ SYSZ_REG_F17, + /* SystemZ_F18D = 84 */ SYSZ_REG_F18, + /* SystemZ_F19D = 85 */ SYSZ_REG_F19, + /* SystemZ_F20D = 86 */ SYSZ_REG_F20, + /* SystemZ_F21D = 87 */ SYSZ_REG_F21, + /* SystemZ_F22D = 88 */ SYSZ_REG_F22, + /* SystemZ_F23D = 89 */ SYSZ_REG_F23, + /* SystemZ_F24D = 90 */ SYSZ_REG_F24, + /* SystemZ_F25D = 91 */ SYSZ_REG_F25, + /* SystemZ_F26D = 92 */ SYSZ_REG_F26, + /* SystemZ_F27D = 93 */ SYSZ_REG_F27, + /* SystemZ_F28D = 94 */ SYSZ_REG_F28, + /* SystemZ_F29D = 95 */ SYSZ_REG_F29, + /* SystemZ_F30D = 96 */ SYSZ_REG_F30, + /* SystemZ_F31D = 97 */ SYSZ_REG_F31, + /* SystemZ_F0Q = 98 */ SYSZ_REG_F0, + /* SystemZ_F1Q = 99 */ SYSZ_REG_F1, + /* SystemZ_F4Q = 100 */ SYSZ_REG_F4, + /* SystemZ_F5Q = 101 */ SYSZ_REG_F5, + /* SystemZ_F8Q = 102 */ SYSZ_REG_F8, + /* SystemZ_F9Q = 103 */ SYSZ_REG_F9, + /* SystemZ_F12Q = 104 */ SYSZ_REG_F12, + /* SystemZ_F13Q = 105 */ SYSZ_REG_F13, + /* SystemZ_F0S = 106 */ SYSZ_REG_F0, + /* SystemZ_F1S = 107 */ SYSZ_REG_F1, + /* SystemZ_F2S = 108 */ SYSZ_REG_F2, + /* SystemZ_F3S = 109 */ SYSZ_REG_F3, + /* SystemZ_F4S = 110 */ SYSZ_REG_F4, + /* SystemZ_F5S = 111 */ SYSZ_REG_F5, + /* SystemZ_F6S = 112 */ SYSZ_REG_F6, + /* SystemZ_F7S = 113 */ SYSZ_REG_F7, + /* SystemZ_F8S = 114 */ SYSZ_REG_F8, + /* SystemZ_F9S = 115 */ SYSZ_REG_F9, + /* SystemZ_F10S = 116 */ SYSZ_REG_F10, + /* SystemZ_F11S = 117 */ SYSZ_REG_F11, + /* SystemZ_F12S = 118 */ SYSZ_REG_F12, + /* SystemZ_F13S = 119 */ SYSZ_REG_F13, + /* SystemZ_F14S = 120 */ SYSZ_REG_F14, + /* SystemZ_F15S = 121 */ SYSZ_REG_F15, + /* SystemZ_F16S = 122 */ SYSZ_REG_F16, + /* SystemZ_F17S = 123 */ SYSZ_REG_F17, + /* SystemZ_F18S = 124 */ SYSZ_REG_F18, + /* SystemZ_F19S = 125 */ SYSZ_REG_F19, + /* SystemZ_F20S = 126 */ SYSZ_REG_F20, + /* SystemZ_F21S = 127 */ SYSZ_REG_F21, + /* SystemZ_F22S = 128 */ SYSZ_REG_F22, + /* SystemZ_F23S = 129 */ SYSZ_REG_F23, + /* SystemZ_F24S = 130 */ SYSZ_REG_F24, + /* SystemZ_F25S = 131 */ SYSZ_REG_F25, + /* SystemZ_F26S = 132 */ SYSZ_REG_F26, + /* SystemZ_F27S = 133 */ SYSZ_REG_F27, + /* SystemZ_F28S = 134 */ SYSZ_REG_F28, + /* SystemZ_F29S = 135 */ SYSZ_REG_F29, + /* SystemZ_F30S = 136 */ SYSZ_REG_F30, + /* SystemZ_F31S = 137 */ SYSZ_REG_F31, + /* SystemZ_R0D = 138 */ SYSZ_REG_0, + /* SystemZ_R1D = 139 */ SYSZ_REG_1, + /* SystemZ_R2D = 140 */ SYSZ_REG_2, + /* SystemZ_R3D = 141 */ SYSZ_REG_3, + /* SystemZ_R4D = 142 */ SYSZ_REG_4, + /* SystemZ_R5D = 143 */ SYSZ_REG_5, + /* SystemZ_R6D = 144 */ SYSZ_REG_6, + /* SystemZ_R7D = 145 */ SYSZ_REG_7, + /* SystemZ_R8D = 146 */ SYSZ_REG_8, + /* SystemZ_R9D = 147 */ SYSZ_REG_9, + /* SystemZ_R10D = 148 */ SYSZ_REG_10, + /* SystemZ_R11D = 149 */ SYSZ_REG_11, + /* SystemZ_R12D = 150 */ SYSZ_REG_12, + /* SystemZ_R13D = 151 */ SYSZ_REG_13, + /* SystemZ_R14D = 152 */ SYSZ_REG_14, + /* SystemZ_R15D = 153 */ SYSZ_REG_15, + /* SystemZ_R0H = 154 */ SYSZ_REG_0, + /* SystemZ_R1H = 155 */ SYSZ_REG_1, + /* SystemZ_R2H = 156 */ SYSZ_REG_2, + /* SystemZ_R3H = 157 */ SYSZ_REG_3, + /* SystemZ_R4H = 158 */ SYSZ_REG_4, + /* SystemZ_R5H = 159 */ SYSZ_REG_5, + /* SystemZ_R6H = 160 */ SYSZ_REG_6, + /* SystemZ_R7H = 161 */ SYSZ_REG_7, + /* SystemZ_R8H = 162 */ SYSZ_REG_8, + /* SystemZ_R9H = 163 */ SYSZ_REG_9, + /* SystemZ_R10H = 164 */ SYSZ_REG_10, + /* SystemZ_R11H = 165 */ SYSZ_REG_11, + /* SystemZ_R12H = 166 */ SYSZ_REG_12, + /* SystemZ_R13H = 167 */ SYSZ_REG_13, + /* SystemZ_R14H = 168 */ SYSZ_REG_14, + /* SystemZ_R15H = 169 */ SYSZ_REG_15, + /* SystemZ_R0L = 170 */ SYSZ_REG_0, + /* SystemZ_R1L = 171 */ SYSZ_REG_1, + /* SystemZ_R2L = 172 */ SYSZ_REG_2, + /* SystemZ_R3L = 173 */ SYSZ_REG_3, + /* SystemZ_R4L = 174 */ SYSZ_REG_4, + /* SystemZ_R5L = 175 */ SYSZ_REG_5, + /* SystemZ_R6L = 176 */ SYSZ_REG_6, + /* SystemZ_R7L = 177 */ SYSZ_REG_7, + /* SystemZ_R8L = 178 */ SYSZ_REG_8, + /* SystemZ_R9L = 179 */ SYSZ_REG_9, + /* SystemZ_R10L = 180 */ SYSZ_REG_10, + /* SystemZ_R11L = 181 */ SYSZ_REG_11, + /* SystemZ_R12L = 182 */ SYSZ_REG_12, + /* SystemZ_R13L = 183 */ SYSZ_REG_13, + /* SystemZ_R14L = 184 */ SYSZ_REG_14, + /* SystemZ_R15L = 185 */ SYSZ_REG_15, + /* SystemZ_R0Q = 186 */ SYSZ_REG_0, + /* SystemZ_R2Q = 187 */ SYSZ_REG_2, + /* SystemZ_R4Q = 188 */ SYSZ_REG_4, + /* SystemZ_R6Q = 189 */ SYSZ_REG_6, + /* SystemZ_R8Q = 190 */ SYSZ_REG_8, + /* SystemZ_R10Q = 191 */ SYSZ_REG_10, + /* SystemZ_R12Q = 192 */ SYSZ_REG_12, + /* SystemZ_R14Q = 193 */ SYSZ_REG_14, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.h b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.h new file mode 100644 index 0000000..9a6ceb3 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMapping.h @@ -0,0 +1,23 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_SYSZ_MAP_H +#define CS_SYSZ_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *SystemZ_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *SystemZ_insn_name(csh handle, unsigned int id); + +const char *SystemZ_group_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +sysz_reg SystemZ_map_register(unsigned int r); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZMappingInsn.inc b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMappingInsn.inc new file mode 100644 index 0000000..949b65b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZMappingInsn.inc @@ -0,0 +1,14175 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + SystemZ_A, SYSZ_INS_A, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AD, SYSZ_INS_AD, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ADB, SYSZ_INS_ADB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ADBR, SYSZ_INS_ADBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ADR, SYSZ_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ADTR, SYSZ_INS_ADTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ADTRA, SYSZ_INS_ADTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AE, SYSZ_INS_AE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AEB, SYSZ_INS_AEB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AEBR, SYSZ_INS_AEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AER, SYSZ_INS_AER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AFI, SYSZ_INS_AFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AG, SYSZ_INS_AG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGF, SYSZ_INS_AGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGFI, SYSZ_INS_AGFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGFR, SYSZ_INS_AGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGH, SYSZ_INS_AGH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGHI, SYSZ_INS_AGHI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGHIK, SYSZ_INS_AGHIK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGR, SYSZ_INS_AGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGRK, SYSZ_INS_AGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AGSI, SYSZ_INS_AGSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AH, SYSZ_INS_AH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AHHHR, SYSZ_INS_AHHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AHHLR, SYSZ_INS_AHHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AHI, SYSZ_INS_AHI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AHIK, SYSZ_INS_AHIK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AHY, SYSZ_INS_AHY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AIH, SYSZ_INS_AIH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AL, SYSZ_INS_AL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALC, SYSZ_INS_ALC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALCG, SYSZ_INS_ALCG, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALCGR, SYSZ_INS_ALCGR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALCR, SYSZ_INS_ALCR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALFI, SYSZ_INS_ALFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALG, SYSZ_INS_ALG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGF, SYSZ_INS_ALGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGFI, SYSZ_INS_ALGFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGFR, SYSZ_INS_ALGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGHSIK, SYSZ_INS_ALGHSIK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGR, SYSZ_INS_ALGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGRK, SYSZ_INS_ALGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALGSI, SYSZ_INS_ALGSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALHHHR, SYSZ_INS_ALHHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALHHLR, SYSZ_INS_ALHHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALHSIK, SYSZ_INS_ALHSIK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALR, SYSZ_INS_ALR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALRK, SYSZ_INS_ALRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALSI, SYSZ_INS_ALSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALSIH, SYSZ_INS_ALSIH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALSIHN, SYSZ_INS_ALSIHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ALY, SYSZ_INS_ALY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AP, SYSZ_INS_AP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AR, SYSZ_INS_AR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ARK, SYSZ_INS_ARK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ASI, SYSZ_INS_ASI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AU, SYSZ_INS_AU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AUR, SYSZ_INS_AUR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AW, SYSZ_INS_AW, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AWR, SYSZ_INS_AWR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AXBR, SYSZ_INS_AXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AXR, SYSZ_INS_AXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AXTR, SYSZ_INS_AXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_AXTRA, SYSZ_INS_AXTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_AY, SYSZ_INS_AY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_B, SYSZ_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAKR, SYSZ_INS_BAKR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BAL, SYSZ_INS_BAL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BALR, SYSZ_INS_BALR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BAS, SYSZ_INS_BAS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BASR, SYSZ_INS_BASR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BASSM, SYSZ_INS_BASSM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BAsmE, SYSZ_INS_BE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmH, SYSZ_INS_BH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmHE, SYSZ_INS_BHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmL, SYSZ_INS_BL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmLE, SYSZ_INS_BLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmLH, SYSZ_INS_BLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmM, SYSZ_INS_BM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNE, SYSZ_INS_BNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNH, SYSZ_INS_BNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNHE, SYSZ_INS_BNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNL, SYSZ_INS_BNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNLE, SYSZ_INS_BNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNLH, SYSZ_INS_BNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNM, SYSZ_INS_BNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNO, SYSZ_INS_BNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNP, SYSZ_INS_BNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmNZ, SYSZ_INS_BNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmO, SYSZ_INS_BO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmP, SYSZ_INS_BP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BAsmZ, SYSZ_INS_BZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BCAsm, SYSZ_INS_BC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BCRAsm, SYSZ_INS_BCR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BCT, SYSZ_INS_BCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BCTG, SYSZ_INS_BCTG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BCTGR, SYSZ_INS_BCTGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BCTR, SYSZ_INS_BCTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BI, SYSZ_INS_BI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmE, SYSZ_INS_BIE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmH, SYSZ_INS_BIH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmHE, SYSZ_INS_BIHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmL, SYSZ_INS_BIL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmLE, SYSZ_INS_BILE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmLH, SYSZ_INS_BILH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmM, SYSZ_INS_BIM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNE, SYSZ_INS_BINE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNH, SYSZ_INS_BINH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNHE, SYSZ_INS_BINHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNL, SYSZ_INS_BINL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNLE, SYSZ_INS_BINLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNLH, SYSZ_INS_BINLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNM, SYSZ_INS_BINM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNO, SYSZ_INS_BINO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNP, SYSZ_INS_BINP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmNZ, SYSZ_INS_BINZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmO, SYSZ_INS_BIO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmP, SYSZ_INS_BIP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BIAsmZ, SYSZ_INS_BIZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BICAsm, SYSZ_INS_BIC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 +#endif +}, +{ + SystemZ_BPP, SYSZ_INS_BPP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 +#endif +}, +{ + SystemZ_BPRP, SYSZ_INS_BPRP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 +#endif +}, +{ + SystemZ_BR, SYSZ_INS_BR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAS, SYSZ_INS_BRAS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BRASL, SYSZ_INS_BRASL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BRAsmE, SYSZ_INS_BER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmH, SYSZ_INS_BHR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmHE, SYSZ_INS_BHER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmL, SYSZ_INS_BLR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmLE, SYSZ_INS_BLER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmLH, SYSZ_INS_BLHR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmM, SYSZ_INS_BMR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNE, SYSZ_INS_BNER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNH, SYSZ_INS_BNHR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNHE, SYSZ_INS_BNHER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNL, SYSZ_INS_BNLR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNLE, SYSZ_INS_BNLER, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNLH, SYSZ_INS_BNLHR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNM, SYSZ_INS_BNMR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNO, SYSZ_INS_BNOR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNP, SYSZ_INS_BNPR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmNZ, SYSZ_INS_BNZR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmO, SYSZ_INS_BOR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmP, SYSZ_INS_BPR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRAsmZ, SYSZ_INS_BZR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_BRCAsm, SYSZ_INS_BRC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRCLAsm, SYSZ_INS_BRCL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRCT, SYSZ_INS_BRCT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRCTG, SYSZ_INS_BRCTG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRCTH, SYSZ_INS_BRCTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRXH, SYSZ_INS_BRXH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRXHG, SYSZ_INS_BRXHG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRXLE, SYSZ_INS_BRXLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BRXLG, SYSZ_INS_BRXLG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BSA, SYSZ_INS_BSA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BSG, SYSZ_INS_BSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_BSM, SYSZ_INS_BSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BXH, SYSZ_INS_BXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BXHG, SYSZ_INS_BXHG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BXLE, SYSZ_INS_BXLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_BXLEG, SYSZ_INS_BXLEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_C, SYSZ_INS_C, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CD, SYSZ_INS_CD, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDB, SYSZ_INS_CDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDBR, SYSZ_INS_CDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDFBR, SYSZ_INS_CDFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDFBRA, SYSZ_INS_CDFBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDFR, SYSZ_INS_CDFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDFTR, SYSZ_INS_CDFTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDGBR, SYSZ_INS_CDGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDGBRA, SYSZ_INS_CDGBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDGR, SYSZ_INS_CDGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDGTR, SYSZ_INS_CDGTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDGTRA, SYSZ_INS_CDGTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDLFBR, SYSZ_INS_CDLFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDLFTR, SYSZ_INS_CDLFTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDLGBR, SYSZ_INS_CDLGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDLGTR, SYSZ_INS_CDLGTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDPT, SYSZ_INS_CDPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDR, SYSZ_INS_CDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDS, SYSZ_INS_CDS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDSG, SYSZ_INS_CDSG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDSTR, SYSZ_INS_CDSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDSY, SYSZ_INS_CDSY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDTR, SYSZ_INS_CDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDUTR, SYSZ_INS_CDUTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CDZT, SYSZ_INS_CDZT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CE, SYSZ_INS_CE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEB, SYSZ_INS_CEB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEBR, SYSZ_INS_CEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEDTR, SYSZ_INS_CEDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEFBR, SYSZ_INS_CEFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEFBRA, SYSZ_INS_CEFBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEFR, SYSZ_INS_CEFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEGBR, SYSZ_INS_CEGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEGBRA, SYSZ_INS_CEGBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEGR, SYSZ_INS_CEGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CELFBR, SYSZ_INS_CELFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CELGBR, SYSZ_INS_CELGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CER, SYSZ_INS_CER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CEXTR, SYSZ_INS_CEXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFC, SYSZ_INS_CFC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFDBR, SYSZ_INS_CFDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFDBRA, SYSZ_INS_CFDBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFDR, SYSZ_INS_CFDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFDTR, SYSZ_INS_CFDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFEBR, SYSZ_INS_CFEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFEBRA, SYSZ_INS_CFEBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFER, SYSZ_INS_CFER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFI, SYSZ_INS_CFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFXBR, SYSZ_INS_CFXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFXBRA, SYSZ_INS_CFXBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFXR, SYSZ_INS_CFXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CFXTR, SYSZ_INS_CFXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CG, SYSZ_INS_CG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGDBR, SYSZ_INS_CGDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGDBRA, SYSZ_INS_CGDBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGDR, SYSZ_INS_CGDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGDTR, SYSZ_INS_CGDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGDTRA, SYSZ_INS_CGDTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGEBR, SYSZ_INS_CGEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGEBRA, SYSZ_INS_CGEBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGER, SYSZ_INS_CGER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGF, SYSZ_INS_CGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGFI, SYSZ_INS_CGFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGFR, SYSZ_INS_CGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGFRL, SYSZ_INS_CGFRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGH, SYSZ_INS_CGH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGHI, SYSZ_INS_CGHI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGHRL, SYSZ_INS_CGHRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGHSI, SYSZ_INS_CGHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGIBAsm, SYSZ_INS_CGIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmE, SYSZ_INS_CGIBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmH, SYSZ_INS_CGIBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmHE, SYSZ_INS_CGIBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmL, SYSZ_INS_CGIBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmLE, SYSZ_INS_CGIBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmLH, SYSZ_INS_CGIBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNE, SYSZ_INS_CGIBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNH, SYSZ_INS_CGIBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNHE, SYSZ_INS_CGIBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNL, SYSZ_INS_CGIBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNLE, SYSZ_INS_CGIBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIBAsmNLH, SYSZ_INS_CGIBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGIJAsm, SYSZ_INS_CGIJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmE, SYSZ_INS_CGIJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmH, SYSZ_INS_CGIJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmHE, SYSZ_INS_CGIJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmL, SYSZ_INS_CGIJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmLE, SYSZ_INS_CGIJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmLH, SYSZ_INS_CGIJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNE, SYSZ_INS_CGIJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNH, SYSZ_INS_CGIJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNHE, SYSZ_INS_CGIJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNL, SYSZ_INS_CGIJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNLE, SYSZ_INS_CGIJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGIJAsmNLH, SYSZ_INS_CGIJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGITAsm, SYSZ_INS_CGIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmE, SYSZ_INS_CGITE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmH, SYSZ_INS_CGITH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmHE, SYSZ_INS_CGITHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmL, SYSZ_INS_CGITL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmLE, SYSZ_INS_CGITLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmLH, SYSZ_INS_CGITLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNE, SYSZ_INS_CGITNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNH, SYSZ_INS_CGITNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNHE, SYSZ_INS_CGITNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNL, SYSZ_INS_CGITNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNLE, SYSZ_INS_CGITNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGITAsmNLH, SYSZ_INS_CGITNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGR, SYSZ_INS_CGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRBAsm, SYSZ_INS_CGRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmE, SYSZ_INS_CGRBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmH, SYSZ_INS_CGRBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmHE, SYSZ_INS_CGRBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmL, SYSZ_INS_CGRBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmLE, SYSZ_INS_CGRBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmLH, SYSZ_INS_CGRBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNE, SYSZ_INS_CGRBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNH, SYSZ_INS_CGRBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNHE, SYSZ_INS_CGRBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNL, SYSZ_INS_CGRBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNLE, SYSZ_INS_CGRBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRBAsmNLH, SYSZ_INS_CGRBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CGRJAsm, SYSZ_INS_CGRJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmE, SYSZ_INS_CGRJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmH, SYSZ_INS_CGRJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmHE, SYSZ_INS_CGRJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmL, SYSZ_INS_CGRJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmLE, SYSZ_INS_CGRJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmLH, SYSZ_INS_CGRJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNE, SYSZ_INS_CGRJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNH, SYSZ_INS_CGRJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNHE, SYSZ_INS_CGRJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNL, SYSZ_INS_CGRJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNLE, SYSZ_INS_CGRJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRJAsmNLH, SYSZ_INS_CGRJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CGRL, SYSZ_INS_CGRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsm, SYSZ_INS_CGRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmE, SYSZ_INS_CGRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmH, SYSZ_INS_CGRTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmHE, SYSZ_INS_CGRTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmL, SYSZ_INS_CGRTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmLE, SYSZ_INS_CGRTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmLH, SYSZ_INS_CGRTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNE, SYSZ_INS_CGRTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNH, SYSZ_INS_CGRTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNHE, SYSZ_INS_CGRTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNL, SYSZ_INS_CGRTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNLE, SYSZ_INS_CGRTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGRTAsmNLH, SYSZ_INS_CGRTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGXBR, SYSZ_INS_CGXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGXBRA, SYSZ_INS_CGXBRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGXR, SYSZ_INS_CGXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGXTR, SYSZ_INS_CGXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CGXTRA, SYSZ_INS_CGXTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CH, SYSZ_INS_CH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHF, SYSZ_INS_CHF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHHR, SYSZ_INS_CHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHHSI, SYSZ_INS_CHHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHI, SYSZ_INS_CHI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHLR, SYSZ_INS_CHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHRL, SYSZ_INS_CHRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHSI, SYSZ_INS_CHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CHY, SYSZ_INS_CHY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CIBAsm, SYSZ_INS_CIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmE, SYSZ_INS_CIBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmH, SYSZ_INS_CIBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmHE, SYSZ_INS_CIBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmL, SYSZ_INS_CIBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmLE, SYSZ_INS_CIBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmLH, SYSZ_INS_CIBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNE, SYSZ_INS_CIBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNH, SYSZ_INS_CIBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNHE, SYSZ_INS_CIBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNL, SYSZ_INS_CIBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNLE, SYSZ_INS_CIBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIBAsmNLH, SYSZ_INS_CIBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CIH, SYSZ_INS_CIH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CIJAsm, SYSZ_INS_CIJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmE, SYSZ_INS_CIJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmH, SYSZ_INS_CIJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmHE, SYSZ_INS_CIJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmL, SYSZ_INS_CIJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmLE, SYSZ_INS_CIJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmLH, SYSZ_INS_CIJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNE, SYSZ_INS_CIJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNH, SYSZ_INS_CIJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNHE, SYSZ_INS_CIJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNL, SYSZ_INS_CIJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNLE, SYSZ_INS_CIJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CIJAsmNLH, SYSZ_INS_CIJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CITAsm, SYSZ_INS_CIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmE, SYSZ_INS_CITE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmH, SYSZ_INS_CITH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmHE, SYSZ_INS_CITHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmL, SYSZ_INS_CITL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmLE, SYSZ_INS_CITLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmLH, SYSZ_INS_CITLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNE, SYSZ_INS_CITNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNH, SYSZ_INS_CITNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNHE, SYSZ_INS_CITNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNL, SYSZ_INS_CITNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNLE, SYSZ_INS_CITNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CITAsmNLH, SYSZ_INS_CITNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CKSM, SYSZ_INS_CKSM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CL, SYSZ_INS_CL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLC, SYSZ_INS_CLC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLCL, SYSZ_INS_CLCL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLCLE, SYSZ_INS_CLCLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLCLU, SYSZ_INS_CLCLU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFDBR, SYSZ_INS_CLFDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFDTR, SYSZ_INS_CLFDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFEBR, SYSZ_INS_CLFEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFHSI, SYSZ_INS_CLFHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFI, SYSZ_INS_CLFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsm, SYSZ_INS_CLFIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmE, SYSZ_INS_CLFITE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmH, SYSZ_INS_CLFITH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmHE, SYSZ_INS_CLFITHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmL, SYSZ_INS_CLFITL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmLE, SYSZ_INS_CLFITLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmLH, SYSZ_INS_CLFITLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNE, SYSZ_INS_CLFITNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNH, SYSZ_INS_CLFITNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNHE, SYSZ_INS_CLFITNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNL, SYSZ_INS_CLFITNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNLE, SYSZ_INS_CLFITNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFITAsmNLH, SYSZ_INS_CLFITNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFXBR, SYSZ_INS_CLFXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLFXTR, SYSZ_INS_CLFXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLG, SYSZ_INS_CLG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGDBR, SYSZ_INS_CLGDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGDTR, SYSZ_INS_CLGDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGEBR, SYSZ_INS_CLGEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGF, SYSZ_INS_CLGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGFI, SYSZ_INS_CLGFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGFR, SYSZ_INS_CLGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGFRL, SYSZ_INS_CLGFRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGHRL, SYSZ_INS_CLGHRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGHSI, SYSZ_INS_CLGHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGIBAsm, SYSZ_INS_CLGIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmE, SYSZ_INS_CLGIBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmH, SYSZ_INS_CLGIBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmHE, SYSZ_INS_CLGIBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmL, SYSZ_INS_CLGIBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmLE, SYSZ_INS_CLGIBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmLH, SYSZ_INS_CLGIBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNE, SYSZ_INS_CLGIBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNH, SYSZ_INS_CLGIBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNHE, SYSZ_INS_CLGIBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNL, SYSZ_INS_CLGIBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNLE, SYSZ_INS_CLGIBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIBAsmNLH, SYSZ_INS_CLGIBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGIJAsm, SYSZ_INS_CLGIJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmE, SYSZ_INS_CLGIJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmH, SYSZ_INS_CLGIJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmHE, SYSZ_INS_CLGIJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmL, SYSZ_INS_CLGIJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmLE, SYSZ_INS_CLGIJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmLH, SYSZ_INS_CLGIJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNE, SYSZ_INS_CLGIJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNH, SYSZ_INS_CLGIJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNHE, SYSZ_INS_CLGIJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNL, SYSZ_INS_CLGIJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNLE, SYSZ_INS_CLGIJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGIJAsmNLH, SYSZ_INS_CLGIJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGITAsm, SYSZ_INS_CLGIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmE, SYSZ_INS_CLGITE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmH, SYSZ_INS_CLGITH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmHE, SYSZ_INS_CLGITHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmL, SYSZ_INS_CLGITL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmLE, SYSZ_INS_CLGITLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmLH, SYSZ_INS_CLGITLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNE, SYSZ_INS_CLGITNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNH, SYSZ_INS_CLGITNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNHE, SYSZ_INS_CLGITNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNL, SYSZ_INS_CLGITNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNLE, SYSZ_INS_CLGITNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGITAsmNLH, SYSZ_INS_CLGITNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGR, SYSZ_INS_CLGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRBAsm, SYSZ_INS_CLGRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmE, SYSZ_INS_CLGRBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmH, SYSZ_INS_CLGRBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmHE, SYSZ_INS_CLGRBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmL, SYSZ_INS_CLGRBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmLE, SYSZ_INS_CLGRBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmLH, SYSZ_INS_CLGRBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNE, SYSZ_INS_CLGRBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNH, SYSZ_INS_CLGRBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNHE, SYSZ_INS_CLGRBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNL, SYSZ_INS_CLGRBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNLE, SYSZ_INS_CLGRBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRBAsmNLH, SYSZ_INS_CLGRBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLGRJAsm, SYSZ_INS_CLGRJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmE, SYSZ_INS_CLGRJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmH, SYSZ_INS_CLGRJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmHE, SYSZ_INS_CLGRJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmL, SYSZ_INS_CLGRJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmLE, SYSZ_INS_CLGRJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmLH, SYSZ_INS_CLGRJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNE, SYSZ_INS_CLGRJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNH, SYSZ_INS_CLGRJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNHE, SYSZ_INS_CLGRJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNL, SYSZ_INS_CLGRJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNLE, SYSZ_INS_CLGRJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRJAsmNLH, SYSZ_INS_CLGRJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLGRL, SYSZ_INS_CLGRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsm, SYSZ_INS_CLGRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmE, SYSZ_INS_CLGRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmH, SYSZ_INS_CLGRTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmHE, SYSZ_INS_CLGRTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmL, SYSZ_INS_CLGRTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmLE, SYSZ_INS_CLGRTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmLH, SYSZ_INS_CLGRTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNE, SYSZ_INS_CLGRTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNH, SYSZ_INS_CLGRTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNHE, SYSZ_INS_CLGRTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNL, SYSZ_INS_CLGRTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNLE, SYSZ_INS_CLGRTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGRTAsmNLH, SYSZ_INS_CLGRTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsm, SYSZ_INS_CLGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmE, SYSZ_INS_CLGTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmH, SYSZ_INS_CLGTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmHE, SYSZ_INS_CLGTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmL, SYSZ_INS_CLGTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmLE, SYSZ_INS_CLGTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmLH, SYSZ_INS_CLGTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNE, SYSZ_INS_CLGTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNH, SYSZ_INS_CLGTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNHE, SYSZ_INS_CLGTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNL, SYSZ_INS_CLGTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNLE, SYSZ_INS_CLGTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGTAsmNLH, SYSZ_INS_CLGTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGXBR, SYSZ_INS_CLGXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLGXTR, SYSZ_INS_CLGXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLHF, SYSZ_INS_CLHF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLHHR, SYSZ_INS_CLHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLHHSI, SYSZ_INS_CLHHSI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLHLR, SYSZ_INS_CLHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLHRL, SYSZ_INS_CLHRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLI, SYSZ_INS_CLI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLIBAsm, SYSZ_INS_CLIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmE, SYSZ_INS_CLIBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmH, SYSZ_INS_CLIBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmHE, SYSZ_INS_CLIBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmL, SYSZ_INS_CLIBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmLE, SYSZ_INS_CLIBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmLH, SYSZ_INS_CLIBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNE, SYSZ_INS_CLIBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNH, SYSZ_INS_CLIBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNHE, SYSZ_INS_CLIBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNL, SYSZ_INS_CLIBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNLE, SYSZ_INS_CLIBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIBAsmNLH, SYSZ_INS_CLIBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLIH, SYSZ_INS_CLIH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLIJAsm, SYSZ_INS_CLIJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmE, SYSZ_INS_CLIJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmH, SYSZ_INS_CLIJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmHE, SYSZ_INS_CLIJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmL, SYSZ_INS_CLIJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmLE, SYSZ_INS_CLIJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmLH, SYSZ_INS_CLIJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNE, SYSZ_INS_CLIJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNH, SYSZ_INS_CLIJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNHE, SYSZ_INS_CLIJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNL, SYSZ_INS_CLIJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNLE, SYSZ_INS_CLIJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIJAsmNLH, SYSZ_INS_CLIJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLIY, SYSZ_INS_CLIY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLM, SYSZ_INS_CLM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLMH, SYSZ_INS_CLMH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLMY, SYSZ_INS_CLMY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLR, SYSZ_INS_CLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRBAsm, SYSZ_INS_CLRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmE, SYSZ_INS_CLRBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmH, SYSZ_INS_CLRBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmHE, SYSZ_INS_CLRBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmL, SYSZ_INS_CLRBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmLE, SYSZ_INS_CLRBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmLH, SYSZ_INS_CLRBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNE, SYSZ_INS_CLRBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNH, SYSZ_INS_CLRBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNHE, SYSZ_INS_CLRBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNL, SYSZ_INS_CLRBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNLE, SYSZ_INS_CLRBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRBAsmNLH, SYSZ_INS_CLRBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CLRJAsm, SYSZ_INS_CLRJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmE, SYSZ_INS_CLRJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmH, SYSZ_INS_CLRJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmHE, SYSZ_INS_CLRJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmL, SYSZ_INS_CLRJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmLE, SYSZ_INS_CLRJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmLH, SYSZ_INS_CLRJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNE, SYSZ_INS_CLRJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNH, SYSZ_INS_CLRJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNHE, SYSZ_INS_CLRJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNL, SYSZ_INS_CLRJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNLE, SYSZ_INS_CLRJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRJAsmNLH, SYSZ_INS_CLRJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CLRL, SYSZ_INS_CLRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsm, SYSZ_INS_CLRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmE, SYSZ_INS_CLRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmH, SYSZ_INS_CLRTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmHE, SYSZ_INS_CLRTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmL, SYSZ_INS_CLRTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmLE, SYSZ_INS_CLRTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmLH, SYSZ_INS_CLRTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNE, SYSZ_INS_CLRTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNH, SYSZ_INS_CLRTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNHE, SYSZ_INS_CLRTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNL, SYSZ_INS_CLRTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNLE, SYSZ_INS_CLRTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLRTAsmNLH, SYSZ_INS_CLRTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLST, SYSZ_INS_CLST, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsm, SYSZ_INS_CLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmE, SYSZ_INS_CLTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmH, SYSZ_INS_CLTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmHE, SYSZ_INS_CLTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmL, SYSZ_INS_CLTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmLE, SYSZ_INS_CLTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmLH, SYSZ_INS_CLTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNE, SYSZ_INS_CLTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNH, SYSZ_INS_CLTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNHE, SYSZ_INS_CLTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNL, SYSZ_INS_CLTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNLE, SYSZ_INS_CLTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLTAsmNLH, SYSZ_INS_CLTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CLY, SYSZ_INS_CLY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CMPSC, SYSZ_INS_CMPSC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CP, SYSZ_INS_CP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CPDT, SYSZ_INS_CPDT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CPSDRdd, SYSZ_INS_CPSDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CPXT, SYSZ_INS_CPXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CPYA, SYSZ_INS_CPYA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CR, SYSZ_INS_CR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRBAsm, SYSZ_INS_CRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmE, SYSZ_INS_CRBE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmH, SYSZ_INS_CRBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmHE, SYSZ_INS_CRBHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmL, SYSZ_INS_CRBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmLE, SYSZ_INS_CRBLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmLH, SYSZ_INS_CRBLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNE, SYSZ_INS_CRBNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNH, SYSZ_INS_CRBNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNHE, SYSZ_INS_CRBNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNL, SYSZ_INS_CRBNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNLE, SYSZ_INS_CRBNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRBAsmNLH, SYSZ_INS_CRBNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + SystemZ_CRDTE, SYSZ_INS_CRDTE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRDTEOpt, SYSZ_INS_CRDTE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRJAsm, SYSZ_INS_CRJ, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmE, SYSZ_INS_CRJE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmH, SYSZ_INS_CRJH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmHE, SYSZ_INS_CRJHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmL, SYSZ_INS_CRJL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmLE, SYSZ_INS_CRJLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmLH, SYSZ_INS_CRJLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNE, SYSZ_INS_CRJNE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNH, SYSZ_INS_CRJNH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNHE, SYSZ_INS_CRJNHE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNL, SYSZ_INS_CRJNL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNLE, SYSZ_INS_CRJNLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRJAsmNLH, SYSZ_INS_CRJNLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_CRL, SYSZ_INS_CRL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsm, SYSZ_INS_CRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmE, SYSZ_INS_CRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmH, SYSZ_INS_CRTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmHE, SYSZ_INS_CRTHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmL, SYSZ_INS_CRTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmLE, SYSZ_INS_CRTLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmLH, SYSZ_INS_CRTLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNE, SYSZ_INS_CRTNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNH, SYSZ_INS_CRTNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNHE, SYSZ_INS_CRTNHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNL, SYSZ_INS_CRTNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNLE, SYSZ_INS_CRTNLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CRTAsmNLH, SYSZ_INS_CRTNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CS, SYSZ_INS_CS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSCH, SYSZ_INS_CSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSDTR, SYSZ_INS_CSDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSG, SYSZ_INS_CSG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSP, SYSZ_INS_CSP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSPG, SYSZ_INS_CSPG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSST, SYSZ_INS_CSST, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSXTR, SYSZ_INS_CSXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CSY, SYSZ_INS_CSY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU12, SYSZ_INS_CU12, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU12Opt, SYSZ_INS_CU12, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU14, SYSZ_INS_CU14, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU14Opt, SYSZ_INS_CU14, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU21, SYSZ_INS_CU21, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU21Opt, SYSZ_INS_CU21, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU24, SYSZ_INS_CU24, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU24Opt, SYSZ_INS_CU24, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU41, SYSZ_INS_CU41, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CU42, SYSZ_INS_CU42, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUDTR, SYSZ_INS_CUDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUSE, SYSZ_INS_CUSE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUTFU, SYSZ_INS_CUTFU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUTFUOpt, SYSZ_INS_CUTFU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUUTF, SYSZ_INS_CUUTF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUUTFOpt, SYSZ_INS_CUUTF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CUXTR, SYSZ_INS_CUXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVB, SYSZ_INS_CVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVBG, SYSZ_INS_CVBG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVBY, SYSZ_INS_CVBY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVD, SYSZ_INS_CVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVDG, SYSZ_INS_CVDG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CVDY, SYSZ_INS_CVDY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXBR, SYSZ_INS_CXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXFBR, SYSZ_INS_CXFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXFBRA, SYSZ_INS_CXFBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXFR, SYSZ_INS_CXFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXFTR, SYSZ_INS_CXFTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXGBR, SYSZ_INS_CXGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXGBRA, SYSZ_INS_CXGBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXGR, SYSZ_INS_CXGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXGTR, SYSZ_INS_CXGTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXGTRA, SYSZ_INS_CXGTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXLFBR, SYSZ_INS_CXLFBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXLFTR, SYSZ_INS_CXLFTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXLGBR, SYSZ_INS_CXLGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXLGTR, SYSZ_INS_CXLGTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXPT, SYSZ_INS_CXPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXR, SYSZ_INS_CXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXSTR, SYSZ_INS_CXSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXTR, SYSZ_INS_CXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXUTR, SYSZ_INS_CXUTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CXZT, SYSZ_INS_CXZT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CY, SYSZ_INS_CY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_CZDT, SYSZ_INS_CZDT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_CZXT, SYSZ_INS_CZXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_D, SYSZ_INS_D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DD, SYSZ_INS_DD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DDB, SYSZ_INS_DDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DDBR, SYSZ_INS_DDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DDR, SYSZ_INS_DDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DDTR, SYSZ_INS_DDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DDTRA, SYSZ_INS_DDTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_DE, SYSZ_INS_DE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DEB, SYSZ_INS_DEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DEBR, SYSZ_INS_DEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DER, SYSZ_INS_DER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DIAG, SYSZ_INS_DIAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DIDBR, SYSZ_INS_DIDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DIEBR, SYSZ_INS_DIEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DL, SYSZ_INS_DL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DLG, SYSZ_INS_DLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DLGR, SYSZ_INS_DLGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DLR, SYSZ_INS_DLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DP, SYSZ_INS_DP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DR, SYSZ_INS_DR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DSG, SYSZ_INS_DSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DSGF, SYSZ_INS_DSGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DSGFR, SYSZ_INS_DSGFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DSGR, SYSZ_INS_DSGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DXBR, SYSZ_INS_DXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DXR, SYSZ_INS_DXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DXTR, SYSZ_INS_DXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_DXTRA, SYSZ_INS_DXTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_EAR, SYSZ_INS_EAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ECAG, SYSZ_INS_ECAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ECCTR, SYSZ_INS_ECCTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ECPGA, SYSZ_INS_ECPGA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ECTG, SYSZ_INS_ECTG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ED, SYSZ_INS_ED, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EDMK, SYSZ_INS_EDMK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EEDTR, SYSZ_INS_EEDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EEXTR, SYSZ_INS_EEXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EFPC, SYSZ_INS_EFPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EPAIR, SYSZ_INS_EPAIR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EPAR, SYSZ_INS_EPAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EPCTR, SYSZ_INS_EPCTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EPSW, SYSZ_INS_EPSW, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EREG, SYSZ_INS_EREG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EREGG, SYSZ_INS_EREGG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESAIR, SYSZ_INS_ESAIR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESAR, SYSZ_INS_ESAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESDTR, SYSZ_INS_ESDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESEA, SYSZ_INS_ESEA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESTA, SYSZ_INS_ESTA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ESXTR, SYSZ_INS_ESXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ETND, SYSZ_INS_ETND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_EX, SYSZ_INS_EX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_EXRL, SYSZ_INS_EXRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIDBR, SYSZ_INS_FIDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIDBRA, SYSZ_INS_FIDBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIDR, SYSZ_INS_FIDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIDTR, SYSZ_INS_FIDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIEBR, SYSZ_INS_FIEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIEBRA, SYSZ_INS_FIEBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIER, SYSZ_INS_FIER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIXBR, SYSZ_INS_FIXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIXBRA, SYSZ_INS_FIXBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIXR, SYSZ_INS_FIXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FIXTR, SYSZ_INS_FIXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_FLOGR, SYSZ_INS_FLOGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_HDR, SYSZ_INS_HDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_HER, SYSZ_INS_HER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_HSCH, SYSZ_INS_HSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IAC, SYSZ_INS_IAC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IC, SYSZ_INS_IC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ICM, SYSZ_INS_ICM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ICMH, SYSZ_INS_ICMH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ICMY, SYSZ_INS_ICMY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ICY, SYSZ_INS_ICY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IDTE, SYSZ_INS_IDTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IDTEOpt, SYSZ_INS_IDTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IEDTR, SYSZ_INS_IEDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IEXTR, SYSZ_INS_IEXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IIHF, SYSZ_INS_IIHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IIHH, SYSZ_INS_IIHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IIHL, SYSZ_INS_IIHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IILF, SYSZ_INS_IILF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IILH, SYSZ_INS_IILH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IILL, SYSZ_INS_IILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IPK, SYSZ_INS_IPK, +#ifndef CAPSTONE_DIET + { SYSZ_REG_2, 0 }, { SYSZ_REG_2, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IPM, SYSZ_INS_IPM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IPTE, SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IPTEOpt, SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IPTEOptOpt, SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IRBM, SYSZ_INS_IRBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ISKE, SYSZ_INS_ISKE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_IVSK, SYSZ_INS_IVSK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_J, SYSZ_INS_J, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmE, SYSZ_INS_JE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmH, SYSZ_INS_JH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmHE, SYSZ_INS_JHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmL, SYSZ_INS_JL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmLE, SYSZ_INS_JLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmLH, SYSZ_INS_JLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmM, SYSZ_INS_JM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNE, SYSZ_INS_JNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNH, SYSZ_INS_JNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNHE, SYSZ_INS_JNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNL, SYSZ_INS_JNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNLE, SYSZ_INS_JNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNLH, SYSZ_INS_JNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNM, SYSZ_INS_JNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNO, SYSZ_INS_JNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNP, SYSZ_INS_JNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmNZ, SYSZ_INS_JNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmO, SYSZ_INS_JO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmP, SYSZ_INS_JP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JAsmZ, SYSZ_INS_JZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JG, SYSZ_INS_JG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmE, SYSZ_INS_JGE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmH, SYSZ_INS_JGH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmHE, SYSZ_INS_JGHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmL, SYSZ_INS_JGL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmLE, SYSZ_INS_JGLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmLH, SYSZ_INS_JGLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmM, SYSZ_INS_JGM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNE, SYSZ_INS_JGNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNH, SYSZ_INS_JGNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNHE, SYSZ_INS_JGNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNL, SYSZ_INS_JGNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNLE, SYSZ_INS_JGNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNLH, SYSZ_INS_JGNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNM, SYSZ_INS_JGNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNO, SYSZ_INS_JGNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNP, SYSZ_INS_JGNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmNZ, SYSZ_INS_JGNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmO, SYSZ_INS_JGO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmP, SYSZ_INS_JGP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_JGAsmZ, SYSZ_INS_JGZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + SystemZ_KDB, SYSZ_INS_KDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KDBR, SYSZ_INS_KDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KDTR, SYSZ_INS_KDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KEB, SYSZ_INS_KEB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KEBR, SYSZ_INS_KEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KIMD, SYSZ_INS_KIMD, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KLMD, SYSZ_INS_KLMD, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KM, SYSZ_INS_KM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMA, SYSZ_INS_KMA, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST8, 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMAC, SYSZ_INS_KMAC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMC, SYSZ_INS_KMC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMCTR, SYSZ_INS_KMCTR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMF, SYSZ_INS_KMF, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 +#endif +}, +{ + SystemZ_KMO, SYSZ_INS_KMO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 +#endif +}, +{ + SystemZ_KXBR, SYSZ_INS_KXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_KXTR, SYSZ_INS_KXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_L, SYSZ_INS_L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LA, SYSZ_INS_LA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAA, SYSZ_INS_LAA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAAG, SYSZ_INS_LAAG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAAL, SYSZ_INS_LAAL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAALG, SYSZ_INS_LAALG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAE, SYSZ_INS_LAE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAEY, SYSZ_INS_LAEY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAM, SYSZ_INS_LAM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAMY, SYSZ_INS_LAMY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAN, SYSZ_INS_LAN, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LANG, SYSZ_INS_LANG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAO, SYSZ_INS_LAO, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAOG, SYSZ_INS_LAOG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LARL, SYSZ_INS_LARL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LASP, SYSZ_INS_LASP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAT, SYSZ_INS_LAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAX, SYSZ_INS_LAX, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAXG, SYSZ_INS_LAXG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LAY, SYSZ_INS_LAY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LB, SYSZ_INS_LB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LBH, SYSZ_INS_LBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LBR, SYSZ_INS_LBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCBB, SYSZ_INS_LCBB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCCTL, SYSZ_INS_LCCTL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCDBR, SYSZ_INS_LCDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCDFR, SYSZ_INS_LCDFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCDR, SYSZ_INS_LCDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCEBR, SYSZ_INS_LCEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCER, SYSZ_INS_LCER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCGFR, SYSZ_INS_LCGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCGR, SYSZ_INS_LCGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCR, SYSZ_INS_LCR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCTL, SYSZ_INS_LCTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCTLG, SYSZ_INS_LCTLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCXBR, SYSZ_INS_LCXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LCXR, SYSZ_INS_LCXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LD, SYSZ_INS_LD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDE, SYSZ_INS_LDE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDEB, SYSZ_INS_LDEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDEBR, SYSZ_INS_LDEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDER, SYSZ_INS_LDER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDETR, SYSZ_INS_LDETR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDGR, SYSZ_INS_LDGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDR, SYSZ_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDXBR, SYSZ_INS_LDXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDXBRA, SYSZ_INS_LDXBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDXR, SYSZ_INS_LDXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDXTR, SYSZ_INS_LDXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LDY, SYSZ_INS_LDY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LE, SYSZ_INS_LE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEDBR, SYSZ_INS_LEDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEDBRA, SYSZ_INS_LEDBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEDR, SYSZ_INS_LEDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEDTR, SYSZ_INS_LEDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LER, SYSZ_INS_LER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEXBR, SYSZ_INS_LEXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEXBRA, SYSZ_INS_LEXBRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEXR, SYSZ_INS_LEXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LEY, SYSZ_INS_LEY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LFAS, SYSZ_INS_LFAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LFH, SYSZ_INS_LFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LFHAT, SYSZ_INS_LFHAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LFPC, SYSZ_INS_LFPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LG, SYSZ_INS_LG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGAT, SYSZ_INS_LGAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGB, SYSZ_INS_LGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGBR, SYSZ_INS_LGBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGDR, SYSZ_INS_LGDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGF, SYSZ_INS_LGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGFI, SYSZ_INS_LGFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGFR, SYSZ_INS_LGFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGFRL, SYSZ_INS_LGFRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGG, SYSZ_INS_LGG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGH, SYSZ_INS_LGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGHI, SYSZ_INS_LGHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGHR, SYSZ_INS_LGHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGHRL, SYSZ_INS_LGHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGR, SYSZ_INS_LGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGRL, SYSZ_INS_LGRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LGSC, SYSZ_INS_LGSC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LH, SYSZ_INS_LH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LHH, SYSZ_INS_LHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LHI, SYSZ_INS_LHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LHR, SYSZ_INS_LHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LHRL, SYSZ_INS_LHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LHY, SYSZ_INS_LHY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLC, SYSZ_INS_LLC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLCH, SYSZ_INS_LLCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLCR, SYSZ_INS_LLCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGC, SYSZ_INS_LLGC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGCR, SYSZ_INS_LLGCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGF, SYSZ_INS_LLGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGFAT, SYSZ_INS_LLGFAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGFR, SYSZ_INS_LLGFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGFRL, SYSZ_INS_LLGFRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGFSG, SYSZ_INS_LLGFSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGH, SYSZ_INS_LLGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGHR, SYSZ_INS_LLGHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGHRL, SYSZ_INS_LLGHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGT, SYSZ_INS_LLGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGTAT, SYSZ_INS_LLGTAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLGTR, SYSZ_INS_LLGTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLH, SYSZ_INS_LLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLHH, SYSZ_INS_LLHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLHR, SYSZ_INS_LLHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLHRL, SYSZ_INS_LLHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLIHF, SYSZ_INS_LLIHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLIHH, SYSZ_INS_LLIHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLIHL, SYSZ_INS_LLIHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLILF, SYSZ_INS_LLILF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLILH, SYSZ_INS_LLILH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLILL, SYSZ_INS_LLILL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LLZRGF, SYSZ_INS_LLZRGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LM, SYSZ_INS_LM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LMD, SYSZ_INS_LMD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LMG, SYSZ_INS_LMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LMH, SYSZ_INS_LMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LMY, SYSZ_INS_LMY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNDBR, SYSZ_INS_LNDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNDFR, SYSZ_INS_LNDFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNDR, SYSZ_INS_LNDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNEBR, SYSZ_INS_LNEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNER, SYSZ_INS_LNER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNGFR, SYSZ_INS_LNGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNGR, SYSZ_INS_LNGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNR, SYSZ_INS_LNR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNXBR, SYSZ_INS_LNXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LNXR, SYSZ_INS_LNXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsm, SYSZ_INS_LOC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmE, SYSZ_INS_LOCE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmH, SYSZ_INS_LOCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmHE, SYSZ_INS_LOCHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmL, SYSZ_INS_LOCL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmLE, SYSZ_INS_LOCLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmLH, SYSZ_INS_LOCLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmM, SYSZ_INS_LOCM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNE, SYSZ_INS_LOCNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNH, SYSZ_INS_LOCNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNHE, SYSZ_INS_LOCNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNL, SYSZ_INS_LOCNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNLE, SYSZ_INS_LOCNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNLH, SYSZ_INS_LOCNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNM, SYSZ_INS_LOCNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNO, SYSZ_INS_LOCNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNP, SYSZ_INS_LOCNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmNZ, SYSZ_INS_LOCNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmO, SYSZ_INS_LOCO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmP, SYSZ_INS_LOCP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCAsmZ, SYSZ_INS_LOCZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsm, SYSZ_INS_LOCFH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmE, SYSZ_INS_LOCFHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmH, SYSZ_INS_LOCFHH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmHE, SYSZ_INS_LOCFHHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmL, SYSZ_INS_LOCFHL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmLE, SYSZ_INS_LOCFHLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmLH, SYSZ_INS_LOCFHLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmM, SYSZ_INS_LOCFHM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNE, SYSZ_INS_LOCFHNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNH, SYSZ_INS_LOCFHNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNHE, SYSZ_INS_LOCFHNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNL, SYSZ_INS_LOCFHNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNLE, SYSZ_INS_LOCFHNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNLH, SYSZ_INS_LOCFHNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNM, SYSZ_INS_LOCFHNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNO, SYSZ_INS_LOCFHNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNP, SYSZ_INS_LOCFHNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmNZ, SYSZ_INS_LOCFHNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmO, SYSZ_INS_LOCFHO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmP, SYSZ_INS_LOCFHP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHAsmZ, SYSZ_INS_LOCFHZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsm, SYSZ_INS_LOCFHR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmE, SYSZ_INS_LOCFHRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmH, SYSZ_INS_LOCFHRH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmHE, SYSZ_INS_LOCFHRHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmL, SYSZ_INS_LOCFHRL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmLE, SYSZ_INS_LOCFHRLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmLH, SYSZ_INS_LOCFHRLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmM, SYSZ_INS_LOCFHRM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNE, SYSZ_INS_LOCFHRNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNH, SYSZ_INS_LOCFHRNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNHE, SYSZ_INS_LOCFHRNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNL, SYSZ_INS_LOCFHRNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNLE, SYSZ_INS_LOCFHRNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNLH, SYSZ_INS_LOCFHRNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNM, SYSZ_INS_LOCFHRNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNO, SYSZ_INS_LOCFHRNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNP, SYSZ_INS_LOCFHRNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmNZ, SYSZ_INS_LOCFHRNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmO, SYSZ_INS_LOCFHRO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmP, SYSZ_INS_LOCFHRP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCFHRAsmZ, SYSZ_INS_LOCFHRZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsm, SYSZ_INS_LOCG, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmE, SYSZ_INS_LOCGE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmH, SYSZ_INS_LOCGH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmHE, SYSZ_INS_LOCGHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmL, SYSZ_INS_LOCGL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmLE, SYSZ_INS_LOCGLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmLH, SYSZ_INS_LOCGLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmM, SYSZ_INS_LOCGM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNE, SYSZ_INS_LOCGNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNH, SYSZ_INS_LOCGNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNHE, SYSZ_INS_LOCGNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNL, SYSZ_INS_LOCGNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNLE, SYSZ_INS_LOCGNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNLH, SYSZ_INS_LOCGNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNM, SYSZ_INS_LOCGNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNO, SYSZ_INS_LOCGNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNP, SYSZ_INS_LOCGNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmNZ, SYSZ_INS_LOCGNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmO, SYSZ_INS_LOCGO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmP, SYSZ_INS_LOCGP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGAsmZ, SYSZ_INS_LOCGZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsm, SYSZ_INS_LOCGHI, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmE, SYSZ_INS_LOCGHIE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmH, SYSZ_INS_LOCGHIH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmHE, SYSZ_INS_LOCGHIHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmL, SYSZ_INS_LOCGHIL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmLE, SYSZ_INS_LOCGHILE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmLH, SYSZ_INS_LOCGHILH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmM, SYSZ_INS_LOCGHIM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNE, SYSZ_INS_LOCGHINE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNH, SYSZ_INS_LOCGHINH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNHE, SYSZ_INS_LOCGHINHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNL, SYSZ_INS_LOCGHINL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNLE, SYSZ_INS_LOCGHINLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNLH, SYSZ_INS_LOCGHINLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNM, SYSZ_INS_LOCGHINM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNO, SYSZ_INS_LOCGHINO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNP, SYSZ_INS_LOCGHINP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmNZ, SYSZ_INS_LOCGHINZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmO, SYSZ_INS_LOCGHIO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmP, SYSZ_INS_LOCGHIP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGHIAsmZ, SYSZ_INS_LOCGHIZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsm, SYSZ_INS_LOCGR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmE, SYSZ_INS_LOCGRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmH, SYSZ_INS_LOCGRH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmHE, SYSZ_INS_LOCGRHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmL, SYSZ_INS_LOCGRL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmLE, SYSZ_INS_LOCGRLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmLH, SYSZ_INS_LOCGRLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmM, SYSZ_INS_LOCGRM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNE, SYSZ_INS_LOCGRNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNH, SYSZ_INS_LOCGRNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNHE, SYSZ_INS_LOCGRNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNL, SYSZ_INS_LOCGRNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNLE, SYSZ_INS_LOCGRNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNLH, SYSZ_INS_LOCGRNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNM, SYSZ_INS_LOCGRNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNO, SYSZ_INS_LOCGRNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNP, SYSZ_INS_LOCGRNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmNZ, SYSZ_INS_LOCGRNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmO, SYSZ_INS_LOCGRO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmP, SYSZ_INS_LOCGRP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCGRAsmZ, SYSZ_INS_LOCGRZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsm, SYSZ_INS_LOCHHI, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmE, SYSZ_INS_LOCHHIE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmH, SYSZ_INS_LOCHHIH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmHE, SYSZ_INS_LOCHHIHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmL, SYSZ_INS_LOCHHIL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmLE, SYSZ_INS_LOCHHILE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmLH, SYSZ_INS_LOCHHILH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmM, SYSZ_INS_LOCHHIM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNE, SYSZ_INS_LOCHHINE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNH, SYSZ_INS_LOCHHINH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNHE, SYSZ_INS_LOCHHINHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNL, SYSZ_INS_LOCHHINL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNLE, SYSZ_INS_LOCHHINLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNLH, SYSZ_INS_LOCHHINLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNM, SYSZ_INS_LOCHHINM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNO, SYSZ_INS_LOCHHINO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNP, SYSZ_INS_LOCHHINP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmNZ, SYSZ_INS_LOCHHINZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmO, SYSZ_INS_LOCHHIO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmP, SYSZ_INS_LOCHHIP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHHIAsmZ, SYSZ_INS_LOCHHIZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsm, SYSZ_INS_LOCHI, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmE, SYSZ_INS_LOCHIE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmH, SYSZ_INS_LOCHIH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmHE, SYSZ_INS_LOCHIHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmL, SYSZ_INS_LOCHIL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmLE, SYSZ_INS_LOCHILE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmLH, SYSZ_INS_LOCHILH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmM, SYSZ_INS_LOCHIM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNE, SYSZ_INS_LOCHINE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNH, SYSZ_INS_LOCHINH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNHE, SYSZ_INS_LOCHINHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNL, SYSZ_INS_LOCHINL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNLE, SYSZ_INS_LOCHINLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNLH, SYSZ_INS_LOCHINLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNM, SYSZ_INS_LOCHINM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNO, SYSZ_INS_LOCHINO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNP, SYSZ_INS_LOCHINP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmNZ, SYSZ_INS_LOCHINZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmO, SYSZ_INS_LOCHIO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmP, SYSZ_INS_LOCHIP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCHIAsmZ, SYSZ_INS_LOCHIZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsm, SYSZ_INS_LOCR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmE, SYSZ_INS_LOCRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmH, SYSZ_INS_LOCRH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmHE, SYSZ_INS_LOCRHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmL, SYSZ_INS_LOCRL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmLE, SYSZ_INS_LOCRLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmLH, SYSZ_INS_LOCRLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmM, SYSZ_INS_LOCRM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNE, SYSZ_INS_LOCRNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNH, SYSZ_INS_LOCRNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNHE, SYSZ_INS_LOCRNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNL, SYSZ_INS_LOCRNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNLE, SYSZ_INS_LOCRNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNLH, SYSZ_INS_LOCRNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNM, SYSZ_INS_LOCRNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNO, SYSZ_INS_LOCRNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNP, SYSZ_INS_LOCRNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmNZ, SYSZ_INS_LOCRNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmO, SYSZ_INS_LOCRO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmP, SYSZ_INS_LOCRP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LOCRAsmZ, SYSZ_INS_LOCRZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPCTL, SYSZ_INS_LPCTL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPD, SYSZ_INS_LPD, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPDBR, SYSZ_INS_LPDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPDFR, SYSZ_INS_LPDFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPDG, SYSZ_INS_LPDG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPDR, SYSZ_INS_LPDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPEBR, SYSZ_INS_LPEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPER, SYSZ_INS_LPER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPGFR, SYSZ_INS_LPGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPGR, SYSZ_INS_LPGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPP, SYSZ_INS_LPP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPQ, SYSZ_INS_LPQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPR, SYSZ_INS_LPR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPSW, SYSZ_INS_LPSW, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPSWE, SYSZ_INS_LPSWE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPTEA, SYSZ_INS_LPTEA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPXBR, SYSZ_INS_LPXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LPXR, SYSZ_INS_LPXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LR, SYSZ_INS_LR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRA, SYSZ_INS_LRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRAG, SYSZ_INS_LRAG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRAY, SYSZ_INS_LRAY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRDR, SYSZ_INS_LRDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRER, SYSZ_INS_LRER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRL, SYSZ_INS_LRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRV, SYSZ_INS_LRV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRVG, SYSZ_INS_LRVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRVGR, SYSZ_INS_LRVGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRVH, SYSZ_INS_LRVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LRVR, SYSZ_INS_LRVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LSCTL, SYSZ_INS_LSCTL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LT, SYSZ_INS_LT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTDBR, SYSZ_INS_LTDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTDR, SYSZ_INS_LTDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTDTR, SYSZ_INS_LTDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTEBR, SYSZ_INS_LTEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTER, SYSZ_INS_LTER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTG, SYSZ_INS_LTG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTGF, SYSZ_INS_LTGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTGFR, SYSZ_INS_LTGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTGR, SYSZ_INS_LTGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTR, SYSZ_INS_LTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTXBR, SYSZ_INS_LTXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTXR, SYSZ_INS_LTXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LTXTR, SYSZ_INS_LTXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LURA, SYSZ_INS_LURA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LURAG, SYSZ_INS_LURAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXD, SYSZ_INS_LXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXDB, SYSZ_INS_LXDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXDBR, SYSZ_INS_LXDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXDR, SYSZ_INS_LXDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXDTR, SYSZ_INS_LXDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXE, SYSZ_INS_LXE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXEB, SYSZ_INS_LXEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXEBR, SYSZ_INS_LXEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXER, SYSZ_INS_LXER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LXR, SYSZ_INS_LXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LY, SYSZ_INS_LY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LZDR, SYSZ_INS_LZDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LZER, SYSZ_INS_LZER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_LZRF, SYSZ_INS_LZRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LZRG, SYSZ_INS_LZRG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_LZXR, SYSZ_INS_LZXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_M, SYSZ_INS_M, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAD, SYSZ_INS_MAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MADB, SYSZ_INS_MADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MADBR, SYSZ_INS_MADBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MADR, SYSZ_INS_MADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAE, SYSZ_INS_MAE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAEB, SYSZ_INS_MAEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAEBR, SYSZ_INS_MAEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAER, SYSZ_INS_MAER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAY, SYSZ_INS_MAY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAYH, SYSZ_INS_MAYH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAYHR, SYSZ_INS_MAYHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAYL, SYSZ_INS_MAYL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAYLR, SYSZ_INS_MAYLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MAYR, SYSZ_INS_MAYR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MC, SYSZ_INS_MC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MD, SYSZ_INS_MD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDB, SYSZ_INS_MDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDBR, SYSZ_INS_MDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDE, SYSZ_INS_MDE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDEB, SYSZ_INS_MDEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDEBR, SYSZ_INS_MDEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDER, SYSZ_INS_MDER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDR, SYSZ_INS_MDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDTR, SYSZ_INS_MDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MDTRA, SYSZ_INS_MDTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_ME, SYSZ_INS_ME, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MEE, SYSZ_INS_MEE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MEEB, SYSZ_INS_MEEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MEEBR, SYSZ_INS_MEEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MEER, SYSZ_INS_MEER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MER, SYSZ_INS_MER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MFY, SYSZ_INS_MFY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MG, SYSZ_INS_MG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MGH, SYSZ_INS_MGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MGHI, SYSZ_INS_MGHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MGRK, SYSZ_INS_MGRK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MH, SYSZ_INS_MH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MHI, SYSZ_INS_MHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MHY, SYSZ_INS_MHY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ML, SYSZ_INS_ML, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MLG, SYSZ_INS_MLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MLGR, SYSZ_INS_MLGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MLR, SYSZ_INS_MLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MP, SYSZ_INS_MP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MR, SYSZ_INS_MR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MS, SYSZ_INS_MS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSC, SYSZ_INS_MSC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSCH, SYSZ_INS_MSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSD, SYSZ_INS_MSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSDB, SYSZ_INS_MSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSDBR, SYSZ_INS_MSDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSDR, SYSZ_INS_MSDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSE, SYSZ_INS_MSE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSEB, SYSZ_INS_MSEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSEBR, SYSZ_INS_MSEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSER, SYSZ_INS_MSER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSFI, SYSZ_INS_MSFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSG, SYSZ_INS_MSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGC, SYSZ_INS_MSGC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGF, SYSZ_INS_MSGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGFI, SYSZ_INS_MSGFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGFR, SYSZ_INS_MSGFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGR, SYSZ_INS_MSGR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSGRKC, SYSZ_INS_MSGRKC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSR, SYSZ_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSRKC, SYSZ_INS_MSRKC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSTA, SYSZ_INS_MSTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MSY, SYSZ_INS_MSY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVC, SYSZ_INS_MVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCDK, SYSZ_INS_MVCDK, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCIN, SYSZ_INS_MVCIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCK, SYSZ_INS_MVCK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCL, SYSZ_INS_MVCL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCLE, SYSZ_INS_MVCLE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCLU, SYSZ_INS_MVCLU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCOS, SYSZ_INS_MVCOS, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCP, SYSZ_INS_MVCP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCS, SYSZ_INS_MVCS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVCSK, SYSZ_INS_MVCSK, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVGHI, SYSZ_INS_MVGHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVHHI, SYSZ_INS_MVHHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVHI, SYSZ_INS_MVHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVI, SYSZ_INS_MVI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVIY, SYSZ_INS_MVIY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVN, SYSZ_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVO, SYSZ_INS_MVO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVPG, SYSZ_INS_MVPG, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVST, SYSZ_INS_MVST, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MVZ, SYSZ_INS_MVZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXBR, SYSZ_INS_MXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXD, SYSZ_INS_MXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXDB, SYSZ_INS_MXDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXDBR, SYSZ_INS_MXDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXDR, SYSZ_INS_MXDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXR, SYSZ_INS_MXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXTR, SYSZ_INS_MXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MXTRA, SYSZ_INS_MXTRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_MY, SYSZ_INS_MY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MYH, SYSZ_INS_MYH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MYHR, SYSZ_INS_MYHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MYL, SYSZ_INS_MYL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MYLR, SYSZ_INS_MYLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_MYR, SYSZ_INS_MYR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_N, SYSZ_INS_N, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NC, SYSZ_INS_NC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NG, SYSZ_INS_NG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NGR, SYSZ_INS_NGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NGRK, SYSZ_INS_NGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_NI, SYSZ_INS_NI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NIAI, SYSZ_INS_NIAI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 +#endif +}, +{ + SystemZ_NIHF, SYSZ_INS_NIHF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NIHH, SYSZ_INS_NIHH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NIHL, SYSZ_INS_NIHL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NILF, SYSZ_INS_NILF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NILH, SYSZ_INS_NILH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NILL, SYSZ_INS_NILL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NIY, SYSZ_INS_NIY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NR, SYSZ_INS_NR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_NRK, SYSZ_INS_NRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_NTSTG, SYSZ_INS_NTSTG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_NY, SYSZ_INS_NY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_O, SYSZ_INS_O, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OC, SYSZ_INS_OC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OG, SYSZ_INS_OG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OGR, SYSZ_INS_OGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OGRK, SYSZ_INS_OGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_OI, SYSZ_INS_OI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OIHF, SYSZ_INS_OIHF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OIHH, SYSZ_INS_OIHH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OIHL, SYSZ_INS_OIHL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OILF, SYSZ_INS_OILF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OILH, SYSZ_INS_OILH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OILL, SYSZ_INS_OILL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OIY, SYSZ_INS_OIY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_OR, SYSZ_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ORK, SYSZ_INS_ORK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_OY, SYSZ_INS_OY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PACK, SYSZ_INS_PACK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PALB, SYSZ_INS_PALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PC, SYSZ_INS_PC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PCC, SYSZ_INS_PCC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PCKMO, SYSZ_INS_PCKMO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST3, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PFD, SYSZ_INS_PFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PFDRL, SYSZ_INS_PFDRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PFMF, SYSZ_INS_PFMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PFPO, SYSZ_INS_PFPO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_F4Q, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_F0Q, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PGIN, SYSZ_INS_PGIN, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PGOUT, SYSZ_INS_PGOUT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PKA, SYSZ_INS_PKA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PKU, SYSZ_INS_PKU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PLO, SYSZ_INS_PLO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_POPCNT, SYSZ_INS_POPCNT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_POPULATIONCOUNT, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PPA, SYSZ_INS_PPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_PROCESSORASSIST, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PPNO, SYSZ_INS_PPNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST5, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PR, SYSZ_INS_PR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PRNO, SYSZ_INS_PRNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST7, 0 }, 0, 0 +#endif +}, +{ + SystemZ_PT, SYSZ_INS_PT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PTF, SYSZ_INS_PTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PTFF, SYSZ_INS_PTFF, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PTI, SYSZ_INS_PTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_PTLB, SYSZ_INS_PTLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_QADTR, SYSZ_INS_QADTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_QAXTR, SYSZ_INS_QAXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_QCTRI, SYSZ_INS_QCTRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_QSI, SYSZ_INS_QSI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RCHP, SYSZ_INS_RCHP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RISBG, SYSZ_INS_RISBG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RISBGN, SYSZ_INS_RISBGN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_RISBHG, SYSZ_INS_RISBHG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_RISBLG, SYSZ_INS_RISBLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_RLL, SYSZ_INS_RLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RLLG, SYSZ_INS_RLLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RNSBG, SYSZ_INS_RNSBG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ROSBG, SYSZ_INS_ROSBG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RP, SYSZ_INS_RP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RRBE, SYSZ_INS_RRBE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RRBM, SYSZ_INS_RRBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_RRDTR, SYSZ_INS_RRDTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RRXTR, SYSZ_INS_RRXTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RSCH, SYSZ_INS_RSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_RXSBG, SYSZ_INS_RXSBG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_S, SYSZ_INS_S, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAC, SYSZ_INS_SAC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SACF, SYSZ_INS_SACF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAL, SYSZ_INS_SAL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAM24, SYSZ_INS_SAM24, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAM31, SYSZ_INS_SAM31, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAM64, SYSZ_INS_SAM64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SAR, SYSZ_INS_SAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SCCTR, SYSZ_INS_SCCTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SCHM, SYSZ_INS_SCHM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, SYSZ_REG_2, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SCK, SYSZ_INS_SCK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SCKC, SYSZ_INS_SCKC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SCKPF, SYSZ_INS_SCKPF, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SD, SYSZ_INS_SD, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SDB, SYSZ_INS_SDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SDBR, SYSZ_INS_SDBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SDR, SYSZ_INS_SDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SDTR, SYSZ_INS_SDTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SDTRA, SYSZ_INS_SDTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SE, SYSZ_INS_SE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SEB, SYSZ_INS_SEB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SEBR, SYSZ_INS_SEBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SER, SYSZ_INS_SER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SFASR, SYSZ_INS_SFASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SFPC, SYSZ_INS_SFPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SG, SYSZ_INS_SG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SGF, SYSZ_INS_SGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SGFR, SYSZ_INS_SGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SGH, SYSZ_INS_SGH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SGR, SYSZ_INS_SGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SGRK, SYSZ_INS_SGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SH, SYSZ_INS_SH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SHHHR, SYSZ_INS_SHHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SHHLR, SYSZ_INS_SHHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SHY, SYSZ_INS_SHY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SIE, SYSZ_INS_SIE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SIGA, SYSZ_INS_SIGA, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SIGP, SYSZ_INS_SIGP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SL, SYSZ_INS_SL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLA, SYSZ_INS_SLA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLAG, SYSZ_INS_SLAG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLAK, SYSZ_INS_SLAK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLB, SYSZ_INS_SLB, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLBG, SYSZ_INS_SLBG, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLBGR, SYSZ_INS_SLBGR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLBR, SYSZ_INS_SLBR, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLDA, SYSZ_INS_SLDA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLDL, SYSZ_INS_SLDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLDT, SYSZ_INS_SLDT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLFI, SYSZ_INS_SLFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLG, SYSZ_INS_SLG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLGF, SYSZ_INS_SLGF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLGFI, SYSZ_INS_SLGFI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLGFR, SYSZ_INS_SLGFR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLGR, SYSZ_INS_SLGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLGRK, SYSZ_INS_SLGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLHHHR, SYSZ_INS_SLHHHR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLHHLR, SYSZ_INS_SLHHLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLL, SYSZ_INS_SLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLLG, SYSZ_INS_SLLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLLK, SYSZ_INS_SLLK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLR, SYSZ_INS_SLR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLRK, SYSZ_INS_SLRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLXT, SYSZ_INS_SLXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SLY, SYSZ_INS_SLY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SP, SYSZ_INS_SP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SPCTR, SYSZ_INS_SPCTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SPKA, SYSZ_INS_SPKA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SPM, SYSZ_INS_SPM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SPT, SYSZ_INS_SPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SPX, SYSZ_INS_SPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQD, SYSZ_INS_SQD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQDB, SYSZ_INS_SQDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQDBR, SYSZ_INS_SQDBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQDR, SYSZ_INS_SQDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQE, SYSZ_INS_SQE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQEB, SYSZ_INS_SQEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQEBR, SYSZ_INS_SQEBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQER, SYSZ_INS_SQER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQXBR, SYSZ_INS_SQXBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SQXR, SYSZ_INS_SQXR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SR, SYSZ_INS_SR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRA, SYSZ_INS_SRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRAG, SYSZ_INS_SRAG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRAK, SYSZ_INS_SRAK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRDA, SYSZ_INS_SRDA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRDL, SYSZ_INS_SRDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRDT, SYSZ_INS_SRDT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRK, SYSZ_INS_SRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRL, SYSZ_INS_SRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRLG, SYSZ_INS_SRLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRLK, SYSZ_INS_SRLK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRNM, SYSZ_INS_SRNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRNMB, SYSZ_INS_SRNMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRNMT, SYSZ_INS_SRNMT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRP, SYSZ_INS_SRP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRST, SYSZ_INS_SRST, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRSTU, SYSZ_INS_SRSTU, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SRXT, SYSZ_INS_SRXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSAIR, SYSZ_INS_SSAIR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSAR, SYSZ_INS_SSAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSCH, SYSZ_INS_SSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSKE, SYSZ_INS_SSKE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSKEOpt, SYSZ_INS_SSKE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SSM, SYSZ_INS_SSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ST, SYSZ_INS_ST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STAM, SYSZ_INS_STAM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STAMY, SYSZ_INS_STAMY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STAP, SYSZ_INS_STAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STC, SYSZ_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCH, SYSZ_INS_STCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCK, SYSZ_INS_STCK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCKC, SYSZ_INS_STCKC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCKE, SYSZ_INS_STCKE, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCKF, SYSZ_INS_STCKF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCM, SYSZ_INS_STCM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCMH, SYSZ_INS_STCMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCMY, SYSZ_INS_STCMY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCPS, SYSZ_INS_STCPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCRW, SYSZ_INS_STCRW, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCTG, SYSZ_INS_STCTG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCTL, SYSZ_INS_STCTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STCY, SYSZ_INS_STCY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STD, SYSZ_INS_STD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STDY, SYSZ_INS_STDY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STE, SYSZ_INS_STE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STEY, SYSZ_INS_STEY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STFH, SYSZ_INS_STFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STFL, SYSZ_INS_STFL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STFLE, SYSZ_INS_STFLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STFPC, SYSZ_INS_STFPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STG, SYSZ_INS_STG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STGRL, SYSZ_INS_STGRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STGSC, SYSZ_INS_STGSC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STH, SYSZ_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STHH, SYSZ_INS_STHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STHRL, SYSZ_INS_STHRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STHY, SYSZ_INS_STHY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STIDP, SYSZ_INS_STIDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STM, SYSZ_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STMG, SYSZ_INS_STMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STMH, SYSZ_INS_STMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STMY, SYSZ_INS_STMY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STNSM, SYSZ_INS_STNSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsm, SYSZ_INS_STOC, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmE, SYSZ_INS_STOCE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmH, SYSZ_INS_STOCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmHE, SYSZ_INS_STOCHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmL, SYSZ_INS_STOCL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmLE, SYSZ_INS_STOCLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmLH, SYSZ_INS_STOCLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmM, SYSZ_INS_STOCM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNE, SYSZ_INS_STOCNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNH, SYSZ_INS_STOCNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNHE, SYSZ_INS_STOCNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNL, SYSZ_INS_STOCNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNLE, SYSZ_INS_STOCNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNLH, SYSZ_INS_STOCNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNM, SYSZ_INS_STOCNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNO, SYSZ_INS_STOCNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNP, SYSZ_INS_STOCNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmNZ, SYSZ_INS_STOCNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmO, SYSZ_INS_STOCO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmP, SYSZ_INS_STOCP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCAsmZ, SYSZ_INS_STOCZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsm, SYSZ_INS_STOCFH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmE, SYSZ_INS_STOCFHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmH, SYSZ_INS_STOCFHH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmHE, SYSZ_INS_STOCFHHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmL, SYSZ_INS_STOCFHL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmLE, SYSZ_INS_STOCFHLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmLH, SYSZ_INS_STOCFHLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmM, SYSZ_INS_STOCFHM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNE, SYSZ_INS_STOCFHNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNH, SYSZ_INS_STOCFHNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNHE, SYSZ_INS_STOCFHNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNL, SYSZ_INS_STOCFHNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNLE, SYSZ_INS_STOCFHNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNLH, SYSZ_INS_STOCFHNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNM, SYSZ_INS_STOCFHNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNO, SYSZ_INS_STOCFHNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNP, SYSZ_INS_STOCFHNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmNZ, SYSZ_INS_STOCFHNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmO, SYSZ_INS_STOCFHO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmP, SYSZ_INS_STOCFHP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCFHAsmZ, SYSZ_INS_STOCFHZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsm, SYSZ_INS_STOCG, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmE, SYSZ_INS_STOCGE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmH, SYSZ_INS_STOCGH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmHE, SYSZ_INS_STOCGHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmL, SYSZ_INS_STOCGL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmLE, SYSZ_INS_STOCGLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmLH, SYSZ_INS_STOCGLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmM, SYSZ_INS_STOCGM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNE, SYSZ_INS_STOCGNE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNH, SYSZ_INS_STOCGNH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNHE, SYSZ_INS_STOCGNHE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNL, SYSZ_INS_STOCGNL, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNLE, SYSZ_INS_STOCGNLE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNLH, SYSZ_INS_STOCGNLH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNM, SYSZ_INS_STOCGNM, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNO, SYSZ_INS_STOCGNO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNP, SYSZ_INS_STOCGNP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmNZ, SYSZ_INS_STOCGNZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmO, SYSZ_INS_STOCGO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmP, SYSZ_INS_STOCGP, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOCGAsmZ, SYSZ_INS_STOCGZ, +#ifndef CAPSTONE_DIET + { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 +#endif +}, +{ + SystemZ_STOSM, SYSZ_INS_STOSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STPQ, SYSZ_INS_STPQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STPT, SYSZ_INS_STPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STPX, SYSZ_INS_STPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STRAG, SYSZ_INS_STRAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STRL, SYSZ_INS_STRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STRV, SYSZ_INS_STRV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STRVG, SYSZ_INS_STRVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STRVH, SYSZ_INS_STRVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STSCH, SYSZ_INS_STSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STSI, SYSZ_INS_STSI, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STURA, SYSZ_INS_STURA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STURG, SYSZ_INS_STURG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_STY, SYSZ_INS_STY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SU, SYSZ_INS_SU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SUR, SYSZ_INS_SUR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SVC, SYSZ_INS_SVC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SW, SYSZ_INS_SW, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SWR, SYSZ_INS_SWR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SXBR, SYSZ_INS_SXBR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SXR, SYSZ_INS_SXR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SXTR, SYSZ_INS_SXTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_SXTRA, SYSZ_INS_SXTRA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_SY, SYSZ_INS_SY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TABORT, SYSZ_INS_TABORT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_TAM, SYSZ_INS_TAM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TAR, SYSZ_INS_TAR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TB, SYSZ_INS_TB, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TBDR, SYSZ_INS_TBDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TBEDR, SYSZ_INS_TBEDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TBEGIN, SYSZ_INS_TBEGIN, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_TBEGINC, SYSZ_INS_TBEGINC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_TCDB, SYSZ_INS_TCDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TCEB, SYSZ_INS_TCEB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TCXB, SYSZ_INS_TCXB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDCDT, SYSZ_INS_TDCDT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDCET, SYSZ_INS_TDCET, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDCXT, SYSZ_INS_TDCXT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDGDT, SYSZ_INS_TDGDT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDGET, SYSZ_INS_TDGET, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TDGXT, SYSZ_INS_TDGXT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TEND, SYSZ_INS_TEND, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 +#endif +}, +{ + SystemZ_THDER, SYSZ_INS_THDER, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_THDR, SYSZ_INS_THDR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TM, SYSZ_INS_TM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TMHH, SYSZ_INS_TMHH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TMHL, SYSZ_INS_TMHL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TMLH, SYSZ_INS_TMLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TMLL, SYSZ_INS_TMLL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TMY, SYSZ_INS_TMY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TP, SYSZ_INS_TP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TPI, SYSZ_INS_TPI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TPROT, SYSZ_INS_TPROT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TR, SYSZ_INS_TR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRACE, SYSZ_INS_TRACE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRACG, SYSZ_INS_TRACG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRAP2, SYSZ_INS_TRAP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRAP4, SYSZ_INS_TRAP4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRE, SYSZ_INS_TRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TROO, SYSZ_INS_TROO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TROOOpt, SYSZ_INS_TROO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TROT, SYSZ_INS_TROT, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TROTOpt, SYSZ_INS_TROT, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRT, SYSZ_INS_TRT, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTE, SYSZ_INS_TRTE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTEOpt, SYSZ_INS_TRTE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTO, SYSZ_INS_TRTO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTOOpt, SYSZ_INS_TRTO, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTR, SYSZ_INS_TRTR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTRE, SYSZ_INS_TRTRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTREOpt, SYSZ_INS_TRTRE, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTT, SYSZ_INS_TRTT, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TRTTOpt, SYSZ_INS_TRTT, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TS, SYSZ_INS_TS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_TSCH, SYSZ_INS_TSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_UNPK, SYSZ_INS_UNPK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_UNPKA, SYSZ_INS_UNPKA, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_UNPKU, SYSZ_INS_UNPKU, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_UPT, SYSZ_INS_UPT, +#ifndef CAPSTONE_DIET + { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_5, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_VA, SYSZ_INS_VA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAB, SYSZ_INS_VAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAC, SYSZ_INS_VAC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACC, SYSZ_INS_VACC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCB, SYSZ_INS_VACCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCC, SYSZ_INS_VACCC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCCQ, SYSZ_INS_VACCCQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCF, SYSZ_INS_VACCF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCG, SYSZ_INS_VACCG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCH, SYSZ_INS_VACCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACCQ, SYSZ_INS_VACCQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VACQ, SYSZ_INS_VACQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAF, SYSZ_INS_VAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAG, SYSZ_INS_VAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAH, SYSZ_INS_VAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAP, SYSZ_INS_VAP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAQ, SYSZ_INS_VAQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVG, SYSZ_INS_VAVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGB, SYSZ_INS_VAVGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGF, SYSZ_INS_VAVGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGG, SYSZ_INS_VAVGG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGH, SYSZ_INS_VAVGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGL, SYSZ_INS_VAVGL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGLB, SYSZ_INS_VAVGLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGLF, SYSZ_INS_VAVGLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGLG, SYSZ_INS_VAVGLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VAVGLH, SYSZ_INS_VAVGLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VBPERM, SYSZ_INS_VBPERM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCDG, SYSZ_INS_VCDG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCDGB, SYSZ_INS_VCDGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCDLG, SYSZ_INS_VCDLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCDLGB, SYSZ_INS_VCDLGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQ, SYSZ_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQB, SYSZ_INS_VCEQB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQBS, SYSZ_INS_VCEQBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQF, SYSZ_INS_VCEQF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQFS, SYSZ_INS_VCEQFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQG, SYSZ_INS_VCEQG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQGS, SYSZ_INS_VCEQGS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQH, SYSZ_INS_VCEQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCEQHS, SYSZ_INS_VCEQHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCGD, SYSZ_INS_VCGD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCGDB, SYSZ_INS_VCGDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCH, SYSZ_INS_VCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHB, SYSZ_INS_VCHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHBS, SYSZ_INS_VCHBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHF, SYSZ_INS_VCHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHFS, SYSZ_INS_VCHFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHG, SYSZ_INS_VCHG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHGS, SYSZ_INS_VCHGS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHH, SYSZ_INS_VCHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHHS, SYSZ_INS_VCHHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHL, SYSZ_INS_VCHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLB, SYSZ_INS_VCHLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLBS, SYSZ_INS_VCHLBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLF, SYSZ_INS_VCHLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLFS, SYSZ_INS_VCHLFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLG, SYSZ_INS_VCHLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLGS, SYSZ_INS_VCHLGS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLH, SYSZ_INS_VCHLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCHLHS, SYSZ_INS_VCHLHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCKSM, SYSZ_INS_VCKSM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLGD, SYSZ_INS_VCLGD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLGDB, SYSZ_INS_VCLGDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLZ, SYSZ_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLZB, SYSZ_INS_VCLZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLZF, SYSZ_INS_VCLZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLZG, SYSZ_INS_VCLZG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCLZH, SYSZ_INS_VCLZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCP, SYSZ_INS_VCP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCTZ, SYSZ_INS_VCTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCTZB, SYSZ_INS_VCTZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCTZF, SYSZ_INS_VCTZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCTZG, SYSZ_INS_VCTZG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCTZH, SYSZ_INS_VCTZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCVB, SYSZ_INS_VCVB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCVBG, SYSZ_INS_VCVBG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCVD, SYSZ_INS_VCVD, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VCVDG, SYSZ_INS_VCVDG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VDP, SYSZ_INS_VDP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VEC, SYSZ_INS_VEC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECB, SYSZ_INS_VECB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECF, SYSZ_INS_VECF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECG, SYSZ_INS_VECG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECH, SYSZ_INS_VECH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECL, SYSZ_INS_VECL, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECLB, SYSZ_INS_VECLB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECLF, SYSZ_INS_VECLF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECLG, SYSZ_INS_VECLG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VECLH, SYSZ_INS_VECLH, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERIM, SYSZ_INS_VERIM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERIMB, SYSZ_INS_VERIMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERIMF, SYSZ_INS_VERIMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERIMG, SYSZ_INS_VERIMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERIMH, SYSZ_INS_VERIMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLL, SYSZ_INS_VERLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLB, SYSZ_INS_VERLLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLF, SYSZ_INS_VERLLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLG, SYSZ_INS_VERLLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLH, SYSZ_INS_VERLLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLV, SYSZ_INS_VERLLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLVB, SYSZ_INS_VERLLVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLVF, SYSZ_INS_VERLLVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLVG, SYSZ_INS_VERLLVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VERLLVH, SYSZ_INS_VERLLVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESL, SYSZ_INS_VESL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLB, SYSZ_INS_VESLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLF, SYSZ_INS_VESLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLG, SYSZ_INS_VESLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLH, SYSZ_INS_VESLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLV, SYSZ_INS_VESLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLVB, SYSZ_INS_VESLVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLVF, SYSZ_INS_VESLVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLVG, SYSZ_INS_VESLVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESLVH, SYSZ_INS_VESLVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRA, SYSZ_INS_VESRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAB, SYSZ_INS_VESRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAF, SYSZ_INS_VESRAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAG, SYSZ_INS_VESRAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAH, SYSZ_INS_VESRAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAV, SYSZ_INS_VESRAV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAVB, SYSZ_INS_VESRAVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAVF, SYSZ_INS_VESRAVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAVG, SYSZ_INS_VESRAVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRAVH, SYSZ_INS_VESRAVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRL, SYSZ_INS_VESRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLB, SYSZ_INS_VESRLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLF, SYSZ_INS_VESRLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLG, SYSZ_INS_VESRLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLH, SYSZ_INS_VESRLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLV, SYSZ_INS_VESRLV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLVB, SYSZ_INS_VESRLVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLVF, SYSZ_INS_VESRLVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLVG, SYSZ_INS_VESRLVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VESRLVH, SYSZ_INS_VESRLVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFA, SYSZ_INS_VFA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFADB, SYSZ_INS_VFADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAE, SYSZ_INS_VFAE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEB, SYSZ_INS_VFAEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEBS, SYSZ_INS_VFAEBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEF, SYSZ_INS_VFAEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEFS, SYSZ_INS_VFAEFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEH, SYSZ_INS_VFAEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEHS, SYSZ_INS_VFAEHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZB, SYSZ_INS_VFAEZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZBS, SYSZ_INS_VFAEZBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZF, SYSZ_INS_VFAEZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZFS, SYSZ_INS_VFAEZFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZH, SYSZ_INS_VFAEZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFAEZHS, SYSZ_INS_VFAEZHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFASB, SYSZ_INS_VFASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCE, SYSZ_INS_VFCE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCEDB, SYSZ_INS_VFCEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCEDBS, SYSZ_INS_VFCEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCESB, SYSZ_INS_VFCESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCESBS, SYSZ_INS_VFCESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCH, SYSZ_INS_VFCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHDB, SYSZ_INS_VFCHDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHDBS, SYSZ_INS_VFCHDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHE, SYSZ_INS_VFCHE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHEDB, SYSZ_INS_VFCHEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHEDBS, SYSZ_INS_VFCHEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHESB, SYSZ_INS_VFCHESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHESBS, SYSZ_INS_VFCHESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHSB, SYSZ_INS_VFCHSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFCHSBS, SYSZ_INS_VFCHSBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFD, SYSZ_INS_VFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFDDB, SYSZ_INS_VFDDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFDSB, SYSZ_INS_VFDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEE, SYSZ_INS_VFEE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEB, SYSZ_INS_VFEEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEBS, SYSZ_INS_VFEEBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEF, SYSZ_INS_VFEEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEFS, SYSZ_INS_VFEEFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEH, SYSZ_INS_VFEEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEHS, SYSZ_INS_VFEEHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZB, SYSZ_INS_VFEEZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZBS, SYSZ_INS_VFEEZBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZF, SYSZ_INS_VFEEZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZFS, SYSZ_INS_VFEEZFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZH, SYSZ_INS_VFEEZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFEEZHS, SYSZ_INS_VFEEZHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENE, SYSZ_INS_VFENE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEB, SYSZ_INS_VFENEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEBS, SYSZ_INS_VFENEBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEF, SYSZ_INS_VFENEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEFS, SYSZ_INS_VFENEFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEH, SYSZ_INS_VFENEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEHS, SYSZ_INS_VFENEHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZB, SYSZ_INS_VFENEZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZBS, SYSZ_INS_VFENEZBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZF, SYSZ_INS_VFENEZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZFS, SYSZ_INS_VFENEZFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZH, SYSZ_INS_VFENEZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFENEZHS, SYSZ_INS_VFENEZHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFI, SYSZ_INS_VFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFIDB, SYSZ_INS_VFIDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFISB, SYSZ_INS_VFISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKEDB, SYSZ_INS_VFKEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKEDBS, SYSZ_INS_VFKEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKESB, SYSZ_INS_VFKESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKESBS, SYSZ_INS_VFKESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHDB, SYSZ_INS_VFKHDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHDBS, SYSZ_INS_VFKHDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHEDB, SYSZ_INS_VFKHEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHEDBS, SYSZ_INS_VFKHEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHESB, SYSZ_INS_VFKHESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHESBS, SYSZ_INS_VFKHESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHSB, SYSZ_INS_VFKHSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFKHSBS, SYSZ_INS_VFKHSBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLCDB, SYSZ_INS_VFLCDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLCSB, SYSZ_INS_VFLCSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLL, SYSZ_INS_VFLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLLS, SYSZ_INS_VFLLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLNDB, SYSZ_INS_VFLNDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLNSB, SYSZ_INS_VFLNSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLPDB, SYSZ_INS_VFLPDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLPSB, SYSZ_INS_VFLPSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLR, SYSZ_INS_VFLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFLRD, SYSZ_INS_VFLRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFM, SYSZ_INS_VFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMA, SYSZ_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMADB, SYSZ_INS_VFMADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMASB, SYSZ_INS_VFMASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMAX, SYSZ_INS_VFMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMAXDB, SYSZ_INS_VFMAXDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMAXSB, SYSZ_INS_VFMAXSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMDB, SYSZ_INS_VFMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMIN, SYSZ_INS_VFMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMINDB, SYSZ_INS_VFMINDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMINSB, SYSZ_INS_VFMINSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMS, SYSZ_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMSB, SYSZ_INS_VFMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMSDB, SYSZ_INS_VFMSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFMSSB, SYSZ_INS_VFMSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMA, SYSZ_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMADB, SYSZ_INS_VFNMADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMASB, SYSZ_INS_VFNMASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMS, SYSZ_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMSDB, SYSZ_INS_VFNMSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFNMSSB, SYSZ_INS_VFNMSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFPSO, SYSZ_INS_VFPSO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFPSODB, SYSZ_INS_VFPSODB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFPSOSB, SYSZ_INS_VFPSOSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFS, SYSZ_INS_VFS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFSDB, SYSZ_INS_VFSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFSQ, SYSZ_INS_VFSQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFSQDB, SYSZ_INS_VFSQDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFSQSB, SYSZ_INS_VFSQSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFSSB, SYSZ_INS_VFSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFTCI, SYSZ_INS_VFTCI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFTCIDB, SYSZ_INS_VFTCIDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VFTCISB, SYSZ_INS_VFTCISB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGBM, SYSZ_INS_VGBM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGEF, SYSZ_INS_VGEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGEG, SYSZ_INS_VGEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFM, SYSZ_INS_VGFM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMA, SYSZ_INS_VGFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMAB, SYSZ_INS_VGFMAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMAF, SYSZ_INS_VGFMAF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMAG, SYSZ_INS_VGFMAG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMAH, SYSZ_INS_VGFMAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMB, SYSZ_INS_VGFMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMF, SYSZ_INS_VGFMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMG, SYSZ_INS_VGFMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGFMH, SYSZ_INS_VGFMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGM, SYSZ_INS_VGM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGMB, SYSZ_INS_VGMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGMF, SYSZ_INS_VGMF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGMG, SYSZ_INS_VGMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VGMH, SYSZ_INS_VGMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTR, SYSZ_INS_VISTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRB, SYSZ_INS_VISTRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRBS, SYSZ_INS_VISTRBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRF, SYSZ_INS_VISTRF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRFS, SYSZ_INS_VISTRFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRH, SYSZ_INS_VISTRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VISTRHS, SYSZ_INS_VISTRHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VL, SYSZ_INS_VL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLBB, SYSZ_INS_VLBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLC, SYSZ_INS_VLC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLCB, SYSZ_INS_VLCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLCF, SYSZ_INS_VLCF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLCG, SYSZ_INS_VLCG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLCH, SYSZ_INS_VLCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLDE, SYSZ_INS_VLDE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLDEB, SYSZ_INS_VLDEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEB, SYSZ_INS_VLEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLED, SYSZ_INS_VLED, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEDB, SYSZ_INS_VLEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEF, SYSZ_INS_VLEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEG, SYSZ_INS_VLEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEH, SYSZ_INS_VLEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEIB, SYSZ_INS_VLEIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEIF, SYSZ_INS_VLEIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEIG, SYSZ_INS_VLEIG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLEIH, SYSZ_INS_VLEIH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLGV, SYSZ_INS_VLGV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLGVB, SYSZ_INS_VLGVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLGVF, SYSZ_INS_VLGVF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLGVG, SYSZ_INS_VLGVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLGVH, SYSZ_INS_VLGVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLIP, SYSZ_INS_VLIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLL, SYSZ_INS_VLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZ, SYSZ_INS_VLLEZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZB, SYSZ_INS_VLLEZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZF, SYSZ_INS_VLLEZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZG, SYSZ_INS_VLLEZG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZH, SYSZ_INS_VLLEZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLLEZLF, SYSZ_INS_VLLEZLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLM, SYSZ_INS_VLM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLP, SYSZ_INS_VLP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLPB, SYSZ_INS_VLPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLPF, SYSZ_INS_VLPF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLPG, SYSZ_INS_VLPG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLPH, SYSZ_INS_VLPH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLR, SYSZ_INS_VLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLREP, SYSZ_INS_VLREP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLREPB, SYSZ_INS_VLREPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLREPF, SYSZ_INS_VLREPF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLREPG, SYSZ_INS_VLREPG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLREPH, SYSZ_INS_VLREPH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLRL, SYSZ_INS_VLRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLRLR, SYSZ_INS_VLRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVG, SYSZ_INS_VLVG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVGB, SYSZ_INS_VLVGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVGF, SYSZ_INS_VLVGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVGG, SYSZ_INS_VLVGG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVGH, SYSZ_INS_VLVGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VLVGP, SYSZ_INS_VLVGP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAE, SYSZ_INS_VMAE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAEB, SYSZ_INS_VMAEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAEF, SYSZ_INS_VMAEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAEH, SYSZ_INS_VMAEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAH, SYSZ_INS_VMAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAHB, SYSZ_INS_VMAHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAHF, SYSZ_INS_VMAHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAHH, SYSZ_INS_VMAHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAL, SYSZ_INS_VMAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALB, SYSZ_INS_VMALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALE, SYSZ_INS_VMALE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALEB, SYSZ_INS_VMALEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALEF, SYSZ_INS_VMALEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALEH, SYSZ_INS_VMALEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALF, SYSZ_INS_VMALF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALH, SYSZ_INS_VMALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALHB, SYSZ_INS_VMALHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALHF, SYSZ_INS_VMALHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALHH, SYSZ_INS_VMALHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALHW, SYSZ_INS_VMALHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALO, SYSZ_INS_VMALO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALOB, SYSZ_INS_VMALOB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALOF, SYSZ_INS_VMALOF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMALOH, SYSZ_INS_VMALOH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAO, SYSZ_INS_VMAO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAOB, SYSZ_INS_VMAOB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAOF, SYSZ_INS_VMAOF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMAOH, SYSZ_INS_VMAOH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VME, SYSZ_INS_VME, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMEB, SYSZ_INS_VMEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMEF, SYSZ_INS_VMEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMEH, SYSZ_INS_VMEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMH, SYSZ_INS_VMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMHB, SYSZ_INS_VMHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMHF, SYSZ_INS_VMHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMHH, SYSZ_INS_VMHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VML, SYSZ_INS_VML, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLB, SYSZ_INS_VMLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLE, SYSZ_INS_VMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLEB, SYSZ_INS_VMLEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLEF, SYSZ_INS_VMLEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLEH, SYSZ_INS_VMLEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLF, SYSZ_INS_VMLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLH, SYSZ_INS_VMLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLHB, SYSZ_INS_VMLHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLHF, SYSZ_INS_VMLHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLHH, SYSZ_INS_VMLHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLHW, SYSZ_INS_VMLHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLO, SYSZ_INS_VMLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLOB, SYSZ_INS_VMLOB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLOF, SYSZ_INS_VMLOF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMLOH, SYSZ_INS_VMLOH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMN, SYSZ_INS_VMN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNB, SYSZ_INS_VMNB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNF, SYSZ_INS_VMNF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNG, SYSZ_INS_VMNG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNH, SYSZ_INS_VMNH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNL, SYSZ_INS_VMNL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNLB, SYSZ_INS_VMNLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNLF, SYSZ_INS_VMNLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNLG, SYSZ_INS_VMNLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMNLH, SYSZ_INS_VMNLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMO, SYSZ_INS_VMO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMOB, SYSZ_INS_VMOB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMOF, SYSZ_INS_VMOF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMOH, SYSZ_INS_VMOH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMP, SYSZ_INS_VMP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRH, SYSZ_INS_VMRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRHB, SYSZ_INS_VMRHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRHF, SYSZ_INS_VMRHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRHG, SYSZ_INS_VMRHG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRHH, SYSZ_INS_VMRHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRL, SYSZ_INS_VMRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRLB, SYSZ_INS_VMRLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRLF, SYSZ_INS_VMRLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRLG, SYSZ_INS_VMRLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMRLH, SYSZ_INS_VMRLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMSL, SYSZ_INS_VMSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMSLG, SYSZ_INS_VMSLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMSP, SYSZ_INS_VMSP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMX, SYSZ_INS_VMX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXB, SYSZ_INS_VMXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXF, SYSZ_INS_VMXF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXG, SYSZ_INS_VMXG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXH, SYSZ_INS_VMXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXL, SYSZ_INS_VMXL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXLB, SYSZ_INS_VMXLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXLF, SYSZ_INS_VMXLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXLG, SYSZ_INS_VMXLG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VMXLH, SYSZ_INS_VMXLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VN, SYSZ_INS_VN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VNC, SYSZ_INS_VNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VNN, SYSZ_INS_VNN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VNO, SYSZ_INS_VNO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VNX, SYSZ_INS_VNX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VO, SYSZ_INS_VO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VOC, SYSZ_INS_VOC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VONE, SYSZ_INS_VONE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPDI, SYSZ_INS_VPDI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPERM, SYSZ_INS_VPERM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPK, SYSZ_INS_VPK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKF, SYSZ_INS_VPKF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKG, SYSZ_INS_VPKG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKH, SYSZ_INS_VPKH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLS, SYSZ_INS_VPKLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSF, SYSZ_INS_VPKLSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSFS, SYSZ_INS_VPKLSFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSG, SYSZ_INS_VPKLSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSGS, SYSZ_INS_VPKLSGS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSH, SYSZ_INS_VPKLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKLSHS, SYSZ_INS_VPKLSHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKS, SYSZ_INS_VPKS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSF, SYSZ_INS_VPKSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSFS, SYSZ_INS_VPKSFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSG, SYSZ_INS_VPKSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSGS, SYSZ_INS_VPKSGS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSH, SYSZ_INS_VPKSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKSHS, SYSZ_INS_VPKSHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPKZ, SYSZ_INS_VPKZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPOPCT, SYSZ_INS_VPOPCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPOPCTB, SYSZ_INS_VPOPCTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPOPCTF, SYSZ_INS_VPOPCTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPOPCTG, SYSZ_INS_VPOPCTG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPOPCTH, SYSZ_INS_VPOPCTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VPSOP, SYSZ_INS_VPSOP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREP, SYSZ_INS_VREP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPB, SYSZ_INS_VREPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPF, SYSZ_INS_VREPF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPG, SYSZ_INS_VREPG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPH, SYSZ_INS_VREPH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPI, SYSZ_INS_VREPI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPIB, SYSZ_INS_VREPIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPIF, SYSZ_INS_VREPIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPIG, SYSZ_INS_VREPIG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VREPIH, SYSZ_INS_VREPIH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VRP, SYSZ_INS_VRP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VS, SYSZ_INS_VS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSB, SYSZ_INS_VSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSBCBI, SYSZ_INS_VSBCBI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSBCBIQ, SYSZ_INS_VSBCBIQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSBI, SYSZ_INS_VSBI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSBIQ, SYSZ_INS_VSBIQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBI, SYSZ_INS_VSCBI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBIB, SYSZ_INS_VSCBIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBIF, SYSZ_INS_VSCBIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBIG, SYSZ_INS_VSCBIG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBIH, SYSZ_INS_VSCBIH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCBIQ, SYSZ_INS_VSCBIQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCEF, SYSZ_INS_VSCEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSCEG, SYSZ_INS_VSCEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSDP, SYSZ_INS_VSDP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSEG, SYSZ_INS_VSEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSEGB, SYSZ_INS_VSEGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSEGF, SYSZ_INS_VSEGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSEGH, SYSZ_INS_VSEGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSEL, SYSZ_INS_VSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSF, SYSZ_INS_VSF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSG, SYSZ_INS_VSG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSH, SYSZ_INS_VSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSL, SYSZ_INS_VSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSLB, SYSZ_INS_VSLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSLDB, SYSZ_INS_VSLDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSP, SYSZ_INS_VSP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSQ, SYSZ_INS_VSQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSRA, SYSZ_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSRAB, SYSZ_INS_VSRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSRL, SYSZ_INS_VSRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSRLB, SYSZ_INS_VSRLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSRP, SYSZ_INS_VSRP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VST, SYSZ_INS_VST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTEB, SYSZ_INS_VSTEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTEF, SYSZ_INS_VSTEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTEG, SYSZ_INS_VSTEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTEH, SYSZ_INS_VSTEH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTL, SYSZ_INS_VSTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTM, SYSZ_INS_VSTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRC, SYSZ_INS_VSTRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCB, SYSZ_INS_VSTRCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCBS, SYSZ_INS_VSTRCBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCF, SYSZ_INS_VSTRCF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCFS, SYSZ_INS_VSTRCFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCH, SYSZ_INS_VSTRCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCHS, SYSZ_INS_VSTRCHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZB, SYSZ_INS_VSTRCZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZBS, SYSZ_INS_VSTRCZBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZF, SYSZ_INS_VSTRCZF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZFS, SYSZ_INS_VSTRCZFS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZH, SYSZ_INS_VSTRCZH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRCZHS, SYSZ_INS_VSTRCZHS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRL, SYSZ_INS_VSTRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSTRLR, SYSZ_INS_VSTRLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUM, SYSZ_INS_VSUM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMB, SYSZ_INS_VSUMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMG, SYSZ_INS_VSUMG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMGF, SYSZ_INS_VSUMGF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMGH, SYSZ_INS_VSUMGH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMH, SYSZ_INS_VSUMH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMQ, SYSZ_INS_VSUMQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMQF, SYSZ_INS_VSUMQF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VSUMQG, SYSZ_INS_VSUMQG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VTM, SYSZ_INS_VTM, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VTP, SYSZ_INS_VTP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPH, SYSZ_INS_VUPH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPHB, SYSZ_INS_VUPHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPHF, SYSZ_INS_VUPHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPHH, SYSZ_INS_VUPHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPKZ, SYSZ_INS_VUPKZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPL, SYSZ_INS_VUPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLB, SYSZ_INS_VUPLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLF, SYSZ_INS_VUPLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLH, SYSZ_INS_VUPLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLHB, SYSZ_INS_VUPLHB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLHF, SYSZ_INS_VUPLHF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLHH, SYSZ_INS_VUPLHH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLHW, SYSZ_INS_VUPLHW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLL, SYSZ_INS_VUPLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLLB, SYSZ_INS_VUPLLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLLF, SYSZ_INS_VUPLLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VUPLLH, SYSZ_INS_VUPLLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VX, SYSZ_INS_VX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_VZERO, SYSZ_INS_VZERO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WCDGB, SYSZ_INS_WCDGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WCDLGB, SYSZ_INS_WCDLGB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WCGDB, SYSZ_INS_WCGDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WCLGDB, SYSZ_INS_WCLGDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFADB, SYSZ_INS_WFADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFASB, SYSZ_INS_WFASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFAXB, SYSZ_INS_WFAXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFC, SYSZ_INS_WFC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCDB, SYSZ_INS_WFCDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCEDB, SYSZ_INS_WFCEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCEDBS, SYSZ_INS_WFCEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCESB, SYSZ_INS_WFCESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCESBS, SYSZ_INS_WFCESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCEXB, SYSZ_INS_WFCEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCEXBS, SYSZ_INS_WFCEXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHDB, SYSZ_INS_WFCHDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHDBS, SYSZ_INS_WFCHDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHEDB, SYSZ_INS_WFCHEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHEDBS, SYSZ_INS_WFCHEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHESB, SYSZ_INS_WFCHESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHESBS, SYSZ_INS_WFCHESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHEXB, SYSZ_INS_WFCHEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHEXBS, SYSZ_INS_WFCHEXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHSB, SYSZ_INS_WFCHSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHSBS, SYSZ_INS_WFCHSBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHXB, SYSZ_INS_WFCHXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCHXBS, SYSZ_INS_WFCHXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCSB, SYSZ_INS_WFCSB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFCXB, SYSZ_INS_WFCXB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFDDB, SYSZ_INS_WFDDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFDSB, SYSZ_INS_WFDSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFDXB, SYSZ_INS_WFDXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFIDB, SYSZ_INS_WFIDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFISB, SYSZ_INS_WFISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFIXB, SYSZ_INS_WFIXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFK, SYSZ_INS_WFK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKDB, SYSZ_INS_WFKDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKEDB, SYSZ_INS_WFKEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKEDBS, SYSZ_INS_WFKEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKESB, SYSZ_INS_WFKESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKESBS, SYSZ_INS_WFKESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKEXB, SYSZ_INS_WFKEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKEXBS, SYSZ_INS_WFKEXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHDB, SYSZ_INS_WFKHDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHDBS, SYSZ_INS_WFKHDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHEDB, SYSZ_INS_WFKHEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHEDBS, SYSZ_INS_WFKHEDBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHESB, SYSZ_INS_WFKHESB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHESBS, SYSZ_INS_WFKHESBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHEXB, SYSZ_INS_WFKHEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHEXBS, SYSZ_INS_WFKHEXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHSB, SYSZ_INS_WFKHSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHSBS, SYSZ_INS_WFKHSBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHXB, SYSZ_INS_WFKHXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKHXBS, SYSZ_INS_WFKHXBS, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKSB, SYSZ_INS_WFKSB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFKXB, SYSZ_INS_WFKXB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLCDB, SYSZ_INS_WFLCDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLCSB, SYSZ_INS_WFLCSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLCXB, SYSZ_INS_WFLCXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLLD, SYSZ_INS_WFLLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLLS, SYSZ_INS_WFLLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLNDB, SYSZ_INS_WFLNDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLNSB, SYSZ_INS_WFLNSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLNXB, SYSZ_INS_WFLNXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLPDB, SYSZ_INS_WFLPDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLPSB, SYSZ_INS_WFLPSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLPXB, SYSZ_INS_WFLPXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLRD, SYSZ_INS_WFLRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFLRX, SYSZ_INS_WFLRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMADB, SYSZ_INS_WFMADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMASB, SYSZ_INS_WFMASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMAXB, SYSZ_INS_WFMAXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMAXDB, SYSZ_INS_WFMAXDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMAXSB, SYSZ_INS_WFMAXSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMAXXB, SYSZ_INS_WFMAXXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMDB, SYSZ_INS_WFMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMINDB, SYSZ_INS_WFMINDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMINSB, SYSZ_INS_WFMINSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMINXB, SYSZ_INS_WFMINXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMSB, SYSZ_INS_WFMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMSDB, SYSZ_INS_WFMSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMSSB, SYSZ_INS_WFMSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMSXB, SYSZ_INS_WFMSXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFMXB, SYSZ_INS_WFMXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMADB, SYSZ_INS_WFNMADB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMASB, SYSZ_INS_WFNMASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMAXB, SYSZ_INS_WFNMAXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMSDB, SYSZ_INS_WFNMSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMSSB, SYSZ_INS_WFNMSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFNMSXB, SYSZ_INS_WFNMSXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFPSODB, SYSZ_INS_WFPSODB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFPSOSB, SYSZ_INS_WFPSOSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFPSOXB, SYSZ_INS_WFPSOXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSDB, SYSZ_INS_WFSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSQDB, SYSZ_INS_WFSQDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSQSB, SYSZ_INS_WFSQSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSQXB, SYSZ_INS_WFSQXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSSB, SYSZ_INS_WFSSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFSXB, SYSZ_INS_WFSXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFTCIDB, SYSZ_INS_WFTCIDB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFTCISB, SYSZ_INS_WFTCISB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WFTCIXB, SYSZ_INS_WFTCIXB, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WLDEB, SYSZ_INS_WLDEB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_WLEDB, SYSZ_INS_WLEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 +#endif +}, +{ + SystemZ_X, SYSZ_INS_X, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XC, SYSZ_INS_XC, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XG, SYSZ_INS_XG, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XGR, SYSZ_INS_XGR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XGRK, SYSZ_INS_XGRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_XI, SYSZ_INS_XI, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XIHF, SYSZ_INS_XIHF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XILF, SYSZ_INS_XILF, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XIY, SYSZ_INS_XIY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XR, SYSZ_INS_XR, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XRK, SYSZ_INS_XRK, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 +#endif +}, +{ + SystemZ_XSCH, SYSZ_INS_XSCH, +#ifndef CAPSTONE_DIET + { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_XY, SYSZ_INS_XY, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, +{ + SystemZ_ZAP, SYSZ_INS_ZAP, +#ifndef CAPSTONE_DIET + { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.c b/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.c new file mode 100644 index 0000000..bc51068 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.c @@ -0,0 +1,44 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_SYSZ + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "SystemZDisassembler.h" +#include "SystemZInstPrinter.h" +#include "SystemZMapping.h" +#include "SystemZModule.h" + +cs_err SystemZ_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + SystemZ_init(mri); + ud->printer = SystemZ_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = SystemZ_getInstruction; + ud->post_printer = SystemZ_post_printer; + + ud->reg_name = SystemZ_reg_name; + ud->insn_id = SystemZ_get_insn_id; + ud->insn_name = SystemZ_insn_name; + ud->group_name = SystemZ_group_name; + + return CS_ERR_OK; +} + +cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_SYNTAX) + handle->syntax = (int) value; + + // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot + // test for CS_MODE_LITTLE_ENDIAN because it is 0 + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.h b/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.h new file mode 100644 index 0000000..ad403ba --- /dev/null +++ b/white_patch_detect/capstone-master/arch/SystemZ/SystemZModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_SYSTEMZ_MODULE_H +#define CS_SYSTEMZ_MODULE_H + +#include "../../utils.h" + +cs_err SystemZ_global_init(cs_struct *ud); +cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.c b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.c new file mode 100644 index 0000000..2829187 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.c @@ -0,0 +1,628 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifdef CAPSTONE_HAS_TMS320C64X + +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "TMS320C64xDisassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + +static uint64_t getFeatureBits(int mode); + +static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +#include "TMS320C64xGenDisassemblerTables.inc" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "TMS320C64xGenRegisterInfo.inc" + +static const unsigned GPRegsDecoderTable[] = { + TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, + TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, + TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, + TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, + TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, + TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, + TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, + TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31 +}; + +static const unsigned ControlRegsDecoderTable[] = { + TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_ISR, TMS320C64x_ICR, + TMS320C64x_IER, TMS320C64x_ISTP, TMS320C64x_IRP, TMS320C64x_NRP, + ~0U, ~0U, TMS320C64x_TSCL, TMS320C64x_TSCH, + ~0U, TMS320C64x_ILC, TMS320C64x_RILC, TMS320C64x_REP, + TMS320C64x_PCE1, TMS320C64x_DNUM, ~0U, ~0U, + ~0U, TMS320C64x_SSR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, + TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR, TMS320C64x_ITSR, + TMS320C64x_NTSR, TMS320C64x_ECR, ~0U, TMS320C64x_IERR +}; + +static uint64_t getFeatureBits(int mode) +{ + // support everything + return (uint64_t)-1; +} + +static unsigned getReg(const unsigned *RegTable, unsigned RegNo) +{ + if(RegNo > 31) + return ~0U; + return RegTable[RegNo]; +} + +static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) +{ + unsigned Reg; + + if(RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(GPRegsDecoderTable, RegNo); + if(Reg == ~0U) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) +{ + unsigned Reg; + + if(RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(ControlRegsDecoderTable, RegNo); + if(Reg == ~0U) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 5 bit value */ + if(imm & (1 << (5 - 1))) + imm |= ~((1 << 5) - 1); + + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 16 bit value */ + if(imm & (1 << (16 - 1))) + imm |= ~((1 << 16) - 1); + + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 7 bit value */ + if(imm & (1 << (7 - 1))) + imm |= ~((1 << 7) - 1); + + /* Address is relative to the address of the first instruction in the fetch packet */ + MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 10 bit value */ + if(imm & (1 << (10 - 1))) + imm |= ~((1 << 10) - 1); + + /* Address is relative to the address of the first instruction in the fetch packet */ + MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 12 bit value */ + if(imm & (1 << (12 - 1))) + imm |= ~((1 << 12) - 1); + + /* Address is relative to the address of the first instruction in the fetch packet */ + MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + int32_t imm; + + imm = Val; + /* Sign extend 21 bit value */ + if(imm & (1 << (21 - 1))) + imm |= ~((1 << 21) - 1); + + /* Address is relative to the address of the first instruction in the fetch packet */ + MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder); +} + +static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + uint8_t scaled, base, offset, mode, unit; + unsigned basereg, offsetreg; + + scaled = (Val >> 15) & 1; + base = (Val >> 10) & 0x1f; + offset = (Val >> 5) & 0x1f; + mode = (Val >> 1) & 0xf; + unit = Val & 1; + + if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31)) + base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((base >= TMS320C64X_REG_B0) && (base <= TMS320C64X_REG_B31)) + base = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + basereg = getReg(GPRegsDecoderTable, base); + if (basereg == ~0U) + return MCDisassembler_Fail; + + switch(mode) { + case 0: + case 1: + case 8: + case 9: + case 10: + case 11: + MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit); + break; + case 4: + case 5: + case 12: + case 13: + case 14: + case 15: + if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31)) + offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31)) + offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + offsetreg = getReg(GPRegsDecoderTable, offset); + if (offsetreg == ~0U) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit); + break; + default: + return MCDisassembler_Fail; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + uint16_t offset; + unsigned basereg; + + if(Val & 1) + basereg = TMS320C64X_REG_B15; + else + basereg = TMS320C64X_REG_B14; + + offset = (Val >> 1) & 0x7fff; + MCOperand_CreateImm0(Inst, (offset << 7) | basereg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) +{ + unsigned Reg; + + if(RegNo > 31) + return MCDisassembler_Fail; + + Reg = getReg(GPRegsDecoderTable, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) +{ + unsigned Reg; + + if(RegNo > 15) + return MCDisassembler_Fail; + + Reg = getReg(GPRegsDecoderTable, RegNo << 1); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + case 7: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0; + break; + case 2: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1; + break; + case 3: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2; + break; + case 4: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1; + break; + case 5: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2; + break; + case 6: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0; + break; + default: + Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.condition.zero = 0; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.condition.zero = 1; + break; + default: + Inst->flat_insn->detail->tms320c64x.condition.zero = 0; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + MCOperand *op; + int i; + + /* This is pretty messy, probably we should find a better way */ + if(Val == 1) { + for(i = 0; i < Inst->size; i++) { + op = &Inst->Operands[i]; + if(op->Kind == kRegister) { + if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + } + } + } + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.funit.side = 1; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.funit.side = 2; + break; + default: + Inst->flat_insn->detail->tms320c64x.funit.side = 0; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.parallel = 0; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.parallel = 1; + break; + default: + Inst->flat_insn->detail->tms320c64x.parallel = -1; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + MCOperand *op; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; + op = &Inst->Operands[0]; + if(op->Kind == kRegister) { + if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + } + break; + default: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + MCOperand *op; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; + op = &Inst->Operands[1]; + if(op->Kind == kRegister) { + if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + } + break; + default: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + +static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + DecodeStatus ret = MCDisassembler_Success; + MCOperand *op; + + if(!Inst->flat_insn->detail) + return MCDisassembler_Success; + + switch(Val) { + case 0: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; + break; + case 1: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2; + op = &Inst->Operands[2]; + if(op->Kind == kRegister) { + if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); + else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) + op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); + } + break; + default: + Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; + ret = MCDisassembler_Fail; + break; + } + + return ret; +} + + +static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) +{ + MCOperand_CreateImm0(Inst, Val + 1); + + return MCDisassembler_Success; +} + +#define GET_INSTRINFO_ENUM +#include "TMS320C64xGenInstrInfo.inc" + +bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, void *info) +{ + uint32_t insn; + DecodeStatus result; + + if(code_len < 4) { + *size = 0; + return MCDisassembler_Fail; + } + + if(MI->flat_insn->detail) + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x)); + + insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); + result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0); + + if(result == MCDisassembler_Success) { + *size = 4; + return true; + } + + MCInst_clear(MI); + *size = 0; + return false; +} + +void TMS320C64x_init(MCRegisterInfo *MRI) +{ + MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, + 0, 0, + TMS320C64xMCRegisterClasses, 7, + 0, 0, + TMS320C64xRegDiffLists, + 0, + TMS320C64xSubRegIdxLists, 1, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.h b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.h new file mode 100644 index 0000000..d49d43b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xDisassembler.h @@ -0,0 +1,19 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifndef CS_TMS320C64XDISASSEMBLER_H +#define CS_TMS320C64XDISASSEMBLER_H + +#include + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void TMS320C64x_init(MCRegisterInfo *MRI); + +bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc new file mode 100644 index 0000000..70dd72a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc @@ -0,0 +1,684 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#include + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 882U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 875U, // BUNDLE + 904U, // LIFETIME_START + 862U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 1126U, // ABS2_l2_rr + 10847U, // ABS_l1_pp + 1631U, // ABS_l1_rr + 85006U, // ADD2_d2_rrr + 85006U, // ADD2_l1_rrr_x2 + 85006U, // ADD2_s1_rrr + 85171U, // ADD4_l1_rrr_x2 + 91479U, // ADDAB_d1_rir + 91479U, // ADDAB_d1_rrr + 91541U, // ADDAD_d1_rir + 91541U, // ADDAD_d1_rrr + 91577U, // ADDAH_d1_rir + 91577U, // ADDAH_d1_rrr + 91937U, // ADDAW_d1_rir + 91937U, // ADDAW_d1_rrr + 132488U, // ADDKPC_s3_iir + 1518U, // ADDK_s2_ir + 233140U, // ADDU_l1_rpp + 216756U, // ADDU_l1_rrp_x2 + 91555U, // ADD_d1_rir + 91555U, // ADD_d1_rrr + 91555U, // ADD_d2_rir + 85411U, // ADD_d2_rrr + 232867U, // ADD_l1_ipp + 85411U, // ADD_l1_irr + 232867U, // ADD_l1_rpp + 216483U, // ADD_l1_rrp_x2 + 85411U, // ADD_l1_rrr_x2 + 85411U, // ADD_s1_irr + 85411U, // ADD_s1_rrr + 85542U, // ANDN_d2_rrr + 85542U, // ANDN_l1_rrr_x2 + 85542U, // ANDN_s4_rrr + 85416U, // AND_d2_rir + 85416U, // AND_d2_rrr + 85416U, // AND_l1_irr + 85416U, // AND_l1_rrr_x2 + 85416U, // AND_s1_irr + 85416U, // AND_s1_rrr + 85019U, // AVG2_m1_rrr + 85232U, // AVGU4_m1_rrr + 1410U, // BDEC_s8_ir + 1196U, // BITC4_m2_rr + 307756U, // BNOP_s10_ri + 307756U, // BNOP_s9_ii + 1654U, // BPOS_s8_ir + 53588U, // B_s5_i + 53588U, // B_s6_r + 892U, // B_s7_irp + 898U, // B_s7_nrp + 353870U, // CLR_s15_riir + 91726U, // CLR_s1_rrr + 85080U, // CMPEQ2_s1_rrr + 85207U, // CMPEQ4_s1_rrr + 101938U, // CMPEQ_l1_ipr + 85554U, // CMPEQ_l1_irr + 101938U, // CMPEQ_l1_rpr + 85554U, // CMPEQ_l1_rrr_x2 + 85109U, // CMPGT2_s1_rrr + 85298U, // CMPGTU4_s1_rrr + 102037U, // CMPGT_l1_ipr + 85653U, // CMPGT_l1_irr + 102037U, // CMPGT_l1_rpr + 85653U, // CMPGT_l1_rrr_x2 + 102150U, // CMPLTU_l1_ipr + 85766U, // CMPLTU_l1_irr + 102150U, // CMPLTU_l1_rpr + 85766U, // CMPLTU_l1_rrr_x2 + 102044U, // CMPLT_l1_ipr + 85660U, // CMPLT_l1_irr + 102044U, // CMPLT_l1_rpr + 85660U, // CMPLT_l1_rrr_x2 + 1529U, // DEAL_m2_rr + 216145U, // DOTP2_m1_rrp + 85073U, // DOTP2_m1_rrr + 85065U, // DOTPN2_m1_rrr + 85124U, // DOTPNRSU2_m1_rrr + 85135U, // DOTPRSU2_m1_rrr + 85281U, // DOTPSU4_m1_rrr + 85273U, // DOTPU4_m1_rrr + 354062U, // EXTU_s15_riir + 91918U, // EXTU_s1_rrr + 353955U, // EXT_s15_riir + 91811U, // EXT_s1_rrr + 102142U, // GMPGTU_l1_ipr + 85758U, // GMPGTU_l1_irr + 102142U, // GMPGTU_l1_rpr + 85758U, // GMPGTU_l1_rrr_x2 + 85321U, // GMPY4_m1_rrr + 5800U, // LDBU_d5_mr + 6824U, // LDBU_d6_mr + 5470U, // LDB_d5_mr + 6494U, // LDB_d6_mr + 14120U, // LDDW_d7_mp + 5818U, // LDHU_d5_mr + 6842U, // LDHU_d6_mr + 5568U, // LDH_d5_mr + 6592U, // LDH_d6_mr + 14131U, // LDNDW_d8_mp + 5959U, // LDNW_d5_mr + 5934U, // LDW_d5_mr + 6958U, // LDW_d6_mr + 85404U, // LMBD_l1_irr + 85404U, // LMBD_l1_rrr_x2 + 85145U, // MAX2_l1_rrr_x2 + 85307U, // MAXU4_l1_rrr_x2 + 85059U, // MIN2_l1_rrr_x2 + 85266U, // MINU4_l1_rrr_x2 + 216224U, // MPY2_m1_rrp + 85566U, // MPYHIR_m1_rrr + 216544U, // MPYHI_m1_rrp + 85720U, // MPYHLU_m4_rrr + 85516U, // MPYHL_m4_rrr + 85728U, // MPYHSLU_m4_rrr + 85743U, // MPYHSU_m4_rrr + 85613U, // MPYHULS_m4_rrr + 85628U, // MPYHUS_m4_rrr + 85713U, // MPYHU_m4_rrr + 85466U, // MPYH_m4_rrr + 85696U, // MPYLHU_m4_rrr + 85453U, // MPYLH_m4_rrr + 85574U, // MPYLIR_m1_rrr + 216551U, // MPYLI_m1_rrp + 85704U, // MPYLSHU_m4_rrr + 85604U, // MPYLUHS_m4_rrr + 216362U, // MPYSU4_m1_rrp + 85751U, // MPYSU_m4_irr + 85751U, // MPYSU_m4_rrr + 216386U, // MPYU4_m1_rrp + 85636U, // MPYUS_m4_rrr + 85780U, // MPYU_m4_rrr + 85849U, // MPY_m4_irr + 85849U, // MPY_m4_rrr + 1424U, // MVC_s1_rr + 1424U, // MVC_s1_rr2 + 1453U, // MVD_m2_rr + 1477U, // MVKLH_s12_ir + 1524U, // MVKL_s12_ir + 1524U, // MVK_d1_rr + 1524U, // MVK_l2_ir + 53249U, // NOP_n + 2592U, // NORM_l1_pr + 1568U, // NORM_l1_rr + 85588U, // OR_d2_rir + 85588U, // OR_d2_rrr + 85588U, // OR_l1_irr + 85588U, // OR_l1_rrr_x2 + 85588U, // OR_s1_irr + 85588U, // OR_s1_rrr + 85043U, // PACK2_l1_rrr_x2 + 85043U, // PACK2_s4_rrr + 85025U, // PACKH2_l1_rrr_x2 + 85025U, // PACKH2_s1_rrr + 85184U, // PACKH4_l1_rrr_x2 + 85050U, // PACKHL2_l1_rrr_x2 + 85050U, // PACKHL2_s1_rrr + 85192U, // PACKL4_l1_rrr_x2 + 85033U, // PACKLH2_l1_rrr_x2 + 85033U, // PACKLH2_s1_rrr + 91667U, // ROTL_m1_rir + 91667U, // ROTL_m1_rrr + 85005U, // SADD2_s4_rrr + 85224U, // SADDU4_s4_rrr + 85100U, // SADDUS2_s4_rrr + 232866U, // SADD_l1_ipp + 85410U, // SADD_l1_irr + 232866U, // SADD_l1_rpp + 85410U, // SADD_l1_rrr_x2 + 85410U, // SADD_s1_rrr + 2699U, // SAT_l1_pr + 353936U, // SET_s15_riir + 91792U, // SET_s1_rrr + 1535U, // SHFL_m2_rr + 85347U, // SHLMB_l1_rrr_x2 + 85347U, // SHLMB_s4_rrr + 223750U, // SHL_s1_pip + 223750U, // SHL_s1_prp + 222726U, // SHL_s1_rip + 91654U, // SHL_s1_rir + 222726U, // SHL_s1_rrp + 91654U, // SHL_s1_rrr + 91232U, // SHR2_s1_rir + 91232U, // SHR2_s4_rrr + 85354U, // SHRMB_l1_rrr_x2 + 85354U, // SHRMB_s4_rrr + 91261U, // SHRU2_s1_rir + 91261U, // SHRU2_s4_rrr + 223977U, // SHRU_s1_pip + 223977U, // SHRU_s1_prp + 91881U, // SHRU_s1_rir + 91881U, // SHRU_s1_rrr + 223801U, // SHR_s1_pip + 223801U, // SHR_s1_prp + 91705U, // SHR_s1_rir + 91705U, // SHR_s1_rrr + 216223U, // SMPY2_m1_rrp + 85515U, // SMPYHL_m4_rrr + 85465U, // SMPYH_m4_rrr + 85452U, // SMPYLH_m4_rrr + 85848U, // SMPY_m4_rrr + 85042U, // SPACK2_s4_rrr + 85248U, // SPACKU4_s4_rrr + 91653U, // SSHL_s1_rir + 91653U, // SSHL_s1_rrr + 85529U, // SSHVL_m1_rrr + 85592U, // SSHVR_m1_rrr + 232822U, // SSUB_l1_ipp + 85366U, // SSUB_l1_irr + 85366U, // SSUB_l1_rrr_x1 + 85366U, // SSUB_l1_rrr_x2 + 438641U, // STB_d5_rm + 504177U, // STB_d6_rm + 8001U, // STDW_d7_pm + 438740U, // STH_d5_rm + 504276U, // STH_d6_rm + 7994U, // STNDW_d8_pm + 439117U, // STNW_d5_rm + 439123U, // STW_d5_rm + 504659U, // STW_d6_rm + 84999U, // SUB2_d2_rrr + 84999U, // SUB2_l1_rrr_x2 + 84999U, // SUB2_s1_rrr + 85158U, // SUB4_l1_rrr_x2 + 85215U, // SUBABS4_l1_rrr_x2 + 91472U, // SUBAB_d1_rir + 91472U, // SUBAB_d1_rrr + 91472U, // SUBAH_d1_rir + 91570U, // SUBAH_d1_rrr + 91472U, // SUBAW_d1_rir + 91930U, // SUBAW_d1_rrr + 85372U, // SUBC_l1_rrr_x2 + 216750U, // SUBU_l1_rrp_x1 + 216750U, // SUBU_l1_rrp_x2 + 91511U, // SUB_d1_rir + 91511U, // SUB_d1_rrr + 85367U, // SUB_d2_rrr + 232823U, // SUB_l1_ipp + 85367U, // SUB_l1_irr + 216439U, // SUB_l1_rrp_x1 + 216439U, // SUB_l1_rrp_x2 + 85367U, // SUB_l1_rrr_x1 + 85367U, // SUB_l1_rrr_x2 + 85367U, // SUB_s1_irr + 85367U, // SUB_s1_rrr + 91511U, // SUB_s4_rrr + 1232U, // SWAP4_l2_rr + 1271U, // UNPKHU4_l2_rr + 1271U, // UNPKHU4_s14_rr + 1289U, // UNPKLU4_l2_rr + 1289U, // UNPKLU4_s14_rr + 85587U, // XOR_d2_rir + 85587U, // XOR_d2_rrr + 85587U, // XOR_l1_irr + 85587U, // XOR_l1_rrr_x2 + 85587U, // XOR_s1_irr + 85587U, // XOR_s1_rrr + 1044U, // XPND2_m2_rr + 1209U, // XPND4_m2_rr + 0U + }; + + static char AsmStrs[] = { + /* 0 */ 'n', 'o', 'p', 9, 9, 0, + /* 6 */ 's', 'u', 'b', '2', 9, 0, + /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0, + /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0, + /* 26 */ 'a', 'v', 'g', '2', 9, 0, + /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0, + /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0, + /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0, + /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0, + /* 66 */ 'm', 'i', 'n', '2', 9, 0, + /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0, + /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0, + /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0, + /* 95 */ 's', 'h', 'r', '2', 9, 0, + /* 101 */ 'a', 'b', 's', '2', 9, 0, + /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0, + /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0, + /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0, + /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0, + /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0, + /* 152 */ 'm', 'a', 'x', '2', 9, 0, + /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0, + /* 165 */ 's', 'u', 'b', '4', 9, 0, + /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0, + /* 178 */ 'a', 'd', 'd', '4', 9, 0, + /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0, + /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0, + /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0, + /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0, + /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0, + /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0, + /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0, + /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0, + /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0, + /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0, + /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0, + /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0, + /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0, + /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0, + /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0, + /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0, + /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0, + /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0, + /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0, + /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0, + /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0, + /* 349 */ 'l', 'd', 'b', 9, 0, + /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0, + /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0, + /* 368 */ 's', 't', 'b', 9, 0, + /* 373 */ 's', 's', 'u', 'b', 9, 0, + /* 379 */ 's', 'u', 'b', 'c', 9, 0, + /* 385 */ 'b', 'd', 'e', 'c', 9, 0, + /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0, + /* 399 */ 'm', 'v', 'c', 9, 0, + /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0, + /* 411 */ 'l', 'm', 'b', 'd', 9, 0, + /* 417 */ 's', 'a', 'd', 'd', 9, 0, + /* 423 */ 'a', 'n', 'd', 9, 0, + /* 428 */ 'm', 'v', 'd', 9, 0, + /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0, + /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0, + /* 447 */ 'l', 'd', 'h', 9, 0, + /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0, + /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0, + /* 467 */ 's', 't', 'h', 9, 0, + /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0, + /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0, + /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0, + /* 493 */ 'a', 'd', 'd', 'k', 9, 0, + /* 499 */ 'm', 'v', 'k', 9, 0, + /* 504 */ 'd', 'e', 'a', 'l', 9, 0, + /* 510 */ 's', 'h', 'f', 'l', 9, 0, + /* 516 */ 's', 's', 'h', 'l', 9, 0, + /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0, + /* 530 */ 'r', 'o', 't', 'l', 9, 0, + /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0, + /* 543 */ 'n', 'o', 'r', 'm', 9, 0, + /* 549 */ 'a', 'n', 'd', 'n', 9, 0, + /* 555 */ 'b', 'n', 'o', 'p', 9, 0, + /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0, + /* 568 */ 's', 'h', 'r', 9, 0, + /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0, + /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0, + /* 589 */ 'c', 'l', 'r', 9, 0, + /* 594 */ 'x', 'o', 'r', 9, 0, + /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0, + /* 606 */ 'a', 'b', 's', 9, 0, + /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0, + /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0, + /* 629 */ 'b', 'p', 'o', 's', 9, 0, + /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0, + /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0, + /* 650 */ 's', 'a', 't', 9, 0, + /* 655 */ 's', 'e', 't', 9, 0, + /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0, + /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0, + /* 674 */ 'e', 'x', 't', 9, 0, + /* 679 */ 'l', 'd', 'b', 'u', 9, 0, + /* 685 */ 's', 'u', 'b', 'u', 9, 0, + /* 691 */ 'a', 'd', 'd', 'u', 9, 0, + /* 697 */ 'l', 'd', 'h', 'u', 9, 0, + /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0, + /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0, + /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0, + /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0, + /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0, + /* 744 */ 's', 'h', 'r', 'u', 9, 0, + /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0, + /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0, + /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0, + /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0, + /* 781 */ 'e', 'x', 't', 'u', 9, 0, + /* 787 */ 'm', 'p', 'y', 'u', 9, 0, + /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0, + /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0, + /* 807 */ 'l', 'd', 'd', 'w', 9, 0, + /* 813 */ 'l', 'd', 'w', 9, 0, + /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0, + /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0, + /* 832 */ 's', 't', 'd', 'w', 9, 0, + /* 838 */ 'l', 'd', 'n', 'w', 9, 0, + /* 844 */ 's', 't', 'n', 'w', 9, 0, + /* 850 */ 's', 't', 'w', 9, 0, + /* 855 */ 's', 'm', 'p', 'y', 9, 0, + /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0, + /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0, + /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0, + /* 891 */ 'b', 9, 'i', 'r', 'p', 0, + /* 897 */ 'b', 9, 'n', 'r', 'p', 0, + /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0, + }; + + // Emit the opcode for the instruction. + uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 1023)-1); +#endif + + + // Fragment 0 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 10) & 7) { + default: + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, B_s7_irp, B_s7_nrp + return; + break; + case 1: + // ABS2_l2_rr, ABS_l1_rr, ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 2: + // ABS_l1_pp, NORM_l1_pr, SAT_l1_pr, SHL_s1_pip, SHL_s1_prp, SHRU_s1_pip,... + printRegPair(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 3: + // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rpp,... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 4: + // BNOP_s10_ri, BNOP_s9_ii, B_s5_i, B_s6_r, NOP_n, STB_d5_rm, STB_d6_rm, ... + printOperand(MI, 0, O); + break; + case 5: + // LDBU_d5_mr, LDB_d5_mr, LDDW_d7_mp, LDHU_d5_mr, LDH_d5_mr, LDNDW_d8_mp,... + printMemOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 6: + // LDBU_d6_mr, LDB_d6_mr, LDHU_d6_mr, LDH_d6_mr, LDW_d6_mr + printMemOperand2(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 7: + // STDW_d7_pm, STNDW_d8_pm + printRegPair(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 1, O); + return; + break; + } + + + // Fragment 1 encoded into 3 bits for 7 unique commands. + switch ((Bits >> 13) & 7) { + default: + case 0: + // ABS2_l2_rr, ABS_l1_rr, ADDKPC_s3_iir, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2... + printOperand(MI, 0, O); + break; + case 1: + // ABS_l1_pp, LDDW_d7_mp, LDNDW_d8_mp + printRegPair(MI, 0, O); + return; + break; + case 2: + // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rrp_... + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 3: + // ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD_d1_rrr, ADDAH_d1_rir, ... + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 4: + // ADDU_l1_rpp, ADD_l1_ipp, ADD_l1_rpp, CMPEQ_l1_ipr, CMPEQ_l1_rpr, CMPGT... + printRegPair(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 5: + // BNOP_s10_ri, BNOP_s9_ii, STB_d5_rm, STB_d6_rm, STH_d5_rm, STH_d6_rm, S... + SStream_concat0(O, ", "); + break; + case 6: + // B_s5_i, B_s6_r, NOP_n + return; + break; + } + + + // Fragment 2 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 16) & 7) { + default: + case 0: + // ABS2_l2_rr, ABS_l1_rr, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2_rr, BPOS_s8_ir... + return; + break; + case 1: + // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDAB_d1_rir... + printOperand(MI, 0, O); + return; + break; + case 2: + // ADDKPC_s3_iir + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 3: + // ADDU_l1_rpp, ADDU_l1_rrp_x2, ADD_l1_ipp, ADD_l1_rpp, ADD_l1_rrp_x2, DO... + printRegPair(MI, 0, O); + return; + break; + case 4: + // BNOP_s10_ri, BNOP_s9_ii + printOperand(MI, 1, O); + return; + break; + case 5: + // CLR_s15_riir, EXTU_s15_riir, EXT_s15_riir, SET_s15_riir + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + return; + break; + case 6: + // STB_d5_rm, STH_d5_rm, STNW_d5_rm, STW_d5_rm + printMemOperand(MI, 1, O); + return; + break; + case 7: + // STB_d6_rm, STH_d6_rm, STW_d6_rm + printMemOperand2(MI, 1, O); + return; + break; + } + +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static char *getRegisterName(unsigned RegNo) { +#ifndef CAPSTONE_DIET + static char AsmStrs[] = { + /* 0 */ 'a', '1', '0', 0, + /* 4 */ 'b', '1', '0', 0, + /* 8 */ 'a', '2', '0', 0, + /* 12 */ 'b', '2', '0', 0, + /* 16 */ 'a', '3', '0', 0, + /* 20 */ 'b', '3', '0', 0, + /* 24 */ 'a', '0', 0, + /* 27 */ 'b', '0', 0, + /* 30 */ 'a', '1', '1', 0, + /* 34 */ 'b', '1', '1', 0, + /* 38 */ 'a', '2', '1', 0, + /* 42 */ 'b', '2', '1', 0, + /* 46 */ 'a', '3', '1', 0, + /* 50 */ 'b', '3', '1', 0, + /* 54 */ 'a', '1', 0, + /* 57 */ 'b', '1', 0, + /* 60 */ 'p', 'c', 'e', '1', 0, + /* 65 */ 'a', '1', '2', 0, + /* 69 */ 'b', '1', '2', 0, + /* 73 */ 'a', '2', '2', 0, + /* 77 */ 'b', '2', '2', 0, + /* 81 */ 'a', '2', 0, + /* 84 */ 'b', '2', 0, + /* 87 */ 'a', '1', '3', 0, + /* 91 */ 'b', '1', '3', 0, + /* 95 */ 'a', '2', '3', 0, + /* 99 */ 'b', '2', '3', 0, + /* 103 */ 'a', '3', 0, + /* 106 */ 'b', '3', 0, + /* 109 */ 'a', '1', '4', 0, + /* 113 */ 'b', '1', '4', 0, + /* 117 */ 'a', '2', '4', 0, + /* 121 */ 'b', '2', '4', 0, + /* 125 */ 'a', '4', 0, + /* 128 */ 'b', '4', 0, + /* 131 */ 'a', '1', '5', 0, + /* 135 */ 'b', '1', '5', 0, + /* 139 */ 'a', '2', '5', 0, + /* 143 */ 'b', '2', '5', 0, + /* 147 */ 'a', '5', 0, + /* 150 */ 'b', '5', 0, + /* 153 */ 'a', '1', '6', 0, + /* 157 */ 'b', '1', '6', 0, + /* 161 */ 'a', '2', '6', 0, + /* 165 */ 'b', '2', '6', 0, + /* 169 */ 'a', '6', 0, + /* 172 */ 'b', '6', 0, + /* 175 */ 'a', '1', '7', 0, + /* 179 */ 'b', '1', '7', 0, + /* 183 */ 'a', '2', '7', 0, + /* 187 */ 'b', '2', '7', 0, + /* 191 */ 'a', '7', 0, + /* 194 */ 'b', '7', 0, + /* 197 */ 'a', '1', '8', 0, + /* 201 */ 'b', '1', '8', 0, + /* 205 */ 'a', '2', '8', 0, + /* 209 */ 'b', '2', '8', 0, + /* 213 */ 'a', '8', 0, + /* 216 */ 'b', '8', 0, + /* 219 */ 'a', '1', '9', 0, + /* 223 */ 'b', '1', '9', 0, + /* 227 */ 'a', '2', '9', 0, + /* 231 */ 'b', '2', '9', 0, + /* 235 */ 'a', '9', 0, + /* 238 */ 'b', '9', 0, + /* 241 */ 'g', 'p', 'l', 'y', 'a', 0, + /* 247 */ 'g', 'p', 'l', 'y', 'b', 0, + /* 253 */ 'r', 'i', 'l', 'c', 0, + /* 258 */ 't', 's', 'c', 'h', 0, + /* 263 */ 't', 's', 'c', 'l', 0, + /* 268 */ 'd', 'n', 'u', 'm', 0, + /* 273 */ 'r', 'e', 'p', 0, + /* 277 */ 'i', 'r', 'p', 0, + /* 281 */ 'n', 'r', 'p', 0, + /* 285 */ 'i', 's', 't', 'p', 0, + /* 290 */ 'e', 'c', 'r', 0, + /* 294 */ 'i', 'c', 'r', 0, + /* 298 */ 'd', 'i', 'e', 'r', 0, + /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0, + /* 310 */ 'a', 'm', 'r', 0, + /* 314 */ 'i', 'e', 'r', 'r', 0, + /* 319 */ 'c', 's', 'r', 0, + /* 323 */ 'i', 's', 'r', 0, + /* 327 */ 's', 's', 'r', 0, + /* 331 */ 'i', 't', 's', 'r', 0, + /* 336 */ 'n', 't', 's', 'r', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 310, 319, 298, 268, 290, 303, 241, 247, 294, 299, 314, 254, 277, 323, + 285, 331, 281, 336, 273, 253, 327, 258, 263, 332, 24, 54, 81, 103, + 125, 147, 169, 191, 213, 235, 0, 30, 65, 87, 109, 131, 153, 175, + 197, 219, 8, 38, 73, 95, 117, 139, 161, 183, 205, 227, 16, 46, + 27, 57, 84, 106, 128, 150, 172, 194, 216, 238, 4, 34, 69, 91, + 113, 135, 157, 179, 201, 223, 12, 42, 77, 99, 121, 143, 165, 187, + 209, 231, 20, 50, 60, + }; + + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc new file mode 100644 index 0000000..edee71a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc @@ -0,0 +1,1352 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * TMS320C64x Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, \ + unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ... +/* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206 +/* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 10 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 30 +/* 14 */ MCD_OPC_CheckField, 17, 11, 0, 153, 8, // Skip to: 2221 +/* 20 */ MCD_OPC_CheckField, 12, 1, 0, 147, 8, // Skip to: 2221 +/* 26 */ MCD_OPC_Decode, 162, 1, 0, // Opcode: NOP_n +/* 30 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 38 +/* 34 */ MCD_OPC_Decode, 140, 1, 1, // Opcode: MPYH_m4_rrr +/* 38 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 46 +/* 42 */ MCD_OPC_Decode, 219, 1, 1, // Opcode: SMPYH_m4_rrr +/* 46 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 54 +/* 50 */ MCD_OPC_Decode, 136, 1, 1, // Opcode: MPYHSU_m4_rrr +/* 54 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 62 +/* 58 */ MCD_OPC_Decode, 138, 1, 1, // Opcode: MPYHUS_m4_rrr +/* 62 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 70 +/* 66 */ MCD_OPC_Decode, 139, 1, 1, // Opcode: MPYHU_m4_rrr +/* 70 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 78 +/* 74 */ MCD_OPC_Decode, 134, 1, 1, // Opcode: MPYHL_m4_rrr +/* 78 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 86 +/* 82 */ MCD_OPC_Decode, 218, 1, 1, // Opcode: SMPYHL_m4_rrr +/* 86 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 94 +/* 90 */ MCD_OPC_Decode, 135, 1, 1, // Opcode: MPYHSLU_m4_rrr +/* 94 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 102 +/* 98 */ MCD_OPC_Decode, 137, 1, 1, // Opcode: MPYHULS_m4_rrr +/* 102 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 110 +/* 106 */ MCD_OPC_Decode, 133, 1, 1, // Opcode: MPYHLU_m4_rrr +/* 110 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 118 +/* 114 */ MCD_OPC_Decode, 142, 1, 1, // Opcode: MPYLH_m4_rrr +/* 118 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 126 +/* 122 */ MCD_OPC_Decode, 220, 1, 1, // Opcode: SMPYLH_m4_rrr +/* 126 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 134 +/* 130 */ MCD_OPC_Decode, 145, 1, 1, // Opcode: MPYLSHU_m4_rrr +/* 134 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 142 +/* 138 */ MCD_OPC_Decode, 146, 1, 1, // Opcode: MPYLUHS_m4_rrr +/* 142 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 150 +/* 146 */ MCD_OPC_Decode, 141, 1, 1, // Opcode: MPYLHU_m4_rrr +/* 150 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 158 +/* 154 */ MCD_OPC_Decode, 153, 1, 2, // Opcode: MPY_m4_irr +/* 158 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 166 +/* 162 */ MCD_OPC_Decode, 154, 1, 1, // Opcode: MPY_m4_rrr +/* 166 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 174 +/* 170 */ MCD_OPC_Decode, 221, 1, 1, // Opcode: SMPY_m4_rrr +/* 174 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 182 +/* 178 */ MCD_OPC_Decode, 149, 1, 1, // Opcode: MPYSU_m4_rrr +/* 182 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 190 +/* 186 */ MCD_OPC_Decode, 151, 1, 1, // Opcode: MPYUS_m4_rrr +/* 190 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 198 +/* 194 */ MCD_OPC_Decode, 148, 1, 2, // Opcode: MPYSU_m4_irr +/* 198 */ MCD_OPC_FilterValue, 31, 227, 7, // Skip to: 2221 +/* 202 */ MCD_OPC_Decode, 152, 1, 1, // Opcode: MPYU_m4_rrr +/* 206 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 219 +/* 210 */ MCD_OPC_CheckField, 8, 1, 0, 213, 7, // Skip to: 2221 +/* 216 */ MCD_OPC_Decode, 116, 3, // Opcode: LDHU_d5_mr +/* 219 */ MCD_OPC_FilterValue, 2, 18, 0, // Skip to: 241 +/* 223 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 226 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 233 +/* 230 */ MCD_OPC_Decode, 102, 4, // Opcode: EXTU_s15_riir +/* 233 */ MCD_OPC_FilterValue, 1, 192, 7, // Skip to: 2221 +/* 237 */ MCD_OPC_Decode, 192, 1, 4, // Opcode: SET_s15_riir +/* 241 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 248 +/* 245 */ MCD_OPC_Decode, 117, 5, // Opcode: LDHU_d6_mr +/* 248 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 255 +/* 252 */ MCD_OPC_Decode, 68, 6, // Opcode: B_s5_i +/* 255 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 268 +/* 259 */ MCD_OPC_CheckField, 8, 1, 0, 164, 7, // Skip to: 2221 +/* 265 */ MCD_OPC_Decode, 111, 3, // Opcode: LDBU_d5_mr +/* 268 */ MCD_OPC_FilterValue, 6, 157, 0, // Skip to: 429 +/* 272 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 275 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 283 +/* 279 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: PACK2_l1_rrr_x2 +/* 283 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 291 +/* 287 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: SUB2_l1_rrr_x2 +/* 291 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 299 +/* 295 */ MCD_OPC_Decode, 176, 1, 1, // Opcode: PACKHL2_l1_rrr_x2 +/* 299 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 306 +/* 303 */ MCD_OPC_Decode, 45, 7, // Opcode: ADD_l1_ipp +/* 306 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 314 +/* 310 */ MCD_OPC_Decode, 130, 2, 7, // Opcode: SUB_l1_ipp +/* 314 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 322 +/* 318 */ MCD_OPC_Decode, 228, 1, 7, // Opcode: SSUB_l1_ipp +/* 322 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 330 +/* 326 */ MCD_OPC_Decode, 186, 1, 7, // Opcode: SADD_l1_ipp +/* 330 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 343 +/* 334 */ MCD_OPC_CheckField, 13, 5, 0, 89, 7, // Skip to: 2221 +/* 340 */ MCD_OPC_Decode, 23, 8, // Opcode: ABS_l1_pp +/* 343 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 357 +/* 347 */ MCD_OPC_CheckField, 13, 5, 0, 76, 7, // Skip to: 2221 +/* 353 */ MCD_OPC_Decode, 191, 1, 9, // Opcode: SAT_l1_pr +/* 357 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 364 +/* 361 */ MCD_OPC_Decode, 82, 10, // Opcode: CMPGT_l1_ipr +/* 364 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 372 +/* 368 */ MCD_OPC_Decode, 129, 1, 1, // Opcode: MINU4_l1_rrr_x2 +/* 372 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 379 +/* 376 */ MCD_OPC_Decode, 106, 11, // Opcode: GMPGTU_l1_ipr +/* 379 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 386 +/* 383 */ MCD_OPC_Decode, 76, 10, // Opcode: CMPEQ_l1_ipr +/* 386 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 393 +/* 390 */ MCD_OPC_Decode, 90, 10, // Opcode: CMPLT_l1_ipr +/* 393 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 400 +/* 397 */ MCD_OPC_Decode, 86, 11, // Opcode: CMPLTU_l1_ipr +/* 400 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 414 +/* 404 */ MCD_OPC_CheckField, 13, 5, 0, 19, 7, // Skip to: 2221 +/* 410 */ MCD_OPC_Decode, 163, 1, 12, // Opcode: NORM_l1_pr +/* 414 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 422 +/* 418 */ MCD_OPC_Decode, 178, 1, 1, // Opcode: PACKL4_l1_rrr_x2 +/* 422 */ MCD_OPC_FilterValue, 31, 3, 7, // Skip to: 2221 +/* 426 */ MCD_OPC_Decode, 53, 1, // Opcode: ANDN_l1_rrr_x2 +/* 429 */ MCD_OPC_FilterValue, 7, 3, 0, // Skip to: 436 +/* 433 */ MCD_OPC_Decode, 112, 5, // Opcode: LDBU_d6_mr +/* 436 */ MCD_OPC_FilterValue, 8, 222, 0, // Skip to: 662 +/* 440 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 443 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 464 +/* 447 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 450 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 457 +/* 454 */ MCD_OPC_Decode, 67, 13, // Opcode: BPOS_s8_ir +/* 457 */ MCD_OPC_FilterValue, 1, 224, 6, // Skip to: 2221 +/* 461 */ MCD_OPC_Decode, 63, 13, // Opcode: BDEC_s8_ir +/* 464 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 477 +/* 468 */ MCD_OPC_CheckField, 12, 1, 0, 211, 6, // Skip to: 2221 +/* 474 */ MCD_OPC_Decode, 66, 14, // Opcode: BNOP_s9_ii +/* 477 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 484 +/* 481 */ MCD_OPC_Decode, 50, 2, // Opcode: ADD_s1_irr +/* 484 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 492 +/* 488 */ MCD_OPC_Decode, 177, 1, 1, // Opcode: PACKHL2_s1_rrr +/* 492 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 500 +/* 496 */ MCD_OPC_Decode, 148, 2, 2, // Opcode: XOR_s1_irr +/* 500 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 514 +/* 504 */ MCD_OPC_CheckField, 13, 5, 0, 175, 6, // Skip to: 2221 +/* 510 */ MCD_OPC_Decode, 156, 1, 15, // Opcode: MVC_s1_rr2 +/* 514 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 522 +/* 518 */ MCD_OPC_Decode, 180, 1, 1, // Opcode: PACKLH2_s1_rrr +/* 522 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 530 +/* 526 */ MCD_OPC_Decode, 199, 1, 16, // Opcode: SHL_s1_rip +/* 530 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 537 +/* 534 */ MCD_OPC_Decode, 80, 1, // Opcode: CMPGT2_s1_rrr +/* 537 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 545 +/* 541 */ MCD_OPC_Decode, 136, 2, 2, // Opcode: SUB_s1_irr +/* 545 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 553 +/* 549 */ MCD_OPC_Decode, 203, 1, 17, // Opcode: SHR2_s1_rir +/* 553 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 561 +/* 557 */ MCD_OPC_Decode, 169, 1, 2, // Opcode: OR_s1_irr +/* 561 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 568 +/* 565 */ MCD_OPC_Decode, 75, 1, // Opcode: CMPEQ4_s1_rrr +/* 568 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 575 +/* 572 */ MCD_OPC_Decode, 59, 2, // Opcode: AND_s1_irr +/* 575 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 583 +/* 579 */ MCD_OPC_Decode, 190, 1, 1, // Opcode: SADD_s1_rrr +/* 583 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 591 +/* 587 */ MCD_OPC_Decode, 224, 1, 17, // Opcode: SSHL_s1_rir +/* 591 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 599 +/* 595 */ MCD_OPC_Decode, 209, 1, 18, // Opcode: SHRU_s1_pip +/* 599 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 607 +/* 603 */ MCD_OPC_Decode, 211, 1, 17, // Opcode: SHRU_s1_rir +/* 607 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 615 +/* 611 */ MCD_OPC_Decode, 197, 1, 19, // Opcode: SHL_s1_pip +/* 615 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 623 +/* 619 */ MCD_OPC_Decode, 200, 1, 20, // Opcode: SHL_s1_rir +/* 623 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 631 +/* 627 */ MCD_OPC_Decode, 213, 1, 18, // Opcode: SHR_s1_pip +/* 631 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 639 +/* 635 */ MCD_OPC_Decode, 215, 1, 17, // Opcode: SHR_s1_rir +/* 639 */ MCD_OPC_FilterValue, 30, 42, 6, // Skip to: 2221 +/* 643 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... +/* 646 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 654 +/* 650 */ MCD_OPC_Decode, 143, 2, 21, // Opcode: UNPKLU4_s14_rr +/* 654 */ MCD_OPC_FilterValue, 3, 27, 6, // Skip to: 2221 +/* 658 */ MCD_OPC_Decode, 141, 2, 21, // Opcode: UNPKHU4_s14_rr +/* 662 */ MCD_OPC_FilterValue, 9, 17, 0, // Skip to: 683 +/* 666 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 669 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 676 +/* 673 */ MCD_OPC_Decode, 113, 3, // Opcode: LDB_d5_mr +/* 676 */ MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 2221 +/* 680 */ MCD_OPC_Decode, 120, 22, // Opcode: LDNDW_d8_mp +/* 683 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 691 +/* 687 */ MCD_OPC_Decode, 159, 1, 23, // Opcode: MVKL_s12_ir +/* 691 */ MCD_OPC_FilterValue, 11, 3, 0, // Skip to: 698 +/* 695 */ MCD_OPC_Decode, 114, 5, // Opcode: LDB_d6_mr +/* 698 */ MCD_OPC_FilterValue, 12, 194, 0, // Skip to: 896 +/* 702 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 705 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 713 +/* 709 */ MCD_OPC_Decode, 130, 1, 24, // Opcode: MPY2_m1_rrp +/* 713 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 720 +/* 717 */ MCD_OPC_Decode, 100, 1, // Opcode: DOTPSU4_m1_rrr +/* 720 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 728 +/* 724 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: MPYU4_m1_rrp +/* 728 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 735 +/* 732 */ MCD_OPC_Decode, 101, 1, // Opcode: DOTPU4_m1_rrr +/* 735 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 742 +/* 739 */ MCD_OPC_Decode, 96, 1, // Opcode: DOTP2_m1_rrr +/* 742 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 750 +/* 746 */ MCD_OPC_Decode, 143, 1, 1, // Opcode: MPYLIR_m1_rrr +/* 750 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 758 +/* 754 */ MCD_OPC_Decode, 131, 1, 1, // Opcode: MPYHIR_m1_rrr +/* 758 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 765 +/* 762 */ MCD_OPC_Decode, 62, 1, // Opcode: AVGU4_m1_rrr +/* 765 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 773 +/* 769 */ MCD_OPC_Decode, 132, 1, 24, // Opcode: MPYHI_m1_rrp +/* 773 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 781 +/* 777 */ MCD_OPC_Decode, 227, 1, 1, // Opcode: SSHVR_m1_rrr +/* 781 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 789 +/* 785 */ MCD_OPC_Decode, 226, 1, 1, // Opcode: SSHVL_m1_rrr +/* 789 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 797 +/* 793 */ MCD_OPC_Decode, 181, 1, 17, // Opcode: ROTL_m1_rir +/* 797 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 804 +/* 801 */ MCD_OPC_Decode, 52, 1, // Opcode: ANDN_d2_rrr +/* 804 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 812 +/* 808 */ MCD_OPC_Decode, 166, 1, 1, // Opcode: OR_d2_rrr +/* 812 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 819 +/* 816 */ MCD_OPC_Decode, 25, 1, // Opcode: ADD2_d2_rrr +/* 819 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 826 +/* 823 */ MCD_OPC_Decode, 56, 1, // Opcode: AND_d2_rrr +/* 826 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 833 +/* 830 */ MCD_OPC_Decode, 44, 1, // Opcode: ADD_d2_rrr +/* 833 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 841 +/* 837 */ MCD_OPC_Decode, 129, 2, 1, // Opcode: SUB_d2_rrr +/* 841 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 849 +/* 845 */ MCD_OPC_Decode, 145, 2, 1, // Opcode: XOR_d2_rrr +/* 849 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 857 +/* 853 */ MCD_OPC_Decode, 183, 1, 1, // Opcode: SADD2_s4_rrr +/* 857 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 865 +/* 861 */ MCD_OPC_Decode, 222, 1, 1, // Opcode: SPACK2_s4_rrr +/* 865 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 873 +/* 869 */ MCD_OPC_Decode, 223, 1, 1, // Opcode: SPACKU4_s4_rrr +/* 873 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 880 +/* 877 */ MCD_OPC_Decode, 54, 1, // Opcode: ANDN_s4_rrr +/* 880 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 888 +/* 884 */ MCD_OPC_Decode, 208, 1, 1, // Opcode: SHRU2_s4_rrr +/* 888 */ MCD_OPC_FilterValue, 29, 49, 5, // Skip to: 2221 +/* 892 */ MCD_OPC_Decode, 206, 1, 1, // Opcode: SHRMB_s4_rrr +/* 896 */ MCD_OPC_FilterValue, 13, 18, 0, // Skip to: 918 +/* 900 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 903 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 911 +/* 907 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: STB_d5_rm +/* 911 */ MCD_OPC_FilterValue, 1, 26, 5, // Skip to: 2221 +/* 915 */ MCD_OPC_Decode, 121, 3, // Opcode: LDNW_d5_mr +/* 918 */ MCD_OPC_FilterValue, 14, 98, 0, // Skip to: 1020 +/* 922 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 925 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 932 +/* 929 */ MCD_OPC_Decode, 26, 1, // Opcode: ADD2_l1_rrr_x2 +/* 932 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 939 +/* 936 */ MCD_OPC_Decode, 47, 25, // Opcode: ADD_l1_rpp +/* 939 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 946 +/* 943 */ MCD_OPC_Decode, 39, 25, // Opcode: ADDU_l1_rpp +/* 946 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 954 +/* 950 */ MCD_OPC_Decode, 188, 1, 25, // Opcode: SADD_l1_rpp +/* 954 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 962 +/* 958 */ MCD_OPC_Decode, 128, 1, 1, // Opcode: MIN2_l1_rrr_x2 +/* 962 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 969 +/* 966 */ MCD_OPC_Decode, 84, 26, // Opcode: CMPGT_l1_rpr +/* 969 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 976 +/* 973 */ MCD_OPC_Decode, 108, 26, // Opcode: GMPGTU_l1_rpr +/* 976 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 983 +/* 980 */ MCD_OPC_Decode, 78, 26, // Opcode: CMPEQ_l1_rpr +/* 983 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 990 +/* 987 */ MCD_OPC_Decode, 92, 26, // Opcode: CMPLT_l1_rpr +/* 990 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 997 +/* 994 */ MCD_OPC_Decode, 88, 26, // Opcode: CMPLTU_l1_rpr +/* 997 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1005 +/* 1001 */ MCD_OPC_Decode, 195, 1, 1, // Opcode: SHLMB_l1_rrr_x2 +/* 1005 */ MCD_OPC_FilterValue, 25, 3, 0, // Skip to: 1012 +/* 1009 */ MCD_OPC_Decode, 28, 1, // Opcode: ADD4_l1_rrr_x2 +/* 1012 */ MCD_OPC_FilterValue, 26, 181, 4, // Skip to: 2221 +/* 1016 */ MCD_OPC_Decode, 175, 1, 1, // Opcode: PACKH4_l1_rrr_x2 +/* 1020 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1028 +/* 1024 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: STB_d6_rm +/* 1028 */ MCD_OPC_FilterValue, 16, 151, 0, // Skip to: 1183 +/* 1032 */ MCD_OPC_ExtractField, 7, 6, // Inst{12-7} ... +/* 1035 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1049 +/* 1039 */ MCD_OPC_CheckField, 18, 5, 0, 152, 4, // Skip to: 2221 +/* 1045 */ MCD_OPC_Decode, 160, 1, 27, // Opcode: MVK_d1_rr +/* 1049 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1056 +/* 1053 */ MCD_OPC_Decode, 42, 28, // Opcode: ADD_d1_rrr +/* 1056 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1064 +/* 1060 */ MCD_OPC_Decode, 128, 2, 28, // Opcode: SUB_d1_rrr +/* 1064 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 1071 +/* 1068 */ MCD_OPC_Decode, 41, 29, // Opcode: ADD_d1_rir +/* 1071 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1079 +/* 1075 */ MCD_OPC_Decode, 255, 1, 29, // Opcode: SUB_d1_rir +/* 1079 */ MCD_OPC_FilterValue, 48, 3, 0, // Skip to: 1086 +/* 1083 */ MCD_OPC_Decode, 30, 28, // Opcode: ADDAB_d1_rrr +/* 1086 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 1094 +/* 1090 */ MCD_OPC_Decode, 247, 1, 28, // Opcode: SUBAB_d1_rrr +/* 1094 */ MCD_OPC_FilterValue, 50, 3, 0, // Skip to: 1101 +/* 1098 */ MCD_OPC_Decode, 29, 29, // Opcode: ADDAB_d1_rir +/* 1101 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1109 +/* 1105 */ MCD_OPC_Decode, 246, 1, 29, // Opcode: SUBAB_d1_rir +/* 1109 */ MCD_OPC_FilterValue, 52, 3, 0, // Skip to: 1116 +/* 1113 */ MCD_OPC_Decode, 34, 28, // Opcode: ADDAH_d1_rrr +/* 1116 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1124 +/* 1120 */ MCD_OPC_Decode, 249, 1, 28, // Opcode: SUBAH_d1_rrr +/* 1124 */ MCD_OPC_FilterValue, 54, 3, 0, // Skip to: 1131 +/* 1128 */ MCD_OPC_Decode, 33, 29, // Opcode: ADDAH_d1_rir +/* 1131 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 1139 +/* 1135 */ MCD_OPC_Decode, 248, 1, 29, // Opcode: SUBAH_d1_rir +/* 1139 */ MCD_OPC_FilterValue, 56, 3, 0, // Skip to: 1146 +/* 1143 */ MCD_OPC_Decode, 36, 28, // Opcode: ADDAW_d1_rrr +/* 1146 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1154 +/* 1150 */ MCD_OPC_Decode, 251, 1, 28, // Opcode: SUBAW_d1_rrr +/* 1154 */ MCD_OPC_FilterValue, 58, 3, 0, // Skip to: 1161 +/* 1158 */ MCD_OPC_Decode, 35, 29, // Opcode: ADDAW_d1_rir +/* 1161 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 1169 +/* 1165 */ MCD_OPC_Decode, 250, 1, 29, // Opcode: SUBAW_d1_rir +/* 1169 */ MCD_OPC_FilterValue, 60, 3, 0, // Skip to: 1176 +/* 1173 */ MCD_OPC_Decode, 32, 28, // Opcode: ADDAD_d1_rrr +/* 1176 */ MCD_OPC_FilterValue, 61, 17, 4, // Skip to: 2221 +/* 1180 */ MCD_OPC_Decode, 31, 29, // Opcode: ADDAD_d1_rir +/* 1183 */ MCD_OPC_FilterValue, 17, 18, 0, // Skip to: 1205 +/* 1187 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 1190 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1197 +/* 1194 */ MCD_OPC_Decode, 118, 3, // Opcode: LDH_d5_mr +/* 1197 */ MCD_OPC_FilterValue, 1, 252, 3, // Skip to: 2221 +/* 1201 */ MCD_OPC_Decode, 234, 1, 30, // Opcode: STDW_d7_pm +/* 1205 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 1226 +/* 1209 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1212 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1219 +/* 1216 */ MCD_OPC_Decode, 104, 4, // Opcode: EXT_s15_riir +/* 1219 */ MCD_OPC_FilterValue, 1, 230, 3, // Skip to: 2221 +/* 1223 */ MCD_OPC_Decode, 72, 4, // Opcode: CLR_s15_riir +/* 1226 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1233 +/* 1230 */ MCD_OPC_Decode, 119, 5, // Opcode: LDH_d6_mr +/* 1233 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1240 +/* 1237 */ MCD_OPC_Decode, 38, 23, // Opcode: ADDK_s2_ir +/* 1240 */ MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 1263 +/* 1244 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 1247 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1255 +/* 1251 */ MCD_OPC_Decode, 235, 1, 3, // Opcode: STH_d5_rm +/* 1255 */ MCD_OPC_FilterValue, 1, 194, 3, // Skip to: 2221 +/* 1259 */ MCD_OPC_Decode, 238, 1, 3, // Opcode: STNW_d5_rm +/* 1263 */ MCD_OPC_FilterValue, 22, 191, 0, // Skip to: 1458 +/* 1267 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 1270 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1277 +/* 1274 */ MCD_OPC_Decode, 46, 2, // Opcode: ADD_l1_irr +/* 1277 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1285 +/* 1281 */ MCD_OPC_Decode, 131, 2, 2, // Opcode: SUB_l1_irr +/* 1285 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1293 +/* 1289 */ MCD_OPC_Decode, 229, 1, 2, // Opcode: SSUB_l1_irr +/* 1293 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1301 +/* 1297 */ MCD_OPC_Decode, 187, 1, 2, // Opcode: SADD_l1_irr +/* 1301 */ MCD_OPC_FilterValue, 6, 49, 0, // Skip to: 1354 +/* 1305 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... +/* 1308 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1315 +/* 1312 */ MCD_OPC_Decode, 24, 21, // Opcode: ABS_l1_rr +/* 1315 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1323 +/* 1319 */ MCD_OPC_Decode, 139, 2, 21, // Opcode: SWAP4_l2_rr +/* 1323 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1331 +/* 1327 */ MCD_OPC_Decode, 142, 2, 21, // Opcode: UNPKLU4_l2_rr +/* 1331 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1339 +/* 1335 */ MCD_OPC_Decode, 140, 2, 21, // Opcode: UNPKHU4_l2_rr +/* 1339 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1346 +/* 1343 */ MCD_OPC_Decode, 22, 21, // Opcode: ABS2_l2_rr +/* 1346 */ MCD_OPC_FilterValue, 5, 103, 3, // Skip to: 2221 +/* 1350 */ MCD_OPC_Decode, 161, 1, 31, // Opcode: MVK_l2_ir +/* 1354 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1362 +/* 1358 */ MCD_OPC_Decode, 173, 1, 1, // Opcode: PACKH2_l1_rrr_x2 +/* 1362 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1369 +/* 1366 */ MCD_OPC_Decode, 126, 1, // Opcode: MAX2_l1_rrr_x2 +/* 1369 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 1376 +/* 1373 */ MCD_OPC_Decode, 83, 2, // Opcode: CMPGT_l1_irr +/* 1376 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1383 +/* 1380 */ MCD_OPC_Decode, 107, 17, // Opcode: GMPGTU_l1_irr +/* 1383 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1390 +/* 1387 */ MCD_OPC_Decode, 77, 2, // Opcode: CMPEQ_l1_irr +/* 1390 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1397 +/* 1394 */ MCD_OPC_Decode, 91, 2, // Opcode: CMPLT_l1_irr +/* 1397 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 1405 +/* 1401 */ MCD_OPC_Decode, 245, 1, 1, // Opcode: SUBABS4_l1_rrr_x2 +/* 1405 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1412 +/* 1409 */ MCD_OPC_Decode, 87, 17, // Opcode: CMPLTU_l1_irr +/* 1412 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1420 +/* 1416 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SHRMB_l1_rrr_x2 +/* 1420 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1428 +/* 1424 */ MCD_OPC_Decode, 244, 1, 1, // Opcode: SUB4_l1_rrr_x2 +/* 1428 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 1435 +/* 1432 */ MCD_OPC_Decode, 124, 2, // Opcode: LMBD_l1_irr +/* 1435 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1443 +/* 1439 */ MCD_OPC_Decode, 146, 2, 2, // Opcode: XOR_l1_irr +/* 1443 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 1450 +/* 1447 */ MCD_OPC_Decode, 57, 2, // Opcode: AND_l1_irr +/* 1450 */ MCD_OPC_FilterValue, 31, 255, 2, // Skip to: 2221 +/* 1454 */ MCD_OPC_Decode, 167, 1, 2, // Opcode: OR_l1_irr +/* 1458 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1466 +/* 1462 */ MCD_OPC_Decode, 236, 1, 5, // Opcode: STH_d6_rm +/* 1466 */ MCD_OPC_FilterValue, 24, 6, 1, // Skip to: 1732 +/* 1470 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 1473 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1480 +/* 1477 */ MCD_OPC_Decode, 27, 1, // Opcode: ADD2_s1_rrr +/* 1480 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 1503 +/* 1484 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ... +/* 1487 */ MCD_OPC_FilterValue, 128, 3, 3, 0, // Skip to: 1495 +/* 1492 */ MCD_OPC_Decode, 70, 32, // Opcode: B_s7_irp +/* 1495 */ MCD_OPC_FilterValue, 192, 3, 209, 2, // Skip to: 2221 +/* 1500 */ MCD_OPC_Decode, 71, 32, // Opcode: B_s7_nrp +/* 1503 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1516 +/* 1507 */ MCD_OPC_CheckField, 12, 1, 0, 196, 2, // Skip to: 2221 +/* 1513 */ MCD_OPC_Decode, 37, 33, // Opcode: ADDKPC_s3_iir +/* 1516 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1523 +/* 1520 */ MCD_OPC_Decode, 51, 1, // Opcode: ADD_s1_rrr +/* 1523 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1531 +/* 1527 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: PACKH2_s1_rrr +/* 1531 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1539 +/* 1535 */ MCD_OPC_Decode, 149, 2, 1, // Opcode: XOR_s1_rrr +/* 1539 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 1572 +/* 1543 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... +/* 1546 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1559 +/* 1550 */ MCD_OPC_CheckField, 13, 5, 0, 153, 2, // Skip to: 2221 +/* 1556 */ MCD_OPC_Decode, 69, 34, // Opcode: B_s6_r +/* 1559 */ MCD_OPC_FilterValue, 1, 146, 2, // Skip to: 2221 +/* 1563 */ MCD_OPC_CheckField, 16, 2, 0, 140, 2, // Skip to: 2221 +/* 1569 */ MCD_OPC_Decode, 65, 35, // Opcode: BNOP_s10_ri +/* 1572 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 1586 +/* 1576 */ MCD_OPC_CheckField, 13, 5, 0, 127, 2, // Skip to: 2221 +/* 1582 */ MCD_OPC_Decode, 155, 1, 36, // Opcode: MVC_s1_rr +/* 1586 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1594 +/* 1590 */ MCD_OPC_Decode, 243, 1, 1, // Opcode: SUB2_s1_rrr +/* 1594 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1602 +/* 1598 */ MCD_OPC_Decode, 201, 1, 37, // Opcode: SHL_s1_rrp +/* 1602 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 1609 +/* 1606 */ MCD_OPC_Decode, 81, 1, // Opcode: CMPGTU4_s1_rrr +/* 1609 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1617 +/* 1613 */ MCD_OPC_Decode, 137, 2, 1, // Opcode: SUB_s1_rrr +/* 1617 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1625 +/* 1621 */ MCD_OPC_Decode, 207, 1, 17, // Opcode: SHRU2_s1_rir +/* 1625 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1633 +/* 1629 */ MCD_OPC_Decode, 170, 1, 1, // Opcode: OR_s1_rrr +/* 1633 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 1640 +/* 1637 */ MCD_OPC_Decode, 74, 1, // Opcode: CMPEQ2_s1_rrr +/* 1640 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 1647 +/* 1644 */ MCD_OPC_Decode, 60, 1, // Opcode: AND_s1_rrr +/* 1647 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1655 +/* 1651 */ MCD_OPC_Decode, 225, 1, 1, // Opcode: SSHL_s1_rrr +/* 1655 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1663 +/* 1659 */ MCD_OPC_Decode, 210, 1, 38, // Opcode: SHRU_s1_prp +/* 1663 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1671 +/* 1667 */ MCD_OPC_Decode, 212, 1, 1, // Opcode: SHRU_s1_rrr +/* 1671 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1678 +/* 1675 */ MCD_OPC_Decode, 103, 1, // Opcode: EXTU_s1_rrr +/* 1678 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1685 +/* 1682 */ MCD_OPC_Decode, 105, 1, // Opcode: EXT_s1_rrr +/* 1685 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1693 +/* 1689 */ MCD_OPC_Decode, 198, 1, 25, // Opcode: SHL_s1_prp +/* 1693 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1701 +/* 1697 */ MCD_OPC_Decode, 202, 1, 39, // Opcode: SHL_s1_rrr +/* 1701 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1709 +/* 1705 */ MCD_OPC_Decode, 214, 1, 38, // Opcode: SHR_s1_prp +/* 1709 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1717 +/* 1713 */ MCD_OPC_Decode, 216, 1, 1, // Opcode: SHR_s1_rrr +/* 1717 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 1725 +/* 1721 */ MCD_OPC_Decode, 193, 1, 1, // Opcode: SET_s1_rrr +/* 1725 */ MCD_OPC_FilterValue, 31, 236, 1, // Skip to: 2221 +/* 1729 */ MCD_OPC_Decode, 73, 1, // Opcode: CLR_s1_rrr +/* 1732 */ MCD_OPC_FilterValue, 25, 17, 0, // Skip to: 1753 +/* 1736 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 1739 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1746 +/* 1743 */ MCD_OPC_Decode, 122, 3, // Opcode: LDW_d5_mr +/* 1746 */ MCD_OPC_FilterValue, 1, 215, 1, // Skip to: 2221 +/* 1750 */ MCD_OPC_Decode, 115, 30, // Opcode: LDDW_d7_mp +/* 1753 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1761 +/* 1757 */ MCD_OPC_Decode, 158, 1, 23, // Opcode: MVKLH_s12_ir +/* 1761 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 1768 +/* 1765 */ MCD_OPC_Decode, 123, 5, // Opcode: LDW_d6_mr +/* 1768 */ MCD_OPC_FilterValue, 28, 216, 0, // Skip to: 1988 +/* 1772 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 1775 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1783 +/* 1779 */ MCD_OPC_Decode, 217, 1, 24, // Opcode: SMPY2_m1_rrp +/* 1783 */ MCD_OPC_FilterValue, 1, 49, 0, // Skip to: 1836 +/* 1787 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... +/* 1790 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1798 +/* 1794 */ MCD_OPC_Decode, 151, 2, 21, // Opcode: XPND4_m2_rr +/* 1798 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1806 +/* 1802 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: XPND2_m2_rr +/* 1806 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1814 +/* 1810 */ MCD_OPC_Decode, 157, 1, 21, // Opcode: MVD_m2_rr +/* 1814 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1822 +/* 1818 */ MCD_OPC_Decode, 194, 1, 21, // Opcode: SHFL_m2_rr +/* 1822 */ MCD_OPC_FilterValue, 29, 3, 0, // Skip to: 1829 +/* 1826 */ MCD_OPC_Decode, 94, 21, // Opcode: DEAL_m2_rr +/* 1829 */ MCD_OPC_FilterValue, 30, 132, 1, // Skip to: 2221 +/* 1833 */ MCD_OPC_Decode, 64, 21, // Opcode: BITC4_m2_rr +/* 1836 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1844 +/* 1840 */ MCD_OPC_Decode, 147, 1, 24, // Opcode: MPYSU4_m1_rrp +/* 1844 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1851 +/* 1848 */ MCD_OPC_Decode, 98, 1, // Opcode: DOTPNRSU2_m1_rrr +/* 1851 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1858 +/* 1855 */ MCD_OPC_Decode, 97, 1, // Opcode: DOTPN2_m1_rrr +/* 1858 */ MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 1865 +/* 1862 */ MCD_OPC_Decode, 95, 24, // Opcode: DOTP2_m1_rrp +/* 1865 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 1872 +/* 1869 */ MCD_OPC_Decode, 99, 1, // Opcode: DOTPRSU2_m1_rrr +/* 1872 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 1879 +/* 1876 */ MCD_OPC_Decode, 110, 1, // Opcode: GMPY4_m1_rrr +/* 1879 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 1886 +/* 1883 */ MCD_OPC_Decode, 61, 1, // Opcode: AVG2_m1_rrr +/* 1886 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1894 +/* 1890 */ MCD_OPC_Decode, 144, 1, 24, // Opcode: MPYLI_m1_rrp +/* 1894 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1902 +/* 1898 */ MCD_OPC_Decode, 182, 1, 1, // Opcode: ROTL_m1_rrr +/* 1902 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1910 +/* 1906 */ MCD_OPC_Decode, 165, 1, 2, // Opcode: OR_d2_rir +/* 1910 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1918 +/* 1914 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: SUB2_d2_rrr +/* 1918 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1925 +/* 1922 */ MCD_OPC_Decode, 55, 2, // Opcode: AND_d2_rir +/* 1925 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1932 +/* 1929 */ MCD_OPC_Decode, 43, 2, // Opcode: ADD_d2_rir +/* 1932 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1940 +/* 1936 */ MCD_OPC_Decode, 144, 2, 2, // Opcode: XOR_d2_rir +/* 1940 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1948 +/* 1944 */ MCD_OPC_Decode, 185, 1, 1, // Opcode: SADDUS2_s4_rrr +/* 1948 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1956 +/* 1952 */ MCD_OPC_Decode, 184, 1, 1, // Opcode: SADDU4_s4_rrr +/* 1956 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1964 +/* 1960 */ MCD_OPC_Decode, 138, 2, 1, // Opcode: SUB_s4_rrr +/* 1964 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1972 +/* 1968 */ MCD_OPC_Decode, 204, 1, 1, // Opcode: SHR2_s4_rrr +/* 1972 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1980 +/* 1976 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SHLMB_s4_rrr +/* 1980 */ MCD_OPC_FilterValue, 31, 237, 0, // Skip to: 2221 +/* 1984 */ MCD_OPC_Decode, 172, 1, 1, // Opcode: PACK2_s4_rrr +/* 1988 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 2011 +/* 1992 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 1995 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2003 +/* 1999 */ MCD_OPC_Decode, 239, 1, 3, // Opcode: STW_d5_rm +/* 2003 */ MCD_OPC_FilterValue, 1, 214, 0, // Skip to: 2221 +/* 2007 */ MCD_OPC_Decode, 237, 1, 22, // Opcode: STNDW_d8_pm +/* 2011 */ MCD_OPC_FilterValue, 30, 198, 0, // Skip to: 2213 +/* 2015 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... +/* 2018 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2025 +/* 2022 */ MCD_OPC_Decode, 49, 1, // Opcode: ADD_l1_rrr_x2 +/* 2025 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2033 +/* 2029 */ MCD_OPC_Decode, 135, 2, 1, // Opcode: SUB_l1_rrr_x2 +/* 2033 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2041 +/* 2037 */ MCD_OPC_Decode, 231, 1, 1, // Opcode: SSUB_l1_rrr_x2 +/* 2041 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 2049 +/* 2045 */ MCD_OPC_Decode, 189, 1, 1, // Opcode: SADD_l1_rrr_x2 +/* 2049 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 2057 +/* 2053 */ MCD_OPC_Decode, 134, 2, 39, // Opcode: SUB_l1_rrr_x1 +/* 2057 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 2065 +/* 2061 */ MCD_OPC_Decode, 179, 1, 1, // Opcode: PACKLH2_l1_rrr_x2 +/* 2065 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 2073 +/* 2069 */ MCD_OPC_Decode, 230, 1, 39, // Opcode: SSUB_l1_rrr_x1 +/* 2073 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 2080 +/* 2077 */ MCD_OPC_Decode, 48, 24, // Opcode: ADD_l1_rrp_x2 +/* 2080 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2088 +/* 2084 */ MCD_OPC_Decode, 133, 2, 24, // Opcode: SUB_l1_rrp_x2 +/* 2088 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 2095 +/* 2092 */ MCD_OPC_Decode, 40, 24, // Opcode: ADDU_l1_rrp_x2 +/* 2095 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2103 +/* 2099 */ MCD_OPC_Decode, 254, 1, 24, // Opcode: SUBU_l1_rrp_x2 +/* 2103 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2111 +/* 2107 */ MCD_OPC_Decode, 132, 2, 37, // Opcode: SUB_l1_rrp_x1 +/* 2111 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 2119 +/* 2115 */ MCD_OPC_Decode, 253, 1, 37, // Opcode: SUBU_l1_rrp_x1 +/* 2119 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 2126 +/* 2123 */ MCD_OPC_Decode, 127, 1, // Opcode: MAXU4_l1_rrr_x2 +/* 2126 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 2133 +/* 2130 */ MCD_OPC_Decode, 85, 1, // Opcode: CMPGT_l1_rrr_x2 +/* 2133 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 2141 +/* 2137 */ MCD_OPC_Decode, 252, 1, 1, // Opcode: SUBC_l1_rrr_x2 +/* 2141 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 2148 +/* 2145 */ MCD_OPC_Decode, 109, 1, // Opcode: GMPGTU_l1_rrr_x2 +/* 2148 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 2155 +/* 2152 */ MCD_OPC_Decode, 79, 1, // Opcode: CMPEQ_l1_rrr_x2 +/* 2155 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 2162 +/* 2159 */ MCD_OPC_Decode, 93, 1, // Opcode: CMPLT_l1_rrr_x2 +/* 2162 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 2169 +/* 2166 */ MCD_OPC_Decode, 89, 1, // Opcode: CMPLTU_l1_rrr_x2 +/* 2169 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 2183 +/* 2173 */ MCD_OPC_CheckField, 13, 5, 0, 42, 0, // Skip to: 2221 +/* 2179 */ MCD_OPC_Decode, 164, 1, 21, // Opcode: NORM_l1_rr +/* 2183 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 2190 +/* 2187 */ MCD_OPC_Decode, 125, 1, // Opcode: LMBD_l1_rrr_x2 +/* 2190 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 2198 +/* 2194 */ MCD_OPC_Decode, 147, 2, 1, // Opcode: XOR_l1_rrr_x2 +/* 2198 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 2205 +/* 2202 */ MCD_OPC_Decode, 58, 1, // Opcode: AND_l1_rrr_x2 +/* 2205 */ MCD_OPC_FilterValue, 31, 12, 0, // Skip to: 2221 +/* 2209 */ MCD_OPC_Decode, 168, 1, 1, // Opcode: OR_l1_rrr_x2 +/* 2213 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 2221 +/* 2217 */ MCD_OPC_Decode, 240, 1, 5, // Opcode: STW_d6_rm +/* 2221 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { + return true; +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, void *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + tmp = fieldname(insn, 13, 4); \ + if (DecodeNop(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 1: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 9, 14) << 1; \ + if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 16); \ + if (DecodeMemOperand2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + tmp = fieldname(insn, 7, 21); \ + if (DecodePCRelScst21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 11: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 12: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 13: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 10); \ + if (DecodePCRelScst10(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 16, 12); \ + if (DecodePCRelScst12(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 19: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 20: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 21: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + tmp = fieldname(insn, 24, 4); \ + if (DecodeRegPair4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 9, 15) << 1; \ + if (DecodeMemOperandSc(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 7, 16); \ + if (DecodeScst16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 28: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 29: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 30: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 9, 14) << 1; \ + if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 7); \ + if (DecodePCRelScst7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 36: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 37: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 38: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 39: \ + tmp = fieldname(insn, 23, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 18, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 13, 5); \ + if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 12, 1); \ + if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 29, 3); \ + if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 28, 1); \ + if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 1, 1); \ + if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 1); \ + if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, \ + int feature) { \ + uint64_t Bits = getFeatureBits(feature); \ + uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t) fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType) decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t) decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t) decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned) decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned) decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType) decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType) decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc new file mode 100644 index 0000000..6f2dad8 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc @@ -0,0 +1,298 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + TMS320C64x_PHI = 0, + TMS320C64x_INLINEASM = 1, + TMS320C64x_CFI_INSTRUCTION = 2, + TMS320C64x_EH_LABEL = 3, + TMS320C64x_GC_LABEL = 4, + TMS320C64x_KILL = 5, + TMS320C64x_EXTRACT_SUBREG = 6, + TMS320C64x_INSERT_SUBREG = 7, + TMS320C64x_IMPLICIT_DEF = 8, + TMS320C64x_SUBREG_TO_REG = 9, + TMS320C64x_COPY_TO_REGCLASS = 10, + TMS320C64x_DBG_VALUE = 11, + TMS320C64x_REG_SEQUENCE = 12, + TMS320C64x_COPY = 13, + TMS320C64x_BUNDLE = 14, + TMS320C64x_LIFETIME_START = 15, + TMS320C64x_LIFETIME_END = 16, + TMS320C64x_STACKMAP = 17, + TMS320C64x_PATCHPOINT = 18, + TMS320C64x_LOAD_STACK_GUARD = 19, + TMS320C64x_STATEPOINT = 20, + TMS320C64x_FRAME_ALLOC = 21, + TMS320C64x_ABS2_l2_rr = 22, + TMS320C64x_ABS_l1_pp = 23, + TMS320C64x_ABS_l1_rr = 24, + TMS320C64x_ADD2_d2_rrr = 25, + TMS320C64x_ADD2_l1_rrr_x2 = 26, + TMS320C64x_ADD2_s1_rrr = 27, + TMS320C64x_ADD4_l1_rrr_x2 = 28, + TMS320C64x_ADDAB_d1_rir = 29, + TMS320C64x_ADDAB_d1_rrr = 30, + TMS320C64x_ADDAD_d1_rir = 31, + TMS320C64x_ADDAD_d1_rrr = 32, + TMS320C64x_ADDAH_d1_rir = 33, + TMS320C64x_ADDAH_d1_rrr = 34, + TMS320C64x_ADDAW_d1_rir = 35, + TMS320C64x_ADDAW_d1_rrr = 36, + TMS320C64x_ADDKPC_s3_iir = 37, + TMS320C64x_ADDK_s2_ir = 38, + TMS320C64x_ADDU_l1_rpp = 39, + TMS320C64x_ADDU_l1_rrp_x2 = 40, + TMS320C64x_ADD_d1_rir = 41, + TMS320C64x_ADD_d1_rrr = 42, + TMS320C64x_ADD_d2_rir = 43, + TMS320C64x_ADD_d2_rrr = 44, + TMS320C64x_ADD_l1_ipp = 45, + TMS320C64x_ADD_l1_irr = 46, + TMS320C64x_ADD_l1_rpp = 47, + TMS320C64x_ADD_l1_rrp_x2 = 48, + TMS320C64x_ADD_l1_rrr_x2 = 49, + TMS320C64x_ADD_s1_irr = 50, + TMS320C64x_ADD_s1_rrr = 51, + TMS320C64x_ANDN_d2_rrr = 52, + TMS320C64x_ANDN_l1_rrr_x2 = 53, + TMS320C64x_ANDN_s4_rrr = 54, + TMS320C64x_AND_d2_rir = 55, + TMS320C64x_AND_d2_rrr = 56, + TMS320C64x_AND_l1_irr = 57, + TMS320C64x_AND_l1_rrr_x2 = 58, + TMS320C64x_AND_s1_irr = 59, + TMS320C64x_AND_s1_rrr = 60, + TMS320C64x_AVG2_m1_rrr = 61, + TMS320C64x_AVGU4_m1_rrr = 62, + TMS320C64x_BDEC_s8_ir = 63, + TMS320C64x_BITC4_m2_rr = 64, + TMS320C64x_BNOP_s10_ri = 65, + TMS320C64x_BNOP_s9_ii = 66, + TMS320C64x_BPOS_s8_ir = 67, + TMS320C64x_B_s5_i = 68, + TMS320C64x_B_s6_r = 69, + TMS320C64x_B_s7_irp = 70, + TMS320C64x_B_s7_nrp = 71, + TMS320C64x_CLR_s15_riir = 72, + TMS320C64x_CLR_s1_rrr = 73, + TMS320C64x_CMPEQ2_s1_rrr = 74, + TMS320C64x_CMPEQ4_s1_rrr = 75, + TMS320C64x_CMPEQ_l1_ipr = 76, + TMS320C64x_CMPEQ_l1_irr = 77, + TMS320C64x_CMPEQ_l1_rpr = 78, + TMS320C64x_CMPEQ_l1_rrr_x2 = 79, + TMS320C64x_CMPGT2_s1_rrr = 80, + TMS320C64x_CMPGTU4_s1_rrr = 81, + TMS320C64x_CMPGT_l1_ipr = 82, + TMS320C64x_CMPGT_l1_irr = 83, + TMS320C64x_CMPGT_l1_rpr = 84, + TMS320C64x_CMPGT_l1_rrr_x2 = 85, + TMS320C64x_CMPLTU_l1_ipr = 86, + TMS320C64x_CMPLTU_l1_irr = 87, + TMS320C64x_CMPLTU_l1_rpr = 88, + TMS320C64x_CMPLTU_l1_rrr_x2 = 89, + TMS320C64x_CMPLT_l1_ipr = 90, + TMS320C64x_CMPLT_l1_irr = 91, + TMS320C64x_CMPLT_l1_rpr = 92, + TMS320C64x_CMPLT_l1_rrr_x2 = 93, + TMS320C64x_DEAL_m2_rr = 94, + TMS320C64x_DOTP2_m1_rrp = 95, + TMS320C64x_DOTP2_m1_rrr = 96, + TMS320C64x_DOTPN2_m1_rrr = 97, + TMS320C64x_DOTPNRSU2_m1_rrr = 98, + TMS320C64x_DOTPRSU2_m1_rrr = 99, + TMS320C64x_DOTPSU4_m1_rrr = 100, + TMS320C64x_DOTPU4_m1_rrr = 101, + TMS320C64x_EXTU_s15_riir = 102, + TMS320C64x_EXTU_s1_rrr = 103, + TMS320C64x_EXT_s15_riir = 104, + TMS320C64x_EXT_s1_rrr = 105, + TMS320C64x_GMPGTU_l1_ipr = 106, + TMS320C64x_GMPGTU_l1_irr = 107, + TMS320C64x_GMPGTU_l1_rpr = 108, + TMS320C64x_GMPGTU_l1_rrr_x2 = 109, + TMS320C64x_GMPY4_m1_rrr = 110, + TMS320C64x_LDBU_d5_mr = 111, + TMS320C64x_LDBU_d6_mr = 112, + TMS320C64x_LDB_d5_mr = 113, + TMS320C64x_LDB_d6_mr = 114, + TMS320C64x_LDDW_d7_mp = 115, + TMS320C64x_LDHU_d5_mr = 116, + TMS320C64x_LDHU_d6_mr = 117, + TMS320C64x_LDH_d5_mr = 118, + TMS320C64x_LDH_d6_mr = 119, + TMS320C64x_LDNDW_d8_mp = 120, + TMS320C64x_LDNW_d5_mr = 121, + TMS320C64x_LDW_d5_mr = 122, + TMS320C64x_LDW_d6_mr = 123, + TMS320C64x_LMBD_l1_irr = 124, + TMS320C64x_LMBD_l1_rrr_x2 = 125, + TMS320C64x_MAX2_l1_rrr_x2 = 126, + TMS320C64x_MAXU4_l1_rrr_x2 = 127, + TMS320C64x_MIN2_l1_rrr_x2 = 128, + TMS320C64x_MINU4_l1_rrr_x2 = 129, + TMS320C64x_MPY2_m1_rrp = 130, + TMS320C64x_MPYHIR_m1_rrr = 131, + TMS320C64x_MPYHI_m1_rrp = 132, + TMS320C64x_MPYHLU_m4_rrr = 133, + TMS320C64x_MPYHL_m4_rrr = 134, + TMS320C64x_MPYHSLU_m4_rrr = 135, + TMS320C64x_MPYHSU_m4_rrr = 136, + TMS320C64x_MPYHULS_m4_rrr = 137, + TMS320C64x_MPYHUS_m4_rrr = 138, + TMS320C64x_MPYHU_m4_rrr = 139, + TMS320C64x_MPYH_m4_rrr = 140, + TMS320C64x_MPYLHU_m4_rrr = 141, + TMS320C64x_MPYLH_m4_rrr = 142, + TMS320C64x_MPYLIR_m1_rrr = 143, + TMS320C64x_MPYLI_m1_rrp = 144, + TMS320C64x_MPYLSHU_m4_rrr = 145, + TMS320C64x_MPYLUHS_m4_rrr = 146, + TMS320C64x_MPYSU4_m1_rrp = 147, + TMS320C64x_MPYSU_m4_irr = 148, + TMS320C64x_MPYSU_m4_rrr = 149, + TMS320C64x_MPYU4_m1_rrp = 150, + TMS320C64x_MPYUS_m4_rrr = 151, + TMS320C64x_MPYU_m4_rrr = 152, + TMS320C64x_MPY_m4_irr = 153, + TMS320C64x_MPY_m4_rrr = 154, + TMS320C64x_MVC_s1_rr = 155, + TMS320C64x_MVC_s1_rr2 = 156, + TMS320C64x_MVD_m2_rr = 157, + TMS320C64x_MVKLH_s12_ir = 158, + TMS320C64x_MVKL_s12_ir = 159, + TMS320C64x_MVK_d1_rr = 160, + TMS320C64x_MVK_l2_ir = 161, + TMS320C64x_NOP_n = 162, + TMS320C64x_NORM_l1_pr = 163, + TMS320C64x_NORM_l1_rr = 164, + TMS320C64x_OR_d2_rir = 165, + TMS320C64x_OR_d2_rrr = 166, + TMS320C64x_OR_l1_irr = 167, + TMS320C64x_OR_l1_rrr_x2 = 168, + TMS320C64x_OR_s1_irr = 169, + TMS320C64x_OR_s1_rrr = 170, + TMS320C64x_PACK2_l1_rrr_x2 = 171, + TMS320C64x_PACK2_s4_rrr = 172, + TMS320C64x_PACKH2_l1_rrr_x2 = 173, + TMS320C64x_PACKH2_s1_rrr = 174, + TMS320C64x_PACKH4_l1_rrr_x2 = 175, + TMS320C64x_PACKHL2_l1_rrr_x2 = 176, + TMS320C64x_PACKHL2_s1_rrr = 177, + TMS320C64x_PACKL4_l1_rrr_x2 = 178, + TMS320C64x_PACKLH2_l1_rrr_x2 = 179, + TMS320C64x_PACKLH2_s1_rrr = 180, + TMS320C64x_ROTL_m1_rir = 181, + TMS320C64x_ROTL_m1_rrr = 182, + TMS320C64x_SADD2_s4_rrr = 183, + TMS320C64x_SADDU4_s4_rrr = 184, + TMS320C64x_SADDUS2_s4_rrr = 185, + TMS320C64x_SADD_l1_ipp = 186, + TMS320C64x_SADD_l1_irr = 187, + TMS320C64x_SADD_l1_rpp = 188, + TMS320C64x_SADD_l1_rrr_x2 = 189, + TMS320C64x_SADD_s1_rrr = 190, + TMS320C64x_SAT_l1_pr = 191, + TMS320C64x_SET_s15_riir = 192, + TMS320C64x_SET_s1_rrr = 193, + TMS320C64x_SHFL_m2_rr = 194, + TMS320C64x_SHLMB_l1_rrr_x2 = 195, + TMS320C64x_SHLMB_s4_rrr = 196, + TMS320C64x_SHL_s1_pip = 197, + TMS320C64x_SHL_s1_prp = 198, + TMS320C64x_SHL_s1_rip = 199, + TMS320C64x_SHL_s1_rir = 200, + TMS320C64x_SHL_s1_rrp = 201, + TMS320C64x_SHL_s1_rrr = 202, + TMS320C64x_SHR2_s1_rir = 203, + TMS320C64x_SHR2_s4_rrr = 204, + TMS320C64x_SHRMB_l1_rrr_x2 = 205, + TMS320C64x_SHRMB_s4_rrr = 206, + TMS320C64x_SHRU2_s1_rir = 207, + TMS320C64x_SHRU2_s4_rrr = 208, + TMS320C64x_SHRU_s1_pip = 209, + TMS320C64x_SHRU_s1_prp = 210, + TMS320C64x_SHRU_s1_rir = 211, + TMS320C64x_SHRU_s1_rrr = 212, + TMS320C64x_SHR_s1_pip = 213, + TMS320C64x_SHR_s1_prp = 214, + TMS320C64x_SHR_s1_rir = 215, + TMS320C64x_SHR_s1_rrr = 216, + TMS320C64x_SMPY2_m1_rrp = 217, + TMS320C64x_SMPYHL_m4_rrr = 218, + TMS320C64x_SMPYH_m4_rrr = 219, + TMS320C64x_SMPYLH_m4_rrr = 220, + TMS320C64x_SMPY_m4_rrr = 221, + TMS320C64x_SPACK2_s4_rrr = 222, + TMS320C64x_SPACKU4_s4_rrr = 223, + TMS320C64x_SSHL_s1_rir = 224, + TMS320C64x_SSHL_s1_rrr = 225, + TMS320C64x_SSHVL_m1_rrr = 226, + TMS320C64x_SSHVR_m1_rrr = 227, + TMS320C64x_SSUB_l1_ipp = 228, + TMS320C64x_SSUB_l1_irr = 229, + TMS320C64x_SSUB_l1_rrr_x1 = 230, + TMS320C64x_SSUB_l1_rrr_x2 = 231, + TMS320C64x_STB_d5_rm = 232, + TMS320C64x_STB_d6_rm = 233, + TMS320C64x_STDW_d7_pm = 234, + TMS320C64x_STH_d5_rm = 235, + TMS320C64x_STH_d6_rm = 236, + TMS320C64x_STNDW_d8_pm = 237, + TMS320C64x_STNW_d5_rm = 238, + TMS320C64x_STW_d5_rm = 239, + TMS320C64x_STW_d6_rm = 240, + TMS320C64x_SUB2_d2_rrr = 241, + TMS320C64x_SUB2_l1_rrr_x2 = 242, + TMS320C64x_SUB2_s1_rrr = 243, + TMS320C64x_SUB4_l1_rrr_x2 = 244, + TMS320C64x_SUBABS4_l1_rrr_x2 = 245, + TMS320C64x_SUBAB_d1_rir = 246, + TMS320C64x_SUBAB_d1_rrr = 247, + TMS320C64x_SUBAH_d1_rir = 248, + TMS320C64x_SUBAH_d1_rrr = 249, + TMS320C64x_SUBAW_d1_rir = 250, + TMS320C64x_SUBAW_d1_rrr = 251, + TMS320C64x_SUBC_l1_rrr_x2 = 252, + TMS320C64x_SUBU_l1_rrp_x1 = 253, + TMS320C64x_SUBU_l1_rrp_x2 = 254, + TMS320C64x_SUB_d1_rir = 255, + TMS320C64x_SUB_d1_rrr = 256, + TMS320C64x_SUB_d2_rrr = 257, + TMS320C64x_SUB_l1_ipp = 258, + TMS320C64x_SUB_l1_irr = 259, + TMS320C64x_SUB_l1_rrp_x1 = 260, + TMS320C64x_SUB_l1_rrp_x2 = 261, + TMS320C64x_SUB_l1_rrr_x1 = 262, + TMS320C64x_SUB_l1_rrr_x2 = 263, + TMS320C64x_SUB_s1_irr = 264, + TMS320C64x_SUB_s1_rrr = 265, + TMS320C64x_SUB_s4_rrr = 266, + TMS320C64x_SWAP4_l2_rr = 267, + TMS320C64x_UNPKHU4_l2_rr = 268, + TMS320C64x_UNPKHU4_s14_rr = 269, + TMS320C64x_UNPKLU4_l2_rr = 270, + TMS320C64x_UNPKLU4_s14_rr = 271, + TMS320C64x_XOR_d2_rir = 272, + TMS320C64x_XOR_d2_rrr = 273, + TMS320C64x_XOR_l1_irr = 274, + TMS320C64x_XOR_l1_rrr_x2 = 275, + TMS320C64x_XOR_s1_irr = 276, + TMS320C64x_XOR_s1_rrr = 277, + TMS320C64x_XPND2_m2_rr = 278, + TMS320C64x_XPND4_m2_rr = 279, + TMS320C64x_INSTRUCTION_LIST_END = 280 +}; + +#endif // GET_INSTRINFO_ENUM + diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc new file mode 100644 index 0000000..a15d840 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc @@ -0,0 +1,278 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + TMS320C64x_NoRegister, + TMS320C64x_AMR = 1, + TMS320C64x_CSR = 2, + TMS320C64x_DIER = 3, + TMS320C64x_DNUM = 4, + TMS320C64x_ECR = 5, + TMS320C64x_GFPGFR = 6, + TMS320C64x_GPLYA = 7, + TMS320C64x_GPLYB = 8, + TMS320C64x_ICR = 9, + TMS320C64x_IER = 10, + TMS320C64x_IERR = 11, + TMS320C64x_ILC = 12, + TMS320C64x_IRP = 13, + TMS320C64x_ISR = 14, + TMS320C64x_ISTP = 15, + TMS320C64x_ITSR = 16, + TMS320C64x_NRP = 17, + TMS320C64x_NTSR = 18, + TMS320C64x_REP = 19, + TMS320C64x_RILC = 20, + TMS320C64x_SSR = 21, + TMS320C64x_TSCH = 22, + TMS320C64x_TSCL = 23, + TMS320C64x_TSR = 24, + TMS320C64x_A0 = 25, + TMS320C64x_A1 = 26, + TMS320C64x_A2 = 27, + TMS320C64x_A3 = 28, + TMS320C64x_A4 = 29, + TMS320C64x_A5 = 30, + TMS320C64x_A6 = 31, + TMS320C64x_A7 = 32, + TMS320C64x_A8 = 33, + TMS320C64x_A9 = 34, + TMS320C64x_A10 = 35, + TMS320C64x_A11 = 36, + TMS320C64x_A12 = 37, + TMS320C64x_A13 = 38, + TMS320C64x_A14 = 39, + TMS320C64x_A15 = 40, + TMS320C64x_A16 = 41, + TMS320C64x_A17 = 42, + TMS320C64x_A18 = 43, + TMS320C64x_A19 = 44, + TMS320C64x_A20 = 45, + TMS320C64x_A21 = 46, + TMS320C64x_A22 = 47, + TMS320C64x_A23 = 48, + TMS320C64x_A24 = 49, + TMS320C64x_A25 = 50, + TMS320C64x_A26 = 51, + TMS320C64x_A27 = 52, + TMS320C64x_A28 = 53, + TMS320C64x_A29 = 54, + TMS320C64x_A30 = 55, + TMS320C64x_A31 = 56, + TMS320C64x_B0 = 57, + TMS320C64x_B1 = 58, + TMS320C64x_B2 = 59, + TMS320C64x_B3 = 60, + TMS320C64x_B4 = 61, + TMS320C64x_B5 = 62, + TMS320C64x_B6 = 63, + TMS320C64x_B7 = 64, + TMS320C64x_B8 = 65, + TMS320C64x_B9 = 66, + TMS320C64x_B10 = 67, + TMS320C64x_B11 = 68, + TMS320C64x_B12 = 69, + TMS320C64x_B13 = 70, + TMS320C64x_B14 = 71, + TMS320C64x_B15 = 72, + TMS320C64x_B16 = 73, + TMS320C64x_B17 = 74, + TMS320C64x_B18 = 75, + TMS320C64x_B19 = 76, + TMS320C64x_B20 = 77, + TMS320C64x_B21 = 78, + TMS320C64x_B22 = 79, + TMS320C64x_B23 = 80, + TMS320C64x_B24 = 81, + TMS320C64x_B25 = 82, + TMS320C64x_B26 = 83, + TMS320C64x_B27 = 84, + TMS320C64x_B28 = 85, + TMS320C64x_B29 = 86, + TMS320C64x_B30 = 87, + TMS320C64x_B31 = 88, + TMS320C64x_PCE1 = 89, + TMS320C64x_NUM_TARGET_REGS // 90 +}; + +// Register classes +enum { + TMS320C64x_GPRegsRegClassID = 0, + TMS320C64x_AFRegsRegClassID = 1, + TMS320C64x_BFRegsRegClassID = 2, + TMS320C64x_ControlRegsRegClassID = 3, + + }; +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static MCPhysReg TMS320C64xRegDiffLists[] = { + /* 0 */ 65535, 0, +}; + +static uint16_t TMS320C64xSubRegIdxLists[] = { + /* 0 */ 0, +}; + +static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0 }, + { 310, 1, 1, 0, 1 }, + { 319, 1, 1, 0, 1 }, + { 298, 1, 1, 0, 1 }, + { 268, 1, 1, 0, 1 }, + { 290, 1, 1, 0, 1 }, + { 303, 1, 1, 0, 1 }, + { 241, 1, 1, 0, 1 }, + { 247, 1, 1, 0, 1 }, + { 294, 1, 1, 0, 1 }, + { 299, 1, 1, 0, 1 }, + { 314, 1, 1, 0, 1 }, + { 254, 1, 1, 0, 1 }, + { 277, 1, 1, 0, 1 }, + { 323, 1, 1, 0, 1 }, + { 285, 1, 1, 0, 1 }, + { 331, 1, 1, 0, 1 }, + { 281, 1, 1, 0, 1 }, + { 336, 1, 1, 0, 1 }, + { 273, 1, 1, 0, 1 }, + { 253, 1, 1, 0, 1 }, + { 327, 1, 1, 0, 1 }, + { 258, 1, 1, 0, 1 }, + { 263, 1, 1, 0, 1 }, + { 332, 1, 1, 0, 1 }, + { 24, 1, 1, 0, 1 }, + { 54, 1, 1, 0, 1 }, + { 81, 1, 1, 0, 1 }, + { 103, 1, 1, 0, 1 }, + { 125, 1, 1, 0, 1 }, + { 147, 1, 1, 0, 1 }, + { 169, 1, 1, 0, 1 }, + { 191, 1, 1, 0, 1 }, + { 213, 1, 1, 0, 1 }, + { 235, 1, 1, 0, 1 }, + { 0, 1, 1, 0, 1 }, + { 30, 1, 1, 0, 1 }, + { 65, 1, 1, 0, 1 }, + { 87, 1, 1, 0, 1 }, + { 109, 1, 1, 0, 1 }, + { 131, 1, 1, 0, 1 }, + { 153, 1, 1, 0, 1 }, + { 175, 1, 1, 0, 1 }, + { 197, 1, 1, 0, 1 }, + { 219, 1, 1, 0, 1 }, + { 8, 1, 1, 0, 1 }, + { 38, 1, 1, 0, 1 }, + { 73, 1, 1, 0, 1 }, + { 95, 1, 1, 0, 1 }, + { 117, 1, 1, 0, 1 }, + { 139, 1, 1, 0, 1 }, + { 161, 1, 1, 0, 1 }, + { 183, 1, 1, 0, 1 }, + { 205, 1, 1, 0, 1 }, + { 227, 1, 1, 0, 1 }, + { 16, 1, 1, 0, 1 }, + { 46, 1, 1, 0, 1 }, + { 27, 1, 1, 0, 1 }, + { 57, 1, 1, 0, 1 }, + { 84, 1, 1, 0, 1 }, + { 106, 1, 1, 0, 1 }, + { 128, 1, 1, 0, 1 }, + { 150, 1, 1, 0, 1 }, + { 172, 1, 1, 0, 1 }, + { 194, 1, 1, 0, 1 }, + { 216, 1, 1, 0, 1 }, + { 238, 1, 1, 0, 1 }, + { 4, 1, 1, 0, 1 }, + { 34, 1, 1, 0, 1 }, + { 69, 1, 1, 0, 1 }, + { 91, 1, 1, 0, 1 }, + { 113, 1, 1, 0, 1 }, + { 135, 1, 1, 0, 1 }, + { 157, 1, 1, 0, 1 }, + { 179, 1, 1, 0, 1 }, + { 201, 1, 1, 0, 1 }, + { 223, 1, 1, 0, 1 }, + { 12, 1, 1, 0, 1 }, + { 42, 1, 1, 0, 1 }, + { 77, 1, 1, 0, 1 }, + { 99, 1, 1, 0, 1 }, + { 121, 1, 1, 0, 1 }, + { 143, 1, 1, 0, 1 }, + { 165, 1, 1, 0, 1 }, + { 187, 1, 1, 0, 1 }, + { 209, 1, 1, 0, 1 }, + { 231, 1, 1, 0, 1 }, + { 20, 1, 1, 0, 1 }, + { 50, 1, 1, 0, 1 }, + { 60, 1, 1, 0, 1 }, +}; + +// GPRegs Register Class... +static MCPhysReg GPRegs[] = { + TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, +}; + +// GPRegs Bit set. +static uint8_t GPRegsBits[] = { + 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, +}; + +// AFRegs Register Class... +static MCPhysReg AFRegs[] = { + TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, +}; + +// AFRegs Bit set. +static uint8_t AFRegsBits[] = { + 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// BFRegs Register Class... +static MCPhysReg BFRegs[] = { + TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, +}; + +// BFRegs Bit set. +static uint8_t BFRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// ControlRegs Register Class... +static MCPhysReg ControlRegs[] = { + TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR, +}; + +// ControlRegs Bit set. +static uint8_t ControlRegsBits[] = { + 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, +}; + +static MCRegisterClass TMS320C64xMCRegisterClasses[] = { + { GPRegs, GPRegsBits, 64, sizeof(GPRegsBits), TMS320C64x_GPRegsRegClassID, 4, 4, 1, 1 }, + { AFRegs, AFRegsBits, 32, sizeof(AFRegsBits), TMS320C64x_AFRegsRegClassID, 4, 4, 1, 1 }, + { BFRegs, BFRegsBits, 32, sizeof(BFRegsBits), TMS320C64x_BFRegsRegClassID, 4, 4, 1, 1 }, + { ControlRegs, ControlRegsBits, 25, sizeof(ControlRegsBits), TMS320C64x_ControlRegsRegClassID, 4, 4, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC + diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.c b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.c new file mode 100644 index 0000000..6e1b434 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.c @@ -0,0 +1,574 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifdef CAPSTONE_HAS_TMS320C64X + +#ifdef _MSC_VER +// Disable security warnings for strcpy +#ifndef _CRT_SECURE_NO_WARNINGS +#define _CRT_SECURE_NO_WARNINGS +#endif + +// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for +// security purposes. +#pragma warning(disable:28719) +#endif + +#include +#include + +#include "TMS320C64xInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "TMS320C64xMapping.h" + +#include "capstone/tms320c64x.h" + +static char *getRegisterName(unsigned RegNo); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O); +static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O); + +void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + SStream ss; + char *p, *p2, tmp[8]; + unsigned int unit = 0; + int i; + cs_tms320c64x *tms320c64x; + + if (mci->csh->detail) { + tms320c64x = &mci->flat_insn->detail->tms320c64x; + + for (i = 0; i < insn->detail->groups_count; i++) { + switch(insn->detail->groups[i]) { + case TMS320C64X_GRP_FUNIT_D: + unit = TMS320C64X_FUNIT_D; + break; + case TMS320C64X_GRP_FUNIT_L: + unit = TMS320C64X_FUNIT_L; + break; + case TMS320C64X_GRP_FUNIT_M: + unit = TMS320C64X_FUNIT_M; + break; + case TMS320C64X_GRP_FUNIT_S: + unit = TMS320C64X_FUNIT_S; + break; + case TMS320C64X_GRP_FUNIT_NO: + unit = TMS320C64X_FUNIT_NO; + break; + } + if (unit != 0) + break; + } + tms320c64x->funit.unit = unit; + + SStream_Init(&ss); + if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) + SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg)); + else + SStream_concat0(&ss, "||||||"); + + p = strchr(insn_asm, '\t'); + if (p != NULL) + *p++ = '\0'; + + SStream_concat0(&ss, insn_asm); + if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) { + while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b'))) + p2--; + if (p2 == p) { + strcpy(insn_asm, "Invalid!"); + return; + } + if (*p2 == 'a') + strcpy(tmp, "1T"); + else + strcpy(tmp, "2T"); + } else { + tmp[0] = '\0'; + } + switch(tms320c64x->funit.unit) { + case TMS320C64X_FUNIT_D: + SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_L: + SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_M: + SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_S: + SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side); + break; + } + if (tms320c64x->funit.crosspath > 0) + SStream_concat0(&ss, "X"); + + if (p != NULL) + SStream_concat(&ss, "\t%s", p); + + if (tms320c64x->parallel != 0) + SStream_concat(&ss, "\t||"); + + /* insn_asm is a buffer from an SStream, so there should be enough space */ + strcpy(insn_asm, ss.buffer); + } +} + +#define PRINT_ALIAS_INSTR +#include "TMS320C64xGenAsmWriter.inc" + +#define GET_INSTRINFO_ENUM +#include "TMS320C64xGenInstrInfo.inc" + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + unsigned reg; + + if (MCOperand_isReg(Op)) { + reg = MCOperand_getReg(Op); + if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) { + switch(reg) { + case TMS320C64X_REG_EFR: + SStream_concat0(O, "EFR"); + break; + case TMS320C64X_REG_IFR: + SStream_concat0(O, "IFR"); + break; + default: + SStream_concat0(O, getRegisterName(reg)); + break; + } + } else { + SStream_concat0(O, getRegisterName(reg)); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG; + MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg; + MI->flat_insn->detail->tms320c64x.op_count++; + } + } else if (MCOperand_isImm(Op)) { + int64_t Imm = MCOperand_getImm(Op); + + if (Imm >= 0) { + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%"PRIx64, Imm); + else + SStream_concat(O, "%"PRIu64, Imm); + } else { + if (Imm < -HEX_THRESHOLD) + SStream_concat(O, "-0x%"PRIx64, -Imm); + else + SStream_concat(O, "-%"PRIu64, -Imm); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM; + MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm; + MI->flat_insn->detail->tms320c64x.op_count++; + } + } +} + +static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + int64_t Val = MCOperand_getImm(Op); + unsigned scaled, base, offset, mode, unit; + cs_tms320c64x *tms320c64x; + char st, nd; + + scaled = (Val >> 19) & 1; + base = (Val >> 12) & 0x7f; + offset = (Val >> 5) & 0x7f; + mode = (Val >> 1) & 0xf; + unit = Val & 1; + + if (scaled) { + st = '['; + nd = ']'; + } else { + st = '('; + nd = ')'; + } + + switch(mode) { + case 0: + SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 1: + SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 4: + SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + case 5: + SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + case 8: + SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 9: + SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 10: + SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 11: + SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd); + break; + case 12: + SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + case 13: + SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + case 14: + SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + case 15: + SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); + break; + } + + if (MI->csh->detail) { + tms320c64x = &MI->flat_insn->detail->tms320c64x; + + tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM; + tms320c64x->operands[tms320c64x->op_count].mem.base = base; + tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; + tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1; + tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled; + switch(mode) { + case 0: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; + break; + case 1: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; + break; + case 4: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; + break; + case 5: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; + break; + case 8: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; + break; + case 9: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; + break; + case 10: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; + break; + case 11: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; + break; + case 12: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; + break; + case 13: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; + break; + case 14: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; + break; + case 15: + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; + break; + } + tms320c64x->op_count++; + } +} + +static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + int64_t Val = MCOperand_getImm(Op); + uint16_t offset; + unsigned basereg; + cs_tms320c64x *tms320c64x; + + basereg = Val & 0x7f; + offset = (Val >> 7) & 0x7fff; + SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset); + + if (MI->csh->detail) { + tms320c64x = &MI->flat_insn->detail->tms320c64x; + + tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM; + tms320c64x->operands[tms320c64x->op_count].mem.base = basereg; + tms320c64x->operands[tms320c64x->op_count].mem.unit = 2; + tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; + tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; + tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; + tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; + tms320c64x->op_count++; + } +} + +static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNo); + unsigned reg = MCOperand_getReg(Op); + cs_tms320c64x *tms320c64x; + + SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg)); + + if (MI->csh->detail) { + tms320c64x = &MI->flat_insn->detail->tms320c64x; + + tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR; + tms320c64x->operands[tms320c64x->op_count].reg = reg; + tms320c64x->op_count++; + } +} + +static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ + unsigned opcode = MCInst_getOpcode(MI); + MCOperand *op; + + switch(opcode) { + /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */ + case TMS320C64x_ADD_d2_rir: + /* ADD.L -i, x, y -> SUB.L x, i, y */ + case TMS320C64x_ADD_l1_irr: + case TMS320C64x_ADD_l1_ipp: + /* ADD.S -i, x, y -> SUB.S x, i, y */ + case TMS320C64x_ADD_s1_irr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB); + op = MCInst_getOperand(MI, 2); + MCOperand_setImm(op, -MCOperand_getImm(op)); + + SStream_concat0(O, "SUB\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* ADD.D 0, x, y -> MV.D x, y */ + case TMS320C64x_ADD_d1_rir: + /* OR.D x, 0, y -> MV.D x, y */ + case TMS320C64x_OR_d2_rir: + /* ADD.L 0, x, y -> MV.L x, y */ + case TMS320C64x_ADD_l1_irr: + case TMS320C64x_ADD_l1_ipp: + /* OR.L 0, x, y -> MV.L x, y */ + case TMS320C64x_OR_l1_irr: + /* ADD.S 0, x, y -> MV.S x, y */ + case TMS320C64x_ADD_s1_irr: + /* OR.S 0, x, y -> MV.S x, y */ + case TMS320C64x_OR_s1_irr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_MV); + MI->size--; + + SStream_concat0(O, "MV\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* XOR.D -1, x, y -> NOT.D x, y */ + case TMS320C64x_XOR_d2_rir: + /* XOR.L -1, x, y -> NOT.L x, y */ + case TMS320C64x_XOR_l1_irr: + /* XOR.S -1, x, y -> NOT.S x, y */ + case TMS320C64x_XOR_s1_irr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT); + MI->size--; + + SStream_concat0(O, "NOT\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* MVK.D 0, x -> ZERO.D x */ + case TMS320C64x_MVK_d1_rr: + /* MVK.L 0, x -> ZERO.L x */ + case TMS320C64x_MVK_l2_ir: + if ((MCInst_getNumOperands(MI) == 2) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); + MI->size--; + + SStream_concat0(O, "ZERO\t"); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* SUB.L x, x, y -> ZERO.L y */ + case TMS320C64x_SUB_l1_rrp_x1: + /* SUB.S x, x, y -> ZERO.S y */ + case TMS320C64x_SUB_s1_rrr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); + MI->size -= 2; + + SStream_concat0(O, "ZERO\t"); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* SUB.L 0, x, y -> NEG.L x, y */ + case TMS320C64x_SUB_l1_irr: + case TMS320C64x_SUB_l1_ipp: + /* SUB.S 0, x, y -> NEG.S x, y */ + case TMS320C64x_SUB_s1_irr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG); + MI->size--; + + SStream_concat0(O, "NEG\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* PACKLH2.L x, x, y -> SWAP2.L x, y */ + case TMS320C64x_PACKLH2_l1_rrr_x2: + /* PACKLH2.S x, x, y -> SWAP2.S x, y */ + case TMS320C64x_PACKLH2_s1_rrr: + if ((MCInst_getNumOperands(MI) == 3) && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2); + MI->size--; + + SStream_concat0(O, "SWAP2\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + + return true; + } + break; + } + switch(opcode) { + /* NOP 16 -> IDLE */ + /* NOP 1 -> NOP */ + case TMS320C64x_NOP_n: + if ((MCInst_getNumOperands(MI) == 1) && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) { + + MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE); + MI->size--; + + SStream_concat0(O, "IDLE"); + + return true; + } + if ((MCInst_getNumOperands(MI) == 1) && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) { + + MI->size--; + + SStream_concat0(O, "NOP"); + + return true; + } + break; + } + + return false; +} + +void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info) +{ + if (!printAliasInstruction(MI, O, Info)) + printInstruction(MI, O, Info); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.h b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.h new file mode 100644 index 0000000..3a79139 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xInstPrinter.h @@ -0,0 +1,15 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifndef CS_TMS320C64XINSTPRINTER_H +#define CS_TMS320C64XINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info); + +void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.c b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.c new file mode 100644 index 0000000..eb30614 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.c @@ -0,0 +1,1926 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifdef CAPSTONE_HAS_TMS320C64X + +#include // debug +#include + +#include "../../utils.h" + +#include "TMS320C64xMapping.h" + +#define GET_INSTRINFO_ENUM +#include "TMS320C64xGenInstrInfo.inc" + +static name_map reg_name_maps[] = { + { TMS320C64X_REG_INVALID, NULL }, + + { TMS320C64X_REG_AMR, "amr" }, + { TMS320C64X_REG_CSR, "csr" }, + { TMS320C64X_REG_DIER, "dier" }, + { TMS320C64X_REG_DNUM, "dnum" }, + { TMS320C64X_REG_ECR, "ecr" }, + { TMS320C64X_REG_GFPGFR, "gfpgfr" }, + { TMS320C64X_REG_GPLYA, "gplya" }, + { TMS320C64X_REG_GPLYB, "gplyb" }, + { TMS320C64X_REG_ICR, "icr" }, + { TMS320C64X_REG_IER, "ier" }, + { TMS320C64X_REG_IERR, "ierr" }, + { TMS320C64X_REG_ILC, "ilc" }, + { TMS320C64X_REG_IRP, "irp" }, + { TMS320C64X_REG_ISR, "isr" }, + { TMS320C64X_REG_ISTP, "istp" }, + { TMS320C64X_REG_ITSR, "itsr" }, + { TMS320C64X_REG_NRP, "nrp" }, + { TMS320C64X_REG_NTSR, "ntsr" }, + { TMS320C64X_REG_REP, "rep" }, + { TMS320C64X_REG_RILC, "rilc" }, + { TMS320C64X_REG_SSR, "ssr" }, + { TMS320C64X_REG_TSCH, "tsch" }, + { TMS320C64X_REG_TSCL, "tscl" }, + { TMS320C64X_REG_TSR, "tsr" }, + { TMS320C64X_REG_A0, "a0" }, + { TMS320C64X_REG_A1, "a1" }, + { TMS320C64X_REG_A2, "a2" }, + { TMS320C64X_REG_A3, "a3" }, + { TMS320C64X_REG_A4, "a4" }, + { TMS320C64X_REG_A5, "a5" }, + { TMS320C64X_REG_A6, "a6" }, + { TMS320C64X_REG_A7, "a7" }, + { TMS320C64X_REG_A8, "a8" }, + { TMS320C64X_REG_A9, "a9" }, + { TMS320C64X_REG_A10, "a10" }, + { TMS320C64X_REG_A11, "a11" }, + { TMS320C64X_REG_A12, "a12" }, + { TMS320C64X_REG_A13, "a13" }, + { TMS320C64X_REG_A14, "a14" }, + { TMS320C64X_REG_A15, "a15" }, + { TMS320C64X_REG_A16, "a16" }, + { TMS320C64X_REG_A17, "a17" }, + { TMS320C64X_REG_A18, "a18" }, + { TMS320C64X_REG_A19, "a19" }, + { TMS320C64X_REG_A20, "a20" }, + { TMS320C64X_REG_A21, "a21" }, + { TMS320C64X_REG_A22, "a22" }, + { TMS320C64X_REG_A23, "a23" }, + { TMS320C64X_REG_A24, "a24" }, + { TMS320C64X_REG_A25, "a25" }, + { TMS320C64X_REG_A26, "a26" }, + { TMS320C64X_REG_A27, "a27" }, + { TMS320C64X_REG_A28, "a28" }, + { TMS320C64X_REG_A29, "a29" }, + { TMS320C64X_REG_A30, "a30" }, + { TMS320C64X_REG_A31, "a31" }, + { TMS320C64X_REG_B0, "b0" }, + { TMS320C64X_REG_B1, "b1" }, + { TMS320C64X_REG_B2, "b2" }, + { TMS320C64X_REG_B3, "b3" }, + { TMS320C64X_REG_B4, "b4" }, + { TMS320C64X_REG_B5, "b5" }, + { TMS320C64X_REG_B6, "b6" }, + { TMS320C64X_REG_B7, "b7" }, + { TMS320C64X_REG_B8, "b8" }, + { TMS320C64X_REG_B9, "b9" }, + { TMS320C64X_REG_B10, "b10" }, + { TMS320C64X_REG_B11, "b11" }, + { TMS320C64X_REG_B12, "b12" }, + { TMS320C64X_REG_B13, "b13" }, + { TMS320C64X_REG_B14, "b14" }, + { TMS320C64X_REG_B15, "b15" }, + { TMS320C64X_REG_B16, "b16" }, + { TMS320C64X_REG_B17, "b17" }, + { TMS320C64X_REG_B18, "b18" }, + { TMS320C64X_REG_B19, "b19" }, + { TMS320C64X_REG_B20, "b20" }, + { TMS320C64X_REG_B21, "b21" }, + { TMS320C64X_REG_B22, "b22" }, + { TMS320C64X_REG_B23, "b23" }, + { TMS320C64X_REG_B24, "b24" }, + { TMS320C64X_REG_B25, "b25" }, + { TMS320C64X_REG_B26, "b26" }, + { TMS320C64X_REG_B27, "b27" }, + { TMS320C64X_REG_B28, "b28" }, + { TMS320C64X_REG_B29, "b29" }, + { TMS320C64X_REG_B30, "b30" }, + { TMS320C64X_REG_B31, "b31" }, + { TMS320C64X_REG_PCE1, "pce1" }, +}; + +const char *TMS320C64x_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +tms320c64x_reg TMS320C64x_reg_id(char *name) +{ + int i; + + for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { + if (!strcmp(name, reg_name_maps[i].name)) + return reg_name_maps[i].id; + } + + return 0; +} + +static insn_map insns[] = { + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + + { + TMS320C64x_ABS2_l2_rr, TMS320C64X_INS_ABS2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ABS_l1_pp, TMS320C64X_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ABS_l1_rr, TMS320C64X_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD2_d2_rrr, TMS320C64X_INS_ADD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD2_l1_rrr_x2, TMS320C64X_INS_ADD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD2_s1_rrr, TMS320C64X_INS_ADD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD4_l1_rrr_x2, TMS320C64X_INS_ADD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAB_d1_rir, TMS320C64X_INS_ADDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAB_d1_rrr, TMS320C64X_INS_ADDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAD_d1_rir, TMS320C64X_INS_ADDAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAD_d1_rrr, TMS320C64X_INS_ADDAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAH_d1_rir, TMS320C64X_INS_ADDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAH_d1_rrr, TMS320C64X_INS_ADDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAW_d1_rir, TMS320C64X_INS_ADDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDAW_d1_rrr, TMS320C64X_INS_ADDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDKPC_s3_iir, TMS320C64X_INS_ADDKPC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDK_s2_ir, TMS320C64X_INS_ADDK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDU_l1_rpp, TMS320C64X_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADDU_l1_rrp_x2, TMS320C64X_INS_ADDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_d1_rir, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_d1_rrr, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_d2_rir, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_d2_rrr, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_l1_ipp, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_l1_irr, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_l1_rpp, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_l1_rrp_x2, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_l1_rrr_x2, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_s1_irr, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ADD_s1_rrr, TMS320C64X_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ANDN_d2_rrr, TMS320C64X_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ANDN_l1_rrr_x2, TMS320C64X_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ANDN_s4_rrr, TMS320C64X_INS_ANDN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_d2_rir, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_d2_rrr, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_l1_irr, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_l1_rrr_x2, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_s1_irr, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AND_s1_rrr, TMS320C64X_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AVG2_m1_rrr, TMS320C64X_INS_AVG2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_AVGU4_m1_rrr, TMS320C64X_INS_AVGU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_BDEC_s8_ir, TMS320C64X_INS_BDEC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_BITC4_m2_rr, TMS320C64X_INS_BITC4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_BNOP_s10_ri, TMS320C64X_INS_BNOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_BNOP_s9_ii, TMS320C64X_INS_BNOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_BPOS_s8_ir, TMS320C64X_INS_BPOS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_B_s5_i, TMS320C64X_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_B_s6_r, TMS320C64X_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_B_s7_irp, TMS320C64X_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_B_s7_nrp, TMS320C64X_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 +#endif + }, + { + TMS320C64x_CLR_s15_riir, TMS320C64X_INS_CLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CLR_s1_rrr, TMS320C64X_INS_CLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ2_s1_rrr, TMS320C64X_INS_CMPEQ2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ4_s1_rrr, TMS320C64X_INS_CMPEQ4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ_l1_ipr, TMS320C64X_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ_l1_irr, TMS320C64X_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ_l1_rpr, TMS320C64X_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPEQ_l1_rrr_x2, TMS320C64X_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGT2_s1_rrr, TMS320C64X_INS_CMPGT2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGTU4_s1_rrr, TMS320C64X_INS_CMPGTU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGT_l1_ipr, TMS320C64X_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGT_l1_irr, TMS320C64X_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGT_l1_rpr, TMS320C64X_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPGT_l1_rrr_x2, TMS320C64X_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLTU_l1_ipr, TMS320C64X_INS_CMPLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLTU_l1_irr, TMS320C64X_INS_CMPLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLTU_l1_rpr, TMS320C64X_INS_CMPLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLTU_l1_rrr_x2, TMS320C64X_INS_CMPLTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLT_l1_ipr, TMS320C64X_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLT_l1_irr, TMS320C64X_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLT_l1_rpr, TMS320C64X_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_CMPLT_l1_rrr_x2, TMS320C64X_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DEAL_m2_rr, TMS320C64X_INS_DEAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTP2_m1_rrp, TMS320C64X_INS_DOTP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTP2_m1_rrr, TMS320C64X_INS_DOTP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTPN2_m1_rrr, TMS320C64X_INS_DOTPN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTPNRSU2_m1_rrr, TMS320C64X_INS_DOTPNRSU2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTPRSU2_m1_rrr, TMS320C64X_INS_DOTPRSU2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTPSU4_m1_rrr, TMS320C64X_INS_DOTPSU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_DOTPU4_m1_rrr, TMS320C64X_INS_DOTPU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_EXTU_s15_riir, TMS320C64X_INS_EXTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_EXTU_s1_rrr, TMS320C64X_INS_EXTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_EXT_s15_riir, TMS320C64X_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_EXT_s1_rrr, TMS320C64X_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_GMPGTU_l1_ipr, TMS320C64X_INS_GMPGTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_GMPGTU_l1_irr, TMS320C64X_INS_GMPGTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_GMPGTU_l1_rpr, TMS320C64X_INS_GMPGTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_GMPGTU_l1_rrr_x2, TMS320C64X_INS_GMPGTU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_GMPY4_m1_rrr, TMS320C64X_INS_GMPY4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDBU_d5_mr, TMS320C64X_INS_LDBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDBU_d6_mr, TMS320C64X_INS_LDBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDB_d5_mr, TMS320C64X_INS_LDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDB_d6_mr, TMS320C64X_INS_LDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDDW_d7_mp, TMS320C64X_INS_LDDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDHU_d5_mr, TMS320C64X_INS_LDHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDHU_d6_mr, TMS320C64X_INS_LDHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDH_d5_mr, TMS320C64X_INS_LDH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDH_d6_mr, TMS320C64X_INS_LDH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDNDW_d8_mp, TMS320C64X_INS_LDNDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDNW_d5_mr, TMS320C64X_INS_LDNW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDW_d5_mr, TMS320C64X_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LDW_d6_mr, TMS320C64X_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LMBD_l1_irr, TMS320C64X_INS_LMBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_LMBD_l1_rrr_x2, TMS320C64X_INS_LMBD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MAX2_l1_rrr_x2, TMS320C64X_INS_MAX2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MAXU4_l1_rrr_x2, TMS320C64X_INS_MAXU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MIN2_l1_rrr_x2, TMS320C64X_INS_MIN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MINU4_l1_rrr_x2, TMS320C64X_INS_MINU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPY2_m1_rrp, TMS320C64X_INS_MPY2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHIR_m1_rrr, TMS320C64X_INS_MPYHIR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHI_m1_rrp, TMS320C64X_INS_MPYHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHLU_m4_rrr, TMS320C64X_INS_MPYHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHL_m4_rrr, TMS320C64X_INS_MPYHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHSLU_m4_rrr, TMS320C64X_INS_MPYHSLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHSU_m4_rrr, TMS320C64X_INS_MPYHSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHULS_m4_rrr, TMS320C64X_INS_MPYHULS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHUS_m4_rrr, TMS320C64X_INS_MPYHUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYHU_m4_rrr, TMS320C64X_INS_MPYHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYH_m4_rrr, TMS320C64X_INS_MPYH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLHU_m4_rrr, TMS320C64X_INS_MPYLHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLH_m4_rrr, TMS320C64X_INS_MPYLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLIR_m1_rrr, TMS320C64X_INS_MPYLIR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLI_m1_rrp, TMS320C64X_INS_MPYLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLSHU_m4_rrr, TMS320C64X_INS_MPYLSHU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYLUHS_m4_rrr, TMS320C64X_INS_MPYLUHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYSU4_m1_rrp, TMS320C64X_INS_MPYSU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYSU_m4_irr, TMS320C64X_INS_MPYSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYSU_m4_rrr, TMS320C64X_INS_MPYSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYU4_m1_rrp, TMS320C64X_INS_MPYU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYUS_m4_rrr, TMS320C64X_INS_MPYUS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPYU_m4_rrr, TMS320C64X_INS_MPYU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPY_m4_irr, TMS320C64X_INS_MPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MPY_m4_rrr, TMS320C64X_INS_MPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVC_s1_rr, TMS320C64X_INS_MVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVC_s1_rr2, TMS320C64X_INS_MVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVD_m2_rr, TMS320C64X_INS_MVD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVKLH_s12_ir, TMS320C64X_INS_MVKLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVKL_s12_ir, TMS320C64X_INS_MVKL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVK_d1_rr, TMS320C64X_INS_MVK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_MVK_l2_ir, TMS320C64X_INS_MVK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_NOP_n, TMS320C64X_INS_NOP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_NO, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_NORM_l1_pr, TMS320C64X_INS_NORM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_NORM_l1_rr, TMS320C64X_INS_NORM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_d2_rir, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_d2_rrr, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_l1_irr, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_l1_rrr_x2, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_s1_irr, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_OR_s1_rrr, TMS320C64X_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACK2_l1_rrr_x2, TMS320C64X_INS_PACK2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACK2_s4_rrr, TMS320C64X_INS_PACK2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKH2_l1_rrr_x2, TMS320C64X_INS_PACKH2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKH2_s1_rrr, TMS320C64X_INS_PACKH2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKH4_l1_rrr_x2, TMS320C64X_INS_PACKH4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKHL2_l1_rrr_x2, TMS320C64X_INS_PACKHL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKHL2_s1_rrr, TMS320C64X_INS_PACKHL2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKL4_l1_rrr_x2, TMS320C64X_INS_PACKL4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKLH2_l1_rrr_x2, TMS320C64X_INS_PACKLH2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_PACKLH2_s1_rrr, TMS320C64X_INS_PACKLH2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ROTL_m1_rir, TMS320C64X_INS_ROTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_ROTL_m1_rrr, TMS320C64X_INS_ROTL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD2_s4_rrr, TMS320C64X_INS_SADD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADDU4_s4_rrr, TMS320C64X_INS_SADDU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADDUS2_s4_rrr, TMS320C64X_INS_SADDUS2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD_l1_ipp, TMS320C64X_INS_SADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD_l1_irr, TMS320C64X_INS_SADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD_l1_rpp, TMS320C64X_INS_SADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD_l1_rrr_x2, TMS320C64X_INS_SADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SADD_s1_rrr, TMS320C64X_INS_SADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SAT_l1_pr, TMS320C64X_INS_SAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SET_s15_riir, TMS320C64X_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SET_s1_rrr, TMS320C64X_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHFL_m2_rr, TMS320C64X_INS_SHFL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHLMB_l1_rrr_x2, TMS320C64X_INS_SHLMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHLMB_s4_rrr, TMS320C64X_INS_SHLMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_pip, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_prp, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_rip, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_rir, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_rrp, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHL_s1_rrr, TMS320C64X_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR2_s1_rir, TMS320C64X_INS_SHR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR2_s4_rrr, TMS320C64X_INS_SHR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRMB_l1_rrr_x2, TMS320C64X_INS_SHRMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRMB_s4_rrr, TMS320C64X_INS_SHRMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU2_s1_rir, TMS320C64X_INS_SHRU2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU2_s4_rrr, TMS320C64X_INS_SHRU2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU_s1_pip, TMS320C64X_INS_SHRU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU_s1_prp, TMS320C64X_INS_SHRU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU_s1_rir, TMS320C64X_INS_SHRU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHRU_s1_rrr, TMS320C64X_INS_SHRU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR_s1_pip, TMS320C64X_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR_s1_prp, TMS320C64X_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR_s1_rir, TMS320C64X_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SHR_s1_rrr, TMS320C64X_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SMPY2_m1_rrp, TMS320C64X_INS_SMPY2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SMPYHL_m4_rrr, TMS320C64X_INS_SMPYHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SMPYH_m4_rrr, TMS320C64X_INS_SMPYH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SMPYLH_m4_rrr, TMS320C64X_INS_SMPYLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SMPY_m4_rrr, TMS320C64X_INS_SMPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SPACK2_s4_rrr, TMS320C64X_INS_SPACK2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SPACKU4_s4_rrr, TMS320C64X_INS_SPACKU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSHL_s1_rir, TMS320C64X_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSHL_s1_rrr, TMS320C64X_INS_SSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSHVL_m1_rrr, TMS320C64X_INS_SSHVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSHVR_m1_rrr, TMS320C64X_INS_SSHVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSUB_l1_ipp, TMS320C64X_INS_SSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSUB_l1_irr, TMS320C64X_INS_SSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSUB_l1_rrr_x1, TMS320C64X_INS_SSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SSUB_l1_rrr_x2, TMS320C64X_INS_SSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STB_d5_rm, TMS320C64X_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STB_d6_rm, TMS320C64X_INS_STB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STDW_d7_pm, TMS320C64X_INS_STDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STH_d5_rm, TMS320C64X_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STH_d6_rm, TMS320C64X_INS_STH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STNDW_d8_pm, TMS320C64X_INS_STNDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STNW_d5_rm, TMS320C64X_INS_STNW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STW_d5_rm, TMS320C64X_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_STW_d6_rm, TMS320C64X_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB2_d2_rrr, TMS320C64X_INS_SUB2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB2_l1_rrr_x2, TMS320C64X_INS_SUB2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB2_s1_rrr, TMS320C64X_INS_SUB2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB4_l1_rrr_x2, TMS320C64X_INS_SUB4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBABS4_l1_rrr_x2, TMS320C64X_INS_SUBABS4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAB_d1_rir, TMS320C64X_INS_SUBAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAB_d1_rrr, TMS320C64X_INS_SUBAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAH_d1_rir, TMS320C64X_INS_SUBAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAH_d1_rrr, TMS320C64X_INS_SUBAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAW_d1_rir, TMS320C64X_INS_SUBAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBAW_d1_rrr, TMS320C64X_INS_SUBAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBC_l1_rrr_x2, TMS320C64X_INS_SUBC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBU_l1_rrp_x1, TMS320C64X_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUBU_l1_rrp_x2, TMS320C64X_INS_SUBU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_d1_rir, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_d1_rrr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_d2_rrr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_ipp, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_irr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_rrp_x1, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_rrp_x2, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_rrr_x1, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_l1_rrr_x2, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_s1_irr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_s1_rrr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SUB_s4_rrr, TMS320C64X_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_SWAP4_l2_rr, TMS320C64X_INS_SWAP4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_UNPKHU4_l2_rr, TMS320C64X_INS_UNPKHU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_UNPKHU4_s14_rr, TMS320C64X_INS_UNPKHU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_UNPKLU4_l2_rr, TMS320C64X_INS_UNPKLU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_UNPKLU4_s14_rr, TMS320C64X_INS_UNPKLU4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_d2_rir, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_d2_rrr, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_l1_irr, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_l1_rrr_x2, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_s1_irr, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XOR_s1_rrr, TMS320C64X_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XPND2_m2_rr, TMS320C64X_INS_XPND2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, + { + TMS320C64x_XPND4_m2_rr, TMS320C64X_INS_XPND4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 +#endif + }, +}; + +void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + insn->detail->groups[insn->detail->groups_count] = TMS320C64X_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + } + } +} + +#ifndef CAPSTONE_DIET +//grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}' +static name_map insn_name_maps[] = { + {TMS320C64X_INS_INVALID, NULL}, + {TMS320C64X_INS_ABS, "abs"}, + {TMS320C64X_INS_ABS2, "abs2"}, + {TMS320C64X_INS_ADD, "add"}, + {TMS320C64X_INS_ADD2, "add2"}, + {TMS320C64X_INS_ADD4, "add4"}, + {TMS320C64X_INS_ADDAB, "addab"}, + {TMS320C64X_INS_ADDAD, "addad"}, + {TMS320C64X_INS_ADDAH, "addah"}, + {TMS320C64X_INS_ADDAW, "addaw"}, + {TMS320C64X_INS_ADDK, "addk"}, + {TMS320C64X_INS_ADDKPC, "addkpc"}, + {TMS320C64X_INS_ADDU, "addu"}, + {TMS320C64X_INS_AND, "and"}, + {TMS320C64X_INS_ANDN, "andn"}, + {TMS320C64X_INS_AVG2, "avg2"}, + {TMS320C64X_INS_AVGU4, "avgu4"}, + {TMS320C64X_INS_B, "b"}, + {TMS320C64X_INS_BDEC, "bdec"}, + {TMS320C64X_INS_BITC4, "bitc4"}, + {TMS320C64X_INS_BNOP, "bnop"}, + {TMS320C64X_INS_BPOS, "bpos"}, + {TMS320C64X_INS_CLR, "clr"}, + {TMS320C64X_INS_CMPEQ, "cmpeq"}, + {TMS320C64X_INS_CMPEQ2, "cmpeq2"}, + {TMS320C64X_INS_CMPEQ4, "cmpeq4"}, + {TMS320C64X_INS_CMPGT, "cmpgt"}, + {TMS320C64X_INS_CMPGT2, "cmpgt2"}, + {TMS320C64X_INS_CMPGTU4, "cmpgtu4"}, + {TMS320C64X_INS_CMPLT, "cmplt"}, + {TMS320C64X_INS_CMPLTU, "cmpltu"}, + {TMS320C64X_INS_DEAL, "deal"}, + {TMS320C64X_INS_DOTP2, "dotp2"}, + {TMS320C64X_INS_DOTPN2, "dotpn2"}, + {TMS320C64X_INS_DOTPNRSU2, "dotpnrsu2"}, + {TMS320C64X_INS_DOTPRSU2, "dotprsu2"}, + {TMS320C64X_INS_DOTPSU4, "dotpsu4"}, + {TMS320C64X_INS_DOTPU4, "dotpu4"}, + {TMS320C64X_INS_EXT, "ext"}, + {TMS320C64X_INS_EXTU, "extu"}, + {TMS320C64X_INS_GMPGTU, "gmpgtu"}, + {TMS320C64X_INS_GMPY4, "gmpy4"}, + {TMS320C64X_INS_LDB, "ldb"}, + {TMS320C64X_INS_LDBU, "ldbu"}, + {TMS320C64X_INS_LDDW, "lddw"}, + {TMS320C64X_INS_LDH, "ldh"}, + {TMS320C64X_INS_LDHU, "ldhu"}, + {TMS320C64X_INS_LDNDW, "ldndw"}, + {TMS320C64X_INS_LDNW, "ldnw"}, + {TMS320C64X_INS_LDW, "ldw"}, + {TMS320C64X_INS_LMBD, "lmbd"}, + {TMS320C64X_INS_MAX2, "max2"}, + {TMS320C64X_INS_MAXU4, "maxu4"}, + {TMS320C64X_INS_MIN2, "min2"}, + {TMS320C64X_INS_MINU4, "minu4"}, + {TMS320C64X_INS_MPY, "mpy"}, + {TMS320C64X_INS_MPY2, "mpy2"}, + {TMS320C64X_INS_MPYH, "mpyh"}, + {TMS320C64X_INS_MPYHI, "mpyhi"}, + {TMS320C64X_INS_MPYHIR, "mpyhir"}, + {TMS320C64X_INS_MPYHL, "mpyhl"}, + {TMS320C64X_INS_MPYHLU, "mpyhlu"}, + {TMS320C64X_INS_MPYHSLU, "mpyhslu"}, + {TMS320C64X_INS_MPYHSU, "mpyhsu"}, + {TMS320C64X_INS_MPYHU, "mpyhu"}, + {TMS320C64X_INS_MPYHULS, "mpyhuls"}, + {TMS320C64X_INS_MPYHUS, "mpyhus"}, + {TMS320C64X_INS_MPYLH, "mpylh"}, + {TMS320C64X_INS_MPYLHU, "mpylhu"}, + {TMS320C64X_INS_MPYLI, "mpyli"}, + {TMS320C64X_INS_MPYLIR, "mpylir"}, + {TMS320C64X_INS_MPYLSHU, "mpylshu"}, + {TMS320C64X_INS_MPYLUHS, "mpyluhs"}, + {TMS320C64X_INS_MPYSU, "mpysu"}, + {TMS320C64X_INS_MPYSU4, "mpysu4"}, + {TMS320C64X_INS_MPYU, "mpyu"}, + {TMS320C64X_INS_MPYU4, "mpyu4"}, + {TMS320C64X_INS_MPYUS, "mpyus"}, + {TMS320C64X_INS_MVC, "mvc"}, + {TMS320C64X_INS_MVD, "mvd"}, + {TMS320C64X_INS_MVK, "mvk"}, + {TMS320C64X_INS_MVKL, "mvkl"}, + {TMS320C64X_INS_MVKLH, "mvklh"}, + {TMS320C64X_INS_NOP, "nop"}, + {TMS320C64X_INS_NORM, "norm"}, + {TMS320C64X_INS_OR, "or"}, + {TMS320C64X_INS_PACK2, "pack2"}, + {TMS320C64X_INS_PACKH2, "packh2"}, + {TMS320C64X_INS_PACKH4, "packh4"}, + {TMS320C64X_INS_PACKHL2, "packhl2"}, + {TMS320C64X_INS_PACKL4, "packl4"}, + {TMS320C64X_INS_PACKLH2, "packlh2"}, + {TMS320C64X_INS_ROTL, "rotl"}, + {TMS320C64X_INS_SADD, "sadd"}, + {TMS320C64X_INS_SADD2, "sadd2"}, + {TMS320C64X_INS_SADDU4, "saddu4"}, + {TMS320C64X_INS_SADDUS2, "saddus2"}, + {TMS320C64X_INS_SAT, "sat"}, + {TMS320C64X_INS_SET, "set"}, + {TMS320C64X_INS_SHFL, "shfl"}, + {TMS320C64X_INS_SHL, "shl"}, + {TMS320C64X_INS_SHLMB, "shlmb"}, + {TMS320C64X_INS_SHR, "shr"}, + {TMS320C64X_INS_SHR2, "shr2"}, + {TMS320C64X_INS_SHRMB, "shrmb"}, + {TMS320C64X_INS_SHRU, "shru"}, + {TMS320C64X_INS_SHRU2, "shru2"}, + {TMS320C64X_INS_SMPY, "smpy"}, + {TMS320C64X_INS_SMPY2, "smpy2"}, + {TMS320C64X_INS_SMPYH, "smpyh"}, + {TMS320C64X_INS_SMPYHL, "smpyhl"}, + {TMS320C64X_INS_SMPYLH, "smpylh"}, + {TMS320C64X_INS_SPACK2, "spack2"}, + {TMS320C64X_INS_SPACKU4, "spacku4"}, + {TMS320C64X_INS_SSHL, "sshl"}, + {TMS320C64X_INS_SSHVL, "sshvl"}, + {TMS320C64X_INS_SSHVR, "sshvr"}, + {TMS320C64X_INS_SSUB, "ssub"}, + {TMS320C64X_INS_STB, "stb"}, + {TMS320C64X_INS_STDW, "stdw"}, + {TMS320C64X_INS_STH, "sth"}, + {TMS320C64X_INS_STNDW, "stndw"}, + {TMS320C64X_INS_STNW, "stnw"}, + {TMS320C64X_INS_STW, "stw"}, + {TMS320C64X_INS_SUB, "sub"}, + {TMS320C64X_INS_SUB2, "sub2"}, + {TMS320C64X_INS_SUB4, "sub4"}, + {TMS320C64X_INS_SUBAB, "subab"}, + {TMS320C64X_INS_SUBABS4, "subabs4"}, + {TMS320C64X_INS_SUBAH, "subah"}, + {TMS320C64X_INS_SUBAW, "subaw"}, + {TMS320C64X_INS_SUBC, "subc"}, + {TMS320C64X_INS_SUBU, "subu"}, + {TMS320C64X_INS_SWAP4, "swap4"}, + {TMS320C64X_INS_UNPKHU4, "unpkhu4"}, + {TMS320C64X_INS_UNPKLU4, "unpklu4"}, + {TMS320C64X_INS_XOR, "xor"}, + {TMS320C64X_INS_XPND2, "xpnd2"}, + {TMS320C64X_INS_XPND4, "xpnd4"}, + {TMS320C64X_INS_IDLE, "idle"}, + {TMS320C64X_INS_MV, "mv"}, + {TMS320C64X_INS_NEG, "neg"}, + {TMS320C64X_INS_NOT, "not"}, + {TMS320C64X_INS_SWAP2, "swap2"}, + {TMS320C64X_INS_ZERO, "zero"}, +}; + +#endif + +const char *TMS320C64x_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= TMS320C64X_INS_ENDING) + return NULL; + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static name_map group_name_maps[] = { + { TMS320C64X_GRP_INVALID, NULL }, + { TMS320C64X_GRP_FUNIT_D, "funit_d" }, + { TMS320C64X_GRP_FUNIT_L, "funit_l" }, + { TMS320C64X_GRP_FUNIT_M, "funit_m" }, + { TMS320C64X_GRP_FUNIT_S, "funit_s" }, + { TMS320C64X_GRP_FUNIT_NO, "funit_no" }, + { TMS320C64X_GRP_JUMP, "jump" }, +}; +#endif + +const char *TMS320C64x_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= TMS320C64X_GRP_ENDING) + return NULL; + + for (i = 0; i < ARR_SIZE(group_name_maps); i++) { + if (group_name_maps[i].id == id) + return group_name_maps[i].name; + } + + return group_name_maps[id].name; +#else + return NULL; +#endif +} + +tms320c64x_reg TMS320C64x_map_register(unsigned int r) +{ + static unsigned int map[] = { 0, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + return 0; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.h b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.h new file mode 100644 index 0000000..ce26d3e --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xMapping.h @@ -0,0 +1,26 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifndef CS_TMS320C64X_MAP_H +#define CS_TMS320C64X_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *TMS320C64x_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *TMS320C64x_insn_name(csh handle, unsigned int id); + +const char *TMS320C64x_group_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +tms320c64x_reg TMS320C64x_map_register(unsigned int r); + +// map register name to register ID +tms320c64x_reg TMS320C64x_reg_id(char *name); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.c b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.c new file mode 100644 index 0000000..ff678c7 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.c @@ -0,0 +1,39 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifdef CAPSTONE_HAS_TMS320C64X + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "TMS320C64xDisassembler.h" +#include "TMS320C64xInstPrinter.h" +#include "TMS320C64xMapping.h" +#include "TMS320C64xModule.h" + +cs_err TMS320C64x_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + + mri = cs_mem_malloc(sizeof(*mri)); + + TMS320C64x_init(mri); + ud->printer = TMS320C64x_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = TMS320C64x_getInstruction; + ud->post_printer = TMS320C64x_post_printer; + + ud->reg_name = TMS320C64x_reg_name; + ud->insn_id = TMS320C64x_get_insn_id; + ud->insn_name = TMS320C64x_insn_name; + ud->group_name = TMS320C64x_group_name; + + return CS_ERR_OK; +} + +cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.h b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.h new file mode 100644 index 0000000..f1c5312 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/TMS320C64x/TMS320C64xModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_TMS320C64X_MODULE_H +#define CS_TMS320C64X_MODULE_H + +#include "../../utils.h" + +cs_err TMS320C64x_global_init(cs_struct *ud); +cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.c b/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.c new file mode 100644 index 0000000..c095240 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.c @@ -0,0 +1,794 @@ +//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_XCORE + +#include // DEBUG +#include +#include + +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "XCoreDisassembler.h" + +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCRegisterInfo.h" +#include "../../MCDisassembler.h" +#include "../../MathExtras.h" + +static uint64_t getFeatureBits(int mode) +{ + // support everything + return (uint64_t)-1; +} + +static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) +{ + if (code_len < 2) + // insufficient data + return false; + + // Encoded as a little-endian 16-bit word in the stream. + *insn = (code[0] << 0) | (code[1] << 8); + return true; +} + +static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) +{ + if (code_len < 4) + // insufficient data + return false; + + // Encoded as a little-endian 32-bit word in the stream. + *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24); + + return true; +} + +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) +{ + const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); + return rc->RegsBegin[RegNo]; +} + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +#include "XCoreGenDisassemblerTables.inc" + +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#include "XCoreGenRegisterInfo.inc" + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + + if (RegNo > 11) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Reg; + if (RegNo > 15) + return MCDisassembler_Fail; + + Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + static const unsigned Values[] = { + 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 + }; + + if (Val > 11) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Values[Val]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, -(int64_t)Val); + return MCDisassembler_Success; +} + +static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) +{ + unsigned Op1High, Op2High; + unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); + + if (Combined < 27) + return MCDisassembler_Fail; + + if (fieldFromInstruction_4(Insn, 5, 1)) { + if (Combined == 31) + return MCDisassembler_Fail; + Combined += 5; + } + + Combined -= 27; + Op1High = Combined % 3; + Op2High = Combined / 3; + *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); + *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); + + return MCDisassembler_Success; +} + +static DecodeStatus Decode3OpInstruction(unsigned Insn, + unsigned *Op1, unsigned *Op2, unsigned *Op3) +{ + unsigned Op1High, Op2High, Op3High; + unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); + if (Combined >= 27) + return MCDisassembler_Fail; + + Op1High = Combined % 3; + Op2High = (Combined / 3) % 3; + Op3High = Combined / 9; + *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); + *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); + *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2); + + return MCDisassembler_Success; +} + +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" +static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + // Try and decode as a 3R instruction. + unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); + switch (Opcode) { + case 0x0: + MCInst_setOpcode(Inst, XCore_STW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x1: + MCInst_setOpcode(Inst, XCore_LDW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x2: + MCInst_setOpcode(Inst, XCore_ADD_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x3: + MCInst_setOpcode(Inst, XCore_SUB_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x4: + MCInst_setOpcode(Inst, XCore_SHL_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x5: + MCInst_setOpcode(Inst, XCore_SHR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x6: + MCInst_setOpcode(Inst, XCore_EQ_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x7: + MCInst_setOpcode(Inst, XCore_AND_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x8: + MCInst_setOpcode(Inst, XCore_OR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x9: + MCInst_setOpcode(Inst, XCore_LDW_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x10: + MCInst_setOpcode(Inst, XCore_LD16S_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x11: + MCInst_setOpcode(Inst, XCore_LD8U_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x12: + MCInst_setOpcode(Inst, XCore_ADD_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x13: + MCInst_setOpcode(Inst, XCore_SUB_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14: + MCInst_setOpcode(Inst, XCore_SHL_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x15: + MCInst_setOpcode(Inst, XCore_SHR_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x16: + MCInst_setOpcode(Inst, XCore_EQ_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x17: + MCInst_setOpcode(Inst, XCore_TSETR_3r); + return Decode3RImmInstruction(Inst, Insn, Address, Decoder); + case 0x18: + MCInst_setOpcode(Inst, XCore_LSS_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x19: + MCInst_setOpcode(Inst, XCore_LSU_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + } + + return MCDisassembler_Fail; +} + +static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + MCOperand_CreateImm0(Inst, Op1); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + MCOperand_CreateImm0(Inst, Op2); + + return S; +} + +static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + // Try and decode as a L3R / L2RUS instruction. + unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | + fieldFromInstruction_4(Insn, 27, 5) << 4; + switch (Opcode) { + case 0x0c: + MCInst_setOpcode(Inst, XCore_STW_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x1c: + MCInst_setOpcode(Inst, XCore_XOR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x2c: + MCInst_setOpcode(Inst, XCore_ASHR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x3c: + MCInst_setOpcode(Inst, XCore_LDAWF_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x4c: + MCInst_setOpcode(Inst, XCore_LDAWB_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x5c: + MCInst_setOpcode(Inst, XCore_LDA16F_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x6c: + MCInst_setOpcode(Inst, XCore_LDA16B_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x7c: + MCInst_setOpcode(Inst, XCore_MUL_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x8c: + MCInst_setOpcode(Inst, XCore_DIVS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x9c: + MCInst_setOpcode(Inst, XCore_DIVU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x10c: + MCInst_setOpcode(Inst, XCore_ST16_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x11c: + MCInst_setOpcode(Inst, XCore_ST8_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x12c: + MCInst_setOpcode(Inst, XCore_ASHR_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12d: + MCInst_setOpcode(Inst, XCore_OUTPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12e: + MCInst_setOpcode(Inst, XCore_INPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x13c: + MCInst_setOpcode(Inst, XCore_LDAWF_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14c: + MCInst_setOpcode(Inst, XCore_LDAWB_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x15c: + MCInst_setOpcode(Inst, XCore_CRC_l3r); + return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); + case 0x18c: + MCInst_setOpcode(Inst, XCore_REMS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x19c: + MCInst_setOpcode(Inst, XCore_REMU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + } + + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); + if (S != MCDisassembler_Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + + return S; +} + +static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); + if (S != MCDisassembler_Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + + return S; +} + +static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + MCOperand_CreateImm0(Inst, Op1); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + MCOperand_CreateImm0(Inst, Op3); + } + + return S; +} + +static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + MCOperand_CreateImm0(Inst, Op3); + } + + return S; +} + +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + + return S; +} + +static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3, Op4, Op5, Op6; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S != MCDisassembler_Success) + return S; + + S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); + if (S != MCDisassembler_Success) + return S; + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + return S; +} + +static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Opcode; + + // Try and decode as a L6R instruction. + MCInst_clear(Inst); + Opcode = fieldFromInstruction_4(Insn, 27, 5); + switch (Opcode) { + default: + break; + case 0x00: + MCInst_setOpcode(Inst, XCore_LMUL_l6r); + return DecodeL6RInstruction(Inst, Insn, Address, Decoder); + } + + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3, Op4, Op5; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S != MCDisassembler_Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + + S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); + if (S != MCDisassembler_Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + return S; +} + +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, + const void *Decoder) +{ + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + + return S; +} + +#define GET_SUBTARGETINFO_ENUM +#include "XCoreGenInstrInfo.inc" +bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, + uint16_t *size, uint64_t address, void *info) +{ + uint16_t insn16; + uint32_t insn32; + DecodeStatus Result; + + if (!readInstruction16(code, code_len, &insn16)) { + return false; + } + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore)); + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0); + if (Result != MCDisassembler_Fail) { + *size = 2; + return true; + } + + if (!readInstruction32(code, code_len, &insn32)) { + return false; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0); + if (Result != MCDisassembler_Fail) { + *size = 4; + return true; + } + + return false; +} + +void XCore_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, + XCoreMCRegisterClasses, 2, + XCoreRegUnitRoots, + 16, + XCoreRegDiffLists, + XCoreRegStrings, + XCoreSubRegIdxLists, + 1, + XCoreSubRegIdxRanges, + XCoreRegEncodingTable); + */ + + + MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17, + 0, 0, + XCoreMCRegisterClasses, 2, + 0, 0, + XCoreRegDiffLists, + 0, + XCoreSubRegIdxLists, 1, + 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.h b/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.h new file mode 100644 index 0000000..a747800 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreDisassembler.h @@ -0,0 +1,17 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_XCOREDISASSEMBLER_H +#define CS_XCOREDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" +#include "../../MCInst.h" + +void XCore_init(MCRegisterInfo *MRI); + +bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, void *info); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreGenAsmWriter.inc b/white_patch_detect/capstone-master/arch/XCore/XCoreGenAsmWriter.inc new file mode 100644 index 0000000..adddeff --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreGenAsmWriter.inc @@ -0,0 +1,772 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include // debug +#include + + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +{ + static const uint32_t OpInfo[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 665U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 658U, // BUNDLE + 687U, // LIFETIME_START + 645U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 2250U, // ADD_2rus + 2250U, // ADD_3r + 10363U, // ADJCALLSTACKDOWN + 10383U, // ADJCALLSTACKUP + 2361840U, // ANDNOT_2r + 2255U, // AND_3r + 2404U, // ASHR_l2rus + 2404U, // ASHR_l3r + 10769U, // BAU_1r + 2099777U, // BITREV_l2r + 19161U, // BLACP_lu10 + 19161U, // BLACP_u10 + 10672U, // BLAT_lu6 + 10672U, // BLAT_u6 + 10425U, // BLA_1r + 10510U, // BLRB_lu10 + 10510U, // BLRB_u10 + 10510U, // BLRF_lu10 + 10510U, // BLRF_u10 + 2099418U, // BRBF_lru6 + 2099418U, // BRBF_ru6 + 2099638U, // BRBT_lru6 + 2099638U, // BRBT_ru6 + 10774U, // BRBU_lu6 + 10774U, // BRBU_u6 + 2099418U, // BRFF_lru6 + 2099418U, // BRFF_ru6 + 2099638U, // BRFT_lru6 + 2099638U, // BRFT_ru6 + 10774U, // BRFU_lu6 + 10774U, // BRFU_u6 + 10791U, // BRU_1r + 553511U, // BR_JT + 815655U, // BR_JT32 + 2099768U, // BYTEREV_l2r + 2132815U, // CHKCT_2r + 2132815U, // CHKCT_rus + 1163U, // CLRE_0R + 19301U, // CLRPT_1R + 10614U, // CLRSR_branch_lu6 + 10614U, // CLRSR_branch_u6 + 10614U, // CLRSR_lu6 + 10614U, // CLRSR_u6 + 2099807U, // CLZ_l2r + 5247047U, // CRC8_l4r + 17041459U, // CRC_l3r + 1168U, // DCALL_0R + 1200U, // DENTSP_0R + 10488U, // DGETREG_1r + 2474U, // DIVS_l3r + 2610U, // DIVU_l3r + 1207U, // DRESTSP_0R + 1242U, // DRET_0R + 10475U, // ECALLF_1r + 10723U, // ECALLT_1r + 19342U, // EDU_1r + 6334686U, // EEF_2r + 6334929U, // EET_2r + 19351U, // EEU_1r + 2099310U, // EH_RETURN + 6334765U, // ENDIN_2r + 10569U, // ENTSP_lu6 + 10569U, // ENTSP_u6 + 2400U, // EQ_2rus + 2400U, // EQ_3r + 10554U, // EXTDP_lu6 + 10554U, // EXTDP_u6 + 10585U, // EXTSP_lu6 + 10585U, // EXTSP_u6 + 10401U, // FRAME_TO_ARGS_OFFSET + 19256U, // FREER_1r + 1236U, // FREET_0R + 6334676U, // GETD_l2r + 1139U, // GETED_0R + 1224U, // GETET_0R + 1151U, // GETID_0R + 1174U, // GETKEP_0R + 1187U, // GETKSP_0R + 6334772U, // GETN_l2r + 51670U, // GETPS_l2r + 2099588U, // GETR_rus + 10252U, // GETSR_lu6 + 10252U, // GETSR_u6 + 6334968U, // GETST_2r + 6334883U, // GETTS_2r + 6334906U, // INCT_2r + 62438U, // INITCP_2r + 70630U, // INITDP_2r + 78822U, // INITLR_l2r + 87014U, // INITPC_2r + 95206U, // INITSP_2r + 8432212U, // INPW_l2rus + 6596970U, // INSHR_2r + 6334955U, // INT_2r + 6334768U, // IN_2r + 675U, // Int_MemBarrier + 10528U, // KCALL_1r + 10528U, // KCALL_lu6 + 10528U, // KCALL_u6 + 10568U, // KENTSP_lu6 + 10568U, // KENTSP_u6 + 10576U, // KRESTSP_lu6 + 10576U, // KRESTSP_u6 + 1247U, // KRET_0R + 45093065U, // LADD_l5r + 12585354U, // LD16S_3r + 12585483U, // LD8U_3r + 14682170U, // LDA16B_l3r + 12585018U, // LDA16F_l3r + 10241U, // LDAPB_lu10 + 10241U, // LDAPB_u10 + 10241U, // LDAPF_lu10 + 10241U, // LDAPF_lu10_ba + 10241U, // LDAPF_u10 + 14682697U, // LDAWB_l2rus + 14682697U, // LDAWB_l3r + 19134U, // LDAWCP_lu6 + 19134U, // LDAWCP_u6 + 100937U, // LDAWDP_lru6 + 100937U, // LDAWDP_ru6 + 2099282U, // LDAWFI + 12585545U, // LDAWF_l2rus + 12585545U, // LDAWF_l3r + 109129U, // LDAWSP_lru6 + 109129U, // LDAWSP_ru6 + 2099396U, // LDC_lru6 + 2099396U, // LDC_ru6 + 1105U, // LDET_0R + 184551985U, // LDIVU_l5r + 1075U, // LDSED_0R + 1015U, // LDSPC_0R + 1045U, // LDSSR_0R + 117327U, // LDWCP_lru6 + 19148U, // LDWCP_lu10 + 117327U, // LDWCP_ru6 + 19148U, // LDWCP_u10 + 100943U, // LDWDP_lru6 + 100943U, // LDWDP_ru6 + 2099292U, // LDWFI + 109135U, // LDWSP_lru6 + 109135U, // LDWSP_ru6 + 12585551U, // LDW_2rus + 12585551U, // LDW_3r + 268437799U, // LMUL_l6r + 2462U, // LSS_3r + 45093054U, // LSUB_l5r + 2604U, // LSU_3r + 452987281U, // MACCS_l4r + 452987418U, // MACCU_l4r + 19224U, // MJOIN_1r + 2099463U, // MKMSK_2r + 2099463U, // MKMSK_rus + 19169U, // MSYNC_1r + 2344U, // MUL_l3r + 2099443U, // NEG + 2099699U, // NOT + 2418U, // OR_3r + 2132826U, // OUTCT_2r + 2132826U, // OUTCT_rus + 78681013U, // OUTPW_l2rus + 2136899U, // OUTSHR_2r + 2132859U, // OUTT_2r + 2132869U, // OUT_2r + 6334721U, // PEEK_2r + 2456U, // REMS_l3r + 2593U, // REMU_l3r + 10561U, // RETSP_lu6 + 10561U, // RETSP_u6 + 612U, // SELECT_CC + 2132748U, // SETCLK_l2r + 10264U, // SETCP_1r + 2132728U, // SETC_l2r + 2132728U, // SETC_lru6 + 2132728U, // SETC_ru6 + 10273U, // SETDP_1r + 2132738U, // SETD_2r + 125856U, // SETEV_1r + 632U, // SETKEP_0R + 2132771U, // SETN_l2r + 2132716U, // SETPSC_2r + 2132951U, // SETPS_l2r + 2132848U, // SETPT_2r + 2132939U, // SETRDY_l2r + 10282U, // SETSP_1r + 10621U, // SETSR_branch_lu6 + 10621U, // SETSR_branch_u6 + 10621U, // SETSR_lu6 + 10621U, // SETSR_u6 + 2132928U, // SETTW_l2r + 125867U, // SETV_1r + 2361855U, // SEXT_2r + 2361855U, // SEXT_rus + 2331U, // SHL_2rus + 2331U, // SHL_3r + 2405U, // SHR_2rus + 2405U, // SHR_3r + 1133U, // SSYNC_0r + 12585025U, // ST16_l3r + 12585037U, // ST8_l3r + 1119U, // STET_0R + 1090U, // STSED_0R + 1030U, // STSPC_0R + 1060U, // STSSR_0R + 100954U, // STWDP_lru6 + 100954U, // STWDP_ru6 + 2099301U, // STWFI + 109146U, // STWSP_lru6 + 109146U, // STWSP_ru6 + 12585562U, // STW_2rus + 12585562U, // STW_l3r + 2239U, // SUB_2rus + 2239U, // SUB_3r + 19245U, // SYNCR_1r + 6334912U, // TESTCT_2r + 6334738U, // TESTLCL_l2r + 6334920U, // TESTWCT_2r + 2100415U, // TSETMR_2r + 138207U, // TSETR_3r + 19438U, // TSTART_1R + 10467U, // WAITEF_1R + 10715U, // WAITET_1R + 1252U, // WAITEU_0R + 2417U, // XOR_l3r + 2361861U, // ZEXT_2r + 2361861U, // ZEXT_rus + 0U + }; + + static const char AsmStrs[] = { + /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0, + /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0, + /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0, + /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0, + /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0, + /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0, + /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0, + /* 64 */ 's', 't', '1', '6', 32, 0, + /* 70 */ 'c', 'r', 'c', '8', 32, 0, + /* 76 */ 's', 't', '8', 32, 0, + /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0, + /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0, + /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0, + /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0, + /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, + /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, + /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0, + /* 184 */ 'b', 'l', 'a', 32, 0, + /* 189 */ 'l', 's', 'u', 'b', 32, 0, + /* 195 */ 'l', 'd', 'c', 32, 0, + /* 200 */ 'l', 'a', 'd', 'd', 32, 0, + /* 206 */ 'a', 'n', 'd', 32, 0, + /* 211 */ 'g', 'e', 't', 'd', 32, 0, + /* 217 */ 'b', 'f', 32, 0, + /* 221 */ 'e', 'e', 'f', 32, 0, + /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0, + /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0, + /* 242 */ 'n', 'e', 'g', 32, 0, + /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0, + /* 256 */ 'p', 'e', 'e', 'k', 32, 0, + /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0, + /* 269 */ 'b', 'l', 32, 0, + /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0, + /* 282 */ 's', 'h', 'l', 32, 0, + /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0, + /* 294 */ 'l', 'm', 'u', 'l', 32, 0, + /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0, + /* 307 */ 'g', 'e', 't', 'n', 32, 0, + /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0, + /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0, + /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0, + /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0, + /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0, + /* 351 */ 'e', 'q', 32, 0, + /* 355 */ 'a', 's', 'h', 'r', 32, 0, + /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0, + /* 368 */ 'x', 'o', 'r', 32, 0, + /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0, + /* 380 */ 's', 'e', 't', 's', 'r', 32, 0, + /* 387 */ 'g', 'e', 't', 'r', 32, 0, + /* 393 */ 'l', 'd', '1', '6', 's', 32, 0, + /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0, + /* 407 */ 'r', 'e', 'm', 's', 32, 0, + /* 413 */ 'l', 's', 's', 32, 0, + /* 418 */ 'g', 'e', 't', 't', 's', 32, 0, + /* 425 */ 'd', 'i', 'v', 's', 32, 0, + /* 431 */ 'b', 'l', 'a', 't', 32, 0, + /* 437 */ 'b', 't', 32, 0, + /* 441 */ 'i', 'n', 'c', 't', 32, 0, + /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0, + /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0, + /* 464 */ 'e', 'e', 't', 32, 0, + /* 469 */ 'g', 'e', 't', 32, 0, + /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0, + /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0, + /* 490 */ 'i', 'n', 't', 32, 0, + /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0, + /* 503 */ 'g', 'e', 't', 's', 't', 32, 0, + /* 510 */ 's', 'e', 'x', 't', 32, 0, + /* 516 */ 'z', 'e', 'x', 't', 32, 0, + /* 522 */ 'l', 'd', '8', 'u', 32, 0, + /* 528 */ 'b', 'a', 'u', 32, 0, + /* 533 */ 'b', 'u', 32, 0, + /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0, + /* 544 */ 'r', 'e', 'm', 'u', 32, 0, + /* 550 */ 'b', 'r', 'u', 32, 0, + /* 555 */ 'l', 's', 'u', 32, 0, + /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0, + /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0, + /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0, + /* 584 */ 'l', 'd', 'a', 'w', 32, 0, + /* 590 */ 'l', 'd', 'w', 32, 0, + /* 595 */ 'i', 'n', 'p', 'w', 32, 0, + /* 601 */ 's', 't', 'w', 32, 0, + /* 606 */ 'c', 'l', 'z', 32, 0, + /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, + /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0, + /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, + /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, + /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, + /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0, + /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0, + /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0, + /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0, + /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0, + /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0, + /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0, + /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0, + /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0, + /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0, + /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0, + /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0, + /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0, + /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0, + /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0, + /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0, + /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0, + /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0, + /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0, + /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0, + /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0, + /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0, + /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0, + /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0, + /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0, + /* 990 */ 's', 'e', 't', 32, 't', '[', 0, + /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0, + /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0, + /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, + /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, + /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, + /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, + /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, + /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, + /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, + /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, + /* 1132 */ 's', 's', 'y', 'n', 'c', 0, + /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0, + /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0, + /* 1162 */ 'c', 'l', 'r', 'e', 0, + /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0, + /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0, + /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0, + /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0, + /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0, + /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0, + /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0, + /* 1235 */ 'f', 'r', 'e', 'e', 't', 0, + /* 1241 */ 'd', 'r', 'e', 't', 0, + /* 1246 */ 'k', 'r', 'e', 't', 0, + /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0, + }; + + // Emit the opcode for the instruction. + uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; + // assert(Bits != 0 && "Cannot print this instruction."); +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 2047)-1); +#endif + + + if (strchr((const char *)AsmStrs+(Bits & 2047)-1, '[')) { + set_mem_access(MI, true, 0); + } + + // Fragment 0 encoded into 2 bits for 4 unique commands. + //printf(">>%s\n", AsmStrs+(Bits & 2047)-1); + //printf("Frag-0: %u\n", (Bits >> 11) & 3); + switch ((Bits >> 11) & 3) { + default: // unreachable. + case 0: + // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE... + // already done. this means we have to extract details out ourself. + XCore_insn_extract(MI, (const char *)AsmStrs+(Bits & 2047)-1); + return; + break; + case 1: + // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,... + printOperand(MI, 0, O); + break; + case 2: + // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,... + printOperand(MI, 1, O); + break; + case 3: + // OUTSHR_2r, TSETR_3r + printOperand(MI, 2, O); + break; + } + + + // Fragment 1 encoded into 5 bits for 17 unique commands. + //printf("Frag-1: %u\n", (Bits >> 13) & 31); + switch ((Bits >> 13) & 31) { + default: // unreachable. + case 0: + // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,... + SStream_concat0(O, ", "); + break; + case 1: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B... + return; + break; + case 2: + // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,... + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 3: + // BR_JT, BR_JT32 + SStream_concat0(O, "\n"); + break; + case 4: + // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT... + SStream_concat0(O, "], "); + set_mem_access(MI, false, 0); + break; + case 5: + // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... + SStream_concat0(O, ", res["); + set_mem_access(MI, true, 0); + break; + case 6: + // GETPS_l2r + SStream_concat0(O, ", ps["); + set_mem_access(MI, true, 0); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 7: + // INITCP_2r + SStream_concat0(O, "]:cp, "); + set_mem_access(MI, false, XCORE_REG_CP); + printOperand(MI, 0, O); + return; + break; + case 8: + // INITDP_2r + SStream_concat0(O, "]:dp, "); + set_mem_access(MI, false, XCORE_REG_DP); + printOperand(MI, 0, O); + return; + break; + case 9: + // INITLR_l2r + SStream_concat0(O, "]:lr, "); + set_mem_access(MI, false, XCORE_REG_LR); + printOperand(MI, 0, O); + return; + break; + case 10: + // INITPC_2r + SStream_concat0(O, "]:pc, "); + set_mem_access(MI, false, XCORE_REG_PC); + printOperand(MI, 0, O); + return; + break; + case 11: + // INITSP_2r + SStream_concat0(O, "]:sp, "); + set_mem_access(MI, false, XCORE_REG_SP); + printOperand(MI, 0, O); + return; + break; + case 12: + // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6 + SStream_concat0(O, ", dp["); + set_mem_access(MI, true, XCORE_REG_DP); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 13: + // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6 + SStream_concat0(O, ", sp["); + set_mem_access(MI, true, XCORE_REG_SP); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 14: + // LDWCP_lru6, LDWCP_ru6 + SStream_concat0(O, ", cp["); + set_mem_access(MI, true, XCORE_REG_CP); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 15: + // SETEV_1r, SETV_1r + SStream_concat0(O, "], r11"); + set_mem_access(MI, false, 0); + return; + break; + case 16: + // TSETR_3r + SStream_concat0(O, "]:r"); + set_mem_access(MI, false, 0); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + } + + + // Fragment 2 encoded into 3 bits for 5 unique commands. + //printf("Frag-2: %u\n", (Bits >> 18) & 7); + switch ((Bits >> 18) & 7) { + default: // unreachable. + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,... + printOperand(MI, 1, O); + break; + case 1: + // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus + printOperand(MI, 2, O); + break; + case 2: + // BR_JT + printInlineJT(MI, 0, O); + return; + break; + case 3: + // BR_JT32 + printInlineJT32(MI, 0, O); + return; + break; + case 4: + // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + } + + + // Fragment 3 encoded into 3 bits for 8 unique commands. + //printf("Frag-3: %u\n", (Bits >> 21) & 7); + switch ((Bits >> 21) & 7) { + default: // unreachable. + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV... + SStream_concat0(O, ", "); + break; + case 1: + // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_... + return; + break; + case 2: + // CRC8_l4r + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 3: + // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 4: + // INPW_l2rus + SStream_concat0(O, "], "); + set_mem_access(MI, false, 0); + printOperand(MI, 2, O); + return; + break; + case 5: + // LADD_l5r, LSUB_l5r, OUTPW_l2rus + printOperand(MI, 2, O); + break; + case 6: + // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3... + SStream_concat0(O, "["); + set_mem_access(MI, true, 0xffff); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + case 7: + // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r + SStream_concat0(O, "[-"); + set_mem_access(MI, true, -0xffff); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false, 0); + return; + break; + } + + + // Fragment 4 encoded into 3 bits for 5 unique commands. + //printf("Frag-4: %u\n", (Bits >> 24) & 7); + switch ((Bits >> 24) & 7) { + default: // unreachable. + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... + printOperand(MI, 2, O); + break; + case 1: + // CRC_l3r + printOperand(MI, 3, O); + return; + break; + case 2: + // LADD_l5r, LSUB_l5r + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 3: + // LDIVU_l5r, MACCS_l4r, MACCU_l4r + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + break; + case 4: + // OUTPW_l2rus + return; + break; + } + + + // Fragment 5 encoded into 2 bits for 4 unique commands. + //printf("Frag-5: %u\n", (Bits >> 27) & 3); + switch ((Bits >> 27) & 3) { + default: // unreachable. + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... + return; + break; + case 1: + // LDIVU_l5r + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 2: + // LMUL_l6r + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 3: + // MACCS_l4r, MACCU_l4r + printOperand(MI, 5, O); + return; + break; + } +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + // assert(RegNo && RegNo < 17 && "Invalid register number!"); + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'r', '1', '0', 0, + /* 4 */ 'r', '0', 0, + /* 7 */ 'r', '1', '1', 0, + /* 11 */ 'r', '1', 0, + /* 14 */ 'r', '2', 0, + /* 17 */ 'r', '3', 0, + /* 20 */ 'r', '4', 0, + /* 23 */ 'r', '5', 0, + /* 26 */ 'r', '6', 0, + /* 29 */ 'r', '7', 0, + /* 32 */ 'r', '8', 0, + /* 35 */ 'r', '9', 0, + /* 38 */ 'c', 'p', 0, + /* 41 */ 'd', 'p', 0, + /* 44 */ 's', 'p', 0, + /* 47 */ 'l', 'r', 0, + }; + + static const uint8_t RegAsmOffset[] = { + 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, + 0, 7, + }; + + //int i; + //for (i = 0; i < sizeof(RegAsmOffset); i++) + // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); + //printf("*************************\n"); + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreGenDisassemblerTables.inc b/white_patch_detect/capstone-master/arch/XCore/XCoreGenDisassemblerTables.inc new file mode 100644 index 0000000..fe4e670 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreGenDisassemblerTables.inc @@ -0,0 +1,853 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* * XCore Disassembler *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType)*8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTable16[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115 +/* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 10 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19 +/* 15 */ MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R +/* 19 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27 +/* 24 */ MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R +/* 27 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36 +/* 32 */ MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r +/* 36 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44 +/* 41 */ MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R +/* 44 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52 +/* 49 */ MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R +/* 52 */ MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60 +/* 57 */ MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R +/* 60 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68 +/* 65 */ MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R +/* 68 */ MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77 +/* 73 */ MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R +/* 77 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 80 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87 +/* 84 */ MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r +/* 87 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94 +/* 91 */ MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r +/* 94 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 97 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104 +/* 101 */ MCD_OPC_Decode, 111, 2, // Opcode: INITPC_2r +/* 104 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111 +/* 108 */ MCD_OPC_Decode, 105, 2, // Opcode: GETST_2r +/* 111 */ MCD_OPC_Decode, 230, 1, 3, // Opcode: STW_2rus +/* 115 */ MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233 +/* 119 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 122 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131 +/* 127 */ MCD_OPC_Decode, 152, 1, 0, // Opcode: LDSPC_0R +/* 131 */ MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140 +/* 136 */ MCD_OPC_Decode, 223, 1, 0, // Opcode: STSPC_0R +/* 140 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149 +/* 145 */ MCD_OPC_Decode, 153, 1, 0, // Opcode: LDSSR_0R +/* 149 */ MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158 +/* 154 */ MCD_OPC_Decode, 224, 1, 0, // Opcode: STSSR_0R +/* 158 */ MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167 +/* 163 */ MCD_OPC_Decode, 222, 1, 0, // Opcode: STSED_0R +/* 167 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176 +/* 172 */ MCD_OPC_Decode, 221, 1, 0, // Opcode: STET_0R +/* 176 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184 +/* 181 */ MCD_OPC_Decode, 95, 0, // Opcode: GETED_0R +/* 184 */ MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192 +/* 189 */ MCD_OPC_Decode, 96, 0, // Opcode: GETET_0R +/* 192 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 195 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203 +/* 199 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: WAITET_1R +/* 203 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211 +/* 207 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: WAITEF_1R +/* 211 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 214 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221 +/* 218 */ MCD_OPC_Decode, 109, 2, // Opcode: INITDP_2r +/* 221 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229 +/* 225 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: OUTT_2r +/* 229 */ MCD_OPC_Decode, 163, 1, 3, // Opcode: LDW_2rus +/* 233 */ MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337 +/* 237 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... +/* 240 */ MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248 +/* 245 */ MCD_OPC_Decode, 69, 0, // Opcode: DENTSP_0R +/* 248 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256 +/* 253 */ MCD_OPC_Decode, 73, 0, // Opcode: DRESTSP_0R +/* 256 */ MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264 +/* 261 */ MCD_OPC_Decode, 97, 0, // Opcode: GETID_0R +/* 264 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272 +/* 269 */ MCD_OPC_Decode, 98, 0, // Opcode: GETKEP_0R +/* 272 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280 +/* 277 */ MCD_OPC_Decode, 99, 0, // Opcode: GETKSP_0R +/* 280 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289 +/* 285 */ MCD_OPC_Decode, 151, 1, 0, // Opcode: LDSED_0R +/* 289 */ MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298 +/* 294 */ MCD_OPC_Decode, 149, 1, 0, // Opcode: LDET_0R +/* 298 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 301 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308 +/* 305 */ MCD_OPC_Decode, 92, 1, // Opcode: FREER_1r +/* 308 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316 +/* 312 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: MJOIN_1r +/* 316 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 319 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326 +/* 323 */ MCD_OPC_Decode, 112, 2, // Opcode: INITSP_2r +/* 326 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334 +/* 330 */ MCD_OPC_Decode, 197, 1, 4, // Opcode: SETD_2r +/* 334 */ MCD_OPC_Decode, 23, 5, // Opcode: ADD_3r +/* 337 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382 +/* 341 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 344 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352 +/* 348 */ MCD_OPC_Decode, 240, 1, 1, // Opcode: TSTART_1R +/* 352 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360 +/* 356 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: MSYNC_1r +/* 360 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 363 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370 +/* 367 */ MCD_OPC_Decode, 108, 2, // Opcode: INITCP_2r +/* 370 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378 +/* 374 */ MCD_OPC_Decode, 238, 1, 6, // Opcode: TSETMR_2r +/* 378 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: SUB_3r +/* 382 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416 +/* 386 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 389 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396 +/* 393 */ MCD_OPC_Decode, 36, 1, // Opcode: BLA_1r +/* 396 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403 +/* 400 */ MCD_OPC_Decode, 30, 1, // Opcode: BAU_1r +/* 403 */ MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412 +/* 409 */ MCD_OPC_Decode, 79, 2, // Opcode: EET_2r +/* 412 */ MCD_OPC_Decode, 215, 1, 5, // Opcode: SHL_3r +/* 416 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459 +/* 420 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 423 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430 +/* 427 */ MCD_OPC_Decode, 53, 1, // Opcode: BRU_1r +/* 430 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438 +/* 434 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SETSP_1r +/* 438 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 441 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448 +/* 445 */ MCD_OPC_Decode, 26, 7, // Opcode: ANDNOT_2r +/* 448 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455 +/* 452 */ MCD_OPC_Decode, 78, 2, // Opcode: EEF_2r +/* 455 */ MCD_OPC_Decode, 217, 1, 5, // Opcode: SHR_3r +/* 459 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504 +/* 463 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 466 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474 +/* 470 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SETDP_1r +/* 474 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482 +/* 478 */ MCD_OPC_Decode, 192, 1, 1, // Opcode: SETCP_1r +/* 482 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 485 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493 +/* 489 */ MCD_OPC_Decode, 212, 1, 7, // Opcode: SEXT_2r +/* 493 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501 +/* 497 */ MCD_OPC_Decode, 213, 1, 8, // Opcode: SEXT_rus +/* 501 */ MCD_OPC_Decode, 86, 5, // Opcode: EQ_3r +/* 504 */ MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547 +/* 508 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 511 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518 +/* 515 */ MCD_OPC_Decode, 70, 1, // Opcode: DGETREG_1r +/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 +/* 522 */ MCD_OPC_Decode, 198, 1, 1, // Opcode: SETEV_1r +/* 526 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 529 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536 +/* 533 */ MCD_OPC_Decode, 106, 2, // Opcode: GETTS_2r +/* 536 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544 +/* 540 */ MCD_OPC_Decode, 203, 1, 4, // Opcode: SETPT_2r +/* 544 */ MCD_OPC_Decode, 27, 5, // Opcode: AND_3r +/* 547 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592 +/* 551 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 554 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561 +/* 558 */ MCD_OPC_Decode, 118, 1, // Opcode: KCALL_1r +/* 561 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569 +/* 565 */ MCD_OPC_Decode, 211, 1, 1, // Opcode: SETV_1r +/* 569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 572 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580 +/* 576 */ MCD_OPC_Decode, 245, 1, 7, // Opcode: ZEXT_2r +/* 580 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588 +/* 584 */ MCD_OPC_Decode, 246, 1, 8, // Opcode: ZEXT_rus +/* 588 */ MCD_OPC_Decode, 178, 1, 5, // Opcode: OR_3r +/* 592 */ MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636 +/* 596 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 599 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606 +/* 603 */ MCD_OPC_Decode, 75, 1, // Opcode: ECALLF_1r +/* 606 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613 +/* 610 */ MCD_OPC_Decode, 76, 1, // Opcode: ECALLT_1r +/* 613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 616 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624 +/* 620 */ MCD_OPC_Decode, 179, 1, 2, // Opcode: OUTCT_2r +/* 624 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632 +/* 628 */ MCD_OPC_Decode, 180, 1, 9, // Opcode: OUTCT_rus +/* 632 */ MCD_OPC_Decode, 164, 1, 5, // Opcode: LDW_3r +/* 636 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659 +/* 640 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 643 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651 +/* 647 */ MCD_OPC_Decode, 226, 1, 10, // Opcode: STWDP_ru6 +/* 651 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 1221 +/* 655 */ MCD_OPC_Decode, 229, 1, 10, // Opcode: STWSP_ru6 +/* 659 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682 +/* 663 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 666 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674 +/* 670 */ MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWDP_ru6 +/* 674 */ MCD_OPC_FilterValue, 1, 31, 2, // Skip to: 1221 +/* 678 */ MCD_OPC_Decode, 162, 1, 10, // Opcode: LDWSP_ru6 +/* 682 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705 +/* 686 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 689 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697 +/* 693 */ MCD_OPC_Decode, 141, 1, 10, // Opcode: LDAWDP_ru6 +/* 697 */ MCD_OPC_FilterValue, 1, 8, 2, // Skip to: 1221 +/* 701 */ MCD_OPC_Decode, 146, 1, 10, // Opcode: LDAWSP_ru6 +/* 705 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728 +/* 709 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 712 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720 +/* 716 */ MCD_OPC_Decode, 148, 1, 10, // Opcode: LDC_ru6 +/* 720 */ MCD_OPC_FilterValue, 1, 241, 1, // Skip to: 1221 +/* 724 */ MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWCP_ru6 +/* 728 */ MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812 +/* 732 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 735 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773 +/* 739 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 742 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749 +/* 746 */ MCD_OPC_Decode, 52, 11, // Opcode: BRFU_u6 +/* 749 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756 +/* 753 */ MCD_OPC_Decode, 35, 11, // Opcode: BLAT_u6 +/* 756 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763 +/* 760 */ MCD_OPC_Decode, 88, 11, // Opcode: EXTDP_u6 +/* 763 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770 +/* 767 */ MCD_OPC_Decode, 120, 11, // Opcode: KCALL_u6 +/* 770 */ MCD_OPC_Decode, 50, 12, // Opcode: BRFT_ru6 +/* 773 */ MCD_OPC_FilterValue, 1, 188, 1, // Skip to: 1221 +/* 777 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 780 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787 +/* 784 */ MCD_OPC_Decode, 46, 13, // Opcode: BRBU_u6 +/* 787 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794 +/* 791 */ MCD_OPC_Decode, 84, 11, // Opcode: ENTSP_u6 +/* 794 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801 +/* 798 */ MCD_OPC_Decode, 90, 11, // Opcode: EXTSP_u6 +/* 801 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809 +/* 805 */ MCD_OPC_Decode, 189, 1, 11, // Opcode: RETSP_u6 +/* 809 */ MCD_OPC_Decode, 44, 14, // Opcode: BRBT_ru6 +/* 812 */ MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883 +/* 816 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 819 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858 +/* 823 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 826 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833 +/* 830 */ MCD_OPC_Decode, 64, 11, // Opcode: CLRSR_u6 +/* 833 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841 +/* 837 */ MCD_OPC_Decode, 209, 1, 11, // Opcode: SETSR_u6 +/* 841 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848 +/* 845 */ MCD_OPC_Decode, 122, 11, // Opcode: KENTSP_u6 +/* 848 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855 +/* 852 */ MCD_OPC_Decode, 124, 11, // Opcode: KRESTSP_u6 +/* 855 */ MCD_OPC_Decode, 48, 12, // Opcode: BRFF_ru6 +/* 858 */ MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 1221 +/* 862 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 865 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872 +/* 869 */ MCD_OPC_Decode, 104, 11, // Opcode: GETSR_u6 +/* 872 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880 +/* 876 */ MCD_OPC_Decode, 139, 1, 11, // Opcode: LDAWCP_u6 +/* 880 */ MCD_OPC_Decode, 42, 14, // Opcode: BRBF_ru6 +/* 883 */ MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925 +/* 887 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... +/* 890 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897 +/* 894 */ MCD_OPC_Decode, 60, 1, // Opcode: CLRPT_1R +/* 897 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905 +/* 901 */ MCD_OPC_Decode, 234, 1, 1, // Opcode: SYNCR_1r +/* 905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 908 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915 +/* 912 */ MCD_OPC_Decode, 102, 9, // Opcode: GETR_rus +/* 915 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922 +/* 919 */ MCD_OPC_Decode, 107, 2, // Opcode: INCT_2r +/* 922 */ MCD_OPC_Decode, 127, 5, // Opcode: LD16S_3r +/* 925 */ MCD_OPC_FilterValue, 17, 22, 0, // Skip to: 951 +/* 929 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 932 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940 +/* 936 */ MCD_OPC_Decode, 177, 1, 2, // Opcode: NOT +/* 940 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947 +/* 944 */ MCD_OPC_Decode, 115, 2, // Opcode: INT_2r +/* 947 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: LD8U_3r +/* 951 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 976 +/* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 958 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 966 +/* 962 */ MCD_OPC_Decode, 176, 1, 2, // Opcode: NEG +/* 966 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 973 +/* 970 */ MCD_OPC_Decode, 82, 2, // Opcode: ENDIN_2r +/* 973 */ MCD_OPC_Decode, 22, 3, // Opcode: ADD_2rus +/* 976 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 984 +/* 980 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: SUB_2rus +/* 984 */ MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1011 +/* 988 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 991 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 999 +/* 995 */ MCD_OPC_Decode, 172, 1, 2, // Opcode: MKMSK_2r +/* 999 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1007 +/* 1003 */ MCD_OPC_Decode, 173, 1, 15, // Opcode: MKMSK_rus +/* 1007 */ MCD_OPC_Decode, 214, 1, 16, // Opcode: SHL_2rus +/* 1011 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1038 +/* 1015 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1018 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1026 +/* 1022 */ MCD_OPC_Decode, 184, 1, 4, // Opcode: OUT_2r +/* 1026 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1034 +/* 1030 */ MCD_OPC_Decode, 182, 1, 7, // Opcode: OUTSHR_2r +/* 1034 */ MCD_OPC_Decode, 216, 1, 16, // Opcode: SHR_2rus +/* 1038 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1062 +/* 1042 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1045 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1052 +/* 1049 */ MCD_OPC_Decode, 116, 2, // Opcode: IN_2r +/* 1052 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1059 +/* 1056 */ MCD_OPC_Decode, 114, 7, // Opcode: INSHR_2r +/* 1059 */ MCD_OPC_Decode, 85, 3, // Opcode: EQ_2rus +/* 1062 */ MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1089 +/* 1066 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1069 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1077 +/* 1073 */ MCD_OPC_Decode, 185, 1, 2, // Opcode: PEEK_2r +/* 1077 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1085 +/* 1081 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: TESTCT_2r +/* 1085 */ MCD_OPC_Decode, 239, 1, 17, // Opcode: TSETR_3r +/* 1089 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1116 +/* 1093 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1096 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1104 +/* 1100 */ MCD_OPC_Decode, 201, 1, 4, // Opcode: SETPSC_2r +/* 1104 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1112 +/* 1108 */ MCD_OPC_Decode, 237, 1, 2, // Opcode: TESTWCT_2r +/* 1112 */ MCD_OPC_Decode, 166, 1, 5, // Opcode: LSS_3r +/* 1116 */ MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1141 +/* 1120 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1123 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1130 +/* 1127 */ MCD_OPC_Decode, 57, 2, // Opcode: CHKCT_2r +/* 1130 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1137 +/* 1134 */ MCD_OPC_Decode, 58, 15, // Opcode: CHKCT_rus +/* 1137 */ MCD_OPC_Decode, 168, 1, 5, // Opcode: LSU_3r +/* 1141 */ MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1162 +/* 1145 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 1148 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1155 +/* 1152 */ MCD_OPC_Decode, 40, 18, // Opcode: BLRF_u10 +/* 1155 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1221 +/* 1159 */ MCD_OPC_Decode, 38, 19, // Opcode: BLRB_u10 +/* 1162 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1185 +/* 1166 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 1169 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1177 +/* 1173 */ MCD_OPC_Decode, 135, 1, 18, // Opcode: LDAPF_u10 +/* 1177 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1221 +/* 1181 */ MCD_OPC_Decode, 132, 1, 19, // Opcode: LDAPB_u10 +/* 1185 */ MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1207 +/* 1189 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 1192 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1199 +/* 1196 */ MCD_OPC_Decode, 33, 18, // Opcode: BLACP_u10 +/* 1199 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1221 +/* 1203 */ MCD_OPC_Decode, 157, 1, 18, // Opcode: LDWCP_u10 +/* 1207 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1221 +/* 1211 */ MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1221 +/* 1217 */ MCD_OPC_Decode, 195, 1, 12, // Opcode: SETC_ru6 +/* 1221 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTable32[] = { +/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... +/* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96 +/* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 10 */ MCD_OPC_FilterValue, 31, 216, 3, // Skip to: 998 +/* 14 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 17 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31 +/* 21 */ MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45 +/* 28 */ MCD_OPC_Decode, 31, 20, // Opcode: BITREV_l2r +/* 31 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45 +/* 35 */ MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45 +/* 42 */ MCD_OPC_Decode, 56, 20, // Opcode: BYTEREV_l2r +/* 45 */ MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56 +/* 52 */ MCD_OPC_Decode, 231, 1, 21, // Opcode: STW_l3r +/* 56 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ... +/* 59 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66 +/* 63 */ MCD_OPC_Decode, 66, 22, // Opcode: CRC8_l4r +/* 66 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74 +/* 70 */ MCD_OPC_Decode, 170, 1, 23, // Opcode: MACCU_l4r +/* 74 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 77 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85 +/* 81 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: LDIVU_l5r +/* 85 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92 +/* 89 */ MCD_OPC_Decode, 126, 24, // Opcode: LADD_l5r +/* 92 */ MCD_OPC_Decode, 165, 1, 25, // Opcode: LMUL_l6r +/* 96 */ MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186 +/* 100 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 103 */ MCD_OPC_FilterValue, 31, 123, 3, // Skip to: 998 +/* 107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 110 */ MCD_OPC_FilterValue, 0, 116, 3, // Skip to: 998 +/* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 117 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136 +/* 121 */ MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156 +/* 127 */ MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156 +/* 133 */ MCD_OPC_Decode, 65, 20, // Opcode: CLZ_l2r +/* 136 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156 +/* 140 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156 +/* 146 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156 +/* 152 */ MCD_OPC_Decode, 191, 1, 26, // Opcode: SETCLK_l2r +/* 156 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172 +/* 162 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172 +/* 168 */ MCD_OPC_Decode, 244, 1, 21, // Opcode: XOR_l3r +/* 172 */ MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182 +/* 178 */ MCD_OPC_Decode, 169, 1, 23, // Opcode: MACCS_l4r +/* 182 */ MCD_OPC_Decode, 167, 1, 24, // Opcode: LSUB_l5r +/* 186 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219 +/* 190 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 193 */ MCD_OPC_FilterValue, 159, 251, 3, 31, 3, // Skip to: 998 +/* 199 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 202 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209 +/* 206 */ MCD_OPC_Decode, 110, 20, // Opcode: INITLR_l2r +/* 209 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216 +/* 213 */ MCD_OPC_Decode, 101, 20, // Opcode: GETPS_l2r +/* 216 */ MCD_OPC_Decode, 29, 21, // Opcode: ASHR_l3r +/* 219 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254 +/* 223 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 226 */ MCD_OPC_FilterValue, 159, 251, 3, 254, 2, // Skip to: 998 +/* 232 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 235 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243 +/* 239 */ MCD_OPC_Decode, 202, 1, 26, // Opcode: SETPS_l2r +/* 243 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250 +/* 247 */ MCD_OPC_Decode, 94, 20, // Opcode: GETD_l2r +/* 250 */ MCD_OPC_Decode, 144, 1, 21, // Opcode: LDAWF_l3r +/* 254 */ MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290 +/* 258 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 261 */ MCD_OPC_FilterValue, 159, 251, 3, 219, 2, // Skip to: 998 +/* 267 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 270 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278 +/* 274 */ MCD_OPC_Decode, 236, 1, 20, // Opcode: TESTLCL_l2r +/* 278 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286 +/* 282 */ MCD_OPC_Decode, 210, 1, 26, // Opcode: SETTW_l2r +/* 286 */ MCD_OPC_Decode, 137, 1, 21, // Opcode: LDAWB_l3r +/* 290 */ MCD_OPC_FilterValue, 5, 32, 0, // Skip to: 326 +/* 294 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 297 */ MCD_OPC_FilterValue, 159, 251, 3, 183, 2, // Skip to: 998 +/* 303 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 306 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314 +/* 310 */ MCD_OPC_Decode, 204, 1, 26, // Opcode: SETRDY_l2r +/* 314 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322 +/* 318 */ MCD_OPC_Decode, 193, 1, 20, // Opcode: SETC_l2r +/* 322 */ MCD_OPC_Decode, 130, 1, 21, // Opcode: LDA16F_l3r +/* 326 */ MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 361 +/* 330 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 333 */ MCD_OPC_FilterValue, 159, 251, 3, 147, 2, // Skip to: 998 +/* 339 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 342 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 350 +/* 346 */ MCD_OPC_Decode, 200, 1, 26, // Opcode: SETN_l2r +/* 350 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 357 +/* 354 */ MCD_OPC_Decode, 100, 20, // Opcode: GETN_l2r +/* 357 */ MCD_OPC_Decode, 129, 1, 21, // Opcode: LDA16B_l3r +/* 361 */ MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 377 +/* 365 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 998 +/* 373 */ MCD_OPC_Decode, 175, 1, 21, // Opcode: MUL_l3r +/* 377 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 392 +/* 381 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 998 +/* 389 */ MCD_OPC_Decode, 71, 21, // Opcode: DIVS_l3r +/* 392 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 407 +/* 396 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 998 +/* 404 */ MCD_OPC_Decode, 72, 21, // Opcode: DIVU_l3r +/* 407 */ MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 442 +/* 411 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 414 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 428 +/* 418 */ MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 998 +/* 424 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: STWDP_lru6 +/* 428 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 998 +/* 432 */ MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 998 +/* 438 */ MCD_OPC_Decode, 228, 1, 27, // Opcode: STWSP_lru6 +/* 442 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 477 +/* 446 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 449 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 463 +/* 453 */ MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 998 +/* 459 */ MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWDP_lru6 +/* 463 */ MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 998 +/* 467 */ MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 998 +/* 473 */ MCD_OPC_Decode, 161, 1, 27, // Opcode: LDWSP_lru6 +/* 477 */ MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 512 +/* 481 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 498 +/* 488 */ MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 998 +/* 494 */ MCD_OPC_Decode, 140, 1, 27, // Opcode: LDAWDP_lru6 +/* 498 */ MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 998 +/* 502 */ MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 998 +/* 508 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: LDAWSP_lru6 +/* 512 */ MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 547 +/* 516 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 519 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 533 +/* 523 */ MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 998 +/* 529 */ MCD_OPC_Decode, 147, 1, 27, // Opcode: LDC_lru6 +/* 533 */ MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 998 +/* 537 */ MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 998 +/* 543 */ MCD_OPC_Decode, 154, 1, 27, // Opcode: LDWCP_lru6 +/* 547 */ MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 645 +/* 551 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 554 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 599 +/* 558 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 561 */ MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 998 +/* 565 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 568 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 575 +/* 572 */ MCD_OPC_Decode, 51, 28, // Opcode: BRFU_lu6 +/* 575 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 582 +/* 579 */ MCD_OPC_Decode, 34, 28, // Opcode: BLAT_lu6 +/* 582 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 589 +/* 586 */ MCD_OPC_Decode, 87, 28, // Opcode: EXTDP_lu6 +/* 589 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 596 +/* 593 */ MCD_OPC_Decode, 119, 28, // Opcode: KCALL_lu6 +/* 596 */ MCD_OPC_Decode, 49, 29, // Opcode: BRFT_lru6 +/* 599 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 998 +/* 603 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 606 */ MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 998 +/* 610 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 613 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 620 +/* 617 */ MCD_OPC_Decode, 45, 30, // Opcode: BRBU_lu6 +/* 620 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 627 +/* 624 */ MCD_OPC_Decode, 83, 28, // Opcode: ENTSP_lu6 +/* 627 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 634 +/* 631 */ MCD_OPC_Decode, 89, 28, // Opcode: EXTSP_lu6 +/* 634 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 642 +/* 638 */ MCD_OPC_Decode, 188, 1, 28, // Opcode: RETSP_lu6 +/* 642 */ MCD_OPC_Decode, 43, 31, // Opcode: BRBT_lru6 +/* 645 */ MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 730 +/* 649 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 652 */ MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 698 +/* 656 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 659 */ MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 998 +/* 663 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 666 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 673 +/* 670 */ MCD_OPC_Decode, 63, 28, // Opcode: CLRSR_lu6 +/* 673 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 681 +/* 677 */ MCD_OPC_Decode, 208, 1, 28, // Opcode: SETSR_lu6 +/* 681 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 688 +/* 685 */ MCD_OPC_Decode, 121, 28, // Opcode: KENTSP_lu6 +/* 688 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 695 +/* 692 */ MCD_OPC_Decode, 123, 28, // Opcode: KRESTSP_lu6 +/* 695 */ MCD_OPC_Decode, 47, 29, // Opcode: BRFF_lru6 +/* 698 */ MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 998 +/* 702 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 705 */ MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 998 +/* 709 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 712 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 719 +/* 716 */ MCD_OPC_Decode, 103, 28, // Opcode: GETSR_lu6 +/* 719 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 727 +/* 723 */ MCD_OPC_Decode, 138, 1, 28, // Opcode: LDAWCP_lu6 +/* 727 */ MCD_OPC_Decode, 41, 31, // Opcode: BRBF_lru6 +/* 730 */ MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 746 +/* 734 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 998 +/* 742 */ MCD_OPC_Decode, 219, 1, 21, // Opcode: ST16_l3r +/* 746 */ MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 762 +/* 750 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 998 +/* 758 */ MCD_OPC_Decode, 220, 1, 21, // Opcode: ST8_l3r +/* 762 */ MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 797 +/* 766 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... +/* 769 */ MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 778 +/* 775 */ MCD_OPC_Decode, 28, 32, // Opcode: ASHR_l2rus +/* 778 */ MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 788 +/* 784 */ MCD_OPC_Decode, 181, 1, 32, // Opcode: OUTPW_l2rus +/* 788 */ MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 998 +/* 794 */ MCD_OPC_Decode, 113, 32, // Opcode: INPW_l2rus +/* 797 */ MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 813 +/* 801 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 998 +/* 809 */ MCD_OPC_Decode, 143, 1, 33, // Opcode: LDAWF_l2rus +/* 813 */ MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 829 +/* 817 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 998 +/* 825 */ MCD_OPC_Decode, 136, 1, 33, // Opcode: LDAWB_l2rus +/* 829 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 844 +/* 833 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 998 +/* 841 */ MCD_OPC_Decode, 67, 34, // Opcode: CRC_l3r +/* 844 */ MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 860 +/* 848 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 998 +/* 856 */ MCD_OPC_Decode, 186, 1, 21, // Opcode: REMS_l3r +/* 860 */ MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 876 +/* 864 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 998 +/* 872 */ MCD_OPC_Decode, 187, 1, 21, // Opcode: REMU_l3r +/* 876 */ MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 909 +/* 880 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 883 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 896 +/* 887 */ MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 998 +/* 893 */ MCD_OPC_Decode, 39, 35, // Opcode: BLRF_lu10 +/* 896 */ MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 998 +/* 900 */ MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 998 +/* 906 */ MCD_OPC_Decode, 37, 36, // Opcode: BLRB_lu10 +/* 909 */ MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 944 +/* 913 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 916 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 930 +/* 920 */ MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 998 +/* 926 */ MCD_OPC_Decode, 133, 1, 35, // Opcode: LDAPF_lu10 +/* 930 */ MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 998 +/* 934 */ MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 998 +/* 940 */ MCD_OPC_Decode, 131, 1, 36, // Opcode: LDAPB_lu10 +/* 944 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 978 +/* 948 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 951 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 964 +/* 955 */ MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 998 +/* 961 */ MCD_OPC_Decode, 32, 35, // Opcode: BLACP_lu10 +/* 964 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 998 +/* 968 */ MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 998 +/* 974 */ MCD_OPC_Decode, 155, 1, 35, // Opcode: LDWCP_lu10 +/* 978 */ MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 998 +/* 982 */ MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 998 +/* 988 */ MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 998 +/* 994 */ MCD_OPC_Decode, 194, 1, 29, // Opcode: SETC_lru6 +/* 998 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +{ + return true; //llvm_unreachable("Invalid index!"); +} + +#define DecodeToMCInst(fname,fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, const void *Decoder) \ +{ \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 2: \ + if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 3: \ + if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 4: \ + if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 5: \ + if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 6: \ + if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 7: \ + if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 8: \ + if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 9: \ + if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 10: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 13: \ + tmp = fieldname(insn, 0, 6); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 14: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 6); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 15: \ + if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 16: \ + if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 17: \ + if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 18: \ + tmp = fieldname(insn, 0, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 19: \ + tmp = fieldname(insn, 0, 10); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 20: \ + if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 21: \ + if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 22: \ + if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 23: \ + if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 24: \ + if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 25: \ + if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 26: \ + if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 27: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 6); \ + tmp |= (fieldname(insn, 16, 6) << 0); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 28: \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 6); \ + tmp |= (fieldname(insn, 16, 6) << 0); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 29: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 6); \ + tmp |= (fieldname(insn, 16, 6) << 0); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 30: \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 6); \ + tmp |= (fieldname(insn, 16, 6) << 0); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 31: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 6); \ + tmp |= (fieldname(insn, 16, 6) << 0); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 32: \ + if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 33: \ + if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 34: \ + if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + case 35: \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 10); \ + tmp |= (fieldname(insn, 16, 10) << 0); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 36: \ + tmp = 0; \ + tmp |= (fieldname(insn, 0, 10) << 10); \ + tmp |= (fieldname(insn, 16, 10) << 0); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ +{ \ + uint64_t Bits = getFeatureBits(feature); \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0, ExpectedValue; \ + DecodeStatus S = MCDisassembler_Success; \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail; \ + for (;;) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + Pred = checkDecoderPredicate(PIdx, Bits); \ + if (!Pred) \ + Ptr += NumToSkip; \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_setOpcode(MI, Opc); \ + return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + } \ + case MCD_OPC_SoftFail: { \ + PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ +} + + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) +DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) +DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreGenInstrInfo.inc b/white_patch_detect/capstone-master/arch/XCore/XCoreGenInstrInfo.inc new file mode 100644 index 0000000..7f579f1 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreGenInstrInfo.inc @@ -0,0 +1,267 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Instruction Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + XCore_PHI = 0, + XCore_INLINEASM = 1, + XCore_CFI_INSTRUCTION = 2, + XCore_EH_LABEL = 3, + XCore_GC_LABEL = 4, + XCore_KILL = 5, + XCore_EXTRACT_SUBREG = 6, + XCore_INSERT_SUBREG = 7, + XCore_IMPLICIT_DEF = 8, + XCore_SUBREG_TO_REG = 9, + XCore_COPY_TO_REGCLASS = 10, + XCore_DBG_VALUE = 11, + XCore_REG_SEQUENCE = 12, + XCore_COPY = 13, + XCore_BUNDLE = 14, + XCore_LIFETIME_START = 15, + XCore_LIFETIME_END = 16, + XCore_STACKMAP = 17, + XCore_PATCHPOINT = 18, + XCore_LOAD_STACK_GUARD = 19, + XCore_STATEPOINT = 20, + XCore_FRAME_ALLOC = 21, + XCore_ADD_2rus = 22, + XCore_ADD_3r = 23, + XCore_ADJCALLSTACKDOWN = 24, + XCore_ADJCALLSTACKUP = 25, + XCore_ANDNOT_2r = 26, + XCore_AND_3r = 27, + XCore_ASHR_l2rus = 28, + XCore_ASHR_l3r = 29, + XCore_BAU_1r = 30, + XCore_BITREV_l2r = 31, + XCore_BLACP_lu10 = 32, + XCore_BLACP_u10 = 33, + XCore_BLAT_lu6 = 34, + XCore_BLAT_u6 = 35, + XCore_BLA_1r = 36, + XCore_BLRB_lu10 = 37, + XCore_BLRB_u10 = 38, + XCore_BLRF_lu10 = 39, + XCore_BLRF_u10 = 40, + XCore_BRBF_lru6 = 41, + XCore_BRBF_ru6 = 42, + XCore_BRBT_lru6 = 43, + XCore_BRBT_ru6 = 44, + XCore_BRBU_lu6 = 45, + XCore_BRBU_u6 = 46, + XCore_BRFF_lru6 = 47, + XCore_BRFF_ru6 = 48, + XCore_BRFT_lru6 = 49, + XCore_BRFT_ru6 = 50, + XCore_BRFU_lu6 = 51, + XCore_BRFU_u6 = 52, + XCore_BRU_1r = 53, + XCore_BR_JT = 54, + XCore_BR_JT32 = 55, + XCore_BYTEREV_l2r = 56, + XCore_CHKCT_2r = 57, + XCore_CHKCT_rus = 58, + XCore_CLRE_0R = 59, + XCore_CLRPT_1R = 60, + XCore_CLRSR_branch_lu6 = 61, + XCore_CLRSR_branch_u6 = 62, + XCore_CLRSR_lu6 = 63, + XCore_CLRSR_u6 = 64, + XCore_CLZ_l2r = 65, + XCore_CRC8_l4r = 66, + XCore_CRC_l3r = 67, + XCore_DCALL_0R = 68, + XCore_DENTSP_0R = 69, + XCore_DGETREG_1r = 70, + XCore_DIVS_l3r = 71, + XCore_DIVU_l3r = 72, + XCore_DRESTSP_0R = 73, + XCore_DRET_0R = 74, + XCore_ECALLF_1r = 75, + XCore_ECALLT_1r = 76, + XCore_EDU_1r = 77, + XCore_EEF_2r = 78, + XCore_EET_2r = 79, + XCore_EEU_1r = 80, + XCore_EH_RETURN = 81, + XCore_ENDIN_2r = 82, + XCore_ENTSP_lu6 = 83, + XCore_ENTSP_u6 = 84, + XCore_EQ_2rus = 85, + XCore_EQ_3r = 86, + XCore_EXTDP_lu6 = 87, + XCore_EXTDP_u6 = 88, + XCore_EXTSP_lu6 = 89, + XCore_EXTSP_u6 = 90, + XCore_FRAME_TO_ARGS_OFFSET = 91, + XCore_FREER_1r = 92, + XCore_FREET_0R = 93, + XCore_GETD_l2r = 94, + XCore_GETED_0R = 95, + XCore_GETET_0R = 96, + XCore_GETID_0R = 97, + XCore_GETKEP_0R = 98, + XCore_GETKSP_0R = 99, + XCore_GETN_l2r = 100, + XCore_GETPS_l2r = 101, + XCore_GETR_rus = 102, + XCore_GETSR_lu6 = 103, + XCore_GETSR_u6 = 104, + XCore_GETST_2r = 105, + XCore_GETTS_2r = 106, + XCore_INCT_2r = 107, + XCore_INITCP_2r = 108, + XCore_INITDP_2r = 109, + XCore_INITLR_l2r = 110, + XCore_INITPC_2r = 111, + XCore_INITSP_2r = 112, + XCore_INPW_l2rus = 113, + XCore_INSHR_2r = 114, + XCore_INT_2r = 115, + XCore_IN_2r = 116, + XCore_Int_MemBarrier = 117, + XCore_KCALL_1r = 118, + XCore_KCALL_lu6 = 119, + XCore_KCALL_u6 = 120, + XCore_KENTSP_lu6 = 121, + XCore_KENTSP_u6 = 122, + XCore_KRESTSP_lu6 = 123, + XCore_KRESTSP_u6 = 124, + XCore_KRET_0R = 125, + XCore_LADD_l5r = 126, + XCore_LD16S_3r = 127, + XCore_LD8U_3r = 128, + XCore_LDA16B_l3r = 129, + XCore_LDA16F_l3r = 130, + XCore_LDAPB_lu10 = 131, + XCore_LDAPB_u10 = 132, + XCore_LDAPF_lu10 = 133, + XCore_LDAPF_lu10_ba = 134, + XCore_LDAPF_u10 = 135, + XCore_LDAWB_l2rus = 136, + XCore_LDAWB_l3r = 137, + XCore_LDAWCP_lu6 = 138, + XCore_LDAWCP_u6 = 139, + XCore_LDAWDP_lru6 = 140, + XCore_LDAWDP_ru6 = 141, + XCore_LDAWFI = 142, + XCore_LDAWF_l2rus = 143, + XCore_LDAWF_l3r = 144, + XCore_LDAWSP_lru6 = 145, + XCore_LDAWSP_ru6 = 146, + XCore_LDC_lru6 = 147, + XCore_LDC_ru6 = 148, + XCore_LDET_0R = 149, + XCore_LDIVU_l5r = 150, + XCore_LDSED_0R = 151, + XCore_LDSPC_0R = 152, + XCore_LDSSR_0R = 153, + XCore_LDWCP_lru6 = 154, + XCore_LDWCP_lu10 = 155, + XCore_LDWCP_ru6 = 156, + XCore_LDWCP_u10 = 157, + XCore_LDWDP_lru6 = 158, + XCore_LDWDP_ru6 = 159, + XCore_LDWFI = 160, + XCore_LDWSP_lru6 = 161, + XCore_LDWSP_ru6 = 162, + XCore_LDW_2rus = 163, + XCore_LDW_3r = 164, + XCore_LMUL_l6r = 165, + XCore_LSS_3r = 166, + XCore_LSUB_l5r = 167, + XCore_LSU_3r = 168, + XCore_MACCS_l4r = 169, + XCore_MACCU_l4r = 170, + XCore_MJOIN_1r = 171, + XCore_MKMSK_2r = 172, + XCore_MKMSK_rus = 173, + XCore_MSYNC_1r = 174, + XCore_MUL_l3r = 175, + XCore_NEG = 176, + XCore_NOT = 177, + XCore_OR_3r = 178, + XCore_OUTCT_2r = 179, + XCore_OUTCT_rus = 180, + XCore_OUTPW_l2rus = 181, + XCore_OUTSHR_2r = 182, + XCore_OUTT_2r = 183, + XCore_OUT_2r = 184, + XCore_PEEK_2r = 185, + XCore_REMS_l3r = 186, + XCore_REMU_l3r = 187, + XCore_RETSP_lu6 = 188, + XCore_RETSP_u6 = 189, + XCore_SELECT_CC = 190, + XCore_SETCLK_l2r = 191, + XCore_SETCP_1r = 192, + XCore_SETC_l2r = 193, + XCore_SETC_lru6 = 194, + XCore_SETC_ru6 = 195, + XCore_SETDP_1r = 196, + XCore_SETD_2r = 197, + XCore_SETEV_1r = 198, + XCore_SETKEP_0R = 199, + XCore_SETN_l2r = 200, + XCore_SETPSC_2r = 201, + XCore_SETPS_l2r = 202, + XCore_SETPT_2r = 203, + XCore_SETRDY_l2r = 204, + XCore_SETSP_1r = 205, + XCore_SETSR_branch_lu6 = 206, + XCore_SETSR_branch_u6 = 207, + XCore_SETSR_lu6 = 208, + XCore_SETSR_u6 = 209, + XCore_SETTW_l2r = 210, + XCore_SETV_1r = 211, + XCore_SEXT_2r = 212, + XCore_SEXT_rus = 213, + XCore_SHL_2rus = 214, + XCore_SHL_3r = 215, + XCore_SHR_2rus = 216, + XCore_SHR_3r = 217, + XCore_SSYNC_0r = 218, + XCore_ST16_l3r = 219, + XCore_ST8_l3r = 220, + XCore_STET_0R = 221, + XCore_STSED_0R = 222, + XCore_STSPC_0R = 223, + XCore_STSSR_0R = 224, + XCore_STWDP_lru6 = 225, + XCore_STWDP_ru6 = 226, + XCore_STWFI = 227, + XCore_STWSP_lru6 = 228, + XCore_STWSP_ru6 = 229, + XCore_STW_2rus = 230, + XCore_STW_l3r = 231, + XCore_SUB_2rus = 232, + XCore_SUB_3r = 233, + XCore_SYNCR_1r = 234, + XCore_TESTCT_2r = 235, + XCore_TESTLCL_l2r = 236, + XCore_TESTWCT_2r = 237, + XCore_TSETMR_2r = 238, + XCore_TSETR_3r = 239, + XCore_TSTART_1R = 240, + XCore_WAITEF_1R = 241, + XCore_WAITET_1R = 242, + XCore_WAITEU_0R = 243, + XCore_XOR_l3r = 244, + XCore_ZEXT_2r = 245, + XCore_ZEXT_rus = 246, + XCore_INSTRUCTION_LIST_END = 247 +}; + +#endif // GET_INSTRINFO_ENUM diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreGenRegisterInfo.inc b/white_patch_detect/capstone-master/arch/XCore/XCoreGenRegisterInfo.inc new file mode 100644 index 0000000..b73b2fd --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreGenRegisterInfo.inc @@ -0,0 +1,110 @@ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + XCore_NoRegister, + XCore_CP = 1, + XCore_DP = 2, + XCore_LR = 3, + XCore_SP = 4, + XCore_R0 = 5, + XCore_R1 = 6, + XCore_R2 = 7, + XCore_R3 = 8, + XCore_R4 = 9, + XCore_R5 = 10, + XCore_R6 = 11, + XCore_R7 = 12, + XCore_R8 = 13, + XCore_R9 = 14, + XCore_R10 = 15, + XCore_R11 = 16, + XCore_NUM_TARGET_REGS // 17 +}; + +// Register classes +enum { + XCore_RRegsRegClassID = 0, + XCore_GRRegsRegClassID = 1 +}; + +#endif // GET_REGINFO_ENUM + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|*MC Register Information *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg XCoreRegDiffLists[] = { + /* 0 */ 65535, 0, +}; + +static const uint16_t XCoreSubRegIdxLists[] = { + /* 0 */ 0, +}; + +static MCRegisterDesc XCoreRegDesc[] = { // Descriptors + { 3, 0, 0, 0, 0, 0 }, + { 38, 1, 1, 0, 1, 0 }, + { 41, 1, 1, 0, 1, 0 }, + { 47, 1, 1, 0, 1, 0 }, + { 44, 1, 1, 0, 1, 0 }, + { 4, 1, 1, 0, 1, 0 }, + { 11, 1, 1, 0, 1, 0 }, + { 14, 1, 1, 0, 1, 0 }, + { 17, 1, 1, 0, 1, 0 }, + { 20, 1, 1, 0, 1, 0 }, + { 23, 1, 1, 0, 1, 0 }, + { 26, 1, 1, 0, 1, 0 }, + { 29, 1, 1, 0, 1, 0 }, + { 32, 1, 1, 0, 1, 0 }, + { 35, 1, 1, 0, 1, 0 }, + { 0, 1, 1, 0, 1, 0 }, + { 7, 1, 1, 0, 1, 0 }, +}; + + // RRegs Register Class... + static const MCPhysReg RRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR, + }; + + // RRegs Bit set. + static const uint8_t RRegsBits[] = { + 0xfe, 0xff, 0x01, + }; + + // GRRegs Register Class... + static const MCPhysReg GRRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, + }; + + // GRRegs Bit set. + static const uint8_t GRRegsBits[] = { + 0xe0, 0xff, 0x01, + }; + +static MCRegisterClass XCoreMCRegisterClasses[] = { + { RRegs, RRegsBits, 1, 16, sizeof(RRegsBits), XCore_RRegsRegClassID, 4, 4, 1, 0 }, + { GRRegs, GRRegsBits, 0, 12, sizeof(GRRegsBits), XCore_GRRegsRegClassID, 4, 4, 1, 1 }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.c b/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.c new file mode 100644 index 0000000..fcd0205 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.c @@ -0,0 +1,250 @@ +//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an XCore MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_XCORE + +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#pragma warning(disable : 4996) // disable MSVC's warning on strcpy() +#pragma warning(disable : 28719) // disable MSVC's warning on strcpy() +#endif + +#include +#include +#include +#include + +#include "XCoreInstPrinter.h" +#include "../../MCInst.h" +#include "../../utils.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../MathExtras.h" +#include "XCoreMapping.h" + +static const char *getRegisterName(unsigned RegNo); + +void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + /* + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + */ +} + +// stw sed, sp[3] +void XCore_insn_extract(MCInst *MI, const char *code) +{ + int id; + char *p, *p2; + char tmp[128]; + + strcpy(tmp, code); // safe because code is way shorter than 128 bytes + + // find the first space + p = strchr(tmp, ' '); + if (p) { + p++; + // find the next ',' + p2 = strchr(p, ','); + if (p2) { + *p2 = '\0'; + id = XCore_reg_id(p); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + // next should be register, or memory? + // skip space + p2++; + while(*p2 && *p2 == ' ') + p2++; + if (*p2) { + // find '[' + p = p2; + while(*p && *p != '[') + p++; + if (*p) { + // this is '[' + *p = '\0'; + id = XCore_reg_id(p2); + if (id) { + // base register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; + } + + p++; + p2 = p; + // until ']' + while(*p && *p != ']') + p++; + if (*p) { + *p = '\0'; + // p2 is either index, or disp + id = XCore_reg_id(p2); + if (id) { + // index register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id; + } + } else { + // a number means disp + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2); + } + } + } + + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.op_count++; + } + } + } else { + // a register? + id = XCore_reg_id(p2); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + } + } + } else { + id = XCore_reg_id(p); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + } + } +} + +static void set_mem_access(MCInst *MI, bool status, int reg) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + if (status) { + if (reg != 0xffff && reg != -0xffff) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; + if (reg) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; + } else { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID; + } + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; + } else { + // the last op should be the memory base + MI->flat_insn->detail->xcore.op_count--; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; + if (reg > 0) + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; + else + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1; + } + } else { + if (reg) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; + // done, create the next operand slot + MI->flat_insn->detail->xcore.op_count++; + } + } +} + +static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) +{ + if (MCOperand_isReg(MO)) { + unsigned reg; + + reg = MCOperand_getReg(MO); + SStream_concat0(O, getRegisterName(reg)); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID) + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; + else + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; + } else { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg; + MI->flat_insn->detail->xcore.op_count++; + } + } + } else if (MCOperand_isImm(MO)) { + int32_t Imm = (int32_t)MCOperand_getImm(MO); + + printInt32(O, Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm; + } else { + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM; + MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm; + MI->flat_insn->detail->xcore.op_count++; + } + } + } +} + +static void printOperand(MCInst *MI, int OpNum, SStream *O) +{ + if (OpNum >= MI->size) + return; + + _printOperand(MI, MCInst_getOperand(MI, OpNum), O); +} + +static void printInlineJT(MCInst *MI, int OpNum, SStream *O) +{ +} + +static void printInlineJT32(MCInst *MI, int OpNum, SStream *O) +{ +} + +#define PRINT_ALIAS_INSTR +#include "XCoreGenAsmWriter.inc" + +void XCore_printInst(MCInst *MI, SStream *O, void *Info) +{ + printInstruction(MI, O, Info); + set_mem_access(MI, false, 0); +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.h b/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.h new file mode 100644 index 0000000..f9d0001 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreInstPrinter.h @@ -0,0 +1,18 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_XCOREINSTPRINTER_H +#define CS_XCOREINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void XCore_printInst(MCInst *MI, SStream *O, void *Info); + +void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); + +// extract details from assembly code @code +void XCore_insn_extract(MCInst *MI, const char *code); + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.c b/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.c new file mode 100644 index 0000000..2a07e12 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.c @@ -0,0 +1,297 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_XCORE + +#include // debug +#include + +#include "../../utils.h" + +#include "XCoreMapping.h" + +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" + +static const name_map reg_name_maps[] = { + { XCORE_REG_INVALID, NULL }, + + { XCORE_REG_CP, "cp" }, + { XCORE_REG_DP, "dp" }, + { XCORE_REG_LR, "lr" }, + { XCORE_REG_SP, "sp" }, + { XCORE_REG_R0, "r0" }, + { XCORE_REG_R1, "r1" }, + { XCORE_REG_R2, "r2" }, + { XCORE_REG_R3, "r3" }, + { XCORE_REG_R4, "r4" }, + { XCORE_REG_R5, "r5" }, + { XCORE_REG_R6, "r6" }, + { XCORE_REG_R7, "r7" }, + { XCORE_REG_R8, "r8" }, + { XCORE_REG_R9, "r9" }, + { XCORE_REG_R10, "r10" }, + { XCORE_REG_R11, "r11" }, + + // pseudo registers + { XCORE_REG_PC, "pc" }, + + { XCORE_REG_SCP, "scp" }, + { XCORE_REG_SSR, "ssr" }, + { XCORE_REG_ET, "et" }, + { XCORE_REG_ED, "ed" }, + { XCORE_REG_SED, "sed" }, + { XCORE_REG_KEP, "kep" }, + { XCORE_REG_KSP, "ksp" }, + { XCORE_REG_ID, "id" }, +}; + +const char *XCore_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +xcore_reg XCore_reg_id(char *name) +{ + int i; + + for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { + if (!strcmp(name, reg_name_maps[i].name)) + return reg_name_maps[i].id; + } + + // not found + return 0; +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, + +#include "XCoreMappingInsn.inc" +}; + +// given internal insn id, return public instruction info +void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned short i; + + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; + + if (h->detail) { +#ifndef CAPSTONE_DIET + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + } + } +} + +#ifndef CAPSTONE_DIET +static const name_map insn_name_maps[] = { + { XCORE_INS_INVALID, NULL }, + + { XCORE_INS_ADD, "add" }, + { XCORE_INS_ANDNOT, "andnot" }, + { XCORE_INS_AND, "and" }, + { XCORE_INS_ASHR, "ashr" }, + { XCORE_INS_BAU, "bau" }, + { XCORE_INS_BITREV, "bitrev" }, + { XCORE_INS_BLA, "bla" }, + { XCORE_INS_BLAT, "blat" }, + { XCORE_INS_BL, "bl" }, + { XCORE_INS_BF, "bf" }, + { XCORE_INS_BT, "bt" }, + { XCORE_INS_BU, "bu" }, + { XCORE_INS_BRU, "bru" }, + { XCORE_INS_BYTEREV, "byterev" }, + { XCORE_INS_CHKCT, "chkct" }, + { XCORE_INS_CLRE, "clre" }, + { XCORE_INS_CLRPT, "clrpt" }, + { XCORE_INS_CLRSR, "clrsr" }, + { XCORE_INS_CLZ, "clz" }, + { XCORE_INS_CRC8, "crc8" }, + { XCORE_INS_CRC32, "crc32" }, + { XCORE_INS_DCALL, "dcall" }, + { XCORE_INS_DENTSP, "dentsp" }, + { XCORE_INS_DGETREG, "dgetreg" }, + { XCORE_INS_DIVS, "divs" }, + { XCORE_INS_DIVU, "divu" }, + { XCORE_INS_DRESTSP, "drestsp" }, + { XCORE_INS_DRET, "dret" }, + { XCORE_INS_ECALLF, "ecallf" }, + { XCORE_INS_ECALLT, "ecallt" }, + { XCORE_INS_EDU, "edu" }, + { XCORE_INS_EEF, "eef" }, + { XCORE_INS_EET, "eet" }, + { XCORE_INS_EEU, "eeu" }, + { XCORE_INS_ENDIN, "endin" }, + { XCORE_INS_ENTSP, "entsp" }, + { XCORE_INS_EQ, "eq" }, + { XCORE_INS_EXTDP, "extdp" }, + { XCORE_INS_EXTSP, "extsp" }, + { XCORE_INS_FREER, "freer" }, + { XCORE_INS_FREET, "freet" }, + { XCORE_INS_GETD, "getd" }, + { XCORE_INS_GET, "get" }, + { XCORE_INS_GETN, "getn" }, + { XCORE_INS_GETR, "getr" }, + { XCORE_INS_GETSR, "getsr" }, + { XCORE_INS_GETST, "getst" }, + { XCORE_INS_GETTS, "getts" }, + { XCORE_INS_INCT, "inct" }, + { XCORE_INS_INIT, "init" }, + { XCORE_INS_INPW, "inpw" }, + { XCORE_INS_INSHR, "inshr" }, + { XCORE_INS_INT, "int" }, + { XCORE_INS_IN, "in" }, + { XCORE_INS_KCALL, "kcall" }, + { XCORE_INS_KENTSP, "kentsp" }, + { XCORE_INS_KRESTSP, "krestsp" }, + { XCORE_INS_KRET, "kret" }, + { XCORE_INS_LADD, "ladd" }, + { XCORE_INS_LD16S, "ld16s" }, + { XCORE_INS_LD8U, "ld8u" }, + { XCORE_INS_LDA16, "lda16" }, + { XCORE_INS_LDAP, "ldap" }, + { XCORE_INS_LDAW, "ldaw" }, + { XCORE_INS_LDC, "ldc" }, + { XCORE_INS_LDW, "ldw" }, + { XCORE_INS_LDIVU, "ldivu" }, + { XCORE_INS_LMUL, "lmul" }, + { XCORE_INS_LSS, "lss" }, + { XCORE_INS_LSUB, "lsub" }, + { XCORE_INS_LSU, "lsu" }, + { XCORE_INS_MACCS, "maccs" }, + { XCORE_INS_MACCU, "maccu" }, + { XCORE_INS_MJOIN, "mjoin" }, + { XCORE_INS_MKMSK, "mkmsk" }, + { XCORE_INS_MSYNC, "msync" }, + { XCORE_INS_MUL, "mul" }, + { XCORE_INS_NEG, "neg" }, + { XCORE_INS_NOT, "not" }, + { XCORE_INS_OR, "or" }, + { XCORE_INS_OUTCT, "outct" }, + { XCORE_INS_OUTPW, "outpw" }, + { XCORE_INS_OUTSHR, "outshr" }, + { XCORE_INS_OUTT, "outt" }, + { XCORE_INS_OUT, "out" }, + { XCORE_INS_PEEK, "peek" }, + { XCORE_INS_REMS, "rems" }, + { XCORE_INS_REMU, "remu" }, + { XCORE_INS_RETSP, "retsp" }, + { XCORE_INS_SETCLK, "setclk" }, + { XCORE_INS_SET, "set" }, + { XCORE_INS_SETC, "setc" }, + { XCORE_INS_SETD, "setd" }, + { XCORE_INS_SETEV, "setev" }, + { XCORE_INS_SETN, "setn" }, + { XCORE_INS_SETPSC, "setpsc" }, + { XCORE_INS_SETPT, "setpt" }, + { XCORE_INS_SETRDY, "setrdy" }, + { XCORE_INS_SETSR, "setsr" }, + { XCORE_INS_SETTW, "settw" }, + { XCORE_INS_SETV, "setv" }, + { XCORE_INS_SEXT, "sext" }, + { XCORE_INS_SHL, "shl" }, + { XCORE_INS_SHR, "shr" }, + { XCORE_INS_SSYNC, "ssync" }, + { XCORE_INS_ST16, "st16" }, + { XCORE_INS_ST8, "st8" }, + { XCORE_INS_STW, "stw" }, + { XCORE_INS_SUB, "sub" }, + { XCORE_INS_SYNCR, "syncr" }, + { XCORE_INS_TESTCT, "testct" }, + { XCORE_INS_TESTLCL, "testlcl" }, + { XCORE_INS_TESTWCT, "testwct" }, + { XCORE_INS_TSETMR, "tsetmr" }, + { XCORE_INS_START, "start" }, + { XCORE_INS_WAITEF, "waitef" }, + { XCORE_INS_WAITET, "waitet" }, + { XCORE_INS_WAITEU, "waiteu" }, + { XCORE_INS_XOR, "xor" }, + { XCORE_INS_ZEXT, "zext" }, +}; + +// special alias insn +static const name_map alias_insn_names[] = { + { 0, NULL } +}; +#endif + +const char *XCore_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + unsigned int i; + + if (id >= XCORE_INS_ENDING) + return NULL; + + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } + + return insn_name_maps[id].name; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + { XCORE_GRP_INVALID, NULL }, + { XCORE_GRP_JUMP, "jump" }, +}; +#endif + +const char *XCore_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// map internal raw register to 'public' register +xcore_reg XCore_map_register(unsigned int r) +{ + static const unsigned int map[] = { 0, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.h b/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.h new file mode 100644 index 0000000..f9b506a --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreMapping.h @@ -0,0 +1,26 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_XCORE_MAP_H +#define CS_XCORE_MAP_H + +#include "capstone/capstone.h" + +// return name of regiser in friendly string +const char *XCore_reg_name(csh handle, unsigned int reg); + +// given internal insn id, return public instruction info +void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *XCore_insn_name(csh handle, unsigned int id); + +const char *XCore_group_name(csh handle, unsigned int id); + +// map internal raw register to 'public' register +xcore_reg XCore_map_register(unsigned int r); + +// map register name to register ID +xcore_reg XCore_reg_id(char *name); + +#endif + diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreMappingInsn.inc b/white_patch_detect/capstone-master/arch/XCore/XCoreMappingInsn.inc new file mode 100644 index 0000000..7d11572 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreMappingInsn.inc @@ -0,0 +1,1287 @@ +// This is auto-gen data for Capstone engine (www.capstone-engine.org) +// By Nguyen Anh Quynh + +{ + XCore_ADD_2rus, XCORE_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ADD_3r, XCORE_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ANDNOT_2r, XCORE_INS_ANDNOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_AND_3r, XCORE_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ASHR_l2rus, XCORE_INS_ASHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ASHR_l3r, XCORE_INS_ASHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BAU_1r, XCORE_INS_BAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_BITREV_l2r, XCORE_INS_BITREV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLACP_lu10, XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLACP_u10, XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLAT_lu6, XCORE_INS_BLAT, +#ifndef CAPSTONE_DIET + { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLAT_u6, XCORE_INS_BLAT, +#ifndef CAPSTONE_DIET + { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLA_1r, XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLRB_lu10, XCORE_INS_BL, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLRB_u10, XCORE_INS_BL, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLRF_lu10, XCORE_INS_BL, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BLRF_u10, XCORE_INS_BL, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_BRBF_lru6, XCORE_INS_BF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRBF_ru6, XCORE_INS_BF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRBT_lru6, XCORE_INS_BT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRBT_ru6, XCORE_INS_BT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRBU_lu6, XCORE_INS_BU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRBU_u6, XCORE_INS_BU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFF_lru6, XCORE_INS_BF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFF_ru6, XCORE_INS_BF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFT_lru6, XCORE_INS_BT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFT_ru6, XCORE_INS_BT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFU_lu6, XCORE_INS_BU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRFU_u6, XCORE_INS_BU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 0 +#endif +}, +{ + XCore_BRU_1r, XCORE_INS_BRU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_BYTEREV_l2r, XCORE_INS_BYTEREV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CHKCT_2r, XCORE_INS_CHKCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CHKCT_rus, XCORE_INS_CHKCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CLRE_0R, XCORE_INS_CLRE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CLRPT_1R, XCORE_INS_CLRPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CLRSR_branch_lu6, XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_CLRSR_branch_u6, XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_CLRSR_lu6, XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CLRSR_u6, XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CLZ_l2r, XCORE_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CRC8_l4r, XCORE_INS_CRC8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_CRC_l3r, XCORE_INS_CRC32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DCALL_0R, XCORE_INS_DCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DENTSP_0R, XCORE_INS_DENTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DGETREG_1r, XCORE_INS_DGETREG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DIVS_l3r, XCORE_INS_DIVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DIVU_l3r, XCORE_INS_DIVU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DRESTSP_0R, XCORE_INS_DRESTSP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_DRET_0R, XCORE_INS_DRET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ECALLF_1r, XCORE_INS_ECALLF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ECALLT_1r, XCORE_INS_ECALLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EDU_1r, XCORE_INS_EDU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EEF_2r, XCORE_INS_EEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EET_2r, XCORE_INS_EET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EEU_1r, XCORE_INS_EEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ENDIN_2r, XCORE_INS_ENDIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ENTSP_lu6, XCORE_INS_ENTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ENTSP_u6, XCORE_INS_ENTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EQ_2rus, XCORE_INS_EQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EQ_3r, XCORE_INS_EQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EXTDP_lu6, XCORE_INS_EXTDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EXTDP_u6, XCORE_INS_EXTDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EXTSP_lu6, XCORE_INS_EXTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_EXTSP_u6, XCORE_INS_EXTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_FREER_1r, XCORE_INS_FREER, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_FREET_0R, XCORE_INS_FREET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETD_l2r, XCORE_INS_GETD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETED_0R, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETET_0R, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETID_0R, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETKEP_0R, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETKSP_0R, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETN_l2r, XCORE_INS_GETN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETPS_l2r, XCORE_INS_GET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETR_rus, XCORE_INS_GETR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETSR_lu6, XCORE_INS_GETSR, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETSR_u6, XCORE_INS_GETSR, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETST_2r, XCORE_INS_GETST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_GETTS_2r, XCORE_INS_GETTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INCT_2r, XCORE_INS_INCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INITCP_2r, XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INITDP_2r, XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INITLR_l2r, XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INITPC_2r, XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INITSP_2r, XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INPW_l2rus, XCORE_INS_INPW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INSHR_2r, XCORE_INS_INSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_INT_2r, XCORE_INS_INT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_IN_2r, XCORE_INS_IN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KCALL_1r, XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KCALL_lu6, XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KCALL_u6, XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KENTSP_lu6, XCORE_INS_KENTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KENTSP_u6, XCORE_INS_KENTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KRESTSP_lu6, XCORE_INS_KRESTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KRESTSP_u6, XCORE_INS_KRESTSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_KRET_0R, XCORE_INS_KRET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LADD_l5r, XCORE_INS_LADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LD16S_3r, XCORE_INS_LD16S, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LD8U_3r, XCORE_INS_LD8U, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDA16B_l3r, XCORE_INS_LDA16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDA16F_l3r, XCORE_INS_LDA16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAPB_lu10, XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAPB_u10, XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAPF_lu10, XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAPF_lu10_ba, XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAPF_u10, XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWB_l2rus, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWB_l3r, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWCP_lu6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWCP_u6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWDP_lru6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWDP_ru6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWF_l2rus, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWF_l3r, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWSP_lru6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDAWSP_ru6, XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDC_lru6, XCORE_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDC_ru6, XCORE_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDET_0R, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDIVU_l5r, XCORE_INS_LDIVU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDSED_0R, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDSPC_0R, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDSSR_0R, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWCP_lru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWCP_lu10, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWCP_ru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWCP_u10, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWDP_lru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWDP_ru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWSP_lru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDWSP_ru6, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDW_2rus, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LDW_3r, XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LMUL_l6r, XCORE_INS_LMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LSS_3r, XCORE_INS_LSS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LSUB_l5r, XCORE_INS_LSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_LSU_3r, XCORE_INS_LSU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MACCS_l4r, XCORE_INS_MACCS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MACCU_l4r, XCORE_INS_MACCU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MJOIN_1r, XCORE_INS_MJOIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MKMSK_2r, XCORE_INS_MKMSK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MKMSK_rus, XCORE_INS_MKMSK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MSYNC_1r, XCORE_INS_MSYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_MUL_l3r, XCORE_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_NEG, XCORE_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_NOT, XCORE_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OR_3r, XCORE_INS_OR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUTCT_2r, XCORE_INS_OUTCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUTCT_rus, XCORE_INS_OUTCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUTPW_l2rus, XCORE_INS_OUTPW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUTSHR_2r, XCORE_INS_OUTSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUTT_2r, XCORE_INS_OUTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_OUT_2r, XCORE_INS_OUT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_PEEK_2r, XCORE_INS_PEEK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_REMS_l3r, XCORE_INS_REMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_REMU_l3r, XCORE_INS_REMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_RETSP_lu6, XCORE_INS_RETSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_RETSP_u6, XCORE_INS_RETSP, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETCLK_l2r, XCORE_INS_SETCLK, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETCP_1r, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETC_l2r, XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETC_lru6, XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETC_ru6, XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETDP_1r, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETD_2r, XCORE_INS_SETD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETEV_1r, XCORE_INS_SETEV, +#ifndef CAPSTONE_DIET + { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETKEP_0R, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETN_l2r, XCORE_INS_SETN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETPSC_2r, XCORE_INS_SETPSC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETPS_l2r, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETPT_2r, XCORE_INS_SETPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETRDY_l2r, XCORE_INS_SETRDY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETSP_1r, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETSR_branch_lu6, XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_SETSR_branch_u6, XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_SETSR_lu6, XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETSR_u6, XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETTW_l2r, XCORE_INS_SETTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SETV_1r, XCORE_INS_SETV, +#ifndef CAPSTONE_DIET + { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SEXT_2r, XCORE_INS_SEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SEXT_rus, XCORE_INS_SEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SHL_2rus, XCORE_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SHL_3r, XCORE_INS_SHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SHR_2rus, XCORE_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SHR_3r, XCORE_INS_SHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SSYNC_0r, XCORE_INS_SSYNC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ST16_l3r, XCORE_INS_ST16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ST8_l3r, XCORE_INS_ST8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STET_0R, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STSED_0R, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STSPC_0R, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STSSR_0R, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STWDP_lru6, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STWDP_ru6, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STWSP_lru6, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STWSP_ru6, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STW_2rus, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_STW_l3r, XCORE_INS_STW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SUB_2rus, XCORE_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SUB_3r, XCORE_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_SYNCR_1r, XCORE_INS_SYNCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TESTCT_2r, XCORE_INS_TESTCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TESTLCL_l2r, XCORE_INS_TESTLCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TESTWCT_2r, XCORE_INS_TESTWCT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TSETMR_2r, XCORE_INS_TSETMR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TSETR_3r, XCORE_INS_SET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_TSTART_1R, XCORE_INS_START, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_WAITEF_1R, XCORE_INS_WAITEF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_WAITET_1R, XCORE_INS_WAITET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_WAITEU_0R, XCORE_INS_WAITEU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 1, 1 +#endif +}, +{ + XCore_XOR_l3r, XCORE_INS_XOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ZEXT_2r, XCORE_INS_ZEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, +{ + XCore_ZEXT_rus, XCORE_INS_ZEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreModule.c b/white_patch_detect/capstone-master/arch/XCore/XCoreModule.c new file mode 100644 index 0000000..90940d4 --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreModule.c @@ -0,0 +1,41 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef CAPSTONE_HAS_XCORE + +#include "../../utils.h" +#include "../../MCRegisterInfo.h" +#include "XCoreDisassembler.h" +#include "XCoreInstPrinter.h" +#include "XCoreMapping.h" +#include "XCoreModule.h" + +cs_err XCore_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + XCore_init(mri); + ud->printer = XCore_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = XCore_getInstruction; + ud->post_printer = XCore_post_printer; + + ud->reg_name = XCore_reg_name; + ud->insn_id = XCore_get_insn_id; + ud->insn_name = XCore_insn_name; + ud->group_name = XCore_group_name; + + return CS_ERR_OK; +} + +cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot + // test for CS_MODE_LITTLE_ENDIAN because it is 0 + + return CS_ERR_OK; +} + +#endif diff --git a/white_patch_detect/capstone-master/arch/XCore/XCoreModule.h b/white_patch_detect/capstone-master/arch/XCore/XCoreModule.h new file mode 100644 index 0000000..c4a7d2b --- /dev/null +++ b/white_patch_detect/capstone-master/arch/XCore/XCoreModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer , 2018 */ + +#ifndef CS_XCORE_MODULE_H +#define CS_XCORE_MODULE_H + +#include "../../utils.h" + +cs_err XCore_global_init(cs_struct *ud); +cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/white_patch_detect/capstone-master/bindings/Makefile b/white_patch_detect/capstone-master/bindings/Makefile new file mode 100644 index 0000000..099575e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/Makefile @@ -0,0 +1,100 @@ +TMPDIR = /tmp/capstone_test + +DIFF = diff -u -w + +TEST = $(TMPDIR)/test +TEST_ARM = $(TMPDIR)/test_arm +TEST_ARM64 = $(TMPDIR)/test_arm64 +TEST_M68K = $(TMPDIR)/test_m68k +TEST_MIPS = $(TMPDIR)/test_mips +TEST_MOS65XX = $(TMPDIR)/test_mos65xx +TEST_PPC = $(TMPDIR)/test_ppc +TEST_SPARC = $(TMPDIR)/test_sparc +TEST_SYSZ = $(TMPDIR)/test_systemz +TEST_X86 = $(TMPDIR)/test_x86 +TEST_XCORE = $(TMPDIR)/test_xcore + +PYTHON2 ?= python + +.PHONY: all expected python java ocaml + +all: + cd python && $(MAKE) gen_const + cd java && $(MAKE) gen_const + cd ocaml && $(MAKE) gen_const + +tests: expected python java #oclma ruby + +test_java: expected java +test_python: expected python + +expected: + cd ../tests && $(MAKE) + mkdir -p $(TMPDIR) + ../tests/test > $(TEST)_e + ../tests/test_arm > $(TEST_ARM)_e + ../tests/test_arm64 > $(TEST_ARM64)_e + ../tests/test_m68k > $(TEST_M68K)_e + ../tests/test_mips > $(TEST_MIPS)_e + ../tests/test_mos65xx > $(TEST_MOS65XX)_e + ../tests/test_ppc > $(TEST_PPC)_e + ../tests/test_sparc > $(TEST_SPARC)_e + ../tests/test_systemz > $(TEST_SYSZ)_e + ../tests/test_x86 > $(TEST_X86)_e + ../tests/test_xcore > $(TEST_XCORE)_e + +python: FORCE + cd python && $(MAKE) + $(PYTHON2) python/test.py > $(TEST)_o + $(PYTHON2) python/test_arm.py > $(TEST_ARM)_o + $(PYTHON2) python/test_arm64.py > $(TEST_ARM64)_o + $(PYTHON2) python/test_m68k.py > $(TEST_M68K)_o + $(PYTHON2) python/test_mips.py > $(TEST_MIPS)_o + $(PYTHON2) python/test_mos65xx.py > $(TEST_MOS65XX)_o + $(PYTHON2) python/test_ppc.py > $(TEST_PPC)_o + $(PYTHON2) python/test_sparc.py > $(TEST_SPARC)_o + $(PYTHON2) python/test_systemz.py > $(TEST_SYSZ)_o + $(PYTHON2) python/test_x86.py > $(TEST_X86)_o + $(PYTHON2) python/test_xcore.py > $(TEST_XCORE)_o + $(MAKE) test_diff + +java: FORCE + cd java && $(MAKE) + cd java && ./run.sh > $(TEST)_o + cd java && ./run.sh arm > $(TEST_ARM)_o + cd java && ./run.sh arm64 > $(TEST_ARM64)_o + cd java && ./run.sh mips > $(TEST_MIPS)_o + cd java && ./run.sh ppc > $(TEST_PPC)_o + cd java && ./run.sh sparc > $(TEST_SPARC)_o + cd java && ./run.sh systemz > $(TEST_SYSZ)_o + cd java && ./run.sh x86 > $(TEST_X86)_o + cd java && ./run.sh xcore > $(TEST_XCORE)_o + $(MAKE) test_diff + +ocaml: FORCE + +test_diff: FORCE + $(DIFF) $(TEST)_e $(TEST)_o + $(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o + $(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o + $(DIFF) $(TEST_M68K)_e $(TEST_M68K)_o + $(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o + $(DIFF) $(TEST_MOS65XX)_e $(TEST_MOS65XX)_o + $(DIFF) $(TEST_PPC)_e $(TEST_PPC)_o + $(DIFF) $(TEST_SPARC)_e $(TEST_SPARC)_o + $(DIFF) $(TEST_SYSZ)_e $(TEST_SYSZ)_o + $(DIFF) $(TEST_X86)_e $(TEST_X86)_o + $(DIFF) $(TEST_XCORE)_e $(TEST_XCORE)_o + +clean: + rm -rf $(TMPDIR) + cd java && $(MAKE) clean + cd python && $(MAKE) clean + cd ocaml && $(MAKE) clean + +check: + make -C ocaml check + make -C python check + make -C java check + +FORCE: diff --git a/white_patch_detect/capstone-master/bindings/README b/white_patch_detect/capstone-master/bindings/README new file mode 100644 index 0000000..63be0e0 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/README @@ -0,0 +1,72 @@ +This directory contains bindings & test code for Python, Java & OCaml. +See /README for how to compile & install each binding. + +More bindings created & maintained by the community are available as followings. + +- Gapstone: Go binding (by Scott Knight). + + https://github.com/knightsc/gapstone + +- Crabstone: Ruby binding for Capstone 3+ (by david942j). + + https://github.com/david942j/crabstone + +- Crabstone: Ruby binding (by Ben Nagy). + + https://github.com/bnagy/crabstone + +- Capstone-Vala: Vala binding (by Pancake). + + https://github.com/radare/capstone-vala + +- Node-Capstone: NodeJS binding (by Jason Oster). + + https://github.com/parasyte/node-capstone + +- CCcapstone: C++ binding (by Peter Hlavaty). + + https://github.com/zer0mem/cccapstone + +- LuaCapstone: Lua binding (by Antonio Davide). + + https://github.com/Dax89/LuaCapstone + +- Capstone-RS: Rust binding (by Richo Healey). + + https://github.com/capstone-rust/capstone-rs + +- Capstone.NET: .NET framework binding (by Ahmed Garhy). + + https://github.com/9ee1/Capstone.NET + +- CapstoneJ: High level Java wrapper for Capstone-java (by Keve M眉ller). + + https://github.com/kevemueller/capstonej + +- Hapstone: Haskell binding (by ibabushkin) + + https://github.com/ibabushkin/hapstone + +- CL-Capstone: Common Lisp bindings (by GrammaTech). + + https://github.com/GrammaTech/cl-capstone + +- Emacs-capstone: Emacs (elisp) binding (by Bas Alberts) + + https://github.com/collarchoke/emacs-capstone + +- C# binding (by Matt Graeber). Note: this is only for Capstone v2.0. + + https://github.com/mattifestation/capstone + +- PowerShell binding (by Ruben Boonen). + + https://github.com/aquynh/capstone/tree/master/bindings/powershell + +- PHP binding (by Fadhil Mandaga). + + https://github.com/firodj/php-capstone + +- capstone-d: D binding (by Dimitri Bohlender) + + https://github.com/bohlender/capstone-d diff --git a/white_patch_detect/capstone-master/bindings/const_generator.py b/white_patch_detect/capstone-master/bindings/const_generator.py new file mode 100644 index 0000000..0ec9e98 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/const_generator.py @@ -0,0 +1,172 @@ +# Capstone Disassembler Engine +# By Dang Hoang Vu, 2013 +from __future__ import print_function +import sys, re + +INCL_DIR = '../include/capstone/' + +include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h' ] + +template = { + 'java': { + 'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT\npackage capstone;\n\npublic class %s_const {\n", + 'footer': "}", + 'line_format': '\tpublic static final int %s = %s;\n', + 'out_file': './java/capstone/%s_const.java', + # prefixes for constant filenames of all archs - case sensitive + 'arm.h': 'Arm', + 'arm64.h': 'Arm64', + 'm68k.h': 'M68k', + 'mips.h': 'Mips', + 'x86.h': 'X86', + 'ppc.h': 'Ppc', + 'sparc.h': 'Sparc', + 'systemz.h': 'Sysz', + 'xcore.h': 'Xcore', + 'tms320c64x.h': 'TMS320C64x', + 'm680x.h': 'M680x', + 'evm.h': 'Evm', + 'comment_open': '\t//', + 'comment_close': '', + }, + 'python': { + 'header': "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n", + 'footer': "", + 'line_format': '%s = %s\n', + 'out_file': './python/capstone/%s_const.py', + # prefixes for constant filenames of all archs - case sensitive + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'm68k.h': 'm68k', + 'mips.h': 'mips', + 'x86.h': 'x86', + 'ppc.h': 'ppc', + 'sparc.h': 'sparc', + 'systemz.h': 'sysz', + 'xcore.h': 'xcore', + 'tms320c64x.h': 'tms320c64x', + 'm680x.h': 'm680x', + 'evm.h': 'evm', + 'mos65xx.h': 'mos65xx', + 'comment_open': '#', + 'comment_close': '', + }, + 'ocaml': { + 'header': "(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.ml] *)\n", + 'footer': "", + 'line_format': 'let _%s = %s;;\n', + 'out_file': './ocaml/%s_const.ml', + # prefixes for constant filenames of all archs - case sensitive + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'mips.h': 'mips', + 'm68k.h': 'm68k', + 'x86.h': 'x86', + 'ppc.h': 'ppc', + 'sparc.h': 'sparc', + 'systemz.h': 'sysz', + 'xcore.h': 'xcore', + 'tms320c64x.h': 'tms320c64x', + 'm680x.h': 'm680x', + 'evm.h': 'evm', + 'comment_open': '(*', + 'comment_close': ' *)', + }, +} + +# markup for comments to be added to autogen files +MARKUP = '//>' + +def gen(lang): + global include, INCL_DIR + print('Generating bindings for', lang) + templ = template[lang] + print('Generating bindings for', lang) + for target in include: + if target not in templ: + print("Warning: No binding found for %s" % target) + continue + prefix = templ[target] + outfile = open(templ['out_file'] %(prefix), 'wb') # open as binary prevents windows newlines + outfile.write((templ['header'] % (prefix)).encode("utf-8")) + + lines = open(INCL_DIR + target).readlines() + + count = 0 + for line in lines: + line = line.strip() + + if line.startswith(MARKUP): # markup for comments + outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \ + line.replace(MARKUP, ''), \ + templ['comment_close']) ).encode("utf-8")) + continue + + if line == '' or line.startswith('//'): + continue + + if line.startswith('#define '): + line = line[8:] #cut off define + xline = re.split('\s+', line, 1) #split to at most 2 express + if len(xline) != 2: + continue + if '(' in xline[0] or ')' in xline[0]: #does it look like a function + continue + xline.insert(1, '=') # insert an = so the expression below can parse it + line = ' '.join(xline) + + if not line.startswith(prefix.upper()): + continue + + tmp = line.strip().split(',') + for t in tmp: + t = t.strip() + if not t or t.startswith('//'): continue + # hacky: remove type cast (uint64_t) + t = t.replace('(uint64_t)', '') + t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t) # (1ULL<<1) to 1 << 1 + f = re.split('\s+', t) + + if f[0].startswith(prefix.upper()): + if len(f) > 1 and f[1] not in ('//', '///<', '='): + print("Error: Unable to convert %s" % f) + continue + elif len(f) > 1 and f[1] == '=': + rhs = ''.join(f[2:]) + else: + rhs = str(count) + count += 1 + + try: + count = int(rhs) + 1 + if (count == 1): + outfile.write(("\n").encode("utf-8")) + except ValueError: + if lang == 'ocaml': + # ocaml uses lsl for '<<', lor for '|' + rhs = rhs.replace('<<', ' lsl ') + rhs = rhs.replace('|', ' lor ') + # ocaml variable has _ as prefix + if rhs[0].isalpha(): + rhs = '_' + rhs + + outfile.write((templ['line_format'] %(f[0].strip(), rhs)).encode("utf-8")) + + outfile.write((templ['footer']).encode("utf-8")) + outfile.close() + +def main(): + try: + if sys.argv[1] == 'all': + for key in template.keys(): + gen(key) + else: + gen(sys.argv[1]) + except: + raise RuntimeError("Unsupported binding %s" % sys.argv[1]) + +if __name__ == "__main__": + if len(sys.argv) < 2: + print("Usage:", sys.argv[0], " ") + sys.exit(1) + main() diff --git a/white_patch_detect/capstone-master/bindings/java/.gitignore b/white_patch_detect/capstone-master/bindings/java/.gitignore new file mode 100644 index 0000000..82f7eca --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/.gitignore @@ -0,0 +1,2 @@ +*.class +tags diff --git a/white_patch_detect/capstone-master/bindings/java/Makefile b/white_patch_detect/capstone-master/bindings/java/Makefile new file mode 100644 index 0000000..32f50be --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/Makefile @@ -0,0 +1,71 @@ +# Capstone Disassembler Engine +# By Nguyen Anh Quynh , 2013> + +ifndef BUILDDIR +BLDIR = . +OBJDIR = . +else +BLDIR = $(abspath $(BUILDDIR))/bindings/java +OBJDIR = $(abspath $(BUILDDIR))/obj/bindings/java +endif + +JNA = /usr/share/java/jna/jna.jar + +ifneq ($(wildcard $(JNA)),) +else + ifneq ($(wildcard /usr/share/java/jna.jar),) + JNA = /usr/share/java/jna.jar + else + JNA = + endif +endif + +PYTHON2 ?= python + +CAPSTONE_JAVA = Capstone.java Arm_const.java Arm64_const.java Mips_const.java \ + X86_const.java Xcore_const.java Ppc_const.java Sparc_const.java\ + Sysz_const.java M680x_const.java \ + Arm.java Arm64.java Mips.java X86.java Xcore.java Ppc.java\ + Sparc.java Systemz.java M680x.java + +all: gen_const capstone tests + +capstone: capstone_class + @mkdir -p $(BLDIR) + cd $(OBJDIR) && jar cf $(BLDIR)/capstone.jar capstone/*.class + +capstone_class: jna +ifdef BUILDDIR + @mkdir -p $(OBJDIR) + cd capstone && javac -d $(OBJDIR) -classpath $(JNA) $(CAPSTONE_JAVA) +else + cd capstone && javac -classpath $(JNA) $(CAPSTONE_JAVA) +endif + +tests: capstone_class jna + @mkdir -p $(OBJDIR) + javac -d $(OBJDIR) -classpath "$(JNA):$(BLDIR)/capstone.jar" TestBasic.java\ + TestArm.java TestArm64.java TestMips.java TestX86.java TestXcore.java\ + TestPpc.java TestSparc.java TestSystemz.java TestM680x.java + +gen_const: + cd ../ && $(PYTHON2) const_generator.py java + +jna: + @if [ ! $(JNA) ]; then echo "*** Unable to find JNA ***"; exit 1; fi + +clean: + rm -rf $(OBJDIR)/capstone/*.class + rm -rf $(OBJDIR)/*.class $(OBJDIR)/*.log $(BLDIR)/*.jar +ifdef BUILDDIR + rm -rf $(BLDIR) + rm -rf $(OBJDIR) +endif + +TESTS = testbasic arm arm64 m680x mips ppc sparc systemz x86 xcore +check: + @for t in $(TESTS); do \ + echo Check $$t ... ; \ + ./run.sh $$t > /dev/null && echo OK || echo FAILED; \ + done + diff --git a/white_patch_detect/capstone-master/bindings/java/README b/white_patch_detect/capstone-master/bindings/java/README new file mode 100644 index 0000000..f6cd8da --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/README @@ -0,0 +1,28 @@ +This has been tested with OpenJDK version 6 & 7 on Ubuntu-12.04 and +Arch Linux-3.11, 64-bit. + +- OpenJDK is required to compile and run this test code. + For example, install OpenJDK 6 with: + + $ sudo apt-get install openjdk-6-jre-headless openjdk-6-jdk + +- Java Native Access is required to run the code, you can install it with: + + $ sudo apt-get install libjna-java + +- To compile and run this Java test code: + + $ make + $ ./run.sh + + +This directory contains some test code to show how to use Capstone API. + +- TestBasic.java + This code shows the most simple form of API where we only want to get basic + information out of disassembled instruction, such as address, mnemonic and + operand string. + +- Test.java + These code show how to retrieve architecture-specific information for each + architecture. diff --git a/white_patch_detect/capstone-master/bindings/java/TestArm.java b/white_patch_detect/capstone-master/bindings/java/TestArm.java new file mode 100644 index 0000000..654d5c5 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/TestArm.java @@ -0,0 +1,142 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +import capstone.Capstone; +import capstone.Arm; + +import static capstone.Arm_const.*; + +public class TestArm { + + static byte[] hexString2Byte(String s) { + // from http://stackoverflow.com/questions/140131/convert-a-string-representation-of-a-hex-dump-to-a-byte-array-using-java + int len = s.length(); + byte[] data = new byte[len / 2]; + for (int i = 0; i < len; i += 2) { + data[i / 2] = (byte) ((Character.digit(s.charAt(i), 16) << 4) + + Character.digit(s.charAt(i+1), 16)); + } + return data; + } + + static final String ARM_CODE = "EDFFFFEB04e02de500000000e08322e5f102030e0000a0e30230c1e7000053e3000201f10540d0e8"; + static final String ARM_CODE2 = "d1e800f0f02404071f3cf2c000004ff00001466c"; + static final String THUMB_CODE2 = "4ff00001bde80088d1e800f018bfadbff3ff0b0c86f3008980f3008c4ffa99f6d0ffa201"; + static final String THUMB_CODE = "7047eb4683b0c9681fb130bfaff32084"; + + public static Capstone cs; + + private static String hex(int i) { + return Integer.toString(i, 16); + } + + private static String hex(long i) { + return Long.toString(i, 16); + } + + public static void print_ins_detail(Capstone.CsInsn ins) { + System.out.printf("0x%x:\t%s\t%s\n", ins.address, ins.mnemonic, ins.opStr); + + Arm.OpInfo operands = (Arm.OpInfo) ins.operands; + + if (operands.op.length != 0) { + System.out.printf("\top_count: %d\n", operands.op.length); + for (int c=0; c 0) + System.out.printf("\t\t\toperands[%d].vector_index = %d\n", c, (i.vector_index)); + if (i.shift.type != ARM_SFT_INVALID && i.shift.value > 0) + System.out.printf("\t\t\tShift: %d = %d\n", i.shift.type, i.shift.value); + if (i.subtracted) + System.out.printf("\t\t\toperands[%d].subtracted = True\n", c); + } + } + if (operands.writeback) + System.out.println("\tWrite-back: True"); + + if (operands.updateFlags) + System.out.println("\tUpdate-flags: True"); + + if (operands.cc != ARM_CC_AL && operands.cc != ARM_CC_INVALID) + System.out.printf("\tCode condition: %d\n", operands.cc); + + if (operands.cpsMode > 0) + System.out.printf("\tCPSI-mode: %d\n", operands.cpsMode); + + if (operands.cpsFlag > 0) + System.out.printf("\tCPSI-flag: %d\n", operands.cpsFlag); + + if (operands.vectorData > 0) + System.out.printf("\tVector-data: %d\n", operands.vectorData); + + if (operands.vectorSize > 0) + System.out.printf("\tVector-size: %d\n", operands.vectorSize); + + if (operands.usermode) + System.out.printf("\tUser-mode: True\n"); + } + + public static void main(String argv[]) { + + final TestBasic.platform[] all_tests = { + new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_ARM, hexString2Byte(ARM_CODE), "ARM"), + new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, hexString2Byte(THUMB_CODE), "Thumb"), + new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, hexString2Byte(ARM_CODE2), "Thumb-mixed"), + new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, Capstone.CS_OPT_SYNTAX_NOREGNAME, hexString2Byte(THUMB_CODE2), "Thumb-2 & register named with numbers"), + }; + + for (int i=0; i 0) + System.out.printf("\t\t\tShift: type = %d, value = %d\n", i.shift.type, i.shift.value); + if (i.ext != ARM64_EXT_INVALID) + System.out.printf("\t\t\tExt: %d\n", i.ext); + if (i.vas != ARM64_VAS_INVALID) + System.out.printf("\t\t\tVector Arrangement Specifier: 0x%x\n", i.vas); + if (i.vess != ARM64_VESS_INVALID) + System.out.printf("\t\t\tVector Element Size Specifier: %d\n", i.vess); + if (i.vector_index != -1) + System.out.printf("\t\t\tVector Index: %d\n", i.vector_index); + + } + } + + if (operands.writeback) + System.out.println("\tWrite-back: True"); + + if (operands.updateFlags) + System.out.println("\tUpdate-flags: True"); + + if (operands.cc != ARM64_CC_AL && operands.cc != ARM64_CC_INVALID) + System.out.printf("\tCode-condition: %d\n", operands.cc); + + } + + public static void main(String argv[]) { + + final TestBasic.platform[] all_tests = { + new TestBasic.platform(Capstone.CS_ARCH_ARM64, Capstone.CS_MODE_ARM, hexString2Byte(ARM64_CODE), "ARM-64"), + }; + + for (int i=0; i, 2013> */ + +import capstone.Capstone; + +public class TestBasic { + public static class platform { + public int arch; + public int mode; + public int syntax; + public byte[] code; + public String comment; + + public platform(int a, int m, int syt, byte[] c, String s) { + arch = a; + mode = m; + code = c; + comment = s; + syntax = syt; + } + + public platform(int a, int m, byte[] c, String s) { + arch = a; + mode = m; + code = c; + comment = s; + } + }; + + static public String stringToHex(byte[] code) { + StringBuilder buf = new StringBuilder(200); + for (byte ch: code) { + if (buf.length() > 0) + buf.append(' '); + buf.append(String.format("0x%02x", ch)); + } + return buf.toString(); + } + + public static final byte[] PPC_CODE = new byte[] {(byte)0x80, (byte)0x20, (byte)0x00, (byte)0x00, (byte)0x80, (byte)0x3f, (byte)0x00, (byte)0x00, (byte)0x10, (byte)0x43, (byte)0x23, (byte)0x0e, (byte)0xd0, (byte)0x44, (byte)0x00, (byte)0x80, (byte)0x4c, (byte)0x43, (byte)0x22, (byte)0x02, (byte)0x2d, (byte)0x03, (byte)0x00, (byte)0x80, (byte)0x7c, (byte)0x43, (byte)0x20, (byte)0x14, (byte)0x7c, (byte)0x43, (byte)0x20, (byte)0x93, (byte)0x4f, (byte)0x20, (byte)0x00, (byte)0x21, (byte)0x4c, (byte)0xc8, (byte)0x00, (byte)0x21 }; + public static final byte[] X86_CODE = new byte[] { (byte)0x8d, (byte)0x4c, (byte)0x32, (byte)0x08, (byte)0x01, (byte)0xd8, (byte)0x81, (byte)0xc6, (byte)0x34, (byte)0x12, (byte)0x00, (byte)0x00 }; + public static final byte[] SPARC_CODE = new byte[] { (byte)0x80, (byte)0xa0, (byte)0x40, (byte)0x02, (byte)0x85, (byte)0xc2, (byte)0x60, (byte)0x08, (byte)0x85, (byte)0xe8, (byte)0x20, (byte)0x01, (byte)0x81, (byte)0xe8, (byte)0x00, (byte)0x00, (byte)0x90, (byte)0x10, (byte)0x20, (byte)0x01, (byte)0xd5, (byte)0xf6, (byte)0x10, (byte)0x16, (byte)0x21, (byte)0x00, (byte)0x00, (byte)0x0a, (byte)0x86, (byte)0x00, (byte)0x40, (byte)0x02, (byte)0x01, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x12, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0x10, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0xa0, (byte)0x02, (byte)0x00, (byte)0x09, (byte)0x0d, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0xd4, (byte)0x20, (byte)0x60, (byte)0x00, (byte)0xd4, (byte)0x4e, (byte)0x00, (byte)0x16, (byte)0x2a, (byte)0xc2, (byte)0x80, (byte)0x03 }; + public static final byte[] SYSZ_CODE = new byte[] { (byte)0xed, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x1a, (byte)0x5a, (byte)0x0f, (byte)0x1f, (byte)0xff, (byte)0xc2, (byte)0x09, (byte)0x80, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x07, (byte)0xf7, (byte)0xeb, (byte)0x2a, (byte)0xff, (byte)0xff, (byte)0x7f, (byte)0x57, (byte)0xe3, (byte)0x01, (byte)0xff, (byte)0xff, (byte)0x7f, (byte)0x57, (byte)0xeb, (byte)0x00, (byte)0xf0, (byte)0x00, (byte)0x00, (byte)0x24, (byte)0xb2, (byte)0x4f, (byte)0x00, (byte)0x78 }; + public static final byte[] SPARCV9_CODE = new byte[] { (byte)0x81, (byte)0xa8, (byte)0x0a, (byte)0x24, (byte)0x89, (byte)0xa0, (byte)0x10, (byte)0x20, (byte)0x89, (byte)0xa0, (byte)0x1a, (byte)0x60, (byte)0x89, (byte)0xa0, (byte)0x00, (byte)0xe0 }; + public static final byte[] XCORE_CODE = new byte[] { (byte)0xfe, (byte)0x0f, (byte)0xfe, (byte)0x17, (byte)0x13, (byte)0x17, (byte)0xc6, (byte)0xfe, (byte)0xec, (byte)0x17, (byte)0x97, (byte)0xf8, (byte)0xec, (byte)0x4f, (byte)0x1f, (byte)0xfd, (byte)0xec, (byte)0x37, (byte)0x07, (byte)0xf2, (byte)0x45, (byte)0x5b, (byte)0xf9, (byte)0xfa, (byte)0x02, (byte)0x06, (byte)0x1b, (byte)0x10 }; + + static public void main(String argv[]) { + platform[] platforms = { + new platform( + Capstone.CS_ARCH_X86, + Capstone.CS_MODE_16, + Capstone.CS_OPT_SYNTAX_INTEL, + new byte[] { (byte)0x8d, (byte)0x4c, (byte)0x32, (byte)0x08, (byte)0x01, (byte)0xd8, (byte)0x81, (byte)0xc6, (byte)0x34, (byte)0x12, (byte)0x00, (byte)0x00 }, + "X86 16bit (Intel syntax)" + ), + new platform( + Capstone.CS_ARCH_X86, + Capstone.CS_MODE_32, + Capstone.CS_OPT_SYNTAX_ATT, + X86_CODE, + "X86 32bit (ATT syntax)" + ), + new platform( + Capstone.CS_ARCH_X86, + Capstone.CS_MODE_32, + X86_CODE, + "X86 32 (Intel syntax)" + ), + new platform( + Capstone.CS_ARCH_X86, + Capstone.CS_MODE_64, + new byte[] {(byte)0x55, (byte)0x48, (byte)0x8b, (byte)0x05, (byte)0xb8, (byte)0x13, (byte)0x00, (byte)0x00 }, + "X86 64 (Intel syntax)" + ), + new platform( + Capstone.CS_ARCH_ARM, + Capstone.CS_MODE_ARM, + new byte[] { (byte)0xED, (byte)0xFF, (byte)0xFF, (byte)0xEB, (byte)0x04, (byte)0xe0, (byte)0x2d, (byte)0xe5, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0xe0, (byte)0x83, (byte)0x22, (byte)0xe5, (byte)0xf1, (byte)0x02, (byte)0x03, (byte)0x0e, (byte)0x00, (byte)0x00, (byte)0xa0, (byte)0xe3, (byte)0x02, (byte)0x30, (byte)0xc1, (byte)0xe7, (byte)0x00, (byte)0x00, (byte)0x53, (byte)0xe3 }, + "ARM" + ), + new platform( + Capstone.CS_ARCH_ARM, + Capstone.CS_MODE_THUMB, + new byte[] {(byte)0x4f, (byte)0xf0, (byte)0x00, (byte)0x01, (byte)0xbd, (byte)0xe8, (byte)0x00, (byte)0x88, (byte)0xd1, (byte)0xe8, (byte)0x00, (byte)0xf0 }, + "THUMB-2" + ), + new platform( + Capstone.CS_ARCH_ARM, + Capstone.CS_MODE_ARM, + new byte[] {(byte)0x10, (byte)0xf1, (byte)0x10, (byte)0xe7, (byte)0x11, (byte)0xf2, (byte)0x31, (byte)0xe7, (byte)0xdc, (byte)0xa1, (byte)0x2e, (byte)0xf3, (byte)0xe8, (byte)0x4e, (byte)0x62, (byte)0xf3 }, + "ARM: Cortex-A15 + NEON" + ), + new platform( + Capstone.CS_ARCH_ARM, + Capstone.CS_MODE_THUMB, + new byte[] {(byte)0x70, (byte)0x47, (byte)0xeb, (byte)0x46, (byte)0x83, (byte)0xb0, (byte)0xc9, (byte)0x68 }, + "THUMB" + ), + new platform( + Capstone.CS_ARCH_MIPS, + Capstone.CS_MODE_MIPS32 + Capstone.CS_MODE_BIG_ENDIAN, + new byte[] {(byte)0x0C, (byte)0x10, (byte)0x00, (byte)0x97, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x24, (byte)0x02, (byte)0x00, (byte)0x0c, (byte)0x8f, (byte)0xa2, (byte)0x00, (byte)0x00, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0x56 }, + "MIPS-32 (Big-endian)" + ), + new platform( + Capstone.CS_ARCH_MIPS, + Capstone.CS_MODE_MIPS64+ Capstone.CS_MODE_LITTLE_ENDIAN, + new byte[] {(byte)0x56, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0xc2, (byte)0x17, (byte)0x01, (byte)0x00 }, + "MIPS-64-EL (Little-endian)" + ), + new platform( + Capstone.CS_ARCH_ARM64, + Capstone.CS_MODE_ARM, + new byte [] { 0x21, 0x7c, 0x02, (byte)0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, (byte)0xe1, 0x0b, 0x40, (byte)0xb9 }, + "ARM-64" + ), + new platform ( + Capstone.CS_ARCH_PPC, + Capstone.CS_MODE_BIG_ENDIAN, + PPC_CODE, + "PPC-64" + ), + new platform ( + Capstone.CS_ARCH_PPC, + Capstone.CS_MODE_BIG_ENDIAN, + Capstone.CS_OPT_SYNTAX_NOREGNAME, + PPC_CODE, + "PPC-64, print register with number only" + ), + new platform ( + Capstone.CS_ARCH_SPARC, + Capstone.CS_MODE_BIG_ENDIAN, + SPARC_CODE, + "Sparc" + ), + new platform ( + Capstone.CS_ARCH_SPARC, + Capstone.CS_MODE_BIG_ENDIAN + Capstone.CS_MODE_V9, + SPARCV9_CODE, + "SparcV9" + ), + new platform ( + Capstone.CS_ARCH_SYSZ, + 0, + SYSZ_CODE, + "SystemZ" + ), + new platform ( + Capstone.CS_ARCH_XCORE, + 0, + XCORE_CODE, + "XCore" + ), + }; + + for (int j = 0; j < platforms.length; j++) { + System.out.println("****************"); + System.out.println(String.format("Platform: %s", platforms[j].comment)); + System.out.println(String.format("Code: %s", stringToHex(platforms[j].code))); + System.out.println("Disasm:"); + + Capstone cs = new Capstone(platforms[j].arch, platforms[j].mode); + if (platforms[j].syntax != 0) + cs.setSyntax(platforms[j].syntax); + + Capstone.CsInsn[] all_insn = cs.disasm(platforms[j].code, 0x1000); + + for (int i = 0; i < all_insn.length; i++) { + System.out.println(String.format("0x%x: \t%s\t%s", all_insn[i].address, + all_insn[i].mnemonic, all_insn[i].opStr)); + } + System.out.printf("0x%x:\n\n", all_insn[all_insn.length-1].address + all_insn[all_insn.length-1].size); + + // Close when done + cs.close(); + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/TestM680x.java b/white_patch_detect/capstone-master/bindings/java/TestM680x.java new file mode 100644 index 0000000..b99517b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/TestM680x.java @@ -0,0 +1,207 @@ +// Capstone Java binding +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +import java.lang.*; +import capstone.Capstone; +import capstone.M680x; + +import static capstone.M680x_const.*; + +public class TestM680x { + + static final String sAccess[] = { + "UNCHANGED", "READ", "WRITE", "READ | WRITE", + }; + + static final String M6800_CODE = "010936647f7410009010A410b6100039"; + static final String M6801_CODE = "04053c3d389310ec10ed1039"; + static final String M6805_CODE = "047f00172228002e0040425a708e979ca015ad00c31000da1234e57ffe"; + static final String M6808_CODE = "31220035224510004b005110525e226265123472848586878a8b8c9495a710af109e607f9e6b7f009ed610009ee67f"; + static final String HD6301_CODE = "6b100071100072101039"; + static final String M6809_CODE = "0610191a551e0123e931063455a681a7897fffa69d1000a791a69f100011ac99100039A607A627A647A667A60FA610A680A681A682A683A684A685A686A6887FA68880A6897FFFA6898000A68BA68C10A68D1000A691A693A694A695A696A6987FA69880A6997FFFA6998000A69BA69C10A69D1000A69F1000"; + static final String M6811_CODE = "0203127f100013990800147f02157f011e7f20008fcf18081830183c1867188c1000188f18ce100018ff10001aa37f1aac1aee7f1aef7fcdac7f"; + static final String CPU12_CODE = "000401000c00800e008000111e100080003b4a1000044b01044f7f80008f1000b752b7b1a667a6fea6f71802e23039e21000180c30391000181118121000181900181e00183e183f00"; + static final String HD6309_CODE = "0110106210107b101000cd499602d21030231038103b1053105d1130431011372510113812113923113b34118e100011af1011ab1011f68000"; + static final String HCS08_CODE = "3210009eae9ece7f9ebe10009efe7f3e10009ef37f9610009eff7f82"; + + static byte[] hexString2Byte(String s) { + // from http://stackoverflow.com/questions/140131/convert-a-string-representation-of-a-hex-dump-to-a-byte-array-using-java + int len = s.length(); + byte[] data = new byte[len / 2]; + for (int i = 0; i < len; i += 2) { + data[i / 2] = (byte) ((Character.digit(s.charAt(i), 16) << 4) + + Character.digit(s.charAt(i+1), 16)); + } + return data; + } + + static public String stringToHexUc(byte[] code) { + StringBuilder buf = new StringBuilder(800); + for (byte ch: code) { + buf.append(String.format(" 0x%02X", ch)); + } + return buf.toString(); + } + + static public String stringToHexShortUc(byte[] code) { + StringBuilder buf = new StringBuilder(800); + for (byte ch: code) { + buf.append(String.format("%02X", ch)); + } + return buf.toString(); + } + + public static Capstone cs; +/* + private static String hex(int i) { + return Integer.toString(i, 16); + } + + private static String hex(long i) { + return Long.toString(i, 16); + } +*/ + public static void print_ins_detail(Capstone.CsInsn ins) { + String bytes = stringToHexShortUc(ins.bytes); + System.out.printf("0x%04X:\t%s\t%s\t%s\n", ins.address, bytes, ins.mnemonic, ins.opStr); + + M680x.OpInfo operands = (M680x.OpInfo) ins.operands; + + if (operands.op.length != 0) { + System.out.printf("\top_count: %d\n", operands.op.length); + for (int c = 0; c < operands.op.length; c++) { + M680x.Operand i = (M680x.Operand) operands.op[c]; + if (i.type == M680X_OP_REGISTER) { + String comment = ""; + if ((c == 0 && ((operands.flags & M680X_FIRST_OP_IN_MNEM) != 0)) || + (c == 1 && ((operands.flags & M680X_SECOND_OP_IN_MNEM) != 0))) + comment = " (in mnemonic)"; + System.out.printf("\t\toperands[%d].type: REGISTER = %s%s\n", c, ins.regName(i.value.reg), comment); + } + if (i.type == M680X_OP_CONSTANT) + System.out.printf("\t\toperands[%d].type: CONSTANT = %d\n", c, i.value.const_val); + if (i.type == M680X_OP_IMMEDIATE) + System.out.printf("\t\toperands[%d].type: IMMEDIATE = #%d\n", c, i.value.imm); + if (i.type == M680X_OP_DIRECT) + System.out.printf("\t\toperands[%d].type: DIRECT = 0x%02X\n", c, i.value.direct_addr); + if (i.type == M680X_OP_EXTENDED) + System.out.printf("\t\toperands[%d].type: EXTENDED %s = 0x%04X\n", c, + i.value.ext.indirect != 0 ? "INDIRECT" : "", i.value.ext.address); + if (i.type == M680X_OP_RELATIVE) + System.out.printf("\t\toperands[%d].type: RELATIVE = 0x%04X\n", c, i.value.rel.address ); + if (i.type == M680X_OP_INDEXED) { + System.out.printf("\t\toperands[%d].type: INDEXED%s\n", c, + (i.value.idx.flags & M680X_IDX_INDIRECT) != 0 ? " INDIRECT" : ""); + if (i.value.idx.base_reg != M680X_REG_INVALID) { + String regName = ins.regName(i.value.idx.base_reg); + if (regName != null) + System.out.printf("\t\t\tbase register: %s\n", regName); + } + if (i.value.idx.offset_reg != M680X_REG_INVALID) { + String regName = ins.regName(i.value.idx.offset_reg); + if (regName != null) + System.out.printf("\t\t\toffset register: %s\n", regName); + } + if ((i.value.idx.offset_bits != 0) && + (i.value.idx.offset_reg == M680X_REG_INVALID) && + (i.value.idx.inc_dec == 0)) { + System.out.printf("\t\t\toffset: %d\n", i.value.idx.offset); + if (i.value.idx.base_reg == M680X_REG_PC) + System.out.printf("\t\t\toffset address: 0x%04X\n", i.value.idx.offset_addr); + System.out.printf("\t\t\toffset bits: %d\n", i.value.idx.offset_bits); + } + if (i.value.idx.inc_dec != 0) { + String post_pre = + (i.value.idx.flags & M680X_IDX_POST_INC_DEC) != 0 ? + "post" : "pre"; + String inc_dec = + i.value.idx.inc_dec > 0 ? "increment" : "decrement"; + + System.out.printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, + Math.abs(i.value.idx.inc_dec)); + } + } + if (i.size != 0) + System.out.printf("\t\t\tsize: %d\n", i.size); + if (i.access != Capstone.CS_AC_INVALID) + System.out.printf("\t\t\taccess: %s\n", sAccess[i.access]); + } + } + + if (ins.regsRead.length > 0) { + System.out.printf("\tRegisters read:"); + for (int c = 0; c < ins.regsRead.length; c++) { + System.out.printf(" %s", ins.regName(ins.regsRead[c])); + } + System.out.printf("\n"); + } + + if (ins.regsWrite.length > 0) { + System.out.printf("\tRegisters modified:"); + for (int c = 0; c < ins.regsWrite.length; c++) { + System.out.printf(" %s", ins.regName(ins.regsWrite[c])); + } + System.out.printf("\n"); + } + + if (ins.groups.length > 0) + System.out.printf("\tgroups_count: %d\n", ins.groups.length); + } + + public static void main(String argv[]) { + + final TestBasic.platform[] all_tests = { + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6301, + hexString2Byte(HD6301_CODE), "M680X_HD6301"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6309, + hexString2Byte(HD6309_CODE), "M680X_HD6309"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6800, + hexString2Byte(M6800_CODE), "M680X_M6800"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6801, + hexString2Byte(M6801_CODE), "M680X_M6801"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6805, + hexString2Byte(M6805_CODE), "M680X_M68HC05"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6808, + hexString2Byte(M6808_CODE), "M680X_M68HC08"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6809, + hexString2Byte(M6809_CODE), "M680X_M6809"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_6811, + hexString2Byte(M6811_CODE), "M680X_M68HC11"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_CPU12, + hexString2Byte(CPU12_CODE), "M680X_CPU12"), + new TestBasic.platform(Capstone.CS_ARCH_M680X, + Capstone.CS_MODE_M680X_HCS08, + hexString2Byte(HCS08_CODE), "M680X_HCS08"), + }; + + for (int i=0; i 0) { + System.out.printf("\timm_count: %d\n", count); + System.out.printf("\timm offset: 0x%x\n", operands.encoding.immOffset); + System.out.printf("\timm size: 0x%x\n", operands.encoding.immSize); + for (int i=0; i 0) { + System.out.printf("\tRegisters read:"); + for (int i = 0; i < regsRead.length; i++) { + System.out.printf(" %s", ins.regName(regsRead[i])); + } + System.out.print("\n"); + } + + if (regsWrite.length > 0) { + System.out.printf("\tRegister modified:"); + for (int i = 0; i < regsWrite.length; i++) { + System.out.printf(" %s", ins.regName(regsWrite[i])); + } + System.out.print("\n"); + } + } + } + } + + public static void main(String argv[]) { + + final TestBasic.platform[] all_tests = { + new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_16, hexString2Byte(X86_CODE16), "X86 16bit (Intel syntax)"), + new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, Capstone.CS_OPT_SYNTAX_ATT, hexString2Byte(X86_CODE32), "X86 32 (AT&T syntax)"), + new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, hexString2Byte(X86_CODE32), "X86 32 (Intel syntax)"), + new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_64, hexString2Byte(X86_CODE64), "X86 64 (Intel syntax)"), + }; + + for (int i=0; i 0); + writeback = (op_info.writeback > 0); + memBarrier = op_info.mem_barrier; + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Arm64.java b/white_patch_detect/capstone-master/bindings/java/capstone/Arm64.java new file mode 100644 index 0000000..258e1b5 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Arm64.java @@ -0,0 +1,127 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.Arm64_const.*; + +public class Arm64 { + + public static class MemType extends Structure { + public int base; + public int index; + public int disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("base", "index", "disp"); + } + } + + public static class OpValue extends Union { + public int reg; + public long imm; + public double fp; + public MemType mem; + public int pstate; + public int sys; + public int prefetch; + public int barrier; + + @Override + public List getFieldOrder() { + return Arrays.asList("reg", "imm", "fp", "mem", "pstate", "sys", "prefetch", "barrier"); + } + } + + public static class OpShift extends Structure { + public int type; + public int value; + + @Override + public List getFieldOrder() { + return Arrays.asList("type","value"); + } + } + + public static class Operand extends Structure { + public int vector_index; + public int vas; + public int vess; + public OpShift shift; + public int ext; + public int type; + public OpValue value; + + public void read() { + readField("type"); + if (type == ARM64_OP_MEM) + value.setType(MemType.class); + if (type == ARM64_OP_FP) + value.setType(Double.TYPE); + if (type == ARM64_OP_IMM || type == ARM64_OP_CIMM || type == ARM64_OP_REG || type == ARM64_OP_REG_MRS || type == ARM64_OP_REG_MSR || type == ARM64_OP_PSTATE || type == ARM64_OP_SYS || type == ARM64_OP_PREFETCH || type == ARM64_OP_BARRIER) + value.setType(Integer.TYPE); + if (type == ARM64_OP_INVALID) + return; + readField("value"); + readField("ext"); + readField("shift"); + readField("vess"); + readField("vas"); + readField("vector_index"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("vector_index", "vas", "vess", "shift", "ext", "type", "value"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public int cc; + public byte _update_flags; + public byte _writeback; + public byte op_count; + + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[8]; + } + + public void read() { + readField("cc"); + readField("_update_flags"); + readField("_writeback"); + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("cc", "_update_flags", "_writeback", "op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public int cc; + public boolean updateFlags; + public boolean writeback; + public Operand [] op = null; + + public OpInfo(UnionOpInfo op_info) { + cc = op_info.cc; + updateFlags = (op_info._update_flags > 0); + writeback = (op_info._writeback > 0); + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Arm64_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Arm64_const.java new file mode 100644 index 0000000..54c6884 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Arm64_const.java @@ -0,0 +1,1010 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Arm64_const { + + public static final int ARM64_SFT_INVALID = 0; + public static final int ARM64_SFT_LSL = 1; + public static final int ARM64_SFT_MSL = 2; + public static final int ARM64_SFT_LSR = 3; + public static final int ARM64_SFT_ASR = 4; + public static final int ARM64_SFT_ROR = 5; + + public static final int ARM64_EXT_INVALID = 0; + public static final int ARM64_EXT_UXTB = 1; + public static final int ARM64_EXT_UXTH = 2; + public static final int ARM64_EXT_UXTW = 3; + public static final int ARM64_EXT_UXTX = 4; + public static final int ARM64_EXT_SXTB = 5; + public static final int ARM64_EXT_SXTH = 6; + public static final int ARM64_EXT_SXTW = 7; + public static final int ARM64_EXT_SXTX = 8; + + public static final int ARM64_CC_INVALID = 0; + public static final int ARM64_CC_EQ = 1; + public static final int ARM64_CC_NE = 2; + public static final int ARM64_CC_HS = 3; + public static final int ARM64_CC_LO = 4; + public static final int ARM64_CC_MI = 5; + public static final int ARM64_CC_PL = 6; + public static final int ARM64_CC_VS = 7; + public static final int ARM64_CC_VC = 8; + public static final int ARM64_CC_HI = 9; + public static final int ARM64_CC_LS = 10; + public static final int ARM64_CC_GE = 11; + public static final int ARM64_CC_LT = 12; + public static final int ARM64_CC_GT = 13; + public static final int ARM64_CC_LE = 14; + public static final int ARM64_CC_AL = 15; + public static final int ARM64_CC_NV = 16; + + public static final int ARM64_SYSREG_INVALID = 0; + public static final int ARM64_SYSREG_MDCCSR_EL0 = 0x9808; + public static final int ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828; + public static final int ARM64_SYSREG_MDRAR_EL1 = 0x8080; + public static final int ARM64_SYSREG_OSLSR_EL1 = 0x808c; + public static final int ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6; + public static final int ARM64_SYSREG_PMCEID0_EL0 = 0xdce6; + public static final int ARM64_SYSREG_PMCEID1_EL0 = 0xdce7; + public static final int ARM64_SYSREG_MIDR_EL1 = 0xc000; + public static final int ARM64_SYSREG_CCSIDR_EL1 = 0xc800; + public static final int ARM64_SYSREG_CLIDR_EL1 = 0xc801; + public static final int ARM64_SYSREG_CTR_EL0 = 0xd801; + public static final int ARM64_SYSREG_MPIDR_EL1 = 0xc005; + public static final int ARM64_SYSREG_REVIDR_EL1 = 0xc006; + public static final int ARM64_SYSREG_AIDR_EL1 = 0xc807; + public static final int ARM64_SYSREG_DCZID_EL0 = 0xd807; + public static final int ARM64_SYSREG_ID_PFR0_EL1 = 0xc008; + public static final int ARM64_SYSREG_ID_PFR1_EL1 = 0xc009; + public static final int ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a; + public static final int ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b; + public static final int ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c; + public static final int ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d; + public static final int ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e; + public static final int ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f; + public static final int ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010; + public static final int ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011; + public static final int ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012; + public static final int ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013; + public static final int ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014; + public static final int ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015; + public static final int ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020; + public static final int ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021; + public static final int ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028; + public static final int ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029; + public static final int ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c; + public static final int ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d; + public static final int ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030; + public static final int ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031; + public static final int ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038; + public static final int ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039; + public static final int ARM64_SYSREG_MVFR0_EL1 = 0xc018; + public static final int ARM64_SYSREG_MVFR1_EL1 = 0xc019; + public static final int ARM64_SYSREG_MVFR2_EL1 = 0xc01a; + public static final int ARM64_SYSREG_RVBAR_EL1 = 0xc601; + public static final int ARM64_SYSREG_RVBAR_EL2 = 0xe601; + public static final int ARM64_SYSREG_RVBAR_EL3 = 0xf601; + public static final int ARM64_SYSREG_ISR_EL1 = 0xc608; + public static final int ARM64_SYSREG_CNTPCT_EL0 = 0xdf01; + public static final int ARM64_SYSREG_CNTVCT_EL0 = 0xdf02; + public static final int ARM64_SYSREG_TRCSTATR = 0x8818; + public static final int ARM64_SYSREG_TRCIDR8 = 0x8806; + public static final int ARM64_SYSREG_TRCIDR9 = 0x880e; + public static final int ARM64_SYSREG_TRCIDR10 = 0x8816; + public static final int ARM64_SYSREG_TRCIDR11 = 0x881e; + public static final int ARM64_SYSREG_TRCIDR12 = 0x8826; + public static final int ARM64_SYSREG_TRCIDR13 = 0x882e; + public static final int ARM64_SYSREG_TRCIDR0 = 0x8847; + public static final int ARM64_SYSREG_TRCIDR1 = 0x884f; + public static final int ARM64_SYSREG_TRCIDR2 = 0x8857; + public static final int ARM64_SYSREG_TRCIDR3 = 0x885f; + public static final int ARM64_SYSREG_TRCIDR4 = 0x8867; + public static final int ARM64_SYSREG_TRCIDR5 = 0x886f; + public static final int ARM64_SYSREG_TRCIDR6 = 0x8877; + public static final int ARM64_SYSREG_TRCIDR7 = 0x887f; + public static final int ARM64_SYSREG_TRCOSLSR = 0x888c; + public static final int ARM64_SYSREG_TRCPDSR = 0x88ac; + public static final int ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6; + public static final int ARM64_SYSREG_TRCDEVAFF1 = 0x8bde; + public static final int ARM64_SYSREG_TRCLSR = 0x8bee; + public static final int ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6; + public static final int ARM64_SYSREG_TRCDEVARCH = 0x8bfe; + public static final int ARM64_SYSREG_TRCDEVID = 0x8b97; + public static final int ARM64_SYSREG_TRCDEVTYPE = 0x8b9f; + public static final int ARM64_SYSREG_TRCPIDR4 = 0x8ba7; + public static final int ARM64_SYSREG_TRCPIDR5 = 0x8baf; + public static final int ARM64_SYSREG_TRCPIDR6 = 0x8bb7; + public static final int ARM64_SYSREG_TRCPIDR7 = 0x8bbf; + public static final int ARM64_SYSREG_TRCPIDR0 = 0x8bc7; + public static final int ARM64_SYSREG_TRCPIDR1 = 0x8bcf; + public static final int ARM64_SYSREG_TRCPIDR2 = 0x8bd7; + public static final int ARM64_SYSREG_TRCPIDR3 = 0x8bdf; + public static final int ARM64_SYSREG_TRCCIDR0 = 0x8be7; + public static final int ARM64_SYSREG_TRCCIDR1 = 0x8bef; + public static final int ARM64_SYSREG_TRCCIDR2 = 0x8bf7; + public static final int ARM64_SYSREG_TRCCIDR3 = 0x8bff; + public static final int ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660; + public static final int ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640; + public static final int ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662; + public static final int ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642; + public static final int ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b; + public static final int ARM64_SYSREG_ICH_VTR_EL2 = 0xe659; + public static final int ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b; + public static final int ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d; + public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828; + public static final int ARM64_SYSREG_OSLAR_EL1 = 0x8084; + public static final int ARM64_SYSREG_PMSWINC_EL0 = 0xdce4; + public static final int ARM64_SYSREG_TRCOSLAR = 0x8884; + public static final int ARM64_SYSREG_TRCLAR = 0x8be6; + public static final int ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661; + public static final int ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641; + public static final int ARM64_SYSREG_ICC_DIR_EL1 = 0xc659; + public static final int ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d; + public static final int ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e; + public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f; + + public static final int ARM64_PSTATE_INVALID = 0; + public static final int ARM64_PSTATE_SPSEL = 0x05; + public static final int ARM64_PSTATE_DAIFSET = 0x1e; + public static final int ARM64_PSTATE_DAIFCLR = 0x1f; + + public static final int ARM64_VAS_INVALID = 0; + public static final int ARM64_VAS_8B = 1; + public static final int ARM64_VAS_16B = 2; + public static final int ARM64_VAS_4H = 3; + public static final int ARM64_VAS_8H = 4; + public static final int ARM64_VAS_2S = 5; + public static final int ARM64_VAS_4S = 6; + public static final int ARM64_VAS_1D = 7; + public static final int ARM64_VAS_2D = 8; + public static final int ARM64_VAS_1Q = 9; + + public static final int ARM64_VESS_INVALID = 0; + public static final int ARM64_VESS_B = 1; + public static final int ARM64_VESS_H = 2; + public static final int ARM64_VESS_S = 3; + public static final int ARM64_VESS_D = 4; + + public static final int ARM64_BARRIER_INVALID = 0; + public static final int ARM64_BARRIER_OSHLD = 0x1; + public static final int ARM64_BARRIER_OSHST = 0x2; + public static final int ARM64_BARRIER_OSH = 0x3; + public static final int ARM64_BARRIER_NSHLD = 0x5; + public static final int ARM64_BARRIER_NSHST = 0x6; + public static final int ARM64_BARRIER_NSH = 0x7; + public static final int ARM64_BARRIER_ISHLD = 0x9; + public static final int ARM64_BARRIER_ISHST = 0xa; + public static final int ARM64_BARRIER_ISH = 0xb; + public static final int ARM64_BARRIER_LD = 0xd; + public static final int ARM64_BARRIER_ST = 0xe; + public static final int ARM64_BARRIER_SY = 0xf; + + public static final int ARM64_OP_INVALID = 0; + public static final int ARM64_OP_REG = 1; + public static final int ARM64_OP_IMM = 2; + public static final int ARM64_OP_MEM = 3; + public static final int ARM64_OP_FP = 4; + public static final int ARM64_OP_CIMM = 64; + public static final int ARM64_OP_REG_MRS = 65; + public static final int ARM64_OP_REG_MSR = 66; + public static final int ARM64_OP_PSTATE = 67; + public static final int ARM64_OP_SYS = 68; + public static final int ARM64_OP_PREFETCH = 69; + public static final int ARM64_OP_BARRIER = 70; + + public static final int ARM64_TLBI_INVALID = 0; + public static final int ARM64_TLBI_VMALLE1IS = 1; + public static final int ARM64_TLBI_VAE1IS = 2; + public static final int ARM64_TLBI_ASIDE1IS = 3; + public static final int ARM64_TLBI_VAAE1IS = 4; + public static final int ARM64_TLBI_VALE1IS = 5; + public static final int ARM64_TLBI_VAALE1IS = 6; + public static final int ARM64_TLBI_ALLE2IS = 7; + public static final int ARM64_TLBI_VAE2IS = 8; + public static final int ARM64_TLBI_ALLE1IS = 9; + public static final int ARM64_TLBI_VALE2IS = 10; + public static final int ARM64_TLBI_VMALLS12E1IS = 11; + public static final int ARM64_TLBI_ALLE3IS = 12; + public static final int ARM64_TLBI_VAE3IS = 13; + public static final int ARM64_TLBI_VALE3IS = 14; + public static final int ARM64_TLBI_IPAS2E1IS = 15; + public static final int ARM64_TLBI_IPAS2LE1IS = 16; + public static final int ARM64_TLBI_IPAS2E1 = 17; + public static final int ARM64_TLBI_IPAS2LE1 = 18; + public static final int ARM64_TLBI_VMALLE1 = 19; + public static final int ARM64_TLBI_VAE1 = 20; + public static final int ARM64_TLBI_ASIDE1 = 21; + public static final int ARM64_TLBI_VAAE1 = 22; + public static final int ARM64_TLBI_VALE1 = 23; + public static final int ARM64_TLBI_VAALE1 = 24; + public static final int ARM64_TLBI_ALLE2 = 25; + public static final int ARM64_TLBI_VAE2 = 26; + public static final int ARM64_TLBI_ALLE1 = 27; + public static final int ARM64_TLBI_VALE2 = 28; + public static final int ARM64_TLBI_VMALLS12E1 = 29; + public static final int ARM64_TLBI_ALLE3 = 30; + public static final int ARM64_TLBI_VAE3 = 31; + public static final int ARM64_TLBI_VALE3 = 32; + public static final int ARM64_AT_S1E1R = 33; + public static final int ARM64_AT_S1E1W = 34; + public static final int ARM64_AT_S1E0R = 35; + public static final int ARM64_AT_S1E0W = 36; + public static final int ARM64_AT_S1E2R = 37; + public static final int ARM64_AT_S1E2W = 38; + public static final int ARM64_AT_S12E1R = 39; + public static final int ARM64_AT_S12E1W = 40; + public static final int ARM64_AT_S12E0R = 41; + public static final int ARM64_AT_S12E0W = 42; + public static final int ARM64_AT_S1E3R = 43; + public static final int ARM64_AT_S1E3W = 44; + + public static final int ARM64_DC_INVALID = 0; + public static final int ARM64_DC_ZVA = 1; + public static final int ARM64_DC_IVAC = 2; + public static final int ARM64_DC_ISW = 3; + public static final int ARM64_DC_CVAC = 4; + public static final int ARM64_DC_CSW = 5; + public static final int ARM64_DC_CVAU = 6; + public static final int ARM64_DC_CIVAC = 7; + public static final int ARM64_DC_CISW = 8; + + public static final int ARM64_IC_INVALID = 0; + public static final int ARM64_IC_IALLUIS = 1; + public static final int ARM64_IC_IALLU = 2; + public static final int ARM64_IC_IVAU = 3; + + public static final int ARM64_PRFM_INVALID = 0; + public static final int ARM64_PRFM_PLDL1KEEP = 0x00+1; + public static final int ARM64_PRFM_PLDL1STRM = 0x01+1; + public static final int ARM64_PRFM_PLDL2KEEP = 0x02+1; + public static final int ARM64_PRFM_PLDL2STRM = 0x03+1; + public static final int ARM64_PRFM_PLDL3KEEP = 0x04+1; + public static final int ARM64_PRFM_PLDL3STRM = 0x05+1; + public static final int ARM64_PRFM_PLIL1KEEP = 0x08+1; + public static final int ARM64_PRFM_PLIL1STRM = 0x09+1; + public static final int ARM64_PRFM_PLIL2KEEP = 0x0a+1; + public static final int ARM64_PRFM_PLIL2STRM = 0x0b+1; + public static final int ARM64_PRFM_PLIL3KEEP = 0x0c+1; + public static final int ARM64_PRFM_PLIL3STRM = 0x0d+1; + public static final int ARM64_PRFM_PSTL1KEEP = 0x10+1; + public static final int ARM64_PRFM_PSTL1STRM = 0x11+1; + public static final int ARM64_PRFM_PSTL2KEEP = 0x12+1; + public static final int ARM64_PRFM_PSTL2STRM = 0x13+1; + public static final int ARM64_PRFM_PSTL3KEEP = 0x14+1; + public static final int ARM64_PRFM_PSTL3STRM = 0x15+1; + + public static final int ARM64_REG_INVALID = 0; + public static final int ARM64_REG_X29 = 1; + public static final int ARM64_REG_X30 = 2; + public static final int ARM64_REG_NZCV = 3; + public static final int ARM64_REG_SP = 4; + public static final int ARM64_REG_WSP = 5; + public static final int ARM64_REG_WZR = 6; + public static final int ARM64_REG_XZR = 7; + public static final int ARM64_REG_B0 = 8; + public static final int ARM64_REG_B1 = 9; + public static final int ARM64_REG_B2 = 10; + public static final int ARM64_REG_B3 = 11; + public static final int ARM64_REG_B4 = 12; + public static final int ARM64_REG_B5 = 13; + public static final int ARM64_REG_B6 = 14; + public static final int ARM64_REG_B7 = 15; + public static final int ARM64_REG_B8 = 16; + public static final int ARM64_REG_B9 = 17; + public static final int ARM64_REG_B10 = 18; + public static final int ARM64_REG_B11 = 19; + public static final int ARM64_REG_B12 = 20; + public static final int ARM64_REG_B13 = 21; + public static final int ARM64_REG_B14 = 22; + public static final int ARM64_REG_B15 = 23; + public static final int ARM64_REG_B16 = 24; + public static final int ARM64_REG_B17 = 25; + public static final int ARM64_REG_B18 = 26; + public static final int ARM64_REG_B19 = 27; + public static final int ARM64_REG_B20 = 28; + public static final int ARM64_REG_B21 = 29; + public static final int ARM64_REG_B22 = 30; + public static final int ARM64_REG_B23 = 31; + public static final int ARM64_REG_B24 = 32; + public static final int ARM64_REG_B25 = 33; + public static final int ARM64_REG_B26 = 34; + public static final int ARM64_REG_B27 = 35; + public static final int ARM64_REG_B28 = 36; + public static final int ARM64_REG_B29 = 37; + public static final int ARM64_REG_B30 = 38; + public static final int ARM64_REG_B31 = 39; + public static final int ARM64_REG_D0 = 40; + public static final int ARM64_REG_D1 = 41; + public static final int ARM64_REG_D2 = 42; + public static final int ARM64_REG_D3 = 43; + public static final int ARM64_REG_D4 = 44; + public static final int ARM64_REG_D5 = 45; + public static final int ARM64_REG_D6 = 46; + public static final int ARM64_REG_D7 = 47; + public static final int ARM64_REG_D8 = 48; + public static final int ARM64_REG_D9 = 49; + public static final int ARM64_REG_D10 = 50; + public static final int ARM64_REG_D11 = 51; + public static final int ARM64_REG_D12 = 52; + public static final int ARM64_REG_D13 = 53; + public static final int ARM64_REG_D14 = 54; + public static final int ARM64_REG_D15 = 55; + public static final int ARM64_REG_D16 = 56; + public static final int ARM64_REG_D17 = 57; + public static final int ARM64_REG_D18 = 58; + public static final int ARM64_REG_D19 = 59; + public static final int ARM64_REG_D20 = 60; + public static final int ARM64_REG_D21 = 61; + public static final int ARM64_REG_D22 = 62; + public static final int ARM64_REG_D23 = 63; + public static final int ARM64_REG_D24 = 64; + public static final int ARM64_REG_D25 = 65; + public static final int ARM64_REG_D26 = 66; + public static final int ARM64_REG_D27 = 67; + public static final int ARM64_REG_D28 = 68; + public static final int ARM64_REG_D29 = 69; + public static final int ARM64_REG_D30 = 70; + public static final int ARM64_REG_D31 = 71; + public static final int ARM64_REG_H0 = 72; + public static final int ARM64_REG_H1 = 73; + public static final int ARM64_REG_H2 = 74; + public static final int ARM64_REG_H3 = 75; + public static final int ARM64_REG_H4 = 76; + public static final int ARM64_REG_H5 = 77; + public static final int ARM64_REG_H6 = 78; + public static final int ARM64_REG_H7 = 79; + public static final int ARM64_REG_H8 = 80; + public static final int ARM64_REG_H9 = 81; + public static final int ARM64_REG_H10 = 82; + public static final int ARM64_REG_H11 = 83; + public static final int ARM64_REG_H12 = 84; + public static final int ARM64_REG_H13 = 85; + public static final int ARM64_REG_H14 = 86; + public static final int ARM64_REG_H15 = 87; + public static final int ARM64_REG_H16 = 88; + public static final int ARM64_REG_H17 = 89; + public static final int ARM64_REG_H18 = 90; + public static final int ARM64_REG_H19 = 91; + public static final int ARM64_REG_H20 = 92; + public static final int ARM64_REG_H21 = 93; + public static final int ARM64_REG_H22 = 94; + public static final int ARM64_REG_H23 = 95; + public static final int ARM64_REG_H24 = 96; + public static final int ARM64_REG_H25 = 97; + public static final int ARM64_REG_H26 = 98; + public static final int ARM64_REG_H27 = 99; + public static final int ARM64_REG_H28 = 100; + public static final int ARM64_REG_H29 = 101; + public static final int ARM64_REG_H30 = 102; + public static final int ARM64_REG_H31 = 103; + public static final int ARM64_REG_Q0 = 104; + public static final int ARM64_REG_Q1 = 105; + public static final int ARM64_REG_Q2 = 106; + public static final int ARM64_REG_Q3 = 107; + public static final int ARM64_REG_Q4 = 108; + public static final int ARM64_REG_Q5 = 109; + public static final int ARM64_REG_Q6 = 110; + public static final int ARM64_REG_Q7 = 111; + public static final int ARM64_REG_Q8 = 112; + public static final int ARM64_REG_Q9 = 113; + public static final int ARM64_REG_Q10 = 114; + public static final int ARM64_REG_Q11 = 115; + public static final int ARM64_REG_Q12 = 116; + public static final int ARM64_REG_Q13 = 117; + public static final int ARM64_REG_Q14 = 118; + public static final int ARM64_REG_Q15 = 119; + public static final int ARM64_REG_Q16 = 120; + public static final int ARM64_REG_Q17 = 121; + public static final int ARM64_REG_Q18 = 122; + public static final int ARM64_REG_Q19 = 123; + public static final int ARM64_REG_Q20 = 124; + public static final int ARM64_REG_Q21 = 125; + public static final int ARM64_REG_Q22 = 126; + public static final int ARM64_REG_Q23 = 127; + public static final int ARM64_REG_Q24 = 128; + public static final int ARM64_REG_Q25 = 129; + public static final int ARM64_REG_Q26 = 130; + public static final int ARM64_REG_Q27 = 131; + public static final int ARM64_REG_Q28 = 132; + public static final int ARM64_REG_Q29 = 133; + public static final int ARM64_REG_Q30 = 134; + public static final int ARM64_REG_Q31 = 135; + public static final int ARM64_REG_S0 = 136; + public static final int ARM64_REG_S1 = 137; + public static final int ARM64_REG_S2 = 138; + public static final int ARM64_REG_S3 = 139; + public static final int ARM64_REG_S4 = 140; + public static final int ARM64_REG_S5 = 141; + public static final int ARM64_REG_S6 = 142; + public static final int ARM64_REG_S7 = 143; + public static final int ARM64_REG_S8 = 144; + public static final int ARM64_REG_S9 = 145; + public static final int ARM64_REG_S10 = 146; + public static final int ARM64_REG_S11 = 147; + public static final int ARM64_REG_S12 = 148; + public static final int ARM64_REG_S13 = 149; + public static final int ARM64_REG_S14 = 150; + public static final int ARM64_REG_S15 = 151; + public static final int ARM64_REG_S16 = 152; + public static final int ARM64_REG_S17 = 153; + public static final int ARM64_REG_S18 = 154; + public static final int ARM64_REG_S19 = 155; + public static final int ARM64_REG_S20 = 156; + public static final int ARM64_REG_S21 = 157; + public static final int ARM64_REG_S22 = 158; + public static final int ARM64_REG_S23 = 159; + public static final int ARM64_REG_S24 = 160; + public static final int ARM64_REG_S25 = 161; + public static final int ARM64_REG_S26 = 162; + public static final int ARM64_REG_S27 = 163; + public static final int ARM64_REG_S28 = 164; + public static final int ARM64_REG_S29 = 165; + public static final int ARM64_REG_S30 = 166; + public static final int ARM64_REG_S31 = 167; + public static final int ARM64_REG_W0 = 168; + public static final int ARM64_REG_W1 = 169; + public static final int ARM64_REG_W2 = 170; + public static final int ARM64_REG_W3 = 171; + public static final int ARM64_REG_W4 = 172; + public static final int ARM64_REG_W5 = 173; + public static final int ARM64_REG_W6 = 174; + public static final int ARM64_REG_W7 = 175; + public static final int ARM64_REG_W8 = 176; + public static final int ARM64_REG_W9 = 177; + public static final int ARM64_REG_W10 = 178; + public static final int ARM64_REG_W11 = 179; + public static final int ARM64_REG_W12 = 180; + public static final int ARM64_REG_W13 = 181; + public static final int ARM64_REG_W14 = 182; + public static final int ARM64_REG_W15 = 183; + public static final int ARM64_REG_W16 = 184; + public static final int ARM64_REG_W17 = 185; + public static final int ARM64_REG_W18 = 186; + public static final int ARM64_REG_W19 = 187; + public static final int ARM64_REG_W20 = 188; + public static final int ARM64_REG_W21 = 189; + public static final int ARM64_REG_W22 = 190; + public static final int ARM64_REG_W23 = 191; + public static final int ARM64_REG_W24 = 192; + public static final int ARM64_REG_W25 = 193; + public static final int ARM64_REG_W26 = 194; + public static final int ARM64_REG_W27 = 195; + public static final int ARM64_REG_W28 = 196; + public static final int ARM64_REG_W29 = 197; + public static final int ARM64_REG_W30 = 198; + public static final int ARM64_REG_X0 = 199; + public static final int ARM64_REG_X1 = 200; + public static final int ARM64_REG_X2 = 201; + public static final int ARM64_REG_X3 = 202; + public static final int ARM64_REG_X4 = 203; + public static final int ARM64_REG_X5 = 204; + public static final int ARM64_REG_X6 = 205; + public static final int ARM64_REG_X7 = 206; + public static final int ARM64_REG_X8 = 207; + public static final int ARM64_REG_X9 = 208; + public static final int ARM64_REG_X10 = 209; + public static final int ARM64_REG_X11 = 210; + public static final int ARM64_REG_X12 = 211; + public static final int ARM64_REG_X13 = 212; + public static final int ARM64_REG_X14 = 213; + public static final int ARM64_REG_X15 = 214; + public static final int ARM64_REG_X16 = 215; + public static final int ARM64_REG_X17 = 216; + public static final int ARM64_REG_X18 = 217; + public static final int ARM64_REG_X19 = 218; + public static final int ARM64_REG_X20 = 219; + public static final int ARM64_REG_X21 = 220; + public static final int ARM64_REG_X22 = 221; + public static final int ARM64_REG_X23 = 222; + public static final int ARM64_REG_X24 = 223; + public static final int ARM64_REG_X25 = 224; + public static final int ARM64_REG_X26 = 225; + public static final int ARM64_REG_X27 = 226; + public static final int ARM64_REG_X28 = 227; + public static final int ARM64_REG_V0 = 228; + public static final int ARM64_REG_V1 = 229; + public static final int ARM64_REG_V2 = 230; + public static final int ARM64_REG_V3 = 231; + public static final int ARM64_REG_V4 = 232; + public static final int ARM64_REG_V5 = 233; + public static final int ARM64_REG_V6 = 234; + public static final int ARM64_REG_V7 = 235; + public static final int ARM64_REG_V8 = 236; + public static final int ARM64_REG_V9 = 237; + public static final int ARM64_REG_V10 = 238; + public static final int ARM64_REG_V11 = 239; + public static final int ARM64_REG_V12 = 240; + public static final int ARM64_REG_V13 = 241; + public static final int ARM64_REG_V14 = 242; + public static final int ARM64_REG_V15 = 243; + public static final int ARM64_REG_V16 = 244; + public static final int ARM64_REG_V17 = 245; + public static final int ARM64_REG_V18 = 246; + public static final int ARM64_REG_V19 = 247; + public static final int ARM64_REG_V20 = 248; + public static final int ARM64_REG_V21 = 249; + public static final int ARM64_REG_V22 = 250; + public static final int ARM64_REG_V23 = 251; + public static final int ARM64_REG_V24 = 252; + public static final int ARM64_REG_V25 = 253; + public static final int ARM64_REG_V26 = 254; + public static final int ARM64_REG_V27 = 255; + public static final int ARM64_REG_V28 = 256; + public static final int ARM64_REG_V29 = 257; + public static final int ARM64_REG_V30 = 258; + public static final int ARM64_REG_V31 = 259; + public static final int ARM64_REG_ENDING = 260; + public static final int ARM64_REG_IP0 = ARM64_REG_X16; + public static final int ARM64_REG_IP1 = ARM64_REG_X17; + public static final int ARM64_REG_FP = ARM64_REG_X29; + public static final int ARM64_REG_LR = ARM64_REG_X30; + + public static final int ARM64_INS_INVALID = 0; + public static final int ARM64_INS_ABS = 1; + public static final int ARM64_INS_ADC = 2; + public static final int ARM64_INS_ADDHN = 3; + public static final int ARM64_INS_ADDHN2 = 4; + public static final int ARM64_INS_ADDP = 5; + public static final int ARM64_INS_ADD = 6; + public static final int ARM64_INS_ADDV = 7; + public static final int ARM64_INS_ADR = 8; + public static final int ARM64_INS_ADRP = 9; + public static final int ARM64_INS_AESD = 10; + public static final int ARM64_INS_AESE = 11; + public static final int ARM64_INS_AESIMC = 12; + public static final int ARM64_INS_AESMC = 13; + public static final int ARM64_INS_AND = 14; + public static final int ARM64_INS_ASR = 15; + public static final int ARM64_INS_B = 16; + public static final int ARM64_INS_BFM = 17; + public static final int ARM64_INS_BIC = 18; + public static final int ARM64_INS_BIF = 19; + public static final int ARM64_INS_BIT = 20; + public static final int ARM64_INS_BL = 21; + public static final int ARM64_INS_BLR = 22; + public static final int ARM64_INS_BR = 23; + public static final int ARM64_INS_BRK = 24; + public static final int ARM64_INS_BSL = 25; + public static final int ARM64_INS_CBNZ = 26; + public static final int ARM64_INS_CBZ = 27; + public static final int ARM64_INS_CCMN = 28; + public static final int ARM64_INS_CCMP = 29; + public static final int ARM64_INS_CLREX = 30; + public static final int ARM64_INS_CLS = 31; + public static final int ARM64_INS_CLZ = 32; + public static final int ARM64_INS_CMEQ = 33; + public static final int ARM64_INS_CMGE = 34; + public static final int ARM64_INS_CMGT = 35; + public static final int ARM64_INS_CMHI = 36; + public static final int ARM64_INS_CMHS = 37; + public static final int ARM64_INS_CMLE = 38; + public static final int ARM64_INS_CMLT = 39; + public static final int ARM64_INS_CMTST = 40; + public static final int ARM64_INS_CNT = 41; + public static final int ARM64_INS_MOV = 42; + public static final int ARM64_INS_CRC32B = 43; + public static final int ARM64_INS_CRC32CB = 44; + public static final int ARM64_INS_CRC32CH = 45; + public static final int ARM64_INS_CRC32CW = 46; + public static final int ARM64_INS_CRC32CX = 47; + public static final int ARM64_INS_CRC32H = 48; + public static final int ARM64_INS_CRC32W = 49; + public static final int ARM64_INS_CRC32X = 50; + public static final int ARM64_INS_CSEL = 51; + public static final int ARM64_INS_CSINC = 52; + public static final int ARM64_INS_CSINV = 53; + public static final int ARM64_INS_CSNEG = 54; + public static final int ARM64_INS_DCPS1 = 55; + public static final int ARM64_INS_DCPS2 = 56; + public static final int ARM64_INS_DCPS3 = 57; + public static final int ARM64_INS_DMB = 58; + public static final int ARM64_INS_DRPS = 59; + public static final int ARM64_INS_DSB = 60; + public static final int ARM64_INS_DUP = 61; + public static final int ARM64_INS_EON = 62; + public static final int ARM64_INS_EOR = 63; + public static final int ARM64_INS_ERET = 64; + public static final int ARM64_INS_EXTR = 65; + public static final int ARM64_INS_EXT = 66; + public static final int ARM64_INS_FABD = 67; + public static final int ARM64_INS_FABS = 68; + public static final int ARM64_INS_FACGE = 69; + public static final int ARM64_INS_FACGT = 70; + public static final int ARM64_INS_FADD = 71; + public static final int ARM64_INS_FADDP = 72; + public static final int ARM64_INS_FCCMP = 73; + public static final int ARM64_INS_FCCMPE = 74; + public static final int ARM64_INS_FCMEQ = 75; + public static final int ARM64_INS_FCMGE = 76; + public static final int ARM64_INS_FCMGT = 77; + public static final int ARM64_INS_FCMLE = 78; + public static final int ARM64_INS_FCMLT = 79; + public static final int ARM64_INS_FCMP = 80; + public static final int ARM64_INS_FCMPE = 81; + public static final int ARM64_INS_FCSEL = 82; + public static final int ARM64_INS_FCVTAS = 83; + public static final int ARM64_INS_FCVTAU = 84; + public static final int ARM64_INS_FCVT = 85; + public static final int ARM64_INS_FCVTL = 86; + public static final int ARM64_INS_FCVTL2 = 87; + public static final int ARM64_INS_FCVTMS = 88; + public static final int ARM64_INS_FCVTMU = 89; + public static final int ARM64_INS_FCVTNS = 90; + public static final int ARM64_INS_FCVTNU = 91; + public static final int ARM64_INS_FCVTN = 92; + public static final int ARM64_INS_FCVTN2 = 93; + public static final int ARM64_INS_FCVTPS = 94; + public static final int ARM64_INS_FCVTPU = 95; + public static final int ARM64_INS_FCVTXN = 96; + public static final int ARM64_INS_FCVTXN2 = 97; + public static final int ARM64_INS_FCVTZS = 98; + public static final int ARM64_INS_FCVTZU = 99; + public static final int ARM64_INS_FDIV = 100; + public static final int ARM64_INS_FMADD = 101; + public static final int ARM64_INS_FMAX = 102; + public static final int ARM64_INS_FMAXNM = 103; + public static final int ARM64_INS_FMAXNMP = 104; + public static final int ARM64_INS_FMAXNMV = 105; + public static final int ARM64_INS_FMAXP = 106; + public static final int ARM64_INS_FMAXV = 107; + public static final int ARM64_INS_FMIN = 108; + public static final int ARM64_INS_FMINNM = 109; + public static final int ARM64_INS_FMINNMP = 110; + public static final int ARM64_INS_FMINNMV = 111; + public static final int ARM64_INS_FMINP = 112; + public static final int ARM64_INS_FMINV = 113; + public static final int ARM64_INS_FMLA = 114; + public static final int ARM64_INS_FMLS = 115; + public static final int ARM64_INS_FMOV = 116; + public static final int ARM64_INS_FMSUB = 117; + public static final int ARM64_INS_FMUL = 118; + public static final int ARM64_INS_FMULX = 119; + public static final int ARM64_INS_FNEG = 120; + public static final int ARM64_INS_FNMADD = 121; + public static final int ARM64_INS_FNMSUB = 122; + public static final int ARM64_INS_FNMUL = 123; + public static final int ARM64_INS_FRECPE = 124; + public static final int ARM64_INS_FRECPS = 125; + public static final int ARM64_INS_FRECPX = 126; + public static final int ARM64_INS_FRINTA = 127; + public static final int ARM64_INS_FRINTI = 128; + public static final int ARM64_INS_FRINTM = 129; + public static final int ARM64_INS_FRINTN = 130; + public static final int ARM64_INS_FRINTP = 131; + public static final int ARM64_INS_FRINTX = 132; + public static final int ARM64_INS_FRINTZ = 133; + public static final int ARM64_INS_FRSQRTE = 134; + public static final int ARM64_INS_FRSQRTS = 135; + public static final int ARM64_INS_FSQRT = 136; + public static final int ARM64_INS_FSUB = 137; + public static final int ARM64_INS_HINT = 138; + public static final int ARM64_INS_HLT = 139; + public static final int ARM64_INS_HVC = 140; + public static final int ARM64_INS_INS = 141; + public static final int ARM64_INS_ISB = 142; + public static final int ARM64_INS_LD1 = 143; + public static final int ARM64_INS_LD1R = 144; + public static final int ARM64_INS_LD2R = 145; + public static final int ARM64_INS_LD2 = 146; + public static final int ARM64_INS_LD3R = 147; + public static final int ARM64_INS_LD3 = 148; + public static final int ARM64_INS_LD4 = 149; + public static final int ARM64_INS_LD4R = 150; + public static final int ARM64_INS_LDARB = 151; + public static final int ARM64_INS_LDARH = 152; + public static final int ARM64_INS_LDAR = 153; + public static final int ARM64_INS_LDAXP = 154; + public static final int ARM64_INS_LDAXRB = 155; + public static final int ARM64_INS_LDAXRH = 156; + public static final int ARM64_INS_LDAXR = 157; + public static final int ARM64_INS_LDNP = 158; + public static final int ARM64_INS_LDP = 159; + public static final int ARM64_INS_LDPSW = 160; + public static final int ARM64_INS_LDRB = 161; + public static final int ARM64_INS_LDR = 162; + public static final int ARM64_INS_LDRH = 163; + public static final int ARM64_INS_LDRSB = 164; + public static final int ARM64_INS_LDRSH = 165; + public static final int ARM64_INS_LDRSW = 166; + public static final int ARM64_INS_LDTRB = 167; + public static final int ARM64_INS_LDTRH = 168; + public static final int ARM64_INS_LDTRSB = 169; + public static final int ARM64_INS_LDTRSH = 170; + public static final int ARM64_INS_LDTRSW = 171; + public static final int ARM64_INS_LDTR = 172; + public static final int ARM64_INS_LDURB = 173; + public static final int ARM64_INS_LDUR = 174; + public static final int ARM64_INS_LDURH = 175; + public static final int ARM64_INS_LDURSB = 176; + public static final int ARM64_INS_LDURSH = 177; + public static final int ARM64_INS_LDURSW = 178; + public static final int ARM64_INS_LDXP = 179; + public static final int ARM64_INS_LDXRB = 180; + public static final int ARM64_INS_LDXRH = 181; + public static final int ARM64_INS_LDXR = 182; + public static final int ARM64_INS_LSL = 183; + public static final int ARM64_INS_LSR = 184; + public static final int ARM64_INS_MADD = 185; + public static final int ARM64_INS_MLA = 186; + public static final int ARM64_INS_MLS = 187; + public static final int ARM64_INS_MOVI = 188; + public static final int ARM64_INS_MOVK = 189; + public static final int ARM64_INS_MOVN = 190; + public static final int ARM64_INS_MOVZ = 191; + public static final int ARM64_INS_MRS = 192; + public static final int ARM64_INS_MSR = 193; + public static final int ARM64_INS_MSUB = 194; + public static final int ARM64_INS_MUL = 195; + public static final int ARM64_INS_MVNI = 196; + public static final int ARM64_INS_NEG = 197; + public static final int ARM64_INS_NOT = 198; + public static final int ARM64_INS_ORN = 199; + public static final int ARM64_INS_ORR = 200; + public static final int ARM64_INS_PMULL2 = 201; + public static final int ARM64_INS_PMULL = 202; + public static final int ARM64_INS_PMUL = 203; + public static final int ARM64_INS_PRFM = 204; + public static final int ARM64_INS_PRFUM = 205; + public static final int ARM64_INS_RADDHN = 206; + public static final int ARM64_INS_RADDHN2 = 207; + public static final int ARM64_INS_RBIT = 208; + public static final int ARM64_INS_RET = 209; + public static final int ARM64_INS_REV16 = 210; + public static final int ARM64_INS_REV32 = 211; + public static final int ARM64_INS_REV64 = 212; + public static final int ARM64_INS_REV = 213; + public static final int ARM64_INS_ROR = 214; + public static final int ARM64_INS_RSHRN2 = 215; + public static final int ARM64_INS_RSHRN = 216; + public static final int ARM64_INS_RSUBHN = 217; + public static final int ARM64_INS_RSUBHN2 = 218; + public static final int ARM64_INS_SABAL2 = 219; + public static final int ARM64_INS_SABAL = 220; + public static final int ARM64_INS_SABA = 221; + public static final int ARM64_INS_SABDL2 = 222; + public static final int ARM64_INS_SABDL = 223; + public static final int ARM64_INS_SABD = 224; + public static final int ARM64_INS_SADALP = 225; + public static final int ARM64_INS_SADDLP = 226; + public static final int ARM64_INS_SADDLV = 227; + public static final int ARM64_INS_SADDL2 = 228; + public static final int ARM64_INS_SADDL = 229; + public static final int ARM64_INS_SADDW2 = 230; + public static final int ARM64_INS_SADDW = 231; + public static final int ARM64_INS_SBC = 232; + public static final int ARM64_INS_SBFM = 233; + public static final int ARM64_INS_SCVTF = 234; + public static final int ARM64_INS_SDIV = 235; + public static final int ARM64_INS_SHA1C = 236; + public static final int ARM64_INS_SHA1H = 237; + public static final int ARM64_INS_SHA1M = 238; + public static final int ARM64_INS_SHA1P = 239; + public static final int ARM64_INS_SHA1SU0 = 240; + public static final int ARM64_INS_SHA1SU1 = 241; + public static final int ARM64_INS_SHA256H2 = 242; + public static final int ARM64_INS_SHA256H = 243; + public static final int ARM64_INS_SHA256SU0 = 244; + public static final int ARM64_INS_SHA256SU1 = 245; + public static final int ARM64_INS_SHADD = 246; + public static final int ARM64_INS_SHLL2 = 247; + public static final int ARM64_INS_SHLL = 248; + public static final int ARM64_INS_SHL = 249; + public static final int ARM64_INS_SHRN2 = 250; + public static final int ARM64_INS_SHRN = 251; + public static final int ARM64_INS_SHSUB = 252; + public static final int ARM64_INS_SLI = 253; + public static final int ARM64_INS_SMADDL = 254; + public static final int ARM64_INS_SMAXP = 255; + public static final int ARM64_INS_SMAXV = 256; + public static final int ARM64_INS_SMAX = 257; + public static final int ARM64_INS_SMC = 258; + public static final int ARM64_INS_SMINP = 259; + public static final int ARM64_INS_SMINV = 260; + public static final int ARM64_INS_SMIN = 261; + public static final int ARM64_INS_SMLAL2 = 262; + public static final int ARM64_INS_SMLAL = 263; + public static final int ARM64_INS_SMLSL2 = 264; + public static final int ARM64_INS_SMLSL = 265; + public static final int ARM64_INS_SMOV = 266; + public static final int ARM64_INS_SMSUBL = 267; + public static final int ARM64_INS_SMULH = 268; + public static final int ARM64_INS_SMULL2 = 269; + public static final int ARM64_INS_SMULL = 270; + public static final int ARM64_INS_SQABS = 271; + public static final int ARM64_INS_SQADD = 272; + public static final int ARM64_INS_SQDMLAL = 273; + public static final int ARM64_INS_SQDMLAL2 = 274; + public static final int ARM64_INS_SQDMLSL = 275; + public static final int ARM64_INS_SQDMLSL2 = 276; + public static final int ARM64_INS_SQDMULH = 277; + public static final int ARM64_INS_SQDMULL = 278; + public static final int ARM64_INS_SQDMULL2 = 279; + public static final int ARM64_INS_SQNEG = 280; + public static final int ARM64_INS_SQRDMULH = 281; + public static final int ARM64_INS_SQRSHL = 282; + public static final int ARM64_INS_SQRSHRN = 283; + public static final int ARM64_INS_SQRSHRN2 = 284; + public static final int ARM64_INS_SQRSHRUN = 285; + public static final int ARM64_INS_SQRSHRUN2 = 286; + public static final int ARM64_INS_SQSHLU = 287; + public static final int ARM64_INS_SQSHL = 288; + public static final int ARM64_INS_SQSHRN = 289; + public static final int ARM64_INS_SQSHRN2 = 290; + public static final int ARM64_INS_SQSHRUN = 291; + public static final int ARM64_INS_SQSHRUN2 = 292; + public static final int ARM64_INS_SQSUB = 293; + public static final int ARM64_INS_SQXTN2 = 294; + public static final int ARM64_INS_SQXTN = 295; + public static final int ARM64_INS_SQXTUN2 = 296; + public static final int ARM64_INS_SQXTUN = 297; + public static final int ARM64_INS_SRHADD = 298; + public static final int ARM64_INS_SRI = 299; + public static final int ARM64_INS_SRSHL = 300; + public static final int ARM64_INS_SRSHR = 301; + public static final int ARM64_INS_SRSRA = 302; + public static final int ARM64_INS_SSHLL2 = 303; + public static final int ARM64_INS_SSHLL = 304; + public static final int ARM64_INS_SSHL = 305; + public static final int ARM64_INS_SSHR = 306; + public static final int ARM64_INS_SSRA = 307; + public static final int ARM64_INS_SSUBL2 = 308; + public static final int ARM64_INS_SSUBL = 309; + public static final int ARM64_INS_SSUBW2 = 310; + public static final int ARM64_INS_SSUBW = 311; + public static final int ARM64_INS_ST1 = 312; + public static final int ARM64_INS_ST2 = 313; + public static final int ARM64_INS_ST3 = 314; + public static final int ARM64_INS_ST4 = 315; + public static final int ARM64_INS_STLRB = 316; + public static final int ARM64_INS_STLRH = 317; + public static final int ARM64_INS_STLR = 318; + public static final int ARM64_INS_STLXP = 319; + public static final int ARM64_INS_STLXRB = 320; + public static final int ARM64_INS_STLXRH = 321; + public static final int ARM64_INS_STLXR = 322; + public static final int ARM64_INS_STNP = 323; + public static final int ARM64_INS_STP = 324; + public static final int ARM64_INS_STRB = 325; + public static final int ARM64_INS_STR = 326; + public static final int ARM64_INS_STRH = 327; + public static final int ARM64_INS_STTRB = 328; + public static final int ARM64_INS_STTRH = 329; + public static final int ARM64_INS_STTR = 330; + public static final int ARM64_INS_STURB = 331; + public static final int ARM64_INS_STUR = 332; + public static final int ARM64_INS_STURH = 333; + public static final int ARM64_INS_STXP = 334; + public static final int ARM64_INS_STXRB = 335; + public static final int ARM64_INS_STXRH = 336; + public static final int ARM64_INS_STXR = 337; + public static final int ARM64_INS_SUBHN = 338; + public static final int ARM64_INS_SUBHN2 = 339; + public static final int ARM64_INS_SUB = 340; + public static final int ARM64_INS_SUQADD = 341; + public static final int ARM64_INS_SVC = 342; + public static final int ARM64_INS_SYSL = 343; + public static final int ARM64_INS_SYS = 344; + public static final int ARM64_INS_TBL = 345; + public static final int ARM64_INS_TBNZ = 346; + public static final int ARM64_INS_TBX = 347; + public static final int ARM64_INS_TBZ = 348; + public static final int ARM64_INS_TRN1 = 349; + public static final int ARM64_INS_TRN2 = 350; + public static final int ARM64_INS_UABAL2 = 351; + public static final int ARM64_INS_UABAL = 352; + public static final int ARM64_INS_UABA = 353; + public static final int ARM64_INS_UABDL2 = 354; + public static final int ARM64_INS_UABDL = 355; + public static final int ARM64_INS_UABD = 356; + public static final int ARM64_INS_UADALP = 357; + public static final int ARM64_INS_UADDLP = 358; + public static final int ARM64_INS_UADDLV = 359; + public static final int ARM64_INS_UADDL2 = 360; + public static final int ARM64_INS_UADDL = 361; + public static final int ARM64_INS_UADDW2 = 362; + public static final int ARM64_INS_UADDW = 363; + public static final int ARM64_INS_UBFM = 364; + public static final int ARM64_INS_UCVTF = 365; + public static final int ARM64_INS_UDIV = 366; + public static final int ARM64_INS_UHADD = 367; + public static final int ARM64_INS_UHSUB = 368; + public static final int ARM64_INS_UMADDL = 369; + public static final int ARM64_INS_UMAXP = 370; + public static final int ARM64_INS_UMAXV = 371; + public static final int ARM64_INS_UMAX = 372; + public static final int ARM64_INS_UMINP = 373; + public static final int ARM64_INS_UMINV = 374; + public static final int ARM64_INS_UMIN = 375; + public static final int ARM64_INS_UMLAL2 = 376; + public static final int ARM64_INS_UMLAL = 377; + public static final int ARM64_INS_UMLSL2 = 378; + public static final int ARM64_INS_UMLSL = 379; + public static final int ARM64_INS_UMOV = 380; + public static final int ARM64_INS_UMSUBL = 381; + public static final int ARM64_INS_UMULH = 382; + public static final int ARM64_INS_UMULL2 = 383; + public static final int ARM64_INS_UMULL = 384; + public static final int ARM64_INS_UQADD = 385; + public static final int ARM64_INS_UQRSHL = 386; + public static final int ARM64_INS_UQRSHRN = 387; + public static final int ARM64_INS_UQRSHRN2 = 388; + public static final int ARM64_INS_UQSHL = 389; + public static final int ARM64_INS_UQSHRN = 390; + public static final int ARM64_INS_UQSHRN2 = 391; + public static final int ARM64_INS_UQSUB = 392; + public static final int ARM64_INS_UQXTN2 = 393; + public static final int ARM64_INS_UQXTN = 394; + public static final int ARM64_INS_URECPE = 395; + public static final int ARM64_INS_URHADD = 396; + public static final int ARM64_INS_URSHL = 397; + public static final int ARM64_INS_URSHR = 398; + public static final int ARM64_INS_URSQRTE = 399; + public static final int ARM64_INS_URSRA = 400; + public static final int ARM64_INS_USHLL2 = 401; + public static final int ARM64_INS_USHLL = 402; + public static final int ARM64_INS_USHL = 403; + public static final int ARM64_INS_USHR = 404; + public static final int ARM64_INS_USQADD = 405; + public static final int ARM64_INS_USRA = 406; + public static final int ARM64_INS_USUBL2 = 407; + public static final int ARM64_INS_USUBL = 408; + public static final int ARM64_INS_USUBW2 = 409; + public static final int ARM64_INS_USUBW = 410; + public static final int ARM64_INS_UZP1 = 411; + public static final int ARM64_INS_UZP2 = 412; + public static final int ARM64_INS_XTN2 = 413; + public static final int ARM64_INS_XTN = 414; + public static final int ARM64_INS_ZIP1 = 415; + public static final int ARM64_INS_ZIP2 = 416; + public static final int ARM64_INS_MNEG = 417; + public static final int ARM64_INS_UMNEGL = 418; + public static final int ARM64_INS_SMNEGL = 419; + public static final int ARM64_INS_NOP = 420; + public static final int ARM64_INS_YIELD = 421; + public static final int ARM64_INS_WFE = 422; + public static final int ARM64_INS_WFI = 423; + public static final int ARM64_INS_SEV = 424; + public static final int ARM64_INS_SEVL = 425; + public static final int ARM64_INS_NGC = 426; + public static final int ARM64_INS_SBFIZ = 427; + public static final int ARM64_INS_UBFIZ = 428; + public static final int ARM64_INS_SBFX = 429; + public static final int ARM64_INS_UBFX = 430; + public static final int ARM64_INS_BFI = 431; + public static final int ARM64_INS_BFXIL = 432; + public static final int ARM64_INS_CMN = 433; + public static final int ARM64_INS_MVN = 434; + public static final int ARM64_INS_TST = 435; + public static final int ARM64_INS_CSET = 436; + public static final int ARM64_INS_CINC = 437; + public static final int ARM64_INS_CSETM = 438; + public static final int ARM64_INS_CINV = 439; + public static final int ARM64_INS_CNEG = 440; + public static final int ARM64_INS_SXTB = 441; + public static final int ARM64_INS_SXTH = 442; + public static final int ARM64_INS_SXTW = 443; + public static final int ARM64_INS_CMP = 444; + public static final int ARM64_INS_UXTB = 445; + public static final int ARM64_INS_UXTH = 446; + public static final int ARM64_INS_UXTW = 447; + public static final int ARM64_INS_IC = 448; + public static final int ARM64_INS_DC = 449; + public static final int ARM64_INS_AT = 450; + public static final int ARM64_INS_TLBI = 451; + public static final int ARM64_INS_NEGS = 452; + public static final int ARM64_INS_NGCS = 453; + public static final int ARM64_INS_ENDING = 454; + + public static final int ARM64_GRP_INVALID = 0; + public static final int ARM64_GRP_JUMP = 1; + public static final int ARM64_GRP_CALL = 2; + public static final int ARM64_GRP_RET = 3; + public static final int ARM64_GRP_INT = 4; + public static final int ARM64_GRP_PRIVILEGE = 6; + public static final int ARM64_GRP_BRANCH_RELATIVE = 7; + public static final int ARM64_GRP_CRYPTO = 128; + public static final int ARM64_GRP_FPARMV8 = 129; + public static final int ARM64_GRP_NEON = 130; + public static final int ARM64_GRP_CRC = 131; + public static final int ARM64_GRP_ENDING = 132; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Arm_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Arm_const.java new file mode 100644 index 0000000..01f21c3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Arm_const.java @@ -0,0 +1,779 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Arm_const { + + public static final int ARM_SFT_INVALID = 0; + public static final int ARM_SFT_ASR = 1; + public static final int ARM_SFT_LSL = 2; + public static final int ARM_SFT_LSR = 3; + public static final int ARM_SFT_ROR = 4; + public static final int ARM_SFT_RRX = 5; + public static final int ARM_SFT_ASR_REG = 6; + public static final int ARM_SFT_LSL_REG = 7; + public static final int ARM_SFT_LSR_REG = 8; + public static final int ARM_SFT_ROR_REG = 9; + public static final int ARM_SFT_RRX_REG = 10; + + public static final int ARM_CC_INVALID = 0; + public static final int ARM_CC_EQ = 1; + public static final int ARM_CC_NE = 2; + public static final int ARM_CC_HS = 3; + public static final int ARM_CC_LO = 4; + public static final int ARM_CC_MI = 5; + public static final int ARM_CC_PL = 6; + public static final int ARM_CC_VS = 7; + public static final int ARM_CC_VC = 8; + public static final int ARM_CC_HI = 9; + public static final int ARM_CC_LS = 10; + public static final int ARM_CC_GE = 11; + public static final int ARM_CC_LT = 12; + public static final int ARM_CC_GT = 13; + public static final int ARM_CC_LE = 14; + public static final int ARM_CC_AL = 15; + + public static final int ARM_SYSREG_INVALID = 0; + public static final int ARM_SYSREG_SPSR_C = 1; + public static final int ARM_SYSREG_SPSR_X = 2; + public static final int ARM_SYSREG_SPSR_S = 4; + public static final int ARM_SYSREG_SPSR_F = 8; + public static final int ARM_SYSREG_CPSR_C = 16; + public static final int ARM_SYSREG_CPSR_X = 32; + public static final int ARM_SYSREG_CPSR_S = 64; + public static final int ARM_SYSREG_CPSR_F = 128; + public static final int ARM_SYSREG_APSR = 256; + public static final int ARM_SYSREG_APSR_G = 257; + public static final int ARM_SYSREG_APSR_NZCVQ = 258; + public static final int ARM_SYSREG_APSR_NZCVQG = 259; + public static final int ARM_SYSREG_IAPSR = 260; + public static final int ARM_SYSREG_IAPSR_G = 261; + public static final int ARM_SYSREG_IAPSR_NZCVQG = 262; + public static final int ARM_SYSREG_IAPSR_NZCVQ = 263; + public static final int ARM_SYSREG_EAPSR = 264; + public static final int ARM_SYSREG_EAPSR_G = 265; + public static final int ARM_SYSREG_EAPSR_NZCVQG = 266; + public static final int ARM_SYSREG_EAPSR_NZCVQ = 267; + public static final int ARM_SYSREG_XPSR = 268; + public static final int ARM_SYSREG_XPSR_G = 269; + public static final int ARM_SYSREG_XPSR_NZCVQG = 270; + public static final int ARM_SYSREG_XPSR_NZCVQ = 271; + public static final int ARM_SYSREG_IPSR = 272; + public static final int ARM_SYSREG_EPSR = 273; + public static final int ARM_SYSREG_IEPSR = 274; + public static final int ARM_SYSREG_MSP = 275; + public static final int ARM_SYSREG_PSP = 276; + public static final int ARM_SYSREG_PRIMASK = 277; + public static final int ARM_SYSREG_BASEPRI = 278; + public static final int ARM_SYSREG_BASEPRI_MAX = 279; + public static final int ARM_SYSREG_FAULTMASK = 280; + public static final int ARM_SYSREG_CONTROL = 281; + public static final int ARM_SYSREG_R8_USR = 282; + public static final int ARM_SYSREG_R9_USR = 283; + public static final int ARM_SYSREG_R10_USR = 284; + public static final int ARM_SYSREG_R11_USR = 285; + public static final int ARM_SYSREG_R12_USR = 286; + public static final int ARM_SYSREG_SP_USR = 287; + public static final int ARM_SYSREG_LR_USR = 288; + public static final int ARM_SYSREG_R8_FIQ = 289; + public static final int ARM_SYSREG_R9_FIQ = 290; + public static final int ARM_SYSREG_R10_FIQ = 291; + public static final int ARM_SYSREG_R11_FIQ = 292; + public static final int ARM_SYSREG_R12_FIQ = 293; + public static final int ARM_SYSREG_SP_FIQ = 294; + public static final int ARM_SYSREG_LR_FIQ = 295; + public static final int ARM_SYSREG_LR_IRQ = 296; + public static final int ARM_SYSREG_SP_IRQ = 297; + public static final int ARM_SYSREG_LR_SVC = 298; + public static final int ARM_SYSREG_SP_SVC = 299; + public static final int ARM_SYSREG_LR_ABT = 300; + public static final int ARM_SYSREG_SP_ABT = 301; + public static final int ARM_SYSREG_LR_UND = 302; + public static final int ARM_SYSREG_SP_UND = 303; + public static final int ARM_SYSREG_LR_MON = 304; + public static final int ARM_SYSREG_SP_MON = 305; + public static final int ARM_SYSREG_ELR_HYP = 306; + public static final int ARM_SYSREG_SP_HYP = 307; + public static final int ARM_SYSREG_SPSR_FIQ = 308; + public static final int ARM_SYSREG_SPSR_IRQ = 309; + public static final int ARM_SYSREG_SPSR_SVC = 310; + public static final int ARM_SYSREG_SPSR_ABT = 311; + public static final int ARM_SYSREG_SPSR_UND = 312; + public static final int ARM_SYSREG_SPSR_MON = 313; + public static final int ARM_SYSREG_SPSR_HYP = 314; + + public static final int ARM_MB_INVALID = 0; + public static final int ARM_MB_RESERVED_0 = 1; + public static final int ARM_MB_OSHLD = 2; + public static final int ARM_MB_OSHST = 3; + public static final int ARM_MB_OSH = 4; + public static final int ARM_MB_RESERVED_4 = 5; + public static final int ARM_MB_NSHLD = 6; + public static final int ARM_MB_NSHST = 7; + public static final int ARM_MB_NSH = 8; + public static final int ARM_MB_RESERVED_8 = 9; + public static final int ARM_MB_ISHLD = 10; + public static final int ARM_MB_ISHST = 11; + public static final int ARM_MB_ISH = 12; + public static final int ARM_MB_RESERVED_12 = 13; + public static final int ARM_MB_LD = 14; + public static final int ARM_MB_ST = 15; + public static final int ARM_MB_SY = 16; + + public static final int ARM_OP_INVALID = 0; + public static final int ARM_OP_REG = 1; + public static final int ARM_OP_IMM = 2; + public static final int ARM_OP_MEM = 3; + public static final int ARM_OP_FP = 4; + public static final int ARM_OP_CIMM = 64; + public static final int ARM_OP_PIMM = 65; + public static final int ARM_OP_SETEND = 66; + public static final int ARM_OP_SYSREG = 67; + + public static final int ARM_SETEND_INVALID = 0; + public static final int ARM_SETEND_BE = 1; + public static final int ARM_SETEND_LE = 2; + + public static final int ARM_CPSMODE_INVALID = 0; + public static final int ARM_CPSMODE_IE = 2; + public static final int ARM_CPSMODE_ID = 3; + + public static final int ARM_CPSFLAG_INVALID = 0; + public static final int ARM_CPSFLAG_F = 1; + public static final int ARM_CPSFLAG_I = 2; + public static final int ARM_CPSFLAG_A = 4; + public static final int ARM_CPSFLAG_NONE = 16; + + public static final int ARM_VECTORDATA_INVALID = 0; + public static final int ARM_VECTORDATA_I8 = 1; + public static final int ARM_VECTORDATA_I16 = 2; + public static final int ARM_VECTORDATA_I32 = 3; + public static final int ARM_VECTORDATA_I64 = 4; + public static final int ARM_VECTORDATA_S8 = 5; + public static final int ARM_VECTORDATA_S16 = 6; + public static final int ARM_VECTORDATA_S32 = 7; + public static final int ARM_VECTORDATA_S64 = 8; + public static final int ARM_VECTORDATA_U8 = 9; + public static final int ARM_VECTORDATA_U16 = 10; + public static final int ARM_VECTORDATA_U32 = 11; + public static final int ARM_VECTORDATA_U64 = 12; + public static final int ARM_VECTORDATA_P8 = 13; + public static final int ARM_VECTORDATA_F32 = 14; + public static final int ARM_VECTORDATA_F64 = 15; + public static final int ARM_VECTORDATA_F16F64 = 16; + public static final int ARM_VECTORDATA_F64F16 = 17; + public static final int ARM_VECTORDATA_F32F16 = 18; + public static final int ARM_VECTORDATA_F16F32 = 19; + public static final int ARM_VECTORDATA_F64F32 = 20; + public static final int ARM_VECTORDATA_F32F64 = 21; + public static final int ARM_VECTORDATA_S32F32 = 22; + public static final int ARM_VECTORDATA_U32F32 = 23; + public static final int ARM_VECTORDATA_F32S32 = 24; + public static final int ARM_VECTORDATA_F32U32 = 25; + public static final int ARM_VECTORDATA_F64S16 = 26; + public static final int ARM_VECTORDATA_F32S16 = 27; + public static final int ARM_VECTORDATA_F64S32 = 28; + public static final int ARM_VECTORDATA_S16F64 = 29; + public static final int ARM_VECTORDATA_S16F32 = 30; + public static final int ARM_VECTORDATA_S32F64 = 31; + public static final int ARM_VECTORDATA_U16F64 = 32; + public static final int ARM_VECTORDATA_U16F32 = 33; + public static final int ARM_VECTORDATA_U32F64 = 34; + public static final int ARM_VECTORDATA_F64U16 = 35; + public static final int ARM_VECTORDATA_F32U16 = 36; + public static final int ARM_VECTORDATA_F64U32 = 37; + + public static final int ARM_REG_INVALID = 0; + public static final int ARM_REG_APSR = 1; + public static final int ARM_REG_APSR_NZCV = 2; + public static final int ARM_REG_CPSR = 3; + public static final int ARM_REG_FPEXC = 4; + public static final int ARM_REG_FPINST = 5; + public static final int ARM_REG_FPSCR = 6; + public static final int ARM_REG_FPSCR_NZCV = 7; + public static final int ARM_REG_FPSID = 8; + public static final int ARM_REG_ITSTATE = 9; + public static final int ARM_REG_LR = 10; + public static final int ARM_REG_PC = 11; + public static final int ARM_REG_SP = 12; + public static final int ARM_REG_SPSR = 13; + public static final int ARM_REG_D0 = 14; + public static final int ARM_REG_D1 = 15; + public static final int ARM_REG_D2 = 16; + public static final int ARM_REG_D3 = 17; + public static final int ARM_REG_D4 = 18; + public static final int ARM_REG_D5 = 19; + public static final int ARM_REG_D6 = 20; + public static final int ARM_REG_D7 = 21; + public static final int ARM_REG_D8 = 22; + public static final int ARM_REG_D9 = 23; + public static final int ARM_REG_D10 = 24; + public static final int ARM_REG_D11 = 25; + public static final int ARM_REG_D12 = 26; + public static final int ARM_REG_D13 = 27; + public static final int ARM_REG_D14 = 28; + public static final int ARM_REG_D15 = 29; + public static final int ARM_REG_D16 = 30; + public static final int ARM_REG_D17 = 31; + public static final int ARM_REG_D18 = 32; + public static final int ARM_REG_D19 = 33; + public static final int ARM_REG_D20 = 34; + public static final int ARM_REG_D21 = 35; + public static final int ARM_REG_D22 = 36; + public static final int ARM_REG_D23 = 37; + public static final int ARM_REG_D24 = 38; + public static final int ARM_REG_D25 = 39; + public static final int ARM_REG_D26 = 40; + public static final int ARM_REG_D27 = 41; + public static final int ARM_REG_D28 = 42; + public static final int ARM_REG_D29 = 43; + public static final int ARM_REG_D30 = 44; + public static final int ARM_REG_D31 = 45; + public static final int ARM_REG_FPINST2 = 46; + public static final int ARM_REG_MVFR0 = 47; + public static final int ARM_REG_MVFR1 = 48; + public static final int ARM_REG_MVFR2 = 49; + public static final int ARM_REG_Q0 = 50; + public static final int ARM_REG_Q1 = 51; + public static final int ARM_REG_Q2 = 52; + public static final int ARM_REG_Q3 = 53; + public static final int ARM_REG_Q4 = 54; + public static final int ARM_REG_Q5 = 55; + public static final int ARM_REG_Q6 = 56; + public static final int ARM_REG_Q7 = 57; + public static final int ARM_REG_Q8 = 58; + public static final int ARM_REG_Q9 = 59; + public static final int ARM_REG_Q10 = 60; + public static final int ARM_REG_Q11 = 61; + public static final int ARM_REG_Q12 = 62; + public static final int ARM_REG_Q13 = 63; + public static final int ARM_REG_Q14 = 64; + public static final int ARM_REG_Q15 = 65; + public static final int ARM_REG_R0 = 66; + public static final int ARM_REG_R1 = 67; + public static final int ARM_REG_R2 = 68; + public static final int ARM_REG_R3 = 69; + public static final int ARM_REG_R4 = 70; + public static final int ARM_REG_R5 = 71; + public static final int ARM_REG_R6 = 72; + public static final int ARM_REG_R7 = 73; + public static final int ARM_REG_R8 = 74; + public static final int ARM_REG_R9 = 75; + public static final int ARM_REG_R10 = 76; + public static final int ARM_REG_R11 = 77; + public static final int ARM_REG_R12 = 78; + public static final int ARM_REG_S0 = 79; + public static final int ARM_REG_S1 = 80; + public static final int ARM_REG_S2 = 81; + public static final int ARM_REG_S3 = 82; + public static final int ARM_REG_S4 = 83; + public static final int ARM_REG_S5 = 84; + public static final int ARM_REG_S6 = 85; + public static final int ARM_REG_S7 = 86; + public static final int ARM_REG_S8 = 87; + public static final int ARM_REG_S9 = 88; + public static final int ARM_REG_S10 = 89; + public static final int ARM_REG_S11 = 90; + public static final int ARM_REG_S12 = 91; + public static final int ARM_REG_S13 = 92; + public static final int ARM_REG_S14 = 93; + public static final int ARM_REG_S15 = 94; + public static final int ARM_REG_S16 = 95; + public static final int ARM_REG_S17 = 96; + public static final int ARM_REG_S18 = 97; + public static final int ARM_REG_S19 = 98; + public static final int ARM_REG_S20 = 99; + public static final int ARM_REG_S21 = 100; + public static final int ARM_REG_S22 = 101; + public static final int ARM_REG_S23 = 102; + public static final int ARM_REG_S24 = 103; + public static final int ARM_REG_S25 = 104; + public static final int ARM_REG_S26 = 105; + public static final int ARM_REG_S27 = 106; + public static final int ARM_REG_S28 = 107; + public static final int ARM_REG_S29 = 108; + public static final int ARM_REG_S30 = 109; + public static final int ARM_REG_S31 = 110; + public static final int ARM_REG_ENDING = 111; + public static final int ARM_REG_R13 = ARM_REG_SP; + public static final int ARM_REG_R14 = ARM_REG_LR; + public static final int ARM_REG_R15 = ARM_REG_PC; + public static final int ARM_REG_SB = ARM_REG_R9; + public static final int ARM_REG_SL = ARM_REG_R10; + public static final int ARM_REG_FP = ARM_REG_R11; + public static final int ARM_REG_IP = ARM_REG_R12; + + public static final int ARM_INS_INVALID = 0; + public static final int ARM_INS_ADC = 1; + public static final int ARM_INS_ADD = 2; + public static final int ARM_INS_ADR = 3; + public static final int ARM_INS_AESD = 4; + public static final int ARM_INS_AESE = 5; + public static final int ARM_INS_AESIMC = 6; + public static final int ARM_INS_AESMC = 7; + public static final int ARM_INS_AND = 8; + public static final int ARM_INS_BFC = 9; + public static final int ARM_INS_BFI = 10; + public static final int ARM_INS_BIC = 11; + public static final int ARM_INS_BKPT = 12; + public static final int ARM_INS_BL = 13; + public static final int ARM_INS_BLX = 14; + public static final int ARM_INS_BX = 15; + public static final int ARM_INS_BXJ = 16; + public static final int ARM_INS_B = 17; + public static final int ARM_INS_CDP = 18; + public static final int ARM_INS_CDP2 = 19; + public static final int ARM_INS_CLREX = 20; + public static final int ARM_INS_CLZ = 21; + public static final int ARM_INS_CMN = 22; + public static final int ARM_INS_CMP = 23; + public static final int ARM_INS_CPS = 24; + public static final int ARM_INS_CRC32B = 25; + public static final int ARM_INS_CRC32CB = 26; + public static final int ARM_INS_CRC32CH = 27; + public static final int ARM_INS_CRC32CW = 28; + public static final int ARM_INS_CRC32H = 29; + public static final int ARM_INS_CRC32W = 30; + public static final int ARM_INS_DBG = 31; + public static final int ARM_INS_DMB = 32; + public static final int ARM_INS_DSB = 33; + public static final int ARM_INS_EOR = 34; + public static final int ARM_INS_ERET = 35; + public static final int ARM_INS_VMOV = 36; + public static final int ARM_INS_FLDMDBX = 37; + public static final int ARM_INS_FLDMIAX = 38; + public static final int ARM_INS_VMRS = 39; + public static final int ARM_INS_FSTMDBX = 40; + public static final int ARM_INS_FSTMIAX = 41; + public static final int ARM_INS_HINT = 42; + public static final int ARM_INS_HLT = 43; + public static final int ARM_INS_HVC = 44; + public static final int ARM_INS_ISB = 45; + public static final int ARM_INS_LDA = 46; + public static final int ARM_INS_LDAB = 47; + public static final int ARM_INS_LDAEX = 48; + public static final int ARM_INS_LDAEXB = 49; + public static final int ARM_INS_LDAEXD = 50; + public static final int ARM_INS_LDAEXH = 51; + public static final int ARM_INS_LDAH = 52; + public static final int ARM_INS_LDC2L = 53; + public static final int ARM_INS_LDC2 = 54; + public static final int ARM_INS_LDCL = 55; + public static final int ARM_INS_LDC = 56; + public static final int ARM_INS_LDMDA = 57; + public static final int ARM_INS_LDMDB = 58; + public static final int ARM_INS_LDM = 59; + public static final int ARM_INS_LDMIB = 60; + public static final int ARM_INS_LDRBT = 61; + public static final int ARM_INS_LDRB = 62; + public static final int ARM_INS_LDRD = 63; + public static final int ARM_INS_LDREX = 64; + public static final int ARM_INS_LDREXB = 65; + public static final int ARM_INS_LDREXD = 66; + public static final int ARM_INS_LDREXH = 67; + public static final int ARM_INS_LDRH = 68; + public static final int ARM_INS_LDRHT = 69; + public static final int ARM_INS_LDRSB = 70; + public static final int ARM_INS_LDRSBT = 71; + public static final int ARM_INS_LDRSH = 72; + public static final int ARM_INS_LDRSHT = 73; + public static final int ARM_INS_LDRT = 74; + public static final int ARM_INS_LDR = 75; + public static final int ARM_INS_MCR = 76; + public static final int ARM_INS_MCR2 = 77; + public static final int ARM_INS_MCRR = 78; + public static final int ARM_INS_MCRR2 = 79; + public static final int ARM_INS_MLA = 80; + public static final int ARM_INS_MLS = 81; + public static final int ARM_INS_MOV = 82; + public static final int ARM_INS_MOVT = 83; + public static final int ARM_INS_MOVW = 84; + public static final int ARM_INS_MRC = 85; + public static final int ARM_INS_MRC2 = 86; + public static final int ARM_INS_MRRC = 87; + public static final int ARM_INS_MRRC2 = 88; + public static final int ARM_INS_MRS = 89; + public static final int ARM_INS_MSR = 90; + public static final int ARM_INS_MUL = 91; + public static final int ARM_INS_MVN = 92; + public static final int ARM_INS_ORR = 93; + public static final int ARM_INS_PKHBT = 94; + public static final int ARM_INS_PKHTB = 95; + public static final int ARM_INS_PLDW = 96; + public static final int ARM_INS_PLD = 97; + public static final int ARM_INS_PLI = 98; + public static final int ARM_INS_QADD = 99; + public static final int ARM_INS_QADD16 = 100; + public static final int ARM_INS_QADD8 = 101; + public static final int ARM_INS_QASX = 102; + public static final int ARM_INS_QDADD = 103; + public static final int ARM_INS_QDSUB = 104; + public static final int ARM_INS_QSAX = 105; + public static final int ARM_INS_QSUB = 106; + public static final int ARM_INS_QSUB16 = 107; + public static final int ARM_INS_QSUB8 = 108; + public static final int ARM_INS_RBIT = 109; + public static final int ARM_INS_REV = 110; + public static final int ARM_INS_REV16 = 111; + public static final int ARM_INS_REVSH = 112; + public static final int ARM_INS_RFEDA = 113; + public static final int ARM_INS_RFEDB = 114; + public static final int ARM_INS_RFEIA = 115; + public static final int ARM_INS_RFEIB = 116; + public static final int ARM_INS_RSB = 117; + public static final int ARM_INS_RSC = 118; + public static final int ARM_INS_SADD16 = 119; + public static final int ARM_INS_SADD8 = 120; + public static final int ARM_INS_SASX = 121; + public static final int ARM_INS_SBC = 122; + public static final int ARM_INS_SBFX = 123; + public static final int ARM_INS_SDIV = 124; + public static final int ARM_INS_SEL = 125; + public static final int ARM_INS_SETEND = 126; + public static final int ARM_INS_SHA1C = 127; + public static final int ARM_INS_SHA1H = 128; + public static final int ARM_INS_SHA1M = 129; + public static final int ARM_INS_SHA1P = 130; + public static final int ARM_INS_SHA1SU0 = 131; + public static final int ARM_INS_SHA1SU1 = 132; + public static final int ARM_INS_SHA256H = 133; + public static final int ARM_INS_SHA256H2 = 134; + public static final int ARM_INS_SHA256SU0 = 135; + public static final int ARM_INS_SHA256SU1 = 136; + public static final int ARM_INS_SHADD16 = 137; + public static final int ARM_INS_SHADD8 = 138; + public static final int ARM_INS_SHASX = 139; + public static final int ARM_INS_SHSAX = 140; + public static final int ARM_INS_SHSUB16 = 141; + public static final int ARM_INS_SHSUB8 = 142; + public static final int ARM_INS_SMC = 143; + public static final int ARM_INS_SMLABB = 144; + public static final int ARM_INS_SMLABT = 145; + public static final int ARM_INS_SMLAD = 146; + public static final int ARM_INS_SMLADX = 147; + public static final int ARM_INS_SMLAL = 148; + public static final int ARM_INS_SMLALBB = 149; + public static final int ARM_INS_SMLALBT = 150; + public static final int ARM_INS_SMLALD = 151; + public static final int ARM_INS_SMLALDX = 152; + public static final int ARM_INS_SMLALTB = 153; + public static final int ARM_INS_SMLALTT = 154; + public static final int ARM_INS_SMLATB = 155; + public static final int ARM_INS_SMLATT = 156; + public static final int ARM_INS_SMLAWB = 157; + public static final int ARM_INS_SMLAWT = 158; + public static final int ARM_INS_SMLSD = 159; + public static final int ARM_INS_SMLSDX = 160; + public static final int ARM_INS_SMLSLD = 161; + public static final int ARM_INS_SMLSLDX = 162; + public static final int ARM_INS_SMMLA = 163; + public static final int ARM_INS_SMMLAR = 164; + public static final int ARM_INS_SMMLS = 165; + public static final int ARM_INS_SMMLSR = 166; + public static final int ARM_INS_SMMUL = 167; + public static final int ARM_INS_SMMULR = 168; + public static final int ARM_INS_SMUAD = 169; + public static final int ARM_INS_SMUADX = 170; + public static final int ARM_INS_SMULBB = 171; + public static final int ARM_INS_SMULBT = 172; + public static final int ARM_INS_SMULL = 173; + public static final int ARM_INS_SMULTB = 174; + public static final int ARM_INS_SMULTT = 175; + public static final int ARM_INS_SMULWB = 176; + public static final int ARM_INS_SMULWT = 177; + public static final int ARM_INS_SMUSD = 178; + public static final int ARM_INS_SMUSDX = 179; + public static final int ARM_INS_SRSDA = 180; + public static final int ARM_INS_SRSDB = 181; + public static final int ARM_INS_SRSIA = 182; + public static final int ARM_INS_SRSIB = 183; + public static final int ARM_INS_SSAT = 184; + public static final int ARM_INS_SSAT16 = 185; + public static final int ARM_INS_SSAX = 186; + public static final int ARM_INS_SSUB16 = 187; + public static final int ARM_INS_SSUB8 = 188; + public static final int ARM_INS_STC2L = 189; + public static final int ARM_INS_STC2 = 190; + public static final int ARM_INS_STCL = 191; + public static final int ARM_INS_STC = 192; + public static final int ARM_INS_STL = 193; + public static final int ARM_INS_STLB = 194; + public static final int ARM_INS_STLEX = 195; + public static final int ARM_INS_STLEXB = 196; + public static final int ARM_INS_STLEXD = 197; + public static final int ARM_INS_STLEXH = 198; + public static final int ARM_INS_STLH = 199; + public static final int ARM_INS_STMDA = 200; + public static final int ARM_INS_STMDB = 201; + public static final int ARM_INS_STM = 202; + public static final int ARM_INS_STMIB = 203; + public static final int ARM_INS_STRBT = 204; + public static final int ARM_INS_STRB = 205; + public static final int ARM_INS_STRD = 206; + public static final int ARM_INS_STREX = 207; + public static final int ARM_INS_STREXB = 208; + public static final int ARM_INS_STREXD = 209; + public static final int ARM_INS_STREXH = 210; + public static final int ARM_INS_STRH = 211; + public static final int ARM_INS_STRHT = 212; + public static final int ARM_INS_STRT = 213; + public static final int ARM_INS_STR = 214; + public static final int ARM_INS_SUB = 215; + public static final int ARM_INS_SVC = 216; + public static final int ARM_INS_SWP = 217; + public static final int ARM_INS_SWPB = 218; + public static final int ARM_INS_SXTAB = 219; + public static final int ARM_INS_SXTAB16 = 220; + public static final int ARM_INS_SXTAH = 221; + public static final int ARM_INS_SXTB = 222; + public static final int ARM_INS_SXTB16 = 223; + public static final int ARM_INS_SXTH = 224; + public static final int ARM_INS_TEQ = 225; + public static final int ARM_INS_TRAP = 226; + public static final int ARM_INS_TST = 227; + public static final int ARM_INS_UADD16 = 228; + public static final int ARM_INS_UADD8 = 229; + public static final int ARM_INS_UASX = 230; + public static final int ARM_INS_UBFX = 231; + public static final int ARM_INS_UDF = 232; + public static final int ARM_INS_UDIV = 233; + public static final int ARM_INS_UHADD16 = 234; + public static final int ARM_INS_UHADD8 = 235; + public static final int ARM_INS_UHASX = 236; + public static final int ARM_INS_UHSAX = 237; + public static final int ARM_INS_UHSUB16 = 238; + public static final int ARM_INS_UHSUB8 = 239; + public static final int ARM_INS_UMAAL = 240; + public static final int ARM_INS_UMLAL = 241; + public static final int ARM_INS_UMULL = 242; + public static final int ARM_INS_UQADD16 = 243; + public static final int ARM_INS_UQADD8 = 244; + public static final int ARM_INS_UQASX = 245; + public static final int ARM_INS_UQSAX = 246; + public static final int ARM_INS_UQSUB16 = 247; + public static final int ARM_INS_UQSUB8 = 248; + public static final int ARM_INS_USAD8 = 249; + public static final int ARM_INS_USADA8 = 250; + public static final int ARM_INS_USAT = 251; + public static final int ARM_INS_USAT16 = 252; + public static final int ARM_INS_USAX = 253; + public static final int ARM_INS_USUB16 = 254; + public static final int ARM_INS_USUB8 = 255; + public static final int ARM_INS_UXTAB = 256; + public static final int ARM_INS_UXTAB16 = 257; + public static final int ARM_INS_UXTAH = 258; + public static final int ARM_INS_UXTB = 259; + public static final int ARM_INS_UXTB16 = 260; + public static final int ARM_INS_UXTH = 261; + public static final int ARM_INS_VABAL = 262; + public static final int ARM_INS_VABA = 263; + public static final int ARM_INS_VABDL = 264; + public static final int ARM_INS_VABD = 265; + public static final int ARM_INS_VABS = 266; + public static final int ARM_INS_VACGE = 267; + public static final int ARM_INS_VACGT = 268; + public static final int ARM_INS_VADD = 269; + public static final int ARM_INS_VADDHN = 270; + public static final int ARM_INS_VADDL = 271; + public static final int ARM_INS_VADDW = 272; + public static final int ARM_INS_VAND = 273; + public static final int ARM_INS_VBIC = 274; + public static final int ARM_INS_VBIF = 275; + public static final int ARM_INS_VBIT = 276; + public static final int ARM_INS_VBSL = 277; + public static final int ARM_INS_VCEQ = 278; + public static final int ARM_INS_VCGE = 279; + public static final int ARM_INS_VCGT = 280; + public static final int ARM_INS_VCLE = 281; + public static final int ARM_INS_VCLS = 282; + public static final int ARM_INS_VCLT = 283; + public static final int ARM_INS_VCLZ = 284; + public static final int ARM_INS_VCMP = 285; + public static final int ARM_INS_VCMPE = 286; + public static final int ARM_INS_VCNT = 287; + public static final int ARM_INS_VCVTA = 288; + public static final int ARM_INS_VCVTB = 289; + public static final int ARM_INS_VCVT = 290; + public static final int ARM_INS_VCVTM = 291; + public static final int ARM_INS_VCVTN = 292; + public static final int ARM_INS_VCVTP = 293; + public static final int ARM_INS_VCVTT = 294; + public static final int ARM_INS_VDIV = 295; + public static final int ARM_INS_VDUP = 296; + public static final int ARM_INS_VEOR = 297; + public static final int ARM_INS_VEXT = 298; + public static final int ARM_INS_VFMA = 299; + public static final int ARM_INS_VFMS = 300; + public static final int ARM_INS_VFNMA = 301; + public static final int ARM_INS_VFNMS = 302; + public static final int ARM_INS_VHADD = 303; + public static final int ARM_INS_VHSUB = 304; + public static final int ARM_INS_VLD1 = 305; + public static final int ARM_INS_VLD2 = 306; + public static final int ARM_INS_VLD3 = 307; + public static final int ARM_INS_VLD4 = 308; + public static final int ARM_INS_VLDMDB = 309; + public static final int ARM_INS_VLDMIA = 310; + public static final int ARM_INS_VLDR = 311; + public static final int ARM_INS_VMAXNM = 312; + public static final int ARM_INS_VMAX = 313; + public static final int ARM_INS_VMINNM = 314; + public static final int ARM_INS_VMIN = 315; + public static final int ARM_INS_VMLA = 316; + public static final int ARM_INS_VMLAL = 317; + public static final int ARM_INS_VMLS = 318; + public static final int ARM_INS_VMLSL = 319; + public static final int ARM_INS_VMOVL = 320; + public static final int ARM_INS_VMOVN = 321; + public static final int ARM_INS_VMSR = 322; + public static final int ARM_INS_VMUL = 323; + public static final int ARM_INS_VMULL = 324; + public static final int ARM_INS_VMVN = 325; + public static final int ARM_INS_VNEG = 326; + public static final int ARM_INS_VNMLA = 327; + public static final int ARM_INS_VNMLS = 328; + public static final int ARM_INS_VNMUL = 329; + public static final int ARM_INS_VORN = 330; + public static final int ARM_INS_VORR = 331; + public static final int ARM_INS_VPADAL = 332; + public static final int ARM_INS_VPADDL = 333; + public static final int ARM_INS_VPADD = 334; + public static final int ARM_INS_VPMAX = 335; + public static final int ARM_INS_VPMIN = 336; + public static final int ARM_INS_VQABS = 337; + public static final int ARM_INS_VQADD = 338; + public static final int ARM_INS_VQDMLAL = 339; + public static final int ARM_INS_VQDMLSL = 340; + public static final int ARM_INS_VQDMULH = 341; + public static final int ARM_INS_VQDMULL = 342; + public static final int ARM_INS_VQMOVUN = 343; + public static final int ARM_INS_VQMOVN = 344; + public static final int ARM_INS_VQNEG = 345; + public static final int ARM_INS_VQRDMULH = 346; + public static final int ARM_INS_VQRSHL = 347; + public static final int ARM_INS_VQRSHRN = 348; + public static final int ARM_INS_VQRSHRUN = 349; + public static final int ARM_INS_VQSHL = 350; + public static final int ARM_INS_VQSHLU = 351; + public static final int ARM_INS_VQSHRN = 352; + public static final int ARM_INS_VQSHRUN = 353; + public static final int ARM_INS_VQSUB = 354; + public static final int ARM_INS_VRADDHN = 355; + public static final int ARM_INS_VRECPE = 356; + public static final int ARM_INS_VRECPS = 357; + public static final int ARM_INS_VREV16 = 358; + public static final int ARM_INS_VREV32 = 359; + public static final int ARM_INS_VREV64 = 360; + public static final int ARM_INS_VRHADD = 361; + public static final int ARM_INS_VRINTA = 362; + public static final int ARM_INS_VRINTM = 363; + public static final int ARM_INS_VRINTN = 364; + public static final int ARM_INS_VRINTP = 365; + public static final int ARM_INS_VRINTR = 366; + public static final int ARM_INS_VRINTX = 367; + public static final int ARM_INS_VRINTZ = 368; + public static final int ARM_INS_VRSHL = 369; + public static final int ARM_INS_VRSHRN = 370; + public static final int ARM_INS_VRSHR = 371; + public static final int ARM_INS_VRSQRTE = 372; + public static final int ARM_INS_VRSQRTS = 373; + public static final int ARM_INS_VRSRA = 374; + public static final int ARM_INS_VRSUBHN = 375; + public static final int ARM_INS_VSELEQ = 376; + public static final int ARM_INS_VSELGE = 377; + public static final int ARM_INS_VSELGT = 378; + public static final int ARM_INS_VSELVS = 379; + public static final int ARM_INS_VSHLL = 380; + public static final int ARM_INS_VSHL = 381; + public static final int ARM_INS_VSHRN = 382; + public static final int ARM_INS_VSHR = 383; + public static final int ARM_INS_VSLI = 384; + public static final int ARM_INS_VSQRT = 385; + public static final int ARM_INS_VSRA = 386; + public static final int ARM_INS_VSRI = 387; + public static final int ARM_INS_VST1 = 388; + public static final int ARM_INS_VST2 = 389; + public static final int ARM_INS_VST3 = 390; + public static final int ARM_INS_VST4 = 391; + public static final int ARM_INS_VSTMDB = 392; + public static final int ARM_INS_VSTMIA = 393; + public static final int ARM_INS_VSTR = 394; + public static final int ARM_INS_VSUB = 395; + public static final int ARM_INS_VSUBHN = 396; + public static final int ARM_INS_VSUBL = 397; + public static final int ARM_INS_VSUBW = 398; + public static final int ARM_INS_VSWP = 399; + public static final int ARM_INS_VTBL = 400; + public static final int ARM_INS_VTBX = 401; + public static final int ARM_INS_VCVTR = 402; + public static final int ARM_INS_VTRN = 403; + public static final int ARM_INS_VTST = 404; + public static final int ARM_INS_VUZP = 405; + public static final int ARM_INS_VZIP = 406; + public static final int ARM_INS_ADDW = 407; + public static final int ARM_INS_ASR = 408; + public static final int ARM_INS_DCPS1 = 409; + public static final int ARM_INS_DCPS2 = 410; + public static final int ARM_INS_DCPS3 = 411; + public static final int ARM_INS_IT = 412; + public static final int ARM_INS_LSL = 413; + public static final int ARM_INS_LSR = 414; + public static final int ARM_INS_ORN = 415; + public static final int ARM_INS_ROR = 416; + public static final int ARM_INS_RRX = 417; + public static final int ARM_INS_SUBW = 418; + public static final int ARM_INS_TBB = 419; + public static final int ARM_INS_TBH = 420; + public static final int ARM_INS_CBNZ = 421; + public static final int ARM_INS_CBZ = 422; + public static final int ARM_INS_POP = 423; + public static final int ARM_INS_PUSH = 424; + public static final int ARM_INS_NOP = 425; + public static final int ARM_INS_YIELD = 426; + public static final int ARM_INS_WFE = 427; + public static final int ARM_INS_WFI = 428; + public static final int ARM_INS_SEV = 429; + public static final int ARM_INS_SEVL = 430; + public static final int ARM_INS_VPUSH = 431; + public static final int ARM_INS_VPOP = 432; + public static final int ARM_INS_ENDING = 433; + + public static final int ARM_GRP_INVALID = 0; + public static final int ARM_GRP_JUMP = 1; + public static final int ARM_GRP_CALL = 2; + public static final int ARM_GRP_INT = 4; + public static final int ARM_GRP_PRIVILEGE = 6; + public static final int ARM_GRP_BRANCH_RELATIVE = 7; + public static final int ARM_GRP_CRYPTO = 128; + public static final int ARM_GRP_DATABARRIER = 129; + public static final int ARM_GRP_DIVIDE = 130; + public static final int ARM_GRP_FPARMV8 = 131; + public static final int ARM_GRP_MULTPRO = 132; + public static final int ARM_GRP_NEON = 133; + public static final int ARM_GRP_T2EXTRACTPACK = 134; + public static final int ARM_GRP_THUMB2DSP = 135; + public static final int ARM_GRP_TRUSTZONE = 136; + public static final int ARM_GRP_V4T = 137; + public static final int ARM_GRP_V5T = 138; + public static final int ARM_GRP_V5TE = 139; + public static final int ARM_GRP_V6 = 140; + public static final int ARM_GRP_V6T2 = 141; + public static final int ARM_GRP_V7 = 142; + public static final int ARM_GRP_V8 = 143; + public static final int ARM_GRP_VFP2 = 144; + public static final int ARM_GRP_VFP3 = 145; + public static final int ARM_GRP_VFP4 = 146; + public static final int ARM_GRP_ARM = 147; + public static final int ARM_GRP_MCLASS = 148; + public static final int ARM_GRP_NOTMCLASS = 149; + public static final int ARM_GRP_THUMB = 150; + public static final int ARM_GRP_THUMB1ONLY = 151; + public static final int ARM_GRP_THUMB2 = 152; + public static final int ARM_GRP_PREV8 = 153; + public static final int ARM_GRP_FPVMLX = 154; + public static final int ARM_GRP_MULOPS = 155; + public static final int ARM_GRP_CRC = 156; + public static final int ARM_GRP_DPVFP = 157; + public static final int ARM_GRP_V6M = 158; + public static final int ARM_GRP_VIRTUALIZATION = 159; + public static final int ARM_GRP_ENDING = 160; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Capstone.java b/white_patch_detect/capstone-master/bindings/java/capstone/Capstone.java new file mode 100644 index 0000000..040c79e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Capstone.java @@ -0,0 +1,546 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Library; +import com.sun.jna.Memory; +import com.sun.jna.Native; +import com.sun.jna.NativeLong; +import com.sun.jna.ptr.ByteByReference; +import com.sun.jna.ptr.NativeLongByReference; +import com.sun.jna.Structure; +import com.sun.jna.Union; +import com.sun.jna.Pointer; +import com.sun.jna.ptr.PointerByReference; +import com.sun.jna.ptr.IntByReference; + +import java.util.List; +import java.util.Arrays; +import java.lang.RuntimeException; + +public class Capstone { + + protected static abstract class OpInfo {}; + protected static abstract class UnionOpInfo extends Structure {}; + + public static class UnionArch extends Union { + public static class ByValue extends UnionArch implements Union.ByValue {}; + + public Arm.UnionOpInfo arm; + public Arm64.UnionOpInfo arm64; + public X86.UnionOpInfo x86; + public Mips.UnionOpInfo mips; + public Ppc.UnionOpInfo ppc; + public Sparc.UnionOpInfo sparc; + public Systemz.UnionOpInfo sysz; + public Xcore.UnionOpInfo xcore; + public M680x.UnionOpInfo m680x; + } + + protected static class _cs_insn extends Structure { + // instruction ID. + public int id; + // instruction address. + public long address; + // instruction size. + public short size; + // machine bytes of instruction. + public byte[] bytes; + // instruction mnemonic. NOTE: irrelevant for diet engine. + public byte[] mnemonic; + // instruction operands. NOTE: irrelevant for diet engine. + public byte[] op_str; + // detail information of instruction. + public _cs_detail.ByReference cs_detail; + + public _cs_insn() { + bytes = new byte[24]; + mnemonic = new byte[32]; + op_str = new byte[160]; + java.util.Arrays.fill(mnemonic, (byte) 0); + java.util.Arrays.fill(op_str, (byte) 0); + } + + public _cs_insn(Pointer p) { + this(); + useMemory(p); + read(); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("id", "address", "size", "bytes", "mnemonic", "op_str", "cs_detail"); + } + } + + protected static class _cs_detail extends Structure { + public static class ByReference extends _cs_detail implements Structure.ByReference {}; + + // list of all implicit registers being read. + public short[] regs_read = new short[16]; + public byte regs_read_count; + // list of all implicit registers being written. + public short[] regs_write = new short[20]; + public byte regs_write_count; + // list of semantic groups this instruction belongs to. + public byte[] groups = new byte[8]; + public byte groups_count; + + public UnionArch arch; + + @Override + public List getFieldOrder() { + return Arrays.asList("regs_read", "regs_read_count", "regs_write", "regs_write_count", "groups", "groups_count", "arch"); + } + } + + public static class CsInsn { + private Pointer csh; + private CS cs; + private _cs_insn raw; + private int arch; + + // instruction ID. + public int id; + // instruction address. + public long address; + // instruction size. + public short size; + // Machine bytes of this instruction, with number of bytes indicated by size above + public byte[] bytes; + // instruction mnemonic. NOTE: irrelevant for diet engine. + public String mnemonic; + // instruction operands. NOTE: irrelevant for diet engine. + public String opStr; + // list of all implicit registers being read. + public short[] regsRead; + // list of all implicit registers being written. + public short[] regsWrite; + // list of semantic groups this instruction belongs to. + public byte[] groups; + public OpInfo operands; + + public CsInsn (_cs_insn insn, int _arch, Pointer _csh, CS _cs, boolean diet) { + id = insn.id; + address = insn.address; + size = insn.size; + + if (!diet) { + int lm = 0; + while (insn.mnemonic[lm++] != 0); + int lo = 0; + while (insn.op_str[lo++] != 0); + mnemonic = new String(insn.mnemonic, 0, lm-1); + opStr = new String(insn.op_str, 0, lo-1); + bytes = Arrays.copyOf(insn.bytes, insn.size); + } + + cs = _cs; + arch = _arch; + raw = insn; + csh = _csh; + + if (insn.cs_detail != null) { + if (!diet) { + regsRead = new short[insn.cs_detail.regs_read_count]; + for (int i=0; i 2017 */ + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.M680x_const.*; + +public class M680x { + + public static class OpIndexed extends Structure { + public int base_reg; + public int offset_reg; + public short offset; + public short offset_addr; + public byte offset_bits; + public byte inc_dec; + public byte flags; + + @Override + public List getFieldOrder() { + return Arrays.asList("base_reg", "offset_reg", "offset", "offset_addr", "offset_bits", "inc_dec", "flags"); + } + } + + public static class OpRelative extends Structure { + public short address; + public short offset; + + @Override + public List getFieldOrder() { + return Arrays.asList("address", "offset"); + } + } + + public static class OpExtended extends Structure { + public short address; + public byte indirect; + + @Override + public List getFieldOrder() { + return Arrays.asList("address", "indirect"); + } + } + + public static class OpValue extends Union { + public int imm; + public int reg; + public OpIndexed idx; + public OpRelative rel; + public OpExtended ext; + public byte direct_addr; + public byte const_val; + + @Override + public List getFieldOrder() { + return Arrays.asList("imm", "reg", "idx", "rel", "ext", "direct_addr", "const_val"); + } + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + public byte size; + public byte access; + + public void read() { + readField("type"); + if (type == M680X_OP_IMMEDIATE) + value.setType(Integer.TYPE); + if (type == M680X_OP_REGISTER) + value.setType(Integer.TYPE); + if (type == M680X_OP_INDEXED) + value.setType(OpIndexed.class); + if (type == M680X_OP_RELATIVE) + value.setType(OpRelative.class); + if (type == M680X_OP_EXTENDED) + value.setType(OpExtended.class); + if (type == M680X_OP_DIRECT) + value.setType(Integer.TYPE); + if (type == M680X_OP_INVALID) + return; + readField("value"); + readField("size"); + readField("access"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value", "size", "access"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public byte flags; + public byte op_count; + + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[9]; + } + + public void read() { + readField("flags"); + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("flags", "op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public byte flags; + public Operand [] op = null; + + public OpInfo(UnionOpInfo op_info) { + flags = op_info.flags; + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/M680x_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/M680x_const.java new file mode 100644 index 0000000..29eca28 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/M680x_const.java @@ -0,0 +1,419 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class M680x_const { + public static final int M680X_OPERAND_COUNT = 9; + + public static final int M680X_REG_INVALID = 0; + public static final int M680X_REG_A = 1; + public static final int M680X_REG_B = 2; + public static final int M680X_REG_E = 3; + public static final int M680X_REG_F = 4; + public static final int M680X_REG_0 = 5; + public static final int M680X_REG_D = 6; + public static final int M680X_REG_W = 7; + public static final int M680X_REG_CC = 8; + public static final int M680X_REG_DP = 9; + public static final int M680X_REG_MD = 10; + public static final int M680X_REG_HX = 11; + public static final int M680X_REG_H = 12; + public static final int M680X_REG_X = 13; + public static final int M680X_REG_Y = 14; + public static final int M680X_REG_S = 15; + public static final int M680X_REG_U = 16; + public static final int M680X_REG_V = 17; + public static final int M680X_REG_Q = 18; + public static final int M680X_REG_PC = 19; + public static final int M680X_REG_TMP2 = 20; + public static final int M680X_REG_TMP3 = 21; + public static final int M680X_REG_ENDING = 22; + + public static final int M680X_OP_INVALID = 0; + public static final int M680X_OP_REGISTER = 1; + public static final int M680X_OP_IMMEDIATE = 2; + public static final int M680X_OP_INDEXED = 3; + public static final int M680X_OP_EXTENDED = 4; + public static final int M680X_OP_DIRECT = 5; + public static final int M680X_OP_RELATIVE = 6; + public static final int M680X_OP_CONSTANT = 7; + + public static final int M680X_OFFSET_NONE = 0; + public static final int M680X_OFFSET_BITS_5 = 5; + public static final int M680X_OFFSET_BITS_8 = 8; + public static final int M680X_OFFSET_BITS_9 = 9; + public static final int M680X_OFFSET_BITS_16 = 16; + public static final int M680X_IDX_INDIRECT = 1; + public static final int M680X_IDX_NO_COMMA = 2; + public static final int M680X_IDX_POST_INC_DEC = 4; + + public static final int M680X_GRP_INVALID = 0; + public static final int M680X_GRP_JUMP = 1; + public static final int M680X_GRP_CALL = 2; + public static final int M680X_GRP_RET = 3; + public static final int M680X_GRP_INT = 4; + public static final int M680X_GRP_IRET = 5; + public static final int M680X_GRP_PRIV = 6; + public static final int M680X_GRP_BRAREL = 7; + public static final int M680X_GRP_ENDING = 8; + public static final int M680X_FIRST_OP_IN_MNEM = 1; + public static final int M680X_SECOND_OP_IN_MNEM = 2; + + public static final int M680X_INS_INVLD = 0; + public static final int M680X_INS_ABA = 1; + public static final int M680X_INS_ABX = 2; + public static final int M680X_INS_ABY = 3; + public static final int M680X_INS_ADC = 4; + public static final int M680X_INS_ADCA = 5; + public static final int M680X_INS_ADCB = 6; + public static final int M680X_INS_ADCD = 7; + public static final int M680X_INS_ADCR = 8; + public static final int M680X_INS_ADD = 9; + public static final int M680X_INS_ADDA = 10; + public static final int M680X_INS_ADDB = 11; + public static final int M680X_INS_ADDD = 12; + public static final int M680X_INS_ADDE = 13; + public static final int M680X_INS_ADDF = 14; + public static final int M680X_INS_ADDR = 15; + public static final int M680X_INS_ADDW = 16; + public static final int M680X_INS_AIM = 17; + public static final int M680X_INS_AIS = 18; + public static final int M680X_INS_AIX = 19; + public static final int M680X_INS_AND = 20; + public static final int M680X_INS_ANDA = 21; + public static final int M680X_INS_ANDB = 22; + public static final int M680X_INS_ANDCC = 23; + public static final int M680X_INS_ANDD = 24; + public static final int M680X_INS_ANDR = 25; + public static final int M680X_INS_ASL = 26; + public static final int M680X_INS_ASLA = 27; + public static final int M680X_INS_ASLB = 28; + public static final int M680X_INS_ASLD = 29; + public static final int M680X_INS_ASR = 30; + public static final int M680X_INS_ASRA = 31; + public static final int M680X_INS_ASRB = 32; + public static final int M680X_INS_ASRD = 33; + public static final int M680X_INS_ASRX = 34; + public static final int M680X_INS_BAND = 35; + public static final int M680X_INS_BCC = 36; + public static final int M680X_INS_BCLR = 37; + public static final int M680X_INS_BCS = 38; + public static final int M680X_INS_BEOR = 39; + public static final int M680X_INS_BEQ = 40; + public static final int M680X_INS_BGE = 41; + public static final int M680X_INS_BGND = 42; + public static final int M680X_INS_BGT = 43; + public static final int M680X_INS_BHCC = 44; + public static final int M680X_INS_BHCS = 45; + public static final int M680X_INS_BHI = 46; + public static final int M680X_INS_BIAND = 47; + public static final int M680X_INS_BIEOR = 48; + public static final int M680X_INS_BIH = 49; + public static final int M680X_INS_BIL = 50; + public static final int M680X_INS_BIOR = 51; + public static final int M680X_INS_BIT = 52; + public static final int M680X_INS_BITA = 53; + public static final int M680X_INS_BITB = 54; + public static final int M680X_INS_BITD = 55; + public static final int M680X_INS_BITMD = 56; + public static final int M680X_INS_BLE = 57; + public static final int M680X_INS_BLS = 58; + public static final int M680X_INS_BLT = 59; + public static final int M680X_INS_BMC = 60; + public static final int M680X_INS_BMI = 61; + public static final int M680X_INS_BMS = 62; + public static final int M680X_INS_BNE = 63; + public static final int M680X_INS_BOR = 64; + public static final int M680X_INS_BPL = 65; + public static final int M680X_INS_BRCLR = 66; + public static final int M680X_INS_BRSET = 67; + public static final int M680X_INS_BRA = 68; + public static final int M680X_INS_BRN = 69; + public static final int M680X_INS_BSET = 70; + public static final int M680X_INS_BSR = 71; + public static final int M680X_INS_BVC = 72; + public static final int M680X_INS_BVS = 73; + public static final int M680X_INS_CALL = 74; + public static final int M680X_INS_CBA = 75; + public static final int M680X_INS_CBEQ = 76; + public static final int M680X_INS_CBEQA = 77; + public static final int M680X_INS_CBEQX = 78; + public static final int M680X_INS_CLC = 79; + public static final int M680X_INS_CLI = 80; + public static final int M680X_INS_CLR = 81; + public static final int M680X_INS_CLRA = 82; + public static final int M680X_INS_CLRB = 83; + public static final int M680X_INS_CLRD = 84; + public static final int M680X_INS_CLRE = 85; + public static final int M680X_INS_CLRF = 86; + public static final int M680X_INS_CLRH = 87; + public static final int M680X_INS_CLRW = 88; + public static final int M680X_INS_CLRX = 89; + public static final int M680X_INS_CLV = 90; + public static final int M680X_INS_CMP = 91; + public static final int M680X_INS_CMPA = 92; + public static final int M680X_INS_CMPB = 93; + public static final int M680X_INS_CMPD = 94; + public static final int M680X_INS_CMPE = 95; + public static final int M680X_INS_CMPF = 96; + public static final int M680X_INS_CMPR = 97; + public static final int M680X_INS_CMPS = 98; + public static final int M680X_INS_CMPU = 99; + public static final int M680X_INS_CMPW = 100; + public static final int M680X_INS_CMPX = 101; + public static final int M680X_INS_CMPY = 102; + public static final int M680X_INS_COM = 103; + public static final int M680X_INS_COMA = 104; + public static final int M680X_INS_COMB = 105; + public static final int M680X_INS_COMD = 106; + public static final int M680X_INS_COME = 107; + public static final int M680X_INS_COMF = 108; + public static final int M680X_INS_COMW = 109; + public static final int M680X_INS_COMX = 110; + public static final int M680X_INS_CPD = 111; + public static final int M680X_INS_CPHX = 112; + public static final int M680X_INS_CPS = 113; + public static final int M680X_INS_CPX = 114; + public static final int M680X_INS_CPY = 115; + public static final int M680X_INS_CWAI = 116; + public static final int M680X_INS_DAA = 117; + public static final int M680X_INS_DBEQ = 118; + public static final int M680X_INS_DBNE = 119; + public static final int M680X_INS_DBNZ = 120; + public static final int M680X_INS_DBNZA = 121; + public static final int M680X_INS_DBNZX = 122; + public static final int M680X_INS_DEC = 123; + public static final int M680X_INS_DECA = 124; + public static final int M680X_INS_DECB = 125; + public static final int M680X_INS_DECD = 126; + public static final int M680X_INS_DECE = 127; + public static final int M680X_INS_DECF = 128; + public static final int M680X_INS_DECW = 129; + public static final int M680X_INS_DECX = 130; + public static final int M680X_INS_DES = 131; + public static final int M680X_INS_DEX = 132; + public static final int M680X_INS_DEY = 133; + public static final int M680X_INS_DIV = 134; + public static final int M680X_INS_DIVD = 135; + public static final int M680X_INS_DIVQ = 136; + public static final int M680X_INS_EDIV = 137; + public static final int M680X_INS_EDIVS = 138; + public static final int M680X_INS_EIM = 139; + public static final int M680X_INS_EMACS = 140; + public static final int M680X_INS_EMAXD = 141; + public static final int M680X_INS_EMAXM = 142; + public static final int M680X_INS_EMIND = 143; + public static final int M680X_INS_EMINM = 144; + public static final int M680X_INS_EMUL = 145; + public static final int M680X_INS_EMULS = 146; + public static final int M680X_INS_EOR = 147; + public static final int M680X_INS_EORA = 148; + public static final int M680X_INS_EORB = 149; + public static final int M680X_INS_EORD = 150; + public static final int M680X_INS_EORR = 151; + public static final int M680X_INS_ETBL = 152; + public static final int M680X_INS_EXG = 153; + public static final int M680X_INS_FDIV = 154; + public static final int M680X_INS_IBEQ = 155; + public static final int M680X_INS_IBNE = 156; + public static final int M680X_INS_IDIV = 157; + public static final int M680X_INS_IDIVS = 158; + public static final int M680X_INS_ILLGL = 159; + public static final int M680X_INS_INC = 160; + public static final int M680X_INS_INCA = 161; + public static final int M680X_INS_INCB = 162; + public static final int M680X_INS_INCD = 163; + public static final int M680X_INS_INCE = 164; + public static final int M680X_INS_INCF = 165; + public static final int M680X_INS_INCW = 166; + public static final int M680X_INS_INCX = 167; + public static final int M680X_INS_INS = 168; + public static final int M680X_INS_INX = 169; + public static final int M680X_INS_INY = 170; + public static final int M680X_INS_JMP = 171; + public static final int M680X_INS_JSR = 172; + public static final int M680X_INS_LBCC = 173; + public static final int M680X_INS_LBCS = 174; + public static final int M680X_INS_LBEQ = 175; + public static final int M680X_INS_LBGE = 176; + public static final int M680X_INS_LBGT = 177; + public static final int M680X_INS_LBHI = 178; + public static final int M680X_INS_LBLE = 179; + public static final int M680X_INS_LBLS = 180; + public static final int M680X_INS_LBLT = 181; + public static final int M680X_INS_LBMI = 182; + public static final int M680X_INS_LBNE = 183; + public static final int M680X_INS_LBPL = 184; + public static final int M680X_INS_LBRA = 185; + public static final int M680X_INS_LBRN = 186; + public static final int M680X_INS_LBSR = 187; + public static final int M680X_INS_LBVC = 188; + public static final int M680X_INS_LBVS = 189; + public static final int M680X_INS_LDA = 190; + public static final int M680X_INS_LDAA = 191; + public static final int M680X_INS_LDAB = 192; + public static final int M680X_INS_LDB = 193; + public static final int M680X_INS_LDBT = 194; + public static final int M680X_INS_LDD = 195; + public static final int M680X_INS_LDE = 196; + public static final int M680X_INS_LDF = 197; + public static final int M680X_INS_LDHX = 198; + public static final int M680X_INS_LDMD = 199; + public static final int M680X_INS_LDQ = 200; + public static final int M680X_INS_LDS = 201; + public static final int M680X_INS_LDU = 202; + public static final int M680X_INS_LDW = 203; + public static final int M680X_INS_LDX = 204; + public static final int M680X_INS_LDY = 205; + public static final int M680X_INS_LEAS = 206; + public static final int M680X_INS_LEAU = 207; + public static final int M680X_INS_LEAX = 208; + public static final int M680X_INS_LEAY = 209; + public static final int M680X_INS_LSL = 210; + public static final int M680X_INS_LSLA = 211; + public static final int M680X_INS_LSLB = 212; + public static final int M680X_INS_LSLD = 213; + public static final int M680X_INS_LSLX = 214; + public static final int M680X_INS_LSR = 215; + public static final int M680X_INS_LSRA = 216; + public static final int M680X_INS_LSRB = 217; + public static final int M680X_INS_LSRD = 218; + public static final int M680X_INS_LSRW = 219; + public static final int M680X_INS_LSRX = 220; + public static final int M680X_INS_MAXA = 221; + public static final int M680X_INS_MAXM = 222; + public static final int M680X_INS_MEM = 223; + public static final int M680X_INS_MINA = 224; + public static final int M680X_INS_MINM = 225; + public static final int M680X_INS_MOV = 226; + public static final int M680X_INS_MOVB = 227; + public static final int M680X_INS_MOVW = 228; + public static final int M680X_INS_MUL = 229; + public static final int M680X_INS_MULD = 230; + public static final int M680X_INS_NEG = 231; + public static final int M680X_INS_NEGA = 232; + public static final int M680X_INS_NEGB = 233; + public static final int M680X_INS_NEGD = 234; + public static final int M680X_INS_NEGX = 235; + public static final int M680X_INS_NOP = 236; + public static final int M680X_INS_NSA = 237; + public static final int M680X_INS_OIM = 238; + public static final int M680X_INS_ORA = 239; + public static final int M680X_INS_ORAA = 240; + public static final int M680X_INS_ORAB = 241; + public static final int M680X_INS_ORB = 242; + public static final int M680X_INS_ORCC = 243; + public static final int M680X_INS_ORD = 244; + public static final int M680X_INS_ORR = 245; + public static final int M680X_INS_PSHA = 246; + public static final int M680X_INS_PSHB = 247; + public static final int M680X_INS_PSHC = 248; + public static final int M680X_INS_PSHD = 249; + public static final int M680X_INS_PSHH = 250; + public static final int M680X_INS_PSHS = 251; + public static final int M680X_INS_PSHSW = 252; + public static final int M680X_INS_PSHU = 253; + public static final int M680X_INS_PSHUW = 254; + public static final int M680X_INS_PSHX = 255; + public static final int M680X_INS_PSHY = 256; + public static final int M680X_INS_PULA = 257; + public static final int M680X_INS_PULB = 258; + public static final int M680X_INS_PULC = 259; + public static final int M680X_INS_PULD = 260; + public static final int M680X_INS_PULH = 261; + public static final int M680X_INS_PULS = 262; + public static final int M680X_INS_PULSW = 263; + public static final int M680X_INS_PULU = 264; + public static final int M680X_INS_PULUW = 265; + public static final int M680X_INS_PULX = 266; + public static final int M680X_INS_PULY = 267; + public static final int M680X_INS_REV = 268; + public static final int M680X_INS_REVW = 269; + public static final int M680X_INS_ROL = 270; + public static final int M680X_INS_ROLA = 271; + public static final int M680X_INS_ROLB = 272; + public static final int M680X_INS_ROLD = 273; + public static final int M680X_INS_ROLW = 274; + public static final int M680X_INS_ROLX = 275; + public static final int M680X_INS_ROR = 276; + public static final int M680X_INS_RORA = 277; + public static final int M680X_INS_RORB = 278; + public static final int M680X_INS_RORD = 279; + public static final int M680X_INS_RORW = 280; + public static final int M680X_INS_RORX = 281; + public static final int M680X_INS_RSP = 282; + public static final int M680X_INS_RTC = 283; + public static final int M680X_INS_RTI = 284; + public static final int M680X_INS_RTS = 285; + public static final int M680X_INS_SBA = 286; + public static final int M680X_INS_SBC = 287; + public static final int M680X_INS_SBCA = 288; + public static final int M680X_INS_SBCB = 289; + public static final int M680X_INS_SBCD = 290; + public static final int M680X_INS_SBCR = 291; + public static final int M680X_INS_SEC = 292; + public static final int M680X_INS_SEI = 293; + public static final int M680X_INS_SEV = 294; + public static final int M680X_INS_SEX = 295; + public static final int M680X_INS_SEXW = 296; + public static final int M680X_INS_SLP = 297; + public static final int M680X_INS_STA = 298; + public static final int M680X_INS_STAA = 299; + public static final int M680X_INS_STAB = 300; + public static final int M680X_INS_STB = 301; + public static final int M680X_INS_STBT = 302; + public static final int M680X_INS_STD = 303; + public static final int M680X_INS_STE = 304; + public static final int M680X_INS_STF = 305; + public static final int M680X_INS_STOP = 306; + public static final int M680X_INS_STHX = 307; + public static final int M680X_INS_STQ = 308; + public static final int M680X_INS_STS = 309; + public static final int M680X_INS_STU = 310; + public static final int M680X_INS_STW = 311; + public static final int M680X_INS_STX = 312; + public static final int M680X_INS_STY = 313; + public static final int M680X_INS_SUB = 314; + public static final int M680X_INS_SUBA = 315; + public static final int M680X_INS_SUBB = 316; + public static final int M680X_INS_SUBD = 317; + public static final int M680X_INS_SUBE = 318; + public static final int M680X_INS_SUBF = 319; + public static final int M680X_INS_SUBR = 320; + public static final int M680X_INS_SUBW = 321; + public static final int M680X_INS_SWI = 322; + public static final int M680X_INS_SWI2 = 323; + public static final int M680X_INS_SWI3 = 324; + public static final int M680X_INS_SYNC = 325; + public static final int M680X_INS_TAB = 326; + public static final int M680X_INS_TAP = 327; + public static final int M680X_INS_TAX = 328; + public static final int M680X_INS_TBA = 329; + public static final int M680X_INS_TBEQ = 330; + public static final int M680X_INS_TBL = 331; + public static final int M680X_INS_TBNE = 332; + public static final int M680X_INS_TEST = 333; + public static final int M680X_INS_TFM = 334; + public static final int M680X_INS_TFR = 335; + public static final int M680X_INS_TIM = 336; + public static final int M680X_INS_TPA = 337; + public static final int M680X_INS_TST = 338; + public static final int M680X_INS_TSTA = 339; + public static final int M680X_INS_TSTB = 340; + public static final int M680X_INS_TSTD = 341; + public static final int M680X_INS_TSTE = 342; + public static final int M680X_INS_TSTF = 343; + public static final int M680X_INS_TSTW = 344; + public static final int M680X_INS_TSTX = 345; + public static final int M680X_INS_TSX = 346; + public static final int M680X_INS_TSY = 347; + public static final int M680X_INS_TXA = 348; + public static final int M680X_INS_TXS = 349; + public static final int M680X_INS_TYS = 350; + public static final int M680X_INS_WAI = 351; + public static final int M680X_INS_WAIT = 352; + public static final int M680X_INS_WAV = 353; + public static final int M680X_INS_WAVR = 354; + public static final int M680X_INS_XGDX = 355; + public static final int M680X_INS_XGDY = 356; + public static final int M680X_INS_ENDING = 357; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/M68k_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/M68k_const.java new file mode 100644 index 0000000..74cd8f9 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/M68k_const.java @@ -0,0 +1,489 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class M68k_const { + public static final int M68K_OPERAND_COUNT = 4; + + public static final int M68K_REG_INVALID = 0; + public static final int M68K_REG_D0 = 1; + public static final int M68K_REG_D1 = 2; + public static final int M68K_REG_D2 = 3; + public static final int M68K_REG_D3 = 4; + public static final int M68K_REG_D4 = 5; + public static final int M68K_REG_D5 = 6; + public static final int M68K_REG_D6 = 7; + public static final int M68K_REG_D7 = 8; + public static final int M68K_REG_A0 = 9; + public static final int M68K_REG_A1 = 10; + public static final int M68K_REG_A2 = 11; + public static final int M68K_REG_A3 = 12; + public static final int M68K_REG_A4 = 13; + public static final int M68K_REG_A5 = 14; + public static final int M68K_REG_A6 = 15; + public static final int M68K_REG_A7 = 16; + public static final int M68K_REG_FP0 = 17; + public static final int M68K_REG_FP1 = 18; + public static final int M68K_REG_FP2 = 19; + public static final int M68K_REG_FP3 = 20; + public static final int M68K_REG_FP4 = 21; + public static final int M68K_REG_FP5 = 22; + public static final int M68K_REG_FP6 = 23; + public static final int M68K_REG_FP7 = 24; + public static final int M68K_REG_PC = 25; + public static final int M68K_REG_SR = 26; + public static final int M68K_REG_CCR = 27; + public static final int M68K_REG_SFC = 28; + public static final int M68K_REG_DFC = 29; + public static final int M68K_REG_USP = 30; + public static final int M68K_REG_VBR = 31; + public static final int M68K_REG_CACR = 32; + public static final int M68K_REG_CAAR = 33; + public static final int M68K_REG_MSP = 34; + public static final int M68K_REG_ISP = 35; + public static final int M68K_REG_TC = 36; + public static final int M68K_REG_ITT0 = 37; + public static final int M68K_REG_ITT1 = 38; + public static final int M68K_REG_DTT0 = 39; + public static final int M68K_REG_DTT1 = 40; + public static final int M68K_REG_MMUSR = 41; + public static final int M68K_REG_URP = 42; + public static final int M68K_REG_SRP = 43; + public static final int M68K_REG_FPCR = 44; + public static final int M68K_REG_FPSR = 45; + public static final int M68K_REG_FPIAR = 46; + public static final int M68K_REG_ENDING = 47; + + public static final int M68K_AM_NONE = 0; + public static final int M68K_AM_REG_DIRECT_DATA = 1; + public static final int M68K_AM_REG_DIRECT_ADDR = 2; + public static final int M68K_AM_REGI_ADDR = 3; + public static final int M68K_AM_REGI_ADDR_POST_INC = 4; + public static final int M68K_AM_REGI_ADDR_PRE_DEC = 5; + public static final int M68K_AM_REGI_ADDR_DISP = 6; + public static final int M68K_AM_AREGI_INDEX_8_BIT_DISP = 7; + public static final int M68K_AM_AREGI_INDEX_BASE_DISP = 8; + public static final int M68K_AM_MEMI_POST_INDEX = 9; + public static final int M68K_AM_MEMI_PRE_INDEX = 10; + public static final int M68K_AM_PCI_DISP = 11; + public static final int M68K_AM_PCI_INDEX_8_BIT_DISP = 12; + public static final int M68K_AM_PCI_INDEX_BASE_DISP = 13; + public static final int M68K_AM_PC_MEMI_POST_INDEX = 14; + public static final int M68K_AM_PC_MEMI_PRE_INDEX = 15; + public static final int M68K_AM_ABSOLUTE_DATA_SHORT = 16; + public static final int M68K_AM_ABSOLUTE_DATA_LONG = 17; + public static final int M68K_AM_IMMEDIATE = 18; + public static final int M68K_AM_BRANCH_DISPLACEMENT = 19; + + public static final int M68K_OP_INVALID = 0; + public static final int M68K_OP_REG = 1; + public static final int M68K_OP_IMM = 2; + public static final int M68K_OP_MEM = 3; + public static final int M68K_OP_FP_SINGLE = 4; + public static final int M68K_OP_FP_DOUBLE = 5; + public static final int M68K_OP_REG_BITS = 6; + public static final int M68K_OP_REG_PAIR = 7; + public static final int M68K_OP_BR_DISP = 8; + + public static final int M68K_OP_BR_DISP_SIZE_INVALID = 0; + public static final int M68K_OP_BR_DISP_SIZE_BYTE = 1; + public static final int M68K_OP_BR_DISP_SIZE_WORD = 2; + public static final int M68K_OP_BR_DISP_SIZE_LONG = 4; + + public static final int M68K_CPU_SIZE_NONE = 0; + public static final int M68K_CPU_SIZE_BYTE = 1; + public static final int M68K_CPU_SIZE_WORD = 2; + public static final int M68K_CPU_SIZE_LONG = 4; + + public static final int M68K_FPU_SIZE_NONE = 0; + public static final int M68K_FPU_SIZE_SINGLE = 4; + public static final int M68K_FPU_SIZE_DOUBLE = 8; + public static final int M68K_FPU_SIZE_EXTENDED = 12; + + public static final int M68K_SIZE_TYPE_INVALID = 0; + public static final int M68K_SIZE_TYPE_CPU = 1; + public static final int M68K_SIZE_TYPE_FPU = 2; + + public static final int M68K_INS_INVALID = 0; + public static final int M68K_INS_ABCD = 1; + public static final int M68K_INS_ADD = 2; + public static final int M68K_INS_ADDA = 3; + public static final int M68K_INS_ADDI = 4; + public static final int M68K_INS_ADDQ = 5; + public static final int M68K_INS_ADDX = 6; + public static final int M68K_INS_AND = 7; + public static final int M68K_INS_ANDI = 8; + public static final int M68K_INS_ASL = 9; + public static final int M68K_INS_ASR = 10; + public static final int M68K_INS_BHS = 11; + public static final int M68K_INS_BLO = 12; + public static final int M68K_INS_BHI = 13; + public static final int M68K_INS_BLS = 14; + public static final int M68K_INS_BCC = 15; + public static final int M68K_INS_BCS = 16; + public static final int M68K_INS_BNE = 17; + public static final int M68K_INS_BEQ = 18; + public static final int M68K_INS_BVC = 19; + public static final int M68K_INS_BVS = 20; + public static final int M68K_INS_BPL = 21; + public static final int M68K_INS_BMI = 22; + public static final int M68K_INS_BGE = 23; + public static final int M68K_INS_BLT = 24; + public static final int M68K_INS_BGT = 25; + public static final int M68K_INS_BLE = 26; + public static final int M68K_INS_BRA = 27; + public static final int M68K_INS_BSR = 28; + public static final int M68K_INS_BCHG = 29; + public static final int M68K_INS_BCLR = 30; + public static final int M68K_INS_BSET = 31; + public static final int M68K_INS_BTST = 32; + public static final int M68K_INS_BFCHG = 33; + public static final int M68K_INS_BFCLR = 34; + public static final int M68K_INS_BFEXTS = 35; + public static final int M68K_INS_BFEXTU = 36; + public static final int M68K_INS_BFFFO = 37; + public static final int M68K_INS_BFINS = 38; + public static final int M68K_INS_BFSET = 39; + public static final int M68K_INS_BFTST = 40; + public static final int M68K_INS_BKPT = 41; + public static final int M68K_INS_CALLM = 42; + public static final int M68K_INS_CAS = 43; + public static final int M68K_INS_CAS2 = 44; + public static final int M68K_INS_CHK = 45; + public static final int M68K_INS_CHK2 = 46; + public static final int M68K_INS_CLR = 47; + public static final int M68K_INS_CMP = 48; + public static final int M68K_INS_CMPA = 49; + public static final int M68K_INS_CMPI = 50; + public static final int M68K_INS_CMPM = 51; + public static final int M68K_INS_CMP2 = 52; + public static final int M68K_INS_CINVL = 53; + public static final int M68K_INS_CINVP = 54; + public static final int M68K_INS_CINVA = 55; + public static final int M68K_INS_CPUSHL = 56; + public static final int M68K_INS_CPUSHP = 57; + public static final int M68K_INS_CPUSHA = 58; + public static final int M68K_INS_DBT = 59; + public static final int M68K_INS_DBF = 60; + public static final int M68K_INS_DBHI = 61; + public static final int M68K_INS_DBLS = 62; + public static final int M68K_INS_DBCC = 63; + public static final int M68K_INS_DBCS = 64; + public static final int M68K_INS_DBNE = 65; + public static final int M68K_INS_DBEQ = 66; + public static final int M68K_INS_DBVC = 67; + public static final int M68K_INS_DBVS = 68; + public static final int M68K_INS_DBPL = 69; + public static final int M68K_INS_DBMI = 70; + public static final int M68K_INS_DBGE = 71; + public static final int M68K_INS_DBLT = 72; + public static final int M68K_INS_DBGT = 73; + public static final int M68K_INS_DBLE = 74; + public static final int M68K_INS_DBRA = 75; + public static final int M68K_INS_DIVS = 76; + public static final int M68K_INS_DIVSL = 77; + public static final int M68K_INS_DIVU = 78; + public static final int M68K_INS_DIVUL = 79; + public static final int M68K_INS_EOR = 80; + public static final int M68K_INS_EORI = 81; + public static final int M68K_INS_EXG = 82; + public static final int M68K_INS_EXT = 83; + public static final int M68K_INS_EXTB = 84; + public static final int M68K_INS_FABS = 85; + public static final int M68K_INS_FSABS = 86; + public static final int M68K_INS_FDABS = 87; + public static final int M68K_INS_FACOS = 88; + public static final int M68K_INS_FADD = 89; + public static final int M68K_INS_FSADD = 90; + public static final int M68K_INS_FDADD = 91; + public static final int M68K_INS_FASIN = 92; + public static final int M68K_INS_FATAN = 93; + public static final int M68K_INS_FATANH = 94; + public static final int M68K_INS_FBF = 95; + public static final int M68K_INS_FBEQ = 96; + public static final int M68K_INS_FBOGT = 97; + public static final int M68K_INS_FBOGE = 98; + public static final int M68K_INS_FBOLT = 99; + public static final int M68K_INS_FBOLE = 100; + public static final int M68K_INS_FBOGL = 101; + public static final int M68K_INS_FBOR = 102; + public static final int M68K_INS_FBUN = 103; + public static final int M68K_INS_FBUEQ = 104; + public static final int M68K_INS_FBUGT = 105; + public static final int M68K_INS_FBUGE = 106; + public static final int M68K_INS_FBULT = 107; + public static final int M68K_INS_FBULE = 108; + public static final int M68K_INS_FBNE = 109; + public static final int M68K_INS_FBT = 110; + public static final int M68K_INS_FBSF = 111; + public static final int M68K_INS_FBSEQ = 112; + public static final int M68K_INS_FBGT = 113; + public static final int M68K_INS_FBGE = 114; + public static final int M68K_INS_FBLT = 115; + public static final int M68K_INS_FBLE = 116; + public static final int M68K_INS_FBGL = 117; + public static final int M68K_INS_FBGLE = 118; + public static final int M68K_INS_FBNGLE = 119; + public static final int M68K_INS_FBNGL = 120; + public static final int M68K_INS_FBNLE = 121; + public static final int M68K_INS_FBNLT = 122; + public static final int M68K_INS_FBNGE = 123; + public static final int M68K_INS_FBNGT = 124; + public static final int M68K_INS_FBSNE = 125; + public static final int M68K_INS_FBST = 126; + public static final int M68K_INS_FCMP = 127; + public static final int M68K_INS_FCOS = 128; + public static final int M68K_INS_FCOSH = 129; + public static final int M68K_INS_FDBF = 130; + public static final int M68K_INS_FDBEQ = 131; + public static final int M68K_INS_FDBOGT = 132; + public static final int M68K_INS_FDBOGE = 133; + public static final int M68K_INS_FDBOLT = 134; + public static final int M68K_INS_FDBOLE = 135; + public static final int M68K_INS_FDBOGL = 136; + public static final int M68K_INS_FDBOR = 137; + public static final int M68K_INS_FDBUN = 138; + public static final int M68K_INS_FDBUEQ = 139; + public static final int M68K_INS_FDBUGT = 140; + public static final int M68K_INS_FDBUGE = 141; + public static final int M68K_INS_FDBULT = 142; + public static final int M68K_INS_FDBULE = 143; + public static final int M68K_INS_FDBNE = 144; + public static final int M68K_INS_FDBT = 145; + public static final int M68K_INS_FDBSF = 146; + public static final int M68K_INS_FDBSEQ = 147; + public static final int M68K_INS_FDBGT = 148; + public static final int M68K_INS_FDBGE = 149; + public static final int M68K_INS_FDBLT = 150; + public static final int M68K_INS_FDBLE = 151; + public static final int M68K_INS_FDBGL = 152; + public static final int M68K_INS_FDBGLE = 153; + public static final int M68K_INS_FDBNGLE = 154; + public static final int M68K_INS_FDBNGL = 155; + public static final int M68K_INS_FDBNLE = 156; + public static final int M68K_INS_FDBNLT = 157; + public static final int M68K_INS_FDBNGE = 158; + public static final int M68K_INS_FDBNGT = 159; + public static final int M68K_INS_FDBSNE = 160; + public static final int M68K_INS_FDBST = 161; + public static final int M68K_INS_FDIV = 162; + public static final int M68K_INS_FSDIV = 163; + public static final int M68K_INS_FDDIV = 164; + public static final int M68K_INS_FETOX = 165; + public static final int M68K_INS_FETOXM1 = 166; + public static final int M68K_INS_FGETEXP = 167; + public static final int M68K_INS_FGETMAN = 168; + public static final int M68K_INS_FINT = 169; + public static final int M68K_INS_FINTRZ = 170; + public static final int M68K_INS_FLOG10 = 171; + public static final int M68K_INS_FLOG2 = 172; + public static final int M68K_INS_FLOGN = 173; + public static final int M68K_INS_FLOGNP1 = 174; + public static final int M68K_INS_FMOD = 175; + public static final int M68K_INS_FMOVE = 176; + public static final int M68K_INS_FSMOVE = 177; + public static final int M68K_INS_FDMOVE = 178; + public static final int M68K_INS_FMOVECR = 179; + public static final int M68K_INS_FMOVEM = 180; + public static final int M68K_INS_FMUL = 181; + public static final int M68K_INS_FSMUL = 182; + public static final int M68K_INS_FDMUL = 183; + public static final int M68K_INS_FNEG = 184; + public static final int M68K_INS_FSNEG = 185; + public static final int M68K_INS_FDNEG = 186; + public static final int M68K_INS_FNOP = 187; + public static final int M68K_INS_FREM = 188; + public static final int M68K_INS_FRESTORE = 189; + public static final int M68K_INS_FSAVE = 190; + public static final int M68K_INS_FSCALE = 191; + public static final int M68K_INS_FSGLDIV = 192; + public static final int M68K_INS_FSGLMUL = 193; + public static final int M68K_INS_FSIN = 194; + public static final int M68K_INS_FSINCOS = 195; + public static final int M68K_INS_FSINH = 196; + public static final int M68K_INS_FSQRT = 197; + public static final int M68K_INS_FSSQRT = 198; + public static final int M68K_INS_FDSQRT = 199; + public static final int M68K_INS_FSF = 200; + public static final int M68K_INS_FSBEQ = 201; + public static final int M68K_INS_FSOGT = 202; + public static final int M68K_INS_FSOGE = 203; + public static final int M68K_INS_FSOLT = 204; + public static final int M68K_INS_FSOLE = 205; + public static final int M68K_INS_FSOGL = 206; + public static final int M68K_INS_FSOR = 207; + public static final int M68K_INS_FSUN = 208; + public static final int M68K_INS_FSUEQ = 209; + public static final int M68K_INS_FSUGT = 210; + public static final int M68K_INS_FSUGE = 211; + public static final int M68K_INS_FSULT = 212; + public static final int M68K_INS_FSULE = 213; + public static final int M68K_INS_FSNE = 214; + public static final int M68K_INS_FST = 215; + public static final int M68K_INS_FSSF = 216; + public static final int M68K_INS_FSSEQ = 217; + public static final int M68K_INS_FSGT = 218; + public static final int M68K_INS_FSGE = 219; + public static final int M68K_INS_FSLT = 220; + public static final int M68K_INS_FSLE = 221; + public static final int M68K_INS_FSGL = 222; + public static final int M68K_INS_FSGLE = 223; + public static final int M68K_INS_FSNGLE = 224; + public static final int M68K_INS_FSNGL = 225; + public static final int M68K_INS_FSNLE = 226; + public static final int M68K_INS_FSNLT = 227; + public static final int M68K_INS_FSNGE = 228; + public static final int M68K_INS_FSNGT = 229; + public static final int M68K_INS_FSSNE = 230; + public static final int M68K_INS_FSST = 231; + public static final int M68K_INS_FSUB = 232; + public static final int M68K_INS_FSSUB = 233; + public static final int M68K_INS_FDSUB = 234; + public static final int M68K_INS_FTAN = 235; + public static final int M68K_INS_FTANH = 236; + public static final int M68K_INS_FTENTOX = 237; + public static final int M68K_INS_FTRAPF = 238; + public static final int M68K_INS_FTRAPEQ = 239; + public static final int M68K_INS_FTRAPOGT = 240; + public static final int M68K_INS_FTRAPOGE = 241; + public static final int M68K_INS_FTRAPOLT = 242; + public static final int M68K_INS_FTRAPOLE = 243; + public static final int M68K_INS_FTRAPOGL = 244; + public static final int M68K_INS_FTRAPOR = 245; + public static final int M68K_INS_FTRAPUN = 246; + public static final int M68K_INS_FTRAPUEQ = 247; + public static final int M68K_INS_FTRAPUGT = 248; + public static final int M68K_INS_FTRAPUGE = 249; + public static final int M68K_INS_FTRAPULT = 250; + public static final int M68K_INS_FTRAPULE = 251; + public static final int M68K_INS_FTRAPNE = 252; + public static final int M68K_INS_FTRAPT = 253; + public static final int M68K_INS_FTRAPSF = 254; + public static final int M68K_INS_FTRAPSEQ = 255; + public static final int M68K_INS_FTRAPGT = 256; + public static final int M68K_INS_FTRAPGE = 257; + public static final int M68K_INS_FTRAPLT = 258; + public static final int M68K_INS_FTRAPLE = 259; + public static final int M68K_INS_FTRAPGL = 260; + public static final int M68K_INS_FTRAPGLE = 261; + public static final int M68K_INS_FTRAPNGLE = 262; + public static final int M68K_INS_FTRAPNGL = 263; + public static final int M68K_INS_FTRAPNLE = 264; + public static final int M68K_INS_FTRAPNLT = 265; + public static final int M68K_INS_FTRAPNGE = 266; + public static final int M68K_INS_FTRAPNGT = 267; + public static final int M68K_INS_FTRAPSNE = 268; + public static final int M68K_INS_FTRAPST = 269; + public static final int M68K_INS_FTST = 270; + public static final int M68K_INS_FTWOTOX = 271; + public static final int M68K_INS_HALT = 272; + public static final int M68K_INS_ILLEGAL = 273; + public static final int M68K_INS_JMP = 274; + public static final int M68K_INS_JSR = 275; + public static final int M68K_INS_LEA = 276; + public static final int M68K_INS_LINK = 277; + public static final int M68K_INS_LPSTOP = 278; + public static final int M68K_INS_LSL = 279; + public static final int M68K_INS_LSR = 280; + public static final int M68K_INS_MOVE = 281; + public static final int M68K_INS_MOVEA = 282; + public static final int M68K_INS_MOVEC = 283; + public static final int M68K_INS_MOVEM = 284; + public static final int M68K_INS_MOVEP = 285; + public static final int M68K_INS_MOVEQ = 286; + public static final int M68K_INS_MOVES = 287; + public static final int M68K_INS_MOVE16 = 288; + public static final int M68K_INS_MULS = 289; + public static final int M68K_INS_MULU = 290; + public static final int M68K_INS_NBCD = 291; + public static final int M68K_INS_NEG = 292; + public static final int M68K_INS_NEGX = 293; + public static final int M68K_INS_NOP = 294; + public static final int M68K_INS_NOT = 295; + public static final int M68K_INS_OR = 296; + public static final int M68K_INS_ORI = 297; + public static final int M68K_INS_PACK = 298; + public static final int M68K_INS_PEA = 299; + public static final int M68K_INS_PFLUSH = 300; + public static final int M68K_INS_PFLUSHA = 301; + public static final int M68K_INS_PFLUSHAN = 302; + public static final int M68K_INS_PFLUSHN = 303; + public static final int M68K_INS_PLOADR = 304; + public static final int M68K_INS_PLOADW = 305; + public static final int M68K_INS_PLPAR = 306; + public static final int M68K_INS_PLPAW = 307; + public static final int M68K_INS_PMOVE = 308; + public static final int M68K_INS_PMOVEFD = 309; + public static final int M68K_INS_PTESTR = 310; + public static final int M68K_INS_PTESTW = 311; + public static final int M68K_INS_PULSE = 312; + public static final int M68K_INS_REMS = 313; + public static final int M68K_INS_REMU = 314; + public static final int M68K_INS_RESET = 315; + public static final int M68K_INS_ROL = 316; + public static final int M68K_INS_ROR = 317; + public static final int M68K_INS_ROXL = 318; + public static final int M68K_INS_ROXR = 319; + public static final int M68K_INS_RTD = 320; + public static final int M68K_INS_RTE = 321; + public static final int M68K_INS_RTM = 322; + public static final int M68K_INS_RTR = 323; + public static final int M68K_INS_RTS = 324; + public static final int M68K_INS_SBCD = 325; + public static final int M68K_INS_ST = 326; + public static final int M68K_INS_SF = 327; + public static final int M68K_INS_SHI = 328; + public static final int M68K_INS_SLS = 329; + public static final int M68K_INS_SCC = 330; + public static final int M68K_INS_SHS = 331; + public static final int M68K_INS_SCS = 332; + public static final int M68K_INS_SLO = 333; + public static final int M68K_INS_SNE = 334; + public static final int M68K_INS_SEQ = 335; + public static final int M68K_INS_SVC = 336; + public static final int M68K_INS_SVS = 337; + public static final int M68K_INS_SPL = 338; + public static final int M68K_INS_SMI = 339; + public static final int M68K_INS_SGE = 340; + public static final int M68K_INS_SLT = 341; + public static final int M68K_INS_SGT = 342; + public static final int M68K_INS_SLE = 343; + public static final int M68K_INS_STOP = 344; + public static final int M68K_INS_SUB = 345; + public static final int M68K_INS_SUBA = 346; + public static final int M68K_INS_SUBI = 347; + public static final int M68K_INS_SUBQ = 348; + public static final int M68K_INS_SUBX = 349; + public static final int M68K_INS_SWAP = 350; + public static final int M68K_INS_TAS = 351; + public static final int M68K_INS_TRAP = 352; + public static final int M68K_INS_TRAPV = 353; + public static final int M68K_INS_TRAPT = 354; + public static final int M68K_INS_TRAPF = 355; + public static final int M68K_INS_TRAPHI = 356; + public static final int M68K_INS_TRAPLS = 357; + public static final int M68K_INS_TRAPCC = 358; + public static final int M68K_INS_TRAPHS = 359; + public static final int M68K_INS_TRAPCS = 360; + public static final int M68K_INS_TRAPLO = 361; + public static final int M68K_INS_TRAPNE = 362; + public static final int M68K_INS_TRAPEQ = 363; + public static final int M68K_INS_TRAPVC = 364; + public static final int M68K_INS_TRAPVS = 365; + public static final int M68K_INS_TRAPPL = 366; + public static final int M68K_INS_TRAPMI = 367; + public static final int M68K_INS_TRAPGE = 368; + public static final int M68K_INS_TRAPLT = 369; + public static final int M68K_INS_TRAPGT = 370; + public static final int M68K_INS_TRAPLE = 371; + public static final int M68K_INS_TST = 372; + public static final int M68K_INS_UNLK = 373; + public static final int M68K_INS_UNPK = 374; + public static final int M68K_INS_ENDING = 375; + + public static final int M68K_GRP_INVALID = 0; + public static final int M68K_GRP_JUMP = 1; + public static final int M68K_GRP_RET = 3; + public static final int M68K_GRP_IRET = 5; + public static final int M68K_GRP_BRANCH_RELATIVE = 7; + public static final int M68K_GRP_ENDING = 8; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Mips.java b/white_patch_detect/capstone-master/bindings/java/capstone/Mips.java new file mode 100644 index 0000000..9bea79a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Mips.java @@ -0,0 +1,88 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.Mips_const.*; + +public class Mips { + + public static class MemType extends Structure { + public int base; + public long disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("base", "disp"); + } + } + + public static class OpValue extends Union { + public int reg; + public long imm; + public MemType mem; + + @Override + public List getFieldOrder() { + return Arrays.asList("reg", "imm", "mem"); + } + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + + public void read() { + super.read(); + if (type == MIPS_OP_MEM) + value.setType(MemType.class); + if (type == MIPS_OP_IMM) + value.setType(Long.TYPE); + if (type == MIPS_OP_REG) + value.setType(Integer.TYPE); + if (type == MIPS_OP_INVALID) + return; + readField("value"); + } + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public byte op_count; + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[10]; + } + + public void read() { + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + + public Operand [] op; + + public OpInfo(UnionOpInfo e) { + op = e.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Mips_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Mips_const.java new file mode 100644 index 0000000..01f637f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Mips_const.java @@ -0,0 +1,865 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Mips_const { + + public static final int MIPS_OP_INVALID = 0; + public static final int MIPS_OP_REG = 1; + public static final int MIPS_OP_IMM = 2; + public static final int MIPS_OP_MEM = 3; + + public static final int MIPS_REG_INVALID = 0; + public static final int MIPS_REG_PC = 1; + public static final int MIPS_REG_0 = 2; + public static final int MIPS_REG_1 = 3; + public static final int MIPS_REG_2 = 4; + public static final int MIPS_REG_3 = 5; + public static final int MIPS_REG_4 = 6; + public static final int MIPS_REG_5 = 7; + public static final int MIPS_REG_6 = 8; + public static final int MIPS_REG_7 = 9; + public static final int MIPS_REG_8 = 10; + public static final int MIPS_REG_9 = 11; + public static final int MIPS_REG_10 = 12; + public static final int MIPS_REG_11 = 13; + public static final int MIPS_REG_12 = 14; + public static final int MIPS_REG_13 = 15; + public static final int MIPS_REG_14 = 16; + public static final int MIPS_REG_15 = 17; + public static final int MIPS_REG_16 = 18; + public static final int MIPS_REG_17 = 19; + public static final int MIPS_REG_18 = 20; + public static final int MIPS_REG_19 = 21; + public static final int MIPS_REG_20 = 22; + public static final int MIPS_REG_21 = 23; + public static final int MIPS_REG_22 = 24; + public static final int MIPS_REG_23 = 25; + public static final int MIPS_REG_24 = 26; + public static final int MIPS_REG_25 = 27; + public static final int MIPS_REG_26 = 28; + public static final int MIPS_REG_27 = 29; + public static final int MIPS_REG_28 = 30; + public static final int MIPS_REG_29 = 31; + public static final int MIPS_REG_30 = 32; + public static final int MIPS_REG_31 = 33; + public static final int MIPS_REG_DSPCCOND = 34; + public static final int MIPS_REG_DSPCARRY = 35; + public static final int MIPS_REG_DSPEFI = 36; + public static final int MIPS_REG_DSPOUTFLAG = 37; + public static final int MIPS_REG_DSPOUTFLAG16_19 = 38; + public static final int MIPS_REG_DSPOUTFLAG20 = 39; + public static final int MIPS_REG_DSPOUTFLAG21 = 40; + public static final int MIPS_REG_DSPOUTFLAG22 = 41; + public static final int MIPS_REG_DSPOUTFLAG23 = 42; + public static final int MIPS_REG_DSPPOS = 43; + public static final int MIPS_REG_DSPSCOUNT = 44; + public static final int MIPS_REG_AC0 = 45; + public static final int MIPS_REG_AC1 = 46; + public static final int MIPS_REG_AC2 = 47; + public static final int MIPS_REG_AC3 = 48; + public static final int MIPS_REG_CC0 = 49; + public static final int MIPS_REG_CC1 = 50; + public static final int MIPS_REG_CC2 = 51; + public static final int MIPS_REG_CC3 = 52; + public static final int MIPS_REG_CC4 = 53; + public static final int MIPS_REG_CC5 = 54; + public static final int MIPS_REG_CC6 = 55; + public static final int MIPS_REG_CC7 = 56; + public static final int MIPS_REG_F0 = 57; + public static final int MIPS_REG_F1 = 58; + public static final int MIPS_REG_F2 = 59; + public static final int MIPS_REG_F3 = 60; + public static final int MIPS_REG_F4 = 61; + public static final int MIPS_REG_F5 = 62; + public static final int MIPS_REG_F6 = 63; + public static final int MIPS_REG_F7 = 64; + public static final int MIPS_REG_F8 = 65; + public static final int MIPS_REG_F9 = 66; + public static final int MIPS_REG_F10 = 67; + public static final int MIPS_REG_F11 = 68; + public static final int MIPS_REG_F12 = 69; + public static final int MIPS_REG_F13 = 70; + public static final int MIPS_REG_F14 = 71; + public static final int MIPS_REG_F15 = 72; + public static final int MIPS_REG_F16 = 73; + public static final int MIPS_REG_F17 = 74; + public static final int MIPS_REG_F18 = 75; + public static final int MIPS_REG_F19 = 76; + public static final int MIPS_REG_F20 = 77; + public static final int MIPS_REG_F21 = 78; + public static final int MIPS_REG_F22 = 79; + public static final int MIPS_REG_F23 = 80; + public static final int MIPS_REG_F24 = 81; + public static final int MIPS_REG_F25 = 82; + public static final int MIPS_REG_F26 = 83; + public static final int MIPS_REG_F27 = 84; + public static final int MIPS_REG_F28 = 85; + public static final int MIPS_REG_F29 = 86; + public static final int MIPS_REG_F30 = 87; + public static final int MIPS_REG_F31 = 88; + public static final int MIPS_REG_FCC0 = 89; + public static final int MIPS_REG_FCC1 = 90; + public static final int MIPS_REG_FCC2 = 91; + public static final int MIPS_REG_FCC3 = 92; + public static final int MIPS_REG_FCC4 = 93; + public static final int MIPS_REG_FCC5 = 94; + public static final int MIPS_REG_FCC6 = 95; + public static final int MIPS_REG_FCC7 = 96; + public static final int MIPS_REG_W0 = 97; + public static final int MIPS_REG_W1 = 98; + public static final int MIPS_REG_W2 = 99; + public static final int MIPS_REG_W3 = 100; + public static final int MIPS_REG_W4 = 101; + public static final int MIPS_REG_W5 = 102; + public static final int MIPS_REG_W6 = 103; + public static final int MIPS_REG_W7 = 104; + public static final int MIPS_REG_W8 = 105; + public static final int MIPS_REG_W9 = 106; + public static final int MIPS_REG_W10 = 107; + public static final int MIPS_REG_W11 = 108; + public static final int MIPS_REG_W12 = 109; + public static final int MIPS_REG_W13 = 110; + public static final int MIPS_REG_W14 = 111; + public static final int MIPS_REG_W15 = 112; + public static final int MIPS_REG_W16 = 113; + public static final int MIPS_REG_W17 = 114; + public static final int MIPS_REG_W18 = 115; + public static final int MIPS_REG_W19 = 116; + public static final int MIPS_REG_W20 = 117; + public static final int MIPS_REG_W21 = 118; + public static final int MIPS_REG_W22 = 119; + public static final int MIPS_REG_W23 = 120; + public static final int MIPS_REG_W24 = 121; + public static final int MIPS_REG_W25 = 122; + public static final int MIPS_REG_W26 = 123; + public static final int MIPS_REG_W27 = 124; + public static final int MIPS_REG_W28 = 125; + public static final int MIPS_REG_W29 = 126; + public static final int MIPS_REG_W30 = 127; + public static final int MIPS_REG_W31 = 128; + public static final int MIPS_REG_HI = 129; + public static final int MIPS_REG_LO = 130; + public static final int MIPS_REG_P0 = 131; + public static final int MIPS_REG_P1 = 132; + public static final int MIPS_REG_P2 = 133; + public static final int MIPS_REG_MPL0 = 134; + public static final int MIPS_REG_MPL1 = 135; + public static final int MIPS_REG_MPL2 = 136; + public static final int MIPS_REG_ENDING = 137; + public static final int MIPS_REG_ZERO = MIPS_REG_0; + public static final int MIPS_REG_AT = MIPS_REG_1; + public static final int MIPS_REG_V0 = MIPS_REG_2; + public static final int MIPS_REG_V1 = MIPS_REG_3; + public static final int MIPS_REG_A0 = MIPS_REG_4; + public static final int MIPS_REG_A1 = MIPS_REG_5; + public static final int MIPS_REG_A2 = MIPS_REG_6; + public static final int MIPS_REG_A3 = MIPS_REG_7; + public static final int MIPS_REG_T0 = MIPS_REG_8; + public static final int MIPS_REG_T1 = MIPS_REG_9; + public static final int MIPS_REG_T2 = MIPS_REG_10; + public static final int MIPS_REG_T3 = MIPS_REG_11; + public static final int MIPS_REG_T4 = MIPS_REG_12; + public static final int MIPS_REG_T5 = MIPS_REG_13; + public static final int MIPS_REG_T6 = MIPS_REG_14; + public static final int MIPS_REG_T7 = MIPS_REG_15; + public static final int MIPS_REG_S0 = MIPS_REG_16; + public static final int MIPS_REG_S1 = MIPS_REG_17; + public static final int MIPS_REG_S2 = MIPS_REG_18; + public static final int MIPS_REG_S3 = MIPS_REG_19; + public static final int MIPS_REG_S4 = MIPS_REG_20; + public static final int MIPS_REG_S5 = MIPS_REG_21; + public static final int MIPS_REG_S6 = MIPS_REG_22; + public static final int MIPS_REG_S7 = MIPS_REG_23; + public static final int MIPS_REG_T8 = MIPS_REG_24; + public static final int MIPS_REG_T9 = MIPS_REG_25; + public static final int MIPS_REG_K0 = MIPS_REG_26; + public static final int MIPS_REG_K1 = MIPS_REG_27; + public static final int MIPS_REG_GP = MIPS_REG_28; + public static final int MIPS_REG_SP = MIPS_REG_29; + public static final int MIPS_REG_FP = MIPS_REG_30; + public static final int MIPS_REG_S8 = MIPS_REG_30; + public static final int MIPS_REG_RA = MIPS_REG_31; + public static final int MIPS_REG_HI0 = MIPS_REG_AC0; + public static final int MIPS_REG_HI1 = MIPS_REG_AC1; + public static final int MIPS_REG_HI2 = MIPS_REG_AC2; + public static final int MIPS_REG_HI3 = MIPS_REG_AC3; + public static final int MIPS_REG_LO0 = MIPS_REG_HI0; + public static final int MIPS_REG_LO1 = MIPS_REG_HI1; + public static final int MIPS_REG_LO2 = MIPS_REG_HI2; + public static final int MIPS_REG_LO3 = MIPS_REG_HI3; + + public static final int MIPS_INS_INVALID = 0; + public static final int MIPS_INS_ABSQ_S = 1; + public static final int MIPS_INS_ADD = 2; + public static final int MIPS_INS_ADDIUPC = 3; + public static final int MIPS_INS_ADDIUR1SP = 4; + public static final int MIPS_INS_ADDIUR2 = 5; + public static final int MIPS_INS_ADDIUS5 = 6; + public static final int MIPS_INS_ADDIUSP = 7; + public static final int MIPS_INS_ADDQH = 8; + public static final int MIPS_INS_ADDQH_R = 9; + public static final int MIPS_INS_ADDQ = 10; + public static final int MIPS_INS_ADDQ_S = 11; + public static final int MIPS_INS_ADDSC = 12; + public static final int MIPS_INS_ADDS_A = 13; + public static final int MIPS_INS_ADDS_S = 14; + public static final int MIPS_INS_ADDS_U = 15; + public static final int MIPS_INS_ADDU16 = 16; + public static final int MIPS_INS_ADDUH = 17; + public static final int MIPS_INS_ADDUH_R = 18; + public static final int MIPS_INS_ADDU = 19; + public static final int MIPS_INS_ADDU_S = 20; + public static final int MIPS_INS_ADDVI = 21; + public static final int MIPS_INS_ADDV = 22; + public static final int MIPS_INS_ADDWC = 23; + public static final int MIPS_INS_ADD_A = 24; + public static final int MIPS_INS_ADDI = 25; + public static final int MIPS_INS_ADDIU = 26; + public static final int MIPS_INS_ALIGN = 27; + public static final int MIPS_INS_ALUIPC = 28; + public static final int MIPS_INS_AND = 29; + public static final int MIPS_INS_AND16 = 30; + public static final int MIPS_INS_ANDI16 = 31; + public static final int MIPS_INS_ANDI = 32; + public static final int MIPS_INS_APPEND = 33; + public static final int MIPS_INS_ASUB_S = 34; + public static final int MIPS_INS_ASUB_U = 35; + public static final int MIPS_INS_AUI = 36; + public static final int MIPS_INS_AUIPC = 37; + public static final int MIPS_INS_AVER_S = 38; + public static final int MIPS_INS_AVER_U = 39; + public static final int MIPS_INS_AVE_S = 40; + public static final int MIPS_INS_AVE_U = 41; + public static final int MIPS_INS_B16 = 42; + public static final int MIPS_INS_BADDU = 43; + public static final int MIPS_INS_BAL = 44; + public static final int MIPS_INS_BALC = 45; + public static final int MIPS_INS_BALIGN = 46; + public static final int MIPS_INS_BBIT0 = 47; + public static final int MIPS_INS_BBIT032 = 48; + public static final int MIPS_INS_BBIT1 = 49; + public static final int MIPS_INS_BBIT132 = 50; + public static final int MIPS_INS_BC = 51; + public static final int MIPS_INS_BC0F = 52; + public static final int MIPS_INS_BC0FL = 53; + public static final int MIPS_INS_BC0T = 54; + public static final int MIPS_INS_BC0TL = 55; + public static final int MIPS_INS_BC1EQZ = 56; + public static final int MIPS_INS_BC1F = 57; + public static final int MIPS_INS_BC1FL = 58; + public static final int MIPS_INS_BC1NEZ = 59; + public static final int MIPS_INS_BC1T = 60; + public static final int MIPS_INS_BC1TL = 61; + public static final int MIPS_INS_BC2EQZ = 62; + public static final int MIPS_INS_BC2F = 63; + public static final int MIPS_INS_BC2FL = 64; + public static final int MIPS_INS_BC2NEZ = 65; + public static final int MIPS_INS_BC2T = 66; + public static final int MIPS_INS_BC2TL = 67; + public static final int MIPS_INS_BC3F = 68; + public static final int MIPS_INS_BC3FL = 69; + public static final int MIPS_INS_BC3T = 70; + public static final int MIPS_INS_BC3TL = 71; + public static final int MIPS_INS_BCLRI = 72; + public static final int MIPS_INS_BCLR = 73; + public static final int MIPS_INS_BEQ = 74; + public static final int MIPS_INS_BEQC = 75; + public static final int MIPS_INS_BEQL = 76; + public static final int MIPS_INS_BEQZ16 = 77; + public static final int MIPS_INS_BEQZALC = 78; + public static final int MIPS_INS_BEQZC = 79; + public static final int MIPS_INS_BGEC = 80; + public static final int MIPS_INS_BGEUC = 81; + public static final int MIPS_INS_BGEZ = 82; + public static final int MIPS_INS_BGEZAL = 83; + public static final int MIPS_INS_BGEZALC = 84; + public static final int MIPS_INS_BGEZALL = 85; + public static final int MIPS_INS_BGEZALS = 86; + public static final int MIPS_INS_BGEZC = 87; + public static final int MIPS_INS_BGEZL = 88; + public static final int MIPS_INS_BGTZ = 89; + public static final int MIPS_INS_BGTZALC = 90; + public static final int MIPS_INS_BGTZC = 91; + public static final int MIPS_INS_BGTZL = 92; + public static final int MIPS_INS_BINSLI = 93; + public static final int MIPS_INS_BINSL = 94; + public static final int MIPS_INS_BINSRI = 95; + public static final int MIPS_INS_BINSR = 96; + public static final int MIPS_INS_BITREV = 97; + public static final int MIPS_INS_BITSWAP = 98; + public static final int MIPS_INS_BLEZ = 99; + public static final int MIPS_INS_BLEZALC = 100; + public static final int MIPS_INS_BLEZC = 101; + public static final int MIPS_INS_BLEZL = 102; + public static final int MIPS_INS_BLTC = 103; + public static final int MIPS_INS_BLTUC = 104; + public static final int MIPS_INS_BLTZ = 105; + public static final int MIPS_INS_BLTZAL = 106; + public static final int MIPS_INS_BLTZALC = 107; + public static final int MIPS_INS_BLTZALL = 108; + public static final int MIPS_INS_BLTZALS = 109; + public static final int MIPS_INS_BLTZC = 110; + public static final int MIPS_INS_BLTZL = 111; + public static final int MIPS_INS_BMNZI = 112; + public static final int MIPS_INS_BMNZ = 113; + public static final int MIPS_INS_BMZI = 114; + public static final int MIPS_INS_BMZ = 115; + public static final int MIPS_INS_BNE = 116; + public static final int MIPS_INS_BNEC = 117; + public static final int MIPS_INS_BNEGI = 118; + public static final int MIPS_INS_BNEG = 119; + public static final int MIPS_INS_BNEL = 120; + public static final int MIPS_INS_BNEZ16 = 121; + public static final int MIPS_INS_BNEZALC = 122; + public static final int MIPS_INS_BNEZC = 123; + public static final int MIPS_INS_BNVC = 124; + public static final int MIPS_INS_BNZ = 125; + public static final int MIPS_INS_BOVC = 126; + public static final int MIPS_INS_BPOSGE32 = 127; + public static final int MIPS_INS_BREAK = 128; + public static final int MIPS_INS_BREAK16 = 129; + public static final int MIPS_INS_BSELI = 130; + public static final int MIPS_INS_BSEL = 131; + public static final int MIPS_INS_BSETI = 132; + public static final int MIPS_INS_BSET = 133; + public static final int MIPS_INS_BZ = 134; + public static final int MIPS_INS_BEQZ = 135; + public static final int MIPS_INS_B = 136; + public static final int MIPS_INS_BNEZ = 137; + public static final int MIPS_INS_BTEQZ = 138; + public static final int MIPS_INS_BTNEZ = 139; + public static final int MIPS_INS_CACHE = 140; + public static final int MIPS_INS_CEIL = 141; + public static final int MIPS_INS_CEQI = 142; + public static final int MIPS_INS_CEQ = 143; + public static final int MIPS_INS_CFC1 = 144; + public static final int MIPS_INS_CFCMSA = 145; + public static final int MIPS_INS_CINS = 146; + public static final int MIPS_INS_CINS32 = 147; + public static final int MIPS_INS_CLASS = 148; + public static final int MIPS_INS_CLEI_S = 149; + public static final int MIPS_INS_CLEI_U = 150; + public static final int MIPS_INS_CLE_S = 151; + public static final int MIPS_INS_CLE_U = 152; + public static final int MIPS_INS_CLO = 153; + public static final int MIPS_INS_CLTI_S = 154; + public static final int MIPS_INS_CLTI_U = 155; + public static final int MIPS_INS_CLT_S = 156; + public static final int MIPS_INS_CLT_U = 157; + public static final int MIPS_INS_CLZ = 158; + public static final int MIPS_INS_CMPGDU = 159; + public static final int MIPS_INS_CMPGU = 160; + public static final int MIPS_INS_CMPU = 161; + public static final int MIPS_INS_CMP = 162; + public static final int MIPS_INS_COPY_S = 163; + public static final int MIPS_INS_COPY_U = 164; + public static final int MIPS_INS_CTC1 = 165; + public static final int MIPS_INS_CTCMSA = 166; + public static final int MIPS_INS_CVT = 167; + public static final int MIPS_INS_C = 168; + public static final int MIPS_INS_CMPI = 169; + public static final int MIPS_INS_DADD = 170; + public static final int MIPS_INS_DADDI = 171; + public static final int MIPS_INS_DADDIU = 172; + public static final int MIPS_INS_DADDU = 173; + public static final int MIPS_INS_DAHI = 174; + public static final int MIPS_INS_DALIGN = 175; + public static final int MIPS_INS_DATI = 176; + public static final int MIPS_INS_DAUI = 177; + public static final int MIPS_INS_DBITSWAP = 178; + public static final int MIPS_INS_DCLO = 179; + public static final int MIPS_INS_DCLZ = 180; + public static final int MIPS_INS_DDIV = 181; + public static final int MIPS_INS_DDIVU = 182; + public static final int MIPS_INS_DERET = 183; + public static final int MIPS_INS_DEXT = 184; + public static final int MIPS_INS_DEXTM = 185; + public static final int MIPS_INS_DEXTU = 186; + public static final int MIPS_INS_DI = 187; + public static final int MIPS_INS_DINS = 188; + public static final int MIPS_INS_DINSM = 189; + public static final int MIPS_INS_DINSU = 190; + public static final int MIPS_INS_DIV = 191; + public static final int MIPS_INS_DIVU = 192; + public static final int MIPS_INS_DIV_S = 193; + public static final int MIPS_INS_DIV_U = 194; + public static final int MIPS_INS_DLSA = 195; + public static final int MIPS_INS_DMFC0 = 196; + public static final int MIPS_INS_DMFC1 = 197; + public static final int MIPS_INS_DMFC2 = 198; + public static final int MIPS_INS_DMOD = 199; + public static final int MIPS_INS_DMODU = 200; + public static final int MIPS_INS_DMTC0 = 201; + public static final int MIPS_INS_DMTC1 = 202; + public static final int MIPS_INS_DMTC2 = 203; + public static final int MIPS_INS_DMUH = 204; + public static final int MIPS_INS_DMUHU = 205; + public static final int MIPS_INS_DMUL = 206; + public static final int MIPS_INS_DMULT = 207; + public static final int MIPS_INS_DMULTU = 208; + public static final int MIPS_INS_DMULU = 209; + public static final int MIPS_INS_DOTP_S = 210; + public static final int MIPS_INS_DOTP_U = 211; + public static final int MIPS_INS_DPADD_S = 212; + public static final int MIPS_INS_DPADD_U = 213; + public static final int MIPS_INS_DPAQX_SA = 214; + public static final int MIPS_INS_DPAQX_S = 215; + public static final int MIPS_INS_DPAQ_SA = 216; + public static final int MIPS_INS_DPAQ_S = 217; + public static final int MIPS_INS_DPAU = 218; + public static final int MIPS_INS_DPAX = 219; + public static final int MIPS_INS_DPA = 220; + public static final int MIPS_INS_DPOP = 221; + public static final int MIPS_INS_DPSQX_SA = 222; + public static final int MIPS_INS_DPSQX_S = 223; + public static final int MIPS_INS_DPSQ_SA = 224; + public static final int MIPS_INS_DPSQ_S = 225; + public static final int MIPS_INS_DPSUB_S = 226; + public static final int MIPS_INS_DPSUB_U = 227; + public static final int MIPS_INS_DPSU = 228; + public static final int MIPS_INS_DPSX = 229; + public static final int MIPS_INS_DPS = 230; + public static final int MIPS_INS_DROTR = 231; + public static final int MIPS_INS_DROTR32 = 232; + public static final int MIPS_INS_DROTRV = 233; + public static final int MIPS_INS_DSBH = 234; + public static final int MIPS_INS_DSHD = 235; + public static final int MIPS_INS_DSLL = 236; + public static final int MIPS_INS_DSLL32 = 237; + public static final int MIPS_INS_DSLLV = 238; + public static final int MIPS_INS_DSRA = 239; + public static final int MIPS_INS_DSRA32 = 240; + public static final int MIPS_INS_DSRAV = 241; + public static final int MIPS_INS_DSRL = 242; + public static final int MIPS_INS_DSRL32 = 243; + public static final int MIPS_INS_DSRLV = 244; + public static final int MIPS_INS_DSUB = 245; + public static final int MIPS_INS_DSUBU = 246; + public static final int MIPS_INS_EHB = 247; + public static final int MIPS_INS_EI = 248; + public static final int MIPS_INS_ERET = 249; + public static final int MIPS_INS_EXT = 250; + public static final int MIPS_INS_EXTP = 251; + public static final int MIPS_INS_EXTPDP = 252; + public static final int MIPS_INS_EXTPDPV = 253; + public static final int MIPS_INS_EXTPV = 254; + public static final int MIPS_INS_EXTRV_RS = 255; + public static final int MIPS_INS_EXTRV_R = 256; + public static final int MIPS_INS_EXTRV_S = 257; + public static final int MIPS_INS_EXTRV = 258; + public static final int MIPS_INS_EXTR_RS = 259; + public static final int MIPS_INS_EXTR_R = 260; + public static final int MIPS_INS_EXTR_S = 261; + public static final int MIPS_INS_EXTR = 262; + public static final int MIPS_INS_EXTS = 263; + public static final int MIPS_INS_EXTS32 = 264; + public static final int MIPS_INS_ABS = 265; + public static final int MIPS_INS_FADD = 266; + public static final int MIPS_INS_FCAF = 267; + public static final int MIPS_INS_FCEQ = 268; + public static final int MIPS_INS_FCLASS = 269; + public static final int MIPS_INS_FCLE = 270; + public static final int MIPS_INS_FCLT = 271; + public static final int MIPS_INS_FCNE = 272; + public static final int MIPS_INS_FCOR = 273; + public static final int MIPS_INS_FCUEQ = 274; + public static final int MIPS_INS_FCULE = 275; + public static final int MIPS_INS_FCULT = 276; + public static final int MIPS_INS_FCUNE = 277; + public static final int MIPS_INS_FCUN = 278; + public static final int MIPS_INS_FDIV = 279; + public static final int MIPS_INS_FEXDO = 280; + public static final int MIPS_INS_FEXP2 = 281; + public static final int MIPS_INS_FEXUPL = 282; + public static final int MIPS_INS_FEXUPR = 283; + public static final int MIPS_INS_FFINT_S = 284; + public static final int MIPS_INS_FFINT_U = 285; + public static final int MIPS_INS_FFQL = 286; + public static final int MIPS_INS_FFQR = 287; + public static final int MIPS_INS_FILL = 288; + public static final int MIPS_INS_FLOG2 = 289; + public static final int MIPS_INS_FLOOR = 290; + public static final int MIPS_INS_FMADD = 291; + public static final int MIPS_INS_FMAX_A = 292; + public static final int MIPS_INS_FMAX = 293; + public static final int MIPS_INS_FMIN_A = 294; + public static final int MIPS_INS_FMIN = 295; + public static final int MIPS_INS_MOV = 296; + public static final int MIPS_INS_FMSUB = 297; + public static final int MIPS_INS_FMUL = 298; + public static final int MIPS_INS_MUL = 299; + public static final int MIPS_INS_NEG = 300; + public static final int MIPS_INS_FRCP = 301; + public static final int MIPS_INS_FRINT = 302; + public static final int MIPS_INS_FRSQRT = 303; + public static final int MIPS_INS_FSAF = 304; + public static final int MIPS_INS_FSEQ = 305; + public static final int MIPS_INS_FSLE = 306; + public static final int MIPS_INS_FSLT = 307; + public static final int MIPS_INS_FSNE = 308; + public static final int MIPS_INS_FSOR = 309; + public static final int MIPS_INS_FSQRT = 310; + public static final int MIPS_INS_SQRT = 311; + public static final int MIPS_INS_FSUB = 312; + public static final int MIPS_INS_SUB = 313; + public static final int MIPS_INS_FSUEQ = 314; + public static final int MIPS_INS_FSULE = 315; + public static final int MIPS_INS_FSULT = 316; + public static final int MIPS_INS_FSUNE = 317; + public static final int MIPS_INS_FSUN = 318; + public static final int MIPS_INS_FTINT_S = 319; + public static final int MIPS_INS_FTINT_U = 320; + public static final int MIPS_INS_FTQ = 321; + public static final int MIPS_INS_FTRUNC_S = 322; + public static final int MIPS_INS_FTRUNC_U = 323; + public static final int MIPS_INS_HADD_S = 324; + public static final int MIPS_INS_HADD_U = 325; + public static final int MIPS_INS_HSUB_S = 326; + public static final int MIPS_INS_HSUB_U = 327; + public static final int MIPS_INS_ILVEV = 328; + public static final int MIPS_INS_ILVL = 329; + public static final int MIPS_INS_ILVOD = 330; + public static final int MIPS_INS_ILVR = 331; + public static final int MIPS_INS_INS = 332; + public static final int MIPS_INS_INSERT = 333; + public static final int MIPS_INS_INSV = 334; + public static final int MIPS_INS_INSVE = 335; + public static final int MIPS_INS_J = 336; + public static final int MIPS_INS_JAL = 337; + public static final int MIPS_INS_JALR = 338; + public static final int MIPS_INS_JALRS16 = 339; + public static final int MIPS_INS_JALRS = 340; + public static final int MIPS_INS_JALS = 341; + public static final int MIPS_INS_JALX = 342; + public static final int MIPS_INS_JIALC = 343; + public static final int MIPS_INS_JIC = 344; + public static final int MIPS_INS_JR = 345; + public static final int MIPS_INS_JR16 = 346; + public static final int MIPS_INS_JRADDIUSP = 347; + public static final int MIPS_INS_JRC = 348; + public static final int MIPS_INS_JALRC = 349; + public static final int MIPS_INS_LB = 350; + public static final int MIPS_INS_LBU16 = 351; + public static final int MIPS_INS_LBUX = 352; + public static final int MIPS_INS_LBU = 353; + public static final int MIPS_INS_LD = 354; + public static final int MIPS_INS_LDC1 = 355; + public static final int MIPS_INS_LDC2 = 356; + public static final int MIPS_INS_LDC3 = 357; + public static final int MIPS_INS_LDI = 358; + public static final int MIPS_INS_LDL = 359; + public static final int MIPS_INS_LDPC = 360; + public static final int MIPS_INS_LDR = 361; + public static final int MIPS_INS_LDXC1 = 362; + public static final int MIPS_INS_LH = 363; + public static final int MIPS_INS_LHU16 = 364; + public static final int MIPS_INS_LHX = 365; + public static final int MIPS_INS_LHU = 366; + public static final int MIPS_INS_LI16 = 367; + public static final int MIPS_INS_LL = 368; + public static final int MIPS_INS_LLD = 369; + public static final int MIPS_INS_LSA = 370; + public static final int MIPS_INS_LUXC1 = 371; + public static final int MIPS_INS_LUI = 372; + public static final int MIPS_INS_LW = 373; + public static final int MIPS_INS_LW16 = 374; + public static final int MIPS_INS_LWC1 = 375; + public static final int MIPS_INS_LWC2 = 376; + public static final int MIPS_INS_LWC3 = 377; + public static final int MIPS_INS_LWL = 378; + public static final int MIPS_INS_LWM16 = 379; + public static final int MIPS_INS_LWM32 = 380; + public static final int MIPS_INS_LWPC = 381; + public static final int MIPS_INS_LWP = 382; + public static final int MIPS_INS_LWR = 383; + public static final int MIPS_INS_LWUPC = 384; + public static final int MIPS_INS_LWU = 385; + public static final int MIPS_INS_LWX = 386; + public static final int MIPS_INS_LWXC1 = 387; + public static final int MIPS_INS_LWXS = 388; + public static final int MIPS_INS_LI = 389; + public static final int MIPS_INS_MADD = 390; + public static final int MIPS_INS_MADDF = 391; + public static final int MIPS_INS_MADDR_Q = 392; + public static final int MIPS_INS_MADDU = 393; + public static final int MIPS_INS_MADDV = 394; + public static final int MIPS_INS_MADD_Q = 395; + public static final int MIPS_INS_MAQ_SA = 396; + public static final int MIPS_INS_MAQ_S = 397; + public static final int MIPS_INS_MAXA = 398; + public static final int MIPS_INS_MAXI_S = 399; + public static final int MIPS_INS_MAXI_U = 400; + public static final int MIPS_INS_MAX_A = 401; + public static final int MIPS_INS_MAX = 402; + public static final int MIPS_INS_MAX_S = 403; + public static final int MIPS_INS_MAX_U = 404; + public static final int MIPS_INS_MFC0 = 405; + public static final int MIPS_INS_MFC1 = 406; + public static final int MIPS_INS_MFC2 = 407; + public static final int MIPS_INS_MFHC1 = 408; + public static final int MIPS_INS_MFHI = 409; + public static final int MIPS_INS_MFLO = 410; + public static final int MIPS_INS_MINA = 411; + public static final int MIPS_INS_MINI_S = 412; + public static final int MIPS_INS_MINI_U = 413; + public static final int MIPS_INS_MIN_A = 414; + public static final int MIPS_INS_MIN = 415; + public static final int MIPS_INS_MIN_S = 416; + public static final int MIPS_INS_MIN_U = 417; + public static final int MIPS_INS_MOD = 418; + public static final int MIPS_INS_MODSUB = 419; + public static final int MIPS_INS_MODU = 420; + public static final int MIPS_INS_MOD_S = 421; + public static final int MIPS_INS_MOD_U = 422; + public static final int MIPS_INS_MOVE = 423; + public static final int MIPS_INS_MOVEP = 424; + public static final int MIPS_INS_MOVF = 425; + public static final int MIPS_INS_MOVN = 426; + public static final int MIPS_INS_MOVT = 427; + public static final int MIPS_INS_MOVZ = 428; + public static final int MIPS_INS_MSUB = 429; + public static final int MIPS_INS_MSUBF = 430; + public static final int MIPS_INS_MSUBR_Q = 431; + public static final int MIPS_INS_MSUBU = 432; + public static final int MIPS_INS_MSUBV = 433; + public static final int MIPS_INS_MSUB_Q = 434; + public static final int MIPS_INS_MTC0 = 435; + public static final int MIPS_INS_MTC1 = 436; + public static final int MIPS_INS_MTC2 = 437; + public static final int MIPS_INS_MTHC1 = 438; + public static final int MIPS_INS_MTHI = 439; + public static final int MIPS_INS_MTHLIP = 440; + public static final int MIPS_INS_MTLO = 441; + public static final int MIPS_INS_MTM0 = 442; + public static final int MIPS_INS_MTM1 = 443; + public static final int MIPS_INS_MTM2 = 444; + public static final int MIPS_INS_MTP0 = 445; + public static final int MIPS_INS_MTP1 = 446; + public static final int MIPS_INS_MTP2 = 447; + public static final int MIPS_INS_MUH = 448; + public static final int MIPS_INS_MUHU = 449; + public static final int MIPS_INS_MULEQ_S = 450; + public static final int MIPS_INS_MULEU_S = 451; + public static final int MIPS_INS_MULQ_RS = 452; + public static final int MIPS_INS_MULQ_S = 453; + public static final int MIPS_INS_MULR_Q = 454; + public static final int MIPS_INS_MULSAQ_S = 455; + public static final int MIPS_INS_MULSA = 456; + public static final int MIPS_INS_MULT = 457; + public static final int MIPS_INS_MULTU = 458; + public static final int MIPS_INS_MULU = 459; + public static final int MIPS_INS_MULV = 460; + public static final int MIPS_INS_MUL_Q = 461; + public static final int MIPS_INS_MUL_S = 462; + public static final int MIPS_INS_NLOC = 463; + public static final int MIPS_INS_NLZC = 464; + public static final int MIPS_INS_NMADD = 465; + public static final int MIPS_INS_NMSUB = 466; + public static final int MIPS_INS_NOR = 467; + public static final int MIPS_INS_NORI = 468; + public static final int MIPS_INS_NOT16 = 469; + public static final int MIPS_INS_NOT = 470; + public static final int MIPS_INS_OR = 471; + public static final int MIPS_INS_OR16 = 472; + public static final int MIPS_INS_ORI = 473; + public static final int MIPS_INS_PACKRL = 474; + public static final int MIPS_INS_PAUSE = 475; + public static final int MIPS_INS_PCKEV = 476; + public static final int MIPS_INS_PCKOD = 477; + public static final int MIPS_INS_PCNT = 478; + public static final int MIPS_INS_PICK = 479; + public static final int MIPS_INS_POP = 480; + public static final int MIPS_INS_PRECEQU = 481; + public static final int MIPS_INS_PRECEQ = 482; + public static final int MIPS_INS_PRECEU = 483; + public static final int MIPS_INS_PRECRQU_S = 484; + public static final int MIPS_INS_PRECRQ = 485; + public static final int MIPS_INS_PRECRQ_RS = 486; + public static final int MIPS_INS_PRECR = 487; + public static final int MIPS_INS_PRECR_SRA = 488; + public static final int MIPS_INS_PRECR_SRA_R = 489; + public static final int MIPS_INS_PREF = 490; + public static final int MIPS_INS_PREPEND = 491; + public static final int MIPS_INS_RADDU = 492; + public static final int MIPS_INS_RDDSP = 493; + public static final int MIPS_INS_RDHWR = 494; + public static final int MIPS_INS_REPLV = 495; + public static final int MIPS_INS_REPL = 496; + public static final int MIPS_INS_RINT = 497; + public static final int MIPS_INS_ROTR = 498; + public static final int MIPS_INS_ROTRV = 499; + public static final int MIPS_INS_ROUND = 500; + public static final int MIPS_INS_SAT_S = 501; + public static final int MIPS_INS_SAT_U = 502; + public static final int MIPS_INS_SB = 503; + public static final int MIPS_INS_SB16 = 504; + public static final int MIPS_INS_SC = 505; + public static final int MIPS_INS_SCD = 506; + public static final int MIPS_INS_SD = 507; + public static final int MIPS_INS_SDBBP = 508; + public static final int MIPS_INS_SDBBP16 = 509; + public static final int MIPS_INS_SDC1 = 510; + public static final int MIPS_INS_SDC2 = 511; + public static final int MIPS_INS_SDC3 = 512; + public static final int MIPS_INS_SDL = 513; + public static final int MIPS_INS_SDR = 514; + public static final int MIPS_INS_SDXC1 = 515; + public static final int MIPS_INS_SEB = 516; + public static final int MIPS_INS_SEH = 517; + public static final int MIPS_INS_SELEQZ = 518; + public static final int MIPS_INS_SELNEZ = 519; + public static final int MIPS_INS_SEL = 520; + public static final int MIPS_INS_SEQ = 521; + public static final int MIPS_INS_SEQI = 522; + public static final int MIPS_INS_SH = 523; + public static final int MIPS_INS_SH16 = 524; + public static final int MIPS_INS_SHF = 525; + public static final int MIPS_INS_SHILO = 526; + public static final int MIPS_INS_SHILOV = 527; + public static final int MIPS_INS_SHLLV = 528; + public static final int MIPS_INS_SHLLV_S = 529; + public static final int MIPS_INS_SHLL = 530; + public static final int MIPS_INS_SHLL_S = 531; + public static final int MIPS_INS_SHRAV = 532; + public static final int MIPS_INS_SHRAV_R = 533; + public static final int MIPS_INS_SHRA = 534; + public static final int MIPS_INS_SHRA_R = 535; + public static final int MIPS_INS_SHRLV = 536; + public static final int MIPS_INS_SHRL = 537; + public static final int MIPS_INS_SLDI = 538; + public static final int MIPS_INS_SLD = 539; + public static final int MIPS_INS_SLL = 540; + public static final int MIPS_INS_SLL16 = 541; + public static final int MIPS_INS_SLLI = 542; + public static final int MIPS_INS_SLLV = 543; + public static final int MIPS_INS_SLT = 544; + public static final int MIPS_INS_SLTI = 545; + public static final int MIPS_INS_SLTIU = 546; + public static final int MIPS_INS_SLTU = 547; + public static final int MIPS_INS_SNE = 548; + public static final int MIPS_INS_SNEI = 549; + public static final int MIPS_INS_SPLATI = 550; + public static final int MIPS_INS_SPLAT = 551; + public static final int MIPS_INS_SRA = 552; + public static final int MIPS_INS_SRAI = 553; + public static final int MIPS_INS_SRARI = 554; + public static final int MIPS_INS_SRAR = 555; + public static final int MIPS_INS_SRAV = 556; + public static final int MIPS_INS_SRL = 557; + public static final int MIPS_INS_SRL16 = 558; + public static final int MIPS_INS_SRLI = 559; + public static final int MIPS_INS_SRLRI = 560; + public static final int MIPS_INS_SRLR = 561; + public static final int MIPS_INS_SRLV = 562; + public static final int MIPS_INS_SSNOP = 563; + public static final int MIPS_INS_ST = 564; + public static final int MIPS_INS_SUBQH = 565; + public static final int MIPS_INS_SUBQH_R = 566; + public static final int MIPS_INS_SUBQ = 567; + public static final int MIPS_INS_SUBQ_S = 568; + public static final int MIPS_INS_SUBSUS_U = 569; + public static final int MIPS_INS_SUBSUU_S = 570; + public static final int MIPS_INS_SUBS_S = 571; + public static final int MIPS_INS_SUBS_U = 572; + public static final int MIPS_INS_SUBU16 = 573; + public static final int MIPS_INS_SUBUH = 574; + public static final int MIPS_INS_SUBUH_R = 575; + public static final int MIPS_INS_SUBU = 576; + public static final int MIPS_INS_SUBU_S = 577; + public static final int MIPS_INS_SUBVI = 578; + public static final int MIPS_INS_SUBV = 579; + public static final int MIPS_INS_SUXC1 = 580; + public static final int MIPS_INS_SW = 581; + public static final int MIPS_INS_SW16 = 582; + public static final int MIPS_INS_SWC1 = 583; + public static final int MIPS_INS_SWC2 = 584; + public static final int MIPS_INS_SWC3 = 585; + public static final int MIPS_INS_SWL = 586; + public static final int MIPS_INS_SWM16 = 587; + public static final int MIPS_INS_SWM32 = 588; + public static final int MIPS_INS_SWP = 589; + public static final int MIPS_INS_SWR = 590; + public static final int MIPS_INS_SWXC1 = 591; + public static final int MIPS_INS_SYNC = 592; + public static final int MIPS_INS_SYNCI = 593; + public static final int MIPS_INS_SYSCALL = 594; + public static final int MIPS_INS_TEQ = 595; + public static final int MIPS_INS_TEQI = 596; + public static final int MIPS_INS_TGE = 597; + public static final int MIPS_INS_TGEI = 598; + public static final int MIPS_INS_TGEIU = 599; + public static final int MIPS_INS_TGEU = 600; + public static final int MIPS_INS_TLBP = 601; + public static final int MIPS_INS_TLBR = 602; + public static final int MIPS_INS_TLBWI = 603; + public static final int MIPS_INS_TLBWR = 604; + public static final int MIPS_INS_TLT = 605; + public static final int MIPS_INS_TLTI = 606; + public static final int MIPS_INS_TLTIU = 607; + public static final int MIPS_INS_TLTU = 608; + public static final int MIPS_INS_TNE = 609; + public static final int MIPS_INS_TNEI = 610; + public static final int MIPS_INS_TRUNC = 611; + public static final int MIPS_INS_V3MULU = 612; + public static final int MIPS_INS_VMM0 = 613; + public static final int MIPS_INS_VMULU = 614; + public static final int MIPS_INS_VSHF = 615; + public static final int MIPS_INS_WAIT = 616; + public static final int MIPS_INS_WRDSP = 617; + public static final int MIPS_INS_WSBH = 618; + public static final int MIPS_INS_XOR = 619; + public static final int MIPS_INS_XOR16 = 620; + public static final int MIPS_INS_XORI = 621; + + // some alias instructions + public static final int MIPS_INS_NOP = 622; + public static final int MIPS_INS_NEGU = 623; + + // special instructions + public static final int MIPS_INS_JALR_HB = 624; + public static final int MIPS_INS_JR_HB = 625; + public static final int MIPS_INS_ENDING = 626; + + public static final int MIPS_GRP_INVALID = 0; + public static final int MIPS_GRP_JUMP = 1; + public static final int MIPS_GRP_CALL = 2; + public static final int MIPS_GRP_RET = 3; + public static final int MIPS_GRP_INT = 4; + public static final int MIPS_GRP_IRET = 5; + public static final int MIPS_GRP_PRIVILEGE = 6; + public static final int MIPS_GRP_BRANCH_RELATIVE = 7; + public static final int MIPS_GRP_BITCOUNT = 128; + public static final int MIPS_GRP_DSP = 129; + public static final int MIPS_GRP_DSPR2 = 130; + public static final int MIPS_GRP_FPIDX = 131; + public static final int MIPS_GRP_MSA = 132; + public static final int MIPS_GRP_MIPS32R2 = 133; + public static final int MIPS_GRP_MIPS64 = 134; + public static final int MIPS_GRP_MIPS64R2 = 135; + public static final int MIPS_GRP_SEINREG = 136; + public static final int MIPS_GRP_STDENC = 137; + public static final int MIPS_GRP_SWAP = 138; + public static final int MIPS_GRP_MICROMIPS = 139; + public static final int MIPS_GRP_MIPS16MODE = 140; + public static final int MIPS_GRP_FP64BIT = 141; + public static final int MIPS_GRP_NONANSFPMATH = 142; + public static final int MIPS_GRP_NOTFP64BIT = 143; + public static final int MIPS_GRP_NOTINMICROMIPS = 144; + public static final int MIPS_GRP_NOTNACL = 145; + public static final int MIPS_GRP_NOTMIPS32R6 = 146; + public static final int MIPS_GRP_NOTMIPS64R6 = 147; + public static final int MIPS_GRP_CNMIPS = 148; + public static final int MIPS_GRP_MIPS32 = 149; + public static final int MIPS_GRP_MIPS32R6 = 150; + public static final int MIPS_GRP_MIPS64R6 = 151; + public static final int MIPS_GRP_MIPS2 = 152; + public static final int MIPS_GRP_MIPS3 = 153; + public static final int MIPS_GRP_MIPS3_32 = 154; + public static final int MIPS_GRP_MIPS3_32R2 = 155; + public static final int MIPS_GRP_MIPS4_32 = 156; + public static final int MIPS_GRP_MIPS4_32R2 = 157; + public static final int MIPS_GRP_MIPS5_32R2 = 158; + public static final int MIPS_GRP_GP32BIT = 159; + public static final int MIPS_GRP_GP64BIT = 160; + public static final int MIPS_GRP_ENDING = 161; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Ppc.java b/white_patch_detect/capstone-master/bindings/java/capstone/Ppc.java new file mode 100644 index 0000000..128667a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Ppc.java @@ -0,0 +1,109 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.Ppc_const.*; + +public class Ppc { + + public static class MemType extends Structure { + public int base; + public int disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("base", "disp"); + } + } + + public static class CrxType extends Structure { + public int scale; + public int reg; + public int cond; + + @Override + public List getFieldOrder() { + return Arrays.asList("scale", "reg", "cond"); + } + } + + public static class OpValue extends Union { + public int reg; + public long imm; + public MemType mem; + public CrxType crx; + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + + public void read() { + readField("type"); + if (type == PPC_OP_MEM) + value.setType(MemType.class); + if (type == PPC_OP_CRX) + value.setType(CrxType.class); + if (type == PPC_OP_IMM || type == PPC_OP_REG) + value.setType(Integer.TYPE); + if (type == PPC_OP_INVALID) + return; + readField("value"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public int bc; + public int bh; + public byte update_cr0; + public byte op_count; + + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[8]; + } + + public void read() { + readField("bc"); + readField("bh"); + readField("update_cr0"); + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("bc", "bh", "update_cr0", "op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public int bc; + public int bh; + public boolean updateCr0; + + public Operand [] op; + + public OpInfo(UnionOpInfo op_info) { + bc = op_info.bc; + bh = op_info.bh; + updateCr0 = (op_info.update_cr0 > 0); + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Ppc_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Ppc_const.java new file mode 100644 index 0000000..4b3ed1b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Ppc_const.java @@ -0,0 +1,1369 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Ppc_const { + + public static final int PPC_BC_INVALID = 0; + public static final int PPC_BC_LT = (0<<5)|12; + public static final int PPC_BC_LE = (1<<5)|4; + public static final int PPC_BC_EQ = (2<<5)|12; + public static final int PPC_BC_GE = (0<<5)|4; + public static final int PPC_BC_GT = (1<<5)|12; + public static final int PPC_BC_NE = (2<<5)|4; + public static final int PPC_BC_UN = (3<<5)|12; + public static final int PPC_BC_NU = (3<<5)|4; + public static final int PPC_BC_SO = (4<<5)|12; + public static final int PPC_BC_NS = (4<<5)|4; + + public static final int PPC_BH_INVALID = 0; + public static final int PPC_BH_PLUS = 1; + public static final int PPC_BH_MINUS = 2; + + public static final int PPC_OP_INVALID = 0; + public static final int PPC_OP_REG = 1; + public static final int PPC_OP_IMM = 2; + public static final int PPC_OP_MEM = 3; + public static final int PPC_OP_CRX = 64; + + public static final int PPC_REG_INVALID = 0; + public static final int PPC_REG_CARRY = 1; + public static final int PPC_REG_CR0 = 2; + public static final int PPC_REG_CR1 = 3; + public static final int PPC_REG_CR2 = 4; + public static final int PPC_REG_CR3 = 5; + public static final int PPC_REG_CR4 = 6; + public static final int PPC_REG_CR5 = 7; + public static final int PPC_REG_CR6 = 8; + public static final int PPC_REG_CR7 = 9; + public static final int PPC_REG_CTR = 10; + public static final int PPC_REG_F0 = 11; + public static final int PPC_REG_F1 = 12; + public static final int PPC_REG_F2 = 13; + public static final int PPC_REG_F3 = 14; + public static final int PPC_REG_F4 = 15; + public static final int PPC_REG_F5 = 16; + public static final int PPC_REG_F6 = 17; + public static final int PPC_REG_F7 = 18; + public static final int PPC_REG_F8 = 19; + public static final int PPC_REG_F9 = 20; + public static final int PPC_REG_F10 = 21; + public static final int PPC_REG_F11 = 22; + public static final int PPC_REG_F12 = 23; + public static final int PPC_REG_F13 = 24; + public static final int PPC_REG_F14 = 25; + public static final int PPC_REG_F15 = 26; + public static final int PPC_REG_F16 = 27; + public static final int PPC_REG_F17 = 28; + public static final int PPC_REG_F18 = 29; + public static final int PPC_REG_F19 = 30; + public static final int PPC_REG_F20 = 31; + public static final int PPC_REG_F21 = 32; + public static final int PPC_REG_F22 = 33; + public static final int PPC_REG_F23 = 34; + public static final int PPC_REG_F24 = 35; + public static final int PPC_REG_F25 = 36; + public static final int PPC_REG_F26 = 37; + public static final int PPC_REG_F27 = 38; + public static final int PPC_REG_F28 = 39; + public static final int PPC_REG_F29 = 40; + public static final int PPC_REG_F30 = 41; + public static final int PPC_REG_F31 = 42; + public static final int PPC_REG_LR = 43; + public static final int PPC_REG_R0 = 44; + public static final int PPC_REG_R1 = 45; + public static final int PPC_REG_R2 = 46; + public static final int PPC_REG_R3 = 47; + public static final int PPC_REG_R4 = 48; + public static final int PPC_REG_R5 = 49; + public static final int PPC_REG_R6 = 50; + public static final int PPC_REG_R7 = 51; + public static final int PPC_REG_R8 = 52; + public static final int PPC_REG_R9 = 53; + public static final int PPC_REG_R10 = 54; + public static final int PPC_REG_R11 = 55; + public static final int PPC_REG_R12 = 56; + public static final int PPC_REG_R13 = 57; + public static final int PPC_REG_R14 = 58; + public static final int PPC_REG_R15 = 59; + public static final int PPC_REG_R16 = 60; + public static final int PPC_REG_R17 = 61; + public static final int PPC_REG_R18 = 62; + public static final int PPC_REG_R19 = 63; + public static final int PPC_REG_R20 = 64; + public static final int PPC_REG_R21 = 65; + public static final int PPC_REG_R22 = 66; + public static final int PPC_REG_R23 = 67; + public static final int PPC_REG_R24 = 68; + public static final int PPC_REG_R25 = 69; + public static final int PPC_REG_R26 = 70; + public static final int PPC_REG_R27 = 71; + public static final int PPC_REG_R28 = 72; + public static final int PPC_REG_R29 = 73; + public static final int PPC_REG_R30 = 74; + public static final int PPC_REG_R31 = 75; + public static final int PPC_REG_V0 = 76; + public static final int PPC_REG_V1 = 77; + public static final int PPC_REG_V2 = 78; + public static final int PPC_REG_V3 = 79; + public static final int PPC_REG_V4 = 80; + public static final int PPC_REG_V5 = 81; + public static final int PPC_REG_V6 = 82; + public static final int PPC_REG_V7 = 83; + public static final int PPC_REG_V8 = 84; + public static final int PPC_REG_V9 = 85; + public static final int PPC_REG_V10 = 86; + public static final int PPC_REG_V11 = 87; + public static final int PPC_REG_V12 = 88; + public static final int PPC_REG_V13 = 89; + public static final int PPC_REG_V14 = 90; + public static final int PPC_REG_V15 = 91; + public static final int PPC_REG_V16 = 92; + public static final int PPC_REG_V17 = 93; + public static final int PPC_REG_V18 = 94; + public static final int PPC_REG_V19 = 95; + public static final int PPC_REG_V20 = 96; + public static final int PPC_REG_V21 = 97; + public static final int PPC_REG_V22 = 98; + public static final int PPC_REG_V23 = 99; + public static final int PPC_REG_V24 = 100; + public static final int PPC_REG_V25 = 101; + public static final int PPC_REG_V26 = 102; + public static final int PPC_REG_V27 = 103; + public static final int PPC_REG_V28 = 104; + public static final int PPC_REG_V29 = 105; + public static final int PPC_REG_V30 = 106; + public static final int PPC_REG_V31 = 107; + public static final int PPC_REG_VRSAVE = 108; + public static final int PPC_REG_VS0 = 109; + public static final int PPC_REG_VS1 = 110; + public static final int PPC_REG_VS2 = 111; + public static final int PPC_REG_VS3 = 112; + public static final int PPC_REG_VS4 = 113; + public static final int PPC_REG_VS5 = 114; + public static final int PPC_REG_VS6 = 115; + public static final int PPC_REG_VS7 = 116; + public static final int PPC_REG_VS8 = 117; + public static final int PPC_REG_VS9 = 118; + public static final int PPC_REG_VS10 = 119; + public static final int PPC_REG_VS11 = 120; + public static final int PPC_REG_VS12 = 121; + public static final int PPC_REG_VS13 = 122; + public static final int PPC_REG_VS14 = 123; + public static final int PPC_REG_VS15 = 124; + public static final int PPC_REG_VS16 = 125; + public static final int PPC_REG_VS17 = 126; + public static final int PPC_REG_VS18 = 127; + public static final int PPC_REG_VS19 = 128; + public static final int PPC_REG_VS20 = 129; + public static final int PPC_REG_VS21 = 130; + public static final int PPC_REG_VS22 = 131; + public static final int PPC_REG_VS23 = 132; + public static final int PPC_REG_VS24 = 133; + public static final int PPC_REG_VS25 = 134; + public static final int PPC_REG_VS26 = 135; + public static final int PPC_REG_VS27 = 136; + public static final int PPC_REG_VS28 = 137; + public static final int PPC_REG_VS29 = 138; + public static final int PPC_REG_VS30 = 139; + public static final int PPC_REG_VS31 = 140; + public static final int PPC_REG_VS32 = 141; + public static final int PPC_REG_VS33 = 142; + public static final int PPC_REG_VS34 = 143; + public static final int PPC_REG_VS35 = 144; + public static final int PPC_REG_VS36 = 145; + public static final int PPC_REG_VS37 = 146; + public static final int PPC_REG_VS38 = 147; + public static final int PPC_REG_VS39 = 148; + public static final int PPC_REG_VS40 = 149; + public static final int PPC_REG_VS41 = 150; + public static final int PPC_REG_VS42 = 151; + public static final int PPC_REG_VS43 = 152; + public static final int PPC_REG_VS44 = 153; + public static final int PPC_REG_VS45 = 154; + public static final int PPC_REG_VS46 = 155; + public static final int PPC_REG_VS47 = 156; + public static final int PPC_REG_VS48 = 157; + public static final int PPC_REG_VS49 = 158; + public static final int PPC_REG_VS50 = 159; + public static final int PPC_REG_VS51 = 160; + public static final int PPC_REG_VS52 = 161; + public static final int PPC_REG_VS53 = 162; + public static final int PPC_REG_VS54 = 163; + public static final int PPC_REG_VS55 = 164; + public static final int PPC_REG_VS56 = 165; + public static final int PPC_REG_VS57 = 166; + public static final int PPC_REG_VS58 = 167; + public static final int PPC_REG_VS59 = 168; + public static final int PPC_REG_VS60 = 169; + public static final int PPC_REG_VS61 = 170; + public static final int PPC_REG_VS62 = 171; + public static final int PPC_REG_VS63 = 172; + public static final int PPC_REG_Q0 = 173; + public static final int PPC_REG_Q1 = 174; + public static final int PPC_REG_Q2 = 175; + public static final int PPC_REG_Q3 = 176; + public static final int PPC_REG_Q4 = 177; + public static final int PPC_REG_Q5 = 178; + public static final int PPC_REG_Q6 = 179; + public static final int PPC_REG_Q7 = 180; + public static final int PPC_REG_Q8 = 181; + public static final int PPC_REG_Q9 = 182; + public static final int PPC_REG_Q10 = 183; + public static final int PPC_REG_Q11 = 184; + public static final int PPC_REG_Q12 = 185; + public static final int PPC_REG_Q13 = 186; + public static final int PPC_REG_Q14 = 187; + public static final int PPC_REG_Q15 = 188; + public static final int PPC_REG_Q16 = 189; + public static final int PPC_REG_Q17 = 190; + public static final int PPC_REG_Q18 = 191; + public static final int PPC_REG_Q19 = 192; + public static final int PPC_REG_Q20 = 193; + public static final int PPC_REG_Q21 = 194; + public static final int PPC_REG_Q22 = 195; + public static final int PPC_REG_Q23 = 196; + public static final int PPC_REG_Q24 = 197; + public static final int PPC_REG_Q25 = 198; + public static final int PPC_REG_Q26 = 199; + public static final int PPC_REG_Q27 = 200; + public static final int PPC_REG_Q28 = 201; + public static final int PPC_REG_Q29 = 202; + public static final int PPC_REG_Q30 = 203; + public static final int PPC_REG_Q31 = 204; + public static final int PPC_REG_RM = 205; + public static final int PPC_REG_CTR8 = 206; + public static final int PPC_REG_LR8 = 207; + public static final int PPC_REG_CR1EQ = 208; + public static final int PPC_REG_X2 = 209; + public static final int PPC_REG_ENDING = 210; + + public static final int PPC_INS_INVALID = 0; + public static final int PPC_INS_ADD = 1; + public static final int PPC_INS_ADDC = 2; + public static final int PPC_INS_ADDE = 3; + public static final int PPC_INS_ADDI = 4; + public static final int PPC_INS_ADDIC = 5; + public static final int PPC_INS_ADDIS = 6; + public static final int PPC_INS_ADDME = 7; + public static final int PPC_INS_ADDZE = 8; + public static final int PPC_INS_AND = 9; + public static final int PPC_INS_ANDC = 10; + public static final int PPC_INS_ANDIS = 11; + public static final int PPC_INS_ANDI = 12; + public static final int PPC_INS_ATTN = 13; + public static final int PPC_INS_B = 14; + public static final int PPC_INS_BA = 15; + public static final int PPC_INS_BC = 16; + public static final int PPC_INS_BCCTR = 17; + public static final int PPC_INS_BCCTRL = 18; + public static final int PPC_INS_BCL = 19; + public static final int PPC_INS_BCLR = 20; + public static final int PPC_INS_BCLRL = 21; + public static final int PPC_INS_BCTR = 22; + public static final int PPC_INS_BCTRL = 23; + public static final int PPC_INS_BCT = 24; + public static final int PPC_INS_BDNZ = 25; + public static final int PPC_INS_BDNZA = 26; + public static final int PPC_INS_BDNZL = 27; + public static final int PPC_INS_BDNZLA = 28; + public static final int PPC_INS_BDNZLR = 29; + public static final int PPC_INS_BDNZLRL = 30; + public static final int PPC_INS_BDZ = 31; + public static final int PPC_INS_BDZA = 32; + public static final int PPC_INS_BDZL = 33; + public static final int PPC_INS_BDZLA = 34; + public static final int PPC_INS_BDZLR = 35; + public static final int PPC_INS_BDZLRL = 36; + public static final int PPC_INS_BL = 37; + public static final int PPC_INS_BLA = 38; + public static final int PPC_INS_BLR = 39; + public static final int PPC_INS_BLRL = 40; + public static final int PPC_INS_BRINC = 41; + public static final int PPC_INS_CMPB = 42; + public static final int PPC_INS_CMPD = 43; + public static final int PPC_INS_CMPDI = 44; + public static final int PPC_INS_CMPLD = 45; + public static final int PPC_INS_CMPLDI = 46; + public static final int PPC_INS_CMPLW = 47; + public static final int PPC_INS_CMPLWI = 48; + public static final int PPC_INS_CMPW = 49; + public static final int PPC_INS_CMPWI = 50; + public static final int PPC_INS_CNTLZD = 51; + public static final int PPC_INS_CNTLZW = 52; + public static final int PPC_INS_CREQV = 53; + public static final int PPC_INS_CRXOR = 54; + public static final int PPC_INS_CRAND = 55; + public static final int PPC_INS_CRANDC = 56; + public static final int PPC_INS_CRNAND = 57; + public static final int PPC_INS_CRNOR = 58; + public static final int PPC_INS_CROR = 59; + public static final int PPC_INS_CRORC = 60; + public static final int PPC_INS_DCBA = 61; + public static final int PPC_INS_DCBF = 62; + public static final int PPC_INS_DCBI = 63; + public static final int PPC_INS_DCBST = 64; + public static final int PPC_INS_DCBT = 65; + public static final int PPC_INS_DCBTST = 66; + public static final int PPC_INS_DCBZ = 67; + public static final int PPC_INS_DCBZL = 68; + public static final int PPC_INS_DCCCI = 69; + public static final int PPC_INS_DIVD = 70; + public static final int PPC_INS_DIVDU = 71; + public static final int PPC_INS_DIVW = 72; + public static final int PPC_INS_DIVWU = 73; + public static final int PPC_INS_DSS = 74; + public static final int PPC_INS_DSSALL = 75; + public static final int PPC_INS_DST = 76; + public static final int PPC_INS_DSTST = 77; + public static final int PPC_INS_DSTSTT = 78; + public static final int PPC_INS_DSTT = 79; + public static final int PPC_INS_EQV = 80; + public static final int PPC_INS_EVABS = 81; + public static final int PPC_INS_EVADDIW = 82; + public static final int PPC_INS_EVADDSMIAAW = 83; + public static final int PPC_INS_EVADDSSIAAW = 84; + public static final int PPC_INS_EVADDUMIAAW = 85; + public static final int PPC_INS_EVADDUSIAAW = 86; + public static final int PPC_INS_EVADDW = 87; + public static final int PPC_INS_EVAND = 88; + public static final int PPC_INS_EVANDC = 89; + public static final int PPC_INS_EVCMPEQ = 90; + public static final int PPC_INS_EVCMPGTS = 91; + public static final int PPC_INS_EVCMPGTU = 92; + public static final int PPC_INS_EVCMPLTS = 93; + public static final int PPC_INS_EVCMPLTU = 94; + public static final int PPC_INS_EVCNTLSW = 95; + public static final int PPC_INS_EVCNTLZW = 96; + public static final int PPC_INS_EVDIVWS = 97; + public static final int PPC_INS_EVDIVWU = 98; + public static final int PPC_INS_EVEQV = 99; + public static final int PPC_INS_EVEXTSB = 100; + public static final int PPC_INS_EVEXTSH = 101; + public static final int PPC_INS_EVLDD = 102; + public static final int PPC_INS_EVLDDX = 103; + public static final int PPC_INS_EVLDH = 104; + public static final int PPC_INS_EVLDHX = 105; + public static final int PPC_INS_EVLDW = 106; + public static final int PPC_INS_EVLDWX = 107; + public static final int PPC_INS_EVLHHESPLAT = 108; + public static final int PPC_INS_EVLHHESPLATX = 109; + public static final int PPC_INS_EVLHHOSSPLAT = 110; + public static final int PPC_INS_EVLHHOSSPLATX = 111; + public static final int PPC_INS_EVLHHOUSPLAT = 112; + public static final int PPC_INS_EVLHHOUSPLATX = 113; + public static final int PPC_INS_EVLWHE = 114; + public static final int PPC_INS_EVLWHEX = 115; + public static final int PPC_INS_EVLWHOS = 116; + public static final int PPC_INS_EVLWHOSX = 117; + public static final int PPC_INS_EVLWHOU = 118; + public static final int PPC_INS_EVLWHOUX = 119; + public static final int PPC_INS_EVLWHSPLAT = 120; + public static final int PPC_INS_EVLWHSPLATX = 121; + public static final int PPC_INS_EVLWWSPLAT = 122; + public static final int PPC_INS_EVLWWSPLATX = 123; + public static final int PPC_INS_EVMERGEHI = 124; + public static final int PPC_INS_EVMERGEHILO = 125; + public static final int PPC_INS_EVMERGELO = 126; + public static final int PPC_INS_EVMERGELOHI = 127; + public static final int PPC_INS_EVMHEGSMFAA = 128; + public static final int PPC_INS_EVMHEGSMFAN = 129; + public static final int PPC_INS_EVMHEGSMIAA = 130; + public static final int PPC_INS_EVMHEGSMIAN = 131; + public static final int PPC_INS_EVMHEGUMIAA = 132; + public static final int PPC_INS_EVMHEGUMIAN = 133; + public static final int PPC_INS_EVMHESMF = 134; + public static final int PPC_INS_EVMHESMFA = 135; + public static final int PPC_INS_EVMHESMFAAW = 136; + public static final int PPC_INS_EVMHESMFANW = 137; + public static final int PPC_INS_EVMHESMI = 138; + public static final int PPC_INS_EVMHESMIA = 139; + public static final int PPC_INS_EVMHESMIAAW = 140; + public static final int PPC_INS_EVMHESMIANW = 141; + public static final int PPC_INS_EVMHESSF = 142; + public static final int PPC_INS_EVMHESSFA = 143; + public static final int PPC_INS_EVMHESSFAAW = 144; + public static final int PPC_INS_EVMHESSFANW = 145; + public static final int PPC_INS_EVMHESSIAAW = 146; + public static final int PPC_INS_EVMHESSIANW = 147; + public static final int PPC_INS_EVMHEUMI = 148; + public static final int PPC_INS_EVMHEUMIA = 149; + public static final int PPC_INS_EVMHEUMIAAW = 150; + public static final int PPC_INS_EVMHEUMIANW = 151; + public static final int PPC_INS_EVMHEUSIAAW = 152; + public static final int PPC_INS_EVMHEUSIANW = 153; + public static final int PPC_INS_EVMHOGSMFAA = 154; + public static final int PPC_INS_EVMHOGSMFAN = 155; + public static final int PPC_INS_EVMHOGSMIAA = 156; + public static final int PPC_INS_EVMHOGSMIAN = 157; + public static final int PPC_INS_EVMHOGUMIAA = 158; + public static final int PPC_INS_EVMHOGUMIAN = 159; + public static final int PPC_INS_EVMHOSMF = 160; + public static final int PPC_INS_EVMHOSMFA = 161; + public static final int PPC_INS_EVMHOSMFAAW = 162; + public static final int PPC_INS_EVMHOSMFANW = 163; + public static final int PPC_INS_EVMHOSMI = 164; + public static final int PPC_INS_EVMHOSMIA = 165; + public static final int PPC_INS_EVMHOSMIAAW = 166; + public static final int PPC_INS_EVMHOSMIANW = 167; + public static final int PPC_INS_EVMHOSSF = 168; + public static final int PPC_INS_EVMHOSSFA = 169; + public static final int PPC_INS_EVMHOSSFAAW = 170; + public static final int PPC_INS_EVMHOSSFANW = 171; + public static final int PPC_INS_EVMHOSSIAAW = 172; + public static final int PPC_INS_EVMHOSSIANW = 173; + public static final int PPC_INS_EVMHOUMI = 174; + public static final int PPC_INS_EVMHOUMIA = 175; + public static final int PPC_INS_EVMHOUMIAAW = 176; + public static final int PPC_INS_EVMHOUMIANW = 177; + public static final int PPC_INS_EVMHOUSIAAW = 178; + public static final int PPC_INS_EVMHOUSIANW = 179; + public static final int PPC_INS_EVMRA = 180; + public static final int PPC_INS_EVMWHSMF = 181; + public static final int PPC_INS_EVMWHSMFA = 182; + public static final int PPC_INS_EVMWHSMI = 183; + public static final int PPC_INS_EVMWHSMIA = 184; + public static final int PPC_INS_EVMWHSSF = 185; + public static final int PPC_INS_EVMWHSSFA = 186; + public static final int PPC_INS_EVMWHUMI = 187; + public static final int PPC_INS_EVMWHUMIA = 188; + public static final int PPC_INS_EVMWLSMIAAW = 189; + public static final int PPC_INS_EVMWLSMIANW = 190; + public static final int PPC_INS_EVMWLSSIAAW = 191; + public static final int PPC_INS_EVMWLSSIANW = 192; + public static final int PPC_INS_EVMWLUMI = 193; + public static final int PPC_INS_EVMWLUMIA = 194; + public static final int PPC_INS_EVMWLUMIAAW = 195; + public static final int PPC_INS_EVMWLUMIANW = 196; + public static final int PPC_INS_EVMWLUSIAAW = 197; + public static final int PPC_INS_EVMWLUSIANW = 198; + public static final int PPC_INS_EVMWSMF = 199; + public static final int PPC_INS_EVMWSMFA = 200; + public static final int PPC_INS_EVMWSMFAA = 201; + public static final int PPC_INS_EVMWSMFAN = 202; + public static final int PPC_INS_EVMWSMI = 203; + public static final int PPC_INS_EVMWSMIA = 204; + public static final int PPC_INS_EVMWSMIAA = 205; + public static final int PPC_INS_EVMWSMIAN = 206; + public static final int PPC_INS_EVMWSSF = 207; + public static final int PPC_INS_EVMWSSFA = 208; + public static final int PPC_INS_EVMWSSFAA = 209; + public static final int PPC_INS_EVMWSSFAN = 210; + public static final int PPC_INS_EVMWUMI = 211; + public static final int PPC_INS_EVMWUMIA = 212; + public static final int PPC_INS_EVMWUMIAA = 213; + public static final int PPC_INS_EVMWUMIAN = 214; + public static final int PPC_INS_EVNAND = 215; + public static final int PPC_INS_EVNEG = 216; + public static final int PPC_INS_EVNOR = 217; + public static final int PPC_INS_EVOR = 218; + public static final int PPC_INS_EVORC = 219; + public static final int PPC_INS_EVRLW = 220; + public static final int PPC_INS_EVRLWI = 221; + public static final int PPC_INS_EVRNDW = 222; + public static final int PPC_INS_EVSLW = 223; + public static final int PPC_INS_EVSLWI = 224; + public static final int PPC_INS_EVSPLATFI = 225; + public static final int PPC_INS_EVSPLATI = 226; + public static final int PPC_INS_EVSRWIS = 227; + public static final int PPC_INS_EVSRWIU = 228; + public static final int PPC_INS_EVSRWS = 229; + public static final int PPC_INS_EVSRWU = 230; + public static final int PPC_INS_EVSTDD = 231; + public static final int PPC_INS_EVSTDDX = 232; + public static final int PPC_INS_EVSTDH = 233; + public static final int PPC_INS_EVSTDHX = 234; + public static final int PPC_INS_EVSTDW = 235; + public static final int PPC_INS_EVSTDWX = 236; + public static final int PPC_INS_EVSTWHE = 237; + public static final int PPC_INS_EVSTWHEX = 238; + public static final int PPC_INS_EVSTWHO = 239; + public static final int PPC_INS_EVSTWHOX = 240; + public static final int PPC_INS_EVSTWWE = 241; + public static final int PPC_INS_EVSTWWEX = 242; + public static final int PPC_INS_EVSTWWO = 243; + public static final int PPC_INS_EVSTWWOX = 244; + public static final int PPC_INS_EVSUBFSMIAAW = 245; + public static final int PPC_INS_EVSUBFSSIAAW = 246; + public static final int PPC_INS_EVSUBFUMIAAW = 247; + public static final int PPC_INS_EVSUBFUSIAAW = 248; + public static final int PPC_INS_EVSUBFW = 249; + public static final int PPC_INS_EVSUBIFW = 250; + public static final int PPC_INS_EVXOR = 251; + public static final int PPC_INS_EXTSB = 252; + public static final int PPC_INS_EXTSH = 253; + public static final int PPC_INS_EXTSW = 254; + public static final int PPC_INS_EIEIO = 255; + public static final int PPC_INS_FABS = 256; + public static final int PPC_INS_FADD = 257; + public static final int PPC_INS_FADDS = 258; + public static final int PPC_INS_FCFID = 259; + public static final int PPC_INS_FCFIDS = 260; + public static final int PPC_INS_FCFIDU = 261; + public static final int PPC_INS_FCFIDUS = 262; + public static final int PPC_INS_FCMPU = 263; + public static final int PPC_INS_FCPSGN = 264; + public static final int PPC_INS_FCTID = 265; + public static final int PPC_INS_FCTIDUZ = 266; + public static final int PPC_INS_FCTIDZ = 267; + public static final int PPC_INS_FCTIW = 268; + public static final int PPC_INS_FCTIWUZ = 269; + public static final int PPC_INS_FCTIWZ = 270; + public static final int PPC_INS_FDIV = 271; + public static final int PPC_INS_FDIVS = 272; + public static final int PPC_INS_FMADD = 273; + public static final int PPC_INS_FMADDS = 274; + public static final int PPC_INS_FMR = 275; + public static final int PPC_INS_FMSUB = 276; + public static final int PPC_INS_FMSUBS = 277; + public static final int PPC_INS_FMUL = 278; + public static final int PPC_INS_FMULS = 279; + public static final int PPC_INS_FNABS = 280; + public static final int PPC_INS_FNEG = 281; + public static final int PPC_INS_FNMADD = 282; + public static final int PPC_INS_FNMADDS = 283; + public static final int PPC_INS_FNMSUB = 284; + public static final int PPC_INS_FNMSUBS = 285; + public static final int PPC_INS_FRE = 286; + public static final int PPC_INS_FRES = 287; + public static final int PPC_INS_FRIM = 288; + public static final int PPC_INS_FRIN = 289; + public static final int PPC_INS_FRIP = 290; + public static final int PPC_INS_FRIZ = 291; + public static final int PPC_INS_FRSP = 292; + public static final int PPC_INS_FRSQRTE = 293; + public static final int PPC_INS_FRSQRTES = 294; + public static final int PPC_INS_FSEL = 295; + public static final int PPC_INS_FSQRT = 296; + public static final int PPC_INS_FSQRTS = 297; + public static final int PPC_INS_FSUB = 298; + public static final int PPC_INS_FSUBS = 299; + public static final int PPC_INS_ICBI = 300; + public static final int PPC_INS_ICBT = 301; + public static final int PPC_INS_ICCCI = 302; + public static final int PPC_INS_ISEL = 303; + public static final int PPC_INS_ISYNC = 304; + public static final int PPC_INS_LA = 305; + public static final int PPC_INS_LBZ = 306; + public static final int PPC_INS_LBZCIX = 307; + public static final int PPC_INS_LBZU = 308; + public static final int PPC_INS_LBZUX = 309; + public static final int PPC_INS_LBZX = 310; + public static final int PPC_INS_LD = 311; + public static final int PPC_INS_LDARX = 312; + public static final int PPC_INS_LDBRX = 313; + public static final int PPC_INS_LDCIX = 314; + public static final int PPC_INS_LDU = 315; + public static final int PPC_INS_LDUX = 316; + public static final int PPC_INS_LDX = 317; + public static final int PPC_INS_LFD = 318; + public static final int PPC_INS_LFDU = 319; + public static final int PPC_INS_LFDUX = 320; + public static final int PPC_INS_LFDX = 321; + public static final int PPC_INS_LFIWAX = 322; + public static final int PPC_INS_LFIWZX = 323; + public static final int PPC_INS_LFS = 324; + public static final int PPC_INS_LFSU = 325; + public static final int PPC_INS_LFSUX = 326; + public static final int PPC_INS_LFSX = 327; + public static final int PPC_INS_LHA = 328; + public static final int PPC_INS_LHAU = 329; + public static final int PPC_INS_LHAUX = 330; + public static final int PPC_INS_LHAX = 331; + public static final int PPC_INS_LHBRX = 332; + public static final int PPC_INS_LHZ = 333; + public static final int PPC_INS_LHZCIX = 334; + public static final int PPC_INS_LHZU = 335; + public static final int PPC_INS_LHZUX = 336; + public static final int PPC_INS_LHZX = 337; + public static final int PPC_INS_LI = 338; + public static final int PPC_INS_LIS = 339; + public static final int PPC_INS_LMW = 340; + public static final int PPC_INS_LSWI = 341; + public static final int PPC_INS_LVEBX = 342; + public static final int PPC_INS_LVEHX = 343; + public static final int PPC_INS_LVEWX = 344; + public static final int PPC_INS_LVSL = 345; + public static final int PPC_INS_LVSR = 346; + public static final int PPC_INS_LVX = 347; + public static final int PPC_INS_LVXL = 348; + public static final int PPC_INS_LWA = 349; + public static final int PPC_INS_LWARX = 350; + public static final int PPC_INS_LWAUX = 351; + public static final int PPC_INS_LWAX = 352; + public static final int PPC_INS_LWBRX = 353; + public static final int PPC_INS_LWZ = 354; + public static final int PPC_INS_LWZCIX = 355; + public static final int PPC_INS_LWZU = 356; + public static final int PPC_INS_LWZUX = 357; + public static final int PPC_INS_LWZX = 358; + public static final int PPC_INS_LXSDX = 359; + public static final int PPC_INS_LXVD2X = 360; + public static final int PPC_INS_LXVDSX = 361; + public static final int PPC_INS_LXVW4X = 362; + public static final int PPC_INS_MBAR = 363; + public static final int PPC_INS_MCRF = 364; + public static final int PPC_INS_MCRFS = 365; + public static final int PPC_INS_MFCR = 366; + public static final int PPC_INS_MFCTR = 367; + public static final int PPC_INS_MFDCR = 368; + public static final int PPC_INS_MFFS = 369; + public static final int PPC_INS_MFLR = 370; + public static final int PPC_INS_MFMSR = 371; + public static final int PPC_INS_MFOCRF = 372; + public static final int PPC_INS_MFSPR = 373; + public static final int PPC_INS_MFSR = 374; + public static final int PPC_INS_MFSRIN = 375; + public static final int PPC_INS_MFTB = 376; + public static final int PPC_INS_MFVSCR = 377; + public static final int PPC_INS_MSYNC = 378; + public static final int PPC_INS_MTCRF = 379; + public static final int PPC_INS_MTCTR = 380; + public static final int PPC_INS_MTDCR = 381; + public static final int PPC_INS_MTFSB0 = 382; + public static final int PPC_INS_MTFSB1 = 383; + public static final int PPC_INS_MTFSF = 384; + public static final int PPC_INS_MTFSFI = 385; + public static final int PPC_INS_MTLR = 386; + public static final int PPC_INS_MTMSR = 387; + public static final int PPC_INS_MTMSRD = 388; + public static final int PPC_INS_MTOCRF = 389; + public static final int PPC_INS_MTSPR = 390; + public static final int PPC_INS_MTSR = 391; + public static final int PPC_INS_MTSRIN = 392; + public static final int PPC_INS_MTVSCR = 393; + public static final int PPC_INS_MULHD = 394; + public static final int PPC_INS_MULHDU = 395; + public static final int PPC_INS_MULHW = 396; + public static final int PPC_INS_MULHWU = 397; + public static final int PPC_INS_MULLD = 398; + public static final int PPC_INS_MULLI = 399; + public static final int PPC_INS_MULLW = 400; + public static final int PPC_INS_NAND = 401; + public static final int PPC_INS_NEG = 402; + public static final int PPC_INS_NOP = 403; + public static final int PPC_INS_ORI = 404; + public static final int PPC_INS_NOR = 405; + public static final int PPC_INS_OR = 406; + public static final int PPC_INS_ORC = 407; + public static final int PPC_INS_ORIS = 408; + public static final int PPC_INS_POPCNTD = 409; + public static final int PPC_INS_POPCNTW = 410; + public static final int PPC_INS_QVALIGNI = 411; + public static final int PPC_INS_QVESPLATI = 412; + public static final int PPC_INS_QVFABS = 413; + public static final int PPC_INS_QVFADD = 414; + public static final int PPC_INS_QVFADDS = 415; + public static final int PPC_INS_QVFCFID = 416; + public static final int PPC_INS_QVFCFIDS = 417; + public static final int PPC_INS_QVFCFIDU = 418; + public static final int PPC_INS_QVFCFIDUS = 419; + public static final int PPC_INS_QVFCMPEQ = 420; + public static final int PPC_INS_QVFCMPGT = 421; + public static final int PPC_INS_QVFCMPLT = 422; + public static final int PPC_INS_QVFCPSGN = 423; + public static final int PPC_INS_QVFCTID = 424; + public static final int PPC_INS_QVFCTIDU = 425; + public static final int PPC_INS_QVFCTIDUZ = 426; + public static final int PPC_INS_QVFCTIDZ = 427; + public static final int PPC_INS_QVFCTIW = 428; + public static final int PPC_INS_QVFCTIWU = 429; + public static final int PPC_INS_QVFCTIWUZ = 430; + public static final int PPC_INS_QVFCTIWZ = 431; + public static final int PPC_INS_QVFLOGICAL = 432; + public static final int PPC_INS_QVFMADD = 433; + public static final int PPC_INS_QVFMADDS = 434; + public static final int PPC_INS_QVFMR = 435; + public static final int PPC_INS_QVFMSUB = 436; + public static final int PPC_INS_QVFMSUBS = 437; + public static final int PPC_INS_QVFMUL = 438; + public static final int PPC_INS_QVFMULS = 439; + public static final int PPC_INS_QVFNABS = 440; + public static final int PPC_INS_QVFNEG = 441; + public static final int PPC_INS_QVFNMADD = 442; + public static final int PPC_INS_QVFNMADDS = 443; + public static final int PPC_INS_QVFNMSUB = 444; + public static final int PPC_INS_QVFNMSUBS = 445; + public static final int PPC_INS_QVFPERM = 446; + public static final int PPC_INS_QVFRE = 447; + public static final int PPC_INS_QVFRES = 448; + public static final int PPC_INS_QVFRIM = 449; + public static final int PPC_INS_QVFRIN = 450; + public static final int PPC_INS_QVFRIP = 451; + public static final int PPC_INS_QVFRIZ = 452; + public static final int PPC_INS_QVFRSP = 453; + public static final int PPC_INS_QVFRSQRTE = 454; + public static final int PPC_INS_QVFRSQRTES = 455; + public static final int PPC_INS_QVFSEL = 456; + public static final int PPC_INS_QVFSUB = 457; + public static final int PPC_INS_QVFSUBS = 458; + public static final int PPC_INS_QVFTSTNAN = 459; + public static final int PPC_INS_QVFXMADD = 460; + public static final int PPC_INS_QVFXMADDS = 461; + public static final int PPC_INS_QVFXMUL = 462; + public static final int PPC_INS_QVFXMULS = 463; + public static final int PPC_INS_QVFXXCPNMADD = 464; + public static final int PPC_INS_QVFXXCPNMADDS = 465; + public static final int PPC_INS_QVFXXMADD = 466; + public static final int PPC_INS_QVFXXMADDS = 467; + public static final int PPC_INS_QVFXXNPMADD = 468; + public static final int PPC_INS_QVFXXNPMADDS = 469; + public static final int PPC_INS_QVGPCI = 470; + public static final int PPC_INS_QVLFCDUX = 471; + public static final int PPC_INS_QVLFCDUXA = 472; + public static final int PPC_INS_QVLFCDX = 473; + public static final int PPC_INS_QVLFCDXA = 474; + public static final int PPC_INS_QVLFCSUX = 475; + public static final int PPC_INS_QVLFCSUXA = 476; + public static final int PPC_INS_QVLFCSX = 477; + public static final int PPC_INS_QVLFCSXA = 478; + public static final int PPC_INS_QVLFDUX = 479; + public static final int PPC_INS_QVLFDUXA = 480; + public static final int PPC_INS_QVLFDX = 481; + public static final int PPC_INS_QVLFDXA = 482; + public static final int PPC_INS_QVLFIWAX = 483; + public static final int PPC_INS_QVLFIWAXA = 484; + public static final int PPC_INS_QVLFIWZX = 485; + public static final int PPC_INS_QVLFIWZXA = 486; + public static final int PPC_INS_QVLFSUX = 487; + public static final int PPC_INS_QVLFSUXA = 488; + public static final int PPC_INS_QVLFSX = 489; + public static final int PPC_INS_QVLFSXA = 490; + public static final int PPC_INS_QVLPCLDX = 491; + public static final int PPC_INS_QVLPCLSX = 492; + public static final int PPC_INS_QVLPCRDX = 493; + public static final int PPC_INS_QVLPCRSX = 494; + public static final int PPC_INS_QVSTFCDUX = 495; + public static final int PPC_INS_QVSTFCDUXA = 496; + public static final int PPC_INS_QVSTFCDUXI = 497; + public static final int PPC_INS_QVSTFCDUXIA = 498; + public static final int PPC_INS_QVSTFCDX = 499; + public static final int PPC_INS_QVSTFCDXA = 500; + public static final int PPC_INS_QVSTFCDXI = 501; + public static final int PPC_INS_QVSTFCDXIA = 502; + public static final int PPC_INS_QVSTFCSUX = 503; + public static final int PPC_INS_QVSTFCSUXA = 504; + public static final int PPC_INS_QVSTFCSUXI = 505; + public static final int PPC_INS_QVSTFCSUXIA = 506; + public static final int PPC_INS_QVSTFCSX = 507; + public static final int PPC_INS_QVSTFCSXA = 508; + public static final int PPC_INS_QVSTFCSXI = 509; + public static final int PPC_INS_QVSTFCSXIA = 510; + public static final int PPC_INS_QVSTFDUX = 511; + public static final int PPC_INS_QVSTFDUXA = 512; + public static final int PPC_INS_QVSTFDUXI = 513; + public static final int PPC_INS_QVSTFDUXIA = 514; + public static final int PPC_INS_QVSTFDX = 515; + public static final int PPC_INS_QVSTFDXA = 516; + public static final int PPC_INS_QVSTFDXI = 517; + public static final int PPC_INS_QVSTFDXIA = 518; + public static final int PPC_INS_QVSTFIWX = 519; + public static final int PPC_INS_QVSTFIWXA = 520; + public static final int PPC_INS_QVSTFSUX = 521; + public static final int PPC_INS_QVSTFSUXA = 522; + public static final int PPC_INS_QVSTFSUXI = 523; + public static final int PPC_INS_QVSTFSUXIA = 524; + public static final int PPC_INS_QVSTFSX = 525; + public static final int PPC_INS_QVSTFSXA = 526; + public static final int PPC_INS_QVSTFSXI = 527; + public static final int PPC_INS_QVSTFSXIA = 528; + public static final int PPC_INS_RFCI = 529; + public static final int PPC_INS_RFDI = 530; + public static final int PPC_INS_RFI = 531; + public static final int PPC_INS_RFID = 532; + public static final int PPC_INS_RFMCI = 533; + public static final int PPC_INS_RLDCL = 534; + public static final int PPC_INS_RLDCR = 535; + public static final int PPC_INS_RLDIC = 536; + public static final int PPC_INS_RLDICL = 537; + public static final int PPC_INS_RLDICR = 538; + public static final int PPC_INS_RLDIMI = 539; + public static final int PPC_INS_RLWIMI = 540; + public static final int PPC_INS_RLWINM = 541; + public static final int PPC_INS_RLWNM = 542; + public static final int PPC_INS_SC = 543; + public static final int PPC_INS_SLBIA = 544; + public static final int PPC_INS_SLBIE = 545; + public static final int PPC_INS_SLBMFEE = 546; + public static final int PPC_INS_SLBMTE = 547; + public static final int PPC_INS_SLD = 548; + public static final int PPC_INS_SLW = 549; + public static final int PPC_INS_SRAD = 550; + public static final int PPC_INS_SRADI = 551; + public static final int PPC_INS_SRAW = 552; + public static final int PPC_INS_SRAWI = 553; + public static final int PPC_INS_SRD = 554; + public static final int PPC_INS_SRW = 555; + public static final int PPC_INS_STB = 556; + public static final int PPC_INS_STBCIX = 557; + public static final int PPC_INS_STBU = 558; + public static final int PPC_INS_STBUX = 559; + public static final int PPC_INS_STBX = 560; + public static final int PPC_INS_STD = 561; + public static final int PPC_INS_STDBRX = 562; + public static final int PPC_INS_STDCIX = 563; + public static final int PPC_INS_STDCX = 564; + public static final int PPC_INS_STDU = 565; + public static final int PPC_INS_STDUX = 566; + public static final int PPC_INS_STDX = 567; + public static final int PPC_INS_STFD = 568; + public static final int PPC_INS_STFDU = 569; + public static final int PPC_INS_STFDUX = 570; + public static final int PPC_INS_STFDX = 571; + public static final int PPC_INS_STFIWX = 572; + public static final int PPC_INS_STFS = 573; + public static final int PPC_INS_STFSU = 574; + public static final int PPC_INS_STFSUX = 575; + public static final int PPC_INS_STFSX = 576; + public static final int PPC_INS_STH = 577; + public static final int PPC_INS_STHBRX = 578; + public static final int PPC_INS_STHCIX = 579; + public static final int PPC_INS_STHU = 580; + public static final int PPC_INS_STHUX = 581; + public static final int PPC_INS_STHX = 582; + public static final int PPC_INS_STMW = 583; + public static final int PPC_INS_STSWI = 584; + public static final int PPC_INS_STVEBX = 585; + public static final int PPC_INS_STVEHX = 586; + public static final int PPC_INS_STVEWX = 587; + public static final int PPC_INS_STVX = 588; + public static final int PPC_INS_STVXL = 589; + public static final int PPC_INS_STW = 590; + public static final int PPC_INS_STWBRX = 591; + public static final int PPC_INS_STWCIX = 592; + public static final int PPC_INS_STWCX = 593; + public static final int PPC_INS_STWU = 594; + public static final int PPC_INS_STWUX = 595; + public static final int PPC_INS_STWX = 596; + public static final int PPC_INS_STXSDX = 597; + public static final int PPC_INS_STXVD2X = 598; + public static final int PPC_INS_STXVW4X = 599; + public static final int PPC_INS_SUBF = 600; + public static final int PPC_INS_SUBFC = 601; + public static final int PPC_INS_SUBFE = 602; + public static final int PPC_INS_SUBFIC = 603; + public static final int PPC_INS_SUBFME = 604; + public static final int PPC_INS_SUBFZE = 605; + public static final int PPC_INS_SYNC = 606; + public static final int PPC_INS_TD = 607; + public static final int PPC_INS_TDI = 608; + public static final int PPC_INS_TLBIA = 609; + public static final int PPC_INS_TLBIE = 610; + public static final int PPC_INS_TLBIEL = 611; + public static final int PPC_INS_TLBIVAX = 612; + public static final int PPC_INS_TLBLD = 613; + public static final int PPC_INS_TLBLI = 614; + public static final int PPC_INS_TLBRE = 615; + public static final int PPC_INS_TLBSX = 616; + public static final int PPC_INS_TLBSYNC = 617; + public static final int PPC_INS_TLBWE = 618; + public static final int PPC_INS_TRAP = 619; + public static final int PPC_INS_TW = 620; + public static final int PPC_INS_TWI = 621; + public static final int PPC_INS_VADDCUW = 622; + public static final int PPC_INS_VADDFP = 623; + public static final int PPC_INS_VADDSBS = 624; + public static final int PPC_INS_VADDSHS = 625; + public static final int PPC_INS_VADDSWS = 626; + public static final int PPC_INS_VADDUBM = 627; + public static final int PPC_INS_VADDUBS = 628; + public static final int PPC_INS_VADDUDM = 629; + public static final int PPC_INS_VADDUHM = 630; + public static final int PPC_INS_VADDUHS = 631; + public static final int PPC_INS_VADDUWM = 632; + public static final int PPC_INS_VADDUWS = 633; + public static final int PPC_INS_VAND = 634; + public static final int PPC_INS_VANDC = 635; + public static final int PPC_INS_VAVGSB = 636; + public static final int PPC_INS_VAVGSH = 637; + public static final int PPC_INS_VAVGSW = 638; + public static final int PPC_INS_VAVGUB = 639; + public static final int PPC_INS_VAVGUH = 640; + public static final int PPC_INS_VAVGUW = 641; + public static final int PPC_INS_VCFSX = 642; + public static final int PPC_INS_VCFUX = 643; + public static final int PPC_INS_VCLZB = 644; + public static final int PPC_INS_VCLZD = 645; + public static final int PPC_INS_VCLZH = 646; + public static final int PPC_INS_VCLZW = 647; + public static final int PPC_INS_VCMPBFP = 648; + public static final int PPC_INS_VCMPEQFP = 649; + public static final int PPC_INS_VCMPEQUB = 650; + public static final int PPC_INS_VCMPEQUD = 651; + public static final int PPC_INS_VCMPEQUH = 652; + public static final int PPC_INS_VCMPEQUW = 653; + public static final int PPC_INS_VCMPGEFP = 654; + public static final int PPC_INS_VCMPGTFP = 655; + public static final int PPC_INS_VCMPGTSB = 656; + public static final int PPC_INS_VCMPGTSD = 657; + public static final int PPC_INS_VCMPGTSH = 658; + public static final int PPC_INS_VCMPGTSW = 659; + public static final int PPC_INS_VCMPGTUB = 660; + public static final int PPC_INS_VCMPGTUD = 661; + public static final int PPC_INS_VCMPGTUH = 662; + public static final int PPC_INS_VCMPGTUW = 663; + public static final int PPC_INS_VCTSXS = 664; + public static final int PPC_INS_VCTUXS = 665; + public static final int PPC_INS_VEQV = 666; + public static final int PPC_INS_VEXPTEFP = 667; + public static final int PPC_INS_VLOGEFP = 668; + public static final int PPC_INS_VMADDFP = 669; + public static final int PPC_INS_VMAXFP = 670; + public static final int PPC_INS_VMAXSB = 671; + public static final int PPC_INS_VMAXSD = 672; + public static final int PPC_INS_VMAXSH = 673; + public static final int PPC_INS_VMAXSW = 674; + public static final int PPC_INS_VMAXUB = 675; + public static final int PPC_INS_VMAXUD = 676; + public static final int PPC_INS_VMAXUH = 677; + public static final int PPC_INS_VMAXUW = 678; + public static final int PPC_INS_VMHADDSHS = 679; + public static final int PPC_INS_VMHRADDSHS = 680; + public static final int PPC_INS_VMINUD = 681; + public static final int PPC_INS_VMINFP = 682; + public static final int PPC_INS_VMINSB = 683; + public static final int PPC_INS_VMINSD = 684; + public static final int PPC_INS_VMINSH = 685; + public static final int PPC_INS_VMINSW = 686; + public static final int PPC_INS_VMINUB = 687; + public static final int PPC_INS_VMINUH = 688; + public static final int PPC_INS_VMINUW = 689; + public static final int PPC_INS_VMLADDUHM = 690; + public static final int PPC_INS_VMRGHB = 691; + public static final int PPC_INS_VMRGHH = 692; + public static final int PPC_INS_VMRGHW = 693; + public static final int PPC_INS_VMRGLB = 694; + public static final int PPC_INS_VMRGLH = 695; + public static final int PPC_INS_VMRGLW = 696; + public static final int PPC_INS_VMSUMMBM = 697; + public static final int PPC_INS_VMSUMSHM = 698; + public static final int PPC_INS_VMSUMSHS = 699; + public static final int PPC_INS_VMSUMUBM = 700; + public static final int PPC_INS_VMSUMUHM = 701; + public static final int PPC_INS_VMSUMUHS = 702; + public static final int PPC_INS_VMULESB = 703; + public static final int PPC_INS_VMULESH = 704; + public static final int PPC_INS_VMULESW = 705; + public static final int PPC_INS_VMULEUB = 706; + public static final int PPC_INS_VMULEUH = 707; + public static final int PPC_INS_VMULEUW = 708; + public static final int PPC_INS_VMULOSB = 709; + public static final int PPC_INS_VMULOSH = 710; + public static final int PPC_INS_VMULOSW = 711; + public static final int PPC_INS_VMULOUB = 712; + public static final int PPC_INS_VMULOUH = 713; + public static final int PPC_INS_VMULOUW = 714; + public static final int PPC_INS_VMULUWM = 715; + public static final int PPC_INS_VNAND = 716; + public static final int PPC_INS_VNMSUBFP = 717; + public static final int PPC_INS_VNOR = 718; + public static final int PPC_INS_VOR = 719; + public static final int PPC_INS_VORC = 720; + public static final int PPC_INS_VPERM = 721; + public static final int PPC_INS_VPKPX = 722; + public static final int PPC_INS_VPKSHSS = 723; + public static final int PPC_INS_VPKSHUS = 724; + public static final int PPC_INS_VPKSWSS = 725; + public static final int PPC_INS_VPKSWUS = 726; + public static final int PPC_INS_VPKUHUM = 727; + public static final int PPC_INS_VPKUHUS = 728; + public static final int PPC_INS_VPKUWUM = 729; + public static final int PPC_INS_VPKUWUS = 730; + public static final int PPC_INS_VPOPCNTB = 731; + public static final int PPC_INS_VPOPCNTD = 732; + public static final int PPC_INS_VPOPCNTH = 733; + public static final int PPC_INS_VPOPCNTW = 734; + public static final int PPC_INS_VREFP = 735; + public static final int PPC_INS_VRFIM = 736; + public static final int PPC_INS_VRFIN = 737; + public static final int PPC_INS_VRFIP = 738; + public static final int PPC_INS_VRFIZ = 739; + public static final int PPC_INS_VRLB = 740; + public static final int PPC_INS_VRLD = 741; + public static final int PPC_INS_VRLH = 742; + public static final int PPC_INS_VRLW = 743; + public static final int PPC_INS_VRSQRTEFP = 744; + public static final int PPC_INS_VSEL = 745; + public static final int PPC_INS_VSL = 746; + public static final int PPC_INS_VSLB = 747; + public static final int PPC_INS_VSLD = 748; + public static final int PPC_INS_VSLDOI = 749; + public static final int PPC_INS_VSLH = 750; + public static final int PPC_INS_VSLO = 751; + public static final int PPC_INS_VSLW = 752; + public static final int PPC_INS_VSPLTB = 753; + public static final int PPC_INS_VSPLTH = 754; + public static final int PPC_INS_VSPLTISB = 755; + public static final int PPC_INS_VSPLTISH = 756; + public static final int PPC_INS_VSPLTISW = 757; + public static final int PPC_INS_VSPLTW = 758; + public static final int PPC_INS_VSR = 759; + public static final int PPC_INS_VSRAB = 760; + public static final int PPC_INS_VSRAD = 761; + public static final int PPC_INS_VSRAH = 762; + public static final int PPC_INS_VSRAW = 763; + public static final int PPC_INS_VSRB = 764; + public static final int PPC_INS_VSRD = 765; + public static final int PPC_INS_VSRH = 766; + public static final int PPC_INS_VSRO = 767; + public static final int PPC_INS_VSRW = 768; + public static final int PPC_INS_VSUBCUW = 769; + public static final int PPC_INS_VSUBFP = 770; + public static final int PPC_INS_VSUBSBS = 771; + public static final int PPC_INS_VSUBSHS = 772; + public static final int PPC_INS_VSUBSWS = 773; + public static final int PPC_INS_VSUBUBM = 774; + public static final int PPC_INS_VSUBUBS = 775; + public static final int PPC_INS_VSUBUDM = 776; + public static final int PPC_INS_VSUBUHM = 777; + public static final int PPC_INS_VSUBUHS = 778; + public static final int PPC_INS_VSUBUWM = 779; + public static final int PPC_INS_VSUBUWS = 780; + public static final int PPC_INS_VSUM2SWS = 781; + public static final int PPC_INS_VSUM4SBS = 782; + public static final int PPC_INS_VSUM4SHS = 783; + public static final int PPC_INS_VSUM4UBS = 784; + public static final int PPC_INS_VSUMSWS = 785; + public static final int PPC_INS_VUPKHPX = 786; + public static final int PPC_INS_VUPKHSB = 787; + public static final int PPC_INS_VUPKHSH = 788; + public static final int PPC_INS_VUPKLPX = 789; + public static final int PPC_INS_VUPKLSB = 790; + public static final int PPC_INS_VUPKLSH = 791; + public static final int PPC_INS_VXOR = 792; + public static final int PPC_INS_WAIT = 793; + public static final int PPC_INS_WRTEE = 794; + public static final int PPC_INS_WRTEEI = 795; + public static final int PPC_INS_XOR = 796; + public static final int PPC_INS_XORI = 797; + public static final int PPC_INS_XORIS = 798; + public static final int PPC_INS_XSABSDP = 799; + public static final int PPC_INS_XSADDDP = 800; + public static final int PPC_INS_XSCMPODP = 801; + public static final int PPC_INS_XSCMPUDP = 802; + public static final int PPC_INS_XSCPSGNDP = 803; + public static final int PPC_INS_XSCVDPSP = 804; + public static final int PPC_INS_XSCVDPSXDS = 805; + public static final int PPC_INS_XSCVDPSXWS = 806; + public static final int PPC_INS_XSCVDPUXDS = 807; + public static final int PPC_INS_XSCVDPUXWS = 808; + public static final int PPC_INS_XSCVSPDP = 809; + public static final int PPC_INS_XSCVSXDDP = 810; + public static final int PPC_INS_XSCVUXDDP = 811; + public static final int PPC_INS_XSDIVDP = 812; + public static final int PPC_INS_XSMADDADP = 813; + public static final int PPC_INS_XSMADDMDP = 814; + public static final int PPC_INS_XSMAXDP = 815; + public static final int PPC_INS_XSMINDP = 816; + public static final int PPC_INS_XSMSUBADP = 817; + public static final int PPC_INS_XSMSUBMDP = 818; + public static final int PPC_INS_XSMULDP = 819; + public static final int PPC_INS_XSNABSDP = 820; + public static final int PPC_INS_XSNEGDP = 821; + public static final int PPC_INS_XSNMADDADP = 822; + public static final int PPC_INS_XSNMADDMDP = 823; + public static final int PPC_INS_XSNMSUBADP = 824; + public static final int PPC_INS_XSNMSUBMDP = 825; + public static final int PPC_INS_XSRDPI = 826; + public static final int PPC_INS_XSRDPIC = 827; + public static final int PPC_INS_XSRDPIM = 828; + public static final int PPC_INS_XSRDPIP = 829; + public static final int PPC_INS_XSRDPIZ = 830; + public static final int PPC_INS_XSREDP = 831; + public static final int PPC_INS_XSRSQRTEDP = 832; + public static final int PPC_INS_XSSQRTDP = 833; + public static final int PPC_INS_XSSUBDP = 834; + public static final int PPC_INS_XSTDIVDP = 835; + public static final int PPC_INS_XSTSQRTDP = 836; + public static final int PPC_INS_XVABSDP = 837; + public static final int PPC_INS_XVABSSP = 838; + public static final int PPC_INS_XVADDDP = 839; + public static final int PPC_INS_XVADDSP = 840; + public static final int PPC_INS_XVCMPEQDP = 841; + public static final int PPC_INS_XVCMPEQSP = 842; + public static final int PPC_INS_XVCMPGEDP = 843; + public static final int PPC_INS_XVCMPGESP = 844; + public static final int PPC_INS_XVCMPGTDP = 845; + public static final int PPC_INS_XVCMPGTSP = 846; + public static final int PPC_INS_XVCPSGNDP = 847; + public static final int PPC_INS_XVCPSGNSP = 848; + public static final int PPC_INS_XVCVDPSP = 849; + public static final int PPC_INS_XVCVDPSXDS = 850; + public static final int PPC_INS_XVCVDPSXWS = 851; + public static final int PPC_INS_XVCVDPUXDS = 852; + public static final int PPC_INS_XVCVDPUXWS = 853; + public static final int PPC_INS_XVCVSPDP = 854; + public static final int PPC_INS_XVCVSPSXDS = 855; + public static final int PPC_INS_XVCVSPSXWS = 856; + public static final int PPC_INS_XVCVSPUXDS = 857; + public static final int PPC_INS_XVCVSPUXWS = 858; + public static final int PPC_INS_XVCVSXDDP = 859; + public static final int PPC_INS_XVCVSXDSP = 860; + public static final int PPC_INS_XVCVSXWDP = 861; + public static final int PPC_INS_XVCVSXWSP = 862; + public static final int PPC_INS_XVCVUXDDP = 863; + public static final int PPC_INS_XVCVUXDSP = 864; + public static final int PPC_INS_XVCVUXWDP = 865; + public static final int PPC_INS_XVCVUXWSP = 866; + public static final int PPC_INS_XVDIVDP = 867; + public static final int PPC_INS_XVDIVSP = 868; + public static final int PPC_INS_XVMADDADP = 869; + public static final int PPC_INS_XVMADDASP = 870; + public static final int PPC_INS_XVMADDMDP = 871; + public static final int PPC_INS_XVMADDMSP = 872; + public static final int PPC_INS_XVMAXDP = 873; + public static final int PPC_INS_XVMAXSP = 874; + public static final int PPC_INS_XVMINDP = 875; + public static final int PPC_INS_XVMINSP = 876; + public static final int PPC_INS_XVMSUBADP = 877; + public static final int PPC_INS_XVMSUBASP = 878; + public static final int PPC_INS_XVMSUBMDP = 879; + public static final int PPC_INS_XVMSUBMSP = 880; + public static final int PPC_INS_XVMULDP = 881; + public static final int PPC_INS_XVMULSP = 882; + public static final int PPC_INS_XVNABSDP = 883; + public static final int PPC_INS_XVNABSSP = 884; + public static final int PPC_INS_XVNEGDP = 885; + public static final int PPC_INS_XVNEGSP = 886; + public static final int PPC_INS_XVNMADDADP = 887; + public static final int PPC_INS_XVNMADDASP = 888; + public static final int PPC_INS_XVNMADDMDP = 889; + public static final int PPC_INS_XVNMADDMSP = 890; + public static final int PPC_INS_XVNMSUBADP = 891; + public static final int PPC_INS_XVNMSUBASP = 892; + public static final int PPC_INS_XVNMSUBMDP = 893; + public static final int PPC_INS_XVNMSUBMSP = 894; + public static final int PPC_INS_XVRDPI = 895; + public static final int PPC_INS_XVRDPIC = 896; + public static final int PPC_INS_XVRDPIM = 897; + public static final int PPC_INS_XVRDPIP = 898; + public static final int PPC_INS_XVRDPIZ = 899; + public static final int PPC_INS_XVREDP = 900; + public static final int PPC_INS_XVRESP = 901; + public static final int PPC_INS_XVRSPI = 902; + public static final int PPC_INS_XVRSPIC = 903; + public static final int PPC_INS_XVRSPIM = 904; + public static final int PPC_INS_XVRSPIP = 905; + public static final int PPC_INS_XVRSPIZ = 906; + public static final int PPC_INS_XVRSQRTEDP = 907; + public static final int PPC_INS_XVRSQRTESP = 908; + public static final int PPC_INS_XVSQRTDP = 909; + public static final int PPC_INS_XVSQRTSP = 910; + public static final int PPC_INS_XVSUBDP = 911; + public static final int PPC_INS_XVSUBSP = 912; + public static final int PPC_INS_XVTDIVDP = 913; + public static final int PPC_INS_XVTDIVSP = 914; + public static final int PPC_INS_XVTSQRTDP = 915; + public static final int PPC_INS_XVTSQRTSP = 916; + public static final int PPC_INS_XXLAND = 917; + public static final int PPC_INS_XXLANDC = 918; + public static final int PPC_INS_XXLEQV = 919; + public static final int PPC_INS_XXLNAND = 920; + public static final int PPC_INS_XXLNOR = 921; + public static final int PPC_INS_XXLOR = 922; + public static final int PPC_INS_XXLORC = 923; + public static final int PPC_INS_XXLXOR = 924; + public static final int PPC_INS_XXMRGHW = 925; + public static final int PPC_INS_XXMRGLW = 926; + public static final int PPC_INS_XXPERMDI = 927; + public static final int PPC_INS_XXSEL = 928; + public static final int PPC_INS_XXSLDWI = 929; + public static final int PPC_INS_XXSPLTW = 930; + public static final int PPC_INS_BCA = 931; + public static final int PPC_INS_BCLA = 932; + public static final int PPC_INS_SLWI = 933; + public static final int PPC_INS_SRWI = 934; + public static final int PPC_INS_SLDI = 935; + public static final int PPC_INS_BTA = 936; + public static final int PPC_INS_CRSET = 937; + public static final int PPC_INS_CRNOT = 938; + public static final int PPC_INS_CRMOVE = 939; + public static final int PPC_INS_CRCLR = 940; + public static final int PPC_INS_MFBR0 = 941; + public static final int PPC_INS_MFBR1 = 942; + public static final int PPC_INS_MFBR2 = 943; + public static final int PPC_INS_MFBR3 = 944; + public static final int PPC_INS_MFBR4 = 945; + public static final int PPC_INS_MFBR5 = 946; + public static final int PPC_INS_MFBR6 = 947; + public static final int PPC_INS_MFBR7 = 948; + public static final int PPC_INS_MFXER = 949; + public static final int PPC_INS_MFRTCU = 950; + public static final int PPC_INS_MFRTCL = 951; + public static final int PPC_INS_MFDSCR = 952; + public static final int PPC_INS_MFDSISR = 953; + public static final int PPC_INS_MFDAR = 954; + public static final int PPC_INS_MFSRR2 = 955; + public static final int PPC_INS_MFSRR3 = 956; + public static final int PPC_INS_MFCFAR = 957; + public static final int PPC_INS_MFAMR = 958; + public static final int PPC_INS_MFPID = 959; + public static final int PPC_INS_MFTBLO = 960; + public static final int PPC_INS_MFTBHI = 961; + public static final int PPC_INS_MFDBATU = 962; + public static final int PPC_INS_MFDBATL = 963; + public static final int PPC_INS_MFIBATU = 964; + public static final int PPC_INS_MFIBATL = 965; + public static final int PPC_INS_MFDCCR = 966; + public static final int PPC_INS_MFICCR = 967; + public static final int PPC_INS_MFDEAR = 968; + public static final int PPC_INS_MFESR = 969; + public static final int PPC_INS_MFSPEFSCR = 970; + public static final int PPC_INS_MFTCR = 971; + public static final int PPC_INS_MFASR = 972; + public static final int PPC_INS_MFPVR = 973; + public static final int PPC_INS_MFTBU = 974; + public static final int PPC_INS_MTCR = 975; + public static final int PPC_INS_MTBR0 = 976; + public static final int PPC_INS_MTBR1 = 977; + public static final int PPC_INS_MTBR2 = 978; + public static final int PPC_INS_MTBR3 = 979; + public static final int PPC_INS_MTBR4 = 980; + public static final int PPC_INS_MTBR5 = 981; + public static final int PPC_INS_MTBR6 = 982; + public static final int PPC_INS_MTBR7 = 983; + public static final int PPC_INS_MTXER = 984; + public static final int PPC_INS_MTDSCR = 985; + public static final int PPC_INS_MTDSISR = 986; + public static final int PPC_INS_MTDAR = 987; + public static final int PPC_INS_MTSRR2 = 988; + public static final int PPC_INS_MTSRR3 = 989; + public static final int PPC_INS_MTCFAR = 990; + public static final int PPC_INS_MTAMR = 991; + public static final int PPC_INS_MTPID = 992; + public static final int PPC_INS_MTTBL = 993; + public static final int PPC_INS_MTTBU = 994; + public static final int PPC_INS_MTTBLO = 995; + public static final int PPC_INS_MTTBHI = 996; + public static final int PPC_INS_MTDBATU = 997; + public static final int PPC_INS_MTDBATL = 998; + public static final int PPC_INS_MTIBATU = 999; + public static final int PPC_INS_MTIBATL = 1000; + public static final int PPC_INS_MTDCCR = 1001; + public static final int PPC_INS_MTICCR = 1002; + public static final int PPC_INS_MTDEAR = 1003; + public static final int PPC_INS_MTESR = 1004; + public static final int PPC_INS_MTSPEFSCR = 1005; + public static final int PPC_INS_MTTCR = 1006; + public static final int PPC_INS_NOT = 1007; + public static final int PPC_INS_MR = 1008; + public static final int PPC_INS_ROTLD = 1009; + public static final int PPC_INS_ROTLDI = 1010; + public static final int PPC_INS_CLRLDI = 1011; + public static final int PPC_INS_ROTLWI = 1012; + public static final int PPC_INS_CLRLWI = 1013; + public static final int PPC_INS_ROTLW = 1014; + public static final int PPC_INS_SUB = 1015; + public static final int PPC_INS_SUBC = 1016; + public static final int PPC_INS_LWSYNC = 1017; + public static final int PPC_INS_PTESYNC = 1018; + public static final int PPC_INS_TDLT = 1019; + public static final int PPC_INS_TDEQ = 1020; + public static final int PPC_INS_TDGT = 1021; + public static final int PPC_INS_TDNE = 1022; + public static final int PPC_INS_TDLLT = 1023; + public static final int PPC_INS_TDLGT = 1024; + public static final int PPC_INS_TDU = 1025; + public static final int PPC_INS_TDLTI = 1026; + public static final int PPC_INS_TDEQI = 1027; + public static final int PPC_INS_TDGTI = 1028; + public static final int PPC_INS_TDNEI = 1029; + public static final int PPC_INS_TDLLTI = 1030; + public static final int PPC_INS_TDLGTI = 1031; + public static final int PPC_INS_TDUI = 1032; + public static final int PPC_INS_TLBREHI = 1033; + public static final int PPC_INS_TLBRELO = 1034; + public static final int PPC_INS_TLBWEHI = 1035; + public static final int PPC_INS_TLBWELO = 1036; + public static final int PPC_INS_TWLT = 1037; + public static final int PPC_INS_TWEQ = 1038; + public static final int PPC_INS_TWGT = 1039; + public static final int PPC_INS_TWNE = 1040; + public static final int PPC_INS_TWLLT = 1041; + public static final int PPC_INS_TWLGT = 1042; + public static final int PPC_INS_TWU = 1043; + public static final int PPC_INS_TWLTI = 1044; + public static final int PPC_INS_TWEQI = 1045; + public static final int PPC_INS_TWGTI = 1046; + public static final int PPC_INS_TWNEI = 1047; + public static final int PPC_INS_TWLLTI = 1048; + public static final int PPC_INS_TWLGTI = 1049; + public static final int PPC_INS_TWUI = 1050; + public static final int PPC_INS_WAITRSV = 1051; + public static final int PPC_INS_WAITIMPL = 1052; + public static final int PPC_INS_XNOP = 1053; + public static final int PPC_INS_XVMOVDP = 1054; + public static final int PPC_INS_XVMOVSP = 1055; + public static final int PPC_INS_XXSPLTD = 1056; + public static final int PPC_INS_XXMRGHD = 1057; + public static final int PPC_INS_XXMRGLD = 1058; + public static final int PPC_INS_XXSWAPD = 1059; + public static final int PPC_INS_BT = 1060; + public static final int PPC_INS_BF = 1061; + public static final int PPC_INS_BDNZT = 1062; + public static final int PPC_INS_BDNZF = 1063; + public static final int PPC_INS_BDZF = 1064; + public static final int PPC_INS_BDZT = 1065; + public static final int PPC_INS_BFA = 1066; + public static final int PPC_INS_BDNZTA = 1067; + public static final int PPC_INS_BDNZFA = 1068; + public static final int PPC_INS_BDZTA = 1069; + public static final int PPC_INS_BDZFA = 1070; + public static final int PPC_INS_BTCTR = 1071; + public static final int PPC_INS_BFCTR = 1072; + public static final int PPC_INS_BTCTRL = 1073; + public static final int PPC_INS_BFCTRL = 1074; + public static final int PPC_INS_BTL = 1075; + public static final int PPC_INS_BFL = 1076; + public static final int PPC_INS_BDNZTL = 1077; + public static final int PPC_INS_BDNZFL = 1078; + public static final int PPC_INS_BDZTL = 1079; + public static final int PPC_INS_BDZFL = 1080; + public static final int PPC_INS_BTLA = 1081; + public static final int PPC_INS_BFLA = 1082; + public static final int PPC_INS_BDNZTLA = 1083; + public static final int PPC_INS_BDNZFLA = 1084; + public static final int PPC_INS_BDZTLA = 1085; + public static final int PPC_INS_BDZFLA = 1086; + public static final int PPC_INS_BTLR = 1087; + public static final int PPC_INS_BFLR = 1088; + public static final int PPC_INS_BDNZTLR = 1089; + public static final int PPC_INS_BDZTLR = 1090; + public static final int PPC_INS_BDZFLR = 1091; + public static final int PPC_INS_BTLRL = 1092; + public static final int PPC_INS_BFLRL = 1093; + public static final int PPC_INS_BDNZTLRL = 1094; + public static final int PPC_INS_BDNZFLRL = 1095; + public static final int PPC_INS_BDZTLRL = 1096; + public static final int PPC_INS_BDZFLRL = 1097; + public static final int PPC_INS_QVFAND = 1098; + public static final int PPC_INS_QVFCLR = 1099; + public static final int PPC_INS_QVFANDC = 1100; + public static final int PPC_INS_QVFCTFB = 1101; + public static final int PPC_INS_QVFXOR = 1102; + public static final int PPC_INS_QVFOR = 1103; + public static final int PPC_INS_QVFNOR = 1104; + public static final int PPC_INS_QVFEQU = 1105; + public static final int PPC_INS_QVFNOT = 1106; + public static final int PPC_INS_QVFORC = 1107; + public static final int PPC_INS_QVFNAND = 1108; + public static final int PPC_INS_QVFSET = 1109; + public static final int PPC_INS_ENDING = 1110; + + public static final int PPC_GRP_INVALID = 0; + public static final int PPC_GRP_JUMP = 1; + public static final int PPC_GRP_ALTIVEC = 128; + public static final int PPC_GRP_MODE32 = 129; + public static final int PPC_GRP_MODE64 = 130; + public static final int PPC_GRP_BOOKE = 131; + public static final int PPC_GRP_NOTBOOKE = 132; + public static final int PPC_GRP_SPE = 133; + public static final int PPC_GRP_VSX = 134; + public static final int PPC_GRP_E500 = 135; + public static final int PPC_GRP_PPC4XX = 136; + public static final int PPC_GRP_PPC6XX = 137; + public static final int PPC_GRP_ICBT = 138; + public static final int PPC_GRP_P8ALTIVEC = 139; + public static final int PPC_GRP_P8VECTOR = 140; + public static final int PPC_GRP_QPX = 141; + public static final int PPC_GRP_ENDING = 142; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Sparc.java b/white_patch_detect/capstone-master/bindings/java/capstone/Sparc.java new file mode 100644 index 0000000..9a8ca32 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Sparc.java @@ -0,0 +1,92 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.Sparc_const.*; + +public class Sparc { + + public static class MemType extends Structure { + public byte base; + public byte index; + public int disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("base", "index", "disp"); + } + } + + public static class OpValue extends Union { + public int reg; + public int imm; + public MemType mem; + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + + public void read() { + readField("type"); + if (type == SPARC_OP_MEM) + value.setType(MemType.class); + if (type == SPARC_OP_IMM || type == SPARC_OP_REG) + value.setType(Integer.TYPE); + if (type == SPARC_OP_INVALID) + return; + readField("value"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public int cc; + public int hint; + public byte op_count; + + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[4]; + } + + public void read() { + readField("cc"); + readField("hint"); + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("cc", "hint", "op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public int cc; + public int hint; + + public Operand [] op; + + public OpInfo(UnionOpInfo op_info) { + cc = op_info.cc; + hint = op_info.hint; + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Sparc_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Sparc_const.java new file mode 100644 index 0000000..31bd2c6 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Sparc_const.java @@ -0,0 +1,433 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Sparc_const { + + public static final int SPARC_CC_INVALID = 0; + public static final int SPARC_CC_ICC_A = 8+256; + public static final int SPARC_CC_ICC_N = 0+256; + public static final int SPARC_CC_ICC_NE = 9+256; + public static final int SPARC_CC_ICC_E = 1+256; + public static final int SPARC_CC_ICC_G = 10+256; + public static final int SPARC_CC_ICC_LE = 2+256; + public static final int SPARC_CC_ICC_GE = 11+256; + public static final int SPARC_CC_ICC_L = 3+256; + public static final int SPARC_CC_ICC_GU = 12+256; + public static final int SPARC_CC_ICC_LEU = 4+256; + public static final int SPARC_CC_ICC_CC = 13+256; + public static final int SPARC_CC_ICC_CS = 5+256; + public static final int SPARC_CC_ICC_POS = 14+256; + public static final int SPARC_CC_ICC_NEG = 6+256; + public static final int SPARC_CC_ICC_VC = 15+256; + public static final int SPARC_CC_ICC_VS = 7+256; + public static final int SPARC_CC_FCC_A = 8+16+256; + public static final int SPARC_CC_FCC_N = 0+16+256; + public static final int SPARC_CC_FCC_U = 7+16+256; + public static final int SPARC_CC_FCC_G = 6+16+256; + public static final int SPARC_CC_FCC_UG = 5+16+256; + public static final int SPARC_CC_FCC_L = 4+16+256; + public static final int SPARC_CC_FCC_UL = 3+16+256; + public static final int SPARC_CC_FCC_LG = 2+16+256; + public static final int SPARC_CC_FCC_NE = 1+16+256; + public static final int SPARC_CC_FCC_E = 9+16+256; + public static final int SPARC_CC_FCC_UE = 10+16+256; + public static final int SPARC_CC_FCC_GE = 11+16+256; + public static final int SPARC_CC_FCC_UGE = 12+16+256; + public static final int SPARC_CC_FCC_LE = 13+16+256; + public static final int SPARC_CC_FCC_ULE = 14+16+256; + public static final int SPARC_CC_FCC_O = 15+16+256; + + public static final int SPARC_HINT_INVALID = 0; + public static final int SPARC_HINT_A = 1<<0; + public static final int SPARC_HINT_PT = 1<<1; + public static final int SPARC_HINT_PN = 1<<2; + + public static final int SPARC_OP_INVALID = 0; + public static final int SPARC_OP_REG = 1; + public static final int SPARC_OP_IMM = 2; + public static final int SPARC_OP_MEM = 3; + + public static final int SPARC_REG_INVALID = 0; + public static final int SPARC_REG_F0 = 1; + public static final int SPARC_REG_F1 = 2; + public static final int SPARC_REG_F2 = 3; + public static final int SPARC_REG_F3 = 4; + public static final int SPARC_REG_F4 = 5; + public static final int SPARC_REG_F5 = 6; + public static final int SPARC_REG_F6 = 7; + public static final int SPARC_REG_F7 = 8; + public static final int SPARC_REG_F8 = 9; + public static final int SPARC_REG_F9 = 10; + public static final int SPARC_REG_F10 = 11; + public static final int SPARC_REG_F11 = 12; + public static final int SPARC_REG_F12 = 13; + public static final int SPARC_REG_F13 = 14; + public static final int SPARC_REG_F14 = 15; + public static final int SPARC_REG_F15 = 16; + public static final int SPARC_REG_F16 = 17; + public static final int SPARC_REG_F17 = 18; + public static final int SPARC_REG_F18 = 19; + public static final int SPARC_REG_F19 = 20; + public static final int SPARC_REG_F20 = 21; + public static final int SPARC_REG_F21 = 22; + public static final int SPARC_REG_F22 = 23; + public static final int SPARC_REG_F23 = 24; + public static final int SPARC_REG_F24 = 25; + public static final int SPARC_REG_F25 = 26; + public static final int SPARC_REG_F26 = 27; + public static final int SPARC_REG_F27 = 28; + public static final int SPARC_REG_F28 = 29; + public static final int SPARC_REG_F29 = 30; + public static final int SPARC_REG_F30 = 31; + public static final int SPARC_REG_F31 = 32; + public static final int SPARC_REG_F32 = 33; + public static final int SPARC_REG_F34 = 34; + public static final int SPARC_REG_F36 = 35; + public static final int SPARC_REG_F38 = 36; + public static final int SPARC_REG_F40 = 37; + public static final int SPARC_REG_F42 = 38; + public static final int SPARC_REG_F44 = 39; + public static final int SPARC_REG_F46 = 40; + public static final int SPARC_REG_F48 = 41; + public static final int SPARC_REG_F50 = 42; + public static final int SPARC_REG_F52 = 43; + public static final int SPARC_REG_F54 = 44; + public static final int SPARC_REG_F56 = 45; + public static final int SPARC_REG_F58 = 46; + public static final int SPARC_REG_F60 = 47; + public static final int SPARC_REG_F62 = 48; + public static final int SPARC_REG_FCC0 = 49; + public static final int SPARC_REG_FCC1 = 50; + public static final int SPARC_REG_FCC2 = 51; + public static final int SPARC_REG_FCC3 = 52; + public static final int SPARC_REG_FP = 53; + public static final int SPARC_REG_G0 = 54; + public static final int SPARC_REG_G1 = 55; + public static final int SPARC_REG_G2 = 56; + public static final int SPARC_REG_G3 = 57; + public static final int SPARC_REG_G4 = 58; + public static final int SPARC_REG_G5 = 59; + public static final int SPARC_REG_G6 = 60; + public static final int SPARC_REG_G7 = 61; + public static final int SPARC_REG_I0 = 62; + public static final int SPARC_REG_I1 = 63; + public static final int SPARC_REG_I2 = 64; + public static final int SPARC_REG_I3 = 65; + public static final int SPARC_REG_I4 = 66; + public static final int SPARC_REG_I5 = 67; + public static final int SPARC_REG_I7 = 68; + public static final int SPARC_REG_ICC = 69; + public static final int SPARC_REG_L0 = 70; + public static final int SPARC_REG_L1 = 71; + public static final int SPARC_REG_L2 = 72; + public static final int SPARC_REG_L3 = 73; + public static final int SPARC_REG_L4 = 74; + public static final int SPARC_REG_L5 = 75; + public static final int SPARC_REG_L6 = 76; + public static final int SPARC_REG_L7 = 77; + public static final int SPARC_REG_O0 = 78; + public static final int SPARC_REG_O1 = 79; + public static final int SPARC_REG_O2 = 80; + public static final int SPARC_REG_O3 = 81; + public static final int SPARC_REG_O4 = 82; + public static final int SPARC_REG_O5 = 83; + public static final int SPARC_REG_O7 = 84; + public static final int SPARC_REG_SP = 85; + public static final int SPARC_REG_Y = 86; + public static final int SPARC_REG_XCC = 87; + public static final int SPARC_REG_ENDING = 88; + public static final int SPARC_REG_O6 = SPARC_REG_SP; + public static final int SPARC_REG_I6 = SPARC_REG_FP; + + public static final int SPARC_INS_INVALID = 0; + public static final int SPARC_INS_ADDCC = 1; + public static final int SPARC_INS_ADDX = 2; + public static final int SPARC_INS_ADDXCC = 3; + public static final int SPARC_INS_ADDXC = 4; + public static final int SPARC_INS_ADDXCCC = 5; + public static final int SPARC_INS_ADD = 6; + public static final int SPARC_INS_ALIGNADDR = 7; + public static final int SPARC_INS_ALIGNADDRL = 8; + public static final int SPARC_INS_ANDCC = 9; + public static final int SPARC_INS_ANDNCC = 10; + public static final int SPARC_INS_ANDN = 11; + public static final int SPARC_INS_AND = 12; + public static final int SPARC_INS_ARRAY16 = 13; + public static final int SPARC_INS_ARRAY32 = 14; + public static final int SPARC_INS_ARRAY8 = 15; + public static final int SPARC_INS_B = 16; + public static final int SPARC_INS_JMP = 17; + public static final int SPARC_INS_BMASK = 18; + public static final int SPARC_INS_FB = 19; + public static final int SPARC_INS_BRGEZ = 20; + public static final int SPARC_INS_BRGZ = 21; + public static final int SPARC_INS_BRLEZ = 22; + public static final int SPARC_INS_BRLZ = 23; + public static final int SPARC_INS_BRNZ = 24; + public static final int SPARC_INS_BRZ = 25; + public static final int SPARC_INS_BSHUFFLE = 26; + public static final int SPARC_INS_CALL = 27; + public static final int SPARC_INS_CASX = 28; + public static final int SPARC_INS_CAS = 29; + public static final int SPARC_INS_CMASK16 = 30; + public static final int SPARC_INS_CMASK32 = 31; + public static final int SPARC_INS_CMASK8 = 32; + public static final int SPARC_INS_CMP = 33; + public static final int SPARC_INS_EDGE16 = 34; + public static final int SPARC_INS_EDGE16L = 35; + public static final int SPARC_INS_EDGE16LN = 36; + public static final int SPARC_INS_EDGE16N = 37; + public static final int SPARC_INS_EDGE32 = 38; + public static final int SPARC_INS_EDGE32L = 39; + public static final int SPARC_INS_EDGE32LN = 40; + public static final int SPARC_INS_EDGE32N = 41; + public static final int SPARC_INS_EDGE8 = 42; + public static final int SPARC_INS_EDGE8L = 43; + public static final int SPARC_INS_EDGE8LN = 44; + public static final int SPARC_INS_EDGE8N = 45; + public static final int SPARC_INS_FABSD = 46; + public static final int SPARC_INS_FABSQ = 47; + public static final int SPARC_INS_FABSS = 48; + public static final int SPARC_INS_FADDD = 49; + public static final int SPARC_INS_FADDQ = 50; + public static final int SPARC_INS_FADDS = 51; + public static final int SPARC_INS_FALIGNDATA = 52; + public static final int SPARC_INS_FAND = 53; + public static final int SPARC_INS_FANDNOT1 = 54; + public static final int SPARC_INS_FANDNOT1S = 55; + public static final int SPARC_INS_FANDNOT2 = 56; + public static final int SPARC_INS_FANDNOT2S = 57; + public static final int SPARC_INS_FANDS = 58; + public static final int SPARC_INS_FCHKSM16 = 59; + public static final int SPARC_INS_FCMPD = 60; + public static final int SPARC_INS_FCMPEQ16 = 61; + public static final int SPARC_INS_FCMPEQ32 = 62; + public static final int SPARC_INS_FCMPGT16 = 63; + public static final int SPARC_INS_FCMPGT32 = 64; + public static final int SPARC_INS_FCMPLE16 = 65; + public static final int SPARC_INS_FCMPLE32 = 66; + public static final int SPARC_INS_FCMPNE16 = 67; + public static final int SPARC_INS_FCMPNE32 = 68; + public static final int SPARC_INS_FCMPQ = 69; + public static final int SPARC_INS_FCMPS = 70; + public static final int SPARC_INS_FDIVD = 71; + public static final int SPARC_INS_FDIVQ = 72; + public static final int SPARC_INS_FDIVS = 73; + public static final int SPARC_INS_FDMULQ = 74; + public static final int SPARC_INS_FDTOI = 75; + public static final int SPARC_INS_FDTOQ = 76; + public static final int SPARC_INS_FDTOS = 77; + public static final int SPARC_INS_FDTOX = 78; + public static final int SPARC_INS_FEXPAND = 79; + public static final int SPARC_INS_FHADDD = 80; + public static final int SPARC_INS_FHADDS = 81; + public static final int SPARC_INS_FHSUBD = 82; + public static final int SPARC_INS_FHSUBS = 83; + public static final int SPARC_INS_FITOD = 84; + public static final int SPARC_INS_FITOQ = 85; + public static final int SPARC_INS_FITOS = 86; + public static final int SPARC_INS_FLCMPD = 87; + public static final int SPARC_INS_FLCMPS = 88; + public static final int SPARC_INS_FLUSHW = 89; + public static final int SPARC_INS_FMEAN16 = 90; + public static final int SPARC_INS_FMOVD = 91; + public static final int SPARC_INS_FMOVQ = 92; + public static final int SPARC_INS_FMOVRDGEZ = 93; + public static final int SPARC_INS_FMOVRQGEZ = 94; + public static final int SPARC_INS_FMOVRSGEZ = 95; + public static final int SPARC_INS_FMOVRDGZ = 96; + public static final int SPARC_INS_FMOVRQGZ = 97; + public static final int SPARC_INS_FMOVRSGZ = 98; + public static final int SPARC_INS_FMOVRDLEZ = 99; + public static final int SPARC_INS_FMOVRQLEZ = 100; + public static final int SPARC_INS_FMOVRSLEZ = 101; + public static final int SPARC_INS_FMOVRDLZ = 102; + public static final int SPARC_INS_FMOVRQLZ = 103; + public static final int SPARC_INS_FMOVRSLZ = 104; + public static final int SPARC_INS_FMOVRDNZ = 105; + public static final int SPARC_INS_FMOVRQNZ = 106; + public static final int SPARC_INS_FMOVRSNZ = 107; + public static final int SPARC_INS_FMOVRDZ = 108; + public static final int SPARC_INS_FMOVRQZ = 109; + public static final int SPARC_INS_FMOVRSZ = 110; + public static final int SPARC_INS_FMOVS = 111; + public static final int SPARC_INS_FMUL8SUX16 = 112; + public static final int SPARC_INS_FMUL8ULX16 = 113; + public static final int SPARC_INS_FMUL8X16 = 114; + public static final int SPARC_INS_FMUL8X16AL = 115; + public static final int SPARC_INS_FMUL8X16AU = 116; + public static final int SPARC_INS_FMULD = 117; + public static final int SPARC_INS_FMULD8SUX16 = 118; + public static final int SPARC_INS_FMULD8ULX16 = 119; + public static final int SPARC_INS_FMULQ = 120; + public static final int SPARC_INS_FMULS = 121; + public static final int SPARC_INS_FNADDD = 122; + public static final int SPARC_INS_FNADDS = 123; + public static final int SPARC_INS_FNAND = 124; + public static final int SPARC_INS_FNANDS = 125; + public static final int SPARC_INS_FNEGD = 126; + public static final int SPARC_INS_FNEGQ = 127; + public static final int SPARC_INS_FNEGS = 128; + public static final int SPARC_INS_FNHADDD = 129; + public static final int SPARC_INS_FNHADDS = 130; + public static final int SPARC_INS_FNOR = 131; + public static final int SPARC_INS_FNORS = 132; + public static final int SPARC_INS_FNOT1 = 133; + public static final int SPARC_INS_FNOT1S = 134; + public static final int SPARC_INS_FNOT2 = 135; + public static final int SPARC_INS_FNOT2S = 136; + public static final int SPARC_INS_FONE = 137; + public static final int SPARC_INS_FONES = 138; + public static final int SPARC_INS_FOR = 139; + public static final int SPARC_INS_FORNOT1 = 140; + public static final int SPARC_INS_FORNOT1S = 141; + public static final int SPARC_INS_FORNOT2 = 142; + public static final int SPARC_INS_FORNOT2S = 143; + public static final int SPARC_INS_FORS = 144; + public static final int SPARC_INS_FPACK16 = 145; + public static final int SPARC_INS_FPACK32 = 146; + public static final int SPARC_INS_FPACKFIX = 147; + public static final int SPARC_INS_FPADD16 = 148; + public static final int SPARC_INS_FPADD16S = 149; + public static final int SPARC_INS_FPADD32 = 150; + public static final int SPARC_INS_FPADD32S = 151; + public static final int SPARC_INS_FPADD64 = 152; + public static final int SPARC_INS_FPMERGE = 153; + public static final int SPARC_INS_FPSUB16 = 154; + public static final int SPARC_INS_FPSUB16S = 155; + public static final int SPARC_INS_FPSUB32 = 156; + public static final int SPARC_INS_FPSUB32S = 157; + public static final int SPARC_INS_FQTOD = 158; + public static final int SPARC_INS_FQTOI = 159; + public static final int SPARC_INS_FQTOS = 160; + public static final int SPARC_INS_FQTOX = 161; + public static final int SPARC_INS_FSLAS16 = 162; + public static final int SPARC_INS_FSLAS32 = 163; + public static final int SPARC_INS_FSLL16 = 164; + public static final int SPARC_INS_FSLL32 = 165; + public static final int SPARC_INS_FSMULD = 166; + public static final int SPARC_INS_FSQRTD = 167; + public static final int SPARC_INS_FSQRTQ = 168; + public static final int SPARC_INS_FSQRTS = 169; + public static final int SPARC_INS_FSRA16 = 170; + public static final int SPARC_INS_FSRA32 = 171; + public static final int SPARC_INS_FSRC1 = 172; + public static final int SPARC_INS_FSRC1S = 173; + public static final int SPARC_INS_FSRC2 = 174; + public static final int SPARC_INS_FSRC2S = 175; + public static final int SPARC_INS_FSRL16 = 176; + public static final int SPARC_INS_FSRL32 = 177; + public static final int SPARC_INS_FSTOD = 178; + public static final int SPARC_INS_FSTOI = 179; + public static final int SPARC_INS_FSTOQ = 180; + public static final int SPARC_INS_FSTOX = 181; + public static final int SPARC_INS_FSUBD = 182; + public static final int SPARC_INS_FSUBQ = 183; + public static final int SPARC_INS_FSUBS = 184; + public static final int SPARC_INS_FXNOR = 185; + public static final int SPARC_INS_FXNORS = 186; + public static final int SPARC_INS_FXOR = 187; + public static final int SPARC_INS_FXORS = 188; + public static final int SPARC_INS_FXTOD = 189; + public static final int SPARC_INS_FXTOQ = 190; + public static final int SPARC_INS_FXTOS = 191; + public static final int SPARC_INS_FZERO = 192; + public static final int SPARC_INS_FZEROS = 193; + public static final int SPARC_INS_JMPL = 194; + public static final int SPARC_INS_LDD = 195; + public static final int SPARC_INS_LD = 196; + public static final int SPARC_INS_LDQ = 197; + public static final int SPARC_INS_LDSB = 198; + public static final int SPARC_INS_LDSH = 199; + public static final int SPARC_INS_LDSW = 200; + public static final int SPARC_INS_LDUB = 201; + public static final int SPARC_INS_LDUH = 202; + public static final int SPARC_INS_LDX = 203; + public static final int SPARC_INS_LZCNT = 204; + public static final int SPARC_INS_MEMBAR = 205; + public static final int SPARC_INS_MOVDTOX = 206; + public static final int SPARC_INS_MOV = 207; + public static final int SPARC_INS_MOVRGEZ = 208; + public static final int SPARC_INS_MOVRGZ = 209; + public static final int SPARC_INS_MOVRLEZ = 210; + public static final int SPARC_INS_MOVRLZ = 211; + public static final int SPARC_INS_MOVRNZ = 212; + public static final int SPARC_INS_MOVRZ = 213; + public static final int SPARC_INS_MOVSTOSW = 214; + public static final int SPARC_INS_MOVSTOUW = 215; + public static final int SPARC_INS_MULX = 216; + public static final int SPARC_INS_NOP = 217; + public static final int SPARC_INS_ORCC = 218; + public static final int SPARC_INS_ORNCC = 219; + public static final int SPARC_INS_ORN = 220; + public static final int SPARC_INS_OR = 221; + public static final int SPARC_INS_PDIST = 222; + public static final int SPARC_INS_PDISTN = 223; + public static final int SPARC_INS_POPC = 224; + public static final int SPARC_INS_RD = 225; + public static final int SPARC_INS_RESTORE = 226; + public static final int SPARC_INS_RETT = 227; + public static final int SPARC_INS_SAVE = 228; + public static final int SPARC_INS_SDIVCC = 229; + public static final int SPARC_INS_SDIVX = 230; + public static final int SPARC_INS_SDIV = 231; + public static final int SPARC_INS_SETHI = 232; + public static final int SPARC_INS_SHUTDOWN = 233; + public static final int SPARC_INS_SIAM = 234; + public static final int SPARC_INS_SLLX = 235; + public static final int SPARC_INS_SLL = 236; + public static final int SPARC_INS_SMULCC = 237; + public static final int SPARC_INS_SMUL = 238; + public static final int SPARC_INS_SRAX = 239; + public static final int SPARC_INS_SRA = 240; + public static final int SPARC_INS_SRLX = 241; + public static final int SPARC_INS_SRL = 242; + public static final int SPARC_INS_STBAR = 243; + public static final int SPARC_INS_STB = 244; + public static final int SPARC_INS_STD = 245; + public static final int SPARC_INS_ST = 246; + public static final int SPARC_INS_STH = 247; + public static final int SPARC_INS_STQ = 248; + public static final int SPARC_INS_STX = 249; + public static final int SPARC_INS_SUBCC = 250; + public static final int SPARC_INS_SUBX = 251; + public static final int SPARC_INS_SUBXCC = 252; + public static final int SPARC_INS_SUB = 253; + public static final int SPARC_INS_SWAP = 254; + public static final int SPARC_INS_TADDCCTV = 255; + public static final int SPARC_INS_TADDCC = 256; + public static final int SPARC_INS_T = 257; + public static final int SPARC_INS_TSUBCCTV = 258; + public static final int SPARC_INS_TSUBCC = 259; + public static final int SPARC_INS_UDIVCC = 260; + public static final int SPARC_INS_UDIVX = 261; + public static final int SPARC_INS_UDIV = 262; + public static final int SPARC_INS_UMULCC = 263; + public static final int SPARC_INS_UMULXHI = 264; + public static final int SPARC_INS_UMUL = 265; + public static final int SPARC_INS_UNIMP = 266; + public static final int SPARC_INS_FCMPED = 267; + public static final int SPARC_INS_FCMPEQ = 268; + public static final int SPARC_INS_FCMPES = 269; + public static final int SPARC_INS_WR = 270; + public static final int SPARC_INS_XMULX = 271; + public static final int SPARC_INS_XMULXHI = 272; + public static final int SPARC_INS_XNORCC = 273; + public static final int SPARC_INS_XNOR = 274; + public static final int SPARC_INS_XORCC = 275; + public static final int SPARC_INS_XOR = 276; + public static final int SPARC_INS_RET = 277; + public static final int SPARC_INS_RETL = 278; + public static final int SPARC_INS_ENDING = 279; + + public static final int SPARC_GRP_INVALID = 0; + public static final int SPARC_GRP_JUMP = 1; + public static final int SPARC_GRP_HARDQUAD = 128; + public static final int SPARC_GRP_V9 = 129; + public static final int SPARC_GRP_VIS = 130; + public static final int SPARC_GRP_VIS2 = 131; + public static final int SPARC_GRP_VIS3 = 132; + public static final int SPARC_GRP_32BIT = 133; + public static final int SPARC_GRP_64BIT = 134; + public static final int SPARC_GRP_ENDING = 135; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Systemz.java b/white_patch_detect/capstone-master/bindings/java/capstone/Systemz.java new file mode 100644 index 0000000..1bc5ed7 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Systemz.java @@ -0,0 +1,91 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.Sysz_const.*; + +public class Systemz { + + public static class MemType extends Structure { + public byte base; + public byte index; + public long length; + public long disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("base", "index", "length", "disp"); + } + } + + public static class OpValue extends Union { + public int reg; + public long imm; + public MemType mem; + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + + public void read() { + readField("type"); + if (type == SYSZ_OP_MEM) + value.setType(MemType.class); + if (type == SYSZ_OP_IMM) + value.setType(Long.TYPE); + if (type == SYSZ_OP_REG || type == SYSZ_OP_ACREG) + value.setType(Integer.TYPE); + if (type == SYSZ_OP_INVALID) + return; + readField("value"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public int cc; + public byte op_count; + + public Operand [] op; + + public UnionOpInfo() { + op = new Operand[6]; + } + + public void read() { + readField("cc"); + readField("op_count"); + op = new Operand[op_count]; + if (op_count != 0) + readField("op"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("cc", "op_count", "op"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public int cc; + + public Operand [] op; + + public OpInfo(UnionOpInfo op_info) { + cc = op_info.cc; + op = op_info.op; + } + } +} diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/Sysz_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/Sysz_const.java new file mode 100644 index 0000000..87e771a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/Sysz_const.java @@ -0,0 +1,2527 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class Sysz_const { + + public static final int SYSZ_CC_INVALID = 0; + public static final int SYSZ_CC_O = 1; + public static final int SYSZ_CC_H = 2; + public static final int SYSZ_CC_NLE = 3; + public static final int SYSZ_CC_L = 4; + public static final int SYSZ_CC_NHE = 5; + public static final int SYSZ_CC_LH = 6; + public static final int SYSZ_CC_NE = 7; + public static final int SYSZ_CC_E = 8; + public static final int SYSZ_CC_NLH = 9; + public static final int SYSZ_CC_HE = 10; + public static final int SYSZ_CC_NL = 11; + public static final int SYSZ_CC_LE = 12; + public static final int SYSZ_CC_NH = 13; + public static final int SYSZ_CC_NO = 14; + + public static final int SYSZ_OP_INVALID = 0; + public static final int SYSZ_OP_REG = 1; + public static final int SYSZ_OP_IMM = 2; + public static final int SYSZ_OP_MEM = 3; + public static final int SYSZ_OP_ACREG = 64; + + public static final int SYSZ_REG_INVALID = 0; + public static final int SYSZ_REG_0 = 1; + public static final int SYSZ_REG_1 = 2; + public static final int SYSZ_REG_2 = 3; + public static final int SYSZ_REG_3 = 4; + public static final int SYSZ_REG_4 = 5; + public static final int SYSZ_REG_5 = 6; + public static final int SYSZ_REG_6 = 7; + public static final int SYSZ_REG_7 = 8; + public static final int SYSZ_REG_8 = 9; + public static final int SYSZ_REG_9 = 10; + public static final int SYSZ_REG_10 = 11; + public static final int SYSZ_REG_11 = 12; + public static final int SYSZ_REG_12 = 13; + public static final int SYSZ_REG_13 = 14; + public static final int SYSZ_REG_14 = 15; + public static final int SYSZ_REG_15 = 16; + public static final int SYSZ_REG_CC = 17; + public static final int SYSZ_REG_F0 = 18; + public static final int SYSZ_REG_F1 = 19; + public static final int SYSZ_REG_F2 = 20; + public static final int SYSZ_REG_F3 = 21; + public static final int SYSZ_REG_F4 = 22; + public static final int SYSZ_REG_F5 = 23; + public static final int SYSZ_REG_F6 = 24; + public static final int SYSZ_REG_F7 = 25; + public static final int SYSZ_REG_F8 = 26; + public static final int SYSZ_REG_F9 = 27; + public static final int SYSZ_REG_F10 = 28; + public static final int SYSZ_REG_F11 = 29; + public static final int SYSZ_REG_F12 = 30; + public static final int SYSZ_REG_F13 = 31; + public static final int SYSZ_REG_F14 = 32; + public static final int SYSZ_REG_F15 = 33; + public static final int SYSZ_REG_R0L = 34; + public static final int SYSZ_REG_A0 = 35; + public static final int SYSZ_REG_A1 = 36; + public static final int SYSZ_REG_A2 = 37; + public static final int SYSZ_REG_A3 = 38; + public static final int SYSZ_REG_A4 = 39; + public static final int SYSZ_REG_A5 = 40; + public static final int SYSZ_REG_A6 = 41; + public static final int SYSZ_REG_A7 = 42; + public static final int SYSZ_REG_A8 = 43; + public static final int SYSZ_REG_A9 = 44; + public static final int SYSZ_REG_A10 = 45; + public static final int SYSZ_REG_A11 = 46; + public static final int SYSZ_REG_A12 = 47; + public static final int SYSZ_REG_A13 = 48; + public static final int SYSZ_REG_A14 = 49; + public static final int SYSZ_REG_A15 = 50; + public static final int SYSZ_REG_C0 = 51; + public static final int SYSZ_REG_C1 = 52; + public static final int SYSZ_REG_C2 = 53; + public static final int SYSZ_REG_C3 = 54; + public static final int SYSZ_REG_C4 = 55; + public static final int SYSZ_REG_C5 = 56; + public static final int SYSZ_REG_C6 = 57; + public static final int SYSZ_REG_C7 = 58; + public static final int SYSZ_REG_C8 = 59; + public static final int SYSZ_REG_C9 = 60; + public static final int SYSZ_REG_C10 = 61; + public static final int SYSZ_REG_C11 = 62; + public static final int SYSZ_REG_C12 = 63; + public static final int SYSZ_REG_C13 = 64; + public static final int SYSZ_REG_C14 = 65; + public static final int SYSZ_REG_C15 = 66; + public static final int SYSZ_REG_V0 = 67; + public static final int SYSZ_REG_V1 = 68; + public static final int SYSZ_REG_V2 = 69; + public static final int SYSZ_REG_V3 = 70; + public static final int SYSZ_REG_V4 = 71; + public static final int SYSZ_REG_V5 = 72; + public static final int SYSZ_REG_V6 = 73; + public static final int SYSZ_REG_V7 = 74; + public static final int SYSZ_REG_V8 = 75; + public static final int SYSZ_REG_V9 = 76; + public static final int SYSZ_REG_V10 = 77; + public static final int SYSZ_REG_V11 = 78; + public static final int SYSZ_REG_V12 = 79; + public static final int SYSZ_REG_V13 = 80; + public static final int SYSZ_REG_V14 = 81; + public static final int SYSZ_REG_V15 = 82; + public static final int SYSZ_REG_V16 = 83; + public static final int SYSZ_REG_V17 = 84; + public static final int SYSZ_REG_V18 = 85; + public static final int SYSZ_REG_V19 = 86; + public static final int SYSZ_REG_V20 = 87; + public static final int SYSZ_REG_V21 = 88; + public static final int SYSZ_REG_V22 = 89; + public static final int SYSZ_REG_V23 = 90; + public static final int SYSZ_REG_V24 = 91; + public static final int SYSZ_REG_V25 = 92; + public static final int SYSZ_REG_V26 = 93; + public static final int SYSZ_REG_V27 = 94; + public static final int SYSZ_REG_V28 = 95; + public static final int SYSZ_REG_V29 = 96; + public static final int SYSZ_REG_V30 = 97; + public static final int SYSZ_REG_V31 = 98; + public static final int SYSZ_REG_F16 = 99; + public static final int SYSZ_REG_F17 = 100; + public static final int SYSZ_REG_F18 = 101; + public static final int SYSZ_REG_F19 = 102; + public static final int SYSZ_REG_F20 = 103; + public static final int SYSZ_REG_F21 = 104; + public static final int SYSZ_REG_F22 = 105; + public static final int SYSZ_REG_F23 = 106; + public static final int SYSZ_REG_F24 = 107; + public static final int SYSZ_REG_F25 = 108; + public static final int SYSZ_REG_F26 = 109; + public static final int SYSZ_REG_F27 = 110; + public static final int SYSZ_REG_F28 = 111; + public static final int SYSZ_REG_F29 = 112; + public static final int SYSZ_REG_F30 = 113; + public static final int SYSZ_REG_F31 = 114; + public static final int SYSZ_REG_F0Q = 115; + public static final int SYSZ_REG_F4Q = 116; + public static final int SYSZ_REG_ENDING = 117; + + public static final int SYSZ_INS_INVALID = 0; + public static final int SYSZ_INS_A = 1; + public static final int SYSZ_INS_ADB = 2; + public static final int SYSZ_INS_ADBR = 3; + public static final int SYSZ_INS_AEB = 4; + public static final int SYSZ_INS_AEBR = 5; + public static final int SYSZ_INS_AFI = 6; + public static final int SYSZ_INS_AG = 7; + public static final int SYSZ_INS_AGF = 8; + public static final int SYSZ_INS_AGFI = 9; + public static final int SYSZ_INS_AGFR = 10; + public static final int SYSZ_INS_AGHI = 11; + public static final int SYSZ_INS_AGHIK = 12; + public static final int SYSZ_INS_AGR = 13; + public static final int SYSZ_INS_AGRK = 14; + public static final int SYSZ_INS_AGSI = 15; + public static final int SYSZ_INS_AH = 16; + public static final int SYSZ_INS_AHI = 17; + public static final int SYSZ_INS_AHIK = 18; + public static final int SYSZ_INS_AHY = 19; + public static final int SYSZ_INS_AIH = 20; + public static final int SYSZ_INS_AL = 21; + public static final int SYSZ_INS_ALC = 22; + public static final int SYSZ_INS_ALCG = 23; + public static final int SYSZ_INS_ALCGR = 24; + public static final int SYSZ_INS_ALCR = 25; + public static final int SYSZ_INS_ALFI = 26; + public static final int SYSZ_INS_ALG = 27; + public static final int SYSZ_INS_ALGF = 28; + public static final int SYSZ_INS_ALGFI = 29; + public static final int SYSZ_INS_ALGFR = 30; + public static final int SYSZ_INS_ALGHSIK = 31; + public static final int SYSZ_INS_ALGR = 32; + public static final int SYSZ_INS_ALGRK = 33; + public static final int SYSZ_INS_ALHSIK = 34; + public static final int SYSZ_INS_ALR = 35; + public static final int SYSZ_INS_ALRK = 36; + public static final int SYSZ_INS_ALY = 37; + public static final int SYSZ_INS_AR = 38; + public static final int SYSZ_INS_ARK = 39; + public static final int SYSZ_INS_ASI = 40; + public static final int SYSZ_INS_AXBR = 41; + public static final int SYSZ_INS_AY = 42; + public static final int SYSZ_INS_BCR = 43; + public static final int SYSZ_INS_BRC = 44; + public static final int SYSZ_INS_BRCL = 45; + public static final int SYSZ_INS_CGIJ = 46; + public static final int SYSZ_INS_CGRJ = 47; + public static final int SYSZ_INS_CIJ = 48; + public static final int SYSZ_INS_CLGIJ = 49; + public static final int SYSZ_INS_CLGRJ = 50; + public static final int SYSZ_INS_CLIJ = 51; + public static final int SYSZ_INS_CLRJ = 52; + public static final int SYSZ_INS_CRJ = 53; + public static final int SYSZ_INS_BER = 54; + public static final int SYSZ_INS_JE = 55; + public static final int SYSZ_INS_JGE = 56; + public static final int SYSZ_INS_LOCE = 57; + public static final int SYSZ_INS_LOCGE = 58; + public static final int SYSZ_INS_LOCGRE = 59; + public static final int SYSZ_INS_LOCRE = 60; + public static final int SYSZ_INS_STOCE = 61; + public static final int SYSZ_INS_STOCGE = 62; + public static final int SYSZ_INS_BHR = 63; + public static final int SYSZ_INS_BHER = 64; + public static final int SYSZ_INS_JHE = 65; + public static final int SYSZ_INS_JGHE = 66; + public static final int SYSZ_INS_LOCHE = 67; + public static final int SYSZ_INS_LOCGHE = 68; + public static final int SYSZ_INS_LOCGRHE = 69; + public static final int SYSZ_INS_LOCRHE = 70; + public static final int SYSZ_INS_STOCHE = 71; + public static final int SYSZ_INS_STOCGHE = 72; + public static final int SYSZ_INS_JH = 73; + public static final int SYSZ_INS_JGH = 74; + public static final int SYSZ_INS_LOCH = 75; + public static final int SYSZ_INS_LOCGH = 76; + public static final int SYSZ_INS_LOCGRH = 77; + public static final int SYSZ_INS_LOCRH = 78; + public static final int SYSZ_INS_STOCH = 79; + public static final int SYSZ_INS_STOCGH = 80; + public static final int SYSZ_INS_CGIJNLH = 81; + public static final int SYSZ_INS_CGRJNLH = 82; + public static final int SYSZ_INS_CIJNLH = 83; + public static final int SYSZ_INS_CLGIJNLH = 84; + public static final int SYSZ_INS_CLGRJNLH = 85; + public static final int SYSZ_INS_CLIJNLH = 86; + public static final int SYSZ_INS_CLRJNLH = 87; + public static final int SYSZ_INS_CRJNLH = 88; + public static final int SYSZ_INS_CGIJE = 89; + public static final int SYSZ_INS_CGRJE = 90; + public static final int SYSZ_INS_CIJE = 91; + public static final int SYSZ_INS_CLGIJE = 92; + public static final int SYSZ_INS_CLGRJE = 93; + public static final int SYSZ_INS_CLIJE = 94; + public static final int SYSZ_INS_CLRJE = 95; + public static final int SYSZ_INS_CRJE = 96; + public static final int SYSZ_INS_CGIJNLE = 97; + public static final int SYSZ_INS_CGRJNLE = 98; + public static final int SYSZ_INS_CIJNLE = 99; + public static final int SYSZ_INS_CLGIJNLE = 100; + public static final int SYSZ_INS_CLGRJNLE = 101; + public static final int SYSZ_INS_CLIJNLE = 102; + public static final int SYSZ_INS_CLRJNLE = 103; + public static final int SYSZ_INS_CRJNLE = 104; + public static final int SYSZ_INS_CGIJH = 105; + public static final int SYSZ_INS_CGRJH = 106; + public static final int SYSZ_INS_CIJH = 107; + public static final int SYSZ_INS_CLGIJH = 108; + public static final int SYSZ_INS_CLGRJH = 109; + public static final int SYSZ_INS_CLIJH = 110; + public static final int SYSZ_INS_CLRJH = 111; + public static final int SYSZ_INS_CRJH = 112; + public static final int SYSZ_INS_CGIJNL = 113; + public static final int SYSZ_INS_CGRJNL = 114; + public static final int SYSZ_INS_CIJNL = 115; + public static final int SYSZ_INS_CLGIJNL = 116; + public static final int SYSZ_INS_CLGRJNL = 117; + public static final int SYSZ_INS_CLIJNL = 118; + public static final int SYSZ_INS_CLRJNL = 119; + public static final int SYSZ_INS_CRJNL = 120; + public static final int SYSZ_INS_CGIJHE = 121; + public static final int SYSZ_INS_CGRJHE = 122; + public static final int SYSZ_INS_CIJHE = 123; + public static final int SYSZ_INS_CLGIJHE = 124; + public static final int SYSZ_INS_CLGRJHE = 125; + public static final int SYSZ_INS_CLIJHE = 126; + public static final int SYSZ_INS_CLRJHE = 127; + public static final int SYSZ_INS_CRJHE = 128; + public static final int SYSZ_INS_CGIJNHE = 129; + public static final int SYSZ_INS_CGRJNHE = 130; + public static final int SYSZ_INS_CIJNHE = 131; + public static final int SYSZ_INS_CLGIJNHE = 132; + public static final int SYSZ_INS_CLGRJNHE = 133; + public static final int SYSZ_INS_CLIJNHE = 134; + public static final int SYSZ_INS_CLRJNHE = 135; + public static final int SYSZ_INS_CRJNHE = 136; + public static final int SYSZ_INS_CGIJL = 137; + public static final int SYSZ_INS_CGRJL = 138; + public static final int SYSZ_INS_CIJL = 139; + public static final int SYSZ_INS_CLGIJL = 140; + public static final int SYSZ_INS_CLGRJL = 141; + public static final int SYSZ_INS_CLIJL = 142; + public static final int SYSZ_INS_CLRJL = 143; + public static final int SYSZ_INS_CRJL = 144; + public static final int SYSZ_INS_CGIJNH = 145; + public static final int SYSZ_INS_CGRJNH = 146; + public static final int SYSZ_INS_CIJNH = 147; + public static final int SYSZ_INS_CLGIJNH = 148; + public static final int SYSZ_INS_CLGRJNH = 149; + public static final int SYSZ_INS_CLIJNH = 150; + public static final int SYSZ_INS_CLRJNH = 151; + public static final int SYSZ_INS_CRJNH = 152; + public static final int SYSZ_INS_CGIJLE = 153; + public static final int SYSZ_INS_CGRJLE = 154; + public static final int SYSZ_INS_CIJLE = 155; + public static final int SYSZ_INS_CLGIJLE = 156; + public static final int SYSZ_INS_CLGRJLE = 157; + public static final int SYSZ_INS_CLIJLE = 158; + public static final int SYSZ_INS_CLRJLE = 159; + public static final int SYSZ_INS_CRJLE = 160; + public static final int SYSZ_INS_CGIJNE = 161; + public static final int SYSZ_INS_CGRJNE = 162; + public static final int SYSZ_INS_CIJNE = 163; + public static final int SYSZ_INS_CLGIJNE = 164; + public static final int SYSZ_INS_CLGRJNE = 165; + public static final int SYSZ_INS_CLIJNE = 166; + public static final int SYSZ_INS_CLRJNE = 167; + public static final int SYSZ_INS_CRJNE = 168; + public static final int SYSZ_INS_CGIJLH = 169; + public static final int SYSZ_INS_CGRJLH = 170; + public static final int SYSZ_INS_CIJLH = 171; + public static final int SYSZ_INS_CLGIJLH = 172; + public static final int SYSZ_INS_CLGRJLH = 173; + public static final int SYSZ_INS_CLIJLH = 174; + public static final int SYSZ_INS_CLRJLH = 175; + public static final int SYSZ_INS_CRJLH = 176; + public static final int SYSZ_INS_BLR = 177; + public static final int SYSZ_INS_BLER = 178; + public static final int SYSZ_INS_JLE = 179; + public static final int SYSZ_INS_JGLE = 180; + public static final int SYSZ_INS_LOCLE = 181; + public static final int SYSZ_INS_LOCGLE = 182; + public static final int SYSZ_INS_LOCGRLE = 183; + public static final int SYSZ_INS_LOCRLE = 184; + public static final int SYSZ_INS_STOCLE = 185; + public static final int SYSZ_INS_STOCGLE = 186; + public static final int SYSZ_INS_BLHR = 187; + public static final int SYSZ_INS_JLH = 188; + public static final int SYSZ_INS_JGLH = 189; + public static final int SYSZ_INS_LOCLH = 190; + public static final int SYSZ_INS_LOCGLH = 191; + public static final int SYSZ_INS_LOCGRLH = 192; + public static final int SYSZ_INS_LOCRLH = 193; + public static final int SYSZ_INS_STOCLH = 194; + public static final int SYSZ_INS_STOCGLH = 195; + public static final int SYSZ_INS_JL = 196; + public static final int SYSZ_INS_JGL = 197; + public static final int SYSZ_INS_LOCL = 198; + public static final int SYSZ_INS_LOCGL = 199; + public static final int SYSZ_INS_LOCGRL = 200; + public static final int SYSZ_INS_LOCRL = 201; + public static final int SYSZ_INS_LOC = 202; + public static final int SYSZ_INS_LOCG = 203; + public static final int SYSZ_INS_LOCGR = 204; + public static final int SYSZ_INS_LOCR = 205; + public static final int SYSZ_INS_STOCL = 206; + public static final int SYSZ_INS_STOCGL = 207; + public static final int SYSZ_INS_BNER = 208; + public static final int SYSZ_INS_JNE = 209; + public static final int SYSZ_INS_JGNE = 210; + public static final int SYSZ_INS_LOCNE = 211; + public static final int SYSZ_INS_LOCGNE = 212; + public static final int SYSZ_INS_LOCGRNE = 213; + public static final int SYSZ_INS_LOCRNE = 214; + public static final int SYSZ_INS_STOCNE = 215; + public static final int SYSZ_INS_STOCGNE = 216; + public static final int SYSZ_INS_BNHR = 217; + public static final int SYSZ_INS_BNHER = 218; + public static final int SYSZ_INS_JNHE = 219; + public static final int SYSZ_INS_JGNHE = 220; + public static final int SYSZ_INS_LOCNHE = 221; + public static final int SYSZ_INS_LOCGNHE = 222; + public static final int SYSZ_INS_LOCGRNHE = 223; + public static final int SYSZ_INS_LOCRNHE = 224; + public static final int SYSZ_INS_STOCNHE = 225; + public static final int SYSZ_INS_STOCGNHE = 226; + public static final int SYSZ_INS_JNH = 227; + public static final int SYSZ_INS_JGNH = 228; + public static final int SYSZ_INS_LOCNH = 229; + public static final int SYSZ_INS_LOCGNH = 230; + public static final int SYSZ_INS_LOCGRNH = 231; + public static final int SYSZ_INS_LOCRNH = 232; + public static final int SYSZ_INS_STOCNH = 233; + public static final int SYSZ_INS_STOCGNH = 234; + public static final int SYSZ_INS_BNLR = 235; + public static final int SYSZ_INS_BNLER = 236; + public static final int SYSZ_INS_JNLE = 237; + public static final int SYSZ_INS_JGNLE = 238; + public static final int SYSZ_INS_LOCNLE = 239; + public static final int SYSZ_INS_LOCGNLE = 240; + public static final int SYSZ_INS_LOCGRNLE = 241; + public static final int SYSZ_INS_LOCRNLE = 242; + public static final int SYSZ_INS_STOCNLE = 243; + public static final int SYSZ_INS_STOCGNLE = 244; + public static final int SYSZ_INS_BNLHR = 245; + public static final int SYSZ_INS_JNLH = 246; + public static final int SYSZ_INS_JGNLH = 247; + public static final int SYSZ_INS_LOCNLH = 248; + public static final int SYSZ_INS_LOCGNLH = 249; + public static final int SYSZ_INS_LOCGRNLH = 250; + public static final int SYSZ_INS_LOCRNLH = 251; + public static final int SYSZ_INS_STOCNLH = 252; + public static final int SYSZ_INS_STOCGNLH = 253; + public static final int SYSZ_INS_JNL = 254; + public static final int SYSZ_INS_JGNL = 255; + public static final int SYSZ_INS_LOCNL = 256; + public static final int SYSZ_INS_LOCGNL = 257; + public static final int SYSZ_INS_LOCGRNL = 258; + public static final int SYSZ_INS_LOCRNL = 259; + public static final int SYSZ_INS_STOCNL = 260; + public static final int SYSZ_INS_STOCGNL = 261; + public static final int SYSZ_INS_BNOR = 262; + public static final int SYSZ_INS_JNO = 263; + public static final int SYSZ_INS_JGNO = 264; + public static final int SYSZ_INS_LOCNO = 265; + public static final int SYSZ_INS_LOCGNO = 266; + public static final int SYSZ_INS_LOCGRNO = 267; + public static final int SYSZ_INS_LOCRNO = 268; + public static final int SYSZ_INS_STOCNO = 269; + public static final int SYSZ_INS_STOCGNO = 270; + public static final int SYSZ_INS_BOR = 271; + public static final int SYSZ_INS_JO = 272; + public static final int SYSZ_INS_JGO = 273; + public static final int SYSZ_INS_LOCO = 274; + public static final int SYSZ_INS_LOCGO = 275; + public static final int SYSZ_INS_LOCGRO = 276; + public static final int SYSZ_INS_LOCRO = 277; + public static final int SYSZ_INS_STOCO = 278; + public static final int SYSZ_INS_STOCGO = 279; + public static final int SYSZ_INS_STOC = 280; + public static final int SYSZ_INS_STOCG = 281; + public static final int SYSZ_INS_BASR = 282; + public static final int SYSZ_INS_BR = 283; + public static final int SYSZ_INS_BRAS = 284; + public static final int SYSZ_INS_BRASL = 285; + public static final int SYSZ_INS_J = 286; + public static final int SYSZ_INS_JG = 287; + public static final int SYSZ_INS_BRCT = 288; + public static final int SYSZ_INS_BRCTG = 289; + public static final int SYSZ_INS_C = 290; + public static final int SYSZ_INS_CDB = 291; + public static final int SYSZ_INS_CDBR = 292; + public static final int SYSZ_INS_CDFBR = 293; + public static final int SYSZ_INS_CDGBR = 294; + public static final int SYSZ_INS_CDLFBR = 295; + public static final int SYSZ_INS_CDLGBR = 296; + public static final int SYSZ_INS_CEB = 297; + public static final int SYSZ_INS_CEBR = 298; + public static final int SYSZ_INS_CEFBR = 299; + public static final int SYSZ_INS_CEGBR = 300; + public static final int SYSZ_INS_CELFBR = 301; + public static final int SYSZ_INS_CELGBR = 302; + public static final int SYSZ_INS_CFDBR = 303; + public static final int SYSZ_INS_CFEBR = 304; + public static final int SYSZ_INS_CFI = 305; + public static final int SYSZ_INS_CFXBR = 306; + public static final int SYSZ_INS_CG = 307; + public static final int SYSZ_INS_CGDBR = 308; + public static final int SYSZ_INS_CGEBR = 309; + public static final int SYSZ_INS_CGF = 310; + public static final int SYSZ_INS_CGFI = 311; + public static final int SYSZ_INS_CGFR = 312; + public static final int SYSZ_INS_CGFRL = 313; + public static final int SYSZ_INS_CGH = 314; + public static final int SYSZ_INS_CGHI = 315; + public static final int SYSZ_INS_CGHRL = 316; + public static final int SYSZ_INS_CGHSI = 317; + public static final int SYSZ_INS_CGR = 318; + public static final int SYSZ_INS_CGRL = 319; + public static final int SYSZ_INS_CGXBR = 320; + public static final int SYSZ_INS_CH = 321; + public static final int SYSZ_INS_CHF = 322; + public static final int SYSZ_INS_CHHSI = 323; + public static final int SYSZ_INS_CHI = 324; + public static final int SYSZ_INS_CHRL = 325; + public static final int SYSZ_INS_CHSI = 326; + public static final int SYSZ_INS_CHY = 327; + public static final int SYSZ_INS_CIH = 328; + public static final int SYSZ_INS_CL = 329; + public static final int SYSZ_INS_CLC = 330; + public static final int SYSZ_INS_CLFDBR = 331; + public static final int SYSZ_INS_CLFEBR = 332; + public static final int SYSZ_INS_CLFHSI = 333; + public static final int SYSZ_INS_CLFI = 334; + public static final int SYSZ_INS_CLFXBR = 335; + public static final int SYSZ_INS_CLG = 336; + public static final int SYSZ_INS_CLGDBR = 337; + public static final int SYSZ_INS_CLGEBR = 338; + public static final int SYSZ_INS_CLGF = 339; + public static final int SYSZ_INS_CLGFI = 340; + public static final int SYSZ_INS_CLGFR = 341; + public static final int SYSZ_INS_CLGFRL = 342; + public static final int SYSZ_INS_CLGHRL = 343; + public static final int SYSZ_INS_CLGHSI = 344; + public static final int SYSZ_INS_CLGR = 345; + public static final int SYSZ_INS_CLGRL = 346; + public static final int SYSZ_INS_CLGXBR = 347; + public static final int SYSZ_INS_CLHF = 348; + public static final int SYSZ_INS_CLHHSI = 349; + public static final int SYSZ_INS_CLHRL = 350; + public static final int SYSZ_INS_CLI = 351; + public static final int SYSZ_INS_CLIH = 352; + public static final int SYSZ_INS_CLIY = 353; + public static final int SYSZ_INS_CLR = 354; + public static final int SYSZ_INS_CLRL = 355; + public static final int SYSZ_INS_CLST = 356; + public static final int SYSZ_INS_CLY = 357; + public static final int SYSZ_INS_CPSDR = 358; + public static final int SYSZ_INS_CR = 359; + public static final int SYSZ_INS_CRL = 360; + public static final int SYSZ_INS_CS = 361; + public static final int SYSZ_INS_CSG = 362; + public static final int SYSZ_INS_CSY = 363; + public static final int SYSZ_INS_CXBR = 364; + public static final int SYSZ_INS_CXFBR = 365; + public static final int SYSZ_INS_CXGBR = 366; + public static final int SYSZ_INS_CXLFBR = 367; + public static final int SYSZ_INS_CXLGBR = 368; + public static final int SYSZ_INS_CY = 369; + public static final int SYSZ_INS_DDB = 370; + public static final int SYSZ_INS_DDBR = 371; + public static final int SYSZ_INS_DEB = 372; + public static final int SYSZ_INS_DEBR = 373; + public static final int SYSZ_INS_DL = 374; + public static final int SYSZ_INS_DLG = 375; + public static final int SYSZ_INS_DLGR = 376; + public static final int SYSZ_INS_DLR = 377; + public static final int SYSZ_INS_DSG = 378; + public static final int SYSZ_INS_DSGF = 379; + public static final int SYSZ_INS_DSGFR = 380; + public static final int SYSZ_INS_DSGR = 381; + public static final int SYSZ_INS_DXBR = 382; + public static final int SYSZ_INS_EAR = 383; + public static final int SYSZ_INS_FIDBR = 384; + public static final int SYSZ_INS_FIDBRA = 385; + public static final int SYSZ_INS_FIEBR = 386; + public static final int SYSZ_INS_FIEBRA = 387; + public static final int SYSZ_INS_FIXBR = 388; + public static final int SYSZ_INS_FIXBRA = 389; + public static final int SYSZ_INS_FLOGR = 390; + public static final int SYSZ_INS_IC = 391; + public static final int SYSZ_INS_ICY = 392; + public static final int SYSZ_INS_IIHF = 393; + public static final int SYSZ_INS_IIHH = 394; + public static final int SYSZ_INS_IIHL = 395; + public static final int SYSZ_INS_IILF = 396; + public static final int SYSZ_INS_IILH = 397; + public static final int SYSZ_INS_IILL = 398; + public static final int SYSZ_INS_IPM = 399; + public static final int SYSZ_INS_L = 400; + public static final int SYSZ_INS_LA = 401; + public static final int SYSZ_INS_LAA = 402; + public static final int SYSZ_INS_LAAG = 403; + public static final int SYSZ_INS_LAAL = 404; + public static final int SYSZ_INS_LAALG = 405; + public static final int SYSZ_INS_LAN = 406; + public static final int SYSZ_INS_LANG = 407; + public static final int SYSZ_INS_LAO = 408; + public static final int SYSZ_INS_LAOG = 409; + public static final int SYSZ_INS_LARL = 410; + public static final int SYSZ_INS_LAX = 411; + public static final int SYSZ_INS_LAXG = 412; + public static final int SYSZ_INS_LAY = 413; + public static final int SYSZ_INS_LB = 414; + public static final int SYSZ_INS_LBH = 415; + public static final int SYSZ_INS_LBR = 416; + public static final int SYSZ_INS_LCDBR = 417; + public static final int SYSZ_INS_LCEBR = 418; + public static final int SYSZ_INS_LCGFR = 419; + public static final int SYSZ_INS_LCGR = 420; + public static final int SYSZ_INS_LCR = 421; + public static final int SYSZ_INS_LCXBR = 422; + public static final int SYSZ_INS_LD = 423; + public static final int SYSZ_INS_LDEB = 424; + public static final int SYSZ_INS_LDEBR = 425; + public static final int SYSZ_INS_LDGR = 426; + public static final int SYSZ_INS_LDR = 427; + public static final int SYSZ_INS_LDXBR = 428; + public static final int SYSZ_INS_LDXBRA = 429; + public static final int SYSZ_INS_LDY = 430; + public static final int SYSZ_INS_LE = 431; + public static final int SYSZ_INS_LEDBR = 432; + public static final int SYSZ_INS_LEDBRA = 433; + public static final int SYSZ_INS_LER = 434; + public static final int SYSZ_INS_LEXBR = 435; + public static final int SYSZ_INS_LEXBRA = 436; + public static final int SYSZ_INS_LEY = 437; + public static final int SYSZ_INS_LFH = 438; + public static final int SYSZ_INS_LG = 439; + public static final int SYSZ_INS_LGB = 440; + public static final int SYSZ_INS_LGBR = 441; + public static final int SYSZ_INS_LGDR = 442; + public static final int SYSZ_INS_LGF = 443; + public static final int SYSZ_INS_LGFI = 444; + public static final int SYSZ_INS_LGFR = 445; + public static final int SYSZ_INS_LGFRL = 446; + public static final int SYSZ_INS_LGH = 447; + public static final int SYSZ_INS_LGHI = 448; + public static final int SYSZ_INS_LGHR = 449; + public static final int SYSZ_INS_LGHRL = 450; + public static final int SYSZ_INS_LGR = 451; + public static final int SYSZ_INS_LGRL = 452; + public static final int SYSZ_INS_LH = 453; + public static final int SYSZ_INS_LHH = 454; + public static final int SYSZ_INS_LHI = 455; + public static final int SYSZ_INS_LHR = 456; + public static final int SYSZ_INS_LHRL = 457; + public static final int SYSZ_INS_LHY = 458; + public static final int SYSZ_INS_LLC = 459; + public static final int SYSZ_INS_LLCH = 460; + public static final int SYSZ_INS_LLCR = 461; + public static final int SYSZ_INS_LLGC = 462; + public static final int SYSZ_INS_LLGCR = 463; + public static final int SYSZ_INS_LLGF = 464; + public static final int SYSZ_INS_LLGFR = 465; + public static final int SYSZ_INS_LLGFRL = 466; + public static final int SYSZ_INS_LLGH = 467; + public static final int SYSZ_INS_LLGHR = 468; + public static final int SYSZ_INS_LLGHRL = 469; + public static final int SYSZ_INS_LLH = 470; + public static final int SYSZ_INS_LLHH = 471; + public static final int SYSZ_INS_LLHR = 472; + public static final int SYSZ_INS_LLHRL = 473; + public static final int SYSZ_INS_LLIHF = 474; + public static final int SYSZ_INS_LLIHH = 475; + public static final int SYSZ_INS_LLIHL = 476; + public static final int SYSZ_INS_LLILF = 477; + public static final int SYSZ_INS_LLILH = 478; + public static final int SYSZ_INS_LLILL = 479; + public static final int SYSZ_INS_LMG = 480; + public static final int SYSZ_INS_LNDBR = 481; + public static final int SYSZ_INS_LNEBR = 482; + public static final int SYSZ_INS_LNGFR = 483; + public static final int SYSZ_INS_LNGR = 484; + public static final int SYSZ_INS_LNR = 485; + public static final int SYSZ_INS_LNXBR = 486; + public static final int SYSZ_INS_LPDBR = 487; + public static final int SYSZ_INS_LPEBR = 488; + public static final int SYSZ_INS_LPGFR = 489; + public static final int SYSZ_INS_LPGR = 490; + public static final int SYSZ_INS_LPR = 491; + public static final int SYSZ_INS_LPXBR = 492; + public static final int SYSZ_INS_LR = 493; + public static final int SYSZ_INS_LRL = 494; + public static final int SYSZ_INS_LRV = 495; + public static final int SYSZ_INS_LRVG = 496; + public static final int SYSZ_INS_LRVGR = 497; + public static final int SYSZ_INS_LRVR = 498; + public static final int SYSZ_INS_LT = 499; + public static final int SYSZ_INS_LTDBR = 500; + public static final int SYSZ_INS_LTEBR = 501; + public static final int SYSZ_INS_LTG = 502; + public static final int SYSZ_INS_LTGF = 503; + public static final int SYSZ_INS_LTGFR = 504; + public static final int SYSZ_INS_LTGR = 505; + public static final int SYSZ_INS_LTR = 506; + public static final int SYSZ_INS_LTXBR = 507; + public static final int SYSZ_INS_LXDB = 508; + public static final int SYSZ_INS_LXDBR = 509; + public static final int SYSZ_INS_LXEB = 510; + public static final int SYSZ_INS_LXEBR = 511; + public static final int SYSZ_INS_LXR = 512; + public static final int SYSZ_INS_LY = 513; + public static final int SYSZ_INS_LZDR = 514; + public static final int SYSZ_INS_LZER = 515; + public static final int SYSZ_INS_LZXR = 516; + public static final int SYSZ_INS_MADB = 517; + public static final int SYSZ_INS_MADBR = 518; + public static final int SYSZ_INS_MAEB = 519; + public static final int SYSZ_INS_MAEBR = 520; + public static final int SYSZ_INS_MDB = 521; + public static final int SYSZ_INS_MDBR = 522; + public static final int SYSZ_INS_MDEB = 523; + public static final int SYSZ_INS_MDEBR = 524; + public static final int SYSZ_INS_MEEB = 525; + public static final int SYSZ_INS_MEEBR = 526; + public static final int SYSZ_INS_MGHI = 527; + public static final int SYSZ_INS_MH = 528; + public static final int SYSZ_INS_MHI = 529; + public static final int SYSZ_INS_MHY = 530; + public static final int SYSZ_INS_MLG = 531; + public static final int SYSZ_INS_MLGR = 532; + public static final int SYSZ_INS_MS = 533; + public static final int SYSZ_INS_MSDB = 534; + public static final int SYSZ_INS_MSDBR = 535; + public static final int SYSZ_INS_MSEB = 536; + public static final int SYSZ_INS_MSEBR = 537; + public static final int SYSZ_INS_MSFI = 538; + public static final int SYSZ_INS_MSG = 539; + public static final int SYSZ_INS_MSGF = 540; + public static final int SYSZ_INS_MSGFI = 541; + public static final int SYSZ_INS_MSGFR = 542; + public static final int SYSZ_INS_MSGR = 543; + public static final int SYSZ_INS_MSR = 544; + public static final int SYSZ_INS_MSY = 545; + public static final int SYSZ_INS_MVC = 546; + public static final int SYSZ_INS_MVGHI = 547; + public static final int SYSZ_INS_MVHHI = 548; + public static final int SYSZ_INS_MVHI = 549; + public static final int SYSZ_INS_MVI = 550; + public static final int SYSZ_INS_MVIY = 551; + public static final int SYSZ_INS_MVST = 552; + public static final int SYSZ_INS_MXBR = 553; + public static final int SYSZ_INS_MXDB = 554; + public static final int SYSZ_INS_MXDBR = 555; + public static final int SYSZ_INS_N = 556; + public static final int SYSZ_INS_NC = 557; + public static final int SYSZ_INS_NG = 558; + public static final int SYSZ_INS_NGR = 559; + public static final int SYSZ_INS_NGRK = 560; + public static final int SYSZ_INS_NI = 561; + public static final int SYSZ_INS_NIHF = 562; + public static final int SYSZ_INS_NIHH = 563; + public static final int SYSZ_INS_NIHL = 564; + public static final int SYSZ_INS_NILF = 565; + public static final int SYSZ_INS_NILH = 566; + public static final int SYSZ_INS_NILL = 567; + public static final int SYSZ_INS_NIY = 568; + public static final int SYSZ_INS_NR = 569; + public static final int SYSZ_INS_NRK = 570; + public static final int SYSZ_INS_NY = 571; + public static final int SYSZ_INS_O = 572; + public static final int SYSZ_INS_OC = 573; + public static final int SYSZ_INS_OG = 574; + public static final int SYSZ_INS_OGR = 575; + public static final int SYSZ_INS_OGRK = 576; + public static final int SYSZ_INS_OI = 577; + public static final int SYSZ_INS_OIHF = 578; + public static final int SYSZ_INS_OIHH = 579; + public static final int SYSZ_INS_OIHL = 580; + public static final int SYSZ_INS_OILF = 581; + public static final int SYSZ_INS_OILH = 582; + public static final int SYSZ_INS_OILL = 583; + public static final int SYSZ_INS_OIY = 584; + public static final int SYSZ_INS_OR = 585; + public static final int SYSZ_INS_ORK = 586; + public static final int SYSZ_INS_OY = 587; + public static final int SYSZ_INS_PFD = 588; + public static final int SYSZ_INS_PFDRL = 589; + public static final int SYSZ_INS_RISBG = 590; + public static final int SYSZ_INS_RISBHG = 591; + public static final int SYSZ_INS_RISBLG = 592; + public static final int SYSZ_INS_RLL = 593; + public static final int SYSZ_INS_RLLG = 594; + public static final int SYSZ_INS_RNSBG = 595; + public static final int SYSZ_INS_ROSBG = 596; + public static final int SYSZ_INS_RXSBG = 597; + public static final int SYSZ_INS_S = 598; + public static final int SYSZ_INS_SDB = 599; + public static final int SYSZ_INS_SDBR = 600; + public static final int SYSZ_INS_SEB = 601; + public static final int SYSZ_INS_SEBR = 602; + public static final int SYSZ_INS_SG = 603; + public static final int SYSZ_INS_SGF = 604; + public static final int SYSZ_INS_SGFR = 605; + public static final int SYSZ_INS_SGR = 606; + public static final int SYSZ_INS_SGRK = 607; + public static final int SYSZ_INS_SH = 608; + public static final int SYSZ_INS_SHY = 609; + public static final int SYSZ_INS_SL = 610; + public static final int SYSZ_INS_SLB = 611; + public static final int SYSZ_INS_SLBG = 612; + public static final int SYSZ_INS_SLBR = 613; + public static final int SYSZ_INS_SLFI = 614; + public static final int SYSZ_INS_SLG = 615; + public static final int SYSZ_INS_SLBGR = 616; + public static final int SYSZ_INS_SLGF = 617; + public static final int SYSZ_INS_SLGFI = 618; + public static final int SYSZ_INS_SLGFR = 619; + public static final int SYSZ_INS_SLGR = 620; + public static final int SYSZ_INS_SLGRK = 621; + public static final int SYSZ_INS_SLL = 622; + public static final int SYSZ_INS_SLLG = 623; + public static final int SYSZ_INS_SLLK = 624; + public static final int SYSZ_INS_SLR = 625; + public static final int SYSZ_INS_SLRK = 626; + public static final int SYSZ_INS_SLY = 627; + public static final int SYSZ_INS_SQDB = 628; + public static final int SYSZ_INS_SQDBR = 629; + public static final int SYSZ_INS_SQEB = 630; + public static final int SYSZ_INS_SQEBR = 631; + public static final int SYSZ_INS_SQXBR = 632; + public static final int SYSZ_INS_SR = 633; + public static final int SYSZ_INS_SRA = 634; + public static final int SYSZ_INS_SRAG = 635; + public static final int SYSZ_INS_SRAK = 636; + public static final int SYSZ_INS_SRK = 637; + public static final int SYSZ_INS_SRL = 638; + public static final int SYSZ_INS_SRLG = 639; + public static final int SYSZ_INS_SRLK = 640; + public static final int SYSZ_INS_SRST = 641; + public static final int SYSZ_INS_ST = 642; + public static final int SYSZ_INS_STC = 643; + public static final int SYSZ_INS_STCH = 644; + public static final int SYSZ_INS_STCY = 645; + public static final int SYSZ_INS_STD = 646; + public static final int SYSZ_INS_STDY = 647; + public static final int SYSZ_INS_STE = 648; + public static final int SYSZ_INS_STEY = 649; + public static final int SYSZ_INS_STFH = 650; + public static final int SYSZ_INS_STG = 651; + public static final int SYSZ_INS_STGRL = 652; + public static final int SYSZ_INS_STH = 653; + public static final int SYSZ_INS_STHH = 654; + public static final int SYSZ_INS_STHRL = 655; + public static final int SYSZ_INS_STHY = 656; + public static final int SYSZ_INS_STMG = 657; + public static final int SYSZ_INS_STRL = 658; + public static final int SYSZ_INS_STRV = 659; + public static final int SYSZ_INS_STRVG = 660; + public static final int SYSZ_INS_STY = 661; + public static final int SYSZ_INS_SXBR = 662; + public static final int SYSZ_INS_SY = 663; + public static final int SYSZ_INS_TM = 664; + public static final int SYSZ_INS_TMHH = 665; + public static final int SYSZ_INS_TMHL = 666; + public static final int SYSZ_INS_TMLH = 667; + public static final int SYSZ_INS_TMLL = 668; + public static final int SYSZ_INS_TMY = 669; + public static final int SYSZ_INS_X = 670; + public static final int SYSZ_INS_XC = 671; + public static final int SYSZ_INS_XG = 672; + public static final int SYSZ_INS_XGR = 673; + public static final int SYSZ_INS_XGRK = 674; + public static final int SYSZ_INS_XI = 675; + public static final int SYSZ_INS_XIHF = 676; + public static final int SYSZ_INS_XILF = 677; + public static final int SYSZ_INS_XIY = 678; + public static final int SYSZ_INS_XR = 679; + public static final int SYSZ_INS_XRK = 680; + public static final int SYSZ_INS_XY = 681; + public static final int SYSZ_INS_AD = 682; + public static final int SYSZ_INS_ADR = 683; + public static final int SYSZ_INS_ADTR = 684; + public static final int SYSZ_INS_ADTRA = 685; + public static final int SYSZ_INS_AE = 686; + public static final int SYSZ_INS_AER = 687; + public static final int SYSZ_INS_AGH = 688; + public static final int SYSZ_INS_AHHHR = 689; + public static final int SYSZ_INS_AHHLR = 690; + public static final int SYSZ_INS_ALGSI = 691; + public static final int SYSZ_INS_ALHHHR = 692; + public static final int SYSZ_INS_ALHHLR = 693; + public static final int SYSZ_INS_ALSI = 694; + public static final int SYSZ_INS_ALSIH = 695; + public static final int SYSZ_INS_ALSIHN = 696; + public static final int SYSZ_INS_AP = 697; + public static final int SYSZ_INS_AU = 698; + public static final int SYSZ_INS_AUR = 699; + public static final int SYSZ_INS_AW = 700; + public static final int SYSZ_INS_AWR = 701; + public static final int SYSZ_INS_AXR = 702; + public static final int SYSZ_INS_AXTR = 703; + public static final int SYSZ_INS_AXTRA = 704; + public static final int SYSZ_INS_B = 705; + public static final int SYSZ_INS_BAKR = 706; + public static final int SYSZ_INS_BAL = 707; + public static final int SYSZ_INS_BALR = 708; + public static final int SYSZ_INS_BAS = 709; + public static final int SYSZ_INS_BASSM = 710; + public static final int SYSZ_INS_BC = 711; + public static final int SYSZ_INS_BCT = 712; + public static final int SYSZ_INS_BCTG = 713; + public static final int SYSZ_INS_BCTGR = 714; + public static final int SYSZ_INS_BCTR = 715; + public static final int SYSZ_INS_BE = 716; + public static final int SYSZ_INS_BH = 717; + public static final int SYSZ_INS_BHE = 718; + public static final int SYSZ_INS_BI = 719; + public static final int SYSZ_INS_BIC = 720; + public static final int SYSZ_INS_BIE = 721; + public static final int SYSZ_INS_BIH = 722; + public static final int SYSZ_INS_BIHE = 723; + public static final int SYSZ_INS_BIL = 724; + public static final int SYSZ_INS_BILE = 725; + public static final int SYSZ_INS_BILH = 726; + public static final int SYSZ_INS_BIM = 727; + public static final int SYSZ_INS_BINE = 728; + public static final int SYSZ_INS_BINH = 729; + public static final int SYSZ_INS_BINHE = 730; + public static final int SYSZ_INS_BINL = 731; + public static final int SYSZ_INS_BINLE = 732; + public static final int SYSZ_INS_BINLH = 733; + public static final int SYSZ_INS_BINM = 734; + public static final int SYSZ_INS_BINO = 735; + public static final int SYSZ_INS_BINP = 736; + public static final int SYSZ_INS_BINZ = 737; + public static final int SYSZ_INS_BIO = 738; + public static final int SYSZ_INS_BIP = 739; + public static final int SYSZ_INS_BIZ = 740; + public static final int SYSZ_INS_BL = 741; + public static final int SYSZ_INS_BLE = 742; + public static final int SYSZ_INS_BLH = 743; + public static final int SYSZ_INS_BM = 744; + public static final int SYSZ_INS_BMR = 745; + public static final int SYSZ_INS_BNE = 746; + public static final int SYSZ_INS_BNH = 747; + public static final int SYSZ_INS_BNHE = 748; + public static final int SYSZ_INS_BNL = 749; + public static final int SYSZ_INS_BNLE = 750; + public static final int SYSZ_INS_BNLH = 751; + public static final int SYSZ_INS_BNM = 752; + public static final int SYSZ_INS_BNMR = 753; + public static final int SYSZ_INS_BNO = 754; + public static final int SYSZ_INS_BNP = 755; + public static final int SYSZ_INS_BNPR = 756; + public static final int SYSZ_INS_BNZ = 757; + public static final int SYSZ_INS_BNZR = 758; + public static final int SYSZ_INS_BO = 759; + public static final int SYSZ_INS_BP = 760; + public static final int SYSZ_INS_BPP = 761; + public static final int SYSZ_INS_BPR = 762; + public static final int SYSZ_INS_BPRP = 763; + public static final int SYSZ_INS_BRCTH = 764; + public static final int SYSZ_INS_BRXH = 765; + public static final int SYSZ_INS_BRXHG = 766; + public static final int SYSZ_INS_BRXLE = 767; + public static final int SYSZ_INS_BRXLG = 768; + public static final int SYSZ_INS_BSA = 769; + public static final int SYSZ_INS_BSG = 770; + public static final int SYSZ_INS_BSM = 771; + public static final int SYSZ_INS_BXH = 772; + public static final int SYSZ_INS_BXHG = 773; + public static final int SYSZ_INS_BXLE = 774; + public static final int SYSZ_INS_BXLEG = 775; + public static final int SYSZ_INS_BZ = 776; + public static final int SYSZ_INS_BZR = 777; + public static final int SYSZ_INS_CD = 778; + public static final int SYSZ_INS_CDFBRA = 779; + public static final int SYSZ_INS_CDFR = 780; + public static final int SYSZ_INS_CDFTR = 781; + public static final int SYSZ_INS_CDGBRA = 782; + public static final int SYSZ_INS_CDGR = 783; + public static final int SYSZ_INS_CDGTR = 784; + public static final int SYSZ_INS_CDGTRA = 785; + public static final int SYSZ_INS_CDLFTR = 786; + public static final int SYSZ_INS_CDLGTR = 787; + public static final int SYSZ_INS_CDPT = 788; + public static final int SYSZ_INS_CDR = 789; + public static final int SYSZ_INS_CDS = 790; + public static final int SYSZ_INS_CDSG = 791; + public static final int SYSZ_INS_CDSTR = 792; + public static final int SYSZ_INS_CDSY = 793; + public static final int SYSZ_INS_CDTR = 794; + public static final int SYSZ_INS_CDUTR = 795; + public static final int SYSZ_INS_CDZT = 796; + public static final int SYSZ_INS_CE = 797; + public static final int SYSZ_INS_CEDTR = 798; + public static final int SYSZ_INS_CEFBRA = 799; + public static final int SYSZ_INS_CEFR = 800; + public static final int SYSZ_INS_CEGBRA = 801; + public static final int SYSZ_INS_CEGR = 802; + public static final int SYSZ_INS_CER = 803; + public static final int SYSZ_INS_CEXTR = 804; + public static final int SYSZ_INS_CFC = 805; + public static final int SYSZ_INS_CFDBRA = 806; + public static final int SYSZ_INS_CFDR = 807; + public static final int SYSZ_INS_CFDTR = 808; + public static final int SYSZ_INS_CFEBRA = 809; + public static final int SYSZ_INS_CFER = 810; + public static final int SYSZ_INS_CFXBRA = 811; + public static final int SYSZ_INS_CFXR = 812; + public static final int SYSZ_INS_CFXTR = 813; + public static final int SYSZ_INS_CGDBRA = 814; + public static final int SYSZ_INS_CGDR = 815; + public static final int SYSZ_INS_CGDTR = 816; + public static final int SYSZ_INS_CGDTRA = 817; + public static final int SYSZ_INS_CGEBRA = 818; + public static final int SYSZ_INS_CGER = 819; + public static final int SYSZ_INS_CGIB = 820; + public static final int SYSZ_INS_CGIBE = 821; + public static final int SYSZ_INS_CGIBH = 822; + public static final int SYSZ_INS_CGIBHE = 823; + public static final int SYSZ_INS_CGIBL = 824; + public static final int SYSZ_INS_CGIBLE = 825; + public static final int SYSZ_INS_CGIBLH = 826; + public static final int SYSZ_INS_CGIBNE = 827; + public static final int SYSZ_INS_CGIBNH = 828; + public static final int SYSZ_INS_CGIBNHE = 829; + public static final int SYSZ_INS_CGIBNL = 830; + public static final int SYSZ_INS_CGIBNLE = 831; + public static final int SYSZ_INS_CGIBNLH = 832; + public static final int SYSZ_INS_CGIT = 833; + public static final int SYSZ_INS_CGITE = 834; + public static final int SYSZ_INS_CGITH = 835; + public static final int SYSZ_INS_CGITHE = 836; + public static final int SYSZ_INS_CGITL = 837; + public static final int SYSZ_INS_CGITLE = 838; + public static final int SYSZ_INS_CGITLH = 839; + public static final int SYSZ_INS_CGITNE = 840; + public static final int SYSZ_INS_CGITNH = 841; + public static final int SYSZ_INS_CGITNHE = 842; + public static final int SYSZ_INS_CGITNL = 843; + public static final int SYSZ_INS_CGITNLE = 844; + public static final int SYSZ_INS_CGITNLH = 845; + public static final int SYSZ_INS_CGRB = 846; + public static final int SYSZ_INS_CGRBE = 847; + public static final int SYSZ_INS_CGRBH = 848; + public static final int SYSZ_INS_CGRBHE = 849; + public static final int SYSZ_INS_CGRBL = 850; + public static final int SYSZ_INS_CGRBLE = 851; + public static final int SYSZ_INS_CGRBLH = 852; + public static final int SYSZ_INS_CGRBNE = 853; + public static final int SYSZ_INS_CGRBNH = 854; + public static final int SYSZ_INS_CGRBNHE = 855; + public static final int SYSZ_INS_CGRBNL = 856; + public static final int SYSZ_INS_CGRBNLE = 857; + public static final int SYSZ_INS_CGRBNLH = 858; + public static final int SYSZ_INS_CGRT = 859; + public static final int SYSZ_INS_CGRTE = 860; + public static final int SYSZ_INS_CGRTH = 861; + public static final int SYSZ_INS_CGRTHE = 862; + public static final int SYSZ_INS_CGRTL = 863; + public static final int SYSZ_INS_CGRTLE = 864; + public static final int SYSZ_INS_CGRTLH = 865; + public static final int SYSZ_INS_CGRTNE = 866; + public static final int SYSZ_INS_CGRTNH = 867; + public static final int SYSZ_INS_CGRTNHE = 868; + public static final int SYSZ_INS_CGRTNL = 869; + public static final int SYSZ_INS_CGRTNLE = 870; + public static final int SYSZ_INS_CGRTNLH = 871; + public static final int SYSZ_INS_CGXBRA = 872; + public static final int SYSZ_INS_CGXR = 873; + public static final int SYSZ_INS_CGXTR = 874; + public static final int SYSZ_INS_CGXTRA = 875; + public static final int SYSZ_INS_CHHR = 876; + public static final int SYSZ_INS_CHLR = 877; + public static final int SYSZ_INS_CIB = 878; + public static final int SYSZ_INS_CIBE = 879; + public static final int SYSZ_INS_CIBH = 880; + public static final int SYSZ_INS_CIBHE = 881; + public static final int SYSZ_INS_CIBL = 882; + public static final int SYSZ_INS_CIBLE = 883; + public static final int SYSZ_INS_CIBLH = 884; + public static final int SYSZ_INS_CIBNE = 885; + public static final int SYSZ_INS_CIBNH = 886; + public static final int SYSZ_INS_CIBNHE = 887; + public static final int SYSZ_INS_CIBNL = 888; + public static final int SYSZ_INS_CIBNLE = 889; + public static final int SYSZ_INS_CIBNLH = 890; + public static final int SYSZ_INS_CIT = 891; + public static final int SYSZ_INS_CITE = 892; + public static final int SYSZ_INS_CITH = 893; + public static final int SYSZ_INS_CITHE = 894; + public static final int SYSZ_INS_CITL = 895; + public static final int SYSZ_INS_CITLE = 896; + public static final int SYSZ_INS_CITLH = 897; + public static final int SYSZ_INS_CITNE = 898; + public static final int SYSZ_INS_CITNH = 899; + public static final int SYSZ_INS_CITNHE = 900; + public static final int SYSZ_INS_CITNL = 901; + public static final int SYSZ_INS_CITNLE = 902; + public static final int SYSZ_INS_CITNLH = 903; + public static final int SYSZ_INS_CKSM = 904; + public static final int SYSZ_INS_CLCL = 905; + public static final int SYSZ_INS_CLCLE = 906; + public static final int SYSZ_INS_CLCLU = 907; + public static final int SYSZ_INS_CLFDTR = 908; + public static final int SYSZ_INS_CLFIT = 909; + public static final int SYSZ_INS_CLFITE = 910; + public static final int SYSZ_INS_CLFITH = 911; + public static final int SYSZ_INS_CLFITHE = 912; + public static final int SYSZ_INS_CLFITL = 913; + public static final int SYSZ_INS_CLFITLE = 914; + public static final int SYSZ_INS_CLFITLH = 915; + public static final int SYSZ_INS_CLFITNE = 916; + public static final int SYSZ_INS_CLFITNH = 917; + public static final int SYSZ_INS_CLFITNHE = 918; + public static final int SYSZ_INS_CLFITNL = 919; + public static final int SYSZ_INS_CLFITNLE = 920; + public static final int SYSZ_INS_CLFITNLH = 921; + public static final int SYSZ_INS_CLFXTR = 922; + public static final int SYSZ_INS_CLGDTR = 923; + public static final int SYSZ_INS_CLGIB = 924; + public static final int SYSZ_INS_CLGIBE = 925; + public static final int SYSZ_INS_CLGIBH = 926; + public static final int SYSZ_INS_CLGIBHE = 927; + public static final int SYSZ_INS_CLGIBL = 928; + public static final int SYSZ_INS_CLGIBLE = 929; + public static final int SYSZ_INS_CLGIBLH = 930; + public static final int SYSZ_INS_CLGIBNE = 931; + public static final int SYSZ_INS_CLGIBNH = 932; + public static final int SYSZ_INS_CLGIBNHE = 933; + public static final int SYSZ_INS_CLGIBNL = 934; + public static final int SYSZ_INS_CLGIBNLE = 935; + public static final int SYSZ_INS_CLGIBNLH = 936; + public static final int SYSZ_INS_CLGIT = 937; + public static final int SYSZ_INS_CLGITE = 938; + public static final int SYSZ_INS_CLGITH = 939; + public static final int SYSZ_INS_CLGITHE = 940; + public static final int SYSZ_INS_CLGITL = 941; + public static final int SYSZ_INS_CLGITLE = 942; + public static final int SYSZ_INS_CLGITLH = 943; + public static final int SYSZ_INS_CLGITNE = 944; + public static final int SYSZ_INS_CLGITNH = 945; + public static final int SYSZ_INS_CLGITNHE = 946; + public static final int SYSZ_INS_CLGITNL = 947; + public static final int SYSZ_INS_CLGITNLE = 948; + public static final int SYSZ_INS_CLGITNLH = 949; + public static final int SYSZ_INS_CLGRB = 950; + public static final int SYSZ_INS_CLGRBE = 951; + public static final int SYSZ_INS_CLGRBH = 952; + public static final int SYSZ_INS_CLGRBHE = 953; + public static final int SYSZ_INS_CLGRBL = 954; + public static final int SYSZ_INS_CLGRBLE = 955; + public static final int SYSZ_INS_CLGRBLH = 956; + public static final int SYSZ_INS_CLGRBNE = 957; + public static final int SYSZ_INS_CLGRBNH = 958; + public static final int SYSZ_INS_CLGRBNHE = 959; + public static final int SYSZ_INS_CLGRBNL = 960; + public static final int SYSZ_INS_CLGRBNLE = 961; + public static final int SYSZ_INS_CLGRBNLH = 962; + public static final int SYSZ_INS_CLGRT = 963; + public static final int SYSZ_INS_CLGRTE = 964; + public static final int SYSZ_INS_CLGRTH = 965; + public static final int SYSZ_INS_CLGRTHE = 966; + public static final int SYSZ_INS_CLGRTL = 967; + public static final int SYSZ_INS_CLGRTLE = 968; + public static final int SYSZ_INS_CLGRTLH = 969; + public static final int SYSZ_INS_CLGRTNE = 970; + public static final int SYSZ_INS_CLGRTNH = 971; + public static final int SYSZ_INS_CLGRTNHE = 972; + public static final int SYSZ_INS_CLGRTNL = 973; + public static final int SYSZ_INS_CLGRTNLE = 974; + public static final int SYSZ_INS_CLGRTNLH = 975; + public static final int SYSZ_INS_CLGT = 976; + public static final int SYSZ_INS_CLGTE = 977; + public static final int SYSZ_INS_CLGTH = 978; + public static final int SYSZ_INS_CLGTHE = 979; + public static final int SYSZ_INS_CLGTL = 980; + public static final int SYSZ_INS_CLGTLE = 981; + public static final int SYSZ_INS_CLGTLH = 982; + public static final int SYSZ_INS_CLGTNE = 983; + public static final int SYSZ_INS_CLGTNH = 984; + public static final int SYSZ_INS_CLGTNHE = 985; + public static final int SYSZ_INS_CLGTNL = 986; + public static final int SYSZ_INS_CLGTNLE = 987; + public static final int SYSZ_INS_CLGTNLH = 988; + public static final int SYSZ_INS_CLGXTR = 989; + public static final int SYSZ_INS_CLHHR = 990; + public static final int SYSZ_INS_CLHLR = 991; + public static final int SYSZ_INS_CLIB = 992; + public static final int SYSZ_INS_CLIBE = 993; + public static final int SYSZ_INS_CLIBH = 994; + public static final int SYSZ_INS_CLIBHE = 995; + public static final int SYSZ_INS_CLIBL = 996; + public static final int SYSZ_INS_CLIBLE = 997; + public static final int SYSZ_INS_CLIBLH = 998; + public static final int SYSZ_INS_CLIBNE = 999; + public static final int SYSZ_INS_CLIBNH = 1000; + public static final int SYSZ_INS_CLIBNHE = 1001; + public static final int SYSZ_INS_CLIBNL = 1002; + public static final int SYSZ_INS_CLIBNLE = 1003; + public static final int SYSZ_INS_CLIBNLH = 1004; + public static final int SYSZ_INS_CLM = 1005; + public static final int SYSZ_INS_CLMH = 1006; + public static final int SYSZ_INS_CLMY = 1007; + public static final int SYSZ_INS_CLRB = 1008; + public static final int SYSZ_INS_CLRBE = 1009; + public static final int SYSZ_INS_CLRBH = 1010; + public static final int SYSZ_INS_CLRBHE = 1011; + public static final int SYSZ_INS_CLRBL = 1012; + public static final int SYSZ_INS_CLRBLE = 1013; + public static final int SYSZ_INS_CLRBLH = 1014; + public static final int SYSZ_INS_CLRBNE = 1015; + public static final int SYSZ_INS_CLRBNH = 1016; + public static final int SYSZ_INS_CLRBNHE = 1017; + public static final int SYSZ_INS_CLRBNL = 1018; + public static final int SYSZ_INS_CLRBNLE = 1019; + public static final int SYSZ_INS_CLRBNLH = 1020; + public static final int SYSZ_INS_CLRT = 1021; + public static final int SYSZ_INS_CLRTE = 1022; + public static final int SYSZ_INS_CLRTH = 1023; + public static final int SYSZ_INS_CLRTHE = 1024; + public static final int SYSZ_INS_CLRTL = 1025; + public static final int SYSZ_INS_CLRTLE = 1026; + public static final int SYSZ_INS_CLRTLH = 1027; + public static final int SYSZ_INS_CLRTNE = 1028; + public static final int SYSZ_INS_CLRTNH = 1029; + public static final int SYSZ_INS_CLRTNHE = 1030; + public static final int SYSZ_INS_CLRTNL = 1031; + public static final int SYSZ_INS_CLRTNLE = 1032; + public static final int SYSZ_INS_CLRTNLH = 1033; + public static final int SYSZ_INS_CLT = 1034; + public static final int SYSZ_INS_CLTE = 1035; + public static final int SYSZ_INS_CLTH = 1036; + public static final int SYSZ_INS_CLTHE = 1037; + public static final int SYSZ_INS_CLTL = 1038; + public static final int SYSZ_INS_CLTLE = 1039; + public static final int SYSZ_INS_CLTLH = 1040; + public static final int SYSZ_INS_CLTNE = 1041; + public static final int SYSZ_INS_CLTNH = 1042; + public static final int SYSZ_INS_CLTNHE = 1043; + public static final int SYSZ_INS_CLTNL = 1044; + public static final int SYSZ_INS_CLTNLE = 1045; + public static final int SYSZ_INS_CLTNLH = 1046; + public static final int SYSZ_INS_CMPSC = 1047; + public static final int SYSZ_INS_CP = 1048; + public static final int SYSZ_INS_CPDT = 1049; + public static final int SYSZ_INS_CPXT = 1050; + public static final int SYSZ_INS_CPYA = 1051; + public static final int SYSZ_INS_CRB = 1052; + public static final int SYSZ_INS_CRBE = 1053; + public static final int SYSZ_INS_CRBH = 1054; + public static final int SYSZ_INS_CRBHE = 1055; + public static final int SYSZ_INS_CRBL = 1056; + public static final int SYSZ_INS_CRBLE = 1057; + public static final int SYSZ_INS_CRBLH = 1058; + public static final int SYSZ_INS_CRBNE = 1059; + public static final int SYSZ_INS_CRBNH = 1060; + public static final int SYSZ_INS_CRBNHE = 1061; + public static final int SYSZ_INS_CRBNL = 1062; + public static final int SYSZ_INS_CRBNLE = 1063; + public static final int SYSZ_INS_CRBNLH = 1064; + public static final int SYSZ_INS_CRDTE = 1065; + public static final int SYSZ_INS_CRT = 1066; + public static final int SYSZ_INS_CRTE = 1067; + public static final int SYSZ_INS_CRTH = 1068; + public static final int SYSZ_INS_CRTHE = 1069; + public static final int SYSZ_INS_CRTL = 1070; + public static final int SYSZ_INS_CRTLE = 1071; + public static final int SYSZ_INS_CRTLH = 1072; + public static final int SYSZ_INS_CRTNE = 1073; + public static final int SYSZ_INS_CRTNH = 1074; + public static final int SYSZ_INS_CRTNHE = 1075; + public static final int SYSZ_INS_CRTNL = 1076; + public static final int SYSZ_INS_CRTNLE = 1077; + public static final int SYSZ_INS_CRTNLH = 1078; + public static final int SYSZ_INS_CSCH = 1079; + public static final int SYSZ_INS_CSDTR = 1080; + public static final int SYSZ_INS_CSP = 1081; + public static final int SYSZ_INS_CSPG = 1082; + public static final int SYSZ_INS_CSST = 1083; + public static final int SYSZ_INS_CSXTR = 1084; + public static final int SYSZ_INS_CU12 = 1085; + public static final int SYSZ_INS_CU14 = 1086; + public static final int SYSZ_INS_CU21 = 1087; + public static final int SYSZ_INS_CU24 = 1088; + public static final int SYSZ_INS_CU41 = 1089; + public static final int SYSZ_INS_CU42 = 1090; + public static final int SYSZ_INS_CUDTR = 1091; + public static final int SYSZ_INS_CUSE = 1092; + public static final int SYSZ_INS_CUTFU = 1093; + public static final int SYSZ_INS_CUUTF = 1094; + public static final int SYSZ_INS_CUXTR = 1095; + public static final int SYSZ_INS_CVB = 1096; + public static final int SYSZ_INS_CVBG = 1097; + public static final int SYSZ_INS_CVBY = 1098; + public static final int SYSZ_INS_CVD = 1099; + public static final int SYSZ_INS_CVDG = 1100; + public static final int SYSZ_INS_CVDY = 1101; + public static final int SYSZ_INS_CXFBRA = 1102; + public static final int SYSZ_INS_CXFR = 1103; + public static final int SYSZ_INS_CXFTR = 1104; + public static final int SYSZ_INS_CXGBRA = 1105; + public static final int SYSZ_INS_CXGR = 1106; + public static final int SYSZ_INS_CXGTR = 1107; + public static final int SYSZ_INS_CXGTRA = 1108; + public static final int SYSZ_INS_CXLFTR = 1109; + public static final int SYSZ_INS_CXLGTR = 1110; + public static final int SYSZ_INS_CXPT = 1111; + public static final int SYSZ_INS_CXR = 1112; + public static final int SYSZ_INS_CXSTR = 1113; + public static final int SYSZ_INS_CXTR = 1114; + public static final int SYSZ_INS_CXUTR = 1115; + public static final int SYSZ_INS_CXZT = 1116; + public static final int SYSZ_INS_CZDT = 1117; + public static final int SYSZ_INS_CZXT = 1118; + public static final int SYSZ_INS_D = 1119; + public static final int SYSZ_INS_DD = 1120; + public static final int SYSZ_INS_DDR = 1121; + public static final int SYSZ_INS_DDTR = 1122; + public static final int SYSZ_INS_DDTRA = 1123; + public static final int SYSZ_INS_DE = 1124; + public static final int SYSZ_INS_DER = 1125; + public static final int SYSZ_INS_DIAG = 1126; + public static final int SYSZ_INS_DIDBR = 1127; + public static final int SYSZ_INS_DIEBR = 1128; + public static final int SYSZ_INS_DP = 1129; + public static final int SYSZ_INS_DR = 1130; + public static final int SYSZ_INS_DXR = 1131; + public static final int SYSZ_INS_DXTR = 1132; + public static final int SYSZ_INS_DXTRA = 1133; + public static final int SYSZ_INS_ECAG = 1134; + public static final int SYSZ_INS_ECCTR = 1135; + public static final int SYSZ_INS_ECPGA = 1136; + public static final int SYSZ_INS_ECTG = 1137; + public static final int SYSZ_INS_ED = 1138; + public static final int SYSZ_INS_EDMK = 1139; + public static final int SYSZ_INS_EEDTR = 1140; + public static final int SYSZ_INS_EEXTR = 1141; + public static final int SYSZ_INS_EFPC = 1142; + public static final int SYSZ_INS_EPAIR = 1143; + public static final int SYSZ_INS_EPAR = 1144; + public static final int SYSZ_INS_EPCTR = 1145; + public static final int SYSZ_INS_EPSW = 1146; + public static final int SYSZ_INS_EREG = 1147; + public static final int SYSZ_INS_EREGG = 1148; + public static final int SYSZ_INS_ESAIR = 1149; + public static final int SYSZ_INS_ESAR = 1150; + public static final int SYSZ_INS_ESDTR = 1151; + public static final int SYSZ_INS_ESEA = 1152; + public static final int SYSZ_INS_ESTA = 1153; + public static final int SYSZ_INS_ESXTR = 1154; + public static final int SYSZ_INS_ETND = 1155; + public static final int SYSZ_INS_EX = 1156; + public static final int SYSZ_INS_EXRL = 1157; + public static final int SYSZ_INS_FIDR = 1158; + public static final int SYSZ_INS_FIDTR = 1159; + public static final int SYSZ_INS_FIER = 1160; + public static final int SYSZ_INS_FIXR = 1161; + public static final int SYSZ_INS_FIXTR = 1162; + public static final int SYSZ_INS_HDR = 1163; + public static final int SYSZ_INS_HER = 1164; + public static final int SYSZ_INS_HSCH = 1165; + public static final int SYSZ_INS_IAC = 1166; + public static final int SYSZ_INS_ICM = 1167; + public static final int SYSZ_INS_ICMH = 1168; + public static final int SYSZ_INS_ICMY = 1169; + public static final int SYSZ_INS_IDTE = 1170; + public static final int SYSZ_INS_IEDTR = 1171; + public static final int SYSZ_INS_IEXTR = 1172; + public static final int SYSZ_INS_IPK = 1173; + public static final int SYSZ_INS_IPTE = 1174; + public static final int SYSZ_INS_IRBM = 1175; + public static final int SYSZ_INS_ISKE = 1176; + public static final int SYSZ_INS_IVSK = 1177; + public static final int SYSZ_INS_JGM = 1178; + public static final int SYSZ_INS_JGNM = 1179; + public static final int SYSZ_INS_JGNP = 1180; + public static final int SYSZ_INS_JGNZ = 1181; + public static final int SYSZ_INS_JGP = 1182; + public static final int SYSZ_INS_JGZ = 1183; + public static final int SYSZ_INS_JM = 1184; + public static final int SYSZ_INS_JNM = 1185; + public static final int SYSZ_INS_JNP = 1186; + public static final int SYSZ_INS_JNZ = 1187; + public static final int SYSZ_INS_JP = 1188; + public static final int SYSZ_INS_JZ = 1189; + public static final int SYSZ_INS_KDB = 1190; + public static final int SYSZ_INS_KDBR = 1191; + public static final int SYSZ_INS_KDTR = 1192; + public static final int SYSZ_INS_KEB = 1193; + public static final int SYSZ_INS_KEBR = 1194; + public static final int SYSZ_INS_KIMD = 1195; + public static final int SYSZ_INS_KLMD = 1196; + public static final int SYSZ_INS_KM = 1197; + public static final int SYSZ_INS_KMA = 1198; + public static final int SYSZ_INS_KMAC = 1199; + public static final int SYSZ_INS_KMC = 1200; + public static final int SYSZ_INS_KMCTR = 1201; + public static final int SYSZ_INS_KMF = 1202; + public static final int SYSZ_INS_KMO = 1203; + public static final int SYSZ_INS_KXBR = 1204; + public static final int SYSZ_INS_KXTR = 1205; + public static final int SYSZ_INS_LAE = 1206; + public static final int SYSZ_INS_LAEY = 1207; + public static final int SYSZ_INS_LAM = 1208; + public static final int SYSZ_INS_LAMY = 1209; + public static final int SYSZ_INS_LASP = 1210; + public static final int SYSZ_INS_LAT = 1211; + public static final int SYSZ_INS_LCBB = 1212; + public static final int SYSZ_INS_LCCTL = 1213; + public static final int SYSZ_INS_LCDFR = 1214; + public static final int SYSZ_INS_LCDR = 1215; + public static final int SYSZ_INS_LCER = 1216; + public static final int SYSZ_INS_LCTL = 1217; + public static final int SYSZ_INS_LCTLG = 1218; + public static final int SYSZ_INS_LCXR = 1219; + public static final int SYSZ_INS_LDE = 1220; + public static final int SYSZ_INS_LDER = 1221; + public static final int SYSZ_INS_LDETR = 1222; + public static final int SYSZ_INS_LDXR = 1223; + public static final int SYSZ_INS_LDXTR = 1224; + public static final int SYSZ_INS_LEDR = 1225; + public static final int SYSZ_INS_LEDTR = 1226; + public static final int SYSZ_INS_LEXR = 1227; + public static final int SYSZ_INS_LFAS = 1228; + public static final int SYSZ_INS_LFHAT = 1229; + public static final int SYSZ_INS_LFPC = 1230; + public static final int SYSZ_INS_LGAT = 1231; + public static final int SYSZ_INS_LGG = 1232; + public static final int SYSZ_INS_LGSC = 1233; + public static final int SYSZ_INS_LLGFAT = 1234; + public static final int SYSZ_INS_LLGFSG = 1235; + public static final int SYSZ_INS_LLGT = 1236; + public static final int SYSZ_INS_LLGTAT = 1237; + public static final int SYSZ_INS_LLGTR = 1238; + public static final int SYSZ_INS_LLZRGF = 1239; + public static final int SYSZ_INS_LM = 1240; + public static final int SYSZ_INS_LMD = 1241; + public static final int SYSZ_INS_LMH = 1242; + public static final int SYSZ_INS_LMY = 1243; + public static final int SYSZ_INS_LNDFR = 1244; + public static final int SYSZ_INS_LNDR = 1245; + public static final int SYSZ_INS_LNER = 1246; + public static final int SYSZ_INS_LNXR = 1247; + public static final int SYSZ_INS_LOCFH = 1248; + public static final int SYSZ_INS_LOCFHE = 1249; + public static final int SYSZ_INS_LOCFHH = 1250; + public static final int SYSZ_INS_LOCFHHE = 1251; + public static final int SYSZ_INS_LOCFHL = 1252; + public static final int SYSZ_INS_LOCFHLE = 1253; + public static final int SYSZ_INS_LOCFHLH = 1254; + public static final int SYSZ_INS_LOCFHM = 1255; + public static final int SYSZ_INS_LOCFHNE = 1256; + public static final int SYSZ_INS_LOCFHNH = 1257; + public static final int SYSZ_INS_LOCFHNHE = 1258; + public static final int SYSZ_INS_LOCFHNL = 1259; + public static final int SYSZ_INS_LOCFHNLE = 1260; + public static final int SYSZ_INS_LOCFHNLH = 1261; + public static final int SYSZ_INS_LOCFHNM = 1262; + public static final int SYSZ_INS_LOCFHNO = 1263; + public static final int SYSZ_INS_LOCFHNP = 1264; + public static final int SYSZ_INS_LOCFHNZ = 1265; + public static final int SYSZ_INS_LOCFHO = 1266; + public static final int SYSZ_INS_LOCFHP = 1267; + public static final int SYSZ_INS_LOCFHR = 1268; + public static final int SYSZ_INS_LOCFHRE = 1269; + public static final int SYSZ_INS_LOCFHRH = 1270; + public static final int SYSZ_INS_LOCFHRHE = 1271; + public static final int SYSZ_INS_LOCFHRL = 1272; + public static final int SYSZ_INS_LOCFHRLE = 1273; + public static final int SYSZ_INS_LOCFHRLH = 1274; + public static final int SYSZ_INS_LOCFHRM = 1275; + public static final int SYSZ_INS_LOCFHRNE = 1276; + public static final int SYSZ_INS_LOCFHRNH = 1277; + public static final int SYSZ_INS_LOCFHRNHE = 1278; + public static final int SYSZ_INS_LOCFHRNL = 1279; + public static final int SYSZ_INS_LOCFHRNLE = 1280; + public static final int SYSZ_INS_LOCFHRNLH = 1281; + public static final int SYSZ_INS_LOCFHRNM = 1282; + public static final int SYSZ_INS_LOCFHRNO = 1283; + public static final int SYSZ_INS_LOCFHRNP = 1284; + public static final int SYSZ_INS_LOCFHRNZ = 1285; + public static final int SYSZ_INS_LOCFHRO = 1286; + public static final int SYSZ_INS_LOCFHRP = 1287; + public static final int SYSZ_INS_LOCFHRZ = 1288; + public static final int SYSZ_INS_LOCFHZ = 1289; + public static final int SYSZ_INS_LOCGHI = 1290; + public static final int SYSZ_INS_LOCGHIE = 1291; + public static final int SYSZ_INS_LOCGHIH = 1292; + public static final int SYSZ_INS_LOCGHIHE = 1293; + public static final int SYSZ_INS_LOCGHIL = 1294; + public static final int SYSZ_INS_LOCGHILE = 1295; + public static final int SYSZ_INS_LOCGHILH = 1296; + public static final int SYSZ_INS_LOCGHIM = 1297; + public static final int SYSZ_INS_LOCGHINE = 1298; + public static final int SYSZ_INS_LOCGHINH = 1299; + public static final int SYSZ_INS_LOCGHINHE = 1300; + public static final int SYSZ_INS_LOCGHINL = 1301; + public static final int SYSZ_INS_LOCGHINLE = 1302; + public static final int SYSZ_INS_LOCGHINLH = 1303; + public static final int SYSZ_INS_LOCGHINM = 1304; + public static final int SYSZ_INS_LOCGHINO = 1305; + public static final int SYSZ_INS_LOCGHINP = 1306; + public static final int SYSZ_INS_LOCGHINZ = 1307; + public static final int SYSZ_INS_LOCGHIO = 1308; + public static final int SYSZ_INS_LOCGHIP = 1309; + public static final int SYSZ_INS_LOCGHIZ = 1310; + public static final int SYSZ_INS_LOCGM = 1311; + public static final int SYSZ_INS_LOCGNM = 1312; + public static final int SYSZ_INS_LOCGNP = 1313; + public static final int SYSZ_INS_LOCGNZ = 1314; + public static final int SYSZ_INS_LOCGP = 1315; + public static final int SYSZ_INS_LOCGRM = 1316; + public static final int SYSZ_INS_LOCGRNM = 1317; + public static final int SYSZ_INS_LOCGRNP = 1318; + public static final int SYSZ_INS_LOCGRNZ = 1319; + public static final int SYSZ_INS_LOCGRP = 1320; + public static final int SYSZ_INS_LOCGRZ = 1321; + public static final int SYSZ_INS_LOCGZ = 1322; + public static final int SYSZ_INS_LOCHHI = 1323; + public static final int SYSZ_INS_LOCHHIE = 1324; + public static final int SYSZ_INS_LOCHHIH = 1325; + public static final int SYSZ_INS_LOCHHIHE = 1326; + public static final int SYSZ_INS_LOCHHIL = 1327; + public static final int SYSZ_INS_LOCHHILE = 1328; + public static final int SYSZ_INS_LOCHHILH = 1329; + public static final int SYSZ_INS_LOCHHIM = 1330; + public static final int SYSZ_INS_LOCHHINE = 1331; + public static final int SYSZ_INS_LOCHHINH = 1332; + public static final int SYSZ_INS_LOCHHINHE = 1333; + public static final int SYSZ_INS_LOCHHINL = 1334; + public static final int SYSZ_INS_LOCHHINLE = 1335; + public static final int SYSZ_INS_LOCHHINLH = 1336; + public static final int SYSZ_INS_LOCHHINM = 1337; + public static final int SYSZ_INS_LOCHHINO = 1338; + public static final int SYSZ_INS_LOCHHINP = 1339; + public static final int SYSZ_INS_LOCHHINZ = 1340; + public static final int SYSZ_INS_LOCHHIO = 1341; + public static final int SYSZ_INS_LOCHHIP = 1342; + public static final int SYSZ_INS_LOCHHIZ = 1343; + public static final int SYSZ_INS_LOCHI = 1344; + public static final int SYSZ_INS_LOCHIE = 1345; + public static final int SYSZ_INS_LOCHIH = 1346; + public static final int SYSZ_INS_LOCHIHE = 1347; + public static final int SYSZ_INS_LOCHIL = 1348; + public static final int SYSZ_INS_LOCHILE = 1349; + public static final int SYSZ_INS_LOCHILH = 1350; + public static final int SYSZ_INS_LOCHIM = 1351; + public static final int SYSZ_INS_LOCHINE = 1352; + public static final int SYSZ_INS_LOCHINH = 1353; + public static final int SYSZ_INS_LOCHINHE = 1354; + public static final int SYSZ_INS_LOCHINL = 1355; + public static final int SYSZ_INS_LOCHINLE = 1356; + public static final int SYSZ_INS_LOCHINLH = 1357; + public static final int SYSZ_INS_LOCHINM = 1358; + public static final int SYSZ_INS_LOCHINO = 1359; + public static final int SYSZ_INS_LOCHINP = 1360; + public static final int SYSZ_INS_LOCHINZ = 1361; + public static final int SYSZ_INS_LOCHIO = 1362; + public static final int SYSZ_INS_LOCHIP = 1363; + public static final int SYSZ_INS_LOCHIZ = 1364; + public static final int SYSZ_INS_LOCM = 1365; + public static final int SYSZ_INS_LOCNM = 1366; + public static final int SYSZ_INS_LOCNP = 1367; + public static final int SYSZ_INS_LOCNZ = 1368; + public static final int SYSZ_INS_LOCP = 1369; + public static final int SYSZ_INS_LOCRM = 1370; + public static final int SYSZ_INS_LOCRNM = 1371; + public static final int SYSZ_INS_LOCRNP = 1372; + public static final int SYSZ_INS_LOCRNZ = 1373; + public static final int SYSZ_INS_LOCRP = 1374; + public static final int SYSZ_INS_LOCRZ = 1375; + public static final int SYSZ_INS_LOCZ = 1376; + public static final int SYSZ_INS_LPCTL = 1377; + public static final int SYSZ_INS_LPD = 1378; + public static final int SYSZ_INS_LPDFR = 1379; + public static final int SYSZ_INS_LPDG = 1380; + public static final int SYSZ_INS_LPDR = 1381; + public static final int SYSZ_INS_LPER = 1382; + public static final int SYSZ_INS_LPP = 1383; + public static final int SYSZ_INS_LPQ = 1384; + public static final int SYSZ_INS_LPSW = 1385; + public static final int SYSZ_INS_LPSWE = 1386; + public static final int SYSZ_INS_LPTEA = 1387; + public static final int SYSZ_INS_LPXR = 1388; + public static final int SYSZ_INS_LRA = 1389; + public static final int SYSZ_INS_LRAG = 1390; + public static final int SYSZ_INS_LRAY = 1391; + public static final int SYSZ_INS_LRDR = 1392; + public static final int SYSZ_INS_LRER = 1393; + public static final int SYSZ_INS_LRVH = 1394; + public static final int SYSZ_INS_LSCTL = 1395; + public static final int SYSZ_INS_LTDR = 1396; + public static final int SYSZ_INS_LTDTR = 1397; + public static final int SYSZ_INS_LTER = 1398; + public static final int SYSZ_INS_LTXR = 1399; + public static final int SYSZ_INS_LTXTR = 1400; + public static final int SYSZ_INS_LURA = 1401; + public static final int SYSZ_INS_LURAG = 1402; + public static final int SYSZ_INS_LXD = 1403; + public static final int SYSZ_INS_LXDR = 1404; + public static final int SYSZ_INS_LXDTR = 1405; + public static final int SYSZ_INS_LXE = 1406; + public static final int SYSZ_INS_LXER = 1407; + public static final int SYSZ_INS_LZRF = 1408; + public static final int SYSZ_INS_LZRG = 1409; + public static final int SYSZ_INS_M = 1410; + public static final int SYSZ_INS_MAD = 1411; + public static final int SYSZ_INS_MADR = 1412; + public static final int SYSZ_INS_MAE = 1413; + public static final int SYSZ_INS_MAER = 1414; + public static final int SYSZ_INS_MAY = 1415; + public static final int SYSZ_INS_MAYH = 1416; + public static final int SYSZ_INS_MAYHR = 1417; + public static final int SYSZ_INS_MAYL = 1418; + public static final int SYSZ_INS_MAYLR = 1419; + public static final int SYSZ_INS_MAYR = 1420; + public static final int SYSZ_INS_MC = 1421; + public static final int SYSZ_INS_MD = 1422; + public static final int SYSZ_INS_MDE = 1423; + public static final int SYSZ_INS_MDER = 1424; + public static final int SYSZ_INS_MDR = 1425; + public static final int SYSZ_INS_MDTR = 1426; + public static final int SYSZ_INS_MDTRA = 1427; + public static final int SYSZ_INS_ME = 1428; + public static final int SYSZ_INS_MEE = 1429; + public static final int SYSZ_INS_MEER = 1430; + public static final int SYSZ_INS_MER = 1431; + public static final int SYSZ_INS_MFY = 1432; + public static final int SYSZ_INS_MG = 1433; + public static final int SYSZ_INS_MGH = 1434; + public static final int SYSZ_INS_MGRK = 1435; + public static final int SYSZ_INS_ML = 1436; + public static final int SYSZ_INS_MLR = 1437; + public static final int SYSZ_INS_MP = 1438; + public static final int SYSZ_INS_MR = 1439; + public static final int SYSZ_INS_MSC = 1440; + public static final int SYSZ_INS_MSCH = 1441; + public static final int SYSZ_INS_MSD = 1442; + public static final int SYSZ_INS_MSDR = 1443; + public static final int SYSZ_INS_MSE = 1444; + public static final int SYSZ_INS_MSER = 1445; + public static final int SYSZ_INS_MSGC = 1446; + public static final int SYSZ_INS_MSGRKC = 1447; + public static final int SYSZ_INS_MSRKC = 1448; + public static final int SYSZ_INS_MSTA = 1449; + public static final int SYSZ_INS_MVCDK = 1450; + public static final int SYSZ_INS_MVCIN = 1451; + public static final int SYSZ_INS_MVCK = 1452; + public static final int SYSZ_INS_MVCL = 1453; + public static final int SYSZ_INS_MVCLE = 1454; + public static final int SYSZ_INS_MVCLU = 1455; + public static final int SYSZ_INS_MVCOS = 1456; + public static final int SYSZ_INS_MVCP = 1457; + public static final int SYSZ_INS_MVCS = 1458; + public static final int SYSZ_INS_MVCSK = 1459; + public static final int SYSZ_INS_MVN = 1460; + public static final int SYSZ_INS_MVO = 1461; + public static final int SYSZ_INS_MVPG = 1462; + public static final int SYSZ_INS_MVZ = 1463; + public static final int SYSZ_INS_MXD = 1464; + public static final int SYSZ_INS_MXDR = 1465; + public static final int SYSZ_INS_MXR = 1466; + public static final int SYSZ_INS_MXTR = 1467; + public static final int SYSZ_INS_MXTRA = 1468; + public static final int SYSZ_INS_MY = 1469; + public static final int SYSZ_INS_MYH = 1470; + public static final int SYSZ_INS_MYHR = 1471; + public static final int SYSZ_INS_MYL = 1472; + public static final int SYSZ_INS_MYLR = 1473; + public static final int SYSZ_INS_MYR = 1474; + public static final int SYSZ_INS_NIAI = 1475; + public static final int SYSZ_INS_NTSTG = 1476; + public static final int SYSZ_INS_PACK = 1477; + public static final int SYSZ_INS_PALB = 1478; + public static final int SYSZ_INS_PC = 1479; + public static final int SYSZ_INS_PCC = 1480; + public static final int SYSZ_INS_PCKMO = 1481; + public static final int SYSZ_INS_PFMF = 1482; + public static final int SYSZ_INS_PFPO = 1483; + public static final int SYSZ_INS_PGIN = 1484; + public static final int SYSZ_INS_PGOUT = 1485; + public static final int SYSZ_INS_PKA = 1486; + public static final int SYSZ_INS_PKU = 1487; + public static final int SYSZ_INS_PLO = 1488; + public static final int SYSZ_INS_POPCNT = 1489; + public static final int SYSZ_INS_PPA = 1490; + public static final int SYSZ_INS_PPNO = 1491; + public static final int SYSZ_INS_PR = 1492; + public static final int SYSZ_INS_PRNO = 1493; + public static final int SYSZ_INS_PT = 1494; + public static final int SYSZ_INS_PTF = 1495; + public static final int SYSZ_INS_PTFF = 1496; + public static final int SYSZ_INS_PTI = 1497; + public static final int SYSZ_INS_PTLB = 1498; + public static final int SYSZ_INS_QADTR = 1499; + public static final int SYSZ_INS_QAXTR = 1500; + public static final int SYSZ_INS_QCTRI = 1501; + public static final int SYSZ_INS_QSI = 1502; + public static final int SYSZ_INS_RCHP = 1503; + public static final int SYSZ_INS_RISBGN = 1504; + public static final int SYSZ_INS_RP = 1505; + public static final int SYSZ_INS_RRBE = 1506; + public static final int SYSZ_INS_RRBM = 1507; + public static final int SYSZ_INS_RRDTR = 1508; + public static final int SYSZ_INS_RRXTR = 1509; + public static final int SYSZ_INS_RSCH = 1510; + public static final int SYSZ_INS_SAC = 1511; + public static final int SYSZ_INS_SACF = 1512; + public static final int SYSZ_INS_SAL = 1513; + public static final int SYSZ_INS_SAM24 = 1514; + public static final int SYSZ_INS_SAM31 = 1515; + public static final int SYSZ_INS_SAM64 = 1516; + public static final int SYSZ_INS_SAR = 1517; + public static final int SYSZ_INS_SCCTR = 1518; + public static final int SYSZ_INS_SCHM = 1519; + public static final int SYSZ_INS_SCK = 1520; + public static final int SYSZ_INS_SCKC = 1521; + public static final int SYSZ_INS_SCKPF = 1522; + public static final int SYSZ_INS_SD = 1523; + public static final int SYSZ_INS_SDR = 1524; + public static final int SYSZ_INS_SDTR = 1525; + public static final int SYSZ_INS_SDTRA = 1526; + public static final int SYSZ_INS_SE = 1527; + public static final int SYSZ_INS_SER = 1528; + public static final int SYSZ_INS_SFASR = 1529; + public static final int SYSZ_INS_SFPC = 1530; + public static final int SYSZ_INS_SGH = 1531; + public static final int SYSZ_INS_SHHHR = 1532; + public static final int SYSZ_INS_SHHLR = 1533; + public static final int SYSZ_INS_SIE = 1534; + public static final int SYSZ_INS_SIGA = 1535; + public static final int SYSZ_INS_SIGP = 1536; + public static final int SYSZ_INS_SLA = 1537; + public static final int SYSZ_INS_SLAG = 1538; + public static final int SYSZ_INS_SLAK = 1539; + public static final int SYSZ_INS_SLDA = 1540; + public static final int SYSZ_INS_SLDL = 1541; + public static final int SYSZ_INS_SLDT = 1542; + public static final int SYSZ_INS_SLHHHR = 1543; + public static final int SYSZ_INS_SLHHLR = 1544; + public static final int SYSZ_INS_SLXT = 1545; + public static final int SYSZ_INS_SP = 1546; + public static final int SYSZ_INS_SPCTR = 1547; + public static final int SYSZ_INS_SPKA = 1548; + public static final int SYSZ_INS_SPM = 1549; + public static final int SYSZ_INS_SPT = 1550; + public static final int SYSZ_INS_SPX = 1551; + public static final int SYSZ_INS_SQD = 1552; + public static final int SYSZ_INS_SQDR = 1553; + public static final int SYSZ_INS_SQE = 1554; + public static final int SYSZ_INS_SQER = 1555; + public static final int SYSZ_INS_SQXR = 1556; + public static final int SYSZ_INS_SRDA = 1557; + public static final int SYSZ_INS_SRDL = 1558; + public static final int SYSZ_INS_SRDT = 1559; + public static final int SYSZ_INS_SRNM = 1560; + public static final int SYSZ_INS_SRNMB = 1561; + public static final int SYSZ_INS_SRNMT = 1562; + public static final int SYSZ_INS_SRP = 1563; + public static final int SYSZ_INS_SRSTU = 1564; + public static final int SYSZ_INS_SRXT = 1565; + public static final int SYSZ_INS_SSAIR = 1566; + public static final int SYSZ_INS_SSAR = 1567; + public static final int SYSZ_INS_SSCH = 1568; + public static final int SYSZ_INS_SSKE = 1569; + public static final int SYSZ_INS_SSM = 1570; + public static final int SYSZ_INS_STAM = 1571; + public static final int SYSZ_INS_STAMY = 1572; + public static final int SYSZ_INS_STAP = 1573; + public static final int SYSZ_INS_STCK = 1574; + public static final int SYSZ_INS_STCKC = 1575; + public static final int SYSZ_INS_STCKE = 1576; + public static final int SYSZ_INS_STCKF = 1577; + public static final int SYSZ_INS_STCM = 1578; + public static final int SYSZ_INS_STCMH = 1579; + public static final int SYSZ_INS_STCMY = 1580; + public static final int SYSZ_INS_STCPS = 1581; + public static final int SYSZ_INS_STCRW = 1582; + public static final int SYSZ_INS_STCTG = 1583; + public static final int SYSZ_INS_STCTL = 1584; + public static final int SYSZ_INS_STFL = 1585; + public static final int SYSZ_INS_STFLE = 1586; + public static final int SYSZ_INS_STFPC = 1587; + public static final int SYSZ_INS_STGSC = 1588; + public static final int SYSZ_INS_STIDP = 1589; + public static final int SYSZ_INS_STM = 1590; + public static final int SYSZ_INS_STMH = 1591; + public static final int SYSZ_INS_STMY = 1592; + public static final int SYSZ_INS_STNSM = 1593; + public static final int SYSZ_INS_STOCFH = 1594; + public static final int SYSZ_INS_STOCFHE = 1595; + public static final int SYSZ_INS_STOCFHH = 1596; + public static final int SYSZ_INS_STOCFHHE = 1597; + public static final int SYSZ_INS_STOCFHL = 1598; + public static final int SYSZ_INS_STOCFHLE = 1599; + public static final int SYSZ_INS_STOCFHLH = 1600; + public static final int SYSZ_INS_STOCFHM = 1601; + public static final int SYSZ_INS_STOCFHNE = 1602; + public static final int SYSZ_INS_STOCFHNH = 1603; + public static final int SYSZ_INS_STOCFHNHE = 1604; + public static final int SYSZ_INS_STOCFHNL = 1605; + public static final int SYSZ_INS_STOCFHNLE = 1606; + public static final int SYSZ_INS_STOCFHNLH = 1607; + public static final int SYSZ_INS_STOCFHNM = 1608; + public static final int SYSZ_INS_STOCFHNO = 1609; + public static final int SYSZ_INS_STOCFHNP = 1610; + public static final int SYSZ_INS_STOCFHNZ = 1611; + public static final int SYSZ_INS_STOCFHO = 1612; + public static final int SYSZ_INS_STOCFHP = 1613; + public static final int SYSZ_INS_STOCFHZ = 1614; + public static final int SYSZ_INS_STOCGM = 1615; + public static final int SYSZ_INS_STOCGNM = 1616; + public static final int SYSZ_INS_STOCGNP = 1617; + public static final int SYSZ_INS_STOCGNZ = 1618; + public static final int SYSZ_INS_STOCGP = 1619; + public static final int SYSZ_INS_STOCGZ = 1620; + public static final int SYSZ_INS_STOCM = 1621; + public static final int SYSZ_INS_STOCNM = 1622; + public static final int SYSZ_INS_STOCNP = 1623; + public static final int SYSZ_INS_STOCNZ = 1624; + public static final int SYSZ_INS_STOCP = 1625; + public static final int SYSZ_INS_STOCZ = 1626; + public static final int SYSZ_INS_STOSM = 1627; + public static final int SYSZ_INS_STPQ = 1628; + public static final int SYSZ_INS_STPT = 1629; + public static final int SYSZ_INS_STPX = 1630; + public static final int SYSZ_INS_STRAG = 1631; + public static final int SYSZ_INS_STRVH = 1632; + public static final int SYSZ_INS_STSCH = 1633; + public static final int SYSZ_INS_STSI = 1634; + public static final int SYSZ_INS_STURA = 1635; + public static final int SYSZ_INS_STURG = 1636; + public static final int SYSZ_INS_SU = 1637; + public static final int SYSZ_INS_SUR = 1638; + public static final int SYSZ_INS_SVC = 1639; + public static final int SYSZ_INS_SW = 1640; + public static final int SYSZ_INS_SWR = 1641; + public static final int SYSZ_INS_SXR = 1642; + public static final int SYSZ_INS_SXTR = 1643; + public static final int SYSZ_INS_SXTRA = 1644; + public static final int SYSZ_INS_TABORT = 1645; + public static final int SYSZ_INS_TAM = 1646; + public static final int SYSZ_INS_TAR = 1647; + public static final int SYSZ_INS_TB = 1648; + public static final int SYSZ_INS_TBDR = 1649; + public static final int SYSZ_INS_TBEDR = 1650; + public static final int SYSZ_INS_TBEGIN = 1651; + public static final int SYSZ_INS_TBEGINC = 1652; + public static final int SYSZ_INS_TCDB = 1653; + public static final int SYSZ_INS_TCEB = 1654; + public static final int SYSZ_INS_TCXB = 1655; + public static final int SYSZ_INS_TDCDT = 1656; + public static final int SYSZ_INS_TDCET = 1657; + public static final int SYSZ_INS_TDCXT = 1658; + public static final int SYSZ_INS_TDGDT = 1659; + public static final int SYSZ_INS_TDGET = 1660; + public static final int SYSZ_INS_TDGXT = 1661; + public static final int SYSZ_INS_TEND = 1662; + public static final int SYSZ_INS_THDER = 1663; + public static final int SYSZ_INS_THDR = 1664; + public static final int SYSZ_INS_TP = 1665; + public static final int SYSZ_INS_TPI = 1666; + public static final int SYSZ_INS_TPROT = 1667; + public static final int SYSZ_INS_TR = 1668; + public static final int SYSZ_INS_TRACE = 1669; + public static final int SYSZ_INS_TRACG = 1670; + public static final int SYSZ_INS_TRAP2 = 1671; + public static final int SYSZ_INS_TRAP4 = 1672; + public static final int SYSZ_INS_TRE = 1673; + public static final int SYSZ_INS_TROO = 1674; + public static final int SYSZ_INS_TROT = 1675; + public static final int SYSZ_INS_TRT = 1676; + public static final int SYSZ_INS_TRTE = 1677; + public static final int SYSZ_INS_TRTO = 1678; + public static final int SYSZ_INS_TRTR = 1679; + public static final int SYSZ_INS_TRTRE = 1680; + public static final int SYSZ_INS_TRTT = 1681; + public static final int SYSZ_INS_TS = 1682; + public static final int SYSZ_INS_TSCH = 1683; + public static final int SYSZ_INS_UNPK = 1684; + public static final int SYSZ_INS_UNPKA = 1685; + public static final int SYSZ_INS_UNPKU = 1686; + public static final int SYSZ_INS_UPT = 1687; + public static final int SYSZ_INS_VA = 1688; + public static final int SYSZ_INS_VAB = 1689; + public static final int SYSZ_INS_VAC = 1690; + public static final int SYSZ_INS_VACC = 1691; + public static final int SYSZ_INS_VACCB = 1692; + public static final int SYSZ_INS_VACCC = 1693; + public static final int SYSZ_INS_VACCCQ = 1694; + public static final int SYSZ_INS_VACCF = 1695; + public static final int SYSZ_INS_VACCG = 1696; + public static final int SYSZ_INS_VACCH = 1697; + public static final int SYSZ_INS_VACCQ = 1698; + public static final int SYSZ_INS_VACQ = 1699; + public static final int SYSZ_INS_VAF = 1700; + public static final int SYSZ_INS_VAG = 1701; + public static final int SYSZ_INS_VAH = 1702; + public static final int SYSZ_INS_VAP = 1703; + public static final int SYSZ_INS_VAQ = 1704; + public static final int SYSZ_INS_VAVG = 1705; + public static final int SYSZ_INS_VAVGB = 1706; + public static final int SYSZ_INS_VAVGF = 1707; + public static final int SYSZ_INS_VAVGG = 1708; + public static final int SYSZ_INS_VAVGH = 1709; + public static final int SYSZ_INS_VAVGL = 1710; + public static final int SYSZ_INS_VAVGLB = 1711; + public static final int SYSZ_INS_VAVGLF = 1712; + public static final int SYSZ_INS_VAVGLG = 1713; + public static final int SYSZ_INS_VAVGLH = 1714; + public static final int SYSZ_INS_VBPERM = 1715; + public static final int SYSZ_INS_VCDG = 1716; + public static final int SYSZ_INS_VCDGB = 1717; + public static final int SYSZ_INS_VCDLG = 1718; + public static final int SYSZ_INS_VCDLGB = 1719; + public static final int SYSZ_INS_VCEQ = 1720; + public static final int SYSZ_INS_VCEQB = 1721; + public static final int SYSZ_INS_VCEQBS = 1722; + public static final int SYSZ_INS_VCEQF = 1723; + public static final int SYSZ_INS_VCEQFS = 1724; + public static final int SYSZ_INS_VCEQG = 1725; + public static final int SYSZ_INS_VCEQGS = 1726; + public static final int SYSZ_INS_VCEQH = 1727; + public static final int SYSZ_INS_VCEQHS = 1728; + public static final int SYSZ_INS_VCGD = 1729; + public static final int SYSZ_INS_VCGDB = 1730; + public static final int SYSZ_INS_VCH = 1731; + public static final int SYSZ_INS_VCHB = 1732; + public static final int SYSZ_INS_VCHBS = 1733; + public static final int SYSZ_INS_VCHF = 1734; + public static final int SYSZ_INS_VCHFS = 1735; + public static final int SYSZ_INS_VCHG = 1736; + public static final int SYSZ_INS_VCHGS = 1737; + public static final int SYSZ_INS_VCHH = 1738; + public static final int SYSZ_INS_VCHHS = 1739; + public static final int SYSZ_INS_VCHL = 1740; + public static final int SYSZ_INS_VCHLB = 1741; + public static final int SYSZ_INS_VCHLBS = 1742; + public static final int SYSZ_INS_VCHLF = 1743; + public static final int SYSZ_INS_VCHLFS = 1744; + public static final int SYSZ_INS_VCHLG = 1745; + public static final int SYSZ_INS_VCHLGS = 1746; + public static final int SYSZ_INS_VCHLH = 1747; + public static final int SYSZ_INS_VCHLHS = 1748; + public static final int SYSZ_INS_VCKSM = 1749; + public static final int SYSZ_INS_VCLGD = 1750; + public static final int SYSZ_INS_VCLGDB = 1751; + public static final int SYSZ_INS_VCLZ = 1752; + public static final int SYSZ_INS_VCLZB = 1753; + public static final int SYSZ_INS_VCLZF = 1754; + public static final int SYSZ_INS_VCLZG = 1755; + public static final int SYSZ_INS_VCLZH = 1756; + public static final int SYSZ_INS_VCP = 1757; + public static final int SYSZ_INS_VCTZ = 1758; + public static final int SYSZ_INS_VCTZB = 1759; + public static final int SYSZ_INS_VCTZF = 1760; + public static final int SYSZ_INS_VCTZG = 1761; + public static final int SYSZ_INS_VCTZH = 1762; + public static final int SYSZ_INS_VCVB = 1763; + public static final int SYSZ_INS_VCVBG = 1764; + public static final int SYSZ_INS_VCVD = 1765; + public static final int SYSZ_INS_VCVDG = 1766; + public static final int SYSZ_INS_VDP = 1767; + public static final int SYSZ_INS_VEC = 1768; + public static final int SYSZ_INS_VECB = 1769; + public static final int SYSZ_INS_VECF = 1770; + public static final int SYSZ_INS_VECG = 1771; + public static final int SYSZ_INS_VECH = 1772; + public static final int SYSZ_INS_VECL = 1773; + public static final int SYSZ_INS_VECLB = 1774; + public static final int SYSZ_INS_VECLF = 1775; + public static final int SYSZ_INS_VECLG = 1776; + public static final int SYSZ_INS_VECLH = 1777; + public static final int SYSZ_INS_VERIM = 1778; + public static final int SYSZ_INS_VERIMB = 1779; + public static final int SYSZ_INS_VERIMF = 1780; + public static final int SYSZ_INS_VERIMG = 1781; + public static final int SYSZ_INS_VERIMH = 1782; + public static final int SYSZ_INS_VERLL = 1783; + public static final int SYSZ_INS_VERLLB = 1784; + public static final int SYSZ_INS_VERLLF = 1785; + public static final int SYSZ_INS_VERLLG = 1786; + public static final int SYSZ_INS_VERLLH = 1787; + public static final int SYSZ_INS_VERLLV = 1788; + public static final int SYSZ_INS_VERLLVB = 1789; + public static final int SYSZ_INS_VERLLVF = 1790; + public static final int SYSZ_INS_VERLLVG = 1791; + public static final int SYSZ_INS_VERLLVH = 1792; + public static final int SYSZ_INS_VESL = 1793; + public static final int SYSZ_INS_VESLB = 1794; + public static final int SYSZ_INS_VESLF = 1795; + public static final int SYSZ_INS_VESLG = 1796; + public static final int SYSZ_INS_VESLH = 1797; + public static final int SYSZ_INS_VESLV = 1798; + public static final int SYSZ_INS_VESLVB = 1799; + public static final int SYSZ_INS_VESLVF = 1800; + public static final int SYSZ_INS_VESLVG = 1801; + public static final int SYSZ_INS_VESLVH = 1802; + public static final int SYSZ_INS_VESRA = 1803; + public static final int SYSZ_INS_VESRAB = 1804; + public static final int SYSZ_INS_VESRAF = 1805; + public static final int SYSZ_INS_VESRAG = 1806; + public static final int SYSZ_INS_VESRAH = 1807; + public static final int SYSZ_INS_VESRAV = 1808; + public static final int SYSZ_INS_VESRAVB = 1809; + public static final int SYSZ_INS_VESRAVF = 1810; + public static final int SYSZ_INS_VESRAVG = 1811; + public static final int SYSZ_INS_VESRAVH = 1812; + public static final int SYSZ_INS_VESRL = 1813; + public static final int SYSZ_INS_VESRLB = 1814; + public static final int SYSZ_INS_VESRLF = 1815; + public static final int SYSZ_INS_VESRLG = 1816; + public static final int SYSZ_INS_VESRLH = 1817; + public static final int SYSZ_INS_VESRLV = 1818; + public static final int SYSZ_INS_VESRLVB = 1819; + public static final int SYSZ_INS_VESRLVF = 1820; + public static final int SYSZ_INS_VESRLVG = 1821; + public static final int SYSZ_INS_VESRLVH = 1822; + public static final int SYSZ_INS_VFA = 1823; + public static final int SYSZ_INS_VFADB = 1824; + public static final int SYSZ_INS_VFAE = 1825; + public static final int SYSZ_INS_VFAEB = 1826; + public static final int SYSZ_INS_VFAEBS = 1827; + public static final int SYSZ_INS_VFAEF = 1828; + public static final int SYSZ_INS_VFAEFS = 1829; + public static final int SYSZ_INS_VFAEH = 1830; + public static final int SYSZ_INS_VFAEHS = 1831; + public static final int SYSZ_INS_VFAEZB = 1832; + public static final int SYSZ_INS_VFAEZBS = 1833; + public static final int SYSZ_INS_VFAEZF = 1834; + public static final int SYSZ_INS_VFAEZFS = 1835; + public static final int SYSZ_INS_VFAEZH = 1836; + public static final int SYSZ_INS_VFAEZHS = 1837; + public static final int SYSZ_INS_VFASB = 1838; + public static final int SYSZ_INS_VFCE = 1839; + public static final int SYSZ_INS_VFCEDB = 1840; + public static final int SYSZ_INS_VFCEDBS = 1841; + public static final int SYSZ_INS_VFCESB = 1842; + public static final int SYSZ_INS_VFCESBS = 1843; + public static final int SYSZ_INS_VFCH = 1844; + public static final int SYSZ_INS_VFCHDB = 1845; + public static final int SYSZ_INS_VFCHDBS = 1846; + public static final int SYSZ_INS_VFCHE = 1847; + public static final int SYSZ_INS_VFCHEDB = 1848; + public static final int SYSZ_INS_VFCHEDBS = 1849; + public static final int SYSZ_INS_VFCHESB = 1850; + public static final int SYSZ_INS_VFCHESBS = 1851; + public static final int SYSZ_INS_VFCHSB = 1852; + public static final int SYSZ_INS_VFCHSBS = 1853; + public static final int SYSZ_INS_VFD = 1854; + public static final int SYSZ_INS_VFDDB = 1855; + public static final int SYSZ_INS_VFDSB = 1856; + public static final int SYSZ_INS_VFEE = 1857; + public static final int SYSZ_INS_VFEEB = 1858; + public static final int SYSZ_INS_VFEEBS = 1859; + public static final int SYSZ_INS_VFEEF = 1860; + public static final int SYSZ_INS_VFEEFS = 1861; + public static final int SYSZ_INS_VFEEH = 1862; + public static final int SYSZ_INS_VFEEHS = 1863; + public static final int SYSZ_INS_VFEEZB = 1864; + public static final int SYSZ_INS_VFEEZBS = 1865; + public static final int SYSZ_INS_VFEEZF = 1866; + public static final int SYSZ_INS_VFEEZFS = 1867; + public static final int SYSZ_INS_VFEEZH = 1868; + public static final int SYSZ_INS_VFEEZHS = 1869; + public static final int SYSZ_INS_VFENE = 1870; + public static final int SYSZ_INS_VFENEB = 1871; + public static final int SYSZ_INS_VFENEBS = 1872; + public static final int SYSZ_INS_VFENEF = 1873; + public static final int SYSZ_INS_VFENEFS = 1874; + public static final int SYSZ_INS_VFENEH = 1875; + public static final int SYSZ_INS_VFENEHS = 1876; + public static final int SYSZ_INS_VFENEZB = 1877; + public static final int SYSZ_INS_VFENEZBS = 1878; + public static final int SYSZ_INS_VFENEZF = 1879; + public static final int SYSZ_INS_VFENEZFS = 1880; + public static final int SYSZ_INS_VFENEZH = 1881; + public static final int SYSZ_INS_VFENEZHS = 1882; + public static final int SYSZ_INS_VFI = 1883; + public static final int SYSZ_INS_VFIDB = 1884; + public static final int SYSZ_INS_VFISB = 1885; + public static final int SYSZ_INS_VFKEDB = 1886; + public static final int SYSZ_INS_VFKEDBS = 1887; + public static final int SYSZ_INS_VFKESB = 1888; + public static final int SYSZ_INS_VFKESBS = 1889; + public static final int SYSZ_INS_VFKHDB = 1890; + public static final int SYSZ_INS_VFKHDBS = 1891; + public static final int SYSZ_INS_VFKHEDB = 1892; + public static final int SYSZ_INS_VFKHEDBS = 1893; + public static final int SYSZ_INS_VFKHESB = 1894; + public static final int SYSZ_INS_VFKHESBS = 1895; + public static final int SYSZ_INS_VFKHSB = 1896; + public static final int SYSZ_INS_VFKHSBS = 1897; + public static final int SYSZ_INS_VFLCDB = 1898; + public static final int SYSZ_INS_VFLCSB = 1899; + public static final int SYSZ_INS_VFLL = 1900; + public static final int SYSZ_INS_VFLLS = 1901; + public static final int SYSZ_INS_VFLNDB = 1902; + public static final int SYSZ_INS_VFLNSB = 1903; + public static final int SYSZ_INS_VFLPDB = 1904; + public static final int SYSZ_INS_VFLPSB = 1905; + public static final int SYSZ_INS_VFLR = 1906; + public static final int SYSZ_INS_VFLRD = 1907; + public static final int SYSZ_INS_VFM = 1908; + public static final int SYSZ_INS_VFMA = 1909; + public static final int SYSZ_INS_VFMADB = 1910; + public static final int SYSZ_INS_VFMASB = 1911; + public static final int SYSZ_INS_VFMAX = 1912; + public static final int SYSZ_INS_VFMAXDB = 1913; + public static final int SYSZ_INS_VFMAXSB = 1914; + public static final int SYSZ_INS_VFMDB = 1915; + public static final int SYSZ_INS_VFMIN = 1916; + public static final int SYSZ_INS_VFMINDB = 1917; + public static final int SYSZ_INS_VFMINSB = 1918; + public static final int SYSZ_INS_VFMS = 1919; + public static final int SYSZ_INS_VFMSB = 1920; + public static final int SYSZ_INS_VFMSDB = 1921; + public static final int SYSZ_INS_VFMSSB = 1922; + public static final int SYSZ_INS_VFNMA = 1923; + public static final int SYSZ_INS_VFNMADB = 1924; + public static final int SYSZ_INS_VFNMASB = 1925; + public static final int SYSZ_INS_VFNMS = 1926; + public static final int SYSZ_INS_VFNMSDB = 1927; + public static final int SYSZ_INS_VFNMSSB = 1928; + public static final int SYSZ_INS_VFPSO = 1929; + public static final int SYSZ_INS_VFPSODB = 1930; + public static final int SYSZ_INS_VFPSOSB = 1931; + public static final int SYSZ_INS_VFS = 1932; + public static final int SYSZ_INS_VFSDB = 1933; + public static final int SYSZ_INS_VFSQ = 1934; + public static final int SYSZ_INS_VFSQDB = 1935; + public static final int SYSZ_INS_VFSQSB = 1936; + public static final int SYSZ_INS_VFSSB = 1937; + public static final int SYSZ_INS_VFTCI = 1938; + public static final int SYSZ_INS_VFTCIDB = 1939; + public static final int SYSZ_INS_VFTCISB = 1940; + public static final int SYSZ_INS_VGBM = 1941; + public static final int SYSZ_INS_VGEF = 1942; + public static final int SYSZ_INS_VGEG = 1943; + public static final int SYSZ_INS_VGFM = 1944; + public static final int SYSZ_INS_VGFMA = 1945; + public static final int SYSZ_INS_VGFMAB = 1946; + public static final int SYSZ_INS_VGFMAF = 1947; + public static final int SYSZ_INS_VGFMAG = 1948; + public static final int SYSZ_INS_VGFMAH = 1949; + public static final int SYSZ_INS_VGFMB = 1950; + public static final int SYSZ_INS_VGFMF = 1951; + public static final int SYSZ_INS_VGFMG = 1952; + public static final int SYSZ_INS_VGFMH = 1953; + public static final int SYSZ_INS_VGM = 1954; + public static final int SYSZ_INS_VGMB = 1955; + public static final int SYSZ_INS_VGMF = 1956; + public static final int SYSZ_INS_VGMG = 1957; + public static final int SYSZ_INS_VGMH = 1958; + public static final int SYSZ_INS_VISTR = 1959; + public static final int SYSZ_INS_VISTRB = 1960; + public static final int SYSZ_INS_VISTRBS = 1961; + public static final int SYSZ_INS_VISTRF = 1962; + public static final int SYSZ_INS_VISTRFS = 1963; + public static final int SYSZ_INS_VISTRH = 1964; + public static final int SYSZ_INS_VISTRHS = 1965; + public static final int SYSZ_INS_VL = 1966; + public static final int SYSZ_INS_VLBB = 1967; + public static final int SYSZ_INS_VLC = 1968; + public static final int SYSZ_INS_VLCB = 1969; + public static final int SYSZ_INS_VLCF = 1970; + public static final int SYSZ_INS_VLCG = 1971; + public static final int SYSZ_INS_VLCH = 1972; + public static final int SYSZ_INS_VLDE = 1973; + public static final int SYSZ_INS_VLDEB = 1974; + public static final int SYSZ_INS_VLEB = 1975; + public static final int SYSZ_INS_VLED = 1976; + public static final int SYSZ_INS_VLEDB = 1977; + public static final int SYSZ_INS_VLEF = 1978; + public static final int SYSZ_INS_VLEG = 1979; + public static final int SYSZ_INS_VLEH = 1980; + public static final int SYSZ_INS_VLEIB = 1981; + public static final int SYSZ_INS_VLEIF = 1982; + public static final int SYSZ_INS_VLEIG = 1983; + public static final int SYSZ_INS_VLEIH = 1984; + public static final int SYSZ_INS_VLGV = 1985; + public static final int SYSZ_INS_VLGVB = 1986; + public static final int SYSZ_INS_VLGVF = 1987; + public static final int SYSZ_INS_VLGVG = 1988; + public static final int SYSZ_INS_VLGVH = 1989; + public static final int SYSZ_INS_VLIP = 1990; + public static final int SYSZ_INS_VLL = 1991; + public static final int SYSZ_INS_VLLEZ = 1992; + public static final int SYSZ_INS_VLLEZB = 1993; + public static final int SYSZ_INS_VLLEZF = 1994; + public static final int SYSZ_INS_VLLEZG = 1995; + public static final int SYSZ_INS_VLLEZH = 1996; + public static final int SYSZ_INS_VLLEZLF = 1997; + public static final int SYSZ_INS_VLM = 1998; + public static final int SYSZ_INS_VLP = 1999; + public static final int SYSZ_INS_VLPB = 2000; + public static final int SYSZ_INS_VLPF = 2001; + public static final int SYSZ_INS_VLPG = 2002; + public static final int SYSZ_INS_VLPH = 2003; + public static final int SYSZ_INS_VLR = 2004; + public static final int SYSZ_INS_VLREP = 2005; + public static final int SYSZ_INS_VLREPB = 2006; + public static final int SYSZ_INS_VLREPF = 2007; + public static final int SYSZ_INS_VLREPG = 2008; + public static final int SYSZ_INS_VLREPH = 2009; + public static final int SYSZ_INS_VLRL = 2010; + public static final int SYSZ_INS_VLRLR = 2011; + public static final int SYSZ_INS_VLVG = 2012; + public static final int SYSZ_INS_VLVGB = 2013; + public static final int SYSZ_INS_VLVGF = 2014; + public static final int SYSZ_INS_VLVGG = 2015; + public static final int SYSZ_INS_VLVGH = 2016; + public static final int SYSZ_INS_VLVGP = 2017; + public static final int SYSZ_INS_VMAE = 2018; + public static final int SYSZ_INS_VMAEB = 2019; + public static final int SYSZ_INS_VMAEF = 2020; + public static final int SYSZ_INS_VMAEH = 2021; + public static final int SYSZ_INS_VMAH = 2022; + public static final int SYSZ_INS_VMAHB = 2023; + public static final int SYSZ_INS_VMAHF = 2024; + public static final int SYSZ_INS_VMAHH = 2025; + public static final int SYSZ_INS_VMAL = 2026; + public static final int SYSZ_INS_VMALB = 2027; + public static final int SYSZ_INS_VMALE = 2028; + public static final int SYSZ_INS_VMALEB = 2029; + public static final int SYSZ_INS_VMALEF = 2030; + public static final int SYSZ_INS_VMALEH = 2031; + public static final int SYSZ_INS_VMALF = 2032; + public static final int SYSZ_INS_VMALH = 2033; + public static final int SYSZ_INS_VMALHB = 2034; + public static final int SYSZ_INS_VMALHF = 2035; + public static final int SYSZ_INS_VMALHH = 2036; + public static final int SYSZ_INS_VMALHW = 2037; + public static final int SYSZ_INS_VMALO = 2038; + public static final int SYSZ_INS_VMALOB = 2039; + public static final int SYSZ_INS_VMALOF = 2040; + public static final int SYSZ_INS_VMALOH = 2041; + public static final int SYSZ_INS_VMAO = 2042; + public static final int SYSZ_INS_VMAOB = 2043; + public static final int SYSZ_INS_VMAOF = 2044; + public static final int SYSZ_INS_VMAOH = 2045; + public static final int SYSZ_INS_VME = 2046; + public static final int SYSZ_INS_VMEB = 2047; + public static final int SYSZ_INS_VMEF = 2048; + public static final int SYSZ_INS_VMEH = 2049; + public static final int SYSZ_INS_VMH = 2050; + public static final int SYSZ_INS_VMHB = 2051; + public static final int SYSZ_INS_VMHF = 2052; + public static final int SYSZ_INS_VMHH = 2053; + public static final int SYSZ_INS_VML = 2054; + public static final int SYSZ_INS_VMLB = 2055; + public static final int SYSZ_INS_VMLE = 2056; + public static final int SYSZ_INS_VMLEB = 2057; + public static final int SYSZ_INS_VMLEF = 2058; + public static final int SYSZ_INS_VMLEH = 2059; + public static final int SYSZ_INS_VMLF = 2060; + public static final int SYSZ_INS_VMLH = 2061; + public static final int SYSZ_INS_VMLHB = 2062; + public static final int SYSZ_INS_VMLHF = 2063; + public static final int SYSZ_INS_VMLHH = 2064; + public static final int SYSZ_INS_VMLHW = 2065; + public static final int SYSZ_INS_VMLO = 2066; + public static final int SYSZ_INS_VMLOB = 2067; + public static final int SYSZ_INS_VMLOF = 2068; + public static final int SYSZ_INS_VMLOH = 2069; + public static final int SYSZ_INS_VMN = 2070; + public static final int SYSZ_INS_VMNB = 2071; + public static final int SYSZ_INS_VMNF = 2072; + public static final int SYSZ_INS_VMNG = 2073; + public static final int SYSZ_INS_VMNH = 2074; + public static final int SYSZ_INS_VMNL = 2075; + public static final int SYSZ_INS_VMNLB = 2076; + public static final int SYSZ_INS_VMNLF = 2077; + public static final int SYSZ_INS_VMNLG = 2078; + public static final int SYSZ_INS_VMNLH = 2079; + public static final int SYSZ_INS_VMO = 2080; + public static final int SYSZ_INS_VMOB = 2081; + public static final int SYSZ_INS_VMOF = 2082; + public static final int SYSZ_INS_VMOH = 2083; + public static final int SYSZ_INS_VMP = 2084; + public static final int SYSZ_INS_VMRH = 2085; + public static final int SYSZ_INS_VMRHB = 2086; + public static final int SYSZ_INS_VMRHF = 2087; + public static final int SYSZ_INS_VMRHG = 2088; + public static final int SYSZ_INS_VMRHH = 2089; + public static final int SYSZ_INS_VMRL = 2090; + public static final int SYSZ_INS_VMRLB = 2091; + public static final int SYSZ_INS_VMRLF = 2092; + public static final int SYSZ_INS_VMRLG = 2093; + public static final int SYSZ_INS_VMRLH = 2094; + public static final int SYSZ_INS_VMSL = 2095; + public static final int SYSZ_INS_VMSLG = 2096; + public static final int SYSZ_INS_VMSP = 2097; + public static final int SYSZ_INS_VMX = 2098; + public static final int SYSZ_INS_VMXB = 2099; + public static final int SYSZ_INS_VMXF = 2100; + public static final int SYSZ_INS_VMXG = 2101; + public static final int SYSZ_INS_VMXH = 2102; + public static final int SYSZ_INS_VMXL = 2103; + public static final int SYSZ_INS_VMXLB = 2104; + public static final int SYSZ_INS_VMXLF = 2105; + public static final int SYSZ_INS_VMXLG = 2106; + public static final int SYSZ_INS_VMXLH = 2107; + public static final int SYSZ_INS_VN = 2108; + public static final int SYSZ_INS_VNC = 2109; + public static final int SYSZ_INS_VNN = 2110; + public static final int SYSZ_INS_VNO = 2111; + public static final int SYSZ_INS_VNX = 2112; + public static final int SYSZ_INS_VO = 2113; + public static final int SYSZ_INS_VOC = 2114; + public static final int SYSZ_INS_VONE = 2115; + public static final int SYSZ_INS_VPDI = 2116; + public static final int SYSZ_INS_VPERM = 2117; + public static final int SYSZ_INS_VPK = 2118; + public static final int SYSZ_INS_VPKF = 2119; + public static final int SYSZ_INS_VPKG = 2120; + public static final int SYSZ_INS_VPKH = 2121; + public static final int SYSZ_INS_VPKLS = 2122; + public static final int SYSZ_INS_VPKLSF = 2123; + public static final int SYSZ_INS_VPKLSFS = 2124; + public static final int SYSZ_INS_VPKLSG = 2125; + public static final int SYSZ_INS_VPKLSGS = 2126; + public static final int SYSZ_INS_VPKLSH = 2127; + public static final int SYSZ_INS_VPKLSHS = 2128; + public static final int SYSZ_INS_VPKS = 2129; + public static final int SYSZ_INS_VPKSF = 2130; + public static final int SYSZ_INS_VPKSFS = 2131; + public static final int SYSZ_INS_VPKSG = 2132; + public static final int SYSZ_INS_VPKSGS = 2133; + public static final int SYSZ_INS_VPKSH = 2134; + public static final int SYSZ_INS_VPKSHS = 2135; + public static final int SYSZ_INS_VPKZ = 2136; + public static final int SYSZ_INS_VPOPCT = 2137; + public static final int SYSZ_INS_VPOPCTB = 2138; + public static final int SYSZ_INS_VPOPCTF = 2139; + public static final int SYSZ_INS_VPOPCTG = 2140; + public static final int SYSZ_INS_VPOPCTH = 2141; + public static final int SYSZ_INS_VPSOP = 2142; + public static final int SYSZ_INS_VREP = 2143; + public static final int SYSZ_INS_VREPB = 2144; + public static final int SYSZ_INS_VREPF = 2145; + public static final int SYSZ_INS_VREPG = 2146; + public static final int SYSZ_INS_VREPH = 2147; + public static final int SYSZ_INS_VREPI = 2148; + public static final int SYSZ_INS_VREPIB = 2149; + public static final int SYSZ_INS_VREPIF = 2150; + public static final int SYSZ_INS_VREPIG = 2151; + public static final int SYSZ_INS_VREPIH = 2152; + public static final int SYSZ_INS_VRP = 2153; + public static final int SYSZ_INS_VS = 2154; + public static final int SYSZ_INS_VSB = 2155; + public static final int SYSZ_INS_VSBCBI = 2156; + public static final int SYSZ_INS_VSBCBIQ = 2157; + public static final int SYSZ_INS_VSBI = 2158; + public static final int SYSZ_INS_VSBIQ = 2159; + public static final int SYSZ_INS_VSCBI = 2160; + public static final int SYSZ_INS_VSCBIB = 2161; + public static final int SYSZ_INS_VSCBIF = 2162; + public static final int SYSZ_INS_VSCBIG = 2163; + public static final int SYSZ_INS_VSCBIH = 2164; + public static final int SYSZ_INS_VSCBIQ = 2165; + public static final int SYSZ_INS_VSCEF = 2166; + public static final int SYSZ_INS_VSCEG = 2167; + public static final int SYSZ_INS_VSDP = 2168; + public static final int SYSZ_INS_VSEG = 2169; + public static final int SYSZ_INS_VSEGB = 2170; + public static final int SYSZ_INS_VSEGF = 2171; + public static final int SYSZ_INS_VSEGH = 2172; + public static final int SYSZ_INS_VSEL = 2173; + public static final int SYSZ_INS_VSF = 2174; + public static final int SYSZ_INS_VSG = 2175; + public static final int SYSZ_INS_VSH = 2176; + public static final int SYSZ_INS_VSL = 2177; + public static final int SYSZ_INS_VSLB = 2178; + public static final int SYSZ_INS_VSLDB = 2179; + public static final int SYSZ_INS_VSP = 2180; + public static final int SYSZ_INS_VSQ = 2181; + public static final int SYSZ_INS_VSRA = 2182; + public static final int SYSZ_INS_VSRAB = 2183; + public static final int SYSZ_INS_VSRL = 2184; + public static final int SYSZ_INS_VSRLB = 2185; + public static final int SYSZ_INS_VSRP = 2186; + public static final int SYSZ_INS_VST = 2187; + public static final int SYSZ_INS_VSTEB = 2188; + public static final int SYSZ_INS_VSTEF = 2189; + public static final int SYSZ_INS_VSTEG = 2190; + public static final int SYSZ_INS_VSTEH = 2191; + public static final int SYSZ_INS_VSTL = 2192; + public static final int SYSZ_INS_VSTM = 2193; + public static final int SYSZ_INS_VSTRC = 2194; + public static final int SYSZ_INS_VSTRCB = 2195; + public static final int SYSZ_INS_VSTRCBS = 2196; + public static final int SYSZ_INS_VSTRCF = 2197; + public static final int SYSZ_INS_VSTRCFS = 2198; + public static final int SYSZ_INS_VSTRCH = 2199; + public static final int SYSZ_INS_VSTRCHS = 2200; + public static final int SYSZ_INS_VSTRCZB = 2201; + public static final int SYSZ_INS_VSTRCZBS = 2202; + public static final int SYSZ_INS_VSTRCZF = 2203; + public static final int SYSZ_INS_VSTRCZFS = 2204; + public static final int SYSZ_INS_VSTRCZH = 2205; + public static final int SYSZ_INS_VSTRCZHS = 2206; + public static final int SYSZ_INS_VSTRL = 2207; + public static final int SYSZ_INS_VSTRLR = 2208; + public static final int SYSZ_INS_VSUM = 2209; + public static final int SYSZ_INS_VSUMB = 2210; + public static final int SYSZ_INS_VSUMG = 2211; + public static final int SYSZ_INS_VSUMGF = 2212; + public static final int SYSZ_INS_VSUMGH = 2213; + public static final int SYSZ_INS_VSUMH = 2214; + public static final int SYSZ_INS_VSUMQ = 2215; + public static final int SYSZ_INS_VSUMQF = 2216; + public static final int SYSZ_INS_VSUMQG = 2217; + public static final int SYSZ_INS_VTM = 2218; + public static final int SYSZ_INS_VTP = 2219; + public static final int SYSZ_INS_VUPH = 2220; + public static final int SYSZ_INS_VUPHB = 2221; + public static final int SYSZ_INS_VUPHF = 2222; + public static final int SYSZ_INS_VUPHH = 2223; + public static final int SYSZ_INS_VUPKZ = 2224; + public static final int SYSZ_INS_VUPL = 2225; + public static final int SYSZ_INS_VUPLB = 2226; + public static final int SYSZ_INS_VUPLF = 2227; + public static final int SYSZ_INS_VUPLH = 2228; + public static final int SYSZ_INS_VUPLHB = 2229; + public static final int SYSZ_INS_VUPLHF = 2230; + public static final int SYSZ_INS_VUPLHH = 2231; + public static final int SYSZ_INS_VUPLHW = 2232; + public static final int SYSZ_INS_VUPLL = 2233; + public static final int SYSZ_INS_VUPLLB = 2234; + public static final int SYSZ_INS_VUPLLF = 2235; + public static final int SYSZ_INS_VUPLLH = 2236; + public static final int SYSZ_INS_VX = 2237; + public static final int SYSZ_INS_VZERO = 2238; + public static final int SYSZ_INS_WCDGB = 2239; + public static final int SYSZ_INS_WCDLGB = 2240; + public static final int SYSZ_INS_WCGDB = 2241; + public static final int SYSZ_INS_WCLGDB = 2242; + public static final int SYSZ_INS_WFADB = 2243; + public static final int SYSZ_INS_WFASB = 2244; + public static final int SYSZ_INS_WFAXB = 2245; + public static final int SYSZ_INS_WFC = 2246; + public static final int SYSZ_INS_WFCDB = 2247; + public static final int SYSZ_INS_WFCEDB = 2248; + public static final int SYSZ_INS_WFCEDBS = 2249; + public static final int SYSZ_INS_WFCESB = 2250; + public static final int SYSZ_INS_WFCESBS = 2251; + public static final int SYSZ_INS_WFCEXB = 2252; + public static final int SYSZ_INS_WFCEXBS = 2253; + public static final int SYSZ_INS_WFCHDB = 2254; + public static final int SYSZ_INS_WFCHDBS = 2255; + public static final int SYSZ_INS_WFCHEDB = 2256; + public static final int SYSZ_INS_WFCHEDBS = 2257; + public static final int SYSZ_INS_WFCHESB = 2258; + public static final int SYSZ_INS_WFCHESBS = 2259; + public static final int SYSZ_INS_WFCHEXB = 2260; + public static final int SYSZ_INS_WFCHEXBS = 2261; + public static final int SYSZ_INS_WFCHSB = 2262; + public static final int SYSZ_INS_WFCHSBS = 2263; + public static final int SYSZ_INS_WFCHXB = 2264; + public static final int SYSZ_INS_WFCHXBS = 2265; + public static final int SYSZ_INS_WFCSB = 2266; + public static final int SYSZ_INS_WFCXB = 2267; + public static final int SYSZ_INS_WFDDB = 2268; + public static final int SYSZ_INS_WFDSB = 2269; + public static final int SYSZ_INS_WFDXB = 2270; + public static final int SYSZ_INS_WFIDB = 2271; + public static final int SYSZ_INS_WFISB = 2272; + public static final int SYSZ_INS_WFIXB = 2273; + public static final int SYSZ_INS_WFK = 2274; + public static final int SYSZ_INS_WFKDB = 2275; + public static final int SYSZ_INS_WFKEDB = 2276; + public static final int SYSZ_INS_WFKEDBS = 2277; + public static final int SYSZ_INS_WFKESB = 2278; + public static final int SYSZ_INS_WFKESBS = 2279; + public static final int SYSZ_INS_WFKEXB = 2280; + public static final int SYSZ_INS_WFKEXBS = 2281; + public static final int SYSZ_INS_WFKHDB = 2282; + public static final int SYSZ_INS_WFKHDBS = 2283; + public static final int SYSZ_INS_WFKHEDB = 2284; + public static final int SYSZ_INS_WFKHEDBS = 2285; + public static final int SYSZ_INS_WFKHESB = 2286; + public static final int SYSZ_INS_WFKHESBS = 2287; + public static final int SYSZ_INS_WFKHEXB = 2288; + public static final int SYSZ_INS_WFKHEXBS = 2289; + public static final int SYSZ_INS_WFKHSB = 2290; + public static final int SYSZ_INS_WFKHSBS = 2291; + public static final int SYSZ_INS_WFKHXB = 2292; + public static final int SYSZ_INS_WFKHXBS = 2293; + public static final int SYSZ_INS_WFKSB = 2294; + public static final int SYSZ_INS_WFKXB = 2295; + public static final int SYSZ_INS_WFLCDB = 2296; + public static final int SYSZ_INS_WFLCSB = 2297; + public static final int SYSZ_INS_WFLCXB = 2298; + public static final int SYSZ_INS_WFLLD = 2299; + public static final int SYSZ_INS_WFLLS = 2300; + public static final int SYSZ_INS_WFLNDB = 2301; + public static final int SYSZ_INS_WFLNSB = 2302; + public static final int SYSZ_INS_WFLNXB = 2303; + public static final int SYSZ_INS_WFLPDB = 2304; + public static final int SYSZ_INS_WFLPSB = 2305; + public static final int SYSZ_INS_WFLPXB = 2306; + public static final int SYSZ_INS_WFLRD = 2307; + public static final int SYSZ_INS_WFLRX = 2308; + public static final int SYSZ_INS_WFMADB = 2309; + public static final int SYSZ_INS_WFMASB = 2310; + public static final int SYSZ_INS_WFMAXB = 2311; + public static final int SYSZ_INS_WFMAXDB = 2312; + public static final int SYSZ_INS_WFMAXSB = 2313; + public static final int SYSZ_INS_WFMAXXB = 2314; + public static final int SYSZ_INS_WFMDB = 2315; + public static final int SYSZ_INS_WFMINDB = 2316; + public static final int SYSZ_INS_WFMINSB = 2317; + public static final int SYSZ_INS_WFMINXB = 2318; + public static final int SYSZ_INS_WFMSB = 2319; + public static final int SYSZ_INS_WFMSDB = 2320; + public static final int SYSZ_INS_WFMSSB = 2321; + public static final int SYSZ_INS_WFMSXB = 2322; + public static final int SYSZ_INS_WFMXB = 2323; + public static final int SYSZ_INS_WFNMADB = 2324; + public static final int SYSZ_INS_WFNMASB = 2325; + public static final int SYSZ_INS_WFNMAXB = 2326; + public static final int SYSZ_INS_WFNMSDB = 2327; + public static final int SYSZ_INS_WFNMSSB = 2328; + public static final int SYSZ_INS_WFNMSXB = 2329; + public static final int SYSZ_INS_WFPSODB = 2330; + public static final int SYSZ_INS_WFPSOSB = 2331; + public static final int SYSZ_INS_WFPSOXB = 2332; + public static final int SYSZ_INS_WFSDB = 2333; + public static final int SYSZ_INS_WFSQDB = 2334; + public static final int SYSZ_INS_WFSQSB = 2335; + public static final int SYSZ_INS_WFSQXB = 2336; + public static final int SYSZ_INS_WFSSB = 2337; + public static final int SYSZ_INS_WFSXB = 2338; + public static final int SYSZ_INS_WFTCIDB = 2339; + public static final int SYSZ_INS_WFTCISB = 2340; + public static final int SYSZ_INS_WFTCIXB = 2341; + public static final int SYSZ_INS_WLDEB = 2342; + public static final int SYSZ_INS_WLEDB = 2343; + public static final int SYSZ_INS_XSCH = 2344; + public static final int SYSZ_INS_ZAP = 2345; + public static final int SYSZ_INS_ENDING = 2346; + + public static final int SYSZ_GRP_INVALID = 0; + public static final int SYSZ_GRP_JUMP = 1; + public static final int SYSZ_GRP_DISTINCTOPS = 128; + public static final int SYSZ_GRP_FPEXTENSION = 129; + public static final int SYSZ_GRP_HIGHWORD = 130; + public static final int SYSZ_GRP_INTERLOCKEDACCESS1 = 131; + public static final int SYSZ_GRP_LOADSTOREONCOND = 132; + public static final int SYSZ_GRP_DFPPACKEDCONVERSION = 133; + public static final int SYSZ_GRP_DFPZONEDCONVERSION = 134; + public static final int SYSZ_GRP_ENHANCEDDAT2 = 135; + public static final int SYSZ_GRP_EXECUTIONHINT = 136; + public static final int SYSZ_GRP_GUARDEDSTORAGE = 137; + public static final int SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138; + public static final int SYSZ_GRP_LOADANDTRAP = 139; + public static final int SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140; + public static final int SYSZ_GRP_LOADSTOREONCOND2 = 141; + public static final int SYSZ_GRP_MESSAGESECURITYASSIST3 = 142; + public static final int SYSZ_GRP_MESSAGESECURITYASSIST4 = 143; + public static final int SYSZ_GRP_MESSAGESECURITYASSIST5 = 144; + public static final int SYSZ_GRP_MESSAGESECURITYASSIST7 = 145; + public static final int SYSZ_GRP_MESSAGESECURITYASSIST8 = 146; + public static final int SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147; + public static final int SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148; + public static final int SYSZ_GRP_NOVECTOR = 149; + public static final int SYSZ_GRP_POPULATIONCOUNT = 150; + public static final int SYSZ_GRP_PROCESSORASSIST = 151; + public static final int SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152; + public static final int SYSZ_GRP_TRANSACTIONALEXECUTION = 153; + public static final int SYSZ_GRP_VECTOR = 154; + public static final int SYSZ_GRP_VECTORENHANCEMENTS1 = 155; + public static final int SYSZ_GRP_VECTORPACKEDDECIMAL = 156; + public static final int SYSZ_GRP_ENDING = 157; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/TMS320C64x_const.java b/white_patch_detect/capstone-master/bindings/java/capstone/TMS320C64x_const.java new file mode 100644 index 0000000..6e48b41 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/TMS320C64x_const.java @@ -0,0 +1,281 @@ +// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT +package capstone; + +public class TMS320C64x_const { + + public static final int TMS320C64X_OP_INVALID = 0; + public static final int TMS320C64X_OP_REG = 1; + public static final int TMS320C64X_OP_IMM = 2; + public static final int TMS320C64X_OP_MEM = 3; + public static final int TMS320C64X_OP_REGPAIR = 64; + + public static final int TMS320C64X_MEM_DISP_INVALID = 0; + public static final int TMS320C64X_MEM_DISP_CONSTANT = 1; + public static final int TMS320C64X_MEM_DISP_REGISTER = 2; + + public static final int TMS320C64X_MEM_DIR_INVALID = 0; + public static final int TMS320C64X_MEM_DIR_FW = 1; + public static final int TMS320C64X_MEM_DIR_BW = 2; + + public static final int TMS320C64X_MEM_MOD_INVALID = 0; + public static final int TMS320C64X_MEM_MOD_NO = 1; + public static final int TMS320C64X_MEM_MOD_PRE = 2; + public static final int TMS320C64X_MEM_MOD_POST = 3; + + public static final int TMS320C64X_REG_INVALID = 0; + public static final int TMS320C64X_REG_AMR = 1; + public static final int TMS320C64X_REG_CSR = 2; + public static final int TMS320C64X_REG_DIER = 3; + public static final int TMS320C64X_REG_DNUM = 4; + public static final int TMS320C64X_REG_ECR = 5; + public static final int TMS320C64X_REG_GFPGFR = 6; + public static final int TMS320C64X_REG_GPLYA = 7; + public static final int TMS320C64X_REG_GPLYB = 8; + public static final int TMS320C64X_REG_ICR = 9; + public static final int TMS320C64X_REG_IER = 10; + public static final int TMS320C64X_REG_IERR = 11; + public static final int TMS320C64X_REG_ILC = 12; + public static final int TMS320C64X_REG_IRP = 13; + public static final int TMS320C64X_REG_ISR = 14; + public static final int TMS320C64X_REG_ISTP = 15; + public static final int TMS320C64X_REG_ITSR = 16; + public static final int TMS320C64X_REG_NRP = 17; + public static final int TMS320C64X_REG_NTSR = 18; + public static final int TMS320C64X_REG_REP = 19; + public static final int TMS320C64X_REG_RILC = 20; + public static final int TMS320C64X_REG_SSR = 21; + public static final int TMS320C64X_REG_TSCH = 22; + public static final int TMS320C64X_REG_TSCL = 23; + public static final int TMS320C64X_REG_TSR = 24; + public static final int TMS320C64X_REG_A0 = 25; + public static final int TMS320C64X_REG_A1 = 26; + public static final int TMS320C64X_REG_A2 = 27; + public static final int TMS320C64X_REG_A3 = 28; + public static final int TMS320C64X_REG_A4 = 29; + public static final int TMS320C64X_REG_A5 = 30; + public static final int TMS320C64X_REG_A6 = 31; + public static final int TMS320C64X_REG_A7 = 32; + public static final int TMS320C64X_REG_A8 = 33; + public static final int TMS320C64X_REG_A9 = 34; + public static final int TMS320C64X_REG_A10 = 35; + public static final int TMS320C64X_REG_A11 = 36; + public static final int TMS320C64X_REG_A12 = 37; + public static final int TMS320C64X_REG_A13 = 38; + public static final int TMS320C64X_REG_A14 = 39; + public static final int TMS320C64X_REG_A15 = 40; + public static final int TMS320C64X_REG_A16 = 41; + public static final int TMS320C64X_REG_A17 = 42; + public static final int TMS320C64X_REG_A18 = 43; + public static final int TMS320C64X_REG_A19 = 44; + public static final int TMS320C64X_REG_A20 = 45; + public static final int TMS320C64X_REG_A21 = 46; + public static final int TMS320C64X_REG_A22 = 47; + public static final int TMS320C64X_REG_A23 = 48; + public static final int TMS320C64X_REG_A24 = 49; + public static final int TMS320C64X_REG_A25 = 50; + public static final int TMS320C64X_REG_A26 = 51; + public static final int TMS320C64X_REG_A27 = 52; + public static final int TMS320C64X_REG_A28 = 53; + public static final int TMS320C64X_REG_A29 = 54; + public static final int TMS320C64X_REG_A30 = 55; + public static final int TMS320C64X_REG_A31 = 56; + public static final int TMS320C64X_REG_B0 = 57; + public static final int TMS320C64X_REG_B1 = 58; + public static final int TMS320C64X_REG_B2 = 59; + public static final int TMS320C64X_REG_B3 = 60; + public static final int TMS320C64X_REG_B4 = 61; + public static final int TMS320C64X_REG_B5 = 62; + public static final int TMS320C64X_REG_B6 = 63; + public static final int TMS320C64X_REG_B7 = 64; + public static final int TMS320C64X_REG_B8 = 65; + public static final int TMS320C64X_REG_B9 = 66; + public static final int TMS320C64X_REG_B10 = 67; + public static final int TMS320C64X_REG_B11 = 68; + public static final int TMS320C64X_REG_B12 = 69; + public static final int TMS320C64X_REG_B13 = 70; + public static final int TMS320C64X_REG_B14 = 71; + public static final int TMS320C64X_REG_B15 = 72; + public static final int TMS320C64X_REG_B16 = 73; + public static final int TMS320C64X_REG_B17 = 74; + public static final int TMS320C64X_REG_B18 = 75; + public static final int TMS320C64X_REG_B19 = 76; + public static final int TMS320C64X_REG_B20 = 77; + public static final int TMS320C64X_REG_B21 = 78; + public static final int TMS320C64X_REG_B22 = 79; + public static final int TMS320C64X_REG_B23 = 80; + public static final int TMS320C64X_REG_B24 = 81; + public static final int TMS320C64X_REG_B25 = 82; + public static final int TMS320C64X_REG_B26 = 83; + public static final int TMS320C64X_REG_B27 = 84; + public static final int TMS320C64X_REG_B28 = 85; + public static final int TMS320C64X_REG_B29 = 86; + public static final int TMS320C64X_REG_B30 = 87; + public static final int TMS320C64X_REG_B31 = 88; + public static final int TMS320C64X_REG_PCE1 = 89; + public static final int TMS320C64X_REG_ENDING = 90; + public static final int TMS320C64X_REG_EFR = TMS320C64X_REG_ECR; + public static final int TMS320C64X_REG_IFR = TMS320C64X_REG_ISR; + + public static final int TMS320C64X_INS_INVALID = 0; + public static final int TMS320C64X_INS_ABS = 1; + public static final int TMS320C64X_INS_ABS2 = 2; + public static final int TMS320C64X_INS_ADD = 3; + public static final int TMS320C64X_INS_ADD2 = 4; + public static final int TMS320C64X_INS_ADD4 = 5; + public static final int TMS320C64X_INS_ADDAB = 6; + public static final int TMS320C64X_INS_ADDAD = 7; + public static final int TMS320C64X_INS_ADDAH = 8; + public static final int TMS320C64X_INS_ADDAW = 9; + public static final int TMS320C64X_INS_ADDK = 10; + public static final int TMS320C64X_INS_ADDKPC = 11; + public static final int TMS320C64X_INS_ADDU = 12; + public static final int TMS320C64X_INS_AND = 13; + public static final int TMS320C64X_INS_ANDN = 14; + public static final int TMS320C64X_INS_AVG2 = 15; + public static final int TMS320C64X_INS_AVGU4 = 16; + public static final int TMS320C64X_INS_B = 17; + public static final int TMS320C64X_INS_BDEC = 18; + public static final int TMS320C64X_INS_BITC4 = 19; + public static final int TMS320C64X_INS_BNOP = 20; + public static final int TMS320C64X_INS_BPOS = 21; + public static final int TMS320C64X_INS_CLR = 22; + public static final int TMS320C64X_INS_CMPEQ = 23; + public static final int TMS320C64X_INS_CMPEQ2 = 24; + public static final int TMS320C64X_INS_CMPEQ4 = 25; + public static final int TMS320C64X_INS_CMPGT = 26; + public static final int TMS320C64X_INS_CMPGT2 = 27; + public static final int TMS320C64X_INS_CMPGTU4 = 28; + public static final int TMS320C64X_INS_CMPLT = 29; + public static final int TMS320C64X_INS_CMPLTU = 30; + public static final int TMS320C64X_INS_DEAL = 31; + public static final int TMS320C64X_INS_DOTP2 = 32; + public static final int TMS320C64X_INS_DOTPN2 = 33; + public static final int TMS320C64X_INS_DOTPNRSU2 = 34; + public static final int TMS320C64X_INS_DOTPRSU2 = 35; + public static final int TMS320C64X_INS_DOTPSU4 = 36; + public static final int TMS320C64X_INS_DOTPU4 = 37; + public static final int TMS320C64X_INS_EXT = 38; + public static final int TMS320C64X_INS_EXTU = 39; + public static final int TMS320C64X_INS_GMPGTU = 40; + public static final int TMS320C64X_INS_GMPY4 = 41; + public static final int TMS320C64X_INS_LDB = 42; + public static final int TMS320C64X_INS_LDBU = 43; + public static final int TMS320C64X_INS_LDDW = 44; + public static final int TMS320C64X_INS_LDH = 45; + public static final int TMS320C64X_INS_LDHU = 46; + public static final int TMS320C64X_INS_LDNDW = 47; + public static final int TMS320C64X_INS_LDNW = 48; + public static final int TMS320C64X_INS_LDW = 49; + public static final int TMS320C64X_INS_LMBD = 50; + public static final int TMS320C64X_INS_MAX2 = 51; + public static final int TMS320C64X_INS_MAXU4 = 52; + public static final int TMS320C64X_INS_MIN2 = 53; + public static final int TMS320C64X_INS_MINU4 = 54; + public static final int TMS320C64X_INS_MPY = 55; + public static final int TMS320C64X_INS_MPY2 = 56; + public static final int TMS320C64X_INS_MPYH = 57; + public static final int TMS320C64X_INS_MPYHI = 58; + public static final int TMS320C64X_INS_MPYHIR = 59; + public static final int TMS320C64X_INS_MPYHL = 60; + public static final int TMS320C64X_INS_MPYHLU = 61; + public static final int TMS320C64X_INS_MPYHSLU = 62; + public static final int TMS320C64X_INS_MPYHSU = 63; + public static final int TMS320C64X_INS_MPYHU = 64; + public static final int TMS320C64X_INS_MPYHULS = 65; + public static final int TMS320C64X_INS_MPYHUS = 66; + public static final int TMS320C64X_INS_MPYLH = 67; + public static final int TMS320C64X_INS_MPYLHU = 68; + public static final int TMS320C64X_INS_MPYLI = 69; + public static final int TMS320C64X_INS_MPYLIR = 70; + public static final int TMS320C64X_INS_MPYLSHU = 71; + public static final int TMS320C64X_INS_MPYLUHS = 72; + public static final int TMS320C64X_INS_MPYSU = 73; + public static final int TMS320C64X_INS_MPYSU4 = 74; + public static final int TMS320C64X_INS_MPYU = 75; + public static final int TMS320C64X_INS_MPYU4 = 76; + public static final int TMS320C64X_INS_MPYUS = 77; + public static final int TMS320C64X_INS_MVC = 78; + public static final int TMS320C64X_INS_MVD = 79; + public static final int TMS320C64X_INS_MVK = 80; + public static final int TMS320C64X_INS_MVKL = 81; + public static final int TMS320C64X_INS_MVKLH = 82; + public static final int TMS320C64X_INS_NOP = 83; + public static final int TMS320C64X_INS_NORM = 84; + public static final int TMS320C64X_INS_OR = 85; + public static final int TMS320C64X_INS_PACK2 = 86; + public static final int TMS320C64X_INS_PACKH2 = 87; + public static final int TMS320C64X_INS_PACKH4 = 88; + public static final int TMS320C64X_INS_PACKHL2 = 89; + public static final int TMS320C64X_INS_PACKL4 = 90; + public static final int TMS320C64X_INS_PACKLH2 = 91; + public static final int TMS320C64X_INS_ROTL = 92; + public static final int TMS320C64X_INS_SADD = 93; + public static final int TMS320C64X_INS_SADD2 = 94; + public static final int TMS320C64X_INS_SADDU4 = 95; + public static final int TMS320C64X_INS_SADDUS2 = 96; + public static final int TMS320C64X_INS_SAT = 97; + public static final int TMS320C64X_INS_SET = 98; + public static final int TMS320C64X_INS_SHFL = 99; + public static final int TMS320C64X_INS_SHL = 100; + public static final int TMS320C64X_INS_SHLMB = 101; + public static final int TMS320C64X_INS_SHR = 102; + public static final int TMS320C64X_INS_SHR2 = 103; + public static final int TMS320C64X_INS_SHRMB = 104; + public static final int TMS320C64X_INS_SHRU = 105; + public static final int TMS320C64X_INS_SHRU2 = 106; + public static final int TMS320C64X_INS_SMPY = 107; + public static final int TMS320C64X_INS_SMPY2 = 108; + public static final int TMS320C64X_INS_SMPYH = 109; + public static final int TMS320C64X_INS_SMPYHL = 110; + public static final int TMS320C64X_INS_SMPYLH = 111; + public static final int TMS320C64X_INS_SPACK2 = 112; + public static final int TMS320C64X_INS_SPACKU4 = 113; + public static final int TMS320C64X_INS_SSHL = 114; + public static final int TMS320C64X_INS_SSHVL = 115; + public static final int TMS320C64X_INS_SSHVR = 116; + public static final int TMS320C64X_INS_SSUB = 117; + public static final int TMS320C64X_INS_STB = 118; + public static final int TMS320C64X_INS_STDW = 119; + public static final int TMS320C64X_INS_STH = 120; + public static final int TMS320C64X_INS_STNDW = 121; + public static final int TMS320C64X_INS_STNW = 122; + public static final int TMS320C64X_INS_STW = 123; + public static final int TMS320C64X_INS_SUB = 124; + public static final int TMS320C64X_INS_SUB2 = 125; + public static final int TMS320C64X_INS_SUB4 = 126; + public static final int TMS320C64X_INS_SUBAB = 127; + public static final int TMS320C64X_INS_SUBABS4 = 128; + public static final int TMS320C64X_INS_SUBAH = 129; + public static final int TMS320C64X_INS_SUBAW = 130; + public static final int TMS320C64X_INS_SUBC = 131; + public static final int TMS320C64X_INS_SUBU = 132; + public static final int TMS320C64X_INS_SWAP4 = 133; + public static final int TMS320C64X_INS_UNPKHU4 = 134; + public static final int TMS320C64X_INS_UNPKLU4 = 135; + public static final int TMS320C64X_INS_XOR = 136; + public static final int TMS320C64X_INS_XPND2 = 137; + public static final int TMS320C64X_INS_XPND4 = 138; + public static final int TMS320C64X_INS_IDLE = 139; + public static final int TMS320C64X_INS_MV = 140; + public static final int TMS320C64X_INS_NEG = 141; + public static final int TMS320C64X_INS_NOT = 142; + public static final int TMS320C64X_INS_SWAP2 = 143; + public static final int TMS320C64X_INS_ZERO = 144; + public static final int TMS320C64X_INS_ENDING = 145; + + public static final int TMS320C64X_GRP_INVALID = 0; + public static final int TMS320C64X_GRP_JUMP = 1; + public static final int TMS320C64X_GRP_FUNIT_D = 128; + public static final int TMS320C64X_GRP_FUNIT_L = 129; + public static final int TMS320C64X_GRP_FUNIT_M = 130; + public static final int TMS320C64X_GRP_FUNIT_S = 131; + public static final int TMS320C64X_GRP_FUNIT_NO = 132; + public static final int TMS320C64X_GRP_ENDING = 133; + + public static final int TMS320C64X_FUNIT_INVALID = 0; + public static final int TMS320C64X_FUNIT_D = 1; + public static final int TMS320C64X_FUNIT_L = 2; + public static final int TMS320C64X_FUNIT_M = 3; + public static final int TMS320C64X_FUNIT_S = 4; + public static final int TMS320C64X_FUNIT_NO = 5; +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/java/capstone/X86.java b/white_patch_detect/capstone-master/bindings/java/capstone/X86.java new file mode 100644 index 0000000..6a8d1ed --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/java/capstone/X86.java @@ -0,0 +1,165 @@ +// Capstone Java binding +// By Nguyen Anh Quynh & Dang Hoang Vu, 2013 + +package capstone; + +import com.sun.jna.Structure; +import com.sun.jna.Union; + +import java.util.List; +import java.util.Arrays; + +import static capstone.X86_const.*; + +public class X86 { + + public static class MemType extends Structure { + public int segment; + public int base; + public int index; + public int scale; + public long disp; + + @Override + public List getFieldOrder() { + return Arrays.asList("segment", "base", "index", "scale", "disp"); + } + } + + public static class Encoding extends Structure { + public byte modrmOffset; + public byte dispOffset; + public byte dispSize; + public byte immOffset; + public byte immSize; + + @Override + public List getFieldOrder() { + return Arrays.asList("modrmOffset", "dispOffset", "dispSize", "immOffset", "immSize"); + } + } + + public static class OpValue extends Union { + public int reg; + public long imm; + public MemType mem; + + @Override + public List getFieldOrder() { + return Arrays.asList("reg", "imm", "mem"); + } + } + + public static class Operand extends Structure { + public int type; + public OpValue value; + public byte size; + public byte access; + public int avx_bcast; + public boolean avx_zero_opmask; + + public void read() { + super.read(); + if (type == X86_OP_MEM) + value.setType(MemType.class); + if (type == X86_OP_IMM) + value.setType(Long.TYPE); + if (type == X86_OP_REG) + value.setType(Integer.TYPE); + if (type == X86_OP_INVALID) + return; + readField("value"); + } + + @Override + public List getFieldOrder() { + return Arrays.asList("type", "value", "size", "access", "avx_bcast", "avx_zero_opmask"); + } + } + + public static class UnionOpInfo extends Capstone.UnionOpInfo { + public byte [] prefix; + public byte [] opcode; + public byte rex; + public byte addr_size; + public byte modrm; + public byte sib; + public long disp; + public int sib_index; + public byte sib_scale; + public int sib_base; + public int xop_cc; + public int sse_cc; + public int avx_cc; + public byte avx_sae; + public int avx_rm; + public long eflags; + + public byte op_count; + + public Operand [] op; + + public Encoding encoding; + + public UnionOpInfo() { + op = new Operand[8]; + opcode = new byte[4]; + prefix = new byte[4]; + } + + @Override + public List getFieldOrder() { + return Arrays.asList("prefix", "opcode", "rex", "addr_size", + "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "xop_cc", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "eflags", "op_count", "op", "encoding"); + } + } + + public static class OpInfo extends Capstone.OpInfo { + public byte [] prefix; + public byte [] opcode; + public byte opSize; + public byte rex; + public byte addrSize; + public byte dispSize; + public byte immSize; + public byte modrm; + public byte sib; + public long disp; + public int sibIndex; + public byte sibScale; + public int sibBase; + public int xopCC; + public int sseCC; + public int avxCC; + public boolean avxSae; + public int avxRm; + public long eflags; + + public Operand[] op; + + public Encoding encoding; + + public OpInfo(UnionOpInfo e) { + prefix = e.prefix; + opcode = e.opcode; + rex = e.rex; + addrSize = e.addr_size; + modrm = e.modrm; + sib = e.sib; + disp = e.disp; + sibIndex = e.sib_index; + sibScale = e.sib_scale; + sibBase = e.sib_base; + xopCC = e.xop_cc; + sseCC = e.sse_cc; + avxCC = e.avx_cc; + avxSae = e.avx_sae > 0; + avxRm = e.avx_rm; + eflags = e.eflags; + op = new Operand[e.op_count]; + for (int i=0; i, 2013-2015 + +LIB = capstone +FLAGS = '-Wall -Wextra -Wwrite-strings' +PYTHON2 ?= python + +all: arm_const.cmxa arm64_const.cmxa m680x_const.cmxa mips_const.cmxa ppc_const.cmxa sparc_const.cmxa sysz_const.cmxa x86_const.cmxa xcore_const.cmxa arm.cmxa arm64.cmxa m680x.cmxa mips.cmxa ppc.cmxa x86.cmxa sparc.cmxa systemz.cmxa xcore.cmxa capstone.cmxa test_basic.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_arm64.cmx test_mips.cmx test_ppc.cmx test_sparc.cmx test_systemz.cmx test_xcore.cmx test_m680x.cmx ocaml.o + ocamlopt -o test_basic -ccopt $(FLAGS) ocaml.o capstone.cmx test_basic.cmx -cclib -l$(LIB) + ocamlopt -o test_detail -ccopt $(FLAGS) capstone.cmx ocaml.o test_detail.cmx -cclib -l$(LIB) + ocamlopt -o test_x86 -ccopt $(FLAGS) capstone.cmx ocaml.o x86.cmx x86_const.cmx test_x86.cmx -cclib -l$(LIB) + ocamlopt -o test_arm -ccopt $(FLAGS) capstone.cmx ocaml.o arm.cmx arm_const.cmx test_arm.cmx -cclib -l$(LIB) + ocamlopt -o test_arm64 -ccopt $(FLAGS) capstone.cmx ocaml.o arm64.cmx arm64_const.cmx test_arm64.cmx -cclib -l$(LIB) + ocamlopt -o test_mips -ccopt $(FLAGS) capstone.cmx ocaml.o mips.cmx mips_const.cmx test_mips.cmx -cclib -l$(LIB) + ocamlopt -o test_ppc -ccopt $(FLAGS) capstone.cmx ocaml.o ppc.cmx ppc_const.cmx test_ppc.cmx -cclib -l$(LIB) + ocamlopt -o test_sparc -ccopt $(FLAGS) capstone.cmx ocaml.o sparc.cmx sparc_const.cmx test_sparc.cmx -cclib -l$(LIB) + ocamlopt -o test_systemz -ccopt $(FLAGS) capstone.cmx ocaml.o systemz.cmx sysz_const.cmx test_systemz.cmx -cclib -l$(LIB) + ocamlopt -o test_xcore -ccopt $(FLAGS) capstone.cmx ocaml.o xcore.cmx xcore_const.cmx test_xcore.cmx -cclib -l$(LIB) + ocamlopt -o test_m680x -ccopt $(FLAGS) capstone.cmx ocaml.o m680x.cmx m680x_const.cmx test_m680x.cmx -cclib -l$(LIB) + + +test_basic.cmx: test_basic.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_detail.cmx: test_detail.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_x86.cmx: test_x86.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_arm.cmx: test_arm.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_arm64.cmx: test_arm64.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_mips.cmx: test_mips.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_ppc.cmx: test_ppc.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_sparc.cmx: test_sparc.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_systemz.cmx: test_systemz.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_xcore.cmx: test_xcore.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +test_m680x.cmx: test_m680x.ml + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +ocaml.o: ocaml.c + ocamlc -ccopt $(FLAGS) -c $< + +capstone.mli: capstone.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +capstone.cmi: capstone.mli + ocamlc -ccopt $(FLAGS) -c $< + +capstone.cmx: capstone.ml capstone.cmi + ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) + +capstone.cmxa: capstone.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< -cclib -lsb_ocaml -cclib -l$(LIB) + +x86.mli: x86.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +x86.cmi: x86.mli + ocamlc -ccopt $(FLAGS) -c $< + +x86.cmx: x86.ml x86.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +x86.cmxa: x86.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +x86_const.mli: x86_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +x86_const.cmi: x86_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +x86_const.cmx: x86_const.ml x86_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +x86_const.cmxa: x86_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +arm.mli: arm.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +arm.cmi: arm.mli + ocamlc -ccopt $(FLAGS) -c $< + +arm.cmx: arm.ml arm.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +arm.cmxa: arm.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +arm_const.mli: arm_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +arm_const.cmi: arm_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +arm_const.cmx: arm_const.ml arm_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +arm_const.cmxa: arm_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +arm64.mli: arm64.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +arm64.cmi: arm64.mli + ocamlc -ccopt $(FLAGS) -c $< + +arm64.cmx: arm64.ml arm64.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +arm64.cmxa: arm64.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +arm64_const.mli: arm64_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +arm64_const.cmi: arm64_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +arm64_const.cmx: arm64_const.ml arm64_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +arm64_const.cmxa: arm64_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +m680x.mli: m680x.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +m680x.cmi: m680x.mli + ocamlc -ccopt $(FLAGS) -c $< + +m680x.cmx: m680x.ml m680x.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +m680x.cmxa: m680x.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +m680x_const.mli: m680x_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +m680x_const.cmi: m680x_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +m680x_const.cmx: m680x_const.ml m680x_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +m680x_const.cmxa: m680x_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +mips.mli: mips.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +mips.cmi: mips.mli + ocamlc -ccopt $(FLAGS) -c $< + +mips.cmx: mips.ml mips.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +mips.cmxa: mips.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +mips_const.mli: mips_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +mips_const.cmi: mips_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +mips_const.cmx: mips_const.ml mips_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +mips_const.cmxa: mips_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +ppc.mli: ppc.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +ppc.cmi: ppc.mli + ocamlc -ccopt $(FLAGS) -c $< + +ppc.cmx: ppc.ml ppc.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +ppc.cmxa: ppc.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +ppc_const.mli: ppc_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +ppc_const.cmi: ppc_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +ppc_const.cmx: ppc_const.ml ppc_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +ppc_const.cmxa: ppc_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +sparc.mli: sparc.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +sparc.cmi: sparc.mli + ocamlc -ccopt $(FLAGS) -c $< + +sparc.cmx: sparc.ml sparc.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +sparc.cmxa: sparc.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +sparc_const.mli: sparc_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +sparc_const.cmi: sparc_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +sparc_const.cmx: sparc_const.ml sparc_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +sparc_const.cmxa: sparc_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +systemz.mli: systemz.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +systemz.cmi: systemz.mli + ocamlc -ccopt $(FLAGS) -c $< + +systemz.cmx: systemz.ml systemz.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +systemz.cmxa: systemz.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +sysz_const.mli: sysz_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +sysz_const.cmi: sysz_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +sysz_const.cmx: sysz_const.ml sysz_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +sysz_const.cmxa: sysz_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +xcore.mli: xcore.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +xcore.cmi: xcore.mli + ocamlc -ccopt $(FLAGS) -c $< + +xcore.cmx: xcore.ml xcore.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +xcore.cmxa: xcore.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +xcore_const.mli: xcore_const.ml + ocamlc -ccopt $(FLAGS) -i $< > $@ + +xcore_const.cmi: xcore_const.mli + ocamlc -ccopt $(FLAGS) -c $< + +xcore_const.cmx: xcore_const.ml xcore_const.cmi + ocamlopt -ccopt $(FLAGS) -c $< + +xcore_const.cmxa: xcore_const.cmx + ocamlopt -ccopt $(FLAGS) -a -o $@ $< + +clean: + rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test_basic test_detail test_x86 test_arm test_arm64 test_mips test_ppc test_sparc test_systemz test_xcore test_m680x + +gen_const: + cd .. && $(PYTHON2) const_generator.py ocaml + +TESTS = test_basic test_detail test_arm test_arm64 test_m680x test_mips test_ppc +TESTS += test_sparc test_systemz test_x86 test_xcore +check: + @for t in $(TESTS); do \ + echo Check $$t ... ; \ + ./$$t > /dev/null && echo OK || echo FAILED; \ + done + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/README b/white_patch_detect/capstone-master/bindings/ocaml/README new file mode 100644 index 0000000..e395232 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/README @@ -0,0 +1,23 @@ +To compile Ocaml binding, Ocaml toolchain is needed. On Ubuntu Linux, +you can install Ocaml with: + + $ sudo apt-get install ocaml-nox + +To compile Ocaml binding, simply run "make" on the command line. + + +This directory also contains some test code to show how to use Capstone API. + +- test_basic.ml + This code shows the most simple form of API where we only want to get basic + information out of disassembled instruction, such as address, mnemonic and + operand string. + +- test_detail.ml: + This code shows how to access to architecture-neutral information in disassembled + instructions, such as implicit registers read/written, or groups of instructions + that this instruction belong to. + +- test_.ml + These code show how to access architecture-specific information for each + architecture. diff --git a/white_patch_detect/capstone-master/bindings/ocaml/arm.ml b/white_patch_detect/capstone-master/bindings/ocaml/arm.ml new file mode 100644 index 0000000..eb2de27 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/arm.ml @@ -0,0 +1,55 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Arm_const + +let _CS_OP_ARCH = 5;; +let _CS_OP_CIMM = _CS_OP_ARCH (* C-Immediate *) +let _CS_OP_PIMM = _CS_OP_ARCH + 1 (* P-Immediate *) + + +(* architecture specific info of instruction *) +type arm_op_shift = { + shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) + shift_value: int; +} + +type arm_op_mem = { + base: int; + index: int; + scale: int; + disp: int; + lshift: int; +} + +type arm_op_value = + | ARM_OP_INVALID of int + | ARM_OP_REG of int + | ARM_OP_CIMM of int + | ARM_OP_PIMM of int + | ARM_OP_IMM of int + | ARM_OP_FP of float + | ARM_OP_MEM of arm_op_mem + | ARM_OP_SETEND of int + +type arm_op = { + vector_index: int; + shift: arm_op_shift; + value: arm_op_value; + subtracted: bool; + access: int; + neon_lane: int; +} + +type cs_arm = { + usermode: bool; + vector_size: int; + vector_data: int; + cps_mode: int; + cps_flag: int; + cc: int; + update_flags: bool; + writeback: bool; + mem_barrier: int; + operands: arm_op array; +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/arm64.ml b/white_patch_detect/capstone-master/bindings/ocaml/arm64.ml new file mode 100644 index 0000000..1a5d981 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/arm64.ml @@ -0,0 +1,46 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Arm64_const + +(* architecture specific info of instruction *) +type arm64_op_shift = { + shift_type: int; + shift_value: int; +} + +type arm64_op_mem = { + base: int; + index: int; + disp: int +} + +type arm64_op_value = + | ARM64_OP_INVALID of int + | ARM64_OP_REG of int + | ARM64_OP_CIMM of int + | ARM64_OP_IMM of int + | ARM64_OP_FP of float + | ARM64_OP_MEM of arm64_op_mem + | ARM64_OP_REG_MRS of int + | ARM64_OP_REG_MSR of int + | ARM64_OP_PSTATE of int + | ARM64_OP_SYS of int + | ARM64_OP_PREFETCH of int + | ARM64_OP_BARRIER of int + +type arm64_op = { + vector_index: int; + vas: int; + vess: int; + shift: arm64_op_shift; + ext: int; + value: arm64_op_value; +} + +type cs_arm64 = { + cc: int; + update_flags: bool; + writeback: bool; + operands: arm64_op array; +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/arm64_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/arm64_const.ml new file mode 100644 index 0000000..aeae554 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/arm64_const.ml @@ -0,0 +1,1006 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.ml] *) + +let _ARM64_SFT_INVALID = 0;; +let _ARM64_SFT_LSL = 1;; +let _ARM64_SFT_MSL = 2;; +let _ARM64_SFT_LSR = 3;; +let _ARM64_SFT_ASR = 4;; +let _ARM64_SFT_ROR = 5;; + +let _ARM64_EXT_INVALID = 0;; +let _ARM64_EXT_UXTB = 1;; +let _ARM64_EXT_UXTH = 2;; +let _ARM64_EXT_UXTW = 3;; +let _ARM64_EXT_UXTX = 4;; +let _ARM64_EXT_SXTB = 5;; +let _ARM64_EXT_SXTH = 6;; +let _ARM64_EXT_SXTW = 7;; +let _ARM64_EXT_SXTX = 8;; + +let _ARM64_CC_INVALID = 0;; +let _ARM64_CC_EQ = 1;; +let _ARM64_CC_NE = 2;; +let _ARM64_CC_HS = 3;; +let _ARM64_CC_LO = 4;; +let _ARM64_CC_MI = 5;; +let _ARM64_CC_PL = 6;; +let _ARM64_CC_VS = 7;; +let _ARM64_CC_VC = 8;; +let _ARM64_CC_HI = 9;; +let _ARM64_CC_LS = 10;; +let _ARM64_CC_GE = 11;; +let _ARM64_CC_LT = 12;; +let _ARM64_CC_GT = 13;; +let _ARM64_CC_LE = 14;; +let _ARM64_CC_AL = 15;; +let _ARM64_CC_NV = 16;; + +let _ARM64_SYSREG_INVALID = 0;; +let _ARM64_SYSREG_MDCCSR_EL0 = 0x9808;; +let _ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828;; +let _ARM64_SYSREG_MDRAR_EL1 = 0x8080;; +let _ARM64_SYSREG_OSLSR_EL1 = 0x808c;; +let _ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6;; +let _ARM64_SYSREG_PMCEID0_EL0 = 0xdce6;; +let _ARM64_SYSREG_PMCEID1_EL0 = 0xdce7;; +let _ARM64_SYSREG_MIDR_EL1 = 0xc000;; +let _ARM64_SYSREG_CCSIDR_EL1 = 0xc800;; +let _ARM64_SYSREG_CLIDR_EL1 = 0xc801;; +let _ARM64_SYSREG_CTR_EL0 = 0xd801;; +let _ARM64_SYSREG_MPIDR_EL1 = 0xc005;; +let _ARM64_SYSREG_REVIDR_EL1 = 0xc006;; +let _ARM64_SYSREG_AIDR_EL1 = 0xc807;; +let _ARM64_SYSREG_DCZID_EL0 = 0xd807;; +let _ARM64_SYSREG_ID_PFR0_EL1 = 0xc008;; +let _ARM64_SYSREG_ID_PFR1_EL1 = 0xc009;; +let _ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a;; +let _ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b;; +let _ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c;; +let _ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d;; +let _ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e;; +let _ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f;; +let _ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010;; +let _ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011;; +let _ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012;; +let _ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013;; +let _ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014;; +let _ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015;; +let _ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020;; +let _ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021;; +let _ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028;; +let _ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029;; +let _ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c;; +let _ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d;; +let _ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030;; +let _ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031;; +let _ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038;; +let _ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039;; +let _ARM64_SYSREG_MVFR0_EL1 = 0xc018;; +let _ARM64_SYSREG_MVFR1_EL1 = 0xc019;; +let _ARM64_SYSREG_MVFR2_EL1 = 0xc01a;; +let _ARM64_SYSREG_RVBAR_EL1 = 0xc601;; +let _ARM64_SYSREG_RVBAR_EL2 = 0xe601;; +let _ARM64_SYSREG_RVBAR_EL3 = 0xf601;; +let _ARM64_SYSREG_ISR_EL1 = 0xc608;; +let _ARM64_SYSREG_CNTPCT_EL0 = 0xdf01;; +let _ARM64_SYSREG_CNTVCT_EL0 = 0xdf02;; +let _ARM64_SYSREG_TRCSTATR = 0x8818;; +let _ARM64_SYSREG_TRCIDR8 = 0x8806;; +let _ARM64_SYSREG_TRCIDR9 = 0x880e;; +let _ARM64_SYSREG_TRCIDR10 = 0x8816;; +let _ARM64_SYSREG_TRCIDR11 = 0x881e;; +let _ARM64_SYSREG_TRCIDR12 = 0x8826;; +let _ARM64_SYSREG_TRCIDR13 = 0x882e;; +let _ARM64_SYSREG_TRCIDR0 = 0x8847;; +let _ARM64_SYSREG_TRCIDR1 = 0x884f;; +let _ARM64_SYSREG_TRCIDR2 = 0x8857;; +let _ARM64_SYSREG_TRCIDR3 = 0x885f;; +let _ARM64_SYSREG_TRCIDR4 = 0x8867;; +let _ARM64_SYSREG_TRCIDR5 = 0x886f;; +let _ARM64_SYSREG_TRCIDR6 = 0x8877;; +let _ARM64_SYSREG_TRCIDR7 = 0x887f;; +let _ARM64_SYSREG_TRCOSLSR = 0x888c;; +let _ARM64_SYSREG_TRCPDSR = 0x88ac;; +let _ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6;; +let _ARM64_SYSREG_TRCDEVAFF1 = 0x8bde;; +let _ARM64_SYSREG_TRCLSR = 0x8bee;; +let _ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6;; +let _ARM64_SYSREG_TRCDEVARCH = 0x8bfe;; +let _ARM64_SYSREG_TRCDEVID = 0x8b97;; +let _ARM64_SYSREG_TRCDEVTYPE = 0x8b9f;; +let _ARM64_SYSREG_TRCPIDR4 = 0x8ba7;; +let _ARM64_SYSREG_TRCPIDR5 = 0x8baf;; +let _ARM64_SYSREG_TRCPIDR6 = 0x8bb7;; +let _ARM64_SYSREG_TRCPIDR7 = 0x8bbf;; +let _ARM64_SYSREG_TRCPIDR0 = 0x8bc7;; +let _ARM64_SYSREG_TRCPIDR1 = 0x8bcf;; +let _ARM64_SYSREG_TRCPIDR2 = 0x8bd7;; +let _ARM64_SYSREG_TRCPIDR3 = 0x8bdf;; +let _ARM64_SYSREG_TRCCIDR0 = 0x8be7;; +let _ARM64_SYSREG_TRCCIDR1 = 0x8bef;; +let _ARM64_SYSREG_TRCCIDR2 = 0x8bf7;; +let _ARM64_SYSREG_TRCCIDR3 = 0x8bff;; +let _ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660;; +let _ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640;; +let _ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662;; +let _ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642;; +let _ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b;; +let _ARM64_SYSREG_ICH_VTR_EL2 = 0xe659;; +let _ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b;; +let _ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d;; +let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;; +let _ARM64_SYSREG_OSLAR_EL1 = 0x8084;; +let _ARM64_SYSREG_PMSWINC_EL0 = 0xdce4;; +let _ARM64_SYSREG_TRCOSLAR = 0x8884;; +let _ARM64_SYSREG_TRCLAR = 0x8be6;; +let _ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661;; +let _ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641;; +let _ARM64_SYSREG_ICC_DIR_EL1 = 0xc659;; +let _ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d;; +let _ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e;; +let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f;; + +let _ARM64_PSTATE_INVALID = 0;; +let _ARM64_PSTATE_SPSEL = 0x05;; +let _ARM64_PSTATE_DAIFSET = 0x1e;; +let _ARM64_PSTATE_DAIFCLR = 0x1f;; + +let _ARM64_VAS_INVALID = 0;; +let _ARM64_VAS_8B = 1;; +let _ARM64_VAS_16B = 2;; +let _ARM64_VAS_4H = 3;; +let _ARM64_VAS_8H = 4;; +let _ARM64_VAS_2S = 5;; +let _ARM64_VAS_4S = 6;; +let _ARM64_VAS_1D = 7;; +let _ARM64_VAS_2D = 8;; +let _ARM64_VAS_1Q = 9;; + +let _ARM64_VESS_INVALID = 0;; +let _ARM64_VESS_B = 1;; +let _ARM64_VESS_H = 2;; +let _ARM64_VESS_S = 3;; +let _ARM64_VESS_D = 4;; + +let _ARM64_BARRIER_INVALID = 0;; +let _ARM64_BARRIER_OSHLD = 0x1;; +let _ARM64_BARRIER_OSHST = 0x2;; +let _ARM64_BARRIER_OSH = 0x3;; +let _ARM64_BARRIER_NSHLD = 0x5;; +let _ARM64_BARRIER_NSHST = 0x6;; +let _ARM64_BARRIER_NSH = 0x7;; +let _ARM64_BARRIER_ISHLD = 0x9;; +let _ARM64_BARRIER_ISHST = 0xa;; +let _ARM64_BARRIER_ISH = 0xb;; +let _ARM64_BARRIER_LD = 0xd;; +let _ARM64_BARRIER_ST = 0xe;; +let _ARM64_BARRIER_SY = 0xf;; + +let _ARM64_OP_INVALID = 0;; +let _ARM64_OP_REG = 1;; +let _ARM64_OP_IMM = 2;; +let _ARM64_OP_MEM = 3;; +let _ARM64_OP_FP = 4;; +let _ARM64_OP_CIMM = 64;; +let _ARM64_OP_REG_MRS = 65;; +let _ARM64_OP_REG_MSR = 66;; +let _ARM64_OP_PSTATE = 67;; +let _ARM64_OP_SYS = 68;; +let _ARM64_OP_PREFETCH = 69;; +let _ARM64_OP_BARRIER = 70;; + +let _ARM64_TLBI_INVALID = 0;; +let _ARM64_TLBI_VMALLE1IS = 1;; +let _ARM64_TLBI_VAE1IS = 2;; +let _ARM64_TLBI_ASIDE1IS = 3;; +let _ARM64_TLBI_VAAE1IS = 4;; +let _ARM64_TLBI_VALE1IS = 5;; +let _ARM64_TLBI_VAALE1IS = 6;; +let _ARM64_TLBI_ALLE2IS = 7;; +let _ARM64_TLBI_VAE2IS = 8;; +let _ARM64_TLBI_ALLE1IS = 9;; +let _ARM64_TLBI_VALE2IS = 10;; +let _ARM64_TLBI_VMALLS12E1IS = 11;; +let _ARM64_TLBI_ALLE3IS = 12;; +let _ARM64_TLBI_VAE3IS = 13;; +let _ARM64_TLBI_VALE3IS = 14;; +let _ARM64_TLBI_IPAS2E1IS = 15;; +let _ARM64_TLBI_IPAS2LE1IS = 16;; +let _ARM64_TLBI_IPAS2E1 = 17;; +let _ARM64_TLBI_IPAS2LE1 = 18;; +let _ARM64_TLBI_VMALLE1 = 19;; +let _ARM64_TLBI_VAE1 = 20;; +let _ARM64_TLBI_ASIDE1 = 21;; +let _ARM64_TLBI_VAAE1 = 22;; +let _ARM64_TLBI_VALE1 = 23;; +let _ARM64_TLBI_VAALE1 = 24;; +let _ARM64_TLBI_ALLE2 = 25;; +let _ARM64_TLBI_VAE2 = 26;; +let _ARM64_TLBI_ALLE1 = 27;; +let _ARM64_TLBI_VALE2 = 28;; +let _ARM64_TLBI_VMALLS12E1 = 29;; +let _ARM64_TLBI_ALLE3 = 30;; +let _ARM64_TLBI_VAE3 = 31;; +let _ARM64_TLBI_VALE3 = 32;; +let _ARM64_AT_S1E1R = 33;; +let _ARM64_AT_S1E1W = 34;; +let _ARM64_AT_S1E0R = 35;; +let _ARM64_AT_S1E0W = 36;; +let _ARM64_AT_S1E2R = 37;; +let _ARM64_AT_S1E2W = 38;; +let _ARM64_AT_S12E1R = 39;; +let _ARM64_AT_S12E1W = 40;; +let _ARM64_AT_S12E0R = 41;; +let _ARM64_AT_S12E0W = 42;; +let _ARM64_AT_S1E3R = 43;; +let _ARM64_AT_S1E3W = 44;; + +let _ARM64_DC_INVALID = 0;; +let _ARM64_DC_ZVA = 1;; +let _ARM64_DC_IVAC = 2;; +let _ARM64_DC_ISW = 3;; +let _ARM64_DC_CVAC = 4;; +let _ARM64_DC_CSW = 5;; +let _ARM64_DC_CVAU = 6;; +let _ARM64_DC_CIVAC = 7;; +let _ARM64_DC_CISW = 8;; + +let _ARM64_IC_INVALID = 0;; +let _ARM64_IC_IALLUIS = 1;; +let _ARM64_IC_IALLU = 2;; +let _ARM64_IC_IVAU = 3;; + +let _ARM64_PRFM_INVALID = 0;; +let _ARM64_PRFM_PLDL1KEEP = 0x00+1;; +let _ARM64_PRFM_PLDL1STRM = 0x01+1;; +let _ARM64_PRFM_PLDL2KEEP = 0x02+1;; +let _ARM64_PRFM_PLDL2STRM = 0x03+1;; +let _ARM64_PRFM_PLDL3KEEP = 0x04+1;; +let _ARM64_PRFM_PLDL3STRM = 0x05+1;; +let _ARM64_PRFM_PLIL1KEEP = 0x08+1;; +let _ARM64_PRFM_PLIL1STRM = 0x09+1;; +let _ARM64_PRFM_PLIL2KEEP = 0x0a+1;; +let _ARM64_PRFM_PLIL2STRM = 0x0b+1;; +let _ARM64_PRFM_PLIL3KEEP = 0x0c+1;; +let _ARM64_PRFM_PLIL3STRM = 0x0d+1;; +let _ARM64_PRFM_PSTL1KEEP = 0x10+1;; +let _ARM64_PRFM_PSTL1STRM = 0x11+1;; +let _ARM64_PRFM_PSTL2KEEP = 0x12+1;; +let _ARM64_PRFM_PSTL2STRM = 0x13+1;; +let _ARM64_PRFM_PSTL3KEEP = 0x14+1;; +let _ARM64_PRFM_PSTL3STRM = 0x15+1;; + +let _ARM64_REG_INVALID = 0;; +let _ARM64_REG_X29 = 1;; +let _ARM64_REG_X30 = 2;; +let _ARM64_REG_NZCV = 3;; +let _ARM64_REG_SP = 4;; +let _ARM64_REG_WSP = 5;; +let _ARM64_REG_WZR = 6;; +let _ARM64_REG_XZR = 7;; +let _ARM64_REG_B0 = 8;; +let _ARM64_REG_B1 = 9;; +let _ARM64_REG_B2 = 10;; +let _ARM64_REG_B3 = 11;; +let _ARM64_REG_B4 = 12;; +let _ARM64_REG_B5 = 13;; +let _ARM64_REG_B6 = 14;; +let _ARM64_REG_B7 = 15;; +let _ARM64_REG_B8 = 16;; +let _ARM64_REG_B9 = 17;; +let _ARM64_REG_B10 = 18;; +let _ARM64_REG_B11 = 19;; +let _ARM64_REG_B12 = 20;; +let _ARM64_REG_B13 = 21;; +let _ARM64_REG_B14 = 22;; +let _ARM64_REG_B15 = 23;; +let _ARM64_REG_B16 = 24;; +let _ARM64_REG_B17 = 25;; +let _ARM64_REG_B18 = 26;; +let _ARM64_REG_B19 = 27;; +let _ARM64_REG_B20 = 28;; +let _ARM64_REG_B21 = 29;; +let _ARM64_REG_B22 = 30;; +let _ARM64_REG_B23 = 31;; +let _ARM64_REG_B24 = 32;; +let _ARM64_REG_B25 = 33;; +let _ARM64_REG_B26 = 34;; +let _ARM64_REG_B27 = 35;; +let _ARM64_REG_B28 = 36;; +let _ARM64_REG_B29 = 37;; +let _ARM64_REG_B30 = 38;; +let _ARM64_REG_B31 = 39;; +let _ARM64_REG_D0 = 40;; +let _ARM64_REG_D1 = 41;; +let _ARM64_REG_D2 = 42;; +let _ARM64_REG_D3 = 43;; +let _ARM64_REG_D4 = 44;; +let _ARM64_REG_D5 = 45;; +let _ARM64_REG_D6 = 46;; +let _ARM64_REG_D7 = 47;; +let _ARM64_REG_D8 = 48;; +let _ARM64_REG_D9 = 49;; +let _ARM64_REG_D10 = 50;; +let _ARM64_REG_D11 = 51;; +let _ARM64_REG_D12 = 52;; +let _ARM64_REG_D13 = 53;; +let _ARM64_REG_D14 = 54;; +let _ARM64_REG_D15 = 55;; +let _ARM64_REG_D16 = 56;; +let _ARM64_REG_D17 = 57;; +let _ARM64_REG_D18 = 58;; +let _ARM64_REG_D19 = 59;; +let _ARM64_REG_D20 = 60;; +let _ARM64_REG_D21 = 61;; +let _ARM64_REG_D22 = 62;; +let _ARM64_REG_D23 = 63;; +let _ARM64_REG_D24 = 64;; +let _ARM64_REG_D25 = 65;; +let _ARM64_REG_D26 = 66;; +let _ARM64_REG_D27 = 67;; +let _ARM64_REG_D28 = 68;; +let _ARM64_REG_D29 = 69;; +let _ARM64_REG_D30 = 70;; +let _ARM64_REG_D31 = 71;; +let _ARM64_REG_H0 = 72;; +let _ARM64_REG_H1 = 73;; +let _ARM64_REG_H2 = 74;; +let _ARM64_REG_H3 = 75;; +let _ARM64_REG_H4 = 76;; +let _ARM64_REG_H5 = 77;; +let _ARM64_REG_H6 = 78;; +let _ARM64_REG_H7 = 79;; +let _ARM64_REG_H8 = 80;; +let _ARM64_REG_H9 = 81;; +let _ARM64_REG_H10 = 82;; +let _ARM64_REG_H11 = 83;; +let _ARM64_REG_H12 = 84;; +let _ARM64_REG_H13 = 85;; +let _ARM64_REG_H14 = 86;; +let _ARM64_REG_H15 = 87;; +let _ARM64_REG_H16 = 88;; +let _ARM64_REG_H17 = 89;; +let _ARM64_REG_H18 = 90;; +let _ARM64_REG_H19 = 91;; +let _ARM64_REG_H20 = 92;; +let _ARM64_REG_H21 = 93;; +let _ARM64_REG_H22 = 94;; +let _ARM64_REG_H23 = 95;; +let _ARM64_REG_H24 = 96;; +let _ARM64_REG_H25 = 97;; +let _ARM64_REG_H26 = 98;; +let _ARM64_REG_H27 = 99;; +let _ARM64_REG_H28 = 100;; +let _ARM64_REG_H29 = 101;; +let _ARM64_REG_H30 = 102;; +let _ARM64_REG_H31 = 103;; +let _ARM64_REG_Q0 = 104;; +let _ARM64_REG_Q1 = 105;; +let _ARM64_REG_Q2 = 106;; +let _ARM64_REG_Q3 = 107;; +let _ARM64_REG_Q4 = 108;; +let _ARM64_REG_Q5 = 109;; +let _ARM64_REG_Q6 = 110;; +let _ARM64_REG_Q7 = 111;; +let _ARM64_REG_Q8 = 112;; +let _ARM64_REG_Q9 = 113;; +let _ARM64_REG_Q10 = 114;; +let _ARM64_REG_Q11 = 115;; +let _ARM64_REG_Q12 = 116;; +let _ARM64_REG_Q13 = 117;; +let _ARM64_REG_Q14 = 118;; +let _ARM64_REG_Q15 = 119;; +let _ARM64_REG_Q16 = 120;; +let _ARM64_REG_Q17 = 121;; +let _ARM64_REG_Q18 = 122;; +let _ARM64_REG_Q19 = 123;; +let _ARM64_REG_Q20 = 124;; +let _ARM64_REG_Q21 = 125;; +let _ARM64_REG_Q22 = 126;; +let _ARM64_REG_Q23 = 127;; +let _ARM64_REG_Q24 = 128;; +let _ARM64_REG_Q25 = 129;; +let _ARM64_REG_Q26 = 130;; +let _ARM64_REG_Q27 = 131;; +let _ARM64_REG_Q28 = 132;; +let _ARM64_REG_Q29 = 133;; +let _ARM64_REG_Q30 = 134;; +let _ARM64_REG_Q31 = 135;; +let _ARM64_REG_S0 = 136;; +let _ARM64_REG_S1 = 137;; +let _ARM64_REG_S2 = 138;; +let _ARM64_REG_S3 = 139;; +let _ARM64_REG_S4 = 140;; +let _ARM64_REG_S5 = 141;; +let _ARM64_REG_S6 = 142;; +let _ARM64_REG_S7 = 143;; +let _ARM64_REG_S8 = 144;; +let _ARM64_REG_S9 = 145;; +let _ARM64_REG_S10 = 146;; +let _ARM64_REG_S11 = 147;; +let _ARM64_REG_S12 = 148;; +let _ARM64_REG_S13 = 149;; +let _ARM64_REG_S14 = 150;; +let _ARM64_REG_S15 = 151;; +let _ARM64_REG_S16 = 152;; +let _ARM64_REG_S17 = 153;; +let _ARM64_REG_S18 = 154;; +let _ARM64_REG_S19 = 155;; +let _ARM64_REG_S20 = 156;; +let _ARM64_REG_S21 = 157;; +let _ARM64_REG_S22 = 158;; +let _ARM64_REG_S23 = 159;; +let _ARM64_REG_S24 = 160;; +let _ARM64_REG_S25 = 161;; +let _ARM64_REG_S26 = 162;; +let _ARM64_REG_S27 = 163;; +let _ARM64_REG_S28 = 164;; +let _ARM64_REG_S29 = 165;; +let _ARM64_REG_S30 = 166;; +let _ARM64_REG_S31 = 167;; +let _ARM64_REG_W0 = 168;; +let _ARM64_REG_W1 = 169;; +let _ARM64_REG_W2 = 170;; +let _ARM64_REG_W3 = 171;; +let _ARM64_REG_W4 = 172;; +let _ARM64_REG_W5 = 173;; +let _ARM64_REG_W6 = 174;; +let _ARM64_REG_W7 = 175;; +let _ARM64_REG_W8 = 176;; +let _ARM64_REG_W9 = 177;; +let _ARM64_REG_W10 = 178;; +let _ARM64_REG_W11 = 179;; +let _ARM64_REG_W12 = 180;; +let _ARM64_REG_W13 = 181;; +let _ARM64_REG_W14 = 182;; +let _ARM64_REG_W15 = 183;; +let _ARM64_REG_W16 = 184;; +let _ARM64_REG_W17 = 185;; +let _ARM64_REG_W18 = 186;; +let _ARM64_REG_W19 = 187;; +let _ARM64_REG_W20 = 188;; +let _ARM64_REG_W21 = 189;; +let _ARM64_REG_W22 = 190;; +let _ARM64_REG_W23 = 191;; +let _ARM64_REG_W24 = 192;; +let _ARM64_REG_W25 = 193;; +let _ARM64_REG_W26 = 194;; +let _ARM64_REG_W27 = 195;; +let _ARM64_REG_W28 = 196;; +let _ARM64_REG_W29 = 197;; +let _ARM64_REG_W30 = 198;; +let _ARM64_REG_X0 = 199;; +let _ARM64_REG_X1 = 200;; +let _ARM64_REG_X2 = 201;; +let _ARM64_REG_X3 = 202;; +let _ARM64_REG_X4 = 203;; +let _ARM64_REG_X5 = 204;; +let _ARM64_REG_X6 = 205;; +let _ARM64_REG_X7 = 206;; +let _ARM64_REG_X8 = 207;; +let _ARM64_REG_X9 = 208;; +let _ARM64_REG_X10 = 209;; +let _ARM64_REG_X11 = 210;; +let _ARM64_REG_X12 = 211;; +let _ARM64_REG_X13 = 212;; +let _ARM64_REG_X14 = 213;; +let _ARM64_REG_X15 = 214;; +let _ARM64_REG_X16 = 215;; +let _ARM64_REG_X17 = 216;; +let _ARM64_REG_X18 = 217;; +let _ARM64_REG_X19 = 218;; +let _ARM64_REG_X20 = 219;; +let _ARM64_REG_X21 = 220;; +let _ARM64_REG_X22 = 221;; +let _ARM64_REG_X23 = 222;; +let _ARM64_REG_X24 = 223;; +let _ARM64_REG_X25 = 224;; +let _ARM64_REG_X26 = 225;; +let _ARM64_REG_X27 = 226;; +let _ARM64_REG_X28 = 227;; +let _ARM64_REG_V0 = 228;; +let _ARM64_REG_V1 = 229;; +let _ARM64_REG_V2 = 230;; +let _ARM64_REG_V3 = 231;; +let _ARM64_REG_V4 = 232;; +let _ARM64_REG_V5 = 233;; +let _ARM64_REG_V6 = 234;; +let _ARM64_REG_V7 = 235;; +let _ARM64_REG_V8 = 236;; +let _ARM64_REG_V9 = 237;; +let _ARM64_REG_V10 = 238;; +let _ARM64_REG_V11 = 239;; +let _ARM64_REG_V12 = 240;; +let _ARM64_REG_V13 = 241;; +let _ARM64_REG_V14 = 242;; +let _ARM64_REG_V15 = 243;; +let _ARM64_REG_V16 = 244;; +let _ARM64_REG_V17 = 245;; +let _ARM64_REG_V18 = 246;; +let _ARM64_REG_V19 = 247;; +let _ARM64_REG_V20 = 248;; +let _ARM64_REG_V21 = 249;; +let _ARM64_REG_V22 = 250;; +let _ARM64_REG_V23 = 251;; +let _ARM64_REG_V24 = 252;; +let _ARM64_REG_V25 = 253;; +let _ARM64_REG_V26 = 254;; +let _ARM64_REG_V27 = 255;; +let _ARM64_REG_V28 = 256;; +let _ARM64_REG_V29 = 257;; +let _ARM64_REG_V30 = 258;; +let _ARM64_REG_V31 = 259;; +let _ARM64_REG_ENDING = 260;; +let _ARM64_REG_IP0 = _ARM64_REG_X16;; +let _ARM64_REG_IP1 = _ARM64_REG_X17;; +let _ARM64_REG_FP = _ARM64_REG_X29;; +let _ARM64_REG_LR = _ARM64_REG_X30;; + +let _ARM64_INS_INVALID = 0;; +let _ARM64_INS_ABS = 1;; +let _ARM64_INS_ADC = 2;; +let _ARM64_INS_ADDHN = 3;; +let _ARM64_INS_ADDHN2 = 4;; +let _ARM64_INS_ADDP = 5;; +let _ARM64_INS_ADD = 6;; +let _ARM64_INS_ADDV = 7;; +let _ARM64_INS_ADR = 8;; +let _ARM64_INS_ADRP = 9;; +let _ARM64_INS_AESD = 10;; +let _ARM64_INS_AESE = 11;; +let _ARM64_INS_AESIMC = 12;; +let _ARM64_INS_AESMC = 13;; +let _ARM64_INS_AND = 14;; +let _ARM64_INS_ASR = 15;; +let _ARM64_INS_B = 16;; +let _ARM64_INS_BFM = 17;; +let _ARM64_INS_BIC = 18;; +let _ARM64_INS_BIF = 19;; +let _ARM64_INS_BIT = 20;; +let _ARM64_INS_BL = 21;; +let _ARM64_INS_BLR = 22;; +let _ARM64_INS_BR = 23;; +let _ARM64_INS_BRK = 24;; +let _ARM64_INS_BSL = 25;; +let _ARM64_INS_CBNZ = 26;; +let _ARM64_INS_CBZ = 27;; +let _ARM64_INS_CCMN = 28;; +let _ARM64_INS_CCMP = 29;; +let _ARM64_INS_CLREX = 30;; +let _ARM64_INS_CLS = 31;; +let _ARM64_INS_CLZ = 32;; +let _ARM64_INS_CMEQ = 33;; +let _ARM64_INS_CMGE = 34;; +let _ARM64_INS_CMGT = 35;; +let _ARM64_INS_CMHI = 36;; +let _ARM64_INS_CMHS = 37;; +let _ARM64_INS_CMLE = 38;; +let _ARM64_INS_CMLT = 39;; +let _ARM64_INS_CMTST = 40;; +let _ARM64_INS_CNT = 41;; +let _ARM64_INS_MOV = 42;; +let _ARM64_INS_CRC32B = 43;; +let _ARM64_INS_CRC32CB = 44;; +let _ARM64_INS_CRC32CH = 45;; +let _ARM64_INS_CRC32CW = 46;; +let _ARM64_INS_CRC32CX = 47;; +let _ARM64_INS_CRC32H = 48;; +let _ARM64_INS_CRC32W = 49;; +let _ARM64_INS_CRC32X = 50;; +let _ARM64_INS_CSEL = 51;; +let _ARM64_INS_CSINC = 52;; +let _ARM64_INS_CSINV = 53;; +let _ARM64_INS_CSNEG = 54;; +let _ARM64_INS_DCPS1 = 55;; +let _ARM64_INS_DCPS2 = 56;; +let _ARM64_INS_DCPS3 = 57;; +let _ARM64_INS_DMB = 58;; +let _ARM64_INS_DRPS = 59;; +let _ARM64_INS_DSB = 60;; +let _ARM64_INS_DUP = 61;; +let _ARM64_INS_EON = 62;; +let _ARM64_INS_EOR = 63;; +let _ARM64_INS_ERET = 64;; +let _ARM64_INS_EXTR = 65;; +let _ARM64_INS_EXT = 66;; +let _ARM64_INS_FABD = 67;; +let _ARM64_INS_FABS = 68;; +let _ARM64_INS_FACGE = 69;; +let _ARM64_INS_FACGT = 70;; +let _ARM64_INS_FADD = 71;; +let _ARM64_INS_FADDP = 72;; +let _ARM64_INS_FCCMP = 73;; +let _ARM64_INS_FCCMPE = 74;; +let _ARM64_INS_FCMEQ = 75;; +let _ARM64_INS_FCMGE = 76;; +let _ARM64_INS_FCMGT = 77;; +let _ARM64_INS_FCMLE = 78;; +let _ARM64_INS_FCMLT = 79;; +let _ARM64_INS_FCMP = 80;; +let _ARM64_INS_FCMPE = 81;; +let _ARM64_INS_FCSEL = 82;; +let _ARM64_INS_FCVTAS = 83;; +let _ARM64_INS_FCVTAU = 84;; +let _ARM64_INS_FCVT = 85;; +let _ARM64_INS_FCVTL = 86;; +let _ARM64_INS_FCVTL2 = 87;; +let _ARM64_INS_FCVTMS = 88;; +let _ARM64_INS_FCVTMU = 89;; +let _ARM64_INS_FCVTNS = 90;; +let _ARM64_INS_FCVTNU = 91;; +let _ARM64_INS_FCVTN = 92;; +let _ARM64_INS_FCVTN2 = 93;; +let _ARM64_INS_FCVTPS = 94;; +let _ARM64_INS_FCVTPU = 95;; +let _ARM64_INS_FCVTXN = 96;; +let _ARM64_INS_FCVTXN2 = 97;; +let _ARM64_INS_FCVTZS = 98;; +let _ARM64_INS_FCVTZU = 99;; +let _ARM64_INS_FDIV = 100;; +let _ARM64_INS_FMADD = 101;; +let _ARM64_INS_FMAX = 102;; +let _ARM64_INS_FMAXNM = 103;; +let _ARM64_INS_FMAXNMP = 104;; +let _ARM64_INS_FMAXNMV = 105;; +let _ARM64_INS_FMAXP = 106;; +let _ARM64_INS_FMAXV = 107;; +let _ARM64_INS_FMIN = 108;; +let _ARM64_INS_FMINNM = 109;; +let _ARM64_INS_FMINNMP = 110;; +let _ARM64_INS_FMINNMV = 111;; +let _ARM64_INS_FMINP = 112;; +let _ARM64_INS_FMINV = 113;; +let _ARM64_INS_FMLA = 114;; +let _ARM64_INS_FMLS = 115;; +let _ARM64_INS_FMOV = 116;; +let _ARM64_INS_FMSUB = 117;; +let _ARM64_INS_FMUL = 118;; +let _ARM64_INS_FMULX = 119;; +let _ARM64_INS_FNEG = 120;; +let _ARM64_INS_FNMADD = 121;; +let _ARM64_INS_FNMSUB = 122;; +let _ARM64_INS_FNMUL = 123;; +let _ARM64_INS_FRECPE = 124;; +let _ARM64_INS_FRECPS = 125;; +let _ARM64_INS_FRECPX = 126;; +let _ARM64_INS_FRINTA = 127;; +let _ARM64_INS_FRINTI = 128;; +let _ARM64_INS_FRINTM = 129;; +let _ARM64_INS_FRINTN = 130;; +let _ARM64_INS_FRINTP = 131;; +let _ARM64_INS_FRINTX = 132;; +let _ARM64_INS_FRINTZ = 133;; +let _ARM64_INS_FRSQRTE = 134;; +let _ARM64_INS_FRSQRTS = 135;; +let _ARM64_INS_FSQRT = 136;; +let _ARM64_INS_FSUB = 137;; +let _ARM64_INS_HINT = 138;; +let _ARM64_INS_HLT = 139;; +let _ARM64_INS_HVC = 140;; +let _ARM64_INS_INS = 141;; +let _ARM64_INS_ISB = 142;; +let _ARM64_INS_LD1 = 143;; +let _ARM64_INS_LD1R = 144;; +let _ARM64_INS_LD2R = 145;; +let _ARM64_INS_LD2 = 146;; +let _ARM64_INS_LD3R = 147;; +let _ARM64_INS_LD3 = 148;; +let _ARM64_INS_LD4 = 149;; +let _ARM64_INS_LD4R = 150;; +let _ARM64_INS_LDARB = 151;; +let _ARM64_INS_LDARH = 152;; +let _ARM64_INS_LDAR = 153;; +let _ARM64_INS_LDAXP = 154;; +let _ARM64_INS_LDAXRB = 155;; +let _ARM64_INS_LDAXRH = 156;; +let _ARM64_INS_LDAXR = 157;; +let _ARM64_INS_LDNP = 158;; +let _ARM64_INS_LDP = 159;; +let _ARM64_INS_LDPSW = 160;; +let _ARM64_INS_LDRB = 161;; +let _ARM64_INS_LDR = 162;; +let _ARM64_INS_LDRH = 163;; +let _ARM64_INS_LDRSB = 164;; +let _ARM64_INS_LDRSH = 165;; +let _ARM64_INS_LDRSW = 166;; +let _ARM64_INS_LDTRB = 167;; +let _ARM64_INS_LDTRH = 168;; +let _ARM64_INS_LDTRSB = 169;; +let _ARM64_INS_LDTRSH = 170;; +let _ARM64_INS_LDTRSW = 171;; +let _ARM64_INS_LDTR = 172;; +let _ARM64_INS_LDURB = 173;; +let _ARM64_INS_LDUR = 174;; +let _ARM64_INS_LDURH = 175;; +let _ARM64_INS_LDURSB = 176;; +let _ARM64_INS_LDURSH = 177;; +let _ARM64_INS_LDURSW = 178;; +let _ARM64_INS_LDXP = 179;; +let _ARM64_INS_LDXRB = 180;; +let _ARM64_INS_LDXRH = 181;; +let _ARM64_INS_LDXR = 182;; +let _ARM64_INS_LSL = 183;; +let _ARM64_INS_LSR = 184;; +let _ARM64_INS_MADD = 185;; +let _ARM64_INS_MLA = 186;; +let _ARM64_INS_MLS = 187;; +let _ARM64_INS_MOVI = 188;; +let _ARM64_INS_MOVK = 189;; +let _ARM64_INS_MOVN = 190;; +let _ARM64_INS_MOVZ = 191;; +let _ARM64_INS_MRS = 192;; +let _ARM64_INS_MSR = 193;; +let _ARM64_INS_MSUB = 194;; +let _ARM64_INS_MUL = 195;; +let _ARM64_INS_MVNI = 196;; +let _ARM64_INS_NEG = 197;; +let _ARM64_INS_NOT = 198;; +let _ARM64_INS_ORN = 199;; +let _ARM64_INS_ORR = 200;; +let _ARM64_INS_PMULL2 = 201;; +let _ARM64_INS_PMULL = 202;; +let _ARM64_INS_PMUL = 203;; +let _ARM64_INS_PRFM = 204;; +let _ARM64_INS_PRFUM = 205;; +let _ARM64_INS_RADDHN = 206;; +let _ARM64_INS_RADDHN2 = 207;; +let _ARM64_INS_RBIT = 208;; +let _ARM64_INS_RET = 209;; +let _ARM64_INS_REV16 = 210;; +let _ARM64_INS_REV32 = 211;; +let _ARM64_INS_REV64 = 212;; +let _ARM64_INS_REV = 213;; +let _ARM64_INS_ROR = 214;; +let _ARM64_INS_RSHRN2 = 215;; +let _ARM64_INS_RSHRN = 216;; +let _ARM64_INS_RSUBHN = 217;; +let _ARM64_INS_RSUBHN2 = 218;; +let _ARM64_INS_SABAL2 = 219;; +let _ARM64_INS_SABAL = 220;; +let _ARM64_INS_SABA = 221;; +let _ARM64_INS_SABDL2 = 222;; +let _ARM64_INS_SABDL = 223;; +let _ARM64_INS_SABD = 224;; +let _ARM64_INS_SADALP = 225;; +let _ARM64_INS_SADDLP = 226;; +let _ARM64_INS_SADDLV = 227;; +let _ARM64_INS_SADDL2 = 228;; +let _ARM64_INS_SADDL = 229;; +let _ARM64_INS_SADDW2 = 230;; +let _ARM64_INS_SADDW = 231;; +let _ARM64_INS_SBC = 232;; +let _ARM64_INS_SBFM = 233;; +let _ARM64_INS_SCVTF = 234;; +let _ARM64_INS_SDIV = 235;; +let _ARM64_INS_SHA1C = 236;; +let _ARM64_INS_SHA1H = 237;; +let _ARM64_INS_SHA1M = 238;; +let _ARM64_INS_SHA1P = 239;; +let _ARM64_INS_SHA1SU0 = 240;; +let _ARM64_INS_SHA1SU1 = 241;; +let _ARM64_INS_SHA256H2 = 242;; +let _ARM64_INS_SHA256H = 243;; +let _ARM64_INS_SHA256SU0 = 244;; +let _ARM64_INS_SHA256SU1 = 245;; +let _ARM64_INS_SHADD = 246;; +let _ARM64_INS_SHLL2 = 247;; +let _ARM64_INS_SHLL = 248;; +let _ARM64_INS_SHL = 249;; +let _ARM64_INS_SHRN2 = 250;; +let _ARM64_INS_SHRN = 251;; +let _ARM64_INS_SHSUB = 252;; +let _ARM64_INS_SLI = 253;; +let _ARM64_INS_SMADDL = 254;; +let _ARM64_INS_SMAXP = 255;; +let _ARM64_INS_SMAXV = 256;; +let _ARM64_INS_SMAX = 257;; +let _ARM64_INS_SMC = 258;; +let _ARM64_INS_SMINP = 259;; +let _ARM64_INS_SMINV = 260;; +let _ARM64_INS_SMIN = 261;; +let _ARM64_INS_SMLAL2 = 262;; +let _ARM64_INS_SMLAL = 263;; +let _ARM64_INS_SMLSL2 = 264;; +let _ARM64_INS_SMLSL = 265;; +let _ARM64_INS_SMOV = 266;; +let _ARM64_INS_SMSUBL = 267;; +let _ARM64_INS_SMULH = 268;; +let _ARM64_INS_SMULL2 = 269;; +let _ARM64_INS_SMULL = 270;; +let _ARM64_INS_SQABS = 271;; +let _ARM64_INS_SQADD = 272;; +let _ARM64_INS_SQDMLAL = 273;; +let _ARM64_INS_SQDMLAL2 = 274;; +let _ARM64_INS_SQDMLSL = 275;; +let _ARM64_INS_SQDMLSL2 = 276;; +let _ARM64_INS_SQDMULH = 277;; +let _ARM64_INS_SQDMULL = 278;; +let _ARM64_INS_SQDMULL2 = 279;; +let _ARM64_INS_SQNEG = 280;; +let _ARM64_INS_SQRDMULH = 281;; +let _ARM64_INS_SQRSHL = 282;; +let _ARM64_INS_SQRSHRN = 283;; +let _ARM64_INS_SQRSHRN2 = 284;; +let _ARM64_INS_SQRSHRUN = 285;; +let _ARM64_INS_SQRSHRUN2 = 286;; +let _ARM64_INS_SQSHLU = 287;; +let _ARM64_INS_SQSHL = 288;; +let _ARM64_INS_SQSHRN = 289;; +let _ARM64_INS_SQSHRN2 = 290;; +let _ARM64_INS_SQSHRUN = 291;; +let _ARM64_INS_SQSHRUN2 = 292;; +let _ARM64_INS_SQSUB = 293;; +let _ARM64_INS_SQXTN2 = 294;; +let _ARM64_INS_SQXTN = 295;; +let _ARM64_INS_SQXTUN2 = 296;; +let _ARM64_INS_SQXTUN = 297;; +let _ARM64_INS_SRHADD = 298;; +let _ARM64_INS_SRI = 299;; +let _ARM64_INS_SRSHL = 300;; +let _ARM64_INS_SRSHR = 301;; +let _ARM64_INS_SRSRA = 302;; +let _ARM64_INS_SSHLL2 = 303;; +let _ARM64_INS_SSHLL = 304;; +let _ARM64_INS_SSHL = 305;; +let _ARM64_INS_SSHR = 306;; +let _ARM64_INS_SSRA = 307;; +let _ARM64_INS_SSUBL2 = 308;; +let _ARM64_INS_SSUBL = 309;; +let _ARM64_INS_SSUBW2 = 310;; +let _ARM64_INS_SSUBW = 311;; +let _ARM64_INS_ST1 = 312;; +let _ARM64_INS_ST2 = 313;; +let _ARM64_INS_ST3 = 314;; +let _ARM64_INS_ST4 = 315;; +let _ARM64_INS_STLRB = 316;; +let _ARM64_INS_STLRH = 317;; +let _ARM64_INS_STLR = 318;; +let _ARM64_INS_STLXP = 319;; +let _ARM64_INS_STLXRB = 320;; +let _ARM64_INS_STLXRH = 321;; +let _ARM64_INS_STLXR = 322;; +let _ARM64_INS_STNP = 323;; +let _ARM64_INS_STP = 324;; +let _ARM64_INS_STRB = 325;; +let _ARM64_INS_STR = 326;; +let _ARM64_INS_STRH = 327;; +let _ARM64_INS_STTRB = 328;; +let _ARM64_INS_STTRH = 329;; +let _ARM64_INS_STTR = 330;; +let _ARM64_INS_STURB = 331;; +let _ARM64_INS_STUR = 332;; +let _ARM64_INS_STURH = 333;; +let _ARM64_INS_STXP = 334;; +let _ARM64_INS_STXRB = 335;; +let _ARM64_INS_STXRH = 336;; +let _ARM64_INS_STXR = 337;; +let _ARM64_INS_SUBHN = 338;; +let _ARM64_INS_SUBHN2 = 339;; +let _ARM64_INS_SUB = 340;; +let _ARM64_INS_SUQADD = 341;; +let _ARM64_INS_SVC = 342;; +let _ARM64_INS_SYSL = 343;; +let _ARM64_INS_SYS = 344;; +let _ARM64_INS_TBL = 345;; +let _ARM64_INS_TBNZ = 346;; +let _ARM64_INS_TBX = 347;; +let _ARM64_INS_TBZ = 348;; +let _ARM64_INS_TRN1 = 349;; +let _ARM64_INS_TRN2 = 350;; +let _ARM64_INS_UABAL2 = 351;; +let _ARM64_INS_UABAL = 352;; +let _ARM64_INS_UABA = 353;; +let _ARM64_INS_UABDL2 = 354;; +let _ARM64_INS_UABDL = 355;; +let _ARM64_INS_UABD = 356;; +let _ARM64_INS_UADALP = 357;; +let _ARM64_INS_UADDLP = 358;; +let _ARM64_INS_UADDLV = 359;; +let _ARM64_INS_UADDL2 = 360;; +let _ARM64_INS_UADDL = 361;; +let _ARM64_INS_UADDW2 = 362;; +let _ARM64_INS_UADDW = 363;; +let _ARM64_INS_UBFM = 364;; +let _ARM64_INS_UCVTF = 365;; +let _ARM64_INS_UDIV = 366;; +let _ARM64_INS_UHADD = 367;; +let _ARM64_INS_UHSUB = 368;; +let _ARM64_INS_UMADDL = 369;; +let _ARM64_INS_UMAXP = 370;; +let _ARM64_INS_UMAXV = 371;; +let _ARM64_INS_UMAX = 372;; +let _ARM64_INS_UMINP = 373;; +let _ARM64_INS_UMINV = 374;; +let _ARM64_INS_UMIN = 375;; +let _ARM64_INS_UMLAL2 = 376;; +let _ARM64_INS_UMLAL = 377;; +let _ARM64_INS_UMLSL2 = 378;; +let _ARM64_INS_UMLSL = 379;; +let _ARM64_INS_UMOV = 380;; +let _ARM64_INS_UMSUBL = 381;; +let _ARM64_INS_UMULH = 382;; +let _ARM64_INS_UMULL2 = 383;; +let _ARM64_INS_UMULL = 384;; +let _ARM64_INS_UQADD = 385;; +let _ARM64_INS_UQRSHL = 386;; +let _ARM64_INS_UQRSHRN = 387;; +let _ARM64_INS_UQRSHRN2 = 388;; +let _ARM64_INS_UQSHL = 389;; +let _ARM64_INS_UQSHRN = 390;; +let _ARM64_INS_UQSHRN2 = 391;; +let _ARM64_INS_UQSUB = 392;; +let _ARM64_INS_UQXTN2 = 393;; +let _ARM64_INS_UQXTN = 394;; +let _ARM64_INS_URECPE = 395;; +let _ARM64_INS_URHADD = 396;; +let _ARM64_INS_URSHL = 397;; +let _ARM64_INS_URSHR = 398;; +let _ARM64_INS_URSQRTE = 399;; +let _ARM64_INS_URSRA = 400;; +let _ARM64_INS_USHLL2 = 401;; +let _ARM64_INS_USHLL = 402;; +let _ARM64_INS_USHL = 403;; +let _ARM64_INS_USHR = 404;; +let _ARM64_INS_USQADD = 405;; +let _ARM64_INS_USRA = 406;; +let _ARM64_INS_USUBL2 = 407;; +let _ARM64_INS_USUBL = 408;; +let _ARM64_INS_USUBW2 = 409;; +let _ARM64_INS_USUBW = 410;; +let _ARM64_INS_UZP1 = 411;; +let _ARM64_INS_UZP2 = 412;; +let _ARM64_INS_XTN2 = 413;; +let _ARM64_INS_XTN = 414;; +let _ARM64_INS_ZIP1 = 415;; +let _ARM64_INS_ZIP2 = 416;; +let _ARM64_INS_MNEG = 417;; +let _ARM64_INS_UMNEGL = 418;; +let _ARM64_INS_SMNEGL = 419;; +let _ARM64_INS_NOP = 420;; +let _ARM64_INS_YIELD = 421;; +let _ARM64_INS_WFE = 422;; +let _ARM64_INS_WFI = 423;; +let _ARM64_INS_SEV = 424;; +let _ARM64_INS_SEVL = 425;; +let _ARM64_INS_NGC = 426;; +let _ARM64_INS_SBFIZ = 427;; +let _ARM64_INS_UBFIZ = 428;; +let _ARM64_INS_SBFX = 429;; +let _ARM64_INS_UBFX = 430;; +let _ARM64_INS_BFI = 431;; +let _ARM64_INS_BFXIL = 432;; +let _ARM64_INS_CMN = 433;; +let _ARM64_INS_MVN = 434;; +let _ARM64_INS_TST = 435;; +let _ARM64_INS_CSET = 436;; +let _ARM64_INS_CINC = 437;; +let _ARM64_INS_CSETM = 438;; +let _ARM64_INS_CINV = 439;; +let _ARM64_INS_CNEG = 440;; +let _ARM64_INS_SXTB = 441;; +let _ARM64_INS_SXTH = 442;; +let _ARM64_INS_SXTW = 443;; +let _ARM64_INS_CMP = 444;; +let _ARM64_INS_UXTB = 445;; +let _ARM64_INS_UXTH = 446;; +let _ARM64_INS_UXTW = 447;; +let _ARM64_INS_IC = 448;; +let _ARM64_INS_DC = 449;; +let _ARM64_INS_AT = 450;; +let _ARM64_INS_TLBI = 451;; +let _ARM64_INS_NEGS = 452;; +let _ARM64_INS_NGCS = 453;; +let _ARM64_INS_ENDING = 454;; + +let _ARM64_GRP_INVALID = 0;; +let _ARM64_GRP_JUMP = 1;; +let _ARM64_GRP_CALL = 2;; +let _ARM64_GRP_RET = 3;; +let _ARM64_GRP_INT = 4;; +let _ARM64_GRP_PRIVILEGE = 6;; +let _ARM64_GRP_BRANCH_RELATIVE = 7;; +let _ARM64_GRP_CRYPTO = 128;; +let _ARM64_GRP_FPARMV8 = 129;; +let _ARM64_GRP_NEON = 130;; +let _ARM64_GRP_CRC = 131;; +let _ARM64_GRP_ENDING = 132;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/arm_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/arm_const.ml new file mode 100644 index 0000000..acc3c8e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/arm_const.ml @@ -0,0 +1,775 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.ml] *) + +let _ARM_SFT_INVALID = 0;; +let _ARM_SFT_ASR = 1;; +let _ARM_SFT_LSL = 2;; +let _ARM_SFT_LSR = 3;; +let _ARM_SFT_ROR = 4;; +let _ARM_SFT_RRX = 5;; +let _ARM_SFT_ASR_REG = 6;; +let _ARM_SFT_LSL_REG = 7;; +let _ARM_SFT_LSR_REG = 8;; +let _ARM_SFT_ROR_REG = 9;; +let _ARM_SFT_RRX_REG = 10;; + +let _ARM_CC_INVALID = 0;; +let _ARM_CC_EQ = 1;; +let _ARM_CC_NE = 2;; +let _ARM_CC_HS = 3;; +let _ARM_CC_LO = 4;; +let _ARM_CC_MI = 5;; +let _ARM_CC_PL = 6;; +let _ARM_CC_VS = 7;; +let _ARM_CC_VC = 8;; +let _ARM_CC_HI = 9;; +let _ARM_CC_LS = 10;; +let _ARM_CC_GE = 11;; +let _ARM_CC_LT = 12;; +let _ARM_CC_GT = 13;; +let _ARM_CC_LE = 14;; +let _ARM_CC_AL = 15;; + +let _ARM_SYSREG_INVALID = 0;; +let _ARM_SYSREG_SPSR_C = 1;; +let _ARM_SYSREG_SPSR_X = 2;; +let _ARM_SYSREG_SPSR_S = 4;; +let _ARM_SYSREG_SPSR_F = 8;; +let _ARM_SYSREG_CPSR_C = 16;; +let _ARM_SYSREG_CPSR_X = 32;; +let _ARM_SYSREG_CPSR_S = 64;; +let _ARM_SYSREG_CPSR_F = 128;; +let _ARM_SYSREG_APSR = 256;; +let _ARM_SYSREG_APSR_G = 257;; +let _ARM_SYSREG_APSR_NZCVQ = 258;; +let _ARM_SYSREG_APSR_NZCVQG = 259;; +let _ARM_SYSREG_IAPSR = 260;; +let _ARM_SYSREG_IAPSR_G = 261;; +let _ARM_SYSREG_IAPSR_NZCVQG = 262;; +let _ARM_SYSREG_IAPSR_NZCVQ = 263;; +let _ARM_SYSREG_EAPSR = 264;; +let _ARM_SYSREG_EAPSR_G = 265;; +let _ARM_SYSREG_EAPSR_NZCVQG = 266;; +let _ARM_SYSREG_EAPSR_NZCVQ = 267;; +let _ARM_SYSREG_XPSR = 268;; +let _ARM_SYSREG_XPSR_G = 269;; +let _ARM_SYSREG_XPSR_NZCVQG = 270;; +let _ARM_SYSREG_XPSR_NZCVQ = 271;; +let _ARM_SYSREG_IPSR = 272;; +let _ARM_SYSREG_EPSR = 273;; +let _ARM_SYSREG_IEPSR = 274;; +let _ARM_SYSREG_MSP = 275;; +let _ARM_SYSREG_PSP = 276;; +let _ARM_SYSREG_PRIMASK = 277;; +let _ARM_SYSREG_BASEPRI = 278;; +let _ARM_SYSREG_BASEPRI_MAX = 279;; +let _ARM_SYSREG_FAULTMASK = 280;; +let _ARM_SYSREG_CONTROL = 281;; +let _ARM_SYSREG_R8_USR = 282;; +let _ARM_SYSREG_R9_USR = 283;; +let _ARM_SYSREG_R10_USR = 284;; +let _ARM_SYSREG_R11_USR = 285;; +let _ARM_SYSREG_R12_USR = 286;; +let _ARM_SYSREG_SP_USR = 287;; +let _ARM_SYSREG_LR_USR = 288;; +let _ARM_SYSREG_R8_FIQ = 289;; +let _ARM_SYSREG_R9_FIQ = 290;; +let _ARM_SYSREG_R10_FIQ = 291;; +let _ARM_SYSREG_R11_FIQ = 292;; +let _ARM_SYSREG_R12_FIQ = 293;; +let _ARM_SYSREG_SP_FIQ = 294;; +let _ARM_SYSREG_LR_FIQ = 295;; +let _ARM_SYSREG_LR_IRQ = 296;; +let _ARM_SYSREG_SP_IRQ = 297;; +let _ARM_SYSREG_LR_SVC = 298;; +let _ARM_SYSREG_SP_SVC = 299;; +let _ARM_SYSREG_LR_ABT = 300;; +let _ARM_SYSREG_SP_ABT = 301;; +let _ARM_SYSREG_LR_UND = 302;; +let _ARM_SYSREG_SP_UND = 303;; +let _ARM_SYSREG_LR_MON = 304;; +let _ARM_SYSREG_SP_MON = 305;; +let _ARM_SYSREG_ELR_HYP = 306;; +let _ARM_SYSREG_SP_HYP = 307;; +let _ARM_SYSREG_SPSR_FIQ = 308;; +let _ARM_SYSREG_SPSR_IRQ = 309;; +let _ARM_SYSREG_SPSR_SVC = 310;; +let _ARM_SYSREG_SPSR_ABT = 311;; +let _ARM_SYSREG_SPSR_UND = 312;; +let _ARM_SYSREG_SPSR_MON = 313;; +let _ARM_SYSREG_SPSR_HYP = 314;; + +let _ARM_MB_INVALID = 0;; +let _ARM_MB_RESERVED_0 = 1;; +let _ARM_MB_OSHLD = 2;; +let _ARM_MB_OSHST = 3;; +let _ARM_MB_OSH = 4;; +let _ARM_MB_RESERVED_4 = 5;; +let _ARM_MB_NSHLD = 6;; +let _ARM_MB_NSHST = 7;; +let _ARM_MB_NSH = 8;; +let _ARM_MB_RESERVED_8 = 9;; +let _ARM_MB_ISHLD = 10;; +let _ARM_MB_ISHST = 11;; +let _ARM_MB_ISH = 12;; +let _ARM_MB_RESERVED_12 = 13;; +let _ARM_MB_LD = 14;; +let _ARM_MB_ST = 15;; +let _ARM_MB_SY = 16;; + +let _ARM_OP_INVALID = 0;; +let _ARM_OP_REG = 1;; +let _ARM_OP_IMM = 2;; +let _ARM_OP_MEM = 3;; +let _ARM_OP_FP = 4;; +let _ARM_OP_CIMM = 64;; +let _ARM_OP_PIMM = 65;; +let _ARM_OP_SETEND = 66;; +let _ARM_OP_SYSREG = 67;; + +let _ARM_SETEND_INVALID = 0;; +let _ARM_SETEND_BE = 1;; +let _ARM_SETEND_LE = 2;; + +let _ARM_CPSMODE_INVALID = 0;; +let _ARM_CPSMODE_IE = 2;; +let _ARM_CPSMODE_ID = 3;; + +let _ARM_CPSFLAG_INVALID = 0;; +let _ARM_CPSFLAG_F = 1;; +let _ARM_CPSFLAG_I = 2;; +let _ARM_CPSFLAG_A = 4;; +let _ARM_CPSFLAG_NONE = 16;; + +let _ARM_VECTORDATA_INVALID = 0;; +let _ARM_VECTORDATA_I8 = 1;; +let _ARM_VECTORDATA_I16 = 2;; +let _ARM_VECTORDATA_I32 = 3;; +let _ARM_VECTORDATA_I64 = 4;; +let _ARM_VECTORDATA_S8 = 5;; +let _ARM_VECTORDATA_S16 = 6;; +let _ARM_VECTORDATA_S32 = 7;; +let _ARM_VECTORDATA_S64 = 8;; +let _ARM_VECTORDATA_U8 = 9;; +let _ARM_VECTORDATA_U16 = 10;; +let _ARM_VECTORDATA_U32 = 11;; +let _ARM_VECTORDATA_U64 = 12;; +let _ARM_VECTORDATA_P8 = 13;; +let _ARM_VECTORDATA_F32 = 14;; +let _ARM_VECTORDATA_F64 = 15;; +let _ARM_VECTORDATA_F16F64 = 16;; +let _ARM_VECTORDATA_F64F16 = 17;; +let _ARM_VECTORDATA_F32F16 = 18;; +let _ARM_VECTORDATA_F16F32 = 19;; +let _ARM_VECTORDATA_F64F32 = 20;; +let _ARM_VECTORDATA_F32F64 = 21;; +let _ARM_VECTORDATA_S32F32 = 22;; +let _ARM_VECTORDATA_U32F32 = 23;; +let _ARM_VECTORDATA_F32S32 = 24;; +let _ARM_VECTORDATA_F32U32 = 25;; +let _ARM_VECTORDATA_F64S16 = 26;; +let _ARM_VECTORDATA_F32S16 = 27;; +let _ARM_VECTORDATA_F64S32 = 28;; +let _ARM_VECTORDATA_S16F64 = 29;; +let _ARM_VECTORDATA_S16F32 = 30;; +let _ARM_VECTORDATA_S32F64 = 31;; +let _ARM_VECTORDATA_U16F64 = 32;; +let _ARM_VECTORDATA_U16F32 = 33;; +let _ARM_VECTORDATA_U32F64 = 34;; +let _ARM_VECTORDATA_F64U16 = 35;; +let _ARM_VECTORDATA_F32U16 = 36;; +let _ARM_VECTORDATA_F64U32 = 37;; + +let _ARM_REG_INVALID = 0;; +let _ARM_REG_APSR = 1;; +let _ARM_REG_APSR_NZCV = 2;; +let _ARM_REG_CPSR = 3;; +let _ARM_REG_FPEXC = 4;; +let _ARM_REG_FPINST = 5;; +let _ARM_REG_FPSCR = 6;; +let _ARM_REG_FPSCR_NZCV = 7;; +let _ARM_REG_FPSID = 8;; +let _ARM_REG_ITSTATE = 9;; +let _ARM_REG_LR = 10;; +let _ARM_REG_PC = 11;; +let _ARM_REG_SP = 12;; +let _ARM_REG_SPSR = 13;; +let _ARM_REG_D0 = 14;; +let _ARM_REG_D1 = 15;; +let _ARM_REG_D2 = 16;; +let _ARM_REG_D3 = 17;; +let _ARM_REG_D4 = 18;; +let _ARM_REG_D5 = 19;; +let _ARM_REG_D6 = 20;; +let _ARM_REG_D7 = 21;; +let _ARM_REG_D8 = 22;; +let _ARM_REG_D9 = 23;; +let _ARM_REG_D10 = 24;; +let _ARM_REG_D11 = 25;; +let _ARM_REG_D12 = 26;; +let _ARM_REG_D13 = 27;; +let _ARM_REG_D14 = 28;; +let _ARM_REG_D15 = 29;; +let _ARM_REG_D16 = 30;; +let _ARM_REG_D17 = 31;; +let _ARM_REG_D18 = 32;; +let _ARM_REG_D19 = 33;; +let _ARM_REG_D20 = 34;; +let _ARM_REG_D21 = 35;; +let _ARM_REG_D22 = 36;; +let _ARM_REG_D23 = 37;; +let _ARM_REG_D24 = 38;; +let _ARM_REG_D25 = 39;; +let _ARM_REG_D26 = 40;; +let _ARM_REG_D27 = 41;; +let _ARM_REG_D28 = 42;; +let _ARM_REG_D29 = 43;; +let _ARM_REG_D30 = 44;; +let _ARM_REG_D31 = 45;; +let _ARM_REG_FPINST2 = 46;; +let _ARM_REG_MVFR0 = 47;; +let _ARM_REG_MVFR1 = 48;; +let _ARM_REG_MVFR2 = 49;; +let _ARM_REG_Q0 = 50;; +let _ARM_REG_Q1 = 51;; +let _ARM_REG_Q2 = 52;; +let _ARM_REG_Q3 = 53;; +let _ARM_REG_Q4 = 54;; +let _ARM_REG_Q5 = 55;; +let _ARM_REG_Q6 = 56;; +let _ARM_REG_Q7 = 57;; +let _ARM_REG_Q8 = 58;; +let _ARM_REG_Q9 = 59;; +let _ARM_REG_Q10 = 60;; +let _ARM_REG_Q11 = 61;; +let _ARM_REG_Q12 = 62;; +let _ARM_REG_Q13 = 63;; +let _ARM_REG_Q14 = 64;; +let _ARM_REG_Q15 = 65;; +let _ARM_REG_R0 = 66;; +let _ARM_REG_R1 = 67;; +let _ARM_REG_R2 = 68;; +let _ARM_REG_R3 = 69;; +let _ARM_REG_R4 = 70;; +let _ARM_REG_R5 = 71;; +let _ARM_REG_R6 = 72;; +let _ARM_REG_R7 = 73;; +let _ARM_REG_R8 = 74;; +let _ARM_REG_R9 = 75;; +let _ARM_REG_R10 = 76;; +let _ARM_REG_R11 = 77;; +let _ARM_REG_R12 = 78;; +let _ARM_REG_S0 = 79;; +let _ARM_REG_S1 = 80;; +let _ARM_REG_S2 = 81;; +let _ARM_REG_S3 = 82;; +let _ARM_REG_S4 = 83;; +let _ARM_REG_S5 = 84;; +let _ARM_REG_S6 = 85;; +let _ARM_REG_S7 = 86;; +let _ARM_REG_S8 = 87;; +let _ARM_REG_S9 = 88;; +let _ARM_REG_S10 = 89;; +let _ARM_REG_S11 = 90;; +let _ARM_REG_S12 = 91;; +let _ARM_REG_S13 = 92;; +let _ARM_REG_S14 = 93;; +let _ARM_REG_S15 = 94;; +let _ARM_REG_S16 = 95;; +let _ARM_REG_S17 = 96;; +let _ARM_REG_S18 = 97;; +let _ARM_REG_S19 = 98;; +let _ARM_REG_S20 = 99;; +let _ARM_REG_S21 = 100;; +let _ARM_REG_S22 = 101;; +let _ARM_REG_S23 = 102;; +let _ARM_REG_S24 = 103;; +let _ARM_REG_S25 = 104;; +let _ARM_REG_S26 = 105;; +let _ARM_REG_S27 = 106;; +let _ARM_REG_S28 = 107;; +let _ARM_REG_S29 = 108;; +let _ARM_REG_S30 = 109;; +let _ARM_REG_S31 = 110;; +let _ARM_REG_ENDING = 111;; +let _ARM_REG_R13 = _ARM_REG_SP;; +let _ARM_REG_R14 = _ARM_REG_LR;; +let _ARM_REG_R15 = _ARM_REG_PC;; +let _ARM_REG_SB = _ARM_REG_R9;; +let _ARM_REG_SL = _ARM_REG_R10;; +let _ARM_REG_FP = _ARM_REG_R11;; +let _ARM_REG_IP = _ARM_REG_R12;; + +let _ARM_INS_INVALID = 0;; +let _ARM_INS_ADC = 1;; +let _ARM_INS_ADD = 2;; +let _ARM_INS_ADR = 3;; +let _ARM_INS_AESD = 4;; +let _ARM_INS_AESE = 5;; +let _ARM_INS_AESIMC = 6;; +let _ARM_INS_AESMC = 7;; +let _ARM_INS_AND = 8;; +let _ARM_INS_BFC = 9;; +let _ARM_INS_BFI = 10;; +let _ARM_INS_BIC = 11;; +let _ARM_INS_BKPT = 12;; +let _ARM_INS_BL = 13;; +let _ARM_INS_BLX = 14;; +let _ARM_INS_BX = 15;; +let _ARM_INS_BXJ = 16;; +let _ARM_INS_B = 17;; +let _ARM_INS_CDP = 18;; +let _ARM_INS_CDP2 = 19;; +let _ARM_INS_CLREX = 20;; +let _ARM_INS_CLZ = 21;; +let _ARM_INS_CMN = 22;; +let _ARM_INS_CMP = 23;; +let _ARM_INS_CPS = 24;; +let _ARM_INS_CRC32B = 25;; +let _ARM_INS_CRC32CB = 26;; +let _ARM_INS_CRC32CH = 27;; +let _ARM_INS_CRC32CW = 28;; +let _ARM_INS_CRC32H = 29;; +let _ARM_INS_CRC32W = 30;; +let _ARM_INS_DBG = 31;; +let _ARM_INS_DMB = 32;; +let _ARM_INS_DSB = 33;; +let _ARM_INS_EOR = 34;; +let _ARM_INS_ERET = 35;; +let _ARM_INS_VMOV = 36;; +let _ARM_INS_FLDMDBX = 37;; +let _ARM_INS_FLDMIAX = 38;; +let _ARM_INS_VMRS = 39;; +let _ARM_INS_FSTMDBX = 40;; +let _ARM_INS_FSTMIAX = 41;; +let _ARM_INS_HINT = 42;; +let _ARM_INS_HLT = 43;; +let _ARM_INS_HVC = 44;; +let _ARM_INS_ISB = 45;; +let _ARM_INS_LDA = 46;; +let _ARM_INS_LDAB = 47;; +let _ARM_INS_LDAEX = 48;; +let _ARM_INS_LDAEXB = 49;; +let _ARM_INS_LDAEXD = 50;; +let _ARM_INS_LDAEXH = 51;; +let _ARM_INS_LDAH = 52;; +let _ARM_INS_LDC2L = 53;; +let _ARM_INS_LDC2 = 54;; +let _ARM_INS_LDCL = 55;; +let _ARM_INS_LDC = 56;; +let _ARM_INS_LDMDA = 57;; +let _ARM_INS_LDMDB = 58;; +let _ARM_INS_LDM = 59;; +let _ARM_INS_LDMIB = 60;; +let _ARM_INS_LDRBT = 61;; +let _ARM_INS_LDRB = 62;; +let _ARM_INS_LDRD = 63;; +let _ARM_INS_LDREX = 64;; +let _ARM_INS_LDREXB = 65;; +let _ARM_INS_LDREXD = 66;; +let _ARM_INS_LDREXH = 67;; +let _ARM_INS_LDRH = 68;; +let _ARM_INS_LDRHT = 69;; +let _ARM_INS_LDRSB = 70;; +let _ARM_INS_LDRSBT = 71;; +let _ARM_INS_LDRSH = 72;; +let _ARM_INS_LDRSHT = 73;; +let _ARM_INS_LDRT = 74;; +let _ARM_INS_LDR = 75;; +let _ARM_INS_MCR = 76;; +let _ARM_INS_MCR2 = 77;; +let _ARM_INS_MCRR = 78;; +let _ARM_INS_MCRR2 = 79;; +let _ARM_INS_MLA = 80;; +let _ARM_INS_MLS = 81;; +let _ARM_INS_MOV = 82;; +let _ARM_INS_MOVT = 83;; +let _ARM_INS_MOVW = 84;; +let _ARM_INS_MRC = 85;; +let _ARM_INS_MRC2 = 86;; +let _ARM_INS_MRRC = 87;; +let _ARM_INS_MRRC2 = 88;; +let _ARM_INS_MRS = 89;; +let _ARM_INS_MSR = 90;; +let _ARM_INS_MUL = 91;; +let _ARM_INS_MVN = 92;; +let _ARM_INS_ORR = 93;; +let _ARM_INS_PKHBT = 94;; +let _ARM_INS_PKHTB = 95;; +let _ARM_INS_PLDW = 96;; +let _ARM_INS_PLD = 97;; +let _ARM_INS_PLI = 98;; +let _ARM_INS_QADD = 99;; +let _ARM_INS_QADD16 = 100;; +let _ARM_INS_QADD8 = 101;; +let _ARM_INS_QASX = 102;; +let _ARM_INS_QDADD = 103;; +let _ARM_INS_QDSUB = 104;; +let _ARM_INS_QSAX = 105;; +let _ARM_INS_QSUB = 106;; +let _ARM_INS_QSUB16 = 107;; +let _ARM_INS_QSUB8 = 108;; +let _ARM_INS_RBIT = 109;; +let _ARM_INS_REV = 110;; +let _ARM_INS_REV16 = 111;; +let _ARM_INS_REVSH = 112;; +let _ARM_INS_RFEDA = 113;; +let _ARM_INS_RFEDB = 114;; +let _ARM_INS_RFEIA = 115;; +let _ARM_INS_RFEIB = 116;; +let _ARM_INS_RSB = 117;; +let _ARM_INS_RSC = 118;; +let _ARM_INS_SADD16 = 119;; +let _ARM_INS_SADD8 = 120;; +let _ARM_INS_SASX = 121;; +let _ARM_INS_SBC = 122;; +let _ARM_INS_SBFX = 123;; +let _ARM_INS_SDIV = 124;; +let _ARM_INS_SEL = 125;; +let _ARM_INS_SETEND = 126;; +let _ARM_INS_SHA1C = 127;; +let _ARM_INS_SHA1H = 128;; +let _ARM_INS_SHA1M = 129;; +let _ARM_INS_SHA1P = 130;; +let _ARM_INS_SHA1SU0 = 131;; +let _ARM_INS_SHA1SU1 = 132;; +let _ARM_INS_SHA256H = 133;; +let _ARM_INS_SHA256H2 = 134;; +let _ARM_INS_SHA256SU0 = 135;; +let _ARM_INS_SHA256SU1 = 136;; +let _ARM_INS_SHADD16 = 137;; +let _ARM_INS_SHADD8 = 138;; +let _ARM_INS_SHASX = 139;; +let _ARM_INS_SHSAX = 140;; +let _ARM_INS_SHSUB16 = 141;; +let _ARM_INS_SHSUB8 = 142;; +let _ARM_INS_SMC = 143;; +let _ARM_INS_SMLABB = 144;; +let _ARM_INS_SMLABT = 145;; +let _ARM_INS_SMLAD = 146;; +let _ARM_INS_SMLADX = 147;; +let _ARM_INS_SMLAL = 148;; +let _ARM_INS_SMLALBB = 149;; +let _ARM_INS_SMLALBT = 150;; +let _ARM_INS_SMLALD = 151;; +let _ARM_INS_SMLALDX = 152;; +let _ARM_INS_SMLALTB = 153;; +let _ARM_INS_SMLALTT = 154;; +let _ARM_INS_SMLATB = 155;; +let _ARM_INS_SMLATT = 156;; +let _ARM_INS_SMLAWB = 157;; +let _ARM_INS_SMLAWT = 158;; +let _ARM_INS_SMLSD = 159;; +let _ARM_INS_SMLSDX = 160;; +let _ARM_INS_SMLSLD = 161;; +let _ARM_INS_SMLSLDX = 162;; +let _ARM_INS_SMMLA = 163;; +let _ARM_INS_SMMLAR = 164;; +let _ARM_INS_SMMLS = 165;; +let _ARM_INS_SMMLSR = 166;; +let _ARM_INS_SMMUL = 167;; +let _ARM_INS_SMMULR = 168;; +let _ARM_INS_SMUAD = 169;; +let _ARM_INS_SMUADX = 170;; +let _ARM_INS_SMULBB = 171;; +let _ARM_INS_SMULBT = 172;; +let _ARM_INS_SMULL = 173;; +let _ARM_INS_SMULTB = 174;; +let _ARM_INS_SMULTT = 175;; +let _ARM_INS_SMULWB = 176;; +let _ARM_INS_SMULWT = 177;; +let _ARM_INS_SMUSD = 178;; +let _ARM_INS_SMUSDX = 179;; +let _ARM_INS_SRSDA = 180;; +let _ARM_INS_SRSDB = 181;; +let _ARM_INS_SRSIA = 182;; +let _ARM_INS_SRSIB = 183;; +let _ARM_INS_SSAT = 184;; +let _ARM_INS_SSAT16 = 185;; +let _ARM_INS_SSAX = 186;; +let _ARM_INS_SSUB16 = 187;; +let _ARM_INS_SSUB8 = 188;; +let _ARM_INS_STC2L = 189;; +let _ARM_INS_STC2 = 190;; +let _ARM_INS_STCL = 191;; +let _ARM_INS_STC = 192;; +let _ARM_INS_STL = 193;; +let _ARM_INS_STLB = 194;; +let _ARM_INS_STLEX = 195;; +let _ARM_INS_STLEXB = 196;; +let _ARM_INS_STLEXD = 197;; +let _ARM_INS_STLEXH = 198;; +let _ARM_INS_STLH = 199;; +let _ARM_INS_STMDA = 200;; +let _ARM_INS_STMDB = 201;; +let _ARM_INS_STM = 202;; +let _ARM_INS_STMIB = 203;; +let _ARM_INS_STRBT = 204;; +let _ARM_INS_STRB = 205;; +let _ARM_INS_STRD = 206;; +let _ARM_INS_STREX = 207;; +let _ARM_INS_STREXB = 208;; +let _ARM_INS_STREXD = 209;; +let _ARM_INS_STREXH = 210;; +let _ARM_INS_STRH = 211;; +let _ARM_INS_STRHT = 212;; +let _ARM_INS_STRT = 213;; +let _ARM_INS_STR = 214;; +let _ARM_INS_SUB = 215;; +let _ARM_INS_SVC = 216;; +let _ARM_INS_SWP = 217;; +let _ARM_INS_SWPB = 218;; +let _ARM_INS_SXTAB = 219;; +let _ARM_INS_SXTAB16 = 220;; +let _ARM_INS_SXTAH = 221;; +let _ARM_INS_SXTB = 222;; +let _ARM_INS_SXTB16 = 223;; +let _ARM_INS_SXTH = 224;; +let _ARM_INS_TEQ = 225;; +let _ARM_INS_TRAP = 226;; +let _ARM_INS_TST = 227;; +let _ARM_INS_UADD16 = 228;; +let _ARM_INS_UADD8 = 229;; +let _ARM_INS_UASX = 230;; +let _ARM_INS_UBFX = 231;; +let _ARM_INS_UDF = 232;; +let _ARM_INS_UDIV = 233;; +let _ARM_INS_UHADD16 = 234;; +let _ARM_INS_UHADD8 = 235;; +let _ARM_INS_UHASX = 236;; +let _ARM_INS_UHSAX = 237;; +let _ARM_INS_UHSUB16 = 238;; +let _ARM_INS_UHSUB8 = 239;; +let _ARM_INS_UMAAL = 240;; +let _ARM_INS_UMLAL = 241;; +let _ARM_INS_UMULL = 242;; +let _ARM_INS_UQADD16 = 243;; +let _ARM_INS_UQADD8 = 244;; +let _ARM_INS_UQASX = 245;; +let _ARM_INS_UQSAX = 246;; +let _ARM_INS_UQSUB16 = 247;; +let _ARM_INS_UQSUB8 = 248;; +let _ARM_INS_USAD8 = 249;; +let _ARM_INS_USADA8 = 250;; +let _ARM_INS_USAT = 251;; +let _ARM_INS_USAT16 = 252;; +let _ARM_INS_USAX = 253;; +let _ARM_INS_USUB16 = 254;; +let _ARM_INS_USUB8 = 255;; +let _ARM_INS_UXTAB = 256;; +let _ARM_INS_UXTAB16 = 257;; +let _ARM_INS_UXTAH = 258;; +let _ARM_INS_UXTB = 259;; +let _ARM_INS_UXTB16 = 260;; +let _ARM_INS_UXTH = 261;; +let _ARM_INS_VABAL = 262;; +let _ARM_INS_VABA = 263;; +let _ARM_INS_VABDL = 264;; +let _ARM_INS_VABD = 265;; +let _ARM_INS_VABS = 266;; +let _ARM_INS_VACGE = 267;; +let _ARM_INS_VACGT = 268;; +let _ARM_INS_VADD = 269;; +let _ARM_INS_VADDHN = 270;; +let _ARM_INS_VADDL = 271;; +let _ARM_INS_VADDW = 272;; +let _ARM_INS_VAND = 273;; +let _ARM_INS_VBIC = 274;; +let _ARM_INS_VBIF = 275;; +let _ARM_INS_VBIT = 276;; +let _ARM_INS_VBSL = 277;; +let _ARM_INS_VCEQ = 278;; +let _ARM_INS_VCGE = 279;; +let _ARM_INS_VCGT = 280;; +let _ARM_INS_VCLE = 281;; +let _ARM_INS_VCLS = 282;; +let _ARM_INS_VCLT = 283;; +let _ARM_INS_VCLZ = 284;; +let _ARM_INS_VCMP = 285;; +let _ARM_INS_VCMPE = 286;; +let _ARM_INS_VCNT = 287;; +let _ARM_INS_VCVTA = 288;; +let _ARM_INS_VCVTB = 289;; +let _ARM_INS_VCVT = 290;; +let _ARM_INS_VCVTM = 291;; +let _ARM_INS_VCVTN = 292;; +let _ARM_INS_VCVTP = 293;; +let _ARM_INS_VCVTT = 294;; +let _ARM_INS_VDIV = 295;; +let _ARM_INS_VDUP = 296;; +let _ARM_INS_VEOR = 297;; +let _ARM_INS_VEXT = 298;; +let _ARM_INS_VFMA = 299;; +let _ARM_INS_VFMS = 300;; +let _ARM_INS_VFNMA = 301;; +let _ARM_INS_VFNMS = 302;; +let _ARM_INS_VHADD = 303;; +let _ARM_INS_VHSUB = 304;; +let _ARM_INS_VLD1 = 305;; +let _ARM_INS_VLD2 = 306;; +let _ARM_INS_VLD3 = 307;; +let _ARM_INS_VLD4 = 308;; +let _ARM_INS_VLDMDB = 309;; +let _ARM_INS_VLDMIA = 310;; +let _ARM_INS_VLDR = 311;; +let _ARM_INS_VMAXNM = 312;; +let _ARM_INS_VMAX = 313;; +let _ARM_INS_VMINNM = 314;; +let _ARM_INS_VMIN = 315;; +let _ARM_INS_VMLA = 316;; +let _ARM_INS_VMLAL = 317;; +let _ARM_INS_VMLS = 318;; +let _ARM_INS_VMLSL = 319;; +let _ARM_INS_VMOVL = 320;; +let _ARM_INS_VMOVN = 321;; +let _ARM_INS_VMSR = 322;; +let _ARM_INS_VMUL = 323;; +let _ARM_INS_VMULL = 324;; +let _ARM_INS_VMVN = 325;; +let _ARM_INS_VNEG = 326;; +let _ARM_INS_VNMLA = 327;; +let _ARM_INS_VNMLS = 328;; +let _ARM_INS_VNMUL = 329;; +let _ARM_INS_VORN = 330;; +let _ARM_INS_VORR = 331;; +let _ARM_INS_VPADAL = 332;; +let _ARM_INS_VPADDL = 333;; +let _ARM_INS_VPADD = 334;; +let _ARM_INS_VPMAX = 335;; +let _ARM_INS_VPMIN = 336;; +let _ARM_INS_VQABS = 337;; +let _ARM_INS_VQADD = 338;; +let _ARM_INS_VQDMLAL = 339;; +let _ARM_INS_VQDMLSL = 340;; +let _ARM_INS_VQDMULH = 341;; +let _ARM_INS_VQDMULL = 342;; +let _ARM_INS_VQMOVUN = 343;; +let _ARM_INS_VQMOVN = 344;; +let _ARM_INS_VQNEG = 345;; +let _ARM_INS_VQRDMULH = 346;; +let _ARM_INS_VQRSHL = 347;; +let _ARM_INS_VQRSHRN = 348;; +let _ARM_INS_VQRSHRUN = 349;; +let _ARM_INS_VQSHL = 350;; +let _ARM_INS_VQSHLU = 351;; +let _ARM_INS_VQSHRN = 352;; +let _ARM_INS_VQSHRUN = 353;; +let _ARM_INS_VQSUB = 354;; +let _ARM_INS_VRADDHN = 355;; +let _ARM_INS_VRECPE = 356;; +let _ARM_INS_VRECPS = 357;; +let _ARM_INS_VREV16 = 358;; +let _ARM_INS_VREV32 = 359;; +let _ARM_INS_VREV64 = 360;; +let _ARM_INS_VRHADD = 361;; +let _ARM_INS_VRINTA = 362;; +let _ARM_INS_VRINTM = 363;; +let _ARM_INS_VRINTN = 364;; +let _ARM_INS_VRINTP = 365;; +let _ARM_INS_VRINTR = 366;; +let _ARM_INS_VRINTX = 367;; +let _ARM_INS_VRINTZ = 368;; +let _ARM_INS_VRSHL = 369;; +let _ARM_INS_VRSHRN = 370;; +let _ARM_INS_VRSHR = 371;; +let _ARM_INS_VRSQRTE = 372;; +let _ARM_INS_VRSQRTS = 373;; +let _ARM_INS_VRSRA = 374;; +let _ARM_INS_VRSUBHN = 375;; +let _ARM_INS_VSELEQ = 376;; +let _ARM_INS_VSELGE = 377;; +let _ARM_INS_VSELGT = 378;; +let _ARM_INS_VSELVS = 379;; +let _ARM_INS_VSHLL = 380;; +let _ARM_INS_VSHL = 381;; +let _ARM_INS_VSHRN = 382;; +let _ARM_INS_VSHR = 383;; +let _ARM_INS_VSLI = 384;; +let _ARM_INS_VSQRT = 385;; +let _ARM_INS_VSRA = 386;; +let _ARM_INS_VSRI = 387;; +let _ARM_INS_VST1 = 388;; +let _ARM_INS_VST2 = 389;; +let _ARM_INS_VST3 = 390;; +let _ARM_INS_VST4 = 391;; +let _ARM_INS_VSTMDB = 392;; +let _ARM_INS_VSTMIA = 393;; +let _ARM_INS_VSTR = 394;; +let _ARM_INS_VSUB = 395;; +let _ARM_INS_VSUBHN = 396;; +let _ARM_INS_VSUBL = 397;; +let _ARM_INS_VSUBW = 398;; +let _ARM_INS_VSWP = 399;; +let _ARM_INS_VTBL = 400;; +let _ARM_INS_VTBX = 401;; +let _ARM_INS_VCVTR = 402;; +let _ARM_INS_VTRN = 403;; +let _ARM_INS_VTST = 404;; +let _ARM_INS_VUZP = 405;; +let _ARM_INS_VZIP = 406;; +let _ARM_INS_ADDW = 407;; +let _ARM_INS_ASR = 408;; +let _ARM_INS_DCPS1 = 409;; +let _ARM_INS_DCPS2 = 410;; +let _ARM_INS_DCPS3 = 411;; +let _ARM_INS_IT = 412;; +let _ARM_INS_LSL = 413;; +let _ARM_INS_LSR = 414;; +let _ARM_INS_ORN = 415;; +let _ARM_INS_ROR = 416;; +let _ARM_INS_RRX = 417;; +let _ARM_INS_SUBW = 418;; +let _ARM_INS_TBB = 419;; +let _ARM_INS_TBH = 420;; +let _ARM_INS_CBNZ = 421;; +let _ARM_INS_CBZ = 422;; +let _ARM_INS_POP = 423;; +let _ARM_INS_PUSH = 424;; +let _ARM_INS_NOP = 425;; +let _ARM_INS_YIELD = 426;; +let _ARM_INS_WFE = 427;; +let _ARM_INS_WFI = 428;; +let _ARM_INS_SEV = 429;; +let _ARM_INS_SEVL = 430;; +let _ARM_INS_VPUSH = 431;; +let _ARM_INS_VPOP = 432;; +let _ARM_INS_ENDING = 433;; + +let _ARM_GRP_INVALID = 0;; +let _ARM_GRP_JUMP = 1;; +let _ARM_GRP_CALL = 2;; +let _ARM_GRP_INT = 4;; +let _ARM_GRP_PRIVILEGE = 6;; +let _ARM_GRP_BRANCH_RELATIVE = 7;; +let _ARM_GRP_CRYPTO = 128;; +let _ARM_GRP_DATABARRIER = 129;; +let _ARM_GRP_DIVIDE = 130;; +let _ARM_GRP_FPARMV8 = 131;; +let _ARM_GRP_MULTPRO = 132;; +let _ARM_GRP_NEON = 133;; +let _ARM_GRP_T2EXTRACTPACK = 134;; +let _ARM_GRP_THUMB2DSP = 135;; +let _ARM_GRP_TRUSTZONE = 136;; +let _ARM_GRP_V4T = 137;; +let _ARM_GRP_V5T = 138;; +let _ARM_GRP_V5TE = 139;; +let _ARM_GRP_V6 = 140;; +let _ARM_GRP_V6T2 = 141;; +let _ARM_GRP_V7 = 142;; +let _ARM_GRP_V8 = 143;; +let _ARM_GRP_VFP2 = 144;; +let _ARM_GRP_VFP3 = 145;; +let _ARM_GRP_VFP4 = 146;; +let _ARM_GRP_ARM = 147;; +let _ARM_GRP_MCLASS = 148;; +let _ARM_GRP_NOTMCLASS = 149;; +let _ARM_GRP_THUMB = 150;; +let _ARM_GRP_THUMB1ONLY = 151;; +let _ARM_GRP_THUMB2 = 152;; +let _ARM_GRP_PREV8 = 153;; +let _ARM_GRP_FPVMLX = 154;; +let _ARM_GRP_MULOPS = 155;; +let _ARM_GRP_CRC = 156;; +let _ARM_GRP_DPVFP = 157;; +let _ARM_GRP_V6M = 158;; +let _ARM_GRP_VIRTUALIZATION = 159;; +let _ARM_GRP_ENDING = 160;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/capstone.ml b/white_patch_detect/capstone-master/bindings/ocaml/capstone.ml new file mode 100644 index 0000000..9d7a8db --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/capstone.ml @@ -0,0 +1,214 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Arm +open Arm64 +open Mips +open Ppc +open X86 +open Sparc +open Systemz +open Xcore +open M680x +open Printf (* debug *) + +(* Hardware architectures *) +type arch = + | CS_ARCH_ARM + | CS_ARCH_ARM64 + | CS_ARCH_MIPS + | CS_ARCH_X86 + | CS_ARCH_PPC + | CS_ARCH_SPARC + | CS_ARCH_SYSZ + | CS_ARCH_XCORE + | CS_ARCH_M68K + | CS_ARCH_TMS320C64X + | CS_ARCH_M680X + +(* Hardware modes *) +type mode = + | CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *) + | CS_MODE_ARM (* ARM mode *) + | CS_MODE_16 (* 16-bit mode (for X86) *) + | CS_MODE_32 (* 32-bit mode (for X86) *) + | CS_MODE_64 (* 64-bit mode (for X86, PPC) *) + | CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *) + | CS_MODE_MCLASS (* ARM's MClass mode *) + | CS_MODE_V8 (* ARMv8 A32 encodings for ARM *) + | CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *) + | CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *) + | CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *) + | CS_MODE_MIPS2 (* Mips2 mode (MIPS architecture) *) + | CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *) + | CS_MODE_BIG_ENDIAN (* big-endian mode *) + | CS_MODE_MIPS32 (* Mips32 mode (for Mips) *) + | CS_MODE_MIPS64 (* Mips64 mode (for Mips) *) + | CS_MODE_QPX (* Quad Processing eXtensions mode (PowerPC) *) + | CS_MODE_M680X_6301 (* M680X Hitachi 6301,6303 mode *) + | CS_MODE_M680X_6309 (* M680X Hitachi 6309 mode *) + | CS_MODE_M680X_6800 (* M680X Motorola 6800,6802 mode *) + | CS_MODE_M680X_6801 (* M680X Motorola 6801,6803 mode *) + | CS_MODE_M680X_6805 (* M680X Motorola 6805 mode *) + | CS_MODE_M680X_6808 (* M680X Motorola 6808 mode *) + | CS_MODE_M680X_6809 (* M680X Motorola 6809 mode *) + | CS_MODE_M680X_6811 (* M680X Motorola/Freescale 68HC11 mode *) + | CS_MODE_M680X_CPU12 (* M680X Motorola/Freescale/NXP CPU12 mode *) + | CS_MODE_M680X_HCS08 (* M680X Freescale HCS08 mode *) + + + +(* Runtime option for the disassembled engine *) +type opt_type = + | CS_OPT_SYNTAX (* Asssembly output syntax *) + | CS_OPT_DETAIL (* Break down instruction structure into details *) + | CS_OPT_MODE (* Change engine's mode at run-time *) + | CS_OPT_MEM (* User-defined dynamic memory related functions *) + | CS_OPT_SKIPDATA (* Skip data when disassembling. Then engine is in SKIPDATA mode. *) + | CS_OPT_SKIPDATA_SETUP (* Setup user-defined function for SKIPDATA option *) + + +(* Common instruction operand access types - to be consistent across all architectures. *) +(* It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE *) +let _CS_AC_INVALID = 0;; (* Uninitialized/invalid access type. *) +let _CS_AC_READ = 1 lsl 0;; (* Operand read from memory or register. *) +let _CS_AC_WRITE = 1 lsl 1;; (* Operand write to memory or register. *) + +(* Runtime option value (associated with option type above) *) +let _CS_OPT_OFF = 0L;; (* Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. *) +let _CS_OPT_ON = 3L;; (* Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). *) +let _CS_OPT_SYNTAX_DEFAULT = 0L;; (* Default asm syntax (CS_OPT_SYNTAX). *) +let _CS_OPT_SYNTAX_INTEL = 1L;; (* X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). *) +let _CS_OPT_SYNTAX_ATT = 2L;; (* X86 ATT asm syntax (CS_OPT_SYNTAX). *) +let _CS_OPT_SYNTAX_NOREGNAME = 3L;; (* Prints register name with only number (CS_OPT_SYNTAX) *) + +(* Common instruction operand types - to be consistent across all architectures. *) +let _CS_OP_INVALID = 0;; (* uninitialized/invalid operand. *) +let _CS_OP_REG = 1;; (* Register operand. *) +let _CS_OP_IMM = 2;; (* Immediate operand. *) +let _CS_OP_MEM = 3;; (* Memory operand. *) +let _CS_OP_FP = 4;; (* Floating-Point operand. *) + +(* Common instruction groups - to be consistent across all architectures. *) +let _CS_GRP_INVALID = 0;; (* uninitialized/invalid group. *) +let _CS_GRP_JUMP = 1;; (* all jump instructions (conditional+direct+indirect jumps) *) +let _CS_GRP_CALL = 2;; (* all call instructions *) +let _CS_GRP_RET = 3;; (* all return instructions *) +let _CS_GRP_INT = 4;; (* all interrupt instructions (int+syscall) *) +let _CS_GRP_IRET = 5;; (* all interrupt return instructions *) +let _CS_GRP_PRIVILEGE = 6;; (* all privileged instructions *) + +type cs_arch = + | CS_INFO_ARM of cs_arm + | CS_INFO_ARM64 of cs_arm64 + | CS_INFO_MIPS of cs_mips + | CS_INFO_X86 of cs_x86 + | CS_INFO_PPC of cs_ppc + | CS_INFO_SPARC of cs_sparc + | CS_INFO_SYSZ of cs_sysz + | CS_INFO_XCORE of cs_xcore + | CS_INFO_M680X of cs_m680x + + +type csh = { + h: Int64.t; + a: arch; +} + +type cs_insn0 = { + id: int; + address: int; + size: int; + bytes: int array; + mnemonic: string; + op_str: string; + regs_read: int array; + regs_write: int array; + groups: int array; + arch: cs_arch; +} + +external _cs_open: arch -> mode list -> Int64.t option = "ocaml_open" +external cs_disasm_quick: arch -> mode list -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm" +external _cs_disasm_internal: arch -> Int64.t -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm_internal" +external _cs_reg_name: Int64.t -> int -> string = "ocaml_register_name" +external _cs_insn_name: Int64.t -> int -> string = "ocaml_instruction_name" +external _cs_group_name: Int64.t -> int -> string = "ocaml_group_name" +external cs_version: unit -> int = "ocaml_version" +external _cs_option: Int64.t -> opt_type -> Int64.t -> int = "ocaml_option" +external _cs_close: Int64.t -> int = "ocaml_close" + + +let cs_open _arch _mode: csh = ( + let _handle = _cs_open _arch _mode in ( + match _handle with + | None -> { h = 0L; a = _arch } + | Some v -> { h = v; a = _arch } + ); +);; + +let cs_close handle = ( + _cs_close handle.h; +) + +let cs_option handle opt value = ( + _cs_option handle.h opt value; +);; + +let cs_disasm handle code address count = ( + _cs_disasm_internal handle.a handle.h code address count; +);; + +let cs_reg_name handle id = ( + _cs_reg_name handle.h id; +);; + +let cs_insn_name handle id = ( + _cs_insn_name handle.h id; +);; + +let cs_group_name handle id = ( + _cs_group_name handle.h id; +);; + +class cs_insn c a = + let csh = c in + let (id, address, size, bytes, mnemonic, op_str, regs_read, + regs_write, groups, arch) = + (a.id, a.address, a.size, a.bytes, a.mnemonic, a.op_str, + a.regs_read, a.regs_write, a.groups, a.arch) in + object + method id = id; + method address = address; + method size = size; + method bytes = bytes; + method mnemonic = mnemonic; + method op_str = op_str; + method regs_read = regs_read; + method regs_write = regs_write; + method groups = groups; + method arch = arch; + method reg_name id = _cs_reg_name csh.h id; + method insn_name id = _cs_insn_name csh.h id; + method group_name id = _cs_group_name csh.h id; + end;; + +let cs_insn_group handle insn group_id = + List.exists (fun g -> g == group_id) (Array.to_list insn.groups);; + +let cs_reg_read handle insn reg_id = + List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_read);; + +let cs_reg_write handle insn reg_id = + List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_write);; + + +class cs a m = + let mode = m and arch = a in + let handle = cs_open arch mode in + object + method disasm code offset count = + let insns = (_cs_disasm_internal arch handle.h code offset count) in + List.map (fun x -> new cs_insn handle x) insns; + + end;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/evm_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/evm_const.ml new file mode 100644 index 0000000..050a8b4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/evm_const.ml @@ -0,0 +1,151 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.ml] *) + +let _EVM_INS_STOP = 0;; +let _EVM_INS_ADD = 1;; +let _EVM_INS_MUL = 2;; +let _EVM_INS_SUB = 3;; +let _EVM_INS_DIV = 4;; +let _EVM_INS_SDIV = 5;; +let _EVM_INS_MOD = 6;; +let _EVM_INS_SMOD = 7;; +let _EVM_INS_ADDMOD = 8;; +let _EVM_INS_MULMOD = 9;; +let _EVM_INS_EXP = 10;; +let _EVM_INS_SIGNEXTEND = 11;; +let _EVM_INS_LT = 16;; +let _EVM_INS_GT = 17;; +let _EVM_INS_SLT = 18;; +let _EVM_INS_SGT = 19;; +let _EVM_INS_EQ = 20;; +let _EVM_INS_ISZERO = 21;; +let _EVM_INS_AND = 22;; +let _EVM_INS_OR = 23;; +let _EVM_INS_XOR = 24;; +let _EVM_INS_NOT = 25;; +let _EVM_INS_BYTE = 26;; +let _EVM_INS_SHA3 = 32;; +let _EVM_INS_ADDRESS = 48;; +let _EVM_INS_BALANCE = 49;; +let _EVM_INS_ORIGIN = 50;; +let _EVM_INS_CALLER = 51;; +let _EVM_INS_CALLVALUE = 52;; +let _EVM_INS_CALLDATALOAD = 53;; +let _EVM_INS_CALLDATASIZE = 54;; +let _EVM_INS_CALLDATACOPY = 55;; +let _EVM_INS_CODESIZE = 56;; +let _EVM_INS_CODECOPY = 57;; +let _EVM_INS_GASPRICE = 58;; +let _EVM_INS_EXTCODESIZE = 59;; +let _EVM_INS_EXTCODECOPY = 60;; +let _EVM_INS_RETURNDATASIZE = 61;; +let _EVM_INS_RETURNDATACOPY = 62;; +let _EVM_INS_BLOCKHASH = 64;; +let _EVM_INS_COINBASE = 65;; +let _EVM_INS_TIMESTAMP = 66;; +let _EVM_INS_NUMBER = 67;; +let _EVM_INS_DIFFICULTY = 68;; +let _EVM_INS_GASLIMIT = 69;; +let _EVM_INS_POP = 80;; +let _EVM_INS_MLOAD = 81;; +let _EVM_INS_MSTORE = 82;; +let _EVM_INS_MSTORE8 = 83;; +let _EVM_INS_SLOAD = 84;; +let _EVM_INS_SSTORE = 85;; +let _EVM_INS_JUMP = 86;; +let _EVM_INS_JUMPI = 87;; +let _EVM_INS_PC = 88;; +let _EVM_INS_MSIZE = 89;; +let _EVM_INS_GAS = 90;; +let _EVM_INS_JUMPDEST = 91;; +let _EVM_INS_PUSH1 = 96;; +let _EVM_INS_PUSH2 = 97;; +let _EVM_INS_PUSH3 = 98;; +let _EVM_INS_PUSH4 = 99;; +let _EVM_INS_PUSH5 = 100;; +let _EVM_INS_PUSH6 = 101;; +let _EVM_INS_PUSH7 = 102;; +let _EVM_INS_PUSH8 = 103;; +let _EVM_INS_PUSH9 = 104;; +let _EVM_INS_PUSH10 = 105;; +let _EVM_INS_PUSH11 = 106;; +let _EVM_INS_PUSH12 = 107;; +let _EVM_INS_PUSH13 = 108;; +let _EVM_INS_PUSH14 = 109;; +let _EVM_INS_PUSH15 = 110;; +let _EVM_INS_PUSH16 = 111;; +let _EVM_INS_PUSH17 = 112;; +let _EVM_INS_PUSH18 = 113;; +let _EVM_INS_PUSH19 = 114;; +let _EVM_INS_PUSH20 = 115;; +let _EVM_INS_PUSH21 = 116;; +let _EVM_INS_PUSH22 = 117;; +let _EVM_INS_PUSH23 = 118;; +let _EVM_INS_PUSH24 = 119;; +let _EVM_INS_PUSH25 = 120;; +let _EVM_INS_PUSH26 = 121;; +let _EVM_INS_PUSH27 = 122;; +let _EVM_INS_PUSH28 = 123;; +let _EVM_INS_PUSH29 = 124;; +let _EVM_INS_PUSH30 = 125;; +let _EVM_INS_PUSH31 = 126;; +let _EVM_INS_PUSH32 = 127;; +let _EVM_INS_DUP1 = 128;; +let _EVM_INS_DUP2 = 129;; +let _EVM_INS_DUP3 = 130;; +let _EVM_INS_DUP4 = 131;; +let _EVM_INS_DUP5 = 132;; +let _EVM_INS_DUP6 = 133;; +let _EVM_INS_DUP7 = 134;; +let _EVM_INS_DUP8 = 135;; +let _EVM_INS_DUP9 = 136;; +let _EVM_INS_DUP10 = 137;; +let _EVM_INS_DUP11 = 138;; +let _EVM_INS_DUP12 = 139;; +let _EVM_INS_DUP13 = 140;; +let _EVM_INS_DUP14 = 141;; +let _EVM_INS_DUP15 = 142;; +let _EVM_INS_DUP16 = 143;; +let _EVM_INS_SWAP1 = 144;; +let _EVM_INS_SWAP2 = 145;; +let _EVM_INS_SWAP3 = 146;; +let _EVM_INS_SWAP4 = 147;; +let _EVM_INS_SWAP5 = 148;; +let _EVM_INS_SWAP6 = 149;; +let _EVM_INS_SWAP7 = 150;; +let _EVM_INS_SWAP8 = 151;; +let _EVM_INS_SWAP9 = 152;; +let _EVM_INS_SWAP10 = 153;; +let _EVM_INS_SWAP11 = 154;; +let _EVM_INS_SWAP12 = 155;; +let _EVM_INS_SWAP13 = 156;; +let _EVM_INS_SWAP14 = 157;; +let _EVM_INS_SWAP15 = 158;; +let _EVM_INS_SWAP16 = 159;; +let _EVM_INS_LOG0 = 160;; +let _EVM_INS_LOG1 = 161;; +let _EVM_INS_LOG2 = 162;; +let _EVM_INS_LOG3 = 163;; +let _EVM_INS_LOG4 = 164;; +let _EVM_INS_CREATE = 240;; +let _EVM_INS_CALL = 241;; +let _EVM_INS_CALLCODE = 242;; +let _EVM_INS_RETURN = 243;; +let _EVM_INS_DELEGATECALL = 244;; +let _EVM_INS_CALLBLACKBOX = 245;; +let _EVM_INS_STATICCALL = 250;; +let _EVM_INS_REVERT = 253;; +let _EVM_INS_SUICIDE = 255;; +let _EVM_INS_INVALID = 512;; +let _EVM_INS_ENDING = 513;; + +let _EVM_GRP_INVALID = 0;; +let _EVM_GRP_JUMP = 1;; +let _EVM_GRP_MATH = 8;; +let _EVM_GRP_STACK_WRITE = 9;; +let _EVM_GRP_STACK_READ = 10;; +let _EVM_GRP_MEM_WRITE = 11;; +let _EVM_GRP_MEM_READ = 12;; +let _EVM_GRP_STORE_WRITE = 13;; +let _EVM_GRP_STORE_READ = 14;; +let _EVM_GRP_HALT = 15;; +let _EVM_GRP_ENDING = 16;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/m680x.ml b/white_patch_detect/capstone-master/bindings/ocaml/m680x.ml new file mode 100644 index 0000000..139715d --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/m680x.ml @@ -0,0 +1,48 @@ +(* Capstone Disassembly Engine + * M680X Backend by Wolfgang Schwotzer 2017 *) + +open M680x_const + + +(* architecture specific info of instruction *) +type m680x_op_idx = { + base_reg: int; + offset_reg: int; + offset: int; + offset_addr: int; + offset_bits: int; + inc_dec: int; + flags: int; +} + +type m680x_op_rel = { + addr_rel: int; + offset: int; +} + +type m680x_op_ext = { + addr_ext: int; + indirect: bool; +} + +type m680x_op_value = + | M680X_OP_INVALID of int + | M680X_OP_IMMEDIATE of int + | M680X_OP_REGISTER of int + | M680X_OP_INDEXED of m680x_op_idx + | M680X_OP_RELATIVE of m680x_op_rel + | M680X_OP_EXTENDED of m680x_op_ext + | M680X_OP_DIRECT of int + | M680X_OP_CONSTANT of int + +type m680x_op = { + value: m680x_op_value; + size: int; + access: int; +} + +type cs_m680x = { + flags: int; + operands: m680x_op array; +} + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/m680x_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/m680x_const.ml new file mode 100644 index 0000000..5e88710 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/m680x_const.ml @@ -0,0 +1,415 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.ml] *) +let _M680X_OPERAND_COUNT = 9;; + +let _M680X_REG_INVALID = 0;; +let _M680X_REG_A = 1;; +let _M680X_REG_B = 2;; +let _M680X_REG_E = 3;; +let _M680X_REG_F = 4;; +let _M680X_REG_0 = 5;; +let _M680X_REG_D = 6;; +let _M680X_REG_W = 7;; +let _M680X_REG_CC = 8;; +let _M680X_REG_DP = 9;; +let _M680X_REG_MD = 10;; +let _M680X_REG_HX = 11;; +let _M680X_REG_H = 12;; +let _M680X_REG_X = 13;; +let _M680X_REG_Y = 14;; +let _M680X_REG_S = 15;; +let _M680X_REG_U = 16;; +let _M680X_REG_V = 17;; +let _M680X_REG_Q = 18;; +let _M680X_REG_PC = 19;; +let _M680X_REG_TMP2 = 20;; +let _M680X_REG_TMP3 = 21;; +let _M680X_REG_ENDING = 22;; + +let _M680X_OP_INVALID = 0;; +let _M680X_OP_REGISTER = 1;; +let _M680X_OP_IMMEDIATE = 2;; +let _M680X_OP_INDEXED = 3;; +let _M680X_OP_EXTENDED = 4;; +let _M680X_OP_DIRECT = 5;; +let _M680X_OP_RELATIVE = 6;; +let _M680X_OP_CONSTANT = 7;; + +let _M680X_OFFSET_NONE = 0;; +let _M680X_OFFSET_BITS_5 = 5;; +let _M680X_OFFSET_BITS_8 = 8;; +let _M680X_OFFSET_BITS_9 = 9;; +let _M680X_OFFSET_BITS_16 = 16;; +let _M680X_IDX_INDIRECT = 1;; +let _M680X_IDX_NO_COMMA = 2;; +let _M680X_IDX_POST_INC_DEC = 4;; + +let _M680X_GRP_INVALID = 0;; +let _M680X_GRP_JUMP = 1;; +let _M680X_GRP_CALL = 2;; +let _M680X_GRP_RET = 3;; +let _M680X_GRP_INT = 4;; +let _M680X_GRP_IRET = 5;; +let _M680X_GRP_PRIV = 6;; +let _M680X_GRP_BRAREL = 7;; +let _M680X_GRP_ENDING = 8;; +let _M680X_FIRST_OP_IN_MNEM = 1;; +let _M680X_SECOND_OP_IN_MNEM = 2;; + +let _M680X_INS_INVLD = 0;; +let _M680X_INS_ABA = 1;; +let _M680X_INS_ABX = 2;; +let _M680X_INS_ABY = 3;; +let _M680X_INS_ADC = 4;; +let _M680X_INS_ADCA = 5;; +let _M680X_INS_ADCB = 6;; +let _M680X_INS_ADCD = 7;; +let _M680X_INS_ADCR = 8;; +let _M680X_INS_ADD = 9;; +let _M680X_INS_ADDA = 10;; +let _M680X_INS_ADDB = 11;; +let _M680X_INS_ADDD = 12;; +let _M680X_INS_ADDE = 13;; +let _M680X_INS_ADDF = 14;; +let _M680X_INS_ADDR = 15;; +let _M680X_INS_ADDW = 16;; +let _M680X_INS_AIM = 17;; +let _M680X_INS_AIS = 18;; +let _M680X_INS_AIX = 19;; +let _M680X_INS_AND = 20;; +let _M680X_INS_ANDA = 21;; +let _M680X_INS_ANDB = 22;; +let _M680X_INS_ANDCC = 23;; +let _M680X_INS_ANDD = 24;; +let _M680X_INS_ANDR = 25;; +let _M680X_INS_ASL = 26;; +let _M680X_INS_ASLA = 27;; +let _M680X_INS_ASLB = 28;; +let _M680X_INS_ASLD = 29;; +let _M680X_INS_ASR = 30;; +let _M680X_INS_ASRA = 31;; +let _M680X_INS_ASRB = 32;; +let _M680X_INS_ASRD = 33;; +let _M680X_INS_ASRX = 34;; +let _M680X_INS_BAND = 35;; +let _M680X_INS_BCC = 36;; +let _M680X_INS_BCLR = 37;; +let _M680X_INS_BCS = 38;; +let _M680X_INS_BEOR = 39;; +let _M680X_INS_BEQ = 40;; +let _M680X_INS_BGE = 41;; +let _M680X_INS_BGND = 42;; +let _M680X_INS_BGT = 43;; +let _M680X_INS_BHCC = 44;; +let _M680X_INS_BHCS = 45;; +let _M680X_INS_BHI = 46;; +let _M680X_INS_BIAND = 47;; +let _M680X_INS_BIEOR = 48;; +let _M680X_INS_BIH = 49;; +let _M680X_INS_BIL = 50;; +let _M680X_INS_BIOR = 51;; +let _M680X_INS_BIT = 52;; +let _M680X_INS_BITA = 53;; +let _M680X_INS_BITB = 54;; +let _M680X_INS_BITD = 55;; +let _M680X_INS_BITMD = 56;; +let _M680X_INS_BLE = 57;; +let _M680X_INS_BLS = 58;; +let _M680X_INS_BLT = 59;; +let _M680X_INS_BMC = 60;; +let _M680X_INS_BMI = 61;; +let _M680X_INS_BMS = 62;; +let _M680X_INS_BNE = 63;; +let _M680X_INS_BOR = 64;; +let _M680X_INS_BPL = 65;; +let _M680X_INS_BRCLR = 66;; +let _M680X_INS_BRSET = 67;; +let _M680X_INS_BRA = 68;; +let _M680X_INS_BRN = 69;; +let _M680X_INS_BSET = 70;; +let _M680X_INS_BSR = 71;; +let _M680X_INS_BVC = 72;; +let _M680X_INS_BVS = 73;; +let _M680X_INS_CALL = 74;; +let _M680X_INS_CBA = 75;; +let _M680X_INS_CBEQ = 76;; +let _M680X_INS_CBEQA = 77;; +let _M680X_INS_CBEQX = 78;; +let _M680X_INS_CLC = 79;; +let _M680X_INS_CLI = 80;; +let _M680X_INS_CLR = 81;; +let _M680X_INS_CLRA = 82;; +let _M680X_INS_CLRB = 83;; +let _M680X_INS_CLRD = 84;; +let _M680X_INS_CLRE = 85;; +let _M680X_INS_CLRF = 86;; +let _M680X_INS_CLRH = 87;; +let _M680X_INS_CLRW = 88;; +let _M680X_INS_CLRX = 89;; +let _M680X_INS_CLV = 90;; +let _M680X_INS_CMP = 91;; +let _M680X_INS_CMPA = 92;; +let _M680X_INS_CMPB = 93;; +let _M680X_INS_CMPD = 94;; +let _M680X_INS_CMPE = 95;; +let _M680X_INS_CMPF = 96;; +let _M680X_INS_CMPR = 97;; +let _M680X_INS_CMPS = 98;; +let _M680X_INS_CMPU = 99;; +let _M680X_INS_CMPW = 100;; +let _M680X_INS_CMPX = 101;; +let _M680X_INS_CMPY = 102;; +let _M680X_INS_COM = 103;; +let _M680X_INS_COMA = 104;; +let _M680X_INS_COMB = 105;; +let _M680X_INS_COMD = 106;; +let _M680X_INS_COME = 107;; +let _M680X_INS_COMF = 108;; +let _M680X_INS_COMW = 109;; +let _M680X_INS_COMX = 110;; +let _M680X_INS_CPD = 111;; +let _M680X_INS_CPHX = 112;; +let _M680X_INS_CPS = 113;; +let _M680X_INS_CPX = 114;; +let _M680X_INS_CPY = 115;; +let _M680X_INS_CWAI = 116;; +let _M680X_INS_DAA = 117;; +let _M680X_INS_DBEQ = 118;; +let _M680X_INS_DBNE = 119;; +let _M680X_INS_DBNZ = 120;; +let _M680X_INS_DBNZA = 121;; +let _M680X_INS_DBNZX = 122;; +let _M680X_INS_DEC = 123;; +let _M680X_INS_DECA = 124;; +let _M680X_INS_DECB = 125;; +let _M680X_INS_DECD = 126;; +let _M680X_INS_DECE = 127;; +let _M680X_INS_DECF = 128;; +let _M680X_INS_DECW = 129;; +let _M680X_INS_DECX = 130;; +let _M680X_INS_DES = 131;; +let _M680X_INS_DEX = 132;; +let _M680X_INS_DEY = 133;; +let _M680X_INS_DIV = 134;; +let _M680X_INS_DIVD = 135;; +let _M680X_INS_DIVQ = 136;; +let _M680X_INS_EDIV = 137;; +let _M680X_INS_EDIVS = 138;; +let _M680X_INS_EIM = 139;; +let _M680X_INS_EMACS = 140;; +let _M680X_INS_EMAXD = 141;; +let _M680X_INS_EMAXM = 142;; +let _M680X_INS_EMIND = 143;; +let _M680X_INS_EMINM = 144;; +let _M680X_INS_EMUL = 145;; +let _M680X_INS_EMULS = 146;; +let _M680X_INS_EOR = 147;; +let _M680X_INS_EORA = 148;; +let _M680X_INS_EORB = 149;; +let _M680X_INS_EORD = 150;; +let _M680X_INS_EORR = 151;; +let _M680X_INS_ETBL = 152;; +let _M680X_INS_EXG = 153;; +let _M680X_INS_FDIV = 154;; +let _M680X_INS_IBEQ = 155;; +let _M680X_INS_IBNE = 156;; +let _M680X_INS_IDIV = 157;; +let _M680X_INS_IDIVS = 158;; +let _M680X_INS_ILLGL = 159;; +let _M680X_INS_INC = 160;; +let _M680X_INS_INCA = 161;; +let _M680X_INS_INCB = 162;; +let _M680X_INS_INCD = 163;; +let _M680X_INS_INCE = 164;; +let _M680X_INS_INCF = 165;; +let _M680X_INS_INCW = 166;; +let _M680X_INS_INCX = 167;; +let _M680X_INS_INS = 168;; +let _M680X_INS_INX = 169;; +let _M680X_INS_INY = 170;; +let _M680X_INS_JMP = 171;; +let _M680X_INS_JSR = 172;; +let _M680X_INS_LBCC = 173;; +let _M680X_INS_LBCS = 174;; +let _M680X_INS_LBEQ = 175;; +let _M680X_INS_LBGE = 176;; +let _M680X_INS_LBGT = 177;; +let _M680X_INS_LBHI = 178;; +let _M680X_INS_LBLE = 179;; +let _M680X_INS_LBLS = 180;; +let _M680X_INS_LBLT = 181;; +let _M680X_INS_LBMI = 182;; +let _M680X_INS_LBNE = 183;; +let _M680X_INS_LBPL = 184;; +let _M680X_INS_LBRA = 185;; +let _M680X_INS_LBRN = 186;; +let _M680X_INS_LBSR = 187;; +let _M680X_INS_LBVC = 188;; +let _M680X_INS_LBVS = 189;; +let _M680X_INS_LDA = 190;; +let _M680X_INS_LDAA = 191;; +let _M680X_INS_LDAB = 192;; +let _M680X_INS_LDB = 193;; +let _M680X_INS_LDBT = 194;; +let _M680X_INS_LDD = 195;; +let _M680X_INS_LDE = 196;; +let _M680X_INS_LDF = 197;; +let _M680X_INS_LDHX = 198;; +let _M680X_INS_LDMD = 199;; +let _M680X_INS_LDQ = 200;; +let _M680X_INS_LDS = 201;; +let _M680X_INS_LDU = 202;; +let _M680X_INS_LDW = 203;; +let _M680X_INS_LDX = 204;; +let _M680X_INS_LDY = 205;; +let _M680X_INS_LEAS = 206;; +let _M680X_INS_LEAU = 207;; +let _M680X_INS_LEAX = 208;; +let _M680X_INS_LEAY = 209;; +let _M680X_INS_LSL = 210;; +let _M680X_INS_LSLA = 211;; +let _M680X_INS_LSLB = 212;; +let _M680X_INS_LSLD = 213;; +let _M680X_INS_LSLX = 214;; +let _M680X_INS_LSR = 215;; +let _M680X_INS_LSRA = 216;; +let _M680X_INS_LSRB = 217;; +let _M680X_INS_LSRD = 218;; +let _M680X_INS_LSRW = 219;; +let _M680X_INS_LSRX = 220;; +let _M680X_INS_MAXA = 221;; +let _M680X_INS_MAXM = 222;; +let _M680X_INS_MEM = 223;; +let _M680X_INS_MINA = 224;; +let _M680X_INS_MINM = 225;; +let _M680X_INS_MOV = 226;; +let _M680X_INS_MOVB = 227;; +let _M680X_INS_MOVW = 228;; +let _M680X_INS_MUL = 229;; +let _M680X_INS_MULD = 230;; +let _M680X_INS_NEG = 231;; +let _M680X_INS_NEGA = 232;; +let _M680X_INS_NEGB = 233;; +let _M680X_INS_NEGD = 234;; +let _M680X_INS_NEGX = 235;; +let _M680X_INS_NOP = 236;; +let _M680X_INS_NSA = 237;; +let _M680X_INS_OIM = 238;; +let _M680X_INS_ORA = 239;; +let _M680X_INS_ORAA = 240;; +let _M680X_INS_ORAB = 241;; +let _M680X_INS_ORB = 242;; +let _M680X_INS_ORCC = 243;; +let _M680X_INS_ORD = 244;; +let _M680X_INS_ORR = 245;; +let _M680X_INS_PSHA = 246;; +let _M680X_INS_PSHB = 247;; +let _M680X_INS_PSHC = 248;; +let _M680X_INS_PSHD = 249;; +let _M680X_INS_PSHH = 250;; +let _M680X_INS_PSHS = 251;; +let _M680X_INS_PSHSW = 252;; +let _M680X_INS_PSHU = 253;; +let _M680X_INS_PSHUW = 254;; +let _M680X_INS_PSHX = 255;; +let _M680X_INS_PSHY = 256;; +let _M680X_INS_PULA = 257;; +let _M680X_INS_PULB = 258;; +let _M680X_INS_PULC = 259;; +let _M680X_INS_PULD = 260;; +let _M680X_INS_PULH = 261;; +let _M680X_INS_PULS = 262;; +let _M680X_INS_PULSW = 263;; +let _M680X_INS_PULU = 264;; +let _M680X_INS_PULUW = 265;; +let _M680X_INS_PULX = 266;; +let _M680X_INS_PULY = 267;; +let _M680X_INS_REV = 268;; +let _M680X_INS_REVW = 269;; +let _M680X_INS_ROL = 270;; +let _M680X_INS_ROLA = 271;; +let _M680X_INS_ROLB = 272;; +let _M680X_INS_ROLD = 273;; +let _M680X_INS_ROLW = 274;; +let _M680X_INS_ROLX = 275;; +let _M680X_INS_ROR = 276;; +let _M680X_INS_RORA = 277;; +let _M680X_INS_RORB = 278;; +let _M680X_INS_RORD = 279;; +let _M680X_INS_RORW = 280;; +let _M680X_INS_RORX = 281;; +let _M680X_INS_RSP = 282;; +let _M680X_INS_RTC = 283;; +let _M680X_INS_RTI = 284;; +let _M680X_INS_RTS = 285;; +let _M680X_INS_SBA = 286;; +let _M680X_INS_SBC = 287;; +let _M680X_INS_SBCA = 288;; +let _M680X_INS_SBCB = 289;; +let _M680X_INS_SBCD = 290;; +let _M680X_INS_SBCR = 291;; +let _M680X_INS_SEC = 292;; +let _M680X_INS_SEI = 293;; +let _M680X_INS_SEV = 294;; +let _M680X_INS_SEX = 295;; +let _M680X_INS_SEXW = 296;; +let _M680X_INS_SLP = 297;; +let _M680X_INS_STA = 298;; +let _M680X_INS_STAA = 299;; +let _M680X_INS_STAB = 300;; +let _M680X_INS_STB = 301;; +let _M680X_INS_STBT = 302;; +let _M680X_INS_STD = 303;; +let _M680X_INS_STE = 304;; +let _M680X_INS_STF = 305;; +let _M680X_INS_STOP = 306;; +let _M680X_INS_STHX = 307;; +let _M680X_INS_STQ = 308;; +let _M680X_INS_STS = 309;; +let _M680X_INS_STU = 310;; +let _M680X_INS_STW = 311;; +let _M680X_INS_STX = 312;; +let _M680X_INS_STY = 313;; +let _M680X_INS_SUB = 314;; +let _M680X_INS_SUBA = 315;; +let _M680X_INS_SUBB = 316;; +let _M680X_INS_SUBD = 317;; +let _M680X_INS_SUBE = 318;; +let _M680X_INS_SUBF = 319;; +let _M680X_INS_SUBR = 320;; +let _M680X_INS_SUBW = 321;; +let _M680X_INS_SWI = 322;; +let _M680X_INS_SWI2 = 323;; +let _M680X_INS_SWI3 = 324;; +let _M680X_INS_SYNC = 325;; +let _M680X_INS_TAB = 326;; +let _M680X_INS_TAP = 327;; +let _M680X_INS_TAX = 328;; +let _M680X_INS_TBA = 329;; +let _M680X_INS_TBEQ = 330;; +let _M680X_INS_TBL = 331;; +let _M680X_INS_TBNE = 332;; +let _M680X_INS_TEST = 333;; +let _M680X_INS_TFM = 334;; +let _M680X_INS_TFR = 335;; +let _M680X_INS_TIM = 336;; +let _M680X_INS_TPA = 337;; +let _M680X_INS_TST = 338;; +let _M680X_INS_TSTA = 339;; +let _M680X_INS_TSTB = 340;; +let _M680X_INS_TSTD = 341;; +let _M680X_INS_TSTE = 342;; +let _M680X_INS_TSTF = 343;; +let _M680X_INS_TSTW = 344;; +let _M680X_INS_TSTX = 345;; +let _M680X_INS_TSX = 346;; +let _M680X_INS_TSY = 347;; +let _M680X_INS_TXA = 348;; +let _M680X_INS_TXS = 349;; +let _M680X_INS_TYS = 350;; +let _M680X_INS_WAI = 351;; +let _M680X_INS_WAIT = 352;; +let _M680X_INS_WAV = 353;; +let _M680X_INS_WAVR = 354;; +let _M680X_INS_XGDX = 355;; +let _M680X_INS_XGDY = 356;; +let _M680X_INS_ENDING = 357;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/m68k_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/m68k_const.ml new file mode 100644 index 0000000..f060d4f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/m68k_const.ml @@ -0,0 +1,485 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.ml] *) +let _M68K_OPERAND_COUNT = 4;; + +let _M68K_REG_INVALID = 0;; +let _M68K_REG_D0 = 1;; +let _M68K_REG_D1 = 2;; +let _M68K_REG_D2 = 3;; +let _M68K_REG_D3 = 4;; +let _M68K_REG_D4 = 5;; +let _M68K_REG_D5 = 6;; +let _M68K_REG_D6 = 7;; +let _M68K_REG_D7 = 8;; +let _M68K_REG_A0 = 9;; +let _M68K_REG_A1 = 10;; +let _M68K_REG_A2 = 11;; +let _M68K_REG_A3 = 12;; +let _M68K_REG_A4 = 13;; +let _M68K_REG_A5 = 14;; +let _M68K_REG_A6 = 15;; +let _M68K_REG_A7 = 16;; +let _M68K_REG_FP0 = 17;; +let _M68K_REG_FP1 = 18;; +let _M68K_REG_FP2 = 19;; +let _M68K_REG_FP3 = 20;; +let _M68K_REG_FP4 = 21;; +let _M68K_REG_FP5 = 22;; +let _M68K_REG_FP6 = 23;; +let _M68K_REG_FP7 = 24;; +let _M68K_REG_PC = 25;; +let _M68K_REG_SR = 26;; +let _M68K_REG_CCR = 27;; +let _M68K_REG_SFC = 28;; +let _M68K_REG_DFC = 29;; +let _M68K_REG_USP = 30;; +let _M68K_REG_VBR = 31;; +let _M68K_REG_CACR = 32;; +let _M68K_REG_CAAR = 33;; +let _M68K_REG_MSP = 34;; +let _M68K_REG_ISP = 35;; +let _M68K_REG_TC = 36;; +let _M68K_REG_ITT0 = 37;; +let _M68K_REG_ITT1 = 38;; +let _M68K_REG_DTT0 = 39;; +let _M68K_REG_DTT1 = 40;; +let _M68K_REG_MMUSR = 41;; +let _M68K_REG_URP = 42;; +let _M68K_REG_SRP = 43;; +let _M68K_REG_FPCR = 44;; +let _M68K_REG_FPSR = 45;; +let _M68K_REG_FPIAR = 46;; +let _M68K_REG_ENDING = 47;; + +let _M68K_AM_NONE = 0;; +let _M68K_AM_REG_DIRECT_DATA = 1;; +let _M68K_AM_REG_DIRECT_ADDR = 2;; +let _M68K_AM_REGI_ADDR = 3;; +let _M68K_AM_REGI_ADDR_POST_INC = 4;; +let _M68K_AM_REGI_ADDR_PRE_DEC = 5;; +let _M68K_AM_REGI_ADDR_DISP = 6;; +let _M68K_AM_AREGI_INDEX_8_BIT_DISP = 7;; +let _M68K_AM_AREGI_INDEX_BASE_DISP = 8;; +let _M68K_AM_MEMI_POST_INDEX = 9;; +let _M68K_AM_MEMI_PRE_INDEX = 10;; +let _M68K_AM_PCI_DISP = 11;; +let _M68K_AM_PCI_INDEX_8_BIT_DISP = 12;; +let _M68K_AM_PCI_INDEX_BASE_DISP = 13;; +let _M68K_AM_PC_MEMI_POST_INDEX = 14;; +let _M68K_AM_PC_MEMI_PRE_INDEX = 15;; +let _M68K_AM_ABSOLUTE_DATA_SHORT = 16;; +let _M68K_AM_ABSOLUTE_DATA_LONG = 17;; +let _M68K_AM_IMMEDIATE = 18;; +let _M68K_AM_BRANCH_DISPLACEMENT = 19;; + +let _M68K_OP_INVALID = 0;; +let _M68K_OP_REG = 1;; +let _M68K_OP_IMM = 2;; +let _M68K_OP_MEM = 3;; +let _M68K_OP_FP_SINGLE = 4;; +let _M68K_OP_FP_DOUBLE = 5;; +let _M68K_OP_REG_BITS = 6;; +let _M68K_OP_REG_PAIR = 7;; +let _M68K_OP_BR_DISP = 8;; + +let _M68K_OP_BR_DISP_SIZE_INVALID = 0;; +let _M68K_OP_BR_DISP_SIZE_BYTE = 1;; +let _M68K_OP_BR_DISP_SIZE_WORD = 2;; +let _M68K_OP_BR_DISP_SIZE_LONG = 4;; + +let _M68K_CPU_SIZE_NONE = 0;; +let _M68K_CPU_SIZE_BYTE = 1;; +let _M68K_CPU_SIZE_WORD = 2;; +let _M68K_CPU_SIZE_LONG = 4;; + +let _M68K_FPU_SIZE_NONE = 0;; +let _M68K_FPU_SIZE_SINGLE = 4;; +let _M68K_FPU_SIZE_DOUBLE = 8;; +let _M68K_FPU_SIZE_EXTENDED = 12;; + +let _M68K_SIZE_TYPE_INVALID = 0;; +let _M68K_SIZE_TYPE_CPU = 1;; +let _M68K_SIZE_TYPE_FPU = 2;; + +let _M68K_INS_INVALID = 0;; +let _M68K_INS_ABCD = 1;; +let _M68K_INS_ADD = 2;; +let _M68K_INS_ADDA = 3;; +let _M68K_INS_ADDI = 4;; +let _M68K_INS_ADDQ = 5;; +let _M68K_INS_ADDX = 6;; +let _M68K_INS_AND = 7;; +let _M68K_INS_ANDI = 8;; +let _M68K_INS_ASL = 9;; +let _M68K_INS_ASR = 10;; +let _M68K_INS_BHS = 11;; +let _M68K_INS_BLO = 12;; +let _M68K_INS_BHI = 13;; +let _M68K_INS_BLS = 14;; +let _M68K_INS_BCC = 15;; +let _M68K_INS_BCS = 16;; +let _M68K_INS_BNE = 17;; +let _M68K_INS_BEQ = 18;; +let _M68K_INS_BVC = 19;; +let _M68K_INS_BVS = 20;; +let _M68K_INS_BPL = 21;; +let _M68K_INS_BMI = 22;; +let _M68K_INS_BGE = 23;; +let _M68K_INS_BLT = 24;; +let _M68K_INS_BGT = 25;; +let _M68K_INS_BLE = 26;; +let _M68K_INS_BRA = 27;; +let _M68K_INS_BSR = 28;; +let _M68K_INS_BCHG = 29;; +let _M68K_INS_BCLR = 30;; +let _M68K_INS_BSET = 31;; +let _M68K_INS_BTST = 32;; +let _M68K_INS_BFCHG = 33;; +let _M68K_INS_BFCLR = 34;; +let _M68K_INS_BFEXTS = 35;; +let _M68K_INS_BFEXTU = 36;; +let _M68K_INS_BFFFO = 37;; +let _M68K_INS_BFINS = 38;; +let _M68K_INS_BFSET = 39;; +let _M68K_INS_BFTST = 40;; +let _M68K_INS_BKPT = 41;; +let _M68K_INS_CALLM = 42;; +let _M68K_INS_CAS = 43;; +let _M68K_INS_CAS2 = 44;; +let _M68K_INS_CHK = 45;; +let _M68K_INS_CHK2 = 46;; +let _M68K_INS_CLR = 47;; +let _M68K_INS_CMP = 48;; +let _M68K_INS_CMPA = 49;; +let _M68K_INS_CMPI = 50;; +let _M68K_INS_CMPM = 51;; +let _M68K_INS_CMP2 = 52;; +let _M68K_INS_CINVL = 53;; +let _M68K_INS_CINVP = 54;; +let _M68K_INS_CINVA = 55;; +let _M68K_INS_CPUSHL = 56;; +let _M68K_INS_CPUSHP = 57;; +let _M68K_INS_CPUSHA = 58;; +let _M68K_INS_DBT = 59;; +let _M68K_INS_DBF = 60;; +let _M68K_INS_DBHI = 61;; +let _M68K_INS_DBLS = 62;; +let _M68K_INS_DBCC = 63;; +let _M68K_INS_DBCS = 64;; +let _M68K_INS_DBNE = 65;; +let _M68K_INS_DBEQ = 66;; +let _M68K_INS_DBVC = 67;; +let _M68K_INS_DBVS = 68;; +let _M68K_INS_DBPL = 69;; +let _M68K_INS_DBMI = 70;; +let _M68K_INS_DBGE = 71;; +let _M68K_INS_DBLT = 72;; +let _M68K_INS_DBGT = 73;; +let _M68K_INS_DBLE = 74;; +let _M68K_INS_DBRA = 75;; +let _M68K_INS_DIVS = 76;; +let _M68K_INS_DIVSL = 77;; +let _M68K_INS_DIVU = 78;; +let _M68K_INS_DIVUL = 79;; +let _M68K_INS_EOR = 80;; +let _M68K_INS_EORI = 81;; +let _M68K_INS_EXG = 82;; +let _M68K_INS_EXT = 83;; +let _M68K_INS_EXTB = 84;; +let _M68K_INS_FABS = 85;; +let _M68K_INS_FSABS = 86;; +let _M68K_INS_FDABS = 87;; +let _M68K_INS_FACOS = 88;; +let _M68K_INS_FADD = 89;; +let _M68K_INS_FSADD = 90;; +let _M68K_INS_FDADD = 91;; +let _M68K_INS_FASIN = 92;; +let _M68K_INS_FATAN = 93;; +let _M68K_INS_FATANH = 94;; +let _M68K_INS_FBF = 95;; +let _M68K_INS_FBEQ = 96;; +let _M68K_INS_FBOGT = 97;; +let _M68K_INS_FBOGE = 98;; +let _M68K_INS_FBOLT = 99;; +let _M68K_INS_FBOLE = 100;; +let _M68K_INS_FBOGL = 101;; +let _M68K_INS_FBOR = 102;; +let _M68K_INS_FBUN = 103;; +let _M68K_INS_FBUEQ = 104;; +let _M68K_INS_FBUGT = 105;; +let _M68K_INS_FBUGE = 106;; +let _M68K_INS_FBULT = 107;; +let _M68K_INS_FBULE = 108;; +let _M68K_INS_FBNE = 109;; +let _M68K_INS_FBT = 110;; +let _M68K_INS_FBSF = 111;; +let _M68K_INS_FBSEQ = 112;; +let _M68K_INS_FBGT = 113;; +let _M68K_INS_FBGE = 114;; +let _M68K_INS_FBLT = 115;; +let _M68K_INS_FBLE = 116;; +let _M68K_INS_FBGL = 117;; +let _M68K_INS_FBGLE = 118;; +let _M68K_INS_FBNGLE = 119;; +let _M68K_INS_FBNGL = 120;; +let _M68K_INS_FBNLE = 121;; +let _M68K_INS_FBNLT = 122;; +let _M68K_INS_FBNGE = 123;; +let _M68K_INS_FBNGT = 124;; +let _M68K_INS_FBSNE = 125;; +let _M68K_INS_FBST = 126;; +let _M68K_INS_FCMP = 127;; +let _M68K_INS_FCOS = 128;; +let _M68K_INS_FCOSH = 129;; +let _M68K_INS_FDBF = 130;; +let _M68K_INS_FDBEQ = 131;; +let _M68K_INS_FDBOGT = 132;; +let _M68K_INS_FDBOGE = 133;; +let _M68K_INS_FDBOLT = 134;; +let _M68K_INS_FDBOLE = 135;; +let _M68K_INS_FDBOGL = 136;; +let _M68K_INS_FDBOR = 137;; +let _M68K_INS_FDBUN = 138;; +let _M68K_INS_FDBUEQ = 139;; +let _M68K_INS_FDBUGT = 140;; +let _M68K_INS_FDBUGE = 141;; +let _M68K_INS_FDBULT = 142;; +let _M68K_INS_FDBULE = 143;; +let _M68K_INS_FDBNE = 144;; +let _M68K_INS_FDBT = 145;; +let _M68K_INS_FDBSF = 146;; +let _M68K_INS_FDBSEQ = 147;; +let _M68K_INS_FDBGT = 148;; +let _M68K_INS_FDBGE = 149;; +let _M68K_INS_FDBLT = 150;; +let _M68K_INS_FDBLE = 151;; +let _M68K_INS_FDBGL = 152;; +let _M68K_INS_FDBGLE = 153;; +let _M68K_INS_FDBNGLE = 154;; +let _M68K_INS_FDBNGL = 155;; +let _M68K_INS_FDBNLE = 156;; +let _M68K_INS_FDBNLT = 157;; +let _M68K_INS_FDBNGE = 158;; +let _M68K_INS_FDBNGT = 159;; +let _M68K_INS_FDBSNE = 160;; +let _M68K_INS_FDBST = 161;; +let _M68K_INS_FDIV = 162;; +let _M68K_INS_FSDIV = 163;; +let _M68K_INS_FDDIV = 164;; +let _M68K_INS_FETOX = 165;; +let _M68K_INS_FETOXM1 = 166;; +let _M68K_INS_FGETEXP = 167;; +let _M68K_INS_FGETMAN = 168;; +let _M68K_INS_FINT = 169;; +let _M68K_INS_FINTRZ = 170;; +let _M68K_INS_FLOG10 = 171;; +let _M68K_INS_FLOG2 = 172;; +let _M68K_INS_FLOGN = 173;; +let _M68K_INS_FLOGNP1 = 174;; +let _M68K_INS_FMOD = 175;; +let _M68K_INS_FMOVE = 176;; +let _M68K_INS_FSMOVE = 177;; +let _M68K_INS_FDMOVE = 178;; +let _M68K_INS_FMOVECR = 179;; +let _M68K_INS_FMOVEM = 180;; +let _M68K_INS_FMUL = 181;; +let _M68K_INS_FSMUL = 182;; +let _M68K_INS_FDMUL = 183;; +let _M68K_INS_FNEG = 184;; +let _M68K_INS_FSNEG = 185;; +let _M68K_INS_FDNEG = 186;; +let _M68K_INS_FNOP = 187;; +let _M68K_INS_FREM = 188;; +let _M68K_INS_FRESTORE = 189;; +let _M68K_INS_FSAVE = 190;; +let _M68K_INS_FSCALE = 191;; +let _M68K_INS_FSGLDIV = 192;; +let _M68K_INS_FSGLMUL = 193;; +let _M68K_INS_FSIN = 194;; +let _M68K_INS_FSINCOS = 195;; +let _M68K_INS_FSINH = 196;; +let _M68K_INS_FSQRT = 197;; +let _M68K_INS_FSSQRT = 198;; +let _M68K_INS_FDSQRT = 199;; +let _M68K_INS_FSF = 200;; +let _M68K_INS_FSBEQ = 201;; +let _M68K_INS_FSOGT = 202;; +let _M68K_INS_FSOGE = 203;; +let _M68K_INS_FSOLT = 204;; +let _M68K_INS_FSOLE = 205;; +let _M68K_INS_FSOGL = 206;; +let _M68K_INS_FSOR = 207;; +let _M68K_INS_FSUN = 208;; +let _M68K_INS_FSUEQ = 209;; +let _M68K_INS_FSUGT = 210;; +let _M68K_INS_FSUGE = 211;; +let _M68K_INS_FSULT = 212;; +let _M68K_INS_FSULE = 213;; +let _M68K_INS_FSNE = 214;; +let _M68K_INS_FST = 215;; +let _M68K_INS_FSSF = 216;; +let _M68K_INS_FSSEQ = 217;; +let _M68K_INS_FSGT = 218;; +let _M68K_INS_FSGE = 219;; +let _M68K_INS_FSLT = 220;; +let _M68K_INS_FSLE = 221;; +let _M68K_INS_FSGL = 222;; +let _M68K_INS_FSGLE = 223;; +let _M68K_INS_FSNGLE = 224;; +let _M68K_INS_FSNGL = 225;; +let _M68K_INS_FSNLE = 226;; +let _M68K_INS_FSNLT = 227;; +let _M68K_INS_FSNGE = 228;; +let _M68K_INS_FSNGT = 229;; +let _M68K_INS_FSSNE = 230;; +let _M68K_INS_FSST = 231;; +let _M68K_INS_FSUB = 232;; +let _M68K_INS_FSSUB = 233;; +let _M68K_INS_FDSUB = 234;; +let _M68K_INS_FTAN = 235;; +let _M68K_INS_FTANH = 236;; +let _M68K_INS_FTENTOX = 237;; +let _M68K_INS_FTRAPF = 238;; +let _M68K_INS_FTRAPEQ = 239;; +let _M68K_INS_FTRAPOGT = 240;; +let _M68K_INS_FTRAPOGE = 241;; +let _M68K_INS_FTRAPOLT = 242;; +let _M68K_INS_FTRAPOLE = 243;; +let _M68K_INS_FTRAPOGL = 244;; +let _M68K_INS_FTRAPOR = 245;; +let _M68K_INS_FTRAPUN = 246;; +let _M68K_INS_FTRAPUEQ = 247;; +let _M68K_INS_FTRAPUGT = 248;; +let _M68K_INS_FTRAPUGE = 249;; +let _M68K_INS_FTRAPULT = 250;; +let _M68K_INS_FTRAPULE = 251;; +let _M68K_INS_FTRAPNE = 252;; +let _M68K_INS_FTRAPT = 253;; +let _M68K_INS_FTRAPSF = 254;; +let _M68K_INS_FTRAPSEQ = 255;; +let _M68K_INS_FTRAPGT = 256;; +let _M68K_INS_FTRAPGE = 257;; +let _M68K_INS_FTRAPLT = 258;; +let _M68K_INS_FTRAPLE = 259;; +let _M68K_INS_FTRAPGL = 260;; +let _M68K_INS_FTRAPGLE = 261;; +let _M68K_INS_FTRAPNGLE = 262;; +let _M68K_INS_FTRAPNGL = 263;; +let _M68K_INS_FTRAPNLE = 264;; +let _M68K_INS_FTRAPNLT = 265;; +let _M68K_INS_FTRAPNGE = 266;; +let _M68K_INS_FTRAPNGT = 267;; +let _M68K_INS_FTRAPSNE = 268;; +let _M68K_INS_FTRAPST = 269;; +let _M68K_INS_FTST = 270;; +let _M68K_INS_FTWOTOX = 271;; +let _M68K_INS_HALT = 272;; +let _M68K_INS_ILLEGAL = 273;; +let _M68K_INS_JMP = 274;; +let _M68K_INS_JSR = 275;; +let _M68K_INS_LEA = 276;; +let _M68K_INS_LINK = 277;; +let _M68K_INS_LPSTOP = 278;; +let _M68K_INS_LSL = 279;; +let _M68K_INS_LSR = 280;; +let _M68K_INS_MOVE = 281;; +let _M68K_INS_MOVEA = 282;; +let _M68K_INS_MOVEC = 283;; +let _M68K_INS_MOVEM = 284;; +let _M68K_INS_MOVEP = 285;; +let _M68K_INS_MOVEQ = 286;; +let _M68K_INS_MOVES = 287;; +let _M68K_INS_MOVE16 = 288;; +let _M68K_INS_MULS = 289;; +let _M68K_INS_MULU = 290;; +let _M68K_INS_NBCD = 291;; +let _M68K_INS_NEG = 292;; +let _M68K_INS_NEGX = 293;; +let _M68K_INS_NOP = 294;; +let _M68K_INS_NOT = 295;; +let _M68K_INS_OR = 296;; +let _M68K_INS_ORI = 297;; +let _M68K_INS_PACK = 298;; +let _M68K_INS_PEA = 299;; +let _M68K_INS_PFLUSH = 300;; +let _M68K_INS_PFLUSHA = 301;; +let _M68K_INS_PFLUSHAN = 302;; +let _M68K_INS_PFLUSHN = 303;; +let _M68K_INS_PLOADR = 304;; +let _M68K_INS_PLOADW = 305;; +let _M68K_INS_PLPAR = 306;; +let _M68K_INS_PLPAW = 307;; +let _M68K_INS_PMOVE = 308;; +let _M68K_INS_PMOVEFD = 309;; +let _M68K_INS_PTESTR = 310;; +let _M68K_INS_PTESTW = 311;; +let _M68K_INS_PULSE = 312;; +let _M68K_INS_REMS = 313;; +let _M68K_INS_REMU = 314;; +let _M68K_INS_RESET = 315;; +let _M68K_INS_ROL = 316;; +let _M68K_INS_ROR = 317;; +let _M68K_INS_ROXL = 318;; +let _M68K_INS_ROXR = 319;; +let _M68K_INS_RTD = 320;; +let _M68K_INS_RTE = 321;; +let _M68K_INS_RTM = 322;; +let _M68K_INS_RTR = 323;; +let _M68K_INS_RTS = 324;; +let _M68K_INS_SBCD = 325;; +let _M68K_INS_ST = 326;; +let _M68K_INS_SF = 327;; +let _M68K_INS_SHI = 328;; +let _M68K_INS_SLS = 329;; +let _M68K_INS_SCC = 330;; +let _M68K_INS_SHS = 331;; +let _M68K_INS_SCS = 332;; +let _M68K_INS_SLO = 333;; +let _M68K_INS_SNE = 334;; +let _M68K_INS_SEQ = 335;; +let _M68K_INS_SVC = 336;; +let _M68K_INS_SVS = 337;; +let _M68K_INS_SPL = 338;; +let _M68K_INS_SMI = 339;; +let _M68K_INS_SGE = 340;; +let _M68K_INS_SLT = 341;; +let _M68K_INS_SGT = 342;; +let _M68K_INS_SLE = 343;; +let _M68K_INS_STOP = 344;; +let _M68K_INS_SUB = 345;; +let _M68K_INS_SUBA = 346;; +let _M68K_INS_SUBI = 347;; +let _M68K_INS_SUBQ = 348;; +let _M68K_INS_SUBX = 349;; +let _M68K_INS_SWAP = 350;; +let _M68K_INS_TAS = 351;; +let _M68K_INS_TRAP = 352;; +let _M68K_INS_TRAPV = 353;; +let _M68K_INS_TRAPT = 354;; +let _M68K_INS_TRAPF = 355;; +let _M68K_INS_TRAPHI = 356;; +let _M68K_INS_TRAPLS = 357;; +let _M68K_INS_TRAPCC = 358;; +let _M68K_INS_TRAPHS = 359;; +let _M68K_INS_TRAPCS = 360;; +let _M68K_INS_TRAPLO = 361;; +let _M68K_INS_TRAPNE = 362;; +let _M68K_INS_TRAPEQ = 363;; +let _M68K_INS_TRAPVC = 364;; +let _M68K_INS_TRAPVS = 365;; +let _M68K_INS_TRAPPL = 366;; +let _M68K_INS_TRAPMI = 367;; +let _M68K_INS_TRAPGE = 368;; +let _M68K_INS_TRAPLT = 369;; +let _M68K_INS_TRAPGT = 370;; +let _M68K_INS_TRAPLE = 371;; +let _M68K_INS_TST = 372;; +let _M68K_INS_UNLK = 373;; +let _M68K_INS_UNPK = 374;; +let _M68K_INS_ENDING = 375;; + +let _M68K_GRP_INVALID = 0;; +let _M68K_GRP_JUMP = 1;; +let _M68K_GRP_RET = 3;; +let _M68K_GRP_IRET = 5;; +let _M68K_GRP_BRANCH_RELATIVE = 7;; +let _M68K_GRP_ENDING = 8;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/mips.ml b/white_patch_detect/capstone-master/bindings/ocaml/mips.ml new file mode 100644 index 0000000..f0995e3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/mips.ml @@ -0,0 +1,24 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Mips_const + +(* architecture specific info of instruction *) +type mips_op_mem = { + base: int; + disp: int +} + +type mips_op_value = + | MIPS_OP_INVALID of int + | MIPS_OP_REG of int + | MIPS_OP_IMM of int + | MIPS_OP_MEM of mips_op_mem + +type mips_op = { + value: mips_op_value; +} + +type cs_mips = { + operands: mips_op array; +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/mips_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/mips_const.ml new file mode 100644 index 0000000..e0b581b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/mips_const.ml @@ -0,0 +1,861 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.ml] *) + +let _MIPS_OP_INVALID = 0;; +let _MIPS_OP_REG = 1;; +let _MIPS_OP_IMM = 2;; +let _MIPS_OP_MEM = 3;; + +let _MIPS_REG_INVALID = 0;; +let _MIPS_REG_PC = 1;; +let _MIPS_REG_0 = 2;; +let _MIPS_REG_1 = 3;; +let _MIPS_REG_2 = 4;; +let _MIPS_REG_3 = 5;; +let _MIPS_REG_4 = 6;; +let _MIPS_REG_5 = 7;; +let _MIPS_REG_6 = 8;; +let _MIPS_REG_7 = 9;; +let _MIPS_REG_8 = 10;; +let _MIPS_REG_9 = 11;; +let _MIPS_REG_10 = 12;; +let _MIPS_REG_11 = 13;; +let _MIPS_REG_12 = 14;; +let _MIPS_REG_13 = 15;; +let _MIPS_REG_14 = 16;; +let _MIPS_REG_15 = 17;; +let _MIPS_REG_16 = 18;; +let _MIPS_REG_17 = 19;; +let _MIPS_REG_18 = 20;; +let _MIPS_REG_19 = 21;; +let _MIPS_REG_20 = 22;; +let _MIPS_REG_21 = 23;; +let _MIPS_REG_22 = 24;; +let _MIPS_REG_23 = 25;; +let _MIPS_REG_24 = 26;; +let _MIPS_REG_25 = 27;; +let _MIPS_REG_26 = 28;; +let _MIPS_REG_27 = 29;; +let _MIPS_REG_28 = 30;; +let _MIPS_REG_29 = 31;; +let _MIPS_REG_30 = 32;; +let _MIPS_REG_31 = 33;; +let _MIPS_REG_DSPCCOND = 34;; +let _MIPS_REG_DSPCARRY = 35;; +let _MIPS_REG_DSPEFI = 36;; +let _MIPS_REG_DSPOUTFLAG = 37;; +let _MIPS_REG_DSPOUTFLAG16_19 = 38;; +let _MIPS_REG_DSPOUTFLAG20 = 39;; +let _MIPS_REG_DSPOUTFLAG21 = 40;; +let _MIPS_REG_DSPOUTFLAG22 = 41;; +let _MIPS_REG_DSPOUTFLAG23 = 42;; +let _MIPS_REG_DSPPOS = 43;; +let _MIPS_REG_DSPSCOUNT = 44;; +let _MIPS_REG_AC0 = 45;; +let _MIPS_REG_AC1 = 46;; +let _MIPS_REG_AC2 = 47;; +let _MIPS_REG_AC3 = 48;; +let _MIPS_REG_CC0 = 49;; +let _MIPS_REG_CC1 = 50;; +let _MIPS_REG_CC2 = 51;; +let _MIPS_REG_CC3 = 52;; +let _MIPS_REG_CC4 = 53;; +let _MIPS_REG_CC5 = 54;; +let _MIPS_REG_CC6 = 55;; +let _MIPS_REG_CC7 = 56;; +let _MIPS_REG_F0 = 57;; +let _MIPS_REG_F1 = 58;; +let _MIPS_REG_F2 = 59;; +let _MIPS_REG_F3 = 60;; +let _MIPS_REG_F4 = 61;; +let _MIPS_REG_F5 = 62;; +let _MIPS_REG_F6 = 63;; +let _MIPS_REG_F7 = 64;; +let _MIPS_REG_F8 = 65;; +let _MIPS_REG_F9 = 66;; +let _MIPS_REG_F10 = 67;; +let _MIPS_REG_F11 = 68;; +let _MIPS_REG_F12 = 69;; +let _MIPS_REG_F13 = 70;; +let _MIPS_REG_F14 = 71;; +let _MIPS_REG_F15 = 72;; +let _MIPS_REG_F16 = 73;; +let _MIPS_REG_F17 = 74;; +let _MIPS_REG_F18 = 75;; +let _MIPS_REG_F19 = 76;; +let _MIPS_REG_F20 = 77;; +let _MIPS_REG_F21 = 78;; +let _MIPS_REG_F22 = 79;; +let _MIPS_REG_F23 = 80;; +let _MIPS_REG_F24 = 81;; +let _MIPS_REG_F25 = 82;; +let _MIPS_REG_F26 = 83;; +let _MIPS_REG_F27 = 84;; +let _MIPS_REG_F28 = 85;; +let _MIPS_REG_F29 = 86;; +let _MIPS_REG_F30 = 87;; +let _MIPS_REG_F31 = 88;; +let _MIPS_REG_FCC0 = 89;; +let _MIPS_REG_FCC1 = 90;; +let _MIPS_REG_FCC2 = 91;; +let _MIPS_REG_FCC3 = 92;; +let _MIPS_REG_FCC4 = 93;; +let _MIPS_REG_FCC5 = 94;; +let _MIPS_REG_FCC6 = 95;; +let _MIPS_REG_FCC7 = 96;; +let _MIPS_REG_W0 = 97;; +let _MIPS_REG_W1 = 98;; +let _MIPS_REG_W2 = 99;; +let _MIPS_REG_W3 = 100;; +let _MIPS_REG_W4 = 101;; +let _MIPS_REG_W5 = 102;; +let _MIPS_REG_W6 = 103;; +let _MIPS_REG_W7 = 104;; +let _MIPS_REG_W8 = 105;; +let _MIPS_REG_W9 = 106;; +let _MIPS_REG_W10 = 107;; +let _MIPS_REG_W11 = 108;; +let _MIPS_REG_W12 = 109;; +let _MIPS_REG_W13 = 110;; +let _MIPS_REG_W14 = 111;; +let _MIPS_REG_W15 = 112;; +let _MIPS_REG_W16 = 113;; +let _MIPS_REG_W17 = 114;; +let _MIPS_REG_W18 = 115;; +let _MIPS_REG_W19 = 116;; +let _MIPS_REG_W20 = 117;; +let _MIPS_REG_W21 = 118;; +let _MIPS_REG_W22 = 119;; +let _MIPS_REG_W23 = 120;; +let _MIPS_REG_W24 = 121;; +let _MIPS_REG_W25 = 122;; +let _MIPS_REG_W26 = 123;; +let _MIPS_REG_W27 = 124;; +let _MIPS_REG_W28 = 125;; +let _MIPS_REG_W29 = 126;; +let _MIPS_REG_W30 = 127;; +let _MIPS_REG_W31 = 128;; +let _MIPS_REG_HI = 129;; +let _MIPS_REG_LO = 130;; +let _MIPS_REG_P0 = 131;; +let _MIPS_REG_P1 = 132;; +let _MIPS_REG_P2 = 133;; +let _MIPS_REG_MPL0 = 134;; +let _MIPS_REG_MPL1 = 135;; +let _MIPS_REG_MPL2 = 136;; +let _MIPS_REG_ENDING = 137;; +let _MIPS_REG_ZERO = _MIPS_REG_0;; +let _MIPS_REG_AT = _MIPS_REG_1;; +let _MIPS_REG_V0 = _MIPS_REG_2;; +let _MIPS_REG_V1 = _MIPS_REG_3;; +let _MIPS_REG_A0 = _MIPS_REG_4;; +let _MIPS_REG_A1 = _MIPS_REG_5;; +let _MIPS_REG_A2 = _MIPS_REG_6;; +let _MIPS_REG_A3 = _MIPS_REG_7;; +let _MIPS_REG_T0 = _MIPS_REG_8;; +let _MIPS_REG_T1 = _MIPS_REG_9;; +let _MIPS_REG_T2 = _MIPS_REG_10;; +let _MIPS_REG_T3 = _MIPS_REG_11;; +let _MIPS_REG_T4 = _MIPS_REG_12;; +let _MIPS_REG_T5 = _MIPS_REG_13;; +let _MIPS_REG_T6 = _MIPS_REG_14;; +let _MIPS_REG_T7 = _MIPS_REG_15;; +let _MIPS_REG_S0 = _MIPS_REG_16;; +let _MIPS_REG_S1 = _MIPS_REG_17;; +let _MIPS_REG_S2 = _MIPS_REG_18;; +let _MIPS_REG_S3 = _MIPS_REG_19;; +let _MIPS_REG_S4 = _MIPS_REG_20;; +let _MIPS_REG_S5 = _MIPS_REG_21;; +let _MIPS_REG_S6 = _MIPS_REG_22;; +let _MIPS_REG_S7 = _MIPS_REG_23;; +let _MIPS_REG_T8 = _MIPS_REG_24;; +let _MIPS_REG_T9 = _MIPS_REG_25;; +let _MIPS_REG_K0 = _MIPS_REG_26;; +let _MIPS_REG_K1 = _MIPS_REG_27;; +let _MIPS_REG_GP = _MIPS_REG_28;; +let _MIPS_REG_SP = _MIPS_REG_29;; +let _MIPS_REG_FP = _MIPS_REG_30;; +let _MIPS_REG_S8 = _MIPS_REG_30;; +let _MIPS_REG_RA = _MIPS_REG_31;; +let _MIPS_REG_HI0 = _MIPS_REG_AC0;; +let _MIPS_REG_HI1 = _MIPS_REG_AC1;; +let _MIPS_REG_HI2 = _MIPS_REG_AC2;; +let _MIPS_REG_HI3 = _MIPS_REG_AC3;; +let _MIPS_REG_LO0 = _MIPS_REG_HI0;; +let _MIPS_REG_LO1 = _MIPS_REG_HI1;; +let _MIPS_REG_LO2 = _MIPS_REG_HI2;; +let _MIPS_REG_LO3 = _MIPS_REG_HI3;; + +let _MIPS_INS_INVALID = 0;; +let _MIPS_INS_ABSQ_S = 1;; +let _MIPS_INS_ADD = 2;; +let _MIPS_INS_ADDIUPC = 3;; +let _MIPS_INS_ADDIUR1SP = 4;; +let _MIPS_INS_ADDIUR2 = 5;; +let _MIPS_INS_ADDIUS5 = 6;; +let _MIPS_INS_ADDIUSP = 7;; +let _MIPS_INS_ADDQH = 8;; +let _MIPS_INS_ADDQH_R = 9;; +let _MIPS_INS_ADDQ = 10;; +let _MIPS_INS_ADDQ_S = 11;; +let _MIPS_INS_ADDSC = 12;; +let _MIPS_INS_ADDS_A = 13;; +let _MIPS_INS_ADDS_S = 14;; +let _MIPS_INS_ADDS_U = 15;; +let _MIPS_INS_ADDU16 = 16;; +let _MIPS_INS_ADDUH = 17;; +let _MIPS_INS_ADDUH_R = 18;; +let _MIPS_INS_ADDU = 19;; +let _MIPS_INS_ADDU_S = 20;; +let _MIPS_INS_ADDVI = 21;; +let _MIPS_INS_ADDV = 22;; +let _MIPS_INS_ADDWC = 23;; +let _MIPS_INS_ADD_A = 24;; +let _MIPS_INS_ADDI = 25;; +let _MIPS_INS_ADDIU = 26;; +let _MIPS_INS_ALIGN = 27;; +let _MIPS_INS_ALUIPC = 28;; +let _MIPS_INS_AND = 29;; +let _MIPS_INS_AND16 = 30;; +let _MIPS_INS_ANDI16 = 31;; +let _MIPS_INS_ANDI = 32;; +let _MIPS_INS_APPEND = 33;; +let _MIPS_INS_ASUB_S = 34;; +let _MIPS_INS_ASUB_U = 35;; +let _MIPS_INS_AUI = 36;; +let _MIPS_INS_AUIPC = 37;; +let _MIPS_INS_AVER_S = 38;; +let _MIPS_INS_AVER_U = 39;; +let _MIPS_INS_AVE_S = 40;; +let _MIPS_INS_AVE_U = 41;; +let _MIPS_INS_B16 = 42;; +let _MIPS_INS_BADDU = 43;; +let _MIPS_INS_BAL = 44;; +let _MIPS_INS_BALC = 45;; +let _MIPS_INS_BALIGN = 46;; +let _MIPS_INS_BBIT0 = 47;; +let _MIPS_INS_BBIT032 = 48;; +let _MIPS_INS_BBIT1 = 49;; +let _MIPS_INS_BBIT132 = 50;; +let _MIPS_INS_BC = 51;; +let _MIPS_INS_BC0F = 52;; +let _MIPS_INS_BC0FL = 53;; +let _MIPS_INS_BC0T = 54;; +let _MIPS_INS_BC0TL = 55;; +let _MIPS_INS_BC1EQZ = 56;; +let _MIPS_INS_BC1F = 57;; +let _MIPS_INS_BC1FL = 58;; +let _MIPS_INS_BC1NEZ = 59;; +let _MIPS_INS_BC1T = 60;; +let _MIPS_INS_BC1TL = 61;; +let _MIPS_INS_BC2EQZ = 62;; +let _MIPS_INS_BC2F = 63;; +let _MIPS_INS_BC2FL = 64;; +let _MIPS_INS_BC2NEZ = 65;; +let _MIPS_INS_BC2T = 66;; +let _MIPS_INS_BC2TL = 67;; +let _MIPS_INS_BC3F = 68;; +let _MIPS_INS_BC3FL = 69;; +let _MIPS_INS_BC3T = 70;; +let _MIPS_INS_BC3TL = 71;; +let _MIPS_INS_BCLRI = 72;; +let _MIPS_INS_BCLR = 73;; +let _MIPS_INS_BEQ = 74;; +let _MIPS_INS_BEQC = 75;; +let _MIPS_INS_BEQL = 76;; +let _MIPS_INS_BEQZ16 = 77;; +let _MIPS_INS_BEQZALC = 78;; +let _MIPS_INS_BEQZC = 79;; +let _MIPS_INS_BGEC = 80;; +let _MIPS_INS_BGEUC = 81;; +let _MIPS_INS_BGEZ = 82;; +let _MIPS_INS_BGEZAL = 83;; +let _MIPS_INS_BGEZALC = 84;; +let _MIPS_INS_BGEZALL = 85;; +let _MIPS_INS_BGEZALS = 86;; +let _MIPS_INS_BGEZC = 87;; +let _MIPS_INS_BGEZL = 88;; +let _MIPS_INS_BGTZ = 89;; +let _MIPS_INS_BGTZALC = 90;; +let _MIPS_INS_BGTZC = 91;; +let _MIPS_INS_BGTZL = 92;; +let _MIPS_INS_BINSLI = 93;; +let _MIPS_INS_BINSL = 94;; +let _MIPS_INS_BINSRI = 95;; +let _MIPS_INS_BINSR = 96;; +let _MIPS_INS_BITREV = 97;; +let _MIPS_INS_BITSWAP = 98;; +let _MIPS_INS_BLEZ = 99;; +let _MIPS_INS_BLEZALC = 100;; +let _MIPS_INS_BLEZC = 101;; +let _MIPS_INS_BLEZL = 102;; +let _MIPS_INS_BLTC = 103;; +let _MIPS_INS_BLTUC = 104;; +let _MIPS_INS_BLTZ = 105;; +let _MIPS_INS_BLTZAL = 106;; +let _MIPS_INS_BLTZALC = 107;; +let _MIPS_INS_BLTZALL = 108;; +let _MIPS_INS_BLTZALS = 109;; +let _MIPS_INS_BLTZC = 110;; +let _MIPS_INS_BLTZL = 111;; +let _MIPS_INS_BMNZI = 112;; +let _MIPS_INS_BMNZ = 113;; +let _MIPS_INS_BMZI = 114;; +let _MIPS_INS_BMZ = 115;; +let _MIPS_INS_BNE = 116;; +let _MIPS_INS_BNEC = 117;; +let _MIPS_INS_BNEGI = 118;; +let _MIPS_INS_BNEG = 119;; +let _MIPS_INS_BNEL = 120;; +let _MIPS_INS_BNEZ16 = 121;; +let _MIPS_INS_BNEZALC = 122;; +let _MIPS_INS_BNEZC = 123;; +let _MIPS_INS_BNVC = 124;; +let _MIPS_INS_BNZ = 125;; +let _MIPS_INS_BOVC = 126;; +let _MIPS_INS_BPOSGE32 = 127;; +let _MIPS_INS_BREAK = 128;; +let _MIPS_INS_BREAK16 = 129;; +let _MIPS_INS_BSELI = 130;; +let _MIPS_INS_BSEL = 131;; +let _MIPS_INS_BSETI = 132;; +let _MIPS_INS_BSET = 133;; +let _MIPS_INS_BZ = 134;; +let _MIPS_INS_BEQZ = 135;; +let _MIPS_INS_B = 136;; +let _MIPS_INS_BNEZ = 137;; +let _MIPS_INS_BTEQZ = 138;; +let _MIPS_INS_BTNEZ = 139;; +let _MIPS_INS_CACHE = 140;; +let _MIPS_INS_CEIL = 141;; +let _MIPS_INS_CEQI = 142;; +let _MIPS_INS_CEQ = 143;; +let _MIPS_INS_CFC1 = 144;; +let _MIPS_INS_CFCMSA = 145;; +let _MIPS_INS_CINS = 146;; +let _MIPS_INS_CINS32 = 147;; +let _MIPS_INS_CLASS = 148;; +let _MIPS_INS_CLEI_S = 149;; +let _MIPS_INS_CLEI_U = 150;; +let _MIPS_INS_CLE_S = 151;; +let _MIPS_INS_CLE_U = 152;; +let _MIPS_INS_CLO = 153;; +let _MIPS_INS_CLTI_S = 154;; +let _MIPS_INS_CLTI_U = 155;; +let _MIPS_INS_CLT_S = 156;; +let _MIPS_INS_CLT_U = 157;; +let _MIPS_INS_CLZ = 158;; +let _MIPS_INS_CMPGDU = 159;; +let _MIPS_INS_CMPGU = 160;; +let _MIPS_INS_CMPU = 161;; +let _MIPS_INS_CMP = 162;; +let _MIPS_INS_COPY_S = 163;; +let _MIPS_INS_COPY_U = 164;; +let _MIPS_INS_CTC1 = 165;; +let _MIPS_INS_CTCMSA = 166;; +let _MIPS_INS_CVT = 167;; +let _MIPS_INS_C = 168;; +let _MIPS_INS_CMPI = 169;; +let _MIPS_INS_DADD = 170;; +let _MIPS_INS_DADDI = 171;; +let _MIPS_INS_DADDIU = 172;; +let _MIPS_INS_DADDU = 173;; +let _MIPS_INS_DAHI = 174;; +let _MIPS_INS_DALIGN = 175;; +let _MIPS_INS_DATI = 176;; +let _MIPS_INS_DAUI = 177;; +let _MIPS_INS_DBITSWAP = 178;; +let _MIPS_INS_DCLO = 179;; +let _MIPS_INS_DCLZ = 180;; +let _MIPS_INS_DDIV = 181;; +let _MIPS_INS_DDIVU = 182;; +let _MIPS_INS_DERET = 183;; +let _MIPS_INS_DEXT = 184;; +let _MIPS_INS_DEXTM = 185;; +let _MIPS_INS_DEXTU = 186;; +let _MIPS_INS_DI = 187;; +let _MIPS_INS_DINS = 188;; +let _MIPS_INS_DINSM = 189;; +let _MIPS_INS_DINSU = 190;; +let _MIPS_INS_DIV = 191;; +let _MIPS_INS_DIVU = 192;; +let _MIPS_INS_DIV_S = 193;; +let _MIPS_INS_DIV_U = 194;; +let _MIPS_INS_DLSA = 195;; +let _MIPS_INS_DMFC0 = 196;; +let _MIPS_INS_DMFC1 = 197;; +let _MIPS_INS_DMFC2 = 198;; +let _MIPS_INS_DMOD = 199;; +let _MIPS_INS_DMODU = 200;; +let _MIPS_INS_DMTC0 = 201;; +let _MIPS_INS_DMTC1 = 202;; +let _MIPS_INS_DMTC2 = 203;; +let _MIPS_INS_DMUH = 204;; +let _MIPS_INS_DMUHU = 205;; +let _MIPS_INS_DMUL = 206;; +let _MIPS_INS_DMULT = 207;; +let _MIPS_INS_DMULTU = 208;; +let _MIPS_INS_DMULU = 209;; +let _MIPS_INS_DOTP_S = 210;; +let _MIPS_INS_DOTP_U = 211;; +let _MIPS_INS_DPADD_S = 212;; +let _MIPS_INS_DPADD_U = 213;; +let _MIPS_INS_DPAQX_SA = 214;; +let _MIPS_INS_DPAQX_S = 215;; +let _MIPS_INS_DPAQ_SA = 216;; +let _MIPS_INS_DPAQ_S = 217;; +let _MIPS_INS_DPAU = 218;; +let _MIPS_INS_DPAX = 219;; +let _MIPS_INS_DPA = 220;; +let _MIPS_INS_DPOP = 221;; +let _MIPS_INS_DPSQX_SA = 222;; +let _MIPS_INS_DPSQX_S = 223;; +let _MIPS_INS_DPSQ_SA = 224;; +let _MIPS_INS_DPSQ_S = 225;; +let _MIPS_INS_DPSUB_S = 226;; +let _MIPS_INS_DPSUB_U = 227;; +let _MIPS_INS_DPSU = 228;; +let _MIPS_INS_DPSX = 229;; +let _MIPS_INS_DPS = 230;; +let _MIPS_INS_DROTR = 231;; +let _MIPS_INS_DROTR32 = 232;; +let _MIPS_INS_DROTRV = 233;; +let _MIPS_INS_DSBH = 234;; +let _MIPS_INS_DSHD = 235;; +let _MIPS_INS_DSLL = 236;; +let _MIPS_INS_DSLL32 = 237;; +let _MIPS_INS_DSLLV = 238;; +let _MIPS_INS_DSRA = 239;; +let _MIPS_INS_DSRA32 = 240;; +let _MIPS_INS_DSRAV = 241;; +let _MIPS_INS_DSRL = 242;; +let _MIPS_INS_DSRL32 = 243;; +let _MIPS_INS_DSRLV = 244;; +let _MIPS_INS_DSUB = 245;; +let _MIPS_INS_DSUBU = 246;; +let _MIPS_INS_EHB = 247;; +let _MIPS_INS_EI = 248;; +let _MIPS_INS_ERET = 249;; +let _MIPS_INS_EXT = 250;; +let _MIPS_INS_EXTP = 251;; +let _MIPS_INS_EXTPDP = 252;; +let _MIPS_INS_EXTPDPV = 253;; +let _MIPS_INS_EXTPV = 254;; +let _MIPS_INS_EXTRV_RS = 255;; +let _MIPS_INS_EXTRV_R = 256;; +let _MIPS_INS_EXTRV_S = 257;; +let _MIPS_INS_EXTRV = 258;; +let _MIPS_INS_EXTR_RS = 259;; +let _MIPS_INS_EXTR_R = 260;; +let _MIPS_INS_EXTR_S = 261;; +let _MIPS_INS_EXTR = 262;; +let _MIPS_INS_EXTS = 263;; +let _MIPS_INS_EXTS32 = 264;; +let _MIPS_INS_ABS = 265;; +let _MIPS_INS_FADD = 266;; +let _MIPS_INS_FCAF = 267;; +let _MIPS_INS_FCEQ = 268;; +let _MIPS_INS_FCLASS = 269;; +let _MIPS_INS_FCLE = 270;; +let _MIPS_INS_FCLT = 271;; +let _MIPS_INS_FCNE = 272;; +let _MIPS_INS_FCOR = 273;; +let _MIPS_INS_FCUEQ = 274;; +let _MIPS_INS_FCULE = 275;; +let _MIPS_INS_FCULT = 276;; +let _MIPS_INS_FCUNE = 277;; +let _MIPS_INS_FCUN = 278;; +let _MIPS_INS_FDIV = 279;; +let _MIPS_INS_FEXDO = 280;; +let _MIPS_INS_FEXP2 = 281;; +let _MIPS_INS_FEXUPL = 282;; +let _MIPS_INS_FEXUPR = 283;; +let _MIPS_INS_FFINT_S = 284;; +let _MIPS_INS_FFINT_U = 285;; +let _MIPS_INS_FFQL = 286;; +let _MIPS_INS_FFQR = 287;; +let _MIPS_INS_FILL = 288;; +let _MIPS_INS_FLOG2 = 289;; +let _MIPS_INS_FLOOR = 290;; +let _MIPS_INS_FMADD = 291;; +let _MIPS_INS_FMAX_A = 292;; +let _MIPS_INS_FMAX = 293;; +let _MIPS_INS_FMIN_A = 294;; +let _MIPS_INS_FMIN = 295;; +let _MIPS_INS_MOV = 296;; +let _MIPS_INS_FMSUB = 297;; +let _MIPS_INS_FMUL = 298;; +let _MIPS_INS_MUL = 299;; +let _MIPS_INS_NEG = 300;; +let _MIPS_INS_FRCP = 301;; +let _MIPS_INS_FRINT = 302;; +let _MIPS_INS_FRSQRT = 303;; +let _MIPS_INS_FSAF = 304;; +let _MIPS_INS_FSEQ = 305;; +let _MIPS_INS_FSLE = 306;; +let _MIPS_INS_FSLT = 307;; +let _MIPS_INS_FSNE = 308;; +let _MIPS_INS_FSOR = 309;; +let _MIPS_INS_FSQRT = 310;; +let _MIPS_INS_SQRT = 311;; +let _MIPS_INS_FSUB = 312;; +let _MIPS_INS_SUB = 313;; +let _MIPS_INS_FSUEQ = 314;; +let _MIPS_INS_FSULE = 315;; +let _MIPS_INS_FSULT = 316;; +let _MIPS_INS_FSUNE = 317;; +let _MIPS_INS_FSUN = 318;; +let _MIPS_INS_FTINT_S = 319;; +let _MIPS_INS_FTINT_U = 320;; +let _MIPS_INS_FTQ = 321;; +let _MIPS_INS_FTRUNC_S = 322;; +let _MIPS_INS_FTRUNC_U = 323;; +let _MIPS_INS_HADD_S = 324;; +let _MIPS_INS_HADD_U = 325;; +let _MIPS_INS_HSUB_S = 326;; +let _MIPS_INS_HSUB_U = 327;; +let _MIPS_INS_ILVEV = 328;; +let _MIPS_INS_ILVL = 329;; +let _MIPS_INS_ILVOD = 330;; +let _MIPS_INS_ILVR = 331;; +let _MIPS_INS_INS = 332;; +let _MIPS_INS_INSERT = 333;; +let _MIPS_INS_INSV = 334;; +let _MIPS_INS_INSVE = 335;; +let _MIPS_INS_J = 336;; +let _MIPS_INS_JAL = 337;; +let _MIPS_INS_JALR = 338;; +let _MIPS_INS_JALRS16 = 339;; +let _MIPS_INS_JALRS = 340;; +let _MIPS_INS_JALS = 341;; +let _MIPS_INS_JALX = 342;; +let _MIPS_INS_JIALC = 343;; +let _MIPS_INS_JIC = 344;; +let _MIPS_INS_JR = 345;; +let _MIPS_INS_JR16 = 346;; +let _MIPS_INS_JRADDIUSP = 347;; +let _MIPS_INS_JRC = 348;; +let _MIPS_INS_JALRC = 349;; +let _MIPS_INS_LB = 350;; +let _MIPS_INS_LBU16 = 351;; +let _MIPS_INS_LBUX = 352;; +let _MIPS_INS_LBU = 353;; +let _MIPS_INS_LD = 354;; +let _MIPS_INS_LDC1 = 355;; +let _MIPS_INS_LDC2 = 356;; +let _MIPS_INS_LDC3 = 357;; +let _MIPS_INS_LDI = 358;; +let _MIPS_INS_LDL = 359;; +let _MIPS_INS_LDPC = 360;; +let _MIPS_INS_LDR = 361;; +let _MIPS_INS_LDXC1 = 362;; +let _MIPS_INS_LH = 363;; +let _MIPS_INS_LHU16 = 364;; +let _MIPS_INS_LHX = 365;; +let _MIPS_INS_LHU = 366;; +let _MIPS_INS_LI16 = 367;; +let _MIPS_INS_LL = 368;; +let _MIPS_INS_LLD = 369;; +let _MIPS_INS_LSA = 370;; +let _MIPS_INS_LUXC1 = 371;; +let _MIPS_INS_LUI = 372;; +let _MIPS_INS_LW = 373;; +let _MIPS_INS_LW16 = 374;; +let _MIPS_INS_LWC1 = 375;; +let _MIPS_INS_LWC2 = 376;; +let _MIPS_INS_LWC3 = 377;; +let _MIPS_INS_LWL = 378;; +let _MIPS_INS_LWM16 = 379;; +let _MIPS_INS_LWM32 = 380;; +let _MIPS_INS_LWPC = 381;; +let _MIPS_INS_LWP = 382;; +let _MIPS_INS_LWR = 383;; +let _MIPS_INS_LWUPC = 384;; +let _MIPS_INS_LWU = 385;; +let _MIPS_INS_LWX = 386;; +let _MIPS_INS_LWXC1 = 387;; +let _MIPS_INS_LWXS = 388;; +let _MIPS_INS_LI = 389;; +let _MIPS_INS_MADD = 390;; +let _MIPS_INS_MADDF = 391;; +let _MIPS_INS_MADDR_Q = 392;; +let _MIPS_INS_MADDU = 393;; +let _MIPS_INS_MADDV = 394;; +let _MIPS_INS_MADD_Q = 395;; +let _MIPS_INS_MAQ_SA = 396;; +let _MIPS_INS_MAQ_S = 397;; +let _MIPS_INS_MAXA = 398;; +let _MIPS_INS_MAXI_S = 399;; +let _MIPS_INS_MAXI_U = 400;; +let _MIPS_INS_MAX_A = 401;; +let _MIPS_INS_MAX = 402;; +let _MIPS_INS_MAX_S = 403;; +let _MIPS_INS_MAX_U = 404;; +let _MIPS_INS_MFC0 = 405;; +let _MIPS_INS_MFC1 = 406;; +let _MIPS_INS_MFC2 = 407;; +let _MIPS_INS_MFHC1 = 408;; +let _MIPS_INS_MFHI = 409;; +let _MIPS_INS_MFLO = 410;; +let _MIPS_INS_MINA = 411;; +let _MIPS_INS_MINI_S = 412;; +let _MIPS_INS_MINI_U = 413;; +let _MIPS_INS_MIN_A = 414;; +let _MIPS_INS_MIN = 415;; +let _MIPS_INS_MIN_S = 416;; +let _MIPS_INS_MIN_U = 417;; +let _MIPS_INS_MOD = 418;; +let _MIPS_INS_MODSUB = 419;; +let _MIPS_INS_MODU = 420;; +let _MIPS_INS_MOD_S = 421;; +let _MIPS_INS_MOD_U = 422;; +let _MIPS_INS_MOVE = 423;; +let _MIPS_INS_MOVEP = 424;; +let _MIPS_INS_MOVF = 425;; +let _MIPS_INS_MOVN = 426;; +let _MIPS_INS_MOVT = 427;; +let _MIPS_INS_MOVZ = 428;; +let _MIPS_INS_MSUB = 429;; +let _MIPS_INS_MSUBF = 430;; +let _MIPS_INS_MSUBR_Q = 431;; +let _MIPS_INS_MSUBU = 432;; +let _MIPS_INS_MSUBV = 433;; +let _MIPS_INS_MSUB_Q = 434;; +let _MIPS_INS_MTC0 = 435;; +let _MIPS_INS_MTC1 = 436;; +let _MIPS_INS_MTC2 = 437;; +let _MIPS_INS_MTHC1 = 438;; +let _MIPS_INS_MTHI = 439;; +let _MIPS_INS_MTHLIP = 440;; +let _MIPS_INS_MTLO = 441;; +let _MIPS_INS_MTM0 = 442;; +let _MIPS_INS_MTM1 = 443;; +let _MIPS_INS_MTM2 = 444;; +let _MIPS_INS_MTP0 = 445;; +let _MIPS_INS_MTP1 = 446;; +let _MIPS_INS_MTP2 = 447;; +let _MIPS_INS_MUH = 448;; +let _MIPS_INS_MUHU = 449;; +let _MIPS_INS_MULEQ_S = 450;; +let _MIPS_INS_MULEU_S = 451;; +let _MIPS_INS_MULQ_RS = 452;; +let _MIPS_INS_MULQ_S = 453;; +let _MIPS_INS_MULR_Q = 454;; +let _MIPS_INS_MULSAQ_S = 455;; +let _MIPS_INS_MULSA = 456;; +let _MIPS_INS_MULT = 457;; +let _MIPS_INS_MULTU = 458;; +let _MIPS_INS_MULU = 459;; +let _MIPS_INS_MULV = 460;; +let _MIPS_INS_MUL_Q = 461;; +let _MIPS_INS_MUL_S = 462;; +let _MIPS_INS_NLOC = 463;; +let _MIPS_INS_NLZC = 464;; +let _MIPS_INS_NMADD = 465;; +let _MIPS_INS_NMSUB = 466;; +let _MIPS_INS_NOR = 467;; +let _MIPS_INS_NORI = 468;; +let _MIPS_INS_NOT16 = 469;; +let _MIPS_INS_NOT = 470;; +let _MIPS_INS_OR = 471;; +let _MIPS_INS_OR16 = 472;; +let _MIPS_INS_ORI = 473;; +let _MIPS_INS_PACKRL = 474;; +let _MIPS_INS_PAUSE = 475;; +let _MIPS_INS_PCKEV = 476;; +let _MIPS_INS_PCKOD = 477;; +let _MIPS_INS_PCNT = 478;; +let _MIPS_INS_PICK = 479;; +let _MIPS_INS_POP = 480;; +let _MIPS_INS_PRECEQU = 481;; +let _MIPS_INS_PRECEQ = 482;; +let _MIPS_INS_PRECEU = 483;; +let _MIPS_INS_PRECRQU_S = 484;; +let _MIPS_INS_PRECRQ = 485;; +let _MIPS_INS_PRECRQ_RS = 486;; +let _MIPS_INS_PRECR = 487;; +let _MIPS_INS_PRECR_SRA = 488;; +let _MIPS_INS_PRECR_SRA_R = 489;; +let _MIPS_INS_PREF = 490;; +let _MIPS_INS_PREPEND = 491;; +let _MIPS_INS_RADDU = 492;; +let _MIPS_INS_RDDSP = 493;; +let _MIPS_INS_RDHWR = 494;; +let _MIPS_INS_REPLV = 495;; +let _MIPS_INS_REPL = 496;; +let _MIPS_INS_RINT = 497;; +let _MIPS_INS_ROTR = 498;; +let _MIPS_INS_ROTRV = 499;; +let _MIPS_INS_ROUND = 500;; +let _MIPS_INS_SAT_S = 501;; +let _MIPS_INS_SAT_U = 502;; +let _MIPS_INS_SB = 503;; +let _MIPS_INS_SB16 = 504;; +let _MIPS_INS_SC = 505;; +let _MIPS_INS_SCD = 506;; +let _MIPS_INS_SD = 507;; +let _MIPS_INS_SDBBP = 508;; +let _MIPS_INS_SDBBP16 = 509;; +let _MIPS_INS_SDC1 = 510;; +let _MIPS_INS_SDC2 = 511;; +let _MIPS_INS_SDC3 = 512;; +let _MIPS_INS_SDL = 513;; +let _MIPS_INS_SDR = 514;; +let _MIPS_INS_SDXC1 = 515;; +let _MIPS_INS_SEB = 516;; +let _MIPS_INS_SEH = 517;; +let _MIPS_INS_SELEQZ = 518;; +let _MIPS_INS_SELNEZ = 519;; +let _MIPS_INS_SEL = 520;; +let _MIPS_INS_SEQ = 521;; +let _MIPS_INS_SEQI = 522;; +let _MIPS_INS_SH = 523;; +let _MIPS_INS_SH16 = 524;; +let _MIPS_INS_SHF = 525;; +let _MIPS_INS_SHILO = 526;; +let _MIPS_INS_SHILOV = 527;; +let _MIPS_INS_SHLLV = 528;; +let _MIPS_INS_SHLLV_S = 529;; +let _MIPS_INS_SHLL = 530;; +let _MIPS_INS_SHLL_S = 531;; +let _MIPS_INS_SHRAV = 532;; +let _MIPS_INS_SHRAV_R = 533;; +let _MIPS_INS_SHRA = 534;; +let _MIPS_INS_SHRA_R = 535;; +let _MIPS_INS_SHRLV = 536;; +let _MIPS_INS_SHRL = 537;; +let _MIPS_INS_SLDI = 538;; +let _MIPS_INS_SLD = 539;; +let _MIPS_INS_SLL = 540;; +let _MIPS_INS_SLL16 = 541;; +let _MIPS_INS_SLLI = 542;; +let _MIPS_INS_SLLV = 543;; +let _MIPS_INS_SLT = 544;; +let _MIPS_INS_SLTI = 545;; +let _MIPS_INS_SLTIU = 546;; +let _MIPS_INS_SLTU = 547;; +let _MIPS_INS_SNE = 548;; +let _MIPS_INS_SNEI = 549;; +let _MIPS_INS_SPLATI = 550;; +let _MIPS_INS_SPLAT = 551;; +let _MIPS_INS_SRA = 552;; +let _MIPS_INS_SRAI = 553;; +let _MIPS_INS_SRARI = 554;; +let _MIPS_INS_SRAR = 555;; +let _MIPS_INS_SRAV = 556;; +let _MIPS_INS_SRL = 557;; +let _MIPS_INS_SRL16 = 558;; +let _MIPS_INS_SRLI = 559;; +let _MIPS_INS_SRLRI = 560;; +let _MIPS_INS_SRLR = 561;; +let _MIPS_INS_SRLV = 562;; +let _MIPS_INS_SSNOP = 563;; +let _MIPS_INS_ST = 564;; +let _MIPS_INS_SUBQH = 565;; +let _MIPS_INS_SUBQH_R = 566;; +let _MIPS_INS_SUBQ = 567;; +let _MIPS_INS_SUBQ_S = 568;; +let _MIPS_INS_SUBSUS_U = 569;; +let _MIPS_INS_SUBSUU_S = 570;; +let _MIPS_INS_SUBS_S = 571;; +let _MIPS_INS_SUBS_U = 572;; +let _MIPS_INS_SUBU16 = 573;; +let _MIPS_INS_SUBUH = 574;; +let _MIPS_INS_SUBUH_R = 575;; +let _MIPS_INS_SUBU = 576;; +let _MIPS_INS_SUBU_S = 577;; +let _MIPS_INS_SUBVI = 578;; +let _MIPS_INS_SUBV = 579;; +let _MIPS_INS_SUXC1 = 580;; +let _MIPS_INS_SW = 581;; +let _MIPS_INS_SW16 = 582;; +let _MIPS_INS_SWC1 = 583;; +let _MIPS_INS_SWC2 = 584;; +let _MIPS_INS_SWC3 = 585;; +let _MIPS_INS_SWL = 586;; +let _MIPS_INS_SWM16 = 587;; +let _MIPS_INS_SWM32 = 588;; +let _MIPS_INS_SWP = 589;; +let _MIPS_INS_SWR = 590;; +let _MIPS_INS_SWXC1 = 591;; +let _MIPS_INS_SYNC = 592;; +let _MIPS_INS_SYNCI = 593;; +let _MIPS_INS_SYSCALL = 594;; +let _MIPS_INS_TEQ = 595;; +let _MIPS_INS_TEQI = 596;; +let _MIPS_INS_TGE = 597;; +let _MIPS_INS_TGEI = 598;; +let _MIPS_INS_TGEIU = 599;; +let _MIPS_INS_TGEU = 600;; +let _MIPS_INS_TLBP = 601;; +let _MIPS_INS_TLBR = 602;; +let _MIPS_INS_TLBWI = 603;; +let _MIPS_INS_TLBWR = 604;; +let _MIPS_INS_TLT = 605;; +let _MIPS_INS_TLTI = 606;; +let _MIPS_INS_TLTIU = 607;; +let _MIPS_INS_TLTU = 608;; +let _MIPS_INS_TNE = 609;; +let _MIPS_INS_TNEI = 610;; +let _MIPS_INS_TRUNC = 611;; +let _MIPS_INS_V3MULU = 612;; +let _MIPS_INS_VMM0 = 613;; +let _MIPS_INS_VMULU = 614;; +let _MIPS_INS_VSHF = 615;; +let _MIPS_INS_WAIT = 616;; +let _MIPS_INS_WRDSP = 617;; +let _MIPS_INS_WSBH = 618;; +let _MIPS_INS_XOR = 619;; +let _MIPS_INS_XOR16 = 620;; +let _MIPS_INS_XORI = 621;; + +(* some alias instructions *) +let _MIPS_INS_NOP = 622;; +let _MIPS_INS_NEGU = 623;; + +(* special instructions *) +let _MIPS_INS_JALR_HB = 624;; +let _MIPS_INS_JR_HB = 625;; +let _MIPS_INS_ENDING = 626;; + +let _MIPS_GRP_INVALID = 0;; +let _MIPS_GRP_JUMP = 1;; +let _MIPS_GRP_CALL = 2;; +let _MIPS_GRP_RET = 3;; +let _MIPS_GRP_INT = 4;; +let _MIPS_GRP_IRET = 5;; +let _MIPS_GRP_PRIVILEGE = 6;; +let _MIPS_GRP_BRANCH_RELATIVE = 7;; +let _MIPS_GRP_BITCOUNT = 128;; +let _MIPS_GRP_DSP = 129;; +let _MIPS_GRP_DSPR2 = 130;; +let _MIPS_GRP_FPIDX = 131;; +let _MIPS_GRP_MSA = 132;; +let _MIPS_GRP_MIPS32R2 = 133;; +let _MIPS_GRP_MIPS64 = 134;; +let _MIPS_GRP_MIPS64R2 = 135;; +let _MIPS_GRP_SEINREG = 136;; +let _MIPS_GRP_STDENC = 137;; +let _MIPS_GRP_SWAP = 138;; +let _MIPS_GRP_MICROMIPS = 139;; +let _MIPS_GRP_MIPS16MODE = 140;; +let _MIPS_GRP_FP64BIT = 141;; +let _MIPS_GRP_NONANSFPMATH = 142;; +let _MIPS_GRP_NOTFP64BIT = 143;; +let _MIPS_GRP_NOTINMICROMIPS = 144;; +let _MIPS_GRP_NOTNACL = 145;; +let _MIPS_GRP_NOTMIPS32R6 = 146;; +let _MIPS_GRP_NOTMIPS64R6 = 147;; +let _MIPS_GRP_CNMIPS = 148;; +let _MIPS_GRP_MIPS32 = 149;; +let _MIPS_GRP_MIPS32R6 = 150;; +let _MIPS_GRP_MIPS64R6 = 151;; +let _MIPS_GRP_MIPS2 = 152;; +let _MIPS_GRP_MIPS3 = 153;; +let _MIPS_GRP_MIPS3_32 = 154;; +let _MIPS_GRP_MIPS3_32R2 = 155;; +let _MIPS_GRP_MIPS4_32 = 156;; +let _MIPS_GRP_MIPS4_32R2 = 157;; +let _MIPS_GRP_MIPS5_32R2 = 158;; +let _MIPS_GRP_GP32BIT = 159;; +let _MIPS_GRP_GP64BIT = 160;; +let _MIPS_GRP_ENDING = 161;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/ocaml.c b/white_patch_detect/capstone-master/bindings/ocaml/ocaml.c new file mode 100644 index 0000000..74cc731 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/ocaml.c @@ -0,0 +1,1105 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013> */ + +#include // debug +#include +#include +#include +#include +#include + +#include "capstone/capstone.h" + +#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) + + +// count the number of positive members in @list +static unsigned int list_count(uint8_t *list, unsigned int max) +{ + unsigned int i; + + for(i = 0; i < max; i++) + if (list[i] == 0) + return i; + + return max; +} + +CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t code_len, uint64_t addr, size_t count) +{ + CAMLparam0(); + CAMLlocal5(list, cons, rec_insn, array, tmp); + CAMLlocal4(arch_info, op_info_val, tmp2, tmp3); + cs_insn *insn; + size_t c; + + list = Val_emptylist; + + c = cs_disasm(handle, code, code_len, addr, count, &insn); + if (c) { + //printf("Found %lu insn, addr: %lx\n", c, addr); + uint64_t j; + for (j = c; j > 0; j--) { + unsigned int lcount, i; + cons = caml_alloc(2, 0); + + rec_insn = caml_alloc(10, 0); + Store_field(rec_insn, 0, Val_int(insn[j-1].id)); + Store_field(rec_insn, 1, Val_int(insn[j-1].address)); + Store_field(rec_insn, 2, Val_int(insn[j-1].size)); + + // copy raw bytes of instruction + lcount = insn[j-1].size; + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].bytes[i])); + } + } else + array = Atom(0); // empty list + Store_field(rec_insn, 3, array); + + Store_field(rec_insn, 4, caml_copy_string(insn[j-1].mnemonic)); + Store_field(rec_insn, 5, caml_copy_string(insn[j-1].op_str)); + + // copy read registers + if (insn[0].detail) { + lcount = (insn[j-1]).detail->regs_read_count; + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].detail->regs_read[i])); + } + } else + array = Atom(0); // empty list + } else + array = Atom(0); // empty list + Store_field(rec_insn, 6, array); + + if (insn[0].detail) { + lcount = (insn[j-1]).detail->regs_write_count; + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].detail->regs_write[i])); + } + } else + array = Atom(0); // empty list + } else + array = Atom(0); // empty list + Store_field(rec_insn, 7, array); + + if (insn[0].detail) { + lcount = (insn[j-1]).detail->groups_count; + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].detail->groups[i])); + } + } else + array = Atom(0); // empty list + } else + array = Atom(0); // empty list + Store_field(rec_insn, 8, array); + + if (insn[j-1].detail) { + switch(arch) { + case CS_ARCH_ARM: + arch_info = caml_alloc(1, 0); + + op_info_val = caml_alloc(10, 0); + Store_field(op_info_val, 0, Val_bool(insn[j-1].detail->arm.usermode)); + Store_field(op_info_val, 1, Val_int(insn[j-1].detail->arm.vector_size)); + Store_field(op_info_val, 2, Val_int(insn[j-1].detail->arm.vector_data)); + Store_field(op_info_val, 3, Val_int(insn[j-1].detail->arm.cps_mode)); + Store_field(op_info_val, 4, Val_int(insn[j-1].detail->arm.cps_flag)); + Store_field(op_info_val, 5, Val_int(insn[j-1].detail->arm.cc)); + Store_field(op_info_val, 6, Val_bool(insn[j-1].detail->arm.update_flags)); + Store_field(op_info_val, 7, Val_bool(insn[j-1].detail->arm.writeback)); + Store_field(op_info_val, 8, Val_int(insn[j-1].detail->arm.mem_barrier)); + + lcount = insn[j-1].detail->arm.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(6, 0); + switch(insn[j-1].detail->arm.operands[i].type) { + case ARM_OP_REG: + case ARM_OP_SYSREG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].reg)); + break; + case ARM_OP_CIMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); + break; + case ARM_OP_PIMM: + tmp = caml_alloc(1, 3); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); + break; + case ARM_OP_IMM: + tmp = caml_alloc(1, 4); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); + break; + case ARM_OP_FP: + tmp = caml_alloc(1, 5); + Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm.operands[i].fp)); + break; + case ARM_OP_MEM: + tmp = caml_alloc(1, 6); + tmp3 = caml_alloc(5, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].mem.index)); + Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm.operands[i].mem.scale)); + Store_field(tmp3, 3, Val_int(insn[j-1].detail->arm.operands[i].mem.disp)); + Store_field(tmp3, 4, Val_int(insn[j-1].detail->arm.operands[i].mem.lshift)); + Store_field(tmp, 0, tmp3); + break; + case ARM_OP_SETEND: + tmp = caml_alloc(1, 7); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].setend)); + break; + default: break; + } + tmp3 = caml_alloc(2, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].shift.type)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].shift.value)); + Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm.operands[i].vector_index)); + Store_field(tmp2, 1, tmp3); + Store_field(tmp2, 2, tmp); + Store_field(tmp2, 3, Val_bool(insn[j-1].detail->arm.operands[i].subtracted)); + Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm.operands[i].access)); + Store_field(tmp2, 5, Val_int(insn[j-1].detail->arm.operands[i].neon_lane)); + Store_field(array, i, tmp2); + } + } else // empty list + array = Atom(0); + + Store_field(op_info_val, 9, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + case CS_ARCH_ARM64: + arch_info = caml_alloc(1, 1); + + op_info_val = caml_alloc(4, 0); + Store_field(op_info_val, 0, Val_int(insn[j-1].detail->arm64.cc)); + Store_field(op_info_val, 1, Val_bool(insn[j-1].detail->arm64.update_flags)); + Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->arm64.writeback)); + + lcount = insn[j-1].detail->arm64.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(6, 0); + switch(insn[j-1].detail->arm64.operands[i].type) { + case ARM64_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); + break; + case ARM64_OP_CIMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm)); + break; + case ARM64_OP_IMM: + tmp = caml_alloc(1, 3); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm)); + break; + case ARM64_OP_FP: + tmp = caml_alloc(1, 4); + Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm64.operands[i].fp)); + break; + case ARM64_OP_MEM: + tmp = caml_alloc(1, 5); + tmp3 = caml_alloc(3, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].mem.index)); + Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm64.operands[i].mem.disp)); + Store_field(tmp, 0, tmp3); + break; + case ARM64_OP_REG_MRS: + tmp = caml_alloc(1, 6); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); + break; + case ARM64_OP_REG_MSR: + tmp = caml_alloc(1, 7); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); + break; + case ARM64_OP_PSTATE: + tmp = caml_alloc(1, 8); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].pstate)); + break; + case ARM64_OP_SYS: + tmp = caml_alloc(1, 9); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].sys)); + break; + case ARM64_OP_PREFETCH: + tmp = caml_alloc(1, 10); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].prefetch)); + break; + case ARM64_OP_BARRIER: + tmp = caml_alloc(1, 11); + Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].barrier)); + break; + default: break; + } + tmp3 = caml_alloc(2, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].shift.type)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].shift.value)); + + Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm64.operands[i].vector_index)); + Store_field(tmp2, 1, Val_int(insn[j-1].detail->arm64.operands[i].vas)); + Store_field(tmp2, 2, Val_int(insn[j-1].detail->arm64.operands[i].vess)); + Store_field(tmp2, 3, tmp3); + Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm64.operands[i].ext)); + Store_field(tmp2, 5, tmp); + + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 3, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + case CS_ARCH_MIPS: + arch_info = caml_alloc(1, 2); + + op_info_val = caml_alloc(1, 0); + + lcount = insn[j-1].detail->mips.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(1, 0); + switch(insn[j-1].detail->mips.operands[i].type) { + case MIPS_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].reg)); + break; + case MIPS_OP_IMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].imm)); + break; + case MIPS_OP_MEM: + tmp = caml_alloc(1, 3); + tmp3 = caml_alloc(2, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->mips.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->mips.operands[i].mem.disp)); + Store_field(tmp, 0, tmp3); + break; + default: break; + } + Store_field(tmp2, 0, tmp); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 0, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + case CS_ARCH_X86: + arch_info = caml_alloc(1, 3); + + op_info_val = caml_alloc(17, 0); + + // fill prefix + lcount = list_count(insn[j-1].detail->x86.prefix, ARR_SIZE(insn[j-1].detail->x86.prefix)); + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].detail->x86.prefix[i])); + } + } else + array = Atom(0); + Store_field(op_info_val, 0, array); + + // fill opcode + lcount = list_count(insn[j-1].detail->x86.opcode, ARR_SIZE(insn[j-1].detail->x86.opcode)); + if (lcount) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + Store_field(array, i, Val_int(insn[j-1].detail->x86.opcode[i])); + } + } else + array = Atom(0); + Store_field(op_info_val, 1, array); + + Store_field(op_info_val, 2, Val_int(insn[j-1].detail->x86.rex)); + + Store_field(op_info_val, 3, Val_int(insn[j-1].detail->x86.addr_size)); + + Store_field(op_info_val, 4, Val_int(insn[j-1].detail->x86.modrm)); + + Store_field(op_info_val, 5, Val_int(insn[j-1].detail->x86.sib)); + + Store_field(op_info_val, 6, Val_int(insn[j-1].detail->x86.disp)); + + Store_field(op_info_val, 7, Val_int(insn[j-1].detail->x86.sib_index)); + + Store_field(op_info_val, 8, Val_int(insn[j-1].detail->x86.sib_scale)); + + Store_field(op_info_val, 9, Val_int(insn[j-1].detail->x86.sib_base)); + + Store_field(op_info_val, 10, Val_int(insn[j-1].detail->x86.xop_cc)); + Store_field(op_info_val, 11, Val_int(insn[j-1].detail->x86.sse_cc)); + Store_field(op_info_val, 12, Val_int(insn[j-1].detail->x86.avx_cc)); + Store_field(op_info_val, 13, Val_int(insn[j-1].detail->x86.avx_sae)); + Store_field(op_info_val, 14, Val_int(insn[j-1].detail->x86.avx_rm)); + Store_field(op_info_val, 15, Val_int(insn[j-1].detail->x86.eflags)); + + lcount = insn[j-1].detail->x86.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + switch(insn[j-1].detail->x86.operands[i].type) { + case X86_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].reg)); + break; + case X86_OP_IMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm)); + break; + case X86_OP_MEM: + tmp = caml_alloc(1, 3); + tmp2 = caml_alloc(5, 0); + Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment)); + Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base)); + Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].mem.index)); + Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].mem.scale)); + Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].mem.disp)); + + Store_field(tmp, 0, tmp2); + break; + default: + tmp = caml_alloc(1, 0); // X86_OP_INVALID + break; + } + + tmp2 = caml_alloc(5, 0); + Store_field(tmp2, 0, tmp); + Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].size)); + Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].access)); + Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast)); + Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask)); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + Store_field(op_info_val, 16, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + break; + + case CS_ARCH_PPC: + arch_info = caml_alloc(1, 4); + + op_info_val = caml_alloc(4, 0); + + Store_field(op_info_val, 0, Val_int(insn[j-1].detail->ppc.bc)); + Store_field(op_info_val, 1, Val_int(insn[j-1].detail->ppc.bh)); + Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->ppc.update_cr0)); + + lcount = insn[j-1].detail->ppc.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(1, 0); + switch(insn[j-1].detail->ppc.operands[i].type) { + case PPC_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].reg)); + break; + case PPC_OP_IMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].imm)); + break; + case PPC_OP_MEM: + tmp = caml_alloc(1, 3); + tmp3 = caml_alloc(2, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].mem.disp)); + Store_field(tmp, 0, tmp3); + break; + case PPC_OP_CRX: + tmp = caml_alloc(1, 4); + tmp3 = caml_alloc(3, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].crx.scale)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].crx.reg)); + Store_field(tmp3, 2, Val_int(insn[j-1].detail->ppc.operands[i].crx.cond)); + Store_field(tmp, 0, tmp3); + break; + default: break; + } + Store_field(tmp2, 0, tmp); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 3, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + + case CS_ARCH_SPARC: + arch_info = caml_alloc(1, 5); + + op_info_val = caml_alloc(3, 0); + + Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sparc.cc)); + Store_field(op_info_val, 1, Val_int(insn[j-1].detail->sparc.hint)); + + lcount = insn[j-1].detail->sparc.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(1, 0); + switch(insn[j-1].detail->sparc.operands[i].type) { + case SPARC_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].reg)); + break; + case SPARC_OP_IMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].imm)); + break; + case SPARC_OP_MEM: + tmp = caml_alloc(1, 3); + tmp3 = caml_alloc(3, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->sparc.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->sparc.operands[i].mem.index)); + Store_field(tmp3, 2, Val_int(insn[j-1].detail->sparc.operands[i].mem.disp)); + Store_field(tmp, 0, tmp3); + break; + default: break; + } + Store_field(tmp2, 0, tmp); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 2, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + + case CS_ARCH_SYSZ: + arch_info = caml_alloc(1, 6); + + op_info_val = caml_alloc(2, 0); + + Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sysz.cc)); + + lcount = insn[j-1].detail->sysz.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(1, 0); + switch(insn[j-1].detail->sysz.operands[i].type) { + case SYSZ_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg)); + break; + case SYSZ_OP_ACREG: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg)); + break; + case SYSZ_OP_IMM: + tmp = caml_alloc(1, 3); + Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].imm)); + break; + case SYSZ_OP_MEM: + tmp = caml_alloc(1, 4); + tmp3 = caml_alloc(4, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->sysz.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->sysz.operands[i].mem.index)); + Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.length)); + Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.disp)); + Store_field(tmp, 0, tmp3); + break; + default: break; + } + Store_field(tmp2, 0, tmp); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 1, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + + case CS_ARCH_XCORE: + arch_info = caml_alloc(1, 7); + + op_info_val = caml_alloc(1, 0); + + lcount = insn[j-1].detail->xcore.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(1, 0); + switch(insn[j-1].detail->xcore.operands[i].type) { + case XCORE_OP_REG: + tmp = caml_alloc(1, 1); + Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].reg)); + break; + case XCORE_OP_IMM: + tmp = caml_alloc(1, 2); + Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].imm)); + break; + case XCORE_OP_MEM: + tmp = caml_alloc(1, 3); + tmp3 = caml_alloc(4, 0); + Store_field(tmp3, 0, Val_int(insn[j-1].detail->xcore.operands[i].mem.base)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->xcore.operands[i].mem.index)); + Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.disp)); + Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.direct)); + Store_field(tmp, 0, tmp3); + break; + default: break; + } + Store_field(tmp2, 0, tmp); + Store_field(array, i, tmp2); + } + } else // empty array + array = Atom(0); + + Store_field(op_info_val, 0, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + + case CS_ARCH_M680X: + arch_info = caml_alloc(1, 8); + + op_info_val = caml_alloc(2, 0); // struct cs_m680x + Store_field(op_info_val, 0, Val_int(insn[j-1].detail->m680x.flags)); + + lcount = insn[j-1].detail->m680x.op_count; + if (lcount > 0) { + array = caml_alloc(lcount, 0); + for (i = 0; i < lcount; i++) { + tmp2 = caml_alloc(3, 0); // m680x_op + switch(insn[j-1].detail->m680x.operands[i].type) { + case M680X_OP_IMMEDIATE: + tmp = caml_alloc(1, 1); // imm + Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].imm)); + break; + case M680X_OP_REGISTER: + tmp = caml_alloc(1, 2); // reg + Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].reg)); + break; + case M680X_OP_INDEXED: + tmp = caml_alloc(1, 3); + tmp3 = caml_alloc(7, 0); // m680x_op_idx + Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].idx.base_reg)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_reg)); + Store_field(tmp3, 2, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset)); + Store_field(tmp3, 3, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_addr)); + Store_field(tmp3, 4, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_bits)); + Store_field(tmp3, 5, Val_int(insn[j-1].detail->m680x.operands[i].idx.inc_dec)); + Store_field(tmp3, 6, Val_int(insn[j-1].detail->m680x.operands[i].idx.flags)); + Store_field(tmp, 0, tmp3); + break; + case M680X_OP_RELATIVE: + tmp = caml_alloc(1, 4); + tmp3 = caml_alloc(2, 0); // m680x_op_rel + Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].rel.address)); + Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].rel.offset)); + Store_field(tmp, 0, tmp3); + break; + case M680X_OP_EXTENDED: + tmp = caml_alloc(1, 5); + tmp3 = caml_alloc(2, 0); // m680x_op_ext + Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].ext.address)); + Store_field(tmp3, 1, Val_bool(insn[j-1].detail->m680x.operands[i].ext.indirect)); + Store_field(tmp, 0, tmp3); + break; + case M680X_OP_DIRECT: + tmp = caml_alloc(1, 6); // direct_addr + Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].direct_addr)); + break; + case M680X_OP_CONSTANT: + tmp = caml_alloc(1, 7); // const_val + Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].const_val)); + break; + default: break; + } + Store_field(tmp2, 0, tmp); // add union + Store_field(tmp2, 1, Val_int(insn[j-1].detail->m680x.operands[i].size)); + Store_field(tmp2, 2, Val_int(insn[j-1].detail->m680x.operands[i].access)); + Store_field(array, i, tmp2); // add operand to operand array + } + } else // empty list + array = Atom(0); + + Store_field(op_info_val, 1, array); + + // finally, insert this into arch_info + Store_field(arch_info, 0, op_info_val); + + Store_field(rec_insn, 9, arch_info); + + break; + + default: break; + } + } + + Store_field(cons, 0, rec_insn); // head + Store_field(cons, 1, list); // tail + list = cons; + } + cs_free(insn, count); + } + + // do not free the handle here + //cs_close(&handle); + CAMLreturn(list); +} + +CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _addr, value _count) +{ + CAMLparam5(_arch, _mode, _code, _addr, _count); + CAMLlocal1(head); + csh handle; + cs_arch arch; + cs_mode mode = 0; + const uint8_t *code; + uint64_t addr; + size_t count, code_len; + + switch (Int_val(_arch)) { + case 0: + arch = CS_ARCH_ARM; + break; + case 1: + arch = CS_ARCH_ARM64; + break; + case 2: + arch = CS_ARCH_MIPS; + break; + case 3: + arch = CS_ARCH_X86; + break; + case 4: + arch = CS_ARCH_PPC; + break; + case 5: + arch = CS_ARCH_SPARC; + break; + case 6: + arch = CS_ARCH_SYSZ; + break; + case 7: + arch = CS_ARCH_XCORE; + break; + case 8: + arch = CS_ARCH_M68K; + break; + case 9: + arch = CS_ARCH_TMS320C64X; + break; + case 10: + arch = CS_ARCH_M680X; + break; + default: + caml_invalid_argument("Invalid arch"); + return Val_emptylist; + } + + while (_mode != Val_emptylist) { + head = Field(_mode, 0); /* accessing the head */ + switch (Int_val(head)) { + case 0: + mode |= CS_MODE_LITTLE_ENDIAN; + break; + case 1: + mode |= CS_MODE_ARM; + break; + case 2: + mode |= CS_MODE_16; + break; + case 3: + mode |= CS_MODE_32; + break; + case 4: + mode |= CS_MODE_64; + break; + case 5: + mode |= CS_MODE_THUMB; + break; + case 6: + mode |= CS_MODE_MCLASS; + break; + case 7: + mode |= CS_MODE_V8; + break; + case 8: + mode |= CS_MODE_MICRO; + break; + case 9: + mode |= CS_MODE_MIPS3; + break; + case 10: + mode |= CS_MODE_MIPS32R6; + break; + case 11: + mode |= CS_MODE_MIPS2; + break; + case 12: + mode |= CS_MODE_V9; + break; + case 13: + mode |= CS_MODE_BIG_ENDIAN; + break; + case 14: + mode |= CS_MODE_MIPS32; + break; + case 15: + mode |= CS_MODE_MIPS64; + break; + case 16: + mode |= CS_MODE_QPX; + break; + case 17: + mode |= CS_MODE_M680X_6301; + break; + case 18: + mode |= CS_MODE_M680X_6309; + break; + case 19: + mode |= CS_MODE_M680X_6800; + break; + case 20: + mode |= CS_MODE_M680X_6801; + break; + case 21: + mode |= CS_MODE_M680X_6805; + break; + case 22: + mode |= CS_MODE_M680X_6808; + break; + case 23: + mode |= CS_MODE_M680X_6809; + break; + case 24: + mode |= CS_MODE_M680X_6811; + break; + case 25: + mode |= CS_MODE_M680X_CPU12; + break; + case 26: + mode |= CS_MODE_M680X_HCS08; + break; + default: + caml_invalid_argument("Invalid mode"); + return Val_emptylist; + } + _mode = Field(_mode, 1); /* point to the tail for next loop */ + } + + cs_err ret = cs_open(arch, mode, &handle); + if (ret != CS_ERR_OK) { + return Val_emptylist; + } + + code = (uint8_t *)String_val(_code); + code_len = caml_string_length(_code); + addr = Int64_val(_addr); + count = Int64_val(_count); + + CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count)); +} + +CAMLprim value ocaml_cs_disasm_internal(value _arch, value _handle, value _code, value _addr, value _count) +{ + CAMLparam5(_arch, _handle, _code, _addr, _count); + csh handle; + cs_arch arch; + const uint8_t *code; + uint64_t addr, count, code_len; + + handle = Int64_val(_handle); + + arch = Int_val(_arch); + code = (uint8_t *)String_val(_code); + code_len = caml_string_length(_code); + addr = Int64_val(_addr); + count = Int64_val(_count); + + CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count)); +} + +CAMLprim value ocaml_open(value _arch, value _mode) +{ + CAMLparam2(_arch, _mode); + CAMLlocal2(list, head); + csh handle; + cs_arch arch; + cs_mode mode = 0; + + list = Val_emptylist; + + switch (Int_val(_arch)) { + case 0: + arch = CS_ARCH_ARM; + break; + case 1: + arch = CS_ARCH_ARM64; + break; + case 2: + arch = CS_ARCH_MIPS; + break; + case 3: + arch = CS_ARCH_X86; + break; + case 4: + arch = CS_ARCH_PPC; + break; + case 5: + arch = CS_ARCH_SPARC; + break; + case 6: + arch = CS_ARCH_SYSZ; + break; + case 7: + arch = CS_ARCH_XCORE; + break; + case 8: + arch = CS_ARCH_M68K; + break; + case 9: + arch = CS_ARCH_TMS320C64X; + break; + case 10: + arch = CS_ARCH_M680X; + break; + default: + caml_invalid_argument("Invalid arch"); + return Val_emptylist; + } + + + while (_mode != Val_emptylist) { + head = Field(_mode, 0); /* accessing the head */ + switch (Int_val(head)) { + case 0: + mode |= CS_MODE_LITTLE_ENDIAN; + break; + case 1: + mode |= CS_MODE_ARM; + break; + case 2: + mode |= CS_MODE_16; + break; + case 3: + mode |= CS_MODE_32; + break; + case 4: + mode |= CS_MODE_64; + break; + case 5: + mode |= CS_MODE_THUMB; + break; + case 6: + mode |= CS_MODE_MCLASS; + break; + case 7: + mode |= CS_MODE_V8; + break; + case 8: + mode |= CS_MODE_MICRO; + break; + case 9: + mode |= CS_MODE_MIPS3; + break; + case 10: + mode |= CS_MODE_MIPS32R6; + break; + case 11: + mode |= CS_MODE_MIPS2; + break; + case 12: + mode |= CS_MODE_V9; + break; + case 13: + mode |= CS_MODE_BIG_ENDIAN; + break; + case 14: + mode |= CS_MODE_MIPS32; + break; + case 15: + mode |= CS_MODE_MIPS64; + break; + case 16: + mode |= CS_MODE_QPX; + break; + case 17: + mode |= CS_MODE_M680X_6301; + break; + case 18: + mode |= CS_MODE_M680X_6309; + break; + case 19: + mode |= CS_MODE_M680X_6800; + break; + case 20: + mode |= CS_MODE_M680X_6801; + break; + case 21: + mode |= CS_MODE_M680X_6805; + break; + case 22: + mode |= CS_MODE_M680X_6808; + break; + case 23: + mode |= CS_MODE_M680X_6809; + break; + case 24: + mode |= CS_MODE_M680X_6811; + break; + case 25: + mode |= CS_MODE_M680X_CPU12; + break; + case 26: + mode |= CS_MODE_M680X_HCS08; + break; + default: + caml_invalid_argument("Invalid mode"); + return Val_emptylist; + } + _mode = Field(_mode, 1); /* point to the tail for next loop */ + } + + if (cs_open(arch, mode, &handle) != 0) + CAMLreturn(Val_int(0)); + + CAMLlocal1(result); + result = caml_alloc(1, 0); + Store_field(result, 0, caml_copy_int64(handle)); + CAMLreturn(result); +} + +CAMLprim value ocaml_option(value _handle, value _opt, value _value) +{ + CAMLparam3(_handle, _opt, _value); + cs_opt_type opt; + int err; + + switch (Int_val(_opt)) { + case 0: + opt = CS_OPT_SYNTAX; + break; + case 1: + opt = CS_OPT_DETAIL; + break; + case 2: + opt = CS_OPT_MODE; + break; + case 3: + opt = CS_OPT_MEM; + break; + case 4: + opt = CS_OPT_SKIPDATA; + break; + case 5: + opt = CS_OPT_SKIPDATA_SETUP; + break; + default: + caml_invalid_argument("Invalid option"); + CAMLreturn(Val_int(CS_ERR_OPTION)); + } + + err = cs_option(Int64_val(_handle), opt, Int64_val(_value)); + + CAMLreturn(Val_int(err)); +} + +CAMLprim value ocaml_register_name(value _handle, value _reg) +{ + const char *name = cs_reg_name(Int64_val(_handle), Int_val(_reg)); + if (!name) { + caml_invalid_argument("invalid reg_id"); + name = "invalid"; + } + + return caml_copy_string(name); +} + +CAMLprim value ocaml_instruction_name(value _handle, value _insn) +{ + const char *name = cs_insn_name(Int64_val(_handle), Int_val(_insn)); + if (!name) { + caml_invalid_argument("invalid insn_id"); + name = "invalid"; + } + + return caml_copy_string(name); +} + +CAMLprim value ocaml_group_name(value _handle, value _insn) +{ + const char *name = cs_group_name(Int64_val(_handle), Int_val(_insn)); + if (!name) { + caml_invalid_argument("invalid insn_id"); + name = "invalid"; + } + + return caml_copy_string(name); +} + +CAMLprim value ocaml_version(void) +{ + int version = cs_version(NULL, NULL); + return Val_int(version); +} + +CAMLprim value ocaml_close(value _handle) +{ + CAMLparam1(_handle); + csh h; + + h = Int64_val(_handle); + + CAMLreturn(Val_int(cs_close(&h))); +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/ppc.ml b/white_patch_detect/capstone-master/bindings/ocaml/ppc.ml new file mode 100644 index 0000000..269bfcc --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/ppc.ml @@ -0,0 +1,34 @@ +(* Capstone Disassembly Engine + * By Guillaume Jeanne , 2014> *) + +open Ppc_const + +type ppc_op_mem = { + base: int; + disp: int; +} + +type ppc_op_crx = { + scale: int; + reg: int; + cond: int; +} + +type ppc_op_value = + | PPC_OP_INVALID of int + | PPC_OP_REG of int + | PPC_OP_IMM of int + | PPC_OP_MEM of ppc_op_mem + | PPC_OP_CRX of ppc_op_crx + +type ppc_op = { + value: ppc_op_value; +} + +type cs_ppc = { + bc: int; + bh: int; + update_cr0: bool; + operands: ppc_op array; +} + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/ppc_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/ppc_const.ml new file mode 100644 index 0000000..457cfa2 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/ppc_const.ml @@ -0,0 +1,1365 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.ml] *) + +let _PPC_BC_INVALID = 0;; +let _PPC_BC_LT = (0 lsl 5) lor 12;; +let _PPC_BC_LE = (1 lsl 5) lor 4;; +let _PPC_BC_EQ = (2 lsl 5) lor 12;; +let _PPC_BC_GE = (0 lsl 5) lor 4;; +let _PPC_BC_GT = (1 lsl 5) lor 12;; +let _PPC_BC_NE = (2 lsl 5) lor 4;; +let _PPC_BC_UN = (3 lsl 5) lor 12;; +let _PPC_BC_NU = (3 lsl 5) lor 4;; +let _PPC_BC_SO = (4 lsl 5) lor 12;; +let _PPC_BC_NS = (4 lsl 5) lor 4;; + +let _PPC_BH_INVALID = 0;; +let _PPC_BH_PLUS = 1;; +let _PPC_BH_MINUS = 2;; + +let _PPC_OP_INVALID = 0;; +let _PPC_OP_REG = 1;; +let _PPC_OP_IMM = 2;; +let _PPC_OP_MEM = 3;; +let _PPC_OP_CRX = 64;; + +let _PPC_REG_INVALID = 0;; +let _PPC_REG_CARRY = 1;; +let _PPC_REG_CR0 = 2;; +let _PPC_REG_CR1 = 3;; +let _PPC_REG_CR2 = 4;; +let _PPC_REG_CR3 = 5;; +let _PPC_REG_CR4 = 6;; +let _PPC_REG_CR5 = 7;; +let _PPC_REG_CR6 = 8;; +let _PPC_REG_CR7 = 9;; +let _PPC_REG_CTR = 10;; +let _PPC_REG_F0 = 11;; +let _PPC_REG_F1 = 12;; +let _PPC_REG_F2 = 13;; +let _PPC_REG_F3 = 14;; +let _PPC_REG_F4 = 15;; +let _PPC_REG_F5 = 16;; +let _PPC_REG_F6 = 17;; +let _PPC_REG_F7 = 18;; +let _PPC_REG_F8 = 19;; +let _PPC_REG_F9 = 20;; +let _PPC_REG_F10 = 21;; +let _PPC_REG_F11 = 22;; +let _PPC_REG_F12 = 23;; +let _PPC_REG_F13 = 24;; +let _PPC_REG_F14 = 25;; +let _PPC_REG_F15 = 26;; +let _PPC_REG_F16 = 27;; +let _PPC_REG_F17 = 28;; +let _PPC_REG_F18 = 29;; +let _PPC_REG_F19 = 30;; +let _PPC_REG_F20 = 31;; +let _PPC_REG_F21 = 32;; +let _PPC_REG_F22 = 33;; +let _PPC_REG_F23 = 34;; +let _PPC_REG_F24 = 35;; +let _PPC_REG_F25 = 36;; +let _PPC_REG_F26 = 37;; +let _PPC_REG_F27 = 38;; +let _PPC_REG_F28 = 39;; +let _PPC_REG_F29 = 40;; +let _PPC_REG_F30 = 41;; +let _PPC_REG_F31 = 42;; +let _PPC_REG_LR = 43;; +let _PPC_REG_R0 = 44;; +let _PPC_REG_R1 = 45;; +let _PPC_REG_R2 = 46;; +let _PPC_REG_R3 = 47;; +let _PPC_REG_R4 = 48;; +let _PPC_REG_R5 = 49;; +let _PPC_REG_R6 = 50;; +let _PPC_REG_R7 = 51;; +let _PPC_REG_R8 = 52;; +let _PPC_REG_R9 = 53;; +let _PPC_REG_R10 = 54;; +let _PPC_REG_R11 = 55;; +let _PPC_REG_R12 = 56;; +let _PPC_REG_R13 = 57;; +let _PPC_REG_R14 = 58;; +let _PPC_REG_R15 = 59;; +let _PPC_REG_R16 = 60;; +let _PPC_REG_R17 = 61;; +let _PPC_REG_R18 = 62;; +let _PPC_REG_R19 = 63;; +let _PPC_REG_R20 = 64;; +let _PPC_REG_R21 = 65;; +let _PPC_REG_R22 = 66;; +let _PPC_REG_R23 = 67;; +let _PPC_REG_R24 = 68;; +let _PPC_REG_R25 = 69;; +let _PPC_REG_R26 = 70;; +let _PPC_REG_R27 = 71;; +let _PPC_REG_R28 = 72;; +let _PPC_REG_R29 = 73;; +let _PPC_REG_R30 = 74;; +let _PPC_REG_R31 = 75;; +let _PPC_REG_V0 = 76;; +let _PPC_REG_V1 = 77;; +let _PPC_REG_V2 = 78;; +let _PPC_REG_V3 = 79;; +let _PPC_REG_V4 = 80;; +let _PPC_REG_V5 = 81;; +let _PPC_REG_V6 = 82;; +let _PPC_REG_V7 = 83;; +let _PPC_REG_V8 = 84;; +let _PPC_REG_V9 = 85;; +let _PPC_REG_V10 = 86;; +let _PPC_REG_V11 = 87;; +let _PPC_REG_V12 = 88;; +let _PPC_REG_V13 = 89;; +let _PPC_REG_V14 = 90;; +let _PPC_REG_V15 = 91;; +let _PPC_REG_V16 = 92;; +let _PPC_REG_V17 = 93;; +let _PPC_REG_V18 = 94;; +let _PPC_REG_V19 = 95;; +let _PPC_REG_V20 = 96;; +let _PPC_REG_V21 = 97;; +let _PPC_REG_V22 = 98;; +let _PPC_REG_V23 = 99;; +let _PPC_REG_V24 = 100;; +let _PPC_REG_V25 = 101;; +let _PPC_REG_V26 = 102;; +let _PPC_REG_V27 = 103;; +let _PPC_REG_V28 = 104;; +let _PPC_REG_V29 = 105;; +let _PPC_REG_V30 = 106;; +let _PPC_REG_V31 = 107;; +let _PPC_REG_VRSAVE = 108;; +let _PPC_REG_VS0 = 109;; +let _PPC_REG_VS1 = 110;; +let _PPC_REG_VS2 = 111;; +let _PPC_REG_VS3 = 112;; +let _PPC_REG_VS4 = 113;; +let _PPC_REG_VS5 = 114;; +let _PPC_REG_VS6 = 115;; +let _PPC_REG_VS7 = 116;; +let _PPC_REG_VS8 = 117;; +let _PPC_REG_VS9 = 118;; +let _PPC_REG_VS10 = 119;; +let _PPC_REG_VS11 = 120;; +let _PPC_REG_VS12 = 121;; +let _PPC_REG_VS13 = 122;; +let _PPC_REG_VS14 = 123;; +let _PPC_REG_VS15 = 124;; +let _PPC_REG_VS16 = 125;; +let _PPC_REG_VS17 = 126;; +let _PPC_REG_VS18 = 127;; +let _PPC_REG_VS19 = 128;; +let _PPC_REG_VS20 = 129;; +let _PPC_REG_VS21 = 130;; +let _PPC_REG_VS22 = 131;; +let _PPC_REG_VS23 = 132;; +let _PPC_REG_VS24 = 133;; +let _PPC_REG_VS25 = 134;; +let _PPC_REG_VS26 = 135;; +let _PPC_REG_VS27 = 136;; +let _PPC_REG_VS28 = 137;; +let _PPC_REG_VS29 = 138;; +let _PPC_REG_VS30 = 139;; +let _PPC_REG_VS31 = 140;; +let _PPC_REG_VS32 = 141;; +let _PPC_REG_VS33 = 142;; +let _PPC_REG_VS34 = 143;; +let _PPC_REG_VS35 = 144;; +let _PPC_REG_VS36 = 145;; +let _PPC_REG_VS37 = 146;; +let _PPC_REG_VS38 = 147;; +let _PPC_REG_VS39 = 148;; +let _PPC_REG_VS40 = 149;; +let _PPC_REG_VS41 = 150;; +let _PPC_REG_VS42 = 151;; +let _PPC_REG_VS43 = 152;; +let _PPC_REG_VS44 = 153;; +let _PPC_REG_VS45 = 154;; +let _PPC_REG_VS46 = 155;; +let _PPC_REG_VS47 = 156;; +let _PPC_REG_VS48 = 157;; +let _PPC_REG_VS49 = 158;; +let _PPC_REG_VS50 = 159;; +let _PPC_REG_VS51 = 160;; +let _PPC_REG_VS52 = 161;; +let _PPC_REG_VS53 = 162;; +let _PPC_REG_VS54 = 163;; +let _PPC_REG_VS55 = 164;; +let _PPC_REG_VS56 = 165;; +let _PPC_REG_VS57 = 166;; +let _PPC_REG_VS58 = 167;; +let _PPC_REG_VS59 = 168;; +let _PPC_REG_VS60 = 169;; +let _PPC_REG_VS61 = 170;; +let _PPC_REG_VS62 = 171;; +let _PPC_REG_VS63 = 172;; +let _PPC_REG_Q0 = 173;; +let _PPC_REG_Q1 = 174;; +let _PPC_REG_Q2 = 175;; +let _PPC_REG_Q3 = 176;; +let _PPC_REG_Q4 = 177;; +let _PPC_REG_Q5 = 178;; +let _PPC_REG_Q6 = 179;; +let _PPC_REG_Q7 = 180;; +let _PPC_REG_Q8 = 181;; +let _PPC_REG_Q9 = 182;; +let _PPC_REG_Q10 = 183;; +let _PPC_REG_Q11 = 184;; +let _PPC_REG_Q12 = 185;; +let _PPC_REG_Q13 = 186;; +let _PPC_REG_Q14 = 187;; +let _PPC_REG_Q15 = 188;; +let _PPC_REG_Q16 = 189;; +let _PPC_REG_Q17 = 190;; +let _PPC_REG_Q18 = 191;; +let _PPC_REG_Q19 = 192;; +let _PPC_REG_Q20 = 193;; +let _PPC_REG_Q21 = 194;; +let _PPC_REG_Q22 = 195;; +let _PPC_REG_Q23 = 196;; +let _PPC_REG_Q24 = 197;; +let _PPC_REG_Q25 = 198;; +let _PPC_REG_Q26 = 199;; +let _PPC_REG_Q27 = 200;; +let _PPC_REG_Q28 = 201;; +let _PPC_REG_Q29 = 202;; +let _PPC_REG_Q30 = 203;; +let _PPC_REG_Q31 = 204;; +let _PPC_REG_RM = 205;; +let _PPC_REG_CTR8 = 206;; +let _PPC_REG_LR8 = 207;; +let _PPC_REG_CR1EQ = 208;; +let _PPC_REG_X2 = 209;; +let _PPC_REG_ENDING = 210;; + +let _PPC_INS_INVALID = 0;; +let _PPC_INS_ADD = 1;; +let _PPC_INS_ADDC = 2;; +let _PPC_INS_ADDE = 3;; +let _PPC_INS_ADDI = 4;; +let _PPC_INS_ADDIC = 5;; +let _PPC_INS_ADDIS = 6;; +let _PPC_INS_ADDME = 7;; +let _PPC_INS_ADDZE = 8;; +let _PPC_INS_AND = 9;; +let _PPC_INS_ANDC = 10;; +let _PPC_INS_ANDIS = 11;; +let _PPC_INS_ANDI = 12;; +let _PPC_INS_ATTN = 13;; +let _PPC_INS_B = 14;; +let _PPC_INS_BA = 15;; +let _PPC_INS_BC = 16;; +let _PPC_INS_BCCTR = 17;; +let _PPC_INS_BCCTRL = 18;; +let _PPC_INS_BCL = 19;; +let _PPC_INS_BCLR = 20;; +let _PPC_INS_BCLRL = 21;; +let _PPC_INS_BCTR = 22;; +let _PPC_INS_BCTRL = 23;; +let _PPC_INS_BCT = 24;; +let _PPC_INS_BDNZ = 25;; +let _PPC_INS_BDNZA = 26;; +let _PPC_INS_BDNZL = 27;; +let _PPC_INS_BDNZLA = 28;; +let _PPC_INS_BDNZLR = 29;; +let _PPC_INS_BDNZLRL = 30;; +let _PPC_INS_BDZ = 31;; +let _PPC_INS_BDZA = 32;; +let _PPC_INS_BDZL = 33;; +let _PPC_INS_BDZLA = 34;; +let _PPC_INS_BDZLR = 35;; +let _PPC_INS_BDZLRL = 36;; +let _PPC_INS_BL = 37;; +let _PPC_INS_BLA = 38;; +let _PPC_INS_BLR = 39;; +let _PPC_INS_BLRL = 40;; +let _PPC_INS_BRINC = 41;; +let _PPC_INS_CMPB = 42;; +let _PPC_INS_CMPD = 43;; +let _PPC_INS_CMPDI = 44;; +let _PPC_INS_CMPLD = 45;; +let _PPC_INS_CMPLDI = 46;; +let _PPC_INS_CMPLW = 47;; +let _PPC_INS_CMPLWI = 48;; +let _PPC_INS_CMPW = 49;; +let _PPC_INS_CMPWI = 50;; +let _PPC_INS_CNTLZD = 51;; +let _PPC_INS_CNTLZW = 52;; +let _PPC_INS_CREQV = 53;; +let _PPC_INS_CRXOR = 54;; +let _PPC_INS_CRAND = 55;; +let _PPC_INS_CRANDC = 56;; +let _PPC_INS_CRNAND = 57;; +let _PPC_INS_CRNOR = 58;; +let _PPC_INS_CROR = 59;; +let _PPC_INS_CRORC = 60;; +let _PPC_INS_DCBA = 61;; +let _PPC_INS_DCBF = 62;; +let _PPC_INS_DCBI = 63;; +let _PPC_INS_DCBST = 64;; +let _PPC_INS_DCBT = 65;; +let _PPC_INS_DCBTST = 66;; +let _PPC_INS_DCBZ = 67;; +let _PPC_INS_DCBZL = 68;; +let _PPC_INS_DCCCI = 69;; +let _PPC_INS_DIVD = 70;; +let _PPC_INS_DIVDU = 71;; +let _PPC_INS_DIVW = 72;; +let _PPC_INS_DIVWU = 73;; +let _PPC_INS_DSS = 74;; +let _PPC_INS_DSSALL = 75;; +let _PPC_INS_DST = 76;; +let _PPC_INS_DSTST = 77;; +let _PPC_INS_DSTSTT = 78;; +let _PPC_INS_DSTT = 79;; +let _PPC_INS_EQV = 80;; +let _PPC_INS_EVABS = 81;; +let _PPC_INS_EVADDIW = 82;; +let _PPC_INS_EVADDSMIAAW = 83;; +let _PPC_INS_EVADDSSIAAW = 84;; +let _PPC_INS_EVADDUMIAAW = 85;; +let _PPC_INS_EVADDUSIAAW = 86;; +let _PPC_INS_EVADDW = 87;; +let _PPC_INS_EVAND = 88;; +let _PPC_INS_EVANDC = 89;; +let _PPC_INS_EVCMPEQ = 90;; +let _PPC_INS_EVCMPGTS = 91;; +let _PPC_INS_EVCMPGTU = 92;; +let _PPC_INS_EVCMPLTS = 93;; +let _PPC_INS_EVCMPLTU = 94;; +let _PPC_INS_EVCNTLSW = 95;; +let _PPC_INS_EVCNTLZW = 96;; +let _PPC_INS_EVDIVWS = 97;; +let _PPC_INS_EVDIVWU = 98;; +let _PPC_INS_EVEQV = 99;; +let _PPC_INS_EVEXTSB = 100;; +let _PPC_INS_EVEXTSH = 101;; +let _PPC_INS_EVLDD = 102;; +let _PPC_INS_EVLDDX = 103;; +let _PPC_INS_EVLDH = 104;; +let _PPC_INS_EVLDHX = 105;; +let _PPC_INS_EVLDW = 106;; +let _PPC_INS_EVLDWX = 107;; +let _PPC_INS_EVLHHESPLAT = 108;; +let _PPC_INS_EVLHHESPLATX = 109;; +let _PPC_INS_EVLHHOSSPLAT = 110;; +let _PPC_INS_EVLHHOSSPLATX = 111;; +let _PPC_INS_EVLHHOUSPLAT = 112;; +let _PPC_INS_EVLHHOUSPLATX = 113;; +let _PPC_INS_EVLWHE = 114;; +let _PPC_INS_EVLWHEX = 115;; +let _PPC_INS_EVLWHOS = 116;; +let _PPC_INS_EVLWHOSX = 117;; +let _PPC_INS_EVLWHOU = 118;; +let _PPC_INS_EVLWHOUX = 119;; +let _PPC_INS_EVLWHSPLAT = 120;; +let _PPC_INS_EVLWHSPLATX = 121;; +let _PPC_INS_EVLWWSPLAT = 122;; +let _PPC_INS_EVLWWSPLATX = 123;; +let _PPC_INS_EVMERGEHI = 124;; +let _PPC_INS_EVMERGEHILO = 125;; +let _PPC_INS_EVMERGELO = 126;; +let _PPC_INS_EVMERGELOHI = 127;; +let _PPC_INS_EVMHEGSMFAA = 128;; +let _PPC_INS_EVMHEGSMFAN = 129;; +let _PPC_INS_EVMHEGSMIAA = 130;; +let _PPC_INS_EVMHEGSMIAN = 131;; +let _PPC_INS_EVMHEGUMIAA = 132;; +let _PPC_INS_EVMHEGUMIAN = 133;; +let _PPC_INS_EVMHESMF = 134;; +let _PPC_INS_EVMHESMFA = 135;; +let _PPC_INS_EVMHESMFAAW = 136;; +let _PPC_INS_EVMHESMFANW = 137;; +let _PPC_INS_EVMHESMI = 138;; +let _PPC_INS_EVMHESMIA = 139;; +let _PPC_INS_EVMHESMIAAW = 140;; +let _PPC_INS_EVMHESMIANW = 141;; +let _PPC_INS_EVMHESSF = 142;; +let _PPC_INS_EVMHESSFA = 143;; +let _PPC_INS_EVMHESSFAAW = 144;; +let _PPC_INS_EVMHESSFANW = 145;; +let _PPC_INS_EVMHESSIAAW = 146;; +let _PPC_INS_EVMHESSIANW = 147;; +let _PPC_INS_EVMHEUMI = 148;; +let _PPC_INS_EVMHEUMIA = 149;; +let _PPC_INS_EVMHEUMIAAW = 150;; +let _PPC_INS_EVMHEUMIANW = 151;; +let _PPC_INS_EVMHEUSIAAW = 152;; +let _PPC_INS_EVMHEUSIANW = 153;; +let _PPC_INS_EVMHOGSMFAA = 154;; +let _PPC_INS_EVMHOGSMFAN = 155;; +let _PPC_INS_EVMHOGSMIAA = 156;; +let _PPC_INS_EVMHOGSMIAN = 157;; +let _PPC_INS_EVMHOGUMIAA = 158;; +let _PPC_INS_EVMHOGUMIAN = 159;; +let _PPC_INS_EVMHOSMF = 160;; +let _PPC_INS_EVMHOSMFA = 161;; +let _PPC_INS_EVMHOSMFAAW = 162;; +let _PPC_INS_EVMHOSMFANW = 163;; +let _PPC_INS_EVMHOSMI = 164;; +let _PPC_INS_EVMHOSMIA = 165;; +let _PPC_INS_EVMHOSMIAAW = 166;; +let _PPC_INS_EVMHOSMIANW = 167;; +let _PPC_INS_EVMHOSSF = 168;; +let _PPC_INS_EVMHOSSFA = 169;; +let _PPC_INS_EVMHOSSFAAW = 170;; +let _PPC_INS_EVMHOSSFANW = 171;; +let _PPC_INS_EVMHOSSIAAW = 172;; +let _PPC_INS_EVMHOSSIANW = 173;; +let _PPC_INS_EVMHOUMI = 174;; +let _PPC_INS_EVMHOUMIA = 175;; +let _PPC_INS_EVMHOUMIAAW = 176;; +let _PPC_INS_EVMHOUMIANW = 177;; +let _PPC_INS_EVMHOUSIAAW = 178;; +let _PPC_INS_EVMHOUSIANW = 179;; +let _PPC_INS_EVMRA = 180;; +let _PPC_INS_EVMWHSMF = 181;; +let _PPC_INS_EVMWHSMFA = 182;; +let _PPC_INS_EVMWHSMI = 183;; +let _PPC_INS_EVMWHSMIA = 184;; +let _PPC_INS_EVMWHSSF = 185;; +let _PPC_INS_EVMWHSSFA = 186;; +let _PPC_INS_EVMWHUMI = 187;; +let _PPC_INS_EVMWHUMIA = 188;; +let _PPC_INS_EVMWLSMIAAW = 189;; +let _PPC_INS_EVMWLSMIANW = 190;; +let _PPC_INS_EVMWLSSIAAW = 191;; +let _PPC_INS_EVMWLSSIANW = 192;; +let _PPC_INS_EVMWLUMI = 193;; +let _PPC_INS_EVMWLUMIA = 194;; +let _PPC_INS_EVMWLUMIAAW = 195;; +let _PPC_INS_EVMWLUMIANW = 196;; +let _PPC_INS_EVMWLUSIAAW = 197;; +let _PPC_INS_EVMWLUSIANW = 198;; +let _PPC_INS_EVMWSMF = 199;; +let _PPC_INS_EVMWSMFA = 200;; +let _PPC_INS_EVMWSMFAA = 201;; +let _PPC_INS_EVMWSMFAN = 202;; +let _PPC_INS_EVMWSMI = 203;; +let _PPC_INS_EVMWSMIA = 204;; +let _PPC_INS_EVMWSMIAA = 205;; +let _PPC_INS_EVMWSMIAN = 206;; +let _PPC_INS_EVMWSSF = 207;; +let _PPC_INS_EVMWSSFA = 208;; +let _PPC_INS_EVMWSSFAA = 209;; +let _PPC_INS_EVMWSSFAN = 210;; +let _PPC_INS_EVMWUMI = 211;; +let _PPC_INS_EVMWUMIA = 212;; +let _PPC_INS_EVMWUMIAA = 213;; +let _PPC_INS_EVMWUMIAN = 214;; +let _PPC_INS_EVNAND = 215;; +let _PPC_INS_EVNEG = 216;; +let _PPC_INS_EVNOR = 217;; +let _PPC_INS_EVOR = 218;; +let _PPC_INS_EVORC = 219;; +let _PPC_INS_EVRLW = 220;; +let _PPC_INS_EVRLWI = 221;; +let _PPC_INS_EVRNDW = 222;; +let _PPC_INS_EVSLW = 223;; +let _PPC_INS_EVSLWI = 224;; +let _PPC_INS_EVSPLATFI = 225;; +let _PPC_INS_EVSPLATI = 226;; +let _PPC_INS_EVSRWIS = 227;; +let _PPC_INS_EVSRWIU = 228;; +let _PPC_INS_EVSRWS = 229;; +let _PPC_INS_EVSRWU = 230;; +let _PPC_INS_EVSTDD = 231;; +let _PPC_INS_EVSTDDX = 232;; +let _PPC_INS_EVSTDH = 233;; +let _PPC_INS_EVSTDHX = 234;; +let _PPC_INS_EVSTDW = 235;; +let _PPC_INS_EVSTDWX = 236;; +let _PPC_INS_EVSTWHE = 237;; +let _PPC_INS_EVSTWHEX = 238;; +let _PPC_INS_EVSTWHO = 239;; +let _PPC_INS_EVSTWHOX = 240;; +let _PPC_INS_EVSTWWE = 241;; +let _PPC_INS_EVSTWWEX = 242;; +let _PPC_INS_EVSTWWO = 243;; +let _PPC_INS_EVSTWWOX = 244;; +let _PPC_INS_EVSUBFSMIAAW = 245;; +let _PPC_INS_EVSUBFSSIAAW = 246;; +let _PPC_INS_EVSUBFUMIAAW = 247;; +let _PPC_INS_EVSUBFUSIAAW = 248;; +let _PPC_INS_EVSUBFW = 249;; +let _PPC_INS_EVSUBIFW = 250;; +let _PPC_INS_EVXOR = 251;; +let _PPC_INS_EXTSB = 252;; +let _PPC_INS_EXTSH = 253;; +let _PPC_INS_EXTSW = 254;; +let _PPC_INS_EIEIO = 255;; +let _PPC_INS_FABS = 256;; +let _PPC_INS_FADD = 257;; +let _PPC_INS_FADDS = 258;; +let _PPC_INS_FCFID = 259;; +let _PPC_INS_FCFIDS = 260;; +let _PPC_INS_FCFIDU = 261;; +let _PPC_INS_FCFIDUS = 262;; +let _PPC_INS_FCMPU = 263;; +let _PPC_INS_FCPSGN = 264;; +let _PPC_INS_FCTID = 265;; +let _PPC_INS_FCTIDUZ = 266;; +let _PPC_INS_FCTIDZ = 267;; +let _PPC_INS_FCTIW = 268;; +let _PPC_INS_FCTIWUZ = 269;; +let _PPC_INS_FCTIWZ = 270;; +let _PPC_INS_FDIV = 271;; +let _PPC_INS_FDIVS = 272;; +let _PPC_INS_FMADD = 273;; +let _PPC_INS_FMADDS = 274;; +let _PPC_INS_FMR = 275;; +let _PPC_INS_FMSUB = 276;; +let _PPC_INS_FMSUBS = 277;; +let _PPC_INS_FMUL = 278;; +let _PPC_INS_FMULS = 279;; +let _PPC_INS_FNABS = 280;; +let _PPC_INS_FNEG = 281;; +let _PPC_INS_FNMADD = 282;; +let _PPC_INS_FNMADDS = 283;; +let _PPC_INS_FNMSUB = 284;; +let _PPC_INS_FNMSUBS = 285;; +let _PPC_INS_FRE = 286;; +let _PPC_INS_FRES = 287;; +let _PPC_INS_FRIM = 288;; +let _PPC_INS_FRIN = 289;; +let _PPC_INS_FRIP = 290;; +let _PPC_INS_FRIZ = 291;; +let _PPC_INS_FRSP = 292;; +let _PPC_INS_FRSQRTE = 293;; +let _PPC_INS_FRSQRTES = 294;; +let _PPC_INS_FSEL = 295;; +let _PPC_INS_FSQRT = 296;; +let _PPC_INS_FSQRTS = 297;; +let _PPC_INS_FSUB = 298;; +let _PPC_INS_FSUBS = 299;; +let _PPC_INS_ICBI = 300;; +let _PPC_INS_ICBT = 301;; +let _PPC_INS_ICCCI = 302;; +let _PPC_INS_ISEL = 303;; +let _PPC_INS_ISYNC = 304;; +let _PPC_INS_LA = 305;; +let _PPC_INS_LBZ = 306;; +let _PPC_INS_LBZCIX = 307;; +let _PPC_INS_LBZU = 308;; +let _PPC_INS_LBZUX = 309;; +let _PPC_INS_LBZX = 310;; +let _PPC_INS_LD = 311;; +let _PPC_INS_LDARX = 312;; +let _PPC_INS_LDBRX = 313;; +let _PPC_INS_LDCIX = 314;; +let _PPC_INS_LDU = 315;; +let _PPC_INS_LDUX = 316;; +let _PPC_INS_LDX = 317;; +let _PPC_INS_LFD = 318;; +let _PPC_INS_LFDU = 319;; +let _PPC_INS_LFDUX = 320;; +let _PPC_INS_LFDX = 321;; +let _PPC_INS_LFIWAX = 322;; +let _PPC_INS_LFIWZX = 323;; +let _PPC_INS_LFS = 324;; +let _PPC_INS_LFSU = 325;; +let _PPC_INS_LFSUX = 326;; +let _PPC_INS_LFSX = 327;; +let _PPC_INS_LHA = 328;; +let _PPC_INS_LHAU = 329;; +let _PPC_INS_LHAUX = 330;; +let _PPC_INS_LHAX = 331;; +let _PPC_INS_LHBRX = 332;; +let _PPC_INS_LHZ = 333;; +let _PPC_INS_LHZCIX = 334;; +let _PPC_INS_LHZU = 335;; +let _PPC_INS_LHZUX = 336;; +let _PPC_INS_LHZX = 337;; +let _PPC_INS_LI = 338;; +let _PPC_INS_LIS = 339;; +let _PPC_INS_LMW = 340;; +let _PPC_INS_LSWI = 341;; +let _PPC_INS_LVEBX = 342;; +let _PPC_INS_LVEHX = 343;; +let _PPC_INS_LVEWX = 344;; +let _PPC_INS_LVSL = 345;; +let _PPC_INS_LVSR = 346;; +let _PPC_INS_LVX = 347;; +let _PPC_INS_LVXL = 348;; +let _PPC_INS_LWA = 349;; +let _PPC_INS_LWARX = 350;; +let _PPC_INS_LWAUX = 351;; +let _PPC_INS_LWAX = 352;; +let _PPC_INS_LWBRX = 353;; +let _PPC_INS_LWZ = 354;; +let _PPC_INS_LWZCIX = 355;; +let _PPC_INS_LWZU = 356;; +let _PPC_INS_LWZUX = 357;; +let _PPC_INS_LWZX = 358;; +let _PPC_INS_LXSDX = 359;; +let _PPC_INS_LXVD2X = 360;; +let _PPC_INS_LXVDSX = 361;; +let _PPC_INS_LXVW4X = 362;; +let _PPC_INS_MBAR = 363;; +let _PPC_INS_MCRF = 364;; +let _PPC_INS_MCRFS = 365;; +let _PPC_INS_MFCR = 366;; +let _PPC_INS_MFCTR = 367;; +let _PPC_INS_MFDCR = 368;; +let _PPC_INS_MFFS = 369;; +let _PPC_INS_MFLR = 370;; +let _PPC_INS_MFMSR = 371;; +let _PPC_INS_MFOCRF = 372;; +let _PPC_INS_MFSPR = 373;; +let _PPC_INS_MFSR = 374;; +let _PPC_INS_MFSRIN = 375;; +let _PPC_INS_MFTB = 376;; +let _PPC_INS_MFVSCR = 377;; +let _PPC_INS_MSYNC = 378;; +let _PPC_INS_MTCRF = 379;; +let _PPC_INS_MTCTR = 380;; +let _PPC_INS_MTDCR = 381;; +let _PPC_INS_MTFSB0 = 382;; +let _PPC_INS_MTFSB1 = 383;; +let _PPC_INS_MTFSF = 384;; +let _PPC_INS_MTFSFI = 385;; +let _PPC_INS_MTLR = 386;; +let _PPC_INS_MTMSR = 387;; +let _PPC_INS_MTMSRD = 388;; +let _PPC_INS_MTOCRF = 389;; +let _PPC_INS_MTSPR = 390;; +let _PPC_INS_MTSR = 391;; +let _PPC_INS_MTSRIN = 392;; +let _PPC_INS_MTVSCR = 393;; +let _PPC_INS_MULHD = 394;; +let _PPC_INS_MULHDU = 395;; +let _PPC_INS_MULHW = 396;; +let _PPC_INS_MULHWU = 397;; +let _PPC_INS_MULLD = 398;; +let _PPC_INS_MULLI = 399;; +let _PPC_INS_MULLW = 400;; +let _PPC_INS_NAND = 401;; +let _PPC_INS_NEG = 402;; +let _PPC_INS_NOP = 403;; +let _PPC_INS_ORI = 404;; +let _PPC_INS_NOR = 405;; +let _PPC_INS_OR = 406;; +let _PPC_INS_ORC = 407;; +let _PPC_INS_ORIS = 408;; +let _PPC_INS_POPCNTD = 409;; +let _PPC_INS_POPCNTW = 410;; +let _PPC_INS_QVALIGNI = 411;; +let _PPC_INS_QVESPLATI = 412;; +let _PPC_INS_QVFABS = 413;; +let _PPC_INS_QVFADD = 414;; +let _PPC_INS_QVFADDS = 415;; +let _PPC_INS_QVFCFID = 416;; +let _PPC_INS_QVFCFIDS = 417;; +let _PPC_INS_QVFCFIDU = 418;; +let _PPC_INS_QVFCFIDUS = 419;; +let _PPC_INS_QVFCMPEQ = 420;; +let _PPC_INS_QVFCMPGT = 421;; +let _PPC_INS_QVFCMPLT = 422;; +let _PPC_INS_QVFCPSGN = 423;; +let _PPC_INS_QVFCTID = 424;; +let _PPC_INS_QVFCTIDU = 425;; +let _PPC_INS_QVFCTIDUZ = 426;; +let _PPC_INS_QVFCTIDZ = 427;; +let _PPC_INS_QVFCTIW = 428;; +let _PPC_INS_QVFCTIWU = 429;; +let _PPC_INS_QVFCTIWUZ = 430;; +let _PPC_INS_QVFCTIWZ = 431;; +let _PPC_INS_QVFLOGICAL = 432;; +let _PPC_INS_QVFMADD = 433;; +let _PPC_INS_QVFMADDS = 434;; +let _PPC_INS_QVFMR = 435;; +let _PPC_INS_QVFMSUB = 436;; +let _PPC_INS_QVFMSUBS = 437;; +let _PPC_INS_QVFMUL = 438;; +let _PPC_INS_QVFMULS = 439;; +let _PPC_INS_QVFNABS = 440;; +let _PPC_INS_QVFNEG = 441;; +let _PPC_INS_QVFNMADD = 442;; +let _PPC_INS_QVFNMADDS = 443;; +let _PPC_INS_QVFNMSUB = 444;; +let _PPC_INS_QVFNMSUBS = 445;; +let _PPC_INS_QVFPERM = 446;; +let _PPC_INS_QVFRE = 447;; +let _PPC_INS_QVFRES = 448;; +let _PPC_INS_QVFRIM = 449;; +let _PPC_INS_QVFRIN = 450;; +let _PPC_INS_QVFRIP = 451;; +let _PPC_INS_QVFRIZ = 452;; +let _PPC_INS_QVFRSP = 453;; +let _PPC_INS_QVFRSQRTE = 454;; +let _PPC_INS_QVFRSQRTES = 455;; +let _PPC_INS_QVFSEL = 456;; +let _PPC_INS_QVFSUB = 457;; +let _PPC_INS_QVFSUBS = 458;; +let _PPC_INS_QVFTSTNAN = 459;; +let _PPC_INS_QVFXMADD = 460;; +let _PPC_INS_QVFXMADDS = 461;; +let _PPC_INS_QVFXMUL = 462;; +let _PPC_INS_QVFXMULS = 463;; +let _PPC_INS_QVFXXCPNMADD = 464;; +let _PPC_INS_QVFXXCPNMADDS = 465;; +let _PPC_INS_QVFXXMADD = 466;; +let _PPC_INS_QVFXXMADDS = 467;; +let _PPC_INS_QVFXXNPMADD = 468;; +let _PPC_INS_QVFXXNPMADDS = 469;; +let _PPC_INS_QVGPCI = 470;; +let _PPC_INS_QVLFCDUX = 471;; +let _PPC_INS_QVLFCDUXA = 472;; +let _PPC_INS_QVLFCDX = 473;; +let _PPC_INS_QVLFCDXA = 474;; +let _PPC_INS_QVLFCSUX = 475;; +let _PPC_INS_QVLFCSUXA = 476;; +let _PPC_INS_QVLFCSX = 477;; +let _PPC_INS_QVLFCSXA = 478;; +let _PPC_INS_QVLFDUX = 479;; +let _PPC_INS_QVLFDUXA = 480;; +let _PPC_INS_QVLFDX = 481;; +let _PPC_INS_QVLFDXA = 482;; +let _PPC_INS_QVLFIWAX = 483;; +let _PPC_INS_QVLFIWAXA = 484;; +let _PPC_INS_QVLFIWZX = 485;; +let _PPC_INS_QVLFIWZXA = 486;; +let _PPC_INS_QVLFSUX = 487;; +let _PPC_INS_QVLFSUXA = 488;; +let _PPC_INS_QVLFSX = 489;; +let _PPC_INS_QVLFSXA = 490;; +let _PPC_INS_QVLPCLDX = 491;; +let _PPC_INS_QVLPCLSX = 492;; +let _PPC_INS_QVLPCRDX = 493;; +let _PPC_INS_QVLPCRSX = 494;; +let _PPC_INS_QVSTFCDUX = 495;; +let _PPC_INS_QVSTFCDUXA = 496;; +let _PPC_INS_QVSTFCDUXI = 497;; +let _PPC_INS_QVSTFCDUXIA = 498;; +let _PPC_INS_QVSTFCDX = 499;; +let _PPC_INS_QVSTFCDXA = 500;; +let _PPC_INS_QVSTFCDXI = 501;; +let _PPC_INS_QVSTFCDXIA = 502;; +let _PPC_INS_QVSTFCSUX = 503;; +let _PPC_INS_QVSTFCSUXA = 504;; +let _PPC_INS_QVSTFCSUXI = 505;; +let _PPC_INS_QVSTFCSUXIA = 506;; +let _PPC_INS_QVSTFCSX = 507;; +let _PPC_INS_QVSTFCSXA = 508;; +let _PPC_INS_QVSTFCSXI = 509;; +let _PPC_INS_QVSTFCSXIA = 510;; +let _PPC_INS_QVSTFDUX = 511;; +let _PPC_INS_QVSTFDUXA = 512;; +let _PPC_INS_QVSTFDUXI = 513;; +let _PPC_INS_QVSTFDUXIA = 514;; +let _PPC_INS_QVSTFDX = 515;; +let _PPC_INS_QVSTFDXA = 516;; +let _PPC_INS_QVSTFDXI = 517;; +let _PPC_INS_QVSTFDXIA = 518;; +let _PPC_INS_QVSTFIWX = 519;; +let _PPC_INS_QVSTFIWXA = 520;; +let _PPC_INS_QVSTFSUX = 521;; +let _PPC_INS_QVSTFSUXA = 522;; +let _PPC_INS_QVSTFSUXI = 523;; +let _PPC_INS_QVSTFSUXIA = 524;; +let _PPC_INS_QVSTFSX = 525;; +let _PPC_INS_QVSTFSXA = 526;; +let _PPC_INS_QVSTFSXI = 527;; +let _PPC_INS_QVSTFSXIA = 528;; +let _PPC_INS_RFCI = 529;; +let _PPC_INS_RFDI = 530;; +let _PPC_INS_RFI = 531;; +let _PPC_INS_RFID = 532;; +let _PPC_INS_RFMCI = 533;; +let _PPC_INS_RLDCL = 534;; +let _PPC_INS_RLDCR = 535;; +let _PPC_INS_RLDIC = 536;; +let _PPC_INS_RLDICL = 537;; +let _PPC_INS_RLDICR = 538;; +let _PPC_INS_RLDIMI = 539;; +let _PPC_INS_RLWIMI = 540;; +let _PPC_INS_RLWINM = 541;; +let _PPC_INS_RLWNM = 542;; +let _PPC_INS_SC = 543;; +let _PPC_INS_SLBIA = 544;; +let _PPC_INS_SLBIE = 545;; +let _PPC_INS_SLBMFEE = 546;; +let _PPC_INS_SLBMTE = 547;; +let _PPC_INS_SLD = 548;; +let _PPC_INS_SLW = 549;; +let _PPC_INS_SRAD = 550;; +let _PPC_INS_SRADI = 551;; +let _PPC_INS_SRAW = 552;; +let _PPC_INS_SRAWI = 553;; +let _PPC_INS_SRD = 554;; +let _PPC_INS_SRW = 555;; +let _PPC_INS_STB = 556;; +let _PPC_INS_STBCIX = 557;; +let _PPC_INS_STBU = 558;; +let _PPC_INS_STBUX = 559;; +let _PPC_INS_STBX = 560;; +let _PPC_INS_STD = 561;; +let _PPC_INS_STDBRX = 562;; +let _PPC_INS_STDCIX = 563;; +let _PPC_INS_STDCX = 564;; +let _PPC_INS_STDU = 565;; +let _PPC_INS_STDUX = 566;; +let _PPC_INS_STDX = 567;; +let _PPC_INS_STFD = 568;; +let _PPC_INS_STFDU = 569;; +let _PPC_INS_STFDUX = 570;; +let _PPC_INS_STFDX = 571;; +let _PPC_INS_STFIWX = 572;; +let _PPC_INS_STFS = 573;; +let _PPC_INS_STFSU = 574;; +let _PPC_INS_STFSUX = 575;; +let _PPC_INS_STFSX = 576;; +let _PPC_INS_STH = 577;; +let _PPC_INS_STHBRX = 578;; +let _PPC_INS_STHCIX = 579;; +let _PPC_INS_STHU = 580;; +let _PPC_INS_STHUX = 581;; +let _PPC_INS_STHX = 582;; +let _PPC_INS_STMW = 583;; +let _PPC_INS_STSWI = 584;; +let _PPC_INS_STVEBX = 585;; +let _PPC_INS_STVEHX = 586;; +let _PPC_INS_STVEWX = 587;; +let _PPC_INS_STVX = 588;; +let _PPC_INS_STVXL = 589;; +let _PPC_INS_STW = 590;; +let _PPC_INS_STWBRX = 591;; +let _PPC_INS_STWCIX = 592;; +let _PPC_INS_STWCX = 593;; +let _PPC_INS_STWU = 594;; +let _PPC_INS_STWUX = 595;; +let _PPC_INS_STWX = 596;; +let _PPC_INS_STXSDX = 597;; +let _PPC_INS_STXVD2X = 598;; +let _PPC_INS_STXVW4X = 599;; +let _PPC_INS_SUBF = 600;; +let _PPC_INS_SUBFC = 601;; +let _PPC_INS_SUBFE = 602;; +let _PPC_INS_SUBFIC = 603;; +let _PPC_INS_SUBFME = 604;; +let _PPC_INS_SUBFZE = 605;; +let _PPC_INS_SYNC = 606;; +let _PPC_INS_TD = 607;; +let _PPC_INS_TDI = 608;; +let _PPC_INS_TLBIA = 609;; +let _PPC_INS_TLBIE = 610;; +let _PPC_INS_TLBIEL = 611;; +let _PPC_INS_TLBIVAX = 612;; +let _PPC_INS_TLBLD = 613;; +let _PPC_INS_TLBLI = 614;; +let _PPC_INS_TLBRE = 615;; +let _PPC_INS_TLBSX = 616;; +let _PPC_INS_TLBSYNC = 617;; +let _PPC_INS_TLBWE = 618;; +let _PPC_INS_TRAP = 619;; +let _PPC_INS_TW = 620;; +let _PPC_INS_TWI = 621;; +let _PPC_INS_VADDCUW = 622;; +let _PPC_INS_VADDFP = 623;; +let _PPC_INS_VADDSBS = 624;; +let _PPC_INS_VADDSHS = 625;; +let _PPC_INS_VADDSWS = 626;; +let _PPC_INS_VADDUBM = 627;; +let _PPC_INS_VADDUBS = 628;; +let _PPC_INS_VADDUDM = 629;; +let _PPC_INS_VADDUHM = 630;; +let _PPC_INS_VADDUHS = 631;; +let _PPC_INS_VADDUWM = 632;; +let _PPC_INS_VADDUWS = 633;; +let _PPC_INS_VAND = 634;; +let _PPC_INS_VANDC = 635;; +let _PPC_INS_VAVGSB = 636;; +let _PPC_INS_VAVGSH = 637;; +let _PPC_INS_VAVGSW = 638;; +let _PPC_INS_VAVGUB = 639;; +let _PPC_INS_VAVGUH = 640;; +let _PPC_INS_VAVGUW = 641;; +let _PPC_INS_VCFSX = 642;; +let _PPC_INS_VCFUX = 643;; +let _PPC_INS_VCLZB = 644;; +let _PPC_INS_VCLZD = 645;; +let _PPC_INS_VCLZH = 646;; +let _PPC_INS_VCLZW = 647;; +let _PPC_INS_VCMPBFP = 648;; +let _PPC_INS_VCMPEQFP = 649;; +let _PPC_INS_VCMPEQUB = 650;; +let _PPC_INS_VCMPEQUD = 651;; +let _PPC_INS_VCMPEQUH = 652;; +let _PPC_INS_VCMPEQUW = 653;; +let _PPC_INS_VCMPGEFP = 654;; +let _PPC_INS_VCMPGTFP = 655;; +let _PPC_INS_VCMPGTSB = 656;; +let _PPC_INS_VCMPGTSD = 657;; +let _PPC_INS_VCMPGTSH = 658;; +let _PPC_INS_VCMPGTSW = 659;; +let _PPC_INS_VCMPGTUB = 660;; +let _PPC_INS_VCMPGTUD = 661;; +let _PPC_INS_VCMPGTUH = 662;; +let _PPC_INS_VCMPGTUW = 663;; +let _PPC_INS_VCTSXS = 664;; +let _PPC_INS_VCTUXS = 665;; +let _PPC_INS_VEQV = 666;; +let _PPC_INS_VEXPTEFP = 667;; +let _PPC_INS_VLOGEFP = 668;; +let _PPC_INS_VMADDFP = 669;; +let _PPC_INS_VMAXFP = 670;; +let _PPC_INS_VMAXSB = 671;; +let _PPC_INS_VMAXSD = 672;; +let _PPC_INS_VMAXSH = 673;; +let _PPC_INS_VMAXSW = 674;; +let _PPC_INS_VMAXUB = 675;; +let _PPC_INS_VMAXUD = 676;; +let _PPC_INS_VMAXUH = 677;; +let _PPC_INS_VMAXUW = 678;; +let _PPC_INS_VMHADDSHS = 679;; +let _PPC_INS_VMHRADDSHS = 680;; +let _PPC_INS_VMINUD = 681;; +let _PPC_INS_VMINFP = 682;; +let _PPC_INS_VMINSB = 683;; +let _PPC_INS_VMINSD = 684;; +let _PPC_INS_VMINSH = 685;; +let _PPC_INS_VMINSW = 686;; +let _PPC_INS_VMINUB = 687;; +let _PPC_INS_VMINUH = 688;; +let _PPC_INS_VMINUW = 689;; +let _PPC_INS_VMLADDUHM = 690;; +let _PPC_INS_VMRGHB = 691;; +let _PPC_INS_VMRGHH = 692;; +let _PPC_INS_VMRGHW = 693;; +let _PPC_INS_VMRGLB = 694;; +let _PPC_INS_VMRGLH = 695;; +let _PPC_INS_VMRGLW = 696;; +let _PPC_INS_VMSUMMBM = 697;; +let _PPC_INS_VMSUMSHM = 698;; +let _PPC_INS_VMSUMSHS = 699;; +let _PPC_INS_VMSUMUBM = 700;; +let _PPC_INS_VMSUMUHM = 701;; +let _PPC_INS_VMSUMUHS = 702;; +let _PPC_INS_VMULESB = 703;; +let _PPC_INS_VMULESH = 704;; +let _PPC_INS_VMULESW = 705;; +let _PPC_INS_VMULEUB = 706;; +let _PPC_INS_VMULEUH = 707;; +let _PPC_INS_VMULEUW = 708;; +let _PPC_INS_VMULOSB = 709;; +let _PPC_INS_VMULOSH = 710;; +let _PPC_INS_VMULOSW = 711;; +let _PPC_INS_VMULOUB = 712;; +let _PPC_INS_VMULOUH = 713;; +let _PPC_INS_VMULOUW = 714;; +let _PPC_INS_VMULUWM = 715;; +let _PPC_INS_VNAND = 716;; +let _PPC_INS_VNMSUBFP = 717;; +let _PPC_INS_VNOR = 718;; +let _PPC_INS_VOR = 719;; +let _PPC_INS_VORC = 720;; +let _PPC_INS_VPERM = 721;; +let _PPC_INS_VPKPX = 722;; +let _PPC_INS_VPKSHSS = 723;; +let _PPC_INS_VPKSHUS = 724;; +let _PPC_INS_VPKSWSS = 725;; +let _PPC_INS_VPKSWUS = 726;; +let _PPC_INS_VPKUHUM = 727;; +let _PPC_INS_VPKUHUS = 728;; +let _PPC_INS_VPKUWUM = 729;; +let _PPC_INS_VPKUWUS = 730;; +let _PPC_INS_VPOPCNTB = 731;; +let _PPC_INS_VPOPCNTD = 732;; +let _PPC_INS_VPOPCNTH = 733;; +let _PPC_INS_VPOPCNTW = 734;; +let _PPC_INS_VREFP = 735;; +let _PPC_INS_VRFIM = 736;; +let _PPC_INS_VRFIN = 737;; +let _PPC_INS_VRFIP = 738;; +let _PPC_INS_VRFIZ = 739;; +let _PPC_INS_VRLB = 740;; +let _PPC_INS_VRLD = 741;; +let _PPC_INS_VRLH = 742;; +let _PPC_INS_VRLW = 743;; +let _PPC_INS_VRSQRTEFP = 744;; +let _PPC_INS_VSEL = 745;; +let _PPC_INS_VSL = 746;; +let _PPC_INS_VSLB = 747;; +let _PPC_INS_VSLD = 748;; +let _PPC_INS_VSLDOI = 749;; +let _PPC_INS_VSLH = 750;; +let _PPC_INS_VSLO = 751;; +let _PPC_INS_VSLW = 752;; +let _PPC_INS_VSPLTB = 753;; +let _PPC_INS_VSPLTH = 754;; +let _PPC_INS_VSPLTISB = 755;; +let _PPC_INS_VSPLTISH = 756;; +let _PPC_INS_VSPLTISW = 757;; +let _PPC_INS_VSPLTW = 758;; +let _PPC_INS_VSR = 759;; +let _PPC_INS_VSRAB = 760;; +let _PPC_INS_VSRAD = 761;; +let _PPC_INS_VSRAH = 762;; +let _PPC_INS_VSRAW = 763;; +let _PPC_INS_VSRB = 764;; +let _PPC_INS_VSRD = 765;; +let _PPC_INS_VSRH = 766;; +let _PPC_INS_VSRO = 767;; +let _PPC_INS_VSRW = 768;; +let _PPC_INS_VSUBCUW = 769;; +let _PPC_INS_VSUBFP = 770;; +let _PPC_INS_VSUBSBS = 771;; +let _PPC_INS_VSUBSHS = 772;; +let _PPC_INS_VSUBSWS = 773;; +let _PPC_INS_VSUBUBM = 774;; +let _PPC_INS_VSUBUBS = 775;; +let _PPC_INS_VSUBUDM = 776;; +let _PPC_INS_VSUBUHM = 777;; +let _PPC_INS_VSUBUHS = 778;; +let _PPC_INS_VSUBUWM = 779;; +let _PPC_INS_VSUBUWS = 780;; +let _PPC_INS_VSUM2SWS = 781;; +let _PPC_INS_VSUM4SBS = 782;; +let _PPC_INS_VSUM4SHS = 783;; +let _PPC_INS_VSUM4UBS = 784;; +let _PPC_INS_VSUMSWS = 785;; +let _PPC_INS_VUPKHPX = 786;; +let _PPC_INS_VUPKHSB = 787;; +let _PPC_INS_VUPKHSH = 788;; +let _PPC_INS_VUPKLPX = 789;; +let _PPC_INS_VUPKLSB = 790;; +let _PPC_INS_VUPKLSH = 791;; +let _PPC_INS_VXOR = 792;; +let _PPC_INS_WAIT = 793;; +let _PPC_INS_WRTEE = 794;; +let _PPC_INS_WRTEEI = 795;; +let _PPC_INS_XOR = 796;; +let _PPC_INS_XORI = 797;; +let _PPC_INS_XORIS = 798;; +let _PPC_INS_XSABSDP = 799;; +let _PPC_INS_XSADDDP = 800;; +let _PPC_INS_XSCMPODP = 801;; +let _PPC_INS_XSCMPUDP = 802;; +let _PPC_INS_XSCPSGNDP = 803;; +let _PPC_INS_XSCVDPSP = 804;; +let _PPC_INS_XSCVDPSXDS = 805;; +let _PPC_INS_XSCVDPSXWS = 806;; +let _PPC_INS_XSCVDPUXDS = 807;; +let _PPC_INS_XSCVDPUXWS = 808;; +let _PPC_INS_XSCVSPDP = 809;; +let _PPC_INS_XSCVSXDDP = 810;; +let _PPC_INS_XSCVUXDDP = 811;; +let _PPC_INS_XSDIVDP = 812;; +let _PPC_INS_XSMADDADP = 813;; +let _PPC_INS_XSMADDMDP = 814;; +let _PPC_INS_XSMAXDP = 815;; +let _PPC_INS_XSMINDP = 816;; +let _PPC_INS_XSMSUBADP = 817;; +let _PPC_INS_XSMSUBMDP = 818;; +let _PPC_INS_XSMULDP = 819;; +let _PPC_INS_XSNABSDP = 820;; +let _PPC_INS_XSNEGDP = 821;; +let _PPC_INS_XSNMADDADP = 822;; +let _PPC_INS_XSNMADDMDP = 823;; +let _PPC_INS_XSNMSUBADP = 824;; +let _PPC_INS_XSNMSUBMDP = 825;; +let _PPC_INS_XSRDPI = 826;; +let _PPC_INS_XSRDPIC = 827;; +let _PPC_INS_XSRDPIM = 828;; +let _PPC_INS_XSRDPIP = 829;; +let _PPC_INS_XSRDPIZ = 830;; +let _PPC_INS_XSREDP = 831;; +let _PPC_INS_XSRSQRTEDP = 832;; +let _PPC_INS_XSSQRTDP = 833;; +let _PPC_INS_XSSUBDP = 834;; +let _PPC_INS_XSTDIVDP = 835;; +let _PPC_INS_XSTSQRTDP = 836;; +let _PPC_INS_XVABSDP = 837;; +let _PPC_INS_XVABSSP = 838;; +let _PPC_INS_XVADDDP = 839;; +let _PPC_INS_XVADDSP = 840;; +let _PPC_INS_XVCMPEQDP = 841;; +let _PPC_INS_XVCMPEQSP = 842;; +let _PPC_INS_XVCMPGEDP = 843;; +let _PPC_INS_XVCMPGESP = 844;; +let _PPC_INS_XVCMPGTDP = 845;; +let _PPC_INS_XVCMPGTSP = 846;; +let _PPC_INS_XVCPSGNDP = 847;; +let _PPC_INS_XVCPSGNSP = 848;; +let _PPC_INS_XVCVDPSP = 849;; +let _PPC_INS_XVCVDPSXDS = 850;; +let _PPC_INS_XVCVDPSXWS = 851;; +let _PPC_INS_XVCVDPUXDS = 852;; +let _PPC_INS_XVCVDPUXWS = 853;; +let _PPC_INS_XVCVSPDP = 854;; +let _PPC_INS_XVCVSPSXDS = 855;; +let _PPC_INS_XVCVSPSXWS = 856;; +let _PPC_INS_XVCVSPUXDS = 857;; +let _PPC_INS_XVCVSPUXWS = 858;; +let _PPC_INS_XVCVSXDDP = 859;; +let _PPC_INS_XVCVSXDSP = 860;; +let _PPC_INS_XVCVSXWDP = 861;; +let _PPC_INS_XVCVSXWSP = 862;; +let _PPC_INS_XVCVUXDDP = 863;; +let _PPC_INS_XVCVUXDSP = 864;; +let _PPC_INS_XVCVUXWDP = 865;; +let _PPC_INS_XVCVUXWSP = 866;; +let _PPC_INS_XVDIVDP = 867;; +let _PPC_INS_XVDIVSP = 868;; +let _PPC_INS_XVMADDADP = 869;; +let _PPC_INS_XVMADDASP = 870;; +let _PPC_INS_XVMADDMDP = 871;; +let _PPC_INS_XVMADDMSP = 872;; +let _PPC_INS_XVMAXDP = 873;; +let _PPC_INS_XVMAXSP = 874;; +let _PPC_INS_XVMINDP = 875;; +let _PPC_INS_XVMINSP = 876;; +let _PPC_INS_XVMSUBADP = 877;; +let _PPC_INS_XVMSUBASP = 878;; +let _PPC_INS_XVMSUBMDP = 879;; +let _PPC_INS_XVMSUBMSP = 880;; +let _PPC_INS_XVMULDP = 881;; +let _PPC_INS_XVMULSP = 882;; +let _PPC_INS_XVNABSDP = 883;; +let _PPC_INS_XVNABSSP = 884;; +let _PPC_INS_XVNEGDP = 885;; +let _PPC_INS_XVNEGSP = 886;; +let _PPC_INS_XVNMADDADP = 887;; +let _PPC_INS_XVNMADDASP = 888;; +let _PPC_INS_XVNMADDMDP = 889;; +let _PPC_INS_XVNMADDMSP = 890;; +let _PPC_INS_XVNMSUBADP = 891;; +let _PPC_INS_XVNMSUBASP = 892;; +let _PPC_INS_XVNMSUBMDP = 893;; +let _PPC_INS_XVNMSUBMSP = 894;; +let _PPC_INS_XVRDPI = 895;; +let _PPC_INS_XVRDPIC = 896;; +let _PPC_INS_XVRDPIM = 897;; +let _PPC_INS_XVRDPIP = 898;; +let _PPC_INS_XVRDPIZ = 899;; +let _PPC_INS_XVREDP = 900;; +let _PPC_INS_XVRESP = 901;; +let _PPC_INS_XVRSPI = 902;; +let _PPC_INS_XVRSPIC = 903;; +let _PPC_INS_XVRSPIM = 904;; +let _PPC_INS_XVRSPIP = 905;; +let _PPC_INS_XVRSPIZ = 906;; +let _PPC_INS_XVRSQRTEDP = 907;; +let _PPC_INS_XVRSQRTESP = 908;; +let _PPC_INS_XVSQRTDP = 909;; +let _PPC_INS_XVSQRTSP = 910;; +let _PPC_INS_XVSUBDP = 911;; +let _PPC_INS_XVSUBSP = 912;; +let _PPC_INS_XVTDIVDP = 913;; +let _PPC_INS_XVTDIVSP = 914;; +let _PPC_INS_XVTSQRTDP = 915;; +let _PPC_INS_XVTSQRTSP = 916;; +let _PPC_INS_XXLAND = 917;; +let _PPC_INS_XXLANDC = 918;; +let _PPC_INS_XXLEQV = 919;; +let _PPC_INS_XXLNAND = 920;; +let _PPC_INS_XXLNOR = 921;; +let _PPC_INS_XXLOR = 922;; +let _PPC_INS_XXLORC = 923;; +let _PPC_INS_XXLXOR = 924;; +let _PPC_INS_XXMRGHW = 925;; +let _PPC_INS_XXMRGLW = 926;; +let _PPC_INS_XXPERMDI = 927;; +let _PPC_INS_XXSEL = 928;; +let _PPC_INS_XXSLDWI = 929;; +let _PPC_INS_XXSPLTW = 930;; +let _PPC_INS_BCA = 931;; +let _PPC_INS_BCLA = 932;; +let _PPC_INS_SLWI = 933;; +let _PPC_INS_SRWI = 934;; +let _PPC_INS_SLDI = 935;; +let _PPC_INS_BTA = 936;; +let _PPC_INS_CRSET = 937;; +let _PPC_INS_CRNOT = 938;; +let _PPC_INS_CRMOVE = 939;; +let _PPC_INS_CRCLR = 940;; +let _PPC_INS_MFBR0 = 941;; +let _PPC_INS_MFBR1 = 942;; +let _PPC_INS_MFBR2 = 943;; +let _PPC_INS_MFBR3 = 944;; +let _PPC_INS_MFBR4 = 945;; +let _PPC_INS_MFBR5 = 946;; +let _PPC_INS_MFBR6 = 947;; +let _PPC_INS_MFBR7 = 948;; +let _PPC_INS_MFXER = 949;; +let _PPC_INS_MFRTCU = 950;; +let _PPC_INS_MFRTCL = 951;; +let _PPC_INS_MFDSCR = 952;; +let _PPC_INS_MFDSISR = 953;; +let _PPC_INS_MFDAR = 954;; +let _PPC_INS_MFSRR2 = 955;; +let _PPC_INS_MFSRR3 = 956;; +let _PPC_INS_MFCFAR = 957;; +let _PPC_INS_MFAMR = 958;; +let _PPC_INS_MFPID = 959;; +let _PPC_INS_MFTBLO = 960;; +let _PPC_INS_MFTBHI = 961;; +let _PPC_INS_MFDBATU = 962;; +let _PPC_INS_MFDBATL = 963;; +let _PPC_INS_MFIBATU = 964;; +let _PPC_INS_MFIBATL = 965;; +let _PPC_INS_MFDCCR = 966;; +let _PPC_INS_MFICCR = 967;; +let _PPC_INS_MFDEAR = 968;; +let _PPC_INS_MFESR = 969;; +let _PPC_INS_MFSPEFSCR = 970;; +let _PPC_INS_MFTCR = 971;; +let _PPC_INS_MFASR = 972;; +let _PPC_INS_MFPVR = 973;; +let _PPC_INS_MFTBU = 974;; +let _PPC_INS_MTCR = 975;; +let _PPC_INS_MTBR0 = 976;; +let _PPC_INS_MTBR1 = 977;; +let _PPC_INS_MTBR2 = 978;; +let _PPC_INS_MTBR3 = 979;; +let _PPC_INS_MTBR4 = 980;; +let _PPC_INS_MTBR5 = 981;; +let _PPC_INS_MTBR6 = 982;; +let _PPC_INS_MTBR7 = 983;; +let _PPC_INS_MTXER = 984;; +let _PPC_INS_MTDSCR = 985;; +let _PPC_INS_MTDSISR = 986;; +let _PPC_INS_MTDAR = 987;; +let _PPC_INS_MTSRR2 = 988;; +let _PPC_INS_MTSRR3 = 989;; +let _PPC_INS_MTCFAR = 990;; +let _PPC_INS_MTAMR = 991;; +let _PPC_INS_MTPID = 992;; +let _PPC_INS_MTTBL = 993;; +let _PPC_INS_MTTBU = 994;; +let _PPC_INS_MTTBLO = 995;; +let _PPC_INS_MTTBHI = 996;; +let _PPC_INS_MTDBATU = 997;; +let _PPC_INS_MTDBATL = 998;; +let _PPC_INS_MTIBATU = 999;; +let _PPC_INS_MTIBATL = 1000;; +let _PPC_INS_MTDCCR = 1001;; +let _PPC_INS_MTICCR = 1002;; +let _PPC_INS_MTDEAR = 1003;; +let _PPC_INS_MTESR = 1004;; +let _PPC_INS_MTSPEFSCR = 1005;; +let _PPC_INS_MTTCR = 1006;; +let _PPC_INS_NOT = 1007;; +let _PPC_INS_MR = 1008;; +let _PPC_INS_ROTLD = 1009;; +let _PPC_INS_ROTLDI = 1010;; +let _PPC_INS_CLRLDI = 1011;; +let _PPC_INS_ROTLWI = 1012;; +let _PPC_INS_CLRLWI = 1013;; +let _PPC_INS_ROTLW = 1014;; +let _PPC_INS_SUB = 1015;; +let _PPC_INS_SUBC = 1016;; +let _PPC_INS_LWSYNC = 1017;; +let _PPC_INS_PTESYNC = 1018;; +let _PPC_INS_TDLT = 1019;; +let _PPC_INS_TDEQ = 1020;; +let _PPC_INS_TDGT = 1021;; +let _PPC_INS_TDNE = 1022;; +let _PPC_INS_TDLLT = 1023;; +let _PPC_INS_TDLGT = 1024;; +let _PPC_INS_TDU = 1025;; +let _PPC_INS_TDLTI = 1026;; +let _PPC_INS_TDEQI = 1027;; +let _PPC_INS_TDGTI = 1028;; +let _PPC_INS_TDNEI = 1029;; +let _PPC_INS_TDLLTI = 1030;; +let _PPC_INS_TDLGTI = 1031;; +let _PPC_INS_TDUI = 1032;; +let _PPC_INS_TLBREHI = 1033;; +let _PPC_INS_TLBRELO = 1034;; +let _PPC_INS_TLBWEHI = 1035;; +let _PPC_INS_TLBWELO = 1036;; +let _PPC_INS_TWLT = 1037;; +let _PPC_INS_TWEQ = 1038;; +let _PPC_INS_TWGT = 1039;; +let _PPC_INS_TWNE = 1040;; +let _PPC_INS_TWLLT = 1041;; +let _PPC_INS_TWLGT = 1042;; +let _PPC_INS_TWU = 1043;; +let _PPC_INS_TWLTI = 1044;; +let _PPC_INS_TWEQI = 1045;; +let _PPC_INS_TWGTI = 1046;; +let _PPC_INS_TWNEI = 1047;; +let _PPC_INS_TWLLTI = 1048;; +let _PPC_INS_TWLGTI = 1049;; +let _PPC_INS_TWUI = 1050;; +let _PPC_INS_WAITRSV = 1051;; +let _PPC_INS_WAITIMPL = 1052;; +let _PPC_INS_XNOP = 1053;; +let _PPC_INS_XVMOVDP = 1054;; +let _PPC_INS_XVMOVSP = 1055;; +let _PPC_INS_XXSPLTD = 1056;; +let _PPC_INS_XXMRGHD = 1057;; +let _PPC_INS_XXMRGLD = 1058;; +let _PPC_INS_XXSWAPD = 1059;; +let _PPC_INS_BT = 1060;; +let _PPC_INS_BF = 1061;; +let _PPC_INS_BDNZT = 1062;; +let _PPC_INS_BDNZF = 1063;; +let _PPC_INS_BDZF = 1064;; +let _PPC_INS_BDZT = 1065;; +let _PPC_INS_BFA = 1066;; +let _PPC_INS_BDNZTA = 1067;; +let _PPC_INS_BDNZFA = 1068;; +let _PPC_INS_BDZTA = 1069;; +let _PPC_INS_BDZFA = 1070;; +let _PPC_INS_BTCTR = 1071;; +let _PPC_INS_BFCTR = 1072;; +let _PPC_INS_BTCTRL = 1073;; +let _PPC_INS_BFCTRL = 1074;; +let _PPC_INS_BTL = 1075;; +let _PPC_INS_BFL = 1076;; +let _PPC_INS_BDNZTL = 1077;; +let _PPC_INS_BDNZFL = 1078;; +let _PPC_INS_BDZTL = 1079;; +let _PPC_INS_BDZFL = 1080;; +let _PPC_INS_BTLA = 1081;; +let _PPC_INS_BFLA = 1082;; +let _PPC_INS_BDNZTLA = 1083;; +let _PPC_INS_BDNZFLA = 1084;; +let _PPC_INS_BDZTLA = 1085;; +let _PPC_INS_BDZFLA = 1086;; +let _PPC_INS_BTLR = 1087;; +let _PPC_INS_BFLR = 1088;; +let _PPC_INS_BDNZTLR = 1089;; +let _PPC_INS_BDZTLR = 1090;; +let _PPC_INS_BDZFLR = 1091;; +let _PPC_INS_BTLRL = 1092;; +let _PPC_INS_BFLRL = 1093;; +let _PPC_INS_BDNZTLRL = 1094;; +let _PPC_INS_BDNZFLRL = 1095;; +let _PPC_INS_BDZTLRL = 1096;; +let _PPC_INS_BDZFLRL = 1097;; +let _PPC_INS_QVFAND = 1098;; +let _PPC_INS_QVFCLR = 1099;; +let _PPC_INS_QVFANDC = 1100;; +let _PPC_INS_QVFCTFB = 1101;; +let _PPC_INS_QVFXOR = 1102;; +let _PPC_INS_QVFOR = 1103;; +let _PPC_INS_QVFNOR = 1104;; +let _PPC_INS_QVFEQU = 1105;; +let _PPC_INS_QVFNOT = 1106;; +let _PPC_INS_QVFORC = 1107;; +let _PPC_INS_QVFNAND = 1108;; +let _PPC_INS_QVFSET = 1109;; +let _PPC_INS_ENDING = 1110;; + +let _PPC_GRP_INVALID = 0;; +let _PPC_GRP_JUMP = 1;; +let _PPC_GRP_ALTIVEC = 128;; +let _PPC_GRP_MODE32 = 129;; +let _PPC_GRP_MODE64 = 130;; +let _PPC_GRP_BOOKE = 131;; +let _PPC_GRP_NOTBOOKE = 132;; +let _PPC_GRP_SPE = 133;; +let _PPC_GRP_VSX = 134;; +let _PPC_GRP_E500 = 135;; +let _PPC_GRP_PPC4XX = 136;; +let _PPC_GRP_PPC6XX = 137;; +let _PPC_GRP_ICBT = 138;; +let _PPC_GRP_P8ALTIVEC = 139;; +let _PPC_GRP_P8VECTOR = 140;; +let _PPC_GRP_QPX = 141;; +let _PPC_GRP_ENDING = 142;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/sparc.ml b/white_patch_detect/capstone-master/bindings/ocaml/sparc.ml new file mode 100644 index 0000000..17df4b3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/sparc.ml @@ -0,0 +1,27 @@ +(* Capstone Disassembly Engine + * By Guillaume Jeanne , 2014> *) + +open Sparc_const + +type sparc_op_mem = { + base: int; + index: int; + disp: int; +} + +type sparc_op_value = + | SPARC_OP_INVALID of int + | SPARC_OP_REG of int + | SPARC_OP_IMM of int + | SPARC_OP_MEM of sparc_op_mem + +type sparc_op = { + value: sparc_op_value; +} + +type cs_sparc = { + cc: int; + hint: int; + operands: sparc_op array; +} + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/sparc_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/sparc_const.ml new file mode 100644 index 0000000..000dbfe --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/sparc_const.ml @@ -0,0 +1,429 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.ml] *) + +let _SPARC_CC_INVALID = 0;; +let _SPARC_CC_ICC_A = 8+256;; +let _SPARC_CC_ICC_N = 0+256;; +let _SPARC_CC_ICC_NE = 9+256;; +let _SPARC_CC_ICC_E = 1+256;; +let _SPARC_CC_ICC_G = 10+256;; +let _SPARC_CC_ICC_LE = 2+256;; +let _SPARC_CC_ICC_GE = 11+256;; +let _SPARC_CC_ICC_L = 3+256;; +let _SPARC_CC_ICC_GU = 12+256;; +let _SPARC_CC_ICC_LEU = 4+256;; +let _SPARC_CC_ICC_CC = 13+256;; +let _SPARC_CC_ICC_CS = 5+256;; +let _SPARC_CC_ICC_POS = 14+256;; +let _SPARC_CC_ICC_NEG = 6+256;; +let _SPARC_CC_ICC_VC = 15+256;; +let _SPARC_CC_ICC_VS = 7+256;; +let _SPARC_CC_FCC_A = 8+16+256;; +let _SPARC_CC_FCC_N = 0+16+256;; +let _SPARC_CC_FCC_U = 7+16+256;; +let _SPARC_CC_FCC_G = 6+16+256;; +let _SPARC_CC_FCC_UG = 5+16+256;; +let _SPARC_CC_FCC_L = 4+16+256;; +let _SPARC_CC_FCC_UL = 3+16+256;; +let _SPARC_CC_FCC_LG = 2+16+256;; +let _SPARC_CC_FCC_NE = 1+16+256;; +let _SPARC_CC_FCC_E = 9+16+256;; +let _SPARC_CC_FCC_UE = 10+16+256;; +let _SPARC_CC_FCC_GE = 11+16+256;; +let _SPARC_CC_FCC_UGE = 12+16+256;; +let _SPARC_CC_FCC_LE = 13+16+256;; +let _SPARC_CC_FCC_ULE = 14+16+256;; +let _SPARC_CC_FCC_O = 15+16+256;; + +let _SPARC_HINT_INVALID = 0;; +let _SPARC_HINT_A = 1 lsl 0;; +let _SPARC_HINT_PT = 1 lsl 1;; +let _SPARC_HINT_PN = 1 lsl 2;; + +let _SPARC_OP_INVALID = 0;; +let _SPARC_OP_REG = 1;; +let _SPARC_OP_IMM = 2;; +let _SPARC_OP_MEM = 3;; + +let _SPARC_REG_INVALID = 0;; +let _SPARC_REG_F0 = 1;; +let _SPARC_REG_F1 = 2;; +let _SPARC_REG_F2 = 3;; +let _SPARC_REG_F3 = 4;; +let _SPARC_REG_F4 = 5;; +let _SPARC_REG_F5 = 6;; +let _SPARC_REG_F6 = 7;; +let _SPARC_REG_F7 = 8;; +let _SPARC_REG_F8 = 9;; +let _SPARC_REG_F9 = 10;; +let _SPARC_REG_F10 = 11;; +let _SPARC_REG_F11 = 12;; +let _SPARC_REG_F12 = 13;; +let _SPARC_REG_F13 = 14;; +let _SPARC_REG_F14 = 15;; +let _SPARC_REG_F15 = 16;; +let _SPARC_REG_F16 = 17;; +let _SPARC_REG_F17 = 18;; +let _SPARC_REG_F18 = 19;; +let _SPARC_REG_F19 = 20;; +let _SPARC_REG_F20 = 21;; +let _SPARC_REG_F21 = 22;; +let _SPARC_REG_F22 = 23;; +let _SPARC_REG_F23 = 24;; +let _SPARC_REG_F24 = 25;; +let _SPARC_REG_F25 = 26;; +let _SPARC_REG_F26 = 27;; +let _SPARC_REG_F27 = 28;; +let _SPARC_REG_F28 = 29;; +let _SPARC_REG_F29 = 30;; +let _SPARC_REG_F30 = 31;; +let _SPARC_REG_F31 = 32;; +let _SPARC_REG_F32 = 33;; +let _SPARC_REG_F34 = 34;; +let _SPARC_REG_F36 = 35;; +let _SPARC_REG_F38 = 36;; +let _SPARC_REG_F40 = 37;; +let _SPARC_REG_F42 = 38;; +let _SPARC_REG_F44 = 39;; +let _SPARC_REG_F46 = 40;; +let _SPARC_REG_F48 = 41;; +let _SPARC_REG_F50 = 42;; +let _SPARC_REG_F52 = 43;; +let _SPARC_REG_F54 = 44;; +let _SPARC_REG_F56 = 45;; +let _SPARC_REG_F58 = 46;; +let _SPARC_REG_F60 = 47;; +let _SPARC_REG_F62 = 48;; +let _SPARC_REG_FCC0 = 49;; +let _SPARC_REG_FCC1 = 50;; +let _SPARC_REG_FCC2 = 51;; +let _SPARC_REG_FCC3 = 52;; +let _SPARC_REG_FP = 53;; +let _SPARC_REG_G0 = 54;; +let _SPARC_REG_G1 = 55;; +let _SPARC_REG_G2 = 56;; +let _SPARC_REG_G3 = 57;; +let _SPARC_REG_G4 = 58;; +let _SPARC_REG_G5 = 59;; +let _SPARC_REG_G6 = 60;; +let _SPARC_REG_G7 = 61;; +let _SPARC_REG_I0 = 62;; +let _SPARC_REG_I1 = 63;; +let _SPARC_REG_I2 = 64;; +let _SPARC_REG_I3 = 65;; +let _SPARC_REG_I4 = 66;; +let _SPARC_REG_I5 = 67;; +let _SPARC_REG_I7 = 68;; +let _SPARC_REG_ICC = 69;; +let _SPARC_REG_L0 = 70;; +let _SPARC_REG_L1 = 71;; +let _SPARC_REG_L2 = 72;; +let _SPARC_REG_L3 = 73;; +let _SPARC_REG_L4 = 74;; +let _SPARC_REG_L5 = 75;; +let _SPARC_REG_L6 = 76;; +let _SPARC_REG_L7 = 77;; +let _SPARC_REG_O0 = 78;; +let _SPARC_REG_O1 = 79;; +let _SPARC_REG_O2 = 80;; +let _SPARC_REG_O3 = 81;; +let _SPARC_REG_O4 = 82;; +let _SPARC_REG_O5 = 83;; +let _SPARC_REG_O7 = 84;; +let _SPARC_REG_SP = 85;; +let _SPARC_REG_Y = 86;; +let _SPARC_REG_XCC = 87;; +let _SPARC_REG_ENDING = 88;; +let _SPARC_REG_O6 = _SPARC_REG_SP;; +let _SPARC_REG_I6 = _SPARC_REG_FP;; + +let _SPARC_INS_INVALID = 0;; +let _SPARC_INS_ADDCC = 1;; +let _SPARC_INS_ADDX = 2;; +let _SPARC_INS_ADDXCC = 3;; +let _SPARC_INS_ADDXC = 4;; +let _SPARC_INS_ADDXCCC = 5;; +let _SPARC_INS_ADD = 6;; +let _SPARC_INS_ALIGNADDR = 7;; +let _SPARC_INS_ALIGNADDRL = 8;; +let _SPARC_INS_ANDCC = 9;; +let _SPARC_INS_ANDNCC = 10;; +let _SPARC_INS_ANDN = 11;; +let _SPARC_INS_AND = 12;; +let _SPARC_INS_ARRAY16 = 13;; +let _SPARC_INS_ARRAY32 = 14;; +let _SPARC_INS_ARRAY8 = 15;; +let _SPARC_INS_B = 16;; +let _SPARC_INS_JMP = 17;; +let _SPARC_INS_BMASK = 18;; +let _SPARC_INS_FB = 19;; +let _SPARC_INS_BRGEZ = 20;; +let _SPARC_INS_BRGZ = 21;; +let _SPARC_INS_BRLEZ = 22;; +let _SPARC_INS_BRLZ = 23;; +let _SPARC_INS_BRNZ = 24;; +let _SPARC_INS_BRZ = 25;; +let _SPARC_INS_BSHUFFLE = 26;; +let _SPARC_INS_CALL = 27;; +let _SPARC_INS_CASX = 28;; +let _SPARC_INS_CAS = 29;; +let _SPARC_INS_CMASK16 = 30;; +let _SPARC_INS_CMASK32 = 31;; +let _SPARC_INS_CMASK8 = 32;; +let _SPARC_INS_CMP = 33;; +let _SPARC_INS_EDGE16 = 34;; +let _SPARC_INS_EDGE16L = 35;; +let _SPARC_INS_EDGE16LN = 36;; +let _SPARC_INS_EDGE16N = 37;; +let _SPARC_INS_EDGE32 = 38;; +let _SPARC_INS_EDGE32L = 39;; +let _SPARC_INS_EDGE32LN = 40;; +let _SPARC_INS_EDGE32N = 41;; +let _SPARC_INS_EDGE8 = 42;; +let _SPARC_INS_EDGE8L = 43;; +let _SPARC_INS_EDGE8LN = 44;; +let _SPARC_INS_EDGE8N = 45;; +let _SPARC_INS_FABSD = 46;; +let _SPARC_INS_FABSQ = 47;; +let _SPARC_INS_FABSS = 48;; +let _SPARC_INS_FADDD = 49;; +let _SPARC_INS_FADDQ = 50;; +let _SPARC_INS_FADDS = 51;; +let _SPARC_INS_FALIGNDATA = 52;; +let _SPARC_INS_FAND = 53;; +let _SPARC_INS_FANDNOT1 = 54;; +let _SPARC_INS_FANDNOT1S = 55;; +let _SPARC_INS_FANDNOT2 = 56;; +let _SPARC_INS_FANDNOT2S = 57;; +let _SPARC_INS_FANDS = 58;; +let _SPARC_INS_FCHKSM16 = 59;; +let _SPARC_INS_FCMPD = 60;; +let _SPARC_INS_FCMPEQ16 = 61;; +let _SPARC_INS_FCMPEQ32 = 62;; +let _SPARC_INS_FCMPGT16 = 63;; +let _SPARC_INS_FCMPGT32 = 64;; +let _SPARC_INS_FCMPLE16 = 65;; +let _SPARC_INS_FCMPLE32 = 66;; +let _SPARC_INS_FCMPNE16 = 67;; +let _SPARC_INS_FCMPNE32 = 68;; +let _SPARC_INS_FCMPQ = 69;; +let _SPARC_INS_FCMPS = 70;; +let _SPARC_INS_FDIVD = 71;; +let _SPARC_INS_FDIVQ = 72;; +let _SPARC_INS_FDIVS = 73;; +let _SPARC_INS_FDMULQ = 74;; +let _SPARC_INS_FDTOI = 75;; +let _SPARC_INS_FDTOQ = 76;; +let _SPARC_INS_FDTOS = 77;; +let _SPARC_INS_FDTOX = 78;; +let _SPARC_INS_FEXPAND = 79;; +let _SPARC_INS_FHADDD = 80;; +let _SPARC_INS_FHADDS = 81;; +let _SPARC_INS_FHSUBD = 82;; +let _SPARC_INS_FHSUBS = 83;; +let _SPARC_INS_FITOD = 84;; +let _SPARC_INS_FITOQ = 85;; +let _SPARC_INS_FITOS = 86;; +let _SPARC_INS_FLCMPD = 87;; +let _SPARC_INS_FLCMPS = 88;; +let _SPARC_INS_FLUSHW = 89;; +let _SPARC_INS_FMEAN16 = 90;; +let _SPARC_INS_FMOVD = 91;; +let _SPARC_INS_FMOVQ = 92;; +let _SPARC_INS_FMOVRDGEZ = 93;; +let _SPARC_INS_FMOVRQGEZ = 94;; +let _SPARC_INS_FMOVRSGEZ = 95;; +let _SPARC_INS_FMOVRDGZ = 96;; +let _SPARC_INS_FMOVRQGZ = 97;; +let _SPARC_INS_FMOVRSGZ = 98;; +let _SPARC_INS_FMOVRDLEZ = 99;; +let _SPARC_INS_FMOVRQLEZ = 100;; +let _SPARC_INS_FMOVRSLEZ = 101;; +let _SPARC_INS_FMOVRDLZ = 102;; +let _SPARC_INS_FMOVRQLZ = 103;; +let _SPARC_INS_FMOVRSLZ = 104;; +let _SPARC_INS_FMOVRDNZ = 105;; +let _SPARC_INS_FMOVRQNZ = 106;; +let _SPARC_INS_FMOVRSNZ = 107;; +let _SPARC_INS_FMOVRDZ = 108;; +let _SPARC_INS_FMOVRQZ = 109;; +let _SPARC_INS_FMOVRSZ = 110;; +let _SPARC_INS_FMOVS = 111;; +let _SPARC_INS_FMUL8SUX16 = 112;; +let _SPARC_INS_FMUL8ULX16 = 113;; +let _SPARC_INS_FMUL8X16 = 114;; +let _SPARC_INS_FMUL8X16AL = 115;; +let _SPARC_INS_FMUL8X16AU = 116;; +let _SPARC_INS_FMULD = 117;; +let _SPARC_INS_FMULD8SUX16 = 118;; +let _SPARC_INS_FMULD8ULX16 = 119;; +let _SPARC_INS_FMULQ = 120;; +let _SPARC_INS_FMULS = 121;; +let _SPARC_INS_FNADDD = 122;; +let _SPARC_INS_FNADDS = 123;; +let _SPARC_INS_FNAND = 124;; +let _SPARC_INS_FNANDS = 125;; +let _SPARC_INS_FNEGD = 126;; +let _SPARC_INS_FNEGQ = 127;; +let _SPARC_INS_FNEGS = 128;; +let _SPARC_INS_FNHADDD = 129;; +let _SPARC_INS_FNHADDS = 130;; +let _SPARC_INS_FNOR = 131;; +let _SPARC_INS_FNORS = 132;; +let _SPARC_INS_FNOT1 = 133;; +let _SPARC_INS_FNOT1S = 134;; +let _SPARC_INS_FNOT2 = 135;; +let _SPARC_INS_FNOT2S = 136;; +let _SPARC_INS_FONE = 137;; +let _SPARC_INS_FONES = 138;; +let _SPARC_INS_FOR = 139;; +let _SPARC_INS_FORNOT1 = 140;; +let _SPARC_INS_FORNOT1S = 141;; +let _SPARC_INS_FORNOT2 = 142;; +let _SPARC_INS_FORNOT2S = 143;; +let _SPARC_INS_FORS = 144;; +let _SPARC_INS_FPACK16 = 145;; +let _SPARC_INS_FPACK32 = 146;; +let _SPARC_INS_FPACKFIX = 147;; +let _SPARC_INS_FPADD16 = 148;; +let _SPARC_INS_FPADD16S = 149;; +let _SPARC_INS_FPADD32 = 150;; +let _SPARC_INS_FPADD32S = 151;; +let _SPARC_INS_FPADD64 = 152;; +let _SPARC_INS_FPMERGE = 153;; +let _SPARC_INS_FPSUB16 = 154;; +let _SPARC_INS_FPSUB16S = 155;; +let _SPARC_INS_FPSUB32 = 156;; +let _SPARC_INS_FPSUB32S = 157;; +let _SPARC_INS_FQTOD = 158;; +let _SPARC_INS_FQTOI = 159;; +let _SPARC_INS_FQTOS = 160;; +let _SPARC_INS_FQTOX = 161;; +let _SPARC_INS_FSLAS16 = 162;; +let _SPARC_INS_FSLAS32 = 163;; +let _SPARC_INS_FSLL16 = 164;; +let _SPARC_INS_FSLL32 = 165;; +let _SPARC_INS_FSMULD = 166;; +let _SPARC_INS_FSQRTD = 167;; +let _SPARC_INS_FSQRTQ = 168;; +let _SPARC_INS_FSQRTS = 169;; +let _SPARC_INS_FSRA16 = 170;; +let _SPARC_INS_FSRA32 = 171;; +let _SPARC_INS_FSRC1 = 172;; +let _SPARC_INS_FSRC1S = 173;; +let _SPARC_INS_FSRC2 = 174;; +let _SPARC_INS_FSRC2S = 175;; +let _SPARC_INS_FSRL16 = 176;; +let _SPARC_INS_FSRL32 = 177;; +let _SPARC_INS_FSTOD = 178;; +let _SPARC_INS_FSTOI = 179;; +let _SPARC_INS_FSTOQ = 180;; +let _SPARC_INS_FSTOX = 181;; +let _SPARC_INS_FSUBD = 182;; +let _SPARC_INS_FSUBQ = 183;; +let _SPARC_INS_FSUBS = 184;; +let _SPARC_INS_FXNOR = 185;; +let _SPARC_INS_FXNORS = 186;; +let _SPARC_INS_FXOR = 187;; +let _SPARC_INS_FXORS = 188;; +let _SPARC_INS_FXTOD = 189;; +let _SPARC_INS_FXTOQ = 190;; +let _SPARC_INS_FXTOS = 191;; +let _SPARC_INS_FZERO = 192;; +let _SPARC_INS_FZEROS = 193;; +let _SPARC_INS_JMPL = 194;; +let _SPARC_INS_LDD = 195;; +let _SPARC_INS_LD = 196;; +let _SPARC_INS_LDQ = 197;; +let _SPARC_INS_LDSB = 198;; +let _SPARC_INS_LDSH = 199;; +let _SPARC_INS_LDSW = 200;; +let _SPARC_INS_LDUB = 201;; +let _SPARC_INS_LDUH = 202;; +let _SPARC_INS_LDX = 203;; +let _SPARC_INS_LZCNT = 204;; +let _SPARC_INS_MEMBAR = 205;; +let _SPARC_INS_MOVDTOX = 206;; +let _SPARC_INS_MOV = 207;; +let _SPARC_INS_MOVRGEZ = 208;; +let _SPARC_INS_MOVRGZ = 209;; +let _SPARC_INS_MOVRLEZ = 210;; +let _SPARC_INS_MOVRLZ = 211;; +let _SPARC_INS_MOVRNZ = 212;; +let _SPARC_INS_MOVRZ = 213;; +let _SPARC_INS_MOVSTOSW = 214;; +let _SPARC_INS_MOVSTOUW = 215;; +let _SPARC_INS_MULX = 216;; +let _SPARC_INS_NOP = 217;; +let _SPARC_INS_ORCC = 218;; +let _SPARC_INS_ORNCC = 219;; +let _SPARC_INS_ORN = 220;; +let _SPARC_INS_OR = 221;; +let _SPARC_INS_PDIST = 222;; +let _SPARC_INS_PDISTN = 223;; +let _SPARC_INS_POPC = 224;; +let _SPARC_INS_RD = 225;; +let _SPARC_INS_RESTORE = 226;; +let _SPARC_INS_RETT = 227;; +let _SPARC_INS_SAVE = 228;; +let _SPARC_INS_SDIVCC = 229;; +let _SPARC_INS_SDIVX = 230;; +let _SPARC_INS_SDIV = 231;; +let _SPARC_INS_SETHI = 232;; +let _SPARC_INS_SHUTDOWN = 233;; +let _SPARC_INS_SIAM = 234;; +let _SPARC_INS_SLLX = 235;; +let _SPARC_INS_SLL = 236;; +let _SPARC_INS_SMULCC = 237;; +let _SPARC_INS_SMUL = 238;; +let _SPARC_INS_SRAX = 239;; +let _SPARC_INS_SRA = 240;; +let _SPARC_INS_SRLX = 241;; +let _SPARC_INS_SRL = 242;; +let _SPARC_INS_STBAR = 243;; +let _SPARC_INS_STB = 244;; +let _SPARC_INS_STD = 245;; +let _SPARC_INS_ST = 246;; +let _SPARC_INS_STH = 247;; +let _SPARC_INS_STQ = 248;; +let _SPARC_INS_STX = 249;; +let _SPARC_INS_SUBCC = 250;; +let _SPARC_INS_SUBX = 251;; +let _SPARC_INS_SUBXCC = 252;; +let _SPARC_INS_SUB = 253;; +let _SPARC_INS_SWAP = 254;; +let _SPARC_INS_TADDCCTV = 255;; +let _SPARC_INS_TADDCC = 256;; +let _SPARC_INS_T = 257;; +let _SPARC_INS_TSUBCCTV = 258;; +let _SPARC_INS_TSUBCC = 259;; +let _SPARC_INS_UDIVCC = 260;; +let _SPARC_INS_UDIVX = 261;; +let _SPARC_INS_UDIV = 262;; +let _SPARC_INS_UMULCC = 263;; +let _SPARC_INS_UMULXHI = 264;; +let _SPARC_INS_UMUL = 265;; +let _SPARC_INS_UNIMP = 266;; +let _SPARC_INS_FCMPED = 267;; +let _SPARC_INS_FCMPEQ = 268;; +let _SPARC_INS_FCMPES = 269;; +let _SPARC_INS_WR = 270;; +let _SPARC_INS_XMULX = 271;; +let _SPARC_INS_XMULXHI = 272;; +let _SPARC_INS_XNORCC = 273;; +let _SPARC_INS_XNOR = 274;; +let _SPARC_INS_XORCC = 275;; +let _SPARC_INS_XOR = 276;; +let _SPARC_INS_RET = 277;; +let _SPARC_INS_RETL = 278;; +let _SPARC_INS_ENDING = 279;; + +let _SPARC_GRP_INVALID = 0;; +let _SPARC_GRP_JUMP = 1;; +let _SPARC_GRP_HARDQUAD = 128;; +let _SPARC_GRP_V9 = 129;; +let _SPARC_GRP_VIS = 130;; +let _SPARC_GRP_VIS2 = 131;; +let _SPARC_GRP_VIS3 = 132;; +let _SPARC_GRP_32BIT = 133;; +let _SPARC_GRP_64BIT = 134;; +let _SPARC_GRP_ENDING = 135;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/systemz.ml b/white_patch_detect/capstone-master/bindings/ocaml/systemz.ml new file mode 100644 index 0000000..755bf5d --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/systemz.ml @@ -0,0 +1,27 @@ +(* Capstone Disassembly Engine + * By Guillaume Jeanne , 2014> *) + +open Sysz_const + +type sysz_op_mem = { + base: int; + index: int; + length: int64; + disp: int64; +} + +type sysz_op_value = + | SYSZ_OP_INVALID of int + | SYSZ_OP_REG of int + | SYSZ_OP_ACREG of int + | SYSZ_OP_IMM of int + | SYSZ_OP_MEM of sysz_op_mem + +type sysz_op = { + value: sysz_op_value; +} + +type cs_sysz = { + cc: int; + operands: sysz_op array; +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/sysz_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/sysz_const.ml new file mode 100644 index 0000000..e738b5c --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/sysz_const.ml @@ -0,0 +1,2523 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.ml] *) + +let _SYSZ_CC_INVALID = 0;; +let _SYSZ_CC_O = 1;; +let _SYSZ_CC_H = 2;; +let _SYSZ_CC_NLE = 3;; +let _SYSZ_CC_L = 4;; +let _SYSZ_CC_NHE = 5;; +let _SYSZ_CC_LH = 6;; +let _SYSZ_CC_NE = 7;; +let _SYSZ_CC_E = 8;; +let _SYSZ_CC_NLH = 9;; +let _SYSZ_CC_HE = 10;; +let _SYSZ_CC_NL = 11;; +let _SYSZ_CC_LE = 12;; +let _SYSZ_CC_NH = 13;; +let _SYSZ_CC_NO = 14;; + +let _SYSZ_OP_INVALID = 0;; +let _SYSZ_OP_REG = 1;; +let _SYSZ_OP_IMM = 2;; +let _SYSZ_OP_MEM = 3;; +let _SYSZ_OP_ACREG = 64;; + +let _SYSZ_REG_INVALID = 0;; +let _SYSZ_REG_0 = 1;; +let _SYSZ_REG_1 = 2;; +let _SYSZ_REG_2 = 3;; +let _SYSZ_REG_3 = 4;; +let _SYSZ_REG_4 = 5;; +let _SYSZ_REG_5 = 6;; +let _SYSZ_REG_6 = 7;; +let _SYSZ_REG_7 = 8;; +let _SYSZ_REG_8 = 9;; +let _SYSZ_REG_9 = 10;; +let _SYSZ_REG_10 = 11;; +let _SYSZ_REG_11 = 12;; +let _SYSZ_REG_12 = 13;; +let _SYSZ_REG_13 = 14;; +let _SYSZ_REG_14 = 15;; +let _SYSZ_REG_15 = 16;; +let _SYSZ_REG_CC = 17;; +let _SYSZ_REG_F0 = 18;; +let _SYSZ_REG_F1 = 19;; +let _SYSZ_REG_F2 = 20;; +let _SYSZ_REG_F3 = 21;; +let _SYSZ_REG_F4 = 22;; +let _SYSZ_REG_F5 = 23;; +let _SYSZ_REG_F6 = 24;; +let _SYSZ_REG_F7 = 25;; +let _SYSZ_REG_F8 = 26;; +let _SYSZ_REG_F9 = 27;; +let _SYSZ_REG_F10 = 28;; +let _SYSZ_REG_F11 = 29;; +let _SYSZ_REG_F12 = 30;; +let _SYSZ_REG_F13 = 31;; +let _SYSZ_REG_F14 = 32;; +let _SYSZ_REG_F15 = 33;; +let _SYSZ_REG_R0L = 34;; +let _SYSZ_REG_A0 = 35;; +let _SYSZ_REG_A1 = 36;; +let _SYSZ_REG_A2 = 37;; +let _SYSZ_REG_A3 = 38;; +let _SYSZ_REG_A4 = 39;; +let _SYSZ_REG_A5 = 40;; +let _SYSZ_REG_A6 = 41;; +let _SYSZ_REG_A7 = 42;; +let _SYSZ_REG_A8 = 43;; +let _SYSZ_REG_A9 = 44;; +let _SYSZ_REG_A10 = 45;; +let _SYSZ_REG_A11 = 46;; +let _SYSZ_REG_A12 = 47;; +let _SYSZ_REG_A13 = 48;; +let _SYSZ_REG_A14 = 49;; +let _SYSZ_REG_A15 = 50;; +let _SYSZ_REG_C0 = 51;; +let _SYSZ_REG_C1 = 52;; +let _SYSZ_REG_C2 = 53;; +let _SYSZ_REG_C3 = 54;; +let _SYSZ_REG_C4 = 55;; +let _SYSZ_REG_C5 = 56;; +let _SYSZ_REG_C6 = 57;; +let _SYSZ_REG_C7 = 58;; +let _SYSZ_REG_C8 = 59;; +let _SYSZ_REG_C9 = 60;; +let _SYSZ_REG_C10 = 61;; +let _SYSZ_REG_C11 = 62;; +let _SYSZ_REG_C12 = 63;; +let _SYSZ_REG_C13 = 64;; +let _SYSZ_REG_C14 = 65;; +let _SYSZ_REG_C15 = 66;; +let _SYSZ_REG_V0 = 67;; +let _SYSZ_REG_V1 = 68;; +let _SYSZ_REG_V2 = 69;; +let _SYSZ_REG_V3 = 70;; +let _SYSZ_REG_V4 = 71;; +let _SYSZ_REG_V5 = 72;; +let _SYSZ_REG_V6 = 73;; +let _SYSZ_REG_V7 = 74;; +let _SYSZ_REG_V8 = 75;; +let _SYSZ_REG_V9 = 76;; +let _SYSZ_REG_V10 = 77;; +let _SYSZ_REG_V11 = 78;; +let _SYSZ_REG_V12 = 79;; +let _SYSZ_REG_V13 = 80;; +let _SYSZ_REG_V14 = 81;; +let _SYSZ_REG_V15 = 82;; +let _SYSZ_REG_V16 = 83;; +let _SYSZ_REG_V17 = 84;; +let _SYSZ_REG_V18 = 85;; +let _SYSZ_REG_V19 = 86;; +let _SYSZ_REG_V20 = 87;; +let _SYSZ_REG_V21 = 88;; +let _SYSZ_REG_V22 = 89;; +let _SYSZ_REG_V23 = 90;; +let _SYSZ_REG_V24 = 91;; +let _SYSZ_REG_V25 = 92;; +let _SYSZ_REG_V26 = 93;; +let _SYSZ_REG_V27 = 94;; +let _SYSZ_REG_V28 = 95;; +let _SYSZ_REG_V29 = 96;; +let _SYSZ_REG_V30 = 97;; +let _SYSZ_REG_V31 = 98;; +let _SYSZ_REG_F16 = 99;; +let _SYSZ_REG_F17 = 100;; +let _SYSZ_REG_F18 = 101;; +let _SYSZ_REG_F19 = 102;; +let _SYSZ_REG_F20 = 103;; +let _SYSZ_REG_F21 = 104;; +let _SYSZ_REG_F22 = 105;; +let _SYSZ_REG_F23 = 106;; +let _SYSZ_REG_F24 = 107;; +let _SYSZ_REG_F25 = 108;; +let _SYSZ_REG_F26 = 109;; +let _SYSZ_REG_F27 = 110;; +let _SYSZ_REG_F28 = 111;; +let _SYSZ_REG_F29 = 112;; +let _SYSZ_REG_F30 = 113;; +let _SYSZ_REG_F31 = 114;; +let _SYSZ_REG_F0Q = 115;; +let _SYSZ_REG_F4Q = 116;; +let _SYSZ_REG_ENDING = 117;; + +let _SYSZ_INS_INVALID = 0;; +let _SYSZ_INS_A = 1;; +let _SYSZ_INS_ADB = 2;; +let _SYSZ_INS_ADBR = 3;; +let _SYSZ_INS_AEB = 4;; +let _SYSZ_INS_AEBR = 5;; +let _SYSZ_INS_AFI = 6;; +let _SYSZ_INS_AG = 7;; +let _SYSZ_INS_AGF = 8;; +let _SYSZ_INS_AGFI = 9;; +let _SYSZ_INS_AGFR = 10;; +let _SYSZ_INS_AGHI = 11;; +let _SYSZ_INS_AGHIK = 12;; +let _SYSZ_INS_AGR = 13;; +let _SYSZ_INS_AGRK = 14;; +let _SYSZ_INS_AGSI = 15;; +let _SYSZ_INS_AH = 16;; +let _SYSZ_INS_AHI = 17;; +let _SYSZ_INS_AHIK = 18;; +let _SYSZ_INS_AHY = 19;; +let _SYSZ_INS_AIH = 20;; +let _SYSZ_INS_AL = 21;; +let _SYSZ_INS_ALC = 22;; +let _SYSZ_INS_ALCG = 23;; +let _SYSZ_INS_ALCGR = 24;; +let _SYSZ_INS_ALCR = 25;; +let _SYSZ_INS_ALFI = 26;; +let _SYSZ_INS_ALG = 27;; +let _SYSZ_INS_ALGF = 28;; +let _SYSZ_INS_ALGFI = 29;; +let _SYSZ_INS_ALGFR = 30;; +let _SYSZ_INS_ALGHSIK = 31;; +let _SYSZ_INS_ALGR = 32;; +let _SYSZ_INS_ALGRK = 33;; +let _SYSZ_INS_ALHSIK = 34;; +let _SYSZ_INS_ALR = 35;; +let _SYSZ_INS_ALRK = 36;; +let _SYSZ_INS_ALY = 37;; +let _SYSZ_INS_AR = 38;; +let _SYSZ_INS_ARK = 39;; +let _SYSZ_INS_ASI = 40;; +let _SYSZ_INS_AXBR = 41;; +let _SYSZ_INS_AY = 42;; +let _SYSZ_INS_BCR = 43;; +let _SYSZ_INS_BRC = 44;; +let _SYSZ_INS_BRCL = 45;; +let _SYSZ_INS_CGIJ = 46;; +let _SYSZ_INS_CGRJ = 47;; +let _SYSZ_INS_CIJ = 48;; +let _SYSZ_INS_CLGIJ = 49;; +let _SYSZ_INS_CLGRJ = 50;; +let _SYSZ_INS_CLIJ = 51;; +let _SYSZ_INS_CLRJ = 52;; +let _SYSZ_INS_CRJ = 53;; +let _SYSZ_INS_BER = 54;; +let _SYSZ_INS_JE = 55;; +let _SYSZ_INS_JGE = 56;; +let _SYSZ_INS_LOCE = 57;; +let _SYSZ_INS_LOCGE = 58;; +let _SYSZ_INS_LOCGRE = 59;; +let _SYSZ_INS_LOCRE = 60;; +let _SYSZ_INS_STOCE = 61;; +let _SYSZ_INS_STOCGE = 62;; +let _SYSZ_INS_BHR = 63;; +let _SYSZ_INS_BHER = 64;; +let _SYSZ_INS_JHE = 65;; +let _SYSZ_INS_JGHE = 66;; +let _SYSZ_INS_LOCHE = 67;; +let _SYSZ_INS_LOCGHE = 68;; +let _SYSZ_INS_LOCGRHE = 69;; +let _SYSZ_INS_LOCRHE = 70;; +let _SYSZ_INS_STOCHE = 71;; +let _SYSZ_INS_STOCGHE = 72;; +let _SYSZ_INS_JH = 73;; +let _SYSZ_INS_JGH = 74;; +let _SYSZ_INS_LOCH = 75;; +let _SYSZ_INS_LOCGH = 76;; +let _SYSZ_INS_LOCGRH = 77;; +let _SYSZ_INS_LOCRH = 78;; +let _SYSZ_INS_STOCH = 79;; +let _SYSZ_INS_STOCGH = 80;; +let _SYSZ_INS_CGIJNLH = 81;; +let _SYSZ_INS_CGRJNLH = 82;; +let _SYSZ_INS_CIJNLH = 83;; +let _SYSZ_INS_CLGIJNLH = 84;; +let _SYSZ_INS_CLGRJNLH = 85;; +let _SYSZ_INS_CLIJNLH = 86;; +let _SYSZ_INS_CLRJNLH = 87;; +let _SYSZ_INS_CRJNLH = 88;; +let _SYSZ_INS_CGIJE = 89;; +let _SYSZ_INS_CGRJE = 90;; +let _SYSZ_INS_CIJE = 91;; +let _SYSZ_INS_CLGIJE = 92;; +let _SYSZ_INS_CLGRJE = 93;; +let _SYSZ_INS_CLIJE = 94;; +let _SYSZ_INS_CLRJE = 95;; +let _SYSZ_INS_CRJE = 96;; +let _SYSZ_INS_CGIJNLE = 97;; +let _SYSZ_INS_CGRJNLE = 98;; +let _SYSZ_INS_CIJNLE = 99;; +let _SYSZ_INS_CLGIJNLE = 100;; +let _SYSZ_INS_CLGRJNLE = 101;; +let _SYSZ_INS_CLIJNLE = 102;; +let _SYSZ_INS_CLRJNLE = 103;; +let _SYSZ_INS_CRJNLE = 104;; +let _SYSZ_INS_CGIJH = 105;; +let _SYSZ_INS_CGRJH = 106;; +let _SYSZ_INS_CIJH = 107;; +let _SYSZ_INS_CLGIJH = 108;; +let _SYSZ_INS_CLGRJH = 109;; +let _SYSZ_INS_CLIJH = 110;; +let _SYSZ_INS_CLRJH = 111;; +let _SYSZ_INS_CRJH = 112;; +let _SYSZ_INS_CGIJNL = 113;; +let _SYSZ_INS_CGRJNL = 114;; +let _SYSZ_INS_CIJNL = 115;; +let _SYSZ_INS_CLGIJNL = 116;; +let _SYSZ_INS_CLGRJNL = 117;; +let _SYSZ_INS_CLIJNL = 118;; +let _SYSZ_INS_CLRJNL = 119;; +let _SYSZ_INS_CRJNL = 120;; +let _SYSZ_INS_CGIJHE = 121;; +let _SYSZ_INS_CGRJHE = 122;; +let _SYSZ_INS_CIJHE = 123;; +let _SYSZ_INS_CLGIJHE = 124;; +let _SYSZ_INS_CLGRJHE = 125;; +let _SYSZ_INS_CLIJHE = 126;; +let _SYSZ_INS_CLRJHE = 127;; +let _SYSZ_INS_CRJHE = 128;; +let _SYSZ_INS_CGIJNHE = 129;; +let _SYSZ_INS_CGRJNHE = 130;; +let _SYSZ_INS_CIJNHE = 131;; +let _SYSZ_INS_CLGIJNHE = 132;; +let _SYSZ_INS_CLGRJNHE = 133;; +let _SYSZ_INS_CLIJNHE = 134;; +let _SYSZ_INS_CLRJNHE = 135;; +let _SYSZ_INS_CRJNHE = 136;; +let _SYSZ_INS_CGIJL = 137;; +let _SYSZ_INS_CGRJL = 138;; +let _SYSZ_INS_CIJL = 139;; +let _SYSZ_INS_CLGIJL = 140;; +let _SYSZ_INS_CLGRJL = 141;; +let _SYSZ_INS_CLIJL = 142;; +let _SYSZ_INS_CLRJL = 143;; +let _SYSZ_INS_CRJL = 144;; +let _SYSZ_INS_CGIJNH = 145;; +let _SYSZ_INS_CGRJNH = 146;; +let _SYSZ_INS_CIJNH = 147;; +let _SYSZ_INS_CLGIJNH = 148;; +let _SYSZ_INS_CLGRJNH = 149;; +let _SYSZ_INS_CLIJNH = 150;; +let _SYSZ_INS_CLRJNH = 151;; +let _SYSZ_INS_CRJNH = 152;; +let _SYSZ_INS_CGIJLE = 153;; +let _SYSZ_INS_CGRJLE = 154;; +let _SYSZ_INS_CIJLE = 155;; +let _SYSZ_INS_CLGIJLE = 156;; +let _SYSZ_INS_CLGRJLE = 157;; +let _SYSZ_INS_CLIJLE = 158;; +let _SYSZ_INS_CLRJLE = 159;; +let _SYSZ_INS_CRJLE = 160;; +let _SYSZ_INS_CGIJNE = 161;; +let _SYSZ_INS_CGRJNE = 162;; +let _SYSZ_INS_CIJNE = 163;; +let _SYSZ_INS_CLGIJNE = 164;; +let _SYSZ_INS_CLGRJNE = 165;; +let _SYSZ_INS_CLIJNE = 166;; +let _SYSZ_INS_CLRJNE = 167;; +let _SYSZ_INS_CRJNE = 168;; +let _SYSZ_INS_CGIJLH = 169;; +let _SYSZ_INS_CGRJLH = 170;; +let _SYSZ_INS_CIJLH = 171;; +let _SYSZ_INS_CLGIJLH = 172;; +let _SYSZ_INS_CLGRJLH = 173;; +let _SYSZ_INS_CLIJLH = 174;; +let _SYSZ_INS_CLRJLH = 175;; +let _SYSZ_INS_CRJLH = 176;; +let _SYSZ_INS_BLR = 177;; +let _SYSZ_INS_BLER = 178;; +let _SYSZ_INS_JLE = 179;; +let _SYSZ_INS_JGLE = 180;; +let _SYSZ_INS_LOCLE = 181;; +let _SYSZ_INS_LOCGLE = 182;; +let _SYSZ_INS_LOCGRLE = 183;; +let _SYSZ_INS_LOCRLE = 184;; +let _SYSZ_INS_STOCLE = 185;; +let _SYSZ_INS_STOCGLE = 186;; +let _SYSZ_INS_BLHR = 187;; +let _SYSZ_INS_JLH = 188;; +let _SYSZ_INS_JGLH = 189;; +let _SYSZ_INS_LOCLH = 190;; +let _SYSZ_INS_LOCGLH = 191;; +let _SYSZ_INS_LOCGRLH = 192;; +let _SYSZ_INS_LOCRLH = 193;; +let _SYSZ_INS_STOCLH = 194;; +let _SYSZ_INS_STOCGLH = 195;; +let _SYSZ_INS_JL = 196;; +let _SYSZ_INS_JGL = 197;; +let _SYSZ_INS_LOCL = 198;; +let _SYSZ_INS_LOCGL = 199;; +let _SYSZ_INS_LOCGRL = 200;; +let _SYSZ_INS_LOCRL = 201;; +let _SYSZ_INS_LOC = 202;; +let _SYSZ_INS_LOCG = 203;; +let _SYSZ_INS_LOCGR = 204;; +let _SYSZ_INS_LOCR = 205;; +let _SYSZ_INS_STOCL = 206;; +let _SYSZ_INS_STOCGL = 207;; +let _SYSZ_INS_BNER = 208;; +let _SYSZ_INS_JNE = 209;; +let _SYSZ_INS_JGNE = 210;; +let _SYSZ_INS_LOCNE = 211;; +let _SYSZ_INS_LOCGNE = 212;; +let _SYSZ_INS_LOCGRNE = 213;; +let _SYSZ_INS_LOCRNE = 214;; +let _SYSZ_INS_STOCNE = 215;; +let _SYSZ_INS_STOCGNE = 216;; +let _SYSZ_INS_BNHR = 217;; +let _SYSZ_INS_BNHER = 218;; +let _SYSZ_INS_JNHE = 219;; +let _SYSZ_INS_JGNHE = 220;; +let _SYSZ_INS_LOCNHE = 221;; +let _SYSZ_INS_LOCGNHE = 222;; +let _SYSZ_INS_LOCGRNHE = 223;; +let _SYSZ_INS_LOCRNHE = 224;; +let _SYSZ_INS_STOCNHE = 225;; +let _SYSZ_INS_STOCGNHE = 226;; +let _SYSZ_INS_JNH = 227;; +let _SYSZ_INS_JGNH = 228;; +let _SYSZ_INS_LOCNH = 229;; +let _SYSZ_INS_LOCGNH = 230;; +let _SYSZ_INS_LOCGRNH = 231;; +let _SYSZ_INS_LOCRNH = 232;; +let _SYSZ_INS_STOCNH = 233;; +let _SYSZ_INS_STOCGNH = 234;; +let _SYSZ_INS_BNLR = 235;; +let _SYSZ_INS_BNLER = 236;; +let _SYSZ_INS_JNLE = 237;; +let _SYSZ_INS_JGNLE = 238;; +let _SYSZ_INS_LOCNLE = 239;; +let _SYSZ_INS_LOCGNLE = 240;; +let _SYSZ_INS_LOCGRNLE = 241;; +let _SYSZ_INS_LOCRNLE = 242;; +let _SYSZ_INS_STOCNLE = 243;; +let _SYSZ_INS_STOCGNLE = 244;; +let _SYSZ_INS_BNLHR = 245;; +let _SYSZ_INS_JNLH = 246;; +let _SYSZ_INS_JGNLH = 247;; +let _SYSZ_INS_LOCNLH = 248;; +let _SYSZ_INS_LOCGNLH = 249;; +let _SYSZ_INS_LOCGRNLH = 250;; +let _SYSZ_INS_LOCRNLH = 251;; +let _SYSZ_INS_STOCNLH = 252;; +let _SYSZ_INS_STOCGNLH = 253;; +let _SYSZ_INS_JNL = 254;; +let _SYSZ_INS_JGNL = 255;; +let _SYSZ_INS_LOCNL = 256;; +let _SYSZ_INS_LOCGNL = 257;; +let _SYSZ_INS_LOCGRNL = 258;; +let _SYSZ_INS_LOCRNL = 259;; +let _SYSZ_INS_STOCNL = 260;; +let _SYSZ_INS_STOCGNL = 261;; +let _SYSZ_INS_BNOR = 262;; +let _SYSZ_INS_JNO = 263;; +let _SYSZ_INS_JGNO = 264;; +let _SYSZ_INS_LOCNO = 265;; +let _SYSZ_INS_LOCGNO = 266;; +let _SYSZ_INS_LOCGRNO = 267;; +let _SYSZ_INS_LOCRNO = 268;; +let _SYSZ_INS_STOCNO = 269;; +let _SYSZ_INS_STOCGNO = 270;; +let _SYSZ_INS_BOR = 271;; +let _SYSZ_INS_JO = 272;; +let _SYSZ_INS_JGO = 273;; +let _SYSZ_INS_LOCO = 274;; +let _SYSZ_INS_LOCGO = 275;; +let _SYSZ_INS_LOCGRO = 276;; +let _SYSZ_INS_LOCRO = 277;; +let _SYSZ_INS_STOCO = 278;; +let _SYSZ_INS_STOCGO = 279;; +let _SYSZ_INS_STOC = 280;; +let _SYSZ_INS_STOCG = 281;; +let _SYSZ_INS_BASR = 282;; +let _SYSZ_INS_BR = 283;; +let _SYSZ_INS_BRAS = 284;; +let _SYSZ_INS_BRASL = 285;; +let _SYSZ_INS_J = 286;; +let _SYSZ_INS_JG = 287;; +let _SYSZ_INS_BRCT = 288;; +let _SYSZ_INS_BRCTG = 289;; +let _SYSZ_INS_C = 290;; +let _SYSZ_INS_CDB = 291;; +let _SYSZ_INS_CDBR = 292;; +let _SYSZ_INS_CDFBR = 293;; +let _SYSZ_INS_CDGBR = 294;; +let _SYSZ_INS_CDLFBR = 295;; +let _SYSZ_INS_CDLGBR = 296;; +let _SYSZ_INS_CEB = 297;; +let _SYSZ_INS_CEBR = 298;; +let _SYSZ_INS_CEFBR = 299;; +let _SYSZ_INS_CEGBR = 300;; +let _SYSZ_INS_CELFBR = 301;; +let _SYSZ_INS_CELGBR = 302;; +let _SYSZ_INS_CFDBR = 303;; +let _SYSZ_INS_CFEBR = 304;; +let _SYSZ_INS_CFI = 305;; +let _SYSZ_INS_CFXBR = 306;; +let _SYSZ_INS_CG = 307;; +let _SYSZ_INS_CGDBR = 308;; +let _SYSZ_INS_CGEBR = 309;; +let _SYSZ_INS_CGF = 310;; +let _SYSZ_INS_CGFI = 311;; +let _SYSZ_INS_CGFR = 312;; +let _SYSZ_INS_CGFRL = 313;; +let _SYSZ_INS_CGH = 314;; +let _SYSZ_INS_CGHI = 315;; +let _SYSZ_INS_CGHRL = 316;; +let _SYSZ_INS_CGHSI = 317;; +let _SYSZ_INS_CGR = 318;; +let _SYSZ_INS_CGRL = 319;; +let _SYSZ_INS_CGXBR = 320;; +let _SYSZ_INS_CH = 321;; +let _SYSZ_INS_CHF = 322;; +let _SYSZ_INS_CHHSI = 323;; +let _SYSZ_INS_CHI = 324;; +let _SYSZ_INS_CHRL = 325;; +let _SYSZ_INS_CHSI = 326;; +let _SYSZ_INS_CHY = 327;; +let _SYSZ_INS_CIH = 328;; +let _SYSZ_INS_CL = 329;; +let _SYSZ_INS_CLC = 330;; +let _SYSZ_INS_CLFDBR = 331;; +let _SYSZ_INS_CLFEBR = 332;; +let _SYSZ_INS_CLFHSI = 333;; +let _SYSZ_INS_CLFI = 334;; +let _SYSZ_INS_CLFXBR = 335;; +let _SYSZ_INS_CLG = 336;; +let _SYSZ_INS_CLGDBR = 337;; +let _SYSZ_INS_CLGEBR = 338;; +let _SYSZ_INS_CLGF = 339;; +let _SYSZ_INS_CLGFI = 340;; +let _SYSZ_INS_CLGFR = 341;; +let _SYSZ_INS_CLGFRL = 342;; +let _SYSZ_INS_CLGHRL = 343;; +let _SYSZ_INS_CLGHSI = 344;; +let _SYSZ_INS_CLGR = 345;; +let _SYSZ_INS_CLGRL = 346;; +let _SYSZ_INS_CLGXBR = 347;; +let _SYSZ_INS_CLHF = 348;; +let _SYSZ_INS_CLHHSI = 349;; +let _SYSZ_INS_CLHRL = 350;; +let _SYSZ_INS_CLI = 351;; +let _SYSZ_INS_CLIH = 352;; +let _SYSZ_INS_CLIY = 353;; +let _SYSZ_INS_CLR = 354;; +let _SYSZ_INS_CLRL = 355;; +let _SYSZ_INS_CLST = 356;; +let _SYSZ_INS_CLY = 357;; +let _SYSZ_INS_CPSDR = 358;; +let _SYSZ_INS_CR = 359;; +let _SYSZ_INS_CRL = 360;; +let _SYSZ_INS_CS = 361;; +let _SYSZ_INS_CSG = 362;; +let _SYSZ_INS_CSY = 363;; +let _SYSZ_INS_CXBR = 364;; +let _SYSZ_INS_CXFBR = 365;; +let _SYSZ_INS_CXGBR = 366;; +let _SYSZ_INS_CXLFBR = 367;; +let _SYSZ_INS_CXLGBR = 368;; +let _SYSZ_INS_CY = 369;; +let _SYSZ_INS_DDB = 370;; +let _SYSZ_INS_DDBR = 371;; +let _SYSZ_INS_DEB = 372;; +let _SYSZ_INS_DEBR = 373;; +let _SYSZ_INS_DL = 374;; +let _SYSZ_INS_DLG = 375;; +let _SYSZ_INS_DLGR = 376;; +let _SYSZ_INS_DLR = 377;; +let _SYSZ_INS_DSG = 378;; +let _SYSZ_INS_DSGF = 379;; +let _SYSZ_INS_DSGFR = 380;; +let _SYSZ_INS_DSGR = 381;; +let _SYSZ_INS_DXBR = 382;; +let _SYSZ_INS_EAR = 383;; +let _SYSZ_INS_FIDBR = 384;; +let _SYSZ_INS_FIDBRA = 385;; +let _SYSZ_INS_FIEBR = 386;; +let _SYSZ_INS_FIEBRA = 387;; +let _SYSZ_INS_FIXBR = 388;; +let _SYSZ_INS_FIXBRA = 389;; +let _SYSZ_INS_FLOGR = 390;; +let _SYSZ_INS_IC = 391;; +let _SYSZ_INS_ICY = 392;; +let _SYSZ_INS_IIHF = 393;; +let _SYSZ_INS_IIHH = 394;; +let _SYSZ_INS_IIHL = 395;; +let _SYSZ_INS_IILF = 396;; +let _SYSZ_INS_IILH = 397;; +let _SYSZ_INS_IILL = 398;; +let _SYSZ_INS_IPM = 399;; +let _SYSZ_INS_L = 400;; +let _SYSZ_INS_LA = 401;; +let _SYSZ_INS_LAA = 402;; +let _SYSZ_INS_LAAG = 403;; +let _SYSZ_INS_LAAL = 404;; +let _SYSZ_INS_LAALG = 405;; +let _SYSZ_INS_LAN = 406;; +let _SYSZ_INS_LANG = 407;; +let _SYSZ_INS_LAO = 408;; +let _SYSZ_INS_LAOG = 409;; +let _SYSZ_INS_LARL = 410;; +let _SYSZ_INS_LAX = 411;; +let _SYSZ_INS_LAXG = 412;; +let _SYSZ_INS_LAY = 413;; +let _SYSZ_INS_LB = 414;; +let _SYSZ_INS_LBH = 415;; +let _SYSZ_INS_LBR = 416;; +let _SYSZ_INS_LCDBR = 417;; +let _SYSZ_INS_LCEBR = 418;; +let _SYSZ_INS_LCGFR = 419;; +let _SYSZ_INS_LCGR = 420;; +let _SYSZ_INS_LCR = 421;; +let _SYSZ_INS_LCXBR = 422;; +let _SYSZ_INS_LD = 423;; +let _SYSZ_INS_LDEB = 424;; +let _SYSZ_INS_LDEBR = 425;; +let _SYSZ_INS_LDGR = 426;; +let _SYSZ_INS_LDR = 427;; +let _SYSZ_INS_LDXBR = 428;; +let _SYSZ_INS_LDXBRA = 429;; +let _SYSZ_INS_LDY = 430;; +let _SYSZ_INS_LE = 431;; +let _SYSZ_INS_LEDBR = 432;; +let _SYSZ_INS_LEDBRA = 433;; +let _SYSZ_INS_LER = 434;; +let _SYSZ_INS_LEXBR = 435;; +let _SYSZ_INS_LEXBRA = 436;; +let _SYSZ_INS_LEY = 437;; +let _SYSZ_INS_LFH = 438;; +let _SYSZ_INS_LG = 439;; +let _SYSZ_INS_LGB = 440;; +let _SYSZ_INS_LGBR = 441;; +let _SYSZ_INS_LGDR = 442;; +let _SYSZ_INS_LGF = 443;; +let _SYSZ_INS_LGFI = 444;; +let _SYSZ_INS_LGFR = 445;; +let _SYSZ_INS_LGFRL = 446;; +let _SYSZ_INS_LGH = 447;; +let _SYSZ_INS_LGHI = 448;; +let _SYSZ_INS_LGHR = 449;; +let _SYSZ_INS_LGHRL = 450;; +let _SYSZ_INS_LGR = 451;; +let _SYSZ_INS_LGRL = 452;; +let _SYSZ_INS_LH = 453;; +let _SYSZ_INS_LHH = 454;; +let _SYSZ_INS_LHI = 455;; +let _SYSZ_INS_LHR = 456;; +let _SYSZ_INS_LHRL = 457;; +let _SYSZ_INS_LHY = 458;; +let _SYSZ_INS_LLC = 459;; +let _SYSZ_INS_LLCH = 460;; +let _SYSZ_INS_LLCR = 461;; +let _SYSZ_INS_LLGC = 462;; +let _SYSZ_INS_LLGCR = 463;; +let _SYSZ_INS_LLGF = 464;; +let _SYSZ_INS_LLGFR = 465;; +let _SYSZ_INS_LLGFRL = 466;; +let _SYSZ_INS_LLGH = 467;; +let _SYSZ_INS_LLGHR = 468;; +let _SYSZ_INS_LLGHRL = 469;; +let _SYSZ_INS_LLH = 470;; +let _SYSZ_INS_LLHH = 471;; +let _SYSZ_INS_LLHR = 472;; +let _SYSZ_INS_LLHRL = 473;; +let _SYSZ_INS_LLIHF = 474;; +let _SYSZ_INS_LLIHH = 475;; +let _SYSZ_INS_LLIHL = 476;; +let _SYSZ_INS_LLILF = 477;; +let _SYSZ_INS_LLILH = 478;; +let _SYSZ_INS_LLILL = 479;; +let _SYSZ_INS_LMG = 480;; +let _SYSZ_INS_LNDBR = 481;; +let _SYSZ_INS_LNEBR = 482;; +let _SYSZ_INS_LNGFR = 483;; +let _SYSZ_INS_LNGR = 484;; +let _SYSZ_INS_LNR = 485;; +let _SYSZ_INS_LNXBR = 486;; +let _SYSZ_INS_LPDBR = 487;; +let _SYSZ_INS_LPEBR = 488;; +let _SYSZ_INS_LPGFR = 489;; +let _SYSZ_INS_LPGR = 490;; +let _SYSZ_INS_LPR = 491;; +let _SYSZ_INS_LPXBR = 492;; +let _SYSZ_INS_LR = 493;; +let _SYSZ_INS_LRL = 494;; +let _SYSZ_INS_LRV = 495;; +let _SYSZ_INS_LRVG = 496;; +let _SYSZ_INS_LRVGR = 497;; +let _SYSZ_INS_LRVR = 498;; +let _SYSZ_INS_LT = 499;; +let _SYSZ_INS_LTDBR = 500;; +let _SYSZ_INS_LTEBR = 501;; +let _SYSZ_INS_LTG = 502;; +let _SYSZ_INS_LTGF = 503;; +let _SYSZ_INS_LTGFR = 504;; +let _SYSZ_INS_LTGR = 505;; +let _SYSZ_INS_LTR = 506;; +let _SYSZ_INS_LTXBR = 507;; +let _SYSZ_INS_LXDB = 508;; +let _SYSZ_INS_LXDBR = 509;; +let _SYSZ_INS_LXEB = 510;; +let _SYSZ_INS_LXEBR = 511;; +let _SYSZ_INS_LXR = 512;; +let _SYSZ_INS_LY = 513;; +let _SYSZ_INS_LZDR = 514;; +let _SYSZ_INS_LZER = 515;; +let _SYSZ_INS_LZXR = 516;; +let _SYSZ_INS_MADB = 517;; +let _SYSZ_INS_MADBR = 518;; +let _SYSZ_INS_MAEB = 519;; +let _SYSZ_INS_MAEBR = 520;; +let _SYSZ_INS_MDB = 521;; +let _SYSZ_INS_MDBR = 522;; +let _SYSZ_INS_MDEB = 523;; +let _SYSZ_INS_MDEBR = 524;; +let _SYSZ_INS_MEEB = 525;; +let _SYSZ_INS_MEEBR = 526;; +let _SYSZ_INS_MGHI = 527;; +let _SYSZ_INS_MH = 528;; +let _SYSZ_INS_MHI = 529;; +let _SYSZ_INS_MHY = 530;; +let _SYSZ_INS_MLG = 531;; +let _SYSZ_INS_MLGR = 532;; +let _SYSZ_INS_MS = 533;; +let _SYSZ_INS_MSDB = 534;; +let _SYSZ_INS_MSDBR = 535;; +let _SYSZ_INS_MSEB = 536;; +let _SYSZ_INS_MSEBR = 537;; +let _SYSZ_INS_MSFI = 538;; +let _SYSZ_INS_MSG = 539;; +let _SYSZ_INS_MSGF = 540;; +let _SYSZ_INS_MSGFI = 541;; +let _SYSZ_INS_MSGFR = 542;; +let _SYSZ_INS_MSGR = 543;; +let _SYSZ_INS_MSR = 544;; +let _SYSZ_INS_MSY = 545;; +let _SYSZ_INS_MVC = 546;; +let _SYSZ_INS_MVGHI = 547;; +let _SYSZ_INS_MVHHI = 548;; +let _SYSZ_INS_MVHI = 549;; +let _SYSZ_INS_MVI = 550;; +let _SYSZ_INS_MVIY = 551;; +let _SYSZ_INS_MVST = 552;; +let _SYSZ_INS_MXBR = 553;; +let _SYSZ_INS_MXDB = 554;; +let _SYSZ_INS_MXDBR = 555;; +let _SYSZ_INS_N = 556;; +let _SYSZ_INS_NC = 557;; +let _SYSZ_INS_NG = 558;; +let _SYSZ_INS_NGR = 559;; +let _SYSZ_INS_NGRK = 560;; +let _SYSZ_INS_NI = 561;; +let _SYSZ_INS_NIHF = 562;; +let _SYSZ_INS_NIHH = 563;; +let _SYSZ_INS_NIHL = 564;; +let _SYSZ_INS_NILF = 565;; +let _SYSZ_INS_NILH = 566;; +let _SYSZ_INS_NILL = 567;; +let _SYSZ_INS_NIY = 568;; +let _SYSZ_INS_NR = 569;; +let _SYSZ_INS_NRK = 570;; +let _SYSZ_INS_NY = 571;; +let _SYSZ_INS_O = 572;; +let _SYSZ_INS_OC = 573;; +let _SYSZ_INS_OG = 574;; +let _SYSZ_INS_OGR = 575;; +let _SYSZ_INS_OGRK = 576;; +let _SYSZ_INS_OI = 577;; +let _SYSZ_INS_OIHF = 578;; +let _SYSZ_INS_OIHH = 579;; +let _SYSZ_INS_OIHL = 580;; +let _SYSZ_INS_OILF = 581;; +let _SYSZ_INS_OILH = 582;; +let _SYSZ_INS_OILL = 583;; +let _SYSZ_INS_OIY = 584;; +let _SYSZ_INS_OR = 585;; +let _SYSZ_INS_ORK = 586;; +let _SYSZ_INS_OY = 587;; +let _SYSZ_INS_PFD = 588;; +let _SYSZ_INS_PFDRL = 589;; +let _SYSZ_INS_RISBG = 590;; +let _SYSZ_INS_RISBHG = 591;; +let _SYSZ_INS_RISBLG = 592;; +let _SYSZ_INS_RLL = 593;; +let _SYSZ_INS_RLLG = 594;; +let _SYSZ_INS_RNSBG = 595;; +let _SYSZ_INS_ROSBG = 596;; +let _SYSZ_INS_RXSBG = 597;; +let _SYSZ_INS_S = 598;; +let _SYSZ_INS_SDB = 599;; +let _SYSZ_INS_SDBR = 600;; +let _SYSZ_INS_SEB = 601;; +let _SYSZ_INS_SEBR = 602;; +let _SYSZ_INS_SG = 603;; +let _SYSZ_INS_SGF = 604;; +let _SYSZ_INS_SGFR = 605;; +let _SYSZ_INS_SGR = 606;; +let _SYSZ_INS_SGRK = 607;; +let _SYSZ_INS_SH = 608;; +let _SYSZ_INS_SHY = 609;; +let _SYSZ_INS_SL = 610;; +let _SYSZ_INS_SLB = 611;; +let _SYSZ_INS_SLBG = 612;; +let _SYSZ_INS_SLBR = 613;; +let _SYSZ_INS_SLFI = 614;; +let _SYSZ_INS_SLG = 615;; +let _SYSZ_INS_SLBGR = 616;; +let _SYSZ_INS_SLGF = 617;; +let _SYSZ_INS_SLGFI = 618;; +let _SYSZ_INS_SLGFR = 619;; +let _SYSZ_INS_SLGR = 620;; +let _SYSZ_INS_SLGRK = 621;; +let _SYSZ_INS_SLL = 622;; +let _SYSZ_INS_SLLG = 623;; +let _SYSZ_INS_SLLK = 624;; +let _SYSZ_INS_SLR = 625;; +let _SYSZ_INS_SLRK = 626;; +let _SYSZ_INS_SLY = 627;; +let _SYSZ_INS_SQDB = 628;; +let _SYSZ_INS_SQDBR = 629;; +let _SYSZ_INS_SQEB = 630;; +let _SYSZ_INS_SQEBR = 631;; +let _SYSZ_INS_SQXBR = 632;; +let _SYSZ_INS_SR = 633;; +let _SYSZ_INS_SRA = 634;; +let _SYSZ_INS_SRAG = 635;; +let _SYSZ_INS_SRAK = 636;; +let _SYSZ_INS_SRK = 637;; +let _SYSZ_INS_SRL = 638;; +let _SYSZ_INS_SRLG = 639;; +let _SYSZ_INS_SRLK = 640;; +let _SYSZ_INS_SRST = 641;; +let _SYSZ_INS_ST = 642;; +let _SYSZ_INS_STC = 643;; +let _SYSZ_INS_STCH = 644;; +let _SYSZ_INS_STCY = 645;; +let _SYSZ_INS_STD = 646;; +let _SYSZ_INS_STDY = 647;; +let _SYSZ_INS_STE = 648;; +let _SYSZ_INS_STEY = 649;; +let _SYSZ_INS_STFH = 650;; +let _SYSZ_INS_STG = 651;; +let _SYSZ_INS_STGRL = 652;; +let _SYSZ_INS_STH = 653;; +let _SYSZ_INS_STHH = 654;; +let _SYSZ_INS_STHRL = 655;; +let _SYSZ_INS_STHY = 656;; +let _SYSZ_INS_STMG = 657;; +let _SYSZ_INS_STRL = 658;; +let _SYSZ_INS_STRV = 659;; +let _SYSZ_INS_STRVG = 660;; +let _SYSZ_INS_STY = 661;; +let _SYSZ_INS_SXBR = 662;; +let _SYSZ_INS_SY = 663;; +let _SYSZ_INS_TM = 664;; +let _SYSZ_INS_TMHH = 665;; +let _SYSZ_INS_TMHL = 666;; +let _SYSZ_INS_TMLH = 667;; +let _SYSZ_INS_TMLL = 668;; +let _SYSZ_INS_TMY = 669;; +let _SYSZ_INS_X = 670;; +let _SYSZ_INS_XC = 671;; +let _SYSZ_INS_XG = 672;; +let _SYSZ_INS_XGR = 673;; +let _SYSZ_INS_XGRK = 674;; +let _SYSZ_INS_XI = 675;; +let _SYSZ_INS_XIHF = 676;; +let _SYSZ_INS_XILF = 677;; +let _SYSZ_INS_XIY = 678;; +let _SYSZ_INS_XR = 679;; +let _SYSZ_INS_XRK = 680;; +let _SYSZ_INS_XY = 681;; +let _SYSZ_INS_AD = 682;; +let _SYSZ_INS_ADR = 683;; +let _SYSZ_INS_ADTR = 684;; +let _SYSZ_INS_ADTRA = 685;; +let _SYSZ_INS_AE = 686;; +let _SYSZ_INS_AER = 687;; +let _SYSZ_INS_AGH = 688;; +let _SYSZ_INS_AHHHR = 689;; +let _SYSZ_INS_AHHLR = 690;; +let _SYSZ_INS_ALGSI = 691;; +let _SYSZ_INS_ALHHHR = 692;; +let _SYSZ_INS_ALHHLR = 693;; +let _SYSZ_INS_ALSI = 694;; +let _SYSZ_INS_ALSIH = 695;; +let _SYSZ_INS_ALSIHN = 696;; +let _SYSZ_INS_AP = 697;; +let _SYSZ_INS_AU = 698;; +let _SYSZ_INS_AUR = 699;; +let _SYSZ_INS_AW = 700;; +let _SYSZ_INS_AWR = 701;; +let _SYSZ_INS_AXR = 702;; +let _SYSZ_INS_AXTR = 703;; +let _SYSZ_INS_AXTRA = 704;; +let _SYSZ_INS_B = 705;; +let _SYSZ_INS_BAKR = 706;; +let _SYSZ_INS_BAL = 707;; +let _SYSZ_INS_BALR = 708;; +let _SYSZ_INS_BAS = 709;; +let _SYSZ_INS_BASSM = 710;; +let _SYSZ_INS_BC = 711;; +let _SYSZ_INS_BCT = 712;; +let _SYSZ_INS_BCTG = 713;; +let _SYSZ_INS_BCTGR = 714;; +let _SYSZ_INS_BCTR = 715;; +let _SYSZ_INS_BE = 716;; +let _SYSZ_INS_BH = 717;; +let _SYSZ_INS_BHE = 718;; +let _SYSZ_INS_BI = 719;; +let _SYSZ_INS_BIC = 720;; +let _SYSZ_INS_BIE = 721;; +let _SYSZ_INS_BIH = 722;; +let _SYSZ_INS_BIHE = 723;; +let _SYSZ_INS_BIL = 724;; +let _SYSZ_INS_BILE = 725;; +let _SYSZ_INS_BILH = 726;; +let _SYSZ_INS_BIM = 727;; +let _SYSZ_INS_BINE = 728;; +let _SYSZ_INS_BINH = 729;; +let _SYSZ_INS_BINHE = 730;; +let _SYSZ_INS_BINL = 731;; +let _SYSZ_INS_BINLE = 732;; +let _SYSZ_INS_BINLH = 733;; +let _SYSZ_INS_BINM = 734;; +let _SYSZ_INS_BINO = 735;; +let _SYSZ_INS_BINP = 736;; +let _SYSZ_INS_BINZ = 737;; +let _SYSZ_INS_BIO = 738;; +let _SYSZ_INS_BIP = 739;; +let _SYSZ_INS_BIZ = 740;; +let _SYSZ_INS_BL = 741;; +let _SYSZ_INS_BLE = 742;; +let _SYSZ_INS_BLH = 743;; +let _SYSZ_INS_BM = 744;; +let _SYSZ_INS_BMR = 745;; +let _SYSZ_INS_BNE = 746;; +let _SYSZ_INS_BNH = 747;; +let _SYSZ_INS_BNHE = 748;; +let _SYSZ_INS_BNL = 749;; +let _SYSZ_INS_BNLE = 750;; +let _SYSZ_INS_BNLH = 751;; +let _SYSZ_INS_BNM = 752;; +let _SYSZ_INS_BNMR = 753;; +let _SYSZ_INS_BNO = 754;; +let _SYSZ_INS_BNP = 755;; +let _SYSZ_INS_BNPR = 756;; +let _SYSZ_INS_BNZ = 757;; +let _SYSZ_INS_BNZR = 758;; +let _SYSZ_INS_BO = 759;; +let _SYSZ_INS_BP = 760;; +let _SYSZ_INS_BPP = 761;; +let _SYSZ_INS_BPR = 762;; +let _SYSZ_INS_BPRP = 763;; +let _SYSZ_INS_BRCTH = 764;; +let _SYSZ_INS_BRXH = 765;; +let _SYSZ_INS_BRXHG = 766;; +let _SYSZ_INS_BRXLE = 767;; +let _SYSZ_INS_BRXLG = 768;; +let _SYSZ_INS_BSA = 769;; +let _SYSZ_INS_BSG = 770;; +let _SYSZ_INS_BSM = 771;; +let _SYSZ_INS_BXH = 772;; +let _SYSZ_INS_BXHG = 773;; +let _SYSZ_INS_BXLE = 774;; +let _SYSZ_INS_BXLEG = 775;; +let _SYSZ_INS_BZ = 776;; +let _SYSZ_INS_BZR = 777;; +let _SYSZ_INS_CD = 778;; +let _SYSZ_INS_CDFBRA = 779;; +let _SYSZ_INS_CDFR = 780;; +let _SYSZ_INS_CDFTR = 781;; +let _SYSZ_INS_CDGBRA = 782;; +let _SYSZ_INS_CDGR = 783;; +let _SYSZ_INS_CDGTR = 784;; +let _SYSZ_INS_CDGTRA = 785;; +let _SYSZ_INS_CDLFTR = 786;; +let _SYSZ_INS_CDLGTR = 787;; +let _SYSZ_INS_CDPT = 788;; +let _SYSZ_INS_CDR = 789;; +let _SYSZ_INS_CDS = 790;; +let _SYSZ_INS_CDSG = 791;; +let _SYSZ_INS_CDSTR = 792;; +let _SYSZ_INS_CDSY = 793;; +let _SYSZ_INS_CDTR = 794;; +let _SYSZ_INS_CDUTR = 795;; +let _SYSZ_INS_CDZT = 796;; +let _SYSZ_INS_CE = 797;; +let _SYSZ_INS_CEDTR = 798;; +let _SYSZ_INS_CEFBRA = 799;; +let _SYSZ_INS_CEFR = 800;; +let _SYSZ_INS_CEGBRA = 801;; +let _SYSZ_INS_CEGR = 802;; +let _SYSZ_INS_CER = 803;; +let _SYSZ_INS_CEXTR = 804;; +let _SYSZ_INS_CFC = 805;; +let _SYSZ_INS_CFDBRA = 806;; +let _SYSZ_INS_CFDR = 807;; +let _SYSZ_INS_CFDTR = 808;; +let _SYSZ_INS_CFEBRA = 809;; +let _SYSZ_INS_CFER = 810;; +let _SYSZ_INS_CFXBRA = 811;; +let _SYSZ_INS_CFXR = 812;; +let _SYSZ_INS_CFXTR = 813;; +let _SYSZ_INS_CGDBRA = 814;; +let _SYSZ_INS_CGDR = 815;; +let _SYSZ_INS_CGDTR = 816;; +let _SYSZ_INS_CGDTRA = 817;; +let _SYSZ_INS_CGEBRA = 818;; +let _SYSZ_INS_CGER = 819;; +let _SYSZ_INS_CGIB = 820;; +let _SYSZ_INS_CGIBE = 821;; +let _SYSZ_INS_CGIBH = 822;; +let _SYSZ_INS_CGIBHE = 823;; +let _SYSZ_INS_CGIBL = 824;; +let _SYSZ_INS_CGIBLE = 825;; +let _SYSZ_INS_CGIBLH = 826;; +let _SYSZ_INS_CGIBNE = 827;; +let _SYSZ_INS_CGIBNH = 828;; +let _SYSZ_INS_CGIBNHE = 829;; +let _SYSZ_INS_CGIBNL = 830;; +let _SYSZ_INS_CGIBNLE = 831;; +let _SYSZ_INS_CGIBNLH = 832;; +let _SYSZ_INS_CGIT = 833;; +let _SYSZ_INS_CGITE = 834;; +let _SYSZ_INS_CGITH = 835;; +let _SYSZ_INS_CGITHE = 836;; +let _SYSZ_INS_CGITL = 837;; +let _SYSZ_INS_CGITLE = 838;; +let _SYSZ_INS_CGITLH = 839;; +let _SYSZ_INS_CGITNE = 840;; +let _SYSZ_INS_CGITNH = 841;; +let _SYSZ_INS_CGITNHE = 842;; +let _SYSZ_INS_CGITNL = 843;; +let _SYSZ_INS_CGITNLE = 844;; +let _SYSZ_INS_CGITNLH = 845;; +let _SYSZ_INS_CGRB = 846;; +let _SYSZ_INS_CGRBE = 847;; +let _SYSZ_INS_CGRBH = 848;; +let _SYSZ_INS_CGRBHE = 849;; +let _SYSZ_INS_CGRBL = 850;; +let _SYSZ_INS_CGRBLE = 851;; +let _SYSZ_INS_CGRBLH = 852;; +let _SYSZ_INS_CGRBNE = 853;; +let _SYSZ_INS_CGRBNH = 854;; +let _SYSZ_INS_CGRBNHE = 855;; +let _SYSZ_INS_CGRBNL = 856;; +let _SYSZ_INS_CGRBNLE = 857;; +let _SYSZ_INS_CGRBNLH = 858;; +let _SYSZ_INS_CGRT = 859;; +let _SYSZ_INS_CGRTE = 860;; +let _SYSZ_INS_CGRTH = 861;; +let _SYSZ_INS_CGRTHE = 862;; +let _SYSZ_INS_CGRTL = 863;; +let _SYSZ_INS_CGRTLE = 864;; +let _SYSZ_INS_CGRTLH = 865;; +let _SYSZ_INS_CGRTNE = 866;; +let _SYSZ_INS_CGRTNH = 867;; +let _SYSZ_INS_CGRTNHE = 868;; +let _SYSZ_INS_CGRTNL = 869;; +let _SYSZ_INS_CGRTNLE = 870;; +let _SYSZ_INS_CGRTNLH = 871;; +let _SYSZ_INS_CGXBRA = 872;; +let _SYSZ_INS_CGXR = 873;; +let _SYSZ_INS_CGXTR = 874;; +let _SYSZ_INS_CGXTRA = 875;; +let _SYSZ_INS_CHHR = 876;; +let _SYSZ_INS_CHLR = 877;; +let _SYSZ_INS_CIB = 878;; +let _SYSZ_INS_CIBE = 879;; +let _SYSZ_INS_CIBH = 880;; +let _SYSZ_INS_CIBHE = 881;; +let _SYSZ_INS_CIBL = 882;; +let _SYSZ_INS_CIBLE = 883;; +let _SYSZ_INS_CIBLH = 884;; +let _SYSZ_INS_CIBNE = 885;; +let _SYSZ_INS_CIBNH = 886;; +let _SYSZ_INS_CIBNHE = 887;; +let _SYSZ_INS_CIBNL = 888;; +let _SYSZ_INS_CIBNLE = 889;; +let _SYSZ_INS_CIBNLH = 890;; +let _SYSZ_INS_CIT = 891;; +let _SYSZ_INS_CITE = 892;; +let _SYSZ_INS_CITH = 893;; +let _SYSZ_INS_CITHE = 894;; +let _SYSZ_INS_CITL = 895;; +let _SYSZ_INS_CITLE = 896;; +let _SYSZ_INS_CITLH = 897;; +let _SYSZ_INS_CITNE = 898;; +let _SYSZ_INS_CITNH = 899;; +let _SYSZ_INS_CITNHE = 900;; +let _SYSZ_INS_CITNL = 901;; +let _SYSZ_INS_CITNLE = 902;; +let _SYSZ_INS_CITNLH = 903;; +let _SYSZ_INS_CKSM = 904;; +let _SYSZ_INS_CLCL = 905;; +let _SYSZ_INS_CLCLE = 906;; +let _SYSZ_INS_CLCLU = 907;; +let _SYSZ_INS_CLFDTR = 908;; +let _SYSZ_INS_CLFIT = 909;; +let _SYSZ_INS_CLFITE = 910;; +let _SYSZ_INS_CLFITH = 911;; +let _SYSZ_INS_CLFITHE = 912;; +let _SYSZ_INS_CLFITL = 913;; +let _SYSZ_INS_CLFITLE = 914;; +let _SYSZ_INS_CLFITLH = 915;; +let _SYSZ_INS_CLFITNE = 916;; +let _SYSZ_INS_CLFITNH = 917;; +let _SYSZ_INS_CLFITNHE = 918;; +let _SYSZ_INS_CLFITNL = 919;; +let _SYSZ_INS_CLFITNLE = 920;; +let _SYSZ_INS_CLFITNLH = 921;; +let _SYSZ_INS_CLFXTR = 922;; +let _SYSZ_INS_CLGDTR = 923;; +let _SYSZ_INS_CLGIB = 924;; +let _SYSZ_INS_CLGIBE = 925;; +let _SYSZ_INS_CLGIBH = 926;; +let _SYSZ_INS_CLGIBHE = 927;; +let _SYSZ_INS_CLGIBL = 928;; +let _SYSZ_INS_CLGIBLE = 929;; +let _SYSZ_INS_CLGIBLH = 930;; +let _SYSZ_INS_CLGIBNE = 931;; +let _SYSZ_INS_CLGIBNH = 932;; +let _SYSZ_INS_CLGIBNHE = 933;; +let _SYSZ_INS_CLGIBNL = 934;; +let _SYSZ_INS_CLGIBNLE = 935;; +let _SYSZ_INS_CLGIBNLH = 936;; +let _SYSZ_INS_CLGIT = 937;; +let _SYSZ_INS_CLGITE = 938;; +let _SYSZ_INS_CLGITH = 939;; +let _SYSZ_INS_CLGITHE = 940;; +let _SYSZ_INS_CLGITL = 941;; +let _SYSZ_INS_CLGITLE = 942;; +let _SYSZ_INS_CLGITLH = 943;; +let _SYSZ_INS_CLGITNE = 944;; +let _SYSZ_INS_CLGITNH = 945;; +let _SYSZ_INS_CLGITNHE = 946;; +let _SYSZ_INS_CLGITNL = 947;; +let _SYSZ_INS_CLGITNLE = 948;; +let _SYSZ_INS_CLGITNLH = 949;; +let _SYSZ_INS_CLGRB = 950;; +let _SYSZ_INS_CLGRBE = 951;; +let _SYSZ_INS_CLGRBH = 952;; +let _SYSZ_INS_CLGRBHE = 953;; +let _SYSZ_INS_CLGRBL = 954;; +let _SYSZ_INS_CLGRBLE = 955;; +let _SYSZ_INS_CLGRBLH = 956;; +let _SYSZ_INS_CLGRBNE = 957;; +let _SYSZ_INS_CLGRBNH = 958;; +let _SYSZ_INS_CLGRBNHE = 959;; +let _SYSZ_INS_CLGRBNL = 960;; +let _SYSZ_INS_CLGRBNLE = 961;; +let _SYSZ_INS_CLGRBNLH = 962;; +let _SYSZ_INS_CLGRT = 963;; +let _SYSZ_INS_CLGRTE = 964;; +let _SYSZ_INS_CLGRTH = 965;; +let _SYSZ_INS_CLGRTHE = 966;; +let _SYSZ_INS_CLGRTL = 967;; +let _SYSZ_INS_CLGRTLE = 968;; +let _SYSZ_INS_CLGRTLH = 969;; +let _SYSZ_INS_CLGRTNE = 970;; +let _SYSZ_INS_CLGRTNH = 971;; +let _SYSZ_INS_CLGRTNHE = 972;; +let _SYSZ_INS_CLGRTNL = 973;; +let _SYSZ_INS_CLGRTNLE = 974;; +let _SYSZ_INS_CLGRTNLH = 975;; +let _SYSZ_INS_CLGT = 976;; +let _SYSZ_INS_CLGTE = 977;; +let _SYSZ_INS_CLGTH = 978;; +let _SYSZ_INS_CLGTHE = 979;; +let _SYSZ_INS_CLGTL = 980;; +let _SYSZ_INS_CLGTLE = 981;; +let _SYSZ_INS_CLGTLH = 982;; +let _SYSZ_INS_CLGTNE = 983;; +let _SYSZ_INS_CLGTNH = 984;; +let _SYSZ_INS_CLGTNHE = 985;; +let _SYSZ_INS_CLGTNL = 986;; +let _SYSZ_INS_CLGTNLE = 987;; +let _SYSZ_INS_CLGTNLH = 988;; +let _SYSZ_INS_CLGXTR = 989;; +let _SYSZ_INS_CLHHR = 990;; +let _SYSZ_INS_CLHLR = 991;; +let _SYSZ_INS_CLIB = 992;; +let _SYSZ_INS_CLIBE = 993;; +let _SYSZ_INS_CLIBH = 994;; +let _SYSZ_INS_CLIBHE = 995;; +let _SYSZ_INS_CLIBL = 996;; +let _SYSZ_INS_CLIBLE = 997;; +let _SYSZ_INS_CLIBLH = 998;; +let _SYSZ_INS_CLIBNE = 999;; +let _SYSZ_INS_CLIBNH = 1000;; +let _SYSZ_INS_CLIBNHE = 1001;; +let _SYSZ_INS_CLIBNL = 1002;; +let _SYSZ_INS_CLIBNLE = 1003;; +let _SYSZ_INS_CLIBNLH = 1004;; +let _SYSZ_INS_CLM = 1005;; +let _SYSZ_INS_CLMH = 1006;; +let _SYSZ_INS_CLMY = 1007;; +let _SYSZ_INS_CLRB = 1008;; +let _SYSZ_INS_CLRBE = 1009;; +let _SYSZ_INS_CLRBH = 1010;; +let _SYSZ_INS_CLRBHE = 1011;; +let _SYSZ_INS_CLRBL = 1012;; +let _SYSZ_INS_CLRBLE = 1013;; +let _SYSZ_INS_CLRBLH = 1014;; +let _SYSZ_INS_CLRBNE = 1015;; +let _SYSZ_INS_CLRBNH = 1016;; +let _SYSZ_INS_CLRBNHE = 1017;; +let _SYSZ_INS_CLRBNL = 1018;; +let _SYSZ_INS_CLRBNLE = 1019;; +let _SYSZ_INS_CLRBNLH = 1020;; +let _SYSZ_INS_CLRT = 1021;; +let _SYSZ_INS_CLRTE = 1022;; +let _SYSZ_INS_CLRTH = 1023;; +let _SYSZ_INS_CLRTHE = 1024;; +let _SYSZ_INS_CLRTL = 1025;; +let _SYSZ_INS_CLRTLE = 1026;; +let _SYSZ_INS_CLRTLH = 1027;; +let _SYSZ_INS_CLRTNE = 1028;; +let _SYSZ_INS_CLRTNH = 1029;; +let _SYSZ_INS_CLRTNHE = 1030;; +let _SYSZ_INS_CLRTNL = 1031;; +let _SYSZ_INS_CLRTNLE = 1032;; +let _SYSZ_INS_CLRTNLH = 1033;; +let _SYSZ_INS_CLT = 1034;; +let _SYSZ_INS_CLTE = 1035;; +let _SYSZ_INS_CLTH = 1036;; +let _SYSZ_INS_CLTHE = 1037;; +let _SYSZ_INS_CLTL = 1038;; +let _SYSZ_INS_CLTLE = 1039;; +let _SYSZ_INS_CLTLH = 1040;; +let _SYSZ_INS_CLTNE = 1041;; +let _SYSZ_INS_CLTNH = 1042;; +let _SYSZ_INS_CLTNHE = 1043;; +let _SYSZ_INS_CLTNL = 1044;; +let _SYSZ_INS_CLTNLE = 1045;; +let _SYSZ_INS_CLTNLH = 1046;; +let _SYSZ_INS_CMPSC = 1047;; +let _SYSZ_INS_CP = 1048;; +let _SYSZ_INS_CPDT = 1049;; +let _SYSZ_INS_CPXT = 1050;; +let _SYSZ_INS_CPYA = 1051;; +let _SYSZ_INS_CRB = 1052;; +let _SYSZ_INS_CRBE = 1053;; +let _SYSZ_INS_CRBH = 1054;; +let _SYSZ_INS_CRBHE = 1055;; +let _SYSZ_INS_CRBL = 1056;; +let _SYSZ_INS_CRBLE = 1057;; +let _SYSZ_INS_CRBLH = 1058;; +let _SYSZ_INS_CRBNE = 1059;; +let _SYSZ_INS_CRBNH = 1060;; +let _SYSZ_INS_CRBNHE = 1061;; +let _SYSZ_INS_CRBNL = 1062;; +let _SYSZ_INS_CRBNLE = 1063;; +let _SYSZ_INS_CRBNLH = 1064;; +let _SYSZ_INS_CRDTE = 1065;; +let _SYSZ_INS_CRT = 1066;; +let _SYSZ_INS_CRTE = 1067;; +let _SYSZ_INS_CRTH = 1068;; +let _SYSZ_INS_CRTHE = 1069;; +let _SYSZ_INS_CRTL = 1070;; +let _SYSZ_INS_CRTLE = 1071;; +let _SYSZ_INS_CRTLH = 1072;; +let _SYSZ_INS_CRTNE = 1073;; +let _SYSZ_INS_CRTNH = 1074;; +let _SYSZ_INS_CRTNHE = 1075;; +let _SYSZ_INS_CRTNL = 1076;; +let _SYSZ_INS_CRTNLE = 1077;; +let _SYSZ_INS_CRTNLH = 1078;; +let _SYSZ_INS_CSCH = 1079;; +let _SYSZ_INS_CSDTR = 1080;; +let _SYSZ_INS_CSP = 1081;; +let _SYSZ_INS_CSPG = 1082;; +let _SYSZ_INS_CSST = 1083;; +let _SYSZ_INS_CSXTR = 1084;; +let _SYSZ_INS_CU12 = 1085;; +let _SYSZ_INS_CU14 = 1086;; +let _SYSZ_INS_CU21 = 1087;; +let _SYSZ_INS_CU24 = 1088;; +let _SYSZ_INS_CU41 = 1089;; +let _SYSZ_INS_CU42 = 1090;; +let _SYSZ_INS_CUDTR = 1091;; +let _SYSZ_INS_CUSE = 1092;; +let _SYSZ_INS_CUTFU = 1093;; +let _SYSZ_INS_CUUTF = 1094;; +let _SYSZ_INS_CUXTR = 1095;; +let _SYSZ_INS_CVB = 1096;; +let _SYSZ_INS_CVBG = 1097;; +let _SYSZ_INS_CVBY = 1098;; +let _SYSZ_INS_CVD = 1099;; +let _SYSZ_INS_CVDG = 1100;; +let _SYSZ_INS_CVDY = 1101;; +let _SYSZ_INS_CXFBRA = 1102;; +let _SYSZ_INS_CXFR = 1103;; +let _SYSZ_INS_CXFTR = 1104;; +let _SYSZ_INS_CXGBRA = 1105;; +let _SYSZ_INS_CXGR = 1106;; +let _SYSZ_INS_CXGTR = 1107;; +let _SYSZ_INS_CXGTRA = 1108;; +let _SYSZ_INS_CXLFTR = 1109;; +let _SYSZ_INS_CXLGTR = 1110;; +let _SYSZ_INS_CXPT = 1111;; +let _SYSZ_INS_CXR = 1112;; +let _SYSZ_INS_CXSTR = 1113;; +let _SYSZ_INS_CXTR = 1114;; +let _SYSZ_INS_CXUTR = 1115;; +let _SYSZ_INS_CXZT = 1116;; +let _SYSZ_INS_CZDT = 1117;; +let _SYSZ_INS_CZXT = 1118;; +let _SYSZ_INS_D = 1119;; +let _SYSZ_INS_DD = 1120;; +let _SYSZ_INS_DDR = 1121;; +let _SYSZ_INS_DDTR = 1122;; +let _SYSZ_INS_DDTRA = 1123;; +let _SYSZ_INS_DE = 1124;; +let _SYSZ_INS_DER = 1125;; +let _SYSZ_INS_DIAG = 1126;; +let _SYSZ_INS_DIDBR = 1127;; +let _SYSZ_INS_DIEBR = 1128;; +let _SYSZ_INS_DP = 1129;; +let _SYSZ_INS_DR = 1130;; +let _SYSZ_INS_DXR = 1131;; +let _SYSZ_INS_DXTR = 1132;; +let _SYSZ_INS_DXTRA = 1133;; +let _SYSZ_INS_ECAG = 1134;; +let _SYSZ_INS_ECCTR = 1135;; +let _SYSZ_INS_ECPGA = 1136;; +let _SYSZ_INS_ECTG = 1137;; +let _SYSZ_INS_ED = 1138;; +let _SYSZ_INS_EDMK = 1139;; +let _SYSZ_INS_EEDTR = 1140;; +let _SYSZ_INS_EEXTR = 1141;; +let _SYSZ_INS_EFPC = 1142;; +let _SYSZ_INS_EPAIR = 1143;; +let _SYSZ_INS_EPAR = 1144;; +let _SYSZ_INS_EPCTR = 1145;; +let _SYSZ_INS_EPSW = 1146;; +let _SYSZ_INS_EREG = 1147;; +let _SYSZ_INS_EREGG = 1148;; +let _SYSZ_INS_ESAIR = 1149;; +let _SYSZ_INS_ESAR = 1150;; +let _SYSZ_INS_ESDTR = 1151;; +let _SYSZ_INS_ESEA = 1152;; +let _SYSZ_INS_ESTA = 1153;; +let _SYSZ_INS_ESXTR = 1154;; +let _SYSZ_INS_ETND = 1155;; +let _SYSZ_INS_EX = 1156;; +let _SYSZ_INS_EXRL = 1157;; +let _SYSZ_INS_FIDR = 1158;; +let _SYSZ_INS_FIDTR = 1159;; +let _SYSZ_INS_FIER = 1160;; +let _SYSZ_INS_FIXR = 1161;; +let _SYSZ_INS_FIXTR = 1162;; +let _SYSZ_INS_HDR = 1163;; +let _SYSZ_INS_HER = 1164;; +let _SYSZ_INS_HSCH = 1165;; +let _SYSZ_INS_IAC = 1166;; +let _SYSZ_INS_ICM = 1167;; +let _SYSZ_INS_ICMH = 1168;; +let _SYSZ_INS_ICMY = 1169;; +let _SYSZ_INS_IDTE = 1170;; +let _SYSZ_INS_IEDTR = 1171;; +let _SYSZ_INS_IEXTR = 1172;; +let _SYSZ_INS_IPK = 1173;; +let _SYSZ_INS_IPTE = 1174;; +let _SYSZ_INS_IRBM = 1175;; +let _SYSZ_INS_ISKE = 1176;; +let _SYSZ_INS_IVSK = 1177;; +let _SYSZ_INS_JGM = 1178;; +let _SYSZ_INS_JGNM = 1179;; +let _SYSZ_INS_JGNP = 1180;; +let _SYSZ_INS_JGNZ = 1181;; +let _SYSZ_INS_JGP = 1182;; +let _SYSZ_INS_JGZ = 1183;; +let _SYSZ_INS_JM = 1184;; +let _SYSZ_INS_JNM = 1185;; +let _SYSZ_INS_JNP = 1186;; +let _SYSZ_INS_JNZ = 1187;; +let _SYSZ_INS_JP = 1188;; +let _SYSZ_INS_JZ = 1189;; +let _SYSZ_INS_KDB = 1190;; +let _SYSZ_INS_KDBR = 1191;; +let _SYSZ_INS_KDTR = 1192;; +let _SYSZ_INS_KEB = 1193;; +let _SYSZ_INS_KEBR = 1194;; +let _SYSZ_INS_KIMD = 1195;; +let _SYSZ_INS_KLMD = 1196;; +let _SYSZ_INS_KM = 1197;; +let _SYSZ_INS_KMA = 1198;; +let _SYSZ_INS_KMAC = 1199;; +let _SYSZ_INS_KMC = 1200;; +let _SYSZ_INS_KMCTR = 1201;; +let _SYSZ_INS_KMF = 1202;; +let _SYSZ_INS_KMO = 1203;; +let _SYSZ_INS_KXBR = 1204;; +let _SYSZ_INS_KXTR = 1205;; +let _SYSZ_INS_LAE = 1206;; +let _SYSZ_INS_LAEY = 1207;; +let _SYSZ_INS_LAM = 1208;; +let _SYSZ_INS_LAMY = 1209;; +let _SYSZ_INS_LASP = 1210;; +let _SYSZ_INS_LAT = 1211;; +let _SYSZ_INS_LCBB = 1212;; +let _SYSZ_INS_LCCTL = 1213;; +let _SYSZ_INS_LCDFR = 1214;; +let _SYSZ_INS_LCDR = 1215;; +let _SYSZ_INS_LCER = 1216;; +let _SYSZ_INS_LCTL = 1217;; +let _SYSZ_INS_LCTLG = 1218;; +let _SYSZ_INS_LCXR = 1219;; +let _SYSZ_INS_LDE = 1220;; +let _SYSZ_INS_LDER = 1221;; +let _SYSZ_INS_LDETR = 1222;; +let _SYSZ_INS_LDXR = 1223;; +let _SYSZ_INS_LDXTR = 1224;; +let _SYSZ_INS_LEDR = 1225;; +let _SYSZ_INS_LEDTR = 1226;; +let _SYSZ_INS_LEXR = 1227;; +let _SYSZ_INS_LFAS = 1228;; +let _SYSZ_INS_LFHAT = 1229;; +let _SYSZ_INS_LFPC = 1230;; +let _SYSZ_INS_LGAT = 1231;; +let _SYSZ_INS_LGG = 1232;; +let _SYSZ_INS_LGSC = 1233;; +let _SYSZ_INS_LLGFAT = 1234;; +let _SYSZ_INS_LLGFSG = 1235;; +let _SYSZ_INS_LLGT = 1236;; +let _SYSZ_INS_LLGTAT = 1237;; +let _SYSZ_INS_LLGTR = 1238;; +let _SYSZ_INS_LLZRGF = 1239;; +let _SYSZ_INS_LM = 1240;; +let _SYSZ_INS_LMD = 1241;; +let _SYSZ_INS_LMH = 1242;; +let _SYSZ_INS_LMY = 1243;; +let _SYSZ_INS_LNDFR = 1244;; +let _SYSZ_INS_LNDR = 1245;; +let _SYSZ_INS_LNER = 1246;; +let _SYSZ_INS_LNXR = 1247;; +let _SYSZ_INS_LOCFH = 1248;; +let _SYSZ_INS_LOCFHE = 1249;; +let _SYSZ_INS_LOCFHH = 1250;; +let _SYSZ_INS_LOCFHHE = 1251;; +let _SYSZ_INS_LOCFHL = 1252;; +let _SYSZ_INS_LOCFHLE = 1253;; +let _SYSZ_INS_LOCFHLH = 1254;; +let _SYSZ_INS_LOCFHM = 1255;; +let _SYSZ_INS_LOCFHNE = 1256;; +let _SYSZ_INS_LOCFHNH = 1257;; +let _SYSZ_INS_LOCFHNHE = 1258;; +let _SYSZ_INS_LOCFHNL = 1259;; +let _SYSZ_INS_LOCFHNLE = 1260;; +let _SYSZ_INS_LOCFHNLH = 1261;; +let _SYSZ_INS_LOCFHNM = 1262;; +let _SYSZ_INS_LOCFHNO = 1263;; +let _SYSZ_INS_LOCFHNP = 1264;; +let _SYSZ_INS_LOCFHNZ = 1265;; +let _SYSZ_INS_LOCFHO = 1266;; +let _SYSZ_INS_LOCFHP = 1267;; +let _SYSZ_INS_LOCFHR = 1268;; +let _SYSZ_INS_LOCFHRE = 1269;; +let _SYSZ_INS_LOCFHRH = 1270;; +let _SYSZ_INS_LOCFHRHE = 1271;; +let _SYSZ_INS_LOCFHRL = 1272;; +let _SYSZ_INS_LOCFHRLE = 1273;; +let _SYSZ_INS_LOCFHRLH = 1274;; +let _SYSZ_INS_LOCFHRM = 1275;; +let _SYSZ_INS_LOCFHRNE = 1276;; +let _SYSZ_INS_LOCFHRNH = 1277;; +let _SYSZ_INS_LOCFHRNHE = 1278;; +let _SYSZ_INS_LOCFHRNL = 1279;; +let _SYSZ_INS_LOCFHRNLE = 1280;; +let _SYSZ_INS_LOCFHRNLH = 1281;; +let _SYSZ_INS_LOCFHRNM = 1282;; +let _SYSZ_INS_LOCFHRNO = 1283;; +let _SYSZ_INS_LOCFHRNP = 1284;; +let _SYSZ_INS_LOCFHRNZ = 1285;; +let _SYSZ_INS_LOCFHRO = 1286;; +let _SYSZ_INS_LOCFHRP = 1287;; +let _SYSZ_INS_LOCFHRZ = 1288;; +let _SYSZ_INS_LOCFHZ = 1289;; +let _SYSZ_INS_LOCGHI = 1290;; +let _SYSZ_INS_LOCGHIE = 1291;; +let _SYSZ_INS_LOCGHIH = 1292;; +let _SYSZ_INS_LOCGHIHE = 1293;; +let _SYSZ_INS_LOCGHIL = 1294;; +let _SYSZ_INS_LOCGHILE = 1295;; +let _SYSZ_INS_LOCGHILH = 1296;; +let _SYSZ_INS_LOCGHIM = 1297;; +let _SYSZ_INS_LOCGHINE = 1298;; +let _SYSZ_INS_LOCGHINH = 1299;; +let _SYSZ_INS_LOCGHINHE = 1300;; +let _SYSZ_INS_LOCGHINL = 1301;; +let _SYSZ_INS_LOCGHINLE = 1302;; +let _SYSZ_INS_LOCGHINLH = 1303;; +let _SYSZ_INS_LOCGHINM = 1304;; +let _SYSZ_INS_LOCGHINO = 1305;; +let _SYSZ_INS_LOCGHINP = 1306;; +let _SYSZ_INS_LOCGHINZ = 1307;; +let _SYSZ_INS_LOCGHIO = 1308;; +let _SYSZ_INS_LOCGHIP = 1309;; +let _SYSZ_INS_LOCGHIZ = 1310;; +let _SYSZ_INS_LOCGM = 1311;; +let _SYSZ_INS_LOCGNM = 1312;; +let _SYSZ_INS_LOCGNP = 1313;; +let _SYSZ_INS_LOCGNZ = 1314;; +let _SYSZ_INS_LOCGP = 1315;; +let _SYSZ_INS_LOCGRM = 1316;; +let _SYSZ_INS_LOCGRNM = 1317;; +let _SYSZ_INS_LOCGRNP = 1318;; +let _SYSZ_INS_LOCGRNZ = 1319;; +let _SYSZ_INS_LOCGRP = 1320;; +let _SYSZ_INS_LOCGRZ = 1321;; +let _SYSZ_INS_LOCGZ = 1322;; +let _SYSZ_INS_LOCHHI = 1323;; +let _SYSZ_INS_LOCHHIE = 1324;; +let _SYSZ_INS_LOCHHIH = 1325;; +let _SYSZ_INS_LOCHHIHE = 1326;; +let _SYSZ_INS_LOCHHIL = 1327;; +let _SYSZ_INS_LOCHHILE = 1328;; +let _SYSZ_INS_LOCHHILH = 1329;; +let _SYSZ_INS_LOCHHIM = 1330;; +let _SYSZ_INS_LOCHHINE = 1331;; +let _SYSZ_INS_LOCHHINH = 1332;; +let _SYSZ_INS_LOCHHINHE = 1333;; +let _SYSZ_INS_LOCHHINL = 1334;; +let _SYSZ_INS_LOCHHINLE = 1335;; +let _SYSZ_INS_LOCHHINLH = 1336;; +let _SYSZ_INS_LOCHHINM = 1337;; +let _SYSZ_INS_LOCHHINO = 1338;; +let _SYSZ_INS_LOCHHINP = 1339;; +let _SYSZ_INS_LOCHHINZ = 1340;; +let _SYSZ_INS_LOCHHIO = 1341;; +let _SYSZ_INS_LOCHHIP = 1342;; +let _SYSZ_INS_LOCHHIZ = 1343;; +let _SYSZ_INS_LOCHI = 1344;; +let _SYSZ_INS_LOCHIE = 1345;; +let _SYSZ_INS_LOCHIH = 1346;; +let _SYSZ_INS_LOCHIHE = 1347;; +let _SYSZ_INS_LOCHIL = 1348;; +let _SYSZ_INS_LOCHILE = 1349;; +let _SYSZ_INS_LOCHILH = 1350;; +let _SYSZ_INS_LOCHIM = 1351;; +let _SYSZ_INS_LOCHINE = 1352;; +let _SYSZ_INS_LOCHINH = 1353;; +let _SYSZ_INS_LOCHINHE = 1354;; +let _SYSZ_INS_LOCHINL = 1355;; +let _SYSZ_INS_LOCHINLE = 1356;; +let _SYSZ_INS_LOCHINLH = 1357;; +let _SYSZ_INS_LOCHINM = 1358;; +let _SYSZ_INS_LOCHINO = 1359;; +let _SYSZ_INS_LOCHINP = 1360;; +let _SYSZ_INS_LOCHINZ = 1361;; +let _SYSZ_INS_LOCHIO = 1362;; +let _SYSZ_INS_LOCHIP = 1363;; +let _SYSZ_INS_LOCHIZ = 1364;; +let _SYSZ_INS_LOCM = 1365;; +let _SYSZ_INS_LOCNM = 1366;; +let _SYSZ_INS_LOCNP = 1367;; +let _SYSZ_INS_LOCNZ = 1368;; +let _SYSZ_INS_LOCP = 1369;; +let _SYSZ_INS_LOCRM = 1370;; +let _SYSZ_INS_LOCRNM = 1371;; +let _SYSZ_INS_LOCRNP = 1372;; +let _SYSZ_INS_LOCRNZ = 1373;; +let _SYSZ_INS_LOCRP = 1374;; +let _SYSZ_INS_LOCRZ = 1375;; +let _SYSZ_INS_LOCZ = 1376;; +let _SYSZ_INS_LPCTL = 1377;; +let _SYSZ_INS_LPD = 1378;; +let _SYSZ_INS_LPDFR = 1379;; +let _SYSZ_INS_LPDG = 1380;; +let _SYSZ_INS_LPDR = 1381;; +let _SYSZ_INS_LPER = 1382;; +let _SYSZ_INS_LPP = 1383;; +let _SYSZ_INS_LPQ = 1384;; +let _SYSZ_INS_LPSW = 1385;; +let _SYSZ_INS_LPSWE = 1386;; +let _SYSZ_INS_LPTEA = 1387;; +let _SYSZ_INS_LPXR = 1388;; +let _SYSZ_INS_LRA = 1389;; +let _SYSZ_INS_LRAG = 1390;; +let _SYSZ_INS_LRAY = 1391;; +let _SYSZ_INS_LRDR = 1392;; +let _SYSZ_INS_LRER = 1393;; +let _SYSZ_INS_LRVH = 1394;; +let _SYSZ_INS_LSCTL = 1395;; +let _SYSZ_INS_LTDR = 1396;; +let _SYSZ_INS_LTDTR = 1397;; +let _SYSZ_INS_LTER = 1398;; +let _SYSZ_INS_LTXR = 1399;; +let _SYSZ_INS_LTXTR = 1400;; +let _SYSZ_INS_LURA = 1401;; +let _SYSZ_INS_LURAG = 1402;; +let _SYSZ_INS_LXD = 1403;; +let _SYSZ_INS_LXDR = 1404;; +let _SYSZ_INS_LXDTR = 1405;; +let _SYSZ_INS_LXE = 1406;; +let _SYSZ_INS_LXER = 1407;; +let _SYSZ_INS_LZRF = 1408;; +let _SYSZ_INS_LZRG = 1409;; +let _SYSZ_INS_M = 1410;; +let _SYSZ_INS_MAD = 1411;; +let _SYSZ_INS_MADR = 1412;; +let _SYSZ_INS_MAE = 1413;; +let _SYSZ_INS_MAER = 1414;; +let _SYSZ_INS_MAY = 1415;; +let _SYSZ_INS_MAYH = 1416;; +let _SYSZ_INS_MAYHR = 1417;; +let _SYSZ_INS_MAYL = 1418;; +let _SYSZ_INS_MAYLR = 1419;; +let _SYSZ_INS_MAYR = 1420;; +let _SYSZ_INS_MC = 1421;; +let _SYSZ_INS_MD = 1422;; +let _SYSZ_INS_MDE = 1423;; +let _SYSZ_INS_MDER = 1424;; +let _SYSZ_INS_MDR = 1425;; +let _SYSZ_INS_MDTR = 1426;; +let _SYSZ_INS_MDTRA = 1427;; +let _SYSZ_INS_ME = 1428;; +let _SYSZ_INS_MEE = 1429;; +let _SYSZ_INS_MEER = 1430;; +let _SYSZ_INS_MER = 1431;; +let _SYSZ_INS_MFY = 1432;; +let _SYSZ_INS_MG = 1433;; +let _SYSZ_INS_MGH = 1434;; +let _SYSZ_INS_MGRK = 1435;; +let _SYSZ_INS_ML = 1436;; +let _SYSZ_INS_MLR = 1437;; +let _SYSZ_INS_MP = 1438;; +let _SYSZ_INS_MR = 1439;; +let _SYSZ_INS_MSC = 1440;; +let _SYSZ_INS_MSCH = 1441;; +let _SYSZ_INS_MSD = 1442;; +let _SYSZ_INS_MSDR = 1443;; +let _SYSZ_INS_MSE = 1444;; +let _SYSZ_INS_MSER = 1445;; +let _SYSZ_INS_MSGC = 1446;; +let _SYSZ_INS_MSGRKC = 1447;; +let _SYSZ_INS_MSRKC = 1448;; +let _SYSZ_INS_MSTA = 1449;; +let _SYSZ_INS_MVCDK = 1450;; +let _SYSZ_INS_MVCIN = 1451;; +let _SYSZ_INS_MVCK = 1452;; +let _SYSZ_INS_MVCL = 1453;; +let _SYSZ_INS_MVCLE = 1454;; +let _SYSZ_INS_MVCLU = 1455;; +let _SYSZ_INS_MVCOS = 1456;; +let _SYSZ_INS_MVCP = 1457;; +let _SYSZ_INS_MVCS = 1458;; +let _SYSZ_INS_MVCSK = 1459;; +let _SYSZ_INS_MVN = 1460;; +let _SYSZ_INS_MVO = 1461;; +let _SYSZ_INS_MVPG = 1462;; +let _SYSZ_INS_MVZ = 1463;; +let _SYSZ_INS_MXD = 1464;; +let _SYSZ_INS_MXDR = 1465;; +let _SYSZ_INS_MXR = 1466;; +let _SYSZ_INS_MXTR = 1467;; +let _SYSZ_INS_MXTRA = 1468;; +let _SYSZ_INS_MY = 1469;; +let _SYSZ_INS_MYH = 1470;; +let _SYSZ_INS_MYHR = 1471;; +let _SYSZ_INS_MYL = 1472;; +let _SYSZ_INS_MYLR = 1473;; +let _SYSZ_INS_MYR = 1474;; +let _SYSZ_INS_NIAI = 1475;; +let _SYSZ_INS_NTSTG = 1476;; +let _SYSZ_INS_PACK = 1477;; +let _SYSZ_INS_PALB = 1478;; +let _SYSZ_INS_PC = 1479;; +let _SYSZ_INS_PCC = 1480;; +let _SYSZ_INS_PCKMO = 1481;; +let _SYSZ_INS_PFMF = 1482;; +let _SYSZ_INS_PFPO = 1483;; +let _SYSZ_INS_PGIN = 1484;; +let _SYSZ_INS_PGOUT = 1485;; +let _SYSZ_INS_PKA = 1486;; +let _SYSZ_INS_PKU = 1487;; +let _SYSZ_INS_PLO = 1488;; +let _SYSZ_INS_POPCNT = 1489;; +let _SYSZ_INS_PPA = 1490;; +let _SYSZ_INS_PPNO = 1491;; +let _SYSZ_INS_PR = 1492;; +let _SYSZ_INS_PRNO = 1493;; +let _SYSZ_INS_PT = 1494;; +let _SYSZ_INS_PTF = 1495;; +let _SYSZ_INS_PTFF = 1496;; +let _SYSZ_INS_PTI = 1497;; +let _SYSZ_INS_PTLB = 1498;; +let _SYSZ_INS_QADTR = 1499;; +let _SYSZ_INS_QAXTR = 1500;; +let _SYSZ_INS_QCTRI = 1501;; +let _SYSZ_INS_QSI = 1502;; +let _SYSZ_INS_RCHP = 1503;; +let _SYSZ_INS_RISBGN = 1504;; +let _SYSZ_INS_RP = 1505;; +let _SYSZ_INS_RRBE = 1506;; +let _SYSZ_INS_RRBM = 1507;; +let _SYSZ_INS_RRDTR = 1508;; +let _SYSZ_INS_RRXTR = 1509;; +let _SYSZ_INS_RSCH = 1510;; +let _SYSZ_INS_SAC = 1511;; +let _SYSZ_INS_SACF = 1512;; +let _SYSZ_INS_SAL = 1513;; +let _SYSZ_INS_SAM24 = 1514;; +let _SYSZ_INS_SAM31 = 1515;; +let _SYSZ_INS_SAM64 = 1516;; +let _SYSZ_INS_SAR = 1517;; +let _SYSZ_INS_SCCTR = 1518;; +let _SYSZ_INS_SCHM = 1519;; +let _SYSZ_INS_SCK = 1520;; +let _SYSZ_INS_SCKC = 1521;; +let _SYSZ_INS_SCKPF = 1522;; +let _SYSZ_INS_SD = 1523;; +let _SYSZ_INS_SDR = 1524;; +let _SYSZ_INS_SDTR = 1525;; +let _SYSZ_INS_SDTRA = 1526;; +let _SYSZ_INS_SE = 1527;; +let _SYSZ_INS_SER = 1528;; +let _SYSZ_INS_SFASR = 1529;; +let _SYSZ_INS_SFPC = 1530;; +let _SYSZ_INS_SGH = 1531;; +let _SYSZ_INS_SHHHR = 1532;; +let _SYSZ_INS_SHHLR = 1533;; +let _SYSZ_INS_SIE = 1534;; +let _SYSZ_INS_SIGA = 1535;; +let _SYSZ_INS_SIGP = 1536;; +let _SYSZ_INS_SLA = 1537;; +let _SYSZ_INS_SLAG = 1538;; +let _SYSZ_INS_SLAK = 1539;; +let _SYSZ_INS_SLDA = 1540;; +let _SYSZ_INS_SLDL = 1541;; +let _SYSZ_INS_SLDT = 1542;; +let _SYSZ_INS_SLHHHR = 1543;; +let _SYSZ_INS_SLHHLR = 1544;; +let _SYSZ_INS_SLXT = 1545;; +let _SYSZ_INS_SP = 1546;; +let _SYSZ_INS_SPCTR = 1547;; +let _SYSZ_INS_SPKA = 1548;; +let _SYSZ_INS_SPM = 1549;; +let _SYSZ_INS_SPT = 1550;; +let _SYSZ_INS_SPX = 1551;; +let _SYSZ_INS_SQD = 1552;; +let _SYSZ_INS_SQDR = 1553;; +let _SYSZ_INS_SQE = 1554;; +let _SYSZ_INS_SQER = 1555;; +let _SYSZ_INS_SQXR = 1556;; +let _SYSZ_INS_SRDA = 1557;; +let _SYSZ_INS_SRDL = 1558;; +let _SYSZ_INS_SRDT = 1559;; +let _SYSZ_INS_SRNM = 1560;; +let _SYSZ_INS_SRNMB = 1561;; +let _SYSZ_INS_SRNMT = 1562;; +let _SYSZ_INS_SRP = 1563;; +let _SYSZ_INS_SRSTU = 1564;; +let _SYSZ_INS_SRXT = 1565;; +let _SYSZ_INS_SSAIR = 1566;; +let _SYSZ_INS_SSAR = 1567;; +let _SYSZ_INS_SSCH = 1568;; +let _SYSZ_INS_SSKE = 1569;; +let _SYSZ_INS_SSM = 1570;; +let _SYSZ_INS_STAM = 1571;; +let _SYSZ_INS_STAMY = 1572;; +let _SYSZ_INS_STAP = 1573;; +let _SYSZ_INS_STCK = 1574;; +let _SYSZ_INS_STCKC = 1575;; +let _SYSZ_INS_STCKE = 1576;; +let _SYSZ_INS_STCKF = 1577;; +let _SYSZ_INS_STCM = 1578;; +let _SYSZ_INS_STCMH = 1579;; +let _SYSZ_INS_STCMY = 1580;; +let _SYSZ_INS_STCPS = 1581;; +let _SYSZ_INS_STCRW = 1582;; +let _SYSZ_INS_STCTG = 1583;; +let _SYSZ_INS_STCTL = 1584;; +let _SYSZ_INS_STFL = 1585;; +let _SYSZ_INS_STFLE = 1586;; +let _SYSZ_INS_STFPC = 1587;; +let _SYSZ_INS_STGSC = 1588;; +let _SYSZ_INS_STIDP = 1589;; +let _SYSZ_INS_STM = 1590;; +let _SYSZ_INS_STMH = 1591;; +let _SYSZ_INS_STMY = 1592;; +let _SYSZ_INS_STNSM = 1593;; +let _SYSZ_INS_STOCFH = 1594;; +let _SYSZ_INS_STOCFHE = 1595;; +let _SYSZ_INS_STOCFHH = 1596;; +let _SYSZ_INS_STOCFHHE = 1597;; +let _SYSZ_INS_STOCFHL = 1598;; +let _SYSZ_INS_STOCFHLE = 1599;; +let _SYSZ_INS_STOCFHLH = 1600;; +let _SYSZ_INS_STOCFHM = 1601;; +let _SYSZ_INS_STOCFHNE = 1602;; +let _SYSZ_INS_STOCFHNH = 1603;; +let _SYSZ_INS_STOCFHNHE = 1604;; +let _SYSZ_INS_STOCFHNL = 1605;; +let _SYSZ_INS_STOCFHNLE = 1606;; +let _SYSZ_INS_STOCFHNLH = 1607;; +let _SYSZ_INS_STOCFHNM = 1608;; +let _SYSZ_INS_STOCFHNO = 1609;; +let _SYSZ_INS_STOCFHNP = 1610;; +let _SYSZ_INS_STOCFHNZ = 1611;; +let _SYSZ_INS_STOCFHO = 1612;; +let _SYSZ_INS_STOCFHP = 1613;; +let _SYSZ_INS_STOCFHZ = 1614;; +let _SYSZ_INS_STOCGM = 1615;; +let _SYSZ_INS_STOCGNM = 1616;; +let _SYSZ_INS_STOCGNP = 1617;; +let _SYSZ_INS_STOCGNZ = 1618;; +let _SYSZ_INS_STOCGP = 1619;; +let _SYSZ_INS_STOCGZ = 1620;; +let _SYSZ_INS_STOCM = 1621;; +let _SYSZ_INS_STOCNM = 1622;; +let _SYSZ_INS_STOCNP = 1623;; +let _SYSZ_INS_STOCNZ = 1624;; +let _SYSZ_INS_STOCP = 1625;; +let _SYSZ_INS_STOCZ = 1626;; +let _SYSZ_INS_STOSM = 1627;; +let _SYSZ_INS_STPQ = 1628;; +let _SYSZ_INS_STPT = 1629;; +let _SYSZ_INS_STPX = 1630;; +let _SYSZ_INS_STRAG = 1631;; +let _SYSZ_INS_STRVH = 1632;; +let _SYSZ_INS_STSCH = 1633;; +let _SYSZ_INS_STSI = 1634;; +let _SYSZ_INS_STURA = 1635;; +let _SYSZ_INS_STURG = 1636;; +let _SYSZ_INS_SU = 1637;; +let _SYSZ_INS_SUR = 1638;; +let _SYSZ_INS_SVC = 1639;; +let _SYSZ_INS_SW = 1640;; +let _SYSZ_INS_SWR = 1641;; +let _SYSZ_INS_SXR = 1642;; +let _SYSZ_INS_SXTR = 1643;; +let _SYSZ_INS_SXTRA = 1644;; +let _SYSZ_INS_TABORT = 1645;; +let _SYSZ_INS_TAM = 1646;; +let _SYSZ_INS_TAR = 1647;; +let _SYSZ_INS_TB = 1648;; +let _SYSZ_INS_TBDR = 1649;; +let _SYSZ_INS_TBEDR = 1650;; +let _SYSZ_INS_TBEGIN = 1651;; +let _SYSZ_INS_TBEGINC = 1652;; +let _SYSZ_INS_TCDB = 1653;; +let _SYSZ_INS_TCEB = 1654;; +let _SYSZ_INS_TCXB = 1655;; +let _SYSZ_INS_TDCDT = 1656;; +let _SYSZ_INS_TDCET = 1657;; +let _SYSZ_INS_TDCXT = 1658;; +let _SYSZ_INS_TDGDT = 1659;; +let _SYSZ_INS_TDGET = 1660;; +let _SYSZ_INS_TDGXT = 1661;; +let _SYSZ_INS_TEND = 1662;; +let _SYSZ_INS_THDER = 1663;; +let _SYSZ_INS_THDR = 1664;; +let _SYSZ_INS_TP = 1665;; +let _SYSZ_INS_TPI = 1666;; +let _SYSZ_INS_TPROT = 1667;; +let _SYSZ_INS_TR = 1668;; +let _SYSZ_INS_TRACE = 1669;; +let _SYSZ_INS_TRACG = 1670;; +let _SYSZ_INS_TRAP2 = 1671;; +let _SYSZ_INS_TRAP4 = 1672;; +let _SYSZ_INS_TRE = 1673;; +let _SYSZ_INS_TROO = 1674;; +let _SYSZ_INS_TROT = 1675;; +let _SYSZ_INS_TRT = 1676;; +let _SYSZ_INS_TRTE = 1677;; +let _SYSZ_INS_TRTO = 1678;; +let _SYSZ_INS_TRTR = 1679;; +let _SYSZ_INS_TRTRE = 1680;; +let _SYSZ_INS_TRTT = 1681;; +let _SYSZ_INS_TS = 1682;; +let _SYSZ_INS_TSCH = 1683;; +let _SYSZ_INS_UNPK = 1684;; +let _SYSZ_INS_UNPKA = 1685;; +let _SYSZ_INS_UNPKU = 1686;; +let _SYSZ_INS_UPT = 1687;; +let _SYSZ_INS_VA = 1688;; +let _SYSZ_INS_VAB = 1689;; +let _SYSZ_INS_VAC = 1690;; +let _SYSZ_INS_VACC = 1691;; +let _SYSZ_INS_VACCB = 1692;; +let _SYSZ_INS_VACCC = 1693;; +let _SYSZ_INS_VACCCQ = 1694;; +let _SYSZ_INS_VACCF = 1695;; +let _SYSZ_INS_VACCG = 1696;; +let _SYSZ_INS_VACCH = 1697;; +let _SYSZ_INS_VACCQ = 1698;; +let _SYSZ_INS_VACQ = 1699;; +let _SYSZ_INS_VAF = 1700;; +let _SYSZ_INS_VAG = 1701;; +let _SYSZ_INS_VAH = 1702;; +let _SYSZ_INS_VAP = 1703;; +let _SYSZ_INS_VAQ = 1704;; +let _SYSZ_INS_VAVG = 1705;; +let _SYSZ_INS_VAVGB = 1706;; +let _SYSZ_INS_VAVGF = 1707;; +let _SYSZ_INS_VAVGG = 1708;; +let _SYSZ_INS_VAVGH = 1709;; +let _SYSZ_INS_VAVGL = 1710;; +let _SYSZ_INS_VAVGLB = 1711;; +let _SYSZ_INS_VAVGLF = 1712;; +let _SYSZ_INS_VAVGLG = 1713;; +let _SYSZ_INS_VAVGLH = 1714;; +let _SYSZ_INS_VBPERM = 1715;; +let _SYSZ_INS_VCDG = 1716;; +let _SYSZ_INS_VCDGB = 1717;; +let _SYSZ_INS_VCDLG = 1718;; +let _SYSZ_INS_VCDLGB = 1719;; +let _SYSZ_INS_VCEQ = 1720;; +let _SYSZ_INS_VCEQB = 1721;; +let _SYSZ_INS_VCEQBS = 1722;; +let _SYSZ_INS_VCEQF = 1723;; +let _SYSZ_INS_VCEQFS = 1724;; +let _SYSZ_INS_VCEQG = 1725;; +let _SYSZ_INS_VCEQGS = 1726;; +let _SYSZ_INS_VCEQH = 1727;; +let _SYSZ_INS_VCEQHS = 1728;; +let _SYSZ_INS_VCGD = 1729;; +let _SYSZ_INS_VCGDB = 1730;; +let _SYSZ_INS_VCH = 1731;; +let _SYSZ_INS_VCHB = 1732;; +let _SYSZ_INS_VCHBS = 1733;; +let _SYSZ_INS_VCHF = 1734;; +let _SYSZ_INS_VCHFS = 1735;; +let _SYSZ_INS_VCHG = 1736;; +let _SYSZ_INS_VCHGS = 1737;; +let _SYSZ_INS_VCHH = 1738;; +let _SYSZ_INS_VCHHS = 1739;; +let _SYSZ_INS_VCHL = 1740;; +let _SYSZ_INS_VCHLB = 1741;; +let _SYSZ_INS_VCHLBS = 1742;; +let _SYSZ_INS_VCHLF = 1743;; +let _SYSZ_INS_VCHLFS = 1744;; +let _SYSZ_INS_VCHLG = 1745;; +let _SYSZ_INS_VCHLGS = 1746;; +let _SYSZ_INS_VCHLH = 1747;; +let _SYSZ_INS_VCHLHS = 1748;; +let _SYSZ_INS_VCKSM = 1749;; +let _SYSZ_INS_VCLGD = 1750;; +let _SYSZ_INS_VCLGDB = 1751;; +let _SYSZ_INS_VCLZ = 1752;; +let _SYSZ_INS_VCLZB = 1753;; +let _SYSZ_INS_VCLZF = 1754;; +let _SYSZ_INS_VCLZG = 1755;; +let _SYSZ_INS_VCLZH = 1756;; +let _SYSZ_INS_VCP = 1757;; +let _SYSZ_INS_VCTZ = 1758;; +let _SYSZ_INS_VCTZB = 1759;; +let _SYSZ_INS_VCTZF = 1760;; +let _SYSZ_INS_VCTZG = 1761;; +let _SYSZ_INS_VCTZH = 1762;; +let _SYSZ_INS_VCVB = 1763;; +let _SYSZ_INS_VCVBG = 1764;; +let _SYSZ_INS_VCVD = 1765;; +let _SYSZ_INS_VCVDG = 1766;; +let _SYSZ_INS_VDP = 1767;; +let _SYSZ_INS_VEC = 1768;; +let _SYSZ_INS_VECB = 1769;; +let _SYSZ_INS_VECF = 1770;; +let _SYSZ_INS_VECG = 1771;; +let _SYSZ_INS_VECH = 1772;; +let _SYSZ_INS_VECL = 1773;; +let _SYSZ_INS_VECLB = 1774;; +let _SYSZ_INS_VECLF = 1775;; +let _SYSZ_INS_VECLG = 1776;; +let _SYSZ_INS_VECLH = 1777;; +let _SYSZ_INS_VERIM = 1778;; +let _SYSZ_INS_VERIMB = 1779;; +let _SYSZ_INS_VERIMF = 1780;; +let _SYSZ_INS_VERIMG = 1781;; +let _SYSZ_INS_VERIMH = 1782;; +let _SYSZ_INS_VERLL = 1783;; +let _SYSZ_INS_VERLLB = 1784;; +let _SYSZ_INS_VERLLF = 1785;; +let _SYSZ_INS_VERLLG = 1786;; +let _SYSZ_INS_VERLLH = 1787;; +let _SYSZ_INS_VERLLV = 1788;; +let _SYSZ_INS_VERLLVB = 1789;; +let _SYSZ_INS_VERLLVF = 1790;; +let _SYSZ_INS_VERLLVG = 1791;; +let _SYSZ_INS_VERLLVH = 1792;; +let _SYSZ_INS_VESL = 1793;; +let _SYSZ_INS_VESLB = 1794;; +let _SYSZ_INS_VESLF = 1795;; +let _SYSZ_INS_VESLG = 1796;; +let _SYSZ_INS_VESLH = 1797;; +let _SYSZ_INS_VESLV = 1798;; +let _SYSZ_INS_VESLVB = 1799;; +let _SYSZ_INS_VESLVF = 1800;; +let _SYSZ_INS_VESLVG = 1801;; +let _SYSZ_INS_VESLVH = 1802;; +let _SYSZ_INS_VESRA = 1803;; +let _SYSZ_INS_VESRAB = 1804;; +let _SYSZ_INS_VESRAF = 1805;; +let _SYSZ_INS_VESRAG = 1806;; +let _SYSZ_INS_VESRAH = 1807;; +let _SYSZ_INS_VESRAV = 1808;; +let _SYSZ_INS_VESRAVB = 1809;; +let _SYSZ_INS_VESRAVF = 1810;; +let _SYSZ_INS_VESRAVG = 1811;; +let _SYSZ_INS_VESRAVH = 1812;; +let _SYSZ_INS_VESRL = 1813;; +let _SYSZ_INS_VESRLB = 1814;; +let _SYSZ_INS_VESRLF = 1815;; +let _SYSZ_INS_VESRLG = 1816;; +let _SYSZ_INS_VESRLH = 1817;; +let _SYSZ_INS_VESRLV = 1818;; +let _SYSZ_INS_VESRLVB = 1819;; +let _SYSZ_INS_VESRLVF = 1820;; +let _SYSZ_INS_VESRLVG = 1821;; +let _SYSZ_INS_VESRLVH = 1822;; +let _SYSZ_INS_VFA = 1823;; +let _SYSZ_INS_VFADB = 1824;; +let _SYSZ_INS_VFAE = 1825;; +let _SYSZ_INS_VFAEB = 1826;; +let _SYSZ_INS_VFAEBS = 1827;; +let _SYSZ_INS_VFAEF = 1828;; +let _SYSZ_INS_VFAEFS = 1829;; +let _SYSZ_INS_VFAEH = 1830;; +let _SYSZ_INS_VFAEHS = 1831;; +let _SYSZ_INS_VFAEZB = 1832;; +let _SYSZ_INS_VFAEZBS = 1833;; +let _SYSZ_INS_VFAEZF = 1834;; +let _SYSZ_INS_VFAEZFS = 1835;; +let _SYSZ_INS_VFAEZH = 1836;; +let _SYSZ_INS_VFAEZHS = 1837;; +let _SYSZ_INS_VFASB = 1838;; +let _SYSZ_INS_VFCE = 1839;; +let _SYSZ_INS_VFCEDB = 1840;; +let _SYSZ_INS_VFCEDBS = 1841;; +let _SYSZ_INS_VFCESB = 1842;; +let _SYSZ_INS_VFCESBS = 1843;; +let _SYSZ_INS_VFCH = 1844;; +let _SYSZ_INS_VFCHDB = 1845;; +let _SYSZ_INS_VFCHDBS = 1846;; +let _SYSZ_INS_VFCHE = 1847;; +let _SYSZ_INS_VFCHEDB = 1848;; +let _SYSZ_INS_VFCHEDBS = 1849;; +let _SYSZ_INS_VFCHESB = 1850;; +let _SYSZ_INS_VFCHESBS = 1851;; +let _SYSZ_INS_VFCHSB = 1852;; +let _SYSZ_INS_VFCHSBS = 1853;; +let _SYSZ_INS_VFD = 1854;; +let _SYSZ_INS_VFDDB = 1855;; +let _SYSZ_INS_VFDSB = 1856;; +let _SYSZ_INS_VFEE = 1857;; +let _SYSZ_INS_VFEEB = 1858;; +let _SYSZ_INS_VFEEBS = 1859;; +let _SYSZ_INS_VFEEF = 1860;; +let _SYSZ_INS_VFEEFS = 1861;; +let _SYSZ_INS_VFEEH = 1862;; +let _SYSZ_INS_VFEEHS = 1863;; +let _SYSZ_INS_VFEEZB = 1864;; +let _SYSZ_INS_VFEEZBS = 1865;; +let _SYSZ_INS_VFEEZF = 1866;; +let _SYSZ_INS_VFEEZFS = 1867;; +let _SYSZ_INS_VFEEZH = 1868;; +let _SYSZ_INS_VFEEZHS = 1869;; +let _SYSZ_INS_VFENE = 1870;; +let _SYSZ_INS_VFENEB = 1871;; +let _SYSZ_INS_VFENEBS = 1872;; +let _SYSZ_INS_VFENEF = 1873;; +let _SYSZ_INS_VFENEFS = 1874;; +let _SYSZ_INS_VFENEH = 1875;; +let _SYSZ_INS_VFENEHS = 1876;; +let _SYSZ_INS_VFENEZB = 1877;; +let _SYSZ_INS_VFENEZBS = 1878;; +let _SYSZ_INS_VFENEZF = 1879;; +let _SYSZ_INS_VFENEZFS = 1880;; +let _SYSZ_INS_VFENEZH = 1881;; +let _SYSZ_INS_VFENEZHS = 1882;; +let _SYSZ_INS_VFI = 1883;; +let _SYSZ_INS_VFIDB = 1884;; +let _SYSZ_INS_VFISB = 1885;; +let _SYSZ_INS_VFKEDB = 1886;; +let _SYSZ_INS_VFKEDBS = 1887;; +let _SYSZ_INS_VFKESB = 1888;; +let _SYSZ_INS_VFKESBS = 1889;; +let _SYSZ_INS_VFKHDB = 1890;; +let _SYSZ_INS_VFKHDBS = 1891;; +let _SYSZ_INS_VFKHEDB = 1892;; +let _SYSZ_INS_VFKHEDBS = 1893;; +let _SYSZ_INS_VFKHESB = 1894;; +let _SYSZ_INS_VFKHESBS = 1895;; +let _SYSZ_INS_VFKHSB = 1896;; +let _SYSZ_INS_VFKHSBS = 1897;; +let _SYSZ_INS_VFLCDB = 1898;; +let _SYSZ_INS_VFLCSB = 1899;; +let _SYSZ_INS_VFLL = 1900;; +let _SYSZ_INS_VFLLS = 1901;; +let _SYSZ_INS_VFLNDB = 1902;; +let _SYSZ_INS_VFLNSB = 1903;; +let _SYSZ_INS_VFLPDB = 1904;; +let _SYSZ_INS_VFLPSB = 1905;; +let _SYSZ_INS_VFLR = 1906;; +let _SYSZ_INS_VFLRD = 1907;; +let _SYSZ_INS_VFM = 1908;; +let _SYSZ_INS_VFMA = 1909;; +let _SYSZ_INS_VFMADB = 1910;; +let _SYSZ_INS_VFMASB = 1911;; +let _SYSZ_INS_VFMAX = 1912;; +let _SYSZ_INS_VFMAXDB = 1913;; +let _SYSZ_INS_VFMAXSB = 1914;; +let _SYSZ_INS_VFMDB = 1915;; +let _SYSZ_INS_VFMIN = 1916;; +let _SYSZ_INS_VFMINDB = 1917;; +let _SYSZ_INS_VFMINSB = 1918;; +let _SYSZ_INS_VFMS = 1919;; +let _SYSZ_INS_VFMSB = 1920;; +let _SYSZ_INS_VFMSDB = 1921;; +let _SYSZ_INS_VFMSSB = 1922;; +let _SYSZ_INS_VFNMA = 1923;; +let _SYSZ_INS_VFNMADB = 1924;; +let _SYSZ_INS_VFNMASB = 1925;; +let _SYSZ_INS_VFNMS = 1926;; +let _SYSZ_INS_VFNMSDB = 1927;; +let _SYSZ_INS_VFNMSSB = 1928;; +let _SYSZ_INS_VFPSO = 1929;; +let _SYSZ_INS_VFPSODB = 1930;; +let _SYSZ_INS_VFPSOSB = 1931;; +let _SYSZ_INS_VFS = 1932;; +let _SYSZ_INS_VFSDB = 1933;; +let _SYSZ_INS_VFSQ = 1934;; +let _SYSZ_INS_VFSQDB = 1935;; +let _SYSZ_INS_VFSQSB = 1936;; +let _SYSZ_INS_VFSSB = 1937;; +let _SYSZ_INS_VFTCI = 1938;; +let _SYSZ_INS_VFTCIDB = 1939;; +let _SYSZ_INS_VFTCISB = 1940;; +let _SYSZ_INS_VGBM = 1941;; +let _SYSZ_INS_VGEF = 1942;; +let _SYSZ_INS_VGEG = 1943;; +let _SYSZ_INS_VGFM = 1944;; +let _SYSZ_INS_VGFMA = 1945;; +let _SYSZ_INS_VGFMAB = 1946;; +let _SYSZ_INS_VGFMAF = 1947;; +let _SYSZ_INS_VGFMAG = 1948;; +let _SYSZ_INS_VGFMAH = 1949;; +let _SYSZ_INS_VGFMB = 1950;; +let _SYSZ_INS_VGFMF = 1951;; +let _SYSZ_INS_VGFMG = 1952;; +let _SYSZ_INS_VGFMH = 1953;; +let _SYSZ_INS_VGM = 1954;; +let _SYSZ_INS_VGMB = 1955;; +let _SYSZ_INS_VGMF = 1956;; +let _SYSZ_INS_VGMG = 1957;; +let _SYSZ_INS_VGMH = 1958;; +let _SYSZ_INS_VISTR = 1959;; +let _SYSZ_INS_VISTRB = 1960;; +let _SYSZ_INS_VISTRBS = 1961;; +let _SYSZ_INS_VISTRF = 1962;; +let _SYSZ_INS_VISTRFS = 1963;; +let _SYSZ_INS_VISTRH = 1964;; +let _SYSZ_INS_VISTRHS = 1965;; +let _SYSZ_INS_VL = 1966;; +let _SYSZ_INS_VLBB = 1967;; +let _SYSZ_INS_VLC = 1968;; +let _SYSZ_INS_VLCB = 1969;; +let _SYSZ_INS_VLCF = 1970;; +let _SYSZ_INS_VLCG = 1971;; +let _SYSZ_INS_VLCH = 1972;; +let _SYSZ_INS_VLDE = 1973;; +let _SYSZ_INS_VLDEB = 1974;; +let _SYSZ_INS_VLEB = 1975;; +let _SYSZ_INS_VLED = 1976;; +let _SYSZ_INS_VLEDB = 1977;; +let _SYSZ_INS_VLEF = 1978;; +let _SYSZ_INS_VLEG = 1979;; +let _SYSZ_INS_VLEH = 1980;; +let _SYSZ_INS_VLEIB = 1981;; +let _SYSZ_INS_VLEIF = 1982;; +let _SYSZ_INS_VLEIG = 1983;; +let _SYSZ_INS_VLEIH = 1984;; +let _SYSZ_INS_VLGV = 1985;; +let _SYSZ_INS_VLGVB = 1986;; +let _SYSZ_INS_VLGVF = 1987;; +let _SYSZ_INS_VLGVG = 1988;; +let _SYSZ_INS_VLGVH = 1989;; +let _SYSZ_INS_VLIP = 1990;; +let _SYSZ_INS_VLL = 1991;; +let _SYSZ_INS_VLLEZ = 1992;; +let _SYSZ_INS_VLLEZB = 1993;; +let _SYSZ_INS_VLLEZF = 1994;; +let _SYSZ_INS_VLLEZG = 1995;; +let _SYSZ_INS_VLLEZH = 1996;; +let _SYSZ_INS_VLLEZLF = 1997;; +let _SYSZ_INS_VLM = 1998;; +let _SYSZ_INS_VLP = 1999;; +let _SYSZ_INS_VLPB = 2000;; +let _SYSZ_INS_VLPF = 2001;; +let _SYSZ_INS_VLPG = 2002;; +let _SYSZ_INS_VLPH = 2003;; +let _SYSZ_INS_VLR = 2004;; +let _SYSZ_INS_VLREP = 2005;; +let _SYSZ_INS_VLREPB = 2006;; +let _SYSZ_INS_VLREPF = 2007;; +let _SYSZ_INS_VLREPG = 2008;; +let _SYSZ_INS_VLREPH = 2009;; +let _SYSZ_INS_VLRL = 2010;; +let _SYSZ_INS_VLRLR = 2011;; +let _SYSZ_INS_VLVG = 2012;; +let _SYSZ_INS_VLVGB = 2013;; +let _SYSZ_INS_VLVGF = 2014;; +let _SYSZ_INS_VLVGG = 2015;; +let _SYSZ_INS_VLVGH = 2016;; +let _SYSZ_INS_VLVGP = 2017;; +let _SYSZ_INS_VMAE = 2018;; +let _SYSZ_INS_VMAEB = 2019;; +let _SYSZ_INS_VMAEF = 2020;; +let _SYSZ_INS_VMAEH = 2021;; +let _SYSZ_INS_VMAH = 2022;; +let _SYSZ_INS_VMAHB = 2023;; +let _SYSZ_INS_VMAHF = 2024;; +let _SYSZ_INS_VMAHH = 2025;; +let _SYSZ_INS_VMAL = 2026;; +let _SYSZ_INS_VMALB = 2027;; +let _SYSZ_INS_VMALE = 2028;; +let _SYSZ_INS_VMALEB = 2029;; +let _SYSZ_INS_VMALEF = 2030;; +let _SYSZ_INS_VMALEH = 2031;; +let _SYSZ_INS_VMALF = 2032;; +let _SYSZ_INS_VMALH = 2033;; +let _SYSZ_INS_VMALHB = 2034;; +let _SYSZ_INS_VMALHF = 2035;; +let _SYSZ_INS_VMALHH = 2036;; +let _SYSZ_INS_VMALHW = 2037;; +let _SYSZ_INS_VMALO = 2038;; +let _SYSZ_INS_VMALOB = 2039;; +let _SYSZ_INS_VMALOF = 2040;; +let _SYSZ_INS_VMALOH = 2041;; +let _SYSZ_INS_VMAO = 2042;; +let _SYSZ_INS_VMAOB = 2043;; +let _SYSZ_INS_VMAOF = 2044;; +let _SYSZ_INS_VMAOH = 2045;; +let _SYSZ_INS_VME = 2046;; +let _SYSZ_INS_VMEB = 2047;; +let _SYSZ_INS_VMEF = 2048;; +let _SYSZ_INS_VMEH = 2049;; +let _SYSZ_INS_VMH = 2050;; +let _SYSZ_INS_VMHB = 2051;; +let _SYSZ_INS_VMHF = 2052;; +let _SYSZ_INS_VMHH = 2053;; +let _SYSZ_INS_VML = 2054;; +let _SYSZ_INS_VMLB = 2055;; +let _SYSZ_INS_VMLE = 2056;; +let _SYSZ_INS_VMLEB = 2057;; +let _SYSZ_INS_VMLEF = 2058;; +let _SYSZ_INS_VMLEH = 2059;; +let _SYSZ_INS_VMLF = 2060;; +let _SYSZ_INS_VMLH = 2061;; +let _SYSZ_INS_VMLHB = 2062;; +let _SYSZ_INS_VMLHF = 2063;; +let _SYSZ_INS_VMLHH = 2064;; +let _SYSZ_INS_VMLHW = 2065;; +let _SYSZ_INS_VMLO = 2066;; +let _SYSZ_INS_VMLOB = 2067;; +let _SYSZ_INS_VMLOF = 2068;; +let _SYSZ_INS_VMLOH = 2069;; +let _SYSZ_INS_VMN = 2070;; +let _SYSZ_INS_VMNB = 2071;; +let _SYSZ_INS_VMNF = 2072;; +let _SYSZ_INS_VMNG = 2073;; +let _SYSZ_INS_VMNH = 2074;; +let _SYSZ_INS_VMNL = 2075;; +let _SYSZ_INS_VMNLB = 2076;; +let _SYSZ_INS_VMNLF = 2077;; +let _SYSZ_INS_VMNLG = 2078;; +let _SYSZ_INS_VMNLH = 2079;; +let _SYSZ_INS_VMO = 2080;; +let _SYSZ_INS_VMOB = 2081;; +let _SYSZ_INS_VMOF = 2082;; +let _SYSZ_INS_VMOH = 2083;; +let _SYSZ_INS_VMP = 2084;; +let _SYSZ_INS_VMRH = 2085;; +let _SYSZ_INS_VMRHB = 2086;; +let _SYSZ_INS_VMRHF = 2087;; +let _SYSZ_INS_VMRHG = 2088;; +let _SYSZ_INS_VMRHH = 2089;; +let _SYSZ_INS_VMRL = 2090;; +let _SYSZ_INS_VMRLB = 2091;; +let _SYSZ_INS_VMRLF = 2092;; +let _SYSZ_INS_VMRLG = 2093;; +let _SYSZ_INS_VMRLH = 2094;; +let _SYSZ_INS_VMSL = 2095;; +let _SYSZ_INS_VMSLG = 2096;; +let _SYSZ_INS_VMSP = 2097;; +let _SYSZ_INS_VMX = 2098;; +let _SYSZ_INS_VMXB = 2099;; +let _SYSZ_INS_VMXF = 2100;; +let _SYSZ_INS_VMXG = 2101;; +let _SYSZ_INS_VMXH = 2102;; +let _SYSZ_INS_VMXL = 2103;; +let _SYSZ_INS_VMXLB = 2104;; +let _SYSZ_INS_VMXLF = 2105;; +let _SYSZ_INS_VMXLG = 2106;; +let _SYSZ_INS_VMXLH = 2107;; +let _SYSZ_INS_VN = 2108;; +let _SYSZ_INS_VNC = 2109;; +let _SYSZ_INS_VNN = 2110;; +let _SYSZ_INS_VNO = 2111;; +let _SYSZ_INS_VNX = 2112;; +let _SYSZ_INS_VO = 2113;; +let _SYSZ_INS_VOC = 2114;; +let _SYSZ_INS_VONE = 2115;; +let _SYSZ_INS_VPDI = 2116;; +let _SYSZ_INS_VPERM = 2117;; +let _SYSZ_INS_VPK = 2118;; +let _SYSZ_INS_VPKF = 2119;; +let _SYSZ_INS_VPKG = 2120;; +let _SYSZ_INS_VPKH = 2121;; +let _SYSZ_INS_VPKLS = 2122;; +let _SYSZ_INS_VPKLSF = 2123;; +let _SYSZ_INS_VPKLSFS = 2124;; +let _SYSZ_INS_VPKLSG = 2125;; +let _SYSZ_INS_VPKLSGS = 2126;; +let _SYSZ_INS_VPKLSH = 2127;; +let _SYSZ_INS_VPKLSHS = 2128;; +let _SYSZ_INS_VPKS = 2129;; +let _SYSZ_INS_VPKSF = 2130;; +let _SYSZ_INS_VPKSFS = 2131;; +let _SYSZ_INS_VPKSG = 2132;; +let _SYSZ_INS_VPKSGS = 2133;; +let _SYSZ_INS_VPKSH = 2134;; +let _SYSZ_INS_VPKSHS = 2135;; +let _SYSZ_INS_VPKZ = 2136;; +let _SYSZ_INS_VPOPCT = 2137;; +let _SYSZ_INS_VPOPCTB = 2138;; +let _SYSZ_INS_VPOPCTF = 2139;; +let _SYSZ_INS_VPOPCTG = 2140;; +let _SYSZ_INS_VPOPCTH = 2141;; +let _SYSZ_INS_VPSOP = 2142;; +let _SYSZ_INS_VREP = 2143;; +let _SYSZ_INS_VREPB = 2144;; +let _SYSZ_INS_VREPF = 2145;; +let _SYSZ_INS_VREPG = 2146;; +let _SYSZ_INS_VREPH = 2147;; +let _SYSZ_INS_VREPI = 2148;; +let _SYSZ_INS_VREPIB = 2149;; +let _SYSZ_INS_VREPIF = 2150;; +let _SYSZ_INS_VREPIG = 2151;; +let _SYSZ_INS_VREPIH = 2152;; +let _SYSZ_INS_VRP = 2153;; +let _SYSZ_INS_VS = 2154;; +let _SYSZ_INS_VSB = 2155;; +let _SYSZ_INS_VSBCBI = 2156;; +let _SYSZ_INS_VSBCBIQ = 2157;; +let _SYSZ_INS_VSBI = 2158;; +let _SYSZ_INS_VSBIQ = 2159;; +let _SYSZ_INS_VSCBI = 2160;; +let _SYSZ_INS_VSCBIB = 2161;; +let _SYSZ_INS_VSCBIF = 2162;; +let _SYSZ_INS_VSCBIG = 2163;; +let _SYSZ_INS_VSCBIH = 2164;; +let _SYSZ_INS_VSCBIQ = 2165;; +let _SYSZ_INS_VSCEF = 2166;; +let _SYSZ_INS_VSCEG = 2167;; +let _SYSZ_INS_VSDP = 2168;; +let _SYSZ_INS_VSEG = 2169;; +let _SYSZ_INS_VSEGB = 2170;; +let _SYSZ_INS_VSEGF = 2171;; +let _SYSZ_INS_VSEGH = 2172;; +let _SYSZ_INS_VSEL = 2173;; +let _SYSZ_INS_VSF = 2174;; +let _SYSZ_INS_VSG = 2175;; +let _SYSZ_INS_VSH = 2176;; +let _SYSZ_INS_VSL = 2177;; +let _SYSZ_INS_VSLB = 2178;; +let _SYSZ_INS_VSLDB = 2179;; +let _SYSZ_INS_VSP = 2180;; +let _SYSZ_INS_VSQ = 2181;; +let _SYSZ_INS_VSRA = 2182;; +let _SYSZ_INS_VSRAB = 2183;; +let _SYSZ_INS_VSRL = 2184;; +let _SYSZ_INS_VSRLB = 2185;; +let _SYSZ_INS_VSRP = 2186;; +let _SYSZ_INS_VST = 2187;; +let _SYSZ_INS_VSTEB = 2188;; +let _SYSZ_INS_VSTEF = 2189;; +let _SYSZ_INS_VSTEG = 2190;; +let _SYSZ_INS_VSTEH = 2191;; +let _SYSZ_INS_VSTL = 2192;; +let _SYSZ_INS_VSTM = 2193;; +let _SYSZ_INS_VSTRC = 2194;; +let _SYSZ_INS_VSTRCB = 2195;; +let _SYSZ_INS_VSTRCBS = 2196;; +let _SYSZ_INS_VSTRCF = 2197;; +let _SYSZ_INS_VSTRCFS = 2198;; +let _SYSZ_INS_VSTRCH = 2199;; +let _SYSZ_INS_VSTRCHS = 2200;; +let _SYSZ_INS_VSTRCZB = 2201;; +let _SYSZ_INS_VSTRCZBS = 2202;; +let _SYSZ_INS_VSTRCZF = 2203;; +let _SYSZ_INS_VSTRCZFS = 2204;; +let _SYSZ_INS_VSTRCZH = 2205;; +let _SYSZ_INS_VSTRCZHS = 2206;; +let _SYSZ_INS_VSTRL = 2207;; +let _SYSZ_INS_VSTRLR = 2208;; +let _SYSZ_INS_VSUM = 2209;; +let _SYSZ_INS_VSUMB = 2210;; +let _SYSZ_INS_VSUMG = 2211;; +let _SYSZ_INS_VSUMGF = 2212;; +let _SYSZ_INS_VSUMGH = 2213;; +let _SYSZ_INS_VSUMH = 2214;; +let _SYSZ_INS_VSUMQ = 2215;; +let _SYSZ_INS_VSUMQF = 2216;; +let _SYSZ_INS_VSUMQG = 2217;; +let _SYSZ_INS_VTM = 2218;; +let _SYSZ_INS_VTP = 2219;; +let _SYSZ_INS_VUPH = 2220;; +let _SYSZ_INS_VUPHB = 2221;; +let _SYSZ_INS_VUPHF = 2222;; +let _SYSZ_INS_VUPHH = 2223;; +let _SYSZ_INS_VUPKZ = 2224;; +let _SYSZ_INS_VUPL = 2225;; +let _SYSZ_INS_VUPLB = 2226;; +let _SYSZ_INS_VUPLF = 2227;; +let _SYSZ_INS_VUPLH = 2228;; +let _SYSZ_INS_VUPLHB = 2229;; +let _SYSZ_INS_VUPLHF = 2230;; +let _SYSZ_INS_VUPLHH = 2231;; +let _SYSZ_INS_VUPLHW = 2232;; +let _SYSZ_INS_VUPLL = 2233;; +let _SYSZ_INS_VUPLLB = 2234;; +let _SYSZ_INS_VUPLLF = 2235;; +let _SYSZ_INS_VUPLLH = 2236;; +let _SYSZ_INS_VX = 2237;; +let _SYSZ_INS_VZERO = 2238;; +let _SYSZ_INS_WCDGB = 2239;; +let _SYSZ_INS_WCDLGB = 2240;; +let _SYSZ_INS_WCGDB = 2241;; +let _SYSZ_INS_WCLGDB = 2242;; +let _SYSZ_INS_WFADB = 2243;; +let _SYSZ_INS_WFASB = 2244;; +let _SYSZ_INS_WFAXB = 2245;; +let _SYSZ_INS_WFC = 2246;; +let _SYSZ_INS_WFCDB = 2247;; +let _SYSZ_INS_WFCEDB = 2248;; +let _SYSZ_INS_WFCEDBS = 2249;; +let _SYSZ_INS_WFCESB = 2250;; +let _SYSZ_INS_WFCESBS = 2251;; +let _SYSZ_INS_WFCEXB = 2252;; +let _SYSZ_INS_WFCEXBS = 2253;; +let _SYSZ_INS_WFCHDB = 2254;; +let _SYSZ_INS_WFCHDBS = 2255;; +let _SYSZ_INS_WFCHEDB = 2256;; +let _SYSZ_INS_WFCHEDBS = 2257;; +let _SYSZ_INS_WFCHESB = 2258;; +let _SYSZ_INS_WFCHESBS = 2259;; +let _SYSZ_INS_WFCHEXB = 2260;; +let _SYSZ_INS_WFCHEXBS = 2261;; +let _SYSZ_INS_WFCHSB = 2262;; +let _SYSZ_INS_WFCHSBS = 2263;; +let _SYSZ_INS_WFCHXB = 2264;; +let _SYSZ_INS_WFCHXBS = 2265;; +let _SYSZ_INS_WFCSB = 2266;; +let _SYSZ_INS_WFCXB = 2267;; +let _SYSZ_INS_WFDDB = 2268;; +let _SYSZ_INS_WFDSB = 2269;; +let _SYSZ_INS_WFDXB = 2270;; +let _SYSZ_INS_WFIDB = 2271;; +let _SYSZ_INS_WFISB = 2272;; +let _SYSZ_INS_WFIXB = 2273;; +let _SYSZ_INS_WFK = 2274;; +let _SYSZ_INS_WFKDB = 2275;; +let _SYSZ_INS_WFKEDB = 2276;; +let _SYSZ_INS_WFKEDBS = 2277;; +let _SYSZ_INS_WFKESB = 2278;; +let _SYSZ_INS_WFKESBS = 2279;; +let _SYSZ_INS_WFKEXB = 2280;; +let _SYSZ_INS_WFKEXBS = 2281;; +let _SYSZ_INS_WFKHDB = 2282;; +let _SYSZ_INS_WFKHDBS = 2283;; +let _SYSZ_INS_WFKHEDB = 2284;; +let _SYSZ_INS_WFKHEDBS = 2285;; +let _SYSZ_INS_WFKHESB = 2286;; +let _SYSZ_INS_WFKHESBS = 2287;; +let _SYSZ_INS_WFKHEXB = 2288;; +let _SYSZ_INS_WFKHEXBS = 2289;; +let _SYSZ_INS_WFKHSB = 2290;; +let _SYSZ_INS_WFKHSBS = 2291;; +let _SYSZ_INS_WFKHXB = 2292;; +let _SYSZ_INS_WFKHXBS = 2293;; +let _SYSZ_INS_WFKSB = 2294;; +let _SYSZ_INS_WFKXB = 2295;; +let _SYSZ_INS_WFLCDB = 2296;; +let _SYSZ_INS_WFLCSB = 2297;; +let _SYSZ_INS_WFLCXB = 2298;; +let _SYSZ_INS_WFLLD = 2299;; +let _SYSZ_INS_WFLLS = 2300;; +let _SYSZ_INS_WFLNDB = 2301;; +let _SYSZ_INS_WFLNSB = 2302;; +let _SYSZ_INS_WFLNXB = 2303;; +let _SYSZ_INS_WFLPDB = 2304;; +let _SYSZ_INS_WFLPSB = 2305;; +let _SYSZ_INS_WFLPXB = 2306;; +let _SYSZ_INS_WFLRD = 2307;; +let _SYSZ_INS_WFLRX = 2308;; +let _SYSZ_INS_WFMADB = 2309;; +let _SYSZ_INS_WFMASB = 2310;; +let _SYSZ_INS_WFMAXB = 2311;; +let _SYSZ_INS_WFMAXDB = 2312;; +let _SYSZ_INS_WFMAXSB = 2313;; +let _SYSZ_INS_WFMAXXB = 2314;; +let _SYSZ_INS_WFMDB = 2315;; +let _SYSZ_INS_WFMINDB = 2316;; +let _SYSZ_INS_WFMINSB = 2317;; +let _SYSZ_INS_WFMINXB = 2318;; +let _SYSZ_INS_WFMSB = 2319;; +let _SYSZ_INS_WFMSDB = 2320;; +let _SYSZ_INS_WFMSSB = 2321;; +let _SYSZ_INS_WFMSXB = 2322;; +let _SYSZ_INS_WFMXB = 2323;; +let _SYSZ_INS_WFNMADB = 2324;; +let _SYSZ_INS_WFNMASB = 2325;; +let _SYSZ_INS_WFNMAXB = 2326;; +let _SYSZ_INS_WFNMSDB = 2327;; +let _SYSZ_INS_WFNMSSB = 2328;; +let _SYSZ_INS_WFNMSXB = 2329;; +let _SYSZ_INS_WFPSODB = 2330;; +let _SYSZ_INS_WFPSOSB = 2331;; +let _SYSZ_INS_WFPSOXB = 2332;; +let _SYSZ_INS_WFSDB = 2333;; +let _SYSZ_INS_WFSQDB = 2334;; +let _SYSZ_INS_WFSQSB = 2335;; +let _SYSZ_INS_WFSQXB = 2336;; +let _SYSZ_INS_WFSSB = 2337;; +let _SYSZ_INS_WFSXB = 2338;; +let _SYSZ_INS_WFTCIDB = 2339;; +let _SYSZ_INS_WFTCISB = 2340;; +let _SYSZ_INS_WFTCIXB = 2341;; +let _SYSZ_INS_WLDEB = 2342;; +let _SYSZ_INS_WLEDB = 2343;; +let _SYSZ_INS_XSCH = 2344;; +let _SYSZ_INS_ZAP = 2345;; +let _SYSZ_INS_ENDING = 2346;; + +let _SYSZ_GRP_INVALID = 0;; +let _SYSZ_GRP_JUMP = 1;; +let _SYSZ_GRP_DISTINCTOPS = 128;; +let _SYSZ_GRP_FPEXTENSION = 129;; +let _SYSZ_GRP_HIGHWORD = 130;; +let _SYSZ_GRP_INTERLOCKEDACCESS1 = 131;; +let _SYSZ_GRP_LOADSTOREONCOND = 132;; +let _SYSZ_GRP_DFPPACKEDCONVERSION = 133;; +let _SYSZ_GRP_DFPZONEDCONVERSION = 134;; +let _SYSZ_GRP_ENHANCEDDAT2 = 135;; +let _SYSZ_GRP_EXECUTIONHINT = 136;; +let _SYSZ_GRP_GUARDEDSTORAGE = 137;; +let _SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138;; +let _SYSZ_GRP_LOADANDTRAP = 139;; +let _SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140;; +let _SYSZ_GRP_LOADSTOREONCOND2 = 141;; +let _SYSZ_GRP_MESSAGESECURITYASSIST3 = 142;; +let _SYSZ_GRP_MESSAGESECURITYASSIST4 = 143;; +let _SYSZ_GRP_MESSAGESECURITYASSIST5 = 144;; +let _SYSZ_GRP_MESSAGESECURITYASSIST7 = 145;; +let _SYSZ_GRP_MESSAGESECURITYASSIST8 = 146;; +let _SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147;; +let _SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148;; +let _SYSZ_GRP_NOVECTOR = 149;; +let _SYSZ_GRP_POPULATIONCOUNT = 150;; +let _SYSZ_GRP_PROCESSORASSIST = 151;; +let _SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152;; +let _SYSZ_GRP_TRANSACTIONALEXECUTION = 153;; +let _SYSZ_GRP_VECTOR = 154;; +let _SYSZ_GRP_VECTORENHANCEMENTS1 = 155;; +let _SYSZ_GRP_VECTORPACKEDDECIMAL = 156;; +let _SYSZ_GRP_ENDING = 157;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_arm.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_arm.ml new file mode 100644 index 0000000..27d95ec --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_arm.ml @@ -0,0 +1,105 @@ +(* Capstone Disassembly Engine +* By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open Capstone +open Arm +open Arm_const + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; +let _ARM_CODE2 = "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c";; +let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0";; +let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1";; + + +let all_tests = [ + (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM"); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "Thumb"); + (CS_ARCH_ARM, [CS_MODE_THUMB], _ARM_CODE2, "Thumb-mixed"); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "Thumb-2"); +];; + + +let print_op handle i op = + ( match op.value with + | ARM_OP_INVALID _ -> (); (* this would never happens *) + | ARM_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | ARM_OP_CIMM imm -> printf "\t\top[%d]: C-IMM = %u\n" i imm; + | ARM_OP_PIMM imm -> printf "\t\top[%d]: P-IMM = %u\n" i imm; + | ARM_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | ARM_OP_FP fp -> printf "\t\top[%d]: FP = %f\n" i fp; + | ARM_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); + if mem.scale != 1 then + printf "\t\t\toperands[%u].mem.scale: %d\n" i mem.scale; + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + if mem.lshift != 0 then + printf "\t\t\toperands[%u].mem.lshift: 0x%x\n" i mem.lshift; + ); + | ARM_OP_SETEND sd -> printf "\t\top[%d]: SETEND = %u\n" i sd; + ); + + if op.shift.shift_type != _ARM_SFT_INVALID && op.shift.shift_value > 0 then + printf "\t\t\tShift: type = %u, value = %u\n" + op.shift.shift_type op.shift.shift_value; + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_ARM arm -> ( + if arm.cc != _ARM_CC_AL && arm.cc != _ARM_CC_INVALID then + printf "\tCode condition: %u\n" arm.cc; + + if arm.update_flags then + printf "\tUpdate-flags: True\n"; + + if arm.writeback then + printf "\tWriteback: True\n"; + + (* print all operands info (type & value) *) + if (Array.length arm.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length arm.operands); + Array.iteri (print_op handle) arm.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_arm64.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_arm64.ml new file mode 100644 index 0000000..8ec39c6 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_arm64.ml @@ -0,0 +1,101 @@ +(* Capstone Disassembly Engine +* By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open Capstone +open Arm64 +open Arm64_const + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b";; + +let all_tests = [ + (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64"); +];; + +let print_op handle i op = + ( match op.value with + | ARM64_OP_INVALID _ -> (); (* this would never happens *) + | ARM64_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | ARM64_OP_CIMM imm -> printf "\t\top[%d]: C-IMM = %u\n" i imm; + | ARM64_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | ARM64_OP_FP fp -> printf "\t\top[%d]: FP = %f\n" i fp; + | ARM64_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + ); + | ARM64_OP_REG_MRS reg -> printf "\t\top[%d]: REG_MRS = %u\n" i reg; + | ARM64_OP_REG_MSR reg -> printf "\t\top[%d]: REG_MSR = %u\n" i reg; + | ARM64_OP_PSTATE v -> printf "\t\top[%d]: PSTATE = %u\n" i v; + | ARM64_OP_SYS v -> printf "\t\top[%d]: SYS = %u\n" i v; + | ARM64_OP_PREFETCH v -> printf "\t\top[%d]: PREFETCH = %u\n" i v; + | ARM64_OP_BARRIER v -> printf "\t\top[%d]: BARRIER = %u\n" i v; + ); + + if op.shift.shift_type != _ARM64_SFT_INVALID && op.shift.shift_value > 0 then + printf "\t\t\tShift: type = %u, value = %u\n" + op.shift.shift_type op.shift.shift_value; + if op.ext != _ARM64_EXT_INVALID then + printf "\t\t\tExt: %u\n" op.ext; + + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_ARM64 arm64 -> ( + if arm64.cc != _ARM64_CC_AL && arm64.cc != _ARM64_CC_INVALID then + printf "\tCode condition: %u\n" arm64.cc; + + if arm64.update_flags then + printf "\tUpdate-flags: True\n"; + + if arm64.writeback then + printf "\tWriteback: True\n"; + + (* print all operands info (type & value) *) + if (Array.length arm64.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length arm64.operands); + Array.iteri (print_op handle) arm64.operands; + ); + printf "\n"; + ) + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_basic.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_basic.ml new file mode 100644 index 0000000..80ad1e4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_basic.ml @@ -0,0 +1,67 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open List +open Capstone + +let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; +let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; +let _ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3";; +let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68";; +let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88";; +let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; +let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; +let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";; +let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; +let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; +let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; +let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; +let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; + +let all_tests = [ + (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0L); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", _CS_OPT_SYNTAX_ATT); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0L); + (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0L); + (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0L); + (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0L); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0L); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0L); + (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0L); + (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0L); + (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0L); + (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0L); + (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64, print register with number only", 0L); + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0L); + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0L); + (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0L); + (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0L); +];; + + +let print_insn insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;; + +let print_arch x = + let (arch, mode, code, comment, syntax) = x in + let handle = cs_open arch mode in ( + if syntax != 0L then ( + let err = cs_option handle CS_OPT_SYNTAX syntax in + match err with + | _ -> (); + ); + let insns = cs_disasm handle code 0x1000L 0L in ( + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter print_insn insns; + ); + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + );; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_detail.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_detail.ml new file mode 100644 index 0000000..3f0fea0 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_detail.ml @@ -0,0 +1,87 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open List +open Capstone + +let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; +let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; +let _ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3";; +let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68";; +let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88";; +let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; +let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; +let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";; +let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; +let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; +let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; +let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; +let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; + +let all_tests = [ + (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", 0); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0); + (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0); + (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0); + (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0); + (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0); + (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0); + (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0); + (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0); + (CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0); + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0); + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0); + (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0); + (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0); +];; + + +let print_detail handle insn = + (* print immediate operands *) + if (Array.length insn.regs_read) > 0 then begin + printf "\tImplicit registers read: "; + Array.iter (fun x -> printf "%s "(cs_reg_name handle x)) insn.regs_read; + printf "\n"; + end; + + if (Array.length insn.regs_write) > 0 then begin + printf "\tImplicit registers written: "; + Array.iter (fun x -> printf "%s "(cs_reg_name handle x)) insn.regs_write; + printf "\n"; + end; + + if (Array.length insn.groups) > 0 then begin + printf "\tThis instruction belongs to groups: "; + Array.iter (printf "%u ") insn.groups; + printf "\n"; + end; + printf "\n";; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment, syntax) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_m680x.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_m680x.ml new file mode 100644 index 0000000..8e26eeb --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_m680x.ml @@ -0,0 +1,167 @@ +(* Capstone Disassembly Engine +* M680X Backend by Wolfgang Schwotzer 2017 *) + +open Printf +open Capstone +open M680x +open M680x_const + + +let print_char_hex ch = + printf " 0x%02X" (Char.code ch) + +let print_int_hex_short value = + printf "%02X" value + +let print_string_hex comment str = + printf "%s" comment; + String.iter print_char_hex str; + printf "\n" + +let print_array_hex_short arr = + Array.iter print_int_hex_short arr + +let s_access = [ + "UNCHANGED"; "READ"; "WRITE"; "READ | WRITE" ];; + +let _M6800_CODE = "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39";; +let _M6801_CODE = "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39";; +let _M6805_CODE = "\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe";; +let _M6808_CODE = "\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f";; +let _HD6301_CODE = "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39";; +let _M6809_CODE = "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00";; +let _HD6309_CODE = "\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00";; +let _M6811_CODE = "\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f";; +let _CPU12_CODE = "\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00";; +let _HCS08_CODE = "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82";; + +let bit_set value mask = + value land mask != 0 + +let all_tests = [ + (CS_ARCH_M680X, [CS_MODE_M680X_6301], _HD6301_CODE, "M680X_HD6301"); + (CS_ARCH_M680X, [CS_MODE_M680X_6309], _HD6309_CODE, "M680X_HD6309"); + (CS_ARCH_M680X, [CS_MODE_M680X_6800], _M6800_CODE, "M680X_M6800"); + (CS_ARCH_M680X, [CS_MODE_M680X_6801], _M6801_CODE, "M680X_M6801"); + (CS_ARCH_M680X, [CS_MODE_M680X_6805], _M6805_CODE, "M680X_M68HC05"); + (CS_ARCH_M680X, [CS_MODE_M680X_6808], _M6808_CODE, "M680X_M68HC08"); + (CS_ARCH_M680X, [CS_MODE_M680X_6809], _M6809_CODE, "M680X_M6809"); + (CS_ARCH_M680X, [CS_MODE_M680X_6811], _M6811_CODE, "M680X_M68HC11"); + (CS_ARCH_M680X, [CS_MODE_M680X_CPU12], _CPU12_CODE, "M680X_CPU12"); + (CS_ARCH_M680X, [CS_MODE_M680X_HCS08], _HCS08_CODE, "M680X_HCS08"); +];; + +let print_inc_dec inc_dec is_post = ( + printf "\t\t\t"; + if is_post then printf "post" else printf "pre"; + if inc_dec > 0 then + printf " increment: %d\n" inc_dec + else + printf " decrement: %d\n" (abs inc_dec); + ); + ();; + +let print_op handle flags i op = + ( match op.value with + | M680X_OP_INVALID _ -> (); (* this would never happens *) + | M680X_OP_REGISTER reg -> ( + printf "\t\toperands[%d].type: REGISTER = %s" i (cs_reg_name handle reg); + if (((i == 0) && (bit_set flags _M680X_FIRST_OP_IN_MNEM)) || + ((i == 1) && (bit_set flags _M680X_SECOND_OP_IN_MNEM))) then + printf " (in mnemonic)"; + printf "\n"; + ); + | M680X_OP_IMMEDIATE imm -> + printf "\t\toperands[%d].type: IMMEDIATE = #%d\n" i imm; + | M680X_OP_DIRECT direct_addr -> + printf "\t\toperands[%d].type: DIRECT = 0x%02X\n" i direct_addr; + | M680X_OP_EXTENDED ext -> ( + printf "\t\toperands[%d].type: EXTENDED " i; + if ext.indirect then + printf "INDIRECT"; + printf " = 0x%04X\n" ext.addr_ext; + ); + | M680X_OP_RELATIVE rel -> + printf "\t\toperands[%d].type: RELATIVE = 0x%04X\n" i rel.addr_rel; + | M680X_OP_INDEXED idx -> ( + printf "\t\toperands[%d].type: INDEXED" i; + if (bit_set idx.flags _M680X_IDX_INDIRECT) then + printf " INDIRECT"; + printf "\n"; + if idx.base_reg != _M680X_REG_INVALID then + printf "\t\t\tbase register: %s\n" (cs_reg_name handle idx.base_reg); + if idx.offset_reg != _M680X_REG_INVALID then + printf "\t\t\toffset register: %s\n" (cs_reg_name handle idx.offset_reg); + if idx.offset_bits != 0 && idx.offset_reg == 0 && idx.inc_dec == 0 then begin + printf "\t\t\toffset: %d\n" idx.offset; + if idx.base_reg == _M680X_REG_PC then + printf "\t\t\toffset address: 0x%X\n" idx.offset_addr; + printf "\t\t\toffset bits: %u\n" idx.offset_bits; + end; + if idx.inc_dec != 0 then + print_inc_dec idx.inc_dec (bit_set idx.flags _M680X_IDX_POST_INC_DEC); + ); + | M680X_OP_CONSTANT const_val -> + printf "\t\toperands[%d].type: CONSTANT = %d\n" i const_val; + ); + + if op.size != 0 then + printf "\t\t\tsize: %d\n" op.size; + if op.access != _CS_AC_INVALID then + printf "\t\t\taccess: %s\n" (List.nth s_access op.access); + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_M680X m680x -> ( + (* print all operands info (type & value) *) + if (Array.length m680x.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length m680x.operands); + Array.iteri (print_op handle m680x.flags) m680x.operands; + ); + ); + | _ -> (); + ;; + +let print_reg handle reg = + printf " %s" (cs_reg_name handle reg) + +let print_insn handle insn = + printf "0x%04X:\t" insn.address; + print_array_hex_short insn.bytes; + printf "\t%s\t%s\n" insn.mnemonic insn.op_str; + print_detail handle insn; + if (Array.length insn.regs_read) > 0 then begin + printf "\tRegisters read:"; + Array.iter (print_reg handle) insn.regs_read; + printf "\n"; + end; + if (Array.length insn.regs_write) > 0 then begin + printf "\tRegisters modified:"; + Array.iter (print_reg handle) insn.regs_write; + printf "\n"; + end; + if (Array.length insn.groups) > 0 then + printf "\tgroups_count: %d\n" (Array.length insn.groups); + printf "\n" + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "********************\n"; + printf "Platform: %s\n" comment; + print_string_hex "Code: " code; + printf "Disasm:\n"; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + +List.iter print_arch all_tests;; + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_mips.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_mips.ml new file mode 100644 index 0000000..aef940b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_mips.ml @@ -0,0 +1,75 @@ +(* Capstone Disassembly Engine +* By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open Capstone +open Mips + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; +let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; + +let all_tests = [ + (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)"); + (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)"); +];; + +let print_op handle i op = + ( match op.value with + | MIPS_OP_INVALID _ -> (); (* this would never happens *) + | MIPS_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | MIPS_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | MIPS_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + ); + ); + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_MIPS mips -> ( + (* print all operands info (type & value) *) + if (Array.length mips.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length mips.operands); + Array.iteri (print_op handle) mips.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_ppc.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_ppc.ml new file mode 100644 index 0000000..e5e3acb --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_ppc.ml @@ -0,0 +1,81 @@ +(* Capstone Disassembly Engine +* By Guillaume Jeanne , 2014> *) + +open Printf +open Capstone +open Ppc + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; + +let all_tests = [ + (CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64"); +];; + +let print_op handle i op = + ( match op.value with + | PPC_OP_INVALID _ -> (); (* this would never happens *) + | PPC_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | PPC_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | PPC_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + ); + | PPC_OP_CRX crx -> ( printf "\t\top[%d]: CRX\n" i; + if crx.scale != 0 then + printf "\t\t\toperands[%u].crx.scale = %u\n" i crx.scale; + if crx.reg != 0 then + printf "\t\t\toperands[%u].crx.reg = %s\n" i (cs_reg_name handle crx.reg); + if crx.cond != 0 then + printf "\t\t\toperands[%u].crx.cond = 0x%x\n" i crx.cond; + ); + ); + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_PPC ppc -> ( + (* print all operands info (type & value) *) + if (Array.length ppc.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length ppc.operands); + Array.iteri (print_op handle) ppc.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_sparc.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_sparc.ml new file mode 100644 index 0000000..671f121 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_sparc.ml @@ -0,0 +1,79 @@ +(* Capstone Disassembly Engine +* By Guillaume Jeanne , 2014> *) + +open Printf +open Capstone +open Sparc + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; +let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; + + +let all_tests = [ + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc"); + (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9"); +];; + +let print_op handle i op = + ( match op.value with + | SPARC_OP_INVALID _ -> (); (* this would never happens *) + | SPARC_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | SPARC_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | SPARC_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + ); + ); + + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_SPARC sparc -> ( + (* print all operands info (type & value) *) + if (Array.length sparc.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length sparc.operands); + Array.iteri (print_op handle) sparc.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_systemz.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_systemz.ml new file mode 100644 index 0000000..8f5dbe5 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_systemz.ml @@ -0,0 +1,80 @@ +(* Capstone Disassembly Engine +* By Guillaume Jeanne , 2014> *) + +open Printf +open Capstone +open Systemz + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; + + + +let all_tests = [ + (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ"); +];; + +let print_op handle i op = + ( match op.value with + | SYSZ_OP_INVALID _ -> (); (* this would never happens *) + | SYSZ_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | SYSZ_OP_ACREG reg -> printf "\t\top[%d]: ACREG = %u\n" i reg; + | SYSZ_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | SYSZ_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; + if mem.length != 0L then + printf "\t\t\toperands[%u].mem.length: 0x%Lx\n" i mem.length; + if mem.disp != 0L then + printf "\t\t\toperands[%u].mem.disp: 0x%Lx\n" i mem.disp; + ); + ); + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_SYSZ sysz -> ( + (* print all operands info (type & value) *) + if (Array.length sysz.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length sysz.operands); + Array.iteri (print_op handle) sysz.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_x86.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_x86.ml new file mode 100644 index 0000000..d35bf0f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_x86.ml @@ -0,0 +1,117 @@ +(* Capstone Disassembly Engine +* By Nguyen Anh Quynh , 2013-2014 *) + +open Printf +open Capstone +open X86 +open X86_const + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; +let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; + + +let all_tests = [ + (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0L); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", _CS_OPT_SYNTAX_ATT); + (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0L); + (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0L); +];; + +let print_op handle i op = + ( match op.value with + | X86_OP_INVALID _ -> (); (* this would never happens *) + | X86_OP_REG reg -> printf "\t\top[%d]: REG = %s [sz=%d]\n" i (cs_reg_name handle reg) op.size; + | X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x [sz=%d]\n" i imm op.size; + | X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM [sz=%d]\n" i op.size; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); + if mem.scale != 1 then + printf "\t\t\toperands[%u].mem.scale: %d\n" i mem.scale; + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + ); + ); + ();; + + +let print_detail handle mode insn = + match insn.arch with + | CS_INFO_X86 x86 -> ( + print_string_hex "\tPrefix: " x86.prefix; + + (* print instruction's opcode *) + print_string_hex "\tOpcode: " x86.opcode; + + (* print operand's size, address size, displacement size & immediate size *) + printf "\taddr_size: %u\n" x86.addr_size; + + (* print modRM byte *) + printf "\tmodrm: 0x%x\n" x86.modrm; + + (* print displacement value *) + if x86.disp != 0 then + printf "\tdisp: 0x%x\n" x86.disp; + + (* SIB is invalid in 16-bit mode *) + if not (List.mem CS_MODE_16 mode) then ( + (* print SIB byte *) + printf "\tsib: 0x%x\n" x86.sib; + + (* print sib index/scale/base (if applicable) *) + if x86.sib_index != _X86_REG_INVALID then + printf "\tsib_index: %s, sib_scale: %u, sib_base: %s\n" + (cs_reg_name handle x86.sib_index) + x86.sib_scale + (cs_reg_name handle x86.sib_base); + ); + + (* print all operands info (type & value) *) + if (Array.length x86.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length x86.operands); + Array.iteri (print_op handle) x86.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle mode insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle mode insn + + +let print_arch x = + let (arch, mode, code, comment, syntax) = x in + let handle = cs_open arch mode in ( + if syntax != 0L then ( + let err = cs_option handle CS_OPT_SYNTAX syntax in + match err with + | _ -> (); + ); + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in ( + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle mode) insns; + ); + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + );; + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/test_xcore.ml b/white_patch_detect/capstone-master/bindings/ocaml/test_xcore.ml new file mode 100644 index 0000000..984ebb6 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/test_xcore.ml @@ -0,0 +1,78 @@ +(* Capstone Disassembly Engine +* By Guillaume Jeanne , 2014> *) + +open Printf +open Capstone +open Xcore + + +let print_string_hex comment str = + printf "%s" comment; + for i = 0 to (Array.length str - 1) do + printf "0x%02x " str.(i) + done; + printf "\n" + + +let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; + +let all_tests = [ + (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore"); +];; + +let print_op handle i op = + ( match op.value with + | XCORE_OP_INVALID _ -> (); (* this would never happens *) + | XCORE_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); + | XCORE_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; + | XCORE_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; + if mem.base != 0 then + printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); + if mem.index != 0 then + printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; + if mem.disp != 0 then + printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; + if mem.direct != 0 then + printf "\t\t\toperands[%u].mem.direct: 0x%x\n" i mem.direct; + ); + ); + + ();; + + +let print_detail handle insn = + match insn.arch with + | CS_INFO_XCORE xcore -> ( + (* print all operands info (type & value) *) + if (Array.length xcore.operands) > 0 then ( + printf "\top_count: %d\n" (Array.length xcore.operands); + Array.iteri (print_op handle) xcore.operands; + ); + printf "\n"; + ); + | _ -> (); + ;; + + +let print_insn handle insn = + printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; + print_detail handle insn + + +let print_arch x = + let (arch, mode, code, comment) = x in + let handle = cs_open arch mode in + let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in + match err with + | _ -> (); + let insns = cs_disasm handle code 0x1000L 0L in + printf "*************\n"; + printf "Platform: %s\n" comment; + List.iter (print_insn handle) insns; + match cs_close handle with + | 0 -> (); + | _ -> printf "Failed to close handle"; + ;; + + +List.iter print_arch all_tests;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/tms320c64x_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/tms320c64x_const.ml new file mode 100644 index 0000000..53a4440 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/tms320c64x_const.ml @@ -0,0 +1,277 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.ml] *) + +let _TMS320C64X_OP_INVALID = 0;; +let _TMS320C64X_OP_REG = 1;; +let _TMS320C64X_OP_IMM = 2;; +let _TMS320C64X_OP_MEM = 3;; +let _TMS320C64X_OP_REGPAIR = 64;; + +let _TMS320C64X_MEM_DISP_INVALID = 0;; +let _TMS320C64X_MEM_DISP_CONSTANT = 1;; +let _TMS320C64X_MEM_DISP_REGISTER = 2;; + +let _TMS320C64X_MEM_DIR_INVALID = 0;; +let _TMS320C64X_MEM_DIR_FW = 1;; +let _TMS320C64X_MEM_DIR_BW = 2;; + +let _TMS320C64X_MEM_MOD_INVALID = 0;; +let _TMS320C64X_MEM_MOD_NO = 1;; +let _TMS320C64X_MEM_MOD_PRE = 2;; +let _TMS320C64X_MEM_MOD_POST = 3;; + +let _TMS320C64X_REG_INVALID = 0;; +let _TMS320C64X_REG_AMR = 1;; +let _TMS320C64X_REG_CSR = 2;; +let _TMS320C64X_REG_DIER = 3;; +let _TMS320C64X_REG_DNUM = 4;; +let _TMS320C64X_REG_ECR = 5;; +let _TMS320C64X_REG_GFPGFR = 6;; +let _TMS320C64X_REG_GPLYA = 7;; +let _TMS320C64X_REG_GPLYB = 8;; +let _TMS320C64X_REG_ICR = 9;; +let _TMS320C64X_REG_IER = 10;; +let _TMS320C64X_REG_IERR = 11;; +let _TMS320C64X_REG_ILC = 12;; +let _TMS320C64X_REG_IRP = 13;; +let _TMS320C64X_REG_ISR = 14;; +let _TMS320C64X_REG_ISTP = 15;; +let _TMS320C64X_REG_ITSR = 16;; +let _TMS320C64X_REG_NRP = 17;; +let _TMS320C64X_REG_NTSR = 18;; +let _TMS320C64X_REG_REP = 19;; +let _TMS320C64X_REG_RILC = 20;; +let _TMS320C64X_REG_SSR = 21;; +let _TMS320C64X_REG_TSCH = 22;; +let _TMS320C64X_REG_TSCL = 23;; +let _TMS320C64X_REG_TSR = 24;; +let _TMS320C64X_REG_A0 = 25;; +let _TMS320C64X_REG_A1 = 26;; +let _TMS320C64X_REG_A2 = 27;; +let _TMS320C64X_REG_A3 = 28;; +let _TMS320C64X_REG_A4 = 29;; +let _TMS320C64X_REG_A5 = 30;; +let _TMS320C64X_REG_A6 = 31;; +let _TMS320C64X_REG_A7 = 32;; +let _TMS320C64X_REG_A8 = 33;; +let _TMS320C64X_REG_A9 = 34;; +let _TMS320C64X_REG_A10 = 35;; +let _TMS320C64X_REG_A11 = 36;; +let _TMS320C64X_REG_A12 = 37;; +let _TMS320C64X_REG_A13 = 38;; +let _TMS320C64X_REG_A14 = 39;; +let _TMS320C64X_REG_A15 = 40;; +let _TMS320C64X_REG_A16 = 41;; +let _TMS320C64X_REG_A17 = 42;; +let _TMS320C64X_REG_A18 = 43;; +let _TMS320C64X_REG_A19 = 44;; +let _TMS320C64X_REG_A20 = 45;; +let _TMS320C64X_REG_A21 = 46;; +let _TMS320C64X_REG_A22 = 47;; +let _TMS320C64X_REG_A23 = 48;; +let _TMS320C64X_REG_A24 = 49;; +let _TMS320C64X_REG_A25 = 50;; +let _TMS320C64X_REG_A26 = 51;; +let _TMS320C64X_REG_A27 = 52;; +let _TMS320C64X_REG_A28 = 53;; +let _TMS320C64X_REG_A29 = 54;; +let _TMS320C64X_REG_A30 = 55;; +let _TMS320C64X_REG_A31 = 56;; +let _TMS320C64X_REG_B0 = 57;; +let _TMS320C64X_REG_B1 = 58;; +let _TMS320C64X_REG_B2 = 59;; +let _TMS320C64X_REG_B3 = 60;; +let _TMS320C64X_REG_B4 = 61;; +let _TMS320C64X_REG_B5 = 62;; +let _TMS320C64X_REG_B6 = 63;; +let _TMS320C64X_REG_B7 = 64;; +let _TMS320C64X_REG_B8 = 65;; +let _TMS320C64X_REG_B9 = 66;; +let _TMS320C64X_REG_B10 = 67;; +let _TMS320C64X_REG_B11 = 68;; +let _TMS320C64X_REG_B12 = 69;; +let _TMS320C64X_REG_B13 = 70;; +let _TMS320C64X_REG_B14 = 71;; +let _TMS320C64X_REG_B15 = 72;; +let _TMS320C64X_REG_B16 = 73;; +let _TMS320C64X_REG_B17 = 74;; +let _TMS320C64X_REG_B18 = 75;; +let _TMS320C64X_REG_B19 = 76;; +let _TMS320C64X_REG_B20 = 77;; +let _TMS320C64X_REG_B21 = 78;; +let _TMS320C64X_REG_B22 = 79;; +let _TMS320C64X_REG_B23 = 80;; +let _TMS320C64X_REG_B24 = 81;; +let _TMS320C64X_REG_B25 = 82;; +let _TMS320C64X_REG_B26 = 83;; +let _TMS320C64X_REG_B27 = 84;; +let _TMS320C64X_REG_B28 = 85;; +let _TMS320C64X_REG_B29 = 86;; +let _TMS320C64X_REG_B30 = 87;; +let _TMS320C64X_REG_B31 = 88;; +let _TMS320C64X_REG_PCE1 = 89;; +let _TMS320C64X_REG_ENDING = 90;; +let _TMS320C64X_REG_EFR = _TMS320C64X_REG_ECR;; +let _TMS320C64X_REG_IFR = _TMS320C64X_REG_ISR;; + +let _TMS320C64X_INS_INVALID = 0;; +let _TMS320C64X_INS_ABS = 1;; +let _TMS320C64X_INS_ABS2 = 2;; +let _TMS320C64X_INS_ADD = 3;; +let _TMS320C64X_INS_ADD2 = 4;; +let _TMS320C64X_INS_ADD4 = 5;; +let _TMS320C64X_INS_ADDAB = 6;; +let _TMS320C64X_INS_ADDAD = 7;; +let _TMS320C64X_INS_ADDAH = 8;; +let _TMS320C64X_INS_ADDAW = 9;; +let _TMS320C64X_INS_ADDK = 10;; +let _TMS320C64X_INS_ADDKPC = 11;; +let _TMS320C64X_INS_ADDU = 12;; +let _TMS320C64X_INS_AND = 13;; +let _TMS320C64X_INS_ANDN = 14;; +let _TMS320C64X_INS_AVG2 = 15;; +let _TMS320C64X_INS_AVGU4 = 16;; +let _TMS320C64X_INS_B = 17;; +let _TMS320C64X_INS_BDEC = 18;; +let _TMS320C64X_INS_BITC4 = 19;; +let _TMS320C64X_INS_BNOP = 20;; +let _TMS320C64X_INS_BPOS = 21;; +let _TMS320C64X_INS_CLR = 22;; +let _TMS320C64X_INS_CMPEQ = 23;; +let _TMS320C64X_INS_CMPEQ2 = 24;; +let _TMS320C64X_INS_CMPEQ4 = 25;; +let _TMS320C64X_INS_CMPGT = 26;; +let _TMS320C64X_INS_CMPGT2 = 27;; +let _TMS320C64X_INS_CMPGTU4 = 28;; +let _TMS320C64X_INS_CMPLT = 29;; +let _TMS320C64X_INS_CMPLTU = 30;; +let _TMS320C64X_INS_DEAL = 31;; +let _TMS320C64X_INS_DOTP2 = 32;; +let _TMS320C64X_INS_DOTPN2 = 33;; +let _TMS320C64X_INS_DOTPNRSU2 = 34;; +let _TMS320C64X_INS_DOTPRSU2 = 35;; +let _TMS320C64X_INS_DOTPSU4 = 36;; +let _TMS320C64X_INS_DOTPU4 = 37;; +let _TMS320C64X_INS_EXT = 38;; +let _TMS320C64X_INS_EXTU = 39;; +let _TMS320C64X_INS_GMPGTU = 40;; +let _TMS320C64X_INS_GMPY4 = 41;; +let _TMS320C64X_INS_LDB = 42;; +let _TMS320C64X_INS_LDBU = 43;; +let _TMS320C64X_INS_LDDW = 44;; +let _TMS320C64X_INS_LDH = 45;; +let _TMS320C64X_INS_LDHU = 46;; +let _TMS320C64X_INS_LDNDW = 47;; +let _TMS320C64X_INS_LDNW = 48;; +let _TMS320C64X_INS_LDW = 49;; +let _TMS320C64X_INS_LMBD = 50;; +let _TMS320C64X_INS_MAX2 = 51;; +let _TMS320C64X_INS_MAXU4 = 52;; +let _TMS320C64X_INS_MIN2 = 53;; +let _TMS320C64X_INS_MINU4 = 54;; +let _TMS320C64X_INS_MPY = 55;; +let _TMS320C64X_INS_MPY2 = 56;; +let _TMS320C64X_INS_MPYH = 57;; +let _TMS320C64X_INS_MPYHI = 58;; +let _TMS320C64X_INS_MPYHIR = 59;; +let _TMS320C64X_INS_MPYHL = 60;; +let _TMS320C64X_INS_MPYHLU = 61;; +let _TMS320C64X_INS_MPYHSLU = 62;; +let _TMS320C64X_INS_MPYHSU = 63;; +let _TMS320C64X_INS_MPYHU = 64;; +let _TMS320C64X_INS_MPYHULS = 65;; +let _TMS320C64X_INS_MPYHUS = 66;; +let _TMS320C64X_INS_MPYLH = 67;; +let _TMS320C64X_INS_MPYLHU = 68;; +let _TMS320C64X_INS_MPYLI = 69;; +let _TMS320C64X_INS_MPYLIR = 70;; +let _TMS320C64X_INS_MPYLSHU = 71;; +let _TMS320C64X_INS_MPYLUHS = 72;; +let _TMS320C64X_INS_MPYSU = 73;; +let _TMS320C64X_INS_MPYSU4 = 74;; +let _TMS320C64X_INS_MPYU = 75;; +let _TMS320C64X_INS_MPYU4 = 76;; +let _TMS320C64X_INS_MPYUS = 77;; +let _TMS320C64X_INS_MVC = 78;; +let _TMS320C64X_INS_MVD = 79;; +let _TMS320C64X_INS_MVK = 80;; +let _TMS320C64X_INS_MVKL = 81;; +let _TMS320C64X_INS_MVKLH = 82;; +let _TMS320C64X_INS_NOP = 83;; +let _TMS320C64X_INS_NORM = 84;; +let _TMS320C64X_INS_OR = 85;; +let _TMS320C64X_INS_PACK2 = 86;; +let _TMS320C64X_INS_PACKH2 = 87;; +let _TMS320C64X_INS_PACKH4 = 88;; +let _TMS320C64X_INS_PACKHL2 = 89;; +let _TMS320C64X_INS_PACKL4 = 90;; +let _TMS320C64X_INS_PACKLH2 = 91;; +let _TMS320C64X_INS_ROTL = 92;; +let _TMS320C64X_INS_SADD = 93;; +let _TMS320C64X_INS_SADD2 = 94;; +let _TMS320C64X_INS_SADDU4 = 95;; +let _TMS320C64X_INS_SADDUS2 = 96;; +let _TMS320C64X_INS_SAT = 97;; +let _TMS320C64X_INS_SET = 98;; +let _TMS320C64X_INS_SHFL = 99;; +let _TMS320C64X_INS_SHL = 100;; +let _TMS320C64X_INS_SHLMB = 101;; +let _TMS320C64X_INS_SHR = 102;; +let _TMS320C64X_INS_SHR2 = 103;; +let _TMS320C64X_INS_SHRMB = 104;; +let _TMS320C64X_INS_SHRU = 105;; +let _TMS320C64X_INS_SHRU2 = 106;; +let _TMS320C64X_INS_SMPY = 107;; +let _TMS320C64X_INS_SMPY2 = 108;; +let _TMS320C64X_INS_SMPYH = 109;; +let _TMS320C64X_INS_SMPYHL = 110;; +let _TMS320C64X_INS_SMPYLH = 111;; +let _TMS320C64X_INS_SPACK2 = 112;; +let _TMS320C64X_INS_SPACKU4 = 113;; +let _TMS320C64X_INS_SSHL = 114;; +let _TMS320C64X_INS_SSHVL = 115;; +let _TMS320C64X_INS_SSHVR = 116;; +let _TMS320C64X_INS_SSUB = 117;; +let _TMS320C64X_INS_STB = 118;; +let _TMS320C64X_INS_STDW = 119;; +let _TMS320C64X_INS_STH = 120;; +let _TMS320C64X_INS_STNDW = 121;; +let _TMS320C64X_INS_STNW = 122;; +let _TMS320C64X_INS_STW = 123;; +let _TMS320C64X_INS_SUB = 124;; +let _TMS320C64X_INS_SUB2 = 125;; +let _TMS320C64X_INS_SUB4 = 126;; +let _TMS320C64X_INS_SUBAB = 127;; +let _TMS320C64X_INS_SUBABS4 = 128;; +let _TMS320C64X_INS_SUBAH = 129;; +let _TMS320C64X_INS_SUBAW = 130;; +let _TMS320C64X_INS_SUBC = 131;; +let _TMS320C64X_INS_SUBU = 132;; +let _TMS320C64X_INS_SWAP4 = 133;; +let _TMS320C64X_INS_UNPKHU4 = 134;; +let _TMS320C64X_INS_UNPKLU4 = 135;; +let _TMS320C64X_INS_XOR = 136;; +let _TMS320C64X_INS_XPND2 = 137;; +let _TMS320C64X_INS_XPND4 = 138;; +let _TMS320C64X_INS_IDLE = 139;; +let _TMS320C64X_INS_MV = 140;; +let _TMS320C64X_INS_NEG = 141;; +let _TMS320C64X_INS_NOT = 142;; +let _TMS320C64X_INS_SWAP2 = 143;; +let _TMS320C64X_INS_ZERO = 144;; +let _TMS320C64X_INS_ENDING = 145;; + +let _TMS320C64X_GRP_INVALID = 0;; +let _TMS320C64X_GRP_JUMP = 1;; +let _TMS320C64X_GRP_FUNIT_D = 128;; +let _TMS320C64X_GRP_FUNIT_L = 129;; +let _TMS320C64X_GRP_FUNIT_M = 130;; +let _TMS320C64X_GRP_FUNIT_S = 131;; +let _TMS320C64X_GRP_FUNIT_NO = 132;; +let _TMS320C64X_GRP_ENDING = 133;; + +let _TMS320C64X_FUNIT_INVALID = 0;; +let _TMS320C64X_FUNIT_D = 1;; +let _TMS320C64X_FUNIT_L = 2;; +let _TMS320C64X_FUNIT_M = 3;; +let _TMS320C64X_FUNIT_S = 4;; +let _TMS320C64X_FUNIT_NO = 5;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/x86.ml b/white_patch_detect/capstone-master/bindings/ocaml/x86.ml new file mode 100644 index 0000000..9e97794 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/x86.ml @@ -0,0 +1,47 @@ +(* Capstone Disassembly Engine + * By Nguyen Anh Quynh , 2013-2014 *) + +open X86_const + +(* architecture specific info of instruction *) +type x86_op_mem = { + segment: int; + base: int; + index: int; + scale: int; + disp: int; +} + +type x86_op_value = + | X86_OP_INVALID of int + | X86_OP_REG of int + | X86_OP_IMM of int + | X86_OP_MEM of x86_op_mem + +type x86_op = { + value: x86_op_value; + size: int; + access: int; + avx_bcast: int; + avx_zero_opmask: int; +} + +type cs_x86 = { + prefix: int array; + opcode: int array; + rex: int; + addr_size: int; + modrm: int; + sib: int; + disp: int; + sib_index: int; + sib_scale: int; + sib_base: int; + xop_cc: int; + sse_cc: int; + avx_cc: int; + avx_sae: int; + avx_rm: int; + eflags: int; + operands: x86_op array; +} diff --git a/white_patch_detect/capstone-master/bindings/ocaml/x86_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/x86_const.ml new file mode 100644 index 0000000..a04a8e2 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/x86_const.ml @@ -0,0 +1,1962 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.ml] *) + +let _X86_REG_INVALID = 0;; +let _X86_REG_AH = 1;; +let _X86_REG_AL = 2;; +let _X86_REG_AX = 3;; +let _X86_REG_BH = 4;; +let _X86_REG_BL = 5;; +let _X86_REG_BP = 6;; +let _X86_REG_BPL = 7;; +let _X86_REG_BX = 8;; +let _X86_REG_CH = 9;; +let _X86_REG_CL = 10;; +let _X86_REG_CS = 11;; +let _X86_REG_CX = 12;; +let _X86_REG_DH = 13;; +let _X86_REG_DI = 14;; +let _X86_REG_DIL = 15;; +let _X86_REG_DL = 16;; +let _X86_REG_DS = 17;; +let _X86_REG_DX = 18;; +let _X86_REG_EAX = 19;; +let _X86_REG_EBP = 20;; +let _X86_REG_EBX = 21;; +let _X86_REG_ECX = 22;; +let _X86_REG_EDI = 23;; +let _X86_REG_EDX = 24;; +let _X86_REG_EFLAGS = 25;; +let _X86_REG_EIP = 26;; +let _X86_REG_EIZ = 27;; +let _X86_REG_ES = 28;; +let _X86_REG_ESI = 29;; +let _X86_REG_ESP = 30;; +let _X86_REG_FPSW = 31;; +let _X86_REG_FS = 32;; +let _X86_REG_GS = 33;; +let _X86_REG_IP = 34;; +let _X86_REG_RAX = 35;; +let _X86_REG_RBP = 36;; +let _X86_REG_RBX = 37;; +let _X86_REG_RCX = 38;; +let _X86_REG_RDI = 39;; +let _X86_REG_RDX = 40;; +let _X86_REG_RIP = 41;; +let _X86_REG_RIZ = 42;; +let _X86_REG_RSI = 43;; +let _X86_REG_RSP = 44;; +let _X86_REG_SI = 45;; +let _X86_REG_SIL = 46;; +let _X86_REG_SP = 47;; +let _X86_REG_SPL = 48;; +let _X86_REG_SS = 49;; +let _X86_REG_CR0 = 50;; +let _X86_REG_CR1 = 51;; +let _X86_REG_CR2 = 52;; +let _X86_REG_CR3 = 53;; +let _X86_REG_CR4 = 54;; +let _X86_REG_CR5 = 55;; +let _X86_REG_CR6 = 56;; +let _X86_REG_CR7 = 57;; +let _X86_REG_CR8 = 58;; +let _X86_REG_CR9 = 59;; +let _X86_REG_CR10 = 60;; +let _X86_REG_CR11 = 61;; +let _X86_REG_CR12 = 62;; +let _X86_REG_CR13 = 63;; +let _X86_REG_CR14 = 64;; +let _X86_REG_CR15 = 65;; +let _X86_REG_DR0 = 66;; +let _X86_REG_DR1 = 67;; +let _X86_REG_DR2 = 68;; +let _X86_REG_DR3 = 69;; +let _X86_REG_DR4 = 70;; +let _X86_REG_DR5 = 71;; +let _X86_REG_DR6 = 72;; +let _X86_REG_DR7 = 73;; +let _X86_REG_DR8 = 74;; +let _X86_REG_DR9 = 75;; +let _X86_REG_DR10 = 76;; +let _X86_REG_DR11 = 77;; +let _X86_REG_DR12 = 78;; +let _X86_REG_DR13 = 79;; +let _X86_REG_DR14 = 80;; +let _X86_REG_DR15 = 81;; +let _X86_REG_FP0 = 82;; +let _X86_REG_FP1 = 83;; +let _X86_REG_FP2 = 84;; +let _X86_REG_FP3 = 85;; +let _X86_REG_FP4 = 86;; +let _X86_REG_FP5 = 87;; +let _X86_REG_FP6 = 88;; +let _X86_REG_FP7 = 89;; +let _X86_REG_K0 = 90;; +let _X86_REG_K1 = 91;; +let _X86_REG_K2 = 92;; +let _X86_REG_K3 = 93;; +let _X86_REG_K4 = 94;; +let _X86_REG_K5 = 95;; +let _X86_REG_K6 = 96;; +let _X86_REG_K7 = 97;; +let _X86_REG_MM0 = 98;; +let _X86_REG_MM1 = 99;; +let _X86_REG_MM2 = 100;; +let _X86_REG_MM3 = 101;; +let _X86_REG_MM4 = 102;; +let _X86_REG_MM5 = 103;; +let _X86_REG_MM6 = 104;; +let _X86_REG_MM7 = 105;; +let _X86_REG_R8 = 106;; +let _X86_REG_R9 = 107;; +let _X86_REG_R10 = 108;; +let _X86_REG_R11 = 109;; +let _X86_REG_R12 = 110;; +let _X86_REG_R13 = 111;; +let _X86_REG_R14 = 112;; +let _X86_REG_R15 = 113;; +let _X86_REG_ST0 = 114;; +let _X86_REG_ST1 = 115;; +let _X86_REG_ST2 = 116;; +let _X86_REG_ST3 = 117;; +let _X86_REG_ST4 = 118;; +let _X86_REG_ST5 = 119;; +let _X86_REG_ST6 = 120;; +let _X86_REG_ST7 = 121;; +let _X86_REG_XMM0 = 122;; +let _X86_REG_XMM1 = 123;; +let _X86_REG_XMM2 = 124;; +let _X86_REG_XMM3 = 125;; +let _X86_REG_XMM4 = 126;; +let _X86_REG_XMM5 = 127;; +let _X86_REG_XMM6 = 128;; +let _X86_REG_XMM7 = 129;; +let _X86_REG_XMM8 = 130;; +let _X86_REG_XMM9 = 131;; +let _X86_REG_XMM10 = 132;; +let _X86_REG_XMM11 = 133;; +let _X86_REG_XMM12 = 134;; +let _X86_REG_XMM13 = 135;; +let _X86_REG_XMM14 = 136;; +let _X86_REG_XMM15 = 137;; +let _X86_REG_XMM16 = 138;; +let _X86_REG_XMM17 = 139;; +let _X86_REG_XMM18 = 140;; +let _X86_REG_XMM19 = 141;; +let _X86_REG_XMM20 = 142;; +let _X86_REG_XMM21 = 143;; +let _X86_REG_XMM22 = 144;; +let _X86_REG_XMM23 = 145;; +let _X86_REG_XMM24 = 146;; +let _X86_REG_XMM25 = 147;; +let _X86_REG_XMM26 = 148;; +let _X86_REG_XMM27 = 149;; +let _X86_REG_XMM28 = 150;; +let _X86_REG_XMM29 = 151;; +let _X86_REG_XMM30 = 152;; +let _X86_REG_XMM31 = 153;; +let _X86_REG_YMM0 = 154;; +let _X86_REG_YMM1 = 155;; +let _X86_REG_YMM2 = 156;; +let _X86_REG_YMM3 = 157;; +let _X86_REG_YMM4 = 158;; +let _X86_REG_YMM5 = 159;; +let _X86_REG_YMM6 = 160;; +let _X86_REG_YMM7 = 161;; +let _X86_REG_YMM8 = 162;; +let _X86_REG_YMM9 = 163;; +let _X86_REG_YMM10 = 164;; +let _X86_REG_YMM11 = 165;; +let _X86_REG_YMM12 = 166;; +let _X86_REG_YMM13 = 167;; +let _X86_REG_YMM14 = 168;; +let _X86_REG_YMM15 = 169;; +let _X86_REG_YMM16 = 170;; +let _X86_REG_YMM17 = 171;; +let _X86_REG_YMM18 = 172;; +let _X86_REG_YMM19 = 173;; +let _X86_REG_YMM20 = 174;; +let _X86_REG_YMM21 = 175;; +let _X86_REG_YMM22 = 176;; +let _X86_REG_YMM23 = 177;; +let _X86_REG_YMM24 = 178;; +let _X86_REG_YMM25 = 179;; +let _X86_REG_YMM26 = 180;; +let _X86_REG_YMM27 = 181;; +let _X86_REG_YMM28 = 182;; +let _X86_REG_YMM29 = 183;; +let _X86_REG_YMM30 = 184;; +let _X86_REG_YMM31 = 185;; +let _X86_REG_ZMM0 = 186;; +let _X86_REG_ZMM1 = 187;; +let _X86_REG_ZMM2 = 188;; +let _X86_REG_ZMM3 = 189;; +let _X86_REG_ZMM4 = 190;; +let _X86_REG_ZMM5 = 191;; +let _X86_REG_ZMM6 = 192;; +let _X86_REG_ZMM7 = 193;; +let _X86_REG_ZMM8 = 194;; +let _X86_REG_ZMM9 = 195;; +let _X86_REG_ZMM10 = 196;; +let _X86_REG_ZMM11 = 197;; +let _X86_REG_ZMM12 = 198;; +let _X86_REG_ZMM13 = 199;; +let _X86_REG_ZMM14 = 200;; +let _X86_REG_ZMM15 = 201;; +let _X86_REG_ZMM16 = 202;; +let _X86_REG_ZMM17 = 203;; +let _X86_REG_ZMM18 = 204;; +let _X86_REG_ZMM19 = 205;; +let _X86_REG_ZMM20 = 206;; +let _X86_REG_ZMM21 = 207;; +let _X86_REG_ZMM22 = 208;; +let _X86_REG_ZMM23 = 209;; +let _X86_REG_ZMM24 = 210;; +let _X86_REG_ZMM25 = 211;; +let _X86_REG_ZMM26 = 212;; +let _X86_REG_ZMM27 = 213;; +let _X86_REG_ZMM28 = 214;; +let _X86_REG_ZMM29 = 215;; +let _X86_REG_ZMM30 = 216;; +let _X86_REG_ZMM31 = 217;; +let _X86_REG_R8B = 218;; +let _X86_REG_R9B = 219;; +let _X86_REG_R10B = 220;; +let _X86_REG_R11B = 221;; +let _X86_REG_R12B = 222;; +let _X86_REG_R13B = 223;; +let _X86_REG_R14B = 224;; +let _X86_REG_R15B = 225;; +let _X86_REG_R8D = 226;; +let _X86_REG_R9D = 227;; +let _X86_REG_R10D = 228;; +let _X86_REG_R11D = 229;; +let _X86_REG_R12D = 230;; +let _X86_REG_R13D = 231;; +let _X86_REG_R14D = 232;; +let _X86_REG_R15D = 233;; +let _X86_REG_R8W = 234;; +let _X86_REG_R9W = 235;; +let _X86_REG_R10W = 236;; +let _X86_REG_R11W = 237;; +let _X86_REG_R12W = 238;; +let _X86_REG_R13W = 239;; +let _X86_REG_R14W = 240;; +let _X86_REG_R15W = 241;; +let _X86_REG_ENDING = 242;; +let _X86_EFLAGS_MODIFY_AF = 1 lsl 0;; +let _X86_EFLAGS_MODIFY_CF = 1 lsl 1;; +let _X86_EFLAGS_MODIFY_SF = 1 lsl 2;; +let _X86_EFLAGS_MODIFY_ZF = 1 lsl 3;; +let _X86_EFLAGS_MODIFY_PF = 1 lsl 4;; +let _X86_EFLAGS_MODIFY_OF = 1 lsl 5;; +let _X86_EFLAGS_MODIFY_TF = 1 lsl 6;; +let _X86_EFLAGS_MODIFY_IF = 1 lsl 7;; +let _X86_EFLAGS_MODIFY_DF = 1 lsl 8;; +let _X86_EFLAGS_MODIFY_NT = 1 lsl 9;; +let _X86_EFLAGS_MODIFY_RF = 1 lsl 10;; +let _X86_EFLAGS_PRIOR_OF = 1 lsl 11;; +let _X86_EFLAGS_PRIOR_SF = 1 lsl 12;; +let _X86_EFLAGS_PRIOR_ZF = 1 lsl 13;; +let _X86_EFLAGS_PRIOR_AF = 1 lsl 14;; +let _X86_EFLAGS_PRIOR_PF = 1 lsl 15;; +let _X86_EFLAGS_PRIOR_CF = 1 lsl 16;; +let _X86_EFLAGS_PRIOR_TF = 1 lsl 17;; +let _X86_EFLAGS_PRIOR_IF = 1 lsl 18;; +let _X86_EFLAGS_PRIOR_DF = 1 lsl 19;; +let _X86_EFLAGS_PRIOR_NT = 1 lsl 20;; +let _X86_EFLAGS_RESET_OF = 1 lsl 21;; +let _X86_EFLAGS_RESET_CF = 1 lsl 22;; +let _X86_EFLAGS_RESET_DF = 1 lsl 23;; +let _X86_EFLAGS_RESET_IF = 1 lsl 24;; +let _X86_EFLAGS_RESET_SF = 1 lsl 25;; +let _X86_EFLAGS_RESET_AF = 1 lsl 26;; +let _X86_EFLAGS_RESET_TF = 1 lsl 27;; +let _X86_EFLAGS_RESET_NT = 1 lsl 28;; +let _X86_EFLAGS_RESET_PF = 1 lsl 29;; +let _X86_EFLAGS_SET_CF = 1 lsl 30;; +let _X86_EFLAGS_SET_DF = 1 lsl 31;; +let _X86_EFLAGS_SET_IF = 1 lsl 32;; +let _X86_EFLAGS_TEST_OF = 1 lsl 33;; +let _X86_EFLAGS_TEST_SF = 1 lsl 34;; +let _X86_EFLAGS_TEST_ZF = 1 lsl 35;; +let _X86_EFLAGS_TEST_PF = 1 lsl 36;; +let _X86_EFLAGS_TEST_CF = 1 lsl 37;; +let _X86_EFLAGS_TEST_NT = 1 lsl 38;; +let _X86_EFLAGS_TEST_DF = 1 lsl 39;; +let _X86_EFLAGS_UNDEFINED_OF = 1 lsl 40;; +let _X86_EFLAGS_UNDEFINED_SF = 1 lsl 41;; +let _X86_EFLAGS_UNDEFINED_ZF = 1 lsl 42;; +let _X86_EFLAGS_UNDEFINED_PF = 1 lsl 43;; +let _X86_EFLAGS_UNDEFINED_AF = 1 lsl 44;; +let _X86_EFLAGS_UNDEFINED_CF = 1 lsl 45;; +let _X86_EFLAGS_RESET_RF = 1 lsl 46;; +let _X86_EFLAGS_TEST_RF = 1 lsl 47;; +let _X86_EFLAGS_TEST_IF = 1 lsl 48;; +let _X86_EFLAGS_TEST_TF = 1 lsl 49;; +let _X86_EFLAGS_TEST_AF = 1 lsl 50;; +let _X86_EFLAGS_RESET_ZF = 1 lsl 51;; +let _X86_EFLAGS_SET_OF = 1 lsl 52;; +let _X86_EFLAGS_SET_SF = 1 lsl 53;; +let _X86_EFLAGS_SET_ZF = 1 lsl 54;; +let _X86_EFLAGS_SET_AF = 1 lsl 55;; +let _X86_EFLAGS_SET_PF = 1 lsl 56;; +let _X86_EFLAGS_RESET_0F = 1 lsl 57;; +let _X86_EFLAGS_RESET_AC = 1 lsl 58;; +let _X86_FPU_FLAGS_MODIFY_C0 = 1 lsl 0;; +let _X86_FPU_FLAGS_MODIFY_C1 = 1 lsl 1;; +let _X86_FPU_FLAGS_MODIFY_C2 = 1 lsl 2;; +let _X86_FPU_FLAGS_MODIFY_C3 = 1 lsl 3;; +let _X86_FPU_FLAGS_RESET_C0 = 1 lsl 4;; +let _X86_FPU_FLAGS_RESET_C1 = 1 lsl 5;; +let _X86_FPU_FLAGS_RESET_C2 = 1 lsl 6;; +let _X86_FPU_FLAGS_RESET_C3 = 1 lsl 7;; +let _X86_FPU_FLAGS_SET_C0 = 1 lsl 8;; +let _X86_FPU_FLAGS_SET_C1 = 1 lsl 9;; +let _X86_FPU_FLAGS_SET_C2 = 1 lsl 10;; +let _X86_FPU_FLAGS_SET_C3 = 1 lsl 11;; +let _X86_FPU_FLAGS_UNDEFINED_C0 = 1 lsl 12;; +let _X86_FPU_FLAGS_UNDEFINED_C1 = 1 lsl 13;; +let _X86_FPU_FLAGS_UNDEFINED_C2 = 1 lsl 14;; +let _X86_FPU_FLAGS_UNDEFINED_C3 = 1 lsl 15;; +let _X86_FPU_FLAGS_TEST_C0 = 1 lsl 16;; +let _X86_FPU_FLAGS_TEST_C1 = 1 lsl 17;; +let _X86_FPU_FLAGS_TEST_C2 = 1 lsl 18;; +let _X86_FPU_FLAGS_TEST_C3 = 1 lsl 19;; + +let _X86_OP_INVALID = 0;; +let _X86_OP_REG = 1;; +let _X86_OP_IMM = 2;; +let _X86_OP_MEM = 3;; + +let _X86_XOP_CC_INVALID = 0;; +let _X86_XOP_CC_LT = 1;; +let _X86_XOP_CC_LE = 2;; +let _X86_XOP_CC_GT = 3;; +let _X86_XOP_CC_GE = 4;; +let _X86_XOP_CC_EQ = 5;; +let _X86_XOP_CC_NEQ = 6;; +let _X86_XOP_CC_FALSE = 7;; +let _X86_XOP_CC_TRUE = 8;; + +let _X86_AVX_BCAST_INVALID = 0;; +let _X86_AVX_BCAST_2 = 1;; +let _X86_AVX_BCAST_4 = 2;; +let _X86_AVX_BCAST_8 = 3;; +let _X86_AVX_BCAST_16 = 4;; + +let _X86_SSE_CC_INVALID = 0;; +let _X86_SSE_CC_EQ = 1;; +let _X86_SSE_CC_LT = 2;; +let _X86_SSE_CC_LE = 3;; +let _X86_SSE_CC_UNORD = 4;; +let _X86_SSE_CC_NEQ = 5;; +let _X86_SSE_CC_NLT = 6;; +let _X86_SSE_CC_NLE = 7;; +let _X86_SSE_CC_ORD = 8;; + +let _X86_AVX_CC_INVALID = 0;; +let _X86_AVX_CC_EQ = 1;; +let _X86_AVX_CC_LT = 2;; +let _X86_AVX_CC_LE = 3;; +let _X86_AVX_CC_UNORD = 4;; +let _X86_AVX_CC_NEQ = 5;; +let _X86_AVX_CC_NLT = 6;; +let _X86_AVX_CC_NLE = 7;; +let _X86_AVX_CC_ORD = 8;; +let _X86_AVX_CC_EQ_UQ = 9;; +let _X86_AVX_CC_NGE = 10;; +let _X86_AVX_CC_NGT = 11;; +let _X86_AVX_CC_FALSE = 12;; +let _X86_AVX_CC_NEQ_OQ = 13;; +let _X86_AVX_CC_GE = 14;; +let _X86_AVX_CC_GT = 15;; +let _X86_AVX_CC_TRUE = 16;; +let _X86_AVX_CC_EQ_OS = 17;; +let _X86_AVX_CC_LT_OQ = 18;; +let _X86_AVX_CC_LE_OQ = 19;; +let _X86_AVX_CC_UNORD_S = 20;; +let _X86_AVX_CC_NEQ_US = 21;; +let _X86_AVX_CC_NLT_UQ = 22;; +let _X86_AVX_CC_NLE_UQ = 23;; +let _X86_AVX_CC_ORD_S = 24;; +let _X86_AVX_CC_EQ_US = 25;; +let _X86_AVX_CC_NGE_UQ = 26;; +let _X86_AVX_CC_NGT_UQ = 27;; +let _X86_AVX_CC_FALSE_OS = 28;; +let _X86_AVX_CC_NEQ_OS = 29;; +let _X86_AVX_CC_GE_OQ = 30;; +let _X86_AVX_CC_GT_OQ = 31;; +let _X86_AVX_CC_TRUE_US = 32;; + +let _X86_AVX_RM_INVALID = 0;; +let _X86_AVX_RM_RN = 1;; +let _X86_AVX_RM_RD = 2;; +let _X86_AVX_RM_RU = 3;; +let _X86_AVX_RM_RZ = 4;; +let _X86_PREFIX_LOCK = 0xf0;; +let _X86_PREFIX_REP = 0xf3;; +let _X86_PREFIX_REPE = 0xf3;; +let _X86_PREFIX_REPNE = 0xf2;; +let _X86_PREFIX_CS = 0x2e;; +let _X86_PREFIX_SS = 0x36;; +let _X86_PREFIX_DS = 0x3e;; +let _X86_PREFIX_ES = 0x26;; +let _X86_PREFIX_FS = 0x64;; +let _X86_PREFIX_GS = 0x65;; +let _X86_PREFIX_OPSIZE = 0x66;; +let _X86_PREFIX_ADDRSIZE = 0x67;; + +let _X86_INS_INVALID = 0;; +let _X86_INS_AAA = 1;; +let _X86_INS_AAD = 2;; +let _X86_INS_AAM = 3;; +let _X86_INS_AAS = 4;; +let _X86_INS_FABS = 5;; +let _X86_INS_ADC = 6;; +let _X86_INS_ADCX = 7;; +let _X86_INS_ADD = 8;; +let _X86_INS_ADDPD = 9;; +let _X86_INS_ADDPS = 10;; +let _X86_INS_ADDSD = 11;; +let _X86_INS_ADDSS = 12;; +let _X86_INS_ADDSUBPD = 13;; +let _X86_INS_ADDSUBPS = 14;; +let _X86_INS_FADD = 15;; +let _X86_INS_FIADD = 16;; +let _X86_INS_FADDP = 17;; +let _X86_INS_ADOX = 18;; +let _X86_INS_AESDECLAST = 19;; +let _X86_INS_AESDEC = 20;; +let _X86_INS_AESENCLAST = 21;; +let _X86_INS_AESENC = 22;; +let _X86_INS_AESIMC = 23;; +let _X86_INS_AESKEYGENASSIST = 24;; +let _X86_INS_AND = 25;; +let _X86_INS_ANDN = 26;; +let _X86_INS_ANDNPD = 27;; +let _X86_INS_ANDNPS = 28;; +let _X86_INS_ANDPD = 29;; +let _X86_INS_ANDPS = 30;; +let _X86_INS_ARPL = 31;; +let _X86_INS_BEXTR = 32;; +let _X86_INS_BLCFILL = 33;; +let _X86_INS_BLCI = 34;; +let _X86_INS_BLCIC = 35;; +let _X86_INS_BLCMSK = 36;; +let _X86_INS_BLCS = 37;; +let _X86_INS_BLENDPD = 38;; +let _X86_INS_BLENDPS = 39;; +let _X86_INS_BLENDVPD = 40;; +let _X86_INS_BLENDVPS = 41;; +let _X86_INS_BLSFILL = 42;; +let _X86_INS_BLSI = 43;; +let _X86_INS_BLSIC = 44;; +let _X86_INS_BLSMSK = 45;; +let _X86_INS_BLSR = 46;; +let _X86_INS_BOUND = 47;; +let _X86_INS_BSF = 48;; +let _X86_INS_BSR = 49;; +let _X86_INS_BSWAP = 50;; +let _X86_INS_BT = 51;; +let _X86_INS_BTC = 52;; +let _X86_INS_BTR = 53;; +let _X86_INS_BTS = 54;; +let _X86_INS_BZHI = 55;; +let _X86_INS_CALL = 56;; +let _X86_INS_CBW = 57;; +let _X86_INS_CDQ = 58;; +let _X86_INS_CDQE = 59;; +let _X86_INS_FCHS = 60;; +let _X86_INS_CLAC = 61;; +let _X86_INS_CLC = 62;; +let _X86_INS_CLD = 63;; +let _X86_INS_CLFLUSH = 64;; +let _X86_INS_CLFLUSHOPT = 65;; +let _X86_INS_CLGI = 66;; +let _X86_INS_CLI = 67;; +let _X86_INS_CLTS = 68;; +let _X86_INS_CLWB = 69;; +let _X86_INS_CMC = 70;; +let _X86_INS_CMOVA = 71;; +let _X86_INS_CMOVAE = 72;; +let _X86_INS_CMOVB = 73;; +let _X86_INS_CMOVBE = 74;; +let _X86_INS_FCMOVBE = 75;; +let _X86_INS_FCMOVB = 76;; +let _X86_INS_CMOVE = 77;; +let _X86_INS_FCMOVE = 78;; +let _X86_INS_CMOVG = 79;; +let _X86_INS_CMOVGE = 80;; +let _X86_INS_CMOVL = 81;; +let _X86_INS_CMOVLE = 82;; +let _X86_INS_FCMOVNBE = 83;; +let _X86_INS_FCMOVNB = 84;; +let _X86_INS_CMOVNE = 85;; +let _X86_INS_FCMOVNE = 86;; +let _X86_INS_CMOVNO = 87;; +let _X86_INS_CMOVNP = 88;; +let _X86_INS_FCMOVNU = 89;; +let _X86_INS_CMOVNS = 90;; +let _X86_INS_CMOVO = 91;; +let _X86_INS_CMOVP = 92;; +let _X86_INS_FCMOVU = 93;; +let _X86_INS_CMOVS = 94;; +let _X86_INS_CMP = 95;; +let _X86_INS_CMPSB = 96;; +let _X86_INS_CMPSQ = 97;; +let _X86_INS_CMPSW = 98;; +let _X86_INS_CMPXCHG16B = 99;; +let _X86_INS_CMPXCHG = 100;; +let _X86_INS_CMPXCHG8B = 101;; +let _X86_INS_COMISD = 102;; +let _X86_INS_COMISS = 103;; +let _X86_INS_FCOMP = 104;; +let _X86_INS_FCOMIP = 105;; +let _X86_INS_FCOMI = 106;; +let _X86_INS_FCOM = 107;; +let _X86_INS_FCOS = 108;; +let _X86_INS_CPUID = 109;; +let _X86_INS_CQO = 110;; +let _X86_INS_CRC32 = 111;; +let _X86_INS_CVTDQ2PD = 112;; +let _X86_INS_CVTDQ2PS = 113;; +let _X86_INS_CVTPD2DQ = 114;; +let _X86_INS_CVTPD2PS = 115;; +let _X86_INS_CVTPS2DQ = 116;; +let _X86_INS_CVTPS2PD = 117;; +let _X86_INS_CVTSD2SI = 118;; +let _X86_INS_CVTSD2SS = 119;; +let _X86_INS_CVTSI2SD = 120;; +let _X86_INS_CVTSI2SS = 121;; +let _X86_INS_CVTSS2SD = 122;; +let _X86_INS_CVTSS2SI = 123;; +let _X86_INS_CVTTPD2DQ = 124;; +let _X86_INS_CVTTPS2DQ = 125;; +let _X86_INS_CVTTSD2SI = 126;; +let _X86_INS_CVTTSS2SI = 127;; +let _X86_INS_CWD = 128;; +let _X86_INS_CWDE = 129;; +let _X86_INS_DAA = 130;; +let _X86_INS_DAS = 131;; +let _X86_INS_DATA16 = 132;; +let _X86_INS_DEC = 133;; +let _X86_INS_DIV = 134;; +let _X86_INS_DIVPD = 135;; +let _X86_INS_DIVPS = 136;; +let _X86_INS_FDIVR = 137;; +let _X86_INS_FIDIVR = 138;; +let _X86_INS_FDIVRP = 139;; +let _X86_INS_DIVSD = 140;; +let _X86_INS_DIVSS = 141;; +let _X86_INS_FDIV = 142;; +let _X86_INS_FIDIV = 143;; +let _X86_INS_FDIVP = 144;; +let _X86_INS_DPPD = 145;; +let _X86_INS_DPPS = 146;; +let _X86_INS_RET = 147;; +let _X86_INS_ENCLS = 148;; +let _X86_INS_ENCLU = 149;; +let _X86_INS_ENTER = 150;; +let _X86_INS_EXTRACTPS = 151;; +let _X86_INS_EXTRQ = 152;; +let _X86_INS_F2XM1 = 153;; +let _X86_INS_LCALL = 154;; +let _X86_INS_LJMP = 155;; +let _X86_INS_FBLD = 156;; +let _X86_INS_FBSTP = 157;; +let _X86_INS_FCOMPP = 158;; +let _X86_INS_FDECSTP = 159;; +let _X86_INS_FEMMS = 160;; +let _X86_INS_FFREE = 161;; +let _X86_INS_FICOM = 162;; +let _X86_INS_FICOMP = 163;; +let _X86_INS_FINCSTP = 164;; +let _X86_INS_FLDCW = 165;; +let _X86_INS_FLDENV = 166;; +let _X86_INS_FLDL2E = 167;; +let _X86_INS_FLDL2T = 168;; +let _X86_INS_FLDLG2 = 169;; +let _X86_INS_FLDLN2 = 170;; +let _X86_INS_FLDPI = 171;; +let _X86_INS_FNCLEX = 172;; +let _X86_INS_FNINIT = 173;; +let _X86_INS_FNOP = 174;; +let _X86_INS_FNSTCW = 175;; +let _X86_INS_FNSTSW = 176;; +let _X86_INS_FPATAN = 177;; +let _X86_INS_FPREM = 178;; +let _X86_INS_FPREM1 = 179;; +let _X86_INS_FPTAN = 180;; +let _X86_INS_FFREEP = 181;; +let _X86_INS_FRNDINT = 182;; +let _X86_INS_FRSTOR = 183;; +let _X86_INS_FNSAVE = 184;; +let _X86_INS_FSCALE = 185;; +let _X86_INS_FSETPM = 186;; +let _X86_INS_FSINCOS = 187;; +let _X86_INS_FNSTENV = 188;; +let _X86_INS_FXAM = 189;; +let _X86_INS_FXRSTOR = 190;; +let _X86_INS_FXRSTOR64 = 191;; +let _X86_INS_FXSAVE = 192;; +let _X86_INS_FXSAVE64 = 193;; +let _X86_INS_FXTRACT = 194;; +let _X86_INS_FYL2X = 195;; +let _X86_INS_FYL2XP1 = 196;; +let _X86_INS_MOVAPD = 197;; +let _X86_INS_MOVAPS = 198;; +let _X86_INS_ORPD = 199;; +let _X86_INS_ORPS = 200;; +let _X86_INS_VMOVAPD = 201;; +let _X86_INS_VMOVAPS = 202;; +let _X86_INS_XORPD = 203;; +let _X86_INS_XORPS = 204;; +let _X86_INS_GETSEC = 205;; +let _X86_INS_HADDPD = 206;; +let _X86_INS_HADDPS = 207;; +let _X86_INS_HLT = 208;; +let _X86_INS_HSUBPD = 209;; +let _X86_INS_HSUBPS = 210;; +let _X86_INS_IDIV = 211;; +let _X86_INS_FILD = 212;; +let _X86_INS_IMUL = 213;; +let _X86_INS_IN = 214;; +let _X86_INS_INC = 215;; +let _X86_INS_INSB = 216;; +let _X86_INS_INSERTPS = 217;; +let _X86_INS_INSERTQ = 218;; +let _X86_INS_INSD = 219;; +let _X86_INS_INSW = 220;; +let _X86_INS_INT = 221;; +let _X86_INS_INT1 = 222;; +let _X86_INS_INT3 = 223;; +let _X86_INS_INTO = 224;; +let _X86_INS_INVD = 225;; +let _X86_INS_INVEPT = 226;; +let _X86_INS_INVLPG = 227;; +let _X86_INS_INVLPGA = 228;; +let _X86_INS_INVPCID = 229;; +let _X86_INS_INVVPID = 230;; +let _X86_INS_IRET = 231;; +let _X86_INS_IRETD = 232;; +let _X86_INS_IRETQ = 233;; +let _X86_INS_FISTTP = 234;; +let _X86_INS_FIST = 235;; +let _X86_INS_FISTP = 236;; +let _X86_INS_UCOMISD = 237;; +let _X86_INS_UCOMISS = 238;; +let _X86_INS_VCOMISD = 239;; +let _X86_INS_VCOMISS = 240;; +let _X86_INS_VCVTSD2SS = 241;; +let _X86_INS_VCVTSI2SD = 242;; +let _X86_INS_VCVTSI2SS = 243;; +let _X86_INS_VCVTSS2SD = 244;; +let _X86_INS_VCVTTSD2SI = 245;; +let _X86_INS_VCVTTSD2USI = 246;; +let _X86_INS_VCVTTSS2SI = 247;; +let _X86_INS_VCVTTSS2USI = 248;; +let _X86_INS_VCVTUSI2SD = 249;; +let _X86_INS_VCVTUSI2SS = 250;; +let _X86_INS_VUCOMISD = 251;; +let _X86_INS_VUCOMISS = 252;; +let _X86_INS_JAE = 253;; +let _X86_INS_JA = 254;; +let _X86_INS_JBE = 255;; +let _X86_INS_JB = 256;; +let _X86_INS_JCXZ = 257;; +let _X86_INS_JECXZ = 258;; +let _X86_INS_JE = 259;; +let _X86_INS_JGE = 260;; +let _X86_INS_JG = 261;; +let _X86_INS_JLE = 262;; +let _X86_INS_JL = 263;; +let _X86_INS_JMP = 264;; +let _X86_INS_JNE = 265;; +let _X86_INS_JNO = 266;; +let _X86_INS_JNP = 267;; +let _X86_INS_JNS = 268;; +let _X86_INS_JO = 269;; +let _X86_INS_JP = 270;; +let _X86_INS_JRCXZ = 271;; +let _X86_INS_JS = 272;; +let _X86_INS_KANDB = 273;; +let _X86_INS_KANDD = 274;; +let _X86_INS_KANDNB = 275;; +let _X86_INS_KANDND = 276;; +let _X86_INS_KANDNQ = 277;; +let _X86_INS_KANDNW = 278;; +let _X86_INS_KANDQ = 279;; +let _X86_INS_KANDW = 280;; +let _X86_INS_KMOVB = 281;; +let _X86_INS_KMOVD = 282;; +let _X86_INS_KMOVQ = 283;; +let _X86_INS_KMOVW = 284;; +let _X86_INS_KNOTB = 285;; +let _X86_INS_KNOTD = 286;; +let _X86_INS_KNOTQ = 287;; +let _X86_INS_KNOTW = 288;; +let _X86_INS_KORB = 289;; +let _X86_INS_KORD = 290;; +let _X86_INS_KORQ = 291;; +let _X86_INS_KORTESTB = 292;; +let _X86_INS_KORTESTD = 293;; +let _X86_INS_KORTESTQ = 294;; +let _X86_INS_KORTESTW = 295;; +let _X86_INS_KORW = 296;; +let _X86_INS_KSHIFTLB = 297;; +let _X86_INS_KSHIFTLD = 298;; +let _X86_INS_KSHIFTLQ = 299;; +let _X86_INS_KSHIFTLW = 300;; +let _X86_INS_KSHIFTRB = 301;; +let _X86_INS_KSHIFTRD = 302;; +let _X86_INS_KSHIFTRQ = 303;; +let _X86_INS_KSHIFTRW = 304;; +let _X86_INS_KUNPCKBW = 305;; +let _X86_INS_KXNORB = 306;; +let _X86_INS_KXNORD = 307;; +let _X86_INS_KXNORQ = 308;; +let _X86_INS_KXNORW = 309;; +let _X86_INS_KXORB = 310;; +let _X86_INS_KXORD = 311;; +let _X86_INS_KXORQ = 312;; +let _X86_INS_KXORW = 313;; +let _X86_INS_LAHF = 314;; +let _X86_INS_LAR = 315;; +let _X86_INS_LDDQU = 316;; +let _X86_INS_LDMXCSR = 317;; +let _X86_INS_LDS = 318;; +let _X86_INS_FLDZ = 319;; +let _X86_INS_FLD1 = 320;; +let _X86_INS_FLD = 321;; +let _X86_INS_LEA = 322;; +let _X86_INS_LEAVE = 323;; +let _X86_INS_LES = 324;; +let _X86_INS_LFENCE = 325;; +let _X86_INS_LFS = 326;; +let _X86_INS_LGDT = 327;; +let _X86_INS_LGS = 328;; +let _X86_INS_LIDT = 329;; +let _X86_INS_LLDT = 330;; +let _X86_INS_LMSW = 331;; +let _X86_INS_OR = 332;; +let _X86_INS_SUB = 333;; +let _X86_INS_XOR = 334;; +let _X86_INS_LODSB = 335;; +let _X86_INS_LODSD = 336;; +let _X86_INS_LODSQ = 337;; +let _X86_INS_LODSW = 338;; +let _X86_INS_LOOP = 339;; +let _X86_INS_LOOPE = 340;; +let _X86_INS_LOOPNE = 341;; +let _X86_INS_RETF = 342;; +let _X86_INS_RETFQ = 343;; +let _X86_INS_LSL = 344;; +let _X86_INS_LSS = 345;; +let _X86_INS_LTR = 346;; +let _X86_INS_XADD = 347;; +let _X86_INS_LZCNT = 348;; +let _X86_INS_MASKMOVDQU = 349;; +let _X86_INS_MAXPD = 350;; +let _X86_INS_MAXPS = 351;; +let _X86_INS_MAXSD = 352;; +let _X86_INS_MAXSS = 353;; +let _X86_INS_MFENCE = 354;; +let _X86_INS_MINPD = 355;; +let _X86_INS_MINPS = 356;; +let _X86_INS_MINSD = 357;; +let _X86_INS_MINSS = 358;; +let _X86_INS_CVTPD2PI = 359;; +let _X86_INS_CVTPI2PD = 360;; +let _X86_INS_CVTPI2PS = 361;; +let _X86_INS_CVTPS2PI = 362;; +let _X86_INS_CVTTPD2PI = 363;; +let _X86_INS_CVTTPS2PI = 364;; +let _X86_INS_EMMS = 365;; +let _X86_INS_MASKMOVQ = 366;; +let _X86_INS_MOVD = 367;; +let _X86_INS_MOVDQ2Q = 368;; +let _X86_INS_MOVNTQ = 369;; +let _X86_INS_MOVQ2DQ = 370;; +let _X86_INS_MOVQ = 371;; +let _X86_INS_PABSB = 372;; +let _X86_INS_PABSD = 373;; +let _X86_INS_PABSW = 374;; +let _X86_INS_PACKSSDW = 375;; +let _X86_INS_PACKSSWB = 376;; +let _X86_INS_PACKUSWB = 377;; +let _X86_INS_PADDB = 378;; +let _X86_INS_PADDD = 379;; +let _X86_INS_PADDQ = 380;; +let _X86_INS_PADDSB = 381;; +let _X86_INS_PADDSW = 382;; +let _X86_INS_PADDUSB = 383;; +let _X86_INS_PADDUSW = 384;; +let _X86_INS_PADDW = 385;; +let _X86_INS_PALIGNR = 386;; +let _X86_INS_PANDN = 387;; +let _X86_INS_PAND = 388;; +let _X86_INS_PAVGB = 389;; +let _X86_INS_PAVGW = 390;; +let _X86_INS_PCMPEQB = 391;; +let _X86_INS_PCMPEQD = 392;; +let _X86_INS_PCMPEQW = 393;; +let _X86_INS_PCMPGTB = 394;; +let _X86_INS_PCMPGTD = 395;; +let _X86_INS_PCMPGTW = 396;; +let _X86_INS_PEXTRW = 397;; +let _X86_INS_PHADDSW = 398;; +let _X86_INS_PHADDW = 399;; +let _X86_INS_PHADDD = 400;; +let _X86_INS_PHSUBD = 401;; +let _X86_INS_PHSUBSW = 402;; +let _X86_INS_PHSUBW = 403;; +let _X86_INS_PINSRW = 404;; +let _X86_INS_PMADDUBSW = 405;; +let _X86_INS_PMADDWD = 406;; +let _X86_INS_PMAXSW = 407;; +let _X86_INS_PMAXUB = 408;; +let _X86_INS_PMINSW = 409;; +let _X86_INS_PMINUB = 410;; +let _X86_INS_PMOVMSKB = 411;; +let _X86_INS_PMULHRSW = 412;; +let _X86_INS_PMULHUW = 413;; +let _X86_INS_PMULHW = 414;; +let _X86_INS_PMULLW = 415;; +let _X86_INS_PMULUDQ = 416;; +let _X86_INS_POR = 417;; +let _X86_INS_PSADBW = 418;; +let _X86_INS_PSHUFB = 419;; +let _X86_INS_PSHUFW = 420;; +let _X86_INS_PSIGNB = 421;; +let _X86_INS_PSIGND = 422;; +let _X86_INS_PSIGNW = 423;; +let _X86_INS_PSLLD = 424;; +let _X86_INS_PSLLQ = 425;; +let _X86_INS_PSLLW = 426;; +let _X86_INS_PSRAD = 427;; +let _X86_INS_PSRAW = 428;; +let _X86_INS_PSRLD = 429;; +let _X86_INS_PSRLQ = 430;; +let _X86_INS_PSRLW = 431;; +let _X86_INS_PSUBB = 432;; +let _X86_INS_PSUBD = 433;; +let _X86_INS_PSUBQ = 434;; +let _X86_INS_PSUBSB = 435;; +let _X86_INS_PSUBSW = 436;; +let _X86_INS_PSUBUSB = 437;; +let _X86_INS_PSUBUSW = 438;; +let _X86_INS_PSUBW = 439;; +let _X86_INS_PUNPCKHBW = 440;; +let _X86_INS_PUNPCKHDQ = 441;; +let _X86_INS_PUNPCKHWD = 442;; +let _X86_INS_PUNPCKLBW = 443;; +let _X86_INS_PUNPCKLDQ = 444;; +let _X86_INS_PUNPCKLWD = 445;; +let _X86_INS_PXOR = 446;; +let _X86_INS_MONITOR = 447;; +let _X86_INS_MONTMUL = 448;; +let _X86_INS_MOV = 449;; +let _X86_INS_MOVABS = 450;; +let _X86_INS_MOVBE = 451;; +let _X86_INS_MOVDDUP = 452;; +let _X86_INS_MOVDQA = 453;; +let _X86_INS_MOVDQU = 454;; +let _X86_INS_MOVHLPS = 455;; +let _X86_INS_MOVHPD = 456;; +let _X86_INS_MOVHPS = 457;; +let _X86_INS_MOVLHPS = 458;; +let _X86_INS_MOVLPD = 459;; +let _X86_INS_MOVLPS = 460;; +let _X86_INS_MOVMSKPD = 461;; +let _X86_INS_MOVMSKPS = 462;; +let _X86_INS_MOVNTDQA = 463;; +let _X86_INS_MOVNTDQ = 464;; +let _X86_INS_MOVNTI = 465;; +let _X86_INS_MOVNTPD = 466;; +let _X86_INS_MOVNTPS = 467;; +let _X86_INS_MOVNTSD = 468;; +let _X86_INS_MOVNTSS = 469;; +let _X86_INS_MOVSB = 470;; +let _X86_INS_MOVSD = 471;; +let _X86_INS_MOVSHDUP = 472;; +let _X86_INS_MOVSLDUP = 473;; +let _X86_INS_MOVSQ = 474;; +let _X86_INS_MOVSS = 475;; +let _X86_INS_MOVSW = 476;; +let _X86_INS_MOVSX = 477;; +let _X86_INS_MOVSXD = 478;; +let _X86_INS_MOVUPD = 479;; +let _X86_INS_MOVUPS = 480;; +let _X86_INS_MOVZX = 481;; +let _X86_INS_MPSADBW = 482;; +let _X86_INS_MUL = 483;; +let _X86_INS_MULPD = 484;; +let _X86_INS_MULPS = 485;; +let _X86_INS_MULSD = 486;; +let _X86_INS_MULSS = 487;; +let _X86_INS_MULX = 488;; +let _X86_INS_FMUL = 489;; +let _X86_INS_FIMUL = 490;; +let _X86_INS_FMULP = 491;; +let _X86_INS_MWAIT = 492;; +let _X86_INS_NEG = 493;; +let _X86_INS_NOP = 494;; +let _X86_INS_NOT = 495;; +let _X86_INS_OUT = 496;; +let _X86_INS_OUTSB = 497;; +let _X86_INS_OUTSD = 498;; +let _X86_INS_OUTSW = 499;; +let _X86_INS_PACKUSDW = 500;; +let _X86_INS_PAUSE = 501;; +let _X86_INS_PAVGUSB = 502;; +let _X86_INS_PBLENDVB = 503;; +let _X86_INS_PBLENDW = 504;; +let _X86_INS_PCLMULQDQ = 505;; +let _X86_INS_PCMPEQQ = 506;; +let _X86_INS_PCMPESTRI = 507;; +let _X86_INS_PCMPESTRM = 508;; +let _X86_INS_PCMPGTQ = 509;; +let _X86_INS_PCMPISTRI = 510;; +let _X86_INS_PCMPISTRM = 511;; +let _X86_INS_PCOMMIT = 512;; +let _X86_INS_PDEP = 513;; +let _X86_INS_PEXT = 514;; +let _X86_INS_PEXTRB = 515;; +let _X86_INS_PEXTRD = 516;; +let _X86_INS_PEXTRQ = 517;; +let _X86_INS_PF2ID = 518;; +let _X86_INS_PF2IW = 519;; +let _X86_INS_PFACC = 520;; +let _X86_INS_PFADD = 521;; +let _X86_INS_PFCMPEQ = 522;; +let _X86_INS_PFCMPGE = 523;; +let _X86_INS_PFCMPGT = 524;; +let _X86_INS_PFMAX = 525;; +let _X86_INS_PFMIN = 526;; +let _X86_INS_PFMUL = 527;; +let _X86_INS_PFNACC = 528;; +let _X86_INS_PFPNACC = 529;; +let _X86_INS_PFRCPIT1 = 530;; +let _X86_INS_PFRCPIT2 = 531;; +let _X86_INS_PFRCP = 532;; +let _X86_INS_PFRSQIT1 = 533;; +let _X86_INS_PFRSQRT = 534;; +let _X86_INS_PFSUBR = 535;; +let _X86_INS_PFSUB = 536;; +let _X86_INS_PHMINPOSUW = 537;; +let _X86_INS_PI2FD = 538;; +let _X86_INS_PI2FW = 539;; +let _X86_INS_PINSRB = 540;; +let _X86_INS_PINSRD = 541;; +let _X86_INS_PINSRQ = 542;; +let _X86_INS_PMAXSB = 543;; +let _X86_INS_PMAXSD = 544;; +let _X86_INS_PMAXUD = 545;; +let _X86_INS_PMAXUW = 546;; +let _X86_INS_PMINSB = 547;; +let _X86_INS_PMINSD = 548;; +let _X86_INS_PMINUD = 549;; +let _X86_INS_PMINUW = 550;; +let _X86_INS_PMOVSXBD = 551;; +let _X86_INS_PMOVSXBQ = 552;; +let _X86_INS_PMOVSXBW = 553;; +let _X86_INS_PMOVSXDQ = 554;; +let _X86_INS_PMOVSXWD = 555;; +let _X86_INS_PMOVSXWQ = 556;; +let _X86_INS_PMOVZXBD = 557;; +let _X86_INS_PMOVZXBQ = 558;; +let _X86_INS_PMOVZXBW = 559;; +let _X86_INS_PMOVZXDQ = 560;; +let _X86_INS_PMOVZXWD = 561;; +let _X86_INS_PMOVZXWQ = 562;; +let _X86_INS_PMULDQ = 563;; +let _X86_INS_PMULHRW = 564;; +let _X86_INS_PMULLD = 565;; +let _X86_INS_POP = 566;; +let _X86_INS_POPAW = 567;; +let _X86_INS_POPAL = 568;; +let _X86_INS_POPCNT = 569;; +let _X86_INS_POPF = 570;; +let _X86_INS_POPFD = 571;; +let _X86_INS_POPFQ = 572;; +let _X86_INS_PREFETCH = 573;; +let _X86_INS_PREFETCHNTA = 574;; +let _X86_INS_PREFETCHT0 = 575;; +let _X86_INS_PREFETCHT1 = 576;; +let _X86_INS_PREFETCHT2 = 577;; +let _X86_INS_PREFETCHW = 578;; +let _X86_INS_PSHUFD = 579;; +let _X86_INS_PSHUFHW = 580;; +let _X86_INS_PSHUFLW = 581;; +let _X86_INS_PSLLDQ = 582;; +let _X86_INS_PSRLDQ = 583;; +let _X86_INS_PSWAPD = 584;; +let _X86_INS_PTEST = 585;; +let _X86_INS_PUNPCKHQDQ = 586;; +let _X86_INS_PUNPCKLQDQ = 587;; +let _X86_INS_PUSH = 588;; +let _X86_INS_PUSHAW = 589;; +let _X86_INS_PUSHAL = 590;; +let _X86_INS_PUSHF = 591;; +let _X86_INS_PUSHFD = 592;; +let _X86_INS_PUSHFQ = 593;; +let _X86_INS_RCL = 594;; +let _X86_INS_RCPPS = 595;; +let _X86_INS_RCPSS = 596;; +let _X86_INS_RCR = 597;; +let _X86_INS_RDFSBASE = 598;; +let _X86_INS_RDGSBASE = 599;; +let _X86_INS_RDMSR = 600;; +let _X86_INS_RDPMC = 601;; +let _X86_INS_RDRAND = 602;; +let _X86_INS_RDSEED = 603;; +let _X86_INS_RDTSC = 604;; +let _X86_INS_RDTSCP = 605;; +let _X86_INS_ROL = 606;; +let _X86_INS_ROR = 607;; +let _X86_INS_RORX = 608;; +let _X86_INS_ROUNDPD = 609;; +let _X86_INS_ROUNDPS = 610;; +let _X86_INS_ROUNDSD = 611;; +let _X86_INS_ROUNDSS = 612;; +let _X86_INS_RSM = 613;; +let _X86_INS_RSQRTPS = 614;; +let _X86_INS_RSQRTSS = 615;; +let _X86_INS_SAHF = 616;; +let _X86_INS_SAL = 617;; +let _X86_INS_SALC = 618;; +let _X86_INS_SAR = 619;; +let _X86_INS_SARX = 620;; +let _X86_INS_SBB = 621;; +let _X86_INS_SCASB = 622;; +let _X86_INS_SCASD = 623;; +let _X86_INS_SCASQ = 624;; +let _X86_INS_SCASW = 625;; +let _X86_INS_SETAE = 626;; +let _X86_INS_SETA = 627;; +let _X86_INS_SETBE = 628;; +let _X86_INS_SETB = 629;; +let _X86_INS_SETE = 630;; +let _X86_INS_SETGE = 631;; +let _X86_INS_SETG = 632;; +let _X86_INS_SETLE = 633;; +let _X86_INS_SETL = 634;; +let _X86_INS_SETNE = 635;; +let _X86_INS_SETNO = 636;; +let _X86_INS_SETNP = 637;; +let _X86_INS_SETNS = 638;; +let _X86_INS_SETO = 639;; +let _X86_INS_SETP = 640;; +let _X86_INS_SETS = 641;; +let _X86_INS_SFENCE = 642;; +let _X86_INS_SGDT = 643;; +let _X86_INS_SHA1MSG1 = 644;; +let _X86_INS_SHA1MSG2 = 645;; +let _X86_INS_SHA1NEXTE = 646;; +let _X86_INS_SHA1RNDS4 = 647;; +let _X86_INS_SHA256MSG1 = 648;; +let _X86_INS_SHA256MSG2 = 649;; +let _X86_INS_SHA256RNDS2 = 650;; +let _X86_INS_SHL = 651;; +let _X86_INS_SHLD = 652;; +let _X86_INS_SHLX = 653;; +let _X86_INS_SHR = 654;; +let _X86_INS_SHRD = 655;; +let _X86_INS_SHRX = 656;; +let _X86_INS_SHUFPD = 657;; +let _X86_INS_SHUFPS = 658;; +let _X86_INS_SIDT = 659;; +let _X86_INS_FSIN = 660;; +let _X86_INS_SKINIT = 661;; +let _X86_INS_SLDT = 662;; +let _X86_INS_SMSW = 663;; +let _X86_INS_SQRTPD = 664;; +let _X86_INS_SQRTPS = 665;; +let _X86_INS_SQRTSD = 666;; +let _X86_INS_SQRTSS = 667;; +let _X86_INS_FSQRT = 668;; +let _X86_INS_STAC = 669;; +let _X86_INS_STC = 670;; +let _X86_INS_STD = 671;; +let _X86_INS_STGI = 672;; +let _X86_INS_STI = 673;; +let _X86_INS_STMXCSR = 674;; +let _X86_INS_STOSB = 675;; +let _X86_INS_STOSD = 676;; +let _X86_INS_STOSQ = 677;; +let _X86_INS_STOSW = 678;; +let _X86_INS_STR = 679;; +let _X86_INS_FST = 680;; +let _X86_INS_FSTP = 681;; +let _X86_INS_FSTPNCE = 682;; +let _X86_INS_FXCH = 683;; +let _X86_INS_SUBPD = 684;; +let _X86_INS_SUBPS = 685;; +let _X86_INS_FSUBR = 686;; +let _X86_INS_FISUBR = 687;; +let _X86_INS_FSUBRP = 688;; +let _X86_INS_SUBSD = 689;; +let _X86_INS_SUBSS = 690;; +let _X86_INS_FSUB = 691;; +let _X86_INS_FISUB = 692;; +let _X86_INS_FSUBP = 693;; +let _X86_INS_SWAPGS = 694;; +let _X86_INS_SYSCALL = 695;; +let _X86_INS_SYSENTER = 696;; +let _X86_INS_SYSEXIT = 697;; +let _X86_INS_SYSRET = 698;; +let _X86_INS_T1MSKC = 699;; +let _X86_INS_TEST = 700;; +let _X86_INS_UD2 = 701;; +let _X86_INS_FTST = 702;; +let _X86_INS_TZCNT = 703;; +let _X86_INS_TZMSK = 704;; +let _X86_INS_FUCOMIP = 705;; +let _X86_INS_FUCOMI = 706;; +let _X86_INS_FUCOMPP = 707;; +let _X86_INS_FUCOMP = 708;; +let _X86_INS_FUCOM = 709;; +let _X86_INS_UD2B = 710;; +let _X86_INS_UNPCKHPD = 711;; +let _X86_INS_UNPCKHPS = 712;; +let _X86_INS_UNPCKLPD = 713;; +let _X86_INS_UNPCKLPS = 714;; +let _X86_INS_VADDPD = 715;; +let _X86_INS_VADDPS = 716;; +let _X86_INS_VADDSD = 717;; +let _X86_INS_VADDSS = 718;; +let _X86_INS_VADDSUBPD = 719;; +let _X86_INS_VADDSUBPS = 720;; +let _X86_INS_VAESDECLAST = 721;; +let _X86_INS_VAESDEC = 722;; +let _X86_INS_VAESENCLAST = 723;; +let _X86_INS_VAESENC = 724;; +let _X86_INS_VAESIMC = 725;; +let _X86_INS_VAESKEYGENASSIST = 726;; +let _X86_INS_VALIGND = 727;; +let _X86_INS_VALIGNQ = 728;; +let _X86_INS_VANDNPD = 729;; +let _X86_INS_VANDNPS = 730;; +let _X86_INS_VANDPD = 731;; +let _X86_INS_VANDPS = 732;; +let _X86_INS_VBLENDMPD = 733;; +let _X86_INS_VBLENDMPS = 734;; +let _X86_INS_VBLENDPD = 735;; +let _X86_INS_VBLENDPS = 736;; +let _X86_INS_VBLENDVPD = 737;; +let _X86_INS_VBLENDVPS = 738;; +let _X86_INS_VBROADCASTF128 = 739;; +let _X86_INS_VBROADCASTI32X4 = 740;; +let _X86_INS_VBROADCASTI64X4 = 741;; +let _X86_INS_VBROADCASTSD = 742;; +let _X86_INS_VBROADCASTSS = 743;; +let _X86_INS_VCOMPRESSPD = 744;; +let _X86_INS_VCOMPRESSPS = 745;; +let _X86_INS_VCVTDQ2PD = 746;; +let _X86_INS_VCVTDQ2PS = 747;; +let _X86_INS_VCVTPD2DQX = 748;; +let _X86_INS_VCVTPD2DQ = 749;; +let _X86_INS_VCVTPD2PSX = 750;; +let _X86_INS_VCVTPD2PS = 751;; +let _X86_INS_VCVTPD2UDQ = 752;; +let _X86_INS_VCVTPH2PS = 753;; +let _X86_INS_VCVTPS2DQ = 754;; +let _X86_INS_VCVTPS2PD = 755;; +let _X86_INS_VCVTPS2PH = 756;; +let _X86_INS_VCVTPS2UDQ = 757;; +let _X86_INS_VCVTSD2SI = 758;; +let _X86_INS_VCVTSD2USI = 759;; +let _X86_INS_VCVTSS2SI = 760;; +let _X86_INS_VCVTSS2USI = 761;; +let _X86_INS_VCVTTPD2DQX = 762;; +let _X86_INS_VCVTTPD2DQ = 763;; +let _X86_INS_VCVTTPD2UDQ = 764;; +let _X86_INS_VCVTTPS2DQ = 765;; +let _X86_INS_VCVTTPS2UDQ = 766;; +let _X86_INS_VCVTUDQ2PD = 767;; +let _X86_INS_VCVTUDQ2PS = 768;; +let _X86_INS_VDIVPD = 769;; +let _X86_INS_VDIVPS = 770;; +let _X86_INS_VDIVSD = 771;; +let _X86_INS_VDIVSS = 772;; +let _X86_INS_VDPPD = 773;; +let _X86_INS_VDPPS = 774;; +let _X86_INS_VERR = 775;; +let _X86_INS_VERW = 776;; +let _X86_INS_VEXP2PD = 777;; +let _X86_INS_VEXP2PS = 778;; +let _X86_INS_VEXPANDPD = 779;; +let _X86_INS_VEXPANDPS = 780;; +let _X86_INS_VEXTRACTF128 = 781;; +let _X86_INS_VEXTRACTF32X4 = 782;; +let _X86_INS_VEXTRACTF64X4 = 783;; +let _X86_INS_VEXTRACTI128 = 784;; +let _X86_INS_VEXTRACTI32X4 = 785;; +let _X86_INS_VEXTRACTI64X4 = 786;; +let _X86_INS_VEXTRACTPS = 787;; +let _X86_INS_VFMADD132PD = 788;; +let _X86_INS_VFMADD132PS = 789;; +let _X86_INS_VFMADDPD = 790;; +let _X86_INS_VFMADD213PD = 791;; +let _X86_INS_VFMADD231PD = 792;; +let _X86_INS_VFMADDPS = 793;; +let _X86_INS_VFMADD213PS = 794;; +let _X86_INS_VFMADD231PS = 795;; +let _X86_INS_VFMADDSD = 796;; +let _X86_INS_VFMADD213SD = 797;; +let _X86_INS_VFMADD132SD = 798;; +let _X86_INS_VFMADD231SD = 799;; +let _X86_INS_VFMADDSS = 800;; +let _X86_INS_VFMADD213SS = 801;; +let _X86_INS_VFMADD132SS = 802;; +let _X86_INS_VFMADD231SS = 803;; +let _X86_INS_VFMADDSUB132PD = 804;; +let _X86_INS_VFMADDSUB132PS = 805;; +let _X86_INS_VFMADDSUBPD = 806;; +let _X86_INS_VFMADDSUB213PD = 807;; +let _X86_INS_VFMADDSUB231PD = 808;; +let _X86_INS_VFMADDSUBPS = 809;; +let _X86_INS_VFMADDSUB213PS = 810;; +let _X86_INS_VFMADDSUB231PS = 811;; +let _X86_INS_VFMSUB132PD = 812;; +let _X86_INS_VFMSUB132PS = 813;; +let _X86_INS_VFMSUBADD132PD = 814;; +let _X86_INS_VFMSUBADD132PS = 815;; +let _X86_INS_VFMSUBADDPD = 816;; +let _X86_INS_VFMSUBADD213PD = 817;; +let _X86_INS_VFMSUBADD231PD = 818;; +let _X86_INS_VFMSUBADDPS = 819;; +let _X86_INS_VFMSUBADD213PS = 820;; +let _X86_INS_VFMSUBADD231PS = 821;; +let _X86_INS_VFMSUBPD = 822;; +let _X86_INS_VFMSUB213PD = 823;; +let _X86_INS_VFMSUB231PD = 824;; +let _X86_INS_VFMSUBPS = 825;; +let _X86_INS_VFMSUB213PS = 826;; +let _X86_INS_VFMSUB231PS = 827;; +let _X86_INS_VFMSUBSD = 828;; +let _X86_INS_VFMSUB213SD = 829;; +let _X86_INS_VFMSUB132SD = 830;; +let _X86_INS_VFMSUB231SD = 831;; +let _X86_INS_VFMSUBSS = 832;; +let _X86_INS_VFMSUB213SS = 833;; +let _X86_INS_VFMSUB132SS = 834;; +let _X86_INS_VFMSUB231SS = 835;; +let _X86_INS_VFNMADD132PD = 836;; +let _X86_INS_VFNMADD132PS = 837;; +let _X86_INS_VFNMADDPD = 838;; +let _X86_INS_VFNMADD213PD = 839;; +let _X86_INS_VFNMADD231PD = 840;; +let _X86_INS_VFNMADDPS = 841;; +let _X86_INS_VFNMADD213PS = 842;; +let _X86_INS_VFNMADD231PS = 843;; +let _X86_INS_VFNMADDSD = 844;; +let _X86_INS_VFNMADD213SD = 845;; +let _X86_INS_VFNMADD132SD = 846;; +let _X86_INS_VFNMADD231SD = 847;; +let _X86_INS_VFNMADDSS = 848;; +let _X86_INS_VFNMADD213SS = 849;; +let _X86_INS_VFNMADD132SS = 850;; +let _X86_INS_VFNMADD231SS = 851;; +let _X86_INS_VFNMSUB132PD = 852;; +let _X86_INS_VFNMSUB132PS = 853;; +let _X86_INS_VFNMSUBPD = 854;; +let _X86_INS_VFNMSUB213PD = 855;; +let _X86_INS_VFNMSUB231PD = 856;; +let _X86_INS_VFNMSUBPS = 857;; +let _X86_INS_VFNMSUB213PS = 858;; +let _X86_INS_VFNMSUB231PS = 859;; +let _X86_INS_VFNMSUBSD = 860;; +let _X86_INS_VFNMSUB213SD = 861;; +let _X86_INS_VFNMSUB132SD = 862;; +let _X86_INS_VFNMSUB231SD = 863;; +let _X86_INS_VFNMSUBSS = 864;; +let _X86_INS_VFNMSUB213SS = 865;; +let _X86_INS_VFNMSUB132SS = 866;; +let _X86_INS_VFNMSUB231SS = 867;; +let _X86_INS_VFRCZPD = 868;; +let _X86_INS_VFRCZPS = 869;; +let _X86_INS_VFRCZSD = 870;; +let _X86_INS_VFRCZSS = 871;; +let _X86_INS_VORPD = 872;; +let _X86_INS_VORPS = 873;; +let _X86_INS_VXORPD = 874;; +let _X86_INS_VXORPS = 875;; +let _X86_INS_VGATHERDPD = 876;; +let _X86_INS_VGATHERDPS = 877;; +let _X86_INS_VGATHERPF0DPD = 878;; +let _X86_INS_VGATHERPF0DPS = 879;; +let _X86_INS_VGATHERPF0QPD = 880;; +let _X86_INS_VGATHERPF0QPS = 881;; +let _X86_INS_VGATHERPF1DPD = 882;; +let _X86_INS_VGATHERPF1DPS = 883;; +let _X86_INS_VGATHERPF1QPD = 884;; +let _X86_INS_VGATHERPF1QPS = 885;; +let _X86_INS_VGATHERQPD = 886;; +let _X86_INS_VGATHERQPS = 887;; +let _X86_INS_VHADDPD = 888;; +let _X86_INS_VHADDPS = 889;; +let _X86_INS_VHSUBPD = 890;; +let _X86_INS_VHSUBPS = 891;; +let _X86_INS_VINSERTF128 = 892;; +let _X86_INS_VINSERTF32X4 = 893;; +let _X86_INS_VINSERTF32X8 = 894;; +let _X86_INS_VINSERTF64X2 = 895;; +let _X86_INS_VINSERTF64X4 = 896;; +let _X86_INS_VINSERTI128 = 897;; +let _X86_INS_VINSERTI32X4 = 898;; +let _X86_INS_VINSERTI32X8 = 899;; +let _X86_INS_VINSERTI64X2 = 900;; +let _X86_INS_VINSERTI64X4 = 901;; +let _X86_INS_VINSERTPS = 902;; +let _X86_INS_VLDDQU = 903;; +let _X86_INS_VLDMXCSR = 904;; +let _X86_INS_VMASKMOVDQU = 905;; +let _X86_INS_VMASKMOVPD = 906;; +let _X86_INS_VMASKMOVPS = 907;; +let _X86_INS_VMAXPD = 908;; +let _X86_INS_VMAXPS = 909;; +let _X86_INS_VMAXSD = 910;; +let _X86_INS_VMAXSS = 911;; +let _X86_INS_VMCALL = 912;; +let _X86_INS_VMCLEAR = 913;; +let _X86_INS_VMFUNC = 914;; +let _X86_INS_VMINPD = 915;; +let _X86_INS_VMINPS = 916;; +let _X86_INS_VMINSD = 917;; +let _X86_INS_VMINSS = 918;; +let _X86_INS_VMLAUNCH = 919;; +let _X86_INS_VMLOAD = 920;; +let _X86_INS_VMMCALL = 921;; +let _X86_INS_VMOVQ = 922;; +let _X86_INS_VMOVDDUP = 923;; +let _X86_INS_VMOVD = 924;; +let _X86_INS_VMOVDQA32 = 925;; +let _X86_INS_VMOVDQA64 = 926;; +let _X86_INS_VMOVDQA = 927;; +let _X86_INS_VMOVDQU16 = 928;; +let _X86_INS_VMOVDQU32 = 929;; +let _X86_INS_VMOVDQU64 = 930;; +let _X86_INS_VMOVDQU8 = 931;; +let _X86_INS_VMOVDQU = 932;; +let _X86_INS_VMOVHLPS = 933;; +let _X86_INS_VMOVHPD = 934;; +let _X86_INS_VMOVHPS = 935;; +let _X86_INS_VMOVLHPS = 936;; +let _X86_INS_VMOVLPD = 937;; +let _X86_INS_VMOVLPS = 938;; +let _X86_INS_VMOVMSKPD = 939;; +let _X86_INS_VMOVMSKPS = 940;; +let _X86_INS_VMOVNTDQA = 941;; +let _X86_INS_VMOVNTDQ = 942;; +let _X86_INS_VMOVNTPD = 943;; +let _X86_INS_VMOVNTPS = 944;; +let _X86_INS_VMOVSD = 945;; +let _X86_INS_VMOVSHDUP = 946;; +let _X86_INS_VMOVSLDUP = 947;; +let _X86_INS_VMOVSS = 948;; +let _X86_INS_VMOVUPD = 949;; +let _X86_INS_VMOVUPS = 950;; +let _X86_INS_VMPSADBW = 951;; +let _X86_INS_VMPTRLD = 952;; +let _X86_INS_VMPTRST = 953;; +let _X86_INS_VMREAD = 954;; +let _X86_INS_VMRESUME = 955;; +let _X86_INS_VMRUN = 956;; +let _X86_INS_VMSAVE = 957;; +let _X86_INS_VMULPD = 958;; +let _X86_INS_VMULPS = 959;; +let _X86_INS_VMULSD = 960;; +let _X86_INS_VMULSS = 961;; +let _X86_INS_VMWRITE = 962;; +let _X86_INS_VMXOFF = 963;; +let _X86_INS_VMXON = 964;; +let _X86_INS_VPABSB = 965;; +let _X86_INS_VPABSD = 966;; +let _X86_INS_VPABSQ = 967;; +let _X86_INS_VPABSW = 968;; +let _X86_INS_VPACKSSDW = 969;; +let _X86_INS_VPACKSSWB = 970;; +let _X86_INS_VPACKUSDW = 971;; +let _X86_INS_VPACKUSWB = 972;; +let _X86_INS_VPADDB = 973;; +let _X86_INS_VPADDD = 974;; +let _X86_INS_VPADDQ = 975;; +let _X86_INS_VPADDSB = 976;; +let _X86_INS_VPADDSW = 977;; +let _X86_INS_VPADDUSB = 978;; +let _X86_INS_VPADDUSW = 979;; +let _X86_INS_VPADDW = 980;; +let _X86_INS_VPALIGNR = 981;; +let _X86_INS_VPANDD = 982;; +let _X86_INS_VPANDND = 983;; +let _X86_INS_VPANDNQ = 984;; +let _X86_INS_VPANDN = 985;; +let _X86_INS_VPANDQ = 986;; +let _X86_INS_VPAND = 987;; +let _X86_INS_VPAVGB = 988;; +let _X86_INS_VPAVGW = 989;; +let _X86_INS_VPBLENDD = 990;; +let _X86_INS_VPBLENDMB = 991;; +let _X86_INS_VPBLENDMD = 992;; +let _X86_INS_VPBLENDMQ = 993;; +let _X86_INS_VPBLENDMW = 994;; +let _X86_INS_VPBLENDVB = 995;; +let _X86_INS_VPBLENDW = 996;; +let _X86_INS_VPBROADCASTB = 997;; +let _X86_INS_VPBROADCASTD = 998;; +let _X86_INS_VPBROADCASTMB2Q = 999;; +let _X86_INS_VPBROADCASTMW2D = 1000;; +let _X86_INS_VPBROADCASTQ = 1001;; +let _X86_INS_VPBROADCASTW = 1002;; +let _X86_INS_VPCLMULQDQ = 1003;; +let _X86_INS_VPCMOV = 1004;; +let _X86_INS_VPCMPB = 1005;; +let _X86_INS_VPCMPD = 1006;; +let _X86_INS_VPCMPEQB = 1007;; +let _X86_INS_VPCMPEQD = 1008;; +let _X86_INS_VPCMPEQQ = 1009;; +let _X86_INS_VPCMPEQW = 1010;; +let _X86_INS_VPCMPESTRI = 1011;; +let _X86_INS_VPCMPESTRM = 1012;; +let _X86_INS_VPCMPGTB = 1013;; +let _X86_INS_VPCMPGTD = 1014;; +let _X86_INS_VPCMPGTQ = 1015;; +let _X86_INS_VPCMPGTW = 1016;; +let _X86_INS_VPCMPISTRI = 1017;; +let _X86_INS_VPCMPISTRM = 1018;; +let _X86_INS_VPCMPQ = 1019;; +let _X86_INS_VPCMPUB = 1020;; +let _X86_INS_VPCMPUD = 1021;; +let _X86_INS_VPCMPUQ = 1022;; +let _X86_INS_VPCMPUW = 1023;; +let _X86_INS_VPCMPW = 1024;; +let _X86_INS_VPCOMB = 1025;; +let _X86_INS_VPCOMD = 1026;; +let _X86_INS_VPCOMPRESSD = 1027;; +let _X86_INS_VPCOMPRESSQ = 1028;; +let _X86_INS_VPCOMQ = 1029;; +let _X86_INS_VPCOMUB = 1030;; +let _X86_INS_VPCOMUD = 1031;; +let _X86_INS_VPCOMUQ = 1032;; +let _X86_INS_VPCOMUW = 1033;; +let _X86_INS_VPCOMW = 1034;; +let _X86_INS_VPCONFLICTD = 1035;; +let _X86_INS_VPCONFLICTQ = 1036;; +let _X86_INS_VPERM2F128 = 1037;; +let _X86_INS_VPERM2I128 = 1038;; +let _X86_INS_VPERMD = 1039;; +let _X86_INS_VPERMI2D = 1040;; +let _X86_INS_VPERMI2PD = 1041;; +let _X86_INS_VPERMI2PS = 1042;; +let _X86_INS_VPERMI2Q = 1043;; +let _X86_INS_VPERMIL2PD = 1044;; +let _X86_INS_VPERMIL2PS = 1045;; +let _X86_INS_VPERMILPD = 1046;; +let _X86_INS_VPERMILPS = 1047;; +let _X86_INS_VPERMPD = 1048;; +let _X86_INS_VPERMPS = 1049;; +let _X86_INS_VPERMQ = 1050;; +let _X86_INS_VPERMT2D = 1051;; +let _X86_INS_VPERMT2PD = 1052;; +let _X86_INS_VPERMT2PS = 1053;; +let _X86_INS_VPERMT2Q = 1054;; +let _X86_INS_VPEXPANDD = 1055;; +let _X86_INS_VPEXPANDQ = 1056;; +let _X86_INS_VPEXTRB = 1057;; +let _X86_INS_VPEXTRD = 1058;; +let _X86_INS_VPEXTRQ = 1059;; +let _X86_INS_VPEXTRW = 1060;; +let _X86_INS_VPGATHERDD = 1061;; +let _X86_INS_VPGATHERDQ = 1062;; +let _X86_INS_VPGATHERQD = 1063;; +let _X86_INS_VPGATHERQQ = 1064;; +let _X86_INS_VPHADDBD = 1065;; +let _X86_INS_VPHADDBQ = 1066;; +let _X86_INS_VPHADDBW = 1067;; +let _X86_INS_VPHADDDQ = 1068;; +let _X86_INS_VPHADDD = 1069;; +let _X86_INS_VPHADDSW = 1070;; +let _X86_INS_VPHADDUBD = 1071;; +let _X86_INS_VPHADDUBQ = 1072;; +let _X86_INS_VPHADDUBW = 1073;; +let _X86_INS_VPHADDUDQ = 1074;; +let _X86_INS_VPHADDUWD = 1075;; +let _X86_INS_VPHADDUWQ = 1076;; +let _X86_INS_VPHADDWD = 1077;; +let _X86_INS_VPHADDWQ = 1078;; +let _X86_INS_VPHADDW = 1079;; +let _X86_INS_VPHMINPOSUW = 1080;; +let _X86_INS_VPHSUBBW = 1081;; +let _X86_INS_VPHSUBDQ = 1082;; +let _X86_INS_VPHSUBD = 1083;; +let _X86_INS_VPHSUBSW = 1084;; +let _X86_INS_VPHSUBWD = 1085;; +let _X86_INS_VPHSUBW = 1086;; +let _X86_INS_VPINSRB = 1087;; +let _X86_INS_VPINSRD = 1088;; +let _X86_INS_VPINSRQ = 1089;; +let _X86_INS_VPINSRW = 1090;; +let _X86_INS_VPLZCNTD = 1091;; +let _X86_INS_VPLZCNTQ = 1092;; +let _X86_INS_VPMACSDD = 1093;; +let _X86_INS_VPMACSDQH = 1094;; +let _X86_INS_VPMACSDQL = 1095;; +let _X86_INS_VPMACSSDD = 1096;; +let _X86_INS_VPMACSSDQH = 1097;; +let _X86_INS_VPMACSSDQL = 1098;; +let _X86_INS_VPMACSSWD = 1099;; +let _X86_INS_VPMACSSWW = 1100;; +let _X86_INS_VPMACSWD = 1101;; +let _X86_INS_VPMACSWW = 1102;; +let _X86_INS_VPMADCSSWD = 1103;; +let _X86_INS_VPMADCSWD = 1104;; +let _X86_INS_VPMADDUBSW = 1105;; +let _X86_INS_VPMADDWD = 1106;; +let _X86_INS_VPMASKMOVD = 1107;; +let _X86_INS_VPMASKMOVQ = 1108;; +let _X86_INS_VPMAXSB = 1109;; +let _X86_INS_VPMAXSD = 1110;; +let _X86_INS_VPMAXSQ = 1111;; +let _X86_INS_VPMAXSW = 1112;; +let _X86_INS_VPMAXUB = 1113;; +let _X86_INS_VPMAXUD = 1114;; +let _X86_INS_VPMAXUQ = 1115;; +let _X86_INS_VPMAXUW = 1116;; +let _X86_INS_VPMINSB = 1117;; +let _X86_INS_VPMINSD = 1118;; +let _X86_INS_VPMINSQ = 1119;; +let _X86_INS_VPMINSW = 1120;; +let _X86_INS_VPMINUB = 1121;; +let _X86_INS_VPMINUD = 1122;; +let _X86_INS_VPMINUQ = 1123;; +let _X86_INS_VPMINUW = 1124;; +let _X86_INS_VPMOVDB = 1125;; +let _X86_INS_VPMOVDW = 1126;; +let _X86_INS_VPMOVM2B = 1127;; +let _X86_INS_VPMOVM2D = 1128;; +let _X86_INS_VPMOVM2Q = 1129;; +let _X86_INS_VPMOVM2W = 1130;; +let _X86_INS_VPMOVMSKB = 1131;; +let _X86_INS_VPMOVQB = 1132;; +let _X86_INS_VPMOVQD = 1133;; +let _X86_INS_VPMOVQW = 1134;; +let _X86_INS_VPMOVSDB = 1135;; +let _X86_INS_VPMOVSDW = 1136;; +let _X86_INS_VPMOVSQB = 1137;; +let _X86_INS_VPMOVSQD = 1138;; +let _X86_INS_VPMOVSQW = 1139;; +let _X86_INS_VPMOVSXBD = 1140;; +let _X86_INS_VPMOVSXBQ = 1141;; +let _X86_INS_VPMOVSXBW = 1142;; +let _X86_INS_VPMOVSXDQ = 1143;; +let _X86_INS_VPMOVSXWD = 1144;; +let _X86_INS_VPMOVSXWQ = 1145;; +let _X86_INS_VPMOVUSDB = 1146;; +let _X86_INS_VPMOVUSDW = 1147;; +let _X86_INS_VPMOVUSQB = 1148;; +let _X86_INS_VPMOVUSQD = 1149;; +let _X86_INS_VPMOVUSQW = 1150;; +let _X86_INS_VPMOVZXBD = 1151;; +let _X86_INS_VPMOVZXBQ = 1152;; +let _X86_INS_VPMOVZXBW = 1153;; +let _X86_INS_VPMOVZXDQ = 1154;; +let _X86_INS_VPMOVZXWD = 1155;; +let _X86_INS_VPMOVZXWQ = 1156;; +let _X86_INS_VPMULDQ = 1157;; +let _X86_INS_VPMULHRSW = 1158;; +let _X86_INS_VPMULHUW = 1159;; +let _X86_INS_VPMULHW = 1160;; +let _X86_INS_VPMULLD = 1161;; +let _X86_INS_VPMULLQ = 1162;; +let _X86_INS_VPMULLW = 1163;; +let _X86_INS_VPMULUDQ = 1164;; +let _X86_INS_VPORD = 1165;; +let _X86_INS_VPORQ = 1166;; +let _X86_INS_VPOR = 1167;; +let _X86_INS_VPPERM = 1168;; +let _X86_INS_VPROTB = 1169;; +let _X86_INS_VPROTD = 1170;; +let _X86_INS_VPROTQ = 1171;; +let _X86_INS_VPROTW = 1172;; +let _X86_INS_VPSADBW = 1173;; +let _X86_INS_VPSCATTERDD = 1174;; +let _X86_INS_VPSCATTERDQ = 1175;; +let _X86_INS_VPSCATTERQD = 1176;; +let _X86_INS_VPSCATTERQQ = 1177;; +let _X86_INS_VPSHAB = 1178;; +let _X86_INS_VPSHAD = 1179;; +let _X86_INS_VPSHAQ = 1180;; +let _X86_INS_VPSHAW = 1181;; +let _X86_INS_VPSHLB = 1182;; +let _X86_INS_VPSHLD = 1183;; +let _X86_INS_VPSHLQ = 1184;; +let _X86_INS_VPSHLW = 1185;; +let _X86_INS_VPSHUFB = 1186;; +let _X86_INS_VPSHUFD = 1187;; +let _X86_INS_VPSHUFHW = 1188;; +let _X86_INS_VPSHUFLW = 1189;; +let _X86_INS_VPSIGNB = 1190;; +let _X86_INS_VPSIGND = 1191;; +let _X86_INS_VPSIGNW = 1192;; +let _X86_INS_VPSLLDQ = 1193;; +let _X86_INS_VPSLLD = 1194;; +let _X86_INS_VPSLLQ = 1195;; +let _X86_INS_VPSLLVD = 1196;; +let _X86_INS_VPSLLVQ = 1197;; +let _X86_INS_VPSLLW = 1198;; +let _X86_INS_VPSRAD = 1199;; +let _X86_INS_VPSRAQ = 1200;; +let _X86_INS_VPSRAVD = 1201;; +let _X86_INS_VPSRAVQ = 1202;; +let _X86_INS_VPSRAW = 1203;; +let _X86_INS_VPSRLDQ = 1204;; +let _X86_INS_VPSRLD = 1205;; +let _X86_INS_VPSRLQ = 1206;; +let _X86_INS_VPSRLVD = 1207;; +let _X86_INS_VPSRLVQ = 1208;; +let _X86_INS_VPSRLW = 1209;; +let _X86_INS_VPSUBB = 1210;; +let _X86_INS_VPSUBD = 1211;; +let _X86_INS_VPSUBQ = 1212;; +let _X86_INS_VPSUBSB = 1213;; +let _X86_INS_VPSUBSW = 1214;; +let _X86_INS_VPSUBUSB = 1215;; +let _X86_INS_VPSUBUSW = 1216;; +let _X86_INS_VPSUBW = 1217;; +let _X86_INS_VPTESTMD = 1218;; +let _X86_INS_VPTESTMQ = 1219;; +let _X86_INS_VPTESTNMD = 1220;; +let _X86_INS_VPTESTNMQ = 1221;; +let _X86_INS_VPTEST = 1222;; +let _X86_INS_VPUNPCKHBW = 1223;; +let _X86_INS_VPUNPCKHDQ = 1224;; +let _X86_INS_VPUNPCKHQDQ = 1225;; +let _X86_INS_VPUNPCKHWD = 1226;; +let _X86_INS_VPUNPCKLBW = 1227;; +let _X86_INS_VPUNPCKLDQ = 1228;; +let _X86_INS_VPUNPCKLQDQ = 1229;; +let _X86_INS_VPUNPCKLWD = 1230;; +let _X86_INS_VPXORD = 1231;; +let _X86_INS_VPXORQ = 1232;; +let _X86_INS_VPXOR = 1233;; +let _X86_INS_VRCP14PD = 1234;; +let _X86_INS_VRCP14PS = 1235;; +let _X86_INS_VRCP14SD = 1236;; +let _X86_INS_VRCP14SS = 1237;; +let _X86_INS_VRCP28PD = 1238;; +let _X86_INS_VRCP28PS = 1239;; +let _X86_INS_VRCP28SD = 1240;; +let _X86_INS_VRCP28SS = 1241;; +let _X86_INS_VRCPPS = 1242;; +let _X86_INS_VRCPSS = 1243;; +let _X86_INS_VRNDSCALEPD = 1244;; +let _X86_INS_VRNDSCALEPS = 1245;; +let _X86_INS_VRNDSCALESD = 1246;; +let _X86_INS_VRNDSCALESS = 1247;; +let _X86_INS_VROUNDPD = 1248;; +let _X86_INS_VROUNDPS = 1249;; +let _X86_INS_VROUNDSD = 1250;; +let _X86_INS_VROUNDSS = 1251;; +let _X86_INS_VRSQRT14PD = 1252;; +let _X86_INS_VRSQRT14PS = 1253;; +let _X86_INS_VRSQRT14SD = 1254;; +let _X86_INS_VRSQRT14SS = 1255;; +let _X86_INS_VRSQRT28PD = 1256;; +let _X86_INS_VRSQRT28PS = 1257;; +let _X86_INS_VRSQRT28SD = 1258;; +let _X86_INS_VRSQRT28SS = 1259;; +let _X86_INS_VRSQRTPS = 1260;; +let _X86_INS_VRSQRTSS = 1261;; +let _X86_INS_VSCATTERDPD = 1262;; +let _X86_INS_VSCATTERDPS = 1263;; +let _X86_INS_VSCATTERPF0DPD = 1264;; +let _X86_INS_VSCATTERPF0DPS = 1265;; +let _X86_INS_VSCATTERPF0QPD = 1266;; +let _X86_INS_VSCATTERPF0QPS = 1267;; +let _X86_INS_VSCATTERPF1DPD = 1268;; +let _X86_INS_VSCATTERPF1DPS = 1269;; +let _X86_INS_VSCATTERPF1QPD = 1270;; +let _X86_INS_VSCATTERPF1QPS = 1271;; +let _X86_INS_VSCATTERQPD = 1272;; +let _X86_INS_VSCATTERQPS = 1273;; +let _X86_INS_VSHUFPD = 1274;; +let _X86_INS_VSHUFPS = 1275;; +let _X86_INS_VSQRTPD = 1276;; +let _X86_INS_VSQRTPS = 1277;; +let _X86_INS_VSQRTSD = 1278;; +let _X86_INS_VSQRTSS = 1279;; +let _X86_INS_VSTMXCSR = 1280;; +let _X86_INS_VSUBPD = 1281;; +let _X86_INS_VSUBPS = 1282;; +let _X86_INS_VSUBSD = 1283;; +let _X86_INS_VSUBSS = 1284;; +let _X86_INS_VTESTPD = 1285;; +let _X86_INS_VTESTPS = 1286;; +let _X86_INS_VUNPCKHPD = 1287;; +let _X86_INS_VUNPCKHPS = 1288;; +let _X86_INS_VUNPCKLPD = 1289;; +let _X86_INS_VUNPCKLPS = 1290;; +let _X86_INS_VZEROALL = 1291;; +let _X86_INS_VZEROUPPER = 1292;; +let _X86_INS_WAIT = 1293;; +let _X86_INS_WBINVD = 1294;; +let _X86_INS_WRFSBASE = 1295;; +let _X86_INS_WRGSBASE = 1296;; +let _X86_INS_WRMSR = 1297;; +let _X86_INS_XABORT = 1298;; +let _X86_INS_XACQUIRE = 1299;; +let _X86_INS_XBEGIN = 1300;; +let _X86_INS_XCHG = 1301;; +let _X86_INS_XCRYPTCBC = 1302;; +let _X86_INS_XCRYPTCFB = 1303;; +let _X86_INS_XCRYPTCTR = 1304;; +let _X86_INS_XCRYPTECB = 1305;; +let _X86_INS_XCRYPTOFB = 1306;; +let _X86_INS_XEND = 1307;; +let _X86_INS_XGETBV = 1308;; +let _X86_INS_XLATB = 1309;; +let _X86_INS_XRELEASE = 1310;; +let _X86_INS_XRSTOR = 1311;; +let _X86_INS_XRSTOR64 = 1312;; +let _X86_INS_XRSTORS = 1313;; +let _X86_INS_XRSTORS64 = 1314;; +let _X86_INS_XSAVE = 1315;; +let _X86_INS_XSAVE64 = 1316;; +let _X86_INS_XSAVEC = 1317;; +let _X86_INS_XSAVEC64 = 1318;; +let _X86_INS_XSAVEOPT = 1319;; +let _X86_INS_XSAVEOPT64 = 1320;; +let _X86_INS_XSAVES = 1321;; +let _X86_INS_XSAVES64 = 1322;; +let _X86_INS_XSETBV = 1323;; +let _X86_INS_XSHA1 = 1324;; +let _X86_INS_XSHA256 = 1325;; +let _X86_INS_XSTORE = 1326;; +let _X86_INS_XTEST = 1327;; +let _X86_INS_FDISI8087_NOP = 1328;; +let _X86_INS_FENI8087_NOP = 1329;; +let _X86_INS_CMPSS = 1330;; +let _X86_INS_CMPEQSS = 1331;; +let _X86_INS_CMPLTSS = 1332;; +let _X86_INS_CMPLESS = 1333;; +let _X86_INS_CMPUNORDSS = 1334;; +let _X86_INS_CMPNEQSS = 1335;; +let _X86_INS_CMPNLTSS = 1336;; +let _X86_INS_CMPNLESS = 1337;; +let _X86_INS_CMPORDSS = 1338;; +let _X86_INS_CMPSD = 1339;; +let _X86_INS_CMPEQSD = 1340;; +let _X86_INS_CMPLTSD = 1341;; +let _X86_INS_CMPLESD = 1342;; +let _X86_INS_CMPUNORDSD = 1343;; +let _X86_INS_CMPNEQSD = 1344;; +let _X86_INS_CMPNLTSD = 1345;; +let _X86_INS_CMPNLESD = 1346;; +let _X86_INS_CMPORDSD = 1347;; +let _X86_INS_CMPPS = 1348;; +let _X86_INS_CMPEQPS = 1349;; +let _X86_INS_CMPLTPS = 1350;; +let _X86_INS_CMPLEPS = 1351;; +let _X86_INS_CMPUNORDPS = 1352;; +let _X86_INS_CMPNEQPS = 1353;; +let _X86_INS_CMPNLTPS = 1354;; +let _X86_INS_CMPNLEPS = 1355;; +let _X86_INS_CMPORDPS = 1356;; +let _X86_INS_CMPPD = 1357;; +let _X86_INS_CMPEQPD = 1358;; +let _X86_INS_CMPLTPD = 1359;; +let _X86_INS_CMPLEPD = 1360;; +let _X86_INS_CMPUNORDPD = 1361;; +let _X86_INS_CMPNEQPD = 1362;; +let _X86_INS_CMPNLTPD = 1363;; +let _X86_INS_CMPNLEPD = 1364;; +let _X86_INS_CMPORDPD = 1365;; +let _X86_INS_VCMPSS = 1366;; +let _X86_INS_VCMPEQSS = 1367;; +let _X86_INS_VCMPLTSS = 1368;; +let _X86_INS_VCMPLESS = 1369;; +let _X86_INS_VCMPUNORDSS = 1370;; +let _X86_INS_VCMPNEQSS = 1371;; +let _X86_INS_VCMPNLTSS = 1372;; +let _X86_INS_VCMPNLESS = 1373;; +let _X86_INS_VCMPORDSS = 1374;; +let _X86_INS_VCMPEQ_UQSS = 1375;; +let _X86_INS_VCMPNGESS = 1376;; +let _X86_INS_VCMPNGTSS = 1377;; +let _X86_INS_VCMPFALSESS = 1378;; +let _X86_INS_VCMPNEQ_OQSS = 1379;; +let _X86_INS_VCMPGESS = 1380;; +let _X86_INS_VCMPGTSS = 1381;; +let _X86_INS_VCMPTRUESS = 1382;; +let _X86_INS_VCMPEQ_OSSS = 1383;; +let _X86_INS_VCMPLT_OQSS = 1384;; +let _X86_INS_VCMPLE_OQSS = 1385;; +let _X86_INS_VCMPUNORD_SSS = 1386;; +let _X86_INS_VCMPNEQ_USSS = 1387;; +let _X86_INS_VCMPNLT_UQSS = 1388;; +let _X86_INS_VCMPNLE_UQSS = 1389;; +let _X86_INS_VCMPORD_SSS = 1390;; +let _X86_INS_VCMPEQ_USSS = 1391;; +let _X86_INS_VCMPNGE_UQSS = 1392;; +let _X86_INS_VCMPNGT_UQSS = 1393;; +let _X86_INS_VCMPFALSE_OSSS = 1394;; +let _X86_INS_VCMPNEQ_OSSS = 1395;; +let _X86_INS_VCMPGE_OQSS = 1396;; +let _X86_INS_VCMPGT_OQSS = 1397;; +let _X86_INS_VCMPTRUE_USSS = 1398;; +let _X86_INS_VCMPSD = 1399;; +let _X86_INS_VCMPEQSD = 1400;; +let _X86_INS_VCMPLTSD = 1401;; +let _X86_INS_VCMPLESD = 1402;; +let _X86_INS_VCMPUNORDSD = 1403;; +let _X86_INS_VCMPNEQSD = 1404;; +let _X86_INS_VCMPNLTSD = 1405;; +let _X86_INS_VCMPNLESD = 1406;; +let _X86_INS_VCMPORDSD = 1407;; +let _X86_INS_VCMPEQ_UQSD = 1408;; +let _X86_INS_VCMPNGESD = 1409;; +let _X86_INS_VCMPNGTSD = 1410;; +let _X86_INS_VCMPFALSESD = 1411;; +let _X86_INS_VCMPNEQ_OQSD = 1412;; +let _X86_INS_VCMPGESD = 1413;; +let _X86_INS_VCMPGTSD = 1414;; +let _X86_INS_VCMPTRUESD = 1415;; +let _X86_INS_VCMPEQ_OSSD = 1416;; +let _X86_INS_VCMPLT_OQSD = 1417;; +let _X86_INS_VCMPLE_OQSD = 1418;; +let _X86_INS_VCMPUNORD_SSD = 1419;; +let _X86_INS_VCMPNEQ_USSD = 1420;; +let _X86_INS_VCMPNLT_UQSD = 1421;; +let _X86_INS_VCMPNLE_UQSD = 1422;; +let _X86_INS_VCMPORD_SSD = 1423;; +let _X86_INS_VCMPEQ_USSD = 1424;; +let _X86_INS_VCMPNGE_UQSD = 1425;; +let _X86_INS_VCMPNGT_UQSD = 1426;; +let _X86_INS_VCMPFALSE_OSSD = 1427;; +let _X86_INS_VCMPNEQ_OSSD = 1428;; +let _X86_INS_VCMPGE_OQSD = 1429;; +let _X86_INS_VCMPGT_OQSD = 1430;; +let _X86_INS_VCMPTRUE_USSD = 1431;; +let _X86_INS_VCMPPS = 1432;; +let _X86_INS_VCMPEQPS = 1433;; +let _X86_INS_VCMPLTPS = 1434;; +let _X86_INS_VCMPLEPS = 1435;; +let _X86_INS_VCMPUNORDPS = 1436;; +let _X86_INS_VCMPNEQPS = 1437;; +let _X86_INS_VCMPNLTPS = 1438;; +let _X86_INS_VCMPNLEPS = 1439;; +let _X86_INS_VCMPORDPS = 1440;; +let _X86_INS_VCMPEQ_UQPS = 1441;; +let _X86_INS_VCMPNGEPS = 1442;; +let _X86_INS_VCMPNGTPS = 1443;; +let _X86_INS_VCMPFALSEPS = 1444;; +let _X86_INS_VCMPNEQ_OQPS = 1445;; +let _X86_INS_VCMPGEPS = 1446;; +let _X86_INS_VCMPGTPS = 1447;; +let _X86_INS_VCMPTRUEPS = 1448;; +let _X86_INS_VCMPEQ_OSPS = 1449;; +let _X86_INS_VCMPLT_OQPS = 1450;; +let _X86_INS_VCMPLE_OQPS = 1451;; +let _X86_INS_VCMPUNORD_SPS = 1452;; +let _X86_INS_VCMPNEQ_USPS = 1453;; +let _X86_INS_VCMPNLT_UQPS = 1454;; +let _X86_INS_VCMPNLE_UQPS = 1455;; +let _X86_INS_VCMPORD_SPS = 1456;; +let _X86_INS_VCMPEQ_USPS = 1457;; +let _X86_INS_VCMPNGE_UQPS = 1458;; +let _X86_INS_VCMPNGT_UQPS = 1459;; +let _X86_INS_VCMPFALSE_OSPS = 1460;; +let _X86_INS_VCMPNEQ_OSPS = 1461;; +let _X86_INS_VCMPGE_OQPS = 1462;; +let _X86_INS_VCMPGT_OQPS = 1463;; +let _X86_INS_VCMPTRUE_USPS = 1464;; +let _X86_INS_VCMPPD = 1465;; +let _X86_INS_VCMPEQPD = 1466;; +let _X86_INS_VCMPLTPD = 1467;; +let _X86_INS_VCMPLEPD = 1468;; +let _X86_INS_VCMPUNORDPD = 1469;; +let _X86_INS_VCMPNEQPD = 1470;; +let _X86_INS_VCMPNLTPD = 1471;; +let _X86_INS_VCMPNLEPD = 1472;; +let _X86_INS_VCMPORDPD = 1473;; +let _X86_INS_VCMPEQ_UQPD = 1474;; +let _X86_INS_VCMPNGEPD = 1475;; +let _X86_INS_VCMPNGTPD = 1476;; +let _X86_INS_VCMPFALSEPD = 1477;; +let _X86_INS_VCMPNEQ_OQPD = 1478;; +let _X86_INS_VCMPGEPD = 1479;; +let _X86_INS_VCMPGTPD = 1480;; +let _X86_INS_VCMPTRUEPD = 1481;; +let _X86_INS_VCMPEQ_OSPD = 1482;; +let _X86_INS_VCMPLT_OQPD = 1483;; +let _X86_INS_VCMPLE_OQPD = 1484;; +let _X86_INS_VCMPUNORD_SPD = 1485;; +let _X86_INS_VCMPNEQ_USPD = 1486;; +let _X86_INS_VCMPNLT_UQPD = 1487;; +let _X86_INS_VCMPNLE_UQPD = 1488;; +let _X86_INS_VCMPORD_SPD = 1489;; +let _X86_INS_VCMPEQ_USPD = 1490;; +let _X86_INS_VCMPNGE_UQPD = 1491;; +let _X86_INS_VCMPNGT_UQPD = 1492;; +let _X86_INS_VCMPFALSE_OSPD = 1493;; +let _X86_INS_VCMPNEQ_OSPD = 1494;; +let _X86_INS_VCMPGE_OQPD = 1495;; +let _X86_INS_VCMPGT_OQPD = 1496;; +let _X86_INS_VCMPTRUE_USPD = 1497;; +let _X86_INS_UD0 = 1498;; +let _X86_INS_ENDBR32 = 1499;; +let _X86_INS_ENDBR64 = 1500;; +let _X86_INS_ENDING = 1501;; + +let _X86_GRP_INVALID = 0;; +let _X86_GRP_JUMP = 1;; +let _X86_GRP_CALL = 2;; +let _X86_GRP_RET = 3;; +let _X86_GRP_INT = 4;; +let _X86_GRP_IRET = 5;; +let _X86_GRP_PRIVILEGE = 6;; +let _X86_GRP_BRANCH_RELATIVE = 7;; +let _X86_GRP_VM = 128;; +let _X86_GRP_3DNOW = 129;; +let _X86_GRP_AES = 130;; +let _X86_GRP_ADX = 131;; +let _X86_GRP_AVX = 132;; +let _X86_GRP_AVX2 = 133;; +let _X86_GRP_AVX512 = 134;; +let _X86_GRP_BMI = 135;; +let _X86_GRP_BMI2 = 136;; +let _X86_GRP_CMOV = 137;; +let _X86_GRP_F16C = 138;; +let _X86_GRP_FMA = 139;; +let _X86_GRP_FMA4 = 140;; +let _X86_GRP_FSGSBASE = 141;; +let _X86_GRP_HLE = 142;; +let _X86_GRP_MMX = 143;; +let _X86_GRP_MODE32 = 144;; +let _X86_GRP_MODE64 = 145;; +let _X86_GRP_RTM = 146;; +let _X86_GRP_SHA = 147;; +let _X86_GRP_SSE1 = 148;; +let _X86_GRP_SSE2 = 149;; +let _X86_GRP_SSE3 = 150;; +let _X86_GRP_SSE41 = 151;; +let _X86_GRP_SSE42 = 152;; +let _X86_GRP_SSE4A = 153;; +let _X86_GRP_SSSE3 = 154;; +let _X86_GRP_PCLMUL = 155;; +let _X86_GRP_XOP = 156;; +let _X86_GRP_CDI = 157;; +let _X86_GRP_ERI = 158;; +let _X86_GRP_TBM = 159;; +let _X86_GRP_16BITMODE = 160;; +let _X86_GRP_NOT64BITMODE = 161;; +let _X86_GRP_SGX = 162;; +let _X86_GRP_DQI = 163;; +let _X86_GRP_BWI = 164;; +let _X86_GRP_PFI = 165;; +let _X86_GRP_VLX = 166;; +let _X86_GRP_SMAP = 167;; +let _X86_GRP_NOVLX = 168;; +let _X86_GRP_FPU = 169;; +let _X86_GRP_ENDING = 170;; diff --git a/white_patch_detect/capstone-master/bindings/ocaml/xcore.ml b/white_patch_detect/capstone-master/bindings/ocaml/xcore.ml new file mode 100644 index 0000000..ee993c1 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/xcore.ml @@ -0,0 +1,26 @@ +(* Capstone Disassembly Engine + * By Guillaume Jeanne , 2014> *) + +open Xcore_const + +type xcore_op_mem = { + base: int; + index: int; + disp: int; + direct: int; +} + +type xcore_op_value = + | XCORE_OP_INVALID of int + | XCORE_OP_REG of int + | XCORE_OP_IMM of int + | XCORE_OP_MEM of xcore_op_mem + +type xcore_op = { + value: xcore_op_value; +} + +type cs_xcore = { + operands: xcore_op array; +} + diff --git a/white_patch_detect/capstone-master/bindings/ocaml/xcore_const.ml b/white_patch_detect/capstone-master/bindings/ocaml/xcore_const.ml new file mode 100644 index 0000000..f32dd4a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/ocaml/xcore_const.ml @@ -0,0 +1,161 @@ +(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.ml] *) + +let _XCORE_OP_INVALID = 0;; +let _XCORE_OP_REG = 1;; +let _XCORE_OP_IMM = 2;; +let _XCORE_OP_MEM = 3;; + +let _XCORE_REG_INVALID = 0;; +let _XCORE_REG_CP = 1;; +let _XCORE_REG_DP = 2;; +let _XCORE_REG_LR = 3;; +let _XCORE_REG_SP = 4;; +let _XCORE_REG_R0 = 5;; +let _XCORE_REG_R1 = 6;; +let _XCORE_REG_R2 = 7;; +let _XCORE_REG_R3 = 8;; +let _XCORE_REG_R4 = 9;; +let _XCORE_REG_R5 = 10;; +let _XCORE_REG_R6 = 11;; +let _XCORE_REG_R7 = 12;; +let _XCORE_REG_R8 = 13;; +let _XCORE_REG_R9 = 14;; +let _XCORE_REG_R10 = 15;; +let _XCORE_REG_R11 = 16;; +let _XCORE_REG_PC = 17;; +let _XCORE_REG_SCP = 18;; +let _XCORE_REG_SSR = 19;; +let _XCORE_REG_ET = 20;; +let _XCORE_REG_ED = 21;; +let _XCORE_REG_SED = 22;; +let _XCORE_REG_KEP = 23;; +let _XCORE_REG_KSP = 24;; +let _XCORE_REG_ID = 25;; +let _XCORE_REG_ENDING = 26;; + +let _XCORE_INS_INVALID = 0;; +let _XCORE_INS_ADD = 1;; +let _XCORE_INS_ANDNOT = 2;; +let _XCORE_INS_AND = 3;; +let _XCORE_INS_ASHR = 4;; +let _XCORE_INS_BAU = 5;; +let _XCORE_INS_BITREV = 6;; +let _XCORE_INS_BLA = 7;; +let _XCORE_INS_BLAT = 8;; +let _XCORE_INS_BL = 9;; +let _XCORE_INS_BF = 10;; +let _XCORE_INS_BT = 11;; +let _XCORE_INS_BU = 12;; +let _XCORE_INS_BRU = 13;; +let _XCORE_INS_BYTEREV = 14;; +let _XCORE_INS_CHKCT = 15;; +let _XCORE_INS_CLRE = 16;; +let _XCORE_INS_CLRPT = 17;; +let _XCORE_INS_CLRSR = 18;; +let _XCORE_INS_CLZ = 19;; +let _XCORE_INS_CRC8 = 20;; +let _XCORE_INS_CRC32 = 21;; +let _XCORE_INS_DCALL = 22;; +let _XCORE_INS_DENTSP = 23;; +let _XCORE_INS_DGETREG = 24;; +let _XCORE_INS_DIVS = 25;; +let _XCORE_INS_DIVU = 26;; +let _XCORE_INS_DRESTSP = 27;; +let _XCORE_INS_DRET = 28;; +let _XCORE_INS_ECALLF = 29;; +let _XCORE_INS_ECALLT = 30;; +let _XCORE_INS_EDU = 31;; +let _XCORE_INS_EEF = 32;; +let _XCORE_INS_EET = 33;; +let _XCORE_INS_EEU = 34;; +let _XCORE_INS_ENDIN = 35;; +let _XCORE_INS_ENTSP = 36;; +let _XCORE_INS_EQ = 37;; +let _XCORE_INS_EXTDP = 38;; +let _XCORE_INS_EXTSP = 39;; +let _XCORE_INS_FREER = 40;; +let _XCORE_INS_FREET = 41;; +let _XCORE_INS_GETD = 42;; +let _XCORE_INS_GET = 43;; +let _XCORE_INS_GETN = 44;; +let _XCORE_INS_GETR = 45;; +let _XCORE_INS_GETSR = 46;; +let _XCORE_INS_GETST = 47;; +let _XCORE_INS_GETTS = 48;; +let _XCORE_INS_INCT = 49;; +let _XCORE_INS_INIT = 50;; +let _XCORE_INS_INPW = 51;; +let _XCORE_INS_INSHR = 52;; +let _XCORE_INS_INT = 53;; +let _XCORE_INS_IN = 54;; +let _XCORE_INS_KCALL = 55;; +let _XCORE_INS_KENTSP = 56;; +let _XCORE_INS_KRESTSP = 57;; +let _XCORE_INS_KRET = 58;; +let _XCORE_INS_LADD = 59;; +let _XCORE_INS_LD16S = 60;; +let _XCORE_INS_LD8U = 61;; +let _XCORE_INS_LDA16 = 62;; +let _XCORE_INS_LDAP = 63;; +let _XCORE_INS_LDAW = 64;; +let _XCORE_INS_LDC = 65;; +let _XCORE_INS_LDW = 66;; +let _XCORE_INS_LDIVU = 67;; +let _XCORE_INS_LMUL = 68;; +let _XCORE_INS_LSS = 69;; +let _XCORE_INS_LSUB = 70;; +let _XCORE_INS_LSU = 71;; +let _XCORE_INS_MACCS = 72;; +let _XCORE_INS_MACCU = 73;; +let _XCORE_INS_MJOIN = 74;; +let _XCORE_INS_MKMSK = 75;; +let _XCORE_INS_MSYNC = 76;; +let _XCORE_INS_MUL = 77;; +let _XCORE_INS_NEG = 78;; +let _XCORE_INS_NOT = 79;; +let _XCORE_INS_OR = 80;; +let _XCORE_INS_OUTCT = 81;; +let _XCORE_INS_OUTPW = 82;; +let _XCORE_INS_OUTSHR = 83;; +let _XCORE_INS_OUTT = 84;; +let _XCORE_INS_OUT = 85;; +let _XCORE_INS_PEEK = 86;; +let _XCORE_INS_REMS = 87;; +let _XCORE_INS_REMU = 88;; +let _XCORE_INS_RETSP = 89;; +let _XCORE_INS_SETCLK = 90;; +let _XCORE_INS_SET = 91;; +let _XCORE_INS_SETC = 92;; +let _XCORE_INS_SETD = 93;; +let _XCORE_INS_SETEV = 94;; +let _XCORE_INS_SETN = 95;; +let _XCORE_INS_SETPSC = 96;; +let _XCORE_INS_SETPT = 97;; +let _XCORE_INS_SETRDY = 98;; +let _XCORE_INS_SETSR = 99;; +let _XCORE_INS_SETTW = 100;; +let _XCORE_INS_SETV = 101;; +let _XCORE_INS_SEXT = 102;; +let _XCORE_INS_SHL = 103;; +let _XCORE_INS_SHR = 104;; +let _XCORE_INS_SSYNC = 105;; +let _XCORE_INS_ST16 = 106;; +let _XCORE_INS_ST8 = 107;; +let _XCORE_INS_STW = 108;; +let _XCORE_INS_SUB = 109;; +let _XCORE_INS_SYNCR = 110;; +let _XCORE_INS_TESTCT = 111;; +let _XCORE_INS_TESTLCL = 112;; +let _XCORE_INS_TESTWCT = 113;; +let _XCORE_INS_TSETMR = 114;; +let _XCORE_INS_START = 115;; +let _XCORE_INS_WAITEF = 116;; +let _XCORE_INS_WAITET = 117;; +let _XCORE_INS_WAITEU = 118;; +let _XCORE_INS_XOR = 119;; +let _XCORE_INS_ZEXT = 120;; +let _XCORE_INS_ENDING = 121;; + +let _XCORE_GRP_INVALID = 0;; +let _XCORE_GRP_JUMP = 1;; +let _XCORE_GRP_ENDING = 2;; diff --git a/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.Format.ps1xml b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.Format.ps1xml new file mode 100644 index 0000000..3fd430f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.Format.ps1xml @@ -0,0 +1,157 @@ + + + + + + Both + + + + + + CapstoneDisassemblyViewSimple + + CapstoneDisassembly.Simple + + + + + + + Address + 0x{0:X} + + + Instruction + + + + + + + + CapstoneDisassemblyViewSimple + + CapstoneDisassembly.Simple + + + + + + + + + + + + + + + Address + 0x{0:x} + + + Instruction + + + + + + + + CapstoneDisassemblyViewDetailed + + CapstoneDisassembly.Detailed + + + + + + + Address + 0x{0:X} + + + Mnemonic + + + Operands + + + Bytes + + + Size + + + RegRead + + + RegWrite + + + + + + + + CapstoneDisassemblyViewDetailed + + CapstoneDisassembly.Detailed + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Address + 0x{0:x} + + + Mnemonic + + + Operands + + + Bytes + + + Size + + + RegRead + + + RegWrite + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psd1 b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psd1 new file mode 100644 index 0000000..fad45ca --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psd1 @@ -0,0 +1,118 @@ +# +# Module manifest for module 'Capstone' +# + +@{ + +# Script module or binary module file associated with this manifest. +ModuleToProcess = 'Capstone.psm1' + +# Version number of this module. +ModuleVersion = '0.0.0.2' + +# Supported PSEditions +# CompatiblePSEditions = @() + +# ID used to uniquely identify this module +GUID = 'd34db33f-9958-436d-a2d8-a77844a2bda5' + +# Author of this module +Author = 'Ruben Boonen, beatcracker' + +# Company or vendor of this module +# CompanyName = 'Unknown' + +# Copyright statement for this module +Copyright = 'BSD 3-Clause' + +# Description of the functionality provided by this module +Description = 'Capstone Engine Binding Module' + +# Minimum version of the Windows PowerShell engine required by this module +PowerShellVersion = '2.0' + +# Name of the Windows PowerShell host required by this module +# PowerShellHostName = '' + +# Minimum version of the Windows PowerShell host required by this module +# PowerShellHostVersion = '' + +# Minimum version of Microsoft .NET Framework required by this module. This prerequisite is valid for the PowerShell Desktop edition only. +# DotNetFrameworkVersion = '' + +# Minimum version of the common language runtime (CLR) required by this module. This prerequisite is valid for the PowerShell Desktop edition only. +# CLRVersion = '' + +# Processor architecture (None, X86, Amd64) required by this module +# ProcessorArchitecture = '' + +# Modules that must be imported into the global environment prior to importing this module +# RequiredModules = @() + +# Assemblies that must be loaded prior to importing this module +# RequiredAssemblies = @() + +# Script files (.ps1) that are run in the caller's environment prior to importing this module. +# ScriptsToProcess = @() + +# Type files (.ps1xml) to be loaded when importing this module +# TypesToProcess = @() + +# Format files (.ps1xml) to be loaded when importing this module +FormatsToProcess = 'Capstone.Format.ps1xml' + +# Modules to import as nested modules of the module specified in RootModule/ModuleToProcess +# NestedModules = @() + +# Functions to export from this module, for best performance, do not use wildcards and do not delete the entry, use an empty array if there are no functions to export. +FunctionsToExport = 'Get-CapstoneVersion', 'Get-CapstoneDisassembly' + +# Cmdlets to export from this module, for best performance, do not use wildcards and do not delete the entry, use an empty array if there are no cmdlets to export. +CmdletsToExport = @() + +# Variables to export from this module +VariablesToExport = @() + +# Aliases to export from this module, for best performance, do not use wildcards and do not delete the entry, use an empty array if there are no aliases to export. +AliasesToExport = @() + +# DSC resources to export from this module +# DscResourcesToExport = @() + +# List of all modules packaged with this module +# ModuleList = @() + +# List of all files packaged with this module +# FileList = @() + +# Private data to pass to the module specified in RootModule/ModuleToProcess. This may also contain a PSData hashtable with additional module metadata used by PowerShell. +PrivateData = @{ + + PSData = @{ + + # Tags applied to this module. These help with module discovery in online galleries. + # Tags = @() + + # A URL to the license for this module. + # LicenseUri = '' + + # A URL to the main website for this project. + # ProjectUri = '' + + # A URL to an icon representing this module. + # IconUri = '' + + # ReleaseNotes of this module + # ReleaseNotes = '' + + } # End of PSData hashtable + +} # End of PrivateData hashtable + +# HelpInfo URI of this module +# HelpInfoURI = '' + +# Default prefix for commands exported from this module. Override the default prefix using Import-Module -Prefix. +# DefaultCommandPrefix = '' + +} \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psm1 b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psm1 new file mode 100644 index 0000000..ba50143 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Capstone.psm1 @@ -0,0 +1,500 @@ +<# +.SYNOPSIS + Get Capstone version as Version object +#> +function Get-CapstoneVersion { + $Version = [System.BitConverter]::GetBytes( + [Capstone]::cs_version($null, $null) + ) + + New-Object -TypeName version -ArgumentList @( + $Version[1] + $Version[0] + 0 + 0 + ) +} + +<# +.SYNOPSIS + Create C# bindings for capstone.dll + +.PARAMETER DllPath + Path to capstone.dll +#> +function Initialize-Capstone { + [CmdletBinding()] + Param ( + [Parameter(Mandatory = $true)] + [ValidateScript( { + try { + Test-Path -Path $_ -PathType Leaf -ErrorAction Stop + } catch { + throw "Capstone DLL is missing: $DllPath" + } + })] + [ValidateNotNullOrEmpty()] + [string]$DllPath + ) + + # Escape path for use in inline C# + $DllPath = $DllPath.Replace('\', '\\') + + # Inline C# to parse the unmanaged capstone DLL + # http://stackoverflow.com/questions/16552801/how-do-i-conditionally-add-a-class-with-add-type-typedefinition-if-it-isnt-add + if (-not ([System.Management.Automation.PSTypeName]'Capstone').Type) { + Add-Type -TypeDefinition @" + using System; + using System.Diagnostics; + using System.Runtime.InteropServices; + using System.Security.Principal; + + [StructLayout(LayoutKind.Sequential)] + public struct cs_insn + { + public uint id; + public ulong address; + public ushort size; + [MarshalAs(UnmanagedType.ByValArray, SizeConst = 24)] + public byte[] bytes; + [MarshalAs(UnmanagedType.ByValTStr, SizeConst = 32)] + public string mnemonic; + [MarshalAs(UnmanagedType.ByValTStr, SizeConst = 160)] + public string operands; + public IntPtr detail; + } + + /// Partial, only architecture-independent internal data + [StructLayout(LayoutKind.Sequential)] + public struct cs_detail + { + [MarshalAs(UnmanagedType.ByValArray, SizeConst = 16)] + public byte[] regs_read; + public byte regs_read_count; + [MarshalAs(UnmanagedType.ByValArray, SizeConst = 20)] + public byte[] regs_write; + public byte regs_write_count; + [MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)] + public byte[] groups; + public byte groups_count; + } + + public enum cs_err : int + { + CS_ERR_OK = 0, /// No error: everything was fine + CS_ERR_MEM, /// Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter() + CS_ERR_ARCH, /// Unsupported architecture: cs_open() + CS_ERR_HANDLE, /// Invalid handle: cs_op_count(), cs_op_index() + CS_ERR_CSH, /// Invalid csh argument: cs_close(), cs_errno(), cs_option() + CS_ERR_MODE, /// Invalid/unsupported mode: cs_open() + CS_ERR_OPTION, /// Invalid/unsupported option: cs_option() + CS_ERR_DETAIL, /// Information is unavailable because detail option is OFF + CS_ERR_MEMSETUP, /// Dynamic memory management uninitialized (see CS_OPT_MEM) + CS_ERR_VERSION, /// Unsupported version (bindings) + CS_ERR_DIET, /// Access irrelevant data in "diet" engine + CS_ERR_SKIPDATA, /// Access irrelevant data for "data" instruction in SKIPDATA mode + CS_ERR_X86_ATT, /// X86 AT&T syntax is unsupported (opt-out at compile time) + CS_ERR_X86_INTEL, /// X86 Intel syntax is unsupported (opt-out at compile time) + } + public enum cs_arch : int + { + CS_ARCH_ARM = 0, /// ARM architecture (including Thumb, Thumb-2) + CS_ARCH_ARM64, /// ARM-64, also called AArch64 + CS_ARCH_MIPS, /// Mips architecture + CS_ARCH_X86, /// X86 architecture (including x86 & x86-64) + CS_ARCH_PPC, /// PowerPC architecture + CS_ARCH_SPARC, /// Sparc architecture + CS_ARCH_SYSZ, /// SystemZ architecture + CS_ARCH_XCORE, /// XCore architecture + CS_ARCH_MAX, + CS_ARCH_ALL = 0xFFFF, /// All architectures - for cs_support() + } + public enum cs_mode : int + { + CS_MODE_LITTLE_ENDIAN = 0, /// little-endian mode (default mode) + CS_MODE_ARM = 0, /// 32-bit ARM + CS_MODE_16 = 1 << 1, /// 16-bit mode (X86) + CS_MODE_32 = 1 << 2, /// 32-bit mode (X86) + CS_MODE_64 = 1 << 3, /// 64-bit mode (X86, PPC) + CS_MODE_THUMB = 1 << 4, /// ARM's Thumb mode, including Thumb-2 + CS_MODE_MCLASS = 1 << 5, /// ARM's Cortex-M series + CS_MODE_V8 = 1 << 6, /// ARMv8 A32 encodings for ARM + CS_MODE_MICRO = 1 << 4, /// MicroMips mode (MIPS) + CS_MODE_MIPS3 = 1 << 5, /// Mips III ISA + CS_MODE_MIPS32R6 = 1 << 6, /// Mips32r6 ISA + CS_MODE_MIPSGP64 = 1 << 7, /// General Purpose Registers are 64-bit wide (MIPS) + CS_MODE_V9 = 1 << 4, /// SparcV9 mode (Sparc) + CS_MODE_BIG_ENDIAN = 1 << 31, /// big-endian mode + CS_MODE_MIPS32 = CS_MODE_32, /// Mips32 ISA (Mips) + CS_MODE_MIPS64 = CS_MODE_64, /// Mips64 ISA (Mips) + } + + public static class Capstone + { + [DllImport("$DllPath")] + public static extern cs_err cs_open( + cs_arch arch, + cs_mode mode, + ref IntPtr handle); + + [DllImport("$DllPath")] + public static extern UInt32 cs_disasm( + IntPtr handle, + byte[] code, + int code_size, + ulong address, + int count, + ref IntPtr insn); + + [DllImport("$DllPath")] + public static extern bool cs_free( + IntPtr insn, + int count); + + [DllImport("$DllPath")] + public static extern cs_err cs_close( + ref IntPtr handle); + + [DllImport("$DllPath")] + public static extern cs_err cs_option( + IntPtr handle, + int type, + int value); + + [DllImport("$DllPath", CallingConvention = CallingConvention.Cdecl)] + public static extern IntPtr cs_reg_name( + IntPtr handle, + uint reg_id); + + [DllImport("$DllPath")] + public static extern int cs_version( + uint major, + uint minor); + } +"@ + } else { + Write-Verbose 'C# bindings are already compiled' + } +} + +function Get-CapstoneDisassembly { +<# +.SYNOPSIS + Powershell wrapper for Capstone (using inline C#). + +.DESCRIPTION + Author: Ruben Boonen (@FuzzySec), @beatcracker + License: BSD 3-Clause + Required Dependencies: None + Optional Dependencies: None + +.PARAMETER Architecture + Architecture type. + +.PARAMETER Mode + Mode type. + +.PARAMETER Bytes + Byte array to be disassembled. + +.PARAMETER Syntax + Syntax for output assembly. + +.PARAMETER Address + Assign address for the first instruction to be disassembled. + +.PARAMETER Detailed + Return detailed output. + +.PARAMETER Version + Print ASCII version banner. + +.EXAMPLE + + C:\PS> $Bytes = [byte[]] @( 0x10, 0xf1, 0x10, 0xe7, 0x11, 0xf2, 0x31, 0xe7, 0xdc, 0xa1, 0x2e, 0xf3, 0xe8, 0x4e, 0x62, 0xf3 ) + C:\PS> Get-CapstoneDisassembly -Architecture CS_ARCH_ARM -Mode CS_MODE_ARM -Bytes $Bytes + + Address : 0x100000 + Instruction : sdiv r0, r0, r1 + + Address : 0x100004 + Instruction : udiv r1, r1, r2 + + Address : 0x100008 + Instruction : vbit q5, q15, q6 + + Address : 0x10000C + Instruction : vcgt.f32 q10, q9, q12 + +.EXAMPLE + + # Detailed mode & ATT syntax + C:\PS> $Bytes = [byte[]] @( 0xB8, 0x0A, 0x00, 0x00, 0x00, 0xF7, 0xF3 ) + C:\PS> Get-CapstoneDisassembly -Architecture CS_ARCH_X86 -Mode CS_MODE_32 -Bytes $Bytes -Syntax ATT -Detailed + + Address : 0x100000 + Mnemonic : movl + Operands : $0xa, %eax + Bytes : {184, 10, 0, 0...} + Size : 5 + RegRead : + RegWrite : + + Address : 0x100005 + Mnemonic : divl + Operands : %ebx + Bytes : {247, 243} + Size : 2 + RegRead : {eax, edx} + RegWrite : {eax, edx, eflags} + +.EXAMPLE + + # Get-CapstoneDisassembly emits objects + C:\PS> $Bytes = [byte[]] @( 0xB8, 0x0A, 0x00, 0x00, 0x00, 0xF7, 0xF3 ) + C:\PS> $Object = Get-CapstoneDisassembly -Architecture CS_ARCH_X86 -Mode CS_MODE_32 -Bytes $Bytes -Detailed + C:\PS> $Object | Select-Object -Property Size, Mnemonic, Operands + + Size Mnemonic Operands + ---- -------- -------- + 5 mov eax, 0xa + 2 div ebx +#> + [CmdletBinding(DefaultParameterSetName = 'Capstone')] + Param ( + [Parameter(ParameterSetName = 'Capstone', Mandatory = $true)] + [ValidateSet( + 'CS_ARCH_ARM', + 'CS_ARCH_ARM64', + 'CS_ARCH_MIPS', + 'CS_ARCH_X86', + 'CS_ARCH_PPC', + 'CS_ARCH_SPARC', + 'CS_ARCH_SYSZ', + 'CS_ARCH_XCORE', + 'CS_ARCH_MAX', + 'CS_ARCH_ALL' + )] + [string]$Architecture, + + [Parameter(ParameterSetName = 'Capstone', Mandatory = $true)] + [ValidateSet( + 'CS_MODE_LITTLE_ENDIAN', + 'CS_MODE_ARM', + 'CS_MODE_16', + 'CS_MODE_32', + 'CS_MODE_64', + 'CS_MODE_THUMB', + 'CS_MODE_MCLASS', + 'CS_MODE_V8', + 'CS_MODE_MICRO', + 'CS_MODE_MIPS3', + 'CS_MODE_MIPS32R6', + 'CS_MODE_MIPSGP64', + 'CS_MODE_V9', + 'CS_MODE_BIG_ENDIAN', + 'CS_MODE_MIPS32', + 'CS_MODE_MIPS64' + )] + [string]$Mode, + + [Parameter(ParameterSetName = 'Capstone', Mandatory = $true)] + [ValidateNotNullOrEmpty()] + [byte[]]$Bytes, + + [Parameter(ParameterSetName = 'Capstone')] + [ValidateSet( + 'Intel', + 'ATT' + )] + [string]$Syntax = 'Intel', + + [Parameter(ParameterSetName = 'Capstone')] + [uint64]$Address = 0x100000, + + [Parameter(ParameterSetName = 'Capstone')] + [switch]$Detailed, + + [Parameter(ParameterSetName = 'Version')] + [switch]$Version + ) + + if ($Version) { + $Banner = @' + + (((; + (; "((((\ + ;((((((; "((((; + ((((""\(((( "(((( + ((((" ((\ "(((( "(((\ + ;(((/ ((((((( "(((( \((( + ((((" (((* "(((( \(((;"(((\ + ((((";((("/(( \(((;"(((\"(((\ + (((( (((( ((((" "(((\ ((() (((\ + ;((("(((( (((* **"" ((()"(((; + (((" ((( (((( ((((((((((((((:*((( + (((( (((*)((( ********"""" ;;(((((; + (((* ((( (((((((((((((((((((((*"" ( + ((("(((( """***********"""" ;;((((( + "" (((((((((((((((((((((((((((*"" + """****(((((****""" + + -=[Capstone Engine v{0}]=- + +'@ -f (Get-CapstoneVersion).ToString(2) + # Mmm ASCII version banner! + return $Banner + } + + # Disasm Handle + $DisAsmHandle = [System.IntPtr]::Zero + + # Initialize Capstone with cs_open() + $CallResult = [Capstone]::cs_open($Architecture, $Mode, [ref]$DisAsmHandle) + if ($CallResult -ne 'CS_ERR_OK') { + if ($CallResult -eq 'CS_ERR_MODE') { + throw "Invalid Architecture/Mode combination: $Architecture/$Mode" + } else { + throw "cs_open error: $CallResult" + } + } + + # Set disassembly syntax + #--- + # cs_opt_type -> CS_OPT_SYNTAX = 1 + #--- + # cs_opt_value -> CS_OPT_SYNTAX_INTEL = 1 + # -> CS_OPT_SYNTAX_ATT = 2 + if ($Syntax -eq 'Intel') { + $CS_OPT_SYNTAX = 1 + } else { + $CS_OPT_SYNTAX = 2 + } + + $CallResult = [Capstone]::cs_option($DisAsmHandle, 1, $CS_OPT_SYNTAX) + if ($CallResult -ne 'CS_ERR_OK') { + $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle) + throw "cs_option error: $CallResult" + } + + # Set disassembly detail + #--- + # cs_opt_type -> CS_OPT_DETAIL = 2 + #--- + # cs_opt_value -> CS_OPT_ON = 3 + # -> CS_OPT_OFF = 0 + if ($Detailed) { + $CS_OPT = 3 + } else { + $CS_OPT = 0 + } + + $CallResult = [Capstone]::cs_option($DisAsmHandle, 2, $CS_OPT) + if ($CallResult -ne 'CS_ERR_OK') { + $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle) + throw "cs_option error: $CallResult" + } + + # Out Buffer Handle + $InsnHandle = [System.IntPtr]::Zero + + # Disassemble bytes + $Count = [Capstone]::cs_disasm($DisAsmHandle, $Bytes, $Bytes.Count, $Address, 0, [ref]$InsnHandle) + + if ($Count -gt 0) { + # Result struct + $cs_insn = if ($PSVersionTable.PSVersion.Major -gt 2) { + [cs_insn]@{} + } else { + New-Object -TypeName cs_insn + } + + $cs_insn_size = [System.Runtime.InteropServices.Marshal]::SizeOf($cs_insn) + $cs_insn = $cs_insn.GetType() + + # Result detail struct + $cs_detail = if ($PSVersionTable.PSVersion.Major -gt 2) { + [cs_detail]@{} + } else { + New-Object -TypeName cs_detail + } + $cs_detail = $cs_detail.GetType() + + # Result buffer offset + $BuffOffset = $InsnHandle.ToInt64() + + for ($i = 0 ; $i -lt $Count ; $i++) { + # Cast Offset to cs_insn + $Cast = [System.Runtime.InteropServices.Marshal]::PtrToStructure([System.Intptr]$BuffOffset, [type]$cs_insn) + + if ($CS_OPT -eq 0) { + $Disassembly = @{ + Address = $Cast.address + Instruction = '{0} {1}' -f $Cast.mnemonic, $Cast.operands + } + + if ($PSVersionTable.PSVersion.Major -gt 2) { + # Add TypeName for PS formatting and output result + $Disassembly.PSTypeName ='CapstoneDisassembly.Simple' + [pscustomobject]$Disassembly + } else { + $Disassembly = New-Object -TypeName PSObject -Property $Disassembly + # Add TypeName for PS formatting and output result + $Disassembly.PSObject.TypeNames.Insert(0, 'CapstoneDisassembly.Simple') + $Disassembly + } + } else { + $DetailCast = [System.Runtime.InteropServices.Marshal]::PtrToStructure($Cast.detail, [type]$cs_detail) + if ($DetailCast.regs_read_count -gt 0) { + $RegRead = for ($r = 0 ; $r -lt $DetailCast.regs_read_count ; $r++) { + $NamePointer = [Capstone]::cs_reg_name($DisAsmHandle, $DetailCast.regs_read[$r]) + [System.Runtime.InteropServices.Marshal]::PtrToStringAnsi($NamePointer) + } + } + + if ($DetailCast.regs_write_count -gt 0) { + $RegWrite = for ($r = 0 ; $r -lt $DetailCast.regs_write_count ; $r++) { + $NamePointer = [Capstone]::cs_reg_name($DisAsmHandle, $DetailCast.regs_write[$r]) + [System.Runtime.InteropServices.Marshal]::PtrToStringAnsi($NamePointer) + } + } + + $Disassembly = @{ + Address = $Cast.address + Mnemonic = $Cast.mnemonic + Operands = $Cast.operands + Bytes = $Cast.bytes[0..($Cast.size - 1)] + Size = $Cast.size + RegRead = $RegRead + RegWrite = $RegWrite + } + + if ($PSVersionTable.PSVersion.Major -gt 2) { + # Add TypeName for PS formatting and output result + $Disassembly.PSTypeName = 'CapstoneDisassembly.Detailed' + [pscustomobject]$Disassembly + } else { + $Disassembly = New-Object -TypeName PSObject -Property $Disassembly + # Add TypeName for PS formatting and output result + $Disassembly.PSObject.TypeNames.Insert(0, 'CapstoneDisassembly.Detailed') + $Disassembly + } + } + $BuffOffset = $BuffOffset + $cs_insn_size + } + } else { + $CallResult = [Capstone]::cs_close([ref]$DisAsmHandle) + throw 'Disassembly Failed' + } + + # Free Buffer Handle + $CallResult = [Capstone]::cs_free($InsnHandle, $Count) +} + +#region Init + +Initialize-Capstone -DllPath ( + Join-Path -Path $PSScriptRoot -ChildPath 'Lib\Capstone\capstone.dll' +) -ErrorAction Stop + +#endregion \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/powershell/Capstone/Lib/Capstone/.gitignore b/white_patch_detect/capstone-master/bindings/powershell/Capstone/Lib/Capstone/.gitignore new file mode 100644 index 0000000..e69de29 diff --git a/white_patch_detect/capstone-master/bindings/powershell/README.md b/white_patch_detect/capstone-master/bindings/powershell/README.md new file mode 100644 index 0000000..1197a31 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/powershell/README.md @@ -0,0 +1,30 @@ +This documentation explains how to install & use the PowerShell binding for Capstone. + + +Install +------ + +Compile the relevant version (x86/x64) of `capstone.dll` and place it in +`./Capstone/Lib/Capstone/`. + +Alternatively, pre-compiled DLL鈥檚 can be obtained from the Capstone homepage +at http://capstone-engine.org/download + + +Usage +----- + +To use the PowerShell binding, the entire Capstone folder should be added to +one of the PowerShell module directories: + + # Global PSModulePath path + %Windir%\System32\WindowsPowerShell\v1.0\Modules + + # User PSModulePath path + %UserProfile%\Documents\WindowsPowerShell\Modules + +Once this is done the module can be initialized by typing 鈥淚mport-Module Capstone鈥 +in a new PowerShell terminal. Further information on the usage of the binding +can be obtained with the following command: + + Get-Help Get-CapstoneDisassembly -Full \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/python/.gitignore b/white_patch_detect/capstone-master/bindings/python/.gitignore new file mode 100644 index 0000000..61178e6 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/.gitignore @@ -0,0 +1,9 @@ +MANIFEST +dist/ +src/ +capstone/lib +capstone/include +pyx/lib +pyx/include +pyx/*.c +pyx/*.pyx diff --git a/white_patch_detect/capstone-master/bindings/python/BUILDING.txt b/white_patch_detect/capstone-master/bindings/python/BUILDING.txt new file mode 100644 index 0000000..e527b15 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/BUILDING.txt @@ -0,0 +1,77 @@ +0. This documentation explains how to install the Python bindings for Capstone + from source. If you want to install it from a PyPi package (recommended if + you are on Windows), see README.txt. + +1. To install Capstone and the Python bindings on *nix, run the command below: + + $ sudo make install + + To install Capstone for Python 3, run the command below: + (Note: this requires python3 installed in your machine) + + $ sudo make install3 + + To control the install destination, set the DESTDIR environment variable. + +2. For better Python performance, install cython-based binding with: + + $ sudo make install_cython + + Note that this requires Cython installed first. To install Cython, see + below. + +3. To install Cython, you have to ensure that the header files + and the static library for Python are installed beforehand. + + E.g. on Ubuntu, do: + + $ sudo apt-get install python-dev + + Depending on if you already have pip or easy_install installed, install + Cython with either: + + $ sudo pip install cython + or: + $ sudo easy_install cython + + NOTE: Depending on your distribution you might also be able to + install the required Cython version using your repository. + + E.g. on Ubuntu, do: + + $ sudo apt-get install cython + + However, our cython-based binding requires Cython version 0.19 or newer, + but sometimes distributions only provide older version. Make sure to + verify the current installed version before going into section 2 above. + + E.g, on Ubuntu, you can verify the current Cython version with: + + $ apt-cache policy cython + + Which should at least print version 0.19 + +4. This directory contains some test code to show how to use the Capstone API. + +- test_basic.py + This code shows the most simple form of API where we only want to get basic + information out of disassembled instruction, such as address, mnemonic and + operand string. + +- test_lite.py + Similarly to test_basic.py, but this code shows how to use disasm_lite(), a lighter + method to disassemble binary. Unlike disasm() API (used by test_basic.py), which returns + CsInsn objects, this API just returns tuples of (address, size, mnemonic, op_str). + + The main reason for using this API is better performance: disasm_lite() is at least + 20% faster than disasm(). Memory usage is also less. So if you just need basic + information out of disassembler, use disasm_lite() instead of disasm(). + +- test_detail.py: + This code shows how to access to architecture-neutral information in disassembled + instructions, such as implicit registers read/written, or groups of instructions + that this instruction belong to. + +- test_.py + These code show how to access architecture-specific information for each + architecture. diff --git a/white_patch_detect/capstone-master/bindings/python/LICENSE.TXT b/white_patch_detect/capstone-master/bindings/python/LICENSE.TXT new file mode 100644 index 0000000..0dabdc7 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/LICENSE.TXT @@ -0,0 +1,31 @@ +This is the software license for Capstone disassembly framework. +Capstone has been designed & implemented by Nguyen Anh Quynh + +See http://www.capstone-engine.org for further information. + +Copyright (c) 2013, COSEINC. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. +* Neither the name of the developer(s) nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/white_patch_detect/capstone-master/bindings/python/MANIFEST.in b/white_patch_detect/capstone-master/bindings/python/MANIFEST.in new file mode 100644 index 0000000..98776c7 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/MANIFEST.in @@ -0,0 +1,5 @@ +recursive-include src * +include LICENSE.TXT +include README.txt +include BUILDING.txt +include Makefile diff --git a/white_patch_detect/capstone-master/bindings/python/Makefile b/white_patch_detect/capstone-master/bindings/python/Makefile new file mode 100644 index 0000000..15a280f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/Makefile @@ -0,0 +1,81 @@ +PYTHON2 ?= python +PYTHON3 ?= python3 + +.PHONY: gen_const install install3 install_cython sdist sdist3 bdist bdist3 clean check + +gen_const: + cd .. && $(PYTHON2) const_generator.py python + +install: + rm -rf src/ + if test -n "${DESTDIR}"; then \ + $(PYTHON2) setup.py build install --root="${DESTDIR}"; \ + else \ + $(PYTHON2) setup.py build install; \ + fi + +install3: + rm -rf src/ + if test -n "${DESTDIR}"; then \ + $(PYTHON3) setup.py build install --root="${DESTDIR}"; \ + else \ + $(PYTHON3) setup.py build install; \ + fi + +# NOTE: Newer cython can be installed by: sudo pip install --upgrade cython +install_cython: + rm -rf src/ + if test -n "${DESTDIR}"; then \ + $(PYTHON2) setup_cython.py build install --root="${DESTDIR}"; \ + else \ + $(PYTHON2) setup_cython.py build install; \ + fi + +install3_cython: + rm -rf src/ + if test -n "${DESTDIR}"; then \ + $(PYTHON3) setup_cython.py build install --root="${DESTDIR}"; \ + else \ + $(PYTHON3) setup_cython.py build install; \ + fi + +# build & upload PyPi package with source code of the core +sdist: + rm -rf src/ dist/ + $(PYTHON2) setup.py sdist register upload + +# build & upload PyPi package with source code of the core +sdist3: + rm -rf src/ dist/ + $(PYTHON3) setup.py sdist register upload + +# build & upload PyPi package with prebuilt core +bdist: + rm -rf src/ dist/ + $(PYTHON2) setup.py bdist_wheel register upload + +# build & upload PyPi package with prebuilt core +bdist3: + rm -rf src/ dist/ + $(PYTHON3) setup.py bdist_wheel register upload + +clean: + rm -rf build/ src/ dist/ *.egg-info + rm -rf capstone/lib capstone/include pyx/lib pyx/include + rm -f pyx/*.c pyx/__init__.py + for f in capstone/*.py; do rm -f pyx/$$(basename $$f)x; done + rm -f MANIFEST + rm -f *.pyc capstone/*.pyc + + +TESTS = test_basic.py test_detail.py test_arm.py test_arm64.py test_m68k.py test_mips.py +TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py +TESTS += test_m680x.py test_skipdata.py test_mos65xx.py + +check: + @for t in $(TESTS); do \ + echo Check $$t ... ; \ + ./$$t > /dev/null; \ + if [ $$? -eq 0 ]; then echo OK; else echo FAILED; exit 1; fi \ + done + diff --git a/white_patch_detect/capstone-master/bindings/python/README.txt b/white_patch_detect/capstone-master/bindings/python/README.txt new file mode 100644 index 0000000..69e36bb --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/README.txt @@ -0,0 +1,65 @@ +To install Capstone, you should run `pip install capstone`. + +If you would like to build Capstone with just the source distribution, without +pip, just run `python setup.py install` in the folder with setup.py in it. + +In order to use this source distribution, you will need an environment that can +compile C code. On Linux, this is usually easy, but on Windows, this involves +installing Visual Studio and using the "Developer Command Prompt" to perform the +installation. See BUILDING.txt for more information. + +By default, attempting to install the python bindings will trigger a build of +the capstone native core. If this is undesirable for whatever reason, for +instance, you already have a globally installed copy of libcapstone, you may +inhibit the build by setting the environment variable LIBCAPSTONE_PATH. The +exact value is not checked, just setting it will inhibit the build. During +execution, this variable may be set to the path of a directory containing a +specific version of libcapstone you would like to use. + +If you don't want to build your own copy of Capstone, you can use a precompiled +binary distribution from PyPI. Saying `pip install capstone` should +automatically obtain an appropriate copy for your system. If it does not, please +open an issue at https://github.com/aquynh/capstone and tag @rhelmot - she +will fix this, probably! + +-------------------------------------------------------------------------------- + +Capstone is a disassembly framework with the target of becoming the ultimate +disasm engine for binary analysis and reversing in the security community. + +Created by Nguyen Anh Quynh, then developed and maintained by a small community, +Capstone offers some unparalleled features: + +- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc, + SystemZ, XCore and X86 (including X86_64). + +- Having clean/simple/lightweight/intuitive architecture-neutral API. + +- Provide details on disassembled instruction (called 鈥渄ecomposer鈥 by others). + +- Provide semantics of the disassembled instruction, such as list of implicit + registers read & written. + +- Implemented in pure C language, with lightweight wrappers for C++, C#, Go, + Java, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code, + or provided externally by the community). + +- Native support for all popular platforms: Windows, Mac OSX, iOS, Android, + Linux, *BSD, Solaris, etc. + +- Thread-safe by design. + +- Special support for embedding into firmware or OS kernel. + +- High performance & suitable for malware analysis (capable of handling various + X86 malware tricks). + +- Distributed under the open source BSD license. + +Further information is available at http://www.capstone-engine.org + + +[License] + +This project is released under the BSD license. If you redistribute the binary +or source code of Capstone, please attach file LICENSE.TXT with your products. diff --git a/white_patch_detect/capstone-master/bindings/python/build_wheel.sh b/white_patch_detect/capstone-master/bindings/python/build_wheel.sh new file mode 100644 index 0000000..39ffcb3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/build_wheel.sh @@ -0,0 +1,15 @@ +#!/bin/bash +set -e -x + +cd bindings/python +sudo rm /usr/bin/python && sudo ln -s /opt/python/cp27-cp27m/bin/python /usr/bin/python; python -V + +# Compile wheels +if [ -f /opt/python/cp36-cp36m/bin/python ];then + /opt/python/cp36-cp36m/bin/python setup.py bdist_wheel +else + python3 setup.py bdist_wheel +fi +cd dist +auditwheel repair *.whl +mv -f wheelhouse/*.whl . diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/arm.py b/white_patch_detect/capstone-master/bindings/python/capstone/arm.py new file mode 100644 index 0000000..4ed902e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/arm.py @@ -0,0 +1,82 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .arm_const import * + +# define the API +class ArmOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('index', ctypes.c_uint), + ('scale', ctypes.c_int), + ('disp', ctypes.c_int), + ('lshift', ctypes.c_int), + ) + +class ArmOpShift(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', ctypes.c_uint), + ) + +class ArmOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int32), + ('fp', ctypes.c_double), + ('mem', ArmOpMem), + ('setend', ctypes.c_int), + ) + +class ArmOp(ctypes.Structure): + _fields_ = ( + ('vector_index', ctypes.c_int), + ('shift', ArmOpShift), + ('type', ctypes.c_uint), + ('value', ArmOpValue), + ('subtracted', ctypes.c_bool), + ('access', ctypes.c_uint8), + ('neon_lane', ctypes.c_int8), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def fp(self): + return self.value.fp + + @property + def mem(self): + return self.value.mem + + @property + def setend(self): + return self.value.setend + + +class CsArm(ctypes.Structure): + _fields_ = ( + ('usermode', ctypes.c_bool), + ('vector_size', ctypes.c_int), + ('vector_data', ctypes.c_int), + ('cps_mode', ctypes.c_int), + ('cps_flag', ctypes.c_int), + ('cc', ctypes.c_uint), + ('update_flags', ctypes.c_bool), + ('writeback', ctypes.c_bool), + ('mem_barrier', ctypes.c_int), + ('op_count', ctypes.c_uint8), + ('operands', ArmOp * 36), + ) + +def get_arch_info(a): + return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.update_flags, \ + a.writeback, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/arm64.py b/white_patch_detect/capstone-master/bindings/python/capstone/arm64.py new file mode 100644 index 0000000..1d4efc3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/arm64.py @@ -0,0 +1,90 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .arm64_const import * + +# define the API +class Arm64OpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('index', ctypes.c_uint), + ('disp', ctypes.c_int32), + ) + +class Arm64OpShift(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', ctypes.c_uint), + ) + +class Arm64OpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('fp', ctypes.c_double), + ('mem', Arm64OpMem), + ('pstate', ctypes.c_int), + ('sys', ctypes.c_uint), + ('prefetch', ctypes.c_int), + ('barrier', ctypes.c_int), + ) + +class Arm64Op(ctypes.Structure): + _fields_ = ( + ('vector_index', ctypes.c_int), + ('vas', ctypes.c_int), + ('vess', ctypes.c_int), + ('shift', Arm64OpShift), + ('ext', ctypes.c_uint), + ('type', ctypes.c_uint), + ('value', Arm64OpValue), + ('access', ctypes.c_uint8), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def fp(self): + return self.value.fp + + @property + def mem(self): + return self.value.mem + + @property + def pstate(self): + return self.value.pstate + + @property + def sys(self): + return self.value.sys + + @property + def prefetch(self): + return self.value.prefetch + + @property + def barrier(self): + return self.value.barrier + + + +class CsArm64(ctypes.Structure): + _fields_ = ( + ('cc', ctypes.c_uint), + ('update_flags', ctypes.c_bool), + ('writeback', ctypes.c_bool), + ('op_count', ctypes.c_uint8), + ('operands', Arm64Op * 8), + ) + +def get_arch_info(a): + return (a.cc, a.update_flags, a.writeback, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/arm64_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/arm64_const.py new file mode 100644 index 0000000..c5efab6 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/arm64_const.py @@ -0,0 +1,1006 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py] + +ARM64_SFT_INVALID = 0 +ARM64_SFT_LSL = 1 +ARM64_SFT_MSL = 2 +ARM64_SFT_LSR = 3 +ARM64_SFT_ASR = 4 +ARM64_SFT_ROR = 5 + +ARM64_EXT_INVALID = 0 +ARM64_EXT_UXTB = 1 +ARM64_EXT_UXTH = 2 +ARM64_EXT_UXTW = 3 +ARM64_EXT_UXTX = 4 +ARM64_EXT_SXTB = 5 +ARM64_EXT_SXTH = 6 +ARM64_EXT_SXTW = 7 +ARM64_EXT_SXTX = 8 + +ARM64_CC_INVALID = 0 +ARM64_CC_EQ = 1 +ARM64_CC_NE = 2 +ARM64_CC_HS = 3 +ARM64_CC_LO = 4 +ARM64_CC_MI = 5 +ARM64_CC_PL = 6 +ARM64_CC_VS = 7 +ARM64_CC_VC = 8 +ARM64_CC_HI = 9 +ARM64_CC_LS = 10 +ARM64_CC_GE = 11 +ARM64_CC_LT = 12 +ARM64_CC_GT = 13 +ARM64_CC_LE = 14 +ARM64_CC_AL = 15 +ARM64_CC_NV = 16 + +ARM64_SYSREG_INVALID = 0 +ARM64_SYSREG_MDCCSR_EL0 = 0x9808 +ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828 +ARM64_SYSREG_MDRAR_EL1 = 0x8080 +ARM64_SYSREG_OSLSR_EL1 = 0x808c +ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6 +ARM64_SYSREG_PMCEID0_EL0 = 0xdce6 +ARM64_SYSREG_PMCEID1_EL0 = 0xdce7 +ARM64_SYSREG_MIDR_EL1 = 0xc000 +ARM64_SYSREG_CCSIDR_EL1 = 0xc800 +ARM64_SYSREG_CLIDR_EL1 = 0xc801 +ARM64_SYSREG_CTR_EL0 = 0xd801 +ARM64_SYSREG_MPIDR_EL1 = 0xc005 +ARM64_SYSREG_REVIDR_EL1 = 0xc006 +ARM64_SYSREG_AIDR_EL1 = 0xc807 +ARM64_SYSREG_DCZID_EL0 = 0xd807 +ARM64_SYSREG_ID_PFR0_EL1 = 0xc008 +ARM64_SYSREG_ID_PFR1_EL1 = 0xc009 +ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a +ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b +ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c +ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d +ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e +ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f +ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010 +ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011 +ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012 +ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013 +ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014 +ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015 +ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020 +ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021 +ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028 +ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029 +ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c +ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d +ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030 +ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031 +ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038 +ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039 +ARM64_SYSREG_MVFR0_EL1 = 0xc018 +ARM64_SYSREG_MVFR1_EL1 = 0xc019 +ARM64_SYSREG_MVFR2_EL1 = 0xc01a +ARM64_SYSREG_RVBAR_EL1 = 0xc601 +ARM64_SYSREG_RVBAR_EL2 = 0xe601 +ARM64_SYSREG_RVBAR_EL3 = 0xf601 +ARM64_SYSREG_ISR_EL1 = 0xc608 +ARM64_SYSREG_CNTPCT_EL0 = 0xdf01 +ARM64_SYSREG_CNTVCT_EL0 = 0xdf02 +ARM64_SYSREG_TRCSTATR = 0x8818 +ARM64_SYSREG_TRCIDR8 = 0x8806 +ARM64_SYSREG_TRCIDR9 = 0x880e +ARM64_SYSREG_TRCIDR10 = 0x8816 +ARM64_SYSREG_TRCIDR11 = 0x881e +ARM64_SYSREG_TRCIDR12 = 0x8826 +ARM64_SYSREG_TRCIDR13 = 0x882e +ARM64_SYSREG_TRCIDR0 = 0x8847 +ARM64_SYSREG_TRCIDR1 = 0x884f +ARM64_SYSREG_TRCIDR2 = 0x8857 +ARM64_SYSREG_TRCIDR3 = 0x885f +ARM64_SYSREG_TRCIDR4 = 0x8867 +ARM64_SYSREG_TRCIDR5 = 0x886f +ARM64_SYSREG_TRCIDR6 = 0x8877 +ARM64_SYSREG_TRCIDR7 = 0x887f +ARM64_SYSREG_TRCOSLSR = 0x888c +ARM64_SYSREG_TRCPDSR = 0x88ac +ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6 +ARM64_SYSREG_TRCDEVAFF1 = 0x8bde +ARM64_SYSREG_TRCLSR = 0x8bee +ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6 +ARM64_SYSREG_TRCDEVARCH = 0x8bfe +ARM64_SYSREG_TRCDEVID = 0x8b97 +ARM64_SYSREG_TRCDEVTYPE = 0x8b9f +ARM64_SYSREG_TRCPIDR4 = 0x8ba7 +ARM64_SYSREG_TRCPIDR5 = 0x8baf +ARM64_SYSREG_TRCPIDR6 = 0x8bb7 +ARM64_SYSREG_TRCPIDR7 = 0x8bbf +ARM64_SYSREG_TRCPIDR0 = 0x8bc7 +ARM64_SYSREG_TRCPIDR1 = 0x8bcf +ARM64_SYSREG_TRCPIDR2 = 0x8bd7 +ARM64_SYSREG_TRCPIDR3 = 0x8bdf +ARM64_SYSREG_TRCCIDR0 = 0x8be7 +ARM64_SYSREG_TRCCIDR1 = 0x8bef +ARM64_SYSREG_TRCCIDR2 = 0x8bf7 +ARM64_SYSREG_TRCCIDR3 = 0x8bff +ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660 +ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640 +ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662 +ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642 +ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b +ARM64_SYSREG_ICH_VTR_EL2 = 0xe659 +ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b +ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d +ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828 +ARM64_SYSREG_OSLAR_EL1 = 0x8084 +ARM64_SYSREG_PMSWINC_EL0 = 0xdce4 +ARM64_SYSREG_TRCOSLAR = 0x8884 +ARM64_SYSREG_TRCLAR = 0x8be6 +ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661 +ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641 +ARM64_SYSREG_ICC_DIR_EL1 = 0xc659 +ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d +ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e +ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f + +ARM64_PSTATE_INVALID = 0 +ARM64_PSTATE_SPSEL = 0x05 +ARM64_PSTATE_DAIFSET = 0x1e +ARM64_PSTATE_DAIFCLR = 0x1f + +ARM64_VAS_INVALID = 0 +ARM64_VAS_8B = 1 +ARM64_VAS_16B = 2 +ARM64_VAS_4H = 3 +ARM64_VAS_8H = 4 +ARM64_VAS_2S = 5 +ARM64_VAS_4S = 6 +ARM64_VAS_1D = 7 +ARM64_VAS_2D = 8 +ARM64_VAS_1Q = 9 + +ARM64_VESS_INVALID = 0 +ARM64_VESS_B = 1 +ARM64_VESS_H = 2 +ARM64_VESS_S = 3 +ARM64_VESS_D = 4 + +ARM64_BARRIER_INVALID = 0 +ARM64_BARRIER_OSHLD = 0x1 +ARM64_BARRIER_OSHST = 0x2 +ARM64_BARRIER_OSH = 0x3 +ARM64_BARRIER_NSHLD = 0x5 +ARM64_BARRIER_NSHST = 0x6 +ARM64_BARRIER_NSH = 0x7 +ARM64_BARRIER_ISHLD = 0x9 +ARM64_BARRIER_ISHST = 0xa +ARM64_BARRIER_ISH = 0xb +ARM64_BARRIER_LD = 0xd +ARM64_BARRIER_ST = 0xe +ARM64_BARRIER_SY = 0xf + +ARM64_OP_INVALID = 0 +ARM64_OP_REG = 1 +ARM64_OP_IMM = 2 +ARM64_OP_MEM = 3 +ARM64_OP_FP = 4 +ARM64_OP_CIMM = 64 +ARM64_OP_REG_MRS = 65 +ARM64_OP_REG_MSR = 66 +ARM64_OP_PSTATE = 67 +ARM64_OP_SYS = 68 +ARM64_OP_PREFETCH = 69 +ARM64_OP_BARRIER = 70 + +ARM64_TLBI_INVALID = 0 +ARM64_TLBI_VMALLE1IS = 1 +ARM64_TLBI_VAE1IS = 2 +ARM64_TLBI_ASIDE1IS = 3 +ARM64_TLBI_VAAE1IS = 4 +ARM64_TLBI_VALE1IS = 5 +ARM64_TLBI_VAALE1IS = 6 +ARM64_TLBI_ALLE2IS = 7 +ARM64_TLBI_VAE2IS = 8 +ARM64_TLBI_ALLE1IS = 9 +ARM64_TLBI_VALE2IS = 10 +ARM64_TLBI_VMALLS12E1IS = 11 +ARM64_TLBI_ALLE3IS = 12 +ARM64_TLBI_VAE3IS = 13 +ARM64_TLBI_VALE3IS = 14 +ARM64_TLBI_IPAS2E1IS = 15 +ARM64_TLBI_IPAS2LE1IS = 16 +ARM64_TLBI_IPAS2E1 = 17 +ARM64_TLBI_IPAS2LE1 = 18 +ARM64_TLBI_VMALLE1 = 19 +ARM64_TLBI_VAE1 = 20 +ARM64_TLBI_ASIDE1 = 21 +ARM64_TLBI_VAAE1 = 22 +ARM64_TLBI_VALE1 = 23 +ARM64_TLBI_VAALE1 = 24 +ARM64_TLBI_ALLE2 = 25 +ARM64_TLBI_VAE2 = 26 +ARM64_TLBI_ALLE1 = 27 +ARM64_TLBI_VALE2 = 28 +ARM64_TLBI_VMALLS12E1 = 29 +ARM64_TLBI_ALLE3 = 30 +ARM64_TLBI_VAE3 = 31 +ARM64_TLBI_VALE3 = 32 +ARM64_AT_S1E1R = 33 +ARM64_AT_S1E1W = 34 +ARM64_AT_S1E0R = 35 +ARM64_AT_S1E0W = 36 +ARM64_AT_S1E2R = 37 +ARM64_AT_S1E2W = 38 +ARM64_AT_S12E1R = 39 +ARM64_AT_S12E1W = 40 +ARM64_AT_S12E0R = 41 +ARM64_AT_S12E0W = 42 +ARM64_AT_S1E3R = 43 +ARM64_AT_S1E3W = 44 + +ARM64_DC_INVALID = 0 +ARM64_DC_ZVA = 1 +ARM64_DC_IVAC = 2 +ARM64_DC_ISW = 3 +ARM64_DC_CVAC = 4 +ARM64_DC_CSW = 5 +ARM64_DC_CVAU = 6 +ARM64_DC_CIVAC = 7 +ARM64_DC_CISW = 8 + +ARM64_IC_INVALID = 0 +ARM64_IC_IALLUIS = 1 +ARM64_IC_IALLU = 2 +ARM64_IC_IVAU = 3 + +ARM64_PRFM_INVALID = 0 +ARM64_PRFM_PLDL1KEEP = 0x00+1 +ARM64_PRFM_PLDL1STRM = 0x01+1 +ARM64_PRFM_PLDL2KEEP = 0x02+1 +ARM64_PRFM_PLDL2STRM = 0x03+1 +ARM64_PRFM_PLDL3KEEP = 0x04+1 +ARM64_PRFM_PLDL3STRM = 0x05+1 +ARM64_PRFM_PLIL1KEEP = 0x08+1 +ARM64_PRFM_PLIL1STRM = 0x09+1 +ARM64_PRFM_PLIL2KEEP = 0x0a+1 +ARM64_PRFM_PLIL2STRM = 0x0b+1 +ARM64_PRFM_PLIL3KEEP = 0x0c+1 +ARM64_PRFM_PLIL3STRM = 0x0d+1 +ARM64_PRFM_PSTL1KEEP = 0x10+1 +ARM64_PRFM_PSTL1STRM = 0x11+1 +ARM64_PRFM_PSTL2KEEP = 0x12+1 +ARM64_PRFM_PSTL2STRM = 0x13+1 +ARM64_PRFM_PSTL3KEEP = 0x14+1 +ARM64_PRFM_PSTL3STRM = 0x15+1 + +ARM64_REG_INVALID = 0 +ARM64_REG_X29 = 1 +ARM64_REG_X30 = 2 +ARM64_REG_NZCV = 3 +ARM64_REG_SP = 4 +ARM64_REG_WSP = 5 +ARM64_REG_WZR = 6 +ARM64_REG_XZR = 7 +ARM64_REG_B0 = 8 +ARM64_REG_B1 = 9 +ARM64_REG_B2 = 10 +ARM64_REG_B3 = 11 +ARM64_REG_B4 = 12 +ARM64_REG_B5 = 13 +ARM64_REG_B6 = 14 +ARM64_REG_B7 = 15 +ARM64_REG_B8 = 16 +ARM64_REG_B9 = 17 +ARM64_REG_B10 = 18 +ARM64_REG_B11 = 19 +ARM64_REG_B12 = 20 +ARM64_REG_B13 = 21 +ARM64_REG_B14 = 22 +ARM64_REG_B15 = 23 +ARM64_REG_B16 = 24 +ARM64_REG_B17 = 25 +ARM64_REG_B18 = 26 +ARM64_REG_B19 = 27 +ARM64_REG_B20 = 28 +ARM64_REG_B21 = 29 +ARM64_REG_B22 = 30 +ARM64_REG_B23 = 31 +ARM64_REG_B24 = 32 +ARM64_REG_B25 = 33 +ARM64_REG_B26 = 34 +ARM64_REG_B27 = 35 +ARM64_REG_B28 = 36 +ARM64_REG_B29 = 37 +ARM64_REG_B30 = 38 +ARM64_REG_B31 = 39 +ARM64_REG_D0 = 40 +ARM64_REG_D1 = 41 +ARM64_REG_D2 = 42 +ARM64_REG_D3 = 43 +ARM64_REG_D4 = 44 +ARM64_REG_D5 = 45 +ARM64_REG_D6 = 46 +ARM64_REG_D7 = 47 +ARM64_REG_D8 = 48 +ARM64_REG_D9 = 49 +ARM64_REG_D10 = 50 +ARM64_REG_D11 = 51 +ARM64_REG_D12 = 52 +ARM64_REG_D13 = 53 +ARM64_REG_D14 = 54 +ARM64_REG_D15 = 55 +ARM64_REG_D16 = 56 +ARM64_REG_D17 = 57 +ARM64_REG_D18 = 58 +ARM64_REG_D19 = 59 +ARM64_REG_D20 = 60 +ARM64_REG_D21 = 61 +ARM64_REG_D22 = 62 +ARM64_REG_D23 = 63 +ARM64_REG_D24 = 64 +ARM64_REG_D25 = 65 +ARM64_REG_D26 = 66 +ARM64_REG_D27 = 67 +ARM64_REG_D28 = 68 +ARM64_REG_D29 = 69 +ARM64_REG_D30 = 70 +ARM64_REG_D31 = 71 +ARM64_REG_H0 = 72 +ARM64_REG_H1 = 73 +ARM64_REG_H2 = 74 +ARM64_REG_H3 = 75 +ARM64_REG_H4 = 76 +ARM64_REG_H5 = 77 +ARM64_REG_H6 = 78 +ARM64_REG_H7 = 79 +ARM64_REG_H8 = 80 +ARM64_REG_H9 = 81 +ARM64_REG_H10 = 82 +ARM64_REG_H11 = 83 +ARM64_REG_H12 = 84 +ARM64_REG_H13 = 85 +ARM64_REG_H14 = 86 +ARM64_REG_H15 = 87 +ARM64_REG_H16 = 88 +ARM64_REG_H17 = 89 +ARM64_REG_H18 = 90 +ARM64_REG_H19 = 91 +ARM64_REG_H20 = 92 +ARM64_REG_H21 = 93 +ARM64_REG_H22 = 94 +ARM64_REG_H23 = 95 +ARM64_REG_H24 = 96 +ARM64_REG_H25 = 97 +ARM64_REG_H26 = 98 +ARM64_REG_H27 = 99 +ARM64_REG_H28 = 100 +ARM64_REG_H29 = 101 +ARM64_REG_H30 = 102 +ARM64_REG_H31 = 103 +ARM64_REG_Q0 = 104 +ARM64_REG_Q1 = 105 +ARM64_REG_Q2 = 106 +ARM64_REG_Q3 = 107 +ARM64_REG_Q4 = 108 +ARM64_REG_Q5 = 109 +ARM64_REG_Q6 = 110 +ARM64_REG_Q7 = 111 +ARM64_REG_Q8 = 112 +ARM64_REG_Q9 = 113 +ARM64_REG_Q10 = 114 +ARM64_REG_Q11 = 115 +ARM64_REG_Q12 = 116 +ARM64_REG_Q13 = 117 +ARM64_REG_Q14 = 118 +ARM64_REG_Q15 = 119 +ARM64_REG_Q16 = 120 +ARM64_REG_Q17 = 121 +ARM64_REG_Q18 = 122 +ARM64_REG_Q19 = 123 +ARM64_REG_Q20 = 124 +ARM64_REG_Q21 = 125 +ARM64_REG_Q22 = 126 +ARM64_REG_Q23 = 127 +ARM64_REG_Q24 = 128 +ARM64_REG_Q25 = 129 +ARM64_REG_Q26 = 130 +ARM64_REG_Q27 = 131 +ARM64_REG_Q28 = 132 +ARM64_REG_Q29 = 133 +ARM64_REG_Q30 = 134 +ARM64_REG_Q31 = 135 +ARM64_REG_S0 = 136 +ARM64_REG_S1 = 137 +ARM64_REG_S2 = 138 +ARM64_REG_S3 = 139 +ARM64_REG_S4 = 140 +ARM64_REG_S5 = 141 +ARM64_REG_S6 = 142 +ARM64_REG_S7 = 143 +ARM64_REG_S8 = 144 +ARM64_REG_S9 = 145 +ARM64_REG_S10 = 146 +ARM64_REG_S11 = 147 +ARM64_REG_S12 = 148 +ARM64_REG_S13 = 149 +ARM64_REG_S14 = 150 +ARM64_REG_S15 = 151 +ARM64_REG_S16 = 152 +ARM64_REG_S17 = 153 +ARM64_REG_S18 = 154 +ARM64_REG_S19 = 155 +ARM64_REG_S20 = 156 +ARM64_REG_S21 = 157 +ARM64_REG_S22 = 158 +ARM64_REG_S23 = 159 +ARM64_REG_S24 = 160 +ARM64_REG_S25 = 161 +ARM64_REG_S26 = 162 +ARM64_REG_S27 = 163 +ARM64_REG_S28 = 164 +ARM64_REG_S29 = 165 +ARM64_REG_S30 = 166 +ARM64_REG_S31 = 167 +ARM64_REG_W0 = 168 +ARM64_REG_W1 = 169 +ARM64_REG_W2 = 170 +ARM64_REG_W3 = 171 +ARM64_REG_W4 = 172 +ARM64_REG_W5 = 173 +ARM64_REG_W6 = 174 +ARM64_REG_W7 = 175 +ARM64_REG_W8 = 176 +ARM64_REG_W9 = 177 +ARM64_REG_W10 = 178 +ARM64_REG_W11 = 179 +ARM64_REG_W12 = 180 +ARM64_REG_W13 = 181 +ARM64_REG_W14 = 182 +ARM64_REG_W15 = 183 +ARM64_REG_W16 = 184 +ARM64_REG_W17 = 185 +ARM64_REG_W18 = 186 +ARM64_REG_W19 = 187 +ARM64_REG_W20 = 188 +ARM64_REG_W21 = 189 +ARM64_REG_W22 = 190 +ARM64_REG_W23 = 191 +ARM64_REG_W24 = 192 +ARM64_REG_W25 = 193 +ARM64_REG_W26 = 194 +ARM64_REG_W27 = 195 +ARM64_REG_W28 = 196 +ARM64_REG_W29 = 197 +ARM64_REG_W30 = 198 +ARM64_REG_X0 = 199 +ARM64_REG_X1 = 200 +ARM64_REG_X2 = 201 +ARM64_REG_X3 = 202 +ARM64_REG_X4 = 203 +ARM64_REG_X5 = 204 +ARM64_REG_X6 = 205 +ARM64_REG_X7 = 206 +ARM64_REG_X8 = 207 +ARM64_REG_X9 = 208 +ARM64_REG_X10 = 209 +ARM64_REG_X11 = 210 +ARM64_REG_X12 = 211 +ARM64_REG_X13 = 212 +ARM64_REG_X14 = 213 +ARM64_REG_X15 = 214 +ARM64_REG_X16 = 215 +ARM64_REG_X17 = 216 +ARM64_REG_X18 = 217 +ARM64_REG_X19 = 218 +ARM64_REG_X20 = 219 +ARM64_REG_X21 = 220 +ARM64_REG_X22 = 221 +ARM64_REG_X23 = 222 +ARM64_REG_X24 = 223 +ARM64_REG_X25 = 224 +ARM64_REG_X26 = 225 +ARM64_REG_X27 = 226 +ARM64_REG_X28 = 227 +ARM64_REG_V0 = 228 +ARM64_REG_V1 = 229 +ARM64_REG_V2 = 230 +ARM64_REG_V3 = 231 +ARM64_REG_V4 = 232 +ARM64_REG_V5 = 233 +ARM64_REG_V6 = 234 +ARM64_REG_V7 = 235 +ARM64_REG_V8 = 236 +ARM64_REG_V9 = 237 +ARM64_REG_V10 = 238 +ARM64_REG_V11 = 239 +ARM64_REG_V12 = 240 +ARM64_REG_V13 = 241 +ARM64_REG_V14 = 242 +ARM64_REG_V15 = 243 +ARM64_REG_V16 = 244 +ARM64_REG_V17 = 245 +ARM64_REG_V18 = 246 +ARM64_REG_V19 = 247 +ARM64_REG_V20 = 248 +ARM64_REG_V21 = 249 +ARM64_REG_V22 = 250 +ARM64_REG_V23 = 251 +ARM64_REG_V24 = 252 +ARM64_REG_V25 = 253 +ARM64_REG_V26 = 254 +ARM64_REG_V27 = 255 +ARM64_REG_V28 = 256 +ARM64_REG_V29 = 257 +ARM64_REG_V30 = 258 +ARM64_REG_V31 = 259 +ARM64_REG_ENDING = 260 +ARM64_REG_IP0 = ARM64_REG_X16 +ARM64_REG_IP1 = ARM64_REG_X17 +ARM64_REG_FP = ARM64_REG_X29 +ARM64_REG_LR = ARM64_REG_X30 + +ARM64_INS_INVALID = 0 +ARM64_INS_ABS = 1 +ARM64_INS_ADC = 2 +ARM64_INS_ADDHN = 3 +ARM64_INS_ADDHN2 = 4 +ARM64_INS_ADDP = 5 +ARM64_INS_ADD = 6 +ARM64_INS_ADDV = 7 +ARM64_INS_ADR = 8 +ARM64_INS_ADRP = 9 +ARM64_INS_AESD = 10 +ARM64_INS_AESE = 11 +ARM64_INS_AESIMC = 12 +ARM64_INS_AESMC = 13 +ARM64_INS_AND = 14 +ARM64_INS_ASR = 15 +ARM64_INS_B = 16 +ARM64_INS_BFM = 17 +ARM64_INS_BIC = 18 +ARM64_INS_BIF = 19 +ARM64_INS_BIT = 20 +ARM64_INS_BL = 21 +ARM64_INS_BLR = 22 +ARM64_INS_BR = 23 +ARM64_INS_BRK = 24 +ARM64_INS_BSL = 25 +ARM64_INS_CBNZ = 26 +ARM64_INS_CBZ = 27 +ARM64_INS_CCMN = 28 +ARM64_INS_CCMP = 29 +ARM64_INS_CLREX = 30 +ARM64_INS_CLS = 31 +ARM64_INS_CLZ = 32 +ARM64_INS_CMEQ = 33 +ARM64_INS_CMGE = 34 +ARM64_INS_CMGT = 35 +ARM64_INS_CMHI = 36 +ARM64_INS_CMHS = 37 +ARM64_INS_CMLE = 38 +ARM64_INS_CMLT = 39 +ARM64_INS_CMTST = 40 +ARM64_INS_CNT = 41 +ARM64_INS_MOV = 42 +ARM64_INS_CRC32B = 43 +ARM64_INS_CRC32CB = 44 +ARM64_INS_CRC32CH = 45 +ARM64_INS_CRC32CW = 46 +ARM64_INS_CRC32CX = 47 +ARM64_INS_CRC32H = 48 +ARM64_INS_CRC32W = 49 +ARM64_INS_CRC32X = 50 +ARM64_INS_CSEL = 51 +ARM64_INS_CSINC = 52 +ARM64_INS_CSINV = 53 +ARM64_INS_CSNEG = 54 +ARM64_INS_DCPS1 = 55 +ARM64_INS_DCPS2 = 56 +ARM64_INS_DCPS3 = 57 +ARM64_INS_DMB = 58 +ARM64_INS_DRPS = 59 +ARM64_INS_DSB = 60 +ARM64_INS_DUP = 61 +ARM64_INS_EON = 62 +ARM64_INS_EOR = 63 +ARM64_INS_ERET = 64 +ARM64_INS_EXTR = 65 +ARM64_INS_EXT = 66 +ARM64_INS_FABD = 67 +ARM64_INS_FABS = 68 +ARM64_INS_FACGE = 69 +ARM64_INS_FACGT = 70 +ARM64_INS_FADD = 71 +ARM64_INS_FADDP = 72 +ARM64_INS_FCCMP = 73 +ARM64_INS_FCCMPE = 74 +ARM64_INS_FCMEQ = 75 +ARM64_INS_FCMGE = 76 +ARM64_INS_FCMGT = 77 +ARM64_INS_FCMLE = 78 +ARM64_INS_FCMLT = 79 +ARM64_INS_FCMP = 80 +ARM64_INS_FCMPE = 81 +ARM64_INS_FCSEL = 82 +ARM64_INS_FCVTAS = 83 +ARM64_INS_FCVTAU = 84 +ARM64_INS_FCVT = 85 +ARM64_INS_FCVTL = 86 +ARM64_INS_FCVTL2 = 87 +ARM64_INS_FCVTMS = 88 +ARM64_INS_FCVTMU = 89 +ARM64_INS_FCVTNS = 90 +ARM64_INS_FCVTNU = 91 +ARM64_INS_FCVTN = 92 +ARM64_INS_FCVTN2 = 93 +ARM64_INS_FCVTPS = 94 +ARM64_INS_FCVTPU = 95 +ARM64_INS_FCVTXN = 96 +ARM64_INS_FCVTXN2 = 97 +ARM64_INS_FCVTZS = 98 +ARM64_INS_FCVTZU = 99 +ARM64_INS_FDIV = 100 +ARM64_INS_FMADD = 101 +ARM64_INS_FMAX = 102 +ARM64_INS_FMAXNM = 103 +ARM64_INS_FMAXNMP = 104 +ARM64_INS_FMAXNMV = 105 +ARM64_INS_FMAXP = 106 +ARM64_INS_FMAXV = 107 +ARM64_INS_FMIN = 108 +ARM64_INS_FMINNM = 109 +ARM64_INS_FMINNMP = 110 +ARM64_INS_FMINNMV = 111 +ARM64_INS_FMINP = 112 +ARM64_INS_FMINV = 113 +ARM64_INS_FMLA = 114 +ARM64_INS_FMLS = 115 +ARM64_INS_FMOV = 116 +ARM64_INS_FMSUB = 117 +ARM64_INS_FMUL = 118 +ARM64_INS_FMULX = 119 +ARM64_INS_FNEG = 120 +ARM64_INS_FNMADD = 121 +ARM64_INS_FNMSUB = 122 +ARM64_INS_FNMUL = 123 +ARM64_INS_FRECPE = 124 +ARM64_INS_FRECPS = 125 +ARM64_INS_FRECPX = 126 +ARM64_INS_FRINTA = 127 +ARM64_INS_FRINTI = 128 +ARM64_INS_FRINTM = 129 +ARM64_INS_FRINTN = 130 +ARM64_INS_FRINTP = 131 +ARM64_INS_FRINTX = 132 +ARM64_INS_FRINTZ = 133 +ARM64_INS_FRSQRTE = 134 +ARM64_INS_FRSQRTS = 135 +ARM64_INS_FSQRT = 136 +ARM64_INS_FSUB = 137 +ARM64_INS_HINT = 138 +ARM64_INS_HLT = 139 +ARM64_INS_HVC = 140 +ARM64_INS_INS = 141 +ARM64_INS_ISB = 142 +ARM64_INS_LD1 = 143 +ARM64_INS_LD1R = 144 +ARM64_INS_LD2R = 145 +ARM64_INS_LD2 = 146 +ARM64_INS_LD3R = 147 +ARM64_INS_LD3 = 148 +ARM64_INS_LD4 = 149 +ARM64_INS_LD4R = 150 +ARM64_INS_LDARB = 151 +ARM64_INS_LDARH = 152 +ARM64_INS_LDAR = 153 +ARM64_INS_LDAXP = 154 +ARM64_INS_LDAXRB = 155 +ARM64_INS_LDAXRH = 156 +ARM64_INS_LDAXR = 157 +ARM64_INS_LDNP = 158 +ARM64_INS_LDP = 159 +ARM64_INS_LDPSW = 160 +ARM64_INS_LDRB = 161 +ARM64_INS_LDR = 162 +ARM64_INS_LDRH = 163 +ARM64_INS_LDRSB = 164 +ARM64_INS_LDRSH = 165 +ARM64_INS_LDRSW = 166 +ARM64_INS_LDTRB = 167 +ARM64_INS_LDTRH = 168 +ARM64_INS_LDTRSB = 169 +ARM64_INS_LDTRSH = 170 +ARM64_INS_LDTRSW = 171 +ARM64_INS_LDTR = 172 +ARM64_INS_LDURB = 173 +ARM64_INS_LDUR = 174 +ARM64_INS_LDURH = 175 +ARM64_INS_LDURSB = 176 +ARM64_INS_LDURSH = 177 +ARM64_INS_LDURSW = 178 +ARM64_INS_LDXP = 179 +ARM64_INS_LDXRB = 180 +ARM64_INS_LDXRH = 181 +ARM64_INS_LDXR = 182 +ARM64_INS_LSL = 183 +ARM64_INS_LSR = 184 +ARM64_INS_MADD = 185 +ARM64_INS_MLA = 186 +ARM64_INS_MLS = 187 +ARM64_INS_MOVI = 188 +ARM64_INS_MOVK = 189 +ARM64_INS_MOVN = 190 +ARM64_INS_MOVZ = 191 +ARM64_INS_MRS = 192 +ARM64_INS_MSR = 193 +ARM64_INS_MSUB = 194 +ARM64_INS_MUL = 195 +ARM64_INS_MVNI = 196 +ARM64_INS_NEG = 197 +ARM64_INS_NOT = 198 +ARM64_INS_ORN = 199 +ARM64_INS_ORR = 200 +ARM64_INS_PMULL2 = 201 +ARM64_INS_PMULL = 202 +ARM64_INS_PMUL = 203 +ARM64_INS_PRFM = 204 +ARM64_INS_PRFUM = 205 +ARM64_INS_RADDHN = 206 +ARM64_INS_RADDHN2 = 207 +ARM64_INS_RBIT = 208 +ARM64_INS_RET = 209 +ARM64_INS_REV16 = 210 +ARM64_INS_REV32 = 211 +ARM64_INS_REV64 = 212 +ARM64_INS_REV = 213 +ARM64_INS_ROR = 214 +ARM64_INS_RSHRN2 = 215 +ARM64_INS_RSHRN = 216 +ARM64_INS_RSUBHN = 217 +ARM64_INS_RSUBHN2 = 218 +ARM64_INS_SABAL2 = 219 +ARM64_INS_SABAL = 220 +ARM64_INS_SABA = 221 +ARM64_INS_SABDL2 = 222 +ARM64_INS_SABDL = 223 +ARM64_INS_SABD = 224 +ARM64_INS_SADALP = 225 +ARM64_INS_SADDLP = 226 +ARM64_INS_SADDLV = 227 +ARM64_INS_SADDL2 = 228 +ARM64_INS_SADDL = 229 +ARM64_INS_SADDW2 = 230 +ARM64_INS_SADDW = 231 +ARM64_INS_SBC = 232 +ARM64_INS_SBFM = 233 +ARM64_INS_SCVTF = 234 +ARM64_INS_SDIV = 235 +ARM64_INS_SHA1C = 236 +ARM64_INS_SHA1H = 237 +ARM64_INS_SHA1M = 238 +ARM64_INS_SHA1P = 239 +ARM64_INS_SHA1SU0 = 240 +ARM64_INS_SHA1SU1 = 241 +ARM64_INS_SHA256H2 = 242 +ARM64_INS_SHA256H = 243 +ARM64_INS_SHA256SU0 = 244 +ARM64_INS_SHA256SU1 = 245 +ARM64_INS_SHADD = 246 +ARM64_INS_SHLL2 = 247 +ARM64_INS_SHLL = 248 +ARM64_INS_SHL = 249 +ARM64_INS_SHRN2 = 250 +ARM64_INS_SHRN = 251 +ARM64_INS_SHSUB = 252 +ARM64_INS_SLI = 253 +ARM64_INS_SMADDL = 254 +ARM64_INS_SMAXP = 255 +ARM64_INS_SMAXV = 256 +ARM64_INS_SMAX = 257 +ARM64_INS_SMC = 258 +ARM64_INS_SMINP = 259 +ARM64_INS_SMINV = 260 +ARM64_INS_SMIN = 261 +ARM64_INS_SMLAL2 = 262 +ARM64_INS_SMLAL = 263 +ARM64_INS_SMLSL2 = 264 +ARM64_INS_SMLSL = 265 +ARM64_INS_SMOV = 266 +ARM64_INS_SMSUBL = 267 +ARM64_INS_SMULH = 268 +ARM64_INS_SMULL2 = 269 +ARM64_INS_SMULL = 270 +ARM64_INS_SQABS = 271 +ARM64_INS_SQADD = 272 +ARM64_INS_SQDMLAL = 273 +ARM64_INS_SQDMLAL2 = 274 +ARM64_INS_SQDMLSL = 275 +ARM64_INS_SQDMLSL2 = 276 +ARM64_INS_SQDMULH = 277 +ARM64_INS_SQDMULL = 278 +ARM64_INS_SQDMULL2 = 279 +ARM64_INS_SQNEG = 280 +ARM64_INS_SQRDMULH = 281 +ARM64_INS_SQRSHL = 282 +ARM64_INS_SQRSHRN = 283 +ARM64_INS_SQRSHRN2 = 284 +ARM64_INS_SQRSHRUN = 285 +ARM64_INS_SQRSHRUN2 = 286 +ARM64_INS_SQSHLU = 287 +ARM64_INS_SQSHL = 288 +ARM64_INS_SQSHRN = 289 +ARM64_INS_SQSHRN2 = 290 +ARM64_INS_SQSHRUN = 291 +ARM64_INS_SQSHRUN2 = 292 +ARM64_INS_SQSUB = 293 +ARM64_INS_SQXTN2 = 294 +ARM64_INS_SQXTN = 295 +ARM64_INS_SQXTUN2 = 296 +ARM64_INS_SQXTUN = 297 +ARM64_INS_SRHADD = 298 +ARM64_INS_SRI = 299 +ARM64_INS_SRSHL = 300 +ARM64_INS_SRSHR = 301 +ARM64_INS_SRSRA = 302 +ARM64_INS_SSHLL2 = 303 +ARM64_INS_SSHLL = 304 +ARM64_INS_SSHL = 305 +ARM64_INS_SSHR = 306 +ARM64_INS_SSRA = 307 +ARM64_INS_SSUBL2 = 308 +ARM64_INS_SSUBL = 309 +ARM64_INS_SSUBW2 = 310 +ARM64_INS_SSUBW = 311 +ARM64_INS_ST1 = 312 +ARM64_INS_ST2 = 313 +ARM64_INS_ST3 = 314 +ARM64_INS_ST4 = 315 +ARM64_INS_STLRB = 316 +ARM64_INS_STLRH = 317 +ARM64_INS_STLR = 318 +ARM64_INS_STLXP = 319 +ARM64_INS_STLXRB = 320 +ARM64_INS_STLXRH = 321 +ARM64_INS_STLXR = 322 +ARM64_INS_STNP = 323 +ARM64_INS_STP = 324 +ARM64_INS_STRB = 325 +ARM64_INS_STR = 326 +ARM64_INS_STRH = 327 +ARM64_INS_STTRB = 328 +ARM64_INS_STTRH = 329 +ARM64_INS_STTR = 330 +ARM64_INS_STURB = 331 +ARM64_INS_STUR = 332 +ARM64_INS_STURH = 333 +ARM64_INS_STXP = 334 +ARM64_INS_STXRB = 335 +ARM64_INS_STXRH = 336 +ARM64_INS_STXR = 337 +ARM64_INS_SUBHN = 338 +ARM64_INS_SUBHN2 = 339 +ARM64_INS_SUB = 340 +ARM64_INS_SUQADD = 341 +ARM64_INS_SVC = 342 +ARM64_INS_SYSL = 343 +ARM64_INS_SYS = 344 +ARM64_INS_TBL = 345 +ARM64_INS_TBNZ = 346 +ARM64_INS_TBX = 347 +ARM64_INS_TBZ = 348 +ARM64_INS_TRN1 = 349 +ARM64_INS_TRN2 = 350 +ARM64_INS_UABAL2 = 351 +ARM64_INS_UABAL = 352 +ARM64_INS_UABA = 353 +ARM64_INS_UABDL2 = 354 +ARM64_INS_UABDL = 355 +ARM64_INS_UABD = 356 +ARM64_INS_UADALP = 357 +ARM64_INS_UADDLP = 358 +ARM64_INS_UADDLV = 359 +ARM64_INS_UADDL2 = 360 +ARM64_INS_UADDL = 361 +ARM64_INS_UADDW2 = 362 +ARM64_INS_UADDW = 363 +ARM64_INS_UBFM = 364 +ARM64_INS_UCVTF = 365 +ARM64_INS_UDIV = 366 +ARM64_INS_UHADD = 367 +ARM64_INS_UHSUB = 368 +ARM64_INS_UMADDL = 369 +ARM64_INS_UMAXP = 370 +ARM64_INS_UMAXV = 371 +ARM64_INS_UMAX = 372 +ARM64_INS_UMINP = 373 +ARM64_INS_UMINV = 374 +ARM64_INS_UMIN = 375 +ARM64_INS_UMLAL2 = 376 +ARM64_INS_UMLAL = 377 +ARM64_INS_UMLSL2 = 378 +ARM64_INS_UMLSL = 379 +ARM64_INS_UMOV = 380 +ARM64_INS_UMSUBL = 381 +ARM64_INS_UMULH = 382 +ARM64_INS_UMULL2 = 383 +ARM64_INS_UMULL = 384 +ARM64_INS_UQADD = 385 +ARM64_INS_UQRSHL = 386 +ARM64_INS_UQRSHRN = 387 +ARM64_INS_UQRSHRN2 = 388 +ARM64_INS_UQSHL = 389 +ARM64_INS_UQSHRN = 390 +ARM64_INS_UQSHRN2 = 391 +ARM64_INS_UQSUB = 392 +ARM64_INS_UQXTN2 = 393 +ARM64_INS_UQXTN = 394 +ARM64_INS_URECPE = 395 +ARM64_INS_URHADD = 396 +ARM64_INS_URSHL = 397 +ARM64_INS_URSHR = 398 +ARM64_INS_URSQRTE = 399 +ARM64_INS_URSRA = 400 +ARM64_INS_USHLL2 = 401 +ARM64_INS_USHLL = 402 +ARM64_INS_USHL = 403 +ARM64_INS_USHR = 404 +ARM64_INS_USQADD = 405 +ARM64_INS_USRA = 406 +ARM64_INS_USUBL2 = 407 +ARM64_INS_USUBL = 408 +ARM64_INS_USUBW2 = 409 +ARM64_INS_USUBW = 410 +ARM64_INS_UZP1 = 411 +ARM64_INS_UZP2 = 412 +ARM64_INS_XTN2 = 413 +ARM64_INS_XTN = 414 +ARM64_INS_ZIP1 = 415 +ARM64_INS_ZIP2 = 416 +ARM64_INS_MNEG = 417 +ARM64_INS_UMNEGL = 418 +ARM64_INS_SMNEGL = 419 +ARM64_INS_NOP = 420 +ARM64_INS_YIELD = 421 +ARM64_INS_WFE = 422 +ARM64_INS_WFI = 423 +ARM64_INS_SEV = 424 +ARM64_INS_SEVL = 425 +ARM64_INS_NGC = 426 +ARM64_INS_SBFIZ = 427 +ARM64_INS_UBFIZ = 428 +ARM64_INS_SBFX = 429 +ARM64_INS_UBFX = 430 +ARM64_INS_BFI = 431 +ARM64_INS_BFXIL = 432 +ARM64_INS_CMN = 433 +ARM64_INS_MVN = 434 +ARM64_INS_TST = 435 +ARM64_INS_CSET = 436 +ARM64_INS_CINC = 437 +ARM64_INS_CSETM = 438 +ARM64_INS_CINV = 439 +ARM64_INS_CNEG = 440 +ARM64_INS_SXTB = 441 +ARM64_INS_SXTH = 442 +ARM64_INS_SXTW = 443 +ARM64_INS_CMP = 444 +ARM64_INS_UXTB = 445 +ARM64_INS_UXTH = 446 +ARM64_INS_UXTW = 447 +ARM64_INS_IC = 448 +ARM64_INS_DC = 449 +ARM64_INS_AT = 450 +ARM64_INS_TLBI = 451 +ARM64_INS_NEGS = 452 +ARM64_INS_NGCS = 453 +ARM64_INS_ENDING = 454 + +ARM64_GRP_INVALID = 0 +ARM64_GRP_JUMP = 1 +ARM64_GRP_CALL = 2 +ARM64_GRP_RET = 3 +ARM64_GRP_INT = 4 +ARM64_GRP_PRIVILEGE = 6 +ARM64_GRP_BRANCH_RELATIVE = 7 +ARM64_GRP_CRYPTO = 128 +ARM64_GRP_FPARMV8 = 129 +ARM64_GRP_NEON = 130 +ARM64_GRP_CRC = 131 +ARM64_GRP_ENDING = 132 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/arm_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/arm_const.py new file mode 100644 index 0000000..6149dcb --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/arm_const.py @@ -0,0 +1,775 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py] + +ARM_SFT_INVALID = 0 +ARM_SFT_ASR = 1 +ARM_SFT_LSL = 2 +ARM_SFT_LSR = 3 +ARM_SFT_ROR = 4 +ARM_SFT_RRX = 5 +ARM_SFT_ASR_REG = 6 +ARM_SFT_LSL_REG = 7 +ARM_SFT_LSR_REG = 8 +ARM_SFT_ROR_REG = 9 +ARM_SFT_RRX_REG = 10 + +ARM_CC_INVALID = 0 +ARM_CC_EQ = 1 +ARM_CC_NE = 2 +ARM_CC_HS = 3 +ARM_CC_LO = 4 +ARM_CC_MI = 5 +ARM_CC_PL = 6 +ARM_CC_VS = 7 +ARM_CC_VC = 8 +ARM_CC_HI = 9 +ARM_CC_LS = 10 +ARM_CC_GE = 11 +ARM_CC_LT = 12 +ARM_CC_GT = 13 +ARM_CC_LE = 14 +ARM_CC_AL = 15 + +ARM_SYSREG_INVALID = 0 +ARM_SYSREG_SPSR_C = 1 +ARM_SYSREG_SPSR_X = 2 +ARM_SYSREG_SPSR_S = 4 +ARM_SYSREG_SPSR_F = 8 +ARM_SYSREG_CPSR_C = 16 +ARM_SYSREG_CPSR_X = 32 +ARM_SYSREG_CPSR_S = 64 +ARM_SYSREG_CPSR_F = 128 +ARM_SYSREG_APSR = 256 +ARM_SYSREG_APSR_G = 257 +ARM_SYSREG_APSR_NZCVQ = 258 +ARM_SYSREG_APSR_NZCVQG = 259 +ARM_SYSREG_IAPSR = 260 +ARM_SYSREG_IAPSR_G = 261 +ARM_SYSREG_IAPSR_NZCVQG = 262 +ARM_SYSREG_IAPSR_NZCVQ = 263 +ARM_SYSREG_EAPSR = 264 +ARM_SYSREG_EAPSR_G = 265 +ARM_SYSREG_EAPSR_NZCVQG = 266 +ARM_SYSREG_EAPSR_NZCVQ = 267 +ARM_SYSREG_XPSR = 268 +ARM_SYSREG_XPSR_G = 269 +ARM_SYSREG_XPSR_NZCVQG = 270 +ARM_SYSREG_XPSR_NZCVQ = 271 +ARM_SYSREG_IPSR = 272 +ARM_SYSREG_EPSR = 273 +ARM_SYSREG_IEPSR = 274 +ARM_SYSREG_MSP = 275 +ARM_SYSREG_PSP = 276 +ARM_SYSREG_PRIMASK = 277 +ARM_SYSREG_BASEPRI = 278 +ARM_SYSREG_BASEPRI_MAX = 279 +ARM_SYSREG_FAULTMASK = 280 +ARM_SYSREG_CONTROL = 281 +ARM_SYSREG_R8_USR = 282 +ARM_SYSREG_R9_USR = 283 +ARM_SYSREG_R10_USR = 284 +ARM_SYSREG_R11_USR = 285 +ARM_SYSREG_R12_USR = 286 +ARM_SYSREG_SP_USR = 287 +ARM_SYSREG_LR_USR = 288 +ARM_SYSREG_R8_FIQ = 289 +ARM_SYSREG_R9_FIQ = 290 +ARM_SYSREG_R10_FIQ = 291 +ARM_SYSREG_R11_FIQ = 292 +ARM_SYSREG_R12_FIQ = 293 +ARM_SYSREG_SP_FIQ = 294 +ARM_SYSREG_LR_FIQ = 295 +ARM_SYSREG_LR_IRQ = 296 +ARM_SYSREG_SP_IRQ = 297 +ARM_SYSREG_LR_SVC = 298 +ARM_SYSREG_SP_SVC = 299 +ARM_SYSREG_LR_ABT = 300 +ARM_SYSREG_SP_ABT = 301 +ARM_SYSREG_LR_UND = 302 +ARM_SYSREG_SP_UND = 303 +ARM_SYSREG_LR_MON = 304 +ARM_SYSREG_SP_MON = 305 +ARM_SYSREG_ELR_HYP = 306 +ARM_SYSREG_SP_HYP = 307 +ARM_SYSREG_SPSR_FIQ = 308 +ARM_SYSREG_SPSR_IRQ = 309 +ARM_SYSREG_SPSR_SVC = 310 +ARM_SYSREG_SPSR_ABT = 311 +ARM_SYSREG_SPSR_UND = 312 +ARM_SYSREG_SPSR_MON = 313 +ARM_SYSREG_SPSR_HYP = 314 + +ARM_MB_INVALID = 0 +ARM_MB_RESERVED_0 = 1 +ARM_MB_OSHLD = 2 +ARM_MB_OSHST = 3 +ARM_MB_OSH = 4 +ARM_MB_RESERVED_4 = 5 +ARM_MB_NSHLD = 6 +ARM_MB_NSHST = 7 +ARM_MB_NSH = 8 +ARM_MB_RESERVED_8 = 9 +ARM_MB_ISHLD = 10 +ARM_MB_ISHST = 11 +ARM_MB_ISH = 12 +ARM_MB_RESERVED_12 = 13 +ARM_MB_LD = 14 +ARM_MB_ST = 15 +ARM_MB_SY = 16 + +ARM_OP_INVALID = 0 +ARM_OP_REG = 1 +ARM_OP_IMM = 2 +ARM_OP_MEM = 3 +ARM_OP_FP = 4 +ARM_OP_CIMM = 64 +ARM_OP_PIMM = 65 +ARM_OP_SETEND = 66 +ARM_OP_SYSREG = 67 + +ARM_SETEND_INVALID = 0 +ARM_SETEND_BE = 1 +ARM_SETEND_LE = 2 + +ARM_CPSMODE_INVALID = 0 +ARM_CPSMODE_IE = 2 +ARM_CPSMODE_ID = 3 + +ARM_CPSFLAG_INVALID = 0 +ARM_CPSFLAG_F = 1 +ARM_CPSFLAG_I = 2 +ARM_CPSFLAG_A = 4 +ARM_CPSFLAG_NONE = 16 + +ARM_VECTORDATA_INVALID = 0 +ARM_VECTORDATA_I8 = 1 +ARM_VECTORDATA_I16 = 2 +ARM_VECTORDATA_I32 = 3 +ARM_VECTORDATA_I64 = 4 +ARM_VECTORDATA_S8 = 5 +ARM_VECTORDATA_S16 = 6 +ARM_VECTORDATA_S32 = 7 +ARM_VECTORDATA_S64 = 8 +ARM_VECTORDATA_U8 = 9 +ARM_VECTORDATA_U16 = 10 +ARM_VECTORDATA_U32 = 11 +ARM_VECTORDATA_U64 = 12 +ARM_VECTORDATA_P8 = 13 +ARM_VECTORDATA_F32 = 14 +ARM_VECTORDATA_F64 = 15 +ARM_VECTORDATA_F16F64 = 16 +ARM_VECTORDATA_F64F16 = 17 +ARM_VECTORDATA_F32F16 = 18 +ARM_VECTORDATA_F16F32 = 19 +ARM_VECTORDATA_F64F32 = 20 +ARM_VECTORDATA_F32F64 = 21 +ARM_VECTORDATA_S32F32 = 22 +ARM_VECTORDATA_U32F32 = 23 +ARM_VECTORDATA_F32S32 = 24 +ARM_VECTORDATA_F32U32 = 25 +ARM_VECTORDATA_F64S16 = 26 +ARM_VECTORDATA_F32S16 = 27 +ARM_VECTORDATA_F64S32 = 28 +ARM_VECTORDATA_S16F64 = 29 +ARM_VECTORDATA_S16F32 = 30 +ARM_VECTORDATA_S32F64 = 31 +ARM_VECTORDATA_U16F64 = 32 +ARM_VECTORDATA_U16F32 = 33 +ARM_VECTORDATA_U32F64 = 34 +ARM_VECTORDATA_F64U16 = 35 +ARM_VECTORDATA_F32U16 = 36 +ARM_VECTORDATA_F64U32 = 37 + +ARM_REG_INVALID = 0 +ARM_REG_APSR = 1 +ARM_REG_APSR_NZCV = 2 +ARM_REG_CPSR = 3 +ARM_REG_FPEXC = 4 +ARM_REG_FPINST = 5 +ARM_REG_FPSCR = 6 +ARM_REG_FPSCR_NZCV = 7 +ARM_REG_FPSID = 8 +ARM_REG_ITSTATE = 9 +ARM_REG_LR = 10 +ARM_REG_PC = 11 +ARM_REG_SP = 12 +ARM_REG_SPSR = 13 +ARM_REG_D0 = 14 +ARM_REG_D1 = 15 +ARM_REG_D2 = 16 +ARM_REG_D3 = 17 +ARM_REG_D4 = 18 +ARM_REG_D5 = 19 +ARM_REG_D6 = 20 +ARM_REG_D7 = 21 +ARM_REG_D8 = 22 +ARM_REG_D9 = 23 +ARM_REG_D10 = 24 +ARM_REG_D11 = 25 +ARM_REG_D12 = 26 +ARM_REG_D13 = 27 +ARM_REG_D14 = 28 +ARM_REG_D15 = 29 +ARM_REG_D16 = 30 +ARM_REG_D17 = 31 +ARM_REG_D18 = 32 +ARM_REG_D19 = 33 +ARM_REG_D20 = 34 +ARM_REG_D21 = 35 +ARM_REG_D22 = 36 +ARM_REG_D23 = 37 +ARM_REG_D24 = 38 +ARM_REG_D25 = 39 +ARM_REG_D26 = 40 +ARM_REG_D27 = 41 +ARM_REG_D28 = 42 +ARM_REG_D29 = 43 +ARM_REG_D30 = 44 +ARM_REG_D31 = 45 +ARM_REG_FPINST2 = 46 +ARM_REG_MVFR0 = 47 +ARM_REG_MVFR1 = 48 +ARM_REG_MVFR2 = 49 +ARM_REG_Q0 = 50 +ARM_REG_Q1 = 51 +ARM_REG_Q2 = 52 +ARM_REG_Q3 = 53 +ARM_REG_Q4 = 54 +ARM_REG_Q5 = 55 +ARM_REG_Q6 = 56 +ARM_REG_Q7 = 57 +ARM_REG_Q8 = 58 +ARM_REG_Q9 = 59 +ARM_REG_Q10 = 60 +ARM_REG_Q11 = 61 +ARM_REG_Q12 = 62 +ARM_REG_Q13 = 63 +ARM_REG_Q14 = 64 +ARM_REG_Q15 = 65 +ARM_REG_R0 = 66 +ARM_REG_R1 = 67 +ARM_REG_R2 = 68 +ARM_REG_R3 = 69 +ARM_REG_R4 = 70 +ARM_REG_R5 = 71 +ARM_REG_R6 = 72 +ARM_REG_R7 = 73 +ARM_REG_R8 = 74 +ARM_REG_R9 = 75 +ARM_REG_R10 = 76 +ARM_REG_R11 = 77 +ARM_REG_R12 = 78 +ARM_REG_S0 = 79 +ARM_REG_S1 = 80 +ARM_REG_S2 = 81 +ARM_REG_S3 = 82 +ARM_REG_S4 = 83 +ARM_REG_S5 = 84 +ARM_REG_S6 = 85 +ARM_REG_S7 = 86 +ARM_REG_S8 = 87 +ARM_REG_S9 = 88 +ARM_REG_S10 = 89 +ARM_REG_S11 = 90 +ARM_REG_S12 = 91 +ARM_REG_S13 = 92 +ARM_REG_S14 = 93 +ARM_REG_S15 = 94 +ARM_REG_S16 = 95 +ARM_REG_S17 = 96 +ARM_REG_S18 = 97 +ARM_REG_S19 = 98 +ARM_REG_S20 = 99 +ARM_REG_S21 = 100 +ARM_REG_S22 = 101 +ARM_REG_S23 = 102 +ARM_REG_S24 = 103 +ARM_REG_S25 = 104 +ARM_REG_S26 = 105 +ARM_REG_S27 = 106 +ARM_REG_S28 = 107 +ARM_REG_S29 = 108 +ARM_REG_S30 = 109 +ARM_REG_S31 = 110 +ARM_REG_ENDING = 111 +ARM_REG_R13 = ARM_REG_SP +ARM_REG_R14 = ARM_REG_LR +ARM_REG_R15 = ARM_REG_PC +ARM_REG_SB = ARM_REG_R9 +ARM_REG_SL = ARM_REG_R10 +ARM_REG_FP = ARM_REG_R11 +ARM_REG_IP = ARM_REG_R12 + +ARM_INS_INVALID = 0 +ARM_INS_ADC = 1 +ARM_INS_ADD = 2 +ARM_INS_ADR = 3 +ARM_INS_AESD = 4 +ARM_INS_AESE = 5 +ARM_INS_AESIMC = 6 +ARM_INS_AESMC = 7 +ARM_INS_AND = 8 +ARM_INS_BFC = 9 +ARM_INS_BFI = 10 +ARM_INS_BIC = 11 +ARM_INS_BKPT = 12 +ARM_INS_BL = 13 +ARM_INS_BLX = 14 +ARM_INS_BX = 15 +ARM_INS_BXJ = 16 +ARM_INS_B = 17 +ARM_INS_CDP = 18 +ARM_INS_CDP2 = 19 +ARM_INS_CLREX = 20 +ARM_INS_CLZ = 21 +ARM_INS_CMN = 22 +ARM_INS_CMP = 23 +ARM_INS_CPS = 24 +ARM_INS_CRC32B = 25 +ARM_INS_CRC32CB = 26 +ARM_INS_CRC32CH = 27 +ARM_INS_CRC32CW = 28 +ARM_INS_CRC32H = 29 +ARM_INS_CRC32W = 30 +ARM_INS_DBG = 31 +ARM_INS_DMB = 32 +ARM_INS_DSB = 33 +ARM_INS_EOR = 34 +ARM_INS_ERET = 35 +ARM_INS_VMOV = 36 +ARM_INS_FLDMDBX = 37 +ARM_INS_FLDMIAX = 38 +ARM_INS_VMRS = 39 +ARM_INS_FSTMDBX = 40 +ARM_INS_FSTMIAX = 41 +ARM_INS_HINT = 42 +ARM_INS_HLT = 43 +ARM_INS_HVC = 44 +ARM_INS_ISB = 45 +ARM_INS_LDA = 46 +ARM_INS_LDAB = 47 +ARM_INS_LDAEX = 48 +ARM_INS_LDAEXB = 49 +ARM_INS_LDAEXD = 50 +ARM_INS_LDAEXH = 51 +ARM_INS_LDAH = 52 +ARM_INS_LDC2L = 53 +ARM_INS_LDC2 = 54 +ARM_INS_LDCL = 55 +ARM_INS_LDC = 56 +ARM_INS_LDMDA = 57 +ARM_INS_LDMDB = 58 +ARM_INS_LDM = 59 +ARM_INS_LDMIB = 60 +ARM_INS_LDRBT = 61 +ARM_INS_LDRB = 62 +ARM_INS_LDRD = 63 +ARM_INS_LDREX = 64 +ARM_INS_LDREXB = 65 +ARM_INS_LDREXD = 66 +ARM_INS_LDREXH = 67 +ARM_INS_LDRH = 68 +ARM_INS_LDRHT = 69 +ARM_INS_LDRSB = 70 +ARM_INS_LDRSBT = 71 +ARM_INS_LDRSH = 72 +ARM_INS_LDRSHT = 73 +ARM_INS_LDRT = 74 +ARM_INS_LDR = 75 +ARM_INS_MCR = 76 +ARM_INS_MCR2 = 77 +ARM_INS_MCRR = 78 +ARM_INS_MCRR2 = 79 +ARM_INS_MLA = 80 +ARM_INS_MLS = 81 +ARM_INS_MOV = 82 +ARM_INS_MOVT = 83 +ARM_INS_MOVW = 84 +ARM_INS_MRC = 85 +ARM_INS_MRC2 = 86 +ARM_INS_MRRC = 87 +ARM_INS_MRRC2 = 88 +ARM_INS_MRS = 89 +ARM_INS_MSR = 90 +ARM_INS_MUL = 91 +ARM_INS_MVN = 92 +ARM_INS_ORR = 93 +ARM_INS_PKHBT = 94 +ARM_INS_PKHTB = 95 +ARM_INS_PLDW = 96 +ARM_INS_PLD = 97 +ARM_INS_PLI = 98 +ARM_INS_QADD = 99 +ARM_INS_QADD16 = 100 +ARM_INS_QADD8 = 101 +ARM_INS_QASX = 102 +ARM_INS_QDADD = 103 +ARM_INS_QDSUB = 104 +ARM_INS_QSAX = 105 +ARM_INS_QSUB = 106 +ARM_INS_QSUB16 = 107 +ARM_INS_QSUB8 = 108 +ARM_INS_RBIT = 109 +ARM_INS_REV = 110 +ARM_INS_REV16 = 111 +ARM_INS_REVSH = 112 +ARM_INS_RFEDA = 113 +ARM_INS_RFEDB = 114 +ARM_INS_RFEIA = 115 +ARM_INS_RFEIB = 116 +ARM_INS_RSB = 117 +ARM_INS_RSC = 118 +ARM_INS_SADD16 = 119 +ARM_INS_SADD8 = 120 +ARM_INS_SASX = 121 +ARM_INS_SBC = 122 +ARM_INS_SBFX = 123 +ARM_INS_SDIV = 124 +ARM_INS_SEL = 125 +ARM_INS_SETEND = 126 +ARM_INS_SHA1C = 127 +ARM_INS_SHA1H = 128 +ARM_INS_SHA1M = 129 +ARM_INS_SHA1P = 130 +ARM_INS_SHA1SU0 = 131 +ARM_INS_SHA1SU1 = 132 +ARM_INS_SHA256H = 133 +ARM_INS_SHA256H2 = 134 +ARM_INS_SHA256SU0 = 135 +ARM_INS_SHA256SU1 = 136 +ARM_INS_SHADD16 = 137 +ARM_INS_SHADD8 = 138 +ARM_INS_SHASX = 139 +ARM_INS_SHSAX = 140 +ARM_INS_SHSUB16 = 141 +ARM_INS_SHSUB8 = 142 +ARM_INS_SMC = 143 +ARM_INS_SMLABB = 144 +ARM_INS_SMLABT = 145 +ARM_INS_SMLAD = 146 +ARM_INS_SMLADX = 147 +ARM_INS_SMLAL = 148 +ARM_INS_SMLALBB = 149 +ARM_INS_SMLALBT = 150 +ARM_INS_SMLALD = 151 +ARM_INS_SMLALDX = 152 +ARM_INS_SMLALTB = 153 +ARM_INS_SMLALTT = 154 +ARM_INS_SMLATB = 155 +ARM_INS_SMLATT = 156 +ARM_INS_SMLAWB = 157 +ARM_INS_SMLAWT = 158 +ARM_INS_SMLSD = 159 +ARM_INS_SMLSDX = 160 +ARM_INS_SMLSLD = 161 +ARM_INS_SMLSLDX = 162 +ARM_INS_SMMLA = 163 +ARM_INS_SMMLAR = 164 +ARM_INS_SMMLS = 165 +ARM_INS_SMMLSR = 166 +ARM_INS_SMMUL = 167 +ARM_INS_SMMULR = 168 +ARM_INS_SMUAD = 169 +ARM_INS_SMUADX = 170 +ARM_INS_SMULBB = 171 +ARM_INS_SMULBT = 172 +ARM_INS_SMULL = 173 +ARM_INS_SMULTB = 174 +ARM_INS_SMULTT = 175 +ARM_INS_SMULWB = 176 +ARM_INS_SMULWT = 177 +ARM_INS_SMUSD = 178 +ARM_INS_SMUSDX = 179 +ARM_INS_SRSDA = 180 +ARM_INS_SRSDB = 181 +ARM_INS_SRSIA = 182 +ARM_INS_SRSIB = 183 +ARM_INS_SSAT = 184 +ARM_INS_SSAT16 = 185 +ARM_INS_SSAX = 186 +ARM_INS_SSUB16 = 187 +ARM_INS_SSUB8 = 188 +ARM_INS_STC2L = 189 +ARM_INS_STC2 = 190 +ARM_INS_STCL = 191 +ARM_INS_STC = 192 +ARM_INS_STL = 193 +ARM_INS_STLB = 194 +ARM_INS_STLEX = 195 +ARM_INS_STLEXB = 196 +ARM_INS_STLEXD = 197 +ARM_INS_STLEXH = 198 +ARM_INS_STLH = 199 +ARM_INS_STMDA = 200 +ARM_INS_STMDB = 201 +ARM_INS_STM = 202 +ARM_INS_STMIB = 203 +ARM_INS_STRBT = 204 +ARM_INS_STRB = 205 +ARM_INS_STRD = 206 +ARM_INS_STREX = 207 +ARM_INS_STREXB = 208 +ARM_INS_STREXD = 209 +ARM_INS_STREXH = 210 +ARM_INS_STRH = 211 +ARM_INS_STRHT = 212 +ARM_INS_STRT = 213 +ARM_INS_STR = 214 +ARM_INS_SUB = 215 +ARM_INS_SVC = 216 +ARM_INS_SWP = 217 +ARM_INS_SWPB = 218 +ARM_INS_SXTAB = 219 +ARM_INS_SXTAB16 = 220 +ARM_INS_SXTAH = 221 +ARM_INS_SXTB = 222 +ARM_INS_SXTB16 = 223 +ARM_INS_SXTH = 224 +ARM_INS_TEQ = 225 +ARM_INS_TRAP = 226 +ARM_INS_TST = 227 +ARM_INS_UADD16 = 228 +ARM_INS_UADD8 = 229 +ARM_INS_UASX = 230 +ARM_INS_UBFX = 231 +ARM_INS_UDF = 232 +ARM_INS_UDIV = 233 +ARM_INS_UHADD16 = 234 +ARM_INS_UHADD8 = 235 +ARM_INS_UHASX = 236 +ARM_INS_UHSAX = 237 +ARM_INS_UHSUB16 = 238 +ARM_INS_UHSUB8 = 239 +ARM_INS_UMAAL = 240 +ARM_INS_UMLAL = 241 +ARM_INS_UMULL = 242 +ARM_INS_UQADD16 = 243 +ARM_INS_UQADD8 = 244 +ARM_INS_UQASX = 245 +ARM_INS_UQSAX = 246 +ARM_INS_UQSUB16 = 247 +ARM_INS_UQSUB8 = 248 +ARM_INS_USAD8 = 249 +ARM_INS_USADA8 = 250 +ARM_INS_USAT = 251 +ARM_INS_USAT16 = 252 +ARM_INS_USAX = 253 +ARM_INS_USUB16 = 254 +ARM_INS_USUB8 = 255 +ARM_INS_UXTAB = 256 +ARM_INS_UXTAB16 = 257 +ARM_INS_UXTAH = 258 +ARM_INS_UXTB = 259 +ARM_INS_UXTB16 = 260 +ARM_INS_UXTH = 261 +ARM_INS_VABAL = 262 +ARM_INS_VABA = 263 +ARM_INS_VABDL = 264 +ARM_INS_VABD = 265 +ARM_INS_VABS = 266 +ARM_INS_VACGE = 267 +ARM_INS_VACGT = 268 +ARM_INS_VADD = 269 +ARM_INS_VADDHN = 270 +ARM_INS_VADDL = 271 +ARM_INS_VADDW = 272 +ARM_INS_VAND = 273 +ARM_INS_VBIC = 274 +ARM_INS_VBIF = 275 +ARM_INS_VBIT = 276 +ARM_INS_VBSL = 277 +ARM_INS_VCEQ = 278 +ARM_INS_VCGE = 279 +ARM_INS_VCGT = 280 +ARM_INS_VCLE = 281 +ARM_INS_VCLS = 282 +ARM_INS_VCLT = 283 +ARM_INS_VCLZ = 284 +ARM_INS_VCMP = 285 +ARM_INS_VCMPE = 286 +ARM_INS_VCNT = 287 +ARM_INS_VCVTA = 288 +ARM_INS_VCVTB = 289 +ARM_INS_VCVT = 290 +ARM_INS_VCVTM = 291 +ARM_INS_VCVTN = 292 +ARM_INS_VCVTP = 293 +ARM_INS_VCVTT = 294 +ARM_INS_VDIV = 295 +ARM_INS_VDUP = 296 +ARM_INS_VEOR = 297 +ARM_INS_VEXT = 298 +ARM_INS_VFMA = 299 +ARM_INS_VFMS = 300 +ARM_INS_VFNMA = 301 +ARM_INS_VFNMS = 302 +ARM_INS_VHADD = 303 +ARM_INS_VHSUB = 304 +ARM_INS_VLD1 = 305 +ARM_INS_VLD2 = 306 +ARM_INS_VLD3 = 307 +ARM_INS_VLD4 = 308 +ARM_INS_VLDMDB = 309 +ARM_INS_VLDMIA = 310 +ARM_INS_VLDR = 311 +ARM_INS_VMAXNM = 312 +ARM_INS_VMAX = 313 +ARM_INS_VMINNM = 314 +ARM_INS_VMIN = 315 +ARM_INS_VMLA = 316 +ARM_INS_VMLAL = 317 +ARM_INS_VMLS = 318 +ARM_INS_VMLSL = 319 +ARM_INS_VMOVL = 320 +ARM_INS_VMOVN = 321 +ARM_INS_VMSR = 322 +ARM_INS_VMUL = 323 +ARM_INS_VMULL = 324 +ARM_INS_VMVN = 325 +ARM_INS_VNEG = 326 +ARM_INS_VNMLA = 327 +ARM_INS_VNMLS = 328 +ARM_INS_VNMUL = 329 +ARM_INS_VORN = 330 +ARM_INS_VORR = 331 +ARM_INS_VPADAL = 332 +ARM_INS_VPADDL = 333 +ARM_INS_VPADD = 334 +ARM_INS_VPMAX = 335 +ARM_INS_VPMIN = 336 +ARM_INS_VQABS = 337 +ARM_INS_VQADD = 338 +ARM_INS_VQDMLAL = 339 +ARM_INS_VQDMLSL = 340 +ARM_INS_VQDMULH = 341 +ARM_INS_VQDMULL = 342 +ARM_INS_VQMOVUN = 343 +ARM_INS_VQMOVN = 344 +ARM_INS_VQNEG = 345 +ARM_INS_VQRDMULH = 346 +ARM_INS_VQRSHL = 347 +ARM_INS_VQRSHRN = 348 +ARM_INS_VQRSHRUN = 349 +ARM_INS_VQSHL = 350 +ARM_INS_VQSHLU = 351 +ARM_INS_VQSHRN = 352 +ARM_INS_VQSHRUN = 353 +ARM_INS_VQSUB = 354 +ARM_INS_VRADDHN = 355 +ARM_INS_VRECPE = 356 +ARM_INS_VRECPS = 357 +ARM_INS_VREV16 = 358 +ARM_INS_VREV32 = 359 +ARM_INS_VREV64 = 360 +ARM_INS_VRHADD = 361 +ARM_INS_VRINTA = 362 +ARM_INS_VRINTM = 363 +ARM_INS_VRINTN = 364 +ARM_INS_VRINTP = 365 +ARM_INS_VRINTR = 366 +ARM_INS_VRINTX = 367 +ARM_INS_VRINTZ = 368 +ARM_INS_VRSHL = 369 +ARM_INS_VRSHRN = 370 +ARM_INS_VRSHR = 371 +ARM_INS_VRSQRTE = 372 +ARM_INS_VRSQRTS = 373 +ARM_INS_VRSRA = 374 +ARM_INS_VRSUBHN = 375 +ARM_INS_VSELEQ = 376 +ARM_INS_VSELGE = 377 +ARM_INS_VSELGT = 378 +ARM_INS_VSELVS = 379 +ARM_INS_VSHLL = 380 +ARM_INS_VSHL = 381 +ARM_INS_VSHRN = 382 +ARM_INS_VSHR = 383 +ARM_INS_VSLI = 384 +ARM_INS_VSQRT = 385 +ARM_INS_VSRA = 386 +ARM_INS_VSRI = 387 +ARM_INS_VST1 = 388 +ARM_INS_VST2 = 389 +ARM_INS_VST3 = 390 +ARM_INS_VST4 = 391 +ARM_INS_VSTMDB = 392 +ARM_INS_VSTMIA = 393 +ARM_INS_VSTR = 394 +ARM_INS_VSUB = 395 +ARM_INS_VSUBHN = 396 +ARM_INS_VSUBL = 397 +ARM_INS_VSUBW = 398 +ARM_INS_VSWP = 399 +ARM_INS_VTBL = 400 +ARM_INS_VTBX = 401 +ARM_INS_VCVTR = 402 +ARM_INS_VTRN = 403 +ARM_INS_VTST = 404 +ARM_INS_VUZP = 405 +ARM_INS_VZIP = 406 +ARM_INS_ADDW = 407 +ARM_INS_ASR = 408 +ARM_INS_DCPS1 = 409 +ARM_INS_DCPS2 = 410 +ARM_INS_DCPS3 = 411 +ARM_INS_IT = 412 +ARM_INS_LSL = 413 +ARM_INS_LSR = 414 +ARM_INS_ORN = 415 +ARM_INS_ROR = 416 +ARM_INS_RRX = 417 +ARM_INS_SUBW = 418 +ARM_INS_TBB = 419 +ARM_INS_TBH = 420 +ARM_INS_CBNZ = 421 +ARM_INS_CBZ = 422 +ARM_INS_POP = 423 +ARM_INS_PUSH = 424 +ARM_INS_NOP = 425 +ARM_INS_YIELD = 426 +ARM_INS_WFE = 427 +ARM_INS_WFI = 428 +ARM_INS_SEV = 429 +ARM_INS_SEVL = 430 +ARM_INS_VPUSH = 431 +ARM_INS_VPOP = 432 +ARM_INS_ENDING = 433 + +ARM_GRP_INVALID = 0 +ARM_GRP_JUMP = 1 +ARM_GRP_CALL = 2 +ARM_GRP_INT = 4 +ARM_GRP_PRIVILEGE = 6 +ARM_GRP_BRANCH_RELATIVE = 7 +ARM_GRP_CRYPTO = 128 +ARM_GRP_DATABARRIER = 129 +ARM_GRP_DIVIDE = 130 +ARM_GRP_FPARMV8 = 131 +ARM_GRP_MULTPRO = 132 +ARM_GRP_NEON = 133 +ARM_GRP_T2EXTRACTPACK = 134 +ARM_GRP_THUMB2DSP = 135 +ARM_GRP_TRUSTZONE = 136 +ARM_GRP_V4T = 137 +ARM_GRP_V5T = 138 +ARM_GRP_V5TE = 139 +ARM_GRP_V6 = 140 +ARM_GRP_V6T2 = 141 +ARM_GRP_V7 = 142 +ARM_GRP_V8 = 143 +ARM_GRP_VFP2 = 144 +ARM_GRP_VFP3 = 145 +ARM_GRP_VFP4 = 146 +ARM_GRP_ARM = 147 +ARM_GRP_MCLASS = 148 +ARM_GRP_NOTMCLASS = 149 +ARM_GRP_THUMB = 150 +ARM_GRP_THUMB1ONLY = 151 +ARM_GRP_THUMB2 = 152 +ARM_GRP_PREV8 = 153 +ARM_GRP_FPVMLX = 154 +ARM_GRP_MULOPS = 155 +ARM_GRP_CRC = 156 +ARM_GRP_DPVFP = 157 +ARM_GRP_V6M = 158 +ARM_GRP_VIRTUALIZATION = 159 +ARM_GRP_ENDING = 160 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/evm.py b/white_patch_detect/capstone-master/bindings/python/capstone/evm.py new file mode 100644 index 0000000..5ddec6a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/evm.py @@ -0,0 +1,17 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .evm_const import * + +# define the API +class CsEvm(ctypes.Structure): + _fields_ = ( + ('pop', ctypes.c_byte), + ('push', ctypes.c_byte), + ('fee', ctypes.c_uint), + ) + +def get_arch_info(a): + return (a.pop, a.push, a.fee) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/evm_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/evm_const.py new file mode 100644 index 0000000..6bd0e5a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/evm_const.py @@ -0,0 +1,151 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py] + +EVM_INS_STOP = 0 +EVM_INS_ADD = 1 +EVM_INS_MUL = 2 +EVM_INS_SUB = 3 +EVM_INS_DIV = 4 +EVM_INS_SDIV = 5 +EVM_INS_MOD = 6 +EVM_INS_SMOD = 7 +EVM_INS_ADDMOD = 8 +EVM_INS_MULMOD = 9 +EVM_INS_EXP = 10 +EVM_INS_SIGNEXTEND = 11 +EVM_INS_LT = 16 +EVM_INS_GT = 17 +EVM_INS_SLT = 18 +EVM_INS_SGT = 19 +EVM_INS_EQ = 20 +EVM_INS_ISZERO = 21 +EVM_INS_AND = 22 +EVM_INS_OR = 23 +EVM_INS_XOR = 24 +EVM_INS_NOT = 25 +EVM_INS_BYTE = 26 +EVM_INS_SHA3 = 32 +EVM_INS_ADDRESS = 48 +EVM_INS_BALANCE = 49 +EVM_INS_ORIGIN = 50 +EVM_INS_CALLER = 51 +EVM_INS_CALLVALUE = 52 +EVM_INS_CALLDATALOAD = 53 +EVM_INS_CALLDATASIZE = 54 +EVM_INS_CALLDATACOPY = 55 +EVM_INS_CODESIZE = 56 +EVM_INS_CODECOPY = 57 +EVM_INS_GASPRICE = 58 +EVM_INS_EXTCODESIZE = 59 +EVM_INS_EXTCODECOPY = 60 +EVM_INS_RETURNDATASIZE = 61 +EVM_INS_RETURNDATACOPY = 62 +EVM_INS_BLOCKHASH = 64 +EVM_INS_COINBASE = 65 +EVM_INS_TIMESTAMP = 66 +EVM_INS_NUMBER = 67 +EVM_INS_DIFFICULTY = 68 +EVM_INS_GASLIMIT = 69 +EVM_INS_POP = 80 +EVM_INS_MLOAD = 81 +EVM_INS_MSTORE = 82 +EVM_INS_MSTORE8 = 83 +EVM_INS_SLOAD = 84 +EVM_INS_SSTORE = 85 +EVM_INS_JUMP = 86 +EVM_INS_JUMPI = 87 +EVM_INS_PC = 88 +EVM_INS_MSIZE = 89 +EVM_INS_GAS = 90 +EVM_INS_JUMPDEST = 91 +EVM_INS_PUSH1 = 96 +EVM_INS_PUSH2 = 97 +EVM_INS_PUSH3 = 98 +EVM_INS_PUSH4 = 99 +EVM_INS_PUSH5 = 100 +EVM_INS_PUSH6 = 101 +EVM_INS_PUSH7 = 102 +EVM_INS_PUSH8 = 103 +EVM_INS_PUSH9 = 104 +EVM_INS_PUSH10 = 105 +EVM_INS_PUSH11 = 106 +EVM_INS_PUSH12 = 107 +EVM_INS_PUSH13 = 108 +EVM_INS_PUSH14 = 109 +EVM_INS_PUSH15 = 110 +EVM_INS_PUSH16 = 111 +EVM_INS_PUSH17 = 112 +EVM_INS_PUSH18 = 113 +EVM_INS_PUSH19 = 114 +EVM_INS_PUSH20 = 115 +EVM_INS_PUSH21 = 116 +EVM_INS_PUSH22 = 117 +EVM_INS_PUSH23 = 118 +EVM_INS_PUSH24 = 119 +EVM_INS_PUSH25 = 120 +EVM_INS_PUSH26 = 121 +EVM_INS_PUSH27 = 122 +EVM_INS_PUSH28 = 123 +EVM_INS_PUSH29 = 124 +EVM_INS_PUSH30 = 125 +EVM_INS_PUSH31 = 126 +EVM_INS_PUSH32 = 127 +EVM_INS_DUP1 = 128 +EVM_INS_DUP2 = 129 +EVM_INS_DUP3 = 130 +EVM_INS_DUP4 = 131 +EVM_INS_DUP5 = 132 +EVM_INS_DUP6 = 133 +EVM_INS_DUP7 = 134 +EVM_INS_DUP8 = 135 +EVM_INS_DUP9 = 136 +EVM_INS_DUP10 = 137 +EVM_INS_DUP11 = 138 +EVM_INS_DUP12 = 139 +EVM_INS_DUP13 = 140 +EVM_INS_DUP14 = 141 +EVM_INS_DUP15 = 142 +EVM_INS_DUP16 = 143 +EVM_INS_SWAP1 = 144 +EVM_INS_SWAP2 = 145 +EVM_INS_SWAP3 = 146 +EVM_INS_SWAP4 = 147 +EVM_INS_SWAP5 = 148 +EVM_INS_SWAP6 = 149 +EVM_INS_SWAP7 = 150 +EVM_INS_SWAP8 = 151 +EVM_INS_SWAP9 = 152 +EVM_INS_SWAP10 = 153 +EVM_INS_SWAP11 = 154 +EVM_INS_SWAP12 = 155 +EVM_INS_SWAP13 = 156 +EVM_INS_SWAP14 = 157 +EVM_INS_SWAP15 = 158 +EVM_INS_SWAP16 = 159 +EVM_INS_LOG0 = 160 +EVM_INS_LOG1 = 161 +EVM_INS_LOG2 = 162 +EVM_INS_LOG3 = 163 +EVM_INS_LOG4 = 164 +EVM_INS_CREATE = 240 +EVM_INS_CALL = 241 +EVM_INS_CALLCODE = 242 +EVM_INS_RETURN = 243 +EVM_INS_DELEGATECALL = 244 +EVM_INS_CALLBLACKBOX = 245 +EVM_INS_STATICCALL = 250 +EVM_INS_REVERT = 253 +EVM_INS_SUICIDE = 255 +EVM_INS_INVALID = 512 +EVM_INS_ENDING = 513 + +EVM_GRP_INVALID = 0 +EVM_GRP_JUMP = 1 +EVM_GRP_MATH = 8 +EVM_GRP_STACK_WRITE = 9 +EVM_GRP_STACK_READ = 10 +EVM_GRP_MEM_WRITE = 11 +EVM_GRP_MEM_READ = 12 +EVM_GRP_STORE_WRITE = 13 +EVM_GRP_STORE_READ = 14 +EVM_GRP_HALT = 15 +EVM_GRP_ENDING = 16 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/m680x.py b/white_patch_detect/capstone-master/bindings/python/capstone/m680x.py new file mode 100644 index 0000000..dae21be --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/m680x.py @@ -0,0 +1,88 @@ +# Capstone Python bindings, by Wolfgang Schwotzer + +import ctypes +from . import copy_ctypes_list +from .m680x_const import * + +# define the API +class M680xOpIdx(ctypes.Structure): + _fields_ = ( + ('base_reg', ctypes.c_uint), + ('offset_reg', ctypes.c_uint), + ('offset', ctypes.c_int16), + ('offset_addr', ctypes.c_uint16), + ('offset_bits', ctypes.c_uint8), + ('inc_dec', ctypes.c_int8), + ('flags', ctypes.c_uint8), + ) + +class M680xOpRel(ctypes.Structure): + _fields_ = ( + ('address', ctypes.c_uint16), + ('offset', ctypes.c_int16), + ) + +class M680xOpExt(ctypes.Structure): + _fields_ = ( + ('address', ctypes.c_uint16), + ('indirect', ctypes.c_bool), + ) + +class M680xOpValue(ctypes.Union): + _fields_ = ( + ('imm', ctypes.c_int32), + ('reg', ctypes.c_uint), + ('idx', M680xOpIdx), + ('rel', M680xOpRel), + ('ext', M680xOpExt), + ('direct_addr', ctypes.c_uint8), + ('const_val', ctypes.c_uint8), + ) + +class M680xOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', M680xOpValue), + ('size', ctypes.c_uint8), + ('access', ctypes.c_uint8), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def idx(self): + return self.value.idx + + @property + def rel(self): + return self.value.rel + + @property + def ext(self): + return self.value.ext + + @property + def direct_addr(self): + return self.value.direct_addr + + @property + def const_val(self): + return self.value.const_val + + +class CsM680x(ctypes.Structure): + _fields_ = ( + ('flags', ctypes.c_uint8), + ('op_count', ctypes.c_uint8), + ('operands', M680xOp * 9), + ) + +def get_arch_info(a): + return (a.flags, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/m680x_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/m680x_const.py new file mode 100644 index 0000000..2ed71ab --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/m680x_const.py @@ -0,0 +1,415 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py] +M680X_OPERAND_COUNT = 9 + +M680X_REG_INVALID = 0 +M680X_REG_A = 1 +M680X_REG_B = 2 +M680X_REG_E = 3 +M680X_REG_F = 4 +M680X_REG_0 = 5 +M680X_REG_D = 6 +M680X_REG_W = 7 +M680X_REG_CC = 8 +M680X_REG_DP = 9 +M680X_REG_MD = 10 +M680X_REG_HX = 11 +M680X_REG_H = 12 +M680X_REG_X = 13 +M680X_REG_Y = 14 +M680X_REG_S = 15 +M680X_REG_U = 16 +M680X_REG_V = 17 +M680X_REG_Q = 18 +M680X_REG_PC = 19 +M680X_REG_TMP2 = 20 +M680X_REG_TMP3 = 21 +M680X_REG_ENDING = 22 + +M680X_OP_INVALID = 0 +M680X_OP_REGISTER = 1 +M680X_OP_IMMEDIATE = 2 +M680X_OP_INDEXED = 3 +M680X_OP_EXTENDED = 4 +M680X_OP_DIRECT = 5 +M680X_OP_RELATIVE = 6 +M680X_OP_CONSTANT = 7 + +M680X_OFFSET_NONE = 0 +M680X_OFFSET_BITS_5 = 5 +M680X_OFFSET_BITS_8 = 8 +M680X_OFFSET_BITS_9 = 9 +M680X_OFFSET_BITS_16 = 16 +M680X_IDX_INDIRECT = 1 +M680X_IDX_NO_COMMA = 2 +M680X_IDX_POST_INC_DEC = 4 + +M680X_GRP_INVALID = 0 +M680X_GRP_JUMP = 1 +M680X_GRP_CALL = 2 +M680X_GRP_RET = 3 +M680X_GRP_INT = 4 +M680X_GRP_IRET = 5 +M680X_GRP_PRIV = 6 +M680X_GRP_BRAREL = 7 +M680X_GRP_ENDING = 8 +M680X_FIRST_OP_IN_MNEM = 1 +M680X_SECOND_OP_IN_MNEM = 2 + +M680X_INS_INVLD = 0 +M680X_INS_ABA = 1 +M680X_INS_ABX = 2 +M680X_INS_ABY = 3 +M680X_INS_ADC = 4 +M680X_INS_ADCA = 5 +M680X_INS_ADCB = 6 +M680X_INS_ADCD = 7 +M680X_INS_ADCR = 8 +M680X_INS_ADD = 9 +M680X_INS_ADDA = 10 +M680X_INS_ADDB = 11 +M680X_INS_ADDD = 12 +M680X_INS_ADDE = 13 +M680X_INS_ADDF = 14 +M680X_INS_ADDR = 15 +M680X_INS_ADDW = 16 +M680X_INS_AIM = 17 +M680X_INS_AIS = 18 +M680X_INS_AIX = 19 +M680X_INS_AND = 20 +M680X_INS_ANDA = 21 +M680X_INS_ANDB = 22 +M680X_INS_ANDCC = 23 +M680X_INS_ANDD = 24 +M680X_INS_ANDR = 25 +M680X_INS_ASL = 26 +M680X_INS_ASLA = 27 +M680X_INS_ASLB = 28 +M680X_INS_ASLD = 29 +M680X_INS_ASR = 30 +M680X_INS_ASRA = 31 +M680X_INS_ASRB = 32 +M680X_INS_ASRD = 33 +M680X_INS_ASRX = 34 +M680X_INS_BAND = 35 +M680X_INS_BCC = 36 +M680X_INS_BCLR = 37 +M680X_INS_BCS = 38 +M680X_INS_BEOR = 39 +M680X_INS_BEQ = 40 +M680X_INS_BGE = 41 +M680X_INS_BGND = 42 +M680X_INS_BGT = 43 +M680X_INS_BHCC = 44 +M680X_INS_BHCS = 45 +M680X_INS_BHI = 46 +M680X_INS_BIAND = 47 +M680X_INS_BIEOR = 48 +M680X_INS_BIH = 49 +M680X_INS_BIL = 50 +M680X_INS_BIOR = 51 +M680X_INS_BIT = 52 +M680X_INS_BITA = 53 +M680X_INS_BITB = 54 +M680X_INS_BITD = 55 +M680X_INS_BITMD = 56 +M680X_INS_BLE = 57 +M680X_INS_BLS = 58 +M680X_INS_BLT = 59 +M680X_INS_BMC = 60 +M680X_INS_BMI = 61 +M680X_INS_BMS = 62 +M680X_INS_BNE = 63 +M680X_INS_BOR = 64 +M680X_INS_BPL = 65 +M680X_INS_BRCLR = 66 +M680X_INS_BRSET = 67 +M680X_INS_BRA = 68 +M680X_INS_BRN = 69 +M680X_INS_BSET = 70 +M680X_INS_BSR = 71 +M680X_INS_BVC = 72 +M680X_INS_BVS = 73 +M680X_INS_CALL = 74 +M680X_INS_CBA = 75 +M680X_INS_CBEQ = 76 +M680X_INS_CBEQA = 77 +M680X_INS_CBEQX = 78 +M680X_INS_CLC = 79 +M680X_INS_CLI = 80 +M680X_INS_CLR = 81 +M680X_INS_CLRA = 82 +M680X_INS_CLRB = 83 +M680X_INS_CLRD = 84 +M680X_INS_CLRE = 85 +M680X_INS_CLRF = 86 +M680X_INS_CLRH = 87 +M680X_INS_CLRW = 88 +M680X_INS_CLRX = 89 +M680X_INS_CLV = 90 +M680X_INS_CMP = 91 +M680X_INS_CMPA = 92 +M680X_INS_CMPB = 93 +M680X_INS_CMPD = 94 +M680X_INS_CMPE = 95 +M680X_INS_CMPF = 96 +M680X_INS_CMPR = 97 +M680X_INS_CMPS = 98 +M680X_INS_CMPU = 99 +M680X_INS_CMPW = 100 +M680X_INS_CMPX = 101 +M680X_INS_CMPY = 102 +M680X_INS_COM = 103 +M680X_INS_COMA = 104 +M680X_INS_COMB = 105 +M680X_INS_COMD = 106 +M680X_INS_COME = 107 +M680X_INS_COMF = 108 +M680X_INS_COMW = 109 +M680X_INS_COMX = 110 +M680X_INS_CPD = 111 +M680X_INS_CPHX = 112 +M680X_INS_CPS = 113 +M680X_INS_CPX = 114 +M680X_INS_CPY = 115 +M680X_INS_CWAI = 116 +M680X_INS_DAA = 117 +M680X_INS_DBEQ = 118 +M680X_INS_DBNE = 119 +M680X_INS_DBNZ = 120 +M680X_INS_DBNZA = 121 +M680X_INS_DBNZX = 122 +M680X_INS_DEC = 123 +M680X_INS_DECA = 124 +M680X_INS_DECB = 125 +M680X_INS_DECD = 126 +M680X_INS_DECE = 127 +M680X_INS_DECF = 128 +M680X_INS_DECW = 129 +M680X_INS_DECX = 130 +M680X_INS_DES = 131 +M680X_INS_DEX = 132 +M680X_INS_DEY = 133 +M680X_INS_DIV = 134 +M680X_INS_DIVD = 135 +M680X_INS_DIVQ = 136 +M680X_INS_EDIV = 137 +M680X_INS_EDIVS = 138 +M680X_INS_EIM = 139 +M680X_INS_EMACS = 140 +M680X_INS_EMAXD = 141 +M680X_INS_EMAXM = 142 +M680X_INS_EMIND = 143 +M680X_INS_EMINM = 144 +M680X_INS_EMUL = 145 +M680X_INS_EMULS = 146 +M680X_INS_EOR = 147 +M680X_INS_EORA = 148 +M680X_INS_EORB = 149 +M680X_INS_EORD = 150 +M680X_INS_EORR = 151 +M680X_INS_ETBL = 152 +M680X_INS_EXG = 153 +M680X_INS_FDIV = 154 +M680X_INS_IBEQ = 155 +M680X_INS_IBNE = 156 +M680X_INS_IDIV = 157 +M680X_INS_IDIVS = 158 +M680X_INS_ILLGL = 159 +M680X_INS_INC = 160 +M680X_INS_INCA = 161 +M680X_INS_INCB = 162 +M680X_INS_INCD = 163 +M680X_INS_INCE = 164 +M680X_INS_INCF = 165 +M680X_INS_INCW = 166 +M680X_INS_INCX = 167 +M680X_INS_INS = 168 +M680X_INS_INX = 169 +M680X_INS_INY = 170 +M680X_INS_JMP = 171 +M680X_INS_JSR = 172 +M680X_INS_LBCC = 173 +M680X_INS_LBCS = 174 +M680X_INS_LBEQ = 175 +M680X_INS_LBGE = 176 +M680X_INS_LBGT = 177 +M680X_INS_LBHI = 178 +M680X_INS_LBLE = 179 +M680X_INS_LBLS = 180 +M680X_INS_LBLT = 181 +M680X_INS_LBMI = 182 +M680X_INS_LBNE = 183 +M680X_INS_LBPL = 184 +M680X_INS_LBRA = 185 +M680X_INS_LBRN = 186 +M680X_INS_LBSR = 187 +M680X_INS_LBVC = 188 +M680X_INS_LBVS = 189 +M680X_INS_LDA = 190 +M680X_INS_LDAA = 191 +M680X_INS_LDAB = 192 +M680X_INS_LDB = 193 +M680X_INS_LDBT = 194 +M680X_INS_LDD = 195 +M680X_INS_LDE = 196 +M680X_INS_LDF = 197 +M680X_INS_LDHX = 198 +M680X_INS_LDMD = 199 +M680X_INS_LDQ = 200 +M680X_INS_LDS = 201 +M680X_INS_LDU = 202 +M680X_INS_LDW = 203 +M680X_INS_LDX = 204 +M680X_INS_LDY = 205 +M680X_INS_LEAS = 206 +M680X_INS_LEAU = 207 +M680X_INS_LEAX = 208 +M680X_INS_LEAY = 209 +M680X_INS_LSL = 210 +M680X_INS_LSLA = 211 +M680X_INS_LSLB = 212 +M680X_INS_LSLD = 213 +M680X_INS_LSLX = 214 +M680X_INS_LSR = 215 +M680X_INS_LSRA = 216 +M680X_INS_LSRB = 217 +M680X_INS_LSRD = 218 +M680X_INS_LSRW = 219 +M680X_INS_LSRX = 220 +M680X_INS_MAXA = 221 +M680X_INS_MAXM = 222 +M680X_INS_MEM = 223 +M680X_INS_MINA = 224 +M680X_INS_MINM = 225 +M680X_INS_MOV = 226 +M680X_INS_MOVB = 227 +M680X_INS_MOVW = 228 +M680X_INS_MUL = 229 +M680X_INS_MULD = 230 +M680X_INS_NEG = 231 +M680X_INS_NEGA = 232 +M680X_INS_NEGB = 233 +M680X_INS_NEGD = 234 +M680X_INS_NEGX = 235 +M680X_INS_NOP = 236 +M680X_INS_NSA = 237 +M680X_INS_OIM = 238 +M680X_INS_ORA = 239 +M680X_INS_ORAA = 240 +M680X_INS_ORAB = 241 +M680X_INS_ORB = 242 +M680X_INS_ORCC = 243 +M680X_INS_ORD = 244 +M680X_INS_ORR = 245 +M680X_INS_PSHA = 246 +M680X_INS_PSHB = 247 +M680X_INS_PSHC = 248 +M680X_INS_PSHD = 249 +M680X_INS_PSHH = 250 +M680X_INS_PSHS = 251 +M680X_INS_PSHSW = 252 +M680X_INS_PSHU = 253 +M680X_INS_PSHUW = 254 +M680X_INS_PSHX = 255 +M680X_INS_PSHY = 256 +M680X_INS_PULA = 257 +M680X_INS_PULB = 258 +M680X_INS_PULC = 259 +M680X_INS_PULD = 260 +M680X_INS_PULH = 261 +M680X_INS_PULS = 262 +M680X_INS_PULSW = 263 +M680X_INS_PULU = 264 +M680X_INS_PULUW = 265 +M680X_INS_PULX = 266 +M680X_INS_PULY = 267 +M680X_INS_REV = 268 +M680X_INS_REVW = 269 +M680X_INS_ROL = 270 +M680X_INS_ROLA = 271 +M680X_INS_ROLB = 272 +M680X_INS_ROLD = 273 +M680X_INS_ROLW = 274 +M680X_INS_ROLX = 275 +M680X_INS_ROR = 276 +M680X_INS_RORA = 277 +M680X_INS_RORB = 278 +M680X_INS_RORD = 279 +M680X_INS_RORW = 280 +M680X_INS_RORX = 281 +M680X_INS_RSP = 282 +M680X_INS_RTC = 283 +M680X_INS_RTI = 284 +M680X_INS_RTS = 285 +M680X_INS_SBA = 286 +M680X_INS_SBC = 287 +M680X_INS_SBCA = 288 +M680X_INS_SBCB = 289 +M680X_INS_SBCD = 290 +M680X_INS_SBCR = 291 +M680X_INS_SEC = 292 +M680X_INS_SEI = 293 +M680X_INS_SEV = 294 +M680X_INS_SEX = 295 +M680X_INS_SEXW = 296 +M680X_INS_SLP = 297 +M680X_INS_STA = 298 +M680X_INS_STAA = 299 +M680X_INS_STAB = 300 +M680X_INS_STB = 301 +M680X_INS_STBT = 302 +M680X_INS_STD = 303 +M680X_INS_STE = 304 +M680X_INS_STF = 305 +M680X_INS_STOP = 306 +M680X_INS_STHX = 307 +M680X_INS_STQ = 308 +M680X_INS_STS = 309 +M680X_INS_STU = 310 +M680X_INS_STW = 311 +M680X_INS_STX = 312 +M680X_INS_STY = 313 +M680X_INS_SUB = 314 +M680X_INS_SUBA = 315 +M680X_INS_SUBB = 316 +M680X_INS_SUBD = 317 +M680X_INS_SUBE = 318 +M680X_INS_SUBF = 319 +M680X_INS_SUBR = 320 +M680X_INS_SUBW = 321 +M680X_INS_SWI = 322 +M680X_INS_SWI2 = 323 +M680X_INS_SWI3 = 324 +M680X_INS_SYNC = 325 +M680X_INS_TAB = 326 +M680X_INS_TAP = 327 +M680X_INS_TAX = 328 +M680X_INS_TBA = 329 +M680X_INS_TBEQ = 330 +M680X_INS_TBL = 331 +M680X_INS_TBNE = 332 +M680X_INS_TEST = 333 +M680X_INS_TFM = 334 +M680X_INS_TFR = 335 +M680X_INS_TIM = 336 +M680X_INS_TPA = 337 +M680X_INS_TST = 338 +M680X_INS_TSTA = 339 +M680X_INS_TSTB = 340 +M680X_INS_TSTD = 341 +M680X_INS_TSTE = 342 +M680X_INS_TSTF = 343 +M680X_INS_TSTW = 344 +M680X_INS_TSTX = 345 +M680X_INS_TSX = 346 +M680X_INS_TSY = 347 +M680X_INS_TXA = 348 +M680X_INS_TXS = 349 +M680X_INS_TYS = 350 +M680X_INS_WAI = 351 +M680X_INS_WAIT = 352 +M680X_INS_WAV = 353 +M680X_INS_WAVR = 354 +M680X_INS_XGDX = 355 +M680X_INS_XGDY = 356 +M680X_INS_ENDING = 357 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/m68k.py b/white_patch_detect/capstone-master/bindings/python/capstone/m68k.py new file mode 100644 index 0000000..9cc8936 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/m68k.py @@ -0,0 +1,96 @@ +# Capstone Python bindings, by Nicolas PLANEL + +import ctypes +from . import copy_ctypes_list +from .m68k_const import * + +# define the API +class M68KOpMem(ctypes.Structure): + _fields_ = ( + ('base_reg', ctypes.c_uint), + ('index_reg', ctypes.c_uint), + ('in_base_reg', ctypes.c_uint), + ('in_disp', ctypes.c_uint), + ('out_disp', ctypes.c_uint), + ('disp', ctypes.c_short), + ('scale', ctypes.c_ubyte), + ('bitfield', ctypes.c_ubyte), + ('width', ctypes.c_ubyte), + ('offset', ctypes.c_ubyte), + ('index_size', ctypes.c_ubyte), + ) + +class M68KOpRegPair(ctypes.Structure): + _fields_ = ( + ('reg_0', ctypes.c_uint), + ('reg_1', ctypes.c_uint), + ) + +class M68KOpValue(ctypes.Union): + _fields_ = ( + ('imm', ctypes.c_int64), + ('dimm', ctypes.c_double), + ('simm', ctypes.c_float), + ('reg', ctypes.c_uint), + ('reg_pair', M68KOpRegPair), + ) + +class M68KOpBrDisp(ctypes.Structure): + _fields_ = ( + ('disp', ctypes.c_int), + ('disp_size', ctypes.c_ubyte), + ) + +class M68KOp(ctypes.Structure): + _fields_ = ( + ('value', M68KOpValue), + ('mem', M68KOpMem), + ('br_disp', M68KOpBrDisp), + ('register_bits', ctypes.c_uint), + ('type', ctypes.c_uint), + ('address_mode', ctypes.c_uint), + ) + + @property + def imm(self): + return self.value.imm + + @property + def dimm(self): + return self.value.dimm + + @property + def simm(self): + return self.value.simm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.mem + + @property + def register_bits(self): + return self.register_bits + +class M68KOpSize(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('size', ctypes.c_uint), + ) + + def get(a): + return copy_ctypes_list(type, size) + +class CsM68K(ctypes.Structure): + M68K_OPERAND_COUNT = 4 + _fields_ = ( + ('operands', M68KOp * M68K_OPERAND_COUNT), + ('op_size', M68KOpSize), + ('op_count', ctypes.c_uint8), + ) + +def get_arch_info(a): + return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size) diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/m68k_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/m68k_const.py new file mode 100644 index 0000000..39f5418 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/m68k_const.py @@ -0,0 +1,485 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] +M68K_OPERAND_COUNT = 4 + +M68K_REG_INVALID = 0 +M68K_REG_D0 = 1 +M68K_REG_D1 = 2 +M68K_REG_D2 = 3 +M68K_REG_D3 = 4 +M68K_REG_D4 = 5 +M68K_REG_D5 = 6 +M68K_REG_D6 = 7 +M68K_REG_D7 = 8 +M68K_REG_A0 = 9 +M68K_REG_A1 = 10 +M68K_REG_A2 = 11 +M68K_REG_A3 = 12 +M68K_REG_A4 = 13 +M68K_REG_A5 = 14 +M68K_REG_A6 = 15 +M68K_REG_A7 = 16 +M68K_REG_FP0 = 17 +M68K_REG_FP1 = 18 +M68K_REG_FP2 = 19 +M68K_REG_FP3 = 20 +M68K_REG_FP4 = 21 +M68K_REG_FP5 = 22 +M68K_REG_FP6 = 23 +M68K_REG_FP7 = 24 +M68K_REG_PC = 25 +M68K_REG_SR = 26 +M68K_REG_CCR = 27 +M68K_REG_SFC = 28 +M68K_REG_DFC = 29 +M68K_REG_USP = 30 +M68K_REG_VBR = 31 +M68K_REG_CACR = 32 +M68K_REG_CAAR = 33 +M68K_REG_MSP = 34 +M68K_REG_ISP = 35 +M68K_REG_TC = 36 +M68K_REG_ITT0 = 37 +M68K_REG_ITT1 = 38 +M68K_REG_DTT0 = 39 +M68K_REG_DTT1 = 40 +M68K_REG_MMUSR = 41 +M68K_REG_URP = 42 +M68K_REG_SRP = 43 +M68K_REG_FPCR = 44 +M68K_REG_FPSR = 45 +M68K_REG_FPIAR = 46 +M68K_REG_ENDING = 47 + +M68K_AM_NONE = 0 +M68K_AM_REG_DIRECT_DATA = 1 +M68K_AM_REG_DIRECT_ADDR = 2 +M68K_AM_REGI_ADDR = 3 +M68K_AM_REGI_ADDR_POST_INC = 4 +M68K_AM_REGI_ADDR_PRE_DEC = 5 +M68K_AM_REGI_ADDR_DISP = 6 +M68K_AM_AREGI_INDEX_8_BIT_DISP = 7 +M68K_AM_AREGI_INDEX_BASE_DISP = 8 +M68K_AM_MEMI_POST_INDEX = 9 +M68K_AM_MEMI_PRE_INDEX = 10 +M68K_AM_PCI_DISP = 11 +M68K_AM_PCI_INDEX_8_BIT_DISP = 12 +M68K_AM_PCI_INDEX_BASE_DISP = 13 +M68K_AM_PC_MEMI_POST_INDEX = 14 +M68K_AM_PC_MEMI_PRE_INDEX = 15 +M68K_AM_ABSOLUTE_DATA_SHORT = 16 +M68K_AM_ABSOLUTE_DATA_LONG = 17 +M68K_AM_IMMEDIATE = 18 +M68K_AM_BRANCH_DISPLACEMENT = 19 + +M68K_OP_INVALID = 0 +M68K_OP_REG = 1 +M68K_OP_IMM = 2 +M68K_OP_MEM = 3 +M68K_OP_FP_SINGLE = 4 +M68K_OP_FP_DOUBLE = 5 +M68K_OP_REG_BITS = 6 +M68K_OP_REG_PAIR = 7 +M68K_OP_BR_DISP = 8 + +M68K_OP_BR_DISP_SIZE_INVALID = 0 +M68K_OP_BR_DISP_SIZE_BYTE = 1 +M68K_OP_BR_DISP_SIZE_WORD = 2 +M68K_OP_BR_DISP_SIZE_LONG = 4 + +M68K_CPU_SIZE_NONE = 0 +M68K_CPU_SIZE_BYTE = 1 +M68K_CPU_SIZE_WORD = 2 +M68K_CPU_SIZE_LONG = 4 + +M68K_FPU_SIZE_NONE = 0 +M68K_FPU_SIZE_SINGLE = 4 +M68K_FPU_SIZE_DOUBLE = 8 +M68K_FPU_SIZE_EXTENDED = 12 + +M68K_SIZE_TYPE_INVALID = 0 +M68K_SIZE_TYPE_CPU = 1 +M68K_SIZE_TYPE_FPU = 2 + +M68K_INS_INVALID = 0 +M68K_INS_ABCD = 1 +M68K_INS_ADD = 2 +M68K_INS_ADDA = 3 +M68K_INS_ADDI = 4 +M68K_INS_ADDQ = 5 +M68K_INS_ADDX = 6 +M68K_INS_AND = 7 +M68K_INS_ANDI = 8 +M68K_INS_ASL = 9 +M68K_INS_ASR = 10 +M68K_INS_BHS = 11 +M68K_INS_BLO = 12 +M68K_INS_BHI = 13 +M68K_INS_BLS = 14 +M68K_INS_BCC = 15 +M68K_INS_BCS = 16 +M68K_INS_BNE = 17 +M68K_INS_BEQ = 18 +M68K_INS_BVC = 19 +M68K_INS_BVS = 20 +M68K_INS_BPL = 21 +M68K_INS_BMI = 22 +M68K_INS_BGE = 23 +M68K_INS_BLT = 24 +M68K_INS_BGT = 25 +M68K_INS_BLE = 26 +M68K_INS_BRA = 27 +M68K_INS_BSR = 28 +M68K_INS_BCHG = 29 +M68K_INS_BCLR = 30 +M68K_INS_BSET = 31 +M68K_INS_BTST = 32 +M68K_INS_BFCHG = 33 +M68K_INS_BFCLR = 34 +M68K_INS_BFEXTS = 35 +M68K_INS_BFEXTU = 36 +M68K_INS_BFFFO = 37 +M68K_INS_BFINS = 38 +M68K_INS_BFSET = 39 +M68K_INS_BFTST = 40 +M68K_INS_BKPT = 41 +M68K_INS_CALLM = 42 +M68K_INS_CAS = 43 +M68K_INS_CAS2 = 44 +M68K_INS_CHK = 45 +M68K_INS_CHK2 = 46 +M68K_INS_CLR = 47 +M68K_INS_CMP = 48 +M68K_INS_CMPA = 49 +M68K_INS_CMPI = 50 +M68K_INS_CMPM = 51 +M68K_INS_CMP2 = 52 +M68K_INS_CINVL = 53 +M68K_INS_CINVP = 54 +M68K_INS_CINVA = 55 +M68K_INS_CPUSHL = 56 +M68K_INS_CPUSHP = 57 +M68K_INS_CPUSHA = 58 +M68K_INS_DBT = 59 +M68K_INS_DBF = 60 +M68K_INS_DBHI = 61 +M68K_INS_DBLS = 62 +M68K_INS_DBCC = 63 +M68K_INS_DBCS = 64 +M68K_INS_DBNE = 65 +M68K_INS_DBEQ = 66 +M68K_INS_DBVC = 67 +M68K_INS_DBVS = 68 +M68K_INS_DBPL = 69 +M68K_INS_DBMI = 70 +M68K_INS_DBGE = 71 +M68K_INS_DBLT = 72 +M68K_INS_DBGT = 73 +M68K_INS_DBLE = 74 +M68K_INS_DBRA = 75 +M68K_INS_DIVS = 76 +M68K_INS_DIVSL = 77 +M68K_INS_DIVU = 78 +M68K_INS_DIVUL = 79 +M68K_INS_EOR = 80 +M68K_INS_EORI = 81 +M68K_INS_EXG = 82 +M68K_INS_EXT = 83 +M68K_INS_EXTB = 84 +M68K_INS_FABS = 85 +M68K_INS_FSABS = 86 +M68K_INS_FDABS = 87 +M68K_INS_FACOS = 88 +M68K_INS_FADD = 89 +M68K_INS_FSADD = 90 +M68K_INS_FDADD = 91 +M68K_INS_FASIN = 92 +M68K_INS_FATAN = 93 +M68K_INS_FATANH = 94 +M68K_INS_FBF = 95 +M68K_INS_FBEQ = 96 +M68K_INS_FBOGT = 97 +M68K_INS_FBOGE = 98 +M68K_INS_FBOLT = 99 +M68K_INS_FBOLE = 100 +M68K_INS_FBOGL = 101 +M68K_INS_FBOR = 102 +M68K_INS_FBUN = 103 +M68K_INS_FBUEQ = 104 +M68K_INS_FBUGT = 105 +M68K_INS_FBUGE = 106 +M68K_INS_FBULT = 107 +M68K_INS_FBULE = 108 +M68K_INS_FBNE = 109 +M68K_INS_FBT = 110 +M68K_INS_FBSF = 111 +M68K_INS_FBSEQ = 112 +M68K_INS_FBGT = 113 +M68K_INS_FBGE = 114 +M68K_INS_FBLT = 115 +M68K_INS_FBLE = 116 +M68K_INS_FBGL = 117 +M68K_INS_FBGLE = 118 +M68K_INS_FBNGLE = 119 +M68K_INS_FBNGL = 120 +M68K_INS_FBNLE = 121 +M68K_INS_FBNLT = 122 +M68K_INS_FBNGE = 123 +M68K_INS_FBNGT = 124 +M68K_INS_FBSNE = 125 +M68K_INS_FBST = 126 +M68K_INS_FCMP = 127 +M68K_INS_FCOS = 128 +M68K_INS_FCOSH = 129 +M68K_INS_FDBF = 130 +M68K_INS_FDBEQ = 131 +M68K_INS_FDBOGT = 132 +M68K_INS_FDBOGE = 133 +M68K_INS_FDBOLT = 134 +M68K_INS_FDBOLE = 135 +M68K_INS_FDBOGL = 136 +M68K_INS_FDBOR = 137 +M68K_INS_FDBUN = 138 +M68K_INS_FDBUEQ = 139 +M68K_INS_FDBUGT = 140 +M68K_INS_FDBUGE = 141 +M68K_INS_FDBULT = 142 +M68K_INS_FDBULE = 143 +M68K_INS_FDBNE = 144 +M68K_INS_FDBT = 145 +M68K_INS_FDBSF = 146 +M68K_INS_FDBSEQ = 147 +M68K_INS_FDBGT = 148 +M68K_INS_FDBGE = 149 +M68K_INS_FDBLT = 150 +M68K_INS_FDBLE = 151 +M68K_INS_FDBGL = 152 +M68K_INS_FDBGLE = 153 +M68K_INS_FDBNGLE = 154 +M68K_INS_FDBNGL = 155 +M68K_INS_FDBNLE = 156 +M68K_INS_FDBNLT = 157 +M68K_INS_FDBNGE = 158 +M68K_INS_FDBNGT = 159 +M68K_INS_FDBSNE = 160 +M68K_INS_FDBST = 161 +M68K_INS_FDIV = 162 +M68K_INS_FSDIV = 163 +M68K_INS_FDDIV = 164 +M68K_INS_FETOX = 165 +M68K_INS_FETOXM1 = 166 +M68K_INS_FGETEXP = 167 +M68K_INS_FGETMAN = 168 +M68K_INS_FINT = 169 +M68K_INS_FINTRZ = 170 +M68K_INS_FLOG10 = 171 +M68K_INS_FLOG2 = 172 +M68K_INS_FLOGN = 173 +M68K_INS_FLOGNP1 = 174 +M68K_INS_FMOD = 175 +M68K_INS_FMOVE = 176 +M68K_INS_FSMOVE = 177 +M68K_INS_FDMOVE = 178 +M68K_INS_FMOVECR = 179 +M68K_INS_FMOVEM = 180 +M68K_INS_FMUL = 181 +M68K_INS_FSMUL = 182 +M68K_INS_FDMUL = 183 +M68K_INS_FNEG = 184 +M68K_INS_FSNEG = 185 +M68K_INS_FDNEG = 186 +M68K_INS_FNOP = 187 +M68K_INS_FREM = 188 +M68K_INS_FRESTORE = 189 +M68K_INS_FSAVE = 190 +M68K_INS_FSCALE = 191 +M68K_INS_FSGLDIV = 192 +M68K_INS_FSGLMUL = 193 +M68K_INS_FSIN = 194 +M68K_INS_FSINCOS = 195 +M68K_INS_FSINH = 196 +M68K_INS_FSQRT = 197 +M68K_INS_FSSQRT = 198 +M68K_INS_FDSQRT = 199 +M68K_INS_FSF = 200 +M68K_INS_FSBEQ = 201 +M68K_INS_FSOGT = 202 +M68K_INS_FSOGE = 203 +M68K_INS_FSOLT = 204 +M68K_INS_FSOLE = 205 +M68K_INS_FSOGL = 206 +M68K_INS_FSOR = 207 +M68K_INS_FSUN = 208 +M68K_INS_FSUEQ = 209 +M68K_INS_FSUGT = 210 +M68K_INS_FSUGE = 211 +M68K_INS_FSULT = 212 +M68K_INS_FSULE = 213 +M68K_INS_FSNE = 214 +M68K_INS_FST = 215 +M68K_INS_FSSF = 216 +M68K_INS_FSSEQ = 217 +M68K_INS_FSGT = 218 +M68K_INS_FSGE = 219 +M68K_INS_FSLT = 220 +M68K_INS_FSLE = 221 +M68K_INS_FSGL = 222 +M68K_INS_FSGLE = 223 +M68K_INS_FSNGLE = 224 +M68K_INS_FSNGL = 225 +M68K_INS_FSNLE = 226 +M68K_INS_FSNLT = 227 +M68K_INS_FSNGE = 228 +M68K_INS_FSNGT = 229 +M68K_INS_FSSNE = 230 +M68K_INS_FSST = 231 +M68K_INS_FSUB = 232 +M68K_INS_FSSUB = 233 +M68K_INS_FDSUB = 234 +M68K_INS_FTAN = 235 +M68K_INS_FTANH = 236 +M68K_INS_FTENTOX = 237 +M68K_INS_FTRAPF = 238 +M68K_INS_FTRAPEQ = 239 +M68K_INS_FTRAPOGT = 240 +M68K_INS_FTRAPOGE = 241 +M68K_INS_FTRAPOLT = 242 +M68K_INS_FTRAPOLE = 243 +M68K_INS_FTRAPOGL = 244 +M68K_INS_FTRAPOR = 245 +M68K_INS_FTRAPUN = 246 +M68K_INS_FTRAPUEQ = 247 +M68K_INS_FTRAPUGT = 248 +M68K_INS_FTRAPUGE = 249 +M68K_INS_FTRAPULT = 250 +M68K_INS_FTRAPULE = 251 +M68K_INS_FTRAPNE = 252 +M68K_INS_FTRAPT = 253 +M68K_INS_FTRAPSF = 254 +M68K_INS_FTRAPSEQ = 255 +M68K_INS_FTRAPGT = 256 +M68K_INS_FTRAPGE = 257 +M68K_INS_FTRAPLT = 258 +M68K_INS_FTRAPLE = 259 +M68K_INS_FTRAPGL = 260 +M68K_INS_FTRAPGLE = 261 +M68K_INS_FTRAPNGLE = 262 +M68K_INS_FTRAPNGL = 263 +M68K_INS_FTRAPNLE = 264 +M68K_INS_FTRAPNLT = 265 +M68K_INS_FTRAPNGE = 266 +M68K_INS_FTRAPNGT = 267 +M68K_INS_FTRAPSNE = 268 +M68K_INS_FTRAPST = 269 +M68K_INS_FTST = 270 +M68K_INS_FTWOTOX = 271 +M68K_INS_HALT = 272 +M68K_INS_ILLEGAL = 273 +M68K_INS_JMP = 274 +M68K_INS_JSR = 275 +M68K_INS_LEA = 276 +M68K_INS_LINK = 277 +M68K_INS_LPSTOP = 278 +M68K_INS_LSL = 279 +M68K_INS_LSR = 280 +M68K_INS_MOVE = 281 +M68K_INS_MOVEA = 282 +M68K_INS_MOVEC = 283 +M68K_INS_MOVEM = 284 +M68K_INS_MOVEP = 285 +M68K_INS_MOVEQ = 286 +M68K_INS_MOVES = 287 +M68K_INS_MOVE16 = 288 +M68K_INS_MULS = 289 +M68K_INS_MULU = 290 +M68K_INS_NBCD = 291 +M68K_INS_NEG = 292 +M68K_INS_NEGX = 293 +M68K_INS_NOP = 294 +M68K_INS_NOT = 295 +M68K_INS_OR = 296 +M68K_INS_ORI = 297 +M68K_INS_PACK = 298 +M68K_INS_PEA = 299 +M68K_INS_PFLUSH = 300 +M68K_INS_PFLUSHA = 301 +M68K_INS_PFLUSHAN = 302 +M68K_INS_PFLUSHN = 303 +M68K_INS_PLOADR = 304 +M68K_INS_PLOADW = 305 +M68K_INS_PLPAR = 306 +M68K_INS_PLPAW = 307 +M68K_INS_PMOVE = 308 +M68K_INS_PMOVEFD = 309 +M68K_INS_PTESTR = 310 +M68K_INS_PTESTW = 311 +M68K_INS_PULSE = 312 +M68K_INS_REMS = 313 +M68K_INS_REMU = 314 +M68K_INS_RESET = 315 +M68K_INS_ROL = 316 +M68K_INS_ROR = 317 +M68K_INS_ROXL = 318 +M68K_INS_ROXR = 319 +M68K_INS_RTD = 320 +M68K_INS_RTE = 321 +M68K_INS_RTM = 322 +M68K_INS_RTR = 323 +M68K_INS_RTS = 324 +M68K_INS_SBCD = 325 +M68K_INS_ST = 326 +M68K_INS_SF = 327 +M68K_INS_SHI = 328 +M68K_INS_SLS = 329 +M68K_INS_SCC = 330 +M68K_INS_SHS = 331 +M68K_INS_SCS = 332 +M68K_INS_SLO = 333 +M68K_INS_SNE = 334 +M68K_INS_SEQ = 335 +M68K_INS_SVC = 336 +M68K_INS_SVS = 337 +M68K_INS_SPL = 338 +M68K_INS_SMI = 339 +M68K_INS_SGE = 340 +M68K_INS_SLT = 341 +M68K_INS_SGT = 342 +M68K_INS_SLE = 343 +M68K_INS_STOP = 344 +M68K_INS_SUB = 345 +M68K_INS_SUBA = 346 +M68K_INS_SUBI = 347 +M68K_INS_SUBQ = 348 +M68K_INS_SUBX = 349 +M68K_INS_SWAP = 350 +M68K_INS_TAS = 351 +M68K_INS_TRAP = 352 +M68K_INS_TRAPV = 353 +M68K_INS_TRAPT = 354 +M68K_INS_TRAPF = 355 +M68K_INS_TRAPHI = 356 +M68K_INS_TRAPLS = 357 +M68K_INS_TRAPCC = 358 +M68K_INS_TRAPHS = 359 +M68K_INS_TRAPCS = 360 +M68K_INS_TRAPLO = 361 +M68K_INS_TRAPNE = 362 +M68K_INS_TRAPEQ = 363 +M68K_INS_TRAPVC = 364 +M68K_INS_TRAPVS = 365 +M68K_INS_TRAPPL = 366 +M68K_INS_TRAPMI = 367 +M68K_INS_TRAPGE = 368 +M68K_INS_TRAPLT = 369 +M68K_INS_TRAPGT = 370 +M68K_INS_TRAPLE = 371 +M68K_INS_TST = 372 +M68K_INS_UNLK = 373 +M68K_INS_UNPK = 374 +M68K_INS_ENDING = 375 + +M68K_GRP_INVALID = 0 +M68K_GRP_JUMP = 1 +M68K_GRP_RET = 3 +M68K_GRP_IRET = 5 +M68K_GRP_BRANCH_RELATIVE = 7 +M68K_GRP_ENDING = 8 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/mips.py b/white_patch_detect/capstone-master/bindings/python/capstone/mips.py new file mode 100644 index 0000000..44513d2 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/mips.py @@ -0,0 +1,48 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .mips_const import * + +# define the API +class MipsOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('disp', ctypes.c_int64), + ) + +class MipsOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', MipsOpMem), + ) + +class MipsOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', MipsOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsMips(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', MipsOp * 10), + ) + +def get_arch_info(a): + return copy_ctypes_list(a.operands[:a.op_count]) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/mips_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/mips_const.py new file mode 100644 index 0000000..af2f209 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/mips_const.py @@ -0,0 +1,861 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py] + +MIPS_OP_INVALID = 0 +MIPS_OP_REG = 1 +MIPS_OP_IMM = 2 +MIPS_OP_MEM = 3 + +MIPS_REG_INVALID = 0 +MIPS_REG_PC = 1 +MIPS_REG_0 = 2 +MIPS_REG_1 = 3 +MIPS_REG_2 = 4 +MIPS_REG_3 = 5 +MIPS_REG_4 = 6 +MIPS_REG_5 = 7 +MIPS_REG_6 = 8 +MIPS_REG_7 = 9 +MIPS_REG_8 = 10 +MIPS_REG_9 = 11 +MIPS_REG_10 = 12 +MIPS_REG_11 = 13 +MIPS_REG_12 = 14 +MIPS_REG_13 = 15 +MIPS_REG_14 = 16 +MIPS_REG_15 = 17 +MIPS_REG_16 = 18 +MIPS_REG_17 = 19 +MIPS_REG_18 = 20 +MIPS_REG_19 = 21 +MIPS_REG_20 = 22 +MIPS_REG_21 = 23 +MIPS_REG_22 = 24 +MIPS_REG_23 = 25 +MIPS_REG_24 = 26 +MIPS_REG_25 = 27 +MIPS_REG_26 = 28 +MIPS_REG_27 = 29 +MIPS_REG_28 = 30 +MIPS_REG_29 = 31 +MIPS_REG_30 = 32 +MIPS_REG_31 = 33 +MIPS_REG_DSPCCOND = 34 +MIPS_REG_DSPCARRY = 35 +MIPS_REG_DSPEFI = 36 +MIPS_REG_DSPOUTFLAG = 37 +MIPS_REG_DSPOUTFLAG16_19 = 38 +MIPS_REG_DSPOUTFLAG20 = 39 +MIPS_REG_DSPOUTFLAG21 = 40 +MIPS_REG_DSPOUTFLAG22 = 41 +MIPS_REG_DSPOUTFLAG23 = 42 +MIPS_REG_DSPPOS = 43 +MIPS_REG_DSPSCOUNT = 44 +MIPS_REG_AC0 = 45 +MIPS_REG_AC1 = 46 +MIPS_REG_AC2 = 47 +MIPS_REG_AC3 = 48 +MIPS_REG_CC0 = 49 +MIPS_REG_CC1 = 50 +MIPS_REG_CC2 = 51 +MIPS_REG_CC3 = 52 +MIPS_REG_CC4 = 53 +MIPS_REG_CC5 = 54 +MIPS_REG_CC6 = 55 +MIPS_REG_CC7 = 56 +MIPS_REG_F0 = 57 +MIPS_REG_F1 = 58 +MIPS_REG_F2 = 59 +MIPS_REG_F3 = 60 +MIPS_REG_F4 = 61 +MIPS_REG_F5 = 62 +MIPS_REG_F6 = 63 +MIPS_REG_F7 = 64 +MIPS_REG_F8 = 65 +MIPS_REG_F9 = 66 +MIPS_REG_F10 = 67 +MIPS_REG_F11 = 68 +MIPS_REG_F12 = 69 +MIPS_REG_F13 = 70 +MIPS_REG_F14 = 71 +MIPS_REG_F15 = 72 +MIPS_REG_F16 = 73 +MIPS_REG_F17 = 74 +MIPS_REG_F18 = 75 +MIPS_REG_F19 = 76 +MIPS_REG_F20 = 77 +MIPS_REG_F21 = 78 +MIPS_REG_F22 = 79 +MIPS_REG_F23 = 80 +MIPS_REG_F24 = 81 +MIPS_REG_F25 = 82 +MIPS_REG_F26 = 83 +MIPS_REG_F27 = 84 +MIPS_REG_F28 = 85 +MIPS_REG_F29 = 86 +MIPS_REG_F30 = 87 +MIPS_REG_F31 = 88 +MIPS_REG_FCC0 = 89 +MIPS_REG_FCC1 = 90 +MIPS_REG_FCC2 = 91 +MIPS_REG_FCC3 = 92 +MIPS_REG_FCC4 = 93 +MIPS_REG_FCC5 = 94 +MIPS_REG_FCC6 = 95 +MIPS_REG_FCC7 = 96 +MIPS_REG_W0 = 97 +MIPS_REG_W1 = 98 +MIPS_REG_W2 = 99 +MIPS_REG_W3 = 100 +MIPS_REG_W4 = 101 +MIPS_REG_W5 = 102 +MIPS_REG_W6 = 103 +MIPS_REG_W7 = 104 +MIPS_REG_W8 = 105 +MIPS_REG_W9 = 106 +MIPS_REG_W10 = 107 +MIPS_REG_W11 = 108 +MIPS_REG_W12 = 109 +MIPS_REG_W13 = 110 +MIPS_REG_W14 = 111 +MIPS_REG_W15 = 112 +MIPS_REG_W16 = 113 +MIPS_REG_W17 = 114 +MIPS_REG_W18 = 115 +MIPS_REG_W19 = 116 +MIPS_REG_W20 = 117 +MIPS_REG_W21 = 118 +MIPS_REG_W22 = 119 +MIPS_REG_W23 = 120 +MIPS_REG_W24 = 121 +MIPS_REG_W25 = 122 +MIPS_REG_W26 = 123 +MIPS_REG_W27 = 124 +MIPS_REG_W28 = 125 +MIPS_REG_W29 = 126 +MIPS_REG_W30 = 127 +MIPS_REG_W31 = 128 +MIPS_REG_HI = 129 +MIPS_REG_LO = 130 +MIPS_REG_P0 = 131 +MIPS_REG_P1 = 132 +MIPS_REG_P2 = 133 +MIPS_REG_MPL0 = 134 +MIPS_REG_MPL1 = 135 +MIPS_REG_MPL2 = 136 +MIPS_REG_ENDING = 137 +MIPS_REG_ZERO = MIPS_REG_0 +MIPS_REG_AT = MIPS_REG_1 +MIPS_REG_V0 = MIPS_REG_2 +MIPS_REG_V1 = MIPS_REG_3 +MIPS_REG_A0 = MIPS_REG_4 +MIPS_REG_A1 = MIPS_REG_5 +MIPS_REG_A2 = MIPS_REG_6 +MIPS_REG_A3 = MIPS_REG_7 +MIPS_REG_T0 = MIPS_REG_8 +MIPS_REG_T1 = MIPS_REG_9 +MIPS_REG_T2 = MIPS_REG_10 +MIPS_REG_T3 = MIPS_REG_11 +MIPS_REG_T4 = MIPS_REG_12 +MIPS_REG_T5 = MIPS_REG_13 +MIPS_REG_T6 = MIPS_REG_14 +MIPS_REG_T7 = MIPS_REG_15 +MIPS_REG_S0 = MIPS_REG_16 +MIPS_REG_S1 = MIPS_REG_17 +MIPS_REG_S2 = MIPS_REG_18 +MIPS_REG_S3 = MIPS_REG_19 +MIPS_REG_S4 = MIPS_REG_20 +MIPS_REG_S5 = MIPS_REG_21 +MIPS_REG_S6 = MIPS_REG_22 +MIPS_REG_S7 = MIPS_REG_23 +MIPS_REG_T8 = MIPS_REG_24 +MIPS_REG_T9 = MIPS_REG_25 +MIPS_REG_K0 = MIPS_REG_26 +MIPS_REG_K1 = MIPS_REG_27 +MIPS_REG_GP = MIPS_REG_28 +MIPS_REG_SP = MIPS_REG_29 +MIPS_REG_FP = MIPS_REG_30 +MIPS_REG_S8 = MIPS_REG_30 +MIPS_REG_RA = MIPS_REG_31 +MIPS_REG_HI0 = MIPS_REG_AC0 +MIPS_REG_HI1 = MIPS_REG_AC1 +MIPS_REG_HI2 = MIPS_REG_AC2 +MIPS_REG_HI3 = MIPS_REG_AC3 +MIPS_REG_LO0 = MIPS_REG_HI0 +MIPS_REG_LO1 = MIPS_REG_HI1 +MIPS_REG_LO2 = MIPS_REG_HI2 +MIPS_REG_LO3 = MIPS_REG_HI3 + +MIPS_INS_INVALID = 0 +MIPS_INS_ABSQ_S = 1 +MIPS_INS_ADD = 2 +MIPS_INS_ADDIUPC = 3 +MIPS_INS_ADDIUR1SP = 4 +MIPS_INS_ADDIUR2 = 5 +MIPS_INS_ADDIUS5 = 6 +MIPS_INS_ADDIUSP = 7 +MIPS_INS_ADDQH = 8 +MIPS_INS_ADDQH_R = 9 +MIPS_INS_ADDQ = 10 +MIPS_INS_ADDQ_S = 11 +MIPS_INS_ADDSC = 12 +MIPS_INS_ADDS_A = 13 +MIPS_INS_ADDS_S = 14 +MIPS_INS_ADDS_U = 15 +MIPS_INS_ADDU16 = 16 +MIPS_INS_ADDUH = 17 +MIPS_INS_ADDUH_R = 18 +MIPS_INS_ADDU = 19 +MIPS_INS_ADDU_S = 20 +MIPS_INS_ADDVI = 21 +MIPS_INS_ADDV = 22 +MIPS_INS_ADDWC = 23 +MIPS_INS_ADD_A = 24 +MIPS_INS_ADDI = 25 +MIPS_INS_ADDIU = 26 +MIPS_INS_ALIGN = 27 +MIPS_INS_ALUIPC = 28 +MIPS_INS_AND = 29 +MIPS_INS_AND16 = 30 +MIPS_INS_ANDI16 = 31 +MIPS_INS_ANDI = 32 +MIPS_INS_APPEND = 33 +MIPS_INS_ASUB_S = 34 +MIPS_INS_ASUB_U = 35 +MIPS_INS_AUI = 36 +MIPS_INS_AUIPC = 37 +MIPS_INS_AVER_S = 38 +MIPS_INS_AVER_U = 39 +MIPS_INS_AVE_S = 40 +MIPS_INS_AVE_U = 41 +MIPS_INS_B16 = 42 +MIPS_INS_BADDU = 43 +MIPS_INS_BAL = 44 +MIPS_INS_BALC = 45 +MIPS_INS_BALIGN = 46 +MIPS_INS_BBIT0 = 47 +MIPS_INS_BBIT032 = 48 +MIPS_INS_BBIT1 = 49 +MIPS_INS_BBIT132 = 50 +MIPS_INS_BC = 51 +MIPS_INS_BC0F = 52 +MIPS_INS_BC0FL = 53 +MIPS_INS_BC0T = 54 +MIPS_INS_BC0TL = 55 +MIPS_INS_BC1EQZ = 56 +MIPS_INS_BC1F = 57 +MIPS_INS_BC1FL = 58 +MIPS_INS_BC1NEZ = 59 +MIPS_INS_BC1T = 60 +MIPS_INS_BC1TL = 61 +MIPS_INS_BC2EQZ = 62 +MIPS_INS_BC2F = 63 +MIPS_INS_BC2FL = 64 +MIPS_INS_BC2NEZ = 65 +MIPS_INS_BC2T = 66 +MIPS_INS_BC2TL = 67 +MIPS_INS_BC3F = 68 +MIPS_INS_BC3FL = 69 +MIPS_INS_BC3T = 70 +MIPS_INS_BC3TL = 71 +MIPS_INS_BCLRI = 72 +MIPS_INS_BCLR = 73 +MIPS_INS_BEQ = 74 +MIPS_INS_BEQC = 75 +MIPS_INS_BEQL = 76 +MIPS_INS_BEQZ16 = 77 +MIPS_INS_BEQZALC = 78 +MIPS_INS_BEQZC = 79 +MIPS_INS_BGEC = 80 +MIPS_INS_BGEUC = 81 +MIPS_INS_BGEZ = 82 +MIPS_INS_BGEZAL = 83 +MIPS_INS_BGEZALC = 84 +MIPS_INS_BGEZALL = 85 +MIPS_INS_BGEZALS = 86 +MIPS_INS_BGEZC = 87 +MIPS_INS_BGEZL = 88 +MIPS_INS_BGTZ = 89 +MIPS_INS_BGTZALC = 90 +MIPS_INS_BGTZC = 91 +MIPS_INS_BGTZL = 92 +MIPS_INS_BINSLI = 93 +MIPS_INS_BINSL = 94 +MIPS_INS_BINSRI = 95 +MIPS_INS_BINSR = 96 +MIPS_INS_BITREV = 97 +MIPS_INS_BITSWAP = 98 +MIPS_INS_BLEZ = 99 +MIPS_INS_BLEZALC = 100 +MIPS_INS_BLEZC = 101 +MIPS_INS_BLEZL = 102 +MIPS_INS_BLTC = 103 +MIPS_INS_BLTUC = 104 +MIPS_INS_BLTZ = 105 +MIPS_INS_BLTZAL = 106 +MIPS_INS_BLTZALC = 107 +MIPS_INS_BLTZALL = 108 +MIPS_INS_BLTZALS = 109 +MIPS_INS_BLTZC = 110 +MIPS_INS_BLTZL = 111 +MIPS_INS_BMNZI = 112 +MIPS_INS_BMNZ = 113 +MIPS_INS_BMZI = 114 +MIPS_INS_BMZ = 115 +MIPS_INS_BNE = 116 +MIPS_INS_BNEC = 117 +MIPS_INS_BNEGI = 118 +MIPS_INS_BNEG = 119 +MIPS_INS_BNEL = 120 +MIPS_INS_BNEZ16 = 121 +MIPS_INS_BNEZALC = 122 +MIPS_INS_BNEZC = 123 +MIPS_INS_BNVC = 124 +MIPS_INS_BNZ = 125 +MIPS_INS_BOVC = 126 +MIPS_INS_BPOSGE32 = 127 +MIPS_INS_BREAK = 128 +MIPS_INS_BREAK16 = 129 +MIPS_INS_BSELI = 130 +MIPS_INS_BSEL = 131 +MIPS_INS_BSETI = 132 +MIPS_INS_BSET = 133 +MIPS_INS_BZ = 134 +MIPS_INS_BEQZ = 135 +MIPS_INS_B = 136 +MIPS_INS_BNEZ = 137 +MIPS_INS_BTEQZ = 138 +MIPS_INS_BTNEZ = 139 +MIPS_INS_CACHE = 140 +MIPS_INS_CEIL = 141 +MIPS_INS_CEQI = 142 +MIPS_INS_CEQ = 143 +MIPS_INS_CFC1 = 144 +MIPS_INS_CFCMSA = 145 +MIPS_INS_CINS = 146 +MIPS_INS_CINS32 = 147 +MIPS_INS_CLASS = 148 +MIPS_INS_CLEI_S = 149 +MIPS_INS_CLEI_U = 150 +MIPS_INS_CLE_S = 151 +MIPS_INS_CLE_U = 152 +MIPS_INS_CLO = 153 +MIPS_INS_CLTI_S = 154 +MIPS_INS_CLTI_U = 155 +MIPS_INS_CLT_S = 156 +MIPS_INS_CLT_U = 157 +MIPS_INS_CLZ = 158 +MIPS_INS_CMPGDU = 159 +MIPS_INS_CMPGU = 160 +MIPS_INS_CMPU = 161 +MIPS_INS_CMP = 162 +MIPS_INS_COPY_S = 163 +MIPS_INS_COPY_U = 164 +MIPS_INS_CTC1 = 165 +MIPS_INS_CTCMSA = 166 +MIPS_INS_CVT = 167 +MIPS_INS_C = 168 +MIPS_INS_CMPI = 169 +MIPS_INS_DADD = 170 +MIPS_INS_DADDI = 171 +MIPS_INS_DADDIU = 172 +MIPS_INS_DADDU = 173 +MIPS_INS_DAHI = 174 +MIPS_INS_DALIGN = 175 +MIPS_INS_DATI = 176 +MIPS_INS_DAUI = 177 +MIPS_INS_DBITSWAP = 178 +MIPS_INS_DCLO = 179 +MIPS_INS_DCLZ = 180 +MIPS_INS_DDIV = 181 +MIPS_INS_DDIVU = 182 +MIPS_INS_DERET = 183 +MIPS_INS_DEXT = 184 +MIPS_INS_DEXTM = 185 +MIPS_INS_DEXTU = 186 +MIPS_INS_DI = 187 +MIPS_INS_DINS = 188 +MIPS_INS_DINSM = 189 +MIPS_INS_DINSU = 190 +MIPS_INS_DIV = 191 +MIPS_INS_DIVU = 192 +MIPS_INS_DIV_S = 193 +MIPS_INS_DIV_U = 194 +MIPS_INS_DLSA = 195 +MIPS_INS_DMFC0 = 196 +MIPS_INS_DMFC1 = 197 +MIPS_INS_DMFC2 = 198 +MIPS_INS_DMOD = 199 +MIPS_INS_DMODU = 200 +MIPS_INS_DMTC0 = 201 +MIPS_INS_DMTC1 = 202 +MIPS_INS_DMTC2 = 203 +MIPS_INS_DMUH = 204 +MIPS_INS_DMUHU = 205 +MIPS_INS_DMUL = 206 +MIPS_INS_DMULT = 207 +MIPS_INS_DMULTU = 208 +MIPS_INS_DMULU = 209 +MIPS_INS_DOTP_S = 210 +MIPS_INS_DOTP_U = 211 +MIPS_INS_DPADD_S = 212 +MIPS_INS_DPADD_U = 213 +MIPS_INS_DPAQX_SA = 214 +MIPS_INS_DPAQX_S = 215 +MIPS_INS_DPAQ_SA = 216 +MIPS_INS_DPAQ_S = 217 +MIPS_INS_DPAU = 218 +MIPS_INS_DPAX = 219 +MIPS_INS_DPA = 220 +MIPS_INS_DPOP = 221 +MIPS_INS_DPSQX_SA = 222 +MIPS_INS_DPSQX_S = 223 +MIPS_INS_DPSQ_SA = 224 +MIPS_INS_DPSQ_S = 225 +MIPS_INS_DPSUB_S = 226 +MIPS_INS_DPSUB_U = 227 +MIPS_INS_DPSU = 228 +MIPS_INS_DPSX = 229 +MIPS_INS_DPS = 230 +MIPS_INS_DROTR = 231 +MIPS_INS_DROTR32 = 232 +MIPS_INS_DROTRV = 233 +MIPS_INS_DSBH = 234 +MIPS_INS_DSHD = 235 +MIPS_INS_DSLL = 236 +MIPS_INS_DSLL32 = 237 +MIPS_INS_DSLLV = 238 +MIPS_INS_DSRA = 239 +MIPS_INS_DSRA32 = 240 +MIPS_INS_DSRAV = 241 +MIPS_INS_DSRL = 242 +MIPS_INS_DSRL32 = 243 +MIPS_INS_DSRLV = 244 +MIPS_INS_DSUB = 245 +MIPS_INS_DSUBU = 246 +MIPS_INS_EHB = 247 +MIPS_INS_EI = 248 +MIPS_INS_ERET = 249 +MIPS_INS_EXT = 250 +MIPS_INS_EXTP = 251 +MIPS_INS_EXTPDP = 252 +MIPS_INS_EXTPDPV = 253 +MIPS_INS_EXTPV = 254 +MIPS_INS_EXTRV_RS = 255 +MIPS_INS_EXTRV_R = 256 +MIPS_INS_EXTRV_S = 257 +MIPS_INS_EXTRV = 258 +MIPS_INS_EXTR_RS = 259 +MIPS_INS_EXTR_R = 260 +MIPS_INS_EXTR_S = 261 +MIPS_INS_EXTR = 262 +MIPS_INS_EXTS = 263 +MIPS_INS_EXTS32 = 264 +MIPS_INS_ABS = 265 +MIPS_INS_FADD = 266 +MIPS_INS_FCAF = 267 +MIPS_INS_FCEQ = 268 +MIPS_INS_FCLASS = 269 +MIPS_INS_FCLE = 270 +MIPS_INS_FCLT = 271 +MIPS_INS_FCNE = 272 +MIPS_INS_FCOR = 273 +MIPS_INS_FCUEQ = 274 +MIPS_INS_FCULE = 275 +MIPS_INS_FCULT = 276 +MIPS_INS_FCUNE = 277 +MIPS_INS_FCUN = 278 +MIPS_INS_FDIV = 279 +MIPS_INS_FEXDO = 280 +MIPS_INS_FEXP2 = 281 +MIPS_INS_FEXUPL = 282 +MIPS_INS_FEXUPR = 283 +MIPS_INS_FFINT_S = 284 +MIPS_INS_FFINT_U = 285 +MIPS_INS_FFQL = 286 +MIPS_INS_FFQR = 287 +MIPS_INS_FILL = 288 +MIPS_INS_FLOG2 = 289 +MIPS_INS_FLOOR = 290 +MIPS_INS_FMADD = 291 +MIPS_INS_FMAX_A = 292 +MIPS_INS_FMAX = 293 +MIPS_INS_FMIN_A = 294 +MIPS_INS_FMIN = 295 +MIPS_INS_MOV = 296 +MIPS_INS_FMSUB = 297 +MIPS_INS_FMUL = 298 +MIPS_INS_MUL = 299 +MIPS_INS_NEG = 300 +MIPS_INS_FRCP = 301 +MIPS_INS_FRINT = 302 +MIPS_INS_FRSQRT = 303 +MIPS_INS_FSAF = 304 +MIPS_INS_FSEQ = 305 +MIPS_INS_FSLE = 306 +MIPS_INS_FSLT = 307 +MIPS_INS_FSNE = 308 +MIPS_INS_FSOR = 309 +MIPS_INS_FSQRT = 310 +MIPS_INS_SQRT = 311 +MIPS_INS_FSUB = 312 +MIPS_INS_SUB = 313 +MIPS_INS_FSUEQ = 314 +MIPS_INS_FSULE = 315 +MIPS_INS_FSULT = 316 +MIPS_INS_FSUNE = 317 +MIPS_INS_FSUN = 318 +MIPS_INS_FTINT_S = 319 +MIPS_INS_FTINT_U = 320 +MIPS_INS_FTQ = 321 +MIPS_INS_FTRUNC_S = 322 +MIPS_INS_FTRUNC_U = 323 +MIPS_INS_HADD_S = 324 +MIPS_INS_HADD_U = 325 +MIPS_INS_HSUB_S = 326 +MIPS_INS_HSUB_U = 327 +MIPS_INS_ILVEV = 328 +MIPS_INS_ILVL = 329 +MIPS_INS_ILVOD = 330 +MIPS_INS_ILVR = 331 +MIPS_INS_INS = 332 +MIPS_INS_INSERT = 333 +MIPS_INS_INSV = 334 +MIPS_INS_INSVE = 335 +MIPS_INS_J = 336 +MIPS_INS_JAL = 337 +MIPS_INS_JALR = 338 +MIPS_INS_JALRS16 = 339 +MIPS_INS_JALRS = 340 +MIPS_INS_JALS = 341 +MIPS_INS_JALX = 342 +MIPS_INS_JIALC = 343 +MIPS_INS_JIC = 344 +MIPS_INS_JR = 345 +MIPS_INS_JR16 = 346 +MIPS_INS_JRADDIUSP = 347 +MIPS_INS_JRC = 348 +MIPS_INS_JALRC = 349 +MIPS_INS_LB = 350 +MIPS_INS_LBU16 = 351 +MIPS_INS_LBUX = 352 +MIPS_INS_LBU = 353 +MIPS_INS_LD = 354 +MIPS_INS_LDC1 = 355 +MIPS_INS_LDC2 = 356 +MIPS_INS_LDC3 = 357 +MIPS_INS_LDI = 358 +MIPS_INS_LDL = 359 +MIPS_INS_LDPC = 360 +MIPS_INS_LDR = 361 +MIPS_INS_LDXC1 = 362 +MIPS_INS_LH = 363 +MIPS_INS_LHU16 = 364 +MIPS_INS_LHX = 365 +MIPS_INS_LHU = 366 +MIPS_INS_LI16 = 367 +MIPS_INS_LL = 368 +MIPS_INS_LLD = 369 +MIPS_INS_LSA = 370 +MIPS_INS_LUXC1 = 371 +MIPS_INS_LUI = 372 +MIPS_INS_LW = 373 +MIPS_INS_LW16 = 374 +MIPS_INS_LWC1 = 375 +MIPS_INS_LWC2 = 376 +MIPS_INS_LWC3 = 377 +MIPS_INS_LWL = 378 +MIPS_INS_LWM16 = 379 +MIPS_INS_LWM32 = 380 +MIPS_INS_LWPC = 381 +MIPS_INS_LWP = 382 +MIPS_INS_LWR = 383 +MIPS_INS_LWUPC = 384 +MIPS_INS_LWU = 385 +MIPS_INS_LWX = 386 +MIPS_INS_LWXC1 = 387 +MIPS_INS_LWXS = 388 +MIPS_INS_LI = 389 +MIPS_INS_MADD = 390 +MIPS_INS_MADDF = 391 +MIPS_INS_MADDR_Q = 392 +MIPS_INS_MADDU = 393 +MIPS_INS_MADDV = 394 +MIPS_INS_MADD_Q = 395 +MIPS_INS_MAQ_SA = 396 +MIPS_INS_MAQ_S = 397 +MIPS_INS_MAXA = 398 +MIPS_INS_MAXI_S = 399 +MIPS_INS_MAXI_U = 400 +MIPS_INS_MAX_A = 401 +MIPS_INS_MAX = 402 +MIPS_INS_MAX_S = 403 +MIPS_INS_MAX_U = 404 +MIPS_INS_MFC0 = 405 +MIPS_INS_MFC1 = 406 +MIPS_INS_MFC2 = 407 +MIPS_INS_MFHC1 = 408 +MIPS_INS_MFHI = 409 +MIPS_INS_MFLO = 410 +MIPS_INS_MINA = 411 +MIPS_INS_MINI_S = 412 +MIPS_INS_MINI_U = 413 +MIPS_INS_MIN_A = 414 +MIPS_INS_MIN = 415 +MIPS_INS_MIN_S = 416 +MIPS_INS_MIN_U = 417 +MIPS_INS_MOD = 418 +MIPS_INS_MODSUB = 419 +MIPS_INS_MODU = 420 +MIPS_INS_MOD_S = 421 +MIPS_INS_MOD_U = 422 +MIPS_INS_MOVE = 423 +MIPS_INS_MOVEP = 424 +MIPS_INS_MOVF = 425 +MIPS_INS_MOVN = 426 +MIPS_INS_MOVT = 427 +MIPS_INS_MOVZ = 428 +MIPS_INS_MSUB = 429 +MIPS_INS_MSUBF = 430 +MIPS_INS_MSUBR_Q = 431 +MIPS_INS_MSUBU = 432 +MIPS_INS_MSUBV = 433 +MIPS_INS_MSUB_Q = 434 +MIPS_INS_MTC0 = 435 +MIPS_INS_MTC1 = 436 +MIPS_INS_MTC2 = 437 +MIPS_INS_MTHC1 = 438 +MIPS_INS_MTHI = 439 +MIPS_INS_MTHLIP = 440 +MIPS_INS_MTLO = 441 +MIPS_INS_MTM0 = 442 +MIPS_INS_MTM1 = 443 +MIPS_INS_MTM2 = 444 +MIPS_INS_MTP0 = 445 +MIPS_INS_MTP1 = 446 +MIPS_INS_MTP2 = 447 +MIPS_INS_MUH = 448 +MIPS_INS_MUHU = 449 +MIPS_INS_MULEQ_S = 450 +MIPS_INS_MULEU_S = 451 +MIPS_INS_MULQ_RS = 452 +MIPS_INS_MULQ_S = 453 +MIPS_INS_MULR_Q = 454 +MIPS_INS_MULSAQ_S = 455 +MIPS_INS_MULSA = 456 +MIPS_INS_MULT = 457 +MIPS_INS_MULTU = 458 +MIPS_INS_MULU = 459 +MIPS_INS_MULV = 460 +MIPS_INS_MUL_Q = 461 +MIPS_INS_MUL_S = 462 +MIPS_INS_NLOC = 463 +MIPS_INS_NLZC = 464 +MIPS_INS_NMADD = 465 +MIPS_INS_NMSUB = 466 +MIPS_INS_NOR = 467 +MIPS_INS_NORI = 468 +MIPS_INS_NOT16 = 469 +MIPS_INS_NOT = 470 +MIPS_INS_OR = 471 +MIPS_INS_OR16 = 472 +MIPS_INS_ORI = 473 +MIPS_INS_PACKRL = 474 +MIPS_INS_PAUSE = 475 +MIPS_INS_PCKEV = 476 +MIPS_INS_PCKOD = 477 +MIPS_INS_PCNT = 478 +MIPS_INS_PICK = 479 +MIPS_INS_POP = 480 +MIPS_INS_PRECEQU = 481 +MIPS_INS_PRECEQ = 482 +MIPS_INS_PRECEU = 483 +MIPS_INS_PRECRQU_S = 484 +MIPS_INS_PRECRQ = 485 +MIPS_INS_PRECRQ_RS = 486 +MIPS_INS_PRECR = 487 +MIPS_INS_PRECR_SRA = 488 +MIPS_INS_PRECR_SRA_R = 489 +MIPS_INS_PREF = 490 +MIPS_INS_PREPEND = 491 +MIPS_INS_RADDU = 492 +MIPS_INS_RDDSP = 493 +MIPS_INS_RDHWR = 494 +MIPS_INS_REPLV = 495 +MIPS_INS_REPL = 496 +MIPS_INS_RINT = 497 +MIPS_INS_ROTR = 498 +MIPS_INS_ROTRV = 499 +MIPS_INS_ROUND = 500 +MIPS_INS_SAT_S = 501 +MIPS_INS_SAT_U = 502 +MIPS_INS_SB = 503 +MIPS_INS_SB16 = 504 +MIPS_INS_SC = 505 +MIPS_INS_SCD = 506 +MIPS_INS_SD = 507 +MIPS_INS_SDBBP = 508 +MIPS_INS_SDBBP16 = 509 +MIPS_INS_SDC1 = 510 +MIPS_INS_SDC2 = 511 +MIPS_INS_SDC3 = 512 +MIPS_INS_SDL = 513 +MIPS_INS_SDR = 514 +MIPS_INS_SDXC1 = 515 +MIPS_INS_SEB = 516 +MIPS_INS_SEH = 517 +MIPS_INS_SELEQZ = 518 +MIPS_INS_SELNEZ = 519 +MIPS_INS_SEL = 520 +MIPS_INS_SEQ = 521 +MIPS_INS_SEQI = 522 +MIPS_INS_SH = 523 +MIPS_INS_SH16 = 524 +MIPS_INS_SHF = 525 +MIPS_INS_SHILO = 526 +MIPS_INS_SHILOV = 527 +MIPS_INS_SHLLV = 528 +MIPS_INS_SHLLV_S = 529 +MIPS_INS_SHLL = 530 +MIPS_INS_SHLL_S = 531 +MIPS_INS_SHRAV = 532 +MIPS_INS_SHRAV_R = 533 +MIPS_INS_SHRA = 534 +MIPS_INS_SHRA_R = 535 +MIPS_INS_SHRLV = 536 +MIPS_INS_SHRL = 537 +MIPS_INS_SLDI = 538 +MIPS_INS_SLD = 539 +MIPS_INS_SLL = 540 +MIPS_INS_SLL16 = 541 +MIPS_INS_SLLI = 542 +MIPS_INS_SLLV = 543 +MIPS_INS_SLT = 544 +MIPS_INS_SLTI = 545 +MIPS_INS_SLTIU = 546 +MIPS_INS_SLTU = 547 +MIPS_INS_SNE = 548 +MIPS_INS_SNEI = 549 +MIPS_INS_SPLATI = 550 +MIPS_INS_SPLAT = 551 +MIPS_INS_SRA = 552 +MIPS_INS_SRAI = 553 +MIPS_INS_SRARI = 554 +MIPS_INS_SRAR = 555 +MIPS_INS_SRAV = 556 +MIPS_INS_SRL = 557 +MIPS_INS_SRL16 = 558 +MIPS_INS_SRLI = 559 +MIPS_INS_SRLRI = 560 +MIPS_INS_SRLR = 561 +MIPS_INS_SRLV = 562 +MIPS_INS_SSNOP = 563 +MIPS_INS_ST = 564 +MIPS_INS_SUBQH = 565 +MIPS_INS_SUBQH_R = 566 +MIPS_INS_SUBQ = 567 +MIPS_INS_SUBQ_S = 568 +MIPS_INS_SUBSUS_U = 569 +MIPS_INS_SUBSUU_S = 570 +MIPS_INS_SUBS_S = 571 +MIPS_INS_SUBS_U = 572 +MIPS_INS_SUBU16 = 573 +MIPS_INS_SUBUH = 574 +MIPS_INS_SUBUH_R = 575 +MIPS_INS_SUBU = 576 +MIPS_INS_SUBU_S = 577 +MIPS_INS_SUBVI = 578 +MIPS_INS_SUBV = 579 +MIPS_INS_SUXC1 = 580 +MIPS_INS_SW = 581 +MIPS_INS_SW16 = 582 +MIPS_INS_SWC1 = 583 +MIPS_INS_SWC2 = 584 +MIPS_INS_SWC3 = 585 +MIPS_INS_SWL = 586 +MIPS_INS_SWM16 = 587 +MIPS_INS_SWM32 = 588 +MIPS_INS_SWP = 589 +MIPS_INS_SWR = 590 +MIPS_INS_SWXC1 = 591 +MIPS_INS_SYNC = 592 +MIPS_INS_SYNCI = 593 +MIPS_INS_SYSCALL = 594 +MIPS_INS_TEQ = 595 +MIPS_INS_TEQI = 596 +MIPS_INS_TGE = 597 +MIPS_INS_TGEI = 598 +MIPS_INS_TGEIU = 599 +MIPS_INS_TGEU = 600 +MIPS_INS_TLBP = 601 +MIPS_INS_TLBR = 602 +MIPS_INS_TLBWI = 603 +MIPS_INS_TLBWR = 604 +MIPS_INS_TLT = 605 +MIPS_INS_TLTI = 606 +MIPS_INS_TLTIU = 607 +MIPS_INS_TLTU = 608 +MIPS_INS_TNE = 609 +MIPS_INS_TNEI = 610 +MIPS_INS_TRUNC = 611 +MIPS_INS_V3MULU = 612 +MIPS_INS_VMM0 = 613 +MIPS_INS_VMULU = 614 +MIPS_INS_VSHF = 615 +MIPS_INS_WAIT = 616 +MIPS_INS_WRDSP = 617 +MIPS_INS_WSBH = 618 +MIPS_INS_XOR = 619 +MIPS_INS_XOR16 = 620 +MIPS_INS_XORI = 621 + +# some alias instructions +MIPS_INS_NOP = 622 +MIPS_INS_NEGU = 623 + +# special instructions +MIPS_INS_JALR_HB = 624 +MIPS_INS_JR_HB = 625 +MIPS_INS_ENDING = 626 + +MIPS_GRP_INVALID = 0 +MIPS_GRP_JUMP = 1 +MIPS_GRP_CALL = 2 +MIPS_GRP_RET = 3 +MIPS_GRP_INT = 4 +MIPS_GRP_IRET = 5 +MIPS_GRP_PRIVILEGE = 6 +MIPS_GRP_BRANCH_RELATIVE = 7 +MIPS_GRP_BITCOUNT = 128 +MIPS_GRP_DSP = 129 +MIPS_GRP_DSPR2 = 130 +MIPS_GRP_FPIDX = 131 +MIPS_GRP_MSA = 132 +MIPS_GRP_MIPS32R2 = 133 +MIPS_GRP_MIPS64 = 134 +MIPS_GRP_MIPS64R2 = 135 +MIPS_GRP_SEINREG = 136 +MIPS_GRP_STDENC = 137 +MIPS_GRP_SWAP = 138 +MIPS_GRP_MICROMIPS = 139 +MIPS_GRP_MIPS16MODE = 140 +MIPS_GRP_FP64BIT = 141 +MIPS_GRP_NONANSFPMATH = 142 +MIPS_GRP_NOTFP64BIT = 143 +MIPS_GRP_NOTINMICROMIPS = 144 +MIPS_GRP_NOTNACL = 145 +MIPS_GRP_NOTMIPS32R6 = 146 +MIPS_GRP_NOTMIPS64R6 = 147 +MIPS_GRP_CNMIPS = 148 +MIPS_GRP_MIPS32 = 149 +MIPS_GRP_MIPS32R6 = 150 +MIPS_GRP_MIPS64R6 = 151 +MIPS_GRP_MIPS2 = 152 +MIPS_GRP_MIPS3 = 153 +MIPS_GRP_MIPS3_32 = 154 +MIPS_GRP_MIPS3_32R2 = 155 +MIPS_GRP_MIPS4_32 = 156 +MIPS_GRP_MIPS4_32R2 = 157 +MIPS_GRP_MIPS5_32R2 = 158 +MIPS_GRP_GP32BIT = 159 +MIPS_GRP_GP64BIT = 160 +MIPS_GRP_ENDING = 161 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx.py b/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx.py new file mode 100644 index 0000000..11b3462 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx.py @@ -0,0 +1,45 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .mos65xx_const import * + +# define the API +class MOS65xxOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_uint8), + ('mem', ctypes.c_uint16), + ) + +class MOS65xxOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', MOS65xxOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsMOS65xx(ctypes.Structure): + _fields_ = ( + ('am', ctypes.c_uint), + ('modifies_flags', ctypes.c_uint8), + ('op_count', ctypes.c_uint8), + ('operands', MOS65xxOp * 3), + ) + +def get_arch_info(a): + return (a.am, a.modifies_flags, copy_ctypes_list(a.operands[:a.op_count])) + + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx_const.py new file mode 100644 index 0000000..11e52f9 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/mos65xx_const.py @@ -0,0 +1,96 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py] + +MOS65XX_REG_INVALID = 0 +MOS65XX_REG_ACC = 1 +MOS65XX_REG_X = 2 +MOS65XX_REG_Y = 3 +MOS65XX_REG_P = 4 +MOS65XX_REG_SP = 5 +MOS65XX_REG_ENDING = 6 + +MOS65XX_AM_NONE = 0 +MOS65XX_AM_IMP = 1 +MOS65XX_AM_ACC = 2 +MOS65XX_AM_ABS = 3 +MOS65XX_AM_ZP = 4 +MOS65XX_AM_IMM = 5 +MOS65XX_AM_ABSX = 6 +MOS65XX_AM_ABSY = 7 +MOS65XX_AM_INDX = 8 +MOS65XX_AM_INDY = 9 +MOS65XX_AM_ZPX = 10 +MOS65XX_AM_ZPY = 11 +MOS65XX_AM_REL = 12 +MOS65XX_AM_IND = 13 + +MOS65XX_INS_INVALID = 0 +MOS65XX_INS_ADC = 1 +MOS65XX_INS_AND = 2 +MOS65XX_INS_ASL = 3 +MOS65XX_INS_BCC = 4 +MOS65XX_INS_BCS = 5 +MOS65XX_INS_BEQ = 6 +MOS65XX_INS_BIT = 7 +MOS65XX_INS_BMI = 8 +MOS65XX_INS_BNE = 9 +MOS65XX_INS_BPL = 10 +MOS65XX_INS_BRK = 11 +MOS65XX_INS_BVC = 12 +MOS65XX_INS_BVS = 13 +MOS65XX_INS_CLC = 14 +MOS65XX_INS_CLD = 15 +MOS65XX_INS_CLI = 16 +MOS65XX_INS_CLV = 17 +MOS65XX_INS_CMP = 18 +MOS65XX_INS_CPX = 19 +MOS65XX_INS_CPY = 20 +MOS65XX_INS_DEC = 21 +MOS65XX_INS_DEX = 22 +MOS65XX_INS_DEY = 23 +MOS65XX_INS_EOR = 24 +MOS65XX_INS_INC = 25 +MOS65XX_INS_INX = 26 +MOS65XX_INS_INY = 27 +MOS65XX_INS_JMP = 28 +MOS65XX_INS_JSR = 29 +MOS65XX_INS_LDA = 30 +MOS65XX_INS_LDX = 31 +MOS65XX_INS_LDY = 32 +MOS65XX_INS_LSR = 33 +MOS65XX_INS_NOP = 34 +MOS65XX_INS_ORA = 35 +MOS65XX_INS_PHA = 36 +MOS65XX_INS_PLA = 37 +MOS65XX_INS_PHP = 38 +MOS65XX_INS_PLP = 39 +MOS65XX_INS_ROL = 40 +MOS65XX_INS_ROR = 41 +MOS65XX_INS_RTI = 42 +MOS65XX_INS_RTS = 43 +MOS65XX_INS_SBC = 44 +MOS65XX_INS_SEC = 45 +MOS65XX_INS_SED = 46 +MOS65XX_INS_SEI = 47 +MOS65XX_INS_STA = 48 +MOS65XX_INS_STX = 49 +MOS65XX_INS_STY = 50 +MOS65XX_INS_TAX = 51 +MOS65XX_INS_TAY = 52 +MOS65XX_INS_TSX = 53 +MOS65XX_INS_TXA = 54 +MOS65XX_INS_TXS = 55 +MOS65XX_INS_TYA = 56 +MOS65XX_INS_ENDING = 57 + +MOS65XX_GRP_INVALID = 0 +MOS65XX_GRP_JUMP = 1 +MOS65XX_GRP_CALL = 2 +MOS65XX_GRP_RET = 3 +MOS65XX_GRP_IRET = 5 +MOS65XX_GRP_BRANCH_RELATIVE = 6 +MOS65XX_GRP_ENDING = 7 + +MOS65XX_OP_INVALID = 0 +MOS65XX_OP_REG = 1 +MOS65XX_OP_IMM = 2 +MOS65XX_OP_MEM = 3 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/ppc.py b/white_patch_detect/capstone-master/bindings/python/capstone/ppc.py new file mode 100644 index 0000000..6ab177d --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/ppc.py @@ -0,0 +1,63 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .ppc_const import * + +# define the API +class PpcOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('disp', ctypes.c_int32), + ) + +class PpcOpCrx(ctypes.Structure): + _fields_ = ( + ('scale', ctypes.c_uint), + ('reg', ctypes.c_uint), + ('cond', ctypes.c_uint), + ) + +class PpcOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', PpcOpMem), + ('crx', PpcOpCrx), + ) + +class PpcOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', PpcOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + @property + def crx(self): + return self.value.crx + + +class CsPpc(ctypes.Structure): + _fields_ = ( + ('bc', ctypes.c_uint), + ('bh', ctypes.c_uint), + ('update_cr0', ctypes.c_bool), + ('op_count', ctypes.c_uint8), + ('operands', PpcOp * 8), + ) + +def get_arch_info(a): + return (a.bc, a.bh, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/ppc_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/ppc_const.py new file mode 100644 index 0000000..93a941b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/ppc_const.py @@ -0,0 +1,1365 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py] + +PPC_BC_INVALID = 0 +PPC_BC_LT = (0<<5)|12 +PPC_BC_LE = (1<<5)|4 +PPC_BC_EQ = (2<<5)|12 +PPC_BC_GE = (0<<5)|4 +PPC_BC_GT = (1<<5)|12 +PPC_BC_NE = (2<<5)|4 +PPC_BC_UN = (3<<5)|12 +PPC_BC_NU = (3<<5)|4 +PPC_BC_SO = (4<<5)|12 +PPC_BC_NS = (4<<5)|4 + +PPC_BH_INVALID = 0 +PPC_BH_PLUS = 1 +PPC_BH_MINUS = 2 + +PPC_OP_INVALID = 0 +PPC_OP_REG = 1 +PPC_OP_IMM = 2 +PPC_OP_MEM = 3 +PPC_OP_CRX = 64 + +PPC_REG_INVALID = 0 +PPC_REG_CARRY = 1 +PPC_REG_CR0 = 2 +PPC_REG_CR1 = 3 +PPC_REG_CR2 = 4 +PPC_REG_CR3 = 5 +PPC_REG_CR4 = 6 +PPC_REG_CR5 = 7 +PPC_REG_CR6 = 8 +PPC_REG_CR7 = 9 +PPC_REG_CTR = 10 +PPC_REG_F0 = 11 +PPC_REG_F1 = 12 +PPC_REG_F2 = 13 +PPC_REG_F3 = 14 +PPC_REG_F4 = 15 +PPC_REG_F5 = 16 +PPC_REG_F6 = 17 +PPC_REG_F7 = 18 +PPC_REG_F8 = 19 +PPC_REG_F9 = 20 +PPC_REG_F10 = 21 +PPC_REG_F11 = 22 +PPC_REG_F12 = 23 +PPC_REG_F13 = 24 +PPC_REG_F14 = 25 +PPC_REG_F15 = 26 +PPC_REG_F16 = 27 +PPC_REG_F17 = 28 +PPC_REG_F18 = 29 +PPC_REG_F19 = 30 +PPC_REG_F20 = 31 +PPC_REG_F21 = 32 +PPC_REG_F22 = 33 +PPC_REG_F23 = 34 +PPC_REG_F24 = 35 +PPC_REG_F25 = 36 +PPC_REG_F26 = 37 +PPC_REG_F27 = 38 +PPC_REG_F28 = 39 +PPC_REG_F29 = 40 +PPC_REG_F30 = 41 +PPC_REG_F31 = 42 +PPC_REG_LR = 43 +PPC_REG_R0 = 44 +PPC_REG_R1 = 45 +PPC_REG_R2 = 46 +PPC_REG_R3 = 47 +PPC_REG_R4 = 48 +PPC_REG_R5 = 49 +PPC_REG_R6 = 50 +PPC_REG_R7 = 51 +PPC_REG_R8 = 52 +PPC_REG_R9 = 53 +PPC_REG_R10 = 54 +PPC_REG_R11 = 55 +PPC_REG_R12 = 56 +PPC_REG_R13 = 57 +PPC_REG_R14 = 58 +PPC_REG_R15 = 59 +PPC_REG_R16 = 60 +PPC_REG_R17 = 61 +PPC_REG_R18 = 62 +PPC_REG_R19 = 63 +PPC_REG_R20 = 64 +PPC_REG_R21 = 65 +PPC_REG_R22 = 66 +PPC_REG_R23 = 67 +PPC_REG_R24 = 68 +PPC_REG_R25 = 69 +PPC_REG_R26 = 70 +PPC_REG_R27 = 71 +PPC_REG_R28 = 72 +PPC_REG_R29 = 73 +PPC_REG_R30 = 74 +PPC_REG_R31 = 75 +PPC_REG_V0 = 76 +PPC_REG_V1 = 77 +PPC_REG_V2 = 78 +PPC_REG_V3 = 79 +PPC_REG_V4 = 80 +PPC_REG_V5 = 81 +PPC_REG_V6 = 82 +PPC_REG_V7 = 83 +PPC_REG_V8 = 84 +PPC_REG_V9 = 85 +PPC_REG_V10 = 86 +PPC_REG_V11 = 87 +PPC_REG_V12 = 88 +PPC_REG_V13 = 89 +PPC_REG_V14 = 90 +PPC_REG_V15 = 91 +PPC_REG_V16 = 92 +PPC_REG_V17 = 93 +PPC_REG_V18 = 94 +PPC_REG_V19 = 95 +PPC_REG_V20 = 96 +PPC_REG_V21 = 97 +PPC_REG_V22 = 98 +PPC_REG_V23 = 99 +PPC_REG_V24 = 100 +PPC_REG_V25 = 101 +PPC_REG_V26 = 102 +PPC_REG_V27 = 103 +PPC_REG_V28 = 104 +PPC_REG_V29 = 105 +PPC_REG_V30 = 106 +PPC_REG_V31 = 107 +PPC_REG_VRSAVE = 108 +PPC_REG_VS0 = 109 +PPC_REG_VS1 = 110 +PPC_REG_VS2 = 111 +PPC_REG_VS3 = 112 +PPC_REG_VS4 = 113 +PPC_REG_VS5 = 114 +PPC_REG_VS6 = 115 +PPC_REG_VS7 = 116 +PPC_REG_VS8 = 117 +PPC_REG_VS9 = 118 +PPC_REG_VS10 = 119 +PPC_REG_VS11 = 120 +PPC_REG_VS12 = 121 +PPC_REG_VS13 = 122 +PPC_REG_VS14 = 123 +PPC_REG_VS15 = 124 +PPC_REG_VS16 = 125 +PPC_REG_VS17 = 126 +PPC_REG_VS18 = 127 +PPC_REG_VS19 = 128 +PPC_REG_VS20 = 129 +PPC_REG_VS21 = 130 +PPC_REG_VS22 = 131 +PPC_REG_VS23 = 132 +PPC_REG_VS24 = 133 +PPC_REG_VS25 = 134 +PPC_REG_VS26 = 135 +PPC_REG_VS27 = 136 +PPC_REG_VS28 = 137 +PPC_REG_VS29 = 138 +PPC_REG_VS30 = 139 +PPC_REG_VS31 = 140 +PPC_REG_VS32 = 141 +PPC_REG_VS33 = 142 +PPC_REG_VS34 = 143 +PPC_REG_VS35 = 144 +PPC_REG_VS36 = 145 +PPC_REG_VS37 = 146 +PPC_REG_VS38 = 147 +PPC_REG_VS39 = 148 +PPC_REG_VS40 = 149 +PPC_REG_VS41 = 150 +PPC_REG_VS42 = 151 +PPC_REG_VS43 = 152 +PPC_REG_VS44 = 153 +PPC_REG_VS45 = 154 +PPC_REG_VS46 = 155 +PPC_REG_VS47 = 156 +PPC_REG_VS48 = 157 +PPC_REG_VS49 = 158 +PPC_REG_VS50 = 159 +PPC_REG_VS51 = 160 +PPC_REG_VS52 = 161 +PPC_REG_VS53 = 162 +PPC_REG_VS54 = 163 +PPC_REG_VS55 = 164 +PPC_REG_VS56 = 165 +PPC_REG_VS57 = 166 +PPC_REG_VS58 = 167 +PPC_REG_VS59 = 168 +PPC_REG_VS60 = 169 +PPC_REG_VS61 = 170 +PPC_REG_VS62 = 171 +PPC_REG_VS63 = 172 +PPC_REG_Q0 = 173 +PPC_REG_Q1 = 174 +PPC_REG_Q2 = 175 +PPC_REG_Q3 = 176 +PPC_REG_Q4 = 177 +PPC_REG_Q5 = 178 +PPC_REG_Q6 = 179 +PPC_REG_Q7 = 180 +PPC_REG_Q8 = 181 +PPC_REG_Q9 = 182 +PPC_REG_Q10 = 183 +PPC_REG_Q11 = 184 +PPC_REG_Q12 = 185 +PPC_REG_Q13 = 186 +PPC_REG_Q14 = 187 +PPC_REG_Q15 = 188 +PPC_REG_Q16 = 189 +PPC_REG_Q17 = 190 +PPC_REG_Q18 = 191 +PPC_REG_Q19 = 192 +PPC_REG_Q20 = 193 +PPC_REG_Q21 = 194 +PPC_REG_Q22 = 195 +PPC_REG_Q23 = 196 +PPC_REG_Q24 = 197 +PPC_REG_Q25 = 198 +PPC_REG_Q26 = 199 +PPC_REG_Q27 = 200 +PPC_REG_Q28 = 201 +PPC_REG_Q29 = 202 +PPC_REG_Q30 = 203 +PPC_REG_Q31 = 204 +PPC_REG_RM = 205 +PPC_REG_CTR8 = 206 +PPC_REG_LR8 = 207 +PPC_REG_CR1EQ = 208 +PPC_REG_X2 = 209 +PPC_REG_ENDING = 210 + +PPC_INS_INVALID = 0 +PPC_INS_ADD = 1 +PPC_INS_ADDC = 2 +PPC_INS_ADDE = 3 +PPC_INS_ADDI = 4 +PPC_INS_ADDIC = 5 +PPC_INS_ADDIS = 6 +PPC_INS_ADDME = 7 +PPC_INS_ADDZE = 8 +PPC_INS_AND = 9 +PPC_INS_ANDC = 10 +PPC_INS_ANDIS = 11 +PPC_INS_ANDI = 12 +PPC_INS_ATTN = 13 +PPC_INS_B = 14 +PPC_INS_BA = 15 +PPC_INS_BC = 16 +PPC_INS_BCCTR = 17 +PPC_INS_BCCTRL = 18 +PPC_INS_BCL = 19 +PPC_INS_BCLR = 20 +PPC_INS_BCLRL = 21 +PPC_INS_BCTR = 22 +PPC_INS_BCTRL = 23 +PPC_INS_BCT = 24 +PPC_INS_BDNZ = 25 +PPC_INS_BDNZA = 26 +PPC_INS_BDNZL = 27 +PPC_INS_BDNZLA = 28 +PPC_INS_BDNZLR = 29 +PPC_INS_BDNZLRL = 30 +PPC_INS_BDZ = 31 +PPC_INS_BDZA = 32 +PPC_INS_BDZL = 33 +PPC_INS_BDZLA = 34 +PPC_INS_BDZLR = 35 +PPC_INS_BDZLRL = 36 +PPC_INS_BL = 37 +PPC_INS_BLA = 38 +PPC_INS_BLR = 39 +PPC_INS_BLRL = 40 +PPC_INS_BRINC = 41 +PPC_INS_CMPB = 42 +PPC_INS_CMPD = 43 +PPC_INS_CMPDI = 44 +PPC_INS_CMPLD = 45 +PPC_INS_CMPLDI = 46 +PPC_INS_CMPLW = 47 +PPC_INS_CMPLWI = 48 +PPC_INS_CMPW = 49 +PPC_INS_CMPWI = 50 +PPC_INS_CNTLZD = 51 +PPC_INS_CNTLZW = 52 +PPC_INS_CREQV = 53 +PPC_INS_CRXOR = 54 +PPC_INS_CRAND = 55 +PPC_INS_CRANDC = 56 +PPC_INS_CRNAND = 57 +PPC_INS_CRNOR = 58 +PPC_INS_CROR = 59 +PPC_INS_CRORC = 60 +PPC_INS_DCBA = 61 +PPC_INS_DCBF = 62 +PPC_INS_DCBI = 63 +PPC_INS_DCBST = 64 +PPC_INS_DCBT = 65 +PPC_INS_DCBTST = 66 +PPC_INS_DCBZ = 67 +PPC_INS_DCBZL = 68 +PPC_INS_DCCCI = 69 +PPC_INS_DIVD = 70 +PPC_INS_DIVDU = 71 +PPC_INS_DIVW = 72 +PPC_INS_DIVWU = 73 +PPC_INS_DSS = 74 +PPC_INS_DSSALL = 75 +PPC_INS_DST = 76 +PPC_INS_DSTST = 77 +PPC_INS_DSTSTT = 78 +PPC_INS_DSTT = 79 +PPC_INS_EQV = 80 +PPC_INS_EVABS = 81 +PPC_INS_EVADDIW = 82 +PPC_INS_EVADDSMIAAW = 83 +PPC_INS_EVADDSSIAAW = 84 +PPC_INS_EVADDUMIAAW = 85 +PPC_INS_EVADDUSIAAW = 86 +PPC_INS_EVADDW = 87 +PPC_INS_EVAND = 88 +PPC_INS_EVANDC = 89 +PPC_INS_EVCMPEQ = 90 +PPC_INS_EVCMPGTS = 91 +PPC_INS_EVCMPGTU = 92 +PPC_INS_EVCMPLTS = 93 +PPC_INS_EVCMPLTU = 94 +PPC_INS_EVCNTLSW = 95 +PPC_INS_EVCNTLZW = 96 +PPC_INS_EVDIVWS = 97 +PPC_INS_EVDIVWU = 98 +PPC_INS_EVEQV = 99 +PPC_INS_EVEXTSB = 100 +PPC_INS_EVEXTSH = 101 +PPC_INS_EVLDD = 102 +PPC_INS_EVLDDX = 103 +PPC_INS_EVLDH = 104 +PPC_INS_EVLDHX = 105 +PPC_INS_EVLDW = 106 +PPC_INS_EVLDWX = 107 +PPC_INS_EVLHHESPLAT = 108 +PPC_INS_EVLHHESPLATX = 109 +PPC_INS_EVLHHOSSPLAT = 110 +PPC_INS_EVLHHOSSPLATX = 111 +PPC_INS_EVLHHOUSPLAT = 112 +PPC_INS_EVLHHOUSPLATX = 113 +PPC_INS_EVLWHE = 114 +PPC_INS_EVLWHEX = 115 +PPC_INS_EVLWHOS = 116 +PPC_INS_EVLWHOSX = 117 +PPC_INS_EVLWHOU = 118 +PPC_INS_EVLWHOUX = 119 +PPC_INS_EVLWHSPLAT = 120 +PPC_INS_EVLWHSPLATX = 121 +PPC_INS_EVLWWSPLAT = 122 +PPC_INS_EVLWWSPLATX = 123 +PPC_INS_EVMERGEHI = 124 +PPC_INS_EVMERGEHILO = 125 +PPC_INS_EVMERGELO = 126 +PPC_INS_EVMERGELOHI = 127 +PPC_INS_EVMHEGSMFAA = 128 +PPC_INS_EVMHEGSMFAN = 129 +PPC_INS_EVMHEGSMIAA = 130 +PPC_INS_EVMHEGSMIAN = 131 +PPC_INS_EVMHEGUMIAA = 132 +PPC_INS_EVMHEGUMIAN = 133 +PPC_INS_EVMHESMF = 134 +PPC_INS_EVMHESMFA = 135 +PPC_INS_EVMHESMFAAW = 136 +PPC_INS_EVMHESMFANW = 137 +PPC_INS_EVMHESMI = 138 +PPC_INS_EVMHESMIA = 139 +PPC_INS_EVMHESMIAAW = 140 +PPC_INS_EVMHESMIANW = 141 +PPC_INS_EVMHESSF = 142 +PPC_INS_EVMHESSFA = 143 +PPC_INS_EVMHESSFAAW = 144 +PPC_INS_EVMHESSFANW = 145 +PPC_INS_EVMHESSIAAW = 146 +PPC_INS_EVMHESSIANW = 147 +PPC_INS_EVMHEUMI = 148 +PPC_INS_EVMHEUMIA = 149 +PPC_INS_EVMHEUMIAAW = 150 +PPC_INS_EVMHEUMIANW = 151 +PPC_INS_EVMHEUSIAAW = 152 +PPC_INS_EVMHEUSIANW = 153 +PPC_INS_EVMHOGSMFAA = 154 +PPC_INS_EVMHOGSMFAN = 155 +PPC_INS_EVMHOGSMIAA = 156 +PPC_INS_EVMHOGSMIAN = 157 +PPC_INS_EVMHOGUMIAA = 158 +PPC_INS_EVMHOGUMIAN = 159 +PPC_INS_EVMHOSMF = 160 +PPC_INS_EVMHOSMFA = 161 +PPC_INS_EVMHOSMFAAW = 162 +PPC_INS_EVMHOSMFANW = 163 +PPC_INS_EVMHOSMI = 164 +PPC_INS_EVMHOSMIA = 165 +PPC_INS_EVMHOSMIAAW = 166 +PPC_INS_EVMHOSMIANW = 167 +PPC_INS_EVMHOSSF = 168 +PPC_INS_EVMHOSSFA = 169 +PPC_INS_EVMHOSSFAAW = 170 +PPC_INS_EVMHOSSFANW = 171 +PPC_INS_EVMHOSSIAAW = 172 +PPC_INS_EVMHOSSIANW = 173 +PPC_INS_EVMHOUMI = 174 +PPC_INS_EVMHOUMIA = 175 +PPC_INS_EVMHOUMIAAW = 176 +PPC_INS_EVMHOUMIANW = 177 +PPC_INS_EVMHOUSIAAW = 178 +PPC_INS_EVMHOUSIANW = 179 +PPC_INS_EVMRA = 180 +PPC_INS_EVMWHSMF = 181 +PPC_INS_EVMWHSMFA = 182 +PPC_INS_EVMWHSMI = 183 +PPC_INS_EVMWHSMIA = 184 +PPC_INS_EVMWHSSF = 185 +PPC_INS_EVMWHSSFA = 186 +PPC_INS_EVMWHUMI = 187 +PPC_INS_EVMWHUMIA = 188 +PPC_INS_EVMWLSMIAAW = 189 +PPC_INS_EVMWLSMIANW = 190 +PPC_INS_EVMWLSSIAAW = 191 +PPC_INS_EVMWLSSIANW = 192 +PPC_INS_EVMWLUMI = 193 +PPC_INS_EVMWLUMIA = 194 +PPC_INS_EVMWLUMIAAW = 195 +PPC_INS_EVMWLUMIANW = 196 +PPC_INS_EVMWLUSIAAW = 197 +PPC_INS_EVMWLUSIANW = 198 +PPC_INS_EVMWSMF = 199 +PPC_INS_EVMWSMFA = 200 +PPC_INS_EVMWSMFAA = 201 +PPC_INS_EVMWSMFAN = 202 +PPC_INS_EVMWSMI = 203 +PPC_INS_EVMWSMIA = 204 +PPC_INS_EVMWSMIAA = 205 +PPC_INS_EVMWSMIAN = 206 +PPC_INS_EVMWSSF = 207 +PPC_INS_EVMWSSFA = 208 +PPC_INS_EVMWSSFAA = 209 +PPC_INS_EVMWSSFAN = 210 +PPC_INS_EVMWUMI = 211 +PPC_INS_EVMWUMIA = 212 +PPC_INS_EVMWUMIAA = 213 +PPC_INS_EVMWUMIAN = 214 +PPC_INS_EVNAND = 215 +PPC_INS_EVNEG = 216 +PPC_INS_EVNOR = 217 +PPC_INS_EVOR = 218 +PPC_INS_EVORC = 219 +PPC_INS_EVRLW = 220 +PPC_INS_EVRLWI = 221 +PPC_INS_EVRNDW = 222 +PPC_INS_EVSLW = 223 +PPC_INS_EVSLWI = 224 +PPC_INS_EVSPLATFI = 225 +PPC_INS_EVSPLATI = 226 +PPC_INS_EVSRWIS = 227 +PPC_INS_EVSRWIU = 228 +PPC_INS_EVSRWS = 229 +PPC_INS_EVSRWU = 230 +PPC_INS_EVSTDD = 231 +PPC_INS_EVSTDDX = 232 +PPC_INS_EVSTDH = 233 +PPC_INS_EVSTDHX = 234 +PPC_INS_EVSTDW = 235 +PPC_INS_EVSTDWX = 236 +PPC_INS_EVSTWHE = 237 +PPC_INS_EVSTWHEX = 238 +PPC_INS_EVSTWHO = 239 +PPC_INS_EVSTWHOX = 240 +PPC_INS_EVSTWWE = 241 +PPC_INS_EVSTWWEX = 242 +PPC_INS_EVSTWWO = 243 +PPC_INS_EVSTWWOX = 244 +PPC_INS_EVSUBFSMIAAW = 245 +PPC_INS_EVSUBFSSIAAW = 246 +PPC_INS_EVSUBFUMIAAW = 247 +PPC_INS_EVSUBFUSIAAW = 248 +PPC_INS_EVSUBFW = 249 +PPC_INS_EVSUBIFW = 250 +PPC_INS_EVXOR = 251 +PPC_INS_EXTSB = 252 +PPC_INS_EXTSH = 253 +PPC_INS_EXTSW = 254 +PPC_INS_EIEIO = 255 +PPC_INS_FABS = 256 +PPC_INS_FADD = 257 +PPC_INS_FADDS = 258 +PPC_INS_FCFID = 259 +PPC_INS_FCFIDS = 260 +PPC_INS_FCFIDU = 261 +PPC_INS_FCFIDUS = 262 +PPC_INS_FCMPU = 263 +PPC_INS_FCPSGN = 264 +PPC_INS_FCTID = 265 +PPC_INS_FCTIDUZ = 266 +PPC_INS_FCTIDZ = 267 +PPC_INS_FCTIW = 268 +PPC_INS_FCTIWUZ = 269 +PPC_INS_FCTIWZ = 270 +PPC_INS_FDIV = 271 +PPC_INS_FDIVS = 272 +PPC_INS_FMADD = 273 +PPC_INS_FMADDS = 274 +PPC_INS_FMR = 275 +PPC_INS_FMSUB = 276 +PPC_INS_FMSUBS = 277 +PPC_INS_FMUL = 278 +PPC_INS_FMULS = 279 +PPC_INS_FNABS = 280 +PPC_INS_FNEG = 281 +PPC_INS_FNMADD = 282 +PPC_INS_FNMADDS = 283 +PPC_INS_FNMSUB = 284 +PPC_INS_FNMSUBS = 285 +PPC_INS_FRE = 286 +PPC_INS_FRES = 287 +PPC_INS_FRIM = 288 +PPC_INS_FRIN = 289 +PPC_INS_FRIP = 290 +PPC_INS_FRIZ = 291 +PPC_INS_FRSP = 292 +PPC_INS_FRSQRTE = 293 +PPC_INS_FRSQRTES = 294 +PPC_INS_FSEL = 295 +PPC_INS_FSQRT = 296 +PPC_INS_FSQRTS = 297 +PPC_INS_FSUB = 298 +PPC_INS_FSUBS = 299 +PPC_INS_ICBI = 300 +PPC_INS_ICBT = 301 +PPC_INS_ICCCI = 302 +PPC_INS_ISEL = 303 +PPC_INS_ISYNC = 304 +PPC_INS_LA = 305 +PPC_INS_LBZ = 306 +PPC_INS_LBZCIX = 307 +PPC_INS_LBZU = 308 +PPC_INS_LBZUX = 309 +PPC_INS_LBZX = 310 +PPC_INS_LD = 311 +PPC_INS_LDARX = 312 +PPC_INS_LDBRX = 313 +PPC_INS_LDCIX = 314 +PPC_INS_LDU = 315 +PPC_INS_LDUX = 316 +PPC_INS_LDX = 317 +PPC_INS_LFD = 318 +PPC_INS_LFDU = 319 +PPC_INS_LFDUX = 320 +PPC_INS_LFDX = 321 +PPC_INS_LFIWAX = 322 +PPC_INS_LFIWZX = 323 +PPC_INS_LFS = 324 +PPC_INS_LFSU = 325 +PPC_INS_LFSUX = 326 +PPC_INS_LFSX = 327 +PPC_INS_LHA = 328 +PPC_INS_LHAU = 329 +PPC_INS_LHAUX = 330 +PPC_INS_LHAX = 331 +PPC_INS_LHBRX = 332 +PPC_INS_LHZ = 333 +PPC_INS_LHZCIX = 334 +PPC_INS_LHZU = 335 +PPC_INS_LHZUX = 336 +PPC_INS_LHZX = 337 +PPC_INS_LI = 338 +PPC_INS_LIS = 339 +PPC_INS_LMW = 340 +PPC_INS_LSWI = 341 +PPC_INS_LVEBX = 342 +PPC_INS_LVEHX = 343 +PPC_INS_LVEWX = 344 +PPC_INS_LVSL = 345 +PPC_INS_LVSR = 346 +PPC_INS_LVX = 347 +PPC_INS_LVXL = 348 +PPC_INS_LWA = 349 +PPC_INS_LWARX = 350 +PPC_INS_LWAUX = 351 +PPC_INS_LWAX = 352 +PPC_INS_LWBRX = 353 +PPC_INS_LWZ = 354 +PPC_INS_LWZCIX = 355 +PPC_INS_LWZU = 356 +PPC_INS_LWZUX = 357 +PPC_INS_LWZX = 358 +PPC_INS_LXSDX = 359 +PPC_INS_LXVD2X = 360 +PPC_INS_LXVDSX = 361 +PPC_INS_LXVW4X = 362 +PPC_INS_MBAR = 363 +PPC_INS_MCRF = 364 +PPC_INS_MCRFS = 365 +PPC_INS_MFCR = 366 +PPC_INS_MFCTR = 367 +PPC_INS_MFDCR = 368 +PPC_INS_MFFS = 369 +PPC_INS_MFLR = 370 +PPC_INS_MFMSR = 371 +PPC_INS_MFOCRF = 372 +PPC_INS_MFSPR = 373 +PPC_INS_MFSR = 374 +PPC_INS_MFSRIN = 375 +PPC_INS_MFTB = 376 +PPC_INS_MFVSCR = 377 +PPC_INS_MSYNC = 378 +PPC_INS_MTCRF = 379 +PPC_INS_MTCTR = 380 +PPC_INS_MTDCR = 381 +PPC_INS_MTFSB0 = 382 +PPC_INS_MTFSB1 = 383 +PPC_INS_MTFSF = 384 +PPC_INS_MTFSFI = 385 +PPC_INS_MTLR = 386 +PPC_INS_MTMSR = 387 +PPC_INS_MTMSRD = 388 +PPC_INS_MTOCRF = 389 +PPC_INS_MTSPR = 390 +PPC_INS_MTSR = 391 +PPC_INS_MTSRIN = 392 +PPC_INS_MTVSCR = 393 +PPC_INS_MULHD = 394 +PPC_INS_MULHDU = 395 +PPC_INS_MULHW = 396 +PPC_INS_MULHWU = 397 +PPC_INS_MULLD = 398 +PPC_INS_MULLI = 399 +PPC_INS_MULLW = 400 +PPC_INS_NAND = 401 +PPC_INS_NEG = 402 +PPC_INS_NOP = 403 +PPC_INS_ORI = 404 +PPC_INS_NOR = 405 +PPC_INS_OR = 406 +PPC_INS_ORC = 407 +PPC_INS_ORIS = 408 +PPC_INS_POPCNTD = 409 +PPC_INS_POPCNTW = 410 +PPC_INS_QVALIGNI = 411 +PPC_INS_QVESPLATI = 412 +PPC_INS_QVFABS = 413 +PPC_INS_QVFADD = 414 +PPC_INS_QVFADDS = 415 +PPC_INS_QVFCFID = 416 +PPC_INS_QVFCFIDS = 417 +PPC_INS_QVFCFIDU = 418 +PPC_INS_QVFCFIDUS = 419 +PPC_INS_QVFCMPEQ = 420 +PPC_INS_QVFCMPGT = 421 +PPC_INS_QVFCMPLT = 422 +PPC_INS_QVFCPSGN = 423 +PPC_INS_QVFCTID = 424 +PPC_INS_QVFCTIDU = 425 +PPC_INS_QVFCTIDUZ = 426 +PPC_INS_QVFCTIDZ = 427 +PPC_INS_QVFCTIW = 428 +PPC_INS_QVFCTIWU = 429 +PPC_INS_QVFCTIWUZ = 430 +PPC_INS_QVFCTIWZ = 431 +PPC_INS_QVFLOGICAL = 432 +PPC_INS_QVFMADD = 433 +PPC_INS_QVFMADDS = 434 +PPC_INS_QVFMR = 435 +PPC_INS_QVFMSUB = 436 +PPC_INS_QVFMSUBS = 437 +PPC_INS_QVFMUL = 438 +PPC_INS_QVFMULS = 439 +PPC_INS_QVFNABS = 440 +PPC_INS_QVFNEG = 441 +PPC_INS_QVFNMADD = 442 +PPC_INS_QVFNMADDS = 443 +PPC_INS_QVFNMSUB = 444 +PPC_INS_QVFNMSUBS = 445 +PPC_INS_QVFPERM = 446 +PPC_INS_QVFRE = 447 +PPC_INS_QVFRES = 448 +PPC_INS_QVFRIM = 449 +PPC_INS_QVFRIN = 450 +PPC_INS_QVFRIP = 451 +PPC_INS_QVFRIZ = 452 +PPC_INS_QVFRSP = 453 +PPC_INS_QVFRSQRTE = 454 +PPC_INS_QVFRSQRTES = 455 +PPC_INS_QVFSEL = 456 +PPC_INS_QVFSUB = 457 +PPC_INS_QVFSUBS = 458 +PPC_INS_QVFTSTNAN = 459 +PPC_INS_QVFXMADD = 460 +PPC_INS_QVFXMADDS = 461 +PPC_INS_QVFXMUL = 462 +PPC_INS_QVFXMULS = 463 +PPC_INS_QVFXXCPNMADD = 464 +PPC_INS_QVFXXCPNMADDS = 465 +PPC_INS_QVFXXMADD = 466 +PPC_INS_QVFXXMADDS = 467 +PPC_INS_QVFXXNPMADD = 468 +PPC_INS_QVFXXNPMADDS = 469 +PPC_INS_QVGPCI = 470 +PPC_INS_QVLFCDUX = 471 +PPC_INS_QVLFCDUXA = 472 +PPC_INS_QVLFCDX = 473 +PPC_INS_QVLFCDXA = 474 +PPC_INS_QVLFCSUX = 475 +PPC_INS_QVLFCSUXA = 476 +PPC_INS_QVLFCSX = 477 +PPC_INS_QVLFCSXA = 478 +PPC_INS_QVLFDUX = 479 +PPC_INS_QVLFDUXA = 480 +PPC_INS_QVLFDX = 481 +PPC_INS_QVLFDXA = 482 +PPC_INS_QVLFIWAX = 483 +PPC_INS_QVLFIWAXA = 484 +PPC_INS_QVLFIWZX = 485 +PPC_INS_QVLFIWZXA = 486 +PPC_INS_QVLFSUX = 487 +PPC_INS_QVLFSUXA = 488 +PPC_INS_QVLFSX = 489 +PPC_INS_QVLFSXA = 490 +PPC_INS_QVLPCLDX = 491 +PPC_INS_QVLPCLSX = 492 +PPC_INS_QVLPCRDX = 493 +PPC_INS_QVLPCRSX = 494 +PPC_INS_QVSTFCDUX = 495 +PPC_INS_QVSTFCDUXA = 496 +PPC_INS_QVSTFCDUXI = 497 +PPC_INS_QVSTFCDUXIA = 498 +PPC_INS_QVSTFCDX = 499 +PPC_INS_QVSTFCDXA = 500 +PPC_INS_QVSTFCDXI = 501 +PPC_INS_QVSTFCDXIA = 502 +PPC_INS_QVSTFCSUX = 503 +PPC_INS_QVSTFCSUXA = 504 +PPC_INS_QVSTFCSUXI = 505 +PPC_INS_QVSTFCSUXIA = 506 +PPC_INS_QVSTFCSX = 507 +PPC_INS_QVSTFCSXA = 508 +PPC_INS_QVSTFCSXI = 509 +PPC_INS_QVSTFCSXIA = 510 +PPC_INS_QVSTFDUX = 511 +PPC_INS_QVSTFDUXA = 512 +PPC_INS_QVSTFDUXI = 513 +PPC_INS_QVSTFDUXIA = 514 +PPC_INS_QVSTFDX = 515 +PPC_INS_QVSTFDXA = 516 +PPC_INS_QVSTFDXI = 517 +PPC_INS_QVSTFDXIA = 518 +PPC_INS_QVSTFIWX = 519 +PPC_INS_QVSTFIWXA = 520 +PPC_INS_QVSTFSUX = 521 +PPC_INS_QVSTFSUXA = 522 +PPC_INS_QVSTFSUXI = 523 +PPC_INS_QVSTFSUXIA = 524 +PPC_INS_QVSTFSX = 525 +PPC_INS_QVSTFSXA = 526 +PPC_INS_QVSTFSXI = 527 +PPC_INS_QVSTFSXIA = 528 +PPC_INS_RFCI = 529 +PPC_INS_RFDI = 530 +PPC_INS_RFI = 531 +PPC_INS_RFID = 532 +PPC_INS_RFMCI = 533 +PPC_INS_RLDCL = 534 +PPC_INS_RLDCR = 535 +PPC_INS_RLDIC = 536 +PPC_INS_RLDICL = 537 +PPC_INS_RLDICR = 538 +PPC_INS_RLDIMI = 539 +PPC_INS_RLWIMI = 540 +PPC_INS_RLWINM = 541 +PPC_INS_RLWNM = 542 +PPC_INS_SC = 543 +PPC_INS_SLBIA = 544 +PPC_INS_SLBIE = 545 +PPC_INS_SLBMFEE = 546 +PPC_INS_SLBMTE = 547 +PPC_INS_SLD = 548 +PPC_INS_SLW = 549 +PPC_INS_SRAD = 550 +PPC_INS_SRADI = 551 +PPC_INS_SRAW = 552 +PPC_INS_SRAWI = 553 +PPC_INS_SRD = 554 +PPC_INS_SRW = 555 +PPC_INS_STB = 556 +PPC_INS_STBCIX = 557 +PPC_INS_STBU = 558 +PPC_INS_STBUX = 559 +PPC_INS_STBX = 560 +PPC_INS_STD = 561 +PPC_INS_STDBRX = 562 +PPC_INS_STDCIX = 563 +PPC_INS_STDCX = 564 +PPC_INS_STDU = 565 +PPC_INS_STDUX = 566 +PPC_INS_STDX = 567 +PPC_INS_STFD = 568 +PPC_INS_STFDU = 569 +PPC_INS_STFDUX = 570 +PPC_INS_STFDX = 571 +PPC_INS_STFIWX = 572 +PPC_INS_STFS = 573 +PPC_INS_STFSU = 574 +PPC_INS_STFSUX = 575 +PPC_INS_STFSX = 576 +PPC_INS_STH = 577 +PPC_INS_STHBRX = 578 +PPC_INS_STHCIX = 579 +PPC_INS_STHU = 580 +PPC_INS_STHUX = 581 +PPC_INS_STHX = 582 +PPC_INS_STMW = 583 +PPC_INS_STSWI = 584 +PPC_INS_STVEBX = 585 +PPC_INS_STVEHX = 586 +PPC_INS_STVEWX = 587 +PPC_INS_STVX = 588 +PPC_INS_STVXL = 589 +PPC_INS_STW = 590 +PPC_INS_STWBRX = 591 +PPC_INS_STWCIX = 592 +PPC_INS_STWCX = 593 +PPC_INS_STWU = 594 +PPC_INS_STWUX = 595 +PPC_INS_STWX = 596 +PPC_INS_STXSDX = 597 +PPC_INS_STXVD2X = 598 +PPC_INS_STXVW4X = 599 +PPC_INS_SUBF = 600 +PPC_INS_SUBFC = 601 +PPC_INS_SUBFE = 602 +PPC_INS_SUBFIC = 603 +PPC_INS_SUBFME = 604 +PPC_INS_SUBFZE = 605 +PPC_INS_SYNC = 606 +PPC_INS_TD = 607 +PPC_INS_TDI = 608 +PPC_INS_TLBIA = 609 +PPC_INS_TLBIE = 610 +PPC_INS_TLBIEL = 611 +PPC_INS_TLBIVAX = 612 +PPC_INS_TLBLD = 613 +PPC_INS_TLBLI = 614 +PPC_INS_TLBRE = 615 +PPC_INS_TLBSX = 616 +PPC_INS_TLBSYNC = 617 +PPC_INS_TLBWE = 618 +PPC_INS_TRAP = 619 +PPC_INS_TW = 620 +PPC_INS_TWI = 621 +PPC_INS_VADDCUW = 622 +PPC_INS_VADDFP = 623 +PPC_INS_VADDSBS = 624 +PPC_INS_VADDSHS = 625 +PPC_INS_VADDSWS = 626 +PPC_INS_VADDUBM = 627 +PPC_INS_VADDUBS = 628 +PPC_INS_VADDUDM = 629 +PPC_INS_VADDUHM = 630 +PPC_INS_VADDUHS = 631 +PPC_INS_VADDUWM = 632 +PPC_INS_VADDUWS = 633 +PPC_INS_VAND = 634 +PPC_INS_VANDC = 635 +PPC_INS_VAVGSB = 636 +PPC_INS_VAVGSH = 637 +PPC_INS_VAVGSW = 638 +PPC_INS_VAVGUB = 639 +PPC_INS_VAVGUH = 640 +PPC_INS_VAVGUW = 641 +PPC_INS_VCFSX = 642 +PPC_INS_VCFUX = 643 +PPC_INS_VCLZB = 644 +PPC_INS_VCLZD = 645 +PPC_INS_VCLZH = 646 +PPC_INS_VCLZW = 647 +PPC_INS_VCMPBFP = 648 +PPC_INS_VCMPEQFP = 649 +PPC_INS_VCMPEQUB = 650 +PPC_INS_VCMPEQUD = 651 +PPC_INS_VCMPEQUH = 652 +PPC_INS_VCMPEQUW = 653 +PPC_INS_VCMPGEFP = 654 +PPC_INS_VCMPGTFP = 655 +PPC_INS_VCMPGTSB = 656 +PPC_INS_VCMPGTSD = 657 +PPC_INS_VCMPGTSH = 658 +PPC_INS_VCMPGTSW = 659 +PPC_INS_VCMPGTUB = 660 +PPC_INS_VCMPGTUD = 661 +PPC_INS_VCMPGTUH = 662 +PPC_INS_VCMPGTUW = 663 +PPC_INS_VCTSXS = 664 +PPC_INS_VCTUXS = 665 +PPC_INS_VEQV = 666 +PPC_INS_VEXPTEFP = 667 +PPC_INS_VLOGEFP = 668 +PPC_INS_VMADDFP = 669 +PPC_INS_VMAXFP = 670 +PPC_INS_VMAXSB = 671 +PPC_INS_VMAXSD = 672 +PPC_INS_VMAXSH = 673 +PPC_INS_VMAXSW = 674 +PPC_INS_VMAXUB = 675 +PPC_INS_VMAXUD = 676 +PPC_INS_VMAXUH = 677 +PPC_INS_VMAXUW = 678 +PPC_INS_VMHADDSHS = 679 +PPC_INS_VMHRADDSHS = 680 +PPC_INS_VMINUD = 681 +PPC_INS_VMINFP = 682 +PPC_INS_VMINSB = 683 +PPC_INS_VMINSD = 684 +PPC_INS_VMINSH = 685 +PPC_INS_VMINSW = 686 +PPC_INS_VMINUB = 687 +PPC_INS_VMINUH = 688 +PPC_INS_VMINUW = 689 +PPC_INS_VMLADDUHM = 690 +PPC_INS_VMRGHB = 691 +PPC_INS_VMRGHH = 692 +PPC_INS_VMRGHW = 693 +PPC_INS_VMRGLB = 694 +PPC_INS_VMRGLH = 695 +PPC_INS_VMRGLW = 696 +PPC_INS_VMSUMMBM = 697 +PPC_INS_VMSUMSHM = 698 +PPC_INS_VMSUMSHS = 699 +PPC_INS_VMSUMUBM = 700 +PPC_INS_VMSUMUHM = 701 +PPC_INS_VMSUMUHS = 702 +PPC_INS_VMULESB = 703 +PPC_INS_VMULESH = 704 +PPC_INS_VMULESW = 705 +PPC_INS_VMULEUB = 706 +PPC_INS_VMULEUH = 707 +PPC_INS_VMULEUW = 708 +PPC_INS_VMULOSB = 709 +PPC_INS_VMULOSH = 710 +PPC_INS_VMULOSW = 711 +PPC_INS_VMULOUB = 712 +PPC_INS_VMULOUH = 713 +PPC_INS_VMULOUW = 714 +PPC_INS_VMULUWM = 715 +PPC_INS_VNAND = 716 +PPC_INS_VNMSUBFP = 717 +PPC_INS_VNOR = 718 +PPC_INS_VOR = 719 +PPC_INS_VORC = 720 +PPC_INS_VPERM = 721 +PPC_INS_VPKPX = 722 +PPC_INS_VPKSHSS = 723 +PPC_INS_VPKSHUS = 724 +PPC_INS_VPKSWSS = 725 +PPC_INS_VPKSWUS = 726 +PPC_INS_VPKUHUM = 727 +PPC_INS_VPKUHUS = 728 +PPC_INS_VPKUWUM = 729 +PPC_INS_VPKUWUS = 730 +PPC_INS_VPOPCNTB = 731 +PPC_INS_VPOPCNTD = 732 +PPC_INS_VPOPCNTH = 733 +PPC_INS_VPOPCNTW = 734 +PPC_INS_VREFP = 735 +PPC_INS_VRFIM = 736 +PPC_INS_VRFIN = 737 +PPC_INS_VRFIP = 738 +PPC_INS_VRFIZ = 739 +PPC_INS_VRLB = 740 +PPC_INS_VRLD = 741 +PPC_INS_VRLH = 742 +PPC_INS_VRLW = 743 +PPC_INS_VRSQRTEFP = 744 +PPC_INS_VSEL = 745 +PPC_INS_VSL = 746 +PPC_INS_VSLB = 747 +PPC_INS_VSLD = 748 +PPC_INS_VSLDOI = 749 +PPC_INS_VSLH = 750 +PPC_INS_VSLO = 751 +PPC_INS_VSLW = 752 +PPC_INS_VSPLTB = 753 +PPC_INS_VSPLTH = 754 +PPC_INS_VSPLTISB = 755 +PPC_INS_VSPLTISH = 756 +PPC_INS_VSPLTISW = 757 +PPC_INS_VSPLTW = 758 +PPC_INS_VSR = 759 +PPC_INS_VSRAB = 760 +PPC_INS_VSRAD = 761 +PPC_INS_VSRAH = 762 +PPC_INS_VSRAW = 763 +PPC_INS_VSRB = 764 +PPC_INS_VSRD = 765 +PPC_INS_VSRH = 766 +PPC_INS_VSRO = 767 +PPC_INS_VSRW = 768 +PPC_INS_VSUBCUW = 769 +PPC_INS_VSUBFP = 770 +PPC_INS_VSUBSBS = 771 +PPC_INS_VSUBSHS = 772 +PPC_INS_VSUBSWS = 773 +PPC_INS_VSUBUBM = 774 +PPC_INS_VSUBUBS = 775 +PPC_INS_VSUBUDM = 776 +PPC_INS_VSUBUHM = 777 +PPC_INS_VSUBUHS = 778 +PPC_INS_VSUBUWM = 779 +PPC_INS_VSUBUWS = 780 +PPC_INS_VSUM2SWS = 781 +PPC_INS_VSUM4SBS = 782 +PPC_INS_VSUM4SHS = 783 +PPC_INS_VSUM4UBS = 784 +PPC_INS_VSUMSWS = 785 +PPC_INS_VUPKHPX = 786 +PPC_INS_VUPKHSB = 787 +PPC_INS_VUPKHSH = 788 +PPC_INS_VUPKLPX = 789 +PPC_INS_VUPKLSB = 790 +PPC_INS_VUPKLSH = 791 +PPC_INS_VXOR = 792 +PPC_INS_WAIT = 793 +PPC_INS_WRTEE = 794 +PPC_INS_WRTEEI = 795 +PPC_INS_XOR = 796 +PPC_INS_XORI = 797 +PPC_INS_XORIS = 798 +PPC_INS_XSABSDP = 799 +PPC_INS_XSADDDP = 800 +PPC_INS_XSCMPODP = 801 +PPC_INS_XSCMPUDP = 802 +PPC_INS_XSCPSGNDP = 803 +PPC_INS_XSCVDPSP = 804 +PPC_INS_XSCVDPSXDS = 805 +PPC_INS_XSCVDPSXWS = 806 +PPC_INS_XSCVDPUXDS = 807 +PPC_INS_XSCVDPUXWS = 808 +PPC_INS_XSCVSPDP = 809 +PPC_INS_XSCVSXDDP = 810 +PPC_INS_XSCVUXDDP = 811 +PPC_INS_XSDIVDP = 812 +PPC_INS_XSMADDADP = 813 +PPC_INS_XSMADDMDP = 814 +PPC_INS_XSMAXDP = 815 +PPC_INS_XSMINDP = 816 +PPC_INS_XSMSUBADP = 817 +PPC_INS_XSMSUBMDP = 818 +PPC_INS_XSMULDP = 819 +PPC_INS_XSNABSDP = 820 +PPC_INS_XSNEGDP = 821 +PPC_INS_XSNMADDADP = 822 +PPC_INS_XSNMADDMDP = 823 +PPC_INS_XSNMSUBADP = 824 +PPC_INS_XSNMSUBMDP = 825 +PPC_INS_XSRDPI = 826 +PPC_INS_XSRDPIC = 827 +PPC_INS_XSRDPIM = 828 +PPC_INS_XSRDPIP = 829 +PPC_INS_XSRDPIZ = 830 +PPC_INS_XSREDP = 831 +PPC_INS_XSRSQRTEDP = 832 +PPC_INS_XSSQRTDP = 833 +PPC_INS_XSSUBDP = 834 +PPC_INS_XSTDIVDP = 835 +PPC_INS_XSTSQRTDP = 836 +PPC_INS_XVABSDP = 837 +PPC_INS_XVABSSP = 838 +PPC_INS_XVADDDP = 839 +PPC_INS_XVADDSP = 840 +PPC_INS_XVCMPEQDP = 841 +PPC_INS_XVCMPEQSP = 842 +PPC_INS_XVCMPGEDP = 843 +PPC_INS_XVCMPGESP = 844 +PPC_INS_XVCMPGTDP = 845 +PPC_INS_XVCMPGTSP = 846 +PPC_INS_XVCPSGNDP = 847 +PPC_INS_XVCPSGNSP = 848 +PPC_INS_XVCVDPSP = 849 +PPC_INS_XVCVDPSXDS = 850 +PPC_INS_XVCVDPSXWS = 851 +PPC_INS_XVCVDPUXDS = 852 +PPC_INS_XVCVDPUXWS = 853 +PPC_INS_XVCVSPDP = 854 +PPC_INS_XVCVSPSXDS = 855 +PPC_INS_XVCVSPSXWS = 856 +PPC_INS_XVCVSPUXDS = 857 +PPC_INS_XVCVSPUXWS = 858 +PPC_INS_XVCVSXDDP = 859 +PPC_INS_XVCVSXDSP = 860 +PPC_INS_XVCVSXWDP = 861 +PPC_INS_XVCVSXWSP = 862 +PPC_INS_XVCVUXDDP = 863 +PPC_INS_XVCVUXDSP = 864 +PPC_INS_XVCVUXWDP = 865 +PPC_INS_XVCVUXWSP = 866 +PPC_INS_XVDIVDP = 867 +PPC_INS_XVDIVSP = 868 +PPC_INS_XVMADDADP = 869 +PPC_INS_XVMADDASP = 870 +PPC_INS_XVMADDMDP = 871 +PPC_INS_XVMADDMSP = 872 +PPC_INS_XVMAXDP = 873 +PPC_INS_XVMAXSP = 874 +PPC_INS_XVMINDP = 875 +PPC_INS_XVMINSP = 876 +PPC_INS_XVMSUBADP = 877 +PPC_INS_XVMSUBASP = 878 +PPC_INS_XVMSUBMDP = 879 +PPC_INS_XVMSUBMSP = 880 +PPC_INS_XVMULDP = 881 +PPC_INS_XVMULSP = 882 +PPC_INS_XVNABSDP = 883 +PPC_INS_XVNABSSP = 884 +PPC_INS_XVNEGDP = 885 +PPC_INS_XVNEGSP = 886 +PPC_INS_XVNMADDADP = 887 +PPC_INS_XVNMADDASP = 888 +PPC_INS_XVNMADDMDP = 889 +PPC_INS_XVNMADDMSP = 890 +PPC_INS_XVNMSUBADP = 891 +PPC_INS_XVNMSUBASP = 892 +PPC_INS_XVNMSUBMDP = 893 +PPC_INS_XVNMSUBMSP = 894 +PPC_INS_XVRDPI = 895 +PPC_INS_XVRDPIC = 896 +PPC_INS_XVRDPIM = 897 +PPC_INS_XVRDPIP = 898 +PPC_INS_XVRDPIZ = 899 +PPC_INS_XVREDP = 900 +PPC_INS_XVRESP = 901 +PPC_INS_XVRSPI = 902 +PPC_INS_XVRSPIC = 903 +PPC_INS_XVRSPIM = 904 +PPC_INS_XVRSPIP = 905 +PPC_INS_XVRSPIZ = 906 +PPC_INS_XVRSQRTEDP = 907 +PPC_INS_XVRSQRTESP = 908 +PPC_INS_XVSQRTDP = 909 +PPC_INS_XVSQRTSP = 910 +PPC_INS_XVSUBDP = 911 +PPC_INS_XVSUBSP = 912 +PPC_INS_XVTDIVDP = 913 +PPC_INS_XVTDIVSP = 914 +PPC_INS_XVTSQRTDP = 915 +PPC_INS_XVTSQRTSP = 916 +PPC_INS_XXLAND = 917 +PPC_INS_XXLANDC = 918 +PPC_INS_XXLEQV = 919 +PPC_INS_XXLNAND = 920 +PPC_INS_XXLNOR = 921 +PPC_INS_XXLOR = 922 +PPC_INS_XXLORC = 923 +PPC_INS_XXLXOR = 924 +PPC_INS_XXMRGHW = 925 +PPC_INS_XXMRGLW = 926 +PPC_INS_XXPERMDI = 927 +PPC_INS_XXSEL = 928 +PPC_INS_XXSLDWI = 929 +PPC_INS_XXSPLTW = 930 +PPC_INS_BCA = 931 +PPC_INS_BCLA = 932 +PPC_INS_SLWI = 933 +PPC_INS_SRWI = 934 +PPC_INS_SLDI = 935 +PPC_INS_BTA = 936 +PPC_INS_CRSET = 937 +PPC_INS_CRNOT = 938 +PPC_INS_CRMOVE = 939 +PPC_INS_CRCLR = 940 +PPC_INS_MFBR0 = 941 +PPC_INS_MFBR1 = 942 +PPC_INS_MFBR2 = 943 +PPC_INS_MFBR3 = 944 +PPC_INS_MFBR4 = 945 +PPC_INS_MFBR5 = 946 +PPC_INS_MFBR6 = 947 +PPC_INS_MFBR7 = 948 +PPC_INS_MFXER = 949 +PPC_INS_MFRTCU = 950 +PPC_INS_MFRTCL = 951 +PPC_INS_MFDSCR = 952 +PPC_INS_MFDSISR = 953 +PPC_INS_MFDAR = 954 +PPC_INS_MFSRR2 = 955 +PPC_INS_MFSRR3 = 956 +PPC_INS_MFCFAR = 957 +PPC_INS_MFAMR = 958 +PPC_INS_MFPID = 959 +PPC_INS_MFTBLO = 960 +PPC_INS_MFTBHI = 961 +PPC_INS_MFDBATU = 962 +PPC_INS_MFDBATL = 963 +PPC_INS_MFIBATU = 964 +PPC_INS_MFIBATL = 965 +PPC_INS_MFDCCR = 966 +PPC_INS_MFICCR = 967 +PPC_INS_MFDEAR = 968 +PPC_INS_MFESR = 969 +PPC_INS_MFSPEFSCR = 970 +PPC_INS_MFTCR = 971 +PPC_INS_MFASR = 972 +PPC_INS_MFPVR = 973 +PPC_INS_MFTBU = 974 +PPC_INS_MTCR = 975 +PPC_INS_MTBR0 = 976 +PPC_INS_MTBR1 = 977 +PPC_INS_MTBR2 = 978 +PPC_INS_MTBR3 = 979 +PPC_INS_MTBR4 = 980 +PPC_INS_MTBR5 = 981 +PPC_INS_MTBR6 = 982 +PPC_INS_MTBR7 = 983 +PPC_INS_MTXER = 984 +PPC_INS_MTDSCR = 985 +PPC_INS_MTDSISR = 986 +PPC_INS_MTDAR = 987 +PPC_INS_MTSRR2 = 988 +PPC_INS_MTSRR3 = 989 +PPC_INS_MTCFAR = 990 +PPC_INS_MTAMR = 991 +PPC_INS_MTPID = 992 +PPC_INS_MTTBL = 993 +PPC_INS_MTTBU = 994 +PPC_INS_MTTBLO = 995 +PPC_INS_MTTBHI = 996 +PPC_INS_MTDBATU = 997 +PPC_INS_MTDBATL = 998 +PPC_INS_MTIBATU = 999 +PPC_INS_MTIBATL = 1000 +PPC_INS_MTDCCR = 1001 +PPC_INS_MTICCR = 1002 +PPC_INS_MTDEAR = 1003 +PPC_INS_MTESR = 1004 +PPC_INS_MTSPEFSCR = 1005 +PPC_INS_MTTCR = 1006 +PPC_INS_NOT = 1007 +PPC_INS_MR = 1008 +PPC_INS_ROTLD = 1009 +PPC_INS_ROTLDI = 1010 +PPC_INS_CLRLDI = 1011 +PPC_INS_ROTLWI = 1012 +PPC_INS_CLRLWI = 1013 +PPC_INS_ROTLW = 1014 +PPC_INS_SUB = 1015 +PPC_INS_SUBC = 1016 +PPC_INS_LWSYNC = 1017 +PPC_INS_PTESYNC = 1018 +PPC_INS_TDLT = 1019 +PPC_INS_TDEQ = 1020 +PPC_INS_TDGT = 1021 +PPC_INS_TDNE = 1022 +PPC_INS_TDLLT = 1023 +PPC_INS_TDLGT = 1024 +PPC_INS_TDU = 1025 +PPC_INS_TDLTI = 1026 +PPC_INS_TDEQI = 1027 +PPC_INS_TDGTI = 1028 +PPC_INS_TDNEI = 1029 +PPC_INS_TDLLTI = 1030 +PPC_INS_TDLGTI = 1031 +PPC_INS_TDUI = 1032 +PPC_INS_TLBREHI = 1033 +PPC_INS_TLBRELO = 1034 +PPC_INS_TLBWEHI = 1035 +PPC_INS_TLBWELO = 1036 +PPC_INS_TWLT = 1037 +PPC_INS_TWEQ = 1038 +PPC_INS_TWGT = 1039 +PPC_INS_TWNE = 1040 +PPC_INS_TWLLT = 1041 +PPC_INS_TWLGT = 1042 +PPC_INS_TWU = 1043 +PPC_INS_TWLTI = 1044 +PPC_INS_TWEQI = 1045 +PPC_INS_TWGTI = 1046 +PPC_INS_TWNEI = 1047 +PPC_INS_TWLLTI = 1048 +PPC_INS_TWLGTI = 1049 +PPC_INS_TWUI = 1050 +PPC_INS_WAITRSV = 1051 +PPC_INS_WAITIMPL = 1052 +PPC_INS_XNOP = 1053 +PPC_INS_XVMOVDP = 1054 +PPC_INS_XVMOVSP = 1055 +PPC_INS_XXSPLTD = 1056 +PPC_INS_XXMRGHD = 1057 +PPC_INS_XXMRGLD = 1058 +PPC_INS_XXSWAPD = 1059 +PPC_INS_BT = 1060 +PPC_INS_BF = 1061 +PPC_INS_BDNZT = 1062 +PPC_INS_BDNZF = 1063 +PPC_INS_BDZF = 1064 +PPC_INS_BDZT = 1065 +PPC_INS_BFA = 1066 +PPC_INS_BDNZTA = 1067 +PPC_INS_BDNZFA = 1068 +PPC_INS_BDZTA = 1069 +PPC_INS_BDZFA = 1070 +PPC_INS_BTCTR = 1071 +PPC_INS_BFCTR = 1072 +PPC_INS_BTCTRL = 1073 +PPC_INS_BFCTRL = 1074 +PPC_INS_BTL = 1075 +PPC_INS_BFL = 1076 +PPC_INS_BDNZTL = 1077 +PPC_INS_BDNZFL = 1078 +PPC_INS_BDZTL = 1079 +PPC_INS_BDZFL = 1080 +PPC_INS_BTLA = 1081 +PPC_INS_BFLA = 1082 +PPC_INS_BDNZTLA = 1083 +PPC_INS_BDNZFLA = 1084 +PPC_INS_BDZTLA = 1085 +PPC_INS_BDZFLA = 1086 +PPC_INS_BTLR = 1087 +PPC_INS_BFLR = 1088 +PPC_INS_BDNZTLR = 1089 +PPC_INS_BDZTLR = 1090 +PPC_INS_BDZFLR = 1091 +PPC_INS_BTLRL = 1092 +PPC_INS_BFLRL = 1093 +PPC_INS_BDNZTLRL = 1094 +PPC_INS_BDNZFLRL = 1095 +PPC_INS_BDZTLRL = 1096 +PPC_INS_BDZFLRL = 1097 +PPC_INS_QVFAND = 1098 +PPC_INS_QVFCLR = 1099 +PPC_INS_QVFANDC = 1100 +PPC_INS_QVFCTFB = 1101 +PPC_INS_QVFXOR = 1102 +PPC_INS_QVFOR = 1103 +PPC_INS_QVFNOR = 1104 +PPC_INS_QVFEQU = 1105 +PPC_INS_QVFNOT = 1106 +PPC_INS_QVFORC = 1107 +PPC_INS_QVFNAND = 1108 +PPC_INS_QVFSET = 1109 +PPC_INS_ENDING = 1110 + +PPC_GRP_INVALID = 0 +PPC_GRP_JUMP = 1 +PPC_GRP_ALTIVEC = 128 +PPC_GRP_MODE32 = 129 +PPC_GRP_MODE64 = 130 +PPC_GRP_BOOKE = 131 +PPC_GRP_NOTBOOKE = 132 +PPC_GRP_SPE = 133 +PPC_GRP_VSX = 134 +PPC_GRP_E500 = 135 +PPC_GRP_PPC4XX = 136 +PPC_GRP_PPC6XX = 137 +PPC_GRP_ICBT = 138 +PPC_GRP_P8ALTIVEC = 139 +PPC_GRP_P8VECTOR = 140 +PPC_GRP_QPX = 141 +PPC_GRP_ENDING = 142 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/sparc.py b/white_patch_detect/capstone-master/bindings/python/capstone/sparc.py new file mode 100644 index 0000000..1c536ff --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/sparc.py @@ -0,0 +1,51 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .sparc_const import * + +# define the API +class SparcOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint8), + ('index', ctypes.c_uint8), + ('disp', ctypes.c_int32), + ) + +class SparcOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', SparcOpMem), + ) + +class SparcOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', SparcOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsSparc(ctypes.Structure): + _fields_ = ( + ('cc', ctypes.c_uint), + ('hint', ctypes.c_uint), + ('op_count', ctypes.c_uint8), + ('operands', SparcOp * 4), + ) + +def get_arch_info(a): + return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/sparc_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/sparc_const.py new file mode 100644 index 0000000..6187691 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/sparc_const.py @@ -0,0 +1,429 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py] + +SPARC_CC_INVALID = 0 +SPARC_CC_ICC_A = 8+256 +SPARC_CC_ICC_N = 0+256 +SPARC_CC_ICC_NE = 9+256 +SPARC_CC_ICC_E = 1+256 +SPARC_CC_ICC_G = 10+256 +SPARC_CC_ICC_LE = 2+256 +SPARC_CC_ICC_GE = 11+256 +SPARC_CC_ICC_L = 3+256 +SPARC_CC_ICC_GU = 12+256 +SPARC_CC_ICC_LEU = 4+256 +SPARC_CC_ICC_CC = 13+256 +SPARC_CC_ICC_CS = 5+256 +SPARC_CC_ICC_POS = 14+256 +SPARC_CC_ICC_NEG = 6+256 +SPARC_CC_ICC_VC = 15+256 +SPARC_CC_ICC_VS = 7+256 +SPARC_CC_FCC_A = 8+16+256 +SPARC_CC_FCC_N = 0+16+256 +SPARC_CC_FCC_U = 7+16+256 +SPARC_CC_FCC_G = 6+16+256 +SPARC_CC_FCC_UG = 5+16+256 +SPARC_CC_FCC_L = 4+16+256 +SPARC_CC_FCC_UL = 3+16+256 +SPARC_CC_FCC_LG = 2+16+256 +SPARC_CC_FCC_NE = 1+16+256 +SPARC_CC_FCC_E = 9+16+256 +SPARC_CC_FCC_UE = 10+16+256 +SPARC_CC_FCC_GE = 11+16+256 +SPARC_CC_FCC_UGE = 12+16+256 +SPARC_CC_FCC_LE = 13+16+256 +SPARC_CC_FCC_ULE = 14+16+256 +SPARC_CC_FCC_O = 15+16+256 + +SPARC_HINT_INVALID = 0 +SPARC_HINT_A = 1<<0 +SPARC_HINT_PT = 1<<1 +SPARC_HINT_PN = 1<<2 + +SPARC_OP_INVALID = 0 +SPARC_OP_REG = 1 +SPARC_OP_IMM = 2 +SPARC_OP_MEM = 3 + +SPARC_REG_INVALID = 0 +SPARC_REG_F0 = 1 +SPARC_REG_F1 = 2 +SPARC_REG_F2 = 3 +SPARC_REG_F3 = 4 +SPARC_REG_F4 = 5 +SPARC_REG_F5 = 6 +SPARC_REG_F6 = 7 +SPARC_REG_F7 = 8 +SPARC_REG_F8 = 9 +SPARC_REG_F9 = 10 +SPARC_REG_F10 = 11 +SPARC_REG_F11 = 12 +SPARC_REG_F12 = 13 +SPARC_REG_F13 = 14 +SPARC_REG_F14 = 15 +SPARC_REG_F15 = 16 +SPARC_REG_F16 = 17 +SPARC_REG_F17 = 18 +SPARC_REG_F18 = 19 +SPARC_REG_F19 = 20 +SPARC_REG_F20 = 21 +SPARC_REG_F21 = 22 +SPARC_REG_F22 = 23 +SPARC_REG_F23 = 24 +SPARC_REG_F24 = 25 +SPARC_REG_F25 = 26 +SPARC_REG_F26 = 27 +SPARC_REG_F27 = 28 +SPARC_REG_F28 = 29 +SPARC_REG_F29 = 30 +SPARC_REG_F30 = 31 +SPARC_REG_F31 = 32 +SPARC_REG_F32 = 33 +SPARC_REG_F34 = 34 +SPARC_REG_F36 = 35 +SPARC_REG_F38 = 36 +SPARC_REG_F40 = 37 +SPARC_REG_F42 = 38 +SPARC_REG_F44 = 39 +SPARC_REG_F46 = 40 +SPARC_REG_F48 = 41 +SPARC_REG_F50 = 42 +SPARC_REG_F52 = 43 +SPARC_REG_F54 = 44 +SPARC_REG_F56 = 45 +SPARC_REG_F58 = 46 +SPARC_REG_F60 = 47 +SPARC_REG_F62 = 48 +SPARC_REG_FCC0 = 49 +SPARC_REG_FCC1 = 50 +SPARC_REG_FCC2 = 51 +SPARC_REG_FCC3 = 52 +SPARC_REG_FP = 53 +SPARC_REG_G0 = 54 +SPARC_REG_G1 = 55 +SPARC_REG_G2 = 56 +SPARC_REG_G3 = 57 +SPARC_REG_G4 = 58 +SPARC_REG_G5 = 59 +SPARC_REG_G6 = 60 +SPARC_REG_G7 = 61 +SPARC_REG_I0 = 62 +SPARC_REG_I1 = 63 +SPARC_REG_I2 = 64 +SPARC_REG_I3 = 65 +SPARC_REG_I4 = 66 +SPARC_REG_I5 = 67 +SPARC_REG_I7 = 68 +SPARC_REG_ICC = 69 +SPARC_REG_L0 = 70 +SPARC_REG_L1 = 71 +SPARC_REG_L2 = 72 +SPARC_REG_L3 = 73 +SPARC_REG_L4 = 74 +SPARC_REG_L5 = 75 +SPARC_REG_L6 = 76 +SPARC_REG_L7 = 77 +SPARC_REG_O0 = 78 +SPARC_REG_O1 = 79 +SPARC_REG_O2 = 80 +SPARC_REG_O3 = 81 +SPARC_REG_O4 = 82 +SPARC_REG_O5 = 83 +SPARC_REG_O7 = 84 +SPARC_REG_SP = 85 +SPARC_REG_Y = 86 +SPARC_REG_XCC = 87 +SPARC_REG_ENDING = 88 +SPARC_REG_O6 = SPARC_REG_SP +SPARC_REG_I6 = SPARC_REG_FP + +SPARC_INS_INVALID = 0 +SPARC_INS_ADDCC = 1 +SPARC_INS_ADDX = 2 +SPARC_INS_ADDXCC = 3 +SPARC_INS_ADDXC = 4 +SPARC_INS_ADDXCCC = 5 +SPARC_INS_ADD = 6 +SPARC_INS_ALIGNADDR = 7 +SPARC_INS_ALIGNADDRL = 8 +SPARC_INS_ANDCC = 9 +SPARC_INS_ANDNCC = 10 +SPARC_INS_ANDN = 11 +SPARC_INS_AND = 12 +SPARC_INS_ARRAY16 = 13 +SPARC_INS_ARRAY32 = 14 +SPARC_INS_ARRAY8 = 15 +SPARC_INS_B = 16 +SPARC_INS_JMP = 17 +SPARC_INS_BMASK = 18 +SPARC_INS_FB = 19 +SPARC_INS_BRGEZ = 20 +SPARC_INS_BRGZ = 21 +SPARC_INS_BRLEZ = 22 +SPARC_INS_BRLZ = 23 +SPARC_INS_BRNZ = 24 +SPARC_INS_BRZ = 25 +SPARC_INS_BSHUFFLE = 26 +SPARC_INS_CALL = 27 +SPARC_INS_CASX = 28 +SPARC_INS_CAS = 29 +SPARC_INS_CMASK16 = 30 +SPARC_INS_CMASK32 = 31 +SPARC_INS_CMASK8 = 32 +SPARC_INS_CMP = 33 +SPARC_INS_EDGE16 = 34 +SPARC_INS_EDGE16L = 35 +SPARC_INS_EDGE16LN = 36 +SPARC_INS_EDGE16N = 37 +SPARC_INS_EDGE32 = 38 +SPARC_INS_EDGE32L = 39 +SPARC_INS_EDGE32LN = 40 +SPARC_INS_EDGE32N = 41 +SPARC_INS_EDGE8 = 42 +SPARC_INS_EDGE8L = 43 +SPARC_INS_EDGE8LN = 44 +SPARC_INS_EDGE8N = 45 +SPARC_INS_FABSD = 46 +SPARC_INS_FABSQ = 47 +SPARC_INS_FABSS = 48 +SPARC_INS_FADDD = 49 +SPARC_INS_FADDQ = 50 +SPARC_INS_FADDS = 51 +SPARC_INS_FALIGNDATA = 52 +SPARC_INS_FAND = 53 +SPARC_INS_FANDNOT1 = 54 +SPARC_INS_FANDNOT1S = 55 +SPARC_INS_FANDNOT2 = 56 +SPARC_INS_FANDNOT2S = 57 +SPARC_INS_FANDS = 58 +SPARC_INS_FCHKSM16 = 59 +SPARC_INS_FCMPD = 60 +SPARC_INS_FCMPEQ16 = 61 +SPARC_INS_FCMPEQ32 = 62 +SPARC_INS_FCMPGT16 = 63 +SPARC_INS_FCMPGT32 = 64 +SPARC_INS_FCMPLE16 = 65 +SPARC_INS_FCMPLE32 = 66 +SPARC_INS_FCMPNE16 = 67 +SPARC_INS_FCMPNE32 = 68 +SPARC_INS_FCMPQ = 69 +SPARC_INS_FCMPS = 70 +SPARC_INS_FDIVD = 71 +SPARC_INS_FDIVQ = 72 +SPARC_INS_FDIVS = 73 +SPARC_INS_FDMULQ = 74 +SPARC_INS_FDTOI = 75 +SPARC_INS_FDTOQ = 76 +SPARC_INS_FDTOS = 77 +SPARC_INS_FDTOX = 78 +SPARC_INS_FEXPAND = 79 +SPARC_INS_FHADDD = 80 +SPARC_INS_FHADDS = 81 +SPARC_INS_FHSUBD = 82 +SPARC_INS_FHSUBS = 83 +SPARC_INS_FITOD = 84 +SPARC_INS_FITOQ = 85 +SPARC_INS_FITOS = 86 +SPARC_INS_FLCMPD = 87 +SPARC_INS_FLCMPS = 88 +SPARC_INS_FLUSHW = 89 +SPARC_INS_FMEAN16 = 90 +SPARC_INS_FMOVD = 91 +SPARC_INS_FMOVQ = 92 +SPARC_INS_FMOVRDGEZ = 93 +SPARC_INS_FMOVRQGEZ = 94 +SPARC_INS_FMOVRSGEZ = 95 +SPARC_INS_FMOVRDGZ = 96 +SPARC_INS_FMOVRQGZ = 97 +SPARC_INS_FMOVRSGZ = 98 +SPARC_INS_FMOVRDLEZ = 99 +SPARC_INS_FMOVRQLEZ = 100 +SPARC_INS_FMOVRSLEZ = 101 +SPARC_INS_FMOVRDLZ = 102 +SPARC_INS_FMOVRQLZ = 103 +SPARC_INS_FMOVRSLZ = 104 +SPARC_INS_FMOVRDNZ = 105 +SPARC_INS_FMOVRQNZ = 106 +SPARC_INS_FMOVRSNZ = 107 +SPARC_INS_FMOVRDZ = 108 +SPARC_INS_FMOVRQZ = 109 +SPARC_INS_FMOVRSZ = 110 +SPARC_INS_FMOVS = 111 +SPARC_INS_FMUL8SUX16 = 112 +SPARC_INS_FMUL8ULX16 = 113 +SPARC_INS_FMUL8X16 = 114 +SPARC_INS_FMUL8X16AL = 115 +SPARC_INS_FMUL8X16AU = 116 +SPARC_INS_FMULD = 117 +SPARC_INS_FMULD8SUX16 = 118 +SPARC_INS_FMULD8ULX16 = 119 +SPARC_INS_FMULQ = 120 +SPARC_INS_FMULS = 121 +SPARC_INS_FNADDD = 122 +SPARC_INS_FNADDS = 123 +SPARC_INS_FNAND = 124 +SPARC_INS_FNANDS = 125 +SPARC_INS_FNEGD = 126 +SPARC_INS_FNEGQ = 127 +SPARC_INS_FNEGS = 128 +SPARC_INS_FNHADDD = 129 +SPARC_INS_FNHADDS = 130 +SPARC_INS_FNOR = 131 +SPARC_INS_FNORS = 132 +SPARC_INS_FNOT1 = 133 +SPARC_INS_FNOT1S = 134 +SPARC_INS_FNOT2 = 135 +SPARC_INS_FNOT2S = 136 +SPARC_INS_FONE = 137 +SPARC_INS_FONES = 138 +SPARC_INS_FOR = 139 +SPARC_INS_FORNOT1 = 140 +SPARC_INS_FORNOT1S = 141 +SPARC_INS_FORNOT2 = 142 +SPARC_INS_FORNOT2S = 143 +SPARC_INS_FORS = 144 +SPARC_INS_FPACK16 = 145 +SPARC_INS_FPACK32 = 146 +SPARC_INS_FPACKFIX = 147 +SPARC_INS_FPADD16 = 148 +SPARC_INS_FPADD16S = 149 +SPARC_INS_FPADD32 = 150 +SPARC_INS_FPADD32S = 151 +SPARC_INS_FPADD64 = 152 +SPARC_INS_FPMERGE = 153 +SPARC_INS_FPSUB16 = 154 +SPARC_INS_FPSUB16S = 155 +SPARC_INS_FPSUB32 = 156 +SPARC_INS_FPSUB32S = 157 +SPARC_INS_FQTOD = 158 +SPARC_INS_FQTOI = 159 +SPARC_INS_FQTOS = 160 +SPARC_INS_FQTOX = 161 +SPARC_INS_FSLAS16 = 162 +SPARC_INS_FSLAS32 = 163 +SPARC_INS_FSLL16 = 164 +SPARC_INS_FSLL32 = 165 +SPARC_INS_FSMULD = 166 +SPARC_INS_FSQRTD = 167 +SPARC_INS_FSQRTQ = 168 +SPARC_INS_FSQRTS = 169 +SPARC_INS_FSRA16 = 170 +SPARC_INS_FSRA32 = 171 +SPARC_INS_FSRC1 = 172 +SPARC_INS_FSRC1S = 173 +SPARC_INS_FSRC2 = 174 +SPARC_INS_FSRC2S = 175 +SPARC_INS_FSRL16 = 176 +SPARC_INS_FSRL32 = 177 +SPARC_INS_FSTOD = 178 +SPARC_INS_FSTOI = 179 +SPARC_INS_FSTOQ = 180 +SPARC_INS_FSTOX = 181 +SPARC_INS_FSUBD = 182 +SPARC_INS_FSUBQ = 183 +SPARC_INS_FSUBS = 184 +SPARC_INS_FXNOR = 185 +SPARC_INS_FXNORS = 186 +SPARC_INS_FXOR = 187 +SPARC_INS_FXORS = 188 +SPARC_INS_FXTOD = 189 +SPARC_INS_FXTOQ = 190 +SPARC_INS_FXTOS = 191 +SPARC_INS_FZERO = 192 +SPARC_INS_FZEROS = 193 +SPARC_INS_JMPL = 194 +SPARC_INS_LDD = 195 +SPARC_INS_LD = 196 +SPARC_INS_LDQ = 197 +SPARC_INS_LDSB = 198 +SPARC_INS_LDSH = 199 +SPARC_INS_LDSW = 200 +SPARC_INS_LDUB = 201 +SPARC_INS_LDUH = 202 +SPARC_INS_LDX = 203 +SPARC_INS_LZCNT = 204 +SPARC_INS_MEMBAR = 205 +SPARC_INS_MOVDTOX = 206 +SPARC_INS_MOV = 207 +SPARC_INS_MOVRGEZ = 208 +SPARC_INS_MOVRGZ = 209 +SPARC_INS_MOVRLEZ = 210 +SPARC_INS_MOVRLZ = 211 +SPARC_INS_MOVRNZ = 212 +SPARC_INS_MOVRZ = 213 +SPARC_INS_MOVSTOSW = 214 +SPARC_INS_MOVSTOUW = 215 +SPARC_INS_MULX = 216 +SPARC_INS_NOP = 217 +SPARC_INS_ORCC = 218 +SPARC_INS_ORNCC = 219 +SPARC_INS_ORN = 220 +SPARC_INS_OR = 221 +SPARC_INS_PDIST = 222 +SPARC_INS_PDISTN = 223 +SPARC_INS_POPC = 224 +SPARC_INS_RD = 225 +SPARC_INS_RESTORE = 226 +SPARC_INS_RETT = 227 +SPARC_INS_SAVE = 228 +SPARC_INS_SDIVCC = 229 +SPARC_INS_SDIVX = 230 +SPARC_INS_SDIV = 231 +SPARC_INS_SETHI = 232 +SPARC_INS_SHUTDOWN = 233 +SPARC_INS_SIAM = 234 +SPARC_INS_SLLX = 235 +SPARC_INS_SLL = 236 +SPARC_INS_SMULCC = 237 +SPARC_INS_SMUL = 238 +SPARC_INS_SRAX = 239 +SPARC_INS_SRA = 240 +SPARC_INS_SRLX = 241 +SPARC_INS_SRL = 242 +SPARC_INS_STBAR = 243 +SPARC_INS_STB = 244 +SPARC_INS_STD = 245 +SPARC_INS_ST = 246 +SPARC_INS_STH = 247 +SPARC_INS_STQ = 248 +SPARC_INS_STX = 249 +SPARC_INS_SUBCC = 250 +SPARC_INS_SUBX = 251 +SPARC_INS_SUBXCC = 252 +SPARC_INS_SUB = 253 +SPARC_INS_SWAP = 254 +SPARC_INS_TADDCCTV = 255 +SPARC_INS_TADDCC = 256 +SPARC_INS_T = 257 +SPARC_INS_TSUBCCTV = 258 +SPARC_INS_TSUBCC = 259 +SPARC_INS_UDIVCC = 260 +SPARC_INS_UDIVX = 261 +SPARC_INS_UDIV = 262 +SPARC_INS_UMULCC = 263 +SPARC_INS_UMULXHI = 264 +SPARC_INS_UMUL = 265 +SPARC_INS_UNIMP = 266 +SPARC_INS_FCMPED = 267 +SPARC_INS_FCMPEQ = 268 +SPARC_INS_FCMPES = 269 +SPARC_INS_WR = 270 +SPARC_INS_XMULX = 271 +SPARC_INS_XMULXHI = 272 +SPARC_INS_XNORCC = 273 +SPARC_INS_XNOR = 274 +SPARC_INS_XORCC = 275 +SPARC_INS_XOR = 276 +SPARC_INS_RET = 277 +SPARC_INS_RETL = 278 +SPARC_INS_ENDING = 279 + +SPARC_GRP_INVALID = 0 +SPARC_GRP_JUMP = 1 +SPARC_GRP_HARDQUAD = 128 +SPARC_GRP_V9 = 129 +SPARC_GRP_VIS = 130 +SPARC_GRP_VIS2 = 131 +SPARC_GRP_VIS3 = 132 +SPARC_GRP_32BIT = 133 +SPARC_GRP_64BIT = 134 +SPARC_GRP_ENDING = 135 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/systemz.py b/white_patch_detect/capstone-master/bindings/python/capstone/systemz.py new file mode 100644 index 0000000..398018b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/systemz.py @@ -0,0 +1,51 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .sysz_const import * + +# define the API +class SyszOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint8), + ('index', ctypes.c_uint8), + ('length', ctypes.c_uint64), + ('disp', ctypes.c_int64), + ) + +class SyszOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', SyszOpMem), + ) + +class SyszOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', SyszOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsSysz(ctypes.Structure): + _fields_ = ( + ('cc', ctypes.c_uint), + ('op_count', ctypes.c_uint8), + ('operands', SyszOp * 6), + ) + +def get_arch_info(a): + return (a.cc, copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/sysz_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/sysz_const.py new file mode 100644 index 0000000..e2e9cdd --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/sysz_const.py @@ -0,0 +1,2523 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.py] + +SYSZ_CC_INVALID = 0 +SYSZ_CC_O = 1 +SYSZ_CC_H = 2 +SYSZ_CC_NLE = 3 +SYSZ_CC_L = 4 +SYSZ_CC_NHE = 5 +SYSZ_CC_LH = 6 +SYSZ_CC_NE = 7 +SYSZ_CC_E = 8 +SYSZ_CC_NLH = 9 +SYSZ_CC_HE = 10 +SYSZ_CC_NL = 11 +SYSZ_CC_LE = 12 +SYSZ_CC_NH = 13 +SYSZ_CC_NO = 14 + +SYSZ_OP_INVALID = 0 +SYSZ_OP_REG = 1 +SYSZ_OP_IMM = 2 +SYSZ_OP_MEM = 3 +SYSZ_OP_ACREG = 64 + +SYSZ_REG_INVALID = 0 +SYSZ_REG_0 = 1 +SYSZ_REG_1 = 2 +SYSZ_REG_2 = 3 +SYSZ_REG_3 = 4 +SYSZ_REG_4 = 5 +SYSZ_REG_5 = 6 +SYSZ_REG_6 = 7 +SYSZ_REG_7 = 8 +SYSZ_REG_8 = 9 +SYSZ_REG_9 = 10 +SYSZ_REG_10 = 11 +SYSZ_REG_11 = 12 +SYSZ_REG_12 = 13 +SYSZ_REG_13 = 14 +SYSZ_REG_14 = 15 +SYSZ_REG_15 = 16 +SYSZ_REG_CC = 17 +SYSZ_REG_F0 = 18 +SYSZ_REG_F1 = 19 +SYSZ_REG_F2 = 20 +SYSZ_REG_F3 = 21 +SYSZ_REG_F4 = 22 +SYSZ_REG_F5 = 23 +SYSZ_REG_F6 = 24 +SYSZ_REG_F7 = 25 +SYSZ_REG_F8 = 26 +SYSZ_REG_F9 = 27 +SYSZ_REG_F10 = 28 +SYSZ_REG_F11 = 29 +SYSZ_REG_F12 = 30 +SYSZ_REG_F13 = 31 +SYSZ_REG_F14 = 32 +SYSZ_REG_F15 = 33 +SYSZ_REG_R0L = 34 +SYSZ_REG_A0 = 35 +SYSZ_REG_A1 = 36 +SYSZ_REG_A2 = 37 +SYSZ_REG_A3 = 38 +SYSZ_REG_A4 = 39 +SYSZ_REG_A5 = 40 +SYSZ_REG_A6 = 41 +SYSZ_REG_A7 = 42 +SYSZ_REG_A8 = 43 +SYSZ_REG_A9 = 44 +SYSZ_REG_A10 = 45 +SYSZ_REG_A11 = 46 +SYSZ_REG_A12 = 47 +SYSZ_REG_A13 = 48 +SYSZ_REG_A14 = 49 +SYSZ_REG_A15 = 50 +SYSZ_REG_C0 = 51 +SYSZ_REG_C1 = 52 +SYSZ_REG_C2 = 53 +SYSZ_REG_C3 = 54 +SYSZ_REG_C4 = 55 +SYSZ_REG_C5 = 56 +SYSZ_REG_C6 = 57 +SYSZ_REG_C7 = 58 +SYSZ_REG_C8 = 59 +SYSZ_REG_C9 = 60 +SYSZ_REG_C10 = 61 +SYSZ_REG_C11 = 62 +SYSZ_REG_C12 = 63 +SYSZ_REG_C13 = 64 +SYSZ_REG_C14 = 65 +SYSZ_REG_C15 = 66 +SYSZ_REG_V0 = 67 +SYSZ_REG_V1 = 68 +SYSZ_REG_V2 = 69 +SYSZ_REG_V3 = 70 +SYSZ_REG_V4 = 71 +SYSZ_REG_V5 = 72 +SYSZ_REG_V6 = 73 +SYSZ_REG_V7 = 74 +SYSZ_REG_V8 = 75 +SYSZ_REG_V9 = 76 +SYSZ_REG_V10 = 77 +SYSZ_REG_V11 = 78 +SYSZ_REG_V12 = 79 +SYSZ_REG_V13 = 80 +SYSZ_REG_V14 = 81 +SYSZ_REG_V15 = 82 +SYSZ_REG_V16 = 83 +SYSZ_REG_V17 = 84 +SYSZ_REG_V18 = 85 +SYSZ_REG_V19 = 86 +SYSZ_REG_V20 = 87 +SYSZ_REG_V21 = 88 +SYSZ_REG_V22 = 89 +SYSZ_REG_V23 = 90 +SYSZ_REG_V24 = 91 +SYSZ_REG_V25 = 92 +SYSZ_REG_V26 = 93 +SYSZ_REG_V27 = 94 +SYSZ_REG_V28 = 95 +SYSZ_REG_V29 = 96 +SYSZ_REG_V30 = 97 +SYSZ_REG_V31 = 98 +SYSZ_REG_F16 = 99 +SYSZ_REG_F17 = 100 +SYSZ_REG_F18 = 101 +SYSZ_REG_F19 = 102 +SYSZ_REG_F20 = 103 +SYSZ_REG_F21 = 104 +SYSZ_REG_F22 = 105 +SYSZ_REG_F23 = 106 +SYSZ_REG_F24 = 107 +SYSZ_REG_F25 = 108 +SYSZ_REG_F26 = 109 +SYSZ_REG_F27 = 110 +SYSZ_REG_F28 = 111 +SYSZ_REG_F29 = 112 +SYSZ_REG_F30 = 113 +SYSZ_REG_F31 = 114 +SYSZ_REG_F0Q = 115 +SYSZ_REG_F4Q = 116 +SYSZ_REG_ENDING = 117 + +SYSZ_INS_INVALID = 0 +SYSZ_INS_A = 1 +SYSZ_INS_ADB = 2 +SYSZ_INS_ADBR = 3 +SYSZ_INS_AEB = 4 +SYSZ_INS_AEBR = 5 +SYSZ_INS_AFI = 6 +SYSZ_INS_AG = 7 +SYSZ_INS_AGF = 8 +SYSZ_INS_AGFI = 9 +SYSZ_INS_AGFR = 10 +SYSZ_INS_AGHI = 11 +SYSZ_INS_AGHIK = 12 +SYSZ_INS_AGR = 13 +SYSZ_INS_AGRK = 14 +SYSZ_INS_AGSI = 15 +SYSZ_INS_AH = 16 +SYSZ_INS_AHI = 17 +SYSZ_INS_AHIK = 18 +SYSZ_INS_AHY = 19 +SYSZ_INS_AIH = 20 +SYSZ_INS_AL = 21 +SYSZ_INS_ALC = 22 +SYSZ_INS_ALCG = 23 +SYSZ_INS_ALCGR = 24 +SYSZ_INS_ALCR = 25 +SYSZ_INS_ALFI = 26 +SYSZ_INS_ALG = 27 +SYSZ_INS_ALGF = 28 +SYSZ_INS_ALGFI = 29 +SYSZ_INS_ALGFR = 30 +SYSZ_INS_ALGHSIK = 31 +SYSZ_INS_ALGR = 32 +SYSZ_INS_ALGRK = 33 +SYSZ_INS_ALHSIK = 34 +SYSZ_INS_ALR = 35 +SYSZ_INS_ALRK = 36 +SYSZ_INS_ALY = 37 +SYSZ_INS_AR = 38 +SYSZ_INS_ARK = 39 +SYSZ_INS_ASI = 40 +SYSZ_INS_AXBR = 41 +SYSZ_INS_AY = 42 +SYSZ_INS_BCR = 43 +SYSZ_INS_BRC = 44 +SYSZ_INS_BRCL = 45 +SYSZ_INS_CGIJ = 46 +SYSZ_INS_CGRJ = 47 +SYSZ_INS_CIJ = 48 +SYSZ_INS_CLGIJ = 49 +SYSZ_INS_CLGRJ = 50 +SYSZ_INS_CLIJ = 51 +SYSZ_INS_CLRJ = 52 +SYSZ_INS_CRJ = 53 +SYSZ_INS_BER = 54 +SYSZ_INS_JE = 55 +SYSZ_INS_JGE = 56 +SYSZ_INS_LOCE = 57 +SYSZ_INS_LOCGE = 58 +SYSZ_INS_LOCGRE = 59 +SYSZ_INS_LOCRE = 60 +SYSZ_INS_STOCE = 61 +SYSZ_INS_STOCGE = 62 +SYSZ_INS_BHR = 63 +SYSZ_INS_BHER = 64 +SYSZ_INS_JHE = 65 +SYSZ_INS_JGHE = 66 +SYSZ_INS_LOCHE = 67 +SYSZ_INS_LOCGHE = 68 +SYSZ_INS_LOCGRHE = 69 +SYSZ_INS_LOCRHE = 70 +SYSZ_INS_STOCHE = 71 +SYSZ_INS_STOCGHE = 72 +SYSZ_INS_JH = 73 +SYSZ_INS_JGH = 74 +SYSZ_INS_LOCH = 75 +SYSZ_INS_LOCGH = 76 +SYSZ_INS_LOCGRH = 77 +SYSZ_INS_LOCRH = 78 +SYSZ_INS_STOCH = 79 +SYSZ_INS_STOCGH = 80 +SYSZ_INS_CGIJNLH = 81 +SYSZ_INS_CGRJNLH = 82 +SYSZ_INS_CIJNLH = 83 +SYSZ_INS_CLGIJNLH = 84 +SYSZ_INS_CLGRJNLH = 85 +SYSZ_INS_CLIJNLH = 86 +SYSZ_INS_CLRJNLH = 87 +SYSZ_INS_CRJNLH = 88 +SYSZ_INS_CGIJE = 89 +SYSZ_INS_CGRJE = 90 +SYSZ_INS_CIJE = 91 +SYSZ_INS_CLGIJE = 92 +SYSZ_INS_CLGRJE = 93 +SYSZ_INS_CLIJE = 94 +SYSZ_INS_CLRJE = 95 +SYSZ_INS_CRJE = 96 +SYSZ_INS_CGIJNLE = 97 +SYSZ_INS_CGRJNLE = 98 +SYSZ_INS_CIJNLE = 99 +SYSZ_INS_CLGIJNLE = 100 +SYSZ_INS_CLGRJNLE = 101 +SYSZ_INS_CLIJNLE = 102 +SYSZ_INS_CLRJNLE = 103 +SYSZ_INS_CRJNLE = 104 +SYSZ_INS_CGIJH = 105 +SYSZ_INS_CGRJH = 106 +SYSZ_INS_CIJH = 107 +SYSZ_INS_CLGIJH = 108 +SYSZ_INS_CLGRJH = 109 +SYSZ_INS_CLIJH = 110 +SYSZ_INS_CLRJH = 111 +SYSZ_INS_CRJH = 112 +SYSZ_INS_CGIJNL = 113 +SYSZ_INS_CGRJNL = 114 +SYSZ_INS_CIJNL = 115 +SYSZ_INS_CLGIJNL = 116 +SYSZ_INS_CLGRJNL = 117 +SYSZ_INS_CLIJNL = 118 +SYSZ_INS_CLRJNL = 119 +SYSZ_INS_CRJNL = 120 +SYSZ_INS_CGIJHE = 121 +SYSZ_INS_CGRJHE = 122 +SYSZ_INS_CIJHE = 123 +SYSZ_INS_CLGIJHE = 124 +SYSZ_INS_CLGRJHE = 125 +SYSZ_INS_CLIJHE = 126 +SYSZ_INS_CLRJHE = 127 +SYSZ_INS_CRJHE = 128 +SYSZ_INS_CGIJNHE = 129 +SYSZ_INS_CGRJNHE = 130 +SYSZ_INS_CIJNHE = 131 +SYSZ_INS_CLGIJNHE = 132 +SYSZ_INS_CLGRJNHE = 133 +SYSZ_INS_CLIJNHE = 134 +SYSZ_INS_CLRJNHE = 135 +SYSZ_INS_CRJNHE = 136 +SYSZ_INS_CGIJL = 137 +SYSZ_INS_CGRJL = 138 +SYSZ_INS_CIJL = 139 +SYSZ_INS_CLGIJL = 140 +SYSZ_INS_CLGRJL = 141 +SYSZ_INS_CLIJL = 142 +SYSZ_INS_CLRJL = 143 +SYSZ_INS_CRJL = 144 +SYSZ_INS_CGIJNH = 145 +SYSZ_INS_CGRJNH = 146 +SYSZ_INS_CIJNH = 147 +SYSZ_INS_CLGIJNH = 148 +SYSZ_INS_CLGRJNH = 149 +SYSZ_INS_CLIJNH = 150 +SYSZ_INS_CLRJNH = 151 +SYSZ_INS_CRJNH = 152 +SYSZ_INS_CGIJLE = 153 +SYSZ_INS_CGRJLE = 154 +SYSZ_INS_CIJLE = 155 +SYSZ_INS_CLGIJLE = 156 +SYSZ_INS_CLGRJLE = 157 +SYSZ_INS_CLIJLE = 158 +SYSZ_INS_CLRJLE = 159 +SYSZ_INS_CRJLE = 160 +SYSZ_INS_CGIJNE = 161 +SYSZ_INS_CGRJNE = 162 +SYSZ_INS_CIJNE = 163 +SYSZ_INS_CLGIJNE = 164 +SYSZ_INS_CLGRJNE = 165 +SYSZ_INS_CLIJNE = 166 +SYSZ_INS_CLRJNE = 167 +SYSZ_INS_CRJNE = 168 +SYSZ_INS_CGIJLH = 169 +SYSZ_INS_CGRJLH = 170 +SYSZ_INS_CIJLH = 171 +SYSZ_INS_CLGIJLH = 172 +SYSZ_INS_CLGRJLH = 173 +SYSZ_INS_CLIJLH = 174 +SYSZ_INS_CLRJLH = 175 +SYSZ_INS_CRJLH = 176 +SYSZ_INS_BLR = 177 +SYSZ_INS_BLER = 178 +SYSZ_INS_JLE = 179 +SYSZ_INS_JGLE = 180 +SYSZ_INS_LOCLE = 181 +SYSZ_INS_LOCGLE = 182 +SYSZ_INS_LOCGRLE = 183 +SYSZ_INS_LOCRLE = 184 +SYSZ_INS_STOCLE = 185 +SYSZ_INS_STOCGLE = 186 +SYSZ_INS_BLHR = 187 +SYSZ_INS_JLH = 188 +SYSZ_INS_JGLH = 189 +SYSZ_INS_LOCLH = 190 +SYSZ_INS_LOCGLH = 191 +SYSZ_INS_LOCGRLH = 192 +SYSZ_INS_LOCRLH = 193 +SYSZ_INS_STOCLH = 194 +SYSZ_INS_STOCGLH = 195 +SYSZ_INS_JL = 196 +SYSZ_INS_JGL = 197 +SYSZ_INS_LOCL = 198 +SYSZ_INS_LOCGL = 199 +SYSZ_INS_LOCGRL = 200 +SYSZ_INS_LOCRL = 201 +SYSZ_INS_LOC = 202 +SYSZ_INS_LOCG = 203 +SYSZ_INS_LOCGR = 204 +SYSZ_INS_LOCR = 205 +SYSZ_INS_STOCL = 206 +SYSZ_INS_STOCGL = 207 +SYSZ_INS_BNER = 208 +SYSZ_INS_JNE = 209 +SYSZ_INS_JGNE = 210 +SYSZ_INS_LOCNE = 211 +SYSZ_INS_LOCGNE = 212 +SYSZ_INS_LOCGRNE = 213 +SYSZ_INS_LOCRNE = 214 +SYSZ_INS_STOCNE = 215 +SYSZ_INS_STOCGNE = 216 +SYSZ_INS_BNHR = 217 +SYSZ_INS_BNHER = 218 +SYSZ_INS_JNHE = 219 +SYSZ_INS_JGNHE = 220 +SYSZ_INS_LOCNHE = 221 +SYSZ_INS_LOCGNHE = 222 +SYSZ_INS_LOCGRNHE = 223 +SYSZ_INS_LOCRNHE = 224 +SYSZ_INS_STOCNHE = 225 +SYSZ_INS_STOCGNHE = 226 +SYSZ_INS_JNH = 227 +SYSZ_INS_JGNH = 228 +SYSZ_INS_LOCNH = 229 +SYSZ_INS_LOCGNH = 230 +SYSZ_INS_LOCGRNH = 231 +SYSZ_INS_LOCRNH = 232 +SYSZ_INS_STOCNH = 233 +SYSZ_INS_STOCGNH = 234 +SYSZ_INS_BNLR = 235 +SYSZ_INS_BNLER = 236 +SYSZ_INS_JNLE = 237 +SYSZ_INS_JGNLE = 238 +SYSZ_INS_LOCNLE = 239 +SYSZ_INS_LOCGNLE = 240 +SYSZ_INS_LOCGRNLE = 241 +SYSZ_INS_LOCRNLE = 242 +SYSZ_INS_STOCNLE = 243 +SYSZ_INS_STOCGNLE = 244 +SYSZ_INS_BNLHR = 245 +SYSZ_INS_JNLH = 246 +SYSZ_INS_JGNLH = 247 +SYSZ_INS_LOCNLH = 248 +SYSZ_INS_LOCGNLH = 249 +SYSZ_INS_LOCGRNLH = 250 +SYSZ_INS_LOCRNLH = 251 +SYSZ_INS_STOCNLH = 252 +SYSZ_INS_STOCGNLH = 253 +SYSZ_INS_JNL = 254 +SYSZ_INS_JGNL = 255 +SYSZ_INS_LOCNL = 256 +SYSZ_INS_LOCGNL = 257 +SYSZ_INS_LOCGRNL = 258 +SYSZ_INS_LOCRNL = 259 +SYSZ_INS_STOCNL = 260 +SYSZ_INS_STOCGNL = 261 +SYSZ_INS_BNOR = 262 +SYSZ_INS_JNO = 263 +SYSZ_INS_JGNO = 264 +SYSZ_INS_LOCNO = 265 +SYSZ_INS_LOCGNO = 266 +SYSZ_INS_LOCGRNO = 267 +SYSZ_INS_LOCRNO = 268 +SYSZ_INS_STOCNO = 269 +SYSZ_INS_STOCGNO = 270 +SYSZ_INS_BOR = 271 +SYSZ_INS_JO = 272 +SYSZ_INS_JGO = 273 +SYSZ_INS_LOCO = 274 +SYSZ_INS_LOCGO = 275 +SYSZ_INS_LOCGRO = 276 +SYSZ_INS_LOCRO = 277 +SYSZ_INS_STOCO = 278 +SYSZ_INS_STOCGO = 279 +SYSZ_INS_STOC = 280 +SYSZ_INS_STOCG = 281 +SYSZ_INS_BASR = 282 +SYSZ_INS_BR = 283 +SYSZ_INS_BRAS = 284 +SYSZ_INS_BRASL = 285 +SYSZ_INS_J = 286 +SYSZ_INS_JG = 287 +SYSZ_INS_BRCT = 288 +SYSZ_INS_BRCTG = 289 +SYSZ_INS_C = 290 +SYSZ_INS_CDB = 291 +SYSZ_INS_CDBR = 292 +SYSZ_INS_CDFBR = 293 +SYSZ_INS_CDGBR = 294 +SYSZ_INS_CDLFBR = 295 +SYSZ_INS_CDLGBR = 296 +SYSZ_INS_CEB = 297 +SYSZ_INS_CEBR = 298 +SYSZ_INS_CEFBR = 299 +SYSZ_INS_CEGBR = 300 +SYSZ_INS_CELFBR = 301 +SYSZ_INS_CELGBR = 302 +SYSZ_INS_CFDBR = 303 +SYSZ_INS_CFEBR = 304 +SYSZ_INS_CFI = 305 +SYSZ_INS_CFXBR = 306 +SYSZ_INS_CG = 307 +SYSZ_INS_CGDBR = 308 +SYSZ_INS_CGEBR = 309 +SYSZ_INS_CGF = 310 +SYSZ_INS_CGFI = 311 +SYSZ_INS_CGFR = 312 +SYSZ_INS_CGFRL = 313 +SYSZ_INS_CGH = 314 +SYSZ_INS_CGHI = 315 +SYSZ_INS_CGHRL = 316 +SYSZ_INS_CGHSI = 317 +SYSZ_INS_CGR = 318 +SYSZ_INS_CGRL = 319 +SYSZ_INS_CGXBR = 320 +SYSZ_INS_CH = 321 +SYSZ_INS_CHF = 322 +SYSZ_INS_CHHSI = 323 +SYSZ_INS_CHI = 324 +SYSZ_INS_CHRL = 325 +SYSZ_INS_CHSI = 326 +SYSZ_INS_CHY = 327 +SYSZ_INS_CIH = 328 +SYSZ_INS_CL = 329 +SYSZ_INS_CLC = 330 +SYSZ_INS_CLFDBR = 331 +SYSZ_INS_CLFEBR = 332 +SYSZ_INS_CLFHSI = 333 +SYSZ_INS_CLFI = 334 +SYSZ_INS_CLFXBR = 335 +SYSZ_INS_CLG = 336 +SYSZ_INS_CLGDBR = 337 +SYSZ_INS_CLGEBR = 338 +SYSZ_INS_CLGF = 339 +SYSZ_INS_CLGFI = 340 +SYSZ_INS_CLGFR = 341 +SYSZ_INS_CLGFRL = 342 +SYSZ_INS_CLGHRL = 343 +SYSZ_INS_CLGHSI = 344 +SYSZ_INS_CLGR = 345 +SYSZ_INS_CLGRL = 346 +SYSZ_INS_CLGXBR = 347 +SYSZ_INS_CLHF = 348 +SYSZ_INS_CLHHSI = 349 +SYSZ_INS_CLHRL = 350 +SYSZ_INS_CLI = 351 +SYSZ_INS_CLIH = 352 +SYSZ_INS_CLIY = 353 +SYSZ_INS_CLR = 354 +SYSZ_INS_CLRL = 355 +SYSZ_INS_CLST = 356 +SYSZ_INS_CLY = 357 +SYSZ_INS_CPSDR = 358 +SYSZ_INS_CR = 359 +SYSZ_INS_CRL = 360 +SYSZ_INS_CS = 361 +SYSZ_INS_CSG = 362 +SYSZ_INS_CSY = 363 +SYSZ_INS_CXBR = 364 +SYSZ_INS_CXFBR = 365 +SYSZ_INS_CXGBR = 366 +SYSZ_INS_CXLFBR = 367 +SYSZ_INS_CXLGBR = 368 +SYSZ_INS_CY = 369 +SYSZ_INS_DDB = 370 +SYSZ_INS_DDBR = 371 +SYSZ_INS_DEB = 372 +SYSZ_INS_DEBR = 373 +SYSZ_INS_DL = 374 +SYSZ_INS_DLG = 375 +SYSZ_INS_DLGR = 376 +SYSZ_INS_DLR = 377 +SYSZ_INS_DSG = 378 +SYSZ_INS_DSGF = 379 +SYSZ_INS_DSGFR = 380 +SYSZ_INS_DSGR = 381 +SYSZ_INS_DXBR = 382 +SYSZ_INS_EAR = 383 +SYSZ_INS_FIDBR = 384 +SYSZ_INS_FIDBRA = 385 +SYSZ_INS_FIEBR = 386 +SYSZ_INS_FIEBRA = 387 +SYSZ_INS_FIXBR = 388 +SYSZ_INS_FIXBRA = 389 +SYSZ_INS_FLOGR = 390 +SYSZ_INS_IC = 391 +SYSZ_INS_ICY = 392 +SYSZ_INS_IIHF = 393 +SYSZ_INS_IIHH = 394 +SYSZ_INS_IIHL = 395 +SYSZ_INS_IILF = 396 +SYSZ_INS_IILH = 397 +SYSZ_INS_IILL = 398 +SYSZ_INS_IPM = 399 +SYSZ_INS_L = 400 +SYSZ_INS_LA = 401 +SYSZ_INS_LAA = 402 +SYSZ_INS_LAAG = 403 +SYSZ_INS_LAAL = 404 +SYSZ_INS_LAALG = 405 +SYSZ_INS_LAN = 406 +SYSZ_INS_LANG = 407 +SYSZ_INS_LAO = 408 +SYSZ_INS_LAOG = 409 +SYSZ_INS_LARL = 410 +SYSZ_INS_LAX = 411 +SYSZ_INS_LAXG = 412 +SYSZ_INS_LAY = 413 +SYSZ_INS_LB = 414 +SYSZ_INS_LBH = 415 +SYSZ_INS_LBR = 416 +SYSZ_INS_LCDBR = 417 +SYSZ_INS_LCEBR = 418 +SYSZ_INS_LCGFR = 419 +SYSZ_INS_LCGR = 420 +SYSZ_INS_LCR = 421 +SYSZ_INS_LCXBR = 422 +SYSZ_INS_LD = 423 +SYSZ_INS_LDEB = 424 +SYSZ_INS_LDEBR = 425 +SYSZ_INS_LDGR = 426 +SYSZ_INS_LDR = 427 +SYSZ_INS_LDXBR = 428 +SYSZ_INS_LDXBRA = 429 +SYSZ_INS_LDY = 430 +SYSZ_INS_LE = 431 +SYSZ_INS_LEDBR = 432 +SYSZ_INS_LEDBRA = 433 +SYSZ_INS_LER = 434 +SYSZ_INS_LEXBR = 435 +SYSZ_INS_LEXBRA = 436 +SYSZ_INS_LEY = 437 +SYSZ_INS_LFH = 438 +SYSZ_INS_LG = 439 +SYSZ_INS_LGB = 440 +SYSZ_INS_LGBR = 441 +SYSZ_INS_LGDR = 442 +SYSZ_INS_LGF = 443 +SYSZ_INS_LGFI = 444 +SYSZ_INS_LGFR = 445 +SYSZ_INS_LGFRL = 446 +SYSZ_INS_LGH = 447 +SYSZ_INS_LGHI = 448 +SYSZ_INS_LGHR = 449 +SYSZ_INS_LGHRL = 450 +SYSZ_INS_LGR = 451 +SYSZ_INS_LGRL = 452 +SYSZ_INS_LH = 453 +SYSZ_INS_LHH = 454 +SYSZ_INS_LHI = 455 +SYSZ_INS_LHR = 456 +SYSZ_INS_LHRL = 457 +SYSZ_INS_LHY = 458 +SYSZ_INS_LLC = 459 +SYSZ_INS_LLCH = 460 +SYSZ_INS_LLCR = 461 +SYSZ_INS_LLGC = 462 +SYSZ_INS_LLGCR = 463 +SYSZ_INS_LLGF = 464 +SYSZ_INS_LLGFR = 465 +SYSZ_INS_LLGFRL = 466 +SYSZ_INS_LLGH = 467 +SYSZ_INS_LLGHR = 468 +SYSZ_INS_LLGHRL = 469 +SYSZ_INS_LLH = 470 +SYSZ_INS_LLHH = 471 +SYSZ_INS_LLHR = 472 +SYSZ_INS_LLHRL = 473 +SYSZ_INS_LLIHF = 474 +SYSZ_INS_LLIHH = 475 +SYSZ_INS_LLIHL = 476 +SYSZ_INS_LLILF = 477 +SYSZ_INS_LLILH = 478 +SYSZ_INS_LLILL = 479 +SYSZ_INS_LMG = 480 +SYSZ_INS_LNDBR = 481 +SYSZ_INS_LNEBR = 482 +SYSZ_INS_LNGFR = 483 +SYSZ_INS_LNGR = 484 +SYSZ_INS_LNR = 485 +SYSZ_INS_LNXBR = 486 +SYSZ_INS_LPDBR = 487 +SYSZ_INS_LPEBR = 488 +SYSZ_INS_LPGFR = 489 +SYSZ_INS_LPGR = 490 +SYSZ_INS_LPR = 491 +SYSZ_INS_LPXBR = 492 +SYSZ_INS_LR = 493 +SYSZ_INS_LRL = 494 +SYSZ_INS_LRV = 495 +SYSZ_INS_LRVG = 496 +SYSZ_INS_LRVGR = 497 +SYSZ_INS_LRVR = 498 +SYSZ_INS_LT = 499 +SYSZ_INS_LTDBR = 500 +SYSZ_INS_LTEBR = 501 +SYSZ_INS_LTG = 502 +SYSZ_INS_LTGF = 503 +SYSZ_INS_LTGFR = 504 +SYSZ_INS_LTGR = 505 +SYSZ_INS_LTR = 506 +SYSZ_INS_LTXBR = 507 +SYSZ_INS_LXDB = 508 +SYSZ_INS_LXDBR = 509 +SYSZ_INS_LXEB = 510 +SYSZ_INS_LXEBR = 511 +SYSZ_INS_LXR = 512 +SYSZ_INS_LY = 513 +SYSZ_INS_LZDR = 514 +SYSZ_INS_LZER = 515 +SYSZ_INS_LZXR = 516 +SYSZ_INS_MADB = 517 +SYSZ_INS_MADBR = 518 +SYSZ_INS_MAEB = 519 +SYSZ_INS_MAEBR = 520 +SYSZ_INS_MDB = 521 +SYSZ_INS_MDBR = 522 +SYSZ_INS_MDEB = 523 +SYSZ_INS_MDEBR = 524 +SYSZ_INS_MEEB = 525 +SYSZ_INS_MEEBR = 526 +SYSZ_INS_MGHI = 527 +SYSZ_INS_MH = 528 +SYSZ_INS_MHI = 529 +SYSZ_INS_MHY = 530 +SYSZ_INS_MLG = 531 +SYSZ_INS_MLGR = 532 +SYSZ_INS_MS = 533 +SYSZ_INS_MSDB = 534 +SYSZ_INS_MSDBR = 535 +SYSZ_INS_MSEB = 536 +SYSZ_INS_MSEBR = 537 +SYSZ_INS_MSFI = 538 +SYSZ_INS_MSG = 539 +SYSZ_INS_MSGF = 540 +SYSZ_INS_MSGFI = 541 +SYSZ_INS_MSGFR = 542 +SYSZ_INS_MSGR = 543 +SYSZ_INS_MSR = 544 +SYSZ_INS_MSY = 545 +SYSZ_INS_MVC = 546 +SYSZ_INS_MVGHI = 547 +SYSZ_INS_MVHHI = 548 +SYSZ_INS_MVHI = 549 +SYSZ_INS_MVI = 550 +SYSZ_INS_MVIY = 551 +SYSZ_INS_MVST = 552 +SYSZ_INS_MXBR = 553 +SYSZ_INS_MXDB = 554 +SYSZ_INS_MXDBR = 555 +SYSZ_INS_N = 556 +SYSZ_INS_NC = 557 +SYSZ_INS_NG = 558 +SYSZ_INS_NGR = 559 +SYSZ_INS_NGRK = 560 +SYSZ_INS_NI = 561 +SYSZ_INS_NIHF = 562 +SYSZ_INS_NIHH = 563 +SYSZ_INS_NIHL = 564 +SYSZ_INS_NILF = 565 +SYSZ_INS_NILH = 566 +SYSZ_INS_NILL = 567 +SYSZ_INS_NIY = 568 +SYSZ_INS_NR = 569 +SYSZ_INS_NRK = 570 +SYSZ_INS_NY = 571 +SYSZ_INS_O = 572 +SYSZ_INS_OC = 573 +SYSZ_INS_OG = 574 +SYSZ_INS_OGR = 575 +SYSZ_INS_OGRK = 576 +SYSZ_INS_OI = 577 +SYSZ_INS_OIHF = 578 +SYSZ_INS_OIHH = 579 +SYSZ_INS_OIHL = 580 +SYSZ_INS_OILF = 581 +SYSZ_INS_OILH = 582 +SYSZ_INS_OILL = 583 +SYSZ_INS_OIY = 584 +SYSZ_INS_OR = 585 +SYSZ_INS_ORK = 586 +SYSZ_INS_OY = 587 +SYSZ_INS_PFD = 588 +SYSZ_INS_PFDRL = 589 +SYSZ_INS_RISBG = 590 +SYSZ_INS_RISBHG = 591 +SYSZ_INS_RISBLG = 592 +SYSZ_INS_RLL = 593 +SYSZ_INS_RLLG = 594 +SYSZ_INS_RNSBG = 595 +SYSZ_INS_ROSBG = 596 +SYSZ_INS_RXSBG = 597 +SYSZ_INS_S = 598 +SYSZ_INS_SDB = 599 +SYSZ_INS_SDBR = 600 +SYSZ_INS_SEB = 601 +SYSZ_INS_SEBR = 602 +SYSZ_INS_SG = 603 +SYSZ_INS_SGF = 604 +SYSZ_INS_SGFR = 605 +SYSZ_INS_SGR = 606 +SYSZ_INS_SGRK = 607 +SYSZ_INS_SH = 608 +SYSZ_INS_SHY = 609 +SYSZ_INS_SL = 610 +SYSZ_INS_SLB = 611 +SYSZ_INS_SLBG = 612 +SYSZ_INS_SLBR = 613 +SYSZ_INS_SLFI = 614 +SYSZ_INS_SLG = 615 +SYSZ_INS_SLBGR = 616 +SYSZ_INS_SLGF = 617 +SYSZ_INS_SLGFI = 618 +SYSZ_INS_SLGFR = 619 +SYSZ_INS_SLGR = 620 +SYSZ_INS_SLGRK = 621 +SYSZ_INS_SLL = 622 +SYSZ_INS_SLLG = 623 +SYSZ_INS_SLLK = 624 +SYSZ_INS_SLR = 625 +SYSZ_INS_SLRK = 626 +SYSZ_INS_SLY = 627 +SYSZ_INS_SQDB = 628 +SYSZ_INS_SQDBR = 629 +SYSZ_INS_SQEB = 630 +SYSZ_INS_SQEBR = 631 +SYSZ_INS_SQXBR = 632 +SYSZ_INS_SR = 633 +SYSZ_INS_SRA = 634 +SYSZ_INS_SRAG = 635 +SYSZ_INS_SRAK = 636 +SYSZ_INS_SRK = 637 +SYSZ_INS_SRL = 638 +SYSZ_INS_SRLG = 639 +SYSZ_INS_SRLK = 640 +SYSZ_INS_SRST = 641 +SYSZ_INS_ST = 642 +SYSZ_INS_STC = 643 +SYSZ_INS_STCH = 644 +SYSZ_INS_STCY = 645 +SYSZ_INS_STD = 646 +SYSZ_INS_STDY = 647 +SYSZ_INS_STE = 648 +SYSZ_INS_STEY = 649 +SYSZ_INS_STFH = 650 +SYSZ_INS_STG = 651 +SYSZ_INS_STGRL = 652 +SYSZ_INS_STH = 653 +SYSZ_INS_STHH = 654 +SYSZ_INS_STHRL = 655 +SYSZ_INS_STHY = 656 +SYSZ_INS_STMG = 657 +SYSZ_INS_STRL = 658 +SYSZ_INS_STRV = 659 +SYSZ_INS_STRVG = 660 +SYSZ_INS_STY = 661 +SYSZ_INS_SXBR = 662 +SYSZ_INS_SY = 663 +SYSZ_INS_TM = 664 +SYSZ_INS_TMHH = 665 +SYSZ_INS_TMHL = 666 +SYSZ_INS_TMLH = 667 +SYSZ_INS_TMLL = 668 +SYSZ_INS_TMY = 669 +SYSZ_INS_X = 670 +SYSZ_INS_XC = 671 +SYSZ_INS_XG = 672 +SYSZ_INS_XGR = 673 +SYSZ_INS_XGRK = 674 +SYSZ_INS_XI = 675 +SYSZ_INS_XIHF = 676 +SYSZ_INS_XILF = 677 +SYSZ_INS_XIY = 678 +SYSZ_INS_XR = 679 +SYSZ_INS_XRK = 680 +SYSZ_INS_XY = 681 +SYSZ_INS_AD = 682 +SYSZ_INS_ADR = 683 +SYSZ_INS_ADTR = 684 +SYSZ_INS_ADTRA = 685 +SYSZ_INS_AE = 686 +SYSZ_INS_AER = 687 +SYSZ_INS_AGH = 688 +SYSZ_INS_AHHHR = 689 +SYSZ_INS_AHHLR = 690 +SYSZ_INS_ALGSI = 691 +SYSZ_INS_ALHHHR = 692 +SYSZ_INS_ALHHLR = 693 +SYSZ_INS_ALSI = 694 +SYSZ_INS_ALSIH = 695 +SYSZ_INS_ALSIHN = 696 +SYSZ_INS_AP = 697 +SYSZ_INS_AU = 698 +SYSZ_INS_AUR = 699 +SYSZ_INS_AW = 700 +SYSZ_INS_AWR = 701 +SYSZ_INS_AXR = 702 +SYSZ_INS_AXTR = 703 +SYSZ_INS_AXTRA = 704 +SYSZ_INS_B = 705 +SYSZ_INS_BAKR = 706 +SYSZ_INS_BAL = 707 +SYSZ_INS_BALR = 708 +SYSZ_INS_BAS = 709 +SYSZ_INS_BASSM = 710 +SYSZ_INS_BC = 711 +SYSZ_INS_BCT = 712 +SYSZ_INS_BCTG = 713 +SYSZ_INS_BCTGR = 714 +SYSZ_INS_BCTR = 715 +SYSZ_INS_BE = 716 +SYSZ_INS_BH = 717 +SYSZ_INS_BHE = 718 +SYSZ_INS_BI = 719 +SYSZ_INS_BIC = 720 +SYSZ_INS_BIE = 721 +SYSZ_INS_BIH = 722 +SYSZ_INS_BIHE = 723 +SYSZ_INS_BIL = 724 +SYSZ_INS_BILE = 725 +SYSZ_INS_BILH = 726 +SYSZ_INS_BIM = 727 +SYSZ_INS_BINE = 728 +SYSZ_INS_BINH = 729 +SYSZ_INS_BINHE = 730 +SYSZ_INS_BINL = 731 +SYSZ_INS_BINLE = 732 +SYSZ_INS_BINLH = 733 +SYSZ_INS_BINM = 734 +SYSZ_INS_BINO = 735 +SYSZ_INS_BINP = 736 +SYSZ_INS_BINZ = 737 +SYSZ_INS_BIO = 738 +SYSZ_INS_BIP = 739 +SYSZ_INS_BIZ = 740 +SYSZ_INS_BL = 741 +SYSZ_INS_BLE = 742 +SYSZ_INS_BLH = 743 +SYSZ_INS_BM = 744 +SYSZ_INS_BMR = 745 +SYSZ_INS_BNE = 746 +SYSZ_INS_BNH = 747 +SYSZ_INS_BNHE = 748 +SYSZ_INS_BNL = 749 +SYSZ_INS_BNLE = 750 +SYSZ_INS_BNLH = 751 +SYSZ_INS_BNM = 752 +SYSZ_INS_BNMR = 753 +SYSZ_INS_BNO = 754 +SYSZ_INS_BNP = 755 +SYSZ_INS_BNPR = 756 +SYSZ_INS_BNZ = 757 +SYSZ_INS_BNZR = 758 +SYSZ_INS_BO = 759 +SYSZ_INS_BP = 760 +SYSZ_INS_BPP = 761 +SYSZ_INS_BPR = 762 +SYSZ_INS_BPRP = 763 +SYSZ_INS_BRCTH = 764 +SYSZ_INS_BRXH = 765 +SYSZ_INS_BRXHG = 766 +SYSZ_INS_BRXLE = 767 +SYSZ_INS_BRXLG = 768 +SYSZ_INS_BSA = 769 +SYSZ_INS_BSG = 770 +SYSZ_INS_BSM = 771 +SYSZ_INS_BXH = 772 +SYSZ_INS_BXHG = 773 +SYSZ_INS_BXLE = 774 +SYSZ_INS_BXLEG = 775 +SYSZ_INS_BZ = 776 +SYSZ_INS_BZR = 777 +SYSZ_INS_CD = 778 +SYSZ_INS_CDFBRA = 779 +SYSZ_INS_CDFR = 780 +SYSZ_INS_CDFTR = 781 +SYSZ_INS_CDGBRA = 782 +SYSZ_INS_CDGR = 783 +SYSZ_INS_CDGTR = 784 +SYSZ_INS_CDGTRA = 785 +SYSZ_INS_CDLFTR = 786 +SYSZ_INS_CDLGTR = 787 +SYSZ_INS_CDPT = 788 +SYSZ_INS_CDR = 789 +SYSZ_INS_CDS = 790 +SYSZ_INS_CDSG = 791 +SYSZ_INS_CDSTR = 792 +SYSZ_INS_CDSY = 793 +SYSZ_INS_CDTR = 794 +SYSZ_INS_CDUTR = 795 +SYSZ_INS_CDZT = 796 +SYSZ_INS_CE = 797 +SYSZ_INS_CEDTR = 798 +SYSZ_INS_CEFBRA = 799 +SYSZ_INS_CEFR = 800 +SYSZ_INS_CEGBRA = 801 +SYSZ_INS_CEGR = 802 +SYSZ_INS_CER = 803 +SYSZ_INS_CEXTR = 804 +SYSZ_INS_CFC = 805 +SYSZ_INS_CFDBRA = 806 +SYSZ_INS_CFDR = 807 +SYSZ_INS_CFDTR = 808 +SYSZ_INS_CFEBRA = 809 +SYSZ_INS_CFER = 810 +SYSZ_INS_CFXBRA = 811 +SYSZ_INS_CFXR = 812 +SYSZ_INS_CFXTR = 813 +SYSZ_INS_CGDBRA = 814 +SYSZ_INS_CGDR = 815 +SYSZ_INS_CGDTR = 816 +SYSZ_INS_CGDTRA = 817 +SYSZ_INS_CGEBRA = 818 +SYSZ_INS_CGER = 819 +SYSZ_INS_CGIB = 820 +SYSZ_INS_CGIBE = 821 +SYSZ_INS_CGIBH = 822 +SYSZ_INS_CGIBHE = 823 +SYSZ_INS_CGIBL = 824 +SYSZ_INS_CGIBLE = 825 +SYSZ_INS_CGIBLH = 826 +SYSZ_INS_CGIBNE = 827 +SYSZ_INS_CGIBNH = 828 +SYSZ_INS_CGIBNHE = 829 +SYSZ_INS_CGIBNL = 830 +SYSZ_INS_CGIBNLE = 831 +SYSZ_INS_CGIBNLH = 832 +SYSZ_INS_CGIT = 833 +SYSZ_INS_CGITE = 834 +SYSZ_INS_CGITH = 835 +SYSZ_INS_CGITHE = 836 +SYSZ_INS_CGITL = 837 +SYSZ_INS_CGITLE = 838 +SYSZ_INS_CGITLH = 839 +SYSZ_INS_CGITNE = 840 +SYSZ_INS_CGITNH = 841 +SYSZ_INS_CGITNHE = 842 +SYSZ_INS_CGITNL = 843 +SYSZ_INS_CGITNLE = 844 +SYSZ_INS_CGITNLH = 845 +SYSZ_INS_CGRB = 846 +SYSZ_INS_CGRBE = 847 +SYSZ_INS_CGRBH = 848 +SYSZ_INS_CGRBHE = 849 +SYSZ_INS_CGRBL = 850 +SYSZ_INS_CGRBLE = 851 +SYSZ_INS_CGRBLH = 852 +SYSZ_INS_CGRBNE = 853 +SYSZ_INS_CGRBNH = 854 +SYSZ_INS_CGRBNHE = 855 +SYSZ_INS_CGRBNL = 856 +SYSZ_INS_CGRBNLE = 857 +SYSZ_INS_CGRBNLH = 858 +SYSZ_INS_CGRT = 859 +SYSZ_INS_CGRTE = 860 +SYSZ_INS_CGRTH = 861 +SYSZ_INS_CGRTHE = 862 +SYSZ_INS_CGRTL = 863 +SYSZ_INS_CGRTLE = 864 +SYSZ_INS_CGRTLH = 865 +SYSZ_INS_CGRTNE = 866 +SYSZ_INS_CGRTNH = 867 +SYSZ_INS_CGRTNHE = 868 +SYSZ_INS_CGRTNL = 869 +SYSZ_INS_CGRTNLE = 870 +SYSZ_INS_CGRTNLH = 871 +SYSZ_INS_CGXBRA = 872 +SYSZ_INS_CGXR = 873 +SYSZ_INS_CGXTR = 874 +SYSZ_INS_CGXTRA = 875 +SYSZ_INS_CHHR = 876 +SYSZ_INS_CHLR = 877 +SYSZ_INS_CIB = 878 +SYSZ_INS_CIBE = 879 +SYSZ_INS_CIBH = 880 +SYSZ_INS_CIBHE = 881 +SYSZ_INS_CIBL = 882 +SYSZ_INS_CIBLE = 883 +SYSZ_INS_CIBLH = 884 +SYSZ_INS_CIBNE = 885 +SYSZ_INS_CIBNH = 886 +SYSZ_INS_CIBNHE = 887 +SYSZ_INS_CIBNL = 888 +SYSZ_INS_CIBNLE = 889 +SYSZ_INS_CIBNLH = 890 +SYSZ_INS_CIT = 891 +SYSZ_INS_CITE = 892 +SYSZ_INS_CITH = 893 +SYSZ_INS_CITHE = 894 +SYSZ_INS_CITL = 895 +SYSZ_INS_CITLE = 896 +SYSZ_INS_CITLH = 897 +SYSZ_INS_CITNE = 898 +SYSZ_INS_CITNH = 899 +SYSZ_INS_CITNHE = 900 +SYSZ_INS_CITNL = 901 +SYSZ_INS_CITNLE = 902 +SYSZ_INS_CITNLH = 903 +SYSZ_INS_CKSM = 904 +SYSZ_INS_CLCL = 905 +SYSZ_INS_CLCLE = 906 +SYSZ_INS_CLCLU = 907 +SYSZ_INS_CLFDTR = 908 +SYSZ_INS_CLFIT = 909 +SYSZ_INS_CLFITE = 910 +SYSZ_INS_CLFITH = 911 +SYSZ_INS_CLFITHE = 912 +SYSZ_INS_CLFITL = 913 +SYSZ_INS_CLFITLE = 914 +SYSZ_INS_CLFITLH = 915 +SYSZ_INS_CLFITNE = 916 +SYSZ_INS_CLFITNH = 917 +SYSZ_INS_CLFITNHE = 918 +SYSZ_INS_CLFITNL = 919 +SYSZ_INS_CLFITNLE = 920 +SYSZ_INS_CLFITNLH = 921 +SYSZ_INS_CLFXTR = 922 +SYSZ_INS_CLGDTR = 923 +SYSZ_INS_CLGIB = 924 +SYSZ_INS_CLGIBE = 925 +SYSZ_INS_CLGIBH = 926 +SYSZ_INS_CLGIBHE = 927 +SYSZ_INS_CLGIBL = 928 +SYSZ_INS_CLGIBLE = 929 +SYSZ_INS_CLGIBLH = 930 +SYSZ_INS_CLGIBNE = 931 +SYSZ_INS_CLGIBNH = 932 +SYSZ_INS_CLGIBNHE = 933 +SYSZ_INS_CLGIBNL = 934 +SYSZ_INS_CLGIBNLE = 935 +SYSZ_INS_CLGIBNLH = 936 +SYSZ_INS_CLGIT = 937 +SYSZ_INS_CLGITE = 938 +SYSZ_INS_CLGITH = 939 +SYSZ_INS_CLGITHE = 940 +SYSZ_INS_CLGITL = 941 +SYSZ_INS_CLGITLE = 942 +SYSZ_INS_CLGITLH = 943 +SYSZ_INS_CLGITNE = 944 +SYSZ_INS_CLGITNH = 945 +SYSZ_INS_CLGITNHE = 946 +SYSZ_INS_CLGITNL = 947 +SYSZ_INS_CLGITNLE = 948 +SYSZ_INS_CLGITNLH = 949 +SYSZ_INS_CLGRB = 950 +SYSZ_INS_CLGRBE = 951 +SYSZ_INS_CLGRBH = 952 +SYSZ_INS_CLGRBHE = 953 +SYSZ_INS_CLGRBL = 954 +SYSZ_INS_CLGRBLE = 955 +SYSZ_INS_CLGRBLH = 956 +SYSZ_INS_CLGRBNE = 957 +SYSZ_INS_CLGRBNH = 958 +SYSZ_INS_CLGRBNHE = 959 +SYSZ_INS_CLGRBNL = 960 +SYSZ_INS_CLGRBNLE = 961 +SYSZ_INS_CLGRBNLH = 962 +SYSZ_INS_CLGRT = 963 +SYSZ_INS_CLGRTE = 964 +SYSZ_INS_CLGRTH = 965 +SYSZ_INS_CLGRTHE = 966 +SYSZ_INS_CLGRTL = 967 +SYSZ_INS_CLGRTLE = 968 +SYSZ_INS_CLGRTLH = 969 +SYSZ_INS_CLGRTNE = 970 +SYSZ_INS_CLGRTNH = 971 +SYSZ_INS_CLGRTNHE = 972 +SYSZ_INS_CLGRTNL = 973 +SYSZ_INS_CLGRTNLE = 974 +SYSZ_INS_CLGRTNLH = 975 +SYSZ_INS_CLGT = 976 +SYSZ_INS_CLGTE = 977 +SYSZ_INS_CLGTH = 978 +SYSZ_INS_CLGTHE = 979 +SYSZ_INS_CLGTL = 980 +SYSZ_INS_CLGTLE = 981 +SYSZ_INS_CLGTLH = 982 +SYSZ_INS_CLGTNE = 983 +SYSZ_INS_CLGTNH = 984 +SYSZ_INS_CLGTNHE = 985 +SYSZ_INS_CLGTNL = 986 +SYSZ_INS_CLGTNLE = 987 +SYSZ_INS_CLGTNLH = 988 +SYSZ_INS_CLGXTR = 989 +SYSZ_INS_CLHHR = 990 +SYSZ_INS_CLHLR = 991 +SYSZ_INS_CLIB = 992 +SYSZ_INS_CLIBE = 993 +SYSZ_INS_CLIBH = 994 +SYSZ_INS_CLIBHE = 995 +SYSZ_INS_CLIBL = 996 +SYSZ_INS_CLIBLE = 997 +SYSZ_INS_CLIBLH = 998 +SYSZ_INS_CLIBNE = 999 +SYSZ_INS_CLIBNH = 1000 +SYSZ_INS_CLIBNHE = 1001 +SYSZ_INS_CLIBNL = 1002 +SYSZ_INS_CLIBNLE = 1003 +SYSZ_INS_CLIBNLH = 1004 +SYSZ_INS_CLM = 1005 +SYSZ_INS_CLMH = 1006 +SYSZ_INS_CLMY = 1007 +SYSZ_INS_CLRB = 1008 +SYSZ_INS_CLRBE = 1009 +SYSZ_INS_CLRBH = 1010 +SYSZ_INS_CLRBHE = 1011 +SYSZ_INS_CLRBL = 1012 +SYSZ_INS_CLRBLE = 1013 +SYSZ_INS_CLRBLH = 1014 +SYSZ_INS_CLRBNE = 1015 +SYSZ_INS_CLRBNH = 1016 +SYSZ_INS_CLRBNHE = 1017 +SYSZ_INS_CLRBNL = 1018 +SYSZ_INS_CLRBNLE = 1019 +SYSZ_INS_CLRBNLH = 1020 +SYSZ_INS_CLRT = 1021 +SYSZ_INS_CLRTE = 1022 +SYSZ_INS_CLRTH = 1023 +SYSZ_INS_CLRTHE = 1024 +SYSZ_INS_CLRTL = 1025 +SYSZ_INS_CLRTLE = 1026 +SYSZ_INS_CLRTLH = 1027 +SYSZ_INS_CLRTNE = 1028 +SYSZ_INS_CLRTNH = 1029 +SYSZ_INS_CLRTNHE = 1030 +SYSZ_INS_CLRTNL = 1031 +SYSZ_INS_CLRTNLE = 1032 +SYSZ_INS_CLRTNLH = 1033 +SYSZ_INS_CLT = 1034 +SYSZ_INS_CLTE = 1035 +SYSZ_INS_CLTH = 1036 +SYSZ_INS_CLTHE = 1037 +SYSZ_INS_CLTL = 1038 +SYSZ_INS_CLTLE = 1039 +SYSZ_INS_CLTLH = 1040 +SYSZ_INS_CLTNE = 1041 +SYSZ_INS_CLTNH = 1042 +SYSZ_INS_CLTNHE = 1043 +SYSZ_INS_CLTNL = 1044 +SYSZ_INS_CLTNLE = 1045 +SYSZ_INS_CLTNLH = 1046 +SYSZ_INS_CMPSC = 1047 +SYSZ_INS_CP = 1048 +SYSZ_INS_CPDT = 1049 +SYSZ_INS_CPXT = 1050 +SYSZ_INS_CPYA = 1051 +SYSZ_INS_CRB = 1052 +SYSZ_INS_CRBE = 1053 +SYSZ_INS_CRBH = 1054 +SYSZ_INS_CRBHE = 1055 +SYSZ_INS_CRBL = 1056 +SYSZ_INS_CRBLE = 1057 +SYSZ_INS_CRBLH = 1058 +SYSZ_INS_CRBNE = 1059 +SYSZ_INS_CRBNH = 1060 +SYSZ_INS_CRBNHE = 1061 +SYSZ_INS_CRBNL = 1062 +SYSZ_INS_CRBNLE = 1063 +SYSZ_INS_CRBNLH = 1064 +SYSZ_INS_CRDTE = 1065 +SYSZ_INS_CRT = 1066 +SYSZ_INS_CRTE = 1067 +SYSZ_INS_CRTH = 1068 +SYSZ_INS_CRTHE = 1069 +SYSZ_INS_CRTL = 1070 +SYSZ_INS_CRTLE = 1071 +SYSZ_INS_CRTLH = 1072 +SYSZ_INS_CRTNE = 1073 +SYSZ_INS_CRTNH = 1074 +SYSZ_INS_CRTNHE = 1075 +SYSZ_INS_CRTNL = 1076 +SYSZ_INS_CRTNLE = 1077 +SYSZ_INS_CRTNLH = 1078 +SYSZ_INS_CSCH = 1079 +SYSZ_INS_CSDTR = 1080 +SYSZ_INS_CSP = 1081 +SYSZ_INS_CSPG = 1082 +SYSZ_INS_CSST = 1083 +SYSZ_INS_CSXTR = 1084 +SYSZ_INS_CU12 = 1085 +SYSZ_INS_CU14 = 1086 +SYSZ_INS_CU21 = 1087 +SYSZ_INS_CU24 = 1088 +SYSZ_INS_CU41 = 1089 +SYSZ_INS_CU42 = 1090 +SYSZ_INS_CUDTR = 1091 +SYSZ_INS_CUSE = 1092 +SYSZ_INS_CUTFU = 1093 +SYSZ_INS_CUUTF = 1094 +SYSZ_INS_CUXTR = 1095 +SYSZ_INS_CVB = 1096 +SYSZ_INS_CVBG = 1097 +SYSZ_INS_CVBY = 1098 +SYSZ_INS_CVD = 1099 +SYSZ_INS_CVDG = 1100 +SYSZ_INS_CVDY = 1101 +SYSZ_INS_CXFBRA = 1102 +SYSZ_INS_CXFR = 1103 +SYSZ_INS_CXFTR = 1104 +SYSZ_INS_CXGBRA = 1105 +SYSZ_INS_CXGR = 1106 +SYSZ_INS_CXGTR = 1107 +SYSZ_INS_CXGTRA = 1108 +SYSZ_INS_CXLFTR = 1109 +SYSZ_INS_CXLGTR = 1110 +SYSZ_INS_CXPT = 1111 +SYSZ_INS_CXR = 1112 +SYSZ_INS_CXSTR = 1113 +SYSZ_INS_CXTR = 1114 +SYSZ_INS_CXUTR = 1115 +SYSZ_INS_CXZT = 1116 +SYSZ_INS_CZDT = 1117 +SYSZ_INS_CZXT = 1118 +SYSZ_INS_D = 1119 +SYSZ_INS_DD = 1120 +SYSZ_INS_DDR = 1121 +SYSZ_INS_DDTR = 1122 +SYSZ_INS_DDTRA = 1123 +SYSZ_INS_DE = 1124 +SYSZ_INS_DER = 1125 +SYSZ_INS_DIAG = 1126 +SYSZ_INS_DIDBR = 1127 +SYSZ_INS_DIEBR = 1128 +SYSZ_INS_DP = 1129 +SYSZ_INS_DR = 1130 +SYSZ_INS_DXR = 1131 +SYSZ_INS_DXTR = 1132 +SYSZ_INS_DXTRA = 1133 +SYSZ_INS_ECAG = 1134 +SYSZ_INS_ECCTR = 1135 +SYSZ_INS_ECPGA = 1136 +SYSZ_INS_ECTG = 1137 +SYSZ_INS_ED = 1138 +SYSZ_INS_EDMK = 1139 +SYSZ_INS_EEDTR = 1140 +SYSZ_INS_EEXTR = 1141 +SYSZ_INS_EFPC = 1142 +SYSZ_INS_EPAIR = 1143 +SYSZ_INS_EPAR = 1144 +SYSZ_INS_EPCTR = 1145 +SYSZ_INS_EPSW = 1146 +SYSZ_INS_EREG = 1147 +SYSZ_INS_EREGG = 1148 +SYSZ_INS_ESAIR = 1149 +SYSZ_INS_ESAR = 1150 +SYSZ_INS_ESDTR = 1151 +SYSZ_INS_ESEA = 1152 +SYSZ_INS_ESTA = 1153 +SYSZ_INS_ESXTR = 1154 +SYSZ_INS_ETND = 1155 +SYSZ_INS_EX = 1156 +SYSZ_INS_EXRL = 1157 +SYSZ_INS_FIDR = 1158 +SYSZ_INS_FIDTR = 1159 +SYSZ_INS_FIER = 1160 +SYSZ_INS_FIXR = 1161 +SYSZ_INS_FIXTR = 1162 +SYSZ_INS_HDR = 1163 +SYSZ_INS_HER = 1164 +SYSZ_INS_HSCH = 1165 +SYSZ_INS_IAC = 1166 +SYSZ_INS_ICM = 1167 +SYSZ_INS_ICMH = 1168 +SYSZ_INS_ICMY = 1169 +SYSZ_INS_IDTE = 1170 +SYSZ_INS_IEDTR = 1171 +SYSZ_INS_IEXTR = 1172 +SYSZ_INS_IPK = 1173 +SYSZ_INS_IPTE = 1174 +SYSZ_INS_IRBM = 1175 +SYSZ_INS_ISKE = 1176 +SYSZ_INS_IVSK = 1177 +SYSZ_INS_JGM = 1178 +SYSZ_INS_JGNM = 1179 +SYSZ_INS_JGNP = 1180 +SYSZ_INS_JGNZ = 1181 +SYSZ_INS_JGP = 1182 +SYSZ_INS_JGZ = 1183 +SYSZ_INS_JM = 1184 +SYSZ_INS_JNM = 1185 +SYSZ_INS_JNP = 1186 +SYSZ_INS_JNZ = 1187 +SYSZ_INS_JP = 1188 +SYSZ_INS_JZ = 1189 +SYSZ_INS_KDB = 1190 +SYSZ_INS_KDBR = 1191 +SYSZ_INS_KDTR = 1192 +SYSZ_INS_KEB = 1193 +SYSZ_INS_KEBR = 1194 +SYSZ_INS_KIMD = 1195 +SYSZ_INS_KLMD = 1196 +SYSZ_INS_KM = 1197 +SYSZ_INS_KMA = 1198 +SYSZ_INS_KMAC = 1199 +SYSZ_INS_KMC = 1200 +SYSZ_INS_KMCTR = 1201 +SYSZ_INS_KMF = 1202 +SYSZ_INS_KMO = 1203 +SYSZ_INS_KXBR = 1204 +SYSZ_INS_KXTR = 1205 +SYSZ_INS_LAE = 1206 +SYSZ_INS_LAEY = 1207 +SYSZ_INS_LAM = 1208 +SYSZ_INS_LAMY = 1209 +SYSZ_INS_LASP = 1210 +SYSZ_INS_LAT = 1211 +SYSZ_INS_LCBB = 1212 +SYSZ_INS_LCCTL = 1213 +SYSZ_INS_LCDFR = 1214 +SYSZ_INS_LCDR = 1215 +SYSZ_INS_LCER = 1216 +SYSZ_INS_LCTL = 1217 +SYSZ_INS_LCTLG = 1218 +SYSZ_INS_LCXR = 1219 +SYSZ_INS_LDE = 1220 +SYSZ_INS_LDER = 1221 +SYSZ_INS_LDETR = 1222 +SYSZ_INS_LDXR = 1223 +SYSZ_INS_LDXTR = 1224 +SYSZ_INS_LEDR = 1225 +SYSZ_INS_LEDTR = 1226 +SYSZ_INS_LEXR = 1227 +SYSZ_INS_LFAS = 1228 +SYSZ_INS_LFHAT = 1229 +SYSZ_INS_LFPC = 1230 +SYSZ_INS_LGAT = 1231 +SYSZ_INS_LGG = 1232 +SYSZ_INS_LGSC = 1233 +SYSZ_INS_LLGFAT = 1234 +SYSZ_INS_LLGFSG = 1235 +SYSZ_INS_LLGT = 1236 +SYSZ_INS_LLGTAT = 1237 +SYSZ_INS_LLGTR = 1238 +SYSZ_INS_LLZRGF = 1239 +SYSZ_INS_LM = 1240 +SYSZ_INS_LMD = 1241 +SYSZ_INS_LMH = 1242 +SYSZ_INS_LMY = 1243 +SYSZ_INS_LNDFR = 1244 +SYSZ_INS_LNDR = 1245 +SYSZ_INS_LNER = 1246 +SYSZ_INS_LNXR = 1247 +SYSZ_INS_LOCFH = 1248 +SYSZ_INS_LOCFHE = 1249 +SYSZ_INS_LOCFHH = 1250 +SYSZ_INS_LOCFHHE = 1251 +SYSZ_INS_LOCFHL = 1252 +SYSZ_INS_LOCFHLE = 1253 +SYSZ_INS_LOCFHLH = 1254 +SYSZ_INS_LOCFHM = 1255 +SYSZ_INS_LOCFHNE = 1256 +SYSZ_INS_LOCFHNH = 1257 +SYSZ_INS_LOCFHNHE = 1258 +SYSZ_INS_LOCFHNL = 1259 +SYSZ_INS_LOCFHNLE = 1260 +SYSZ_INS_LOCFHNLH = 1261 +SYSZ_INS_LOCFHNM = 1262 +SYSZ_INS_LOCFHNO = 1263 +SYSZ_INS_LOCFHNP = 1264 +SYSZ_INS_LOCFHNZ = 1265 +SYSZ_INS_LOCFHO = 1266 +SYSZ_INS_LOCFHP = 1267 +SYSZ_INS_LOCFHR = 1268 +SYSZ_INS_LOCFHRE = 1269 +SYSZ_INS_LOCFHRH = 1270 +SYSZ_INS_LOCFHRHE = 1271 +SYSZ_INS_LOCFHRL = 1272 +SYSZ_INS_LOCFHRLE = 1273 +SYSZ_INS_LOCFHRLH = 1274 +SYSZ_INS_LOCFHRM = 1275 +SYSZ_INS_LOCFHRNE = 1276 +SYSZ_INS_LOCFHRNH = 1277 +SYSZ_INS_LOCFHRNHE = 1278 +SYSZ_INS_LOCFHRNL = 1279 +SYSZ_INS_LOCFHRNLE = 1280 +SYSZ_INS_LOCFHRNLH = 1281 +SYSZ_INS_LOCFHRNM = 1282 +SYSZ_INS_LOCFHRNO = 1283 +SYSZ_INS_LOCFHRNP = 1284 +SYSZ_INS_LOCFHRNZ = 1285 +SYSZ_INS_LOCFHRO = 1286 +SYSZ_INS_LOCFHRP = 1287 +SYSZ_INS_LOCFHRZ = 1288 +SYSZ_INS_LOCFHZ = 1289 +SYSZ_INS_LOCGHI = 1290 +SYSZ_INS_LOCGHIE = 1291 +SYSZ_INS_LOCGHIH = 1292 +SYSZ_INS_LOCGHIHE = 1293 +SYSZ_INS_LOCGHIL = 1294 +SYSZ_INS_LOCGHILE = 1295 +SYSZ_INS_LOCGHILH = 1296 +SYSZ_INS_LOCGHIM = 1297 +SYSZ_INS_LOCGHINE = 1298 +SYSZ_INS_LOCGHINH = 1299 +SYSZ_INS_LOCGHINHE = 1300 +SYSZ_INS_LOCGHINL = 1301 +SYSZ_INS_LOCGHINLE = 1302 +SYSZ_INS_LOCGHINLH = 1303 +SYSZ_INS_LOCGHINM = 1304 +SYSZ_INS_LOCGHINO = 1305 +SYSZ_INS_LOCGHINP = 1306 +SYSZ_INS_LOCGHINZ = 1307 +SYSZ_INS_LOCGHIO = 1308 +SYSZ_INS_LOCGHIP = 1309 +SYSZ_INS_LOCGHIZ = 1310 +SYSZ_INS_LOCGM = 1311 +SYSZ_INS_LOCGNM = 1312 +SYSZ_INS_LOCGNP = 1313 +SYSZ_INS_LOCGNZ = 1314 +SYSZ_INS_LOCGP = 1315 +SYSZ_INS_LOCGRM = 1316 +SYSZ_INS_LOCGRNM = 1317 +SYSZ_INS_LOCGRNP = 1318 +SYSZ_INS_LOCGRNZ = 1319 +SYSZ_INS_LOCGRP = 1320 +SYSZ_INS_LOCGRZ = 1321 +SYSZ_INS_LOCGZ = 1322 +SYSZ_INS_LOCHHI = 1323 +SYSZ_INS_LOCHHIE = 1324 +SYSZ_INS_LOCHHIH = 1325 +SYSZ_INS_LOCHHIHE = 1326 +SYSZ_INS_LOCHHIL = 1327 +SYSZ_INS_LOCHHILE = 1328 +SYSZ_INS_LOCHHILH = 1329 +SYSZ_INS_LOCHHIM = 1330 +SYSZ_INS_LOCHHINE = 1331 +SYSZ_INS_LOCHHINH = 1332 +SYSZ_INS_LOCHHINHE = 1333 +SYSZ_INS_LOCHHINL = 1334 +SYSZ_INS_LOCHHINLE = 1335 +SYSZ_INS_LOCHHINLH = 1336 +SYSZ_INS_LOCHHINM = 1337 +SYSZ_INS_LOCHHINO = 1338 +SYSZ_INS_LOCHHINP = 1339 +SYSZ_INS_LOCHHINZ = 1340 +SYSZ_INS_LOCHHIO = 1341 +SYSZ_INS_LOCHHIP = 1342 +SYSZ_INS_LOCHHIZ = 1343 +SYSZ_INS_LOCHI = 1344 +SYSZ_INS_LOCHIE = 1345 +SYSZ_INS_LOCHIH = 1346 +SYSZ_INS_LOCHIHE = 1347 +SYSZ_INS_LOCHIL = 1348 +SYSZ_INS_LOCHILE = 1349 +SYSZ_INS_LOCHILH = 1350 +SYSZ_INS_LOCHIM = 1351 +SYSZ_INS_LOCHINE = 1352 +SYSZ_INS_LOCHINH = 1353 +SYSZ_INS_LOCHINHE = 1354 +SYSZ_INS_LOCHINL = 1355 +SYSZ_INS_LOCHINLE = 1356 +SYSZ_INS_LOCHINLH = 1357 +SYSZ_INS_LOCHINM = 1358 +SYSZ_INS_LOCHINO = 1359 +SYSZ_INS_LOCHINP = 1360 +SYSZ_INS_LOCHINZ = 1361 +SYSZ_INS_LOCHIO = 1362 +SYSZ_INS_LOCHIP = 1363 +SYSZ_INS_LOCHIZ = 1364 +SYSZ_INS_LOCM = 1365 +SYSZ_INS_LOCNM = 1366 +SYSZ_INS_LOCNP = 1367 +SYSZ_INS_LOCNZ = 1368 +SYSZ_INS_LOCP = 1369 +SYSZ_INS_LOCRM = 1370 +SYSZ_INS_LOCRNM = 1371 +SYSZ_INS_LOCRNP = 1372 +SYSZ_INS_LOCRNZ = 1373 +SYSZ_INS_LOCRP = 1374 +SYSZ_INS_LOCRZ = 1375 +SYSZ_INS_LOCZ = 1376 +SYSZ_INS_LPCTL = 1377 +SYSZ_INS_LPD = 1378 +SYSZ_INS_LPDFR = 1379 +SYSZ_INS_LPDG = 1380 +SYSZ_INS_LPDR = 1381 +SYSZ_INS_LPER = 1382 +SYSZ_INS_LPP = 1383 +SYSZ_INS_LPQ = 1384 +SYSZ_INS_LPSW = 1385 +SYSZ_INS_LPSWE = 1386 +SYSZ_INS_LPTEA = 1387 +SYSZ_INS_LPXR = 1388 +SYSZ_INS_LRA = 1389 +SYSZ_INS_LRAG = 1390 +SYSZ_INS_LRAY = 1391 +SYSZ_INS_LRDR = 1392 +SYSZ_INS_LRER = 1393 +SYSZ_INS_LRVH = 1394 +SYSZ_INS_LSCTL = 1395 +SYSZ_INS_LTDR = 1396 +SYSZ_INS_LTDTR = 1397 +SYSZ_INS_LTER = 1398 +SYSZ_INS_LTXR = 1399 +SYSZ_INS_LTXTR = 1400 +SYSZ_INS_LURA = 1401 +SYSZ_INS_LURAG = 1402 +SYSZ_INS_LXD = 1403 +SYSZ_INS_LXDR = 1404 +SYSZ_INS_LXDTR = 1405 +SYSZ_INS_LXE = 1406 +SYSZ_INS_LXER = 1407 +SYSZ_INS_LZRF = 1408 +SYSZ_INS_LZRG = 1409 +SYSZ_INS_M = 1410 +SYSZ_INS_MAD = 1411 +SYSZ_INS_MADR = 1412 +SYSZ_INS_MAE = 1413 +SYSZ_INS_MAER = 1414 +SYSZ_INS_MAY = 1415 +SYSZ_INS_MAYH = 1416 +SYSZ_INS_MAYHR = 1417 +SYSZ_INS_MAYL = 1418 +SYSZ_INS_MAYLR = 1419 +SYSZ_INS_MAYR = 1420 +SYSZ_INS_MC = 1421 +SYSZ_INS_MD = 1422 +SYSZ_INS_MDE = 1423 +SYSZ_INS_MDER = 1424 +SYSZ_INS_MDR = 1425 +SYSZ_INS_MDTR = 1426 +SYSZ_INS_MDTRA = 1427 +SYSZ_INS_ME = 1428 +SYSZ_INS_MEE = 1429 +SYSZ_INS_MEER = 1430 +SYSZ_INS_MER = 1431 +SYSZ_INS_MFY = 1432 +SYSZ_INS_MG = 1433 +SYSZ_INS_MGH = 1434 +SYSZ_INS_MGRK = 1435 +SYSZ_INS_ML = 1436 +SYSZ_INS_MLR = 1437 +SYSZ_INS_MP = 1438 +SYSZ_INS_MR = 1439 +SYSZ_INS_MSC = 1440 +SYSZ_INS_MSCH = 1441 +SYSZ_INS_MSD = 1442 +SYSZ_INS_MSDR = 1443 +SYSZ_INS_MSE = 1444 +SYSZ_INS_MSER = 1445 +SYSZ_INS_MSGC = 1446 +SYSZ_INS_MSGRKC = 1447 +SYSZ_INS_MSRKC = 1448 +SYSZ_INS_MSTA = 1449 +SYSZ_INS_MVCDK = 1450 +SYSZ_INS_MVCIN = 1451 +SYSZ_INS_MVCK = 1452 +SYSZ_INS_MVCL = 1453 +SYSZ_INS_MVCLE = 1454 +SYSZ_INS_MVCLU = 1455 +SYSZ_INS_MVCOS = 1456 +SYSZ_INS_MVCP = 1457 +SYSZ_INS_MVCS = 1458 +SYSZ_INS_MVCSK = 1459 +SYSZ_INS_MVN = 1460 +SYSZ_INS_MVO = 1461 +SYSZ_INS_MVPG = 1462 +SYSZ_INS_MVZ = 1463 +SYSZ_INS_MXD = 1464 +SYSZ_INS_MXDR = 1465 +SYSZ_INS_MXR = 1466 +SYSZ_INS_MXTR = 1467 +SYSZ_INS_MXTRA = 1468 +SYSZ_INS_MY = 1469 +SYSZ_INS_MYH = 1470 +SYSZ_INS_MYHR = 1471 +SYSZ_INS_MYL = 1472 +SYSZ_INS_MYLR = 1473 +SYSZ_INS_MYR = 1474 +SYSZ_INS_NIAI = 1475 +SYSZ_INS_NTSTG = 1476 +SYSZ_INS_PACK = 1477 +SYSZ_INS_PALB = 1478 +SYSZ_INS_PC = 1479 +SYSZ_INS_PCC = 1480 +SYSZ_INS_PCKMO = 1481 +SYSZ_INS_PFMF = 1482 +SYSZ_INS_PFPO = 1483 +SYSZ_INS_PGIN = 1484 +SYSZ_INS_PGOUT = 1485 +SYSZ_INS_PKA = 1486 +SYSZ_INS_PKU = 1487 +SYSZ_INS_PLO = 1488 +SYSZ_INS_POPCNT = 1489 +SYSZ_INS_PPA = 1490 +SYSZ_INS_PPNO = 1491 +SYSZ_INS_PR = 1492 +SYSZ_INS_PRNO = 1493 +SYSZ_INS_PT = 1494 +SYSZ_INS_PTF = 1495 +SYSZ_INS_PTFF = 1496 +SYSZ_INS_PTI = 1497 +SYSZ_INS_PTLB = 1498 +SYSZ_INS_QADTR = 1499 +SYSZ_INS_QAXTR = 1500 +SYSZ_INS_QCTRI = 1501 +SYSZ_INS_QSI = 1502 +SYSZ_INS_RCHP = 1503 +SYSZ_INS_RISBGN = 1504 +SYSZ_INS_RP = 1505 +SYSZ_INS_RRBE = 1506 +SYSZ_INS_RRBM = 1507 +SYSZ_INS_RRDTR = 1508 +SYSZ_INS_RRXTR = 1509 +SYSZ_INS_RSCH = 1510 +SYSZ_INS_SAC = 1511 +SYSZ_INS_SACF = 1512 +SYSZ_INS_SAL = 1513 +SYSZ_INS_SAM24 = 1514 +SYSZ_INS_SAM31 = 1515 +SYSZ_INS_SAM64 = 1516 +SYSZ_INS_SAR = 1517 +SYSZ_INS_SCCTR = 1518 +SYSZ_INS_SCHM = 1519 +SYSZ_INS_SCK = 1520 +SYSZ_INS_SCKC = 1521 +SYSZ_INS_SCKPF = 1522 +SYSZ_INS_SD = 1523 +SYSZ_INS_SDR = 1524 +SYSZ_INS_SDTR = 1525 +SYSZ_INS_SDTRA = 1526 +SYSZ_INS_SE = 1527 +SYSZ_INS_SER = 1528 +SYSZ_INS_SFASR = 1529 +SYSZ_INS_SFPC = 1530 +SYSZ_INS_SGH = 1531 +SYSZ_INS_SHHHR = 1532 +SYSZ_INS_SHHLR = 1533 +SYSZ_INS_SIE = 1534 +SYSZ_INS_SIGA = 1535 +SYSZ_INS_SIGP = 1536 +SYSZ_INS_SLA = 1537 +SYSZ_INS_SLAG = 1538 +SYSZ_INS_SLAK = 1539 +SYSZ_INS_SLDA = 1540 +SYSZ_INS_SLDL = 1541 +SYSZ_INS_SLDT = 1542 +SYSZ_INS_SLHHHR = 1543 +SYSZ_INS_SLHHLR = 1544 +SYSZ_INS_SLXT = 1545 +SYSZ_INS_SP = 1546 +SYSZ_INS_SPCTR = 1547 +SYSZ_INS_SPKA = 1548 +SYSZ_INS_SPM = 1549 +SYSZ_INS_SPT = 1550 +SYSZ_INS_SPX = 1551 +SYSZ_INS_SQD = 1552 +SYSZ_INS_SQDR = 1553 +SYSZ_INS_SQE = 1554 +SYSZ_INS_SQER = 1555 +SYSZ_INS_SQXR = 1556 +SYSZ_INS_SRDA = 1557 +SYSZ_INS_SRDL = 1558 +SYSZ_INS_SRDT = 1559 +SYSZ_INS_SRNM = 1560 +SYSZ_INS_SRNMB = 1561 +SYSZ_INS_SRNMT = 1562 +SYSZ_INS_SRP = 1563 +SYSZ_INS_SRSTU = 1564 +SYSZ_INS_SRXT = 1565 +SYSZ_INS_SSAIR = 1566 +SYSZ_INS_SSAR = 1567 +SYSZ_INS_SSCH = 1568 +SYSZ_INS_SSKE = 1569 +SYSZ_INS_SSM = 1570 +SYSZ_INS_STAM = 1571 +SYSZ_INS_STAMY = 1572 +SYSZ_INS_STAP = 1573 +SYSZ_INS_STCK = 1574 +SYSZ_INS_STCKC = 1575 +SYSZ_INS_STCKE = 1576 +SYSZ_INS_STCKF = 1577 +SYSZ_INS_STCM = 1578 +SYSZ_INS_STCMH = 1579 +SYSZ_INS_STCMY = 1580 +SYSZ_INS_STCPS = 1581 +SYSZ_INS_STCRW = 1582 +SYSZ_INS_STCTG = 1583 +SYSZ_INS_STCTL = 1584 +SYSZ_INS_STFL = 1585 +SYSZ_INS_STFLE = 1586 +SYSZ_INS_STFPC = 1587 +SYSZ_INS_STGSC = 1588 +SYSZ_INS_STIDP = 1589 +SYSZ_INS_STM = 1590 +SYSZ_INS_STMH = 1591 +SYSZ_INS_STMY = 1592 +SYSZ_INS_STNSM = 1593 +SYSZ_INS_STOCFH = 1594 +SYSZ_INS_STOCFHE = 1595 +SYSZ_INS_STOCFHH = 1596 +SYSZ_INS_STOCFHHE = 1597 +SYSZ_INS_STOCFHL = 1598 +SYSZ_INS_STOCFHLE = 1599 +SYSZ_INS_STOCFHLH = 1600 +SYSZ_INS_STOCFHM = 1601 +SYSZ_INS_STOCFHNE = 1602 +SYSZ_INS_STOCFHNH = 1603 +SYSZ_INS_STOCFHNHE = 1604 +SYSZ_INS_STOCFHNL = 1605 +SYSZ_INS_STOCFHNLE = 1606 +SYSZ_INS_STOCFHNLH = 1607 +SYSZ_INS_STOCFHNM = 1608 +SYSZ_INS_STOCFHNO = 1609 +SYSZ_INS_STOCFHNP = 1610 +SYSZ_INS_STOCFHNZ = 1611 +SYSZ_INS_STOCFHO = 1612 +SYSZ_INS_STOCFHP = 1613 +SYSZ_INS_STOCFHZ = 1614 +SYSZ_INS_STOCGM = 1615 +SYSZ_INS_STOCGNM = 1616 +SYSZ_INS_STOCGNP = 1617 +SYSZ_INS_STOCGNZ = 1618 +SYSZ_INS_STOCGP = 1619 +SYSZ_INS_STOCGZ = 1620 +SYSZ_INS_STOCM = 1621 +SYSZ_INS_STOCNM = 1622 +SYSZ_INS_STOCNP = 1623 +SYSZ_INS_STOCNZ = 1624 +SYSZ_INS_STOCP = 1625 +SYSZ_INS_STOCZ = 1626 +SYSZ_INS_STOSM = 1627 +SYSZ_INS_STPQ = 1628 +SYSZ_INS_STPT = 1629 +SYSZ_INS_STPX = 1630 +SYSZ_INS_STRAG = 1631 +SYSZ_INS_STRVH = 1632 +SYSZ_INS_STSCH = 1633 +SYSZ_INS_STSI = 1634 +SYSZ_INS_STURA = 1635 +SYSZ_INS_STURG = 1636 +SYSZ_INS_SU = 1637 +SYSZ_INS_SUR = 1638 +SYSZ_INS_SVC = 1639 +SYSZ_INS_SW = 1640 +SYSZ_INS_SWR = 1641 +SYSZ_INS_SXR = 1642 +SYSZ_INS_SXTR = 1643 +SYSZ_INS_SXTRA = 1644 +SYSZ_INS_TABORT = 1645 +SYSZ_INS_TAM = 1646 +SYSZ_INS_TAR = 1647 +SYSZ_INS_TB = 1648 +SYSZ_INS_TBDR = 1649 +SYSZ_INS_TBEDR = 1650 +SYSZ_INS_TBEGIN = 1651 +SYSZ_INS_TBEGINC = 1652 +SYSZ_INS_TCDB = 1653 +SYSZ_INS_TCEB = 1654 +SYSZ_INS_TCXB = 1655 +SYSZ_INS_TDCDT = 1656 +SYSZ_INS_TDCET = 1657 +SYSZ_INS_TDCXT = 1658 +SYSZ_INS_TDGDT = 1659 +SYSZ_INS_TDGET = 1660 +SYSZ_INS_TDGXT = 1661 +SYSZ_INS_TEND = 1662 +SYSZ_INS_THDER = 1663 +SYSZ_INS_THDR = 1664 +SYSZ_INS_TP = 1665 +SYSZ_INS_TPI = 1666 +SYSZ_INS_TPROT = 1667 +SYSZ_INS_TR = 1668 +SYSZ_INS_TRACE = 1669 +SYSZ_INS_TRACG = 1670 +SYSZ_INS_TRAP2 = 1671 +SYSZ_INS_TRAP4 = 1672 +SYSZ_INS_TRE = 1673 +SYSZ_INS_TROO = 1674 +SYSZ_INS_TROT = 1675 +SYSZ_INS_TRT = 1676 +SYSZ_INS_TRTE = 1677 +SYSZ_INS_TRTO = 1678 +SYSZ_INS_TRTR = 1679 +SYSZ_INS_TRTRE = 1680 +SYSZ_INS_TRTT = 1681 +SYSZ_INS_TS = 1682 +SYSZ_INS_TSCH = 1683 +SYSZ_INS_UNPK = 1684 +SYSZ_INS_UNPKA = 1685 +SYSZ_INS_UNPKU = 1686 +SYSZ_INS_UPT = 1687 +SYSZ_INS_VA = 1688 +SYSZ_INS_VAB = 1689 +SYSZ_INS_VAC = 1690 +SYSZ_INS_VACC = 1691 +SYSZ_INS_VACCB = 1692 +SYSZ_INS_VACCC = 1693 +SYSZ_INS_VACCCQ = 1694 +SYSZ_INS_VACCF = 1695 +SYSZ_INS_VACCG = 1696 +SYSZ_INS_VACCH = 1697 +SYSZ_INS_VACCQ = 1698 +SYSZ_INS_VACQ = 1699 +SYSZ_INS_VAF = 1700 +SYSZ_INS_VAG = 1701 +SYSZ_INS_VAH = 1702 +SYSZ_INS_VAP = 1703 +SYSZ_INS_VAQ = 1704 +SYSZ_INS_VAVG = 1705 +SYSZ_INS_VAVGB = 1706 +SYSZ_INS_VAVGF = 1707 +SYSZ_INS_VAVGG = 1708 +SYSZ_INS_VAVGH = 1709 +SYSZ_INS_VAVGL = 1710 +SYSZ_INS_VAVGLB = 1711 +SYSZ_INS_VAVGLF = 1712 +SYSZ_INS_VAVGLG = 1713 +SYSZ_INS_VAVGLH = 1714 +SYSZ_INS_VBPERM = 1715 +SYSZ_INS_VCDG = 1716 +SYSZ_INS_VCDGB = 1717 +SYSZ_INS_VCDLG = 1718 +SYSZ_INS_VCDLGB = 1719 +SYSZ_INS_VCEQ = 1720 +SYSZ_INS_VCEQB = 1721 +SYSZ_INS_VCEQBS = 1722 +SYSZ_INS_VCEQF = 1723 +SYSZ_INS_VCEQFS = 1724 +SYSZ_INS_VCEQG = 1725 +SYSZ_INS_VCEQGS = 1726 +SYSZ_INS_VCEQH = 1727 +SYSZ_INS_VCEQHS = 1728 +SYSZ_INS_VCGD = 1729 +SYSZ_INS_VCGDB = 1730 +SYSZ_INS_VCH = 1731 +SYSZ_INS_VCHB = 1732 +SYSZ_INS_VCHBS = 1733 +SYSZ_INS_VCHF = 1734 +SYSZ_INS_VCHFS = 1735 +SYSZ_INS_VCHG = 1736 +SYSZ_INS_VCHGS = 1737 +SYSZ_INS_VCHH = 1738 +SYSZ_INS_VCHHS = 1739 +SYSZ_INS_VCHL = 1740 +SYSZ_INS_VCHLB = 1741 +SYSZ_INS_VCHLBS = 1742 +SYSZ_INS_VCHLF = 1743 +SYSZ_INS_VCHLFS = 1744 +SYSZ_INS_VCHLG = 1745 +SYSZ_INS_VCHLGS = 1746 +SYSZ_INS_VCHLH = 1747 +SYSZ_INS_VCHLHS = 1748 +SYSZ_INS_VCKSM = 1749 +SYSZ_INS_VCLGD = 1750 +SYSZ_INS_VCLGDB = 1751 +SYSZ_INS_VCLZ = 1752 +SYSZ_INS_VCLZB = 1753 +SYSZ_INS_VCLZF = 1754 +SYSZ_INS_VCLZG = 1755 +SYSZ_INS_VCLZH = 1756 +SYSZ_INS_VCP = 1757 +SYSZ_INS_VCTZ = 1758 +SYSZ_INS_VCTZB = 1759 +SYSZ_INS_VCTZF = 1760 +SYSZ_INS_VCTZG = 1761 +SYSZ_INS_VCTZH = 1762 +SYSZ_INS_VCVB = 1763 +SYSZ_INS_VCVBG = 1764 +SYSZ_INS_VCVD = 1765 +SYSZ_INS_VCVDG = 1766 +SYSZ_INS_VDP = 1767 +SYSZ_INS_VEC = 1768 +SYSZ_INS_VECB = 1769 +SYSZ_INS_VECF = 1770 +SYSZ_INS_VECG = 1771 +SYSZ_INS_VECH = 1772 +SYSZ_INS_VECL = 1773 +SYSZ_INS_VECLB = 1774 +SYSZ_INS_VECLF = 1775 +SYSZ_INS_VECLG = 1776 +SYSZ_INS_VECLH = 1777 +SYSZ_INS_VERIM = 1778 +SYSZ_INS_VERIMB = 1779 +SYSZ_INS_VERIMF = 1780 +SYSZ_INS_VERIMG = 1781 +SYSZ_INS_VERIMH = 1782 +SYSZ_INS_VERLL = 1783 +SYSZ_INS_VERLLB = 1784 +SYSZ_INS_VERLLF = 1785 +SYSZ_INS_VERLLG = 1786 +SYSZ_INS_VERLLH = 1787 +SYSZ_INS_VERLLV = 1788 +SYSZ_INS_VERLLVB = 1789 +SYSZ_INS_VERLLVF = 1790 +SYSZ_INS_VERLLVG = 1791 +SYSZ_INS_VERLLVH = 1792 +SYSZ_INS_VESL = 1793 +SYSZ_INS_VESLB = 1794 +SYSZ_INS_VESLF = 1795 +SYSZ_INS_VESLG = 1796 +SYSZ_INS_VESLH = 1797 +SYSZ_INS_VESLV = 1798 +SYSZ_INS_VESLVB = 1799 +SYSZ_INS_VESLVF = 1800 +SYSZ_INS_VESLVG = 1801 +SYSZ_INS_VESLVH = 1802 +SYSZ_INS_VESRA = 1803 +SYSZ_INS_VESRAB = 1804 +SYSZ_INS_VESRAF = 1805 +SYSZ_INS_VESRAG = 1806 +SYSZ_INS_VESRAH = 1807 +SYSZ_INS_VESRAV = 1808 +SYSZ_INS_VESRAVB = 1809 +SYSZ_INS_VESRAVF = 1810 +SYSZ_INS_VESRAVG = 1811 +SYSZ_INS_VESRAVH = 1812 +SYSZ_INS_VESRL = 1813 +SYSZ_INS_VESRLB = 1814 +SYSZ_INS_VESRLF = 1815 +SYSZ_INS_VESRLG = 1816 +SYSZ_INS_VESRLH = 1817 +SYSZ_INS_VESRLV = 1818 +SYSZ_INS_VESRLVB = 1819 +SYSZ_INS_VESRLVF = 1820 +SYSZ_INS_VESRLVG = 1821 +SYSZ_INS_VESRLVH = 1822 +SYSZ_INS_VFA = 1823 +SYSZ_INS_VFADB = 1824 +SYSZ_INS_VFAE = 1825 +SYSZ_INS_VFAEB = 1826 +SYSZ_INS_VFAEBS = 1827 +SYSZ_INS_VFAEF = 1828 +SYSZ_INS_VFAEFS = 1829 +SYSZ_INS_VFAEH = 1830 +SYSZ_INS_VFAEHS = 1831 +SYSZ_INS_VFAEZB = 1832 +SYSZ_INS_VFAEZBS = 1833 +SYSZ_INS_VFAEZF = 1834 +SYSZ_INS_VFAEZFS = 1835 +SYSZ_INS_VFAEZH = 1836 +SYSZ_INS_VFAEZHS = 1837 +SYSZ_INS_VFASB = 1838 +SYSZ_INS_VFCE = 1839 +SYSZ_INS_VFCEDB = 1840 +SYSZ_INS_VFCEDBS = 1841 +SYSZ_INS_VFCESB = 1842 +SYSZ_INS_VFCESBS = 1843 +SYSZ_INS_VFCH = 1844 +SYSZ_INS_VFCHDB = 1845 +SYSZ_INS_VFCHDBS = 1846 +SYSZ_INS_VFCHE = 1847 +SYSZ_INS_VFCHEDB = 1848 +SYSZ_INS_VFCHEDBS = 1849 +SYSZ_INS_VFCHESB = 1850 +SYSZ_INS_VFCHESBS = 1851 +SYSZ_INS_VFCHSB = 1852 +SYSZ_INS_VFCHSBS = 1853 +SYSZ_INS_VFD = 1854 +SYSZ_INS_VFDDB = 1855 +SYSZ_INS_VFDSB = 1856 +SYSZ_INS_VFEE = 1857 +SYSZ_INS_VFEEB = 1858 +SYSZ_INS_VFEEBS = 1859 +SYSZ_INS_VFEEF = 1860 +SYSZ_INS_VFEEFS = 1861 +SYSZ_INS_VFEEH = 1862 +SYSZ_INS_VFEEHS = 1863 +SYSZ_INS_VFEEZB = 1864 +SYSZ_INS_VFEEZBS = 1865 +SYSZ_INS_VFEEZF = 1866 +SYSZ_INS_VFEEZFS = 1867 +SYSZ_INS_VFEEZH = 1868 +SYSZ_INS_VFEEZHS = 1869 +SYSZ_INS_VFENE = 1870 +SYSZ_INS_VFENEB = 1871 +SYSZ_INS_VFENEBS = 1872 +SYSZ_INS_VFENEF = 1873 +SYSZ_INS_VFENEFS = 1874 +SYSZ_INS_VFENEH = 1875 +SYSZ_INS_VFENEHS = 1876 +SYSZ_INS_VFENEZB = 1877 +SYSZ_INS_VFENEZBS = 1878 +SYSZ_INS_VFENEZF = 1879 +SYSZ_INS_VFENEZFS = 1880 +SYSZ_INS_VFENEZH = 1881 +SYSZ_INS_VFENEZHS = 1882 +SYSZ_INS_VFI = 1883 +SYSZ_INS_VFIDB = 1884 +SYSZ_INS_VFISB = 1885 +SYSZ_INS_VFKEDB = 1886 +SYSZ_INS_VFKEDBS = 1887 +SYSZ_INS_VFKESB = 1888 +SYSZ_INS_VFKESBS = 1889 +SYSZ_INS_VFKHDB = 1890 +SYSZ_INS_VFKHDBS = 1891 +SYSZ_INS_VFKHEDB = 1892 +SYSZ_INS_VFKHEDBS = 1893 +SYSZ_INS_VFKHESB = 1894 +SYSZ_INS_VFKHESBS = 1895 +SYSZ_INS_VFKHSB = 1896 +SYSZ_INS_VFKHSBS = 1897 +SYSZ_INS_VFLCDB = 1898 +SYSZ_INS_VFLCSB = 1899 +SYSZ_INS_VFLL = 1900 +SYSZ_INS_VFLLS = 1901 +SYSZ_INS_VFLNDB = 1902 +SYSZ_INS_VFLNSB = 1903 +SYSZ_INS_VFLPDB = 1904 +SYSZ_INS_VFLPSB = 1905 +SYSZ_INS_VFLR = 1906 +SYSZ_INS_VFLRD = 1907 +SYSZ_INS_VFM = 1908 +SYSZ_INS_VFMA = 1909 +SYSZ_INS_VFMADB = 1910 +SYSZ_INS_VFMASB = 1911 +SYSZ_INS_VFMAX = 1912 +SYSZ_INS_VFMAXDB = 1913 +SYSZ_INS_VFMAXSB = 1914 +SYSZ_INS_VFMDB = 1915 +SYSZ_INS_VFMIN = 1916 +SYSZ_INS_VFMINDB = 1917 +SYSZ_INS_VFMINSB = 1918 +SYSZ_INS_VFMS = 1919 +SYSZ_INS_VFMSB = 1920 +SYSZ_INS_VFMSDB = 1921 +SYSZ_INS_VFMSSB = 1922 +SYSZ_INS_VFNMA = 1923 +SYSZ_INS_VFNMADB = 1924 +SYSZ_INS_VFNMASB = 1925 +SYSZ_INS_VFNMS = 1926 +SYSZ_INS_VFNMSDB = 1927 +SYSZ_INS_VFNMSSB = 1928 +SYSZ_INS_VFPSO = 1929 +SYSZ_INS_VFPSODB = 1930 +SYSZ_INS_VFPSOSB = 1931 +SYSZ_INS_VFS = 1932 +SYSZ_INS_VFSDB = 1933 +SYSZ_INS_VFSQ = 1934 +SYSZ_INS_VFSQDB = 1935 +SYSZ_INS_VFSQSB = 1936 +SYSZ_INS_VFSSB = 1937 +SYSZ_INS_VFTCI = 1938 +SYSZ_INS_VFTCIDB = 1939 +SYSZ_INS_VFTCISB = 1940 +SYSZ_INS_VGBM = 1941 +SYSZ_INS_VGEF = 1942 +SYSZ_INS_VGEG = 1943 +SYSZ_INS_VGFM = 1944 +SYSZ_INS_VGFMA = 1945 +SYSZ_INS_VGFMAB = 1946 +SYSZ_INS_VGFMAF = 1947 +SYSZ_INS_VGFMAG = 1948 +SYSZ_INS_VGFMAH = 1949 +SYSZ_INS_VGFMB = 1950 +SYSZ_INS_VGFMF = 1951 +SYSZ_INS_VGFMG = 1952 +SYSZ_INS_VGFMH = 1953 +SYSZ_INS_VGM = 1954 +SYSZ_INS_VGMB = 1955 +SYSZ_INS_VGMF = 1956 +SYSZ_INS_VGMG = 1957 +SYSZ_INS_VGMH = 1958 +SYSZ_INS_VISTR = 1959 +SYSZ_INS_VISTRB = 1960 +SYSZ_INS_VISTRBS = 1961 +SYSZ_INS_VISTRF = 1962 +SYSZ_INS_VISTRFS = 1963 +SYSZ_INS_VISTRH = 1964 +SYSZ_INS_VISTRHS = 1965 +SYSZ_INS_VL = 1966 +SYSZ_INS_VLBB = 1967 +SYSZ_INS_VLC = 1968 +SYSZ_INS_VLCB = 1969 +SYSZ_INS_VLCF = 1970 +SYSZ_INS_VLCG = 1971 +SYSZ_INS_VLCH = 1972 +SYSZ_INS_VLDE = 1973 +SYSZ_INS_VLDEB = 1974 +SYSZ_INS_VLEB = 1975 +SYSZ_INS_VLED = 1976 +SYSZ_INS_VLEDB = 1977 +SYSZ_INS_VLEF = 1978 +SYSZ_INS_VLEG = 1979 +SYSZ_INS_VLEH = 1980 +SYSZ_INS_VLEIB = 1981 +SYSZ_INS_VLEIF = 1982 +SYSZ_INS_VLEIG = 1983 +SYSZ_INS_VLEIH = 1984 +SYSZ_INS_VLGV = 1985 +SYSZ_INS_VLGVB = 1986 +SYSZ_INS_VLGVF = 1987 +SYSZ_INS_VLGVG = 1988 +SYSZ_INS_VLGVH = 1989 +SYSZ_INS_VLIP = 1990 +SYSZ_INS_VLL = 1991 +SYSZ_INS_VLLEZ = 1992 +SYSZ_INS_VLLEZB = 1993 +SYSZ_INS_VLLEZF = 1994 +SYSZ_INS_VLLEZG = 1995 +SYSZ_INS_VLLEZH = 1996 +SYSZ_INS_VLLEZLF = 1997 +SYSZ_INS_VLM = 1998 +SYSZ_INS_VLP = 1999 +SYSZ_INS_VLPB = 2000 +SYSZ_INS_VLPF = 2001 +SYSZ_INS_VLPG = 2002 +SYSZ_INS_VLPH = 2003 +SYSZ_INS_VLR = 2004 +SYSZ_INS_VLREP = 2005 +SYSZ_INS_VLREPB = 2006 +SYSZ_INS_VLREPF = 2007 +SYSZ_INS_VLREPG = 2008 +SYSZ_INS_VLREPH = 2009 +SYSZ_INS_VLRL = 2010 +SYSZ_INS_VLRLR = 2011 +SYSZ_INS_VLVG = 2012 +SYSZ_INS_VLVGB = 2013 +SYSZ_INS_VLVGF = 2014 +SYSZ_INS_VLVGG = 2015 +SYSZ_INS_VLVGH = 2016 +SYSZ_INS_VLVGP = 2017 +SYSZ_INS_VMAE = 2018 +SYSZ_INS_VMAEB = 2019 +SYSZ_INS_VMAEF = 2020 +SYSZ_INS_VMAEH = 2021 +SYSZ_INS_VMAH = 2022 +SYSZ_INS_VMAHB = 2023 +SYSZ_INS_VMAHF = 2024 +SYSZ_INS_VMAHH = 2025 +SYSZ_INS_VMAL = 2026 +SYSZ_INS_VMALB = 2027 +SYSZ_INS_VMALE = 2028 +SYSZ_INS_VMALEB = 2029 +SYSZ_INS_VMALEF = 2030 +SYSZ_INS_VMALEH = 2031 +SYSZ_INS_VMALF = 2032 +SYSZ_INS_VMALH = 2033 +SYSZ_INS_VMALHB = 2034 +SYSZ_INS_VMALHF = 2035 +SYSZ_INS_VMALHH = 2036 +SYSZ_INS_VMALHW = 2037 +SYSZ_INS_VMALO = 2038 +SYSZ_INS_VMALOB = 2039 +SYSZ_INS_VMALOF = 2040 +SYSZ_INS_VMALOH = 2041 +SYSZ_INS_VMAO = 2042 +SYSZ_INS_VMAOB = 2043 +SYSZ_INS_VMAOF = 2044 +SYSZ_INS_VMAOH = 2045 +SYSZ_INS_VME = 2046 +SYSZ_INS_VMEB = 2047 +SYSZ_INS_VMEF = 2048 +SYSZ_INS_VMEH = 2049 +SYSZ_INS_VMH = 2050 +SYSZ_INS_VMHB = 2051 +SYSZ_INS_VMHF = 2052 +SYSZ_INS_VMHH = 2053 +SYSZ_INS_VML = 2054 +SYSZ_INS_VMLB = 2055 +SYSZ_INS_VMLE = 2056 +SYSZ_INS_VMLEB = 2057 +SYSZ_INS_VMLEF = 2058 +SYSZ_INS_VMLEH = 2059 +SYSZ_INS_VMLF = 2060 +SYSZ_INS_VMLH = 2061 +SYSZ_INS_VMLHB = 2062 +SYSZ_INS_VMLHF = 2063 +SYSZ_INS_VMLHH = 2064 +SYSZ_INS_VMLHW = 2065 +SYSZ_INS_VMLO = 2066 +SYSZ_INS_VMLOB = 2067 +SYSZ_INS_VMLOF = 2068 +SYSZ_INS_VMLOH = 2069 +SYSZ_INS_VMN = 2070 +SYSZ_INS_VMNB = 2071 +SYSZ_INS_VMNF = 2072 +SYSZ_INS_VMNG = 2073 +SYSZ_INS_VMNH = 2074 +SYSZ_INS_VMNL = 2075 +SYSZ_INS_VMNLB = 2076 +SYSZ_INS_VMNLF = 2077 +SYSZ_INS_VMNLG = 2078 +SYSZ_INS_VMNLH = 2079 +SYSZ_INS_VMO = 2080 +SYSZ_INS_VMOB = 2081 +SYSZ_INS_VMOF = 2082 +SYSZ_INS_VMOH = 2083 +SYSZ_INS_VMP = 2084 +SYSZ_INS_VMRH = 2085 +SYSZ_INS_VMRHB = 2086 +SYSZ_INS_VMRHF = 2087 +SYSZ_INS_VMRHG = 2088 +SYSZ_INS_VMRHH = 2089 +SYSZ_INS_VMRL = 2090 +SYSZ_INS_VMRLB = 2091 +SYSZ_INS_VMRLF = 2092 +SYSZ_INS_VMRLG = 2093 +SYSZ_INS_VMRLH = 2094 +SYSZ_INS_VMSL = 2095 +SYSZ_INS_VMSLG = 2096 +SYSZ_INS_VMSP = 2097 +SYSZ_INS_VMX = 2098 +SYSZ_INS_VMXB = 2099 +SYSZ_INS_VMXF = 2100 +SYSZ_INS_VMXG = 2101 +SYSZ_INS_VMXH = 2102 +SYSZ_INS_VMXL = 2103 +SYSZ_INS_VMXLB = 2104 +SYSZ_INS_VMXLF = 2105 +SYSZ_INS_VMXLG = 2106 +SYSZ_INS_VMXLH = 2107 +SYSZ_INS_VN = 2108 +SYSZ_INS_VNC = 2109 +SYSZ_INS_VNN = 2110 +SYSZ_INS_VNO = 2111 +SYSZ_INS_VNX = 2112 +SYSZ_INS_VO = 2113 +SYSZ_INS_VOC = 2114 +SYSZ_INS_VONE = 2115 +SYSZ_INS_VPDI = 2116 +SYSZ_INS_VPERM = 2117 +SYSZ_INS_VPK = 2118 +SYSZ_INS_VPKF = 2119 +SYSZ_INS_VPKG = 2120 +SYSZ_INS_VPKH = 2121 +SYSZ_INS_VPKLS = 2122 +SYSZ_INS_VPKLSF = 2123 +SYSZ_INS_VPKLSFS = 2124 +SYSZ_INS_VPKLSG = 2125 +SYSZ_INS_VPKLSGS = 2126 +SYSZ_INS_VPKLSH = 2127 +SYSZ_INS_VPKLSHS = 2128 +SYSZ_INS_VPKS = 2129 +SYSZ_INS_VPKSF = 2130 +SYSZ_INS_VPKSFS = 2131 +SYSZ_INS_VPKSG = 2132 +SYSZ_INS_VPKSGS = 2133 +SYSZ_INS_VPKSH = 2134 +SYSZ_INS_VPKSHS = 2135 +SYSZ_INS_VPKZ = 2136 +SYSZ_INS_VPOPCT = 2137 +SYSZ_INS_VPOPCTB = 2138 +SYSZ_INS_VPOPCTF = 2139 +SYSZ_INS_VPOPCTG = 2140 +SYSZ_INS_VPOPCTH = 2141 +SYSZ_INS_VPSOP = 2142 +SYSZ_INS_VREP = 2143 +SYSZ_INS_VREPB = 2144 +SYSZ_INS_VREPF = 2145 +SYSZ_INS_VREPG = 2146 +SYSZ_INS_VREPH = 2147 +SYSZ_INS_VREPI = 2148 +SYSZ_INS_VREPIB = 2149 +SYSZ_INS_VREPIF = 2150 +SYSZ_INS_VREPIG = 2151 +SYSZ_INS_VREPIH = 2152 +SYSZ_INS_VRP = 2153 +SYSZ_INS_VS = 2154 +SYSZ_INS_VSB = 2155 +SYSZ_INS_VSBCBI = 2156 +SYSZ_INS_VSBCBIQ = 2157 +SYSZ_INS_VSBI = 2158 +SYSZ_INS_VSBIQ = 2159 +SYSZ_INS_VSCBI = 2160 +SYSZ_INS_VSCBIB = 2161 +SYSZ_INS_VSCBIF = 2162 +SYSZ_INS_VSCBIG = 2163 +SYSZ_INS_VSCBIH = 2164 +SYSZ_INS_VSCBIQ = 2165 +SYSZ_INS_VSCEF = 2166 +SYSZ_INS_VSCEG = 2167 +SYSZ_INS_VSDP = 2168 +SYSZ_INS_VSEG = 2169 +SYSZ_INS_VSEGB = 2170 +SYSZ_INS_VSEGF = 2171 +SYSZ_INS_VSEGH = 2172 +SYSZ_INS_VSEL = 2173 +SYSZ_INS_VSF = 2174 +SYSZ_INS_VSG = 2175 +SYSZ_INS_VSH = 2176 +SYSZ_INS_VSL = 2177 +SYSZ_INS_VSLB = 2178 +SYSZ_INS_VSLDB = 2179 +SYSZ_INS_VSP = 2180 +SYSZ_INS_VSQ = 2181 +SYSZ_INS_VSRA = 2182 +SYSZ_INS_VSRAB = 2183 +SYSZ_INS_VSRL = 2184 +SYSZ_INS_VSRLB = 2185 +SYSZ_INS_VSRP = 2186 +SYSZ_INS_VST = 2187 +SYSZ_INS_VSTEB = 2188 +SYSZ_INS_VSTEF = 2189 +SYSZ_INS_VSTEG = 2190 +SYSZ_INS_VSTEH = 2191 +SYSZ_INS_VSTL = 2192 +SYSZ_INS_VSTM = 2193 +SYSZ_INS_VSTRC = 2194 +SYSZ_INS_VSTRCB = 2195 +SYSZ_INS_VSTRCBS = 2196 +SYSZ_INS_VSTRCF = 2197 +SYSZ_INS_VSTRCFS = 2198 +SYSZ_INS_VSTRCH = 2199 +SYSZ_INS_VSTRCHS = 2200 +SYSZ_INS_VSTRCZB = 2201 +SYSZ_INS_VSTRCZBS = 2202 +SYSZ_INS_VSTRCZF = 2203 +SYSZ_INS_VSTRCZFS = 2204 +SYSZ_INS_VSTRCZH = 2205 +SYSZ_INS_VSTRCZHS = 2206 +SYSZ_INS_VSTRL = 2207 +SYSZ_INS_VSTRLR = 2208 +SYSZ_INS_VSUM = 2209 +SYSZ_INS_VSUMB = 2210 +SYSZ_INS_VSUMG = 2211 +SYSZ_INS_VSUMGF = 2212 +SYSZ_INS_VSUMGH = 2213 +SYSZ_INS_VSUMH = 2214 +SYSZ_INS_VSUMQ = 2215 +SYSZ_INS_VSUMQF = 2216 +SYSZ_INS_VSUMQG = 2217 +SYSZ_INS_VTM = 2218 +SYSZ_INS_VTP = 2219 +SYSZ_INS_VUPH = 2220 +SYSZ_INS_VUPHB = 2221 +SYSZ_INS_VUPHF = 2222 +SYSZ_INS_VUPHH = 2223 +SYSZ_INS_VUPKZ = 2224 +SYSZ_INS_VUPL = 2225 +SYSZ_INS_VUPLB = 2226 +SYSZ_INS_VUPLF = 2227 +SYSZ_INS_VUPLH = 2228 +SYSZ_INS_VUPLHB = 2229 +SYSZ_INS_VUPLHF = 2230 +SYSZ_INS_VUPLHH = 2231 +SYSZ_INS_VUPLHW = 2232 +SYSZ_INS_VUPLL = 2233 +SYSZ_INS_VUPLLB = 2234 +SYSZ_INS_VUPLLF = 2235 +SYSZ_INS_VUPLLH = 2236 +SYSZ_INS_VX = 2237 +SYSZ_INS_VZERO = 2238 +SYSZ_INS_WCDGB = 2239 +SYSZ_INS_WCDLGB = 2240 +SYSZ_INS_WCGDB = 2241 +SYSZ_INS_WCLGDB = 2242 +SYSZ_INS_WFADB = 2243 +SYSZ_INS_WFASB = 2244 +SYSZ_INS_WFAXB = 2245 +SYSZ_INS_WFC = 2246 +SYSZ_INS_WFCDB = 2247 +SYSZ_INS_WFCEDB = 2248 +SYSZ_INS_WFCEDBS = 2249 +SYSZ_INS_WFCESB = 2250 +SYSZ_INS_WFCESBS = 2251 +SYSZ_INS_WFCEXB = 2252 +SYSZ_INS_WFCEXBS = 2253 +SYSZ_INS_WFCHDB = 2254 +SYSZ_INS_WFCHDBS = 2255 +SYSZ_INS_WFCHEDB = 2256 +SYSZ_INS_WFCHEDBS = 2257 +SYSZ_INS_WFCHESB = 2258 +SYSZ_INS_WFCHESBS = 2259 +SYSZ_INS_WFCHEXB = 2260 +SYSZ_INS_WFCHEXBS = 2261 +SYSZ_INS_WFCHSB = 2262 +SYSZ_INS_WFCHSBS = 2263 +SYSZ_INS_WFCHXB = 2264 +SYSZ_INS_WFCHXBS = 2265 +SYSZ_INS_WFCSB = 2266 +SYSZ_INS_WFCXB = 2267 +SYSZ_INS_WFDDB = 2268 +SYSZ_INS_WFDSB = 2269 +SYSZ_INS_WFDXB = 2270 +SYSZ_INS_WFIDB = 2271 +SYSZ_INS_WFISB = 2272 +SYSZ_INS_WFIXB = 2273 +SYSZ_INS_WFK = 2274 +SYSZ_INS_WFKDB = 2275 +SYSZ_INS_WFKEDB = 2276 +SYSZ_INS_WFKEDBS = 2277 +SYSZ_INS_WFKESB = 2278 +SYSZ_INS_WFKESBS = 2279 +SYSZ_INS_WFKEXB = 2280 +SYSZ_INS_WFKEXBS = 2281 +SYSZ_INS_WFKHDB = 2282 +SYSZ_INS_WFKHDBS = 2283 +SYSZ_INS_WFKHEDB = 2284 +SYSZ_INS_WFKHEDBS = 2285 +SYSZ_INS_WFKHESB = 2286 +SYSZ_INS_WFKHESBS = 2287 +SYSZ_INS_WFKHEXB = 2288 +SYSZ_INS_WFKHEXBS = 2289 +SYSZ_INS_WFKHSB = 2290 +SYSZ_INS_WFKHSBS = 2291 +SYSZ_INS_WFKHXB = 2292 +SYSZ_INS_WFKHXBS = 2293 +SYSZ_INS_WFKSB = 2294 +SYSZ_INS_WFKXB = 2295 +SYSZ_INS_WFLCDB = 2296 +SYSZ_INS_WFLCSB = 2297 +SYSZ_INS_WFLCXB = 2298 +SYSZ_INS_WFLLD = 2299 +SYSZ_INS_WFLLS = 2300 +SYSZ_INS_WFLNDB = 2301 +SYSZ_INS_WFLNSB = 2302 +SYSZ_INS_WFLNXB = 2303 +SYSZ_INS_WFLPDB = 2304 +SYSZ_INS_WFLPSB = 2305 +SYSZ_INS_WFLPXB = 2306 +SYSZ_INS_WFLRD = 2307 +SYSZ_INS_WFLRX = 2308 +SYSZ_INS_WFMADB = 2309 +SYSZ_INS_WFMASB = 2310 +SYSZ_INS_WFMAXB = 2311 +SYSZ_INS_WFMAXDB = 2312 +SYSZ_INS_WFMAXSB = 2313 +SYSZ_INS_WFMAXXB = 2314 +SYSZ_INS_WFMDB = 2315 +SYSZ_INS_WFMINDB = 2316 +SYSZ_INS_WFMINSB = 2317 +SYSZ_INS_WFMINXB = 2318 +SYSZ_INS_WFMSB = 2319 +SYSZ_INS_WFMSDB = 2320 +SYSZ_INS_WFMSSB = 2321 +SYSZ_INS_WFMSXB = 2322 +SYSZ_INS_WFMXB = 2323 +SYSZ_INS_WFNMADB = 2324 +SYSZ_INS_WFNMASB = 2325 +SYSZ_INS_WFNMAXB = 2326 +SYSZ_INS_WFNMSDB = 2327 +SYSZ_INS_WFNMSSB = 2328 +SYSZ_INS_WFNMSXB = 2329 +SYSZ_INS_WFPSODB = 2330 +SYSZ_INS_WFPSOSB = 2331 +SYSZ_INS_WFPSOXB = 2332 +SYSZ_INS_WFSDB = 2333 +SYSZ_INS_WFSQDB = 2334 +SYSZ_INS_WFSQSB = 2335 +SYSZ_INS_WFSQXB = 2336 +SYSZ_INS_WFSSB = 2337 +SYSZ_INS_WFSXB = 2338 +SYSZ_INS_WFTCIDB = 2339 +SYSZ_INS_WFTCISB = 2340 +SYSZ_INS_WFTCIXB = 2341 +SYSZ_INS_WLDEB = 2342 +SYSZ_INS_WLEDB = 2343 +SYSZ_INS_XSCH = 2344 +SYSZ_INS_ZAP = 2345 +SYSZ_INS_ENDING = 2346 + +SYSZ_GRP_INVALID = 0 +SYSZ_GRP_JUMP = 1 +SYSZ_GRP_DISTINCTOPS = 128 +SYSZ_GRP_FPEXTENSION = 129 +SYSZ_GRP_HIGHWORD = 130 +SYSZ_GRP_INTERLOCKEDACCESS1 = 131 +SYSZ_GRP_LOADSTOREONCOND = 132 +SYSZ_GRP_DFPPACKEDCONVERSION = 133 +SYSZ_GRP_DFPZONEDCONVERSION = 134 +SYSZ_GRP_ENHANCEDDAT2 = 135 +SYSZ_GRP_EXECUTIONHINT = 136 +SYSZ_GRP_GUARDEDSTORAGE = 137 +SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138 +SYSZ_GRP_LOADANDTRAP = 139 +SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140 +SYSZ_GRP_LOADSTOREONCOND2 = 141 +SYSZ_GRP_MESSAGESECURITYASSIST3 = 142 +SYSZ_GRP_MESSAGESECURITYASSIST4 = 143 +SYSZ_GRP_MESSAGESECURITYASSIST5 = 144 +SYSZ_GRP_MESSAGESECURITYASSIST7 = 145 +SYSZ_GRP_MESSAGESECURITYASSIST8 = 146 +SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147 +SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148 +SYSZ_GRP_NOVECTOR = 149 +SYSZ_GRP_POPULATIONCOUNT = 150 +SYSZ_GRP_PROCESSORASSIST = 151 +SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152 +SYSZ_GRP_TRANSACTIONALEXECUTION = 153 +SYSZ_GRP_VECTOR = 154 +SYSZ_GRP_VECTORENHANCEMENTS1 = 155 +SYSZ_GRP_VECTORPACKEDDECIMAL = 156 +SYSZ_GRP_ENDING = 157 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x.py b/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x.py new file mode 100644 index 0000000..1323dc3 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x.py @@ -0,0 +1,66 @@ +# Capstone Python bindings, by Fotis Loukos + +import ctypes, copy +from .tms320c64x_const import * + +# define the API +class TMS320C64xOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_int), + ('disp', ctypes.c_int), + ('unit', ctypes.c_int), + ('scaled', ctypes.c_int), + ('disptype', ctypes.c_int), + ('direction', ctypes.c_int), + ('modify', ctypes.c_int), + ) + +class TMS320C64xOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int32), + ('mem', TMS320C64xOpMem), + ) + +class TMS320C64xCondition(ctypes.Structure): + _fields_ = ( + ('reg', ctypes.c_uint), + ('zero', ctypes.c_uint), + ) + +class TMS320C64xFunctionalUnit(ctypes.Structure): + _fields_ = ( + ('unit', ctypes.c_uint), + ('side', ctypes.c_uint), + ('crosspath', ctypes.c_uint), + ) + +class TMS320C64xOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', TMS320C64xOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + +class CsTMS320C64x(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', TMS320C64xOp * 8), + ('condition', TMS320C64xCondition), + ('funit', TMS320C64xFunctionalUnit), + ('parallel', ctypes.c_uint), + ) + +def get_arch_info(a): + return (a.condition, a.funit, a.parallel, copy.deepcopy(a.operands[:a.op_count])) diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x_const.py new file mode 100644 index 0000000..7f8daae --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/tms320c64x_const.py @@ -0,0 +1,277 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py] + +TMS320C64X_OP_INVALID = 0 +TMS320C64X_OP_REG = 1 +TMS320C64X_OP_IMM = 2 +TMS320C64X_OP_MEM = 3 +TMS320C64X_OP_REGPAIR = 64 + +TMS320C64X_MEM_DISP_INVALID = 0 +TMS320C64X_MEM_DISP_CONSTANT = 1 +TMS320C64X_MEM_DISP_REGISTER = 2 + +TMS320C64X_MEM_DIR_INVALID = 0 +TMS320C64X_MEM_DIR_FW = 1 +TMS320C64X_MEM_DIR_BW = 2 + +TMS320C64X_MEM_MOD_INVALID = 0 +TMS320C64X_MEM_MOD_NO = 1 +TMS320C64X_MEM_MOD_PRE = 2 +TMS320C64X_MEM_MOD_POST = 3 + +TMS320C64X_REG_INVALID = 0 +TMS320C64X_REG_AMR = 1 +TMS320C64X_REG_CSR = 2 +TMS320C64X_REG_DIER = 3 +TMS320C64X_REG_DNUM = 4 +TMS320C64X_REG_ECR = 5 +TMS320C64X_REG_GFPGFR = 6 +TMS320C64X_REG_GPLYA = 7 +TMS320C64X_REG_GPLYB = 8 +TMS320C64X_REG_ICR = 9 +TMS320C64X_REG_IER = 10 +TMS320C64X_REG_IERR = 11 +TMS320C64X_REG_ILC = 12 +TMS320C64X_REG_IRP = 13 +TMS320C64X_REG_ISR = 14 +TMS320C64X_REG_ISTP = 15 +TMS320C64X_REG_ITSR = 16 +TMS320C64X_REG_NRP = 17 +TMS320C64X_REG_NTSR = 18 +TMS320C64X_REG_REP = 19 +TMS320C64X_REG_RILC = 20 +TMS320C64X_REG_SSR = 21 +TMS320C64X_REG_TSCH = 22 +TMS320C64X_REG_TSCL = 23 +TMS320C64X_REG_TSR = 24 +TMS320C64X_REG_A0 = 25 +TMS320C64X_REG_A1 = 26 +TMS320C64X_REG_A2 = 27 +TMS320C64X_REG_A3 = 28 +TMS320C64X_REG_A4 = 29 +TMS320C64X_REG_A5 = 30 +TMS320C64X_REG_A6 = 31 +TMS320C64X_REG_A7 = 32 +TMS320C64X_REG_A8 = 33 +TMS320C64X_REG_A9 = 34 +TMS320C64X_REG_A10 = 35 +TMS320C64X_REG_A11 = 36 +TMS320C64X_REG_A12 = 37 +TMS320C64X_REG_A13 = 38 +TMS320C64X_REG_A14 = 39 +TMS320C64X_REG_A15 = 40 +TMS320C64X_REG_A16 = 41 +TMS320C64X_REG_A17 = 42 +TMS320C64X_REG_A18 = 43 +TMS320C64X_REG_A19 = 44 +TMS320C64X_REG_A20 = 45 +TMS320C64X_REG_A21 = 46 +TMS320C64X_REG_A22 = 47 +TMS320C64X_REG_A23 = 48 +TMS320C64X_REG_A24 = 49 +TMS320C64X_REG_A25 = 50 +TMS320C64X_REG_A26 = 51 +TMS320C64X_REG_A27 = 52 +TMS320C64X_REG_A28 = 53 +TMS320C64X_REG_A29 = 54 +TMS320C64X_REG_A30 = 55 +TMS320C64X_REG_A31 = 56 +TMS320C64X_REG_B0 = 57 +TMS320C64X_REG_B1 = 58 +TMS320C64X_REG_B2 = 59 +TMS320C64X_REG_B3 = 60 +TMS320C64X_REG_B4 = 61 +TMS320C64X_REG_B5 = 62 +TMS320C64X_REG_B6 = 63 +TMS320C64X_REG_B7 = 64 +TMS320C64X_REG_B8 = 65 +TMS320C64X_REG_B9 = 66 +TMS320C64X_REG_B10 = 67 +TMS320C64X_REG_B11 = 68 +TMS320C64X_REG_B12 = 69 +TMS320C64X_REG_B13 = 70 +TMS320C64X_REG_B14 = 71 +TMS320C64X_REG_B15 = 72 +TMS320C64X_REG_B16 = 73 +TMS320C64X_REG_B17 = 74 +TMS320C64X_REG_B18 = 75 +TMS320C64X_REG_B19 = 76 +TMS320C64X_REG_B20 = 77 +TMS320C64X_REG_B21 = 78 +TMS320C64X_REG_B22 = 79 +TMS320C64X_REG_B23 = 80 +TMS320C64X_REG_B24 = 81 +TMS320C64X_REG_B25 = 82 +TMS320C64X_REG_B26 = 83 +TMS320C64X_REG_B27 = 84 +TMS320C64X_REG_B28 = 85 +TMS320C64X_REG_B29 = 86 +TMS320C64X_REG_B30 = 87 +TMS320C64X_REG_B31 = 88 +TMS320C64X_REG_PCE1 = 89 +TMS320C64X_REG_ENDING = 90 +TMS320C64X_REG_EFR = TMS320C64X_REG_ECR +TMS320C64X_REG_IFR = TMS320C64X_REG_ISR + +TMS320C64X_INS_INVALID = 0 +TMS320C64X_INS_ABS = 1 +TMS320C64X_INS_ABS2 = 2 +TMS320C64X_INS_ADD = 3 +TMS320C64X_INS_ADD2 = 4 +TMS320C64X_INS_ADD4 = 5 +TMS320C64X_INS_ADDAB = 6 +TMS320C64X_INS_ADDAD = 7 +TMS320C64X_INS_ADDAH = 8 +TMS320C64X_INS_ADDAW = 9 +TMS320C64X_INS_ADDK = 10 +TMS320C64X_INS_ADDKPC = 11 +TMS320C64X_INS_ADDU = 12 +TMS320C64X_INS_AND = 13 +TMS320C64X_INS_ANDN = 14 +TMS320C64X_INS_AVG2 = 15 +TMS320C64X_INS_AVGU4 = 16 +TMS320C64X_INS_B = 17 +TMS320C64X_INS_BDEC = 18 +TMS320C64X_INS_BITC4 = 19 +TMS320C64X_INS_BNOP = 20 +TMS320C64X_INS_BPOS = 21 +TMS320C64X_INS_CLR = 22 +TMS320C64X_INS_CMPEQ = 23 +TMS320C64X_INS_CMPEQ2 = 24 +TMS320C64X_INS_CMPEQ4 = 25 +TMS320C64X_INS_CMPGT = 26 +TMS320C64X_INS_CMPGT2 = 27 +TMS320C64X_INS_CMPGTU4 = 28 +TMS320C64X_INS_CMPLT = 29 +TMS320C64X_INS_CMPLTU = 30 +TMS320C64X_INS_DEAL = 31 +TMS320C64X_INS_DOTP2 = 32 +TMS320C64X_INS_DOTPN2 = 33 +TMS320C64X_INS_DOTPNRSU2 = 34 +TMS320C64X_INS_DOTPRSU2 = 35 +TMS320C64X_INS_DOTPSU4 = 36 +TMS320C64X_INS_DOTPU4 = 37 +TMS320C64X_INS_EXT = 38 +TMS320C64X_INS_EXTU = 39 +TMS320C64X_INS_GMPGTU = 40 +TMS320C64X_INS_GMPY4 = 41 +TMS320C64X_INS_LDB = 42 +TMS320C64X_INS_LDBU = 43 +TMS320C64X_INS_LDDW = 44 +TMS320C64X_INS_LDH = 45 +TMS320C64X_INS_LDHU = 46 +TMS320C64X_INS_LDNDW = 47 +TMS320C64X_INS_LDNW = 48 +TMS320C64X_INS_LDW = 49 +TMS320C64X_INS_LMBD = 50 +TMS320C64X_INS_MAX2 = 51 +TMS320C64X_INS_MAXU4 = 52 +TMS320C64X_INS_MIN2 = 53 +TMS320C64X_INS_MINU4 = 54 +TMS320C64X_INS_MPY = 55 +TMS320C64X_INS_MPY2 = 56 +TMS320C64X_INS_MPYH = 57 +TMS320C64X_INS_MPYHI = 58 +TMS320C64X_INS_MPYHIR = 59 +TMS320C64X_INS_MPYHL = 60 +TMS320C64X_INS_MPYHLU = 61 +TMS320C64X_INS_MPYHSLU = 62 +TMS320C64X_INS_MPYHSU = 63 +TMS320C64X_INS_MPYHU = 64 +TMS320C64X_INS_MPYHULS = 65 +TMS320C64X_INS_MPYHUS = 66 +TMS320C64X_INS_MPYLH = 67 +TMS320C64X_INS_MPYLHU = 68 +TMS320C64X_INS_MPYLI = 69 +TMS320C64X_INS_MPYLIR = 70 +TMS320C64X_INS_MPYLSHU = 71 +TMS320C64X_INS_MPYLUHS = 72 +TMS320C64X_INS_MPYSU = 73 +TMS320C64X_INS_MPYSU4 = 74 +TMS320C64X_INS_MPYU = 75 +TMS320C64X_INS_MPYU4 = 76 +TMS320C64X_INS_MPYUS = 77 +TMS320C64X_INS_MVC = 78 +TMS320C64X_INS_MVD = 79 +TMS320C64X_INS_MVK = 80 +TMS320C64X_INS_MVKL = 81 +TMS320C64X_INS_MVKLH = 82 +TMS320C64X_INS_NOP = 83 +TMS320C64X_INS_NORM = 84 +TMS320C64X_INS_OR = 85 +TMS320C64X_INS_PACK2 = 86 +TMS320C64X_INS_PACKH2 = 87 +TMS320C64X_INS_PACKH4 = 88 +TMS320C64X_INS_PACKHL2 = 89 +TMS320C64X_INS_PACKL4 = 90 +TMS320C64X_INS_PACKLH2 = 91 +TMS320C64X_INS_ROTL = 92 +TMS320C64X_INS_SADD = 93 +TMS320C64X_INS_SADD2 = 94 +TMS320C64X_INS_SADDU4 = 95 +TMS320C64X_INS_SADDUS2 = 96 +TMS320C64X_INS_SAT = 97 +TMS320C64X_INS_SET = 98 +TMS320C64X_INS_SHFL = 99 +TMS320C64X_INS_SHL = 100 +TMS320C64X_INS_SHLMB = 101 +TMS320C64X_INS_SHR = 102 +TMS320C64X_INS_SHR2 = 103 +TMS320C64X_INS_SHRMB = 104 +TMS320C64X_INS_SHRU = 105 +TMS320C64X_INS_SHRU2 = 106 +TMS320C64X_INS_SMPY = 107 +TMS320C64X_INS_SMPY2 = 108 +TMS320C64X_INS_SMPYH = 109 +TMS320C64X_INS_SMPYHL = 110 +TMS320C64X_INS_SMPYLH = 111 +TMS320C64X_INS_SPACK2 = 112 +TMS320C64X_INS_SPACKU4 = 113 +TMS320C64X_INS_SSHL = 114 +TMS320C64X_INS_SSHVL = 115 +TMS320C64X_INS_SSHVR = 116 +TMS320C64X_INS_SSUB = 117 +TMS320C64X_INS_STB = 118 +TMS320C64X_INS_STDW = 119 +TMS320C64X_INS_STH = 120 +TMS320C64X_INS_STNDW = 121 +TMS320C64X_INS_STNW = 122 +TMS320C64X_INS_STW = 123 +TMS320C64X_INS_SUB = 124 +TMS320C64X_INS_SUB2 = 125 +TMS320C64X_INS_SUB4 = 126 +TMS320C64X_INS_SUBAB = 127 +TMS320C64X_INS_SUBABS4 = 128 +TMS320C64X_INS_SUBAH = 129 +TMS320C64X_INS_SUBAW = 130 +TMS320C64X_INS_SUBC = 131 +TMS320C64X_INS_SUBU = 132 +TMS320C64X_INS_SWAP4 = 133 +TMS320C64X_INS_UNPKHU4 = 134 +TMS320C64X_INS_UNPKLU4 = 135 +TMS320C64X_INS_XOR = 136 +TMS320C64X_INS_XPND2 = 137 +TMS320C64X_INS_XPND4 = 138 +TMS320C64X_INS_IDLE = 139 +TMS320C64X_INS_MV = 140 +TMS320C64X_INS_NEG = 141 +TMS320C64X_INS_NOT = 142 +TMS320C64X_INS_SWAP2 = 143 +TMS320C64X_INS_ZERO = 144 +TMS320C64X_INS_ENDING = 145 + +TMS320C64X_GRP_INVALID = 0 +TMS320C64X_GRP_JUMP = 1 +TMS320C64X_GRP_FUNIT_D = 128 +TMS320C64X_GRP_FUNIT_L = 129 +TMS320C64X_GRP_FUNIT_M = 130 +TMS320C64X_GRP_FUNIT_S = 131 +TMS320C64X_GRP_FUNIT_NO = 132 +TMS320C64X_GRP_ENDING = 133 + +TMS320C64X_FUNIT_INVALID = 0 +TMS320C64X_FUNIT_D = 1 +TMS320C64X_FUNIT_L = 2 +TMS320C64X_FUNIT_M = 3 +TMS320C64X_FUNIT_S = 4 +TMS320C64X_FUNIT_NO = 5 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/x86.py b/white_patch_detect/capstone-master/bindings/python/capstone/x86.py new file mode 100644 index 0000000..63bcd99 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/x86.py @@ -0,0 +1,85 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .x86_const import * + +# define the API +class X86OpMem(ctypes.Structure): + _fields_ = ( + ('segment', ctypes.c_uint), + ('base', ctypes.c_uint), + ('index', ctypes.c_uint), + ('scale', ctypes.c_int), + ('disp', ctypes.c_int64), + ) + +class X86OpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', X86OpMem), + ) + +class X86Op(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', X86OpValue), + ('size', ctypes.c_uint8), + ('access', ctypes.c_uint8), + ('avx_bcast', ctypes.c_uint), + ('avx_zero_opmask', ctypes.c_bool), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsX86Encoding(ctypes.Structure): + _fields_ = ( + ('modrm_offset', ctypes.c_uint8), + ('disp_offset', ctypes.c_uint8), + ('disp_size', ctypes.c_uint8), + ('imm_offset', ctypes.c_uint8), + ('imm_size', ctypes.c_uint8), + ) + +class CsX86(ctypes.Structure): + _fields_ = ( + ('prefix', ctypes.c_uint8 * 4), + ('opcode', ctypes.c_uint8 * 4), + ('rex', ctypes.c_uint8), + ('addr_size', ctypes.c_uint8), + ('modrm', ctypes.c_uint8), + ('sib', ctypes.c_uint8), + ('disp', ctypes.c_int64), + ('sib_index', ctypes.c_uint), + ('sib_scale', ctypes.c_int8), + ('sib_base', ctypes.c_uint), + ('xop_cc', ctypes.c_uint), + ('sse_cc', ctypes.c_uint), + ('avx_cc', ctypes.c_uint), + ('avx_sae', ctypes.c_bool), + ('avx_rm', ctypes.c_uint), + ('eflags', ctypes.c_uint64), + ('op_count', ctypes.c_uint8), + ('operands', X86Op * 8), + ('encoding', CsX86Encoding), + ) + +def get_arch_info(a): + return (a.prefix[:], a.opcode[:], a.rex, a.addr_size, \ + a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, \ + a.sib_base, a.xop_cc, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, a.eflags, \ + a.encoding.modrm_offset, a.encoding.disp_offset, a.encoding.disp_size, a.encoding.imm_offset, a.encoding.imm_size, \ + copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/x86_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/x86_const.py new file mode 100644 index 0000000..06b1aff --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/x86_const.py @@ -0,0 +1,1962 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py] + +X86_REG_INVALID = 0 +X86_REG_AH = 1 +X86_REG_AL = 2 +X86_REG_AX = 3 +X86_REG_BH = 4 +X86_REG_BL = 5 +X86_REG_BP = 6 +X86_REG_BPL = 7 +X86_REG_BX = 8 +X86_REG_CH = 9 +X86_REG_CL = 10 +X86_REG_CS = 11 +X86_REG_CX = 12 +X86_REG_DH = 13 +X86_REG_DI = 14 +X86_REG_DIL = 15 +X86_REG_DL = 16 +X86_REG_DS = 17 +X86_REG_DX = 18 +X86_REG_EAX = 19 +X86_REG_EBP = 20 +X86_REG_EBX = 21 +X86_REG_ECX = 22 +X86_REG_EDI = 23 +X86_REG_EDX = 24 +X86_REG_EFLAGS = 25 +X86_REG_EIP = 26 +X86_REG_EIZ = 27 +X86_REG_ES = 28 +X86_REG_ESI = 29 +X86_REG_ESP = 30 +X86_REG_FPSW = 31 +X86_REG_FS = 32 +X86_REG_GS = 33 +X86_REG_IP = 34 +X86_REG_RAX = 35 +X86_REG_RBP = 36 +X86_REG_RBX = 37 +X86_REG_RCX = 38 +X86_REG_RDI = 39 +X86_REG_RDX = 40 +X86_REG_RIP = 41 +X86_REG_RIZ = 42 +X86_REG_RSI = 43 +X86_REG_RSP = 44 +X86_REG_SI = 45 +X86_REG_SIL = 46 +X86_REG_SP = 47 +X86_REG_SPL = 48 +X86_REG_SS = 49 +X86_REG_CR0 = 50 +X86_REG_CR1 = 51 +X86_REG_CR2 = 52 +X86_REG_CR3 = 53 +X86_REG_CR4 = 54 +X86_REG_CR5 = 55 +X86_REG_CR6 = 56 +X86_REG_CR7 = 57 +X86_REG_CR8 = 58 +X86_REG_CR9 = 59 +X86_REG_CR10 = 60 +X86_REG_CR11 = 61 +X86_REG_CR12 = 62 +X86_REG_CR13 = 63 +X86_REG_CR14 = 64 +X86_REG_CR15 = 65 +X86_REG_DR0 = 66 +X86_REG_DR1 = 67 +X86_REG_DR2 = 68 +X86_REG_DR3 = 69 +X86_REG_DR4 = 70 +X86_REG_DR5 = 71 +X86_REG_DR6 = 72 +X86_REG_DR7 = 73 +X86_REG_DR8 = 74 +X86_REG_DR9 = 75 +X86_REG_DR10 = 76 +X86_REG_DR11 = 77 +X86_REG_DR12 = 78 +X86_REG_DR13 = 79 +X86_REG_DR14 = 80 +X86_REG_DR15 = 81 +X86_REG_FP0 = 82 +X86_REG_FP1 = 83 +X86_REG_FP2 = 84 +X86_REG_FP3 = 85 +X86_REG_FP4 = 86 +X86_REG_FP5 = 87 +X86_REG_FP6 = 88 +X86_REG_FP7 = 89 +X86_REG_K0 = 90 +X86_REG_K1 = 91 +X86_REG_K2 = 92 +X86_REG_K3 = 93 +X86_REG_K4 = 94 +X86_REG_K5 = 95 +X86_REG_K6 = 96 +X86_REG_K7 = 97 +X86_REG_MM0 = 98 +X86_REG_MM1 = 99 +X86_REG_MM2 = 100 +X86_REG_MM3 = 101 +X86_REG_MM4 = 102 +X86_REG_MM5 = 103 +X86_REG_MM6 = 104 +X86_REG_MM7 = 105 +X86_REG_R8 = 106 +X86_REG_R9 = 107 +X86_REG_R10 = 108 +X86_REG_R11 = 109 +X86_REG_R12 = 110 +X86_REG_R13 = 111 +X86_REG_R14 = 112 +X86_REG_R15 = 113 +X86_REG_ST0 = 114 +X86_REG_ST1 = 115 +X86_REG_ST2 = 116 +X86_REG_ST3 = 117 +X86_REG_ST4 = 118 +X86_REG_ST5 = 119 +X86_REG_ST6 = 120 +X86_REG_ST7 = 121 +X86_REG_XMM0 = 122 +X86_REG_XMM1 = 123 +X86_REG_XMM2 = 124 +X86_REG_XMM3 = 125 +X86_REG_XMM4 = 126 +X86_REG_XMM5 = 127 +X86_REG_XMM6 = 128 +X86_REG_XMM7 = 129 +X86_REG_XMM8 = 130 +X86_REG_XMM9 = 131 +X86_REG_XMM10 = 132 +X86_REG_XMM11 = 133 +X86_REG_XMM12 = 134 +X86_REG_XMM13 = 135 +X86_REG_XMM14 = 136 +X86_REG_XMM15 = 137 +X86_REG_XMM16 = 138 +X86_REG_XMM17 = 139 +X86_REG_XMM18 = 140 +X86_REG_XMM19 = 141 +X86_REG_XMM20 = 142 +X86_REG_XMM21 = 143 +X86_REG_XMM22 = 144 +X86_REG_XMM23 = 145 +X86_REG_XMM24 = 146 +X86_REG_XMM25 = 147 +X86_REG_XMM26 = 148 +X86_REG_XMM27 = 149 +X86_REG_XMM28 = 150 +X86_REG_XMM29 = 151 +X86_REG_XMM30 = 152 +X86_REG_XMM31 = 153 +X86_REG_YMM0 = 154 +X86_REG_YMM1 = 155 +X86_REG_YMM2 = 156 +X86_REG_YMM3 = 157 +X86_REG_YMM4 = 158 +X86_REG_YMM5 = 159 +X86_REG_YMM6 = 160 +X86_REG_YMM7 = 161 +X86_REG_YMM8 = 162 +X86_REG_YMM9 = 163 +X86_REG_YMM10 = 164 +X86_REG_YMM11 = 165 +X86_REG_YMM12 = 166 +X86_REG_YMM13 = 167 +X86_REG_YMM14 = 168 +X86_REG_YMM15 = 169 +X86_REG_YMM16 = 170 +X86_REG_YMM17 = 171 +X86_REG_YMM18 = 172 +X86_REG_YMM19 = 173 +X86_REG_YMM20 = 174 +X86_REG_YMM21 = 175 +X86_REG_YMM22 = 176 +X86_REG_YMM23 = 177 +X86_REG_YMM24 = 178 +X86_REG_YMM25 = 179 +X86_REG_YMM26 = 180 +X86_REG_YMM27 = 181 +X86_REG_YMM28 = 182 +X86_REG_YMM29 = 183 +X86_REG_YMM30 = 184 +X86_REG_YMM31 = 185 +X86_REG_ZMM0 = 186 +X86_REG_ZMM1 = 187 +X86_REG_ZMM2 = 188 +X86_REG_ZMM3 = 189 +X86_REG_ZMM4 = 190 +X86_REG_ZMM5 = 191 +X86_REG_ZMM6 = 192 +X86_REG_ZMM7 = 193 +X86_REG_ZMM8 = 194 +X86_REG_ZMM9 = 195 +X86_REG_ZMM10 = 196 +X86_REG_ZMM11 = 197 +X86_REG_ZMM12 = 198 +X86_REG_ZMM13 = 199 +X86_REG_ZMM14 = 200 +X86_REG_ZMM15 = 201 +X86_REG_ZMM16 = 202 +X86_REG_ZMM17 = 203 +X86_REG_ZMM18 = 204 +X86_REG_ZMM19 = 205 +X86_REG_ZMM20 = 206 +X86_REG_ZMM21 = 207 +X86_REG_ZMM22 = 208 +X86_REG_ZMM23 = 209 +X86_REG_ZMM24 = 210 +X86_REG_ZMM25 = 211 +X86_REG_ZMM26 = 212 +X86_REG_ZMM27 = 213 +X86_REG_ZMM28 = 214 +X86_REG_ZMM29 = 215 +X86_REG_ZMM30 = 216 +X86_REG_ZMM31 = 217 +X86_REG_R8B = 218 +X86_REG_R9B = 219 +X86_REG_R10B = 220 +X86_REG_R11B = 221 +X86_REG_R12B = 222 +X86_REG_R13B = 223 +X86_REG_R14B = 224 +X86_REG_R15B = 225 +X86_REG_R8D = 226 +X86_REG_R9D = 227 +X86_REG_R10D = 228 +X86_REG_R11D = 229 +X86_REG_R12D = 230 +X86_REG_R13D = 231 +X86_REG_R14D = 232 +X86_REG_R15D = 233 +X86_REG_R8W = 234 +X86_REG_R9W = 235 +X86_REG_R10W = 236 +X86_REG_R11W = 237 +X86_REG_R12W = 238 +X86_REG_R13W = 239 +X86_REG_R14W = 240 +X86_REG_R15W = 241 +X86_REG_ENDING = 242 +X86_EFLAGS_MODIFY_AF = 1<<0 +X86_EFLAGS_MODIFY_CF = 1<<1 +X86_EFLAGS_MODIFY_SF = 1<<2 +X86_EFLAGS_MODIFY_ZF = 1<<3 +X86_EFLAGS_MODIFY_PF = 1<<4 +X86_EFLAGS_MODIFY_OF = 1<<5 +X86_EFLAGS_MODIFY_TF = 1<<6 +X86_EFLAGS_MODIFY_IF = 1<<7 +X86_EFLAGS_MODIFY_DF = 1<<8 +X86_EFLAGS_MODIFY_NT = 1<<9 +X86_EFLAGS_MODIFY_RF = 1<<10 +X86_EFLAGS_PRIOR_OF = 1<<11 +X86_EFLAGS_PRIOR_SF = 1<<12 +X86_EFLAGS_PRIOR_ZF = 1<<13 +X86_EFLAGS_PRIOR_AF = 1<<14 +X86_EFLAGS_PRIOR_PF = 1<<15 +X86_EFLAGS_PRIOR_CF = 1<<16 +X86_EFLAGS_PRIOR_TF = 1<<17 +X86_EFLAGS_PRIOR_IF = 1<<18 +X86_EFLAGS_PRIOR_DF = 1<<19 +X86_EFLAGS_PRIOR_NT = 1<<20 +X86_EFLAGS_RESET_OF = 1<<21 +X86_EFLAGS_RESET_CF = 1<<22 +X86_EFLAGS_RESET_DF = 1<<23 +X86_EFLAGS_RESET_IF = 1<<24 +X86_EFLAGS_RESET_SF = 1<<25 +X86_EFLAGS_RESET_AF = 1<<26 +X86_EFLAGS_RESET_TF = 1<<27 +X86_EFLAGS_RESET_NT = 1<<28 +X86_EFLAGS_RESET_PF = 1<<29 +X86_EFLAGS_SET_CF = 1<<30 +X86_EFLAGS_SET_DF = 1<<31 +X86_EFLAGS_SET_IF = 1<<32 +X86_EFLAGS_TEST_OF = 1<<33 +X86_EFLAGS_TEST_SF = 1<<34 +X86_EFLAGS_TEST_ZF = 1<<35 +X86_EFLAGS_TEST_PF = 1<<36 +X86_EFLAGS_TEST_CF = 1<<37 +X86_EFLAGS_TEST_NT = 1<<38 +X86_EFLAGS_TEST_DF = 1<<39 +X86_EFLAGS_UNDEFINED_OF = 1<<40 +X86_EFLAGS_UNDEFINED_SF = 1<<41 +X86_EFLAGS_UNDEFINED_ZF = 1<<42 +X86_EFLAGS_UNDEFINED_PF = 1<<43 +X86_EFLAGS_UNDEFINED_AF = 1<<44 +X86_EFLAGS_UNDEFINED_CF = 1<<45 +X86_EFLAGS_RESET_RF = 1<<46 +X86_EFLAGS_TEST_RF = 1<<47 +X86_EFLAGS_TEST_IF = 1<<48 +X86_EFLAGS_TEST_TF = 1<<49 +X86_EFLAGS_TEST_AF = 1<<50 +X86_EFLAGS_RESET_ZF = 1<<51 +X86_EFLAGS_SET_OF = 1<<52 +X86_EFLAGS_SET_SF = 1<<53 +X86_EFLAGS_SET_ZF = 1<<54 +X86_EFLAGS_SET_AF = 1<<55 +X86_EFLAGS_SET_PF = 1<<56 +X86_EFLAGS_RESET_0F = 1<<57 +X86_EFLAGS_RESET_AC = 1<<58 +X86_FPU_FLAGS_MODIFY_C0 = 1<<0 +X86_FPU_FLAGS_MODIFY_C1 = 1<<1 +X86_FPU_FLAGS_MODIFY_C2 = 1<<2 +X86_FPU_FLAGS_MODIFY_C3 = 1<<3 +X86_FPU_FLAGS_RESET_C0 = 1<<4 +X86_FPU_FLAGS_RESET_C1 = 1<<5 +X86_FPU_FLAGS_RESET_C2 = 1<<6 +X86_FPU_FLAGS_RESET_C3 = 1<<7 +X86_FPU_FLAGS_SET_C0 = 1<<8 +X86_FPU_FLAGS_SET_C1 = 1<<9 +X86_FPU_FLAGS_SET_C2 = 1<<10 +X86_FPU_FLAGS_SET_C3 = 1<<11 +X86_FPU_FLAGS_UNDEFINED_C0 = 1<<12 +X86_FPU_FLAGS_UNDEFINED_C1 = 1<<13 +X86_FPU_FLAGS_UNDEFINED_C2 = 1<<14 +X86_FPU_FLAGS_UNDEFINED_C3 = 1<<15 +X86_FPU_FLAGS_TEST_C0 = 1<<16 +X86_FPU_FLAGS_TEST_C1 = 1<<17 +X86_FPU_FLAGS_TEST_C2 = 1<<18 +X86_FPU_FLAGS_TEST_C3 = 1<<19 + +X86_OP_INVALID = 0 +X86_OP_REG = 1 +X86_OP_IMM = 2 +X86_OP_MEM = 3 + +X86_XOP_CC_INVALID = 0 +X86_XOP_CC_LT = 1 +X86_XOP_CC_LE = 2 +X86_XOP_CC_GT = 3 +X86_XOP_CC_GE = 4 +X86_XOP_CC_EQ = 5 +X86_XOP_CC_NEQ = 6 +X86_XOP_CC_FALSE = 7 +X86_XOP_CC_TRUE = 8 + +X86_AVX_BCAST_INVALID = 0 +X86_AVX_BCAST_2 = 1 +X86_AVX_BCAST_4 = 2 +X86_AVX_BCAST_8 = 3 +X86_AVX_BCAST_16 = 4 + +X86_SSE_CC_INVALID = 0 +X86_SSE_CC_EQ = 1 +X86_SSE_CC_LT = 2 +X86_SSE_CC_LE = 3 +X86_SSE_CC_UNORD = 4 +X86_SSE_CC_NEQ = 5 +X86_SSE_CC_NLT = 6 +X86_SSE_CC_NLE = 7 +X86_SSE_CC_ORD = 8 + +X86_AVX_CC_INVALID = 0 +X86_AVX_CC_EQ = 1 +X86_AVX_CC_LT = 2 +X86_AVX_CC_LE = 3 +X86_AVX_CC_UNORD = 4 +X86_AVX_CC_NEQ = 5 +X86_AVX_CC_NLT = 6 +X86_AVX_CC_NLE = 7 +X86_AVX_CC_ORD = 8 +X86_AVX_CC_EQ_UQ = 9 +X86_AVX_CC_NGE = 10 +X86_AVX_CC_NGT = 11 +X86_AVX_CC_FALSE = 12 +X86_AVX_CC_NEQ_OQ = 13 +X86_AVX_CC_GE = 14 +X86_AVX_CC_GT = 15 +X86_AVX_CC_TRUE = 16 +X86_AVX_CC_EQ_OS = 17 +X86_AVX_CC_LT_OQ = 18 +X86_AVX_CC_LE_OQ = 19 +X86_AVX_CC_UNORD_S = 20 +X86_AVX_CC_NEQ_US = 21 +X86_AVX_CC_NLT_UQ = 22 +X86_AVX_CC_NLE_UQ = 23 +X86_AVX_CC_ORD_S = 24 +X86_AVX_CC_EQ_US = 25 +X86_AVX_CC_NGE_UQ = 26 +X86_AVX_CC_NGT_UQ = 27 +X86_AVX_CC_FALSE_OS = 28 +X86_AVX_CC_NEQ_OS = 29 +X86_AVX_CC_GE_OQ = 30 +X86_AVX_CC_GT_OQ = 31 +X86_AVX_CC_TRUE_US = 32 + +X86_AVX_RM_INVALID = 0 +X86_AVX_RM_RN = 1 +X86_AVX_RM_RD = 2 +X86_AVX_RM_RU = 3 +X86_AVX_RM_RZ = 4 +X86_PREFIX_LOCK = 0xf0 +X86_PREFIX_REP = 0xf3 +X86_PREFIX_REPE = 0xf3 +X86_PREFIX_REPNE = 0xf2 +X86_PREFIX_CS = 0x2e +X86_PREFIX_SS = 0x36 +X86_PREFIX_DS = 0x3e +X86_PREFIX_ES = 0x26 +X86_PREFIX_FS = 0x64 +X86_PREFIX_GS = 0x65 +X86_PREFIX_OPSIZE = 0x66 +X86_PREFIX_ADDRSIZE = 0x67 + +X86_INS_INVALID = 0 +X86_INS_AAA = 1 +X86_INS_AAD = 2 +X86_INS_AAM = 3 +X86_INS_AAS = 4 +X86_INS_FABS = 5 +X86_INS_ADC = 6 +X86_INS_ADCX = 7 +X86_INS_ADD = 8 +X86_INS_ADDPD = 9 +X86_INS_ADDPS = 10 +X86_INS_ADDSD = 11 +X86_INS_ADDSS = 12 +X86_INS_ADDSUBPD = 13 +X86_INS_ADDSUBPS = 14 +X86_INS_FADD = 15 +X86_INS_FIADD = 16 +X86_INS_FADDP = 17 +X86_INS_ADOX = 18 +X86_INS_AESDECLAST = 19 +X86_INS_AESDEC = 20 +X86_INS_AESENCLAST = 21 +X86_INS_AESENC = 22 +X86_INS_AESIMC = 23 +X86_INS_AESKEYGENASSIST = 24 +X86_INS_AND = 25 +X86_INS_ANDN = 26 +X86_INS_ANDNPD = 27 +X86_INS_ANDNPS = 28 +X86_INS_ANDPD = 29 +X86_INS_ANDPS = 30 +X86_INS_ARPL = 31 +X86_INS_BEXTR = 32 +X86_INS_BLCFILL = 33 +X86_INS_BLCI = 34 +X86_INS_BLCIC = 35 +X86_INS_BLCMSK = 36 +X86_INS_BLCS = 37 +X86_INS_BLENDPD = 38 +X86_INS_BLENDPS = 39 +X86_INS_BLENDVPD = 40 +X86_INS_BLENDVPS = 41 +X86_INS_BLSFILL = 42 +X86_INS_BLSI = 43 +X86_INS_BLSIC = 44 +X86_INS_BLSMSK = 45 +X86_INS_BLSR = 46 +X86_INS_BOUND = 47 +X86_INS_BSF = 48 +X86_INS_BSR = 49 +X86_INS_BSWAP = 50 +X86_INS_BT = 51 +X86_INS_BTC = 52 +X86_INS_BTR = 53 +X86_INS_BTS = 54 +X86_INS_BZHI = 55 +X86_INS_CALL = 56 +X86_INS_CBW = 57 +X86_INS_CDQ = 58 +X86_INS_CDQE = 59 +X86_INS_FCHS = 60 +X86_INS_CLAC = 61 +X86_INS_CLC = 62 +X86_INS_CLD = 63 +X86_INS_CLFLUSH = 64 +X86_INS_CLFLUSHOPT = 65 +X86_INS_CLGI = 66 +X86_INS_CLI = 67 +X86_INS_CLTS = 68 +X86_INS_CLWB = 69 +X86_INS_CMC = 70 +X86_INS_CMOVA = 71 +X86_INS_CMOVAE = 72 +X86_INS_CMOVB = 73 +X86_INS_CMOVBE = 74 +X86_INS_FCMOVBE = 75 +X86_INS_FCMOVB = 76 +X86_INS_CMOVE = 77 +X86_INS_FCMOVE = 78 +X86_INS_CMOVG = 79 +X86_INS_CMOVGE = 80 +X86_INS_CMOVL = 81 +X86_INS_CMOVLE = 82 +X86_INS_FCMOVNBE = 83 +X86_INS_FCMOVNB = 84 +X86_INS_CMOVNE = 85 +X86_INS_FCMOVNE = 86 +X86_INS_CMOVNO = 87 +X86_INS_CMOVNP = 88 +X86_INS_FCMOVNU = 89 +X86_INS_CMOVNS = 90 +X86_INS_CMOVO = 91 +X86_INS_CMOVP = 92 +X86_INS_FCMOVU = 93 +X86_INS_CMOVS = 94 +X86_INS_CMP = 95 +X86_INS_CMPSB = 96 +X86_INS_CMPSQ = 97 +X86_INS_CMPSW = 98 +X86_INS_CMPXCHG16B = 99 +X86_INS_CMPXCHG = 100 +X86_INS_CMPXCHG8B = 101 +X86_INS_COMISD = 102 +X86_INS_COMISS = 103 +X86_INS_FCOMP = 104 +X86_INS_FCOMIP = 105 +X86_INS_FCOMI = 106 +X86_INS_FCOM = 107 +X86_INS_FCOS = 108 +X86_INS_CPUID = 109 +X86_INS_CQO = 110 +X86_INS_CRC32 = 111 +X86_INS_CVTDQ2PD = 112 +X86_INS_CVTDQ2PS = 113 +X86_INS_CVTPD2DQ = 114 +X86_INS_CVTPD2PS = 115 +X86_INS_CVTPS2DQ = 116 +X86_INS_CVTPS2PD = 117 +X86_INS_CVTSD2SI = 118 +X86_INS_CVTSD2SS = 119 +X86_INS_CVTSI2SD = 120 +X86_INS_CVTSI2SS = 121 +X86_INS_CVTSS2SD = 122 +X86_INS_CVTSS2SI = 123 +X86_INS_CVTTPD2DQ = 124 +X86_INS_CVTTPS2DQ = 125 +X86_INS_CVTTSD2SI = 126 +X86_INS_CVTTSS2SI = 127 +X86_INS_CWD = 128 +X86_INS_CWDE = 129 +X86_INS_DAA = 130 +X86_INS_DAS = 131 +X86_INS_DATA16 = 132 +X86_INS_DEC = 133 +X86_INS_DIV = 134 +X86_INS_DIVPD = 135 +X86_INS_DIVPS = 136 +X86_INS_FDIVR = 137 +X86_INS_FIDIVR = 138 +X86_INS_FDIVRP = 139 +X86_INS_DIVSD = 140 +X86_INS_DIVSS = 141 +X86_INS_FDIV = 142 +X86_INS_FIDIV = 143 +X86_INS_FDIVP = 144 +X86_INS_DPPD = 145 +X86_INS_DPPS = 146 +X86_INS_RET = 147 +X86_INS_ENCLS = 148 +X86_INS_ENCLU = 149 +X86_INS_ENTER = 150 +X86_INS_EXTRACTPS = 151 +X86_INS_EXTRQ = 152 +X86_INS_F2XM1 = 153 +X86_INS_LCALL = 154 +X86_INS_LJMP = 155 +X86_INS_FBLD = 156 +X86_INS_FBSTP = 157 +X86_INS_FCOMPP = 158 +X86_INS_FDECSTP = 159 +X86_INS_FEMMS = 160 +X86_INS_FFREE = 161 +X86_INS_FICOM = 162 +X86_INS_FICOMP = 163 +X86_INS_FINCSTP = 164 +X86_INS_FLDCW = 165 +X86_INS_FLDENV = 166 +X86_INS_FLDL2E = 167 +X86_INS_FLDL2T = 168 +X86_INS_FLDLG2 = 169 +X86_INS_FLDLN2 = 170 +X86_INS_FLDPI = 171 +X86_INS_FNCLEX = 172 +X86_INS_FNINIT = 173 +X86_INS_FNOP = 174 +X86_INS_FNSTCW = 175 +X86_INS_FNSTSW = 176 +X86_INS_FPATAN = 177 +X86_INS_FPREM = 178 +X86_INS_FPREM1 = 179 +X86_INS_FPTAN = 180 +X86_INS_FFREEP = 181 +X86_INS_FRNDINT = 182 +X86_INS_FRSTOR = 183 +X86_INS_FNSAVE = 184 +X86_INS_FSCALE = 185 +X86_INS_FSETPM = 186 +X86_INS_FSINCOS = 187 +X86_INS_FNSTENV = 188 +X86_INS_FXAM = 189 +X86_INS_FXRSTOR = 190 +X86_INS_FXRSTOR64 = 191 +X86_INS_FXSAVE = 192 +X86_INS_FXSAVE64 = 193 +X86_INS_FXTRACT = 194 +X86_INS_FYL2X = 195 +X86_INS_FYL2XP1 = 196 +X86_INS_MOVAPD = 197 +X86_INS_MOVAPS = 198 +X86_INS_ORPD = 199 +X86_INS_ORPS = 200 +X86_INS_VMOVAPD = 201 +X86_INS_VMOVAPS = 202 +X86_INS_XORPD = 203 +X86_INS_XORPS = 204 +X86_INS_GETSEC = 205 +X86_INS_HADDPD = 206 +X86_INS_HADDPS = 207 +X86_INS_HLT = 208 +X86_INS_HSUBPD = 209 +X86_INS_HSUBPS = 210 +X86_INS_IDIV = 211 +X86_INS_FILD = 212 +X86_INS_IMUL = 213 +X86_INS_IN = 214 +X86_INS_INC = 215 +X86_INS_INSB = 216 +X86_INS_INSERTPS = 217 +X86_INS_INSERTQ = 218 +X86_INS_INSD = 219 +X86_INS_INSW = 220 +X86_INS_INT = 221 +X86_INS_INT1 = 222 +X86_INS_INT3 = 223 +X86_INS_INTO = 224 +X86_INS_INVD = 225 +X86_INS_INVEPT = 226 +X86_INS_INVLPG = 227 +X86_INS_INVLPGA = 228 +X86_INS_INVPCID = 229 +X86_INS_INVVPID = 230 +X86_INS_IRET = 231 +X86_INS_IRETD = 232 +X86_INS_IRETQ = 233 +X86_INS_FISTTP = 234 +X86_INS_FIST = 235 +X86_INS_FISTP = 236 +X86_INS_UCOMISD = 237 +X86_INS_UCOMISS = 238 +X86_INS_VCOMISD = 239 +X86_INS_VCOMISS = 240 +X86_INS_VCVTSD2SS = 241 +X86_INS_VCVTSI2SD = 242 +X86_INS_VCVTSI2SS = 243 +X86_INS_VCVTSS2SD = 244 +X86_INS_VCVTTSD2SI = 245 +X86_INS_VCVTTSD2USI = 246 +X86_INS_VCVTTSS2SI = 247 +X86_INS_VCVTTSS2USI = 248 +X86_INS_VCVTUSI2SD = 249 +X86_INS_VCVTUSI2SS = 250 +X86_INS_VUCOMISD = 251 +X86_INS_VUCOMISS = 252 +X86_INS_JAE = 253 +X86_INS_JA = 254 +X86_INS_JBE = 255 +X86_INS_JB = 256 +X86_INS_JCXZ = 257 +X86_INS_JECXZ = 258 +X86_INS_JE = 259 +X86_INS_JGE = 260 +X86_INS_JG = 261 +X86_INS_JLE = 262 +X86_INS_JL = 263 +X86_INS_JMP = 264 +X86_INS_JNE = 265 +X86_INS_JNO = 266 +X86_INS_JNP = 267 +X86_INS_JNS = 268 +X86_INS_JO = 269 +X86_INS_JP = 270 +X86_INS_JRCXZ = 271 +X86_INS_JS = 272 +X86_INS_KANDB = 273 +X86_INS_KANDD = 274 +X86_INS_KANDNB = 275 +X86_INS_KANDND = 276 +X86_INS_KANDNQ = 277 +X86_INS_KANDNW = 278 +X86_INS_KANDQ = 279 +X86_INS_KANDW = 280 +X86_INS_KMOVB = 281 +X86_INS_KMOVD = 282 +X86_INS_KMOVQ = 283 +X86_INS_KMOVW = 284 +X86_INS_KNOTB = 285 +X86_INS_KNOTD = 286 +X86_INS_KNOTQ = 287 +X86_INS_KNOTW = 288 +X86_INS_KORB = 289 +X86_INS_KORD = 290 +X86_INS_KORQ = 291 +X86_INS_KORTESTB = 292 +X86_INS_KORTESTD = 293 +X86_INS_KORTESTQ = 294 +X86_INS_KORTESTW = 295 +X86_INS_KORW = 296 +X86_INS_KSHIFTLB = 297 +X86_INS_KSHIFTLD = 298 +X86_INS_KSHIFTLQ = 299 +X86_INS_KSHIFTLW = 300 +X86_INS_KSHIFTRB = 301 +X86_INS_KSHIFTRD = 302 +X86_INS_KSHIFTRQ = 303 +X86_INS_KSHIFTRW = 304 +X86_INS_KUNPCKBW = 305 +X86_INS_KXNORB = 306 +X86_INS_KXNORD = 307 +X86_INS_KXNORQ = 308 +X86_INS_KXNORW = 309 +X86_INS_KXORB = 310 +X86_INS_KXORD = 311 +X86_INS_KXORQ = 312 +X86_INS_KXORW = 313 +X86_INS_LAHF = 314 +X86_INS_LAR = 315 +X86_INS_LDDQU = 316 +X86_INS_LDMXCSR = 317 +X86_INS_LDS = 318 +X86_INS_FLDZ = 319 +X86_INS_FLD1 = 320 +X86_INS_FLD = 321 +X86_INS_LEA = 322 +X86_INS_LEAVE = 323 +X86_INS_LES = 324 +X86_INS_LFENCE = 325 +X86_INS_LFS = 326 +X86_INS_LGDT = 327 +X86_INS_LGS = 328 +X86_INS_LIDT = 329 +X86_INS_LLDT = 330 +X86_INS_LMSW = 331 +X86_INS_OR = 332 +X86_INS_SUB = 333 +X86_INS_XOR = 334 +X86_INS_LODSB = 335 +X86_INS_LODSD = 336 +X86_INS_LODSQ = 337 +X86_INS_LODSW = 338 +X86_INS_LOOP = 339 +X86_INS_LOOPE = 340 +X86_INS_LOOPNE = 341 +X86_INS_RETF = 342 +X86_INS_RETFQ = 343 +X86_INS_LSL = 344 +X86_INS_LSS = 345 +X86_INS_LTR = 346 +X86_INS_XADD = 347 +X86_INS_LZCNT = 348 +X86_INS_MASKMOVDQU = 349 +X86_INS_MAXPD = 350 +X86_INS_MAXPS = 351 +X86_INS_MAXSD = 352 +X86_INS_MAXSS = 353 +X86_INS_MFENCE = 354 +X86_INS_MINPD = 355 +X86_INS_MINPS = 356 +X86_INS_MINSD = 357 +X86_INS_MINSS = 358 +X86_INS_CVTPD2PI = 359 +X86_INS_CVTPI2PD = 360 +X86_INS_CVTPI2PS = 361 +X86_INS_CVTPS2PI = 362 +X86_INS_CVTTPD2PI = 363 +X86_INS_CVTTPS2PI = 364 +X86_INS_EMMS = 365 +X86_INS_MASKMOVQ = 366 +X86_INS_MOVD = 367 +X86_INS_MOVDQ2Q = 368 +X86_INS_MOVNTQ = 369 +X86_INS_MOVQ2DQ = 370 +X86_INS_MOVQ = 371 +X86_INS_PABSB = 372 +X86_INS_PABSD = 373 +X86_INS_PABSW = 374 +X86_INS_PACKSSDW = 375 +X86_INS_PACKSSWB = 376 +X86_INS_PACKUSWB = 377 +X86_INS_PADDB = 378 +X86_INS_PADDD = 379 +X86_INS_PADDQ = 380 +X86_INS_PADDSB = 381 +X86_INS_PADDSW = 382 +X86_INS_PADDUSB = 383 +X86_INS_PADDUSW = 384 +X86_INS_PADDW = 385 +X86_INS_PALIGNR = 386 +X86_INS_PANDN = 387 +X86_INS_PAND = 388 +X86_INS_PAVGB = 389 +X86_INS_PAVGW = 390 +X86_INS_PCMPEQB = 391 +X86_INS_PCMPEQD = 392 +X86_INS_PCMPEQW = 393 +X86_INS_PCMPGTB = 394 +X86_INS_PCMPGTD = 395 +X86_INS_PCMPGTW = 396 +X86_INS_PEXTRW = 397 +X86_INS_PHADDSW = 398 +X86_INS_PHADDW = 399 +X86_INS_PHADDD = 400 +X86_INS_PHSUBD = 401 +X86_INS_PHSUBSW = 402 +X86_INS_PHSUBW = 403 +X86_INS_PINSRW = 404 +X86_INS_PMADDUBSW = 405 +X86_INS_PMADDWD = 406 +X86_INS_PMAXSW = 407 +X86_INS_PMAXUB = 408 +X86_INS_PMINSW = 409 +X86_INS_PMINUB = 410 +X86_INS_PMOVMSKB = 411 +X86_INS_PMULHRSW = 412 +X86_INS_PMULHUW = 413 +X86_INS_PMULHW = 414 +X86_INS_PMULLW = 415 +X86_INS_PMULUDQ = 416 +X86_INS_POR = 417 +X86_INS_PSADBW = 418 +X86_INS_PSHUFB = 419 +X86_INS_PSHUFW = 420 +X86_INS_PSIGNB = 421 +X86_INS_PSIGND = 422 +X86_INS_PSIGNW = 423 +X86_INS_PSLLD = 424 +X86_INS_PSLLQ = 425 +X86_INS_PSLLW = 426 +X86_INS_PSRAD = 427 +X86_INS_PSRAW = 428 +X86_INS_PSRLD = 429 +X86_INS_PSRLQ = 430 +X86_INS_PSRLW = 431 +X86_INS_PSUBB = 432 +X86_INS_PSUBD = 433 +X86_INS_PSUBQ = 434 +X86_INS_PSUBSB = 435 +X86_INS_PSUBSW = 436 +X86_INS_PSUBUSB = 437 +X86_INS_PSUBUSW = 438 +X86_INS_PSUBW = 439 +X86_INS_PUNPCKHBW = 440 +X86_INS_PUNPCKHDQ = 441 +X86_INS_PUNPCKHWD = 442 +X86_INS_PUNPCKLBW = 443 +X86_INS_PUNPCKLDQ = 444 +X86_INS_PUNPCKLWD = 445 +X86_INS_PXOR = 446 +X86_INS_MONITOR = 447 +X86_INS_MONTMUL = 448 +X86_INS_MOV = 449 +X86_INS_MOVABS = 450 +X86_INS_MOVBE = 451 +X86_INS_MOVDDUP = 452 +X86_INS_MOVDQA = 453 +X86_INS_MOVDQU = 454 +X86_INS_MOVHLPS = 455 +X86_INS_MOVHPD = 456 +X86_INS_MOVHPS = 457 +X86_INS_MOVLHPS = 458 +X86_INS_MOVLPD = 459 +X86_INS_MOVLPS = 460 +X86_INS_MOVMSKPD = 461 +X86_INS_MOVMSKPS = 462 +X86_INS_MOVNTDQA = 463 +X86_INS_MOVNTDQ = 464 +X86_INS_MOVNTI = 465 +X86_INS_MOVNTPD = 466 +X86_INS_MOVNTPS = 467 +X86_INS_MOVNTSD = 468 +X86_INS_MOVNTSS = 469 +X86_INS_MOVSB = 470 +X86_INS_MOVSD = 471 +X86_INS_MOVSHDUP = 472 +X86_INS_MOVSLDUP = 473 +X86_INS_MOVSQ = 474 +X86_INS_MOVSS = 475 +X86_INS_MOVSW = 476 +X86_INS_MOVSX = 477 +X86_INS_MOVSXD = 478 +X86_INS_MOVUPD = 479 +X86_INS_MOVUPS = 480 +X86_INS_MOVZX = 481 +X86_INS_MPSADBW = 482 +X86_INS_MUL = 483 +X86_INS_MULPD = 484 +X86_INS_MULPS = 485 +X86_INS_MULSD = 486 +X86_INS_MULSS = 487 +X86_INS_MULX = 488 +X86_INS_FMUL = 489 +X86_INS_FIMUL = 490 +X86_INS_FMULP = 491 +X86_INS_MWAIT = 492 +X86_INS_NEG = 493 +X86_INS_NOP = 494 +X86_INS_NOT = 495 +X86_INS_OUT = 496 +X86_INS_OUTSB = 497 +X86_INS_OUTSD = 498 +X86_INS_OUTSW = 499 +X86_INS_PACKUSDW = 500 +X86_INS_PAUSE = 501 +X86_INS_PAVGUSB = 502 +X86_INS_PBLENDVB = 503 +X86_INS_PBLENDW = 504 +X86_INS_PCLMULQDQ = 505 +X86_INS_PCMPEQQ = 506 +X86_INS_PCMPESTRI = 507 +X86_INS_PCMPESTRM = 508 +X86_INS_PCMPGTQ = 509 +X86_INS_PCMPISTRI = 510 +X86_INS_PCMPISTRM = 511 +X86_INS_PCOMMIT = 512 +X86_INS_PDEP = 513 +X86_INS_PEXT = 514 +X86_INS_PEXTRB = 515 +X86_INS_PEXTRD = 516 +X86_INS_PEXTRQ = 517 +X86_INS_PF2ID = 518 +X86_INS_PF2IW = 519 +X86_INS_PFACC = 520 +X86_INS_PFADD = 521 +X86_INS_PFCMPEQ = 522 +X86_INS_PFCMPGE = 523 +X86_INS_PFCMPGT = 524 +X86_INS_PFMAX = 525 +X86_INS_PFMIN = 526 +X86_INS_PFMUL = 527 +X86_INS_PFNACC = 528 +X86_INS_PFPNACC = 529 +X86_INS_PFRCPIT1 = 530 +X86_INS_PFRCPIT2 = 531 +X86_INS_PFRCP = 532 +X86_INS_PFRSQIT1 = 533 +X86_INS_PFRSQRT = 534 +X86_INS_PFSUBR = 535 +X86_INS_PFSUB = 536 +X86_INS_PHMINPOSUW = 537 +X86_INS_PI2FD = 538 +X86_INS_PI2FW = 539 +X86_INS_PINSRB = 540 +X86_INS_PINSRD = 541 +X86_INS_PINSRQ = 542 +X86_INS_PMAXSB = 543 +X86_INS_PMAXSD = 544 +X86_INS_PMAXUD = 545 +X86_INS_PMAXUW = 546 +X86_INS_PMINSB = 547 +X86_INS_PMINSD = 548 +X86_INS_PMINUD = 549 +X86_INS_PMINUW = 550 +X86_INS_PMOVSXBD = 551 +X86_INS_PMOVSXBQ = 552 +X86_INS_PMOVSXBW = 553 +X86_INS_PMOVSXDQ = 554 +X86_INS_PMOVSXWD = 555 +X86_INS_PMOVSXWQ = 556 +X86_INS_PMOVZXBD = 557 +X86_INS_PMOVZXBQ = 558 +X86_INS_PMOVZXBW = 559 +X86_INS_PMOVZXDQ = 560 +X86_INS_PMOVZXWD = 561 +X86_INS_PMOVZXWQ = 562 +X86_INS_PMULDQ = 563 +X86_INS_PMULHRW = 564 +X86_INS_PMULLD = 565 +X86_INS_POP = 566 +X86_INS_POPAW = 567 +X86_INS_POPAL = 568 +X86_INS_POPCNT = 569 +X86_INS_POPF = 570 +X86_INS_POPFD = 571 +X86_INS_POPFQ = 572 +X86_INS_PREFETCH = 573 +X86_INS_PREFETCHNTA = 574 +X86_INS_PREFETCHT0 = 575 +X86_INS_PREFETCHT1 = 576 +X86_INS_PREFETCHT2 = 577 +X86_INS_PREFETCHW = 578 +X86_INS_PSHUFD = 579 +X86_INS_PSHUFHW = 580 +X86_INS_PSHUFLW = 581 +X86_INS_PSLLDQ = 582 +X86_INS_PSRLDQ = 583 +X86_INS_PSWAPD = 584 +X86_INS_PTEST = 585 +X86_INS_PUNPCKHQDQ = 586 +X86_INS_PUNPCKLQDQ = 587 +X86_INS_PUSH = 588 +X86_INS_PUSHAW = 589 +X86_INS_PUSHAL = 590 +X86_INS_PUSHF = 591 +X86_INS_PUSHFD = 592 +X86_INS_PUSHFQ = 593 +X86_INS_RCL = 594 +X86_INS_RCPPS = 595 +X86_INS_RCPSS = 596 +X86_INS_RCR = 597 +X86_INS_RDFSBASE = 598 +X86_INS_RDGSBASE = 599 +X86_INS_RDMSR = 600 +X86_INS_RDPMC = 601 +X86_INS_RDRAND = 602 +X86_INS_RDSEED = 603 +X86_INS_RDTSC = 604 +X86_INS_RDTSCP = 605 +X86_INS_ROL = 606 +X86_INS_ROR = 607 +X86_INS_RORX = 608 +X86_INS_ROUNDPD = 609 +X86_INS_ROUNDPS = 610 +X86_INS_ROUNDSD = 611 +X86_INS_ROUNDSS = 612 +X86_INS_RSM = 613 +X86_INS_RSQRTPS = 614 +X86_INS_RSQRTSS = 615 +X86_INS_SAHF = 616 +X86_INS_SAL = 617 +X86_INS_SALC = 618 +X86_INS_SAR = 619 +X86_INS_SARX = 620 +X86_INS_SBB = 621 +X86_INS_SCASB = 622 +X86_INS_SCASD = 623 +X86_INS_SCASQ = 624 +X86_INS_SCASW = 625 +X86_INS_SETAE = 626 +X86_INS_SETA = 627 +X86_INS_SETBE = 628 +X86_INS_SETB = 629 +X86_INS_SETE = 630 +X86_INS_SETGE = 631 +X86_INS_SETG = 632 +X86_INS_SETLE = 633 +X86_INS_SETL = 634 +X86_INS_SETNE = 635 +X86_INS_SETNO = 636 +X86_INS_SETNP = 637 +X86_INS_SETNS = 638 +X86_INS_SETO = 639 +X86_INS_SETP = 640 +X86_INS_SETS = 641 +X86_INS_SFENCE = 642 +X86_INS_SGDT = 643 +X86_INS_SHA1MSG1 = 644 +X86_INS_SHA1MSG2 = 645 +X86_INS_SHA1NEXTE = 646 +X86_INS_SHA1RNDS4 = 647 +X86_INS_SHA256MSG1 = 648 +X86_INS_SHA256MSG2 = 649 +X86_INS_SHA256RNDS2 = 650 +X86_INS_SHL = 651 +X86_INS_SHLD = 652 +X86_INS_SHLX = 653 +X86_INS_SHR = 654 +X86_INS_SHRD = 655 +X86_INS_SHRX = 656 +X86_INS_SHUFPD = 657 +X86_INS_SHUFPS = 658 +X86_INS_SIDT = 659 +X86_INS_FSIN = 660 +X86_INS_SKINIT = 661 +X86_INS_SLDT = 662 +X86_INS_SMSW = 663 +X86_INS_SQRTPD = 664 +X86_INS_SQRTPS = 665 +X86_INS_SQRTSD = 666 +X86_INS_SQRTSS = 667 +X86_INS_FSQRT = 668 +X86_INS_STAC = 669 +X86_INS_STC = 670 +X86_INS_STD = 671 +X86_INS_STGI = 672 +X86_INS_STI = 673 +X86_INS_STMXCSR = 674 +X86_INS_STOSB = 675 +X86_INS_STOSD = 676 +X86_INS_STOSQ = 677 +X86_INS_STOSW = 678 +X86_INS_STR = 679 +X86_INS_FST = 680 +X86_INS_FSTP = 681 +X86_INS_FSTPNCE = 682 +X86_INS_FXCH = 683 +X86_INS_SUBPD = 684 +X86_INS_SUBPS = 685 +X86_INS_FSUBR = 686 +X86_INS_FISUBR = 687 +X86_INS_FSUBRP = 688 +X86_INS_SUBSD = 689 +X86_INS_SUBSS = 690 +X86_INS_FSUB = 691 +X86_INS_FISUB = 692 +X86_INS_FSUBP = 693 +X86_INS_SWAPGS = 694 +X86_INS_SYSCALL = 695 +X86_INS_SYSENTER = 696 +X86_INS_SYSEXIT = 697 +X86_INS_SYSRET = 698 +X86_INS_T1MSKC = 699 +X86_INS_TEST = 700 +X86_INS_UD2 = 701 +X86_INS_FTST = 702 +X86_INS_TZCNT = 703 +X86_INS_TZMSK = 704 +X86_INS_FUCOMIP = 705 +X86_INS_FUCOMI = 706 +X86_INS_FUCOMPP = 707 +X86_INS_FUCOMP = 708 +X86_INS_FUCOM = 709 +X86_INS_UD2B = 710 +X86_INS_UNPCKHPD = 711 +X86_INS_UNPCKHPS = 712 +X86_INS_UNPCKLPD = 713 +X86_INS_UNPCKLPS = 714 +X86_INS_VADDPD = 715 +X86_INS_VADDPS = 716 +X86_INS_VADDSD = 717 +X86_INS_VADDSS = 718 +X86_INS_VADDSUBPD = 719 +X86_INS_VADDSUBPS = 720 +X86_INS_VAESDECLAST = 721 +X86_INS_VAESDEC = 722 +X86_INS_VAESENCLAST = 723 +X86_INS_VAESENC = 724 +X86_INS_VAESIMC = 725 +X86_INS_VAESKEYGENASSIST = 726 +X86_INS_VALIGND = 727 +X86_INS_VALIGNQ = 728 +X86_INS_VANDNPD = 729 +X86_INS_VANDNPS = 730 +X86_INS_VANDPD = 731 +X86_INS_VANDPS = 732 +X86_INS_VBLENDMPD = 733 +X86_INS_VBLENDMPS = 734 +X86_INS_VBLENDPD = 735 +X86_INS_VBLENDPS = 736 +X86_INS_VBLENDVPD = 737 +X86_INS_VBLENDVPS = 738 +X86_INS_VBROADCASTF128 = 739 +X86_INS_VBROADCASTI32X4 = 740 +X86_INS_VBROADCASTI64X4 = 741 +X86_INS_VBROADCASTSD = 742 +X86_INS_VBROADCASTSS = 743 +X86_INS_VCOMPRESSPD = 744 +X86_INS_VCOMPRESSPS = 745 +X86_INS_VCVTDQ2PD = 746 +X86_INS_VCVTDQ2PS = 747 +X86_INS_VCVTPD2DQX = 748 +X86_INS_VCVTPD2DQ = 749 +X86_INS_VCVTPD2PSX = 750 +X86_INS_VCVTPD2PS = 751 +X86_INS_VCVTPD2UDQ = 752 +X86_INS_VCVTPH2PS = 753 +X86_INS_VCVTPS2DQ = 754 +X86_INS_VCVTPS2PD = 755 +X86_INS_VCVTPS2PH = 756 +X86_INS_VCVTPS2UDQ = 757 +X86_INS_VCVTSD2SI = 758 +X86_INS_VCVTSD2USI = 759 +X86_INS_VCVTSS2SI = 760 +X86_INS_VCVTSS2USI = 761 +X86_INS_VCVTTPD2DQX = 762 +X86_INS_VCVTTPD2DQ = 763 +X86_INS_VCVTTPD2UDQ = 764 +X86_INS_VCVTTPS2DQ = 765 +X86_INS_VCVTTPS2UDQ = 766 +X86_INS_VCVTUDQ2PD = 767 +X86_INS_VCVTUDQ2PS = 768 +X86_INS_VDIVPD = 769 +X86_INS_VDIVPS = 770 +X86_INS_VDIVSD = 771 +X86_INS_VDIVSS = 772 +X86_INS_VDPPD = 773 +X86_INS_VDPPS = 774 +X86_INS_VERR = 775 +X86_INS_VERW = 776 +X86_INS_VEXP2PD = 777 +X86_INS_VEXP2PS = 778 +X86_INS_VEXPANDPD = 779 +X86_INS_VEXPANDPS = 780 +X86_INS_VEXTRACTF128 = 781 +X86_INS_VEXTRACTF32X4 = 782 +X86_INS_VEXTRACTF64X4 = 783 +X86_INS_VEXTRACTI128 = 784 +X86_INS_VEXTRACTI32X4 = 785 +X86_INS_VEXTRACTI64X4 = 786 +X86_INS_VEXTRACTPS = 787 +X86_INS_VFMADD132PD = 788 +X86_INS_VFMADD132PS = 789 +X86_INS_VFMADDPD = 790 +X86_INS_VFMADD213PD = 791 +X86_INS_VFMADD231PD = 792 +X86_INS_VFMADDPS = 793 +X86_INS_VFMADD213PS = 794 +X86_INS_VFMADD231PS = 795 +X86_INS_VFMADDSD = 796 +X86_INS_VFMADD213SD = 797 +X86_INS_VFMADD132SD = 798 +X86_INS_VFMADD231SD = 799 +X86_INS_VFMADDSS = 800 +X86_INS_VFMADD213SS = 801 +X86_INS_VFMADD132SS = 802 +X86_INS_VFMADD231SS = 803 +X86_INS_VFMADDSUB132PD = 804 +X86_INS_VFMADDSUB132PS = 805 +X86_INS_VFMADDSUBPD = 806 +X86_INS_VFMADDSUB213PD = 807 +X86_INS_VFMADDSUB231PD = 808 +X86_INS_VFMADDSUBPS = 809 +X86_INS_VFMADDSUB213PS = 810 +X86_INS_VFMADDSUB231PS = 811 +X86_INS_VFMSUB132PD = 812 +X86_INS_VFMSUB132PS = 813 +X86_INS_VFMSUBADD132PD = 814 +X86_INS_VFMSUBADD132PS = 815 +X86_INS_VFMSUBADDPD = 816 +X86_INS_VFMSUBADD213PD = 817 +X86_INS_VFMSUBADD231PD = 818 +X86_INS_VFMSUBADDPS = 819 +X86_INS_VFMSUBADD213PS = 820 +X86_INS_VFMSUBADD231PS = 821 +X86_INS_VFMSUBPD = 822 +X86_INS_VFMSUB213PD = 823 +X86_INS_VFMSUB231PD = 824 +X86_INS_VFMSUBPS = 825 +X86_INS_VFMSUB213PS = 826 +X86_INS_VFMSUB231PS = 827 +X86_INS_VFMSUBSD = 828 +X86_INS_VFMSUB213SD = 829 +X86_INS_VFMSUB132SD = 830 +X86_INS_VFMSUB231SD = 831 +X86_INS_VFMSUBSS = 832 +X86_INS_VFMSUB213SS = 833 +X86_INS_VFMSUB132SS = 834 +X86_INS_VFMSUB231SS = 835 +X86_INS_VFNMADD132PD = 836 +X86_INS_VFNMADD132PS = 837 +X86_INS_VFNMADDPD = 838 +X86_INS_VFNMADD213PD = 839 +X86_INS_VFNMADD231PD = 840 +X86_INS_VFNMADDPS = 841 +X86_INS_VFNMADD213PS = 842 +X86_INS_VFNMADD231PS = 843 +X86_INS_VFNMADDSD = 844 +X86_INS_VFNMADD213SD = 845 +X86_INS_VFNMADD132SD = 846 +X86_INS_VFNMADD231SD = 847 +X86_INS_VFNMADDSS = 848 +X86_INS_VFNMADD213SS = 849 +X86_INS_VFNMADD132SS = 850 +X86_INS_VFNMADD231SS = 851 +X86_INS_VFNMSUB132PD = 852 +X86_INS_VFNMSUB132PS = 853 +X86_INS_VFNMSUBPD = 854 +X86_INS_VFNMSUB213PD = 855 +X86_INS_VFNMSUB231PD = 856 +X86_INS_VFNMSUBPS = 857 +X86_INS_VFNMSUB213PS = 858 +X86_INS_VFNMSUB231PS = 859 +X86_INS_VFNMSUBSD = 860 +X86_INS_VFNMSUB213SD = 861 +X86_INS_VFNMSUB132SD = 862 +X86_INS_VFNMSUB231SD = 863 +X86_INS_VFNMSUBSS = 864 +X86_INS_VFNMSUB213SS = 865 +X86_INS_VFNMSUB132SS = 866 +X86_INS_VFNMSUB231SS = 867 +X86_INS_VFRCZPD = 868 +X86_INS_VFRCZPS = 869 +X86_INS_VFRCZSD = 870 +X86_INS_VFRCZSS = 871 +X86_INS_VORPD = 872 +X86_INS_VORPS = 873 +X86_INS_VXORPD = 874 +X86_INS_VXORPS = 875 +X86_INS_VGATHERDPD = 876 +X86_INS_VGATHERDPS = 877 +X86_INS_VGATHERPF0DPD = 878 +X86_INS_VGATHERPF0DPS = 879 +X86_INS_VGATHERPF0QPD = 880 +X86_INS_VGATHERPF0QPS = 881 +X86_INS_VGATHERPF1DPD = 882 +X86_INS_VGATHERPF1DPS = 883 +X86_INS_VGATHERPF1QPD = 884 +X86_INS_VGATHERPF1QPS = 885 +X86_INS_VGATHERQPD = 886 +X86_INS_VGATHERQPS = 887 +X86_INS_VHADDPD = 888 +X86_INS_VHADDPS = 889 +X86_INS_VHSUBPD = 890 +X86_INS_VHSUBPS = 891 +X86_INS_VINSERTF128 = 892 +X86_INS_VINSERTF32X4 = 893 +X86_INS_VINSERTF32X8 = 894 +X86_INS_VINSERTF64X2 = 895 +X86_INS_VINSERTF64X4 = 896 +X86_INS_VINSERTI128 = 897 +X86_INS_VINSERTI32X4 = 898 +X86_INS_VINSERTI32X8 = 899 +X86_INS_VINSERTI64X2 = 900 +X86_INS_VINSERTI64X4 = 901 +X86_INS_VINSERTPS = 902 +X86_INS_VLDDQU = 903 +X86_INS_VLDMXCSR = 904 +X86_INS_VMASKMOVDQU = 905 +X86_INS_VMASKMOVPD = 906 +X86_INS_VMASKMOVPS = 907 +X86_INS_VMAXPD = 908 +X86_INS_VMAXPS = 909 +X86_INS_VMAXSD = 910 +X86_INS_VMAXSS = 911 +X86_INS_VMCALL = 912 +X86_INS_VMCLEAR = 913 +X86_INS_VMFUNC = 914 +X86_INS_VMINPD = 915 +X86_INS_VMINPS = 916 +X86_INS_VMINSD = 917 +X86_INS_VMINSS = 918 +X86_INS_VMLAUNCH = 919 +X86_INS_VMLOAD = 920 +X86_INS_VMMCALL = 921 +X86_INS_VMOVQ = 922 +X86_INS_VMOVDDUP = 923 +X86_INS_VMOVD = 924 +X86_INS_VMOVDQA32 = 925 +X86_INS_VMOVDQA64 = 926 +X86_INS_VMOVDQA = 927 +X86_INS_VMOVDQU16 = 928 +X86_INS_VMOVDQU32 = 929 +X86_INS_VMOVDQU64 = 930 +X86_INS_VMOVDQU8 = 931 +X86_INS_VMOVDQU = 932 +X86_INS_VMOVHLPS = 933 +X86_INS_VMOVHPD = 934 +X86_INS_VMOVHPS = 935 +X86_INS_VMOVLHPS = 936 +X86_INS_VMOVLPD = 937 +X86_INS_VMOVLPS = 938 +X86_INS_VMOVMSKPD = 939 +X86_INS_VMOVMSKPS = 940 +X86_INS_VMOVNTDQA = 941 +X86_INS_VMOVNTDQ = 942 +X86_INS_VMOVNTPD = 943 +X86_INS_VMOVNTPS = 944 +X86_INS_VMOVSD = 945 +X86_INS_VMOVSHDUP = 946 +X86_INS_VMOVSLDUP = 947 +X86_INS_VMOVSS = 948 +X86_INS_VMOVUPD = 949 +X86_INS_VMOVUPS = 950 +X86_INS_VMPSADBW = 951 +X86_INS_VMPTRLD = 952 +X86_INS_VMPTRST = 953 +X86_INS_VMREAD = 954 +X86_INS_VMRESUME = 955 +X86_INS_VMRUN = 956 +X86_INS_VMSAVE = 957 +X86_INS_VMULPD = 958 +X86_INS_VMULPS = 959 +X86_INS_VMULSD = 960 +X86_INS_VMULSS = 961 +X86_INS_VMWRITE = 962 +X86_INS_VMXOFF = 963 +X86_INS_VMXON = 964 +X86_INS_VPABSB = 965 +X86_INS_VPABSD = 966 +X86_INS_VPABSQ = 967 +X86_INS_VPABSW = 968 +X86_INS_VPACKSSDW = 969 +X86_INS_VPACKSSWB = 970 +X86_INS_VPACKUSDW = 971 +X86_INS_VPACKUSWB = 972 +X86_INS_VPADDB = 973 +X86_INS_VPADDD = 974 +X86_INS_VPADDQ = 975 +X86_INS_VPADDSB = 976 +X86_INS_VPADDSW = 977 +X86_INS_VPADDUSB = 978 +X86_INS_VPADDUSW = 979 +X86_INS_VPADDW = 980 +X86_INS_VPALIGNR = 981 +X86_INS_VPANDD = 982 +X86_INS_VPANDND = 983 +X86_INS_VPANDNQ = 984 +X86_INS_VPANDN = 985 +X86_INS_VPANDQ = 986 +X86_INS_VPAND = 987 +X86_INS_VPAVGB = 988 +X86_INS_VPAVGW = 989 +X86_INS_VPBLENDD = 990 +X86_INS_VPBLENDMB = 991 +X86_INS_VPBLENDMD = 992 +X86_INS_VPBLENDMQ = 993 +X86_INS_VPBLENDMW = 994 +X86_INS_VPBLENDVB = 995 +X86_INS_VPBLENDW = 996 +X86_INS_VPBROADCASTB = 997 +X86_INS_VPBROADCASTD = 998 +X86_INS_VPBROADCASTMB2Q = 999 +X86_INS_VPBROADCASTMW2D = 1000 +X86_INS_VPBROADCASTQ = 1001 +X86_INS_VPBROADCASTW = 1002 +X86_INS_VPCLMULQDQ = 1003 +X86_INS_VPCMOV = 1004 +X86_INS_VPCMPB = 1005 +X86_INS_VPCMPD = 1006 +X86_INS_VPCMPEQB = 1007 +X86_INS_VPCMPEQD = 1008 +X86_INS_VPCMPEQQ = 1009 +X86_INS_VPCMPEQW = 1010 +X86_INS_VPCMPESTRI = 1011 +X86_INS_VPCMPESTRM = 1012 +X86_INS_VPCMPGTB = 1013 +X86_INS_VPCMPGTD = 1014 +X86_INS_VPCMPGTQ = 1015 +X86_INS_VPCMPGTW = 1016 +X86_INS_VPCMPISTRI = 1017 +X86_INS_VPCMPISTRM = 1018 +X86_INS_VPCMPQ = 1019 +X86_INS_VPCMPUB = 1020 +X86_INS_VPCMPUD = 1021 +X86_INS_VPCMPUQ = 1022 +X86_INS_VPCMPUW = 1023 +X86_INS_VPCMPW = 1024 +X86_INS_VPCOMB = 1025 +X86_INS_VPCOMD = 1026 +X86_INS_VPCOMPRESSD = 1027 +X86_INS_VPCOMPRESSQ = 1028 +X86_INS_VPCOMQ = 1029 +X86_INS_VPCOMUB = 1030 +X86_INS_VPCOMUD = 1031 +X86_INS_VPCOMUQ = 1032 +X86_INS_VPCOMUW = 1033 +X86_INS_VPCOMW = 1034 +X86_INS_VPCONFLICTD = 1035 +X86_INS_VPCONFLICTQ = 1036 +X86_INS_VPERM2F128 = 1037 +X86_INS_VPERM2I128 = 1038 +X86_INS_VPERMD = 1039 +X86_INS_VPERMI2D = 1040 +X86_INS_VPERMI2PD = 1041 +X86_INS_VPERMI2PS = 1042 +X86_INS_VPERMI2Q = 1043 +X86_INS_VPERMIL2PD = 1044 +X86_INS_VPERMIL2PS = 1045 +X86_INS_VPERMILPD = 1046 +X86_INS_VPERMILPS = 1047 +X86_INS_VPERMPD = 1048 +X86_INS_VPERMPS = 1049 +X86_INS_VPERMQ = 1050 +X86_INS_VPERMT2D = 1051 +X86_INS_VPERMT2PD = 1052 +X86_INS_VPERMT2PS = 1053 +X86_INS_VPERMT2Q = 1054 +X86_INS_VPEXPANDD = 1055 +X86_INS_VPEXPANDQ = 1056 +X86_INS_VPEXTRB = 1057 +X86_INS_VPEXTRD = 1058 +X86_INS_VPEXTRQ = 1059 +X86_INS_VPEXTRW = 1060 +X86_INS_VPGATHERDD = 1061 +X86_INS_VPGATHERDQ = 1062 +X86_INS_VPGATHERQD = 1063 +X86_INS_VPGATHERQQ = 1064 +X86_INS_VPHADDBD = 1065 +X86_INS_VPHADDBQ = 1066 +X86_INS_VPHADDBW = 1067 +X86_INS_VPHADDDQ = 1068 +X86_INS_VPHADDD = 1069 +X86_INS_VPHADDSW = 1070 +X86_INS_VPHADDUBD = 1071 +X86_INS_VPHADDUBQ = 1072 +X86_INS_VPHADDUBW = 1073 +X86_INS_VPHADDUDQ = 1074 +X86_INS_VPHADDUWD = 1075 +X86_INS_VPHADDUWQ = 1076 +X86_INS_VPHADDWD = 1077 +X86_INS_VPHADDWQ = 1078 +X86_INS_VPHADDW = 1079 +X86_INS_VPHMINPOSUW = 1080 +X86_INS_VPHSUBBW = 1081 +X86_INS_VPHSUBDQ = 1082 +X86_INS_VPHSUBD = 1083 +X86_INS_VPHSUBSW = 1084 +X86_INS_VPHSUBWD = 1085 +X86_INS_VPHSUBW = 1086 +X86_INS_VPINSRB = 1087 +X86_INS_VPINSRD = 1088 +X86_INS_VPINSRQ = 1089 +X86_INS_VPINSRW = 1090 +X86_INS_VPLZCNTD = 1091 +X86_INS_VPLZCNTQ = 1092 +X86_INS_VPMACSDD = 1093 +X86_INS_VPMACSDQH = 1094 +X86_INS_VPMACSDQL = 1095 +X86_INS_VPMACSSDD = 1096 +X86_INS_VPMACSSDQH = 1097 +X86_INS_VPMACSSDQL = 1098 +X86_INS_VPMACSSWD = 1099 +X86_INS_VPMACSSWW = 1100 +X86_INS_VPMACSWD = 1101 +X86_INS_VPMACSWW = 1102 +X86_INS_VPMADCSSWD = 1103 +X86_INS_VPMADCSWD = 1104 +X86_INS_VPMADDUBSW = 1105 +X86_INS_VPMADDWD = 1106 +X86_INS_VPMASKMOVD = 1107 +X86_INS_VPMASKMOVQ = 1108 +X86_INS_VPMAXSB = 1109 +X86_INS_VPMAXSD = 1110 +X86_INS_VPMAXSQ = 1111 +X86_INS_VPMAXSW = 1112 +X86_INS_VPMAXUB = 1113 +X86_INS_VPMAXUD = 1114 +X86_INS_VPMAXUQ = 1115 +X86_INS_VPMAXUW = 1116 +X86_INS_VPMINSB = 1117 +X86_INS_VPMINSD = 1118 +X86_INS_VPMINSQ = 1119 +X86_INS_VPMINSW = 1120 +X86_INS_VPMINUB = 1121 +X86_INS_VPMINUD = 1122 +X86_INS_VPMINUQ = 1123 +X86_INS_VPMINUW = 1124 +X86_INS_VPMOVDB = 1125 +X86_INS_VPMOVDW = 1126 +X86_INS_VPMOVM2B = 1127 +X86_INS_VPMOVM2D = 1128 +X86_INS_VPMOVM2Q = 1129 +X86_INS_VPMOVM2W = 1130 +X86_INS_VPMOVMSKB = 1131 +X86_INS_VPMOVQB = 1132 +X86_INS_VPMOVQD = 1133 +X86_INS_VPMOVQW = 1134 +X86_INS_VPMOVSDB = 1135 +X86_INS_VPMOVSDW = 1136 +X86_INS_VPMOVSQB = 1137 +X86_INS_VPMOVSQD = 1138 +X86_INS_VPMOVSQW = 1139 +X86_INS_VPMOVSXBD = 1140 +X86_INS_VPMOVSXBQ = 1141 +X86_INS_VPMOVSXBW = 1142 +X86_INS_VPMOVSXDQ = 1143 +X86_INS_VPMOVSXWD = 1144 +X86_INS_VPMOVSXWQ = 1145 +X86_INS_VPMOVUSDB = 1146 +X86_INS_VPMOVUSDW = 1147 +X86_INS_VPMOVUSQB = 1148 +X86_INS_VPMOVUSQD = 1149 +X86_INS_VPMOVUSQW = 1150 +X86_INS_VPMOVZXBD = 1151 +X86_INS_VPMOVZXBQ = 1152 +X86_INS_VPMOVZXBW = 1153 +X86_INS_VPMOVZXDQ = 1154 +X86_INS_VPMOVZXWD = 1155 +X86_INS_VPMOVZXWQ = 1156 +X86_INS_VPMULDQ = 1157 +X86_INS_VPMULHRSW = 1158 +X86_INS_VPMULHUW = 1159 +X86_INS_VPMULHW = 1160 +X86_INS_VPMULLD = 1161 +X86_INS_VPMULLQ = 1162 +X86_INS_VPMULLW = 1163 +X86_INS_VPMULUDQ = 1164 +X86_INS_VPORD = 1165 +X86_INS_VPORQ = 1166 +X86_INS_VPOR = 1167 +X86_INS_VPPERM = 1168 +X86_INS_VPROTB = 1169 +X86_INS_VPROTD = 1170 +X86_INS_VPROTQ = 1171 +X86_INS_VPROTW = 1172 +X86_INS_VPSADBW = 1173 +X86_INS_VPSCATTERDD = 1174 +X86_INS_VPSCATTERDQ = 1175 +X86_INS_VPSCATTERQD = 1176 +X86_INS_VPSCATTERQQ = 1177 +X86_INS_VPSHAB = 1178 +X86_INS_VPSHAD = 1179 +X86_INS_VPSHAQ = 1180 +X86_INS_VPSHAW = 1181 +X86_INS_VPSHLB = 1182 +X86_INS_VPSHLD = 1183 +X86_INS_VPSHLQ = 1184 +X86_INS_VPSHLW = 1185 +X86_INS_VPSHUFB = 1186 +X86_INS_VPSHUFD = 1187 +X86_INS_VPSHUFHW = 1188 +X86_INS_VPSHUFLW = 1189 +X86_INS_VPSIGNB = 1190 +X86_INS_VPSIGND = 1191 +X86_INS_VPSIGNW = 1192 +X86_INS_VPSLLDQ = 1193 +X86_INS_VPSLLD = 1194 +X86_INS_VPSLLQ = 1195 +X86_INS_VPSLLVD = 1196 +X86_INS_VPSLLVQ = 1197 +X86_INS_VPSLLW = 1198 +X86_INS_VPSRAD = 1199 +X86_INS_VPSRAQ = 1200 +X86_INS_VPSRAVD = 1201 +X86_INS_VPSRAVQ = 1202 +X86_INS_VPSRAW = 1203 +X86_INS_VPSRLDQ = 1204 +X86_INS_VPSRLD = 1205 +X86_INS_VPSRLQ = 1206 +X86_INS_VPSRLVD = 1207 +X86_INS_VPSRLVQ = 1208 +X86_INS_VPSRLW = 1209 +X86_INS_VPSUBB = 1210 +X86_INS_VPSUBD = 1211 +X86_INS_VPSUBQ = 1212 +X86_INS_VPSUBSB = 1213 +X86_INS_VPSUBSW = 1214 +X86_INS_VPSUBUSB = 1215 +X86_INS_VPSUBUSW = 1216 +X86_INS_VPSUBW = 1217 +X86_INS_VPTESTMD = 1218 +X86_INS_VPTESTMQ = 1219 +X86_INS_VPTESTNMD = 1220 +X86_INS_VPTESTNMQ = 1221 +X86_INS_VPTEST = 1222 +X86_INS_VPUNPCKHBW = 1223 +X86_INS_VPUNPCKHDQ = 1224 +X86_INS_VPUNPCKHQDQ = 1225 +X86_INS_VPUNPCKHWD = 1226 +X86_INS_VPUNPCKLBW = 1227 +X86_INS_VPUNPCKLDQ = 1228 +X86_INS_VPUNPCKLQDQ = 1229 +X86_INS_VPUNPCKLWD = 1230 +X86_INS_VPXORD = 1231 +X86_INS_VPXORQ = 1232 +X86_INS_VPXOR = 1233 +X86_INS_VRCP14PD = 1234 +X86_INS_VRCP14PS = 1235 +X86_INS_VRCP14SD = 1236 +X86_INS_VRCP14SS = 1237 +X86_INS_VRCP28PD = 1238 +X86_INS_VRCP28PS = 1239 +X86_INS_VRCP28SD = 1240 +X86_INS_VRCP28SS = 1241 +X86_INS_VRCPPS = 1242 +X86_INS_VRCPSS = 1243 +X86_INS_VRNDSCALEPD = 1244 +X86_INS_VRNDSCALEPS = 1245 +X86_INS_VRNDSCALESD = 1246 +X86_INS_VRNDSCALESS = 1247 +X86_INS_VROUNDPD = 1248 +X86_INS_VROUNDPS = 1249 +X86_INS_VROUNDSD = 1250 +X86_INS_VROUNDSS = 1251 +X86_INS_VRSQRT14PD = 1252 +X86_INS_VRSQRT14PS = 1253 +X86_INS_VRSQRT14SD = 1254 +X86_INS_VRSQRT14SS = 1255 +X86_INS_VRSQRT28PD = 1256 +X86_INS_VRSQRT28PS = 1257 +X86_INS_VRSQRT28SD = 1258 +X86_INS_VRSQRT28SS = 1259 +X86_INS_VRSQRTPS = 1260 +X86_INS_VRSQRTSS = 1261 +X86_INS_VSCATTERDPD = 1262 +X86_INS_VSCATTERDPS = 1263 +X86_INS_VSCATTERPF0DPD = 1264 +X86_INS_VSCATTERPF0DPS = 1265 +X86_INS_VSCATTERPF0QPD = 1266 +X86_INS_VSCATTERPF0QPS = 1267 +X86_INS_VSCATTERPF1DPD = 1268 +X86_INS_VSCATTERPF1DPS = 1269 +X86_INS_VSCATTERPF1QPD = 1270 +X86_INS_VSCATTERPF1QPS = 1271 +X86_INS_VSCATTERQPD = 1272 +X86_INS_VSCATTERQPS = 1273 +X86_INS_VSHUFPD = 1274 +X86_INS_VSHUFPS = 1275 +X86_INS_VSQRTPD = 1276 +X86_INS_VSQRTPS = 1277 +X86_INS_VSQRTSD = 1278 +X86_INS_VSQRTSS = 1279 +X86_INS_VSTMXCSR = 1280 +X86_INS_VSUBPD = 1281 +X86_INS_VSUBPS = 1282 +X86_INS_VSUBSD = 1283 +X86_INS_VSUBSS = 1284 +X86_INS_VTESTPD = 1285 +X86_INS_VTESTPS = 1286 +X86_INS_VUNPCKHPD = 1287 +X86_INS_VUNPCKHPS = 1288 +X86_INS_VUNPCKLPD = 1289 +X86_INS_VUNPCKLPS = 1290 +X86_INS_VZEROALL = 1291 +X86_INS_VZEROUPPER = 1292 +X86_INS_WAIT = 1293 +X86_INS_WBINVD = 1294 +X86_INS_WRFSBASE = 1295 +X86_INS_WRGSBASE = 1296 +X86_INS_WRMSR = 1297 +X86_INS_XABORT = 1298 +X86_INS_XACQUIRE = 1299 +X86_INS_XBEGIN = 1300 +X86_INS_XCHG = 1301 +X86_INS_XCRYPTCBC = 1302 +X86_INS_XCRYPTCFB = 1303 +X86_INS_XCRYPTCTR = 1304 +X86_INS_XCRYPTECB = 1305 +X86_INS_XCRYPTOFB = 1306 +X86_INS_XEND = 1307 +X86_INS_XGETBV = 1308 +X86_INS_XLATB = 1309 +X86_INS_XRELEASE = 1310 +X86_INS_XRSTOR = 1311 +X86_INS_XRSTOR64 = 1312 +X86_INS_XRSTORS = 1313 +X86_INS_XRSTORS64 = 1314 +X86_INS_XSAVE = 1315 +X86_INS_XSAVE64 = 1316 +X86_INS_XSAVEC = 1317 +X86_INS_XSAVEC64 = 1318 +X86_INS_XSAVEOPT = 1319 +X86_INS_XSAVEOPT64 = 1320 +X86_INS_XSAVES = 1321 +X86_INS_XSAVES64 = 1322 +X86_INS_XSETBV = 1323 +X86_INS_XSHA1 = 1324 +X86_INS_XSHA256 = 1325 +X86_INS_XSTORE = 1326 +X86_INS_XTEST = 1327 +X86_INS_FDISI8087_NOP = 1328 +X86_INS_FENI8087_NOP = 1329 +X86_INS_CMPSS = 1330 +X86_INS_CMPEQSS = 1331 +X86_INS_CMPLTSS = 1332 +X86_INS_CMPLESS = 1333 +X86_INS_CMPUNORDSS = 1334 +X86_INS_CMPNEQSS = 1335 +X86_INS_CMPNLTSS = 1336 +X86_INS_CMPNLESS = 1337 +X86_INS_CMPORDSS = 1338 +X86_INS_CMPSD = 1339 +X86_INS_CMPEQSD = 1340 +X86_INS_CMPLTSD = 1341 +X86_INS_CMPLESD = 1342 +X86_INS_CMPUNORDSD = 1343 +X86_INS_CMPNEQSD = 1344 +X86_INS_CMPNLTSD = 1345 +X86_INS_CMPNLESD = 1346 +X86_INS_CMPORDSD = 1347 +X86_INS_CMPPS = 1348 +X86_INS_CMPEQPS = 1349 +X86_INS_CMPLTPS = 1350 +X86_INS_CMPLEPS = 1351 +X86_INS_CMPUNORDPS = 1352 +X86_INS_CMPNEQPS = 1353 +X86_INS_CMPNLTPS = 1354 +X86_INS_CMPNLEPS = 1355 +X86_INS_CMPORDPS = 1356 +X86_INS_CMPPD = 1357 +X86_INS_CMPEQPD = 1358 +X86_INS_CMPLTPD = 1359 +X86_INS_CMPLEPD = 1360 +X86_INS_CMPUNORDPD = 1361 +X86_INS_CMPNEQPD = 1362 +X86_INS_CMPNLTPD = 1363 +X86_INS_CMPNLEPD = 1364 +X86_INS_CMPORDPD = 1365 +X86_INS_VCMPSS = 1366 +X86_INS_VCMPEQSS = 1367 +X86_INS_VCMPLTSS = 1368 +X86_INS_VCMPLESS = 1369 +X86_INS_VCMPUNORDSS = 1370 +X86_INS_VCMPNEQSS = 1371 +X86_INS_VCMPNLTSS = 1372 +X86_INS_VCMPNLESS = 1373 +X86_INS_VCMPORDSS = 1374 +X86_INS_VCMPEQ_UQSS = 1375 +X86_INS_VCMPNGESS = 1376 +X86_INS_VCMPNGTSS = 1377 +X86_INS_VCMPFALSESS = 1378 +X86_INS_VCMPNEQ_OQSS = 1379 +X86_INS_VCMPGESS = 1380 +X86_INS_VCMPGTSS = 1381 +X86_INS_VCMPTRUESS = 1382 +X86_INS_VCMPEQ_OSSS = 1383 +X86_INS_VCMPLT_OQSS = 1384 +X86_INS_VCMPLE_OQSS = 1385 +X86_INS_VCMPUNORD_SSS = 1386 +X86_INS_VCMPNEQ_USSS = 1387 +X86_INS_VCMPNLT_UQSS = 1388 +X86_INS_VCMPNLE_UQSS = 1389 +X86_INS_VCMPORD_SSS = 1390 +X86_INS_VCMPEQ_USSS = 1391 +X86_INS_VCMPNGE_UQSS = 1392 +X86_INS_VCMPNGT_UQSS = 1393 +X86_INS_VCMPFALSE_OSSS = 1394 +X86_INS_VCMPNEQ_OSSS = 1395 +X86_INS_VCMPGE_OQSS = 1396 +X86_INS_VCMPGT_OQSS = 1397 +X86_INS_VCMPTRUE_USSS = 1398 +X86_INS_VCMPSD = 1399 +X86_INS_VCMPEQSD = 1400 +X86_INS_VCMPLTSD = 1401 +X86_INS_VCMPLESD = 1402 +X86_INS_VCMPUNORDSD = 1403 +X86_INS_VCMPNEQSD = 1404 +X86_INS_VCMPNLTSD = 1405 +X86_INS_VCMPNLESD = 1406 +X86_INS_VCMPORDSD = 1407 +X86_INS_VCMPEQ_UQSD = 1408 +X86_INS_VCMPNGESD = 1409 +X86_INS_VCMPNGTSD = 1410 +X86_INS_VCMPFALSESD = 1411 +X86_INS_VCMPNEQ_OQSD = 1412 +X86_INS_VCMPGESD = 1413 +X86_INS_VCMPGTSD = 1414 +X86_INS_VCMPTRUESD = 1415 +X86_INS_VCMPEQ_OSSD = 1416 +X86_INS_VCMPLT_OQSD = 1417 +X86_INS_VCMPLE_OQSD = 1418 +X86_INS_VCMPUNORD_SSD = 1419 +X86_INS_VCMPNEQ_USSD = 1420 +X86_INS_VCMPNLT_UQSD = 1421 +X86_INS_VCMPNLE_UQSD = 1422 +X86_INS_VCMPORD_SSD = 1423 +X86_INS_VCMPEQ_USSD = 1424 +X86_INS_VCMPNGE_UQSD = 1425 +X86_INS_VCMPNGT_UQSD = 1426 +X86_INS_VCMPFALSE_OSSD = 1427 +X86_INS_VCMPNEQ_OSSD = 1428 +X86_INS_VCMPGE_OQSD = 1429 +X86_INS_VCMPGT_OQSD = 1430 +X86_INS_VCMPTRUE_USSD = 1431 +X86_INS_VCMPPS = 1432 +X86_INS_VCMPEQPS = 1433 +X86_INS_VCMPLTPS = 1434 +X86_INS_VCMPLEPS = 1435 +X86_INS_VCMPUNORDPS = 1436 +X86_INS_VCMPNEQPS = 1437 +X86_INS_VCMPNLTPS = 1438 +X86_INS_VCMPNLEPS = 1439 +X86_INS_VCMPORDPS = 1440 +X86_INS_VCMPEQ_UQPS = 1441 +X86_INS_VCMPNGEPS = 1442 +X86_INS_VCMPNGTPS = 1443 +X86_INS_VCMPFALSEPS = 1444 +X86_INS_VCMPNEQ_OQPS = 1445 +X86_INS_VCMPGEPS = 1446 +X86_INS_VCMPGTPS = 1447 +X86_INS_VCMPTRUEPS = 1448 +X86_INS_VCMPEQ_OSPS = 1449 +X86_INS_VCMPLT_OQPS = 1450 +X86_INS_VCMPLE_OQPS = 1451 +X86_INS_VCMPUNORD_SPS = 1452 +X86_INS_VCMPNEQ_USPS = 1453 +X86_INS_VCMPNLT_UQPS = 1454 +X86_INS_VCMPNLE_UQPS = 1455 +X86_INS_VCMPORD_SPS = 1456 +X86_INS_VCMPEQ_USPS = 1457 +X86_INS_VCMPNGE_UQPS = 1458 +X86_INS_VCMPNGT_UQPS = 1459 +X86_INS_VCMPFALSE_OSPS = 1460 +X86_INS_VCMPNEQ_OSPS = 1461 +X86_INS_VCMPGE_OQPS = 1462 +X86_INS_VCMPGT_OQPS = 1463 +X86_INS_VCMPTRUE_USPS = 1464 +X86_INS_VCMPPD = 1465 +X86_INS_VCMPEQPD = 1466 +X86_INS_VCMPLTPD = 1467 +X86_INS_VCMPLEPD = 1468 +X86_INS_VCMPUNORDPD = 1469 +X86_INS_VCMPNEQPD = 1470 +X86_INS_VCMPNLTPD = 1471 +X86_INS_VCMPNLEPD = 1472 +X86_INS_VCMPORDPD = 1473 +X86_INS_VCMPEQ_UQPD = 1474 +X86_INS_VCMPNGEPD = 1475 +X86_INS_VCMPNGTPD = 1476 +X86_INS_VCMPFALSEPD = 1477 +X86_INS_VCMPNEQ_OQPD = 1478 +X86_INS_VCMPGEPD = 1479 +X86_INS_VCMPGTPD = 1480 +X86_INS_VCMPTRUEPD = 1481 +X86_INS_VCMPEQ_OSPD = 1482 +X86_INS_VCMPLT_OQPD = 1483 +X86_INS_VCMPLE_OQPD = 1484 +X86_INS_VCMPUNORD_SPD = 1485 +X86_INS_VCMPNEQ_USPD = 1486 +X86_INS_VCMPNLT_UQPD = 1487 +X86_INS_VCMPNLE_UQPD = 1488 +X86_INS_VCMPORD_SPD = 1489 +X86_INS_VCMPEQ_USPD = 1490 +X86_INS_VCMPNGE_UQPD = 1491 +X86_INS_VCMPNGT_UQPD = 1492 +X86_INS_VCMPFALSE_OSPD = 1493 +X86_INS_VCMPNEQ_OSPD = 1494 +X86_INS_VCMPGE_OQPD = 1495 +X86_INS_VCMPGT_OQPD = 1496 +X86_INS_VCMPTRUE_USPD = 1497 +X86_INS_UD0 = 1498 +X86_INS_ENDBR32 = 1499 +X86_INS_ENDBR64 = 1500 +X86_INS_ENDING = 1501 + +X86_GRP_INVALID = 0 +X86_GRP_JUMP = 1 +X86_GRP_CALL = 2 +X86_GRP_RET = 3 +X86_GRP_INT = 4 +X86_GRP_IRET = 5 +X86_GRP_PRIVILEGE = 6 +X86_GRP_BRANCH_RELATIVE = 7 +X86_GRP_VM = 128 +X86_GRP_3DNOW = 129 +X86_GRP_AES = 130 +X86_GRP_ADX = 131 +X86_GRP_AVX = 132 +X86_GRP_AVX2 = 133 +X86_GRP_AVX512 = 134 +X86_GRP_BMI = 135 +X86_GRP_BMI2 = 136 +X86_GRP_CMOV = 137 +X86_GRP_F16C = 138 +X86_GRP_FMA = 139 +X86_GRP_FMA4 = 140 +X86_GRP_FSGSBASE = 141 +X86_GRP_HLE = 142 +X86_GRP_MMX = 143 +X86_GRP_MODE32 = 144 +X86_GRP_MODE64 = 145 +X86_GRP_RTM = 146 +X86_GRP_SHA = 147 +X86_GRP_SSE1 = 148 +X86_GRP_SSE2 = 149 +X86_GRP_SSE3 = 150 +X86_GRP_SSE41 = 151 +X86_GRP_SSE42 = 152 +X86_GRP_SSE4A = 153 +X86_GRP_SSSE3 = 154 +X86_GRP_PCLMUL = 155 +X86_GRP_XOP = 156 +X86_GRP_CDI = 157 +X86_GRP_ERI = 158 +X86_GRP_TBM = 159 +X86_GRP_16BITMODE = 160 +X86_GRP_NOT64BITMODE = 161 +X86_GRP_SGX = 162 +X86_GRP_DQI = 163 +X86_GRP_BWI = 164 +X86_GRP_PFI = 165 +X86_GRP_VLX = 166 +X86_GRP_SMAP = 167 +X86_GRP_NOVLX = 168 +X86_GRP_FPU = 169 +X86_GRP_ENDING = 170 diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/xcore.py b/white_patch_detect/capstone-master/bindings/python/capstone/xcore.py new file mode 100644 index 0000000..ec95b78 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/xcore.py @@ -0,0 +1,50 @@ +# Capstone Python bindings, by Nguyen Anh Quynnh + +import ctypes +from . import copy_ctypes_list +from .xcore_const import * + +# define the API +class XcoreOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint8), + ('index', ctypes.c_uint8), + ('disp', ctypes.c_int32), + ('direct', ctypes.c_int), + ) + +class XcoreOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int32), + ('mem', XcoreOpMem), + ) + +class XcoreOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint), + ('value', XcoreOpValue), + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +class CsXcore(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', XcoreOp * 8), + ) + +def get_arch_info(a): + return (copy_ctypes_list(a.operands[:a.op_count])) + diff --git a/white_patch_detect/capstone-master/bindings/python/capstone/xcore_const.py b/white_patch_detect/capstone-master/bindings/python/capstone/xcore_const.py new file mode 100644 index 0000000..f1b7485 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/capstone/xcore_const.py @@ -0,0 +1,161 @@ +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py] + +XCORE_OP_INVALID = 0 +XCORE_OP_REG = 1 +XCORE_OP_IMM = 2 +XCORE_OP_MEM = 3 + +XCORE_REG_INVALID = 0 +XCORE_REG_CP = 1 +XCORE_REG_DP = 2 +XCORE_REG_LR = 3 +XCORE_REG_SP = 4 +XCORE_REG_R0 = 5 +XCORE_REG_R1 = 6 +XCORE_REG_R2 = 7 +XCORE_REG_R3 = 8 +XCORE_REG_R4 = 9 +XCORE_REG_R5 = 10 +XCORE_REG_R6 = 11 +XCORE_REG_R7 = 12 +XCORE_REG_R8 = 13 +XCORE_REG_R9 = 14 +XCORE_REG_R10 = 15 +XCORE_REG_R11 = 16 +XCORE_REG_PC = 17 +XCORE_REG_SCP = 18 +XCORE_REG_SSR = 19 +XCORE_REG_ET = 20 +XCORE_REG_ED = 21 +XCORE_REG_SED = 22 +XCORE_REG_KEP = 23 +XCORE_REG_KSP = 24 +XCORE_REG_ID = 25 +XCORE_REG_ENDING = 26 + +XCORE_INS_INVALID = 0 +XCORE_INS_ADD = 1 +XCORE_INS_ANDNOT = 2 +XCORE_INS_AND = 3 +XCORE_INS_ASHR = 4 +XCORE_INS_BAU = 5 +XCORE_INS_BITREV = 6 +XCORE_INS_BLA = 7 +XCORE_INS_BLAT = 8 +XCORE_INS_BL = 9 +XCORE_INS_BF = 10 +XCORE_INS_BT = 11 +XCORE_INS_BU = 12 +XCORE_INS_BRU = 13 +XCORE_INS_BYTEREV = 14 +XCORE_INS_CHKCT = 15 +XCORE_INS_CLRE = 16 +XCORE_INS_CLRPT = 17 +XCORE_INS_CLRSR = 18 +XCORE_INS_CLZ = 19 +XCORE_INS_CRC8 = 20 +XCORE_INS_CRC32 = 21 +XCORE_INS_DCALL = 22 +XCORE_INS_DENTSP = 23 +XCORE_INS_DGETREG = 24 +XCORE_INS_DIVS = 25 +XCORE_INS_DIVU = 26 +XCORE_INS_DRESTSP = 27 +XCORE_INS_DRET = 28 +XCORE_INS_ECALLF = 29 +XCORE_INS_ECALLT = 30 +XCORE_INS_EDU = 31 +XCORE_INS_EEF = 32 +XCORE_INS_EET = 33 +XCORE_INS_EEU = 34 +XCORE_INS_ENDIN = 35 +XCORE_INS_ENTSP = 36 +XCORE_INS_EQ = 37 +XCORE_INS_EXTDP = 38 +XCORE_INS_EXTSP = 39 +XCORE_INS_FREER = 40 +XCORE_INS_FREET = 41 +XCORE_INS_GETD = 42 +XCORE_INS_GET = 43 +XCORE_INS_GETN = 44 +XCORE_INS_GETR = 45 +XCORE_INS_GETSR = 46 +XCORE_INS_GETST = 47 +XCORE_INS_GETTS = 48 +XCORE_INS_INCT = 49 +XCORE_INS_INIT = 50 +XCORE_INS_INPW = 51 +XCORE_INS_INSHR = 52 +XCORE_INS_INT = 53 +XCORE_INS_IN = 54 +XCORE_INS_KCALL = 55 +XCORE_INS_KENTSP = 56 +XCORE_INS_KRESTSP = 57 +XCORE_INS_KRET = 58 +XCORE_INS_LADD = 59 +XCORE_INS_LD16S = 60 +XCORE_INS_LD8U = 61 +XCORE_INS_LDA16 = 62 +XCORE_INS_LDAP = 63 +XCORE_INS_LDAW = 64 +XCORE_INS_LDC = 65 +XCORE_INS_LDW = 66 +XCORE_INS_LDIVU = 67 +XCORE_INS_LMUL = 68 +XCORE_INS_LSS = 69 +XCORE_INS_LSUB = 70 +XCORE_INS_LSU = 71 +XCORE_INS_MACCS = 72 +XCORE_INS_MACCU = 73 +XCORE_INS_MJOIN = 74 +XCORE_INS_MKMSK = 75 +XCORE_INS_MSYNC = 76 +XCORE_INS_MUL = 77 +XCORE_INS_NEG = 78 +XCORE_INS_NOT = 79 +XCORE_INS_OR = 80 +XCORE_INS_OUTCT = 81 +XCORE_INS_OUTPW = 82 +XCORE_INS_OUTSHR = 83 +XCORE_INS_OUTT = 84 +XCORE_INS_OUT = 85 +XCORE_INS_PEEK = 86 +XCORE_INS_REMS = 87 +XCORE_INS_REMU = 88 +XCORE_INS_RETSP = 89 +XCORE_INS_SETCLK = 90 +XCORE_INS_SET = 91 +XCORE_INS_SETC = 92 +XCORE_INS_SETD = 93 +XCORE_INS_SETEV = 94 +XCORE_INS_SETN = 95 +XCORE_INS_SETPSC = 96 +XCORE_INS_SETPT = 97 +XCORE_INS_SETRDY = 98 +XCORE_INS_SETSR = 99 +XCORE_INS_SETTW = 100 +XCORE_INS_SETV = 101 +XCORE_INS_SEXT = 102 +XCORE_INS_SHL = 103 +XCORE_INS_SHR = 104 +XCORE_INS_SSYNC = 105 +XCORE_INS_ST16 = 106 +XCORE_INS_ST8 = 107 +XCORE_INS_STW = 108 +XCORE_INS_SUB = 109 +XCORE_INS_SYNCR = 110 +XCORE_INS_TESTCT = 111 +XCORE_INS_TESTLCL = 112 +XCORE_INS_TESTWCT = 113 +XCORE_INS_TSETMR = 114 +XCORE_INS_START = 115 +XCORE_INS_WAITEF = 116 +XCORE_INS_WAITET = 117 +XCORE_INS_WAITEU = 118 +XCORE_INS_XOR = 119 +XCORE_INS_ZEXT = 120 +XCORE_INS_ENDING = 121 + +XCORE_GRP_INVALID = 0 +XCORE_GRP_JUMP = 1 +XCORE_GRP_ENDING = 2 diff --git a/white_patch_detect/capstone-master/bindings/python/prebuilt/.gitkeep b/white_patch_detect/capstone-master/bindings/python/prebuilt/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/white_patch_detect/capstone-master/bindings/python/pyx/README b/white_patch_detect/capstone-master/bindings/python/pyx/README new file mode 100644 index 0000000..2b88620 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/pyx/README @@ -0,0 +1 @@ +This directory contains Cython files. diff --git a/white_patch_detect/capstone-master/bindings/python/pyx/ccapstone.pxd b/white_patch_detect/capstone-master/bindings/python/pyx/ccapstone.pxd new file mode 100644 index 0000000..8b163f2 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/pyx/ccapstone.pxd @@ -0,0 +1,72 @@ +# By Dang Hoang Vu , 2014 + +from libcpp cimport bool +from libc.stdint cimport uint8_t, uint64_t, uint16_t + +cdef extern from "": + + ctypedef size_t csh + + ctypedef enum cs_mode: + pass + + ctypedef enum cs_arch: + pass + + ctypedef struct cs_detail: + pass + + ctypedef struct cs_insn: + unsigned int id + uint64_t address + uint16_t size + uint8_t bytes[24] + char mnemonic[32] + char op_str[160] + cs_detail *detail + + ctypedef enum cs_err: + pass + + ctypedef enum cs_opt_type: + pass + + unsigned int cs_version(int *major, int *minor) + + bool cs_support(int arch) + + cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle) + + cs_err cs_close(csh *handle) + + cs_err cs_errno(csh handle) + + size_t cs_disasm(csh handle, + const uint8_t *code, size_t code_size, + uint64_t address, + size_t count, + cs_insn **insn) + + cs_err cs_option(csh handle, cs_opt_type type, size_t value) + + void cs_free(cs_insn *insn, size_t count) + + const char *cs_reg_name(csh handle, unsigned int reg_id) + + const char *cs_insn_name(csh handle, unsigned int insn_id) + + const char *cs_group_name(csh handle, unsigned int group_id) + + bool cs_insn_group(csh handle, cs_insn *insn, unsigned int group_id) + + bool cs_reg_read(csh handle, cs_insn *insn, unsigned int reg_id) + + bool cs_reg_write(csh handle, cs_insn *insn, unsigned int reg_id) + + int cs_op_count(csh handle, cs_insn *insn, unsigned int op_type) + + cs_err cs_regs_access(csh handle, cs_insn *insn, uint16_t *regs_read, uint8_t *read_count, uint16_t *regs_write, uint8_t *write_count) + + int cs_op_index(csh handle, cs_insn *insn, unsigned int op_type, + unsigned int position) + diff --git a/white_patch_detect/capstone-master/bindings/python/setup.cfg b/white_patch_detect/capstone-master/bindings/python/setup.cfg new file mode 100644 index 0000000..2a9acf1 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/setup.cfg @@ -0,0 +1,2 @@ +[bdist_wheel] +universal = 1 diff --git a/white_patch_detect/capstone-master/bindings/python/setup.py b/white_patch_detect/capstone-master/bindings/python/setup.py new file mode 100644 index 0000000..7a1eaaf --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/setup.py @@ -0,0 +1,289 @@ +#!/usr/bin/env python + +import glob +import os +import shutil +import sys +import platform + +from distutils import log +from setuptools import setup +from distutils.util import get_platform +from distutils.command.build import build +from distutils.command.sdist import sdist +from setuptools.command.bdist_egg import bdist_egg + +SYSTEM = sys.platform + +# adapted from commit e504b81 of Nguyen Tan Cong +# Reference: https://docs.python.org/2/library/platform.html#cross-platform +IS_64BITS = sys.maxsize > 2**32 + +# are we building from the repository or from a source distribution? +ROOT_DIR = os.path.dirname(os.path.realpath(__file__)) +LIBS_DIR = os.path.join(ROOT_DIR, 'capstone', 'lib') +HEADERS_DIR = os.path.join(ROOT_DIR, 'capstone', 'include') +SRC_DIR = os.path.join(ROOT_DIR, 'src') +BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..') + +# Parse version from pkgconfig.mk +VERSION_DATA = {} +with open(os.path.join(BUILD_DIR, 'pkgconfig.mk')) as fp: + lines = fp.readlines() + for line in lines: + line = line.strip() + if len(line) == 0: + continue + if line.startswith('#'): + continue + if '=' not in line: + continue + + k, v = line.split('=', 1) + k = k.strip() + v = v.strip() + if len(k) == 0 or len(v) == 0: + continue + VERSION_DATA[k] = v + +if 'PKG_MAJOR' not in VERSION_DATA or \ + 'PKG_MINOR' not in VERSION_DATA or \ + 'PKG_EXTRA' not in VERSION_DATA: + raise Exception("Malformed pkgconfig.mk") + +if 'PKG_TAG' in VERSION_DATA: + VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}.{PKG_TAG}'.format(**VERSION_DATA) +else: + VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}'.format(**VERSION_DATA) + +if SYSTEM == 'darwin': + VERSIONED_LIBRARY_FILE = "libcapstone.{PKG_MAJOR}.dylib".format(**VERSION_DATA) + LIBRARY_FILE = "libcapstone.dylib" + STATIC_LIBRARY_FILE = 'libcapstone.a' +elif SYSTEM in ('win32', 'cygwin'): + VERSIONED_LIBRARY_FILE = "capstone.dll" + LIBRARY_FILE = "capstone.dll" + STATIC_LIBRARY_FILE = None +else: + VERSIONED_LIBRARY_FILE = "libcapstone.so.{PKG_MAJOR}".format(**VERSION_DATA) + LIBRARY_FILE = "libcapstone.so" + STATIC_LIBRARY_FILE = 'libcapstone.a' + +def clean_bins(): + shutil.rmtree(LIBS_DIR, ignore_errors=True) + shutil.rmtree(HEADERS_DIR, ignore_errors=True) + +def copy_sources(): + """Copy the C sources into the source directory. + This rearranges the source files under the python distribution + directory. + """ + src = [] + + try: + shutil.rmtree("src/") + except (IOError, OSError): + pass + + shutil.copytree(os.path.join(BUILD_DIR, "arch"), os.path.join(SRC_DIR, "arch")) + shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include")) + + src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "*.mk"))) + + src.extend(glob.glob(os.path.join(BUILD_DIR, "Makefile"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSE*"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "README"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "make.sh"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "pkgconfig.mk"))) + + for filename in src: + outpath = os.path.join(SRC_DIR, os.path.basename(filename)) + log.info("%s -> %s" % (filename, outpath)) + shutil.copy(filename, outpath) + +def build_libraries(): + """ + Prepare the capstone directory for a binary distribution or installation. + Builds shared libraries and copies header files. + + Will use a src/ dir if one exists in the current directory, otherwise assumes it's in the repo + """ + cwd = os.getcwd() + clean_bins() + os.mkdir(HEADERS_DIR) + os.mkdir(LIBS_DIR) + + # copy public headers + shutil.copytree(os.path.join(BUILD_DIR, 'include', 'capstone'), os.path.join(HEADERS_DIR, 'capstone')) + + # if prebuilt libraries are available, use those and cancel build + if os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE)) and \ + (not STATIC_LIBRARY_FILE or os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE))): + shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE), LIBS_DIR) + if STATIC_LIBRARY_FILE is not None: + shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE), LIBS_DIR) + return + + os.chdir(BUILD_DIR) + + # platform description refers at https://docs.python.org/2/library/sys.html#sys.platform + if SYSTEM == "win32": + # Windows build: this process requires few things: + # - CMake + MSVC installed + # - Run this command in an environment setup for MSVC + if not os.path.exists("build"): os.mkdir("build") + os.chdir("build") + # Do not build tests & static library + os.system('cmake -DCMAKE_BUILD_TYPE=RELEASE -DCAPSTONE_BUILD_TESTS=0 -DCAPSTONE_BUILD_STATIC=0 -G "NMake Makefiles" ..') + os.system("nmake") + elif "bsd" in SYSTEM: + # *BSD distinguishes make (BSD) vs gmake (GNU). Use cmake + bsd make :-) + if not os.path.exists("build"): os.mkdir("build") + os.chdir("build") + # Do not build tests & static library + os.system('cmake -DCMAKE_BUILD_TYPE=RELEASE -DCAPSTONE_BUILD_TESTS=0 -DCAPSTONE_BUILD_STATIC=0 ..') + os.system("make") + else: # Unix incl. cygwin + os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh") + + shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE)) + + # only copy static library if it exists (it's a build option) + if STATIC_LIBRARY_FILE and os.path.exists(STATIC_LIBRARY_FILE): + shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR) + os.chdir(cwd) + + +class custom_sdist(sdist): + def run(self): + clean_bins() + copy_sources() + return sdist.run(self) + + +class custom_build(build): + def run(self): + if 'LIBCAPSTONE_PATH' in os.environ: + log.info('Skipping building C extensions since LIBCAPSTONE_PATH is set') + else: + log.info('Building C extensions') + build_libraries() + return build.run(self) + + +class custom_bdist_egg(bdist_egg): + def run(self): + self.run_command('build') + return bdist_egg.run(self) + +def dummy_src(): + return [] + +cmdclass = {} +cmdclass['build'] = custom_build +cmdclass['sdist'] = custom_sdist +cmdclass['bdist_egg'] = custom_bdist_egg + +try: + from setuptools.command.develop import develop + class custom_develop(develop): + def run(self): + log.info("Building C extensions") + build_libraries() + return develop.run(self) + + cmdclass['develop'] = custom_develop +except ImportError: + print("Proper 'develop' support unavailable.") + +if 'bdist_wheel' in sys.argv and '--plat-name' not in sys.argv: + idx = sys.argv.index('bdist_wheel') + 1 + sys.argv.insert(idx, '--plat-name') + name = get_platform() + if 'linux' in name: + # linux_* platform tags are disallowed because the python ecosystem is fubar + # linux builds should be built in the centos 6 vm for maximum compatibility + # see https://github.com/pypa/manylinux + # see also https://github.com/angr/angr-dev/blob/master/bdist.sh and + # https://www.python.org/dev/peps/pep-0599/ + sys.argv.insert(idx + 1, 'manylinux2014_' + platform.machine()) + else: + # https://www.python.org/dev/peps/pep-0425/ + sys.argv.insert(idx + 1, name.replace('.', '_').replace('-', '_')) + +long_desc = ''' +Capstone is a disassembly framework with the target of becoming the ultimate +disasm engine for binary analysis and reversing in the security community. + +Created by Nguyen Anh Quynh, then developed and maintained by a small community, +Capstone offers some unparalleled features: + +- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc, + SystemZ, XCore and X86 (including X86_64). + +- Having clean/simple/lightweight/intuitive architecture-neutral API. + +- Provide details on disassembled instruction (called "decomposer" by others). + +- Provide semantics of the disassembled instruction, such as list of implicit + registers read & written. + +- Implemented in pure C language, with lightweight wrappers for C++, C#, Go, + Java, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code, + or provided externally by the community). + +- Native support for all popular platforms: Windows, Mac OSX, iOS, Android, + Linux, *BSD, Solaris, etc. + +- Thread-safe by design. + +- Special support for embedding into firmware or OS kernel. + +- High performance & suitable for malware analysis (capable of handling various + X86 malware tricks). + +- Distributed under the open source BSD license. + +Further information is available at http://www.capstone-engine.org + + +[License] + +This project is released under the BSD license. If you redistribute the binary +or source code of Capstone, please attach file LICENSE.TXT with your products. +''' + +setup( + provides=['capstone'], + packages=['capstone'], + name='capstone', + version=VERSION, + author='Nguyen Anh Quynh', + author_email='aquynh@gmail.com', + description='Capstone disassembly engine', + long_description=long_desc, + long_description_content_type="text/markdown", + url='https://www.capstone-engine.org', + python_requires='>=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*', + classifiers=[ + 'Development Status :: 5 - Production/Stable', + 'Intended Audience :: Developers', + 'Topic :: Software Development :: Build Tools', + 'License :: OSI Approved :: BSD License', + 'Programming Language :: Python :: 2', + 'Programming Language :: Python :: 2.7', + 'Programming Language :: Python :: 3', + ], + requires=['ctypes'], + cmdclass=cmdclass, + zip_safe=True, + include_package_data=True, + is_pure=False, + package_data={ + "capstone": ["lib/*", "include/capstone/*"], + } +) diff --git a/white_patch_detect/capstone-master/bindings/python/setup_cython.py b/white_patch_detect/capstone-master/bindings/python/setup_cython.py new file mode 100644 index 0000000..d36769a --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/setup_cython.py @@ -0,0 +1,144 @@ +import os +import sys +import shutil + +from distutils import log +from distutils.core import setup +from distutils.extension import Extension +from distutils.command.build import build +from Cython.Distutils import build_ext + +SYSTEM = sys.platform +VERSION = '4.0.0' + +# adapted from commit e504b81 of Nguyen Tan Cong +# Reference: https://docs.python.org/2/library/platform.html#cross-platform +IS_64BITS = sys.maxsize > 2**32 + +# are we building from the repository or from a source distribution? +ROOT_DIR = os.path.dirname(os.path.realpath(__file__)) +LIBS_DIR = os.path.join(ROOT_DIR, 'pyx', 'lib') +HEADERS_DIR = os.path.join(ROOT_DIR, 'pyx', 'include') +SRC_DIR = os.path.join(ROOT_DIR, 'src') +BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..') +PYPACKAGE_DIR = os.path.join(ROOT_DIR, 'capstone') +CYPACKAGE_DIR = os.path.join(ROOT_DIR, 'pyx') + +if SYSTEM == 'darwin': + VERSIONED_LIBRARY_FILE = "libcapstone.4.dylib" + LIBRARY_FILE = "libcapstone.dylib" + STATIC_LIBRARY_FILE = 'libcapstone.a' +elif SYSTEM in ('win32', 'cygwin'): + VERSIONED_LIBRARY_FILE = "capstone.dll" + LIBRARY_FILE = "capstone.dll" + STATIC_LIBRARY_FILE = None +else: + VERSIONED_LIBRARY_FILE = "libcapstone.so.4" + LIBRARY_FILE = "libcapstone.so" + STATIC_LIBRARY_FILE = 'libcapstone.a' + +compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR] +link_args = ['-L' + LIBS_DIR] + +ext_module_names = ['arm', 'arm_const', 'arm64', 'arm64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const' ] + +ext_modules = [Extension("capstone.ccapstone", + ["pyx/ccapstone.pyx"], + libraries=["capstone"], + extra_compile_args=compile_args, + extra_link_args=link_args)] +ext_modules += [Extension("capstone.%s" % name, + ["pyx/%s.pyx" % name], + extra_compile_args=compile_args, + extra_link_args=link_args) + for name in ext_module_names] + +def clean_bins(): + shutil.rmtree(LIBS_DIR, ignore_errors=True) + shutil.rmtree(HEADERS_DIR, ignore_errors=True) + +def copy_pysources(): + for fname in os.listdir(PYPACKAGE_DIR): + if not fname.endswith('.py'): + continue + + if fname == '__init__.py': + shutil.copy(os.path.join(PYPACKAGE_DIR, fname), os.path.join(CYPACKAGE_DIR, fname)) + else: + shutil.copy(os.path.join(PYPACKAGE_DIR, fname), os.path.join(CYPACKAGE_DIR, fname + 'x')) + +def build_libraries(): + """ + Prepare the capstone directory for a binary distribution or installation. + Builds shared libraries and copies header files. + + Will use a src/ dir if one exists in the current directory, otherwise assumes it's in the repo + """ + cwd = os.getcwd() + clean_bins() + os.mkdir(HEADERS_DIR) + os.mkdir(LIBS_DIR) + + # copy public headers + shutil.copytree(os.path.join(BUILD_DIR, 'include', 'capstone'), os.path.join(HEADERS_DIR, 'capstone')) + + os.chdir(BUILD_DIR) + + # platform description refers at https://docs.python.org/2/library/sys.html#sys.platform + if SYSTEM == "win32": + # Windows build: this process requires few things: + # - CMake + MSVC installed + # - Run this command in an environment setup for MSVC + if not os.path.exists("build"): os.mkdir("build") + os.chdir("build") + # Do not build tests & static library + os.system('cmake -DCMAKE_BUILD_TYPE=RELEASE -DCAPSTONE_BUILD_TESTS=0 -DCAPSTONE_BUILD_STATIC=0 -G "NMake Makefiles" ..') + os.system("nmake") + else: # Unix incl. cygwin + os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh") + + shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE)) + if STATIC_LIBRARY_FILE: shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR) + os.chdir(cwd) + + +class custom_build(build): + def run(self): + log.info('Copying python sources') + copy_pysources() + log.info('Building C extensions') + build_libraries() + return build.run(self) + +# clean package directory first +#import os.path, shutil, sys +#for f in sys.path: +# if f.endswith('packages'): +# pkgdir = os.path.join(f, 'capstone') +# #print(pkgdir) +# try: +# shutil.rmtree(pkgdir) +# except: +# pass + +setup( + provides = ['capstone'], + package_dir = {'capstone' : 'pyx'}, + packages = ['capstone'], + name = 'capstone', + version = VERSION, + cmdclass = {'build_ext': build_ext, 'build': custom_build}, + ext_modules = ext_modules, + author = 'Nguyen Anh Quynh', + author_email = 'aquynh@gmail.com', + description = 'Capstone disassembly engine', + url = 'http://www.capstone-engine.org', + classifiers = [ + 'License :: OSI Approved :: BSD License', + 'Programming Language :: Python :: 2', + ], + include_package_data=True, + package_data={ + "capstone": ["lib/*", "include/capstone/*"], + } +) diff --git a/white_patch_detect/capstone-master/bindings/python/test_all.py b/white_patch_detect/capstone-master/bindings/python/test_all.py new file mode 100644 index 0000000..4ec9121 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_all.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python + +import test_basic, test_arm, test_arm64, test_detail, test_lite, test_m68k, test_mips, \ + test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ + test_m680x, test_mos65xx + +test_basic.test_class() +test_arm.test_class() +test_arm64.test_class() +test_detail.test_class() +test_lite.test_class() +test_m68k.test_class() +test_mips.test_class() +test_mos65xx.test_class() +test_ppc.test_class() +test_sparc.test_class() +test_systemz.test_class() +test_x86.test_class() +test_tms320c64x.test_class() +test_m680x.test_class() +test_skipdata.test_class() +test_customized_mnem.test() diff --git a/white_patch_detect/capstone-master/bindings/python/test_arm.py b/white_patch_detect/capstone-master/bindings/python/test_arm.py new file mode 100644 index 0000000..8f11ce4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_arm.py @@ -0,0 +1,151 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.arm import * +from xprint import to_hex, to_x_32 + + +ARM_CODE = b"\x86\x48\x60\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" +ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" +THUMB_CODE = b"\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0" +THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" +THUMB_MCLASS = b"\xef\xf3\x02\x80" +ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" + +all_tests = ( + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None), + (CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), + (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), + ) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == ARM_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == ARM_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) + if i.type == ARM_OP_PIMM: + print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm)) + if i.type == ARM_OP_CIMM: + print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) + if i.type == ARM_OP_FP: + print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) + if i.type == ARM_OP_SYSREG: + print("\t\toperands[%u].type: SYSREG = %u" % (c, i.reg)) + if i.type == ARM_OP_SETEND: + if i.setend == ARM_SETEND_BE: + print("\t\toperands[%u].type: SETEND = be" % c) + else: + print("\t\toperands[%u].type: SETEND = le" % c) + if i.type == ARM_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" \ + % (c, insn.reg_name(i.mem.index))) + if i.mem.scale != 1: + print("\t\t\toperands[%u].mem.scale: %u" \ + % (c, i.mem.scale)) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x_32(i.mem.disp))) + if i.mem.lshift != 0: + print("\t\t\toperands[%u].mem.lshift: 0x%s" \ + % (c, to_x_32(i.mem.lshift))) + + if i.neon_lane != -1: + print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane)) + + if i.access == CS_AC_READ: + print("\t\toperands[%u].access: READ\n" % (c)) + elif i.access == CS_AC_WRITE: + print("\t\toperands[%u].access: WRITE\n" % (c)) + elif i.access == CS_AC_READ | CS_AC_WRITE: + print("\t\toperands[%u].access: READ | WRITE\n" % (c)) + + if i.shift.type != ARM_SFT_INVALID and i.shift.value: + print("\t\t\tShift: %u = %u" \ + % (i.shift.type, i.shift.value)) + if i.vector_index != -1: + print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index)) + if i.subtracted: + print("\t\t\toperands[%u].subtracted = True" %c) + + c += 1 + + if insn.update_flags: + print("\tUpdate-flags: True") + if insn.writeback: + print("\tWrite-back: True") + if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]: + print("\tCode condition: %u" % insn.cc) + if insn.cps_mode: + print("\tCPSI-mode: %u" %(insn.cps_mode)) + if insn.cps_flag: + print("\tCPSI-flag: %u" %(insn.cps_flag)) + if insn.vector_data: + print("\tVector-data: %u" %(insn.vector_data)) + if insn.vector_size: + print("\tVector-size: %u" %(insn.vector_size)) + if insn.usermode: + print("\tUser-mode: True") + if insn.mem_barrier: + print("\tMemory-barrier: %u" %(insn.mem_barrier)) + + (regs_read, regs_write) = insn.regs_access() + + if len(regs_read) > 0: + print("\tRegisters read:", end="") + for r in regs_read: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if len(regs_write) > 0: + print("\tRegisters modified:", end="") + for r in regs_write: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment, syntax) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + if syntax is not None: + md.syntax = syntax + md.detail = True + for insn in md.disasm(code, 0x80001000): + print_insn_detail(insn) + print () + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_arm64.py b/white_patch_detect/capstone-master/bindings/python/test_arm64.py new file mode 100644 index 0000000..f6c7a42 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_arm64.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.arm64 import * +from xprint import to_hex, to_x + + +ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" + +all_tests = ( + (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"), + ) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = -1 + for i in insn.operands: + c += 1 + if i.type == ARM64_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == ARM64_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == ARM64_OP_CIMM: + print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) + if i.type == ARM64_OP_FP: + print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) + if i.type == ARM64_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" \ + % (c, insn.reg_name(i.mem.index))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + if i.type == ARM64_OP_REG_MRS: + print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg)) + if i.type == ARM64_OP_REG_MSR: + print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg)) + if i.type == ARM64_OP_PSTATE: + print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate)) + if i.type == ARM64_OP_SYS: + print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys)) + if i.type == ARM64_OP_PREFETCH: + print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch)) + if i.type == ARM64_OP_BARRIER: + print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier)) + + if i.shift.type != ARM64_SFT_INVALID and i.shift.value: + print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value)) + + if i.ext != ARM64_EXT_INVALID: + print("\t\t\tExt: %u" % i.ext) + + if i.vas != ARM64_VAS_INVALID: + print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas) + + if i.vess != ARM64_VESS_INVALID: + print("\t\t\tVector Element Size Specifier: %u" % i.vess) + + if i.vector_index != -1: + print("\t\t\tVector Index: %u" % i.vector_index) + + if i.access == CS_AC_READ: + print("\t\toperands[%u].access: READ\n" % (c)) + elif i.access == CS_AC_WRITE: + print("\t\toperands[%u].access: WRITE\n" % (c)) + elif i.access == CS_AC_READ | CS_AC_WRITE: + print("\t\toperands[%u].access: READ | WRITE\n" % (c)) + + + if insn.writeback: + print("\tWrite-back: True") + if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]: + print("\tCode-condition: %u" % insn.cc) + if insn.update_flags: + print("\tUpdate-flags: True") + + (regs_read, regs_write) = insn.regs_access() + + if len(regs_read) > 0: + print("\tRegisters read:", end="") + for r in regs_read: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if len(regs_write) > 0: + print("\tRegisters modified:", end="") + for r in regs_write: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x2c): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_basic.py b/white_patch_detect/capstone-master/bindings/python/test_basic.py new file mode 100644 index 0000000..b55187b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_basic.py @@ -0,0 +1,107 @@ +#!/usr/bin/env python +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +import binascii +import sys + +from xprint import to_hex + +_python3 = sys.version_info.major == 3 + + +X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" +ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" +THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +THUMB_MCLASS = b"\xef\xf3\x02\x80" +ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" +MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" +ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" +PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" +TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" +M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM), + (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None), + (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), + (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None), + (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), + (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), + (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), + (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), + (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x", None), + (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), +) + +# ## Test cs_disasm_quick() +def test_cs_disasm_quick(): + for arch, mode, code, comment, syntax in all_tests: + print('*' * 40) + print("Platform: %s" % comment) + print("Disasm:"), + print(to_hex(code)) + for insn in cs_disasm_quick(arch, mode, code, 0x1000): + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + print() + + +# ## Test class Cs +def test_class(): + for arch, mode, code, comment, syntax in all_tests: + print('*' * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + + if syntax is not None: + md.syntax = syntax + + for insn in md.disasm(code, 0x1000): + # bytes = binascii.hexlify(insn.bytes) + # print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes)) + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + print("0x%x:" % (insn.address + insn.size)) + print() + except CsError as e: + print("ERROR: %s" % e) + + +# test_cs_disasm_quick() +# print ("*" * 40) +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_customized_mnem.py b/white_patch_detect/capstone-master/bindings/python/test_customized_mnem.py new file mode 100644 index 0000000..a09cc72 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_customized_mnem.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.x86 import * +from xprint import to_hex + + +X86_CODE32 = b"\x75\x01" + + +def print_insn(md, code): + print("%s\t" % to_hex(code, False), end="") + + for insn in md.disasm(code, 0x1000): + print("\t%s\t%s\n" % (insn.mnemonic, insn.op_str)) + + +def test(): + try: + md = Cs(CS_ARCH_X86, CS_MODE_32) + + print("Disassemble X86 code with default instruction mnemonic") + print_insn(md, X86_CODE32) + + print("Now customize engine to change mnemonic from 'JNE' to 'JNZ'") + md.mnemonic_setup(X86_INS_JNE, "jnz") + print_insn(md, X86_CODE32) + + print("Reset engine to use the default mnemonic") + md.mnemonic_setup(X86_INS_JNE, None) + print_insn(md, X86_CODE32) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test() diff --git a/white_patch_detect/capstone-master/bindings/python/test_detail.py b/white_patch_detect/capstone-master/bindings/python/test_detail.py new file mode 100644 index 0000000..e7cc6a8 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_detail.py @@ -0,0 +1,108 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +from capstone import * + + +X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" +ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" +THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88" +THUMB_MCLASS = b"\xef\xf3\x02\x80" +ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" +MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" +ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" +PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" +M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None), + (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), + (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), + (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), + (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), + (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), + (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), + (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), +) + + +def print_detail(insn): + print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \ + % (insn.address, insn.mnemonic, insn.op_str, insn.id, \ + insn.insn_name())) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.regs_read) > 0: + print("\tImplicit registers read: ", end=''), + for m in insn.regs_read: + print("%s " % insn.reg_name(m), end=''), + print() + + if len(insn.regs_write) > 0: + print("\tImplicit registers modified: ", end=''), + for m in insn.regs_write: + print("%s " % insn.reg_name(m), end=''), + print() + + if len(insn.groups) > 0: + print("\tThis instruction belongs to groups: ", end=''), + for m in insn.groups: + print("%s " % insn.group_name(m), end=''), + print() + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment, syntax) in all_tests: + print('*' * 40) + print("Platform: %s" % comment) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + + if syntax is not None: + md.syntax = syntax + + for insn in md.disasm(code, 0x1000): + print_detail(insn) + + print() + except CsError as e: + print("ERROR: %s" % e) + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_evm.py b/white_patch_detect/capstone-master/bindings/python/test_evm.py new file mode 100644 index 0000000..345424f --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_evm.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * + +cs = Cs(CS_ARCH_EVM, 0) +cs.detail = True + +for i in cs.disasm("\x60\x61\x55", 0x100): + print("0x%x:\t%s\t%s" %(i.address, i.mnemonic, i.op_str)) + if i.pop > 0: + print("\tPop: %u" %i.pop) + if i.push > 0: + print("\tPush: %u" %i.push) + if i.fee > 0: + print("\tGas fee: %u" %i.fee) + if len(i.groups) > 0: + print("\tThis instruction belongs to groups: ", end=''), + for m in i.groups: + print("%s " % i.group_name(m), end=''), + print() diff --git a/white_patch_detect/capstone-master/bindings/python/test_lite.py b/white_patch_detect/capstone-master/bindings/python/test_lite.py new file mode 100644 index 0000000..41b16ca --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_lite.py @@ -0,0 +1,99 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +from capstone import * +from xprint import to_hex + + +X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" +ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" +THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +THUMB_MCLASS = b"\xef\xf3\x02\x80" +ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" +MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" +ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" +PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" +M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM), + (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None), + (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None), + (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None), + (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None), + (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None), + (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None), + (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None), + (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None), + (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None), + (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), + ) + + +# ## Test cs_disasm_quick() +def test_cs_disasm_quick(): + for (arch, mode, code, comment, syntax) in all_tests: + print('*' * 40) + print("Platform: %s" % comment) + print("Disasm:"), + print(to_hex(code)) + for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000): + print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str)) + print() + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment, syntax) in all_tests: + print('*' * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + + if syntax is not None: + md.syntax = syntax + + for (addr, size, mnemonic, op_str) in md.disasm_lite(code, 0x1000): + print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str)) + + print("0x%x:" % (addr + size)) + print() + except CsError as e: + print("ERROR: %s" % e) + + +# test_cs_disasm_quick() +# print "*" * 40 +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_m680x.py b/white_patch_detect/capstone-master/bindings/python/test_m680x.py new file mode 100644 index 0000000..0c0e973 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_m680x.py @@ -0,0 +1,159 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Wolfgang Schwotzer + +from __future__ import print_function +import sys +from capstone import * +from capstone.m680x import * +_python3 = sys.version_info.major == 3 + + +s_access = ( + "UNCHANGED", "READ", "WRITE", "READ | WRITE", + ) + +M6800_CODE = b"\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39" + +M6801_CODE = b"\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39" +M6805_CODE = b"\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe" +M6808_CODE = b"\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f" +HCS08_CODE = b"\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82" +HD6301_CODE = b"\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39" +M6809_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00" +M6811_CODE = b"\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f" +CPU12_CODE = b"\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00" +HD6309_CODE = b"\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00" + +all_tests = ( + (CS_ARCH_M680X, CS_MODE_M680X_6301, HD6301_CODE, "M680X_HD6301", None), + (CS_ARCH_M680X, CS_MODE_M680X_6309, HD6309_CODE, "M680X_HD6309", None), + (CS_ARCH_M680X, CS_MODE_M680X_6800, M6800_CODE, "M680X_M6800", None), + (CS_ARCH_M680X, CS_MODE_M680X_6801, M6801_CODE, "M680X_M6801", None), + (CS_ARCH_M680X, CS_MODE_M680X_6805, M6805_CODE, "M680X_M68HC05", None), + (CS_ARCH_M680X, CS_MODE_M680X_6808, M6808_CODE, "M680X_M68HC08", None), + (CS_ARCH_M680X, CS_MODE_M680X_6809, M6809_CODE, "M680X_M6809", None), + (CS_ARCH_M680X, CS_MODE_M680X_6811, M6811_CODE, "M680X_M68HC11", None), + (CS_ARCH_M680X, CS_MODE_M680X_CPU12, CPU12_CODE, "M680X_CPU12", None), + (CS_ARCH_M680X, CS_MODE_M680X_HCS08, HCS08_CODE, "M680X_HCS08", None), + ) + +# print hex dump from string all upper case +def to_hex_uc(string): + if _python3: + return " ".join("0x%02X" % c for c in string) + else: + return " ".join("0x%02X" % ord(c) for c in string) + +# print short hex dump from byte array all upper case +def to_hex_short_uc(byte_array): + return "".join("%02X" % b for b in byte_array) + +def print_insn_detail(insn): + # print address, mnemonic and operands + #print("0x%x:\t%s\t%s\t%s" % (insn.address, binascii.hexlify(bytearray(insn.bytes)), \ + print("0x%04X: %s\t%s\t%s" % (insn.address, to_hex_short_uc(insn.bytes), \ + insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == M680X_OP_REGISTER: + comment = ""; + if (((c == 0) and (insn.flags & M680X_FIRST_OP_IN_MNEM)) or + ((c == 1) and (insn.flags & M680X_SECOND_OP_IN_MNEM))): + comment = " (in mnemonic)"; + print("\t\toperands[%u].type: REGISTER = %s%s" % (c, + insn.reg_name(i.reg), comment)) + if i.type == M680X_OP_CONSTANT: + print("\t\toperands[%u].type: CONSTANT = %u" % (c, i.const_val)) + if i.type == M680X_OP_IMMEDIATE: + print("\t\toperands[%u].type: IMMEDIATE = #%d" % (c, i.imm)) + if i.type == M680X_OP_DIRECT: + print("\t\toperands[%u].type: DIRECT = 0x%02X" % (c, i.direct_addr)) + if i.type == M680X_OP_EXTENDED: + if i.ext.indirect: + indirect = "INDIRECT" + else: + indirect = "" + print("\t\toperands[%u].type: EXTENDED %s = 0x%04X" % (c, indirect, i.ext.address)) + if i.type == M680X_OP_RELATIVE: + print("\t\toperands[%u].type: RELATIVE = 0x%04X" % (c, i.rel.address)) + if i.type == M680X_OP_INDEXED: + if (i.idx.flags & M680X_IDX_INDIRECT): + indirect = " INDIRECT" + else: + indirect = "" + print("\t\toperands[%u].type: INDEXED%s" % (c, indirect)) + if i.idx.base_reg != M680X_REG_INVALID: + print("\t\t\tbase register: %s" % insn.reg_name(i.idx.base_reg)) + if i.idx.offset_reg != M680X_REG_INVALID: + print("\t\t\toffset register: %s" % insn.reg_name(i.idx.offset_reg)) + if (i.idx.offset_bits != 0) and (i.idx.offset_reg == M680X_REG_INVALID) and (i.idx.inc_dec == 0): + print("\t\t\toffset: %u" % i.idx.offset) + if i.idx.base_reg == M680X_REG_PC: + print("\t\t\toffset address: 0x%04X" % i.idx.offset_addr) + print("\t\t\toffset bits: %u" % i.idx.offset_bits) + if i.idx.inc_dec != 0: + if i.idx.flags & M680X_IDX_POST_INC_DEC: + s_post_pre = "post" + else: + s_post_pre = "pre" + if i.idx.inc_dec > 0: + s_inc_dec = "increment" + else: + s_inc_dec = "decrement" + print("\t\t\t%s %s: %d" % + (s_post_pre, s_inc_dec, abs(i.idx.inc_dec))) + if (i.size != 0): + print("\t\t\tsize: %d" % i.size) + if (i.access != CS_AC_INVALID): + print("\t\t\taccess: %s" % s_access[i.access]) + + c += 1 + + (regs_read, regs_write) = insn.regs_access() + + if len(regs_read) > 0: + print("\tRegisters read:", end="") + for r in regs_read: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if len(regs_write) > 0: + print("\tRegisters modified:", end="") + for r in regs_write: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if len(insn.groups) > 0: + print("\tgroups_count: %u" % len(insn.groups)) + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment, syntax) in all_tests: + print("*" * 20) + print("Platform: %s" % comment) + print("Code: %s" % to_hex_uc(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + if syntax is not None: + md.syntax = syntax + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_m68k.py b/white_patch_detect/capstone-master/bindings/python/test_m68k.py new file mode 100644 index 0000000..557369c --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_m68k.py @@ -0,0 +1,120 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nicolas PLANEL +from __future__ import print_function +from capstone import * +from capstone.m68k import * +from xprint import to_hex, to_x + +M68K_CODE = b"\x4c\x00\x54\x04\x48\xe7\xe0\x30\x4c\xdf\x0c\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4e\xb9\x00\x00\x00\x12\x4e\x75" + +all_tests = ( + (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"), +) + +s_addressing_modes = { + 0: "", + + 1: "Register Direct - Data", + 2: "Register Direct - Address", + + 3: "Register Indirect - Address", + 4: "Register Indirect - Address with Postincrement", + 5: "Register Indirect - Address with Predecrement", + 6: "Register Indirect - Address with Displacement", + + 7: "Address Register Indirect With Index - 8-bit displacement", + 8: "Address Register Indirect With Index - Base displacement", + + 9: "Memory indirect - Postindex", + 10: "Memory indirect - Preindex", + + 11: "Program Counter Indirect - with Displacement", + + 12: "Program Counter Indirect with Index - with 8-Bit Displacement", + 13: "Program Counter Indirect with Index - with Base Displacement", + + 14: "Program Counter Memory Indirect - Postindexed", + 15: "Program Counter Memory Indirect - Preindexed", + + 16: "Absolute Data Addressing - Short", + 17: "Absolute Data Addressing - Long", + 18: "Immediate value", + + 19: "Branch Displacement", +} + +def print_read_write_regs(insn): + for m in insn.regs_read: + print("\treading from reg: %s" % insn.reg_name(m)) + + for m in insn.regs_write: + print("\twriting to reg: %s" % insn.reg_name(m)) + +def print_insn_detail(insn): + if len(insn.operands) > 0: + print("\top_count: %u" % (len(insn.operands))) + print("\tgroups_count: %u" % len(insn.groups)) + + print_read_write_regs(insn) + + for i, op in enumerate(insn.operands): + if op.type == M68K_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (i, insn.reg_name(op.reg))) + elif op.type == M68K_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%x" % (i, op.imm & 0xffffffff)) + elif op.type == M68K_OP_MEM: + print("\t\toperands[%u].type: MEM" % (i)) + if op.mem.base_reg != M68K_REG_INVALID: + print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg))) + if op.mem.index_reg != M68K_REG_INVALID: + print("\t\t\toperands[%u].mem.index: REG = %s" % (i, insn.reg_name(op.mem.index_reg))) + mem_index_str = "w" + if op.mem.index_size > 0: + mem_index_str = "l" + print("\t\t\toperands[%u].mem.index: size = %s" % (i, mem_index_str)) + if op.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%x" % (i, op.mem.disp)) + if op.mem.scale != 0: + print("\t\t\toperands[%u].mem.scale: %d" % (i, op.mem.scale)) + print("\t\taddress mode: %s" % (s_addressing_modes[op.address_mode])) + elif op.type == M68K_OP_FP_SINGLE: + print("\t\toperands[%u].type: FP_SINGLE" % i) + print("\t\toperands[%u].simm: %f", i, op.simm) + elif op.type == M68K_OP_FP_DOUBLE: + print("\t\toperands[%u].type: FP_DOUBLE" % i) + print("\t\toperands[%u].dimm: %lf", i, op.dimm) + elif op.type == M68K_OP_BR_DISP: + print("\t\toperands[%u].br_disp.disp: 0x%x" % (i, op.br_disp.disp)) + print("\t\toperands[%u].br_disp.disp_size: %d" % (i, op.br_disp.disp_size)) + print() + +# ## Test class Cs +def test_class(): + address = 0x01000 + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s " % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + last_address = 0 + for insn in md.disasm(code, address): + last_address = insn.address + insn.size + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + print_insn_detail(insn) + print("0x%x:\n" % (last_address)) + + except CsError as e: + print("ERROR: %s" % e.__str__()) + +if __name__ == '__main__': + test_class() + + + + + diff --git a/white_patch_detect/capstone-master/bindings/python/test_mips.py b/white_patch_detect/capstone-master/bindings/python/test_mips.py new file mode 100644 index 0000000..976380c --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_mips.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +from capstone import * +from capstone.mips import * +from xprint import to_hex, to_x + + +MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" +MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" + +all_tests = ( + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"), + (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = -1 + for i in insn.operands: + c += 1 + if i.type == MIPS_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == MIPS_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == MIPS_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print() + + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_mos65xx.py b/white_patch_detect/capstone-master/bindings/python/test_mos65xx.py new file mode 100644 index 0000000..c9b831e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_mos65xx.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Sebastian Macke +from __future__ import print_function +from capstone import * +from capstone.mos65xx import * +from xprint import to_hex, to_x + +MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" + +address_modes=[ + 'No address mode', + 'implied addressing (no addressing mode)', + 'accumulator addressing', + 'absolute addressing', + 'zeropage addressing', + '8 Bit immediate value', + 'indexed absolute addressing by the X index register', + 'indexed absolute addressing by the Y index register', + 'indexed indirect addressing by the X index register', + 'indirect indexed addressing by the Y index register', + 'indexed zeropage addressing by the X index register', + 'indexed zeropage addressing by the Y index register', + 'relative addressing used by branches', + 'absolute indirect addressing' +]; + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + print("\taddress mode: %s" % (address_modes[insn.am])) + print("\tmodifies flags: %s" % ('true' if insn.modifies_flags != 0 else 'false')) + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = -1 + for i in insn.operands: + c += 1 + if i.type == MOS65XX_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == MOS65XX_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == MOS65XX_OP_MEM: + print("\t\toperands[%u].type: MEM = 0x%s" % (c, to_x(i.mem))) + + +# ## Test class Cs +def test_class(): + print("*" * 16) + print("Platform: %s" % "MOS65XX") + print("Code: %s" % to_hex(MOS65XX_CODE)) + print("Disasm:") + + try: + md = Cs(CS_ARCH_MOS65XX, 0) + md.detail = True + for insn in md.disasm(MOS65XX_CODE, 0x1000): + print_insn_detail(insn) + print() + + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_ppc.py b/white_patch_detect/capstone-master/bindings/python/test_ppc.py new file mode 100644 index 0000000..1a069ba --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_ppc.py @@ -0,0 +1,83 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +from capstone import * +from capstone.ppc import * +from xprint import to_hex, to_x_32 + +PPC_CODE = b"\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" + +all_tests = ( + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX"), + ) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == PPC_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == PPC_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) + if i.type == PPC_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x_32(i.mem.disp))) + if i.type == PPC_OP_CRX: + print("\t\toperands[%u].type: CRX" % c) + print("\t\t\toperands[%u].crx.scale: = %u" \ + % (c, i.crx.scale)) + if i.crx.reg != 0: + print("\t\t\toperands[%u].crx.reg: REG = %s" \ + % (c, insn.reg_name(i.crx.reg))) + if i.crx.cond != 0: + print("\t\t\toperands[%u].crx.cond: 0x%x" \ + % (c, i.crx.cond)) + c += 1 + + if insn.bc: + print("\tBranch code: %u" % insn.bc) + if insn.bh: + print("\tBranch hint: %u" % insn.bh) + if insn.update_cr0: + print("\tUpdate-CR0: True") + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_skipdata.py b/white_patch_detect/capstone-master/bindings/python/test_skipdata.py new file mode 100644 index 0000000..726a086 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_skipdata.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +import binascii +from xprint import to_hex + + +X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92" +RANDOM_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" + +all_tests = ( + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), + (CS_ARCH_ARM, CS_MODE_ARM, RANDOM_CODE, "Arm", None), +) + + +# Sample callback for SKIPDATA option +def testcb(buffer, size, offset, userdata): + # always skip 2 bytes of data + return 2 + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment, syntax) in all_tests: + print('*' * 16) + print("Platform: %s" %comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + + if syntax is not None: + md.syntax = syntax + + md.skipdata = True + + # Default "data" instruction's name is ".byte". To rename it to "db", just use + # the code below. + md.skipdata_setup = ("db", None, None) + + # NOTE: This example ignores SKIPDATA's callback (first None) & user_data (second None) + # Can also use dedicated setter + #md.skipdata_mnem = 'db' + + # To customize the SKIPDATA callback, use the line below. + #md.skipdata_setup = (".db", testcb, None) + + # Or use dedicated setter with custom parameter + #md.skipdata_callback = (testcb, 42) + + # Or provide just a function + #md.skipdata_callback = testcb + # Note that reading this property will always return a tuple + #assert md.skipdata_callback == (testcb, None) + + for insn in md.disasm(code, 0x1000): + #bytes = binascii.hexlify(insn.bytes) + #print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes)) + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + print("0x%x:" % (insn.address + insn.size)) + print + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_sparc.py b/white_patch_detect/capstone-master/bindings/python/test_sparc.py new file mode 100644 index 0000000..96fae5b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_sparc.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.sparc import * +from xprint import to_hex, to_x_32 + + +SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" + +all_tests = ( + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc"), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN+CS_MODE_V9, SPARCV9_CODE, "SparcV9"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == SPARC_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == SPARC_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm))) + if i.type == SPARC_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" \ + % (c, insn.reg_name(i.mem.index))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x_32(i.mem.disp))) + c += 1 + + if insn.cc: + print("\tCode condition: %u" % insn.cc) + if insn.hint: + print("\tHint code: %u" % insn.hint) + + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" %e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_systemz.py b/white_patch_detect/capstone-master/bindings/python/test_systemz.py new file mode 100644 index 0000000..ca9deb7 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_systemz.py @@ -0,0 +1,77 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.systemz import * +from xprint import to_x, to_hex + + +SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" + +all_tests = ( + (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == SYSZ_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == SYSZ_OP_ACREG: + print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg)) + if i.type == SYSZ_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == SYSZ_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" \ + % (c, insn.reg_name(i.mem.index))) + if i.mem.length != 0: + print("\t\t\toperands[%u].mem.length: 0x%s" \ + % (c, to_x(i.mem.length))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + c += 1 + + if insn.cc: + print("\tConditional code: %u" % insn.cc) + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" %comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" %e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_tms320c64x.py b/white_patch_detect/capstone-master/bindings/python/test_tms320c64x.py new file mode 100644 index 0000000..4960401 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_tms320c64x.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Fotis Loukos + +from __future__ import print_function +from capstone import * +from capstone.tms320c64x import * +from xprint import to_x, to_hex, to_x_32 + + +TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" + +all_tests = ( + (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == TMS320C64X_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == TMS320C64X_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == TMS320C64X_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.disptype == TMS320C64X_MEM_DISP_INVALID: + print("\t\t\toperands[%u].mem.disptype: Invalid" % (c)) + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + if i.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT: + print("\t\t\toperands[%u].mem.disptype: Constant" % (c)) + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + if i.mem.disptype == TMS320C64X_MEM_DISP_REGISTER: + print("\t\t\toperands[%u].mem.disptype: Register" % (c)) + print("\t\t\toperands[%u].mem.disp: %s" \ + % (c, insn.reg_name(i.mem.disp))) + print("\t\t\toperands[%u].mem.unit: %u" % (c, i.mem.unit)) + if i.mem.direction == TMS320C64X_MEM_DIR_INVALID: + print("\t\t\toperands[%u].mem.direction: Invalid" % (c)) + if i.mem.direction == TMS320C64X_MEM_DIR_FW: + print("\t\t\toperands[%u].mem.direction: Forward" % (c)) + if i.mem.direction == TMS320C64X_MEM_DIR_BW: + print("\t\t\toperands[%u].mem.direction: Backward" % (c)) + if i.mem.modify == TMS320C64X_MEM_MOD_INVALID: + print("\t\t\toperands[%u].mem.modify: Invalid" % (c)) + if i.mem.modify == TMS320C64X_MEM_MOD_NO: + print("\t\t\toperands[%u].mem.modify: No" % (c)) + if i.mem.modify == TMS320C64X_MEM_MOD_PRE: + print("\t\t\toperands[%u].mem.modify: Pre" % (c)) + if i.mem.modify == TMS320C64X_MEM_MOD_POST: + print("\t\t\toperands[%u].mem.modify: Post" % (c)) + print("\t\t\toperands[%u].mem.scaled: %u" % (c, i.mem.scaled)) + if i.type == TMS320C64X_OP_REGPAIR: + print("\t\toperands[%u].type: REGPAIR = %s:%s" % (c, insn.reg_name(i.reg + 1), insn.reg_name(i.reg))) + c += 1 + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" %comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" %e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_x86.py b/white_patch_detect/capstone-master/bindings/python/test_x86.py new file mode 100644 index 0000000..2dd74a1 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_x86.py @@ -0,0 +1,292 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +from capstone import * +from capstone.x86 import * +from xprint import to_hex, to_x, to_x_32 + + +X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" +X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc" +X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None), + (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None), + ) + + +def get_eflag_name(eflag): + if eflag == X86_EFLAGS_UNDEFINED_OF: + return "UNDEF_OF" + elif eflag == X86_EFLAGS_UNDEFINED_SF: + return "UNDEF_SF" + elif eflag == X86_EFLAGS_UNDEFINED_ZF: + return "UNDEF_ZF" + elif eflag == X86_EFLAGS_MODIFY_AF: + return "MOD_AF" + elif eflag == X86_EFLAGS_UNDEFINED_PF: + return "UNDEF_PF" + elif eflag == X86_EFLAGS_MODIFY_CF: + return "MOD_CF" + elif eflag == X86_EFLAGS_MODIFY_SF: + return "MOD_SF" + elif eflag == X86_EFLAGS_MODIFY_ZF: + return "MOD_ZF" + elif eflag == X86_EFLAGS_UNDEFINED_AF: + return "UNDEF_AF" + elif eflag == X86_EFLAGS_MODIFY_PF: + return "MOD_PF" + elif eflag == X86_EFLAGS_UNDEFINED_CF: + return "UNDEF_CF" + elif eflag == X86_EFLAGS_MODIFY_OF: + return "MOD_OF" + elif eflag == X86_EFLAGS_RESET_OF: + return "RESET_OF" + elif eflag == X86_EFLAGS_RESET_CF: + return "RESET_CF" + elif eflag == X86_EFLAGS_RESET_DF: + return "RESET_DF" + elif eflag == X86_EFLAGS_RESET_IF: + return "RESET_IF" + elif eflag == X86_EFLAGS_TEST_OF: + return "TEST_OF" + elif eflag == X86_EFLAGS_TEST_SF: + return "TEST_SF" + elif eflag == X86_EFLAGS_TEST_ZF: + return "TEST_ZF" + elif eflag == X86_EFLAGS_TEST_PF: + return "TEST_PF" + elif eflag == X86_EFLAGS_TEST_CF: + return "TEST_CF" + elif eflag == X86_EFLAGS_RESET_SF: + return "RESET_SF" + elif eflag == X86_EFLAGS_RESET_AF: + return "RESET_AF" + elif eflag == X86_EFLAGS_RESET_TF: + return "RESET_TF" + elif eflag == X86_EFLAGS_RESET_NT: + return "RESET_NT" + elif eflag == X86_EFLAGS_PRIOR_OF: + return "PRIOR_OF" + elif eflag == X86_EFLAGS_PRIOR_SF: + return "PRIOR_SF" + elif eflag == X86_EFLAGS_PRIOR_ZF: + return "PRIOR_ZF" + elif eflag == X86_EFLAGS_PRIOR_AF: + return "PRIOR_AF" + elif eflag == X86_EFLAGS_PRIOR_PF: + return "PRIOR_PF" + elif eflag == X86_EFLAGS_PRIOR_CF: + return "PRIOR_CF" + elif eflag == X86_EFLAGS_PRIOR_TF: + return "PRIOR_TF" + elif eflag == X86_EFLAGS_PRIOR_IF: + return "PRIOR_IF" + elif eflag == X86_EFLAGS_PRIOR_DF: + return "PRIOR_DF" + elif eflag == X86_EFLAGS_TEST_NT: + return "TEST_NT" + elif eflag == X86_EFLAGS_TEST_DF: + return "TEST_DF" + elif eflag == X86_EFLAGS_RESET_PF: + return "RESET_PF" + elif eflag == X86_EFLAGS_PRIOR_NT: + return "PRIOR_NT" + elif eflag == X86_EFLAGS_MODIFY_TF: + return "MOD_TF" + elif eflag == X86_EFLAGS_MODIFY_IF: + return "MOD_IF" + elif eflag == X86_EFLAGS_MODIFY_DF: + return "MOD_DF" + elif eflag == X86_EFLAGS_MODIFY_NT: + return "MOD_NT" + elif eflag == X86_EFLAGS_MODIFY_RF: + return "MOD_RF" + elif eflag == X86_EFLAGS_SET_CF: + return "SET_CF" + elif eflag == X86_EFLAGS_SET_DF: + return "SET_DF" + elif eflag == X86_EFLAGS_SET_IF: + return "SET_IF" + else: + return None + + +def print_insn_detail(mode, insn): + def print_string_hex(comment, str): + print(comment, end=' '), + for c in str: + print("0x%02x " % c, end=''), + print() + + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + # print instruction prefix + print_string_hex("\tPrefix:", insn.prefix) + + # print instruction's opcode + print_string_hex("\tOpcode:", insn.opcode) + + # print operand's REX prefix (non-zero value is relavant for x86_64 instructions) + print("\trex: 0x%x" % (insn.rex)) + + # print operand's address size + print("\taddr_size: %u" % (insn.addr_size)) + + # print modRM byte + print("\tmodrm: 0x%x" % (insn.modrm)) + + # print modRM offset + if insn.modrm_offset != 0: + print("\tmodrm_offset: 0x%x" % (insn.modrm_offset)) + + # print displacement value + print("\tdisp: 0x%s" % to_x_32(insn.disp)) + + # print displacement offset (offset into instruction bytes) + if insn.disp_offset != 0: + print("\tdisp_offset: 0x%x" % (insn.disp_offset)) + + # print displacement size + if insn.disp_size != 0: + print("\tdisp_size: 0x%x" % (insn.disp_size)) + + # SIB is not available in 16-bit mode + if (mode & CS_MODE_16 == 0): + # print SIB byte + print("\tsib: 0x%x" % (insn.sib)) + if (insn.sib): + if insn.sib_base != 0: + print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base))) + if insn.sib_index != 0: + print("\t\tsib_index: %s" % (insn.reg_name(insn.sib_index))) + if insn.sib_scale != 0: + print("\t\tsib_scale: %d" % (insn.sib_scale)) + + # XOP CC type + if insn.xop_cc != X86_XOP_CC_INVALID: + print("\txop_cc: %u" % (insn.xop_cc)) + + # SSE CC type + if insn.sse_cc != X86_SSE_CC_INVALID: + print("\tsse_cc: %u" % (insn.sse_cc)) + + # AVX CC type + if insn.avx_cc != X86_AVX_CC_INVALID: + print("\tavx_cc: %u" % (insn.avx_cc)) + + # AVX Suppress All Exception + if insn.avx_sae: + print("\tavx_sae: TRUE") + + # AVX Rounding Mode type + if insn.avx_rm != X86_AVX_RM_INVALID: + print("\tavx_rm: %u" % (insn.avx_rm)) + + count = insn.op_count(X86_OP_IMM) + if count > 0: + print("\timm_count: %u" % count) + for i in range(count): + op = insn.op_find(X86_OP_IMM, i + 1) + print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm))) + if insn.imm_offset != 0: + print("\timm_offset: 0x%x" % (insn.imm_offset)) + if insn.imm_size != 0: + print("\timm_size: 0x%x" % (insn.imm_size)) + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = -1 + for i in insn.operands: + c += 1 + if i.type == X86_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == X86_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == X86_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.segment != 0: + print("\t\t\toperands[%u].mem.segment: REG = %s" % (c, insn.reg_name(i.mem.segment))) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index))) + if i.mem.scale != 1: + print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale)) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp))) + + # AVX broadcast type + if i.avx_bcast != X86_AVX_BCAST_INVALID: + print("\t\toperands[%u].avx_bcast: %u" % (c, i.avx_bcast)) + + # AVX zero opmask {z} + if i.avx_zero_opmask: + print("\t\toperands[%u].avx_zero_opmask: TRUE" % (c)) + + print("\t\toperands[%u].size: %u" % (c, i.size)) + + if i.access == CS_AC_READ: + print("\t\toperands[%u].access: READ\n" % (c)) + elif i.access == CS_AC_WRITE: + print("\t\toperands[%u].access: WRITE\n" % (c)) + elif i.access == CS_AC_READ | CS_AC_WRITE: + print("\t\toperands[%u].access: READ | WRITE\n" % (c)) + + (regs_read, regs_write) = insn.regs_access() + + if len(regs_read) > 0: + print("\tRegisters read:", end="") + for r in regs_read: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if len(regs_write) > 0: + print("\tRegisters modified:", end="") + for r in regs_write: + print(" %s" %(insn.reg_name(r)), end="") + print("") + + if insn.eflags: + updated_flags = [] + for i in range(0,46): + if insn.eflags & (1 << i): + updated_flags.append(get_eflag_name(1 << i)) + print("\tEFLAGS: %s" % (','.join(p for p in updated_flags))) + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment, syntax) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + + if syntax is not None: + md.syntax = syntax + + for insn in md.disasm(code, 0x1000): + print_insn_detail(mode, insn) + print () + print ("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/test_xcore.py b/white_patch_detect/capstone-master/bindings/python/test_xcore.py new file mode 100644 index 0000000..0460a6d --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/test_xcore.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +from capstone import * +from capstone.xcore import * +from xprint import to_x, to_hex + + +XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" + +all_tests = ( + (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == XCORE_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == XCORE_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == XCORE_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" \ + % (c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" \ + % (c, insn.reg_name(i.mem.index))) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" \ + % (c, to_x(i.mem.disp))) + if i.mem.direct != 1: + print("\t\t\toperands[%u].mem.direct: -1" % c) + c += 1 + + +# ## Test class Cs +def test_class(): + + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" %comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print () + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" %e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/bindings/python/xprint.py b/white_patch_detect/capstone-master/bindings/python/xprint.py new file mode 100644 index 0000000..70affac --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/python/xprint.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python +# Capstone Python bindings, by Nguyen Anh Quynnh + +from __future__ import print_function +import sys +_python3 = sys.version_info.major == 3 + + +def to_hex(s, prefix_0x = True): + if _python3: + if prefix_0x: + return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + return " ".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + if prefix_0x: + return " ".join("0x{0:02x}".format(ord(c)) for c in s) + else: + return " ".join("{0:02x}".format(ord(c)) for c in s) + +def to_hex2(s): + if _python3: + r = "".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + r = "".join("{0:02x}".format(ord(c)) for c in s) + while r[0] == '0': r = r[1:] + return r + +def to_x(s): + from struct import pack + if not s: return '0' + x = pack(">q", s) + while x[0] in ('\0', 0): x = x[1:] + return to_hex2(x) + +def to_x_32(s): + from struct import pack + if not s: return '0' + x = pack(">i", s) + while x[0] in ('\0', 0): x = x[1:] + return to_hex2(x) diff --git a/white_patch_detect/capstone-master/bindings/vb6/CDisassembler.cls b/white_patch_detect/capstone-master/bindings/vb6/CDisassembler.cls new file mode 100644 index 0000000..468e97e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CDisassembler.cls @@ -0,0 +1,153 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CDisassembler" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +'NOTE: the VB code was built and tested against Capstone v3.0 rc4 +' if the capstone C structures change, the VB code will have to +' be adjusted to match! +' +' instructions details are currently only implemented for x86 + +Public arch As cs_arch +Public mode As cs_mode +Public hCapstone As Long +Public hLib As Long + +Public version As String +Public vMajor As Long +Public vMinor As Long + +Public errMsg As String +Public lastErr As cs_err + +Private Function CheckPath(pth As String) As Long + + Dim hCap As Long, capPth As String, shimPth As String + + shimPth = pth & "\vbCapstone.dll" + capPth = pth & "\capstone.dll" + + If Not FileExists(shimPth) Then Exit Function + + hCap = LoadLibrary(capPth) + If hCap = 0 Then hCap = LoadLibrary("capstone.dll") + If hCap = 0 Then errMsg = "Could not find capstone.dll" + + CheckPath = LoadLibrary(shimPth) + 'If CheckPath = 0 Then MsgBox Err.LastDllError + +End Function + +Public Function init(arch As cs_arch, mode As cs_mode, Optional enableDetails As Boolean = False) As Boolean + + errMsg = Empty + hLib = GetModuleHandle("vbCapstone.dll") + + If hLib = 0 Then hLib = CheckPath(App.path & "\bin\") + If hLib = 0 Then hLib = CheckPath(App.path & "\") + If hLib = 0 Then hLib = CheckPath(App.path & "\..\") + If hLib = 0 Then hLib = LoadLibrary("vbCapstone.dll") + + If hLib = 0 Then + errMsg = errMsg & " Could not load vbCapstone.dll" + Exit Function + End If + + Me.arch = arch + Me.mode = mode + + cs_version vMajor, vMinor + version = vMajor & "." & vMinor + + If cs_support(arch) = 0 Then + errMsg = "specified architecture not supported" + Exit Function + End If + + Dim handle As Long 'in vb class a public var is actually a property get/set can not use as byref to api.. + lastErr = cs_open(arch, mode, handle) + If lastErr <> CS_ERR_OK Then + errMsg = err2str(lastErr) + Exit Function + End If + + hCapstone = handle + If enableDetails Then 'vb bindings currently only support details for x86 + If arch = CS_ARCH_X86 Then + cs_option handle, CS_OPT_DETAIL, CS_OPT_ON + End If + End If + + init = True + +End Function + +'base is a variant and currently accepts the following input types: +' x64 number held as currency type (ex. makeCur(&haabbccdd, &h11223344) ) +' int/long value (ex. &h1000 or 12345) +' numeric string or 0x/&h prefixed hex string (ex. "12345", "0x1200", "&haabbccdd") +Function disasm(ByVal base, code() As Byte, Optional count As Long = 0) As Collection + + Dim c As Long + Dim instAry As Long + Dim ret As New Collection + Dim ci As CInstruction + Dim i As Long + Dim address As Currency + + On Error Resume Next + + Set disasm = ret + + If TypeName(base) = "Currency" Then + address = base + Else + If TypeName(base) = "String" Then base = Replace(Trim(base), "0x", "&h") + address = lng2Cur(CLng(base)) + If Err.Number <> 0 Then + errMsg = "Could not convert base address to long" + Exit Function + End If + End If + + c = cs_disasm(Me.hCapstone, code(0), UBound(code) + 1, address, count, instAry) + If c = 0 Then Exit Function + + For i = 0 To c - 1 + Set ci = New CInstruction + ci.LoadInstruction instAry, i, Me + ret.Add ci + Next + + cs_free instAry, c + +End Function + + +Private Sub Class_Terminate() + Dim msg As String + If DEBUG_DUMP Then + msg = "CDissembler.Terminate " & Hex(hCapstone) + If hCapstone <> 0 Then lastErr = cs_close(hCapstone) + Debug.Print msg & " : " & lastErr + End If +End Sub + diff --git a/white_patch_detect/capstone-master/bindings/vb6/CInstDetails.cls b/white_patch_detect/capstone-master/bindings/vb6/CInstDetails.cls new file mode 100644 index 0000000..c63a4f4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CInstDetails.cls @@ -0,0 +1,119 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CInstDetails" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + +'Public Type cs_detail +' regs_read(0 To 15) As Byte ' list of implicit registers read by this insn UNSIGNED +' regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED +' regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED +' regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED +' groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED +' groups_count As Byte ' number of groups this insn belongs to UNSIGNED +' +' // Architecture-specific instruction info +' union { +' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode +' cs_arm64 arm64; // ARM64 architecture (aka AArch64) +' cs_arm arm; // ARM architecture (including Thumb/Thumb2) +' cs_mips mips; // MIPS architecture +' cs_ppc ppc; // PowerPC architecture +' cs_sparc sparc; // Sparc architecture +' cs_sysz sysz; // SystemZ architecture +' cs_xcore xcore; // XCore architecture +' }; +'} cs_detail; + +Public regRead As New Collection +Public regWritten As New Collection +Public groups As New Collection +Public parent As CDisassembler + +'this will be set to a class of the specific instruction info type by architecture.. +Public info As Object + +Private m_raw() As Byte + +Function toString() As String + + On Error Resume Next + + Dim ret() As String + Dim v, tmp + + push ret, "Instruction details: " + push ret, String(40, "-") + + If DEBUG_DUMP Then + push ret, "Raw: " + push ret, HexDump(m_raw) + End If + + push ret, "Registers Read: " & regRead.count & IIf(regRead.count > 0, " Values: " & col2Str(regRead), Empty) + push ret, "Registers Written: " & regWritten.count & IIf(regWritten.count > 0, " Values: " & col2Str(regWritten), Empty) + push ret, "Groups: " & groups.count & IIf(groups.count > 0, " Values: " & col2Str(groups), Empty) + + 'it is expected that each CXXInst class implements a toString() method..if not we catch the error anyway.. + If Not info Is Nothing Then + push ret, info.toString() + End If + + toString = Join(ret, vbCrLf) + +End Function + +Friend Sub LoadDetails(lpDetails As Long, parent As CDisassembler) + + Dim cd As cs_detail + Dim i As Long + Dim x86 As CX86Inst + + Set Me.parent = parent + + 'vbdef only contains up to the groups_count field.. + CopyMemory ByVal VarPtr(cd), ByVal lpDetails, LenB(cd) + + If DEBUG_DUMP Then + ReDim m_raw(LenB(cd)) + CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpDetails, LenB(cd) + End If + + For i = 1 To cd.regs_read_count + regRead.Add cd.regs_read(i - 1) + Next + + For i = 1 To cd.regs_write_count + regWritten.Add cd.regs_write(i - 1) + Next + + For i = 1 To cd.groups_count + groups.Add cd.groups(i - 1) + Next + + Const align = 5 + + 'each arch needs its own CxxInstr class implemented here... + If parent.arch = CS_ARCH_X86 Then + Set x86 = New CX86Inst + x86.LoadDetails lpDetails + LenB(cd) + align, parent + Set info = x86 + End If + + + +End Sub diff --git a/white_patch_detect/capstone-master/bindings/vb6/CInstruction.cls b/white_patch_detect/capstone-master/bindings/vb6/CInstruction.cls new file mode 100644 index 0000000..e8a7b6b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CInstruction.cls @@ -0,0 +1,133 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CInstruction" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +'Public Type cs_insn +' ' Instruction ID (basically a numeric ID for the instruction mnemonic) +' ' Find the instruction id in the '[ARCH]_insn' enum in the header file +' ' of corresponding architecture, such as 'arm_insn' in arm.h for ARM, +' ' 'x86_insn' in x86.h for X86, etc... +' ' available even when CS_OPT_DETAIL = CS_OPT_OFF +' ' NOTE: in Skipdata mode, "data" instruction has 0 for this id field. UNSIGNED +' id As Long ' +' align As Long 'not sure why it needs this..but it does.. +' address As Currency ' Address (EIP) of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED +' size As Integer ' Size of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED +' bytes(0 To 23) As Byte ' Machine bytes of this instruction, with number of bytes indicated by @size above available even when CS_OPT_DETAIL = CS_OPT_OFF +' mnemonic(0 To 31) As Byte ' Ascii text of instruction mnemonic available even when CS_OPT_DETAIL = CS_OPT_OFF +' op_str(0 To 159) As Byte ' Ascii text of instruction operands available even when CS_OPT_DETAIL = CS_OPT_OFF +' +' ' Pointer to cs_detail. +' ' NOTE: detail pointer is only valid when both requirements below are met: +' ' (1) CS_OP_DETAIL = CS_OPT_ON +' ' (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON) +' ' NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer +' ' is not NULL, its content is still irrelevant. +' lpDetail As Long ' points to a cs_detail structure NOTE: only available when CS_OPT_DETAIL = CS_OPT_ON +' +'End Type + +Public ID As Long +Public address As Currency +Public size As Long +Private m_bytes() As Byte +Public instruction As String +Public operand As String +Public lpDetails As Long +Public parent As CDisassembler + +Public details As CInstDetails 'may be null + +Property Get bytes() As Byte() + bytes = Me.bytes() +End Property + +Property Get byteDump(Optional padding = 15) As String + Dim b As String, i As Long + For i = 0 To UBound(m_bytes) + b = b & hhex(m_bytes(i)) & " " + Next + byteDump = rpad(b, padding) +End Property + +Property Get text() As String + + text = cur2str(address) & " " & byteDump & " " & instruction & " " & operand + +End Property + +Function toString() As String + + Dim r() As String + + push r, "CInstruction: " + push r, String(40, "-") + push r, "Id: " & Hex(ID) + push r, "address: " & cur2str(address) + push r, "size: " & Hex(size) + push r, "bytes: " & byteDump() + push r, "instruction: " & instruction + push r, "operand: " & operand + push r, "lpDetails: " & Hex(lpDetails) + + If Not details Is Nothing Then + push r, details.toString() + End If + + toString = Join(r, vbCrLf) + +End Function + +Friend Sub LoadInstruction(instAry As Long, index As Long, parent As CDisassembler) + + Dim inst As cs_insn + Dim i As Long + + getInstruction instAry, index, VarPtr(inst), LenB(inst) + + ID = inst.ID + address = inst.address + size = inst.size + lpDetails = inst.lpDetail + Set Me.parent = parent + + m_bytes() = inst.bytes + ReDim Preserve m_bytes(size - 1) + + For i = 0 To UBound(inst.mnemonic) + If inst.mnemonic(i) = 0 Then Exit For + instruction = instruction & Chr(inst.mnemonic(i)) + Next + + For i = 0 To UBound(inst.op_str) + If inst.op_str(i) = 0 Then Exit For + operand = operand & Chr(inst.op_str(i)) + Next + + If lpDetails = 0 Then Exit Sub + Set details = New CInstDetails + details.LoadDetails lpDetails, parent + +End Sub + + + + diff --git a/white_patch_detect/capstone-master/bindings/vb6/CX86Inst.cls b/white_patch_detect/capstone-master/bindings/vb6/CX86Inst.cls new file mode 100644 index 0000000..61fd840 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CX86Inst.cls @@ -0,0 +1,197 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CX86Inst" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +'// Instruction structure sizeof() = 432 bytes +'typedef struct cs_x86 { +' // Instruction prefix, which can be up to 4 bytes. +' // A prefix byte gets value 0 when irrelevant. +' // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) +' // prefix[1] indicates segment override (irrelevant for x86_64): +' // See X86_PREFIX_CS/SS/DS/ES/FS/GS above. +' // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) +' // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) +' uint8_t prefix[4]; +' +' // Instruction opcode, wich can be from 1 to 4 bytes in size. +' // This contains VEX opcode as well. +' // An trailing opcode byte gets value 0 when irrelevant. +' uint8_t opcode[4]; +' +' // REX prefix: only a non-zero value is relavant for x86_64 +' uint8_t rex; +' +' // Address size, which can be overrided with above prefix[5]. +' uint8_t addr_size; +' +' // ModR/M byte +' uint8_t modrm; +' +' // SIB value, or 0 when irrelevant. +' uint8_t sib; +' +' // Displacement value, or 0 when irrelevant. +' int32_t disp; +' +' /* SIB state */ +' // SIB index register, or X86_REG_INVALID when irrelevant. +' x86_reg sib_index; +' // SIB scale. only applicable if sib_index is relavant. +' int8_t sib_scale; +' // SIB base register, or X86_REG_INVALID when irrelevant. +' x86_reg sib_base; +' +' // SSE Code Condition +' x86_sse_cc sse_cc; +' +' // AVX Code Condition +' x86_avx_cc avx_cc; +' +' // AVX Suppress all Exception +' bool avx_sae; +' +' // AVX static rounding mode +' x86_avx_rm avx_rm; +' +' // Number of operands of this instruction, +' // or 0 when instruction has no operand. +' uint8_t op_count; +' +' cs_x86_op operands[8]; // operands for this instruction. +'} cs_x86; + +Private m_prefix() As Byte +Private m_opcode() As Byte +Public rex As Byte +Public addr_size As Byte +Public modrm As Byte +Public sib As Byte +Public disp As Long +Public sib_index As x86_reg +Public sib_scale As Byte +Public sib_base As x86_reg +Public sse_cc As x86_sse_cc +Public avx_cc As x86_avx_cc +Public avx_sae As Boolean +Public avx_rm As x86_avx_rm +Public operands As New Collection + +Public parent As CDisassembler +Private hEngine As Long +Private m_raw() As Byte + +Property Get prefix() As Byte() + prefix = m_prefix +End Property + +Property Get opcode() As Byte() + opcode = m_opcode +End Property + +Function toString() As String + + Dim r() As String + Dim o As CX86Operand + + push r, "X86 Instruction Details:" + push r, String(40, "-") + + If DEBUG_DUMP Then + push r, "Raw: " + push r, HexDump(m_raw) + End If + + push r, "Prefix: " & b2Str(m_prefix) + push r, "OpCode: " & b2Str(m_opcode) + push r, "Rex: " & rex + push r, "addr_size: " & addr_size + push r, "modrm: " & Hex(modrm) + push r, "disp: " & Hex(disp) + + If parent.mode <> CS_MODE_16 Then + push r, "sib: " & Hex(sib) + push r, "sib_index: " & regName(hEngine, sib_index) + push r, "sib_scale: " & Hex(sib_scale) + push r, "sib_base: " & regName(hEngine, sib_base) + End If + + If sse_cc <> 0 Then push r, "sse_cc: " & x86_sse_cc2str(sse_cc) + If avx_cc <> 0 Then push r, "avx_cc: " & x86_avx_cc2str(avx_cc) + If avx_sae <> 0 Then push r, "avx_sae: " & avx_sae + If avx_rm <> 0 Then push r, "avx_rm: " & x86_avx_rm2str(avx_rm) + + push r, "Operands: " & operands.count + + For Each o In operands + push r, String(40, "-") + push r, o.toString + Next + + toString = Join(r, vbCrLf) + +End Function + +Friend Sub LoadDetails(lpStruct As Long, parent As CDisassembler) + + Dim cs As cs_x86 + Dim o As CX86Operand + Dim ptr As Long + Dim i As Long + + Const sizeOfx86Operand = 48 + + Set Me.parent = parent + hEngine = parent.hCapstone + + CopyMemory ByVal VarPtr(cs), ByVal lpStruct, LenB(cs) + + If DEBUG_DUMP Then + ReDim m_raw(LenB(cs)) + CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpStruct, LenB(cs) + End If + + Me.rex = cs.rex + Me.addr_size = cs.addr_size + Me.modrm = cs.modrm + Me.sib = cs.sib + Me.disp = cs.disp + Me.sib_index = cs.sib_index + Me.sib_scale = cs.sib_scale + Me.sib_base = cs.sib_base + Me.sse_cc = cs.sse_cc + Me.avx_cc = cs.avx_cc + Me.avx_sae = cs.avx_sae + Me.avx_rm = cs.avx_rm + m_prefix = cs.prefix + m_opcode = cs.opcode + + ptr = lpStruct + LenB(cs) 'we dont include the operands in our vb struct.. + For i = 1 To cs.op_count + Set o = New CX86Operand + o.LoadDetails ptr, hEngine + operands.Add o + ptr = ptr + sizeOfx86Operand + Next + + + +End Sub + diff --git a/white_patch_detect/capstone-master/bindings/vb6/CX86OpMem.cls b/white_patch_detect/capstone-master/bindings/vb6/CX86OpMem.cls new file mode 100644 index 0000000..21b6757 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CX86OpMem.cls @@ -0,0 +1,28 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CX86OpMem" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +Public segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED +Public base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED +Public index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED +Public scale_ As Long ' scale for index register +Public disp As Currency ' displacement value + diff --git a/white_patch_detect/capstone-master/bindings/vb6/CX86Operand.cls b/white_patch_detect/capstone-master/bindings/vb6/CX86Operand.cls new file mode 100644 index 0000000..210ec64 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/CX86Operand.cls @@ -0,0 +1,202 @@ +VERSION 1.0 CLASS +BEGIN + MultiUse = -1 'True + Persistable = 0 'NotPersistable + DataBindingBehavior = 0 'vbNone + DataSourceBehavior = 0 'vbNone + MTSTransactionMode = 0 'NotAnMTSObject +END +Attribute VB_Name = "CX86Operand" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = True +Attribute VB_PredeclaredId = False +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +'// Instruction operand sizeof() reports 48 bytes +'typedef struct cs_x86_op { +' x86_op_type type; // operand type +' +' union { +' x86_reg reg; // register value for REG operand +' int64_t imm; // immediate value for IMM operand +' double fp; // floating point value for FP operand +' x86_op_mem mem; // base/index/scale/disp value for MEM operand (24bytes max) +' }; +' +' // size of this operand (in bytes). +' uint8_t size; +' +' // AVX broadcast type, or 0 if irrelevant +' x86_avx_bcast avx_bcast; +' +' // AVX zero opmask {z} +' bool avx_zero_opmask; +'} cs_x86_op; + +'Instruction's operand referring to memory +'This is associated with X86_OP_MEM operand type above +'Public Type x86_op_mem +' segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED +' base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED +' index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED +' scale As Long ' scale for index register +' disp As Currency ' displacement value +'End Type + +'this shows the alignment padding used by compiler.. +' cs_x86_op op; +' op.type = (x86_op_type)1; +' op.reg = (x86_reg)2; +' op.avx_bcast = (x86_avx_bcast)3; +' op.avx_zero_opmask = 4; +' op.size = 0xaa; +' printf("&cs_x86_op = %x", &op); +' _asm int 3 +' +' +'0x0012FF34 01 00 00 00 cc cc cc cc 02 00 00 00 cc cc cc cc ....烫烫....烫烫 +'0x0012FF44 cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc 烫烫烫烫烫烫烫烫 +'0x0012FF54 aa cc cc cc 03 00 00 00 01 cc cc cc cc cc cc cc 烫.....烫烫烫 + +Public optype As x86_op_type +Public size As Byte +Public avx_bcast As x86_avx_bcast +Public avx_zero_opmask As Boolean + +'only one of the following will be set based on type +Public reg As x86_reg +Public fp As Currency +Public imm As Currency +Public mem As CX86OpMem + +Private hEngine As Long +Private m_raw() As Byte + +Function toString() As String + + Dim ret() As String + + push ret, "X86 Operand:" + push ret, String(45, "-") + + If DEBUG_DUMP Then + push ret, "Raw: " + push ret, HexDump(m_raw) + End If + + push ret, "Type: " & opStr() + push ret, "Size: " & size + If avx_bcast <> 0 Then push ret, "BCast: " & bcastStr() + If avx_zero_opmask Then push ret, "AvxOpMask: " & avx_zero_opmask + + If optype = X86_OP_FP Then + push ret, "FP: " & cur2str(fp) + ElseIf optype = X86_OP_IMM Then + push ret, "IMM: " & cur2str(imm) + ElseIf optype = x86_op_mem Then + If mem.base <> 0 Then push ret, "Base: " & regName(hEngine, mem.base) + If mem.index <> 0 Then push ret, "Index: " & regName(hEngine, mem.index) + If mem.scale_ <> 1 Then push ret, "Scale: " & Hex(mem.scale_) + If mem.segment <> 0 Then push ret, "Seg: " & regName(hEngine, mem.segment) + If mem.disp <> 0 Then push ret, "Disp: " & cur2str(mem.disp) + ElseIf optype = X86_OP_REG Then + push ret, "Reg: " & regName(hEngine, reg) + End If + + toString = Join(ret, vbCrLf) + +End Function + +Function opStr() As String + + If optype = X86_OP_FP Then opStr = "X86_OP_FP" + If optype = x86_op_mem Then opStr = "x86_op_mem" + If optype = X86_OP_IMM Then opStr = "X86_OP_IMM" + If optype = X86_OP_REG Then opStr = "X86_OP_REG" + If optype = X86_OP_INVALID Then opStr = "X86_OP_INVALID" + + If Len(opStr) = 0 Then + opStr = "Error: " & Hex(optype) + ElseIf DEBUG_DUMP Then + opStr = opStr & " (" & Hex(optype) & ")" + End If + +End Function + +Function bcastStr() As String + Dim r As String + + If avx_bcast = X86_AVX_BCAST_INVALID Then r = "X86_AVX_BCAST_INVALID" + If avx_bcast = X86_AVX_BCAST_2 Then r = "X86_AVX_BCAST_2" + If avx_bcast = X86_AVX_BCAST_4 Then r = "X86_AVX_BCAST_4" + If avx_bcast = X86_AVX_BCAST_8 Then r = "X86_AVX_BCAST_8" + If avx_bcast = X86_AVX_BCAST_16 Then r = "X86_AVX_BCAST_16" + + If Len(r) = 0 Then + r = "Unknown: " & Hex(avx_bcast) + ElseIf DEBUG_DUMP Then + r = r & " (" & Hex(avx_bcast) & ")" + End If + + bcastStr = r +End Function + + +Friend Sub LoadDetails(lpStruct As Long, hCapstone As Long) + + Dim opMem As x86_op_mem + Dim ptr As Long + + Const align4 = 4 + Const align3 = 3 + + hEngine = hCapstone + + If DEBUG_DUMP Then + ReDim m_raw(48) + CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpStruct, 48 + End If + + optype = readLng(lpStruct) + ptr = lpStruct + 4 + align4 + + If optype = X86_OP_FP Then + fp = readCur(ptr) + ElseIf optype = X86_OP_IMM Then + imm = readCur(ptr) + ElseIf optype = x86_op_mem Then + CopyMemory ByVal VarPtr(opMem), ByVal ptr, LenB(opMem) + Set mem = New CX86OpMem + mem.base = opMem.base + mem.disp = opMem.disp + mem.index = opMem.index + mem.scale_ = opMem.scale + mem.segment = opMem.segment + ElseIf optype = X86_OP_REG Then + reg = readLng(ptr) + End If + + ptr = ptr + LenB(opMem) + + size = readByte(ptr) + ptr = ptr + 1 + align3 + + avx_bcast = readLng(ptr) + ptr = ptr + 4 + + avx_zero_opmask = (readByte(ptr) = 1) + +End Sub + +Private Sub Class_Terminate() + 'looks like everything is freeing up ok + 'Debug.Print "Cx86Operand.Terminate" +End Sub diff --git a/white_patch_detect/capstone-master/bindings/vb6/Form1.frm b/white_patch_detect/capstone-master/bindings/vb6/Form1.frm new file mode 100644 index 0000000..99bbdf4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/Form1.frm @@ -0,0 +1,275 @@ +VERSION 5.00 +Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "mscomctl.ocx" +Begin VB.Form Form1 + Caption = "VB6 Bindings for Capstone Disassembly Engine - Contributed by FireEye FLARE Team" + ClientHeight = 7290 + ClientLeft = 60 + ClientTop = 345 + ClientWidth = 10275 + LinkTopic = "Form1" + ScaleHeight = 7290 + ScaleWidth = 10275 + StartUpPosition = 2 'CenterScreen + Begin VB.CommandButton Command2 + Caption = "Save" + Height = 375 + Left = 8760 + TabIndex = 8 + Top = 120 + Width = 1455 + End + Begin VB.CommandButton Command1 + Caption = " Arm 64" + Height = 375 + Index = 4 + Left = 6840 + TabIndex = 7 + Top = 120 + Width = 1455 + End + Begin VB.CommandButton Command1 + Caption = "Arm" + Height = 375 + Index = 3 + Left = 5160 + TabIndex = 6 + Top = 120 + Width = 1455 + End + Begin VB.CommandButton Command1 + Caption = "x86 64bit" + Height = 375 + Index = 2 + Left = 3480 + TabIndex = 5 + Top = 120 + Width = 1455 + End + Begin VB.CommandButton Command1 + Caption = "x86 16bit" + Height = 375 + Index = 0 + Left = 120 + TabIndex = 4 + Top = 120 + Width = 1455 + End + Begin VB.CommandButton Command1 + Caption = "x86 32bit" + Height = 375 + Index = 1 + Left = 1800 + TabIndex = 3 + Top = 120 + Width = 1455 + End + Begin MSComctlLib.ListView lv + Height = 2415 + Left = 120 + TabIndex = 2 + Top = 1440 + Width = 10095 + _ExtentX = 17806 + _ExtentY = 4260 + View = 3 + LabelEdit = 1 + LabelWrap = -1 'True + HideSelection = 0 'False + FullRowSelect = -1 'True + _Version = 393217 + ForeColor = -2147483640 + BackColor = -2147483643 + BorderStyle = 1 + Appearance = 1 + BeginProperty Font {0BE35203-8F91-11CE-9DE3-00AA004BB851} + Name = "Courier" + Size = 9.75 + Charset = 0 + Weight = 400 + Underline = 0 'False + Italic = 0 'False + Strikethrough = 0 'False + EndProperty + NumItems = 1 + BeginProperty ColumnHeader(1) {BDD1F052-858B-11D1-B16A-00C0F0283628} + Object.Width = 2540 + EndProperty + End + Begin VB.ListBox List1 + BeginProperty Font + Name = "Courier" + Size = 9.75 + Charset = 0 + Weight = 400 + Underline = 0 'False + Italic = 0 'False + Strikethrough = 0 'False + EndProperty + Height = 840 + Left = 120 + TabIndex = 1 + Top = 600 + Width = 10095 + End + Begin VB.TextBox Text1 + BeginProperty Font + Name = "Courier" + Size = 9.75 + Charset = 0 + Weight = 400 + Underline = 0 'False + Italic = 0 'False + Strikethrough = 0 'False + EndProperty + Height = 3375 + Left = 120 + MultiLine = -1 'True + ScrollBars = 3 'Both + TabIndex = 0 + Text = "Form1.frx":0000 + Top = 3840 + Width = 10095 + End +End +Attribute VB_Name = "Form1" +Attribute VB_GlobalNameSpace = False +Attribute VB_Creatable = False +Attribute VB_PredeclaredId = True +Attribute VB_Exposed = False +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + +Dim cap As CDisassembler +Dim lastSample As Long + +Private Sub Command1_Click(index As Integer) + + Dim code() As Byte, arch As cs_arch, mode As cs_mode + lastSample = index + + Const x86_code32 As String = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6" + Const X86_CODE16 As String = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6" + Const X86_CODE64 As String = "\x55\x48\x8b\x05\xb8\x13\x00\x00" + Const ARM_CODE As String = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" + Const ARM64_CODE As String = "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" + + Select Case index + Case 0: + arch = CS_ARCH_X86 + mode = CS_MODE_16 + code = toBytes(X86_CODE16) + Case 1: + arch = CS_ARCH_X86 + mode = CS_MODE_32 + code = toBytes(x86_code32) + Case 2: + arch = CS_ARCH_X86 + mode = CS_MODE_64 + code = toBytes(X86_CODE64) + + Case 3: + arch = CS_ARCH_ARM + mode = CS_MODE_ARM + code = toBytes(ARM_CODE) + + Case 4: + arch = CS_ARCH_ARM64 + mode = CS_MODE_ARM + code = toBytes(ARM64_CODE) + End Select + + + test code, arch, mode + +End Sub + +Private Sub test(code() As Byte, arch As cs_arch, mode As cs_mode) + + + Dim ret As Collection + Dim ci As CInstruction + Dim li As ListItem + + clearForm + If Not cap Is Nothing Then Set cap = Nothing + + Set cap = New CDisassembler + + If Not cap.init(arch, mode, True) Then + List1.AddItem "Failed to init engine: " & cap.errMsg + Exit Sub + End If + + List1.AddItem "Capstone loaded @ 0x" & Hex(cap.hLib) + List1.AddItem "hEngine: 0x" & Hex(cap.hCapstone) + List1.AddItem "Version: " & cap.version + + If cap.vMajor < 3 Then + List1.AddItem "Sample requires Capstone v3+" + Exit Sub + End If + + Set ret = cap.disasm(&H1000, code) + + For Each ci In ret + Set li = lv.ListItems.Add(, , ci.text) + Set li.Tag = ci + Next + +End Sub + +Private Sub Command2_Click() + + Dim fName() As String + Dim fPath As String + Dim t() As String + Dim li As ListItem + Dim ci As CInstruction + + On Error Resume Next + + If lastSample = -1 Then + MsgBox "Run a test first..." + Exit Sub + End If + + fName = Split("16b,32b,64b,Arm,Arm64", ",") + + fPath = App.path & "\vb" & fName(lastSample) & "Test.txt" + If FileExists(fPath) Then Kill fPath + + For Each li In lv.ListItems + push t, li.text + Set ci = li.Tag + push t, ci.toString() + push t, String(60, "-") + Next + + WriteFile fPath, Join(t, vbCrLf) + + MsgBox FileLen(fPath) & " bytes saved to: " & vbCrLf & vbCrLf & fPath + +End Sub + +Private Sub lv_ItemClick(ByVal Item As MSComctlLib.ListItem) + Dim ci As CInstruction + Set ci = Item.Tag + Text1 = ci.toString() +End Sub + +Function clearForm() + List1.Clear + lv.ListItems.Clear + Text1 = Empty +End Function + +Private Sub Form_Load() + lv.ColumnHeaders(1).Width = lv.Width + clearForm + lastSample = -1 +End Sub diff --git a/white_patch_detect/capstone-master/bindings/vb6/Form1.frx b/white_patch_detect/capstone-master/bindings/vb6/Form1.frx new file mode 100644 index 0000000..da8c0d9 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/Form1.frx @@ -0,0 +1 @@ +Text1 \ No newline at end of file diff --git a/white_patch_detect/capstone-master/bindings/vb6/Module1.bas b/white_patch_detect/capstone-master/bindings/vb6/Module1.bas new file mode 100644 index 0000000..0808276 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/Module1.bas @@ -0,0 +1,635 @@ +Attribute VB_Name = "mCapStone" +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + +'todo: cs_disasm_iter / skipdata + +'this is for my vb code and how much info it spits out in tostring methods.. +Global Const DEBUG_DUMP = 0 + +'Architecture type +Public Enum cs_arch + CS_ARCH_ARM = 0 ' ARM architecture (including Thumb, Thumb-2) + CS_ARCH_ARM64 ' ARM-64, also called AArch64 + CS_ARCH_MIPS ' Mips architecture + CS_ARCH_X86 ' X86 architecture (including x86 & x86-64) + CS_ARCH_PPC ' PowerPC architecture + CS_ARCH_SPARC ' Sparc architecture + CS_ARCH_SYSZ ' SystemZ architecture + CS_ARCH_XCORE ' XCore architecture + CS_ARCH_MAX + CS_ARCH_ALL = &HFFFF ' All architectures - for cs_support() +End Enum + +Public Enum cs_mode + CS_MODE_LITTLE_ENDIAN = 0 ' little-endian mode (default mode) + CS_MODE_ARM = 0 ' 32-bit ARM + CS_MODE_16 = 2 ' 16-bit mode (X86) + CS_MODE_32 = 4 ' 32-bit mode (X86) + CS_MODE_64 = 8 ' 64-bit mode (X86, PPC) + CS_MODE_THUMB = 16 ' ARM's Thumb mode, including Thumb-2 + CS_MODE_MCLASS = 32 ' ARM's Cortex-M series + CS_MODE_V8 = 64 ' ARMv8 A32 encodings for ARM + CS_MODE_MICRO = 16 ' MicroMips mode (MIPS) + CS_MODE_MIPS3 = 32 ' Mips III ISA + CS_MODE_MIPS32R6 = 64 ' Mips32r6 ISA + CS_MODE_MIPSGP64 = 128 ' General Purpose Registers are 64-bit wide (MIPS) + CS_MODE_V9 = 16 ' SparcV9 mode (Sparc) + CS_MODE_BIG_ENDIAN = &H80000000 ' big-endian mode + CS_MODE_MIPS32 = CS_MODE_32 ' Mips32 ISA (Mips) + CS_MODE_MIPS64 = CS_MODE_64 ' Mips64 ISA (Mips) +End Enum + +'Runtime option for the disassembled engine +Public Enum cs_opt_type + CS_OPT_SYNTAX = 1 ' Assembly output syntax + CS_OPT_DETAIL ' Break down instruction structure into details + CS_OPT_MODE ' Change engine's mode at run-time + CS_OPT_MEM ' User-defined dynamic memory related functions + CS_OPT_SKIPDATA ' Skip data when disassembling. Then engine is in SKIPDATA mode. + CS_OPT_SKIPDATA_SETUP ' Setup user-defined function for SKIPDATA option +End Enum + + +'Runtime option value (associated with option type above) +Public Enum cs_opt_value + CS_OPT_OFF = 0 ' Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. + CS_OPT_ON = 3 ' Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). + CS_OPT_SYNTAX_DEFAULT = 0 ' Default asm syntax (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_INTEL ' X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_ATT ' X86 ATT asm syntax (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_NOREGNAME ' Prints register name with only number (CS_OPT_SYNTAX) +End Enum + +'Common instruction operand types - to be consistent across all architectures. +Public Enum cs_op_type + CS_OP_INVALID = 0 ' uninitialized/invalid operand. + CS_OP_REG ' Register operand. + CS_OP_IMM ' Immediate operand. + CS_OP_MEM ' Memory operand. + CS_OP_FP ' Floating-Point operand. +End Enum + +'Common instruction groups - to be consistent across all architectures. +Public Enum cs_group_type + CS_GRP_INVALID = 0 ' uninitialized/invalid group. + CS_GRP_JUMP ' all jump instructions (conditional+direct+indirect jumps) + CS_GRP_CALL ' all call instructions + CS_GRP_RET ' all return instructions + CS_GRP_INT ' all interrupt instructions (int+syscall) + CS_GRP_IRET ' all interrupt return instructions +End Enum + + +'NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON +Public Type cs_detail + regs_read(0 To 15) As Byte ' list of implicit registers read by this insn UNSIGNED + regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED + regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED + regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED + groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED + groups_count As Byte ' number of groups this insn belongs to UNSIGNED +End Type + +'typedef struct cs_detail { +' uint8_t regs_read[16]; // list of implicit registers read by this insn +' uint8_t regs_read_count; // number of implicit registers read by this insn +' +' uint8_t regs_write[20]; // list of implicit registers modified by this insn +' uint8_t regs_write_count; // number of implicit registers modified by this insn +' +' uint8_t groups[8]; // list of group this instruction belong to +' uint8_t groups_count; // number of groups this insn belongs to +' +' // Architecture-specific instruction info +' union { +' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode +' cs_arm64 arm64; // ARM64 architecture (aka AArch64) +' cs_arm arm; // ARM architecture (including Thumb/Thumb2) +' cs_mips mips; // MIPS architecture +' cs_ppc ppc; // PowerPC architecture +' cs_sparc sparc; // Sparc architecture +' cs_sysz sysz; // SystemZ architecture +' cs_xcore xcore; // XCore architecture +' }; +'} cs_detail; + +'Detail information of disassembled instruction +Public Type cs_insn + ' Instruction ID (basically a numeric ID for the instruction mnemonic) + ' Find the instruction id in the '[ARCH]_insn' enum in the header file + ' of corresponding architecture, such as 'arm_insn' in arm.h for ARM, + ' 'x86_insn' in x86.h for X86, etc... + ' available even when CS_OPT_DETAIL = CS_OPT_OFF + ' NOTE: in Skipdata mode, "data" instruction has 0 for this id field. UNSIGNED + ID As Long ' + align As Long 'not sure why it needs this..but it does.. + address As Currency ' Address (EIP) of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED + size As Integer ' Size of this instruction available even when CS_OPT_DETAIL = CS_OPT_OFF UNSIGNED + bytes(0 To 23) As Byte ' Machine bytes of this instruction, with number of bytes indicated by @size above available even when CS_OPT_DETAIL = CS_OPT_OFF + mnemonic(0 To 31) As Byte ' Ascii text of instruction mnemonic available even when CS_OPT_DETAIL = CS_OPT_OFF + op_str(0 To 159) As Byte ' Ascii text of instruction operands available even when CS_OPT_DETAIL = CS_OPT_OFF + + ' Pointer to cs_detail. + ' NOTE: detail pointer is only valid when both requirements below are met: + ' (1) CS_OP_DETAIL = CS_OPT_ON + ' (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON) + ' NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer + ' is not NULL, its content is still irrelevant. + lpDetail As Long ' points to a cs_detail structure NOTE: only available when CS_OPT_DETAIL = CS_OPT_ON + +End Type + +'All type of errors encountered by Capstone API. +'These are values returned by cs_errno() +Public Enum cs_err + CS_ERR_OK = 0 ' No error: everything was fine + CS_ERR_MEM ' Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter() + CS_ERR_ARCH ' Unsupported architecture: cs_open() + CS_ERR_HANDLE ' Invalid handle: cs_op_count(), cs_op_index() + CS_ERR_CSH ' Invalid csh argument: cs_close(), cs_errno(), cs_option() + CS_ERR_MODE ' Invalid/unsupported mode: cs_open() + CS_ERR_OPTION ' Invalid/unsupported option: cs_option() + CS_ERR_DETAIL ' Information is unavailable because detail option is OFF + CS_ERR_MEMSETUP ' Dynamic memory management uninitialized (see CS_OPT_MEM) + CS_ERR_VERSION ' Unsupported version (bindings) + CS_ERR_DIET ' Access irrelevant data in "diet" engine + CS_ERR_SKIPDATA ' Access irrelevant data for "data" instruction in SKIPDATA mode + CS_ERR_X86_ATT ' X86 AT&T syntax is unsupported (opt-out at compile time) + CS_ERR_X86_INTEL ' X86 Intel syntax is unsupported (opt-out at compile time) +End Enum + + +'/* +' Return combined API version & major and minor version numbers. +' +' @major: major number of API version +' @minor: minor number of API version +' +' @return hexical number as (major << 8 | minor), which encodes both +' major & minor versions. +' NOTE: This returned value can be compared with version number made +' with macro CS_MAKE_VERSION +' +' For example, second API version would return 1 in @major, and 1 in @minor +' The return value would be 0x0101 +' +' NOTE: if you only care about returned value, but not major and minor values, +' set both @major & @minor arguments to NULL. +'*/ +'CAPSTONE_EXPORT +'unsigned int cs_version(int *major, int *minor); +Public Declare Function cs_version Lib "vbCapstone.dll" Alias "bs_version" (ByRef major As Long, ByRef minor As Long) As Long + + + +' +'/* +' This API can be used to either ask for archs supported by this library, +' or check to see if the library was compile with 'diet' option (or called +' in 'diet' mode). +' +' To check if a particular arch is supported by this library, set @query to +' arch mode (CS_ARCH_* value). +' To verify if this library supports all the archs, use CS_ARCH_ALL. +' +' To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET. +' +' @return True if this library supports the given arch, or in 'diet' mode. +'*/ +'CAPSTONE_EXPORT +'bool cs_support(int query); +Public Declare Function cs_support Lib "vbCapstone.dll" Alias "bs_support" (ByVal query As Long) As Long + + + +'/* +' Initialize CS handle: this must be done before any usage of CS. +' +' @arch: architecture type (CS_ARCH_*) +' @mode: hardware mode. This is combined of CS_MODE_* +' @handle: pointer to handle, which will be updated at return time +' +' @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum +' for detailed error). +'*/ +'CAPSTONE_EXPORT +'cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle); +Public Declare Function cs_open Lib "vbCapstone.dll" Alias "bs_open" (ByVal arch As cs_arch, ByVal mode As cs_mode, ByRef hEngine As Long) As cs_err + + +'/* +' Close CS handle: MUST do to release the handle when it is not used anymore. +' NOTE: this must be only called when there is no longer usage of Capstone, +' not even access to cs_insn array. The reason is the this API releases some +' cached memory, thus access to any Capstone API after cs_close() might crash +' your application. +' +' In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0). +' +' @handle: pointer to a handle returned by cs_open() +' +' @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum +' for detailed error). +'*/ +'CAPSTONE_EXPORT +'cs_err cs_close(csh *handle); +Public Declare Function cs_close Lib "vbCapstone.dll" Alias "bs_close" (ByRef hEngine As Long) As cs_err + + + +'/* +' Set option for disassembling engine at runtime +' +' @handle: handle returned by cs_open() +' @type: type of option to be set +' @value: option value corresponding with @type +' +' @return: CS_ERR_OK on success, or other value on failure. +' Refer to cs_err enum for detailed error. +' +' NOTE: in the case of CS_OPT_MEM, handle's value can be anything, +' so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called +' even before cs_open() +'*/ +'CAPSTONE_EXPORT +'cs_err cs_option(csh handle, cs_opt_type type, size_t value); +Public Declare Function cs_option Lib "vbCapstone.dll" Alias "bs_option" (ByVal hEngine As Long, ByVal typ As cs_opt_type, ByVal size As Long) As cs_err + + + +'/* +' Report the last error number when some API function fail. +' Like glibc's errno, cs_errno might not retain its old value once accessed. +' +' @handle: handle returned by cs_open() +' +' @return: error code of cs_err enum type (CS_ERR_*, see above) +'*/ +'CAPSTONE_EXPORT +'cs_err cs_errno(csh handle); +Public Declare Function cs_errno Lib "vbCapstone.dll" Alias "bs_errno" (ByVal hEngine As Long) As cs_err + +' +'/* +' Return a string describing given error code. +' +' @code: error code (see CS_ERR_* above) +' +' @return: returns a pointer to a string that describes the error code +' passed in the argument @code +'*/ +'CAPSTONE_EXPORT +'const char *cs_strerror(cs_err code); +Public Declare Function cs_strerror Lib "vbCapstone.dll" Alias "bs_strerror" (ByVal errCode As cs_err) As Long + + +'/* +' Disassemble binary code, given the code buffer, size, address and number +' of instructions to be decoded. +' This API dynamically allocate memory to contain disassembled instruction. +' Resulting instructions will be put into @*insn +' +' NOTE 1: this API will automatically determine memory needed to contain +' output disassembled instructions in @insn. +' +' NOTE 2: caller must free the allocated memory itself to avoid memory leaking. +' +' NOTE 3: for system with scarce memory to be dynamically allocated such as +' OS kernel or firmware, the API cs_disasm_iter() might be a better choice than +' cs_disasm(). The reason is that with cs_disasm(), based on limited available +' memory, we have to calculate in advance how many instructions to be disassembled, +' which complicates things. This is especially troublesome for the case @count=0, +' when cs_disasm() runs uncontrollably (until either end of input buffer, or +' when it encounters an invalid instruction). +' +' @handle: handle returned by cs_open() +' @code: buffer containing raw binary code to be disassembled. +' @code_size: size of the above code buffer. +' @address: address of the first instruction in given raw code buffer. +' @insn: array of instructions filled in by this API. +' NOTE: @insn will be allocated by this function, and should be freed +' with cs_free() API. +' @count: number of instructions to be disassembled, or 0 to get all of them +' +' @return: the number of successfully disassembled instructions, +' or 0 if this function failed to disassemble the given code +' +' On failure, call cs_errno() for error code. +'*/ +'CAPSTONE_EXPORT +'size_t cs_disasm( +' csh handle, +' const uint8_t *code, +' size_t code_size, +' uint64_t address, +' size_t count, +' cs_insn **insn +'); +Public Declare Function cs_disasm Lib "vbCapstone.dll" Alias "bs_disasm" ( _ + ByVal hEngine As Long, _ + ByRef code As Byte, _ + ByVal size As Long, _ + ByVal address As Currency, _ + ByVal count As Long, _ + ByRef instAryPtr As Long _ +) As Long + +'this proto also lets use byte() to get a dump easily.. +Public Declare Sub getInstruction Lib "vbCapstone.dll" (ByVal hInstrAry As Long, ByVal index As Long, ByVal insPtr As Long, ByVal size As Long) + + +'/* +' Deprecated function - to be retired in the next version! +' Use cs_disasm() instead of cs_disasm_ex() +'*/ +'CAPSTONE_EXPORT +'CAPSTONE_DEPRECATED +'size_t cs_disasm_ex(csh handle, +' const uint8_t *code, size_t code_size, +' uint64_t address, +' size_t count, +' cs_insn **insn); + + + +'/* +' Free memory allocated by cs_malloc() or cs_disasm() (argument @insn) +' +' @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc() +' @count: number of cs_insn structures returned by cs_disasm(), or 1 +' to free memory allocated by cs_malloc(). +'*/ +'CAPSTONE_EXPORT +'void cs_free(cs_insn *insn, size_t count); +Public Declare Sub cs_free Lib "vbCapstone.dll" Alias "bs_free" (ByVal instr As Long, ByVal count As Long) + + +' +'/* +' Allocate memory for 1 instruction to be used by cs_disasm_iter(). +' +' @handle: handle returned by cs_open() +' +' NOTE: when no longer in use, you can reclaim the memory allocated for +' this instruction with cs_free(insn, 1) +'*/ +'CAPSTONE_EXPORT +'cs_insn *cs_malloc(csh handle); +Public Declare Function cs_malloc Lib "vbCapstone.dll" Alias "bs_malloc" (ByVal handle As Long) As Long + + + +'/* +' Fast API to disassemble binary code, given the code buffer, size, address +' and number of instructions to be decoded. +' This API puts the resulting instruction into a given cache in @insn. +' See tests/test_iter.c for sample code demonstrating this API. +' +' NOTE 1: this API will update @code, @size & @address to point to the next +' instruction in the input buffer. Therefore, it is convenient to use +' cs_disasm_iter() inside a loop to quickly iterate all the instructions. +' While decoding one instruction at a time can also be achieved with +' cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30% +' faster on random input. +' +' NOTE 2: the cache in @insn can be created with cs_malloc() API. +' +' NOTE 3: for system with scarce memory to be dynamically allocated such as +' OS kernel or firmware, this API is recommended over cs_disasm(), which +' allocates memory based on the number of instructions to be disassembled. +' The reason is that with cs_disasm(), based on limited available memory, +' we have to calculate in advance how many instructions to be disassembled, +' which complicates things. This is especially troublesome for the case +' @count=0, when cs_disasm() runs uncontrollably (until either end of input +' buffer, or when it encounters an invalid instruction). +' +' @handle: handle returned by cs_open() +' @code: buffer containing raw binary code to be disassembled +' @code_size: size of above code +' @address: address of the first insn in given raw code buffer +' @insn: pointer to instruction to be filled in by this API. +' +' @return: true if this API successfully decode 1 instruction, +' or false otherwise. +' +' On failure, call cs_errno() for error code. +'*/ +'CAPSTONE_EXPORT +'bool cs_disasm_iter(csh handle, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn); + + + +'/* +' Return friendly name of register in a string. +' Find the instruction id from header file of corresponding architecture (arm.h for ARM, +' x86.h for X86, ...) +' +' WARN: when in 'diet' mode, this API is irrelevant because engine does not +' store register name. +' +' @handle: handle returned by cs_open() +' @reg_id: register id +' +' @return: string name of the register, or NULL if @reg_id is invalid. +'*/ +'CAPSTONE_EXPORT +'const char *cs_reg_name(csh handle, unsigned int reg_id); +Public Declare Function cs_reg_name Lib "vbCapstone.dll" Alias "bs_reg_name" (ByVal handle As Long, ByVal regID As Long) As Long + + + + +'/* +' Return friendly name of an instruction in a string. +' Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' +' WARN: when in 'diet' mode, this API is irrelevant because the engine does not +' store instruction name. +' +' @handle: handle returned by cs_open() +' @insn_id: instruction id +' +' @return: string name of the instruction, or NULL if @insn_id is invalid. +'*/ +'CAPSTONE_EXPORT +'const char *cs_insn_name(csh handle, unsigned int insn_id); +Public Declare Function cs_insn_name Lib "vbCapstone.dll" Alias "bs_insn_name" (ByVal handle As Long, ByVal insn_id As Long) As Long + + + + +'/* +' Return friendly name of a group id (that an instruction can belong to) +' Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' +' WARN: when in 'diet' mode, this API is irrelevant because the engine does not +' store group name. +' +' @handle: handle returned by cs_open() +' @group_id: group id +' +' @return: string name of the group, or NULL if @group_id is invalid. +'*/ +'CAPSTONE_EXPORT +'const char *cs_group_name(csh handle, unsigned int group_id); +Public Declare Function cs_group_name Lib "vbCapstone.dll" Alias "bs_group_name" (ByVal handle As Long, ByVal group_id As Long) As Long + + + +'/* +' Check if a disassembled instruction belong to a particular group. +' Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' Internally, this simply verifies if @group_id matches any member of insn->groups array. +' +' NOTE: this API is only valid when detail option is ON (which is OFF by default). +' +' WARN: when in 'diet' mode, this API is irrelevant because the engine does not +' update @groups array. +' +' @handle: handle returned by cs_open() +' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() +' @group_id: group that you want to check if this instruction belong to. +' +' @return: true if this instruction indeed belongs to the given group, or false otherwise. +'*/ +'CAPSTONE_EXPORT +'bool cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id); +Public Declare Function cs_insn_group Lib "vbCapstone.dll" Alias "bs_insn_group" (ByVal handle As Long, ByVal instruction As Long, ByVal group_id As Long) As Long + + + +'/* +' Check if a disassembled instruction IMPLICITLY used a particular register. +' Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' Internally, this simply verifies if @reg_id matches any member of insn->regs_read array. +' +' NOTE: this API is only valid when detail option is ON (which is OFF by default) +' +' WARN: when in 'diet' mode, this API is irrelevant because the engine does not +' update @regs_read array. +' +' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() +' @reg_id: register that you want to check if this instruction used it. +' +' @return: true if this instruction indeed implicitly used the given register, or false otherwise. +'*/ +'CAPSTONE_EXPORT +'bool cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id); +Public Declare Function cs_reg_read Lib "vbCapstone.dll" Alias "bs_reg_read" (ByVal handle As Long, ByVal instruction As Long, ByVal reg_id As Long) As Long + + + +'/* +' Check if a disassembled instruction IMPLICITLY modified a particular register. +' Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' Internally, this simply verifies if @reg_id matches any member of insn->regs_write array. +' +' NOTE: this API is only valid when detail option is ON (which is OFF by default) +' +' WARN: when in 'diet' mode, this API is irrelevant because the engine does not +' update @regs_write array. +' +' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() +' @reg_id: register that you want to check if this instruction modified it. +' +' @return: true if this instruction indeed implicitly modified the given register, or false otherwise. +'*/ +'CAPSTONE_EXPORT +'bool cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id); +Public Declare Function cs_reg_write Lib "vbCapstone.dll" Alias "bs_reg_write" (ByVal handle As Long, ByVal instruction As Long, ByVal reg_id As Long) As Long + + + +'/* +' Count the number of operands of a given type. +' Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' +' NOTE: this API is only valid when detail option is ON (which is OFF by default) +' +' @handle: handle returned by cs_open() +' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() +' @op_type: Operand type to be found. +' +' @return: number of operands of given type @op_type in instruction @insn, +' or -1 on failure. +'*/ +'CAPSTONE_EXPORT +'int cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type); +Public Declare Function cs_op_count Lib "vbCapstone.dll" Alias "bs_op_count" (ByVal handle As Long, ByVal instruction As Long, ByVal op_type As Long) As Long + + + +'/* +' Retrieve the position of operand of given type in .operands[] array. +' Later, the operand can be accessed using the returned position. +' Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) +' +' NOTE: this API is only valid when detail option is ON (which is OFF by default) +' +' @handle: handle returned by cs_open() +' @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() +' @op_type: Operand type to be found. +' @position: position of the operand to be found. This must be in the range +' [1, cs_op_count(handle, insn, op_type)] +' +' @return: index of operand of given type @op_type in .operands[] array +' in instruction @insn, or -1 on failure. +'*/ +'CAPSTONE_EXPORT +'int cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, unsigned int position); +Public Declare Function cs_op_index Lib "vbCapstone.dll" Alias "bs_op_index" (ByVal handle As Long, ByVal instruction As Long, ByVal op_type As Long, ByVal position As Long) As Long + + + +Private Declare Function lstrcpy Lib "kernel32" Alias "lstrcpyA" (ByVal lpString1 As String, ByVal lpString2 As String) As Long +Private Declare Function lstrlen Lib "kernel32" Alias "lstrlenA" (ByVal lpString As Long) As Long + +Function cstr2vb(lpStr As Long) As String + + Dim length As Long + Dim buf() As Byte + + If lpStr = 0 Then Exit Function + + length = lstrlen(lpStr) + If length < 1 Then Exit Function + + ReDim buf(1 To length) + CopyMemory buf(1), ByVal lpStr, length + + cstr2vb = StrConv(buf, vbUnicode, &H409) + +End Function + +Function err2str(e As cs_err) As String + Dim lpStr As Long + lpStr = cs_strerror(e) + err2str = cstr2vb(lpStr) +End Function + +Function regName(hEngine As Long, regID As Long) As String + Dim lpStr As Long + lpStr = cs_reg_name(hEngine, regID) + regName = cstr2vb(lpStr) + If Len(regName) = 0 Or DEBUG_DUMP Then regName = regName & " (" & Hex(regID) & ")" +End Function + +Function insnName(hEngine As Long, insnID As Long) As String + Dim lpStr As Long + lpStr = cs_insn_name(hEngine, insnID) + insnName = cstr2vb(lpStr) + If Len(insnName) = 0 Or DEBUG_DUMP Then insnName = insnName & " (" & Hex(insnID) & ")" +End Function + +Function groupName(hEngine As Long, groupID As Long) As String + Dim lpStr As Long + lpStr = cs_group_name(hEngine, groupID) + groupName = cstr2vb(lpStr) + If Len(groupName) = 0 Or DEBUG_DUMP Then groupName = groupName & " (" & Hex(groupID) & ")" +End Function diff --git a/white_patch_detect/capstone-master/bindings/vb6/Project1.vbp b/white_patch_detect/capstone-master/bindings/vb6/Project1.vbp new file mode 100644 index 0000000..5ec6b1b --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/Project1.vbp @@ -0,0 +1,46 @@ +Type=Exe +Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\WINDOWS\system32\stdole2.tlb#OLE Automation +Form=Form1.frm +Module=mCapStone; Module1.bas +Module=mx86; mx86.bas +Module=mMisc; mMisc.bas +Class=CInstruction; CInstruction.cls +Class=CInstDetails; CInstDetails.cls +Class=CDisassembler; CDisassembler.cls +Object={831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0; mscomctl.ocx +Class=CX86Inst; CX86Inst.cls +Class=CX86Operand; CX86Operand.cls +Class=CX86OpMem; CX86OpMem.cls +Startup="Form1" +ExeName32="Project1.exe" +Command32="" +Name="Project1" +HelpContextID="0" +CompatibleMode="0" +MajorVer=1 +MinorVer=0 +RevisionVer=0 +AutoIncrementVer=0 +ServerSupportFiles=0 +VersionCompanyName="sandsprite" +CompilationType=0 +OptimizationType=0 +FavorPentiumPro(tm)=0 +CodeViewDebugInfo=0 +NoAliasing=0 +BoundsCheck=0 +OverflowCheck=0 +FlPointCheck=0 +FDIVCheck=0 +UnroundedFP=0 +StartMode=0 +Unattended=0 +Retained=0 +ThreadPerObject=0 +MaxNumberOfThreads=1 + +[MS Transaction Server] +AutoRefresh=1 + +[fastBuild] +fullPath=%ap%\bin\demo.exe diff --git a/white_patch_detect/capstone-master/bindings/vb6/README.txt b/white_patch_detect/capstone-master/bindings/vb6/README.txt new file mode 100644 index 0000000..515432e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/README.txt @@ -0,0 +1,30 @@ + +Capstone Disassembly Engine bindings for VB6 +Contributed by FireEye FLARE Team +Author: David Zimmer , +License: Apache +Copyright: FireEye 2017 + +This is a sample for using the capstone disassembly engine with VB6. + +All of the capstone API are implemented, so this lib supports basic +disassembly of all of the processor architectures that capstone implements. + +In the vb code, full instruction details are currently only supported for +the x86 processor family. + +This sample was built against Capstone 3.0 rc4. Note that if the capstone +structures change in the future this code will have to be adjusted to match. + +The vbCapstone.dll is written in C. Project files are provided for VS2008. +It is a small shim to give VB6 access to a stdcall API to access capstone. +You could also modify capstone itself so its exports were stdcall. + +The C project has an additional include directory set to ./../../include/ +for . This is for the /capstone/bindings/vb6/ directory structure + + + + + + diff --git a/white_patch_detect/capstone-master/bindings/vb6/mMisc.bas b/white_patch_detect/capstone-master/bindings/vb6/mMisc.bas new file mode 100644 index 0000000..113e007 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/mMisc.bas @@ -0,0 +1,385 @@ +Attribute VB_Name = "mMisc" +Option Explicit + +'These are old library functions + +Private Type Bit64Currency + value As Currency +End Type + +Private Type Bit64Integer + LowValue As Long + HighValue As Long +End Type + +Global Const LANG_US = &H409 + +Public Declare Function LoadLibrary Lib "kernel32" Alias "LoadLibraryA" (ByVal lpLibFileName As String) As Long +Public Declare Function FreeLibrary Lib "kernel32" (ByVal hLibModule As Long) As Long +Public Declare Sub CopyMemory Lib "kernel32" Alias "RtlMoveMemory" (Destination As Any, Source As Any, ByVal length As Long) +Public Declare Function GetProcAddress Lib "kernel32" (ByVal hModule As Long, ByVal lpProcName As String) As Long +Public Declare Function GetModuleHandle Lib "kernel32" Alias "GetModuleHandleA" (ByVal lpModuleName As String) As Long +Public Declare Function SetDllDirectory Lib "kernel32" Alias "SetDllDirectoryA" (ByVal lpPathName As String) As Long + +Function makeCur(high As Long, low As Long) As Currency + Dim c As Bit64Currency + Dim dl As Bit64Integer + dl.LowValue = low + dl.HighValue = high + LSet c = dl + makeCur = c.value +End Function + +Function lng2Cur(v As Long) As Currency + Dim c As Bit64Currency + Dim dl As Bit64Integer + dl.LowValue = v + dl.HighValue = 0 + LSet c = dl + lng2Cur = c.value +End Function + +Function cur2str(v As Currency) As String + Dim c As Bit64Currency + Dim dl As Bit64Integer + c.value = v + LSet dl = c + If dl.HighValue = 0 Then + cur2str = Right("00000000" & Hex(dl.LowValue), 8) + Else + cur2str = Right("00000000" & Hex(dl.HighValue), 8) & "`" & Right("00000000" & Hex(dl.LowValue), 8) + End If +End Function + +Function x64StrToCur(ByVal str As String) As Currency + + str = Replace(Trim(str), "0x", "") + str = Replace(str, " ", "") + str = Replace(str, "`", "") + + Dim low As String, high As String + Dim c As Bit64Currency + Dim dl As Bit64Integer + + low = VBA.Right(str, 8) + dl.LowValue = CLng("&h" & low) + + If Len(str) > 8 Then + high = Mid(str, 1, Len(str) - 8) + dl.HighValue = CLng("&h" & high) + End If + + LSet c = dl + x64StrToCur = c.value + +End Function + +Function cur2lng(v As Currency) As Long + Dim c As Bit64Currency + Dim dl As Bit64Integer + c.value = v + LSet dl = c + cur2lng = dl.LowValue +End Function + +Function readLng(offset As Long) As Long + Dim tmp As Long + CopyMemory ByVal VarPtr(tmp), ByVal offset, 4 + readLng = tmp +End Function + +Function readByte(offset As Long) As Byte + Dim tmp As Byte + CopyMemory ByVal VarPtr(tmp), ByVal offset, 1 + readByte = tmp +End Function + +Function readCur(offset As Long) As Currency + Dim tmp As Currency + CopyMemory ByVal VarPtr(tmp), ByVal offset, 8 + readCur = tmp +End Function + +Function col2Str(c As Collection, Optional emptyVal = "") As String + Dim v, tmp As String + + If c.count = 0 Then + col2Str = emptyVal + Else + For Each v In c + col2Str = col2Str & hhex(v) & ", " + Next + col2Str = Mid(col2Str, 1, Len(col2Str) - 2) + End If + +End Function + +Function regCol2Str(hEngine As Long, c As Collection) As String + Dim v, tmp As String + + If c.count = 0 Then Exit Function + + For Each v In c + regCol2Str = regCol2Str & regName(hEngine, CLng(v)) & ", " + Next + regCol2Str = Mid(regCol2Str, 1, Len(regCol2Str) - 2) + +End Function + + + +Function b2Str(b() As Byte) As String + Dim i As Long + + If AryIsEmpty(b) Then + b2Str = "Empty" + Else + For i = 0 To UBound(b) + b2Str = b2Str & hhex(b(i)) & " " + Next + b2Str = Trim(b2Str) + End If + +End Function + + + +Function AryIsEmpty(ary) As Boolean + Dim i As Long + + On Error GoTo oops + i = UBound(ary) '<- throws error if not initalized + AryIsEmpty = False + Exit Function +oops: AryIsEmpty = True +End Function + +Public Function toBytes(ByVal hexstr, Optional strRet As Boolean = False) + +'supports: +'11 22 33 44 spaced hex chars +'11223344 run together hex strings +'11,22,33,44 csv hex +'\x11,0x22 misc C source rips +' +'ignores common C source prefixes, operators, delimiters, and whitespace +' +'not supported +'1,2,3,4 all hex chars are must have two chars even if delimited +' +'a version which supports more formats is here: +' https://github.com/dzzie/libs/blob/master/dzrt/globals.cls + + Dim ret As String, x As String, str As String + Dim r() As Byte, b As Byte, b1 As Byte + Dim foundDecimal As Boolean, tmp, i, a, a2 + Dim pos As Long, marker As String + + On Error GoTo nope + + str = Replace(hexstr, vbCr, Empty) + str = Replace(str, vbLf, Empty) + str = Replace(str, vbTab, Empty) + str = Replace(str, Chr(0), Empty) + str = Replace(str, "{", Empty) + str = Replace(str, "}", Empty) + str = Replace(str, ";", Empty) + str = Replace(str, "+", Empty) + str = Replace(str, """""", Empty) + str = Replace(str, "'", Empty) + str = Replace(str, " ", Empty) + str = Replace(str, "0x", Empty) + str = Replace(str, "\x", Empty) + str = Replace(str, ",", Empty) + + For i = 1 To Len(str) Step 2 + x = Mid(str, i, 2) + If Not isHexChar(x, b) Then Exit Function + bpush r(), b + Next + + If strRet Then + toBytes = StrConv(r, vbUnicode, LANG_US) + Else + toBytes = r + End If + +nope: +End Function + +Private Sub bpush(bAry() As Byte, b As Byte) 'this modifies parent ary object + On Error GoTo init + Dim x As Long + + x = UBound(bAry) '<-throws Error If Not initalized + ReDim Preserve bAry(UBound(bAry) + 1) + bAry(UBound(bAry)) = b + + Exit Sub + +init: + ReDim bAry(0) + bAry(0) = b + +End Sub + +Sub push(ary, value) 'this modifies parent ary object + On Error GoTo init + Dim x + + x = UBound(ary) + ReDim Preserve ary(x + 1) + + If IsObject(value) Then + Set ary(x + 1) = value + Else + ary(x + 1) = value + End If + + Exit Sub +init: + ReDim ary(0) + If IsObject(value) Then + Set ary(0) = value + Else + ary(0) = value + End If +End Sub + + +Public Function isHexChar(hexValue As String, Optional b As Byte) As Boolean + On Error Resume Next + Dim v As Long + + If Len(hexValue) = 0 Then GoTo nope + If Len(hexValue) > 2 Then GoTo nope 'expecting hex char code like FF or 90 + + v = CLng("&h" & hexValue) + If Err.Number <> 0 Then GoTo nope 'invalid hex code + + b = CByte(v) + If Err.Number <> 0 Then GoTo nope 'shouldnt happen.. > 255 cant be with len() <=2 ? + + isHexChar = True + + Exit Function +nope: + Err.Clear + isHexChar = False +End Function + +Function hhex(b) As String + hhex = Right("00" & Hex(b), 2) +End Function + +Function rpad(x, i, Optional c = " ") + rpad = Left(x & String(i, c), i) +End Function + +Function HexDump(bAryOrStrData, Optional hexOnly = 0, Optional ByVal startAt As Long = 1, Optional ByVal length As Long = -1) As String + Dim s() As String, chars As String, tmp As String + On Error Resume Next + Dim ary() As Byte + Dim offset As Long + Const LANG_US = &H409 + Dim i As Long, tt, h, x + + offset = 0 + + If TypeName(bAryOrStrData) = "Byte()" Then + ary() = bAryOrStrData + Else + ary = StrConv(CStr(bAryOrStrData), vbFromUnicode, LANG_US) + End If + + If startAt < 1 Then startAt = 1 + If length < 1 Then length = -1 + + While startAt Mod 16 <> 0 + startAt = startAt - 1 + Wend + + startAt = startAt + 1 + + chars = " " + For i = startAt To UBound(ary) + 1 + tt = Hex(ary(i - 1)) + If Len(tt) = 1 Then tt = "0" & tt + tmp = tmp & tt & " " + x = ary(i - 1) + 'chars = chars & IIf((x > 32 And x < 127) Or x > 191, Chr(x), ".") 'x > 191 causes \x0 problems on non us systems... asc(chr(x)) = 0 + chars = chars & IIf((x > 32 And x < 127), Chr(x), ".") + If i > 1 And i Mod 16 = 0 Then + h = Hex(offset) + While Len(h) < 6: h = "0" & h: Wend + If hexOnly = 0 Then + push s, h & " " & tmp & chars + Else + push s, tmp + End If + offset = offset + 16 + tmp = Empty + chars = " " + End If + If length <> -1 Then + length = length - 1 + If length = 0 Then Exit For + End If + Next + + 'if read length was not mod 16=0 then + 'we have part of line to account for + If tmp <> Empty Then + If hexOnly = 0 Then + h = Hex(offset) + While Len(h) < 6: h = "0" & h: Wend + h = h & " " & tmp + While Len(h) <= 56: h = h & " ": Wend + push s, h & chars + Else + push s, tmp + End If + End If + + HexDump = Join(s, vbCrLf) + + If hexOnly <> 0 Then + HexDump = Replace(HexDump, " ", "") + HexDump = Replace(HexDump, vbCrLf, "") + End If + +End Function + + + +Function FileExists(path As String) As Boolean + On Error GoTo hell + + If Len(path) = 0 Then Exit Function + If Right(path, 1) = "\" Then Exit Function + If Dir(path, vbHidden Or vbNormal Or vbReadOnly Or vbSystem) <> "" Then FileExists = True + + Exit Function +hell: FileExists = False +End Function + +Sub WriteFile(path, it) + Dim f + f = FreeFile + Open path For Output As #f + Print #f, it + Close f +End Sub + +Function GetParentFolder(path) As String + Dim tmp() As String, ub As Long + On Error Resume Next + tmp = Split(path, "\") + ub = tmp(UBound(tmp)) + If Err.Number = 0 Then + GetParentFolder = Replace(Join(tmp, "\"), "\" & ub, "") + Else + GetParentFolder = path + End If +End Function + diff --git a/white_patch_detect/capstone-master/bindings/vb6/mx86.bas b/white_patch_detect/capstone-master/bindings/vb6/mx86.bas new file mode 100644 index 0000000..17a8b79 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/mx86.bas @@ -0,0 +1,1868 @@ +Attribute VB_Name = "mx86" +Option Explicit + +'Capstone Disassembly Engine bindings for VB6 +'Contributed by FireEye FLARE Team +'Author: David Zimmer , +'License: Apache +'Copyright: FireEye 2017 + + +Enum x86_reg + X86_REG_INVALID = 0 + X86_REG_AH + X86_REG_AL + X86_REG_AX + X86_REG_BH + X86_REG_BL + X86_REG_BP + X86_REG_BPL + X86_REG_BX + X86_REG_CH + X86_REG_CL + X86_REG_CS + X86_REG_CX + X86_REG_DH + X86_REG_DI + X86_REG_DIL + X86_REG_DL + X86_REG_DS + X86_REG_DX + X86_REG_EAX + X86_REG_EBP + X86_REG_EBX + X86_REG_ECX + X86_REG_EDI + X86_REG_EDX + X86_REG_EFLAGS + X86_REG_EIP + X86_REG_EIZ + X86_REG_ES + X86_REG_ESI + X86_REG_ESP + X86_REG_FPSW + X86_REG_FS + X86_REG_GS + X86_REG_IP + X86_REG_RAX + X86_REG_RBP + X86_REG_RBX + X86_REG_RCX + X86_REG_RDI + X86_REG_RDX + X86_REG_RIP + X86_REG_RIZ + X86_REG_RSI + X86_REG_RSP + X86_REG_SI + X86_REG_SIL + X86_REG_SP + X86_REG_SPL + X86_REG_SS + X86_REG_CR0 + X86_REG_CR1 + X86_REG_CR2 + X86_REG_CR3 + X86_REG_CR4 + X86_REG_CR5 + X86_REG_CR6 + X86_REG_CR7 + X86_REG_CR8 + X86_REG_CR9 + X86_REG_CR10 + X86_REG_CR11 + X86_REG_CR12 + X86_REG_CR13 + X86_REG_CR14 + X86_REG_CR15 + X86_REG_DR0 + X86_REG_DR1 + X86_REG_DR2 + X86_REG_DR3 + X86_REG_DR4 + X86_REG_DR5 + X86_REG_DR6 + X86_REG_DR7 + X86_REG_FP0 + X86_REG_FP1 + X86_REG_FP2 + X86_REG_FP3 + X86_REG_FP4 + X86_REG_FP5 + X86_REG_FP6 + X86_REG_FP7 + X86_REG_K0 + X86_REG_K1 + X86_REG_K2 + X86_REG_K3 + X86_REG_K4 + X86_REG_K5 + X86_REG_K6 + X86_REG_K7 + X86_REG_MM0 + X86_REG_MM1 + X86_REG_MM2 + X86_REG_MM3 + X86_REG_MM4 + X86_REG_MM5 + X86_REG_MM6 + X86_REG_MM7 + X86_REG_R8 + X86_REG_R9 + X86_REG_R10 + X86_REG_R11 + X86_REG_R12 + X86_REG_R13 + X86_REG_R14 + X86_REG_R15 + X86_REG_ST0 + X86_REG_ST1 + X86_REG_ST2 + X86_REG_ST3 + X86_REG_ST4 + X86_REG_ST5 + X86_REG_ST6 + X86_REG_ST7 + X86_REG_XMM0 + X86_REG_XMM1 + X86_REG_XMM2 + X86_REG_XMM3 + X86_REG_XMM4 + X86_REG_XMM5 + X86_REG_XMM6 + X86_REG_XMM7 + X86_REG_XMM8 + X86_REG_XMM9 + X86_REG_XMM10 + X86_REG_XMM11 + X86_REG_XMM12 + X86_REG_XMM13 + X86_REG_XMM14 + X86_REG_XMM15 + X86_REG_XMM16 + X86_REG_XMM17 + X86_REG_XMM18 + X86_REG_XMM19 + X86_REG_XMM20 + X86_REG_XMM21 + X86_REG_XMM22 + X86_REG_XMM23 + X86_REG_XMM24 + X86_REG_XMM25 + X86_REG_XMM26 + X86_REG_XMM27 + X86_REG_XMM28 + X86_REG_XMM29 + X86_REG_XMM30 + X86_REG_XMM31 + X86_REG_YMM0 + X86_REG_YMM1 + X86_REG_YMM2 + X86_REG_YMM3 + X86_REG_YMM4 + X86_REG_YMM5 + X86_REG_YMM6 + X86_REG_YMM7 + X86_REG_YMM8 + X86_REG_YMM9 + X86_REG_YMM10 + X86_REG_YMM11 + X86_REG_YMM12 + X86_REG_YMM13 + X86_REG_YMM14 + X86_REG_YMM15 + X86_REG_YMM16 + X86_REG_YMM17 + X86_REG_YMM18 + X86_REG_YMM19 + X86_REG_YMM20 + X86_REG_YMM21 + X86_REG_YMM22 + X86_REG_YMM23 + X86_REG_YMM24 + X86_REG_YMM25 + X86_REG_YMM26 + X86_REG_YMM27 + X86_REG_YMM28 + X86_REG_YMM29 + X86_REG_YMM30 + X86_REG_YMM31 + X86_REG_ZMM0 + X86_REG_ZMM1 + X86_REG_ZMM2 + X86_REG_ZMM3 + X86_REG_ZMM4 + X86_REG_ZMM5 + X86_REG_ZMM6 + X86_REG_ZMM7 + X86_REG_ZMM8 + X86_REG_ZMM9 + X86_REG_ZMM10 + X86_REG_ZMM11 + X86_REG_ZMM12 + X86_REG_ZMM13 + X86_REG_ZMM14 + X86_REG_ZMM15 + X86_REG_ZMM16 + X86_REG_ZMM17 + X86_REG_ZMM18 + X86_REG_ZMM19 + X86_REG_ZMM20 + X86_REG_ZMM21 + X86_REG_ZMM22 + X86_REG_ZMM23 + X86_REG_ZMM24 + X86_REG_ZMM25 + X86_REG_ZMM26 + X86_REG_ZMM27 + X86_REG_ZMM28 + X86_REG_ZMM29 + X86_REG_ZMM30 + X86_REG_ZMM31 + X86_REG_R8B + X86_REG_R9B + X86_REG_R10B + X86_REG_R11B + X86_REG_R12B + X86_REG_R13B + X86_REG_R14B + X86_REG_R15B + X86_REG_R8D + X86_REG_R9D + X86_REG_R10D + X86_REG_R11D + X86_REG_R12D + X86_REG_R13D + X86_REG_R14D + X86_REG_R15D + X86_REG_R8W + X86_REG_R9W + X86_REG_R10W + X86_REG_R11W + X86_REG_R12W + X86_REG_R13W + X86_REG_R14W + X86_REG_R15W + X86_REG_ENDING ' <-- mark the end of the list of registers +End Enum + +'Operand type for instruction's operands +Enum x86_op_type + X86_OP_INVALID = 0 'CS_OP_INVALID (Uninitialized). + X86_OP_REG 'CS_OP_REG (Register operand). + X86_OP_IMM 'CS_OP_IMM (Immediate operand). + x86_op_mem 'CS_OP_MEM (Memory operand). + X86_OP_FP 'CS_OP_FP (Floating-Point operand). +End Enum + +'AVX broadcast type +Public Enum x86_avx_bcast + X86_AVX_BCAST_INVALID = 0 ' Uninitialized. + X86_AVX_BCAST_2 ' AVX512 broadcast type {1to2} + X86_AVX_BCAST_4 ' AVX512 broadcast type {1to4} + X86_AVX_BCAST_8 ' AVX512 broadcast type {1to8} + X86_AVX_BCAST_16 ' AVX512 broadcast type {1to16} +End Enum + + +'SSE Code Condition type +Public Enum x86_sse_cc + X86_SSE_CC_INVALID = 0 ' Uninitialized. + X86_SSE_CC_EQ + X86_SSE_CC_LT + X86_SSE_CC_LE + X86_SSE_CC_UNORD + X86_SSE_CC_NEQ + X86_SSE_CC_NLT + X86_SSE_CC_NLE + X86_SSE_CC_ORD + X86_SSE_CC_EQ_UQ + X86_SSE_CC_NGE + X86_SSE_CC_NGT + X86_SSE_CC_FALSE + X86_SSE_CC_NEQ_OQ + X86_SSE_CC_GE + X86_SSE_CC_GT + X86_SSE_CC_TRUE +End Enum + +'AVX Code Condition type +Public Enum x86_avx_cc + X86_AVX_CC_INVALID = 0 ' Uninitialized. + X86_AVX_CC_EQ + X86_AVX_CC_LT + X86_AVX_CC_LE + X86_AVX_CC_UNORD + X86_AVX_CC_NEQ + X86_AVX_CC_NLT + X86_AVX_CC_NLE + X86_AVX_CC_ORD + X86_AVX_CC_EQ_UQ + X86_AVX_CC_NGE + X86_AVX_CC_NGT + X86_AVX_CC_FALSE + X86_AVX_CC_NEQ_OQ + X86_AVX_CC_GE + X86_AVX_CC_GT + X86_AVX_CC_TRUE + X86_AVX_CC_EQ_OS + X86_AVX_CC_LT_OQ + X86_AVX_CC_LE_OQ + X86_AVX_CC_UNORD_S + X86_AVX_CC_NEQ_US + X86_AVX_CC_NLT_UQ + X86_AVX_CC_NLE_UQ + X86_AVX_CC_ORD_S + X86_AVX_CC_EQ_US + X86_AVX_CC_NGE_UQ + X86_AVX_CC_NGT_UQ + X86_AVX_CC_FALSE_OS + X86_AVX_CC_NEQ_OS + X86_AVX_CC_GE_OQ + X86_AVX_CC_GT_OQ + X86_AVX_CC_TRUE_US +End Enum + +'AVX static rounding mode type +Public Enum x86_avx_rm + X86_AVX_RM_INVALID = 0 ' Uninitialized. + X86_AVX_RM_RN ' Round to nearest + X86_AVX_RM_RD ' Round down + X86_AVX_RM_RU ' Round up + X86_AVX_RM_RZ ' Round toward zero +End Enum + +'Instruction prefixes - to be used in cs_x86.prefix[] +Public Enum x86_prefix + X86_PREFIX_LOCK = &HF0 ' lock (cs_x86.prefix[0] + X86_PREFIX_REP = &HF3 ' rep (cs_x86.prefix[0] + X86_PREFIX_REPNE = &HF2 ' repne (cs_x86.prefix[0] + X86_PREFIX_CS = &H2E ' segment override CS (cs_x86.prefix[1] + X86_PREFIX_SS = &H36 ' segment override SS (cs_x86.prefix[1] + X86_PREFIX_DS = &H3E ' segment override DS (cs_x86.prefix[1] + X86_PREFIX_ES = &H26 ' segment override ES (cs_x86.prefix[1] + X86_PREFIX_FS = &H64 ' segment override FS (cs_x86.prefix[1] + X86_PREFIX_GS = &H65 ' segment override GS (cs_x86.prefix[1] + X86_PREFIX_OPSIZE = &H66 ' operand-size override (cs_x86.prefix[2] + X86_PREFIX_ADDRSIZE = &H67 ' address-size override (cs_x86.prefix[3] +End Enum + +'Instruction's operand referring to memory +'This is associated with X86_OP_MEM operand type above +Public Type x86_op_mem + segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED + base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED + index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED + scale As Long ' scale for index register + disp As Currency ' displacement value +End Type + +'Instruction operand 48 bytes +'typedef struct cs_x86_op { +' x86_op_type type; // operand type +' union { +' x86_reg reg; // register value for REG operand +' int64_t imm; // immediate value for IMM operand +' double fp; // floating point value for FP operand +' x86_op_mem mem; // base/index/scale/disp value for MEM operand +' }; +' +' // size of this operand (in bytes). +' uint8_t size; +' +' // AVX broadcast type, or 0 if irrelevant +' x86_avx_bcast avx_bcast; +' +' // AVX zero opmask {z} +' bool avx_zero_opmask; +'} cs_x86_op; + +'Instruction structure +Public Type cs_x86 + ' Instruction prefix, which can be up to 4 bytes. + ' A prefix byte gets value 0 when irrelevant. + ' prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) + ' prefix[1] indicates segment override (irrelevant for x86_64): + ' See X86_PREFIX_CS/SS/DS/ES/FS/GS above. + ' prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) + ' prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) + prefix(0 To 3) As Byte ' UNSIGNED + + ' Instruction opcode, wich can be from 1 to 4 bytes in size. + ' This contains VEX opcode as well. + ' An trailing opcode byte gets value 0 when irrelevant. + opcode(0 To 3) As Byte ' UNSIGNED + + rex As Byte ' REX prefix: only a non-zero value is relavant for x86_64 UNSIGNED + addr_size As Byte ' Address size, which can be overrided with above prefix[5]. UNSIGNED + modrm As Byte ' ModR/M byte UNSIGNED + sib As Byte ' SIB value, or 0 when irrelevant. UNSIGNED + disp As Long ' Displacement value, or 0 when irrelevant. + sib_index As x86_reg ' SIB index register, or X86_REG_INVALID when irrelevant. + sib_scale As Byte ' SIB scale. only applicable if sib_index is relavant. + sib_base As x86_reg ' SIB base register, or X86_REG_INVALID when irrelevant. + sse_cc As x86_sse_cc ' SSE Code Condition + avx_cc As x86_avx_cc ' AVX Code Condition + avx_sae As Byte ' AVX Suppress all Exception + avx_rm As x86_avx_rm ' AVX static rounding mode + op_count As Byte ' Number of operands of this instruction, or 0 when instruction has no operand.UNSIGNED + + 'operands(0 To 7) As cs_x86_op ' operands for this instruction. + 'opBuf(0 To 383) As Byte + +End Type + +'X86 instructions +Public Enum x86_insn + X86_INS_INVALID = 0 + X86_INS_AAA + X86_INS_AAD + X86_INS_AAM + X86_INS_AAS + X86_INS_FABS + X86_INS_ADC + X86_INS_ADCX + X86_INS_ADD + X86_INS_ADDPD + X86_INS_ADDPS + X86_INS_ADDSD + X86_INS_ADDSS + X86_INS_ADDSUBPD + X86_INS_ADDSUBPS + X86_INS_FADD + X86_INS_FIADD + X86_INS_FADDP + X86_INS_ADOX + X86_INS_AESDECLAST + X86_INS_AESDEC + X86_INS_AESENCLAST + X86_INS_AESENC + X86_INS_AESIMC + X86_INS_AESKEYGENASSIST + X86_INS_AND + X86_INS_ANDN + X86_INS_ANDNPD + X86_INS_ANDNPS + X86_INS_ANDPD + X86_INS_ANDPS + X86_INS_ARPL + X86_INS_BEXTR + X86_INS_BLCFILL + X86_INS_BLCI + X86_INS_BLCIC + X86_INS_BLCMSK + X86_INS_BLCS + X86_INS_BLENDPD + X86_INS_BLENDPS + X86_INS_BLENDVPD + X86_INS_BLENDVPS + X86_INS_BLSFILL + X86_INS_BLSI + X86_INS_BLSIC + X86_INS_BLSMSK + X86_INS_BLSR + X86_INS_BOUND + X86_INS_BSF + X86_INS_BSR + X86_INS_BSWAP + X86_INS_BT + X86_INS_BTC + X86_INS_BTR + X86_INS_BTS + X86_INS_BZHI + X86_INS_CALL + X86_INS_CBW + X86_INS_CDQ + X86_INS_CDQE + X86_INS_FCHS + X86_INS_CLAC + X86_INS_CLC + X86_INS_CLD + X86_INS_CLFLUSH + X86_INS_CLGI + X86_INS_CLI + X86_INS_CLTS + X86_INS_CMC + X86_INS_CMOVA + X86_INS_CMOVAE + X86_INS_CMOVB + X86_INS_CMOVBE + X86_INS_FCMOVBE + X86_INS_FCMOVB + X86_INS_CMOVE + X86_INS_FCMOVE + X86_INS_CMOVG + X86_INS_CMOVGE + X86_INS_CMOVL + X86_INS_CMOVLE + X86_INS_FCMOVNBE + X86_INS_FCMOVNB + X86_INS_CMOVNE + X86_INS_FCMOVNE + X86_INS_CMOVNO + X86_INS_CMOVNP + X86_INS_FCMOVNU + X86_INS_CMOVNS + X86_INS_CMOVO + X86_INS_CMOVP + X86_INS_FCMOVU + X86_INS_CMOVS + X86_INS_CMP + X86_INS_CMPPD + X86_INS_CMPPS + X86_INS_CMPSB + X86_INS_CMPSD + X86_INS_CMPSQ + X86_INS_CMPSS + X86_INS_CMPSW + X86_INS_CMPXCHG16B + X86_INS_CMPXCHG + X86_INS_CMPXCHG8B + X86_INS_COMISD + X86_INS_COMISS + X86_INS_FCOMP + X86_INS_FCOMPI + X86_INS_FCOMI + X86_INS_FCOM + X86_INS_FCOS + X86_INS_CPUID + X86_INS_CQO + X86_INS_CRC32 + X86_INS_CVTDQ2PD + X86_INS_CVTDQ2PS + X86_INS_CVTPD2DQ + X86_INS_CVTPD2PS + X86_INS_CVTPS2DQ + X86_INS_CVTPS2PD + X86_INS_CVTSD2SI + X86_INS_CVTSD2SS + X86_INS_CVTSI2SD + X86_INS_CVTSI2SS + X86_INS_CVTSS2SD + X86_INS_CVTSS2SI + X86_INS_CVTTPD2DQ + X86_INS_CVTTPS2DQ + X86_INS_CVTTSD2SI + X86_INS_CVTTSS2SI + X86_INS_CWD + X86_INS_CWDE + X86_INS_DAA + X86_INS_DAS + X86_INS_DATA16 + X86_INS_DEC + X86_INS_DIV + X86_INS_DIVPD + X86_INS_DIVPS + X86_INS_FDIVR + X86_INS_FIDIVR + X86_INS_FDIVRP + X86_INS_DIVSD + X86_INS_DIVSS + X86_INS_FDIV + X86_INS_FIDIV + X86_INS_FDIVP + X86_INS_DPPD + X86_INS_DPPS + X86_INS_RET + X86_INS_ENCLS + X86_INS_ENCLU + X86_INS_ENTER + X86_INS_EXTRACTPS + X86_INS_EXTRQ + X86_INS_F2XM1 + X86_INS_LCALL + X86_INS_LJMP + X86_INS_FBLD + X86_INS_FBSTP + X86_INS_FCOMPP + X86_INS_FDECSTP + X86_INS_FEMMS + X86_INS_FFREE + X86_INS_FICOM + X86_INS_FICOMP + X86_INS_FINCSTP + X86_INS_FLDCW + X86_INS_FLDENV + X86_INS_FLDL2E + X86_INS_FLDL2T + X86_INS_FLDLG2 + X86_INS_FLDLN2 + X86_INS_FLDPI + X86_INS_FNCLEX + X86_INS_FNINIT + X86_INS_FNOP + X86_INS_FNSTCW + X86_INS_FNSTSW + X86_INS_FPATAN + X86_INS_FPREM + X86_INS_FPREM1 + X86_INS_FPTAN + X86_INS_FRNDINT + X86_INS_FRSTOR + X86_INS_FNSAVE + X86_INS_FSCALE + X86_INS_FSETPM + X86_INS_FSINCOS + X86_INS_FNSTENV + X86_INS_FXAM + X86_INS_FXRSTOR + X86_INS_FXRSTOR64 + X86_INS_FXSAVE + X86_INS_FXSAVE64 + X86_INS_FXTRACT + X86_INS_FYL2X + X86_INS_FYL2XP1 + X86_INS_MOVAPD + X86_INS_MOVAPS + X86_INS_ORPD + X86_INS_ORPS + X86_INS_VMOVAPD + X86_INS_VMOVAPS + X86_INS_XORPD + X86_INS_XORPS + X86_INS_GETSEC + X86_INS_HADDPD + X86_INS_HADDPS + X86_INS_HLT + X86_INS_HSUBPD + X86_INS_HSUBPS + X86_INS_IDIV + X86_INS_FILD + X86_INS_IMUL + X86_INS_IN + X86_INS_INC + X86_INS_INSB + X86_INS_INSERTPS + X86_INS_INSERTQ + X86_INS_INSD + X86_INS_INSW + X86_INS_INT + X86_INS_INT1 + X86_INS_INT3 + X86_INS_INTO + X86_INS_INVD + X86_INS_INVEPT + X86_INS_INVLPG + X86_INS_INVLPGA + X86_INS_INVPCID + X86_INS_INVVPID + X86_INS_IRET + X86_INS_IRETD + X86_INS_IRETQ + X86_INS_FISTTP + X86_INS_FIST + X86_INS_FISTP + X86_INS_UCOMISD + X86_INS_UCOMISS + X86_INS_VCMP + X86_INS_VCOMISD + X86_INS_VCOMISS + X86_INS_VCVTSD2SS + X86_INS_VCVTSI2SD + X86_INS_VCVTSI2SS + X86_INS_VCVTSS2SD + X86_INS_VCVTTSD2SI + X86_INS_VCVTTSD2USI + X86_INS_VCVTTSS2SI + X86_INS_VCVTTSS2USI + X86_INS_VCVTUSI2SD + X86_INS_VCVTUSI2SS + X86_INS_VUCOMISD + X86_INS_VUCOMISS + X86_INS_JAE + X86_INS_JA + X86_INS_JBE + X86_INS_JB + X86_INS_JCXZ + X86_INS_JECXZ + X86_INS_JE + X86_INS_JGE + X86_INS_JG + X86_INS_JLE + X86_INS_JL + X86_INS_JMP + X86_INS_JNE + X86_INS_JNO + X86_INS_JNP + X86_INS_JNS + X86_INS_JO + X86_INS_JP + X86_INS_JRCXZ + X86_INS_JS + X86_INS_KANDB + X86_INS_KANDD + X86_INS_KANDNB + X86_INS_KANDND + X86_INS_KANDNQ + X86_INS_KANDNW + X86_INS_KANDQ + X86_INS_KANDW + X86_INS_KMOVB + X86_INS_KMOVD + X86_INS_KMOVQ + X86_INS_KMOVW + X86_INS_KNOTB + X86_INS_KNOTD + X86_INS_KNOTQ + X86_INS_KNOTW + X86_INS_KORB + X86_INS_KORD + X86_INS_KORQ + X86_INS_KORTESTW + X86_INS_KORW + X86_INS_KSHIFTLW + X86_INS_KSHIFTRW + X86_INS_KUNPCKBW + X86_INS_KXNORB + X86_INS_KXNORD + X86_INS_KXNORQ + X86_INS_KXNORW + X86_INS_KXORB + X86_INS_KXORD + X86_INS_KXORQ + X86_INS_KXORW + X86_INS_LAHF + X86_INS_LAR + X86_INS_LDDQU + X86_INS_LDMXCSR + X86_INS_LDS + X86_INS_FLDZ + X86_INS_FLD1 + X86_INS_FLD + X86_INS_LEA + X86_INS_LEAVE + X86_INS_LES + X86_INS_LFENCE + X86_INS_LFS + X86_INS_LGDT + X86_INS_LGS + X86_INS_LIDT + X86_INS_LLDT + X86_INS_LMSW + X86_INS_OR + X86_INS_SUB + X86_INS_XOR + X86_INS_LODSB + X86_INS_LODSD + X86_INS_LODSQ + X86_INS_LODSW + X86_INS_LOOP + X86_INS_LOOPE + X86_INS_LOOPNE + X86_INS_RETF + X86_INS_RETFQ + X86_INS_LSL + X86_INS_LSS + X86_INS_LTR + X86_INS_XADD + X86_INS_LZCNT + X86_INS_MASKMOVDQU + X86_INS_MAXPD + X86_INS_MAXPS + X86_INS_MAXSD + X86_INS_MAXSS + X86_INS_MFENCE + X86_INS_MINPD + X86_INS_MINPS + X86_INS_MINSD + X86_INS_MINSS + X86_INS_CVTPD2PI + X86_INS_CVTPI2PD + X86_INS_CVTPI2PS + X86_INS_CVTPS2PI + X86_INS_CVTTPD2PI + X86_INS_CVTTPS2PI + X86_INS_EMMS + X86_INS_MASKMOVQ + X86_INS_MOVD + X86_INS_MOVDQ2Q + X86_INS_MOVNTQ + X86_INS_MOVQ2DQ + X86_INS_MOVQ + X86_INS_PABSB + X86_INS_PABSD + X86_INS_PABSW + X86_INS_PACKSSDW + X86_INS_PACKSSWB + X86_INS_PACKUSWB + X86_INS_PADDB + X86_INS_PADDD + X86_INS_PADDQ + X86_INS_PADDSB + X86_INS_PADDSW + X86_INS_PADDUSB + X86_INS_PADDUSW + X86_INS_PADDW + X86_INS_PALIGNR + X86_INS_PANDN + X86_INS_PAND + X86_INS_PAVGB + X86_INS_PAVGW + X86_INS_PCMPEQB + X86_INS_PCMPEQD + X86_INS_PCMPEQW + X86_INS_PCMPGTB + X86_INS_PCMPGTD + X86_INS_PCMPGTW + X86_INS_PEXTRW + X86_INS_PHADDSW + X86_INS_PHADDW + X86_INS_PHADDD + X86_INS_PHSUBD + X86_INS_PHSUBSW + X86_INS_PHSUBW + X86_INS_PINSRW + X86_INS_PMADDUBSW + X86_INS_PMADDWD + X86_INS_PMAXSW + X86_INS_PMAXUB + X86_INS_PMINSW + X86_INS_PMINUB + X86_INS_PMOVMSKB + X86_INS_PMULHRSW + X86_INS_PMULHUW + X86_INS_PMULHW + X86_INS_PMULLW + X86_INS_PMULUDQ + X86_INS_POR + X86_INS_PSADBW + X86_INS_PSHUFB + X86_INS_PSHUFW + X86_INS_PSIGNB + X86_INS_PSIGND + X86_INS_PSIGNW + X86_INS_PSLLD + X86_INS_PSLLQ + X86_INS_PSLLW + X86_INS_PSRAD + X86_INS_PSRAW + X86_INS_PSRLD + X86_INS_PSRLQ + X86_INS_PSRLW + X86_INS_PSUBB + X86_INS_PSUBD + X86_INS_PSUBQ + X86_INS_PSUBSB + X86_INS_PSUBSW + X86_INS_PSUBUSB + X86_INS_PSUBUSW + X86_INS_PSUBW + X86_INS_PUNPCKHBW + X86_INS_PUNPCKHDQ + X86_INS_PUNPCKHWD + X86_INS_PUNPCKLBW + X86_INS_PUNPCKLDQ + X86_INS_PUNPCKLWD + X86_INS_PXOR + X86_INS_MONITOR + X86_INS_MONTMUL + X86_INS_MOV + X86_INS_MOVABS + X86_INS_MOVBE + X86_INS_MOVDDUP + X86_INS_MOVDQA + X86_INS_MOVDQU + X86_INS_MOVHLPS + X86_INS_MOVHPD + X86_INS_MOVHPS + X86_INS_MOVLHPS + X86_INS_MOVLPD + X86_INS_MOVLPS + X86_INS_MOVMSKPD + X86_INS_MOVMSKPS + X86_INS_MOVNTDQA + X86_INS_MOVNTDQ + X86_INS_MOVNTI + X86_INS_MOVNTPD + X86_INS_MOVNTPS + X86_INS_MOVNTSD + X86_INS_MOVNTSS + X86_INS_MOVSB + X86_INS_MOVSD + X86_INS_MOVSHDUP + X86_INS_MOVSLDUP + X86_INS_MOVSQ + X86_INS_MOVSS + X86_INS_MOVSW + X86_INS_MOVSX + X86_INS_MOVSXD + X86_INS_MOVUPD + X86_INS_MOVUPS + X86_INS_MOVZX + X86_INS_MPSADBW + X86_INS_MUL + X86_INS_MULPD + X86_INS_MULPS + X86_INS_MULSD + X86_INS_MULSS + X86_INS_MULX + X86_INS_FMUL + X86_INS_FIMUL + X86_INS_FMULP + X86_INS_MWAIT + X86_INS_NEG + X86_INS_NOP + X86_INS_NOT + X86_INS_OUT + X86_INS_OUTSB + X86_INS_OUTSD + X86_INS_OUTSW + X86_INS_PACKUSDW + X86_INS_PAUSE + X86_INS_PAVGUSB + X86_INS_PBLENDVB + X86_INS_PBLENDW + X86_INS_PCLMULQDQ + X86_INS_PCMPEQQ + X86_INS_PCMPESTRI + X86_INS_PCMPESTRM + X86_INS_PCMPGTQ + X86_INS_PCMPISTRI + X86_INS_PCMPISTRM + X86_INS_PDEP + X86_INS_PEXT + X86_INS_PEXTRB + X86_INS_PEXTRD + X86_INS_PEXTRQ + X86_INS_PF2ID + X86_INS_PF2IW + X86_INS_PFACC + X86_INS_PFADD + X86_INS_PFCMPEQ + X86_INS_PFCMPGE + X86_INS_PFCMPGT + X86_INS_PFMAX + X86_INS_PFMIN + X86_INS_PFMUL + X86_INS_PFNACC + X86_INS_PFPNACC + X86_INS_PFRCPIT1 + X86_INS_PFRCPIT2 + X86_INS_PFRCP + X86_INS_PFRSQIT1 + X86_INS_PFRSQRT + X86_INS_PFSUBR + X86_INS_PFSUB + X86_INS_PHMINPOSUW + X86_INS_PI2FD + X86_INS_PI2FW + X86_INS_PINSRB + X86_INS_PINSRD + X86_INS_PINSRQ + X86_INS_PMAXSB + X86_INS_PMAXSD + X86_INS_PMAXUD + X86_INS_PMAXUW + X86_INS_PMINSB + X86_INS_PMINSD + X86_INS_PMINUD + X86_INS_PMINUW + X86_INS_PMOVSXBD + X86_INS_PMOVSXBQ + X86_INS_PMOVSXBW + X86_INS_PMOVSXDQ + X86_INS_PMOVSXWD + X86_INS_PMOVSXWQ + X86_INS_PMOVZXBD + X86_INS_PMOVZXBQ + X86_INS_PMOVZXBW + X86_INS_PMOVZXDQ + X86_INS_PMOVZXWD + X86_INS_PMOVZXWQ + X86_INS_PMULDQ + X86_INS_PMULHRW + X86_INS_PMULLD + X86_INS_POP + X86_INS_POPAW + X86_INS_POPAL + X86_INS_POPCNT + X86_INS_POPF + X86_INS_POPFD + X86_INS_POPFQ + X86_INS_PREFETCH + X86_INS_PREFETCHNTA + X86_INS_PREFETCHT0 + X86_INS_PREFETCHT1 + X86_INS_PREFETCHT2 + X86_INS_PREFETCHW + X86_INS_PSHUFD + X86_INS_PSHUFHW + X86_INS_PSHUFLW + X86_INS_PSLLDQ + X86_INS_PSRLDQ + X86_INS_PSWAPD + X86_INS_PTEST + X86_INS_PUNPCKHQDQ + X86_INS_PUNPCKLQDQ + X86_INS_PUSH + X86_INS_PUSHAW + X86_INS_PUSHAL + X86_INS_PUSHF + X86_INS_PUSHFD + X86_INS_PUSHFQ + X86_INS_RCL + X86_INS_RCPPS + X86_INS_RCPSS + X86_INS_RCR + X86_INS_RDFSBASE + X86_INS_RDGSBASE + X86_INS_RDMSR + X86_INS_RDPMC + X86_INS_RDRAND + X86_INS_RDSEED + X86_INS_RDTSC + X86_INS_RDTSCP + X86_INS_ROL + X86_INS_ROR + X86_INS_RORX + X86_INS_ROUNDPD + X86_INS_ROUNDPS + X86_INS_ROUNDSD + X86_INS_ROUNDSS + X86_INS_RSM + X86_INS_RSQRTPS + X86_INS_RSQRTSS + X86_INS_SAHF + X86_INS_SAL + X86_INS_SALC + X86_INS_SAR + X86_INS_SARX + X86_INS_SBB + X86_INS_SCASB + X86_INS_SCASD + X86_INS_SCASQ + X86_INS_SCASW + X86_INS_SETAE + X86_INS_SETA + X86_INS_SETBE + X86_INS_SETB + X86_INS_SETE + X86_INS_SETGE + X86_INS_SETG + X86_INS_SETLE + X86_INS_SETL + X86_INS_SETNE + X86_INS_SETNO + X86_INS_SETNP + X86_INS_SETNS + X86_INS_SETO + X86_INS_SETP + X86_INS_SETS + X86_INS_SFENCE + X86_INS_SGDT + X86_INS_SHA1MSG1 + X86_INS_SHA1MSG2 + X86_INS_SHA1NEXTE + X86_INS_SHA1RNDS4 + X86_INS_SHA256MSG1 + X86_INS_SHA256MSG2 + X86_INS_SHA256RNDS2 + X86_INS_SHL + X86_INS_SHLD + X86_INS_SHLX + X86_INS_SHR + X86_INS_SHRD + X86_INS_SHRX + X86_INS_SHUFPD + X86_INS_SHUFPS + X86_INS_SIDT + X86_INS_FSIN + X86_INS_SKINIT + X86_INS_SLDT + X86_INS_SMSW + X86_INS_SQRTPD + X86_INS_SQRTPS + X86_INS_SQRTSD + X86_INS_SQRTSS + X86_INS_FSQRT + X86_INS_STAC + X86_INS_STC + X86_INS_STD + X86_INS_STGI + X86_INS_STI + X86_INS_STMXCSR + X86_INS_STOSB + X86_INS_STOSD + X86_INS_STOSQ + X86_INS_STOSW + X86_INS_STR + X86_INS_FST + X86_INS_FSTP + X86_INS_FSTPNCE + X86_INS_SUBPD + X86_INS_SUBPS + X86_INS_FSUBR + X86_INS_FISUBR + X86_INS_FSUBRP + X86_INS_SUBSD + X86_INS_SUBSS + X86_INS_FSUB + X86_INS_FISUB + X86_INS_FSUBP + X86_INS_SWAPGS + X86_INS_SYSCALL + X86_INS_SYSENTER + X86_INS_SYSEXIT + X86_INS_SYSRET + X86_INS_T1MSKC + X86_INS_TEST + X86_INS_UD2 + X86_INS_FTST + X86_INS_TZCNT + X86_INS_TZMSK + X86_INS_FUCOMPI + X86_INS_FUCOMI + X86_INS_FUCOMPP + X86_INS_FUCOMP + X86_INS_FUCOM + X86_INS_UD2B + X86_INS_UNPCKHPD + X86_INS_UNPCKHPS + X86_INS_UNPCKLPD + X86_INS_UNPCKLPS + X86_INS_VADDPD + X86_INS_VADDPS + X86_INS_VADDSD + X86_INS_VADDSS + X86_INS_VADDSUBPD + X86_INS_VADDSUBPS + X86_INS_VAESDECLAST + X86_INS_VAESDEC + X86_INS_VAESENCLAST + X86_INS_VAESENC + X86_INS_VAESIMC + X86_INS_VAESKEYGENASSIST + X86_INS_VALIGND + X86_INS_VALIGNQ + X86_INS_VANDNPD + X86_INS_VANDNPS + X86_INS_VANDPD + X86_INS_VANDPS + X86_INS_VBLENDMPD + X86_INS_VBLENDMPS + X86_INS_VBLENDPD + X86_INS_VBLENDPS + X86_INS_VBLENDVPD + X86_INS_VBLENDVPS + X86_INS_VBROADCASTF128 + X86_INS_VBROADCASTI128 + X86_INS_VBROADCASTI32X4 + X86_INS_VBROADCASTI64X4 + X86_INS_VBROADCASTSD + X86_INS_VBROADCASTSS + X86_INS_VCMPPD + X86_INS_VCMPPS + X86_INS_VCMPSD + X86_INS_VCMPSS + X86_INS_VCVTDQ2PD + X86_INS_VCVTDQ2PS + X86_INS_VCVTPD2DQX + X86_INS_VCVTPD2DQ + X86_INS_VCVTPD2PSX + X86_INS_VCVTPD2PS + X86_INS_VCVTPD2UDQ + X86_INS_VCVTPH2PS + X86_INS_VCVTPS2DQ + X86_INS_VCVTPS2PD + X86_INS_VCVTPS2PH + X86_INS_VCVTPS2UDQ + X86_INS_VCVTSD2SI + X86_INS_VCVTSD2USI + X86_INS_VCVTSS2SI + X86_INS_VCVTSS2USI + X86_INS_VCVTTPD2DQX + X86_INS_VCVTTPD2DQ + X86_INS_VCVTTPD2UDQ + X86_INS_VCVTTPS2DQ + X86_INS_VCVTTPS2UDQ + X86_INS_VCVTUDQ2PD + X86_INS_VCVTUDQ2PS + X86_INS_VDIVPD + X86_INS_VDIVPS + X86_INS_VDIVSD + X86_INS_VDIVSS + X86_INS_VDPPD + X86_INS_VDPPS + X86_INS_VERR + X86_INS_VERW + X86_INS_VEXTRACTF128 + X86_INS_VEXTRACTF32X4 + X86_INS_VEXTRACTF64X4 + X86_INS_VEXTRACTI128 + X86_INS_VEXTRACTI32X4 + X86_INS_VEXTRACTI64X4 + X86_INS_VEXTRACTPS + X86_INS_VFMADD132PD + X86_INS_VFMADD132PS + X86_INS_VFMADD213PD + X86_INS_VFMADD213PS + X86_INS_VFMADDPD + X86_INS_VFMADD231PD + X86_INS_VFMADDPS + X86_INS_VFMADD231PS + X86_INS_VFMADDSD + X86_INS_VFMADD213SD + X86_INS_VFMADD132SD + X86_INS_VFMADD231SD + X86_INS_VFMADDSS + X86_INS_VFMADD213SS + X86_INS_VFMADD132SS + X86_INS_VFMADD231SS + X86_INS_VFMADDSUB132PD + X86_INS_VFMADDSUB132PS + X86_INS_VFMADDSUB213PD + X86_INS_VFMADDSUB213PS + X86_INS_VFMADDSUBPD + X86_INS_VFMADDSUB231PD + X86_INS_VFMADDSUBPS + X86_INS_VFMADDSUB231PS + X86_INS_VFMSUB132PD + X86_INS_VFMSUB132PS + X86_INS_VFMSUB213PD + X86_INS_VFMSUB213PS + X86_INS_VFMSUBADD132PD + X86_INS_VFMSUBADD132PS + X86_INS_VFMSUBADD213PD + X86_INS_VFMSUBADD213PS + X86_INS_VFMSUBADDPD + X86_INS_VFMSUBADD231PD + X86_INS_VFMSUBADDPS + X86_INS_VFMSUBADD231PS + X86_INS_VFMSUBPD + X86_INS_VFMSUB231PD + X86_INS_VFMSUBPS + X86_INS_VFMSUB231PS + X86_INS_VFMSUBSD + X86_INS_VFMSUB213SD + X86_INS_VFMSUB132SD + X86_INS_VFMSUB231SD + X86_INS_VFMSUBSS + X86_INS_VFMSUB213SS + X86_INS_VFMSUB132SS + X86_INS_VFMSUB231SS + X86_INS_VFNMADD132PD + X86_INS_VFNMADD132PS + X86_INS_VFNMADD213PD + X86_INS_VFNMADD213PS + X86_INS_VFNMADDPD + X86_INS_VFNMADD231PD + X86_INS_VFNMADDPS + X86_INS_VFNMADD231PS + X86_INS_VFNMADDSD + X86_INS_VFNMADD213SD + X86_INS_VFNMADD132SD + X86_INS_VFNMADD231SD + X86_INS_VFNMADDSS + X86_INS_VFNMADD213SS + X86_INS_VFNMADD132SS + X86_INS_VFNMADD231SS + X86_INS_VFNMSUB132PD + X86_INS_VFNMSUB132PS + X86_INS_VFNMSUB213PD + X86_INS_VFNMSUB213PS + X86_INS_VFNMSUBPD + X86_INS_VFNMSUB231PD + X86_INS_VFNMSUBPS + X86_INS_VFNMSUB231PS + X86_INS_VFNMSUBSD + X86_INS_VFNMSUB213SD + X86_INS_VFNMSUB132SD + X86_INS_VFNMSUB231SD + X86_INS_VFNMSUBSS + X86_INS_VFNMSUB213SS + X86_INS_VFNMSUB132SS + X86_INS_VFNMSUB231SS + X86_INS_VFRCZPD + X86_INS_VFRCZPS + X86_INS_VFRCZSD + X86_INS_VFRCZSS + X86_INS_VORPD + X86_INS_VORPS + X86_INS_VXORPD + X86_INS_VXORPS + X86_INS_VGATHERDPD + X86_INS_VGATHERDPS + X86_INS_VGATHERPF0DPD + X86_INS_VGATHERPF0DPS + X86_INS_VGATHERPF0QPD + X86_INS_VGATHERPF0QPS + X86_INS_VGATHERPF1DPD + X86_INS_VGATHERPF1DPS + X86_INS_VGATHERPF1QPD + X86_INS_VGATHERPF1QPS + X86_INS_VGATHERQPD + X86_INS_VGATHERQPS + X86_INS_VHADDPD + X86_INS_VHADDPS + X86_INS_VHSUBPD + X86_INS_VHSUBPS + X86_INS_VINSERTF128 + X86_INS_VINSERTF32X4 + X86_INS_VINSERTF64X4 + X86_INS_VINSERTI128 + X86_INS_VINSERTI32X4 + X86_INS_VINSERTI64X4 + X86_INS_VINSERTPS + X86_INS_VLDDQU + X86_INS_VLDMXCSR + X86_INS_VMASKMOVDQU + X86_INS_VMASKMOVPD + X86_INS_VMASKMOVPS + X86_INS_VMAXPD + X86_INS_VMAXPS + X86_INS_VMAXSD + X86_INS_VMAXSS + X86_INS_VMCALL + X86_INS_VMCLEAR + X86_INS_VMFUNC + X86_INS_VMINPD + X86_INS_VMINPS + X86_INS_VMINSD + X86_INS_VMINSS + X86_INS_VMLAUNCH + X86_INS_VMLOAD + X86_INS_VMMCALL + X86_INS_VMOVQ + X86_INS_VMOVDDUP + X86_INS_VMOVD + X86_INS_VMOVDQA32 + X86_INS_VMOVDQA64 + X86_INS_VMOVDQA + X86_INS_VMOVDQU16 + X86_INS_VMOVDQU32 + X86_INS_VMOVDQU64 + X86_INS_VMOVDQU8 + X86_INS_VMOVDQU + X86_INS_VMOVHLPS + X86_INS_VMOVHPD + X86_INS_VMOVHPS + X86_INS_VMOVLHPS + X86_INS_VMOVLPD + X86_INS_VMOVLPS + X86_INS_VMOVMSKPD + X86_INS_VMOVMSKPS + X86_INS_VMOVNTDQA + X86_INS_VMOVNTDQ + X86_INS_VMOVNTPD + X86_INS_VMOVNTPS + X86_INS_VMOVSD + X86_INS_VMOVSHDUP + X86_INS_VMOVSLDUP + X86_INS_VMOVSS + X86_INS_VMOVUPD + X86_INS_VMOVUPS + X86_INS_VMPSADBW + X86_INS_VMPTRLD + X86_INS_VMPTRST + X86_INS_VMREAD + X86_INS_VMRESUME + X86_INS_VMRUN + X86_INS_VMSAVE + X86_INS_VMULPD + X86_INS_VMULPS + X86_INS_VMULSD + X86_INS_VMULSS + X86_INS_VMWRITE + X86_INS_VMXOFF + X86_INS_VMXON + X86_INS_VPABSB + X86_INS_VPABSD + X86_INS_VPABSQ + X86_INS_VPABSW + X86_INS_VPACKSSDW + X86_INS_VPACKSSWB + X86_INS_VPACKUSDW + X86_INS_VPACKUSWB + X86_INS_VPADDB + X86_INS_VPADDD + X86_INS_VPADDQ + X86_INS_VPADDSB + X86_INS_VPADDSW + X86_INS_VPADDUSB + X86_INS_VPADDUSW + X86_INS_VPADDW + X86_INS_VPALIGNR + X86_INS_VPANDD + X86_INS_VPANDND + X86_INS_VPANDNQ + X86_INS_VPANDN + X86_INS_VPANDQ + X86_INS_VPAND + X86_INS_VPAVGB + X86_INS_VPAVGW + X86_INS_VPBLENDD + X86_INS_VPBLENDMD + X86_INS_VPBLENDMQ + X86_INS_VPBLENDVB + X86_INS_VPBLENDW + X86_INS_VPBROADCASTB + X86_INS_VPBROADCASTD + X86_INS_VPBROADCASTMB2Q + X86_INS_VPBROADCASTMW2D + X86_INS_VPBROADCASTQ + X86_INS_VPBROADCASTW + X86_INS_VPCLMULQDQ + X86_INS_VPCMOV + X86_INS_VPCMP + X86_INS_VPCMPD + X86_INS_VPCMPEQB + X86_INS_VPCMPEQD + X86_INS_VPCMPEQQ + X86_INS_VPCMPEQW + X86_INS_VPCMPESTRI + X86_INS_VPCMPESTRM + X86_INS_VPCMPGTB + X86_INS_VPCMPGTD + X86_INS_VPCMPGTQ + X86_INS_VPCMPGTW + X86_INS_VPCMPISTRI + X86_INS_VPCMPISTRM + X86_INS_VPCMPQ + X86_INS_VPCMPUD + X86_INS_VPCMPUQ + X86_INS_VPCOMB + X86_INS_VPCOMD + X86_INS_VPCOMQ + X86_INS_VPCOMUB + X86_INS_VPCOMUD + X86_INS_VPCOMUQ + X86_INS_VPCOMUW + X86_INS_VPCOMW + X86_INS_VPCONFLICTD + X86_INS_VPCONFLICTQ + X86_INS_VPERM2F128 + X86_INS_VPERM2I128 + X86_INS_VPERMD + X86_INS_VPERMI2D + X86_INS_VPERMI2PD + X86_INS_VPERMI2PS + X86_INS_VPERMI2Q + X86_INS_VPERMIL2PD + X86_INS_VPERMIL2PS + X86_INS_VPERMILPD + X86_INS_VPERMILPS + X86_INS_VPERMPD + X86_INS_VPERMPS + X86_INS_VPERMQ + X86_INS_VPERMT2D + X86_INS_VPERMT2PD + X86_INS_VPERMT2PS + X86_INS_VPERMT2Q + X86_INS_VPEXTRB + X86_INS_VPEXTRD + X86_INS_VPEXTRQ + X86_INS_VPEXTRW + X86_INS_VPGATHERDD + X86_INS_VPGATHERDQ + X86_INS_VPGATHERQD + X86_INS_VPGATHERQQ + X86_INS_VPHADDBD + X86_INS_VPHADDBQ + X86_INS_VPHADDBW + X86_INS_VPHADDDQ + X86_INS_VPHADDD + X86_INS_VPHADDSW + X86_INS_VPHADDUBD + X86_INS_VPHADDUBQ + X86_INS_VPHADDUBW + X86_INS_VPHADDUDQ + X86_INS_VPHADDUWD + X86_INS_VPHADDUWQ + X86_INS_VPHADDWD + X86_INS_VPHADDWQ + X86_INS_VPHADDW + X86_INS_VPHMINPOSUW + X86_INS_VPHSUBBW + X86_INS_VPHSUBDQ + X86_INS_VPHSUBD + X86_INS_VPHSUBSW + X86_INS_VPHSUBWD + X86_INS_VPHSUBW + X86_INS_VPINSRB + X86_INS_VPINSRD + X86_INS_VPINSRQ + X86_INS_VPINSRW + X86_INS_VPLZCNTD + X86_INS_VPLZCNTQ + X86_INS_VPMACSDD + X86_INS_VPMACSDQH + X86_INS_VPMACSDQL + X86_INS_VPMACSSDD + X86_INS_VPMACSSDQH + X86_INS_VPMACSSDQL + X86_INS_VPMACSSWD + X86_INS_VPMACSSWW + X86_INS_VPMACSWD + X86_INS_VPMACSWW + X86_INS_VPMADCSSWD + X86_INS_VPMADCSWD + X86_INS_VPMADDUBSW + X86_INS_VPMADDWD + X86_INS_VPMASKMOVD + X86_INS_VPMASKMOVQ + X86_INS_VPMAXSB + X86_INS_VPMAXSD + X86_INS_VPMAXSQ + X86_INS_VPMAXSW + X86_INS_VPMAXUB + X86_INS_VPMAXUD + X86_INS_VPMAXUQ + X86_INS_VPMAXUW + X86_INS_VPMINSB + X86_INS_VPMINSD + X86_INS_VPMINSQ + X86_INS_VPMINSW + X86_INS_VPMINUB + X86_INS_VPMINUD + X86_INS_VPMINUQ + X86_INS_VPMINUW + X86_INS_VPMOVDB + X86_INS_VPMOVDW + X86_INS_VPMOVMSKB + X86_INS_VPMOVQB + X86_INS_VPMOVQD + X86_INS_VPMOVQW + X86_INS_VPMOVSDB + X86_INS_VPMOVSDW + X86_INS_VPMOVSQB + X86_INS_VPMOVSQD + X86_INS_VPMOVSQW + X86_INS_VPMOVSXBD + X86_INS_VPMOVSXBQ + X86_INS_VPMOVSXBW + X86_INS_VPMOVSXDQ + X86_INS_VPMOVSXWD + X86_INS_VPMOVSXWQ + X86_INS_VPMOVUSDB + X86_INS_VPMOVUSDW + X86_INS_VPMOVUSQB + X86_INS_VPMOVUSQD + X86_INS_VPMOVUSQW + X86_INS_VPMOVZXBD + X86_INS_VPMOVZXBQ + X86_INS_VPMOVZXBW + X86_INS_VPMOVZXDQ + X86_INS_VPMOVZXWD + X86_INS_VPMOVZXWQ + X86_INS_VPMULDQ + X86_INS_VPMULHRSW + X86_INS_VPMULHUW + X86_INS_VPMULHW + X86_INS_VPMULLD + X86_INS_VPMULLW + X86_INS_VPMULUDQ + X86_INS_VPORD + X86_INS_VPORQ + X86_INS_VPOR + X86_INS_VPPERM + X86_INS_VPROTB + X86_INS_VPROTD + X86_INS_VPROTQ + X86_INS_VPROTW + X86_INS_VPSADBW + X86_INS_VPSCATTERDD + X86_INS_VPSCATTERDQ + X86_INS_VPSCATTERQD + X86_INS_VPSCATTERQQ + X86_INS_VPSHAB + X86_INS_VPSHAD + X86_INS_VPSHAQ + X86_INS_VPSHAW + X86_INS_VPSHLB + X86_INS_VPSHLD + X86_INS_VPSHLQ + X86_INS_VPSHLW + X86_INS_VPSHUFB + X86_INS_VPSHUFD + X86_INS_VPSHUFHW + X86_INS_VPSHUFLW + X86_INS_VPSIGNB + X86_INS_VPSIGND + X86_INS_VPSIGNW + X86_INS_VPSLLDQ + X86_INS_VPSLLD + X86_INS_VPSLLQ + X86_INS_VPSLLVD + X86_INS_VPSLLVQ + X86_INS_VPSLLW + X86_INS_VPSRAD + X86_INS_VPSRAQ + X86_INS_VPSRAVD + X86_INS_VPSRAVQ + X86_INS_VPSRAW + X86_INS_VPSRLDQ + X86_INS_VPSRLD + X86_INS_VPSRLQ + X86_INS_VPSRLVD + X86_INS_VPSRLVQ + X86_INS_VPSRLW + X86_INS_VPSUBB + X86_INS_VPSUBD + X86_INS_VPSUBQ + X86_INS_VPSUBSB + X86_INS_VPSUBSW + X86_INS_VPSUBUSB + X86_INS_VPSUBUSW + X86_INS_VPSUBW + X86_INS_VPTESTMD + X86_INS_VPTESTMQ + X86_INS_VPTESTNMD + X86_INS_VPTESTNMQ + X86_INS_VPTEST + X86_INS_VPUNPCKHBW + X86_INS_VPUNPCKHDQ + X86_INS_VPUNPCKHQDQ + X86_INS_VPUNPCKHWD + X86_INS_VPUNPCKLBW + X86_INS_VPUNPCKLDQ + X86_INS_VPUNPCKLQDQ + X86_INS_VPUNPCKLWD + X86_INS_VPXORD + X86_INS_VPXORQ + X86_INS_VPXOR + X86_INS_VRCP14PD + X86_INS_VRCP14PS + X86_INS_VRCP14SD + X86_INS_VRCP14SS + X86_INS_VRCP28PD + X86_INS_VRCP28PS + X86_INS_VRCP28SD + X86_INS_VRCP28SS + X86_INS_VRCPPS + X86_INS_VRCPSS + X86_INS_VRNDSCALEPD + X86_INS_VRNDSCALEPS + X86_INS_VRNDSCALESD + X86_INS_VRNDSCALESS + X86_INS_VROUNDPD + X86_INS_VROUNDPS + X86_INS_VROUNDSD + X86_INS_VROUNDSS + X86_INS_VRSQRT14PD + X86_INS_VRSQRT14PS + X86_INS_VRSQRT14SD + X86_INS_VRSQRT14SS + X86_INS_VRSQRT28PD + X86_INS_VRSQRT28PS + X86_INS_VRSQRT28SD + X86_INS_VRSQRT28SS + X86_INS_VRSQRTPS + X86_INS_VRSQRTSS + X86_INS_VSCATTERDPD + X86_INS_VSCATTERDPS + X86_INS_VSCATTERPF0DPD + X86_INS_VSCATTERPF0DPS + X86_INS_VSCATTERPF0QPD + X86_INS_VSCATTERPF0QPS + X86_INS_VSCATTERPF1DPD + X86_INS_VSCATTERPF1DPS + X86_INS_VSCATTERPF1QPD + X86_INS_VSCATTERPF1QPS + X86_INS_VSCATTERQPD + X86_INS_VSCATTERQPS + X86_INS_VSHUFPD + X86_INS_VSHUFPS + X86_INS_VSQRTPD + X86_INS_VSQRTPS + X86_INS_VSQRTSD + X86_INS_VSQRTSS + X86_INS_VSTMXCSR + X86_INS_VSUBPD + X86_INS_VSUBPS + X86_INS_VSUBSD + X86_INS_VSUBSS + X86_INS_VTESTPD + X86_INS_VTESTPS + X86_INS_VUNPCKHPD + X86_INS_VUNPCKHPS + X86_INS_VUNPCKLPD + X86_INS_VUNPCKLPS + X86_INS_VZEROALL + X86_INS_VZEROUPPER + X86_INS_WAIT + X86_INS_WBINVD + X86_INS_WRFSBASE + X86_INS_WRGSBASE + X86_INS_WRMSR + X86_INS_XABORT + X86_INS_XACQUIRE + X86_INS_XBEGIN + X86_INS_XCHG + X86_INS_FXCH + X86_INS_XCRYPTCBC + X86_INS_XCRYPTCFB + X86_INS_XCRYPTCTR + X86_INS_XCRYPTECB + X86_INS_XCRYPTOFB + X86_INS_XEND + X86_INS_XGETBV + X86_INS_XLATB + X86_INS_XRELEASE + X86_INS_XRSTOR + X86_INS_XRSTOR64 + X86_INS_XSAVE + X86_INS_XSAVE64 + X86_INS_XSAVEOPT + X86_INS_XSAVEOPT64 + X86_INS_XSETBV + X86_INS_XSHA1 + X86_INS_XSHA256 + X86_INS_XSTORE + X86_INS_XTEST + X86_INS_ENDING ' mark the end of the list of insn +End Enum + +'Group of X86 instructions +Public Enum x86_insn_group + X86_GRP_INVALID = 0 ' = CS_GRP_INVALID + + ' > Generic groups ' + X86_GRP_JUMP 'all jump instructions (conditional+direct+indirect jumps) = CS_GRP_JUMP + X86_GRP_CALL 'all call instructions = CS_GRP_CALL + X86_GRP_RET ' all return instructions = CS_GRP_RET + X86_GRP_INT 'all interrupt instructions (int+syscall) = CS_GRP_INT + X86_GRP_IRET 'all interrupt return instructions = CS_GRP_IRET + + ' > Architecture-specific groups + X86_GRP_VM = 128 ' all virtualization instructions (VT-x + AMD-V) + X86_GRP_3DNOW + X86_GRP_AES + X86_GRP_ADX + X86_GRP_AVX + X86_GRP_AVX2 + X86_GRP_AVX512 + X86_GRP_BMI + X86_GRP_BMI2 + X86_GRP_CMOV + X86_GRP_F16C + X86_GRP_FMA + X86_GRP_FMA4 + X86_GRP_FSGSBASE + X86_GRP_HLE + X86_GRP_MMX + X86_GRP_MODE32 + X86_GRP_MODE64 + X86_GRP_RTM + X86_GRP_SHA + X86_GRP_SSE1 + X86_GRP_SSE2 + X86_GRP_SSE3 + X86_GRP_SSE41 + X86_GRP_SSE42 + X86_GRP_SSE4A + X86_GRP_SSSE3 + X86_GRP_PCLMUL + X86_GRP_XOP + X86_GRP_CDI + X86_GRP_ERI + X86_GRP_TBM + X86_GRP_16BITMODE + X86_GRP_NOT64BITMODE + X86_GRP_SGX + X86_GRP_DQI + X86_GRP_BWI + X86_GRP_PFI + X86_GRP_VLX + X86_GRP_SMAP + X86_GRP_NOVLX + X86_GRP_ENDING +End Enum + + + +Function x86_sse_cc2str(v As x86_sse_cc) As String + Dim r As String + If v = X86_SSE_CC_INVALID Then r = "X86_SSE_CC_INVALID" + If v = X86_SSE_CC_EQ Then r = "X86_SSE_CC_EQ" + If v = X86_SSE_CC_LT Then r = "X86_SSE_CC_LT" + If v = X86_SSE_CC_LE Then r = "X86_SSE_CC_LE" + If v = X86_SSE_CC_UNORD Then r = "X86_SSE_CC_UNORD" + If v = X86_SSE_CC_NEQ Then r = "X86_SSE_CC_NEQ" + If v = X86_SSE_CC_NLT Then r = "X86_SSE_CC_NLT" + If v = X86_SSE_CC_NLE Then r = "X86_SSE_CC_NLE" + If v = X86_SSE_CC_ORD Then r = "X86_SSE_CC_ORD" + If v = X86_SSE_CC_EQ_UQ Then r = "X86_SSE_CC_EQ_UQ" + If v = X86_SSE_CC_NGE Then r = "X86_SSE_CC_NGE" + If v = X86_SSE_CC_NGT Then r = "X86_SSE_CC_NGT" + If v = X86_SSE_CC_FALSE Then r = "X86_SSE_CC_FALSE" + If v = X86_SSE_CC_NEQ_OQ Then r = "X86_SSE_CC_NEQ_OQ" + If v = X86_SSE_CC_GE Then r = "X86_SSE_CC_GE" + If v = X86_SSE_CC_GT Then r = "X86_SSE_CC_GT" + If v = X86_SSE_CC_TRUE Then r = "X86_SSE_CC_TRUE" + + If Len(r) = 0 Then + r = "Unknown: " & Hex(v) + ElseIf DEBUG_DUMP Then + r = r & " (" & Hex(v) & ")" + End If + + x86_sse_cc2str = r + +End Function + +Function x86_avx_cc2str(v As x86_avx_cc) As String + Dim r As String + If v = X86_AVX_CC_INVALID Then r = "X86_AVX_CC_INVALID" + If v = X86_AVX_CC_EQ Then r = "X86_AVX_CC_EQ" + If v = X86_AVX_CC_LT Then r = "X86_AVX_CC_LT" + If v = X86_AVX_CC_LE Then r = "X86_AVX_CC_LE" + If v = X86_AVX_CC_UNORD Then r = "X86_AVX_CC_UNORD" + If v = X86_AVX_CC_NEQ Then r = "X86_AVX_CC_NEQ" + If v = X86_AVX_CC_NLT Then r = "X86_AVX_CC_NLT" + If v = X86_AVX_CC_NLE Then r = "X86_AVX_CC_NLE" + If v = X86_AVX_CC_ORD Then r = "X86_AVX_CC_ORD" + If v = X86_AVX_CC_EQ_UQ Then r = "X86_AVX_CC_EQ_UQ" + If v = X86_AVX_CC_NGE Then r = "X86_AVX_CC_NGE" + If v = X86_AVX_CC_NGT Then r = "X86_AVX_CC_NGT" + If v = X86_AVX_CC_FALSE Then r = "X86_AVX_CC_FALSE" + If v = X86_AVX_CC_NEQ_OQ Then r = "X86_AVX_CC_NEQ_OQ" + If v = X86_AVX_CC_GE Then r = "X86_AVX_CC_GE" + If v = X86_AVX_CC_GT Then r = "X86_AVX_CC_GT" + If v = X86_AVX_CC_TRUE Then r = "X86_AVX_CC_TRUE" + If v = X86_AVX_CC_EQ_OS Then r = "X86_AVX_CC_EQ_OS" + If v = X86_AVX_CC_LT_OQ Then r = "X86_AVX_CC_LT_OQ" + If v = X86_AVX_CC_LE_OQ Then r = "X86_AVX_CC_LE_OQ" + If v = X86_AVX_CC_UNORD_S Then r = "X86_AVX_CC_UNORD_S" + If v = X86_AVX_CC_NEQ_US Then r = "X86_AVX_CC_NEQ_US" + If v = X86_AVX_CC_NLT_UQ Then r = "X86_AVX_CC_NLT_UQ" + If v = X86_AVX_CC_NLE_UQ Then r = "X86_AVX_CC_NLE_UQ" + If v = X86_AVX_CC_ORD_S Then r = "X86_AVX_CC_ORD_S" + If v = X86_AVX_CC_EQ_US Then r = "X86_AVX_CC_EQ_US" + If v = X86_AVX_CC_NGE_UQ Then r = "X86_AVX_CC_NGE_UQ" + If v = X86_AVX_CC_NGT_UQ Then r = "X86_AVX_CC_NGT_UQ" + If v = X86_AVX_CC_FALSE_OS Then r = "X86_AVX_CC_FALSE_OS" + If v = X86_AVX_CC_NEQ_OS Then r = "X86_AVX_CC_NEQ_OS" + If v = X86_AVX_CC_GE_OQ Then r = "X86_AVX_CC_GE_OQ" + If v = X86_AVX_CC_GT_OQ Then r = "X86_AVX_CC_GT_OQ" + If v = X86_AVX_CC_TRUE_US Then r = "X86_AVX_CC_TRUE_US" + + If Len(r) = 0 Then + r = "Unknown: " & Hex(v) + ElseIf DEBUG_DUMP Then + r = r & " (" & Hex(v) & ")" + End If + + x86_avx_cc2str = r + +End Function + + +Function x86_avx_rm2str(v As x86_avx_rm) As String + Dim r As String + + If v = X86_AVX_RM_INVALID Then r = "X86_AVX_RM_INVALID" + If v = X86_AVX_RM_RN Then r = "X86_AVX_RM_RN" + If v = X86_AVX_RM_RD Then r = "X86_AVX_RM_RD" + If v = X86_AVX_RM_RU Then r = "X86_AVX_RM_RU" + If v = X86_AVX_RM_RZ Then r = "X86_AVX_RM_RZ" + + If Len(r) = 0 Then + r = "Unknown: " & Hex(v) + ElseIf DEBUG_DUMP Then + r = r & " (" & Hex(v) & ")" + End If + + x86_avx_rm2str = r +End Function + + diff --git a/white_patch_detect/capstone-master/bindings/vb6/screenshot.png b/white_patch_detect/capstone-master/bindings/vb6/screenshot.png new file mode 100644 index 0000000000000000000000000000000000000000..3780f670241f1f0ebc301462dcd9db6fffe9ccab GIT binary patch literal 23811 zcmdtK2Ut_t*Dst9I)q*Vp^6A7K~S2~LQ5!8?GdFZhEN0qR78w|^w0$cR7$8S3JM4+ zNC)dA5NU!+HHt8TQ2_<+4&VsRy!Sr;`@P?N?sLb-VTNtSbocOV;DYHpUQ0MMCIz zhg9(Ya_$z6HV{aNA_PJVhd}0*z|Z#(NRT=N^1%fH*_jD}h@VJtZpA<#PG>C5jQ5=G zcY7Ex)N(%3L7f}ZsElAEyNJYJ1pgDM+@Vt90^yVs6EHpWCR9^%-BnCu5{yJ5xk$

HJM9%fXG2k9Sdxh^vC6D&nBIrZI@kB@Di<(znIyx|p|v7@+>p?5y+R{Dq%CZ{4ReJa#Ipbpz3Za*)S zUGcu`N|}6zuGcC14$J}n*V}H&orr(_G8)zVp}g;*hIaNn!EPUe$C!igL#K+9%APGn z!td<#p2rbU9(8}k_%FG4Z_F+`7XO@j#xDN5Q7AS;^yT|p-|f{bOZOx!?-&fEPJPcg zeX-)O=Jl?}_oW#HxFx-XspM-ScZc;~&c2x(GdFlVzvNv1&C4M~lqjty2L)UZU@Qgc zv0Tk7WrMhEg|=*yWc^9iWg<4qnq|$Tmi17n$*xO_3nK6BCi>B$ry8Cab3mY){Uy?W zGl6-#Jn>36wA;JaSZjf%%^?9{6==jv-qY)P>#cVArl8=^?H8xQJ^jg!_xr!oPj9(` zIRpsm;1Qjm6aKo$E~|dEw_Mab z^hljfrY)ggTXM(pKB2Ik>|(4hoof9q-tuMPlpDqnmQ1IP&qh{LGBYt#J+F2*Y9`{e zGZzEAxHHH1{^>d!dXhUb#E_(~`+ek#rE&lZZVvI`jq@Kw`Ar3fIE&sKnSymSg_s}Z zpgcX9#C|KnU*fQ2Wk5rls#f~RHwLt5`J!QpMbIhdS9{?_RRjI>bo`$u)EWi0&-``i z?w`KO>|Jfpa|-tx`nDUfnLg7xqt-X>lk*3p$e>G{@|+*J3F8{gCaS9R>fuX+JeQp} z1GSC>ZP^*#7-%+!yEBRF{J>x2?xoFlzf$AI6KPY`x^v>q@!b2>^~mlzk3DQr{!Ic; zCkO3BzkPkz=N2t$XV^r^c89sz?TFp$d@5b^%36QW5Hv)vr{t2B#}fI7VdOwZ;Zc!{{RZOR zt;NXH3#Wx(IUX_(ji2%#b^qAb!V(cE2k$$ze_rDC;i=;S?AqR!g5nU$KJq3QFO5@X z{2mZ5%H~%(=zRXm2<-;SZH|xRli5~?7e1{Alrrw}F<+5`a#w@L zmtuQS6AzooaNn^&tR|+keY9uEja1zxSF91o7ZCEbaRN?g-%BlM&eVIX0vX#bCwlC7 zBwM+>*M-h zKGMw#%{IJN=qwSx?`Q*V=jVcMuglJ5j^lN8n)`IV=BmX|0?k!3YN~mLWqnR{L{GlF zTC&(RO`Kht`O3|!$9TAN=wsX=2W$&G^gic&J7;grB`t5#1^6LGa{u-T2kZx%@cBkY zY0xF*;qk_3how|6`{Qh?Ch}Krj@+2BZz*e13V-juH9gt{$>yQL zXxrSwj6jjO@VM=7y*X5^1;1{MP&N09&0#D0hO&Tlz2LeV6T38cGF78xVE1@qpWbmL zHy_G|M4E55U}9dIp0K~v+jLKV<$(IWxYBEndcI(DKZVEbyZBz~+z^6bYP~P-)Bd1l zjCYUv&5wN0yUkCDA8)z%g^RtiKzU2BaGLGC#nJV&pQSM{Q1ob5Q)f3sU3xdEx23#> zZKvCz2VA?h626-HTZayM=$>^Y^HUdd_P=90uB3BcLSeF63g7nY&2X!o`z*!R`;`W1X7wc?7il*)zvg zYdh@4$^7qhw$^F(UzcQSzJ7t%t5>KC-^LDMDL;8?tIZ{UsfL{I_tT;|Cp;`8EVs(Q zojnwb_KDvZGS9atrMVFBX~Wj{U9m>m zjh#t2YwL4Y^hmVxY(SFqi_zSV%|lPSe_TEi{NSqJ4avlIiMyWY2dzaO9P%ea%7YU5 zh&j$tbQRPl|1e^sQngX~#bG_oy>zb04esX8`4`h}J`CRMacnU`e;fXuG@V%VhU#k+ z__F2W%tsWwQg7xq^k`6x3S~-_p1%o(+VqO0|FHR>+bKc!udm{%*xh(PU+z$4{_&U!n=3-21ROLhW;sb z>`vtw>F{wc_P5=T4oRWAvP%7$6tSJ*#J;yD zat$1}n;m8=dlhlB>0^|`!ik5oPSNUdXN-o06sx{L?*91vKq-T)eGbIWtB4 z1hnQ$UHm{tgC`fxP@7@n*u|z(B|ds9_<-Bj6Q6VMHhJHX!|xTrAFfv!O38#D-f`>d z`FkUX{chUemxo{{%#k9(c$7^@{i8y&*}>l7pt+F)EYJGk}8*Kqxplp==YKkTtwMB4fpEe;H9Dn?Yl!R*(!LAN2~&U#j*{OwQ}h9 zdG)>NvJDXLIp|H-IG@9)8u_?mbB!)AJKO3Z=|V+OWfLsk5`K=6jB{)VIxr$u=3s3@ zG{jlMA;>awUs`@5Ek9hiyv;}XL;uvs4LQ<*17tCF3i3`ROTzT_Msn46v7*M-D?%P4 zyEtgLF!bi$ZSeD^!Ch$xk^1vfozUkwxyiT?l$MEXS)rJP=W9Nhva7qp@uS1YLUZRZ zBAkdJPb8wcpj<>BS%Ri9c2+c8Q(kg7I|s%0L3wkx8bF|K z8L|SfEFn^PEIE;u00O!c=!`OI#*x(xgk>a|_vRdO?nh$o{CGPZqkUb=+mh{6E*#gZ zJUO}0qUERMgtJeVb$WBy=58d)J56k)T5=oF5-l5ADaLAhdn@Z!BVD);r3vF{XN>hU zZqPrv;mJ(6@Qu$6@Iz0_EtQ}0qZKMU;D>sZQM|l8NT+DFatEB#G(F=k>*w@5K^C+^ z70vq!6$wtI;kzdv!aUsx5i%>|=%MDmj_g)Sh8(e*wn4|+lgou%*>NO73qM4zB*Ogd*OM=M<4#p#Fck~Le3ZR`s)Kes@a|=04C5YhX7)Lmq*xhvzGQ-8G z3_tX#6V_>K0@3mYZkGZrapl20D$bopgvvNkJ_~9;81@8JP{GCr2xv#LdKR z{1a@x33A#7rEs(ldfEWhS#hK$U4{tpHb8NLODUaw;#$hk+c(Yy)kl5ggq9VumECBq zJ{aF?+6t%nSxNYL%e`}^$m_3qTe?cSgbDHVygf#=_UieuMwkgS-keFqSfD0=)v>0PU*hFtaZr?C}t;+sNIg&pj z{U-bJrs59}eaHv)ybSr|QBmjvMSO6-u5&T*i^*$c_NLsRs$T85)}9mWw{ILqk9uf$ zBU|zCJNLg5dtT;mHR_mp&2ik$cxQhcCHctQ0!QNnftn$kbpPN@9S)6chqirDe!O^* z)N5jkMoV$>GdDb&z-Zziyvtz&8*vVU^sBPt?06*0q^0wu*-UF4cEO2Wn(4GL5M|@_ z9w@N7A`-I2_fI$Ko$E4}irx_#$nD|BBJRgm$Wh>#wKezQ+`HTvFVhsV6H7DOqt9Ow zu1fnRW`u0>X+ftBq%ndIAKz5jU}ZI?3$Gg2vwx_``|`jzN9GInJof5??5%&qUc+oX zkxO~m+x+KWXLtGT{sO!D($$ppzzeIzj$_#jr-ip>n`Jsaiyg$ezE;)VYwa!Aonq6e zhRnIAc$4Gn+=W(;J2D?oA#$PupHO8D-3^Q1-(?QW1RVL%6`Qr!b;}8Bmm3F7z2P5? zDia1W4tg{H#wNTn>#k)n`Kx^AM9Ceiu>P;FPO`CvT0fvJ)*VMCqLa$}ci~PfMcN$j zzMTFeka9v#!_)cu{^6^wVhNUpH}vgZO&Yzp@4PE((x|HV@T7YO1=NRFPd+A-$CgenA|}v=cMECY5Dg z2Wcl!9Ye4yi$Si*R3W^J!YbO!i7y@^@bBr{KN2!FQyB;=1y2rMNt9RLF2Z{T1jA%f z|8HsVDAV3*6R=9n6Pk;dM*I&_ z+Z*t&mRYh$eB097#PdXmn|%A*8{&2eky8+&7Bbkr^$K+sNqXd^GszhkH4oC-vs}4U%;dUbC?jS7T`|b2b@?sXrGv>IpJl(Z z233&fhp^x)9rV`xiU~C61CSv-?}MK-j7RtTlS{&^trhRF8SO>l**imr$;7YI*x1)# zpF5|cP`;Rv6K{u4X@+8t=qIP>U>o0VO$6Wwcz!4;*)4NjPNpee^$~_w^ch>c^daYN9$irotjmGQ7x4n65%~M{E zNfc(xO0YF=xrRAz78w@Ou-_y9DSYe)uK?OKU=AAcSK1Y=s))^gN9!UYzhbxREsXFN zC1eIUgLP_#6KVQ8CC@X;Ag)6(K9*eC+8SQD*hWfpF}3QC<{SE(ihi{0KgHL|Tujwe zrOEG@1%ubtHzNL)wZzV8Z2Up8i(i|p#)SW}putk#U_Xz4iq`R#7G(rT_Z*4NWbQ!#T#>fnnC5o)92}YllbvH{bHI{SwdVj5s5= z5w3&2nv0Q`A46LX0FeZ`a^Z0g*@fPQEG>5DjnV|lV(MmtlGj%I(voF;9Z}&c!B!b# zM3DNTC3!x4%c2D-n>tJOadH<{+JuU4Yo#P8InDsq{qVdfRhuW%4uSSQfC&K+g%~e6 z-&3F{5CWi(Uh97WQ2ukZ`cL##;2<`ntgqZ%b2L&NL3#uPm2Fwpm`83~@`FL3W&z}G zD%D?;_OCav0*ap=Yl>OwpC9L42GU5sS&#wg!zvV#j?4-axV5-wXv?CHwA8fdYkm z05R;Sasjv(IZuDRCBSn>*U9n9K^_F7SpZ+<=t~p9toKce#UR8wRskL@xckwgW6BEk{fDhZx1P0cJPLh zL^5@EZJm!+(AGvt8nw*xXGq;DSLhBkndgwqeIV%Ul&FpSJV)X(#xioyqL5KvIEh~PXDJ2v>V8(K5 zHi<9j-uipR)!@Pc$~1`xDUF>bT7Q#Z86j6@UeWvw+a&M6KYHDOSQR1 zPUS&PGrWRm-Y3Pt7hCdbg?2#(~_{;KD6h3}NB= zmfpnMc~-X;YJ3fl28Ld11dax5hi2|mehgBp628ST@uuW2kq6<%b>Nyy>K)=UU)B3v zwTqj$a`32Djih_auCi2up|%mlEkbZ`l6Ig79fQPT9e(l1L7fJCqeGQL+==^t*f)!8 zjIuV;*niEC2t$O`p;t7xNgt~i7<7rLW3SY10X(qtsA z7c-1E4Onwr1vuam@kl+|O2J1CWXQ!hXAAd@+85Pv>`M! zfYB^j-OF$pA)jDZIBIwcvt0`rHk&RkFmm2ItZm%LX=)SZn&ecwXc(;*!i*9AUW&*A z^!eqBQpHPl*TVt^(AVc$`YkQp<0-fU0fSi7z0@ssiRHlB|B6BzIG9ehL^m+-_`=`I zEK6tu8_>xPO#&8KvF3gd5kkPJ<%+0sYlB1ZsHyb-Eg|NA;tT)p2#WvT-mw7Bj;x|x zbeEct=}|nLnRcy_Sz{;=z)_6PxpNEnlHacZ5d_yJ>72jE@ZP{sbl}3uJ(?4!N$Ug} z!KTTPyO*Vf_c{x3ZM9-jx_&O2X=_adHwO9~f|nJq0BamjuD~z*b%Qlq0{bgxu}Uu+ z7ul0kAOmh<@BB>#Tu#G$&Yev8qN%N&a+3qxfe8;;qxL{wC_)r>0TDUK*;8u*gAlVh z5GDM7O-fkq!$96~J&WVtayL0Rj-c%g{g9so(m$CQ!DBY5xiQo?f6&?>rOyl;qtj(8s z#K;U~1FOW&Uq9eQj|N>`DBU_rwIs_IDQqBDTCOQ49Ru;~Mw~GIF%+*W(OojO@43um z?6QCO+sv|v_z`TRV5O70MyogB3o??zGI7js>pe$q`s{ieieQ5=MR;?uEHN^Z+6c;! zL*CvBwUy~nrHx8hukRc}Zv$lS=xPllZi%N(%D?2pMJ?GUzG+OU$25ERMRnPeln7&w zhOXF7zdQkxHX@I`Q${E=Lm5w6Q@8EgC*H6|r9$;w?epcL!5yIjHmGkS+{eAglifJV zn$MTC|K$QH57gvlKc!235*9MbMaVR|()Av#jpw?YsJ@7o(BP)SncI8HUrwU&1$xN( zMDXrvOuTVNLD7)2RGRc^nH4SweMHa_I9NE-yVzg=3piB##7pj|<;HW_+h#t+#+LHKrSJURs7ZAWW_IU`j*7 zg$tW+dhVSaIcbC{GLEvIg&#f6k)x}XQRFglbSM?OKirPL>PKRk{H3R1ZUg)y?p@f9 zFt;wldfg^*kB9;61jF2OmOpS&PH~BsMr^{*>2kAg2X2{~+%HHe&kfGAxot)4jSVZg z^v1&Cd|JnDf?<87X6EK&R$Zd^bJ*SAWrf?LVX|aH$_}yz?})RAHh(+YvKzPV*d`{lQ~YxJBP~^yCBtT~0LBqI4NMb0nB0rLw%hvI!JFiFG)Kc3V=F29&sT7SSy#pt^AFl`9fS0XuRF+9 z3kBXH`ClDQ^Un z!A&7)GKJXpdA8v@KPXV &HpkD}xO1QvQW2{M;LKHr>!{*MyT1W7w<2xB3-ZQ(L z{5!(L4G`^fmba6E-ndD^r`Bt{I_XLRF;&oh62lL?gc*17?g#5KAvbi8I!=Or zX|}by(e${xSA$@RQuX#2JE@%Sl#D-J4%wQLUZ~0YJNXt=eP6XaOhgADRE`zHl5D-r z$2A{DI{)DF_|EmX>wXu|f%stV6)#8BUw#E{^ByNMsT!0~^a2^aqbVVhk6i**cM;Fh z529V>Vh21)+IVa;*jSmSuE2J#@WFGd(Vi5Dr~%Ea@$>QBGjwtZouI5GJNU72-+OyW z!-&mJf!jOafZUpTfxX&0@@{jrzO+}^XqT|i;TfOwo$^_=UVoQu{iabv?>UYPefe)c zjW(JMNW|S_oC%vcYAmKqN+ntLBT37uIm)q)Ec)q_Z||@$8S^?n_;qVlOnjDjs=dNr zf)n*WNuLQ619SWFYWhjF?OUble-Dr;@LW4quz$hU>rAGkiITWI!O(E-0&7|%zsk5U zw`ssfxvvaXs|B?0d~VRZtQyf?649Y=_EeayMDS6i+9SL)`wHpMCjbL9J!wKak0;B7 z;_ja)-_H&f*>M@A^=J3SZq^0$K2zcR;@> zZ|{lT;8BpA_0@f1kKh)&zu4vO55mUMsXw+aOLzj4kjSb%*RQY(BY1T}9K39X&{2QU zvrO3^!p#`!O;ws~&Zkp4%bRpACxo6v7@niwI|Vm;ZT1LCN}uq>cKx+X`2xs_80ERi zdc$)X%RN#hzm5=;sZWi_a9opgdZUNYExtkf`)ygc_a}2d|GC003VIklIDX+WK_=tGy?Jm=J{o1RW8CutCMlCIu(p0k> zMIX^U#STdpX`bucxwIM)xGW3v7)P3no@tDJ#bpK57>DUdc)D+K(5$@zAICP|sLvJF z5eb1vdZjV^yJwK9bTuCzYQXO4&*O!Q0#eXt!dJKK^J$f%|4nE+)tijS8@$I1IOHoo zX8`7$Y(_)f?2P1k7HHA3R?n0~9)%Asn0{fv0-9Y521Cpzo{D0+dRF-40;DkClAKO~ zYct+t`` zllaAogDz(;D4QD=?_CYEv+IpBR6GLpDP<4$}njFp{@`cH9Tk7QFMo!AkOdju@WpL^d z`i-)dR@90abuiKVer5Rwj*12R&ZfsjcoX@kE|ob+KhTLuj!zeBc8YdsM<~;k;dR@X4u|N zTl023;4`w~X+l{?$W{9Dl7@j=v})PxtVY_WO)t-nYHqOLa<&?@Qx4aA&8ldL-(W&C$x5URX|TORpX26Vj(+#ZQ8=L@srVW7PrlE3X#B{_7&h ze}v5D_hB?l9-Qz*@$WXJS4#(c5mqotA|6;8N>yqPb!z8ICU8_dxTjL9d$Du2_}IKG zTQiK8QFerUFVZDQab#k0%+;#W`<yRv&3U;6Vr z4PQRAO}3{hr=S-b|6L`9!)hd_`~7(lURia4cW*nJ7l)EOu%D%Ty56A+&ssg*PpFjT z>`R=St#?3618cFXS&Qr#BE_GlP{@Arf<=c9nWWrboI`yQxSZXIATPDl@XUpd4RtGT zDq569z2Vr(B$-zLwlN9yi6cbByI_CiEN0AKl+g=-MTxiDWwZ6wcHj;>61Un2xf|^m z!j}EP?v~CkuY-?OP6mA3n|!&tI0`Ya0$1I-wUq_mEoP<&W#7~ zBU5HsB;{yFx=eSuq92pID%HH{2YZF?s(C5DR*odKy>n(DTRBnt<+b#w&s&tRF$<$L z{LWb7l~3W*74H?QQ;m215JE=QNS}zKfQh6 z$+scU!^?bKJhYzsQl}QS<(9;TcD|6C#)adOxBzZ_6R;%~gn{tWx zOKo^#%mAKi$B@|vPXyU|Po&3jsU1^(T1lQ7lG;gg>5^AZ;U38Dct*vJs-SYBp0M|W zH9j%d0BLHb&TOPtVU)h8wdIgWTvJRY`7J1x6`mO_9lmhj8`hH?rkkPDn~sui7nGm7 zFr!e789*0q#l7Qa+!24JDqZ#DI8NK*F)4?+EnukzoQ(MzbplE-vyS3*}-=^Ku?VTnwWdNh*nQ`{8u$h)Ne{@yWu6KWtY+L=N@|-c} zY5wlWB4HhE!@V;a+CMheKPoqbwwOGP(6XOt*(XyO@XE!rx3iPKhOztPps*H=vU!2G z;1!4U{U$9T(-(Ub%DS{meG3aVY*JjDt__mw607}6X`X7#tpB97=qbU`OkJp~%tkCZ zC@he)k8&_k<6qvUEbT4n%+ZjV??HjrPm9DC)eSK*zd&Xjv4Rl_zRZ-BwgmXf`xB=D z-9Pq1xc~w{%w4+uN|4TLgZiI<8TjfS#580vULI&W{+&MR3qL!$gP+_bM<$AS{(^*a zb(ls`lVDjV7%LWPHHeK_Y^2fU%tJwUs$&B_{BJnIg$3As)eKn|J%Oxi^HFDK*Cpk= z+RT`@SeAD;F|39Gwolu2s6%?AcR&r_J8VzlQz^H}_M)8Lr#u*b%hf8&@>we#tl1Gh zstFg9uPsh%$x#0aZ*Ohu=2ED>8+lte%1-9+bHCc_KlcEI!Ilf-DmQ!m_fEmMFk9X` zsAtY_RJ}}1eS^7Ov1%@dR%^z)pz{ka$)ews5vB0)p8>1_jLCr=ReSLIeAQNB+RtPE z3Y!BL*}atF#pWx5W|A@#{yy0}@Im-(j@I~)L=b|DBJN9CeHjs!jfb;^V$HN z`9~Oge`u&@1kPU_(b+@C+-Q`xHPr%LDeZDn=V52u+R+(_47^eN#pUwPrF~p7b@JvX z3=5|eSlK_%rO*C|n#9>V@?hP*q#_N|+LqAScJbF5LlvYoTo|D}d4jf;cXDLl*Qssn zi?hfM_DOVlB2D?x^x-cC+>zQq5Q~Oz0`@6GDld(2(+MA+#HX>GT{irIpXW-xW1qG= zs53jINk>wxUE8D#DzEy@0!PF%JLGt97vLguBaIAf?nH5S zhmi*PVu$!X0c1UG*GNH|k;V}A&o+@AQ|%d%>|U>di%#giO(yPPiZH3)l@ovXK-Z0J z4SVGs`wwjT(zcTzGNn+LoKVjiIS?D?_?fDgPn*hg+s<>yJn?Cm$)f4LC>vS%?=jDj z1rhSM+CWD{e(?N;O+WAwOO<{`w`}`eq}1iKLse8{-#dgQUd&r@DAulxnh2~{X~lSq z(C5-)vi01_Dak61-A>7e&ImjhKdq~M+ET((lJheMAtIrFIx+0aHy7`>l%{iO<5;U< z*;n(nj?X1J*u}L5>`2D^R!^`YX>Z8H`P_<%WVNr$;eC1n+k^!?hpJML%w}N#52rme z^ZE?>18kfbmDvLUJ|z#%GnL%f)|hSZBMWe&7}RC%sJz#ZLXRQL#MO$*K)t$WvYw(( zTw;}Qe;yS`HHz%Y`qB87!^F4Yo`{=r&3WZw4qOkEJofP|2Po94<0rDWJJp>|@y__53rkBufvHd%EIj-nE+H}VE60r-p(UPM0@K6J+3)VJJ2(rGGx{JsjI zByaCLVrrbftFFcYy8H>Fi%9 zplu!PHVs#d$3TN1ig27GvYMIh*-WjP>3y-E+Vr;>P<$m0^8*~atDC~XkSb+kQuHTo z&T`s4Ox?+F`+)%faCFTn=Stb{bhPGX1}}f#vx>{-a^=3W0C3MgY7$Tzhyj)W1-Kou zHG1%>#TI6ktoPaT*diKc@?du|w6;flxYG`B+vjzFI=`wbtX&H`(7pmca5?zQK@-eeGg~NK;pv*$&4js zl5^na_gBL#s$fXO$0=F7IxZPb^2`4s+Fco}hq9BGpl6S=U;mMhnbW*46C{$vLf_%Y zvx40eN+e{Cm_+W5EDCNWlt;ny1hc43D?mL$@+)}^q&a-VYYJ6>n)i!>MR@U0{SS*n z67T4U9DRf5Sn=W(>6ZJ6d%jQ4@n?h)E^XC*Q1ORd{9p}@H*h}R{7P5T37X#oeol*< z9kxodBdL14JZ!i(crD8KZug^S0&NiIKJ(0zOh(5wte#^Z)y4Pke>r^r4_<@G;X64= zOGz(Xm+{QcGAgdow*Ur+zY1a~qw4Hh_CtL($~QgFDD>DL76NbBy84C$8ej7fwXz;> zAuq$)A?$?K1NwaF;=8)r-ZpXy=Rh@WPkz{wef1q#nRZJWzS{VOm)styQZi+ z-GH7BLrb4>qM7P_6!hvYXJC}hmPZV3Q(WJ6oGZNSQ^8R#Slx)^8LKn81$P_YMh&Go zmnIu})(yCW#{(dx)?6LHxtOJ5P^DhMC8)&u3YNog4KEY_vgQqKKN{6jjOkZ!xLc3& zgXZ%z2RL43z0C`aR1VR9oBg6i(avfl!SQo)myxz%q3BMvZw^n-7o_`)&a*ksMfvg@ zJjDbI%MLEV4u=UJG90nWNlTZlRC8wHVHUuus#ZR$fhpQ~j~Q>d2TzYgp$2Uy)Frjf z(+g2nqn2F!R?phIb;(~jMODW5OI?jU`!GC46urY;_kHs`5DqxQ)I$mU>FS_VO?=JF z3Uy*vvo3rg--%}mU9ib?>K975&eiy~=gNq9<}E$H8p-yM=BUX{)WB`rky|MmuXZ%H(jks>?lqE!atX+ir_0Os?y&DM-AvC zMV(I-no5flRQdXLH-LAbbzMdVpZn~;JzX&nyhoeUad4afGt#Ss8%5nXg1r-S#r+KpYsYBp+lgOM;6`~fwiTt>(v>WHnyZEq}+ zDJ$^+I9w?`%P|4lYhmgpTjUtcb>NqB+JkbZjz(XFHUxh%sEz6nzK?($mNxjTq_Nm6 zZpeI=X>2-HI||!K-4||ZM$M28k|8<`!L3{7eQaucl`lTeb$K8ilk!xY6BU(rTxQd# zk;%~ZtW}6?8K5PTaNLrW;kAu=l*>Qp0TB-9+k8lk_vhs#7Yk}GQL+|(!d*|+_@!V@ z?E|321W~35&Z{}!AyHU39tm9g3biXacCd*C-sO=aB5phBPCFlZb7km5YpR(S?yf6G z^92|O0+cdyJ5tl=Yr1uqWT<&{p!}Mc}Z01=cQkT~Y^zG4WRG8#&PE+sXZnw68F* zJyj!wPw)D-OXc=}w-Y{tw*$zPr0u;bNGo!|&Q5VJ2rjSs0%}A>*pS~Z)A{iRj(Uh! zr-2y?nQK~m>PB@K!)dqP0cMc)TLWvP1R_Q!7QB$BkR6n5`AQala(sm^MD7yM7@r?y z#iTZ>{1%+paVLR5d#(E9y=ItCh&JWz58KD~~1;BmB?w*De9op>cq%EG`3G_HLQUM}i_ z#x<|~y)Ku`9e5xOQ(UuxQwS_tTUN$~Q1oftu&%mVTbu9uFSy=wwT>$Rh+~R62 zMrlpbsMbpF@Q{Z&4bwv^sJ*{z@v?rf%xmIHUzP*?TzPg@GL!CY0tP(%kk#xUTl=L% zKv`&BA#r08ROG9iN8Y8ey6;D{^Mkk-#TZk`9!VFsG3@gtqY&GlF&k4(ltI>OcKIYh zCAm0KVs^AbD_7Zn3#!?b_G9fXmcg*#skQCT(bsSg$XCF|ig@-_o&U+JTt&RMcR{T* zMP zDJ&B7X>S8Dc&fQDvt@3x7Z{OYQ}{B&>U}RZ`7E>c~(LxE~MA2@AaEIE=M= zF0qc`zQiNT0pW%hrGCFmNEjLwKPw}CuBT+LB2WDS{wDu^s-IF5r z234oc%WkrLoOQ@#$ohTO>pb7J9iAW_TzQj^4QeLK(PXA3;Zu`hq8c_{KZN{8(n6Yc zQAdy-s_E3mthMsk$VCTMP5>Raqm$J1{UJXq_R&LqkYRfp`h#vU-%e@@TRCZowqxAuX!8@FggW&?$h39a{sdc*ocqj(X=Jq^@>7Kn*H%yc1%sL| z*`h|g$$l=TiC%GNo$xjPd`*BYDnvo_4}PzL;X^0m65C!1Y%0zp`Tk~Wa#5=+9lL@v zahsJ)PAe&-U0t^#nOMClp6ks7P@r6im8XCAd(391Wm)^@7{lMBJwa>I_DbGj=XDPr ztRAwhWep)Bg;tiO)`3cJb2r+TF8MM0F=izI{OQREtDCz2<5y$hvKgiDt`fSl#M}t< z7|qa!M^)__f^F3d^*Ge~Zkh_NJanLB=m4WlY<`TpcXV2-J83NW zx%^Qz6_W8$e@2|#r#b#XeYa=rqPFWO)GWR7Fde{VDB^(f#_9{vVcCcs^D&+co!fXZ zSkJYg#-3F*90v7hg|cvHuFft?P`B+WFTjSUQs`gT5CYTa!n!OGxvq~KcCYKHaS;=xob-ryCH&Ocosb_gc8De^Yd@}~Ygr(!8-r_=Zdp&cbOOth1&oocSW5GQp{(95ts zQmuAzy}#mKVFj3ofW=Tmmhj7C48P2m%gTZA7Pm`VwPJVf%-XTmE350SiV6c$@#`5T zYtY+Q^)rx!!{r27!@muk{N{3MU04gcELH@KQdX+?rKYU0Gq?5BjsA5sv{*3)%qr6! zJl)OfVZz@@#EJyab(rR94^Z}6dF)5Hd&?0I;`7j>3!qR{0=2Rl2@3RF=gy$htC~1% zftopUr$%j8L-01}yg5t63!?e{xYsqU$Bb@8G7;f5Vv=jHBGmBGF%Ejh1`1F7t;Am) z?Le92_*bL|c-7KcSXYiAVoD1_mWaq=+{3O4gF$Z`P8GWq#Qn0aq5 zPtlmi9bjxflI-d2?KWBLVJZyFx3*Ed+Wz%Bd$a65Lg%5?LAQFf&kB06s|2+4+ub}^ zFnhV*V_gF_FZO?BGygH#^*0-TA9P~L`e{IsV8HRD{8RWoV!eaU8m$E6v*%ke#d}WB z_*$Ruq2J5;Jv1+Yt=vHd9p3BNv}%Ny4ddSLo(-ocVT`~xO#)2)∨&jm3(R$;JLz z+8RuSR6phN)7t5Ocn|U6Mo5Nq!L_J3p4_cF5C$iIg7V9+A?{qYKySgY?1>S{=*Tg8 z*1D92rGHhSp1OQe4Sh{@VR^?MrsgXoiLh z9fbA#Z=`tjrkLvO+$rP(h8-Oq{($uCF}R~!ZH=HntDlOMUp;PJdWh?f?e`h$JP7eV zF->qk0>rBuEe*hP3m6SXOlRT{^l{eB0qrEh1LqK%~WiF|KV`!=VQ>CbPEB( zmG$Jgn8)m71ov88Rw|sfury7@`L5Gw(CokuVRiXyZS!nm$>ZhE?EFV_nt?tvw^#NU zdJzB;mD=NnLQeM4N#1L@ehVCp-e1yMEgzSaU0LGV?e|(!`@X#I8fj|=?ItcgYxi=h zL>2-m&j9_a$wvyV?2hxQOiDTFHvLCpsG8cXS1+P#uRt@FD3hB;#R4$amR!yO%>cDu zBS*?BSzp|ZyhzoAGHCQ|K@0&VkTX{vx#`ZCn%-W?3lTp!w#)Y2u3;p-%56PvRMqq^ z3(S+;= zjd zSvc~O*rxKmn|U8%E*{~J7Ptx-|{ z)dzv6F2Pb7$jaZ8K^el?;496X1XSn!@Md0g(^fgQp3=+vAdpzDhS$XN&6R7HGL!d#=VZ{F0o5zm1+A;llKvwzH^aAQ~Jw) zgU(>gA(Rg~vG5kHn`ym?6FUzDO#XHY17L+_(-;l!2?r|H&XcPHG%rjcrR&xycdje| z5Uy`ELW{L`H<-#=UYdS9c+OA6ARp_;z<`L zXjWSwkk;P~0A2*f{LYpcu+G(Eta2Jww%oaUmh52)&mXO$Ukm83V{(=fsY>``$CXBU zO8mP0>;i?Z!)w3bHJBF$Sr!;z11)wGi}hG2)V`w$k#myz3Ti;OUEeaLOK z5b`trt6`2m)i}i6kdIPLm=uDUkjxyB(X)(^RE5znw;xzbg%qjp60=x@q_GOHt;7QjANVMLKI1YyqW-nz8>GUV9 zl_m@3nCrGoX)IpyTqShfn3Xy=8UkiMgP71+gL=vNiT#-mi6TzL`*2W*@+QzHF}Su* zLXhOPQb5n|x0v+Xp%j#xun}o+e66h@FQeIe9)NMa%J95?b!4%9&v zv=7H3{a|T5yVJO_w^uXo_xKax(-s-(Z`&DTkve%~HsinvwCHtJM~E<5=qQ4cz2}pAJ~WN` zP5bxRSzPN!wtn&nUXNn1%>qo-!DkMdhd~&g2^jlS+F12fGzVujfVMOZtc0!=*kx%1 z#(3FEb56XO|H|ffh?jS66R4^{ARMPW z!|aav{WE+3%}dk78*4HLo&NE`gTDjB=`396yFZ2Q+Xn9mTlu5>_mrv}ud;NhVznzs z$wYJrDs?2UpZAnJ`56bv@h->wzzl5y)IcL>kE&G0*>+I)A&`!Twv+$z*@>U1z<;@? ze>=%a?)}ed_5TX?V0tUM6c*9e)?Ub$bCBlOZqL@-$iL3Ys;_410KC>~7Zitkm0Xxr zk1wM}-i*8wDJTCqiW^}desWFN)6BIR_1^gbsg>vQa!Kh@R^)K$(xV}(*R9;lwsPZv z$g}8S!a#oF#*q|kx~Z?~NLQi_U&fJ8-vW=3_3@D0O1vFSK(@Mo{EDQODaGr)+w_K3 zMaNV5a+Cww`94uC@!>|6gQyU9@tzqDlaPu&yN<2v-fO!0UVw1%cwKSzs?3iY!fhkk zT}vnSMrz*4<|Hu^v@O;dkd@4vj1AFHcVRMJ(CUfB#QNN96%xCy2{4I$@9Qjivd_^F z@1+Ov>mqUVj$b%dsAfR3a8DM_t$P5VDvH6+)v7VNYG=HUe;U4vJR`xbF%)iNbPMwZ zZ@SWGv*L|R;VV>Q#_1<~R5gZMo}_-@a~xF}ymHCwq*TR_>CHFT4DGdARBv@o}_Bu+zI95~EV%fFp0j*t4iT^nv`hQq{73w}+U9zG-8E}|e z{d1=O@v8Q@K++OuLa&yK8E=%eHyi!@qdU6FT=kVC&!s1U8JGxwz{Dr^j4>Yr27zq5 zy<6{Jt;YYZuKm{#<9~@nFbhUIl?26QxFLgeH3N3>kCdl%G`^+?S4S{}k>^b{eAf!; zr$jo6xzV29#xCHnmD!9JJiXoKvUoUkHqH&paIyz$nXqqZY{L< z6XI5uDQ$gOE@1_i8O=V^;d#^Hu5sMdwF|t$p<&2%!3`0yVjA4?s<27O<8+c%C`pHr zZ0#nwmrRbL#oVT>Ta${ZT+|N4xlxe}{k%vum8lk;%`p$JiR=&0 zN}sTy_Ee^9&x*HOqT~A31auUZ2FapP3aG)Dy@D~nnj)`Gr}kddVniP_iuHO7F+4*E z;!}QUhu;CsE62!st_zaoSS=1>Ak1&vZY<>h-(&z$yvB<$BF#W>)}W=ejC`#;1wZ z4VjfBTb6;;ZK`dY-y1pbNlWChL`++uY@fksCTYu&^0|z($WL_o+!`~&F3gP4wFsqE zSv0F~M#?`eTy35e2DtE8>^cddGj;JPgl)QJwWv@>qeVC0FmdlM6(Vm(= z`xt&&c(k^+iVx)?c=tch^hP3Rh@j@OftdGWw+0-jRI}XDt>gKRW$Z7|SRj5RAJ>1G zy=8td=%1Zd|C28fxk7F! zPIQdFUB-PE6b6-jX(=C+GZ(25+t!WL8ZablMk^)WQ%gYS8PtoGuql3ZRPg7-;C4s7 zULR*<;@SeFwNd>Z=8+J`z>8{JNJI)SY)2ECIXzmL&_2#;)ALY=ByS z7^~fyjyy0}AM-F&t*YNBsoAGc)hk&EW1dwm3v|Bx#4(GWJA)HHDKP*!a4l2ZSn#FjMMW)CPDcB@nvl~^i$Pd zW1lV<2cJ4fa-*0@E*cUk5%OrKgkLnOq4k|)*%da(+smTpjXH!FY3kZUYB>WqvJ$(l zL-#<9BnZUv|L_g!|G$2K>_Q@g;O#91k6B}PnV$bB$PK=()X<><3r5n64HN~B{b~@1 c)C~wo*7Hm?mBX)Mfx<&9&27zYnYdj1ALA0CcK`qY literal 0 HcmV?d00001 diff --git a/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.cpp b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.cpp new file mode 100644 index 0000000..e5924d4 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.cpp @@ -0,0 +1,119 @@ +/* + Capstone Disassembly Engine bindings for VB6 + Contributed by FireEye FLARE Team + Author: David Zimmer , + License: Apache + Copyright: FireEye 2017 + + This dll is a small stdcall shim so VB6 can access the capstone API +*/ + +#include +#include +#include + +#include +#pragma comment(lib, "capstone.lib") + +#define EXPORT comment(linker, "/EXPORT:"__FUNCTION__"="__FUNCDNAME__) + +unsigned int __stdcall bs_version(int *major, int *minor){ +#pragma EXPORT + return cs_version(major,minor); +} + +bool __stdcall bs_support(int query){ +#pragma EXPORT + return cs_support(query); +} + +cs_err __stdcall bs_open(cs_arch arch, cs_mode mode, csh *handle){ +#pragma EXPORT + return cs_open(arch, mode, handle); +} + +cs_err __stdcall bs_close(csh *handle){ +#pragma EXPORT + return cs_close(handle); +} + +cs_err __stdcall bs_option(csh handle, cs_opt_type type, size_t value){ +#pragma EXPORT + return cs_option(handle, type, value); +} + +cs_err __stdcall bs_errno(csh handle){ +#pragma EXPORT + return cs_errno(handle); +} + +const char* __stdcall bs_strerror(cs_err code){ +#pragma EXPORT + return cs_strerror(code); +} + +size_t __stdcall bs_disasm(csh handle, const uint8_t *code, size_t code_size, uint64_t address, size_t count, cs_insn **insn){ +#pragma EXPORT + return cs_disasm(handle, code, code_size, address, count, insn); +} + +void __stdcall getInstruction(cs_insn *insn, uint32_t index, void* curInst, uint32_t bufSize){ +#pragma EXPORT + memcpy(curInst, (void*)&insn[index], bufSize); //size lets us get a partial version of whatever we have implemented in the vbstruct... +} + +const char* __stdcall bs_reg_name(csh handle, unsigned int reg_id){ +#pragma EXPORT + return cs_reg_name(handle, reg_id); +} + +void __stdcall bs_free(cs_insn *insn, size_t count){ +#pragma EXPORT + return cs_free(insn, count); +} + +cs_insn* __stdcall bs_malloc(csh handle){ +#pragma EXPORT + return cs_malloc(handle); +} + + +int __stdcall bs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, unsigned int position){ +#pragma EXPORT + return cs_op_index(handle,insn,op_type,position); +} + +int __stdcall bs_op_count(csh handle, const cs_insn *insn, unsigned int op_type){ +#pragma EXPORT + return cs_op_count(handle,insn,op_type); +} + +bool __stdcall bs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id){ +#pragma EXPORT + return cs_reg_write(handle,insn,reg_id); +} + +bool __stdcall bs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id){ +#pragma EXPORT + return cs_reg_read(handle,insn,reg_id); +} + +bool __stdcall bs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id){ +#pragma EXPORT + return cs_insn_group(handle,insn,group_id); +} + +const char* __stdcall bcs_group_name(csh handle, unsigned int group_id){ +#pragma EXPORT + return cs_group_name(handle,group_id); +} + +const char* __stdcall bs_insn_name(csh handle, unsigned int insn_id){ +#pragma EXPORT + return cs_insn_name(handle,insn_id); +} + +bool __stdcall bs_disasm_iter(csh handle, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn){ +#pragma EXPORT + return cs_disasm_iter(handle, code, size, address, insn); +} diff --git a/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.sln b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.sln new file mode 100644 index 0000000..0ed4f7e --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.sln @@ -0,0 +1,20 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 10.00 +# Visual Studio 2008 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "vbCapstone", "vbCapstone.vcproj", "{B693CA7B-8B91-4413-AAED-14F1947F012A}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.ActiveCfg = Debug|Win32 + {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.Build.0 = Debug|Win32 + {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.ActiveCfg = Release|Win32 + {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.vcproj b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.vcproj new file mode 100644 index 0000000..b929c21 --- /dev/null +++ b/white_patch_detect/capstone-master/bindings/vb6/vbCapstone.vcproj @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/white_patch_detect/capstone-master/capstone.pc.in b/white_patch_detect/capstone-master/capstone.pc.in new file mode 100644 index 0000000..b8ea3d3 --- /dev/null +++ b/white_patch_detect/capstone-master/capstone.pc.in @@ -0,0 +1,12 @@ +prefix=@CMAKE_INSTALL_PREFIX@ +exec_prefix=${prefix} +libdir=${prefix}/@CMAKE_INSTALL_LIBDIR@ +includedir=${prefix}/include/capstone + +Name: capstone +Description: Capstone disassembly engine +Version: @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@ +URL: http://www.capstone-engine.org +archive=${libdir}/libcapstone.a +Libs: -L${libdir} -lcapstone +Cflags: -I${includedir} diff --git a/white_patch_detect/capstone-master/cmake.sh b/white_patch_detect/capstone-master/cmake.sh new file mode 100644 index 0000000..e5af540 --- /dev/null +++ b/white_patch_detect/capstone-master/cmake.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# Capstone disassembler engine (www.capstone-engine.org) +# Build Capstone libs for specified architecture, or all if none is specified (libcapstone.so & libcapstone.a) on *nix with CMake & make +# By Nguyen Anh Quynh, Jorn Vernee, 2019 + +FLAGS="-DCMAKE_BUILD_TYPE=Release" +# Uncomment below line to compile in Diet mode +# FLAGS+=" -DCAPSTONE_BUILD_DIET=ON" + +case $1 in + ARM) + ARCH=ARM + ;; + ARM64) + ARCH=ARM64 + ;; + M68K) + ARCH=M68K + ;; + MIPS) + ARCH=MIPS + ;; + PowerPC) + ARCH=PPC + ;; + Sparc) + ARCH=SPARC + ;; + SystemZ) + ARCH=SYSZ + ;; + XCore) + ARCH=XCORE + ;; + x86) + ARCH=X86 + ;; + TMS320C64x) + ARCH=TMS320C64X + ;; + M680x) + ARCH=M680X + ;; + EVM) + ARCH=EVM + ;; + MOS65XX) + ARCH=MOS65XX + ;; + *) + ;; +esac + +if [ "x${ARCH}" = "x" ]; then + FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=ON" +else + FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_${ARCH}_SUPPORT=ON" +fi + +cmake $FLAGS .. + +make -j8 diff --git a/white_patch_detect/capstone-master/config.mk b/white_patch_detect/capstone-master/config.mk new file mode 100644 index 0000000..afbd095 --- /dev/null +++ b/white_patch_detect/capstone-master/config.mk @@ -0,0 +1,82 @@ +# This file contains all customized compile options for Capstone. +# Consult COMPILE.TXT & docs/README for details. + +################################################################################ +# Specify which archs you want to compile in. By default, we build all archs. + +CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm mos65xx + + +################################################################################ +# Comment out the line below ('CAPSTONE_USE_SYS_DYN_MEM = yes'), or change it to +# 'CAPSTONE_USE_SYS_DYN_MEM = no' if do NOT use malloc/calloc/realloc/free/ +# vsnprintf() provided by system for internal dynamic memory management. +# +# NOTE: in that case, specify your own malloc/calloc/realloc/free/vsnprintf() +# functions in your program via API cs_option(), using CS_OPT_MEM option type. + +CAPSTONE_USE_SYS_DYN_MEM ?= yes + + +################################################################################ +# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library +# more compact: use less memory & smaller in binary size. +# This setup will remove the @mnemonic & @op_str data, plus semantic information +# such as @regs_read/write & @group. The amount of binary size reduced is +# up to 50% in some individual archs. +# +# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read, +# @regs_write, @groups, etc in fields in cs_insn structure regardless, but they +# will not be updated (i.e empty), thus become irrelevant. + +CAPSTONE_DIET ?= no + + +################################################################################ +# Change 'CAPSTONE_X86_REDUCE = no' to 'CAPSTONE_X86_REDUCE = yes' to remove +# non-critical instruction sets of X86, making the binary size smaller by ~60%. +# This is desired in special cases, such as OS kernel, where these kind of +# instructions are not used. +# +# The list of instruction sets to be removed includes: +# - Floating Point Unit (FPU) +# - MultiMedia eXtension (MMX) +# - Streaming SIMD Extensions (SSE) +# - 3DNow +# - Advanced Vector Extensions (AVX) +# - Fused Multiply Add Operations (FMA) +# - eXtended Operations (XOP) +# - Transactional Synchronization Extensions (TSX) +# +# Due to this removal, the related instructions are nolonger supported. +# +# By default, Capstone is compiled with 'CAPSTONE_X86_REDUCE = no', +# thus supports complete X86 instructions. + +CAPSTONE_X86_REDUCE ?= no + +################################################################################ +# Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to +# disable AT&T syntax on x86 to reduce library size. + +CAPSTONE_X86_ATT_DISABLE ?= no + +################################################################################ +# Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building +# a static library. + +CAPSTONE_STATIC ?= yes + + +################################################################################ +# Change 'CAPSTONE_SHARED = yes' to 'CAPSTONE_SHARED = no' to avoid building +# a shared library. + +CAPSTONE_SHARED ?= yes + +################################################################################ +# Change 'CAPSTONE_HAS_OSXKERNEL = no' to 'CAPSTONE_HAS_OSXKERNEL = yes' to +# enable OS X kernel embedding support. If 'CAPSTONE_USE_SYS_DYN_MEM = yes', +# then kern_os_* functions are used for memory management. + +CAPSTONE_HAS_OSXKERNEL ?= no diff --git a/white_patch_detect/capstone-master/contrib/README b/white_patch_detect/capstone-master/contrib/README new file mode 100644 index 0000000..e29823d --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/README @@ -0,0 +1,5 @@ +This directory contains contributions that do not belong to the core engine. +Code here might be helpful for those who want to integrate Capstone into +their own projects. + +The license of these code was defined by their authors. diff --git a/white_patch_detect/capstone-master/contrib/cs_driver/README b/white_patch_detect/capstone-master/contrib/cs_driver/README new file mode 100644 index 0000000..f9a268a --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/cs_driver/README @@ -0,0 +1,5 @@ +This directory contains a sample project for using Capstone from a Windows +driver. Open cs_driver.sln with Visual Studio 2013 or newer and see cs_driver.c +for details. + +For prerequisites to compile Capstone for drivers, see COMPILE_MSVC.TXT. diff --git a/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver.sln b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver.sln new file mode 100644 index 0000000..f36afa1 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver.sln @@ -0,0 +1,49 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 2013 +VisualStudioVersion = 12.0.40629.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "cs_driver", "cs_driver\cs_driver.vcxproj", "{F29A9424-0ECD-4FFE-9CB7-C844756373BB}" + ProjectSection(ProjectDependencies) = postProject + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B} = {FE197816-EF84-4E8D-B29D-E0A6BA2B144B} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "capstone_static_winkernel", "..\..\msvc\capstone_static_winkernel\capstone_static_winkernel.vcxproj", "{FE197816-EF84-4E8D-B29D-E0A6BA2B144B}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|Win32.ActiveCfg = Debug|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|Win32.Build.0 = Debug|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|Win32.Deploy.0 = Debug|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|x64.ActiveCfg = Debug|x64 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|x64.Build.0 = Debug|x64 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Debug|x64.Deploy.0 = Debug|x64 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|Win32.ActiveCfg = Release|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|Win32.Build.0 = Release|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|Win32.Deploy.0 = Release|Win32 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|x64.ActiveCfg = Release|x64 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|x64.Build.0 = Release|x64 + {F29A9424-0ECD-4FFE-9CB7-C844756373BB}.Release|x64.Deploy.0 = Release|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|Win32.ActiveCfg = Debug|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|Win32.Build.0 = Debug|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|Win32.Deploy.0 = Debug|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|x64.ActiveCfg = Debug|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|x64.Build.0 = Debug|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|x64.Deploy.0 = Debug|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|Win32.ActiveCfg = Release|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|Win32.Build.0 = Release|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|Win32.Deploy.0 = Release|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|x64.ActiveCfg = Release|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|x64.Build.0 = Release|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|x64.Deploy.0 = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.c b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.c new file mode 100644 index 0000000..99a1f12 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.c @@ -0,0 +1,99 @@ +/* Capstone Driver */ +/* By Satoshi Tanda , 2016 */ + +// Firstly, compile capstone_static_winkernel and +// generate capstone_static_winkernel.lib. It can be done by adding the +// capstone_static_winkernel project to your solution and compiling it first. +// +// Then, configure your driver project (cs_driver in this example) to locate to +// capstone.h and capstone_static_winkernel.lib. To do it, open project +// properties of the project and set Configuration to "All Configurations" and +// Platform to "All Platforms". Then, add the following entries: +// - C/C++ > General > Additional Include Directories +// - $(SolutionDir)capstone\include +// - Linker > Input > Additional Dependencies +// - $(OutDir)capstone_static_winkernel.lib +// - ntstrsafe.lib +// +// Note that ntstrsafe.lib is required to resolve __fltused indirectly used in +// Capstone. + +#include +#include + +// 'conversion' : from function pointer 'type1' to data pointer 'type2' +#pragma warning(disable : 4054) + + +DRIVER_INITIALIZE DriverEntry; +static NTSTATUS cs_driver_hello(); + + +// Driver entry point +EXTERN_C NTSTATUS DriverEntry(PDRIVER_OBJECT DriverObject, + PUNICODE_STRING RegistryPath) { + printf("Entering DriverEntry()\n"); + + cs_driver_hello(); + + printf("Leaving DriverEntry()\n"); + return STATUS_CANCELLED; +} + +// Hello, Capstone! +static NTSTATUS cs_driver_hello() { + csh handle; + cs_insn *insn; + size_t count; + KFLOATING_SAVE float_save; + NTSTATUS status = STATUS_UNSUCCESSFUL; + + // Any of Capstone APIs cannot be called at IRQL higher than DISPATCH_LEVEL + // since our malloc implementation based on ExAllocatePoolWithTag() is not able + // to allocate memory at higher IRQL than the DISPATCH_LEVEL level. + NT_ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL); + + // On a 32bit driver, KeSaveFloatingPointState() is required before using any + // Capstone function because Capstone can access to the MMX/x87 registers and + // 32bit Windows requires drivers to use KeSaveFloatingPointState() before and + // KeRestoreFloatingPointState() after accessing them. See "Using Floating + // Point or MMX in a WDM Driver" on MSDN for more details. + status = KeSaveFloatingPointState(&float_save); + if (!NT_SUCCESS(status)) { + return status; + } + + // Do stuff just like user-mode. All functionalities are supported. + if (cs_open(CS_ARCH_X86, (sizeof(void *) == 4) ? CS_MODE_32 : CS_MODE_64, + &handle) != CS_ERR_OK) { + goto exit; + } + + count = cs_disasm(handle, (uint8_t *)&cs_driver_hello, 0x80, + (uint64_t)&cs_driver_hello, 0, &insn); + if (count > 0) { + printf("cs_driver!cs_driver_hello:\n"); + for (size_t j = 0; j < count; j++) { + printf("0x%p\t%s\t\t%s\n", (void *)(uintptr_t)insn[j].address, + insn[j].mnemonic, insn[j].op_str); + } + cs_free(insn, count); + } + cs_close(&handle); + +exit:; + // Restores the nonvolatile floating-point context. + KeRestoreFloatingPointState(&float_save); + return status; +} + +// printf() +_Use_decl_annotations_ int __cdecl printf(const char *_Format, ...) { + NTSTATUS status; + va_list args; + + va_start(args, _Format); + status = vDbgPrintEx(DPFLTR_DEFAULT_ID, DPFLTR_ERROR_LEVEL, _Format, args); + va_end(args); + return NT_SUCCESS(status); +} diff --git a/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj new file mode 100644 index 0000000..623040c --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj @@ -0,0 +1,129 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {F29A9424-0ECD-4FFE-9CB7-C844756373BB} + {1bc93793-694f-48fe-9372-81e2b05556fd} + v4.5 + 11.0 + Win8.1 Debug + Win32 + cs_driver + + + + Windows7 + true + WindowsKernelModeDriver8.1 + Driver + KMDF + + + Windows7 + false + WindowsKernelModeDriver8.1 + Driver + KMDF + + + Windows7 + true + WindowsKernelModeDriver8.1 + Driver + KMDF + + + Windows7 + false + WindowsKernelModeDriver8.1 + Driver + KMDF + + + + + + + + + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + + trace.h + true + $(SolutionDir)..\..\include;$(IntDir);%(AdditionalIncludeDirectories) + + + $(OutDir)capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + + + + + trace.h + true + $(SolutionDir)..\..\include;$(IntDir);%(AdditionalIncludeDirectories) + + + $(OutDir)capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + + + + + trace.h + true + $(SolutionDir)..\..\include;$(IntDir);%(AdditionalIncludeDirectories) + + + $(OutDir)capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + + + + + trace.h + true + $(SolutionDir)..\..\include;$(IntDir);%(AdditionalIncludeDirectories) + + + $(OutDir)capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + + + + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters new file mode 100644 index 0000000..2949111 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters @@ -0,0 +1,26 @@ +锘 + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + {8E41214B-6785-4CFE-B992-037D68949A14} + inf;inv;inx;mof;mc; + + + + + Source Files + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/contrib/objdump/objdump-m68k.py b/white_patch_detect/capstone-master/contrib/objdump/objdump-m68k.py new file mode 100644 index 0000000..3454de3 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/objdump/objdump-m68k.py @@ -0,0 +1,426 @@ +#!/usr/bin/env python + +from __future__ import print_function +import sys +import bitstring +from capstone import * +from capstone.m68k import * + +# +# Objdump with the same output as his binary cousin +# + +TODO = """ +TODO : + + o need more testing on M68K_AM_*_DISP + o cleanup, etc ... + +""" + +objdump_cmd_example = 'm68k-atari-mint-objdump -b binary -D -mm68k --adjust-vma 0x30664 u/m68k.bin' +objdump_dumpheader_fmt = """ +%s: file format binary + + +Disassembly of section .data: + +%08x <.data>:""" + + +M68000_CODE = b"\x04\x40\x00\x40" + +all_tests = ( + (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_060, M68000_CODE, "M68060-32 (Big-endian)"), +) + + +def dump_bytes(b, len): + str = '' + i = 0 + while i < len: + str += format("%02x%02x " % (b[i], b[i+1])) + i += 2 + return str[:-1] + +def dump_op_reg(insn, op_reg): + if op_reg == M68K_REG_A7: + return "%sp" + if op_reg == M68K_REG_A6: + return "%fp" + return '%' + insn.reg_name(op_reg) + +def s8(value): + return bitstring.Bits(uint=value, length=8).unpack('int')[0] + +def s16(value): + return bitstring.Bits(uint=value, length=16).unpack('int')[0] + +def extsign8(value): + if value & 0x80: + return 0xffffffffffffff00 + value + return value + +def extsign1616(value): + if value & 0x8000: + return 0xffff0000 + value + return value + +def extsign1632(value): + if value & 0x8000: + return 0xffffffffffff0000 + value + return value + + +def printRegbitsRange(buffer, data, prefix): + str = '' + first = 0 + run_length = 0 + + i = 0 + while i < 8: + if (data & (1 << i)): + first = i + run_length = 0 + + while (i < 7 and (data & (1 << (i + 1)))): + i += 1 + run_length += 1 + + if len(buffer) or len(str): + str += "/" + + str += format("%%%s%d" % (prefix, first)) + if run_length > 0: + str += format("-%%%s%d" % (prefix, first + run_length)) + i += 1 + return str + +def registerBits(op): + str = '' + data = op.register_bits + + str += printRegbitsRange(str, data & 0xff, "d") + str += printRegbitsRange(str, (data >> 8) & 0xff, "a") + str += printRegbitsRange(str, (data >> 16) & 0xff, "fp") + return str + +def dump_op_ea(insn, op): + s_spacing = " " + map_index_size_str = { 0: 'w', 1 : 'l' } + str = '' + + if op.address_mode == M68K_AM_NONE: + if op.type == M68K_OP_REG_BITS: + return registerBits(op) + if op.type == M68K_OP_REG_PAIR: + return registerPair(op) + if op.type == M68K_OP_REG: + return dump_op_reg(insn, op.reg) + + if op.address_mode == M68K_AM_REG_DIRECT_DATA: + return dump_op_reg(insn, op.reg) + if op.address_mode == M68K_AM_REG_DIRECT_ADDR: + return dump_op_reg(insn, op.reg) + "@" + if op.address_mode == M68K_AM_REGI_ADDR: + return dump_op_reg(insn, op.reg) + "@" + if op.address_mode == M68K_AM_REGI_ADDR_POST_INC: + return dump_op_reg(insn, op.reg) + "@+" + if op.address_mode == M68K_AM_REGI_ADDR_PRE_DEC: + return dump_op_reg(insn, op.reg) + "@-" + if op.address_mode == M68K_AM_REGI_ADDR_DISP: +# str = dump_op_reg(insn, op.mem.base_reg - M68K_REG_A0 + 1) #double check and fixme '+1' : 02af 899f 2622 + str = dump_op_reg(insn, op.mem.base_reg) + if op.mem.disp: + str += format("@(%d)" % s16(op.mem.disp)) + return str + + if op.address_mode == M68K_AM_PCI_DISP: + return format("%%pc@(0x%x)" % ( extsign1616(op.mem.disp + 2))) + if op.address_mode == M68K_AM_ABSOLUTE_DATA_SHORT: + return format("0x%x" % (extsign1616(op.imm & 0xffff))) + if op.address_mode == M68K_AM_ABSOLUTE_DATA_LONG: + return format("0x%x" % (op.imm & 0xffffffff)) + if op.address_mode == M68K_AM_IMMEDIATE: + if insn.op_size.type == M68K_SIZE_TYPE_FPU: + map_fpu_size_str = { M68K_FPU_SIZE_SINGLE : op.simm, M68K_FPU_SIZE_DOUBLE : op.dimm } + return format("#%f" % (insn.op_size.fpu_size[map_fpu_size_str])) + return format("#$%x" % (op.imm)) + + if op.address_mode in [ M68K_AM_PCI_INDEX_8_BIT_DISP, M68K_AM_AREGI_INDEX_8_BIT_DISP ]: + disp = op.mem.disp + if op.register_bits == 2: + disp = extsign8(op.mem.disp) + if op.register_bits == 4: + disp = extsign1632(op.mem.disp) + + str = dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016x}".format(disp) + "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size] + if op.register_bits: + str += format(":%u" % (op.register_bits)) + return str + ")" + + + if op.address_mode in [ M68K_AM_PCI_INDEX_BASE_DISP, M68K_AM_AREGI_INDEX_BASE_DISP ]: + str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) )) + str += format("@(%016x)@(%016x" % (extsign1632(op.mem.in_disp), extsign1632(op.mem.out_disp))) + if op.mem.index_reg: + str += "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size] + if op.register_bits: + str += format(":%u" % (op.register_bits)) + str += ")" + return str + + if op.mem.in_disp > 0: + str += format("$%x" % ( op.mem.in_disp)) + + str += format("(") + + if op.address_mode == M68K_AM_PCI_INDEX_BASE_DISP: + str_size = '' + if op.mem.index_size: + str_size = "l" + else: + str_size = "w" + str += format("pc,%s%s.%s" % ( dump_op_reg(insn, op.mem.index_reg)), s_spacing, str_size) + else: + if op.mem.base_reg != M68K_REG_INVALID: + str += format("a%d,%s" % ( op.mem.base_reg - M68K_REG_A0, s_spacing)) + str_size = '' + if op.mem.index_size: + str_size = "l" + else: + str_size = "w" + str += format("%s.%s" % ( dump_op_reg(insn, op.mem.index_reg), str_size)) + + if op.mem.scale > 0: + str += format("%s*%s%d)" % ( s_spacing, s_spacing, op.mem.scale)) + else: + str += ")" + return str + + # It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. + # While this is not strictly correct it makes the code + # easier and that is what actually happens when the code is executed anyway. + + if op.address_mode in [ M68K_AM_PC_MEMI_POST_INDEX, M68K_AM_PC_MEMI_PRE_INDEX, M68K_AM_MEMI_PRE_INDEX, M68K_AM_MEMI_POST_INDEX]: + if op.mem.base_reg: + str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) )) + if op.mem.in_disp: + value = op.mem.in_disp + if op.mem.in_disp & 0x8000: + value = 0xffffffffffff0000 + op.mem.in_disp + str += format("@(%016x)@(%016x)" % (value, op.mem.out_disp)) + return str + + str += format("([") + if op.mem.in_disp > 0: + str += format("$%x" % ( op.mem.in_disp)) + + if op.mem.base_reg != M68K_REG_INVALID: + if op.mem.in_disp > 0: + str += format(",%s%s" % ( s_spacing, dump_op_reg(insn, op.mem.base_reg))) + else: + str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg))) + + if op.address_mode in [ M68K_AM_MEMI_POST_INDEX, M68K_AM_PC_MEMI_POST_INDEX]: + str += format("]") + + if op.mem.index_reg != M68K_REG_INVALID: + str_size = '' + if op.mem.index_size: + str_size = "l" + else: + str_size = "w" + str += format(",%s%s.%s" % ( s_spacing, dump_op_reg(insn, op.mem.index_reg), str_size)) + if op.mem.scale > 0: + str += format("%s*%s%d" % ( s_spacing, s_spacing, op.mem.scale)) + if op.address_mode in [ M68K_AM_MEMI_PRE_INDEX, M68K_AM_PC_MEMI_PRE_INDEX]: + str += format("]") + if op.mem.out_disp > 0: + str += format(",%s$%x" % ( s_spacing, op.mem.out_disp)) + str += format(")") + return str + + + if op.mem.bitfield: + return format("%d:%d" % ( op.mem.offset, op.mem.width)) + + ############# OK + if op.address_mode == M68K_AM_AREGI_INDEX_BASE_DISP: + if op.mem.index_size: + str_size = "l" + else: + str_size = "w" + bits = op.mem.disp + return dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016b}".format(bits) + "," + dump_op_reg(insn, op.mem.index_reg) + ":" + str_size + ")" + return '' + + + +# M68K Addressing Modes + +map_address_mode_str = { + 0 : "M68K_AM_NONE", + 1 : "M68K_AM_REG_DIRECT_DATA", + 2 : "M68K_AM_REG_DIRECT_ADDR", + 3 : "M68K_AM_REGI_ADDR", + 4 : "M68K_AM_REGI_ADDR_POST_INC", + 5 : "M68K_AM_REGI_ADDR_PRE_DEC", + 6 : "M68K_AM_REGI_ADDR_DISP", + 7 : "M68K_AM_AREGI_INDEX_8_BIT_DISP", + 8 : "M68K_AM_AREGI_INDEX_BASE_DISP", + 9 : "M68K_AM_MEMI_POST_INDEX", + 10 : "M68K_AM_MEMI_PRE_INDEX", + 11 : "M68K_AM_PCI_DISP", + 12 : "M68K_AM_PCI_INDEX_8_BIT_DISP", + 13 : "M68K_AM_PCI_INDEX_BASE_DISP", + 14 : "M68K_AM_PC_MEMI_POST_INDEX", + 15 : "M68K_AM_PC_MEMI_PRE_INDEX", + 16 : "M68K_AM_ABSOLUTE_DATA_SHORT", + 17 : "M68K_AM_ABSOLUTE_DATA_LONG", + 18 : "M68K_AM_IMMEDIATE", + } + + +# Operand type for instruction's operands + +map_op_str = { + 0 : "M68K_OP_INVALID", + 1 : "M68K_OP_REG", + 2 : "M68K_OP_IMM", + 3 : "M68K_OP_MEM", + 4 : "M68K_OP_FP", + 5 : "M68K_OP_REG_BITS", + 6 : "M68K_OP_REG_PAIR", +} + + +def debug(insn, op): + if len(sys.argv) > 3: + print("id %d type %s address_mode %s" % (insn.id, map_op_str[op.type], map_address_mode_str[op.address_mode])) + + +def dump_ops(insn): + str = '' + mnemonic = insn.insn_name() + + i = 0 + while i < len(insn.operands): + if i > 0: + str += ',' + op = insn.operands[i] + debug(insn, op) + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == M68K_INS_INVALID: + return format("0x%04x" % (op.imm)) + if op.type == M68K_OP_REG: + str_op_reg = dump_op_ea(insn, op) + if str_op_reg == '' or op.address_mode == M68K_AM_REG_DIRECT_ADDR: + str_op_reg = dump_op_reg(insn, op.reg) + str += str_op_reg + if op.type == M68K_OP_IMM: + str_op_imm = format("#%u" % (op.imm)) + if mnemonic in ["bkpt"]: + str_op_imm = format("%u" % (op.imm)) + signed_insn = [ "move", "moveq", "cmp", "cmpi", "ori", "bclr", "pack", "unpk", "sub", "add" ] + if mnemonic in signed_insn: + if insn.op_size.size == 1 or mnemonic == "moveq": + str_op_imm = format("#%d" % s8(op.imm)) + if insn.op_size.size == 2 or mnemonic == "pack": + str_op_imm = format("#%d" % s16(op.imm)) + if insn.op_size.size == 4: + str_op_imm = format("#%d" % (op.imm)) + + dbxx_insn = [ "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra" ] + if is_branch(insn) or mnemonic in dbxx_insn: + str_op_imm = format("0x%x" % (op.imm & 0xffffffff)) + str += str_op_imm + if op.type == M68K_OP_MEM: + str_op_mem = dump_op_ea(insn, op) + if str_op_mem == '': + str_op_mem = format("0x%x" % (op.imm)) + str += str_op_mem + if op.type in [ M68K_OP_REG_BITS, M68K_OP_REG_PAIR ]: + str += dump_op_ea(insn, op) + +# if insn.address == 0x3127c: +# import pdb;pdb.set_trace() +# print("type %u am %u\n" % (op.type, op.address_mode)) + i += 1 + return str + + +def is_branch(insn): + mnemonic = insn.insn_name() + branch_insn = [ "bsr", "bra", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble" ]; + return mnemonic in branch_insn + +def dump_mnemonic(insn): + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == M68K_INS_INVALID: + return ".short" + mnemonic = insn.insn_name() + ext = { 0: '', 1:'b', 2:'w', 4:'l' } + if is_branch(insn): + ext.update({ 1:'s', 2:'w', 4:'l' }) + + no_size = [ "pea", "lea", "bset", "bclr", "bchg", "btst", "nbcd", "abcd", "sbcd", "exg", "scc", "sls", "scs", "shi" ] + sxx_insn = [ "st", "sf", "shi", "sls", "scc", "scs", "sne", "seq", "svc", "svs", "spl", "smi", "sge", "slt", "sgt", "sle", "stop" ] + no_size += sxx_insn + no_size += [ "tas" ] + if mnemonic in no_size: + ext.update({ 0:'', 1:'', 2:'', 4:'' }) + return mnemonic + ext[insn.op_size.size] + +def print_insn_detail_np(insn): + # objdump format hack + if insn.size == 2: + space = ' ' * 11 + if insn.size == 4: + space = ' ' * 6 + if insn.size >= 6: + space = ' ' + space_ops = '' + if len(insn.operands) > 0: + space_ops = ' ' + + print(" %x:\t%s%s\t%s%s%s" % (insn.address, dump_bytes(insn._raw.bytes, min(insn.size, 6)), space, dump_mnemonic(insn), space_ops, dump_ops(insn))) + + if insn.size > 6: + delta = min(insn.size, 6) + print(" %x:\t%s " % (insn.address+delta, dump_bytes(insn._raw.bytes[delta:], min(insn.size-delta, 6)))) + + +def print_objdump_dumpheader(filename='', address=0): + print(objdump_dumpheader_fmt % (filename, address)) + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + filename = "/dev/stdin" + address = 0 + if len(sys.argv) > 1: + filename = sys.argv[1] + if len(sys.argv) > 2: + address = int(sys.argv[2],16) + if len(sys.argv) > 3: + debug_mode = True + + with open(filename, "rb") as f: + code = f.read() + + try: + md = Cs(arch, mode) + md.detail = True + + print_objdump_dumpheader(filename, address) + + for insn in md.disasm(code, address): + print_insn_detail_np(insn) + + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch new file mode 100644 index 0000000..b51aa51 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0001-capstone-generate-GenRegisterInfo.inc.patch @@ -0,0 +1,338 @@ +From 5d631cb16e7ba5dd0380ff1ee9dda192b1cdad18 Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 17:02:40 +0200 +Subject: [PATCH 1/7] capstone: generate *GenRegisterInfo.inc + +--- + utils/TableGen/RegisterInfoEmitter.cpp | 130 ++++++++++++++++++++++--- + 1 file changed, 115 insertions(+), 15 deletions(-) + +diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp +index 49016cca799..6ebb7148b1b 100644 +--- a/utils/TableGen/RegisterInfoEmitter.cpp ++++ b/utils/TableGen/RegisterInfoEmitter.cpp +@@ -99,6 +99,12 @@ private: + + } // end anonymous namespace + ++#ifdef CAPSTONE ++#define NAME_PREFIX Target.getName() << "_" << ++#else ++#define NAME_PREFIX ++#endif ++ + // runEnums - Print out enum values for all of the registers. + void RegisterInfoEmitter::runEnums(raw_ostream &OS, + CodeGenTarget &Target, CodeGenRegBank &Bank) { +@@ -107,13 +113,22 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, + // Register enums are stored as uint16_t in the tables. Make sure we'll fit. + assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); + ++#ifndef CAPSTONE + StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); ++#endif + + emitSourceFileHeader("Target Register Enum Values", OS); + ++#ifdef CAPSTONE ++ OS << "/* Capstone Disassembly Engine */\n" ++ "/* By Nguyen Anh Quynh , 2013-2015 */\n" ++ "\n"; ++#endif ++ + OS << "\n#ifdef GET_REGINFO_ENUM\n"; + OS << "#undef GET_REGINFO_ENUM\n\n"; + ++#ifndef CAPSTONE + OS << "namespace llvm {\n\n"; + + OS << "class MCRegisterClass;\n" +@@ -122,16 +137,20 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, + + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; +- OS << "enum {\n NoRegister,\n"; ++#endif ++ ++ OS << "enum {\n " << NAME_PREFIX "NoRegister,\n"; + + for (const auto &Reg : Registers) +- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; ++ OS << " " << NAME_PREFIX Reg.getName() << " = " << Reg.EnumValue << ",\n"; + assert(Registers.size() == Registers.back().EnumValue && + "Register enum value mismatch!"); +- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; ++ OS << " " << NAME_PREFIX "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; + OS << "};\n"; ++#ifndef CAPSTONE + if (!Namespace.empty()) + OS << "} // end namespace " << Namespace << "\n"; ++#endif + + const auto &RegisterClasses = Bank.getRegClasses(); + if (!RegisterClasses.empty()) { +@@ -140,18 +159,29 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, + assert(RegisterClasses.size() <= 0xffff && + "Too many register classes to fit in tables"); + +- OS << "\n// Register classes\n\n"; ++ OS << "\n// Register classes\n"; ++#ifndef CAPSTONE ++ OS << "\n"; + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; ++#endif + OS << "enum {\n"; + for (const auto &RC : RegisterClasses) +- OS << " " << RC.getName() << "RegClassID" ++ OS << " " << NAME_PREFIX RC.getName() << "RegClassID" + << " = " << RC.EnumValue << ",\n"; +- OS << "\n };\n"; ++#ifdef CAPSTONE ++ OS ++#else ++ OS << "\n " ++#endif ++ << "};\n"; ++#ifndef CAPSTONE + if (!Namespace.empty()) + OS << "} // end namespace " << Namespace << "\n\n"; ++#endif + } + ++#ifndef CAPSTONE + const std::vector &RegAltNameIndices = Target.getRegAltNameIndices(); + // If the only definition is the default NoRegAltName, we don't need to + // emit anything. +@@ -182,8 +212,11 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, + if (!Namespace.empty()) + OS << "} // end namespace " << Namespace << "\n\n"; + } ++#endif + ++#ifndef CAPSTONE + OS << "} // end namespace llvm\n\n"; ++#endif + OS << "#endif // GET_REGINFO_ENUM\n\n"; + } + +@@ -830,7 +863,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + + const auto &Regs = RegBank.getRegisters(); + ++#ifndef CAPSTONE + auto &SubRegIndices = RegBank.getSubRegIndices(); ++#endif + // The lists of sub-registers and super-registers go in the same array. That + // allows us to share suffixes. + typedef std::vector RegVec; +@@ -922,25 +957,40 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + LaneMaskSeqs.layout(); + SubRegIdxSeqs.layout(); + ++#ifndef CAPSTONE + OS << "namespace llvm {\n\n"; ++#endif + + const std::string &TargetName = Target.getName(); + + // Emit the shared table of differential lists. +- OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; ++#ifdef CAPSTONE ++ OS << "static" ++#else ++ OS << "extern" ++#endif ++ << " const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; + DiffSeqs.emit(OS, printDiff16); + OS << "};\n\n"; + ++#ifndef CAPSTONE + // Emit the shared table of regunit lane mask sequences. + OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; + LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); + OS << "};\n\n"; ++#endif + + // Emit the table of sub-register indexes. +- OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; ++#ifdef CAPSTONE ++ OS << "static" ++#else ++ OS << "extern" ++#endif ++ << " const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; + SubRegIdxSeqs.emit(OS, printSubRegIndex); + OS << "};\n\n"; + ++#ifndef CAPSTONE + // Emit the table of sub-register index sizes. + OS << "extern const MCRegisterInfo::SubRegCoveredBits " + << TargetName << "SubRegIdxRanges[] = {\n"; +@@ -950,14 +1000,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + << Idx.getName() << "\n"; + } + OS << "};\n\n"; ++#endif + + // Emit the string table. + RegStrings.layout(); ++#ifndef CAPSTONE + OS << "extern const char " << TargetName << "RegStrings[] = {\n"; + RegStrings.emit(OS, printChar); + OS << "};\n\n"; ++#endif + +- OS << "extern const MCRegisterDesc " << TargetName ++#ifdef CAPSTONE ++ OS << "static" ++#else ++ OS << "extern" ++#endif ++ << " const MCRegisterDesc " << TargetName + << "RegDesc[] = { // Descriptors\n"; + OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; + +@@ -973,6 +1031,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + } + OS << "};\n\n"; // End of register descriptors... + ++#ifndef CAPSTONE + // Emit the table of register unit roots. Each regunit has one or two root + // registers. + OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; +@@ -986,11 +1045,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + OS << " },\n"; + } + OS << "};\n\n"; ++#endif + + const auto &RegisterClasses = RegBank.getRegClasses(); + + // Loop over all of the register classes... emitting each one. ++#ifndef CAPSTONE + OS << "namespace { // Register classes...\n"; ++#endif + + SequenceToOffsetTable RegClassStrings; + +@@ -1005,15 +1067,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + + // Emit the register list now. + OS << " // " << Name << " Register Class...\n" +- << " const MCPhysReg " << Name ++ << " " ++#ifdef CAPSTONE ++ << "static " ++#endif ++ << "const MCPhysReg " << Name + << "[] = {\n "; + for (Record *Reg : Order) { +- OS << getQualifiedName(Reg) << ", "; ++#ifdef CAPSTONE ++ OS << NAME_PREFIX Reg->getName() ++#else ++ OS << getQualifiedName(Reg) ++#endif ++ << ", "; + } + OS << "\n };\n\n"; + + OS << " // " << Name << " Bit set.\n" +- << " const uint8_t " << Name ++ << " " ++#ifdef CAPSTONE ++ << "static " ++#endif ++ << "const uint8_t " << Name + << "Bits[] = {\n "; + BitVectorEmitter BVE; + for (Record *Reg : Order) { +@@ -1023,14 +1098,23 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + OS << "\n };\n\n"; + + } ++#ifndef CAPSTONE + OS << "} // end anonymous namespace\n\n"; ++#endif + + RegClassStrings.layout(); ++#ifndef CAPSTONE + OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; + RegClassStrings.emit(OS, printChar); + OS << "};\n\n"; ++#endif + +- OS << "extern const MCRegisterClass " << TargetName ++#ifdef CAPSTONE ++ OS << "static" ++#else ++ OS << "extern" ++#endif ++ << " const MCRegisterClass " << TargetName + << "MCRegisterClasses[] = {\n"; + + for (const auto &RC : RegisterClasses) { +@@ -1041,7 +1125,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " + << RegClassStrings.get(RC.getName()) << ", " + << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " +- << RC.getQualifiedName() + "RegClassID" << ", " ++#ifdef CAPSTONE ++ << NAME_PREFIX RC.getName() ++#else ++ << RC.getQualifiedName() ++#endif ++ << "RegClassID" << ", " + << RegSize/8 << ", " + << RC.CopyCost << ", " + << ( RC.Allocatable ? "true" : "false" ) << " },\n"; +@@ -1049,6 +1138,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + + OS << "};\n\n"; + ++#ifndef CAPSTONE + EmitRegMappingTables(OS, Regs, false); + + // Emit Reg encoding table +@@ -1067,7 +1157,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + OS << " " << Value << ",\n"; + } + OS << "};\n"; // End of HW encoding table ++#endif + ++#ifndef CAPSTONE + // MCRegisterInfo initialization routine. + OS << "static inline void Init" << TargetName + << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " +@@ -1088,7 +1180,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + OS << "}\n\n"; + + OS << "} // end namespace llvm\n\n"; +- OS << "#endif // GET_REGINFO_MC_DESC\n\n"; ++#endif ++ OS << "#endif // GET_REGINFO_MC_DESC\n" ++#ifndef CAPSTONE ++ << "\n" ++#endif ++ ; + } + + void +@@ -1568,10 +1665,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, + + void RegisterInfoEmitter::run(raw_ostream &OS) { + CodeGenRegBank &RegBank = Target.getRegBank(); ++ + runEnums(OS, Target, RegBank); + runMCDesc(OS, Target, RegBank); ++#ifndef CAPSTONE + runTargetHeader(OS, Target, RegBank); + runTargetDesc(OS, Target, RegBank); ++#endif + + if (RegisterInfoDebug) + debugDump(errs()); +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch new file mode 100644 index 0000000..56ad282 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0002-capstone-generate-GenSubtargetInfo.inc.patch @@ -0,0 +1,86 @@ +From 46ca491e1bbbc9ace2a91fe6a7b112c83b9b88cc Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 17:42:59 +0200 +Subject: [PATCH 2/7] capstone: generate *GenSubtargetInfo.inc + +--- + utils/TableGen/SubtargetEmitter.cpp | 28 +++++++++++++++++++++++++++- + 1 file changed, 27 insertions(+), 1 deletion(-) + +diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp +index c5da8d8142f..98ab3240472 100644 +--- a/utils/TableGen/SubtargetEmitter.cpp ++++ b/utils/TableGen/SubtargetEmitter.cpp +@@ -147,7 +147,9 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { + if (N > MAX_SUBTARGET_FEATURES) + PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES."); + ++#ifndef CAPSTONE + OS << "namespace " << Target << " {\n"; ++#endif + + // Open enumeration. + OS << "enum {\n"; +@@ -158,12 +160,22 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { + Record *Def = DefList[i]; + + // Get and emit name +- OS << " " << Def->getName() << " = " << i << ",\n"; ++ OS << " " ++#ifdef CAPSTONE ++ << Target << "_" ++#endif ++ << Def->getName() << " = " ++#ifdef CAPSTONE ++ << "1ULL << " ++#endif ++ << i << ",\n"; + } + + // Close enumeration and namespace + OS << "};\n"; ++#ifndef CAPSTONE + OS << "} // end namespace " << Target << "\n"; ++#endif + } + + // +@@ -1709,14 +1721,27 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { + void SubtargetEmitter::run(raw_ostream &OS) { + emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); + ++#ifdef CAPSTONE ++ OS << "/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n" ++ "/* By Nguyen Anh Quynh , 2013-2015 */\n" ++ "\n"; ++#endif ++ + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; + OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; + ++#ifndef CAPSTONE + OS << "namespace llvm {\n"; ++#endif + Enumeration(OS); ++#ifdef CAPSTONE ++ OS << "\n"; ++#else + OS << "} // end namespace llvm\n\n"; ++#endif + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; + ++#ifndef CAPSTONE + OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; + OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n"; + +@@ -1857,6 +1882,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { + OS << "} // end namespace llvm\n\n"; + + OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; ++#endif + } + + namespace llvm { +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch new file mode 100644 index 0000000..2baa59f --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0003-capstone-generate-GenInstrInfo.inc.patch @@ -0,0 +1,130 @@ +From a73fe8ac18d3ca81fa7a8d8c404cd7e0faf92ddc Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 17:59:43 +0200 +Subject: [PATCH 3/7] capstone: generate *GenInstrInfo.inc + +--- + utils/TableGen/InstrInfoEmitter.cpp | 49 ++++++++++++++++++++++++++--- + 1 file changed, 44 insertions(+), 5 deletions(-) + +diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp +index 0aff1aa6f94..2f3a2729262 100644 +--- a/utils/TableGen/InstrInfoEmitter.cpp ++++ b/utils/TableGen/InstrInfoEmitter.cpp +@@ -92,6 +92,7 @@ private: + + } // end anonymous namespace + ++#ifndef CAPSTONE + static void PrintDefList(const std::vector &Uses, + unsigned Num, raw_ostream &OS) { + OS << "static const MCPhysReg ImplicitList" << Num << "[] = { "; +@@ -99,6 +100,7 @@ static void PrintDefList(const std::vector &Uses, + OS << getQualifiedName(U) << ", "; + OS << "0 };\n"; + } ++#endif + + //===----------------------------------------------------------------------===// + // Operand Info Emission. +@@ -426,8 +428,17 @@ void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS) { + // run - Emit the main instruction description records for the target... + void InstrInfoEmitter::run(raw_ostream &OS) { + emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS); ++ ++#ifdef CAPSTONE ++ OS << "/* Capstone Disassembly Engine */\n" ++ "/* By Nguyen Anh Quynh , 2013-2015 */\n" ++ "\n" ++ "\n"; ++#endif ++ + emitEnums(OS); + ++#ifndef CAPSTONE + OS << "#ifdef GET_INSTRINFO_MC_DESC\n"; + OS << "#undef GET_INSTRINFO_MC_DESC\n"; + +@@ -545,6 +556,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { + emitOperandTypesEnum(OS, Target); + + emitMCIIHelperMethods(OS); ++#endif + } + + void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, +@@ -659,7 +671,9 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { + OS << "#ifdef GET_INSTRINFO_ENUM\n"; + OS << "#undef GET_INSTRINFO_ENUM\n"; + ++#ifndef CAPSTONE + OS << "namespace llvm {\n\n"; ++#endif + + CodeGenTarget Target(Records); + +@@ -669,17 +683,39 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { + if (Namespace.empty()) + PrintFatalError("No instructions defined!"); + ++#ifndef CAPSTONE + OS << "namespace " << Namespace << " {\n"; +- OS << " enum {\n"; ++#endif ++#ifdef CAPSTONE ++ OS << "\n" ++#else ++ OS << " " ++#endif ++ << "enum {\n"; + unsigned Num = 0; + for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) +- OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; +- OS << " INSTRUCTION_LIST_END = " << Num << "\n"; ++ OS << " " ++#ifdef CAPSTONE ++ << Target.getName() << "_" ++#endif ++ << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; ++ OS << " " ++#ifdef CAPSTONE ++ << Target.getName() << "_" ++#endif ++ << "INSTRUCTION_LIST_END = " << Num << "\n"; + OS << " };\n\n"; ++#ifndef CAPSTONE + OS << "} // end " << Namespace << " namespace\n"; + OS << "} // end llvm namespace\n"; +- OS << "#endif // GET_INSTRINFO_ENUM\n\n"; +- ++#endif ++ OS << "#endif // GET_INSTRINFO_ENUM\n" ++#ifndef CAPSTONE ++ << "\n" ++#endif ++ ; ++ ++#ifndef CAPSTONE + OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n"; + OS << "#undef GET_INSTRINFO_SCHED_ENUM\n"; + OS << "namespace llvm {\n\n"; +@@ -696,13 +732,16 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { + OS << "} // end llvm namespace\n"; + + OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n"; ++#endif + } + + namespace llvm { + + void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { + InstrInfoEmitter(RK).run(OS); ++#ifndef CAPSTONE + EmitMapTable(RK, OS); ++#endif + } + + } // end llvm namespace +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch new file mode 100644 index 0000000..0002b81 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0004-capstone-generate-GenDisassemblerTables.inc.patch @@ -0,0 +1,472 @@ +From 29da4c6929679b8ac4019767ab4ebcd83c9894b4 Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 18:20:17 +0200 +Subject: [PATCH 4/7] capstone: generate *GenDisassemblerTables.inc + +--- + utils/TableGen/DisassemblerEmitter.cpp | 12 +- + utils/TableGen/FixedLenDecoderEmitter.cpp | 248 ++++++++++++++++++++-- + 2 files changed, 239 insertions(+), 21 deletions(-) + +diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp +index b99a0a973a2..2ac6d89645c 100644 +--- a/utils/TableGen/DisassemblerEmitter.cpp ++++ b/utils/TableGen/DisassemblerEmitter.cpp +@@ -106,6 +106,11 @@ extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, + void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { + CodeGenTarget Target(Records); + emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); ++#ifdef CAPSTONE ++ OS << "/* Capstone Disassembly Engine */\n" ++ "/* By Nguyen Anh Quynh , 2013-2015 */\n" ++ "\n"; ++#endif + + // X86 uses a custom disassembler. + if (Target.getName() == "X86") { +@@ -150,7 +155,12 @@ void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { + } + + EmitFixedLenDecoder(Records, OS, Target.getName(), +- "if (", " == MCDisassembler::Fail)", ++ "if (", ++#ifdef CAPSTONE ++ " == MCDisassembler_Fail)", ++#else ++ " == MCDisassembler::Fail)", ++#endif + "MCDisassembler::Success", "MCDisassembler::Fail", ""); + } + +diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp +index fcecc764d44..36845d960d8 100644 +--- a/utils/TableGen/FixedLenDecoderEmitter.cpp ++++ b/utils/TableGen/FixedLenDecoderEmitter.cpp +@@ -730,7 +730,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + ++I; + unsigned Start = *I++; + unsigned Len = *I++; +- OS.indent(Indentation) << "MCD::OPC_ExtractField, " << Start << ", " ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_ExtractField" ++#else ++ << "MCD::OPC_ExtractField" ++#endif ++ << ", " << Start << ", " + << Len << ", // Inst{"; + if (Len > 1) + OS << (Start + Len - 1) << "-"; +@@ -739,7 +745,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + } + case MCD::OPC_FilterValue: { + ++I; +- OS.indent(Indentation) << "MCD::OPC_FilterValue, "; ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_FilterValue" ++#else ++ << "MCD::OPC_FilterValue" ++#endif ++ << ", "; + // The filter value is ULEB128 encoded. + while (*I >= 128) + OS << (unsigned)*I++ << ", "; +@@ -759,7 +771,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + ++I; + unsigned Start = *I++; + unsigned Len = *I++; +- OS.indent(Indentation) << "MCD::OPC_CheckField, " << Start << ", " ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_CheckField" ++#else ++ << "MCD::OPC_CheckField" ++#endif ++ << ", " << Start << ", " + << Len << ", ";// << Val << ", " << NumToSkip << ",\n"; + // ULEB128 encoded field value. + for (; *I >= 128; ++I) +@@ -777,7 +795,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + } + case MCD::OPC_CheckPredicate: { + ++I; +- OS.indent(Indentation) << "MCD::OPC_CheckPredicate, "; ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_CheckPredicate" ++#else ++ << "MCD::OPC_CheckPredicate" ++#endif ++ << ", "; + for (; *I >= 128; ++I) + OS << (unsigned)*I << ", "; + OS << (unsigned)*I++ << ", "; +@@ -803,7 +827,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + && "ULEB128 value too large!"); + // Decode the Opcode value. + unsigned Opc = decodeULEB128(Buffer); +- OS.indent(Indentation) << "MCD::OPC_" << (IsTry ? "Try" : "") ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_" ++#else ++ << "MCD::OPC_" ++#endif ++ << (IsTry ? "Try" : "") + << "Decode, "; + for (p = Buffer; *p >= 128; ++p) + OS << (unsigned)*p << ", "; +@@ -837,7 +867,12 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + } + case MCD::OPC_SoftFail: { + ++I; +- OS.indent(Indentation) << "MCD::OPC_SoftFail"; ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_SoftFail"; ++#else ++ << "MCD::OPC_SoftFail"; ++#endif + // Positive mask + uint64_t Value = 0; + unsigned Shift = 0; +@@ -869,7 +904,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + } + case MCD::OPC_Fail: { + ++I; +- OS.indent(Indentation) << "MCD::OPC_Fail,\n"; ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "MCD_OPC_Fail" ++#else ++ << "MCD::OPC_Fail" ++#endif ++ << ",\n"; + break; + } + } +@@ -884,23 +925,46 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, + void FixedLenDecoderEmitter:: + emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates, + unsigned Indentation) const { ++#ifdef CAPSTONE ++ OS.indent(Indentation) << "static bool getbool(uint64_t b)\n"; ++ OS.indent(Indentation) << "{\n"; ++ OS.indent(Indentation) << "\treturn b != 0;\n"; ++ OS.indent(Indentation) << "}\n\n"; ++#endif ++ + // The predicate function is just a big switch statement based on the + // input predicate index. + OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " ++#ifdef CAPSTONE ++ << "uint64_t Bits)\n{\n"; ++#else + << "const FeatureBitset& Bits) {\n"; ++#endif + Indentation += 2; + if (!Predicates.empty()) { + OS.indent(Indentation) << "switch (Idx) {\n"; +- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; ++ OS.indent(Indentation) << "default: " ++#ifdef CAPSTONE ++ << "// " ++#endif ++ << "llvm_unreachable(\"Invalid index!\");\n"; + unsigned Index = 0; + for (const auto &Predicate : Predicates) { + OS.indent(Indentation) << "case " << Index++ << ":\n"; +- OS.indent(Indentation+2) << "return (" << Predicate << ");\n"; ++ OS.indent(Indentation+2) << "return " ++#ifdef CAPSTONE ++ << "getbool" ++#endif ++ << "(" << Predicate << ");\n"; + } + OS.indent(Indentation) << "}\n"; + } else { + // No case statement to emit +- OS.indent(Indentation) << "llvm_unreachable(\"Invalid index!\");\n"; ++ OS.indent(Indentation) ++#ifdef CAPSTONE ++ << "// " ++#endif ++ << "llvm_unreachable(\"Invalid index!\");\n"; + } + Indentation -= 2; + OS.indent(Indentation) << "}\n\n"; +@@ -911,23 +975,39 @@ emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders, + unsigned Indentation) const { + // The decoder function is just a big switch statement based on the + // input decoder index. ++#ifdef CAPSTONE ++#define EDF_EOL " \\\n" ++ OS.indent(Indentation) << "#define DecodeToMCInst(fname,fieldname, InsnType) \\\n"; ++ OS.indent(Indentation) << "static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \\\n"; ++ OS.indent(Indentation) << " uint64_t Address, const void *Decoder) \\\n"; ++ OS.indent(Indentation) << "{ \\\n"; ++#else ++#define EDF_EOL "\n" + OS.indent(Indentation) << "template\n"; + OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S," + << " unsigned Idx, InsnType insn, MCInst &MI,\n"; + OS.indent(Indentation) << " uint64_t " + << "Address, const void *Decoder, bool &DecodeComplete) {\n"; ++#endif + Indentation += 2; ++#ifndef CAPSTONE + OS.indent(Indentation) << "DecodeComplete = true;\n"; +- OS.indent(Indentation) << "InsnType tmp;\n"; +- OS.indent(Indentation) << "switch (Idx) {\n"; +- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; ++#endif ++ OS.indent(Indentation) << "InsnType tmp;" EDF_EOL; ++ OS.indent(Indentation) << "switch (Idx) {" EDF_EOL; ++ OS.indent(Indentation) << "default:" ++#ifndef CAPSTONE ++ << " llvm_unreachable(\"Invalid index!\");\n"; ++#else ++ << " \\\n"; ++#endif + unsigned Index = 0; + for (const auto &Decoder : Decoders) { +- OS.indent(Indentation) << "case " << Index++ << ":\n"; ++ OS.indent(Indentation) << "case " << Index++ << ":" EDF_EOL; + OS << Decoder; +- OS.indent(Indentation+2) << "return S;\n"; ++ OS.indent(Indentation+2) << "return S;" EDF_EOL; + } +- OS.indent(Indentation) << "}\n"; ++ OS.indent(Indentation) << "}" EDF_EOL; + Indentation -= 2; + OS.indent(Indentation) << "}\n\n"; + } +@@ -1054,16 +1134,21 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, + const std::string &Decoder = OpInfo.Decoder; + + if (OpInfo.numFields() != 1) +- o.indent(Indentation) << "tmp = 0;\n"; ++ o.indent(Indentation) << "tmp = 0;" EDF_EOL; + + for (const EncodingField &EF : OpInfo) { + o.indent(Indentation) << "tmp "; + if (OpInfo.numFields() != 1) o << '|'; +- o << "= fieldFromInstruction" ++ o << "= " ++#ifdef CAPSTONE ++ << "fieldname" ++#else ++ << "fieldFromInstruction" ++#endif + << "(insn, " << EF.Base << ", " << EF.Width << ')'; + if (OpInfo.numFields() != 1 || EF.Offset != 0) + o << " << " << EF.Offset; +- o << ";\n"; ++ o << ";" EDF_EOL; + } + + if (Decoder != "") { +@@ -1071,8 +1156,12 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, + o.indent(Indentation) << Emitter->GuardPrefix << Decoder + << "(MI, tmp, Address, Decoder)" + << Emitter->GuardPostfix ++#ifdef CAPSTONE ++ << " return MCDisassembler_Fail; \\\n"; ++#else + << " { " << (OpHasCompleteDecoder ? "" : "DecodeComplete = false; ") + << "return MCDisassembler::Fail; }\n"; ++#endif + } else { + OpHasCompleteDecoder = true; + o.indent(Indentation) << "MI.addOperand(MCOperand::createImm(tmp));\n"; +@@ -1091,7 +1180,13 @@ void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation, + << "(MI, insn, Address, Decoder)" + << Emitter->GuardPostfix + << " { " << (HasCompleteDecoder ? "" : "DecodeComplete = false; ") +- << "return MCDisassembler::Fail; }\n"; ++ << "return " ++#ifdef CAPSTONE ++ << "MCDisassembler_Fail" ++#else ++ << "MCDisassembler::Fail" ++#endif ++ << "; }\n"; + break; + } + +@@ -1129,10 +1224,19 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders, + static void emitSinglePredicateMatch(raw_ostream &o, StringRef str, + const std::string &PredicateNamespace) { + if (str[0] == '!') ++#ifdef CAPSTONE ++ o << "~(Bits & " << PredicateNamespace << "_" ++ << str.slice(1,str.size()) << ")"; ++#else + o << "!Bits[" << PredicateNamespace << "::" + << str.slice(1,str.size()) << "]"; ++#endif + else ++#ifdef CAPSTONE ++ o << "(Bits & " << PredicateNamespace << "_" << str << ")"; ++#else + o << "Bits[" << PredicateNamespace << "::" << str << "]"; ++#endif + } + + bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, +@@ -2047,6 +2151,17 @@ static bool populateInstruction(CodeGenTarget &Target, + // fieldFromInstruction(). + static void emitFieldFromInstruction(formatted_raw_ostream &OS) { + OS << "// Helper function for extracting fields from encoded instructions.\n" ++#ifdef CAPSTONE ++ << "#define FieldFromInstruction(fname, InsnType) \\\n" ++ << "static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\\n" ++ << "{ \\\n" ++ << " InsnType fieldMask; \\\n" ++ << " if (numBits == sizeof(InsnType)*8) \\\n" ++ << " fieldMask = (InsnType)(-1LL); \\\n" ++ << " else \\\n" ++ << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\\n" ++ << " return (insn & fieldMask) >> startBit; \\\n" ++#else + << "template\n" + << "static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,\n" + << " unsigned numBits) {\n" +@@ -2058,12 +2173,92 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) { + << " else\n" + << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit;\n" + << " return (insn & fieldMask) >> startBit;\n" ++#endif + << "}\n\n"; + } + + // emitDecodeInstruction - Emit the templated helper function + // decodeInstruction(). + static void emitDecodeInstruction(formatted_raw_ostream &OS) { ++#ifdef CAPSTONE ++ OS << "#define DecodeInstruction(fname, fieldname, decoder, InsnType) \\\n" ++ << "static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \\\n" ++ << " InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \\\n" ++ << "{ \\\n" ++ << " uint64_t Bits = getFeatureBits(feature); \\\n" ++ << " const uint8_t *Ptr = DecodeTable; \\\n" ++ << " uint32_t CurFieldValue = 0, ExpectedValue; \\\n" ++ << " DecodeStatus S = MCDisassembler_Success; \\\n" ++ << " unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \\\n" ++ << " InsnType Val, FieldValue, PositiveMask, NegativeMask; \\\n" ++ << " bool Pred, Fail; \\\n" ++ << " for (;;) { \\\n" ++ << " switch (*Ptr) { \\\n" ++ << " default: \\\n" ++ << " return MCDisassembler_Fail; \\\n" ++ << " case MCD_OPC_ExtractField: { \\\n" ++ << " Start = *++Ptr; \\\n" ++ << " Len = *++Ptr; \\\n" ++ << " ++Ptr; \\\n" ++ << " CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \\\n" ++ << " break; \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_FilterValue: { \\\n" ++ << " Val = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " NumToSkip = *Ptr++; \\\n" ++ << " NumToSkip |= (*Ptr++) << 8; \\\n" ++ << " if (Val != CurFieldValue) \\\n" ++ << " Ptr += NumToSkip; \\\n" ++ << " break; \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_CheckField: { \\\n" ++ << " Start = *++Ptr; \\\n" ++ << " Len = *++Ptr; \\\n" ++ << " FieldValue = fieldname(insn, Start, Len); \\\n" ++ << " ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " NumToSkip = *Ptr++; \\\n" ++ << " NumToSkip |= (*Ptr++) << 8; \\\n" ++ << " if (ExpectedValue != FieldValue) \\\n" ++ << " Ptr += NumToSkip; \\\n" ++ << " break; \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_CheckPredicate: { \\\n" ++ << " PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " NumToSkip = *Ptr++; \\\n" ++ << " NumToSkip |= (*Ptr++) << 8; \\\n" ++ << " Pred = checkDecoderPredicate(PIdx, Bits); \\\n" ++ << " if (!Pred) \\\n" ++ << " Ptr += NumToSkip; \\\n" ++ << " (void)Pred; \\\n" ++ << " break; \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_Decode: { \\\n" ++ << " Opc = (unsigned)decodeULEB128(++Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " MCInst_setOpcode(MI, Opc); \\\n" ++ << " return decoder(S, DecodeIdx, insn, MI, Address, MRI); \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_SoftFail: { \\\n" ++ << " PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \\\n" ++ << " Ptr += Len; \\\n" ++ << " Fail = (insn & PositiveMask) || (~insn & NegativeMask); \\\n" ++ << " if (Fail) \\\n" ++ << " S = MCDisassembler_SoftFail; \\\n" ++ << " break; \\\n" ++ << " } \\\n" ++ << " case MCD_OPC_Fail: { \\\n" ++ << " return MCDisassembler_Fail; \\\n" ++ << " } \\\n" ++ << " } \\\n" ++ << " } \\\n" ++#else + OS << "template\n" + << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], " + "MCInst &MI,\n" +@@ -2240,12 +2435,18 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { + << " }\n" + << " llvm_unreachable(\"bogosity detected in disassembler state " + "machine!\");\n" ++#endif + << "}\n\n"; + } + + // Emits disassembler code for instruction decoding. + void FixedLenDecoderEmitter::run(raw_ostream &o) { + formatted_raw_ostream OS(o); ++#ifdef CAPSTONE ++ OS << "#include \"../../MCInst.h\"\n"; ++ OS << "#include \"../../LEB128.h\"\n"; ++ OS << "\n"; ++#else + OS << "#include \"llvm/MC/MCInst.h\"\n"; + OS << "#include \"llvm/Support/Debug.h\"\n"; + OS << "#include \"llvm/Support/DataTypes.h\"\n"; +@@ -2254,6 +2455,7 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { + OS << "#include \n"; + OS << '\n'; + OS << "namespace llvm {\n\n"; ++#endif + + emitFieldFromInstruction(OS); + +@@ -2322,7 +2524,13 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { + // Emit the main entry point for the decoder, decodeInstruction(). + emitDecodeInstruction(OS); + ++#ifdef CAPSTONE ++ OS << "FieldFromInstruction(fieldFromInstruction, uint64_t)\n"; ++ OS << "DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t)\n"; ++ OS << "DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t)\n"; ++#else + OS << "\n} // End llvm namespace\n"; ++#endif + } + + namespace llvm { +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch new file mode 100644 index 0000000..cd1353e --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0005-capstone-generate-GenAsmWriter.inc.patch @@ -0,0 +1,225 @@ +From 5569e48b9cb34a33910e1e850fbfabc999f016a2 Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 20:00:08 +0200 +Subject: [PATCH 5/7] capstone: generate *GenAsmWriter.inc + +--- + utils/TableGen/AsmWriterEmitter.cpp | 89 +++++++++++++++++++++++++++-- + utils/TableGen/AsmWriterInst.cpp | 4 ++ + 2 files changed, 87 insertions(+), 6 deletions(-) + +diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp +index 3c4c9c8e5c6..133800d217c 100644 +--- a/utils/TableGen/AsmWriterEmitter.cpp ++++ b/utils/TableGen/AsmWriterEmitter.cpp +@@ -272,16 +272,22 @@ static void UnescapeString(std::string &Str) { + /// clearing the Instructions vector. + void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { + Record *AsmWriter = Target.getAsmWriter(); ++#ifndef CAPSTONE + StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); ++#endif + bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); + + O << + "/// printInstruction - This method is automatically generated by tablegen\n" + "/// from the instruction set description.\n" ++#ifdef CAPSTONE ++ "static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{\n"; ++#else + "void " << Target.getName() << ClassName + << "::printInstruction(const MCInst *MI, " + << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") + << "raw_ostream &O) {\n"; ++#endif + + // Build an aggregate string, and build a table of offsets into it. + SequenceToOffsetTable StringTable; +@@ -379,9 +385,16 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { + } + + // Emit the string table itself. ++#ifdef CAPSTONE ++ O << "#ifndef CAPSTONE_DIET\n"; ++#endif + O << " static const char AsmStrs[] = {\n"; + StringTable.emit(O, printChar); +- O << " };\n\n"; ++ O << " };\n" ++#ifdef CAPSTONE ++ << "#endif\n" ++#endif ++ << "\n"; + + // Emit the lookup tables in pieces to minimize wasted bytes. + unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; +@@ -409,21 +422,45 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { + // If the total bits is more than 32-bits we need to use a 64-bit type. + if (BitsLeft < (OpcodeInfoBits - 32)) + BitsOS << "(uint64_t)"; +- BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; ++ BitsOS << "OpInfo" << Table << "[" ++#ifdef CAPSTONE ++ << "MCInst_getOpcode(MI)" ++#else ++ << "MI->getOpcode()" ++#endif ++ << "] << " << Shift << ";\n"; + // Prepare the shift for the next iteration and increment the table count. + Shift += TableSize; + ++Table; + } + + // Emit the initial tab character. ++#ifndef CAPSTONE + O << " O << \"\\t\";\n\n"; ++#endif + + O << " // Emit the opcode for the instruction.\n"; + O << BitsString; + + // Emit the starting string. +- O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" +- << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; ++ O << " " ++#ifdef CAPSTONE ++ << "// " ++#endif ++ << "assert(Bits != 0 && \"Cannot print this instruction.\");\n" ++#ifdef CAPSTONE ++ << "#ifndef CAPSTONE_DIET\n" ++ << " SStream_concat0(O, " ++#else ++ << " O << " ++#endif ++ << "AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1" ++#ifdef CAPSTONE ++ << ");\n" ++ << "#endif\n\n"; ++#else ++ << ");\n\n"; ++#endif + + // Output the table driven operand information. + BitsLeft = OpcodeInfoBits-AsmStrBits; +@@ -455,7 +492,11 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { + O << " switch ((Bits >> " + << (OpcodeInfoBits-BitsLeft) << ") & " + << ((1 << NumBits)-1) << ") {\n" +- << " default: llvm_unreachable(\"Invalid command number.\");\n"; ++ << " default: " ++#ifdef CAPSTONE ++ << "// " ++#endif ++ << "llvm_unreachable(\"Invalid command number.\");\n"; + + // Print out all the cases. + for (unsigned j = 0, e = Commands.size(); j != e; ++j) { +@@ -536,6 +577,9 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, + } + + StringTable.layout(); ++#ifdef CAPSTONE ++ O << "#ifndef CAPSTONE_DIET\n"; ++#endif + O << " static const char AsmStrs" << AltName << "[] = {\n"; + StringTable.emit(O, printChar); + O << " };\n\n"; +@@ -552,8 +596,10 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, + } + + void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { ++#ifndef CAPSTONE + Record *AsmWriter = Target.getAsmWriter(); + StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); ++#endif + const auto &Registers = Target.getRegBank().getRegisters(); + const std::vector &AltNameIndices = Target.getRegAltNameIndices(); + bool hasAltNames = AltNameIndices.size() > 1; +@@ -563,12 +609,20 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { + "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" + "/// from the register set description. This returns the assembler name\n" + "/// for the specified register.\n" ++#ifdef CAPSTONE ++ "static const char *getRegisterName(unsigned RegNo)\n{\n"; ++#else + "const char *" << Target.getName() << ClassName << "::"; + if (hasAltNames) + O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; + else + O << "getRegisterName(unsigned RegNo) {\n"; +- O << " assert(RegNo && RegNo < " << (Registers.size()+1) ++#endif ++ O << " " ++#ifdef CAPSTONE ++ << "// " ++#endif ++ << "assert(RegNo && RegNo < " << (Registers.size()+1) + << " && \"Invalid register number!\");\n" + << "\n"; + +@@ -595,10 +649,22 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { + } + O << " }\n"; + } else { ++#ifdef CAPSTONE ++ O << " //int i;\n" ++ << " //for (i = 0; i < sizeof(RegAsmOffset); i++)\n" ++ << " // printf(\"%s = %u\\n\", AsmStrs+RegAsmOffset[i], i + 1);\n" ++ << " //printf(\"*************************\\n\");\n" ++#else + O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n" ++#endif + << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; + } ++#ifdef CAPSTONE ++ O << "#else\n" ++ << " return NULL;\n" ++ << "#endif\n"; ++#endif + O << "}\n"; + } + +@@ -1135,9 +1201,20 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { + } + + void AsmWriterEmitter::run(raw_ostream &O) { ++#ifdef CAPSTONE ++ O << "/* Capstone Disassembly Engine */\n" ++ "/* By Nguyen Anh Quynh , 2013-2015 */\n" ++ "\n" ++ "#include \t// debug\n" ++ "#include \n" ++ "\n" ++ "\n"; ++#endif + EmitPrintInstruction(O); + EmitGetRegisterName(O); ++#ifndef CAPSTONE + EmitPrintAliasInstruction(O); ++#endif + } + + namespace llvm { +diff --git a/utils/TableGen/AsmWriterInst.cpp b/utils/TableGen/AsmWriterInst.cpp +index 2c19e5d663d..6fa751e50df 100644 +--- a/utils/TableGen/AsmWriterInst.cpp ++++ b/utils/TableGen/AsmWriterInst.cpp +@@ -28,9 +28,13 @@ static bool isIdentChar(char C) { + + std::string AsmWriterOperand::getCode(bool PassSubtarget) const { + if (OperandType == isLiteralTextOperand) { ++#ifdef CAPSTONE ++ return "SStream_concat0(O, \"" + Str + "\");"; ++#else + if (Str.size() == 1) + return "O << '" + Str + "';"; + return "O << \"" + Str + "\";"; ++#endif + } + + if (OperandType == isLiteralStatementOperand) +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch new file mode 100644 index 0000000..7ee22d7 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0006-capstone-generate-MappingInsn.inc.patch @@ -0,0 +1,174 @@ +From 7a436110ef15c803dc8524af2fb5612bcacbb126 Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Tue, 7 Aug 2018 20:55:32 +0200 +Subject: [PATCH 6/7] capstone: generate *MappingInsn.inc + +--- + lib/Target/SystemZ/CMakeLists.txt | 1 + + utils/TableGen/InstrInfoEmitter.cpp | 95 +++++++++++++++++++++++++++++ + utils/TableGen/TableGen.cpp | 6 ++ + utils/TableGen/TableGenBackends.h | 1 + + 4 files changed, 103 insertions(+) + +diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt +index f83b4242fb4..4b5d9c4a3b2 100644 +--- a/lib/Target/SystemZ/CMakeLists.txt ++++ b/lib/Target/SystemZ/CMakeLists.txt +@@ -6,6 +6,7 @@ tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv) + tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) + tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) + tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) ++tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) + tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) + tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) + tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) +diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp +index 2f3a2729262..14ab1ea8a72 100644 +--- a/utils/TableGen/InstrInfoEmitter.cpp ++++ b/utils/TableGen/InstrInfoEmitter.cpp +@@ -744,4 +744,99 @@ void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { + #endif + } + ++#ifdef CAPSTONE ++std::string GetPublicName(const CodeGenInstruction *Inst) { ++ std::string Name = Inst->TheDef->getName(); ++ // Apply backward compatibility fixups. ++ // BRNLE -> BNLER. ++ if (Name.length() >= 5 && Name.substr(0, 5) == "BRAsm") { ++ Name = "B" + Name.substr(5, Name.length() - 5) + "R"; ++ } ++ // SSKEOpt -> SSKE. ++ while (Name.length() >= 3 && Name.substr(Name.length() - 3, 3) == "Opt") { ++ Name = Name.substr(0, Name.length() - 3); ++ } ++ // BRCLAsm -> BRCL. ++ while (true) { ++ size_t pos = Name.find("Asm"); ++ if (pos == std::string::npos) { ++ break; ++ } ++ Name = Name.substr(0, pos) + Name.substr(pos + 3); ++ } ++ // CPSDRxx -> CPSDR. ++ if (Name.length() >= 2) { ++ std::string Suffix2 = Name.substr(Name.length() - 2, 2); ++ if (Suffix2 == "dd" || Suffix2 == "ds" || ++ Suffix2 == "sd" || Suffix2 == "ss") { ++ Name = Name.substr(0, Name.length() - 2); ++ } ++ } ++ return "SYSZ_INS_" + Name; ++} ++ ++std::string GetRegisterName(Record *Reg) { ++ std::string Name = Reg->getName(); ++ for (char& c : Name) { ++ c = toupper(c); ++ } ++ // R0L, R0D -> R0. ++ if (Name.length() >= 3 && ++ Name[Name.length() - 3] == 'R' && ++ (Name[Name.length() - 1] == 'L' || ++ Name[Name.length() - 1] == 'D')) { ++ Name = Name.substr(0, Name.length() - 3) + Name[Name.length() - 2]; ++ } ++ return "SYSZ_REG_" + Name; ++} ++ ++std::string GetGroupName(Record *Pred) { ++ std::string Name = Pred->getName(); ++ for (char& c : Name) { ++ c = toupper(c); ++ } ++ if (Name.length() >= 7 && Name.substr(0, 7) == "FEATURE") { ++ Name = Name.substr(7); ++ } ++ return "SYSZ_GRP_" + Name; ++} ++ ++void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { ++ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" ++ "// By Nguyen Anh Quynh \n" ++ "\n"; ++ CodeGenTarget Target(RK); ++ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { ++ if (Inst->TheDef->getValueAsBit("isPseudo") || ++ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { ++ continue; ++ } ++ OS << "{\n" ++ << "\t" << Target.getName() << "_" << Inst->TheDef->getName() << ", " ++ << GetPublicName(Inst) << ",\n" ++ << "#ifndef CAPSTONE_DIET\n" ++ << "\t{ "; ++ for (Record *Use : Inst->TheDef->getValueAsListOfDefs("Uses")) { ++ OS << GetRegisterName(Use) << ", "; ++ } ++ OS << "0 }, { "; ++ for (Record *Def : Inst->TheDef->getValueAsListOfDefs("Defs")) { ++ OS << GetRegisterName(Def) << ", "; ++ } ++ OS << "0 }, { "; ++ ListInit *Predicates = Inst->TheDef->getValueAsListInit("Predicates"); ++ for (unsigned i = 0; i < Predicates->size(); ++i) { ++ OS << GetGroupName(Predicates->getElementAsRecord(i)) << ", "; ++ } ++ OS << "0 }, " ++ << Inst->TheDef->getValueAsBit("isBranch") ++ << ", " ++ << Inst->TheDef->getValueAsBit("isIndirectBranch") ++ << "\n" ++ << "#endif\n" ++ << "},\n"; ++ } ++} ++#endif ++ + } // end llvm namespace +diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp +index cf1404d8769..bbb4e860536 100644 +--- a/utils/TableGen/TableGen.cpp ++++ b/utils/TableGen/TableGen.cpp +@@ -27,6 +27,7 @@ enum ActionType { + GenEmitter, + GenRegisterInfo, + GenInstrInfo, ++ MappingInsn, + GenInstrDocs, + GenAsmWriter, + GenAsmMatcher, +@@ -65,6 +66,8 @@ namespace { + "Generate registers and register classes info"), + clEnumValN(GenInstrInfo, "gen-instr-info", + "Generate instruction descriptions"), ++ clEnumValN(MappingInsn, "mapping-insn", ++ ""), + clEnumValN(GenInstrDocs, "gen-instr-docs", + "Generate instruction documentation"), + clEnumValN(GenCallingConv, "gen-callingconv", +@@ -135,6 +138,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { + case GenInstrInfo: + EmitInstrInfo(Records, OS); + break; ++ case MappingInsn: ++ EmitMappingInsn(Records, OS); ++ break; + case GenInstrDocs: + EmitInstrDocs(Records, OS); + break; +diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h +index 1329a6d833f..a41e46b1db0 100644 +--- a/utils/TableGen/TableGenBackends.h ++++ b/utils/TableGen/TableGenBackends.h +@@ -75,6 +75,7 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS); + void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); + void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); + void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); ++void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); + void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); + void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); + void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch b/white_patch_detect/capstone-master/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch new file mode 100644 index 0000000..019540d --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/0007-capstone-generate-GenInsnNameMaps.inc.patch @@ -0,0 +1,110 @@ +From b42f9f2014ec49a22077b6610863d9341a74e142 Mon Sep 17 00:00:00 2001 +From: mephi42 +Date: Fri, 17 Aug 2018 11:07:39 +0200 +Subject: [PATCH 7/7] capstone: generate *GenInsnNameMaps.inc + +--- + lib/Target/SystemZ/CMakeLists.txt | 1 + + utils/TableGen/InstrInfoEmitter.cpp | 29 +++++++++++++++++++++++++++++ + utils/TableGen/TableGen.cpp | 6 ++++++ + utils/TableGen/TableGenBackends.h | 1 + + 4 files changed, 37 insertions(+) + +diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt +index 4b5d9c4a3b2..2c64e0a94b8 100644 +--- a/lib/Target/SystemZ/CMakeLists.txt ++++ b/lib/Target/SystemZ/CMakeLists.txt +@@ -7,6 +7,7 @@ tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) + tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) + tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) + tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) ++tablegen(LLVM SystemZGenInsnNameMaps.inc -gen-insn-name-maps) + tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) + tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) + tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) +diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp +index 14ab1ea8a72..ccf8170ca62 100644 +--- a/utils/TableGen/InstrInfoEmitter.cpp ++++ b/utils/TableGen/InstrInfoEmitter.cpp +@@ -837,6 +837,35 @@ void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { + << "},\n"; + } + } ++ ++std::string GetMnemonic(const CodeGenInstruction *Inst) { ++ std::string Mnemonic = Inst->AsmString; ++ ++ for (size_t i = 0; i < Mnemonic.length(); i++) { ++ if (Mnemonic[i] == '\t') { ++ return Mnemonic.substr(0, i); ++ } ++ } ++ return Mnemonic; ++} ++ ++void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS) { ++ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" ++ "// By Nguyen Anh Quynh \n" ++ "\n"; ++ CodeGenTarget Target(RK); ++ std::map M; ++ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { ++ if (Inst->TheDef->getValueAsBit("isPseudo") || ++ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { ++ continue; ++ } ++ M[GetPublicName(Inst)] = GetMnemonic(Inst); ++ } ++ for (auto &P : M) { ++ OS << "\t{ " << P.first << ", \"" << P.second << "\" },\n"; ++ } ++} + #endif + + } // end llvm namespace +diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp +index bbb4e860536..27c6603de5a 100644 +--- a/utils/TableGen/TableGen.cpp ++++ b/utils/TableGen/TableGen.cpp +@@ -28,6 +28,7 @@ enum ActionType { + GenRegisterInfo, + GenInstrInfo, + MappingInsn, ++ GenInsnNameMaps, + GenInstrDocs, + GenAsmWriter, + GenAsmMatcher, +@@ -68,6 +69,8 @@ namespace { + "Generate instruction descriptions"), + clEnumValN(MappingInsn, "mapping-insn", + ""), ++ clEnumValN(GenInsnNameMaps, "gen-insn-name-maps", ++ ""), + clEnumValN(GenInstrDocs, "gen-instr-docs", + "Generate instruction documentation"), + clEnumValN(GenCallingConv, "gen-callingconv", +@@ -141,6 +144,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { + case MappingInsn: + EmitMappingInsn(Records, OS); + break; ++ case GenInsnNameMaps: ++ EmitInsnNameMaps(Records, OS); ++ break; + case GenInstrDocs: + EmitInstrDocs(Records, OS); + break; +diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h +index a41e46b1db0..5656e5be849 100644 +--- a/utils/TableGen/TableGenBackends.h ++++ b/utils/TableGen/TableGenBackends.h +@@ -76,6 +76,7 @@ void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); + void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); + void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); + void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); ++void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS); + void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); + void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); + void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); +-- +2.19.1 + diff --git a/white_patch_detect/capstone-master/contrib/sysz_update/README.md b/white_patch_detect/capstone-master/contrib/sysz_update/README.md new file mode 100644 index 0000000..c50c7d1 --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/sysz_update/README.md @@ -0,0 +1,58 @@ +# How to update SystemZ tables. + +* Checkout LLVM. Patches are tested on commit `c13d5969^`, because + `c13d5969` changed the decode table format. +* Apply patches from the current directory. +* Run tablegen. + ``` + cd $LLVM + mkdir build + cd build + cmake -DCMAKE_CXX_FLAGS=-DCAPSTONE .. + make SystemZCommonTableGen -j$(getconf _NPROCESSORS_ONLN) + ``` +* Copy `.inc` files. + ``` + cp arch/SystemZ/SystemZGenInsnNameMaps.inc \ + arch/SystemZ/SystemZGenInsnNameMaps.inc.old + for inc in $(cd arch/SystemZ && ls *.inc); do + cp $LLVM/build/lib/Target/SystemZ/$inc arch/SystemZ/ + done + ``` +* Fixup `SystemZGenInsnNameMaps.inc`. + ``` + comm -1 -3 \ + <(grep SYSZ_INS_ arch/SystemZ/SystemZGenInsnNameMaps.inc.new + cat arch/SystemZ/SystemZGenInsnNameMaps.inc.old \ + arch/SystemZ/SystemZGenInsnNameMaps.inc.new \ + >arch/SystemZ/SystemZGenInsnNameMaps.inc + ``` +* Add new groups, insns, registers and formats. + * `include/capstone/systemz.h` + * `enum sysz_insn`: + ``` + comm -1 -3 \ + <(perl -ne 'if (/(SYSZ_INS_.+),/) { print "\t$1,\n" }' \ + +See the full example with Capstone integration at https://github.com/zer0mem/libc.git diff --git a/white_patch_detect/capstone-master/contrib/windows_kernel/libc.cpp b/white_patch_detect/capstone-master/contrib/windows_kernel/libc.cpp new file mode 100644 index 0000000..ac4a4eb --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/windows_kernel/libc.cpp @@ -0,0 +1,143 @@ +/** + * @file libc.cpp + * @author created by: Peter Hlavaty + */ + +#include "libc.h" +#include +#include + +#pragma warning(push) +#pragma warning (disable : 4565) + +#ifndef _LIBC_POOL_TAG +#define _LIBC_POOL_TAG 'colM' +#endif + +// very nice for debug forensics! +struct MEMBLOCK +{ + size_t size; +#pragma warning(push) +#pragma warning (disable : 4200) + __declspec(align(MEMORY_ALLOCATION_ALIGNMENT)) + char data[0]; +#pragma warning(pop) +}; + +EXTERN_C +__drv_when(return!=0, __drv_allocatesMem(pBlock)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size) +void* +__cdecl malloc( + __in size_t size + ) +{ + /* A specially crafted size value can trigger the overflow. + If the sum in a value that overflows or underflows the capacity of the type, + the function returns nullptr. */ + size_t number_of_bytes = 0; + if (!NT_SUCCESS(RtlSizeTAdd(size, sizeof(MEMBLOCK), &number_of_bytes))){ + return nullptr; + } + MEMBLOCK *pBlock = static_cast( + ExAllocatePoolWithTag( + NonPagedPoolNxCacheAligned, + number_of_bytes, + _LIBC_POOL_TAG)); + + if (nullptr == pBlock) + return nullptr; + + pBlock->size = size; + return pBlock->data; +} + +EXTERN_C +__drv_when(return != 0, __drv_allocatesMem(p)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size * n) +void* +__cdecl calloc(size_t n, size_t size) +{ + size_t total = n * size; + void *p = malloc(total); + + if (!p) return NULL; + + return memset(p, 0, total); +} + +EXTERN_C +__drv_when(return!=0, __drv_allocatesMem(inblock)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size) +void* +__cdecl realloc( + __in_opt void* ptr, + __in size_t size + ) +{ + if (!ptr) + return malloc(size); + + std::unique_ptr inblock = std::unique_ptr(static_cast(ptr)); + + // alloc new block + void* mem = malloc(size); + if (!mem) + return nullptr; + + // copy from old one, not overflow .. + memcpy(mem, inblock.get(), min(CONTAINING_RECORD(inblock.get(), MEMBLOCK, data)->size, size)); + return mem; +} + +EXTERN_C +__drv_maxIRQL(DISPATCH_LEVEL) +void +__cdecl free( + __inout_opt __drv_freesMem(Mem) void* ptr + ) +{ + if (ptr) + ExFreePoolWithTag(CONTAINING_RECORD(ptr, MEMBLOCK, data), _LIBC_POOL_TAG); +} + +#pragma warning(pop) + +__drv_when(return!=0, __drv_allocatesMem(ptr)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size) +void* +__cdecl operator new( + __in size_t size + ) +{ + return malloc(size); +} + +__drv_maxIRQL(DISPATCH_LEVEL) +void +__cdecl operator delete( + __inout void* ptr + ) +{ + free(ptr); +} + +int +__cdecl vsnprintf( + char *buffer, + size_t count, + const char *format, + va_list argptr +) +{ + return vsprintf_s(buffer, count, format, argptr); +} diff --git a/white_patch_detect/capstone-master/contrib/windows_kernel/libc.h b/white_patch_detect/capstone-master/contrib/windows_kernel/libc.h new file mode 100644 index 0000000..9498bac --- /dev/null +++ b/white_patch_detect/capstone-master/contrib/windows_kernel/libc.h @@ -0,0 +1,40 @@ +/** + * @file libc.h + * @author created by: Peter Hlavaty + */ + +#pragma once + +#include + +EXTERN_C +__drv_when(return!=0, __drv_allocatesMem(pBlock)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size) +void* __cdecl malloc(__in size_t size); + + +EXTERN_C +__drv_when(return != 0, __drv_allocatesMem(p)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size * n) +void* __cdecl calloc(size_t n, size_t size); + + +EXTERN_C +__drv_when(return!=0, __drv_allocatesMem(inblock)) +__checkReturn +__drv_maxIRQL(DISPATCH_LEVEL) +__bcount_opt(size) +void* __cdecl realloc(__in_opt void* ptr, __in size_t size); + + +EXTERN_C +__drv_maxIRQL(DISPATCH_LEVEL) +void __cdecl free(__inout_opt __drv_freesMem(Mem) void* ptr); + + +int __cdecl vsnprintf(char *buffer, size_t count, + const char *format, va_list argptr); diff --git a/white_patch_detect/capstone-master/cs.c b/white_patch_detect/capstone-master/cs.c new file mode 100644 index 0000000..3a5b1b3 --- /dev/null +++ b/white_patch_detect/capstone-master/cs.c @@ -0,0 +1,1580 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ +#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#pragma warning(disable:4996) // disable MSVC's warning on strcpy() +#pragma warning(disable:28719) // disable MSVC's warning on strcpy() +#endif +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#include +#include +#endif + +#include +#include + +#include "utils.h" +#include "MCRegisterInfo.h" + +#if defined(_KERNEL_MODE) +#include "windows\winkernel_mm.h" +#endif + +// Issue #681: Windows kernel does not support formatting float point +#if defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) +#if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_ARM64) || defined(CAPSTONE_HAS_M68K) +#define CAPSTONE_STR_INTERNAL(x) #x +#define CAPSTONE_STR(x) CAPSTONE_STR_INTERNAL(x) +#define CAPSTONE_MSVC_WRANING_PREFIX __FILE__ "("CAPSTONE_STR(__LINE__)") : warning message : " + +#pragma message(CAPSTONE_MSVC_WRANING_PREFIX "Windows driver does not support full features for selected architecture(s). Define CAPSTONE_DIET to compile Capstone with only supported features. See issue #681 for details.") + +#undef CAPSTONE_MSVC_WRANING_PREFIX +#undef CAPSTONE_STR +#undef CAPSTONE_STR_INTERNAL +#endif +#endif // defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) + +#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(CAPSTONE_DIET) && !defined(_KERNEL_MODE) +#define INSN_CACHE_SIZE 32 +#else +// reduce stack variable size for kernel/firmware +#define INSN_CACHE_SIZE 8 +#endif + +// default SKIPDATA mnemonic +#ifndef CAPSTONE_DIET +#define SKIPDATA_MNEM ".byte" +#else // No printing is available in diet mode +#define SKIPDATA_MNEM NULL +#endif + +#include "arch/AArch64/AArch64Module.h" +#include "arch/ARM/ARMModule.h" +#include "arch/EVM/EVMModule.h" +#include "arch/M680X/M680XModule.h" +#include "arch/M68K/M68KModule.h" +#include "arch/Mips/MipsModule.h" +#include "arch/PowerPC/PPCModule.h" +#include "arch/Sparc/SparcModule.h" +#include "arch/SystemZ/SystemZModule.h" +#include "arch/TMS320C64x/TMS320C64xModule.h" +#include "arch/X86/X86Module.h" +#include "arch/XCore/XCoreModule.h" +#include "arch/MOS65XX/MOS65XXModule.h" + +// constructor initialization for all archs +static cs_err (*cs_arch_init[MAX_ARCH])(cs_struct *) = { +#ifdef CAPSTONE_HAS_ARM + ARM_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_ARM64 + AArch64_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_MIPS + Mips_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_X86 + X86_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_POWERPC + PPC_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_SPARC + Sparc_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_SYSZ + SystemZ_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_XCORE + XCore_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_M68K + M68K_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_TMS320C64X + TMS320C64x_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_M680X + M680X_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_EVM + EVM_global_init, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + MOS65XX_global_init, +#else + NULL, +#endif +}; + +// support cs_option() for all archs +static cs_err (*cs_arch_option[MAX_ARCH]) (cs_struct *, cs_opt_type, size_t value) = { +#ifdef CAPSTONE_HAS_ARM + ARM_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_ARM64 + AArch64_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_MIPS + Mips_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_X86 + X86_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_POWERPC + PPC_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_SPARC + Sparc_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_SYSZ + SystemZ_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_XCORE + XCore_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_M68K + M68K_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_TMS320C64X + TMS320C64x_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_M680X + M680X_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_EVM + EVM_option, +#else + NULL, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + MOS65XX_option, +#else + NULL, +#endif + +}; + +// bitmask for finding disallowed modes for an arch: +// to be called in cs_open()/cs_option() +static cs_mode cs_arch_disallowed_mode_mask[MAX_ARCH] = { +#ifdef CAPSTONE_HAS_ARM + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 | CS_MODE_MCLASS + | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_ARM64 + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_MIPS + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO + | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_X86 + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_16), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_POWERPC + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN + | CS_MODE_QPX), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_SPARC + ~(CS_MODE_BIG_ENDIAN | CS_MODE_V9), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_SYSZ + ~(CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_XCORE + ~(CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_M68K + ~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_000 | CS_MODE_M68K_010 | CS_MODE_M68K_020 + | CS_MODE_M68K_030 | CS_MODE_M68K_040 | CS_MODE_M68K_060), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_TMS320C64X + ~(CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_M680X + ~(CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | CS_MODE_M680X_6800 + | CS_MODE_M680X_6801 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 + | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | CS_MODE_M680X_CPU12 + | CS_MODE_M680X_HCS08), +#else + 0, +#endif +#ifdef CAPSTONE_HAS_EVM + 0, +#else + 0, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + ~(CS_MODE_BIG_ENDIAN), +#else + 0, +#endif +}; + +// bitmask of enabled architectures +static uint32_t all_arch = 0 +#ifdef CAPSTONE_HAS_ARM + | (1 << CS_ARCH_ARM) +#endif +#ifdef CAPSTONE_HAS_ARM64 + | (1 << CS_ARCH_ARM64) +#endif +#ifdef CAPSTONE_HAS_MIPS + | (1 << CS_ARCH_MIPS) +#endif +#ifdef CAPSTONE_HAS_X86 + | (1 << CS_ARCH_X86) +#endif +#ifdef CAPSTONE_HAS_POWERPC + | (1 << CS_ARCH_PPC) +#endif +#ifdef CAPSTONE_HAS_SPARC + | (1 << CS_ARCH_SPARC) +#endif +#ifdef CAPSTONE_HAS_SYSZ + | (1 << CS_ARCH_SYSZ) +#endif +#ifdef CAPSTONE_HAS_XCORE + | (1 << CS_ARCH_XCORE) +#endif +#ifdef CAPSTONE_HAS_M68K + | (1 << CS_ARCH_M68K) +#endif +#ifdef CAPSTONE_HAS_TMS320C64X + | (1 << CS_ARCH_TMS320C64X) +#endif +#ifdef CAPSTONE_HAS_M680X + | (1 << CS_ARCH_M680X) +#endif +#ifdef CAPSTONE_HAS_EVM + | (1 << CS_ARCH_EVM) +#endif +#ifdef CAPSTONE_HAS_MOS65XX + | (1 << CS_ARCH_MOS65XX) +#endif +; + + +#if defined(CAPSTONE_USE_SYS_DYN_MEM) +#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) +// default +cs_malloc_t cs_mem_malloc = malloc; +cs_calloc_t cs_mem_calloc = calloc; +cs_realloc_t cs_mem_realloc = realloc; +cs_free_t cs_mem_free = free; +#if defined(_WIN32_WCE) +cs_vsnprintf_t cs_vsnprintf = _vsnprintf; +#else +cs_vsnprintf_t cs_vsnprintf = vsnprintf; +#endif // defined(_WIN32_WCE) + +#elif defined(_KERNEL_MODE) +// Windows driver +cs_malloc_t cs_mem_malloc = cs_winkernel_malloc; +cs_calloc_t cs_mem_calloc = cs_winkernel_calloc; +cs_realloc_t cs_mem_realloc = cs_winkernel_realloc; +cs_free_t cs_mem_free = cs_winkernel_free; +cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf; +#else +// OSX kernel +extern void* kern_os_malloc(size_t size); +extern void kern_os_free(void* addr); +extern void* kern_os_realloc(void* addr, size_t nsize); + +static void* cs_kern_os_calloc(size_t num, size_t size) +{ + return kern_os_malloc(num * size); // malloc bzeroes the buffer +} + +cs_malloc_t cs_mem_malloc = kern_os_malloc; +cs_calloc_t cs_mem_calloc = cs_kern_os_calloc; +cs_realloc_t cs_mem_realloc = kern_os_realloc; +cs_free_t cs_mem_free = kern_os_free; +cs_vsnprintf_t cs_vsnprintf = vsnprintf; +#endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) +#else +// User-defined +cs_malloc_t cs_mem_malloc = NULL; +cs_calloc_t cs_mem_calloc = NULL; +cs_realloc_t cs_mem_realloc = NULL; +cs_free_t cs_mem_free = NULL; +cs_vsnprintf_t cs_vsnprintf = NULL; + +#endif // defined(CAPSTONE_USE_SYS_DYN_MEM) + +CAPSTONE_EXPORT +unsigned int CAPSTONE_API cs_version(int *major, int *minor) +{ + if (major != NULL && minor != NULL) { + *major = CS_API_MAJOR; + *minor = CS_API_MINOR; + } + + return (CS_API_MAJOR << 8) + CS_API_MINOR; +} + +CAPSTONE_EXPORT +bool CAPSTONE_API cs_support(int query) +{ + if (query == CS_ARCH_ALL) + return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) | + (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | + (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) | + (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) | + (1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) | + (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) | + (1 << CS_ARCH_MOS65XX)); + + if ((unsigned int)query < CS_ARCH_MAX) + return all_arch & (1 << query); + + if (query == CS_SUPPORT_DIET) { +#ifdef CAPSTONE_DIET + return true; +#else + return false; +#endif + } + + if (query == CS_SUPPORT_X86_REDUCE) { +#if defined(CAPSTONE_HAS_X86) && defined(CAPSTONE_X86_REDUCE) + return true; +#else + return false; +#endif + } + + // unsupported query + return false; +} + +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_errno(csh handle) +{ + struct cs_struct *ud; + if (!handle) + return CS_ERR_CSH; + + ud = (struct cs_struct *)(uintptr_t)handle; + + return ud->errnum; +} + +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_strerror(cs_err code) +{ + switch(code) { + default: + return "Unknown error code"; + case CS_ERR_OK: + return "OK (CS_ERR_OK)"; + case CS_ERR_MEM: + return "Out of memory (CS_ERR_MEM)"; + case CS_ERR_ARCH: + return "Invalid/unsupported architecture(CS_ERR_ARCH)"; + case CS_ERR_HANDLE: + return "Invalid handle (CS_ERR_HANDLE)"; + case CS_ERR_CSH: + return "Invalid csh (CS_ERR_CSH)"; + case CS_ERR_MODE: + return "Invalid mode (CS_ERR_MODE)"; + case CS_ERR_OPTION: + return "Invalid option (CS_ERR_OPTION)"; + case CS_ERR_DETAIL: + return "Details are unavailable (CS_ERR_DETAIL)"; + case CS_ERR_MEMSETUP: + return "Dynamic memory management uninitialized (CS_ERR_MEMSETUP)"; + case CS_ERR_VERSION: + return "Different API version between core & binding (CS_ERR_VERSION)"; + case CS_ERR_DIET: + return "Information irrelevant in diet engine (CS_ERR_DIET)"; + case CS_ERR_SKIPDATA: + return "Information irrelevant for 'data' instruction in SKIPDATA mode (CS_ERR_SKIPDATA)"; + case CS_ERR_X86_ATT: + return "AT&T syntax is unavailable (CS_ERR_X86_ATT)"; + case CS_ERR_X86_INTEL: + return "INTEL syntax is unavailable (CS_ERR_X86_INTEL)"; + case CS_ERR_X86_MASM: + return "MASM syntax is unavailable (CS_ERR_X86_MASM)"; + } +} + +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle) +{ + cs_err err; + struct cs_struct *ud; + if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf) + // Error: before cs_open(), dynamic memory management must be initialized + // with cs_option(CS_OPT_MEM) + return CS_ERR_MEMSETUP; + + if (arch < CS_ARCH_MAX && cs_arch_init[arch]) { + // verify if requested mode is valid + if (mode & cs_arch_disallowed_mode_mask[arch]) { + *handle = 0; + return CS_ERR_MODE; + } + + ud = cs_mem_calloc(1, sizeof(*ud)); + if (!ud) { + // memory insufficient + return CS_ERR_MEM; + } + + ud->errnum = CS_ERR_OK; + ud->arch = arch; + ud->mode = mode; + // by default, do not break instruction into details + ud->detail = CS_OPT_OFF; + + // default skipdata setup + ud->skipdata_setup.mnemonic = SKIPDATA_MNEM; + + err = cs_arch_init[ud->arch](ud); + if (err) { + cs_mem_free(ud); + *handle = 0; + return err; + } + + *handle = (uintptr_t)ud; + + return CS_ERR_OK; + } else { + *handle = 0; + return CS_ERR_ARCH; + } +} + +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_close(csh *handle) +{ + struct cs_struct *ud; + struct insn_mnem *next, *tmp; + + if (*handle == 0) + // invalid handle + return CS_ERR_CSH; + + ud = (struct cs_struct *)(*handle); + + if (ud->printer_info) + cs_mem_free(ud->printer_info); + + // free the linked list of customized mnemonic + tmp = ud->mnem_list; + while(tmp) { + next = tmp->next; + cs_mem_free(tmp); + tmp = next; + } + + cs_mem_free(ud->insn_cache); + + memset(ud, 0, sizeof(*ud)); + cs_mem_free(ud); + + // invalidate this handle by ZERO out its value. + // this is to make sure it is unusable after cs_close() + *handle = 0; + + return CS_ERR_OK; +} + +// fill insn with mnemonic & operands info +static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci, + PostPrinter_t postprinter, const uint8_t *code) +{ +#ifndef CAPSTONE_DIET + char *sp, *mnem; +#endif + uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size); + + // fill the instruction bytes. + // we might skip some redundant bytes in front in the case of X86 + memcpy(insn->bytes, code + insn->size - copy_size, copy_size); + insn->size = copy_size; + + // alias instruction might have ID saved in OpcodePub + if (MCInst_getOpcodePub(mci)) + insn->id = MCInst_getOpcodePub(mci); + + // post printer handles some corner cases (hacky) + if (postprinter) + postprinter((csh)handle, insn, buffer, mci); + +#ifndef CAPSTONE_DIET + // fill in mnemonic & operands + // find first space or tab + mnem = insn->mnemonic; + for (sp = buffer; *sp; sp++) { + if (*sp == ' '|| *sp == '\t') + break; + if (*sp == '|') // lock|rep prefix for x86 + *sp = ' '; + // copy to @mnemonic + *mnem = *sp; + mnem++; + } + + *mnem = '\0'; + + // we might have customized mnemonic + if (handle->mnem_list) { + struct insn_mnem *tmp = handle->mnem_list; + while(tmp) { + if (tmp->insn.id == insn->id) { + // found this instruction, so copy its mnemonic + (void)strncpy(insn->mnemonic, tmp->insn.mnemonic, sizeof(insn->mnemonic) - 1); + insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0'; + break; + } + tmp = tmp->next; + } + } + + // copy @op_str + if (*sp) { + // find the next non-space char + sp++; + for (; ((*sp == ' ') || (*sp == '\t')); sp++); + strncpy(insn->op_str, sp, sizeof(insn->op_str) - 1); + insn->op_str[sizeof(insn->op_str) - 1] = '\0'; + } else + insn->op_str[0] = '\0'; +#endif +} + +// how many bytes will we skip when encountering data (CS_OPT_SKIPDATA)? +// this very much depends on instruction alignment requirement of each arch. +static uint8_t skipdata_size(cs_struct *handle) +{ + switch(handle->arch) { + default: + // should never reach + return (uint8_t)-1; + case CS_ARCH_ARM: + // skip 2 bytes on Thumb mode. + if (handle->mode & CS_MODE_THUMB) + return 2; + // otherwise, skip 4 bytes + return 4; + case CS_ARCH_ARM64: + case CS_ARCH_MIPS: + case CS_ARCH_PPC: + case CS_ARCH_SPARC: + // skip 4 bytes + return 4; + case CS_ARCH_SYSZ: + // SystemZ instruction's length can be 2, 4 or 6 bytes, + // so we just skip 2 bytes + return 2; + case CS_ARCH_X86: + // X86 has no restriction on instruction alignment + return 1; + case CS_ARCH_XCORE: + // XCore instruction's length can be 2 or 4 bytes, + // so we just skip 2 bytes + return 2; + case CS_ARCH_M68K: + // M68K has 2 bytes instruction alignment but contain multibyte instruction so we skip 2 bytes + return 2; + case CS_ARCH_TMS320C64X: + // TMS320C64x alignment is 4. + return 4; + case CS_ARCH_M680X: + // M680X alignment is 1. + return 1; + case CS_ARCH_EVM: + // EVM alignment is 1. + return 1; + case CS_ARCH_MOS65XX: + // MOS65XX alignment is 1. + return 1; + } +} + +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value) +{ + struct cs_struct *handle; + cs_opt_mnem *opt; + + // cs_option() can be called with NULL handle just for CS_OPT_MEM + // This is supposed to be executed before all other APIs (even cs_open()) + if (type == CS_OPT_MEM) { + cs_opt_mem *mem = (cs_opt_mem *)value; + + cs_mem_malloc = mem->malloc; + cs_mem_calloc = mem->calloc; + cs_mem_realloc = mem->realloc; + cs_mem_free = mem->free; + cs_vsnprintf = mem->vsnprintf; + + return CS_ERR_OK; + } + + handle = (struct cs_struct *)(uintptr_t)ud; + if (!handle) + return CS_ERR_CSH; + + switch(type) { + default: + break; + + case CS_OPT_UNSIGNED: + handle->imm_unsigned = (cs_opt_value)value; + return CS_ERR_OK; + + case CS_OPT_DETAIL: + handle->detail = (cs_opt_value)value; + return CS_ERR_OK; + + case CS_OPT_SKIPDATA: + handle->skipdata = (value == CS_OPT_ON); + if (handle->skipdata) { + if (handle->skipdata_size == 0) { + // set the default skipdata size + handle->skipdata_size = skipdata_size(handle); + } + } + return CS_ERR_OK; + + case CS_OPT_SKIPDATA_SETUP: + if (value) + handle->skipdata_setup = *((cs_opt_skipdata *)value); + return CS_ERR_OK; + + case CS_OPT_MNEMONIC: + opt = (cs_opt_mnem *)value; + if (opt->id) { + if (opt->mnemonic) { + struct insn_mnem *tmp; + + // add new instruction, or replace existing instruction + // 1. find if we already had this insn in the linked list + tmp = handle->mnem_list; + while(tmp) { + if (tmp->insn.id == opt->id) { + // found this instruction, so replace its mnemonic + (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); + tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; + break; + } + tmp = tmp->next; + } + + // 2. add this instruction if we have not had it yet + if (!tmp) { + tmp = cs_mem_malloc(sizeof(*tmp)); + tmp->insn.id = opt->id; + (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); + tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; + // this new instruction is heading the list + tmp->next = handle->mnem_list; + handle->mnem_list = tmp; + } + return CS_ERR_OK; + } else { + struct insn_mnem *prev, *tmp; + + // we want to delete an existing instruction + // iterate the list to find the instruction to remove it + tmp = handle->mnem_list; + prev = tmp; + while(tmp) { + if (tmp->insn.id == opt->id) { + // delete this instruction + if (tmp == prev) { + // head of the list + handle->mnem_list = tmp->next; + } else { + prev->next = tmp->next; + } + cs_mem_free(tmp); + break; + } + prev = tmp; + tmp = tmp->next; + } + } + } + return CS_ERR_OK; + + case CS_OPT_MODE: + // verify if requested mode is valid + if (value & cs_arch_disallowed_mode_mask[handle->arch]) { + return CS_ERR_OPTION; + } + break; + } + + return cs_arch_option[handle->arch](handle, type, value); +} + +// generate @op_str for data instruction of SKIPDATA +#ifndef CAPSTONE_DIET +static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) +{ + char *p = opstr; + int len; + size_t i; + size_t available = sizeof(((cs_insn*)NULL)->op_str); + + if (!size) { + opstr[0] = '\0'; + return; + } + + len = cs_snprintf(p, available, "0x%02x", buffer[0]); + p+= len; + available -= len; + + for(i = 1; i < size; i++) { + len = cs_snprintf(p, available, ", 0x%02x", buffer[i]); + if (len < 0) { + break; + } + if ((size_t)len > available - 1) { + break; + } + p+= len; + available -= len; + } +} +#endif + +// dynamicly allocate memory to contain disasm insn +// NOTE: caller must free() the allocated memory itself to avoid memory leaking +CAPSTONE_EXPORT +size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) +{ + struct cs_struct *handle; + MCInst mci; + uint16_t insn_size; + size_t c = 0, i; + unsigned int f = 0; // index of the next instruction in the cache + cs_insn *insn_cache; // cache contains disassembled instructions + void *total = NULL; + size_t total_size = 0; // total size of output buffer containing all insns + bool r; + void *tmp; + size_t skipdata_bytes; + uint64_t offset_org; // save all the original info of the buffer + size_t size_org; + const uint8_t *buffer_org; + unsigned int cache_size = INSN_CACHE_SIZE; + size_t next_offset; + + handle = (struct cs_struct *)(uintptr_t)ud; + if (!handle) { + // FIXME: how to handle this case: + // handle->errnum = CS_ERR_HANDLE; + return 0; + } + + handle->errnum = CS_ERR_OK; + + // reset IT block of ARM structure + if (handle->arch == CS_ARCH_ARM) + handle->ITBlock.size = 0; + +#ifdef CAPSTONE_USE_SYS_DYN_MEM + if (count > 0 && count <= INSN_CACHE_SIZE) + cache_size = (unsigned int) count; +#endif + + // save the original offset for SKIPDATA + buffer_org = buffer; + offset_org = offset; + size_org = size; + + total_size = sizeof(cs_insn) * cache_size; + total = cs_mem_malloc(total_size); + if (total == NULL) { + // insufficient memory + handle->errnum = CS_ERR_MEM; + return 0; + } + + insn_cache = total; + + while (size > 0) { + MCInst_Init(&mci); + mci.csh = handle; + + // relative branches need to know the address & size of current insn + mci.address = offset; + + if (handle->detail) { + // allocate memory for @detail pointer + insn_cache->detail = cs_mem_malloc(sizeof(cs_detail)); + } else { + insn_cache->detail = NULL; + } + + // save all the information for non-detailed mode + mci.flat_insn = insn_cache; + mci.flat_insn->address = offset; +#ifdef CAPSTONE_DIET + // zero out mnemonic & op_str + mci.flat_insn->mnemonic[0] = '\0'; + mci.flat_insn->op_str[0] = '\0'; +#endif + + r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info); + if (r) { + SStream ss; + SStream_Init(&ss); + + mci.flat_insn->size = insn_size; + + // map internal instruction opcode to public insn ID + + handle->insn_id(handle, insn_cache, mci.Opcode); + + handle->printer(&mci, &ss, handle->printer_info); + fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); + + // adjust for pseudo opcode (X86) + if (handle->arch == CS_ARCH_X86) + insn_cache->id += mci.popcode_adjust; + + next_offset = insn_size; + } else { + // encounter a broken instruction + + // free memory of @detail pointer + if (handle->detail) { + cs_mem_free(insn_cache->detail); + } + + // if there is no request to skip data, or remaining data is too small, + // then bail out + if (!handle->skipdata || handle->skipdata_size > size) + break; + + if (handle->skipdata_setup.callback) { + skipdata_bytes = handle->skipdata_setup.callback(buffer_org, size_org, + (size_t)(offset - offset_org), handle->skipdata_setup.user_data); + if (skipdata_bytes > size) + // remaining data is not enough + break; + + if (!skipdata_bytes) + // user requested not to skip data, so bail out + break; + } else + skipdata_bytes = handle->skipdata_size; + + // we have to skip some amount of data, depending on arch & mode + insn_cache->id = 0; // invalid ID for this "data" instruction + insn_cache->address = offset; + insn_cache->size = (uint16_t)skipdata_bytes; + memcpy(insn_cache->bytes, buffer, skipdata_bytes); +#ifdef CAPSTONE_DIET + insn_cache->mnemonic[0] = '\0'; + insn_cache->op_str[0] = '\0'; +#else + strncpy(insn_cache->mnemonic, handle->skipdata_setup.mnemonic, + sizeof(insn_cache->mnemonic) - 1); + skipdata_opstr(insn_cache->op_str, buffer, skipdata_bytes); +#endif + insn_cache->detail = NULL; + + next_offset = skipdata_bytes; + } + + // one more instruction entering the cache + f++; + + // one more instruction disassembled + c++; + if (count > 0 && c == count) + // already got requested number of instructions + break; + + if (f == cache_size) { + // full cache, so expand the cache to contain incoming insns + cache_size = cache_size * 8 / 5; // * 1.6 ~ golden ratio + total_size += (sizeof(cs_insn) * cache_size); + tmp = cs_mem_realloc(total, total_size); + if (tmp == NULL) { // insufficient memory + if (handle->detail) { + insn_cache = (cs_insn *)total; + for (i = 0; i < c; i++, insn_cache++) + cs_mem_free(insn_cache->detail); + } + + cs_mem_free(total); + *insn = NULL; + handle->errnum = CS_ERR_MEM; + return 0; + } + + total = tmp; + // continue to fill in the cache after the last instruction + insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c); + + // reset f back to 0, so we fill in the cache from begining + f = 0; + } else + insn_cache++; + + buffer += next_offset; + size -= next_offset; + offset += next_offset; + } + + if (!c) { + // we did not disassemble any instruction + cs_mem_free(total); + total = NULL; + } else if (f != cache_size) { + // total did not fully use the last cache, so downsize it + tmp = cs_mem_realloc(total, total_size - (cache_size - f) * sizeof(*insn_cache)); + if (tmp == NULL) { // insufficient memory + // free all detail pointers + if (handle->detail) { + insn_cache = (cs_insn *)total; + for (i = 0; i < c; i++, insn_cache++) + cs_mem_free(insn_cache->detail); + } + + cs_mem_free(total); + *insn = NULL; + + handle->errnum = CS_ERR_MEM; + return 0; + } + + total = tmp; + } + + *insn = total; + + return c; +} + +CAPSTONE_EXPORT +CAPSTONE_DEPRECATED +size_t CAPSTONE_API cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) +{ + return cs_disasm(ud, buffer, size, offset, count, insn); +} + +CAPSTONE_EXPORT +void CAPSTONE_API cs_free(cs_insn *insn, size_t count) +{ + size_t i; + + // free all detail pointers + for (i = 0; i < count; i++) + cs_mem_free(insn[i].detail); + + // then free pointer to cs_insn array + cs_mem_free(insn); +} + +CAPSTONE_EXPORT +cs_insn * CAPSTONE_API cs_malloc(csh ud) +{ + cs_insn *insn; + struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; + + insn = cs_mem_malloc(sizeof(cs_insn)); + if (!insn) { + // insufficient memory + handle->errnum = CS_ERR_MEM; + return NULL; + } else { + if (handle->detail) { + // allocate memory for @detail pointer + insn->detail = cs_mem_malloc(sizeof(cs_detail)); + if (insn->detail == NULL) { // insufficient memory + cs_mem_free(insn); + handle->errnum = CS_ERR_MEM; + return NULL; + } + } else + insn->detail = NULL; + } + + return insn; +} + +// iterator for instruction "single-stepping" +CAPSTONE_EXPORT +bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, + uint64_t *address, cs_insn *insn) +{ + struct cs_struct *handle; + uint16_t insn_size; + MCInst mci; + bool r; + + handle = (struct cs_struct *)(uintptr_t)ud; + if (!handle) { + return false; + } + + handle->errnum = CS_ERR_OK; + + MCInst_Init(&mci); + mci.csh = handle; + + // relative branches need to know the address & size of current insn + mci.address = *address; + + // save all the information for non-detailed mode + mci.flat_insn = insn; + mci.flat_insn->address = *address; +#ifdef CAPSTONE_DIET + // zero out mnemonic & op_str + mci.flat_insn->mnemonic[0] = '\0'; + mci.flat_insn->op_str[0] = '\0'; +#endif + + r = handle->disasm(ud, *code, *size, &mci, &insn_size, *address, handle->getinsn_info); + if (r) { + SStream ss; + SStream_Init(&ss); + + mci.flat_insn->size = insn_size; + + // map internal instruction opcode to public insn ID + handle->insn_id(handle, insn, mci.Opcode); + + handle->printer(&mci, &ss, handle->printer_info); + + fill_insn(handle, insn, ss.buffer, &mci, handle->post_printer, *code); + + // adjust for pseudo opcode (X86) + if (handle->arch == CS_ARCH_X86) + insn->id += mci.popcode_adjust; + + *code += insn_size; + *size -= insn_size; + *address += insn_size; + } else { // encounter a broken instruction + size_t skipdata_bytes; + + // if there is no request to skip data, or remaining data is too small, + // then bail out + if (!handle->skipdata || handle->skipdata_size > *size) + return false; + + if (handle->skipdata_setup.callback) { + skipdata_bytes = handle->skipdata_setup.callback(*code, *size, + 0, handle->skipdata_setup.user_data); + if (skipdata_bytes > *size) + // remaining data is not enough + return false; + + if (!skipdata_bytes) + // user requested not to skip data, so bail out + return false; + } else + skipdata_bytes = handle->skipdata_size; + + // we have to skip some amount of data, depending on arch & mode + insn->id = 0; // invalid ID for this "data" instruction + insn->address = *address; + insn->size = (uint16_t)skipdata_bytes; +#ifdef CAPSTONE_DIET + insn->mnemonic[0] = '\0'; + insn->op_str[0] = '\0'; +#else + memcpy(insn->bytes, *code, skipdata_bytes); + strncpy(insn->mnemonic, handle->skipdata_setup.mnemonic, + sizeof(insn->mnemonic) - 1); + skipdata_opstr(insn->op_str, *code, skipdata_bytes); +#endif + + *code += skipdata_bytes; + *size -= skipdata_bytes; + *address += skipdata_bytes; + } + + return true; +} + +// return friendly name of regiser in a string +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_reg_name(csh ud, unsigned int reg) +{ + struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle || handle->reg_name == NULL) { + return NULL; + } + + return handle->reg_name(ud, reg); +} + +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_insn_name(csh ud, unsigned int insn) +{ + struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle || handle->insn_name == NULL) { + return NULL; + } + + return handle->insn_name(ud, insn); +} + +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_group_name(csh ud, unsigned int group) +{ + struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle || handle->group_name == NULL) { + return NULL; + } + + return handle->group_name(ud, group); +} + +CAPSTONE_EXPORT +bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_id) +{ + struct cs_struct *handle; + if (!ud) + return false; + + handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return false; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + return arr_exist8(insn->detail->groups, insn->detail->groups_count, group_id); +} + +CAPSTONE_EXPORT +bool CAPSTONE_API cs_reg_read(csh ud, const cs_insn *insn, unsigned int reg_id) +{ + struct cs_struct *handle; + if (!ud) + return false; + + handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return false; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + return arr_exist(insn->detail->regs_read, insn->detail->regs_read_count, reg_id); +} + +CAPSTONE_EXPORT +bool CAPSTONE_API cs_reg_write(csh ud, const cs_insn *insn, unsigned int reg_id) +{ + struct cs_struct *handle; + if (!ud) + return false; + + handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return false; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return false; + } + + return arr_exist(insn->detail->regs_write, insn->detail->regs_write_count, reg_id); +} + +CAPSTONE_EXPORT +int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) +{ + struct cs_struct *handle; + unsigned int count = 0, i; + if (!ud) + return -1; + + handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return -1; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return -1; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return -1; + } + + handle->errnum = CS_ERR_OK; + + switch (handle->arch) { + default: + handle->errnum = CS_ERR_HANDLE; + return -1; + case CS_ARCH_ARM: + for (i = 0; i < insn->detail->arm.op_count; i++) + if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) + count++; + break; + case CS_ARCH_ARM64: + for (i = 0; i < insn->detail->arm64.op_count; i++) + if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) + count++; + break; + case CS_ARCH_X86: + for (i = 0; i < insn->detail->x86.op_count; i++) + if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) + count++; + break; + case CS_ARCH_MIPS: + for (i = 0; i < insn->detail->mips.op_count; i++) + if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) + count++; + break; + case CS_ARCH_PPC: + for (i = 0; i < insn->detail->ppc.op_count; i++) + if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) + count++; + break; + case CS_ARCH_SPARC: + for (i = 0; i < insn->detail->sparc.op_count; i++) + if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) + count++; + break; + case CS_ARCH_SYSZ: + for (i = 0; i < insn->detail->sysz.op_count; i++) + if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) + count++; + break; + case CS_ARCH_XCORE: + for (i = 0; i < insn->detail->xcore.op_count; i++) + if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) + count++; + break; + case CS_ARCH_M68K: + for (i = 0; i < insn->detail->m68k.op_count; i++) + if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) + count++; + break; + case CS_ARCH_TMS320C64X: + for (i = 0; i < insn->detail->tms320c64x.op_count; i++) + if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) + count++; + break; + case CS_ARCH_M680X: + for (i = 0; i < insn->detail->m680x.op_count; i++) + if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) + count++; + break; + case CS_ARCH_EVM: +#if 0 + for (i = 0; i < insn->detail->evm.op_count; i++) + if (insn->detail->evm.operands[i].type == (evm_op_type)op_type) + count++; +#endif + break; + case CS_ARCH_MOS65XX: + for (i = 0; i < insn->detail->mos65xx.op_count; i++) + if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type) + count++; + break; + } + + return count; +} + +CAPSTONE_EXPORT +int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, + unsigned int post) +{ + struct cs_struct *handle; + unsigned int count = 0, i; + if (!ud) + return -1; + + handle = (struct cs_struct *)(uintptr_t)ud; + + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return -1; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return -1; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return -1; + } + + handle->errnum = CS_ERR_OK; + + switch (handle->arch) { + default: + handle->errnum = CS_ERR_HANDLE; + return -1; + case CS_ARCH_ARM: + for (i = 0; i < insn->detail->arm.op_count; i++) { + if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_ARM64: + for (i = 0; i < insn->detail->arm64.op_count; i++) { + if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_X86: + for (i = 0; i < insn->detail->x86.op_count; i++) { + if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_MIPS: + for (i = 0; i < insn->detail->mips.op_count; i++) { + if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_PPC: + for (i = 0; i < insn->detail->ppc.op_count; i++) { + if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_SPARC: + for (i = 0; i < insn->detail->sparc.op_count; i++) { + if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_SYSZ: + for (i = 0; i < insn->detail->sysz.op_count; i++) { + if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_XCORE: + for (i = 0; i < insn->detail->xcore.op_count; i++) { + if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_M68K: + for (i = 0; i < insn->detail->m68k.op_count; i++) { + if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_TMS320C64X: + for (i = 0; i < insn->detail->tms320c64x.op_count; i++) { + if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_M680X: + for (i = 0; i < insn->detail->m680x.op_count; i++) { + if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + case CS_ARCH_EVM: +#if 0 + for (i = 0; i < insn->detail->evm.op_count; i++) { + if (insn->detail->evm.operands[i].type == (evm_op_type)op_type) + count++; + if (count == post) + return i; + } +#endif + break; + case CS_ARCH_MOS65XX: + for (i = 0; i < insn->detail->mos65xx.op_count; i++) { + if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type) + count++; + if (count == post) + return i; + } + break; + } + + return -1; +} + +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + struct cs_struct *handle; + + if (!ud) + return -1; + + handle = (struct cs_struct *)(uintptr_t)ud; + +#ifdef CAPSTONE_DIET + // This API does not work in DIET mode + handle->errnum = CS_ERR_DIET; + return CS_ERR_DIET; +#else + if (!handle->detail) { + handle->errnum = CS_ERR_DETAIL; + return CS_ERR_DETAIL; + } + + if (!insn->id) { + handle->errnum = CS_ERR_SKIPDATA; + return CS_ERR_SKIPDATA; + } + + if (!insn->detail) { + handle->errnum = CS_ERR_DETAIL; + return CS_ERR_DETAIL; + } + + if (handle->reg_access) { + handle->reg_access(insn, regs_read, regs_read_count, regs_write, regs_write_count); + } else { + // this arch is unsupported yet + handle->errnum = CS_ERR_ARCH; + return CS_ERR_ARCH; + } + + return CS_ERR_OK; +#endif +} diff --git a/white_patch_detect/capstone-master/cs_priv.h b/white_patch_detect/capstone-master/cs_priv.h new file mode 100644 index 0000000..2e6c88f --- /dev/null +++ b/white_patch_detect/capstone-master/cs_priv.h @@ -0,0 +1,89 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_PRIV_H +#define CS_PRIV_H + +#include + +#include "MCInst.h" +#include "SStream.h" + +typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info); + +// function to be called after Printer_t +// this is the best time to gather insn's characteristics +typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci); + +typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); + +typedef const char *(*GetName_t)(csh handle, unsigned int id); + +typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id); + +// return register name, given register ID +typedef const char *(*GetRegisterName_t)(unsigned RegNo); + +// return registers accessed by instruction +typedef void (*GetRegisterAccess_t)(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +// for ARM only +typedef struct ARM_ITStatus { + unsigned char ITStates[8]; + unsigned int size; +} ARM_ITStatus; + +// Customize mnemonic for instructions with alternative name. +struct customized_mnem { + // ID of instruction to be customized. + unsigned int id; + // Customized instruction mnemonic. + char mnemonic[CS_MNEMONIC_SIZE]; +}; + +struct insn_mnem { + struct customized_mnem insn; + struct insn_mnem *next; // linked list of customized mnemonics +}; + +struct cs_struct { + cs_arch arch; + cs_mode mode; + Printer_t printer; // asm printer + void *printer_info; // aux info for printer + Disasm_t disasm; // disassembler + void *getinsn_info; // auxiliary info for printer + GetName_t reg_name; + GetName_t insn_name; + GetName_t group_name; + GetID_t insn_id; + PostPrinter_t post_printer; + cs_err errnum; + ARM_ITStatus ITBlock; // for Arm only + cs_opt_value detail, imm_unsigned; + int syntax; // asm syntax for simple printer such as ARM, Mips & PPC + bool doing_mem; // handling memory operand in InstPrinter code + unsigned short *insn_cache; // index caching for mapping.c + GetRegisterName_t get_regname; + bool skipdata; // set this to True if we skip data when disassembling + uint8_t skipdata_size; // how many bytes to skip + cs_opt_skipdata skipdata_setup; // user-defined skipdata setup + const uint8_t *regsize_map; // map to register size (x86-only for now) + GetRegisterAccess_t reg_access; + struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic +}; + +#define MAX_ARCH CS_ARCH_MAX + +// Returns a bool (0 or 1) whether big endian is enabled for a mode +#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0) + +extern cs_malloc_t cs_mem_malloc; +extern cs_calloc_t cs_mem_calloc; +extern cs_realloc_t cs_mem_realloc; +extern cs_free_t cs_mem_free; +extern cs_vsnprintf_t cs_vsnprintf; + +#endif diff --git a/white_patch_detect/capstone-master/cstool/Makefile b/white_patch_detect/capstone-master/cstool/Makefile new file mode 100644 index 0000000..5410fa3 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/Makefile @@ -0,0 +1,47 @@ +# Makefile for Cstool of Capstone Disassembly Engine + +include ../functions.mk + +.PHONY: clean all + +LIBNAME = capstone + +CFLAGS += -I../include -I. +LDFLAGS += -O3 -Wall -L.. -l$(LIBNAME) + +TARGET = cstool +SOURCES := $(wildcard *.c) +OBJECTS := $(SOURCES:.c=.o) + +LIBCAPSTONE = libcapstone.a + +IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) +ifeq ($(IS_CYGWIN),1) +LIBCAPSTONE = capstone.lib +else +IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) +ifeq ($(IS_MINGW),1) +LIBCAPSTONE = capstone.lib +endif +endif + +all: $(TARGET) + +$(TARGET): ../$(LIBCAPSTONE) $(OBJECTS) +ifeq ($(V),0) + $(call log,LINK,$@) + @${CC} $(OBJECTS) $(LDFLAGS) -o $@ +else + ${CC} $(OBJECTS) $(LDFLAGS) -o $@ +endif + +clean: + ${RM} -rf *.o $(TARGET) + +%.o: %.c +ifeq ($(V),0) + $(call log,CC,$@) + @${CC} $(CFLAGS) -c $< -o $@ +else + ${CC} $(CFLAGS) -c $< -o $@ +endif diff --git a/white_patch_detect/capstone-master/cstool/README b/white_patch_detect/capstone-master/cstool/README new file mode 100644 index 0000000..a6b0208 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/README @@ -0,0 +1,47 @@ +This directory contains cstool of Capstone Engine. + +Cstool is a command-line tool to disassemble assembly hex-string. +For example, to decode a hexcode string for Intel 32bit, run: + + $ cstool x32 "90 91" + + 0 90 nop + 1 91 xchg eax, ecx + +Cstool disassembles the input and prints out the assembly instructions. +On each line, the first column is the instruction offset, the second +column is opcodes, and the rest is the instruction itself. + +Cstool is flexible enough to accept all kind of hexcode format. The following +inputs have the same output with the example above. + + $ cstool x32 "0x90 0x91" + $ cstool x32 "\x90\x91" + $ cstool x32 "90,91" + $ cstool x32 "90;91" + $ cstool x32 "90+91" + $ cstool x32 "90:91" + +To print out instruction details, run Cstool with -d option, like below. + + $ cstool -d x32 "01 d8" + 0 01d8 add eax, ebx + Prefix:0x00 0x00 0x00 0x00 + Opcode:0x01 0x00 0x00 0x00 + rex: 0x0 + addr_size: 4 + modrm: 0xd8 + disp: 0x0 + sib: 0x0 + op_count: 2 + operands[0].type: REG = eax + operands[0].size: 4 + operands[0].access: READ | WRITE + operands[1].type: REG = ebx + operands[1].size: 4 + operands[1].access: READ + Registers read: eax ebx + Registers modified: eflags eax + EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF + +To see all the supported options, run ./cstool diff --git a/white_patch_detect/capstone-master/cstool/cstool.c b/white_patch_detect/capstone-master/cstool/cstool.c new file mode 100644 index 0000000..4834442 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool.c @@ -0,0 +1,487 @@ +/* Tang Yuhang 2016 */ +/* pancake 2017 */ + +#include +#include +#include +#include "getopt.h" + +#include + +static struct { + const char *name; + cs_arch arch; + cs_mode mode; +} all_archs[] = { + { "arm", CS_ARCH_ARM, CS_MODE_ARM }, + { "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, + { "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, + { "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, + { "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, + { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, + { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, + { "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, + { "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, + { "arm64", CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN }, + { "arm64be", CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN }, + { "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN }, + { "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, + { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN }, + { "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, + { "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 + { "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT + { "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 + { "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT + { "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 + { "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT + { "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, + { "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, + { "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, + { "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, + { "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, + { "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, + { "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, + { "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, + { "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, + { "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 }, + { "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 }, + { "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, + { "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 }, + { "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, + { "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 }, + { "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, + { "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 }, + { "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, + { "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, + { "evm", CS_ARCH_EVM, 0 }, + { "mos65xx", CS_ARCH_MOS65XX, 0 }, + { NULL } +}; + +void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins); +void print_insn_detail_arm(csh handle, cs_insn *ins); +void print_insn_detail_arm64(csh handle, cs_insn *ins); +void print_insn_detail_mips(csh handle, cs_insn *ins); +void print_insn_detail_ppc(csh handle, cs_insn *ins); +void print_insn_detail_sparc(csh handle, cs_insn *ins); +void print_insn_detail_sysz(csh handle, cs_insn *ins); +void print_insn_detail_xcore(csh handle, cs_insn *ins); +void print_insn_detail_m68k(csh handle, cs_insn *ins); +void print_insn_detail_tms320c64x(csh handle, cs_insn *ins); +void print_insn_detail_m680x(csh handle, cs_insn *ins); +void print_insn_detail_evm(csh handle, cs_insn *ins); +void print_insn_detail_mos65xx(csh handle, cs_insn *ins); + +static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins); + +void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +// convert hexchar to hexnum +static uint8_t char_to_hexnum(char c) +{ + if (c >= '0' && c <= '9') { + return (uint8_t)(c - '0'); + } + + if (c >= 'a' && c <= 'f') { + return (uint8_t)(10 + c - 'a'); + } + + // c >= 'A' && c <= 'F' + return (uint8_t)(10 + c - 'A'); +} + +// convert user input (char[]) to uint8_t[], each element of which is +// valid hexadecimal, and return actual length of uint8_t[] in @size. +static uint8_t *preprocess(char *code, size_t *size) +{ + size_t i = 0, j = 0; + uint8_t high, low; + uint8_t *result; + + if (strlen(code) == 0) + return NULL; + + result = (uint8_t *)malloc(strlen(code)); + if (result != NULL) { + while (code[i] != '\0') { + if (isxdigit(code[i]) && isxdigit(code[i+1])) { + high = 16 * char_to_hexnum(code[i]); + low = char_to_hexnum(code[i+1]); + result[j] = high + low; + i++; + j++; + } + i++; + } + *size = j; + } + + return result; +} + +static void usage(char *prog) +{ + printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); + printf("Syntax: %s [-u|-d|-s|-v] [start-address-in-hex-format]\n", prog); + printf("\nThe following options are supported:\n"); + + if (cs_support(CS_ARCH_X86)) { + printf(" x16 16-bit mode (X86)\n"); + printf(" x32 32-bit mode (X86)\n"); + printf(" x64 64-bit mode (X86)\n"); + printf(" x16att 16-bit mode (X86), syntax AT&T\n"); + printf(" x32att 32-bit mode (X86), syntax AT&T\n"); + printf(" x64att 64-bit mode (X86), syntax AT&T\n"); + } + + if (cs_support(CS_ARCH_ARM)) { + printf(" arm arm\n"); + printf(" armbe arm + big endian\n"); + printf(" thumb thumb mode\n"); + printf(" thumbbe thumb + big endian\n"); + printf(" cortexm thumb + cortex-m extensions\n"); + } + + if (cs_support(CS_ARCH_ARM64)) { + printf(" arm64 aarch64 mode\n"); + printf(" arm64be aarch64 + big endian\n"); + } + + if (cs_support(CS_ARCH_MIPS)) { + printf(" mips mips32 + little endian\n"); + printf(" mipsbe mips32 + big endian\n"); + printf(" mips64 mips64 + little endian\n"); + printf(" mips64be mips64 + big endian\n"); + } + + if (cs_support(CS_ARCH_PPC)) { + printf(" ppc64 ppc64 + little endian\n"); + printf(" ppc64be ppc64 + big endian\n"); + } + + if (cs_support(CS_ARCH_SPARC)) { + printf(" sparc sparc\n"); + } + + if (cs_support(CS_ARCH_SYSZ)) { + printf(" systemz systemz (s390x)\n"); + } + + if (cs_support(CS_ARCH_XCORE)) { + printf(" xcore xcore\n"); + } + + if (cs_support(CS_ARCH_M68K)) { + printf(" m68k m68k + big endian\n"); + printf(" m68k40 m68k_040\n"); + } + + if (cs_support(CS_ARCH_TMS320C64X)) { + printf(" tms320c64x TMS320C64x\n"); + } + + if (cs_support(CS_ARCH_M680X)) { + printf(" m6800 M6800/2\n"); + printf(" m6801 M6801/3\n"); + printf(" m6805 M6805\n"); + printf(" m6808 M68HC08\n"); + printf(" m6809 M6809\n"); + printf(" m6811 M68HC11\n"); + printf(" cpu12 M68HC12/HCS12\n"); + printf(" hd6301 HD6301/3\n"); + printf(" hd6309 HD6309\n"); + printf(" hcs08 HCS08\n"); + } + + if (cs_support(CS_ARCH_EVM)) { + printf(" evm Ethereum Virtual Machine\n"); + } + + if (cs_support(CS_ARCH_MOS65XX)) { + printf(" mos65xx MOS65XX family\n"); + } + + printf("\nExtra options:\n"); + printf(" -d show detailed information of the instructions\n"); + printf(" -u show immediates as unsigned\n"); + printf(" -s decode in SKIPDATA mode\n"); + printf(" -v show version & Capstone core build info\n\n"); +} + +static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) +{ + switch(arch) { + case CS_ARCH_X86: + print_insn_detail_x86(handle, md, ins); + break; + case CS_ARCH_ARM: + print_insn_detail_arm(handle, ins); + break; + case CS_ARCH_ARM64: + print_insn_detail_arm64(handle, ins); + break; + case CS_ARCH_MIPS: + print_insn_detail_mips(handle, ins); + break; + case CS_ARCH_PPC: + print_insn_detail_ppc(handle, ins); + break; + case CS_ARCH_SPARC: + print_insn_detail_sparc(handle, ins); + break; + case CS_ARCH_SYSZ: + print_insn_detail_sysz(handle, ins); + break; + case CS_ARCH_XCORE: + print_insn_detail_xcore(handle, ins); + break; + case CS_ARCH_M68K: + print_insn_detail_m68k(handle, ins); + break; + case CS_ARCH_TMS320C64X: + print_insn_detail_tms320c64x(handle, ins); + break; + case CS_ARCH_M680X: + print_insn_detail_m680x(handle, ins); + break; + case CS_ARCH_EVM: + print_insn_detail_evm(handle, ins); + break; + case CS_ARCH_MOS65XX: + print_insn_detail_mos65xx(handle, ins); + break; + default: break; + } + + if (ins->detail->groups_count) { + int j; + + printf("\tGroups: "); + for(j = 0; j < ins->detail->groups_count; j++) { + printf("%s ", cs_group_name(handle, ins->detail->groups[j])); + } + printf("\n"); + } + + printf("\n"); +} + +int main(int argc, char **argv) +{ + int i, c; + csh handle; + char *mode; + uint8_t *assembly; + size_t count, size; + uint64_t address = 0LL; + cs_insn *insn; + cs_err err; + cs_mode md; + cs_arch arch = CS_ARCH_ALL; + bool detail_flag = false; + bool unsigned_flag = false; + bool skipdata = false; + int args_left; + + while ((c = getopt (argc, argv, "sudhv")) != -1) { + switch (c) { + case 's': + skipdata = true; + break; + case 'u': + unsigned_flag = true; + break; + case 'd': + detail_flag = true; + break; + case 'v': + printf("cstool for Capstone Disassembler, v%u.%u.%u\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); + + printf("Capstone build: "); + if (cs_support(CS_ARCH_X86)) { + printf("x86=1 "); + } + + if (cs_support(CS_ARCH_ARM)) { + printf("arm=1 "); + } + + if (cs_support(CS_ARCH_ARM64)) { + printf("arm64=1 "); + } + + if (cs_support(CS_ARCH_MIPS)) { + printf("mips=1 "); + } + + if (cs_support(CS_ARCH_PPC)) { + printf("ppc=1 "); + } + + if (cs_support(CS_ARCH_SPARC)) { + printf("sparc=1 "); + } + + if (cs_support(CS_ARCH_SYSZ)) { + printf("sysz=1 "); + } + + if (cs_support(CS_ARCH_XCORE)) { + printf("xcore=1 "); + } + + if (cs_support(CS_ARCH_M68K)) { + printf("m68k=1 "); + } + + if (cs_support(CS_ARCH_TMS320C64X)) { + printf("tms320c64x=1 "); + } + + if (cs_support(CS_ARCH_M680X)) { + printf("m680x=1 "); + } + + if (cs_support(CS_ARCH_EVM)) { + printf("evm=1 "); + } + + if (cs_support(CS_ARCH_MOS65XX)) { + printf("mos65xx=1 "); + } + + if (cs_support(CS_SUPPORT_DIET)) { + printf("diet=1 "); + } + + if (cs_support(CS_SUPPORT_X86_REDUCE)) { + printf("x86_reduce=1 "); + } + + printf("\n"); + return 0; + case 'h': + usage(argv[0]); + return 0; + default: + usage(argv[0]); + return -1; + } + } + + args_left = argc - optind; + if (args_left < 2 || args_left > 3) { + usage(argv[0]); + return -1; + } + + mode = argv[optind]; + assembly = preprocess(argv[optind + 1], &size); + if (!assembly) { + usage(argv[0]); + return -1; + } + + if (args_left == 3) { + char *temp, *src = argv[optind + 2]; + address = strtoull(src, &temp, 16); + if (temp == src || *temp != '\0' || errno == ERANGE) { + printf("ERROR: invalid address argument, quit!\n"); + return -2; + } + } + + for (i = 0; all_archs[i].name; i++) { + if (!strcmp(all_archs[i].name, mode)) { + arch = all_archs[i].arch; + err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle); + if (!err) { + md = all_archs[i].mode; + if (strstr (mode, "att")) { + cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); + } + + // turn on SKIPDATA mode + if (skipdata) + cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON); + } + break; + } + } + + if (arch == CS_ARCH_ALL) { + printf("ERROR: Invalid : \"%s\", quit!\n", mode); + usage(argv[0]); + return -1; + } + + if (err) { + printf("ERROR: Failed on cs_open(), quit!\n"); + usage(argv[0]); + return -1; + } + + if (detail_flag) { + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + } + + if (unsigned_flag) { + cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON); + } + + count = cs_disasm(handle, assembly, size, address, 0, &insn); + if (count > 0) { + size_t i; + + for (i = 0; i < count; i++) { + int j; + + printf("%2"PRIx64" ", insn[i].address); + for (j = 0; j < insn[i].size; j++) { + if (j > 0) + putchar(' '); + printf("%02x", insn[i].bytes[j]); + } + // X86 and s390 instruction sizes are variable. + // align assembly instruction after the opcode + if (arch == CS_ARCH_X86) { + for (; j < 16; j++) { + printf(" "); + } + } else if (arch == CS_ARCH_SYSZ) { + for (; j < 6; j++) { + printf(" "); + } + } + + printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str); + + if (detail_flag) { + print_details(handle, arch, md, &insn[i]); + } + } + + cs_free(insn, count); + } else { + printf("ERROR: invalid assembly code\n"); + return(-4); + } + + cs_close(&handle); + free(assembly); + + return 0; +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_arm.c b/white_patch_detect/capstone-master/cstool/cstool_arm.c new file mode 100644 index 0000000..4fc719a --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_arm.c @@ -0,0 +1,156 @@ +#include +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_arm(csh handle, cs_insn *ins) +{ + cs_arm *arm; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + arm = &(ins->detail->arm); + + if (arm->op_count) + printf("\top_count: %u\n", arm->op_count); + + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch((int)op->type) { + default: + break; + case ARM_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case ARM_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case ARM_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + printf("\t\toperands[%u].type: FP = \n", i); +#else + printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); +#endif + break; + case ARM_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != ARM_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != ARM_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.scale != 1) + printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.lshift != 0) + printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift); + + break; + case ARM_OP_PIMM: + printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm); + break; + case ARM_OP_CIMM: + printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm); + break; + case ARM_OP_SETEND: + printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); + break; + case ARM_OP_SYSREG: + printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg); + break; + } + + if (op->neon_lane != -1) { + printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane); + } + + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + + if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { + if (op->shift.type < ARM_SFT_ASR_REG) + // shift with constant value + printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); + else + // shift with register + printf("\t\t\tShift: %u = %s\n", op->shift.type, + cs_reg_name(handle, op->shift.value)); + } + + if (op->vector_index != -1) { + printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index); + } + + if (op->subtracted) + printf("\t\tSubtracted: True\n"); + } + + if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) + printf("\tCode condition: %u\n", arm->cc); + + if (arm->update_flags) + printf("\tUpdate-flags: True\n"); + + if (arm->writeback) + printf("\tWrite-back: True\n"); + + if (arm->cps_mode) + printf("\tCPSI-mode: %u\n", arm->cps_mode); + + if (arm->cps_flag) + printf("\tCPSI-flag: %u\n", arm->cps_flag); + + if (arm->vector_data) + printf("\tVector-data: %u\n", arm->vector_data); + + if (arm->vector_size) + printf("\tVector-size: %u\n", arm->vector_size); + + if (arm->usermode) + printf("\tUser-mode: True\n"); + + if (arm->mem_barrier) + printf("\tMemory-barrier: %u\n", arm->mem_barrier); + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(handle, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(handle, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(handle, regs_write[i])); + } + printf("\n"); + } + } +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_arm64.c b/white_patch_detect/capstone-master/cstool/cstool_arm64.c new file mode 100644 index 0000000..f2c2620 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_arm64.c @@ -0,0 +1,141 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013> */ + +#include +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_arm64(csh handle, cs_insn *ins) +{ + cs_arm64 *arm64; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + uint8_t access; + + // detail can be NULL if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + arm64 = &(ins->detail->arm64); + if (arm64->op_count) + printf("\top_count: %u\n", arm64->op_count); + + for (i = 0; i < arm64->op_count; i++) { + cs_arm64_op *op = &(arm64->operands[i]); + switch(op->type) { + default: + break; + case ARM64_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case ARM64_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case ARM64_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + printf("\t\toperands[%u].type: FP = \n", i); +#else + printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); +#endif + break; + case ARM64_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != ARM64_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != ARM64_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + case ARM64_OP_CIMM: + printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm); + break; + case ARM64_OP_REG_MRS: + printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg); + break; + case ARM64_OP_REG_MSR: + printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg); + break; + case ARM64_OP_PSTATE: + printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->pstate); + break; + case ARM64_OP_SYS: + printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys); + break; + case ARM64_OP_PREFETCH: + printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->prefetch); + break; + case ARM64_OP_BARRIER: + printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->barrier); + break; + } + + access = op->access; + switch(access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + + if (op->shift.type != ARM64_SFT_INVALID && + op->shift.value) + printf("\t\t\tShift: type = %u, value = %u\n", + op->shift.type, op->shift.value); + + if (op->ext != ARM64_EXT_INVALID) + printf("\t\t\tExt: %u\n", op->ext); + + if (op->vas != ARM64_VAS_INVALID) + printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); + + if (op->vess != ARM64_VESS_INVALID) + printf("\t\t\tVector Element Size Specifier: %u\n", op->vess); + + if (op->vector_index != -1) + printf("\t\t\tVector Index: %u\n", op->vector_index); + } + + if (arm64->update_flags) + printf("\tUpdate-flags: True\n"); + + if (arm64->writeback) + printf("\tWrite-back: True\n"); + + if (arm64->cc) + printf("\tCode-condition: %u\n", arm64->cc); + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(handle, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(handle, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(handle, regs_write[i])); + } + printf("\n"); + } + } +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_evm.c b/white_patch_detect/capstone-master/cstool/cstool_evm.c new file mode 100644 index 0000000..692a3f0 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_evm.c @@ -0,0 +1,26 @@ +#include +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_evm(csh handle, cs_insn *ins) +{ + cs_evm *evm; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + evm = &(ins->detail->evm); + + if (evm->pop) + printf("\tPop: %u\n", evm->pop); + + if (evm->push) + printf("\tPush: %u\n", evm->push); + + if (evm->fee) + printf("\tGas fee: %u\n", evm->fee); +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_m680x.c b/white_patch_detect/capstone-master/cstool/cstool_m680x.c new file mode 100644 index 0000000..4a9a519 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_m680x.c @@ -0,0 +1,155 @@ +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#include +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +static const char *s_access[] = { + "UNCHANGED", "READ", "WRITE", "READ | WRITE", +}; + +void print_read_write_regs(csh handle, cs_detail *detail) +{ + int i; + + if (detail->regs_read_count > 0) { + printf("\treading from regs: "); + + for (i = 0; i < detail->regs_read_count; ++i) { + if (i > 0) + printf(", "); + + printf("%s", cs_reg_name(handle, detail->regs_read[i])); + } + + printf("\n"); + } + + if (detail->regs_write_count > 0) { + printf("\twriting to regs: "); + + for (i = 0; i < detail->regs_write_count; ++i) { + if (i > 0) + printf(", "); + + printf("%s", cs_reg_name(handle, + detail->regs_write[i])); + } + + printf("\n"); + } +} + +void print_insn_detail_m680x(csh handle, cs_insn *insn) +{ + cs_detail *detail = insn->detail; + cs_m680x *m680x = NULL; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is + // turned ON + if (detail == NULL) + return; + + m680x = &detail->m680x; + + if (m680x->op_count) + printf("\top_count: %u\n", m680x->op_count); + + for (i = 0; i < m680x->op_count; i++) { + cs_m680x_op *op = &(m680x->operands[i]); + const char *comment; + + switch ((int)op->type) { + default: + break; + + case M680X_OP_REGISTER: + comment = ""; + + if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) || + (i == 1 && m680x->flags & + M680X_SECOND_OP_IN_MNEM)) + comment = " (in mnemonic)"; + + printf("\t\toperands[%u].type: REGISTER = %s%s\n", i, + cs_reg_name(handle, op->reg), comment); + break; + + case M680X_OP_CONSTANT: + printf("\t\toperands[%u].type: CONSTANT = %u\n", i, + op->const_val); + break; + + case M680X_OP_IMMEDIATE: + printf("\t\toperands[%u].type: IMMEDIATE = #%d\n", i, + op->imm); + break; + + case M680X_OP_DIRECT: + printf("\t\toperands[%u].type: DIRECT = 0x%02X\n", i, + op->direct_addr); + break; + + case M680X_OP_EXTENDED: + printf("\t\toperands[%u].type: EXTENDED %s = 0x%04X\n", + i, op->ext.indirect ? "INDIRECT" : "", + op->ext.address); + break; + + case M680X_OP_RELATIVE: + printf("\t\toperands[%u].type: RELATIVE = 0x%04X\n", i, + op->rel.address); + break; + + case M680X_OP_INDEXED: + printf("\t\toperands[%u].type: INDEXED%s\n", i, + (op->idx.flags & M680X_IDX_INDIRECT) ? + " INDIRECT" : ""); + + if (op->idx.base_reg != M680X_REG_INVALID) + printf("\t\t\tbase register: %s\n", + cs_reg_name(handle, op->idx.base_reg)); + + if (op->idx.offset_reg != M680X_REG_INVALID) + printf("\t\t\toffset register: %s\n", + cs_reg_name(handle, op->idx.offset_reg)); + + if ((op->idx.offset_bits != 0) && + (op->idx.offset_reg == M680X_REG_INVALID) && + !op->idx.inc_dec) { + printf("\t\t\toffset: %d\n", op->idx.offset); + + if (op->idx.base_reg == M680X_REG_PC) + printf("\t\t\toffset address: 0x%X\n", + op->idx.offset_addr); + + printf("\t\t\toffset bits: %u\n", + op->idx.offset_bits); + } + + if (op->idx.inc_dec) { + const char *post_pre = op->idx.flags & + M680X_IDX_POST_INC_DEC ? "post" : "pre"; + const char *inc_dec = (op->idx.inc_dec > 0) ? + "increment" : "decrement"; + + printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, + abs(op->idx.inc_dec)); + } + + break; + } + + if (op->size != 0) + printf("\t\t\tsize: %u\n", op->size); + + if (op->access != CS_AC_INVALID) + printf("\t\t\taccess: %s\n", s_access[op->access]); + } + + print_read_write_regs(handle, detail); +} + diff --git a/white_patch_detect/capstone-master/cstool/cstool_m68k.c b/white_patch_detect/capstone-master/cstool/cstool_m68k.c new file mode 100644 index 0000000..9a0fc7f --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_m68k.c @@ -0,0 +1,121 @@ +// +// cstool_m68k.c +// +// +// Created by YUHANG TANG on 26/10/16. +// +// + +#include +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +static const char* s_addressing_modes[] = { + "", + + "Register Direct - Data", + "Register Direct - Address", + + "Register Indirect - Address", + "Register Indirect - Address with Postincrement", + "Register Indirect - Address with Predecrement", + "Register Indirect - Address with Displacement", + + "Address Register Indirect With Index - 8-bit displacement", + "Address Register Indirect With Index - Base displacement", + + "Memory indirect - Postindex", + "Memory indirect - Preindex", + + "Program Counter Indirect - with Displacement", + + "Program Counter Indirect with Index - with 8-Bit Displacement", + "Program Counter Indirect with Index - with Base Displacement", + + "Program Counter Memory Indirect - Postindexed", + "Program Counter Memory Indirect - Preindexed", + + "Absolute Data Addressing - Short", + "Absolute Data Addressing - Long", + "Immediate value", +}; + +static void print_read_write_regs(cs_detail* detail, csh handle) +{ + int i; + + for (i = 0; i < detail->regs_read_count; ++i) { + uint16_t reg_id = detail->regs_read[i]; + const char* reg_name = cs_reg_name(handle, reg_id); + printf("\treading from reg: %s\n", reg_name); + } + + for (i = 0; i < detail->regs_write_count; ++i) { + uint16_t reg_id = detail->regs_write[i]; + const char* reg_name = cs_reg_name(handle, reg_id); + printf("\twriting to reg: %s\n", reg_name); + } +} + +void print_insn_detail_m68k(csh handle, cs_insn *ins) +{ + cs_m68k* m68k; + cs_detail* detail; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + detail = ins->detail; + m68k = &detail->m68k; + if (m68k->op_count) + printf("\top_count: %u\n", m68k->op_count); + + print_read_write_regs(detail, handle); + + printf("\tgroups_count: %u\n", detail->groups_count); + + for (i = 0; i < m68k->op_count; i++) { + cs_m68k_op* op = &(m68k->operands[i]); + + switch((int)op->type) { + default: + break; + case M68K_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case M68K_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, (int)op->imm); + break; + case M68K_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base_reg != M68K_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base_reg)); + if (op->mem.index_reg != M68K_REG_INVALID) { + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index_reg)); + printf("\t\t\toperands[%u].mem.index: size = %c\n", + i, op->mem.index_size ? 'l' : 'w'); + } + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.scale != 0) + printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); + + printf("\t\taddress mode: %s\n", s_addressing_modes[op->address_mode]); + break; + case M68K_OP_FP_SINGLE: + printf("\t\toperands[%u].type: FP_SINGLE\n", i); + printf("\t\t\toperands[%u].simm: %f\n", i, op->simm); + break; + case M68K_OP_FP_DOUBLE: + printf("\t\toperands[%u].type: FP_DOUBLE\n", i); + printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm); + break; + } + } +} + diff --git a/white_patch_detect/capstone-master/cstool/cstool_mips.c b/white_patch_detect/capstone-master/cstool/cstool_mips.c new file mode 100644 index 0000000..1edf16e --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_mips.c @@ -0,0 +1,47 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013> */ + +#include +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_mips(csh handle, cs_insn *ins) +{ + int i; + cs_mips *mips; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + mips = &(ins->detail->mips); + if (mips->op_count) + printf("\top_count: %u\n", mips->op_count); + + for (i = 0; i < mips->op_count; i++) { + cs_mips_op *op = &(mips->operands[i]); + switch((int)op->type) { + default: + break; + case MIPS_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case MIPS_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case MIPS_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != MIPS_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + + break; + } + + } +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_mos65xx.c b/white_patch_detect/capstone-master/cstool/cstool_mos65xx.c new file mode 100644 index 0000000..6b29aaf --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_mos65xx.c @@ -0,0 +1,76 @@ +#include +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +static const char *get_am_name(mos65xx_address_mode mode) +{ + switch(mode) { + default: + case MOS65XX_AM_NONE: + return "No address mode"; + case MOS65XX_AM_IMP: + return "implied addressing (no addressing mode)"; + case MOS65XX_AM_ACC: + return "accumulator addressing"; + case MOS65XX_AM_ABS: + return "absolute addressing"; + case MOS65XX_AM_ZP: + return "zeropage addressing"; + case MOS65XX_AM_IMM: + return "8 Bit immediate value"; + case MOS65XX_AM_ABSX: + return "indexed absolute addressing by the X index register"; + case MOS65XX_AM_ABSY: + return "indexed absolute addressing by the Y index register"; + case MOS65XX_AM_INDX: + return "indexed indirect addressing by the X index register"; + case MOS65XX_AM_INDY: + return "indirect indexed addressing by the Y index register"; + case MOS65XX_AM_ZPX: + return "indexed zeropage addressing by the X index register"; + case MOS65XX_AM_ZPY: + return "indexed zeropage addressing by the Y index register"; + case MOS65XX_AM_REL: + return "relative addressing used by branches"; + case MOS65XX_AM_IND: + return "absolute indirect addressing"; + } +} + + +void print_insn_detail_mos65xx(csh handle, cs_insn *ins) +{ + int i; + cs_mos65xx *mos65xx; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + mos65xx = &(ins->detail->mos65xx); + printf("\taddress mode: %s\n", get_am_name(mos65xx->am)); + printf("\tmodifies flags: %s\n", mos65xx->modifies_flags ? "true": "false"); + + if (mos65xx->op_count) + printf("\top_count: %u\n", mos65xx->op_count); + + for (i = 0; i < mos65xx->op_count; i++) { + cs_mos65xx_op *op = &(mos65xx->operands[i]); + switch((int)op->type) { + default: + break; + case MOS65XX_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case MOS65XX_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case MOS65XX_OP_MEM: + printf("\t\toperands[%u].type: MEM = 0x%x\n", i, op->mem); + break; + } + } +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_ppc.c b/white_patch_detect/capstone-master/cstool/cstool_ppc.c new file mode 100644 index 0000000..d46c2ad --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_ppc.c @@ -0,0 +1,89 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013> */ + +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +static const char* get_bc_name(int bc) +{ + switch(bc) { + default: + case PPC_BC_INVALID: + return ("invalid"); + case PPC_BC_LT: + return ("lt"); + case PPC_BC_LE: + return ("le"); + case PPC_BC_EQ: + return ("eq"); + case PPC_BC_GE: + return ("ge"); + case PPC_BC_GT: + return ("gt"); + case PPC_BC_NE: + return ("ne"); + case PPC_BC_UN: + return ("un"); + case PPC_BC_NU: + return ("nu"); + case PPC_BC_SO: + return ("so"); + case PPC_BC_NS: + return ("ns"); + } +} + +void print_insn_detail_ppc(csh handle, cs_insn *ins) +{ + cs_ppc *ppc; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + ppc = &(ins->detail->ppc); + if (ppc->op_count) + printf("\top_count: %u\n", ppc->op_count); + + for (i = 0; i < ppc->op_count; i++) { + cs_ppc_op *op = &(ppc->operands[i]); + switch((int)op->type) { + default: + break; + case PPC_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case PPC_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%"PRIx64"\n", i, op->imm); + break; + case PPC_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != PPC_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + case PPC_OP_CRX: + printf("\t\toperands[%u].type: CRX\n", i); + printf("\t\t\toperands[%u].crx.scale: %d\n", i, op->crx.scale); + printf("\t\t\toperands[%u].crx.reg: %s\n", i, cs_reg_name(handle, op->crx.reg)); + printf("\t\t\toperands[%u].crx.cond: %s\n", i, get_bc_name(op->crx.cond)); + break; + } + } + + if (ppc->bc != 0) + printf("\tBranch code: %u\n", ppc->bc); + + if (ppc->bh != 0) + printf("\tBranch hint: %u\n", ppc->bh); + + if (ppc->update_cr0) + printf("\tUpdate-CR0: True\n"); +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_sparc.c b/white_patch_detect/capstone-master/cstool/cstool_sparc.c new file mode 100644 index 0000000..4d914be --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_sparc.c @@ -0,0 +1,54 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_sparc(csh handle, cs_insn *ins) +{ + cs_sparc *sparc; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + sparc = &(ins->detail->sparc); + if (sparc->op_count) + printf("\top_count: %u\n", sparc->op_count); + + for (i = 0; i < sparc->op_count; i++) { + cs_sparc_op *op = &(sparc->operands[i]); + switch((int)op->type) { + default: + break; + case SPARC_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case SPARC_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case SPARC_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + } + } + + if (sparc->cc != 0) + printf("\tCode condition: %u\n", sparc->cc); + + if (sparc->hint != 0) + printf("\tHint code: %u\n", sparc->hint); +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_systemz.c b/white_patch_detect/capstone-master/cstool/cstool_systemz.c new file mode 100644 index 0000000..1b6280a --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_systemz.c @@ -0,0 +1,56 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include + +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_sysz(csh handle, cs_insn *ins) +{ + cs_sysz *sysz; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + sysz = &(ins->detail->sysz); + if (sysz->op_count) + printf("\top_count: %u\n", sysz->op_count); + + for (i = 0; i < sysz->op_count; i++) { + cs_sysz_op *op = &(sysz->operands[i]); + switch((int)op->type) { + default: + break; + case SYSZ_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case SYSZ_OP_ACREG: + printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg); + break; + case SYSZ_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case SYSZ_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != SYSZ_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != SYSZ_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.length != 0) + printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + + break; + } + } + + if (sysz->cc != 0) + printf("\tCode condition: %u\n", sysz->cc); +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_tms320c64x.c b/white_patch_detect/capstone-master/cstool/cstool_tms320c64x.c new file mode 100644 index 0000000..daede36 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_tms320c64x.c @@ -0,0 +1,106 @@ +/* Capstone Disassembler Engine */ +/* By Fotis Loukos , 2017 */ + +#include +#include + +void print_string_hex(const char *comment, unsigned char *str, size_t len); + +void print_insn_detail_tms320c64x(csh handle, cs_insn *ins) +{ + cs_tms320c64x *tms320c64x; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + tms320c64x = &(ins->detail->tms320c64x); + if (tms320c64x->op_count) + printf("\top_count: %u\n", tms320c64x->op_count); + + for (i = 0; i < tms320c64x->op_count; i++) { + cs_tms320c64x_op *op = &(tms320c64x->operands[i]); + switch((int)op->type) { + default: + break; + case TMS320C64X_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case TMS320C64X_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case TMS320C64X_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != TMS320C64X_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + printf("\t\t\toperands[%u].mem.disptype: ", i); + if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { + printf("Invalid\n"); + printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); + } + if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { + printf("Constant\n"); + printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); + } + if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { + printf("Register\n"); + printf("\t\t\toperands[%u].mem.disp: %s\n", i, cs_reg_name(handle, op->mem.disp)); + } + printf("\t\t\toperands[%u].mem.unit: %u\n", i, op->mem.unit); + printf("\t\t\toperands[%u].mem.direction: ", i); + if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID) + printf("Invalid\n"); + if(op->mem.direction == TMS320C64X_MEM_DIR_FW) + printf("Forward\n"); + if(op->mem.direction == TMS320C64X_MEM_DIR_BW) + printf("Backward\n"); + printf("\t\t\toperands[%u].mem.modify: ", i); + if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID) + printf("Invalid\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_NO) + printf("No\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_PRE) + printf("Pre\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_POST) + printf("Post\n"); + printf("\t\t\toperands[%u].mem.scaled: %u\n", i, op->mem.scaled); + + break; + case TMS320C64X_OP_REGPAIR: + printf("\t\toperands[%u].type: REGPAIR = %s:%s\n", i, cs_reg_name(handle, op->reg + 1), cs_reg_name(handle, op->reg)); + break; + } + } + + printf("\tFunctional unit: "); + switch(tms320c64x->funit.unit) { + case TMS320C64X_FUNIT_D: + printf("D%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_L: + printf("L%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_M: + printf("M%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_S: + printf("S%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_NO: + printf("No Functional Unit\n"); + break; + default: + printf("Unknown (Unit %u, Side %u)\n", tms320c64x->funit.unit, tms320c64x->funit.side); + break; + } + if(tms320c64x->funit.crosspath == 1) + printf("\tCrosspath: 1\n"); + + if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID) + printf("\tCondition: [%c%s]\n", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(handle, tms320c64x->condition.reg)); + printf("\tParallel: %s\n", (tms320c64x->parallel == 1) ? "true" : "false"); + + printf("\n"); +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_x86.c b/white_patch_detect/capstone-master/cstool/cstool_x86.c new file mode 100644 index 0000000..ff3be36 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_x86.c @@ -0,0 +1,345 @@ +/* By Nguyen Anh Quynh , 2013> */ + +#include +#include + +#include + +void print_string_hex(const char *comment, unsigned char *str, size_t len); + +static const char *get_eflag_name(uint64_t flag) +{ + switch(flag) { + default: + return NULL; + case X86_EFLAGS_UNDEFINED_OF: + return "UNDEF_OF"; + case X86_EFLAGS_UNDEFINED_SF: + return "UNDEF_SF"; + case X86_EFLAGS_UNDEFINED_ZF: + return "UNDEF_ZF"; + case X86_EFLAGS_MODIFY_AF: + return "MOD_AF"; + case X86_EFLAGS_UNDEFINED_PF: + return "UNDEF_PF"; + case X86_EFLAGS_MODIFY_CF: + return "MOD_CF"; + case X86_EFLAGS_MODIFY_SF: + return "MOD_SF"; + case X86_EFLAGS_MODIFY_ZF: + return "MOD_ZF"; + case X86_EFLAGS_UNDEFINED_AF: + return "UNDEF_AF"; + case X86_EFLAGS_MODIFY_PF: + return "MOD_PF"; + case X86_EFLAGS_UNDEFINED_CF: + return "UNDEF_CF"; + case X86_EFLAGS_MODIFY_OF: + return "MOD_OF"; + case X86_EFLAGS_RESET_OF: + return "RESET_OF"; + case X86_EFLAGS_RESET_CF: + return "RESET_CF"; + case X86_EFLAGS_RESET_DF: + return "RESET_DF"; + case X86_EFLAGS_RESET_IF: + return "RESET_IF"; + case X86_EFLAGS_RESET_ZF: + return "RESET_ZF"; + case X86_EFLAGS_TEST_OF: + return "TEST_OF"; + case X86_EFLAGS_TEST_SF: + return "TEST_SF"; + case X86_EFLAGS_TEST_ZF: + return "TEST_ZF"; + case X86_EFLAGS_TEST_PF: + return "TEST_PF"; + case X86_EFLAGS_TEST_CF: + return "TEST_CF"; + case X86_EFLAGS_RESET_SF: + return "RESET_SF"; + case X86_EFLAGS_RESET_AF: + return "RESET_AF"; + case X86_EFLAGS_RESET_TF: + return "RESET_TF"; + case X86_EFLAGS_RESET_NT: + return "RESET_NT"; + case X86_EFLAGS_PRIOR_OF: + return "PRIOR_OF"; + case X86_EFLAGS_PRIOR_SF: + return "PRIOR_SF"; + case X86_EFLAGS_PRIOR_ZF: + return "PRIOR_ZF"; + case X86_EFLAGS_PRIOR_AF: + return "PRIOR_AF"; + case X86_EFLAGS_PRIOR_PF: + return "PRIOR_PF"; + case X86_EFLAGS_PRIOR_CF: + return "PRIOR_CF"; + case X86_EFLAGS_PRIOR_TF: + return "PRIOR_TF"; + case X86_EFLAGS_PRIOR_IF: + return "PRIOR_IF"; + case X86_EFLAGS_PRIOR_DF: + return "PRIOR_DF"; + case X86_EFLAGS_TEST_NT: + return "TEST_NT"; + case X86_EFLAGS_TEST_DF: + return "TEST_DF"; + case X86_EFLAGS_RESET_PF: + return "RESET_PF"; + case X86_EFLAGS_PRIOR_NT: + return "PRIOR_NT"; + case X86_EFLAGS_MODIFY_TF: + return "MOD_TF"; + case X86_EFLAGS_MODIFY_IF: + return "MOD_IF"; + case X86_EFLAGS_MODIFY_DF: + return "MOD_DF"; + case X86_EFLAGS_MODIFY_NT: + return "MOD_NT"; + case X86_EFLAGS_MODIFY_RF: + return "MOD_RF"; + case X86_EFLAGS_SET_CF: + return "SET_CF"; + case X86_EFLAGS_SET_DF: + return "SET_DF"; + case X86_EFLAGS_SET_IF: + return "SET_IF"; + case X86_EFLAGS_SET_OF: + return "SET_OF"; + case X86_EFLAGS_SET_SF: + return "SET_SF"; + case X86_EFLAGS_SET_ZF: + return "SET_ZF"; + case X86_EFLAGS_SET_AF: + return "SET_AF"; + case X86_EFLAGS_SET_PF: + return "SET_PF"; + case X86_EFLAGS_TEST_AF: + return "TEST_AF"; + case X86_EFLAGS_TEST_TF: + return "TEST_TF"; + case X86_EFLAGS_TEST_RF: + return "TEST_RF"; + case X86_EFLAGS_RESET_0F: + return "RESET_0F"; + case X86_EFLAGS_RESET_AC: + return "RESET_AC"; + } +} + +static const char *get_fpu_flag_name(uint64_t flag) +{ + switch (flag) { + default: + return NULL; + case X86_FPU_FLAGS_MODIFY_C0: + return "MOD_C0"; + case X86_FPU_FLAGS_MODIFY_C1: + return "MOD_C1"; + case X86_FPU_FLAGS_MODIFY_C2: + return "MOD_C2"; + case X86_FPU_FLAGS_MODIFY_C3: + return "MOD_C3"; + case X86_FPU_FLAGS_RESET_C0: + return "RESET_C0"; + case X86_FPU_FLAGS_RESET_C1: + return "RESET_C1"; + case X86_FPU_FLAGS_RESET_C2: + return "RESET_C2"; + case X86_FPU_FLAGS_RESET_C3: + return "RESET_C3"; + case X86_FPU_FLAGS_SET_C0: + return "SET_C0"; + case X86_FPU_FLAGS_SET_C1: + return "SET_C1"; + case X86_FPU_FLAGS_SET_C2: + return "SET_C2"; + case X86_FPU_FLAGS_SET_C3: + return "SET_C3"; + case X86_FPU_FLAGS_UNDEFINED_C0: + return "UNDEF_C0"; + case X86_FPU_FLAGS_UNDEFINED_C1: + return "UNDEF_C1"; + case X86_FPU_FLAGS_UNDEFINED_C2: + return "UNDEF_C2"; + case X86_FPU_FLAGS_UNDEFINED_C3: + return "UNDEF_C3"; + case X86_FPU_FLAGS_TEST_C0: + return "TEST_C0"; + case X86_FPU_FLAGS_TEST_C1: + return "TEST_C1"; + case X86_FPU_FLAGS_TEST_C2: + return "TEST_C2"; + case X86_FPU_FLAGS_TEST_C3: + return "TEST_C3"; + } +} + +void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins) +{ + int count, i; + cs_x86 *x86; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + x86 = &(ins->detail->x86); + + print_string_hex("\tPrefix:", x86->prefix, 4); + print_string_hex("\tOpcode:", x86->opcode, 4); + printf("\trex: 0x%x\n", x86->rex); + printf("\taddr_size: %u\n", x86->addr_size); + printf("\tmodrm: 0x%x\n", x86->modrm); + printf("\tdisp: 0x%" PRIx64 "\n", x86->disp); + + // SIB is not available in 16-bit mode + if ((mode & CS_MODE_16) == 0) { + printf("\tsib: 0x%x\n", x86->sib); + if (x86->sib_base != X86_REG_INVALID) + printf("\t\tsib_base: %s\n", cs_reg_name(ud, x86->sib_base)); + if (x86->sib_index != X86_REG_INVALID) + printf("\t\tsib_index: %s\n", cs_reg_name(ud, x86->sib_index)); + if (x86->sib_scale != 0) + printf("\t\tsib_scale: %d\n", x86->sib_scale); + } + + // XOP code condition + if (x86->xop_cc != X86_XOP_CC_INVALID) { + printf("\txop_cc: %u\n", x86->xop_cc); + } + + // SSE code condition + if (x86->sse_cc != X86_SSE_CC_INVALID) { + printf("\tsse_cc: %u\n", x86->sse_cc); + } + + // AVX code condition + if (x86->avx_cc != X86_AVX_CC_INVALID) { + printf("\tavx_cc: %u\n", x86->avx_cc); + } + + // AVX Suppress All Exception + if (x86->avx_sae) { + printf("\tavx_sae: %u\n", x86->avx_sae); + } + + // AVX Rounding Mode + if (x86->avx_rm != X86_AVX_RM_INVALID) { + printf("\tavx_rm: %u\n", x86->avx_rm); + } + + // Print out all immediate operands + count = cs_op_count(ud, ins, X86_OP_IMM); + if (count > 0) { + printf("\timm_count: %u\n", count); + for (i = 1; i < count + 1; i++) { + int index = cs_op_index(ud, ins, X86_OP_IMM, i); + printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm); + } + } + + if (x86->op_count) + printf("\top_count: %u\n", x86->op_count); + + // Print out all operands + for (i = 0; i < x86->op_count; i++) { + cs_x86_op *op = &(x86->operands[i]); + + switch((int)op->type) { + case X86_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(ud, op->reg)); + break; + case X86_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case X86_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.segment != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(ud, op->mem.segment)); + if (op->mem.base != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(ud, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(ud, op->mem.index)); + if (op->mem.scale != 1) + printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + break; + default: + break; + } + + // AVX broadcast type + if (op->avx_bcast != X86_AVX_BCAST_INVALID) + printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast); + + // AVX zero opmask {z} + if (op->avx_zero_opmask != false) + printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i); + + printf("\t\toperands[%u].size: %u\n", i, op->size); + + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + } + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(ud, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(ud, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(ud, regs_write[i])); + } + printf("\n"); + } + } + + if (x86->eflags || x86->fpu_flags) { + for(i = 0; i < ins->detail->groups_count; i++) { + if (ins->detail->groups[i] == X86_GRP_FPU) { + printf("\tFPU_FLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->fpu_flags & ((uint64_t)1 << i)) { + printf(" %s", get_fpu_flag_name((uint64_t)1 << i)); + } + printf("\n"); + break; + } + } + + if (i == ins->detail->groups_count) { + printf("\tEFLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->eflags & ((uint64_t)1 << i)) { + printf(" %s", get_eflag_name((uint64_t)1 << i)); + } + printf("\n"); + } + } +} diff --git a/white_patch_detect/capstone-master/cstool/cstool_xcore.c b/white_patch_detect/capstone-master/cstool/cstool_xcore.c new file mode 100644 index 0000000..cb377db --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/cstool_xcore.c @@ -0,0 +1,52 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include +#include + +void print_string_hex(char *comment, unsigned char *str, size_t len); + +void print_insn_detail_xcore(csh handle, cs_insn *ins) +{ + cs_xcore *xcore; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + xcore = &(ins->detail->xcore); + if (xcore->op_count) + printf("\top_count: %u\n", xcore->op_count); + + for (i = 0; i < xcore->op_count; i++) { + cs_xcore_op *op = &(xcore->operands[i]); + switch((int)op->type) { + default: + break; + case XCORE_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case XCORE_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case XCORE_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != XCORE_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != XCORE_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.direct != 1) + printf("\t\t\toperands[%u].mem.direct: -1\n", i); + + + break; + } + } + + printf("\n"); +} diff --git a/white_patch_detect/capstone-master/cstool/getopt.h b/white_patch_detect/capstone-master/cstool/getopt.h new file mode 100644 index 0000000..81af410 --- /dev/null +++ b/white_patch_detect/capstone-master/cstool/getopt.h @@ -0,0 +1,73 @@ +#include +#include + +// global +int opterr = 1, /* if error message should be printed */ +optind = 1, /* index into parent argv vector */ +optopt, /* character checked for validity */ +optreset; /* reset getopt */ +const char *optarg; /* argument associated with option */ + +#define BADCH (int)'?' +#define BADARG (int)':' +#define EMSG "" + +/* + * getopt -- + * Parse argc/argv argument vector. + */ +int +getopt (int nargc, char * const nargv[], const char *ostr) +{ + static const char *place = EMSG; /* option letter processing */ + const char *oli; /* option letter list index */ + + if (optreset || !*place) { /* update scanning pointer */ + optreset = 0; + if (optind >= nargc || *(place = nargv[optind]) != '-') { + place = EMSG; + return (-1); + } + if (place[1] && *++place == '-') { /* found "--" */ + ++optind; + place = EMSG; + return (-1); + } + } /* option letter okay? */ + if ((optopt = (int)*place++) == (int)':' || + !(oli = strchr (ostr, optopt))) { + /* + * if the user didn't specify '-' as an option, + * assume it means -1. + */ + if (optopt == (int)'-') + return (-1); + if (!*place) + ++optind; + if (opterr && *ostr != ':') + (void)printf ("illegal option -- %c\n", optopt); + return (BADCH); + } + if (*++oli != ':') { /* don't need argument */ + optarg = NULL; + if (!*place) + ++optind; + } + else { /* need an argument */ + if (*place) /* no white space */ + optarg = place; + else if (nargc <= ++optind) { /* no arg */ + place = EMSG; + if (*ostr == ':') + return (BADARG); + if (opterr) + (void)printf ("option requires an argument -- %c\n", optopt); + return (BADCH); + } + else /* white space */ + optarg = nargv[optind]; + place = EMSG; + ++optind; + } + return optopt; /* dump back option letter */ +} diff --git a/white_patch_detect/capstone-master/docs/BHUSA2014-capstone.pdf b/white_patch_detect/capstone-master/docs/BHUSA2014-capstone.pdf new file mode 100644 index 0000000000000000000000000000000000000000..b9ceae5b7ee56496492a1f1479de6be3cb87acb9 GIT binary patch literal 798667 zcmce-WmF~2k~Z3nyEN|Z?zVBKad&rj*f=!q?(VJ)H16)wxVt-z!{t3Q=bM=|=dL;D zTX$~#s9lvAnN^XMJDzwVGsxsc#ORpl*}2Y25A#pGiP%` zHdZ#me>-3p#4N0xO&kds#HlAyky>?A((O88?RSSeVjmval) zMoiF?S~JDQ!;Jx#D493TMxRWab=71#Db4aobB$N9HjD2hwWV*^J>h09BUGBy>opoZ zFxotW40A!!>I9OeObp8_OxQhB%}&)HZ`ZGwn^@pvY{O;d)>H2RwqW8eij5>c(2F~C zBG2^K9;9U>o;c3~!ReTTAaLhyG*o1%W?wXSMVutkSj0k*>uC33z?_;u@!zbmg&}4N zXSIr|DA>j;DHdX^zFU`b8@`$1UJ|#wzlzYat>H6b8NOI&U!zXWGDe*n&TwJ$y-bd9 z#nDY(Hw>9oa*eBsck{PI;Da-ajoT?sb02_R%sGmfNb8w6%VWt})-bN-(yDld-#F&3 zn(^p^5ObkX#*Y_F;vnR!D1oxLN}#5q_43i{r5ojm&}zLt4P8?RKq7It&*_Cvk(-oK z6l`5L?nkoF_dFdzL_uw)$`%n?!&K&=1?XoF7hl%n9dwqxYN#ruy)M32HO+a0o`ujGEi>P|#Z`Yfi5keduP#wC!m*}&SbP5fR@fGI{CK^WktMmy3k-7DtZ+Hu zE_!%jH{j~QHCIk(ama|ZzzJ$&(^x*e{)VC$j-`@|ODW)2l)DiZkPBrD-I!?}sF{|I zdI!h%_;^`iFZkzb=}X(Aexbm-y9C!krWOMlE!hT8QbxFPMaC}$8iAeDv~~L;q%ypM zdZdfitpUjyOft??RB;&t`E}=+T~4yeHAX|l#^7i4c_sM4&{2EgiavD#fhfy0i#hqA zMX?Y1M5(Ge47XH+YVlxp6R*B+vqa-h!9{~G2k@BqFi*4l1K`OuZI4$sJE%C=Q4BR=#bP0HTDl!+ zRBgXPwuWy&a1u|6zL`ATGLIw}qS)2n1Q`<}lZ$l5TZBr3y~9j!resP)#ifcBO%9Wi z-(O`JezO)2{84=1d83xbLAz4fFwmT}n*Xs-o~No{v#=Vp|9i{_g!qT(Tg3Bdg|MzD zj1`#}@OS8Z=!j(dNtE=qO3a3Zraw4HZVSxu6EKZ#CuI&|l%7Pd%SQMoG6Xa0yM>jA zrNlhx%AHv8bg}p)s|^_HQvF+H(tu%0RkXU3HU~$8kNWbf?<})pt%01(iB><(<7;-v zt+6V;Jbi{i&ZLKc673g*AKPx7yp7yLk3AOCp=rtW-zagYE;GS1niNgs2}Km_&#_1H z(4-*U%II*L+OR0(+j`Zc!nbs;_wX;8UF{+FMGXkDH-23_m?Rkw7@~`bKz0pQoL9R) z^G@tqhhdo5lKJwi6-^=}>su_!dC$#b?)D?{5YWf1(Qs?B4s!y`Jeiz(Es4TD zKw7`*{`~LegM;NinGa>4y$K>O=i7=(oE+zGW9KjoR2 z>Dd|C|NTej6VyKI|JIfXhC#-_+0o)tj_FhGQ}VC#r-Y)3lbwsBk%sZ|8qik-v2NUr~hV(|Z3m zCxVHE?cay$e;%lF4VzD!j`V(^*W;Zq6Sn;_#t65%G9WO6=7OCI-sEj>GjMJB{T^rb z^#xB-5}i&34Gj9zs9XOMk!F!j6RLpI zxeul*fNW09yP7j+6P*}}@Ex;ayKYi5kq0u7b4HWK2zsqZb9?%BoMmOPgqL<}QwG!5 z#P-BP^^*>WXgG5T`jXmlh~^v{yR6D_DUF2qz{oA%(_WUarh#qW&Xn924>!E)r7#d+ zu5Hp2Wz+kAf$T|E?+@)&mSokP=lz?#UtzZ!f>pLEga>+vgyhb{=LI=+h z5s1qIkx*l-El~mv%AM0j!C&}LpJ3lzMAUIm3SC9iA>{JQX&xt^C%H7*qJ@yE@te|j zou!k^yd|k)r{ej1u^v@4Yehh)0|b7rlWg;VQm10Njj8r1?( z*EutCXy}JJR1DdlFo+S%u>8QNol9$NkCy}qD9HWk+1McQ+X%}aX=hRa?*1*ceDe?+ z2oz1#P4^o_7-J?RphSXRlL63Fz7w7)VY!{wg$0ZJJbLmGx~THBAv|_P4Mfyxm2rKw zH`;Ruk7E)#IZ!a@Kmt_3RU{hqwc{s{p?5;9D2&UE7?=&T7onPv7 z2Vn>gSBwrMl64@7!o~eaZ0rpYRd3hHOF_yg*`=wyNiC}_yTQoZH1%vH=SCe`Zvg-Z z1!}}=Od%Xxhr4q_$C-O;Mx`L$&hW0kq0wC@IYb@*y_vsBq_%%Gu){<}Cd3 zIg2*=5{DvNG|OL1>5MqPkBg_1ENFGs15Ud`uE@*pz+kQN5a`ksEqe3)el$;hJzLFo zSGS*82$!+3wk+jfV`XoIlt#N2Qe6$O#&#Xlr4&W=JJTh>?liFz;-MOkplCy$P9P|a;==pegK2l>dYEbh2#0YAlid zr6wJFvgcsPh+7ppP6h97-&vb#M3js1n(1bvkhQ6P*X%1z{N(}GQ1eJ0Hy_6ua$T1| zXkYYZqV}4c*>W*Nupxe`|D~V!HVqb||4HaO-;YZ?Z#Os;C@6noyGGS0VH0Z^VBxqw zyLnb-kXWmDp7f2!$x;8GrYXsIt_z}V9EvUkj=t#>Jzs+C9E?-zWU0CO7*Cr(kgM*@3T_9&WRJ;EPRk4 zW)Ih)2RtHP3Gl-GcaY)Y`cJ0$p9UFrb}o8mE+#@2dM-}3e-USx82@_Y{}Ryrg<*eZ ztN*MvoP?bJstQd1YoO1>$ozky0@J7S!u~HS@xKW8e~r(-`W@K*KCAxq&+*ro{V&a^ z{~Leu|K15>V*2ZO|2wKM{R1zIlY{G@4&_X!ez!wmLh3wJ8;75gg(N{%Srhm3XTN0%#hv zr7?^U?5HS21#Y!RU-E2EA`B%zd<9it7skh^rT10S?{NV(OeO4S&MCpQ-mT0@e-_I$ zaNAgHgoJzzl9H*%uT#{X%xlT^b_x z?5eL)WxS@)7LD`J3cR4WRzH-qYI^|&(|bfE>1Ea-bJ`$|DL$09j$g?db!IW~FM3nB z!j#W@&1iTg#o)sOhu?c08dX{x^eXDxM)_$kel1BVpOezM&1zg0R%}VO?MQ0hRD}=a z?~7%WZh>Z3xTUv-4>@e%JtDEei6u2I{OYs*H5fwb1i{Axns$#K3&&kZtkPCw`Adxr zpxCHWz7%7mv-gx-LA)+Tt9lUU=$+&O)o*zO+&h`%HM**ocks^aDlvmw`(gJ-A-dm|J#>z?cOME7MZY(F&OhafUKv1#P||~Eay}Q_rT1fDKmo1Kqku6tS5!FPSUd|xas3t9 zP_LVB^TvJ^$6F8Nvgk}$*H?$UEZF~!)J)9(*%bYID3*!+lkNTO_-9y@hTWv1f&(E6Gbu9j;8j23MM4Q z3Hxu9`_g0@Nl6bC3Q`G%Xq1~FtCl_;u90pR-$ZV%NI&eACL`{TY9clXu%7i82v@4x zyQKo?>Ovg?iWJNNR@sa~P~_5D#a1qtUv zJ}m#8fpC4_5D@xLP6Z+oz%7kLJB>v7n8tjzP!j4%49PU>goq$k))gxrGTN6;S3{_OY6y zllA2#UxhaN>b4oRc3RY_ZA+_tM_7pTK0QD}4SVFu2y_!#= zvR?V+7pAe1*O`1KX9!H;GjwnrUEi#xg^eC#ourY?CmmWHkBf|PO{dJ($6aQZy&Jc@ z1O!-;M0E?nc2Jnxe&_i}GMgKc!7l{#aYfsk3FDw~j6ZNfup)1=uH zL2|9LBHi9u89|4}mTfa~@+ZUbSI8|1(p?4)d}A1&aQ&%{=2M zoie%FuIGL}QC#&h8;eKSggqJF*LB)867soS2K3F6r0ytdjH zpBm_Sa+>9t2wPcbJ;}=n-AnRmt0rqru@z2*i28cmvb&~IXgE+EvbCR;rUR8?Ba8tA zMfQ}s``f2l#F85APPhvC$w~L-;EG&~(^p#_7gU0_-{yZ+NLGUgD^%T*;nw@_HnoD# zENHl>D5I=#*@yH&3|*5u!VP*&BL9ZCcqXaC35{7;3TTg+V&Q;#T@OQ)h9*h>DQs*Q z>Rz86@}ku%il*c3tEKwH+(tWUsIyl=(N@A)oJ??mpGypTv(b_Aw0~YWx$my2%=Fvn zs`gK%*%fHXYm8jc5QX2w+WXw7oJqByB|jt#*2K%X-_u%~O`VGLfPtJaNr)}AzDCV` zOjHSg$^bNR+lV0r|GNO~!kk2^+P=3=2S+nL4{lC3@~Wn^V`U%+&#TZTcycxG^tBEW z$WYcQxj{|)k6A?64YX4WbqcMjn`M)ZlP2$6e1H-*RB{_GoznTf@cfeDH=lV==VPh8ys<(|6HkZWu*hANn}f+9Vb=X-#1v zJ?vzLs=)?YeG6#GyxZ%wRR*Up71>v|OAECwK`!F%I8AJDI!wERVs!7GweZx!sp7lr z2DJy)m`xfGT7*&`#ckxgU1|M$$liZP(2mkkc zAZ-i#{;L5X0*SL0l*S5Q~5e1d;~TP*(ow>UZfdB1Z&Rnl&i6ZO;YykbX1npqP?%jzj~KygL@ z-?`2cD27}%#U;}GCTX$j%OCSyks&PZ*T8s>&mPIs@TF%4r6zIsWXw^rF(KA4&$K)# zD}@+kKZ`8pVrj$C$&umVbOzZr<{%;Kz{w$B1fR01 z!W{t4jClbNXDmH;8xkSBB0sa=u;cYNu+1P#yjM_}e65zqLWJnj9mJ&S{dqIk$pgx6 z&=cC9#NXuT%U(XJuKYrjEPPpR_6wdv$O-Gr>(`}jd9(sZQB0s|3nFtKv{LkB8%ciP z>?}hK{98OD02dTPWdBGh3;YkmA2y1`fj2$!{D?)igvIkGWC#l{*XKLinvl>G+8?92 z19Rf@Ru>!3oWQ5#=|9JsNfA0Zd*mKM!sEtR_~3b95@qo3?ap=1T~c5JohsCnixV!G z+JTJ+&z$3Os~gD^07(|htCyWgy0@0fhnwsTanH!%8Ks}V7A zwJ+ojzTH_o7hkpN}4CuDdY#wGHg2EO+ z-ol0?vN!zcUyk%#pzrsn`866eJWgabAC1dYHf%m@mRcN);~pS$(qkz(rEW1!eB!@h zI*7?RU#x_i8+ak@tnWV~8W!-@Q#PxLpx=R~+0@4CcInA45r;|^SMLL0=wzhbSoa({ zym-0-W_wo(2Zn4jD5F?f4>KhHiK9#n_!RPFD_kR4ak z7M!4_!bUT2kAl1UO2bWDK!@YCq#)X%R{->^P^IM}$2 z@G;PMtiD^1xDlNv2m5RpfYpS%=1+m=QQRcwafb;8X;@u51>6m-7do zZd=qhOcd$X<1IaYhQlej^{%c!^eR1ldd8Jt+8V8w_1jCI!*@3%)CnX^^zn+El%5{J zZ|8)r>0b%HJqfH*0*8VAId=V%2U`WAd>7AE@cg5pS*Cp~e)$a9!m%@a_i(8{#iEqJ>-S)%#(Mn;D*n zb+x>+u#;*c$P9A_(Bo}fH=#RdKQ~puAS!bJJ~J`WOZfg}&_G){hFy~tfIpB!^MvS> zfnihVvlsnt4_dhe3q(W}ePoH@@%__)mtS-W0Pz$dxAHFz*v9;J}F{6au)6qJSQx6>QfAr4UY0rb6tv_xt16Ww@Krtl zqZF}#;V3-W>}YDdrrQK9Ld5eXVfC7XUSpp1^KpFtT7jFcg7*y@*>sAbE1PbGNl}<6`4+Ty@x~QuYS*XLpgPWxqY=Q&4yE||@n!S-{;AZU9q1@iZsG`8tO8Z8b z`iVWYT`L_6hkoU`fTN(vM;NekuNoECOBE_R8&#Y*SgX;$%BHDBJfw{Ia= zu4}v5Sv!&%+n8x;rTvk8XVt5e#wTJiG|_6D6&bp|N);Gk+1)`~X!-Ukr1P*qYaY*x`UarLo6mH8Rj5r@UAA&dn zubVvug&JrZ*}=9_OGb+}ZAx2qsB>J686rd3GWyePX>2h#}z|+@?2cN>DKLS<8(s_`Xf*iUz79PSHi*+q`B@)B2I#7RGTaX^U8mp%+!vY6ie=7R{M! z-137JT{Ae`-`tMzon%uY8sjkNM43}FGHV(dA$1G#~&R$09Ad<-SlK~I2fHeQ2;nO z;)EjQ>Fx+x9XT@4I7R{#hKM@ooHh{PnSsLUJsCD(T?!c&`aV<={eIo#k39=cAUAnq z+xLVXBdcBr6d)~ynWS0;$+^e8!Hxi-Q|qg#hJkj3+~C-4{Z684hk|ZCGUd25`Jimb zv-r1N5(TwpQJyBDr}Uz?@ww7qE-tyQvgxrC|0vfzX+(|I*nFbpk-b-2LPSrCM)zj* zb|qT+{keifF=|Na_z?JSexYQ0aTvmDD-E{fF(k=zZXJmTacBTT(`Y4MiL*GeN=6c3 zlkVa65PCQ)?6{EmC;o;&mMUF2ffsb8#2ma`@F;*aLm3-%TO{C5h3Iadl_nu;9JMleOc4k$ znb`oFcG=qt03^ZVX$=OTj09L*aw)D_G}My*#tyH!81U3GG?&pHQEzSUfvs?{vqGdN z2C@re>;LxWcn@tcp5-M=8U(B{-rLeaQBlaX>W%gO%rIF=KW`i+DgBizsYJ2KpL`=H zTA4JgM0Jp7eXN(eNo=3KQsX2wThOQ@m5nZ^+@2}#Of=qX;j%Rb-r{o;D*5ayCj``3 zio&cSqWL+)O_ZmQq&?-M68}IBT%yj>6kGfegQ?tX0!}(5R!=v05*Fibh%eLEcTFWA zMaZFz?<7Be^gG^FEgn(gmIUPdSlzw#rw7Zr?#!t^;?e3)nteo4L@_b8LOZgvmZG*+W;cJLY}=S+yFM50o~ z$FdXkoRgWt&w7;EZq_D5SMTcMIhw?WZsl(nE2A*P(11~nJQy7cQ%#ljXd?|tOyibu zftNGoJtcGRKIgq^S?i^9$?N>Y>Wnd@nJ}trk`K-f6RE;BUb#Z>w(dd^KutQl^I%_R z%EsbZHVmm3XyXtXeC@9IYYVoVb+K%#ZMMZPeYhs)*%ATC+J&gsC{~m%YRT@3u`?$C zZX5D>7$-jt&V@c$-bhtc=K8Ao?a&~n6?7@n=8};<2zZaZeg(Q}fSNo%)d4#Aq*Q}k z8%cU(lJ(fsfG`5=+#sWkZ4STqkO18P8065hmjO1iWE!k)bJVWb+#OnDvrzzilcj%^ zJ0E_QUs6Xec-X}?^W}wNur8BM&r*@OJybHx%&BA5Zk{LHU=2C3R5h-2c-s%apLaV; zplaJSi8>gLZ0`b7Tb3Bpki7{;hgz@Uhsp?7k`887c)ccY*uZ7F0 z>fJ5>07BF|YBzm$4wi)dpq*ALRrjWdDQUTqk`fjcG>##&-=`+ZF%z+_etT==lX`Z8GClRr(BVF2{Y7Gp)d`JJeB#$WxivE5~{>C+a)3KG!#1z}@E zHKx`P_4P+QD_!ddt^_{%Nqc!kBC|Onnb?R6ODx~?JqV;YP2WYISomJr9 zg}I*l$H^jOvxV@6=4KOyFWb4N(1)EA*{n|4`SQZ{fby*gQ(!yS0sv$hfM3UDt~HHs zR7JfK-}Tf!8}V`ZI+X0_2uac8@!pIfwUy#`uen0*yh<-6N}fVuUWomKo#&x~l#)N= zuYiW-KP<(!2*de;MLTb)yyn??q0wCGw=v!~QHf(le;{orp* ziB`|%1W?xfYl;poaYm8lF7yY}TL+T+hK9qY<+rq=KWi=!ARJpN0@@~&56gDl{}2Gt zBRvfUclFQzT==*|!pEDnjr64-%q`6v22;-#LEi0T!mh>2x6!~m$ zTI{mnTvaqziV)CZo>Id-RdR_;UeR92o)({n8a{?el)XfR1o*KlYY^=W9Z=XI-KT)DyH3N#c@{DpJRuod5w77 z?9}LgW&~BxC;QrB((M8z)BIA3Ze<)d@L7Q61c+eYZ4PArAOn9Qd*H2ICkRbRZW}i{ zXs!<3NMviarbTkERWjp78ML0QwWwQ$ZEQtzan|(FXorehpIq&-FPzI6FQ#3NiDV-> z<^R|fD3}@7>5$_vb8>RB9QNTsYp9zCM%Q0BU9-0A)+a`JdUX=%g~~#y4rku3to}UC z#S>yBKX<*EugXsy)15M|K2)XIDA(20>B!RS&`{SZpBm7QQ>J}tPt}SHd@@hOVA(U< zCZEFG1v2kwlX7E3X%9=?C1Z6ooA?M=XYDSR>@mqO{$e~U5{_vjVLePo*2$`TCYswg zKFyhgoTs3zT;I5`&57WHVwh_6TE7ZY!PHoS+-s4!O`m=GF+Y-gFJ3*m!sVjv@cXHA zoGFG6F&OW*_o{oRz_NrW_ zQ^zuRz;AjqFx_CX@aJUe;pKT5#Kf4H4w4KVgO$9dzKi_e{@51f_jdmII|23#@@8$a zm|>{kP$=#@bR41uh6yw<@lhmdUa9zSu43vzMG7BJFM8=@JwSpQs>yueRogNn2=803 z7w0z#6I=Acw*5V5Y$p*9aQ-va?Do3!t{+TO#UweuPs1LA)Scukc;^U~>s^kIGbnGp|!f2usAuhUtK< zN-$gV*1L*mD$BZ%v|O?>J#X=VJc04M&q6A2y!}+ve<66-dYoxSTj?)~=n4kp{(&zr z>h8FBw-%i8HQCZi;^~|75dM(S%bg3mK_o z4cE$`Zzag~h#LG=vM#?TAB~?^ zUf=cKL(#!BKJ5%{6rF*od01`q>Wrq*j2HGRYs0;an&pQTIY79RPEC@^RTQlzWOH;G z&F`~y>9;geaO+sqFYL0s*uXU;cEwF>4BI@ii@n`?4;XG(I>8B1jQ;v54S|qrYN-Az zuiBM210~||0-AJ+eon~8Rm{6%t3A*twOMpvJT^O;sS}g0BD&Y?cN}1q$(1zE%t`nf zcQW4puVHK=I~ZZ0X7L`tV0p^&{rNZkZU!OzUzq)#;QtGo|2tLx56b^`?rH3D`Wq7ifU&XWX&)_Q%-Z)SO0C_l4-Cs;B09?;ho;qMWW@rjO@Kda&0e)kE79W4)^oscj#YFQDiwS}lz zvVaAXp*JmC-zPw-l54HEJ$%)4Z~~e8Z2??gX?QS2hMhpiOjFPJ;_K|_c>M0&u8Tv% zNQLQIAc}vBc)hoG^!D=Id@Ks)Gm=%YdDFjQMltob&=A4|N-9RA^yFA~_m`)s`KMc` zoIyiK>2e%k!QRZ&*wd{NR8Ev3WMmW3*y)1L!)qH<&Vd2sxYgfcWj{`Gu0W$K)C%Hh zzn%LT^t97uSk~sP_yDM_k)|z%80W zdt-a#t`|EgBL*hCw7Ar0p$#^V)zsM9+DpE>3GfL$`c{L*_RxqC7BeIVeM=awnQNc5cvA-0hlu}rDUScN-iP>cS;BY!0t)$l7bZ7MM@KpTj;j5!1-=El zg}jBah1bRB3c?ryCv>>zhbqew5747H^2Br%9g{O;BhPaa6Al! zLN<#V{LCA&H?@;b|Gv$x^NB9GV|E#MIvke+xE((!hMVcX%n=zR8| z9`Qcg6S@;W?($Ga$d)n9;^)E(!t0|42!uj^yxuQotwz{?kE=y5Cx;E;zCu-+L1g&?SC%c|cLP8Kf4(4(OZ$pL7E&VY*uC5HO%&)9M zgSv;@BnbDMxi?)o3E5x7>@FKqbXy6D}%DD39Hh=e=&o55GJ1 z`E-gsu1wqa5yZb%ibCu#M`Yc!azy2uGfA3ty)}En8y2%0elZA zcM#>W>wuSSr4j%rC_nH3i*>QsI8H76W<_;)L~v4lg1D4`-0dMn20hV^s5U7joXeza z*sfCUyL|Obd`}gA!>{~1l%Knet#2UZU$la0Omxk(s}Mimow5AAT!p>}} z_cex=DG3yMV-X{>%C&KOk~V1oD#>Gtz&#-2sP_TOXd-9P92k6s+|UPh2r)+>z|_~6 zi>pz{o8qL1U}e2NYaMnEnKp_drjR+!V6^ex$W(p#JQ=H9o*>o7^J;5V_AvI(RoUDz z7}DF$ZI1XDYc{}Cj@ESkG$&yWiwkRJ4SqT?AwpCoJ~K3x-FPpQ@(|W}MoJaoMcPNx zyHC@*X;@o+@*ru7OmecwWTT3UoWe{k5pxUw)Aky?Xt7|x6(W8*f^!r$Q>&2KRmm!Ve zt)!1d-87czI-|=>jzdeL$^7Y+-|w50L`HHP3S3;RHO=V}2~v&)GqRpA7PnhAAE~3_ zJ=Q@pcB2A%5x=b|Y90g}G$<3v<(m#FmpV(wpQ-#HRxR}!KaQ=V*}` zh!TyAdFMwi=06R?{hA;I(J>w`H$qzghWJEmqAVe*G(68j79$dIh=dWxkQ$X}sc^P?H;?;hr9hT}rdOcQ1L3voG; zq=cyY%&e@{jgb8nCFOgjK~dBvt|M4&zmnaEb?1^YgTU*nPdFLr7SPzOaRQvOLfo&V zGB4=WXg6!CVVo3#!WNv^74wQk3d-`)n}1@`mWySFza3G0XT0zGOvxOQcY#fH8a$>2 zyfXgv9@n!3GV49iK-!{ZK|YEhq2k!=q+Lm_9F8KEbgRXs+Ck#CknBXk&^<*`p>Fvq zdFc^-;+W;3W1rhW#d@L%*56gM%b`^^)L48*NS9ZS=tLM(iv=ay>lVPt$KrbIK8e{B#**j7lE0 zXiL3UXuaRED9}cf>Il|vL`Q1BsnhDkIytmY;t=a23<4%75J}8_=Zv?jU+Cd}`caxa zwM+Z@iGN~IOUERzmTjndQhsg(v!M?-?o&YwVDJBIzX7z6=z0OOC{9E4KtShtS=%#9;1Qv)b5Eg0Zr)+zEU1e}F(D-%@$Dnb8SSP{#18#h zH_B6%456_ePTk?)QoBb`;N1mUA_;euQCMzfVJwz0s$GQS32IUs)5=t^YlrQ)Y?N{% zZme4FV4Ai(W18-4p@P>lW0GShu+R+RnXOwfOOm-zr{5H(%3JkeN8I&8a!ZCgGHW>& zWa`8K&aiJNuQcKY0$nkrsk%4=(+HcD_}oA)0} z8E>(eYoUC>VE%7=`z}fAn>zFEHw#yiw?s54aN}g}MY%d$J zanRx&-S|;6}GlD?Kd#SHrl>jX8Kz%3|)~dg9Y+0UdDv>U(CNqe_{SYpqaj=&wwPK z<-+-1+5C{B>vgRbN{DK?3H6HCj_*YP^#ylH1Ri)A)t-Qgu!Ymnv8d~DyfG*DfeZkTa6#!g{g=A=`Hz-RQJrF5lwwQQ$V zmF@r4e%lQKqPsvRDZ6>4uBxU6(XqP$6jWfWS-aY<^Zj{KleW3*aUh5Hy8n{@NfIzd zIS;yciHQ5fx83`Z@sZq}@{!8@R3nKUvCwbs%5|q7`jJ@bbMHX+{XKjZ_x(kNolk_x zM|H#PLLAAb50dsj}x^J zgttFiJ+CA&sQ5mQzI^voq3Of5`5(f0e{zNeu&+R_z^|aLB0jj?k-YXw8RSKH^2ux2uyT|215@*oh}lT2;f@st z`3m7SzKbKFd>0gzsKSbkBIfZiBpI^NRl&u*>E;tJ_w8b^kAC;j+4Q{N4HGeRuAYZ3 zW#vdeq8bKxMC1SJ{sWBUhvvOWxYoTEp4fex>BD%m!{4pxMSLw6f49F~;_`?D$+*Rg zx^3-xxJKlPxtQ5ST}l-vpX_$xIW^0V%03oBc|SD06{lFn=D&zh@vfPVC{Td)|bicxnay?UWfkU?Z~9}eb2;o zb(^jK-$pDNNIJKy9sA)mq0OEpeP-Ex``CTd19MgY@})bL2Y4`MwYl-JzdhFlGayy) z+tw{uqix+%IXtK<=l%Wk?Xue2;b70NoFMI&yVJG8yH0^}C4$?vj$W8$-Mo8>?_J+S z1d8}G#{1IVJ>-;DlA-Xnw*@Lq)gfYM+Ur@tSWddG*D~#IQr=q4vL{D}=lQ&`oYeO+ zc|8rZn`u?Glc1auIb6Wo@)LhL&GUVa)a~-?@{dBf^$9i2)_a+X_^yl;)jL35r({2osZZ&j+G*G=z_H#3Mo3EDc&+I(`mzK%5yxmx&o<(*7BPM7}<+T~q| zSu0x@fX>zJV5w($FIq%104ZzlocGpnDx;PfzRW4IS#)7&cR--HYRTomXxf?b*cEqw znX>KALFNyqvAQmC4!wJDBaf5d8jLAQe!dG*8m_DCd>kzc3Z=luw?tCV2nel|yV@X7 z?UF=_Gs;dK0z^NM;9q_mciE1Aw1)LBqBDvxH@c>umm@GKn`LgsVEDS8-i$s4SZNus z!5r!=M*SJolhT|+8kuB+w>kwfFWiDD)R>BSRGGYNXg2lu9^UDWHFZYcCc9+*;BBn+ zvKq%ep!}oR*WTjOrT^x$**F^1v3P06={5yBEjQt~z0m@?4%q9g^6_5e$eAcvYrx#d zyVO|oFkVi4aX~yZx?Eg$t$B{QP~q?9%DngdT_cBoy15I&m-hHNIOv2e#db>QVX-K6 zI%T2WKC^hp`sH6eUSnQCK@`=P|A8@M{m)5!|DNZ-!OZ$^mgb*Gs~=Duv0Y_E>Ug1X zFPsiXmJIu@fNB$8Y>xQ#+oS4Tu0$kVe>|?FSbEo`eH|T-|2Ag`{y33Yp6LdybATzO zAV2vCevtsxwD=ZjD6AOj6jDN@Jh{Bt^xNJ+&`buE!SDy^iK)3)`M6pF^YZ%frv!r3R7pYujTo{Fv>dqboM)j#a$%@RBB@Y;MVQa-tx6+hg(><#rlhv2 z_r^nUrxrjfxcfmzH=_hfq)MkXgzuT&TP^0 zI<@n1r=mB#VL7r)s4QzEvXdBT!eq982kg^I>bLw|+^H2xQVF54%4-G|Dpk&J~8GTio49fM_ZT4eW0- z8F>`=YjXxtVB4BG2q;S|my<C#Z_ab~SDtTe9DtqFfNAx8W1WO?g z9fZ`=nJ6|cG6nh)Yax3E(t&>(5F|EmPpo)g)`@|`3#m??nUm}V4p-b8t><9j@rhD} zVOtp`N2xKFQIDWG*K;g_STl;@GgqXVLD5MH(nbAd*~Yl$)To`ou6geFxYuAf8CA3c zo9Qi^Ywj8>A4gLdHg@I3q1~WC{D(2BcP^^J;K-{gsEc}k+P04k;YYUHanA=TmXFVRY}w_oama$GWmo}@1wXa-#(d0iZmGimAI{!7DvmB_ zA4~#-5Zo;U3vR(3LI@BTbb>T69^LACwKx3?(XjH?(PI<&~5U{_r3euJ!j9- zfAyK6yYKC)TTj*V)SVBo&olRAE99)$Z&!MgkmaAb8;q`z^UE*O6lEeK!-MW0TVbrd zQM*H+eu>BT|KKE?|GSy*|E<&YKM|k*HP^pdOdd|2|36wxVBe?zYB71Z`2Ig?G56{* z-SJf759gP|Sd#9d?42Cc)cmV^uM5P{4&5$7Z;0)oUwlqWFygIA=Rso;S9wlcTDod3TX*T%FFIsyz222Cj&3 zF4Hl3|JH~jve+m>pKfd{vhaD!N+f-rglRR-HxxrZjbB+aJVSi)82SV_yx%mzD6oK2 zRwP!WuYaFFoqHCaQLXLLtX^)^cMvhM0T1z6wt#%LtIx3huNU&!>n}X7+xVhRW`=os%;k9# zSVX38Cw+@Q5cII+#-v6lp^49$$ajCviOS$pr=P`Iw4Pe~u3tIoC^aWZSS8xJGU9e3 z6AO(M()d_WS7se=S42*;Gx#zr_Ip~yDhR{T32y&0heDObKP9sL{BVieHGLWN#UslL zGWXZ+ta8PocL&prR~!3V8M;e-l$#@7U8wY4hAWR}5$^T2QFpZ$ODtw9YVs3IliB(W z)~cefwg+ZkK|L#YhO3kXZ`;Myt_rU0f79HES%Nqbt0(-po*Qxao1nRxd>f86m)&_k zX=bzggqCl#NG}_Y+K3?rv4dSX=ac_{P`cBLkpASlG6A3Im-t_fBNtL~s_oA^CM;L% z1cyq~>|LXE!Wd-F*?8&?*WKoHM3jF0x+?8VGtf0TZ3_%-vM%Id2~+7^&eSjV2=9zr z>GH_v$t1kvP9QdA-S^6@Tl(egjZ~V6wz_+*wKRfUq5Wp@msX)@ECr^^eB$_F;?^<7 zd;8k!()`Bgf>j00<6NT@miu+9uyYzlXog5bO#Nn~#Wk6LG3U-(?E~zmK_8qCQ1|SN zN^BTJocj=sYUE=#-`l1k^&f5VrY^Aft!LMS1=D0x zL=)HGMf7*b++^I3wF{^QyPLxl6^CA0UfmwB3xgkV!gx!M`LC_uwqO?j6-JOWQZl{U(VQ-xj%6nA9lBnH73|a?)V`D;({_37rP7C{ok= z6apH4C`TGc(pIuUIfvNrTPr&m=O+CN!EN{S&qLSxuZcnokzVK;=eC_-R**coNKm)M~{bd+c{YChNA)<-5S>XC%m!^I#c;$ENow;HLU;sU_C3P z!0cAo?qu}RD^o}++aK?GbymZjce|UG^4@r7R8w@PZo5&k{wve?{M9fBUQ*jMIPZS> zajD*g;dBl?gw7Stw7YLQs~Sg`X|^V)wp5o~U(n*OCCGZ}*}o`H=B9O0hZH~!?<>7cIU(sE^qLa8R|GDdc74Ws#~FB znZwv(fw}3%z#%t3x|x!gi>%tQW{6=@yK{&oF)L+qH@n-}Q0IK4YqUv-e77&PVif7I ze2~CMF?zh`RZ{&{>;A~ER@4w;s&i@ibJl8bqRr>P^G2SqGI~)XN)b}yJlb55TUqoL zA39*}rkV^AE@!H!u%D|7Sv(Oy?ca>*1DY1k4}u6AuXeL}UtTp%-`ud*yrG~?YHarE zJ-Mh;&4gAzb}&4q3u@I>u2c7z7g&$|pX#!h9$l z0iq`JyTlXR~ z7dE7d5ohCe=d#wRIs=L(2>!UQZ`@ki@yFel!8v*87kE+Q+3{~zBzx=}=>6X>|78yE zXQk##z3UqmTG<#JIgGT(dDKK?E%qYA-iU1Bd?4;=uHNJSJuP?CE&<{9JVxRT^-{dQn6HesbO>7MWKl=bDU@;Sx(OAorz$ii28ffm{fxz{?-8I_Ai`ub(!>j*e{%jr$6ft znNY@hqQ!o4QE17t9c2`}V*jY@)0ziu7g^b_nX=8s>^X|s87bzSIzpL@GnWZ3K=lDB zDM2?zr1PSFUG1qTkz6y)ozScjJJH><)PPT`$cd_sBnPsr^%lk+7Eu`WsaLDcER+nD zb^lPHvhWUbS5=u=^C)5dC0^=cBR^)fr6KR}d+Xk7Xg`yTm&z?&p-^|075`0o$N4qs zlcPQ{&ky6fC+`;4ul8$Ot^l|~6h4YDv6gC#E(IM~97g}H4SFt_W&_$p*Wx|Pv;aC-Ju^Jwj z7<%ea_wNtCiwd9M4(Pd%`N(d3B@_|Zw6Zoq)m0lk4ujX7EneTLJFcjLt+S&Bywaj{ z2y;F7#Hz}U`zp5>-4yoj_4;GUI$2SSukJ>VAv5sq3c`D>^W@18xR;Jle>;==?0L;r zL?@72T$N!5U&pgl)~h&a;7j`=@rxg3xD>cW^B4P@R_kO52_nYXp<4e7{F0b5#(hep{ z;xhm{D$fjv9^p@hf=JkYro8%bUuT4H9-u?x($>p9qBialciD0~Lm1fEzDcsYSwB)n zLN=)7MI@0U8%*Dz93pYFG{Rn*b17v+_flgifqsG0-Cb;HRBFm|Y0{gp?CQ}yzeSTs zW`sMNZ!b*PE$u2gyAp81_tvwG)9NiE{4${^12y*^SNoY+)m~_q3&gNoUfp2a-^@jo1w$T|+Q6GWaG z1>0y=IY08BesdMY^0gkH$R=X8s4BY8jU(`888U;jJ-RWSyr$9|CL^ym<)V-^wRGT; z=Am%Nb9YCc8CMk7t3{Q}HWhZ19A(6}*{8DCjExQT69KTJOv*;_$4)gY71|yzu^aa` ziM(RgwP%cxv8@V>7E+BOBG0O@q}&_#sxEdH5*D3Jr}$)9vBT=CjL$y2BcXr!#vXGi zc&v<%Gu}qB2bLNSvV%)SuCV1T!7ojj1CgPr>H>6^PutnX2}9|m=r!iw%;E1}fU#~V z1PK}3B-sUL7g`JNPS)bKE)@(7B^>Ge%O2hp)@-N0S?xT0? zckF4&Zde%py)HxHibP@Y=iJ5Q#Um?G7O~FWAo9S-M<2)us}6R_+Mhe5K1~1(k5M*e zox)1Z?!K>$BqN-_rT8t_v#K@+?SC8b-vxf7_x^;h$4wkUtLl!G7DY)dkN=DjKPa)U zh!mxvoo>`H{AkoqyT9`Z-?*I#njiK{XyC@X+)+|F0@D3!iMA<=ul1G;&n@=Ty+IBH z$S-#oZE83+lqD|l@-zKgVa@hN@xtOyzn?{)elm6K5~x|e0xb^ouBH6iV|>(;O(?2! zu0#mUyENn;_zcbny1BX4-_3j0 zC~BkJ%Zd#n1&Sdp15h7qcKt(LMVmQms?3~s2GLIU(T731pCvd(?cysTFV_yS+TJ&4 z-YUU0g;^(`C8?2Uw$yqFrmcYuf>v5!26a+17ZK)GhkGsUMm)uYGy(fl{_)>8+!(sn z?9sldRt;n9Sg75S;q;v^{-A+h_8~A`B;Mq5S(l$g?St;sf7Zfl`A^&y?-@9GTv^9& zPk6Xb_^{%S|84Fg5V+YiT&~xtl zMA=Mj#}!iUi<_o>+jWgx+*hQcSmdlB z?XO!-p^TCp3%@|z@qLaQV)S@W90|FkND77FZF}0(FQXT~-%ozD$qwzB9RY0&<#c*I zp5o3h;y-i%m$tq^6n8@u{$VN@ds^8j>k|Rz&$!k(dKuf|=JPc?aHCDeqjYqVFwA z($4tz!g>hWeL#m$7Bgneb)t|VCo#I7SrKc+5~nvG7eO*4!o@A5Zmj67j^m4zffbFn zxa|T;_brwSuZFhi8oM1=Xwok)`;uFOd^1r35vx>h6+YLpZ#M3S@It}8QvuUWO{5-* zPzuOS`kli?|4>G08Jo4qq@Y5$+M!xzb!@%W?U+2A7zgRm%4EGmHuqdv(jok|m~!Y{ z=+9GvOdK1e5JMEzbYas!Q<>Bh{$0;Cx&*Le7RoBF)cA44$$Zs{(l7l)ZvHhcG;?g^fM%1SaAy99|R10jEv^0p=9EoJyQ z?rg5kN8&7x%Up*;hM|on$K%I2eK1N*3_VtK6E{f-ikNN3luc|A^uVApNMfAQe#hwJ zA-{Jx*6~+Y?Ym-C%CX2RP9a4nfs5C8DU~!=vcP)&XI6dHO$$67)nUPqf*v|LK_5;R zU+?{8Pc{ao)#a6ubyy++OSb9iGndYh_M736Kv=s=#C$j9gB_%UZHBgMQb`Ml=p(K$62f|E8}`C#qFSbxhIX*#9vhR)fZs$ zs#+~!T1{Wh26iE+7E*vj3{FOIeL?%ESg)NLFI4w=i1+87CPkC%HHXHE{MUU3#lC+@tBTeit=-uX=!j-US9hJpfOlxl;?5+_GM15M45fl#`NG@)p2 z6Xwf8DOeGXd~z9H|$XeQNKn1Z4&0WT1&Eei6ic5m7&1>M35yKJ(Lg*w+sew{?Z zF)op%*c-~!&EwsHJ}SHDYCH+S%cLpn&ey*yE`n0oTW__&HdgX(m>0@l8ijp{QH3m4-US`*->xm?%fe}+PEIR zvgrSmsIA5?I$4sujG!_J&XNlWt8Y`SR;%9!8wa0Ht7ivquTzjl5zxI8Qs{ zK~hBdVn5mA1(bStxn5@E%C+wZ1yGBpu7bscB$J$S zlyKjYk=nKj{v7MA$7ymsooO<6j#47B|EvKzcFz|mokV|Dk$aDUqI=!M>!oe68QYGE zNo}>ceW7~$%E#pkjrieisRyKT3=yA_N~*GoaCC{p!q0#8rfH=N&s{ z-K*$N0=1izpKW-6x=;eyX;YEDIDP@wU~zLyFn8Tll^i z_X&e=*(xY*_wLLq)lK9TRN!}Nv}^MsH;=uDNH;9C%w9KUE_uL66@Hig!`aq^+3%~9 zAkM{Ouq_h$@3B{TGdSW0TJ2wTm?w_9^G(X1;x+Y51^2)X^*UfvkNB?3+-1Lhz+aFm z!rb0uqLsN3Z7WEkuYH9zC27V*tdb9fYp@0;{6fsvO8fIV?plm)Ig9BR=yT%v2=gm` z8p&+r7&fr3n_YhUxkHX!_QLadtK;>c{HIW#)w{aO>Xc6stD3o}?}`bi?%u^rNi;&n z6d^(d*vZ^slb+2TYy%o^t&U!L(mbv{wYtQNXJ!wr6TIm5HqYK?nL?hp*iBQ2oWPsD z7@@GscAXvf@<*)H`faL_d^<=w$#&?Xo?Xyzmswc1IK6m($0>uEMhCB>6YZguy&dr~ zl3KqW>>qTJrF)sLWNWgsswrr_dE)NY=F>NAFJJLg1d7LFv@I}6WpX>B>6R=hL_2qK zo02y+yN3~9@xd>}0$=N5=lt=oFnK&knr~Ty)3Jo3hJ+RWC{psUkZk>sF(m6-Hg_i! zr1u(4X$dxsde#yNeXj;}J~vKpruH~{r**5^zC9Su9`19r z$X`@ZQ>%2~%z5TfyBZdvZtcO@<#pZrw zu2zbV4sU!fY9bfYXJy4Yq>C}__8Q_VqH*WnzB?>d+z5Rkso6>@%EqjrxcA|gmC*Ml z*pE!7rSpDHQW?|?e$Inn8PbAZBTfJm9)&i-+c`|kMn?%-|MUfliZ=!#C>^zq#hs};ra?&97^)Va>WYEOA) zcKxP9hG0fM;rz*R!RocEv|Nld+vc&Ew{3RTLCxDl7)`_OB|Gs`3-HP34Fr3O$N<%R zSrr#Y%;}HTCgIN?`Lx1Pou67t(qI^C)a-uXyB4--Y^z_byxR4Um z`-(I+u2z~z!YJ_V5j4G&?anXDgV~{>$wcP&@32v1wM*GHfYfYk_D*qLdU)g6Ili&K zx-S36M(Z@N<7s*9B&|$=iGQF=D4hFw17YR}6}M{8o1x*JhdPJ>J*v80%>6{N_HYJO zxA5i5yvjPu1$B~z3$VUxYEDH%gQuN~b~I<&f}_I&+#yYQixlUEAuOyVF790U`rCovyM(Hr5w{A`!KSYKUSu8AjBpJ^{p;eJkg1=FEC;vLv@ zdBma{dg-ZNq>wsgLcFqPV=4VDUB*tfC5F|iJyTzfXfeIMp|8Dw!6|$i*XwX*86Vwt zK7%I@&j|5Pt{X}vIVASYaU?(D2AU1JSzX`CSRcs`l?>fX3@7`=p`+^-f>@Ywouri+ zkO0@%4Nc*YaWd(^HFI=d0R5ot`3<&G!h_7*%eyp-BO#$0DqwTJw^>`M&3-Ofp0cpc z_>NjXNz}_?u0(FiJF46RvqX6A5Jm|lnN{)hM=bUj%Tnsau$8Z|VzYpXsNWfllg?I* z*F|TZ+b9oAey<_&Ov>Uj8U9L2S#{b*k_gIVfsdCC#@-)SN?j{kZzE_HlRMQP-Y14S zmN^YvwhyRQKh^=ZWQRY|*^04q_H?^y%?NszG;K9lUuZoT#*>b{zRGm2_2xoIeR0I3 zd7>o3$BbEAnnKFxr*W-xiCE;QAs$&oGg(hGV^mxLue!>dDI!+JbC_s%#7TR^izy5# zfiz*q*55ul@!E9^In6SoQ^ZFka`Fl7^q7GfE5Y*BIWl5~_=Apw3RQ$B0H^WM5BiTxJK0V+^!99Sk`e zr#g1zI&G?~Jt>i0YBJy~xrTwwth~6rcPuQdo+T6)4JgeU&r5~fi01kjE!6JGs1CfM zb#F%w1KN&YV+u|SwAtMB&=tWM9SvMgyvcqBbu#*p^5PoT`J578muBY+o!EvVR>ilw zm4k>+6qABmCDr>3gJMcF5WJ>LjDnwb3`P5UUxA!Mn;mDA*?J%tbJ%jZb{)oT=@_(w`qRsO&@yleiDcs${f!jJ^ffY9gEl1> zY7j__LUDz@K)NzE4EB=e7&m5ba*us4ZFeE44(a67jk3c!Lw z7<*x3$CCFQFDjol2sa`m!hXIx`H_+R-nFE2weMXZ0h8}*J>Z7MKNt(9r70fxCFjEn z#3${`8x;v?f#w2W@{*-DYmj)xjFD&cC4X_Tf6=cbA`g7Z-eNr?MO3$b1=z8Jc<_S& zGp&3Fmt&{*Go%L!7T{|i4hlu8ho^e-^$X}LaEJl-d7yM37+!$1{p;j`-vt=nFTkh3 zXMgxz;KW~*cmPEmCxkS$SZL4nWNW&xX6E)PCwF&@7OpiTWk|3u=(a3-UF}i8k0Mxn zu@S?}#^O>|#OznwlXGZiJcvQ?Rbpol;~%=%S#Ey%_UucrWunOM^F~8X9~4;bTvDnS zM7RiC!N9oe$t?z|8eEu~k&7PzSkJ3ZXZ&SG$U#l1zX$%k1{TyZb`va*%w+e}=tXu| z{^sDcSDlU1{zOg9)m8tx%Q0q&o2s*q_wLYJ6Q7po1GW_GdlCQhy-&bGe?I-s_`|<} z8gn$)b8>QQt36NrJ8-9bU?;F6YUIx^I%sOAPssAo_VuJ~)*AK@CbecK2;}6;P###q z_?nrPL~{Mj#y!i;F!yo}yLXW57c-?k5}%Y1jgbGDLMotIZ22RAj4W#PtwKDT=>~cW z-(AXC=SQRMS(mg(7ZHHNbD7ml>?UX4S;9;%=m|1P5qEPedd3{Mw$}t(lx966-3|Ce znEVAU|C0vGdfR$)M04`oz$`$>7kNh>qpQt&0AO~0blR0vUfwzM3SyN{M!3PJazQK!0tO`WA_y=ed?*J-E&l!^ z6PZfIvKJBpCSIg^H8IawYrDW58;flt`qY@5j$T#`oW4Jd;-8y?h_@xT|9AuCI=D4; ze@}1yc?XPsd8=fz$%xnLyKeUbWgot)zr*;MGHfU&V|=yf^>D-2PdL6|1ESUp`nqEe z+zP0&u0KqdpdYfifxNB0Mq$Y~TH>VS-{2&i^<5~a`sbZpMaqe0wak;5ZB{mRiDcdW zfTE7<28A=0W~w538|EjhWFnBAqPVqp{B6cEnzx-Scm~fI)22fk?U?m2U&MSed8FE3 z@pH6g=mje&3*cuG2QX~!GS0JF~xFRI&2c09g%*nrQnxF8u*Ft$YZ7`Nk4A+GY>zz2aA%y zdw2n;P!3hZRIXLt&H=s5fLBSOkEr6w(B$G+REz1?tj0eez7?>zQyXDGCO}^*((E^1 z{R!DAOTgX(R){a4D7J>Nl1sTlh%-?)Oh;wY;CaEAw1k-s{mabZ;5e0b(G3B!4HR^H zyNTbFMxBK3rw-{7Ct)WpwSi3XF-dA`;6}YOy#=US(TLH+p5$GM6r?mg-{!$b0#TqZ zpQlqA6_~CJ)Ml6?TofIsvk0ZBgnaNw`J7C~{3Hmcg$m%@n_+vpuAd_28MFlm^Xmj} zkkJWhsl+w-j2NgpW6jmJ?B9!3MHk1h(=h|;lPWHhs$(tdV~0lxdME63Jc-lP#jmV(?v{UUa=Qb#7jzB;~za`DWNnZ?a}@&t(2L0UeWNMAbrpdIn_|1=EQ_Y%HK``C$jk z!h8mDyH_GZTn&j)kaz4z0n{U(zPT6KUQyU)FZr$1_W-rKh*!w3+W5vVh=->EUo{S3 z0en>w5}2Qp;2SRQqw)TU=TfP z4CvPb^6^gwIr+81jLAoqzW<)t#<%F{zI+aG6>$!1o9j4V;=gOKEG^zQFQ}YY#z#O4 zT6h~auo#ix(-{l$ptew?uP@ihdW&_yH-1WN`6sSDdzcuhB>DuU3{QsRG!3#WS=@H| zZ(&zz*XxQAvt`kSEz7{RWJor@o*348@iKmSSOUCl8EWSy7UzHZbprX*j-eC%#;To+ z&6+B2Pt$h!`DiV~cjUa(G^}_UEOQ5L_?imfS^k4!-iVZnw=1wX9j8cA@m@2TWf#Ux z%4kC?^L>K#n7wAk<_t-W0W1&6F`NfGU3jq5l11E<@Yinz0 z6hDaRI1R%8#ySyKr3g?AOjZeZ`g~l8VKj{)Oz;;jISln_cY0sf%y;zJrmVj1?tmN+ zfSC_-&kMc69=7BT+W9d<_H|eQ;gr5M;Bf6CFj6zys6J07A$H{>X&L$e4DXfDzYtVl zt~wgnYVEC2OBn8h{_yLAzHs~Z#$WLKZ*coZe+b;;57K?mAO3a22ax-plm7?A`xpHE z3sOJG8_8ZMJ#JoHK3wc?1O}JHVH?N%G)E%Pkgud82INpAvB9f$?%VKb@!H7P9}R$MBZU|0dR16M85EHY?k-U&Q?ZA8##RI zJ3cUeZ3~U$_p9;s#pMZ!1Ic8tQRMtVJlbo*goTUa{d1^-tZk5=vq*Dll?DLBcP}Zh z@>YGqJJ#~}L@5eGwR&;ge^WQ;G-KS!Jh9o{^E)Us*tGM42RmQzA0OOo?qYuT)O!(l zQzvdUte8T^99Ro@$-^kE83HE9`fm`{&-*_Nt}75P-z-O75uARU*5rFx#lDIG3DaY7{!Dxa^6gto1Wz%9R>w#VHxr()bKZRgZEpYuD=T`;BHZ%q)Ud@N-n zfC!WkpzlvNr#1sC-5(h#D^hWM#U0W0UX|-78c&Gee7htdnLc42x;!BSZ&fE?lAkyW zxoP=g);dDAB(x_&>kC|DZbgCIr1U(u%Vu)Y?P&B09S9qN?iC7Fw^=6}EIK|5RyX(i zmbY858(9;pG&=nKbN6nif7MmbAy;o)`ju|R7T6ZEnH2-{vo5pRM^_y0r&swG%6Q^G z%HFoH>}@yvs{>Adq~JfAd0+pp66^-rSEcWC`Y>8w zJ;9IBc|ef-TUx7Xa3Igxn+=Zs_4*pYQliSpp(!koBY2Hk>7oGdEK%31?ru*7VB8U| z$D-w)OL}eQb!dBguJzUM zda;Yxm#>n|1n3H zl*smXyTBEIM8c8h=7VaRXoSSC7l;O{9?|xMYa8_o=}LHl;R)AfGOs*ilF^?K8RbO^ z350+uP84?}8wlqUxwTQCp>ZnXbWWx^dJFTe?vJID`Jm@cyzSpW)6%_=@wU5@uJ{u4 zxmJ>t9XR<(kw=j&)xZLPXQ}o%wIKqp{*UPlhtz~Cc$jJk#jTADKs#1LHjl&j$G$JU zHp!01XRe9SQQ4aYz4H&PG4h2%RHOzQs0+4BeBMCjL+6oibQ);X5k&xC0R5O3cu)%{ca>Uq8 zEU1iH4SelZz5y2x!P>D}cxqidlkXMlO{nW9WWP6RbrbuJRM$%7WQpj}(W>)*4xb_tBnZRAKy*%Z zaF5VIYVEzVn5%*B`MsGk?c%n%`#y296C5G-l~{PmGC)J7>eO@kNpf-iW_E|2gZ^Nr zwxyMKWVq;K?J8&VkbM@)be zN=aU^gYw-K-}mLSsz!OGN@qLo>=G9C+H60NxQxr-Uj}w(rM-*>Yqlyf&sEwJK}fuK zDQE7Y$7IsBZ}@^Y#qTmYQwOK6LH=#20T#$XkzG_kY35Jhd1V{;QY%8dfuk}am_z~q z&+`M1)Ph76C=J>M=Lyaq$ zx!gwL`RNTd+@w#aYQT{%1@Nxmp>;H0n;9=IfQpZv_8APk@$6lDdGT zpG>=^A{v|ke{npz@B^(JQ?+lf<8by1+N7$8iMFg4nKJaN+&}bpUx$c^lYdTs8|trW zPVTdtMB-x-yn0KNiwYz&T`f6`*ciCVYgk8&+H}tg>C$wnluA75Ud>!M@qUM7Foe!! zJ};p;JYx>eJq}4Wj?0aQ*JKxdPC~)A!h+uQm&}(8s;g2T4tPY03Pzd`D>ZV(ySuw9 zbPTHf+++L|&(uJdW_1h~P`jPo0Ma~36(;Bl58ul;EXkBAEFvywr~>d#%Ko-9e-!A9 zEZ?Cz5pg7Yc(`-0`yfw#@l{;9qQ<$|pea45CLi`l!J)eqP{da542+s zs5fFXl#MdY;2lqhE^5%ujjVYpP)R36`L&#B`*t|@eeqnDgx$c+SPGZd6KM;ld4F1x zk5CYxx21qQ!tVSm;YlhNsJq)O6@rtRyRM6cTO#|8>UxiLM!l*!sj*Emh%1K znt1Y{B62L?Sb#H>Vr`b6;4O^VbEmJY>6IZuM}F}+l;f_9 zAxLb?Bb~C}E2OPjG`Qbks;a>H;7UyY)$8dO$SgY>fkcrOrY!GVtn}6 z5pO;BcACh6@O}Gh0O@OE;zdV8q0m@WpcD+ZQ4K_NR!pLA#64@=5NXI7E0lnL@OH{g zh-|HZXh1Hz%-cJnPy=I?qmf7mWCmFu(M8q&oLb!4lmHS)%15@!6S5UYBP%O(sJ4d* z;T%6sT&z5?MN@n!{RO^x&<06#bEJGy0+M9_zQ-8JC%^KsV;Fo%Fy_r+%x$CD*~uC9 zUW7n$_w;kb%54EJ$n;T`72EpA(rScOXD4O`Nr>yV6vwzeY8Z&SMma9mHglM<#!*!- zCpF20XZkf-ez$y8^Dr^|+KAajY&3+DExhORBPeYRqL<02?GJRUXLwA2ae!FmGUL$v z!owQCdi^kgB>9q$yKhjg1rQ`b>?`0}>C7c>vD-}Fn)UB0heb1>YGB&+CvT5@I6@7u zG5j{b9NKTWo}*qFa~gU)6FlTnH}F*7>Su-u=D!;&3T<2p<;v3`SMslV^BE1{pH8bM zPz+R7^!$(3*%QWZli4s9IyeG69VAN`Hh^j+5fV|yZ|C6V6@3P2G-m7$o_|{3qfp)|8u0CRPhPpoU3}T9wbGlD9H`@Zm@>oMK zL?}O_BUEuUbGzzFApgm&fQgpFV;v{TQ?;K^Hv7r{1T%kFGL8#i-uWA8Hq>7gZ^~0I z){iE~$~0j@v+xbw9N?GdODc z25ju_RyvboV02VaPP`L$_xgT*RSMktampL&@#G`nYYICCu}D`^+%>H|=N1ccJ68OZ zF%#+nrSQni9)~l7sxiaoj_T5rOq(5TULVpkM%|lyCX6eNqcXUs_kOTklF2&FtI! z&Q_wR1e|*Ic$)m`W`e=mG>Y9qjeBg$$TWdRoPqA%NOTJckaxPZxQpzHGl<29KC9 z5XQeBNtwz;aAZ{n(CUoh|qHhzP_&ZuQsy^nVJ z2oj{kbU_nt8ZGw*_jXDw=uAIf3GT))h4kDASUG-foxN{$NhTIFL$&h^Pr5IuO%gpG z@9D!v8KHYt zD8J!x#X4Z=kcaPaX)>f#Z#RgpI1hZnO|^ZvPZsxL|H;b2itOD#-FdpFD1Q;JVm>VX zZ&_S{Dj=1~!A5JRP;!)<%0Hc1jn(Zq(8^p3O`6AAn9-9jEE)q%>N2s_r4-N#l;Y-;cKj$T-42(mv1ouXD2AzWWU=K1cH@@Djmn*i}|r!T+! zxW^yD7g*CC5=45&kmQfeHFvCT819ZIvGktDj*HF6+~zCrF_o4T?q5uDx!6DCa{2pS z)~#E3DpTv{4FXh};3=~$7IeI9PirjZPz%$PYS4}?>ppRR^JYT#JixK07xZJ5VIugM z8Ndo4{#}@R$et9rNRDm;PhJ^m+j>=HR~#TXX_9xqf)bGEg@=FpuY(wKb})ZY=a0j? z46cG}qc+E5_9*8Q9Xuedq*iOeIOt7P`jt&EfCZImhJ|stH=mC}1im|Xs;1O4%A|T3 zjC2)s5X-0h-H;qzl`5zA;80P40MR?piwDV$3Y=(A6p~LP=FAO5t{8}Sd5ZvK{O&*2 zkC2`y4BY>?sC}82m^IvIxpwc;#tjm9lnA=6P0($D`9Co^2C|E)lLCg>re^&?)31~& zA)I}GjQn91l@591OFrg#s^>XY#e4zbCW8_PjGk`R+j;9K-+(=qor3`;ws>LGUtHxzY_<%Cwdvy`agUTE%Pe04*98NS*4TX z^3H9%6CDmQ=t7yCVpSQFP4VeKULN@ZG{#{vnn4{mad^s`0={3@=Nm#;gb&Xa#3$ld z7iOQ zU)3_69$7pkH`4#tfPjJ>9y|1bvN864;e*gWKFFFI9nq@-U(=7swR1#}EJbEQ*6WpD zn|*=h_T^BjK~6dp9AG0k_Q&D=)*3|EZO3G+KbKQ{>biO2Sgy9Vy#Y#1KT|VmBU@0E zqbooYAwLdmXACeC@O@!~_@8@|v*PotteMgHV##PUt~)fU(&;eZF`O0epw`!$=b1X0 zX#vDW)>9GfTWKGd>UYznTwj~ zIGf4nI81`r#^K-D&?y2_)|@9-68%C4^A(Y}LNn5!A00&nA_p^ML|ZOqHVe_+{A|w! zp8%2q+rN<9GSnL-$%SBaMs`ZTj6YWa))gCcRi;~cj@Y%y}EOc9s0b}7qN+3Ux6=Z*7E z02R#tFb5-#%;TA<=(5Hc&-De!9>3!fB#P(I%+pmONCutZeGQjSxR0^#`6_|Hx2MWE z%SR6t*f&J1ec%lL*2`d+v92e^O$_j?2XPh7Z^$SbGrns zj@v{=f7LA>Oa1sC&h+o`dlFVfV_0W3OC@%tbr&tjd_}_+@A=H2cF_GPCP)z-D?_Z| zIO_?NgX^%!Ab{fWpD^<`1H=uz>gx(;E=hA%%59CKT$7ysm&lCXe@6zjjRt)~{Eec> zwMPh0iGPzluQ$LhHbXyNevx#<7S*y$TKGkz-lLa2Oce%u4l(8S4G(#|@sOa4hrH0S zEvoI!L{LF0Hs$B?)Bj(>B;ePrm2gXL;+MX;;XeqQNO(!7@Z3@OQ}tcEJcTz~qaVNR zju#x3qBv0Y^w5a|vHYr1X7zmz_??_95FdxxmnO$E){9N!mi%5t>@h8nEuD#NzpBy# z=CTQ9!~Ru49mkHQL156=2^{?PG7FQ%p!Bp_4rBuKFX9`jVDS=_CLP_Q20YZXn7LQ3 z@i!5s>}c=?vaR^JFgpRMk~%B!LkK@0q?*8%9Y4j_IhPy(^7sj~!>BrW!>O#2G9`QT z^J?YCW9l?}LZz?T|2GP6dF3QIFC37JJ!EFU9u|OPsjj@hac}C>T^9QK_FmpOw1L$6>vsly-{*P1 zpMQSKwOBI4%sJ;i`@Zk%y7smA`N_)J6Ax=y89(WlYxVV^*G|KM5WMUbR)&PX|8kwBM`JOMfcXqqJ0f%GR$j8}(?I zH#Zwyv-h`G&s8M0>EoK$o%v|CUFzpcx}u!gX2UZ1W^j#No5OKwv# zmI_RHtMS*L_PQ{yRy6(}$i%DRwA0CV?cmy2wKKn|aA$h~hHQ{@;9dt(kR-4Iyg9q7 z&fOjV;Hxl3xb)h|tt1>tauFCK7%G^*?oXxlJA^CgO$<;ou8r)z<)b{%=^GxK+o^lqBga0}E_ zHgC=}U5FLERVuS=w{iAhqZWg&2`AYI)JFw&yq#;dgeYAUZiu<9nyGk!t-WrAyKVll z91-I|MSpmpJw$asv2k|;Tt{ja=5vQvlJNq&%*EEGrg^2M^K-6_F9iCY{Vam~EU~I` zqRc>|EKUj6X0v|$ny6 zuP6RXcJH;1WRR!l!}#o_7CU$Qygj1~DfAwxJyzFN-??b(>XXD7=mQF7U8Su|`Wxg! zi6-`NR+cek4gfz-b3KzekOr$w4ukMta*N#m6Q+Ri5%4TQR1+Dc(HHyiCL9|U0n-d} zRCTPq*~n7g@6G|-g^muAtkGtcB6}pC3M>HA^>RtcDTvrAED=irwVwFj^IUzEk2cRn z%yAB5#K4Y_e_x{KI{l!_nAe_`hl!0%=|nS)3UQC{5|!1fV=dm0TsV*oHJbHW{6>hp zxZTti(Lr4oeG0u8I$9{17gLM$(Nq6D8$Rl=otFf^HlQ{j8Q=U%B zbnHJlmmb|jDWJrk;um1ZVUTlu@~_Jy&_PuC86F*Nu^MOuy4V-C@j+7YQh3LJ!%``z z49N)T(r<2@^!Hv`Fn6?n0KaAy=8b9xNzCElW^pN;~J zvbhl;2G~>pxUfVE6v2IlT34t4f?T)u9Q5?`1nU)hD1PL9SRL~+xkrbz9QFjw4K@5D zVkWPNG8nZ2vTayMFc|N$+nMgy+`k+=;l1j|c|{+6@S4l;)S50DpyI1HCDnl6PzY~) z_AfQM^ZK1(w0n9}*D)ISZ7=>T!aT29!U1|&wcs$jza8xyA9ULa-KmU+$dtiP(JP3(wDCrVP%=c*&}tSFOQjt5Cz95(si@6#Ccz~qMFnmdvQtSoV#hOM`C-DAW+ ze_h^s>H%0JOfjdZ5L(ZF!p{)a`*xoR-5!9_ZeEF-F)igD4{P(TPfI8u<>8}gPRW{B zLO|xCJf5Z#Xxtk9Yh~FacAR2sBQA42Ow2}`O?zH?TAL{dq|0-B95Ug@J*^l|3+#;l zxNMg86o91uFKC2Pe%B@+XG2f*WggN7{yxK17svU{Jri;V%pRYmeJ)Yc)o#*Ef zD*@`>-Zv2yDeQXx`pBIz=5M|i0G)Rsc?bRf`Q<+tvjry38X#3Zf|Hv9!YO2z%(+zhm+cCJm;)PaeOmL5jCKWRl?k+$CdQ7PU(*xiNNjLSS*Y*cDl#LOiS4o z{u3(spNrn*sb=7&y8Sk3H3M_y;Ky4W8z*x$u!Wk7G70)Ip*~}q(a+=%G}5z8==g#Z z%C7v!JaTudlOE`pa|M+YLFAR>>)6cMoRm>RN1uxe6DSnEyeWD5zEX$YfbbfW|MW;|tm{uZMBWOc28hLf|LkQ>LE z7%{kJ(GK}iCYc5UF!WUr%x^#Y`%Wk_^rCAN9~(+aSgV>QhS1&u%cK;Ge!nZ6=c6+_ zzC>`J?pHS=LUOs%Q`4jUvwAF6kA7Bs!?J#I_m%bz`IKJ2pE#JI8dPX&CbANWWYaJA zI7#>Af>_9KyGt4cO(<#s~d`ZE6Gf!5zHI+c9INX6&Vk_=o!4G=S6EJ> zGdv5Z>t&WcQr-u9^CEU%_OC@{K(VbJ!K^_Y>iG< zdeu@^H=}JOd}0>O!2{F(by2kzW8K}tXKZ81&-uUEf=BFi5)DQ#%@H?-uT*M9o<=>%0huMY~dtm_2Nd1R_d1#GP-M_R|1na_!)99pK`iH zu@`(OQC_MW^G2iN$<==Dfey3mS@ggOnjZ?FDwVvUR(|88z85mebka#yzambJTZa~y z!8S;gZGs2Qe6Mptezvv7sb}xeDAz=-Qm=Vmf_HHF#>TxCtT!=j*CTFui|p(<5xCuqUsN{# zso9yYaQi274(gKzPBU5|@L-LQ8<&92XusA(=O7s`_~87^1lLl_@!L^aIs$>2kBrwC z0S_4};7Jx0c4A80B>R9+D&oPZnR{R{O+h-Ho&=TE>qI2mQOORNAf~g>P)|m3tZ-t1 z(-8-6jQU(}ZyHLWOzCSA{dQPW;@55|yx+3%9d61Ai~$KE4xgMd(Xth*mf&$WPXObJ zWGie!8?rA(v7iqdQVSuj9@b>7HI&5OfVk^!?#~v8~l_m#=szwpMoaZdD>>IHJaQ zF)v?-VM9uH(GcY=P``kuL=e+6KclB|pO5QquPeKPA?1CiaCa}n#tks6<<@0renqiR zQu(S1CsL4Hle}dYE_yf_l8sfhDi-Hb!qJF_CXCcnetidV8<_hQxWE`_)~7pGQTX9Wc&H;(t5VZ z?ObMgC(Ht3TkCz9_9%SwG?{Jei;$k}V6|$$@8x3z+)AR=VLp)EaE$hnDNayP4drm9 zeZj9|uG9|`btUwm88eCw84h!#FPybRTUs(~)$D}k6STjPc*4>fctF7BD0dcl%sJE$ zWpDN~@|})BA2%RZbFvu);k3IQeCQN7`sG7iAgszJNA=2yUyE1#k$-%3yMh?qA3oFDM;#1dYDdtV;0?}2@7gold~O?=7;|Ng+8Y9~<>jq458FpoPqtekn{>;u15_e!~$}V|rfNcE`3f@H^6F?DH%}Tud_)RhB)RlMB z&8b5M4;n2h{y>ROf>qpp9YMpSL%^jV^Tjm(E@b19a@Jsk`=6{39rP%K#QQ!=_6OEMTU_CrV%!e_aU-GB6<&?-vUu1ZGxqqiL)^M-a za4*P^XSKi#jlW4*yb$8&;H9~d+p3L~ucf9)$&ib{k9ExrYSkE&G!$fxtxz?N#Ba!I zSHsj4t$dXKT4Kn9fyA_Bw~h{o=2NPwTqgYnky%r2l$FaEeE=Q!wZM=mBh7Ye2H9JT z866r_DlwIT6TII`1y@#O2xckPUP0+v`Rb?|~_ky8VYfk3)r(t+d!LIv?1`;Gf8Pu<~Y0WmTg;F_hLd%nU`L;vw;tNps7EAJ&xhcFZp){A^lHhG_IcfG+9f23$C#;+TeAEBoA zdwct!@LPQq8>u2qL16@x;^(`3HBVhH1;+Qcf0}DZs?bfUbITS)VF(E;p|1_ zTCX728fuL^BHaXzRpsH4yrCy%KK?YmRlcQb5l)(p8#Z=I86P8cNOkhpHA5xpl14BI zsEO-ZI;egQW8aTG^&sudW7orVI)1sostk~GWLlr{S47Kr$wnpSPZxRw8v{~b=cRE2 za~F}V@M33H%(`nj@dm5tjSAs>pkrSVa}%}tZM9paRE*MC4{Sy6JI2B-bgMJOIQZn# zaA@E2i%;pWaNSp`$jkvh=VxhsrwOHZR8S^ux%?3FAweQok|&GXb=y66I7ilAr>AS1 zaFEfO5=30r9r;!$gY%5qcm(#ak%gq<<@IaP;dgc&pTJI1LX%N#`dAmJ#UJzR7i3iI zb-*rY3pJ_?tI9so>IP_pfnG8%?bejT*1QSX-TrNB3;d{l7i%gq#;qOnM+Z%-5Ll(>qGGsaJ;uZfJf z;I&qzb$iPKt}{L=qv2z1l8d;vv);!ej!w_ec+oJGVz8cFV-{ZHsG&Vr-akz%=6I-n3utpIOb<`mY~);?bU@pZS&}+6n0D3j?mV zbAH)*pp(E$d(}aJtWS06uGON1@2B`wiBnOE`P!LxefbIGmoyE_5w*UoJ;qZi%(PRv zq9^pk8@7k?k~wEhsd_H>xHf0E6IX%HS3Cx9;11`B2cDw&hRN{EyzA{`irrXvOXDAK zDiu`SOBlaEk}RuScIR>EHn)E{6dhcy+>GIq0_*YsIw$+;`(&jP6UjT^#7G=?9ESAt z0$hC5r(QmeGF;>UWtyPfh!bx0dw z)z;ILOi$0*ufGHk9QH569+o)yQ`C+8^uOgRfL!i!xlQj!og6-jo8D&)>{NeJAwW+0 z1(sD+!u9k66hqF$KJ}gf;E`$nPvJG93L9bfLJ;@A*^vJz1b-PmA}93^t^ZFQ%pVWQ z|6Acb{9~+ZpYCCOy{F(CwP*9sDop1mF-@ihw;lRPP*3KPHOd<*SB6^46Smk$71BvY z>?!qBwUyR2+Eq|$mlxKM|5$MDdV$MlF{nFYojFyRxfx!}5KY}_xSRHi;AyU)zSIsa8%O(nTm-L$#fsC#g)*cftUK>R6u~ zby7cTqp`wxBzO$e3^o5`DKb4hh6oRzog7>-`HsY;)!%W?iV3x|uNDu@Jui(rArr!r z3Z4JQC{lO~7)5dcqXrj2h15=bQk(NsLWJ5N_8(6i|v1tsyB`9!7pTT`)}n0S6ecX$ejxX z(C%dgICJ^xBIIgwT1D3?rT67-RA3@F>)yrPeP&PJ}2u@`zQkmO)qBj)ItLdl9`md zkzZL>#sNeX?ia=XPT5wAId9JqUP-hbG?O^A-X(kpv?|DK=9V%xLCG4iHw71p5F@t6 z!pgdgj0~U!jK}g2(yISW;D$n`@X>WL1k#kPKbDkqD(r)2_dHnN$mu_gTc>|U0p-}4 zX<=YzOda=sYFf1DRsZW%X#tZUxR*!m{^nZIa`$Bi!01|cRn!Rzv_TcyIB|-f>Iv>v z9ZQ{_p)4`SQR;{goI?E>rjAHs?bz8LtV?ebL)mL%%gRbsVu=umfuse1=M9MGlb!Da zh1jk{HL5@kg_a|D@EY$!*jVah1gLdzjPvtIP6~mx56xT~OP1Gfc3W|MApt zyg&GM$mxb-LeZe&!pyz`6u^8YJ@X1Aj%*A6qNon26;Wa*8y~A|E$$MoF=1cLPrhbG^=W$~k7c;$=Id{c5Cdb}!ZR*ei z1_V6^r~>uFWa7b2A7)#o&PaRBo;VLq&DDd9`=87rON9$sU|9YB5B3<4@2Zq>p*WTd zcr1WO_rP4y${{_*cv8>8%_=23CarNvAe9zzOFMRl-c5(04X8MQF1OJS#PR?vQT(fJBSdYm1d2{V??F;vHG%Q^|2(qm* zLebC{2)>y90$~6lo2OIfKm9IGrShB7kxmbbfwuLHzD9qpZeFAr0;uN2-0Yx6#YBQ? z2%m!)!UGGb`=lmgCD@)2|&J8j}#Id?R z6rpc(T^Oa}4>UIhVLd>HT6Gn)$tUmFfW@a39mSWIl|H`LWGpQd54!Ybg3bP;zMEpM zj5dLKqvTxsXlDWF=*0PaYB=uyE}2ZDq5J@+yU`*lfOn46nQ`(W{JbeN&9P=JxbDdW`O$y#;V`uc_d zC{6D@qjOC>*ahmPnOK|L6sz7Qf`hOe0gxZ)NwjA_zC}*BzP% zE$;Te@RusRqCA;Hd0wzNb4%Iqqss{O<9q8fk8n77;dl7@ItXGea?F_Be3K<^MQu>% z#QoIY73Y-!NP&{{Wut18)q+nXZ+`PII^i@`sAn zY=W`xA30K~RE?jrGQB7m2S2B*DukKFi#D3&tM3LugB`nGfQZmWe&^#L-2-iVNaRE^ zpG<(q6?q;AKaJ7+AwxI_ekjqIWG3IN6K!E|;J8NidUPn!PVo(C^>i6p#rm&sKH}ss zf=uj<-@ha`F=UC{IZykG3+KH@quJ#%&dxK#Ru2`X5mND-WfGy;HCD>27gVxLXvjrd5kYb_(=*yFY4b@a#dLoS%jT%5b?|rHD1_hG{sp|!2;Nf3?h>GQwdI{= zzt-^ATqmo-$7T2cZ3R=hg2D`WO*cyJndK#vE1$o?KUNR`%Nltw9qc1DRF)p@#*6S; z3o0%KG+@qn%@Ku5=9?2-#f-6rMz^GhTyzsy^`-_X(RdGs79wRfwgM;C4Ab+Wy+aq6%8 z==T<2d&3Xg!Btz=QrHR}gsDIHe(L8xPR`HGEK*L6FRvQk7O(`V(JZ33fGZNRI4KD}h&i4A=Fe?O1=_*$C&X>pT#{@Q_3uj3pTDM^4*P0z;Els^^f z=_7PraTeP*8mom4Jn#VBakTPBC6R)9PHum2*kh6W^!KA9IRdizB%_HSS_OGn~% zj1dAqev`<^UcL2=KC^~wNG|be@HpFsn zy?)4w?rQnx{DCXEy=8Xe?3L;^nUwRc+`HLjBh?sn)sV-j56@LRDUn?6;L?pwQ5-&A z7N})(y8P+|T(0un*e;mdckGyOUV-mU*NWO%>KzUzN@_eID4I`VKfdiqfK-gLOE>8W z3?DKuN6$ffIP!*F`j?L|Bu7ER-$rXcaruj!bR4EPr5_&XSFBHPaE#y&pQbWIO`oJz zRJpqT=lp!m)YYL$Ce;?kf) zzNXgA%=VtsPMh|qPdvX$EhrvXRw8+*m{OX@uX5~Gtu$z5Fsc` z5Wkx{=W*Fvl|nFPHYy`D-IL2Sv#Q1f{mDAhkZxfO1lC+R>1pYK_mc3pQkh&{no4n_}kvETiq4GA0jI8YsI=)ati zl;9DqWA}J7xQwi5Mc#aoF$g+W;+g7I49ru@tYuhf-LBfJA;|)N5Ua{w3$TzPA{>O0 zDV*#Rz7k3~=)vkB+fm?D8_3**=QOaGFCZx?iGqSsAEF3Gx#tFPuix0yQ&E{9Qj4a^ zt;mt{C!mOTy)+HQg$TxQv<#1OsP1v)CPAOgA6+Eej2>Np$K8zy0k2N3%{%hO)!BUH z&vib-Q!gp#oXRdDQo!Yf3bND2Vr_~l)$visuw8|*+CLUsf&zYLvN~rSz;+;S@$OuE-fs&c!(_pv! zR0fBhI)2PIiWq8#%@_mIdUY;?i(}Y4(89vPeBdeVW`%Cp%qi&lFc_Vrq_k*p(~jxk zoQO2Dx>FRW2m7B%VasJ2EvbpoRB_y~KNI@C$!#5o<*ak1ABBC{=h;t5ae|;}%vV1; znAilplRrVHv~)d^L$9y%uWC5D_gx-K&>d^1QyVGmLIxZhN?$EiH0j4b)aeKRpm}(& z;V9!&*^iA=2Zn`%LHi((F;F5eV-y(RI-`YzAF1QLtuyD-aW=Sz-@*PBizIQ_BDx(h zKftnkG2K-@!9T!ya1S#byh7@aKNDq>i5=Xk6bS}7E$)3P=?yU4xl9;CL0rYuM5Ah{ zn*ReipM{T9c-p^kfJKc&;x%{DV=en;)0*k+8;QC8WiH8-DNKB+qn}S?QW@(iMIESy zS(F)qzgEU-TotSrcawJ;4xdcBv>)yS)IWI+VnnRmkc&N!d}Eo&6t}ua_6G_`4TN1L zW@cfREjhrGL^fdBC!KueD%%uFA($7s17mAzs1N(Y)Xtj{$SekC)vjf~%N6TyY>Y&H zy2eR9-uB!N&Y|t|_*5dYS_Z{&u;;aM zN-M5u)*mX@DX5No=Qaav7Z_Sy$gY+92T2-=)A=MMTTl+$RCIN9*p$}N%mg~_#afav zaBfYpAJG>&v&do_?D7>XtR1LWAg8gzvXi9h_C4Q+J-^$F1KYqfuTar*ws_o)?ZtGu z(`RtUNxz5y_r(>jc{Ust_qx-$q4t+$$|I{c(w%JD8Zzd+6(*Jcz^W`2?~?((q`WMy z<+L|@n;YMtMhrMAjNZWP!ohIxxzg0o`<~DK^XMk?%+4UUNm;Id*Q?o{)-BT*08hjY zCL^8HDhYI1CHOg(R!wg9mq63w{45_q77Lbc;(8B(bk27`?#JL5UhkmZ9BIm%D37is zuo{XlBuQ~80xVWuXpN3}Y@tGGrG#tz>#eV9^hrC2RQ!0U<&AFJZ5SB&X(jTpXds)x z-R5Ih0~3xLws9)NDexEz(#j3?IAvK1b^pVQ%n6B~p9*U=er}HTf$^dQHAy}|=NLfS z(Z2#?V`{j?-^9eEx6i9vYxI1~;@Zd_T>q-&ua~|!kPbe4&WB`n{6Y~JM_h%{Y$L46bYY$Z0jwLL{dR{Im z%Dge9?Ijy4>BYjpll@AXJ^H&UqqU*%Wsi)XCQa~*6J-rQ?QZuFjF5K#W}66->j&AG zJ}xlpHE~N64oWIN4)p+870+7ufN${}yY}7pPg04hQXbqEw7R+D!3{we$0PDCGiwD> zX(Eqv6!ck{f3>RqsEg%@z76d+Ix%k4J?E`e!gLTNyf_K#5eIeD%!$%_^=j}?qfSq{ zXPxbKx9!y+2AjW8m9k@e_=Rj1SDspm&sFNjzKlBS$2q70=3STTk(`s-P~Nt*t}K3Pfy(` z{K8+LT_9=Hs2hDSoM3*d=?~aBjEPZ6{MaS~Y>T2Z5JB2Vf{NIuRI+ph+WmM)FIm8^k(Il(2m_`7fY%@wk35)6x^o;?J*`=p0>uK#N2BVq zV=9c}$|Xva>*53Ko%r~p8(OdjmCqFc1o#K!dAY*(C-;XtXWPL7nNPCEH&s*KzzzDE zV1CH8RBt#y*d}gFo33Af*mbS~Sn}_IeiwnfLi^h5QS+5hgm~RZ3vh8)P}v1uD!EL` zQ<>L7NYVaaRv?n3$G};mDVY~kGavHlW8LlEL~?%iN;05M(|9LG3NP})^;m!N_wo?{ z_=89O#~9d;f-OQLv>3Sr%Isk&Ni(g(v+I=Pm}oL;XOdQ zqDu+B1b?!$h@ye7}3R|%- zG{4Q7Xs4OD9>brEM48YEm+0oLmNJi6g>C%tXNYm|m5xQM6m{e?%-ylK%8EKTf4

  • NP4h`|(FobXJ49ey7oK-N zCxg8(VsQf{gJ|9m^%HbpK#sol6wS zF##mk3S10s{T-lNpeoDq9-xeG8mHe8zC)M5^!R!DfC5g(A^z4|mvd zDj&U9$e6Yqzjf74PXe=%v=a(wu;=0fH)1uQ1*#mDqepVa6V7_ZTSvwwc4s%=DOBhd z2%o4Q80vLc!->~xb1kfE2P(Z>-uY`)w)y26lNT1{RcebB=AD%rUYq)O%FIG^PjrKO z_+6JgCEF7V1}nnccO<2*VZS9LCEL#n1|8(Juimu)XMYcf$ltog#$6eE7R+>#pj# zIZkQUr=P3O>+@-v#aR`~3@@g0{$)@18ha|v;eZuSFzr-(Ejm?^mO**+7k6+#P(NI5#K79pzB~8?O;$ zOOx_@Aus=C-BqCYK#Bd|bL;ENWXWVcaP3Q>EvvO8b($g~fw)PCBtsz?>SH;Bqj zTT@CNG=i5Xt|(3_PPzvOR#@u==NeE7(bnmyUZ*Kfv)*FC_f4)P?O|JP@ zg&wYOxc9K!!}$NAV@0i;1^E5HsJrEQZ#X12*(z=8<>$WF8+^UtNf64B^kWQ;^c->eEoHXcyK3plS;mh}48FuLVGd;j3lRc6@Qr+>M(xh~fw=s#fi!+Tb5MnDBn zMzH9a3DnR2}~{lE7qhX~x5IjBS}PlS#0CHIwuEce=vo@Ta2II!BCtAj(MKy6oWThOhGb z%7v1D%m)NxU!e1&*V=d>z?oXi7Y;YZI_wAUs#>kqk{U?suCma(!D04O+-vb* zlUqj~3i(6ZEyeBlt}uNEYA^diPtm73v-LvFbtk-LaIfbqh&hJ%PFp<^etNsyOk+X5CLT3ct!?e3jIoSp6lq57cVY)h5L6k4dR@&)2|m|K zIy^WaqSk!Q@;IF5s4sB&`&eV$p`GOO-Q%NO6hsW%=@cK*sLV5mD!ZaDC6SrdCYv0p z$0H8U)_iU9jok`4yb?R%RkHW}h!3L$UQ6WE%wl%;|B_x+RZ$b)ye(M2PPfJ_*=bMJ z)9zup8aol?>gY3*+WPljbYi->rntHFuLUrol^Dagg4|`PZ=tI+|USLxuOL) z>u&Tn>0H|_LlSedjVFl|ICo&z*c{u`K+QW;(M{35bZ0%4vbNw;cVBr^DhM(JY$$){ zFi${42+@wzkzsh15D2y@Q3kcZ*vc#96iS1clTA0gE{U3_mo0MSDSoP{FX7?3l_im*8YY7qIG@9LMiRVhX`$sw_0ZFQU~6IhzhNt+|In3B`P_<= zVB9%GsKVH}k6m)~*QC~J$)sB~w1@KY%qq-KaS*(loy0(zxuqb)N_9P(39bK8uMGx4LYc(+X;cGI#Sp*^IRUt~#$XK)%A8dZ13 zjOOVkj1^r94kq!I0rjK%)d*jx`;}`8n34`OX3?tZ+{#1U$Ya{J4PpYw)@++ksi^Y0 zDVOqKeRLL2Rdw>T{?7sm8+9pDs<*&a^OPu4`LLHP$=`kaKnv*46`pLFNGl2GfR}GC zBEGa)PlSBib+o!Cw;ig*ueckQ;Wldg&U2htXK~B2vC^z|)xqS`*MX|N7QeD-^q(XS z!IDRN&ixaY&(RxV{D>`0wog?Fmk)zq3ur*ypuXPU{Ac1rqpo~P*El^Y06l_C>?r_i zI>E;qRLl(Tqo^Clr1<01iq&f+Npju?N(FB43}oGBRg;5!c8XW=r?9~dgaX2<>*y0v zHfMExedPkbcH?E!+o~%-4J??XRgt%;78pRQG9p7J)cuXQBiM2ry8LpLZ-Nuhx{w_)2QoySB^*8hGmNf zjC@yaOn9rjt>gd{R1(|2z6~t%{d$KMznCbo-sXXMzePU9L1?2-$*_$g!eLp9OLci6 zkvc9t_Fe3(p!%S+9}z#L-G0L^WHy|t1c9X)vESd{s(eNQNeU7|z5A$^x?HDVn-eN> z)o0Z&A*wskFN7vpWVXkdW%M((anv@mTPyG(1uiGAcz)b4TUGx#elE#zWjFW8FA@5f z^>tI^9b&|iaE(*egO(~T=#;syteefA5kzc3&|z{tlHkHH|)dp-9ZBW|2A{eLvg0@yCHuy>_ti`bcuT`EiG2qt2O6QBa|prs*>|3I;Vv%Tw%)KZ*IY+QN*Sd*XS(Yxu2oG!$qn$E zYzTAp8h1+d3;LX%dC6FpoU=L=cd5Dl%r`E;^R(FA6!E$|5NAHaW$P$Kp?1_nt8xQw zv^^G`<44@P%Q~nOCmFYs#s_Xyd98d;#vpf~P9wX#k?{NsxQrJr%}MEf<+7IeQ@he6 z8Y!UJEsjzL2dDXU{~Kgrg{s8OG}`4ex1GxRP22SGF}UiNya$?xwpw6bNSVXCtT)3-#gH-5Xo0 z*Twq(t-SsQgI0BPGd}mS3VG#hTq*T#`6ODMS6&Em<(yzXoakV@?`nce9#hl2BxFBO z)gvN1qM;MHH>{TpPb;Zitpiu@;uO7uOGz4$3)?kiF3FF3h`;d_PORPmm44V;|2M2S6$c7)W%7JM#dv~ z8P?LWah!k2nUs<9JNv~sH&+MKQoz&E#ttH6R8Cx86C_mR`sjD9=U!JLaPG(S!Pjrj z*#C9xU02>)@@1OWorjQKo#--i-JOhJ8;N2YS91j=C8d`yzwa!K=;FVWOaqi(!K;bU zQ76f`m9F)o{5hww`a+v7?Z$rhLizE1A)BgAYIjs=*9}k z-N{{L=kMtD+0301_d`Kin~C2>TtK!Ls2!JY=TZef{4buJRh$A(ld(~*?`f?bgh3P>dU^JOUe+TI*p5z1bf6jKHFINsN09 z$I5cQw0RXzp6#vDo242Bye^GcA9VLWlOG`+u#1RtIo^Oxd0Uz+$HnWTT0;wEw;n$x z)LV695;!bpnd_?e&_zL~(R?b?8uS{@Hv2A~yoiVb{09SjOercY68E1Um`Wgyc9*QV z*VGQCFxPI{?Qb_8`DE&+*Y}2>rJqr+w_fE~WE<8{7_+S5{HFd*SPxJ`O+Q$2kKRl; zEU~Nlv>_*_=_7W`m=kqsOxY1F0lD$x_h~60)|CHIiS?{Qa<8$-g(jkXRtl3Y*4B*4 zoF2y@(>0Vm4g1$!z(jqG-+jGq*=Q%sXOLiH>_hkujfpw>(x!Q`5O$HxT#j!u{bsKpj(j5ieT;`7(Q{v% zeM|R`v(9;d1lt2FV0Mngk^GP&E%5Y6z%^z}f%oTGMwasf+QTj#plMF^t3Ce+ts8jW z@8))nf%iO~2($CxRVsji!AC=FtBWti02o2$; zf3j>5&y@(mawOwtK%_EMBZw4|cS<@4Axa1LL#L-;V9xHP$>)mRE z&7|+ZU=7jguN(3#aTi{S$u3;zLpb67U4;2$9%51t?n0J50{4UNEAyF$yp3JL#nl-(#kAx<*r`bN8-9>gncq%r%hz_^$& z+&}Lb(fboRN{Ty`
    %4LAGUH4Pc4ks`VV62K^(Vio%ol!R@g;jW|0hOc#p#tsH!!Gq}n_lq`;II5yY1I<}HFmc}$GBNzryNOg&v(1%I?Zzq9V{irbbq;` zY2ijzfA=J3HGVL4Xh;x#AAR>OEdP+t17ox%4l@?-(w-_J-wWIR2X= zKf=mN<4rUst?xAC6rr$cxduQB0-XK9fqy~|p|E0rw(*Vxiv!k6!;jvSuF?#( zHr>@_<&9R)}UHQx^?m9VSXMP>8RZIhfkjj5P-xDzwXgiL9(@!P*DOt znMu@htCp&x;MgCIN50|FyMMg#j0AVvAl#yEM#wReK~dPj;kUv@t83{)>0lv-U1sLu zg_rvCR&cc+JIzAAqwD~;y9X#$fY{am-B5j=foa<xQKPMp}YpE`i^B0TMqemQhpb zV{aA4M+GLp;;Qc#-xqWshIqiq_|d5nG3EYfVnmE6`KSsw>e zu#oUGBD;MHy|m}A1eTQ#F*h^>5$bx4st)IQMuNMrd;KX91*Lr4+$jTKZ_^I4=%c3M z!p20~(&cFiGhB(mv8+sr&{xH*z(tS7xH5H)zS87{EhbDp`?f#)g2)Bs1C{S`(8u=! zeAkrQkJ6kloWNO2sAfUT4h=xD0=vA&@)lTh08f049GgLoJTI!pFnE{|xgK}1?oe4_ zPwO}A6@SM-b2=jQ`dfxboK%M{qvg**A~k4yd3EQ{LKR|GH%_8PIb5w50W<(w+uuGR zDcCk{)$IYh(NOl7iA5eL&W$#!lHzF``mS3(4~L=#x8n-f5FRVf<-r&_d4>zc{MlHm zv_Dkaxj}lYBwBR=DEt9Q(Rh-U7k&FQE0hH{ytaF#tSo1hg>!ghWO$rNlpR8vX#bIJ zm|>VdrdG1IV&=Uah3m0W=CV!&c zUSquznHOPc?O;DOb7~bo#u)qdr^sz%@4p9I1ETzC_KFcuLtcQnZJnk&3P#R%^o}^# z_xsVP5Dz7#_ScxGu=z-B`x&ClIe|xRI$?8}<$1x{Qv%x;a3iKaBh?ggiV?`R=__D(;&db9NYMHxCK$2C6*F6O6R|nA(8VaO z`2`n3D$}#PY19c8zyn_dKXo;Gm-iz+gR^1u(Li`8DmGPTpbT61s$2ftWN@^@!$*iU z=GlT4ecJfgn4|D+RUaKm;rQy)f-|X6fxz4~LLwp}Lc%RJQP#Mdw!`8770jywF9p0k z`YG&dG25p#a&k+xp{M)j7BkF9l~9BwLwj#7peS@z%V%0oskfoj>utk0<{c9mMlg}f zL|t27^86l-eeoyYllq3Elc6W+jobhkk(*D(5p?IT_)UF>ZjJ{4Vjtw8mL0D;>QYp~ zjkP}jeu(1#se*;WZZss^H~2dX1KkGfr5sF7_WkYcqnB!`Ht_x03~di_xwvJ)){D#x zK^I6*%-;8pAMYlYu<>K1w6TMoQKS@soCE<`{KI9O>=B<|2qm6X;Aygo6sDd*6!8gN zbNcg(Q4#m9EV$m z!(7NzC?%;>jPx^|2e+_t(6tX9p}R4E+gYeYj9}*dYepv}P=9tC#9~*%(1(!Iij*|_ zSco!!lgDdIM`(qg&s6)*iH!b?RK=Xp>kkg_ z^Yf2WQuFc%yn(v1=J2Y56%{>iQZebRNeYTpunL}JlBA~jhEgrf` z|B2|Y`42(?t^tK7CTg=)(z>EEOdACRvk%pcj7XyN9h{MEQd-x>#rv z+X~{d`t_?BkXvWN3}^=wg8!){VDzh_8x#vXgBAkxu!KP1HhKZsN(TJVW1#p4+U zwaP8l_hz>in%lD}fD{X#TE|^k?+!XgFQQN$U+<80;5q+b z^Y-%VJSYf}JDW9xbgYe=YDWV|9&p4F<@&YUB*H%CS;T~z1wWaol2|*bmK`EBx598?VT!giX`cQQmHjy+$q>gHa?7GNOz%ew5;o_?>LF37Z5AS zUO1fuJV?SZ=x>pOOd=S-&c^L~A5)W<)73SAH_)8zv9-7Jq6a=Oz(25ERFzn|aQf{V zo_}>Nz$!1pSlw%wq+LtdW?tu)Klk6BP&<4Q91FkgOCh`-&7{l9m>G(jQ@?+^!cx_z zss6`AYkJn0c@L4yvm;*g2}9M3+(fNow}aZ7n0%!0k};r0g4iTpx-Sj=d3xKG z8GzO6_h`x4F*(c*xsxzfJ!bhwe8$86*_|O~cSocxq^n9c<~@2gzyS19a&tGj3o@qs z&cnsm@&O&C>1rWOTq3QOD$W|0dkKxz+*c0j2RNv&y<=D)$*oCl@eII?U_DPhX{IeC zuhXroS&I2o`Aa)kP?$rFlMbi%Lc|kY4sSVSxD9CzbP+mQ|1O{zwiA^ zdckX)M5A14dnIX-C=S1T*4L~fN1=2;b0e?*XFMWm?bfwRLoc0;(>swoVv5*G9I@_;YkptS2O0#`Ivy_LH+Kh@R4e(cBI@QAH&z4ja687@8yY+c!i zFF4dX>Ja){U72?QF&fPHv}KWC%RH=w^Uw8nN0lR5{{C`ELb8P5wDaNJ&|rrw(@2Hq z=;@xHcB)7$5bO*hnbvU173hV@w>w-cKXo5%I5S@DYs2qqzMFPqI~Ggj0E9a0HP7H{ zo}KkU7&VIY%uJ9ymkwZ9!=g9AK-FVH%*-Dc$fivh+0NQuHoPh(eerp-tHf{t$A zRFo4Gc!DR5xZ{#T`2KhSWc^?G5x{|e-}FDP{+1R1p8Mag05Amn`3j=``xS7lKVqp& zg3eF6-p)KR0z|)i6}PUS*!p)GqX8;muM~%)+anKv_kDi@0B?}VxYqgUBhLc8(#zH= z+lQV8BvCC}R(a!9bdPEAt{C(XD+{{883O}0W{G+_x)*{fzPx~n#*DQrPNvNStI;AI zOR3vLa))1Pt6J7nao)}w+c7oyLRO6P2l3~}N2^1aTT}W}T^0-Z-h-Vg>~2*`bWei( z#{-GZn`Paq4TBcZI#C9cUE#nQqa082pu+=#QKn91^ z@N#{Ysr})BTSmH_15z=&@j^jy}_7D5+ueh4r$$8-e&Gi2cni~QW#6P2}0Y(>uLv;74Tn#HZ zhayd{B{@M*g-7XD+4S_{vK8;@Dq>`X6(#jrtg!gE({w zECDQ0!u@eH9Xw5wgRjRx??qR=g&@a}d3<0@U!H9v76uoFbb`iurK7 z&^;M7Cs&D~RqLUS^e*ep>Mqup3D4tW7z}pWJ^dY8V=7{N$(Ld{?GC!zx7Q}G<_n(^ zrJVBy(M0Px`Dm>RQuaK*T2G@MDtUb_%ECIh}}eE7Dwn5750xU1so90Ua@6nCmq9>Z3mJ@X?;0=OW!Ira*usdjz+_N#ij&K=1V*l3gkx7gvifn7ABJk$q< zN=uzWI*j|P&yaE+)gh7J??tiivO#C%#=sOj8Tq#X%UEA6Q5?RFU~AD!?iR(x?^bsCoBGN`vDuke4Fr&^m-3pO;-!^?QxR5 zqnk1{K_^i-a#-CAv;l7D6*!@2j_41&L(ucIsWgh~uu(A1HumXkvp3U>({A^tL7}`!nEZ}7#Q#=f{VE$Lp zOD@v>rzMo*6_4++#7~>=Aq zF95y~dy9qhAn*q8&D#~+x~l;*v@n9YPO<*bCOR)Vtob16b17!?dmxRIQ2&OM*n&H9 zV?JlI2h$C9|Ms%Ep=J|0HGZ>0O}rhGL6xrE5lfgN_4Pr}1dRgruhiy+kVRn_upoYglBY{+{6HEp|8_f(|tep)rBlX%Il1&vb*i!b!MSJ+skE>gu{d|MkgI?m&hj28Jg?!DWf6bptIP9@&oS zS1~<-!@Gu8gy$g+jpgg5u)=2tywwiQ&}r-IeQ%zdAa;K+tR~sVM6@43=I3q#!L~)# z;x0GKjUAI_<`W8O#>K~^8XZd-KWxP;xjWmta7b7FJ*s!JMFtmPAKXTiHJw%M1|hquIDb~L9&z8^*5MJ{JZ{pksAyO zFK)?p9i2ioQy_;*OSL&J*@U)};rc%fl~sDnF|NWb*hPrmn)@w<7ZDsaLzz@kaXV8a zKxvlheUVyV*MO>u22v3`s=anVT@KF<-v&H7p2EgsOhxF$jrIx|d@IE$!h}Qfmrw6f zAr5Yu6c9&`D&tf*XWchUu;ET$O-Dtk7X@^!kVd+7gQW^soZwe1?AF@5*!=NciEF^D zb(O&SW7Wml2nX%aSUAL7|W zmu|kJOg8w3kS8KB>hcG3_d#eFglW1CSu~PZd~wc4UNX1AEF#Pkr!lS*YS~?Y@tS9@ z88)n3Z)BvXW(ib*21kznu>XC&I4(I{6gM!>@p<}GO~R6sYgsn$PN@H@D8qb#XUBLC zFjD0P+`5_`z(1eJWlioD8T_pe{QJGGc%w3H)-hdKnTi>4&705T6qIGCK4@ZtbU?KU zlqP@2%YX+4yo8Z*TLjUQ`6tNsYr z47>$QOt$>4H2X^Xoa+mJ>CZq>DGb42trsKjGC9WAjZ}F8xr$ASOY%J8W8oJZqKrH* zOf?rQ)28*PV}-0-b>8=FFO#uXq)#;vj-M8a@-# zv)STme)`FAuf%lktkUkYDmIE|&;J3N#giL};_Ei%OHlB3t?Md)0>yl7l(pIZmJufO zr zC(I*GLQ_0lC+-2m1XRVpg<3~{4M~6)lN;cDbayudl0~&rZOt{$RuRVRQ~m5rB6v`F znCTMQ{opdDMk_=V#^E&NFMn?CJAL;ogQ@G+8uxTe)9r& z6S`}6sT4c(z-2zv0j4kD{4*?oKK)gicUSe&HfZIAC4s~IDIl!wzn^Al)j%;bC>%ZA zgOr<19lOmvTl@;Z)b+4^%3Ao)R(D&Q$p{Lz7fvq|LL;OB#c1o!f1c#bt>9Y^;JJtJ z5;{A0!&B200sH%UPa33>#JU^LSKS)GOAkl{V}&CGV&Aqm!t0>$ zcl)x^X=qalvI@2HrukIY)N5>pJ*-Wz(Zfxv)qd}GFP;rrHx6)yD-}9scgo^^ zGz3K=Ww z)XYh?4op3`3uhW)TUSgUCs;p1OyMe3oT}gBx}u6(T|Hwp!~p$hw`9dx5baN89%y4v zmbY5PEcr_tckTWw!1)d8u_>aFa@i78RJ_Id=&=`>z%GyUpXLrxnK!Pp91d<$7p~vn5lx2UQjF z-8yt4PY;(#Qs3qIkV=El+kHc0Xw}H6OtKKuZ13t`SfQ5;yU+G@R= zxJgCaxrAIiXN_z1pOZ{GokG6k>5VQykhhv|`tPw^*?;8eA`g_t8c|VgDi%*um3FXp z_=3e9e>mi>3_ZoUP#IS+>krUw{%K*Y+TNK~#+^QZLLbVE8*kS0{q3N9r{~HJgaKIg zRAy41tbMfpx`?cv!M62Vp3OFrgiC$0PYbRbfOp!@rM5mNLbR38O{;c1N) z!E-9k{hVun z3d+Vzn=*0V*#L1XBla5Wvq9hsjHjG)hfdp_F2A?wEHBweM=SnX8cc#iT^kk<)`&ff zgr@GvCv~Y+40!B^xtS19y$pg0-0~D0xu;Tl-udYUSdiW#dWzVO&&k81)+rJ7;K#+fOu}N)*#mQd8uBu0B%xhs-Cq*zU{M+o6wB{)E@OyLIMy z2+?@Y8>)3I7jQR``Nv|iyEscK5cqp4=yp_T*PC{4iVz;z(&#){?P+e9Le3L9t+6vZ z|CYXir$>0tSM1DSwAkeCPLUNzFPG}1fU4F`%d*Msbn6aKo9{!=g0h>DB#$!Sr!hb8 zM{9$eNHb`#{81$-vxWcnZT`yNU;vIshXKLz5P?yElb^>eGSIniURCB?kRWVnWK)%J zJ0bRbR?f0KvY`4!^$uzwd=u^Xn<4xjvU`ZC#ewJBF&Rii{m4JKQ>4rJfzwz8bL$nQFhjgJRBvOMlIKYVB2HL5C_;c1OOZp&JJ`>?flc zV=GygI2D9|g5~-LW~KcbICP{m0G>NGZpl02YdeCm;2$)ttlCc@wfJv@plnlo54FIHuJJT2}$nS|8 z7dW6x(M5jzV9Q10z_8<;lR69IbBNv3b6 zzvx|&!!MXbxbq?JsU6!vTEd{X>F1~=AO?_-wk#>BB0`yn?St<^#fYIPp*I8|b{0;}%nJ>jw08<cK--iA<^4N@yqQPT5t?!Ae_{;LIEeS#lgc?;(q;zsZI=%+XQ9BgQ5t)=5VjAzdL zrYx{r{pK{!w(Rry_*L28Q043zd33vf2I|(T2ny=Ws`lF!mF7xg&kk1mTcW}T+#SOe zW+S!fD~a6{E8Dq%lrnu0-SUj#_x|c!6kNV%j*70~GvdO8F!+l;!0Ea&zyh-L{sZg{i7#nT zSYyH7>FO2O(<0W?bV}+T`X@yJ<^MZH@%c_N^)Ow@6iqpgrD+QQ>VuP#)Vs$r+VMe* z&kcnB-QPvcK_)lhcKh4iFn3jsYVvC{p%!BHrSHtHH~7+e z9UU*FqzE`aqUG|~M`fOPoaG%SC^`S^N8 zGBf)WyUOFeO37>G)1iH5>xkU48Y`uO*z~XvA|bLyrclQ<#D$0W*)qbN0+h5k1da>h z(F};W#kt^cxtAtX3WxYBL7>_f)WCLA0CM8j`rg|S*TOIP?Ka-hP7_*ASSo;A3d!y)QS+Llc^M^3+BHictlx#FKsBC0NrU-Og^ ztvv5_HE)k|S4)uU-v>I+41${iMR#_SkD?V+&*(pWrsqxo*5Y(8Jx(bt&{}U$pxRvAxZ-;=5U^)x(V9oDtYW%0>8 z60B?P;}c3}v7qJaO$sg3vF$l!?q~u`u$ymwUgNs*JYV?)Pnaa<&VFfVH^~is{;mC5Q!#PK2el51+6qvh1l#bu$k9B04eAf(XnSH#`P}7 zfUq!|Hpaul2XMgz7|}wKUhlF2AE%f5Og?M(~0wG8e_ri(+1QR~{=}tYm7ok1MVKP$^h72ot^s@qHpc z^QQ4lFfE!_z6(h*DE5{VIZTD2RDV|U&HTeH?iB2%kA1HS2IAspJvHwGw_khh|Jj4( zpTM>wig&~TL~t+w-e0dM)WCl~5~zT43;FCT(ckh@Xb@bwJrsUB`^(;ukMTx}@$bUL zb)V5ub%}io_3z7N&putf^Y`!y{V6b#v=2ZVRLf`#CZxOPoM z`jVJ+A(+6qy|_!1kI_Yc_@7=sBBcduK5GacraS?=l8un0T}|2-pcl(VnfTA-G3-oC zUe&yH!T!Yff!*G$W~WnVcbCnH<6jw0aeGW+vC6INUNG^iFM7h1K6SyFvbMnk9rJoJ zd6qjWEM}AVC#tebJvhblwOgy5xnM#nMi$*vsgw;A<<*U8)}CDY}kzIndT()^OMF#+5XHlYZMZ%-I0StpK;i9ZcH;PjJmH3(Wivk5Iu+aMRHz(#NIlE1P5$(3859 zbGbRZhFZH7+&0r32ija_C*DR11zMJ| z^wR~@qdoebK5)_B(31v41lpbG!f5N4k6En|u0YQ4x%?l*z8MjXDARY;@{8hYPZl~w z;9rx^fA3C|^k?<}iGCNDb&Jn?m#d=wn(!B{)w8AWN_{=_!xj8s>Ot z#}8HtK_hP3*x4og@-HDQXYTObo=A%~RZa-nVs@Q__Ipy%#(W$QEcS`{GX3^I*E)mw z`~M@+KwTG3^}jF;{0lU29p@8;!Q-@;(M#^}UGsgXUH7Be&aWsZnW^$hF>e09LVA;jC^Jl|4MY{I(I{=jvU zHksJXoZrZ7rw6=Omz{^cm~??#SSHj??I(5_QPp zdLVafmH0`Mf&FCv3p~P@u3}&-zS}R*^jF4~U=y6)3(eX6Y#@P81OxGJ3WE&{B9*)b zSUne8yk}fj!r-z4;ogf?Wmcdv_LPJo{K3sOl(t5Bcy#V6CJlbE_RZFHqaz4j+@H3& zp|~=aPq)`yLjN;W`Hn#U!o2m6CY>I+yl^A+mhkC;@c^z5ux2+wDp;1|g49-^c3&}Y zVT-m(-lV)v$mv>-AB&BqS8QB-ysF11YF0%W2}*1b2y4GH;c9E;digp;Z6Q`tFYrUx ziQUxD8T}Bx^$n1%KhX}M;I6Ki(9|KPik zV6BDp?mYg@G=u0_OrbyC1;R@uq3;K)CnQLxU!olmd@0wP~`A#xA=-vq5d5EAl4!dHr^T82r)%amz)#AyZw=0s|+HD1~pRzSx z%6bVN4qhGExiJmi8qgP1)h;#~k2wp?dJ(Bsz;=1$FpCHjqqpQp;G!KbS=idDt*bbi zkCx7a+q`o}CKi>%g`FlPaJbgFnnSekK{9O%h@@%Hh#K>Rj}0wL=cqCOrYmI_mhZTcPV6>FQZw_W|^T51c3dhnW-m7a4W;J9tZvni?mjQq` ziC12VpFb4Xp&yN0U(;k(CGK7-b{J;f%~;p_H*XSAf#pp|+5dOmB>6+eRH&}HxTm{? z9;K?d{=A;oL7(M#(vR+Qr%u$feKtMUOb^7lj*0f&V_xNads1SE8Cj(AUU2J=$7L%? z@QXJ|Edh4Vo659Bp}A=i8SMCC0x{?MD6)$h4Bz&RE?RwB=y^m;dhZ<(TH1@}#P4krX&!{Jo^GNCVB>Pgp8QJ@MaPq!HqfS+y4?Xo zS6o1_r7 z6}$pxwCQz5fq{yGO2bjk3Y)SCgILdVmvM=b7h80pMPJ z40J!POgKTH3VAFaU#=ej9`hSy3ZdbBozk z#=okmu%%gL-F-VZOK#;)&9;%-eL5zVjPvE5nMOkwK<4fEwUtugYI9_aj^$xU%w{$a zcT@CH?DX16e=**sIY~*=TSqoEBK1F#MQ7zx`+Zs4a3sSMV&5PS18>X2lG4L+k*(JW zQ!w*}PcSzX&_*?y=ab;>X(-iX)4iU2dMM?t#}C;Ujnlj>LbL#D)B(ijo@USpC1Yq`0FO zScwSxgOi|#Ftqr~LOMAGX{P0;jtGG7b}Ej6Yn&b6K>=>a`l=D9Om^>pq#FkZ&uC{6 zdS`EUR2iTrZdk+7ogx7tt7fcs9E#`4}(XX8eFD@RQ3=&zYY6G&86%Jlf zLvS0$4uOP&NCk&DASVq|uK&(rWS0!oofwmGJp99IL}B5Fig%L*rwSgx1W;$ru3`Qn z(&QbxfEKsJ0mkCz`9WVkeXf-obYRmdAF!d5?EtO)B4naG!~f>7#_3whTHSmCVQq=z zbgKCP*D`LIrSG+mN{R+_-+x+je9fuUIPD(QR{n>`!ngTPA`3GGcH$|YOeZI$jW-Ts z3`=%3?<^h^xVM!nzxV#J*!jH|DdS3cJPf~zXe*;0#@b&Ih**Tj@ctB7 zP8Yru2H0TH!2sFS1}+DBjp@QsvGb4&>Y=;-8|w=LgJ$F+g(MNB8AS^?a1;Za3Ip0pea+mrlc$bf|{*EiRh8jsB7!FStvyI2f|iUGq0 zy=HWTzw3~{L)`9-L^5nglYCE4?v~Xuc=6%WbH2b*#nejC4T*Lr!|$oLyI@+Bqs5fT zZjF1e^q=4zkWC>2Yy*)vkQ}27BUZ_WJ3Bq(GFeF}3zpM{(c81+uqu(tOS~nED>89M z+9~x>6HJ3s1m3jlK@LW~PCa<(N%6wj=4_k0#tV75wn~M$*;2stw0}=aS<1pO)oGt# z>_fCXg8IP^)8|K*J^ye@tTaKE2B z$NNx}EZH4d=bBwNJ9bG1T*Rw)pPDPSmp))>%Q+ucCm}c)aalv>8UyaeYaf$mSW}(z z%39zQDa&S$qGR3F-g2hsn3SGpG5*@j5z{XXr#6<-mAh4z1F%Cv$VLBeEH%T5U|H{q zW&DI3wOZVKDO0qNmDx~d2t|e;rI1igVwqwzQ0y7jJLki5Q!MVd3Nsb?^@`iz&n30# z{@EtPGJthh+)}lq0S~In3p9Sqgl+GEKMlRWz4m9^7 zMva!@%zB0f`IqU`2u;a&+zke{F4e>21-2_{V!x)ryWb`?#VMr-?)WDu=cSBZy6;AQ z7Q0|*Jl0UBgB6^Eia`gp#upp5k@~tdb80VC)y-2T!O=j^6TvAevK0-`z7nbP$cM@y zewA?Vr7EX=8f8BfTE>$vBbTyI2j#tA#>mCM5;w%LZDy{0xBaSs*j=&(8WCx~lT6(f zPxE0i(G3%gTS6GqLiqDd#Fhfa{l#~o$f5Of^2f9_n^}o`6ju!o9jz-mh$>0-wRWbY zcWB;)f^WS$J!k210c~XXkpS)Fsks?gr@J!cV8~4Cc1)j5Ilpz94`Lv0Gv)p#xcr7h zbvSxjwZdpi5i|(V$cBhqT-vw2tLr=?TKH~8IO6p|=p@EFR*m?fftWjDwj2{TZ5v0; z3-njPdG8eO_iVM=20ifoN6)SgyuEHOe^&E>@*PqR6WfDt`Jm zysJh0_2&_X1{qP;3aZl}HCzzeoLT?}W}~?gm$}q4j3qDicbXdf5M8X!P}OdWL3ANOqoB?`WgHofV zSQPA`g|h8+%ti#2s^Q*M zmcf(b;|36IW%TI>&|Fxm_1DZ#5Ie8LvG2+(fi6pirQ*YRh|(832lPGsdzcu`RdnIdcrFYRql=9pSIC2V6e&4cjLIc><*xht611F!K9%!1E5Dbf#U-5ici>mJs zSm35T;VUp*JayZE6ePnU42r{cz;+&?oi6>5v3eFNpXa77s80o0^|1wC!4rV6#k!@? z&;KtEtdE8wT0-&}vNeZWoLx{Ew15brP}Kxz0_=w35*C*PSmA&MMYJK^y*?-cb`Ztz*?SXJW9i+^4cNRE4)chMuz zGq7rxSafGY?2=_9`;UUotjWXX5TI@=Gek;R`}1ev<>kHRe8ZVa$2Ri%HA0p&S2rNQ z6$fAbRX7XIjjv*DQ|=pOwg$|%))w4TV1mUZCB;KiI(xf$`=0m!F$}ae6-P&{*U0~5 zX=BW2WVpCr3v;vm6^&4%&rd$nX8VJH+Mu7Pes;Ki#RdcIg(4Rb^YIYPeD&Er+2&`k zFJU}O-R~z*n^E3g`XgWw_dQ7MLpE$O9{b@qAkPW(K%`3m^`IxW+>+gs||ox#QkCs(AQD z`ld&_{Jg~70U;9(M$!!g@N3&w*BSAB-9R4@PZ^vj|K_lWwdgeLwp62}G>VjR-)~Fe zB!NDz9D&J)x)kgjd?H%kMD!?+*(*)kZ%v6z{)&}(L94&OImbX%<<`DHl1UYJ(99r4 zA36Q({F%r#+D`!w!AS9yC34=Rw$hK6JxAr2pbyzQJ>G|VbH{4O>xdi@m-Ue%k&SWN z$T_1$h4n5lB5eECU$=!*>hlvVy7lB03_0_r)Gc0Hg#QD_Qq<2Rbw!bT@rN=e_6d+% zw{r%6{o2~vbPYfcm=8f`ha5G%4O~Fcow84<>S8gn!~PHzJ$}PYGc^-4BBI;pc@Dl} z@lCv)RnsENMUpZz?wxO!a7Q(P$nPffC2E)8KHJsG`d(Kw7m^bNU*#jDZ9H^)r_>KZ zIls9tqVnBVrA)aD{+NLpd0IVmvC~(VF(66?ZGZg}ELR=KHw&#U7)*sP+VIJV}g}I}KPBvc98r^U4nS@h$m_%RRq|f*AwXm0ZJB@TKh0oz-`5Z#r#5 z#P7QzCo^hsfQxRilQ1c~f{ty+x+6se?$bD8^fZ4fX)!K@0fF4)SnC~s*Nb40T z-soJ-C1Yq+;8%m|S7TMfZPS(sZ&&E=D!{Kv**$G*l-Pq1{CTgNpiy9 zb&vF>G6*Qs7*+R-m4E#+~?LfhJ2tU0cIxr;=&j%Z!Nn z(M+p`xVOd(istIcL#ylSd+)6djva7`tF9jAHfucK(+9`*oNT_0)mHN)N&wl^IdK{} z(T+d#7u>f}>{`fq2)D4{LZEv@<*LuN%f|Vgs>kDKalPUlc9d|dGdILG+%&rnAemuD z^(nm&u*7)R*%4z+4i0KycSLb-GTKS8xo9o_vHohuwt>|4aI{l%M{2*G$bK*T5%{u< z;oQUXd?P;Ia(}-Ie$ahT?gKAJoRf%&8ulm_Hw63ov9JJ;!YSQqPqTQQKh#mnm+7h+H0x&_V->eK}Icg_8P+k5TjS zTo+Q`;C(mLC9KW+DPwfkJniVU-PpFqo*1d&!1XP)gE= zY#eaGDfQz)$>tG#`Mj3m-~h3R@oBJkifi0pZL2G5^5el6ik&RnhNemS{_oXaY){&h zVTrn!NgxS!{aPW3Xo?yyJy7`|6YBEs23=UCa#M!GRo7LFyABe&jH4V~GgI@4Xz4ZE%&^SWcVI(H> zHl%ix!2C7d1>ogV4AM)`@bGcZ@R4};81XCVq{F-@oR*1Z2;X(36ob#AU;D%<(oWKD zXKZ4(!xW@vq1^7Upy4;Zc7ooBY@SMuIF*7WUJ!$GNaj`%;(F(ioRRc0crZt_q*XX@9k9S9tp z*%_n6*V=a8>BGs?)}mB)H`nYs9GmAQ)aOcS*Znr8TlmJ5{P0m((SYL%g>ZSF?Mt`n z4t|~S;t}^Rzz^MQYHJx>B$q~sR5faA&E7?(i+|^vQ2cA7_}H`@U(sK`NTQjWHep3D ze7Lz-Aj5gfiv9IoZ(5g3a!S;z^PBno-+l*PXXu|pJ{eSYC^~k`kh@5H$a^EjcpAl* z==Y&p>9-A`k>Y4S$uxl$@x+it$$J<+LioN`(b}wMR1{fSYkE;w0dc~y^|dN zY2cf3M!UZ!&&2r#viYnRt2Fy8q+HEijy0E$+VO6}p7954_g$VwjIDpqb4;j-Xmz*O ziO*YdMaC8}%OO8ZggJ@5sdg8eQ;Z(QZ3Xh6A@@Mm=f9MoCrt5n7f(*{0=Ci!G4Y|w zk8zm6ezCUC;cB?4+ao16DkYL2)uR&|KdAI`V9G^J8EPyY9s0}8srK{vp zGv=19fgfVTY@~IDBKtQj-zEv<7!2Si!CfMI!2XdsE=nHK9$S*G$eDMoC4_{;gT`6U z&0-s}c#B=t>fFr_kMlZdNji_Y{hMM>d#k3@Cj4_GhUYTh4rX-y?$X}vTdQH}6C$sY zUJOSd@@?o*j&=fZgy}u8{!4S-Z_MApkgY{&K5u37sxFlH8MTopqaVzpiun#q?Me5* z@?CHDmt1;!^N%|~b){ux;gio|Pk!swTy8z)p7ltBZ}z%q^@;C&jlSirC_h<%pwewU zBuuX4NGm+DGBEIu<7tYs^Ts@!R&EPYJYMQnkB)n3lo7PIMF)*BL7 zeyn$d0g;WtY{c=P56NjNKJZ&t%50nAdjnCgYaiF%Wv0pS=u^PkO6iRylMX{mihb!? zr5zjNRGQvDs3^-<8upW5B$%P~)!tlXfpyICB}F_h;azFz9$wMb*2YM>s}VjN25X&5 zwjlQt-%llq=xtUXegA+O;LS?S%?lj(H7An|w3Qce_mO_%^65@9Phi#Oiv8v332%oAEeBG?#)_$`H0CYB>rSDYRtev_FTF3w zPOaMp$K3OzKk=8AK2o;XFn%d8bwPz|%PlkrpBA6_ga7CZpavcR- zUG9i{IymT+`Kre7?er|dtfX$3Cx$Kv>|P07ovVsxVQHKTD?TJFKNLM2i#bqcA6qvA zZR9J?=QUT#Jg7vo2Z zO}>9tkn_SUX>A)P_3cz7BKl?oa=dcyXntNa$#cZRs{E`X>9XwLG1@(~4U#)TJ$~7> z#nd^66--@O@tkI%@w%5Efk(}AAx)+dr)oMbSv#y6Tk3Yq_Lw(beXk{}GXLvDMBpAO z$?t$FqFKDvYz9W8morKPWV6 zDoAx*iSeC7aF{oGNA*a+Mir}SRJmPSJI@aG1THj6N2j6f9&#gK_v~qxih0CarRuLm z%w48dWCgn?e^^ZA4|&9CGvHIo@t=p_8Q&KYyKr|B9iKa;ZljntPx^>Jqrd^P0`4y^ z;o*!(Na4 z@rss84W|Nd1TGXV?jR#%zIgsPwwuhfSGg?rv*RqC`eR}7at=pJGA|EWofC2--(Tdc z@n9E%mvZ;|FZ>r{4vu!564HM4+8`;X)YiU}fzLWt>OLDzsSiK#G_aB(Z(1EfwkXV9 z+N7GQYT4L>R1)DQoO%h8MIv0QfCT=@)Lv3c)wmMwR)|s~4r;#G(rhHd8EfS-AJjF> z^l-M^+fldCVN>~pzv-oHh%U{Hq&FI9(ON>BhaVabiljQm7d_8`d9LvN@LlDvN&sw? zh-=%td$&zwG|QfHOy^{*zvmL#TA}NQkK7K7F(fP28+Has+3CedRC9{Gw?sv4GP93b zK-#}PwtL>js3wrxe`9ce^u~@P%OE>W`zzW>ivf6mi&{Ea)7D>eC`fNzB(*xPBRS(8-X6hJ zX!+{j2L%qVSjbuA&y>!TjEy@z@nSgu^u8fLa-I^!?!1a$1yk^W-is|bC>aE6nZ%pU zzp>P^-tHr|`}&^lv5*~^I`m_2J-*R-m8HJEJX`rFc*j$=pfR;vLY1nMwt$T{c z-YY(ErHtCL;OW-21uNUATb$qlj>1v!%GdBk(oomhh>!4$K|Btehg%5MgNP2L>NW27 zASZ3rfzhsAh{w7vRk(t_d=L#OM{3{adz!OMSy2~4jxmNGWqt2}*F&pMLJA5cGMq)F2d{SP-8xR|-F^E{8=vG4mKzkJv;bCsK|48A6pRrZy2Q&_@w zDTx>N&8?07UFz7+E2i0R9X*8HhmvLz%nYvHtdO$#de`QA1@^$Y}0Ojoth~a#)h%ewm|ksZqqePU;?FiGB;TJ9ix?PcM(F#Y0buCT1_gWDy?2n=va949M_>5K)^&p0^PbEt-T%{ zai3f_7X>8A3p4BVPuico7Sb4_Ryo|KL=JJ{sOkI^Nk9G7Z>ry{Pny+nfRh;?K#+Pu zjN%M(IQTVY=?$JJSlK*c=7n)=$*+g4y5MPwO(h?rS6ZRp!@DjP=w@{LiJMhA_vd}Z zqDLPt=utnP-A_tA?}blncc>}LN(CBoO&TU>3JcK3>2VAX?Q{Z}NypIis z9Y5X_sY)JMLh16$SE(uY^*|ZD_vOy!&zqq2YS^({lW&Keu+|_m`T)};V0+0mm#=}< zIUvdrGg`gRX4nsboeZK!ApQ1y zUrR{iQ%NNqerk+T5VFl%*u%_)p(bx@%fH&q^it42@8u)&u0ghH$V~5#db`SfpSL3- zRlM-=;+S zD0}pVaGeJN$4)|i8R8@gezW?hT4``1@x)7g;Vx=k`_L03rAgXBi64Sm<<@t(C;={d zCm2+w*yGwEOHtv|spsOBp7_n&K){4o)y==j+N?6M=8%PhK>&Qj@oj&P$p!fS+p`jI zyxu@Q}aAYlNA4}}R1Bz7KB^SfKB|a7 zLuACpGJJ`Rop>q(uH;m?ozw-OLV&dPL$ktpd@H7U-)ZnI23#{tCJ>%wKCzAP+X*U% z#eVd7(IcW4oE1M1{249o>2Epg?e8cxekMoQ&pD+kiPbRC{cf@PQMKQszWmx6)mkkU zxu5thF^}%?CTghWEx@{Ue%6#E)*|)Nhh5fe=I7yZgyMzqj>wes08=0?_0LQB3L9^L zXioC+@ju2RVcScB`=IlhkAbw2N%8UaK<+1%)x~`S_rwhmoK{DkN^BBFE{e{TXn9Vb>{|uGqQB8vEfYnh z`lD>jw@p1D(BZ1$>t^`f?7GAF%E+Mv9L?WM6;aF#0ld~*g;VMoP5A~jO9YmB=^xNC4ptQDv;*J!uD8<@1cXOH;g zAj+&$gUQgZvQ6RlA?nT@vp&pwC+9Wa?kvH-i}bG>n;cF4ER2)C=b*%X^vY5(-Lvef9mCLrUj02;!)#dT>zls+oEozWFh3fTa0+v2Z3ClascdiDReTSR!AD zHzFhZo0otJS_!81Ly**U!)x|%JDQ?K9G$yNHnrJJuLpPLS~Sc|gT^|h-rMZw(7wPC z_l*@6^^_dj;;ja9YNR)*l&wb2(b0@a%!P@eSSv+%;@JE{@LE9NOU{D!Hoa zNEA8VTfO_!b+VDvMzLMhSaG?zXqvntx4Iu)buW)6CAs~XU5bKAX0&!vk4Waj6iINp z9L{lD9pMj3H2lhxpY5R}NPUG@NrqdhosZ&b|Mt#aZNa-Yw8)!IOqiB1tHS%*J$BKj z6*R=j&YZe^z8tTU0M@q=m;fgwFc)}lAX7(E28gtyIk2`_nTNls^F+bV?MVLNfHPIXSh&_MIv zvUrs8hgUmZO@ky34nb9&dmnPb2&cKA6tn#d*$;0Y_}$ow%(F!CMRyD!Th9<*e)-c2 z*9Ug5a=!35f+!!?9QN-Gtjvras5l}zzq;j&^0q=~q+O%-do|m4lYd@+plvSVhDsVI z3$M>@uj^dCPGC>1fzoRetQexDA^LDl+Zo8EBPuE|we_pfbNUtE?TKlqn11r6=Z|M} z0xj^oy3iGft}PkD?mRNA0oFp`iatkML5|~)rLnB0YUA&3%(HkZSsWj@x7=wCDEU#e zzrRl%(^qeNJYz;lmsCAY5@aOoNaDt%rmiM#80xTUikUm#{enuZE+p}(-evffQ^Z?} zfK`%gHl~ znF2*$Vli(vJGD_dP5ZdZ>5sutby+bpS1n8se!oW+#Ilg9v6@xXdAX!ZdfL`25=@gR@ECMrqnv&Q6dQ zLUib)U^4qyeS}r%q)@6qxy(r`p=$aK2gKERFc*@+DiG7`a_-kPPb{V!yB$dmiCglo zIgDrvTzj~Z&t7VmQq1E~=~B!HcDJXfErDfw?rA{=dPhcP@&Fg0){Lw1j+te4EwX(G ze+#m+zOF-%K{OM4Lm-$bd9(Y5Iv?ieYlYUNEakVfwKo5A#V$oIUBd-+V&560KJ@IN z1X>&DYsr0rs z?T>$;((yS52-0J#F|v5!M0Z&dN#0RNq4S)3k)8}rTH&jg=@;Ex={vLhThoYVBsB_d zpEdGTs_EkJ9%%(8uaz6_^7(?C}SeP*)|6H^r56Sp?44Og#M zAaV+D%zVO2C$Qj>lrREmM*0>#1urcw987Mt-x9BiqHWTT*dNIy% z=ov10)BgyJZxivU#nki_n8{T}I~P{8(l@13N9S&3B7mdo{?lS?6Hf1i3`3Fcv&t-| z%XSCJv_|`GEz`db_?3l;Lnu?pS!nRa>ntnE$+d1MHgiT&zTe$}Q<)AmU%@}26;^SWED`|5*)_H zAeLLK-aJ@8PT+e__vrU@9r}qEg7ak0RxKi%YK3|yS{IY6&%Des70uN|6=)FAOAw+9 zv_Leii?a^Zd+DvKS)n1}KPKqr`}y2A8x~rJy^4lm-^u8xbEj4WN{1oM8i2B*09JPW z@f(a)Lqfnoi=lt`h{o@W+o4>iBg_57ZyJ+CZpx0VTAV9U+0T3hD>^$0US+%y5SZ4* zXWKL}i<7NE5)Iu^q+cR`!cQw7tupe|iBk6=;+v;c#3%**QQ-i@ZE^c+*wH?v0#DT5 z4P5f~xyvytI*BIthfm=r!$#gCueTt_t`il-;5Hibw$u=-sgEt9doWB-%$1{oOE2mi zlFzUGB2qm|#oUE>Ka}OrWlW6}@YpCdW)kv%cW4t~ICSOPai;;N)4scMjSV4&WTb7s z1iq)oX=A1iw9U(2ZNsNl%2_?$zmoByBhbA^pg0D?+YBfP1+`TR`vyJ?R4g9&w2|yB z@bE-VIqyI>?gvDcF?YC5mt;xB&co9&C+T~~$jez@w04A(>Jodd< zwmk}5MybEthh$7Q-M`O`ZTSu6S0kC@0FZ6N>BBYoqffoWwN`qi}{OrALd7}+e5*2hfD1t>n8Q`Nt!G< zmU{!mV>25>5bPE>zXn*;SCkJE{7To@!WtSm246GwcBvUO4#rCQG|+v zpt0XnEix_LqIPSneexh)_GHXGfa*I#|qC#!}{tz6s+HUN}~E!Upm?x_Y5kdJ+Qu% z?bv6e)J>5(UqxUINyv|I;$0iywTrm;F`VbiQC2eF*rbu{24M_-h(J%V6;q!C3hvHox{Sy5=7oPeQ>RIZ)RtIXBGe&HPwR$2XtuU9kq zqf!FvPH&d>3w0&%k^`1^{EBn&I!SN!uufKQP7~#X}2^?3|jLE@>Uh70FYkjTnZI0_NSnr6ecv#9liTgO%3wLw6xv=1JDkw(4!&81I>DA7!7@rHb< zARF@N7KMr!Wq_pRLC=#6l{CzPDae{=Y?X!1_hjS1%bPCuPLYEiPmw7IR76YQwy#L#uY z@ea=FH9Mgo>4ik1%J1D-@Tg6*wrsH3i)fj=reBg9{8;n88-wLK@mE6m(5O^24Amy| ze)PPt((k%DDyh9Ld;DqSj-tH%Ygqh=ZRi@r?3*Zr1$`{fv>KLD!Q4qX6-iOT4wXC! zi!fscEeQu#L@nZEkq#Sw+1hMI4z>D|bA7xxI)vw4*VORT+%YR?Eaq?qmDLPd-$MAq zMo1L*m9qg{C$kM)6sRCe>ugQxWGvImWbhrk6G8~X4co5D0kKX(v?lHQg=>&|5lnh~ zWlJy1AJw&Gd$KJK{`!8*F^Gn|_@2<>QEzC3FH=fpu zk47Cgw<2@vb&PPfoop_IZA_~ zt9MqbZ71jsqM_r?_JzD#aApSU3C1OU?XV-kofG|fKP|XjT+v;iN#vXDc_6orQRBWQ zZq4g4(wmW&E5N;5h>L%_BcIwo`kWD=96DY)Ldb~WXq9B55OvH|t|n02kvUgEi(Jk2 zfL36THBsfg{5n233Y zY3AOVg_C*lLFp3>r9mcjs{1=zRhiCcp5fm|}QiGd4SMOP^Jh()nSeB!$%Pbpn@iOJ!c zj_+$|6k=x|_UUUERs{8>x!faEmW_d2?Tz(kw&P4QXaMfIJ>*k^WVD&u~@Y`yIVZZ zK(J#zKXbS2&GS3FyY;E(+wfXEs}$?_5RocI382}H3N9^^VyIOx>ei#*IF#Kp^t4YF zg{~hSmq#YjP=f7LLz*?)$D*<6_vydD{7_~d zFQRs_Pv;1W$7H}X>*&t6 zt}G=1Q2rl;Tr8!t0AopAX4et1U&=&NuI^~Pr@li#W3zG+$kjU?sWsDnrkS~B(&3UR z9e&|gi_bW6RI(}P>dn}q6K#nLVJq!ThscpZd8f;03_}{2DyX+IR{^=#Ngg((C7?8|Zg6N>(D+5h<|F6gdegOZ%g*{CR); z?CSrKxKfb47%YKfy`OBqj=J$g!~%T8?u6KKOY8iBa+1&qI=zSm?(wEo|N?^@AaaiH~o@9;fqoQ_@Rg4+IZ7qiDlj8 zdUk%B&Y_*m? zNOe~8spJkZH!SbGbabNr8vcmX=gfb*FuKi(1^Oj;RbV5^UM+dl;2{Ky;$c7T!*c>f zbf^iMw*m5a9KdPPzN;$AHc-z8BbMRt6#Lg-89ChY5Z46`s1XXAj&edDL zZu!6ovE<}xAF|7GC^r;hw~C68i4i`{$Zl+1MLlD8LFLfjSr&2ug;p;ne^50!7%;rM zC{)grDRsqpFa=K+7d@AiRvf!#cb9At=K^z&ODBv)*FJS4WolX6R{$Oh;NkgP_v#N_ zuDpTN|1DjvdeMKT%S{)U`QWB^pOfr*4AzJlIg(^!p}48_%1x2I{vuF4(isn9@^wn& zd9jm=?$_4wS$NNZJ$B%wHMQF_yH9eGL?)L)iX8>+`*LghljG_~M@O9b&|Gsm9sS%R z7bTAnH!rjn_J7pocGjBwrOiEvV-h`DEh6Eu#CN^cHegSLWy$vrBQ@$Itq|$UI_p%x zRvp^vqF zp1umt_SS$uzOE|j8TE+YUI*DY+8|rd)@#SY5FCVYCUEet?%I57yGY3a&a9oZ#zpJZ z?RC9*cB+Psp`2zBppw5`>CRj3oORWRT`LBO67%SJ7kzOw<|_IQ|73L-Zi~eh>dFr( z|Iq2sAro)8qnDu?0>o1k@$z^HT%~Y?+ZVuej(%O~wI{rg(AEC%9*C!SKhsc8zoQU< z0nHNlQ@hwOw|9Q|-#X9tgH( zEa}=Gpc&z!+sy-$6%{3ECN-dwguqf3LDy^y4%RN6Dv@Kdm!Xr#;Eh$*{TK(Je@%K@ z;x3GBXHA~hfI_(Wvmd$5^F#;BtqZ-M_g*SXVyllaBJSVE*|&6d*mJ(-;AJR<3J}!T z_MjGZZ|`?68-CN6l4K+T_JLbb?<&cys5gaO_aR7~J*Kxl6{1gU|K9z({@Vv944AEN z#b}olQ>nc|!Kq?|1Oswv(Famp^Z2MJ(y7#n?;2|Iyebr3sn}_*RIKb!fN@-boIw<) zv@G_``=h;>k<=)!(jJ0NFI4Sbv)G%f?O|+3V`6@B3V-CV4$f#6bC0rB0nfq*2f#^P zOJ9*vE!fS?rZ%16*jn2_45*)^gzSj90#30oVoy_@Yp2K`meL&ElHDI(ee*JM+ieGs z^hydHwOit@c#t$I%>P8Sb@n)X5@@y6xQ~7X{NZ zxnJxN{?cK+D*m5hGYr}v0^;Fu%=Ml!cd8l)z z{m_yA{BTgiOd#I)halaxYCRD2jBh|^poSm!LI;#>~fsxNT#bTCuDv)$%};+YpNTp zCz5L-&$mzt1GO?tfyg9DZG+nf(H%kam8hW7U(l+GOXYcs$eNw+Kvsq3YAdlBImOAq zHpDn{&jAsoEpydU;AwWccb0 zs%y8hhn>?g|KfppG`0dq_@P!ftZ3YfzlL2zyv)h0ED09$PAIkdIxt^&dtHqA+3brq zppW%0Zx`=78@IHx=7OxgkP9Z45-UrUc z*T1lbG2Re2cgX%ytFC)1bhBVkqR-F0Rrh@;x|mq3w$I6l^Qc}5&%9^hP_KIo&ZD1jZMN4J2 zM#*AV)3=(vp#1dm5RZkrMj$4gWyT@t`6ueqN3+iK>!s!1Bunrv4t1FaZRrLd%+Z|I z4!&q5)n^!t&Gmkqm_yx_4O=EACg&7>dKAA6c#eC@0@7LfwPjBNvxBDV z2QH`yv4ZUIu;}{i9<}1}?m$AV5Orqtn+LjM%5@aANJhI&;-h`13$-k>~TE*lP4yTm6b+iUpX0#vtieMkL(UwMYLQm8@fOqMT_t_qBEIyEW=hz z7UzfD2kA12tcE>@&+F@4RjKLf2@W1D&E+~J_g3*p^G^;mZ-jUVc4%N-m>U1UL%@xD z$eJO09Gx&{1m6swSwAH4Y(`%+e$hH;+tkJ9TSBc9LIG7<{`c*|@MivS>22h_KnU*c zfJ+9)jGacpT`ZVOgSR0UEG$9=JFmH`7^#AeZNH*tTqTUD>1T_xKUHp zT{)5y*GhPT$UEkJIF8?V4uqV>UezWP;%RG)Hy+7R^bWnnc^WLzG0i(V?ZP9kJ}#JR zB+s|+G!u$Hs}3RP*j$A(-*hd%Gh&_0Zl7A;=vjcPAVcvB*fq`$1KrPy#P;N-WH{US z@1Y5@Dt0lnjf5ZgPC3v2xV>;IE=_!>{esdM%1wM6zwM{>{niVus~i> zjI=WzMR&ODf32bWeY_KJH11_#j7`8Vo%nSqCnAq&N}fpX^mddmhGN8xp76-h|JjJ} z21Z``cQ$BH4jKE{0s`oXN*<1Ca4G*fG{)FPi}C+7J6%ia}PFiG*;fo z#8h|UZS)ksua5R(3-g8SB(S_f(`u5T+)rNRsHS)LSbsMYuR&{gkS2{IXs4Nzl7iy4 zo=gJQ2#xhCnm_J5$pZ1lboRJZwH?xwHKf3!yv#;Qry#N#u%!@-PONcaU{+7NWLZqO zb+Wj|duvoh%#D(t_QyKw>kFb-0Tqm+BS31!!T$R0y@CeJUZD9pS{4xr;Tv0qzjSLS zt>!J3V+qG)d!bbm_WGe<-E4S+0Mu{mB(3r-vufW?RA)QziwoG#Cf#x`6(hd8s*Uzd z8>qRt%=8VO?$j+V4B8!ai*72Sfz}eU-QTe9wpIgab>roke#UG4^9D63h+w}iSveE> zU5@s-Ha^+dx4G{76$2jBnpB(TK-uBQ$+2`G2YSKx+jTm6Cx$}&`rWL|vdo~pr(t*E z(EEAQFLA!tG9CCpLu`^ST?qWBOZj4K9i9Uuz*=XP=5RQ!`BVtM#tx3>@}~#?G@1i2 z!enVamd;nU#*XRqyvQyU5!%@$`%{G^@ z4&W!myaxL`&VpYPRYSF7YfBEU_W+&bdA}>KspJpAGg#scz*|)a>Ni$p0-fo5j8Opd z#-j6@O}V*Rq$+jmz+OAUyl!=QEq**F|;_;*42JepQE)p5_s*a!f^1)>?G)*Q@TAb!ll& z7R>bZRmai(u)Kc0ejJUq)H{=ZYVx|($5Go$jLc100X?y6U#UL%Fa|0#6;+ zGhG=X1_ZI)3>ND5cy8)t-ZI>ckpb`F&(ON~KHTy8^{e2wVDd9r=!0e*RlXN+1WThM zwOzA!5iZPuM2NzMf+0&j@I^Op1M&PDt?_?K@ z$(UL@>7b%NTYvN{Fz7Ozu_fd3U9nd0d;E6k_qhh!8auPIxY1DL=r6^=VKxLys>_K; zW3tiF>r!Wn=MILMx0d7_jfhPNEemBB%xw(U(y9?qNt1fii6eKLXqrK4k6iJ8FJZI1-0O`wN zX+7JxQBrxvvI{&r{k5fCphwM*@u;t#krI%Rkr7o=(XuKe-CsBchFUgRyLd+gTeAH~ zau}gAmywp9jt&ohMu<%#MKBkA8m>+i(QeUy+UIGHncic`RYbzgPql3rYugIsvmqx7xoz@ooqg-9lFZflf-2kutEmisrmu|nfZQ|hu zM{T|ULSx_U%Vk8n5Z@M^w_HUWD|GA~5CH(R9RS}@7KLO`F!ISIFfGCMn&>yQycNkR zgWZfiC;m)qxb4H=4y9>;P}~yGs8*o6{3px&6Nvs3&Ajcb+!p)5|INxSVslR;}$75$F=8j0()|J;e>3-tp;~U_}@H#8;xVvPfnF!nd^1R#Bjx)$KUGN>J zCXY#)uPpuFe_;Pz#hUsN!xI2y{Y`<+6=@?m+mn?}{;2!np8@-2I@F}q|6uib@D--! zm2N2b+utwbvHc`v_`cj!%iOn9C{~y8Iovz=>#FZPH~({U2e8{RT!nuQo-xcvd7>_6 z@#)Pcwb_opzgougFK`!*u_h->chdlNl(!S5hL4BYK(eEwvoqL8_$GbKqu49%^R|g4R|@K!`C+M%xiMM1=yY;EcZnZo zn2*t!u)A=`o_yJgB97au6w90*718x*s^?~!lJ;vy6XwWl&8>4&e7gE4hQ4o;junhm zhng2+LT0>-+$-E;&s{~1LNO+7PYty&c~zj_dMXtQJsJ)bhc34{EmYTKUw<0(QCsg_ z-U>t|H~j|V>75XLz26ylsEurR2hz{nLs0}Zo=-uVgI1ST^ZotNu^%=!yC}b3=HR5I zyf{CCEWPi@a%a6h`E>*VX*Zg?36mxy*39dPI*D5CMepw??sEp0_38>PxE!$EB+*|j z9HRdL;DOt`p8NhH+X3;JGB<(oY6zL6;~aeMv1#dC1(&mAm3Op6T>@M^bBT8;qo>@V zs3*gEv{m217R~Kk)cobv6XZP!s7etX>VV2Kyum92(m{va1pEJiDjmu(h`ruGGWBrt zZ9pnBP`#;g9fbobm@?$Uc#gdCCsZu_PY9mbOS`tfs>uF+iDbY1+ghi&|2^yJ2T^;e zP#pmJH*Wg>ME|z$jO;CW{?J1(JBYR=Pl}TG_tn}4V$!Hr^7$)GBwk5`w zVUsivTBlv`nV&DMT!Jwf-cj9^QxNv6vPk_Ag)bSnGycm7Mplc=!mfQ99Uc~DGyC(4 zn-iP>O)*-A_f1$t=nr?Czzo}nd~+Ee?2%>^V{om@oD*76=5~a4@1P0^G`|QG6|j6-mHFtg1fc2epTI-NLAsMR54Aneom-^&n5it2IdyxlMP_j z35rO9-KXaee84;dkd2gZM13tX5?giX%Z)~mUXjyalh9=An?>CDpYK1cU+@VyZ}ytd z?p?$>V$}It-%Vu_JWYTfj^LgCo_N? z5*OgZffBAL35oCXr}Xi&%a2hhpKo${TeN#a?r;q>452wWSVP>qkHDxZZLlU zV#m|xR_E69&%gLem%*laONHK8U=XEqk13y^>J2`I|4fRsl9`Rh9wtyVDu^Bjlb5E0 z$Bbk%L#|7UT6#9%L3MmYa++HXXeA8akC>p&92YM9x}aYb-nigW^S3Fyul)T|PA1=D z7}n_>;p!-h(I`yK2^?5{aFX$&qB_2PR)Kd5_)HHoVC!6HubC^a@8-jb3@!s1Q&=;) zn7_E@XS^~#+E?T=dY!!-ENi8RQb|L&;=~(TSTdrx4N8GSk6IWTz$_DQG6r}2X2=EmPJ0=)@5UW#!RhoIcj3*)P^Eb@ zD0!Bv9o$PnUqshV$Z8Le`v56A5irR`dWwk2&Z%y%rlCd%We+668lfOY713VHp@N%|c38@)Z)^eJZIBKwD`I;&jdud3QXC}2J5=#jE&1LxmNu1_t=Obvk!I(#?! z>C>7Isr=%EBdmI!FLRFM6zKdIb7hz^nv~c_p>&eiTx@YVp*%_DydRr=nr!drpF6Dk zuk15+6`Z54(Sb`pFKH?@KoWmCBC@mDPNaD&+X31JN7*oEP7sD>{irOCaZvs&a=RM* zyd$Lr9r|A2njce?S_wp3`M=lFAz@UjP-(N*oT$ZXwo}DiE4xg}-IJ?I%+bq!2O@NC zYJLIx&>ZAR8~-=0461+|B3lrgA0&TA39mLNa|HA85)TX5-%iHo-P395s<8p#oHyoK zlI8pqTGzdoJes;>Bsl^q8@+*nODduoy8{^wkcXia?PoQ}M!x6K*`8-nn6hYH3s{QI zMFL%_kNST%q8_ZYhI-(f(h(H@R=}us-6~*=^l0PHg)PVjlL+rGXJ45e$tlUE5^*CX zMM-LG-)d0Cn6^l#5sJ+-)w~)`tUf-1r|HDj;>~y;N-~;|h+16$Q%mY3-ehL|FsCLy zoslIV(EL~_{m9HlQOE)R%yYK>^HU;od%&2B`vw+9Hoegf+y$Yq7*d4>T=3F&$$#)-M{Yp>`R?c7|5(goB=o14W##Q|(|>Otr7l0QiS) zF%&z`e)sjJNF|%DbI70v<1uYe9nmQji%@-F)efLv6{XY;eUH?QDC4KZy!xQ5wdyA% za4ipv6wu`FMi+>%#!_y%vVV|D2Al#!!Itl1PTb$V>wh{aufxcgEm-yK|*Hsq)PY=)kE{!yY3C? zA5~bip@zr}kM-xiC#;19yB_xpm|rED823sZ;O$O+8Z?G9Hm+pfZwV&uJCTkNED|LHVaTo0o4}t+;Mqf!Df$M#!&ni z@&s&Wt9*Xxt@D@-Q_@g+jtT3v^7x6~aJY4(aM!JtOUc&9AWi;7)Z)SWIX;W#n&9@@*vwEb+Is=$(%aNqGXmke)vTxxl~K{;33{I-$fD z^4JnNSD0t}(fBG^UNNJ?;A4TWCc zkRSb>aM&LW+?~G5fE$qGHX?HtKB+YfM#uYZieH)dpxC0XqAOj?nXyl{qRr*yb>Obh zF+TrENi`v6zU#u?xrt3oDeP3ePxI;_aAvsuQ+L(1Tgj9`4+qRi1$^jUUFhs)ph!Es z!e6#MeCzM#U$kRUV9{AmEl_S7u`{>@f1xbjXa$xk-h|gDs3MYT6wby8N2{{2+fYrqznZ}p3Ziw>e2t<>R0`H(wCJi>tGzsr_EmJ)h z8@~V0G2{R^a|XfIk7;O(LH65|PC!0g7@Z8kk{OypD3n-sSWMk$X|B{J9p&MbuKqw> z%DFUU_5ItL{iYz9cfh6G%~&Q5=S|NN2=R{Q#GITlgXq2TeS^V{_%HBl|GP%9IZ zlK~83@=$ec*S%lS$V_+l|EiSrh7~cFx-eFz%>e?DSLwG(&mgSC4Y-YTNrzm|*0pg<%}$l>9rzNc(1o6Oyt<8zSA89;6|hT3MJdQms3UH$EWb1y!g6duyNKz3p%jd(FYl@ zLd!WTU6Bi`FkX%ltr-KgW|u}u)=k1w6f?4%_JBjLvPkxVMfgkGfKo6sAXz<`x?f}o zbd`h8VUey-z`J%sH3~77$l81SsyA9${$5Qx5cYRjjhyXuoqy-Dwkd*K=uq|94B-lYB+eAm4!Z9ob^yXw+I_fy|6)5vi;zu~E$oIGAx_;#ohw zI%%R?WuLw^kvuP)U&joB5ffXI3hqkjZ2Bz~CXzAci(kF}Us=kMFgXd+ELekHGDBn4 z-2s!9DLE(DE-J0x0G^SNo^GI7Bcgeru@JoWKy@Z3ZQ#JWX$f5+-8n+dyYGCdN$Bd_ zb9Tg=1h6f_q$NSA?)@r_F|9i$^~cTgZAN~()yUn%i>PX z&dfk~`pj3Jz}^g@QxE>BrPy3^C;Z4bcs}E)Qnjha7?T=TF!S7r+*B}1nem`U%D0KF z8L^OqQ$Jtz%zEe)VI5Ts(tJ&Jy}V+$*ndi!oZ|O;`Xs21xTEQ>fHO0_e=vhlVqRNQ z$NPZz1wmiVB?n{&8}5wy)z&6%h}dNm z`Ufs6v1@22&2*U*Byu-*H~v_4-?9p+3rjV#-sY60a!Ymb0A?)%R~a#~cNfAl7o1$O z;6t3q{jS~Uf3$10?7mDzUyJU4g}l`*_@@1%ZXriGNgS|Kx-wTi7gb?Ge2_z~-IKpM z@tnOjYjtuRG%;cG%(9CfVcLMyHKlI?Ry`Z(r}Rf-2c{rOJF!O>Zl89|ob*xOsXFx- zy3_B?F!mIeyJ@MaDjER7nsq?MsN|+Cs%T#{pE3ypBoEroAdxafD8+}KF<0A2QX2kB zCh?YuOB?DV(9i_s&h63T?i)S{Zt3FA%2YF}0h$oIPlmG8e*}gpP| z#bdXAu~T1fyEf4G+yjt!$Jm8b_EZi*laX}=K?%`DwGR15cf}wih*)!DOCYhj*x{#N zmXJ`>k@ld}TD`}{_k0I+ zEzz)U1-2nb&h_a9-O5GmvJaxN=bHuYg7zCHnKOd@J(|IiNheop>%^WR)1Jfwbr-~D z?YFJkd<-MV1yIkBV0FvxI~&VD&NYtR4YoF>O0M3CcXS%ae`69hxWAbM4d74z zi%FmgXkobgszuJ#&!hVeTEtNMnP&Nzff}LCQr3b3lz@rX>o6r$7F7YOFsk6&D37el zG%n}M^En!IVCHTKBNH$0Al2B|*agmX;rs?#Hc4N2H80IK@2)OO!Ni4N7f@YA`11tG zFy~#nm)meZ%Fs%4TRBDD^)9+jh?Ku^Z3KPxj3Id)n%Qk$$Q{$V)L`w(ft;sf1nDqh zAUmeGWc|MKs|(?Sg({h)lxybS30BhTr8GF2*v3 zVwpdyq&8|wwDuEf4AVks;%zJIYJGlqIbANnn|z)qb3T}bR$a52k_<109cWNEffYeZ ztO##!60ZzcS8RSUz1RO??=6Gk+O{=N2q7eBupj{%cXuZQ_u%gC7Tf}X;56O|8l=$x z!QG{CCpZKT?rv|f_c>?Zs(W9(TlN0lE`BUl_nI>1&~J@7X8y7IG?{_QK(Dr=M!%lI zQ2*D^Bo|d%6$uuI1T;2fX>SJ#Hwy$#f%%_#q>ca77on}3$Ck#N03ZmBw+va?QxZUP zK@3-E$Z7*)=(-|p{Bn-;;Fm845}`>$jCviIWC(%IC)y zLk9p#n_rvYP*e4q;X`WC_-&3NPCvZ38$#Fg6vhB_XNQLb$m@FmlAUN-s$G00Xk~%Z zcpM|o$1{Lhh()Zb$PYCkG>3GoYt+@~-#PQ8L+MleX^(w_o7JfDLlOfgQ}_3gSt_e# zp$>1H&tumPiHZ_a!7f#kjKw7Ekq`-M4daPg{X_jtPA4W~}j^s6m?IG0GJpJh^9H30n;maqD3ZN&+Ga$F~@(3+j zGn-I9X^Q>^J6*$@8xilVA^M@QTl zt1H{xFPevjwEKNC2haLn7xKKxJWuwC;|3C+*ern(jZaG+_TLbiH~jx?yU|Ct^#36l zfF_8hr@A2AD5o#+e<<+vUl1DA%THyc54^5Lil==-07wf2-D)yYH!Qgf1~o1fJ>uTh z-z`Q0f1I7230Yf#KMCO0)A>Y&qMPks?>Y9v`(2J36pfnVW$|0We6oyP6%rn^dWzfq z)WUqJiZaF}vsz~FUpafyx}8TiN$zL73z6TJK0HPsK%zwl3E!=OMUs<})RVTdc9bIJ zPzyp^4f+?GoG#{92Dtb5e3}P_p$fOpYu3N#7w1u4Cj?wyw?2Tw%#Rym9wx0^1`J1j zsQui95FT!(+bMh+-#UDY{3kmvUn9ZoJoJb7lx!oIiDqXq@g|i_rZkJ19XN*SyPVR&}Q_}8LqZPRE@7Bz@ zF8PecaJ2EKF+`l0SCHyz79=1k~Ev9bY- zujhh=KU2GzRHGXjLrg0X9tHY`4I)YwyXo{dc1ejq+!8pQQd(y!KEh-eLvmvq(D!*C zBa%mjvh7u`=knxUtZ)Pje|wOw`!*2t5k-^4i%$P80)npkb8;OzW1%Ee>pIEq4N}?Y zskF+nUbzkMe%=W+(0lBP!D!DNOa0mfVPN9V4GmhvVhcZno&meelh{|?3MWy3u#E*V z zadIm?{k5&Xf(=S9D{1!!nQ2s?+()Qurq?H@!7}rx9!T5_`Qw27PDE!I$1So+1ea4H z*?)Eq=-3?{=j6=UXDi;H9BO#z_fYIYRg&Mvt6tP`V%5tL?RRO$5|$(-bcu%*G)|^s z8*KOof5K0&_=`Ip9{1Bx)KoPaV4~^PwkTx52}oJC(HzsoA&r}*yPpSm-Ei`3f6>Yd z;O^PmPR6`XAIPZ=+Q*gEEl@Qr`2bSZ&CxL0gA;zo;BE~MZL|7GKS@8X;fuqFA(2g6 zM#s~~XSvnHw?!#<|G-dOOf7J`*F1uLz2Rd&`nh2H%U4`FnQ(WBN48i9|B;PiD>{&o zU`6kQoWDqkk6%N%w6u4Ab!GnLh(I)>6l2_ZHn>|k>ma2rKY&)aSJM=g8HJyQSh+mYD~VLle@Ht-VK~pqD!GjzjU@sUh8KyzVs_`Vj2ws zTFXH?k8m1)W-7n?tEo?NqHR#p*G_a{fn5Xf6B85iNx4#~1}$)PICUR6oeEoDJ zCx?^c$D_!FyC@m>>s^09?>Jj673}YXKIo8Berm#ZqI+3~^L#Y{NQ@YzHDk4K(SZFr zD#y4&hi4{M&?}m@zN4*|rms%c|1>$TS+eDFeM%_T_gY0mB?%6Kl_-buiWK{Mm6HL^ zQ!CkWX6{&4le2y4ecC1GhW708Ux=US@!Qk^$Vu6mY9$?($0|ep-5LK&J^J^Tx3*N&1N0)U zKhNSk*F%05_>T1V_!tb@>&X0Jkp$zg>&~k~%HFE)8&ru%r|2Bg0UcI%i+G89G{w8) z0`D9M5De(yxgI}qec}&+8~nU;OS!GXvMpYTNoyM_bkEfY0V=_hXQEl}-LebFPc!aF z4`2P$&j8fMIKLjOGw%qm0%A7nKF#vnNgsbNBjHN7zV`V)ZQIo2B#~?+$nN(}Y<*na z?W@eL69mekX2c`hKsSwrMMXxj!wX6{Xc)ZgBsv zH>vdOXw2?h{ljF{EW_(x$8UBaZ%Y#ix1#e>V-SIS-dup4m=XV)(C86n5k|ng`2|IN z)$NCh746T)GS6W$#~BYfM3(d>40UbQn8+cDBK7m92FBWOO8lZ?4QO5&R=w z_{1lXg^VYW9A315rKEmsn6)^w_fbWc%P?pvP?GL<8os}vqPR;p#t z0LR~!C>CHhKeR#r=E0ZG30L&yY8(ht<-{(u3FPU&$c0{^dMoK)eQ8=)=(vk!n~;L- zD^_q`!b6_@d%9OY3)a@6X3DHT)SbQC6QD-hd7h z$}Ze>Sfa3?=LxCilSU z5ChndKiLzxv1>;PnvXvoFHII0Y3mW584pdJhP)+5*cUr7aCV}tQ`?KmqdKh7>W}MZ zOm3!gon2HI5!5pbC`>7J1!|Z+_+&k(Xbe);3v{i;)zi_~6xlK+t4>WBLhRCZGVDbj zTN27k1ZFplsuPj%FPw`6)51*=S^avid)oLoI*wQy2jsb+CmTEB)b9=xkKWLX#TM!@|tu-BNQz$>dy=G+C!Vox>UO#FjnS^ zk7y3{`?{Np!GnF2Lrz1RhzWF*v7&@Dtp@K`kojdEj3UzH-6|aQ-hy>U-dLva^ss(2 zR{X`+VWj)D?O!(J!?kLK7**JJ?v?M^le&a@j$$Y3U9RQW2h8z? zI_v+#s`O+p1o{}aVk){{<-LE`agj~^I-PTki7v#0pO7#`w}4#Lt^gt?bm^|%OxpW) zEuV#b)BjjO%+<%I5%&;07--^3XPWls+Scnhh9*c}yzc!xH9sf0_<99ojz(R(&c2?^ zM)JD>=PjD0Phk~7IH--nHNCts%H&+d<7H`E+hYbMJ}(=u)_S3QlNujYNx0w}clyZC zz<+B%tAgOR?VMRtFQRmL=4Sn4c#H-2t$DwS)@4|NLMPdTPS{GWv^FTiW0{#!nBq+Y|J253XnNLcP4*xx4;gGLGAu56<-lUmbPWH$G_v)56yP~_8kc5Gl+zrCow zO~g((0a2K)R7NVN(gic!KgX1_?7a5Nt1eEk7lJm`U(;qbC&DY<>CM%GNsRjXpd>Ly z)4rAuI9!N(Yp*C`;#>Flo>bnh_3h_z47|}!NB1V3VxHORF|&?i}9wAzWD5J+VjX~cmv;lFl1K8>O z4x@!PhWIZm@&poFJ^`@x9`?!rYL-iVqVlAbKPEvT?PocfGCHXi3t2HsBg*Q~@OI<9 znQ1!e$i_OHjZ_GYqD#759D&~VqWC6)=<7?$!0#xsrK*>4o=fi(3I&315T1`%xdJ65 ziaPpmu?+(L5g6%vk}Q2o)7jk>rKmBa?yqvQQzzT%l8tiFW84OQ><$9n@g~j^Zzfxo zh6e<&(KycGxskp3`Mos92p9%}XueeUet>`5m!?}w`Y}kV?F`X6DbcjZ%!#hz)%=-h zUr)XFNT`@;#LF$=oY2=&MT+y`P4)w5D;&?xwT!g%dW_k9^4BN~I={0*B=Jv?kzHL~ zPhCa{;CXCgEH-8{=xGOUkN5(Vrt1^)k(+}FqES#eUPs(?B3CBSYWf(-c;Y3j$;=4+1f21 zNVagzaqv4j&IwJMP7U|;bA)GOKG)ur(V6#mXHhC_e(^XkyvQrj))l0)h%(Bhmn7e8 zK6ffGrbukc@;Db35Dc+6ypHLqTKoW`N_(Y{mYs1)X&w5vE(H9Y(a$-@an^}xc=6;F zsx(eIJB*>oEH&dt)$WgSi~||@%xT`Tg_X{o(DxKfo{oEz9S*ZynP4T<_!yOD;Fygc z?EV{0jRMQXio7H0JZ-?a66(m-n%5=HBE;zP=#ImsIqLk?bfj#x70`4v7vlU1)%*)3 zfyK~xv=Ks7Ir1RB(5@U%L3`C)80}{=VAq^dqqq|tJB#aPp-eg^zgnb{Ss;sAXP~b6 zS$yuQN7&l*M8<=~di-d_t6(4lgt5 z=a6YA5W|g^7UriqO$Xd$R4mus>-|Ded%pgoC#5%*`oCd>p(5fDxJ%T3Y5ATmZcp{T zqsAPFM*h}lfKL0%K@F6XdJfsScO#6}$Z-?=C?r;j|b;9#*_cjf(4XI z23)*nkQf~1sVjQW=>-{yfxix3!+0Eq*SLz*>Y4-lluaVCq2*&u=zD0FXI`-e1CFeX zDNBef6#f?i(9xH4aSNJ2z=>{yQUuEtR(pzdXvUy<_a~Ar3=xc>! z_x#KN-V6@VF%UmI{k{#Tfz;!fl~@PtA~OY%sy?|@e-8)UmU#+Ymsy>zz^G8IfD`|V z*MyZSl=?6OW8ce=DzE+SuF2{`9qzwAK@Qoe`ij;^gptpk#0&Wn>6HS3A2_SMIB{P&t%&WMGPjF7wkn8QypRuny{+$Bq^n7|n z=6cF9@#J~mG1}PP0>`M~<(y@kITywdYRh`e%#+T$>vHk;4g(>?zuMX+b)`F|v_@2S zQGx2j$~6<~6=~2TQgFv%=tqDI_oWWI*zC}Hq^(SDkDH}^ej3Pe9buUo0q1q;h=|CW z2NbZe#y`3APth9?c}mwO?o3-GDw6l97OT-VYehFV`|VrEqj5y{9>6R)shJYuSLLRJ ztJ-N<(S%~uHaMeAIK$3WZmw^NtPrTnBn|`9>kso^%mK@KY%Bln9cgCJ8G@f%*^E+& z-{QXXrBBPiZmYxiOdlKce42$vkB)2Dbz1sG_DEbdlGj1!#v6Ir0z3QiLh^~wPT;*l@vS-L()TD)sR-)Z5H-VqEUQ1I>4aeH(ZzfmH)JW_TK&y7m7ELpU-@^ zFQ59W1#3qng*(t^+O?{5e01sA*d?t|H1yl?w+8)k?@?hXc7D(^V5~MU_08pm%$=b> z=XA5tgPOZF&max`P=l(76HZTx?YMkJ9AaX&C46N;Vi^}<;Z2wV_-yn;Gif`2MOByU zHXP0!5e`vTe(lBsv5EWH)S^w@A(=}rCvR>^v z1F=M99$MD&qln+@V4*$@XYzM>Yg0l}WcR$ktC^K>KtDVEkSY~x3@^Ui7@u%O)n@z{4ZwIBjk=qkK-J-tXiqs<{3aM?) zyL>vD)>idu>q74%SvIBG-}%N!K8FmmV*eV?xU*VG7J1Yk=K4Ku41?ZbNbOS*=-D(r zuY3vDIi`r=e(rMo!cYP?y^LO;z z+}zZ?u08gzGS6aitiKdQb!v1F|I&CZg%1;~K0WS{iW(asxHP1hyF7R2CT3%H3X#kI zuW=`$#aWv3B@bGyviy5ZpS5p6=>vJYR2KxVQ$6lX+^V}xu1lLy4tEqgsZa`m!1NoQ zd~)N?m5x4bUsP4e{O~G}j}`tC*;Y>9pMU87DavMa(9-U_4DF|i|SIr zHKT*W;BY*Pz1UEel0v`tm!>#B)J0ieHYL16g=l1V^Ca3;fi0mb9^pIc*7nw#lX z2UTD+kg@H4__=aI{ekje`%ZD9PnC$ffj9B=1D*$%d=S^N*tW=SKt87A(8Ue6<)p@q zVHu0*)|JwGIy^m20X(R{r>v@PTAo%^`p{rz8W#Gtj+42u;((iqvhcKL8E<8 z{zG~BasN~?&nUh2{$o{fc{%iahLAvy@aE=AGcMjPP&Md#N_KUFw*IjK4aaD0ZSjdUh7ytIQ>4%0 zS8TTUe2%9@+2|NLlHS(A@Wff5Rv+ zPJ>j`J{I_64pk4e|GOq1EF7L-d(qLU-^s_EB6iNJ^mw! zKM9;UKK*c{Y*KM@j5wZ{hRPV*Cc)5g$U3ugSGT*fOR)70{uB`Obr-rI$$7^+mx;Ni z$dW&Yx#qXGpaeq$&l6#2d8d`eskV(tc43_&FU$}XqA1Ua3w&^J_85d2zEa{=q5uhGA$6<$>7Gt4e+~;7RM=4zvn_2DlwYDpO0(|nHznK3%lFSLcPYIjpFW*k zKrutIH=liLr)ijAEUa_S^x2ZKB>oS9j22bgTB5)0&GIP;34B1YHJRZd?ZBJ`r^EHa z^+18owBEWpn3j61;UB1?bSWoR-Qt$;a5h8E#pm){kncPepW06fDwQ5TJU?*mP}og= z&qJ~RG{7lZZi3}8*t;@=3>C^MBy*{ZwiEm2#(Ug-E{U=}b^19Yvs!FZZ8#T+q(R3&fTuXeD7ye~b_cerB z#0|8+&OmcqgCA~6L)z6B+F?X;Mn{6+pk9AMj_qy|TdWu4w-;2jc?^^Ci zLTPs)fiI$%wX(mm6gz4)SCp0-;{~R=uTH2F8I66H9nY=u{@rg=iBH-}J(3FDY z;}QyE#-eT4Xgoay*=Z^xZTZ)>%wv~r4OyH&eY=eC%Y9Yu4RuGI59$}-YOfbD3~rqf z4P`RBz28Q-_iHs=lAMTSd55p4uqxM3Q$zj*1#v(HKsv#W`HWHNu;IQP^#jraJ}Z zSW0q2&+psJsXSxufs_j0ZG;cDvS&n<{2{ffyz$FsO}f^_k{vnxRzibhIN8+=WhiXg z$`*Aj5sKqtO4BrQ$LOy@A`^O3Qr7b4KXqjsxf~{;3lutgu<_O1(gliN!~|MB!Bza7OGq7wca5)!a`vYC~V+I-t$^>MWzv z$aH<$)Xh0rS@j|G?Co1-Cu+#Cwf5O8Wk!;z_{v0)_vaU5UN%<>qL&4q$6UTT7e?vRcu6W2SJ*MDw|f7qd|a=( z4MHF($X)PL<6qFW1-195yEsCpxQlb%__yK^PP@Gf!cl zZ{am}d0n)e4AO4zs>(x3`5&LwvW2sQqL1hV(c3YrngDF;iEr7mfqYwhqBsP@rYwuU zA_zC6;#*6s0|j3Q%6ztydejpOQ3^g@E)> zz5)FSzdHW?+>%ZLtu#%fCLrKq>FzE~DaHUgD@Wy0r~qc}rEOklhi}jnxu?J}MFL*Z z1j?B^TYK1Ienv$TS9t-0P@g136z;I>!C*)fd#7%3a(r^gbq9=_SSJY=seM>g31
    XoD&~dOi}!pVXa=N%*7|Br7#6HHoj9Y-Jw6Nt9z-5Ky!ZhB90)U+liHzvet63M%+ns6wdtxenhY6o_WW2vea(6| zGvh*jiHv)qD=L;VX05DIf5Mz!P+hyWxiP!hP-%;Y+2id0rE4#ax}qkc^<*vDFZ~?z zGKsPj3n&;U8OcsEN}Z{l0N{>w@Fb(_kiU<^`%Gfu{K8#Oqq>^=5`%d|C=NHiQNcts6>fmw)&#Z2UK>b*@;08m(~1T0NY)Tm^4 zC53(;EK?54$Pi+l{-rN^jbeGmF3K%Lj*j^Xgg*G|^lU=;z9I8ed#bTOjc#?EF3~x= zL47T=uV}3Z8@GkkJ?l#!G(dRr2{wj@2*V+Vv2FPqeE9G+RaZ7ybI0Mj=VBx%C@7oa zx^RVGvu^U2b|Kr`Mf9E7g8LceM4mW(>D`OI1k2id=#1&iuRKO{$`))G;unIK68FX- zv$Bcrg?>^BA_rVthtb4tpEp$^4~2kN$sbigtj;$JylV&i-r;Vq{Kkh2FI?^=8V#aj zw6Ppj&-9wN+MMa8o-NFKd0A!~=h^eO8!JiC9MbcfLP4IvMr}1;Ks^N68edy-h+@T? zBmUHf@~RlkDX!b=0-zIS0qj}lDm!|DHXHE|c@SGMrN1PWhRg}?A`Ci-jmH0WzyKq_ zBubdJN3Y*G`MJ5XKjW;GZo(6GNeg?|+aQHir*`Lu=L60i3|mQY7Ss0|8uz0`t-Q3E zifO%fw3?X+knyB29Vsu<-K)HvF08Ev4{WLUEc#bGHbUr6T=v+C5w&+I_Fs&zyRKU+ zrQ^kvhDVPIRsU&5usl@h5LH$y+F1;^;J>BgzTY3(hn_d<0m)PlqCP$Qa~cdsxd6AZ z38fd0+hvD`t)JXoHrNf{AwIp!KBLc-W<7p$`4R=MPc%=Fnb|yI;x1@6OWRsO5aB0< zrt@c~UnTpISRs|(5{|VIya~!GnROo|NQXsbaczx-JT<7HicYa%t0aD7X1KiIco*C; zR}4()Aq$A!>-s1D^G;fiQtdCnoI9=SOFTRQ;L|)pmwd~_i*SKz)t(2+<{iB(cC1^R z0C3kx@4X)3>)*Jk46KSI%p0Y1T@wLhw})57Qn&b$mRBygTeXxfOaA5U^YsbmwLV zr<~~pl0>lT9-ow=b1|i3+Fg9bmUA>%KF3Tajx!^@pBeE;cg>$ayNY-zO<$@pZSY>E z1^Nxxpk4SRjO$VOn7y9vxsiG{6P;O)9^Y#|?;^>FEe2NaU95Y_51H&i-8rM@^`{mT z_Ul4WExVWaKXkVBE*0ljpsysWN!CoVXm08_2;AfO4LvUS{L%FtaDSi({H?OThnDY9 zwQQ-Bms9@HHuqW7Ur8F$d5(k_I=60D9W&yMW@(7q4LwLB-DMBnzGtVH?G%3YfDAH) z!}76P2VVkRISZrt(o8y) z#-aMUO928k%RNexlEbMyhXEaXad0~9pvQv)E6JsaG{gWu+x@vgd)?ZZGsTY6q7?&8 z(34$2b7fA76GC$lGUAO5M}z-X%@h6%@i@Ua@Lgw&&tey}Q~yCpVmMzx^$=7ODX6h~ zlUEPy-s^m9qWSA(wH~s`OP**0dXdC9{Cjz=BS-S|cGNwW3INmG{%-wc*1&Grd)DQn zl%&huYHO|olQpH^4Kd7c?9bn?2}a*Zn=xZpk>+Zh^C`_3%@0d6{lEZtw1AVUG48O^ zi{CBJ0ORj`ffwSdu3qmPrmuRd*6_;M;sYEeeQSLAePaO7SB%c*i<&FaTIHp1P}MG)CB+`W+p~|f@A-k z_<^j)uU0W6m!I&!eVfwj1^Vl?-d`CiND*>wHuBIjRx}#%BJ~>0Wq_7F9QskAK~fu{X9fM`qEqHv4Er%E!uy z%pz@WZE5w9l$(PandQCpN7oPLE@F=MPL2-d4j)N*ky*qX?HpZHos3O^_QcKItxe6P zT#UVtS>(+fEP*!I*f{t||N0=aNLt%{GS$(;EG&%tuW@?L?YENw z1yH(AEbh^D~|Ef6$U#tp7zz z{!52(a`F7F!btzWby#+l4q|ivOYWuDJEEq8=N?ISJCgT*SZe|uF%rQ-e78|WHYyFhD7}Bh4Mniq~#q!P5H8HwIo{62y5Cxm+ z2(IV(t96)st>(@<)<_m~P87o6%9qMXDwLs1>jcs|e}MNdK`?vsghbS3wyPESor*hZbQzdjmSRxk)55*eudvyW zU5{G$>3!OxkbAA7a&pv;a94H(3Aziy`^Mt3ylyiT;C?0lTmu`JAXJITuwihxpWkVx zN|(p+;p$i{0(K(4eC)qQLwohr<=$IBw=vMcf!;KM`1trz<#1L@tKky#$qX*r#BJs7 zdV*TX`Oi$>d+1!1F@=U$P|#sMw7RLU~KDIE)==|s}@vu$- z^s3IHQ}4@ng^%;v>2jEu4|KUd%h5K4YmgBHM#9F}TWsE%D%ONo&GYv0iYC}-=BGzK zHYVeM6Ynm9TfMM97JGpvnX4snSJ6wQB^3Mh&tx}zTxY2FYMCaZuJA9PD)NAnIDm#l zEcZ>V4PG1{HV%Fnb|vCKzNQv_K_@{?4g`NnPrOtShN2te#^e@ejosC|<|82*Q|< zjga+&IItE6^3v}Q$`@zlj-ebv^LgjIk(&dEK2ic}O5VLIjS%emH^ zzpOs&{HkLrQIHpyoxk*O-nUyOyHs!hSz6k6}Rlh%-T zTnMKVRwF-eUS1ykRY5OEjS55;kzF8}#X?2p#Ja&o)lJ2(LFSnlE4X>OH8M4l`NV$z z{1qwp{(h{s`ji!jrz92l^dxmB?2BHmWFX03RQ9C=^+^E_oWucFz}LM}z*R2r{L=-{ z4*B0-NBsS50e|g&nPKa&|Fw!E+2Q_t%89bRM&1Y(InJ9m@!)gl0#E(T58LgvMI4DZ zFtVG~v_U4zG{#5QVmgp(Mdi65LYpB9UL5$GYU@DgOnX|W(S40Czu-kFAS~u`$uT5+ z^hW)YpTm)ISqPVvOgPqQ&Z%5h7dd z^x)ei($~vsH^xpwliyENlu*GgY;dy$x+mIfY4))lf&tXMp<9poy}fRFe{$SazIJn6 zmOvBVD^*muvl*TGQxlM|;GvgE?~{D>2nlAFyQ@WsrFRw^d1Iw8KoL{H`}6jUjPOIz zyF8>M#lRY63j1|zL~ZOoJ}@-NeOfz#%6*@|USD?`8&i=5C~o)6R}X}3yU-8UKG<6a zu5|4`-&IMGKzZ{;5rYgwS0pQJAvpX&XEKdw=FUcj$Pa@%uFE@w!h*pyKHJh6iUIn0cX#c2M&rD{ zwY6nxYheMr?}g`208fBSMa@+7^zME?+}GBNWHyVkm*b6_HTT|J?7t-+oA*84M7x&e z@)BN>t`8g#56;de@1i+a27Ah>?~;9f@wVCyx6y%^nFywsetWUQ1!$2}LP8K3QTKOv z1Z8eh1O&&jxRDGYF|)a5&Mvr1%aJsKT_K%!t{R@a4HH-(U?+)lpB$arT?o3cL9>gw z`_*7ix779G`R}$iXj~j`L`45#Lr&%Mi*{C7YEC=JKjk@6eXth;QkM@1;_Ed`x?``R zz6v32fet9Yzrn(30{G&`h0~6WiBVYdYiozR_qKugv%|m8nb7oMfC6>h5)W%;HmDmN z8gpLG5b9-RH0w$GRtYdg->EXm^Q-5e6%i8xO?dCD0SNQw(-3qsz<|6QF-D68)4uf| z8w0f6%SxjxmG-#Ag3uD(wVJCag5A;bgtJlNtFU4cDM}ja{i`|-vi9M*Jm+KON#VWq zRfzy5ou5t%f7re->16QvHB>Yn)H}M^GnKqk*}GkXfj`lyIVzT} z5Y)1V%~!q3J#_*F8>}{ky=<5Ikxd_pah|p#LeTiTf%mH?96Y3_ShMUy_mY9ZxPeVI zzs0@|<-^Ga3jc`H`@X0794~yU9C=`Xe|dzdnJkUn?2X0@AB!j?iCM|a-;j0eti6r} z8`jUY)DV>+nob(fq}(ad$BuqD%|m;;Vlj-0vU{*jd1YnqK;~X3CfpItSJ$ z7Y1M0POQcBk#F=BUR=sr7OMb+MPE{*;AK~uu-lHrCQ2N>wmxsbgVK?5Lt{)pufJl~b~!Qb#QTS&mYWSRDMQ#R=<2kuuf-JBaIudh`H5Gb z|6}l4&hMN=71XlH6fhv@%+0rLHQ%MO*tz-K&;G!`AV7Ct9BeZ>Jem;nEp2Yn_lT{8 zojdL90A}w^-%J~vS4S2?NmuJt%-c}C-5jkTgn8}nOo_Bhp(G*Gz%RaH{QMiv z!`x#rWT`a(JYi*N&V;Na%q=AB5IrAsG1|98QfxJdS!pqF?YVwr-1&xSxycJyEg%6P z!fEr&T0yv@MvB=0RlLK5M_w4Y-EYDd2C{m0J!QjX*NAWbL!Nx&@W?r$Rm7L!D*q)Z zyF0wQ=({*x|6T5OsiET!Mu>{pf|hVEy$)up-_os|X0HbXfoZ)?>djh@u|L#zKz{6% zHojiaYQqc*juaK9`{VAv}D^fFfTZgWQe#Ifx4;w!#6pLg8j%!KYy%h=4|X%Z?)-tXy=(F|zfN zI%xWcE3JXo_u)<(c9rAlwCn4_{=4@WMm-4Y4}LM*S-6`Jg$mf>f|QfvnXw!T$sW4t zG6YU+KbYxmdlv%WORVH9wzw6W`uMaUQCqAw)&TR8EGhXcP8#)SQCfzMg(b8$%3lk;rfq+eAK4?B}FJk&Jlv1KGYbt2Vr4SFF}MAuT!wz z97AH0w2T_b0UyL>kDiGMahp;F4tuA99T9}v*wzei&}aO9!Pu{~$0p;!;j7^{nbuX& zp}>aazO74yDE`^`&ZJvx-#fAKepmr6!+O>E<*8|-4Wq9f9&rgi0S#b6uM6txc#Ur_ z07v6sxwcHcM_48lgE-!<@$6X+x^RC|N{Wr05gg?8Fr@yQEbO!#*?zWZwp`V6%V80! zsaVt}b)h;!83&>H|TmI|o>pwL@J~wI&3^6f!-rfz9 zR0%Y1sxK%hOx-5wGuceLcXFh_>nyjiU^Q$FMa7uqt5+BHa~&UZ3VB8nKExUVMn$<} z`FG$!O4+*(Y$AS7)|!}el9Cy<^lQz)&w#7cX%jwORa`hYIOykd(d$u24MIUdZV=$7 zA{H5Qy3#t{MI>_m(p@R3rZ2N#9GlUYe0uD!qoey)7voaY{TFw>QaToPfBhxM$kN>J zU{ITrRqyssy>_Z@u3l@Yv@gqfMsx@jmMPxRvGdIuy8V3p*}-Q{yx~k5P$BgQVt1_{ z;A1VIj(q-VphB|BZ9gu5@%zD#gTj=p#8%;2OS4EA)EyXgL4}pkVx#$!^S*CnuA{DqBud zw_F?$F#POW9&ro;JNB$a0c#c%zfLh#g@{aBH(I87XyHlH1re|zwqqx0GY&rcV4 zQor~TiN`z+)Umofo7%eEC3p_PjMAymY5K#$2MX|KxE>{2kxn5b4E*vetkz+v>O@?||Dkq{D zbVes8_D6UecOY)pQ?x8Avpi6Q)o`*`6ck7g!}=1ahmbKsJL|mGdf-b-P2Rgy>oha- z6SnwzT3JbdV66dMKp^-~h{I>YtlTOXm{h%|StAUr+!kff9tiByv9WdxxBS}1j;uikGr*_i=hoASG1iKq9v(kUi4n$Y8SYj}XhU(g72 zD1>FP#N<}r)&+s#l07jtJPyia%>`UO|Js4`|4#+a4RxTx+rT67hHs0$~PK zrt+%kugD+5!^8V_`yT`f3k$R3W^{D;+;{FMDb|4S@80{orm~`ko?khl%gb@uWNL2V z**YS~)y3ua`_-K`jjHD-aW;fEfK%zy$Zb{Z<8c@VgFqlYK3;w4FxWOYb&D?O_;4zR zW)H4m2w1HjW9Fs5bFQk+0BO6}pQU)g5SR}*S!5@^E+?0U@d1kn_pTp%yHU%(zva$C zz__JQP&ggwjvR+9Gpw2Rtf88I&J4qACjHKOt#|T>E7Jo5iYgm$G%&=%6Ztm%VvQJU&rm(lHgk`uI&8Q=jx2_y?)mh^?j{I{~a_It`dTMEEg|L}3R8 zGAx62Ah_h|DlHq!Ng9&nTFv;@hmS2;G@ z17utj9^Pbbe&{Wa34>rzf{aKj4b_Gr0Z1wupX}VVYs+>c{J1WlKQ$LKZHp+83Y<`PyLn6E~7Iccn2ADpBuM z+=gL_7Z)bi20KD~k**FFW{jJCV|NWwKs*b09!pJLrhsnM>7xmrW_!?5ZoYQ4(P?^1 zM~5t|p}{Q!gdM#Nc`5O6`8%;-(n$QA>&rPVUR$RL${k?bIk|P>44`sIcp#a3tNXdl z;t4<*Z0uZytAc8~zaQYsfhQM>mc!gT?U_6`mqHQ#iASlc((KNH-B_KqU6N1N<=TF54se`PI`f#iDT z=$h6baBpRDs;liaohXlMWhTpAo?hz`5P+1(ncG!R2ph1eGF(doE1-XTjFFUEdUYkG zgm*pDcKv5X_+@(LikMLTjgllPoCoVMT*uO)k3q9HE~|M_Ed*kcr*RTT4k}#UGF4O@ zp5?G4WCT509rwZ{+ojmBfB(y0&T5Th=zTff9VFSPuPaXBaHv3>D&bm6OU)?Ke zVK$bx=uRXX9M$n)oTmw_n@()zpl5|hV+&iQ7bf}U_5y^V1f`OJHi|a??(t;u>1UOz zroh^$tWzkZI|u__RLFD0T{2Vx&bnW|s6e2f`QF|2BPD1T0`B~RI;EtK0osxI>(~0` z5eCf`$JwoCZ))skbtYWiym_-z8T@km(sdU7ybOrT|5TO&Vr!|d3bai;(C02)UP@P^ z9^q>ykgGL~GfyueToH@2n_{91?Ui~HZ=$aX+`I05ukyn-!bFz}q%9rcrl4$BEaT?HzZ&eWku4|w`(fw|Ivv1qn;(EdPAvcx;46K$N&(9PfO-3es|}p&CxG$*q7y-me>K8` z`{oTbu?QQ3;6h=f7>$n)qtW?dqsPbN|I*~F6BDg~V+NPum``u6qS(w^dcaur{>t0Dqz#}to&mnI$mi%8G zYMk&~0`4M|tb2TX+?#O(cW@A@yQ zAks)l2@D}2f{JtvsKB7o0wP_~5+a~5gdmL!A<`ltohqfYbSNMt2A!e|>43z!2fk~q z-`Zzi*E!eTf9a(#^UnJ|&;5MvPuv6darDlepPX;Sg*Vd|+AD8d-@&bBiDr*x7<&t{ zs>=3V3ZZX8B_Mq^xA3%MC(vUBp2#Ka;*wrr7O-VYU#px4qAj?+dV=v>8JU&-kN0?6eEG*_~^T{L0WihD*8%bXS+3z=nGh-Ep08?-yO7_&n-<% zC&bbM-BVXr>#qXv(TF@04NYnC+m&ipbCIh`qt(9GruO%S=NO>2tB6S>uLAkLFp!Z| zHKH;pPlmjz-$+D-Y>siXw2VVWK-Ej-VeD5vCPbJ?aw4HWwtAS`M!&fZi zi1E2OV3UXs z^Hq1(=PXf}lSC(?kKR)2yq?OR>rn`q;H^_wQl!ayuL?NKP8d1Ct9>0C1t#8XG;{WO zwd7jNy?A?ibn1c(J3An{ahJV)x7ExE?g3f9eO6(3{-@E3U9g?aQP}?P#Rotk;}0Zw z=9$~%)XdUyRxeY|Fx-FrW>WokD25MV=awvvusNZDknoCpKz!2XWp%YaR*U_$i4`dl ziN+o~7f47bCnviUfibN|UqMNjw^Ip=QrIvgc<6UT4rvu$X1C!u$zZlUaJTt`8ZsgB zL#cXYuKJ5_Nzsk4o#l`w^$%*&iqq06dg=ZADh!_fR5BXzpDu_$@A^sw-Sg=a>MRbo zQsFR4#A$2Ln5&WA=Y~Wt^mWa48+-k^@>=bTIMtcU&+z4595Jt?7|9}hRWM!3XAF+L z+s`Ma_kI2j{C*YY?{pT&Uwbn<(xfg2mi}gIJM=&rr^u3*r_sp1C9C%qU+&Lz9$xO%Mhi9h)DYDIDPdmNQsUQXrXnL=$jr>;yVkM@1E&-U*P+2sVdY?_W&RhEHojZOw z>=i6c=iH~XuW&Z*&DYk-N;dfWZgnR}3N4&5t-Igqyn8~yRJH-C2i&E7E&Kr%H^a?j zKKNP}$OW_J3g?D9lao&YXs4DxZh{+DE;w)L&i`=F6kj_v6b3zutRPfgzeMBA6WQmqh)*3C^adj+&toW z;7JPlb!$;Hl7W$NT&2d`DW~gUD(C!k(E7YgWfh8|Bk|9c5ZUs|JTY>ruVwlKaH{3b zpSQ3X*Fc1!Vw06T%g=O<4Y+_NJejirI|45Sa3Oen4)*u<{{E3R`H~m2FNy$0Cb0Ve zN`hW-Z>do|*Xrs$r{4+^RX}M6K+pf1DNDTx<)VoThF$Q``w^TsT=jLvDR9#SAJ~qt zGdCxGQ@L)AfA!+#_*oezR{W#!cXRQ>Dqea4R=AH)}jk%*W1dF)k9n1JG@erwcLc za_@FeIuKvUgcTJwU?;% zqYo1V(XS2(7mdlhgP62N^#V`q`-FGTG?6sT>5o{GxF z{q#O}BFQHw;|CjkO@SY-`5_yFPk>lUkgI+x8>QN^EVXobQ|F*_f;&}h+;tk@M!k<= z?Tm>1CIT?Vq&yc7V7<{k9KTaZ_{B_t-=+3crQFOGEz~b8vg@m>aZP)Fo!$KAvZRVi zlTHKq(dGTO5}>nV!myUs80(EV3@p>QPcI5_zy z#@#nIW))<6zt)IWQs zie25@T8m|Or#>}4FsGT^d+htzMbrAwyS;y8vXR9T+^lV}Q?%RD_TjlBGmD(9xs&C( zFM!*+V!kyC9fFqc;k)r^BtJ>~Yi9>#7b-;;YUva&`{;Y`Q|}T$>utUP-`r9WH5i9+ zKM(wc=w({Ahl9GZz2r)RWi+KMSOTc?iujgb!%DuaE#a5s>TBBU7${<79)Tj z1h9&)Xg^c&7r+-6E2vux&*bF0n(uXPC}?%WoNhYMeTIg1&)7)jtEc}uKjNReS@Q!p zRX~J`kGFrwrP=-ab*_d_y1OSC>{Aq=vrUk_zkAM3u>jE zTi*DjrLV8=72hjIBHD!mU^`wdEoZxu zQNx`madCjOa2NoxaL?=duYWmg+PHttaNnbX8vYu(gK*3cw0SAl4&NO9hW}u~NP_|c zZ|_Hoe2FQ^hnHQq?%L=7*yKa-PfkgX-&c_XbD{%l^4>e5PM>*wf??k{s>7wri3dU- zxxqYR>VFpsk@+_CPOa9Bm0fLZYqy{o>-E1E58nxs3r$p9JaFF=X=<;F+IqN`PF^4RKEcvfcQ>TjU2IiR}$=ex=5r-8kia zclB=}*;Qp;ks^YVOks z-iQ4QB|G^JyIO#4m&!_@7KuoRomrXAN;k7KuW?@ak<8%RIqv8Ax@ts&)HPNs7Q7|) zT_|9RLBCpnZxk+t)=6yE^3EM*@kd@1%+tS$L;8A~`ZFwT@b7#c(eUiqLhcihfZRB| z2v64@^>e-fkXV5mQrcswsLD;OueaC(O+iM|r$O4_^HZ+qj(#)(Mh*Q ze;?Y%s2rvDig0UtpJK)v{6Ze{!2QgCm7F(Z-`f&e>Kh|UHzI_nV0f*}Gno7W?t3Td z26nYO;bPO{$FM6%rj;>|4)%SFXB#d^k9mHRTr2NirRhi%aT|v6zSaQ^7pP)Ak&%BT zWpbfNI=_238Q^+85KIg=gyDItZLQhgvsn5)EdO`58`P=Zt4sXmPsy$yK5QP`!%M3Q z2~=zVw$l<4=EthW$Nlz#)S%J;G!PIFpglKqcL@kK5Xs8J8SqY>axr=N29Abf*384# zyO`gD#{kHYE}I_xwQ|?h^6Kh`nJW*oZ)07p^%H^rH|zQ)MRSe#)bpwSW2%%-qfMe- zRI8;N%LgEn6-Y16{r2N_UPW|#d|6HqeDL-$JjA+iVH+Uid|X`l4xApq;;tP_m{h(& z#sbHKKJMXG53`%dQ1Iwx-X3hAPcM)@sr%K}zIwo8eOpmp2fZU`us$i33zmk5%)hU^ z5asHnf+KyvK+>-s5F{L4y=uL*e^yYH|FI0QoJE{rLzr6ME!MAO9RaS`_VnnJAQ0Js zC6A>eR)2hhY~!U?MhvUGN0Dji4`>UArQo?~JCHhP!R|sA5g}+W*3-Xcg9?B2bl|MC z2eLv=#h7f=D?-Od74XC4 zJ>0}&0y$fydybA?e;$a7U#h;peIspM3&nYwr$~ttn)`AFwCsZk4pz$Y(?(}x`;4)x zztd#atO79LM)>;1;m^}&XQYF>JKKXBQ5$Y8hIvHWM3WgASUTgsTW$-Zq%DdH@~m4T z=6^lRA9r_mmyb+d3n?Q*4Gi{?ETpp2KN*51D2f$HKz>OQMTKDaQ`*s<(}MCp$)NB} zCIDc6ne+p!+2G|hl&8v#unWVW;R`yBGhnt}N+1Pp=)b=Twa8Kk$5dg_8hz!UrqFM9 zw0xL1C-dgXpW({<1j~H5(2h#+%4VJ~w2UaceyLn)@)=|kU`703w?Jcej7#+$blmzu z-?8Zn#J0faWu?74W&tSaQ$e z&oO&@0fs&u&=4=A%A4xwY%G4}Ysocgs2AZpZVu*~4pS?x0YW)jaoe-NG4%I9-_V*a zaD#tJjQkv%*4@KpZGfebJOiDoe*MEq0_|qGmQqK7?d<*CdiDJ#-SOU2 z=qC>6oC=#I`pr)tu8r~{y+V1veZlc?-R(Npjn3J^@Rno(kJ-W*%jv1Cvl|Ju!IY&+ zvIaNJ&CMS@szLumBqLrb2R%dC3!Q~?V>keFX2d!A_tmqG<3B(j1c6xJ{u zSj`2rr=Bj&GeuYF+%B-}5+C#p`d{sRijya)*kta78kcexLcMlRdiOq#t{G?$hMp9g z3~eD;g$i_!*k!y#w~a0{9pP{7DGI~&Gy+xwzDHq zhA)$0e|qC3NB)z%b|4o4pnYeEh5N{3eDKGVqjU#dbS(zsHQX>#(ln^khH5QxMIg}+ zfhgEujfy%qCm_oE?3Sv=ZLRISp~n2rPhw7FJc$|1IG<3eg3(q%8@=Z>P*7|+#U{&C zIOXpAJ?Pt8bIWm)x_aNea4Wc_+uQfQMfP>QF5pFgn``7 zm;6MAyg~P8(!%xkaNP~01#{8JWA;?KL1(dTlGpwp&2C-seQZ$t(JO{$uKZwQkuK`N zP**%KBZ^MR@g;#6|7u+aH?5BBX+F_UGrtV0vQf1KGnQiHchYE~jAR)tBmhIt_{W0< z1fk|HR6mWTQd069)R6WcSwhyq1?is_zgZ(<;hc{7K*k{N$2a)kM?#dfJ508R8aHeoJBujQsF}|n^3UtN+KFep45*Nm zo1f!HM_w#ulo5U9W@Ep*+k`Oqg7~%Ph*KDbU%b-c=iT}7E;sQ*0s5*`>&63G$ua$}gXY_RrT@g@ zB=6%wp>yKZNFE$--2~>?Kl%678~c{PnB>Rt#T-+veq9t@ZTWXgOemu!Kk48}*t_k# z3xBt_n}P6AV9h1ZWr@lTz<4^1f9(9|>vDkXpz?bIv?MXYfn~yF^VfGn2?Pwfpb4{{9+4!>&BP`XyGRhsBA(0r*fIehmD@<(pl*f)?ALEb#aXuvLihyM5&aQ(0{6!K?E#))%e23k z%o3uxv-ovR%v&(D1jH3!v0=H^RExvUue*cc?|fnWUThi|WdY^0K?fv)yyryJ?u9%cr)-zzKdrU#bmR)`QCHo!MJIV_s`Lq zh>g56{O5vY&Y$t47irYlT8IIm`TnG%Kh0FblLK38D++2bIqNLS6Y%F{jV3Z>EB1i7 zpv-&uox8sJX!$kAA%n$td#LZcH*uJ}AXw8AqsW<&WAgpGWNIDJRmzgyp8;6i_*})f*A2kf89{ z?}@kfdRs4O_#X;VQu4{x$nCq@pZy#Onhu;IMP}xneN_~Tsm}X4I{Kh;g##%~A@QwD zsawMNhtBTKbLOr{%Rz(1hR*hhMukBGrOg+g@?S?U%)#!K#yv!C%U8Xx_&9V;>^ibb z4b<##nJtcUdagoQaly!9w5t7RbOsm>9-pR6ygc-^`=+p$?icKd?L3=vE?L{YAu}rx zcXTI>bo|1lTA$nxUtAQJ<_)y_2-o z*;Rl(Sj9G7yEM|glqua(*kaI*02n<%WV$n-4&^-(V_z{g+d#fJF$Lpg>G?I`bBT9Ez2ByT#hHVoM{YI+YPc{e74ab(g@ zw+;1{u5&JQ^6GV9WCY$D>i0*_5%*=-e@rL*P~zS8W-0G7GILr0A!7)RDHYAE?c;Ew zj(o^3+|5X4$=^XgE6iCZ+_mPcSaSuktn#@YiHp*zjBTSr{%r*@4WvLDeE=aL5K{c$ z-8wNT($${rTNhkQ*6l)z*M*f!Mc)8ikwpA7GT2Uh@xtj_m%@H8QH|gH!23_o@+K1^ zek#VVuI@A(fGYWzt_$&X} z2Fr`Qe>4*%?FLjjtL@n83i_(IHIU+N$fXho@F$fT!+AS=5i!!<5`G8QSHp%JT<`x7 z62Txyk;bmwfZk2JYy>v{4rWgu^RE;#0XMFnv8Z}8)Fw^$g)jXQc85O9*>h@Y|-bSmcsVOlF zIAq4RI@DX_B;LnkyUoUSd+_>ppy^8=ZX7w4pS?_}Ng@+EJG>CA?k;`Hu6xb+`HJusrNn^IkKt#aGL{^J4ykVHOBf~z8&3M z=0Rxr#I=f7JFfiq%K`ah)>_K^T(8(DEC{Fx4sMm)zs4`#O-+M++JpD(p_Lc9>>$)h zXDzJOelsIZJIz{i9z8gwSkV^Y+|pqx{PX+gJHoRZaDA~D9kFfx9*)S!1#9wY!u8Cf zm&zm}uX6mMiX4_fXsswIDM62~Y#iwHrul=?hv)|ET}Ly`|Gefw>hQjwsqp92!@Jsv zTJpqI1KIuC^U+c`=KOP^5p+@-dQcwG`ZXWIGfjlwTfYTnns=DulBZTo;bkyrMK|qQ ziyWzcU6DI3@7mC#g!w<)B$CZJka6fneUCN46H z*wE`RSnnTgRFLOU^ez-bxbn8DdiqIEVBS4gPy{AMU;`u`h@WgQw-BoW7*t}$h(J;U z_nu|Q9VD#ra?A5yXFum^fGv81nLb^uC<;8yOEuA0E(fnGa(??p={%|$8l|l~ez=J% zKEcoY4qh2^A@2AVG!1W76yDy>*s^xNA{Ku0g-2KdVYkMRxAAz5k2hAq^9Ac#Oi;Ey z#xcaP@V=bahDuM|^%#ucSv(DAWf=b~DG98w=QY#`YhNBkt}x)Bf^S#ns7aMD1VXU)^f~T1%5id*Ey9?zFJycS7bGA0%3@H zo?fv2?t&nH*_+DA&i(@;d_n~78F;soQ<8Zguz)AN@7;5h`$n9h9K|NL1g`xc5c&93 zR+W_Se3j}3+lquQ!L~{{`yJmUjX^PV95m#zQk%`~07M_xK#9j}vOi@4BWQxsg?yZt zUEnRo5RmFaC|E#?%f)48_SMUIpR9h@`~}FxVeW2?y|8z|KEaIKNcJX8zKk986X(#N zBibNyYD9J;I`zE{;G*)L2qDG2Nf3tA~ZO}=tV`l-&f;hjW% z;5dzMiN$aD@P}dki7c^qLzh2!hIe`NIPXdIv>dn$?2aezS&ky3de)(Ws-&NJb6HRc zK2oKh>m8v1z5yapp)`}%m6ZXPfR@#o#`l! zl}mjGR^3zGUoM)mR9)5=^*f$y0p0)-|1rRv{d&+Xu>xfQks*8Q!qM{(q=J0Q8H*7< zI6->)$LYq&1t1_UwSk`sVqqI^1-8gV`wGuVBQBGgv@FtXp>9li&q>-QVKYhYet}QWhW#~ z#DPOXvDoO`K9ARCGI&=HKckWsr5c7EDJpXL!nq5_zfbf%#^eMm|N1q?F=J(OdzXbj zMEA}c`-->Scn3XlnP3UvSNYU@h=JbmAb`jh&Y!2VoAIW6;P&;sH|B)V!+e@IHh)|_ z+J?cOX1`iNFs6#P3k{|-_zyu81*G4aeCB9kD%h95i*Tolw4Mr>_PCe7JV)ysz9RVDtd%F4kP`t)pU-9Q}~* z0Nv=remlTe!as*Q4}$)Axnn%PgG_2&u3-D&FaqDl6Ho+!`l6|MC_Lr-qZ-0Cw5D3< zloT1r0CoJFUWUBUx+yv`7DqxNu;sP4BX-Q*=I(c}!lgh4Qh;Ce@QH@oUj`bspnuwG z>9YHE*X!J`lSWER*dQX5J_&-4+Uxuts`UI%pC!-Brs7j=J8pPZ&n(2_7g)bWG+?(& z`7G(g$$kKJ<%Ak}-zPg@tQQ~@u&tt{b4@dM>sN{Z0t~f7hQjZpq{YpVFC;yTtCErHR8;&8 z=#jqE3$Y8H@3=@k2{d>(8@PY4EaJ7<)hA?)%N-xVkpcu5Y>j0ZC!^8GbZ4fpQwm@s zF-raxhQ9^qB2Ogn-d14xT<7B2uk%oAfi-!sH)4vlZ4q4#t%-@fEFu_*1~-bVop#Sy zg}$WMj7llHTvI!{y0P2%O!&(h==$uy*$KB=X$p=ha1huzSb75o31Vghx)G&=xGXGu ziGExOZ|5)YY)ZWNG*S^Kg;2Me0nfwGL7GvC6jqpzuU&g+%yW4Z+}~i!PSa4oARu7x zJYo&i3lJ6r*?{$mvI_hA2dL_3OaKN9H;sydXVY&w**JvUh4S3nt3v|rgNpR|W7!15W2DZLjK5lFrW<_c%F!hxt{#3(+lX-^W6b#`L()ipf5 zWZjDD^#8!|A^%IA+iln@K{tp9eJ`KO2a?`lM3EfHbpXum?>*wi+W~3LAJLJDm7E2Y7^ExLR5?g7S_ZCj&!R zRY~lZZO}(Luv))I+MTb#9EZO=KT0 z{yBp;D(yW17E-+xcvJXZm$FnS0h1p>Ak*o)zq>6T^(aYNPOc8_hKMTwW_N%(MNtN` zBGyIvJ{t=$Z*}7^Kmff^y@CI%TnN86yO)af!Qtt}%@c$!s)#hGT!aQ~ci0&%rGMdhXNkt#m)$l$R-5EE6D+>VDrc?#U$l z@QI#l-d;D@mJ|`B2qS)16XvXe4^GE`IlRHzKL{}=oNc;-oU#0c<5$l*7MF^d7{f=p zC66NAhrSc0)}>FM_=!&d2w*hyY-wNl`u=vz!yf*XAuTO^O7f(~YWu#vbZE2)yN#gX z>%rLuF(PC@S@LN};!q2FgPIKG6eqKv<)Q)G?WM*+|HrNy=kw24Qe%WT_49PViEtlj zaYywm)p#E$E28v=Bo^%lUHbK5-@jYMwY5euOoedDwAn*h%;Nx%#47C(AQQ%+R{L_u zPq9p=;s;Ar&{0_wLwIj4oSUoH`(`@Cy42+p7r`VA`%VrN8@g~L z`ozR1=jwb6n*jX4O|B3+fF$y(FsoVgAnVeN(Q?A>P}ilYXpf7)%m(*;9Cmt{lF~J5 zg+kX_gsT0_yF)iU{Sc8p|0(@u;eDiaUB}Y&a^(8wp(bH5G2K*F!<*;9beV2tRqM4` z0Q#JymcGx5Z_UX#JRYS>f@Om#~Ef`M|yM4*ZJ1Vg#=fOrIh~A?;7nJ!Qg{0Gr=Ia-t(-^lenK zuIR{rM;-qCtN(*)hzUdwQcM_v1-%eUho>5X4}aCg_ZU9EzE)1NrsbCR(@Hz`RY67Z zt06F`;hmqT-paOncK0mCfKhCSa5!?OUvo4-^&aKk*UE+0v{Zx#UtPG>oqi=Alk9Wu zT+EC0e(9E+j-xC*G-ekO4!QPJ<@jDqN$bd}KIFKan4WGLZ5o}FbVpzFSi&x34+KNi z-kEaa4+8v&&f9}pC9^s*b*PZOOG?Ry8{yud42eQ|JTU>OO*rU)92Z9C&4Y-2y1`ml zI`N^xABXJ2_koNyxHVXrLW4+=^@VyREm!>*Z%1qW_kSOnIgpca!E73GzJX$u-axUML-D{LO*?WRJaHc=60Wdzgpx2@~!U)J`$dl{<)gd zL+)rxqPqPcmI)}%=OkO{rkH&b<;c9<@<^e?;eU4=`Z6+Y-SmC&FcnXzP>%j` z_=Ej(eb#ut2fUdrzPb3{zP4!U8baQqM|;R1opamhew-sG;rDMFk68Y`uRi+pekHph zRIJOt7asf_7TS9P#vcgF*~bdCfRUoYA#>A>1)%Y-BUlIp3AMd2kX!mAyuY`1cu7p7?1b<-(f*13phTQDsAoTZ6Ewv(k%js*3V0`4{S(q zw1dwHmYevA{{;-PpPD|!Xa`iUKFlKd{|f{aIB6qp?Tj=l)lauUmhI1DVc-%;O=X278BhrGpVG)p=g?~hbqUA2F%&Q4p- z43}GiHcG%y+0xn+BI`}RQ7uOT>h}*8Kycg`kok8B7@v8~`|n*LGzLWh5~xKk5o&G1&JoFQti@nCv(b$e@Y92sJ=1 z65^K@mL`Dr!!HO?WI^}Dm%MAaA&nD-exxqTU`7Sb68j+fS5Mg`YjyyCUx4FihXRvph4x(}(D<}pROy4~T z0(@_S^$%iV$4|s^-pYpCrX?El4~R>`Y8C5!q97;ag5jx$IIhu8R7`Y?rAp~V zkHe_T+2|ie9C*K0CYTxxe1+$9c@RNhkEEYr9Mly~rbW!=u4-Ui!G;CSh@r`>%m6$b z?Pwp1_v@bP1s<_gCq31)WVrb;E{ZKBE-ot`vv3>S1TXXQNV+A5jzr-_IDrqQQxfuF zHU&93xftE;-DIu#>&k6FoFFaR!iP{8_UneA+)DU?jR4rSqxTp;chI(Zrp(^Ku0qVI z`?1g8&US-!nq0Wuivt}U;Leo#FGq2p)&D7;14SVWdZWHy$3u_q1WUZBgUiyl8dTM9 zuk*oa@w#_;>;^O5XT@30U!X-aRp2LuxNr#fgMx%x5Oc)AswyLkgpkAk7pR*&bHVU6 z{j+B{l4g6M>ku(II*>hR_qngaSRw#Lu|uy8^vMrsuH1Db$lP2WHlE_<;OC_cakjO$ zJ;6f8@#Ebi!0Z8qiD1*$!@I~#OiENDhaf|4DF$jVw!gwzJ|rq_LY+&6?xO7`0=x_q zR1`oW;2S+9qaJ@W@MDF_CuVkx%!nl#ad4- z7NZc06A0PeUjo(?+!7zm!EZ2q?DlOO#w^pI*o2Wy?g4fJ+t(NU(#%n59(*#QN)|1O zJud=p$qo5k#*x^31}X`ku^DGrfr%9$rqJFhF?II37Z1mmR{A@S&84`=1KDoQ`K&q3 z+u&E#SB?Y*@U6GqnwH3k>U21gCggsFVs2BE+p&o`Sm4?Jctmn4=FY{}JCZWfyARx5 z6fe8pcRVx?w+f?HYD2rL zt1J2N*o2I0=XRddAkoN4VIXiVEG>ZHe}+kBQ(#3^=Yww@S zkn}t114c>km+pQj0FA*h`ZDD!%&ma8gE=Y?+WKYXJPuQM-uMtpV%9jti?gip3_0`< zqfFcU*-T5?3Hh_1UUs2+VZ%38(03bzjMCrv7j&DRwfv>i%UNmN{a@0}11XSh+5$$i z|B5jmEncnl@?`tU|5bbu;FB@@<8b*u@C;5c{OAv`Nvm(BM=~AzZ8mlMdueC%KUnKO zZrl=s8d`F28DCNU@BdcOEStzm^fkf)uKV}v%5DRiJGu}+b7Sbi3<1+Pm=1IZE3G?F zH3i$r6#s&E=aG7lYy>2g#f}>-uiJx^(cTjXRDi>k^Gef>)YC)nCjMmh(}6yjSql9G z`Jp&PB4s9tf;=hX(`P1WxhIE3I2#{F1c1d4CfZE?F;<8_0t6Ee$xOC4?0uL@BPulE zYmiJ&2j5Lqk|xu7f2{89BN`g8^%AS6c|e4LCX8u0lLQ=-1CfG)f*=|_s`#&APY)V+ zZs2J%Ey|2ylNvOU-**`11tBQK9>{gI6kP%4McnD`goyPrlu*cXu~aznn5^&qEp2GF zegbDfdlcl{%Og3~R?o;^DGEOZ2iV~Ev{Y(_UehwOAF|}}_Au$J$O#W73$(B_$1l7{ z#b@AvJmScDwx(dg6$|4tZWhhW%$RMaM=-W7K_^#E=ByLr2R^q@zYT1LzS?O0_qJx* zzFiP&!JrO)GmD{H^xJv)FeVBD!MeQDd;FC{^1bcx-3cG$@H-b*4I4@l^D^<7cClVy zBKEjD7EB*c19k~$pzWtVSe-`2mxtwsfI1L@1a?kOZ)@+bXG??kAF4$-##;(8OBBvcyi^J*cvch0hJ2b zq9H=~mZr7ThP_Wj9*mHV{b82vS{;<-Kfx)F&xduaNFEP>Ay{Y#`_;zzNs<=ghvC71 z9FupK#Gq!i;Ar0c9Gw~d#3L_{C@hnQ=T9s5s7Ar0CBj(r^Gh@S>*nU1J#!(ZSF`mY z71HpM;^Jjfjt>V9nemp|2diemQ3RTl;TQ#7br11xAHZlDfWh+jKf3kp{lfRpkCd@s z^TAIAdvicWn$7!oytcL$21@{M2E2gF**nuv|LyHz^2SEyt09NmrOL(n{m?V7WnW)- z%g8{lk^(#1Hz_`dNMA_f)F~;1tF8Y_@HxS}8m4lmsHneN%S}08t{pu=_tx%%^70R0 zL?jD90D2X2D&q;840Yhc+zV7Nmp~``5fEsv*~G2**H)QDJRoBJB;53ki=}SNJg_Hl zA}udX*gDxiulDmha^3>ZYi>clWM z1_45m>+(0HDM9}Hj_3GOB(@>l^r3B@>`5PYaB5?DfLvN*(l~D^jRPrKDKMKI$OrKe`zMchZ?Q|*N_J|fRj{E_;&Yk0V!JX}( zHGoWB4l|cZ<*TY3+<+KQ{x*9v0YsC{Uqd%pVg|d~VV+wV2hoEqi0dlICR2}{F=(z0 z4Fw7ki+7QOt@Qw=Kt5bI}m4oQg7RE&cl{be#HqJur@|hE=3Un94K{${ZxENbdg;IXafANrBw=&kYxa zkrcu4bdhxE)YI(y-M^kT7jOaEgI=Jr*_cfVeS$yzADD5{^61l{uE+Qbljru|5 z!W&G5pXlQ>_H!bOD-{NDO^w)k-zG-U1oC?R`IttAOuq)TR{T{?PQcxE4BPqh=ViR- zCA_4LTo52h)_`y9^c== z0)udy8&({(#XX`<#$a5X#?}-mXl{Q919OD%+*I0{+#u`vkk0j!+ma zuEgZxM9UzR+uFQIlEzLe>27eB=q1Zd!=Sz!{eNTSI}Bvv=@ZbqxR}#w(1gDulKpb$ zPGF?Vcw-cho-YHxx3#t9M+BmI=_CWSZ{y9eQV88PUX}4L^?@5kKVv?GzCd2jO&5EkM6fOLDqK|m!i5VAgi)D!xQpAr4c4DMNu4!x=gYw( z3|qJT)FTTE3{Z-c?r{UAY)Xm?e~9H-JGcQT8rUp^s*%hQ(?-r&*;rl#nPHO-Yw9Otr1SYIyR?huryyCpX5`2T%WC15C>Nx1)DFfd7 z+#wI4ZYhDnvr25sd4_4SG1)fA=LreUVG-9pLNHz6CijnS5>hgg+J#bJ6Qa(@on)1F z+j$#0vdfP8oni#MVD#Im5lQ#PXZc{P-J9E08U3Dj_dHetX4{o&1d}OP+Hk}1|lsRhw@^~0qcw_y? zu}2_C?SVf;91$f+?I`WL%oJ_@t!o1GgabFC*%>47M?o-i`Rf~$YK6dsLi|{l{ll>? z(%y4DV89a*5rLcqXyq}J&}~EMM9Fp?Q&sr_8ELMm*=_Ep`pT=2|3*=Ejr+!SVV4(g zJ$w(^)M-pe{PX9)l{cr~cokst^gxMft^HH2DNNd`r%7&O@(8xm39ETSbT;pVjfaX`rPP6g9_mUmmhGm zRzonkP4X2#VS#hU%OoNsc`wF4RMJoOYgrB#`N-f z_|g~7p#GUGuJitcHWa!THEd1{r+!%T%UxSpv$$O|44a&RzUIVez8e^t!Mo69<9eGl zZH}`e&d$2~lMLwHB9{odG#b~2y)6UtXlqAAS= z%iR(nqMZAqj-2rR&$-^{CTU66!?Kp@IF9eu5B>*pOQK6uv#t<6eIzT z*=qHdCld*l$&fj@xxn+>ySD5_Y6B9&m2rTvg8oF9 zQ7u!*Nv4cT6BUX1knfj7>Aw(hdk%~Nptr2#miepxv@XYaG~Oo!Tdm1NyF6?2!Y~kv zotI@5E9pe_7WJvOMXo6)L86oN(+*5Ylzg=yX2-sam-0;?_NvG?yCpgyyG~tsp(u{W!d-$#kpIj^FTo(opm+&3i z)>6AaFty|zAP=x@y)m&0<3QfJKfiU)l8|t;ZDGiPWpHl@ywq)okN7cSu-7JUF5%dT zMdkPx=1(vdQ_LVVp9|J*m=}R|6-|oP$I|?$dT7jul$550P0mU3GPI@-jM*@kC-4o~ zbP?|4^JgdD!aM;s{pCrd?a0S8_}nVobH-0J&q@A*h*eCzEP==L3bwElmFRPct)8|k zSS_<2qJlkS6ACg{h)Ekj5uNY}2??IMRKZ^4Fz!1bu{<#WN97dtOsD9ZAo8Na+n`pI zBp+q)2EQ7HWcS)3mebkZ+fP|p@istWH3cKQi$p-l4B!UZ-k2aKC1aQE+k-R@2@IB?&b=LnnRxckY@q_ZfCF4c#pg1{Q+n~^*F?m zLtsROKD@gt!K6*t$FjL5_2f%hV{Dt5ftc`X(R`nKDxr^dgXc9?HU~Ha-yBXP3-t6@-Rjita+;!tGW8NQKR5*2lX8$LtQ}*lOi%k-G90u8GB8s z;c$m_vLPz3_}a%%R*;V(2v{p=YciNh60Tt#YG`i&9>{|)GN-EeORDw`_!@qm(Nds4 zUG7g*_V_7Rz(A3IxIVQvw?{eA>6@9yTT4tGM0puhEr@Og@MPwVD)59;atcK6eP63x zdBo>t-TwWq=N)WKXp5o<~D*Jo*b*b-c|IaZCCO)Jw38Zf=-GMQSaKOcbticV7x9ZUYVVJV%?w(^{9NL)cDpf z;c|EXo=d-ii+MTCGs`iU6#$l=hT-?#`o#ZInP9dT^o{?N+sBJS-LK4(>y{{Ka z5j#jvQPS0we3dU8CUo^LLqg>Jo|k#H$C^huy5jcw5_;NWZ9er;U;UWqHc7Brp3rcR zaxersv$Ih{)Ukjz(lr`S35nMiT~(2>cTd8&LByid*W9SzBgJuhk}z^1^i|M_li}@A zX1BOF z8UkYXT2glTv{e9y$W`H<&@94|7{VxFU5xW|%#rgB~;*jQaJpoHdo=LEW*0HgN_^ZAKvii!zsp?L33!q|dpt za=ewlVQ6uIwCx4cHx_fl>6>@gXs*&eUZ*^$eYi?+yRWoi*P`$BrtqrR$)9tWP-}%t z9}QP3e=X!(uv^ORd>}G2u}@gfCNsIF^)x9}R?8-uoyli%+_Q!9Ow>s!p5TeBHGOUs zkJZ&QdCv>+ir3igaf)7L4aaye5Sc7r*u!wecuz?e+-9)~o9?d0EGY^s3sG zyJG(GMwOX1mTwsD?zCmr6?>J~KUVz`V)0Y;+hp?TH(GmlD8n$emX-s>yM{^3%p{3} z$E#aQh4o`Fd5xnjidKF&Vj;uSp3Jjj-l3x~Rpgq5MIKdw@J=AwZzy~x6W7rc(h7f& z1f3+hc&Apf%riZH9BsM0^=wHwu6%^4r~~EdciMg3#o4t1TmSm;uaPgr`8-|J)w-4& z#7USQ)SFU{)<1s*8Gd$8PJjF*lZ+lx`Qi`gK)q<P;f5Oe+mX=WAwRIGosbv`vf>P|Fd*H+yo1Wc`Rp;J9 z8fYkv?KJHXD>4r;?OmDUUXN+D5Jpgb^NV_(h{KSkTVap|07Zl)zT z!@nzeiE#_V?>D!Rr13N)oNPCcT1{fRH4>smKVm4wHq_3mie_jQ8@MT*?0j-{T#_)z zmC{1qOx9=g?xo-CT;d+xbAqWt`seg~g#ToYvc@Zg<~$9pt1#E(z4_0rYTgQ=H( zn`^JGbc?qpPKIX8@yIz=Ka4rm&1kb|^YbEtNbkekbaW!qGgel%r*5Cjw^f2WER`|P z+gKwFiW-0Tl<~>D{WI3!i74^pK{Sc2IgEnA#nc9Y73RH6cK1@KMd$VFZVmfmnx6?j zy!ifJHzUM@0l zp0Ogi89H?SHmN+-lUp<)Fo{3vm(uXJ@1^7(`#gsdhYF{ed3xz+>6tOLy{b=}d{gyMIx_XzollxNXBYGxL)2sU`_ui~XI2Oqv zXaqv2SR%hozByIh+l5&D;O@H7f$8vhfD3KzDivW-*bg`N79XER%V2&SuLhHZi7u0+wso&^En9-* zNwnhYFmb6&>H;By#pG>nUwwLJ*&!js-NT#GiJENZT&JU-RlIw+LeK`+-Z2t&9N z!s#EHs)b#Js%YCYU4S|Uy;Igarr7Z9#;;M*)$F{yJPienPtS`lJt;%FN5r=^XWRtd;=N2_L5LteMkQ8oFJCQE&+FP z$>O(Cw!meC7;Fw{HnIOKkF+R_7?CK1h+ZToa;Z9`<4oZ<)-PNjcCKv=d{#&%LtZc_ z>%%srdC?$rE6>^1FvBiz^!$-36{@}$5TKyF*A|)AFsEhKC+ditBFKmeq8#`uwRX!{ zfZIeJr_a6G$nx}BYMVa6M?XcK9`$GRY4f{VKTB(*q~_LWZu$aq&Ga@ABhM=RMAb&o zh}Gi%q3tW9-czPm481a%|H-v(48Aq7@6uB_hDON$&2g+A%Dj&?PYKlJZ7EX=2lUu*x z=QNNcVU$1Ya!74mITiYX;-NPuLhr=A>-AG(M*(R#fA@| zQQzHDy>h=Bi6pnYxl`OizmGa-+3>>iXGNURvpHN%ONs=k^uE zqg{?aw;&vhu=S9IwXeaZm)FgwXUiFyH)~60zd-zFt)RNfVwy%Pa#z3={`w|Oc!EZz zF81*P;PJ%QR!RL%{TwU~mZCE0enc8ArduIVq|jXa{+15*>dVea5JYm>Yi*LCl*IKy zw6nBi-ybKUo^G*iXm0h=TZXL9;OspWxuGIEqH1JY{uxg}VTx|kZit9I3wP&EF60>! z@+9HAur&h^H&dI-p&?Xzk7+p`5{qxvm^PP26>OS3z&Fy7F^QK+0BGa|p%tG1@ z=URaTJK0P55WwKTzS-j7`v!#Gj6@U?&Rit=BCa-`q7^FWec(+DcA0w zI@Z?fH24!!LswINK0X?L@0A4__>1=k1rhpgK;1I&-7`yXZi{l}D!$$nUGZbx(&yxp zW0U&v-6~GU1$bk#>)3UOiREW+Ce4}8`}_>keB70>nNmF6c`h~vkvVZO;$9O`PI~s?qU+!OCtGj+sd2@6N!)O?=i<{KxT3tF33^mJx(Pa`lEfZW zxvo9;?q}O5EGgMEpI0f#yZ;HTucIIMk!0%!?!@ZTVKDR%vD)h7YJKxEfa1wsvq>S{ zb;MSRXAFa* zK-Dk1FLn8fV&AoFn?e;Wtwoh%0%4A-g5A{#xkV~oG4uf=ZPJx+8bZ6!`#wI%jBmuR z2Hlp3QqD7OB}F!F!hSUk8!k0{@51^X^3pr+a>EhGYKS3oa`X!-yiVF@Z2V}wuesT* z49yl>=6{xVWIC0XP8(LBcfJ$llHz$y9KoxVyu*J-UqAG5$U{0t@;$(HPovfn9BZrh zwAj@?QXx34FyUeE@r!D`&&nuvlkBm&DTql)MUgkeek$(2k7T;B&Z>Jf-9n*x(~_Ni z$!u~8dhcg)zwCm1!STmOl8Y3K_c>f{mvT4N9DMJ--wW47bb)_(8jS(-rakkTCeJq1 zz%=qlCo7Y2o*Uist^N)NA>-GbU7Q67+2cl&f-_751vk!P>x%T;zMp$~ZA~6;+gEB< z5Z_jy9mkY{Ld&8uoqe;VW#{+U)gABaYDjf(=|R8EzZ-%{t-VAr9FjtVAV*5~ zU9&x!VZET(rOPx~b!XZZVCg!k`lhf7YNy>f_I3HU2DynwBfXB>dyn zNJ`0BMjon-=sl}69$+kb#k9dWAp4O{_t#WLc)JB( z9^*iJ1U{Ij|(QWnTFV&O(?Z^hglo^ z`GIjSs7oJD$gVXMk{O`H8R~&+4Kn#*LZ*k}%QuS|O~QYUOwPOBJxuQSJ(Qg@Yy7(K zuWy1Y4+;~YYWu!tRXcTk=|qg^(shTSSAibIw=Dd#gn|UF-9FX+*=)^3zH@k06O|b^ zH!f4`uInwqgZO|Edbu`U2sdQpw<(vp~SmPeKA z(i`BO()xc{k?C+>P8=E%Mq!#j^2iLemoOK>AZ%>c>M6rZ%(b!=t92b#GMUSv^{BU? zlRV^`y=V7(IJR>ztCj1?*D@{38CFwR1~sIgXJS~IR@x^^`lUReo?x&I9q~LP*(w-@ zXzgY$bja0kW1u>2MQd-(7TPcBdhjvAR?miWY3&!D3zC1qMnXuV#se-_bbq0$Wb99TAj zd7UQ7jL7A7xho;812+ne+8)cIrMa>rQ~aZuOI`0A$7@YQz$9%!zO~8Y{;cMdOX+se zBS$74swM_1gvj{9K8NAXY^{k?yYZUlRIWv#9)pV>y7zIm{@=f7dpmTk(%?eYlm zFaCsA*PWp9)QQu1RCTsvi^yYZAuh5BUvvSS>Lqc78KuvOUOoNcQ)lvxYqtC6zPH`4 zaZ{VWY%9?r~ubW6foq1DpuT_BxUAtct3~zfK^l z*W79kw_+e?8n6C9e}>rmjAG)!)_|m%ywSD$UFs9*76tk%bAx*Xvr2{qDfmHw`q8$|GRjHASD&Dw+)SgTTIyIj#La#b=Y)GNWR;$R zHc;i%%Ql!j6E_uIFv`gxy(-p=j*XC(?>VPtt4g%+{l(+`ogcna$}gnw<-XESSyNS< zTX@1vSC}_FR7@?B)*URP<8h|@sO~_Ixg$&ke991k4R=L4hz5UU4rRK#K8&w?t2jbW zLKEhNDx0r(HmLL-KR_!j43l5@oT4!T)uDN6{-GhJf0tfFpl+;V`GAD}oQOlX_*Hxb z1yg*Ml1Ve^y<1h>9E17Am^(=yTm7rJc-8t+zO0!x#S*4h+`ELwiy;lyymvn9jO2M{ zAq1>o@26Ah;ec*LC2tYVg_;hhexeqwuB@aRY&a1={jk39(ENjnSru8w7S8IVrgt-|Vab>`U)X9Xrm*Xmv49agTzC zL7UbF0;*Fik=L62?&8Sb{!Xj~#U^IGP%ij1?E|)W)u(sfO87Z#YI(RNEK-_8T}KwA zJiXj*lJg|;Y{<{_3_^mn^X$CGJM-P-)SUeaGts)N8VnUHpCOLir0IhdWV!IecT?2lOnGK} zbX})TJF~57>tp~j@$4}HrXE!iKi^LadrUj^H2H&(cwSd_lGMIG%Vf9-lZMV!G13Yu zfA&7;pB%q$@12)-zlw@C8;oogVkKPmg>}_-uJ+8OeaCoSQY0Jy_=vmPW%bMHha@-g z>z3w!_)v6_5xRw(WNh?2h`bXb(>8UM-2>ulGWLw(jj0>OjjjAVrw`WdgNm_D);|GV z4c;~R-9Y<2Bej+pHrPI0vjrmYHM2Zl$IWJ1g@JOtgInO{QHM${{h3H9%3aQfO{SVO zq58|~hs5_g@u^HRs48BS;V72~#Dy~57N}o_o0{xa?9LshqchS*GPTIaVCRFVM2v@ zR`-)?8h?)KkG`1+_eAKt>4e01yr+kN-2Dt-sLrZLixlxtb3T>3ETdvz<{Eq!LM5ZQ zV8GFDpS$NoK7R>0aivGFvkP%Dh`+M_ba>>H#mvl_r-+hIBYfK6<7qq7mtEV_)9Wmd zZF0pk@Qr!q{F)3(krR~^7+ZAd&c9nJ@{hJl3W?RS5yNFyS|5-H;rz4Z^r|698 z8o7QFpgN3-O%1(-^}Mr9S<?f8|PQ?(wa;RhgYBAX~Ef3fCowkyM+PO zYxFr>^n$_12Mlz1r*xs}=7P(9ISx)+vOM;xx4QhPCU}YdfZ;tKZ_K^czUlO11K_1( zAJhtAi52{diHrOy_rGmWGft=~9;eZkk#{xxih=1Y;NL+_%Gn)HrE=xgjlOD*H)sV7 z9lVn%t_=K0ZJimz{l<9C05^;4J!bdirWrTGqne#;?h=s||eeMjCLnM#hB9Ubc&T%xhG#hV(L@&%wQ> zB}}g0-h`Lq;WF#Gv&iy;J}2U%h53hZ)+~M$NzbX=ML@vNc?NgBkSu(tj$31cJErz^ zw71lYcYG7x4U-99ouks-)^|feJ2jB+6THw+@l1aGJpyAO$eKOyd|9^J=gYC?QD@4v zrh{jF0w$eMrbmelZLq&)PRIiv(rb6t*V0k5xIO@=Amk<-BWV>NP3Pqi~#W<_`X+{=;n5^zGQ)8O;u8ow@t|XtJDLgQYUr} zY?i7?{i&Z`;ARsqQrpz>h}-nuJ?H$YpVuG@sUmje#9?f$xXa<(+;}?bMP56KDoiJT zFLRGEhF92p@^ahmVA&nVs^!MK&!6MhqLGzl{&SS_lT&c@&`VksgkC)pDaqKTcSq{z zac?KOT1!K~vGbJ#C+DP#kA4D|mn8`84Bq?SS8H**a7A5Ypsenqu~$d#iKW7C8t|DA zai`q(YD~b!R&NSmuBNCvu_RJNNSG-S?B&V>4U1vch|@(QdNEB}6++&7XRc@*nC`8JXS zKdb@nd4n%a&!0d4$dtQ6J)X~oXlrf#LcMlj2?RGuqE2|I*t;)at<`{bY4T(8c4%$h zTwF3;viH5V;dCsh0N7virX8WIV5KKmuLmwp5+q6+Q0yZ8MIU zbNTWyfH5hNObUW)H{LjBwVsiiWqoNf`pL!e*ES=FFw=zqx)Jv{#Gx$rUfh29-E#Aj zD8W6klS2yP+WUnM`>y;nL1l!`yjf#LrV00MdgYAbyt}5TsR_+~tvYYA%2n$_gLMv_ z7h;`9W*9jRJUMpG650MHc?aXyTw9BQaO8i9api8WvaeFVH{SdjrX@Hy9g92F;q;K) zfny4{BKdF6?N#bzM^?$x>7SD&yHc)+tze`^U)_ZcpK0bjR>JBpo+FPRGe1adK%Gl_ zNlwS$x5<8$Rqp#aS*5|7*!1-!AM&%30>FD(DSIXhaBXoBpL>ZZu_;l-+a#51Rg7n7 z6@qh&QiEqZ#jm<$^PQ?xK_pX)*@GgJ=6L6!N`S#@;KwKDhO!ASW- zDW4_L!n36^@oY~-bkZM%#p~$ktY2Y{OFuS^vkaNN5;ATbTlR29hk4Nz;zPjEwEE<9 zz&Ulhs_JdJGffT^bNcPE9aMq?kR zSP5n1-jCpTBcD4BLMt&j4Q$ayV_ZZJ59(*ykNroBnR+KtJ|V&T$IXxGPzyJ)JpGq4 zbxSoNM2`UTnKS#DAK|ImQI|E$VvI9AHiM#fxiea+XcEzH`F0wzB7pC*J-d1)JQEGk zJ@@W-0Pu&#m(rvdp3h#fTGzaXs}bmVrfRUgbDXijtZ;dKxUfv;GgBfub|+~4XKOr* zRuu!P7rCc0TR+>W8bUb_W4YQ}!KAutx|S;@5gKOrHvhOM2Fh zdT4{~qUgeKkp!`(V7cQ1v|Uao1>zdmN`|khh2q8E>Y7!ZPJg^-*0JEKZ3w$<*3?AS zubee`rwKt5TB3w~9m1e#5IH`LjB4s>j(u4if|2xocjn#~oTpe_E{(pf?iEK_3&o(r z$cTTQBQQ0Com=?r0WNN|fAOH3$Fg2V>wp|^IOAmBN-p+rc9{%?VET)YWsHcfG< zmJhlC9g!!LQ!9&yN<~AAb#TK!-4rMQdU}QnS2N$dk=AE2<-1$?wgqMPXd}Zx^5_#f z9@G5%KcW+I!Vd-N(Dcsh#^_9Txj7^aHmKRk3;}wy*h|bgrr5IcGxQcnXr?@QU6)yR z25FNh6EYN-j3bKZl|}|WVhg7U4T;cFS8dQqFZv=7jbX>6WLC5~YkIU>5g|gwpNQ)! zkK3$YdGk>SAtm9Zob(1*Jxa1x4c4f8b>t(FT6as`%woCjle+9>T65N+&4yAic(!^e zBe58Qnvh_E-rWg0(z)@op_tTJ5)w!}n)xrBPBkx{9aJ5nF zs!p(GEr86!zx?(bo?kU#;t#6_H7)M2ucE&1hmA?!|8>N-SjT(M=OXlFqvVcgI*bKpIT%5?)G#C`>mfv+{s3w?-8q z7iwNf&h%yQmiHG2*IY1TCQj@Jfl5LCCjQKNr~OZ!u7y&?^Yh|iD>oi(iH-02S3j2FX05|rv>;{X#0jm zyl=GI9?b}*LyT<7hSGRW0>opaMOZ}t5eAlKl%xwHlFnht0TX-=BcQ_M>~r` zcB^E`A({s}cd*XDz}-K-3*eS_SffP0(u#J7^wSJ+n@Gk$yrAPZM&mRHkk79}z4#dz zlBEv-RPQVgw$#{)QB;YU71CWm*jjt5-&(bALiL*2nM{JZ>hP*#Cxf{u{YxIj^O2Dm z8CQU~w1rj#U;|K%4gN-(S=AA{<@Rk9DxOzcPp{l^fbVD^K|d#`wP{!{C8oGSZI1(5d0Vz1s8p_>VvXWu z8ufi+O<^hQL~`=Eh6s0So?9}$1Q*egEz9Wp{16V)cu&xw7FianU$#ahSUc zuQ1(UfC6DU*0GZtEGBl#MQ_|diuPYb-s`B!LeCoB0f7*EosbxjVEWnN+YHAO!H)6# z`6Dptug{410{8G6@ug^!K0?G%m0K9#AQNN8dm$y~J-V|>g!f~+1P}1_N*)*oZ>Nlp zrWdRbpaXQ@Y@l^P zGACj7p2&b-y@4o4no#R46}|i7hDuh<^R5k@KQQY_7&qo1EzNz~6N^LqQX>G>Yz9=zN!GvgkObH^K zm*QWc(QeM@Q%QA}qK%Nwdpd46-&)J0nWm;qr*kS^YRr+7H~(nY`TT~_xh0x!1-n+i z`E%||d94c;+;McVom-j~cI-6rTJI?~S8?GcqMLg{Pqn&ve z!N9h?Jhlk88d{#j>60lLjhec0TE|dgT&d-bgU*Dpe=u_uAdZ@TH$w>tS*Iq+{o;A` zx%SiLv`-t0*!l@QYCtij5DYz#E!WJsSD`F^pE)f{67{c!$c&xDPVaxxTEcb z&MCHEQ%b~RarW@&OXNONjlSl#z(_`Rfkw&OGsN}gJ*=mWpjQ{u@sS)77ymGS82kLr zU4@cfIz#Vrmq^nbQ(1H`Q^yQsnlh$czs*HTefC-qx^~YL>KLUCrW0d4(b4nNvjr#v-B`$XDBooYav78L zjBwSWE5Ox(idfg~_7Z z+CV_l1CCQ<({NNDa=<-ij^uiAGteo#pb=<#>-C<5n2>50*X^u@Gn#w;r*246ahWJ& z&;&L=B5TuR;*1Lpd&(&HSqYdog{hPTy@OvEWq5F8uRt3$lN7f07rX`e8ev?1o;(4 z>lCe=U41W&6~678EQe1M*$g6LyYcWB~%Z?zu?k^PGwJ~+q|?| zoYecCkfWAlj$9BAZN7%G%+KN@i<45a(kO@we5Mx-+ufN_7!%w2wc$(TrTdo=f!x9E zsLHBH#aGkD-x4pO!*M^s~@MLMYLO*yuEhvlnq}B zxlq;dCkFn=GsI*}flSvakL3)51eyl7`sh8?PF#_ zR>cLqOaf%0$wig{nfGkz*Qu6h)^XQ0IVlnIzn{8SZT}1m(=xp*1Y<{TpgB1?HOH4v zR$kvw&UTXYh%$L_L0!oxHvy+0u?-am;sx_aW>R^R7Arzl9>n#BPbya$-#t~O0(%d+ z-f5tyTW8LN(gs|_3wb4K&V~217|^jnMd{NKI*n}7 z;KznA&M;Gk;P%Hn7$TR>p#3Q1ZTKBv#s&pzeBpK~dJtC|@GyNaF^;XZZI;f8A}#re z#o0(=I?5-}3FOspXhrOWT>WzYvmV_JcH_Ovvnjrl`wcYSNRvLRIP;Wt#i~L%FaF|P zjz0@yced@Ad7p~Q592I2#37&OuLl-gu}yxAatRnNr08+i9kYTePF4y_WhM$8x3 zq}otMHM{sP@P3A56A}w1W7a!+hO#G%S^eXsfN*^FGu=q_UV7xCkpK3GZky|AC;7A9 z`w+3pu}0;}8k4&tVkYAH__FZNN~ zABl!;x)jj2&&iF@NIYOBBW?ZJ-emL71JrjX{YAiSjLHo*EuUU>3+~}UxN4H78Cj4%$0Y^2lsJF@B#MlzkfXvzLy6PJ*^l( z`eowx%nIg4`+upJD7R-Hz-@z;R}SnY%|&?z>a?Kt9BRJVyc$3H4e^taoX`Lgyz}O< zW9B1~7}=4J4wN^1pf{26W#TUH{mS-Owq8QSR?}c42K3x|>L7*6e!&lcr~4y$%7dS) z#`s9D{oXfy2d@Tg-j2iE@FP#R)-MGDv#enaHeb*yu^^~t3PrL1`^{1j1GO~E zQ-3}*6J2tb8qp~p0y*M^w9%S}1E3BS+XzI!+MW%SdrcZcmw zHMV6S+H(3DG-X+fi2hRHfA!{QlfK+1($!^i~EwM`U zXr}iA_|#`2IUedEvzBD4DGP z^nA?w8(zD_$lLi&EmJWChoHev+>&AYgK-KW)TYxTAL@p5wTO77e1BoOuKBS{`T~1p z@P!89<*QK|Q=`nLVUQ5gOr_iHGjC`@!$ZbYP}VSvCb3Sys#l@LNk8qM_;Bu@pYH{c zhuAa4MHSh)O+`H0NiilzXgzGn-0)h!;X38u?iijaI#vy_xtBR#p86H_5K`zlUpHqp z>L#jJgny($&FB&$1aH)zU!oUZDeq%x_#MeA!AThM_RQiy9xjP_6_J1Zygw2l!YJmt zo8T=(|C05{_jpty_E-L{KF`P+Ij`BlVfU4?a178XZrN{LSlI!aZg1%G>+|?%Xa1W9 zxI~^=R=o!)VLs!nt?j92CFwA? zO0LmZ4F;&VMZu)BbaWT(YF{+NPhKnbglVZ2#g@x^UJp;6;?6%$=GHebuyJ66b{*TH z%7?u?NrgZ|jw-Xz7yWXmUtoy96nzRT^5VFpwm}dMLTrz_^kUX4LwLfmuulv!NEiEa zG}koejZ?8})Rfhl#Yw>~0%2=6wYs%FqQOK$8!HaUzHexsh6%Ee(zLn_y;mXcBk*|n zNh#D2u^-824ZPl*-%sW#)Z>XP!Kz1=`C*LtzZw&p=S5{yV!)T zQTJr+Ur+C~HPc~XTl?gSwj8yij&Gp++O^no zHssj@IwFjk@0FzWIwlyCIUWb|tE)K=Y8|dUZHSIA<05j3hy}^Enk;XVG)sX$2Wb{VN-qM#T{P?3ZP&D zX`0gwlQ9^h?9xyDd>cgh2Eg4|?v9ak`1JfP<0_YT>Eg;4t4~WjH23Mi^ zqSTVTFGfZ7CrH-5;KQ_b`*S~q!VC~EnXSdW0}5%hQ@XwJ~5 zITMoK){mjd4zdY5XMkk2ih9sqnBt39gM$#sy(Mg$S?qR!>xtT%<4wqtX)jXpZmdCq zVsh_Lq!*q3taX&X`WCLnQ@HF}liz5G{n7c9233MN)Zt)W>94ZI{-iq8+XuVvfx-a9 z37Uqij)qG`dUi{~w5Bcz3Ie}&&BG%Y2ao6l$-55x^7I8a%CP0%0}c7bx1fEfIELcP z=ZAB8Wfmke;zhTDIUl`2e!JOfKA8g4g`B@!6azTm(v+a(V)-taTq+U?wGf%+eZF|I zFrxx#t0z8AcO(k{S1D1`baXb?hh|ENKk<0a|DF|PXT!a??J(j1@G2!jFdu{-dem7s zvGg|k#cB+3(zwvN(P9+j=BGY}l_;IhTr+K4P>riPZ%dOLs()kzmXp??-YmZLO1@eo z8KYz<;Jh9FQpS6KGNo4`3@8PDUS4nTK`m*~g6U{Ho;TlVsEQ(-%chgAik0rz$!+WD z4P&K3U$e@oxei>J7x(NKW4#NxUWEE)zE6gV|CAUW?+-F_{(RXYkrv;brReNSj?qRZ z0G^+513eV9%R$pzJxXnn!l2Yht`^ld99U2mEt)0`&_9E&@`X6G{KijpnbSIi?9w_q zlu8TGOmcoRjGABCtrxX~lUxb+agOKP)>h>Jq|tiFb%Hn=|C*41kPCA7B#MVd0*=Q} zAMF{v6a9(>u%rW^Rm{Kl)QQ!0&HHInU=4(Yy!&hxxTtpJp8G}7GY$I!o^)p;k86*^ z4rzu|e<@D*;hD375W+m={OU~cBMrQVGeWh*iI**6z2$`WI1FQ+Ty*~PsxZ@<)kLMD zHUS99Dl>6_u)6-r%zxz-Jc#E&I2V3eg z^bds(9Pg}aRu5yvGJ)nxH_J+|gC1W#WE0VFf z8EF`N_F#Ka;EqK450WE(g!@ zacZ~FG%q5FS?BcFKF+3mm4dkIsSM%trSEHikiw(e8MK!}A#%V7lnPe*0+2H0iPmF{4k0A?3XKo0Dk}Wi&giTDwVC>VM>1Y#p*#x&x1$XwUztZ3%Q$kbuzVm#=B)Y&*0txly__wOI9A9waY!6r9brVermf13_1(a zb!$sO;54mfI8PiuI1ws^%?ip!>`t8dvAXOYlsF*tfqUr=|NU>?!|mbc-bT6l_GwI+ z=Xm+iA#!AAH;=3Le+2SHZx10`3Y*kv!BGMEHY&`<-awjC@Ncm`@0P-Od zUSQo-I5rMeK+wLvGOXrt=OqXUrhcMFW21-K8z^}V&$+FyE3Svg^;asW7 zgO%0srK2cE7LT`L523>$te)b7x#i0Fn)?+drxDN_FYeQ>S9L_itJnOCtF4oZhiA0d z_Kr8&8g|fOosQ-`J_kkepRGUQ7DpE}kv>AbqsnK*ct49w|H$>K3yB6zS@Bm#U?j6F zZ=&-6!G>$*Vy=Gj>q@KW)Y*}3fMP!L@Rn}T)ixnW5rtj-N1Icc*pk2mS!DA8lm|;= zACu?$pJRI*;GI%g1Az`Qs=;0>>0k`pMZBYlP~>OSLe(i|KY3kLP;>95g{oOEgbvsf z*vW&jL$T5G14F+6XWs&X?orZnHoMoGcg)hJzNPx(LrdMOSFvVxn!h?>bSdI1)|~m@t@!R z005~)+U9t)!o&A)Vs;6pi@~@$DT5w+Wv#l|o0bY!B>7S&dZx1#A=B37xocsk+4}nT zG<;pbc9!8Hhn8Du=%26aBZlP}zs4-RiL$(foSmH(c5!;gR0;RP=&K6rDR+8M+CegT z`e=^3_(#4GG~n0_3}1zKlKe>G3WB`-7K4=fYh{8JXrHL`*sw4+XH%T?9bVqoA~9gP zS=2$1+x%u`?rll3kVTocjy|?y@Yw{JQKjomakCGt-07b(`eN6QpV(yC>Ao9PDf$&_ zbZ@)M69%O&9h!GLFMZp2`P@CRGbrS4t^u)q12hFM4V9|&>Msd)=rqUQTMEW5SZuez zc@iSsPZc)!NET&gudy=sl@1V*4A;{N%Rf{k`kqyB?WjNB5Y@0Bym^*o>wc=cD)P1? z?=>3FIkq;-Hxy81rOtAhsqk-qg~P!>5iQb*E7-q$cDfiX&+;Vx>TSHA zPj*APFI5J3A8ap2EDl5)SOETY=;ZD)^3h!7#tiF6Ka;yw51aiwHr7a=>=F{WuPoe( zyYU6SBIiw8LKwM zj9lK+j*t~*&y+quqxku`RCUd7rCfhUXOk!Uar612gl8|uL|%jOv%TglZqPPF(B6wMaz<<5%ru#YfCCth>QH5oC0{rhzo{M-;*bGexK`(zUXb@|D?C83sQ4j z#G{N>rkgjX8e8B8lKrPuTHc!0&f3uV!}7e-z7`i22jR81VStl8(c)~2v+A?mLLYDbS> z*?vXYen?%{+*X45yKn3^!(Z!w0Q6I3O-fSE4+Nb9S$WA%Q-NCYL0 zDDUm;^y>cD5rE^(x7XG{pWhlOxo2dKjSumZI(m9@V|ho> zUxU>+jUYa2r6uM6=wXE(l4_r215mC*%5%fegW+KB7bpsRJb5pP*B6^-$28q~pzx24 zK$*?&*I0rNEwYjo>_vRBk>}?Wq{09dZY>WHoBK#SQikyh(VCEGWqF9#I1LgBZ zwE5jjYPQfwrtS6-Myw!K18C#WI0Ko6xe(*_A8nsTXhP|CT+957jh(IIXx~;&?ZrHF zA?Q*vfjmShxYj!6{e#;kvURXYM#>!c|McmDe}m1pmNqYldRzNOeZslS`4N!z=FF8E zry;Az46EV`uuttj2fN#$ldqM3N9sWC_x6WkCtSqZN$pvDj^Qd%hck2+$gr7Cof72- z$5*5Xr1qUV*+iyf;sU*c=qH$`pAL3i=R#aB)P$@)tVNlG zkL};oK2XRfq1YM<92_nUzy{}q7aYE>4p>@|!81H_dI|*Img*^y0c+3^0L?YgQhuTE zc5T0ZhgJ-=6v;=<>+-6}Q2m3VM<-D5ih2JMfEP}ore9E(lhz6g!2)BnNP^o*+fV(N zh8+15mWpnnw??ihNlw%@Dw)UZJJGuVML-glKZ$DhUr2PIYozjPJg12C*$ly3xp?ux zy_qDg3`1=zK4nwt8=kHpn^2XEOOE(Zq!S!T`$x6cM~SFqoq7L58Hp@EdGn&i7eL9o zXf#wqb9<&xjzZdW1_>=15NZEVH3Z>Vb!=U)jSF;K+^3)aWUb@>hpf?7h`}i3)L)iM z-X?v}o^-Z6x`WP)op`83cE0p!hAi(VQ8Qb@iu3!#GGpBzQ%``(1MvLPXIFuNG}%&) z%gxTlC43sE&v}-Yow}uSg-+6f0lRy2f^T~t^Z5R_G_DIH(h13V<9N{lS~G7rRBvy; zyr~rz_{U7c0l=}2wXLO#Lpd^TMN!unMfCb?qNBmu$@Q z6asBDp@r``F$H2{V?zqP%ba92m*Dhg%Se7`e64Bz?YkhZK_ z5y*auw&aGNQD!{0Z|=X~%(zMI=cWQ`BdB(80wzKzWIfF9&UERP@0|W;zgaP`}fsL0{~PQ4@A;7suv{VS9S~y9BMx79>JRunqjJ@6iJe z@N%;BlA#I+%zQ6VySU8T8>{L#l;ToRwklXt>8@*v_C$%{pEwS^QYZ`4hY!g%-q755 zSMS+`lDC7kvxu=XFfPa%2(sgiE_6x*R{2Gc@eRO#!nRjoi!5!;{c5mp6*D+ z!^^54fM3xJ&^P+{&_n*Qc-kiTh^VNjFs5Kq;zBJ*imU@GRKBkbcf02cI9-y=dZ!TR zV?31gb+f}5kOH2j3D!5;MVsbeb!tL4IS!Y}CL41=;|av*lpEeQ-3!Tan_Ek<3C)=R zqXRMlf=9`7MR2w}S8~XU_Nstd2K@&7rNRZhoRQAx^zii+Ib*!_C8?f{57Ls+^ zBd6a%lMf8shVIEi?-9|zX*AtA#8?3h zeZX-lr&J+mJRJaGGUVA<2v~#$2?6o+30ODX-|GyZW{ad*dWY*k~bF5e|LK%zh-!%%w%Yt>2BpZ_It4KRBcl_%BQ5O(r15- z;~ycCJ~S%Mth9na=;c2Ty?I%5(y0CMcD`*fU9MXb4CWz#E&#I_yDU zqhn5);Zx=C3Gnj6L{TRoq*9V%{(W4|7hb^Q@{&jK}CEQ6n7xmkB^Pzc~$c!=EaWG$>F~r2D3*u58}81o`?ONk#7)D z3%G96dB!Ul4!hgeE+^DCb^j!ztB`Psf!O@-4i`W?t$@VpNi($f6Z^AHP68gqk^!x* zZVuDhckhxQMcwV`M#T!U^Z6SgGs&zF{`X(vAk@mLyqK@k3E zeLdrlyiLMub_wt(`P={g11VdEvCF54|jU{_gQRbf9;Gy`q$z<6mgNld|Z^_Fxs ziu?F&b>$#i5+Wt`4$J<$0h2#+!Z27(k@Z91Hz8WP6A^t8pAP?N5xjj5CY@m$T>ieN z``X7=swamVU7&vv`SHd0pAT6Kn@Pup-hVE|e@vm^f{6ZSn**;N*`M*gsi{%upCh7E zQvy5UzVBWG4FZs;lWM0asDXEDz*L|ijM{x=l#`n~{R6+G^bYXNq-E z%N)sKq6O85J?OYL`B=4f<-o-vwG7 zEPku!haE80%NCTF&v+zx@C2KQ!AgFCR4jmKt2hfq_z;MFHm{^R#^Y2fY4Fz(rzzo)6cuQYoAD6mu z%#)wkJSrOJhK$^qNia1Y9UG0}au_MX^@mXpnR$7-l#M@OmkTBoI_nj5RLvsPX z_-k>W(M|pS{JYuh!f|Ny!xI^P-xIgo8&$izvokY28%@y6vG2BoLqttU39Xp(Lq(L> z)GCwc#dWWsTHTJZr`K24piok}6#dA=W;-+{5v^)iI0>oR-#dqAk?70%d^a{FFVzn@ z{44RO!#X|;#W6VFz-BYD#(inAfqMt%|Ad$!1K*>qJHQu1BAhql3|=fo#gaFmpy%#? z`FC3jS2EyjGamy4`}Zu{y$APS$Z|^@dW0ld)}g0ICo2!KiV3&Upmd|-Tz;ZvrGxFUQAM+vHyoZ$FKS& z_DF=|V$VJlo8D(U^9+lF{w|D~eozt^{=K4?2t_<2xAhTs<#^*oN-Nh|s!=9dIstwf zC%(sf>^2YT%j*Sc{3Ta@RFT$z)RK~tGSxxpuFj{f&>_e1>Y>K3>6WCv(A%JskNY=% z_gxU9oSAXFD7#(`_|R+z@+C=DD^1;!@sX_H!SjYN5Z(?v$561Vev#7aY<2uxD+TTs znmXMi*}wlu4RjPBHE=Q6t`7(Rw0jqyQgQ2VoE2(B5kI`jDM4$Uu?zK-Eim`STzZOQ z-q`~3J9h-j!N9;jEzP#2silSDLtXETxDHLla#l&4w7_3_{r&V5m{)0@n~L*b`+HrM zHjy|t)?73wmh_%`Q_FE3+mk!55O}GOYGmzyQsyLy++LtQfWb%9ZJTiG@25z3|GS>W zyH+d?N-!?^H{u&;AW?J>(O3jI`!wXO!Txi6OPOGdm5c!*J@NiEm z&cUsp@t~PU|L`as_fr>y=07RD$|$tpvj~fqmuEKjFU}m#K-`B+|30)5nW6aefgl+& zzWdV@TIFH;fBedC-f#DJYx3wqx~&|hm}FyTVghz8RbT7qXEgIl%(e|{{aSG$>nW1qYRs_q^< zdq(u(C>-?l9roB+WIo{ejQyF+k-yF0<%f^0OnySr;}65QQ2xI4k!UX$Os_q+AZ zse1RzA1Nq`-c9#fbFMk&7-KGTDbn1{>3Z>kFZ-?Aa&kysUtLL|hcIfF*7f73w6^vo z$q(}ltE2He*B4_uD)zm#X3iC4bu4@yx8uJ=hJaxwiZr-{Xl7%t?nP;@oBDti1bCc3 zbLfQd`J>^p!@1p}hr(E%tYj8!pfuT(7}?)t8irQbEL zJ6CxXuq!zh9(tABA>PfGHY__Es_Fv6Y11d?1%W`DxV8x(ArZK|3yyr&qf15|ctfl4 zp^HB$4ggQje{FrfS*+L0EY$e`M0$<$GsRWA|NC@^|L8@--ISWC8(WF@v+3t2Y3cHk zvU|Xg>R_PR3}aX4`5CBA{_ApFc%W>c%m+a0u7w7x-@d|QOs`XM@0<^Ky#6c!_6D{N z&JfEC)oa&QbG_1l3#yvB`nT=#ZMF{|00Xy5-3GcMS>3W0z`a$hCN{Cbgdgg^t~~n* zhjCw?Cj8zVrMu48w3Quz$t4ylP%1S)&LfoLk}Uq?p-OW^280DmgabJjh{v!wZ2 zL(F1#_5rQ5H^97@*8C1&dbM;a)72>o|M(hk3fRfZ>jngTfGJC&Vxj345HtbPxd|J< z*a-dyfM4knfq*kKX=hiB?6a&Y+pBpyzsbj^NMmFW)AV}}rNIWn!iVoSpEgMu<^U%| zRO+xuvF;vEUTzUgj`;NBrGB&J6xI>#RM?w$-4UI7fR-*r>XqJK7SPuR*r3!~PsF6f zpfUrb|BLJlc`B2y{hR{ zR#|zb=oSqSFfva&;sa*XCUQ!(IRBD2wYBFSX7uA{ndA`5006aW_j0<>;MBnjw zoVEjj>s9+++1^vk7(se&K%m7EYkL`gqw3WCnttEKLm~pZ)Rz}6+qv(?L=c1_S&cdkS2NMiK7m?zR99||1`9{qwy7s3E%Gk@b%X# zj6N-LER!GZ9bjjPzKZ-&r}0N_Vq(dwG!J0e2S;`VB8lMiWqqZMv<8FiBePVtNH?4} zUp&5h!0{WILoB-^MLchb+ycxEKvV_TGW5QP`=aJlg%fex=XCKudiV2N4Jt8c@5bk8 zoTFI<04Kdyvz>B8h7DkaH!sw}%)Kf(ztivRKni3{0w$zJMkO6%?-`uEoB(dZn^G8$ zY3vl-ehDX?hu3PPj6NhXHYOHAj7VWg?g?P{bbBbL3D3g;9ky4Okm`EC8tGKrA$fM2 z^ne1k!NfS&)Z=jvA} znTN$W0}fk~8@Eo^f(8-Nu8+4>=BG6Z78Wq|-zp-!X?ne|NFX&n+3umfW}+&< zVot8|r-dS;qb_jSfo1vn@rPI>T z0E3Syt`z{W(JdHg0n+6Db3>*yS^D02f8h=_m0i+KS3ogA?BlahwV4};0uXSa>`wXR z;1PgEVviP3Sig!x8w?KoBR8H8fB*p0V?ig+QIEc20uoacqsgmYHn%rV%2Y+NtH59w zV6W6CP=F@fB(!TAtqx~j-QVy*bN^jvs&uX8R#(al-H!saSWo2OnB%raeF<|ytycW*=!%5q#Sm@VZvCz?1M&+H{l0dcB zY-}&UC+Z(qDJk`Ey6)E@|Bwh(@B09&fSm<9wKDe8`D#iPtDPif6?j+va|Z_p0GAQk z@xGw#PfswuR`co*(ZYnwSRh(OpaoHHZv2ja^I8(@MaJuHB0kEAk-)k4Jmk19A? z-O&AYJdQEoB;s0c=>#bF0X2Rln-ySnH<8dkG9ZuDn&N_W{O4Wkw?(Sv7xQY~7YCS%$(Q!N+?fyWO#s;^;y3@B7RYI!qpuG#OYu8JgH!s(@>YN4 zcmbHW0#yzJSOeDqmN`hQy4-);4uEsRctv}bSHmB`f322Nv!?p`Xr-JcOa(4QEg&V* zh>@C+7{V&%pPmC|-1OF~HL#=UiO4@U!hJEZv>G(e@v0?)9Wi-|D*TwnzMA0yVB`RA z(fQ&EKb1o?Fp{YCeEF}IXcaKqiC%|-28s0X^}ho)yC9&SSxae3#a9qH5ZdhuL}^bh zVSq&e{LVXoE_z2FVEqGhPoYC!D`sq9pjo$i4aKDpz3vadonT@bu+jWZZS)n0*G}_~ zX#BvVyg6A8%pk8Z?&xEW)6V#Yb|b7M~!BRnzq}12lhq@Tcwo_8#TDbY>JF zq6Z-pLRyP<_q+=Z?g+4mD1HZWhl7?|Ef4VG_xh&>_p%hi1_6_+c-)@n0cHk3y+g2G zrK6z%_Rds|F)b31N93^RzFi~v0q%RGiO?V*XM|y*t5X&LCMH030iu6U93=lr?-TK01nI6)Ib-GyJNr zudi%8lQ5#L*7A1y9eT}gMcCMr(pD!NJ5l-F~!wY5-h28}09^VLX(I z**uUAu_a#shEx0dfmi8?B-bi`g?hS-it#ME*UPJMCOW8Clk>#+xC0Tpuy$@ zq~icsm^osQJmb9=P{IOz#VtmF!#)F`@W81iEHeD%Lb>Bu7Pcvsi3x4; z0Ke}jW=N3NxTNFff zLo~KDAhG`ph~&;*O}}A^rtHZ{w9J|?j&LoJVm4alqJ!U z;p+mt#y5lVEx=(ken_3c20Z#5F$=}Y5a0m|@K7+-RXNdOJb?K$eRP!mT3F%XfPAnJT(Czo#pr@1f{ulG;eB|^bg9l+AEUk> zFE(Kt#oYxhVW54eDYXavqZw(syCYtQX_e0e3X!C|ki{ab5P*6Lm1J-_xIOegWh0l* zB@qH$KvNd58llq3`>WdkSb2aYDgYD$`@Y5VA>r>mFn|~vy-r$z4kM6o0D%y$c}DtM zz7NmqaNgAHlt5auRC_mmIyVMj`v}74Yzd&6ZL)j12UvFR zG+Jt6Ok^_o0JmNW@^C_St8>iPRB1l{S4~1s#t@~W4@{d7P)|vbL^isGrc*GG>F@CkVpy%Z>eelPc*k?c;aT#b*wf37fr5)=Dw(U)cz?DQw3<7NIkFT z0ps{{Pk>VC?zq1Ixb}@Au=p(0T_0g%`g?d-s3epC{T=S*T()V)@QB}kLkPqL8Wl8j zyeLw2lqr$%cohyC1@~#ybxGl~%KHmOo?3on!l-}nD&RD|ubs8l>O-_C%l|>-IY=Ag z)F+Ip;0XBr=YPQyvj991lrix4j@Hj!Ax|L6edPnod!(iDMBj>oG|>M;TT9+#_7azh zjhd4aa0LJROaWC(T~Z`qFAVJ3)Sr!j_Nr44&>&l;{L|Rtc9AOpFbx4kC)s~tNyB~j zLt=#MWvH2z=GUW=IoMTOf1eA`pYpJb0t!pt74_G<`uqK;H(=h?!rinJFxT$B6W@(<>(}i!WM9R8T7zp@Sn-o^ zNss@{t72b&tgO(S-u&q@|^sT#oVj9qD}R@kMhN7yk-}QQVt7?TYt$jsZGH>(55*ldXF#m!!o0sLQu6EHF>v z@WlQFYw{RE@Y&R^)BdPJrU)NcfuE-Mib?!VO2#n)ZEF*i5!S@05API*7bbr<5+TfdOEGIUl+TTsEoXRb_YWX8f*Yy zbbaLcQeVtksshX$1DrM@{$9P`r~dS-S59nARjW_wP&e?{L?h#rRg{cOjONueMjTxd zad9)HCDCV^d3ef)ho`{JP4*%|6M(@vFf@WrxBdvIzV}W66NXqyna!ZX*a4VE5l&XonMKtu710a zKL*0rxT(9QW(^)qJVJUJXS)B+zS%yig^No=-FI@H+uI3JQqQN96ue6Y_X2FU`4)@0 zNpFGsXjGwoqMOZwaXHI&b$|$U;`x$KJe=fq$i~7hNatc_?~5xh-AsLMrjii+rQT$Q z#y?rXS2PhCx*NnDfzV*HVh`XeGUhavOq1jA1A0k1T9#$E9#~j11d%W1&yfFh{RQRH z?;w=kZgKGC`6&;M!<+RF=bp{GK@5t;N}Y~?!;k3jt<1YEP6FF)B|dazcU0`PsE+t7&y{ zv01|I7ymT)55Tzt=_-JKz=I^j+`=OK@+zHh`*jsY(R*Ll*GEJkJB8QR)th;BR@K$j ztrprn?35$!wt;>)9`;KAy>CkUTRF?=(e%kbS~e$-s&`P#ms`QHX#@mly~qNc0u>lq zdtyTH#J|oSe={#KzMfHWaQMxG_wN&@H5>L{fAk_3ZCKumey_UUl zQ=0Wae;q5i8A&MSP5rpHy-v*}OPNv4z?lE{6_|;b-;lDf4>?d^QYY~0qNDyWc4$;` zqvu^VZEOX`@qxr5arW2Q41KjC()=+f?~lU&ZWtxZ;^oM%GL-7cngSj^&(8*Ss#FRz zynv3hr93?dMBEA(zwiurUwGXz?$6w&rqtKFI{*DGC4QzYWP1IsFC!xZa3VRDTAz5`djYj1Kf%ba3q~TE zEkWfeNBs5b@K_SBVJMq~KNPfSU$h*N8p+9pPp%Ds#>zRY zF0m=_&NLQaY=jTe*XU{_CFL-sv_}F#@2Jdbso;x9dghP#Di=DB|L#Xx1*FTc4 zl4M=X6nOYq=IqpzpSEgZaH&egQoS*vF~ z10S!|$`ASF$S6HY`)YVHF&v!E0HGk+n(8k`O#UIeqiG%1s;Y^S`IALq%NEqs^U@r4 zkl-{%t6!UqXYiEK9?dP}{2H2Smz)?JEN(Z}8LvAm6NVZr+?@z!FTWYftOSCprJ))Q zWN+-*Sq8HS5!fFiUeZ|0@(4iEyJpKZo6K1y=gQUb@y^Rdjko-57Rr>UKKmwiMZ&WI z@3E<=X)H|!;h92Q>d}-2-|47-0*DeBgs&en5xJ8qEkjNg;#OXKIyG$j{C9DJ{;tW(T&@q+%s`L; zwY~}cy8|7c)O2-MXH4+kdrDGB!F2cgF_YXEm zh=|At|HL~9@a1*N%+wUKSB0$jsr{BfG|+q%{N=cA0AR+0Sj3?oo~$aF7*@awDF5_P zF(wwo?`D)&sjH~?nIHKR0O79^6;GGU1s!t%E?6{o8ahG7O|8#g%-N3o8=RB66JnouxiLarldW5pN&p z;Z$HBh0Of+n_lNq{RIe>>=n8%yPJQ)mVC0EEEaVgi2S2u&o=*Nu%4LB&PbgP8E}Tk zM0&!lkv9b4GrPi?FFoMYPPU+9jJ{36quy-DCl1s7y}kJ+O1xc`tLx*izQ~4vKx}NR zyH8q|Lu33>PQXF}hOTt#%5%GjiXDTmFR4qkr6dG3fn6pjl|YffgIjN{4J@qby!v`J z`$gxi%&d#Q67AcxtKo!x6>D;Qw2;K4$N{3Nw}jz{GG=)k{m zvPHFtwrOQmWnp6xxF+v;#i``3sclun{wT47v40X1-3oTo;CkXnO6L0}DIqZcXwZNZ zD@?`S*)I2pn4mXW_M1L~|Hl4C4UOPv^Ef>AwWLn#>+KcwPxyhp0DJ2h&ZQ75;N{hC z0eJ8gebgY={fQ8I92A7Ps(Z3hhnQ@;O`@wi?Pzc7Kar;btdQtmDchWiNOKDd2Ykz) zc8!tkZIgqoy&4@QhV_3>+MtSW)Q>E5PP(jkh%0Ic%6l@=s``7ddO>Iuy9`-)qn-zY zr-j@#Q){DKGfT(J0>K3S-A9XorwHsk8$25-UnK5Nn;9l>Xl)XpwvS?WlFqUt1EI7-%0XfQyAr@^LE(_=GdL56cNrdEx8NJH|~75}C< z4|`?(?H#Jn^H0#sg#H!hy&bCW544SWyblppu7$O=n1xtp%Yoo-*{$63(qny9bJ&i?sR-IJ*i@>8^Wn5Fy9!8ImwRGB_(n zhV?n0g6p#0MfMUHzw7vijgC!)myW_8^_a&Cm?QrL2bI7;;I#|HU!ZpRkN=&&ba_D( zL0P{?Ft#>waI`npw|f1`#=snbk(G^zfe84Dh=&J({)@5oS4UGKb`DmefBqrRi<((F z8ru`mi(2YC8Veg6+87xl@bMx1>ng4bJu0gBw zM$Q?`7X1#Ry3H*MVJnBc_!(-YC-bFa19_ADHjytpT?q6TAaFeR+AU(#B+8oW@Q~Cb zqxIfqrI83Jj#Dx4HM(tFng>&zg5XA=Kcc|BSj@Pu$*M}jz=xxP*Re+UxL4i{)YMRR z`Q>$1E@{g@Ocv4(n|e8yqf_KVlpO=2kw820Dby zp;w-f7*w>k9$6Jx1gt1pVe>^K#?H4}1$?+*MzzTFuxx6{ZC1ArS4G|>OdUDr)#aik z6BMP8KC{I|wPp)J?Ms*|AM3&2tgvm5R#NvpN+k26cdcAtkBZ62R?>aqh$PU*+8NN_ zYXsI_-wu{(+-3yM=p%egULeISw%lQL`JVje9hHn+=hQNUx>xVrkhi69*{@=yP5rH8 z6^P%9fopE7&7Z8cW=t_K`0ae#LZ=a`**$2`OblFZmF8(a=>}vv1^&+8uVtWNx5~Y2 zD#Gr2TPug$GGV94cRhJK&U{subePrJd=$9SaJL!KA(QN3!v!xg@W)8aCP0E?MV-~G zMuKB}PQ=BiZgrpK5a64q&Cm8?^|lXecYZmf(IezIyk4k76tk1d{MuIYrsZX4oVelP z5G^2v1G-y%ubFy>qERhG1$RLUZy9TfH4WxGfz|KWk}HBc07j5;T_7ipS8IFm(danj zQWXjIZOl@}LLWY?1e(B5kr+pym=4+SAP3fI=X)W@MUn0w<&g;yWC49M(=HW{TCBX6 zo8WR~`EB_~Lx|O{4b}&ndBY*N_VMxU=Ur|ER_|bPySMe`;7Rf?cMbyWw1pUk&j^8-i)gqhdE95Uc*$SP|IXSkoFdc9ImX54h&g;vG19nhc*HpZ! zKuRYwHpL6NUbhMc`>%Z}uX8mw)+p)8m|JYNH>wu@VTZ9X{re8%WMukZ@33W6b%#YZ zRParufG(b`LMMl7_SF7#xP>g2HH97P)Nr0>mV{cT614FLfT_?#M3fSvC?b<~>53ZB z1G!{#(`6tsK_Kr47Itxi<@I}pCBqE%kNwgeRG7w)ktLdan5%lj#@k3q@KZM=g)>El z{-s!vz5OIJ#i*ZMeFu3Z#v`N$6lipE5LuJE$vlc08We;cVKPTW${3CsiJKiPT!Y@y zQCKo4T|B}A4;YY#6J0z=m^q^wta3 zYZ&}IefwwmX$q-vAj+8XGl3~Jv_Ue_+ufp~H|{-5jv8%&`F>xMgu~D!$ZImt((-r+ zuf?=D<{nE*XA~fKh;4JN-Ij|alPjG1KQJoveYLGIAemyRs%L;lnMY@m$>FfC=Xrs5 zLB=7Ee(Tcbo3ds5F*uL^DiQp9AI*>txa!=hi8q@q1wfw^@nRUL+hRL3l2i z6dGHRL#-pb~z}V}UehkoDqQbrKH<>!|{-8(n9iqYHsHdnMa(&vD&~CK0O) z9SwCan6&pqO2oXd7>u7b3R)^y_v*n_ptA&)YKZqMhP<$K}u z=jXI)dYXI0J~opLL)}q#Wcm_DQ#VQT)cH}!n@Tc)BHu;BZAnmE9FZL^mzg1p6EEP` z5Mo4r!(~KIys`1*VDuWp_-xpj6ge)^LM*-*KE}Wy-(Yn@zq}lZbdGF2)5-lyS!8w3 z+9;!41fcRI2ayo`if?K*HXoZr*I`MWBO>wcB#9u^#i+fiJ^@^Wk*`#6ZQ>Jc5f(u3 z`9@?ilYOCEZToS&S0SHZ0x7UEOce*V^|{z@ik)^x^@;r+`V|@rgK?zJKJ&FIZv43m zEB&xf)^)oP-9J3#KS5+<780qA9ZD2O(nG)V#I=TwQWi|=VesDiv_vSM5vZparOt1)IyX%^#a^3jno-&(q372}w>VzJg_Z%wK z0b^CHh_q6E!=7EN7#&Y_O|?9cj-tj2i;qm~!&D2)2R9n{n+M9k?ID3K8#`Wl_Nn+l zg*2ae(TO#!)Ee z)$DQ|o&&-20DtLUv&W{(DJlf%R-n%#q$>!cYRb@ABr?p=nXfJerGl7~M=K5uiK(5v zy*I|BE>Dp<)>XS@FHvNG;&apN`f2Ce7}B~5u?Y-X7~Br%3c5>zNB2vt`sf4&nK7T8 zOxT(-%OI+>Ivm3ide@-dN6$9W}Qpj4`-F|+RRnV8d z4%}@@H}*J`c8Ft;nY@bIT8M9zUL2RpxZbxbA|fPT0ik1NkQRh3M*Q0ZQ{ikhVAYZ={i?>AjE|<0vg-F2e`55Q)%2vd1QdyH zFL#^nw#l0K&)BLtZjK4Njfu}V)nroMEvCN9nz$z?beP%oX^8zfRO5r{9ifiZuH!AcMLTs=j@ilU(nrv|&e-WH2}1We+W3jy%YLL^t3KE-5Ox zGY>ED?zU@zWTXc5E3^A$&i*{$!K{c=5E9H>I{3jaib9(MSR_{O>^IdK*w|TLy4n`G zQ7fQEhK+{m2!6y4(j>{Zl4D=*N{HU`w2$jiHT{I=yM4Kn8XJ*i9ts<40*}fIlE}cfpz3EM4_?U~3Dhgu z)=k&w@J*J~zLuc%+CJMIxVK2KpRnF=bsR?)zagZ{d>V0H@zzCQZ!Tq~Jf2;ej^BuG zxr0KyV_}Yh7KE&8Ca`dD-R=dCFgh*M{^<;^8S>5aiNW!^`CKSWZ{N8l+trhPL;iLT z)gRg;N;{w2lS+*LARChaf+sl7%2+zeql9kyOA79axD!(!GV_a<~ z4RNS6mQq_qrNS2KaNkY6R&;_YdS<+-`N#tkx+a1{{Ev$88AWTx2&MYD6n)I>y6nKs zw@W^3Z?@+Qu8fhGv%7w54UGp)$B-^|L@(}?mnIsf$ic$2QTpng&7K#o!z}3k5NX-} zQ?bI#`M*9&ji^XDOfjIg-lztp^7tvYl)-f|#3eWfd=5;or6E`nmgWgRo_5ZJ{d%KZ>(Ti0=@Qbt2)p74P z^Ewp|p0eSzXUn6iifTJZQyKOXoT2Y}czmL3GbpBf0maX+OYv`%?U`7E#f^~*cI|{$ ze*aE%55cQq@UVF3aPMJlN~){s>aq_a5B;+h6Js}VsK3A$>YOCeE&{EQWI@Vp42f+Y zhEN>x1dUlpv^3L-r*Cijcw#Q9lZ|>fLcXKke(h$ZBek}5(hMZO>B15meEi5*_$7)e zL1BYFmc>O-ldev$T;~`xa#*0zj6imb!k+DK-o&qEw#ai~8fj89-Q^&{tPRZ{dd?N1 zUw*l1T2;`w#u9={M-qU~uF*;B_se?eqxi+|f*pLUbH1RFZWwKqIS19)M08?k39`jZ zcn*3p-5%asj*;G23fE*deCy9gq2veW1%Li9emHmQN6d0>jJho?*5H3fdF&ZBC8>KOh(`PzCrOA6>D}n3huEUGB#?c23I3E~ zdGPk_Y)L&=JtRj!1y5k#ewp=PrV2A(w6Y2Hs`=w~oDpd@a2UMQM0~8bMCXtJ{Yy6hDu-vmxZ;P)q9$ zE)UuDE1gKkdT|aMZJ2+coc3|B&x-&RmZwy2^R+_;> zpFsQKN_~99cND7n)oqhSj2Ak#?1_=};#P=0W*bNv6=Gd38EsI9xINDbls+Wd2DkkGZL z!JqTv#0gLXqpT;3zD0>C-=E;RgVevWXJ^N+{QwV-hVe)4;-_{%<6LrCR_@L_9H~<2 z6DbOoPZNb@Y32PG)mz$U50m**?ET36BSXN`?W(dl0pG?=`V(e&-Oo+&bIk5{NPK$) z9JvvkYwz8M^jRvO;d^n6h458D5j%2bQ7LHzkn=gIxqo03{23b?6W!NHr0ryou(RCq&y(R_xDAAEyMrHewEcWn9NN8Dy5bcuLrwBKd0d2|GyvG!pc@9lV?KNRtyM=Ix8cV-ho0;pCM3TsKF zIjqh+=K~8i0bN3Wmg(7A8OSovK;%o%TkaogLMJ63IOp#Wz;LYM3I@%M-yj(#-iS&T zlD85VVEsnVilfj=$O_dhN1efFucF|ngDcITL@MFgnr4Xq0G}c&@Mj9eDdR*yVn0zS z;vw)fU*~h_=Uc7yz6UD7Xs+ruc&&ZqKb>=W&iGGnZ*jXi zw2F7}YK{zW{74MSKWVLbk^LA=1=Hi&>pnA3{S2@fxI5i7Y0@&%)=i9IZ&e()E=Z!U z)?M^q8F>HOtudVr`|i>07p^ti@5jC);s)Hxz>A|+TFdIok^5_rn};T+lsn1*C1P6>kZ4fJ=88837eVN$*M{S|>&DNNRUe>@|(a{QlUWSN~ zf#J2fuy=4I;$UU@Z}^Uhf#Y8(@&8?W9BTmJf+#w8w{ov<3nnSUy8jnekvDe#=0dF=5hoL}i1P3}nEuIXWK^=cpKVag6 z8*ZXi%#R>liVmTGukxYA3`^?*&F8jk9bH*SbXmkiu4M$sdhco)OCT>bpqE2d#09$; zOm6jA{BffhKXh`u9Tg3RFo^f_`6J)O$ALwX(}Oo4)sK(wAD({9uz?=V;ddnJ$H1(B z|EaTYqZ$Jgb-stnE8#R8kj+XV(GdTGlp?H~+%91vW!_F~SXy*R@E|sxjQDV%%hq{s zJK8$n=KvH05`3OzcB}xEaDop+9@gh-ahil5zmT{i2;WD>3!38)3wP_0N_lPfz|q@7 zM4Pn3i~Wdb*^>%-8ww3QK`$Ov2hA@|RhNXQwL#VCM`W+kN%z5kNGqN}0EbDi8ebUO zJD|JYl+#RNv_~WS&^sZI0!jz@&3Ce31`4MP-rQ=b?bL}twD`*Xz|5~x>sb{_9sH9Q zyXhbu6pEICykE~OkCMus-=#3_rPl*ez!k8DcwZ=L%+EKSS%1l2l(;Y_M;sj3I07b! zjqG_H#xtp7_s2rMCYS0Qb+1qs-}9mBQksYmae9;Zl_f{>Jc&60wmoI3m^d0R(I~u$y#*{% z5dECbp02W)lEM+s@0r}X59x@tEv`_=^SQHH_iIu0%2-XPLO{+WLGIptQltY#Z!Wk& zC@<^b3O629LO(TgTPZ+%uS_NE?n>ofrdZJ3Y*B_1zD}iH9V!iPxan?bfIhM4k=b{gjO@wU<{JpaW)U0BKs%Z9#Nol2G81D58S;+e zbM^P@Mn5eyTz_bE{+Xu$vbho=5W_K&QdG_7pR6Nc|77NJ!z-0E-1j8=zI%1&Wxc}N;2c*8%9 zX0r_)KnBItMWTFP87SHzdl=`Otcp_3fw}ssUa-CcuaB(}VHgsFr)SI=WZRE`bNN*@ z;0sRxHIdd^4|)XID>XE1(M7_5`P}YqSS6;iYr|F_RGjHt?cs+X0X)tS?X-{lzu5A? z4b!c88PpXRcUZn&VvqTHUXOQEUS#M$A6OIa^!aFHNMPE=B)yf@v=RDAv;8Vzwj`z- zqTH54h>}S}`Vb$*jYVs1vsqy@4krR2mLoGM@5nq_e*1G%R87t&2-M1d3avMZJ$nEA z=FR4c9sX@6lWafcdXt@|#&B{^T$%UJ#TM7L1-4asipzEQNzXlD!{=3@hK#V4zN6`l z7{?WR_wVoXRBl#%kFV&g+FSHidO7GCYJ0Be%2A@%-7$HPcDl$F_?e;`oc4laobbCh z^UZ2z`^XL-R5D&FOI}n}W;DO9v>lw^%kik`kk@;nwvsiavoxS`6IrZ0QhC5x$iz*4 zvY0*Ri#!>11h;s&Q=FVmFDEx|GrOZ%>QK&mAo-453+ptOt%on_2StWw_pKF>D}6vj zwwi6vzJp&IKTzt(cA~XCde5!k6J04&o1WQE%6$CHl;2mDJ4Ar2ZPT0k``v&TA*~*> zl-^MN$oC=Z+#6Art2PqjWs!vI1S39P&Y%=$R8~reiP@rNcYCGQmiKBWuGvV`S%))p z{pvb_S_}C0mdA9%J&K=f>t`CEKXqrM2!4VT<(o!;g9uZ!@UA+u_5LXq^o}w#Y8sh% zKRDxyjabj3#ofm-5G=gKYF1ehssY z!zE2S3PW2M!C7zf>J2(%7UgLVL!0Zct!5V8x*l@^(KbQwdO^C^EDZho!GsYwWBhyL zkdy6yU03v|Xv!`!V1jp5)lzCXeQ|UR`jQLGv|#b@$^`O>t=!?usb}q}e`4OB>`Dok z;lgW}xfexxS{Cj;jP4p50)0aQ>oszzF!J6N92D3ua%8x0ECoSw5Hv6qY%(A#w>lBb zTV14*w|gjK&vU9LKK#!mQCSvwmmr{aWimp_Wp=D0v7<;}jTTAE#3b*IH|E#`4oQ(^?U4Wo(G){t!k1GBKrY zy|~nQ2a*o(9dc*QE5KBk>3@pp(p zoTW>X!a*y_gK&{)O|%X}-g4}EBv^Ow4&_dxb*Y)goVn#4)5Ldw;tx(+CCM}?Y$Me_ z)g^gyOC7p6nZnAxyo;10k;qIjOJGyY-=uW8)VtNjhVU`m3|lXc^#?4hb zBYcK>#)8!1s5=JI2TmQ6eP4%@k+zLa4TmDt9bfd#4QZ#@!E`~B6gA|qc0?I$9sV6tO`VIRM2WyaARzMU_T zO7f)@3&$BJ^db+A#q|wI76!8r`|hJU^}Xv(rsRTX!GgZf?yjGjw`3En^}Ry%+vU;w za$JIw4Q8VSzO+!-AvLtDe}u<)-xVvtjbaKJKSC0@CS!NZU3lEwSl_ur@F%`*vWE)Z z@Z);mWv`59%9bdUsnQN8k@;!klyO4^sv??90=>=S_qXemctnj~yV#n9ywbO!xoSDf zFVe zShd4{T;6NQeVo8Qni0sT4(R5`M>6sM51WmX_1`xe8zcMwezPeLST8c5wmi_zL0*kE~nqh?oa~7MG?E7qc+ve=~rnRM1F3Tb=1i$i| z4*HqCc*f&{F$)J*J~V0s4mM^Og+Mlvg8;Mdk8wRm7;s0Xv?nKfzVvfgYs)29hSrnQ zR-UjoHU`9WaS)?`zkshe1D$pex%^rlSXc=He!^QXuZrRWe6F|x?yN(@N20sdqy~`` zN~I1H9{0q&w6C^tRLF;9PBL>$y?Q@!#yldsn#f$A9xWay&}}*5kVrpXt;;oD;~fzH zOx`^v3sC(d(4}fRPn)ZcWSmA2(OdpC?Rs77{fx4_w3T-!FXr`a4>Z;JRTgS6gGu0L zVo2&lR*1n!^VTrNmG1HKPg?iFs*B45Hp8yU^T=Q1MYtJV&Tb~5nB@!Wp|on#DPB?v zxb<}6L@X*cvKZ@iSPU=h(!-X6_oNg|$qro)+yfp)-a5iEVcC77@DcSbmwe$1w2Yfp zi(%-GN>I3@L7yxs6(f^UAR*@op)iyvN%r5J`o1asdGq%$$D`JW!LC77nTd@jzh7S+ zs|c%%LNJy`=IXs}W`VKJ@I)gWza@g%$tmMtbGJ}#&@7kCsv~kHvx9UA%A-N$ zVGr!_SyC^G$JZ;i@f8u&{AlM&krSGT3;e~|_%qy679RE+E4TM_0^+U;^Gh0vIsyKu zkQo$6T@>``!?iDF%xRPXWH-w$qBujXIu0)9B3$Nh`>ERItOD#Hq^Kp7QuGjO9K6BC= zKXBx67=c*CCIUH<5k*lvoT1&?Lxm_RS=w&gYR!NH@PE6d#BgxLY-m0}5yuv>)eYqr5Xkt>!qc`X^f+bR21) zs(f>L{AvV$M2Ezup<+1eb$p+gA)VDbLA)hoA(9C8u)BcP%Yg|~lA-m0=}!5L@DKbn zq?`U1eq!UOgDOp?L^}8jKOGZ~P!iqj2Xc*J%PHKE*KKz2c_hz`n}hgN@6Y&XZNzmoZdkWovU(M`Tu;`;Fwe?n*_zPOU9t913a zf%3VL@6uD^+$~!jRx$r9&UCU?;}Z3A4I&U6sA6>B{N)o$L4sI8#SrF$on>hCxV^HG zW@%3^4^u@%HS+g)q-3$;eJy5D&=hJFp3^jcx@8{E0{mQnq$O99-$`In$x?jbhro4K z4(WKzfAA;Y%7MatF3?DCv5nM#G}t{AT|f5Bz~hRBT(WqJrEPiX6Sm-I@{7lk>GYKr z@wRvTvub=unsDU_SV_CQrY~^xa1~O|uoya`3G4+0TjzFMr4?(l9s&Fbir)$QCcez7 z_V<;wI)Thw@ zWg6eCxr7&9uy4AW@>m9-3ZmF@JLS6A-ukecuKY<%Tq{a&;jA~9l7lsH@bC5%~sbmp4RV9SE zG_&L6%BE5TymC;la8HN^NgCP!**s!S`wHVX{3;~+5D|W1j8TkXgF&xQ3W=DtP{G9k zYX)Y1_E0J|Pjwb!#oK6I%Pu?hFw=n3r#U^1?JINVIk7xyJ zzqsLMN1p}-3T?2ptv%Y9<0p9gA(z%3Fb0F+ThBkex686rSBt5Dy3}+2sTHF&_KEay*a(|*F%`^x zNVZ57WBue~j8V>fc|2 zo-TF<>DH=4fu$Ilg+Bwg1b2?3FAB@;3fD(Ta#2IjJIKe_uTB;Ds#U+n0nAXoF0ec|CD}x3 zn^--b28p~2lsvD0_FP5DMB=CDbSrW#VWeIDek5;u6+1Vf{o2%7P2bF)0z)784nF>vxYTd z0Kwf|g1fszf=h6MOMqaT5ZocSI~#Wi?rwJ{&vVXuzPFyL@6@e(H~+9!t?AV=)6@Oy znOXn68_-;GSms9aztuWRU|`C?mH8S)CXGo85yEYK#Eg+Q3dL;g`9^M2GHvk$ZPEhDHUsPLttsa2_p z-fYrSat==xNCa--`b?wNR~BfWA>D??eFzJW*qB6q_+AliY`#42q1_VMQ_oVU6wMPp zca}NHikl}AmIaBwNhU;&HcTy(goTZ~ZksMva)UzcbHyYTlbE$Tl8>7u&Enr0^zq!mekAC_q(od@nY;ljdYL~XP&?2)a5)KeFrwb7`Mt}q)eY!*1 z6k6^0xyy8|tnl9Mr*Jx2;O#a&Wr)QiE$TVaW+?nMo5xZs`Q(qBA33H$kZ#3|SsBw( zDKKd|qXEj<>S9zx-j5WY&ai$8O-xS+L?26*A5XyHdEl#}WP7u{H&Ad&1=>QBoE-3c zvga-i8};2xpQt0nq0DlQy&sR|5uO3^uW+)hnQXnN4G~|wkoQW=`0X5-2!VS{dnWC6Ho+>eM1F=R!|wMhdEF95V71%H!?#pnn>-|A5c1 zbAjtge}4b>%Fw8ej^mQ#?`5ajd7|RvlRl?~bUqT1vCT3^^A6~o;Bm`dkCyP`J$>n` zza{DdMd`p->RNBMCf%`-v4FLaBa;vo^mpODUvG-fiqG1ENkSSw%sWM0nA2Gh`)FMo%N5b0QaJ@oYsA2h~$ zmgG*#5a#L#_RvxbtMt>hSJ4UhcH&?m2jquMYS$i^Mp^7y+FwYU_PwyZ$#^}+9wCtm z+@cw#^md%+NN87YnDsieMlZ^AKvlfO`mDz@A4JwiHY>h$f3X=sqC(`-PKUpG7e7rU zw->F012EW=hM_?ghS#}$&p)B=YlH-0uX()_ccmGiJoY_Av`nC&nxYnpj_BujMj0(@ z-@0^sl3D6y>Z&%pfJi>Wdq_fRelJt(;yKMW@0=pm=wW9)XJOZ3H4^WLT>xhV~j^St#*eaUOZTuiof@r2~y%NlLuRA0m^2#tfgVwLm z@fYN6cu1KA($8x0Jq%DVf-B*ZyxY=8`k!n2<=+w-ek$ATcfTIt$xA#Y1z?xoi&xVq z?}bEqs@OKE^VThxQ}x+uwFTMDu6xMYU$wJVC|7PnmktXF;+7el{JK7=u&m+09({{S zgQZ?!KP1S7py%X=i@t#nQO6`U(UJ4@GG2`o^F9z01BcK$ZBax-zV2&CeFA3GXHA!o zOYUV)xVEk~j{GkRalZ2|y7r#kZFA`n+9&~xLy$xGLF_}j`(COiK`+JiaQc^;E{mVX zHYDnL^e0)U!(3;hUdK9l?%^M|(1br-a*Zk{RoSC;s7F7ziu+jU@_i zp>`J2+rdGy`Z3^^=39j9mDEe7SH=K;%NY(S#Jl;O?bG4&dxeM`erUJ0v#DR&JHDGkG-FKS8tG%KHRSFPs8`Fx6HdI z2Pm3ej&jZ{9sRPy#>EeN&6M8!I38AWeoYiG`OU+N$esjs$`9kA9koh?_|raBWe|J` zK?o<4J{1;VKUFH2xBl(hPTLC&E9g1p#|OrXr9|ku&*;}yiK5v-4@1riryAa5vg(l- zM&z>j2i ztMJ4vb&&FA9lc5X4CQp>f{R2%*teql3uV_9j4qjd*Z53_V#QnaCJi#I2dfd40o`S> zE`4157cWWJ$VZEuIK+85+yy%69)gXfVT90N($b{Ma;9G+KU_$tF5I?1FxwuWlz6w( zeQ*L6VSTHp((2UZ^*suUb{v!qM>O*kI3~^Lhc-Cov!`{Pj%oDudWM@PLM%(@{cdTv z%2kKo>T%d^l5Sz#|7d5I2GW=jd$P(t3QyZ^Yv1Abc5P}rX3sP`X{9wuURCl{mZVk#U2(>%j(C6rC8-L-md)tPEmG)zsCcosx1U-D^1tsCNs%)jj5Vy3Oh zHZ3_Pj!X$YZUP6pW6w&w9(5i)<@X}(=w4nS@fj+`{$U<@`wwgGcsc)j=y6n21`Oa} zf!7bUZpC~ws4^uahpy$s2$!W#;3Y#LSD21q`f3ecKjeMGRLzkzF(K}D-hM?G-0QBO=T0F7XTo}WWC31~wVM>aagbzZf)~ZN`0;nJ`4Sv+t?~J^*t%~l z6ezQN^S_F%@7jJ*U$o`J_H%gs^tnrpGC_R-GGUaGton?Apg3)U@T(uZ{5Rpwets1m za{7oMjgGq&wb+BhflfqU+C9Xs4ZBao$vv~u~$%PfOT?VW7kH1%nbGWfx(hcu4JM{&t+ zcf$Eu)09;osbhb`H=q83Z|={9ZIr1bZ*Y5N4R=!8H7z~s0+*MqYm&Y$$t<6Ityz=N z>Q3_LPpaL~BaT-XuB?{nmU_E(s{R<)Zz+Oy_ZbOEGR1Z5VbrdO`|H;;6k%VuPlzN= z`<_dS=@2QksOw{OZALJ+9_S90rAI$|CufYM(?2AKeVjEb zc-c3joSl?xrveS@?Y~JRRuG?*B}qJ4YyKugE6X^o*W-tvEdthHXZ`f zWG=XU2_y`#3GpMUS5#&`q+|6Bc|kQqSq^=gr4o#(0E$&_Us&@W0xP)u!dSr|O<|A9 zh=xCppX^n(04Sd~pWi9Ynn=9(tku> zNz|G#nhTFR3iodt1NB#1FHZRd4D4xYc6e#S7LG=(jz!wQON46ph^ufMlOFgjZ0Csr z+`__lc+F+64K{YzGql&1vSyZRx(B`9MvWyeE0%9Ta}7yE(4jAX@Z5yJD=Ijd1o5fN znd2rId446uP)@n_2LtuBm-&Dm~Nu;qyh4=vfEB{w;wYA>2REflu zhg0z=kM$yyRw8g|fP}ETThpIgA8uSdoV~m0CZI1R*arIYoMbVK z>3b!t1|-ig%@aNhNXQphd}#Tlb@RMj(AxYcw+sEgOD+o1Rd4I?+&`vf?;5c+m&%b*Sup3u4{o*gx$FDT?)O^6qc-}Y;;&!-l?xpGgY`Z;TV0kxm*FE zCbFVeNWq3z?g!tnVfVgC$*W#xZCEBJU1$~(yG56-PF1boBAv5Y@EM_xk&R>tmGQ>1 zWtm(t+vO}txK5PEyeiEI8+^7?QCPe4jshOc?as1AQLFsQ_P(eRR+QEHAXqVcyF@L_ z>mQO>5k27{z!w z@8NE~Ch1(j*<2IYa#zn9^!XRRqr%eSMgExq4RmuP@4Hy~PyO&8;6m=V|2@$EuYUNyOH`r%E>Yn~C1*aI4!?hcMT=rbD~h_QERMo= zdX5~~MFcKU{rsy$<@}!|s#@3)N!<95oBD{5JDG{Gt~1Z44$U^G7cY%`(KR}3+<Nwa+a=PhrmLI`NQqu!AMB3yis?WZa!$|u{Ze27Hz zFP=5&hIKH=9a7zf_{gSoTiZ^YEIH2nA6<23wB8FfKp@;I&ric)<_&;C#i)L!6Qg{B z|EfO=O=p^vw!?4H6f>x&*9aK}1d5~>rJpx{7s@J#^RRH(I$IRyP$}h(D{7;P2BJQg zE(YZO_!c#$-}|PrdbBJ%<6~z$YUF}p@{12bteKFd__$XCU+|)61qE=IYC`(^qor}0 z0yhxkC1moMoVf^ZSy8(D#i4*xCNlYqE+dAz)B+=CTr2J!a_k=0)|qQtM0WISvtjG? zGZG2U9M(0b47KK&f529_@Mw7}-DGX4uw9hR-W9k`wfwI-Rov~Dd(nDNaGh%Y_~U67 zxK8DqIrn-u_AKxY4(?sD)mFhBUsfF6 zD}xPbsnsRKvPa{`YYR%Uhz~eo_%X_l@d`o7zH#yo{g?9}a4sJ9|9+kH%Kz*wkdw;k zDkG^ULF!i4)eRH>lDdqCVpBjBHZN;mQuInP=%PwXPm@2Ayn$9(+mhhf;aG$Xiy72) z53%~WM`m+7cG|d;_kChf5JD9EP9CSRpHtIyNgH(m*%LG!ZC*>O56~bj((!bN+6s=o zyU#YGMB>Tv%a!gLGD_SS9R$@orVT8lKG6a!+Mr@+6JVz?bbII46Ms2}p1R7&x1exC zr}WquU_n)Ayps91+qF|TU^D#L^?QK(r(QfVBFY$gyj_-uENLej($X3lo&rFZw8?uv zhZu@?Fl41-7&V`l;rwm&#bVwGW!}p`_Dh1Ir_|qNW53(2|5h?PyskRWZ*@w^kUtr~ zRE~>G#Imi?sZG91>Co|uB7n^#4MyS9fnqqHws#M)f9pmKp%>~vuLMF#{2R~nZ);?r zH)J14JvUE-xlAH1I6EJj=6dNw&7y;JgzSTX#UAX0Uw**M$MGB`$>X})&RmDFGwL%R z=xC3WG{3b%bpHf`e6al{g6WyuB3_!P_< zt#)veiO=$-n%TBk2tzz`53xVdvlUfX$Jy4hp_n)!*Ic*P%(VEq$|JoaS z)KDyXa<7s@a_XfVDIF|K@^uxoQauKm^}=*#Au)6S-tW|JhTg2Uht~XJbe5brgBgfZt+=y9($Q5MeETEcnzYyY0QnuF7!%H zoML@4yMDmGH_EHUJLi7z^sp=)H3-BzPmO~ZtJ{)K41qVhS9wrP%8v20k z-FH!iymiZg?>e~@4v|DX(n5+8Z*a+aBNDlsKSU65z>aBgvQTuxAQEI}vbKDk{gKZ` zq^9s`a+ZgmD)Pd+^x(=d+$eXf1;2BB^$y7=xf@o6n%XMzS6%plP>14pZ6(2aAs zE_yC<4R+KEhcOtm0}DqP4=GX2DVsQr3$~zk$90b`qzeJhKow{i$C;6@u;*`ZWTT_S z7PksfH+uM}NK+iyV(js8G-Vkdvm)K`7@_#m<}BhUMCzs`&SAF(>YWQrHC?CC)g5gp z@-x|GZaXb*IJ~}bIZcw{PJdS=a^SqZU9#e5i7xc#wke4sWKJUq$SD$TV?e71bd_&SFH>uHI`Jd zTi4~HSfhi631lmQtja0^IyyJg)VD?+hP=W>%3xUPmOK7U6)AlcMxd3H;36}LXHPJ% zhy9Tct&x;|eNQ>%I7?g{*^Dz;dG=v_wiV@6NaIR%9RH);Tl@!XQ%HIgSSbxf*R<&+ z%NE5~HTLw9gBv)5u2JRb7vAnf83|KlMMMx}VD3*78JJQ&QfCsTp;V6tU$ z1e(ORxfV%oFJqoErora}D4n=h^jKohht~v3G)6A^y6?9%mHhD;CcJq%+31L}C<(fD zRo29JgC5D0!029+r$D7X5#LWM;eqM8YQmVbt|#w}U&B*vq*@DR^OA+ftA{I_?5ScT zr#J&rVtfrJ*&@r2lp(FPCL}-_>v&j1DWaxM-Z8(=g68iJEHDB;-sE1+?1(i>N1JQL zC}rk2wh!;W9j*xs3R**eg@P@JhlASAXVPP0fgP-=27heRl4P{MVQ9aAU@&Z-ZB4GlUH zz4=E-Xi4TuX6Ln%I;17aDj`jEsdaOzqU;tT20K%-HQ0Lu82fIl^{dN%Jgo-{?2eyy4Ub!BH=4x zqNS2jIBgqZ7rK@@1LedSEMM6dF)`Pn7^!adhp;Ljyd_ECvpfbp6AMFP5Wc0_h5z0D zC;0$8$S?1Nh}^{6f?IeM>NKp>gMi;uG^4rmYV6{%dOpT-F&dqkcH#3^iMl@8KMNMSP^ts-tl_pXZ0kptGtvuaJyrgrfO&`xTj?Q7t1z0sbHU?RAoN)Vp@t^mzz*%_lKZkUiZc= zb?0b7E*Bvel>0$N#(qs>X*I{-4h34}(^P*lPMOBKM%>s`s`IH$@Gg=Nc+`ntgvztW z3vQMN)aZ*F4Q<=cs@Xd`5mc#sPc&_)Ql~WUGnDqfF|0bcdh}f5BMYG$#rd9^-T_^m ztm>csky3@7?`30I58l5%l#WFQT_Km zDNc@mZ5{r{M`RjFbhpdIfPg&u{s2kmcvwuiFPa|YosTC?+NKrfVRQS zx4FEe`SB5_Qd0qZlGb&pZ+o-*X(_HD;D7({P{(p_wSp>pw?3ysf56DYO1eYr{4Vbm zx)+*4QeN)k&*Ft+{E-RHCvfbHx*Y|;{$_e`C|cVC6YCST3Qat&yjer($Bd9kmrwRi39Wh{9hw{h4Xq4q zEhMp<1zGT}4!zB4 zu4Vn31wMRksm?ulh+f0vlK`-^d~av_E3$x3CtE}2&sZjAQDab{?PH{kl3|{|$I*FEIhlnyzYc&n3BA$OYy{opR`T(z7 z_f9N6iPpVgXLa59Y~%mnI%WD4G5Ij%cBk(GVj0iLG`17urx7bWrR~4s-9*_)^*>C@ z@0>3|ftmK%@xPAW=mRXo?)i+2i(nC*uyeTD=2;3({)gHcU79aiT-uhkQGy7e%yJhZw>?W`q3w&wAe<-31YD^(A%f8%up( zQAYYzMMS-f_s3unBfzHWn}e2j*4aidx|iB)5B_IdEw6gRA9wm1@K2G137jPVCLwC( zF&fK?V2GJK=PjPcwc}-Ny%)6Zr-|J0AM8bCcTr!$WyyPW|Ucmlcf6%JDQyp1DN90@2*VrNON)E8R;1 zKNoq3Aq;RE1G!H_+YLrlh8(g?SqU2pw+j82awh&a<&__1&cYc#L2d$5zPCU>(hkmx z`i0=b72d}jftuH})6CBzJcOnlcj=#}_#gC-En^9X3znQr?R8!mdFE7_D?8~J?f%WF zVA8W+M^1Z*#8AmY+1z+@{#}PZlCF93@I*M^@7-e1gVMRW4 zM`fw3ZcxxP+_c2}$X0iAFCivz7$?01-MLzmd;XlW^~1LAxNoss zzdFCxPuueI4SBpgUF^wOz>yv3!O(jo^!AF|DE{tA;FRxHX^@gp_EAvZWh|SU#{+dg zj&QF9WBYt?H87X>$P=S&hxDrg9WnlLdioJaueD?NbiN*xRHJch65F8=PZ&sRB|y7t znz=V*&U14f#e$^q8KTZ{Jcq-pd&KY{fe4Me2U}uzI`NI{NOR*|vV&S2)8N z>!Hn%q?NyszmX%Iga>$!6EIFKrRA!S-U_pWWsdJ?>8GCZaRvAp|T>`fxxbl%PQOS z_7?Ze?cUU>o|+n?Bj4UohDTK~@mTJrUZx_?Dq$6M zHNj;gInIx(k!NV$7O3={HJyrw#ou%MXOqS_aC7+5Z(MZ;Czo3HfR;YCXq;yDNQACu3FMypM$rWt3HLmT`(oRq*yGpm z1j`}^S@gT^t-N20n~F70JS(e8i@wnvi~Ac?WOy`s$6$h;ZMRu>dQ|<&{Noom&#fuE zv8f~9Fr{>z-zyk69HvL}L=dL^2yAz4;NxMrW^DGInUNd3 zW%pN1azqBRe}eRUGn^thd3QHH*;3t5UgRj`rH+|o;AGmH-d{2|xYhS;-Jz>$q{i6r zIY1r!n%Ua!qKEQPt-|T`K7*X-5~KdZ`bchz(}Q0MeMJ1@to%L!2K#lwVb_dlHa>2Z z4N(LRp^eVKH`9U?z`oe)7OzT?z!S653;8y}w40{lTMSfd)ZEP7j=F%Br#3;gJ@z*_ z=&d+KzS4vaN4^?A8#tuF>=b%#$&)~BEzIG6E!G4gZYzDS1ox#i6tMjkX}Fe~xg~#E za&8lZ+K&|O>l$=*QRXkG%W2^oekyk3Y^8}&^IlK!SWxoqn3eoaelO%uOatu zY`Idj+IR+Y->JEnk}|Wgu-7!Lx?jKSL}{-wrXSwy9V&=8aJgGJnF0jA_Ce4T;zp-K zcg8-NyQYXAFjnoBr383Vu9=?+A50N%11BA^$!_PDhc{-!x0i}&mG=bV|JAlwD%uqs zW~PG&wEnB8!j49j|G{m|GT>6}{^B{|CI^>~$z^mz6?krVu0KA<4C)Wqn;U;zT^YAM z7+LQFc)_D30UFQO9gZkHY#6FicatojuDmIVqLK|rzUXs|4}h#aOap~2tcML7mRA~! z$B-P5z%xJln;^n8ClE8f`UwQEwDo}FlkM_+Hrw~aurj9Rdo4Fr*g~V*p%Tyzrz_{jlA`C$#&REhQv9+a+Zr!!-(UR z;`%QwK}W~{mK*VPzCGZz6&J<3(p@`oYZ;DiQ7;p=rEyh#v9*XpT-{n}Ef)Dy*5tTs z%RJ`?KH$ag-&0k5G+~-uWpP8jg~FOeY>|?xxjHx^LWLlsf#4xA;(-NUoS}g)z!v#? z&IgA=|9{;4^@C7^Sa8zRVQl426db+%356S5s$Cvdf?e7!+L!N|0IXsA9$R% z1V@?kB>GSj5cM!URA6(D($S>!JEA79k%EKl^432gFV-t#@L2RG5?Uo;jAcS1q;@nv zGB2aE)pdg|fsh6m$2Y4)t#6FK(E+hct56LIe+gB?^-#$ZMpZY!4)qQV4^5t;Cby*Y z|BiNFFtd)F4`w(Z9FW!>TCuVYsvEroc?pOR91sEs`~>c7&hCvJztc9porn2O?{PC< zXDjvd)yMn0z{JH$WNY>?Br_Ztjmff#KK&lUYgyWzYZnM|$9BhI$9d=K@lPzv2XH|8 zzR_1+K0GWZH#}StiWw}qZ>ydtsrf|HNIrq@X>isnn)9?^{QBbmcyqd!0tzs?g|XSV zrMYPPIb|gGT7K-B94^0qMb-o7;K!1mU9Av z*s4h>0v%_niIn2qox#t6I8S5~e0Po5KVjHolD+ryW)$H{pBHq6dpLi zLTbmSdu707WG%1KzSnKi^Va7xxHo7r^nTUQJrrtqOe!=x|2)O$TaB$X(qg) zg@gYz0R2huPR0qU6YxZLXX50aH)kk!_2L_ON(2S$3Y{{hev%49 z5{r>>Z~RhTFbHwQ%Uwe&jvy%)S;y0aQ&EQFT76i|GWUSIyr40M&;_@%c!D@eJZ$m4 z11}H-h2RC$0ox7}#{i};LpROs0;Kx69t;FINfz6OsruTYrRLL)nde1_|ld z&HtEi|D^_CcA}Z^t-EaIpLS^zvA@f(M2Z8CGPZ>*t~muSW}`H}`AR$<*l!%$$Vzkg zRC;4$S>8Ct(%TXIX%jAvug`&zGGKcWe0W=P5jZEMu-*+go_E>D&O?5P<@ud@lhI@v zLi}%tfhP1766p#M@DG^HANb^7M@9dCgW2%@6J#UhV&eU8kcOR&^S?jLWZPZ z+|pAzyw4$v#eTpzo>-787!4i=U#yu9UzYqW_{dqA=fggz}rs?7@D;CwoOM#E*`vxF>r_3E#0fYykcsd2`HIiwP5r)xj@ zlWi7KYlVE)EN*JJuMHL4uRQn;G$i&wQj0!Xzjo#nM6lcZiHIE++I_vxpKN_v2zOY^ zNlihD%C*8cj2%o=w=W})2Gx(&YD(|25e$}0o@eDhU9Y`13lq!)%>Ssf)NC!XdKmkX znzdjQ4V)TYWb>tW<+RuJm@TmOt+?e0|AA9T>*~Cn6LKj)Q%L&!fb2R{pKI`}%f(DR z4eAqJZG4h+dp_H@rE28HQRnu3cKP7QDrAvZg`|*!s-S0}bdFq;HdTaCZ@2gq#}ebE z*-C9*Q(pWzC1+^Od=qu3+(NdNBawRK>sp{&IPHr{T{Win-5qSwYyGJ2WzQO6JhMM; z3sk%X#nyxQ`KZ(h>19=tPk3xTg0+PEY;IyXR6nVNd!F5M{ZRp34z?qD{eed93|`h< z`6O1>4<)%#`5U341SXSIGFivo^vFQ<=^O#xgm6-MY_;C5waM?pKMYszo-RbIcBqsd ztFqTVeRi3Bw&m_>xUV1ha_w!MSM)7VujW%~O_Gry<0?j$&YVc8zd_sAaXinj&HY0G zA}ZYeC8I_&M3=`VPyOaHQY?d~_qn;1&8ksBr$Z;SuUiMXt?)Q1qxq-fr?}79fxP*+ z_y4}&)y*qU8~JM|*w+B7u$9y|UM0rf{wv`42bl;u4&UrtjmbMUr(6(6Z6ImpkI zwQQ$ZT2XMYA1j-S9?kSW@t0=Ri|9X4Xy4;*XLGDr!$wG3xRsn{(Mz{Xk-G1syRuFT zchRB0iNR!;_Bb)%qq*6Bgt^`QWLblRlaQzJax{tv1G?>9(ihysHh)|mE{wrX2;wap zYfHAT@;Z<3qK!*R^9FzEfwmuCaPzD$X-gyvlybxuH=jEa)4*b+zo?_E7DM4Y@IjXO zo1DPKr-qy_=%?n^gSQ|}Ab-QSaJH#vWH-9fo{smj zl-Bx-%%{i0Y}Q$%!k2u?v%}>7>wvpke}TxYcU=DmSH|_9i#`4;SH{H!_Emqw&u`iO zU*gZdLGS;;pV>J%IsQ5%_`kuQ9V_fKzU)>7>MkkT3Jmt_^KQ8vDHhW*-0(__)^5d6 za9|dGO!wj_)+-3xp!kXXmR-Mz#wNyWBJYhNXJWcMo6Tnl?;qhk;u_$APb<`*9YuzaJ$d%tdS9Ks_&1_ASJ!EAJXT_m4Xz9|KX zJ>w0{afJEh%CJb!K}wDkA$GnygM+Mv3M(a!8tCOmjklfA-A)2@&h@Qa`s_7?$w(>7evRHNoW+DXYt@9gC7C)KKb9P{ur z1sUu6XF>WLV3im^xgi5`N{JV%-nE1g6FNUNN?M;HI3TZL=Ml5XA1nJYXr7{Abw^oR zhi?)c1O7G*nQgemfwd5(M!Ah*uB4sgn=zCL6ue>&I$=i?tcEC)-kQbtR&apkus?l+ zYq45*^VcL?s5s@^915%@j1?S`ngCYrA33!b^XDc1E#tSzxPHlsDqHR~)DWmHfxk2o zHBJ~R0M+|_Q>XkY@81&EPR4mc|C>@R6u>|n1TcUKlBqQ%v<|;Gob0UI3Iof%VH^J8 zI!^SDei+9Vt_lBs5Ks#>fdVA_7n4?SVA6kgB+VQRFk8HMg2Q6D?Rw<1-KXIvk zdGIvP{)w4y3y3Ztw(aVGzk0|-s%ua}eKKeXF)=JUg!HH6!}Z4%sybD*xqS7W*yZ(C z=I41vC^Ay8JYmp$Ex*5=Dmi>S7*`haZTIez}_inp+8JES3|@j%mV<( zu`%W=`GT>Hl$9~tC@@f~p)TZ)7I$|d-Ez}* zW!0WKe1vZ!n-J1gHKu*TXvIK)u+vBy;{CH0pzg4XY!%g6&E zmCLN<2hi_cN=pzz>tcTEp8BKM%>Aqx1%xGt-V9qF)Y|zaayRGl{Ul24X>wU~TU4VP zX!O>mN*m1I{qus}DgSszOWT-EAz{<=DM!i^%GwLBqE?;jsH?8r-Y$r(DrSSr#V}J# zSG>E9_0>Z-vmzi{`%iznyp{kud%G_r(q3o=-!^ST;;4XTbm@+pH`iDiQ2mQ4c2`ZW zn|Z2AVWKhiY)%QiA$|E^w65pDTZgfqwzhyE3F4Dd!ub!KH4`0x$fUZFjDg`nE>; zm5)&seFMKAE^5_C#g{4w@$Q=T84k6Kr1@i^v->Vm7+kmpIDf0~Do-Kno`)#=ds#&v zlzU#`8_xaHZ;ms&t5dVi51oN^4=HFDMAZ*DeKI15O3(l=icZYgUm0;XS)#g6VR^Nl zl3L7$ryEz6`iIw^BpO#f46is%{j;8Sl+uqlR&+qa&UMc2Di4ao71q3nu z?SKJ&2(=vzN(Vyc5@72>3aV)3&@}*z&|2xdj3#D%zMp8eV$kgAT6>7+bX442Dnz#5 zx_*42XpL7fHj>HvVt{RhB@_7S?xgem*Wv~jaOel{raw4i;PggOZz^s$^p$Wu66`d* zD71x@-0YoX&JxzA@@8&)O~03Cq`?@>E_!SD?Q9^}C+6rd=Doc4D8iusMvB>-i7)4egndJhCub!HNb`L4g*Z=34QUv$gYSYY<`mbm6^I zWH|SrwOhlmZyKmE5g|NKM%$Pd-$U z_WRz;`bUz82%jX4OG!-!w!yjF3ntWVwXTmsb%pM9K+UH~Z@h^9zaS zkbqAaVAiT|0D>x{IRlSFUwIAp*4v1LF(+!~ABAN7efWz{T@S{nZ{c?9mi+@Yv{XUU zeq-&Vhd+D@GNBB>Uvm^h?{q1AEISDCYs*6nB|pqKb^fxa4{u~U+);(qqj&l+cS3XE zYa|Dhk{Zt4$pPwAwmJ;CbDW|c9vimx>2=&=URFSZ8e2OobH+Co$eO0{3jRS7`&quDw#_KS_6GnVYJKkhE)0Yc5Wo1Had`3F~ELt z_&Dsv|EyK?wo?R27!yecR4Y4o zW!*~oxPW|*eYWNGJ~jSgyJ_iUK%a4i`hN0E0zAC?B4z!}i){AvkCh3$$HyNzbSAR| zPb=JnU;HllSQ}`k9>|*^9|(^D+BAMoKUY3i(SNOr4zI8k2C8I4ZyftQYpt!=?)k;3 z%J^q=IPP;jNccD3;`mTE#iKQy%$$yY^SnP8eKD%aquVcRci-3BzNWbF(yR#qcR=uf zEg%Tokeyt`Tv6}ztv!?AT0DPQUj~3*hT_&RLr^yQSc&Ai!bi@!Maf&l@JX;BfmjNN znSPbCc9gm7x{uF??rEmuDVsB3dGye7HN4A_K${p%zh7w7O`w#Vjhh1xQ2Iz)HVLyL z;`&}6n4CF=*)+5r)u_7SRYN=ETa+@#rK_prW}9d0!b^4wfs-wQXmgWCR1Dl9VG}yV z{$O~SrL~FS&Ai!qAXXDFYh^@2dvVF?&l*S*AGnXS@_gUoM!ZaY&%p(rVR8o6QW&pf zP3^rX0D|Z_bZbkOOk){_#ZRqRUA84{uMAbQ$``^#dvbfNMCA`4+kX7uxk5_tONr~O z-QgzMlg5#kk*$R%+1x9=B`po7d9~tF<|uCNd4Xg)C9;cJE@`UBuS_6T(v6{^U*-6B zI!&a5QK_JvVGwysFM*Oee}<6;c*e+ycy6~HNU`&$3((5ll+r6sc{;2UzvgI)M+e|! z-@*{^`IzJpGrTfr3xj8n!~28emhVsWMZ`9XRRznH1u2?OB<;YB-?jlvTlX(PQs5i& z4WuZ>!}&t3;7@RAI~a8Tc2fYF**I1>uE!>*&a?Bn;z=&B^8)0+PsI5gYsXzv12n%( z>3g{$gQ!M1{TV?=K?Cxyhe^NMG!DvbZ zME@j#`W?J0L4!$H6%w~wk`}%PbobvvF;}w20>PdF%w&*L_j5*Y~7c);pL`Es@J zPxA5mrKYOKXOjgRM+W* zpL9#qSLsUPY(C=J9TW!zu?W!(Lg_uo4*sBh&UAdIFi}BRM6C25k9XGQSUsX22klJ6 z5r%RvZWO-f5}E=`kP?tj>32N%N&E@kZ*r{sdnOA}VZ$XWD*ah`8ASz*(--sa1o5ou z48a+Ix9YLg>N7OJB2+ShW|sI*mS(jTnS&JfJBvDtpp**0TgJ#DZWMz+f&iz7m%F0Q zkJISksEj$-OV^9+`%f@{U#W+Xv1r!j(%{y0+~C|5oS)#+b;QN;20Z1jgHL=~PwH9< zZGd$|FeGhd@v=Y5SfA}G2k7Q$^D`^Q(63_oT0%$3^pLK@{|Q|tY~J`9|!8VDEH z>x{uJ_hq6B{?wwj!lb{8Hc>p+`Sd8*Nl{9@Wq(r77Y(*-kJ{5Z*r0{IzYp3qb1#coA^D^+B$PBnzA zqfDwAU+n+TYk>{YvB3XJ@Dk#(_8UX4*$M{Cl$3+232C5wXCbe0JZ!(6()LM02UqC_RJ<(Hs8vm zTsvD1rf=p-#xxi9o|igc)A=&TjZ2Vk+&VbF+JTc1aK;Qg)BJKOR{wu!d+)HOnr?j< zD+&TCMT&re(u>kNND-CZr34hE_udJLihzJfQ;^< z`@ZM*eAoG%@4JqFaN%ap%$k`sYu38gJ+qD7XT0peH=tv&0UESOqD87GzQ)n&yCRMe z4))asz=yc#*Ydbe=dZ#cH^SJuH*)0^$srA6)nJ71sKaG|P(jJm<>ncUTo)-UQH_ zdukdZ-ps_ntWoOez{lAGkN5r{5eV0%YEeHcQ(NW$TYBCR#*Y?q@xoSL@UJrMh#LBZ zgY=sGdi{}3=z+CUli5$+n5!>@Itb{ptat>D0bZWtu@fYv0G$(XjIX`;Es-NCRtM2n zH7MIt8$F`22PfFs{z$j8r|V9tM3fd^uwCAe+!QKgsThC8FuvTrcF${({-euguW%6H zXwEFZ#z^QD6Xi2q#&A~B)Up3DsQrk|Fk=FwQaYaMnTLi687aosb6E{%31Yj2gKjU< zf9LXJiD)XY)LU6VQ;yNpN&YFQTQtGI0YF({7?*7iGpp%BgJ?kN(9@xmYa$rE?lAla zT-}euE_R1tOhKn21N{W-B>{zr_x#}HxwxX*Ph3JrnJE3>wAoeV_bp-skTAm2IwxgN zPzzcxzh(1tCw_AE4|GMam_g8v9C~omF!wyGrU+BZ!wCg^!e~-A2S%)AnanO`GW_}x4f-_ zJip(ADs1??aJC{~Wp;5XhPELO!%Hr;2t0-INMh@xk;I^LPsu^&zEeJyoVfNkP!^KL zNYDF8kfr^ZN0}<7Dv=Qe3}quQ4;FaE(MOW8W>FVQ7)1$~m6;?}q1Sl=PG)ZGBGV2+ z>OH{E1@Q#ywUi0I-aPA0_G}O6lExcPqLKUKHE@Aj?ayk;SNG*u6+;MpJ>B!=BrBSJ zs08z0d`ZV+7Z1NHCi>Zl^f#W@O)e+-E{8GUVgV;hdm^|wk&Xj3lshkWOkW(Pf5L~N zVr`ddFCi0>cLxWtv&^)J5j>+yL>Ol#ihgt5fNO^F`DRsy5S}A1FU{I_Ll+Vk<~A~4 zh#*xUUyd9l8@kFwiLn&#y5$vyTEqZx{xr9*I6#$;SVToZ|HL}JS zTPHST2QERspA;?}>Fm(i2FFcg4|U6L@*J#8{&*(FE94&W0f77fcevt(*hsqVUii7a zw1tbX>j}ga-6K`qZ}z_&Jt?4P$E#quC$YHYTSnGxWl!B z^caFQr1<@E8@Cr@E zi5E1ru9(cF*uqt;GP<-0MH?3;CL8P1i8K_OqFuaMXyrSE8uSt&o_STx*jnEl%cCy6 z?|uzWiaMdVlm?4l@_=da2d#AZUa>SrRlGu=*1iZ!#to}}^*-!$SD*YrpWKF22Ms+i zZVi-VH35jH#feLZ@Q3PMs*8Ka0wc{<2b+r9_&2w!YB!yRsysO^9)f&x=4I+gymPKh zt=&f-zgaSWVLftN4S$egHHwCW4D|de*bC}sVCH@N0$Z+nyeFQtA`c00Uc7kCZc zglu>9X0aIFJcpw0r6;W-mWVl_-t{Ft5l)k*em5qsBh`-V5^bL^1fbWs(8SH`oZ?=G z1Ctl;CtP>pA3MJAhOtz!xH7PU9o<&4`;Sw%VAU{wIHF>wg-1Gi#CzhnAC0g?L}ohW zmT%Ko<}WBh@PSv3k`2^0u00Qkmr+t)zqa6r?aDTs;J;)_l}C~hHGU^aIy$2T@&RwN z+XBOm&(Ey-d{u%JxjYo-a#v-hbT`AoxOQs>>T=-hz1-3hvB=tYOyb!ZT|?cF6xgR# zHCO*-r>1USe>BADL|A2q-(=Kj2UAW-C{C^69!zg^AVNTh!YDfo6_c z3+N2@IGh-SSzLC8d>pQgT6~E5P#}5{RR z?n^@FaFj?g`=?yZ**xAX+QClFg!9ao`N(#*AF9RMP_>SCBgw4O>+kJ3)gv#z`)IK_ zARM&kn_(Bc{~<}p%#@}gAKJccxi8rztYgPp^%ahpDyD}BxZa2vy|-PQkhlXzd3|w$ zTA{?E@m~{+vP9|bf(>wrD91)WWI20*i$*&pwCo)2={9ZWP?kH{5#^C@{KLnI;FUyl z2Fj%TadW7v^z$RB!CoH`Kb9lDeI=az1F!qp*y(0_nFSH3Tlh+7#me24&iapgsla9V zS2WIhXH5CA>?J2%ufbQx21`U5AVRsXKsoB12DvxwjQE8yCy7{XoL9EUVYgH?tW%o- zHbGg#KHwCsoK}ldjIkWNXSYx{fa&Cj5(aML@elln=dHji%6R3>3zy>+_hkB-DCbmN zwis8WwQTOVf0?Ho=)d|@$6u#Wd;X%da}M^wT`#Djc%GL#_6N&S>Q#+_D~-r?$j zKbzy0jekopy+RQ?5-2ljzLU~2)QT7E=&HgiW{VUA<^zNKyrgsz;?AFXBALvdD8z;1 zkK^vf<=LU^0NlLhxO{JKNlGgpQK~CBv>N(kL0?eN1uz4f^rR^k5}O7W!YAb0VPVyQ z+g0yW4`yaT=Wdx<6-(wqs|_3?-p&V5(r~-x9Ps&?)~pVXo8+7JzBVlRCQ-pCXWMiw z-Y??q;mWL?b|Q27POvPtkj6X87f@7gjaf|7SQS<mY$!?unsN(( zp9HE!uyZk@HZ5v~rgwP!48Gl5>D(Ld@_N3`g%+{<7_T4NOo{5HJi^P_xqyY9CPS-} z@M@nO`DXn`XSdOfewFaokGh7cHeAU*LApoL`yC3SXR>l4s&3l344Jt(o$+O0?P{5D zsNP?sbn7x!Tgf)on2i(Ma|_ADt`Q%sH`X+!B-@}Ugq7-aE%2?^VJ+)jvH88rx zpk(ntX9TR=)x1*-ox%E~A^{efJ`n7o* z9r8s3dn+ySHHv(!C}l%>O=<6H=-TGa!MSiwSqmOA2y(Y2gY`_*1SKzt4EkkDal-R` z^6!+;&|WFm1@1gbhVWlT3}x&RG>5S7;~%+d@fX9BENWg?yn*yB^0oRUtr&#j2jAiw zTc!7Ew`2kno3&L~M|{*v@EX1pFHui+eX#G8Is}e9`GHeJ>xw?=iksxO90q9|nLU6p zUQn($0Rb?T9q*W7|Ej%q`HgpI(SE)GyF-Zst};aB=ag3RcC-A}4lu-hbIm6OW zykd=o-b`p6vE=7AtjO=3IC1I*2#X3!mbM{IF_{qvjasT3E1?(psu2VfOlsp~bgS`ozOUy_Ie; z-?2Dseg(7T@O(*1A^yDVUIg78OL)dZUTvN@hFsXjX8{|#HovQkSb5hY} zrSpt(bps$|rSm~v(iUvD_Iye)qSG0bXq0W=rU%}ZOzK~K8x8spW#|XWFdOI%;}A~C zqdF(SM(FeTZ;2_7?06m#LnzirE1Y)0m*e@{p9oR`N}5X7xfZs~+oUA5SyHwtmxkUr zezqsotiR`hLsS31;DJgNY88{L#u*N&zmR=enWXAO3S=)s!7FdI&fRN~qhpbQ@g{Jvv@r}eVXG61? z`*jHcW(59LSi~qJ?|u)65U9&m!|PRo9j&_4?Btq&M!U&@=p$14;%UGGxiU}PdK$b2 z5uyq+%z6N|Fd^tGuozA_hjyYOgfoOX^_3-Yrm3gFRh;MSgFgZUSqzYy8IE|Z0SyV4 ztHRdW=zyH|DVY16%UYS~HW2m1m8;tEJh^vGUaS2|2lb2-%02~OJ z_sC&8Wt%sIpt?gjyx$K9!hxpWt%jytVqz#otc|$b0^-fxk@Tlfbpw0{1cP{pZS(N&k2OH0oKhPuO7bFWh6w=gI_HQ_%VJJ zKx8REPBdcO98=$OtvQmB$z`^MBG~wK`8g~#G3{9ZSy({5n%>D}C1)mZDqsWTC_0FZ z8lktBnR&Se5;N?GfH<5;s>d?zP(oyScO&FA?6q;Q#ziNJ3Hmxt?|}8%Noc*@YXf4) zS?gEkOBHhWa{x3X`5MP55(oHH-=M*8#o zLY|bh1AOS{W|1fYkT+MqaJDgJdfoU{0V!4CA9SHu%qf#G2EbV?q&`{PO*HtXJmh_6 z#u7k7CO<%5FrY?spaooHfj9GVHVsD_mT8#EIt`aBTfVz z`_dOIqaVmR6ZGL+&{BoMz|ce?kd3#X8R|EO3wuye~n(&1w9ZlFHHW?Z8MqmI!_ZZn&CCO;hGq{S`PAjmVgY@gr9bJ`Ema^w) zqH>Cgcxq;Fif(I@4YcN!q(#`e3(NO^wOHQJ!KN;Z%)Iiww5>M47pE^n(tWLsO_~cR z6ehiWg|H0TAjy@6FrJl4dFs;?MXh{Iyx%~@W^z>@5TVl)hM+vor*Tsm(2Ht?EAff~ z!_!+>$^u`S$_(s-!Pq~@FU*&tZoRXkU>DxV|uTD8i zeFL<+b-J8s6*K#j4fPX~KPDCGFI+q*djN)w6CnT5g9*%dA%Hd(Q0JZklr|Na$jaez z@yz7a&3NOTCtu9YxhrxuiGaJR^>dAxg_3Obexu8}l34-2@krYQ_$ehVe|O6;Zz2~2 zxfKv~Rc-pylPID9P3BiemalL|cJ7%#?f^P;%2ew=SSXlU+00|ki~`*u8mUU_Z-^gS z(2^Q5FoQ9v78!D9ihW6<@$!{=*rAV(b3!*Agm%udxI@pFX1AX8f93HcVkd zHWU^Sy%W@9^mTtFlK=>lkpN-#Ms9SHOJXhFTza;fhs+49xC9E;8wAoIGoeB{8Y^G& zjP%_0h0Og_oIU@-1l`iA^?>bYfX@~43@BE*4thfvm@**SQ}yquE5<9GB!7BGeQF9T z6iP88rOlJ{XRk1CgRG(c#b2WU#e2tocCm|6TEsj6RK6E@_2#7sx<7E@1nn3dK}e%) zKPVkoF`9wW^wpkYSApvNF`7ja*G@rP2ToE}MWXOX0=x;NFD*biU%BUN9D$8p zPSO@&m`>IOtz7(8ZC&xG6G#vOiCcniq?yS$L`;8M;->RB5e=hWcPlfH4`iRNC2Zjs z>%qvX^9vWPiN6cX1v2r<4=qDX)u>%IxAVm#kq=jh2a()kY*t1T&`i`6=QT#Uf zB(IgbLwrh}kE6lFWpx8%^@2UnK7Y!kzw)A~B*%BWPv518pz$GP1|?;)<9cfUh810< zv%M^;!v7?7V{DtbUy}kl_N=C-<@HEc6tUTrV~?Pc?S;_8{ew8&BV(q^BL?5mbKBnD zET^dHGYQPD_4=nt1R*W&cr2s2azqilKp;wrfT?v{ownr$_cH+Ls45Djo2k)}>d-lV+vkZ&0W?kSIuZ*jWU zJ{_EFtGXS|YT%Pw4t>U%>l{5rQXVOLtEZI*D11b21LEO+9E3k94nVG`FNAJ!BDAfW zly^p9L`ts%FW}9XR3^%!Gy9{`iiSMapAOi~&TpB?MlQUL)Wof(T+80vxTX=cXXu;J zch-j`Ssc(ht2-5gBq^5wQqVxvWtdVk+9B4p*r#8hYVBzcJc1nuYAD0&hO29(i@Xes zIMF^{l2PaeMMd2@Ku_$fjZ#{GydSJ*$dS0-qfKP*73PNyuy6lB`2eO%b8|^}sF|CH zn!460Hbb{(&Wo4vLDxZYeRHRO*CmKZ|K>4gcIiDVsFnIdc1JH*8fTTscp|s1$R%h0ahKKLDAxx0fY{DHv8Ba!gGBO-zL2$5!gzWKlg!d$JJY&l;YuYMuD(hxLNANL1VBh1oO^(mzoXR$) z@Mf&w-lb!VE5^j;#^oB?lP&*Zf98+#ZYgkfb3QJjOU1R5or|l0acG|k6_QnVsEj(F zaB;ly@@W6aT)gw9jQ+j}^k%2(Y|3+e_bvm7c>E#B;*&PIC9Wl;%*Cvs-Ax2r)(OqN zJDkmr0~^wXECREnSZiy{4xxq=IF8nYl|4g@eG`t21*0H=UpbIvR0Df{ah8|o7LMp3 zTYO5ECAXbA5%X?MlxM!LYDJpSEi!E<0@8SA412RM*SEfq@Tq*=^~x;f(?hwQDZ(cW1Ct(hKK1I>PhuxqbTxOM46@YebbdnH;@5NS4d$A;ks^LWg1 zBj`oC5Jh9FThnL%v&wk1N1} zuv`j#S97CgExtB0e)%dc&_{jnz04p-r-zz^ylG(p1%(S@0I``sp-b;T3S^o=NtUMlCu&>&mIyo__VMh zGR{P^_DyO&;4QG56G&KR0VZ9BW?x{T4YeqwBY!z_tO{L+^+bJ5&^8{C%@%5(m%X@f zQK1joJ2581EC|*y6CSeKnoXYEf0|h>q#o;4i#J0>r8XPdPWQdYcPGydaB#JFhLRea zw|hii`T0gp8V}K6OM?K*|0pOS^=6<>tnc9#i!!T;;s~e-y(iM-n zO(TWz5-k(K6HxO;vcz1Szo#c)<_u+z$2}^fUh9kuv2~FGs}0B-t}9v-pE7Yxg=Zal zdU~q=8;C}Yloko{*m~YR zBc&BO_FB(QFpAlyaDW@?8V-lE+oo8!`Q5t-YJVX?$4r)wSDbiDQ|pX!G2-#fowe;aB>C!fPSMWby7Vno!?pxJ_8i{ zUdD+4;xC_I{HR^cH-2Uhz&$0xGype?{VYJ9OJf8)gwpqdJo9?QXE$*G0ouswZdtiw zWcI55AqY_^hfZ0{u4e`61}X+LccdqT-KdC;#)snC>46WxZAoJcVz&i$db@W@s6+$c z%*bi_7jURFDuB_&$*`RsBLRv7?!B;dkL{^kSH(|{M*uPqPEP!F6oim|JqH|7DPaK6 z7;EB@GXQ-b_zkFX4o-zP|j&lQIj13CJCoqOs32e1Zx?!vQ6giunHIBYaEQp}$a zHvH?%35QMd|6h0p@TvZEpu31M_ch^Yk^h})_G;c;$93qWO1;%<4PZM=IDg{;^Lgv~ z3$M%{yJSz4M-iuzQHA`bl1=o72!&>l*4+so*c0<5gjdf`_B z__oQuSMIYf>W_~SK$T$GD5**xU4Wp(M9gzV%4TnbYku!vulL8jf zM>@M^kwj>&t)3qJp_rz|+xhG#4-icLcQyIUs5xMe^VX<^bB%ETjFAH%0)HV5griGH zAfEZ_yign5RuU$jC%^qNEudZ~R|8s9MZ9d>msf(rk4!Su8wA@C8D&1zHVF{iRZo*% z?GIraARHtbh{>Vd30pw}!NFgrZth|yS^m4}FUx2D>KmKh z)q(ul*VaGvp+#*v#o&w%J*Om3NMEGArpQHDYkx`57i5hV9Bap27S~l(I zq4W&b*{!p{8U)bdXZp6x!~20pzmkW=_Y>~th21XXekXS6 z$)%sMceFWTslP41=5*JWPJ@tB_Py82$hV}4nN)Ngj)-~-(DdMNGWil`>hCXlh~#fO z_jD#5dOF(k{;PJmTX>zyrq6zj z8U7BWuU6!O5YNq$I{S_c)rHLi#9CW>|8y(SFCPA*MXd{UkEAvR&^D_4%IhyvG72&s zdVkp42}!+T(&(y}HP6Ua6HY)T1QV4&oEJ2AFTK2NtlxVPjg9;@B5|8#lEPCv~e%DJ1#ach|3gv9?dhdk^1 zhU+YEjv2Nb`+uYy?aVEkQ#YR@A%5@atVH+N_kIfT+SRha`t^v>bux$z7k`9Es^8v+ z-qG6pCw(hF+4KhDO%)O{u_=#kaIwAK%(OVuK!+bZ;_GtMapkc|-$bpCWZ-d^7i zlk4RpzD*-2_G_8>^}R5bqQS1^{WHXTl3jbXDO~4-Yb{vsUdldP`nhWsRyIRp3CS5( zAc2HFZyyK@xX3v-e8s@slbP!2-I!WQ zoE!Pv=GWdBJv#IpnIJZK@dBdc^2RJy5RXH^`K@-`qh3_s7+~WszZL6D9GDVVni`n$ zy1eUhH7+WN{ntbbN2tR^Pl^i@=^#9+sZhbU#KKiWdK`Yk4>DcPNLQONdP%0Pl~YV& zDyr!jx9_=fn2iw>(^p`VM z-}f#Ge{E5{$E(8<`|OrLuc51tyQfuOuoc^*UCv(WmwYKFX1VI$u_=i*0^~*^!Bs+0 zHNa=&cZ^PqZZaaT%iVe|(0bm`4)srMAo@bDmp{f({1%#GR{zKQ&h zwkC<&nd}Z!nT{6080HjQALY&4p9`hrF`}Zs`1ZXvc1q8T!w#?)*jTS7M9Q6?PmdM5 ztNIe)=e{m}5R-t>=EKXsW8%0#-JR-@Ie8l znp#ooXO}t5pRzg060dD8NOrBJATRUNvU3VPu_!0LLh5z}ruj=KE~EMR6ALPa{KW(F zh=@_mR8kvxGa-ZLE|tfFCN=&lI`(*YXv{+xNQgQ-y1KXB=RrOlLhZjS4 zX42|uDaX9x7AQ8xxX_`#2w56DqEUmjSG=CrQTFano~vnOg1avFNgE#rj#D_iIC(#< z$gn>V$T+R};Y$X;Q~Nmlrr|>~rB8i)5KO|OvkvgB)ZD{P{7~?#)%+&rSW>(2e^{6z z|Ndcx|EsGg?%x*`|NAZqK|#@fxC{9o-K^8AkpC=w;0lZTzZd`i#oZI*#80Wbj+-|w z#9J&W@dV`sku{dQe@*SzSn{j%MnA0|mLo6perZ!)XyPy9jQdSOlsc-bY^7I)Lqq3W zYk*7jV0XAqu=_KEC_Ww)>e(Y-nJ9{m&dyG9R!QcZ?5uxqbpF>L1?e_NG0TR%##W&N zUszlO+9OHQ&OR&5vD=v}+1z#oct9oc>eVZ|p`zWnH4kk$H{Ly|x8%U%wC-ypj0E{e z7}L86&gZ{9IDLWWZKUQR;RVgbOMg9(CkFl>B(KcjPWS_d`*nH+ObyM=R$_Gl^A| zy*>Iy-jT7w>!ds+nzdiuow>Lp4&Kq}yY^CqP3@*ZjyvZU`8}M4+0*FHmgzBbG^V-n z;o;$?5Xg0X8$Aw`{@=vHAV0m_2b)PnCaPj>kKJ{zo{&c4;1J{L%4N0tn?S(QH00b)+>D17{w&w z`g78CPJVWjNxJs0X(`iRG&McRNVn3afmE1e!UGVg(Nc=jx4BaEBB=#jg#^F3a7TM2FS2iUCRi9gg6Locun_oC4L zGY@5&i~XHYH3oy+J?mz2hq;~`27JPd-rG1jxT%wsmDgS`=U%0bsw5pdr^~A)F~M97 z0bX~Igx5!>sGAeq8uu+n`mHP`zYgng{!ti14)?&oyDuw97i3g6dp_MgA{$@m$hB-3 z=!Bj-sA?ZtzSR+vigcRG;CS%Bq8BEd(l7BxOF=Xw$%Tc5A9BdQsbYIlolNgDOq3~A zTmc7+a^s*#WU7C%|6Ea=yur_AWeo9Hxm~!;4rX}gXgi!rf}pHawLDZ3W@r|Hk%4xr zA}QaE!v)I*yZ*c!^7L3p16N4fP_9OReRg*o2@fYaWp|gOikDDKQ;c-H=u1p?sA{r+ z3^6GP{@$5;pCm@7P)?W_yD&edFEgRU@ zxFd_M%P4s*kOnTI{}fv-hbU$+9rYfYUrUCFOG+lu)D9G;#5kQhd#I`bh4~#werc^k zQvbaW48v%)i%s&)2MV5RE0~y=AYi_H#H7hoLLLj%EHX01Mk03o98WL-I>gT>YU0Me zJ&~T`J z@fC;u@$q7-F20S-5RVo5%#vnvPuy=IzW3=aHbv6ic2LQ6i=~HJ4bk+4I3BqV3=fOn z`rd^zB&JyXXg&bWyyZ8AreOD`~Paf{|soqEw##7!UK}eX}1*8?MCD8 zo?ef4p|!^Cod~;&r+ST7)ZFh!59Q@;(_>c0+i`>fL1$S7a4zW#QlJ0)xdAiExw8{R znv4XuHH7d`6JFvV5^?Yyo7a^&`I>#&%mukB$N9I8^Q!SAgul;vog6uZ!C*e=g@!Q~ z2o{)VZ#bBfJ=NI>NwSciQ{^c;WXH5&bUv=Y`+X^{4EAyzu|2a$x8D9|`lH(*C!?051f6 z#X-PFD=1O)S3xUvdwcAnC5k~blNAamTo#)lhke(_*jraKV`Ja3Hz(`#d3eXwC|Svk2VEYjxs)v z51~Fg!&YWKb8%S20Ut78_xJ#PBICLGD?=%KACDa^(Cf2Av7}D>oBljtw>nzWKGs-a zupcU!`}Vvc#c!>KA9;v7K02^BKHDM)_%PW1nsD`nEVteSvO=9IrKlW`a>bfty2A-) z)~y_$sNIM66$%EN^!oWVGkan$lbBXJPdOov;tTDfRn0^my;f*zy~pV2D6G2Hpy-+& zQq9a~yYh&AGx*l9hI^G3nZ!@MlD?m#Rn>>D3-sYl;rxi*11wT@g95#|&_zMpJ%mz& z42%qw6k~_F0&y=<^-%jRDo&SQw^DjF9xCOo z*=$0(>~90s#>8umMD>W?4u(;4->ewvP9$rBi2ckx>`QKh@k67Mrk2+Xp+?(S@$p6!cy=QMTLOZafVQEwOOcG3yHayL>vHAKgL7U!27M7Y zw(3f;Xs47T-=B$+eRqYfz|D1eyTesxm{eolK^lZGf&;3TEat+Zte+Lbu0g{;bwj(R z^Xm}8e1j%sD`ow){bl@$>?9JfPVojQX5b^J;pY6BsSN842dn5$?4R;iWVZN02$MaM z1b*PMcM5a}1#@ST=umw<-|hOfDTRIY=dEzRL?-D9N5_4*AHM7|$*o)&&03F@HNC8- z{=KF$-K56X@oYm*!>Z;|(9By-^I?RL8!%xKlo;W=B;rHZZZ9`ROF9a(zK zCSy`LYDw{Lk(}F$J$+T)tu@B#rL?V-8oh{Fk^xq3J#v^A*0dyW7qK&9M^5gEty6$; z)_svhcQ!VLzTiLevaddvnDJ(Xi=gSeLY*@<7e;TA?}?F^0_;S~i2B5P-|b+o!O5%| z`IP!{(N=6s2a{rKY;2a7=akcvJIsuc2#o4RkN^ng(GI6D8-6#m!e~&G)=#x_}To}x#_RgMGVOID7Dv5k)s zJ?TtqRX<`3G~fXTm4!*hRXyQ`?st%&_2&8qe(RI&kCm~!Ef?npC=W7>EtO7^(L zd2VkhH?_h@nS76JPq17hpv0q}QN~}aSr)u91QGWBc24OXE!ILaJ8W&(s=3^Tl{Gm==HU8)TKP++KBWLErhys&b&eWlwtJ9mFo}N{X z<7FB08Ch4_S;leB7y`B~` zA@1TN5FYuN&9Y_Hm72@ayT2+XCUCtdf`{*ulb}~SXT(Fd{jH^&hwGUB{G)HrJ#}f# z;|uh*LqkLDlh1w|4<@E~sbdS+M}Jew@;AB#&}a2$84T|1ZE@-#NJt|-Tm1Yn#8_dp zlG_8Saa9tDv$7YfpJv$;PnkfBRywrTccHtx1^D5L;M?;{&K3`D~&@xA{tVxIcC2ls=sOKqu(BzG-l52lzloZ$Go&en3gB z7fz-N_%EN1`knf!tRSW$C67u=ONAM<7T-6%g3GYr%MKYJ(lm~aToq2cR?;4aCzm^S>K$-`Gg=}`Si(YxPKb_6P~ooa_S*!g9qJGKtUv-(C}lxteAH3KuoG?5+KMyt%c<^#-}Alz^>Xi$lO)DvVMc}wk%jjX8TMv8T zRA%CtKWL1MTFm|sNQd^X?~Qh9|1L3`EqlB>gKY`GuZ?FCu#WU@>M@>?J&$Y1-m+L= zPdnBbdK!7}+46|_nfl8xL^gmCTzbpbb$GbhWtK4sb6ZgN)IYZuGHrn?IqanZg46WwZ1xB9=PsZN^a{%i7fnDQv>*OfD_l`oH0SSTrJcw7 zhBRoRLo_zB0$M9&U2w~ImeDP4nyaf>ULO5R0b#_0jw2RhxN}Q&ZP2w1l{Vd?d@q-n zjo^mmCY1NEZ#o0a9*kUJw+w~x2?p(|dZ74D9?uJC(CxvRhIPD?IF<&jB}R~{KMUPOJX@_MuxRm$rdDa-&Y zJ=dq>H1RLmz|It@<~B67@ugjPE)|gyOG)HL#ruO0)kZ)el>js)T3&mRh2_WaFTU=4 z6VBM*`au|qIosL@)1q4K6V5^h|0k=v3j;cB`o%X=tF2m7xWm27=n>D1TR+|tmhwDw z%bBTKJ}RO&6)r=)iBrysZnfLnkGn4-SuQ{H!v2#)It1|EY!gfXO#)`B+J`23D%~UT z_vD_=#qS^Kf~%w}(x%V?KrcoF5dEThMQv{epNt(OCoZrt3|6X-_5}9FZZwL>#jK|49REjBTIolCL@@@xu~Y$frg@PvJ~ij z05iO^y00(Y|HA(I@5OPttWJMW)dDM^AYLf2@wRc3)0oX-rg6k5?{L5{PHV}<)^_~i z-OnI-xB8U@`s%HnWY3uDjej+x0Rysd@VZ?97CED@optws4g)^t6)ZFCD+=8>u#VltBJ(^tEj z1wWB|v35Z?OR1~W_EBPpwb8MFO|Q>qdb2=hAu$rrAg)uA{wR~;p_doxS1Dc8N$QEU z5wurKs`i?4V^|^@tnuQj>`A}|(gZ~B-`G@j*f7f5!!q7jvL0`#hTYM zETA$RrxerM>#uw%H!O7X-MYP|$zHpXW(XmK4uEU<6E$`VU0}>RIy~$VW%kL>P98W~ z*?6v97<(<1!Rej>yLx(iDqYoK8a!B^kyhNb$Fu#~%QUbiLE&14aD@*eOc1`Y8x!Zb z+^W91;`#O$kKMP`hzm|`co=U9F&YN0(1&L&@yGa#b}oMXYVqvR(>KFgm)~|ab)-5y zg?#-gM9n27aVgj8;!I(gKKr%^eWKmaF>djOnYEO(4s%#&k3G6X+(+AO`i1io`5bMIKTK2NTi8mcuH0f@ zuvv*(m`ju+Y+a+rI{jQ$R#pb^2L}_BrnJe`elLIQ@Uhao(G7hBKNzj07-%6Iq0m*} z>bJkMa+twr)`j-;{N4`*$m>SR<8R`elGN)w`}meQ)V?GxTgT|b8BD}YK&W0^LTGJw z_VayV`bgtIxpBC-Ah7V*c?e*>5F$RHyMTP2D7vl z0}s?FuYZ#GQ3A4&3cx!mIMjJX5&HSIup5rRP#5b<+DuokYAjFhb&ZdigpftF|8TQX zPo15e-P%wF3?*R9K$h5F7IQ3qr8B7pGc6DK0i`ks>b3bL1-0w=6g*gJi1+SOxLero z6gU6b*8rdHW+t43dp*?km{f(azEKU+sB@xhE4=h_uU+wpnRodbTS!Ig$_i5|y@>$9 z9RP$MM>uepvv6{bM@!NTK2XE2CBppxr3|OZCXaP&QPSdYuZhi6-jS5BC2rhC&5P}Q z6Pt~ZXIFvvRjD5z2TCNr=*d9v8Y?2prm~UaHSx(dC1zG)>9_1i`*>!W=+>Cs7mGoL z-fOL0=&JJaaLho2yj6UgM-rf&_(0FM9}JNm%vJ^z#hv+2;PE*#s-{P#FOvcr&%RFH zDv6YUYixWUQG?MsWhKq`$1_z=tbCb!kPh|my)m41nY@rebY`wON&5uG0HOQh{iDRm zt)P2YOt6VZ+PT>8@RI*ut+|wc{dQqI&%h^(LU+1SIZW_37qyR2EjH?bKsgE7F}v}H{PC@AI)H6x zU@?-}97}5AzB*_(Fxrs&*`BF=WEAi+e01iGKiH_5P!D|kc4^oo!NJZa*dqg`X5`U< z!$g59k(M*G{AOS}wTWj-B*GHpDK?&q5Z;qU4tI?^K>RRKxA0k;+P2zvSIipPTL)~4 zwgU&lUl{s!kEERUYroav3J8mf6=nx~zjlU5f{(UDEwNYYX4Nn>*Ji^c zqxzx)i`0PAv>jk`wH9YN@2b$h+dW|53zJXh=6LIPD3}Sr4?wD=EA^;Cj;i+D!Nk2W zM7f=+NONmQ<84{0+EB`-wy*6B{2;DxE;AQ}ZFOU8dC=ta{rte+QXNfqc6La}ia*YA z3fa?gDsA^x<#M>^L?^Ol0zk>_Th+K3SxHzmo$}&6>vs}&e`<%Pyy*LySm#?~8@;^C zVxzE}=qg`1J75h`=KW+t&t8a#e-!*JkjW&6BsoIx#VUUp)N+q0`{iR+jyG=|fsozy za#qcT4ZTOQ=Y5B9WlK_7%f*{BKMafuY�JjSJPS+7r{*^Z5t5+Ak~StE|N zypdYrwZ5uWHo%K+o3Ehq+5Tt|@x*O<`3Y|MCO4*6*lrGg+Wh;&GI zNH@|AN^LqfT^68pNVDlqY1lMKcXxL;NZ+~9_x#>-e&5f%=iJLby7!)It-0nJW6m+h z^E_jj9MkxkcZ@>hcQBVT4i1k(MG|U`s1>ZcO?Aeubo>NFK{T5Fcq&mavsOQVKvJ)B zZ9pO4j8aDf3x2So;LUx2QbtSh#&f$nS0BI{nGx8LV8uGo_ieFt**d-xo}rI2(74>i!C8(RX_M-FKx8Gn`gSD6wcVK}n;kBpQ*I`88-qgce)V zz4;MdsI<{UzO7cc;$voruJbcjUn~-rkn4)0BQx_r2*j=mBgGMH*{lWzk}lK315Wm> z25E+AN;?pRN)i1Suy(XQZ~{@_5C>!U2m=L*XWqnW6RWms5Bu`08eSJx%{u#$#)%vk zBi7dMaYrMyh+t%MO^h5&&Z9^9)Z7xOb2#VICZ9h>V+(@Abrq8t!1j{p8Um`KQA zf0*eq26td1+B%tGX+rUc8|1!r9rv`Df)5gNImoX*mP(wsY9?#UeKS!K?m_LToYKoP zHovQnJax1~S6+dWXZBO?+^|E`qsHkqu*B^tRPU$wyv1A{3cvRky%{}4{F5FlB^FiT zrkKIhEqZZFjg!YSyHp04LDo#koL0LYD6|)6B&ZGhJJ!KiBi7 za#*MD<9nR#4Wb{H0_0#0FmM`qGqmQX5~89duS8XpOifFkM<--?iS=S%rx8TCTO`ab z89OQ13iO!;$6rvceZi&&gzaXDp`Ec&&Pt&ZW!H@3;k1F+xL?&ved@mu4KUuBnH+}L@_Q@)V%3b-|5*lbv3ZZb`>9NLREg5!u z8iSUAA0P#P@_6cGgr1X&%UcOe348C2t6uBQwc)PXgjz@Qh3#P|8Vkh4Z>i&SLJZZo+}8Cd zQ{v(X^YZfg>7~j>rIDu=#TOPmv1nrrj%!F>y-EqxWIs`}_xW=4I_Sm~v;Yun&arPV zbzx0;`dMX#sYJt z#(7b6JPuu}3L7uq#pBh!*VPf><3^*;vVYX)ErKDq^T@$`u4(V z!IVWHlnfPR9LpI7N8LSLS;K-;W;z_a z@smpI2-dRjQc_HpG#;igX!7~7xQI^=m5=tr+fA?Gv|#@}k^gnTs2lgBXL{ zkATZi$jHc3hGC1*wKd$_Zm42?1UW+awUSXok=~%Tz$sj%Cy()`&Wv`l2%5EnL+GcC zkz8h%q{Dag^gX&wJ`x5&5=TZS1qT3IEv13V7ZSqG)us>KGEYod-xM{~pFL|8uy!o; zl)=jE+#05(*T8|y#F?)P-3tmg>E(pE!*53P zSrSerKCo~avRagKgsB^P${dvt)n1FBZjKFDA@zjQCJk^e7MiIw&dl*SUI(q2-_P0f zFDzhJRlB1`jhK1E9y6Q4@keWU8mk@Y^E6F3ch{GgoU5n1ySMjWH$H!#GK9PB9#USn z$%_U~9$k*YVdI$3-4SW5fEtk!$>d@Zoln=)YZc3Xt-4_;v_&*oY;EWK3a}lf+q1!_ z%kyNxXg#|RQA+NpuMXPb!eX^3q0K0;lW6rpm{)fRZ`vV&-6x5G0j6A_Zks?YIME+uT!@?Lk-(Eqxbpeu_Sh zHz`dtEnkf`Po;V|Z_%qqOn-eNn%VgM*{{d|FX@(*aB}eenx)kY+W7@N<<)hs5!R_F z$GJ&}JcYiLT~LZzVi9*ju}!KE2rAd6GV7b?-y1yA&t>Nx6G%T!vhdIg4YQUAKV&l_ zjb+fW$jZ%T%s^}4K0Q4jruTVfphRgwBCX8?uzpcPb<)h1aY?6dsp;L+>N&CSr`*BZPgRWIJhf2YSh6c|ZbQDqrp zMyKl<5Kt+O^rx2336#ylf`jdGh9DC4ppntm{>w`GO1Mil^~z}Zu8XYWTiUJQM-w2W z!erRl@3vl;(XZN)&z|ytb&Xr9+NU_(RehC8sjzUrO06`<*WCO^5V_iFmZ&tP9LW?* zh4T@#EZqNe<93v1daro1zhpHtz$v}X{rETyL=HTz!6Ufb_q|ABLdn#u*nQ5)7x-g# z7C#_RwmCba?RHcYE%aaohi=Zm*>H>vTUMe4%sQ2)jb+WBV%YNJDm(QzP6kz4q|@Io z5o?qV4OCgQ1=ZixpEZpciGp>L-DRqp6$eZt6h4=;uS@KO=Jb|bj{Iv7@_@EvRNO&X z%ehfi{2ZE3InTYxHCFXMy^x8Mj?^>2cPe5GSb7fdg>T_=`IauiHOD6>q4}Ztu_fB8 zDJj{PMlSZ|3|%!m6E(H&3|%VmTo83<-vPuyU#HgL8r)bDw&q`IHc zYfNCS8LZ0^tw{?F@hQR04y9WAEvM;0BhA>@HDuCSY{Q2+b|-CKHjFKU<x^v`BkZ zKwwdjn5&|%)ch?a6ajN>A1Hww(OUH*QjjB(Ke49MC~+U={GkuvZo`qguJWET(*bZN z=oA)DS6%@TRv)9RrN%q5R)CX~DrQd7L0@5%PVm5$qa6xv4a9iiVSp`433fi%t&CY{ zE|i?TQa@(Ya!RxOEi^@yr&%I~H}aL64w@E$!kG6Us~5+z{*C1X4ht#Bs&3YbxKl!D z)m7D;ru}?u#8+WY!oN~GR^u-|5aU=YUb&ESx{Qoy2@ zsjwn0^44@eYpYc5Ua;t^%3M;I<}FTFE1ugaR%)O^PzW~=i$>gnr_5HO!iah?K4eP0 zFLJ=vEIUOjH~Gve6+sSX(Yf*T-@GG*1Bt%DX-G&aK5y6M<~a`OZY1WY}LjX7QG zOMg|XENQ6Cy;5(=((*|&tpqtXPEtDnrI=V4=sN}e&9B+6K6KJu>AjDX?uQddU(Hs6%lxV6d5<7`xFG30ttu>1v`Ia}EnH~ngOM6;rS z13CsGmBz+h?C)JM3ft3N`@(XAHIWszX;G-Pu4_MzpW4|WcVySARZFWC-vbtw@j8gp2$y&@#s-rly@sj8MGT%XKzJN6ayLMAV2nrj2Qyr~mc z-`|^)ds%A*prWm_UE5KB7v&dv)fA6y9UFcKCP@%QYnMM zZpwQtS4I8|B>4+nl`B6DbT*e2k}X;%hO(a2`s29RAvX;2IUeJmM@-qD*CJaEU+!%Y zq#kpv`^{ic;{bGnR2F$k$H5+RKU*^k5LTMIXpbWL!)Z&wGiwjS#g2e(yQU0C#dizK z6)LXwpK=KTwx}X{3DZVrrYsGSl1p?rX{VCLh(=kJ+2j%_UT2s9b=Irx9B%!EQfF3V zn8}kY##ZKu5+*Zq5Cb%}|2jYMRkGv1a$7j^SH=pay$O%itsUn*x6e1Qhr+Z6r6<>g zzedpF<+v5kRD+;<-8_qJ>4rgxq&8b$|2B&!6Yn7|{GhADL{8|x(kF9z+mcL&vQCo; z&MbIb?7tK7NV#jTL(J{3U~3Bc`l6z_Yp2%DM{{7O?MI+6b&>ZiP&PZf3zx-5p6iJ} z(g!SRWktibL(RVQl3qK!YE{-Z0Ot{V)iH}vIr$)khlPoTn=I`brkyXFsbTbAaHO3yhS_HhRDz^Gc@DR3L7DY8 zZsD`&qct(&koc0$+M<~BPQR)pklRIvov24!+Kyh(4keE}VIM^d$!jYv>xcy4Fisrq zJS)Ax2H0*$lR!jwcYuJ>>TnJNJ~mA#5@S?$le?hWuZ8vjvlN`vP zQ_fblD{-=9kLSsdnyllM*B^9}mxtx>{k5LK$CSAJQmOPAp`||9^oBGF#xj~yLES%* z+RMHjad}P1DmFOIHJkGeYkf97aZMkOv z=C8#Gfe6pVJqt?UZ=QL*msgcxFap3{4hBJFNT~UZQ%$9OU)bE*ilEi{G0lrR#vR`E zzQl>9`Ju^PHc~$>R)8lMG~ArEpk_hy9c=JpW#(fEYR&OmDCO+;>7O zXXRF_qfgc1K6Adbo%^iz2lSL%RaH)Tj}7kx$aE~_O{Qffex(7eT53kM>WRpfDAV*L zckOee$68($)>}z2F{WZ-@50lc;NT<c#cq6V`kNRL+}^p49ot5o}HSS{^>DR^n{7lyq% z#!y~uc4e9J3hCYJ6T*CS*trQn&;T+8&?l!>Fl-<<0dPXoSb_9J+W~IdcOu%w3#J1j z(N$;Ft*n>&@{HF2z>>-Ws3PFIh^?3iuXR61^pl2dTwdFmGF2%XvpNnzQTZ2Z0cH-Q zz9w`aAKuw8pm73w4**RH-T=DAR=fQ|J# z4F2v0vO`pK#Cei`2@{@#z6Ba~)Dk z7!*~0l2z#-S2ECL7VSn}o07(1Jj76B|7yHNnvFm$Iv96a&rJT9TpOfKIxEH$^rbpJ z(dxwq?`>^v0>0~XxB$7Oj$IpI@3d}S8nBGI7l?hA-w$$-y9O3N#;$_sfXnAU&+*0^ zoB(p`??s@r_Qn+7F6QJXcUJFV7UdU+x#Hawa~^ZnF2Kjl6ntIjuWdGLag*jo&!S*i z26%f7F`HEHiX>V{*A8y8P$#d zbsxX*jj4*L-K;Pj=qcRsPju>GSl49Aqz#uNkB-{bQP@gz{&F0C@GeQw$tgoS zd%A*Q?~u`OjrS-m<=2?}Dy{==*6}LfvT)>f=n=}xZgT6o+b`c(#eW)OGg%N|WPRrb z2&l4%0t6m~1qa*|W@TeLnalK?($uNnNS^J2^0c;k^O+H8ng{No-Hj3|8FTA%dR65T z0I$1v5Hx2IC)^)YMBcD(y(eM?e1Na_<8sHYjkK?5PqXv+FC@DO0Vc)FEVvgrH4v$qD%60nNLK4R4xbm9!Sg#rK}4%XzZR<&=A=G zc>0F9LcS$gYIEWZ%pWnEr2zO7mn93K5K5U%)2s;E#O6e`A^P(q=*k8X1Y^&_CK4|B zCy=!O9V7#S3MP*LY&d?bqhjUN`t)r>VVW)hwhv1anen{HI&3jA07_G+)SkEKQ2CC- zsKLW&erb((vY6ilS`3dBUdDK$-M^vhJ@o8$UN+}i&>EZ>UF)w}^)^Thg=A{E)PJx8 zy!QB4o^(j$+T`#U?nSkfuVcG_lm@6$g9U>w6aW~(^B7L+8InHKCywmu2Z?fnGZPDQ zz9)bR23EV?{MxH%zt21I*B9gl-hUnX>Ynew$t(a54Z z^JLOY3K1pcnM%_&aERcZpbI+?!SFC5NH;Iig!8QdFGrjl zYGaQI$P8d10s|-+3>{oc&pmI2F8-=+>w>p*Ah%689PMTfrG$>rjv&eCU@Mn-ddpfz zMNbcDNhJAM(zuoO+$=1AM4n(|Zf3$iJx4r91l0o}i24&s+|VBpOD5WlSQNBP?9Dr-c6Ew$(nDaBtMCa_nO0a0v^%r~qTU{~B%m53Qq2uSNMzMMe-}S{ndwXbXtQot^`^HCr z-`umeOSgZvk-sv#VwoyYPp#6g^UcZmsE~-6A^>zbNHzkH3{#V8(LnGG#0&O%9e}>_<}Ui zr}IsXN@bW{3;rWl;a1c$A|fL7Y+^vkW(LLs$P+*ZV7j1wxRGBw&c*I0FpOKt;Y9BrUKCVLqlt37L{n2 zL(rM@8Xx5j?@c+(bnW%bi1@D`ZEf)T5>t6xWj;c+YagrByG6mxYBoB%Io~Y9nbcpr z@vYzBv-|bsiBzs|;goi%=BWq+KD#JNRM}B6<^_;IO_X2x5%JYHwj}`9py3Rek@(7actU(A0lwJ${J{q%1lN#q#;E6m&aX-jl-*{;@VT)@`n70Pm_L;q#2HbV1 zwKXH>l2$$LIl)wpzEy^lx2IaOSTA zh(}%Bat&>*I2Mg+kmnJk?&GJzOK#Hz2#v`8 zuh8-n6S36sl8vv|KrGNbgg%29682F*WNwJfRM_I?(W*UN#w!)R4Ja!$my_I8A~deB z!2O2s*Ol}mCin~U^UlkiQD%9<*mRm!C%YMa3AE>Hk3WdK-n2T|UjzJjQ!XbD@Kl|T zUiqFzL=~^UKn~>|3+3-n$z53?+6B6x<$CX($qL&;XYX8%Ojb|2lO0ns=|WqppB@{z zWuuSp2fac_k*>xdK+FR3>e54(oNEIl$uK&dA-;sgOoenCePK?IE7#0^1BtL~#)U9h zwJJ|?KosgXArSQ^G(XR@4R=4^DvOkX0Zq+=E@w|+i8wI?X}z-+8kRMbr&AjTiLdR5 z0Qa+%E>&=TAZr42Lo?TT#uLgLTU+*vtxs9s-d@ZB-2Zi`OnoAYD4E$x=;c~>5=@6} z=V`u!wSR`n^>D5RM>*D1wM*ICFJ3?)RkWRqU1c37dm{J9ny{>;oj6WRlyNzJXCJqJ zaaFlovBF$a6Ofol96_h03zStB<<<)#JJW9ZU#N=hlX)?8RCmufcvs^K2bRDcP8M&7 zInc)gqljTOZ}*>wY-a|_5M0%)V($pqfxK4;g%~V3zEDhQhik2=SKS{VT+YXvVX?8X zUp9Kc&_=VE(!~t3;Fc0`o4yj=1;G>`cZ0pBNXZ7c?Oa8UO`s@|U2g=8{Yt%-<_+jL z+|F)e*w|t!>73iV0xDi)l}JX>+BPzxH&$p6RW11Bmj3YCK>GO!(d_oz2g{u&FYwiQ zvZSk(s|`A0F?*Re*(s`=PJCEMQa>0oN3XM(QEckv*R`x25hE?X z*wF~GqL{^*oERyCaQL*D9Dk+>BWv-0484#7l7A+Ts|%n@3)_;q<+Kb`LEz=BzY7gI zL;~=~N=(a^!3yRdKz5&DYrl2S_hu^z%O}^OZIE*QhBY78?VgaONX$sd@mn)r7 zMJ^}XwU=9#r(2CDK$@xJe!2uikL-q>k>G)pT1@2tosg`#k0Yz?Fe~*^L?%Q!LoJuT zs`7YCqpA5AK(77N`BgSRzRpU6kk@i6WhsjH8OiJFG41_8LYHr7kl(K-R6@vb6M7Bu zdSUDz9DOd35uYhkJuTWX8xvsc&vNs70wx@bmJpls6c_RF-OI;QmbIzu96X>w3Chg@i`N2Wwkr#)=_G=PCbv#& zdyjT3wO93Tq{A=cvEiU|KF^uxp^QRaH`?QU+e9wwhN`a2Rx88-{O)v6g|rl{Reg5E z$CrHAoGfVue?QD%f&L9x*i!9N-2CW)1sC*|k7kkdkBFF~+|LK8%^Ov8YrJQ-qT&zm z)y;kVXK61;S0E~D{1qSnH?+n7)E=>GM4aTGwab6h!+*ulf27R+EJuE$UP9G0!Nr1x z=4GEYz(Z(rNbyG}y`O1W!@yj~yf7cKzvH2>in!Lx>&K78D|?%M>0fC6QCM@oU1&+y zS{=?$ztLFp*Bno~7#DK@nR*P{pDGYR`Imd5KI!RBiOA?>YZZSw?O5o1_=X;Ou>40l zpKxmwK2!w?Cp`ai?Z+Q=KurG#Ceao`iB9yVJVnBLquyB{R%d7!hWt5d_PYlB&^poO zK>AN#Fkj5LhK?_5YRX?-TK@ftl$hAd9t$J%d-|V2c**yIZ@RbpKl*$7VA_S!-ky@p z^6ynXo-PFbFzjMH!Mr)cNAfu!RaCLEvU(zQ|AC>&Au1su5f@iSttaGB8*Y)uwfogM zVq|28`L6cR{Y5bNoJaQ!d><@N=r$s%AT)fRI5W)yB@ zP>6#Ofi}V*KsxMCNdZK>jWEp{Z5E=%zrOfa%m2-x@I#x!R(Da+t%UL#S+lL5GdyI)}jWzjCfJQPjR07C)f)CKy0aI+i8g0`> z&@e$`LNh@`Op{SZ9Xd8m3R^y!VkCiISlNY2FB^sj+zc_0DL`%|Nx(d~Vot%;KEF+I$9vBV;&fGXJb z6jz538qqlHvg~xJ4c$QAA6NK~DT5@l+8d8FsUo|LWn&dTdfs;}3=&$5=KP>a$z+M7 zsH`lyipmHmSR>t$;755Eph*_2nI)#mUq>>R=I4_}HnP7esmH!q+1}cba)|Hx!=N;d z05)hoQK~qA&r8$28Oxrld=3hvfTAqn5&Yssy=w8Y9hmgmQp=~uJvjI}XX|Mtg$Y&v zr6Nv8-^GPQ>!8i9kqr>+}~w!V^Q`_P5{3@ zS1EhBKRsmxZ~!*|zX2T&7g5}Wkf4`OxrUI-@T*_ErvOB4hQ?bJ^jnNF^eL4}mXRBA zAgHmkO#5#&cEawTgTd`;HtSFM#C>>G@OK^p91z7v*`x!mb_41g-dq-L=G6taGoKxT zaxNK9LEu6ns9yR_Cck%UqDXp(WFaqaf=?&+U);9+t&R;H=D`fAu+(}S^m_yV->?={ z3c$CC`jFUR#Yu0%dZzy4?1-oXdW8l^X~5VrH&X^U1f}w?Wp=mBDcj^%%~@SA_Wm# zx}k$k@Wk&dvE%#=_mQ+Jd%rC80Za@9O^^8z2X| zP*9DBc`XQ@B7+~ApZdbEws#F00C=Bo{P!+uP>{8}4veFmY|}fEK^+*iErlz_?h2-5 zNN1*-2hy=68$skxqf!)nHVe|fzF`pA?2k%rPOB5Xox0D%J!$Zjp4VkYA~9P%wQ#SK zzC$3r`{P8h^--LbhE$Pd538LMhKh;`PJMeA|Ne4N2g=F-qwR`RXu2OE%V4`-ro#!q z#0?w&MG0zx&NkdH(w`k=c=cz|0}oov;it`1pu@}&|TL^6n$k&!_Z5jqa~QEu4hztqRD*C>tmPEnC(pijolZW5FV0}KF| zDnxB{kkZB%V>yKl{fML?H(pQ$P-SuEHjs4|O%T>IP=)hp&F!pTN?-r0Uy*&6PwnK@ zPE39*A%nJth(YV@ZN~kB9@@Vb=hR5DzsHApP$jZ>2Sztn+y^5)9* zKq5WT-dI~Y^+Tgr$CUlQmJ{ui{2|nQfI2`!5u>6(PELMWsxN*m8&In^{4oV;R5D&y z_YrW*v%V1f0{oOarMK{JeWB>Q#N!Oj)UM7dI01xqgcH7!4GspYLmK%lT+5gM*a@1oFd*yv1G398yR48b< zm4*G34kj6fInc;5P*qSa#rGf8ht{D1w{N?fj~9;KRJ&<-HaQx?zrtzmSbmHu$ui~8W9BQ(Xyao(7EW1zAQ zK;%cN!$HkN346`gqmO2|75&@`57n>h(}sK&K`^Mcmh{(>$wLrzxTIK(`xAmN;ecTT zuc+|)de6W^J~;TPdhYSXnCzb@&XX>%Nbh|4cuPIIvZDGYNkI@MXB(KwyTHa&VDLzZ z#`4kIzjK?@6H05ab&7~sDKE&xcBCQYa9CCVtJm8vXCNXNNS6*ug*Ye5{au=0A*7@r z!uj7sH2)95(BDIYBt0$8@nS;qV_*MjzW4k5CYt@|D!=;i??}i_f@%o0_ZW9T`eyDX zWJ5$<|95}0#{1XSVLF!oP&AS4--{;xEosQX@joeeENwf%`lR|?B_YBq*6YpQ+h?s% z&Jq}>H6&IXpMcxkIe{W_UX}E>F3)9g<75_C!ph>yM8G>o;-&Hq@6EqOzp?oMP+G;DpwN z4X*>#p{h2~HWm+_znJXdN>eQ9_VvN&P|I=4)`z2A@;%w!;~AY>gq+SaZ}P3$Ypvg-IiIjxUpaljN8NE*Fv9 zWxob1$xd;Am}z7Eft<-Y~z?zUQwxJGSQndZet<_ab?0fLJzm`ZAQ&GckV0d zdSi3Xc70pggq@iQ^!UIt)xXu!Y_5;r{adNI`VYLj zLU|{RSNO$qv(rSXgca&A^){ZaXTga&fv!A(qb?-|#08Sinj{KOxQ5OaJ&a zSfJ2Bwlz}(XAe!G9YFT{F}@nhLv2nOP2z)QzpC7kV9*=)#WRUwNl56?JPx^E zdWM`)p{=XI08FDH_`KsClki4kXzfx7lKYS;RnYarIebf1LYw(>;?t$g?78k~UdXp5 zQXho?FAP#K0li-sB1TkwR(>_JW$F$RNHbnLgt&e>+wM&Fh#B-#emy}#6@IE462gvU z#O(d0JBmMl!<5wE!<+9fUWZ5+z88ws=Po*T+O$U5&&ry3>6i4-W2bnlsay`G-2K~n zc3jij)4r%92{r_qVctk{Pd$@J&Oj@#lg|F0yv){YU`e!3LCn}8f7k2nn_E(??B7F2 zk(LPeev*olC~QwQFt*jxeos9)n-i>i(HPIm8JW!a@bzrCVn?wH{Lx0SV5+=Uu{nag^ zhRevG=;x+RIZ%e&yvL-QwvYUndK=gWPlYa#S_A!3rfBEmFp&0b<#0+Mj%#=GE1Pu9 zm0aT4R>qOSYcaW6ta0X9Bj=8Bf#sIAa?6$g`G*L+P$nB?3#fjcg)E$@SV@y+* zyh;C}(N+qz`+$c$DMJ-s*|*MM+X%-!o&M#yhVqdU9dCs5;2r~a4{~`sRc*EDEZIHX z7e=r-Q`L%!JjSEcOZ{MSvnd;!N|tbyj;veX8NbnqCo2(n#1M^T1!}p8k1%#bM7+e6 zWsUgA*0CFB8ba~V;Ky8}F;ZaMuXd}@U%w4lY+(!Ah0#%2uf%6hhq5w6-bTuOieFkW zTyMf;r)|rKGBkNSxDp&l_YjDCE#?!n8h-3@^iTyw%lm0iVm{7v6d zNPUF+RQhR3M=gTujL?PA)xVc|uFkC%7+<-0>@mcWm z@2xRKMwW|jY+mf}KYJSWIK1ua!`CmcDc4Zd;iLAvo{wowyHe&d?XIW~ z`2Cg*Pn;(Y=_&ZlOp4^-p%x3%c_ic5sUQ2eP&LHwwVaetgW3<1LW;JT!+uO9NwIpt}G%# z+;7EN^h-5C6JluHZ}IA?6XXFc_}ZIeF(*_ zb4$g9&(afFy)i#5g@1H;(vO5s_GFhRUj2&i&EdskDv3K*x6oBvKZU>l(0boD^aZV} z%bhNKn=UBTJ6im^-Ctvy#!agu8%^Z6u*#LR{PoP2-=HgO$tuwXtl|{y?FAT5`QNp$ zlf-vXkTH)cyE6QACfOM9@LWy?xonpNEByl5F*nMG1>V?K8?)a3MQ3Ge9Vgf@aMtF< zdFG4sX;-d+p5^)B`Y;b`n8uLX_x`@xsy)L|T9v?CVh?Hh#Xn;u-{%$Ts4=x-HJ?=r zW!tYS=!^L^^D8|jWohl?)Kr`-CEtvQhnQ@1Hg&xvaXI(d&8JY) z40L1z=srvJNBGLAp`P|SuC6|>J@8Lo?BSJE_q2N?vroD zoso2#iRGH*t?J{wf&BM+SX)8OCk9fG8tTxeLIRY|0fHo7-bo72Jrine6fsL|`@*fDCJU#ImkSARCm%Iw8rLE>un!zopE{t-l;2A6 z(H@szj$9VJe1D&kIgByMZ94LtfBdQ^&jQvFf2m>39CSDHH&LPLt%iScdbWRXdPbK2 zw$nF-i-UL{^W)Cd^YZ68f)A0g69(3bgE#ybt<#j5t5bM>Vv<_73ok!wxvoJ+CQwsm zDV>)>BmL&>x#MPen?n7S&va~Gb@SoUUdAJv^E>vuVT8efm_cp-;Th+E&_TM9>?DC1}N@U)?c!qy_~%6f;LJ0j1o4%WT9{dJ_j)M8uK z4u^@VT-SVjqu+XuL=d0k-NRq^M_<2ar+!nU`%H@&=}y1E`^O9tm`a`ePhwNJOE#ir z0~$6GDI(qnJSoRfKX^J<^{D*b28_K3W|(nV?3>i_IcP3#V2Cf(;;t8Y5q#s?$QM51 z?%SUSXQH37cfSt9yK7eJp>c?J_sJkC&MT?_n1qrXwvsYj{FE$v1pX@E5cxsdBB--M zMkS5W_y9AZj_jVMypymYdHD#ViqPvxbL0U`Z*y_xZO)N0^FEhyN$?7myP4Voq?}`V z_Q8;q*}z$k#|;#W?5LM2uO`$`(boLFI4?vaPc7x6$<;)6AHi4a^opE^Huu~(^5%GM zOC)`D!}!^U{Bi30`<|ml@0uYsJBdYtcJ**Zl22`!YNo^FUYWpe3@g~|oZYt%O23Xq zD#B-&-@Euk$e0~;c2A<|$)96tMzP~a{aUPf*l>}nHK~df*MI7E@6j{SnveEwT#J|b z86TEx=T~0BC<@az+MpzFF;Ad${@#gRsiXRJwc0EPY{`C?w^({bRWjRUl|~^!?@YD$ zem2NFDYxY2u1qB7V*h>1^rKF3%|hm~KWcR<9Ug}?IYFn%vacJJNo` zEmakX9uC~i2+lE!Yzr}VR^>uX8+;BF2KVnAdea-~i5qY{F8)T=2gr`ZRi^MqF?3H| zJ|)c?V({!R9dvGXZqj4L5LND;uD?Rw>FnO*WomSFbeC4c8SCW+rTgdv9un&x%@Inp zig?X%e0?Hd#VR1tG{%eh6j7(Te(YgAqHZ+g)z?`w@I}$n&qV<3?H2jh*Y_X*FRT0K zR;_KeS!xP1!uT{*f+N1I#3rs!C)qBn7u(c^2nXz^y>IuW;ayq%h5Eia|DZi42IA|=?7Z5W_$9Apt?@xnwq;Be|Dr+R zZH$i@8+}WhVnnQ}J2mF}%pG<&y+|)Qx>_#QT=}|EIT?N1hM4||Q&g+3K{ZTTE0D0~ zQOccRJU3F~3`qbJXq)oH2Ww!3Tx$20K{P9R6&amQU zQ0Aef@btJJ8{i>X>pW=nM0A3LKK#g@)sE-E7i&LoUZ?0K&TMN|0iS`f!DOpQcI=ne z(8_fN{+sjZ&uflGuG!ndhS>3lo7T)s2rSxfomR}HpG?;kRrEa?ePMI+6Fc6mZm*)- ze+(E{Wvu^`SkzmP#<9O9&W_jp0Gt8w&&Q(Me=PX#cfi!^#%=-kuwvbAy~U0M~ow8H$)T__EM7at-nG-vj+1m^GJ zX3X(u>E^PCv)==~x@io$_NPB{W{9TjcuQXpT`Rx$Pi=BrHT2%bqFS+jzG=$Oz!h_% z<3U+A(04%e|DE;YJe0L3KTcd)dF*mS=HHqZaA;h=*BQrOsII^EM~ssdYb+|{E=8$x zX}F4Pim}FQzuLbyKZ3Z-%|!PXZ#7K(X{0o%7r zEk;Zz|M2K=jOh(l$7J}VB`K$Ok@<5%v3u>1twRqzr`DPVHztUKRP3d?ZiZq_-=*z1 z_Gz1pz}9+-D}dhO@b zjyl-S9~BK?ds!9HZkY8^*T==h&3)6lqf2~#S((0bQ5WfE4P{>~Z;VHmHmnUL_xfT? zmtaoEj&Ge~Ta%wo{-VVG4V$aBd(uH@fGjha3Mb#2sB@Rai4oOR*T4nj`(5a+dgtS$ zkeJH(>Doqa>|=Y>mVJWZPoXXfD_!n8kpp|qXc1vsCIMvL8PfP=_T|QN6YwGy5-^UO1|XYbG6d!7R?SL@CW>(#H{0M_J5Su&PePuxX|AqG0bs`5yKTPkq^k=0 zg1%Y@_P$SIRSj_*r41lMaHZ@{X_Hvu(M?D0zV`FQ z>_G>>pqYLakN0Z)JG#`gtNr7^QI9PDB(|TkzU`WeDIN}!N=*WZqnLb$k4DfP>#PNE z>X7&vs1cI{g;XF4H`B}W@6#0YLoj_L0AsQ!k9(S51ZFSS6iPTaO!6U24UtA3kSz_* zs_OuHYb(G(uKl_q6e{XM!qtz-fN`owX8P+~sXJHPW2^mSjg!(qO$rkHt{wV%?HktuH*D z7h&hrI03F1RbceM`?SfHd5iE%*vZ1cc2D{y$o7x?-gNHmBqAu2AdsY$FK-B}9`s{A zH$a16mfPxx2Ha<0fw>?<>C#ty+qQc1S2gx=d(Na(y<52$AHP&u8&q8Z$3UiwJK@HY z%*U655|3nEEa5Va@!amFhRcV?+>-PfPKY}PDoFE_FOE7ZlgH>P+L58h0@#t)xgTu&xVag6Lp5vxD}Rf4r_)0*18wL;VHJ&`IfZQ+tyi=t2FPr zo1Za8Ea1RRStx+e!BG30myT+siN)|%ra8L-AVQ(xSDJvKY`Nk$RVH@t~Rc1 z;H_D*=A%%zU$4@D{ZPG;Tmetw9OqLT({uE!O7~68^WBi+$(~Y3+SSd%l&My&!P3Pt z>)GeB1J_9C8hGGL6>}^h`%AE5uk`INbhsd~ad$Pgy5^Om#Su(H!FZf2h@`999@RJ4Y<@k*UiEFro&kxNMN*tN?dN4W7lndFK}&1% zB6ewr>TKvjB~XvBhHO{A!LaafpJ?1>bMbp!&%w*_$)CN271?7S%Q|R!e#{JBRt=<} z;eDvMI=QhGO{hzl57c+h@=P5WT#fCWS;$1;P$(PU@v{2z?WgcH{|3+0e0A)?hD(AN*h&#qaDN!I1lb#ns;q5o7yQ<-5u-0*wS@tGBA{ zu(DrU8(KSXRAgu?jKr=nv@L>VASiZQUb#_CC0>d!tx}KD9?}CGx^q5>onAJnJ5p1T zUNOec_pZkC2e#qf3rNJ&_oq@z(&B>dS;gAejfrSY8z+OrAK(R@nBMSYA(=V2Re4$6 z0bd^A+6Qy(SaN3(|bR_z%f3~3N0Pv`+XvCX1^0&Pj6L-pVSFrHfYK=zVdHZd>H2!3Sbq$4SM34jVp7FY}*` zet1jKcc(ryTo`4bPw&HdI1SPeTCPyKnw7-H)-TRrCj?9vW{#1Wz`2~tY%j=Oz)${59Y-WgqJc;)JRXZ`>eeI=H zw4<6g1h5%1U>)IXtBsMRh+!K1drJ%4{R$ibbsiAgC$aN=RuY~0qtNs>ANnX)?UamH zIzXcR&a2`)f~bR3_{rhappXDC8)h2i&n(@m-kGrd?R?P+{6wee zk*u3@xC$&E3SziI-;V>&&5<{eUCc-IxQ6Mw84CW485XTjUp>TU5g`@W8jhuL)d&9Q zM4OEESM_7{gfbCh*&mB{a0e6zs{kAS8gXIoy<_Dbxl1YxuVKr+hxB7Fw{(@46bc(kJ>6YU7C7^9Jfvl&&%BT9; zfMFRP+w0bD+y(3q>lN^O`nm@Pk+bM%J;u>|o zT~o6!RQHAW)2bT}lse|SZOv--@4LvY=LB+I&I};UZmZ{jr9i+A@|`iSQll!ZfC_{8 zXVc9U7Y}T1{!K>~5OzGDf)wy?*coo}?Q7NY7yWqKMVY#25pkg9uXAA63F7mF(V($J7W4k6UpygPA4`s#+ z9Wh$3Be4VaegOQt5jtw+P#(34&F^YaT`Sn3W`-Y-?9;FDFE7p4A)uC1*Hn%$UG|wR z3DuH1NW?~X$7)hK4>nL38*4$|Jqu1aoYxzw){zI17o)#lhK%c#uDu>Q@wg9+s9ZL= z?m|C5h_KX&=bOBn2%}r+XQZd5fl~->8?P8wsI`i!=a~;^O15Mq1Fdr#TgI)?`LS$r zGXw12tVRG(NRoK$qEbvVW~-twUmPf9>me7ych_Dq%&Ty9vH!q&Wv7+c4)OK?M(xR; zAfZ`T+)d?|CcLQ++iX}In?)a~IP;Cbtz|o^89l?l)4Kbu*0oUi*CNqi>y6OB!ETK+-HEr7CQ8-sC(KtuGD1K?<0r3UAO9O@;_E-d-m`i zX!SiyhBVWyXb4|e#Go57E*1V;S@#lQ?R*C7yW7jGuDr7K32ifAR|bnEH}CSy2P1u4 z!$S?ryye8c4Q*54>d%6dg4PDA+nja`kTYf&IMG;|zTvdi1B-b60 zYleT!vRVvvXA56&mh|@MOszZ6Rs>lir@+TmTla3~FD~F!Atpy}s^|}H2Z4-1p4$cK z^<1#PSC09)KIdGw*VS?Jt3_zJ*nA6vvck#^ue`e%UN4N!sx8 z6o$k*Bq@W~4@2dUkH_G|CGZT&AcbT!?#d|T_L$}IL~#TyToCKO!)_^1Bxw*;%yD@Y zf^iL@(WhDBX72VlfJ11GzVgm7*f}L`@ zBd^Xrj&Qt$ia~13Zj2OEY>rKFyDnPLvN_2<^+oXIfjXTKn9PIx&v!-h;PLD`&Q7#p zpLCoxbO;fl$6%MMq%cxaEhuau(R=2DRW9!GR#+0wm0on%VbGfPeCh3E=-@tV;Q?VX z{E^l2+}P{~2SnMC?BPCJEyh|t*Q0VN*t-fxGWL7BYHJTE190pcW^aMX=(OH>NH zxnB;pRF%oy&xqEXeS9#2U}{!@g{>@xJp3rSD&XaC`#>e6W833sn9v3Sab_4xOsIZ1 zULS0$IBJ5(6Y?lOcH92~bj(0}(;B)40~$J|p=bn38r->6jdzBVyHmwHM~z&q#*C`I z1LBHxXX{n0Os-S$C!jFQFvi;DWBHjV3Q<#OC9oXaxsr-ts~FF@+OE z$hyOA9CGl9pJ+{Y@Fu~VdvilyF#yLAi_f-k{jjcheiuI3uoQCyk)x~n!9me?^DCHC z^kGC>6_8HdY$23ok0mHL0_r_>*$ZT+;N( z_ZJXu!KPk^<$~`?3LKx?S#<6PcvWgi8MrzqTxFr5j>gg?h89i48TlX-oDrTpA@#;R zdJ}4`o&y-2>eXl@xz~ov+|P;{84in;h&mLLa5c)iO-t6ZGr)7ShK@9|D4{0CY3BQ& zUpvW;$Ikb$vQ4DKQPbyr7$&)UrqBG!i*4^06<@KRVObs>7?rfw#L?JH^? z?Ah%A%3^(EW_sV}^;RA0 z4xu?RC7Gyjv`NMN+J$Rr!;m8aWjv4oqBdo6$VF^#8S*5rQ1(<;>~G4vnF~Aq*(b}O zHw5}do&@O>2BNK_g}J{33Sv*0L7(?Z+ETwo!;#0gM~2p+5^c2%_QkDu!h)wUYDp^r zzSb{k?d>L3P84hC?TPS66VHhzz~>U@!ED7T&&d&AvS9H;57^HO(4I1!BvM0I64bYZ zL*YA8ZyxC(I(ZWhNAWeolO#ZCO7~^~NTm^dw1m|C$2pD%F!vK&oP%)k2`Y9DUz1;K z2T!EH`;~naEpPXVWpyw732)X#2+xBElEO|=({CVkN`>$c>XgBpmG(D6guebsO17b4@{*J`1$m_Z!X z)fO&dE!%0!*gtrt=dr(L(WZH;Yb6K4^fUdt8{CnUogTt?{3$Fn_U(ybU1W}S(QiHp z#e?S=Ax4q$ng5ed;wiAI_3)^Y_njC-;M9YlN` zMwc)db^4w$T^Q`e7?nVd4Y@*(S42JJDFXoYkeP$n-4gt{Bug)%M`S>19H3Po2F`!s z)O^-*ZOIBp&c!rl*Q)8oC-zqHfcHHigK@RqcQNw04s!jJ?TzWUxYt%9!#`*cg+rOO z_eE34>F8|nAU7KufKp6iQKEI^oko$efh?H8Oq z_q*r*;A&0^Q}i$KUHTk;$lW{hgZzTYr$zm-8E>B@LtM7Q267Apd}>!^ z#f7@MqVX>?c|C0uMJPvKMtiW*U8;}W7!k9Z{kR(M2fIqodpr)wM; zBu_8kzDs;k_t$~@X9r$NQaDa=Ki`I)ek{%$GUY-s$7CiN}0jdSfy56NOh zOgFyp@rmmF=zeQbhnT5?`YR+0vJc&h>zs2q8lIuCs|u_TCGb$*-7;p{=E2{zDTzSh z;pVG)t-1Zy+$Gy8?>LH$5A6huWT_(W0uK9UwTdC`HVlLDQx2$V-8p4AIBAF^C%5Mg z-YKHuiojs_uh9=$=~cduD>83uVkDak7PS&UTLV+D`DBS>4?V6J0bgLR-QGOC0hL9h z%l;P0@OWTRP^ESp`^L|9zb9m7$K&7cEWz1&R{VqGA7IQrHN{wQ|8H%He zrF32Ga@h5zC!z_J={pV^N(IjfAatIcr>iI_J3OrZ^t(O)KEu@T`K+-3eFfnUC;Wg` z4@jrufuZ8k*EGLpfe&x3{jP?2ZDVrvHzrerX*dq=L~%(Bx&4SGbW-%R)KirIm$<`A zxYJqTtZ(hu{}#f(y1`$&@O|O8Xg=!@c7P6Y{1w8kmt`eEk&NXJ0~#{YaI{tdzH+-w zc_r67GmO;Nm?PZToA=l+#_Yt{A zoU5nqfwO|};u`P`!`vLj$-`nr?AH1G*}LYqXjX?|%{A~u4~gKStED!!yt$E~*zty-pLcE}H4Zp;ki zhHHGcI*Br7W}S_5zPBtt4h|b~>vZeoEuvn*wUsdioi9ym5Xs^{phEwIA#$?10%}JSg0;pOkPaFgU4bNKqtLGal}ghYL8XHrG7E> z0CvTYj6QH!vJ#Cj@%+&q2a49(L&({F5s=J=qlnwa6h)X9<6hPsMb+<|klVH89O_%G zIa^{`r%g=J6qnh|gtJJ1CMX2}`PAv`e%h_@B8kP$W-!;9hWLHDgrxLGyp5JT1*8XIJ1T}x_jQuhrVm~bzXQGPJ?vu?(JJx z^$-9)n#h3iA#?}TshmCXWb{qopWXJdw(Kc#WWtb^g5oj>B@5CYlWsroXj2l4h#{NUW9tNo<@?j0f%uL61CjiV-vw&PPK0Mr~1xQj|jqFHCgg72eqa13%9= z0}k%KO>pST_f%`>tQszJ(>^JWM6yoFIQm=#K_dZS)5fiTjn1UgWEGPI?(fswJ0?P4|z9#)-Hz_iz=C#T*D zj{~lJ>eIGwub~0S5&Kq|^hfpHUKuYLQWW|zJGnkScQh?%auy`{-{e| zZ=jkAyI{h?4iVUl+;;7+D)^;Fxv1{gqo|jSA+c4%Ex=GA-aH}D$YchF&0sVk$4QlD zks`&R$;H^Oajt(6?Vv!FAtUsyDPt6rAI>h90x;p28_9q-=k6>OvkhVf(}qlSlN>^h zB^`B&^P*~*@%1$ZP#4g z(lSDY0JhDkAzZxHq(oKJAYkeX6FUUl88D+qGBs3a-s_mJzpuo{!UnY*Iu@Z7cfRy% z9NA2Y>04f9c%GObnU_$OIap3VoZ2yfhVH4gxhXHTs#^+u;@oQ2jI5(``IhwJL6t@5 zrB}CESI*1U04pCQeqK;_3}^nT#Y^!2v?90LzG}r?}8{>i= z@R@Z~eRvLUQo;!#iAN;n?^luBjN(8 z>DA&$*6VkVLb<9eqg#G}n-{@+KB(Qj7fvERtAihNCSJagv!*GQrWETd^qSy!aHLuk zXg#|;n#$hoJE-I8Z2BT^NLF$p;$u1~+{#v*ANSr0T<63@-xmY6)IGj%M~vsVbbUx= zEA#mw`6dUvK{1SD9=N}iu||fUK1~mVusSzX8zO;Hl3A6xt`-KwTrADA!q|5`pYBTI zh(g(|V`r?nlA+Jmh$~q|E(s;Bn#6Uz6okZzjP4*qg>)vekkWqTVX;UmfAJ(*ZHG{e zmp*qA_oIu=XR^W(eL|y{Sh0y_&sqYN`G zaoOdFA=N2g)bKP%eueyES>>RP3EvOJQE;o^ne`JxWKfYgv%bHTAfiVHs#)*=6kE&# zWZy4FPtuXdx;|&AvpU*ZPcqeKq>V?W? z$Ze7^(6Z$O!rCjmyjrLNgz&HX)>GomRdn6PThDltY{k5fmIdpLW}^j+V${rrqr^P6 zLdQ5gic|)73y;B8gEIS5^!ZyzOPCv-8_P^en2{R9NSDX8*CSeJ z={Ul}tYb`5ldQFjEVE&HsoXLwxi4W^yDGfdf?9X`|p3Y z8Ehex6JdP6!XU5-$cDu{Rt3NO>nZtswop7q=3#W`v&NLK*%*8_*VA`E5<1uqdniiX zL%LY%e3R55l8p=7*0AoUN`ks2vt2*pMGde@`!1`RneD|f$COos=^z0ag4pMt`GmtL zyDg4Lxd8{h?%l~X+G760^=fV5pwk%>Yyg63`V~$T<}3!XM_KFpMw!&Vt8BZ?baT6v zi%J2&Bba(()3uvUc7c?!3nW@TatNkxUImlRQfl&Ke5a(=8{Tqv;&2I8h1|c%Kl^|H2UvHy5#A>DO>AIdKE7pO`Q-!Z9pv(Ug1Rf6wkFay-y{qoyT`Bc7GsO1P$C~hlJm9_qe#o zb2{k+SBNLBjReVA`tE<51uhY5>F`jii}v65RpUl*-YhkDus(@C3R^GfuM)r50)?3| zCA^y#iVM}X9?G9RUd#mnx$(*?)iP%=-UveAr%K8n-~xJ#W)Ug_jQrFa%(}UnT~QyC zh;!h<)ECw}r0nNHr@{QaW6HB69F%Z7%{Wu5R=LR&Sm=?_2W8D{MnO%u|> z@yT1M6gTP^2612coB@v2CH5ec_F`vC4qR3+x3z;`AXz~awyQFp^aFBV>>^t&(gfTC-=n-ytJo>N}5Y)M|EGuo3>l;zK?uEZDh#ErPPF&V;n z@aok;M?4Zu&&^DbIdC748RNHa>$mqxk?*_F!w*yMPc@}K%rW5k+@J1^@{R8I@h&gHl$IdnvB4am%AgV-(F!fnS1dn<_DszJ&NVVxYQmqJy z8I1dV?4t#;PN+jrHJpN|EU$am6 zxG4G8F!5lHk-Gqx^9McS$(v%Apx%7VP?ZQ z18sG=Tj_Y`aq;b^Q1g$*Te-Y8wJ0dHE&)LY{0!yd$sddg+3!)U8#cWrIjhxoFVzG+ z;CtjcC72GyP3jhNsobUS_;mSU1#C}UR9)B8C8nV{7cQ(Czp4Wwwnw}yP1|pT&V#GN zWn|z&rR&N!cv@R7m&E{mK&rwh8g*g#1vS2~O$nIzSlRr}`xYI0t|a}`_h(k_FMS`n zDyIL)I0O-|tZH(7q%mQbn@Oe-?RT|MTZw^k3LhyV)zlJ79U03yS#C({XSfESxFT#m zRy*B2sgqB{jj|I=XVx1y7952<(}ShG(RIUG9_)JW)y_WxyMb_we2)@%=udy^gXa+e(Fh z3p8|#&VK|yx*WXMg^#Rdas~*MNT2e@{Rvb;Sz7kGz__X7SAGV>PTBS#SR{ZHZ`zETgDl##}GB?H9_~cr|+x z_8TbW^0dwfO*8iHQIIOwEiD#%5zov%C!f-*e?qBi)p?Y@jPCBAroTqvX;x)+ zcFv3h>vY_29`gaud4>V0WA-8Uh^%_Q7UM1msvUx^oyvMU0FFfa*gcou_k&9CDa(Q` z0=}N{GL7Muc-8*1qtJE;wc?mxgbjITSSgtI7yLq#?j%i|@v4G)NRr?qkJB~*Kf=T4 z*HBS@?lV;VKe0R0spPOy6IvdZPzUo7hSQj5WXm0eW)WHPnXW^fQ|Kpv?d}OcvhFVl zg^0~`kzYT9jEF>gK#GR;&jDuJ#dyDujtlg{r%|S53rK+QLCaVC98PvW@&wHh@|_oqHi;9=MGnHtc%t)%hmYx#%d(A( zeLSx@MPPqi;|KW8*&Uv4{Uc_!^5W@Le}G3MiN0bg*Hn?G{(;k=@zVkGtC^hb-aAaV zhPV`4Kq;L^cKCZSc=M+Q*rZyTl~wS}EnkZCcUfj5vx)%$v1WbqUUi}m)sSk`#pT<< zpY2RPckB3y+>?67JJJh9YjV)Q@}FmEIjk!CytSA&UtMUP1P4%hDnQ?{33V8Xfny!B zw5~6_U=Lm&qdnQ5sJtGs7j7a6{aLL4l0;Bc1k$1@pc(KxW0Ik-2TY!e*OyB4y$b(bF7*bd z#mG#Y45WAnsBV=YqDGz1*>7BMX9;bPz-LuwGlJ=WheaGX2w`z0xR-i$M)nxGV*e!Q z2V;J|mQuwS&L@hnnT!@lZImuW z-|O|Ur#YVt(24!rNeTl93iWZ2g``PHRrlw27oqzVj`uo!v%xWnptrM24o6SX`_-gS zP^ap0k3#5mi~hP~rVP`i zMq{5rH(PUReeNaAVn!)XGvtPnc=)9xdP>adiS`udqw)+Cs2@CPfyB$g0biSnq zx?{EC-G8S{=tcay`EJJ)H9Z5BP=6^Y&E#o+Gd>j(j!RPVzM^O-Ng{Waf90)P>odAI zXWBXNUPxU!TMhGEUeL!~by48=>i~5&YTDZq%9$4U;4$w73jUP-l9J2?9&75$jWTaq zAM?&2)sGiiOJ5H>fY0ofZxe-iJa_->(X2LNajgiSW^sBKm~Es>2Xu4*nCZlg#E@I^?ctbqR2A@F@CmHcMW9 z{ulr4%`6XC3T)sNhe0trc(&AHxg76cx&w<#uY;6}fcA12S}!P)wZ@_%gMpB|2~5n1 z6@Dz^Gef|HAnW4maa-7o95DeSc+!#FI*Y?7*f5_ z?SwdNE_(T3I2rQOJm$Dvov3Y1z=+%ARvFDOXI6zcva>P1FXZ`n+@PBJxCPxSpkPk8 z37Xq!OTJU@w8cLRG}VV68;cko)I-A0bNrgl?_n!apwD>cW7sADbPkjw>!8JHCif_ohcO+IAW`r4m{zjGh&-7`548-_i}=X92GFZWGTMrZo*Lh;h2^o zwpkF|W;-rhTEx^D5s`mv%MS5IUC+}u_`ZzjJ8Vu_bOua1mIt*&&w4rvLp_vVID1yX zp9rzAyLXQ{&GJ4Vt!IT~Vmfr@Ylto;mfA)SHqo`G_r*9AAlI za{$g)8-wvRFJ)l3J?Dj2hLz!2`F&-=iO|%P2^5h%l1&HrtybUT2(BUQT&bG0zz3px z;fT0nmJ6?V-2AHI=f^qLlSF600KfzfQg6PIXf+`Gqjyw8%KOc)@U(O*v%N$?lZgaV z{Ysu7Q9`Ykrt6ss5;D@MTSJc`^)pqIxFVPRO=gmMB&f<2Hr3f>%;^|j;OdI=`1UoZ zwJF|snD|Bd;~Ye4+a0}csVom)Waqm z>05Qp+?Y*0btJ;igkB0g3?VqeEIqir6=bTr%lv7H;MC0e09gSSB%k1?KAlnijjj8c z)W|H+BHqoac+wc{Ac9-f-Dr)<`eQB3G;GaA=yTU;|iz=FVY1(}6B$O@OUK zxT^254`N@Xg<=Z(-{DnJov1@uRN2C?F!?ycTmmYl+ zs_!j77@fF2<2dc9rv7hLvmB*{yW!P6hMZ)vU#X?1$86Pg)50R!&R2>*7OS75PWSP;e z{I_A$HhtZloCBgGk?$o4V#G=uOz zxzr#0-=+-yZ=L*KIP>vw1HXpAA7(=(bx}8IEzjnxFb}~RyP`79FRl8EhXXF)<c*ZxN4?eGE8-jN$~rD zaqi=jZ^FnG-Q;;+MtkP~Ju2iZ*cr}V5+{CL6PO=*LdW1WCkg5vt6Lq|Xs~rQw~QC1 zzhjr58AEXvLSzSc%{C3*(GXJxI!D-Oh}S$W63YpsQp?gGbXwB+Ug!lJwYU%j^X42) zvI>F_ZExW`0to~xn} zZAvM1P>NqMOHVK!fFW28w!ZjeYbB-c+9UCZ)6}6dr%o$QXr(>qz-}+uHT&S;EnP!m z;{Gdng|4l^*n%*hgG1x#rfFNUVNY~cKGNx6-@9Vp-z=gWR}glBEF?RW-leO7!R0Mb z)(osXL`1(v0zR87KVh8O8!a$I`kvX-XiFipl)D?ly@ZJ^u8(8w!j#K&ji-P;7b817 zlQh3q_=ODjZ;DAag$EVa({fw&)2}R7&?YQ)J+^mhk`n|r_l(W7T{tsYi|>AqLTcHrr-Bha329aUKbfRp8QLzt8f+iXEBArD8v ziEqI%hH??rZ@b-S`uV(b!CD73@=p1 ze*UP~^~m?{QwF}KRAdv5>7|sR&g{uEW3wb6xm!6h3#I%1{ajLa!dhTT*^5yVwmJ^6 zImDQQt#@lMBvS&muz6$La>3vBk_xTYcPGHy1FDV=9~uu}-Ej)!u(7@GjVs8LUI88! zuHXDS-Lr%)Nx=i@na2+4c>4`C*PqjrER+g+voW#xKE^dtY%?*&QxPd|Ccpc5^JrXq zrG%W(daZo}oj+^6?W*oJ-*aj?<0FQA4Li3%vmLw_g?aQ%$xT~13&BcRAF*hl1y#%p5Y!{)zbT_ig7al*>3?6 zxcOBc`!#=vJU#kW1^Z#B&?7vtoV6@JjT=~}PK55_W>k`C7H%NQWLwjG#abCLKOTgFrns-oQ zx%bAK<}%mu5e)7=R}^bY)OM2810Z+Tl+RKK1fNcls7^}I8B9lY>o}WaC5`T{&uf=* zzrQ}c*M|H4_K^^_kp0_-@UPSGm-y$IoQ(hR(Bu&6A6YH}ioz_Qbh@q(*q2%XlHXtD znRK8x?)DU)DF6I&`R5V%|6cp{bavCOSOgKw&Zr)3*14279dB;z%X;rf2oD>bxV!Jw z)t}6>o^Itn(Kw+Q*B-GkQ~d6(FE%bn^JR|CYixao?$BFSSa-5^S18d%z(U{4S628A zfWxQgsqh^E4!o@=lIX(8fxNIe$@=@NH{2!Z(rmM~q5hv=f2-tamE$@qoG9+(B%}5Y zHBN*b8()x4Q*-_2Ryb|*zc+O`LG?dd`#-kdzntmk@;{yF`1Y^oi7)VEb#yBzt^N=-9^J#%?jk(5L|}3dUT7Ej`~20smkh(?Oa%M zM!tEN+en5wy+MlR7(D}9DkTHu>m0q*&FWg4Z`jT1nuT?H+M$KLTHT5%mpb;I!_oZw zAeoV3TKfhYLE91rE(#u5&RIF2s|1Ujq^m^8&dkA7V+@HD>$UYttp~Z zij^XQGW6KhbU%Wc{SH>VXyNU|WJ%}2rm*l)EAZ~QWm!Y%5|KyK6*P-pZWl<4quYthLsbJ`Mp%zZk^Fi(b>+P znWKUhoU^; zekZ3$)$$NsLmMvT1|KKD#7np{dm~PmpzTh)%o&9R}$qb#XR{h*JCCM_!?QSRA zlXpDdZr+ay&0M&{6xDxm{o{=UOJ26#R5!I$&1^vT2Qo9PROyeKj#yKH?XW5udDY$c zsi}9$VZIFFOGneYclWvRZ~n3$sXAD>#oP8l{hs8VX~v7Z!OxS^wMnV0vwMwdq{G6` zXWz(_Qtf6XcuU@%g-x|uU~(Im;nJ)WC3ybqM;W!wI4$4N&pf}k;W5MErs!?EVVdD=Tg*;HVMAAt! zDI7`EVM|bw7g;JzXb}weQjQ)x-~MR9#3M(W^!5UTYwF>P=(Hq8sj&b_@?`rpidf5Q zHZL+X^=;cpBm}%x@j1H@?yK!Zw5k;ff+1AbVz)<{dtYaDCf>iyXa>8RSbHcSHklZ$ z8fCf+y18Nf)Z7S4WT7^c{bcj&MVH6s%G-AbIqwiiXk?GV=RkIib&rTdO4&O047j(d z6WOL3FWQl&vHTF*tn4(Wk8)q#`$-Vp6YKM)a~>HX0-Ifod!iV1(RZ;6#2i&{x3skG z@k92NrHD=G!Z2xZVQ|si^s-<2a*~X@iMdA;zmdoQH-LAPna4Vh8)5^xU&;A!) zDtx|4G1g3fLzl5bq1bu!x3og~fJ9 zS>AdjZk$h%9_H{sL8EJ6G~Mkd6XNn`7y-7*9kPx~$oqkQyECNoL}S5-gDPuX)=j5* zP4^u4d$LZkHBZ%4jcp{7+v^q)F{%*YEBkf=9frI!vy+k=ak=aP`N<_p%JjH@GqSn< zzG~O+RkQ>E|NY2r){t`?6gXX&bN(U?vGrE@XDAeU=~=E_+H)(L61dsp;3;FU5}53R zuTm$J2sy3%;`ONCsEVA`!omJMdzG7tW6SGwOizhF%%x38%|r>By(^C*ijQXhFi@9i z9YW6<|8Q5kKgM)e^thqW=8Zu`f^d`%GJS$2AysgF>cfcOzC$U$_=mSwx<4WxX(!!m zy*eaC^VMy&ebV16EePjvd$IRw^DB5at7^Z>ZD~cGTi&@L=DD$=*EG5`C2B8!@#PxBL}Daoj~9C%tNiB8F76dl9q$|O z_f^yiCI^_;V=i0}mb*(}p7gmigGqzZ8)dRa6wJ+=&JqYnSp2ST<3q=YnOP7V*jt-^ z_*fZUcv)&FplmUy7l*a6=RO%$Z@Qjva;0FG&Ct1Q|ABDI<9B95HfT{#sSo2HM;qPD z-H+#&!J!nGkGm1>0=7cg>-Z6l4*X&hXsA3GY_L#=Qa@s22aS5eYS2zcu z#3KUe;#CTUheTl8Ds-TIC2b|BKQv&=E5Z^vk@9XTdRE}0ur6pzgI~NbK&I!;s9nJ1 zh> z>7a1iIiq_#4$gbKRXt?6-)k&6y-Jz#osKa^GucPC>8}UT%8WrJ-J4r^nvPM zM=aMrmc#yKD=QgWsX9T3ITY`5apITJld*Jgbh;}bi2wP=x_CUiod4}|*)s{_wpf{~ zt>ZY&pZ1=mt8E9;cc1iT%K;3Rf*+HOz7?s=du1xO^2I)IwP8H2ESguDizEca#NOK? z^1gK{l3{e+^x*z<8>MW8e`J1+sD^Ei7ceA zP>+g|%W;0aL0H*EUqPNZlOCOcd;Q)&5)&G0dLesunS1LSp_VyW`bF5w#;bmJUg&7{ zefae0EzIpOTJu>9JdG8jL)Q`-N$9HM3m^9yeb?ejI^?RmT*J9Ju?>uQSewOhG!hNIe zrN7xjRtovI1ZBCLJzUBg6f;y;)`x;k(r>ZyU(qLSBQ^PPi;bV?nR!UbE9N$?DPI?) z&Fw1`u@~8s0v_?0eZKJa!Nse}$iUF=&@1;I82=Pz{Fc<$*1SO?UnaBFcrh3jdI2#R zc@0T@p^N9H`bD0Sw%D|yXF7Qg9j`jYURJO@lRd;Gy;H!E_`!bDz~ zEmZf`Tjk#Ds=E}=5szt!4lM#1uPVZ+4A6CVrHqq=2phiTx^!J_r@w4S(4KPnO&Qf9 z`(5m$0>^s|PfzuuD8(`iE6U#IK1AketeitW(6)|e%F<}z#9<))}ea6LGY;x7?HO!(~uwOR-Y2T7F#W zqrR3Ze;LFnT_~_HcEbjFSLyL3#`gF*MIsa*&9jpDJy`Y5+FR{(> z#2jmm;qo{I%eB1i=RzMA93)$P?_IJsP>gtczNb}^N-glUgnJ>U#r&lvb9l}*f?|r~ z1J3!ooF5|_zbwI>39gC`y4Z{x#xe98&HUJ2DA{)`bo%V$^f}ppxz@?>r_U9tT3VK? zDV|?Tv{x3I()6h44U~06Pp${@>QKEDr>ZxXc8}XSF#PdxHrnUS%{zCzUHpvtkvOr( zcLKlon-zYttL271gj262HldNhaEIsN<4S?LCPG%gM7q@&fmS5@Kye{YdF$yR-VL%f~W z)YIzJKkCf98$7!5$i~R?g^k&i9alsBLtoYU5w6>^HP~-HH41ljY&HjE4?5V3S|vK` zgR!rP2cNbcKQ>j_NsDgW{!nG|Fl;+5dY?{TqWAye>@CCMZk{$#oDkdt1Wj;v zcPF?z!QFxkI=H*Ly9aj(?(Xi8!DVn+p8qT7-Lv~%XZQ4%`SR;)y1S~o>%ObHivNRM z|8`*K9{-AFvOkkd*=pb(pCj*X6al}c@R2{oZQpJt{)QwpvdLoPH9T3jt7@RYxvS!U zOf*($@JWw8MSpAIPH~N%rQuni@|eUV^3FT8?af}jajTuxMIj;o>|An{|NVGxN^qAW z%g4Fli1-ZfHgoHIh2HN&YfkEzCHEr}DJG_+_S|sS$RCc!itDLC+ao97l{(ENi{{vc6&s<1F zdg+iNFEE-+4ptZq)+C9nCRCt z;}Am=7fY96^fT%5w8!`)eJ=M266WZUoPrZ@n8|vS#?9&!9f<_H;vxHNyCMnnd#x<#C6LfS6+0@A*k=4Bq20_>9&X>4 zO(|sgQ*SVF(CWh|Z^|+UBSq2kS=g12AP z90gE=Qu1r1sq`l^${8L?MePwFXErDx;GBq?dBOGHkfzk#S7NR+8!Q0Icn~#BT$Z5& zZ_XK2kGU2#okmBV#!yeO>{>5@N)BLkgkgPtO?{gAcZ)xt#wd_L1!ANR!yP%F#Ulae z4T=)Lp7o3cU+~jyO~S@k2~P!WGy={XLghT2p?#=WPmdLtCG%Z{% zb}r|YYEAK{W@=36zpCRFUx1HifCAzD1Y@ZBSrcwg2?Ky`v%2f%mDwWUSCO3f({H;t z%3%MR1;6-j#vV$6Z$z|)x-sgA;Zpc4p}}i@WQxD76WfaKXOv^RtsC%X&FrlB!3k-| zafGh8#+U{jChdM$^fmOH*@xa`eS($4T{r~G3Pe20pF-_~UPHsZPiYl%YJIxiOLwC8 zG<50UzyLFX+21k8JQM+y6xmd;MU)iUX**wXOQbB3!DA%peoJ3So&kuDi(S^ahN#?k zG_yc^^it_{riBe)YF5B=%jF7W@UN^|G|^W}yVnBuU^cCUB89Y%S1myzUHBkM3sP~) zeFj96Di&M{4z-eZT3EHELu7S3!aj5v=o~BAr;>c;oBekIUxguWc4}qK6&}v8Ps^5VrZ5KrzvE4&DArwG^s~ilW zD*%uk)niwRHj#7}t>vFv(x{tKtkMU6{7A?mL;vqN_$vsqjrbL z608mA=#8>!i|>}U4BfkIIz>dt*%74SDxgJr+$b=(GE*e=>TUx{dCoFSHbK9lZ1CpglOOV8O^VWKNf`-+x&7c)eJ`EmZdOny2hrpPiPd$C=;~3vaov& z{^Hb5@q5YMa9u^d@QBhTuQwLlnwuW-gk8zeQ8~V8wlprMs-`m4nz2{^C6~`Ks=inX zJwXaO;3YSQh~1wD?&o*O^kLV}V9a#nRzg=)V{24UijpI*0kZ!4(pQFOQj#_va79aI zHOzqIpwsT74HC;@@i*mspnMN8Z^?WyV8l`jo?+F4^c4|;oti*b+zB&C1`|Rpb1oQW zQ*(3o-Uiq<{FdeY0y_EhfY}_Ij~PD z^!-Z0e3HTT{!}xPaGW1Rke9#Gs2{LwBB(kD4Pe0u zjj?7-Cq$TD>qn!lR>D%RRIo3xi)2>cunK2$Z*RG;@UTwt%lt{oqdgIYS1f(}_JWl2 zfL1warQ+svr&DR#!|8P1C_MqcH?dg$WBl~`;gjnnmkj}Y&S@O@Gv1a5U(?wHglxi+~*Z!z*~e8RtwzYxXV zX)GcLC<14sz|qKG>Dmji1=z9qN;=hUXp#c1=q7HHGPZ(BSM8-L%&-m8Hw= zGxd-`|OviFG#_nTPX zQD&i_Xw*IvINHGHT-Z+Qn~v!tszS}>>4v{6EWQFo)FzMLdxc2K3yPeuo7#|IgfMvE zY88vQMY=RsN=|!>8l;NPtAJj>bf%h^fFp-gPg>V^{?i5nPOY?4x4{0;aEUOj$g;hI z>FA$Df!fu9)Jnz<6ILQ<;!A@RIDd*UT1t@eWXlfCXluyr!Z1#Vn+1OUuzmWQ#b3o* z)ySbXxEvmHq>IM=jrVTb)(5DlIkVa3Y*KLMH4JT(ClZh#AtA49mAX~O?x#b<2>IJc z$K?|iVFySL1``%j{?7V8(L^GvOZxl%ckOsEmJ>m%-Z&|QV|)PlDk>n~>Lb7I>{~5Q z78{O*M|DEhtx0zg13<&spN7|EzjS3XY~wMZk!;=z*FXK;79yJg#F(8n3UaTB_R;s( zd$6VR$#Hd!3xdKT72|}+XLDZZ6J(9-$>I4%)<~^FJ2w;_h zj+~-bgU4=JQPsB9Dx@~`pgq{gY<2d6Usi$fqr8V^MNmY^a{rG)qV}?{&%umM2N2U>G6bi4nUW0qH>NEg-77YT3kwJBLEaOR~L; zAbXw?9X-lK6_~$>OV!~XA{!9ZDyhOfzIR+)@7*Vj^W?{S7%6|sqlwGzqTE_=(%-uL zyHM5XblM`F6`Eu8PM9^9f0aLr&>RQ5kmcG9557;2V z*kQ|j8mvo2N6QOAQ||MjD+#-o{6SHu=C{R730)TWuk>{ERUM0_=t|we_FnX>HI6t> z9&J4Qf3fg>fl~6OJweAHJS3FWd!qTby`_AH!1T2+me_V+s7M8zQb>8c?6qw!Fc09y z`@msmU7BN8&rXbW)@U!TD=9y>-1{r^rbYqMt*O^E^x!9^oU6eBeL-#h_f~=sn(b(! z=e<{Towok@m{Oke=TBDg#{QBzYg`Iz$=av_gy3l*lP)qenSjjxZ+1(5qwUOduP?s2r=&1T`*o}Zl_nD%o4;4_3*uWe&7YiX!?^6nvrBk$@O z@y_=J&4&WC72hxDT=&9qdUGFg^oWHQJs4^28bw4KU7hEzao#6jz<|RqGPGi}cwl23 zBfcYbdaC8U(#6T(AB(2tLSM$PWUwjw7}!zI#1AYqZDX9t&2(TpI2z!xbrjD&*$>8M|W$FGgdur<7PRp z@ze^!Msi*2{?0%+zvxk*n&lf{kB`4a^rqj;-tb)({{>(9*p|4C%Z6zYHz<$!LTI80 z;dH$jD=SRHird;$dyCp9#V>x(?{rDU1xmpi>f*lT4lVAHSgCd^T_w4}Ike6>6SkIS zMWCZh3TwhaV6`}e^@{DGUty>FuWNNVDe3Q!X|&J=wK6s%1N4U$&%nCe=X2h}`|cbc zIL(fOzXsipw@G`Gu8SRz2b7tKut!t95;6-~@+iRYbntq>i2ErlVtpHvca0>f0Qqp* zTOtbndEmY6(ivb!k0Rn;xuK(J-7Wn-C~K*O>{;99XE((KxkNWiNR0kvBah-QlSmjb6$gjEAqEbbFOd>zAuGY-PA(6QYD3 z1`?!s2GfSm<9ZK=pR{V46ml?LE&I{dR6x|GlHogax7N}9{UhBm_m91{&JR+s0g`~({UZHAr zoan11Y%0lzdc%TP@22jF+1DLk!XpNb+kQ5YBFBvXO+~6pcgx30%uXGycHo)*9g^8^ z5@I1IUoI2#nL9Ow(AvKFZlN9ek05`wJi>)sT;fyN6Z#081m@)|h*v(K_rN7htwkeYwvz6-t)K`?!E?n(ZPLgvE_4bJqVYAD*O&+ z{vf&A?XIf>l1;s<9kBiJyqZIdTv~PHsBb2F3wnFRYdl{nyVr;Hfv6soLw(o=C4E*{ zBNLQIu;sV=`YrK+w|J-SnIEFH1ekq%#_ImK0)WWUY~4nb#Wn4JR~+&g43qMB;OLE&_ezZ`7~6BVr~3qisL(_#FK< z7SDCy9MrST2aeYy5;|dtysF*1(x>kpu^NuVY0zCB+%6{v@gzzVe4kPxW4z}jqJe!} zv-#__LH<>Yuu2AM1RxA5!JCk5Ot0-1Qy03J7ub=Ga^VzdaaTc~$UQ;2{9Y%m6CcbR z6ie82rk8?m2trHA@VU|6T;u;H*Q)}mQ%@g}?pjhH{^CeMoHfD!b~2rII|>T1Cd?>D z-0`RpxF{ym(*kix+AaU?5f7o5QwNolr$uQsJRhz}%)=08M`m*<=NOxORzJ?~-c5{1 zo-j-F2)~P(cI4GS{kW2)|BO4V)KZmBT`XR zzxVFvT(Kd8w^}*;x(U>IVE}-E`xz1li+dgY1iXypR7Zb>Q18+%G zVqmWZAE!x5-H~5spp8?Uz!DKW22yw|!Qgu>Gwn!W+-9_Xx?!E?I&9M1nTsSNX0E7~ zJsF~8K2Y*W_Vv$l4c~=(;gwFB&2Rp5Q=vzTyn>A1nj0X$L0} za(;==xv@&^syKfyH+jA^OC%R-cM2vSQR(1OBV4pI>U)TjJIyFpR^fbx z2!+>DyzCmdn)flS`iKQa;Cqt*uIi0qxBo(LO47=jA_@sJ!L=bn{?cdf(~>vWTLF23 zix_yPAAt#M*~81r@UFzNOW4eYc0Ow1#Xwc1%EFOOwDHb*hvsjj|Dfw0@q42)rY;MC zcYVPPJ9EfVuD|QQ1`A9&pSbV5Mx-^cfuPqG9i~Ki5zegK(GO-PRg~5Shb?CFDkeN8 z@(4zA`HM;A2G)Ko8JL!rkkP(_R~R#|JWW#vRp?Rv+vOGc17TO23QLcUBB zs!vz%NbkDG`ljyX!MfWy9NmZt)Z8z+NR3JMPk$>ga%4M0S(31Ml-){+c|C^nfTtoN z3*2_!`ip@b(AtZB5l#A1l3EoMrU4bj5OT`TlQP(JowRz4BpqXN97A_6_$Kp=iVYej z-7rvZVRW&NKjwh68?MjruBqAmHp3yUZn2!7UN8?r>M*Oz^YImiaWywgV)@imng9N4 zU!<39fn{O$Ci`*b8GAhtN{REV@sJ6dzePMg1_H(szP`*)rG0PaLKB*~71Thf+w-rC zY|sv#NIJd8GP;r_zbfm-R9yj=<&+cqp;TlxuK&pGfPC*_P0%9YT#P<`NWm&In7Hux zcA^duV_WvPVPT?sr<9a;mzD-4G}!ybroX}W=|s-M1G#ze>BmHhBpXyU2U`}EZHaGp z)7%Sq7U5y9T#4|Q5D##M4Bfag93E8X6nnL}VxuK`%uS5@aXo zz`#=$wfTmlhbh-1Z?5R6@YD{KNOW&Lg)ZeP@j<^A*9jd=s2QKxN`wsZ8~ZowoVkY( z=38}>R;844`w1b94}7<9*CAKj$KJdOed<6;R2!gTYBOS~F^e<-TREOr;wL+t(CDgDVv zDY;d&L{tMLlI+!xTEIj_^gu|xUNs^p&qn|r%`oV?EHh2|1ZQ*>ney%=bj8l`JLg>6oZ zTZ_rUEO4;CvC}6vA$rFC>yIC={j%p{=EP~NywNZ z{Oy&zhRl5VqFPLErq6To;@p-qZn*XIe~?S5Z&AZrugf#NYxm~H#+dga_r+~)8|Z!W zF&#?PQl7O_X5sT3LQon@`ex@8y0>0Ca}YuaI$r306%crFd^ zspw7>T#1x}i}#wYds*ou(Mr7m)=sf;d_G90c$<8)1fg=@MJi>w3RYR_Bm|3@(ok`~ zjK$+asI58m9heiZq*YlV&N5UYuoXvmj@PI~*^{~7i<0L)twsX9jAg28>~9BT*9%AW z-!RWA7>91+ww@|hl5F@Flguawqjn~O>CL&A8U8{8F{|?)cH~h{sqodt_;~~hN~3RN z4JBUMAfVlWj+1ZAM0|P_4hBl`KF@K5^4*^fqwt&1 z+wD8eVpf8uxTSr9@kd6`GNM8a<+*779tsk9rcTKv4bqJ~oB(nJY!DJSvd5Rv+Tt$4 z_eSiwDHOp1?j?W-&v3#bnY<^mB4FGit?1m%TKX+IugJXSwMB}#lRjBq$}`o6VR>=r zWwe!UO(o0w8X;*9tS2h~zU-qucrB+XO!mSlm6XOW7d7iAVW@Q9PQXF=Z+)vk*2x~X za2%}4;LI*Rc=jQNJb9!z%Ff~{M;rL_<6=-NlqPgiN~zf@@hnyCx3m(`f1eUsw7haXl+;a8LFt;%iWEv-b6%I zc#EctV=SY)6zh6Q#zggoF&)ZM`-H%JNJz!IQ+=0Iru?)i(JR)aw{Any2IYwo#^d2E znwmv%mSNq|;di8}u^|uQtePs^qdvmbEF&Wth$9Ts4-h&elruT7MlBH5F4DMqV^LYX5QKHyP7t!xmKw5Ps9TAYE zD&f614EqT4pMome%o5ulRq#2{9u_2LWFl=YvJA<(fd9#h$pBLOXOLRFRBd_p!mr|+ z>jPHC)f^BV(dEZQjsIeZ;$!V)7&|%AY(vqtNg1vuab$Q+DMCKT*kdRXx~*?7-^%SS z7qmaP1zE;$=gp#BkK$uFFC!(_aYb17G4`||z^>C6!*i*$?5p#dEwRvyzTK$vz>a4` zk4`3^iOI8fH&gG1rj`{mLy%qC1xN9@H3o(mUqNn{Y^W94w?+ZbTt@kpzvsL?HZ zGV_Gl*j@R0wn2hX;2NU4Y+W%E$TM0??HWy$p|F*Z8sptdJZs zQfeT|^!C@$MaIoOyzqnckC8I-&<06 zg1{ST1Yn~ABNrGRA2)V7am83M(<=PIZJbXAIDjPG8|%=2RLHAwHa4-S7m%c5ViK&V z`Eqj)3NO9|CA_X@N$`5Y$bMmk$dQ?zM}kXFLw41E51d zMtayQ3gB`P_@I{)@K5Xl9h{8G(*Mn;I~vDU@JN+pO2-_BE#j)mUe6riy5$w&TE4$C za%}kx>~0;4SOTo%uCb0L4L*Ri4#!Mk6qfpO-^!d1hK0MzB z;D{#V^k}F3V0GMqe<{e*yr79UgF#q(Qzs&A{6GtFd4)+kw&}@#U{?oF?EfCSGVfFV z6dRd#f16p-{Qg{8@Qc7yN{thbNN8)g`#=&!5|w})v`cWYbh&jyDN@1#MJS_(^_^DXhkre5dk&P3Br zaXrxj|9cpJb1VZm;r0j1ngub)9(C;>H_P$$hk|FhqWa=071t?yq}0t_T@SWnvZ0r! zhc$vB5?k4z-fgLPgWGi1+ciF1sK2^s?5Lg{Y3e_2x$wC><;!agCytr_#DLeCHwBiO z5A>_vugK88b+>c0o#4WT$OP8U-H~(kWcst$+z=xwF8#T0hyL{sf)O9!Q*3PI1AInR z?_9-v2B2zS75*oLET{Q52&qAY9`IDF_nbZ?sKEas!0NFaI>BxK{z?C>@Uu$LmwAN) zw2EN2d4*ZV5t{(-_3rXAlZ^S&?oJzMC@84>6XkBC35RoN9IEA`RZ*Uym-&}!&N@5T zOD+rcZi1-DF@bWHc>z`xh+)m;oIURqn+z4RfPzF zH0|(s6Q%1N14>Qn5gD~))d1pI2&v4_+LG&GX!2YE!{j_0+R~g=fEf$o{@^MC5n(P! zavh$;oc^As6JkY44ccO_uDAS8=0! zlOqKbllwnW^Qa`${-X95SHSMlNkJS{XlrnbEi{N(URGO2I8w@0c-I7EP zc@kfP%eUCa!2q!fA^7Qk%s&4_B!A31wC?QUFI~?#&yCK5Ch9#i=3!-YgzH?P)Ez^n z$d?qin$$8610&yl=}xr70dtD^fb_yBQii^e_8>c%YVlU*V94{+m4Az*F-!exd{mDe zTKRdVJST(4n7)r3((0NxTYqPzJq-9C1}-i4 z{rV>5#qHp^SiGWOlgRmhppd5QDnCWNn=Wbt`D7^bs=l-#$DYs5lNwyhBIV|9Imda;{E0S+x zY5xhJ>t8|$U;TYBf^_Mq!KuB9uK3;@wODeS2mTfAK0wD0T7Z^#`H0XUS*F$Hug_Z) zVVdt~HqvlR`mZ+diG-z2AjS2o8M0cwSeNPsf)6&dq8B?z5QN3G`mfHFmH~P_7{RD( zw(T-?s!y?{1(KYBE0(S`#v96vTXRXIhL1$)$&CR;O?&%YE>PgB`8=-vvW* z|KA5ga{gy9Br`M1|F39BPBt#i|KpPI03j?%g29#cy<@pJicpf!&-qXu#GyfCYT^0$ zRIWH{vo)lbX+PLBSi~kL`!cw>z%7r`gW^GkP_B}kc0%iL_!Jet~zEw zdv*X}>l?f!_u-R2r_ev#NA6fOaMM>rgs`BR@No91O(HATgW0WzRr%XYRt=Y^t7TIm zZyivQ#`E-4%j4}w7~M7$1Zq3p!MDYvp++wH3HHW-2=WQmq-yk`H`Zo&)?ZTN*S0UX zWtM%|Iwut46 z?zZ*YmiJ1;A&ysTuRpZ}A>d2P?R_Cx2OO8Uf_xB$|$t+SMhxltGn(p(0BX3nf%bJ-=mq^CV$w>jIJzsv2CkSm;A&)bA5v3 z%=BHokCCr(*u8I=HbXg)rl&mXjMJCys-ZdhGu10tLynMyCOYH7ci#m^V%^=&QI%z# zwsc7|>23`Sgrw5E5K=k$+kDz17*jvG!j7=@rMVPGwsC6r=D1{mOv)@M6WJV# z-_+jbq;2Pg2zq2a5Ry5U^F1HJCd{(zk5I#Fwp|B-4ToXp()8(2@k1^HAPwFdI zjyA+k}Zei!~|u@t4sU;rEX1yva~Li`@T=Y+|6wv`Dkff!5mYr$usk=nfSOZeXS z7UF5d-l?IY{f{JpgH+K7XJI~Wv|v3K_JYiZ{_#j|*URgZ&piws-9uBpq{dk@;1|@Q zCC(0RK4k-p37YZXDhWFtUKqx-)eMWi@YkkJShW-=7t6wVV$as}`=~Ld^h;>KT;UC>-2`Oz= zIr;wJ;QjSATo#$Pt3``bVT@w@SZ<@#@gdLjXI7-Y(+1KSVx6mV4nPxi$1vJ1&XG8=mj#vEFgKil0mxEY%OOia ziX2W--;|H*nL7uhk~Q<<>xLCYuV{OA*TfWkJhcfTzaZ3@vJhRju;;G~L&y!?3|T9% zMp(CmnU>A0LAPD=8d{cPEb{)eLTR6sF%o?)|Lpy_sz67~kfc9p6OuWZAsFRTGk(ngK5?*Y{Z{9`yvxsDUJicV*Kl?e}_)a?uN=Rlt zpTvN(gmm)!&9ASWHUU$CeS5&8#?Sc99P-jDA?Ie^*qwy4S6{11Tcv3$NAf}K4N`j0 zG}p+t*a*a8eH4_^Qm|C?6_F!3rGUWa=9BL-g2cwr1|4;Gdq?w#2_Kap$xzFcdIWCS z(;^=tZ17Bf_ZSzo&e;NfR28d0wBFS{%n$Dg^#asz?`D&EflTY(SWZ;$QQ&=otU*$$ zyrPZx?)A24TG<+*CV@dGKiAvZP!hr%&z$xhiQC8?gjBkM8{@vl>;el>4AM}}!1Jts zhG&XA%H^+{%N!;rj0i=E-vFiN8dpbx0ie#7|4XSK4SiJU0ft{U`QFDPqt1>1^=u%b zgVs@g(4PU{*iX|H?S3pvtD`6_0QCWzwBti2--BZgt5rH5%o!Es-Ehc1jq{ z)hUk3fYl0RWNk|Jj8u%(&|?WwH_S4hj*VuWu`(>F(m*UcGb+EAzX}h{euSKj^_5wW zYV@pZk)F4p1<&PRjjDc#KIa`w2xXu2-M#a3PM5hTWeB2>>qE4nav7-$p*iIKlf2u3 z`pQ|4X~j2=^KDL7xtr$5N#P^J>#0aqlTxI&Druyi^Z>djDP?$HZPD=UX$BOMvE|Ia zFGK$I%}{4qc3kvLd57A+Av>@6q}zWc&(~SXt^9QolU=@8Xa>pF4vjnMP!Q+ zM~K);EgiFaIrf7&kz2Yq1@SoC6>-Tc%eqE^fSKC0FaVl6JRAs_R|SEE<4TOa*r=T& z3|XI8(4o1U)KQJt)NdsB@dHSxvN;^NvD&|~ZHj39#>=$*36B{g&eP`v!3J8vtGP68I8S!+?$ z!YHI?6?*FubMHI^m)~Q4f&pnRsJ{CPQQzu5cP{O|ihF$`eIzl0z=34*W?1k)m0}#p ztOuw26%MS&2}`MQ+}&cHJ7gixuj} z$Rg-?R9QT|Qjo%9P}Gu`b5-Vl8HYt3@fD*%NBNjIXGOfHz?1HCmOHCS>zSyfs2t=z zTt96aLO-n{;Wu+PeNN0G5J%x>X_IZ$&2(DM_`+#N4o8(9U=t<90`IHy@47I@b@KP~ zpCV5vqH2&=T_t#w-|wBa_RDcQH#BF81G7-MU$3aBYAY%beinb|R@`S{c7dMn@U$aV z8D7SilgoOJx?jl5iP^Udtm9ntW&b1AJH!7NzBfTE!q3p0mb+Fsi>bH#>#>kGFIj)E z+hhWQqnCSBP7y_Cqg&sAZ~0fz`UvLg(}naf$hxH%%6x}w{5-^lckaN3nmY%A%DI*=`Qpx2GaBXSJCCnj@9f@;wY^(=pL?{_ zte8nk=A91z%JxN3AS{;E(m?P=GYQ-=>Bj_@ioGsZ$_^aHe(xlM>>DN_k`HgrFjSl{5Y%!(s8j9 z0(jl*UgFsIw4UTD-0@2goGo9T+ShETJ39VG(jNE*jQJ&=K`&4XXsd{PF-7d9U6#K@974wry174yLXL_jLy2wzac4lnaS?; zll&u`x(@earx#<7{8*Ww4#e56)dAZU8-{YDVw7)>o!a|4*rAM+Bas8hoWA+l*=5vnwkkMeiyVRSpCgr_6TQ#Oec50Pn` z8Hdlk%P(oGgw%7RzsX>uhHLm~y{f80Z;9uddIPc)00u9Y5y*VkIUI~L?{KVBd^HTX5F2JOYSGzw`^#Zrg~LoX*mC% z6B{Oz{3yfR+pB&QUb!X%i1K!YH@UX^>vp6Gt95@jHnC%jQ$_ese7T5NSMsw@i53R>(m)31WLK=nY_!Ycr|Jm}kQuU{@n^7)Bd&6 zl6OJdgkRW9U-5wC+}De}TVSy3V|qJ;EbV6R8eko^{IDjf0%b9$k&grBm2d@!oRx_t4LipoR3_@ za{M#zH@lpz>exirIPoM%Bt;BKN;he~6B^)~Ot{vfC_iFnPEpErk|!KUVx%Pc%{AeT z243s=rLx_M<>!QOlf?J`A|Xp%={atwC4r!&rr^j+hnuh6--;}wVh6YNEFn|{xLUm8 zyF=OmJ&EEGFKxp=7~w99*M0QJ;D4*UJs7Tj0yOXV)h~sFAnyUluFWD6mQ7>MaTfUX zm!n7}BnO$kcG6nyWis1ES3;uLVFF2tJ>u2TSn?gM^WeueM|>9VD%?asM7Y_XlpI5c zVT*j^0LOh>{U)a6BfbJ?$+uSnzIEP(fry_5R<%Q^0WP0c-i~en@4*gzK^-IG8SJ^I zi^bA?AquO`6-e{zNTkiqhWMgDj{u(nSd0Xh+sVB*I_RLGSE+?ut7eP2(Z2THlR`pN5V zoG259;w>RqcY%=Re!W+H#C+nF1`GR;>(OHdr#rTO_4U`;`9b;Q+2;Q65!%OD8bbD> zH-Gj6sX1;~(ThI22QmgHgZ&+{_~5HF9SL6}%kU7V+rr9tF>K(k>y5)bLF)Ea_iKlb zz=+(lnsk7VrsO-KTJGUyG_}Ba_P1h&)cFVk#CgIc@iR@VeeTqS9Cl}u<22oA2lH^! zPWpbKoAQ32!i&c15LnEYbv<1^C=m|*{;acC#%hzpvJCD*^pOmhi_Pa(tQ=Bko2M0I zqSjMghAl{vJZ055Y9w;1v~NzrlbgxLv9=mxQCZB)pwF`?6Udi@{I)b+Bq@!g z*iAo6^e12F(V7~(ou8a0$`7m@ZuMh%V7}H%ODNI_;be*LWza%Zr0xzDl<=|0X67+! zCB#PyPD7@k@Y(azD?2_S|4qy3-hk%05zDmTkAeirI<%uCaG}XnGxi{bnGx}ISV0%} zu%lit9@g~TKVOZYktppXPUvxZKaK#C@k7>o7MbA%QMHwOg{tf0ad!NwgsrRj&({t4 z<$y3;V5V8gLLqlDpDjC)xI9Qv@Lvi9p*Que5!Qqw<9duHvB%hddi=!$WXTMu7@rgD zA`~Oy2`pQAe}MCP@D|(Cs*Ge%v7h$^pa(24bGKCwCHrJ|*6el_@f^*xB14+>&tu35 zK5!7M+ZNZh8e5$5Vm@M8JrHL*`cOrOeW5^%*QOI8#X(?XZ-~u zTSCaIOq=#$y4c9P`NGu$=RwDWvDTGmC(lgoMZTSZQA?Cq@Gjult{ca9^!Try4h&9l zoWkC%y@|s_qhyh&k)L`xw;2re0ARw*QcL4MwPE2HY^VfvpS5GC^X@| zSbjY%A5@9?oSkWKWIK$7O(Tx0m6`|h)qSzMarpf&-KxFiKPfto=O_M%^jg0?RK5EL3y@ zQW-NyTAwg_lcTQ$roIfCmbjvZqv|&dDZashML4o1LkgR?(`={7y3~;DwPQ~W0=Q`Z z(bbZ83Gg^mpi^AefH#bDWoFf`RfAB0>9~ ze?pst|M0o>WwW2RSrATYSh?>*e0*>fN9xMp^f@1nrUHpawO=}ON$n1nDK)&TpoX|2 zp`lhce(k8pt?l`uh{QXf(Vs0%1H^o`1mC*92@a`G&-#6Jb;l_kar{-r$h{?x&8x|;o5R4!?+zx}uz#8w1Yns?rAIa*Rw z$}y`;pP)S87b`rRW00!g}A{>b&AZFSM@Xc!B)@~GKAn;`;39Wr|8M_e)OZQO!VZC1*L=$k(#=)=v03?f2iebA7)b zz#oUct0$PINKv5bq3}Ozwy#*^6MXki0oN+@(N!7*9q;_x9g*p0ruNq67d%#r@nQVf zf)zA4ydh__a00>{t7D3`pYB<@hn#f0o}0ZZ#6AQ=HHz|_Py^#kVn^Mc{MC}t%`MqK zZs@v?*^+#{Ab-UaPow*!fGWfV-=!62A0ZRHdfL+)zx2_(kb|Ox<#;JSd1zEU^H9%G zXzq8G6O};1%c+sZA;mf1V%klmsQe&tIMrtNc;R1^6O=dP;Lq!4AodW|pNw-7)WGjM z%v+C_@Ue~c2SMZ0-A2N-zMPnYo;6#J@covaHdV#P6rZ^x ztbyUG;;AC-Si-*xAPnW;59|%WXL-6;CK2|ZI9Uu6^Ge79O^|88brV+TLD7PzDtDl^ejqY=4#fk^ ziUqA`qp=!`EH0mkhHmycHlakM5Q%``a0MnTV>D)D+Uhq3Rljk`Ah^3*a0n3G z-QC^YJ-EBOySux)dvJIAo8+8(&%5uw@qc452D`hftM;z0S~b_4YgH9ryg_{iNl#m^6^?Xbj7MA%-|FoHF5=~!rs3xc2;%zMI{d<=)Zfp% zh6OtaCI|PSwgvhnrQ&NBC0ua;Cy7GONpEKgf^zmPUJ;sGt_wxMtm*3+-rP!F zSYs|)hS9f@RuvdJ*wE81q$97a=<`p<@QF~Du+XxfC7?BhzvaCMoCs-oux!qHIZw!U zvTUHX^pmh|7EzI5#Bh9?xulz>2*{#AlM|Z0Ws`xF?iO55ILtTz z0@%yO%x}LmfeTt0r@!Avne!)?T5um6kkV7jStG=e!Z1TBP-CnNe zu1XG0NH%~`X~4>)Nw;my3Itl;6)%2$XM1)2g~QBT67H4P(0?$c8D`~X*&}?;42!Zd z>=m_$d$bi(#&v~5P*jbk5S4kLn5`^isgh*ChNhUyx1`gF{-)35GGbuQUKKfcBqK}7Adqk{Qpm(tx`~a= z5Mj*gVmKBEEiPwwGOqs66$b{)jyqL0jX(sYIH=LxRXmG6fmQ5jf_4Fv;bg22@%llv zPq0yZ3A_9Y@cJZ~+8cT*K0$v|PgySxB1s?-r9>L!mF?jbX_TpNqrK3|O3 zzTVHU8ioWMQ8`<8^NDg=*VOU28U0ka*x=t;NvVIx*PNpd+mD$1sWN{ z0>rnC;g8=IlM6Rj12!-Sthv+|Nvm7o>`V6ZV~2k&6Nq^{8w10JWh)LEYso+}tgMwB zv|g)xT9j)ksf79qY^1^*VttR<4cgo{Sn+L+?nxB&+yNNPNv0g8ccTeWHEI8DG-Je} ze<)JDuhHC+HLHoB!Ql|1klmRWqt2hm#y`P4V&AZ6|3MfV0E$AW3iw55Pcm;iu$_o6 zvX~fq^pw})%^DZ5mhu*$a6Ash;BWMSEu^=fh_Y+R4bjm(%C7bDZHT`82itC5LjCxSReZhi>IFU(Z#oL8Cc}`aOsTmO_~w+# zQ846mUVTn2E97mtoL(%Urm=G~uE)&uu^A5Qc#A_{xFUOuI93o$e80L4)cEBN}jcuXcJ=_h10L_R>`&XtLMB4CGso1Hn(cJ1^%yZX)YSu zFSqUvX37`@TB2fVczJf1C~2WRKp$}P(0;6Img2~kmWzSa)*I9>(mqTDdj&v&UrOND z)g2GD{!+7;QUi+WW`9~&SXAg z0$QXIxW;~7_ph|vMtq`+*0+nthbbP}@&P}sZEB7Rizh@wNN-ax)Kpcju@OPEpInza z8Is+y(RaSX&UP#j35C_Wp#=edKfHQGybC=!r<-%e9Hru#F$Nct}f4ED{K>eMz)7PUZ#r7ym)m=eN~#t%W8H zg}cXQupEoyZgN}zym|`{){zA!VP%rd@U`W5<2$&4v49Pqv2aFmG7uY4G}D>{lldbA z#xzh79|$FK!{;%?#LRi}NojPg-DF+pe^n0f`jFNReIXopR zf8XPrY3oI;)0wZSqjJRi1@>>bY0$=HSUS5N+*S_0TXHG}iVCcNE_}YCGXas5aHq3> zcJTt-VELR_mc-^$HE!Ns1$ij}Q%!l%#3a44V13~AWdK*h{nrPaJhTX+081|4nJQUM zxFDbj2U0XA3a+ow@?D#+Wfa?o4sJN47di4KjMAg$4@ny9}+ zvgK_*{L@m@medGyB!uvgT+aQ|6*y`xNPEcEPHB|X!;Qi5rznOHH zL}j)4wiE{l1@ytDvnXKae5ZuGw6j6qIzGi_X<@5hNr)5qjsoHp#)%=Tz$ziZ<2!S*p`IKBjFR0qY6ax)J=2LWG?6Cn)jlZ%hwK0s#K$+8`f{nu4l)qGgaCUZBTuCLJn3iam=3XPWaextNy}1k3zWd^V>T{j$Z^$H~ z^Orm$Qa$yTRuNC!(umc#Fs$l#hv9$V+CuHzHIF#zZ$Jt|Sjw0oIfr_zCL4b|(LB-w z&V6~<*CvvAx1<2n69B)i4zRE~^CQ2$p)!wwoQ7xkN42T)_5x8{b-5qb`j?#1kn{tA7RL#86OiPPOVBvpjhTF@Mi$1k z@8iGFxSDWY=#8~b=(Cm0C$~)UyO#uLJ?+p@`JfT)jaNg-Zc?0*7Q7?gHb%xkIa?Xf zbxMk^2CL*9puGVBEQDWrJv)+s$*aRg@*=%{>j{kEVzzdOCUMbkC8^AiJTKj~Ox_xC z|3Jk-m?^Y>W8ctl0QPmj{Xlt__QeZ<39d`l-x!V-sF0ep#}j?B7ed`Pdj!%WoE*qN z4x-01WvQY%_B;3hk{(InFrh4T2VM9Z@BG6uex;G0oT<2&mAN|y5MY0Dq@ICHNsOs$ zqCTiG2`iW-OSc*(BEe})r@VsuaoU|CHb7lStiA^7F=!DZ`%fn3(fKo>KU;adw`K}(hH<(V`eN(_>9VfO)y~2t(Ag(2@r7564s&x-S*Tt=T@}#Za9rl z*;)DIqBq1To{+hurwgR4Asytk^2zJ<+T-b7JL3-EA9c33ekKA7%s>A|7wI2Wq&lPR ziFb9W4~4jp@$0hbf(qpER>z4dq!5`ofY&V02z(8AWA;#;U7_n+Sm#@6O-GDZaROUu zE+DQO<3oFvWYO0ydg@v<_`@s9{yZd*z07goz;u$sDZRgC0A~zBTv|`=0WvVOzIAq> zoBBRJ73w_G+G|`OY6bYpB=f)Nd{QPnvfITNU}1@-K`k|~7zvwG6En6-0>Ee)^j5Nkke0w%w=|{&6u4hzXRjI%;HstT8f?m_iu{g8yM+uKaBa7ija-kTP6fcBL2pD(8OS+$cv~_~j*Z%F(YdR}fMd`>WoK<4TaMuB?KnQJ zJiOj!w^5>`BqV=@})+Jd*ohZ#w&luJm zaRgj2f*Yp-o$fV1(!|G-Z&+{s`z*-s+;dXs9<8YUiwaa)*{?w)JcwMOEF_Srzxw!l z_1(h>#|HcQ=E~>Vgm8NX@wC6xLnVWu2?dsnCJ>nYo}jkjL*Vt zg=lDT)Sh^8+H7gL?Y`31mnw}mtA0R7h*PF%ch+&M=_t@eskn?^;I$vClmd%N1$xSz zL%r;#UfwrCw-+gk@l0CKbCa#8`{9ixNa6Ngktr>=o7892-`uS>=4QAdKJCQcv~Dil zW4yA)09?B&n*Vkfaf+HD{?3(p6TvTj{;FE)|3>KkgWfeneGl2&FLyC^qo@AO{hC2L zIR)ZSE1cV#^F-|gLWzpH&ZjiJl_j~f4E~AN{B91UK!;KNVtonDX;{V*GN5Ec%)F&fvlf}hSb#HQas9MAZ&q9t#q21-)oN^TEBc$@>YF`#jL4^-hUrWB zL5dq5Ryr2O1voG`l}H(y+nxW2#**j$p&@3a>f5DEI}1?_u?#eA2iH`h79Cfl2S$0) z5w_C-s`jOH{f&%l#acv)%M-7_AlKS=jsXYEMv|UUQRGz6K!9(qQHqvv@K-1p0@la; z(`yyng21%p=9^gm2m+%XAc}y?)p!o@S=5(r5f;)898!?#r3l9igh(J0BN$;^Pr#o4 zGhC_|Mu|AUH;C5FiRd-*_sKgNA+J^zzIdG|gOZZa3~NuoZ|zk3{j!fgdk;NU6-K z%rQURR8R5l*8wP=o_S(0B(wL3!~GS4HplopR?Uk>Xr=MEAt@}UGJ7PJeQ`e2MP-)ahRMgVYl5fJn zY)7CyKw?t)XTIsv+BfFkWv* zHX)y>(>3EXd~G018ebVY2|L60SQnU8wg{BD=P06}ULd)>LBa%YW;`Yg#tFOE+aIRN zTFA*VGAYR#a7pWZ;<#Wq?NQ3m3{uwQBcTqttr+hi9h9gE6$fw;0YBOeQ<P{2^-l{tGL$Y{;{_^%9joT&n30svonf9RKYX3YqzZic74)+sfr>)?vLjA zDr`)9?iw2%n|o65@+ISbB%zPZR4z3vo@oVQrtcT}UR~WPB}>&R45?F^+oIdDu0pxS!GEXV98J|Fb`l4;Rb_Y@)Di4;k=4 z5vU&bPuwb)fZfvo?AjLBPgxZx+S%751Xj<~%YL|Nfre%nxRh2-cGCo=mMdMfur=gb zt1&cY!8suCdI&DnA#fZc(0XEj0*Ga0!`0%D0>5KCYZ8k(mLRp;U*=M)+kUHPTO#-n z!-T{Z|COKBW(J` z33b6@eyBy|nB{k{t@ujUG=>}Yu-!9i=oTF2s|^(A)S@6uccWy-{wl_rcokf7->SZo zU!P^vF()#9WzyiWFNgv?CWGth%>Jqjt05r`T2ApeS>GBC!F-A$@iCqo6?iof_Cr6M!63DZQ zFA@dHstHiJit261U!^_GX-?0o{CA=~T0!{x-O$f2jc~zsXihwTHOj%5~{OE3A=8yvgnQ0eJ8Ubwhc zfX{uRa0UEhb$g1((ggQk5iKR=mjf}sZ|9jf0Mz!wYY`CZ(^ol+w=B-mpKZOp&Zyaew2gz;bcuYc==lUvY&LW?)sIzu){_{(p~|Efb%-!K7w# zYroWB3OFemxU~v{&}J&-kf$$RWS|#zUPg__E@}!lh8$LN6Zt+acRcvB9!RdUCNe?d?CNdPr4^2)>o7~Zdb+&Iv-3Oh5tiu+Jp z9)2K|9&jhEFl2BV5J*j(=5WpWP#3pv^)G&UoZju1zsy+$V9TTZ(g)JvQ5dU4u14G0 z{>fS0sD2#s+to`jBlEVE}pB5@cIUse64-wQS?GzpDUBI;z8##$-C#rHc5`TP%H2^*P zEOU2XjLx369E&URG2@)%Gjg8cR`cG>i^FWg=c8ct^%X9`5_qDHcnk6Mkwhtq-A_3Wq!^AJs(TKH>PGX(o+_l>yYJ3XJl#mdrb#Z7(tvOLl~2=&RaCRo1)76jEdJzQjvvKaqO&`Q)$ zBCo)7g28nEYw&mpL9L^n`Ih?~Y{Eo&z!+?&NZze{91nEI8h_LNan9IbU)nl;03qDf8@ zQlb)_wHDSDWr~!JkG{_NDGVJrFU{~`QL#Ah23n+O(?bdSlvGYsLZ)>CdPQ<*J^6QH zPQ7foV!l+o3C|iZ_^VYeAm}^aE6GE^SV!80+HTtC8S;^vmW*GU3*cpA3zu6s+BoKL zD!Y3|C__)!`n)G3Sn%4yBqVj;DrDRW&A7IA-tzUAGzEHauch%58NseTfq4R$4ug9b z8!PPk8_@O8!d}m>fIw)$a`n~#Ge^Sj&@?Wk;=unAvCs(fB?^XBFW|)~gG_(;J97Xq zgsdRSVUwqUAP836i$wqgut+BDNR#Ph?s9xAJDWQaD1| z?qUgX` z4J(ChY1!>Q2WDOvh**nr(TjVCfBru+XoBTm!oE}TkKTk|`Y$(xWtu22EF~CC(417# z!sHUC$Yshw6jBEYO2vodp}GcuNY5$K`8nP;9Npj?39=D--AiL&{&21QvEN#eM;wa= zpDmqp!KdfKF1fh_MS}a07lD>rX6ArxbDv=%qN0IqvhLU4)H~K&$Y0d^Mrg!uesPL< znT#3svjB4-E|_Czx8s-&8SR8CdXy>c%wh+ZpzEKcfz~-O@3Kjg`>ntu3-t2{=QrJj z9Uirh23@)EATej&dy--Q=?Ss02&c|CLtfe+!TsnxrGKRYJK%zujB)o&Su~j?mvj)a zY*AP}(x&{Pq4M(w`J$;PNXmjyXt%)DcoPvN6aHcPn%*1-P?UlS8H0OqX)l}KJv{!m z5#S9bUq>Xaok#3Jkl8n?Uxg&%Zae`7yKFa5idc5!hz>>1E`kc-N9DsYg*Q^MB7cX& zV94|^0C(&1AOPJpXk$rJ0W^XYUWxmnN~PkMyj+qui}k0+28gC2*vLj8UGsXW$#mEH zvdSYrS;Ce!UuUEoRe%z_=3Vrjg2JaVQTy%OJ~iEh|92h#*+nv?6v}L%j_FD(Ug5`H?f}{*s)r{{#B{~@4U66 z`JVKV*WX)3HaO|&fov_GHb?b6b>^c8$pl%h390BXBPk=qG^PLZ^X*A&^4XNbvdW07 z;?=WCm5zxDEf8tE_WJ0T`w-t?U{!{n4U(XA4)BZvaxmCoO~!$as68&3VsMw_!T^CH zMq)GI69L$#|8(qvh|GWemIQtZ03-p_H&dL|2GSyCL=fMPQ&C@r@cA7nTlSxtXb^9_!hLv<%2?NJEcC;FNa zS5!e&vGVR%o2|lGbuhE*2SP6}%&47ln6!kOpQx8~dC^ zuRM#1g$!Hw3@d};P;H8d12B|uVlN?H;Jxx70uveJ=IUf6ZM(u%fAWoi>Y5rrBu+9U z-hHz0A$Ors2?2hW1%RSZ66i?SQvgXKSg4cLO%uJzL>XfOA$jG0i4_d|U`@_&<)E9B z-+c;&f2Rc~ZU3O)58U2+8O$bjZn9?nm~agar%e~q6Hp=6ds$alPnD4(7{9W;i1llm?vJ&Wom z*m)RYJD&nlhUr_DFH^Jl2o{r;Mt3DmNNgo^mCG3AOkHyzgb(&zKDfp`kTe+!sFJ1krT#-itw9F5LuA5#O#rau2+!ModjbcNmY{&Tyn$11Va{tA4Bc%W zmDuq7hhR{Y8$iBvI?#jBnb`>31|am|_QZCj!Qg)|?fhR+>~h<`4w0%}#`n)&VT^uq zA>oE;v2V*$76h-NA8T81nNEe>8?zHg5VHv%I`CKz{AX%GLrgeSF7ghZ(;Y$N>2JI_wzk!K zvjFtK50cJEC2chS2MbdwM6qJFVUBX|Qe$q@ic@*lm6Y~_7N>+VM1d6HDN}o0?7JBQ zh7TVO0TM_L(oxGtrl(ilwJlWVd>$ycHF4tnV|30ORb}&0lZKwWgun!f)4T+Sa6}Q% z)r7yq4Ay#u-y!NPi(itj#mltj>4Va%ps-J_2vn#jJSFvf%C=GLH-*$;&cqres7x=J z^V0bG4bfcBqYazBi4S{t#Ha|K=DA!ySrcPcW&5>A`M%9aYzh#&9HGu3g$HXGKh-Wy@Sk*QpQ+@(jCE53p zlXp0c(@kT%bguzqTA9MtAn7MexLbd%klX7^>*>nuBVHZKqpzAM5gd#2gF}MEv>|ye zNC!0kiIi>kmphfEgG~zjrj$?pd01)4me|2kD1#Jm)Tnv7ht-FU&lu|TMFYX>NBq!> zJUu`ys(%H^6%#WDqvWnGZkO`KH|0hEPA1aQy&F$$w)m#Uy@L}z@rnCH>ijXw=sNjP z#@71teAr*a(p4{Q-hqA2r}=ahzmZ0fU++jt8v2vT@RnR~kNW^k8j9GlM;TIE1%j8M z1OZF;4!xH&v@66137w9i`zC$zo1AR1vHFK`yk0G8GkvESY51up-0bM-I)&q|>@>^? zcHj>|z?HnJ#eg_DpnuXn+;jMXZQ`^zC$tr2M!&!JfUCxJ?#c=Dpb+;a5$*pokXxI( z1^$juT{dUtZ#iaJ({6K~6fCC|Cy$acTp5yAm`nH9!Z+n3GMrKW|BDg&KX?G%Z?AB1 zhAc$?WdjsC+J9_-^4Do?OpNq@PUgh<|39s*S5CxYnFjj(uw4?J>a2hpbbl?iW|Y-T zMemh5ElWgVM)~E^6V2gvY(m!3jtjl>UTLZEg=ch5qO49_it)6rDkPOK17gpsJ{LwJjmq z=9Ww#mb@D+ro|b#pEXPI{qvcv)W@pE;A*O1uq;x3q-1w8I)Y-aUJ2o>wcz1Oy+zb+ zvaZkxmCOzC=x`%*hkPLp68%s!jK6R}THQm2)#aVM3m->N7vg+*Q#CA84eXwp#rUkl zZLytfB*ZYYS?SvRBHb?P5HW8QEdi31bxESHl;EBpHCE-+)MCb?$FT=`Ut{FnTzLYz zk@_(Z4v0}V370UirY-FZ{5x7^j>cJ``=I0@u_g6<-=_ETaJd90hKb*3y(3wi# z(*rvKq62t1w!|qa^bEwbB$qI|?W>!6+oY7kGZ6#%Qt@+{!e^5val$APedTQ}c`V% zbYp%fY`N2nC}XTJhi>z+r>n-=9Uhod-E#KI3m7w74RsfHK2Z*EuX{S=2=*E|&)3K$ zwuWr=D7wbJ7;QsIcuw6@SWM*&1|KcQ(v!GiK?EPw47dZ1k{%j&e~967F@^)H+NOI2 z4bxo@_%EZImiZr}`~T^zLzef`YJcb%85r8)&@lqeJ>)gAwUN}b=Cd%fv@q8*2OMGx zNzG?rYGEy7simWbL;YRP-bhDJT96l#T1HIE#sr6+jsei9^uG_fWuRwd{eRx=2iz5D zcIgeSFv1$2!0Y1=U<7A`Z&Nt}McRDdeNo{f+C7nSg+Eb8PUHmH;zp{20F!!4e~9<| z6uAZ?$0K#z(c1OIwXI~poII+Jh-1#QzP^9g$ow>tm`D$Ilya74vp3=c4)+R&>kH5O ziQ^lGXF1?MuI~o<`)k~L$lvd`y}t#|dyf43zpEcSFKe4gB#1Bk`{gIxj~c&A{m;_g ze=7Q)MLHFJSM=#mg?|uhJWg9j`Q2yFOfg!1cvS1{9R++yva& z`xhU=%ER0)K>N^8b-Mwz-b3pAyaLsjB>bU3>|IXNht>ut<@cRO`PeI|$23hAP zX7@R=|9gA1fL8u>;R>n&=o_t{n}8Ys_t@5jrt^=B-!};Qe}4S0FSPx2zbx1nvm=TA z{%iz2%9X4((7nPjKz1AC?+wrbS_1T2+g959BV2}+%a>xGU=tF=XW3p}6Q z-YA~Rg^7%#?DYXx-Z@qKj0OAqem}rfbQ95Nxp^1ePLH#Xa^bn&3_Kh*pZ!#mgMjGM z#uw~TI7cS4bhUdp-L>ILt?q6<(kWfQ?*T#hq@i^$d@=iQCD69ivZ!eKXnPOY#tS>9 zP=4p3h8*@r!+HC%FkziJHa2Elva?X%|Jbsculitp>bKh3(t5~L)NHxRTfG{6M>KpZ zi}HyAnT19F{1CHv6n$}djU=)K=SXozDpKr)t`NmkOurZX#t5Ia5@Js^cD`SQ9cS1Oca6Byj zE;8T2;hFk8HIXC63WdZ9I`dQWH1#y8+N`a-ezhhWA?k^}2c|>YEBR5GNW$c}gvh8g zFDvYyA&F@C^f)#oZw>-m&~h2hsfT#c9ccH#uYjL3Q*c0`%4_-zqzaky{-#r!Czr0C zvwIz*?5ufr17&e5*}PP_v`7h`eED<)+-NQD0nmR15ZS(j2a4Jvqc%ed1QWL(-JKqW zBdT!q!Q(S>>+;ehC_gLWT`eZpn&;uijVW9yjE~2aKZ87rh07F3W|{@mbt;_8VU4#3 zhcS(`H`xgK`T^cRCL?jpRW@6E6;EP2h<-^Qs1pTcvp*tPZr*7fyAqHBgJ)ym+E80c!I(R%l&3IK zh@yCVP)N^L6N@HRYcS9B_L}O35p_^o$HfemRB*EDUGb)`jx5Y&fvecfFZh3a{EFcQVq+`?+YPD>yAL zCYK{}Mpe~u+r2ETp9hRS2-4?Mkw7wk_1E50q2)jc2# z?x0_`k}n>%kdB`{xa8SZ@9|8TTI>M6`)iPTnly04=nRM}@J0*gS0lJP1~mJ%b4_=%|YYZZB7d zN%N)A87*=kOV%nMY2{2;$Lx&zlO*OC*niqHif#FZfrlHpMttOqy6CJiF{=9sXMZ>; z#J`q&krvFpe(<1r9vkL2X_gI)2Cz(kwaB@|m2fpj4-whpcGsXDbIJbxaFx?C2ZqVmt^mHx9f?4sm1(U?aQ=~|EUHY&9k7;3xr#oJ*OfYoB8zaO z8!x@!Nfglsb%9JDEJiZo&t97)QwD^2`Xjeq7T5mbEB9ypaACAV%dp3l@W@ZZ5*PK4wdZ|kRLz?MVzmQ^j$Fu#v zZavl+w^sKc3dLaKmt({O?#obQ>?pcY>w33rr=Ba4oB@mVZlDrq7rEcQceyUQouiH$*kA3exaOjO z|6;2tH?7my6&YK7<)*I1E7&O; zNQ%_S4`o!-kmZ0Tad5D*i)0N-M9U7p-VH3z0Sr7st|7#CbNIgYUl-gTYNa@p0xgae z$vB)$Gq$gftYf~FHK7Q>62Jqn0Ff5}GsH5x+U*QQf{9^_s4!CR$_||(HtVd1&*sAs zo{ZgHDb6UzU^dwUmfY_5YW+5fTXx7prX3$)PfUhS$88<^vJ9xxU&7Z1r{8|uU0+_` z+;O;Xvp|gaoiv)iqaXmHIZiAed$BD87`I*W_`BN+dn>yOxbtvx)Y9?Dx(o9}r5C|# zYMc{45aI|ARcMXf878W4LrXd5$kvX3K+Er?{WrLA_1pX(kfVxRMF|WtS{i^Ul-rsd zrLGSNjb{LE*&kWH}@z2KvV7oO>jR@NgE9le24435lGDOaUd8EhH4fj1ou#_rA!p zyW<~l;{i8!F^L-5RgX=>Y}NQ-5Egrq0UMMWS0&Xe=H%*x?!1;2?CUrR2*gE&GQL3!-U znF)UA>QJb=nyoX#BNP7l1s?&iHZ1kwia!+HKd*%sRHrfl4L_a1C@WK>*0?Va_WfCR z$q6MSq*|NKZ)Wd}4`p>|sKf~fgEqVUqN9N;ufrIzvH1v?C&j{>7j^>u*X z(b}BbAM9h}*=!|`8g)0CtCKS`B-a7Jq0+Bc}~|Hnw7`2%UATqbvJ#>)qi-RQtQj+oI)y(=I!xQG1EC zWYuPOGbNk~*^P~a&SHlWCKrg+3yl8eyAv!`qJ`PfTFb~TLXmjWsj9&kP??f> zA;6rH;Eyv^j+$kI?02J~(%1g!yq)>H{w0WB7WhaZV3V9)1X8(zoBbvxv%X)n zsQMQGen$F!+-}1c)CU4|pWa@v&Hm4eqj^6&e*Q1QbEPJM4Nbv;pDr$k@i^7LvgxzS z)`7mGY$addMaP4;-a-BAjd^ep(Ac48?CtYA|Dz{!)&~B%vpkhz`C?-*kSdN**N8o{ zB$e{n1C@L|lQQF6ywG&>lH1tOjAzIDORbwq`BvpQ>K=QvirpwEapCHw;I9|6-8t98 z!x{i!M7u2I9k-O^%vt+gGiXH6e6A@mO!1q>s0Ig@O4}ve`8W$>?nE8mG63z9<-5+d zw=*V4RgaFRGYc?TFrBiwIfGeNRVIAV5GtcD9S=fWJeM;p$kbI%Vsap_7Wi3F3-s;* zh0tUy87_MM4d(2H&rT!ElrGnFXB#(ncCM9{42(4vhYILEGve))CNVot8NS>&L4t+3 zxrn-%PSkX^(Ld>iG~()YS2Sq7_}>iIX#>_MIeLfZz6&Etpe!(v;U1KAi&2>Qi z^NYV-M_XDwJjsE+)WVW{5tU%xFYaIRKt_nl6b4KqxGKj=`7iVut;Q6tXK74a9>A;z zR3Ea)70ao$SXG*8-N@)3t@$_?^AVc=h%u{t#&3~sU{BJ3;A*VhSK*kQ%T1@KwZ=uk zwy$PM?TZr`Bh}bFiqVf9ZxJeNE1!u2Q5mUow|gP4on2gf2)U+~rE%A95m#;8AO}sH zy1bOjk@^Guta}vlB`~xEuvwCs$5YBhiRJkPF^J?>8+8ccMy|?BP^-HXrg(V1xU(#;mAEV{St6A-;*IFZ-qQW^72%(Zs zk9JRH9~`SA&Q6fCNx+UY!5O7#*BEHp$N$3Dr!3EX7J4uJ1mwIV0j`d>>(c2ta{H}4i2U}~qtf{X z^#Cf&9c-vMieD?$)y8vbuZMo|KQv!>t${)0saX53malAttA`BMa;_uK<(5&Gl144k zBU$jt+osC--xLB1J_7^XVb)X+M$3!`iJ&-2%JW%^_MjrUQH5;drJ1iOrWE?Ac|vBLgsy zJc+yf6k(&8m5R$%fQMUMsa>7}?39&xP#LHGkixQvszMwp#(^ zCH>8igMD+eYgH|VvRF*6$$9pJhR}Kwq4OPzyZaLQ836IqFHlmAnCsAzyXLmIx6VBg z007kNTyJn7yjpWGqX~nr3@8F3e>_!|FtS;3b@llzO07u<1Y(UiD+bi>A8A*OSWKBo z>cT+7-F_M1i&A5+J@(E4{JB|U1(hnJATpV9D-JmUu>Fz*dOG)EZ0W0P_P%zo>rM zlzQ|Rpib@1XApFaJ&IAbx?&o=p`w8JFr8+Ct&Ee8OBKkI;f;Uui}39dpnBZWtN>lE_fc4goH9WgFkq5Rnj*G{AWpKw)oE zyY68{6x)9oNWZN;oVB)bhz?y z$dEQm9EZ7a$){7q)UXX+n4cN%4#KLjMMwiEx%X~4yy*1oEo5{HxUJQ@Gx)}?Gg%!! zUf1p7@`!x^U}oB0+xjiO66c2ZJQUXfptR8YGQSI>k@|F?8o#DCq(F6cvVF33xP`re zy-M|M*=bncVR+<_E6c;nj0aLy_~C=*Klr|PLT}6eouJ$J-8g`-#7qFpUqj4)Q+>ZV zORF`<@j(tBZ7`v6RTn)kwYL$Ls$X>&Bk4f~s(wAu5$fzT(<1u%Jl&iOY;B*$^M z`CwQ1PC;S;{@CHG^@E&me8a;n?NNGzgN9=H_s6ui1x&Vm+S-&#axrEv)FAs4AN2+zdI)Y|J@wC*~jy?k`Q0Ktb#$9`RTXNDneTue2p z1pt4Y^EA5^%=~}BuW1dCc>tGXyzW%IS2z$QCQ{`LzT!f^hVj_W2XNC=S5>>o{gPoQ zG25+LT-HwkKIHCP7e8b?g<6%+Fp&(3=-?#f(kAuo%w0ZM7`h^9R#ZT~;OB5WE#$5p ztLxIaqx5MJw7bp*z$iI{@x1gfAQ+PbEt)S(YfN;!EF{MLczo{4Xj`Bs8Wng$<7)TT z=6J#gr2>VFFr5c1a*kXj*tTSC8DiQd_T~fN$Bg9%a4}3;6Sll&t_lf1i0HnSw<#Uz z7tPKsA3YTB8!W3of!`-%?spSnAIg<37ntuMGFnWp+&)!zYaGYNw?mU+XxGJmq^xCJ ze&pIAL?V+l1lXo?WU2wz-EEzYv<1b;6bb~y-d~eh@|2-rCFipxO4^sYKHJ-V`T3cm zh6N1{667>?MYwp(y}dy>1hlRVmezDBBI?X70BYT3n|$%GufZrFu*cIb0LOR)r$Av~WJDjyDC-8T1b=flzAtgiI^ z#XO$1rmuY9u+W|ggOL#d&}6H#(|=>7v9HT{(0p~{eb}LD0LFysnbU%Yc{}7S_9Pei zPQh2DhoM&T$5RcpH{nx~Z2+gMk>io+eL=r{Bfy@2Qu}(S>lC*^=Z`T2Sl{$^-l3N2 zAE;$@_#iu-w4fc(z5pNuiz#o$4+v`j_>(`*y-JoJz1FbjnOrsEsr>MD z_2T%D3=gkonA+q;sy}S8iL?8B)4$XYDx}o~rt^;%(D^=usM~(CW~UQA{~vX48CF%> zwT+4*Eh#M>(%mWDAkrWp-QBP#DW#-4q`SKoAl(v+lrHJ+`X=iA-1qms&wlsw{n*Fe z+hhIkSgbkc6=R&&InHs7YgP)4AaDa_YTD>Awoi`9h^gG~h$R2q6QD5FErk4L)m|w- zYe#9g+!hQmBiH3@sC5=}O42P_?hc*tZH9rN-nl3q0r_$lddoBFb=ITNRN5_yV}35i zh1XsFIH+c3mZ?mQ2*;)`dJbYY3Aa;)B(Zm2{wD5Jj|RfKUWD#Tar$8;u#+wiG!i;u z7CjHhiN+^6fLrtywh-Pg*xqp|hzS}6zA~{%CtxxDWZ5pa`SuF-G9B#1BLP~^$G(xg zq>+e6eb8&xuqHDXZBwiFDI2jpNSkg{2?bPfGZaKtQYH6BcCfVkWE!V(5)XSvuEkU+ zRgG(f^DBTVBQUnB^@1xbPoAG=>&rmF z(-9YUfui$9z{P0nkETMpZi5q%6BFqZA^?#_@kCq$lPUq*!V~m8?t1eS9q^W(KB6K? z$2rrsC)lsREZXuyL%lTGv)^NEW}+x`3Al)ZUov;XB3Ii^fBj0Ar`Z=G;EJmAu`FVK z$fj(nK8@x*ps#V$ZiI#snHlxh;o2w2Czk5uT>}y9>!DOb4kLG9%-t6Urp*j^FLsL` zPzQeK$eiJQx47TFx^_*}h3|;5`9&fOC=cY~T+2_U<*yWDH7cwEel%Kd@@S|x&WG&1 zy4SC=|1Z4Y$5i*94gjp;+75m4HTj_*X{?PzH#$ENv_eu)eXW%prB`b36E z+|~9Zy_FQLr~FOl=WY}DoPz~OziguZ?zin}MLMlqeqk=J=6qe<5OVUiM-$`)_ct2~ z0c@_8OrrM7Em4Dg=kDcl?6)fOvNH%e9fQVF@kLrPRlV$CfG$IC$v_>0T4dl59?xx; zu@St%AHKld2u%y3*eU2p9{ZXgg!TgCAw|!L;X9A72Gh&;kp3h-`l@U#0OHFr0Gn#qY2C#(-77 zvAz*H0H#YebW|dou68PVL!L$roWiH9-o;c!!3o=g6u0~GElXQVc@rJ+m&pc`%}0s1 zWPpQF2^P@h3OaO)G1G7Nvzr+-U_S$|lKj?x`g5w|{Bd+ES7^6X=G6MW9E$>g%LR%} zplWnPQzv`h;%E6Q7& z)?XeC4Cn3A!z00HdKBwytdl1ryTx01@3oyG0FvQ&8PbIVUb*uFh{pM#8o;y6fIt^W zV!V^j*%heZJ-<`;lzun1pAGVVW&T;lQ<1s{to|qW*E@XGub=0*nBjS{TYGib8wmu9 zdGUE=tp|WuLU6C2zI7NXHlibtO!-UY3oMJ^KZG=-4?Atm=YZCa7X%gC9EdN?K0amu0V*)lckBF{VE~z1ASH?f#1+31mfe2{66WK7 ze#wYH8sMLQ=0(!g0C}?hmAi~hJ%p%4ud9!Z`H=pVG<=jb|4Oa?$(MqRT0v(6jQVX) z&~T^#Q6FIIL&;%XFvx5#EoN9c_Om4LSHkcuYHtO~z}?3dQ^Bew{;jRHPMBRGA?JHy z($ay?1YC)YhtSWq;faWrcj~||enTJh4n5e|t6Mb!B^78s;<{}lW zCZX*`zCTkaOX>b0xzk$CCe@R(pM%+`Bzs+r-nS?y4tM_#k4g2Z!4{}MLHoWqN1PTb+L|) zR;HOZ>V7lH)!QC5Utipn8grwc8Z5~}3t2&u3Y`1-ej2JErxj5S5GI~E74-#;O24o# z8rkD8t)~GQ_1^Xv-OGLmd-6SPfWq*w=Jx@aPy!38!}GZrU@h3w41|*CGdAW(W%WKt zn#_A=f;6u!Qb|95)2UXp|FF4)O^mAO|c1Jg` z7em1m1tuwO5j=m~OzjySH>~{vKlo_1W)qfCXM#g6QU6DgfkcI6;yGLf-P=|$mXsvZ zE8ql?YKy#~hN$=PDRlb!NFz9piR4Gyi;XNaoTQ*JPDrg~!4H}* z2YV$Y2RPr|NPZyO;?DNyRPGm(losuLk3&NYT`6(?XbK%_R784Fd%wPc1rm;r z-~1dsj=i7vdHm5|Ur|k+8U^c}>I%Ubq5w&^$B^SY+3uA7J*NK~;66Ztex_A!>U}_2 z1c8361|t^eIY|WnWia&PM1TSaqlzm(0uK`=26_YUU$#3*t7d*s5@$V+2NrggP{qpA z{?%E(GD#rQx=b5`Slo|Q`m6cvK+0PF(tMU}Red@PKhwcvd6g{9Rk-;$xZX{PHX`C{ zi`5LEKv0wA$`9GU+S^R;YV*xBlv>`PBqgi4;7U$4-P0T`j6Gj4QBzZFt~XuO$wjW9;g`Z!S4-_e-_|C^@Z(zPr%KOFZ|25&fYeiQlHN7n!-{$5}BfWpr zXFOLcX2QBzhDGdTu}&eGE{f-Vkc3lA;+=BUc}yhK1(ir`jRk(On#J*`#$#iGrd1u( zu%bVXy%i~t#yr|7>yDZ#ZC9gW?EU9sfUpJ|+wP*2go;|Yz(7J|?WdxFmhDj{cMuo% z=S448Xp<2R=nyQ3fKF@LkPLrjCSf6EZjUbbhpTp#G4871gQW%V3<&2U4ob}jsFOKG zo#BUv1!s2L7QO`D5!2vYrfM$pfLX~|*+0KkFC+5kBOl9N0jEp*eH_fw+=_$e zay`_u$Rt`^xdqN|wO7^JIVq!28)kagJ~jeYaYT*3tp9`WN)feE=#BF(RUG{|A;~L2 zor$tCF~cihe%JcAJ-nE(K}P4dOKrZh8fo4-F*Lwh)YL}vmuJzLf?^@pYSJhpYTVin zG}s^tl;i82V()<6q~gE4sr=2+BQ46*=6xagUb}|9n3Pm>s#JdnZ#4^qqJ+^W2uP@@ zYF)r_T}1t>b(RGLd~+%@R%^8DL&-H~bI+dD$hfY+D`o}a@L~bPNLckR>+QXP1z3sd zZ_rA7^!jC5!x6*h|AY+U-xxrS0Spfl@Z%Z!-@pIM?|XsNIchIq-{amSBwZoZtNh^~ zIV6uL^hibm%l`C~JR0;3;5i?E_vshF0h^}mEi33k0Z7UMAQS};T?zfKHLW~NGPGjtd7|Mr>TD2|H`-$&-eJjhG zlC?~2ZR_OA(x#ghcN4ZGz$AE6d#@UhGT#E0`b-)|}u*aOuiLo;1z#)=7QxO3q7ES1}T zYkjIO7Lvw$nd8Lb>(mfie8t18kolA1id}E z^9`vzcYa*t{es%ZjbR^D?$?VBhEpC|)jRI2el#(&RDPI6IvXuZILINBP^qv^)lq48 zud&Fpp1XG&3#`n@pkWa(uBJJ;n?ckw>MvX>Vgy&4w`cBIM4=lGySF&Rhv?>VqwD5a z&g!4@r?9#OpJ|f|{^0XO2D8Y`#>Ez$$rTA|8a7I8(q7TK7pd87rS3!n`%bor){52# z#2l*+PcRr5gzrCDLZpkelQY_YZEZF-lAr25wNCeFpFR~`{sz$Y3b(2flmE-)Z%s)U zK4M7JCQDJ&^@>a}$QC)?mJvB)!P2hO z0X`4dy)}c>AP`vztwBo6-Q|v`hj4lO!ky76E_{T)?A~COQpy$YTN&bnbe_ z?m6B$YVc7y?)dP~wNYwZ=?3N2_I?M-=Je>|jP_lY?XVvi0%Xqk@XMJQOxxQ$eo z`2hiZ-Sen{jAr;5m2XYTk&&{3qfRl=A~O=Aqt#nxa~)m)R8F*tS@uk~p}rneap$0tYjrwa z80znj7a18fNlqil#OtvXL3RWg(bYu;1idt2((x|FacS7N+nxI@$NP|u#H&KURPH=1 zy47N7m6`5T)sRqZ78}FNvW=BvvW{bu<~KLCug~;K43wg>Wxo>E2?*p%HrSqb~Uv(%>*? zBM}j+eF#x&dS_^1#G=)R#@Z%0t8Az3r%yYxu@Tpkdx} z%zozk+a6+Q_-9cxkhc6mKLlw>rXTyxd&~wt%gm>f@O~HBBx12RMyUh z1D9uUk5&m{%ih&lO|{Z*)4Cil7I3c=4Kq5uMUyJe@UGL-QY{6$Z5Jmg;HczmH+FWt zzQ{=;VE{tAnPIip@;Gy3>_~ad&LzxVTkl|+;gJSy{WWVsqiZVpQ$=&%<IIT%|-^%9D*iVYKJ|lp!g{VWU9uj>l;*jcRxH2oqByzMku3 zS_4e!Z=zXS`Au!TKc>$aLU}2@S#+h8w^N`rFun1q>=gOU)<#$w%X(3A-f(v_zo^&F zX`-b$c+x;KcTnJJ`xZOM2rq||P9si*yoeZNwB73cUNg;Gr64L`xq(6kseQi5f$2f| z`rPUSSL1rOj9#m{Hw?e~+5RF5U|SKfcgK*#3C0PZ_=#EnFOU^^b43?y?09dRncQIZ zn;W~uIJx8;>p8H4XJxpaXQPvv5wbUUV7;sdrG>9$l0iDA>l8V-ewmEG2ep)dw*X5c z_9~IfeemW1KaaOu6y8aP{WAf$GN24B=pjT8gRWdT0iY(3Z0{?}4F196qPXcj&R#Ro zk*2#RZ8lpT*;Nugq=p~Qz^TPY?(n-mebEjlw;wL{GZl!A%Diz&75MZLY^~>)mjOCu zH5}_-v1W*dL3Zz6sXCq^qUrl^ul7@k8;|4VYL5k^$rTMC0&O%+t3|3qT0b$0SVn3K zRoPe00~~Q9-x$qeel4m`U)-ATyAHP_TNrwu3;05=NZ3_8sz3@;U-5vv3xHM-%9-m9 zHIC!h?dJr{wh`HOXUq~H3dq5k&cMd-6fEp|-BHkq?f}b~`BdC@+Scmh&5ro=y%-`D zU%3I*Heg$({1r{!j_z~lPpu|-coG+?#pPS?HTe8X>{7ilv31!N8_h64D&MaVDl0j` zny2kS*YEbOEv+CGUt1rAk^zxP0?J;0H$xmTub318&uw7M1uz?}hv=P))5WVG?>NJTleP@`nzE6<0amw2z} zTBjeQTqW?kfkH;DTp{@i{n_h1AP6&(sW6s{>u_kj)mImopVv-aEWPZ(dQBP3pe-6p zGfTZzH$A7Nb?^BN+HNzvV(?l0L+v-?_W@o<(KnVGVgYD##ec{sz+6?rpR{F? zr$I>`V*cU7kD^>)*)KZW_UqC|eh6Ighol3K3P5}cH2)X52AJ}r*!PRw%Ki%4f7ucA z-^>~S_&;PA_}yax0q__*19w@KTLTsSC_OxOs`s~+0nq#pX-Am$ ze7-7hzli?t7y}1t87~Dz>enI(T5PS<$v}H zYLiyWy}Fzp7z#ie{4H}-6M<)2TXpWP9~jF4}>UJth?#t&CtijV>W zbBmU?#xWmv*8h^*L2j=?%PaxLxXj`>WCrqhCSkwf7L4UJ= zNLO&)(B<}6PQ=%*v{;*Ow?Iyt^2_>NUQF{Z@p;9&<$R@im=2Ryx@`W^N~e9Vq=(82 z)ofauZnWVAI|Ah{fi7cBVG{^|K)1!#Y&TJ5Cr{uym~N8^vCacz*s9^5{Qv&n;qcq<@C!%C ze}CF}U3>oVfjw9v`1|9-*zD)>_vhK)mjSo;87XSN|La+aaXa3hK!H557 z?Gf_--If0znIf(aP=rZMq5sbEx&Ben`=?%=o16VVuUA*IvYF#Ry-(9^x5+C1ypb$w zjuTiTr{!o`$-y4@be<_6%gUi5TRAG4qSZ?x(w^Y86^2=xfV#x7>l*(>H>((}=;#2M z`y1T1FsB&BZ^_@uS4*O*r7)#sc7I(To#Pe$lIu_Qpp>tXakn+|;I#eZcE6xNd^xK| z@N%;MWmpf%70t!gt?Btk)=qLXmUUCGXcD`TNn{W+dO z+oqOJ`d@P^oS>_Zc1zE9r^?90S#NLpTuMw{as=aApVYFi_k@{c3U0Q_JMF9Gq>qp= z;o4{Pp#~+qd}@~zMXqP6`1CN!%<=sqMrMnKdLRx3?oa}2$dafXWFW-fqp7(NVb$_$ zg|A|#Ed)xLI@`f-8QQ_yCJE z6-L%5ODft>wuDEeHgwIvlFi#0i`M*s5YVVwX$hazURWa18+cL`7Q!dJ4zcb}Y?7|W zuqZ#knHqk90U5&V#e3;&q?XXO=4fp~O)SoFv?1An_|?CT1nBdukW(bST}AV2MxP~1 zE5nb*wo7Jw*7&X3Sw(JA@f~TUWpntL_IHa*Xc}L&62!zO;%7!VhYnh9;ZLw@v<|3JzGG#kjb3rS|Z~+s*}? zT$@aQUmv1$KGD#(1L2WoE?y9cyJUXKT$MrlB*JNnGT4k5+|ZOlbN3|X4bd%`my;M) z24k>XO=T>}y$@tJ%e$xS2Iecx{j4Q}Oyz$6kX7-bwe|b)Y3~@gjcHwOkLk1p^Oox* zv_9faDH`XYD-i~6Q+LmCNkw6n^@U085lI#T9`Q(^W+%WTjhr-iS+OIph#rT+Zx%^h zo_M;bhNyX7M{S4b2Uq*Z_T;oVT34|7t?Z)oW{n70V?cxn2%t z!F#yiJ!gV%`mZx)a`Cx`75^72pgm!wFD!$oWO@SbW+ ztCGjfyL_uJ3jSkj%Bcm58sj}}nbJ~_PAuiBgoPu>W@iZfas?W;6Qd``!buzSth^PI%%-Tidz zHWqol5iYbhOw{lrFC@kKVKPnYDa#tYm$W`b;(x<1M(^+peOLZ|tz4It%mL}R*mTa? zCqFw|?2h{5Qm~|HqXXB}oO@7K=^0Co&4Or(!}X0;3L#Gn5qjdn*RFNvJ=DaqgsO3e z{EE;-J~aU>NYq(axH$i~o^SO%$lt=k9TYzN*&XHEfHbV}8bk(CEhjXh2t zeqm#GL8XOuO?8WQ=04pZ-D)Mn4>&{ic38S3)LW>$;yF>~CpH6x`DptwsT=+fTgA2K0F3rmL#+ORX$!^z$3z<`o8}WF+{YOwNs?7&D-$HS#odq0a{0&UUpqb;;!edUXr4I~9(Q?%n$V}qJB zqUUA|OYW@wn-nj@p=~#jbVW5s!8B$3g$3D*ZX|pmPlCZOsxRD^pE7(HEqQyN0V%Pf zLt;Umh{*C%-jy4*G{1TBp-0#6{(N}oXo`3@NE^yGey+m4G}u|=i$BeNum_C)lmu~` zF@|d6i^|-fS#Zf>r0}@XQA<;n$wA=NIl`UVGZrnG{(IP|P4%)?Xi-nMBTN66Fp{rI zO)&@w_zjSXk<&tvUwqr<5@daszk8q}DOVn*$TknM^SKQ#oh3l#q1sruL*z!mSjJC2 z>|2K$2W_m_arjR9PT--gauXM;u-aaY0iqKf5%fzAI??)_${B+H#Dd5;s~kJX1)Y#ihV@S8@3>UZ*%YvruD(edK~D zUV=zaFVRH(($qRs=;W?1Bu{;ziG>n`;jP7obeW}40n2+YcYrBazsJA9(<&c{8wa!vMm&n&51LP!=b^qraH9HFqj zv}klpHo@V6i&b8J^|M&#F+#i>oyFuI4*M0_!Qucm6Ew21;NXV3EM-WNr%<7hF>veg z355ww@ov&e*$~1@+`m?26%N^0@@{cL2A!3B7M>TOepoR{v!Yo*>MJU`=}28bGx;PY zDhe;rVUaB#EqIyj&D z;903Hp3i*3!i?CV#ih}l061x$=pzhnC5_=Hzgzz|vNV~Fp_S-Nak3d5*NosD>de_|0P)pHWlpOE5; z%pvhCS*Fw8fh}T$crjxp-2io3IqRDf+J@M=#o`bm>--rQ{TiX%zKY$4iV{J34(G|* zYuU0V^~#^i+%Z45HHGz=B=$XU7W7^kq3Tv#NHJrj5i1dz0fZw;R{Mk z~(=Y8K79QjEqTZ%NTblgdx z(oycpAT2Y&lsY;>-rzIM_00nkmYy;~Sd@I> zOt|XT$SxN9JR=*yTlQdgY*P`~AsPi)&od$^)fS+rh|TwC8_lRe(RD^%K);gRcJL}t zxf<{<)9ymwyJrn!-(A}RuOo(ikj8kyc_>V~p|%r592(P|_jUVlnw>cEvfOmMHlSpm zA)dTl!uM;vl#Bxr91QHo8f$`eTJLuYNNYK0lDE(BP8q2Fo#XuTw46WdBp1hjzD^FQ zYT1l4z4SULJ2W8G8=0CGhl9c|>g>q2j(sD{7Zc?KiHp(6t?(YHa3}zZfa?1v(W!>po{zx*7ELH2Sb38R~}x_|WS!vr&rJNYY>FXBbG2!f0c zu~Wv&+GUACX9EfScI0lzE66YsJR+g!GW7Z|;vL_sO&@HfsWaZ2;mhYeH)ppc?(uM> z`o`cNH++UJbW3tf{GsL>UI5{bL7x3WH91pqUnc`8;wLIg;cua#G@+iYFu!IH5c!7q zJYm#XKSxgRbVgG#kXf)KS%w34Zj&~{#F+TMxKj{n~_Vz1o7urs(KfWV-Df5B#h!a1f)u@ z>ODAquFKFL2u~%2pXka8KEpY9(h)Weqx-zVs1}OK|2*OOyR$N#Psg}Rrod|md@(2C z#jFTeG7ARJBQ_8s8jhc(#>-Gy->ys^nG%5q&8Qks(o62Rh+a^=BE3Oe!7J03(ao#6 znH99$ub;7-*yFNv`7w7;U$$&lw`%v}I5j*d*GN1$fB9MBj!WkIo(_+n@Ssl|NYdFg zll5JeIo)~W4#=e`euM5POh_Kpq)JT&<_VnabSyQVx#dJXwZtb{rJK*O1*t=gJpEj(=|4|M*2|GE|Tse``YB>%&=uR zLPNRxl#vcO4g|Bc#maQ+{- ztcr}n+#6Kz3GIe*NsfEffrN_6IwmwMxhZliY7kpOCuuGIT+HzSu1EBTs3^*ucOHlP z%_b(BC&+%xOk6Vtw7fm3s{$hM&&;5m-uab(wAcG8yX1VJKV-I-#;0WmV7inVKOgw@^P@ zFgLDP$`AHVAZF6*RWo@SxuK%H@MXKYx9F$4?Rj!%i@?QF0p}+S+5Vhdd57=HOc+sx z^qI{ipL?F|8a#VnoUS;+M}5HE6h(9PMsrh zZaAGE6^*o49h`=iV8l#ZKWq{3Rg2?tWWfstFya*MP!%whtO`@%7{tI^dB(poDzE;; zd+ge^;bb}Dxfzd+7`{|4xAFv=F2&tqu6sEnC8CX9#Z_d!dnoJdT9r7rnYpkcenR~@ zvwMY!EpC*ulfB=YcTs%VXXI~T`wqE?^4!MCKT7s5!gg&blJm`=gaU7OUVQGwQ_QUS z)tlTX77K2s+1Cm5vP{%g~dmCmw`XPngc`mpzTRJ_d`LrRkjs>2VBrEB)Q z$um5|X=QaPT=JOrN@;ivuPElob=@*Kvo(TFZjZ7ShDNFRNqaQM5R>B+cXKE0ro^?d7U8+?tC+xt~AYRziTq@(nzA88Cst^P&5zi$Fgl(`-EB7@}Y+cw%ajD zaO}w%-<3wsYpZ9W6cT3a#f9WI99A&V%-KXz;{AGYe4VjnT7l|HJ72BlVM;jqP8jy0J3@C%pY1oa**xA!K9c;$-;`k8#`8hE;#rbAzmp z?ZJp$U>@3XL8wL7s*Y};ANINBVmgcf-&u@If47CUHVuu7>5T zn@K5cYg;#8<@0Rx?{Pc)Ai#(7kz~f>%sim(g0I}rtNpOGm}F*h0s~jYa}tAOjHQ1| zztS(xhmfPo7T6*|ujQqTu)pu{Gp6i-6r%K6A)K}F78aUr2U4`3$4HJfVrb6HjDK-J z#BHbFG@6w>k~V*~(6VJbNwK%Up9#7m4K4M)$Ia##h7@^Els!;{uU+9@tt z%vrL1q~WD;WvLXO*Uv%pqTcg{vEZ&Rx{JkwG*vn^p}uRu>qok`bM`{eJrCDyTuikX z`)n%jcpTl<-IQ)>9OD6yHZ%|snKGm&F;Cu$Br`C)ue5K(Sw+$)qL_Ghcf5`u_rthN zi{`o3TzanDj_C5w(e#WUR;-_jrpIgNT_M;XAWJ)CGV2B8sEah=5RB=P8oy z1Y?F&bO;9=-`_ffaN4L!F={l|WAo1C$XH>}c+^=t(b3WII2W^9zu%FL4OY5$SS$Zp zX(FDXUC*@jMUW?kO0R3iVr;D_iG5(B-$*Km+hODKsE2ZSc}F%NbL4oS-(+scibLvq zrr1f9>|~)z+_gYykkoPH;Md^_;ebq56KBPuAjrAsu?zuLZLXe(g)_ZVyHWqk%m;kV z($o7pO~N3r{o&MB5|8zMihRc0$!rT0iXc?;+Oc4@9BJypK3L??sD}Z-HbYqrW8=Py zo)xLlZj2m^R+||)V;`fp-p`sJETpq+(C3iwToVO%kSeV!-jF}%r(=!CGm;I*J8Ky$ za64(NQab%^vf$*}9m+tL>T)28eLBEMzvaE{nVHG)=#*85hZ$B!E1CO4ksW69jTmF2 zO9?p1GgS)fBL}9vdA5EF2~MjDW3iI)Thx2(@zlN zb*&P=%y5L4X{tNvRSqF3W^5wfHp%_-oMqe5=vZ1cKqT z`B(}I<0{;Ss@ZBYrqgoyRIztswMpzYkvO?bb}P6}2SYBK{p*J1NJN5OG4^BGeNN+J z9mNhdbG0y4Q$-gP1k#L(JQMwG>e9YHrc9d7`~D7B;>*3Ijo|+IUaLAAAt~vkE?~ol%gm>0d%Qx@n*cPtTt3}8 zI(<`8i(E967RLl~RVsKw$n+KME?v-jzgMzB=}g~%^ZIfyk1w6;Xs0VAT6q)o-IVR! z^#qwjcM3nR?>=ej%k1@-*^ix_mTSdcm*u`MWK+3W)2xRiP(J0z#8YB)FzS}Rby96| z4s*S8r{I^Iow-}t;Lw`wk2$qfpT^s=k*=d8n~xzFo3YFc`a;Ox-&r0Ia1w&uq(Vmi z+J=aABPCnF^5UqX#di7oXAB7j9lp!m8N$BVu+;YUCiPFBE8Nb^O2p*VZ8Ltg4_LVM)YeG57*sTR%*@H{DZj#C!?Vc_cy63YC1jHWuMvE zUzl54epK>>R*mj60ZSPI)QWjrTIyjY`Ec`<;3NfP>j6{I@3~ z^f8_98VMP-r?QLE?QAdU$qi$-kp^kia#8no<1<&V>5~=*EYh|ai zwZT5upWjX6a*kH#3^DlmK$mX0K}D)96j=hh}x$-Lk^x58ABQKtpB7bSb=jpWdA zO{T85cGMMZ@Sz={@kl5;6{O8Z$TMHy)ONKyHo@*_MaP~`r?HgUz$=h+u_5cbF}X*t zRaAv!JnP=yy3y=#XcWK-==v9l~G}s5TyDR(VD9CmfPymQqbi6^g#nk;0MnjX!LtHAw=)mwhkq>@M!0K0^UV+2E!>rKT zY*eHQNf621#JfhDsdM!97Ucz8T=la3zvs==>9WA^zwnIe&vyA%8vQ{3GCZ z#HET`@KbXh3oeT)8_y(6M&w;DZG{dN&JqHy-%^-#@jtucxfOad4gyZpc&W{IN7~$r zL0P@tXAH|P+Za>O!=PQ->#EdTWjg9{dZFZ5-&?BPtezn+5ysO)7fqQeFQq5gNo~9} ze>2t-TtTZV&?6mdU9~&|V9%nrci5I*l98r*g!ePL0~Ypp$FHD+sDt_!ZXm3>fop#k_3Z$#RDl+550{{)&W*&FTBrGm%7;nX$oJWXtdn0| zUC%A4-SQ&IT20Wp!z@zW0=oHG(N@;jqV2_6NC@5qZc)c_w>c67I8Tu;j(k6G+L_cv zAsjTp(12fK(n#U3Dr7~(Z(ofbs*hH@HZr12W>&Dq;it=c9i^LocNfp3C#3+3%_tAN z4f{S%K00je=5o+vYi&5y;qKa(JguNFlwj`N6hXu(v##)2eC&8v_MH3{7&L~4ufFm5 zE&iH?e3+7qVFRJ+4!vMY%n#`X?V3VC-rcbrju7!!Tz9T$cXh;i!rcD8w9B7UhMsR9 zaW`U{#M?}AgXLQ*J$D_GyVt9g$qd?GpXwP` z)Phect}JO)r0I;)_`+okI8BKKo~vu}NQliCmJn{_-5)&A6zpl$R408wy8U)m?(ggP z3T~>yzuoWQ0C4<*y=c*xZM{^ynC)=^;! zlc@PQmeVI)6HfDF-Piuxq~$x=RK9ZGv+_6w%6aGhGp2OnyZw31ZlpUS6c+$dPP2nl zS}4kdm1(CxWK9^Mz1KDoK`{|Wx!BWsTo~DIuPtaP_+_mUHG(l|+l(&{2ez2w4hTDH zDDHk*CP90=*${`&3z3pdX{l4`R994yH%^nx6v#zJx*>gA?LmZ0>T%B~5#Sn!Yz1Qt zDSYu&UQ`Da`dYG#jb;h5BC4HjA+w*z2elloBxb{c+#Boah~g9K#i$>o^Ty~u6_W9I zIDZ_gBGHX+Z=$IQ@h$?^oY2$G5>=F*ZtJz8jhW;XgB~xE#%VGUj?oTGS{h3H(*tkC zycj7%dwxFKuj2f-b{b(TSZbxOnmt?uZvfgiE_R$fTB;iAXe6?twP)D=8$!Wu^HX?%24F$CC}gl;ltS!S&bWXybGd)blT zQxxHb)brx%B=fFiQRrlMt>&){-v7wOq`hXD z@8aNE$3Di4x!9N6Jc}snXV&B|p6Kc|%PVwOZ`?lYkEMQ`&Ai9i)NP^ll+7YcB&=5- zgvXc_M%nQIcka!3o8gH#JEu`=fKFLmWDwq)tS8$dXVB8qy+Rq~D? zE|K4C$uGTlOVRpjr_}~bjg3<0aMLnKmA5~h z#G)^hW>o@+L9L_kc!48gRDgSepegG`k+V1a0%FzVRE>pIO-mr|j$SE}RvkFW+FVGe zsXLTgt>wDpTfo6)KgIBBY*x??L<#ATkk^@<+sz{cYbrb1e`lg$>!4LDn$YW7nZ$^m zK9yof!cNy&uhISTeD7|ISK6=Y1Y8X106odmZG|zvQKc^tFCmnl@--dnNOE^hJ!L|f zDx(#bpjD-##5~ks_g3c-%&=RP-r_;nE2VzsCEgbnUHw5x@2ZX9A|F(00CQ^luX*tD zq=XvmCXsTfsI!5GPo61qBaQQamCh*iE@(4Ip`ZoiR(Z6eXNFCdms$wv7!wUulKH9d zxI{0n#!XxuuagESbglWCRJtBLO%hmx;!ja=Pnb$Xrzi$EzOOK&5OMP&4k~79L7#~Rk(Mz0(h5@${5%o~QcHy4^rxO@qY!%>HEPS>= zbmFAD&k)HfzLiaLb!TELn38|cL?Qwvj*X}*U?hEDtmC#^^s`4r#axcBoc%Bj zzpPUNV>5(hKv||p5z?{6gWB;^4*~Q^ydcalmN1Q@1jF0c>trKc^OYDtp@4Z%3BJ8K zP(P1kLEm2EpWYQP$8~&quvNRpg}dvwL;e8ajH%lP%YPsbMJx*c$a7?wl0RO zZ%{lu=8l&qPc~5s!bA$kX55I>Vq<9+@0E!RxAba1Lno)85-}FOkEJCI;waH}&)S`7sjW?w((R{VO}TmAA+Ct#e{zWsxx21(I^PcQ)@aa&lWI@Jly<~q1tp3;Y$V%v z1hNybWCImy!MbeG;c`ZQP1M7I_YfO>oMEsvpmQ|4NY*{_l`BUJ0Xc0adpa8l(7s(5 zo)MdsL8c9VGssQ%-jrAgMWzXddr!H9(723b+VT171iJfJhj|OdoVobfOjv8#GNVIA z&{<=vD5NmB;Z4$HU6etF1h@GauQQcS$|!|pDRpwB{B)~#_I3b>msnMdpKs%^pqcKe zmg@j^SmBxQmazi0ETDgN0UN$U#zb&0BHT_kc7NW#wIU1W#Xr!m7AE#4r*AOG<*Ba@{}n+D*B~J=c1Q~l9Q)~V>OrG)VRYz zEG?`?HK1bjO?8y%P*79=7w>( z$Unw729V|?3i1FK8*HH(D8!P8EVbzONe7&)C;U#hQuOSGEOE30_i!z7q63>jcEzcq z9eDp6*wV_IlnnC5I&vJNuXu!n4rRWCFOKn!U1-US<zqUkFBOT1Re$9cy8HF z7M1icSUeZ4lxCj zlf~P)(h)+dQogTZ@D52_!C#HO1bog-j~Ci6oz=ouTsdN zV}SMa@U%h#wS18P-5+&tO{>{;RIwNg9?{~G(04_SW*^ko?OrRhgpK7dcMN&k2e|)w zvk%ZF5`L}Tt-dz6<@)}&-9JxAG^L$?_LKc`OV}UmU%;h73xUs|UM%tLoRPbw5rwIiTwWz1#LW;73C2CXcAvfJ5 z#62SNN54$0^WGf>UUlVAuE`HLdyxymcF-Ko;*@f#a<^d(aq_%rMeMDQ-MAMr6k3MZ zE>3pIvF~p$+>chCz;ZVg95#okcH2F#MMn(?1Vn}kETe2U2AAYxvxE~IU{rEZQLR(D zgcl1fx2k<{D!!VTBIYzk)Mj*v$fU_Z3KX(J;^UK;xs^&Ti(Y*{N#R-GHWNMuX#1Yt zN;`YWPu47k;s!PS@_n?7Pk3DIiPF<#YDo`H0XFF_&JQ_*`g>j;`fhB>DJAK8v=_N3 zX>9y@qB7GQQd;}f8T_wZG4rwq@5phF%-bem;q(>SR0%ODM7`__cX7M}bN=Lfed_Us z^UZ#vMWso){%fAyS;v&2>*|^o;Eo^K7WHqZTlW%YW!c#@>JpQq_eOn-)zy%5v*>Ji zn8M74fcbcx$VkA``sXjq$Y%m>vG2c#<|{hSyt9NE&$QTDZa-O=9h4xwn_Td1Il) zlO|qed>|5Yc#(aY@seNmG^C4a$J~ze*|XLo(5G_9&DO{P7S9Vyc@lohFPahFUs7zL zzxHZz##`P*>U0C_9Yv~9!5Xx8WFUP>=xTzE5iHkeF*-5SOB$Y1 z9$`fbaBdR;=vr3ok#4o}cxL-Q9%%I!0+UlJw0P3+gW1;S*)zQ zqp0)&!-qEUfWURAmtl@uim%}pD@^1%g^*O>-SFenGJ}L;g_Dry)G^%DmdIY&);C_K zw zomMNdKQ5N$4lnd)v_K}Twvhf-HKg-?ptQCWg}eC#oo18EqdNt-Em$`|Yx!6y3oIE?&slkd79pKsV5!FYW$#>gE|E{KC^Rq6sW>=TfpXk1v%zuK-jE`de4wl_Di8(i)O znBqzhldn0T(E1I5Wz)e+*;0G5sVy^Qde3=-8Bl`p(sw6zFhK%0wivr_BND8UQLo$= zoA&qSreH`LfMVu#p}n5&ZEd$TYFHM!9Zz;KU8q{xz&EUfllLI<0xB;&AOk-FbYOXO zNXW;Ja3DlLNPY|`$zKTms~aN&!tuw4P9PvS;Oc@H$Ua&HQ#EXV@+a zl0Nz)OT(Sy%+5CGzY7P!!|C$B$wK_2Gk@L9pX~4evXp+b!Tr&ZAANxW?>=+@#PA9D z!8gDQ5ADO1A=JD@2Kt8x2M2z-`{=h!4Rr4*92_71H2iO!`=NJma4xUPkUl<0;Sb{v z2Y0Be3xazPxgYxa&`GL3W*vjVH0OwbItY4zAqDcl9PARE!%Y+jC&$P8`Q9PW;r$LE)`$JC~;K!L_0d| z4EaPp+4A6|StXkHX3h3?^{kL2ADm89x)b`8s5>H&#p_#FR~Yf@n)l6aWMpKD*NJQ< zS7$q_&2DGr69pU=la}8;V}QVX!!bRTCPPW=W))U*oQzzO5)$h5_LLma0(X}}?s1}F zL=yQB?>j9egzx4H4UXQ|d$o0S+zz;k(g~zhmMHi47-)E?sl3@JY$jgzR$#$+ru=gj zgJG$pN6}qsnaHtW$NzY6q?V*SxRMLvm65 zKUL9Nc|GO_>^uiAdTZH8Dr1&(?!01EZSVRGoAz5&NM}U;G{~KPWW%7~najJUq6Qr0wmGH%GD<85uVQk^y76 z3I&nuFE%&29IXHajLfklBqd+ANuQ;!ShS{whRQU!ansR#Z*TX>+?%ggl44hE-wVL6joKU!0s59ge=C!UhTO^fN@FM8Z;GZVAsMO6i`kYLJx4%1Wf!c_T_? z+;`sXMx|}IvG!@@*58P>E?k8MkD5ddC5+Jb)91>_8W-8;Nfta00x>r=zIw3()G_iP zYAbOl!z7M6^1N}+2Q$@{rYLq55SMhlq@bc6m61r3VFKt@Q)}fk?nhOQJuX zUbO@uuzTHhgry5BZJqH_v(rgV%MkAFd}3pJ`i3*icAq^HTx{|wq*r4lqzX;7%Ay$N zJ1r}(=l4`79-=dZgLtrAQYi)EfRrgFzU@`-nM@PHCOU7O;-QQ8`faFqnIpFJW*W-0WL+~>=+a}xy@m>`V>bE`4FqSa|;aD!v zos(kArmcZg1xGU5b7XXTQxe!8)r5w>IT`Ng`gwIKUcFcl@#yq$m|iGRn&1Ou0QT%& z+?zk5?we!ppxF1)0Qb~`*g2|;^ z=Z$sF{nNjsO^mgcTYS`M?2NZ;8+@f9{pCZ>=~NJg4N=5kgPwkT9({d%NgxgbxMyy9 zn!R;uw%Q_}Dx8o@R`z9NWMnM8D!sSoU5C)FK;I+!C%&Fs-u^-cl{#XqzkaKM?LeVC&K~icSmnvL}DPrn`#uhIvcO zMM=9o@jxEVgc@KPW?lk)~LUFEun5af8qjaK>y%5o8 zqLb2$>%jPmPM-SD#0$M(Q!@@(g5I3Z*;wYi>wOP+vK2aYwq&%lTflm*Az3c4)*l5V zltPulF5_R@FeuV9qRai%%e0qNR6l>T`2y6)Kq6aiWhGlUr~WtOd@$AUy`e%X^Vw`sw?#unDxVXYZ23#t5l{4vQCR70Clflf=v`WS#<7J$cgO zbV#~!-w)mZ23(hrRDRR5g)953f#^4}!vv(;XRNDUt+(?%IVy*@l#@dZ7e@y>B&DUi?r%{m z#%35nHMUX?`VQS=#Jy^U&XK@Ih_7etYb0luBBNpfXzRrr-O2@}*NPS=sT-B?*RW9U zx=Z-v2nOQ1pM6&}tXu(I0a26`RDKl$0ZGwHQO^9cy)^}-Z%ZfwIkxn8xLDOvaxvu4 z<6f-VBAt53C<$S+*+L@P!r{1V9PAZ;hUDZew zflQzSr3seAB_z>Fw@$1%IP^FcT>cP4JsLIU%K0C zU&<4MQNw9Ys>h*CSBZH$W3MON@&vCYJ3c9V(jrfFwG&n0Z3%NNb_iT06sy3SSCQwn zaPB{2VYovqMencZF^cT})!~On^8RpSp^KUz7nv5N7lrSqmq2HCyCun-`HWD)rvqZu zxsn>9KQoJ!_}r|lAK!b9LA!x{VwzkmjAmv=dI1n=B|_WU+6=48%3Q8TC>hl&V8Bd| zY7fHPxcT^QKsaS6m;l9TXh<@pxYsH=xsX}LE#a`EljJhroh);l)><=#c;6*Y zji>roo3Sx%MdRlj)+o}AE#YrsutKQOVvnxf)5I6#Vn-{T`CWHF)R*LWgX2!rZGR%0 z`RY=W>sW7Z@AvOOH4=I+%n(AZu)#1AfwVhkJG)&ee9 zqyzBbr58rfZ4L=k;Aa=~fCSJhsTUHz$=zN{$GjPk<1~R5La^OynVhuy8D!+xjc_MY zDW6>u%P)LaYy2-7A;O`52P1I5Jk+DS4i~r+KQBK0k%+tgJ(m1>qEIzgCi&d|-BU2% zWe(~zG(BngXq%>-Xz*gK4M}Q6P0ir5)F+NeFmFK2)gbM+0WQ7c&Q!?1_OthKqq422Je6oRB2yU&(5pmh^?~U0lPIg zH6}{<-aWuoa%_1iqo^X-b(kKZ3UZq zz9WO*T&Bj5o3?}|iDB!=@f@EbW64e;6=mxbHJ)6Bjbbteti>4KIV~>N!?S_C>=V=_ zXX9YVvuB4;Kaj`;w$Zswm{*6jB;BliBc=Lmnt9=KaT2_%2c(Y8T`51v<(50+{ZVE^ zm+&3zMb=mmbbbEsQt$ry2|mAzNux@<7mS6a1e6{DAgK3c#Ff+6zP{j>-e(i4Ns4{_ zZVj|bIS~pCymBfaAW$%c0q|n7%#%KB3}yrIVd&qfQair|W^TN8W1l$QDP0*wH3fxw zOyrTlZqI9x3tq)E1EtLuq}rm?U;X)Zs#CXiKdtnZyh#%r){kJSqEofrjilq$mkc%P z(~#F7B2LH)i4ZwH7!zLd8;R4@MTrSu}(RCZ5{cc_shO0N z6lV6Wlr3P@VVo1PB|S~x7Qhit<8w71&%x z6fHVXQ;umW=r#?E)cd^24>+tLV5(iWs$kE&Fe_xOGh3DH+wTv+#>YHvm7$u}@@&T3 z^J@}{8ScrBkj_b`miNMSunk8M!SR02+@@L{tPn|VL^rJtn=FByX62NFAa5MO!1%C{IU&;Pqc7KqKN9Cb_e+l1bYR zxcd7`t@mra(M8QRfQx&wF$Amw3GfMIaum2HASgUMys*$hT6#Ne?qYu-+BzgfhBw$B zO^G^qAc<1BhT)XHGYQhZ|PMf7;gO6Rng~%JB&@&H`td3?b_}_|sju)F*I% zvM}KOuu*V-QZC?zJK*5H`hJ2$z&+$wJkVa%K+#^rXVU28qR0n}i4r4scbW=$`AQsJ z8SRRZ*-tn3EHL2+IDpsT{xEUV_&{;*I_}f!1OL8w|BrBQbBiB~hG8eMW26a8**x>~ z@O$6vH65$W= z2M1(`C<75cT#%d9a9$mJ97;7cm{*Gy2{Jm4*S&U6qEb^|hLHKo=@}Frd*rd);KYoc z4rnk`EIdcl<($D2($8W`div^tmiwox_-<-Q)6>Y&)WI6;9cnFFb>2F+`2)%RHmx{! zS5icc?+T$E9sce9{#~I;i~v0sOP6_c>%OVy@(S)Rf4HePPT#z<-0vH+y}z(6S6`1p zOS>X)dzC-cu`?BXu2MLPztN8oYB41U>hOK^AM%hsH!g)Cj70H=k|6}*Uup8h`+l4| zGO|6CP+$J_PYD)gt>=U3cxn7H1}447UnWbQ#E^`7nG7O>!Gc;T$1`6@?JyaPwnnnp zokoL3Pt`M`q6`-lTELT0Twdfk8m?ZOm{&`4noU3jViqX?CKDx{0wPo9?Mf%RsJr{f zbcPTCM60%B1-R(p<`=t+O8_|FH@8ahn=2jA1Vx`(P04120aIO8gL`kHH_QGI*2;mK zTp*bt_(b8g-S9n7g&DY6Y_>=YMCR?4p(oU~pluiT&9KE|MMcMx@+l#etRbba7+RJn z3Wo)1{fFQa4UXkmjtqOF`Wl;X!bx-AQUic zDut-7CqX>9LJc>^M$Mbc$Lk`E;c^7zw={+fN>riX5+yOUI{AK-EPAnLdiz=r)A$c1 z>sT|^(cTS0i>f!2IMSSBVruVzws(bQ^1fVM>jhGZLEz6$m|cdymXSJDO5X=6mbp3l z4^#4aGsQ5{W7EFem-_n3tH}k0mWwikh<004#^pv0dz6Ayf)8tD)gKXE__m+peP>X6 zFkZe}n)OJFXA*W-2uA2>JQ2e zU@9Yeky`7_$Z;y9e0?+a9LHEg!sMo_KIR~yQFn@R`=8j4;gweXpuyz57yD-YYk3O# zFKcS@<2Wp^S5owLCdZXv;#AOO9>ug>aZEnwX(|~1rigcaj+2=C%B%gMSVRdqP};tyx1&~wXFpI zcN3ESrt(uEXRpjODC^JenoY}V-Vw33<+FQE&1td}3reUCrKOtB)F}`#O!x%hbV`YP zeMsSF)X=C=CRrL)q>+C!2A!;%jbrbnS^%{McEqB-kimknMS?@%3N!-+`hx0=25q`$24)Co~Frh%G=gk z9z%A@5Y&I<=&$k69oDnMov9$$I8#yIp+}$}f=ET_`|NV0C$zie<-;9^y8pGj>R+HU z_t?|y8qcCMNA1K*_IoP4TQBcZUke6enx6;%xIBCt*}l>VMCX`2j{XeuYrT@xBH%O% z;#Sq`!wq%grVuX2l;_RE85xz}yeOL%#M!=D2yvQ02f z?|bbg!?hlU;f~o8z+KA0?on%Pxx!}6f^H1r?2S@F{aWvFL)lFJ*T|YA08@a48Aq+ddS_BXK_uA8bm^~ixutNUf>lcl zg+Ug*58fz7g<;?oHgHvu^_B@f9c9^ zD~S-%t4a~H&X_4M1e-7n;z{?NkDmSr%{fMVu}L3wG_hIn=Fs<2oi~y6Y@#efusZ6p zstS9y3Iop{LpBxjphs4vh=ys*V)#vrw}ZuKqW3+cmua{mkHpMWY3C(~Bxp3!6Q{(< z%1$7t1KNqOWjjESdRBJcgyG)oM*FS`$QFGsYghpj7vZv^+vlGuh)qb`Ul>dDD?)*3 zY(euhR8oWo;(8|X$sKlSb{CQfsA(k<*u>`5eDyiaDX^Isyr5y;;d5y$1wUQS|?S&}|$zIMea}Af*2vkNNQb z3t@q`zy1qfJ-q#YJbuB5iRE9S?Vrrm2HsY4D)pl3J~z<=g^s7>4NBwq021!k6oRw$ zKA-ID=eUUH^4%5gXKXw*0%-20u%E(?#sv{=r-zQ--6f6PG4JP#)-rQaokE*_dZ(w) z+PX8VkD}KwQOAt(?bs-l>&>A{-}K#RJjx;q|wK#aB!!GCc@d0?b{Q& z2mclZL0}jU4k7*N0kg+#_2Fh@L`ulNdMJ9v=KoI*-+-XqqPS^G5io=1v*yiLl$6<{ zL7WcaT^HpTd;}=EB^v3??)fo2s`Rt0kd%ZJVHOGSMxwT67?|qpdcERZHm-L!dAhp? zn?YiX`g6FC;5#iqpL2gIAW%mAskK$ti1L`#!IYrU*EfQz^v5=8Tz~adBJNyzFeEzP zOLQqh;Ppgeks#u5$BxY$D;e*g7k}l`*T>YAMa|V>IbiG7Rc~pKSZBAit(wP4;>mke zcOJKdab^+j>r2FNz8^ong%~LszlDQyyZoT{TPiEd^(ofu^zv!%jYgGv^HIJkugnZf zjdgX~M8ndX>0CPh>V>n=-LA4p#e-txyvPw0D9Z2byx57}KdQGO2b}yYr62Hat)&>R zwdB5!bijjTudGkrTy0!4`l_w*Ra&$L2ll+7GQvfG`vMif`>j&JyKfJdXHAF3(ULQ9 zNQggA;>1CG3Mchb`&K%5Z>TdZP(^^;x+gt#TlzQobu6X%YQ%KaB}VJA)aO z5~xrR7|{i(ZRfe$j??=%cO=)FQ0H@CmRZpr10G)blShyA#q6#*rRQi6Ot~yO7;PwKKMrfE(BRL5~NeKvq(=B0(WFP*kz3zpi^-he-x2 z3bT4=`KKlliS37;1fa=eXQ$M|Y4Ixo24234A{(_EM8d1hB#B>79>Hxc5BYfCVMxZZ zmOP>C>Re2N1jQGNa?U+Ss~GPDu=KClDoorahSUg;H?nz8RK%CuxL@wWtA-#g$g!+? zaUof+Dd7RR3^6g-h4p83cjGFc=zU@bQ&xf9W@n<-Z{(MevWYP|zgGXzoilC|%2>A4j!rhxQ@W{e!D zoRuj)d`)NHyHUG7yMvRPD2d#-&6vNR!62rUa+wzKq#E+Zr7nU#Ue^Y6&Q4DD)^t>u zrDD8Q;CDk5mV`X+K+){bYOA*Y4wvr6d{5+fBH8dSN#{z!tTQTisUizs{8} zh`Cgdr6l4eUF)M37W0J+B=D(gc@D(qk?s*3OwLVzQSd=JD26Y0QjZ58=v_2OYe04mw}x@C~x2D z_J$OuN0wQw?ItFGIadOT1PaiV{GWb-CfgAA3$Jb`HzpVz#SZk3I-GoTI6F**oBDdF ztNnYw7+yT}Dl%*Z?5fU$=MXdR-#w}3O)4kOL%`3scVg2dpBJHP0DsQ@V}{KxdNlPl z&I32zFZ72S2U;#Kw@TSfi~@7+2Ux-toM}9?yzyRZNO(2oK8~et=zdTyE^!0Mw1slK zZ3OQ(xJ#!xny2AjimlVErKq!U9~a+9e`i33djr}5Nk|C(W~f)hBzXo?u^1Tqrb^q= zcqu550T;LFY-(vZ`Pqm5 zyyffjdj8YH!q3keRx1kU#@};qwDWqA-B$#p{L?fJ7Io16{pN^rA8^yrj?~vQ(H8UZ z=b4!?d%lQ)e7JNJ*7GQF{pD9L$mT?Q(t4EzvTS++GBmt_sdh_vb#{u%3EsiD`8=d{ zdD6ecC#a>*cYn^}KR2X}6&=mKK*@g9Y;w4|wejxg63@dX@@1&(XAJ%@xS_i|mxE?o zz&KJ4G8dIMoIo#46BA=zAOSY&3{^~Qgyj5JRiMj1JS<>Cu&5PH2*2!X~KD%bV1BU||6plJr3@bzJ^ui7|M~h(&(GTvSd*~SvFbmRCq;6zC2-GM zz%vnIw#sdj6iY%v_pbN1(z#@WA?6SjG9dFKVABu(;tMpbEj-lKf|VzcJ7H}=_CXI zM#$ev`&tX}&xDzJp`!@=e7MQ)Y3Bu5OMJTZ}2VIQ?FDj5V(NP z`^VQ@?EU#b!8rVzn-w)gHGGzpnMP*`#5(2$|9#44j&%euJm7+VqJ;Ys*jJ?btus5~ z?q&sTLkQX)K^f5KoVB^X!R$3oJ+h%@Zk>taFZJN*CgzRk_C)JKJ_ z<)Jjn9H{rr$UPhDE88DRf3Y~+-w3=@TVqTVH{DIzW{o$=K;do%+o*8l4SaW z2PK*QcItuf#osh(ayhugo)U!xr_Vt1{xRJZL6N;?(sPvOyyV+O@_ogN37&0p%3 z>+j!QLH0&En7zHG0?<9h=|}T}@yL@n+=W#q3OAIh3se`IN?^B}hkeWtW}UF{G|Ex? zm}i{_(Hc|3qHX^ECy-u476ayE=17zR8?!+JJ@i0*<$J?z3O?U zJ37IdPF8^P(aOH0607;dan9U`+Yy)7`^_5Iw>eqEY*(n{AIv1iFiq7tyX?N<&<$jSL=nV^8Wc_MWw3u&1no;_@^7`pQMAo z_eNDk@r6~j7C_;}Pgwkv)~5`z!y5#TUA`W;1DIn}Y`aq`BT!b(C^v1ixz z<`U1L&fPgLiiVQhOr&In*YP-3^l~-)4Qm+qR!hk%VGzh+n<@}x;+Gg>wR(XO*|24u z$_t_ib8vdw9o8~e+ZvmwIiZ*fLk6lM#3fQzyQ#R(RB!4{@b!#$WQhivPfl`HCs<52 zQT46$ewwdv+#$RZKr!Y8GI0oNg+-}U3Mg7IxV`y(dJRU`%=?fbPk)E&{`OA?tpVJP z_d+fe)dVWdApw;}SzKf>ERt_iil%CE+<|{lTnyn@&$Uzs1^rmZ$

    X-@o-^a6hN< zOE0uwcOSXGK47jhW|IFJ>z(~_Vcwjs`i3F95E}cPNepD+17!PA)$+MSX!MWecJz)` ztdq+~sB1JlS5WMWrH{nLUD*u_C0rWzFJOcIStV+ZQT_(va+ZiM-(It)iv)ib*FR54 zFsx2GJljFQeY*#o&90V~6;4O4H<#`e4!e2c9xLDQ$i?`naa1$?+y#9Sj>Cv;+|S(F z2fz0g=P33KDK@yNNF{lzGJ2S=~)dGc{!J!6kLC=p+ZY zCLY6gUPl$FR1^luMb&i%)mQ%Nhrvt5pMT-2>@+<;UoljT`cCmn&5);lLfQP6I*?yS z9}DRNG;mPR3d4J%D*JT{vmaO@;wau{v8suzV5J;{67>_eKHM`Pt6(5eNedn*5PMNOXZZ4KO)vUIM)b@yX;{TKr zfRIZ8Ms{ORByUkw%DUQAA+-V~0?bgV%%^vwRX}DOOuO20sjaIc7MG0-_0OI zfk>igS+z5Tss4veM~6rwqe(I7EUp3u`y^s$55{usD1H?cY0Xu;&jb5AXsNo8Bt7{%J7I5Sjtq&@ z&d;fW34^GZg~n^M#D(uaemox(2olQ>2^Iqc!K@Yz3pbnT=PyGgUXboNFAHvO8UbLo zzG4bExRj$O(li^kE|%yeWkzB|qt;C%ax0v-GB3eI3o&XFX%7c+s`>OVl(LUMLvS=z z?)*#l3;mC&*_eAvB$I&Ume9}iQ7qKFcmyFI7AVyT{^fD`sz#?ZcX!q8w9#h%67k=H zLn`rUSqU&-4o+cCj-l@~Tsqk`fz2U~z{?||^n<*7%g1mpORW6jK&;s=8g5@*5Xq~Pmcn#`wz3dSu;dHYzRof7mgo--z{|eqV8|vpRGw~NlNB; zIse<3aGaJA4NTTo+He*LUNN~hxJ?60%O5uLug2OpVkv3yy&@JosWYQ~)fwD)vAN7; zHX4jhC^){qk+S}!akzOi%mKKSa{eC+`XCkqsVM-tkiAR7|2h3W8Zmn>@(iINc+|6+ zAr#>Ua2l&U{{2@o>Y&%$e$M;5Qb}co5*Gk`sI=)a!ZO^bfdAKd2HZ&foz@Tf76x^a_|4wV?eF`kGAsg_Wz2-4@o5dx5rr``kBMk zg|;VD(?Z1Xe+Lo{&ahk5^H+tg8LglHANd~0d$D40bLrS?26#tluIYx9FFo;T^Dn$k zOR18*@+vBXvT>{kEH_UC8n*z_$%KI;_f6^1v*6j85Fm$xF#Da2C$r>@&jI6vWiAZ1 z>-=G}W@DqEkat{bEPJ9R1B(dvy2Z1^B4y_;Oxrn}wz*EdS44)EaO&p3gkb~R7CxS~ z*X*2f>V#oO@>6^M4Fit$a2`M)oDTU&5ej@0E4(%1^CeMQ8*CKyY%GDE9ZxEwuDA|o z^h%XjlF6<_V;bTDN;H1RJ`(a0!yBO@mJVUh1EBN zOu)aIxT1aw&_J*FE@4APis3rarCpB$N0(%oE+@PeH&-hIz=^XRPDMceW949Jc8}o@ zOBSM;u40;0sWl^aDSxA%p%tQ{rjsL~$mQ}^zYcJ2?fh%;ml4{>eS!6(M53MDRZB+# z6`BLZwLgFEFAR3i%|6ZT5Zb@r!tNg2Au>t}DYV%K+*RU-WDUrWG3kbC`r^h2EaU5Z z!wpc`_GLlozHpaTrTLx%Z_Ux5S3}A(i5q}Ul0>_tqASYXQ;U1tYfQ&qUOqLEc4=1b zh+Mhky-Zd~3U^u-nWadncV=F8fx`SAxmZ()-|z7gKP1p-N>C`y)dgP5orcRP5MCon z%=R}2+xGC_29tyLbg8%IBAO-89h=R8J%C_5E+m47ILd^czAyK` z@80vu7?R+vC?xV=`f&Z#H##BGkgZaN|)9dfvwFc)0oS>({&r};| z8>jX*N_cS)fNGesb&bJ;qeGxwi5~~dfSTX*lsKtt{|D*X0DWD94`rp^==2PyNw~VZ6<3Ml`Zsm&xwy_3CIac|0mQ%9I(SS7RL1&|0)V}syHzHIJT_Fk(hx7U zQ|ryghMS@)Kyw^A3oH6L*|>j@r}P$XQ*ZT~&lACcBwe{Dnzca?WdCStoVbs08Kw$) zV^n2^veHR#b6sMj1?hnb#ax&nZ$Ts{yxmkNtsySARCJCnqyajm)qJN}s38aUm@Eb} zCQUz@h~{Re6OC@IG-XtK1C_kY&~UrEj%X@xK9~TRO6sH1Qz?BT9j&uNN|+5Vijum#aP3=$_vNcye$`I6J8-=BFMkw?K;Cs=m2Mp9ETG%I zzP{|@xWE3i+$PzXQJIa$WiS?^BjR`2ipEf%N2^r)=s>5OyZIvQp=ge4)cz24>%(|r ztfYJUDQ1UQybZJ~uQdr@fn-GvaI!a}mxjbjMC;8ZAPb+dNfeyDX*U_~prxgK_hH9w zq0?@3gH`A9os~-WEghz6?l^ax&Rhw*x(_?d;R3NCWvO=Y>U~?JjZs(N=j*TJL=FO- zn7Ni8RvQzLQ|$*Y;%UnBBtF$U&fEiZE9B@$W)ww9eGb~({im&I-kpXIEYhYmMx?E& zIlUcFHdT zFtAW16pN7_x-PMh>gM9_<2z&&<*Fg-uq5nXKF|Vdq%kDrh;pr-asq0;!lLcrJA7Sv zO~BeFqFYopr2+ktD|>mYVTc^F25&T`tcl2wN21CK&Y}&Gc6+pT9R&cW{j! zy;*kRBzH(MW&AzspX|;G+D{Z{R3vX`Dlz{Fpl?evmQG{XZ)sCC`OTe&{O)>Ntd_wKawc>6)HMX-Ba5jpYuWZq4Kf8!V z`=tV$=#eLA59Bk%Qa1w5>;C;yU!>r{gQD*jdWcV-H#j4?C+XQRuMIJ~xCY)|Y>`K) z6(u~!Mu_VV{FBE7EL=#znNa)2M2GWZtzVMmF)=ZDm-yLeasmxq%%^CcOadH;QT}_D zqH75X24@4>=4_&ZG1(_Wsh<7Eo1p@7DSKX2)UqeVzB6R4BP;aDiP>8}AMqZ&kzY_> z`DloFQ203liOj2@iqGphgpj1gRWgn(yyQdQjnuvA)x^8S>9&cwexC=K2@U2)3n1=X zmad0bb`(xdT{-wP2-d|0kdSDHkNHxzAq(*K5g&Svr8{@|u;o|^&P08Vc5877Zqo+o zP-cl`ofL^_1UQyg4{bKIvrzks>2C>AF>})1w~hX~T@y66^V%w|qV`SU{=i&f0#&-x z1Y(wN4v35sUA;nO`6wuROf58*rcC0Ouv7D05H6gFB8Em+a(9R z43mAD-IQI0%?8PP9pa}I_kbezAU=vqVoJv2qT*t=4)xmYr|9aDHF=?*kCOpn&%7Ew zCqwASpzKjvq%(b!R}#BTv4>SoZ31FhB(a92~8~+Osg!F>|`jJ`@MJf zHo|+x$1Oqopi2gyP_TcL;mZSzKqb);cgGWoYl74iZkPb0fNY_uMHYUozQv4vf8N_! zm8q1mJdV*s<(~>~0a%lm4T#a$pI$8Zcw9cik(`@kk?#l2 zaOT#URN~(&>E;ECUFPPmFtAMZ%~fGt)#F{WwL(#JGCIi_e$$8^gABoyt^wU%h6Hw} zn$V~>$^uH68tD}HZ$QAPoY>qc*4@slG^isWp-A!08DEzH(@!z_a)tlK^{0)K#2t_0 z0Ycq&3_;uRSd-2~go%?C*lInL*rSVKsj5w1)bVxc2i{J-jvgM9NkD&g7|<4y zfcx)=5FM=x=Mb3?@){w2zo;^srhI`J)rD!=hb?}%;h&YY`RnR*xkQLY=e=45!ft*? zAXYxsUd(e`Dz6`b_R}S)q`xpB+X-8&X5*HG^q&CUU8p)uVz?GuW5-ueAl1wI zU#s?%ugFiSY5Sq8oQp*}56O?R`Mu*Ee%gcG(_)(sv*KM?vi+rMtTcsNqE`Yqv?`M{ z!}k!Slbn{e<)+k5^ZJE~V}W*^Tur84c$fw`*yy!Sx!IkQ=amCUsiS@uIxeP(U8K~qz;bmT76LX);(QVV8STiuHYsH+6Nn;; z7#@=PxcTzNoRL&-7wgz>)WP$N^c5es$ccgSy9dxWiG<4}oyx#z5hq{I`X3*rD+&TQ zO90}BySWvC%(paOdhgA)!zBKsxBrgig@=o1=2QDe2%!o2BZT~oBgTjOxVzrQX@eVU zd$zsuE~X&85FU_8{__;>#Ckj<1IU>8z7Rq7zduS0Q5#Cj1oPV?07A|G#o1ejRn@&) z!rU|oxf|(h( zDH$Kvx+myV(l@HKU;C$80SZs-C4b_WT0yXjX0PeWC;-y>akbHaai(Qgth|m&6ylDJcYqL{oxe z>5%KI#Mbk#4^EFIg@vi{Ya>_`<2l~-&f;=DOx~gU+V^CBW#oqY8ArUhjt&-1EWeD* zV|KlR`mQ)vYB(OFpiq&K`B}U_G3P zhzD7J?(z5aI(21b=fVT*G%;t#B^ifw@mf%Qo=FtYl4@$qbep%-6>6(d6$+O)W3&!0^?ZMWp6ehH`!4+r8c{|v`8(HASMZ)+ zrQh|nXk7Lsj4=^Vx#RcXK^xhF&u_~6$&?xjTgXaN#P$QsY^M4sR0})zNyLeISq$%q z^hWLM^KNfEq@>grpNx$rK>+`PDD}^~udyuh}Mz>L;O0^bsr?Jch>{P_Y9-t{I(!j-g zrJ+o+G;yBl&}27;w;!&pe8qZedgGnZ-FZ-P1l^;#q=eI#J&sf0epAox@^S|OYg-1i zU(+#?45}GtKh>F1f4JR8Z=TLOHy6$8dJq~*DFH3Ge~3Je^1@L#+1~MIri*3q;kzV? zP^U_~V<5BoXi`BgP4ke6Pu=t&ub!WkmXW$(r}xRLQxz0c^x+Q_C}Vdn50G`h19ad1|-Ck@>UrB%NYoc|)69jUqf0|LWeT-lkskLw zZHLz@eqA!ktys|!Cbo9uV3ar;vI`K@*W{XamFlI`UmxEiy4Mjv6CUX5yRyPL z(b6gzbz&1Rosoe4UE`87?5YMK|7Rs`$HE4l2j0JHzA8We?^Zl? zj1)*lCGlsa!`@$T=?ZopbY&+%*jB2q0p38%CN|WNQI*)bh+Q8a<->(>MKBpwpzQHn10cf+k5WxX-(VjohiC{706Me|H^ zKZ_KNpz#a|rEDK&bPWqPjHY16TCa%^#_(LJwALq;WvW&l4WUppvHIAvb0yQA;VsYo zKhvspPILOe5_rH7bn&}u#3knFw>FopuLHufznZ%? z?%-ev|B2La(9~@L>?&Q+uRiyDdy)@*@@0e)enhBa808%KhlrdNR8tnO14av7Lrb*d@^zKN=-S+1?!b#r^F^nsA+;>3=k6iT|H+(M8jtEXE|#D8V{5HKXZ0mhj3S2honW;wB&xM$s$Q8bdhcog27-nhiU=Wlrp<%{5L(7j+$4EAQuLqQqN(8Pp- z*LhfoSlCwD>&_Mv%9l@UOTl-#8a-(l zymt?th!UIzIaK1( z7sM-H8#-dlt&(5CCv8to$~R}0>Dr-->c0N7k6xEc)@od8ik!Lq>rJulyJ3w4H-4_9 ze$g`M$RYjdSX!lJX6j(Pbk?o(0D}Bpk}z0JP;P|mnd9}Ij48BFY%jdjE@76^#t2cP zlgX}&72*)J70GJjuDdTGq0H#6AwT?yK4PzLY;o~(Kq&UWoJlIQpY(Flhq#En^ex7& zb+yg0h@H3bkiesXEi|p{4;W*K7+bKG#Xj%jY4qXa7~`RGX6+1;abkOmf&yE$th{-> zuGzJk2vMQ$#Y+Cn&4g|tMH6&;DaI*E9u4(LK;jZE! zhBJD>Lx(H0jy7Y~(4i30Ll}EM*rwM_;@CC( z7%)6mvsLAVeU{?mIU-TkgW1W&jdq9(Pn8&Mj&AwS*;d=vb%^kCm3;_*qbs-7pBF)w z`Jj~Z2aI^>0j6Ip>5KA4Kh17z3BFDeLFc_$Mpntp^1I~aibWc&1>On8ChQSBKDYVq znzwZ3Rr{k0_AMnVlnVSGZZD;~1w#5~M}J#gADO zlF#7UE#j0%XefNGVBop;>Kjx?g$^B^4OCx0Jn+bJD_2@EXSb{*^RdUg4Qoeb@Qf&`@yXRap- zc8YFB!g^&TcXxr8LY$y$(2MT;6Hh zSN^>W2?aft0rwy6)Pi%^_NWIE8bipUTif3wLOq#GgyRaM(GvMk=b9A}$d3;agC{2~ zJVUYy1qloE{|vgWa?9~*N7&E<>9h^+o;=lxdVU3~gWoL=flGw_Zh4_QgiVQ{1s=M0 z;!We?diYs0QA&1qC(lu4(z0YI&Ci+d>9*JyCP_-VOofQ7sV1?2ZN;~DB(r=)_L68= zXwtsK?Zaj zN2JF3+l{U{I;Jgh$rWD%1|<#q`Q7);1S0djis7a4lcpBM?B?k-_VQ`vwbGE=c zTcVyEP4LlARBiLM88*DTGQL`7EkdyprQbt_Trx&r?S4SjJRgBVCVu1bJ6kXXcAc@z z(rz#u4&j&w5-btklrHR38(s4CK2wA3BpR#Wj9X1lygs<1&+^tgY$dwP7Zj=|UPU2s znwN6AO8GDgLjtpFE{uJ4yy7c#^m7qUtq)YE^LO3IbqDFpwseM{NN79&MM3e1JNe>y z<06JDod8ws5yY~?4El^E5CSKy|^=5k>A&QTP@*O|gWmFF>YGZa3_L?g= zY~|-_64g>HR`o7!-7%lbfnaNP{?<^$mv}|> z(_`!K@TR#U{cXs^_yM7PeF!-Q-`!E%M4r}Ld_CqZdy=MAq&nW*D#>{`Zu?NE-y*^& zH|?EZ{OB&0?DA%hP^i7j>DGJXE8Aw5Woao{sI(fB&9;qP;asm<`|_RjxC4I?C3?a; zQ85;5yNq&(Q}sb*wdW?b-!!@UpF_;-_+K2Jg5#u)(m9ETvhm8yh*zSfhYJXcZU;~? z%)8I|I&s+1f%6eN5MBv4O#Qyavv?(7v*{dXluq0!w1rIG1*!|{Cn^~_gI~*Dms*gj zHZ9TdRrHK2m8v7Z&h#C8t$sd7cvkvKrEXu6DXET5=jO>(8yDN?;f&TenG z{_h5Qe`9BMv>35oK)wPIgHS0I*L-#tjEo zNy(V{{kf{fl(3F+XJ>Z3Ia3Y}X}a%~pkw0K24Rz;&MIxZ!w;fMA&`q(hLxBg(n#)-y#Ju=G&L-OPS{{mG}bY&FqDsWFDI?@D7kk$}&Ivbqky1 zuFkpo`lXXMcYocXzSQCT4jD_zydJ?oit#6)d?qRv0ABz98g9a_xDWTGwF z8C2M0Vx4L}q#T0r!sZ(B`b0!nO4X=y-^=Ngt1Vr(!yf+d^>+j<2q|S{W##n!TsC1h z=S||VGJnZ%e4&L(jSIQj}Urxp8Su#is;w6wE{%oc&R$pNa1on>rbRNl# zaXC3i0YI}L`|H=sAZGo-=JAYm%ObgYOT^1z3wHkqzO{kQn8GHH8t=?7_h`%F*)yM_ z?QjawLK@l<0RbcRDHbQE1B;t`Y=6UgTvJF_O9qcq@s3>XT$-|V3->s7nN$ZH&9iBO zN9$n2A@ODI;O;V>m}hD#0mk1jACM`L@2C72(HuVCR1%1rsFFQLMiy3glJwC(Co8jOz+GEQ z%htkTBnm*74}4A)&_N@pQ=o4Eaah?!Ai0l)>S#k)$Vm{+g`tt^WS#DYu!i z*TR|Br1xFPVb2 z(j#f)<|_ey{*qQRLOXbDYfK9qVD}xUbb8w@^eb0HGdD8RLtyZ~9bPiLwXrntbfT)A zI-7$_J#khLy**gJ8@j(r=(;~4S)`x7w@%WR>Nma-ggiW4>Pf!0R{dmaL|?ioP|RdN zL=cm}pz~qaoY!r?WKIdbI2P^eQ{oF4h55Fqs$hWoGorxCE;~ zttHa4gijy8qqzkkvY&G80mrEHIWJNRqXYZDelmhrA>Nx1`5xl%z)Nm_Hq@stT^*dT z85@tLepPqf=U!;0qEgGiyDKN@$Frg1&p&8!*?ipC6sD(o!%l&@zl0-f?&FtzuYQsC zbA3DydBMNChspkQiL#Bx%e_zHbx!T+o`tWY2!;C|tW=KO#vnF3`}K{d0I^G>+*>;p z*bKUyQZe}2YE>z>%K7C`o)x?(!fV^M%!K-LGk=l4Sj^UK$}}u4JM2LG&=!ckes+d@ zd_1#&z|qTycs0?)8tvwfVBW~_7eqy;8ug{A?ryg`o}Ipi3J|VJTyY#|rwyF!Qsrx} zba!X=Niun@I23!^+7-r)$$oUL=Zst-;-k7deX?LvK(@6R6xsaTbBEDcNg7^eu@bq- zt#7=|g#Y<0{+n`Pp^VquP8fwnxQMqa#$VLjnBWa8)R>~q`?xnL0IelcXdwB>d9<>` zWEjQ)7o@UL4EI*-2XgCtH`4ZmFhfNc9c`86-N6r-O;Xq3BiF$9-&rm5T-hWvS4ozy zJI-sN;+G~ZF^LoaCuHhM*m4GT+L#ve-JTr)fbV7JAC{4@3%+}-;RrF?K_9KHdFJ5L z`?#h*Q`$ol{U`UBlyNfK`WQEe8alN8w!|^AmJaH?y*=PH=jmxAXXbrOsr?rZTl8&P ztWUZ~`3BTjrtLJ`ycX^ciTe_7w{pKHE1Zr>NK@GOQN=m$xYW}ldwaIq{dAdzXQJp; z!cjduoKCt1dBiHmA9WbWRqy$+@p62R%}C^ZB;zh%)^s2HDGiXIZ*O>_+Tn)bCdWA4T+Yhsjc!lE z-D|Grj*Uo9ApG3(!{n1U{o(s!B?h|Jjz8YC1`>N>+sDP_10HOAO22<%oD2}nkGM2U zA!+NLyYyUD;vb$qr3t-Ast81S)6x{vRl4j*b}b|<;4{?AT#XAnK3ab7cABIph9-lG ziK`s%{p88vGojYOjBzS=sfN{Y#kFa&_HKFU8!J8JAt4W|?$a{`CoGCcMv;+Zzh;iK z^%Bd(`HZ6Hpx3K|TLR<5o!3MV8S17E;-2^I$NwN&cf_LF;SWn?X^{laG%H2#Z8P3d8 zX^0*_3@q9_(F|3;b87!q&1vH+XFyB`e5@1)aAH0B?x(hHgALV=i)9Zn^Ho~UcDxYR zT(7z+$^g#_t{umP?Nk$@*JpG41)cyo0^{bRC??X84Qej^Ds%Nut%I-Y^TLx?`VEje zMUOe{{HYj+627=Brn1l&jc-xbIq3e zv%Ne)D6zic;yLl*;_hwY$iY$^a=Im8mX}qjq%4(`INqD5S{~XLE}LCQtzPf|8&5ti zDzh#%H#>V}e`+^TD7i;0#x7i>x6fFtRIiZI{Zv*sGgFLkWNktqtj);C2JEjUW-v*l zN|9HcU3c?>;3FMM4dcFDP*7#BlHYD%iJHc&l95k^rBy$AA1jn-TmJa?g#a(#S z*g!X26sl9;Lm}8l>JJ=&ua%O6^X%8?QpzH$69~Wj6DO72-vaxR3uF6JuoJG2%C>|I z!!#{(g01j$1<<_fZQg(VFhjNRCM^l9c|p*bW}Mr_dLf@5TsyAfQx*&m+1QAgk}79MB<94^S0(?g25Sb zI`PHfx}VG&74=`F_F~=5eiJpwRQDfBd-)fo{jP!=l$xR_CZpNh?>7ECwsRJSLt6;e zr4}GCW`$Hw;Ub2qm2*!`R4h9Bu1KCaL0VVwjd@e|Ccl)`wZ$kv9vSo~@-ChaE zA|S>WCXYMhIy-86HVDAjOzV1DhfCo)khLCismS)*e`)XlZhvkQ8=eVz^Ey$y!!YVr z^Ey}4?fH`<$|dus#b`=*a|7i@D~eQF;6^1~Q+(YZle;x1;<9@&5WjBM0>{BoQu0J- z*?8+HKg(uPqOM|tRjU-4speInKfJW3@rR`TURCwt@-Hge z!ek&!WAlveH-UamSZ|-x*}oWckP$#}yg!46@-~3r0)LGHlZ5}`(PuUNfeQR5_x^w7 zy6=Of^_*ep#j*m?Kec+I{y33s0ztTpazq_Hc@Nf#{j&nL#D+bhisSeD@NC~O}? zeU&J#)1U-e!fxC|sHl`rYYoqE@bQ_Q9B{T5>K;XqkyqTjXBNh&@RoTVHf7 z7$=VIVVT5v7qxA@pXQGrM>vm#9FI&pAAE3p1q~cKT(_fz=uzyOI~?t2N8FmSEuorO zlYpd0jOG(n&-EhDPRy_I*r|=W>nl8yj;7C~**?+YuIYC=yi!#k_@0b56%zZTx?K_P_)jIr67=WXNR<~e z<7#5|(L9*hEJj0fpn9n5P*7@!c0syF+hXcS&S+Vp zw?Zp1ElF*Ko{#($`GOG7X1Riph#)#`iXE&FOcW_Tgr(l=)&Jrt^vl$>Byag z52^}HPzo6_UA^HnYCX~7U-y9>)-uUrWX$1Eaz$$d6cl~1Hh{ra?o8*|89E;Gx?X^7it^gp;|z&@vo$Og<_ zd7FZXJJV#jJ^wY{QHEyi)2kgyS-ma~ismQO_+wgFV4MjLumwNx;^x*GqeFnBJWn46 zr_}FUd&NgoZYedjtNqG-`#m`I*OPOOH5`lq)|Pm)+VY@*y9|Bs6HSx`7g$CnBHh2B zakdr3^S$vzH2N(Mo^3j%26a;^mGffJbWbDyqr(u+yv`vt{nisg*7W9; z6hW!LBQSfNvP{VnN470=O=Yu}`LJHK7okqF3~j|cKf-NVkGHq(Y?`M;4-fV0RV-QV*c*h;9^%zvZkaBs#O+U11!7G<4(TTMRs6 zGsL2M8X|mi7&ifo2cOK+C=We=fbiN*p*HVux_EYw1;f%_10JoI;G0!c=!K&7d1AFS zqee63u=8o0G78070r|YING=VZJ1X`b5Z*YeryQFn5qNu(We94y zAJ#v3;GabuhXH5mp5mEV5}i|6jZoGvjDl-M^?;L&)wJfopr+2GX{TnqU+Kt6J7Q(X z2c~!khr&0=Cr;agjern&^*KgXFP?iuTz1+?ad#UVPcXS9F`EPDY&iXyQJJWX#2xoK0#Lf|LfEQ83A5eT7iR3du07a8c@X|Vz<{c5EQVM0EX>ZW#>sMd@T;2Y@wtw>{?5jC7Z;|c6f>!m(nfkP;x1>clAZ4tc_c+P zGy#=Ls?v(evXa>*J9-#0?=FJ`Oc*z1{G?TOw60E=o^(6tkP+R(8{8;DYZ{2f))GVb zl(yK%=11N5UjUW*Q@|uS_cIVFL*uI>#FL;?@7i5OcfPOvQ#SJn5TEo0n9%691%&0y zLGy>}mgaT0|Mg#EOtwEXF6vBQI!KD&`b9hfDp+^*YpLl>C@h`Q-FWYaPagH+F9T~N z@o+XH2&C8J-64QW{wY2o2NfBVrXeOvGQ5~1oL4ViPj86{jcNDv95_tm9ERV&a;|y! z$;AE>#Iu6z`>#y@&xV}`SbwzzNo{a0dtBrU$!3l7s{o>?x9=|f48MNn_OpOW0lAdz z0#rK{)iexwm8N4GxV$u7aoLd^%oY0GEoKw5GtHE7Jj!bswAaq#w70($0Pas!@>FrK%U2jV>TYiI1vuQMU+3{2eZ#5 zuE)MqPN(~I_~+DW?p~89h}ge=)z$9`>$?&l*oq)BH=xblQZQf-*din3UXgT#8ZMNTqk^0Pm%fy$iM1^Dbe+DaKCAg9f`f<-ZVPGepZ z@p+=3c8ln~=)ioJn09_Vk1{A@&r-teY-a?(q-tdgVSK6PVY-lTX5yAw4OwPz@qIS3 z2zg1(?)Xo*PG-=5^=|FrVC`9LInu?aH8hmk6dLwpAz!L6j+xw(2jj-~1^N5Pp0jQ~ z+RTP_+O<(uq)WbF@))S)JRmDL!a<$sH6SdSoyvK(@BS%WJX}|&e||p8ZiULmYTBCP znvh(2xxz%cgbWb30ffvyL&!E;v%ybef9g*wU@tNO7}VPGpA0HdZX=cO zCR$P5;Tt@j%GKWuD@a2NTQNw?Hk8^uFwKW|Q&octNr?Ng!&Tw@@}A zDd#nuEF-uZ|C~)^cscH6_#b^#;#dw?S-D&t;I}{8rT<5!C<7Ra_Y61?zC3kNAYj|s zX~RkFA)qGetuuiNn5+a8eWetq%Fx*{DB^pdHIV*>YNw|dNETV>83teV0m&joe2i`? ziZc_+9~F?fDMYP?(|fMqH}^NJ2XYzheP@jcs$zo%5V>sI9A1I1M{(F{r{6#1lo(qN zKX&JJZ#qcy*6MWC$>#MGNmUoHvy00_fBN(YQ%W_rq`~^Xb|5G5{_fDV6%TrPGqbzr zgk89|=aYo+a3#?#3&YG>Hvvzdt3sYD13|oPhbPGw zGoPfI0=iA%M}?x?#hHFEIIsEc+qbrnqQm~BB^ptoj8bmQBHDVTGU#HS`W?O2Lrptf z{DGXQ+tx#IiXXvrb68V(Xy(QPkm zsFngq_8)Xu#)c^o8EkT3v#y3@=h|DH(SJn5({?6vwQAwT6-S3nEu`Mvb9rLC_lR=5 z<9t@DTUShknFAb66t*ONr?r)pfuS%{dfDcC&#M{0p~488Wn~Pg%j0=f&AP)c|B{RS z6mONfLx6_!6j{Z)YsgY**q0|I?8FI*jIxAD)PeauH=mW2T>{Yd5kMySOW#P7)awj1 zAHx7g8NIdfQH$>jP|&4HZPw|(GJa|wm>~KL0aLBApiHODmeXCB%~0SB@XKb~C$}GT zLz7#r*?&y^@jB{qx8(Y`qR_ykySlq5yWOkuqdr2DN-30|#N#h?Tx#6eOu5^|bvX6P zc#79$w#CB}eK*r#<2#3l!Rc}Ho3_*wLBC+7iskfYigYGpY%W82{7`S|93Uj+GnCqz z38E}DB#+^Ksu;N}dKlapl6oYau9ljU{l-AATU<9H1TZN956veVI)w ztDD<8{IZ2YWC--pBx_lrRJ&YUm<-%(NKeR&p$_`-21S*1BY3bERk%_`wXc=)=~!GG zU-y*!(+8g$;%Tq_(k%ZZ8tCRR+qYn4_EMtvpM-e>3NWR?uM_nz+d<$s%!Em(DzV^j zQKwk23O2DnWIs7(SuwZDPo<)K`3;PJ{pa4l*%-`Qbd5mq=gjm+V@OYl84+gi_=&OS zwRDL~U=#YCDYf-$1M0(z&$t4PP5dLS{26Hcb8U%1)dB)xNr>|0orS%<_tjr|!SBOa z)L*C1fEE9zhVgu>Uig32BL4m9Px9u%)_ty9ys)|fjpM})6mU5()O++stn8L#_Q>-j z_)k@)AjpmvHw17#^su%>`1<_`&Po)vHU{}H{ik@k4K^oFw|3UmovAez)Aj3Wf*GDT zwa@zi7|=ZO_L%@*p$avdVW$LkP_Q~7FGlOdTcr_>Cyo8~UJrnW{UjMZ+du%7*} zN_ep@HUbW(71BUh}wh8d&v1wRVB6;V$r zoY&{DusCvYwL31o_8l!%I0rL=B>@z}`n3(p&3sr}`bxsMv~+Sb^Cue^v^Gjh6^z{9 zHt547m+J(+$9KnLlVyt$qM|q|@YjU5AI9lgJzl{Nj&3V4?{?nY%#?;;Hrjlr&tszFrA_h&|uMKQR|8OV<2U74)w&Pvy?6KbFvNI?TFhw)Uj0Y{QT>qlR zQ)<2t^x%IfBTm@z1d|5NbpLu(_C78gLFa8?GSldCG@pWqFY=YmY4ueY{bq z{PS&6v(;T2ZPyv{&_x<_&Ho1m1NxJ}xcyQtPJGC1?)y62{hz!1A`jF)ypF0Td0uHZ zhlZ}%y7^k9wbbA$_<*vzxzKa+U|u=lD4#%3F1ay_d%WSiDY!4#jf@WXJ^^N+OCs^R zQrZ0FE1KQhG&uV$enFU;V%T1Sse1nw+IXoJq&dHq{A1^27(&)ZrXn1n^)PA*> zud{oBazb+Ik=T2RSC6SLjZNPJh?aSPE%e)p^(z$Ik5hH6?dnB_o`6 zzH{1qcTbRhz!7O}HNCY3ST`CRb{7tId$YLuw zLkyBy$*raAlT;j-{-FFBQbjk_@^EFO`V~7nvZ)g`d*?slfA#?D8HNJcY&UVDw?w)M zhB)`xoM+9xse>=h5s_0+)=l$F$ss_1)NcHec{R-vn2vIwJo7;H`}W4Io87e%nF-P_ zOO3h8sLp8|b}LOUxyXI}4oMu6Ac4f~q7C;$YlS7paI?WsZ_OwzxT?H>(4{;Dnq_uJ z{USCJjHUfU>Fq$e)R#sFxNXG@?h;2hxHM6=8}!a>7$|pEzt;DK8uxkCHAmkG5?doz zzNo&M0P3qc_c(d`wb|g`Zpx;R{Hi4yGH=#?-P(5lrQVeNWc{|BrW*kA%qf931SGb5S=@8*CR z5=?@Inp3uaE%-S+!!4g;{m|_<$w>TvDXV_+@jzbx7FvQjRvI8tA0K~`OSOEaLVWR; z9D9PQG7aiV&ug5Kju$bufsZo`=%=_{e%!fueQ^Vif*AuIuH1t6lEww#f5D;jZ%O|- zpYT&i^%Ly-(O`ne>LAFyVSkO7)k^2`_3J-#AV0BnhMA<}0g(QIOx5gG7Dz{xn!+1b zX2&ah0dRBP^IsVh<8^cC9Vwb)Q&oKv{C-f&>|AR_c=zv?Uedn}Q_5W)mF3kHdF))N zB~WVMdG%@-kmV>AKFltZ0wSQjU9seJZ_J2cvj9+7aLlYq%L-VI_|IIw2!g`je|CTR zU2Y=WG*BO*jTRru9{x$vdB-4AjL-R0mI|A|e*Yr^K65+N1)vrg1*NQl9w%yWc&Sqf z?2TzLok}FL>8Py9^9vCOMzD9#f53OWzHT*loEWyvbR+hQx~Q`Ad$}JO=1ImSk=X(> zOa!BL;nfQ*B%ei`19~as|35%~>Q$hFlk;ti%jXDq0izIOeI4b=i`Atn0ai!rJ;&-bVF~#V9!^9T7kPp!o9@bR0|0qDZ`&3J)+Xj; zrbZ6YvL!5?W?Qb(;B#}V)gC8}mEKP0cX9%%C{ohfsw;YjH0P<)YWaL28kXon+TSP} z>I}215yZyJ1{xzK-?@uvF<_(FJl${HT@Za8A3L7vSDo^bk1---)gPaF#qt>nUtPV0 z)Yo$jolk`Pc!_bzj!bgT>XiD*5>2v6Y?zF89-mz9`%wU}^R?RBr107JB}N8JX~Mhs zG39d0cuCwM#S*Z`FfR1A_5xxsR~HVDx@#R$Y0v@!;j8UR@%$sa>D+D3k_9#=g|*IZ zdBWOM*qhEaPnR(&x!j?TfW(PW_Q=hrxcWO3z7Fhro$=mWcK!wfBDmNo8R}E@+%5?I zYdB60FQb;hVYvX}I+g>73t<4RJOqHao{$`+{JQ|EVBWuz+^5-h;j7qfa94wG&>lrD z*kC@P^vtq<^rup#Rb#E5Gg~fEYEfYhIPkV9tgLp7GxG+OetgZ^CE#bJ7F{2a_PBi^ z{2oPY!^E3iPi>!r@l3~ASs_5gtzdF4oB1Ip7cHIzy6i`BD=8Q~qKvorm7D3-$IR2qzSvN;HVk|eNI!nYa7nptiBvvaaW)U~< zh1^b9n`l4NYp!)Y=^sgcb(rww+#Uw#km*K686oCg755yaYoB6OW~RwvI7_dx{c!U+P*fT~C)B))4(jpP3d zv5JJuA88NJD3t6^wx{e666MtKjCRF&%B-I5Kk;OXplj7CdLNJ`%VJrR;1<0+kE`i0 zM|>f9Z0FCtG85{w5O=a(TVhVaYo$|P?|CG{?O;Jf(TzOSrka!DO_@8`BxI+GVIqxc z>;fyR{VI*lzm0PZK!EwvIcMi}S1yMfnB3rUh~E^8NkBQWVOxm40a_ftUD9kd1KW+gnn@t$UsVopx!k#p$!iLewy9F z9GI&?ULIWY%d9o_vznxhupJ?gI4A0dB*1uzzm5e*kD%EVqhOQfo&J4sLAxwF^z9rvU`^-;Lwn zu<<89{TGRzZ;gNPrXS210)doWLLs_gZ*MR3n_CIYjmDxwCS0($S-AbbX7&FqRsJui z@gG|G{J#GMaP}n0S>L0yTIhzy>-azIefL5JE@4#~(+IKhBhNHz`zfC0=oKW!s;?-w zXl#U0;%f)me7`fW5gNOySKvK9EtD1W*kc9i-JR+seq#0<*mLZZxwKB!9QCEou+&Cf zEJ?yyDp$gZliNV9!u)D3an(#CNT~y3me1Fiv_oJ>D@#F_%PrtlinE(XvU|C*o`P)j zqzyUP2?kfH4-;`mO4HCb>P^69Sg<$H3-}XMEEG|Ca*vO!lkhuQNjfdhVZ!XMHF_$P z2*L%;)Hj1AA*H2vK|mQpToKEs^^g)CALjq`H3WBTBNVziUq~5+i1>+exwbB#+!=%3 zhI21P_2RS|F6$X#d31OO&kir`h=XR3r=tVFx9E-z_4eDh)d@g`&3UL^J3B{-{KNY- z;5aEi4s8zDg2@J;0ElvZFb8q{)>|GQeCtSVx>5us{aB~2gb3XH*p7FjXRA-*D8&C( zo;0P|vK*0EH1BzD7s%R3Xr12c)M-Kg z?|Pl}J+shTq+GLzbCVjg)vF(xa$5tb>x#nNw&Z}IzWwbC-F%OsE;v^%_mdD~r&*oV zMinJ*Kzp50m^Z!o)pLj!{OKzR6@!|`c{BaF>FWP6tT8?bwYFc-?TqiN*~S>kCy{>? zbu*Stc4CKAXPG;v#|UKY3-2ESOWLh7$jF(;kL=zIpx+HLO|X7I)-q18P3sFBDbLIk zOB&`Wl}iMtGgTQU$`F|}vbHvAA)1iVtn)A1_(fjba-zy_`90RBv3owu|8}eGt@Lz9 z2e%Y!9%lgK9B`sAWM|%aJp266Qm&kjOo)mulg9V~=CV!Y9xW=mPcbhL=nNVZddwM* z9 zd`xc5B{+Av`Yu_KzCb=Wi^7qr$42uDOWoau^=L6*rbBfm3$`?~n6$=njBEpBjXN0H z?bUf+m&cjUnppO=5FUm}e>TOX0w zn;lW~2m`HzpZ(dJ;d!g#Y~2vkS-07PpR}1^{y#iwkG7cv2Ep=DkUd6Y6h4?|**1A@ z7`;1b06yh98%hh@?t2IR=~@DGZQ_t*j%E7GrM11Wr>R(=#jj7^y-b2jJS-J3lW=l$ z0FE>^wECJy7!aF-WFJ?rVB);=sOL}jxa?Exl`w4L*B2kQWuZjiUWQPu+L74aKBR8wKNAjBY8ftCyi@oB zq6SR2exKG)PHxiP6>nnTTAVU~uqDYQZvoN~XmN1e0@fZ43Q0J-a<^G50=bOl>WW1&6lCHTj6_Ah#ZQtZ|C>abDNlw zpAR!s35h&0LL`K%eywNr-Q~T9ny;&5P#y8U8&{Ad}2uB0o zNrQtk7^BfdMOinl{8iWoaIXxTjE1?7nacmmzU57Fp`^plQZan*gwc64 zUJA&b9vLed83nvauU6S^Cc!C|kuzE@6J~Wk&Rv;pEes1IfLjgbz#{3)KWFzRe7rHo zSVu)ho^530Z#+Mnq4Su+mYOuNt0vyIl5@2PGqp#dSTGb6fB8pr@H`=mRY6@z@)IY} zt3%EURP6BBW_7?mefc6qVkgge z%_p9VJphXwhbDY9LS3AM=|R(g?EG?!US7g~=WF(=&F*8u&-0Tf2bnGImi>rtknC(N~+ zthVt@o9B#*R1kaa1k#>p-8;p<)ChC>q&jaaI7Y&lJZYxYw(__cnW@vd{>xAs_o z%wkJ3TdolFXJR0KqTvw32~dAq$GIHp@^-FGI4A3Z$|$&9BYo#Jog%2{`$W%6I+ear z%S&Vtojb4DYfJPF`rJk{&yiR7ilxJpP-oO1=yz~*j*q?lB+{$zIM^wZ@nD~OU zo@I+kSBd5X;jNXJQXGZ}5TE1Tv%tDGXdNBCPonI=$7=C)0ty?L#! z?-YNl&pk96d>+oPI<9zlBgFO|gg78ME-rbpR+VgEyCZ0M@rnV4OtK!B;XHu7XE&i?V~>2@u0)CAJiEnh@?>9+p=;q5I0 z;@GydVRAwU?h+tC2=11~B|va@cWw z&YhX}&-?9PT~$z3yY^nPpY^P@{j`Hlc8j?*w@kjt5%DF_(Wdj-uT+~Ma{p858z9^x z2G+y6Ir7vhyCam>?AT97c|z1VO%Vg`Lx_yz_277LAbEN#wZd08V?awQZSC-v{8-AH zziUAO58*liAC-yr2sI~0tg;^NRrTW*Kg5bKqN4=|4!5JlY z`wwLi@PxE-TsL@b<|T;APKMmDIsR!EqlXC=ez||U{|t_7bwiQYh1sc8;g!^Rym+hvHZMGiXz&>y(2zRJ@}uM$%4t5qf>Q@R^>qJ zaSZNJ0U?UmZdt08| zy3Z=Sx0(?e6x z%z)wEvH+Yw2G7yipbwY?!xNa`NoM5!yve4w@C8pgiSb>*c)jF zrz>(ow+Ob6$k(=0@_M6b{z=Lu(!w$novQDK2rN9CYSwIL=(A8e!FH6*&EP6_iw~b_ zYHAeI^9e#iH4WQ!^IGSPd;|hIf+p?Wzn94a*g)dqG!n<*@ooAY-44_ORk>S1MlkBN z_VfSr7~Bs8nI-74u6J;B3}cLm{hz_8zp`QeM(_Rt(GY&~9seSE!nqd+zw1B2Guq)KPdJG7{Lf-fkbi(^f6^+| z1uU=010GKQtQi#+_VQnAM!|8}|EJAS8b)EH6v2;b;b89K>TF?R|N9rn6o|?N;CsXV z2L9`fpdc!nyoH06tMwaRZr(S4HB>f98#`AE=QnJUb|$VCA1us3<`$^J!l-}W#dBd) zQx1g3f!(pKHR7bzU6Er;N{Lwa4)_D5m&abuTP2O;cmQTO={8it)YHY2L$C@}xQ1w}_nXynHbQ{un zrfc7J2&h%=C}Vjo6~Fz)!Q>?0<=1C^=tsTREMcc@FsfH(i758^F8tZz<)S3c&hNvX zoyxu1GN?qDJr+j@Y)u*idY*7?H!~U1ursfT5IG~o`J%hq`X3>;ReoC;_M>BgzAeJVV(yM8& zff5r&f%oZ3?~kUi+zeU2=AX#{`-8=AI4g4@l)e=g8-D6vrSayCu(iCB1nzW`mNj6b z>oHMTA0Ue9TZ;VqS*`?vHd=xaavd6{+I34Lqy)a=(ETi+(do_6%ReZ-g?1G?kLh%# zWle{EF<TtKfoSN>p@8@uo>jI}0o;_K16N>#b5Jh6v=9Fs9zivSfnr z6d~iMmuylMGB7Bvp=2^oLE+|}4S#9H*BReXkz}=ytiB2P8Lj@JvJMX#fd)lsayu82 z*2F>IBW-Z?E@~TJ^IH(U910ID9}^Ob+Iqf>u+kBQ+FHDCAYY!wnZJ{sJkoV+)S{Mu zMZ)Oy)I?LG*0qD% zt5&gwUuaTF%m=;SjZ>%&CRp6u5z~VVW|US2a&crHFtq6sp8k!{a=-hpLd(tme=oGX z8iNjt?AY!1Oi)eKVry31lyCHV3yNR|V=q2lt_g3D)CHF@ zuErECn%Eeku6ARl){5=W8*|j8+J*bdDa&=A%?R3pcpDQ z76W_2$IRyhe=t3>agc_pi&j2J@$;h;Bgt0Lrt6~c_QcB&v3^SVRcOtq?zlu!lqn9Tk10lseqp3_ zX@)splH9R?9bTQRYKKo+2C13;FrA3bpt6{e`Z5=ayBxh;xM!U>|1O+rnt`_CoZSdN zA+~`c&q2p(>Me$t4E|ka+gwTIhG5#5qb}6Q-34lWgV@iVp`TYgv%t1W_Byl18NSEg z9d5>#uoogEy)g%{)FJ+cTGo5Jjkm><+8GpGeHvv$i$!lfCrWzE>){!;qG97+7P_g< z>cD&&s-FL0@FMdo<6!OVM>Tc+VVR<x6yB%kh70 zWqQ@+KvVDkVP!J>M6ku)%QEq*%bs93v6o~>{&2@@40`anT6@LApdyC#y6t=^YyP$a z5b{E~iDW`(u+7}CqCG6=XQp=UM^eRCvsDah?(c-=TpOrgPg)t*e$3^&H!3<}_4fof z{A8Ia49@X1oILGZ-n70D7bY=sMv}*+1cW^hGOMWnq4in$@J(l6<&K=na;0o0O2tH5 z7jffGAy(60?Z}@WhkRcpw2wp!Pz&Fptvl*>Gby;%P@CJnDD};Kg{&*}OK*;{+r~i4UkMm+g zaaiZt-l`9$ugyG^9*;Ek*|6_0((8$D0X{|es~Z<_oDr<}_)dL0&-B7;$+W2Z{ewj} zs1v`Z;UO8YkvFCas3UdIN36_x$fOB7?6+!(YFSU#ZPjFNj3`H~;O}F5Hx@^3MUG_b z*?*hkGdpzAcw?f^>@rqx;kSK|DX%mm5`G}56l><>Of>$s21Qc&&SUuHd-nbCb2cx8 z-uxyIMS6>GG?xuo3u}OoxfTwB{m?9v+zA>&eEUf7L&OVlg*yKqaTE^+ zV;uu=L{Fp!SMn79X2x*y{L_q4_j0s&!=|ld3bZhDMP*ZSGj;v*jEudBl?5uBmW?^w zYvBRBLuHe;u(7gsee;fw2bE3C#??jH!dV<-?+9|RaBzLYi^?VrvI9A*IhvTk@AtvN z-Nwv9RZ8qX93L(&c0R5@C*}X{_#7j0Ies6YP>e5L;2^-O-8_Pg*ZIDt76J@J40h-%w zl5s^e*pa`*g$#;^fB=1%>#&^K2oVs|*N!YGB7fTH%d`QTR7Cr3x~>n9K&4hsy0z@W zb>;kH(&+S;a8t;A_v|87y++a0xHO$d6DU8GnpUulaA4SZ2zwvV@n8ylxp+J^Cn9S( zYspj;c@U=c&T`XC+kZ>06B_FaO!0O;P)w=y-gntHAf1W8Wajs=DzMO>JnqM*R57iFzw^h~d%nFtO{XW$)MVrgGOuq{0n(_`1lxQy}Lse}CKa)ET6el9nW5 z!`Cp`jXp%zR7%ChGQ_PRw%;wjTdJQ{t1Hr=Hp&c%MdNXvUkO9oy#+n7ez`Ykp?ndg z#FJswVX+psv_-z8Q%*tJBjRz}aD|5OvH1hC7CBfCm)RAET-TNVX@fAyrif&0?}zTT zp9-rB-+2Yfszp89LUL33u+!RYIqI^l@b~zAF$caZpPRhcfsl=BHRr6UK|I%)Z)ytt z-JT_AdQE)+PuIj*V*)%CqzV8lXHAzmR{7zu-ZzE1b22e2KU#j3juAIc+05QKy2AkW z7(V7Lh#b9+{X-OKk=MHtbVmXK(tyHRuV%F?2!R-8Fn)z>vF;bI75&1ztwqLuO3^W$mpR9ITQkq>8SH2nTXL3@oV&F&jB@PZX^6lH2f(bLnbcHw~ znk#uH*V?wNhF4pfDD*sGx2hA>|r44AFHe}7xFw5rth>HhzE9OhWnn>t8M{ItSC`7O-yO(aw?w+M*tm8T(15 zVZKJY=8u`}ch!KLS`87ZIhEBcvJ7BfgAt0By;sMtO($El?Stvq^0k~!-+U5;8>Vyl zIV|GCjpH^~7T$Z~=I~b9LTAyw+oTF+Bp$nYCpB7zI>X?wCD*a$>%7VgG|_UD_Vq-K zx_CKX-U*Nz|8Y)!IW*57;0o6HqE$T-WedBeDsmlGS@yrBaM5$BbLm=%#w!|7efTm_ zPru+{-tjGE)15i)w7-Z1DLAK%xANA<=;*U5#_oDjRrmO)Yk3PNwfAz^6jL*I-Sq8r zNrY$=&EsiGpG37PQCGt;XVR*iMBZ*ML*+bQ>pb82U_2Q^Dc`5%wU}g(SoyquhqY}n zTD_M%m~!UDBQ(>^FC=x?I8w{OZ_m~IX`sF#_*}$`&sA6Zi`Mm{Hycq>arwNlw)az-jO{l)|@ozLY}moKNr4j1AJ%L}8G*ELl`yH2z3! zJZcWJhs2J0XGERZ9}poRxCCnx-L;;tSQA-(ufbDF@z%M|VHTO_U?1|>MAzF(v{wWa z=IQ9(ci+6RWi%cP7_cUBDRXCr@MiJa38{Hnu#PlWJMW!|C=#v=E4lI=qNnjnxZhmQ z8$`XOrjj}sICkMD3TtYXmjW#XHNxZylGe;3+DN}&iR8lY%k4-J5r#Fjo_Meb8<@9`{)lH2n(CmQgLpTcGgPeva$=0{=sH#m^0iJp*fMY*Txc#7EJW;9<^F}mjpGKw2;Yr@S~+!gT`PK)Bq#P&h%3Ch@1_USVo@F*%0dBUAuPej>O(U!nIzLEmlHzzO`)+ zTQ(a-8x)qpMp`KT(C;@)t4x4FGc{V?-KI^&iQCc*16ciuGRH-!0x*(|nZYfn++5mA+015w7WA??tnPkmbNqeQk?RVv#W``YQnxOi+ODhJ@s2$X(b^Hs{Lpdm zCnzTR?|D6HFZuwXT-1^koOSZt7vyGBu=U`NH-+Kp^^may*!?6~)TGjHK2Dm7P=mIt zSD&F%=;(Z#V@08eb!nNi$@_1Z37RE)?2>+M>q)z=%iOTf%O1w7I!(@%7^ zOKMl|F~qxm`Diz-<03BVp63EJbD1U6E9vvUO?a!n)W{~JZh!R0DbQq(c>fsk#i4ZF zfjPfuan1LgN6l&}!@aO&!r^LZ^+jVEACX~q{J}!O3KZXjUo9WNwt#ENH`R=M%{=CH z`h1yEt;zYGYTE_MkX@r$IqmX2jf`XH|(IM zeWCLCeZHJ}M%sK5BnBD($?J<$3baLR_^z|Q?|4f3IP#^2YCHN8as&+J_2S-umL%)uXFt#;9x{gV6U2`wL)&ND+4Dq>A)G5atA;asI zErrLL)>&#TqgXk34>R@orsG(w%=F+p=-%M^PN#iR1n}Pmqes4dB_A+h;P!Lk>ja1l zSemP*u#5%kuE&Wb%xrI&)OeU$>+4;^y<>_M8WzX5<&!5W^n^5QqxnC&0nU3?{iZ8J z6#-~xjLBY3qfh>uiT=K$J2&c{CY7*L_q9}%+Wd8?c9>r8%!?7b6ob!n3d8TcQ7f+p zBd=ZPZggF*pXzDmI^G&HI7vHl^?-_H|(!zIdsguccAs@rg-DyJ@PjV|i); zEM5~24t^SeR@rO5So0ICf`w!>dPySVJhfPgflXc%G?EzR-*Q$H!-06;k`hU>FXj%a zCRKcNhJzJ-P-WQSkuOYvXbblkaA@B17HOts@{gWS~O>wGv|^G zaG$bSu-x7xk;&)(2=$v_)qb$as?C*6|4Dk4j%WJi&P0Qf2P&T7GimAxrJ8A7TV z`0;na{#D)F!{)E=JAdCWb(?woeF!Dw_Z43yz^TRF3X^9IDf|#Bz<6MKueW6)LI{Ry z7X&CzveM+%HVcqtB^7@7zqJ4X`J6gQ`(+cQvs&2TbaA+CR{CVL;FO5hL?i!-wOg>{ zMlF6D^Y70J1%WxtUS!%$Q2l-lgul8LfVkDkRQatPG*`@HO)|_W<_Wd_j^DqfS+^5< z*>enNcT4f`;*_G2busjoX&^$7N6@b*+`vEV*PEi=yw5%OOj= z1%BOLAVkTax#MdcET*W+0j6gAJgM)4r+6agsd*e%gB?cOS-wpiH{;Ndv{!q-jK_oz z*XoOaVJiElcI~boYZpwttM!D`41)BgVjqaDhtW-S`WOy=CiOQfW&sNy@W$?zG#{tz zyW>uc3hwp#pURgxI~W?S78L;Ut5g`rhFM9qQprVMi=G@Fc0Mum z@>%HZm&X$Qo{UhsNv3)SL3i9TS7tKHf4Q?9sEy_~PoPH63xx+fMspXRd%f zb*|l|1 zXz4fDP5V|J+J!j;)SNAlV^9k{T{-u(*6$<DHvh@Fke4dBTT>iF zyW=I$C zTr$sJd$pvkLrZq_ii|#p!hi32X60(;ZhHu9`=a0wbO>MUi^^OlP1k!g&HxyXlNcdp z$M4g`Vpms4S;W2boQlsIv4?8RyD>VK$~1R(1I0nWqnwDFFF@Y?bHn}U%dqyex!>|^ zOio3^P=8#%)!J(fhQHOv+t1jv!av{TBv-2tz_0%=EdYgaT{q=wg_hhB1^%Z{oc$@U^QupVn#cLmw(5(B}IgMH4;{uCIPEeNcwA zo-r=mhemq`7gjSJO#6TgEDc|T3HXK%roSsfE z55XErw~y6l8!k&ALv5ZOwk|`PTZ`nYD|H5Q8UD!XFx!n^0p?aIY89*jkIeAieP6O7 z=_)i$$}RB>6N!DJ{Z>M?CP=A>L{VF%-}rLveWdXh{o@ns5J&!^vsnJ>pK0taL}x;@__uVv9Ggv$3=h=Wg)z&eb=L0>ZRj5+f?RwT^|dGD zdP!$=?jep^QK~6wneaQxIw{W2c<*nZBEmva&z?A2;?wO=|d z{pycWq2N)v$HLQBanEr~&(5qw#C!v5;ZH)yc}^ML{*Ch;zQg$zE_$JIhhO8;Qf262 zrw{|J@&N5C=Ej|<%KM}e!;$&V*xW-;OlqT_Eh89YMi@HM>jyD}!r|SA-RbwB$g_G* z=8|*otzx`Ou?kJk3H*kyV^N;|EKfzG>{#7!m8pKUJ+xMMTOwuV;d|UfF~_6$a%yK_ z4IYYJqDWMUrGsTet?+UEigv(UMg+^Bvy4MEUiIEkuS4&1;h)xP9NA?3xx%>(F{uXp zsqB@Ge_UBYH=&9To39tc4QYN)zyH2*NjTLmTD+J*1pZ~;Xu0fS*;UWdR55V;^)%h$ z)_q0MMxvUhDqHXsO(4(VH~P~wJxEN5;WKqiQrk`slHTQeMBSJU+mfJg7QQPk6ljux zbFJ~i_zjuVz(Ko8Y>$WY$oq|L$|^@(HtmWl`KWE4nd^(TzbGGK?ls(o4O1m&{$r(4 z=z#N<{>i|L;Lxu}vR!maI~k|Dwk=?i3Z^eH{8a_?&UFG*u({yJL?hJppVq9NlWir7 zJcLE)R=;2pb2nP@@rz~w#GQdFm~RfgB1C{N|fKrF=!5QZJmo9_x1-nB@;Z zBu*q(R@=rg^$!3r;OJ`($|^cb*dfuqcdS;^{qjANv55T?st^af=!0^Z6iWX%Q!1Tmu#%Hn-7v2$4<%Lk zHbGkIfjrR<_bY!zDFAlMyDYpO-f(aX-Y&R-R}?28hs@^3z6Qvi+o*&Yes(nazIk#jNXa zSx(2Vg|LT`1;A@LK)x1m`TLwZ0a~(=Zf&lx&_|2gO55%p%EM^->_>I3dB^*b-wq!X zBj{vlPiLN@X*?Egv5}u0s|S}|Acmcru&;Sh|FWnb=&9E7z+2<7&`4>TawwhGtvKu? z?a5INzlZza;;wqpK@O#-{Hm4qH@%BXO5u1;<@bkms-yPyAScA%6Ycv$k7fVC<}ETx zkSKDV5KR4^&TC!)z^u7`JXyr^;%LOF_lse7snBGQ-|J^lqE#}L$o~4sd>Taff4lDH z3S5XN|Hjyz@@tnL2DrW-qS7X>4k2r)K%<1JcQ32o6+Xq=r0$+r0DqFTnnZr6OH*gEonp4e6r z+fm~BByvlcf$NC0M1s4@SfrQ7Na@2|@J%6xwc|gv(Upr!wx1e!7!1OG#bsFAb+#9j zw=Yzr3`H^#k+)@!k0}4pJ3Ioo*f!x|A_K>3ctQbs9(*wwpjaHp0KZn(Gl`_4kM?K+- z$sMT@>Xsh-kw?1A(o%#e_)3~r8J{w|b!95OJ)29Z)U@W7jyG@+u7rSjDxm3lA*OJ* zJSA>K9{T1To&7I1UscWv*Zi->9~hV-PoyizXGmLXwlXKCX5)}r5YMfu>hFd+jLA)` zTFO2qupAq0A=a|wA-k)$%`PvP-=|6sD)EpkMCIv^hTyh^Kd_1$!~|sv5>&PBc-?=o z@n31TX-OeueU-*K<)y^p zq&!;R8_jJo@wQmTigDY(>TqlMS>hI!VuN<6`c!#aQrfRx^1)K6Jt^?Q+3p}#eW#;) zX^>-d(_8`1)oS?NCl}o6n4Cj=*i{DohR9p6|JON}1mG(wf`S}>u*sMBO*%iN*xTyY zsfB3wKO0s2q6|uumf5V#DC(-8%`LneR(=9tivR4<*NWKS0%&>5AbW&CH&JkX zT%!&>y&@RhU})c`K)>7BddwQq-l3(c@wBd?CAFV-krVPmx>jzdS`W~UG*yt?a@jQ~ zJ?wbrJF)71`H;1@&;X~Lrx6`1E@T9_D_drCY_I>Y^)6hUkQ7%-o{r-ZUh61Toib>; zOjTV>CjJ2rr?P5eB`?jrB-x1ab1hAa-sR5*$`^!Yf*{=HWm=iw2|!MD1J4O}GA6p_ zF}C)Yhe-R|l9;X%5X2fPe~oTi$%woX>Vn~x#^J-b z;-{+@ZJuU&qNmguvB;kVOh2EL+tZNDGrTup+LDe*^VaAN}Z9Q47yTo&Lo-^yF;VWu$tnyrIo1wd^**1{Zu-C;2IwL%6mQ1{PF11^lMbL?7X-o-J5$$s;S_zVk${g)j8Jr(P z`yeTP3)i7MqgaX(QI>PY>~b1bih!ZVwSGp@Gu#*Zr^}gIdi+mgC z1Jm)h8SOi=#YuQQGH1v^SD6GTb(7rqzCW}?CVWsLHrkWhwTg#`XyvCkdmpM6$lSNn ze($l6+ZZgFr9}TPLo;QJOYz@c1FtN%v)8 zmcX7~!ydCKbY&Bwl~Me+bdk(MU=;@ll?7o#5Hw9D`E6O9GBtUr9zsE1h&%r$bLU6>p; z;B7Mn$*Hat2nmWi%qDeL$0r#)mJa;EeEnlT2`lEd)^j4~rzY35hndUAqNEQ$C=cwN z6SQ8?@#f_gxfb10HY>>i%m?Bz{Lo$$qJ*c&`8?4m7>Xl4U@uq>A#gXUCR>U1wG)*C z&o#?QXGm@1mykot%NOd1;P}_f;%D@|?RbZKkFUQ+D-2QM$TpbD!0FYdWzj(LF?<&} zxt1zw+qvuwkv~%S=Dxu51RJj4;%7CfX?Dof1v`5!>o9jyYsavNOc< z)Zgby*7;ll`5T-2zOAARgW+8BRo6D%sQm}K-QBC}Xse(yImS8I&Erp@yS6nF7o#G7 z>~T^TMz*vy9UphF12yEcLl#v@D0_L?^{%a?ZXqt=!L1_Yv54@Y`_d)pKnj z$tas_lY{~qJ!0;c!_%hWUt0le!rmU+q0ZD#Mu;MMK#-K1>zKioV$2?LcG$WF^#|BJ z9m;S7ig9-tH%l1#E`#ov3YTX#f*}hqsh9bJL0dR_bGiF9D<|C7rMs;iQyB_p1VxFu z3N~eMR>ExH&9omEFBi z&7ljK@&LUQa_LIHNueXzaeR9~p^KAdZ40XbQ1_nsSSU8E@3Pbc+4T6jl$=^7)$FQf z@H#yX9NWBH-a^vlwi%AyG0kSnXLZ3J*c@}%9=aiL)Z^}w7K||nMKZRfsA~r;bQIS% zi^d$(CJL5%No#dj$#ZZOYamp);ZXk>gvtqw|3?sN-B%2poAb71RVzTy*sd1sQ4jBh z6906Mc0PTLyu*-8&9c*_nqS1&y4hYtG9*laKX5UR=RU8Sj`MJAK9>n z23;Ncg;=msY|S;^>7)%&%}&^{FDe-XTqz#=Y{9T>1_2AM;bj8QQDTqH{6*y&-LMt> zG>V#RyOx*&k{}9=X-n(D*DTri$DYL+B7DaDg`B+{#8~O8Z9GpiQnOQNgU@CN-Xn8A z-1%g=r~1Q%>cDkmZi>swZ^gE~8di1vt`%WK3^K0>aGm{{nt7&mL3`RE=S6dyw^}-J z)z+5P+&9q2vwW}6*!^wkFGtkCs$zkmFU{@Ho z_gS`GWwkHO!r9kGRyF8AEr0Em42G*ZU(-KHnWx8#P4D zp@fX=K8)}0e%t$HyZEK5>wm)yJ`(>4F`o9I!QIIDwdQTIm3+pz+sVVsq+EXBadng}NVD|{Z9f}8Q(GpDtvuSJy>^=`N!w;C@03NLbY9z~o8 z9BDyVd`w7+(fn6fN^P!{k|vD42s>Oup2^_4MA(f*Xw{US=4YLaZu~0=LiqApl5ah7 z^$QUG4jotOc?lww_+jBYzTM~B$U5k%Z=1^ElQK6W=g<{D{xU79dlSfaC%YcI2rQHa zP^5rJjOYTsh^in4@3OU&V)Bz*L{vJb3PK#IWZ!w4U1GN3!@KrtUmEbdrfsL%p5~Jk z@V$5*@AtbsQPpI+at61pFLd?Pr?r;1HBn z9B?|YBydA4jM-=*AFX0HSx3aLs~+o?>X0m^C_Q3pk#yC;neWVgI-oOG25*}Lgd}FC%xFXi>X^Yk4iEdVFv;iNubh|(mb#wt!SOoU!8I>+!zI{< zF(~^W2UlMrH5A`ybYWA{Q~^GyzDXs0KLGNs6|#4#bRZIBf7L@5df#{dN922sGxbFF zlyyJuvE-stmAQG2GNVVm2S-bP2|i~gl-AonP7sog-L=hnn?0I<>ek>L{q8F%s|sAT z9rlQt_&s|N&WS1IeZSfWvzX;E!VmwK26I;bQLm`5E4k7{X|Ujv;d$9EvYD!9-&gV2po*P)s=RgK`A9o-6B`buC_WWgx%I-bjj=;OkOsJ90-=19R9iYm8-pDEDV^eAN}+gJ zKxp6krZG;h8`eVIllAA93BsvIB|qCVvLju$k%Quoi^FtXg65OcyjGnRyEd9%{K#MS z=UVa-QhcwiG#U*4hWyM5F@ujyFNK#fUN%XI8njn0!lNODj5n;F<>fr~Zmd1=#5nPK z=1u29x00`n&>9K$q|vKuJ%o&2cOiGz435#+jLfcl`=pJXlV)v1AB)?6MQJjpX3Kc1 zo*|6PXiD84a~f1$Vvt@UDVXU| z9>|9`tooH}U=UxnoGR3F4{iSgjDV~xDsEjqcZMU4zW&`5!RbJYSO@J(sjh;^jx|ci zqxpShIW=N#zXRlgM4q73!OxLXRXX*hB#~QNiR`6CniXGezWDvN|7zUStF?|=VAa;c zoUPmWg58)LTZvYh<`;MK^7+gFQrmg=_IY_g!q}61RWRq`g%A-PcPTbG1K=2PZEC<$ zi|tzIbaTn~qTd z8)=_=eeO7^=Gd%p)u!b@0{fN3|9LkNcyRBP2>cY`_xQZwV zCH8r9`c&Z6l97^qrc=rCnNJdAS~h2pacScZgO<-I5Q0ZnQyJgdD=ld9#bD<2N~Gcp za`yge%=V`M6(x|**d0N+F+CdkbLNo{P9k0!|CcbTu={_7V=BMG4T87Xc^doFZtPZ$ zW|2Ld5wTrS-q)wf&TAq;77Ph{&JZN(+}@K%Am$vYwpkjOZL3FZm%OumK%3`p9O(~e z7%JK-U&p)c`CG1)FXr}!e z*2LR$oY+!cgQD_5)h6%5TZ2ca_j+m%8iC0xtLXy8DZJ4Bg2igph-0vXR=E~mh6|$s|S0~-s{)_okWXLZ%@y;pp6bXAvd{iCp zZ2uFbH*AtOH(N=)gQ6bd+jg~GwpU#BK;DyJ-nd)wOGybpeZ9F$=C_EL4GT5#=fd9f0Zz3QwrMtLaz*Pt#-q{`gyGUg5ynsq^b}qq0(+8<3Y}6Q zcw*7VaiJcSV=?*<$|f&_9z8b7A){vk>V>;L^MIdUD7r`m)Y|4+`3-E)L1N(Fw3nI+ zfSM;+?F?<&Z_)K{_sawxjCGo6|BV^pHL@5^NBf%{PQ)Rx8IIU5J6;-caKNVJkrNoB zk11$Qqy)my+quwRjZlpCc)~ubDR|pD>X3^_%gfhj%qarCA&w6@bQ-{tE0M>iKZZ&= zeXLKG*2%6boK6}xM)tUaH2UcBV8th?lRa2*hY3l*$>WFPI*{t1Nj(gmmY33nsL;|q?bBq=FPXl!;1^qwdJ<014&f^HhNpU{JsrDU0s?v z{|7GAJaVo`yeP?aDVC;*zPDEVxUaS=&tR- z1qUmR7;*w@RD_4QC^uH3Gy#573I%_{8q8XZ2{9m9Kw-h{@YL0jrHDU%W)`V7fo>~kh_`>U7va;@@+@^9u{A% z{xxXhPe!x<1ihr)N>H{A`l;$1cui=X_(1MUc0 zRdY(q`)Xd|ES+MIAu^d5tv^MYDmBHaAu|3s5Hmzwx$$Djb~}3X?7irx&Nj!L`GdCM zA1TBZlTUcBR7W>oo)2PqxMRV%xe-2&&uP}y>n{fISaw@5tO<9NL$Q}N^L}Z^7%zkx zF%vmwhTATKijsg1wmwl*h4Y%fQHbcvaGo=iPEHNI(R?|M2JIo9Q{cGqxr~qBsm?Px z!}fBSdiS9X5W_66=-&Lg=?vxcs7TzPG5&GXiYw-AC4@a5NK3XV3C^{HgFW`svx@#v zk*-Q@kld0M$D+JOsQJ%1;}3A3@KPa7bp{@Kh5q%qs~@J)FUPT@2W&<=^X6&}-2KKu zcuZ03EC)W9%i7tOrW|I9_mIzHFV>nNwKXD+ITR)$5bQrzN|1DRQN~hv-+PjycfJK;h6ko)$X)!j!O)zHqE#*6F6t=u}@CoJe$)R3P{d%DU= zd=HgmRIwPs0iV&z*Y6O}O}laTxe}sDP8J#*9mVlNPAs>FA5N}CVmM|R zmgO599TG@_vdV40mz?#@-jKY;eqZ$1BTQ73WUYrHdOwwUH^EeWM#SU>!l|k2u@d_h zXd?}XH7EG~@>wSJnTfu88qSh#uW|2)N6JO9;xozD+sH>iE)! zc9fxDG*2@^I!is?q*>_-gk9N&RWO&j!44npJSN5ULAv5eCN5`Qe(yQqwEqAPAiW9w zH+DcY)<5QlzR=a=i)O2@saMczJZAmIc+oNVi~@nX*$|ns_1vM|B>ctNIM@m~>u-BmhK{<(-Tl1nz)nr*RDgpjhd(wo!h zic^zXEgISa4W|PaPRH*r=~5yS7|Q+N?==T{b_QTy=2yhu{{vPh%GU)FI>Yl0-=l?? z?px%WD$LO;=Hxrdv2WXI*%|ktJ$)I3H^Mg>bn%L6dKL5fK)$i^w4!p1PgzNmmdf1I zR1y>svTv1>TIl)q+NM-3Gy96=Sv{oMlY;*px`xn)`hts=foQVUBXM``?=?(Wt&EEe zFc0v};k_{he+G4!rR|&PA8Z{P6t?M~Jy0!v*kFcc2B=Ch3vohGkAIh&)h zG=6N24mL(IPbj%JU#8PaSW8G<(7Hs`@5^b4!Z(DK%Xk+sBm{^W6K# zp!43^vr1%dT)g_!*6S;lc-HFGPA$Z@w>uDX9D+j#`kTM@xU{AB^igE|`jyesq;>7d0o!Euy@kRKJ1lX*9R_wN zdP^HZ{MrcfTZ2u@qSH9;LrVKv_^W(xRSjQfg;y1CKQ#{UK0X*hr{vSqG&zP$(l7ULJC)N!uq-47*&zM)H_cx|7J`RJ4{V8rq*7X$nN6wo& z7hroB#bf_)7zzR|U-uvn(VlP~(W?0p@3}~up1SlW(ti>te4K*ojr$yHF1ZorDKvfM zfkb%raP6-cl}@-j{q5WiZqCGJFxw;mu=U>m!yAZ@KH3aB$}2p~(4{&@Lk%mEN!blDAwJ#ECKk-*!)ru5Q*q{EYAUgZbtTkP412}!;N19&TL8i-gj}X z*byT|;u%LJl#0ZZK{HXawM{Zud4&2->1(RZKTadb(CKfu(~*TPD5diIi}N> zqbB-VbrG*QtW&S@SZxx*&4k#WrqBaavBB`)<+2O3h?QOS@EcD&kdW7dp~ zRa4!@OrPoo2RTESjlNj@$oDIcZrrc^zJ5D*zBj)u-ryLbA|MqvF0$7(!gX1J#C`LS!SdvI*>zk~ zjPB$WtU{IMPlmMSEJ8$QG;_}@M!5caevD$lW7_5-MAW7ajTW5eI4to zE?1tqZBv!0`iEc>uRNR(2R$qtzEO=vKUA+R;O@8o05M=y6;Y~5(IVSFUmqyMIj77o z#}N@3FIDBz>U_$N`SCX4RfQ^*vr<()w~@r_zp7TGC^M{Dp1wl)aAT$GP(|x<2hzKx z{(JI{X6)rc%$V5^X|y7TCTmG2_KbRr_RDHpujB-;uo1Qx|P73smt{gRvB%2wcl~j86sL0VwuY! zSP7-tsK6^EJpufly1p>4f5hC{j^$7QC`5fvv5r{cOj0ksbUrMFN;!u5;b4^qXpZP4 z7h}(fbyOaG?OooIW&Yr)hRk>H9T^uBXYx{FKb-;Etx(9s*TnyyknaCPxyf@o%5NsX z`6}WbJR;} zmQFf+_MNS>!H-p3s%SEjebMbuSxdKZP3024Si`=T{~N{T8c3Okg!A!9ql+-3KsuY< zi=Aum5UOOn+sr-`J?#ye%QmyVnQ-@Vdkn<2aG}fMZuN2eC3@eQxO^+}mV!FWe#7Fd zXi}JHKdtO;wY}-Nqe2%DvvO5lfAj=F{JL1)(04Aj>tB#*dd#JbEd||?w*Sij)4j6% za&Ed#y~7`}_r8vH3@AvrCqeYPfbT*A;)mGyCbve!8b6Wp>}Nf~a{ZxvD{#d@d#vgm zYkn`5TkT&|k>0Xr6uM$Qy_T@Ma;N`U6Pa|c$NE#M*TPytf9_nFmo>|$_*VZbx}m#Y ziE<_ZQ2DWhdRJQ_A%U#$LEWnB{ab&4@E*G~3gkOg6#s{){L6*=LWZD~Dmg7j7gjND z;=Sf}DdYDKY;$6nODp2L03Q2~c1_}Cj|_Z*@~rsdv4s+DkI>jyGPM5`6W*IXBB$<& z7>lg2S!aaG1lo32jHwqt$ddz}P9gR`M=?tn^4Wh6VvNU0^e=`fG_52ndoMSi7P$XR z$(hxAD}Pt((R6C~)JOR7T2>3^5d zJb24xKsg{Rg8q#EB6;$6p8(T8;*z*X?G8-@S6r=UsHkgC z*c>J~#9iQ0Im;8d%WuM+FO@JB>FGcyxQGSgv3%}cxH@A8OaJ6=98k-n_-vB0XGcPF zeWEn)3;SeG4mchuw5q0@safXn?ew*A0v77ig%@&T242;x&R1-qz%J8pXa3WF^S21z za(Yl)wGp3=*^1Y`0cfm!+4^P*Kr!e&wAw`+0eVhQ!sGywu zwPj!!xa7Z&raA$}){^Vo4e-loO=$!7EO3dg3qhWlbCu~5+G=0z8Rw#qLP{z>Ajw=t zKh@zzs8mmWou8)(Vjt9s-ti*R1{iw0KWybWhvy?d^ft|X<36q1p<24Qy)aj_4%brN zY2UbCdNS9oa#{U;%tHRPwARl7o>tpWIJVhfd+Nma%qq@TSo~t)DaSlKYwI%9qa6u6 z0$5zLhucDc`w)ov8lrF^c*MI*CK3{9=pICQv&Q)pz2H8{&1dVz$3?1UE3fA7AiZbL{pjF|ZPU~+mF~*~I^{a)dq~l;Ffdnk-cLl0o z<7`Q?$2NHaiw)2L|Ijk$;RxE7r{G6C?r(DQBdD@?a{*W|7hvu}EFp_|12U&MWj-#; z(*q6y{(n?QwSqP3l#{8JSX~yl&XRP3&f4XwmXOrZb(DN2jrY-fl=9FVo7w0q)*yXc z5^mTt7M@>79^T0ZftaI9E$VURQObN-b;pSj4JzTV`L_zyah3#g|H9sdv_vPn704O; z9|P4he>oWV9qT{Pnfs|r4iUD}@l8$H|K?0gJ^hCwx^EmDpIvxmFM`c;Nq9bwU+J}9 zalGiV3W8VAHiZLYM1jk<-MPdA_3RVy7-fuzkpQX5RDx4*ul~D37@n+<|xBSOJsgp)R^8F_$$RUCE zzc?GmbRxgirFLX|)#%M^yk@b&`CClLZT8aK^N=d&h}#9$?}D^|Qo*XDaXF}Ip|5cM->y-3|2jmfNavrA*u5~%Jbah z9ljqq;{-mv#tXrd1Z_2qzVpv&3aZN+iy=qmr6vodr|ZJ2SU(SG(&sb>MKiv$qAY{< z{ya9Ea2L{^=JVXMLKe9lQe0y0dxH3zVxk#iY50xzH`RRjt&9mC?qmbP*t9gzVUmQX zW!LRKG_2KwpZ{m8}r-QmvCR3zd<`dt-yGgi+L-<+*(FQK-JidgBoP5qN0+0 zsWc;g=%7nd6@BuwK6hW_ybR=Khw+(<5ar~BF9)OYbw1Wq@>AsF+`D-~fbBl|U&8w= za8N7ItKgXTQZ8TO`m6a@Gl+cy@%o$i@B@OwYRH1PXixk2?Si5|~-aXz05>`1@EYKN8N(d<6P=C}?j zudaXMH+ooP?v#aF%l-bw_z7$`uUod8ONTS{{d#D_&Bq*=f#fgb9L zab20(#_&D~5v~51SkQy%?gO&X!f_pVyBl6;vI1k%SR|_C--wkbAa%4+cD4=`%^`Hj z<$3vjc^a^@;8*0)w0hSurTHog!s3^@j z2;4(DpU1%{u_|>;z`AOnZpg_S_*gl;leHEoLG6XrL3me1_Fu;*6fe9(?2i_$W9p2|5f7LA@KtSLRohFjzD+ZE+jF1h0M^4Zh=j~k6O$5FUi$r_Tv zgr@GTYUU2hs{_Xs&pOBIndW=YFSrP5*K&8`iSl{xH_(eEE7tLWH`ie+?DKAtp9weP zxA+K3cUBR7$@VMWg9#fC&>mP{z>ebuY0MmtWXuwnibrnJU`cK-p3W zi~3cm(46B7zKyQ-zQ)fHaOl7~)$McvS|?L+;N|rWIH;U8NojY8v3uG&vclEVW25Bp zR~V66N0^Dnxh53vM9H_xn{*Hq<^@kJ3obB7%jV!!zUK4&(JOgjkqQ3KCpuPpoy&7bQUZ z{`8bc)M`IOIA&PQSu`9P1xAX|z23cW&YR|RCe@@tKcJouV&conXf-flkHaL1_}TKD zS>7ARjFm(JVzR&eQq?wR@z9&q*pl{n$s>3M;`|A0bJcVET5wFg9(L=p+A)_lJzt_<|{y>pZ3pc1gSgE$J8&B0i(Dm)uwa z*v`&i5ogw`PCUn->oNFc>G}o>{B_!^WBy?p;|9?6k-gyOeVb)NE}z3!Fg}X5mwvlU zD)1E;5RT=M5zC~E1zDd(-fXag_rP?h9belvw& z7uIY|DF+{)=el7I#uw>XY4hAj`mHV0Duo8cgl@WS?8x)pl(&ufQoZsc=R) z!pVL{9E=hn$D-p}BU!UjiJlZn6iGuW80N*r%uT=?$(&KmR<6(|J^9L>224C3$v&1U z=8#E3L9wGMJe=~8sy(`DPDwGj*FGHSX+d4Ybq@7rNAjlyna#b3ts3JCXCL0Ua3Ck5>;!o)b-iU+xH_|!sb*Fn+mqJsBVmmBxs`}9sHk#=Z z_C9X*^^2a~>^Om2A#{^7&T_F<4Yj$Pl4P?D>`*67=>ZPb1smbh^CaS~78aybi7q!V zVS>ojP)v&^U&flm)F6SrZ@Pu394><_LSE*zWd(1)0&G0jd0l|oTUgL=6<#etAfB(1 zV!G3J0Lvv2so~@vabS!mamrw1B^M_pSH7mX*g#)!BCWfH_yus;Ev-j}-iu$LJt_?D zeWuuUq*)(ec$JM(`Ih#)jIO?J+#e7XBO6t$`YNt#SSg%jJ)&iU2Ss=7vaf)3 zKo%`=gl(q4Is+qj^FsyQPEr3`n9)~_;@l{6z8Cy91!%&GwlV25)7?^_UFEMLYGKMO zX3p}foCy~*T9(Tuh@z*UWwZVA-LTi*-}U2LUP}TsxNct?;=Sa<_9)&ZI(kmIaS5;k zPhV=b2m8v^BX*C$I;NFOldyz!HDEm6M6lW(yQdzXucj38rRa1nGMy=nkEeI1hFH;{ zGi2i<3(wQnEe>sG<>aQ|?8Ko^qDFNxtSDSLYay7c(0K)W{OL_5>|1W}MBYx`vj4Mb zkL7i%=Ig3>$Gnr>Z?pX-xo`cEqpx!_Asw>g7zlWM5lN&Yvx<;pFk@Mc-Qb~X_O4#w zx2(*r%qeQ|<*|3`^Rd3RQ*4bK^L=kr!%dVz7-}_T54e-1&!af&#?f#+InB$cZN#5> zUgUz5mEmlvM20yRg)Bou1toEVPO!}5K5vGjprhN|MYpg^uA6p#NybtuOgE3H2E82B znNBM$OVe2z`(zTSMmb+{yHPU3I3Dnd0@(Y-#Kmy(Xl&wvr-oQrfF zR>qy0k*BxcKp&ZTv`9hM#RiL7*rY&t4k6iB$)W|xvF>Wb7ZX9;Dr+ZLBU%G!d3)c7 zp(co|iauj&DG$ctO?-{VB`Z1}@HM|3T-1B04e*bxRjH+UVGWVB}l(L zt+l7!yPj)$i7RiVHZmM}ltDu#wZR2dp|o88+_UNxe(@E%KmoSc7j!Knq;h>Ku9kba zmh~AYtS%dmkfiS>seIDDu@~)S8fozHR9^`9Iv0P<@?;)u6XHklT9h+~s=a$x#|o{a zq@^}D|uZ?(xtQc7FVusf2XZnp-~KtY4-YBH$8GYzfI9TuXNVLWf<(j%6pP4a~42po6Lij?i0Z5-)gX%s*3_LVY z__E3zT{38z&#k z(BU?H$9RMgrM{($eI{|}L#S-tP|7HDF3#?{3GZPG)zn}-ju*ShqlFI2dTx16dr(ClU%#~cs45K(I=kD6Xs)e7 z@>`wjTRUZIiU^gG8)O|&gzSrD=oA65K=seGTW;u=OKjM*vM~LN8HIi}S{3OxxRIX=) z`|O<%mFKM!+6#;tpu>@36zM8bT5Ga>R-&ki9gCcd*V?LTKrC^Khm;X7$&#m7j&(+u zq@(I~X+6naahKMN3DA9o~Wwlq`r8(UNB47gR0T~3H7!S@A{|tXO1Dc23^btr8&ac_z2u5 z(0D0|MgH}J!5i+bPAK>2iIVd3KF7xgb+4WPUoL4`%t@RbIgRjryNvR|&j9PobW;DGsW@ol@>LA@rAn>4$%?V@+O?5l zVK&A4>*{gRJk#UaSqq12e@He>oa*Lz_CLi;>y=iSc|EKRy}X&IKYszu zz_U#Myw1@1nY(bxjm2$IH0Fzl6kg60JVsnSpWLJ`t&uLDNbW}5P2F|O$+IGr_NJ?_ zS=L*c=GL@uU`j5CxWQ)BV4w5l*1*dpMNiO6N!9eZ9k)lT2-C0DgD88I>v~Bf@OUu4*HluHWmV*RS6T zibRCW8M92`pXincSMqU3Y;nqPY;Mi>Bu!&p=6%*G_1oIS#l@l$m%H%j@6wExvOCJ3?vWTO862 zJ|br0Y3co7Uz#ub8Q1&f?$J2ksrHBBPc-?))rd8>Ad;SOupb{_Vy8W z7MOGCpwuJ1OK&q*E-&1wJaC%|E~^J7fx#>~dFFdyzh z_0$#T^%OJ}-U;41HtCImeFeFO^>s1O-<|f$n`BknBR65JiyF6Q2)UVToH z&2;H8ayJ(r--d_j+(d*QM-jGf+1H-uU>1J+u)fOp_gE=HQKL`;KZjQau3{LApOU;+ z9sRbk#<%XrB&P5EW!csM(lEwTa3Nz$ViqNH*qr*@w<8 z_cA^_Gc25UeO&^S{J3yyw^gg;i;X2M7qkrg=C!eqR$tMoWR&0GFHe3=gNUZ8sF~54 zO?-)V+{!E_qyf(`r}(!&uiN_b)6a=_F3k>#xCY=CkLk5mj&Rh0Su~A{fJSb}!^&y{ z8o2e0yD@8TYh5;y;2%>dVpS(tZToNa*$&{x5ifc(lcL_t(M#uCBqdcvZ@qzT z3<$c4gM96-Fmo4|F6&qT9a!5Z1J7fnq9xIYI%Q$VOBI?fKP5misw@tYX!+c~n0n<* z#HINo^u~N=G{T(*<2}Oq*faGH^yF^%$}G;V!c-~G1`~%%)?BN3JE6d%aV-u|^s6-Y zZ#8a|4dy!b{P)f%Y+C~Dj96hK;S{kS))X_Y9H@R!j=^5*i6OKzn z{dp)7wADA_P`m518w5)xU8B|VI(j=5tz?$tmg-n=`&$#G$*D-uyf_{Lx zyJ zffo+nXvqf=o19JBt`9KWByxp&dC>!x{nx=q|6Z)TpIaBtvalDe#XJ+Zu&6&EyzrZJ z<#J!c-K)8B5^-v`o~zzyXV8xW9x zW!A==b7TpJi)V#ftqj@jE;aRK-7g4muTb=s1p%*%ERf`KxFpw7_b$@|Ui;ov)%@Qd z6F>h+J0xywdJe4OzK0fv!2IR#$gqOb7-fH|h%aqx%ONuB^l zD!Ubrl6BRZ55{ydXx<|qpqWc4%wUs{{A#l&ja!((D4rb=n1&OPFZ|jF|J&U=#}q?l zbQwWwp2Yc3)r06v@l9t)C}&m?u**vYpa|VW z+s`7FM@D$YhZBRCNJP19D&0Sh8B``5qficK_!`=?XK~%W_$6Ppq$LB#S?60sg4A~3 z_O#H-C`=S5Lz)wC_A2e4NySS{bzc(?fN1xp+j(x+^M-$0hG3d_f}y#&{O8YYzZ%#h zL=~(e{fW-1lmiMm54(-@@`EpnRaJ!*LyQJG=zn1FYmJ%_(1$E9|9o=q6H1IR+2r`Q z()#fV;Xp+1Xk+BBtoQpnltS(7ow9bdSp^P6bd1EJKWqup4v=XPfX9@VB|vYvrsbmP zZ66^r6EnXJb;$TWJ0KBV5&n!L<;916j+b9Q$7^@oI)t)7 zRkHW=zv4LT`rZ!T6x@ziqdunCOw-As2lsN!jzq4HsnVU<2zq42Z^FYxrZjt3NyO!o zCw|RkGA9y|&I~xeK6zo;q|p z=XYPkeVmtM+j~YrbKKY=^A5G<&fZZve$s`Rv>2rt@bk2ESw;2|7 z^G1G!3u;vm9-=@xm`If5u1Y7I{p{X7v#N&pUr`UL<5MZd#m8(YEbj1cL#tAtOO~PI zw1)Uro{C@r67fP4Yss^f$3oWr`Db~7@JNMa_gY@voW&nFIm`CC` z)9$RJ(8|{$^`O(SLIoHXm-QQ{cn(R%bczZJPQ*)m;KaM4A@uN>R~?gk@%fAV-om2G z6}y49LAi^<7PP$q(ML#x1hI-doS8f?_}v>6mW{g4{xzmxca;P_I9zdKQ7U3geB+Ss z&K&J42v8&UYu2hp6Nq^5N6C>~O;125uM}Q;qxR?HR(#VCvl2qnIjuj0bgKIx3cv2E z)-Q8EAcZpiv0^a@+`@CXEOQcA^nG7*r+~!8C;NEQM?*q5;AaWE6XyF_SMmK6H5L;( ztolJNr7&j~A~VZGwjIV4yT>NRIo7AtWJL8N24#~w4!QPqH;Zu!j(`@rw|OveXjQW9 zH0q}6eQsMQtTN6c<4`+!NR*YFqt_u!2AH#X$Om*Vhe@d;!Lv->Ofl!OkMgTe>unY1 zgEmdhIs&<0b%ac~OY=1c+nJ=ySB)}m4FF*_fs$KxL{d_G@k`DgzPV07Oa5g5V>D$o zb}4{eswt);gnDHDyWbMklJ0AjpZI14W)ZWpnq_Kg!E6s=_RSH56 z8$SY1=`qS$!^oEX!K0UAD?eV{FHU9yY{)_`y5KIa>)!Q6W{RyaGou<{ME-}ti|`K? z?6Pb+Hm)}`OSasBrr_+epr0~204O$95{or3^UlImwfym2xN9(f8Jh+Sx$4GR> z?p&tNuR_In^wf#7_+2hs(JPKdDp?13W=_xZano-Fy!~`;&S8~+;kQ|3bAj?iSM7-^ z&O+~Tl-qFJ&CQhLj}?Sbj)fw3*{9c>`pR^yBc+i+EfsLsWPO2u1Z^<{UDGqz<3}Mc zh7VOG?p6PJE5HA~v7Wg@Z7PIn;_SN)zcW=%tuW!Lb1E^UK%smd^Qn7Q{Bw6RUHy08 z5{a+r?;5LXzj-98?4M82_#-yzN=(E)DrfxpG;h|a8-*?x;bRe`J%!fgfaiLdXru|0 z%Pt*h3)Gu@{#jK^Vk4{o z0v}=W);AUocbxvt5CT3&@T$6Yc9DFIRl()_tZ>z%T&APN4U=F!;3opG$c5`H6?jyap0n8a%lZfE`!h>m!h zlC&Y@)Pa$m{xj}L`CO~qF*cHpiI$b~-T08F;^ARS2MgPUCDXy2(&dS;LTczsLVrOf z+wCsOvFk5eCn+Wkw-a!4`M%4NQ(z@OHXfc+BGb!XQdtHR2EhF_a+AlUY~sB?QS|T0 zJG(tWsYn0j%)DF&rJLKQ=M9-us$y$-rL_c~NTAHsSvBVCS`F(BE3F}L6cQZ%%HQQd z4JxPe^1}3m%M5js*73!v*Ei97;t57}l{)Q~RhCgNuETvC%6gw^e8I_cduy8=uP@q~ z^r2f}Z(CXKgXEf%W>LCZ!KR@0!SY=1E6Cn>^z$$T`Dc9?CcNv{uw1(>4-@rFg&o5j zV?-oP7onhUG;(~#{rKBJ{#VNLDEDIngGfB)Sq-Uf6`!lsWE5gyJ`D->etqcZYy{6- z%A^uz{0qj)V4da|LW7r=rB_5hJnEwsYfn;1TL{Yyo^2%7i?$NrJ|x(b_P{ureTov9 zR1?LyqB20(>GDK4f7Hh6O^j(R{%T4?6z4>Y`9|N42YP9{d{5#@D-++kUEv97{}-Yy z5x3!ReWM^g_4vV&m|4X)%Hewo5hpp^mmaojPM%}i>WjwVpfNtf8(+@tPFW|gyToLW z-TX;wNWh?jNk#t~S@c(#t^|#uE%h35MUBnH@UZbcih7fto&2x8;rSDMf_^tI>~D>; zbYp@XGDZnsJVgRuC7Iq{<{&Ttel3Cq&3uleKDH;*e@Y{2a6k_bon=eytGI(hSh$)# zNP*tgHqeQ#7#;aMef12}v6P!(-!2O;A<3LtJca|$_0H|HYS`DC1e`h`w!i9U?@1*M z*#wjWEYH=3__o|-txJ>G$atjb5%Xd4UA}+F$vujkhxnmJDwZ3Viu0aA=~C#weBIiT z=EdJKzTb{(O3f_8 zZr18hb~08J^;qodZLZa!X7+x8_|$axiXMRzM*W6+E;f@3hbkM%n7{2S-0WuR(nO@W zf2!AOJJ85a_;Htqdo&M*@{aC?U6 zBUeH_G)<&u$l-h&B2xrAQlQD@!qLZK;V%MF=eqEJME9-VD30EMmL8NL{ZE;Z4* z*M+>WT$IkKknF-z4$fbGa$Pf;w(gxq5@?qq*XDed-B-!t3;QLHOsfm~jw`Utf|uz1 zMQeVEE`=cI7n^OmXjcySv#W$x$}Ce6pry-W&9H#=&emfCR7WmP7G91;Bi^;);L6Pw zGUz+c;biTP4XQ*t;&hSL{f&NFE@xGE0)>V=we%v`X?(8jOlvTdOuq|j&Fc7l@3H#RN_>9aUrXu%ngA0qY?Mwnt4 z+c&L!l8SMAbGB1TJzDtH@lP?l(7Q*tQ*I#%zv{P=R~wPoQOc zx*OHHmIpPx>t_Mo)zKVQsue3e{pIu3r~Ak!?*`R92e!DW)od0H^ebtRlRFveW&l0x z)}DfMs$83bbZmUcW5`l(gnpV zm3~SFgZL59eNDXq+MNR#HGAymMmbON`}iK`fuM*ZzoG$nqK^h7E1MsiejTBf*9K`5 zS9v5xDULprRxm*<+z;HbBC;kIRJqx6W%6PD%A~HZu|h%D2w7ULH{bByrp0q_mKMv= z%u`N=Grec0`XRT3WTZ+-CXY-yFAYPCl0LKZP4y0qAF5{*Z1Nx_tkI8?D`ym%YoHJ; znSJ&|g5||gky=yuc5q|}wOeakY2M(}(%PkbhySde;a zE+)BqU88^ns>e%ve7yTZIsi`nAH=7Sd>hb?jHap<$Abf#qR{Cr+sz@Z2~KIUis#jj0o|tv9QDb$GAT4m1?9dQ+=*P z@442Vi9AY3xBX7KxVZ2a>s`l!o7#^&j5ZW>+RiJ)FE4z$-<&Y99vTBV84J&kAPtF+ zRt5+YKmR|Z#5zM3TazeuQ$wSOl$K$HKdNOLxJCV3-ephXN?1v*hg}m?G7IndQ*?>Q z#$Ipr2%Wuij+-B`3KZWS(b9~}cP=YRzh0kBo^Q#JP?}s)2BS#R)o1oqB@JX_kG2-5 z<7&ou>yrEWu#;(vH<)TXdUHLp+-rE{8;tFx^ysz#W~vdij8j>_WgQZ(qB0=l$bwKn zo%WIti|Xb?bu8^rNGq6jzURc|GdUe470)*ZR?{*Cn*xsQE~)iUq`k{SUclZ4Umhlz zbWD#X_-HPh>=~Sb!`<E{SwBQ3kE=+1Cj zI!7RfMJZ(;oO=NhZbIi4qr2Rs46DW8|7AxD5WK~xg0JO+n|i1}E8Iq&!S(bWU5G+D z4zG-RomlKQF{J($ye@r1E5eZLD}#5e;yf9%NWpVfi>FSwT62{I)ct>rAPs;b@^fS5 zzsG_&Gmc$RCW(&kc@lRx3CllP_8qN5k4Ta*2yr z(mjQr*Wm?UXui7aO8-o-esN=M&M-1XNWps{XZDd$sk5m9?5GQ~S6Z z_>7l0l0%|2;YJtUmV~EE8w;{GYIxM#>F7XdU{uQVvU_#nv`~&`fTihx4Jyx;npGi+ z@{LvB0LQHB&A9}KXy0pi?wPo{-KsU#$$%=~VslK=8M?m1czdLl^nU)aCSP)L{pH-w z;hGR>d>w=13E;PcVkD$(C0Flxxg^<~g{~7)72NdOYh2_Y6as0vO41c)=vqQD29v26 z$k)ua)pu{_h*$8v+v<bJ%6mH|`?WM9ytQ7elwAVe{62 zTQltaVL73j{eCbO5E)CqXAI+_O+l0ND4I6t;|a<{daZ2w?~?175~?z-^y779Zlc)Y z>77#2sp(op{sC}xw7AG`YOQ>7m%_a@fOWHT_{(>KH!KfvmT*2lXm2zzfWOBr)+5)1 zWEGZVRP-2CPOF&fdxUZ=ASwu(l&44R6KumygHBHy*rngFuciDQNIbUo@D8Ad=l7g9 z^XdZBcBbm${+pgERsg{dR!aU4x+nMEs$BQK z3#xrlof)GN6Ui14^n33vLW;Z^yNoVy{2E!I6Fa(W$fPgTqMePM41Q>=#(Vt-)@yxz zpDSVo@fSO{9hX96Tj4onWeS`z+%w$cx?5p959wIHglXuSJ}YGie1PM)k0@{2_ttgV zf!gaK@MN@w?kA)a$)8k*XO6^W{3W*fok!Z#RUQdy>r4ZEUSBxwBSW|+n7EE|a|_$A zY#;~Vn)#Dk&heOLGEG(q=;~Jq`7J4-8CbGq69A23MW!q8iuZ zuPD`b={C$ctcUk|K9^5Rad)S4v-W@a+W~VaR0NiyitjUyjD+OvLY3i*aI1qY(xhgy zTkRcJD{dkFynOt^d~O2kJj;q)vThdi4}S#LwrUNEKa%awl7fL3R~9wa>ly=ojJq{m zV=4#5yOfx4YUd+QQGCdIxFz7G{s@Fee7Rh2YxaDOgdLQN@yDsF8WX98l)=mAR%qsr znhh)&?63!z8g<>j-BCo*KQqRIFB%@Ky549Cr4S|Ev{VKF>*#vJ9i$#V0jWv6*N=-x zQMZt#leO==uWsiSB_K=)Feg*l=T0bJ5!GgtZJQ>Q(=n{*W03h~bhp`GEZxw&`~wB` z6%xn6_(nS5vMV(iLi*Rb;j2VxCUDoI{aY#P%oqF(xlm4B#1dWQPE1^`PE=HKxZmgUns`yF=WuDU$7 zw)8Qf6u)F-j;F=HxC|OqJDkzhu7YJ*SUt#-40QW^_Rx{K^)__y>?|PUmZ{{#awHzE z_|7)-#cSf#(T6u}p$*$n6{}H>@dpl(5+;{`u4o1?jkq0#wW{xSwg`ys0J)KS z=dsui9`41aiJx|vYIT+c=Wy8}qbw)Vi$x}RLbgiUPVmxmLs$xuF3ECXqf?a%5Fd*<8dML}PCzydj{%moxLmhZIYrVxc? z5$fTDC(w4D2S|OS=XxS0@3bCp;E;$wA4e4kWo6)8KTQ2$qo66jfbWVKnr>Fy=6rgTSay0PF;dt(JU*{4wU*X?!JMAE9V3H~W zB0|=kt`){H_?jT#by4zP9v{)&xkdlWcoj&Tsb-kW6jZ6ahOh{+xx2w1Ism8V5dHyp ztuimN3YV%lb7G$}y{o?2e)U%h{v|2^CB(#H>&g7)ll zfZnNaxK8`Xs0Eypc5jS@Un@`lBy*_h9`NM=H-uQtKm7bFKeNpZr9#`B*h|-`D!n@? za16vB?>OGZJ5AI4;|>N;seD8YO`?FwINl5iV({Os>wg zJh(3xC^;P@R{Lpqie~GF*?lrPBnZSTPgI`-MWk_H@gZf@i~_X&WVC)ieg&9x!?a!$P>|(c zuHOoyzLwuG{QPO}qgS%|152OE=IMJyVkLFoJ`!ZrBv3YY)#kR?k;iebcW3w$7@Kg) zT9MR)EBmJ(J$9);szaH3V)?L%hU$JbgG}o?@Afc62A!r)4OJ`B&9{aDIa-d=4j&Lg zB@=$m#L}A&B;a9~mP_I;DebCRa?uaAN>)tY4{F6gWXF&H%4~@5{+$Um#ni<~o-0>t zaLiF-!f+Z^{>0!(rL?JE$xYrXNMdAsiDM}hZ!qIld`d;PH&rh0$??zXj+{gC7wRUP zg@^{EgP-aqvD?YVgHmjnZEcdjIV`V(`PAGfzL*_WSW~4RNiB2xeFR6&I`b2?8NYeh zwD%cnjw__0z9hz^d~9yGa>LEiHzZS@z~*?Lu-*Lt@ZJ7*mgV~?KvAKu9eoxF0-y=U)!d-pqMzy4$78F{*@tE#)Ie^tHJ zyBq?oo^H+$dI0_TT4CTA!QS|_CAwwH&ifsSs)S_NEtNs}oJnLtHkPIE8kjT4HA+Y@ z0jJxT*@tR~HATqy5_SniT{7^h`Km3}N_N(F@S_Apkr~_qQ0b%nlM1p=;x4JOX8DX7 zc95gIka)F4XahQYV3v=Wx_i04k^q-Z;@JA1Vw5%N&y%%sX;%;_Kv7?d>3B0)Br3|S z)0SOL(VtgoLqfKNGMxIH~T_cyv zeanV8ZG<0s=XOyWvYVuSSm_vd<+#)-8Bq-;ngbcgoQqM!#GcFYFaf&4x<-8X3Brjg zpmJ$2sZV-ZdWmk&iBD&E@U5Mk8qztzhMcio zeNGOsUx@Wj&j{u(({*+*LrSLRQ=m+}pnd9MchTx`R!7W51)s>%XTB@Z{N#aNp5H?!*_cyk2 z^+~%^ZKm^zk?guy9#usr9~$^g0^gcz9OBYB_pt|T#VO`88;-0MAlB9#UFA8&{`e{= zR9>N9*^yX__OQ&?xtt8BqUP0Y;;Q~*ilDM8uPwl2)tLCo&^;{;Uq|!Kx*rQU#Zyi5 zbM4DUAW153QxQp1Z+#zQQxXE`A)7t4*+CS8$TKuWu;%JkmE;FH_Q5^10?^JQ)~Wus z|8=_qTiAH`)2_5wz|cgi4Zz1<#IumK+?`5Z1XY%A8QNku9&#RJz9(m;_CDB}9v#LU zr`WEDFg~u)iC3I1dN@_+`>?U?oDVt-n_G_#AY%iu!ofL;zfl~4&Cl2+m& z1!IJcInY$_TemIolq@78hjTi5zp*UG&zo56&{EK$!*woKB-JiF%Y@B8DZFIf?l@ew z2-K{1T${B#(b5@IsAkCS*{?@y082RnFf_DSpQ?K-AM8AC7p|YS#0 zbFe`%>c`HY8w-__M;}2Q9DY2gBiQ72A+FZCFm`snKeS1`OTiVi9`j6 z_(PRyh>RRa&+=7Dq}nzD)(jU^+r3P()H7vY!6-zB8W2>&WAk3(sU{07+Yp8yrGvHU zwD~yEv7jUr>Atz=aHBuseG=P9TwqRd&d1+oKlG`rb{}r_(B5OmE;yehZ@<5My`53M zra13=Spfg3sxP@sT3thhhte>;?2H4Dhj%bK`3_*|-ZB$STG<&*kRyMUbl3+2!|{RSbhYeCU`h+AS8 z8#pan7goM4T+rkyaxIC0RtGd&Ye*`LARpx|{Sp!r?CgIhJY=Tf+JB7Qfb2A$R+RRL zu3f>-I5(GfB~BLmx=klAo7#b*tj+*r0O+2x^rt$^RDuGCI<|-#KmXbm!3(u(tXize z=>f4%W2=}_A?uS74@?;0ex~6#q-Cd*W&cg zcJDlIET^y$tP$#2UTUV7^p>3!sMU-)vN`+d zNBgb&ID^slE+T3jOGk&(1RBZWqDsr|N1>H$(82DhG+u}G-RXOA`&Ti9eEaN1u02{E zjry(<+Og~OT`{ro)FPcp_%HJFqY^e}w_`4_@ z|NJKGHCalPIFBIXy3`6or5*6K1Sn;q!Yl0)M;fLBA0P0{bJ@rW6?kf;%+uI*>RPU4 zkhrTE{IR8^^lF!cSC~X#=Ia+x*B;KNW>3Nni}DXPcEiid>4l?UjIi+JF9O#T_EteB z-FLQ^Mo(GE>DBjFSOyfJcI2TetfDh8ENCdu!ec;rQXr$#O;L*y&> z*W7edDI8i;R8cq0)l824h3*W-@VgD`=j+WG5;t*)7=M$*C*3v>)b&~1!v^!w^9Ef) z7pN?xqVK6ogu^JPuLVosw*Af4hQ9t+Z(pz+a7pSs9%U}c5@}C3ISq^kmO~~|OCv^k zpk+EW$8G$874eMV{< z^YSW$O#z=Ld+r)U9d!0Gk>8sIeWmHZbt_(#EvXBpOKZvtCqU@ zIQWqBP~SH47Si+^csqxVMrlNv7mxKv`DgFP9gDtO1>RXINh)WLFTJ*^Nz_R`8_3%oCszvpUc?>HH*u;e%iuO9 z&mmwvgzv`FE|;8&vPo@$lAJYGdrh>Fb!zvmGk={cAeVGx)IUs)Dk1lRvQR=vtmi+>@+;iR`hPtYdQgmWqCEwc#APQV7HXRyi z#4#x~0)SJdYhj(eed{!%OT94cYy1A%ItA$?=iXw6ce253=D7zRE|m7UiAMg>-Dn5R zkrU3)vo8I@w7pp{b?-0`el1Ag9qbqhRum6H$X|5a-}Ym50{V)PliBybaVWW&|C2-c zFNcqVi{+pG-lzX}hp#VQ#(9Yu{m1!Jn7}Yw{p7c~(wW0Lxl~!N!MDTZGyZQ-nIr99 zn`^)LfSG%LQU>l#`sc6CS~K`8=^>~XIxd=cv9;i@dY^wm4%h-ABI!DZ>2}rpSYF#O zoEc)>(vgod>M?~GK<{t!om{v_4Xci!@A9SSeak^sKIOLj(t$vWY!{>qLu z>!eaH_!2>Vk>Ncu(x(@b_lusjA}*eg)oRvr*FvrWlQNA`e45*6FRIR65HZDwi3&+y0!^8*8tj&;DXrPwu8fxQJ4KCj zjw6atRCloc4kAB8FOt2$>5@m5c@YL0izUGc%50FGV8WsE>>`kj6scZO!dcxE&5s$c z^7{yc5D@1m^Bzsoe8+?%yxS01Z0^wZWk?H1w>Qfz&B3;#=X;(cC_Ccq zD>>kL|H4v>88uOKQ;&n-Keu$y?m(2eg}-1QXEDN+H-Ft3E!al_xl7B}XsbHbY`aFc z{8G~%Ku|}$6F(q&_QvB93$e(bR(<47b}1uKfj(Ei(5kvY{Ob{uJG$ zfgLYWJ!==gp$vptw4vJD`WjU0LlaLS-5GFjq^$a*CZq$P=f^i~GwUUwj(oCK8gL!T zy3{SSQ_-77=+S}y%xkFc9FKbi1MVVQc)8_Uu>t<|ckz{x=o~P8?qdfQ;wci*m)q-P z3n+SmAHLv))6Kzf$hHv1#OoubHh%*#f-jGiA%L5D=7kov$91xx1fyudD2_^Go+r7Y zz1*g3CiwR2fmn}?hp>mUP3hXHJRd+UcSI<reC(z zpeakfk^xglCU3=uJE6e`bqPX^-bfxwM=9V=Ag&+5@@@Xji^XO}*5}sti_naZ)`e@- ze0+6TKBN^9bAG0aJmZ%41H(mdW!6@QK)duLhbofI)xI0Cyo|0-Y zaP9s%4oj$4v$E0yg?Ws;3ku0qxcHXkvU*>X_a?)2j$wymw9m)oM>J}CY?kc-VI-Ra zKA~_n?=H+2^0p4vlg8O=OJthOyFbOJ9_pVkg_$$SX*6JkQ?Qcuv29f!s#pT3zZD-6 z9}A+3)XD&-$`~W7J`2tA?E|2bfgVxdDRiZ4+cGCf^e9Eeph{N#E^$3^u_8MTx8gC7K=bR{)FkbN1simer2_lb|5!DH}7I#e!sTK zsxQTOdxi+7X|61Eg&n+G^q~WhKq!p&GENVYbVDybyjJ zM_F8!nCesIaRj=TUWU9uTCY<*n!wGUB@ZEgKI~a{9QY;W^|GB2iY2yce1Jks+e|vr z%^zL)b4m>Sr~>PyirvqsY*Z^>675NsqHCrSrn#Av9bkC}eNsSN94L_ad!&HI#9d0# zZO^;AVc5n{k}~PcGsD@PI>zH-p^3QIrgiIG)fb}@wfHaO1yEU75$^4FWj9UVKxRD8 z-g;23peF+bWYBZZsjs-NJ{m+oe$2|vYsJpBdx4P#I#$&QXfWB1kqnk?oZ)FW6kdo* zC1iNkzTPo>oE3^E>J0>$ylP#ND-ZnmSfyFah1^o>Bn$hQwp&PfMgcutD>91BVn72a z2{WO=LFhPonm(7{cV_`VvY1NDzl4b#nUFkxs6{)a8M=_Xy5Y$CE70L#N2eapjU*^r zTO#}qGdi#yTVJnLda-6YNM*sQ(dB_Y^h65@elzGXXzfGu&xST&j))zA3T!elY}O$8 zhQ{Yx4zVxxt%A_3(40Q{4`A#=cuV%SQj`+V&|DQtk1@v;=9Nk zZ3EiP7J@mc4o&}dKt-9f49fi(fT9Zv(0@@rVj#FXE=i7o8JEJEfr*al{iD?+KtP3aY^tr^|pS$8z`< z!kh0=A~;zg!fy|d`c!D_-YXVH{S4NCbXcw&o--qsOh6Y0f|@ow z%NGL}d08e1La4As*)~EH*?udwzZ2kulUC|Z24)gUG_RDH+hCGQB+e?wt#KU(V3FS_Xq+=;&ohaQ_QDriAb$F)IQ3K zT_Ngdxu^+%%I$rMTHITXlyAc|l!bBxJ$LLo#%02f5pfn&*1f9Sf^{B&}bIdJ2ebX;6~c z_E5MEMfsR+*-HtZk%(hF11V;V&wH4(l_(PIs9#ztYCb$|WE1Pdu#1{W>KxB1h7AdSpB2p{;EVlm&K5i(9@~nlMdC{3V#eX5+ z*S3l}Of>74g!pF%sUupfpX3jHKdU@i2$dZeQPd}ucoPET z0jjadHyUa;oPyZGR!Awde#Gyi^BKAYQ;3z3T<3+pNGG@R-iHJPO=;fqv5mGq`6!`1 z1eaxHUZKHvH7{>_&*Z%tn@vGgj&>CL^_FFZu&`$FTW~7DCmCri?cF zPELE;>_mu{4^Fa;i$l)RI?gr;nR@lsK8@OCg7g*4$E^n_qLEW|!YLuNG<@J7t1UNb_X3cLB5abn9&F~`Ba8=N zeUQNryF@qtB*d5aazriBJKPjn^ZP<8&Xl0A?K6-fp=a-Iji>G`EImqI`oVw$-y{Ja z6PtFd`PH|l1Q4H%`@CSbcFdu)z#>16=*cHAmakMmJNX`$16{&5g)x1;b{%qIT$8L` zRI+Tp`8>T37LyEY&jB9JW~vA?K98Ss4ISnj5hRK5T*&2!Iw5vEiN3Tyj$njBV1zo6 zf!VX`%2}^FI2Qd90?PMu!ViT~{G^^C2q$r?xNwFa=wG|lr#;F`j;ULkuV?|AJqs(J zV~wcwi85?gzKEHB6X+hZVpag<*AzN~gPdkUhFYu~@~ZR%O`l${d27hsR-7I`U)?Dj zY|(sfV|zD!ENWGIC4sjN6&BZa_mps;j^+Tf>3&+m8;!Y4G3tsveykn4_iYGe)@p5q z;0v<4YI&6OmER#37yh}aJK5>5Z9em#x?lTTQ}hzIKt_4fVMf-F7a)FMPdr`}r@Yz_ zT?0un7f{#?D5M7R<5efp0~9lyMyv-!U&zi23!k>hOC*cEaTqVJi)n`^9k9J9u%hpS zR~#I=1>xF?i`JOE-O9ymC3|yQ$7gf(lPx*q_?@>sfbyNBcv;-l4)TCkUCNDlP`$Xi zwDTvH?pTQ^QkjMB)JC5!Nb$+Dmx=>j8O9QFu_VQe$|%(pJ7ZW*T~Tk-J@O~ zC2p~Luk*umA7>oi{@u^f#0x7st*YnZgQ-Mq3B0JOT$(4*B?X0hi&scQBWOM%9J8Sv z&Z~_Ids&`O4Is#?PPNZp=#M!eq$wF5!eVKuH0&C&$q-$i>H%kP$olR3p0K7QHqPCl z`H-W~B&Y6DY^!=@WGCqqB*bv--g74jo%ea=LMi2aMngzzo zby`H}*5SjNkawRMt$7ojmdWUJETPh;3pr*fCUxFygFcV7-@DtRc#P2Qg6m+GVB&SY z{uj~`={1_K0{j2&AiS#583(Yqo?5cM$4TFCbgxY;+ZBGi0I>Q&&8QB}0=~S1d&e7I z9%?#~g2g!Wo@f-zA*CmJttWSzRXug5U&%$F+Q8{)tYFv)It{;kB2}$uB@z*3ann-j zzn0B(^&}{WxRAqUd+Rc)Ln+w6bq#fUr|B112D1ZE*AxRqnTc^pmm1alDS@A`O8BYG z+o+pCgih-)yXJ-3rv7vJ`$k;CFnd4wNnH8OMZDkO!yzqH(@#wNQ1(11H^qII-MIQU z17G}?RieSGE|&JMnh>x4^?WiT)v*1iZR5bvv}!cC3S%RQi-Mk8KwYo#U3Eo&55yI$ zYGiz0j_RN9l%wIw>OS5A(1UJ=QymY^&n|zzbMR*VlJzj`TKE)7h?iY`i)(gcvFP9z zK{}~gUyEiSYCn;QTka3GaYaX|ZKy7czfUxG}P9YS^BAN}MwNhnZRv`E}pe}z(n zS1TCr&kiRh!R#1q^eR(!cKET72ugIcx4B+Y#VS>ncE>60KXsdI>pnNCmhPDL>w#5D zH4r;xE-~WeX%fZxyI|!$=@o>_j1(>r#Zqi<>C)Q(<29t~g|!Y1Zbaf(>q$uYX|K!$ z?$OXsYvJ!Q;Qw&@VfLEDwMEj4Hu3)KCgi9Vn0?(3AbU^q&JhZTDzZK0C+dPZ(Vc{G zfWJ#HrS)=_w8*`wig#+#Pxrfoo0M6H8cBiE`}O|JdCeSXAOx9QExwB#Z7pQNl=&8S z`|Z4`6&>oV8U^sYOrCSsXQ~3X5Fk7cQ}kI2j<%CDA!5 zWW8?G4VHed!_e_!nj|FgM8~vUFlS5BhCWjDgtki)52}yUK8d(x&szA@W!IrNY2{wr zpx~NKIUCFgMu(QW4$n4}cd)L2H*{NG!;Tp|p;uhKMQ+LA;QjpXdo6HLwlNbXFgudcOonZPRe;Da`ht;&t zD{@2wR(RBTPl*SQVLA_XMUA}0RE`egoU<_~3d@0aiDJL4>HpL4(07zG{^mV(9Fz2l ztCL~PzHH5`AQ{-ipF@f00gJt4L}hOp8&Oni5wy0#Cj&e6oa=edP$4iKm5Zy2->~q7 zr@&4X94(LfqUBoV>oLvj!7!hMuJaac$)&;7ahkutj>oIa$WS^jlbYd>6+-Izv0f=~ z=-n}&Bu!)-=2CVd=5b#o2^SGP3lkWp)F>F#LerNWmQyeV@qrA+<9k_|ma&AJDDV*- z<7?PmH4x!O^RqC!u*C&`S)_HGaSZ?w>U^VDm80rvx-DpdI0w4Ic!hB;Cx@B3M44#E zb=Y1QH-VKk6d%n6S07;pKFF5 z>ePil5#UC|k5E$MkoY??82YOTtwg4R9$O0dN#hlNM8&+!9E-6>;Hu1-b4Gpn3DP-h z+><^9?=%M;VsK3K6S%+KM1(iHqua(_(Xb-c)evPN5o5CIHEVxi_cGtOJfkr@uNpf2yaXp$AqIvZ>G zAh6V8$BL7{_>Ff-V5KfRc|_62T{ED*IUb=NX{Hj|RS=b)0ZjFV?VA+vDOd zmKy7T7SY+CVwZwoE;Pbex%fxhBS5QB>ZkElS={U`;<3FL=Kz9MT5yGK7b4$X9@vsS zE{#LuDAe1h*S`8^`p%r$gGQ<|H{-LjmofLC6u@zQJ{ejYqPwA zD<@0x2&2OmFeFWk~Mo_E8B@AeZ32zA3dHJ~1$UP&b75 z{TNO4#?6@9SkWT?RokXvBB`BVeuoiWYwED@LG~^XQz7gZ^RP>Wudam$i#g}9YQnMi zVMUaUf|x>7sw_pKUHah933^z0^E4NI8}?f@bgOiY+O+s1H-82j0hjH0!&1JgjV;Dn zr#e_dP_WU;pmBoljd}l;*obHa%oU)nKHq!n5oj4_J|^=1zOMK z>bGbLcS7Z>^%pa%ud-?$N>=5AvIzmo$)Mqj~4^UQNOynYAn7Av*d zN+BGuaZ(b1-wZe{YMz>|b1qzPQ`w*Eruo zmtV@#o_Qwvxoe5MOBo+XsPc~xUpv_tvDq}u!5@IKC(f70W0IAEk7n#L5 zDsB1v%nI(il^er2^c;X8kBmT+w3~aI1=n(4n_PPMX) zQ&h`!*j1mUs979ThIIFt@d1?k65u~15w?HEz`)^Ze zX6c531zh!WJA)qF;~ydx(~~|^7J%wHN7H*hF`{G}KHcR`z;d@qOGJI$_Dv$gJaU<{ zh$TFn`W%Xl+WCo09(r*&EoDoHeRovcXI(%GJB|PIFtGC}k`X@l%*ZBi2-+G`^5^?bV7V?PZjo z*DSFppt`NmDcriov>Q?Bk)$fx`G66P`gGWVRO?BCqDP^Yt*Ul-Mb#BvE^fNFc_c;y zvo0yTG6iF~-DQNlW2<(F7D#Hzn%+Pk!|s-sw%eCY-OyDGM4ImtvpB1H`Fb<1&JH=b zWiz7mnS^8IeBQ;CPVZNoiJL)~m4qKh99+?luW0~kG|u~FrSo8+cFme7Z#^JG@cFls zAw6MoFrvdMI6Ltpep$z>AMS*yb$3n!&6J#`+WR7uP1G)poSj)8VJCR!iH`yIunVr3a z<7EW@SPBp4-Bxr)*Npnp-li=#3Hg)%R0@Ob`OZMFs&&jn0)*cCJ;yZMm~HAC9O1I? zPVndA>UudHet|uO=+|&6}b^Nn$zINqHz_h5Mocy68q;v{1T0_oq!TWMHa) z=T!g+wKd*NxPAl6__56MGC+c<39=Q7`{JCv@_!G9=#2}br?(1>bIB1*>Si2%0-L(6 z*fr|-!~UoyY`-rZ(|WOo3`XITQdU{90^rMtn+(O1>E=)ax{Q~NyWu_c(hX@Wg*U`g zPH~gd2uyMKykE12GsVwQhM~Wgu-_u=zsTLPf%OjhPHTPGayzW48Xt-1p+do=wF9-O zhOX^#8*gm?6>Z0;$$&F9_7H@Im{@vD4B+^}Gka~c^}(D8plZ=DR7e-gx0=-koiq72 zEgV@gONlR8dd5Fp)0+&6DtKA4?p}}+>wL?dG`{{(^S!Te)HAcqG~r-qsd@>?1;s5o zHTnR?59;n>51L68hUxXxYznYh2-pUV|Dkh)vAsH|W-unN&=|Mgc?k^sH?w}0jaeibXk=T^^~qA9RB1;3To z|D85)5f2)u^Hrz?nyWsETIu$gP0)Zzii^0{U*shumDw;b3vuQJm2F^~Wvd$pFo!1I zB%D6uOkvK?>ut+F+2!y`30OXXXkzXXX;`c?4Xuz~61eR#qf~mfU`!wyd z*QA!S6J=juhUz|NG6(BEdoh8pRaI|{)w~P5A=tNSZTt%G{mr?~`fM>rN%Idm`OG1| z)m49c*ZA?4xVLxM6uaj_ax7pvtv2)9g$lX<+E20h>^mY#--4Mq{sf!n%m^6^-8TyW z7tvT7ec@E`=e^vYR zdPf{a@Xh3vB#`%*0J~Pp1{O!RGRr$w91d@W)_w-ULKq|1EQx-Wf+&g=mqnn~ilT!) z-bU85-F@#&ld4k}zv-zMkgV9ka8Bt_w!Q1I=qzwXEvdy|A%E@uvw-myMY4TrmkqCr1K?gcO=4bK7&K9a!%Hiyf^Cu z56WsDl8+oq*7pX_oSzOA$SIKb=1K;~qXK@;718@$yk&$k#-Gvfdk9_`>D`4g*v{GT z$0@2Gwns$0Ex101&b)P1J05??4Hr67UUuJ9m_GKXzql*8I8(r`U$5cTmmi1KC=8n` z?asv}S+^QY3Ol$|n)d{brK6jvTQ^9`SW5U(!jV z_8>3IOStM}X1J#sFJXMNgXmIn<9Jl)ZP)?syY8*S4>4PPMDE3>FgHPeVNWf_0vf3V z#PbqDV|w-+CrejV)y*k7e@*~w2=wR``$5A@l;6N}xlZ?3JlUlApSi%#VlgjNgyWH0 zZc$mO7)UK2M7%{k8t5oMq7&HgIy0Jl?%I%fmomrdD%DB)>h{4jT4L8OmkjOERBrXB zC#$K`bbzyb(Uy&h?fQ2yY_Hs``LN#4@J3FkE1~6j4hcSQW%$uoJ-_XQYf-TT{qD_3 zqIgd^7wxH}gdg$(qfb8v8Gd#cHG3*(=g>g;J8N5}9}x*FJ&dUZ_X z6;31Ad42T7zO9)@t@6YzD+?+8`^yIZ0yR1jsdz<=RJZ=uoQw z9+#hp2!tPU{*E9d3>#Pyi{3I)Is#$a?_*iFDke=>|I!tj3J`%zt!?;Uer9C=n~Edv z?;Ih)J~CjUK2dz*slh&-p=>&(BoG#ukC@|u$o4yn*amI2*f=Ywp~x6tu31evUIe!w z=$7N1q_*9batGfSMr*#RQfk|&uOsV3;=x4)H|hO_dhZZ}t%JeYoLHjuVbV!%^qUCXQ z9b%CcVDOyCpg(qhO4@a+F75upWF;pt7o6;5lrrH%?(K{4dJFNIZ>FU!7C|1#tkm#^3Y z3+^{=lm^-&!U7XxN6N;Cs^{s)&!V_nJQXcFM_>4&k23W2Q11aWF!rAo30kHJVEmBK zi|5ERo-EAIEDOn2DV|5Lt6$9C4zympq;#25KCdf$nl+?3BHS>WhA+nh&Mr9ccWR%A|f~+{dw~+$wSJVM&GwH zATG+l7NhgiN_lC;0l-l2(|DPK0R2>PFXFpT-w`Qf6csbF5*BtQ^Bh6w*wRg*1uw0U z0L$&0`qL4=!L644PhbF4wJlIm6?|NoSM_-Zn+8`o^m}pMn&)5s!GHvBSafcqT%y;$ zna7|-j-qx?Sh0gM6_<|jL*3ca0JoT!tREkDo-Hb2a5)hTd?X9A2bbUR_4&g`nZl${9B}o$Ui(;B91TyTtYA0N~9ziSTH&*vu<=(Vt3hSj! z?lM{$hZGjS&xF>+D3}GEjI-GBG8Dq}h;WUnIZt6F7n$t;2td}9)|uxB>(15Ju4vYe zOHBtlwgaC;)-NL4w&Ox14MKb7WnB&BVPcoR<{2ni^FFqMPDZM zr`@)rH4`2iv1(b^toG1DzPrq=0`<%!j8M`@E0B=(sr>R;NuHG#bApL_eS59&fBMkkKyH`!wu@ zblb48kXCyx&zN9L&mxZTq#!k~!T$NSpo9LE7=x}P z3|(0WQnvE4YA^o)qA(=8y-Kegm2E2`oY#U>iANx64=!8ro zn&ze3AtoF_8spH_lztU-*8*mn*^{wb_i2MtY54URsr>$Nj%^1`2dMKE7ad&fWvI}` z*8PJkxCvAlYZ0nhb||86G#Y{~ncrqRz0Ps|-p##(O*ym-JKm^x=b(UoB>@2A&hq8r zTG7nB-3N2>WOrq7?UcR_ki9XVWRo(3h+Uv~{KDcB7M(_Bv+xU@Mo0W#rDD(!`Y))D zk;UZF+K7K)JfayikEFv)+Gmt2QRsMxCjZ1VTIJD%;Ssq2lI3CXU0nUML@kYt!Q~(Z z=x;qfF;jEhZ@}G_Eh5DsZ4R;${h{&S;tC$<2+lfcc`X!18&)oMKYjEB7{Qf(L~7Pa zHofjZk>{^_cLmr+Raa58r0bFPyrjvUl6#Bmhc=6cWzh;gyDchgvCdLoO~u^J=KN4C z@ZOt+;R~fW>6XSrah4XageGGq*9lY_*L6hvdLXOrcLeHPxERk_pS{%K%k;LbC8#91^fntn zamZuh7_zeQ+D;mBHx_M`yDM|(dpGZiEFgL}q<=vYt3CxO?1Tf7OAZME9oj!@|FZKn z8JOZIPVx+LJZkQ9e!9h-c}x>IQX6q^#|zc8n2wHw2rDC?`1G_`NlPdLu0*7>4KB7`?iXkS_+tk%MlKh3^O>0 zP57v5{g~P6xaK0>*Vy+?@$a{%mg67(@jU@JxN{0vXpM1ESK0Ss+m za@$T*6J2jAz6ohf`kt2ns{O=Qr@g3un;-`|`40DLuSc>+Q8D-T;qF+T>Bhc`BuQos zm8#nTRQ%|CUxpLEgWEE+IJ9b>spS#v;E~H?ZK%Zug zqbAkp%0#$uiU5x3Nz9}tNW=f5KVNF*-w_7na-}G*egNkf;Q|Xx%IG=a+;fDT75en7 z_vMayv!OY9V`dVq=<}XNKCC2V;gDCHJUl^%J$HGnGDEq=umx&(!#sg!(H%0TT)p`0R+y9c4K50%{XZp>P z570j+Up#;MYxm(N&;0^dCy!Tfj>pMv->z#)bIcW8yC<|}j`8*gezwiL#Xq#+~12Fa>Umo1#sottbXv`env6s;lNM_76tV+WJV2>tm<68xpr& zWv0h`NICWb4x*>EbRhxT*-h6*IA*^8svIjO$=cQ0@|3W(h_-+FeW`emGp$~y7;8*# zx#l|4!r2A~*Tj-6Y1uWqta5!lGID+HTWHKny?1d1sQ|^Qo5AodQ?=~bR{hSD^B_@$ z@yCt$V&0bdOcHFKsOJdJAL}M}>sS@Z`?6eZPlWZPB27_}zaqb99Z z1OeFv~@1t6jKEb zi8NSJy}^eJB)&8dl*^=$Hjy!cEZBoZr# z)YM_PlywV$g$TBdfg~X_!NJ*o=$9)yBTjp9KAU;EnjUSvteDBR4ffPt?KuhW(NISZ z#WD4eBlt3qTwQ&)is>zCIjuZi|;FQINL;V#ntd$<+!2x2|$2N(Uo-_|cyT2{z}&c-w%@e6LXM%GbF;odZu%o(T*V%nWcRP7@Di8kWDeB%Bb%FHzv9bq6ngkbO_Wud)d_r+jkXfkc@I#nZ=LOhQ{h zI&wCx!nj;oZ^t*j!@p)s+RXFSk~}ZDiGx4Atti2L)BrI6EnYJStRKm`{r;}c5p!<0 zCgnIoP-?&wt6Eku?-JqKhp>?bA>dPlkk9M*UyT0UEh~eFPc53f>04(_ z+lk+x1x*rj*rhkyC@~+~9lS3CJ@XV_Y`=9c;KS;JwELcQav34VL|=JynV}HK`DiiU zCb4`J_*SFawEgr{B0iRnqt!EQ>?#OltM)e6=0j;|I1HENOQ2%$j2&l4R>bQ#hFcHC1qlHIA{>9(ub>(gS-Tm!|nSl8f0zqh37e&!!7~$|H+J#oqh89 z`q%cVB&{W#qh;8Cjtt$H=1NnCdPOwOruQ^*od(aad|BErm=y}y)kfvf_l&HuVK(w( zhZPwbUwq@w1EjQbK$aeX+I*AU~Nq0)NHQmOTi1r zjf>HxW%6qKnzNXbH5P2g1xvA!D}}N#{W|QdLz0+5z<@};f&1aWY}3dfPPH;06L&15 zXmyKjy8wBe*{xLj`W&2jE4SONb*(q#Ke0!Ad14<8ut*Sx(F$fQfB zIQ0;-bI2tu&1%(E^r|vTsQ7y~y9b*@d&2WtgvdCR@qB+r@>#+pYY%ZOAG`WzsDxGW zAk@(lOjFm65OBXgZ=-P(){BgMD`gvhIN4(5WTda}T+PndJCHRoVQD{Q&4i6`mY#*cm*z#^;xhauYMIB<>^_yJNLtP!m=4BX8C04L~NeD1L z|6Tmt%f8NlF9yRnBHXbnrf{%oq<=!Q4b8k#c%G}-`rkIVsGVW(Vf<=7sgjwq<1T0u zoR4;O?26w*xcH{UufI43cU1;ZLRb=*lmNEU?VjFP8zhOanAh(xZW}3e-Dvya&qMOJ z&W#33llY^~Tis7RmaupBKmRU2S6;(-_uscFzl)Hja_Bk|1CsgV)C5E{j& z3xyK*=p#-D!P_5tTnw}0M;jS+dTgA}=e}rA2H|U!6H>oxQ$8SWS9B76RN;g1qv?Z5 zSyRi0I0r9q(0L?kyPvLd%uXnuk@o1Zp_9YRqgs!Kn8rF67>9JlBXd?rb011!4q-x~ z7b1>-IVXXXd8sy5&wPSA!I*iW+FF4c3f+oz(8}yq@8) zOT#fKLA70}_=^5pSu0lvyE}p4?gV#tcL?t8?(VR0ci1>=+=9D18@asaoI3UU>fWmF-hXCI)zr-N zTD?|J_p^GQ<{OK^)4jECJZrXx6bko@GS89&qa1fRyS)BD`nT7*1)+S?R(@65eB?|_ zc~jKYZn!f87nyo*^IBmj80eYBf-`T;n6ryJ?*{f?c$^L{E8mwUP#VtSPT~pLN|;j> zs33`J+R>dz`(-gdXMjJ6>gw}7edNH#{QJ$MFY9fc)ObDLwM$IIvB0~P?HDfxIi2p0 zuEd)js<{=~!(YhKX>0c*NFWZU(4$%$`m_ZTOIq{Z%BS^aW8|(L%xNOTr#ALKOLG6}cJ$QxWH#fkG#4aimqJL= zg=U55GyY=&O`657QAC#0D5>&2kE}|z2)Vd<>bWD$3K?e$nC@%Sa%63Tn|T7wwL8JP zjOf|k-G|+s3R{0J8>$E zHp1Bt%bZ|e@;)bjm>f0<`$OySeUa(o!-wzAGaOVG-{v`O;Osv8xr?;^4dpKHsM7ol zc9WM7cM~*(S=E#$3_zJ%DeW4FZPHTr)J-JQ z)B7IaTWKchS|rkDTzv82^h!8q)aYy6DbAxH_Y-XNSy;D~Fackcv!!1lnS-h>MwTlK zZg36%<5fpph+`!KD!qAerr6mW?sqh#%0guw#pZl;)=gHweWlu0j)7l{5as+(u0K`m zs{~^D$P1-b7m*}uYO*L6`WT?5f$VD(M%+w=G_vW;M{!`ws!C-asp<`%|>+lJKw0xc^9bAuRvfHG<3N21oW;|I{4Lcn_vB}LOv=Wey~zq3#hw; zS@?CPt8@uHc2yvWr%%dbiZM7@VgRX)-EypQklj)!0!7Q_G!@ z&s%qen~x!7NQ29^O{0nE?tNMp!p)gt=x(wm`CiTBy=D5g0x1umhNmtMSzTGHk`Crj z-;(51Dq`ebQ3-k;KK_OirJmm%gNKHpklUM-w#5ELQ(WXOvZkd>i43Gk0E#j&i<- zg-;b3i9VE5J!@t$Ie_zq_v8E^$anRqyVE;NNT$o0{ndZsSSq#oHaeO0{WZ03T|oRy z{C3~zy-O1XEc?;1q3~3?Ih*ca4Bf2tmT&B;MlFDH{*-J5-kPeZ2iN{0qmzWiZ#jqH zV5AJ)qTmPDSMoV-?j+9PIf0&|Z9&>NuOW;3o=1f{H@$K`Ujt$mTH2E>UMJjhgyqB zz$tyQ`-eu?R(|57Bgtb< z;yO6~w%BojU>XS9cU&zznOnzUPZuj`9T)jUv1=Jim=syo7da2U%Zi`b`8&-F7?DF?YYP#wQq=Aa^z5+EUD6&J!|8D>SW@TG;>$a zXG5L5Yd`<%gxOs;`?V=p=l(1h=O&6&Zrk=})GbZsJfUOwy)v)3&>Th8JkjzigKlr< zi_a6<<*Q4Ub}2Gac<>AbWhNe@m-JF|Y!g2;=PpuB&tdK;nA{#(N;Efc%`LAD)&dQi zi@|^~V9bTlA_M+ehDw^W<-2lvu$o6&IyzoGOvy!q-ZP%9?PD%QT(xE4;715$UQdx? zK5iP0vbr3=+D%>qZFDcXQJlz#)Lkma-ppOgx#-i~U^jcjTea@bpK5EdQF=8=L*wf1 zZ9TWmfAIE5TP3NjZU|tY6$u0fy& zrLF?D1!5XDv?%QV8FeAPd^_OQc71mCEluyi`1c4O*y1b@V!n#atwVR zUe8J%AAF;HZgufb`Q{y)L!9pgifnzumEPMKw+R@rdvv-gucW+M)@D!#?VPFqnCBgQ zxcAl^|33NOy^9yh7lBp+wCMi>CdkS0KQO`nupuxpvT*$0Vs?WmnvMnR=);>gRJWm~ zn2_3^W{#ZF$=lP;PsuV`=0dCqU{tNx2s{25f>$37g~GGkEEltnAP)VV{=VEU&JYPH zq34}6m{pLL^>)2qWg3YlB;oa^q>N?~mhhLr zEXe=TOietk@>>3B0^M*%)dPX_7iph*B1(XtLgp+w?GPtKL~_5e&R&t@c!vKZfhf^| zy`6fq;?WmEM$Fxa>gsD*SuHdZIz)0kGJnx$CT@nsDhut3aWNv;^Q+*y{?D&i;R4MUd>dLQvg8LXxX%3*T=h#1C&JlsW+nD>GW6gT zLqkD8yF3jP{yO->`KQfIn67eLz^JW8Ri7fChTY_zDF0~j9b#FDq|`Dc-(6vPN4zRM z(y}1~7DI7)=b;iG)2wtkB-`8 z%`=0#)8yd8lah}btHs70aqS7u6|sM=W_x;*eW8+^cVgNUUxSa~TlH-r`?W@st=80V zhZ_s%+k^glz-+`kror9QxmhKOUR1o20b~TL+3wDqDo)@np6w z|4((0wLo7||6$YNJaoP%Vpa(4r+OT+30ZGNnW~A3XpvO%)GXFwKf!I+-M#$UUZB{w z16%knEf08hnrE@6LGErn%dWH`oc(2l6uY0G47UW=B0XHIAnIE)QW{qMM`sCq z&ed0gY}FP9ewx$6w1hG|hx*cDPBQMD>eikHf0`pX4*(56=Qu-DJ#5&biRe}pjP0Rf zJ$0N}(EW0)*EiMk*qHR-CZ@br-Bwq#CRg&@4IqzbYEE>=?9X0(9r|r_KL^>HSqS4m ze*e;3KPA=l_C*U5k4PM2j`auW3?~{tp&gPvmrQ`8+JF_h2`wVO3|6e7F*$D_?S5}i zb}KMtP-9BkD;m1Y7(49m@JojK?F|5^5=Qjn(Oi?()7K}^kc8xe>h!?a=F#QgjEIC| zcj+c765SPI6HL=o+rG$JtWQ1F&Ei!1P1q>5GHy#z%fl}{il+W=f|m1EqxK(C#A@Y? z=Bmo`vBo2Dy@2`=TX|8vfb@j|k+*GvOFc1{q)%72q1(<({|D>B#rnTn7gm=42d)+6 zG1(nP^z{dt^V#H~>P_UpZ_@5&CVn95c9aNtp)x{P>+oFPm>mEaprAAeGUA!vQa8sD z7Ya?!Zr)Hc8G0-rD+mF?{HwEKK&`)nzFu~(w{6Q!NdO(j^b74c#Wa$bK;y~tc6&QE zbj4t+$&Oswh4f2fhLfr8REF=BYm*cm8L#%C{Q!v zIcf$Kje)K$yMwmwl9GloP9v{jJI_9tVQhO#?aY#uvcgIulBsSyZ^ubBMV7*y+dF@U zS-^Zr;Ol}+P4yiL)^O*84A{lNN!)aL2Aah3P@MzIQ|?Mvbl+K?CnJPJL)h-13|X#B zWRTFi8q+uqPd`6XY;k$jUrXdmq{zV>byYcSx3|UuYyf?oky-ZsGEFjW5|c+{?1h&# zQkVF!p%=8(CDY*lN&o+oYv=!p--Mm@gR%8L z7C}0i^4WO`0S3mur2;1#+%}k&opxM)eExi=q_S?EvS|Vh70|24_#NSYG?%vXP3~2g zM~y>adr+wc0ZYXHzTVxzGzepX@|SoiD`tefbwU)@SWpB}=9TkHlAvMqzaR5981=KM zjsWZT?-)HSzl%&J=4%B}Z3+;^zuu5D4C8|G*hRoVBFO4*RZ8%$=L(cSz~OxRI^|z) zZ{V&ZfJ6=bk1&6yj)r`2{r{@Vv-hC)b29(?eqXO2f|pj5!*YSp{_IUxH_Z^`1s+&8z^^5z2#YR=YSM?i4c8-7(r8E zqs7?_u(_c5!t14kiP>t4s})c}NT9$?LU-4w6#;#i^J#DSs9+=ScO(QQL#?(bv%yWq zNKWjREP31%6$w2-WB=a20xXFMvx;4tmuJAJP21%Oa1P?f`-~AU_}@sdqR;th0cp1D zKo#99c=)iTXX=_nnZ7w?>~m=B}LX15Gf&Mk9^u%?rS^A1;q=?CYWr zO|47N^z((Qt(LnJxQzxHQWoBNrTxvbi*56&^2uiB*!Jn0UCry(iSPSIh5-1&*B3nT zOy~8k-hMP`sNS7wv{@?L9U7Rslvv%B65(H;TUwtK5LA`rw^9HB!{ItAe8-GMf4ZI5 zv6G%zmlVe}ywG%&70B?(7*pRU_ejLm(Nj)IOztM4I`}@1=(wg+QB+I^t~lYoLMTn> zaI~-3O^nPvP@iNBEcSx{!WgQIm>pPwAeP<~%e(gXAVrb)x$dXw78u*WFoBmieyx8l z0edL)P{>0QbBLZ3MLm?8yW0R^60Jw?&-KAgKuOHoL&p2-FwplJ&RTn-!K9%lc?T<+ zfX~qlZ>oIWvRkwB9DJAI`_^6ae!=kme4;k?*5&ZD$?*<2?b#=gyQ;wyXkQdQE{>^I zj;$_iKZc+XVUm(ikb+e(9fTHyaL^YA~Cnd=FW40y* zq_t6eRy;L|z7Q2!Uxyx)CdrThnah(q5AiOM^*D}}d8sDw@VvUW)s#V`(ZiM8*P(SA z;x7Cwlofn87mDAR>lfQ)85$}JT!4A?1V2K$J;rD+Ak^R*=5R5N+{JmMAYbfntp9`E?oqO#?)mLL|v6G=rSR^3qP>Z6&WKtirI>bjk}G6SRkPw61zid zHe0XGjxXN2wl{q>ucq!Y7B5gX8qIH3d|$!7s#Q-ubIB?lUO3ILHm{4}z6{{|iX2s+ z2J5p24kY-ck#MM^FpA$a=ua6Skrj^MRaOzMCWAF>;!I5gz7@voi5dDk{U+z$WaI3% zx*=vAiw7Cf>NQSaxA*Jy#EF{M-TeE@*@dtA{oOSpPSYum9cX-+1tH@{Rx(;rJYLYm zvp8kUj-<286|7eDcS5-XatK{Luk;YPzoCJ3X+;ZruVUGH&!bB6a95}C2o@!D zsc*RQCf~v*rmikwvlIbMO`w(zu|K9UR?5f$5XSg|TN7R(lcVk`D8Wke(U+IHs&;Vq z_VS#46oiGDEI$b-8lkm!(UvF<@X@!6NPJ!e#j%b$4Nybcadc)&rOB(Ct8xL&m)P`{D(;u~Hnp z&;)1o^gYT=h3ie-B+)svjH8-To}dDkgG-7v3MhK=Xa)tU=k16m92Ww1AR1b7`gTVC3PR!! zrb=>m1$q9`tlyh6paoU+??uiEp&=J-Qt;N?98|AY&5w|eIpnSlIKIqrKlP+V>u0IV z_Yd43WlN2b6R_Bdy(j=NTqIY113WKZ{Nd7GPY1+k&Z4hjaT~1%9COEAXHI|M`(d^6 zT*Kw`6#d1&*C}RePulEcmMKbmu zbHaoTBopbCyVDw9_Fl!)WGQ8&r7ncjrF&fs^5JmAX(w$Bak#q4y3KwyaO?WC6mMT| z&o+Q($P%}>yO*BL<*V(GsVqw-p^Y)afVtzr4jR4R>bNm*Hf8hT!F5cnNd<<3T9i{t z5L-;yWl`F@PYP1!a^d6EJq^=V0|QTFMvudVk7VfkO$j5@Mt;4Y_NER4#A2$}0asu) z0Xp5Mv--XF7yZF&nF`hOr52l$A+{5a7eJ8joJO{@uJ6NLea(B5@j7z+qMWk7cX!p2b87356H#*OU%HOQr(4Q!~Tobdp z%sz->Ia>^z1-sO}x(}x#GkF0X8>0!JgeR?01GDCjH; z8{3TjAU4)*JnKWjr5|Q$*r5ClP&pE8B&ALWI;o5p-WM+16)iS$4@3ui)WCir|FQV} z`zj-+gedU0joEhKYygl# z%T~1IjBi>>>(Qa{MbQ{wCDNau&#OJzr_?VVNqI zIq7IR{TM2ag9K)?5n4M$-1GzkN9@O9e8h!cJ|>S^0jh z#aH(4K|qJ4i_M$+9S}p;`)$Y=bnPULNN z)zzUV{(uD?h4nwCbrfvQ>@m!y(OdPw7AyhfVTCjMv8e}Dr1x^A408r>=~O$8J_*xm z=UEFGS_ z2b|HHdnwRvrCvh20H6xSK@@Y-TN5rd;u zdH#U8erckut6K@m97mrGwS4E_e-3H|`J)@ZQYL`6ZLZ;Aq{;bJ4;;KS9_~P=HnI~mnwi1QfPTkOd--ap#r7Rt~=Sd4eyWkW*$CllQ0`ES@FM33VXZLh+=UPFZuu+2ok8y7|nR4YKa?z7_n1A{E}R4o#V{QVw#n~JA=vEr3#+$hM%E{%M*EBnqevu5xA791c4L4V=H(VXaRH%91oHf5cpSOE5Gy5sn z3o2X@&A<|&e3zmbj!8chIS+56qwI0qXpQG|q{sATmD2p0bx3AzrC;ECGVPb~8E?RK z+Q?;4;_3!A)5T_p!8jkQtLG5iGe0G&GoZH$f`#0pvwb%_dTf?I+Uu+^KA|M0;Pwa6 zXQ#-F<&^vm&qWM#n(kcr186X0(^}M7IwU7tbyox*QJSdN4CuG=vht!F(YEdan=`2S z?#{vBfNN*7mwNM&oLy7BpDu|0v-^!;nh*uQoNV}BG*!Y$eVx8@W>4~rN+6;ov0M~Y z3Yh_#M(C-0+{Wh2oZJ?z^bjjbt0A!J^(Ko{{yQkS0~G4fCtb<})$RdaDk6+=As02p zaE$HzN-5Vpl!j?AQAde$*VD z@wno0d*7~AMW~%?w~>47uRIwx%Mze3#c~>mF_H>&LFT8Z`LS3?F=OXdMPO zV@s8VsNkE~*;mG+&#AYUebJw(OKiY5ib}jBwfr+>YiX;F*`x@{Egpkz!^Th)xkzI+ zhB3l(;PmVeQ8JHU3Xg%^16M~=r*~rcVmd8|3+Y38zzu>coYb~XJZ@b0IVpmLskZtD zlbhIYe@$f@%!66F4_xFUrAdCH-4X3w_3hQaq$azK%H?Rk>L%twS1lP$!2WtVE&-Yi zp%Fh^;L&_g?ZvW-DYga0Am50@_n~*RGll_I#lvk~T!D9FGM5loLWVP!7GORVY9)bq zHWF?z8c7{~B?D&{dDkd+*$lj8ntEW5a8+(dX>%|hw&>02em1|m-rMwQu-H+>(^TuO z{hsrOF{j7QHHVPlU2lnx6Cw-Gny<6)$6=m4rCUqR_YWxOJuk1rx#TaVU{_%hyDG=x}{omjwkWM<9`1tgs6}MrgE3p;g|RHvG(TBtZ!Wo zMh|J;s~`fMD0@~)82j?xM^>_@lweN1EJS~4W&CU|yOV(~9<1oKc1o+qLxYw)t;#Hi z$h64kBnU8vPrJ#T+Gfq8$K4cf^7&^$1z3JTlye`V^DZKrjkj7)=?Q!6(=+SyL+f+l zb3*T7u*v>0df-C>UL#F^7WFSYxQ_9B znIv5F0n#bF#7=w3o4V4|s)UD_Ybm?~4i7uxl}Gc`?7-4X%#FrPpPT0QPPctUWdjp= zC!wFDLwtlF9?rhORb&_Be?YQ#^Slnr2c3;GuZ(6}_0G4FiBdVf6o#YMki`vpFVA|~HXDWQqadt~$MSsP6I z5KM@&B?dzf&pt8(wm_Ff)#Hfrc~@RyX~>WvM{5Roj9k#+np~5-e5XUK?_GU^XCST& zEo%Ji%<^Jf9loFb22mXTXQEoqe_+2yIrzO_&@r%ZXDjpo!}a2v=4)$iC%wfh63-aC z^=_Y?^iHt{-8T0lpmE#|xOpT3KZ-pCe$KPf_iVb;TT_}qtCbv}urqY@n}y7^Ov;bC zx#DHw*uRSL88r_Z*?S&87@H<*U)$Sd7^*A+I&ty>c`mMJiJDY%bbqP*d+5hU$vG(v z@KKxzk)4W-n2L;$dy;{8h=G`$kQ(W~L+B-?EG@hXI`3?6w%S`J>Y?e7J3Q>=gT9Bg z-d`v5+P+MqDXG!nb~)Mp+)06jW|df*4EH^tM90DPWuC0>Zf}Q{ErBjEAjww5Jais1 zRTYd)hAmmFPEDpxIjC8h#@k{*LbhLYHE@5m_f_f1|Jx2R!MYbTTRXI=N_E!d{G22r zf~<@zqMSI=0BP_5S0N@%>%Rejq22us#J4wL#r$InpP(#F$@kWHck#YE*cg( z9#&i|YDRogyvnC`=zs9%cYyr;C4!TkLqdFlfaBX~)QKAY21=*%RbRnsGrDn6&1Q?w z3+T$zwT4D&%~{?T)wWD|-*_6`U>$#J34doL%)a81Nrp)+9ORR3kf%sspmb!KZBv$L zUZIL*wV80ZiM_M>?R*_|dluVFbI&yMtS0HGEMAZJh|q^%=rE3%I)qM}kG}8wfE#%}1++ zrAiAc<0?~slH$47<%d^B=L_S13%i)6qB;QROgciS8`6b&JjhRv@WV!eXY607(W1xU9_yj0_TTwwk@8B;!D6o^(in`H*JC27M zk0RB_`q*KWF;Y=X=@m46{STD(k7#H{NXg(aU7n$cZ zpv+9F>cu@~VakDa+yc(-qU0CuQFA3p9x{F2-*u_rwq=gqe#Cp;tEp$*gxz=3_%5an zE|ly6MEN%-N-#7}i^t&)oCpCQQVNnXQaUP{H+h}wu(t5}w&3Dozr5ltbTqVR`&M0AUOZRmR9@?Ut&XN^kZ%Coc}N4#5>%El8R zZK#9*oj~q|$M1WsR1})xffgH$o*wI)T0GOE^t7C$2npYkKBj&qeolH)YW=d|b`b(zmwuTD_h+_-H=%7I4(0m<{iw@pupaV62C zV||)v&!bW6o!ix;zKBO>dY^Va0dtIMVi~b)b-hV;hGXz4$Hq!W#DU_WG{CXavI;6o zGir+?Dl;>IP6`VeSC(Pf`_=}Bs1l##AdBiKovudN!WX=T3b958JVa2UwBzi9e21w6 z7|^~OB~3G7;k!x;eI`tkWcr!CQLt%#BX}xP1=Z;SvV4OnrRChXdS~bK8#XHTkEpQ7 z;UPVif`nNTG)2RB7XDOC56jD6Z@*U3PFI-|pl7qsu`nY}@lI%9Zsp90J1wEzkTVid zhb7jjpd>MuKA)3>fp;!$;7-s{O$xcuyLS$SJmJA&btMRB8Kra z{zBK#5{uB8xUCM_!0w0=gyrhrw|C*9 z;&Q(9SFP5qbJ+}8Zpf%CPqKm&V)BBW^YZ-n`ZCFqTAXA*8~g6@ZbB4*%H;CP7C(EL zScpdvM8g}hx>cNi$RR}oCifTz-(DUMWqvGCAFxE%k>0l$XD|6~wX3iRl9~d4jdBfNgBRS%S z(<=&pmz!{%7|%z0bT++sy&U3xKwAqAo$ucL8rEoH`jFE| zbxO)K+JEOGhjgJb@gp}TW_RT3LUjathdh*K26elefMrBW(LIFfX8t%{k)+`B#pDgr z-mCJno=WT^%2!QFtYnQPvc(NAfkJw3N4tWZCi6IE@Exk7P(f4@H9UMaGJWjqiEE9h%E}3@@e$2jtxSXmT-9K!-_CqR0H2YG()L9e{iJ6f=SP zWklLSU~2TqHf8~vo5EjqIhI>quCN)vew9{|Ra2r!$?2W~x?6g~W{waaP!B46B>^q#S0^^sOn4o%^@a-dC1EQk;1hwB_&c zMZ~rVigN1+mdlh`;0=q1J2IP$Qet7zzTLpvHAog|v-{5a zi(r+^voh}oZ=LB4I$I}!pzJeve5Gg$($2*ol{0Ve3yH?exFG!JUn8pAF0*ApwFAzb z(0f6sxO8)?bfnSlqx_~OvFXgH3FRT_5H?nPJ30bSdL+m4^`$-b>u}cw^(1%s_uO95&!+XpNb5W8i!3A%H0VL32uoY zCBZnsUH1?$JVZks@D|#eat8R!R)gb)`$9CJsExfFJy|Gxn5fHiN>lYi-pkh4G`{al8v((C z14r(E0XR0!N@qi3q=oC#6{HNAd@DZ_3rEyThM4v_?OlEW62DTB46c+QYdg}q3F@H+ zTLfSTe;p9goMsGMz^w7Lp~%qn6j8~#je!Y$c4kgi-arN&qbeFQ@ai$P#xA3HM5K%b z6=ArHHgaqt!{*d_9|T;_I{5!gTSK>Xe($sYoVV`9^N`E3HlPUoLrONbWfz!pVD_5% zFWtS2;g5+jqpVAb;Yo@;n+ms7RwobPEubTfq5hB1gx^Cx?gBRFskeN%1KuY6>c9^V5ooN@^;q%5Dy7y3b8H z8*>O)S>bxCxM~I8CQ39+k-v_F6=jsGxh=B=wr~V_f}psQT2qs_(h9#*w}$IFCv+z1 z6{PQ3YM@$V9hYL75aO5KED1j4ot{;sO9HFU-+C3w1ZT{Nm?U~n!xZ>h4$=jOKAFeOWv@a^!Ap@v)$;pj zI|@DZ!!mm^J-7wkMZmI@B$7tl;CT#VD`s4n`;F080U(u5q*PG&O*Mh|yXgzx=(u{X z@|?=fz?_CbnR*LnkI@zQ4CG@{6y087{OxdRrQ|J2!F)ZYFNLQ1HB>^le_?6}+QRaQ4`~?_ zjwY<@Dk_if%gV)Zet$mg1q~$z{ObH7WQC{Q=#1#(ben{pR8(YSWW1M@sH_ZPV*@w? z0HB=kO$8s?V{=LZo9fI9bJbIublUh+XbEmfE=&)yNz5XoVs+7D^ESyV zi`gR+i=gvj^GS~%T_&UF9w^0%`a|(PZE{Zd+Hq};+9Ep3y@MQ-)bj$&WQ4qv0<`Re zUm7?m8-n4Yknm!|D3QAx9tvG%z9)^I$|>>KFL!(waF^9I^bCCu*Tk7EWNE9@fPN6L zs~+$jC^(jIE-s0t$z$Q;x6r;3dJ2Gzj!8bc*dW4O7~|3}W*u_(G`Wq+XNfLe8a|au z+{Id;>S0J-`F`(5h)R12ce+Ad85IsW@ zC?O|RA#BGeCOddR9gnWz&FQsL07B%(I zPe$?hnUaBuBC{H*02L|EjL#=uDef9IB3RR4FJ{UWfGTiM$M}vuw|yNg?WBWQ(O$J) zWP1#hRQ0splguD~rGLKVjd4ZWMFw)Eu4$c{?dFQ#n9&NAMH2`3yiXMZ;xo)2|+w4Xj1 z?kS7CdO@$F;;c(sx4NZyUWLb}4XrF=whi7FW6-OPYFy92$$eu@X-P%*NH1RSwrRi_|q^HI?RKBC++0%bIZrKtH${BbcWoDlx?a&4c4`dU0{Ub)fhQp8~m%ciHu?;P2On>^IqH z&k#|pu3-Pv5^7?DImUaYlYFL925_8;(|&5!hQmf<3z{}obd#Mwt5;F4eO^F%SR;eI zbC16>XHSh#xr`wqxgG^|pgnG9E&tWG^A)brfYquT>zQY&qw@ zjqdvKx&~QdJ=|zrnitaY2?9TsZ`Z$#<~9^;|VJV>+Ukp z>BHq=ud7>RVpm#RNJ&zQi&OD<5k4+U%6f&B}Jl9c8p0%2($>B?cVM&UYOz{r&|?Ux*XF^f75s8nPttBN#)~fv$PqRi?Nn znPe*)dE2E1>QRUFZZSMYwfKNt2mNma$W_}bWtn4HO*i%wXVT9mdQ<)ZoRx2d6hdlz zh7+C@-}Pykd%4DV6LP5zhAd86r|aZnCDr5|?@ctJ2mNhK7)^ z8@#2@*W$h@skTGDL{hYlvIj_a^(-vxAR3I+JGEQOGJz0Q(a4@Z%s<_c#wyIIERW00 zk19$}MnLdkPl*I3F=2P}Ukj}!gEP1Q!Q0sZI`o=!&hG<^(iVr3*+9F2T27ji_b4^`l zO;lS$^EG#~~sWBo&P2B0Ho0Xk1@0Yz6(CH)D`V9O(@abOxs6-WIXQx|fV`G)X zq{hg|s`>f5xW!p!N!0jjWPFK@F7Jz%Wyj%Y{MAOw5<-EC`=|<=oQ;~N%lwjTKu%eF zcbY~^qfK$Mc5<_Ia*TC!j<$b*U}cm`Wv5GJfNX3~eMEI&*_w5$WeCUy_jbMm$K)EM zAfqKFx&|Bo4S=rW5<4Qpi_znfPi<_G2 zii`8&E?M#2y!+{h+K%L{|aU{8YQL$R;>Io zI~pCU zAdydwQxy_2`SBx&LXLDYo6q<1Z{FC!q%J>|!^0X=S_Q>9E=p`CwL#U(z_2jM&>%I* zG~N6r*W^0)lE##Rlm>VPV=#k)j2=cxhg*-;+U)b6Q$w9mCHB{m>;?&IK*lfHzZL`KD+gvWq}C}j+L z2fc`&#pAZ~?LBM9AC4n>nKBGA4OrA-X5?9l@oZ7tTDn}pTQ9Fx&(<(I&yk|A&}RQI zgJy30ONqzX8jVcFn~cqSiLd9M+~$&?`l2F|K4S<7_^-p6dg|KR1a;NbRM>1Zr4r)6 zY+lEs?IcYN?%-Y@pSF5bj~LtI_3m6E53T*vjn$B^=b4;@K5wayPb98#r=2c;F76dR zr_qE&k}`n5i;JyV>S;H^dEG_4HcEbR+ObNqQpR7!Ib8m|L``|L=0i$GUsY;pX8e&G zoM%m3Q&~`24*eetd|bY%){c>>PEd!?OjTj#!($NnVrmrD)C7C2Dk*w24mpG4n$zM5 zWn5UedT4$mwb7V>#nRzA^mmdf=|qemhv)I{KsI#A{fHKSp%1t)Xxy0q?}}3D30>{X z33;7Zpx~OY-?SHMs$aT)9OIPL7;j?S2@r`dMJ`qjEr?uRMp+x1OO0~1EkLBa{DEugO-q~r2KpTOwYEO zaI1{Un8CAOb-Vsn-MXw^%S$@)KhVq)t3*SHo&qf_X zUme!~+o*gux5mcMqNv#5QC>(wX|r!>O;l-YWMl-6i(q<|Sy^S?@4sS^5Q?UT=Kjd5 zZE9i?G9s1Umq#UPYzuyS9abbZtvS}@JV*p3C#r}+L8X?BJYrKmS_)h#cb$|xjmUu& z{%q`gBN_cJ)k^BQhoBaPi+twAkYzyddeCb!uh7(3hm@qy^dyMsx1cd;BHE@gbR7j5Lj66+`G~cWimGZlJU>$4U_E#RV$^?z{3en^co9r0Dycz|G+@l-D zv6b)OXSahk&V%spAuo1f0yq$k-Vo;IZ03-^=pdk-=?vj%c&xPzwILj}`IKC0t-k(u z8-<;v;TL7(x8=1peAw8y!&H`m$e-#83QDT7R|{F5B@AJ~;y3l; z4xk=x%i^|^y~p%j==444w0-Dwtgq^rAuIe5F4f_#6|$G5(XKV&50qgpa!7WyY_oIo z%*u=P%Ai{1`TA)N;cXK`ZxVPz7EL?|mS1R=ySINMtg(*mJcQhNFz)3p3C0kHMks?u z{*?dDA2l+V`sNb|^e_KJ=}S(Tp>gyhooIoLaejeCWTe#8OkdBcD9`%#r`G<0wnQ%< zF|;tfQHpZ$ev%2g%5KVnDsRnAZ6h22Ges#YZXoCf->wkM)F%d{`iJ5#D%BP{Rt} zP*8p15{($`IlTy?r>EH5PYsVQrGBPK8h$%UI5DmbHCkEXnG0iGU{L#tsUOMtJSH%0 zH#%B>*;1FCSLd@$obAoqUN}Gmcay@`jolZwlyR+AUK9gF&{!e@-pY((;|wCltAE;) z1GG1HM|Z&v!$deEj>okm-3TrA2&oDlB&PxrGfi|PjP*t6zU<{6$fz_jILt9;BB;c# z-_3SL)}538&>3?7OkSkFzn7O>)T^2lH>tuzKV^uQGq}PhXGazF5dPo@YiB<{Kdqz; zidS1uU1XYNsb^(rUYuiNVgDryF)eHL6}aIe2>*+Vy*citl#TmIL?qi(@#fPjTJAV* z$@H?f(kJ7~nvLig`vSMZATbgKY|9xLg0P-ce-h_!4{?F7MwA6Kc=-Q|vbT(ia|s%R z2`(W7f)gOPLvRW1E`xiJf#AV?2qZvo8{FL?xI=JvcO6`U>%cd;_wJtWJ!kjF&X4J* z`)R4}s;TPg>8d&+qK(K#ArAYwhij4&EaDM)?kIH^A(kvgz5{mrA#dTc()Zx%mTg>@ zAWS^e#>Z%7Jq#FxcEdr8f6ux`5HBI4zQg9AG^vg$#>8PeBGIL+biEo?VoB5FR$?`5 zA&DBLuP9Su^D)v`G`J|MDz2aym}Q)h=U*NdTps3|U;f4SyGU@RRdA$4aHO82ua0uA z?fv$H;9wj4Q93CE`{c;f!McLJu%yDIsKPEMr?@iT($v)2^2^V@fr0yP^<>0s^W615 zh+s8!eJ6mau_~WK2%G-aHUNR$%Ksq3aR2)f><$ynT01r?J5guyD3r@whLRT_g4~~v z(o=v8Y`~l-sPZ^OO4mrugpk7=BXMTigAwUpz2Fq6E`He#unkeQK%p{#2Uyioymx%d z4yraWp9q#_@ZccQ<@@%-%G~WMFB*_BkW18Dl}=8mRko2zq+iJ*broKn9^8p7zW(vh z$Ufw!S-5clDlW&=uc+&Y9EG>2lqXMc{&ALw5+e1E`JwZK6=9?7yPjNvB<_*h4=FQE?1o|cggLCBT;sYDDpCQ~QDEoOgc zQMv~??v@1ysx%NP9$v9=>VSzlfNDf#Sax%2Q}h6?H-U=|j*?rrU;@@LKn*lFm}6^a zM)608Y)>fSK-x#$@d-^#vVDP}3ub~F^Xhg4J~XBVf} zw>LFc#8hNA6*skIQ!J@OiY^Y!FbXj_Y_5z2UGP;k%<$TL`~Ak1bNeDASB%}Jh@I`1 z`42AbJVnS&7duLcv#H*|%x#t;S=pPRb9=DLw}N;?mcGDMo|kB+wTVABp35T=NDNZ`KJsvTDAMoUd-_?lr?x$wfr30<=f@Enj!4t z0X<})!824cE#Lfc91*e}vG)@^{In3mQN_7V!^}xZ!;8bt^XWr&bC>|h&`u(^*x)h9c9$=^ zhPv^!j2G;B^x~#*eW6*EFax&|BJB+S-E@Q-WV3+x>`qJ&2$m(&>zr`=#sdA=*M+;kh~FSy+tOTQSf6vF7kgX!xqX- zJzh?B==x0!<}alDemtG$u4*Ldm=J6C?cxk>sJ4Cu_qDeoQ3SXqy8cAsU0Yv@bAXLp znqlCACa#769k|KTJ=ZYaf6z|iD+}6PVo0K{2Yj~sO%ewV*XDYZ=$`!^(N$txrKKd% zbay6E3`dJen(!osuM+JPZHu1>(vYkzw{xGihzWLjGY0;qkXH`-JfWRS_y`d`IpuUv z-xu87Rt9E{MXAviGT+MWhi>Ozdp|h3a;^3#;?iePBa0=`Jwpv->rr-Jv(Oc{Ey#MF zr^buPC}YUTy4XLw#((9hkf(Gi!i*EhA)d9dcchjaz~MDEnD@2+v@omnt7Ad}Y@QCp zLoV_%t{LtZJI6LlvOKh&Wh1+hUS&4b5OiF4qD6#m~EL9@P)=VYNT+9c^3>G*rP z94O$B?p4?C8eG_>mWrm^aHJ)qPhps>af9Gjtl;(RcQn_31hbDu+%goY-zdHzq8gUr z_a{jg%c^cP8|uCj!`WUXq_Mj>w!y(pcjS6vpVw3p_bhWq98X@K4W`Owr^0zwakW>m z>@URik4PmlJo@sC1~ogLOI0T6!A6#gGf!*5f&E;%=+tV(PB-8^!xc&26Fp8eO$So~ zFMboc8<2SXsfI`Y0;hVIILD5)e{$&}1r)&G__c1?q%)f?*Q^ghp z_U(Y)#|zqoo4H&7POYZn_W~}Cw?=e#*w7%oxO-vdB!7*AMYdfhB*=g26h6F0BNrNt z7thbVMWawk8A+N$Ynm990QDED)C~3JbbX#9pZTjSJtb#{8|?&0PnZivBfUnZ|JSzp z?*-1kr!4=a|Ct^CznLHZXNLUhpW_-BWK>}9HE%xRf2^A~jF+9o?^#e0;r&Ik##z5{ z{PP3{eEa`T;f6l^lm9P$1s3}!&w@1MX@|`IU*-S(vM_7K`mH+ZEIh2s4{t?@{&xN0 z8%MvK5}TPkah4ve5Eb!ZOBFPy(xX)`TKDar0#)R{wNbNRGyVIp-+%-WrmTn0di_6o zxxfXZErePW;r~x~Ui}N;{{oDHLxnl{4aDic*%-^7CgX|Wt&T~t{RgD4BfZSb6~ztf z5j_3(zr$YXf8#KvHfKGep%y{;uP87(9JbDXho4A{)whuHP+AB7HxN`h%V0@C_P@r6 z{|k1(gIF^0EzbYFh#K$Sy{j~8BPRFbWB0)Kqo$&PnI}8YNP1*0fg3_lXeYdY8 z{0m8n-{o2K8Mi$I==XEiP?i-q3>m*4LdEabMfKA~{fVtw{VHODu$US*W#GjYk&3)3 zW(2=$0j+)kHDlw0J9@`^(cE=EsMp1#fwgmwE}#DtNv}(9&4vH7(VIpXe)pqfcAl}} zW5oTq7YPFje$1c&IAx(9>aKdT($uiER(T;?_Tu9A1m8ITbo8E+Nl6&MoinC4@%_nZ zfoVkv2!I=cf}2t_Wps7PU8iIcj`5#8{E8NSaZI#vVzhBfda1^(F!M}kN;>oV4%lc| zwA46~jR;TBZ_y7#eQ~db(mp2lnpba|vc~YY%?%j4C5=#Av=Dk$zw z{L=2Fsd?Y}QKTWSFS9-1543Xaf;1$JF9Ed@u=_7r!iZB!yfR zO6BCF1s_NZhBieZ3A1mjNP#m`4#-1ycNYb0L<}`a$BjuOY#pY-!|xTTFt927qNU!w zThU2+r$AMSU5~%JC&a`gF=Yay9heI;d^`V|PZ*kVVk zTBz6}`TaJ=89Kl-(ezb+u2#(m2OC#4jciE{4v^!&Ym+W+E6;DFulyilnbi@c^ymE9 zzkTKDxTxr>gkky4PgJcJRT~Qgrvq|~g`ETrW@_FB4fCdyiU`Yu_?FgFKB$<9s2O5(}fo)8X67)#p6LWRty z=?i|_yCwKht>7i~MROh8!3|MS@?D8Ap=F>6GUUXC`7eRA{OlV3OafQYCVH8F;O zU2U@t``p2})klB&xxRke4mf-iO6z0-)CX9Y=qPGSul3XfHE^?8Q*QhC3dZ!XPpS>d zIp)(y(SsLn(M;x{J-9K2r-~el&g~1b_n2*T{rWF!_ub2Ph#q%8+%oXyU(=JCKR0V@ zw0Y@n93Afv>apJdX+t_rv04VdC)^5UUi)-DTwPfK4^g6LZir_l{Ge$LpIlC|)fPBc zO4n7O-$mgdA_!n_jOIT{)ogqPPbs}A%?}|ktE(Vn6qK#)oN4vAbF{%ttCH3VCYnNK9*Q-#iRI3!JbDox+M%hQyiZgwqnCa2v*nRq4?@tkh-=p> zwapMmLVNR(c22ayc`ws|ZZqX|?meXD8!3neZln==f z;ptz*veRw^YpdP=a?rTAib;RqSe^}STu3Vh7KXBt5;Nn-;Hb1IBroM~NY$?+Bd?6t z^+f2vQ@Ot0)02O|vW{D`iJvIqy3T%VjNw(M15?VHM#F5ssS@V(laHW6C_3jfpsDkM zZ!gm14BmXqi>@-5%y>qUO)L0TiNejhVn?4xR7UU0(Z?*bI~^gIy#EGTvbx@ZP4D0t ztMZ&)C%2O3kjR$(HBnJjpNjlU%A5Z*e{=l_<}4HO0g*n}-ROamdI}`}vB{?HloRTWw|2XW?sgH%5;yCjloZ{Rbt|Xcn z9Nc=hgJ0Hm*p};!q~>->F3e&=x~`mRdtV%Q;T;W`H`P<{)fhXKX!>;)R4`ssRjl8t z6iqCCP5yo@B*;nJlC0Qs*JWxw8pGVf5^>i(H<*t0)g|Sm*6GTtD-Hj%eNv>`)-`w1 zgSb+RO4*OTzcR`1H;rQGl=&sjn(g|7LiRg^pl<+=Tl6ewpq~H?9&tX zz5fG>Kj={vbnUe@{nT8X;=zI}0!eKO_dgF&QFbe^x~8Rs7i`!<>9=eLLHVDMvfpd3 zU6p0>L7pnA7T7R=r`M|Lw`W^MSiMb}vWz?o6v8~8INJ&<=cktvR5h;atAW%FBU201 z%v{tA!gEs#3$t@Pyv!v?se|;TzR)t0)>bkxXFm%u2?;}OOBp9q16WLYYes^-7a{}D zsIPEum)Vd5>H$v6grmwT`r(r?B|$L;#mP-OXCYh0dbd^gEo0#ZZ9!bv%M3P|aLh0c z`Yju&IqyYcnRO989IbS0-c8Q;jKZ_^7Vikm+%UI@*IwzD-C@BC>$v=WkL^W`Qo{be ziE7sA-L4eM>&KhZ{flNR@K0MNq$5OGJBuye%Z}`h#V9h9h%nPav@>AhH8-n11hv_G zFYvL!A!9A{`3Y=)o@Uq_7I@)vWa=8UveHSh-dqyU`T47bXB!CWwFL7_Ugcq3 zF%Q28%MdhX#mWm2%N;C7inT60mXm>De%~h)Wxvk|~wA z6233hF2>-&{4H8G_vcW^ssP62(qe5!%_Der$K{pOtn0iJ7~6qRNC(nAaER#e<91wU zHR78VvX{eGz4UJOtBFP;j&DB7Eb}5kKKHRQ?>@z5{)X&lmGYfkoB9~lj*_Vh(-QS{ z?gYAre3 zXKI536QF)%^c`e`pA&G5qEuM3!&NhTMglmD>Q3-%*j3jY4LfI+dScB;g7fT&Melhr zfn$=T=Lage9+wuT7d*!FDO6nnVd$45qY(io@97v*v3J`UEB*8r!&UF>PQr9l$ni91 zr({Qt_LR!1n_=SYZH>Im`ds~dFLfZ|L$1<|jdK4rq9up`r6-L}`|GLqD5-|g+o3D# zlkc(;zOv;3^`9qclQiJ{N0K~*-umO16l&4f5!>7xXe-m4d(oc?gr=f6%5o`HP6>Q# z#m9FZJINdU*}MA#6eDdB_Y=d zM#cVRHjix+37v^-!K$~oU&xc;*L_qoAWRu6Rz?`*3WT1%T}5t;rQ0WDiTFP*Dw8kG z+{$tQ4H6KKb)k7YlOGJm!JAg6*|msx!;khTU4E``Wvx@xAtxZ zO+plryGDbWQ^IR;5fi_6ON_?>qCeix)*$zcOzC;4&GuaOE#1u={~;82oL$~EdbkWK zxC47BUZjRvXjzS>rVx-7SVXWWp@R5T%rkr{kh~n+IFe!Kp9K{WTLy7;s(CBsO<(h# zf+my8{It!hAq2uMxF@))*#^q#eJQC6RlL(*OQYZ+X}(NTD;>l=)?`~xTKloJ&JP%e zJ+Ni{O_Rk%03J@|(F#pNG?2tU)ndtR*I%t`#I|P~k>IzQhR5pMTxGw zgDy(v!!GVh$Bewh-)SOz@5oS&u+JvgGGaGwJGG-|#{y0Y_6^*jsGBK^CkxoHnw-5v>4R*|bH zFBUhdt*r-3_O+JVnqU#}w%HwfE>Ata)VPy=ma~3>HC_<$i+$ak9hf(<3s7v%rI&i&R_cHBn=`j8WT)cwg~l`U>nmA~CQIGF z+7wP4V<(uB)6Jxs7Ww(3i=ff4up~$_}z*T2NqvF5@QbRthji{Cu6SuXu6ImaS9OEE&lzgd}yVhFO|1qwZq%{Z0(Ga%^dO7QfP3;vyadC@wsV-&{P8O&W6G$Rp5+80G z8iSBAnEBZ|#reIv?WS^~)DJ!}Rp5}yOmzK|Jcf?ll{uf)HR1?{J^Y9)CKbN%aA^*T zK>XBCb@~q9aRi@Jh^7QJ9hzCC7!(%2lsW)T2c1aS=zuhqneV3Ue=#<@e#51aTVM~G zrDM2dxp)JZ(|S<00L3#AVY|P`i4Sd9egGP(4QTF>UF^})BUzW1oJhs^EU)q~V7$?` z)=0^a^W4AUHVSUNIU0)59}gr}n`-D@(83@)*DsN)=^&T*B?xcb3nK$7-*{%wo1_!D!1;oAWe2>&;H3tcA})YmLxqft%#OJb zme<$*+hC@Mh-(Tlf2XE2e0mmjq;&CNa|#NqOz4ITU5ATX+OE69p-V%0OGn#%uCbGz zye65$3Sj5gJb|EQRD?LRmK0Pio{>1q}kd972GwH~!E{jaKQCn9x zV|eg>^2OrwM%zSm@H42rQ|#5M4D+5x%OTmlbh!|@cJI}L^^g0_exZ{xIx>0e*wLYY zxNxw{iPd2KU|)3IO&`Fbiq1Z&M4J;KDby!%v5jy)zZ~mQ_`xhvcAisy?qR%O-AOQ3 zhQuhQZauQXqJt@hAA2@7fjmP}`|c@hJ49gKia5h(c;_JD^qG6fes+#o0h&SdBKY+o z1W{N$Jr?h!(WX?TJY5@QI}r@q=4?!!QkhBBfS*DvVP$rmBExTv-`iF-7F*To77$+6nWoT{)ePT!|6a zUT2{{7PZmPD*iZMEH$*=5Sj$4I@wb`Dy@BLEZ4H_$D^CqOKvh|Qe5XwA#A&xInMqu zT`VqFX-@>Of3%;m?(Pn__c8kXyNyl_TT>J7DvWzpQw)ndntHK$oZ~XyclpfX0_N6R zi#-{v{z#qO+Nh(u{(*rRFAq2`q*N3cULG0A6d_0Nm!WH@0ZxrePreppWoHf5E#zco zza|1X= z<OtpJQ~=htGr=SZXzfu-NmVrAl&mQ~iygC9>|c3TT8^WZAUmsy7UO ztkwdQ;qx(=$TzRNG(6*rCYCq5}ZWEnbbO9ewD(-6Pn61p5)S|rC7 z+QT=zP&KO%{hrDSGl^OWCjXJS8bj0U(6DZ^?rxvJ#2YNRpzfW z3|upLMKqA-8s`Q!tVx45UStsF9JO+cn6-NmQL?)vL z#}*2s+rZ$=VfgBNBZ?C(Y&2}+a=@@shFEsoMUun;PWQZKSK}ES2SP);u+!6>J(jn{ z##}mMynK#LVu4iI4Dr*7uJ41!kX{G>h+nLmceSLolJ5fg>XM{>2D+DTjf2*Z+`oKs z1ZIZ&g_5d!EKL9(8-K*6h^?~hkFa}nLA_qCh1Q)Ztz0oTN7K_p#u;Zf*{p>{ytyFT zz}Sea0%Qk*3&sWRIq{{X1q8Hi1w0L1R4*OMXNK+VIDKbOu%oJQoz5cUjnj)5AB>aJ zJ-BjrGXL@iX2C5k0S^QW9(9;e%|F>@f$J6np9qG%<*JoO&98Xx<&o+~5I5@Nb&Kb& znu|2VqV8xd#EBA7VsVp;Iq4Z$IRU~+wCr9AdPIk9PRAdY3g@VVI&O#Y81@NhbiJ^( znK1oM%Y@Z&krE547O3WXL-sp{O3suE$tM$k%$Iukc0@a+vT8EYvNJLdhjL7*-74ihP#qrC?%J?QXF#cbp$9G zvrcBB=dCQ|mCcsF?ee(n3aoM8t1P*{RSSKEfTiNN2PS|)ZO*ZjAFqjbG*`A%@7e8m z)}6?faoOR@$;CJDxB(JqVr3i}9~>MS-owSm$0fj{rK3At-*!FT-)w1sJ~zS)U>0{EqfS$^`m<=6@{5O~d7sl0>|3P}4qaBQLu!xttfh5B6iJMo9r z4$^Z=j6oSK-R=UKr`6|)X4m|cW(yY1_~NV&XTR6Zrq$Ii`1pH!rKAFpq>%2pXJ^H; zzp+xrs2cZ}VrTZ71vv}?O{}&`J7kx2aB|7AF^~k`aiC!+vqB_)WTrW7d(sWTt1tHgY zsOk4t(KscmchFJIes$F=EQkBLVE=t3j?x z7TGp+TFzT{F?4?Q)F?@oZ!4ZUA~v7atS=45vwrE3{g;G3iLy$ka z_?kn$TT?bNT>$@9@V=`qjQ3n3_v5mM6gJ z(c~H$UE0#VzQspz8Ko6?Jc#G#8jVQ^c;*eZ<6ONwDoNtfEuX6l`)4ttIr5%r;;Y-~ z618gVdlIXYb4sM1PBJcS)=3O5Z`tL#3+2{%E1_|Q)yWDcXJsWX=K9wtsfQx3E1yn& z9U7-5cJLPcfp+$uVX^x7$xaqZZaOeufVe-tw2fncxPN)Um7cayxOTh;yePOqQFfnR zedmAKOnMx5EO}*7*FloO?IUnIexn^yMG@7tPpHuxWCImQyE`L*`*SL%TLH**F9F(KMPBCxKe9OjFR;o_3Xq+&hurGoKUl5ry*kljH`+atM#zZLs5uxLpH<1PUypYQoyvX zskE+8#+ZUA8@cGI+HZfT)hrVWz)Dh`x2NRS_vZ`c{VGGi@^MUXPWzo_ISz&n9NY(> z?ES1fxnM(Cf2^Gy5v-*aK{d-wX>?7X_py8qa2ZDO8gmEvFx=h`FYjJ_QWr zm#)9_gwY$hS^_Si-bt~vGem<{|JRkwjJwTzGtUMpYSio>kPgVH=XEETlQ+u87xdp zoX`NcZmVmBIC~B(QW}Qwqb<=~8!)HQk8GrD_lbdqAygPohqB-U5DqTysX~^Yfvw#j zi_H<@0FnnA4L#5l6De3HN!voV^x*S-uIrUTI_UDqrxq*l&Zyc<%3T3u;}FMqMolH9 zcvbqmxRpxn$}~Z%l_55Qxt~8GRN`#b$w$nG$fpNk;*ngJ%h$YV&ed98O0LG<8|WLU zXxwl;wM2HspgwiDg;Q)#hZ_GuM2K6EmjBQb=qjaFA-b$MB!6)Pe6URgCl&~|eZ9V^ zvbkjq0wx|9&xZ1klcjfHf8CXiHa2w~)>{-{pqrWR4MfgtcY7>apKeTE&4C^E-#5HGs`>A(i zeama*OOM=s@CRR0+UvuquSY7;4a?^TJa-%x1f5xqOhN`~ja-v2`kQx;j8o#FX140; z@2F$|9Vy&(p3wQ1^Lam4N8({^hC|ah8)0*2s}Ro7d9B)XtHR;+hQ=PZ@bR&%qoZK` z275KJnDQnscir-`#w@u`#TEd#AYY_XJGwTlNh(HdFnL5T2Ao%&mtrM9&r=YTfyQL3 zsx}I4rV!!G7gJ)Yr={5Hf6Z!UP|n4BnC+0DJX{Ng9co{F5Kb>Guwf#0^6|}`y6)1_ zSZO6wUjkY1Fod>{K7kj}(2_aevShga^cZC0?w;gKWMV-X+KP=QzUQ@CLSR~G-y>Mx z+m%S-uwKjDEBP8jONP2HP~k#U%A^K3yi}$gwZha$o9l!Yz~IoACr@SEj_53QL-Q>qj}82U)7mBCq)wtuv|t z2AaI0a%)PtPEONFknA2wtVm)5*a|-mveB?SY+9IVJ|Z0S2m^m#^uAIs9#wI0MWFTxVc)6)+Kxa5&)2sX|+>2h9d z86Kn67#qsJCyjwoUbC`iQpUyT}l$J6cT-vTzAG|>4{S*ly3)FbL1$!F47K4w` z6H%CEOBKm;4y7qr!KeC-8fAdP%OltYa>gs^Qyz8NUd{IzL4!YsGy1jaxj8P?--X>b zOT=T+3NMo;Ib z`P9RY+G>^20|YCoOBd3i+R>u}^LyX0>D|aG{sRq8Uqq_fdWC6Sr&~b6%+6P$s8EHB z{(AemQtP2G*$T6ZJqwn~#pnK8J^@3=zWuzZBPSP+8;yyKZJuq#B+Ot3D++JDAXNqse{UF(t`Z{#Ce`L7*EQ{C?dECe%oBIBWoC9%;k z|A&TJO+TvgN^YJ2BhV@&cIPtTYB1bt=DoZxxT z)4I4)R4qo#t$YQyVYq1ouvg^oC~tLSIO;d3yZOUmH}D_?Rx#qkd#J=8iYl`rxD=`1 zJ%|Oa1tXpSJ1a-5pTFpTy){u1*K@Tsy{_pwq;tenbIhR|T={7U*;EOwKXxGgy@g3w z#`N6-0r>*ub)MhbH-sA88<{PFyO+3AbNIIMevZDCPQ06d!-pK}bgH_orKz2nvYu9f zY-y$n2Hy<*SoOa6Ivqp(L|h-*)*>}2_5*uIH&Yg9TmcXJzT{Vs&}EL6Y8o-PT%D0~ z;^?%=`<$pb$PuXCz8*1fHAe)tdY%EHugPt=*X%{*CK%I}@N!EBv?|+x=Y9AloE^=q;%z&(QZ;OE^4#Bff zkjFiF5W#bA!QG1h{)?II!MY6IOK-&=5gCGKXM^*XaJI+C{m^V?kChy++d6Mck34hB{d(;=tlKGGQ{G$i3=W3!ZH?Q{F>e7{Nmq9(@yq?N z1I_oH#Zz_moNTnh!tU2&AxF1tLFV`h0||=!9|W`O59R)JtIyk$x8ad416m;bqH2k^ z8#jgynaln5QVsf(rOC1Ll4~9A$HCw9lLr!EST2uuGPPGE`UlI?to9@hv(-$9QZ%$Q zpav6(>F%QDjiQH%{%e;2!iPKt)`--rw8XSd@3Bq%gg=*Ih)qaO)lOor5z(x!*OaW< zJp{5p#6xtLH3!TY^9{;lZDy)>E%?>x(eksU2p{OLwwh{2n}tf2f0IEz!Tnxl213yj&0DG_9)J?cXMJ@fwbNr`|@yY03hZiM?(``gZkMHhROXpFh4u6wSI~m*(-*n zw$_vhHxzb`#>&V%Q8Xi;Y*4OYt>I#FV=%`Up9hd4kT0jzw3hE>=FYJ>x3_vJ$X71r zzRDaWwj0j83PX;16)qS>ww9R^n};PTa;0}m=LA!6;6xbQ-|?#qd)Prn<(pP<5>x6) zBQgu~$rf&X3lG>>v<$OL>%%=M<>KY@HH!B+i&9eY%BAMbSIevmb~uuMO4H|IWcKI! zT|hU7*v}+Jo72HCmgho;4C@*+1}M1tB)0F)rBzBan(@hZt2BPNOPm~LUwX7=_wq?( zt=W0`Y>s7pdERfJZ7b1x6M1h-X>5_aIx=ls#N+hT-z+%tee>4`T;G{jm1ntgr?R?r zLRO>7&D6{WFFvR9?(GIGj+X`7FcV*a#+QL?g#M`a0;j$^E$PeS>HM?Jt%V@y+ox$5 zD1T}aoSYTBord$MeMwxbr%(a<^hVuDI5$rcX~B|Ps@LYS6ATozpMq%YppecQ?C)KmyTsqj7}BHG`&X+ zb)eW3Pqut7>Nd?>ARa~N`7fK7Pn3fEM#g(r>}PrFNeUt)bAOV#Z`F^2)?cgpSigh$ z>^b@7U4G-xVya+Y;Z62i1RXYr1F~MHiVLeflY_w!EDM+SngIcpM05Pj{M~TESi@hm zz+S+twcfol5<50;LhgVKkhg;Mz7ujmW}a{ovRj5arYD{lou;IsFt*D@i@|kvN5EZ- zsx-1rtgU?$cX)oSpj+yZ7Rz}L*eUc5K=wfL^P+Tf^0-%LM}rOg0RmzM%F}KbML>M6 z^F}H)qS*inb-1&N#j}Tc?eqd2T}Ns+4|geu>~d|T9TX8?N6)if1yAK_o<)K+bDDvB z0aoL0{-EDCaI#zM<${Kv-gA8(pN_vr=Z4Mm8~72nH?{M$S}c(11#zQG(M{#cau+uG z*yud>%I6=ZKVh~x0}8;cl`5R*&$lf=w5f!3ru>-T{`{vvwad72ZesL*bZV%=&{Awy zjw?GiQRr#h=cZo=3sht0==sEe(=z~VjakM-5OhaNQ>wq-x+FC2#(Qa)KmlF$FESWz z$r;pJ4=*BAterH3>=Lv>NU$Vv?=I`k^gi8uq6J2L#`FDTG}%I;utA*h;=gGo#$l1uQHlWe*JgWTRqfL#hmiQIfuCD>HYV!z@tnT z!nd=^ta?%&E0-p8;;z1lCNGT%RUMKQT-SoX9c=lCGX$PodMaH>(>wSGf#+tY`NZ+{ z7|z#MJ1h}!y@9=9KABHeFkg}?kwWQj^>8RZdZlH7g@v0l<{}}Bnjw?9!CGW7N!+`( zJt!`LZJRHyEZwD|v}c0frgCCwcr%|%S-%;-_p*J=qW`_&S>WDKfTykJk^H(Y|7n*@ zdunTEs`HA8?lL3whDkH+4qWjPMQ2L$FOI&$aAe`Nb}Ih;l?cFSbxqY`<+{%@zc4ne zVM-)8LGm0aSfVygWCv?@1+{kK#agmXD!- z&Bn?s_mVzF)o~HY(}5#$VSNmmnu*M$`1*NG%0_sCMT0T(7Z0J8Mm$MdFp=! zy(b?ZO&}UlhEfZR_OhKiG?(hH%R8RW$G6<8;E^gXHl7BY<^<>1*;7X}UEGr&m|jWqfHk)zF|j0b0XV3YNV}10y}y$GIY~yb2fUu<%6J%0ursOWBPSbEU^4n z>Sktesr@aql4WE&=_H@2pKLcq8gSY>Xyq-0>LK|Efrc$MG?rh>X^P7~tS3LH4a?7x z>bthswa>}FG0Zk3vVN>BuD|{qm}TF~Z&4DX6srLw{GINN?E-g}K73WI-LUfvrsd?c z`LmXVRS}Q><Jvg{vL9654H|ZD@_u{a>X5 zj-kVmL0$76X?>@5SdPKf0B{q#(IpzwdD{q3t(%Nd$yMiZF&~yZy14_}1n~ zcSp*V6@nI#xBf8RPYG1X8G;3#)1K%M!C_2!1UZRW^^qSu6!J}y%2cY&KCmm(@u3|W z$t9PJDL(yX+IPq{5DVUx)ZE^G|Md9~VKI!rv-iO7vtCpU)edPqQGzAJdPfQ%B`ck(8_c z_nJAN{3jkH8z3*06~o>=+TcydY3@R+4V&N;WugeOQ?GO)Uer$0=zZ^xA}~>jdm^U7~dKF z`4U;eO_P|})>ZpsoJrH&y`K%*q=s(%^6}x23LsE$2ogAXrix|b5C}5PfcjmpPRP`3 z&HlqtK;1BA_k^GZ;b&|28H_zPSZWnPk4X8%FuSdzH`E(~jF!qn#W3GuWJ90$xzI;F zE+5zR&DHHovUubmMIShUDIpOZaxK3)L~VVV)-8shOki%43Ja14002u#w!xDjdOv6m zITjPYt*F$ht9GC7Xtr)f@>tFLc?&zrn6m@zU_s2=V#I!6dNSp(`VJ5ZLBt{8#CiuA@XX*aXLIZbon}dQl8(n zU~exc6R|CC={Vols+YS{gLg6Egsv+2%rg<1WD~CZ+G#2`%-?o*+d=loSPHjifz!J6 zz<|6k3oqmFejaQh6|T#VDO;`YHn@T`g%pmo7;RysFp_NjM`jREq*K40)m z_AHN?UiL0fd!k>PV@`O;a9wUOwr93MaG$BefT%sGW$lmfqYO=6A#yRD4PC(p1|&qY6&&lo~EGvQL`C#!-@h}UNn`Gd<9OO z3(=DVj$7IIITaEhv~hKD)Y$hK)V<3nN}IUW-E%Q+QUMgqY+@zrE=ZX6hPFc=W}krl z0m#Q8m)InNKg9l}9nqnbRx)jZhNB%jdX_v$i;(sbPly%^oXiBl*cm6ViM6aS}b3Apag<+=Zp`c_Qg%4$yep#3;H_F@UE)- z41b@z860xw1wAE?Qkb{Z^1LXP<#M}oR^ZL?>VzNh9K$|p z)S1gJ0-?@DwcYluZFcR-clp{A#^N40RAy^t$ZTzC;MC&2fZFxLxznG=jczEK#($p1 z6^T>l*`wxu)~CHD{>8>H;c_9TX-NYbD2s{DG&i@CXTfBMt=Iqbqhy5ps&SD zWf|@T8ODR4XhkyMYhq?r#EXlJp?efc9%XEIDX;Zf!W;pXS&+HN;^M@)(7)3tHfW-z z^V81GfzGoP#|Gu&mD%d5@!!J96rEMgFiJk3rzHRrs6s2X8Nh6b=P?(^x7{O*6JeJ| z$4#Q8C;h*YqTUEU9}UYVpHGf{3SaSarFfK9KU#_hKX^*_i6n~+Op=sv^(_Ndp8R#C zoL#Jsx@KTz*goO>+r!8B=h-T!q(;jHI2!79kSz>~EB+3vGZBE>xkV8uU1eQbX_+JS z-m|G5<)9ErIj7m7p&$g!5}(9G3In*B-~CX>E7B6{TP08707WVULUfMJf=sX?@QB{1TJ_WN|cUz4z? zPm!Re6j1<*`d6-*sV*Idx2_^xXjl1vC2y4rA-1kx34w|<+hL--_pv2WeNRiNzsuBC z3%(x5_VkpxtdMyb7KYA6u*Y@DQ~faC3)8a3aCWB4z?fG$z{J-jxEixItDLtOK~d{ z*W&I3m!iRGvEmd661-@U-~@+KtOP5B;8NV(ir>(4&hK}|yW_rh-?%q_?7`j%d#^Q@ zeBb=$Tx-WP43{?3PU&(;3v$3&?EqrrhHoPvXPA)Uz??D=XRM#Fl3wI3AbREp=YzzwjFokOjb-At$ zkT{j&*leeMus!LUv3K&^dVuoNf8wN-%bCt-p#@6$ZfHYod{lLPC!@!L`{W+_#W#O- zP_DsvGQ|JffXPlZIyB4KZp*qGkl;ZVA*-%tvo$|Gr%&G5H7F@WZ(dxeRg2!lT6d* za39s+>xF)BT0R$=j3(TY4$@;~q{jJRenP99(Z-0!v;0nUAqQ(BMZx&d_LhOEiwdQ& zWBny;s~^$%iYfYdt4C#PeMOYr>Qwc)wO6a=ROXZ1qWaf~Cb}#E6OyDYh5Z7OSwFqSiDS2SU*n7U zmI<`GwCT&7-dOr{=@W6F+WdwEsKgnkvA3)OT+GrFfigx``pRjuq9-?p+(eYu+f74W6eHehuP@6fx6%A2cS* z)*+OjV3)IIGu94ZRm&v#IqDknLmi}pN-34W0A~=tC(ZC~nlA}(mR3tA@-#uZ*1nuybCX)J&A_kRHnNUpe%tOO^W>|C4<0vSu_7lgcBFemYw zQ~WiEcQUNZ9N!VeZ0-KHfl&_8^QMj@B^@V!xO&ogy?(_6+a;I9PTTL=lQS!>gv=Nh zL6UVkxr-#&=}-3q>4z=e3_yqITYSqGyCI9a$;E1`-@^}9|m z5G$sW{x?)}UQ~kta+_t9kNUjbvmKdAU)|2oPH~kL3hW>R9BTJi0=qnB@EN#x=pu+3 zN0Pc=`qz?@cbo+YT$^3TP?|_X?x@1IgKCyS%RMboQ;5>Jrj@#3jY#99(ZSeblwg-V zFAs?al6#m|LT8+`YT2ae6vWp1OBX$ht~X<7*}d_qMVEg+lvcNpb3CqtHEO0}9j%MX zHK5Yx>%T{dPLCpVrTfg^9Ui7kL}*cPLfeBTf-}ZlA;WLK=MKcscPpJ7Tc*u#d_c|X z$Lav)!$B^{_$bCs;qkkiPKVs5V?Q5{GxO}kuY_j1NAW*Vnm((@bB8FYrGo;-JuUeU zMuUcg_=}v>3S5VZ^&=hDF(6*#SnN*vPZc}X9&M+HMs;Pn)FAcqI6Q(Vst-?NWNM3v zC`+GC^YzVG9?GI}&9?>y#%6R^1YM%~gtI8?%f%j{>io+gxvF^iyW$is+a{$X~(>?3k{-OV=tK>yU(=(NHfVH^hi+0Q0NHbOLHQJBNp0B#IPSKlOoP4?F_ zNQ8O2@VGOqu}!dFByG&`n6uXh7SJr3Nm4Q%&}6ryjnS=#TWT7~p4aVI$>(NJ?x>~i zZ1c=juZPA9Uia#5usYR&c?kFjG0pH`LN9{5uREtgFZ(vOha9D3bK8l;=$ONsYutyy z3xpR?GAq_;AMP?O`TBhUTe(r5qC||yaVA{e?Vt7M68fpVoifW1zD12UB+J5 zJx-V2w^7JyRDso=IN@tL$oqyrnyp2h{x3z{e~Gw& zJHq!jc>g2xHoa9}<&K_|ey<%$-bRV~7L|5XFRHU#uQ?i6E$$&sv>)?E3Ce3t-n034Hf)3E=Xhu<#4Xh z(ja%;`St{~rfLt{mG~RTXDc5Y-BF3MU%p(^U)$2-^L8i|=7+EB2yCyaAKmdF*3T{y znYThvDcBe!@v`SuSb6c0L_D5nt$L{0FU1b;w-`U6>GULyN z>-MSebIe8*ISIL+jvz7C>QlLU^!Ta5mg1i9{DJc_u7AUM+s_G}`$*fjCk5M(H*GwB zh(uXz11HF@QYSnBj4~3S?XeonS)ZfV_d9I*Jf4tQt?Ijv{S}t_A!6L=vSM*#@trdYLiN+)g`G# zHTd-cSm@bX%Y1H9e%w)z`PW)P0w?ch$W)0ym#WPhMVXzY=@_kG0z_TZKl z)q-mN%z26xp=`&{*EIk-rCIJwf4lAQK#v9nx~N&+s4_ACfb^dn(0nPQ%%lN^Cd`ke zI0mA@O8nb$xMcLBQ;nY@q3B5ip^V~nO27K$ChWf-ye~67RB)l;8-egt3YLmfg%rR+ zY#H$?hw{m4zlqTA^6T_p0n?n+^QBJ`y?SI2Hz!Z6t+}DFF(>SHv)H**>fOlI*96H0 zFIXa1aMGe?p(r4iF>9fYlJNkMMo@{4r<*j)L$}^(PVbw9uttj5nn!)e6QQafNmq)R zh@+-G*u%YJ#&uF~En`tah#<9XCP}+X!@HT(w+Yc7cNJ58h09eaYNi^S5R;wRAzuvC zlfZ?0FjG7&eKjC`ym?4=C9Jq0lUbD;=iyegSKO$JUfD*o zwpUHR=n9JeW5US1?Rp;MD3kHX??kOfc8eQVT4%io4=i)MBz-jtzh`eU8#_{!qD1ww zwkuA?B5Qw-=jkjrHYfme_n*)voh#xoARw zxmKHtQ_J|LESD`z~H3DLlT)-(og8bhZI9`s~ur%=spUZBCXcVr@0qI}LGR zPDu>|%W;+z57n15fQO4kL{lpDIg;Vi(zvBxFv>tWEcmGB=3QaSLUccH-)=^zUXUmf z;>}ul4^kG+Gko{G*!>#nxFRDbAlgTM@(BlYa;(EKJE z&_;ZHGWy66ias0l3%AS_W*AG@D9poOP3ixdG`Xszen|QOuF(xR{ zfATp|tb?}s7INV582SX2R5zo;5vDY;EBl-jXLE#i##ni6)q`1r^b1M^L_tva-?7dA zci$6Lr2j8RHapp^q3TP@Co3md-}Py)kwv-Nd|!s+jB z4FF@1U{2xIj?VUi!mG#NUe~9&$-|#wrw}wD#hXk16V*T6kDm)3e!*78@JNp=(|Ttp z3jyPYQtECwT8Yb8+Xy%>6db8AVd8wYq5|a%t)dW-@t%A<%!j3&D=Pphas7hISH-Mg zI3mKljAG)~u5iSFrReRD1HF>*k{^Tq!~)U&)WbW*ab6gIIF^!^uv-)3kS?6Ws<$rc z!gzE&l;C9y?A6e)R%4xX0N#`dysxO z<_=Q?UTdWpo+WecZ+b<^gWOgwb3B@}HO9uK`+pqf>!8ljNd;~8^d;M}rpBX>{FFBG zaGS-(FhlbcK@a6>!v4$+E)52uq@%Nilhjjsg-Py@{(kV47n*376t20(peCKt?X6F9 zODSnx2mOVe!WaUIkj)0q-DZKMos+D!zj3*>^^Rbv-Js_S+g}~4S~~i4FeQ4wjW-)i zq;sQJm~aqnGsWbzzKH9oWxCb}moA?+avtjw+T{un=RuaG99(neNrji*ye}$UQNj{i z8XFsqlA+&`$8X`6NNr3!jYMk4M!5pzpI5r@8{V3f6*uiG+yVB`3reeaQvE1-KuOL& zkPREcJOOR~K8ap(TqRW2H(pL9-F3}E_ES{OC|mX#J$n0W2`2cQWl^DRlc?$sY}+-a z_iG)W)9iWm5BwMH(WvE(D7`G6U5{Gu_7u*%=__Y8xf=-qY5;_bfphsF^%0Ucgl&wW zE2(dnxK#>$i5KMp9(8?G+JP#D<9ST|JYk@ad*NPD3lp_Z;JF^F?;v3()n2h_>ZzLO zNS1c5;mTlOhtcZbsjPvPEUHA`pFihas9=z?_k89s+tD@lsL%3klWX0~#vAVMrdEnQ zJ?Ov<0u_4q3~y+TAx!a(3WPJ=Q2}FP^%bGyGTvThL-~_~hkKg+h8e*F^yD~er1Wj& zG=G)a7BKAv^w^Hb3&vG|qTW1LN2ee}NvANw6+bB0CYMl0)V0&#_JAL?T&1(~Ol*?4 zK3Lh`A*oJ1=GE2*ku(ndlZl@a`0Qpp4(SJ03XL20ks1c6@)ayeV)m#_8r4_HbN2eY z#dXsB^{K?R+oA~|Pv6CX0&NhKpeV$g>r^Njv%T)NDw+8sTIj&H#8rE<&X`9pC&!1H zK%AgwT{u~G$`vzvWA46JUdTIzB=1UHVbc2mud=9)ewfe|XH~V^wt+XO3uZvf>Sa1x zK#jv4$g^PK&mfY#_#5i>!m5>bw<{6cfYv=McabXl5;@0b+Gp*jB4j)jolxrzDy$Ai z?YP=d5JjUhuT;2m$4EleC|ygxxqaBII&wr|+e!L@JJ0_lT11S4I!?G&PgQuHiJLoU zDv4<46u1pwrb$0%S*s3_jz%x%{mZ;A03k;u9?F$cHc_#VE=t&IEnEAr3!luIU&2)3 zQy4%`D+wE=UEu*iPszl9nGofyWD$Q;6mlQrKW%Ol3OkkDxK_H&n=)+*m5Gx zIB%RUVVIuZ_z~Tk@t9F%a`%TBj`2Zh$91v%ozCH({=UMpQicV?@n>si&um``Wa#Zb zB8K(re?*L?YQh_B5|k+O1}@eBRvMhsOy*FdY`ub@1Ndh47=g~mhac^~Z@8%zUVl5R zVfA>_=dbN^TM{uCn|o3z*jW2GZ8-!={GGnFUKatC|3iwj6Yofo2I5AUfr@>b<&EZo zjrPU!*yp(izu;HqZ2gl@yf3s{(igl*xKXSr!!i5!R}%dg!$X{>Pciq;T6{gvE+z;2 zIhvK5W{nNM-Mix{8ETepOK!!?0PYSbR{qS0wS6rt|L)N&B;961Cna00sEpGVa4*{0 z_6%rwyia>2LcuYD)5;kk7zb`kVKUYaPwK@_g zq`Odq_DCXm`01 z?Hx@wRO;fZr!8vge!;SZ{MhK#7IEd8ur7#_Y5a`Ba)~&Zt8tV$c=k*4 z{n{rrvJOjd{xLxfD3_1ZP9jFk?P3h+jL* zcf^kYdF7nvt__z+$dpBX&m1?Z)%dSs!B#98#l49{?3@8Tjb1(#TMwGew$Rvp(mcJzKG+z5{Z7hhmQ-{V4W0Wc(lYI5pj* ztM6)+xb=gR?a0^rS1Vw5!5EI<@QKj{nQ8r^^^pD%3k$Wc#7Oy_4U#T)oK)St8KRSpyaVR^yyed7m=EI z-2|C@gZAA#{+mQrw~$;{ZaE(sS%6vh(`lC9ZgMWo8G5PfRsirHC3UsjiKCUHat!>h zw&UdZx3)u3fJNM#$6|A_FhYER0a z{x8&^**zYVM~xDG%5fduF7F-?o>E$Icj|~>pawB;Us@Ge(3vdz(-3v~hr9m&ObGmC z1pq2RhF)7*eKRCEOcscSah`rc$gs<3mRu4(-a8LUuoE!|)#dVe35m|Eb;}A+%e~N? z&C^Ob+wZSCn(3}^pQcWY&1|qP9Lj}JWX(&;qRL9WGERru7+_B)5ZJ^jH|AsRvV_xs zGw#G@zq`)mfAzKf0xJgn?7DI$*{CTV-^wVnd>-Mou0u4Gk3l$)#y=tf5-23_?{e8J z#JQ__p8X4Xt)%CKFK$w3d;#Ofns9KGt8XJ4!O1>0z*bjOucNP_Whruq1ZR*xl`hwa zUZxDgKsZV?c6J8gjD(MI#~mK_^jL8T;m6Jq4=@BweMa5%4ZJ*AR9-jEbtZajp8BlM zi$YCHE#1ZQSwgyCR=?`80E^euZsoCDdULdhe0aj?1oxVldiDk2Ey{O9rSYLQw^jOL z%q0S=_Jb>(AemfZ6?5h(TKS{Kdnj;G+ONR|cYm{%RxT=+ynnlf zL#IQ?OjRooAD@R3#XfPOM6vej`_L_O#p>$muEow+evBGF1NQ*N6=R>k=m;iR7z=mG}#}00e}((b`>+1=_4sa)*oNsLfsQb7`K8! zU-bUXQMq?)=%BN>D0R93&p^{}JA8wXqOo~r)mU-O#@O)h(Z&cYVW&!ye+hiEF_UU*o5*f+CC?nlbKusx3FKZ0@8{n#c60BJ+0k<&!<~H@=vy-)w{K(BGg+jq8g+u&0EhhESzSDvk~aoj?8jZ|qnWh1 z{bl7kHMm8GgC#N!w?r@tUlE;(J--}yo)}&VUY4?dZ&KOAHoq$ntTeHw%#}(2g&vrv z3*FeuSuMf94Kgyr%2{OJbB(0_zLf?_$T}?HURS^~79()0@+D+!m0W7u)m$8zE?mPV`V$`oek5a)p&b#94qu(~^y-?S8M+E7X z+k*-g^Z%aS$N)s1D%3iJB~+0Yh`Oe(XN~cU9ZmyZu_>>VrgX>&^KV zB%cg*?3vHfG*id4M{oqWLC(D-A1qkad?aUMXnZICLNp5HR`I;@N|5Q`eteI}7@z0}698IDO8A+QN-Haz+m9t3+MkY`*dZr+(G z;Sc>VyrUo9pXH23>6v*=Vawu|LN*0?0l5KJntWNl*I&+# zVyS<^M0cSj)Dnb0|AtynOmZi~{XZ2m)T;B)e+6=Q+s*K@rWI3LyDybt@1}e2gR6ME zt;P+kK8d?sf62|zCO;m+w{CiEPldfB-^~;u=Vu%{k%lEQ{Y6^JcQrn~*GVuS(HO(pU$^T8a z;2W)K907?g;WpLsjhwT}d>&bRQw|B5SQ^Wk75qL?;m4n+jw9&rw^X0j5P}#Z@@fvf zoUu9~mUeJtsI~wPzvOkqpogeTcnBFwz-BT^_vZ+O8e1W2wekZBvJF{}P_6N6HqM3N z^U24)$-Cf;V-se~a%cb$1xxJvd%rd<)xf?#HIt9sIquB+J*e}Kh=UpX+E-oIy9*KF z58AAK7CrnDB_aDUBPl2))y|>{=Sh8XvQ>7vubJ+eeXkiccKm-ExCXAEwo+0OOf9Ce z9Km)MO)ud}bS~T>2U<*sl8@x0>7LGaM@0G9rxAEDq*yLH_wd7GK27+hG4T|a_X~-p zmhIvGd~<3Dzoz+f*Br3ie1B$%%BhcpRi7T%uDv@Qlw_y~u^%xl`4Cj;EMtg4$hR{(`@&0SX+a28Rg_zhI7Pb|y zO_6=_e>WvX99M5ZRdx!?%3cS5C?`;AMth`%z>|?eE%E=vMq+ z{ONpe;TG!qiy!UHYCxIjHl%X8aSc65N-2IwP5tAFn1S&Y(L4nlLHq5RoL3Ix)`ZiR z!1U5{hIkh-^gjdVB@j6H1)T-9Q|zhk61VZhyOuiy<;Gz0{*@oIpwyiUyLc~~Oi7DM z$AJ(g!@5CF+RXx-TNRJg<^EG_m(zCi(4{z|Y(U$l{Y2qRX;Hm!w8wyFxgwtBhK0Pw z9?r%{5KGTqLLR;4OB<%LhLOD(vCL^_!Vx>L%k9&@OHy#|{XDJW$a`)$oOW;6vIqNN zOA3i{dw;~MtfA)g`7bSLy6BzJU9i_i!g*&XgNh4^iKH-X{=9`cc>X5fW^tH0kB{*W5d_t?tMI}A}^~6;uk(Ez0uZME0oRags!|{2^ZAf*_bN0=9Fec6M5qvf z#HBdlmA{{=3Lm%_Kx-KvaIP3(CtF;s+_AN9Y1GYZMb6a#7=Z(bJ|U3|8Egw)D!25S z;|~Ez6-`hwA3xbOHJaN1pR@b(onHISGsIEtymN0x_}Jy9=xwAg=^bnmep=SpNLM4` zMxyBHXkR|(2*#S5Abx1+vnN8U0JG5VP?+;sbnw~};n^G9lcSvI=H>eGCH!`N2;m>~ zS>-H!=5j+I+`EEh%JghL^O~-uqwVIzE{oDd#YXR>Y4#-J{=E+bq`(yV zlJ}lATWL4H-Iea$3*(wG9JQ|OQ&4GLFbF?kx_2)J6NEdQVSTw-o^|;RYVoM87{&5b zL!0F1;E2V{yZ0OwCc5|L4(Of(CGXM}R8gJl4H)Dz z;}UA}XAJOx-&iR7r@auvt@}h;hR^R+k>LH59OK>xDm}2Ajk;-szO`N#asKdi_?P3b zA0@cXb8*MNynB}MPnf;}MHVT-xai2X9Vs%W9_5oel$Em=l`?0NYep~L7jW+>$o{&7 z?)s@$$Zy68R1MCHqS#!<-Av`qHkeD0!lA5Fm7i^wWAs^kg&@PfZOE-5FYc`}O9S%J z%f=+TqPyjIGB*W66KB1l!k~iNII5TNIX6Kv zHeRZOVNvzZHK%y4HRSbOXMAabP!|48DG4F9W5zg1L!WezhRi9d+N(|0Z`Ks9moIhi z2Toj3o4T(p>t{x=Ioiv)OBwN}?Ge%a(!v5*O6iV(arvuf)ZLCIQo9W2(nvX5rd5F% z@-8)%)U+%YF4^9{LyB%Aw5vM52au>|OLq#0iY|<&eE*rJck#4$s_Nm04>BQP{E(j$ z8qu4f5(e1R*t>dwCLS~}SL|z^2+844He+PqOyN9wMmv)LZKMMy^aFO1?I?lrdReT` zqH!Nd9|fv+J?sq5;}oH83fP?J6XM@4YIsgFAfX&c#XXmnsL3y|(aTW7#m6srbis(K zI2%XCe~Bz-J;F*u&qJe4%uBJN zud?O=BD?o|#fiwmOJ8*)q@kpb+rPh0ys|YN)70yXxX2XT8<&(rtqjbvZJ){_P0%XV zV^;0pu@P_BoMLJ;3pA%uxX?_-PkgA$d3Ef+*e$Q?ce9sbud6NoUU~>R6bP^gXfoNR8i?kO{7?{h^ z>=59@Jt}|FPwKc~II>a-2Dlvl`uuPOz)}g0ukEUkZw%`_2coI$z7zmc(DbiswMCH@ zN1Cnj^=S^N+si7-8jX)~wmA=*@469Y9&R zEt({b4BWnh{H!?i27Wn4HCAVWXh674F%jc&91E7beU_uha9r0~4M3y3>N{f7g8P%t z0wX)u3LT(vq7_k&BQWsdg1_2oHD$J#)(1lXQN3z``8iUmL0lY5J2G&D*=*8F$;HJ} z5T2^I=HYSId4%Fu7A)`6_>OIeykcw-E~yA6>d9>GqH%iX71@=XLnk8I>|(3Q>ZH_0 zm_*!#$GIN&nfwPpvsP`mYenlgj(ctP>Wylh*_aQ!__2$3Y#{M-=OcX{qon5#S132> zkm+9mjZ3R7BVh*1d5xuj{&EH$jktb%g$sE^d?Rgikxf^}(n|9&(?*W|Py1?8!(YT@ zi$l>|%+4G3EH!HM7kxoXc9(@?T>@Xuiy2als6YKQ{vos^u#%7luCsiyg7tzM#}Gnn z#GIeSp}bw1+b9brf*g*N3x-zb7ObwMBFodMr?_?05f(_y_)*WdseQ{-ev%k%3c>`y zlaMV&OG#Eg23z`nnInW43J(KiqL!V|l@Lf5Iij;}v`P)re?6d=w$Qrn=i<&+@JAee zG6L|aurKFD+lW7Y+qsS74Y*V{J0fj_(~LCn-13inS1q8`{4S97+of+iNy&E$Fr%Sj zR`E($H=X^516VyiRM8`!KZ%|43q9dzO+_=FULA8Wp3w<>2!2HaCLMfz7Me1qIp+eXy({K+4q^iau9sD zG5(dfqeEZ4cQv@V1ZI$;>)!&3iya%1gv_PIwX3R8%tI2Zo*)`pW}n=XJjV|8dY8Vp zl^@}2~|ECx3IAIlkr*wS$D8`;KV}y zbumBFCl`UhD1VpT!t&l-U(@&LpXXbnczWHyZ-*|p8N}w@d0y#`ve5u%zyI7&$Q~vT zkylc4F99erc0Mq&W#_zHP}enJ7mo~XowoLqe8gAd8=QVq@)(xAVCgiu%;{Wl;W|DT zbv4ph^*-Q4@ohws-T*5;P)ghXjY}Gn#)K< z9JUEVNDt~Atro${Dy)ht6ar;Y5tBl1G5OHVmYQEJHS11FU90c$vAkG0N9gYJ&kQiy zab+}BP2Uj=D@VbNS;aBc=kb%({dS?tIx2QHQVzq%jAdJtsW)ve;*McFm`wg*h3aZ- z>VxR~QnD*L{r6D@0#U;|-?2sx9GR~nqs*mH;&s?vhD%NqBg${2zDo=Z)yRm@clb(B}wwv@s4<*c-UXZe|>Qt6IUDj zm_hPTGAej9?Dx##eY3&n;<%T#$=Jvh?nU*$j@&Y72AS?ct7FEVEd-?Yg?tNExDLJs zf8Na?x|G%ZT(^|;w#N-mrfGM-mm-A{hM^jJ-XH@;cBho|lx%5R$x?3skGoSg zIwc}Mmz)g7@0WWPEw^Yy^_krnlfdvGFjO_dz$BHAiu{fVs%oKy0IU;=+VZ;7%sk!S zE~k@Oy+rFnJj#IgioMHqSMA-|yktyON3Hlh=_n436A7`gY3Y2R|I;K51RUdYv|~3Z z0CK>kH8d&lxI+d|L!bVW>u)KCV^OvE;=Im0UWj*2eB*0ViO7qs$FU0EX<;Ol zRSaJOUMV7@G@5h>GG- z*`}kJSCd)$hZhtLMH_y!0va6vO7ha)Uv|MZFSq zk%U}tGEX3FDx;4Le|$VV&SOJT!lzwx%VOjCjNV}ak0PcLBgs4Ha+`mCxue|AS9;&% zg>v$L+*ouJ$UiUEn#=5Aq#`NnQ{H&>bbGHbzo3$RXS(jVCGtrur8?@bk{kSX< zm)qDn`}1BE9P;YuFr|Lh2IY8KW$JqsFSOu?yYW9qVMQQS9?Y+$tXl8Xncz;J5nHP_ zuT7<)XR8}=tx+jql%aqwd5`E9?1cK#cedm zvrM+bKpRoNIn%x+egD%m2LH27*I2RhAGxtNo=5cRG;dpEs9yV>kH`96Y`SJOA2yxc zRGeIk-TDuS&3QUatGAs`J``&TII^rhv0SBZn?23Ze$EXh2xw`1!tnf_4!UYV!bnOc zc;btW^cz6$$)lLqY+Zr^bYL~(+$Z&61!dp89K~q9u7Vn+@uY2lqGrHYDruQA#!?~e zz&0ga(R2EOniB2r;L?}e;e5A2M%6J3XP|sxk_iYs!be5bB``Y+n6F_((Zy6DI-Zs= zO;biiwVOq~Oe_A*m9-v8WE?PTQr-R#$6?atwgpGb?RF{lX0+d}W2}(U{pNxlod`Qg z#-PZ;E2&Z#ZZ>0QZdg47eEM7RChir10jVD z{NkMrqa8M;gcRvfsOO%vn>IkJjYEHUyC%E{GE3+X=sh6dyOA4x(6djt2blL|ys^`Q z=Lz;~vdhN5(jY36JAcHJ^EpYT+Lnbv&>>x#OD%M(xD$(q;?R`NPbQEWDUjLR+-#Cc zbvtkinKN%*X&q?uJpN*QeHET1cJaBPXwKL;KyN<3 zw%^BcXIQ`(VRC|MqHRZ{F)XcIawT zTSfF>qQ%mis_n?2Aj`b$7UGiB;|_CT<@@@QEjwmMmD0QH=g?~Znv?K#wa;FQ6(V8i zYM5Q(7iDLKt7z;RF3Kg>kyFhyU@3Y2jP9kjEZs{LVm(6ZQ= z3BPFPayD0*{qf@|g_A^)K~A5_^$p0W^>R%G)^@!ic6$i#V{f@$wNnwc_Mch|Ix-IM zoLfxrWM8xOmvpxe<7Z=GpAnfGc-hw@dOW&Il;vxZun|gR?9WWC_KSklXFv>phz13K z6)ri7Y6vB*7kMt5x0VhS)rCTQb;5#GodYeSrv@NBEn{~-AN9A|pv#E~VopPo6^&$u z(LJf5gMD?Co8<*or`DTG)c(`wEobvSCy8RsjVCYrVvXjGPEp%q&-34GO#6Z^nL-(+ z7uMr;oOFHn3kE)w|JL0VKJFzuBQ2Xe-@v9<__c|*xwskqmvO|Ifq}I2jQLDGU>EDp zd#k!b1fO?W5(1c$qj`A3N_+%?YF(qVbW1zH@gR2NK_$6@+tPQ8ntQD3M`8^7qcDe9 z;nQD;A>q^Gz09jFr>u*ktlOHUfq69Y^X2u+@;$%3SgW%uk^YM#38$W4Z-vM`ZmuIi zH|zCFJMWqdDH%YmC&zd%9m~kI4BnUo2Uyc)%AhdZbVbt3Oi><9TUzNe&Gi*KtY;nC z%fm%ytp-zy4$5sg|#s#H;@lPqB>J0-sZq9<}>DtzS#G&zPo@ zfwrkxYOd7_E6YK@5&L2N*Ky=Ur>MM$tDcSAUOFNr7ReUw0zhzIQL3|8ZcKi>U!$Hyvr9MsK0Y+&kFjI~Pjy_8nMrPcC+!Y_X?pdZt*TZ9uVp^1bKN+cM2@6*s>9 z5fq!)v%lsrh7g-r{MK3y+M98zT-#rGdkNZc`@PwL3DO_5!6+D@42TRk-?`>LoY2NB zY55+hg>HpIS*6gbcw(+)ce70{mraYWllSM9%{d-!dG6aAmoe>A7 z-62(;!s1LQhOqxI=J1{2&4s!FwEDqLBDgS7zz!?d*Kodm4z-zRgBC&>dJ%1xs-!3w z6}`#3Y0xGUNjb2p=bm;yYymc zN251)2K^BaRzXQxzjj>;l)%Yg+6-1O=}Ta^$%e;zAU!MFq3I|+)f#H&7v(miG}Z_y z1Mwi+YzqPg6vvV8rh9aH#$`csmOJU?lmfOV$mAvu-_x$vAci^bwemLqtCz_%LJ1=F zi-VMwx_Y#NdUOK1Jpz;p?jXfuVFKqHvQHub^Ox<@R@)98y23*oj>KtHS&ZM&AKi70 z%vbulUV4z~F%EcQnmcKf+f+248_8B(N?Fll-fX>U$*h}Z3B)n7NI5xNc~*MKB)3*u z(XA!wxH-ywR!O@kw3ige+|T$Sp0OVuh~_$S^(eR5=eD;)1`67{xVSzOyXomMzS*b+ z!9>qH?S@2mO;5b8G`A+W8RFRl>5M%H4MbRvg$J75`u&H57}|Wt7k(wfdSbFb2m9ET zGTn5QAv&m-Daz$4&t@FAS2L_HV4ktbn{||6PpaMGD=V9=52cJ=oywq}f?ATj;$8Q2 z{CU7NcEEx3;L+c5tQzcjpON)3Gwb8W!nk1qSDNJL&?8=-{k(zpT&*6J^r_2}1$K|! z>)#y#ZTnY8Do)pJDs!HL{^K5@kxJevIAT9(_DiGt_=I8{Z-bWB%0mRHgh6I)OW_G< ztk@I+wqBD$pXuQ3C{v=;a<3K1hROcyUN^t$jSG5&JFBJLlv1sbqLzC~nJp*6i3@4R z&G|gd3H$X3Xxe1i#(Eq0bryipyDN4y-A;1UXUDLbz9asik_?+1Bl^4x_oi!_% zwS*P7`)al{Xe~)Yrw34t-JqEJ^4o+mU{BgU&L|xZ0(kS-GFQze?j03!Hjc?a~BQF=M zu=70i2ty}&d?vE$1iY3%ugv)|4DlNa`G5DHzsW_h%sSt`5a;kB(_c@wH_zg zfS0c-rDShMd>GvZAbiBJA7`*gib2SOs?L27&U_$jzF~8oe;ZD*0BbTcjG^_O z$iJ9a`y^;+l^J>FEa<)%+{HJ>V9%zbmr-5oBIrNy;%_r1;;no+gxg9h_V%g^l(!|H zPb}$@ow#Dw$Ya)Q9&3-MmD$x+xS+fc926{}7+;^-+?;lpbFtil zm1OynE-mP#XL31J7jCQQ>rZA>fn419eb&QH()Jw1+y|k*y#2z~=mHAgrYp#(8K@N0 z>*t>f5K0@eSQ!J%jm>>B#GH?R^YvuJOc~Tv2{>8#bzcNipytmHj5Kg&1~?v~&CS{1 zC7FYRJ>j9eAzQw0BliKsxO=uu)#PhJi}E-qag2nORX?a!D|W_bcV&&H?OagkXKn+( zKG#pzBX);$x7`^!GJP5SCPX25Iu1px|H(j`;Su@}0IEQEc*Q=&P(K~sZ13_Qqbktw zka+yr#O@>uRaT@Gwy*2*H}sx_Q=(FbjGdkIjP$`J6q`nACe0|~h)WA#06&vBX^Jbv zQ@X7)%Wf-YEN9~9So$DB!pYi}lUJ2Qf!kScpRgMsD70>GIg!|JJ=9NZ?D%z$1nmhv|$E$y>E<5mg^-e^{n57bbj6~~pAc&YsZKR7To<%BHW>h>99 ze9AjGdV^#UIKeH_=8@D~vr-`Siv$F_flD1o*v`gv^K1UKD|<`r*=HqX8wb>TJV$wC z;<8*leuR)0$oNZGt8!g#1E%Zdd_m)LZ$Ck|9ViCt4eDtX<@5ROP=gvCb{G+HCpTc; z=}6S@zm8#CcLLL2N7NORxb)ZY?@K6s;y;&AU)=q6zKIdRV2gS8iE0wPQ;blO(*M=C z9qNu+ieP}QN(RTvo1EAR3Bk)PfwMRd&C1+{Ok9Jr_u>*K6%y{bRdgZlFH_#men*OJ|fxc-(#RK<(KsV`Jg%Oab%3SGe*CEiF)ybKY3b zKAA$Nq`G9_6UokVNtc#}5G2jA5}L=L7QP5j)L*XF&KZR0L>6v_qKwzr zc(wW{AyFFNB&k`A0PpLUKA&&&REO3IPZA=R71Rj(`iN65^t(*_+&o9&cke?q;!Y8XUqD+IZtAhvBtxM@oarGk%iJ}ht0VWQ}{>N+uP%B48w;F z&ay53XkJFd0_k0;jy?V3@VVgUW!C=N`0fYxuwucHE$8r%Trj5y zUY^^}GkTL&Z7CYk`n^~q$>e-XEBef$NJhgA9~j*I^ntFhn1`i!mbZu!W}alBX3a?C z;v=mS;)df~yr3LL|J|ScEz66N*tz1cZyz;5Exek~wdWz<6~+JPMnFl3+A-)13$Qk) zK9~3$V!(^?HFD1tlf-0*zbWpoSy;Y~#Z!>dolGU{u}><&>m8ybF8S5tng#?nM-Jg9 z#$v8jCsP3j&MbOm@?>o+F zE8l=Oc-+0;Yt<of;$9v z8C-%pBxqo88{7s-NN@{IaCZ$ZgS!RSVQ`1R8Jsgop6C7EbMCt9u6x(*KW6PUdv{lN zb#-^uud2Jl*J51hH4MmqkC)@xV0QWfyrcGzYZG)&VXhCu2*$TGrg`6S-RUXXgcCP^ ztp((%bIR*KO;x1Q%T3L6i_bqMxdPh;vvbY8#3l6N`%VI_b6Kxli0&edd|QA4#N(Ek z#46cSK(a7DE4dwKk_B(5KB82g9{-mPJ$SK6RrB1;PQou*tN!;`lenCh_z@MvaoOe$ z_~{p4xh6s{oNoM0*DXhotwMxiTQSU8vD7KPTD3V0@bL!QWXMA3hnL!<*7-5PxJtMp z{s0%)$%u?A3aJ(Y)~T2)?eD<-$HShB<=@iZ7_tIpj>Jk|(nr#VD>~~=8TD_hgwI49Dg(kJr z7l#9xt5x+cMrnb1QOo$sQRt)}{tP5!e8Jzyg5Qw_|35rQAw>~6t^X(_?sqZk=>Eirh8oSp*4WX>!Nkz!_Y=s-5{;9Ujf|BH`9vlth{hssVr%APPR7N~ zL-seJu}E21JDE6;u}E1PI+;kA071qkXhK40|CHi3*QG88nrD5{ys33a_pmZEprl9n z#rzm*jrf-*&A0-_;fYT|_PcB&Hx`wmQYK{3C_iEWK4iZS+K~3f@#9mjBO0OXOEy+4 zP4V;no@^fZKr5M*IpgOc@0&E;h7YeWhw{=B#a#t1^YaCk@>FvCT}B(8dwz0P>b?)i zp1uYUzX0()#(Rw|hq+B@9yRjDt^HZ-(=h_U^ihS1d5j=wo2nbn`Se`eP4cph6G|t z@-{Itfu2<&_;xStX>-ukt*w&FcmrE9Rg3m(WN`fzYah57ir zEoM#;1}6wUXh1dT<@!Wb!ie7vk^EbmP$%*>t0xLG;SSi~%x z9FK!o{hpYzja8fQ?l z=_q_DDAF^@#w4)8ZS5*3Po79*BfNX6FU=6}CCt(9~&DR7Z;bDoc#U!OClm7Vq#)!Y-~I{sl0J?#d**uuEl{U>ICO~Mnxn>iZ)_&NLJQc~9X_;dSEtJy(IYN4W6d4iw-(}R zYisM_;UOz4>*?vKu8yPc`2KxwM*!BrLL>g$w{LN9oOY*5lKvL|U_`x5D755FBOABz zUf)by1qaZv`!1A;u#uD7ve_Hh)14c3mL%QgdQezc*x%nD74^z`o0lW*JR#xDyA!2U z!FtEd;V>eeQiB%w_O|=w@p=e8OGABqy{hg%1U~0JG5A`61!U~D4aFb;v)7pH4bCK2 z2m?d9nZv>e!CW;~dowdtR?c200uXd`^va(<%ZpYe^_x8}m)agTk+86^G&#`H(t^QY z9UUDcpBNb#<>Ur{|JMJsl_u2djSia&(7Jafx`GL4*1ZvWOQ6H)VqrZoQ&gd++L`%`?SH>VW-Qcd#|zUVBtrTJtfyxxDlASq6bly`kv@j>bTR+{ zKu%81$$2`QB7p4e5vTu9`c5{Cm8dt+0&7ot;HyG&D49YeQbiZBSEPjiP{Z^m|=KrX7_3omOKh*v!NP;(p?=&?J+#KXgb?CS3t<+gvn zPuKtSKb*6Gr~LR4w22gwlFGSVD0e5S02J&^8#7%TY~vMEzMM;{wDml zWp%EQv1Y~S$ILm0J61yi>R6w_$g5ZWy!#AhOvXI@h<%qUI`smM0mt~8176}5;p&Rv zQTSHCG(J|dg0Kwi3K+5YZt|-wb9=@WAlmd#&6RdwOaXdW#ov*)vrI@74Z(fxyz}c> z9Z&S*#5deaE5n|%s6ru*HHv~$HtBw+#;|&X_Z#h(f2fGqOIc~_ArRH0gpU?9n9`}4b`8xY3CV%VNAPQdg{^DIh3r#Z z_it43GsV+K7CK^09q1?d{+n@l;~*g(1Av->r14@=XljnnlBeB7BQl&zsZwst0C31# zV;c8?*EV+GKCVf^OKsf|K5tZn3#_c|s6yQNF?? zC(O)iBQu_*TDTOoNPOMiru4y}0W4NuZL9MBCM&TLfaSp8-HO&Ri8jIOah`Ui+XS81>&B3=_;HgBbVaMKOsi0qZyjHwJprk3uz=F*i{ZB^cRDdJj;3B_u{fX zN{NZ^Y#AO#f2hatoWBJ*8WI!15pP=T_Pra?Q@!27)8dO3M6>+3L?1J(#u=qSOmq1Z zfLZn9xCY7Vg(nploXNn>3(4Jx)T7o%dp`TVXPRN!#Jmhyxy&%9)2eH(pP-3f<6SO` zg?vDbm|AE2nq6CmV?>L$QO@C<#x%ra!f>tXZ20cZcHVENlwIbY^T)ufTOnDvq+mes zT#KCR2R?V*JbvhHsh&g4LW^bM4()>4&m?sy1Vv!jvro)xJi2t^)wHgSD@$5wDDQZr zTG;RkuE*Q-zJ)9_Vm)mR=bDdv2Gl1Py8K?PpGn<|_^o;*ee6qhEJJDVlR$Ojdocs+ zR_ete2ubOap}FWTgkSKE`hJ-7p57&j!AWbQ)jpJsL3R4l9oo3qCGy-msnWgkq1X>N z6EZepOaIIfZ1V+B+e51yQ=*jilLK1+=tuOe-ywMw|$qGUNy;d;N%E<6Oa8s)CP zmQol|887&Ybl$?qxM}_HV{uyZIguvZx!$GC5+Ma#RX|k))*|&1Q_CSPY@2X1|-*DHqVJvvLaLT2(=hp-4JzgT|l9l zMHOo$9-ZuI;>+@-s1u$umxC-dL28MlwTr74g$47?!}kkbgEy=QZ~Rig%FFwy z^pv@?kP{FMLAu@`4nUW@i=Dm+Pm%~-f5`Q}>*qEj> z1v$z+so_kqgjs4Skk{Y==XnjaZ_|;H(HM%KIvT6u@24VL!*70pQkb?_yW%WGowFL? zFSSXV`H4H%>#dXZ7fhOlgMMZNF>n#)y1&$k?MTGJa>Z^y_!Ls!jn;MqJ9j5|Y$BJe z^(jNnp}oYGv;|d$+POzfDDg}~3pWrZE_yI=mWlhqVvm&BJD+oMB_ClOy&UOEx~9A} zo&pKPxhsqnqWxW3kwfU~{=C@k<22!XCjK4z$`&`b+i+%5fm@$K(9<4Eos|WnfkmdM zRdIE7>7pPKNd}B!*2G=f0rjU)yS&vj9Rac^RPwy>FB?NqTMPGONvpDT}5diNh!XLyy2#3{!dx&vx z?|g2l`&=7B!p*m)X4a?CcA(@7Bc$`67l(PjwvK6A89{XfFiSro`D+jW2G84S*Q>vU z=rLzX~tS1Qt_)D~2$K}YVComR=&jcw4wth`L9S;A1Sc(6wF|1_O|0I{(iPimS}LSH@=^=S zf_cuXZxKj(nY)zlo|`>gx&q=6R&VQ&_t}_Y+6v3RIjkL%;+p6UV{ty|Cuil_YB z9GM``dk1La!kXCub?2)^qMNP;#P0lK@I=46@zoGNU@^$`=~;0axRwCHTA*kFdZ$=j z&=}^W2Ms3Nf;DYU`)o0v^Nn8C&^ynsI+w7%jHMT#+lqQ!Ji(*g@v3Z#YSGKTNX18HyH8KR`I~A@_yKGt-FXmlXrN7sx z;yEH|{FJFwdhKXu@`j!kKfhfPiJCot>OjN8nG5$}Lfn~f3OFpQ+S;=M^WeizJAGnP z&$^$%^*p#TUvTGoG(pD_*a*#R%$x9!_|ew5$^5eqY9F?sHYG*^ z&CIuKW}Mf)MWbFmN^2P)!Js}{W-QNJ1BD}J+6p`#c`iZ%meUM)$)_gQj_^`T1PS#} zw1$~Ae}I<#@=OiaKs6U0Q?f9KWN0K2$_$a(fDNG<_%JVPbgiMZ&`m>Pxw^?bGC`xo z;ou0ncb9eucp;(`E)XZ(LmH!AOR45rM7RNqIP27Z)YW*AX0z<b z%d@NwEtEADc0+Irzs`xVE8bQ`re1Q1R`Iu>LZ?QS>LOYYYzp+~MfpS8o1bs5Lzj(X zmFn}1ZNobgq7yY&7IVLg*LvCw%AE1iURwZ-t$jMenSooXwxvo`U)KHe><|goLjT@wZ{nd2Qzwe@DBEf)%M17?kYjYE@6rLheI~F3XNY zwEWDWFJlixgXWFyfX&QB;2+~kp%>x@>PQ($(>>uvPR+H;J4k)fn>&SeV3u78IwTdI zlKstXdk(H}H7Bd1d)HN|WeKZR&&Ff`R@)ppkl4Z|!*ci?i;`Lvb3%l;C{vYx0=%m} z*e!ByZMcHnsLwg;s^cdiMEs&pu5YLf9lfnmI z&f#E_=FIf~`+h%SY3depgi-0ld9Lz~K<&01G|2wT(+-5RwsZGj6LfYl60--3b*7Vv zVb}R8OU%TtNKs0g;bG3^8y*6nrrZG+)Y>;hrP`I=C&OQ-hNnH>YI zOKWgmDW8@8N{y=JLr%A2mqpWhOs;QA*jeXHmsd6q4!n#e)pMGd3;7ie@&&krY6gPD z8*8nhoVM}K*5=P(fnRVv+;4$m*zKhT&|3N z?CZoTa5R8>75@!!`Kph1*L`Brt>~)c>%#rwFK~svS*pY%@A(rg&kNG5qdL1e&)Uc- zV-0GXlsa&9TbyaC5xhj1_+mBS;(E3uL3u%7kaYWcrF52SRvme&B&V?RT@?QPe)BGg z;#A|QX}HQ|6YYjDK=A^1uTPZjVaJd2mi!le;IX^q}=M^iH*H3D{o&@ z`x-!%#pPZFsRL5(cwieoT8VSWz(Vy~8{+D1#`BqaceN6`$yv*y^Ha%dK?!J*K`nLC z&|BtX{L}gsPou>|zII|7!<4iENKo@|_$zT-2Lp?H>H~CvMV(N6{ENkd>y}3dnyX~j z5`jm(*Dohw)xq_`J_v}uMjd z>MQMDyD!XF4J9;IM77YTdF^T^K;*t528@PLz0~ej>k)@RG!eV7*T!yBp0k#nyk}ky zw+~CHe>d?n_;K1Sq%nbe*L8|BbezoM&I6jXoDhI36#_A(tL0T z+{gr3h2_<_db3^|)AOVN72JQ}BqZ&E(Ub5O93Gcdwn$vJ2Cnc4#>X-ft!stBvR26Dfx6-uHzeV0bk~|se@bLLV&wWL_&&Uv zqGL6pETVveX0^+4(dlv!u8?_^RAsP9Cc1 z;uoLu%=);dt#^FgaIJ+S&mzr9D%`0!UyzSgl>o}yNG+CR!Jq;jcxadbch51Cuz`0v z)=fP(-)?_6nh{$w$@9ER<1nPUN&MS_W@ChH@OD77HckB9g?mfY3nm}O%Am4&i?sLG z8lw*fm-GL@6cPSZuM$;bFR12r(p%#EPXdoz9&0Gx@WThQshb5-7O7+i<*3@aGa&7f ztt$UwSr{_1AL^PS#VO!-lSKcbjZmVo9_NDtoNf1q7tiT~t768-1te=y7khb9d?|F{qyqzfU3z(1e-#R!$l zBRAP6{6&E08SMIAcx##20lh{5!UcTnC;agb6=s#)wrgAhskalKJfQtJqy3w~R zp(R*aj^{9^U5ebc*Ia04fzbKm-1iV-Eq%^{<1aHS?bvk0;0v7y`jO6sM!|=~BchL+vxYl{Mi4FJXBb;j zvajbzsb{xr2pJ5$p5se89nrD>P=tpJ|E{Gc)ra0ao@2prkEaZm=6-ZT5cjQfBL~0| z%pd~HbLoY~X@VGT`TBI#z=<*2D%=(z=316javvoeAiV#wv4YF$4ruI-p+VpLfM|hB zyn}yI(CrpTj&}7ZHLST36@e5psE!EiHD@MD9YSjzR<86VcNdn^n~v&!$bv35Syt{i zJ{s7)1=Hx=!4b)DAbs?&j>+n* zaeKl~!A}g?b#c6&TjXbi$MjYo1eunJD>?2=ziDz0)c4So2~#>d$0X{<6+yP~L1@U+bkhXem6fRLVjltQJB88fpn{gT1BXl0w& zM`|EEBb47u%A&2;j(=xV(=Kx7L=Cc7-3i{AvdC7{o96Z-*TkFS@VoIjG2C*F72}E= zedlN2+lPa^-$Oo?agjU%XbxLk>x@-0uCJ}~LVKXl24PIgN}V{k%H8U#eOt0OcLBY= zb)Fzj1K_xTJdNH;-ooM+@Sv`TvXSJt5BSb~mlz%+2aQOy^8pp=DFWn+&F}<1Br@+) z7@3oHt%A0Ie}*jtu;#*qn8-PU-hn@6n9Ivetgtu%aB>)@mh}$_0nLHl=~I<$L;xSf zT&*7y?nz&g@l@Ca@#+CmGDp3REIYxD-e1F;M1sSEKKLmrP-wAx5;xqwSZECA4#Tg6 zPSV31r*dK4P8pQ9TOyjx0=-GUCB8mh(3ulL`JB51TaQpS+gajKdg*#B zrrt>g_K!YD2gr?nKIgja!|mJJBjL1o;O@|50v-Z=gmcri`Lj3~AJUkauG(}rYtKtBApRRwk zw|L)xE)wmXSuXhiuK6dkLb(h8VL=#tbHe4|)V#_7^(>=7=;`sGya83;=)~K}U zsrOlm3MDGF1|x5os>~_)f`!~s6~qawyN(aN*x!cP1OzH>Z6Prl37IbwX^WYwY`#UU zsTujyi=`T)6?|gjB;VR$S@@i{b(P16k}FU@*N4(1r_{G!#G@%&w}OPTaP$r=$R*!Pu1e>K#NtP4w~X|vPSk7ZptK72OLJ2sto9xFJ`#T`#H*lm zPIF5)(Qc@|_k=>$@EIK6H-fxF!yICx@J+s(PZZTb-uauH21Ygie9k2RYlxCp}jye*EJE^OpL~j%oANY|!mcdm^)IUo{i1_4Ztk zFH;yya^F{24eYp6)l~BQ0E9!glV-Vh9S&K5da)^UGS}b}j@333dtW z3y(l}{DKs;vS}QWa<=PgL(mi1QHByk??Ud8{!2zb-+1$V-pIuTgI>0#4bGxEa7Y)e zW8}3l!;1(S-im=CHK%C)P0xtbpk{A1Urv5yrMA?-`MqZ`ZLy9K>AjPi!)%;YdP6n$ zvf{NcMsIy_P-fGTUHWZbh2z=-ro$0n{);C`57Qx4F;KDfw9pQ_?pkTGlk{ zzS{4wI9#Pu`bwKVO2T~(u__10OJ?PW(_bD0_+w$8a+@bhP@f@ppNo|pqyv*iPZzBM zP-KgleB|bbBR%?}M>KCf6dpb}L^=rW$@9^>oF-T;Ucg*c~&s;2*eJVY@@otO$sRt#b+R63a}j|F z@0Z$UVYUJ)DvZa_YoY2K;_7TojZ$zlZ7I^nYTY)XBw<#?^q^u18Qj;3+UTnC=BLmX z)xwx<7_XV+6T*H(ZFPQr>MapcP7psoy$^$wSzb~&yw#6Lh}JH2Hw|hnb0SrqyLfb# zb(g&BTPUgX6HJLyp`i?)7prO_B4i>7Om){U-^e;rWjutbeBT_rj@bIm2A4`tSp-es zRnGk_R*6Bx%1X?Mc)|REUP>HGz{#^ZSMm2JQcrdIv{EJA!NL5c{F&D#q-(It)QKQ_ zI$1-;7+NQQ2AnR2sbcZEJn9-!38k~YRTyFV6>#5Fwr(7g*P4^TfPE{s5Md>drOM#5 zP0WxWkqU0fh80tFKZ6xpCxB1-&?RYBQ8vGbR~!yJdaxwEaP5bE`Ght7LmxcM-G=%Z z#}r2XB5&zrD$SK9x&Us0>T3^rP?{gXrO?R{|c7&QFgqxiRLfoqkM6ed;FsEC0IbU9$xZZ z!I%f#9VJxyYkut8&}%Y8+;whLmG^;vj_Hu{=I|N1uD!jecz~?_e1xzVQbb%Kc@P&7TEiRoW@t%LGrhqvvKkIkhuQGI(TF3U5Hj9~Lk*2ccF?%q# zS@Ew=G^b=BiU=Y6ON(bMEvvK+2Cbroo1=o1I}|#8m}-km6p2|1JbvzVbUQIi=)AJ_ zAW2J##*e)lzr>?2R|k{v>Jju}_jDVuC`18OIW3P>uKevrPtgRvmsf$6qqE;@v^rNL zCM`m%+UXtDtS-^{ImMTaGx%{n`7LVJ6HNd#DK{|rhiz`ksavQ0M3)qeAHzuVgu1C;E#`1b5S0F8O&jZ?tF!5j2T&r1euv|;V zUl4cd_YuJ)d%1pN5?3bu94Mflz0L=Xg!vseiH+pmhcIiO3lrp-9HgcX``?Q_RS(n~ z@KF|{>Bq?p<>@`_Aw+c3GJ5qVdgE{VGt~z)9JNf+jRE^)@K4294vPr#3;8$Mmi<1b zD27GIrk{^1C%3a~9-@sDyZG|xY9^6`t&APM2?CD$zn^hh+GKqncpURGq;xN%xn%tL zM?XgXDDr!LUJDMia1j~%UK@b>7`#dO<;zgqf^XY>r+oN1DN z)Q~+G$C4Czf}UL1L!rS3?oY{-Xsb-Q&sHtJ-h^~EH4HsDpzmtvP@5 zsg21esjb&d_@`jtscA;I*OP-9+KqYL1tE>9`6dM^-T+62? z&-pzYi3r8_^uB)85237?PPHZRtGS`#&Y4FW`(m|uL);ZVH9V_wp?qBG|GsmNQgSzW zE7V^Fv{kkDO?`uG9(gn&Fw4wr6nQ4fLi_!$-v&sG<#>0LupTjbT##SOTAr~>mTl%Y zCizI{r|(Fzs4wh*ZLSyaBG&Ku)k)uI#d!!yKzVdQh1qpFs|A2p9>+Q?_m25O(WK|j zd|3)7nPQ{cgw4Fe>6Cc=#!HG^O)2I?cjTjl%fLI8r6XokzK9aYHQr*Gw89!UdP_&Y z>}%&7{s!<1>X!B&QS@#%ZKOeriC+Y}r%U~}84Iq}MSZ_oNeNw^iiKl%o|;cI173JP zf-i{lua07Sao*7OV-;X6-mpL2uls!5B}|)!{W(|JY?K=?(loRsgEM)c0KiFF)mfdq z_ytOQE`)ZnDZh51{_d$#q+miY&(>$W9XYSSye`)*QZJ{Lt5GWSl$QkP6(5OCH*F&^ zcVwL$zAS||PTN(@;>PyvpDj@|a3pfcm#bfsj^6CkHApOPtY!uTjFRoVU{%Jj5ei^m zMPYf(wfh-UvbUJ2c{EUj$SlKlB7lDWOya&o>S0izR#45IN~L;|L9etob?p-`=^Ju$ z8i6bc9?mnY9f;!2Njfk-^LqBM@;B0z$XQWgzQBL%ESFQ{R>G!ncZ*M9RG=bTOVpPxcF&4LEK%aQ>>D9VK(vc5XJnZwIoNuTj$M<`9D#1 zo@AJq=4&Agyw;w5>{EOYubq>V$PT*|sWVYN(eSP{|b-MKB!GGfO=%PoI zCkiz>zCvgfztKEF#C1p$Tc9FCSHl>QP$Q@P;Lxu9u(}$hupOTh-H$^bUETECR!AF! z92rFVn?icB_kry~YgHR0b`=S0aoR7bBOB4Wxh`jH>K__vc~y1!bARiZ&13lO5p$h9 z&B;&_Ph@1|Da~`(VN6U+VIhM##>`g(1FOG4A`|+5B3mF&~usw7 zK^4G<5)EQ}20Z)Ch(qeO0^}u6w8O^Tfe7nLKEYH6sE*90C%00mYiAxYQyRMNi34rwTo*ga~@EyD?5=AV895XT2C zq^Y`|CDQV=j!kYKTsPM!3vOoK3^SG4jb=7J?H^wJOks&ve??=pT;IDc8K@u`) z&^;w%z=RwjXmvb$qQBYxIrm|N^BqOaR{rI$;H?~}w&B8{Y_7p49K#=5i39S?M!7NN zKc1~qw@gE#ow-Xd&KqB)<%iavpWN{qy<2xRVg`NrzZj~gfhIitiwlFzlf!voZO;%r#DC&>`dTKp45zvD>p9 zrFKZC+f8(DR+!ZO>+Mj@n*SV4>8M%jGYCE zKr2fWYs9FxrX3@Mf*}I?jN2=nz)SvZ674U@Y!_e0;8w?$23jZI31!iu5Do#cUkfie zIrRlQ^_5;6y7ANlI7;%OX`+I%$HWe zEwxkF{N7a5Flr_T7C7qkdbrL8=Gx$?Jl}*U{X`{T>v5iR1u)!|i$`gle%f3K^G2R7 zSkKk^+x58PZ0UnfBAp<)m1|F3$60AyLk&5&O@!%5onH$f14~-W>f%>!VMcKwZn%E0 z2e-VwhESfosmP>nDU??o4EoJZu{iL+41Ybc`{Ep^G--4{$mw_-1BPfvJh3j!%&8Uyu?lu@i9vuOcJ_f1;?Wu1>W-bh9dZMOh`&sYwi&yq8`A-ik% zA&63bNlA%CO;(tWZYXxVMF75V5;n6*{vrPn?B@wj`m>L4Cac}G$+u9Qo#l_%j!$=M z&d`e)2eU(V&E+Eea8_hb(BS(c9}G!*Kvt$Je2>G1zGQoHtSD}8lRRIZ$0+*-|72-T znQ}Jkt)F@OEwiB=KlbWJ(w;)c2E_44bEF~!+Nj?@-MOIi9DK;=0IL7HT9DnU8|3=1 z?_Hz!?TS0FbmDq6_0PgzkI#j|?qu~D)=e&-gXR(>2i^2<=(27k6*c(s`r81Z<>1}8 z9z(~Oe1Z{$8yU%m;URD0f!to!1{|$` zLLflL2&iJBQ)QKUCU~F^IZBNiY6nZA^&IU$1eq#?hP6?-n=kQ@M@gz7wz3`-_9sJI zhY0N_U3>^xzy@D|4|Zl#6; zQ-uOJ@)+mg9}E8coI|lhOr>2oClLc?VEnQZ&m<2UK-jO~@gsR&M(<<*(&nmLcdkYG zw#Z)%4#QONn%#(Y9V>b%0GSG3itE1q2;v&a9j(G}nM2J{R*^DL91IGbLarLf8w5(Z z-+EZ*W=!vV@V?#MLt1Zi3vX-1guJU(5%Wo~wq?Y~m% zL<&S1pxISL6P7qo#;weqdIz#X9*dAi>3vj z3F{fC)$xg_S1C}#{Hy|C-R;^?_Av`1Oh^3>$GF2{ms=e9Y(MuWixj}abd<-p+&*LF+6!t8lusc9llWeEof z6D9n4>|)M?A?*Q7H^DGD*>u#m23e(6=h@${O}fBxR)3X-^uA-{1IS&&=YBurT*!D~tEz)z9cxylc9(U`ZZhJYgx=gy;!ya~1}cd1pr#5ReWcwd(pCN+ z*E0Ne6lun9KqSRCmu{gqd3X(+l(iC1`A$vXB_%r^n3EZO8ZylOJ4Buwe6cEVa#dL4 zj8De-eh3k9PU*_uTC?adj6$=mwPmVuFiW@_G*x2R7X+a4(mfQfpx2cRJT2=vjjsA5 znnRPD2J3iJ%Id0pU)Y}h@ts4jf%QBDA2JL2NLP}g9p}}PYVI7^qj#1x4BYt@dF`Yp zlTL~z6q-1Ap-uDi)l+qOhl|Whv13fmTnItB8*8Zo3CHN47H_5QuGJsXFT=Zcir%Kt zLVf`cEgN|hez7T%t;O1hd+fwCeF6K_!^0fYbW7_`G)r46e$Y3&Fe*wj(ow3iM2>urAZjuAMF+ig-3$F);}yqC9?XDk+1~&Wc%Q+n)q9F|1V7k zsbIrMe?dCh+Y1>-V)WM6`l69Lv=lP9K4EdEOqqX!5B1kMe_Bpk(7}E(n%iTCQQ0`V zr_JY_?c!MR#%7IwpRwzfJ5sYm1#sp zML~y?|DRg?O{)Knb_#sohLY5@@PO0wA`HsZ=d(GKH51G9B`dUb0*1~^o`hvfLeduEr z433Fm7{pgTA@}>XhgFXfpFBwXj)bCtf2=p;R?>g1H%k?Z6{N9s$Y>QNwFZM)BkW^5 zBKYGK>#cSQTIerRS7MdA-D98^Wwa?9GJ%VcRedF>09{(mBfI%=4$l_5~z_`glU0l8{ZkF>7iN77z&~ctAC%?TU2qbC2pi~)0?~UGoQ4UkZ z#>B?rwg?^N<%0(pP|zL17mX~fd|-HqCld*lL2x;cI(~Z~UoK5kz4>UIlXd1$aT2ws zmYib>2Rj>h~ec1-~fpMAM|=C@QK3rD#}W>NjKDkm;MBHj)ZY0dPj*Cu@n)G0DHDRvC0 zqWzYln?e;PRX1tTi-C)=H|in9~pjxCKugTQ`36$ z^pF?gD4F2X!uTD@YoZKzIt~hatD44U^LG}y{M7M1$}pS+lcM2*iKM-i46I2S*p5a< zIw}ZFzaK0*cx{hnbA0>KV#HG3|^^Rx@(t>SdFNU^fbzESWPsteX7BNe#AZZ}QEv1;Vy;8uez@yDy8+ zp1)JSb3>U-xl8)^sM^?~Tq=MNp=pk+t(p^19}MjkE(U)LVo2SJl-5KITT=Z~T`(v+ zo@V|<*FBL@iaKFUP^dnED;Mb;E;3RKx#}TGQDZZ9ePVDOkICU-Zq!amevc(6+I3#& zI|IIY3>vs-Wqr*Kw9V{NzhCjMtL=0H`N@i|vv4b)(RzT~$gg}&N6&(cH=R%Dy}O)) zOP+n4OwnCC822r;bcs59DZ8j3hP*`YWsZBNTbWq%tmOWV!740x5>1);;?oZEGi=N0 zQa!6XAA0O~$6~Yvu-XTUe*1oiP1OJ5>@CCEik5KU3KT0)ycCKQC=R8#7m90(JH_3d zAjOIl*WxW&EVvWg-8I2o5I=-fVR#0v$?9DQvpvS^+49nofyps;KmgxHz7S!TGLVF1MHkC@MY2l&iCefM2hEUfuTJu8k1oTQ{R z>*)V|_GJL3qn+!yatjLm#uNSm_nL3di*4Ir;+q5zmHf_{+6*|q4+?)i4_mKmzP!81 z8G0bAKi2GZ*c>8Xq>Wy>e_7*qQzD!v+ogj&PpqZqt?#&@FVY0x>BVK?<&joumCiT! zX>#k`CA)FA8-X+FO=-iC+uiLXb`&|>>v#<9=-Ym~gFJY%PB2tn=R6cs* z{#(Ex2GB*;$Ev-fo=Jk>r{m%?ZE_8DuA=u?LqgVGc73^rVbIcFyAa1>Z}j@MVzE6O z73o`U0eT!Bf?Dc+liQXSmtW7D#J5ByxZHE5!(q3ZyVJ=5E!m!RjdyHjGiUe`E}%MO z#lg*687%5qpVl;QtnS;ra2T`Q!sCt4?Y?u>UDQ#QnwzE#;cru$PsW2y-bbk-ARhvH z{6C5*N0Gp(_n6S$Ua1Q{-bWnthoyRVDBFL5sVPh~@84TwN}^^yW-hA+b3|1rSf($f2;>REQ7>_Q$`hy2yY76&f^dHC#!VS!dBV_l=}#ORT@1bu3coTKhXZP(dr z6ECGf5c}I#^LcIcX;GhF@I%bLH*CJm2b9LH>R)MWPb6vzF|INcP;|<`=kf|F2W}0V zNg*SKG()5G8I)EHN;L{Hreh^)!_%rDUb7E)BDaq~{v5Cyl;9+DTLC9lKFZCN%aZx; z@^*+i$tkP2$A80!iv|eEQ5aeB>*u(2gryfpLI)ePZwBab3d3u3f%SWOkJbBkdFCFc z656$>_fnM%&wVf&kZ-eO$W~-hUh1Y$N2(`~(N-o|f8=MnT@B z_on{I?!zC9oW3w$+PeSxAHh1pCBQfQ!I9vtRBZNP+n_`XDSCaly9p~c^K^A2aGmg* z29vhuI!;1p96_CI&!L?0?hvy-RQdJ5c9#3hQ%M2kLZl=({>;?uk|R$)>u;W&)x~r( zBZio5x`7H`=-d;r{N$lLHd6 zSWR?A-ez$mb(+~%uHVjvJES@~`2$MQN;;A?<|wz|#H`Bs7C^8e$q$vbxSD4?P8^)@ z%>r0gm#$qWfF6}T5b239yNAH}9aj<|-v;MAn56}JBeY*_RM^g!E^+n{Yq=2fxb%3B zX{#qY5m-2dRUyNJ=G=y=+1;J)yQmCAp{yd) zCj6<2zygQQzW)?|6senYg>Z$ZsJj2f((@U(HFDyHDPK{|-DWLu(fK@2TJ=J$u?C6% zcCin0QA2>=<-8|T#&4Ab&)?}XG@!eO-o)XOlU)K=I@Mz^$uOCHS^!|C2ZXZ+QJsj3A;4|q;B-Yj zh&o#|!-&XpTK`O`K1-yfjpb3ix?k0K_;ccIiYyjnV9hJXpGSO5{hT>_Ol|)pgf7~h z#{84WUkb}b9eKBpF-o9W#oOu=nPk5+5Mg93O$(rqR)6>X<97d8hPGYzTvq19PugwF zUamTd0~f|$G(=?#FPH&%2LwH28;oX4sxvXuCbURdO7}NfVO_f;+n#FRn6Wabjm1lgFvUM_a>U5gaK$-Q9pCtJu;NFa07<$ zsIdqc0l+k_BwfZ|fP7UphN9gN@1qD!o6yL4cp#1qjR;0FF7uzN=Y7cJ1 z-ZXtKc%N3=k$Uf5GDeQ(NH;RXe(rfYarCY|TtP!3;&7mWme8U#B1)dbjy!U!rZP(Z zx^Qx{={M!Tj{$E&d~s4mhY0EW88&~N%cI$#5g8{Bbl@f4jTo+VPc`K;Yfr8AQoP!C z?y9U=x5hojO>0Gl@cZ%N1&)X@U9{B&91_-yiTi9p5$9JR+Q30(08~=I^p#P%pTypx zMhy6zuT$lXDY$?@E3Z8pD`6svX}UUmbt(6VVJ!{Qf@9t@3g6U*W>eLarZX2`eW``b zP=RG)_UyOq*VAA^vAdZ2POYfC=EXY^t=w=*!B~4i$)!d=7ng4uGRV$5 z=RPRX6i~R8QZa{oX0sZ)g8&-e7{Wsz+19tXh;da_Y3c}ol|xR z`dD{ZOAP=vaV2RoiZr>gH^pf@L&4@446jSXgk_YG-Sxm2Hls65;abgSo(r(<2z0Z-Je(3`RgfP}gPg zO#6wIf}xB$yQgC5pe%iEt>OE;%&=|K&qlrPx0IkZ5_aBvU2JixZH5!si|2^EF@aLw zr!Pa9&s^t&l9zBnYRE*6INUwz`6Oc&Z6-cQ_!fmoW6E1{Ul&sDE<$#H9k_QGb=Zle z`ht#PSPhus}e(Ik2fv;Y_va84i{yo?_^jra!Bf|?1!=w*Mbptd` zzjAA1%x+R@$OUd@pacn6Al&xv$-(#FMoNU?%hXQYZ%P})hi0RunrH#Y3Co?Hau<~f zyr#XmRR{65$UqRzJ3C$!19mX3V?e}QC&8|lxm155YM498`AEJSGyt{qlC8ReN!)1% zAC-i-POvnMGzygyk9o{xA4^PSOd{7Jh>=)Bg?@781Ey^u=vAh?d-}<*Vv`^R?Hlu3 zMWmwzsC`?B@0{Qe)~rFxK~BXq+wvX6DpBk9F!Mz4a%I_Z^RJ;}M4kWLICczHZTV`Y zaLws!CGv%~{*7bQ@bIaoU|rA`fHtNs`43(8Qii*27}A(8zy;-*hnAT`b0L+8$V=WG z;bd{U;k;oto$k-Hd@Db2==Wy@O9)DwZoWw?#MZ(+0$O z>oziu*&J2d*Lu7TCF5-SG-)smS++nfe6D*>bp(k;*$5%7&(=SAoW~}|>m+>4Ht}-r zIfoKlB7qGH0EyFFZyjKqoZ%CYlLMU0T7bIW4o$EU&2qwTH%%Wa2xRRIL7WcD)5 zD-!vp-`OMB;_6HzzvTC-@Z+Cp%v{L?x0Mo^l=w|D_v{;OQz+)q`w3-k=dh02cWK~8 z6qm`F3{=zz#jt#o`I3pzMZ6zfY6`z*FPM|YpO-vs$Bi>0Ph%U?G5Ag(Hvj5t-qs@W z4%DfE3s&I4%zt0xWM?bAdJ+t`z2<>s-;SqUeBM(k;ig}2;NF9DiR*^c;8`0ocFjka z3vF7bv|2OjMH^&OkruQN{9vpdBB-OHkQ74K8Bd__5qzmmb8$V~ATp%=T*umhW_xky zdobZSjn+-`jvvKhMC#7_Fp6jU-d#6gQAh=~ivLZf8=Vp4`QrAyZZD#HX(n-h`PoFi zv5b*x4&%AzxsD%zT=o>tVsbn_$8Iod+RSl-`5JA7aFK0a9uj@VjpIS6KxR60eGrn9 z=JKUd@9nPyWA`c8kgo>3LTMNr4AJqmZH@mqB6=dRtv&jl z|2z(nSJ4DSoLCi>CL=if%;EPZ`9WZ4#+EI1-eB(BrQo8qR~Zbgt|Isg-v zRFtO;e#l2Hhvp#2r{Fx`_u5tIx5^h0(hmUocg`T9&xHuGgRK7bTy$nBb&H_q`uG58 z;AJK;jv# z=st!KCuqf@d0{-nw#xG_mYD1H^DZhh%;bG&LPSV9yPNa<#X|j1kcMUTWN-4SsT+0# z3!?ee%emC8zki}99)lQ$+2OdTbdkRfFY>&oF4K`%AHG96%9qD=!5fizM6NXBZe#>? zwetP93^CbMx4LeXs1Yi_CKF+Lg42@QvhKSI?l4N9ADplj#uRDL^Re)-08<*x+p*%F zlq~|sO&@=wJho|K^Z18YxDKAbhgo#8Id;MsaWq7QET3>`3464k9Dr22EP3>kit=8S1{vgrO{9Kq`llc51mYhRFgYqVRX|l zW*cBDXb4Y0Y}FlosmX$Q9LDTDr|5q2`O12)RIEr}0&caq9|bzywN1o6o{jSQqgj7L z`GFEC|4VWg3GmedSABT|8{L?S2h&mc2MzlC$rL;rvr7Vo^@9Wl*NJ8tz9GIi4Ry6- zw!D@XLn;TzAF;BI^Q}B_JL&S_q?b+vmQM85tMBICM79nc<+;2GF;Kgikz~{d-sAA! zH@`ISCXQ*mT8r&PIh^EM8|wA1ZNm3x8ZKD%QkC>K{%?grX(Ko!xD@plfQqGKFm$n9 zkX3%RYJZiKAjaKJ(+T-#(Lh-b?a9{B=dBfD1r1u1_ZuwNeYWK%0jIvy^NNDkH3Ds} z)>f;u+1LKqyk5~g46cLrCorh4=)`-W`@F)jN#Z|wZtyjgUZRs12S1*e{#iCu4~Vj9 z;I`L%YMKq$P^&;}c&tC3KSLMc0$^517qn`$+n8lR5_vv*p>pFQ+c)6oberg<_+m+J z*5N$skew@uMc+4(s!qab9Ab7GWzOcFoFMtNl<_Pyl4ahfy^eqGA;jpbE_83UJ^UIv zP(#KCwV%HGebi#iVa<9=u~HGP9(-pl@j{qcz`l)pw8!M$zZq#vX^2mRP7v(><)grk zcJ&k&nP07)o)ehOZGH7;Z0U|vv}3$FZ(T5ss~zN+#~O=Y;OgK*QQ0dvVYmdY5Pc3u z#1JDZ%iJE>SbOm_5AFEoF@!&BAar))mw21qcWb-unnJEsjbs|sB`TB%kGm8jM0ZL`1TP<`@ zaCyJStuO-h`1M1r%!y2cm1H66YWwDXjvxE*M+MiTOb)Tq?_GvTx;{+PYSXR@2Q04R z;(;#&wGzw3AY~!Ax~I5;QdCGHNK_yx>KHN4%)TmPQz&A0sC?tM$)RWlK``&(I9jIx z-mP=DVXrOl+w{eI$bq%$%!K-i+$f;yXh6r?Fy);t6O|`f-)vkgzf=ckXD#7n5}Owz z)w-!Rt~D&t-8>3b;tO>2g0UCW8#PfyY~Kj3Ndz68aCXCioLgHhD+T;5?6e2PBZVkU zF(%jHmf|V*O{^cUipi{cd8yDdr<3oRxv#AKn%X9bMc@)IkRT)?(Mh;L0Achl$%c&5 zuF#^Z7vpv&UdT`kXFF#*B#}`N4w4AmC!>*e;97ZtE73=MwkjMN0ga$QZQ%B&*j_~S z|Iab1|4%?Rfa>oDf4}|y9d+wtd98;Wwx7x;6#w*pim;U%1FGi9+<~y z9R;%RV~ky%|M|txfpeJDTGwoK$-p2>6olVHW9IFt&IwdsK{$Z=LL7<5RVKCz)`>WA1PmJ z#!%Z{G_g_Ywq(|L?g4G~66NkDcHGYyvxtwIl(V&P$1TC>rz z5s_c8kA*@nzZ#k3a3+7*el0iJ&i0EOud4y4bD#0wnoF6qtViJTg#qvV51!=J)ja7% zVD@UDY-u{o3KAJzd#B@axPE8SQt9;6%3WN1{3GmeEGf?Oj62KsEYh*Nj4#y-CwF?e*iW@M#KS5Cv}^Yf)jZ8~r|7 zv7Jlu!H~<|6Poz(Ckoz*zITElBV+;8QTJo#H*Vo#N+p$^PM64O@qdlZ@P!bSlOwNGHsHQDc1lsHbR2&Uvs*Y#sc==XDxq~R zagliS6QC|tkW_ax@zd!{6G}#a#<)lo;d8tNB6Z6!o6~D@9Q&)MroY?cmXc%dOQbDF zxv4GgTt<#M05$L41ace*Y)1u|y~kfr-n_TM8}EOcqf<`-TirIzxy)?apNJ;niB0xU z<-|k!g>?|J6T;rb7o~BmHD9xo0?@x%ciGTf%zQB}U(XbAcpk6NX?_tSAoEdBANYvD%&txg6&KS#uZ71hB1nN>w zt3Qri?$ec?uye~(6S{abc%?yB87z$(2cxxSU&PJ;3q2?Iec@Fkil1mn!8_3(AtWvXZV#Uh2R;`R9Y|Ga#p~Nfxyy($cgQ6F<+-d((}uTbeRP)b z+~Ts@Qt?o0FI<3mqkit`jQtQi-%e^>SDM*Xm_S}&b<=Esu9_JDwyWm1vC5-X)WGqC z88AkLWa2WIJi?7x_xix0ndDXWAy$h)dQF<<*+#cb1G9-u;WmyUt~L|E!>BI987RY! zeKYRwoKC9q2F2r!w-GDnY}=^6H<}hA$S_brmYXMpnlhFC!w1C8m++QZP;ty+ReCSX zP(X-_ChsY!prS7NIb>I$4rhl$=(p6JzAdX>{e#u}3783p3Dl_00ac6dVdo#5HhONH z^6h1u_I##wB9Uu#>k9C_!Z|*F0xYvkDXu8I8Yf+%zi0o<)sPGlW~5N$R3zPz;lB

    qPbm67I>;lO37giIc7{`4w+ND6OVHBGLRT-5k9Ot+*g;# zDGBJGLS8vpv;g~hFx}Rb9wC)h5BDnjh!o9wgvd6%2TD(Fg_w8Q0_VzCb!2P?*iIZ( zEot#e=Z84Y=$Q@Gfn-jGpKQkzk}+3)3m)kpYc6W0p63J{?1X&ut$LHr;V<^Q5unn^ zx+nkY{#9>LN4jLj*2zb_amUjgFB8p*aNUpc;X-pUl-Jm`|1}MJJAJa@!3Sy{{)bq2 zcNb&BgU^l!qqp|&Ot4Qcqc2z4{&dS=&k7pi+$zaf!n^5*fg?Qp}jLRartLpA4v zqg{QiF-KNT$bx~_<$@=Z`+TX|h{l@ikvDUZ9GBzl&6W}+dxaUWF3n(HD?9MquCrdu z=7}z8;mVWgNUl-qSA|JQi0#~5w$5sL z(i=qMyJs8cu#did163HtZ}coe{gpB_)H=k^(u%^AE7mKVxYcNvT+x`bcirKmYm3!D zZJ*?cG>-cdr71q^N%x7dq>D3$9zg&9%&}lhS85nbDS9QH;5~?b=iO0Wncu!t&BR)8 zW2Lj;G6VU|$C3R?hR@Y5t8}%sXvFKuS z2KHq598gAji<&`u@q(^uw{>8cd@WY6zOMni&jH05l+;Pk;K}48BfFsv7W)OmnZkumRn+u~~A^6Z-(sPu&--*0R&G14`BaX*_qi zlxuXO?NP=#(xNs!%shkFna%#!O#rc}9b^G`*@`uS2*zl6TIK5UcqgL=lSZL@)lbq_ z)N{C{h%G*_SoAYs45F#Kz10Xv6NBJZZ`*jT1bya{(@g~QXJJ|x5f$HIYQ`_0d1H)U z&FJ$&MrPq8#$z4g1&p z#q+r1kk!nNd@Ppx0H3!lY%HI)C@?v*Br-plt?wYnXR@Ym3(iZ~s%*JLgE>pxV0ggQ+ zg`&MAki6oCEeO30bP4)gB*Z~;(41C&^y5Cal^q3?$a{ZN5M&p#`IE9D+$I2x@^zXm zn*QkdYQpzF$kh!b0Pw)!PZ#q2?#=62nV~N){9|-W*36F6#FxZ&(dk00^sum5aeSYB;u~lx?X_#2H)5+ezF(Izmvy-y%ew}! zb9`Z?y3OAEPaABDao=1m22~0ch$gUh0Cv@pW4M+j?8lRb7-3tPVX#wHyi}V_V#w0g zSlD`)3}Q`Dj-lOspn_F30^G~mvhsS4O!ZHuFD1vhPMb|Z=?BhW#Wn`<~1fR}>EPg(sfidCiQZe(5TAOshP1mMZ|#$ytou8Wri1mhjXJ1Mf4!)mW*R zBl%X?7RFLKi1|&%B9}RIFnzIUeWo_Iz`uku11PBzY$j3}DMfnAd zD}rBX2*=q782An>d1Zy@jx8mp1U~Zya@EMP5~$SLN$`TnB9j@c{3;`$(^SI|dGsBwsvW z)fY$}L6B4iEKT#BI%W~JSCQ0nfY^BF)9r$+_J zgu~a$_`*G({G~=52r*c!5It9FSyWv+Af`8YbmE5zbfzcnMdDMEwc>vQrx!>fuYdsc z&7cFP%#|-~x9XLw2;XRXTU=ViL?{-jw z)?UU_Z}j5ULL3SyPZ=ko6e`oaStLzI8_@J3r)4`X&}sAgVZf^Dr59A~PUwGwuovry z8jwN(%RRC0(tE>Bak1G?xcRhs4npugkMCoAKOnuw^k9k&brR*~ovX{}AJvOvKy#=p zTY8a8Y81?X<*;VId8tZ*E2&3VZuH)4by%!iWbe2mQ6q8zKVM7Z_)Cu%W35&0OP9Zq z8wKhyVi}dH>jb3RAp3oP0InF!L4PkvoK+>+#m5g>vag9fnR9*sVSJJnG>3Uxhw#E= zV*{r7#s`LYGqpDs9YwSbH+M*fkw(f4lSTH_5_Oy^9p|%seu5oIhb|zyBx7b3r#&oz?#?|vGx-vZ7z)@l8sZj!wq-U?}jG>VbFb-YLgAH z;b!-(6=?~fo~kJ|V+1c0+PcEia4kl-r(_1%+ck&R6o2OZ7rVa5F=&8)gh{K}&Qzn| z#SkIYYsrC+K4ejD6HXb{sD6sA@HhMwjthpDWtMS@w0oWnVdC);R@Uea;7=6}aZV>t zTf0>0d4A8=k!{trv1(y?wT1{a9$+<+h#oRLPeznblh?D0E_j)c7V6~0AN_;)-H2iP zIa0aSC|thA9-#mmixvKX+WNAYb8I3%R|GmZoFKiyZzjBLQeIg_gp&l!_$UWdbQ zH6(x8*mJoG*G8qlwY0wxHmZLUI#hno_M*XobPLl59;dukdf-^@2qtYyBGl0|Fk`cc zTLPibW7j>_V`sLx!|E+Lw^f!t)-#J-+g0w{T3~XjW$PDM#oCHi(Xw9s~_z|xuIuSQc*Tdk7sOA&k8@X_4MH3V%lz< z9#cF?84Lf%=>1xUUzO=WB_~ftPOy>8{}BiN6s3`WIfF?w>CLVPb_t(RPy{h$XI017 zC9r~3(A?*y-gJeIhU5t+>48NmQ*v3{X=};o9MX&%XDty>)}jy4!q(bEU8fKkG7S@0ubBVEY&%zAu6hAUmzL$Vhu*@ zQi2gA>I@@_V7lJ^A#~gQEa6UaW6u?K-|+9EaKOo>mlpf>^*F}lb0m*B98@F+2L~b+ zooFfQ?Zr|8L>aIsl5 zi6Aqyd+*sTfrIy*-W80rpCM5)dMnjQvRFy@s`YO3JMn)4#nUj7wI1*$5l0g$3NPz8 zV7?ZlO^hR&a(*+vG5c|dGJvu2Ch11#ryz;*)Nh+o*0=l8Ku7TVrP7cv&q(O+YBhXe z$Ll)mrFWE_>k*3SwRV>Z1E5T!l0WuQPZBQVaZJ7V=7kuo02vIi$%u=#B!f;_fUIlY zZEA1h-48dR<}aT|*D5#SMWBe*NT$l|>({xI#3l=@G+al^SXg+WB$H%#UG84iGIA(9 zo*51J`;Ai`_Eh5*UeT75Uv{!>GLxgvTUdlWkFKhJDmSXjRoOQ(|Hd^ofM!olu8-z= z@6I_|l_W61PBTl;c1*TBHnZ;if|jbd^Jug?K$+VA9#j!7s(HghNSK3?Su%52-8PWPXyy|FAHntFoMk@B4k(dv9ff2hOxWvjs{acMa1{k}-xzcOa(1?5y}Cf#E8nnD zEzWo1&w5xSbCT4WU&4VPwWih>d8x)DZj~X}ahf-IHsa_0LzrQ9fF5_6byzoV9_fts6KA3AjF*+m;GW2S-V>nZO(8aJ^CEa7B!<1Fr&xl zGYZ?xIjORrip)p%{$|vOVE6vqo+(-_&R3w3yZPoK5;PBG1CT zu^D#@)W#+CKB5v=oW-ad)eAU_qC9Yu|JcbKkvcaM>AR?4rA;tBUrc*TidsdR@M0&` zIA6k!C;gzuO=8cji26XRID(oPZ;2951*o{eYEp6EI?4u+CwS`0nS&qo@ZunL+e=mJyjY9CPWUDoit&D2 zNtG(>`P^Xcy`nroN9UJCKwsP9?mPlz!$+=u+3}mA+GU%*zV{io1u_$K0Nk#=Rvs$> zRjS|cqsm||ra7oPso;OUs2UEedg)#BLC>z*um@g4KJMoLRlDVZ4t%rf1dymOBAnbG z_Q($DQV~qzk)c8j-2Eukl5jCD{m1`33;_%>l;)f;(A`aJhG*`H2hmXyrDQb0Y?z48aq$v4^V|^gH?2wZse^N2F zR<(E^5}#W3-6?*_;TC||e%@aEcJMZ&`8k~IgAbdrV_OYX6DQG+qdlZ|XY%fVR|1KT zgt6|-Q99fn8#UtVxIBqld=ZanGIr=Kd*RjN%lG=9AP`7Q^S9x0mEr!3JF5NVK0c*8 zmf2Y&eOkX6lAVtB=GxcGFZYx$@!st|Qn(iBJx`7$Y&E6bhJ4d)#yPG1#&MoUGZa+q zdZ@M46+_#}{kUY04!&mkarC!(Q^ly$pwWpUg~!wegeT6t!HSa1H#87%`@OA5ol zht=JTa&3{oVRQh0`YodwBo*0|TqN)LSM0=+FBg=b1X`hTC~+duZ*O6F|FJ2k4Yloo zr4=|&kbF*xQhKrdxb{0g6BU6|FL|&D=lzMV@58lE`Mw5oqsopC1>nY>CtSlK=p@hHk!x$U8Tp#`vut`2;rq); zi%2ZJWBtm@uRBJ~*o0zNPX1c-*Q6q^l?N$%(JZ!B0a#nm%9|P=|HBosd5_lZijDxz z%bbnqIJA|XLfel0M#s>VyxXd9 zE>7+$cmC3S4~dPEpErf$KECjo6pc#Ab>&Byw)6YYsk2}9ZWz~!PKXk`jbvz-g5BdJ z0-KDkcWFZhCu`C5ABl$?V|2w+p23R1+VyG?>#ss-{Rv}$U#^65D#}R(SZ1FaUuki9 zlYsBOnd+_}knr8Uqhh^R+vgJ39U|fX715`zL)wM<@l&G^{4!;+vP;HX%FM|SIFtwN zr9NTDs+-EeVqxMgG6SS=8VZ6^vVV3aZ>S{iDL+`0pS`a&dsm5MFe(j!mS_y1g1so- zeM-Jz{UCs?h{T))X}!?>ed*a+Rxr8>p!*r`Fr!bZ)~&mgUO*6aOD^|6Q;dK(_^06K z8Wmq2{6(8wYx_G3TK?fsi6;1UOZ)GrgnLC$o0$2CZ_=$f`jUnpgnZO39ve(DV_EhNtOjr$>mNf5B{HT6O*zmP$W)w&S#sfj~ z{WwVOE>VD8A`ZmV$ZfUEKYK_&?I*07*QKJH(7b?Rf?oNZsGirNp#v3=CWP#H$@|w< zw$u(UU8i`c@B5tpISGWJnx?paCU^Omk4p_peH^YmYp==K`m-M-tb;rujH2x6=laeE z8&zd3%{t`~2*1Jh*==$BTAGS!ho#lFCGfcn@#dpn$o&-;F<-c&U-#uaon=*fmdM!6 zTQC^p+aofPD3b{TWACer08d?nF^xUmZE3rA=v>}zFK9*=UkSz55P6md^l==Zu?Sgz z5W?sRh#(w|6-?0|31-^y6}X*pwktH;@?qgsNxR2)%B0!)hN4Q==yqHNlt-o9gtVmj z@O+jsNdN1|J<=hKTq;n({g=y?C>9@n0$QkhPrOSOaE_-li?A}lE&K34c_Iy_9=`tq z3~0nda&G3thRNdKk*MdLi~f;S1cjHHy687+g*d~1w?>#}xP+b=oDd&>m?vS@Xw7@I zjb<-Pm@ktgi@<`y_eJJqR}HEs@UjMF!tgTVngg>wvHp00D7&w_D!@Tgct70u{nAU} zO|F)&@84~0DTJLhxQ zLfzYIM?91M`pZ6x1Hrm<#SK#VHIy!s`#R2wj(LWUKo^$1MKZ9&!i4Ll3OZvhcv})8 zSQpSCX86?6hfV7Ll_r?muVK%Vkuq!4^$E^vmPg$&uAEphbJZWe2xb?b#M|`$m*t36 z^n1v1n3qFNa47ADqF%HlB9d0W0m}ZyEkm}-`%Kofth39h8n&Y|W&On`82hFfy($~D zTeKIzOzyTYqYWOjgPk8r!~#YlODbV2?RLy@F5D}5iSar9BdMpMp|F>J-6>0-ltOq`%!GM z9gN6)1bPF|Tc?JL)bF|xu+naUg&J!n%| zyE1(c-XAQEsuV?ps!GpGkaBf&-YZdcRXEPwH>ms_mk=Ai+>FN%t0H(2=u}IOS$|$H z1Ha?G^qR6>&d=pILBM$`-|+_47an~kTeg8KHc6v}C~QWB-GW3C<-=FN&+18lH^1fd z7Dg_HlHJ4=e-xe1t|AE5YHp~t3t#DPJ;54E#H*VlUL9gzOWZ;)!`7VimoTDK+y=;| z)}{tbIP+Hnl)ES~m|xe@&}l`|^ex6QZ6T{Tt@062dwW^t1)bdCcl|Jqrx+&BE zcYN#?ksfh=TE5A&%90-b$5hMJet7sS&vt+O*=+=$JSLHl0nqg3 zn^NK)zfbnVTWdg>r4Jpe^j>wVr@c_Qge26QlNgE}$Cg!Nt*Hf93^NR1Y8Y=dF{&9< zCTJ3YN$>gk1i43K9(a+j9*LH!z`?_0+a1TZ+J*15v9|2qUL)io&0EoF=5{1jPJI^UV2Jd^Q~TuauGy(2_cbE z>0=zV1hwNs1F8sDyW72H9=bc58F+{$?3Z9f#1-ob`tPg5*_2ztj{Iq(macCaW;t#3 z+``tO8+C;mW_%5O5JD2nKEkSaK8gG}fp=>Q(HBaGEHcGcJ8XWFVGRWHCDJaq zL4175ODw{b^GqtE4*FeG&v~o>!-CHcP9-wFIYJUcHc^_WGy*OElw6hP8*y|cG@HgS z#d6ahTTZ%1d`+gt@q>@5Gy-dx?D!uA%c^3_j z8?1^XC|!9=$UDfNtk=fnqF!Ii_e7`dfn7Az-c^gf;(L*UY?m>-B6s+lF_A5)Yih$a z(Fx1`Bycr${bzNgvw_p_R)0n_MZ^!hzJT<&ef8j?N&VQSnK{!V&Txr8)Tu`phL~RY z+M)OA+4iSjatv`2odTY2x3>&%wMYrvBbS%L$}(vE?y^{tDefvHTVhK(K>*2`1$^N< zJ&VKa@gct>)2SZbvD6a`kwovC5w4sKnB;8PXumUzJS7IJrrD#y>|A40kW3%FIn!6jB(1JU@?|lvC+dyag1{&*kE)seq@aZWT>-tXwcRH7|ZbHFEwR|dL zSBwJ~I{WY7?ys_|wGh^^9^{a97S8+_9ycCK#1u`A2OTTf?K-BELT)*1cBNjs)(DQ-+dpR>hD$y<-E0MP<$5IAMy~E z9di&#(X#bnb~qKmq&lRb4H$K~eUZ(v;LO#WJv_TA!%o zLNySVX5S?b**OurXn`V3)2yc;^7hJHL?pVXtMfIsiu@1({dGFCDZ&^C+K3bzErH*~ z7_nI`R1c6YZ}e`lsE$ciTp#`~)e$t*Aa zlst7)LjDuf9ud^Bj)L^39TZ3fvI+DDsigsLH5+ved{KUN_63_p-tNtImBd-!@r~R( z`55}0ET2*OJC8tz;qmZcd{2;}1%mVcj<$gJ@PycZX?))O~~x>mzG3rn+qr(K@PFgo5+Rti~Y<}oI>BJ57K6)zsfaLQvMA(xG5f> zP)betDPwz{i8Cz8&C5>my9Gax)=a3W+$=G-qoJ{QUS{0ObfMuQM|$1FZ91yf345B1 z{S)J+n3}ywPngZU5*=gNdRg55uf#=ZGNiE?qJ2cz8-bC2z+|0H^gpc=Axj+5GmD#P3YU}ij^;pG2Cjvk^ubFwL z<8%bEmgqkv-p3;+^j7!46BES9?#<4T7_oYWFJXc+71RhCx&c1X;HG?WBl~hz(_)z_ z^2s@)XWt-+?T}w{re&QQO)&`)v#*~RrOIYUliM%Q(?bVI5TXK(LaM_Rw)OpMqYEH@ zTa^J7p;?HoJ(ZbXC9icUZ)Sg7&YBR?u_#&y6;}pBhmu3P50-1YTJQ9bd1-$!+wA0( ztvsgkYm|J4!Eud4W-zdL^6Q4HN%)0-lz+iIXrQfu=DB)0GF+$i^l5LW5bJ|BKp|hj z+Ioa8hQ6azY-j!WffU<|E)K9&`|X|@fN!ZeoF&);lpOV+puA`!?(5}-G#2H=k0^|4NFE?&~SWXyl#w^I)e0(QTnJ%My>;PfQsLYhQ3q ztAgL~##=OSPdt5Qda4e+$7=ad{K9Q&LYHFFH|8O6hTu}7XJ$bQt-bm`Q*lmwCs--J zRo6L}?rH(0fHD2m--ktE7ij~;zu0GFbGiH0M&#rhFR z$sZ-|RP3Rv#=cBsaL%<%WGOOOekiI$=v=SW&SDiE^#|V?lWO>z7ZWbMf1}Uh=v2`y zpD!(8#JBuDuNPV>Fw^=?sNa}BY5d?@rykjJfLzZlzesbDP5z^zr|8;#HuLK%vt?wZ z?=D50+Ql(q)`+s+P)lkTEKBxMvD*iV4nffABM9S}84zcewhhD(bBM64AWhzj>*$oa z8K?r3d6JO)y&9AB>|fsFff3ZRflphXs(r6*ZwO+TQ?qgdH5XGwi8d*W_6cRTLolCQ~S? z_m{??&*o^9OXaQ#)Sy=T$X5UR;eXWMt3m+dC~R@6Gj&9(R;wOEl~BIOh2;ZQYQ^J< zM`SZnn)}6;^pXkqj=*>Jh^sl?D3nUj^o0pUoO7%974{>x^qO$7+kMpKdYY! zTkSY^IQ)jjexz(Rd#sxP5Qb^}a~f2rSv??57D9Qr8iyyw+&A;QuGCDgU&1{Q>*1KG zUn^~6wOGh$S(uX{b61W5T5y;S6Tw8&d64O#S_owjyf{XoKHlCcJ^&mEVCWhJR-Kn zIH&rm@|Aiz_ue5SGMfTz*{_)AkUf$=*?l|gT@05EpI~!SkiCGQBR=_>E$k}T)#dtS z*D?0vSi60#kNemc7>;wxaqnw%TqfZI>x=px!kVA#cpvXPgLf5_+e-z>E9%F)@E9GK9p>`y_K(foQlK3J_bj)Vgt zfx5I--?GV3&zpoCW~(}Lu}Z=3|9X3G$tnRlx6<{oP#C6Ub_h?mgm?{kCykJRHHL7S z3T0dM&?Jrb-@OA;0f3JsTO_%l!RnKEUEiPHOZ{2Q!7?+QxV9XOw(emd=zUiiXppIV zerel7df)Z_WM@fK>FB`@^5)t$=wGIT`3nzvCZlu~CVl3#D+79U_#^MgHWEQv3s0Q} z^efN6WVQAY(@Uv?yXuYlyPren5YM$RHERS4pBm>=7Caa?WK zAz&^0X~t-J(53{vO$Xc!1M2L=)R?q{zJ=>(4WHN1cV7MJlg%>cYS3kYcCNG;<$h zX^tcJJDSi~a-$z&mdxN+!GFaGmNU3^)`MNO>s^;#BBWjlZ%k}3&?&!f9Pinr{Jgo@ z*KfmJO6z*WwQ^&)2wTT~S&UuFfK_Forj7^hl`(%B$!g(rt;)>(OP&h6_#uQTMH<)O z$0U+2xhk^gGj2igxOzsF_6eg{*S!g9t;FarbN#}TiFcIL{Kf@{i_$olJJ zQ4$oMwnJ%J@906VMviBnDh<6eH8oXHd1v}dwy~wu%Ve;i-tlS9WjK1qrtt*XNCG)A z4Y$KF8U8DCTT3w?`PodWbW}T1_S-&I8Qyh^>hzOga>+!d-$*uL56U}epZbKdZDrvp~kNAo$Dso#A0eR9!b zql2%uwXymdVJ}`8KK!0dgU1>SMETf9e0U-z5i}Z|6VCMNGoHgEJ-ux?Ia-%SwLzF& zw2004{lZ|n3d4IP)<9GUZ~EIm5CxhFvc7D^^p8N1-zGF0& zYCgwHFTUfp(BuTLqN`~cL(6nT`W$&{(qE=>1L6bbpO!vZdgVC2?87{n0XO(-bq?h0 zUHOR3`vKd7;Qjl%+Cyjq#Pl0)k3UhjX-b%g9KN=4vE*U}VfB#nJdpT>C? z9bZ~+FHR& zCTDNDhZXsqb{8?BN%QG`O(%;RHcf%Z~6Cf^L>vsaf~~o9_Z$N z=vh#J{q2=3BWSbWkuk8iy)EbMi(@3nlB-u^$sp#wH(fG&ez@9W=B%&(B3h?+M`-KI zVYvj}(j3iy(#7AigNl&t4PEp9#N9xNh5uZcdx7SGwMWptffx>6+mm#H52&ujSss13 ziK|KAm+1dK7fq}9Jp~Ls$2xihnsli&g*OL0Jz$q#EPef@4aqN{cOtmE7EVJUQ>+qz zJJ$C|oApKA;S^}hABYP3oz(viUJsMlZy^Lu4TgGs3Fi&~L4kA`1G?tC)9x;H*^`r= z-oEvnu;HPhg?fiY7#Qt)b2*&EC;Q}UZhrpJg?L!D8>q^ArD54&@fC0PTTH(EJ7azv z10KaTCU2?mNJ{kwu^B=uTu^SjXLnRidgG<~L|yZ&Qc@(zVsm=Rzn(1KsHWr(y`6+f z%~w3uQCdf2GMG&joIh)Jq`+I_!>K*=u~0r(A5Hm!d}GBgtX+8R;rgU@#v1M3SdeDy z^k@;5*$ERkZI-e4`9!-j=mn+Dv#i@(<9x&Q{b_Ou_4dt8j-}Lmxp1mJKkyZ{w}CGZ@d7ER~?jPfJq?Y%1xV@pkPaoq3V zT~Xq1-vLkOlJc*&q%`J{Wna*@E0ss!VR$kP%HbS4`(qm=PIz1ReZ} zHhR3;_ocPKs#AROfh)g7ixB@v|J#@QSc%73;*7qI*qMMnXBDEhH|$23kvi3d%nE32 zeHh}BY3-=J{I`#5bq%d zu~~%mRArn|h0F5GQX9;HdnZWQJ^SGdu6x2!sVm)YwAK&{&2A|$?7o5Vp4GRXL!-WS zyiUZmah}4Do{yTLADQC_cYjcT54znb6frqk#JmU5Oi4J z(yPv`taL&lUX(F`v!d-2iM6MY4i`obvHBDH#- zcV1CBI_wk1(rJ~z?34v(cU!dJ=iMF6m{wWde^lG$OS|#O&n@*wM2*TU_H614gTcFlZ(+-rVDP|`1HMRx zUy+&Xj^Z(D`fO==ba5TUAa=GlAA7rr5oOZS(z3F$*4pDexZf*b>z+4-?=V}Yzda3j z`g98L0Dd(OPo*jxyhr-Lr6b_)!Q>VH?-v6bX3appJW>)K6Q5UQGL41{9UQge>voUR zmFzC6TF!(pgvl ze0gXc&pDB>U_RN$)AkW&)mqB@DI@O^ENu}y>ZX{;FJO{rm`q(i>JuD*-Dlf*J$#Qt z=7TEs+l8xr4o$T*a z9wz^zEU$?1W6 zf2opO%si8192znXIaKxVYZGLHCHCmNK5${}4@ta(vDT`cT^eT)H&w7|CA<1Y4f_uU zX*Bls$SGXVW*Lvn)I=BPJgydxY~eEN`#jQ}9=h<0#vjaS-&=+++-8B13&*D)`*Zto zl&bHfj*uFdiIl&{m;H}aJr3a#gw|P{A2Dk5C{7QG?>b=>s}R@dj#RAS<*IkR7Fw&4 zXB)wXuYF$iD)!pt&|<6uX7}U*HyaiD)&1zwxzpUcLr=8YV;1w7Z@X^?Me0z_u!}(g zS?xL1xgYBanA7aybQGrMVQq1S4Lx*&%U#^lLOT4InXY3t3d#77x}FG{A11pboaX7f zFno(S%-UovQ^EW;`|}44fz6vjN?C2nRZ%xY%?y~l?zf&g^Y2cW&3aT=*wN`}UZj8D zDsXSE3UhL6UB+~p-Y^&HH(9<^*nfb#`-NO5m)ihCN>sae-by8ZMQgKZx3nf&bun({ zT5^Rvb6$KH>BbZW$(3>6hZt-!S?OA<0_|O?NQs%lb zS3%4fzngCCGCVwBqgq{@Rr6~9K(pjR8vB(G-*crwu8`H15g{%?mYs$1brOun;+Msq zu}-f%XA&s?ow>k&tN=rP|5^d`zE|AGX#gqwSg~1TlD9Q^2f3|YYVR?BUMAJx)!9u9 z8jM?JzW#rSy?X{aQ2!HpFVFG+LE@dXh-|uAs2ap@U6qFSbf@D#i8n(fchf31gB+4E zDEDvWl{;!{%Nhc?yT10;Z^5*kq~_M2YW2Ai10lzByi845@*HzW@QYHxoL{0tdLw~v zGq_AhD!MCewh)-|rwIHp-oi7v{~G~kD;k7$DU#pkrZB0+RMX0QHs(>I<(JB7k$?!f&Ihc$??u4)1fPzYxO;}z<{YdX7!V%D#4P5oqSr;ZYlT6 z1sE}W|2L!CLWSfe!#q_)fVlyr@ACF#*kZ@;#;To9ceJw9wl+5l))BAS*tBky?f}fS zwNUFU@CksoLVs0t4bw`>X8Fv~;w_%d!m(YVIcbT^TTYGWCYRtd+vUJ*j)k>hmNZJ~ z`4>_}@(bcEeA@zOD%G!zEzdk$bS6#~(~C~OU;S@Y`F4A!K`esV$P!+Hh&QqGS~tJT zYeNIxS12io5z*JIXq0O^6$nq%iP>ECZKpP;2LmnYhjRDZi*yEUxzYV!P^0_rQhcFi z{adZv$7 zY=xu_mp{WnotrA1mbqtO->Yta(!fu@e6PB4n!?_ulvcK`HtVh?)AgksnpNB2Hjdr2 zfLbI|>G*xD-{Dqbd+g)?-%WBvWKfGhxC5tS{IcaqF_dGE<8M8} zTAd3(|AloTJ1?(J3AV%ITAjD=-)D-r2H$d0+2Q*5-g?H1kTMxln@mgHDhwuEdYSy+ zc4T>hYZ=e2(yxN$bZ6-YZS>@B-T~$i{)xrYj2%>@Qz-q~#pa%9%uG(S z#cUUEW_8OXq@FD|5o7ERzs05UokS$LtIzlqWlt`req|ARRj2qh->X%1=>281t3 z$f;V23vn3jYNwZ;ut^2@V~bOCm7t@Q#@kEMqLzb+`@2OU@vw7tNl-d$dU^H(yU*nO zAgzm^;Zu7}k> z2F5wxiLf;aJ7=aY`hEV|N-*V~TKqFHAujGwUi#gj=PF$Ma{1eb^7F(bR;^CfxLi3L%$Z3fLOR3TL^ z_NJMhz@Wg@Kyym_tbVy467IR+khiYGR<`{ZvR~Kvz;)L>wT;QZgYQ_ z-441lX!^AI`c;95&Fv;@hSvwV&M>t6ZwvWAw4QXye(N z>HdH%c(I{bb*YyK`Aoxt;)?oeZGg1Gby){;%rc_|FOc@3w*EhR&)st)Z-CN9O9t^fA4oR3w($uepp|3MzdR4h@yRS(dR*!=NO=HEr%?Nhbg1Jbm z9EBzQa`~(Y{3smOZTl;P zG1HO2SfXLJ_NQwaRWB3DRE(#Z!2bHQ=m~JN;JT{|&$HR98FUIDQ{|Z@Lkm9kE&W>q z#Z{7!Tem-bB-#Ki*U$PdPGJi{EZ25=+WJ~BIGkEK18o1+d;$V&8Oij;p6#t?!K4CO zjn)^D9Osb_{*20xr8HzeNjF2dA ztFay2YisD;DWgPj$=Bk>loyid5)m7VZIjY#KG?w?YFHs$DqtYPzEPEZ_AfLWcW;`G ze%k@kexWC1f0}0C!Fl34p{EkJVUPYJhc;ru`-HJ;6iM#Ud^&iDc}!V@jJ&fud21G6 zI#o=ntkBGBWiP$~;W!wQuCN%9g4q5VB*<;~xrYgY`!uMzS2l9LZY0c?9qlm+qw2j? zNIeTTM5^BF&(lvGPz5s8Tz5nSY5j*g60RpO2P$H{iI&;Z3Kb0!#Z8t8OO19#FP zyMZ(b5Yn5=j$Fmd#H^nOR!Yted(sEw$jihcuZhB-A(NkCzGsWTQg+<5$#?xXv} zg?H3VpvamO|KU_1y48LPk9@@g)3WJi44Tg25cO_Y^z5b=ag%FH^Ga|0bQ*GE(-HW$ z(C)=_goNbevc`p}#m)$7NI`73#&$O0zuQ=?3U<0jKI49u$z3=p(j8IbAeD=?+FEw$ zyp%{h8_}F#fjp0)TErJh4v%9pTTF?`x^gW(s`w$^=CO9S@QRZTO80U=;-$f0k!{VA z{-94aSm+8^G8@RUpETYm=KIQ7)$o*tKCJI_jmX-n6eG0y*Qn%!b|lDz;A4q#GW9%- zlC&E1qH4^0W2i?;S;!rmI1Gz4-QkYWelz26jzPjQaAe}asV4y*l3#iTa)oW{8bAm> z>v6^=0i4+%#gQ;Uh6u6tUb=Q_8C#lCecYh{6FmMVX8`@fv$O=4t$&+M#){zE#Jb-{*x?=wyo;Q4+wQGjFQMrLAp7nLK7 zO*K{7f8<6nN!m`4e1^S@>$zN=ivX)p^?;wI{7)q*6Z<2#LevNP&ljQ;9-0vJ-cBNUajt9fuq zgmA}_JGF>5O`?qu|0wZBKIJ~vP`gBVma*g(qE6b*eHh0{ZV!F@CS(1k$c9d_En7#5 zfcRgr21>L6iS?-h%61 zoRn`M{8PvLG7vQO8y(r6pROcMsvcxKx=!dwESuNzYCl(aiD9C+W(*QUWkrG4G+ggG zPMEpX>{|zk5ZioJ~zHhJ0*l#GbAgC;nz?)-2P*cI^}!(V0;}|iXe1D z4bVFw3E-ACwcyzv*fvUAN&t6}%%g!(2`tUUxqPiS7SWzj`dBfsD~@OEOzeQf-;J>e zT~fFl`4}dA<7@QhkA?UFe32PFqa?)@Ag;an;if$;y;_o-fPneter=A_ zI;<}h6COy@8DW~Q5OM2DnN%`d%d*IpISKfS+HxqSn}$m%K%=jnMrD+5V`%s8I-qPiwqmkq)emm#p2D`^5vgQIGot z$X|ijbGmtt1g43kM3%ksE@!I^urbO7(KU0eqn&z$y&^GyO~ zXO&`4k^Mv6mXJ3bTR-0FnGrUW(s)2=f@@fPeOscY!S|33L?pg3r+6yEe);J?4Sg}F zYa6c61T%lEf?m)-CYD>X5cVbnYtppc?VWjBSqqf>#hg1T|G}9hf4F9x^p2;s70&bU zy0)dy?V_Ti(lJX;j32fTI9dGXf!kime_!GJqx-nJXoNo52n11hRgWS%>}WVY))UeB zrIJ3tc@cYu{bf@+xviSvJQG(*koDe}egXJn1o6Ow7!T5s(txwQSBtM`NX13td>TWD z*@vJB)kL(ll|O}(s)_d;@LSp*eiPy!Z0l+rLk&JHwV(a*7XI7bb^NcrD`=+5i?8`u4DZ*pUkZQ=w#ukkm3ryX0;PQKFqlI(UIC2b`vP!r1=Boj!+hu zLS_pwzmL#YfR8IOdNfForwC)rM?3fs>`axexWlc7-y&YfKbs0ESSokOtz13U3uOaZy9m(BsSJa=Z0L+n#PJpPF zXW&hy8y-X5A%#NIZ@w~Uw!kr1%`nVwN=?LE;ijVd*{BVg5B+p%MtR^@RBVHLZBs>Hs|E5aT3nmWD#AEueXVLeo>;qy0Yu%z103bhOo=3kEtR5W?5;0EB_ zMnQudmiKleo{M8jOb=DUSOJUYz zY(ew!Y8qTRBwsvR)vC9*ylMv`Zzj-phJ;+dskd7jJU2Nxd}s z{wDv#U=zU>TR`#eM@P76Ag75OU7UWOM_@fjEnxS~jK7+BC#{dhN%!C5S`VOSbWFN# zt;JYpnbcH>InUi+f18X@o{(^Dx!QCGtv!p}`TWVlHIv^T^y$LH@z!j@yu6Xp9lDv~ z8q|V?jr#7@2G^%3ns7M#l~*Fy67Za6GiNrp96`p;)kc@5c*@VcGD-_KDgViX=P2`w z_r=ttZd7ZWv9rHgt8s{FNqLGgX@wVkgXeVE^x{ZgVLFDiwIADw7Mtc>Wy6y>Twv(C zb02p5%k{D=hcLLd!svrn+YYBhzI`)mk@^m0=9yfe7sYMpv_PZi0zea(eMEBaxK9*SX<`35jU*M2SN)=_VPoN~r6^q} zvTa|jg+3!GZd$9J-QI%h&4Dh0PNBXek@FAf4`=+}m`=mOy&w@p&FVd3 zl}mt!C7mm0!3b0hms%2d{(Z`>X6#AsRZDyE6$Lr}qgQOzL7<N~T~MyzQV59rrJlh~-~S&VBE%tMyv?*{oQk(g4z^1aX2o zZq~C1>*)^`tGaimJ7wZouCh-q%YFBR^qZ$A9Hh?XTTo+u4xIUCwqjdde~tK225m~7@0Wj!7IXvryEW?FP#Sq2d@)K5Q1+0+5OGEPpxY~}smOH( z0{kAt?Q;72#bq~&0bdy_2qx7K$=w(MfD2yOaYOa`xJ-ccB%1atLGq~<8UX%#2=E4KE5-Ghd z&H2D@FMIk4d`BSDbI)M39HsuQ@YVU~dzIcpjCcg$29S}L1OXrr4BDAj66qPNFtc>! z+#T#lNuaskd@3DhgwCL@=QW>`(Z9yaZ2z`s&OhPuY^hNlakcaVZ=CpbX!If&cSbbL zdP{0H_okXhO_$19C5$z?*(b*zq}E3FjidNm+bOY|0eZ{b5f(OCJ`7;PV_k^IKreRG z2xTVqhwP*x^agJox?roMUU82;oJoF4%6=hmvWO#dNa_|VT!bo{F4qF|VlO^bm>S20 z*~(vh+=-B)%Bd7gshum74_(CV6X%_}SV7^zGu54Ku9LFBlQ8@&@FoR%CbFVdpi?o? zDyidnH!WH)T;!|8u@e>_; z6b831VY@0&II1j^Flp%xyXM{L0``(|%EP4ZrL+2{>|0~4uqR^Fr(Dl9X&cNEPi7_W zj-!*m1R<3%_Z~7`b!jongMT02c>)H6j>j{ZRR7?c8|rfrRC^Am+gW4MSqw!}DTKBd zj9w}AecyT*zD9D;ay0)GC=9)m7?`qfu((U;Y|~P|bJTDB+_Ulh`M_~nA?j`>@5{l& zUbx_z=xH_7h4@mlaHH6Z>W0fwRB9=?Xhx^CoC z*UelR<$V~aH%(Kmm{T+ZfrS76hUCQIK>*+Brw8ZE` zsqXj-tdK%}APBa*hqMokG!bQ`!QjI=L_%p5U zEHIOV*K2X{Ydv9=t8_#H>eV{4^IIpU%CoDK{g}wTWdQ5-qCQgkJyLn=Pgp`YVR*nT zjH=02Dp5m2x@&4(6{TP zqJEicdde8P3vF_g|r=YmF z_f7WF0eF%p_fAb~Dcw%zZMiWdrW=p+pF2?qex>*3ioqdSe(cp=cXbTeH@eEl-q}9! z?0%Xgrq3{u6b~+zXnGM}cH>qzWk2|XBC6rpv&2s&Xz;@8dSXwuC4*S6yG#LoDaNV3 z9Msq$0`fr4ipWq+4)=x+5H|bQK3yyoLqpM(`g6%oy?;BWqJ$rx*f|(Qz7UvCd*rOa zW3i~&7lcd_a@IB3XOqgT5jYRk99;{SlnuG1|5obeX-*tEce>v03|X2H2(1>)eV=~e zaCV;MBZ1?goY8#IGB2owc2{CVE9&;THg-BlN}@y1R)WpY%gird z8F>Y&{06N?F8H4)CtuC$>QI7?znO;3#Evc|q z_U^A|@tlHvYbQkYkNn{wmk<^2%@MiWuy#$}o zig)z!c6#px33>i>e&_x4@{)^W;&w1mu2fG3E9%qXVl0Z zph0KdYd@r||5KFgONRe0N^t1-dGrkUd47Oo?szJ+dD%9U?1itYoyBsO5N!vs<-@k| z+|L-5dJ>zJ;g2ol_r7`g+{}RtrZ}Fray(+6J-CxxbQ*UvV=8h0)-GQsA=3wY^=&6s z9T^PvrcpJ^a?MJ@Hx75vzSnlM*&N1LS0pEwF5`&G2Rwbbl$l;9 zR~v8Bwoffwjm+1V4z>$}tkx(g?J2fFAXPeHxAMF6XIe)vbE)VpDbK;O*Bl$4D?{Ed zR}tP3G`XMdWn36D`mmwM85VnwvVE7}62LEK6}cgh&%~Sc2Es1S z`bNiI3o1{inaU!_4le`tVqC2>byk`AieNgwB2uDL2T;PHqaA%h)2vW!UovQy?mem# z@Z7OA`2{dC_4le4=8!=6$BvKhuqEY{qFS2(BWnBZQp>>QRFJDP>3GrZV z;X_@E;}&74G6w2+;=a^VZB6IF)7;O~&UNi>h7%C42YJ5wb`@~^UN0yc_eRHli4~fcZW-N$x@IbR z&DU4p>GAp5z42#h2IuOT{Z~v1Rr5D}rKE|2tG5|~?VT`(@{+a~o+~e6G`^srViXh~ z=+@r(3llF+W|KL8>5L)`L|gC18vC+yJy0DtZDQ$si@FnyB3M_WlBu7~J*NX;lQ^p9 z65`mEZh-f|v2t>t?eN;YZ$xNXsMCJ5?3IcLeOc8eA_~gkc&2cGs=)z!5T(~~Y*h^) zJk?u&FPk8yH!f zgtB9BNY?Xv_?&d}LKDkkLl-=~=K5l;hSsze>bhzd41&%-- zWaXQxvgI0ImisZk&HxKUBGbd+2C;5;AFMr;f}2@GxE}9aOjpq;Ph4b5?%nx(_kF@E zTUyhvE47QXay5dB9{NcUGt?bbkLONDL5rf6gc?T=)@eEOg3C^Kp7zQaG@$iReps7n zij`H~-Uq5!+%9EADOMSFJ>`?O8fH(Jo)^Eyw`##9HXu*A4@T~Lq!t&pZIYt5j<+YC zLWv(53XXAqJGR6Kcc^ijCB?2XfAdswF{)3v+KEPtJS@;a|x zkz9BIw{hvHL}BO|opzaKpB8jtHF_-${5<`!ffkwZ^0`{TN#NYGcWg( zkx2tN%d^i{U+=ufZQT>H3=p4FrJz2a{N6el{g%^3Ds}e*L{jAJG$dy>nASuOvzyM; z(X{nkns;f5Ui*paKD~fu&PHh80cF>P#FcW^Dkg3k8 z5)Ai@E8S|){0gbK_3RRXyOyy1+Pm%u*m&?b(&k45*v?GV3o-}Used`i;p~t>-GqTL zt)^l4Ec227RbyYO%`i@LFV7M-)fxLLo(!KjW$Iu~ahz+v3u++&9Ztx`_q-T)@k)p6 z1<9P3yHE5hnfMNf<+WS6f;P1?lw3Z659Qt29|{a_IT^;@uXi266uh1ZiG3gfGkodppM zTny7g9Fb3uqu_wl4j*GDBs zf&#d~BK`6y>S{gTyx?}2`Q__ZTIR0133oocaye7#4rPRgI)y<2S1MwcZ&!1{;i)Z6fNh-|Tu%=V z?=1m~@r*Iu!)?7?#M8bqky?k_wXZkgm(kY~R(HgWw=;>O-@ta6P{1X3hWONE&hn3b z1f7apezHW2=sv>C3lL62V`SeFd5poG{}fV|;cr#=3CR0rNm<>2}ObgSg0^e4| z^ym(DxA)iesKwE4#+G>}{Mt>{&WAq?^py((>iGz;8L!=%WLO0HrwhLCex5HnBurkj z$pFHbr)SI|X*uzcW-6a8_##D|z28PH8885yys`FEGcOhuGqRhSTU{S!?S+J_ZX-OO z_A#>r{;9q{rwdmtHxG<)Tk)niZEL5^5mG@bzryA=ItU7lf*x+I%?vf!{3h(%4f4G!jX?7^MBk20z^&i00K>!?26467b}w z)xQu5S>ek(tm5calveo6R4!}s$yPxSuV>lcY9}{FoU}ddZ6vF zzjOIkyb`q7)MEmME#{As7Uy>6DEqMy^(bXgS(86c2-fMDtT`%!7>+|Vhh*YT_EON7f z)-|EjaGT#wxA|xxxDDflZ7oba{JoZE;&$~;RSD_ zWmnD(G~-lD_STZcWAM;rlh3;r(84KYdN}_2m4i^yHe6X^5RY~FW<8)i%~d@6-p8GfehJ$!eH9P8-~BQ< zE++Yu%iKB)9fwo)WPc{1C}W>an@3NL3&{Bq+BJs#o=IPj;&-&cyao6BNAPqmGg%Dk zqi)VlEsp=}l|M5fTQTD??tY$`^jwNVPeW=`MUoZy2Ia!0XZZ(3z?Ai3_=GuNif_@C zY3D8jao45GJKbPYooD58&k8f=yK=#s1lKo*ORh&gI{8G`*XMq3<$c{y?idgvaP4Vr zicxj$h0$^@e!YGFCd1EBK{u2k3t~nCnPVvOK^Oy6R+#hX$6-R^ZRhMPBKLQBN{GP< zoPg1zQ{z}yL^P-C*9?h6@6L*m`$^&>*5&UO2b+tRuyrMmAGggBt85`IaBF-4`}?YR zp7m7=r)A*y7d;37rrQY!pnN@_8R9{7XM^63X_umoI-+@v{;bps#5~{LIts1~ITYWn zPXK8(Dpo#4H0k{6#3Np>!%&{1lBT8}H^7UKN|*JyT{-#IH{gOrdGRms=6P{9RKYIh zURtfWB)zyub9A4~{glb#({=>m(&qnD)gH#YbO9J(hA19_X|>=2>T7U*?Sv_2M?$}D zK$V6=$5ay|k{GDanuKo)=Q;ypmi*s6?e!3{F}pRL&c<$T-A1U+!amASlkN*02a02V zW4m2O;Si-TagBr)D}=UEJ8!yg)#GQpLps=b>cls1*yx0UQ*Vfd5ic>oh2CqN+53Fo zv)!U!%eD(Fg}&=W$BRA`DmUN#bU|`C!zA=1%My!1#wF7aavFb;c$=#*g;}YOZm0$d zesQTwk+;j~@h+Yh2dy8Y#rqrB{;8<`na&b+pN-Vq;z)Sgdx|FL_R4|dvmR?$xUL<_ zB!e3+CRZtx;Gl@t54(i7h~PrTVXl!F<5aZLzL?px)(uyM%`dv%lk{3%4T~y|eKXuk_`E#HCW z%lyl~sHoH2 z(1MDe?c^sjGmU?rTh&C9JqkIo-aE%PGLd81e%Y+l19N*GrMV=>u08yA6KADaQfRF+ z*I@27wM0s2P}i;C4xvJO!nXCz{iWQe+{W1ZI6v+E$B}!2K^jLt=2^Of=K8&}rvYca zlQ7pA%&so@K_z^7heE4+6A!242>o3*xVYfA+(v1S6kRw3uJ8`R< zd<(Rg_*N0wYbkXO=wnyV<2>n2cdH6^eN5-L=q$!p*mOI3*!uO&t`y>!*)krw3^uJZ##g)Eb9-_$U5Nc+NX zzuk$}FvZ^Ue3sa~_ny{4LAtcr>KO=hX!+0$Zb>ucX`9`!!YReP+F|I!WEA!#s4F@Y z(kszEJZW9L%gz&^^3nOp12L=YGTcr|CDsIQDuF!Urm-M>XKQrsLX)Y_JGkcgzJ%x8 zwsO4d`xJ72uY4pogOn)cOJ`JWY+<%hDY?qlu%IO=0bL`sD_?C4o!B=*!cs2BITucC zAarmoff9#{g}@C4Y9wk$`v#+pVLtok#i|mxcPD^S96|Wv24-82lAwco{!-e{>>cgY zCT{To8xI8{%b1l0f55aJZvEt;s@KC`9j8lSZ+U)meR5>@gGr|9T&)SUaAT%>w4u?E z7+@0NYX=%Hs@!U)W2AB5q+I^MLNDnzd#pEXIbD;FH%n3AxrG6 zn}*;iB%Y-Hg$k<(D3<^(W?3*rVT@M-*d>)BPZfG1J|CK2shS}s7WkRs3T<%l%V2kn zND>pPBfz^GiH5>GcAqlu8JqCT0Yy5x|K?s=Jo`Nnacyq>kaeOOOK6hCvPYF!OACS;cV(4L{8~zvQ{kxy@e4cZj7w66SoOduY*R}RuYwf+i>$}$8`}FSi2$GAb zUGeM}OkDY{ABfGRD_E|L$*_w&wy}YNG-IagXQ)-^3>CP4qreQ@o-i{P$faBps(BPG z%6xE|Sntv2fXBTNujO~$Y$ST|zZ zD)3pHz&9%Pn3b!~FT|u7h;0N(QRJNJO}@NB+(w>89=gmb8+Y-Zs>rGm-0{gug@1W7 z#`4y>C0LWykEKWrOOWkX5B}cd0lM?=HgzX3LM9(LCu$ZRY;oGc5VUF9gSvlL`#+M~ zCe{=-0Ccd8#M5dp+WJ~YOgy*Z;IK$D7I_U|E$7Z!AHm!wmAnhWTed$2?u`6u&;np< zuzK3JH@Nydr;!+`bVX_eGEcWO_ws6McBwVD;d&awQ@`(R)Nigny?B7LuFM_eyE{8g zNdqe5IsKfV0xZ&~!rB_A)#^j7auoc!I%5s~skwVy&_bWxKqCmhzdwVd5=|)%6D(;e zE7j;g65@j*Jkh#Xa4vQMy0h^GVo6ks3fV1tEU+l4K1Dy6LM~oT8g*YpM9ZW(;p7_Z z4kSZB1D_>;E}-n(Q2R+%EOYuSaXdZv!1TygV`i@*DbicF%b z^a&)6O(F8q7R=*65#&3r5bhJ5aRX^XQMG<**Aa6xqxjAocZ4K{0cVj6!f z+M>;ZxVPcnN*}}S@IX(tYJ;1QLBJndjN1AgWyr6slJ>I8++4vxrr_3Gq*}DtZQH28 zbGTj}N!E^KWfKnGvpf=z_s@{ua7&$fvIpH%XuwdfKasuXnLxFSQ1bOD3}Rs~AhR zlBFWAXj@dszemNnNIQa4`gAU_doMD+Fgg|2k+J7AdZc7Y6KTTZ)TtG|fp^?56W{qF z{fx0Nz%Z?iP5h3J32L~|sSsr0yO5`Y;2!$OsW9MX6`lKS} zByWDiS(L?pxdB68vf_YD==1ns~Bc)9{pl+xA-{XNWsHQ@Pj%GPj;ktJ>ryA_wzNCDV0#i$shUh+)Z`OP3m|K0wdXeVZL8A2WL5T0WNj|(?H1X$mng7t0jKPd-uDJTH&+80y90PU}%D@=X>AYp`5Ja)j%%Uh7ap0S+0gkPK#tW zP?C-+-W4-xC0&NA%yDWy8~t17iPG96w)tFEokQ>U(HF^~2w!aI5A7h~e$2kw{pg3%xz*ua74M`=tss-APoyD4qUkCoVY8ua$bocI&nzCp< z(2q!EX(zz-_bQ2KadFaaCIlgqsi0@S`02dA8S`+&gdHcDl6#&|Y1yN8D-dw^Vs7zr ziROOJv`V{ft?Ln$(h%0yM1nzRF`_JfBt7NKZA-KIH6sbfEF`!rhLe-(SG;~(z&w#ge@uXH{pzDR*ArZW9U03gFwe+WyWVq?k2C@ zF4C%g?=)Cx$Xs%@K`)>~wUihS2)0uqW1*SGuMJ8sgi<9JRwowI?!lfj_jkfk3yBEI z&6?``n&l8==_P+FtLfe&jUiU8I~6K&J5$P4klmIuwMlwKW)!u8eQ)C%Z%yw?ghXEh zuZ?jyW1h#|^y)^Z%^Iygz4iWmX%{-1e1zK^T5M78U>pPn9eL1Amz*e{Gz1MJjx(5# zJO$Q%A_nu|^IXl)D?%PO;WFFbuUDOI(E5fzPPOn}<@E6C%%{pUJ+vH<*Hb@3)x=+` zuz!#ag}hD5={SF8f-)y|O$^7SoO+3CFZ?9c!WX~&oBC~+BM~0ed==c}$<>FmXH6Pv zkIokDw&yk|ZIw8FxmeH5@Z(tO{Qe7(m-TyJP!Y_9>$NApC5*5taUK7{x1+l71ne0gi z(!;7ak=fhdV>RI2lR{ak;y_tz3#nSN+>t>r4dvwILP|AJIo?B()mae!JM58(nZm%G zK3)L)YAZ7Pd$EorTPFbHdN*;(TH?$q^;-$v_U@%t%tulM;5||~t&5SOq>=c100b5j zmhckSN6 z80q!sMz@O^>D*_AS{xpK`{FL;VdrP2=CBS|1uggJ_{MHU@t+~>oO_&(gtV|@CyD}o z;jPZX7GkAuxEUAvxKH%gIz$1Ti-W<23cvahN%<jps!AIN~shawFH6_T^i zN8mGp%M+e1i{+ouHCX!((Cj_Z08aM*l#1N;HLkA|^w{!QymQpV z-d4Ti9s|$+Eb&+5FKg$u<9UEAH7sY2o>HPWDM$ft|452$-wlTDbm?-iuUyXbHPl=% zMe$3WyPXRVLiI8}>Qd*J?!9sPX%Ev4)#hA?Au*QWSXFN{>|MLp) zdnaAd>T(#ov7yAmJ6Z}Su4co~6gUK%542ruc*$>8?_tc9LdvJH_WdPbPlS00(iV^*Y=-e&@4>+8HJdqa%39JucvV z&(c@bG_UMA*g&jw;R|)n=;BTpFzM4b1SOFZsD<7jem?`z;K_}<(HMf#>4Adq^JhKk zIiO|+POb!G?H*ME-h4jt{Xik>?&2 za`IS$@LaDz<$6hq-pJ*>hj7jq5YOd^ho8HV!#*VUe$9s^=l4)3sGq~rDzLI@ga4_i z&g+3KZQvMm!AZ^pcQAsdyAoonGI}(!|4RI};uKR-BfrA%Q?ElZiA50}cdwo(Aq&Eh z$fi$&=kK4HBFf^lU?->I)*Wh76t+`)v1y#^aO@K9&tmOqYdT^g&Gy0^OES!Qp$ybR zI!8%hQ++F|Hf32qcd!z(w5(A}RFt=v z>4mClJZe0aROj!X5QHD3g)_wW9&k!7*gRYEojb1mOoWWe z+T-x6p7Q@p_Fj47;(ul_By~-1ZVlbcR(97 z{!Q|puS#A^XW*ByElTULF7AgDu!3;lzcB%^{dG(boWf{FOq+{Z!m^&}QBG2PhJ`oL zZb&LXCGv#jKy?&x6)=!8T>F%<=|xBbGkcaYNChbupQuNmWXkz69y| zTB2WAsO0S9&Q?{cIh|*$-pm7VM9$nB)QE{O*Tr5uFvI=)AY_}VAoXheF@WSNG54@% zgkal6E$?ne?;@A=QXLR`ilf8OJ@z=tc|;G#Zs4-a5%%fGx#97S5FPZ5nwnGYTEU6} zZzqCV@>%Cc)?8IR*21ADZL5^6+|&ExJXU&IiN7yiR<7Nr5IwHunqPn0maTS5w0D~R zek?{mD~x}~^vHYbS72E< zbhgDf_k|sQI;LFYB2aoa@8fFCJm{^PjqUA=-Ry|FP-ACVgf~C`!2t^aM^#^xEj(Hr z{P{WCm*HRf>SR?saAk` zZbu>F_c#_K%zwh4@GQ#0{2DJ#dP5UVotkXWt}q5CUrTfLEou(CkzIPN_2t-1`2i#sXb*<(0TLiryYHWEDpz_4(LM9^8z@C5liqmIMT&`?bceU=pwntfY$%;ILN@cLweS>XnYRCZO{>C%IS$bPQO zpUF?Z`pR23Y7rEKXfUt8AmF_w6@Sl1KO}!-%2cR*N#JK^H+5N?LZo4EWy#`m&I(YG zSABn|$QLrv3AHtITvi3^#nVmC$SQNxStO1IRCIz2sA%7b_KZY66#6^tHjsVY+%DbrsLIk36e!-AI=XV5aq6w_+(iH{v=yV^*2^ytFRBn|R_9^EH)<4mjpU`IhL;Gz9 z1gHvRC^xNq(7>1jbrWlB!+T)rC)cgv>zi%R;ot>I%W=hbpM4@lu$A*}>aW8;T)q;s zu4taEKxRtE;gi0V-d-!iP8j}J*uQ74`Mm1DBOb#t=p^d-dGO$T{5|j zGSPuDNXditxAKdkO(OAmra$i=VJ9&7H-k%wbn8kQnA_-MoYTE)YQF1o)N$VMb9DDp zeYcC2A2E7>5lFcsy6T^yLQXDinZH94GU-K($Z98Sjd&2+ix1$TV0-N?I;bWsklTr1Bq42jW#DUbkw`)Obj&gh!t^qr zXAa~A83Eo36fpkeVws;3eI@!4S$`m<+}|0ZzViwZ2oarn4jvuY&+CkfB?_byC_5)o zNya)JxPKIVt~7AQvGjhuNkeB?Xw^iy@6oKbC_U;M_4GFUA06Ek+9o~OwTtn?P07j) z{)}48&bm*t5MvX)GEwGOw7+RptS~A}G)&U9U4$4BdP(Cs^ei_;;1*$B%@KYK?{NQ1 zn90M)(HZkdEW6W~%`QDXE!4l5W{j7Z$hKI1^q9&X zm*We=fjW;3TJDc==O_#6)yZE&5Arz2ooG5sOOtU+I1hyf!Zz+H1;56*GE?OI0-%#G z78SzwHM{O}puGnvt_(79#MZxY8_g#;F>adE&yiay{3jVpNhA7uji_FPE#$Zw8KApY z>WoF;8&dpv%e=N`g~L0ZKp~MhA&HKFnuZcA)W!Zr{Q_+i)V-^fk0TV)V*3C-=1|1W ztI(Z%jTpQ=wl$%vGT$01cNW3a+=kZuMccxrOD>W1W|}z8s7-Wfuf0l{{U!%?Q@O~) z&XE%$QBu9Cv3Ao-n40;_8zhc?UFdv{f=i1~h?ixGY~a_}jj(N&Z%dNL_b8e1HbwDc zAn}{#p-0u4C(BQ`KlAb|f0WW3pBj-6VMF-_XZ3QNxwu+KnW)JPrUWC%Q^k^$ERi4a zt8;d7Wo~xf0q&Zlab7_XFfZNDdHSdxF;puoJ@6wHQ+D!=I{F@70~g!#HHE!aii3$v zxz5YFwPPv_IRw68;HnuJlsZnuyTvS)Gj*u$kWxir;iGAEft@*OwV%(>DfdO-^;&NZ z-P1P+$TrV=V{1G{^dT-RjVZ@Jl7Vd#9aP5-ry5tvKYp*r(gUYP9b(ZY=ALY@3H+H z+Z48lsNY4AuzG;|sVgThOw_P)K9_Gk7bncH6N}Udm_B{W`khrClR(0>eEr)~_9kH< z9fq38hS=WFVTn=r6(e|3Wqfh}ycQ+20;iWwMBf`r4mG=I;1KMa$JcvKh1%z%OX=L3 zUV^_i?vnlD*p)O-O$lL4BMHyGBkv`9qRLZSj=$$lJ-$)8za{iybLk69_dvKV7{l+* zFffAv9OYgjB&Xw--t+q!UmEL)?-Va6R}TM}lANuLE($Q;xxCKjru2=U6xMqjy10hw z>|rM#!-B?0HQEI0wiwhl@>gV4=m4nD`<~c zKOgxa2HOC3rMoJVObp#w*~ujj0<#I9{cs=szD^Qdjmn<`S)2FCK}_7nmoWD zrB9n)`+Rx?nZQJSty^G%!FXpoToIH!SEgw2C^e#?o_$uQ5i~{f`g~5bqdT%5kNb=3 zbk=+{$zNcUZRvaij9U3Ovq@T-TlaXre9~ew#5d?#NDI-*_l7+-yb58ILM(Xl7?pBN zj41cVa_i8zv$cJTUfc-Q)k^y{D7AL@IWy1WN%doj<`DUycG1n|h>N2Xe*YT2MFi){ zr^A5g8O>SdG|U2Y^DTHxoUx+z*b7=jSWz&X%aKLy9mKLI56Khs9#aCMc7vIABj4QQ zgO5>nl$@v@Fy&-qaDN^ymuTT}WpUjAO}^dza0qeS>s+%_^eo>79-KYaKb?p$qPzsbg-L=uUi3=eQR%dDf6T>XYWL2|RQ#l@eiN5R;kXkgS;~&m$Ntz-m%jajaf|%J`b2)))aXw1a!-==)pCU$GMR)aA1?f! z57YXL-n5M+Dtdg)m%+j}!(EIK-xTK>qy-}r-h;Eh8-Y%~g;%%LNj7Y!AhN3`@vzw< zx%;f`_!<5~w6L4Zp;#*FUT;sr`!+gZ{yZP_nbY>pB#FW0Tyzn53sZ!jM6pVyjBa0q9jk z*Sc(tXONF&2UJA~57X%6HnDHo#@U*hBr{nmhp(oOMhIq0 zFH;xFwrh@-TYmCs?uP7r+*OkUcsMpU=R%#u3GB!F_VGYE`i`mc1Im~3ta6X=x2b() zd1F^g20_cgGE%kPl!0h}mt3H4)lRsv=;gRsvzeF4m28ii>>z60GGRY2Wg>=vyB^4BjaH|Yy zhbwye7s!zi0MwhIi{%__VlKZaB2H~#?X8^?SUUwX2V35DS3yrsTM7$}&a%oR!3raY zFnH?nXh=TapWbK>Oi>U*&_F0v6|_BtYx*McTvK2w|5SgQ@wh)|@`cYvKxFh)LjmHU zkAxbq&VS62E|z^18;&CB*=1+>dcDPkcdp?TDVYGn6~Dvz>0IwDG^6^*Ty<9b7FI^8 zY#>VK`s&Iw8kUe#piQf7m5feiEjpC2e_>h25LlaUn} zItAVO8g(9zFbMVi6rcv**xxb&(y*b=@9}y@CNpT4HE!NrtRva}x*KKJ)Zp4E&n0`0 zPA!m=UKcM4#0{IU$?crm(|M^e113kyxdxXiy(BJDCNGdVwk#JpzT+Q0$zJDyNwUkjR`U^fVF2q(_1Nd6SHu+f&-ZJ%@(|g()ecjowJ&nyu{u}2f1uOtU_RcaUxy>@+ z^PJRf@1o6}o&!m*HMp)D>X-E{mYZaEax}^LUV_MA8%;YY!(`C9TAiS~NLkZH5OFnr zLDIe!zG~U>sm2e0^MlnTuHHLxAFp$qfgbfN>8u*MNOdIJ0h*CMtUKx__pJC_>(B;2 zUMeK&clKuiVB;=#cT@Z8_~bCc$@WmyZ{|WcPU6qNmvAkn6qZCZyM*WowjWA-G&vYE zSU;xGq)_2gO6mB%9101AobkVygvm<2@?H`#OmH7Oy)@OZx^yYxDcAAm?`h8x;sUw; zDZ-(fHYj6vAR?7tHer~%CV4KFT zb049)r9kfEw7mL?m5g>+zM~wj+hZ2Hj%JjIXLt5WubiVeJHdyq$nIfHTy1V97h~^% z$Hy=QFAH8|*xEa3w|xfc{dx0CL#x@>mjt}-q#?vV0Q)(iDtkTUYzAkH_(PZEKfL;| z`r7RQRm}b{HkPBFKQhZm#>H9?ADwze?}7NKQe_;0RT*062UlW=jl@eD>^udL0Fn_C zrPZ&IITb*@i)WB&8=3F2Fe{cQ%VJYu1$)I=#=P(`yTcn*c_@!39P&9E>D*4f2 z(@h-xU^^@QodBWm6HsPac|ZV2&1H018s zRc1M+wKU&cg3*v^p&yX}BLS3Bg!78J=&SQXmQ1d3t3<=jvExk%FTuHZ(x6vXj%WO= z^r2V$+~RuQ1ftt@d`vVto4R(Ro8tWha4_Dq0*5}2@i$9e^7Q;JEi7H}>Vg`$vnIdH z4S{5aB)00fvh?EjZfS?5V^TwALC-ApFwUYJzA}j>G~5I+)mQWV%0BSxK(E*h98VLh zChJ{0m35d#u{_S@ZU7Em&=%j3aLXC9)w`~$VImIeC&fwKIyMNBtK>}UX2g8hl!?+- z%(M6V8Q&BFk|K+CNvEw4#EswWvy-0#P5Z6GP1I?r7O6z?nXeQnT+u)6Nb^}>Y|nRW z8<&e+c;0zzg2-h#!1Wndy9$t^_u+iF6#OlyGDX>?W0Qr2AS7GX@^`4A5I4V&xFG`5 zzrA1?sR*VejI;U6R~q3#mE$WVZ>Y)-3;$A;Mm;xF<&*N`SCy{uHR_k5YqP{rOy3tH zcEMDgDzn(O#c0koZe07(%e@GZ}dAjl^zcI z#l{2*s%O!*#ev`0`jZe{dtdk8%gJ?omo3#V=U`>xXY;?D^f_C)!WRW@7iDKl^J+0) zT?|Et8F17IBeccFtir#~FX~q=WbnA)tG_?Ep2%`bvr|qs?qc@}pKA?h3lMPgq};h= z%FKLYV-VB2+7;gH4FA89r$i+AEt9)#y*K19vy(qIOMOdM+P}&+Zwi&GveVo75kS`q z2TG(mmTNF3yS~gTk--KUFk-CCLm+~RziItXX2k@%70$K^nQ&chAutjHzbyws1bfT4nuo=Px?5pK*n;S8j7okUJHAHVLw&}?LSmf+ryn_jknIW~S} zVX#LnnJMUZZAJik$UJN^8=Io)cthxg{&-~P?CSfmp!Ds*X%t+Z(+Ow+(=^*ZGzM%N z`MLdd^za*hqX*`tgH+bPPfC`3T5XH6dM5;`OZ=86zfnieYkrkv5}bt@zh`UXy?Cuf zf>*cpK##CB1Uztt{#xSSN&2WM`4mVhacuS`nB~B@8n~PoJWyl3 zRxemi>~o>C_}lS-uCIx)RQns}4w=13<44Iv+TW(52<^%74-qK>P%x?E}p*YMf{!AUo4~lRRVE2 z8^;%6jauA5xv2JYZQB5x6thb|alB~7SgFeSD@SS)OZteb?SBi9I3j@pB%C=h_xYf5 z8oh)8v!FuS6(Y;q#1YzuTVrF$|*J zsr=NpsQq}8npleTf5}(l$TP^Tc&J`ugxFAWr{taL{$ceqDj`=U?Ene_jE^+J8U$Q`dj}?+t}=?HM;L$3Kk9 z-(4X9mvGZ6;04#L!e7=5c>OR{U3z1MCsQQ}1+rLD z>bJ9meoNl9ax`aJK~AJXEqx}11aAh-a)J}s4KKU$VNHOg{tMm-F47r&wwo_zgLAYVjK#@)b zB71>0j7XEgzwS?dRQadziU(c@oVEiWa)R*OH1nE#Ink&RmE-CD*Mq&g=YuK$}0wel1dz$>swce#s;P^b@5av9D@(Ba<# z*Zp3zis{)jJg}hRxDSc{w#u}aR#3e3!^hPj(&P@tmkvmb)5{ifL3tzWyvB_|pB_oz*bSAt znTw0Qhe;nTerEjAvB7k>sKIvfEfWv7=|4qfM*RkS-Q+8Yc;~~KGh@9E6!=bxjs9;o zbW}24Z|LZdNr=>hX34yD*YPJajxY1N&uDdIcwGpG{yCghcqliTS)ABr6&2KprTU6p zwc)>$Y*>l~map?jVpVIOCf0~utS*11Dp}G`XL5HPbP9A7=RfyI*Szi2F$rB*MQ@g< z#mgvU7-7#TTX@xpZ2z`#D!RF3Vw3Goo`A?`3hThA`Bi$U+n8PsY-_OWx~$iob>nRE zX({!dn_2W{nh;mIpw+wP8vm>^*YME#pHFQKs3!J-aP%xW>6#LaD`o2AV@X>UH` z+javC3+4OHl&{F^&7I&c@p0B4x=zbuOgo;|xO+aQU^Y3-h;&bQuj4T&3q>vVQ?1qa zmrkqWcHkSGh@A$fA__3KD-LWyRVI$dLatVR+rjMjWJABUZZWA8MUv*rWY;eZE6*4S7`?X@t zff+KzWOzR%dr|U%`+y|qabS+Q`(!b{O%SNm=&I02m368qiq5&#fxx3ki}KRwU5*_z?9w<2)HrGK>3bY-iYy$vY15B4d3Hk?;9D;O1F$t7zQOz%x zC*7SG#qa0!J)>H4M1HP8n;P_h-Ewj~Yh59T_Ez_1qVz5>E585aVZ<F)+BxowB&wL zWGbG()uW9JV@J!!Y06Cl^i7bNZTp-{*1B~4Qr`kgnQ6e3RaFYyEQpEzE7_ooyZfL9 zfIU>mI%91M_w0{HjnW^U1$`|2b^slA#CXcGkv|4gOw?^M%Vd|gj=@pQ;8~%u8S}ECljE9g0^3aoxZ4!Gm zhi>uk{O}mL=}maI<-X`Xh3}0vQ-K4By73Y3ksw>DpiK*>Nni(ySzKk+;uLtvx_#lV zs%+;#morTfs;4-Pd&S*Bd>+60q1sJeOIMZ`J^b_<*l=66&9t4PgR@16%qHoTcjCoJ}OkE?nDB z94P8Dm`S|h_{g=ZX#RK{P_BM84^Kgta-zo|Q_0^|t7=%8?S~z8O%&9CO+Ra9(Alsa z+4IUFH5+2L9P)8wxIHOJN<4#z+@ccS;5|V|OGZgcWvEJ`Q9ei~(pY}-+xIAg?2ex(4^NPUiiZjpmyfmoC`&2{-DS$e$)O;9qzn<)BZ49Yyyl6k zJ*WXvrj2VJE>2Uzj_vldehT}v5&S^#PaagEu_8N zu=`xejE731H7aex9}|5oB%0`|=5%#2vKyO20XbJK;aL>#xob(4xpX;|&CDTxHD}~M zEArsnfrl_u`+$oWHM&r`Y)`>Xwq$Ys*4Q-8Q%n?bst8(gT;fTZIjg)xTYMaaryB*W z_y)mz1LKo2s`MD7s6x7wR$fAPBR7Ihl3N03jNrcmBcd8Q}{>uHu{fRiV zTW=4m;c#j`5B`woYQ4fq6sPaGQRfo6;nA4KiYe8|vQYfwY+p@{6&|S}`}Qlyi1O_E zKB!45P}xTKN;$XNnTN_c=eWxUCPJKpKi@wwxU5Yzv3&P?=iSWFZ@i4Wlw`T0Uu4qr|Fjx9xsOgswnP=aAt{&mJDJ*$-1_{*d;+Ue478gcHodb# zwHkfwD!w`W3XX#r7ZEhtacs2lp{%;@j7x|F@?F~VT+Uy1d9uA&$B9KEuy7*n^@`kr z-}Lg58_QynKT-Ta&4<8}=3|qvYv}vZAfn=lue89wYAqW!n zn?j~T7F1zE=uDgQOoO@42IfcT$`MV%`mUOho}G^HslzLEE1MTD*w4L=*toPJ1HJ-(GFzYOvB5!5Uh(&hEQ9E#f z$D3O*s9U?fZ;`ideS=zqXGp(6Zv%gcK>`l%1AdkbMa2-PI?4)Vfl(ipBz-YKXq9}o zZdLLj=g`MY#w*B0(T_s;^^7;6rY7y9DiI+R69&B{w`WMN1^Ajxl^$C8Z*f$kTY&*n zfcImS(WCGF`FjZdN7BDCjSZylBeDKI%E~A&bo$~y{|@XwpeI}XEBjPA=eOU!>RhVh z+nYv88`XGN&?TW=$TeMY^YV_s0pUr9eotVeYaUxi_iqisf%anUGZbktl`JhT_Vn~z zHvy>x8HK+B9+j4sR#L)3V*ORX8hYf*+t<$=-KAs`YLA~4+;Ns%q=GO2lb6Fio z;sgH`@$9tz*(~Xr3`ta{qY~sU(8C$X+ESswnuoQu^{!si$@0od51ZflPFH?DBhax| zfW*i8z}?v7`@}`5=dJ8xnVFe1l$2tAIK;%dhK9=5??7EzqkvDV^!gv?f;-wnbJ7SN zixxJ-8G&rT-;9WY6J>)Zn|!F{m6XgYuKnB33S3t^GNRUo&9RR^>NJ;qR{_wpaGRi_ zzP`SVJjwB$H$a_u@*X$n? z69b$*?P_D!uj0=L9y?#APjRr6_@36S?Q3ZGY~fn7XBE)lRRQEY@75wOg!dHWX7lQx16qHrZhS9>UZ>YB*FpU>)x+myFAs4B>S$13^k#$tZ+ z3X{^^$kv%Wu%e$}0~C8UOMCOlEDJ0o<>y9pxJdx;^bow(Ba$8X!?P3yb5uS7u69x` zn_H!iM|uBp7D2kwt>15JJR~FnBGUmYr00r8Qiuk6c<|}bUbPqG z=YLk=JxN{-17tkwJB*89Vq#iCA5(dh6Xw5+GiUx2i_>~*pvrcVikcb|1H%*O;al_y zXw2u&+$30{&-b+;@t|tp;zTeQH8!SEjSn=49R}iiK)hCR7#G~9t_;gJ|6vQ#OwGFS z`TIy=qP8<-gSIapM{zHrq1!I5Z;j|qg9IpqCx^xq{cc>8wDRa1CitZMVlp+?X{poq ziMN>HAa=9RkCJ)#Gm)#Qmu(`BsRjSMFLVZ!G2FQ5wtUgHI)5r~=>b{1e~du-?r=8G z{}yJ{P6CGD^#HR%wT#1eV+D;j`8ciUw?%|su!50MF-*+=L+2o+dB;C<&k#Hy9h#JwXy`2Z9CA2Lt{Q-#($*>F{W~&&uZy8w^~kg*t~P%k zwZ0z4!b31n3PN<$p(77w-(1RLzVoc&i!~`#`1Y#q8i_>D7`Y{X^0@V&J`@Z>CD0-nL= zTSWR3hloRm)j8;o%-WfTEXJ2sP3d}G{56+NekKZ_%ajPH%d5o?{FxpTGdf5+fm~( zg~J7>`z9PG&HIs2xzn*)&8jxab9ghbgMkksTtjDO=fSn*NcgyUq4!++EVy|Y@+$}d zXFJtP(z%R%uKo4K909q|s)K2C13DNBJjKwZIY8S5*xip8|26!b=g;8OVvyB# zYV2XEjp)32T*hY5Ms>$nj`u)vlieqq-3tel@`?Qe)b~j^wL$X;*79$x3eO#EVw9ir z{Nt)B=Oi1FJ!e+dW9K6)iap$B;#1S<@lmi&0w}(>9UQSi5|Mnjt@D0oN&%Dpld1mw zf3&7E0~*!9D>F`9+)C2adrVg?K*?}LN~ zTaLD zVCCft_vqfnbP)O|_nhKXo%_3t6cbUGlj`5I0!39Jvn248$)Y^&odP$^92nCf7Xf$* zvZEDq5@Ic0Q2c_GvGJ3a**c9aQutsGd{-p7X`B?p-VJSVO4=j9|@n!#ry(;e`_6_cp_K)-S3&Q&|kiboCQ=hg%{m#>1 zib9)u=k-=d3;q0*+saa9{!CK*C1o=Lhke$3GD4)@TDsv3%j3kR5mV+- z7NZ91k3al=G~RF48@<3PMtzAq*^(hmyD&SGtuYuZIo{=q;1jN4m4qV@Kb9~L$^3hd zeuoY=g_W>48X~wxdKY_sisDKST`!A}(n=3ct@DZL@I|~YSq@iPqfykobb`f#j;vfq zGg<6|Uhbp3sYO<0o(*=Wgz!1DRV5i*F3zVP>ibpcN}`#^U9C~w*n6V-y9n*?mU}i; z1QuELjMxV0&S9*!4#Rr-STKvMq&~lq!V}UD`m8TlWoM!71AfS9`J$nT%;Uat7iUbU zD~li^GpAzC?rPsVf{R1RGRAFmBI`_$fuc~@k(FBTVylTq9e?#(;c4;X(LVP{tOL(Cw(->OF7OGgIX+N*e5mX-)l7NE();#^hjI zi4dh3z)}n?wu%$o>>Um<+QWdDgKZ40d(PgKJ)^A`Eg0jWjd)*l!Sd>6eHR;nhucJF zTojJmrhLgWO13^5%MxJvVLd}QU&EUq0NnFl#aJzFyK`93#Px+3ZXJBll}^d@v)f_k z69rES45sW9#!gq4rJE4FS;`+3RWYJuQ6td#8?da2c0K`F<8Wb-P=gj?Ex}~X#NOU! zXhz9csw&RHq{nQ|hOJ&eaoX`P+W37OjKfxAbXI*sP*l+gj7)J})%%sK3oBj=ujkU`~s$LC2hpcfbxw)g3@L4BsRU6H={=lQg=-$IiF>Xo8wA9*7{a-AU z`IvFYsN>O{EvkdZn0NGGFi|_jH?z7IUvZh3+Wc;&cVGc>nk6!r)k&*zN!@K(L2HYK z$H7!7n8Hm;5>2>uFKsX1QH&8dfJds1maFC`EAK5MqOh@zHk?aMAqB}E2H>X?1jA+{ zHE}s*PFnTdE8E>%(Pz0Ae*JjU=}J*`4arE+b#5!zu3}$}hs!V@CNiFk$$@2Sg%lmp zETO5vUZ=Hl(w?M0Odph^>Be2{{7K_bM8-Di|zI6o(|) zf;Z2gUB`jZFt_cB%+^4djhl;vmhy}q>aA*O7fY3gul4Ty1=g_NwyQzik;9xHY7>!= ze+xJfG$eCl_IT}~bM@`Aocsvw`zf^rhZfCz0MvRWX{sET)|eH+Z*TAYEoO1;lMcgV zT^6%*(8X+uwu5G6gSuu(nQMbXU-zT&ddw=i+w1Hd2hQ<_4p(2&I&>4NYdWm$k~O;q z@vEym2C(VRVx3~iVX#HT!YU6d$gP@-hO@_9Gh^^{kvZFm%zbqK%oOzzq{~Z`Wmh14x>PuG=KC|BrQvK5*m~DIX@}^-a0U(dkLl zPr9DP;?zWXb!ts@hx4RBfbwC0zbrvDr%@eY~p%M!Y{AmjyJhgHN_9vJe9RA zPO`_W#_J#}O!+GA9od$aG-LRU72a7>(M?r<`Y z6}NC$nfAR(&F`B|)h$7G91>K;&ymrqqzOq~z3V9v^Jk1zwi0QAk^rJ`RBq~ReH93$=wB9Y%>HOUa<#^(`Ih?8;B*5$`sNY zFS}nRT;fY|yl|vh#aD9PFWNV82>098_uUDv0wT3rZvpI353D6HZY3v-Mzw-*4VsWz zKkiXORkCDl^bUf&C}NvK_i1N%7dtkaB}gOTUgZSB zC)`&>a&vK7)LU0tGitUpHtVwN-gJkx|1KtEZw&cHT3fcP{^FxZ}%^hm`a!lkT0fc^H+@7oM%CEpoz8uuSr(IsIO(#U4gSM;n4Q&CJaF{4W3fL2P|}JrLgk zu}K}>`PU)bi8k2WoPkIIB1Vbs^obSt#G81v8vF!#^bF~{HRva!_y>=lHA88u^iqJ( zE;-rf;TqTO!?^f(KD1WQh)vaQY{R0?d4vP{qZ8pDB{JYMEyJ^9xlaWw+NpeI03`RN zfRO^FqczeQdBwImWmoMAOf}~gWt+E}BSDC|%QX+I4e7d>n|@|P-vMz$ura-ol9EkT zz44D2CI;>C-wqOg!f8^X$djUBtHguE`|NEbJ({$Qx39?utVi(k|HIx}hef$X?ZY+- zDvAOsf|T^oDJ9(?Au*IRLxXf0gmg)#z|hUmr63>;L$`Ey_qPZ1ob!Fx@4CMC`u+WS z{$S2L&+K`g{j9y#z3z3dJ*a|6D8>Rz z6)LT~czJo^ll;}w^J5v4Q*=Eu-S^g3dRnHaSLWJA=*;xYg!F{q6(JWFI-P=pg&rZD zvW&Koo{lv-oxF{<^~F14rdkGi=yXajU28)^4t9EUI#E5CfuS`aD?JlB9Y4(a{Tn?i z0drFeb2B|NYeIH(IstPNb1QiZEgdkPpq?#EM^D5`%K@EEQqRl)jKRRbMo)P051mdJ zW@4>pMMx)XqGhcosHbDDtB20RgZ}3_?T1%?5TWk#8sT|D|5KdAo8a~T{`=n<_`jKf z4}t$TpZed={O=5)X5f4Cm8`yT=>N%ya{R}M{&8`vOstn4j`08A#WlQ@G9RJ8TRpF| zKykf@SiI!rz54td&A~2g!-p%3E5AvNw3$mr1{>`4%B6j zdMHhM%UR@_`0K+DIMTXgk>QjN#pxeBRe@S@mW@~LfS*vm!z&cdgj6y=8^~Jzxv$yI zyoi%iU#}XzFL+WSdEc?t|5p9`t2eO7LM4N`A>A~ycOFvG$3JC^4w=|lsfiSH6XqS4 zX!tQ=Kte-8m>cxrb~YiUY~mwEMoNY@EM|@zO$v&H8&9sqJ~jLPlIW&9|KTxZdQgJ{ zDYN<<{1oqwka6CaP{G%b5*zXehd!FE{#PvDrjuGu3+h-WU%TLOITWLN{!VB+UMJnz zV!U?cXxV^1(AV}80T)N{)uvLCx<|LfYw;h_M#&m$WI0#m#|S&R{36TYf4J>lw?RCN?=c8_?q)NG>=?%hB8j+l9tI9m5t*3gUt< z(0@@7E(rF~XeUq#rdP%mHH_}c>*F%XeWBEM@_8g}C&kP}Rw_x^Qi^vLvtw6JajxN$ z)Y8_r+3Ab8r?!R5cWVvl8{MZX8)F7yN0;(hc24MVMMO42JUH!*O5>zZc7W z-p>si-IA~?H2+V=%<>;&{vRO%HfDeV{vZNSJouj?0yz;g+#O|w-7_zP5Bi>3gKT_3LV`E1Vyis}d))R|_3r!nmp1v#ExldLl=}r{ z16@@%^}Q7-QDRUs$M%VF9#K{%+tuc3qx)Zdhw$ZM#-q8Jw+yYlzEKOeh-yaq!7pTFn*{TTfl z*d5=6);W2CjVb!ek$2>wC3@;5L86fe3KNq(bx68pX+4_{=7}xZ#aDa?4++0x-k!u% zSymoe&{dbM*IY-2r>Y8Na%_ol#lJ3UqF~&wN|_C7j~qxlJ}8Z7rV*nmA>ifRfIqaN z_DC+;-f4Kje{oZy5|6|rjOol@ZA(mt1%LMJ;(tBgMTI2B@#VZ_cW3=YwRR6H8HAKR zj=!=%&lnHSU_i0v4Bt?NI4q?8a#}@Y}gXQeH*Ya1UMK z!36IX49jVl!$O%Df+keOjMql*ym&+|%1?t$O@NvjNfl_4XO(E0 z&Ay>PE86>YMhOQ8q;Ul@Nmc7-ie87N(&nyskHL16qvPTlm)+sSv(2qn9-a(og(W4@ zqM{TO6yM`e!$c+`R$4nEs2?X8u~(E4)X37qG& zzbjCd#IP#oqNSxJCr8^yS;IRyB%@BVrgCT)EjLMp=YFa+`f6j9-q7&9BN7N6s|maH z!W#vJ$MU$KA_A9l*q)Ob1=Wo!AG}2+juRieG7v3|ub{4WJ~h;{KR2un!P$FxaSl1!})7fZas_2B1Q`cy&--oBC|WG?b^to*%!vhtJOOWS+$ zlm2XRaq-)?Z<6XJrlyauu*}9PJSr~_F3i)PrO>KZ+V;JT7%4TMjz<|7A>@c-|3QXC z1g&~x#o*8opE_!2QC}XJ$jI<;oCgmG(>afMb`FLZs(@U5=q z&XBOQWLQI0tiU02ByqaL@!smUKiAg@7kY#1=H`}4+tJYhQoENgUzR1KP8Id75ySY_ zXCyB#f78a&((+>k>fIn5?yorNHn4$Qe0f|YB_+8Ckj;%=Tu_QoUW&&L%jX#qBPFIc zZDcbPW@l&1nl8uE5c5r>rKF@Z9Y*{e$R!*Mw7IjRyM)YqOP!9I#x4q^b~JMwVjpL-eN8YG`OQH#d`|)9UN%6JL4#`EV}Ad}HR?72rVD z#z>T4V->~CnW!ZT*53Euy$xeyai?3GdwZ!7&zqtG5LKG==0DcgiEhgU+Iu+gfko3U zsiG1k4!5$k)nA&Lo(2`Kq&_1e$n8(4^>CC&TT@fhm_r+ca|7ir{9dca#>V<-s1rhN zqt^eEt8h3xg%%{dlIp`HrV>lnV0;g5fK}ZkG2*QgGERcJ6 zcvLK5J$YjI{NiNPWq#>v`0?XohD4fl91@AV7#e(;eB)Pl z9qPMv^QP%g;Z5WxLg21YKFdWB7Y`4QPrbx!3>|zq7%!C)lFHipo=I|NbYZmoeVR|j z$pPrkxx545z7~oqlvP!kZ0=xSj8r?ZrQGBL9uMWej+*`P*s!p$to!uV$E*KeAE0=Q z&ZiE3Qx5I&D}Xcfbq$G#NK>GiwJJ}fefsq2e@-VK$kW8_6{5ir5fogRsD1J8#R|wq zTt~bA8hSBDz{4gbfXZ}8g)$V1L?eAmXv1N>@Zi7KGus*g3gtI!ynTFLIc$;s_Yhnn zLR4LsF)EQ(MMdSmUye(sk)1>f=JFGm^9w^r5#lYknB+Gx$@cKL>0;q62!0mt{m~9g z6a)2;Q2}8mbbG#2Nj8GXpyTr5K2VBEC<|(`W)FS9^rN<+hktub)=ic* z+XLavj}vQLa~$Vef#yRT*DKxcKYzu=TxHkxgaahzwKh3MrhW0o=4;+1n1P<%a;4m_}TYh|J`N?anBxupN_z&Db zut`Hjpqo=vTL?mHd2{=^<};#FIrdkaGMXnuoLxOl5w>`TM*RNkqSr`*#YL+3Zl%Br z*j-QTB_;iGE7Z!Z{#clwBoyl8&@)NruOxi`89&C=IDsrtUuBxLC!;T`+;)7VMj{bG z-%&0#Jjc`|R$cY*$nG~aWs00tWDYrPzEw=n+NAZZ;cu!5X*~h)TJvffr7YHU2S3Yw z!;*{WL1Q>H%AP zxK}`oU@K$P?4G>Ro@ON^XTcxzS1m2AIt_6wZV-_)<;&q7?Qi%`t-GG$a!4w#i@vHV zNO?&?u@EZ5Q*N`2vvxyRU!N=kv3gMXWWpHg{?{EVXkkaCZke=CHO^dup*o92#zE-j=fasXn{&S1gwk0ptMf zmWMUw{-$}SkEP*Z=(=lWDS|#l4%QjZ9RX1dkBRYB{lxCLV+aC{OZCp|ui34#vNGd= zT<)!O8QxQctiC_CQzO<|v*HY_Ez>jEcX<-8;gc6>j${Tg#H9V_)Af8}5d8RCZSMyl zPFfIxP>o8G&vCZP-WZ!jnsIbFu)db&G6 zE*J6fI$B30!}ZIBxg!PDr#Zx+US2>lB^leBi>Gy&t(4cAta^Hiw)U1|7!LK1^X!G$ zoAbIs$$q47t@)3n&d#;R06)C*L4TWsX>@FCks&TVUPEN@Bc;X6uVAXBkkC;1>G)2r zZNKvJ!*Gb|rN4ZgmjZWrb9+LqL{(-iOrypX!C2*HEs)}oR?v( z{KQT=RNVKqtgNh&krA*-{Zjl*7sP+7BE)2zFj}Y zqJcncoNUU=%L}lc{PkXl1DekH&IEEXa}kHt#@!kofqu>1p|DHpg1m z)4vy&goz}!I6c~(nbGZez6D1htb5aClc37^@2>v!t~(;o8%EE!JXVA<6rRln(WS{G z?CtO4_5~}AK=*rx{CmWq&6${g zulC9Uo)q&8MjXzc@eR@4i8NPMSMhjeT9br)`?FQ9U*49Kk9Xh~V~WpHtoU_7bkfq& zy98T$(~bUfb92;6x$ghOMtH_UPiOFZSoTOF&5n3(2~G*pkiIM>fr}va8Z5#)9b4I* zkGMFrvDB)dL~kNA*Xcw-@pxTXl`vi-l)fP z+FgPh(^Y(FnBsUp_tzExejo=^?R2!WSkWh3(H6_`=wGPe^6vcXl$Dj$#+ph-RP?Xa zVx++JIIL#AGw} zyF?RkA$H3t_s^fNyL<$w89@1ZFH9M6@uR&F^Uefb&FP=Me@*x!Fiq7`v$0Zh&9VC9 ze!+DkpcKC0IbwxFUJ3oEv|bckXq3ZGqIQbQG(rL`@G zb#+jG_VK*yH%)Is2uSBZ+&x$x0E-70C<+=v-$1jeh4EsxyU7t`R$ULE`a;w!;fVa% zh(>BL9bHBVI?dV{f8P8tji~U2r8(NL<{3qFOuB?cUtV_rh%Nyd{2|<9MvyqH#B^e_ zDO)1t`MBwb4f?8LDMFbt+lxBQdU>0fx63Q+(|xsK2TsVy5U1algjd!pKZ6J+3m%aP zpspFfWJhs_^1Z2-?E!8^ih14XXLT<-X1~gp4a%zZzRQ)kG5;vLWKY&tt(TZHPB}ve zIhO;&H!L^n6s98F>J9qvG?L#36)A=*gY^JuF@!uCga#bKDZgK>BVTx^Fn z?b_Ju04I(sWf4JaL|Xy!P~pUJ5=pyWJLZsr$gdz32YI98;mLxfS1xYIVWg^Z{`N23 z@JHj(Hv#xY84>e~+KKM9Q=uYlY)yTn)0O#NX-HxJb*2oF?A|#IHNzKXz4q;OFQeNh zLLGxY@Il>k1+EgQdk}vW5pV6X3^hEA$SO6V7WNF3iFG;V zVF9n9uOEdc&&(K}ZL;hS1MeD5Tbg8@ux{u&Zkslc?Cz4GYvE5C5}f&_gx(nMtfn|IljIzoM1hp46G|My>Ga> z*5Z9g+1ck_EV|S5DOkp!C4POGWhk>|cArKk6AP@nodm8oiU;J>H(PbXNvT=~++>yq z40LVpu4(HS7!U;mKIGafud~yp1R{{ifE4S4=T@zDyB%!Q{^dNLc77js`vY8BVrY?a z1DiL494tcwYLv)92Kn*h2MFtHYin9sS_}*f;&3_e9~=&%E)EXPlpE_sC~K78ea{>k z6aVYx?u=?yomf0Y`1mMBJ&SQ|g{Hy{7>p0LxwVDW_ep{3Wz^zmIa71nS4#PCTJ;L8 z`dcAUBaP!}cQ0;L$4D&ekj4X#UJzpC?!+ui!!d!H!r};80Vq^gaP;KFSuPlXU?Qr9?&F zg-IE7##h^|6I?!$aI)O1NF&$5#(T~L*st54b_^xZIXxU+V^xtc5|uc8b^(OEQUI#y zBqbvYNdP+BpiYq2$*v9#4tDV%$X8`Vx(lpty~1p=1kVB_h4%`>K6{l<>PRMr7P>}M z->~kX(X>2wYY4&-h@zJ*Eu;iLQ+_fN945sWC0SbNeP2>a3IK$z^G2rOrvA(9D*8q- zbbE0=R@0zZ^pjtQ|2 zEUAS|Mn-0m3(H%#4@bhYLT`6^%so83@KY{rIjQx-O;Ky8={@|PsvReuEBn|duLnB z0os7~bf?D$n_9mulEL|4_7`gg`t-t>Eyck4`!jP+f1YGD=5Z zgT%cSw+)4xQsO|NV51KB8RasINx*z`J-`JA zNBqwf7r|66qF~4VS*P(#=b+L4N`n9nGp&H~+sZ~86f zuaHCDQsXmEV_3!O*J2ZseK`m(vqbphQ~%yB+ESbEry*EerhL9vE}Y4|n~++9h7~W- zoN+8pbQzh8cYQV9KwCJDr@Q@n8Ga<`Z|~cGxONfqpwHLh93Y2ECkJAqW!^F+88U8W z9bCmRN`1R=m7B|)H#VE7G^Zm-GK;Ad*}EKFL*FlZ^|!7v`-W$pUN^1@QF-6Xeazh4 zw7!3LzhCnD29Ec@snh<(-J6$oi4MFRAUS262Xj=7f(0;m?iJS(^bzoE>BczjPpdDl z4!!L+?srRmn-%46cy1GIo?c{N{#NV>cYuqTjm3gMOzi04`}?jnbJT~^nB%I0Psd$k zij@15UuZJ91p^>apHAxN7Hl!_<%8(VF1>EEQJw#DhT$llF;5X{{CbqjUEqA~*-nx~Vn##k+(3)+h zx+kmr0`^d%`1~-Cb$d{NT90)&iMYLFHLU4u8L`(7fiz{PbH502&*4QLk%!?F8>ki+ zCtKWVU*jgDfEWcgo$?;1*D0fzIr(rLCJZJC4|w^{SX0xHrcz;;7(2VrWa0y|(4=I; z9|d5GUoBA#9l*z~>@AE}ALpu963jm+{?)UQ;t{`#5wU^0-gCys@!hxHe%apPDSt5HRx zgLjO)KTRy*ey`?^S$FD7s~uJ|n7VH6W;T4cy@|Sf0BgbJg(Ka>eYKOvW?KpsXPHRt z??tCNW%iWfqc|SW1N#l%;9~eakCTK{L#K~ z6Q^JKP-Sg1gt)q_vgLFP!-RhfR{7@sE<^G(vKD%}G_4_MB z^6$sGVo3$Ua7uO$yuFq@74sbO!%}8P*2{i$hJH>TtEO(yAF*w3luEf*EQYauCmWJG z8bBvY6qioH)ot3dmFW1ZMZ;;@bI!}u$g<&S#a`n66j^o43#Zdpl=8EV#v-fDG^@dy zhk6pKg%4})FH>fTmmW?Bila<6s_EcWo}wughKIC1%=R?fzyq>|f`cgyH?q7$r3o?# z7}-Kw;5+8{eF6mu_w-b~+#dSoJw|RtdO)u6@$spam}F2vI=KwWkabcnp>}~jg|`*i zekye>h_|M;&)gcGaGOtU|E)A!Zn!=+t?{hmo~;Z8SdVQtiy0gf)wipk$v z`?G2~htKCwIRlvN2prGy-qDWs+>yv=yeWR@jySZ@A1}?>Dpe{b{9uMgIsf%8sUJRP zNu%v&?E-dUV$ioT4brW93~Df0&I(v-Yk9d?n2o^DP}obn3M79_jdH6rzwkE*m0YXI zQb>3j8kh2;aV2H>B1BtseL`BaLeT0)TqMa9Y76pv8r;RV(O3A?Y{?s9(5JCiDR(6qt_JZZIlVE2^~#M(h^=pGMda> zk9#Mj`Kh9x3bJ0+nlRLza|B7T6!z?-0P}K9CMv(#z&~cg(Rk$#wx6pE1$Z@+a}nW6 znl8lzdSvox(m5iBZRxVf+6nF;IcE%g<`0SyS^zD8LPgk1NPs5<5{Au?{d0N}>kc2Z zcP`wS2@Aypv~AP%K_Joa7hLwQ@|58aTE*5?qpn){=mY7Sa7_5p&iX{{(dpdUT6}D*nxf*~ zn;4wh4o4zL1g)hG`GW9RvfWq=6-n{j@z%+vNW-WYG8*m?UzBjBo~5|$;+xWMBjH<; z?PqSGt=GxT{o3icWG*={3zIhOaO=e|wbDVbD$UIB_W9gIbof{`3#DcdZpL-~15f4% z+D(Z0SXHmKYn$ro`I(Z+15#N-I?aB9V_q9P-dC|PN2%e{?&AW{)yIa^QBT~iPLmmJ zZ!sI!_LgdN0#5^yo$yPC{T0a{UF?0cTv`AVs(({5MQezDuxVw2tZ!&h&X1HN!BaFhfNe+wJtedBa=*PQd& zJry5%alcpT)Q5L#YqVW;D}J@`sZ$VX4WFNQO(_aEn zLG0NzPseFJuAM-wfM=pG80G2HmnQ*9nkti%lb}0Mzpozv0tS4TcR&D+D>gd^2VesG z(y7CcjOIN0*R!87MOD0KEA|zMd$dVG@XT-^t-34gh_4NDSfFwwylEz{*CVgEWLAB^ z5%QDe?p~JJNboXm5M6b5(|Xe*^>`wPe_b?-appN>eRVZQE(28D0N>n6d>wL%v0I8oU6nK$E zT$q*BR&`T+kdo;DPN(*aH*^ve0cod zt(_0eTmd{aQVz6TPFe1)47Ihj?d-qC%Gogvg=PfQX>tAF@AuTFhC5;-+K_agxr zZpBd@OYgD=$_ec&Pi!jLdm2uUD=y49fIj;u3zK=Z!uJ@ zZ;|r_MXMH-A!<7YF zQHB)q>ALmZwK~kA#fkXvQa$wmSEBy%Fg(qj$!`5#WAhWMU7Q>@8(XZ^9v%w!a5mlN zSzULs1O_m~cuiJT7G^bTrIV#bWYnLsTbBVQ1%GXFmdSLIaZ<|E#1vL~S;2cp6rA3l zowv%kfDayt{prTmkk!ibk)uwx`4b4FdNBo_o$W`k*~Y!_jjp#U=q^Q=I3I7MQxGfj z8{QN-%D9i^Xq5MQFy{zBZt=;LexHys)62CtaCdoNS;OGnyLbNb$O|4)u3nQ{C9Rj( zm@6(g+E;~4GS{lUR{)9(h_|%aPmBO{zGj@k!YrrdG&J5O=469fis984PWO8X+vIA_ zhgaF=>GaHZ7WX;(*M7a5B|>wp6o?t+;#zzOYqpquEMi~)b>)Ty=OVr|XorMuoOM&P znr5vs@`#VMb)1irQ|=n}@Cy?yi1-V=041JJu0b4tgXmS|T^N$`!Z?!E=@tK*q;1imxPNe)`i*0>A1lcHzFcJ$ASZJMO=I@yQ6J(&{zn%MBnNxjxM_v!?c&W zQ-$mgXr&LSU=8!m`0gGJnB;UwGYnq!))F&r*LaOr?3-92C++>?*Kd`Vm8*)9PER;H zZLK(*=+1r{gQ3~7d$*_7tAMAZWj4JsEUpA4M!V-QqgS;(DZaPWs*biq1lbiP3k4<1 z;B7$5*sYD0g9Q%~)s=j$`mf@%fGn8nOaLxr3uK_gz)gTsI=OUg88H4hPCLKF(t9ox zh2j|sM=jKOz1$(Z7uH`KfTHQ_g-PBDhxUx0nD45>2~43C`>Xr>qX#zUqcY3n?ap5P zfMCrZ`^7zYN2OXa!QfVp6=3B8Xmh*iejeG}y}kHwJg2h!C-*u!oFvhfIpdEuH?CH7T>}%iz1~L!L^U)hX2|JU{O6qV@`iOV2MUDK1Kj zpd8t|?bSNF^)gF7B4_M-;YLp}Q2n4ILlBI!!4cm^Qa!M@m<3{RUat%l%`@y@)F9w% ztfy)#6kK@^i_^pQel`!Ah29cx1=aFgvy)z?9H`Uni+N}&38}a}OFo08OJ)*ft8@DG zu%3Dt4$7_m&McFM-P6}9-3z0W$wP2jk~(X9SGi}VCp37SFr#QLGE%OJD!nCUu41WI z{XD}GHrQiqZ=e*su~ko4W`xL5<2(iPTf=_=(or&uTi?%p$~VQW zJy?S?JVfPHD#-w_yChr%AXX~p{?M6EO%fIg{dFSFgSM!W~^K!i0CQ?FHif1+~vW-_mj*hl{5f`GM$XG#-!e zabA!AR_MRSd(o5ojM+P1fB9I`=!wT6?KG)Pa@K|-doM??j9QafR4WxN7QHXimGDie ztaQA_ZCNq-Jo}$>{64CdGPf#OTpjBrev0_!G4<15$%rYCWeoEv(BNIrP7RTXUS#`V zqlTv}%Y-LCxLLAzDmCShy}W8DTru#^1}SQ(rl|qPii{`T~$7C34qqS zxbGbaU0RK)am}AXf>}b+U4i7@*zNP|zGC$qkq8iPDNgw8Vvgitq>gjl+C_3q=`1GNZ>b=^-gURb8C!vB_fcg~$ zUfahfGuiCR#{Pb-)hzljs@~D?fs$?@o+tTG|4{_u10HKM###oB!xR0_8X_H>UqDf1 zf9`I3T7vQZi!!%;TGy)Y%0jb)1v)_ShRC38%6QhXJf;{z+j%L5omYhGvzC8 zqi8Q**|0`%Q_j_VMLXBm`fiwY`KrBW)l7^!td}YPwA(K8`LZm6fl8W`eS84bxpp7Gy*UCi zt@{^WC$@2nZ#u^yHH_09Z4+Hfwmr*a-toJUx_sVqleoJacm7cuC|aovX9?v{Po>}t zWeBnMjn?N9ubuGp^PCVp-VacFXII1T)xm0p#b%nSKZ(_z*~yGo)3-LB++LG8(v5c| zIV~}fkcH(f2oT4|%Z^`^X;N8${tf^^5OLlH3>WH2gz1;|b^a-!USSRbjH6ue;Gi-c z9UZ8D^YMy8KYjWn`c72G>izPw4GT~l<$o~`5aqM|%j(mWD@#8-FmM4wET#aI8#Y-s zx))jletv!^ba<@EEE$`CK)T7%$ti);F1N(xvW9o%Lla+C9}wMTDr7FHyJqL)kPs7t zXVKHs1Ewl|r_HDs`t6ONurMgV^cP(6yH}VW?6DP67J+(-4)|H}=Mllde60M^azY9~ z`q-=iSZkz4F7KLjN-*D9)Kn9AK!PKku(+Pl1<}u|ptI845rv_x7pmL~E-=sks%# z-$E-+&)4vilM~R22F?T8M+^*%A9BC$xz{u+yb?nbCay9u zgFqkv-d&z=_*=(qD1*-eqMRy>ii|8(d_orh`)}r3Iwe$p<{9OC9%ksg;s@1$ezx*S zb=N;r3EWl&8jvgMsJs3W1GRe_p@xo*fE6LQ94KIA_8HYz_xwFmI}s@dg+fQH-E*MD z$WU6|i?s~I%M4O5l$t3fARl~lfpXgs*#J8}5daexvlp%(6pqJc*4xb%B_$FW8mhBn z_v`{_0G;2?8z`+t)xodD+v}s{I&%LxAP60_cJDhT1A-N-Fh>~?)EYyH8B^dNk#(sg z*#+iSB+~zRmjEf(WbF=e6O&i`0_!nV(ev<`@x)A%F7Rs-;WR46MtuXCZq+WwdjekfQJD}gujW58s__dXvBR9Uoh>%e z)W1?|%W1QoXA&jp$y&{+jjY~x!ql3pmH zFHg2mjvaBe+oc!CokZGrvpO6f?i0`(&ddxXdsZ1LPTqOpS}eOyVf8KGhkD(yh}+kS z^5O`#oPv^qMNaxuC*9iI$!a_ysBj>G`o6V0z@`l@awK3Wb#m{=F31M$nvPXqU(_|P z>lGR#y}hI45YK9)5o)EQ)z1uJL@^ zXH6Ce%kv||sO2N;or{kjsP=52laN8K$z?E8P#A8_H1BXu0;Omf8$syLpMqqh#ha5} zFOnQlN!68wKt#R?mxcBo8g-=WgJm}ks)eT5Kpw4Q1m@K8QUR(s=rYw?9W!3GU6vBza^v_0!wr z#YKF)()9=yRbnx;CgEV>&=V}bQc!HPZOg~&i4qUis#WW$GWc3LPmPwho;POt{F3Au z&-Z9XLF#332_P+R2?@teD4I{~Qb;Wjhwf;F8`KMB^`*k$LV|+5%7a)>pEg@Qzg$m1 zmAs+TtJ=ct;tbTB!^4|U?fKtj`@C#7PlH-?xsQb$4v*g6#WLQlZ}u(XRsNCU;chVH zXQ#{9`YOf4q-iYq-g4sOLzBC4R0t(NKx4=$DwY`aWq$Z@Ma%OOl?Mda4j@hH&Mwz| zA~}+AshDjT%_AsXG)0cn$qPJek9a{z-o|Q%o?3bODDSkq^{w5BZ7G#p-23*Hk#&uY zjUBW=WoKx=4!*JQ)Y`UfqdRvkr`he7@3ZRt2lkS*YGn^_aScpO+hCgR zKT4SlN-8S33C{xEvb*&hXS}K#z#Sku^!H z%#%w?V8`#wbq64dD(M6XgE1HOpBb-3JXxmcOnvi+)bDP#>LUdbkw60Ym~g;zl@Wk> z0YJOx?O-MbV2>)SWnw}z{SK&@bK7tHCczvn&_NTE#_v)6>%>9bkV37(IzwFQjkfj_ z@b@paH>R5cC#oEZ0`UKOVNk9m1d#}&s^Dfy$E8f^kun=RT4_he!J(3Vrx1bg^Y;fB%do@vKVqi)g+)a`cL2)V^e@2;Xak+sw&tC` zuAUIWvbEjGyWD@nW~n!0$mr9*H{^hfCcF?r_q4I_U0zR@HB!6fi9cdycJ?JHsY1q` z3ftA_cr_p|KrLMq;`h3b@8j(q+^oCu=;nYKZ}eF@QoIf|9K%~(IgNU_B5Pm4h5A3&o& zv-IRCXaom#p`f4uwlAwuCvUO@n6$W{z(F@{%Wm8Otxw=W)BofVoB6n;q@=Z-9j?(Q zKmh=4-_Bt)0ApTvpMusKVI|urPOUt;@$Om8)5Tl2MVLNpl9~_X9lSh30`lMy| ze5Xfde0=<^wTGmqpx!{P`d@EmNC*rGH;N0`iph`Y#Qc1EML8|NkSDP41du}YtPwZ4~EHd5-m*Y!)%oXNb#Eyf0J`ngx z!bXS^qu?mm4KOge$0zQg>gwvZRDGaKcW-m<5J=mi?4n{~ni?8Fdy142R54dAqmt>b zW!&Y5BA})~sS6rioNSAt6M-5AYW}6P9q9J~OpJ^L1(D6~AFrEK6Y5ku?q*s65!9tk z?WjS4=>r@IWOD8Cb3m^r4&Q2vV!Gv6pWe3wwx8?oiFyoxk>zu86TKIq_uBqJaRR~N zkI1DL`fmUO=q5Sqh~xBhDqR_?REku11@PF>V}BF-D0g@FrKU?wHR#5fNP&w>1u4@6 zeEA|OA<+W~rf2_EJT)~1NY#Z$U}c&P=6`D(18JU!84wlU`in$e!oz{42V4s#Cgxal zVo#b3-jP&DZ0yR+j9`K&StwX6k8yDaO6GqBla!iIXiS5o{g1l!Ga{DL4y=6X^gBj9 zss6yXt!@}6#`3yp7+T;xdlnrQ_ICdaxUU@3M}KDo2>1L7$-c-cDuU#MFrszw{m{q= zIXO97e)7NP2tt*mf`CAoKG;%CZIlFq_^t;;wIpAhmhs+^8sNsq^bF zaXn*WiG+@p79U9R%*BYu*x21Yqn({HrDO{;&7qCfc%V*k3k|IZ^9ccg zD&-7x++Jr1E(WgmRv?tdnZFzTbCq+A5iyV3gkV;mf$fi4pP0QjH~&)SW5=|^4{ ziM8%W88~4+(Oq9KBmzm!@XVrT|2zmV`2(Ic1Xc5Y@ht`U`Jv| zg7bc8o*Np`UVyYDl&mv;Ul1v$rj{+20myLj-Wv^#jRaiwT?ejfpcf14);pjaG4$-b zNJKHNw39%Nb8+$sUV_er0+!>vG3l{mYKWj9X3Fk$jpvR1bSKBJ9AO6Q7WDgT)IC`0 zW211!s8R7rKmogKdLceL;n9uNJ#ZAGE={Olv{k!Zis&^79RQex zQa0;`|Ip(8)BI;G4Tx4-=`nz)>iRq4?=Nz{>zY==>=sZ15}1*ZqAV*L8!2&dDzHUq zO#*w&X3(x{l3P}r{hvz~euJF)JtOH9BKt1{eJIXxaK|ktN6chFZzhpw$LiNFhAdWd zgFQxKS1NogBng*oo$m0*o%-&EFxFuAyU$pCG(yhH95$}UAK2V|k{ioU#owAo4nche&|7kSCMGi-6vP}e+^=OLE zQwtgxn;d?Iq%d7XwzQrTs!w18&PHH*BQ2A&&G{gZBp7rDtPd8{E4y`pr5)h!uQ%5P zO3z zgKi0LV@kIn8im`~tgIt!)IK;-_? z=#V(`D|S>bd}RYfp)`OscLGyP2mxT<&|&JXhB=pubCv{#69%A6)#ZHKwz9oqxf~do znZKUqSJ*7u0+bP6fpw9;UjfT35-W)QhV30ai2CaD=N{q-k>JPSie-#Ju-R;&r93h{WWeG}-tS-(IJXBEwSJEfCe7p-w=4eM7niWu$P4nHtUH~71R~}S z9}laSI;NY!h(@&5rH!pCAKrV)(WnattqclwjrCxI%u%q1>=j8tC@>XaAjJg|L#%&* z^4Hy`QQ1zxU6|4Rppx_d6`^`a=|0XDLU&ren!~$ z@w>4Av7j>%?5$6ngI0mE(u?sVO~Vbi=hwz6+nJ_`z~@k{%)K%9@L0>r%Qs1GsVY;1 zwIn4GS6BCfV4ZXG3NsKPKIbY&N%6Infd`h2+@zAGAwvJ?Q5JXs?~+ zbdWx2x}6rwx=LOSc;!|*s4B+A#Vz6nD^LN^ZrA)%%nKdk)hm%?xU^~y^to1gGkSta zMEs7o{{R(wcCa%rpu@nZwzjsOjNmHZ4WSWq36IVDQ~iG-<#dh7(HCjX>>K2zb~H|t z59X&o82mgKCIWryp(xl0T2@UO>p?{g)Zn9kp?M*g=?&tIt_MnhJS5cB+VH;D7CPDT+LON{kucJoUe(8DaZ|DKru;%Cx_wwiuen8+5+*L50J=DhXX1SWSI3L(S2nC$M=a}Xv*f@ zww$NcR=mw*T2Y=W8yV&O=~KhikJ`5JtDJDe;;4{BA>r0S7rkZanzjLMu$xoOg8p}= zDWAztf;)6M-yWY6t>aPZ&u?!0zUQ8}JNwFB@0Vw9HDFv^f|54b zIn)?pTwFq*b$%Z2wHkd54-8k$?-@VToaHRk4pmBv#4soNx;i+tNry{Y@*p6yE-iuA zBY`sI=7(E6ZzRK04__16?duMw6Vjk>g&}rw(-}x9tNeaD4c}Y$#61kbL(-eSq|M~ZOw_vcJo@MKF`3Kda zt}^vXLsg8yc9FBqGTmh5RY(C(E^?quTpjinZ<#%(4lRY%*RJ3-kNnEvuMzfMwJlZd zcvhdXJ{41WH(*i*tGiMTdjEOG4zVMhV>v`UQ*}!|264MjAO=b0wq`wK?P+!L8mu?w zgO7z9>&w6)&;QOR@IR1voujziVV^FS!5&aQb`u8s8hf}8WHW6V?zEk{bl7o7L4kNS zUzZ`jauIA85xk&iT8Yth_(x1L9h$B+!TFx^qli6xD!a-v&9n4HrgoJHqe6VeasF%d z;{&a#q**}^Yi%)Ee&*0Z_)#FQH#v=+S+dP2Kr~_Fx(AB)08I@;rRE8>wYBuqlc0^u zQj-t*%*CSITfD}YiQ{^P<(qtV2R*&%pau!Zujis1M?2Uu4r5gnh#>bMWY_(GfF$?} zh2e(TtZ-87+?<2%rR>3cfUr0>huTJZR5l3bR17;A z1zcW3B^9Bd8W9&8>;4oIlzS{WQHt@4W-DI}u~yJZ=J6C$KtQ0Vu+W0!zlVI+{Ji$| z_Q+5k@=rc_R{{#UGc!1+wZPuuYk$bVi@gH?t8s^k08};1Cu;ER?*IJ&5Ede!IpXlb z;$nDQPIfjZN=RD#8!bS8;&V=08d6esmNGcq65yfAwEmJPNlHjLkZIuJHtBO&gH0AT z|8ec0uN_%vIW4T!C;*oeyY~6`ACk-QB_x7Q6Xzm%V7K2OTmy7HDp#a8gQ*n0dP{>7 z6BXrBrG=ro?T93HB#CN6Ne&if$tO-953;m1_V@D>7Zew*BblaJ6EM-e^8U7^^Bq@S zbfsrxz&+aS4NXn`|6a`ZUU6u=KfaiOt(DD~&15M6KqjwC4pi0)b8Poc+KkRV@{vrX zIUa3%POv{dERu3NY%0aU_7?*c^?!QP%gDmQxt;a^_bMH^iIN7DFzdB${W=8;d_WyRE=B8YYk4M+WDSF$?T=fuN|P zqto8jc5ug(n;X!LKC0I)lQT&vCs!6@_BVI^eqUmsjur?n4n6CpiDl z0M{NB}fzhaWe zXq-P$h|9JcW(HVt_CKtYt2E3}kFCm=xXIXhjeDlK&_=ee>_!v|&ATT{8OJSZ=MVq? zr)!3ORp`Uom4ovQG5;Md>a~@In7+mapW{8(XBZM-7ggZ#VI4gH`ooq?ixt@nE;KpW zyIj2R^udKhE4j0mW(dXe|T=zhO3cq7c0?XuLB0847_N0(k*4I;at(>8Kn^TTmFJd4S#4JKpYzh8Iffgz({(VE_cqiYL~kG?3(`jVEt+ZK6OzWKY{Zpqi=%-z7? zIVDBFdLPtn9Czu;2d^tT-@IDy7)&!%Z9ygH!>|3Ae&=H|M}M(bcpj%!nkkKB~x}4E34TDf;p7I?E?{*cS_^ zSXr{e5;{(WPm+q>et@Xs1y6XR;dV8@$1q{?#^JAUi+iu=vYD zWWIgyf{>}*e7wJOuL&$yM)K;5c#?UD!VlYToU9du!~<*MSUnn|Fh7#*p3OiRg=3Z6uKMsJYZ zg@l-a3p+fkHX?mFIc2Kw+O)JU+@Bj693nnNyDkM?>k%yCJ>;E)>_apS%`30% zI18e8DLFc#`(F9D1+&k_VS7fNX^CaP0c{iA2#}vE8 z`Yl;CVjcbL4u&2Tm* zSJB(B!bq3o^!fXfmrv>TWm%YlR+NWX%|UvIto8Cd)Ky+)j*(Pv=|BIbCTbUyA<>3wx|X|Z3yv=@|L zi)D8{<$C-%w!-`7FSTc0blh!Q7_JiI3D)bjJ^~f_ySe!-@0YeeOC#BXerju?jh+){ z)?Lj~{KR03L9-QE(TmPp;Jz(Ypr0FCHWGS}f4xl#^_^s?QB}In*L%DByida*mf*cUFgm!)Y~v)Afx5W zQ_bV+h<`vsRNOrC1ajE(_QgwMze2mRo|dDu`lpU)gz4G+!ZUa@2eLEz<=IdwlY`bE zTFIgz?!sou{%zLBx8(gE23Em>)=Q6c1E))svXiM;t7t@4sFaNd1=8d$(;@FO`pZai z^1Yl7-rjjScU3QTG^(|I@res(tl;88^%|Skr7=D(V%2=BAh0<^aNk4U^eBofcMb__ z-gM%Tk5agE8p~s%r~;6E@msDl5fae zSe0=V{DLER+Wo?<5anHwJR3cIC4=C1FKrd&0gC?rwpNsz`?7N}p+7P4|9&a&`lMZy z1~Tb6{;i@p-)&y^orkFJENnL4DFaz1EEeCWIEhChQeSR}srGYof3HgQi)6mkFffpJ zvE|z8HL07f7t&sS^>g@e=_yGAUl93#%w?7kn)~$euXzQk^4~1G)i_)Znl!*@B;`tI zy5_DP=$$QmblJ>>cx*y)PtVE@Hdg=SH~%a2|2O){jRP(*TX*wu041Y@>Fa~DkmKG_ zS_TJeh~Zx%m$eUy_^m=4@H!S(&p%1Au15`z_V*WCskg8t+}9gVqRh7TMWi>L90eDK zod3n04Do$8la|f99Ca{!6kB^}?aYVW_K@0q+-DkycYS{0EJzPurl#bn&=m^wZ`;~3 z&n)eaURe8IlTbu7l;xb}Fa>WW@vg;ms8hsCoWz!4&hQmhBI`}B%`#`)%E#4L=TBP)$^T;&==Jde4Q(iQl99_Qn3aN}?ta~AdMf&^}sf}GvE zbvL(Bm0U?U>^!A{4=@Ev--LiU3_tNib zlyG;c8Mw(tFNH;b^GaJaIGmSO1fs6FNuK^MT5~Dy-^~zzLE8~4JGmugGMqk^5E-zT z1YVsG6Scu_^tLr;Zn|+aujM5zJHgWMAFbvUEaP-5_HY z{2SDJC2T0b3`QFOTL}sw5>-kPW$eOJNbs-YSkxmc`h?l0>K3QN>W^|V<=x2|T<7Vj z$wKE7Cy?PhHKh62qurM~8KC?~t_-nOZ^^d`Y6{MFR{%*o>n$Yu*;Tw?z0i3rUch8iLsrwto@axQJz87Dpdvip6Ti?=|U}P0_2bnNtSuMkT&o&aqxx zYtaCXgbrQoIU9@Ezv6A8&Ocf9bv-HVmoXZt~S@_?D4?S)i-NT%Xp z)@-{!G9u<_T8xG|uZun87?W!@`%BeO)R=>Hr)0ruJqT-tqD@!=(`_#|2zVV<%0g*@ z)fjRgA05}V8pInMkTHaVg@q;+Ou{sq)AH}k`FXjXOj%20nCbn)#MhPB5fkE1i$B|X zz>|Xv$2M3Fz2pRtu-$gdt>FlYk((5Z@4et>r$<(6^AcL3<_Eo8^d19}+sFtB!IhjC zoQBN@gPtBG2fpDm`|V?^+gyjZ?EvWx)8vwOuW0svU9(Y467XJ{+Yjks+{4CTJ@qQ= zv`ZX2iL$bpq(|^;>Y=}j=;%^R+ILoBz2+nBg|~b{s((1UZKjeeyqD~?hvwFIDqD?> zMCj9=FP_DZSK@Pv`F}E42JH;nTF=i}i9eH<)0yA+pn&@2Q79rfaev#Npso;+UJmixSLnWDiH2BJ={bXg=jXAb-sE?Fq zW%%!%KFAL=h`isAj?YPO_ONtA@s@GYXsAOLXet};%x0MsF`a;7QHJmJo5Yd^@{HLT z%RvVp_aOXx)KI1S8mYR2?VC2J)fEd1PUgi!6nh{@Uk~zrlyJ7!Ay}8#SyCSp(s-X& zn}apYZ$aUQVh+=@a;Kdxgdkar@q=?a~UdKkDo<$M^ZYfNJP*J&S=hogyOR0%395Yq= zApzXw0kx?F{>u;GCBGLgsL+fjE2FoTXUIaE?Wq|&IaYQB8%C;6rY}>=B%tZ~JiRT< zUzE&?b{$;h^wK)kRjcex>PytRT@yH1dDl+a9yD=#f^t5`59__3+;O|D&ubMnU(a=< z#xhJ4$BB3X+~GseO+M7qHoU_3Q5!iQ!tTC-L9M;8(~B2zR^xb~sU2F$+f|(ULr5e| z6dRiyM~;n;@Jh#)vs!np>@OBCwZYfbwJ#&M{4W`Xt16ruU^ZEjO(CV?4Cw95uO<=| zh4HgmQ4AcMa=)_yspVg9DH~xeM>xw&zpLxv1uZ!7y6g$9nusz))<9vu3&_b14RPV#Cb>7IAi$RpZj$hWn-~ z$WOD4Fur%_3N1*uKY~Kii;W`46Kc*{8L8H^^D1IAs_frZAkufL1m14cpUd!dV$=Ru zP;r@}ueF?kXEKHUGrPUq$rI1U0@7YZWj6A}$#PIpR5`#?6mt??h2aFcW9?H;G>DuN zMh~%LJ$P^JV3)7QV>3rIEp%GE15HdXsv-YV@Z{VIL+H(^Va9;O9zvT)%rZHv6tHd$V&IP^tXK}QWNxw_wRYDI-x zZ|7EM{aRdHBqyEt9Grro`wQgMy;-R%0e#E$D&87h^{)Ac)~5H-w==QX!dUfc@N3#w zWg6ZZjOsC5G#Lh(g>gx?CtK%xE@wKW@vI->ppU(^MKQBl36Y*AL33E?p&H`fzrSU< z!E=1>3GbkRd4Z&gd=P3OMst^w7P+s%P8Lp%;i`q zwmp*;|6C?lL=hdt7Tq)8q^*!tQAAJgizThb`rI^K;PgaTlX_l@Aj$|*$-#|Lz<{W3X`%P=B)KOD%sFf4;IASwIPUi~LJ&#qi|3>{Q^?-f0; zhu_drX)c7-&!CK$IKLSW+IatXbInU-pQBmCR(jq12pJJHB^>$QE)S!7?lQ*R9(+;Uv6jZqR4E_%!{EMQGk z$V6oSGxE%3pgx$Z(?rDL5~tIcvekg7#jTID3@pU#AdS0cxrbk)e$oBP4VazZR zfo)6afl7evV9A>ZJG=hj0%hDgd2@~&$nJU*Xe~>*_q6SjjRmnA*Eo%*^6P@SXIlsf z&yF-{MpCQ|Gu-fY0Gxg7{x;L)T~`8>%?AD5!5%VG{<%Wm!@2iO+=0x3Nk>_XMmDcX z_QiYpkAG*xX!tc~t(r_DQW$w9Idu`DR)U!u8%hA}FXFB#j(gR8MPq4$4^z335q`1lD>^3~a$U`v#A5hKlaeIUk%*d_ zib;?44|Pj~^3T!Kq$NAE08YBYt3}7T-`)C?f19SBMXmFk+l0Llyp0XTW_xfz&-k_8 z{H4=%7{!{UD-4W^Ms=xAA^#gj7!p!uA7AM@vIZ7HWC2i!4WcftkJFTH9L5f9pb|Z8Z zRy|;Y9qx8<(^(2MSwHoRY|!x z3fEQZz#Co<6K_$%bfs~@%S`w2ZJA3;F-uFCz}75=8psY2Gd-9Fk>1Z{SmD1ih+wZ1 zij{pD;Tos_us;yhW?dtA9vi_{@;np>OT|V!LEf^ug6fN7wZ% zHd8j0&i3+;!+- zh=bq=alul)4C^<7!LG?lAS3D*R_SYJ7wc> zG|ikm&`5k)-b+$~#WB^Uk~Kt_1A@9=)nqWLr!@XYf=>VmuK$%_V16=y4ovt@=YDb%y7MY`v-fw zizEgLBnr)YATV?^ws5&DK*JdDTy{Tszm_7vbte&kTf2Ao5)Q{14|tsV^ngG@ItLkS zhCw2#DX^YTKaa#ullZ~VDL;0aMp#}EEld?(nHckrmb6A z4TyAOKp2ES!gw+c9_jwlAaEKhd$Jzrtr10HsIa=~0of@&j&TzCfjzqtgF;BJX~$j z!eBu+=_pL)NA)3oerlQDf=}yXG?sZ)2BTa935GeL;*MqM6S>Dkx78FnWj`}%w%q0H zs)#g*ft>n_8nVSIB-6{Zg4-zw-rU`ls}BWfHj{zzy* z6r4Co@XCNBd?kNX72na1bPrTl==2cM^!XbBB+)V85Sm2w!S&7dsS1hq?iV+$<&50Z z$-;sUs1BD8EqW10+f~s%7A3@eaD-Rrarw+~4cQ-UVAL4Z}H8dFoOa%;{ zwjk!B{dFEnIL#p$u9~gIg7(wm+MBr8uDcu$*+dL=8wHCPBEIOVIrYA{u0F!F=@}Rw z>jK36#%WED?U4wciA#p7?O>4ON|`cw?aAa$b!!fjnRsGu<6obXhVULxej_3l+db9< zL>apJlT_d-bz=?R-ab0QN;Ka8{;@`c<)WG!BK>h+6=BlUr3};~oEL>i59iaG!uV{? z1z)1X)O_y$Wbh7ion2>XJ0R5Y{%u`_XX7+1I-MdHVO**NCRfqNXdIjL4GWHyPdN^l zQEaWjRJdzg?RlKN7GGG3_{!;IEvG}#{s$DY@M6(#C!BhngxTE>5FN_W-Mmy;Kpd^W z)up7HjqFE>RQ856l(~-~BT6@7HTV*;e9AtZ>i{LiDyopl$_+$QC5wW_ek#01HR`^j zy~*YXE#4_$x`QQ)vbBG632(SExG!o>Nio&5D7q_OH)!w`k#4JVAXrHL?Cv?N(J9mw zWu&EYA1H1$oEwhdVGR9?O_Il_brA0+wz45n=kZxJ1~?l9IBA=cPe0w+scs+YWp$H! z+cp4#-9}7b`Xb zl#x{Yq`dH60_&CJ;|-8LXvY=H)=ozowL(6bs=$#WVk0NF?3tm6g4XTK$1Cz0hS52# zOy&tt`LOoR=nj_qb;kfj5y7odUVEl8Hb>vuVzkaVJ$3)kqw#?<-mq%k@2Aeen;JyP zV~D799+Q7T)*dP=AX7#6t~clea|S?=mMLXF8@aw%D-PE8n_*Q%$;WB!Tx-e+KyH?- zPNBj9qW`QnVkOVQJSi~vFbe0 zXV_a=F&g^^Pl14%^3tonc)9s2frZ|^Z8A=)h7BkLR0;eo4$OpYR_%{o6vnEDj{>~< zJR_`Q6uf^2tj&=lge(jfzQ)xym8q+?-gpN^^IC%==QpfqVFgc5$`xGYvU=_)2R<*U z8Qdm;3X|xpZ8pb>I3FI7A+mPr0sGQC`J>0#PinpOJe@zUPY-`hkfJV&8Af1MZb}Y8 zE@^R+aFUr#WIX^v+;C^!r8B-*!E&Z_N>}?T{w;cM>rt#fcq;cnf*jF?uW?B2s1I8q zuS#l^>m$73rNMmzPoOB17r6T6wvUVQNw1$FRgk^{Nt^|h8_ut?uDZ@hdC_1lxAtGM zNco(?E*T~MGzb7i)?jhmsAX*;@g{4ydk3O*B*G9*rM=$8OZ)c5!@MoC$qy0~L>;Jl zM_iWkvydF79H!{pO{O0)HiF%t9CkxWcZm0Bs)J>Jeje~Vzorp7Myjr|?%Vn`m zzV6>Wx>!y|TIg?J@vf7N+z*?a{jt(I2*yN`vLj4C&WS-;%|`BL@IJW^kcwYl1^rYW zM-7uDP7bTi#M+Zj{Az$RgB+EEl;K{%x@uaF`d;K%pX;Ms4in6Ud2G8@IPy`is>tek z?KEe%^p9mACIN7qM5Gl0SEyaN!s!_6G+D;e(5mUq(eYOhinVYu#S09$47O%?ET`MK z&7y}*DEn%P)ZcZTW5cC`$nJBCsrI!R_1>7KuPkOY;RiRS%_N8r6&^*pOBi_js1TTb zo$3J~NG&5jvi~4LQvqLv5Y*~Uc)pXKzj$74E%UE>O4S%cRdK}zj-h+mxpCRSZaw?A zf`0U7>|aCG$ewYXwYL5&L6z*v>cNq-mK0|}-0KtPYIznC8ZvKlX;n%6ewkvpoH@tJ z{`l=nkm6~b5?qM}2Q$|=Sew&a?e;;soI2||)l z5B!=R>ZyqN5(#JaeD4Xy;(2VCiu7BD@7Nes6|l^H1LuHN2iUj%%r@7j|U;lIA4e z7=LO^6|vIZ(DxN2AUS#0_3H6jbD7utE6qqJtpuP(x_XK}5z5{>t5;qMziRj-V5+j# zn9J$I06II4?iJCaSad z2otan6wqtOIkWcJjy3v#=L6v_aWB{Js2w2h!O|@23qB5gWc~~l<$4Q$4u2?fqJ3p! zEo3=xM8bYe`|Y73Yl6hghOYKW39e<0B(<$fDUg_*@xNKWMz(>kO_nKVW>h*55%&X{ zWFa8lrHTv$Gv>tm)?0<~yXDe^pWO@fgov?^FWunh+tyAdo9pe{$D39zoZ}7mr0f}( z^3}xW`vr8O$~iW2{IMgOJs6i5BM#Orq)liwu0Y?g2C{qNi$p6HB@Z`feKqM@aTdIT!Gz_4Qx1AnVe-z!3(Uum`} zA9E%ltUVi)%Fl}^?`oDjX{b$DHGu@(({Yil@y;g-d3g@215yxSXVxfSSCASMXXDA3 zse3kDKJCL->D6yIQ&`12G`*NNl-yH0+i2@?oCOvZTW_u4sAu200|Kyuu*7K+3C%Sf zH6Nxv6wzC)MuepeLskvlc}~zr+#A?c%mm}|G^9vey|;)whn(-%s};oQ!gWE|hN|0x z8F@^u^}_DjGdw^+$LG1FxBT!MwZhn{D=xi*hP0CjK(zZHwW58{aViOCgzPHx2s>n! z*=(CV9E<ZkgKaU+RVQqQ#4L<#1~T+Gu+_1-N!rfyVoFYXqP~b_U6yrl=|V& z=Y>0YiEATMkHjfM61JMq)fL~zaidXXWr?HV2Aj1>JewiQTnN{ZG2akVrK1=zF!f>Z zQ9-&!3?h9-j`7XdB5Ga=NUut? zv2lrKfO8I=>szDk-#uLz*Zv!{AE;LJiqvoNRwAJF6Xnd~4wVf;C+o%fJ(w&r_xDvU zKpNc+BdiA%bM9EN8*!|hEODGGPp?yenZ)H zlG~%Ys&h73gN@U7}%p9cc>{6H(^gb$u8B@B13I zlh5Su_5lb&3ZHwV)b@8jo7H{++9W{6b&H-*Sli%IEaNyHl9&2s`@O}|SoH=j0)Fef zIO6un&QKZ zSP$3=J1V$HI}*J6IzP89X>10PV{;DT1;iU&PWjW6$q79(2aNy* znLU{WGLwBZ$TDQh$KK1RZ5i12mvO(5y|Gul+snXuQS;$-G_AmXlJMZTcBSd8U-a1k z1EwVEn9RkV0_zHwSd2%ml<}+o@#|*xCO9oFt7*2LlFb!_+ZZ^>V(#PcV zFg(xYI5w@xaIadf%PmV+Zzt*%{h2bPH^|vOtN}kZ5t=K;<&;79y#pu;AN@7UsA7$d zhXIVxaUJTfwbnaIWw-=yY-`CG-*I|=U_5-Ow)E{cAc`2QSu6k6FZhm5Y_a-UA43KI zcCc6`cv4ubtJW*rJyG9?Z(9z49yZMbr?_{*UVWwmc0H+Sa^MfNdz>o4WlsV-4ONq|wfWA`5`oj**TP9Kd1-D%V-cN}k3 z{aDJcmx)N_*pVONzT+ zrtOsI^VxuDVK+escc<-c($AmVdI==qA)Kv5N07+mpu<(5)fZfvG|ivj+>jfKVJeKe z%zGWE5B<&6Vz&JBR+?M%YT6CAFVIYiF=PV zr0#X~Dg_(M2^}b=m?fk}dzc&Rv(}QPG4Do(7j+fKXl%X0?t7Yu#e6blM+P`aCk*4V$xeh?|LPs8B|k5t1pv29{i0qJtmY}1%!gmDOTS#! zijw)03_LJ$6BFBB5OSuA3%~FhkxrIigVB<% zv0N%G=AeDVHs&o?Uv77V{QmxyC8k>+=awF8d)Cs;xCa#(9jmM#9GLD^KlYmZtdBQZ z>`@STfbd!`sXqG&DpcKYZve5bMeG3>h_G~uw5g$lnEWghaRP^fL{!<*xa4Earbe2^ zl;}@{8l3A|qut*9TbO^+52poJE&8eN^r{|jc7!eHHeOR4lU7vU!$3hdBTBnWR?>U< zFWQs>5ZXEl{|o5r?1R+Z51q13vT?BrtF+T$IiP&_4gFS{22;;(o=cwOVdwebR5ZeA zh{3&pzf$YCE3^H)Ykw52?x0;Ne9#Mlu^-hmNq$r3Fu^ViJ!ZfRhhuejL}OYLeeH9o zv*1au4uGaGGpasitz%iUHge)TNa@AA>9UzK0$J$aUGbY})La3IcSjo93OBQA-%ch8{4)m-@C}m)!ddVx z9ed~)wD?q%|C+votMhWz?OiQ1@!59^^e_hk5t7uxKx`*HRdd9Rj~$LQk=^e;MSX`) zYE=sN#iCDK@Fu%AiC-$y@0SftVf*!HA#1b+`=o7V6Xo@U33K@+43r({cNh>z*ZL;- zHoCigw$tFRi z_Kn|NfchURn_zo-ET$iIVaLvTKh-#OaDN;Ct%Mt(S-ZS;L@!PouQ&6A*YEd zCk*44;HPgAd5$t`?{XQS`$rR3eGH3WK&LJ9a(sfG#P6JX-0;TI(#J*uoWpZxy4Au* zlsLi4qmmy9{|MBV3PJRi7*KoyH0#-q+jXenL){Z^8(IN7J1d3PeO{F%M%W;x#yAiL zw=$GP_Z)`bqk(L=J9cz#98}lyPpMCzW@Rc(UN+j;W4+BBdJ@Y`O~+@y-kL{2_K8}M zAJG~769@XUKXPfw!o?R7MZ#k-=z4_qb4V3sot@7q&wvoD#;nE_N_K1Am zVz4!earNy42!f9`X~&*LhS8u-WEhBqd2$SQ(ZT=U=it&6MuIEDm7d|YE0=pWBUl^BHR@QQ! z_s0G|c&RvIb0~q`^oyWIRE;PC?CB}C`E;B7yoDTIgu{UvW92h+^`;fD!8siox%IVU zCui`gt4x{CQ#=~br%zHLo}TnQN+IHPW5W^MErDh9EZ;+yv>0>g)yt;+xm*_nOsDm^ zH{%DgC~{X8gPB8)V>_UQQFcH^;RODbuYXg&(&_&Zzz+SVwt zKS-2-(@^{fJhMi9x&_wQt^g+6k}IsmG5312?Fzr zFAxeIBb*~6Q#$;ceh=d)aN$2q>7w3z%7k7IBXB1)@Vq!ZYSBuWInOu6w|3y`0Dyc%;^$Sz*#Sfn> zuyeL{2VH`p_rl)>cvvggOU1_Nt=oP_TTJHa zh=Pt#NE1(>)+0jLfR@$&I=mnCz4^m9SE!VWn1cf$u?%15!q7GG%Tq-t_h^b2QrdOF5{ER2i~iP%@{FT z(hEqo6`fikJ@oEQ7@@cRzEHKd!zQCV2cxLaNp_LVmT%xY(YxM_Pc0tvGUedJrY$07 zfN4SWE?OSwUcllB$K}+#|DrF5?It}6tpHxy&H#YI~^C)rl3l`+EV z26I5hN$-cE=^eLEjCnc2P%}Lmf!F;1Mw-9NIDKW(I7U)Z;jWg&Tydv>CUM$@W(k@n zVm8zkHU;M+qHxAj>lw=Pw#SFQkl4Z@gV#gVyCp{aM~7%Qh}P{0ERyRWtAxI=7;-+? zu*(}OxX$|i<1KZKgAYNxH|a6xE=XK$6-CyCEFuyklmU1gq(%YqUOt~ldZ#(L3pGrH zf?@TzPkYlxdmWYO;sfP&t0e(hXA9iCs91xK8e!JDmDMWb##9=LS(DG*zlTAP1-Sy6 zeTDUAXtunV?j%Fc+2xzSu+#IFpDZkAs>N%+q=TvVy9W0&9lFMuSjZVHY=G*jJSbd& z@J1g08-M*{+Szl>e3)4g*7x&iHZBu5jXf<V+Hic;+a++b|AXB876pzS*a^Xbqf|8KhDcAY?u@991735;1B z?I9}=zLa^ChaPzHl0GwRB$1!tDoftgoOoI%{sOdq_Em0@XPHBpZw(jc^)-E*b2F8Y zyzoG~eYPb<8Ul8HsIRU1^G8*ck+c-Z+6n)O+xn%x@!#W2OymqUHaUB8a+BV=)cOpo z`nR_RrwvLCvVI(B9z=$1Q*&t#VQx*vFJ|((NJ2a!VHoO9SnnP4rrXAoX(rH%v{Bzv z$B8w(0+*|%4f}bZIu6=S^l#R)h=MR-Lw&!~imrOUAa}1ywE=qEA0c7l755drKWYT# z{!0e(S=b2%+)POrMDs@wAcZ|1QEx#DHT(;qxpc_WKD{IB-DH?ZkgCd3+Jl8S-$d<0 zjS)^^omy=@Qn`;l4$@nwg;3YC`+T%r)Wja{D`^1@gV0I*`zWlJv(%xGJlDw{U346% zkT|pPyy#0H8TsQ>YmRRX5WV+w=Y&wt&r+q*vm6G@@(V5vXk7-mGdM2leG6!@;Bt2X zAMw4`Bn$XAVimJsj~#zpXT;>b;04#aTx3u<~;@a3e!n z`Oa~sCpOd&iel{1&4=pGF2xe5D?F+VgA(D}`~-Q9hk<-jno;WEQQ`-CctyJA*6syv z0Tyomi+3E;y4h|Te5s6W=r&+bCf>(5k_=E#>CRy4ZD9!4Db~xWApM)Vy5dXYm7STA zxsNQ=G}i>Evn9X!$*+{>e9STq2Y8tiFQ7?@`x6aF@9mo`)w3iRQE7~@T&n^vtkx>H ztv)YxyWTPWEAg_er-W_1=FH0%No(fX^P$~ty&$$%!lf94Wnd0hidM=Ovh7z3vv`fq zgK~wGNCvW!WnXY-N+sRF?dUFXwzaUn7FDqXX3Ux!AVeJac&qrScDP35^n>W4nh`rr zjgR+;?hIN%d;9A0Bf}tf#BbzUsqZ&!S}NFFmY}A`Ei#Hvnbv!!rOe4lwzGi>h4VAP zevBC}MhdBPYO5e0W)bO4aXONW@T*fm?j}izt*xk=*b0bQuQ%S^bC9_&Rr}FF+jpLi z{bWCG*R%U~a2Y^huJ;R~jz-H{XXrK0>EpE_NV08Vj1+?PB?qe`Y41nQljU8D9oqCA zO=L|Ek@bzVl)OhGc0gxJr?PF!snD-6LUSl{bp=i;IORO|AtlSgVKm$39#OOq$sk;| z2Win;xfh;qU|i}}!aRl(13gkNaeZfJ&?o0EI=J}&Xmv#yzN*W~%}MZ>G}parNC%r! z)=v04X>O%r9AwR?B3vJrKV3??jl(x~C+XfQWG2#{x7V&{H35hk)ExVVsC601ewfqz zVHkrMqY!qCY2Jq7z^O1-1C_Z76FrM*5^t_)bSxO+{pv?TPefyHeRJ$q(t;_LB;3@- zz|lNL`axg(?!b5!Fv^J~koApK>UL;cviRsyJl+shD$miTH~)JwYleSh zZG(W}J1x|BcvKD`=DZpK%}w!luOvjt6YZ=-0n?C`?CW?8X4o(DjL9#|%hN-E4LpXC z$i}L})hTRJ?fBsXZk^hfPsY^P%20YBSSNqi$X)>tV=lL(_a(yafEEZ%$Qnl}-lLPP z1o3S%PXS>+d*|XE_UTkP-zmfCCoQTLixubGL_Te7h#wLuRJH%o;Sf%uWdImQCSV+; zv_w`E;{BpCpK=KBbn?lkP3_ernsy1fviDH!-S3qepOZX;Qqgtpkk?mxTSN^F0m0W$ z?)!F^3(c)a1e;0($KJ!#=O5b@b*5~ox$$h-pe%<*q=)iWq`5GZ5JoK@Qhly^o-c^H zDlOHrD^Y!B8^aOV0!RDE@FMe{NDPZ$>w@65xBx{Rz+Hy}?z+>SYHz><_4Nm%QmcwW zE{|qq4xV}5OlCCTX&#z}C|Zm}!f<$xmh=&4DSz12q&uRd1An87a~HEIFqg56&ESH>4v~mi%e}rX zvziACTM@*LkSD>H_Dc(K3+sPqBi3jIbk7Pf2tfB7&=iZ(Ah~C`OqvPSXpNIJ#>so7 zT-tkAL}es(LjA(jiK!c??2>BAHC_#arA7)_bZRdxT@bC55MqD%(5k8F4_vV0P#YiDxy*-sh zg?Zu+7pMvP-(Es#*S!M+^g44Smvh5i6KaDhZg9#-R=bRoGdc`RtwGXsZwY&QJ*!kg z9+2i;8y^0uZx!L~ZDJ|T$7FGKYOgL%Pl@vO^%4jTy0;px%3$+m`?P@K zs!o`!Vawap*PcRRN8~Rv^3nR`{*Hh^Q-^Sev){t@75#FVZl)RoHn6ckBf)<3O8rjS zgIvKvtoYEv&Q;{wh$sZxONwHNB-uOL!@rTc(r%yGY&GNPKBoI z89mQ&&+Z2jPlY4EVp#UXnst1=_69Xb?toA&Ikaysqw@b>3tgC0B^E~#l8kF*@F!kZz3bIkJseS@YWXd z^8;BmS>#jui=z*a`OW~5Bj-d0ZkA*7+8JndZvv50D#JE6+2gSL@y^i)zNMx8&mUA( z9s*2^m1xj8JbtBC=H}mX(QN~0th85eu=uBcY!K;r{g4@$vDvE`^)?zT{kk$ST66Lv z`o^67xz}Y-d05%0hKjg!E>Y#pvI%Hw(Xq9h#$?vyJ^X4Ra)^s2ia@>{uViP2et^vJ z`xjByH_LOP0~i<@oDJ}**-SS%G_}<;6LJH%YHt1PPgt|NY)2J!#`1*)>-IdOgK&^Fj`4n-ffT`7JNE{~CZ% z=yy5kt_i`2bBid|;yQaGD8#=d8n1gx@|n5%e)x$!jWK8JP^#^ccClZcJG0>1kt8)8!= zwQ*MSc+fQQ{Fs0&P%6wQDR=>-gQ`83p9$rKJ3Ojsa^Ql+)lN(4EWP0f%vB(}TUz91 zpG1rMwgV)HxxcUGO#DzY0=%)+L;bIQSD@p{3=9-SUvikfo#@FZjoIfmxZ?#|yv<#T z>RZ%;W&An(sri0TrlokvNb(hsdK6uC@BWH%xpeD0f=w!-062D}V=h;2R|m`|(d5Zt zBrMd3#u_bc>nhr*LpHmEJ>p0AhQs!O z84y3T#L{@ko$&{Ea(4i^5B^a`YOBQ(0(r z;`H5U1pBmZxk1r$l1?a9c=0e3(#@Z%ut`^uqiAtFf)L)1w}&tvHJ##HiJ(=Yv<0J z+Dy|F@g#S{#98%?QZigme-b9*piybZY59PMB&xdqo zkOXCpTjL12=3-#?_^)JB8=b?GJ;rNOpj4ACV4{bT)+rY6tR#cRBqB}N3cLHV&(9j2 zv|vf0buq$ux2yQ{ffHnxYnL%k#iRL^qI~{&lw;aN!gHFVRggPr+|x#U{K?KW~;v6zoRk}(6rS&)K3soe@7Ly z#`48j4^DQJ;_k3a{DjYj8XCdjh_@cy+FqwQI#LKL6f)9`VZD$!^A8xU@ zI(7ezCkwVkarEo@)FN=+^RJ_Na}b;#xa`+hzh}0=&=s?-rjR;Ll?`Yvh2e&4(~OP4 zTg#6c%hz&7T@w^aZ}7=Tz7(>^vZ&SD_`%pM@E+-n9=@48|Z@kwKX<;zyIQA+_V zC<~I{dgWFEBDfkMfta_w%~av9q~x6Nz(vK@$5C6UXZCW~=0*mupjq!|MI)+sdETGM z!whRgdQozG1gFin-wez*E3cUBC=s8UVExl%$vTTi zmXotSnlBJ_KfSh&17u@64G*sW>%bPbu5-LR7jDre4-_s8>iTP6#51nEa~pX-`?y>M z-zz7hho3e|K2!GxC_Vl|>Cic)O8)k_3=OshO@Mrrzw&2k?{u-SpjE@M+2A9mO+v5W z-MS2}@a24i#Da{NP?GP9E(5v!axxG1bH1@fM_en$#@r@esBPUVgN=Jw*?N4om>F)k zGc`hV@%F*hDY_`4pnqtTKGnUsa$EPuv>~1c8n31kPPtL2^A=Fxi;v2_eRGq-V(NBBGMC!|%6GzQRW}@ys zdI@(OZyU)c053J80qD{FhnGkzQItNT76)srCOeD5ow^(k>qTXg947a|CKi@y)o|5m z;(O%3g?!X-OIL z-~Da>Q0TGh^Qb1pp(xKr7Tzw+19&8W#x{UPmG`MGlKQhs!#1Xf2p<)w%G8ZRF@4dW8Idx^R}qK>3UZ{0DB9% z^7(zM%JzHb&T5rd!!~gFQpiE_LBqAbwL|#bFKC=F26)A0|2*;1@!s&(Yzy((OyR3t zJJEQ-Q{V*bT6MXsEzS6a2Bd78OO zu)8+K!}?D2YxwL9*c#1OKhsdZ8?dq)aj}AuBb)#VJk&*(Y|ZUmJ{n&z6Q@W&*%w{` z@w(`KtVZu`M6VfZo8fndcqHJ{726f+#CwK98_Ak^)L`K{lw+0Sz|!x^W^evKH4d#u zHTUN0+Y7kt;%dVpt^*aLi^`;}&tMgvE|b$Fl>0~y#F zU$P+hn%_%2zZa;4)(x`DND4!B5$UU%cL2U)xq7ESEXypHc7p7F4((lCJp9fmBRMD| znbO+>)A~Qyd(W_@mf#Qg+OGvr5s|J}BLW6&h;$VZA<{u40a0nvrG_3m3IZA=NR2=! z0Ria{no3i84=o@dgqqNM$h)Cf?!Ev1;e9{6J`cx}bGFX>W@dMGcFzOuf(p1_no~b! zyMIb%3vhGeq|bQF>s(a{^CXkfWA#qqsIoL#YX_$WVb4%dOB;>v%Dx*dR^2(y?ayB| zM-@s9KZ^^o3pWm7*t0`wwvZ?v(XQgIS%rlsz!&*3ZrgrS@U`1^MKMz5z5e!RWk`f( zbKT*<FvDDnsb;@v}LMODtyAup= zwrd3!7G&^Ko^`birXT);kAzG>k_I+2oY@@VH=uaI^2@+wT*m(+s5)^5FJob@H~xYAzBv4U6~9g(+mpZ0d!zB0#br~X!3cI7Z<+O#B} zZl<+cBK{!o+(QyS1HrBb9_ejBKjIQJ9YYgPO`W}!4V9bhL)~cCU58gRi>jVLvAXttE*o0Vj%3+6%1F(=sL|*={%*UkpPPL=yW84=tM=(U1-du! zQpGd%y(cp;MwK7DwPHdO_?pfYQL}~=!ab1wPjl$^t*B<43K1?-SM|$I#J^X+KUg!_ zp^o*w!2{0xI}ro+LxZUPIp!mRA}vydpZ-w&LZ~ja+Uo$XxF~9q;8}-C%1N!giv$G} zS3FZrc|Y7SFwU5<8Ujxm_cjpwm{xmq7cg}13s;-$A$C&7VJ{m;wyJyUA3F{QCwOYk zY=LJln^e5L#1R|zGROU)aQG3x{)kCk4r)2ciH7Hh6aWgb(KwMkb7Wc9j`XGW zb`NI8Cf4Vdp^EVk<1CXQ3zgXT{G64}ytz>od5+CvDC;7Z&Xn-e>MpjmGph64jMF6c z%DX~`f>;Nnm%co{{6?o!-%S4lCwhEfx0ae~vGWD;~ZJ2QHU_%X{>8?MPk;fhNIO$?D>A}Td>78UF5QDV;=+6ZpA48K%kp{ea*z_235O_cT?D- z+IwpfsRCD^W`N$|2=%A79sN_y=(U7Eh@L-bLMMwaF~@1W(LY&e6}i@=W4V|N^ZLgW zV$`m_xmqcW=kSL1K(tO2XJ2kPp9Z6DkoC_sx?TfY4jzWGpD#$&dp_yC5J2_K#$?>7 zjz)FnUwNM3tvtf3y^(x11E?B~Uhe_eyJexMTIKd3aYXz`h0sCL;)t__VqUk$=a{Qn zh*2{Sjg4wn8w~0-S7b<-B18HCo;IWgbb9sSFOOGg)x_v1qqcQsMPk6ORoeYt4xs-J zj)MEuY-?q%ck;)NAB6k+i;cehNXd}qA3y%rZ`XUY!TBHkSa0v|xcJZC{^vb6S9A^k z7s~ubVL9|bJC-+ znD*TnyH0F|9!7qTJ#cH+z7M+)m(23(+W!)izAWa^DHW-!^Pzu&0; zYgM=G%4x2S8@%4VQh_cJbn#j_=!+(F#xV`pUzx`kx7U8TC^8;uz#4ve_++QKB7FZw z($xge7jQJ@3RDpmg~378f2LLhxA71&MMm)(nHVX7!-sLH`>$WFru+4>b*--T64u|W zRl44V)qbpB80}u~!fHP@F2D5nXL4B$MjP>Y9sP*;VldsWbBPnhz z*DrKo5aUPgf70cbw%+>((f;xBXUo^`9{r%~&kn4%=)X;ZHBSE{`5G5-fVrzZ{&`vN z%^HDLsq`zUR{PI)A@dl6vW(meX#60-8twiAX#5RN8zB1G(SIlE4^aIi!1^7)&F{zt zKN*1e71`^+Ux)O6FZmj<|5u>-NskR8FkrR{z#55P#bv#(8)W}omj0`k8<5w40eJj^ zp`Yma_lN8B`I&w7?tdguYb5^{G_4Z)S8=`bXr1A|RI;H<{>FRoE%#&pH{z^Qd4rsI z$fZ@i_4D^S6Bu0iKceQV|C=>s@SjM?PqA5L{VHC6N&Zu@t~cvfLHY-9ek!1KT>PSq zcm6kC{sZ*y{x0&XiVzf@FpY6oENQQGs_Fi)NO3uflDO00Pvu0CNSdhg78CRQMA_*) zl92zN!AOZBiFt<=f^gkGS+@Z%sK5%wAj-xV1*c2xXXQX@6@ z?)^KRskz0@8y#ktpI;#Z%7F@$p$fZGc!PCPg7=av?us|I1E*}lturdw>EPBkki!VVvkHuqfG?^ zZaTE(Mh#x@@z%d}@`t5*l9r7-t3d7&zjy!6rh5ionYE2ziwHnTL1UPN$K5egNwUpN zkGcF{+3-_CSu;Bl8gEfqP*w3Aj^FgqmMZ9Hxd z&)}(o{X7BIVOh@0!^-wDgHA*GBY+%7UVT%qYb$UY!YI#WixfHzJ(?}2aa%7EzY7yCcv)c&IzNK&v z`wukYm>B8)jB%U6%3SqPjE(J>n$K!OTh;GdQa_8H_0$tH`k?*;bn9aU93@yLi2R=gk4a1{ub{y0vNe; zXJ0L)y5_>|@)Xl1vg0fIS?kYnDnoE{#na3Wfd{UUKVmSef=)g5J);I}-Ua!CG-5BAe~puH-{*B(!K_R({@h7AjCU z1LSOd9@59{`uO;kYcQquGM5S7>g`5w4fP2375}`0HhR)SJzmx!7tEUGC!#6gt|Oh0 zIS0$PMTV;6iA~Z?&r(>DD!a*3G$HJTENg0EAfM;-m5OfcQc>QVl*hN$XZv*mncQT| zy9=!*I>?=bzSnbe4h*ZK8wefx@+lBIdTZj7m%rzD589qSSKmZOQa^3pZu5dS&u?L9 zQcud$LAzZnn24QpoU4#_!(OKy(xhiE-P4(s9rQOv&BMBAg*=7}zxs9S?=LM0j=(Y#fVS;rcK`CMF zb=0%AhOu2s1BEjX*`^?S{sW87r0^o$fT?bRVd-0{f`3XDN=6qQVYe9V#rr3hu6-9G z1p)!BHrv*up&VhVa)H{`aaMd`Ft1xhW%jIs{s)D;j_&r!+X_obEY}MPO>>(hkCQG` z+u^m_(K5GqU3RpW2E=}s2~nD8bsSXki6(*dqtbT>)s-$w=JTGK_hr3is< zJ3F%;MSL{g22f%hhOA)VI~UQA+#Ef%I2V3k)x_~nd9k@u^r!1SbJJU}(3-_6(!0b6 zac;NkL$3Co7EOH4OBi7&eiTTp&^ye%Nhy2t#rl)#nG2ZiQU}z$*p3bq$+MA3$G{}F zsohLbU5BY)E;4D*CL;HWzkX2f&}10mW1#NJb8vv=ktJG(Df2T++m-BnMCBrurAQBI z0zyjmRwNYvc2lNB*@x$D0+PG)Y|dKcJ;~<3rC!HmGG;H#F?zBYt>%Y$(^tAum)BuB zDj{*-%R8j*&^hz(QKi`m&Ld$i*|OPjjn|sccP$l7{iF{pUa6t$Ennkc(SBq)*J7rVKVbgzu&^} z=BAuJ;@M$n5d1N8s0726PM2dDxp|{Wzhaw=6VFm(f9b9HtsFBA6{GBT#h5B)2m;f! z-u*U_kiZxS+u3)_R)olT-FIV}!nIPDYd;^=H9?zFy~DoI2o_i7Eu&EPfFOyw3h&B?YG+O3z{%|9@q7}_-nN#@A&xL3jBh~ar1`f*VHEsXy5TXGb zavXQ7k%~-)1ZF}Yw%eL=_-o~`wr{%(w4f_N3#|Tnx?h-B@z@t(T0>9)_qIgt2%@kf z%zJKV(izcEsC9= z2q(P2*t5@VNmlJTbm(K&PT9&a{%A;GDgNS)Gzeg2q%OD{qYOv#y1liiuhtvbDOY_on; zJOU~}A){|3S-*7eE{HLtJe=fC;D+Me;99UrjDB-1WQ~g#W`_@D7q#5}jg3-m`*X`` z9_{FIr%u!sx|?)I%!-MTWKqkRZG6YQfw_bZ^&ZjjFfUY2+_vdXke;GjTDf%eOjV-=-A`8Nnu9uM4C`5qp_}|nN@~vbS5tw(4 z{7|0U=fRtQ0BSb=j*m9Wm|K)eF;FZ#d-|=DVF%YfRTbl!iL19R?cro|oYVv(2c>$n zEAJ7Mr#Y|KB(3@F&Lt(6_{&&WT5SmCfDH`J<;YUDpc?78n<&yQR_EotupQV#ZkNRG z##8orke7jN=w4|XA?E|`nf=Mno>L24iu-Ch1g(E%w*AQGfC|}@E;b%thmN#LH67ykn~FQz<)t~Pdpszx6@6F6M(ECg_oSk^uhL`^ zt*1C8rO2(~?Ux`-8 zweQG}2_0~+qfMu>*78WE&iaI(H8CZneyzIrGz)i9D3Lv@YUqV&p8vF;eF zz4M2AYKDWMS|`1Bc}y*;bkMNedb#|kDv89v9WSo{LBTjsJkAoWK9-$a>EFS>eL!v7 zYzx&d?Ebq!SZ<-1jIM8f#p(#OSK$(Q03lLMQ)3tHp3GxaX-_cd6OQB}uZ}qoFbNr1 zhg-cOK~lGB87U`kOLKifZMY zq>3^Y+CRj@r#%(P$hw^Pg=fk7kyMLBLKOB@16nWx^3_91j*i2nO?$6{U@f~eR83{&u!_BFA(G({W5F&jI zHauZ8_qp_F5nm-q#)ZfH8#_D_^JZ*+ircKT&iB*0G^EvQF7Hyu_|GQwXXk`RiQNkH zOURpE`R4%y4*$Nm&?I@ju%qW?(nHLfR^KVhi(mq1;hPtuUR$F4Ma;Ye zdD9?kE>*ZykuP!Q$~PL#r+1ztF&mU~ZVx#ZIM zedo&$$-xArii0KM>o5lhrWFRh!S}yc*~fJ=cgtHh%+@@F_X!V>KN%h(KISA>zh|NE zy#f?e4sXUL(1Fspi$S1F_*vC#|86)uSt|j>mjTJ#GVEM(2C2@%A)oYto$yhAHpr+4 z)opS^33mAmLSuMptTQJ9QZ=CloHcLqF%HQ|qv6@3Sx3YRQ<{^^L`adlLgi~M_J(&! z3k(-de0qEp*r2K07Pv;0+~L>Jx5v_bx0T>ios<(OKRJwtNY81=)|NEO=HGFdyT~V) z1_?*JOdc;9CA^%uQ;5{=FxBn#!)OWBLLg4tz!C3C*e;&55WU(1cf}DJa~bg%2koW1 z)Z>9I=+E0P-)1k(=6^==IWwrxCIaho8$_$b?BP6MeM335;UUN`ZVsWK;bvgYi}PZ47IZfka)7W-vxJko!zp!!8-Bl<4i zW<{=T-Q1Qa!>KBr8VT|YG#z|LnUFM0nNMr2Xc9pz8p=z0Xy1epLQMh==PCVq!H$Zv{ zo0}bBTZYGtn`tW}iY%DkRalH;96W0lUXxAEnWB&ugEwzP$ptzX`kdX7uB;++>afsd zaG0aDVk*nSt$vSQUYfWzE5E?oS=io&D1{Db{Uui8Gk1?M3Z87QCKJVFS;d^bR{5(k zS4DnCXfXQ|NqnhqZ)h-Q_O5Yqk+JWT40{lj4Dgezs9+P&nxH;^a_>1 zALaDI8~B2V@+sxb=_ShZ33{lrlur*`ML8eue<$?m2>l%wF#%ui)yEZT;Y>t$xd;p7_F!yufo*#_AmJi z|Ano2JDe3SXrm~dD16L(!_y;Bo1A)2gSWPXR{X>fw&NQZk>IHMjzrTt3M02j=!H1h ziPG3rW{gPSXyXk7*lmx+rQN^?Z&@5{VC z@vwnA!688M^{G!TVs!BlPp=1|7KBWrF;5=aC`Q`smE~@huw5AwYPo(Z z+qL27*%bQ3t1uZWMz5*!L9}nfk#f)UFr{}Mi{uH7E-0BRLT094j7y#?lpLmb#E5H| znbb?BNh#}PJ4dqKgmFGNqDE0y`+_k2gwnim7dCu)=MTr*wp?>slf|UVabXGmQd`FG z+q}|U*lellC97kdW2h>iAV7K1>Kwq-ucrECf*H~o69b{iEK;4z2ef6B!8FPhRUa5k ze{+<;TdQ~R=(*hOd~bwkhQv}?mag2TVg=d3ayEmoFVPTrnvq6EIO5$cSOOlSMcCwM zIW<_sy8CHY5l{c74tSdP1^cd9ao!3PUg-Z{yRc_W6NEdBQ=#aaR0QrY6?^8r)_Pqrw zIs4^zGVaO>VCr`hwz%YVFph^jZK`?3X0V{=skV424=_Yz;rVyP&Hr*?jhh{*8^#Ocbksx*_UY7EFW$IaULbKl0V71O}1|y$ON8wd;h(D zU+l=>6Av&b{>c_W^WZ!m{_2T)RC2>smR+`i5P&Q5B zlFCtI!z*@U)LHo(rm*2uy&sH~cO8v>>aSYW^C{{QG}JF>SS=DdBx$AT#OG>4EsQ(r zKA^TJ_MxZRHppZd&C;RCSYh9vyV+bXfE4T2z@Qy-y2q1hd~d_;q4!klnMUf$6V(pWAS2xBnQ z&5N(4#iXu}!C%psvs3b}K8x@T61la1DN^b5(42Lv$5FBc^(5J8_gPh7bv@doY60r!=X6 z>ZmFs`)@g{sX=Rffa`DVD7clc$OyxSM znPVw3%~MeL`=+RPD7)tJoUP_;_>h#lLvv4b?UkJ2#K*N4QWG;74us=Q2g1Z%dt?gs zHBy|7P0L?D&(6J5ZzC<%mXOkd(BL?~VHSI*D~(}M*cX+0n!?F)V0O2>l5@65hSoJ- zx8Qw;%v0q1|_m7 zMIiXCV?M{wQ`zr_Y3%F1cHH=~J_u*Ph&yKE>M&oOG~?)XduM3-MoAIN4Pv@7p@Ag0RHz z5mx|pLomiv_HwU1F!hBvJ(I!S3FRLpee3$f2OtjbKycf{%38Mq27 z#TZ^SX)#oxD={Y0UnV>e%cE+vy?T)8?cz#=!Cp9CgWSdEU+wF9VrB(-LlT;KY>zW+ zxLPbxrb8UnxVR+QUM>Q6Uji;x5lgi7cj-XNLR_$atb(j(yRuR5q3zAam9N){* zIyd0^B{XOAM$amaby@AH_r(ruwS_C%c{dHGcNXHdi?2{l#dq zEQQFfVpav&Q!`~JRl=S7K0|rpCT$e)1_$(yo~6&*gi>Ec!ZiZ3aT+Y~?<+g?&!cLm zObL8n+%;xW$~sZF=U=_D?ES;9(ukL-nT$1Bu!^<}9h%Fv^5ICWuIt>-lQ6G44OTkF z@!zUG-8HRuOWtcBJusd88FPT@656SL-+`hm|8leBuZ~o~caZQQc;g}0W)$$GioYR) zMXc|cxHIn`gydtibo5}uH$~4(K8BNepUOyTTQinz>q}tU%ggK7mLf#lVBSkZlkNzO zCb_3BQas=o?R&t8ZwjPsin_y7SqSeASt#;%#nZP@YPiFAB~CZzy)egEI3-qFtVTkC zwGWRer-uPMH}tCELE7htyLkUir`@|w%cL2u<#u$1{|>0Lq| znCA3JG1lXN<7LO}`{iXLVS~2QlFPw4UP`v{t+TLpTZNak5Sm~#glEOB--}QB^(0L? zygU=fc~5Z*7$rDL2W1TF>{I=)OHsQH9d*!1=xt&@OHB zApvvlk1YwrI%7(q8|{mLVIfvrciNKKW|NKT9@My#-tC=v{$Tig^3R0;9u@GJD-d#k z+nRxk_?rAIf8gy7eR0z%!x)(+{GjylNh}x&T;aCpY&#h%h|m}%TWKhKvgdcAPtG23 z>Bft?6o~Z>+x&EJz#ASi5$B{%Emk_h(&Jt|9!X}Qu@~M|bQ|^ZPKAVvH%^ReKfW9M zWC2yKN}ZZpw5xv^D-&9&Cx!ED^Q+M-N|oEax+GbW{D8CayUWW^>nAG5JV~S#u#gwq zndxRc{WyNzR9Da7@ePOut~((1m*_Ny8Jo&33@G*LZgbZueizpA#WxY0q%GwvfM~Ff zLw1K&MqCF_&BSdwq*lP&W@p%>;axmw@J)F5B~vm4P5YEMND5~}u`q}M41;uLKbF|- zQTrA(N)EVbUkt3k()M9BQ$OJd>EWfP`n54*V`)g*+dHNDhgWV7Kdu=ww^FoadHBTd zQN)5b2|)?9?GU9gdjb8Y>|v8zz3@Q-p+R|Ly@r8)b46ak1}~d=AaSBDXHs+ZDes_~| z{-c^Pt8os`gaew>#gy*U4l?n&w|(|+3G7WBX~pgkF@q^BxH@=&?HXwirm6?S$l$z3 z2Xhch%f658@^7~l5l#=^IEMh?w~X*WNGxQgP%>rFlDw=uLZ#m0E4nu^W&w!> zDzp=y=w*wJL6h|5q2`<~lUDAF7A@oJ=nHH z?Ta0iY;>6)Oej{szPR74vjaO3EZ74bY8|ML6#8o*hsCDp&7^FVTh0N0{c-?AJY$Gs zMibr<3DMSsalYNuOf^*7Hu`LD=6=udTbU0kW96kn9CEc)GmkOi3c)GAUpQ?PjhM1< zCDvi4AX-2`9V&o~rQS5~mSaPGEaJ4MM}m2)-0shOZCqN|g_*c)e~|%x`+7N_Oq@nG zjv+#Q-(8ZCJ9xlX!9HLPoUWu@neS71oUG?|BCey!p4_W=L*<$sY`F7K7HbQ=5K2TS zMZv#29pTdj^=ghz4Q_+gm@sE<|!o%N4R%; z!T_rKygUqqYbbqQT^k6B0;=LrD)aC=LZLzT#5Hb70(|mBDsbFf&k^ts;m8!!!Sc`a zf*C*X^zL{Ek!Kcz;)mf4518WJgK|gaxGrQ2JzGAiHQ(~kw6+1C9v%hX|4Trc1_wf; zwqJYm53hvXbW@h(E=kpumB`?7m{a^Ac*B>SF&@H0RekAlaWbDRPWr3RM#F%TX1V(Q+o%(DHg#pmL2Bzpj%@r#ez?e zbtgLK2h1BgYOLgx`*BJ_Zjr9`uw2aYy{{j$aK-kYvtH~Z(NFY0V~VtJ(zom5t10P3 z7m7JXZlGJWG}pvTpd|-!P{zI$#4a`RAH1HAo5#HAmI5Z@6;!}sArrs~b*rua`rMXC z>fujM`3&8GTLt*q=3g-BchJ3WsYWm{m(8$N&P&%?k84~D7gV|o0+w-8;6qWxB|8mQ@Yo&CLqf^# z5lzy!y(F^SyS{AZOUVP%#s&J`7MXxl=}+>?R(UGVP_!Xw7L$|od6x9-_sk2u0sgWM z+C8eqoeQC&a19_{_^m0ckhiuFQfBc<(79S=hkR!9#Nn&zqV?C*;TIQLa+Z=rDd=|e z?E9L|38TTs9Xe#UqKd>j{_@LMTXvHVeV(gMq^a@58N-H^H*}k-aB4r;bIso_$chf7RZ3BzVd|wft(bGSw+I&diDomsaK*ys)nz-LFdU^*1=QXnM_Z6{ zbP_LWuBNV;#WS^E0K_DK7}wwAL`j1&6dYN}v6z5y#U@!6nF3$n6xrV`hZYgnQr((w zSjz5o{>_-$mcbW>wJ49lV48uN^U>yoC*`)4TbvnR)B_L}A5M)j7fBaNRifl)x^ zVy?6}z`Rj+#XnhK2G05B&fOMH?+nMH=Eqx*196>`l*uigQ$!;MUJfBZ=;c}z=hivLIQ4ZyE6eLd>_C#lv51b(l- zS!cwr$$tmOdcgiKUHc{K`G33zFw*84rrY7qy%4vUL0-tz^| zTfTrdj1`;EdWXf0j9o_9SV~*bW%}YB{%->Nd5TRojL1gC2g-;B+!0L~SCF>@7km=g zJy&{G05;PkPR2rBH%DSNb|-GwCcE$RSU(%xB14ZQ8?1rKjeL=l^f8OtLbv&k*j~=V z18_WKLHAcSulI5DgA>*T%SRfM-Ya3>rX9(~Oh3Z1B{nyS2K}RoKMs8LsD>$LrwMvk zw^`)wd1xS;+g$72Je-`3WN$&YKdV{noihDWF}9#$*eW)5L&{9~N*i2j1|Ki(NW>+%_#OOu`&c zYrQ>;qXZ@xvc71gXyh0VdEIZNSV=Wl97xeYXAWql^Frleu6AY7o>}j~DWZhyjIXy} z)OEgR>9wGJBXLQFrUd(|&sop{3$6#^36fs0{~CB!EK9#f?m}Y4*Q30&z8y=uxelb;cvi5y z(jIEa%UibvX(9PEFZh1Y^6h@bJN)vCtZI{!u&=bg#YxJ_x=b2YQp^)5;G*E^X&A%7flR*8_xy*oK24AV81k+#sJ zMBiTUD4JwF8m+hNQ=?Z_AL1gir2D!@vwOy8#bNLsg{o9ecW}Skw_jH5OcQ7{;So46 z~$uupc@4=Wtk(Z=h?5O`u{KgFH_*brh$=^BG2vdkS@=q zvC+r9i7ADXnwQzeTM#xb{tS$Pb6H*{A+lGvKpK)Q2A%6_2g1?NcxKkkXCO^*(o+K~*|1mFLT zv0g)%Zh%!^irh7?LmxIUQ+xo(p$OZ&>s!%s5WP2nb+BKAJ}DBty|U0_Y1#e3VcCVR zsu{;F!Zw4QqC4x*e}Kf7wX<-n{3@ec%+VBz_1e?bSAeE#sop`1Wt$CLhalKg_0VO1 z`h@Iy5v%1esLJ^L2-wWkR&8RdM{5L4(Z$rxf=_-;h$ywAS7wSuN>sPJ)dHp>*s6cyH~> zXzea*ML=>CWykaOo*lCD57!E1v;nP15~$wxsposI&{xd;OAFP?z!H-8A?1yPHt^dXT434Nf!^aRKz8b~D${z^fPAE~!| zoM%(^cNCS$O*89ky&>zX6bTlDrUqL=JK!jpWJrH&eNv5iNdp>`v1s6lj+Z&ZezXDo z;CjZf!wMP4-Z_K+uL9Z*5kd>YkDOC{-l^yeOR%xE_IhP%X%P)V)h zU8w~B+J&z@1mrEtLvM+*_sd&)q`OfSTd+jZx3I*$`@wdgLkI9dQp-xkh#lZiSvI%j z(fcGD1M8flboKuC$(*3JUC^Chwt>HW093rtozM3{@x5>j55!1W3izfGiZt7~T>Oxr z(;j-pzfp?d*j4t-%4?+I_)gh&gY4vJ`~v}*fG48zXhg%48DH$QbRxD;l&VX$FgX{; zjs>##YS2+B;)%R-aZK_C(q9U3>;-@O6@BgyHWN{<#I z!R~J5l6by3{o(TQ#p@o#13N7h)1&yJzhpyv^@yf_(E{9ShQSxzjhYOV3qBz`?0t=w zvzeL4#(0!fRz{B{K-i>CJfaV}%@Q4xti#Sl_SXnNr_P_p6?nM6sa^E_DxMhL%0Qqx zz@9Mp^8_Yd&74(q6GPyzuzEL3TmQsgbVq zP>3?3embk6nD=y#f_0Q?!(M^Nd!?#igXaKR+R-SZ2WaG%3AE*;t_GM z@##|il>f@YLqb0bjy#`Oo^1*3P2R%qF%m_Iz{wd!sG9ZT{!Z^ z%1LJro>#DPV|VAncd{vmx0e1|VUr1rvnXmPHMxvm=e#eM1$Ar51I!zCBB^O{$`&f^ z$3v31ogyCtG@dbxU^wzrAPt~@8+nV)b`y5wQ)y|f?iS8YrJ+pSYBuDJ&?Deftrm2I zjOQ$NsV{s+vli99M+HajLVI3_i9rTLr_2(4IZ2CoVQ!#}OvX*~mPkDZIm~s;JG~s0kT}sZR4sbu90+3Xu%8fVt%#_2kRj2h^(#q$YS`=uJc&e3lE38I%_rkz< zgpRLImpT755jLI&xAm~->m1C>e(i}6R72l26+XFs2s(bqhd1Toh5nBg*B)xA_R9)SC#GJSCmFX#J=bI$Q7N#cYdMVcOu`lnz(uB?yB?9mkU?)oRx;bv` zmOCmABFrxBQ~E%Rt4ZbBfB#0%V2RTWh1ac^H;WH!?GYBAkb!ggvwrq-F$WgHa|8-Z z6yY#}$yNJykz}A!L&Zf*mG*AAei_~n#x27pHFet)c}Rl1Zz^R%&|FcRQqH3%Ryb-= z+MORe@mP~M+xc>$RUfMIWmk+7T%+#^#@E2>W#MQLT}Q>zMb_&Gw}h--m4$lbJ;i1s zx`n6c6ug^i`O;N$Mb6Yvxaex(g|HE4F+c$=0GOdF(E<@&XIfj(xz0BhEPw!|d*aW@ ze#ya4M!)Rv51J#fT9FlIxU!kL^RtD={PRpL=v#)9Aj-M!Ixfl*+7jB`=!TWZDY!z0 zgQ??-RW1Ydgs^_gUAna|3Hymgc@JG>{pumVpzrP&8vTkhX6x=;Vus zBBJ^Kcx+*B%nO3Au4);=c16fiWk{`(2knL~mFAyM-ZbM%&bE(`4Q`k$8?uO|cTSysk0_~06JH-DO^4mH2^l-cD<5229r zqX`Bxx0T;>=~hGWNsgDgRpZqC|7051)hDoa=<>)%!5cDGB9v6Z_X|;(uyUdKsXYPj zQq9nL#kHY=69E5N=+vM2FzNfu7;9xsWU{LOLh#;wK-4y2>nKIjmzvcc@f4cu>u ziT71xBX4d)UfOl5YqnD}$Ph-b^}zc3=m#{G53zd08JT96Ou@B;S7T0YJAHM3e>`Wx zb+-A;V-~TQykrwa{+-Gm`~iTnpG+ra`Qk?k_N|$&K29~WMx2={#}2Riv^Try0_8px z+_JK!o;oSQ_)?aR<|cG|i)bNgel+%wfUL|7_OM`CNuL~9s=PnU;YJW;Ro*~=uM-Vj zS|t>O@OHMMG$O5)Qbd6+YA_l1mgQI8`PbEoF7zXQxw*KRU?g%!kZMX@-sZ6J=1cO~ zI6-HPjtdFQ=x+2Gb_jDaGrK!Wf=%8j1(7kW1A&9)iZhz5#3gXMN`jq#JD z^rB=7$3EOnC{o2NI6Jk6wi4mWEc2eWfVV*9SvfCN#Fkoc8nhyUJll&f-LeIt4Hm(` zB!4Sf8434IVI!fhuMyzj4jHW{&*}&2*=4?x3y1Sqc~dp(p+lL^lMGm7A4HY8P>WYx@G?wLnzTU2WRz;e!>o$yE_xUPE7_ZgE&*2#nCAO zyVD+)8p`&$JgUdA)XWRv`7aHPDqV(IYI-{KS+7Cp z?unPvQ$-pkN%ON$@#^9>ccyBOW|faE^aq@&)F4~2!Zm`zkQwrxjIl^xtw*($Ho-m_ zqooWT`t&GKp=DkxUJ5RtE-bW?9nH^PTm= zmLWc9GH-X9=!jmNEzNd8mjIzDgYGN69|K-tri(u^ncxi!qOY>g z1mheuAEj3Bf4l$vIe=1=Z7R=#C_7PKC{L$4A_qFqN}e_4uAe2ztSbFkxNj1PF4CPk zz*u8cMRaz^U{kmoLnQREgLzvm{HbH_{W-JnyS=pUh={xGn^?8gBQ`txzaj37BYxUy zJDuDhXZcA)gAf_XGhBTYAlQ>#4>4c7Xy9j&YuNTwvZbLbG&!{HjN@fkVG!MLOW(Ph z?;GaTzxBq?B_x3P32fqMffrV)Gc3!h@u`7G$Fn%vEhVO|(SYHji?OLSd7r8BE>O$< zDD%s(gb>V|%7DkYs>htRJE{6)LxLBRnG^7kf-!L_d)Yp->#bDeu% z;{`xkqg{(f@Nh*)W_|N6+x|t(OKY|$?);jU>-^hk9KaefR1Cu z2e)K?Qo_?~vOi~;KcgDmRZ=orOi7=f&ZY0gfbm%voi3NA>~>W% zVRO$Cf#XEsAGV8e(s5oOfinr?C*7<y8X zY3Mx?r+ZdbjRhdf$|Y=ZmZLs7-u53X!Q=it&b917B-n-FdyyM#T3Df|=?N1@n-z3Z zN~SJ7H`4ld|6;?5hgEUU!j1@f`EYodaH=Hs%vI8!Ex+p!{-%absA(fV-4_KH$@2W& z^;_dqI6a(Ojp8iXK=^B7S?;^lu9L4hyLW~vn$eNU)GUlgcP2-98vTqshvzl@hC!Kt z0m?lY>O**A7#2DUb9u`5w;2Ezez<+$A^JU^mrRtWm^9>_ zyd$b$k%F!Iu9#5@=$O1Otzfh33;Avr!-IQEd3A6SF@BF4qj|9;d`MN5`(x=vptHqC z7RHwEQyf8$tHMu@x`YFPYfy?9kLpynw&y>1jm2(Pz9^Pw>3-k(;s~k5*X#j(V+kY3 zn?=|<9wB<%hbxbkCbDeCEG^S(6l7U4dn~1nj~2Zbb+u!^r~wz2PjgkSa?r+1jUI;i z1C)>fyNhfhPke-)I+?9Xi>t0ccIuCCAQmt&?3EQxFH&vnbLs9$N-tSK>YgOz6* zivH<1fpOrM;P-vu)!?Az%D#s3o{5cz!g?Qf7xmmPT9$UsC|LXWbW+Hs_!8Zi3c*8o z2kU`jil_q7`!3CSRpmX~1D1FM9$#SYdYenfRj+E0cZ6z8Cu6^SKZ_h>9htO0C_l8& z+daC2>{#$*%T~Snt6lXtc#p(HL&SQ{#X+U3*$z)ea)qJy_BnMZGL)zzc^2tDj87Ns3-h2 zV_Dl&g6fyWC+CBGkS<7pzJ~FiW_!5nMe4XGCIY9V=Of)h)Kctf#2KpWgpZYVVJ50u zwp$(EVTR%f!P*^8_WQL3%!s>eE&iIh1P(SbZ4^vc{s; z`~4!#X?VMn3WevD8N6|UnVM+5sp6wtFchmnW8ui}&gUyuGE~ zjF%gn2HxdqWDEA5R(v4h|F+K<+Ek9}u4_`LVPV`Y1-^RU3P&Ach?q|Ju}fZk)K$)O zXd>kTyfll9aaRTMswHci8Ck*U(|o4eESUuAiq;DitRgu*HZKjGXN=oj_i@+r{$Bp@ z*=BqrI2EnP(}^;^u6m=r#p!X|rSM27nRySblE2E9fjr7$jdEH<^U(LE(fQH)#D&HlVWr|)OP7SD)7Bb7+WlKGzZgg- z!?oSR3&H!C%A8FfyLy&Pl#+K-=M|2y2cR!`JmI#&;iu}U(WuaWnFer83Eh^p{aE@z z6H&@+KBbC#yfD$3wCWtIWH~uUu(#)ghOj7@lqEA|1l<8gWe8apUNn8xsgA@}1l`r3 zvkbn=ojS7vudcldKzI$BBZ=~hvki@UJS4&ChAJaKYfT~YqWc)W)kN(#_s#gskNSHT zu*#jrI2^{DNZyVZLJ&-CL3khUxU)WAEKQ?&n`*=4njUe`!PH3+D_9F#!^hFqTHV}9^h4;0~F8+v)^Rp{N}OA zF2*@>VDMd?nb+LoBf;9BNJ${WEMwGzxv*LH7>$|I05m*84xil93)n=qz$OCdzeFif zSFF%4M_%{9DRM5n$6CwW69Qj*XhsyzsC;2x z^;5tSr3qYostKL>%!{QG7c{LGT)5_Mz8~y5ugJ81R<8C8tlqqnpV*IZUb(MX1@6Fd zyaTSxSz$3z`4GvBhPd3XFJ*l_a;Z~MSyNypsWis89`8O{NZ<-Gxm*d1--q)4730F>4N6f|r&v+$%A^MgK#@Q)&UOA^wAvw=mijW3 z&3!&7l^;0U0c@xEY-S^?Ep`-~9uqY}e(d_>bmTrz$stg+E^}VP(BaVzZ651rcSHpc zX@^OuSWl>TGzQVh5HtuFA!~PfN zgR2VO7~!FquXqjHFGcC>-MuapC|aH95VBvgZ;^6P#FOOmMh?d0^me|K;=T6ac(|ow z+Fug`oC=QIW(geOglLV1+a9krb6MT%sVY1R?6H#uiJUql%2Nm=z=r2BvHfB4YU+w( zSvNRtQt9mscR%QZW_sF{r0T@Zuz z9RHI41EX>x?@w43&5ZBBCJ`=gsyXsT-z8!i7rJZYja=t`+$%u=Nxoo1aZWOIl_PfY zW!gWph3dj*Rr@tz7yodfVPIf-Rtnd!+ZD@j+@~aKVpfH-DY72@9a|0Ou^>xZ6}y_c z`;Rf1c3dqR*Stg64Qw_Az@sK(gK&o{wioL}Q~r1!-6dYX>C#kNW`A?_K$WWK(z*tq z#B${V(M!{x+ChJa=I`8|q{mr;6hE0J*QNi(0wsTo9surr?4vyyKX|rLp*QWj?{nS< zhUTnMRMi4`Do|xH{;}m9}FV; zB~|Lji|@(6R+F9W*Wy$u`xlYkJWPL0g{FG{#YThOqsi*Phxd2Ko_P}KU&hQ_CU9%T z(bbQa2#Yvu2<6hHSE)|BUP60ZHvZ(Z&U8jLac$YrQLR#&`2^?BN(6m}i@4semf zY|pad8u7}TQ9z0UxR&%wOD8M`!DMd(g!}CPoo3=xv*fr9%hO_&V0+OIX>=@K{f+;SOOI|?xB{C#?3&Iaf-W)n9gyx!7`sV3g6KF5b7}kL zV-(MsoK~=zwF;Gk1q7DivxFhJyAps4ry9C;yUz!v-!}G1|BbzU6&YDf#HXp6T~tA> zC=cmGiO)*34{0iDwmj|so-^lMSxU|hyqW7!q|8ljNsRT<$$*VH(d$3L&Fr~W3$um= zEPR1?GbBozKu0>4cjfkGKl{k1-E)IUv+)%GANY(VN?-Z`e7;g)r|-%;jq$hTe+`-_ z$zO3#W&Fp}o5XfrtmeIrG@+@){(Lvz9kS|5bTpPj=-I_31zDFoF-;Qcvdr88pzpgq zO1O}nW_geWi<9AI`ZkM@ou$x#hG}2A4z-1?K0jgdTGYZc2ND* zpW&)V>P#{diH8nmGw_Ok1mG@XxcX&CN~@sDjT|8h}N;c`}9 zPU+#XI`*TZP2fcM=N8na1Eop~+{{)EO40<1U4M$M1g20`)-|K}ypuBFwV4OSk*XMa z0KX(WZy!PwkySBrA_yPB+&+$IuAU-xBj#GY_$|z#Fz$;yjAQNl%OwC8 zeKBacP7Esy`YTsN4wAiBO1)^xYfi+&eoO!Y;c8i2$vgcKR>4>^tHi0Z!L_@DJ=0U> z#Nb4AV`wIk>p!8jUh7iZ>Q7|7^gNi_=QDjVdFgI5wO)Qo%j?>_L?M5Gl`CsSR_?@?W;Q#&)sZC9uE)Tiy) z1B2=3hu5b^UJj(>Oj-SIG>_5fbk8X12hv zYf2&NJi!{NQqR8cGHk|m)+LmZqze!!ok0kDCbt^#(bxzNE`y$hY#cjumjpaN{aQoR zT4gv+EqA``&(}0YFQnn_b;yc}o}?uzCgX@I1noY_Q<*``Agg_sPf zPa)`TEpI_V5tc^hgY5R#mlQKRD(AU?+EUz?01fFWx>zXTLNd*t*83^k_<}c(T@Y1BVI^vX`(>Toq}%0DL6+CneR$)9N^l7R>+xAdS)S2$o3lld!F>jJooU7Fds00OGMk8XR&*y|3+|zeP-25R< zn!DQ!7Z86r)dCmBiLr36q_p;l?5yg`Rgb%2DrS1Mjuw#v&vQ6x?G?#zy$*xZC-OJ7 zVyfxvq?3vUy0|OqoY>; zb9`P`zdqZqIH^+j#H2D18*3=JS#2+?pOKQh%nM(Epd-!QH1v#3S4*P!Jeq@&eN&%f zErvZvLTE-qHk#P8RIU0bCjHihnF^N?cNx`q<$gDfyH&<^+byNV@Ek2i`^EAQTSGsk z8xK(Anu>+SmTVj8AIpPfM`fH30MVb(*k)c+@#^xh$i~ZISYoWhjj4=})Ds>-ndLZg1NUg%gHZ;fCbQ%eOrAE>D|jmgO5AE)R5cBUuy46tA}JP7`$XE%^INSs%< z0kfU~ewun6p+SL>H0P&F=D0&Y9hYiOMr6-;W33FW48!u%zd%W`0S=e1n=~gYJAIpDC*Hx=Hz$@9WMuiXj=!1TNsf)y%ENwa* za0}#e&Kljc0s8P?y5nyRrJZ{32xVQ22znolGfSXJ3bgeUX#EqRCg~4cU}VJCff>02 zjN}cl+OOFP0EfD`lawGA{kAQPr!8i_cvy{?r(#UoQ{gw zGb0kY!y66!d9-!FyaUbu%c`yeGcSHMwwpkI5Wo-OcyTo9=vDE?XauD2fic!(W0;5;YrBO$F!3!M#wh7=4-AHmO4?3L@~7uowpI;=PY+|Jy!l=< zjFmHZp3!|)SFQ9S%vb-f#slmwM8AQb%FW!f*Q{rmn;YNyLivu~vz);`x?0O?u@XzK zEOshPL5>67&@sB^-&O6Opy;*GPplWpPT=7fqtTlo?FJF3^`I0zP5S@#Ef;HMqrEi2Q%c++JX*3K4$q$|GocQ7?7bWy6&Q5 z?l-61{LTFPC*H0hLmYaUfjtivH@JgODp6*q4$;L$N zCDE5h7RS>%oiC```cd|F>7g!`F3DJ{HTFGuS1F~i+L8G2bAG!?fxvylfsm3(HL5&@ zeYkc!c2iA@R?ah=Lj>Dbi^->%3`RhQfSvMR>^rLmyl=t2La1WSZ4!Xd^VE(MHXYwd zw4@z2=>9@qsn^|jngd*mXj3=@>~6r&{>Rz=-z}NRj!w8dF>7 zGtAs}Osa?gd!H=pU_9-husLx>BG3qB(fAPQe;Nm5wz7@PhsglRKf5FEZ zO2c|{=wHUhggZ=kF{tNYFI~--Ml+_XGJpFC;NZFXhfN><-;GQOhmxCe?;b9-i(n*I z9&0S!hTuB^UKXh=O56nl0$19rO)U@dY2h5zt9G{G&}=I9pwUhsdZvH9Ge)T{&HI1- z(hR~JFqQMeAt+L=f@i%KSQ}vTqgJhSQ6&CdcOuNn zVKikwwFCZn)Fh4V781CCz71>%FfnKf4vsp0jiRHc|no*Yv$dOG_4Dd6I;Id zxB7O_gfjv*p{Y2{st8#rRdC6&{AOUwibgR#v4murya}_S)UnEn&`dRE1VZ0`h8i!} zZ2yTk%R0M^VWfwf5ub~jg@`8U2QQd(3XGkSefsj^tCg~~p^6&p#^RpkmaeuM5fbMa zu@TbVj+u)SapDMan6*6_-ySSglUsA*%Wyj}Tz4bYRD3}E0y)^*6M$OrsW8*a{M=I7 zb6QHL+Mj9{TpK(jlc(_S<3`BoafglTUKrezra@lWS&C8zB=e)MjsDv?$xr2ENY1VL zo%6VEsd#?mJ)v~rqxbF=QF@ncB|FnrhSt<709u0DLoJAuDbHg8U<+tQY!?^rr7lUI zEZ*?k?pxJ%uOfaanE5mYF9qoP;GD~wv{()ec{8$vqEdc!oH6Al{}7n^s4n|RmBSL; zh^O=<(#Yd0>_+|n@&sVYw2oIIS>}Htn7SkMpvW5-+;7p1>aPpL@7JPBerS^lg_p)_ zGv}XqRNBl-SA@wt-4cFrf~spsY5xS1j)O__7+HoMI9Wx_`H4{WH+$y0dIy1! zafJE~8;Dyh2^bAUjk5*DHGtn;-?o7!3fpz^AJrEtMh%6zvFAT&p}qo7*GPav@+EQ3 zx`GZXH7+Kg(qeqFw_e0(l(?8cG~MYPx2IqLFT5=IXNTNODDEFDf~73T?ZCb)K3J>m zL=6DBQJ)@H>?4Z#+7zh+;TMu`KK5$K)`7v@;66#A>bD~?^BH(4&TU|SNTvsy$o%p2 zR4D7?vMj!VvG~m_YT<}!AUS}WZ{wHolt*0-Mam!bKKGF2HY%Ivg+4{IJgauPrvpi7 zsGl42bWKNuS}A2~bZQAzoMVFTn7Rtw<(IQt9P=TMQcb!Z#0IZV^oo{I6AT^y;@E%=Y<+7!6uhusD?D~bqMHY6x z^JI&-&7g-zQ?0t9t+)&bVuwVm)K?Sfu<@Fts|aQlej_Q(`!Z=}zdpvfr&%W^3@5Fu zTF1oFvM$plM7K&^>LYpAtLmM-MPe0%$=oEP$=(kbXvUDqus?!Xh&KdC%4qg~eGyDE zhrPWP^s^LqtT#BP8x_lOX(a7H`+L?V=$-_FCaaUJ{NytHtfp!INQZ#3gMv27z?jjL zTTI@=ul%PO-J=t5HS1mEea`|xl%jGYxY||Swc@Rj)l!;~(fNYg*wn&kmEy91#2v-H zot!9!TY`Qeu(4nHT25&){Iq-WMiIM9{Tdy%yE2;kQIT_Qj$8(u`f?X%Cl|Z=+ACK3 ztM;a@-^OcNQUT*M29N$+#Icd*1-yE+^vzmyse#h=`3&!#t=k!G3~$ zcG&uYl=W^+*HmBl>3+4o^@h93fw-j^66*hw`VF}?v`qs!SSC0w*joV#DQT8@+ikjo zM{DQpL4?hmT5Vsg4eC5Sd`3WU$7XXLp^0qVbINeae8LkCJ=JdJC=PI?Oy~s5&b84L z%UZ_6boR_;rNks!d33gqja5QQ$lj6A0i?j7yt;U}TZV)Qp;YC*!Zx-%ctPsqvVlX^ z$6s+xD8v&zaMWU@ZM57ysTvUZ+6q9S=AOnJ48UiDyg$JLMBdXVGBV8~jP;>4kLM3- zS@Q>l50+#Uyp`?YXwZ!4W6l0{^4(J%H-0`;@BXsZ}1`T1ex zN+}{f%k}KkEbwEZSiN~Ig2U=4GCSnpVPFm{Ab}yd!Z}0775!YF;R@`3p~K}jYN*i5 zX{pl+29WuQ#O010w+OySZz4gCrFG|&(fgse(O;J4o5KRGd)4vH3{*1FyM>OUebLjx zv*7bBp=<})=w@?67Rcc04G5$EKH{fvQM0|l zMdE-m(O02QIm1OJ%0{XVBv$j(a%4N?&H!_}PjD}7$Qv+wirCA;_<(GXu&2hs+OG?7 zmc0`}bA==}J()M5unN9NN=m4E$9VU*G=8&u4)PO~88$*=hkR{6yx?u}>FW@v4fGo5 z#+3s>xs0IVS2D6XZ@58`jpjrYzdW4&SwJnw}4Y9Pf!Hco^#1ce9wA}1IhZK$aB7KW?O3EL!0DCsOIS#b2YcH1n_ zT&`MI^uE70acIg6Hf5AiU%{qj-s5ya?7jBoF0_Rr+TNubMR=Wa*&B(ysZ~_Y(k8XI zeF*l30U;Qxx$P&)r0Mhu0kA`3I6DJ^30Zg*`;l=NOv5q;QG=N&efx%e{spw?S%du- zxrQ4;A|uX5s@#<9NYBF<)dmOX;X)0uLbMZ{_8}n2hGgOuyY<-xz5oz9Km?#b6(Ihw zf&wjCs54bs5@eDNF73gI3L@;!8QO6W z2DOs3prY)upPi&(D82myc>OjLKY6Ze z#>>*(k_q{Kn)V=JQKXxZlgR%Eh4drs)hM;|DK-S(BM4(RBoourX~A~+nrzyDL*R6; zA%oNGD&)#u4?eJrJsuH0|5Q4cbf8vV!x+2mE|ooAo6At!@m(}Gd$QmX9BUW<0BPRr zq6X_m`IxNFVZGLosUF7D5?cMXv zHSI2OTpOm)O{`OOKM7_rGxt=`RD*2DLXcX-AgusPz7>udPBh8M>w`IbiV#-UqLc$&@)BLh8!qX=4=|JZ@ zN@WTPHP?_h4aN4p<{%*dX|fU(H*$!s2@QOuLTyvPf-dAK7WdcqRW_IuvJk;c8|MB3b(hfz! zKBO}8nfWlufg|N6S1Wf1@irSV57Qdr8+Ehzj|UT8uWM?&%%UY#b9%9fw#Vc~r7<^K zN&%|Vth=OVbV|^)RB1WI7H%tIc>8j7W#=r~y+=8uilCFa(?!zLMLI0eS1cn+m>(&8 zL;zvD4)G7>I+^NzPeBycF*!vuq2wOBYLu)m6I)M^tXj~AJHLw_Ef5-&STsDiESjU!zb|I=*)O5^uE4kA{G++= zD?V;2)|OPvvmvBnfA5(#2dLv0)Tx~G-nS$3_(5-6;7U^WW{g(DKu-AFa$rM*Q~}5(nfcqIPA+OP{=DhwP8mWUiVq{%DeHY`|Hb&b@L;Yo2-N%yU&9)84nKyMcFYH&5`-2BY2(N@bdKx!IM>rL74O>ARKR}PM-WYYCkh+UTa@Z zP^@NMe{COFGnXtpsWsxd>JlI z_N0CDrJR9##eqzwN4V1!yLh!3N?{1;e0rH@#O)O$S4ADmp~QBn0FGjWZB+DNQ~;53>6H( za5aR2FU_^L{RS-_@7ET#e$&-WvvlTd&QiiL7{h$C4*qB{k~O3 z9!%okSp~|)h$flvl-hIhHBGQgIhl$f8F=gkP$s|Df0Qn_=e&|yt4*`p9Uq|TMPDq$ArnEM%Z75d65_^S|zYw9c1FFbwn6_Po{C*ryK__9oFzz$>g#bsK{#J-&PS*-m~CB??Y z1ul29!&>3V#v4=nZclgd@S}&HU^~ILmRK_~R#j^CZ2*tL?zQ&n^B!@smPJVYuN2y5 zMId6(~e#~rijJ@s#u;pbqc@e!#p7UeZ;gAS)vAYooLiN<{W+t|wgd zuWc=PW~Z#75pXDH|LYfSeZ;AA1l>UG5Hl=*!)pD*vu~ zB9?o1*6l)#&ZUL0>e$xaxM2uvZ!IbX#m*g;$I#rwf!`Bqd$2$Qzmuhs8@A;5WQEU3 zIqCLcD!{b>yeMKBF%k0VCv^=9(iY#-QjI~D&|&W)l|7J+ITT3)t14f!Na)mUA?jTu zLV|L5#+{X|C5)6?c<)vaQOjOZ6;>ob;Cx^YwU2tl*`l=^`I-ZV{n#jrzDvtii2AT6l%)W&bR%FVJX|%F|NK;B1`n?2k6Rv0((n^Qh+;MXJj+^7I>~Y_;?HN7=aCEV>PiZ$rn`9lPeD)F{c3Oi-r6mP zVG&Vs%<#%?*Y{UA5V3|>u5d8?Ao2O(RCbxk&X*))p1#wBp7e$R#*$A64Y$F0E3P|> zcv$OcSx#bnI9ukUSP6=u`>FTx&E}mnGsfXxkq`m_Pl#+{NIB8kkWDsR1$N2s9_HTrsigQOL>Q%CqI$3}K6XUY#BcwP3qkD0mXMCw^ zv-gh$7kk2J$qj9(Hd!M)W^ds9Bb&!fx4PF*|S zh}u4pr?rzQS^(w@O1Q%2ma4=m-cU{~BHamW;v|56eU}EKT$GJ`9uG^gD{$qG#t5G` zI<2;cyKEG?I14(Q71W4^zPNTp3A{y?tjV?04ct&FQRkfh=C*>ddu4Cskd5)KI-4?z zPn})*Gzhe~k7gA-?rpSmkIOlL?!xk5y7aJtM7s7A|0I8vXON;FGdsjHuqG`8+=GUH z`kSi&>8;FGyL!5YAs10Yg$TK3a#px|$ixAmSky8A-o$`~T$l1Zj1T`|IcZeYBK;OQ zPmPXzjKaIS(VzDOJ}fKx`Z(`liky^f-!wxWe|Ji>$kgQPu^*d>gW?MA744)~8+v8l zF%{Ef-c~q%V*bf3OEmT?oB$UKd_4HW%C(jX{9ZZA>H;hOz`M?ZpNuJjoz=vV;rJ0M z-rSwbqXDybfa(lTMP+n`FvgCCcfAolU2d%H$ABoqe^G8A>xu#AahxJko zuuAvIQw@Fx!>)}Qx4u>F*c*siv1{nQeMVdP%hs^QpIMGSgwD&lG(&QvMcu1N%vL-S6EK%&OZ zvN5EI!S2GI0%WsCDSI>f-?d2NXEwC3!`tFD@l3-Zq;`L!S${jIFL|QbVT&T)lrF8= z*-=-1u(9*g{&)OH@r)gDrGDV$vTH>k;MHlxS@`rhMh zF+{}d)GYC0A<5B{nTtCE?aSdgx9_0JFIGQ%Wb>icQm0yF&UB?OpD*w&+D`WI>Cm>f z(&>Kl$;rE}X!ok{b#`3G7D$GLd)&rLNVmYnyc`=zlKw$lf91HbJ$IUW2505_W(yD( z0nAO4RF6i7p*Tk6R*2d7c+dp7oodL%KAO&)ovAg9IE5vA8oaQCmjD}=Z-!TXBk5^Y zOo@Dr7sdJOr}En@?@rjeIRrs|NRja~I4P&XmONZttiL-RZYi z)E>}ex(X{htFbAKWM|2c5U+=%0?3lRZ_D;9Kca2BCJ9y%Rdji2RHy;9>oTS3Ec1_k z3v~E24;kp!_a)+Pj1|8NsPHM_(TEZjm3=h#a|U5r4~Ci|dr7~X47|SC*Q$v26jE%U zPE2sNv76|Vsw%JLZd2Ot!`K&kgh%}?EdWUV6cew_2~{G;wb-I)pnf^3DO}MMjzP^e z_B$v=x5gT~3a0My-8A-dWkB*)f~GADBbAG+3p?J4OpYZ$tb-f6xVAF}V$PylzqCli zx+);7G^Uz6X4u#=-cxb75<9fNCZk2_x5P<(#=%DQ>V}uSB|(Cw-%Ix?F28rFN#(J=V4%CX56EvQHPmW@$g)zP9{NpfYR}cgw zdh}t}iunZ?0VL!5I2D0+ICyjNB*9}NheP%A;e85zrX|BI!=xQJP_(UM>~eh;XH_2R zG47Kw#m^26QRuXW0s^aLyWhiXx$igMw7ezDGgu!Nq?JUpO!LMtDFh3w)>bWP^=hK+ znXhVuIM*~4ODjNzL!U?J<87XwDCu>gG~`8wAjHHoqi-_9)m&>sl4MTr$=AkFFed-Kp|hc)X1}^W z2|wI6=DD%R;^8+v1bWP@WJPaGZ$GaUe4gCZ_qmAd_CUl8UR-ALAM4@^NV%1d1ks63 zm^G|?9*RHL*g4`nmjlcz_YT)P{{%oW@t0--sLF7;CCj%n-=KtXMP|pEZgWN3oX^GC zo=4cixmn#4I$vOmS(q0kCIm2zUEmG3C*PbzVpXw%sx`H77e6s2U9pEQdoR4t?!d9x z@l2ipe}myczFcYUp5+a9Y=_sVuc^I$2ChK@0bc)ZL1JH|Z`lhGut?p(j4 zwWlNgu3{CY!s<`M{bS)TxUdNE_ow3UQ2>-HSIc&0xjEuH;8o+>&ErmkXCLJF@n>^@ z&{rw-TZaP^)td1TtcSf!YBic7Pg(CT+oWrwlxhtZyv-!~BkyE{uGEXUcUP9^8Pl(p zR+YuIfMvuod{zr5$dI2@DD(G~+;8g|gwY15fY~HCj~wsqJ9~Uv`>nM9#Olj334fS> zR^P~3feyOy*J?MWVP7U58J+g=$?Vis^*2*I2jGe9A6AlQvpU$X`KdH1b_pIK` zpuV*+t3KHZFM4E2!q%Nw6x|iLv^6@5e^is{{-r$TEUsqlNIk}fp z1!^Ii(a3V`<+`pThUHA!vB{K>9htH}0x<8AJ%C?4JcEBNEaim`0uAxc^V%5IUp(0(o6CHmv|8G-y0AUC-EeZtf65Of?%_Ue1F26Z zxmiKpP=RY>XYPUq#pGBSswCH6FMs3<%fdy9n@OpU_tJ}&i(J7091Dcc(>ep&K5h5B zm)Y(@-Q0;{=%GFA2xcK?UX$*31!xKWEQa&vAR=k$k22y)3Ix!eGNG7MjZ5@o!DrVg zFVT?RXc=V-F4k+78@$p?;(oU>f@{F|?oY7sZ%rEkp;35LB`WJF=4SNjlVpfLzFl9F zr2@Guj%*33&36f0r0=yy08V0-L%cbHFGV6@u9pBU{9yy_&d;ju5fmHI7ul|!jYrj`cc zkGbsK3CH?uSVMv2!`%wm23C7~KB{ncRH$p_+`|H)DfhJbo<&tBLkiTt$Xk8liEl54sZf44}Z<+mHD zEY5I2qg+IlJ-v}o8Q|1<6+TjV-tt$|TugjpUG;gXyp@h>C-@~NQNg5~E1YT=Y*9KL zd2ep7Un#X$iGa=VLqA75&+)>->QeuK?BXOuPrs(SGN=H!3ul*U_1tl;HG)%?30tb! z;f#|#dT)JX!!Y4e-DS^=FxZZFHEsl;Xa7=@Swj_0xk2gMw(1YVlNQVo+6*@a8vy;q zwZA6~;5@Y8j}@5dA8CgX?Dra*gx>Dsp4Z6o^Dqu7ogW5pT zQuA__N1e) zC-z=;GH`XnKXN5NTV5_CG>R$+xSPf(+P#GHxCW3w_Rx=0rk$pbx3AW z<1pAJEIX$?`eygfzzJ&?fC~~O%l(^hs6!qB>uOYY<}i953uSmhcC#n4%ieeqD7mlocKnE7Mv&3u)863ilyx)f{_g%mN-pDxx&RAbyQC zL0Wo~gmReer74H^g6|Fl+V7$q7gY&59_DoB)5{UA%-o&de5U~!k- z_o07_6qRXa5KJ(0t^Q-t+)(L-4$+Ol_on7@HgJiHW{sNr06EYr{(|H$ZeRLC*+xg+EgaZqy%kpH|7HJ(biBS+eUz2`JycRi>oq?Qw~$Q*fuatM(IV*)U`q zIoL6mMt};#ouzny3O`lHD3pbVeIPu!Ko=+WBgl^MDV1 z!||s~T~Q1tKd-oiD}nAGaj^3J3nS?)LK}l?bCpd07=`FKnW5nA010y~#3naK_PRN# zWaAYH5N@0%yz>{(oN86U1>AFL&(fh^x2q4MtCvwel` z;60W8tz9@k=x~KDyuWEAUm+@hLKtEV=*!z(S=&8>Z36*!#9o5UbNkgeb2sdYyfX{#v{z4+ZG~yk z?_Y?&5LoV??9qCG0yW{4(mY^TgfMar@6N_IO(1CU0WCM>=1=YX{G~Wd^{InI0U+Jh z`vtexao_dJg9TN{*fB&SuAklP3p8_~)W3TuVlrqYrZUEB1$3 z4E3DT=;WJ)|CeD$9Ree9)97vFeSKkM^*4Cr{C z2`Oh<^Le>9kp2c(z3^}D`V$^dcI6(47W|{ugmLOWNS?q@3XlR^*`U1Jg~`HEPI;^ zVI=8o{Dys|bAMjOkMFOtEC`M2zpMVa`{Ww_m6Yu-$$A8ACra!)nC(4pI1Zx3rjzFfEFijAJZpdRS&A9k4F=9Luz z!7TLYvv*Pr^w~Hz0O|U_bnES6u#hQ%AJnS@JmSMe5`y;uyatH1fvEyNYfr(C7Jm`` z9LN_d1#!?<+P7P16k@0Oo}S|CTYYU0d!Rl~V(=a)Y`0&=03q62`kmSMMszB`Ni70# z^e=Jx?9HExz=$&M~0GD_{jXP!;|!~=v-%)r>B+QPvdqso6&1@7Mcq)+Yx8PK)c zfSU43&K(hMZ)X_SSmzn1;sU4g$;6cuqyOV&3n321VQNQf20NSaZHYF{_(`cRp@aNlL>ph);msVcEWoM$s{;lzp6SZbax)RvgQ$7; zmVM<-@IuUJxj%Hibp{6iy22TQoez9;`I{r6VC1DdtH<990O+IUKYw8;XGpbV|GC)q zXCbgdge#2Aa;9v2_qTxK4=aoBO^reO8*f${7xv2MGR=zPe49G>76x=P*plIMUx-aNnxi|ujJs3@%q?=3bk+WdV)VKofg?E)WE`{iM zcFGIf>8l{U6k`#Z$i1mXf3iod;qC5lptiB@dfv5nu#8cU!H;A{>g%j7dAf@2 zIDb4J29DUUA|XT}uyVH8o~?qQd32?Nj7D`hqi*~RB2+~92Q%Q0{ywOIqC}-Jh&1vJ zW?0od`~IX3?DIK&tT~+f8WNDmYb_06H4g!G0U$p+Rk_7R$?n>NYSDb8MBDRR%okv} z`mx=i$FHT<@_-hHRPS%qJ^ zhxG0mN{;J&6F98il!-*Acc3|2^4~hzF)!p=iahSOgjhSe@n`RCI+h5hb!<6_r^j+g z(eA!jouYxV#b4hP8|7So*F z=;z{h{|H!02%;grS;S-4Mb5p;RlJ|>G4QopO;=eh`3Krnqnn~~{4{C*lh)9+G1vyv96Xfx0kHvaak+udWO6f_C z)*4KbF}sPxx73)locZY1VrchPZ#G8FvxH`0r|!<1lASt|P;_9R&z zef0;LmFJqeo;qd)pFhuXZtTMHx5tD?|L@YCg{URe9<2>a+=FAIS5Usmx{ENH_Vm0)SgP+F=(iaL=I|qOG{%kCO+TRMO>ckRzWYO2~@)n90E0Pe<7uxoXW6>m~-u zND|cS|Ey{5Ih{N~N^wxRUy=4)4L*EDJxfJq9`e(La{+t@dd4>E*LND6*0VNjGsOKL zLaaSFE%-kChh&lHrBGmQ)1Bqa3`=R)7C2c~nhW6yLdyTG&k4CUF)$({)?+^ySKv(O z9eSqKQR1MXvOC*O{Of!OU@sk>uf}VkhKe@0)8;4xIhLB;?D+AUsd1!GlRBO0s5?E^ zh5)i_;2W8@Yv=f@{$OS(t<*vPaRcSk;mJ2W0jgh3mP@PuaoZV(z z*b_APmunk&4(LaXrv_Uf%N8a9?i854R9lxx`UqF2EC*9x)6L~JnguF| zi+5B+LZcX0GL0TZstvKON#fY{6XY4ZV;7myqIUc=s)c!L^#d_8-QA=^C=zT2xGX~u+*6NJ1T(XHywR_^{a5Aq=$$zX{PqmY~e+u z=I@=5_~93j#y!FGe*w=CtS|)xPl9RyvK~zQMU0>7xkH-w`P(_F>G<&h6aVaC`RTaW%=aQWtGA>r~jE+3)Uci~GRJ*I9%%QPsPU#GUwb?rDF#dQG~JZp1~ z|Dhjy1bg5;D(PsvbP-mT(vc&`^;f8wja(|7JuMY)27V*q(F5gx?vFC_Ll@n22|DU6a1f!Law z$@AjMM1aTnH%B=PSY`_P5E!nE2n2@9-tFX;p2bE|*jgM{_4Qtm8!^GKBST&d*o#Qv z>a;!y&gC|f<;gwlCl<9e8MxYKNzi~zo$g|2wD7m9SYv{_6s{8wkf%iK6tpDq%uZ5# z9=$97R_&@itDJk$G$Yd_qrKDx@JqyQ$ff_mFM$iC_pv`gLAP*Lb{(}1;v@*M13TxrUb?m`nMFgV2e-zw957kle>IV%@Np!9y4VhJENMty^@C{2E8M1^%*$)>E zQuI^IV!59Ywo5+-X*Hzd+Iz=AW zkkiRqrM8)qUwS3kISB&Ynj`Th+r4c+w#rYlWoHXp(Cm9>3V)>d4iudo@cumHbDz*X zMblo=wn~tKLT-ZDB;Avab%nn9THpD_3BbW0o{%5wNX%+HRg(QCUpLnxwf3R}u-8W1 z(fL<~Cp@iXk05zRMqd$NQ0F%A+XY0PZz(7bq4?24B}ruc;IgNlB1z2A7vxXT>9|HwV>>MdzZ z!9m`&RQ5Ncjn+JcOl2ij72PY-JFS?{2=2)-DRx0y21mlotgtXb&4ws;xBCC0kVk)8?0YYmcCf9;sP zsy`UYzdW#ab}rE%#o4_W`ugYO{M_iKy!FN1-;`ri12)_}zYbc_3r1S>xTtVTr2AV{RD8 zDRI6}@BB&wK1+Bp`q;^BwbJ&ea^Lz>ZH-3`4qllb#Hf=veK0n=;9kZ-C*@-T-KTeG z0kG`Z=QLR>;`#DaywKs+xzM*x&@-Q}%VI6T{xLT?&K1H_eD+9xu28oY=SKC9Cc}r< z;`?gu0yxrCzb8J_gC{ZeDR1faw9xEB#xeojUHw}KSKtM2jL)ZgpM7P7>dz;0Qb39k z1?h0LpCN);;4s`1yEQ|~X)2ec3VOX%THehjgY$iU`c0GllhwzNd zCq1bb{zRm~pUFUPdgjnDW8AYBE<0?kcuiSw+24j7g(#$NnXrIMwG<*=jXbtJ7;bII z|L1&na3_`To36JANu|e*Y8#tz@RzOU&Je!LYcj6+u!ICdk04=NJ1FK2aH zV~e8~Lupr*rbYsagLC!#MUW0b|JLjFSoVkwt@3L(eZNIKFRnc7g|~TE6FyKHuz^?! zi}|%Wgq%tIu9|jT{x@6J46dbkRg%Q4ak`zU71ACzOhu*8%tqQ8=7pW_scnb7Hvm^u zUjh;Z`~8h?EZWlt#rki>8`=n-#0V`7u$SULG5hLHs9ES&8@kQV{0Fp7qZc-O312YA zu{nes&<_#nXQ|9JB5ECOflSa5-rX6h-{>;Be@<&8icv!W(w0gNFaa30bzQ26Fvq^& z3EpXOq?s`OVeh)_@`2;YUS)2gySWDs|kydn|hI+ep9t zxEmSyYj-XS2V=k9w3}?i#Tq>${NM$rA_Cnnbt#)$6@PtIADlbE|tzRI5gP8O20DKYt35m_Zy#BNfj4(u7n_Tb+g+Y9fSqAK#-CLo3-8;`0ufwGC}TdQ#c7 zMUzzjYCqJ-fp$U;LYxF4sNMO%`M^%b*CSQ}DlZ4)*q`MM9!s(XiP`Zb4i+mdXP0(U z#NmsOpXqn{+F+8HkgP9Su!Q-_ice06+h4#Bn)@S|c2f_e`6LT6Qz$(@{3Nj;ULEQl zuD-X_`$ADzihqyd>bRda`xn&!R`95!3!LnHXxh%4|K{dTx99FAjGTlNfbQ?eQGg^M z>=Ar;xAUQp(Zs89lc{Q*xgMpo#Ra^BO9sb7t*K`L-mS53{RW21miud^Ov954FhI@U z^Y#?!g{DHl-swP$&Lu6A&d?0rC4s>qM-NBscD$>u)Ll_D@;46Elmz^BO<9jQEA6eO zno#k4A_RS3DS^~yO5cj5FPlw7T`jIkwG81{OlcI&VhF9@?f{YTxRN__>=R+^QtueHe^taf;~Wj zV^32(u~_gay6Io}wnzTlD)0v#b1H^qbM;Iq%wO%|8SN-G)z=@}YWXBGL3{y^&d=XK z=)%-!<&mC3=(q!&CGoFXM212+!tQH^WXc3dj5U`^4kx$00L=j#Em$d^R_DVrXNH#M ztfj@r_m&E=8mVlYF!tWauPbT*^}5hzS`>_T=f9R8;-K~=zgb@tE*GS(q9q_pBhdP` zO03mF#H#ri!P?D5Vnd`fG{aN@rrlQqYVfeEHJXE**KBuW-Jd4Ih`09wzvQ?S#Q+71 zNVBXcN~Mf-Ro~AeE_x|~kO)|;r<*ahgp)*de66G*s~FtQR?&O#BKxB4sE6VC-YK|M z0L6+l2O~!(-3eeZk=uUTl{YvoBL9LrbRgkN5IqlhYb^PffwknhW9tc?yH5{~_91kc z|7^nj9>$e2bbXc3nehmwx}UOtB1DMZ4h}SQxn-|?XjIllx-HYYaSskWdwS^|0O3vm z_B>9%%fH5cR9Z$eghy=tVs=voBSTixu>3pAy8H~K9b5IKoZC^Po&MSN3CD-e9kB9- zZam%S_x%+_iXD3qgu46Q4M4gEXY6m)WD9mW!T!3UyX4nuex)5*(Na(MIj`Wi`I&*F z&6*RBdYw4?Uih;FWf1(^lUFq2o#yT-uH191wat|n-!?56E$5JG9q5ig4<^Ti1jL~@ zDEAUMr#q|Y;!<6fs1=SM%8(AQrn%txe|2^TLr;V2^Ua$g|tbqASE+=Z2{SJ1Y9Ti(Opl zPUQn@=BT%Guy~r!;{}x`7N+g0a80P6P3)5P@3k@7tx}RvXA5UJx6rR+>V0Y6)SkIU zwgM0m$M^L!CCHUcCMOWt)ni>#p&8+JgzG3@697wvM{*AKge+yUiccOC4~xg=3;%Sq zVjSFAwvkZMx>^mR_;50p=$foCJ5-S1&|9CLWejo!q1j|(ZFr-QG{xhc>!VB}S#HF< z?bfeK!YL;b53pRjZcHbgO$=#Pu+8+T$tv*FUPYW##C?6A-bZZa#++m&_bhRD=jx8r zUZRIA9%sg?He--z_#^mIbx-$8p18}14UNfAyUw*pKx6j`Q{9cHd+BNux#$fd)+~6_ z>gHZD_1V#w4&cLP-i1?k+R#i)a||&#ZC(23E}}m-3&a;KcC+;I%D2{WftUZ%ygs6G zkobNNI6+Jsj9@G9tQ}JZa__3juK}}r5Fp*u68+HVvMg-Shn+n149&h>R=)<*DRc*R z?DX7GMqprcWXG8{_XIjm>&0*xkvU6&o}Z!bXEAe5Cf%_%l>0aF$f1rNyw8tAM?&mI>c(Oba`hS}-2bZ8xE~KW-tKPJH*lc@rN^St0W% zI|aAAeW_wLX%W2`d&>htiIv6Dwe#sQYo;2hOX?Ty<*X`mf7FBQj)oPr*mLP@DU38EHSI3nm1>>xKJjFiYoI+^4j+| zU-Ps0)&$R3`RCs5kL_*V^-;5oWhCLtYQ-oN@V#RS%?KeK<@i%n;ZyfS!JD0h-k`t2 z!y5qW2*o7}i+W-KPd*d+@|xGtD#qEQ;+P)d)_jtyVoN|gn(fhO zN^(LV?CzFOo56#(&&q$_4!)8c@i&W$s*UVcj(6OzVu=%4#kh)J532#%R?tlyG3{c7y+F@A)2YoYEP7Sn$k}xryFy>*#>r`eudx9USxb4Y)UJfSqmkVyHaX}6miesen z@hP_BrI?1bs7wyOl*8$w=rtAI0z80*^x1Fq3JCdar-Bkp96w6R^?+ZhzxMC~1&8vJJ!jbWh~Uy*+b|wkzNUcGCRPQ zWg_>tc}SpzOtU*vQoUTJq1Nu#>dV5eZ*K;a=h6(dU{^#g2ywJw(Zc7?aSE6+h!36` zbC=>BNak$fPg7F#cX5@y76sh^q_BMIGD~!lV$N6%DQ+SCt4yKH1Y#MdlUj5=D+G4+ z8za{c@nWzoVVZ+(MaH>jJ^Olz+k**bI%CQlX&k`BU#g-+die+(%dIfmKcQ3JKMq<{ z79j&|WRTR`Zxs*WuZq`YEnojRV*oVTc(KMG1he^~r?PFm0+Iw%oHLFKUmiwZD)s+k z`_%q`PFIBv(fN4vXFs&4Q0JhG3sVbg(FIKNwwe(lCPt}rq1<`NhFNNG;jxy#f@<3$ zcSeV3;()l>2&*nN>k4B3qF*+(Tsp0T$;7gKrx*7)sFj3kx_fx4&=Gm=J=^Y0EXl=MlTTRqhI7~o3Ii-1*i70?PX>$(JdG)$F6)9 z=*p8>qEGHv`|LNz>sdrd;h3ySrm)SXQ`KjRHBSJ4Fv^n= z)&IXx@p!2ENPOR~%fGS?ORKs+ShP%dH4~#rYMtbGhT*5`FCT-!m;`?-mB9Jjmx09n z6shu%y)Jgdfup8+ti>l>gKQv+I`H;Z_W$iHED`@mOjM?pT!8^9(5{zPQ>uu4DPig( z%#T#2mD+=20?=s^D-2Yt(6$6r|EbB)6QxjFGH@+1k+v$rVQ1|?cVhtW=s%Fmo3#=W z>xg_0CdfA7IlF2-XU>v_0HdeiPtBlcQy4?G>i?BK14jEsK~ur3-qBOiV+}=9wwI1# zF{^+(xb?$~FZuD6u|lqzkqMF<>D*C^A z{w&JYN}z{xaO=K@hlG|w1=4#3z-K9vo9r&Gd9ydtQgH|uILH|sYL*+jAFgoz+;X2j z$AqY^&qPxnKD5aKuuI}wq3D4!jMZu9EoUsV0;^LP+uOY!M+I^2(IsHUIi0v#a+p!v z`8dE*wRxJ)53129&@W?4-UGG+RaY0bUWhXb$nhXfJLxRS^WG} zM{nXJHqG6Eh;$2QG60?8)n9#2ovVQMuZ9xnbO;;W)tm$(GcSR_)2(Wme?4@v^r+X#yjgC+%<0)5%3mW_|?9|bM)!|+hdu66)0)3?Y)w1{ZwiTiMGOMz+TelXjE zC#fS$xK0%ynqC1kG0#ujwWFC?RqW!YR7l?*>FvOx>z2EJKvIj13Kd3hBd$@vz2=^w zGG$#->8e|Qh^xb2ip#@!O?)xUT3wvPgmR$*SXCmguF4A?YC_*O8GL;3^7qhI$n3FNBF~Kq*PJnkGe!9Qr$}E(K~M!^Z;zd)4W00P&mJY%Q5Mq<0DKS76lillu>tW*^u@{5kdi{7xNelhKPU<-O%smr zD-cOQgnT3j#8s*@N;6O$jvcjK@lW9gCT?(}gU;^`;%0XP|7)Td&$qB`n$9(M;it(CzQj(#}7b+PIeY-@| z?DMUHQk~lc2rkh(Ie6V%>_<-Pdx-`iwE#%gtq37-=m1!SIfECPvLa(;`PxpSyPiQ= z0L-r^T@U}6$X7RbTpe3p0T|n#tV_Uw-_cSY=jYFx(X02Zy=YjB6>E4dUl^C*QQ))- zDDyMED(c)FjBa|IDe7;pt6^=xBeuMw-K<) zrDyzH!Mwft%l0VT`tY^DeH%B*Qj#VnJYX0P!KonEAdK!ImdztZ*|XY4c+5 z3wT%#-M#KF1xz#RiN&ExH@%%mHAHi~x7d}dJU0`)#`bc3M*pZ=b%UI4;B#+c8~~ub zrTrnNf&2mqUv>`m5t)(CbvM~DQ+BrBM(xEtBg)UMB4(4AassZFJ}fP-^FI%%^jlU-xeqPJOF`Z7eoqXfJF2tp_IYMz{_ z#CdZ7*a_0lN^L8ZWq-jVEs;FLWtb5q>Q13I2eZcfjKFMj!XqpGa~v>{Ste~oSvvce zL}RsC1b{|idX>U^Vn$|>Z~ZK=?m;YJ@!5FjWV>FiMq9}U6jf;~fW{V(3RLWNw6cw^ zl#}Z8gJhFSp5Cw5=P($>`Zf1o%sc5j+e4a>ZPg_dp4b_9Es3osdOT_WcAPzWYBbO>TEt`^iPV zx<~U4VgklZmYtX!_Aw;Slz;x!ucE9Xg}Mmf8lbSUh!j>%w(~a;UvdFB=t&3OK8tfD z+%g$9o{6g^oKl_Uby4nhQGdsuZqLx?AaRvAUl%h;7aHO-Vur%88t7QdYu;O{--z;)Cg5(h_(OF26OGT)>+gjJ zsa|`C#K=n9O)ZN(Ycip92D_ikt~Jc4#&I~K^6|A|K zox%kNAUNcV6f7~U;0KoTlDn|#5fvdis1l^%k^b#2{)nTomiYc%P3}kUUPkXAm95lp zO4zp7*>lfa_362RN^bdt<-7Y2VmU(2IRec-YzrjlYxZYh82Y)L1H8ejEi+J=Z z!JqS-Wm1DjAk*Xb$M8VH)+C1$e zF*81!u3;fVi$;4v35>Ph8u(`yEd_G&)qPz%VW3k--ndjQu>EpY3cgS)3Tnyii-=G6jfp0gR2iOZ zEgvmAVj7QMWP4jguxY@^RU8oi-Q)6TDQ~-+vqtHsn^}n0?_{>NJf==pvrWp{p&U^r zF-xyOkT3|mwF*r%lN{VA@~KRFvpg*{@;P*{`L32vOJ&$4zkdIhMK@&78v(?7ENm_~ zQ6!lyIvg8QUDsuwna4aM6vvfVUG_=r@lTDgvG5<8yBf^JWGJjqc9hLr$WV|A&y7th zzN+b414+YFbyi>z;7pYKpnB(&PRN&vqj)V;1J}xAV-0_n4}YB<_QxE~wwT>eh05Zg zM3J>kxAoEr_v`3N$Bla>74vV-ys}4-=h(Jk8woi1G3$3i2upTbm-7RJBsw;+dbYWK%3l88J;6$Y#JxSvX97p7u&*}%s}_n<9e z0d_aa2}1>yU-FsVq6emEeb@)YvMKD4f29KS=1VPw&*ZDjkjDrMUAx@#-+4V002xa4 z{RQS*J4s@CmnZE8nicy(*v8T3*oW)X>dtGpxheQTYg2NJ+~^P!S65dWq>k0$EXB2> zJ92{XX8XsWOjp0Eq8iY`3jRKhYW?lH)ytm(4F=js`t(8}JQFdI1%UrNW*;xhawKRR z@(58$KKWZiyN;rzLpHWO@B5ot6i^-E@uKkN(L5vB%0}tl!*F_jbK0|+TSq<8=RHbv z;(?8uPINY4Ii0$4D$62CZm&QN&<^`M^QH}ACVGMw>H|!a9ew!e^Zq+X&W8Y#ngf-T zT+(c%x;rFPRzBPB5k&cKiltJ+1ep1- z6MPud5LQjU14BXrw+^R;ii@{>*CF&$AqO-ZL&&8=hx^&ZN&*98%tccpsca=mH1G?# zFFT{%^S?9>d}04?jX2uU9ayY*`a`G3Tg=!;WloVPH4o>V|Gjkot(?b)6%(A*1|OiU9&Ic89^#5(Eu@0 zC;*e0I!H(a#CKItA}(y;-EE=43xOV0<^@gZ-3uZcD_>m9+w~Z)jZt10rZkSjhCJjM zpMwb((i;Z^BS!C&`?6dgg9SLYCz96HvnB8aUAv02s%gisy&?4B(4un@R%cr5H{)pK zNXSC;>u_`{v2zdLP)(<)4B{32O=_ylMQS&fO)WH-F5)Tg#x6+rIqUm1Tyahz@|ejZ z1DbZc zGdoLHKxpl3fi&cpW&5Y@?SQN`p#dspn!*M6ap0m4hd}jkFZv1YE;DQ}Dw763|z8EzL-d%H~B!-evUkEZsCFr&=o2{6H!_NZzb9kH}7n0x~k zOZXsRZPP+UM3?9cSJ(SCCLkffc3=!;f3Q5J@MVd&Mg=-!fCMo|86g;O;l-N>8NRKg zjD6eyCQ;$nt)3Q*ELH+e;*>3BPgP3Xyg{|mEcsvq@m2=VAi|!50Kh%oQFK4;4D^|WD5}Cqem8`4g?>7rOVgvLv#_Gd}(G;_Euv`nFmhodLy(}b%Xm8W5uLSm`|K!lIetk?p_ZPeER(a8 z&o?gX^zuU?ddq#RUBIqGf-kKC0zZ?Tyj6_)B>SW|<)_Msp=Q@^a&*^Aw}lD)KZyQjPcNuOEYoWUc1{0aSo{O-+`3DJL^kaQpZl8{LGN+j^Xz(e*OBySZ`a#0$V@ zVi!-e*TNdylJm-9jCAOxxEDut>Mvuwo}Rp^vywDW9@guBakvf`%yaI+-8&cgX{1%| z@eYzeWK1KD=&CCCYNAvvQBotb+Frp-coyUmV0b^4ko3i)Q*)T7U)*JFY?-6B#>_>N zS4s~(iN}ZnN}|Im&0Ph3Da!>U?m*fO5`=rToRZISlA$Q-yZo--fwq7#KsmvGe}{Zo3(C~U@`4C8)$U!IwcOqNu^d)%d3z3Z4zJrMSt zPt~wBTq@|zZSskPq`U=-zF6TZ&g=R;rVEC@0OaT%$rAVcQt19W*~J9&l|1Uoas78U z^<8UQ19=v0xDhCkK&n(LVyY^`9KoT=5xdFNz>~;-lTq%v$2NsQf3}`mVCiXZe0{m2!vL~DOzS9&msD4iF>xb4wsgH2{(R^3 zusbMjF`sw29Yl^D*v7qRC%BhQB=tK%IQAhbf_M2DyfWNgDfKszC2zzoVxUCPW~vw_ z5HrD3v$SXTxqV2d_d`bVgV@T@{h@@j{Kbpy)^Pgu-t_h+$yKwzt$W8;lwN;G5<0Y+ zhF?dTU}oYz0rO9!Wbo7oTEiQX+s>i7okR(DXy&N{L7*$LD^i~MYZ}dim~xlS=N*ef zILa+OHY$m>OJGK8Ex`^vM^_EvxN@N=hrWoEyMansdP$S|Z{=gN?qpEuW#60gOvKIG z*8;FR%OvVIIzFMWPWDR;kVIuU@yT-$m^d$EOidfc;C}kYG;jN8x49gc1JkqfG`?fi z(ToXlMfO0Fe_&XDeK8BC;i@(ggpwrn?m;X=s`n!)KtM`>7Cly)nZ7_=6rjergae99I;?xP5RbJ_`sDfR(In3FmGrWl^ zYJ#ek-CMA;I!K!+J)otH>dcc25wif|1Z25raktl%Vc6U-5@P3;-N_3XvnQBZ7&x{q z(+C}znQlz417#HImV-e?iT3QKY31!i_wET|qAQe!C~|Ml4Kz*><96UJmAK(0T?CkV zD-Yq7nNI!4PmlOVU!A?onrX}{?J-=LA4#-k$gqvRTL6bRQ)m(7Zd&A5huzxX#HM*=9uRq z9e}`EhGAiH!7*-k^A`I8{w&Q@WRimI36LlQL9rq&ts?EfTYXgzX|=%P9PT}lRXF^c z$Y^7K*0~GbsW!|bOzF}>(sU&#++bP`?PO}FS;7ac$N5k!i>W{;=pxh#h-Y;Hy8#vJ1K{lQaoxe?_k@G21UG&D?+*T* zz9J#X9YIVCf?PHVxw+G4;uSC~0>)A<{8xW0cLSXT=*b9_A}c}KTK4vzA#@PP`tO3G zLE#@i-naz1`UO$4jFcN0;>eS{a=ip{qw*NFN8&id!ar6jc9H2!5MFqp>b6W9`;0N& z+_?*D^k_|CB?9O7uO((rQmxlgIy+P_3oZULLd&qSexBsNdOV6*FfC$*0vLLY*(=>{ zgi>ax;qG2^1Z9H*#gv^g8IQ)Xbj%ThqUKgc;{Jd8?_JEPrWP{j+8S#L9qeTJ+dmZ z+&ypmE_k8kiC`3NR+|lbu}k5LQ@~*xjVD-h`;*B9ITMsr3ULQhA*}D;pUuNi1ft#l z^X+fol82~t%|;CG{?E4~Ko|Yp$G%vrB3vA<9}JyBIe;ArL@*eaMSv+GDeNtTWtFti6LM@EEy z2Twx?Ocrp&DBE?^BHHrpDppDHipE706_hU?`*mA9-}#fO`HL(y?RIwpKDWBBBuRU`7>Kg} zKTyHj`p~7Yb{b#H@>e?!pP$8njRZe3*uH(p`i^z-Mb+_g^6`=J+zQlS&_G$;={Ga^ zdWOrgdXgi9o@Y@c&)P!muS_!)iWHdcIEUz$_wb#N=qeU0&Y`TNt-(GFlftuMX-0)i zCr>%0BveS&)8F>PY2~63%KZiUw{8wmX#Qh{pat`?wIS!Sl2R@WI~E$qz5SJ-WRfJy ze$CldZjn8srTQ7PKQOU}(8azfl1g4C$V*S5Q8tT8PY+%w>Xr8{9j z1{e68b_4*^2N7hDXo=uyQIjKit?OOqmD*QQ8P{W1bfRCn==17_)k(L@C2PkX`{s38 zyAz)zm8sNSDVm7hGc)Yx@7F6kYSnPNE}D_k??AijM$Ecr)5zBQEQu zbHJ%d*O1uu3 zUx;AwWTuU4ZU6OvO8SYhT4JpQv@iNN-3V2qZtWF}!#t6MiD0%j9qP1323y>@7V&WV zvwc;ak=t*jU6JZC(xe}lt6 zR(I?C!n6jj?ri@kxKsJFuhaZz`AgjPH~8sO2k9JH9@6Z{wf&~eH794qZM+Ae`DU=Z zPKH%{O@&X@lx!aq>s|Kx=r=Vl9hPrM9XDZOTNf5k+Z^Ox1>td4(Jzpq8@SUwf~1mr zS6Nnp<6P-8y^D)fd6Q>C;R+{S0N)MLk^68;VGIqOkcXCh3RX{$(c$B##t19>_Xqyg z!XgbSNv@a{a}f2eHi@DVl;hJHs9am@oX*K%u?LU*2=QCXB@w-945VQJBUwE@$lq>`h$R+^T-N5(!Q6W zTC(^j#NkbCQ1x<_BSmfKCnGZN+obNzZiS9>^p~=x zD_cQ)mWITWaz=B9T6_HT!XVc=E!fg_e5SEuJm=;G-jQ&6akIi42Y8kZxRwWvGy)F; zsZySiK0zdahzknNAJG=;s7{0Cuie`a^GsY0s>ubCP2tZAR?c+KfLoc{8-~qY@Pn9{W3e^u!n%Dc(4c(deYS=}4!xsEaz}RrRC3c1 zF^56q>tViKZd&INEifb0&ZU~cx;}MT#Af|9P6SFC>Em4|2~9`3&ZyZkN|kDtDNPM{ zN#)>kDqodszAqIfjs@N5uCt3i{qg$o(5lr0w6G9$BckOya3wj&`k7wMR&UUQ<+GIJ z#NKT?QJG;h2MNvh?^}b_h~XvU1mjB)qoH4@2i#uzg~IKvjBb7P91KORqQ7FSG+P-_ zmi#-PV*df%Kf`hVwiFq0!t7!z5u&N9Z~9Q+4+}IGZcEHof(1W3uT0jRy{@D3w&hBG zuLbL~op#v!kZTwj9rf!MxQ<*V-Set*4Y|zw3O{+>^RFG~KGR(gIfeX8M!wTA&$*#{ zaN-=U36K(qJphA|AJ%j}t1JkY_rHSG{#hZBh8dia>rL%B#3YC1<7O*eTau}Gd}Qd| zdm`JgA9zqt{KxL^sQ*9+#-IQxwc^lVH1#d0{@lXZF|>#6+jchH)%~{(5WY&k0RA2$ zX;+4Gf?HLzkGC}}IGkG#``2iZkXqJYqr7ceWYuW`$7}Xd*L&Y4z@uT?g9YK(+L|Kx zay5|kbAu}@Vo@`{JrO^fl#x@;tqcuzVtb_r+?CLG)FXTv0VwX=$;)Z4r-fas;6Yv? zA4&EWs7ywAu%BRM+rP_aQs<{;W z@ZJKfW^DW_IGTALAN~Uky8ycJJL-$}K<74oCEAzJuJh&(ro!dn9Tl&mB^+%Q` zeoyS)|8m#w?^UIVVi7b18xHX~`;wT4xk_lx1z1;Z@}!^#c2T7hW-p3MoV<~w8`P69 zH?c!WHGfVablB5*ZL}IWZ9<}JCwc^1)2H+b1&Jqc80;a?>_7=Vnm&>4U9W@9CQa@a zqZ05LahzQ{(yIhqI|aR*oRR21g$yo{-dTr3-Jh|>byts5!NZV$ogJboNBS9}HTYX( z+N@Mi<(ht;#Q2TibqTt3ZHwo%TMza0$)agBr8+US>n{{1d=QGh{21nWwlQa%d=Ot) z-z}PCL;>c}%c-+ab*HqMn&1y&?pKPYQ8<#@ALg;Mj~_@T4CblZ#c{pL!Xgl;(;=r(L^ z>fTNdp{zg0cTYYdf3BuT9|yGJv;Sibx%%+t=&q6In~$$FDzf4Z3+#phc~t5>hlx(E z^AbLd&MR1HJu8hNwr9>jj#Be`=VwyXUk%=28`oU-*K}h`ARqMWT3VEuh_FH=XeaSa z#@7ak!|IzkVy0vJj2-;DwByI3392F%Ca-D}U!A$ti04!2?B9ltG>1i)<%vna+qYYc z{m1R|iX@Jk{2129+GgsI4yEbz(CT07gj7|`-gnWCpT7j0%Uc0TW!al*yn zmC-_U(sKtEGs?x4+CQE>r8LM(%(~1C7<%2GZS!Q!wqKFUr;_QBn6l@XEf^GZeSRc8 z0kj2ernov>R zzIxU$qCP!VnwC1BtScDP56r-Lpm5z3JZuh1rMFlEbOTBe{qYKm0a-M@s4od4f!?md`86|@jXM$XBqIGiOcNpAMb+b0>=;sE&bv=wW|!Jm>$ zJ)$|7ZKhR4i8*r@PUx0(&KwNunm$^_tWwiGxKHVXyASUH;S64sdDqaQ2nc&0LUD~^ z9Bz+i&_ROVfhEhjvhp$v$aR4*l+8EumerIek0xVK&u|f@l>Lk3eoaUbe2Yd6i*@#I zV)U=n2)h(o)t?pWiZLi7pyFX#T_TgEP1wsoD`xhtHN`I7p~P0O;y#}-w3a|)8W>VK z2c^2HcIAb-3ungHKKefKLcGOno4E0$PNl%4y1Q%sltR*xn`*J)c;NF*mLj?mJSRHBvTsQx98eWn@juoxv z#`V6A2y`71(gPsW9^bcyu0daZGyl8{yeC-cAR=3t(@JKc5D6)049P<qTn;zE?4L z%u_WwAV_O`o=_97Xjxc9~2iGy!ch8R>>5y)h;=!P(?BGY9}~#y7l;oxofRvk&T3j?~EOUPKETzZNCoi zr*?iyk=4rurYC?z0Zc{{H5D4$Yw(Jm;YdX%_<2~HXs-plORb`=-5bn4FMlQ(${NQS zB4Lfan&cRrenL})Zf2oaTUpRzPg=q%fIPi(&dFMOo#WC%Pu%&#TY*63O+yvs!)o^9 z$nkWp3BqbykPM8Jw(dSJV=aH4{)79hC~qoXGtq9Q z=Fpi=tGX?yZ<}EXgNOT~-TaJG^ZwAE+v2MeO4*=`DaGQg{lmbxh88B&1 zNeJ)CW_oz5pBy*I3+)7iZ?IP%-h8S~vsgZ!xq7D; zo}|P=U{8mc+t<*v&3E%C&y1kwd(#Z%lJ|f?$RYaBZJY(LZv9=aY)R|x!50_E|j-WWwX#{7snre@)Sx1vpa zH$2#chxBUn-NDZFK~x8zVoI9={^|~`1pM%)h9*(Ok?ung5#Ke2*q8?`W^3lNp$n-) zLVf;stFHJ|BtwPFxG#Bg(xMdDxhhR1$CXSjA%X^Qj>5~aRg-mndnZLR%3w!S(n%C74k15qg@ltzW283aKZ1gT*N z0qIh@JERp*KzfLgZjhF4knRp?q#L9gerND`zW4oo*LV4kmvRmFx#yg{*IsMweZnZj zuK+%$loJ(vH=GSDhB4RD1IB9RenyseRh%R|*{bR# zYzy1k$kBqwXiPq+YHopz={ueWQIwv}+&xT)9iNq54;RrCzK2{G>=D!)hV;V1*6mN- zA5Hw-EhxUr;ZgviDD2#(yT)>@ouJ-!@fW8|hBaFmZ}*JmrwI8<6cX6_gef^UuooYz z8kNk)+Zz1wgffnS!BJ#5-Ak$K*AU3i0RqxaUA;+}Cn|fcUrag~nW3L$UZNsJE-A7p z9t~9vEy|KQ1Y0@w{dch!^zr7yx4ykhbcBGg|BWyjGCB8;af|t?=hEk1H^OryA+6kJ zX5W+ZZDn5DFmQTDfDITRd8N1#v*S)P&T`}Q9q7!+zmnA8ucd0xs3bTH_@6ZA*izc{5tj<@n8Ct(Re_XgfSd2GDshz~Gm*9(j9xP+qSFrfV&-DA+fI>8hKr#cK@;k~Q za4lA`2q~VI`y`Q?OPK1~TZvYegHhM>eB9Vigk!D%tQ1>l$ZzVljvg=AmgEk9$5O|L z>0SvrY)m#(!6sLC|M(s95RBW`+gNBL?0Uh3gA_?=*Ai5oD)@QU9;3`QnX|0iTWoJ9 zCX)Q;jT+R?<(>d3j$W8#e@2|&ARB*1@$jFy54LH#2EHy9Vr=SW9vM9xmKl4Zd^IZa zfz|}q$;xySG1^($uADJYd`Xqv+@_8N!&drQ-qp#Gst(s3caU(;Xn8W^OF3wm6#3MP<@X3)zP3QGQW3Uy?hO8OLgq; zT5&WGN)|Iz$WxVsCv?B(Dcs)fTS=()V|~=IgR$!=s+^5tjDnmcq`ivucfM;-0>lten>U`rHVK@EBYtp9oc`Dt9_Ol21GXl?cka!qj)Zgbg}7Z2_0v>$Z3 z3m`WWSn!@Y?jOHX&b8kxnVUX5l)v4y${AEz!My~`0&45fo?Q!ndOk^=i!*!^m$0Zk zR9O8w1&P9Dw6E6_YsLp~xG+&#ar?sm^za=Y{FeG*xeZ6Svf3=kddlKZ_(my6nd8m} zd&q-G=N?bB z*x_#C<8^VDW;FcR?bROpu0f602^EBfzbuH^JLJOEYZdG<)@6z9hv88m7u&oYjtP{b z!s7^H=e@(-o%rGBn@Q{YV;C{>XWacJRw*i%Vt(esZ!Nb>S*OHV4k+`mn#HxL;LMia zt+BETv5$^}kcDwYvQrQISSZg*Ul!1uX|z5wur)m=Q1srY_5jEKZM8M5gfXQYVGTPI z)gO1&L0f%dYv+?o$x$&G5ghxe{h9^fN2mwgu5S5WVskbWLerH%OlgpyC@^Dqg8MOH z#-b?h{58Q1=OWv*&$HRCxn&}6{C>P=|J`s=6+uy>i|nT0Fr>LH?!lLS%2hj+K&sKr zJNt~~{w(5ley2)DcH-97DYkA zz4cETM5(waezUyJf!j3PZoBBuXK;kG!1I#3J%9 z>P=Fil2RB7epw)&le6x~_;b^TF79TT{)j8x6waOvySabaTrP83<(Su>V2EDWa<#+g zVK>`DOsV;c+H^LJl%X(G6H)bcMsQ7OlFku3HDD&G((s2IL%HHK1X48!vi3m_{eubQ zqZ8RUA>JCjH}L2Wbb>xYRU8ZXWmen6;$m+GV<+-vmUU8Zt{uM&eRB1Ws29WR&OM* zqL$HdUcdTLC+QV*a6R3X*!UxGd zdlgaMaOAhRW%aX_4l-a&LHh~oh-J;MlFtv4##%9v;YL;};76j(FVDh+-Da6*Hzeis zk}Pq0xtIJ-1g{2ROscmt;2HRS-xbK(a>TMb8jhl$aM+9uZR;bf&B7GzEn+<|Cr(jY z=OMo12+zaP7vIXbrTacl_LVa~_h>U?$%OIN^-+~ zDTs!FKYwVJ4`OTqgprB{Pt$>)a~{)M(^;0OLnEET{Xt{O4rss9?Yt(IV0`PAQ8q>lNAye zyo&W^m`#!}p@zIwdvps*zxu$~v%cv~yKnZp zkuHT{Ltn3vD@n#QTLb8-LBGAhJ(sC8HNpQ+#JF|^N z#c2DddDX>25B^${g(_3eZjmUnA=JH#gybtzZ(XQ$d|w;m?%l7*Rmi$3Eq2@-{1&%N z9#(~r8_2;Y+?x_iUqxYHWVj$0Vf5a1kLbdXB3<1rhJRtTsna4jZg6)_Ih*z1p&0?P z*xtD3s)vmO2e94sZ~8d!_NIrOGv7isL1kFnUSs0jWBC#=5v8YG)Sg-9lj&Jno>(1~ z!Jw6RT_E2dgzOYZV19K;cPxpEhi4s&*ARKh(&C>=YkOW=yuLO3 z%`w(qcZ{ZehS$93V`jm<5)W#ty|imD8mPJ$%2Qb|$n*VTS})et43yl?7O=Dpq6Iav zmjqvQu-^pLB_IGmqJYvf7u!t4wdt%`Jb@#rb)~2uA0-~;85DU)#z`68e6I#ZZ9|QR zH3pOnTLklND`MYkIt(SZf(b(}*EmT>u*Q+o;i(%V0~Usr`XAY>Kxcc1g3KgGtTb;$ zN>i+^qyWG9#dq#iGO8@$GP3JfP+yfg%jlf!%I&h9U`^v;D@(Pr+GOM9p5tNjC3SY{ zQE8MXSO#xi*1zlishU=>$&l^xJ%|jLWta<} zvzd%@Pwy}*iPyjjdCe$s^)*DyZW4=FOH75~v`E#$1ou3$>uC=Q-X+~FtnHQ=SQL)xvP%`hf&yq@yQ zapNf{KC9=UZD4X>XYyTN?sN9fA*H$7omXN3ZCXw{WB+0wvgPDUomaK{n`|!l`jD%^ zkqg>Pyz^@lX0M|kTt+i~CZ7_iZ3Dx-QFQ^-xUrJ@2p4vGvpWIKL&%Dcu38-#>Fh(v zy}+<%=OMgFI#ik8`eOb9>B#mq*#TBn2aD6YT%4Nwj-$#2^~13^rZ!0tE%#RVhTy(4 zh6fvrkf=<}?b)|8*V<}P=GGsS@xZ2?jN$e8-LAP3hB8c}fh8?Gf(3Y3S~X!)2K*<2%#E?k*unvVL4A9_5%R*~F{?irprI!0Oe!0qrFQ@u4;+ z)X!~g=k2pqiye{okAvXJGwI4s`AyG#W!9!FouJ7_kER0o%v1T>oBR3aX zU1Pmuwj!%cRScElQCb8Vnu;{CDeYTIANPdDh&EWj=JOx%ezNiEB+=oMx8i!|alRl< zxXOBoHS3Q3z}p~m-04ddz)tbKF1d2k;gv({ZO*eVq{5{S%%gYX7$08J6BCzv$h9_u zro3z5jY#dK`oZY~^*dAiHWJKHc@>pmqJ~YUg%sKI6U9}T#hLHy|JfJrY$!}lhHV%B z;t)wVNayyxk~)Ecszzt3DAi~!qQ0fr7OSHw^*-XK>W7^dID$$wHsXe3G6@RHwW`H7 zF>1!88l#4@X<$4W;QIb(B4h;<99~dY)d%@z05vvGlub>;-8R3)%64j;Y@W zV|bqSh#-~@3F;0+D_Hg{BAItXHul7@mNx>qHo^W2<3diVwLV1Z)<6D={m2lvCksbv zlXFs9LbkmFoK>>7eY#}jEVgC<#lz+SZX>t66PI2H6a@Yg>1IJ{Z7!(sRfre{c6ASP z$@8KfYpiJJ&zng+7h1HN!e<#@mMml)&6zBM9%(+!b+E__SWb80OCND5XLd-E;mLld zKxKAkQ%^aT9P`=rclGns3RX-?7Pfw8@SfadS{M1$x5ceTx!zFi_BPYhep+Y@@te)pX_%B)R7; z`ku+4FMWGUc`t|$PoJN$?smqVVkVETJa?9t&v!LJF<4Bz9edOnT(+7hsvGqy5N>lj zm5J`xY4HdSsGvxmEhQNgRkmbdsp~htur0LG!0Y}R`+!p0{e9oMxnqq}gr0`Aq1_2p z1?=EiVKJ8LYnxNgD^f*P9v~;QRk-Lo z*CsTaYDLCoUJv9m0PKW9PXk|UVC?G0!NGH{n=phAdkT+_|LkbF4V|PIkDfi&;bS(Z zzWjx|*1h*y&AV$P?3}(sRHZsvc|3-UYI!kYho*VyMAeslf=JyWR8Y}=RYNWbsDR~z zizQNB4CK-Vvw}SLTOsC)hz4es`MsS`?^aC7j@6vvFLJ$~h6a^nd+2uYzn8o8xn0mk zF8h0$SG-9q9?zuYSS01<{%&2kp%uN?G)akn?M*=gv@~_Q#q+ouTa-xZ*ym!3;jT9@ z$B9O|6KzN5>U6R$c!dAb!Z2k={Ty7LzpCUpD%x>(HJmh#y`7Qy4eb>lEaH4hK={w@ zFUER2^t-Ga50U-UWk^>)KXv7@2m|+m=t0nI(dV<1mV*aIW7?(X?Db5h7(YJQ9*-kWbM@#sAi`Sq=G!@drz zN`YFxuLo|qpteGyyyNsH^?>!-%z%al%zP%U>CWAghvSV)0c#M5qYS!&!2tpUO4XE9JCMOqI%qLsI5l_+|eYbJ`& zn=j&~nKoVp1L`&a6x^IzE@D`LvW&~mJQXT^!quJaL{0L{Y9=|h1uY}(9Y5y+Rp7+p zm2Gx1)_D8(0Fs&7x7G1Pf&%haOAlv;PSjwXkfdl-PDcCKU=7oqo)z?>Sfq93DPXtG zQ{IkV_a5Z$>jp(=dv*C%i<$9rH%Wfyf{KC4iV&^aJlB*jutqhNZ^a5qT}4YDY~D8L zqoA%!v<%xwce8K%cH^H=Z1Z!vn)z2r73N(1^apc-nX=^qm7julJ$vv%+u6@7{GGaW z7os*#F1^R0lH=(kY7My-ETXVjcPfjIQWJ>GpWYQtWjrtJv0g^+o*}t;G<{_1l1}&y z;yiw@E{EdW-t-L`-|vG!Tp~O&OV-o^)18Ydhq)fH3gV~>q&zAfl55S9Rh&|? zpfr0)nzGZOnvjkm$ zjEp>^q}{gQEVzr~T45<>1(TDz?SG7!S#Sts24AUb>PDcaX~i1!3Gk(b^T-qhh)u$sC*)l+CLN-5<_S7Z#`wcd8T@U?<$Ww3> z;_k{KuP*h2YWdr?W6cSv?sa7GmrmRDMN0`{fJ;hR%%1I7BZ}1jm8JfGvN4aV=H7bH zfDPUj(<_1c17^LOqg|eJJuIyb)8ZM4yk`ZEr^AnfiQW6sWO)V^TsXck#)e}p;J*B} z%(C8~s%PH>v8O_yDu?n^MQfP4CO(?ctXDv`C8h@zEi&`QP%}z$LM{ALvd^Qc6G2(U z{NbSxejH@+*S_#z`a$mGI23P!_Ud5;b!h;WiQhX)=w%$Uwxa4T)VRoY8GyK{jDV(U z`WHsZVu8H=?(LSj&?$a{wwJ+{6J}bPj}+|$Dr9v}W1YhAAR&0fXey1T&~=w~@4Pj4 z>;sgc6;SiQ%*Vw&-zNIHs7g=6jn}U#gp~&C-wgEAdF2M;*dn1E(MT;-^%E|ZcMBt-w%O6}vIgeYyXj_bM3KOu4 zEOIRk$8y!MV8{Cjkt@a697tm)KoAR#4EEp9kgx1xbJD;Tm8$Y4&bc;aW`48s{y+$<2i>}!J}AEjE@S8Xmk&d zc1a492NdBk?s@mcC(bqTQbbe3$`{XMG)MVHrY=sA1QXLw_J%J=_gX397-O3P=_-*4 zhH@gepzXn5djqHM*>`1%YctU~0$D@k_WbB<_Gu&cVtvlLiWf=lyx&WPVorF$8E1Ha z49`*IuTimS(jA~Wm%3@*RSk^)geKq4L^^6U+KGC4a7hp+X;1L<4DJ*hg9a4b%naJT@-&GyGS@tnA@lt zR$9eP^gO<1zG?L-ruFyiZ=e*rnZTVLnr?8LmV zlV@>TAxrA^(HmB&3{^_hc1G#!>x~dd%iJ_3w}S5H4X^H<{tEnDG5bJBg-@J5{g?UD zh}Lzof+?|NvAu!#K{gH$MShXYls?sQCo7eFVUA_`#RdH^LGi#q=c@JDQpTAaFY2|k z83x2$+4xZhtsILwWQW>{^#tPpuV5=A_i0s~s-J}0g+}u*C=CA+$Lj%rkT7QdGhaOi zoID?tDn>HgG^mHczyP!dpvFW)1Md+Jty%a}c`7ijU&=WcQd^}f2#%#CP!8zq#Vh$% zrdBn6+FA$Rg7IICpOWZ@$z5r4sKUDY>sxL>+c8Keh|X?u-u;8R&yDQ5XdU?)r@vDX z&K4$!2~6kzSiwP<|CsN z3jD$e4dD25haWk?;s3v^>u7&69%u}NJ`UQSpNZRj!7+R>4$>N9>(m&(XVjz>;7F%bW`MxL~S&6gguW{PcCM=se;(yyJ4^-8>qwJu{YV zL$>o(TQAT*l7e4u10F+Tpk<-a-7nQNMVF+LM1jg=fA7deN@aUWBf1qh&m^%-y;kMtMtXujwP! z|N7WEu0zRaxoKbs2`nmtBFAgkii(K<3lo?u?2yq%9OE-?9DNL^%z zvm#^3$j!*U{(_h@md#*}xg4o)%xns2EIVPK*SpclgJCva48jg$BvV2g_K{&#-yS{K zC(dYI)MP@XgxnWKyOor+&#i=aZ-e(N41O)j)O_Q2?|3D3wAlb1MaKo89m(^_L zh@0k_&6_HLG#Na_rbv3jM^%4+bq_?*adiXwp>U-fbCiucA1nAyt?#$*igCDa9!w@Y zvw^8qObw;XxMoUKZY6%waw|JxoVQ~7VKMWCwoOp_{ujj1v-Hls1Doy7snNUmw-f7mv$ud z9+DHqiS^VqnJ+rnoAOO=YgoFTBsUsKM0gZd58VINL(Y)^E%4UUol7|KrXX%8 znIqunCyw`<=c#4=x%e>DV_>@brAoiFl%+*h* z;`ZMI_8UeX%)b)RESy ztht(l#l7_WIo@|k`xRhy5;U<1t`hG|^B)cSGZgZ&ly17N%KXfyI9#@RcAha$(wJ32 zpu@(-xjWI#K==>4J72nU&CHl#-SemJ9|ehU2qf}Rn;D!fG=RO)fIqAQ7F5+*)X@fC zyo@!yd6M&Pxy>45Bnl45q-GJSm&#|wfNcadC96p+<-it~Wys^QTgNto}Sb zT=o(~1))PB^<>;%;}?yi}W?wMBTWMkrRu{+i`HOu>Gv#wH@ zWHWwgezZvrzOwFL3h*Y0d2=Ryld~P%-iXTNf8z(BqGx}*dg;#1jqyi$-;qPw?eqrm zTNObo>XsH(K)1jv4LnYq7u?a#=VNBi&oYKsVx(Lvh^T$w$tn>eQSO`bor z*v-HmZsy@0t0aNl`Wf{sq}};vN!veLf4#Qt;;I5N+d%u`f`i(b{XqaDskm*d3`^uW z?TLQzhto(LfN}QF{`#(^2Bs!z?K6K8u)Gt$wtzu>-R3T__AY z7fZVpgEM}~?3}wZYtowSyGoq@>y#&48uIap_B@l@aZH+cRY-BSb=Jj3h%p?gGp7Z5 z;;!uL7Cm(DvuxX0;sblhdrdrL#~dv?+rB@KpaN~oyp>tZ3EjrWxQ=%3yE#Zoul91} z*Va`n?xwJq=5DR4g|&t)+$|8@@<~k%KD35$3)Ya!ke99|HY)b7-Zt6nNVw0}P74AJ zSP9CghDOJOZ1Sz8-#IOb!AI`5Qi$I>z*h>oMoje(Ytd|V$A#bWJ%tR8287wRHbw-u zSr*nT*TIzsxBM#XVIGxP%O#P-fOw3n@I z`~$14mcj83cxZd@&_~=gRG@EjUk>h06%rZPQIqmACRA|75ZItVXD|CsDYjx~VI~z#Ux& z6|hd0J+leXc0MinCccu!`$O)_uH^cgqA?=_K97Gop10kGLY!p*=$)%NZ9vLmjus$`rE+S&9yhDmZ2;W0Q3mBYkx*lMnfxpN%lMTr0Wxg%O_sz= zV7vaG(48oui6AbnyKuuiidi2k1_rhKY|cgw&_Y?xPLfzBrn?HR<|MaRVd+e{Ri4V> z2xCv_Twl)OO_KakAHdX&;lM(xhHY^%sk9iGfBoel+Z2SX%2PG!hkx4|iY?CFuF29l z_?jmR6_o$_rYa+fpv6X86sggyWCRg{1}b*QDYZ}B{s}QxL5gVKzD(kO)c;Htqu5MC zo~>0AXm^aQaaY*xr%?<=d$DyU%FFww`Hj;zuMXrj@OEZjC3$0AD-ZvCMbGSE>PUl~ z=7E#L&;)4IGZE38`Q`H(N)yZFE`V^kL;bylpbsJ7L&cQ$hOH)EFeLz4+~Cl zCAjSa@3=RKuy^6yeQa`r58hYutkL~8<8){6o0W~F3;LF z4sFf25mS-_?_vc!xyb4>xW9>NOFvQsZSe<#V+yg$CzL(0hM z$ve)3fleBtvBfn`lir|^@q~9oz{g|dgeXt4TpN}np0|<{(h>8$s>Z2VO{6N?Z@dxc zLUq+@Qe(2`=)5>zG>RLtv_4+GS20y;x|#Cjzt<*Lm3o^nfmEw~IH8x`4QcNvnV|PF z9=IT>c=yBNWHtNA zMgsL(OMsT;SK1DjpEp30bRK)Sb%a z7P6LkS|y-VjlqmB0{6Gyj~oag&npmMNEKGTCYw-57D%VUv&Tf1ubcF)3N2h!`+Da# zn2L_V$LKvCS~3PBuM8NM4*^&(HrGVxP8tY>vc|JPGWOm^s7sb4KKVd#{oSoW_eh>Z zcz0e7>G^36WIOf#;fXHc;8tKU(Kr9Bp7YGgEuaQkgPyM9E;^cuejSvy5`t;$sz;yoTp25A8C#2~FWs0^^r5Ry_loowSY?~*0AdYRjuMWnWo7<2 zU@WGo{DjC?UF^1BYsf#e@}8t8O?tca|5czbE$ANor=UPnnSuIs`lG~(TgdQW5Rp+! z*i%OB8vX+X(?DKKq7!O`hN=!IeVKQaIL#-RDk_o1nh?40XFvTc zOInKLz4%5|&NhS_JL`;N2;Q+_f1=ekT{WX~WuZMq_AtkkoC^8I%^fHH*pBciuNM~4 zM92IDO=K)}U*ZifT(&HnE{nXw&eJg*T@TfVwEHNSjtVWPUAjI2VI6N{(m0GM;~BQ( z0y`ojYZ43(M6Xv)0!R&kwGmBhALJU}<&4#bH4YroqD081l@pGG4=JfO9ZUC(sTEcR zEAOII4A8M_L?GI>JB)>oSV`WpR6lx646SVOw>Bn`+oz$5G>_ z-c47ve2&u)xT96K=-IlT)*sqKX$J=yCAtXiWZeP z_dRJ_JZgr|0WE>C+8S=M?9HQq=z#F~GX-cJ4ZB~TlO zN|c|vWo&so24!JWHK(B^Pkz$slFJQZ!sfI?glqGPxO9S>OfUU>E$_puJUeY)Ztj}Z zS`%ZmLaX;vFG~^v;2<=x^3;(cH6ZEnK-W!6&y_B%q#Zpn_Z-QV^0aa=bfbca#NEUQw#pj zQqG-idY<*ht2@f3%(Fd~EX`kH-NSTfTXk+YhK;wsR!N6M#c4(H58Bt-<|z!P%|ziR z45%ybH{2TmUF1VN5V?N&t=wM)e9W|7nU8ZCU&fm-@|zv_=Rp&=X@Ox7(s=K4glr92 zwo5ycpH3vX#8qwgU;DnuN0qZ$PiV`(7D^Nzed!6ep{&7TGZ`@PwElj^Kzgu~l*2#vTF??6Zx;c}hg1}Y7 zGbjAchf|Umh%a+u>a=9u)%faA;ca$nSFvpt;CK#TCBC4n5v2Siy&tQcn#sRxEGA z*FOwrzQ@oH%r_0B438U?J$gL(+v!GSDnrIASB`v*&7rYOU2T#7bQ&Oj3LbLhbf^0K z{_{-#Q)kQ5-rw|;$bEXh$@iN6|8^Pd=WACMo?zcUy~CbpZ17TRDL~VGgU9u{tD*Z< z*<$Ifikc~jo^K=-$!FivyS}nsn_aH!e3T+XR!J=;E%jV~XWHnuRQ8TFmsV_9)->OA z_KcMb;Zot}g(`-!ULLx;@pY&}WNd9FHhVvaT`aIvMzh?t|2=iL!R~q8H$^B5wkM?H zGwq!hEVADx(Vs9ayX`2q>RWA2PWXForq-+eyjWJ%cZ@Cy{v4qscBkYPJf#&h;VgO1 z%W5m8IX;v`p?=_S(!GDhje9=<$d($of5xny%o9OJlD;~n28Y?fimj4(4awtXhYhI4tYk}uk7-191Bd)$-D*x;rk606BRZ2)GFLqx?|{6<-IXU zcC~8{@6ykuX7q|8gvR-ku6qxtqcEj*Q6(bk59mv1hp_=~IOq_Ff4&OCv0wKxuB0|8 zSxQG=o<8QWPmtxg(6GngZ`XLoR(21iB3)a~8-7_RJYvm3 zwRgf+wj6X+s5SArMQF)xOElpKk}3$Q$6H8lB7)(&J~3hqn;D_iDs{Pd35og0y}_kE zh%sOxv#n1H-SdpIb_{Iy0ua`1CMzRwqVw3EHYTcR}$`ddrzLJNAK_ z*f_t00P+ymc(n%`HB1EL=kVC4VHrq+hs~IeACoRO0Sn|0sHQyP&1jZ6YcOXFXwDIj zo=4BAkrc&j7gw~n`a0~y&(6(4S`2pJKvq38)k^w&OLt})v^VBWcfGr0u95&(2~k%t z{I;mf59ymoiB+k@DXP1xk18WUh(rRjDUrAYda~(oR2|FoQzub8Znfbz&epK~C1*&S z2@5SiP_H@{%O~c;*{)W3?ng+6d8tKWmkTCZH{&a$j}i(X1;Qmb-WcHmR0>uAG_fp= zy%&b@S=?j)H5!5dleG1^m_~-<8Wn;IcmAy764byYmwaPDcOfmJ32Ph};oC3DUw<{a zAp!=tc*%+FMEvF`FXpC0doDAeW+X7Dd=p#o%S8F|S8uLH&8OIHTCYu&XeUJ)_ z`bl^af73OJCGdr>**-dxVanyTd2UFAa*+I`B~TIjnh_PVg88u?#_4}1^#DW07QnQG z(cR#!F>Za!K8v+}%i6c`Ap;4$$X(I||KoP@Eaolkp)g)>&7s{QC{s*UCm3m=tM|!S zoS#VSE03huroiS?K7H|RM}MH1+4=k|un&T*-G6jvMy=unK926e4|Um91d$)t%Dl)x zfu#?B?dTP4q;M6---q>t&)uh&VL2tV_1^u*_J`t7u9-*h6DmhgUSr)NxtNg&W9Jfbzhi zqeI%sjzbC->k_iIo)V}r`zmQjc0%Ojb`=##`Pu>}R^Kky4Mc{R4~i@7}g8P+wQo32ttMh(BkD~unhx=2K{EVww$ z1bf=mTY#P)B?lKc{IFaG+gR71!g>)5*+|~%HW+YP8P$&w5=gSpapFr)-}vSR+~QAo zPC=tIoM7t$SXxZACdYwjt>^%i{XdsxvxTs5Sljwe#< zw*U@%fBy$+a=sToWqTf{-6Fx&l;fW4aT9y$?A|?zp%1)J#WpWw6)8iT&-^T_17# zBW46fVE?DdqhFn56#Szz0vLp)CMMZt|(J-4(FHyu?QNZF$67?{X0tnRV( z+-SyZAvQD{Kn#(SUmh2~u1G&(d%0ktjNku8D=_^5i|1s7*3S3h&=Hr0ivf~WghlCy zrSB?y|F+fq9Wa&%uuOEiU=~>$PA_&vuv3FB%`R|X*SOc>MZYEH035AMzfGpHZ2TW! zVzrsP?t<;8fbXs;(=pR*a=&%4BQx={(cx$8sr!L5oao5#lH|@74%PS?mXI^g4>G#9 zruN#u5IUc|T6V46(8|E9s;uwQ7z*B!{cQ3%dsKHV^HFx}xX`N3)q~uJ8ba10lucDDw|w?nr~{#CgNElSPYL*+z{jIXS&v=JMF3^bj0o z>QHoe`5()Ko9srH&s~~Ul4IpjISLgw>ZaNelyU!3%TIOHqRkji>2&;j+s={csIQQ( z06gH|cm3DL0WjoQiwI0Of;Xe7uBwbZN6#BxNj()cD&n3bZcR``q42`U19aGu8itH{ zecgK_UsyeUY82S z=1!nvwNPc(OeiW=d3=!u9o2#dxXq*r>eDKhrOeT#K9U>z%U57vUpa8t`Xk>I!PX%c zn;#F5YU}eq7C8)_#m>dNMh&B}6D#;dph5Z2_A2?U#=u6bVd*Pk)Ucc6gU9780;a*QpZBoGSkm`iW-ns;tfh zozl^^w~Pp1v)(W=vl_nkr$@=~&Svdm4!z$%*W-nyPkqD{W{ot#f!_&YB8cR69ARb^ zb6qnHHwV`Ue9p7~tP4Pfx?8XMgeI>@#Dg@;Qi2LR(MK1B`Y# z%a+H7%?@QV!)iax0xe3hV87)xTU%hP9gLg%Kigv@Bydm;6dFKzz1*C++`PJxczlBN zI6(q0W`KVkk9&nSuVFa)yx??M#02&Q$winH4t^3tv??&?sOg?2l(DzFxyxJ9AguyL zGalf&y?+~8H^7F$KI_rY{9mP<;1Z1?Lmj|GEOpOUV56FrT5g-8C*AYL7%KNLR8U1* z(s8J8_fj`Hxc)J#aKXo`JWe~XDdtG1#>rj6e}g6GrwQulp_wisa6;RY&4?3%4WAG@ zLf?*bN$;UY*d+6rz@8ruE)qYnTMC}AjiXs4Q0|7L@lqhbtxZeiUhs}l$i+6eod<%3 z_TJ78)sJ=!osh*sD4r{##2&^jsBYs_OLr{i@iZ182@PnEN8tZJQP#GUqCttAaEg= zp9Zd;D1@_lIT&RgH;B{Ic6`|o;r>!1RFAa^Mt4Zola1M}|$h&s!O16%@ zTV8&{KK=4A$!Pihzq3)W31^HhQy{=*u=)ri^}eowP^L{S1t)oNi`$Fe_f}6h0w2cf zwGdK9A#5gYdn6#Dcg_aCsfEg=3-CzTBqU;laoZ+aJBLG{ll`*-$V8*+c?>Y z9*x6Z>bn{7REbdAP@YgmTObe8jlK^7d0?IT93zS)TphXJbFvRE0M@K2CvQ8R5UTkL zbwNOrER?md@lWYo==!>cf;rQ=yPFb;9gg11jT9Fc{p=gdwvxYWobIY|3K_83dV*>V z^we?iI0CmvI@Y*UrFuVkDVTP3uvrD%PS+WU?MqFTg|C+42LHj-$H-650MP&DXj9F< z;Kp#plU?^XgmSh*t%hxU0Qi+n?b^scm7Lkme>swA$%wEG?OOiO*Z2Ie#V})w66(@i z>#I&d`_;mIIsC()1r?@{8cNg{5HwJp;pMt;34G@$BMJTf?){aAf#+L^SX(>GQuc3Q z(?v$!UKGNMaza{T3b)27O_*82gweaZ6gZfP!_(l&?moP@^k)n?>MGGaWnrk)dVP`f zySR!}Tni&Max4bBmDotHOcC7m414E%BR+U3DjIc*uRKgHnw+%{Y6k;) z9f;=ha?`i&Si%0bhy&)mG-3h_W@t&f5vKcaZ!l+lHT=t*P}SB|hJ6r^!&vj~D5uvU zP<<+uQZlD=ECLgffq}q+m(#`FlKzj=Vx6#Moj=N&nDuI@X^FSf?8-iCt^13F>-%o# z&q36aqP;uN#6x11b(g8{`lyN1J&+#goGxNj`&g*%!xV&{XB`DjQ|x=m1`!_nJd+67C4#)W!a9vvDkew~7wfGYA+V)`4GA4TqmRHB zNFocJg)0kYQ5+En3aP^H@N?0h$4yVZ{SkC+o%?Z$s-c_<)!AtKnZba-McR{vL@Md~ z%o{70pRPc&Hxy|WN#Pkp{nnP3ZyU*FF(|~ivQqTdvC40OOJd_g0M!x_;v0K3Cwi?=pr_3@DZa`Js2 zHv?7Av%7X8jI7`7xwvyV^%7Jf#oKiu>DYroePC<>=*e*X-87fhqSei4xTdu95SV8) zS;)nVyP`&9R}fo=#*{v}vdJyV!9$q#bWyjF#qq0~n-?B8Mv2aQug-fxhlkHgDLgzB zBaD{#Q&WCF(6CGc$pp>tD+Ymu%#?Z6}+wyEbo}}!4F0q3SHR#wxSj0AbBn4soofl|80xC5|dv-VD5!2sF4lTqI+0=by7S>kP zX>QZV-B>jLII|-ltd{EDlTg&`F^ARzN2$Z8`wv-P;Gt(5g7Cu!wlVJRQpxFN-Ru^A+eREQHO9M9@u2u_!sG zs6_wk`NH6HH$QWI5^hWmlY_IbPYKqD19?FPK0w_6{ZE1+;mPh8z2<-FbNMY+C2N z2JKyCdUl>}wkIc64&qXM>g~AAU*o7Q_1+6#eJbJ2L`+i#gqHRZs)_`y|2(!Zc1m*2 zi!UUxKAko6jboja;~8$;Z7lp3B!QYdRjrSjE>mCd@}$8LGev)1Tf3BdZ8%&b;M9Y; zzhjKh-rR-yg?@L_h+I04G+*4wMUCX5U<9Lc-xZBrkGKG%z3fcr&J;469*&t97c=Wo z8nIHzc`;*iJTg~YmFN9@X2?6Ex>UBeDKvJ+yFp2FeW0Iesr7v}`|#<;3b0v&bo~F= zd&{7>y60V#C_xf}2PX;cEF4Y)7?=Lvt^7a(^^qXgoFX~ijqr(M?w`u^7B3pup^GT7~r)(|2m+qddW z=f0Bi>vpR)poHNTf)9L5@Y})5LVi)o?c!JP*MeWvmEs=^K6^ zrmQ-Q0O87eU-Y5XAUzchJ_7zn5po#{S{*iNmX3N0LY0P)vW zJkD!OaMOUeIsP=VMG$0;guqFe-p$B2*b&t~Qh|c3znU-A>++Y4X4O^E z|FOX5qzp1d*nE~X_<;dLp0bcslA&kkvl1D-eU1RHRV#yM*^d+q1k_t}FZd_#nFwRw zge?eUufZ)m=)ZO5&jdZ{GJ)pK)!pQtO61Z)&hHGHKn(CcNE8YaRQQQY6*jgY^RE%W zA+8P~1-l6_?fKJm-GXym$6}?Qw|Gys%J2fN999^a;pd93j^JZWpUyu=$+I{HvWj_hND zoqHNig!Dq}Hc&Xy39s9SFBG>k=sek}!=ge8QKbv_Y9A+U_z;S-KUUw_6BHpBvpv@w zz;}k0{tdf-HM%&v3Ie+nQomnv2*A?b3GWZgEmh~`(Db*1rVBsojH5(}wFY+=euk)( zKm@>#T^b|3a?|kb=A8?K!XWVE%$7Ljv5<3+Ub3^s#oO>LncPjO)cv4vG&32Tdm5Ka z7$-dj486cRZVg`N{9cp$Gr7!5=w}Cu&)FB4pK6+^fu?^qq1P3P0{EfkP;9CF{le9L z4|DtKFEap=?1#6(ed_hPQaUT%G-5!5M4|^{K3jwEhfGl#upix~Ajq8)k6MZF_#8QX zaDTqFR&kFZZ|CDBXR+#yr9t?lr*3g#M!`H8^Cycc}uy< z5C|r7-|b&;mg+A7TE`buzM+8?T_(u>#(h2uFI3vLqPUlLeMvEDXksVH2iI`0izR|@ zfZu5fr31z|Q!z%mVY}#0&&EFSm0|5~uRGYv=+P7MpEA!W(IJ?i-e}HSBS*k4!*}C* zpcWAh)NXTDIFUCKr6_l~=9;wLN@U*x8p{+Za@qBvbC$2=uGxqVcg-(F2f_(5Vsf;& zcu6~;tX3!%BT5n@IF88urVTri=*&&8gOH(k*0Qt#a_HtT|09hw;m{J|JY1M83mlXp ze8De^(86$JL+it~hDB~}in7SFz5Lz?^jx0`J}xqNk5!?0o6p=IXt8!LE7%+;P_h*exeliQ@8&=KD&<>*E9INz z_@pMDx(ZzT`fk~c53*9PI@>9Iy+VF@6}XK`%(b_=?|co-4rG&>Spad;QZl`Xq>1H+RfO$v@|;^ zT~_9oB`cTtyu$-zwY0FvA#;MCsLFh4j6C5b4^|~mwI+71fIW;f5u+DO@6HF~g8Zwo zSfat$_g-fLI(-4NE$1yfK1A>U#(X0KpV6l>41p9Gi*}82p8KCPaIITn z|7y?rJ*&*!^5sT&RRGXG_uKZwy8R&E^h+lmKx#lz4P>n~#Ghlaqi!|)k|kmVhot5L z9w9fjX*n{_nBgHQo(4srxgU_=+#}#mQ>cy2$T>zcYe^Y4I^o*p@qGxd%dmmxuBJQ_ zZ6;Auk};ur>telftCitoFp|LI8o_3N{704Qdft{5GGj@ZBUI8!{3!Br29ci#U#K0gMyr!Y`*fJ48kG(S5W zXd%o2iL9TY0-(_La9q{FocgG~f{Cpe3RJL~+61=c#jth_+4f4ypurRlA0KP1DREk#@iw~l)i@{VQC1Uou021%>mC&z_i+yS z{2uRJ?N^suF(g0$vCA@_f6EA2)%#&s0aXZwgreYM|93n-s`^mX_C`TSKH1%09e#dbH0Q=#NEEwB*91`f{)6aCrplP~nn0?Rv4axO7raBJks^ z5&>D>!5!1QZ#dE{*De;U-+Dfh`*YeShJ$M@WT+4Od}1?!)bt6xB{<(@s}3)l1w|#O z-p4ouJn`bT6ZP@P2r|FtZdsN5*O4{i`kFJD z>K>zI_mRs6+vV8;jf@w{r{>2O9cvJMXSC>Jt>RwhirG&2g06r7&7^TQ!uBU92_xIY^X0XHNCzz)yS;Iz(OJP9(X$Qw z6FJ6*j#Rsa#hNk+?F`Jdl+4EYjroMBm(L>0%t0CJ=8dK^yQZxX`lk_6EZ$unt|6awYt-^Es zHKh9~c^FWZ3aWmjXoND}G8S1*hJe#_4+095dleY=*vtNb_kB!hk8wl6gVtu}{5<36 z6ScnESLGCh*_VgHWoct?gre{-%Z-)$tsc?m4LWpMgyG0L%Xr-5bIl!K-Bz)@Rq`*& zTv?gfW}0G?wQ{(NTBTX6ZQ+!oFXGL;JGZB8qUNCQ;?4yhi&EC+k}-w={-! zQ-UwSA7bwcikg8;LFyO-c$?NB+H1vJ2q-jGNFrqG)a_Z7J9tDP>Ah3EGGUTP*kbr0NslP=rVa(CeZA3$+6Du@PHy8p`{DljiEG zvMD%A>$2zSL!Ynq#LP-Ib8>1c3#l2!!Ri+}w=2jHSR}x&0HyQkGj#^qlqKsxXH=(b zu4*Y;53?aws}y!IRvy`;F(*=Hu-GSY(c1+Hqh!-9*Gt|juNtpz>CA{v6nLp)(}RGL zs$B~O@Z`?Kfyz5Z>rkIZ-n{$3W_tVFM|}!7PR@earsrcw4;Q5k4C3DSK-7bAFIMqV z`eZxKKCfga$5Ch;7>g?JZxiNJm8mndKg^(FHb!o%39rJn>I-rVPsgom-K~w2xC4y2C!s+CjgduOmz*3bTrR2Mq>O3TL|Ke-U?(k4m!ab^W^Yn$XBQ@TEZ z7DV~w5ED}qSuq`~9ZX!zB_1>@&%gQ}?49pHkK~h5ej?0~jyZj2mA$woz zR3sU`D7q@g_^G6ho>8j5a9N(*-VXKr0^cdpn--t~-?TzakGh@Uhs$db5+-|6UcP&q zqniDe(pbex4u|U2M%}YK#&pl;BQU`-6dULKp6{G1)rVy66*XOK9Ud$f1FP}Zg7%e@ z4FD#%XL3B!tMnr;FL9ts&ojrW>>hUK;e#hVHM2TpvaGY` zBtjaI&T{L#h}8XCML!rR?~`mkq*#=K9!Ge#?FPq97S*^Mf{C~My=qTs(QB9wkD70OFtXnjl-zT7U_w-0#uWDFBw>Vc-xmqY_dO(3i&uaaM0%2>D*VE&&DlI+lfZ9zdG4j2vyE>opo?kKwJ-^>Y5CHaj zp4IC&XmDpab*xXx)#h+lirDoy=-a(`n*Mydovt$VYhf^AiRSrb!!EB*t0u2Rhfj8@sT;@U{+G;ZIk9cL*Yu!N?s{zV>l=#k*N$>z7yK3A8&7B@S7y?~OD z#jbWjO`(o~AYk(IuYx$gospF}u!)hDO0>ETPrRMrei{%p+*FeW|F*MmE9A`vjV#ve zFJfl_^w~#5^5)41U!VQ_?u!g5`nBC*c6zf>-^xtHV{Cz@(u2^`StOV3c$3NWI(_r~2P=?gQi8&%Dti1jC5mATB$0M0x(M8_BgcaG%?{ zjXwwHLpKzOBWwHNqARcXxNl{aXY5e14*t-MbfZyZ0T)uj}2N{cYAG)edZ{po)Thht7&SUg4FF#nYXz!|Y z&t!XlbRLk}SiKit za;xH8(007Ly*XkCg4i``uT+Hy;ZO5_VX(lS=OO26ms!5P(kPVlj3f*g>So5TDa&bS z$Tu<)yXDwiOz!1P$&PLcP}+HW)qOJm#-3#(7wCHB;toyn?=N0un4a#Sv?C#=IjPMe zzoj;w9UDy$l<09rcMd(+CKM%km$7wnx_{cXYG-u5A<2KCscl~_dmZ2AWGN>!%cI4Swi-Hlg_Jis%)VEtAO zz(%JguW^iI5p;`<$HWaCzxGdj@T0F+?$V-SEZJ2ZtKwv)qcv_E0_Fr%}Klx?SctsYZJ?> zM8&ESez;dhm=yV?u<3yQ+f-JS6t6t0*YvRbaM4fDH8o3@Y+*Ac0nR_`^kc`fz8Gs@ zhi{tC*1P4I8Rx;Y5U;}Ns*e{}Xlr-8^VcyqPiRPr;}o^3a%=rf)W&ok3CuDQuB+o+ zT>grie97;LH5TAKWUH7_7$Iu1;pV)|siJJ6KcH*FBWR!i)>yHzfR|t1ZPC(eTNF$I zINv2q=uQ=cz4MM#QE?6NTIcMH6-5}zhBa0}{Y`a_L%&U%R zq z$-N#hdqB=8#|i|dxuIpm?+Rvdq}fxHt;acQM*5q%)0hw0)g**60jq{1@JGc)A`@x1 zY5Tm}dV{X^I_8J$5rY^TIcoTLG}Xs(`>VUZU@p%VB3Wk~w#$UZ=8JvjlgIyIwU#Fg z-L3s-I^NrGL`Y@b$bMv=O1}n#R*TJyx!Y^Srxlg(uu#o;N@EDv#0ue`R!sHy>8VLP zys{pl=eu!nDLNh~05#~tm+cf0w52P9$^EL=iHiI-Drav-BN2X({vMw-7_5#n-I}mj zo!JuPvO3t3K=2T!yD{-xYm%`Tlak1jG^}=UwSRRzd}kuTW8Zv#Lv`E*svTFn>{P-a zFmj@;N!!By{82G&K+_mJMAAj7-UNaO6NRYG@}bCwGJ%TIP~iw!`7|E)Exn-3kd@Ph%12 z^SnB0ym?h6LmthrYfe^{oQ!eS?99&2V9<}?RRH9L&(xn;hE--Zx`;8MXzrs6<`HvW z3~!mpIPjGf8}AIBaax3Vm>P_9r4$1jaunt;`*!bKfDXd4Ka-M_VbfW{xLi4{?re71 zxKLA@%vRv8VBsgqQ4#MC*A8$`f9Bu9g5k75AYzMWzM~Yd&hUE>w1bgXN095IMWO&vQ&N% zusPNF$LA1xqD-zV&*pSw$iTxu{1s8tXN#N4Nhp^E0I4q+`}U?F9nXQ$GgcXoy=-fe z>`<)K{a<2W7>t}Vkp^5fEdVfy1)xga3Z@szgcC;tx5p#KAlXt33FR-y#jTnm!F;bq zhyvDWiHZph4!V=N2||1G$TyL*cU@^!*FZO$);O;+b6S?I%II<3v6PGr=jUQxCUv)E z#qq)5)5X<&F=@w!3w<*wNc|_15x9M{=DEQepL6%=^FDjJS};`aQ`RaoXg)*QrekkP z;9w8eY)RBbZrphQ7^EEEmrCmdysI|cIXK%=F;0m7>xR9I1@P5W)&KlGvL$?Pk!RSs z#6vd)nSU9;`KhhPZ|IlRH20GGbK&9aw39jpfG7>&&atNH0&*TSnuYAtpgHYaxZWnr zFc{O=7@cG|6yQ~DZyq=A zzNl7_nbT1#t=*eao&4GJ%;?H{mX;ro`9frS?1;OK+mC_vDwNRF)-c_~iGuM+)@BO+ zx*Y!F)>&Oe{;m^f3|Ed{afBq3(`v)X4d@CgNjaR69SV$4xPK~f=;EoJF${Y+&7 zL*V)Z=C>v@bbh61x@^$!*;9^_#@zashLkj&*EOA!e4+QgKK9EoG$*lEdojd>~;b7qZ?!=q_bF6}0d0>*>J zQ~>AFP5}@ta-Tt-OJm`+#)mJJcLTPwuP*_JMB){7elTf>T5H3nB7krTB^tc=sXIXG z#S&T^8%;&+M^Cq9-L|V39QDC;%RtG0RbnFvZt;pAg3>&r!Jz~!t98n)mh>>ZQbDE6kBX|un)yK z(e`x1q0g(PPt*Y0jf26rS@Nam^Pa&{lkXm0&A2@BE~;H!F>tF}q{vaNqn_mDs^R01 zP2D|JB)$N2{am-)vHIX(%v4E7^E$p%w<6=v7Nv>IjF+uChPCgA{pC$+BHvmCj2y62 zUabu$H+tPAxZF(jG~`{H3O+YfG$v2J?MUjoP}okp-*rbO`W$hnsb0w8n_-f}7T*c$7czCKT%kDv9>@hJAciG>gl%4K+NNTfWHIBzG4ro3j; zj1%W9raBK#>ha+gz3oW_^YV92hp{87!_ln$_nu#Eb{$-BtCWy0jss4rCP6tOz6juT zGv*Md#sq-XE*y@01w4Xc_HODKoxtIQ+o=%TNdN-1_H!!FwDA~N)mcd+VNhC42&`Rf ze7$Gy*lkFnIXDz$%eQo(oSuabGD0M+53jG< zr|zYx0d5m0@3q#k*I&E>*guyIZIahN=fhJ` zLN2vNKvhD*U^RhNL=aSoCJJ!)?l^NFY?n=ez_+XNG%)eb(Lp=fVfL&;Q0*e(`NFw- z5;PL7*V$thrVhzsRRDFN&WFXZ8Svn<2My2($=$I7QyPDV;wo{6W#zekhSf_An6 z@GHQEYR|k0czsAJfQ$z40cp~|P%a361*byrh!Ob4XYm_wvU zx>0q{*A(DU0yM|b(}Tb^_;ApkvfOkQQgo;t0+mlN1Odi!h}fx zLY+fl#v*HtAAd9iF6WtCp9qgnCP?%B6`U5d!=9tiE~JQ|m{@0$G!5E=HPuIm1iblm zn$As3_6m%VCHli0L&ux)$L;D=;z(Yo!`EH6bP&!4!WF^X0<3;){IsI%&D5wxjg;dc z*(2ZXV86k00XCi%lCiASOtJ7jo1>d>wL?n!vc+^w6RM3Xu#wNZQT)-=BO6>`SyIBt z$$d35Kcu?o+0>9|5gB#01MM*xhd)W~uP5n%)qm&jR`}~u3;IEUrWp6*mR!CbO|p#yh6OTdl(n_a+Sco1~@a&D6Y4HLX6odMzGE2>ndAfnJ$t)AT*jfYLg}n+`LJIwD9@Goqb)cKPv&y|V++7sb&5$ql6$usT%Rfw z!8QVmP0SHRi%N(>9Ze0`7I(w97?soJJqfzzNecl{9b)c6Yq;~j>BZS;SkpI@d+F?I zYDvRwqi)2XEoiO)cDry;c_Pe_)jL{At13p#%%96&y-|=v$1u&ud_l>3t|RR62|m7qK}&t;)A%PIv$eCOJDAaSpZ>k_}H6Iab7VVn;agoXgXEGmg-|V z{Q6-4P*siov&AO|Bh$CIdhh})5Lejn`3{a^bLDKf<13#HF>*u$L~tGPyPQ5^hF5Gr zyqYLfa%HpX(CbQS?En)k>tV+w&U6J&*1cFBs?_<$KFMe6m{(%eShB(l&y&#s7T}i+ z0Fp@EzMAp^Hra#U)0te~G?O!5YGn`~Y=x!eOYmDtn)yZM6JO=hI&R3gz#t_QDm>P(MDt7&^Nz!>HMJ1JOm`eBaNlLqwlv{6lInQDJwT^v4?u zVs^aoVbjX0ya50Gaiz*}G;D3|$mvIoY7fM=>UU(_z<}K!MJ`Kkx>y?fkq|L7C%!f@ zKNQx%oErnS*o)tRHS$M6miS zV6VI`8cf37Uz9>?{6wGEE}a99Sf0VDyBixc5*B-KvQ~@}a1`waJ7}NsKP}J9HsJrZrr z$fB4U$TqDk%31jKA?~vLWbpLj<8%MZZAs}5#{hbSufzL4#ugYsxux_vx&QNcb<`I; zja{5+iwqkI^ybSWK=Acwwc`9>v!$zg<<>P5mKq}fEX4oPOEECAduPmgO@(c%*cOnu zV5nxw_NZ-&uZ4^dk$^Pzsc;>VAtftrlLL`0otmf51Xf>*0I?bX%sVt(tW?r&BKpC< z_I-DC=G9)_hdsiXCt3U(08z#zHa*v{7K{U|*LYk~e>m=zwkmpniMNrXYqN$tSD+5e zS5{9-<2#(WG-w`eh&k%Q0y4CrxR!vdtZ@Mr0$%j?H66e~K_4M@^8=am%h7ToKzLI& zsOS$j-6II%HE{F*CnkU)ljjMtKXf#Y-&( z8cOFE+xS6!qm2&#rq2K*?lw0V0LZ>$Al>NHIf^212fxW&~$$D~~px(q-jIza;6%rS?;#)AwnqrCY}7Ya3GxI(p!+!?uACOz9% zs7^4zR@N)?etTdvSSr@d;C2-$4~Y;_M*iPxL?VKq|WFlfF#7<_F4|U=(?})9XRu*AZE_aQj9GiR&g4K zoqHwAqQ-vH5(JQC-WM(=t>a5>)}{(<#+q;w!1Big0D&Ji8jzgvic95{PU}^nG_fF7 z2-{AUe42p^9J4tTy1Y$D#UXI+DKx0j+$9wV72r;rZ6G&i@zy#V30>lhRzSOI{`hLS zq~9~n>%DRq3I9s}Lt;$FPR3LzkRxRnmU4TP_vMeVruw?)b`}5*!~yWoZ*3869ZhNmkS zt*=gQz}aGK*bHt7LC}4O_T@EuU7B-8(;K+^{>_^iWo@rr744 zGJx3V32y5KfI z9be9+AulpQG&@Uh?9^%94ZwD=-)|^2m~I7+$-yDNKal&E6iGt|j^n#=O+b*We}Fjg$FjM~J`O+}=|9%& zXIezdV03dGA8m`)%gf-@f4ycmaC&QWIb&${o(NM4zprJXJ0h=Lg#l?yHF#3b%C(9<0a;{rf_v$m#t zpAk202EV8fnwJC5AE%)j2b?cuE$~5iFB_t!gdB6kc?)tsZ+~6dJtm}jWEF%FezE#+ zEso=I^4kJ^5!IK%(9b=yYq#*6pQ|csBgwj_nPu6F6j4n1Ula{5Nj_?iDi0 z5M_Zxw4T3Jv10o4@YXz#;fOvf6x|99o=R7!K;w6}xR=i5Vwmyt)x1GV*$6883)PDg z(XO(yJ$38Z*fghvQ6)Cl-W&%=7(B9fO9pesdfVgYgsJQ4+EsO%-JT!!PK0|4&G!s-j0 zRC^QlPdQ~A8r-?#xU^L5@vSh-5j0YnV86oAnuUN=Dz37i84ineU-1I+x z?SauG3Y02&(~O`ApKX}$)sH4CrtPfk7gwCb0?s-z=eKz+7grw|yljVUnBUY`wH`F- z)TC+{7yh{?-?745mZ{(T&aM`(pvB{>;qEcmWDUi>rmKK#Suk5>jMnHZ>I?j?-QmaNbU<_h@ z8-qbBpcYCcZryp-i`?^e`9h^>z4fgOz`35)9O7h>!%MB$zZ&j01&PYg!NS7dgjyP$ zk$!0Vp4F!Mk-N#l-lZGBwRwN`acu+rT2yV#NIo3RnKS43rrYkxe$07Dzcy7+6SJ$y zVAT<|@-`i(|FaJO&UdzTWJY@Mz8jhjy=wSx_cD7lT(NmsY@A&IsAkjOii@&pv?fC+ zi}0ZKb~t_xE5niM0%k6;K5peiumEA7HlEBfu3kkZQqC~Y ztpE&4l-l=SXiqZ+KzkyawA}s9R?7eOQ#DJF5};q(JV_)a7MLdH0W);@u~^0_q6LrW zU2anT?Y1E2%>@1y6%q&fle)2mf181mhP=`U5yUgcrnpjS!;N%H5^T=alQRfvRUIxp zjEwCCc$Ky+`nfue#ee%HunlEuGT~(>YfQE_S~aWy=x{OVhcwoYGuq1Fwa$FI1^|5+Vi}dPMq|v;87g6q)6ZcyK&j*_y&60@`hP@ zv;d0Ha11v?9ovf)g!CO2jhY~eIHm(B2ExShtYnt$>5n8^mMqva$+H#Q_5blarGQm{ z*Sr{bz0e9B_SC;j@)r%>eiM*yS%M~=ohHU1;vR-`e>{4XBYP$5IzLaOWRvdjVlU3Q zwWpNgl&pQ3~GBl_Tx}vkdhfsix${;7_p;U+OD_YsBy;Q7G*yV z95t?RZx_+>*n5qy?7)qXeAaIx6kQaH#Xz7q!JwH&#~5fU7|0$17}mVnMg{LBfUWm- zYdDF!-RvE15@+!J<+aP0)Ta`ven27Px!apEeBK`!C6nt zo+=du<52fKhw+xm%%J(;QwluODa_^44zb|cMFB4XA@B>$DypFn73M{9RIRW5-#^WG z*Kn@x*`A!fv5jtj_mKG+5aNyCZJF+8QdextsY&5$o6_Dr z0NGQKlpfle1(Y8gHUH4T7kj^x8KcF4CT$H+bE`*%Fr~25p07*8E&%LfktQx0+)o?g zlr7d4IaE9B*``sif74Yk-gKCg(*T^*eHCcee=#$lJo8J7+WwB8Us9NY1UvtH^1HU= zkHr8kZt6%q!Dj_cX9d^y!Qz)y64$MW0QW-vyQ&8$i2PIzq#_lVooD74Me*ZyDkIFz*xi&F=oZ8E}b!!1k+<0De924lw-yX$HR* zeExHY@N0z7|L=b=QkB_sn$&cFvhAO^j@0ZD{XcXQXEZ zzk=wSBeSt^k}{D3SERhW$c&1vHb$h3sxtcKMg|VZj0%qW4mY2Gtn^HbkQr6X3>{2K zSybNCG|$2t}DB4F83tV`csu zOZSUGV`gIF_@6RpP!+KK6vyMnbCo%9X>bt2$%exVsf8C&eQanNtbCb#16X7qDPH;` z4A(X_qR>%+?UqVYGE>e-eN`DqH>&DLoG?E>LvnSEBn-h4MP5XFPxfY&j=@z_wOPN* zj^)8;URP&}LBGy;^b2f5)d=X?sdvS?;mM}fe&mUm+CqnWWIy-rB3;e?`u^#+jS#t4 z!|^%X&-clx7wJGq-KNP)*a?hZ&*wx+5}igqtGu}IyxL!NTk0DX=zW?zs3D^+;bK@G1^yA)e z$LOoP?_a!Oeh3?oI;=)|u6$qrz2}2Pp9TMsim~)M%Mv+H?va#}Ve=1@qcbx)Es!$S zuVr+_LC>m;1?g+*d*mj#--i$RQ^w#8QoX=@ub#gbgR-z*#0dqo=u;N*$?E&mf_Hp8KCI!lC zoZRQH@N;7nz0?Ut@I|rlCIWNb%j2f%5^!hTvtj6ZuTbCHO>lKj^98~R1}+0#o#d_` zS9UW5NhY9=oMPoed_#?37HwRSAI7GF&vuVGtGe~e^$X96+)&&?(YpvNvbw3wR`-6~ zN^W;Z8MUhGSCR28oIUxv=a6x3YsyR2&nUf{xUdZdid{!LQ@xfvuR=h{u&3vM|{gTAy&ZgZ%l)2B@FFh;v1%^(f z#(s}#jby$%*7108dWnRX|RWf+8z4?@!?O&pKMlkKe`&ud2 z(WPM-%2rKiV1WPO&THDaKG z{8xuU^QS^=$G7cTI7^#d2zT7m77&h}Ls1Osl)R8o5ql@YXtQN67(#|VBWnjYNgfPw zlQQ}aH#Cy<&%4b5otBZRk|8GFlcr%NB$i)G(FHFM-=ri_{x|c%@t@{{gNx;-^&tJ< z6Y%Y^8jvI=ET7qP+6&W6J&#+KD#PW)AX+K)EYXOwfz4aF;DOtPg3*Vw+uz^QfRZ>s zw3|;)Fw$C2`+8-gp9e9>{22SHYskd^<&ns<72&`Kw%?Eznaxpa1!}w~9CpOHVBQ$) z-0C{gS8-$5C-z09uUdujw0ArD-0AqkmPWmsq-1v*g;C}E#5Lg*7-Wt{n!+fhkA z7Y)o#RKscxTpIeOFtDg<&0G8lG?mVp!x!ovQ_&{%<-WsufZm(9Zt`!uZ!!B#PGqJ= zV_wHV^6PU^^Y|ES?+~1RScXQ+N$L|3$sp}L{mRqTot{K5-;euhu2P$ALgP~nHbP>w zp(7p{T5zX1jv*+V$RU*ZrO}lWK_RL6;dLf@3T28JPkgBqgmBCMJqFIV#RgKgLDKDd zrhGn<^puK{mH@ts?xnSQX(Cq}PO3YU6&%lfznxef7+lB=uKKnKI(s^WK zE6k{_%3YlKL-Drc5ziv;!iEB>FL?w-sY@;SvFo?7&0%Lq(6jWcknu#$L38nYRN`r% zKtHc{Z&ody?kY9998`B?`x2x3pA;q@Mp-0XrET!GtU6i*(d>JGu&<_7I#g`*nX9t) zjOvDtInpA(8V9;lWmjy4Lm<+RxN9P;Xs_jyOzVgmtFSe!w{?cU`={_~Wq8m(mV8O# z8|+ArwJP*6#my_1t4I?~=!%RaVdta;$eGx@QcA6|p&CPdyvdD`kPT>5A z>xtp`1L+IISEH0%|3&rLSpHM>IXPMX=c=!)1(_nn^4u=b^^E_-rf{cY&Ma}PNFyh& zV1xtKU5?oK^ii;Yyf@u?6Uh?{?lt+WZ>_|)HRtsEY69FbeNgYt?U8+lm2Q=8ksL@O zm#AYA$bTi-H8pO}Q(q)isdmxVTF!Rf8O~vc?nrN7v2#8dV^euJe zeYxfvyuaqQpHi!_St&{M=R~(;y-Z>oi#Ol6J!U`L6_|iBUtWw{cQ)yo%UcCDQ>x70 zm+AC zD`i(C=h`yN7Cr%Wx$eVMWzXzhH%>Qypc3_cfCB65kjtj|77#~>Ogh4BA8eo`t(c(p zd~Gt}o)<4gk1W+fE3=vR!d)lMf?6kBpK{o)^imhylzM307;+6BFADui->stM?8)#> z0u(G(4<^mcKF7UJpyD3F_+&%%)69^$Pl_Y#*-3lGt-`2R z417U{2JBj55jn|awi`Ld0 z@u|~3J02zVj+r2LW1{R9ic!GchouzoLqw__{YZb0uaAuoN1GkU$uQm|d=ncEDv=2? z#;f?;EiOnA{0#m5SERsK&C3H!wEhT(be}?>C%*R)E>%zP{g6y9C*Ftg>gDqgF;L&D zd-uo%M_43SkW69pVV<12RBaQea}R=rcd;^-)3biiidI&m_q zC)w?DA7oKP`hJAav_BAIRcwovr9})fm!f)>Gj=x_4~4MT2GJwB*Gs}P8hrvQ9l|9> zhJ5ga1c~C=JoRBV4p!djlVZty(}ugg-+lzyMfDbi z*VDYYHLpg?Wt7*QgAY?1QmmUUYdi<}p-Cbzfpe*IbK8MIV(kdEm#fn~Gi;2k4rKj1 zu`d^xt*qqgz?*%r!=Oo%gVx~F*?{d;=)C!wH}GZ?zDG}xNqOgoFN3t^vlmwZgO9S1 z@Vd(~GA{cuGmh3^rWG@M2_$sy`m=QU>a0t(heVds_#Jrap!FK>w^)6C?&mq&+2f9=!Uy$*o?amz%DPo#j*j9A z+!)6T{Gj&;kqy$U6wcjtKeCpdp0_L1?tO8s)_zv@k}(ddKarxZy6&!r&aIVFgocxI znfu-3vew0!%lq@0py!j_$mf#icNF4JeICDDbZg{o2pRUL-e*6U{O(X}VAAk{=jAG+ z;?bw%7FmMG-ivEhl{=Enp}uR@rEYpHJFAZP9(xFBGiaFe`w_UomRa>bxU>(v7nb+Y zYtVyubanB*e9^;X`c#5_e?^XIn*NCWK3Y4C5>%yAc=~aahqvS##CX$+_-NbsXhZ?y zcaL=6S0gebGZ$Ql0vN)wF; z_XsRkLHUCuQtDcDP|)JhOJ+r;LXQ`x)9)TC7dTBb_Zm~iK7Ce;E-YX1ZfV!A*KuOX zrfYUqH|i}IipB9#KHn)Xse|4TQ{aR>c$;mr>rF@i zVjh2-=k&V8`rsRk@^jT(+txY0vkTYrQcK@w#ZICNwyYSP0gZS#c**%e)uCTx*Yol( z@9kGoU8Bs~?(+PnU1tMoa{j6Y`olAD|BowmdR3;Z0lV!vuF|u}AUjmg@a+TD5JjmE z|C9Fx=~TYyvN08OBkD@(_wuj#g|V3pi`4fX^Br8o`E$a`Xq!G!h*E>KHe>DWCU^m1`G#G(?E_@24IWHV27#5WI8^}bd(Ps!|m z8?E@FY6~mJVQR8y?VuY~Zn?npkTg!)-}^L!Vi@(GFwTbM`*AV)UkJAMf!&PMttxgF&(OFC)25{Bo)()@^q?Rc$K#rpd)X zfq7qhX?+53F%3Pj+EIEu#l?Y;#dfRguGTd>vRuP$LIPg}K2=*J7E`b$SI7tEqmU^N z$3>)?Iql7M`>6eOq0jgyteG0PH(DiZ0d;3byT>_#|ufDM(dCHN|ouHRwu7WamX!qTu*W{3!E zxI;x%At7YH4rGn#*ZK^&D_6B_Jtyf9Ch2bJI1VRm?704@sTgI&UOcCE%{-huFqY2i zP$CgUKA!=$|2p$6I5@P0>2%9pskwBk!9sVlZLxkdR+ z47QH#7K>=4Z5{pM*XNm#XPk%v^l+7OtCa_mZ1#sW9(;A^CzyA?p6}Gpb;=ScK8MK# zN)yR8?_S)>K;gv^);UfY`;D}9j36WZ503wFRU;9VpJ;$Tx$`cVz@;7yTk0G+XZ^{# zQp0cq4LmQ^wvkaAIjKk)cktmn`s8@N;3t2R_-`zmrn3T7e0giqR1-|1;S=S^Y!6xI zb-jM=l0H!qzO*;rBKvFy4T8HXcDoF&Z@%*Akc}I(D+taV+h2D>Yy%VIOS>=h?|$`; z`%!&*3xk7WAAuOsws~buI2G9|Ir|9JNFgl;=H#1k#i!OgpKtB;vMTwo3?LE&8S-A; zCd}Z0+?SP8^T^V(=|`2=UsXxu9U4BqG9l8AdP$ngk|kBeoxd})E)TX^Czpm9$b;5N zdUms*a_((IHkPcfm&fY*`o!R z`;yFXz=H5s35F+<32en;yS-Ad>`TYO)p3R*m|IjX0*k!0e7GnAeyZ-ky zf>~)hyNbKCxQn}rwWP4mArj#Cb#8oSR(x`AZ#giB*d8+aaaefHR*M4i7!P}6pz*2*Lh#+ji&eUYGdZ&SB z1owIu)UkPfk7>$^Ng?amS{p%uucNPJ`a=ng;-gsl&KR)XP|U^NIfMuWmxjmB)!^TM zE3FVw}0G*qp!8I`F_u)dnegj+MHS)A-I0=kf0db8i9WdZ@;Xj ztFL|%$6;tBq{FK!=O+UoXJd7D@VD@IAmVw>7%uhhgNKjYfwX0CflO`Lfl%BfhOehY zu5E1kt8@1KTI8qxY*EDbBtahjW>{JAcyaL5{nBu>HL|e$E_<+GK#IBW(1>H?H?R3s z_Y=SEGQ$u;^??C#gZST+rbhQJe6!K@4o&qA?XkbPbFJ|JO~u$`2k@(&2;OnHGng5v z5ds|@fjr%RDBs(G%}zlx{x`G$NW5;1z28WB8#7yky&o-D(+9m}KQaG{x)>?Aof6X* zS9W|LmV7SWqCh?IG=6W*v7EAJ_bB6IE3zsKgboo8*=P>9pHIx7kj}0U_21VJU~T(;P(fb5QS|%h8Gdl~GYoxf~UKw=O)UWjYpdwU=c!0DSj{lA*B@UB2b zcMS8p;h=q#4>%4Wn4*3p^gu;xc0+LbsK1a7%)pprz9gnVMMri+Ao|H4G3vn43%y7< z{)#6YAWjM2F@4%cz9fto@4HY_qWk|L#V<&QfDX!UF@5@pUZnJ>2|KWp!VjE)j`IJZ zi~pgK|DpH)koo`6#xJ2QBSy|H)Roy6f+6@P)+V=q+k73}ogNiVdI8fLr(>gI>(90| zBb(9OEvLSGk{==qjJg#Fewg3VUZQMvpBFS#BXH*L{>Vq%*R9Tb9LUuA6TuLCtgWRT zXzr#TXTx{m+Q!ex%oG^?)D;4h9P}3+@D|-(FSGsE0#7IA=2tDg3X)#PDsge$Q~-Dd?R%ialLwFAZp2V@X&L+1w2R zO#Rda0u=qpHvwXI=!&19eUmT7Fz`*}be-(C7DDZQ+@Fkoh+gG}AfxpFgrHqn;IdYy z2DW#XX3a052&^ss&)wpFrt9B3LsJNhi#sj2nSFg&fbeh2oAuOh!jIQ^KO_o?J6O%t zZ@Qp83ZAw04`m=0t;3hj5yKIP^UtOEXBgKeLjm6#HrxAltlsF(?t&kMi7ABEZv*+% zUZY=`(Qk--!M?l z(8*gopqckoma+Avo%7k5z_it81gM+tO#;wA@E1RjU}n#6pn+<`j~r(9r1JTTyRbh# zb2Q(cXJ0O1EZ_X^zmFhaFjaxsS2Y2ds-}CZw*=%5BYQqqwUb}~|BQaeyHP*Cgh%^**+_rogh~jF^=7RjK;-ugTS?+tD?>G=aCs4~Cy-WDuZ$8$so_ z5^yi&oxRrz*#Z;5LCE59{m~XIMT$CzCi6X`G}a>C8>gX%7O7x=p+EYsOeC=v7ZtwG z?h#N|oaRw~I{WNpjiidQn(2h_<_O>c@FsCEVAO#Pdl8WF5cPAcL%I~k+yTBpX3dge zb8iz2^xQzAcoTc`X`VWcu|z;c>UnHa^@+ovDaUSp6GiEs^A@$36Q7^v6}^Tq z;xi!4+9U>Epl-xmhwIrj??xzq3d2v2-e8o6JzzNOZ1%{Tl&3(k6#Navw{mG-tDr1h zAL{O<&)0k*=9tW;Feta@{u)3kkIRFlw66cueCJ9X^dxFPo>5|yuV0}zsO^Hb&#zpC z-w8~|d2zZ(Ej*}x1F`5sIO-x)zIT->u!8A82s-f`fo1y%A&dKXg4BQ!dRo)8l$isb>42ZCAo5knwi7O3@##AM~f_nX7`{K{y|MuZ|W@I~+ zRSR)!88O{h;m2sl+}Sv0b)Pq6a%p!-E#7}Ej8J|cRI!Xy{<~pKJs^#aRO7YCAS$*v zzin?0@M;y#3o~AvkkqWI)(W1#HQtBym4bA2qkPXdu+2C2o)Hox5!GGuzp$IA6x4UY zl0cwe)S+)~$PvVia8qU**~L?D52C#YEVG)NP1@b6FQ4E7b4y`o=G|)djZJm% zq&eDA-j&#i#>>H3pn8cIw#bNl9czl~vS+#NFnzge^)yZ-Ba^4&hb;bbDomCQ1=b0W z+D#PxLx`v_MLy@8{XppmOg9XGAQ`fGfA1^pfERl9rFMm-*jTdX7%TWd3B71i*^!E8 zbiP4SV1J>B^5-5UUj+R#K{LGzWrU@IacY z>>r4_LjFF{ZP|NI zYa`v41D`!4a&+)$JlpgF!B&QXEXz&pb#ndBnAOU#w&KPhW;#;#gL4AkhKm>@5}l&# zzb+)#y56GER9!YS$o@vNSB6OzdHdnyDHn#z#i&=-9beCW_#`SU4v#^fb#x7FCPEPF zNd7+9uOC9m<-qfwA%(n@RFjU2MPff|t%2mbAgB{`Na8NpDy@41hM#89t}B3G6JyaW zWxt-vXLj2fcW(gtK?`djjCke(&ly;%^ICaDC;+6>o}m>U1ynktgw`sB^=;}^swS5m zc8*qf5PdGi;i-V5%8X#jX}sbc7v=$Z5|^r^d^Od-fJf` zgGMf)LJ&c^uNPX<_GV#Mxf1pKWm(?y?=zcGS(pl@F>fW0B(9f|fegXOU@iwc|A1`= z&^-K}Y#^qaUr9kP;woCCB#ApwAdi)1RG}J|+i}R}pC3AxlC#fAXovf5_gNJh*c!Jt z9_N;$$GCMcV@dAI4vVNjK@3%EJyP=fOj}vyHsW8yHipT6QUwdT%U7p$mU9?8AjH@P zI1E&=NehRGkffDo4d>~9{|ol|En>duF#w_?zxgU zX=cOKD(sD4`8?!(S>Bzqn9D#u@lr14JxcevkNBQ@jqmlSqO%&SK8`TPZ5(%~?q^XI zk40~rhk04r+4!Uog@y;DwHHM_gFsy_Yn3CKY8C*~pxTx#fPZdgNgDI~WJ>&`>P(;hM= z|2c8#qVxj`X9v{z8T()3T!fWO$hdo=Jeg3*DeEA=wX85bDO&YFaM8m)QPI^TE?Tj~ z*L_)!b|myNL(N1XEDdTKuI*BO-Y&q&ge{e2RYJiuk@J$9Q8n>xy5;?T_=z4#V_*79 zAjQ-i@2uVbS71VGn~`o>9JKB5D4I#b?y#v+l{4}Rwze0cts)GwGPn2 z_3mTK5(U#jg7m=yDfAOTX*ykU-;W=fM~hxI2>mBX3709-6aN?*jBmmg=gBI5ZpoA) zeP|mRU_SxnDSBMGTBfEvO+NQ|X- zTDJI5e$>!Ltfktx7Yh<(oIiXDdah|A`tPDAVy)3*c2etL@Q)#Vx?A~p#93`DbmY6) zp!Q|&xtL-3=%I?P*J=+-_oNi=-qqF&0}Xb-AK6*;7|EpDC$ga$Tfe#xom@F8zdA`+ zhG1&l=ezfK>FALKI#y>t)C3KnM=aO)xNhpH3lM0mB)4NnH9;&>QC>!oM}Lfyr^ieh z8EY@of90!O^r`o`0Pz54uGfDQ))JX?g@AVHJp)~*{d*ExZ7Ryv$^wYf6r;s=mA}sk zul^%0^{(vBuNFwZQ%aem8L3(!+U55B zbia6eWFAsbN0kej38@s~9R8#p5(@FSxWwaMXQcdTPGp{jZh zROh)crdN~<+sYu9t|ByQsL9~%7eOlK$@@_c32S+c5Ry9nmqXF#NOgJ&6jfb6)tZCz zX$*d0lX-f(v#N0g-ED^@_@mov-YX2?8Gki#qF35>i(qpP28a4IzAMVeje6)XNM{`> zvvWn^_s}=PIAzS35D*hWu6zzJ+@L_;b*(Kfmfv*!_e;+KpLd2VC`eLs_xzDtyFRPa zY*t%@!TQ=RSl_$CY~GgaLaX@2MZV{l&+8x-+MqsZJni%*b8mUp^hf!q04{+Ai`!Lb zqQPnXa5!us&4=7mcZ3<>FcZpw=*tQBRP0=YS-l4B5L}Ir{lNOESfJQ0XLzC6L9qa~ z+pseGF^NTJq>WRp-tHr)x=Xtw$2L1YJcn&-KX~mjJ=(Yq0By$?*>JpNaZD>@Y7x&j zdv_b;x@8ysi8qmjA>Nko`DC9Xa21zVFI>J|UWjMdS_D73D%Q>*x%3tDHa{Y%nt2)3 zAqI4OFJQsGB20NTdyF))1#wT<0ZK>~i!&TM9GgPN+qHYzhbR6*Ka&|@jlR9GmD%7m zyUiB;BX-49@n#NRX!9_`k;dX-p<$0EI&D`lX~?xpt*YVFaAyNq%z|E^JRS};YT`b; zyXn~*-iu&ObTR){%s+fYO$#Y9>)?ba#Mh0_+pCm_@q@nANaKE-b7}c;eSa2XZ8aXP z{v1(c75_r>GYoumIn70!NIC0Y!mTLbQfp_w-5JhG;t<2V!kkzpd;rN(Ie|Ty$?@+O zQp=rEz{n(Emhr?Lk-|xV3!$Y*oyJCIShlT>oj`X-hP~%Y436574Y#ZbBf60Cl_bTn z@ewz8xKJEJhP&Wp_Gd>_6oY@*K$d&CIVJG$w4L^j+Ff6i`%1_~cTN7pNeER`Jnj(;%$;AQt+3ZIxFd04tw66HTki>!H$v>maN>I$5_E& zJ@{iNsxg3@NaaY#AurA2yrq`c%qdz#B0_4$xJO#%MP8*tsykE7!}UR_;h3aQG2c5| z%}~sZU^IK4x-m?1fo>+06E`I+1hBVDUi#vBy+0^acNjwOuC$os_a3nkC?H$&PdM+} z7BUc~&F$T)YqEmFPCYwM}H}{y{~^yv*Bpg7Mn&?@p;3VEIBPjWmh{ zNp_k+r$;FyZcSe{A{a77VjezKSl-=@t0Z@Y{!U+mVe%En8a};q%?T;e7klGT4usimt5{ujx*{&kuY2FP?4NUjuZrIlL+m`Zk(8%JFwZuF zptgM4ipe2%3_=?2XT!mNJ)hEAEL8E9^X?h|R|MZl9V*qP81T*slu(?|M~;ci z_2p7_xYBvXfNk5^BQ~7T*LmP5r|3H&GR0XH-{uwRg^LVg39gRn%M~y~)>qdsIB^Ga zl`pQeZy|cHTa}smM(da%K$bCPX+QbNDc)`=zr(x^n1qs|lG~{&iLE@U)}F~@i&IQw zJC5zCnF~q((9e>iBm$35ftuXYSEpZ!3i(J)Wqln1T08Sn%DYTNq3B$cQ^;!gR5N7* zezH-G5bj~wAJ{#hc))pH8i$?srd49Wl33%p(PeLgFF-@bHJ4hOzz_Z+cd35)bLQXEX#3Yr+hSGPan`efC8$5Ple_Y0mW3TO+F8<{TheOW z^A4@7uzz+1kv@U<6}u3@n*e&PHUtHG5Ck-JI* z*!_NFC@VeiezX;t^?|LSE{q)P$Wrco3g&?G?+VyXeurPB(TrFYSUQ+8wEnn5;QUjI zlG-vZ50dxe;t=*5q?3W`4>sJ!>A!oh5gpV<>Dt`q{^g_bRC+g4{z^CaEOvq{A0=eC59(gPIAUn$6u0TvWq zE423!qvU^{#^UZ5B~RVte_+lv-EH{SUo5UC19aV-6zaI)+b~HPu<5yiyHsw^&|d-g zbQ2R3QDR8Jl&oca*USJ%)qI|6`2v-zA267(E0lm8`|=lw8Y@PIZ=sRK3>C`W#;h&I z)fkDNmAgbXynnYV_}XX-ZbL2In>Ii`SBt?X=5?dUlNV&4wLGab2DWHUxqyu;;_!Hf zt-VL@d6!+|3b=t;(0Px4`zPTrcsx-H>{*-qNarS>S@ieY=ee7r1~8@A>p5j21E|l% zcDRx0i!$Cl`JgqmC^ISa|9+2On&b)psUMs@D_ABj@VvD}J)h7+R>xW`{tT2ATT~aK zawVX&#;$5ei?@LP(}6)pHRO#XZw9L?iD{9)97BNN!sN-PSNh7I+3JmzJYqU|x_Jd4 z2^eVAFo~1A6hJCOjx3vd?lGtYSF<#YP_y`T@eJt_&;NVc#@VW2%}l{RO})3aVe1-* zYy~_{T7?L1K)256`N}u9v?^Hh6E1W9%9y{XO7$x=K?3I#J%#QO^0TOke~QLtW0Gp7 z6|pTC*7lDxB3)EIKUS0v7D2N$^M>CTjk|&6DhU=RiH%x3ert{<=!WjOX?IO!P&)lZ zAD<8@HKgS&?xK{Xp!|iuD0yqV1i=Rc@ya;6AE95l(7(_wqCFTJs#Df9Pzt?tCE?e( z>P=R~Za`dgFz4l=A`-K~Wnqo~m7c!!mJ#wd72(~jdV3d7@HKn_uKix^an)iD%!b&p z)Peqo!Lr2(krje3_+4Q5b7zn?kknL89Wqv+6%75x!rvjub0tzkx}chnLZ9&}hPd>I zkR+Vb_SzE5T;t_+!RD29iKv_z(JV?rGnS6Pu#*E%DfLccQB!cWg!eC9J;$B>$~)t7 z#b_I6?cd3Pw1K@hxL8PHDy#zB#}}FjrjF~P3Ppvl>kYCVxWUW3Sy(&oI>*2432Hw; z)vLuHl_nRn`_Pj`pT03wvlL=r8?LA671smo%!CB;Tex1^TrpvsS!$u_H8I=&PLg#k z|ItCLO=B;S3SQ_I;^i!{SAW+plv_9MNfj>Kg!#VyEeH+z7-Wgei=l|*#mR26l@?u= z7p++hg=HoTM)!_iy__`cc$#%7;`O&)jt-Zp5XPd|73wy;uv zCEp!ec)*@$#76Izh*G7mZtw8Q#4QlZ>00} z-c7oF_dX6AeJsK^T7Stxa&k_{x>-`U<48O%+k7UT7%hVn4YxCUm&v)@H6sMFFCX!z z2OggVgW`r#+^{v`H}h$mJjWQKJo~_Cn(w|){QTDJ4#h=N%*ZMEUZJX!7)A!@)>yxy zH1E`v7H#AwI*szYSOqadllL9tD^q5O4C^{1I3gy9QmCvsC?537nlh!m@7Qz{}8 zk}nj4MuN7LUK( zLuj-1D-;_yqX$O0Kzj8eK8!ftEO*kN&o)vL(_qBOSbVvZat&KHimN3n7ime3`- z;eCWv@X+I$2ot)wUf#tp!`*)e1{M1#<#Vh8&^)@tgJG<`O?uulO3u*FLD6bLg%|+} z*pk+Z!k~&*^nX;541@%vF}nI6!m0jllQ0ZfF$)#^J4sV1l_JjCLw&(Wp7I1o#gt0P zMZZbI{r-j(qjfCA3TEMzDXV)A*j=5)R<2EU0vnEm(U+`c-jL*pp7pqV|9qZ`WKCk4 z8|^SxYXC;I2-a8(jj|Gw`l4(onIeMd{vIEFl%h_1OY8^36`HSLiX~51hyrC%i4$ux z^p~Bw@_EB_{K-9q@rysalU1H2hF{ht=Yad)ILmY{)7VW{) z4XZ$7GaBBGz=k@(9zyaLs9a&rSNg@Qzs>0$9qt@(oW;(HZS{cAxcmv6?6)gIlcSqk z&_2(~Ee{M%sOSu@PTv1>@)(kD0)TYH6BD`@Tmr=42L z=K#ZZ24iaqouuT;dNB8#xvR1{bf$|XM=*5Fo-aj|zDY>(u~)vGX@*Gv3+oJNe8*_% zkmq%NdBrqXw|DRUxK0btznvDi&pSK&tPbuvSr=%X#jZSnVKXVb1;h)kuPKKYiVj!p zc7^odG$RJeMaR$-qqtgJ)IRzvm5+qIOMN*AdI!{fMyks77`{ZBSh-eAaoQso%t31y zOJBw2p1ELae+L*>Jlc0(0+uev(x-k>FgKy z$aKqw#VD2oQGC_j2%a5XKs$OuT^`R63%=fNVa$jVq3E$pKL!sYN}naU>|I%OAsntg0_raC#NoE5{yv-8|gv+p?X;y_=1 z1b%d#o@ifl{8xS)Y&R z$Uf^gl0K~vC6W)%VR5c>OyUiHG|;|r)2l@*NH+#rDZDj!d~s!h*4OFMso?tI?Q+On zBkfhy>)&Cb3$a;my}Jc8D%(t9TNGGMkibmocunP_##LO4fC55(~~ z9ho(Qf&TWobw!*A6z!$1!qgbiYygp|J>0zBmISPV+}e6s-P#!1AvBI`u|?Xd{+Q`0 zdUL~^r076q);^~CRF0?St;o|tZ3yu;@Qm_(cAK$NOBLB>&TNb)k|H^aZR9`+5)r3D z(q<^LCh7guuI!Z;T#|`T6xrJ(vf)j~HmfKrUuuYa1M6*1YQQWO4d02~k^4s8UBQIY z!qa>5mvZ(KiD+G-SAEuS?_|pfhP=!^0IBZku-u}XNmRYHnmf>#WiUileiGa46G}%8 zniO2=eG4*a_7LqcZ#H{Cb^AlSa^^63Y6(Dl5hlwgu2I*40#4cN;e=eC(bi2WWRk`B zGgc6VjI_Dl%o}TzW$p5$I_V=yTWsFXKpgFw$uh*$g0Z4G&nIK1Q6H|--l;zy_ys+~ z&X-*y$EjN>@mFHhvquM3ib6ub;&c6QErpt`L$;;k-pk?bq;1Za468&= zcDO!Tq(k-aO6sy}@7$B(Uz|(gV?IC;k6*iT!^Jr;Rxo-^(hblB#cI6!yCHT*T?UTd zDjd>=hz~f&OCDfBANZ9DGl-f|4r8|_2sRU?FEX{!@?@u$ty6UKtC{rF#WQeJ;1=U6 zC*v6m8)Lt2b#kp-A~{wLTLpCGm25n++hkks*;LRL`fXZwZF-qCo*?1D1)sa6TW*aO z>OBPevjWQ1FlDUqOJONJV;D=Y8>Zgx7Qr^_?GZle665St2HSV$;H!`bmnnpq5)1jN zMzqF!qvwqU!~Q&;DPO9xWAMv+WDm7cI{p#X&gg5uPF3_Xt%7#m0@6_*Kl%g zTBWHlFn`T9Xznl5Bti8v=p1ZDoNgb^u&E^*+?W%npnR9eTEwBG9LQaYQVvu#WuxMg zUJeaskdxHipbCGX&y39PYN=ycCFkkGtUN-@gtaIY%9u8cAxcy4A7Zo<7P&~OojbCY zq}qX1x(eo!u5O+kQMEL|aB?r~E$wNxvl08Fyi=9NVK2Tm{%y`sL4!A`F1=D#LQFze zR}|w)pm5dx?cmVP@A77um*~C!>5&53JU;VqQ}XX}p^tV?p%_g0*YgP-7d9X2~vPU>e=B;JA?asIFV z@6TO+XW=e=prX7W#gQTFRlkA#UbP#Y;N2l4Z04h5*j@bD1??Hb=_dYlC_0uc+TpnMm9`h3#DE1PKa z$)h15^UHnOxJHfI0rS=nrFP4tTEksW?x7a`zwJDUshp8irC<$qRv~m{>-h^DK0cW_ z!&nYPZ7kuUYScM}$ zrv*jSE+3cPrBzOIFO{A^1Xc5;peq@!pM%9>a~qCo=;g_Of6y1(mvm@~sTK1eA+v8e zEyL}Cl5g^k%ZiH8Q5*|-o_vu)pI>Ep#0ho@}zGX@#9o_bim;aQ< z4xKWYe0N2fpxnC6HnJH%N@Sd}0np>Qgrs@2g5$t7BE2TPXGO?ZTU1d-{r88A*Oi~L z{vq+49jjc&#cG@v7hMj2h=SVkwfy0b0T1xvte=U7D-M*!AaS94$;0TkmrsVmM8tV6+- z61xOm)HU6AKWBi%3%kGF1_}2ltNPQjd+%Z+;1*JpI)dD@45#NaVL>(@(+6_kyX?Js zOr#-DHC(0O>+~+&ke;3TjnbX9ThotuJk?~pX+$I>z0pk$fz9(D1G#B(JU2#y+HG-s z0DLUTo-ZXPKuX^cGW$GDrVyv?CZdGkvz^z|h3P4T8zr}SIh(3zHak>?W7+m1 zEA4By-LFs*A+q=a{CY*_-RU|kGFH&tjY%dHu6SH)C*_`#=VKYcsUA#mLOGRhTpV=B zXk65JUIJuNT8BucO%dg_n4)$)x2up^oNM8#*%Pz-%Qx)?jZuys**IV|Kc=S8dErG6`Q+Y0X&K?Fu ze2!>5XwZY!Em3vW*Myeo@cQLhY3YiO#AO%e%YhDZIbehy2MZNEYLwD_`Zlx0Zj}HL z`&CI8Cf>HEe*%KhU}W8O3KP(ns`repZR&#t12ai73hQPn8GoUd60-@ zcRgnET(DA3`<%!ZD5N>d&=Uvx>589cWtFyEkqVchP4~n3a@s>g)+}Rq4*5%#lqiz^ zELr-4FV~B%xhyi0>0;l-_tFX7m7sOd9?4DRR3I|k3#O~C$N70Y!m^N%pH&sr`O>M` z5V47X7UxF}^s8F3#_rZ0SeBxdl|ZNLL}dv$y`{7+35H?MbOLCPu0~v)7sI77HTQph z_AUo=fVOo%e)`#$$p(4i=4Q1n34ewdW?#NFa2n?h`}`x94xRUkTFceX@1~V^PQxl9 zpdd|PO?ucqY%p%SU2|r-1X>rqVGCyUY+|wR^fBgo8S)#a&!W=lw^|JwiKr7$?Sqsp z=B9!;yuk~2whd<(8O@EGN2l}EqJ;iwy#5g2Sj^ZY{9E_GbsvUbDBy9Of6;Sx>=2Fs zgj1Y&mpr0IbOSVBlpM?xR0BoydYFD~%$!7Zv^(r96C&a*2upBvb@%Y)M4-BUWa}qE zmRS%Bazrd1GE$e>*NbXsC>VFP%c@usmsRX^Bf&&?m_keJFs=+#)i_BCH-l zd#?n#Bsw7UKy*hKF5#&KBnGcLQfhXRbb@BmkR5eB&dH?e4I48$&3?J(C_O@uOtZuS zv1$K8Jhax~i|E8WG0MSTXsLAsh0!RLW};0_7A4*3}`Dy@+- zz5}D&m{{(TSX=Q-Uaj^c9u(9J$8)CD)MAxNBYGP@zT@x$UEfU-+jg?1DS!H0e#H5B zjOAt7j?pif!919FOuQZ|g;NVWt&IgwBAr=MUn}}ybOZY_W#0TI zO{uza4q4hxnP(3b*KS8A>^St!^|^AJklw&d5+Sv0hf+DH8%YBU4{{?fnG_ja%tuv+ zZ0yP~@vliS>->CQRkU62%(Md=6GNCO0j}uT)t7yk#cC#ceZ9q}E zS6EN|6*}IGgIr}sLo$`&Xx`>3SdlEp4)ydue9V)9sHy^m8KMR}sHv*Ark292DhYyX z41Il`(62NE^5sFFfra2M4dYJ+vV_RTE{=CY`RChRl|nsgV4L1_&x>+Sy}1Y9-(*#E zWXJ6A^?a#do8AwNJh8%RkB%>g`3rLmT{^3Z072#sjT`Z7@jyA3N!M`Gwaqy&hspCx z(TX79xZ+`<9)$c8kczjbo93kvgM7asbqkT{4@1T9`FtWBF&V+Ot8N9e-$p(!h&Jlw z3K%TShJ>i9JDHDSORZA>wVNSBSpWDt3VtFnx^r84m8znhRud4D-PsifZ<9%m zgy!POo%GmwNV;4HiXNKTA5xTcWxDy&&RM@7<3l)*^Z^=KM;1lv%;DlB60xmfxq}yV zjB`p6s>)T;OowIpj#1%unYX+9bfLCX_4tv3Bst&(0(nLNZ!w;O%#J+`PDxLaRawR^ zu7ZzW$I6oeF8fmkxh2a#v-lKPz2c_t#4%VdJvKhFelMJvEqG5g*6b@9GmH^R$?0bq zUb$ClE$*Ch!)Pw%CQ?Z{-}W8x5?3h8_-vBjw|=i1!XZLm!~4_b6cKH2iX7@PNYEKw zj?fIESR6|ENDL%z*|PtX{?T@=Bedkgu6x1gMjg-}blV<1sQ0O-L@F@KIm|}SsMKD0+Xi;Sc{(t=IsA8KLQ>O6;QM{@)?6r_ z+von_BX(X>I!&DdY+VF0G&YkLUzUY&_XA!>h7-#*|8S4#2{f%?l34_IJgi}H?@iDE z4Bg^b%~1Ua8yz7MTaYLINziTS4P&Bj#Kk3p`OXta^4*a)3N6!w$R(Oq8?+EDPp%+4 zoT(oIIc(*!Tu>2rinsaRIASQPLW7KprfvhPNhDhUZ*&G)Fj@8}$8pj0FbvG-wk>VE zdBpbdUP=g#!2ZpM{{x`r$U&a}W^Q zq4ehCV@Y`*pOA(q2`SH9Gt`R5lsE>`TF16%f&G1!3%pM}ODWeP$RJ2a3O13e6}_{dr^c zVoDGh>Bwz@T6Cwa%BNqz^r}KQw_)!;qm^B4h3;AWcZ!}HrFkTAjBpc#*z*=lo@xtN z+Ji$Jd>>FLWL{l-6#9J2yj6}tO_-a~J!iRiQ2w!A9Q)N?(6@V5+x&?!R5!*&C++Pe>~bue1i!eBEU%2!)-7Gg)lc?9zKH|wyuOCa}nPJjp8ojo*=8Ksq?dnFaFqn1!~^~LR`yDxey zf=@8n#@qMs{WZwoOQMBlTOcD_%*!cvEFrVm7*vPfMQCL%X}597)M?=qHF>RMVw&A{ zl1kyqp~GIrIv>vRmNmODP7XaC&8!JjTK{_#^ZMdM7#FAypX40vGhH=ywRR9N+cwoO#KD?9V}$-V@s5X8-^NKoZeR#+Q+Z8bkj@Mo2wzw?t0hJF!%Y;c@w%`^y_r;+-T&ZfuB2sD%FTKmR0Sn*?2TW zn!5#32|54Rj<8>ANs&9;|QG&)=DNzkMV|4|BWtlOoBzWG>e0RkRrw58Wp9g-B<{T5 z?e5-aLjTBi!Yt9lK(8{bu% zDo$H+|6I}VwHl^)JaOc#e51f40NWccm^9mUl`lC>aSEdOp#Tr&F%5tW)*8p88i~CX zN~)G#!BFd5{&{qBs?3a`u}r=pXvR7sQ@gMMzcD?IJ&j8tH4SctzIT06)cbDV_Yv#Y zrI&Z#szH6MRZfOuFh2ybFj2g5jhh1C+w$8)pJq~hJjhNr#-I9lrlj|_UWW-KT0e|I z2?yUY3D?ArlV-O%VfFLQu*)%DvB-+q;Mvq}j2=@M;4JgLq+w~^o`I?`5NXsOX&PM7 z>xv#p$iOTn8vM1996Mih*C5o1%pM|m&Q3nho7vS!S$Q*3%=bqY!9A{qf#}if^*QP5 zXju&El?5N~?w>dzLo~<2M2Q+()DEyvB!)Rs_#Efn6cFcIlq#5(6Z>LAjd`e*WPRP~gUkA&*n4|mMZvO(erZXc4J&^=Rubr3eOF}u z2svJ4uc~VPG@&f*e4QV{qkyP zyk>L*wv?IWh3h!F%oeQq$4)Snqu=LR!`zI%VAW@p?g^3V5DkpbH^l3ia22G#g6#Oe zf7j;9jFl0qY|vJo*xjS(O-D88`R{`m1~16U)aI6_xFh9;0lg9NTu-F8l88JRNMR3E zXF{fnIDheylft0cEC^nB=I9|Te?KF?O){A5Xqc9yl_=Mm)a6vRbdwJD9iurCS3SC} z8e#>wHl`isUe2ah!d97MGgMa^IWk=tXH?`e|G~$$&UM|k@KF?~hD)m_@knXJaP4F& z3LeL7oe18TM28G;?npq6?c^~}Ef~eLX_bJyV2Nu&t)ziBO5dSnW)4c^7PqPXW!EP9 zG;Of{Cv3dJI3TK*gE-{Kb$XN>_A7;N*)+Wz*UXe+;pWWB}K7{^KcHjEqgMNRKSG;RK+`+Vf z925jr=^GM*)ggHsMg>tZqHP9o# zVCJ}l-^vh~lW>QX_Zty*Bdm5nLMG(aIrj}f`PWp=8km7!UifU#0qwj^74=EN}5ob#P;BwQIME=?9c(l6i_Jd8xc4Dm>eC=k= zh2R?=!0%#kH6`jpq{kiK$EtOX@B7)WsF*~$__%0zsump4MjVu;>0D4-CRY!8!+EM( zQs?lu!Y2v=HNLIo`N;>%jg3^-&o$XCkH?X5HY;IIJ}JaK&{=Azmry`Tb+pzy0^S-2 zzDssYTG3e184v23N`9A+5v*@G3B@Uc%4AmEP+9hiwrgjAH&w}|dvnO*dPli|{dTVs zPyXCVx=AwMT@ALZU=G$_FjSXKky+EV5=!mEG|!R_=>lR>0*U@~*@%=}&5r25COl__ zA)u>Fk@&D{O_;N0=L^PwLz}2#wNpQ8_BTozC=)M=h-daePMIU&4W-Md?o5G>x;#wr z%TGKE@%{?t>@aOF!wZODxs!sCf&e9+Fc(x9vz=r%Y(OZQxV4fDc-cVzJXiNdzHe$4NgZALx0i3Y$+d(jHdO z2X)PejVoycmzNn42@2*|>;}{Z&*8r_{SMJ~V*OF=Zz#2Ra^427~zJ7S;VbP?`_G{=yETq)wXS|Rbu0J?P{Ng%1^{B<8e_C z3uj8)9e&?^P?RdLv%`oeAR?gPKsQBU+0=%@RRS5b)pgjYjE7E$=tYtJ6tjIr5j0<2 z)#?hvA8Y#M_be{O-$^Xkz7M}6d%BW|ozc?0$jHg>R)!Fglz3K5+BV+_UfDc>1(w6t zj*3dTzK@1-`97T9Ra@*J^(z-4QAW#wq0q9Msi=XyMAY=b7-yhU8sidiAd?4RB)D46 z=M(g>1Ucx~XDt~ww);H4AtXrt+)nbq+&A7yygoXykcZMKXzoMP&cP|HX6SOc>}y7_ z+o9gSdkacJCwMN;9H!3jlM@k9-Z09s3RQo9C1q{37V)LdK9LSL3 zrymKu*V1gWx1gpdrPCkl+ZVMX(g_}y9JMOK7I5I#@F1cFa;c>6ABtbVR-_|Nkk0e| zFUIaEMz=2N5^&kJZPzK=wr$(CZQFIqJZ0OqZQJ$smvsJ4I_ZnP*~z-zH!E|EIi6}b z<^mX?bm^L83C}}Ys|K_MV-1mN*yh1V%$DRybgwKzPMLt{waU@vq-jTGCk8~y)!_?Y zrJxz3uiqcF@R1KlGwd6XYwVgvNqxUYSkOO7>v zM-zmYLZOWxp=367inX~@TW55VD#pK_NA$Gh6B{JS6V23W4RxXvE*oB5(UMM~SwbTT z!X#={Y)rQHlycbxkHu7etc$D;0e{E;4!$_$TAp>EpQ;iWtc8q99;@Vd2}2?hl8ojt zm_%gea9iK-m_ucOC0mp&63tP%pL>)U*s`48Ohcgk`PgD*D62=xB1P=l&7KwVp~*UN z0O99l4XLwlo}4JRM@#Z9QPvijpK`FE4L%Z- z8__$^7`Z%ezGKs~x?1u%RS-e2vs{Yg4o|JGe|n9{J$qe9X9M;@-insJ`dAe&Hot!k zkx&sR0wvJmIF2|f*Yb-FrN>(CuUNciRsSYL5FsvH+dn2 zEqxL?Vx7|4K{E-yFY%2owgcmb<4~uIbjv8D4FQc_Sh84P!3*x&GB^BJ+>Qps z6lInm?u`ejQv}Eq3AQUnuELw9Nafoa-7~x=^1^)o%6m=0iNH)7Zv5foVr^{l);54d z35w$3Jx)CMS5h7+%JXSE(rGb2&Z_; zcCa?J$0fN^^1V+syvY7)AbrH^H1EkJM`XvQCgkzdh$n0?1h&}Z&qS^Q&_-n&?R@@= zM_(KTJC-A)?x!27V+I;;(9Tb!PgsydX_l>pm7cO3P9C1xNnnVF*2N&EsJKgQsn2j~P5tfO?5-X{RcJ zO=kHaY-&0lkop}XHg+}=PpA=dOd)2%57zGy=}v0g79P__3&uqQ`hdR4K(`!}J`y?o zsDOH5Io}GY3=Ylsviv3HU$FemTF_)SBq)Z~>E!w_d zAsgi8-3K-ja*0-AaNB?I$^+b1C?$lk_-@o54uu)7uKmC`P(7W$tM>f=f(o$KB4PM@ z|0^D)CEfp{Rm-Bq^WzegG>qF}c@Et`stSM%n=^>q81O{rhx>J>;e3S1cpA<6QS-2zhugF!Kzpe3?QnZTX0ht zmxYPp$-asyjfV2Mqz9GK_G_c!_|4D%pR9l8IkbWJP<*dbGm&ec_yvN(C_Lz+$^ z+8?3nt8f{h%?3=qAQJ&ixI&!rFK0 z!!e&nu|TDkM;$2Dz>Utg%e>WA&}qNXxQ22)v?=Ak6~niR+2cFVjL|sN5dr)V{lP+A z3@=Lyp-BziD_H6TJ`mfkIo!yFhMrW$f(my!x%q@shFFm9@;=e)39n_H`#v{ zKj+u)yk+eM$qz4LB;Y06#WKHMru~@fXc3?s@2X`SAyVAbC0e2@W1^XG?()f+6@_5z zBJ|YkuN=3hujp8WguwWH51mm5hqRPpRa;7!59{huR>~sVQ?q$xj7Ltlx?@cS+*;9& zx$HDeN1F{UbhUBk^oDENJWilnpIzXD6R_}C{SEoC&*suZZZ&c9x3HP6w{p;plAmxO~ zA05J?^&I9{-)e&NOt_&*ysnWHpD}4C!Ve+)U1sb#V9_9(ERu9uy%#_V}Oz4H; zsEFuHT-$CYTpFiR*LdX&Q}({u_*cT(Dqfq3VXmX);lugC=0e|yMVW|rR0QeTSTE*# zs+c;eV6W!+bR*tjA?9J98Nv*ie@1-Wu3Kkb@Pe;M0#@0;#T zI7NLii1=C!z12@`lc&=ea@#$kc{GS%O|~CqCj6*3x`de!Hu*fCW-;96lVVAhb0l-!*yeX_%7PJ<0YX>G^^UDih~?1m z4_tFTHnwB`{W*T`gZhf1ovA)10+%c{83O^GiQg<=0)W={8aViAG8mX00jx88HsH3W z40SE}niYq4A|B_3xKVTgj(A6M04};yAX)vl|CbT-bi^ViNVeRp2l&}5VKj?wPp8pq zJurD6UF*q{2)hUO5nXb@d*s~p2ptwm^HnXT7G-(`XI#}o?&z}{T+Cu(etz&3$25VZ z=I&wC1}z@c`YYfb@*%ofwu9Ez!{d5)n*`wSUN}@VQ2$@(aSYv z+AHsSd)qPvY!q9}9gLDB0m=uuD4Shf8$gf0;k^*`$|4X*tAdoJwq{}C^S@!b<7^nT z((RzORb^mM)>XSrLy4CT6 zfNy6R;6!0rAFfS<9)}KgH?1}F8}NWVyQ+b}u}|IEugViFU5(f|b{y})Bq3f!Y#;;oOPcctwyjqU(P`exk;OF@Dfg4IL*$%ycqHG=w+*gu zKV^~6KHusE+bb51geWbmeivV17Ne~)s?m~%K~v1KT2DEUQ+2TIfH%&W)hk?`hxhZj z;8OqAiak_&5xIboGp9ON;y9l!h*DvUNbSdzM?puU@aDOG@Noc}I4nmprXrWNmW_mk z6QFB((fW6dK#seUbD*InBg<#=_zvyk6hYDrbNqTT=mvkzM0Fqg;O*;KI220kc0r)> z-^di`TPqVc19B?kV$Mu7kik_vas0Td+l`hPnwyFHcgo#1O*KWY)#~p&4p(_ckAanC#bfS0=Q&V)Dqe4{g+9j&%U7h>6Pu_ zC$7+-+qR2gJkEr)%9q|O?8Wz>vXRp~WwSn4{-#?M?1bIHLh;X55KVe2r_bo$B3Y4u z&mjykhq7}Jck8|5u$C3)hsnb?Z5xvDRb&_o2=<=(^(3d}@}|H<6r4cYdbRu+7-~L2 z5_9&sSR)d`eP+)XZ|0@zjv)-cC<78r3H`Q&WgVa}keVhtWB1K$YxAp_XG%aw0yS~+ zY)4=~Ww{tFc;$ZSa!uHFE&dGql$>#-qMBJiS9nQX5z zdp03&gRa~kM@K{{l31_dg}YH5w#&?tpv1iYet{YuBLEPd)q|;~TFfb@quu}SZ+}nF zMeoDLZr`Tt%)Ip6wcJNKkNFfj4$zXLa0r1M+th@rSH8-FdaNPfD4z>odo-Qj`L0#A z;Tij_Fqj_KARa_$ToGyCh{K1By?sNoC9J%Ij^Qew3mLSE2dtPAD zGW*}Tpb7x*(6Y+17hSga^QETas8G0Izbfgl-(~NZPW`R37ogO**0uq&o6T!~pE93z zd)iP!#eY%rf2MMOvv1a~lKT!+{8Ys<4<&+7j6j6V<|0KA7c4N=vHf|YW;UIVV2nf3aQ6e+`&L(@b3UP=U`js7B5F;{PeT#U+-|sKu^8L zPU}1t@&=~qI5}Igk~UYOo4@+&4ejkW<7(~YXBRTCgDPq-bMpgh#fp4m(x`(nsV7&w z&^+KF9hHh67pO==0FnT;W*>-mM^RF{jt#$3J`=FL=v7Pc8<2{I89Gy zmkFovx=u?LZ4B4UKN!tAnL0mgtMT%}$xC_nsvjE%W3#Jfh}o7LxuAFg%;TJySy0Dc z0-G$Lr``VDu>y(LC!5EWF8@?l{EnlXLz@5}kqH420_Vn=c5rbtj#H1<5!eJ7}C8&w1TEd(Zo)4=n@U<#(QEw3Zjtr;91TgQ)G?Y)W zyEwS(z<1S(gO+J&{8GFtM@rc*RFp?Ht>Xb)^NMO-P4fV`%H^sIZ13kLvkMo^-MRAK zobZDc61cpW7m+&3=83xyC`kqL@YeSoC9TORYJo#8R%DPgtO{vnPS%T~31@1FStl)O zQ`M>Sbw!;TM}SJKi!OtwpXo(n!dh-Mwgg^x8%b#`NgI*5hl(>Ep4e_*(IUaY7ZdWyTOYdPQls)9Q z#(!F>WK6k+y^7Neh%V?2qf?l9cbGDx-Njf_>>v||1${hG#9S;9cvZjssKYsVkVtk!^UR7N+x>*n(RAX#tKj$5nubz#iU;A+{ZZm_IN+EPE zd3c)eGH2RgZA9^&D|fct>vb)skj{gnoS@9ePal8Q4FS`=3z&=<9%P0v%a}8-fo=sR z&#Kyp5v8`XDV`^E_6Gi1VBWawzXrEO+^Tt<4R#Pyp zz=4RnKXU4LO=z2T`-aSMrK$@7R9Cdk8i21f?T!g0nu{G#6RwIAAxF)mDL><5s*)(3 zz#*I+8KC=K`{W!d^0TpTesk^kdos_b{jAL=k)R$RX2EO^i(abn0NLLp2km*u6p46# z-9@H6x5ayNN#Piq%Q4EKyk;aV?82#)Xk_=w9pl7&;ar9?OJ>c*ImW^;86t5IGI&a*uL@P9Gi zfC5F0mL^}z6dX8N_&sVmG?2=~WjUi7?D?9KgOGvK!zoEN?P^Yp+IO1-3hM2To^pL5 zA5zGot~`s39nRd%ySo7Eq#}@b@ipV9E8GD+wv1UqVMLS1_i}`CP&nnlyZh>-It3!1 z(0ZZ);mc0*7up|WRbb`$N*gqdgA@8D#Xp8Z8U*%)<6DV{8NM6e);dX-!CQX6E$_AA zY|xsOXI>0=Z*X*h)TN(Jw@9wrgBmrn>S)Wt=&U^~ZbCYf(m`Pt@o65r$xDo9 z(-*>&0J$NpEbS_X0Wj1Om&*N}S$nu9pim1AQjJ#dxk|^N-zS>?{gd*Vw&dWIQzw)CRzKc z{Vl2I#^HydK$H>1i6ME{owst0dQ{3w{(cxWwdaN%5`I!GrgA88GGDlO1Rsnv*fIm)I;rUSU~jV*5C%-eyg~7Z&il`iM2=1cwD(upeq+}&>tB>6pS%Z^(4szY8iBv+Q}@ikZ!BN;$>a_xlD?Z`plIM+bXgyh9z6@b`d? zM%_&p+dSmQ7oxM;hU4Sx;^q3!*zAtPrbgfjoWSr>34#BeA8LgHnL$EuOhUFCA-Luj zb=IDx;Cs4mLS{*=>y3iqsxcPOziYBk1?0Qh^>WJe;CY%b=Eol?@k=1+qH#}tPWR2S z;ldhSv=c58zhoK4KUtHIO$HQ9lqx_GUkM~xaRI_pz@4o@hMV0&n~-^?K_j=ipngM{ z-4$*{`6IfpI?9N4filkx@H&6tRO=NX!~(wntNglbho+mj=D=cZ6p_12!u-sUaLN)P z^BbC+(4Bw2XNiGaE66+pi><2_-OrJNV4h5Po0L4spI>Ud24oEqdpYkEqsR`*59l)8m*-)r`9&7x-7K)T8TL$Mu)*?G%W#M`skvLA?) zsy2{N;NCwt5=K0w(z@ATH)EQNM3q=S93;G9tv|yiM|~(K48TqayaB?$lJw|CZcf!a zuZQ;Mckv?QtdzM9X+CO@nLID!YQ^B&77S^SBg=1iZ31!67&BX`Fer4BOO;26q%xPW za3e^Bt#16Fe*k)wBJbRD1R<5^F*nS=*BWx~2hq7 z-yEZLqZK0ubt-p`s)Y5{acn~>&}9pt@$fg;cCOEqYdw}Bu>s==UK;{qyQf8Y(qE<2f1N63 zV|CC-L_Z)rn&IYnJnKpiF*q-Z>o0=gEVrJ(zUucpAdfE0YC~=QQ!6h%W@uFJ)pIT4 zB5=E`g|S&pUxEDse*xy81`Ti4=98&s9TLLX_x=SWY1LMct?F6VC!C-r2;BTK2gWrR zRbr*s3PK{4=PjH_tgL(Hb#B%VtK_gw@|vQ~5LZUgN~gJ1vza^FkC&bhW2EN=#@u!xqvd$3u<=<5_aK|6~oQ8b&*G~N5&WD~> zobv!|2zrlxB<}t@;=O}A7m7+bHe?SbQec>H$AeVK9Kv~1K`cZ|GODMBK!nP~zL@Rr zQEY;z3UE_t46{a}e{2Kq;}ET~iQRXIvmhb}y~Bb~1)#YVLa6zWOmdlPx{fYX@?PBi zOV5tr!8XKv<&FbzwCH$>z^F1ZS-NM2k!Go=rc{k8=xO9dduUPDWx<*q{n<`H6#tkWGPWl3|K3qP zA(^i{ZCTdymt@M(v+B;f;WehFX{daXfMtk!v&v}%^FF%7Z1LN=R5{?G8@W`+MQayf z@!2q1U_>%|Bq_|~-v{KSc{ep%6wynZHPlvmb@#Bf+m98;V(F4j?^rIaZUXtWP8 z0CO~xjkAfMDd84-<)qaUr^TmVQ$>sfY*m|_)-MalabZQ=u~bVZTwE8A{!YD9a#cPN zhUQ%r4m<9yO4m_w0z+?QZY>WRM77s=Lw1B*lJ($#1HCgNRscz$nN+ZY?hw; z8+-t$N!+)Y{0$4e3(Et?yu+;-h@pGg>$3HPB_nN>A#wbyA z&F;tLzD@Z5ML6k9?jacXl+Z9OKu!NCc!7KJ{Mv1Jfkk6y|qfINolg6 z3MvSJo>|a1&;M#>t2&H1;S9Q0t&p~q3VwqYu^&$Z(U=s#r);=}@^fe1ScUWVj?`g% zt=x2j$0BU@7YU@tj9e5ffgE&Y%hiKu4n^_GKF@W>F&y{1c}cA&`70_=W@2M9qLG5W zAe=W?%-1)H+p93f6UFHto|}XVL*;VR=c<{7bXof+`lAt{ab65a8ozX~bw1OU`D0we zSOn7oT;S#XNC?T{A|hI<(Tp7FFt%2(vfm}#>2Af|*!QMJi)cO6cdArf{^WzwIFsSk$);68dq)ISwoUiRK{aSW@ljq5^z{DwO&bD=` zZs9(M7f_2HWxzR#_>A=Es1-PvCdb4+***5;XUc(<<}F1IRZl3ah9_?jUKN;m9RHke z&@`uMtFvfZVp@$i`0|nLkl+{YQU@T?(Vt9O(MRtCGbfE7Kdi=)|OnwHaO@0RLn>s24kjMVW#$v;!W|k@~gSX zSn!8V*>-}DGw5#($K#r$N)UaM3X-^Neaib5+t~?_$xog}eX9=un+dKWN~2_0I=}eH zW8(D-k6Id*2xjTLDew{?J9#?@%uRF}^SP2m$Oqd}%#n6I)M_R5YAkokjK^C#fVqvy z`)}GeztRYsA9AC9sq^a`fH{54YgzAx(d(#>!P@+O%F!Q}ZUKJqsTp&g`_#|F35vWe z&LyvzUuTY??W0eyt)L}q&a;f$1sT#NN~n@z?W=@=9Wu#19`{DI{JdampRTU_^`=(= zj>R0KK}$`IP&!(mLZDti9uCv!Dt^%r$DPUq_$SwVVxgvA>wNVy$Xx9IjH~y~0=6@+ zDJPJUDXK(DMlLp~kSPq-$~~6t!`3Zm)K2|*{N_k70S#d?FX)u3;F@q*>4a^a_VgFWx{2KS!T)9|b z!BG6vs+;YFa=IOq5y2~Jk-Z&%LO&A|&R>@yAu8N{mwroi`RjJCza4F_8E1P>qc;tc zGV-w_Wb}O!cj#@o&95hKkV>#|SHL&kNy7905=ke&lZh2%l>2Gub9!~#<6#Q(xlL)U zNLb~Y)V3DMU;iUHpS3EQr(J^Js?&<4pxpiqD(P>Ev7*aRi6YaCLoDKP@!pp{w`f=Y zDHMeYxQ?~wnB=!eJQDhcl~u66_ADvxum{Y71#GwSIDjqMovB6a?vnvlTzggIpbkv! zKsxS5!W6xnS9(*9-cRMT?cQ!*QU?;flSwqVyL_3`!q(hHe-HL6n-zXM23A((?QXQ$ z;u*;$Fe(P3+_pTt%j1MT4e+Wkit&5hZbMxx+~cNGL?jpHcZSt_d;Mhau=*`HFA8B=4DfwrJ#lsFP zIPpnAy3=vb89UTSK}~8rgCK@pc!DPqy>Y>C_McExr(M$~#FiqI4;DsciSxKP)@t1} z41}wd_0iv5qKE(hvyxO%xUWDQtnVu(X6>ggc=js{(IAD((Ft|4ou z(O#nGW>7vtqkQY95wEK?)_PTH+%BHYA~CWNqc^#9K<6`+om!-aw%#kf3zRc97j;V-Zd%Bw-#GufXgXhzV^b3vKF=)jx9Vv? zbb-0ce=!|{fy?wMA`&1vzCC!I2J8x=Qij>runcqcWP-76HtyhG^DfuL!h!IJRl^M6 zm=qRAA@koS&tkH|^vq}M9Q zmmSDU0M^0E7|GoTojRn|BR zPNMBNHd|tL$ZiD(R7}+Zs@;^fv1>aAMGNgp`HQRi$I$7+69vZTDmOPlVWR4yXnmsX zr-5!ssg^X5wx)poZSHM|u_&;)o$Kt{z_9kuED+|Q_dV12r zIGfwTD)NZtKSpem*`V5oDzZ{=A}mj}LrDL_tq%ukvznM=SUwb2%5{w&37;}B&ef@@ zhBCQHqPk!z;4$hA*F`d@Ej_ok*K4Pv&7w0521T5^pP~T-XMDuuX`}k zbUjmkTl2aL5A;B4Y3cM#D1;@6cHkQ7FJeUQY%HRC$AVoth$%}E)luzsDHKw0R}f6_ zo1qvgEW}znk7E@-5;}Q^p)-23)i~hZ5=jfsT(r2yy$IyWJdRszceClD9s!8 z$yqJh>4V?a|CP=z=%GamF;$=YX)!vKiRvAxZjW#%@*RTH0IljsV1K-CBAIl6LH)7X zH);VnK`It<5<-D_pyT%;d}iAS~i zZLGL@?P|isAtFsSE02dP!7QU`IT}O*c=7zHrEPXfhRbu z{C!siC%tdD9gN2=WZzlO#LCPK^%y(|o;ZVBqEi2}s!Io+8!(cZF14Ha4hu;Amtr#i z$q)fZ(V2YWXv3-=L!FTd-0rJWB#*-%2I3mHS&f;+)L$3;SFJH+j}KD~Nalr#_!TIg z?Vj?--98vY(x?tARYu@XZ1K0!vpfk8`plI-67;g_37aMmgFq#~tvQx?^*KPvIxF2c zTTj2mTey%~{p!452yfDhr6(Pz{*;U3m4g6`DiP{_j?B-uvcZOHNRxDdB3oA-)0IHA zNtLu_EmRv3?{TcB#$c9=lCl;`hB3(INvx=ui&x))ud~hbxGo{AJ`Yi1c0-0z*)3~B z_6QRX+td#DL}+vsMWZtJ>8}+R%WkKdaO%9wnr2e9W05MEyC{Gl3b{*TW838;Dx-T3 zLpD*2-2cBsp8tp)A_rq@B3|DAk#?Ag{;;vJ|Ig_^k%x(yA05H&w+C1?duC3 z;!nmb+Z*@SGS<9eMMZO@4rey78J>_m9bV0KFc7$yn@S=rBxMZF{N&E=GI;;Q1iU^0|4{!423k z(0tA>s4AY`j^?zi-he&P_#_0FDbQa@Zf>uxbxp0VpSppO!N;z}J6mY=ejODT9ti~v z9^63cagh6TwIuYy<8x^CO`vmpq5l+?mdYOT{sojm;ALRTDw*m^P}7xEHnnAJ&4I9$ zoxEH;z2AtK($4U5Iu=1`T`3V9pk-r-aqB9Z@83#bu%HheX3$jD{@*>n{-C}k^fI<# zHdnP$u66%8pnV`uAU$0>|F$1S`+tV!fdb3@mFW!e2mn@~d7Z8fF6gF4FK_QA?T)U_ zM($3{M(z#3kiyXBDEj`zxiKUVz#VuK6o5R6Zwj2gG=uYA57LJSUTA270M-E#Ksmwr zJ9Pn+j*<)3+Vzuzr3uxx$94liM{ooO0hGkGR9*>mz|hdZ070tYCgLKQ!u)}R?9A%y z=mL@bZ4COav)&az0tF`7+137iTlC(?kP*=KVQ`5Ozdr$Y?e`LpA(sg#0zX`}~@=6$GrKjieo$m9DU9qV>l>8Y{ViRf8J4Jvo0- zetPgZQG*Ks3GgrmiUi{JBj_tzC5Dxjgn(wY&@MWBl-l-lcW`xjHvbg#w1RSZ2m1o* zcNQT`jXrd|U_B_=ycX-64&zL^l+G3}FMv zVF;8H(brSfNxJ}CPYW0=61hmg;wGX8rbJ*GULG1>#tkFrgUJ&R1TsQ;{-qDp2iU>{ z#-SgdL&yVjc65D!(&6hR`WH|zA_mHRw_O-SV)j!!Kt2GklL3hQfpV4!$$$(~emM?J zAR8vWg>-?~KLnt3RSpnA)>OYk`qfeaaqk0as=q`CKslF$!_bB*Um^YY%m4X04dMYv z?FFlZV7GsNAcHLCKR8f;zGMM$?fv{Jkd*h@0R4%8vA|mM0HnpqW!I17hq@NC8 z&+jtG1di?1achJKhS0h%1KyTk? z_?OnV=Z|e9hHiYn!GJp;S`=k@+oHmEIRz|WmQIA9_0bS~$#-WD2Kg3$ou zzaVdeV^CXo2yVBO;YG&}fOPHKp#C;MAAKM8Cg9=jjRFYj86=yOewHU2Hf*z;BQyXy zksn;uAO?j>8*dpcQ%>i)f{4-*D-j3mvql6p+6K_H znybw0WLHGfYKK#ZB^XOV&!7EwqzXH?wjJrcB_#Ra-cG;B9{SDIUB(y|ThQfMQn|49 zi8$Tm8~y1|+~U5?lr(V7*cP2P!z{(R`KK*;g}_h_4sAy9&e1-8tmTUb z?X>8YH*E>`4xK{`xu{5z)F%&Wxu`Ne7w$^Sy@_a%thfg~SP1$Os&iI2{Ck8u1*7FC zogH^2UbcUsmdH;^=(hUM^csWD;Sb&Z9>keKw}YuCwb&`hF&Mql&DCWcn#qX_j^}2x z@YV2;mAQmzXUY*DB%r%;w;;<2_F7UgWhj*h zMz5f>vPI!Es=z^ZCdO#06pw_;qy(NP;5tcTCBtmHz+4x4^UIXM zs`S|gbN~1wWJSvHSXazpTRXEN3+XVU%jpbsx%sc-$1wh%9R%?ulGSN;UsS zHwn0MSJrr(?fo~oCEidph^(!9)pnl=F*cK-nJ}qE7aJEo8o$2r+IGPBr_0_h*!;)f z@-B_@D-FtpH_8m?@hlg&EuREC zoJ@vB1E7XCHzRFR;_607?5dUI%5-a`=ncwsAE&d~e-$WH_8>AJ3OPAuc&W~~2qAn6 zZ@fDEtWI0elda&tI9aetMP#{0*%bO7XC?%0`T>*o`_14ffy+La6pAi(EqG9Lh*RDQ zjhetmv1Ay&sh|`6SF*Q{Gj8<|Dt8|Lftj3wzFyob$#M6#uhJHNFzSi8k);AXk&;6HKH)me;hUWyodbjeL^Re*>c<8)sxN4v873a4dh(_ z&oyTw<}KBN*C&P)1FI9z-|A{5MuSR5U_oFecu0ECIbeW^#==a^2c+YugLGv<+|P*N z_suSuPpi5H@I%cS4t=C9LvveEjbD}k;sPy)gFh7gudXcJ_VN%qBB!iXO~bHi86H%~ zRlavEQJ)Ho12IH)^`m0+_TVt0!=a2l@8)HOSb7J7=}zO4z1JcgR9$l=6?^kLJ^W(I z;q_@gi(eCY4h)N0QnuBZDF=KSmgs$Vxg&0=+jJ- z`Rtb$LN%>&Covr&OajF~Rd2HFFID>nZnLdystH(gvSC+g`Ry%^GyH}^posZf(?CyH z#DDaAvgi}7$yyq>>weU5e&KL@RG=N~CYDEc_nbyv8uEz*59(~wZpqqC{VZWSFJl~& z7Z7n)gk1$+tns79U0{gPW{yw5B)jj_T+=Obrl>jX5bhmyiA7#+q*4%tUo@!a+(7#G zI_dTi&Z45(P#Tjud{1yMa`W0BaEJQuvOY06L`h??JMtFiOHvq_cT9ZTKktr2+3xJE z=iH}NzAUSiQSIE0x*exjut;+$FWz+cZg)0mQ}jo+Z`;)xT?QOYGQi88mh@XN4r7_+qw9 z-|yANB~E--8(0)NXOp~qv56NoLm(8EUthxNOxUx?UlVrozC&V*Id9f@+$}46J}EX4 z!;n-`W(>v`MAFMw6%G&oIfsRPy$YWRw;+!%Ffd-qgp7HDw6ZffUgMf|9Lt}sIq7Kg zR=|iRV}{*_A{(x1@N3dN5Iy+Mm?aTGhf(4H!i}N&|7{k?)gYoN9p-(D)uD$cui5dwnbX2A<*0P(|^c$H4u^pck)Es zgVCwOPpO*h6>Y$-As(G|*|>Y#qeE&f)9Et&A-$ln=bgTXM@4K$EQqHX zq0ScjncvI<)Cm!2ulX3A2Rd%NZg0m~R!W1KE4a@_!LAEOn7x4$5)Oyvyz}4vENd){hl|#S`6O2mVTdPR$_QUrvHB&J>14bl z*trh=m0LdSL)F9BPH=3XfANQ@EabjJs)(gswBKY$$-edZNHWl97N9Us(%gH~3eu|# zDL9tMNKXuP>;8~*It8bQV$++B#18j6dGqG{vnjIfAIx{FlW;ru6nR;oEgH}2PY9ta zaDbLV)JGBZ^WCjWryA)m^F!@mBj%J0>>yjuyF}fPs;u4|gCow?`F>Ph-2&c8%`J2O zE5D;E{+Uyy6H%}34+Y-)=>J8UL@1rtvpj=$WDxq!q{l+FqzM+C7z$6$wdjI^o<4fG zT-C}XG`4-Q1bYYNaKxQw`k-fazV&yvsslGmSB0Z=0ADr73Zw{)F@#@b)=!oLlPj1D42_lK+b7n7Q8cNaf zCl;(TV>`DM&J)SW=kq0-pdd3Fk%MlgLaQ^0j7$v{TZS@rAlID$7<$ zjM)7=G1FgZQkbl9o9vPeBAS|3DcIawsUnowu~KPiLrWR1t}shMX!>w{-C!c{&nN(0 zi(Oc_oPhczYw{|)$XjgYvY3T*chGPR%-GO$hRkaE4XdbN)OTASgyQKiftp(bnIduz z9(3;jX8!@XHbTUtQc&8Z=j&T#qFzv)_V4s^zv~lQpD+C#tTJ@$tE>lN=r%4IK3+!9 zcUyWYIp%H*2t2fzd&3sRaz?d##3kI<{o1eZ$2q2x#7{|g#!3!qI9`p@xUv3;d~^+h zW`)7|Qiwc0#9M*}lh*Ob18*22JR5$MGq1;gw`|=V*-IaBZ$A6JC-Q@Kcby}ct(VP* zQ-(+=5}%Q7Hz}B2&4c|&y@;FCcFtG1dwyQ!T@@NXfxfr8k!Y>q^w!(kyv>&c1{_tx z*p3Fbp(B}8_hHV4?<3yXTSd5CCbr}AB=$2wcdcP+a`!k6YiBoV658IIVZ{JuRx8Rz z1^xTKEE^TD1fuJb#a<6UFml&l%F<#~*?}AO_K6VW85g8hF&go>8!3Vbd1q9z(^III z4_o08Lp2_-SQ)2OJF=#^lkZq96}4NAHAJyo=yK9^neUJI=agpdgA42~uLS#lM{O2G z<#OxK)mW$Ln#Q*hs$z5T?I4t5k)jzrtGNtlvS-dB)i*($(XpmmfC=yhSbCTtH+9ALQxp2Slq2LkEn&!)VO>mtN@`YH5VM!AZEeyV6 zWgdz;kKc2kusE@pkCIF9OvzlfA*5dMiXipRe;^j{J<`|c9#dB&f!g5JfZLDxdxC}j z8=u7_raPfxX`aER`K{-Fz0()a3`VzQctM@gMwh8<`h0Q3)?w{I?yiEP-Y%L`7LMjS za-<332ai&m>ma0gI7jQQlEFyb9SMtJ{dw1i>SV7K_@{QQ(k4C+t0R7=(0#5ye1+WZ zWZWKAEPX{>W)6-N8(g>eP|sXJ3e)a+w+o|dz&>@p@Dk&kp)Tmi?bS&y@;x0rd0cr$ zE2My2Az5p}hWU;n1MzPIZWdM=-$1iHtcS)Q~OR=Bhj$`Q5ak02jpZFhxL9@z2xsPgb3DRM3A6 z4EBqu+_pBk7~^u@it}50J%t^)_m?C+B9eDqVG%I8GuwMFh4kP4+i@aZ-M671_($Xn z{M_chFC&fd<>i~+0`XCpDK5RK(Wc+=snEiy7rR-Tg~a37qOguXD}E#$asPKuUEfs1 zJ~~}WHnEDvSWd^D8rvc9Yl?@TY5vGdIcHBAUf$*{0!@g_$r-;t193k&Jzz;ZlZ?)) zZgDJGl1jBC>!Z^^yqRFeBlBNjh(D?!E0@XXCXvRTZRw(%!mD>!gfl&`(3#N<0&=X4 z&nN>aZ1l>unsIv*91Ue5d+4G~h^Z%SUy8%9+EiBYY6&LMA$Tgk6c}^VQ$}2+GKmfHRKwH zw`6VWG);;BsixfxJYRMGLQjbm_NUA#X8NuN8y4g6e@)Ehc2v<^^8s?7xe5rIwOV3v18I5}U+#(Z z;xgDC1-b&%SzIPQ$$}dCo|iC9S@9!mRM&m$?}TK1rbOj>MGB4NX92)Dbw!h}?+Y|R z;L0bb>o~j=TB_NJTU%IW5YPH;Z9}v- z^AwKrQ5WLxCxgFllsdtVtZX}kb(1TbS!bHgPQ8X;$@5`AC9z2!s!_H|HgQ579|^-o zD4=FiH^tC|_=oNCDc%m=sL$MF+8plfas`8AEcy{UFi(o%G>e$3f4Ya6-6anI&gi#;KDvr0Xmv z`e0t%q3Z3DOZCo5}~l!vy!9{O4jUoZ`uJN$Q5 zg}?PP65J{frj6q7cYWe)3HNyk+Kd-K-AqP81=5cr-V6V0WG5#5h~%d48X%Q#&}cn5 zT345V?K3S!S>$_8cNSjg|LZn|_Vu@XbwWzpC{?Z8t~o~dIg-g)ouV{X{;6nGk^HJw!c@)a z{o^Ghp~2A_Qki9qoY$Jv$kf3X(|0OVVJEOjV3o+-cP@3w@W(65mTAm@eKd)(sloDV zcTvZPm6$`{4GRbZTz^g+1=w0Jb=92fU7m!K!ry9GqNXgzl7x-R0}LUwM9(dpEJaiW zw;pKUIu#KXGl<)rvl(3H3!-JtD;vZ5QXlOFTf|OVMgJVCPLc){yuEfBL|G?n3nCp`#n6BHgd8R2MKM@{=fOgV7JjZLVqW ztyc<7GhLv5JFnDJ$VAYh*f?WqUuNsKARYR}*=2=O2ZFuH7Pl&?F5V$W0f(;Bq00HGF-$5FMeB7Yq zZwSGja%@}!`3|cx8xyp@^JkA7y(PRx)M!(BY_D1un=1~;^8m-S7E7c|vb8Kd#PG3w zH!pq;X7j-N^e_D~=CjbHm4=n@_N6W~`X^&3-hsIb%TN1}evMfLpS_c4U8D~DhQ|;# z^(XhrY!)R}bl0rNUB>T2j(}x4fw*`v%4t4Ojk)fhISFg7+jItpjXKqM36NP15_?oa z#+mgMz%|+`5a}mr6^T`hoZ5D}6}AXgZg}L9)!Y=Od!8bjKkxHz6DfW78eBLR7l#qi z>U1&_QEr@G*~oA1&j(TQ2_=T6EgMqjoy6UCWI(ujbv~W?f!qYU8@pV8bqQ#<=2+c9 zR>5jYqordIpXAG)JQ$l`Y%>-Mn`~miJmMK^VkGED1G6Ldlb;zY$z10iAaA2{T3JO z9Q%=YJ4J_J{<%|-$&0I*v#ZHmER)J%__(b~$uxiSwSVSxl3CcO|HG#x+gTE2SS8F~ zKqb<4wS8Kyn?2jl?p!RU>@bPuGMEQhqW-3$KsG?%4u?C87a)`rX2`X32T=ha|K^^g zhYFXfQlfO>zWUtfEX4HZ4>^iWTKS{mgJ}%Bk88l{Ku1b*G8d>vAEbtyFT}o@v0Lvn zaTU>pADQgsx1eK+35?VCC!2e@UgF5Tw8gCEjqj|%rU40T(pG7-j$yJXEKY?m0>6y6 z6J^}>F--_t;A5>c8uKAV2~Cs!ZV~;&dzxj_P_J&V1s|MMSOhfzJ({Z7{j1-v{|L-hizu$zy@D_L7uFXQ>(Hi{ozXHR8~hAkk3X4%|KkN4;j7DcL&{-=sk` zZp6gJIY}40<*KMFWK;Jd`)hgna>DKc#2qy|?;9t(49?r1nw9jAfX2L>w`>PkV(qKJ zi*m)i!XC=QnR1gbz*Q66-Si}cMRC-^3pDZAqn6(|^XJpn;V|gkh%AiMcLa9vz_X!C>!^9jH zCYY3HQ4(&c7R%jiB!qh2xmtLZRl^9p-+T)H;5fmYb>|!rjDrQD2X4~^Z(VV5#Fn9UJL+Mg94i|APymP>IC+xYyZQJTVC?n9b}gr3*5H#Ys%d#>6+loD`MA+*(zHf6ZALMSGvwNvS;a3V~31ZFe1 z{zYyTD_>h}INkG|qbuiR5BIf75p|XXMpkCRG#qY7+E|2gJ0;j-_{hpme^DD2kq-ZY z0E9C-#F7s*W@*F7WHu?>mM`fSqDe}uLmRCG{rRm0UO7n^W|Sn24j#92h~A<6zlMfd z2eGjO#gNqOdLPPTKC=_sVS4XhktCB9Z9%itPSHs=2Yd#kWmMdz=ER0=#>AJU7jcC; zMA9HvjcBH=HP8An5{6!FRco<#tfZZGqtr|Z()5~YvPyPsFN!9?&hVs|AuDREjLQCX z$Fq+eh-qpyspobg|KQScZNz}a($~akN2eH&q6XY<+lL%+(Mot##EB0RF*ncSNLmyu zf|m??>-P#nMBQw*T_koZJyq(*ZwZpHtsqkVsTrezKk~0j3r3)jI4p-Y7t<|m+Z;W1vQ~LK z!U%?^%933$*Ud#Fkx-8Dj??c|x_ZOyRy++APh&E}*b|P#`Je?DYB)a%UxB3uUl>D9aX%v?| z#H8^jY<^l=5Q*$w)bxQ-rmrDiII~Bj-hd%WH2o^{FvrdWkMs3ToBR`h15>j>CrnF` zy%5!%r%Ji<{p6Scx)6m}-fLM5V~OpVB%`}3Kp@QG-GyzO?w~F>mNV1G)^|aT zC<4#;s{+oo_I)8i^^huap4rIc9>Ww!q`M~HG0Sr`jPrnaw(d=7UL%?y1OY}~J7!@4 zzw!RSOiyHiP1Dv9r9_@S!W(Wx^4alEm|?cmNN*EycdRX>>a07x>Bi)s-Cd{(s-SUF zslN1VSUbYn_R&2V&|e|{@OvjNd=&6q)khYgYYHiMJhvProXwyf8Xb=77oEW&8a$s)V7KS zP=)MWHQ3%Ty^PRHo05sElJ@wF5KyJ$*4OuWtBlNqCc`0Hq)`-EaPM*4KR(kbQ3#(v zrX;?o_6l0f6yHk-DGGSbC*Lj1f}|8yQNPlL4*)XS5o)Zg!Tfr!99+}s91MJ^eKGU4 zvdZr%2pW#?c9cv%(`n1HlVnm5Gb1S0mdIK#rR{a&b;0wGzuq~k-cEA3 zSbz|QFvFN1lO2?InrTNAPq12)I~pa_0WRVhia5XRJ!79uW#?%s?%0POW6Of;ZyhVB z2HE?Epy-36*E;`^3)q#MjMe_<;@TzV*~$@2vzN3JV1tpde-v!$FTg>|hC*hWh5nX! zsu(HRNBPcYnY9xoT(K(b`)-9eD5ZfaGJfUGNRb$_Alw>A|JE#0T_c4lJRB61?b{37 zJDq5M)qC+WRt`0Ew$(fYU8&1sSi8(5TVGVP!ziNrJH^=nL<#m(-e(+wZU2mC z{GxeD#rt!K{W|<(nWT8Fxo7-7nI@&L4pRP3g2*p5kO5x!Qbo1tvtv|}9o9g3-9 z%+Bs;QIYBsA>yUe3Y=bNw8lW5D4QCg5A_SW_=#w5wyna&d^qrxRLR`T!97Qi#CvOb zNpzA~CC|AhtI%1G3%mHnc25)k%J>Y_mpUU)sYS2n884>Jeo0AF0;2fG^#q$l;^QnP z5(PW51XUoulABd&Ex%J(drefqCoM)B&2}Bv$0Upy#A*bNKx>tYlz@+sE>gfgaJ{Bti#O;L=AIApGJUHBvnlmguKvd%GbCfKy^D zO@v|kD01rnx{H1dz^G8%*lL=^Aq>8X&>vzw&GSX&46+4z znJVjM9F++96fqW#LrA?JNaGFPt(0RhJ-3(@EJ$S|GDT;*75#e+A=EOP-IXHg~b zA5ER-n05qYtuxWQleswxM?vSKM8wSx)rEc^rr?TPhl|vt2QZ1cG|b`?IKPI_5DXG! zUWTd+vn8AmbRnxK#~Bq`&t|$Xg{h@1$|Y=(-0XOUfHc+NMi0 zme|I(j~&g8u;QUW2qy6tU3^Hu)Zv)u_@8ehVo76DxN~Xps)NVQa3w)Vl z-YqHyFdB7m8JjjjlYJHt_qkm;_O4RGhXrLsC~U{L1?oeS^srjVej0+-HAB00ap;mBXl%GJV}l((KS;Do)cTs-yb~PW&(qfx-{Lf*~bWPVh!$hj5(Zo zX4FB3`^RYc(~c+3jLTg?;(CM2tX+i%Y#={dMaAP+td&%Z@wKe%oel%N0?vJ;-T_o8 z=X{0Uy?Z7X9_|+OZYq1xF2`DV0 z$@LVr4-*?}vgM!i`VW2m#kET2${D?VuJ;4QA54tpcZ>GVTPRWaoWNGcK<>VP6n}n z#yRs#_{E!Cmw6?U?u>^*y5~nZ1VosG%#%^}!q7c{Wf8vb+pEw6B4q?BW11pc?ZWU> z6)O=m+qItTAAk|O79i$U?9@-q_1zEvx6@}b>^LG8_fr$k!rM3JB;?wIEW8Xzg2tkn zn){|=L540*;hJAHCWY-P&z5s3MHV3PV^T$V=ODKqSXNhm7!HG(It9G0tMq4iWF@q3 zu96TGQnT(gkp*~W8^P6OB`OtHBGoKxxy^BML(FtHCK!t>a#i(2_4}RbYaH|yPk`=e zpJDW5^p}RzYLV8wSURaJr-#l@k2LQ_4V9cy09cE|Ss>EUz_ZB+#G$f}C8d7_pU0V^ zV0%r~bJZPbFAXMW0?LSwtd&}*QwO2tcsIJREBYX5AW$m)4vxO^l`--XQkvMxZN~HIlF%ixYc;7Zn`3RxXv1`w1i<`Oau=B zi8B7d9mh+I3rNt`DOrdgYFGldgGP05s^2+Jg$4`kytxuHeQ{I|MW@k^W78+ZKB{?)Kosio*Qna}Vm&NqReR&ZI zjBlDo^TSeCtJ5b{s(+J9B`8cm=egTn#_gIR9Dn?7|IvnU)EXJnVa z3uX-&lX+qGAh(}Er%4IWZr4FH#pi^|TP}LIAk)ek=N{yP%!%I3C!&Ubqr)4OsYm=3 z$xAnrqf44}v+Qz!X<4(h0E+y_mPQpDyIEgp6Z@2ynd9@0_wlvm`aPM?*0B61%< z?olz3SdkuSVa=Z5+L)I9QR_*YwIfBd^2I*wBX!TH`~1mZxAq~#UFQhPf2_N|(NJx_ z^wC(p%f+pKSZKZv-NC3o`;bA>s*v=Y=<+_s)Jw}zbF)AnZ0a;4emxn#ao<{e_1`^FqLZ?vi5 zs$ad8`;#?&fmYT(2?JSjhKUaGNrx_ z$+^<|4Hd-_jqdQKYyQEe$`Tp7Ez=}-Xpd7K!i*=R^g3E_nbO`3VtYuFUAJy*=#RaT zgeWL;1Vr-Ies+R*-x);(tu{HLf#aA{RO3ojsc_1{#OOVfye}E)t4>;!4aMLj#X~{f zwQ0~62hah#iQAzzyz)o37&gcDQZg`xRd$jvsG+fWoji)*h0tg|Jyfj=&b$aW586;* zxtIE1UfwE=_IjS959o|DSY#=aGeQC*E&s3vr?&4-Ba)A#C$9IXn1jru-%2JS@&Gas zc6i;4XUDHjGT=U%NE8Am7M)DPhx!+=0G?0z_3qKq0@o0bgsy@Y#9AI0eB(SiQ71;i zBuYJ6{0LG|jJaqwndq-Y=yI8%`z%Hw;2;4>#3vk-*~`pQn61OC(6&}{y^f}!OZAmM zIEMbJKg56;kOZ^67#Z-ddJf@3}k~w38j6E$vn+@M^#*v8A*o#nD zqeCG?@jbX^32Hi=M@nT^(C{XOWrX_$d5LOUx$EKL1AZCQSb~i`;eoB zXKe6;5tp$B@o0Wl!f;4@p-f8#;rG2Q^)J2n?2=PSNZoFoZixz^5>G6Vce??=0*MV) z{qHDMGm%%p4CfrVO9%;z=_IJFwLb<>>^XJJl~NePD^p{2|3c-~9{ASh1QyL&n^8ta zbAAt>rl^i=Z*Vozl_&j!M__?&j$~;$wy%R@mM60WrH1YVP(%$jc^2W3S?ye;#oIK8@9Yk=I)`1L(t z{4C1o?d1<_)!LA2x6=2vU5*%h8b~$v6ZgT_sx93WbOoZ^Ii?mQ5vDowx0Q_jR_%vd zUKU#oNDoH4tH24gTqJKKJ!Zh2m{0#1=IIBB9bXXgE@oSON=d1q2Jd8)qCkmn(%`3M zg?h%gz_Pd4+{ukmHT_z|kz7;lwnNd|1AS=I(?G8h=z>dPY`fCF<9_RKI+HikTTZVw z!~h{CNhJ;E#Oo{U-gwDM!0aZHOFf^-1 zB^l__Z6#>m*H|T4ibNTqRT91ceEkz#*?QATt<9dn>qiv@woQu(b;)L}D2k?1Jz8Po zYR9gbe*Y*tI%f>NAPl|Gy^t?sfnoo(7FL^A(4AQhH8~_2%L-%Y+B4`I(;F`{6f^M@ zR4^B=)JyVrMGO`XzQ(NfS#%4>L021aTMg9#&ehA5%Xcld1pC{so0qV4UfSe z(ai2liU5HydRU#aAPJnAIgKL^z;HvVUt5|(G!ju$M@|GHvR=J@*aui0>g{j;) zOQU@tKPpZ+9QrAc-0UbC;*8&;NSEIkdBJn$#k&ygFCd*-R zv%WZBYfN_8(Anp%de`srCX5TM5JWvA$x2foaUAd^O-n^pxt^8_MHkf`QV%NwWfmiR zdWfJWpnLP)Ui?GH@Grql&Bs}2h8DRfcT8`r(F%Qzv1+qDiQZFfRU@S!vU<-cS-sUaoHgJldR?v(iCJ@3UJ^!~0XO#%H+~uH1elyK!FHqO@Cm5N0CTP zT(XhMEKQpN$J#T;vWrZOis(+3*_4aUEpo@8*lM}p6KfrlYQ4GpwAa6Cd75W+Xxd~C z5*u`n_c@M3pu>J>ccvM;(T_L$&=gWbjIOZVWSA%m6Nfh3#0?)(nUq<}od{0yvB$u` z5}R}Og~U5TlZ2t;qJ|k}-``I-OD~DML+n5M0^P=pr@=R?`|kWfsO(v3f3r2y@B0rv zx>2`;!PLNFzm)6pfafvD=(<^Tx>1q1(>HGj*E9v6oqD%DU3~n zEq%%d6JRJ7c{w!ZuLo8~dvUeG`nsX}dLZU_$KYBCm1vGkbA)s zjH`4@?@EZht<&DyI2F@kV~}o9CMaByY-qctPlTgWPkfY2tJ7E(Zh|9X^m-bcuipCX z_ww9)${D*V(S^SQ710qZ^@8ynHmJ|8zQaY|$glHL#Z;-D} zxwM&17{UdTEQ>Gmc{%K+`{RVh&i6&Z?9Ih(1MiN}V>Q@@s!vRKF9!n0R5(tng25T& zVZN0A9TIb|Y*=N%^-t2E1e7qP6w5vOCmqq5QULi#=MJfm*httORI&XyE@g-8;z2Z8 zMZA-&V@3gpG4~@2R9hn1i?>ivi*_kaZ9irW!iMfLq`;xJbKv0xq8K%LmB{5Vy=g>o zV@t!v$nby~)8X$jC-LY}TmC^AqX~3F5<6BC{o?_fvRqJhh*BROgbJUa`?CA3xc3iy zWe*Vn&_rJ4mTYxg3Sl9i!hsa}{K%>L+0pVd{V^2H)d+%eBcEn^Sp5b|n{ab2l)KY1 z7HzhdS>dS?kCV=;zZTGASLgYB76p0s)83q6&=N zEz#F0Meg!*xL_Mpj?+avRyjuOV1u$A<;Zl-&`x(p$v35gkBrG7)3+ls0@gTIh9+9; zyG4Ekn<6`;d|*Sbl?Me-lb$CN2_CmO>#dAB-Eg5zjMqT=vhoIkzmXAt)zzi?kEG9E zX!9>_{w_rp;$#Og$Oaus2R-*F7!Wsi7dLJCQGz%v$W666dC3HFybm_KSWIW^qjAS> z2{XI2McHhZC+YeMyhn52;ZYXLrhqzx;v^m?tqJ#J?d>NgQ1L+>zDuse6SvsgVWhGc zJrCLDePX9#h8zhn*z)rs;-CzKcI~ z;^k~57`&Xp8yXN8;}tn(XS&%G?7y!Q-i&osJFr~mhbNyK5gTTQ)g+_|tpWo2&xzWo zrwv`dv^GEzpJreSJ+FeLDHS69p?NU&5;MNl_Ntb0JbR2JXe-_mEAkO}6aW`v{lL1r z9!Q>UflNJ3DsKx#^qMjfN5}^1PqU4ckjJp_TALWS&txyDg$N*No)h~*^hwdjIw_jS zoztXJep(b>59B#kAlo7zy}^*$?*sm`sJoX(_^Q{CDR|#pK$bKky10$Y_?V~q1`1KB zR3NmDWxmF3d&WmDRtMd4nvN`LpvyL5)NZ)pvvhlD<8Y){h2E+zX>ZVyAA{m|A~QzZ zbn=4JZ}}%55-Bl+dWnWmg5UsJx0^w7&zf#-)7cI4=PK>PaC{Mrw!BVNPoSD-{>_L# zP76Fk(8X_CmbKw%B%=pFlt5yx9_$z#48N&x3WS$Aj} zhN~mv!2k^J_-m0ATj(tHWWo*>Iq>D?V(vGyK9Eh7cmbwhid(a0y5P1cvo1m>oLY5C zUoe6r&?ydZHkt)ts%Q6x)9_YNlV2+uMV}6&O6geCl_bS*<#no&)lhvzy^`AT<<{l- zjL+o*q*WVZ9bhuw!3o&BsANY#C!R0wro*=1!MHAC&2=)2xcsi=l~eVKJRqNMkw+5P zTvBuUd1Al=Q2gngZ9^3R7zxPrO`31|vV?3Iaa|{1>GtlgHo7NCB{=yvNS!e@&aU|C zB5JNjUj-sR)kJ0%`r3gzpx>P0R;mXN7U|`!-bC@Q_OCa`W(ocoZCsd#TOS!!eY=jTnKWud zo2!la%iOaXx=K{zcHczAzuc z82O+A)NY-&^Tm*RZWiTF1sXzle2G^BrG#KjP2X_ewj7QI$3!N8IkQ)fW#zYkuxkpy zhoy^pn#3MJHnPOq3H#J~<CPKr$6ylp;f2W*7!`!+R6tP@66?Z~Ax=WFq zz=Q-O=wDR>^B}T5VrO`1o=Wd5&zaFgU<6P-`5O3x3a_F?9no2tVBs{OYAyTjnDA+sM-!pYqe7_iy_tEV z?bd>mblV{S1%w+Fbs9Nc`_Oa7$jKFOch$lW)>mKv(=i0%nxY}5a*Yfc%+ESBM-+0O za{|!J)MJuNrl$;|$z~PzP!}v%B8T|&4XPo01pMwX0BeD(W}0LY`x#emv0{9$`@VX9 zKv%fsn>IF+AyNZrXiYoy=9i#2%-sk%oD=v6eIi!{mC}$Jr@&3)yLD`#ze23RYq|o7YdoWT4XhUJE&(Nda{&j=aHVO3Fd@j&A|_?1^x)@U#N_ zusp8uGc{gEmbuyV!wBi@^E^a(I_?;4Znw!0hsm~d#}NiTlW%1{9w7V$>R|HHJD(0Y zh6cfZx1p7h4yEkvz?CDc(f5$6c@j*S9_$VgSwgH%Ap6>M?|D`~e^qh(o7H*sG!2)D za#De?amH>)Pe}EPn!F>+z$q(^yTFX%KG7VT^A%gf6-d*kGv|3JBRt9{Mh*D=>L!Xr zLgp0J*6-0aNX#gQuEu5J$Sh0)O-*crCX`9hlt*lxUsz7 z{UP~wbTfbx3UCkW}30zFERG<)^%}0Of_>Vg`)EtlCBExroY}Q2w4H z*9rlY^=dk~#){o3@zfkIV^FsaT^E?0`kfY=FZ>;+Tyfj?JWdlfut%faco+}qIv~mEbd2?k( z)%Jr0-M*!C+0#S=k-+M#snpk;(LqbXGsvdHg&{gez2iWu3mWT(ffaBr zLW@)X9Msofq7!I>vPyXuueYyU7V$kdrr9V`IUM4y&>pu=0jr#w^dA9TzOycINx z+OwKw-mw!F9l4|bFqSAyeEepRNZ2^W6=M&4LL|MQ3oR}EH_W69;#rGnPlP1*jw~YH zdOXq0CLku5iWXF}-8W5YYZ6>#xB7cRy>e6PES;yYN3h`$TYjY68;wwitaE2Nv&1U} z#GYr1pu>dU1oHNag#11Hdx~U4eJ{<+dn3Yab@HwR^Km#v46b#%N%4@5ZN8Q_KQK?^ z)!W*a?c4%NiQaHqt{NTdy4+%k3)`o9nG_PPQg(K0Da(l$P78WtbX3|pY-+frCqpf% zN#7Iby~Qj`yoG*ax|2snA_kmcufmA($wN`$=UC;A+uYivX!hxY%*N_l-DE~@1^0oA z>lM25gt~)u7;vs;SY7d>kC)ac%9=fyc>`0_FIxUBVpBiR$A8hUL`cq#z^EOdVn7?v zzfryg{tdp?y?(g!6DN7=G;RSry(3YVk%V}k@gR;9i%;Zc4TbGzo})B;5nOy^Bc7~W zsIRC3fCAvzYGMDJ#O5}(WPq8$`VUK~+-9)o`=U>&kutWy1qP|Tzm?>`#P>IY=k}Co z!!whWrmNmUzXoMEwk@VP9gm1U&`L2}VN7Syt#f-a^>4~Dr^F24DPupPA}M1Ls%%hO z|G9n{!oHIS(18$`2hI&=Wg8|!yA(vvSyjiQsHQ39BSl|<|hb}W1FMThm%Ira)$-=z?# zs>3VS0HVS!NU;I#tVJ@e?*t)7q1@#&%%wT&eNXY0E+}(UIL;BY6QZ^%vxeY7TYHUq z71Rrzy^;H5Q}3Nz0qGIYGGfh%1)re_Otd6zS%;{r~`L?a1Ec4>{yX`qMiviQXWk&#CNxm?P zYTH5GhzN4$eB}p$**jKH+mn@FV0)(7;ox7r=?<}AMhj8TlFIE}V;7cy_m={DwAO}A z5V*q5|2lgs^ufX5InPx^2gNKTAuplJy=SYDw&Y}D+gdhI;%8?p8j>s{i_CZ26Uo4% z=~@S)&Uy;~l72GEJxz9Uh5T-YU!!cRcB^kiYO-KkbQRcl5m~=IFKBMYZBU)CpM4dd zdGw7b6ck^60ys!W!E#&PJq6{ym{>mFAOcYqd&9x!;K(Y!9g<038J|1D^s_G7;ub5? z9t*!Fe@v7%+>^KNETNXqB{xF%;8$!S9FkyJzY&ca(zN^6y?xB|6IszTw|oDz31^Is zk|#3^B>}5Ay1V>&7@XSVeMnIDfoAVAs*_VF8vqnl#bmck{hvq<8r zdSIidMMlq3+sW^E->WX?X`nrLge$u-`Ml>N$2qwbWO+3%)+(50w#S4i+C_laQCg5% zfL-D0tnmL=?9HDK_M;*-odJr3Mwxr9LyND%@V7p_KZOq~`158WGhx2obV5}+&$0mX zK6f{durSh4m29a^2uH7mFD9}{zFzSmDBBK02I&^_DhZlrWu}xDIb(jm<1DDo_l%Ag zQ6R!>IX^ie?5F+pxe$^^H$;vK&gf5|r}`HB)5o*$#oM3B_XZL@m%Q_tqJvpFVV zB4|vR!^?90vC26978|)KGi8z?FDrZK4*GmntMDxps!tVKnCNjI<*>&){$l`QGZT#r zSfc3=f+LHhbv=FCadIVm`N=%1Xcj`vhYW0Eua*R|itXMXoqhhz0atta5X}?)AdII& zBNp7J1+N+?Q{jD6%qCg{oWNcINrX4aNO#{_XgiXH@uSX#)OOs>BJS_t4SwP6OD1KI z*g^Tu4Y5sri6e3jJq?{`pcUSww7fUh`JAcxJ$qD-UUMR`Y^)+;`DMkx{%Bo`q(v3Q z!a91(5~#9c58ie6T)rp%AL`qaDx7pWxyJ6oOZZ5^Ec@YZ`SLO8tk>Hpo0@dxss5H# zhH%${r?q7^#PX#4x6?1B(``$>8Ky@zx0e+gO>m*oJ}TT)8G+7bVXjcO(Sd|KDiRi? zIRQZ{xQAHcBb(7DUEH&iubxxA8udT6Xwa(aU91-)ofj9Pksc=)yn<(XuT2z^VFA&p zoA3NO!7vsx-19;M6geVjKYW96_4a-xPUIGI4l~(vt(!T7bIz#v@8q2O2J_j2TyR>d zMAck5lu<w|$ZsEAy4VnswkS)>yo1 z>StRmnLW1Fg;qAY1FBWtr3&rk)?N+jP$f;1Wbc>{{!%4;nPGY`j95X@;a;+xV-bhb+yE zHywK&8}h)hcYAUr5eQ2C?aa0+2v`sIAJ=Rfx{P=TM9Tr$QZ<0h= z1_Tt6-|y9N#$__JGcBblQpHKyi7XV;!rV9@OS+s$YA?0`jBfi11KSkHFlT?6MB@=F zO$)HjN@MR=5;UP56co#wlTTOKKg`^>iFyp+8B_+l<|erbZ@%$E zZHgEH@5IEMS>TJ#!B}i%g-#j0`c*jJTTGjCkEU_Ir%lw`RBMDWYlYeNuT3AQDqd{* z;(Dmq#ZvDt=OmWrC!}$|IKI#fX`2;y%0?^-RfEIJ+4I_aX1CJ(X(1%d$*a~2u8B+>(sb`PVp3u6so5ylk069zANyD)Z6xB?3;6F~?$ui>@`Jsg3DNS;4<<+i>6#~2ue6enug^Y@q29(uYwC;lX^Ky|Q zGDTA13l{Q3fQ@Q?K{S6HeNt%Hc=`F9%Qin&7(riKL?v=JCL^r)wY_Drrq1y(&J~`)jGE$ViCV3uD zRW@SHly$N2eaZzxged>bq9`LX6CyB)gu~p#4AU#}lqjm@S!71{@GP0zzfGM)D7=hi z5l%ariel#}GzASa=S1W_2(fAbE^e9T7`ICy`!(HLacA|O9W1Du2uSm*Tad2=5! z2PxV2x2QMnBk!~}4dWV|?#BZ~$k!a)vVCqt13B8pPI_IZ`Az@by_JdBTA_>0|6VJR z^RJ;jyvyE_6QnF*W~O^w{7**(8J$}bCBv_CYOGelRPvLP-9z68HJ~3D5hY^>C`Irv zTZW{YkS>d&>kS8VUHdVAUp4S7*~WRm?E#<5!TIv>VsY{z+0|^Ov}tpC@62?mbX^i~ z=P)BYpg*(;NqZC8=&8r>a;~u_OLQS|OS+yoS+EKot*vj%Rf*>-+u8u;RCMAc-_}?8 z3a?MjKy%9${E{l&HQf2)23#E9RTwK?cPWm>o{~j|(J8R%UqfsK(!S-JslJK|)p@d; zxveUQSMwOAw6!zMsr)7PBY#gh{Iyn;ieV3eUSHl=ZseJj*>bt25ggxAu6QuDBK>?T z;^OR3t2oikuocUN1h$A7Pur)L94Bdh;JD8jfP!FbF>%>#S$waD@X6Lbi>zTn^e($q zKD3`F;TLCs2g`(pQAQxzhd9 zdcK$2)e09rpv@EbPEzlM;*K1-s|;ycva&n+dOfA_E%AXjps(Ov?ac|9deG`{mZnBUu@LfNdBJv~e(5EpEYb=BGE z-Y$_n?@&3pE{M@O|FGRDH1m`1|fdUna|UPE+7ZcLi}t zk`94ac9qzFpVdxBnGm*<<-vY~7{R~EBGO)ebp1Gg)6Ql3rmxF{aoWxzMFACk9MBd4 z5Op&-C_5)-<{_o?O@8X}-N7`{f>+qr{vB;iosv4G`6HbDzxBpyA7)Hzd{$3Q>&j}m zK;-sSI<%{@94tCkqOED~Xv$cZR0+yDgnL40Jb0kS5DrW=$llWj+$rAN%j1n(wSS1` z6l+cao{7U`z6&#+i7OHXO@62y9D0g^I}X$n@Se5Y-*0*woZ=H!g^Z^u15;oT?VNDe z&UR>81U{%&z*pg*o&XeM+=p%Meeumh((w}Zq3{c83-(0t1dL>|Q`4U`R^0Uq;d}_? zuOf7cj6rxp=}wQpx$%{idbH0!L4Ih|<|2)N!*4ebMa}*P7y@wwg00*j!Kgvry5)$_ z)D~cd*>fVPM{}LiDF)W@_ffSXK6Qbzlgu##?*x0g!*x~5n)@?BQQC3(*|e>t+IMF& z2zK`aV6@jo@K#||rfu9)S`lv(fQqk%*__Vtv9tiyY zvMG*vdP*GTHfbId>-GzW{N`^B%UQdBO*X+)7Jd+rGk!KzFN|7Si7Zij z7@)8lw_ci-+Y}%+lpX_t!wK?|~l7Slw@jv^II{KhS)Q zcIWLM0El|U7!BGwFb^$0mv=^xyx11VrhTwne462yM_T&k0>);DGoe)I+qBL=$mxKE zjT%AAq!CB7rCeoR7GKcIN>|_7;sloid-XQW$(#`T8&s>+qF)U$v7CfXf|i<0ca;>> zMbrR-}0J*^F` zJP}f(LTUHdx=nw1Jx!Ms>np@dUn7#t#>MweGc_@-Cmg6I_CKC!812Rux*ae3GjI3=ci69AH z)S5x|ng5Z$Cv&clNaJavOhNA-K&arcv9xQ@z8c*cY^HoL-K1GTbRp6gI~6+{ zFClEl4}Ne8*;Lj`{aIT6S9ND(cJyN&nt1YqElmXYe)Zeo|r0eC+A=MDXs% z$h8JAJ)0NvJQ)r>)p|`GW7nl+gE2alvR@r)$FnreYR3ZSFS-cRA%@8gL3@G<5?%QU z=eosL>8x3E%J0wtqL-BSOD6bhYoN^zrvsrqG@`X?*}g~@c6Ln1Jwl<|p)CV4V||e( z*Dm0M&wJ_<4dVbtNv0b!osyyr*Za@G7r%T|JG>GKyo;Y0i0W7;*7K`TPXE^?!q; zGXFP7D*b;#Qt4TkSQ-A0nfjlQRC-ocHfFs4eg6+gYP+#gmgF*6L`TO$D`?9u{N@(1 z+JVf$^)(K}^&kJ;>uVc+puVjDZHMDbcGKhS9@o0OweQPP7iH%ckMhwZC3In_t7!kf z&n|c(DkLa6ep#Ir@!1ceBFK4dkJK!cBv|j<_ zDfj(WU~n+FKNKEhBQQr7rZnI%4uCt}sMyp1;3!lc^Sh*6y(<_!1}1w?roYQ^iVI)+ z3%tB1I2@^@BlK)8)@4+bFT+>(_aI0dJwsiyt7CIB2-;dYkWt!UIsnwO&5eX4KvfrZ zFPfRYks(+uD{vWL6To@JK1Bt9II^%au`)-=%U}h~pFhtsKcT`(%F^2RzPA9S6T%VS8o-W@}=5m1ACR05!mBK2p;OUgIBd z%qLEU-ksTP!KtiE>mLe$ye0sDEVuOZt^)ssX%~KyeLBfa~nQKOo|(KNDsjGDn`X9XOA;dN)FT--nHF zshqv&5T7*+C?eCoL*wM+V}MrCR9Ad_oP?Z-uA*@WqeJL=uc_BxsAdumw0?YkWs!*s zxfu69EbL#UlRf#q^}aV!Gs6=jqgTGFlcUo^YY(`apROAu&o0v`(|9Mo#vnkGRMvjJ zvz$NbjFKHaPWJ>*^MCg%ETSB40!>HAY=5R>un|YGA5&j)y$B2(I{jj)v;b6a{s2sT z#6@hR{|ddFH2(u#K%&16 z%<6WQjxIoHvHx>^S0VhZGY5hIEC8S*0O)RF!ThJ#U$gQ@&H6|EPJ)k@gS`X5%*e(W z=woRHe1AdkayD`W0zghKKp(Gv8va{CVC4pwTAF~~$NYV(ApDhG+Rn@#!1FKlJCc8! z{%-(i|JtT>?|anL-pWHFcjo_~1u)BMYe{M- zGW_qr{N*KXXJT(^X=e^#D>LoK1o5e~k%%naR!`^d16m zZ~^%M%

    I{wyUICxBVxkLq6%H-K66KN9yx0JFk>q>rosX664#Jnx=Hf5&mWOQ64v zJOE~s|41C~Mw9oQ@wYoG%X=>1f5dm-%zsh;w}u_SY-Z{D4;Qv~g}sZ@KT^EAnEwsn z-ERKpmH__K<-M@QKg9P|E&n0DcW3i=0+x5_&vN{2e{aI}Z;|!g!R~K7@9o>YFXKP# z?=9K?-Sc~}{Xfhc?=3n2ohCZX**CE65 z_i+B-1@)J#3Uacy25MTGzF*G&aFI6xIa#{vvb>)Vtnd2wpMU?S|6c{D{yyCP5&h|t zy}K79$2)n9?5rFBR?hcDc;|`3=f7f2{&iRUbvnK8qJPVO4r%}p=ngbNSXs0;;S07( z`yN{6D_$^N4o$_wbW({Us3nsCwen@Uoe)nfcZVD(R2b0gpGjS4FDJ#T@0$`}SFA-9 zjBWF}*^*o}bz`b5yldnu?@NdxE;5#*!K5CTDZlJr-bqe(D3g<~UBWS&*_zNw0#F}2 z66I;{dW>P4d_%uVCD$u&UC)DdE1G9*!g8{~a9>6v=pbC4?f?h9Jz~X08}*8;(9ap> zhvJOMz&P}DVIEW(SYUi)ha-WIOXEdjGU&_*UD1MhTKhUr*g0|-?qVt^I-l`YzZa)< z?pKs9+B^==So7T#YUNDss@Z!Mg8XhhJ<4AsF1EcD=Get;{qwXWullobOT$`4vzw)e ziLu4d{5@37<*+u*&U80t$aiG@^=VJieT;A@{#Qw_6Cnb`7BjPX#lTQWktntUEH@2m?(t1SZic0EfJIWib9B?cRFY zc3nNK21LEULpD}sR+>(QrVg$fqwKQL@G8+=QYCk*=D2dpSfB>%)RqW`*L14XL7J#L zMIK{8#pV)(EU|oz_>E97yt4x0 zi@x1H7K{y+6%*q-T(F!X8w)L#@5;|G`C-&TKz-`v@eg!Uhfb>c1tzQ7_>5Rbc^d%) z=>%dkryKsZe@pJ#qV~NK3fqvgB6N@wttK) zCO6?;c(%+WfCsyf78jTjniwwFP3uMv!IE9w{fd&_| zJ}v_#9*N99P`0LH@5wbO+l_UCCY>Uye?-AZWYn*6#d__TTabh_ESz+yo!2Y<`qa3R z6{9h(LYz$5t=C^O^`%$1vqCi!IAG6<3?rPSeM~B`w9n+OQ6*vx`k3yqm6dQsxQh|-K`n& z!-zPrz&@uN87c9adu2n`Rz`qGd|2m4n|O2ZbEpl7a8qw6y}%D-%hUp z+|LWdHn-~}3`D2;nU)pbKo)LpcxVD)J?gyBm|o($iBEm@ylVrqQwcwdk(hw8MFn9d2xMo8ll93C^!%KUao`I!p)6?X=8G< zR+WfKBUO0YK(VbC40Pm`%1RphfIRdl0R_frbv(THkfBqAo$dc-aTd@yZ&z2@eTYb{IJxDaRkFJa zI7L5-!IPb`(vx|?j+eLS5gweRK*QczY%_Pmv<>~OpcI4m`w%mfne>HZ*3IdD^?Lvz z8qG_o&7B=2Ga<6H1P=MgGR#x}n8sVJ;+ynu5(Gag<}sv}i+Y_=a>LJDD7-{5iPx)y zJs2;aJ)hkpZ20VEGXO1M`cH`k^V`Vmq{XoWfgZ9I^UDFUs-Xsu-QA0uUg&otJA2%) zs;D;-w^7_f{8u5Ko^9M;MXvbW24HF7>jN^`B;yt$(?m`3q^n_U*PWBDGUb!lVLbR< zM9`rWtQZ;Q`C|}$KUHQ}ddcdRE2#55k!9tIM3$xX*wBTa`+`g5ZGl!HqmrG#8u+1C zBMe!-gua200Fg5)+Z5mn*OdSPtr6tG%U^RZRLi5<<8xX>D0$c!lt;19n^N)CSFYEW z*?u>hq1PpeRV>|1KgRvg+Q?|`yJ5D41u7aqQ52Q2_pIn-fDkPs%K++f$7^MF4~9WC zKv;~aqIRgq=eP!3)|zFw=pcfYY`_=}qV+Jzyrr!fPUgC4WX%F$*zcT*d+t4QsHLWf z@pR;3C+G<5JlLJlr0@QvVZ8A#eL_{^6`Mbnvqh(y7VkBCA;3^9@l=X~_~brdG1r41 zcDe$5lk{#V_^GklATs#zZpmY^D;oQDRSxcKKmx}KJuc@mTg zm8u3~4cBj;ZlZ@cc##u)`?T^yPvIBENCBqDOWA!_>E;Jqol|J#2x%dONP~}s%U;XX z`&-_f{?J+ULABBL1V6-oDXkLseeab$byeZSas3VkiF5_KB04WjlwC9m?_$Md~afij`6+yi`ty5_4%tstlBP|KIGcG&MQOalHhj1xK3=ev@ zn^)7S*RPQ=0z&b(^viH=9*o~lZVV1X9^DL_T)9hlaw>n&e-%Q{&dOFj`&CYLwS@Ts zZPJNS|IKzqp0vWG!VaR_4!#3l^w2;~;US94EP_g9 z?7n3;wLn?T_caT>^{Cm`ou-+M$Zu9vtbohvxSO=(!Pk(sRGltS9O6ks+4XW*WuW$Z z{hi7}e6rC!XwL4+&B0i?eTf6Z#5YmCIJ`a%|r768eXz z&fXmf8F3b=uNe>QOY}d&Z{@o?=0%PS8uOllcBE5XCxBfmcfpem=d{jKU9*EJt^{O9 z^?G5yU!ml-{hW-o4bPcNKVBDU8DuK7GAdq?%EYH`+#b|EPkg8|%=QO7DG`wiNeiGB zg#l84zt4L5@6)g!%hy%`#>$YDCyyaGEjmIXcKrBDSWjk>)MV(qOKp_M2U{JaxOW*% zXzeaP(Cj}acT5=c1={8%TRh-a6(t1N#TWj{_|a6wwnHzD3jpuBc(F z2#F$5v^ST_*5XU}X9gcX1-DNxoK(pUXM+ro?0!fE1KE2#%3W1l^gnJT5+`C4^wD$m zwkZpLu^XDAz0_n+<;5=5arUtwE7(L?SV_;*j8CtM3kKL9;~RXg#~W|K63Y~ON*vr5 zz<~u)d|A^MWRqP6w3|xj(;lE?MOh)0*!ai>-ytC-UaUnPbmLatC0XBlN^sZHGQx2%Y*wm^YfE1#?b-f&>j=o>Q_kmKn&eycSQ38 zn;vmVXG9l`Tll!6eY(x1cAtlD+qBNP6jgye+%8QA@dJ{jS zAkcoa6006S{ieKChW$0rvh}+p_~(tl{&Uj^tvKS#yzN#vm<(KI^^{aEO(dtZmO(P5 zezvd4vG~P|N1)@0?RSUn07w-ZpErmY_n2F5-oZ%3$SBie#XJq`)E%-=8S#9X)f1CD zqMVr^kg;cBfbmb!I@|iN%AlWF#bd7b$j52BaEvi6$!gUXRbb&R0>_DovXPa0N&5D+ z0%2d{QOKy%xqL9C)6$y0qJpo>eX(=O93aEkwq-0~_?D1=>3VV5J(ANtHqsyR49wGg zEf8L!6vlgOX!bxg!hJ7ks`>d4cUJb7ENRBqyoQ`*W`nlXxcHDgKma#j}ri z>aRfgZ2it4Fb#QQw8<1TyZBNbF=SN{4&5^~K4-utv-Gm?bHrF=(Ly(exsirehJuW} z4kvW1R2Etk2e*Z}kk=$k06XeABpb(F2cpcWD`i13l%VpLMFBWY#~eToM_H4e3^UF| zOq^l&5Hj4-Z&`e-1T0M1C$yOfnaUA3HKZIH9xgw$NNvjq4Yh8B&n!g`;A`S(?A(MR zlaLvbNZd+bq-#D>yEM!0#wwN@EMMbBu9-HEV3$#FgjR28rGrqBM&TAeb>&-ARQ~?1rxwD*bM2aHC1}%S z9`!oP_z-m|MH_un{$)*g(o}36WZ(5A(b7wW|J>u{$r;}C%^Lsno0c}s4(7k zOw<{&j#Dolp@2RxjIR$Yeg=AGPml`BRZ-mOLn}Ljej}OEa=G~*@Kkw z_GYiHA{SvgNmN<_H>1@=EIS0a!=4S}pCN(S_*UW`9$tY$bE3xMsQVHZA|-l63-*5vX!i3I!e^N$pm;~JKhjpZKOHk&FB)d%T9nxZfWj$Mn*p5o?(EfC>nZdT?z zDjCw?;QnNw&PA%NpJwa}FG2V?q!8Qz>xoK!<(H2#C}bnay29nX=R=x#l|hHhQV4MlEV)b3B#8=y0njG0Nsy5m*Wj(vK4XsuB0u_-*MW@ zP$EB@c^gJo@W_RdG;R5!!*<#f%ENaU{eUJh= zUS8~VrV#wJrZZ9~Ckzv?EL_*M5!}4}GoU&>9D|-xMyzySx3XYk7UsrXe_z*6!aFOj zX-u{jx-Hbv*}4hneU)3pd^|4_0@a}nm6DMrx}KyKr4)HdA5va|m*L*h4n!Vuo?`8t zxX^kvR#=vcUSYoKspCv{GbWWQ&E zvQ*}KX4X#IvROs%#d9=2U%02SmrC8N%Ywyvnb>X_82YUYrb#Gb17dguj|)zxQJkX z*hm|T&IuOb0w^W>L|YrDZ0)@QtNqHNt_`Jswvy&sQDx9-RCG8-FRY9oclca?rN};~ z-7*evM*q%jR`ukN5h_M|#2MTl$}D@AN#v=z<1Rq_#Rh@z%JrQJ8v~Iaa#Rcizrc_Y`Fz4~PoiPL?-|j$z2Zo!ARN9ZVGVTQr*h=K zS&W=D4-jG8>_^Dz9J}{Os`sPlZ|R29lqkTDW8G<{WjJ+C9O`5+vLq>DW<@Iaz_yY- zNQKC>&lyY(PC--@l`*y`>qL?Ia09<}Eo7_|$a1tzOW+my2}{(=-V@~aX?sDO&dp=+ zTp_)SSSx(BPfG&ket_o=5xauSpZy{i^L70G%Z>7zH;Hh%rj3Suc3#+zUmgdF9c8v?6_h+h=&;Tm-YR=}w|i-jy5-6-H=u`5A%08R-a z%o!PT*w)ODm8L9y4%Qy5tS?`WOJ6}7egb#jdh31gQWi7H+NYfDXl`Gz*tOa~PU;S` z22^PL3wh3DK6cz)o^SZ1d`>ZY2;-BnDY1}gNl6HZ;OmL!fc_QQtDi`d!mV3aDN@i^rwG6V{n&NRy(RO2| zhWP=ds7h26?GSW~_P?1=AcC)>)ZVt86tQ5oS;6Dwr(7u)iy@_xZwo#)>&a{&&<>S8 zx$4Ql8r^fdOE4i4y-CDdGOq1MCXW6tp|_@b1o|X8Bnd>}_)xh_VVQ8X5xF|+RpT#^ zs2NV>vd3KBI$0S1e#C~xX8(i%AE1Q_y|*gF!szfV^Tjv^CAje>hhu9rY5BHpYrWo) zEg5X|XA899{Ih;nS5Di<2UO7aP8K%VfzQzg7nD?lwI?`?*DzKUh65aSP!d1Ri^`-_ zNh5l^z*)ptym=IGsP6Y;qfxn$lT>QNT{6(kSI@2N(eTy`7arKbk$T{oa28e##S552 z0P(=@1lisiXRj`#_(`!>FkAo~217Gnss^N=4^u5Q45P$V>d~YWv%h45@xvj6rVR9f zh3$oqf4!h&v`%}zd1{++*!fB8d@a!@R0YhR?$0;KoyUZMsz8zKsI8|np!>OXUo#F-GX4a+=q=E&nl;5dd5*sHXcdnS=^dCtk1soPiQ^^g35s1pg` zqcXqLZniRB^VI~Y=r(FvUS82>{Lz%fnd0X=p%$oGUlwRAIxb6@!J|^rujs#?gx~m! z8K3&@36&?mw1x76; ztJyF*XJs%b^=a?x=}=|M4^0K)0=H=0DrYZxrcsRWC};tjc8-(K+0leua;%LIU;kbx z8`#rm){i13ngh?uIJU8%-B04Aa9ve!>ClqD)j-vuH_`l`TbW_jZa8fy#f4MmoT=g) z56s8$6woCH0M6xndMyL=BSg)YyW7YaHI$Q)7 zm3#`6;OpzsINeUQ5!s2!W`7+#z0J`S^xe1f6(6BCh}>F>k}H`|uslGhg%z+#yi&*t zih}#J&YPY3;?>wGQXC*vv=7;sK3Z)fmjez`bE(_?l<5b{Medu3&Icj>@}f*0WGawZ z(uw>K*1SUBUnqnIr}3kijYktk*j`knuLB}uXMvP?wv<Sa+!#E*wZ3#hS9Ch0IpU=rM962I}KB!R_*K;QCP*|*e`O1YHTW>`L0u(<#=4 z)<7qL6N|+@%oqnf*2%P-Tmcvj@L}?k5JeTla|bD@444`E#VB0|sW$mn`u5X~F#DBT zx%r}M4mX8ugdp24%LM9BqC1M|g(c^G8 z<#x2W!Ni?skA?ih;5d_O|A6#lKSu&`0Rbtcpo-Cw`tIb=g8gneadyYBi5$_PefAdK;szIKd;}K_RB@R23Q`DO1WA=ra)SfSK&Dt~Mhp}1#c+;&Is{4+KgFt!7 z^zF@3tT~yPUWV(X9daxa(W)}V(umC3vCA>DM()P_tK51Ay+$o!u-$gkqlQhh$iBcv zZeUO5C%jdGU_vAgbJv5qLn?LK5kf}@&*^;*L8c=2!@Kr1i>|mol%M@o7e21}Be?=Vp_u)bBU2KC%cRQ!j(&p>p z-5QFqWgG9XV>LZKKMPg8cf+HuESY;6vZF+;Rv1D3(a#TYj;Mrv1YFPF(CwruDtVvP zIB@Qy_JZrK`s9fd9?dW73K;qn!p0M4fccJIfgzw%!(dcDJ^kR~5+yT+h&UkUAs11{ zPDTr2_f8$$h&9gRKC)ovQ&?iz@)U8 z?<|E?bsURg6CaDcy}UZNWgy>nY-3y%T@Y4tEmSR^5xX0yIC7R0?bo48SCB}I{!bc5 zmGW5|W@|uKKl)h*Y(%EZk~*zZ`g3!2_=owMCO&eBUV#)$sy@T?*Y!p(e_l*}TSp;{{D`c)#a&?+Kc4I}ZJ>|^`a3MZH`h7v+H6I-{ zINlD#mmYuXS&@;$O>CPiKz#r7^T8jrWhhfc0tN>FnT$GJoLuk|jSK&lpyPKi8I|+a zM!)4SpPw2_2cKy;t+MdkPNwv4nB@k7C_NXp4-mU?tFe3kLmFQ_bBmGF5G)ttL$4^5DHQ!EswWE4Uz+R zjXSO9OP?-Xe|Np55O>OR1fbFW&|YuNXRT1_j{|E=%%QlgfKV(E9{6S6#iTG#J)U0K z;4AphMu3=y_BJEVG0dkD!HN9@{&`$IeX@)w4s)@fK(kDmLH~Q;hnKoAm55n0%H?nu z&9;$Joz;*C!{;O#{QQb6x}xQyNNtaHPyYg;Vda|oA59W4{5qJQX`_|}Qa$L+erd(> z%)DHOln!)|v(g|Wd@)I&Kvqy$1gHMhLB`J(?a8it3D?9Ex{5U{t)OOVh-y&|iChb5tL!HB9~%!AH4txv6?Za^kbkav(mJW>drm z5D3@JE)wBW8RGPa9e%)H4ovYWmH zxI`_DDQHg8Uc^KnqivQLbO$$S@~3<8QFYN=1V*rX+zW3v#Rn=LZbEpqqH2n#rDbN7 zcvzW!?C0%JsnxLAE;E3Son*EKf{(YD<9JRPX3t-&K%jTODE+s4->|4;eF90*rPEbFotAjtmo+cND&^Ks)!>heUk&@?pRb)SVZ#7iRSLTJsX8uU4{=Y@@ZRhWv$G$U>QF_iDE+3PmEacIA#V zQCi3^$@Nw_R;e|~KIS^j;Tpj3gP5e(ac}yaPLG$D^bOE)Wv1d+Xb>_5(HCT>gzBpW zxPLkug?h+Xn*dBG0UQ=MnzQLW9|bpfEv!sjNxv6eLIyd`VCdyF;iy`Eb&V8zyku*4 zh)~#&#rpVJ_t9V+yqEFHI+9b8gyi(pr**M+-JIbO^Hi*mfRRMq2kR9NUjAGujJKP> ze3)aPev+p8?e0?u@=T2T8omD0jU}t2A9Red&Kj6O;P>po_A=|~m#JEYy_lH0O4o(+ zhWhob_1<~H?{Lmv2k8SOPecw92C~6T6)SRr!4Djh5xo}&ye@vtu-?&c^}yTD3t~P8 z71%R|j*b91U|HM?<>R0fN0xs^xb#jwgGH6}<%ZzR+JpHS&|5ex{cOk9!@Q{VjZFlo z$ZQnd<;-33PTu$lLi$=v48X@@pZQk>ZTGt!+0N z$~R69gHYcqGkl263sRXNKX6G_%hp0Wm8Az4$?6pcBhPtI)8oqv1ed$A<`Gzb2y24A zd*j)?8ZuWreU)@^@O0#N_^|iOP5mfrH||#J_t>EcG;^h|rfS^ygw5D%5v^5hhOtY^k;-ppM6A|nO4 z8Gty9gDYif+82Q5WpC;5p(6ESRseT;S%hzDX?V)E;uSI)FLIyBG67Z_-whCP#qbSU z`il{pD|^#TJk>pOI+I|^wW?dXeHUAP3j zm)(>5S)qVYiJ((i9TWbseR2^Jc%O4JB>RU!H8-%hWK4l%ISr?$juo5m0B@m87g(0W zp^C2@gSKzU1&CqGXFe(e*;V@PTw^)9U#Qn1KV_YEt<^3*#JSehD_|Q?AP&^X~Tu6N47_44Yv!>JMGq{i&Ze#i1`H`)nAe(U&H1s2|#gZz}xOXs6YM$hVeW+=Ec zFFVgplF>rOCEnV8*|i$}NX>~_)=k;84bKH!<(gD+$2+>2{q-PDeEo#BJ#LW;z&d>K zyARtxYRvsuUQySNv;|Ltft;O7rdE1ulEOpNG2@Ha^t~z|#a-ScFMmXnOrIZ3z<piEB*CG9*ZUh&5rW%ia!N8g8uRsF_s2WV(m{s9K>JVc;-Vr?2pLjRL%db{vNeoWRYlyL` z1@1Q+<&BET2(1#s+rQ?Zjm~0%LtJo+Zb``R%Evl;c$uPnG$38Oe_1}n=yLpwuD&jY z3^4Um^SoY+6n+tuLSpZ|;VlbsWX?9ybw7yiU$8xgboNF3fbfKP2*j<;s5Z$_=##YZdg}+C=qPYt1r7=W1oof5GZcB!{8EDB)@;?2$!Tid=TrB8`UwF8!cS>IogwoJN&!_QU=v+H~FOb}-8Iu;*Geb%|?$1jw z-A~H~Xbi!Lp=uP$)nAp0?S%Hzsp!Le-Pe|lx+PM(FukYsHKwv}Qe*aQhyRrZHJguZ zM(8DiJMZa6qIR3!Z}Xd)d`ol@zDc?PvD-^?b1Dx86QY$uHH|!%5VMklep2|hBW-wF zbU_rw7;~&J3u3yyo*j*S?*cUY^+C!1!cqeb|A!2|+c1{ex6&4ELNhF|z58rf2>OX3 z2b~MHfrz&u2pY418Xw4Sc!W`xrim*;uaTL?a`bGNgEsRB=_`%sAt*(V0;7%X-4EXea`=)CpL5 zBtIY^HS$3F6?gB~nnnDi|5}kLhsmk~iKYR6^bs2CPV}$>Su=!Vr++RM*C+bW@RZ$$LRc$Frf4#-e?qoHe#?ZrrK(QJpHLy20qJ* zN_pOM9`!FfHuBp*Z3UWatVz@F2SU#4`pYG{(dJc9-wn6Su$5tVU)P7CpZq;qs<`bOtDB)J!P8@2k zju|66lY_7*v^9ZLDt`mMyE}hsGV5 zt^u@c?_d$J3lmAs?=P3s!8T0w5WFcIpDZ#6UOuDY6(j&d4;|4jsQH!@CQrF?}NhG(4JmfyO~ z)xnbSijkeoUi1k!)UMk{ZTO4-q~Q9-?2j+kJ!ApWC{Y=F=R+SUgq&ph4}%oQK9nBYmOPzgX|Te8K3B1cQF1;7IZ*E|M&j1>;NO*ckQ(prN0@wry_b1wC9g>tnigtlo2x*srv~?a| z;JDF7!d?SAKP@LU_$}lK2f)Jz)^svPLDwM>knCGGfhvNqCkQvjiUd?E{l=Jpgd7#W@E z8q>^F!1W=DM8oXq3|aU8 ze>~7u<3~v~Wd6TXr(+vRG`a8nEagsmbaELd7qW~vo_ zl45r#^4QsId~~bOTz>cu5{3k4b+751MZzTf`&pq#m%AAW8Bc#IY6hZ|tAK+m`m{GUFS&$M?T`T;>H^{+r3Woho(|;hzz4cd|onVb%JYU5}50o&5 zxv`IU{5PCi1`40FXSft9#DPupulf%PjOfeQU#YZ)kP8Qea|Gg?7fui@*U7&vT2BW$ zNKUG79b-0K(%vr7GqWWf9AuX{=#A&hWi)&f{a|MbpPQ){d4&?mh-3LB2O`OuTde2i zXZuBOcIN?8)-*c=rv2SG-YKc@imM&^bSo0=Dk=NY1Y@Owy36VwOQbt=-}0Hsz2BV! za>FpPpmkg|4e-^4sDw}Nj_kYuE8*4=n35Z$apAz@HWI;SO)?kcXd`oS!egREcMprU zm6a0oK=dY=*nvYM-G@czKDJdP@VqPaMD`;X<;;A_K$y|nLN5_+b55Llk}*C_BM_-M zfn!foQ&KeMP8ESa69<`GrzJ0OT~Ji?!?(w#t?->_!&+0+eZTGf1o8vw>-9FeEBWw4 z)QTclOUuVELBI*#&`&*Zb8>R0_CB5dSNbmK)*X46n%7KY0hpS1S)-#<5uToe*m_Qg zkIcR1^AG%WhCL2+v4n5zIV?cvBgIptfi#%-ZU_MH@@oqPsSYDDeZw-C3&!D6<&rnc zlS&aqv7kzF^U*hib!CHCQ6&Gf1{IwwwlNbIOo!BPCFOJr{ zE!^-Mmt-{OJ{q=EL~V#QL0+~)-U_3XhJJ03 z>DOTn8;(T!;*a4TPTN4Otzygr;b0zp8)A< zLB_i>(s_>>DlC(;&r*jNY$Zw^THhnu844souu_4mK=gFSL3W0^=QA;OkFRvlc`AS2 z2^V9xkLqcFx!!1$4?=DU(i==`KO*51xHOpr+o(rN$&cBCGvXY1A-wMX zx<$}@xmZ#lMSqUb{v5$=C3&=)vy=1I9kIlKH4$e{`gMy2;^jHb2kIOnwaKto?Pg)b z@1b3Y;Y%XIlo(sRFq*TD*qw{59(DUg+l0@DIYbMm5=sAZGh9bBC3I#$`tsa*1ykK{ z)DdYaG3B?^Eft?0rG^#d_#sLl1}4VAHK-G!;ETMIWh1wsB?NGAa#X zN4F^=>IxvXt$iBP5JU0~Rb3=ItcmhuTUp|jh84>) zou$K|NOs?)CkatkM&DLew8l5+NSU(BjtOI=&gil%4F^Li_jMR?U2u_7cd&{N=>>Tk z>e#8k^9uj>vqSk1AFUJme7XVQ?LCiqh+82YVxxrop;SXzAFq0E!bYRIErFn$6}RB_ zX_o`$qhIJK4hYec06Z4z`4+N%XWFbeB+8`MG^g)=9)8)44VVe5Vf$6_jQvn>Q=67# z#JQg@#U)u#f7iY62q(CFvPF9kKrnV7#tXDRk$f=ke@?Zf$osI!W|xj#A#}`r5CAiZ zz#-zSQ<>e6HKF5lw%C89IeqG^()AeGV>G2FG6cH4v#f^zN)T7uX*P~%70HU8T9p9d zQ@$f}KWZ_v*KemMeM z=_cv851_U$2xF3w8T40Y;CNzVic=6>Gu?MDcP|;b7uAGnp#TWRUp;$z#B`4juj#2f>ZI2<%3@@Fb5jC zqDOIODw`tQTh%%u6?Ku93O2~-RO5Sr~5oG4+XT8ichl*Q|=LDQ`V3_}6Hr3b% z#Ba4D;@BDKh2;v&+z0Kc!z?KBMMlA$sczc-NOk)=SgDA9D}48Zc5HP>@qxtl`dGaXQ1#P3ctCnnwx~i^R}0D_V`Lyh&>3Rb!93>pgp;vbDEtV+ z#Yd$F^*Tx{Hx;dBz3=cqla~9nGSy%SmkSGlRmsz!Rkx6#5WvUqeXd|4p zYS^k#lHWm%fDsxTiJl{}^h-x9kBFc(`Qza&{%1Nx53O56Xp_Iw&JmUa+0V~b!owSCQ- z_5%R{*=L6VNxl#6hDf&O+0wCVO9h`K7)>m7l6k`LqQ#>*Gtn1kchqoHcF_wAAMpBrsN#GO|R75m54?uloLW!)s`TE zO69mi{S}H|kaS^k+$I_d(f%y~#e@T@MS%CTz~rM1$lb_YhrLxkbk6hfKX}5#S@j6+Xk{4N~LX?h?#Qsp`$52DG9Q z{6R}UH?q5YhBfgI99r32q-k=9y{hmjyAJ0e0Z6$%247gOqM|}i5z;C!WH3(1!LLW15(p#)2ct$i5Z=0rM7TewhV=HI$ z{iRa36N>pX%2Vt71PAtcP2Tp zG_8h6^p5T_eF9{BtNBlE=am*R;{JubhN{0j{pv5hv(q(n=gO5SY2OYkh>)$Qq1lO^ zKdi>D4`5|W9qx8KoHA+Ea@Q%qj(MD3%3HD)M$zcWH@2}>UkFqsBWBg4aPsGf z7r$BbsDleaNZiiO5f}>Aa~#nR&#a` zstb%s{*7=@2ZQqFw`J0=Zh?LN3N>0N;b^uzz4rTt9yQw9h(KY%9`Yilkri{IBn=T_ zC~)ZvpQIo^I#y)z^OH2Z`^u41xi>!6Z`-jeQ|uXxSQu4cuen#rxP1PMwp~w$ zbFa!myma7$wqbZ{Bg1lsVC_`z&HoeP10DQ0k8{_`gSa#Myg|jC$!=cghI8Ch?_~+l z$l@p_c6aj(ukWF2N*W7$&Z_bkKkR)I@*&;tThF5%(E_lGk5x8L%iX(imOMQ5iuHmz z5&S0-vV1Y?)#DF)AY^F9p82)7Hv`u~e27<7n#$2JqA#7@7@_bAV5+D~B)XQ0Ri<9@ zj#cjh{~9UYoPCz5IeS;le5@OCj_voY?VjM~KBra3)p6GJ4ROrsKY*aJn+pim_SE$J zH?EZc)P{L|qP^_SVnF*c!`HkTALl$}G6FiNnc z+qT_*+qP}nwr$(CZQHhO+qUP%M7+gByv@|E7P-n=WYjtNovc=m&m}ahqbY?;>#1<3o9nd{wz@lsN!6^Y?>%-6Ivx#eB5y8I2;2a5Zpl%ZN zGJ=e26gj9WHj7!(Gln~2HfG@BZ`m5Uxk-Q;@nXQ{S|ebCVyzwLDV0(6RJC;rC7)e{ z_-F+M(K3=_P(;fskhKS8=3%dBLn1qeUd)mA1*;;t_wO z?m54-R2+t)iXPSR3EZbmHjMs;rtzJnW}*LWc6sZrI$54ecz53g5uTna%NZ3BfNo12 z4m{#FT?)Q-rj+}vV(hA`r*^FxCd2-7sGywLB3ST&`m_A6RVzQqMGW6PRrLlU%)-BF zY*M$(_W($9vw#Yd5T>{sEXiG-H9}r4IFsY}#u>^$BSoZTk4iZ@eEAX zZ}$LE1BQy_G+VLZz}j!FR6uQ@gle2qEJ8j6+snn96F%2n?a-7l4A*oSH0}5?=cgQW z6q*)}tu0Mpc#nTs8m3~uITy?XqWH$Gv_I5GaDBg0d<68a?2U5ZCq~DGRq!gsNQ}87A#(#j{UY>}zvG;5C$i@;}+f$KJ5}(Tx58Q8Q2Ncgz|9AggpI>AYMgkTNL=(`8FDc~T3(b#ZURQQ( z2wMyufAIr)Tz!3A@$z!byUZ_Tq$Kt4BP=REr6sDSq9NiZ4!hd=aDIcDBfr$-B9TPCwzY@Si!~j&pzdW$IF`JNM zMoeD>+{%h->+guLyu6rN5)|PuO#ulEpic=)AydO6lk2>=lt*ZgZ}%7 zmZo~Ru9%ceTJEb141lK}(cH@HlkDctp6Ej#>^*BUtSX@56 zBq-;K&+}=|1pB`(W^8V3{ZJ7i=o?$YeGl#4&Shk1{*ok}rXivuswx+zeqwM-Sz1)Z z-KsCHb8Y>Z{E*@G#iM}x$Hap2&&`75e_<#ZNC^p0K}W%_y4L$`k{N$4kaO_& zd|{HJB9m(SOIsgbUYtLd+k?fewn(9ovBB{_6#O&$CJ6k|GKFadp9l131;}p-fV{~w z_M4f+XZXQ?5JTqPuCA#D6!koH<%d@y+8=|i&dSLpLeRIn0(iFnDm&~$q~@XOpI`3( zHJavA1%0hMKTH)>1$gy~;7kA3dhrA1e_hK=^t&!ENGa)n?nf{Ok)kp(`D1`H{`<4u z_&Y{&pl3^4XaY$5krVq{lb#z~-ag3-{WHo3`W{M_9-Ukjocs23E_Ed=o#hweQ1Sv! z@@sj~b9C_PiR(CPV`c^S#hK6}JmIS{{$*&we~Z1yvx4TAnG^rx>x^??rf&k-+yKPb z_*Det%e?3F=HvVeqw!bORaF;I&v^6$Kc%BGkOHO>Qj#(P0A_;bpIcR(15Ld(g2G78 z0JMF^KeC2!{ZMP z#P(M`w;P7bNBxC2Gy$29{EJBkXh!lYf|uI(`^U-&P_w;vKBRbI_naW`!WaHS)V1q3 zFP3KhLS4;AdOO$rJ$5Qo`N#G-ZhVhF{EWD@Z$$7HDFUDi~=a0WU^9RV+uJsLj!I!T2 z3+zkZ^4Zl0uSGTGcc1^aZ}HRiSri{9nxXkqr2GkA%KBf0w9S7N>6HLOz0`dLn4<^FH__o!-H}$!8w$?}KWW_TmqUn*Bh`-XYE&(ZBC5(!QLY{#JD9j9)%*Jty_RfFOpBoO||_W z#}oc}S&bQC484D)Rk;Jr9G9qmym%-|XS{i3VS~Jkcpk zpPPc`$B273-d^&5z+z>NeRZc#Mf?7zA)`s!>&x6i{-%-tZv@hEWG;Wa3>;Mqx zrtl{UeVQm3#rdi)nrALb>Y^M78xe^YJ&AYpe&8Bkz*6xvo5OQR6fD|O^!3U2G&B2t zH%7RH2>|}$DL=3~EMXJa2K#M}j@})Sy3kRWql6;S1$5I-ecCk}y;Us4MZae7&B2<3 z$%PyISj90sb(`2Acq@sy8Q?Xk^ z`lDPJm@-MmW{q82!c-VN^;)i!>t4yTa69P?`eL1FmqPufw(=NKa@Shtz6?~B@nJuV zxVO+2GSQp>$pRD=>y+LOH6l(kklz;C?WU9J#W`iy0WP^xKhNl_lb!0AEH*Lzi}p!K z&hRMxVi9<%c^@O@$wR7M8KSrf`bQRae<;#DTBn;iFnEyO>Hs#slw!$1Om8iv*2t6X9f)>%vA@)*XRwRT9{kPr61y=(DG^k)-tMhz*pRapiBY#-ORxr;-XYw8wM( z(|CVYzgfT#M;%VYi5Zk5i8fL0PSKWE^^i1TLe}TWO_IVFKgK-!toV?xaBd8`OUEM% z|6n0i3oVSK^3gV2dA9xEP+evKh-&7pel{m{tK+us)I-iR$T5Juft#bCHy%0q5J}4G z69ww^0-%?+>~n2o)e#}hCvx0g#C)XIZ6vV`#`oj7F0DAUh|ru}4y(dhIgN3wQvBm# zI^EFf#mtJom76L)DmdH54EtYXq}+*Vbh06Sk4Q9#JGvnRDQEo5Pl^;z%;Z< z<1Gj7fj=9rkY_riDZIpH6H|98NteQtdG7Zj6&%6TLhYB&^D||uQ0>>5+wl?Mq#g$N z^z6J@)!~I$81(T!Gcf87NXHs7h6VWvg`{SnEZj4stJBCECE!@;3_CmW-=@7YB%7)! z!-oY--mfLj{X)$Fz6J**)OO-8Y8RdTJwJ9&1VarJzgen&n zRhUyXc-)0t9p1osiG^I$`JNdW6kWha#iwNlpdARhO8W7wP|T83A`0(UFW$M)a9^}R zcwQ>v_e*oCdD=~%*wZH7Pm)nM8>i6o*v}9gy?b23hM!yHMBMmD%+6)z=L16o>mD2!48F8Z-vwU)|z9+ny`=NE|#~)ZxuxHT(}D!BvX-R%|7-k}&sGod5RB zsjMhy#xq~U?-xe%^4qbzFq>uWnoQS%O{n2 zc9yD{<+glB@idPUUY~Pe=WQE=Ci+zH-U77k$X-hKw2~AeGw7XX>4KE>QyUAA*~dq) z)47gxCpleZhZRPUUqVBa`l22wUT8BBHyoi;frHlsw3zPc9$wvhr-hD3|zZP}H#6TPr4HE>fD4?l`pNyWh=gigdR0#J|vsw*D0H7cMI~S2Ue*p(zL@fr+JyFcYrs$;c5} zqtUM?{70KHE8Lk~Y(GpksiwLp3BNHTwtVp5cW9NYQ5|*)e#QFLUUTp(bP+8T+nU~( zb#{RT^s;d2Fd$2!g6mkEBRMefRAHcO29$9se_iZ*=yS`&A@o4e(Z#4 zyVRe?TL9>p8dbv*r=)M}7bC6t)CQ#y^k%#3_D-R2ugaatS7`lfYFl*5-TG0QaL=f~ z=^ZP?*GbzqWj7 zt-k4|_NUev-$c&Y?cgSl*>+!L1_Usk5*on#H}U@*(_)MHRdd~rd9!eqcZXXY)%R1{ zPn}&!C&w;To6;h`t`NU1mNSn=6w)ywnT@~T8Q>;}AsvVrm6g(BO@{-DnaoR?rN0D~ z&XCsK`=Tl?2uAzh?5Z=!MMjGYInGm0DdwK&?+iT=_2v510PqE|nl%)CUyFgUA30 zPwWqLV4$2qe1yHjt(ASklRUaP+67Jp!M2pumpf`Z!StY z**kibin-s7<~5K2vOrme`JdpU7v;?i2A2!ue9Jj z*aQ%+|IWSLkiz!0h@;?=JByD!^XfivA#NpwVbR5-mXRqdGa=RHFL(OF#?Gvq>r6B( z-@Bk4VBpFyQ*_&??GJXd~=fO&(wSycl=5Yrge3$E!0YI}y2Y>PR8$rLWszKpe+=kj_Qe z%(rJ6QpIYP^(v)jda@`asz84CogIM_;~vF8xNhL&93%~<1YL%3l)rEG+EE3WI({IO z{%K4p6p%1OkDTqqsmYC4TPXc4WfKu{?n7lkn$gAI#i&4riZqqad&0o-k8usTyV;@u z`cc#f*FBt5;iGlQOuWOh>d+_W#heWE2kfj(V?x4{OZz$dnr@zC4*5xWATTQt!5Du? z21b*E$63FH)wk$}{?gQ?iL&(;eIMBMvYeAWiXAt%bG4(@6!K^+ZG-8T5@>7j75aDF>={{lOP6BwNsZLm0 z@h%%d4o#ct=cG-#rxMQLNrZ9L?MkH7S{1}cBfL|i6T&kb#^&cb+F=GSaELFjSU=nGlyUT`{t8mL|-b&{>P3ma{dRTkj3( zmVrlPk20pm61PScD5!SG9tnYk=4)}x14@Wx>m)LF%It9DY8D1g!vCqyOqgVdSIXP1vb62x zyXB?BMsa?`3H8{P$dWus`vu}z72J5%p}sv3w1y3}(&q!bfE|hP-d`4J10vb-lK4Y z{8OB+Jfts=bJ0tUVr1n#Ery7?Qx|XrIvwvCi6F`uCr7Pq_fH|ia#^8;1Eb3mL3}F5 zOvC6gh=9PlX!u{HcqGZUaH{nmv>L-KnGo8+X#bU`~utsSeL-jL4!j!L7+BVsXB~jxRE6fb+21jG0+ZSStQ%yX>o<(Yh$4egMEFt<*#K^bpOIqQU z1?Za>01!DDLm_&nHUV6x7+o}d>B{3@xA5nf>p1ac(5wPLi9oYxd*XN|=#g0va=XuaznwKaQ+T1K<4zfjtR?VK2c}_b9h3@3y zQz9VGX`^(r4x~;SG`#ABv{BM;7445%QNFxSAg27*fA7^7Vm>BRR=LY{hQ1Z!Ne^~B zW+J~wk9Nchyw?2pb11$vA9_OJu^VFP!TVIe`MAc(1k9#8)T zUz)J3#%~yr*N>T48?AV9RO_S7&E0WYpjhISvJ9c*x4H5w>7vrdz8z&V*@%eu>b%no z>uek30}>cvmZn6m@>lIom`LESWB_$XML3IuO@z$^o5!t2l;C)mf>hz+V(j^m=4LWd z@XZejhxbKsEb30gIXb-by)5DR1G(`kk}vU|VW@=7a4=nOQ_ z-)9~xGJHV&j+OMJel(P&r`TthZyY=bK8xD5H>_V_^P)wbl0^@jxxbhVZ&a7d9}eur zH$~84=$fMYJgg7SGwW;j3{!VG8&Pm~*qjczg(l(Smnr8W6g_ocR`E|CS)QmHzNDXA zHs1zqH{a9I(|;CIU28R1gqwhmNfiG^AaUtFBn_cq+;Q5fLN0Ok)XOo43nW&)-V;D`Nit|@?@ zel;+-yUwUC>Ml9c!cIpyIzr%N;_E9E1DlAx3;z+8$QI03^_3?fvCl?^g9b^L$ch21 z@PteW{>^`+8I<|c zV&sl7}u^i(^k0n@}ziGLEFKpcP)u1;=V8jVG?!xLgOPf!2AGr;S@!| z$5_wVvH7$^>UkSF>pe{-YCP8O524~VT!n>-x8m4}0^U4UOm(pb5DYjJfr0~aZF|^`r->hDt&Cws zY?ong<;rP=t%8;_wViPj!8OnuBTjG|e><^TI)0yP2E}7NtF?8kE$3K*-1_3hZFPo| z>TX^=Afe5>GA)O)XpmN2y0$o55X46TcG1A}aV^-mkjNhHz3V6>;Lb-?Kis>D)K)W@ z4*Wg|W?E#^>LrmYoD7$zDdZVh+a(E9yU6tWi1*>{eqo3f>CT6qor4Iq!3++{wey%| z7wDfRaur04KVy?pFGgTRM6#OXjFZ&)7lEin=y~)j$*ws3r^l6fp8%COAj8pIO&i9J zERt3~_Y=fG-8^dz6yP^o+9&z%waA5qVpF^Qv3TKV5vA(yQrY!-Mr5A=e9IL-WAGGT z&#Y#2FfY-F-E1Q${3I4-m$*2*f-aahREtG2o%=k!{yMKB;` z;#)^k+#SNCOD(Q1#LnnmpDLG}^(Baf6HGfDi$e|htLqe_fE!7n9*ke93VC#ml9uq+ zRG9V4;+~Ux9qfP8kEYjG!S6>Pry|s1l$s>!gw#Yd=LD>dYb+Z&5H_vKjE|ol&miK6 z)NFmm{>=T<@Ji_R+<&&48~p)hi*8+e3AT9i4OKN}0%yT37^^9q)G*;X2MSm^8QK!5 z<1a&hlktoP$imS6>!c2}&5<@6`+&Mg6qfA#g94v z`pwY5LJ8=7A;E9bRGj#*wC#0y?$cF;Oq?@VRE1@HxVTD8`6v^a^Hi*2Hykp(g>YC> zh(hXKk)2Y;k7GoW#ONv`8Xb=;``rglhcnPM;%!Rq`n5TTd1n=}hX& z)h@E@b#+YCa${i1%n^;@*XN3xnJlzf%*pSloF)2!MeD_{{g*WR&WGtOPV+c=Zv~1h zjN0*tb5p06(@Fq~zr&?u!owJ!uwA)B>A6VzX%mIXv;Cx363M)NpRQ0W7wq?1%QJSM z-Zi|Ir4f~R!BrD7RspHjLA9IOv5D*4PdDK*F~cTaR1``w%fQA8$P4${AFMKdDGRtS z9I#hy(9tv^=I0Y!85y;EvGGpLYGM#~sv}5<@PcLsNwCkaig{SS=0G%4iC;E}e>8?- zQN|6u1i5^m6XR3xJ=^}^>m+6T>3D%H!!g=qQX+e-hE3<)~NLfEKf*XFkMj79=98L=7=SC2Q&jHUleY z5#&h5Fh;jQSQqr5eNL~hjnIO;9QWAm>ZU$4+CjE9x_y-b$!cEDaw|#>7vQr&$L>AU3k#S~H`6^A1 zE7qXS`_&>t8nrwLZR_j$(bwIiYnK^UGs;Us`Y=s4W8+r!*G{<{Ms_75!zEnnaG^bH zD*}u*1NR0L>PXFVFMzJb#~=p)uZXQ7j6~4O7>!=4ybb5fY^NK?-Q$>Gj5z4;_3=E@ zI3|ksQ;;V-w{FP0#z7?ym+Y^tK-Z>nX@k_t{9GmHNt>iMB$hIHr*o~LQO}tWZ}Wmr z%X(5X*lw67jvtP2yML;|e8uQ8p0n`W?DIq02`bOSCh7IVu?y3XchDhPB z7O(u<4nLM9gO*9Yh$BkfJ4@rX@x-FarxoApWmjE=ELrJ>Z4{kPQ&^y$LWq6vA9KqD z7GQ-wu&6_&F^9oK1`~N6SrF_gknGcTOYGtpVkQdzIlhA~84=h~63opZ^`@SX!(61ZAfPy{8t@CxC#|<0 zDwD{S_vqsSV-;exUf2F|$EwlEDM-N((3j=s2@>2a%=%ZVOYW=-#ED{dtn_?HQ+in; zVSE`}_uHZ7J6vKeg^&ce%;hN7!}aV2n?YQcd{TZX+&K(nfG!%Amh%peQP5y2mj!R3-s%W!@Ju^ zeiY!SBqGnR`kI?KyM6xSKUwDb%b5r1l1h*dv$9ejNKpHmnBO}!tC`BvDT&7#R_HhQ zRn%4CN^AYLA?%;G$f6gKvKg%VTi#U-!T3Q5G|BzkY4=SffR6Om&{hAa_V5M;OxUV! zNCX&(UoG=pQr5t7?TmehOxS#XA2)@l@wfexjvoW1qDUelj_27yCfhFn29_s_F*&q> zZOwS?!9Z%f+1`lb=@o_G(h8zEq(nJspN(M)J8McBx|gP9+mTByj~Nmxq^83QEKq^+ z7{U_qW+LI*d00Cxt*6hHRD5{x9yDkRVs=;tYhCg=!%S_^N16=e&hwF^MTPO4x zXPhMP$jDt`+v|u=P*tkR>)Y`9le`gNii6{$F(Ud5I-3BXN>RJT?iXkva71V!cWoTK|!E^^*p1=JNs;jS=IZS^;WdWj6$V{)d>d(HMe|YX7gB3_*>ztL@A-< zC3PoP1#D)?LSWG9YB!JTI&eY9YeI%(i+#^WgeljO9izMLARlk@LtCiXny|hVn1Dz3 zRD;w)Z5>1TZn1JdyqCALIxPfaPy$FJV0fsOY0Mjjhjl5Db&`}xBR33IQD;K3a_S;y z@O1*Z+GC}(nPpwgPPt%eGAj!{CEqj%?^e+v10fwzz^?wK+_ekNOxi=0WTKhl8o1+c zma7t|6NM%tBZ`Y=aJu91Ojv7zp_A{$=JR)w825w})o{wUD?#ZC&7|zRp$6N1Y*=0$-@?ZAb#51OygMpyVG?1( z%xI7I$%1k(rwF);uI={jS(saVZB1Y!w-_kXlw>#k^%+wm#@%grz-S)Q%eUTHgv+hi zVw=xFA)nz!$j!fayZn}2$TLcm25hnj3C(XRoZ$Jkd~2BWDc2?lg>go#3p3F!KXAiT zx{kMR8S%Dixpb(jiL?*~x8H`hJqr)}=myiwZq9j=gf+PDlaQo^(;ZDYN-%wy(_{TJ z)gllL3Ec_O$`p6@OyX&F8s<&I_|%P1&njuPLfOQ(x&6wDcC!Aal5qc_bMb4iGx#L- z1QzjH(9#8_TzX9iS=MJO%GxG?ttxl%z`MfVXzOz4W<9k)d+CA}k4n)F+7Z25?<46} zg!G5l8&wKNCVkx?|8!O5%@U^c1cUBs=ZS!#2J`F5YQEP7_sokLnRzt7IrCyp{RAd z8POvl^Si8sp5jcMIifIjgTFd46#2mDYkd+8ZvCZ+&=nJJRtV>6LL$1DJN2VFCqY6t zOsmt@G4g$&cfiKL6q>NRqm3+Z&pek~Xr)SF;IFbCJcRlLZQw()ERsA(EI-=iG^(L( z^?0W$#!xIAp70LfK7SmIMTFPsbNZ7$>_$Xyje3W!VDcs=7=qOJeLwywIpEX{@lC#~ zXjovzqRRtcc6cdEl7#Y)$_%!-fDE3G=w1uK4SIIohKm7-5%)r);-XE*F6@4}L0o3F zKBc1Uli}JBQZ`I_Hdkb~wpl@JjsTNXbK1Ojo>|Y83d1n==tn@zzCObyS-^@hbr9)k z#;{{=^DyD;Y-_4Z$lTCGZ--T9`kCvM*nm=t6cJZlYQaIvCx+FtO4Qwc#BHO{H%ldA-ckCjHD81TS$9KH9~_RozbqZTAm;Sabo~h%Apc)rh;J7r8e-Wq=@2s9TC-FNA zu&=YHNHIclP(&*|BoT=7or7viu3D)wUB+>}{InS+wCgbks`@eJ5vT+8yrH7CCHRkuz7*1i12Z4KG< zLk(7k^z#y^7aZwn@1RSfwb!_oIEAftN~i|0Hm;>;|3pjw;sgMtAsjl|*k%s#Sv z4SY}b*;R-Qj{J$R)X77EgW3TCkPHk(_$6$H&zeB3OVglg$iKCC+r_y;H86%#ID3-gXLA5q5^i#Ma%8kZ7QqH=h7}EAv9VY>!i>mte z8`Bu|6mt|dc)p$wz=g|!*hrtwop(t^L8V)qb83P#ux7>Wq=WUIw;GZ!=%9{=mjsp+ z%D;Gv_97+sb1R--Eoer*kf0pkv)2~v&NwKIrkM6!%Z&{fUpdt z83=>E>>I9%OsCa$Y^{r&mSY+MS26lPSRcF#YxQIYy|v_AV({>!N4oHs!T`6*uuEaKJee`a**3^}EXL^gwxJ?nQ7l zFiX$*O}8*|iI%%{tafzl0{>&_eN4;!TOeFIK%>=%m&?tT*H9a>Vd={C7YKIcWX~1Ia5OTxhkd1VS(=E;8k?72Y>C+8${!}#WXJ6~P zqH)>copIG-oLNXDQdZSDd%e0Qe|ndyYi8$QDk}+_;Nt&j=SB6edJ3Ep+TQGIIj^^D z4wz9s%PM=(5wg-Zzd4(CtCh)Yo<(5M{pv?_ZKvTOpNe65SaS?ZdvVh}zX8&v4^Q|o zAU?t()G;K+@=rsgmavH(M~~Ziz-14eg;P0fd017an;Ui0^O6XePDWZ!w0NpenLJ|I zMOI5QLFF<7O*nQnw{N>EBug>l6y*x9asIK{AD<4|`Ph51WACG&m4^wBq&x-r^<|R^ z?1T!`jVZNxk#}F~qO6VSk41i01e{{!(_Z4VyA;5!>hngG4%T-DR4@%wOJVJB=BmZJ z>xiJvp^YFoXnWl9QZz4;RI_)()tepQB>N$?iVb!bO5x3^a7!L$_G3c?zKQ^-a7i<| ztiOV2T`5zFe-JcBxth^Dc_}6b`PuM*5KQ||QLvb=Bk3aJ9om=$TQ%M^1~wC`Iz7!s zH~)HxFTy3@9Dm#pNeyBt@qcfO`d~6~R~5qhPZ2s|nXUr2B_Aef=nhUAbSoBWyDz4W zOjF<}DAB7q8JZ$MK;uTVFTkYryl!4mZUofDI0)F0?j(yw^hS*FY{%OHfm-$~0+sUS&X zMf9AjPq3U6E7lN0LuT3-Et=wy%o>Xu%RY}`?4^E5!wt&ot+@}Znt?!;DqVRe{-Koi zdsQhE>vmCHf(=_X2o)hSvT3PI z(f$T>G!?a652~*uCMT7jE*>71Rr*cY0ITuQxAc{u?d3q1Vno(tp2^lSK4m};H1(1Djl|`lg8u2Q^hlFs5|)*E`husZCcPO zbyS(yMNbto2N)683boQJYj`0`zxoRHbbv+tqfj}}As08pbe>+e$VGuHupQI=V(Ab~ zF*e7LKZ*3cYRT;Zc*%rhFV?)wSs;0fFKxozWswc>88DktU~HXZRE2|z+cf(+^~aAX zB$rFg)7Ikp7bh>rfwN>uD24;`vjjjyABexC9@7)Qk* z*g`w;81;~nioa}-jR>Km#-})i^F!&-{*qsRJbbu-0NTMoYvWMVg)0aMF!t<|A2DLq zFA7o%-h->ppByNsg~U_Oq;R68ypy>r%$PHPmR0i-g7exla<>OsEkZ7FSl0;>QX;`#F%Vh|q;05|io5 znPp>hD;CHpl0sV1dV<~DSLtit3S(ttm@^rV&mBgE6lFPwO$Q^dJjh$V+ zN7THt;MH=O1ZU?WOhKkhO7bq(~(|3lTEmaMWqof456z1A&#c>28TVhd&-p!)j|qUng*<^XF34UUfu@ij!Q|VM-ast7Pe5&o zY95Q~bBCbsu7#rhbC%&`3OcWEm5Q1BEUZMO$nv$BYpSSoY0aD1z{-{nId+)e8>->x z64T*=5w(B6_U(+7Mt-29kq^ABiFwR8b^igMP5vr}TQAS84o}{~I*G^!d&g&$zq+07 zm+xh>>CSl%!9wbek6klo0JWR546|%ewA7ca_OqUYF<#;-3EW>5J4PM*rS0XbZjvO; z00Qv7pOYHrN^{ks)(ZYx4y_yKABxRaL-@;jlaAipw3nC^vbp2`<)KuVoyxu=uTPBr z4(IkcYA`#XX7`itk8fRyC7A=!-1}E)0Lu!QggP63y;zL%wMOen@ z>lHl?vQF=r=b8~CmH5#!8}GFwGDaHFVn&bS7-|X#xMP*GzrByOm%lfqOFcq!bANAx z*Gq6~gVHiD&&|kmksLL)wMwPM&p8(P{wJN}E`*0`8!Xkgn~{-RT z9oF+bO0=rkV;Z63O8DNr1-Q&Ww28OHbY&+i-8Q^0?gcZ`>r914_~)q!f@r#%?3RG$ ztAUU^v@ETy?w!KA!*x200M&WkbXKxKDPVkrXHgty(oNS-zgXm*I&||;0q9c!;|d9u z?Gu)xBE=?_eAj!b#vv$2vGJS%mn&SJE)p0#Bfj40Bh-K_4Qhe})LuE9 z3kzUYE?f|PsbKS-GRod4{7$>M!?cr1`V?uxA1ukH4o*{oYFFdnV#8faJj&|UItr8` z2E4;2y-n0C?4QRu4UrcJo4n~k-3zUC5VP-1oX~$QbBtx?fj#yWthaW=SlpzBe1v|W za^`EA$fG5@+enqWp#=b$Z?YeuI`1zavRfkstuR}g% zZ3@~6&-V&v@H&gat{n;)JskV7f>qP{Qw|Jd1{LvdnEnY*Gaq5z(PVc^->gB^h*Hp; zVN)K}e@pCDAGczWZQ6~(Sn+s2{34ZzvTgs)#QdLq2#w=xoODLA(&N;}GL%iTP*G42 z-vk?-b6V9zx}qCB9lQ`$P~M%`&s;dwH;%-*QWRvbi>Qd~@Kbo89q-V&K&x33khMYQ z-40WRz7UpxR(Q-|9T@$UbH(XeMT^o~XvaGSWN*)!J9RYUqNM~totO3+fiz6)6Kdr*Hv|4v_w(Rag2`++#oPiC zJSo(0nBg)9cj@_Ut(Z(7^ZURMZTx~DJ@RWvC#1iTT*l1-PO3=99hM{>Vo8Z4$Nf5IX}KId;@pz5?WYyXVAuZVoPa9iJ(-cbKnLM)Pejm=sq?6Swje+q*~lkE=;0Fb4|;@R*4sq|E6hB9#dJc_@ zg6#kata1DC=usU$7C{LoHL&inL_s55kJSiojbeGgvL3hlzKKa#N|}UWXt-3dP9$6W za=--njcA>Z-9w3%INFSk8$p@4-O87nTV)K&+68%zlR@; z=&JFxQPgD+zIcA`u6Px&?LCBkE}kKwvXMYp_n8Rw71AF^z>`S*h`{S1E#8 z3Gpk-aH@&G56)~smn_QPeOm3$#E`@NfbYbu_{y2oG;lvx%?7jttFlex#|x+GZS?9pbB7I9td|6Jpyz!@=Ei&fO4BXvMj zMgYCZ;!Pd+$E2a86-4_qRM%nE@oV%D6`~Hv;e@rLSR=*Ax@k23Nybpa=0>JpN;E zQ&UYFl%*?~MS8XU(86+zeGct!$DE{S{#ekz{`Mro2v}=-(u8Yaer^yyH{q&LEJ`Ls z?oX{D0bhfD0HXLwOCSlp-}|Ejo?@ZAqudh{CX7!wBvzluOY9)^GNlrn?2eNKrKu$y&uz#0j-I zi|b~K@dQdR@Sg_T$qU7VOWJce`LB&^i>Wzv;(fejxc}-IYV+8mXq;JT)?YYULVdYzEC)AVIQl4yqzhX89e@$0 zLuKzPv21PDfpE%D*P`$cTM+@4XXI*6 z*O`WN{F;iJN-ESr$oU_5<^E)y2&U*NfNpBjAC?kRuB?#Xyw4G_L#jTY(xX)>v zXP0#eTnL)0-?RuVV-GUN7iT|AcACO-t=1erp}=RdQ{Oi~lXemD&PDZx2bC=nn;sZ2 zIDKH5qj~)0=t;Lzqjp&5#cJ!DK74kJaLj&PnR57si^t$f%^7sTTyru+mzK;*hV|2t zao@y7k0GiS>)GHU9F+cjc(kY$tWq%7c*K-9wWXe~!^37)tPo=-SSuze<^`12S6|(k zxULcZS}4mLNMMBPl81rpIdE3{)wp%+HCw1hU%G!kF8QJHoS#Zfq@@1U{U)zJQ&oJpdGL5H?oN?WCzVgb4Z00N= zD5cyruoe+j0QIk$qq-?wa;e2b-YY%x?YI(Q#6mFV*~^c!bI(;f(N3LzPQ(TT77-bX z4O3PE9ybHdz97n1i|h7up?Y9XiEFk@awz@YIWRc>Pl>Pnb+t$}#itnb4H=?rk?l`n znSCe!0q1T8R-xsaGm7tbq%rR)ejrKGIr(u?om3nDZkMM^yN4vAbh3~ND&QP3*A&cxu3J#wu`+-7SxpTBCH+(3 zxb$W&FOAG*HDI)Vp2!LGnR;M1Da3y+)(L_y2$I1@4>#sd9%4M?xsZ}=Yk6)L-tv{& z#ZVAeAhz{hjHQDtavwf1iCz$PVZ@Msx@KC@Tw@-^9e4J*0UL9;&TwoqIpnr>m^heC zkgFfFr~k!X60X(3)IO8KfIlDd0M@%ue)!L-$i9jHAGYo(MwDRP0`S3Mxy8d<-o1rqaQz{fC7^AkFm(nS9x(&+chYULB6cpQ_&rdmhX>V5zAHvr z|4*m4xp)3Dt!?=Vi@;sCW0vG>*bW^v4*(6IVP*4~uF*3`!%?^v3-^PC$ zGRJ!(_aj*6HEK&D*H^Cqi&QPglb>Rr-#-GF+z=<{q=#@T3y^!}HL?OiPih*p-JQ&T z%tujOXv3&;DXt&rs{x(E3K-C1e%_VVv3e2j0eEI*P}7yhU|A>>^T6(ItjrbpD!07+ z@x9Sq)^-n}RPFH~(!5(e8e^uvo>x#!)Pg{^&h8fm<9t+e?x>~F&kP|gBKP&4$(RNf;%)CBG16-X3g38u$ zg$DYK-G(oDqm`*oMGF=EIFkya5*dG5zSzrj2&`?G_FjW!jhNfS8$47;1;0ut{js6A z^#o~TK<;eWBa0Qa8Pe?;S8(V*|>R5$E2-VJQD1tgC6K4LRDE{CIRL5 z-Mt*%5@+Kpvv+k0tSY?v$#>1wxFCUZ{+LRl*Y!*LzrO=5eLI9{r8#RVmMR-z3WFs+ zpFKLC(@>8NwwM>OsDklUNk9clDqk@@yL|Bpns=Bg!<)_FV%cQ~&u?iI`wgq0(+m-4 z+Q?kXapa$X;|fVGE&HK3CTTxl;wHy9y3f<1sEX|$RTP&ZqQy^?*O)X?L;bR>xYD57 z&lW;z{On)De7b=?LZQ{oODw~y?5^_Sc+gWcT>{&S=VifICew3Qu-aD4_g(@CW*2d}U+Q&oR^L^&*z_?V>K-mG)65GI*kWH(W{$8K!J6!6f?XDCZTRaaja2TX-zKT|mypKNH}S)G z!<=WrAvBIksoV%It?aWy)%?PA}M(t3#W!l>NJ;yD0BqVH@E2f z_Zzdkf^A9DG# zG!k?;Y*kqe=3owtpVH@RCtD%)_&ZQkPcFqNg&;Z^iwf}m;?JQ=BJ#6ufw-D6L~B{ z+O_NJ`0u=bz%#^zw^AIlM|ejY!k)<+IyiEZBfb)6oNKoz{w?v+5O8t@%nOnI}+;zvdLMU%jq)0E|{)X-f6B9dlCH9 ze?Pc3HkoZwyz*WfCHXUi$G#R$dV6p5M-qe^P2!Qrx8_YlS8pf+_Q(vUH>K{<)Hy&2 z>E%b$8cJ1NW?m_u;~Jv01AC^`uS-Mg{)GIN5wswLZYa||hRhn#>IH1()`XUXjrw{Y z24faY1uAj*18*rj;fP(d#WON&?g&0*24Ie2JjD=P?5Egx-@6k3(I12&{C+6i8(Nvi zR1v=tCj6KjDti10qPgT*O!Wh{!N$Dp0AqsE)h-X=>z=A#Po4ZaS?sWQ*CQ>K)qb44 z%s(gFg*)0_#poHpkLt7$8NAupBbbNF;Ol*hoZe(~oAwUj~dh>ftrJ5)6} z0q?qPOMm?$i971LY>FKj?LrKvR?&YusS-bf5s-&r>p9v6pVb64xyU!`)8v^u)bBN3 zs{#qWxYAIzf?4q2WaiIkd&CLHBJ(+cW9}GJj3GqfIPaG*dhP%^4bGm9FBvJ|$C;PK zAq7ovjT7(Yuq%@Qa}eK+oA)oheG75hlZCj?T#tV4>x;UFsGg$rcc|{SNPH4vX0{QF zr+Wv4G0_?Ue5WI+T98^~=K31%03O7S2Qylop=C*{T*(40W?|R5(tRdHG19SgxgDEp zpKPyIDWh9?q9`Xl)QGCMa3W$*?0qziY2ntg1)zY0Mw(FA9Q3%XjXn1-DtaLVCfVh` z01h}D>>Hv!$38#Uug78rACw>i!F(e!iL*6K>?=&uh-uzBsNkMU*fB+v#O`Cm@E;k* z>uI#PwMV^@_cm4FQ~GAHIYRH6#nX&7?e#ew=SS&RtvYaLtrb)`uEZt3HW#u4==ywS`R z%m4ZQyKR@g$+m}*syx!3P3;q};1v3xrM_g-`@*Nz_GAkK| zWDWFaUvyVu14{|3V6@d4JZ9`x3nNLdCOBb4FY<5Ud})MyIhCRTcX5yH&w4i_h*~E& zB4_;H51@RJI9+dHzGtus8*2D$D?Xb(^XQ+61OmW8oRnDGbt0LbXJxQ~dV+tWln9_F_tZ;GYsQa9NXqZu2E{k7T z!52F@hqSht2|7G4*F;iyy(wCZOH6xE0Te$fgD+@ZO6tev13iys+vMX0%NGE0sEsP8 zkF!@GbMNmHTtn0IQR{34lZ9Xyw{tZd-wtzuD)?vtGD)a?Y&(G)c|)h7`$*1#bQUg` zLE*I82?Xbrnw~4l0EsU+jUwVDoRVa1$Je^5#U2a!rW~2z4eY2y4vW@`Bwp#u748Og>q zrgc)x&ha4D+pMLovP|v_F2Tc>s#AN#H=ZI)zweL)?-~<~)yN1|L3h32?H{+8#Ib;l z2!q}KjwrrZdnwTKqC6%(CQ@OOuy+kn>P*Xr4bFp_(H3!mH0Bn=0_d>zc~YG>V3~Nx zh=?XDm^x4+N;iv(4T-I+RbJOJ#-s z;RU?>Gq?(^zpwUDIamY_Re>@2(XvZFMw6ii1zd;GqxmpRXr_@KnuPpt5n?$7F7!-J zla}!oaRV1lK{zjd8TbbD{rUQ8;b>4ofar8AUgo}mlQ?GaEuakrT-3Y>As5ygeNxl( z9=~MG5w@JC7>SmN)cZn}dID&(9gyf80#tfb@QMN=n!Z~-S6EFV3e6y;U)vLVfevvb zzBhceD&6#3N$!VB=2uxc;GTn8h|kpI!8!riN-2#cj9^eTVA9Qc6R57FGLtgcaELl}lfV9%SpTQdJKG=|xHz{z zLm43Q57f!O^UUvMJqOG#%C@-yptqcsH`wp)Qwy^BnLAYjM2e%2i5%n7v}vKEg~)j0cwYDYvPj3IBK3qVe1i9{sOFXiY6?IUr+@wwRv9oP<+)Id zLzR!g>Qk#8pbSm~E+u|c+=%H1DLP9ux5&wosACSixOqaz@a8340%3udDyd2o8~1DEy4Xsa7Q)JpFGl?fjUq8?8P-y38YrkMC7VdM zLS2CO(>6i85*N-r_91UKyh~$#llr!xEI~R`VUZjIvAu~Y z6dxayvx}3dp)HihMstU=%aQg6Z;p$NHtMF@XzR6#O_OmpZdG!e?dDa%VH|hsciF9v z`Ax27pZ{)Zs>;itZ(h^vyGjiaxtdBLI#UZfSk&fb#~d>=!##k>u}aKUPG;s==(Vj3 zAPtO+j7|N~5s{n#F}k!jw<0k*0eryXFwnpF;zQyoh=HNeK^Q5x1i*EG9KM`#Km)k| z+?i3y#W{cpm;&ZED9UxN?pbVX4*!+_x3e@i!LxW&L{D&ea%o5CWIk5))002d_c)pv zfCP4?#%33{wl+}Al?>nlj1vrir}ry-F=@cW4x9l@GeaXI@LD#YN?;ZMD=MQYYCuS1 zP*xEX>!7$HsyaBhclkeMt*EGyOb{FaHAx*67-0Dv0LhA~(*LIt=$h{>dlB$RmH*5C z!w2L?G96hNRcToX#n|kt2@HVwFYMWo&3pMjWv%$_f0Z@y%FN`RYkgP%6*M|JIG&i8 zo0}V$liC?Nm>0Pd7&x|n%34dk3t0OmwI` zkzcfymfW7M+}B@>X_{-9>7S{srR6}y>6wLjR0`4$|3ZASwLaSu0d#^qa)adRu&+?o{b8(I=Om5-77!tZ>&KkCtz6` z867^-F9%t@ziN6Ta}&73@8nni(QfVUrcY&G9L4kKJ4;Jj(>+KA(6j;O@wF~riNN#k zEaYdt-a#!J+k;rEK;>`N=`R@Oy4HrrkNVoLhy}neLg|P9krr39wikdbDy^;z%@6CM z|9YuT3?B%+iMbu{*IIm^jFtaP!gRO>KON2_|0`-hUS{l}zYjhaOG7I#7dLRb#;+3~ zKiM6>3;)PZI8A_}l&YShaLP+x%Y%AMMs8%!pVC~;fY4lEgQFvpBgn}oLI5;3w*dCX z@F>|pJby}%zhegGw-1Rx4i2vOpc(7j{XgrXaBu*{cle8a2;>2ZNA^RY1}NXyj=&hh zKfxTC05J#t#AX1+L%V0iWmo@RQD6QD=-dH{*ZdKm#rgBQXT%F{_D}P(NB@wuL31Pf zN5%<%?Tk!5ij02@nghTO?r;BoUCoy`0Cm9p7k|Qaa71W%Fz8)AD!)zIKL+ip`X7Tv zvGxV*ch~fd&E#MIE>3v@&-U^gKm#Ba?k~UwP`vmLS<^r5`{U1%OUwJS|D!Rvdui}n zab>g*0`fz=7hG}4zX#6z+DAAE-sG=h{66;j1^v^uhVr{r@2^WJ<6m|Ai^uD4h>A|` zZCwyndOm9WicjbyMkkks$0dV*n*TodbN_hz`}9)<_`a*Y%HJ3odd=H?zRr;W@I-@e zWpHw2@S_1hoqg+nob`1{dAGX#=qU3O`>WFrKrjbv0o3)ixD&#@c44h-agN?#&uoft zv;{+snvu_1iu^a7*^KM1Ui7h5G5{zPkoG4NCG@2+iN{M{3FxZVItko(t^3W02`N z&M8%@NPDF<4SrvbWp*p(#w7TnAtYuqvW;aC^5Wqq0uSAGiM&~c*<1r5ijxlZd~P$g z6&g#ICI3Bx=L*7D0QKUGGpIg8iRin3W0c=@P{j3p@H$=Q;+h&r}5 z|EoiHxiNGr!+sh>)Z|($=<7WUI_Zpd^*9iL;Z<1#;x0BFqK4RJPSM~sGkG#aT7Mo5 zzg9B4&J=p37+%pFJRxn}pTVg<`A4XAo${(Z9^(-86iwyKN)?N*9p70j(JtUn+{yyx z&yU+tj+i5LJY6KYmHeK0pwJTvZqi>(ITY-=@$41d8f&2%Rz?DrWG4C(h2XE3jV2|C z>a9KNs?q2rcV{f#Dk{4lGPP}_yy^1BcZ(EE@c4&^Bm5M|{l=KzE~WW1W-D#Hs4`0A zu8-$?TW5+4B*uzVWTq`9onTNmbYYX;#s_2xx`LOW`qL2KubWTYHr zF~yXa7fJpNgn62?YMQOe-lesyk4BZs@wQ4G8F5>dpql3&i8XmA?D-2`7@sgUqv^HhxYzWURJV4Ey*vTHQ)y-C0jeT z0EG5$GRq@9{fMdl;8M8;Gs5_+k2AuhF|tF*N*8Lxk2%EkbgY=`L@<7(n9=)#D-^!C z=A%8K$>ug-2yFbUE$(an;Y|@hDerD`GNb@TlL2jJdPwG2&8UoqXURS4*2)?RT$T~7 ze_z-PqRVW~9tX=39B`k_oAR6&F%dRi?Bw-yTB?9lRC7DhrxTu=r>Nm!7670lpNQ~o zX=b&^6S1ZFj-#4-#iuM37X@qr{q1tF?@>*kcMFuFIq@1}(6uGIe>L%rJ}{2QYftqm zz}(hfKkq+l)1cRk>I#foiwf9SCO?7TTCBTTm3?N zXwMc&pGwVj>YYbuBZR2V^{!6aaky!_Yfrykfi3IS(j@Igm2kiA^2$yZJ9UK8Zvc+` z8ejp5yip}m5MR1J5>w7-&-zt>+clTQ8t zvR}8BrQ^B`gcV*$H(@a|Psr5MA+95|q`h^Ro2q1F7|QENEuH{Y+6(F$HTkJ3+yjCu z-dw29gE^vuJ{k@J$*9y73HiH~V>dCi`y9jrz(v`w0VXloPdmA(i3^5>yQ> zUn>CRzexD9jUx*{lBQ!lbrjtQ{-o&c9?^gOjQoX>ee&3FUyVvH5*Pz*QEv++CYw|z zEeI}EDdk8UT>V1t*ixqcCcH!N4NUEM`e0?NaXj$iFkz+ST#iSOSi0T4O3LI9)McfC z-eAtAvpx^PVGc}lsj3-id9DX()`$A0mCNVt=)AxHgO0i8p`#ZfKtNMjbpsiqx}dV> zROZy&a0e@nQ<(LfrljfHgXqZ)mQC`6_z$q7XmDmg-JC`-5Koveep$8K>~g63AFM}? ztor*(5Vx++-*>FG?DcB^ny-KBS|=O|qhIOO2G_~*(Hi_Irm+P!6?@_iZ7V#z0zBZ0 zpZc2z=CeYS%l(=tQONpYmtE_CvR>lA7afHeQX?_jYdEL{bEPH%g;u0#)K_gh_2Nkbob%Q&S|1`KM zaFuQ5*xTS4=LA8+3cIACUlnQ|>UjWIS&w>IA|6RWl@m7(MT~@CN_Y>ZUD#bJ?`FMs zo-HDpu)hh92KvwfPoXLuB(i$M zuOLx7=X5v{rVD%h?{ZX`{Rk3O&uW%mJFr7u^He*)E&$^qBs)pZ_%2Ll?jZjAO|NYo23i9rIIR*8Vp)b`nDE21=;J|Q) zJ;H`PqWjI-BEo$*TFeftLi{zLx71f-ov({}LFf-J{7INKf^FH=j=bD5_AfdYk(0ggJ?ijzOW=7#t#IaB9NrJqQo}VW^%O!f| z4$1N1%^c?v4{3#m(MHlQ}h+?MHhMD1(tYq`{C3m81 zUN3o%Ovx6YI6nPVWZO0EJ1~kU_~oDoWvl>7^;vDNV9`}Uld2>R zDX`EJ8jHC8C7R%_Pjy2qi#RY-5b2%K`L+pa1r$e6B2Vj-NiJL~*se*7q zTf|fsqrw9us*!^HyfXWNkuSN|J2d z#nIV%fKP6_CqzQ>KFN~~cRHh#KAgVf*yQ81u-%b7k)-E~bS>Q3gg#1aIESbSC%^c6 z&6Wp{ahMY-C-xK7ha&OaL6S`s--+%>OR`73bqmk|O(aJR^N0sU0ydWR42;)})ov}? z@RyJbHX&~f=g*s6Q0S~88T<``bDjA6X~xb{Jb z5v@C=?Xjwf;ThMVdehD!+KRu}Ets%N*Nn4O5J)KQ5cq|;@<^fu?{ZgP@dXy515&D` zj7CDmzd0v99=_hJ^_hMC(JL0G=9wcocoH87>Y)GL5bUKrCRP+nN}WVUOW4dqa`;JP zFIz&-H$1LB2yR3_XYdeKj~TF7xvTfr){O>6_&Ue-3mgs>Y~%GA=GitR?77*jSwIZ= ze5oHlGH0xc>EB|KSJ<5#jODF?g0D8H2b;muz7~V|iXmItQNH6TV+`cJW!A*IWmiE> z!9|~9oNElQ^Oe)@FoSF@$B)ACS->fJ42YFIpq`#tiQQg}$mFlQq=shgW3nIGgNRQOFL zTVW~sD99Tv*UM{w(b;@KC?!tZJ?y@~;xM4=^Rj9)wK?VLOV_Xqd2RL>eB@8RPoVAM zsENggYopZu>$r+W_|St6hwDncN|&_q>M23?gE6Ec>&cSe3msxb`{El)st|qX!(?6v z-z~KOlp

    YE~J#=@?EFPZn(lgOR2(JGr&=2Kf-|K{`q^=tb%2 zDJKS~!x8>_rWV3zZFh^Qx6ml?f$n??aO0kZbU>fv%4*AMbA^=QX5Y|<2^l>Iby^Wy zO6yPcyYz+UBhr0%@=o(!bwY|s@;KaBpFZyqyiIjm)ya67DxK!0-o`OBZw&5FF%ee? zKA8jm-o6)~T3%3kL>BudfwB>jryGSElQD{Pk{qOga-_foZ)b)AlywE=(Jy6*A)V=U z9qzSvz7(8T;Wt^k_Fktk)>-&D`$?(yt|QB}n)Vu3HolFsThHd_RE$JQrO<&-|7sCQ zCHkIz=TP0sp=T+=LBU{aN?CX8Ec&@FdLWzh!z4;>kFiWYAQPRT8Lp?GEvYGK8YRzT z7Euyhr9LM0(9WCvV)dN<>zfL@Apc`#Zg2WA*HhQFE;@-wt_K1cPm+-Hk3@&{Dduv(f)Z_<_SGjcWFwcZ=wsp>d-z14PB2yMIW9 z-9I)U5d@F9U2Z>Ru5w4NI&80x$XXvu;-gIAhCFyhBezR!?mqd(nwg%ZVgYtqs*=F5 z{-Nccr0S1$-YZ(mx|`xT8-fRVNGQ|cJLdjmOHVh+?*uhJm38lBYuwDBXXWHum zh3T>=c0Hx8-@$ppd&N9YT1y9EtAT}Z?Ze#~*T(ATpwYml0{1UX=NsE~!*BYnhqNXx z_Oz++Lv3O~bNg)1w2RF7F1ng8S|EfFh8g;A?XIwoPWLxEW+hKg44KR8GH7W8!tcsz z!cJ+gy4!5>@WcDh+y5o!B65R;2rc4Mfmpxx@J9P`8Tu6tk~1%}Z=GPlAe8oy_FwV~ zJtgNh>Y{R%o~pZb4#gDQZ*>hz_!#IOaHA*vN$9hPrRbWQajR+GWn;TVdw4K=ATm*B6NbA#i>gX(4 za&6gB@j}g9#F*~@NqSIO4cc05QJ4-C)BDy&7nLpe1Er7Dk-3yE+d`wTG^?+FCqXkc z58(g_;LReWij80#MBB;z7qeEdRv^kMFb+-VrPWF(dy|7O;Q^7o_3`j)%1O8Jkr3Zn zN`WdlW{y>PDFxwGPmwlf?>KmO1t1|^+TE1`FXMq+p6kS~Zl3VN&~t19<8%H}Qp&8Z zC-HGHa&eCBQ`{ZX`xGCW{0}YcycNH>7CAL-BGFbaHyGM7@@7sA(i0`}Bsq1+?NGAa zYlQj}4XQ*gogRC~c2X4QF*i`cAGVeiEqhp5;npGC@$C3_r%@JLLLdOnq0A^e4?JV{@h_2Zz7GGgUxe2(+L2EtC(Gp+Od4yy~j z;3J}#KOrF`tx8MgeCxvb(s;ZDGH^szpckFW8w9(R4wsF6vao!N(Yu!*b`nFuM+_2YdIud+$Fwbji~Fo^yhAXZ>bDWHdb7xA`Vp ztvg{o;^?R&-}lzz#=lr%!}pi4Gxp>k&;yr=6>LT4<$gvSz{d9xazL(;NCsV?ddT_XK!J->Y5B>5(Y0?QTb@eYV>Ex9LIt{m~i)C&oqWfl(|NbkvJBMA! zehrjDTy18s_ZD9Qj|L|U(UCd(eyywKx9bZxfO9GqjS2roQ80M#`B0s*y#24wq5C@c zgx|H1j;s^+OZ5Bl3@sg(JYsvVn;E2{O>}hFrY1C_-y8<|bt*dMtYtcv$HW0|g({QP})Yp_NHFne91 zzc2h?#;5OBYP3hW-djcM5bGCaHrsu$b^L#uUX*qvNS>Pr-EVA|bhQm+QFu(V0Mm@i zcVxtCF#?S>!47P?rR2pwdg}!u+L-N=pK8$bc5+OD1Y3dtaML@7LwuF*VWJN7d~vWJ zlt>+7(K|94Qn?5TOBqw>o*`64aAP~{->0zGgbr*sEng%{Gx|k{y1XCP^(%%ri6Tl% z<&Qk~uD9$1q0pDCrt1f$l>A_!(kv`3)F!f)LYFQ3ll&pdk%NyoUh#w&DdiaCdZg{s z-prKgxl{bOPX!psMZe-vj-r$u*`)%jC~$o$TF@_UVM!|YGwr5g76u4os&}q z)OL+=YNJ_ zd0BgQl+we3#20fa5HNz-G!wRzo)=~sO>L3hagJHvu%D0Q&`Pi)y5CK0rmp#8vlXUr z+&-1fX{|82sfpMi2`RyKn+-!;?EUJ(q54`W@cSoiA@6kvCU|jk6XM$_*Q7B+N>9^E z7>zLE+KLD@k6)SJALAYWgot&TnPOdIGzD{6m)&`k!cBLfS8q5ND$gIKKamF$A?&7E zo2_$;Q7M-jMGDo_@C393H%z*0<3+d-%Ki-rGDjhuaoWu7V>XxmoMDAXjYdjrc%dXr zHjs;aES)YLQS?r-j%ibA3cb=AoS1`?_AFMcv^zgAExvQsUh41s;;!)_`wN~WX`I6H81$5e$pgXH91|<7zzB@cG6%qM32h#4K2<=N#x&ePM0QZxad)pe4FfkcZ4xKi=u|YU)&(fOMicVullB-EM#yo5%+Qr|sygmHiyM5dRvx zn*_&G9&%w5gW91gdu7RtvaKFp8>noSZ4%zQlBjBXdC8_#ZcB5~&bIIu%mt0SCD81C zp@8hu)NVq&MwaT*Dh@3+6%hf1>?Qg9YzeQ+^>6x+;Q`fKcO~w-k62Q~`if3Uq9IYr zWD_^)y_;!CZfyjL~Xe7yb;KRoU|10LvZ za^60kH!`*nT|o%-EH7YDxiKZO4k}CNHO$CELy7o?OI-=&q&g-)=qGumirq-*8W$*{ehOb zCK-^;Q+?CQ{ig5|b3KN_W)7GFN#Cj#q}X>}-52oWIY`Ing?fqGY@6^eB!ydpHkvjO z^3|R~z{F3MN9ZLT23vTP>dl~WL~S1u-Ld>*CBgZU$TJH9vx2`^?CqJY(ZXmd6<}#~ z_$Ij;UgcGws=!$Vlhc)*+SquPNlVcw;2WybGYD*mbvC^{7-#ACb z3BH7cAJ{~iHEn5?(gXYWNlY5$b$(kB+$|*)Z5~$@RvjQ=>k*H((Jei^2JwM42)Vr{ za-D*waU8zD$Edv6@diEmE_)v^M3q5;F^q+Xqjo6iJC=9Q+@Z_auQ14N1AmUV6zxJ` z;|P~(l+F7)KoAjmWfIT`9&|ggKxnzp331HYFVb%lWE7ml^0%I@Gm86a@PL`9GrF7U8}9ZP!>j0+hzTgMw9Xiq#}Ztcjw{=l zj<&Aeva=vl2_6bH^WMJ6I~3`5@_U!!(kS{gs{~QjHgoXGSf2r9x?O`~DnXq+{9&?`nXnnc~;@|G*%Th~9t0#1ac$ra*k2dQc5SuCteWH?pkr5Do~kd}ZT zzrWUuBQ~EYX=@v_A`Bb+EmIeX~CT}yyWRPdx zkrkFO?^d`x4y22OF!=m!q-w&QmDTkuCN(T|6fFua)zqG_iIC!X{-MVX47)X|g~#{- zP>DB$>GH3(UCS4Oz(mYipdKF#kCI@mYskpDWF4Nq=OBu zCe-d;knIKc+mSW}@oW0u4dL0-bl;Ql)EZM4^l=Nb${MD2min`z&Dc%OhdMBoyFL;A zT#y|24EeS0yq8j21{m(O44Y4q&tibC zvC_X>xZ|H{p4z|Tg*Io}I!FD$L_Sq@`gl*iyCr+ih}FbWnGm^D7wHlf zU{+&zbhamQcYj;BzokQG zHU(&bEdMIIt`PO^*QM7Vt;h5`8OsI0%sQuG)#=LQz5z}KvyO@~iR0qo{(1N)!mc94 zPx58XueJM5uqi2>3 zch&4oQl3M#B-wNNA>;37oA^7jJL}njY==rck3kuDX4REsIk1hNYhOy z!5Y$IVhoVaj|!_l0(zbKB@fId641vbZ;Um5*oGHcruRqdudQOY#d7$PyuNb0rQtRdzU8iqA7Nycqd2V{=PC)GRV#RLHS+Oq3 zhUt^5?qn|aSeI|P9w(jFm>04Xi{9GW#N|)6r>Rj_++L^a*g+{~K&ENsMuEUbU7TIb ztudU>A!499V@E}GAq~JbqXh=8Q6Aj6I1-9x22_iw`j?Fp5&ldrRew04%rI#g;L}Io zMusL(XN8pOzjo$0Yxx^w)+4CG-eYK9nD1cSOSFd)I)M;6y`&bJC{kHU1-K83k8m|D{{@{H;zFb?y_}aANy?*iIlX2rksNIGX(WIpC|To$XIJ=SV;ZwgrUWxeT|B`Ja2l0S~<yyL#;3(r$^Hk`FaZMEO;6)a`Iam%CNbvzR%2iaidGn%vU<9c^2FC^uesV z8TTQ4{I+ylKLE6lgfS40mR(mc-h}0ByQ({J;1y|N@%yo znqITe&m^U`JbVIR#C1phKVx9upw{#Ag)=4Xa+(!n%k-E*rsgyt7nsdv z)1pd5fg!7s0A{wfS8mfz+%1)@AP+$y8OIVji}sxKbH+sr1qMvvytH5f2zehhv3B1fGqKT?nchMMZ?hoDp5~&9_z~47-qIX_EY#nQwPU?F9mNso|+m)vsYaV6Dd4AC}Y3UZNdl)oC!h{^W@Z21yS53 zJMYs)QBh(7g5wdV)$Ek|;sx`Gf;GrqC}*10-=pg^m{2+l)3G4)y?kIGj(lcdlRs6!G6LIzL{{Ii(v=lzplJR=99ty5k{)n-}o0qvsslABK;{9#|`K@PQnuB~jn|nIiq$FJs_^&t1_3Q{$&CpC7MEPW6_<++ z&B@XDM8FtCfAb^*Eql^}2{>2nr0H`hU~>kl{&iAo4Lo?0eKoEeS6Bo1LLRe3#oP#f z)H|Yhac&11cuxUeJ|Ge%JOPzb_!ZHJ^XLHcvt941OQ}LFU~b2Zk&QGo)U5uML>rVR z*W#T(IAEjAGm*_%O=agVC_lc!`@b4OMGZx~ArQ+<20!6L;fSc)X~0?5uIbOz>+GcPIs zZ4Oq0lv7F2Ag5zHSS~gKP9sqID6;XNBUH*eY{612|NC^DUNe!K5P@^lA^!=4OkA-| zLiym)g=nynXplVf90PE|UndbdnA4w@j1FV~T-KOiYP(fSqt8EFyhUCSghC7w!sjk0 zDRhYDsvv?7FQ(%O6=M}<9caU>&##|hJd6?Sg#CxIK|&PACNsx2SgvArmKf!(<U}zKRZ)lU^9}tAMPpx3{TnxJue%Ezpr*oddmV zY7`;fC(Sb~w)?k>?{c1=4A_j|Y~8RQP&dS*UBiHXtYKhN%%&;?j&_Af3g3DMTMaQJ zf>C>5(`?4AjeD{;yK+02SU!W~Pzi|umW4zlb_FyLX2+;-#o8OLoO(RTWYnu_^~pWI zyeE`nRPsqMB_SdXTMb;zQ5Y!5UI43~{ZuJ=unng_=KFNqe3-K8o>BhP?1vP&Y8`0K zJ@052d4TAo9K8lR+oO-cIa9IrZd!a8>aiDKldpI-_#259hMLMU zS)UwjE}=9Di@*xORwk(la$zN~t=okffi1|^=D~u2Vx~3kxR9jSJ>5Z87;e0F;Va-{ z>%a#{Xz6W4zk{<1LZ2KwJGqGB7VVhz0CuzSPFc}|U{{oEFh&-kvZ@2LE%zRf+9C2v ztiU<>;Ev^e=D;}IKHfC+zKL>AoR9z=9G^ANN%Lz7U&d7}@pT{xK|WJDLZR$wF`qKO zvY@kvWkmlQyiREOuGJzFY2E8RQwm_k-xm#x2|f4>-AuYrbONV0qO#WuV{pH@Gw2Lv zm5yk9FvC&mW`EcKMxp~qMeA3V=GEF4%_4g9bZ7ohiG?$31a)i4d098#1TCz^#BfGu z)4J;P89FtgtBD)@mimaCdI(j+s_7*RqVQyA2v_I(c12?mPIWPqmwfS7Np7PRGIi1S z8t0H4##K6*SSCy&{tkwsuc>iR6(o5Q=F9Cqzl&wgX2hPd;*ac3aqb zVx0wymw@%{zh7)@5wMI86em7gu6qI7I_61X?aC*z zmwtqzGc>3)K5Z{Yh+KksF?9>B{*zJ=F{}4gnM%qBH6eQmYQ}#~qys<6a~CnX(OkY% z4$fNVn#!+Nb2{$@CzUSXg;5!8rljP|*{aDaAX1VuQ}1*<4xb5C;Ts&@4kXGx*Lg!( zLijS9JHt)4N!*F90?LbgBEFmo@ace*2`6BVPFdV;G#mX(i7W9>*eScIT5I(cq^$Bv z(o4@W*pML>ABb;eY^c#6?{|;`J$@5TvvHy#hKtcNfL@;+FrBLN%dC~YI6Pbqbl&F- zaZvnDFAbODQ!~dDD8(Eqbe&j8ngzRTHnQ?2+ugO}nO&#&>m23>#HDTqps@ zlMpI@ECxYkf;FWMDC2t2y)`v?)=Lw&c_U0u{#HGn=;w(;!ftOhe2+{Ww0cDD;+J*q zV+cQD-fhs?FgTjH@hPWYP1mC#VxSxjFivE)Z0aH3;Kko{)6@iR&a%YAnU*DdsrcoE z7fP)XvDYKb;CWw*JP4bQOWG0NUd8!#N3OKzTsg!4J{H{lPdA2EI?35357IXt+$l6GKlq8v^AA&C?mtR&4 zM8I7;Hmlm?pl3^!cV|)4Z<9iuAx$T^73ag#*bcC42^DLGZ+JnL>>T$tyNUY^N(dZ# z$F8f%kMrJdGM%`L9>?X(Jr3=1=4Y6>)Xna-0!@>b*h%PsTJ3W0EV35EId%LPu1P_{DYZT;I^@?XS^PE+OakeD02m;&@#hD z5tu$A%hw^JGr(_N-_Od_@pp9>=ylVJBmb_{ZyBHr;F{>V4u(Qo9NA;qc0O}NM4DDA zg~d7@lUZke1q_W0@*6OjluI=`KjZYX4c9>!Hxdm1)&UkhN0(hMf0U=zUU*P>i+X3M zD99#s1oil}Sj*()Lg$rf@*+A5snTa6e{0^qJBx^U>JC`H1+u?ywbp#3JdzD`01&Bj z-OA|L_{H&i^IIiXqskJ5Nq}AGJhfl&fuWM{CZ>_?t`x{yF+h*SrD~k%D8|>aGS?={ zCSTl7PvsE78&cs@clbn6#PEb$G4$O!e;-dn+9uZar;}O?3bXBvU*ovE&Yh#$=Jpsf`NYv$EoNVJ0Hy{HUs220}PTEG94uVpX_d>34yK4I$yS5E5U zumv25N4_Z`RzQ?z1xz1bcQ?a?8$Xu9ok{a}vJr8>1Kz0?e~(HGms83za1U1n>A&>p)% zAe*(e=g374kYu{z2PDnpJFzJ@gJ19YF-v)E8*L)Hbsa{U-3ne|HKRmPOX;GD4@%;D zNr4WyKXJTR9k$hedU>x6-MwrDi|PW5uE7d~905vuOD+*C*%SuasY z4kZJF_MUzom&TaYH<~Qv5PV!eZ4T~|MO|8M7|A>&$li%fIL%t$fiZwq0bg%<%F5or zulwZPf~{v<*D?W?XhgGD<-w5eB0G{tO?w=9H-S9XbGY0F`NC+BxQRrfjHup+63xzf zhNQEWYL!!CCczx0lI|h|1^wvj8c>^G zsp=I}(8k+8P3jH1Z=ckd8bw=C1`-B1b)|WHCa!k2%~7a~Y(j<1y~ZEODO?xGNC0sw z-4qP)aPwZ*2{T+r!P!1g(4H`we*;7)ih)1Xj^}BDI^p|LmapW#fyVR8)KDdvvx#Kjd=QR4^V6kFKX=Vmkk#+& zFTI#{f9oAAMiwWvap7r~y&w~0F|`-B7x1gx^7U`ET{ff5Q*}2pH*zK;8YI9A;l?SB zT#8Tb3&K(gTu0BxgXfmMTW!z`@dDR9SJ$;$jo+#wQ(%d>)zfJMuIFkxmnL12L3$*B zJJ!Y{5NjdTmO#OjVF#)7Ac3KLopJK5aK}val6q=jWH#M)@=`{^#NZwHFZ^|+ zY!6dQ=z06YhUk{Etf0Uz{qOqp5%LGGs5|KFQ&76uZ7@P~i<(#6d|eQ;nC~utUNCft z;UFB_T+!`n01BtqW&;03<`nVN6_drLO z2KG$l{9?W4?~3G{ey(I-<>`}C7J8-8vNjZ3$im#rM7Q{WIQYw^Ewfx1r_RamKBEi( z13Zh#sj|NRoiE*YM1;_4(|FdP-Fz<{p(7QIrZh)`i&q{4-UumJ9H%$HO^tmn>F`=2 ze1yhB*(jy~Pqm0#Z=_(TCzt|mn%81OdZa8HAw1}=En%vQy}KpZ%BXtvaGwEMYU#-1 z=e%dYgx&a8Df8^$+cRUYE)0=PD5wK#>Bw*iN zr-K=8Juo8Kg!iKNoybQGo(moO%*(&ZpaLCdIW z+jV-gu6g+lz3%Wet_X{FQm)XN&T&ws>A4Abp{cP<1sq*M&+Y}tr9rlVz3-19WSilF zD-MdV7L|drgv5F3Lr+UKn^(h%8yH`VN%*8GYun=1=oJFaK}7^JkX%dXTZbrJM^K4R zN5sqzTMK>6E~RIuk{(*NTKcU4=w!I=H&_P@?FozJH+j{nk>HH4j|Jy(41XX#i*K$r zA+PsE>Pq~`{F@T$1*pBz^{h%!Hl!903!lN~8N8$;6;)^%qA@4|qd@&yVs`h;n3qen z;5Nn98Iv1|a}Q?kTe1by=4y};fLz zF!2bT!pdVR6s3?7OZKc$Oh>m5^DrYqJ(DJT!Ret*9kzG1%Ep}BVU;bAmj6h0?L<6l zRoHD^Sl90^1#+%KOtUf!!&me|sA81eDx)fu`oN)Kg(=>Js08adeyU(W&b;E=l_+@y zKlk`V!|nh*B%Ti*suvQ1V3ZC!A-u~rn6zHYWW&h&;aczm$Z^MGvMNOvCuz8!PcdeX zqI1rp%TfJmLFHvBHG8u4S~7gk#S0%*rtiM!Yn5AEqc2k8Y0tUMghd}*NDoO4{DU+L zC<bCu+T>Zd`^NeS5dEZQ%`iVCon#_oxk?6t%gN2TIG91s@MNR}7_4rnY(pq@0I+K^Bz_YnBG1+_sFUONZIX*L+mbAo(P%6%%q z9*;IvoLxmj@?D6Ze3(@<(T!4E*IUMkPDSmfrnJ|N%t7_THRtpP_M9#v4Vpqg+S~6Y z$FNncnO8EhFd&9`O3U;QJ*m+~HWSg{Y&gaZoQre*`y2Xf*v%Kyh)D-cmatvyuoXZq z#L~ID(yih*w4Ha}k0r-kyggTk^6}C|j6vRi4>jXhkOpT@m+MqB=8yVG7Z;T!|8=nadDAA$UjCsE5b*B#PA^p{l93VCt5Bqr)gC(W=O9@Q{%s505qnqbDr(C#d7Aqe2%HKJ1F2sg zXmqWKBLn?L4h8x3Q%n)nu$)K-SB6*Mll)4L?8PSp6lsrObv%iu#6FPsoo@mBqrqnL z1U8f}ohvXFEK|#XUYZ7rZ>T&G8VbSeiq`xz6&JwPxgv(Wec#XNjmLjmf2$@2>JLkJ z%yefEheN*;gDR8w)K2to%ti2a+uHg){!F0|m;8P6ZU9tJ<@y6-ruD1%mAXoU8`kqw zb&iQS%Iw2aSjN6gB9OIQs@$|AK`rlInFwnnV2AX%|4VCU5-Lw5lZ#GHdTC)dqCWr- zx-<0gctee_P4QiEf`a?6o7P~k;7RZuz3VHo&zpyr^%>cj2ow6V*m>5dD}5s*WVHOi zsz{=&c<8E%zI1+MFIK3sFyDzoWv0H+t}M7elNC?RpKU+G@Ys6pswxw9c-12&!<^IuLTqlW@bgL_>g5~Kq|b|7EO2}k!XgsnRiT@L69Uc;t!%*+ zdp&}3YCx07@JYA~u2br^zg%YS%_GIJUq<{(=sNy0#=1`nY<{8-TG~<5la1D+Bv2uR zTar~w|HM#ae~?SQe9OVyA&n=7U|k)_6|7^h+4EG`>Zp!yYL{Yu8=X~qOW{)`!;6Sh zu~fC8#3yQt$IDR3r$7RgG}?#oM(Lr;=V8|{3{6mxjmMiBgX z6xBd)-0eQn5c^OwoT4e#C+pwt60(jRiScVNpyqnYWt4d@PtCzG`pnL10}5@}WwEfv zW=*YAeL(y^Nfh;f7I0(J5+RMUwTW64%tJUD;2jBsgRAtMQW_tlR85RAr@h(x#XM%c zl@ii?(sD-~9N0Z^awakbN?`lx1^JYJd`zUXQ%Y~RuDFzOc^5=NR5Dbh4D|H4tY;;+ zr8tskNTi^-Y;Qe83pM39h;tnfml>N8RzfMLu-~xMmV&i4rE!Qbjf6G{_Wcy!zvchJ zGI~NXUuz8r_u%@{a;Qfp73aydw?#~Gy=89rNXZoq0416GWAF}_0`+-e)9T!^K}oY) ztp_FE3Z5+kD+dWPp#mR7|5}G*Vp%(|JTg<%#XOifo_a4~4WkzwJ1A1yA}0*D@3xxjV<>Q^W9eDU%FVsi+70H&VPOvgGjz|AFkxp#&;i z5VI`+^*q}$ACHJ4Zmgi*b~z-D@(|5aHY3)O0_UAA zSZ&PILUK75D?ea;RFNr*G&IH}avwLnKDNd2o;z?G9>;0N88XYVVZHZDd*q>zPHaj+ zQ?X}b==n{F7?@Zu`AKw*eoq!{4iQhC^z^-%Pnco>`GQA0n1g`tt*9PV9*xcreA6FA z){3s|NDjd@wynA8a%dHIzP-~y$S+^>$LMXdE{jQ=p_6x6EMzrTxFg`eG;9qW6-n)H z3*?JOtz)HTD2E=%EQ6DcY_Y3ix*nH7rVCS0I_^{CaVt+`DDe8i@^@$PXmq@QLyTq~UJYoCkat&-!3iTLp6D(%T9{J-od#Lyh7Lq-Ie& z7Q4X^_DU#nFi@*sHj~|uT;HzC;)JJ-D}lULv)q0EK=77w+(W8Us);c-#GQ z(y%L_v}X)dw=%$@;8zTbx#8TG8XvYpq`xRR zDkI=92j^W>rTn_q;0iy>!hEk>^myuF3>NoCLGPOk^She(BXQN#4OFAo3k8h22$6q! zo77fgQSc_O^&G+J;tm8&ieVXzJZl1x-o)!O#4wS*f zo$NVbIxlmNC)n`q?FJsDF;C8pH1?t}hPKi*a7H9?1eT03ZdUK-H}yetc@8!}BCi8Q z;3i%Fl%cq6CU1oU?nZkErAg8;0@P$=u*MGNF3RAy@l#BrTz-7g{JHR9!26e2SRVr) z;*;Yim6*UL^-dwocMa^u5$tOR+QASYZfXP7$|O$ShiusJ z@+2C|uvr2sM5wYOi;eZrn!UZ%y%`RnBG~Fd>a+ZFLC{1Za>3i{;*D~Q&pJQW?s92k z#s^zJat!IM%xuG|I-0K3mn_;L)?w{h;Xh-$JQM`Bl`J3vohl<+nAmZ(Th-yrUY6&4 zMw9`wry-kO+mJAw`Vzee3_Y*X>K-W{W>{bAMzR<2uL5c@_>(x@=uTHJy5X+Gb(^NR z$xzvNsUJE^Q1rK0M8-ZC8|LoVk-dG3ADu5eJ*PG2Kfz`nR?F*9ViOSotdcGn{+3r*~Kc`G{KgBxQ|XG!jRwQV=>$|CYc6BlP=*W*5Eb zRt7m?wKJ1v+zOydO=kBREi3c`S?IZuBaNe} z&QlTgiyn{Ki2Qtpgu^^R0h+iCrE6HJziYNOBfuJNCuH4^f>Ri0H8Gm|gPHKC5r7Y1 zz#OjIF>8a-3C4P}MWp&lb~0)3*}@9xC4dui!TqKT6^3=N{?Vb$R9hDpb)|$WF75y+ z2F6jyMb$*KMtO0qeYFkkG=KFgT)>*_c}z)I^AyR6yh#IM*OLxN+T63ih0KCRwUD2U zRfb?aEmJGjfstRpSML&KO1rz&$Kpqr;@cw7B8VHq`bqpKfo+A-`v#x~97K(~LZzb$RToDTr zutn|9z)>#>8H(spyAn-JW?N+UDX8VY-9xx!l}{Skks9qbS1F&@pXo?UURDM{E53}9 zT@K)ZUNe>yVSew6_VOVmrT~Tf$O`sMfw@90wmp5mKv~?c=6-1_lWsx8KAR5Sr1kF~ z4C6BrImv)VC5{LRlW_a=Rr;G)Wg=PPvO#TqvZ4S4BuZhk1h_3G7RY2x$wW>yTohD_ z640nm$B2rjU3}3@UNiIa0!i>bFUrKs-pu#Of!E5w?;kr|Sx0@dzSHunskWKfdEb}*@1kJi4T%od;&2i~^ym2u0L|bcLI&3c&UO!ppc9z9V>p-~TWhHdz zINr6VhB>+47g;HYP0TgH>0EJE{BmC7gY7Nz709ULxi-PEyqX6tDp^7%=l9 zvZ=s8C9}4x;6eh6$|X9bt51)pK^ooEhpas3l?I!50=SYsUdfLewW_IO3cvFm0MvXqGJv z$G8uDA26KGa?nIv*@iZ%@pn#(lDdHDd7i8}ivl|ROMS)o>8gpDXcbO)7Y=NBX}NxC zZ)R6Kb3@*#_Du`BVJgrT`!I0uNwosVSvhtqY&iFiDUP;Ufj-cPJW>&)x zK&;OzRBW7kD@V)x8hq>ERF*%4tR`6m5OT%-c8}E)r|(EwX#d`+-xlK08`XzTRc+%K zu6}g8jrpZaH~DGhYFb;WHrYNh6`v8(b@x8qX-4SV10Qqy*v*HTR9+R*E;uU3&^m3t ze#OM946Z`!hPCXk1m9=!JKHm7rl+0+4zS^*y7!otfP=c1D7Oyk`!#1Oo#7ocgrWt% zaQ>zs>MJqnab4R)AVjW>sF5-290;zJlr#N5p`%c0z$scl`;3*I1)rUhtn}~ zP6h-5Q1!zt3Ram>ecXaUId)}|i9U7U%59~j`kN8)I5#%2sSQUDwhxl#?9nZG&xqUi>h?Y*$z$=5oDx?|t;;N8{i>jeh-O zCR4EksNpY`9KPryYvV$1HHOk!hoJ+s6k>q~U~ZVZHpBJ{gkd)W88cY#7M})n^m0&7 z5@dsqWVJ1^ z!WP2V`ZBt~*&-C{)5lXfoX&-Jr>s#9T{Q;OI8Gz0|LVe-|AtPO$jdD{T+v=u2U{(z zamA?M87|l6cdgJ6zHyHGnL1o7I4WCra%$?}^whTGygKYeAK{|{o1Ep-;OD|*meIR+ zb`;#s7A)i07EO*JM%CC__;TPi740f01$*mDRYG0%@A#Sb9tnRa_D)Rm;owai`z{dR!k*4oeh4^Ypw*woW4qsFru(@|>_KfVfHpewV z5T#6ZzLs6hngG(N(E*zXL3w~1WN7m^K*~5P-Z)!dvY(r{EHR0*r)&kY>FNsK{Gji! zH>{2*Ipk{a+zyGyv7?xsd75grr4UA2;f8{5Q3@1!9DL9dkCU&AGHklOYqcvBM?s2Q zW{R9i$rZ=Nc8UQbfBbq&Gf+(yfguTA{NB8zxLINK?q6VLlOFk+#@)?7Yc~4`)4%3n z53_mm)vL(hq=(@M;B${fXUQJ+-`VhHLtb2T!Ry|#l1Y*ecFEno-($gEi5+WGhn)rbmG}=X`U#h>dPSjfP>Awsxg$)1TMgE?s&A^;_U_HH&lc9JsMp ztQDuIecpYH(i@A*B0E4-=XO}a_lbKPBPAD#uT%5D-lz)MWnhX^VAy}ZK=74>A)Dyw zyOGm_^;Eqt-G4PikdCRS;7{_h_N_cy;1;IFCJApw4%CUob@@8@JMKs_uunNhM$0n~ z$CEcK)Qf;yR$7wRou=jeT(*8wS3aC_!cxm|oC2dKR&L1f;e@^EYOk)BeB!O(#wwFi zD?&gbPR;`KnDaSpkvH*9=wm>;^+8}O5v47YFey+t7YrKwoA@ek`&eK9m%12eswJ73 z3q}Y#Vy;daJctL6(z`g|s(3ilJr#W|I(LH4Zel$kgMiALzq*{C4M>bIb$-L7e!p1> z813B6dFH;yDR#vSnaUyO>vT&foaG#%3oQ90W4(hQL)H4CWhuhA0je?f-?ZPV>Udv4 z=1FlZ)kPlW@b75GVsw5N&gx@T$b~3GeSkg-ipdo}?x_IP9a>t{sY`GuvfeAG!5>aQ z`>*Y3>Qe{P$U^`zcs(wAnVG)oyB?@2qX7EnFAN+e{@X7^fHShyGK;IS#C|v)4rz_x zF@TQ3(B`Oz0~{OTNmHT<2m2a>FX9pG<9&+*_B@E63ge z9?Nlkh#_dj=#>Di=+UC%XNPR=Em#8WU!;4M-}~jBf;ZuG=hA=mTU&&C@y(h}uXMVG z$yNslL!SFqXZET%8}#S3u189gyn`m9`1?FUI)HxftWP%C!Eyylu z9~NHBKPutL2LyjnP>nh%Jhi<9U?Fy?;}KlN2?(HInjR0S0mDv>Xt4vN@6AqO_rk~Aqpwh`2nhR*-T3hiKoe6AnO!i5nc(m zbxouVdi?B1(m5S+ey2Yvx0kzQQUsx8$%^+>gYQ7(%A`DX1Fgj!d;Fd)= zu@Qm@erdV6**&`xrdoaDH)dLxJ;fz8@1Dy~3nh`27ljc-R+vB6v%3fmn}8MCtUTH6 zMz&T_4$bj*IK_T1w&!e+Q8LEj*;**)UuXE-x&@KAyt3lSU5S{m$CSL&ri=%BOtTCWTH{Q8a&Gi^k>i3*#mQz;?g=yQzMqwgp$2m(!Ru2} z268tN&7;{@ssd@+oSA#ZGAUpDjH5^ zAM{KGh-PFhDu@8S-BwR7Upw4>aHn*?sr8jSQhx4jgN;JZ@W%6?Y_F(BK2VZhaFu^X z6i~PO?`1&gp?=uaOBSmF5&`qII39{pj%HfQ)WQ@A!RFjkI@B@{K~_z@)Q zL9iIbu6#|sC|8K=iYO+>8Q;*^>-w%YJ2njl4wi0&$;I(+*C`o6TPH z)4bmM0-XXn^u?e!A`SwN9k(`s-RJ23ZOeaOOX(Obzlq-?m03|9Fd9kXF;6zQnPzdc z$3wrXlK)3Qf)a30717AUTff#Cl4S7 zlIF8vO(8PZdIZtt33pV!JXYQ37nEHne;0=W|Dg9b?7e)Z!gZ`b_9F1d!FR^)3qud? z{jv@=m3tH1r5q7Vh@=yB{WO@}Yy!kU>lWtB0Am8-1|49p<1}H@~@(5xr}+rAonNI;Kxtz5KQzlutnv8#CE;7fxADu* zBO*_;Q*Waakfq~g&+D!41j+LtM3!MB(xpv#I0A{9aXob_v|=a{?wVS~S|%%)c=kJT z!`|4F7N75D?*543ER@P@On$=D)*w8!2HRLeP?ovt?fWuzlYeb8pggr$Dvbd}FMWPKIb z1Y_;aGsoVS3(enaAH8^>#0;Q!Bfj5`?$|Q{F;%Untp&Bm5`jxTam}(lxo>y-6j-cR z%t$i^SYqT2d_5f*J!DV!V*j}<1&M+m@i_rjYatIsSlY>X&g_1_wt9kD6TChhC!C|i zDnWXy{U**u{UBCr>^)hNR+f)Bl=EbFd0Ed3Kn*#*zXO(tSJ02&5|3ubpD6VmjC_(% zoW-oG^mJ<=$##@fe))As34c$^I4fr=K3VO2#@(AK=W$zCoS*dPqQeokpTJ{*XBpX4Jx1xwq&6>)S~S-=~6&) zuB9{p*5m3hNwmJ3v&xn3_I^i2pR=j7UkBChM*g?{fB@9E;(!3GO`Km&ajdrH zxvTYFlm5<4A2>mCGmftSiCa$}tfG^(Py%L3VuF~OSqPPy%(38ouR05KpiskYQv@q{ zKnM3aDGy)^8sECnMjUHVA+^4)O$Z)13c;VHt|+&}y*%K(J)+!dQ5Rg6ma+C5(ORM0 zI2*fK$yGcLu`y;Mpz$6@|%G7j7e zx#((Zu-&T$!u?$p%BtqkY$`^C*DZep1Zv4yqwNW}lIHd_W^=HjpmVak#gcP$5}wMJ z!Ghl2>AJGu*m)ey#JmBp+m7>Clx7jaz2Df}%&zC#D6P(%##S5M2IGpE&BwtvJnj)} zBij`o8Ps%J9}s&d)sxS`PY2sue_QcDX#oD&i&D|OKohUuPmQhq=(`{l9Ry*HD3Fe= z6+U>pVSDN`A=`69MbXa$8V+oTAN#GBtzH5G#?zsF$CF+uaeELZj)VC()t?NEd@jfV?+Dftk$-F}ETr^JCR#K@?EOyL20Hvw6g6M*n*~2eV6!PuGX8Hz)$L?!4@F z!A3kkTOqjfnFqsu33!4+44)SZMb|fcw?jJgp0Dasg3(8vvG|uj!zdr@i|BCIu(_lO zK=tMv>o8tc#RA?oF3s-TLKlmT2U7H4GMH(c=i}*8jch)xN12qd+3-#117NjbRkl zX8TMhSz-0oO%NSuxr1_BR_%c6FZ6ZGcG(G`frzF{Lf5MwCl)$)G!omh$}klUBnZ_; z^0T$;8Y}FPedgf!j(vEoPKBzR?Mu&0C|b+Hn5n1EbC=LGWAbW1(DiafH>ryozvEKx zMqKsy(SL03>rLKOS3P})oOIvQw;61i<e2G z-QyCO&WLq1pD7^y2ctMuHa3`O4Hs`-@RFLFBZsM=1+S)fc3_@5p-N!Hd{WvxrKC<; z3WPb0u06%L+knbZU<1(cMa4|o7OX{hwpJIOJ$@Cu_m(GM`CDF6tCh13+tplk5^o-y zVamoZ(5oULyh8-pt$n;yx{aKU`$wMQ8eITJcb9a(fINgev#NDcFJ>0^B*+KgYsnqx zt%G-UTz=5b?s)Gh8%jtY#?S9wV1#!()N)Y%MDN?_O?PIsHNn$SaIBcyWJQ$)SDb)- z<-^;%1aDL9x5N^x22YhVNZuwEUtJRt&awz0q!%GfZ8e*rMF_ICdzjfEw#%N#LYH8w zYIW`=5qY@Gn+6;z9*>Pnyij|#lyq5?QU&o2nFGbZF&kC|%BE^Ls1#~!%iVH4vyKfP z3W$K(oPVx~`QCll^IGO%Rh%A8R~C=!T}E?Ty@uS7H@)b>NSx#S&yev^g+N;7n}ZCr zh_AXS0FdyD3+2ux8|NS^uU+lhNj@CDZMUDuE6q_ba7+acIuNp~oVHVxT`cqd=)7>{ zhc|2PQAf$OQAZtcvOWvp9@~uu@HIZ)^}6UG&q)qw{|N{w)KfD^qXNTB2aI9R97L*6 z#~Z4@mNHa2(bQn?k)3(b7W*vM2emqZrUI2j(-fM3_KG@EowKJe4uY_woGU{Gz6quv zC6f0IxeIY55SFVoMLM5j&LZ12@nL|2Ig&OBWpK~ti1KLN3AP|t2VGAZ|K%T8dH1V# z%4I{P_YykmM{c1H@*M9+@_!XGvM97&g ztrwNH7M#evwGcAvNP7p9%F99RU;?wWPgy}*AE>jY#6OVGJ%NG6t)Fa!rF=m_jC&;S z061Clu-`sFpuGysrW~g#UPkp^O&9I3Lj6nDXP0emmmMBkbQoK0dZ&(?N2WNBssa`W ze-gs?VofkN0^Y3Rd?A@6?O>F3t-(~&eFY}#T@IgCX|CPR>YZaWFEJY~=$=uB7S|fb zmtTb+g2c?HTPuRH6{igvZ6-r7u4ma#f`W~ zTx4fvcLlQtj93hM>gkP?;T~%?$77P3y7@ki4diEC4Khvbfq>b`*)&X5OFzDx9-|z- z(s5!Ig((!&=l^G6>qIGe{=!XJ5kUfI1)fWAkCp_s(Z8BBPtX%hL;&(%E=l|#H4qAH z(!D!xhbeayAYYv1J@5ncvC=yFsNS?})SOQr?Fv;NI4hwAWC$Ag?T=Ot2AMk;+f5iX z7K&`vUt?GR?$IGAI+()rX%$`4XxEkJOYp)7M$YvS!I9giJ*0SE!F`!LZ>ZZ-|MpS~ zXD@Son-VA)=O`jNfVA0BOYOK4>~OLB!yzpa6~?*)2#Ck1RlY#AjYZ{uaaOP~{4dT5 z238K1|B+NM5-_l`u>a5L|EH{Aa$TtKcL?lEUN~AWXv0;L2(Ll3Z z$3K(^;-GDSIBc?0VD}1ah)9%(3O|PE#BWqv0%_?(W!%LCDD?Xg?FUA}yqV%xfOUP? z>Jh}sYkFI~#OZ!7OXG6ws0tZS|ENR)=3ePi-8wT0XZC^qW~fk6lS6V{axyImumsmbJ40h)2&yv6aom0SZv{-! z;4DL-kU{zUP=sWE1&EZySP@918@`uP`t7^nLt=JK(^~g0=yH_@gyzbOQ7i+ zxhR6@5y~Ps>np{S7^tFOuqU z1WX(+af~@(nUF+Oul7f}+XRXuUUy6VA^U;uEdj8LCCOB_i*YBXOQ(&M5|fzI!Nv(u z;mC;{)4dlG?ag6fAZp-bWj_(#-9?PP05FM2#W#|QgqTe9q9+;pF&UGjcLnS~4-RJu z$R|^9v@k;}qxr$6ET-wB2~G|k|1vraT7X=rR4|G|b$Ayx4sPSI6fpnP`sv3g(hYBs zLM>L}Eipp(1Hu7QArS>DaV($WeHZ`}oCZWtsW9d@a$!=#+P)BwBxJH9lUY4@2$w;{ z4t9s=6b ziyOof+PypiNLVX;F|FwbnTVJ6wl6+Yss+(7 zpUr8GcIVvlh^yvuHxje1}GbO@NNX~6#c{8zB~nKgCK0vFo4*W?V> zB5SJhg8gG@d1iTb26N46e$`WH0ROKU_nd~23)QRsaj?TdE3-AGX1Bv|YvTtEQ?0p+ z^rXyeqiowf-cch*Q$57 z9ZD?@HKVa?gRhmd3Io|%uicfzE`@t!RzEjq?w;XBjkUsTi4T98JL#EcY+8sz5RY-m zaN)J<#A_0BB;=vShzIjV_R~bz0y2@uWV2hNw*VB~3(HgFDV)5msP*OTzG1Tqwy2e@ zd-IJfXG3uURv~6i@8^b?4Z6GC1gmUy1F={dN`c%pQ>Ixn$31*?|IfwXF!Eu&r?djF zDNs{wi8P&r+v#p0zaJyP>kw^>Z+8B`Fe`e4w5yu7C2p&*0_TkGlm_CLNdNO0%xP%- zG<@+KlJK+rVyP(&)3(%i?^rBn3e6$jD5v@Lhssd;r3t~ zPR8Qp-)krf`6}YOxpcyp)$#E;3^X6tSu6M_<_+-97iidn)WgcJRA&>6uT!UJ@v{`i zbwrk^&5U}dP!haL%-=&*`;v-4z#5px4rwOi4#QY_#l;%cgU;p0#a<5?FAg#54n~H^UE)_H56Hgt1*03nPTnsUnK6gwimJCAwsa0N z$JV{m54C^DS#)09yfft$+NkN4K2V%3NF12lkM%Qish;DFOJqZL5hT-g%ME8qUhP+D zYBt*)w|ucUd7WG@VMSZC#Vk$CMw`8_u-CjU`MU*wf;RTEFMxwP~!JMxf^i+%!6yn^YaKSAP zUtK$GSe~O{!!CThge%aATyrD7t%JTA@+O6e8_pX4^T!Ni-~l5q@wB()*d=esj_dx> z?Jf+7>;}~u3EJZ0i=gDjEaCgT{J=J$8^Ga)b-->fOX)!JG9&J*1eb)!E)VxnR&3pG zA4>G!UaVS7(8*DoeQwOwe}1+jax}Llccjkh91yElSi@LtKXG!~P9JTet)+1>sGjaW zJ?n`SUHwLJg5$Mk?p*WuU7DHtycJid_2_i5YKX(dj&~m?hR|Wy*RE8;bGOH5DjCj3 z+16_NP21UgMtVN6=IV$D-Y(V1DyfB>pQ=HZ?n7GRyHXy5Cm5;cfox zd?)TF#VB|;+hH?_<~Ho_pZNi%TWOU3Zv^}w(-PPjS`u(`{}1Id5HK(?{ePM^MgkTN zrvH_IS=pHx{$B|=#u-#O*=miIa0gZqc#*>yYB2|xh!k!bKxn#udY&MEcperh5ovL! zgh1Raiin1gDlm953~$b3@9F1H^RF+r<<#T0r>^JC=f>ye;FKN=vWg$!RbB=Jhvpv{ zP%=1%zcS3QKLCNeAP58s`ROTZP{B^V-&RD&onQh51`zF^9s~;sN_1~)MbJW@KLk7f z+7v7S86ZMZDtb}^I1u0=fByC!KZqh;KHO`l000;ffDQ;wB+;p=ko!BKf$XfgM?YU4 z057<&e|mOy^!%N@erg@Mv7nv-dbau>mi@Ptf&Z*v$N=w| z2l&1e;3U()F-QUf+rADcKPji3Gg$WFSc5ybP+~>lemiowp~0NmZ##0&bM`t15cux> zd*osmIEU|1V8c^F%Q$dP&w-cae*@ZC;eSR>frWsI{E!SB8Vmr-$N(=c_GmvU{nK;6 zpIaYW-ZO+0{lEu+_T8m`uz?(cb$Y{q6!mN<{-T}&K|sG-4|m87=@@GhbO@ zZ}wj->-*6v&5`Su`e`TM4Z!ye0+uOch zAHP7~_`daA(=&H;!J%o`C?9=*X!Cuo>i|#z9vy#nb#PeTJs4E>v0(FGzboql>GkdFNp&Ay?rf^2&e(X z^J|0v@N~`y{fGf1zbr@^8vf-$Ov?i=X&LW&6}a8;<5w*oJUv&PetCX(6eyR_E(E%n zV(b*b9m`=Zxhs|QUl4XNd$|X@jqZbVIQ7BTkDUbM;zxB89?x(dm5Hp+iH|d(V0#le zCa?H_Up6ry2{)8vxM=}rxbH(u_qOHKw%D$5 zv~Im+Y5zJL2xl_n`cmzNsvc7o!arz|Zm=wP67Noy1|3ctSPM#;wn1Oz&M-J076z+> zftK^UDNW^M&B~w1{tsi{9GgiP?pxcox7fPj2fCmK*+CpJ@Yb!Ej7RWgJH{Zng7QUeYkzocH_)b5)Zro~ zK4wH`+`J*_s;tv%sUYqQGhahZ(ZRn_QPz%XpB=L3gT)8ad3uR;L?;0)?vA{Yi4jel zGB&-_%t?6)u=kNfA=+)vxuW=UWg{UK>gWGaapx!upd^5T0j9n4qywor9b_E>N6(>>CD#ed>4aF3-H%nCu z#I<#J&;`9v^Hg1-(e82?LkLV+HMeC=2q}=V?Hq{~30LWO%2CpGh}!W$&BtjYE6{?K z{jD{O!E-~@@yTRng^=J_%RqzJ%aCJ+&W6j38l@qNf$%UqyBXfpA?9o(PI7d_0%IgC zZa}gnHySg%dpIE@H3j4$p22ACPr%2k$Cl(NT^yHDdP$6nJEjlKL4_wKz0s`t@TSGy zj}CqP=#r$9*`exJXHth1VS-mrCAB1Vp-RUK=q-ZBY%Tqnij+ zie-#kkDhPk+12O~4HRHzFFW7ra1l8h=I~f0B&INn&Jw8&v7IG=6@^cCv! z4V$Oa%Y-DnRK*wiF<`>+7x{9@yuG9OY}ICxvri3k2q(}6irf&ZxP2xEJ%4m4CsK^3mtXM0Ca*8Zx(L(7x z`W5x)(Mp`kC!LtuLE4X9Vyv`#UP#BZ{`)6YZJ79}$QbY3 zKI5B~YrnK{9Jxm8kU!8I^nwOTg#z7%Vt?-oza)v~4U#nHEkZ|A@%I=X`-kMz{!N(8 zlA&u94ZvC$-=5Ja16wSs5O-#Ri9G`^AymH~OS+q$xT%<_f;qxIM% zjqJwy;?PLCa~)pe#(S8+uD=t*Fk?7lRAG9;Fy4D=2w^^7CoM-HE z#f8o3d{I0XVrL`w@WFMG6+Vr*WLw_Sjk*79L0mFHY0!uITk~ltA=~mQnsR%&KfYgF z;Bc1}kLn&)+X|UjB@#ROoa5KnnWP4&zi398eR4gc-_+@ zUz`YmQL+2(g8#flK0mMRSF{ltT1yeA+wk$CkYhB|N3?Xfb+aiVTh^hHSxnfn$3VZH z0=ep&y5ie*X|aTw;a9X{fmdAU-hK35IDiozAu`mcb(w(I;oZh-qrED-_j5O;mDjuy zy>5a)bZWv8RK4`WmX8d@$>OP$#Ldk|s0dSbm`R-9uS}1 z%X9lrLS4W2$4%K88QM!vO$74WCEM-Dw5lo<;_2-YL)BIwH=e*A zt*auvBGw(jNNC^rio!iBC;nAed&<~0lfnD)mY!LCWH$~_N%7`^0?AqhGB%=aNQlB~ zbVP$N_QCHwhz$`}hHdq?YzF&pI+@$PT30q!tggXpzspQjWBADL_lTI} zyW)%kSo%#1{g1M@#b#r&sLDlKB_rEm6?BCsXJ@nBUz`Uu7Xz`dHURM$s;+zLxDCRm zF&|=aH=0i=UA8{vWtZgU0^$qtnMIsY7din_mm0tBTnqy^l}r~Huf>$+FWK#T&BK%k zj2Dk^Qu)3VM>xf_M(nGwqWZ_Y^e`Inda-<_f%WQ%O*fcrp2zKlD>qRnytGZDNOzeM z+Tk48aMHRDifCqU)#}kuOLlI}#t--6aGC2_W@yhO+BZ@}a~)B~e)&9~+h^-;Rwz;f zZ2Jt&BL-funARei$c9$0xJZ+MO?AB_*%6;Lsqymxk2Oey3Acqf+s4?iMU!WKYH&`Q zFZMmY%0`9D_1pHr5W=RCkgI1FOz*2enV{KwZvA`j;S-or-t*lC~CE-h!#9eMC z1~KlP<~!Z!3&JWSo#&O^OnDm<5WY;K^C3ULt^W{@i{62$z1F*%rN41k$(vXrU_r&v zZwB?#LFI`-!z$B8{*=H%l-d!}O4+WLFqD^wgTlk23Sp{hJ&wek%hO?fF7v9iGgUu< zk)a-wQ2+e>$OG>@E*dE6Gsi%u96S!{$bR&=v_?;e_np7xi_-XEv`RBmd4k$4gcEj{ zag+H+D|zO}>SRJR??)apZkucnK1#U4{#au!mL=u}4O=xjgvw;0$>N8X z`If3$dsK7wMAnN^rW@=`H|~C*xN*)1wK4KyL5T$*b6+Z$_w@C|_ot;m74^IV?`mA^ zgwOKt`-3d4t90ReM5u?7uv(8z_uya3l@Av~_@fKcS-S>X$*%j?^$>k!74|Bx*Basi zY^zfMkANCWd`Uq~J74oWtIzQmxyPPawDlZ+Y)6BbvB2hMCBybY7qX}%mIJnj@YSCE zHo7i~MI5^2$id7WSv;??xLMNR*t|Nai9W?i$>aRpDEl-l`iHO;xp1W>ZEfZ}#Zu_G z!fNAT>Ul9Z{AEn+%-alC4mIA@ehk;yWPM zU)N^mpUuj?osS#WDH^#w8LosOE9s4)EoQ!O7fabUUa0JZT)yup%>|WP=D|qO`k2Kw zDPT$%(><9)Lj0`OTuTH2)rQZeCZA>{FyhAd98TTJHBO2@`7i0!IodG}OEPT6CV5{8WRbXm`??P2*>u9H3Cb>`$)9J04rz3Y^8KjNa zm@_lNgws+KR7k~2A~=H<{dFRI!K+V+Wu<5DO9fsdwWth)sNKD?FURYIvK_C{zbX7N zRT5a6qw}e{WH@qC_$g{X7)f?wUC$g z(Ht~Ur;i5KVIK*gpB)hDL8+^Gvyt?~eCX(O?{j@FAeZxp+2Bygbx`>?68`n9(mA(O z{+usvl7aLzClJ(Gb?eRB(7{hNr9=Q`LukMrgrdFGa4Z$RucwJh(#e}4c*mt+aXTnE zvhi)*%p9rfg=+xJC+0ha9yf@ZeR*YZdi7Ck;XOTvaakz3U6VMy^hUD+(pL#9^XbWF z?(!;-CH_Tfsc1Zz@xGnDD97EtizOt|3!55j>Zbl${%m?o3gOgt(aM_dAj%Cib;#rZRLaz8QsU?-WA z?uT4k(RPCY=kUwE%b{sm>3`EnkG3#t2O5T^lO=pqR_b_7EI8NV)Z!15oT={FvDFK7 z)f4=$T7;*47(eW=j;gLNGax#YS)C?nd(h1g;a?a!qf%+E@^OQTOQ{4(4BNE3{KnUe1QY=hEim!O@s!L8bu zfKk0KL13lIsQs)Aev{RZGpLF6OYSAn5)z;&!xt*HAVl59Ld{J+&PO(H4rv!2m~y69 zk*q8WSZ6fD&R#z*&Z2T@d=$L%G`&*a+bmmxHW>HaFB9GL^yDaW4}9En<0fq!B3jd? zwUa-- zVXvp*xh6X6?^{PmdKf)l!jBssRG~YfS#$0K+G7c*D9Or9l`EffsRFkSL#Jp@MhkhL zem87raq{=LKA>GSo?N&jBL1-K^=LC10Imu#v8{kz%X#V&oCx)&WOIc?mI9mZJk+WPT?ghrUdm6C;--Uwy3^Ohl8cg46wn{)(GA)A`Sd1i$R zjt~BQURVmS=hC*k4b2uukN5q!*YaGmu9?nZ`$X^q1CD4915zj#D@RBc-1v2UaB;=C z{TcTsW|^Mymq`_Jt;%Gz))VcIG4!d8V0_-SMij$o&0;NBl9Rh(`)Bl(P$TGcVRm<2&ql{FG z?l;Q)9)`C4AyGk@?ZJF0bT4>}3sG--2AylvjQO_`!RmG7MNPlC#3V~3Yh2=`D3LVl z%87fGyIwb?ZSqDYf4K=ou@*$j@4z=d#hkOR{rz};p}9uTxa4H>kDoe+{Bp8)k2xX_ zr&yL6#VK{RN|+L128DAvnox=(s_0cqsksl4{?8R64OZgYv)-YfWvp(U&y zr5867XV^?tZ%7Ghr1~Z$pL{bR#r|`nCd0Lty)JsRMMA|I06bGVcjgIP{_-%bS_}*! z!#j@MgCh-7;2wlUY}R?9bURVU7mO%O9uL!Bn==kJXyFw$HkxaDn6%@|F_x$B6d3T8 zDbP|0o=hMA?LTV3dJrU>+n8%aW2dnNMe>8gd5#S4kqpJ8TJ32YPCxSzka7B3x;dtv zrY>t>eUpZ|CIDSsH!kCS^`c~Ku)nj;EOW5v-1byxT6ME#&?(mBb*e#km6j@uiMDv!}nFa0YH5}>fH(>&6Y{{$PQOz;L zPr2@tUQXnW%8N0sVWDDY&*^QToB9BnZJX% zXOn=^<5{`|6O-a^ii9{8FPb9ZCZtD4Vf>$1m(Ghf*W{OcZPzEq$hy@TKX+>x6U|!n zJ0)RZ9{{FP$9&^^#(O~=)KGP=&TBfa!G1q^%1dGS+EtCG+a&w(*IYu@pJf%DRvIA6 zyfGMf@!*v7kX6>$9UkD#8UIdkO44gH3I|iV%Lu@fdk2Qu*<^nFedf*?s5D_v_W0{5 zq9ru2hGDp)1(?+sO~1Hy?!~iUvG?6QLxen|EQ3_QEtKcw9{fy~mOyTYH2Q=tMZ*vM zp8zwq{}C`_WBE_`jD>`qo#TH5%sAMY{`Y{HE99?q%Vm1Cj6AV$Nb1Y)1?i6<7=$nw z1t&%d7-TpPCL9L!r9920b*_eaZi|flo4IF~*(VO84x><;`h5?afps)?-|U z@xX1D-5LiOX1!*Eg`Y-}^QTE51oGl!sNJqEua80yJ3 zCYQl?kAo6H-alY|*PB9LM?^$8e7Hc5vwx zLh-c|X#tk0?<@o(D(B!mZbTQC&-`4W1W81xHK;9t-KsWmOz(9OR?fF3jzClis>n(#%h92L6FYyPz*zWkf zH>y1D2~Z@IkNlk~x3Afqhh>eLk4BbrKi{n!@a}XVlix-5Z1XPqVSV@8?$?)|-xkAH zbL$u8!57=>S7vND6~^oO#N+y>?_d8al#(mrfI2FS^P4RQtg0_-RSB@G zWMQI1n2&ZhlpwePXoR^yl8ekw*(qBBuV$pLN7dlfexdG1aX}3Tko#+p*WFF$i%SZG z>!WUMCX|(`lM5tMNNii#wI3Nw*7|8?^az*?-k# zSyx&=OnKLM883|r>(uvyeC{~o6bRiE0AC`h7aBInpKHG5rC79OT$(;WgOuM78y6NnP> zmB-a;p=P_fNnZOtCIqIKO82QRg}Rp%KgcQL)3MS6jkiLs?`}q^;@@kvJ)({>TKw0i zA-0~iy|6QY+$V`ZFmuq1c!`7F)JKrkgdM1ro*`Ed(}XCaZQB}hUUCc9uWD- z+Jsi53#OHx+_85x)w<@f6+Y^R``YfQp?k0y8Td~%68H8OKq29Zox3ejROmWf#|zX{ zcYoI}`Mmcu!yUEyc2>X#uhty4`(N>+P5w^C%8sFIP+|T%0D(NSBPY<=7VWQ^w`n`0 z58Le&{|PuP9Z!(9ybp%#x+NimX2V;WgxJoy-zeN5bqLdo5n0b@qIJuukGxx9JBLJwo&HjoAIp) z{Z9xRf>_}+kZpQ5I1TG2T&k4JGu}rS(Sk6%# z7;W>@pprRX!Vi-v5^_QMSBv^_KOLX<$Q)YVblR^J6U6F?pr)B)3N#Zobyfl%7Ke*$ z$b@yU9%0A`S+k7AcY!}gLo@`rv>C3ipUi2 zFr;`8DhkQ?`<0R(W6rX{lsGPZ_p%proDFA0a6)lV`r;JcyfGnX*Vz@6!+$8Q4Fy0% zi~B6f?%-FWQh~#{1aQYSjbTd5omO_}sKY83?t*whC!xrMy)@L8oWxQ(j9I_()9VfF zQ?(2#*@#=q+{4OFwFvnkj7a1Eqh2TCQrNnFVKU)Q8J{XbR|S8j5fgSft*Imx9{ze6 zG-LbAY_N6P&^(R!SyJgScXuQI*s>V?HM}8*ywDuPUfpmufoE~FMUoK3w0CHUCCqMAm5Vs4F(hzjI+|~3>XqUiB~V$9Qm+?!IzpEhaC_QhSG}d)d2J5T z*3!LoKPaB9{|T-h^~gNuDmHcz)PEw)%FMVkub6Nv{fKL`F;yYT!e=C-YRq%YYPgFk z(PkY8)+gXMH|GTKmjWYzIoq9Rw%i-a-DmKGuY{PUACgE)JgnN~U71TOe7b4S{nuqZ z=Q(;%M?d;(=&Cm-o3X=R$Rg(j{G3l15R67WDQ1eag+#S!CMux(!Y!F=0N7j(AJuEJcCa zZs!~y8@_sBD5+2584|2vC??TdlCK@%H1%Ljogz9v>7`fSn2)aI{p8n?UFs_h=cORb zb>F=KDaZccntB#T=8`$NW}9YuYRE-UkGb@k5^@BM?Rq6p_?t@OUU6-w7NzJ1D$94D z*hYbTFgul3P8askS6sL^F_A8sUl~ z;-7TgK5eGm6a-3vJ7pfej$=S^fp%iS!bvk7fRMMT3ARk1*%*1Dj>^tSE(uOiOwrs! zQ7=mr!d!#TBRzYP4SnbzHc76*_t+`F&gH*tHEmMU|LGu#bZ$9ec4ry6~#B|q$oGz+s$QNiwfa)iONh998BM; z4ObnIO@`laf|-p(-ByX@cd@VT!RT#TMQvBX_Kk0%3ZBd&hmGtM8_S9Tfpq%LWfC!i z1M9`*TMD%pTN>(14&0vMNzlXqW6*b$1+^X%NnL6Qg3(@kZdlmmjj^c`ecs_C2p=~@fc7R;RM3=H>^cv zI30d)WidBfT<7>|A8K-wvh8_NY9#bSXr1ISEoT$16rJ_ZZo-f?Ep^w_kkmifUCh7| zrK87ii`;;z*rTKhXk1bn0c;h>Kb)&sEDZs0w>qOI^>w`__*w17gaUPZRM49Q*rXfi zk&Og$S^v`WBdFD9m^!?sYBucJO?Qye4L9NqBI-@L=^C%o*{xqm{G?d!?@nIg7r0Ec zY5H|CSiq5~c#c4knvK_+_GaZGQY9l)v`0MO-&({FFE(nJ`Pkhj5;l^R7H^f$;~Y#7 z6joYmG3lMI+U2WFrBl^@kVN%;2fgPDMTvG?jm9o(Awx}#F|YTUjf^XX6TjUvRpbxE zs6k7k>@i!`I1C&`EOl`27x(NBYpGSIh6Acau|+@w?x`aEBeL9f*3w^so#BAntVAuk=YLEd%5Px(6^`IDMTj;^Dll9 zWyGzTU-yc-9G_Yp10|nbIzQ5%oDMR!VOGs&Yg1w0-Hy5Ky;1~teNcE0HOX-d0I4(N z5th}r(ueq>)XZq}N|MzFW6i^!-CmvV>5@lX;VjwLb5M*zA9>z-%LO~6_2eIFG_E-M zN>Pc;6)bP-*?Ps#i&oe+LV$SyPna~T31e=*byp#@id^#}*w@r? z6|+0crVl+y%yHg)K-E=E=8@o;0c@ zh=WwqAyu;#p^kbVJKNWYg}E29anEwIWLgu{8?sTg^cj_S_s#&T3$rHVg#7Q|gmblb z8wCH_vVD>Dj+wBwuGGyRM|6K`#7l@f4wXm<7}_PT_Kqqzn#zOoQcSpKANdbN^RMVJH|c}Krn+` zhBi)*V-w@N+T$EuuayKx30SV@6IZ8Om2GaF2sK4xF^2-w8W zuI!q$GyaRZc$&P*Zb>LKpG5yu{<5(l%4u1sA&{A>q1md1-Xwum{3l|nZiKS<$$lI$ z!0Ut13apAQunbKRP)Nl1;#TVExG6qyaRx`9K*d!>%KWJ4GA}b_A%3pJht|1fF}Oig z)i@j<gks14XS*=Nf8wM2eGz@e%MaDHx(}%7w?*R2`G3#vxg@c{FilUJxrtzH}Rw~X; zj=&ot4&ZuKGoB{;oRA5OkP;I`2VFQMsUwl$WHJ()wBjWNY$;#$jMMP5t0S6a$x#SOPkIpBqmPCSXcHVB0$=*&au zqr!(!D}!%}(((Lm8YDTl^4Gey)x;sK zyM8P+Z`&Qv?B30kDVE{h0v-1tS|iQHLWe@N?SEXZI_eDK;Nb%&Y@3GGFO@EJS+;&= zE1CkG&BVNC+1A+YJsnu6>ST?vJ7st{N&j%N2O}zF9G3U0UL&OimBIU$6W6S83Dl!k zq@wCAi8htvZ4n!x;(4a!o#?UK#KGO@!?kxbo~d(s4O)5Mc`)jnEWV8CpBiNc86i zQIs0>k}X767a5%eAUiwkXXy;)vTx{@!0j|InHpvcE~FNRcEI&hiQzoW4gG?nIXG6e zS`s5VJ73M$9E4OWEyxO=UCa)o1_t3OmQ4!yS4=20E#6~=9wWHSKH1}=6s4~ z)m603h~}7A)q;%}#exxozm0eVcvNC3?)h$&A`p8fa9LDMs~-gsDUc?{9)K4j(_9e^ zPMuZR#=72CRrusX3y}$|!TzijUzCOod4IV(?8XrOga+-Tai}>;y0NteJu2YD%2Wz5f8B0s6}^v% zJ&?P;KaO$!uK1(<Zwu+ipg8_Rm~Jd>WI0B$>g1w;H}=tIh-am83>w(mS|#f9$?r2Dn# z*R?YDj#A=nTF1Dg_PAx>^Qi5eNc~0usG9(bzTcW#zAxF81f5@l6HbFVmgXpXQ;~oZ zW+=bf;D+3I8{z7ArjVgFTE+EXRZO~z%#Ekv=^9O4rFNI$fQ&g>=vdXWm(e^ zA=XCQ`N*|g(96aUnu+y|TLO6-)VKBX6&W|tntsueEF>Htyl^R`q-!E$AXqeq&DIG1 z^fI7-cO+Ob&7ZVpx&9CV0IMb3@UxcNHXhnfAQCY+Tp0B<9{Z6-O+gk-Q=PR(8`1d& z7Vl!5M{z76hC$Yx^ak^ZN!sBhed=#pGQxZAiP}>7iW4HbeyvFuC>r~&?q)6ju(jx# z3XnfHK9hm5NVy%o4dl`sdCNVd6?G=UR|^ExGC{abp<(9q_p1e&o0ag2Qe8H<8Zq!h z9m4jl8O%L>=`M^NSWtkx?+;jb>5ic~tT0SKCm zewM0Y#xLvYb#|~Nxs#DfJd?8s+VJR%KB8DO)w(2qbrwFg7zD=^=A?lxezs@DkumB# z6uvkjrBFKJl?@E^aKm|~Pq+$o-L$`a0 zo^->R7h}-E9}kKTL^f`Gk$pMaO}ol02RsW!Rg|GLF#PCRGBBQOOKj($=3|gEKPHx5 zYOng9Iv}ePR@q7GpZoAuB$!^H6tuwwS_AXFHlj!plHE1gXnom;6>E4fm)~UkHJj|} zdiqe7)tvjnv$-CA2(y&v#^^Kx7ua$S!)!AScujDc5Ycs*{C;bba_IBMG)VV!!ObM$ zDYE~SPcZ%Lj}u-EBp*2}bj}6PjhkQsU*PRXQ&Ld03m%9#bz@ApLZV3JZKbAZKyY6k z&aR0Ql1Bf>!s%kw4GAa1WV76pI0o)qwKyX6E7gEWSNo**6|KN-#6-^B(!ik(dNuG3 z))szF3ZwA$v{j>_zA0jCz5#{|EoyXEL7KYM*3?}vat-Btdc1yY3#tU-!qdyR?`;*q zkY~M21oqJBAX3Q7jm`z&@izE;a#tvcYjCI3fnf4_q{8NZZc^oRj4<>PomsTpWu_t> z2B{mLjN6vpIIPn2SAM*9>ur-l{y~}AEO8t{(k|5eNA5v{dZRX>_w1c1MR*}04k;l; zhWC2yJisFscWeJ8O{PixUByM-kbZ2jb>->jIpMrdyPLb0Vlbup$2nC|YzR%$ilooj z-W?1UOZYJ7>sC4J!PzMPh*l)8sgwk;gx3!|JZY70glsQ5On=E4FUp|Vj(23>xcf0i z-5&A{^6WfL`3DP2x1in6U1skzpZvXuapF!L{(#ceI2J1Jb{NE;Z^5Lw&p!`LXFtUh zipV9V8|CEGs}GC3CPXt+o9uR2G=$KVXU40fCgV4l8Wh(*Fl39pd(g^f`_{Vrc$QznLX4DpdkFgf)3eqB$N8S=K94FGnvjC#l;JVpNvw5O?-< z7B?6eqOf>!iLZO19mdfV^vcq6;eN9!dM)OxU7tpR?N7ZD)Wz!_R-uQ&GFZKpc%NA5 z<0zx2FpFZ^7XNiD(*6Yzp0+HI4--FD_1N45xc_o{1Ki>3iOeg|#hA z1{nk;_+c~!fxh6_1T@86RD?5f6D(OmbBRvyt`O`mUN7Yf(Fn%5Krp&m7vG0<_T z@1x64oPM9H@4GzRCX@fkH6<`f*PLLIAIm{26mLU4;!^XI4t%mPkiH{vh0ljaXsqTk zzd|&8KJmEC2_SK_^EVUxH8uI!6=M5I7V*Z<6 zTjM=ftxVQW=ZmzJV;B?JdWxMYD!U8spG$B<86s1P2}*MiJuI5f=B*H)gYoG&(k(Gg?BZ&*p z!O`5-hJ=-Y1wh02%fZ&z*$C)BZD(xqT~E)<0AONZ{vMD4y1Uvs7&}ta!2QQ9zpoKB zZ~~H0i*mCtF$0)5|L+RmU}d3a;-F$;qWZ3rvo-$zm8duv*x3P%Nf^ZqtQ>)GjK5UG zG#JF4t*i_UY;3-Jq*gIAcO?1V{-Yl{61D$oml?p!#>K);&%(g=pKX4Zf6r0Y+yzMT z-4iRLDA3T{z=nq8I|0wh%n@ktUz25LU}j*Zf#c^V0ooXU%TwV1fd7uWtGL?%Nf;Fj zEtH+C;TYvfI00~s;^q#HP9z+F|MG4j0kEtGd5}MWv=JPX%dFHXLi(S0E)9xzrbv9G!va z{Dwe_SF4|Aa+tCQhRR&}>YHv(A!8g>bE+_Mf5sKnv8-9`a0sIMCAG~h?b4r6=m2lQ zK_H}pW^_RsCw~D!D!2jma=NK1dyhjZOL!QQVN=`Mive@$m<0&SEq z=^}HPtGDT#)q4ZWf=7k>>-|tja72c#?SI>GQQT|PgtEa-sVOF)kmA5h0aP0(f_{nB zRgxQK{ZSc&a?%~RK*YnLhr)-hu|xofA%r4+r+AL`2DeE!Hen)USfDgCN#j8c=(89* zw@~9wjEgD%n7isBXX`~ESSel+lnAOmU9)s)szRjZ!I55`iVq4~iXz2i5+`J<^~1D- z=Y)Pv6trK|8j6SxAQ2<+S5P?gB`u&z{MTDrUX{)L_P3LqhYBH=Mn%=8 z+G#)Wmq_HZP`heylz%M~^ttDFC`&ds9+ zhha^+0dXPW#8~lPyLu^=xN_o64HZmpQ39fv7L{X99D?M-&f;kHg?ZP9l7#5;?b_Mu z{e6zEip2Kyu~Z?_I%7ncQ5n)#t3}v`I}gaoXkI4Wp+-@d4RJ~Hg_j2(kM&W9L+hEC zCp#YhU!T%w3#XN#b8-w?^a*}CFJ8Z)RXY|_O6a69j9}K|gBBp+6IBAu?`Tdrlxa3@ zFYg?rDg~_fj~BCB^Bf{sQ`3t`gEONC{RbsJ-nA#pFG6&6oNdWrn2_f(sLC;mW`&!s zmtCIf&4L>7 z8vfjm>jk_?F2|u61)@s+0OXb0(-%qd@sd4@dU%uY#^KLhmO?EA0~P`DvC2%4@HU7i zEHf)k^{A_!4J_g&!N#zBn`FDCYE`2eV3~3)%bW^JNE_fp>`$WqW_aCXx%9NctrDRq zjPNDLVEki&>|~Cfyqw`nm)c%rITl_8X2+E5Zhl}G<;IWbRc=O4r7+47bv=Ad6Q1}g-Ogqe-A6-^k4qdP`lM`9M% zlgmJmq)m<})KQ(YOXM-f{tomReftq7E4&QAl)&w?XP^OE!f>Yty+t)=;O1FUz4%b3F=( z%BfCirjVx>s!ur{bUJ&ac9T3RH%ppN1qsVsPhB7Mynp$Ye3jFG7rzt}kx1v{SG zNZct{wEUtvHRe>Ns^2*&c44*=VBmHaA30UYG@KR?@^t4?F)dS_kZknTMIJ8uaNs7= zD~mZL{}g|I+bE0SG%a;>=C`y*_*)9^d^5c$#-m97Q2bgjWU(=IbgCq`U<@!{+<(1= zs1QFwXH!*n(kZ3oHeyCk4uUR;DKb5^@ZwYVE$yya=gM>@k;T4P9o2xqeTT?vxAmi4VPj{KnaYM{Pr5R2dl=;(tCA- zXnx#~%Gx+-Rn`9pjqpIK+uF_9`h32=e^Or+y21L|2Kc5R5#YVWW$$O#^a~)@+HJ)m z8~4sColSJR%SCy>)4T~LkLstNYiqbBFn=`T+)b7b+Y)z=56L#;%xkewojC8B3faWOT=^lmQ2yS2dU5=P6 zy=7Pm-A&Zx{t24w!K|Z0@b2i&Lb#=sB3E`v=^_b% zZMsV54=9(3qx(F*j|T1}Tj^Hlr>%biUj53j_@=^_H=87^Bg#(7vOkKFN&%DVvOlad z$GrS?ksbjeZGpM~;_OO!YY{LnUarinD9R&0BJcN=yrNn3eR6c;{y=L>b)ppfxO7BB zc{H&lnzF4Sme!4g8!U-iWjzh9FG;-Ofl2o;mR36YDx{2V&UMGll*Z8{e{8y`cO@p{ zy(QInpuPCPOO`IM*0v&Eca>Xh6kC-5Iyysu+RI2WkrdX&K0$4<`yMQay<}Mb z0J~++1eWM2zrhVfArmGRy5D_Vp~ThdNxd(9Yy2kvizhr=_t%w# zX+#89_u^hHp}r4(vpwiVUX!SI`d&>&dfP8-|qdN``qV#xaWVK^ZW9=-52&l zsvOGHIIz{eG_40NlX_T;-Bwy{)A4F`>5;6GnHvua_O20F#PB?O@UHg~Z1?$`cb9w| z`3X6m&0{pmfBj7ApPM~P)cM?Lq=)lTTMS)#L*)P)mAJ2Tlkz(w8)^7-K#uk8p`8^55H?4i2PYn!)O=)y(4Or8LrK(V*2P&llo-ZtK*c znp!elI{gn-)rDX@diy~7l=q92G_$h7^U+jKgSa5n4pv&@b=P2L>Bow1{)bQF+or}F zb1$k8ljQ1Y^UR^np(jdUTja;(Ao)i0u(z|8lkS840nak6m56O|{X9oT2p-oV?G4ta z1Mc6H=<9x5P#K~MRGHnNiEZPqxTLPRxQnm7d5yw((BIR?+$@O5sSS9?EaR)P40x%d zT~u~+G%x>anQYG14=4JO^AyB#9dy$bxfqU#S9rHnhcUO0E-RnVlxRCwx+S|NY11)7 zD^Xw7KxU6*=9#>hfBLZ5$kZn*N2j`^qm9&3?Olg&^YSuWKP9|ol$}3q+>H*ZbD3{% z-kp>*_+Asmh%Hxb98c{r1h+k(bckNWO?Ifv%a!Lp)UZs}(XR4-IF6BWk>^tMt@$ul z(YA!si#_97Ixb%h-EKYIN@d}cqjKrf>w-j@o`@1!}4GP_^B+Gfg{PQ}UB z)`iD`fd2c(w*5k}KQuP-A8$SDe``x;CBBv0O?mUSZsC%t-veVQr@1HcD+kldi}EY# zh!&}>%<5cxuv8By#tI*l&>+aY<2VA$np>OeY9WDp2Y2^WR|+Q5QOcL zaF+-G5U5d2_8E;b{=XW?*{lXnKm|7gKm zZXV|h-loI_g-#_Sr7GH__Kzi&UX>){ob$DfYp!cYg~An9a;MO@yc!H|3dD(;LdPKu zNzY8dVQ779>>PKQd#Ku%nmD@iJ$!T+yDG-tl=il*5KsC`fG+L%!@^h9>{V7=<+&Y6 zN007XIxlxhxwt;{7RNF%HDLMuOw<-gHl+rGQ+bx-lFc9Rn&NV_7ZZW zzzf0iNFwzt29~OZfyJO&l2vE_;)YrC8})N@GI0qAKY_aQNl-QCbZ8t)dw8vK)2WDaoqPiC~pswT02$_V9}74eiBu{1^Utab^mxbrb%X2i)bv+{nuAEd_b*Nh%cH?3^Wo+^nc$Ln8}A*x!! zl9MeApcJVbgqV+B0OYKOYWVEXAQ4rabz_%SMf0_6{d$x{l4#z4OMCf+MLRQZR~G+9 zV87iU+~5-Gd{uL8wLepDtw5^7k;4jOqiCOJzZcUVE#*m4STp)pB+)~10SPy zKJ=;$-EAvm`dWO;_nmLW^7OSSXK)R8!BQt-JbH5)+!c^1tk{=+*9Q^tNX}Xz-M`|_ zXsslWKlAtEH%^4dW|6j)5W&8q50rrFm$M5RJTW})2&Di!p?sx_>VISdsh)v6V}wco zT!?ZCb-Fn*%r^g|y#t3A%Jk?Y1o4d@r--3Un=Srbux^Hjsn59eP!odceJ2_SL4a{V z3J9gzoEb*`!5u=vKsC=!1c zjA!sYTL~=waS4hP%D(yaW>;H#YoIdQ9#hBpi{#t#&!vz^f&YfG4E_aW{e!)@I{Equ zf?**(zSn_BO`wjJrn?~68H4xz6$*k~fJiMM1gOOkokBySfI6CboEA>MPWXj#vR`cM zS7ru88kuTB^t8+%5Iu7}J>5$XEiDsWO^B(5wz(cB*3mt89{9gYIQQ82hWK;XnHEG- z^Z$iDAVzEe94GgB{UbYfp>bhibz<8nCxjN0Lz~paMTYpd4q-Wls*m%~0}r2cJmI4# z?RrV_gqR6IOp=cvmhSnoX&<5J>M6NpDOGo2udMiZ(eHxLwY9^T^}V<*|JUE4UG(oz z!v%3s9_8~QC(eY^Kqp@m13A$hwYdVxfdV;|0`Uz8{xJt${xh7nXOG-s>d$bOHAVgJ zo!$-il^4Afk9Ru;vQFH6blZE>@C4}8Z$&~CI89sA#PIkFXEfb~0pS()E1z2&z#0dI zwz8fIOwv%2k}H=G8ZdfaC_ntefQAQO^0Q-Kx&!rT153*u3`fzS+N-FEH9OS2r_B!a z$$f~{PDE@9arns4XYCAl(A|<+VK+~MYOYxH_N&R+w*7!xXfR{C8H>=1y040=6}ZaR zs5Ut#@;UpsS@`t{9WsyVjjxDae=t6lrp|p-}`0dqlL9O|J)2G*2pDm8` zt&sWY3f}i~Csd>w89#Hp=GITqg?(eJh+M9A%K~ER`9g2`i-?yh+Q16MjonZ6yu`35 zJfF$?io^s=4quiG*;<^qcs7X;a{CxydX=gH8`S_%IweWxnj+vV?%t9qaa2pF&ZY7W zqXTU~$hHAM0?PnqSoKC_B=k?hSxMZ0LE7YFeU+9G6M*$${d>(v7eKeHC{bp;OGw7l zu{ryGQo5=^?S~tZdpa=RGwGQr+n!) zD$jVabaEyA2rQR+T02{GU#7?cmTTazLt6;o4g*>adZsBtA0nd9GV^u>&DGOaDAZSi zu4nsGf9k_-;^~3p+9Pml?cLr$?65|EXy^T!z36RQO8izWJpHPuE1B02ku(*q3 z7zl4Gmc=VxX%BvvIxO0eUip-aC7g#%(I%rH!hN@kJG;De9`prV9_gBnPCq=2p^|Im z8!zvAWQ|#P=J?=~f?FkCp_6=eYYLkr*x)59x*gsvzwI|cBZiFc!%-MaYb99XO z*y&Z|)_<^BnYygVW{b#j`ux0y5Gj5kAw*Y-y*9??np|BiMh6+kF74g6-RA91#P1b| za3fhwT+qb{?Jg0fbr&yFk8ZJ}0;) z?tShb^YF0GIeW!^*Spr*XPCv=g5?SNiq=D3s!<`f+wDi3!NM~QNBH;>|meJ7swttE77=%Ls!Z${IhzmLFEUZ7RzTG#NgCwl}cRMP6x<7`z=8XdJ zQ&1h2(jjO(*7SvT#UA12;P1{G<9i4Q^pYtG6C~K>A}l0eT*TPXYQ4ugC?v zw-bSlr9g78`YqAI>!I|``ZG?88M1$qO>Dm+u1-PU@PwcsOD;p<`-5tRfy^JWdls;- zpl>7(qf7=Y_Xnl+*7dlxMj%UcY6u7?vtliJH2@SweF-r|b49i^=*>U=OsUUAentbGqbQg_uhJ{L?+-euhcbV3-h_!#fI!j@hPHk$ch^*0 zi1Z@_AxQygNKM2CeH420Jk9|f$dUsPWocIF#S3%C!~6sKg9F^5lLah9y@ed2oTa8^ zW)=;^2nGF-L)f|L_lK&AII#%c@Ly1)%b}S>gW@t>aMf;NY)Y*neZpmJhlm*60ncsl z8j{|-#+&9c*O=DY;sCgiEA$feK5a-)nhVNVvL zS0>?KBgpAjG!THHe^rC+Rzwogw}w*!4yajyzSZ z-AeJp4+%FQ{O@0lI(Ba3MZp}gMsA~@(dZ9K-NnrehhxvTDKmCad= z>OmyV#@fvj<-J*cYAeJVeVx(cj7WJ8^xFO z#n^y6RYSxF_T8WL_r|r9)mry=U+djg=5ftyjZA3@D0FXSN=~Ffk(i+AO{c@of`iM> z*E$nUuJ2T(QJq^qUZha^gkl34S~fyoq&K^a={x2!QYYnRSI%f<{cd=xu?71&xt5$= zNp1CDhvipOUYhl}WkG2{ziJY3O4q`X2XL~l-3H4tR;zL@FvthRDm zY|=NQ;J`;Cf`spHI;|NjL{iK#&WSy}fQvfsjcJSVycmFs5vnVo0r1)2Hq^U62#K~> z+HGK(tK3+PW&+est1=xiz10hJb*F`osHxXBbw5C*-CiFx_`277Q2ltZ|nzH%?)NU z#_aqIDi!1oRmhf5eHywxutPRb%GdUXfe0@=09cYZ4ntD=pK^5stX~0BcG@#;H$ry- z{+gHcxe5G{Mg~aP$u!k8%f~8p{nJ}DFZFy$VG=(v9O=5A|AqL^zac zAF$Ccj~J|*oQ&`zRHb-W&4mp$j9)I{VfA8PjVAF=*tGTR$Is}2d4cD)bd`Ag#GKcz zeI-Bx=;12kpU^Yc(vq%`lw8EDZ=qA?7h1Gq@5pmSt-C+bz97yJ5us)w7}D)RW#ObUYs&{e7D zML>*(GphM_e?8yz+-6_Kn`=?s?HKf&j}zLPyKG0JS;_(&kXDhS%Fi=k$7}NsTn935 zz)!{XcTW4i0#efPfAH`do#fn;@EZf9E&5COKbLKAbCim6Z06Dbx2kdoFV-Mw>?NU% z6UF~~S$a8OAg||^(qoY5|LL0UNBB7%yy~ct07LUZcclR&BhsK2H?u{(*OZsI7P~d< z+}=c##uA{nj8T~Vkl(f5e#iEI?Z;| zzrBml>H9~=^%@%k%=lz9y~13;U?5K!Ua6gD7O42;z4}a&fSemr3CHLchqIAp5pn!7 zaqv)DsL^rYuNXfqs{cU2$XhDLeg4RY4k&>Sp6(cr4@Lrf9th;8h#yKOxq>qJ+0Ci7I5wQB(LREY?Pvg8$l76<5-elA5 z4x6()mE{*een0tXrp?2Z=|Op|cO4!TTc3%3kx#dXhsy)GKaGb9o!{Cw%n%nUp+(gz zx8YlQ<_@s3+?to@@yeY#YwdbecBLch0F9(nC(8qU!ytw*+P}(LAT8@D+rR-SodGHK zVNV%x$2&F7{~4tzQvp*Ni1X+I7VrzY(xCuZGYykralh~%!|yzP8y8;fDbM^3SsXt- zkcO%pBB6?Q18=bHVyriibs(>K8dnjSUFqEgQVi!+po%o*rR(WK7C8I^SVn;6iHIJ~ zxJkdI{7Np1ArhNQ&Eoq`_9mO0&}UMWYKZe_TN``;9RpkpKE=x?Wkw^Xs(@)StIpJ` zQTS8M|AhyG(NO3P76_Q{&s!K-`edH=D z3^$QzsH(aWPgVt%+l?IyR-}p#&H^okYGAn`-Q61?z1^RXVKjO zPd%)XB#TMlkSYg0ke;v=Tw>d9M3^x#z~6Kb4yb^HHW^wB_`A1DjATCBs#u z{O+{Q*qNb+^lQ@z!~`Ondyt%z*hllN7@>Ks1kwuptQPR`7fwU3h{L1j=p>A4wAide zWI-^rNK74hL{0#s(ty+%y#9GDd~+s@eu4$88_Ddi`T{|i=s-{mjO~S|;AxzWoFTxNEpQ&{O9Z{rfq~bVBX7rlyyA#?f;g)4K!(UV ztbokqu)r;8Jd%O|s10Hj1jhYJyyd^XbX>S;ceiwZEVuQ54g%VZ?kJ)qz~?}RMYY=)zyl%8j8I3+H6 zSqsZd!9L>pQ=ms;M!n@>k0ac4()1d;qAT^@G`OJ5BR6C*vV)73?$FNzFm_NxG+}X| zHIv+qjnSKExq9pyn5{gn3}sq~VSnnqXoQ19fseDnjn>TlB1>b6MddiyrB~G;uL%6# z{Ou}%jv4o0pjy?p7fyz?aU;OAOz z>)H4C6==VwnnV8s*iMG2;N^uJVg{D8c5(NDA~EOB#eTo~3|t3DTOnyYbA(1hMi+{R znGXS|?O536WiH@~$`UNF^*7cf;bs!fQ1=)rQ6r$r#VjGX))>VF(s!B&S^b+}ElMwa zcxCBj!RV2yftJoG;TFI-S%6MtCgdZ5B_ZXy@J(TvEQjy2d>g{x^%b8WfG~A4coOEZ zSq)W%;h9{(h%mr)#MHPB`bR` z6whj;o6WrNEngt1JGUM-(AT>?os$iCkaNmXKF)LibSIte@cm92X}@=ySPiu}emLK+ z&>P*On!5$0KIKAqXJmX`j>O~#8Me5~K=nXFpt+Ht@0nwoTS#M)QE^6odHTDxkutsT z5iy!pMGs0ULn-@i%QWcaGd6r3N+IZYwD(3iG4s>Uy4UI3;22TC&?*qx#`QM}e zA${UZHd?0?i`z0H%2b&waU6M_ARuQ3@FMR{A{ndUC&Se*ro5*0mEYe0c4!5%2fc9w zKR)Eek7WM<_)(#6J8K#8JnnMicLhV94o=QdMys`r!?=&HKr=mi3f zPnQ+~qqk%9K6wgMubVd2vu4T>VYlalm1C}3KgDY>tq&f^p1Qa*F%q@U)sTf}U8@II7j?bfv$mLkh! z@mNF+v0oPj(>@7=T23qOIWMe~hWes~1TA4{T#pY+CfTP8nJgQYLgGGy%u@c49JtQr zt4w7{3PV~he7MAGc49T0F`FMVfs-~PgG)@(KkXQBVNN%wiv55@mHsPm_+(V{(_D)q z8cj?d3oJH3UNL8P`{e+yazpL=hl5ZhfA}R}>K@KmX8)Qx1F2qR_0%sp^^l!ZOj-aV zdl{AvwBe?Kf}m!v>*hXy-7_x04CH#1{BJ05*%zRxihVs7fSH(0_DCZNluP)Mcc-NZ z{486oupTy&Udai!JvVYpt>o!41|RZZV1OImFO_mBBi{H*$65!AVFG;H{;T~Xta*As zVP1S{-S8O%C>v3anrS2_7kvd?`-(BQ%FI+w&A|uhm8X)8yXi_dvAx5;Q!#NUo_ax4 zmh|aiYm)U+f>0;cyfxqF{48gK@Rcifc28jq+Vr3S;}(5>;V&s~4f9E{hU04$H$UFre6NF-zD;V_M3uw28G>JWKAwBk!Yj)5?DhH-YBjVq zn2fga9lZ^CHUc+cR>>C|>z7wa0syyBo5twT?vX~RAXa*iss^$Fj?*0x88OML+yzM` zSUlRzrOO`~{Ljb?ln%_*lRJ`MeU&o(m;n&QU)bn({X{** zX0@81`ZzBUGZPwFw^|J!lJcjKAyIKO9N>y>eJP-<5*(a_m+;9NEen3}60N&bX*O2* z=obmg4N=ZIpnXo&^c5+^QRfEubk>V4W7?VdC3UmSc%_!wf*{>v3G*Ws)fo=fA^d?4 zIlL67qY5(FyQfzyUmdAx4IK);=EJ!rjhu${-8c?{(=L)JO4psmVDPRsW7J9WFwJ9p$ zmcxOy=M@WMOFSFs;wpM!yYn~2Qog9fB$yXwjcmhG`LLFQWHySo3921`d1{W`()O6n z2^q^{$ReKa_N%7maEgy7aQ7v{$uEF#_13rZ^C0iXdUvNF1e{|VauunZl`MdN zqX7%U=(-hMOwuTYmQ&m%caAZzD{aRCu1BaY3nnaA^c2+4q9S40a;6)m&N4H&a|#HU z`gu|sv(Y2@UZMp^up56gFnd$@J zB@%-E%j9Xms<1Nf*XMS!k4(|7)R=iYF1EE;zO(c)RiC^8j~KGE*297kELhb#ne&8X z##}uM=Py`cA+FVx=RNxeby%a<@EGo+NKD=me*(DqN~-PB^ss03ybh~#3QW|_rM~Gs zL&df9AJ5y@3RKtFqR@XCz>cin!R)8`H?~We_--Pk2U$e`-hXSbuY@&w2A>sVA!r9t{+H1z`tNLoY# zG+56c&&K*1lGT6izQKWuD%Iw7(oWgb52`;{631eQU1`aEoME*zEvfJ>8D>U2KTjw1 zejhPo!_;zQwfSH3>_x9He2vHJDTk@+9{ zUz_r~EqBcM!B-dl;$fzwv2{#QnH{DB#j+eE!6k>>-9Htj_ZFVYRcybB+>0%WdHF0$ zwOc#dn|~M=hk{DLrgmk>oua~Ceh(obwEXyxk6A1Wa>(m)X9S(L8ITTmq3SPmClPv= zAn<{}B$|sKxAR^eE9jd4V5?UZ3kzY$tUX7Z;Wc2 z7H<}x{N~b71wi50O^$nmol}->I&oCqxoE3>Dl8J=c9bmmJM|-hs5b8Q@^+ylIw}&2 zXD8RD!s&@{MHYTaOGO7u%%uyLFnUo@yQXGn@w2Jg~ywnhA z1B@v5JOhp8ljXG~*epmZW?|rCY-8U-szPqoYH>PJsq{N+Ub@e&a(>4<= zRSidNF@YNq}$BE8OFB=r2Z*wPyy*RS z5T*DiC;1_V#axF3(+8kqFDrqWNozGs+wSi-RDZ%bJcRzB<>B3l%EUQsEC1fft3}{s zGl(hlj^KZs{o2sB^s|b=v%B?`rPX zg2T77U-g^leI&pdd5h8PPYF#>C*W`9OT304yA%Q6|WZoOj+-=oY% zfjO4A^GUR}s4&0`#o3ZSHoW?FryQJh3_SA7BYa2eDDyI51J8R0x^~;9@I$}A;umZ6 zn`{J8w&OSkZa^}YA^6qMJ;PXss_soz-Sh`i(E3uH!_umONzC^U>1|W2WXsL(NiV{9 zvP_~#><@jT3o=q|Z?O6bVtgfhuuPyXWnGchjEx#3mTEW}Vbgof_twKLhVTey z#&R;397E|pCp~3u;Ilf5L0~PkKqh;nAoFEpN*TFDK@di`OS+} z($*+t^u=fnm#Hdxz<}v9-o@X91_GR!wBja@H)PbJWSK9L67x|BF=A!)X^^>w(jUR1 zm3-0W5>Bgr@epra@c1Vtp-^O6=2S3q4e=ZezWLJLOtFSFtoj>?WV%=&;4Y5$HI|3{ zFvDL6SLK~9^{*mH;DxJ~N@UFPSUd>Rm$MzgL|3%$k`FpK%yjz_n z{fy;&yamt`Df>I++j3@iCZpOfmbw+O(`8+Tst4y(dVf+Z&;Fu(>uhIxrv!RoI2YcV zo4Z;L|NP^h41gez&IFs$QQ{H~58wII}CQax@xh7c8uRBzC-0QJnCTG?T^rd>^>x z&gxC<7OuuOKAOh`+T zc)$|DUX7i`_4IPc0WTGv(vk@)P)bQs>tpb|XqH;-S&}I>av`|J)nqRf{Iw`+|MR!Z z;e98t3&GK40G?|whKAau9L#eI7QMNH1Inf;VHzn?AaM**b0p`5Toe%9xC~@xakoIg zWQ*rzmdChpOtMrk*xZ}uX{b)w=x=@Jx8q%7Euww%l)?Mb^EUrET4W|+P*+S#@rXup z=vcnaVfI|{eoRC&6F$3tjlL$)8I1EzuDb;z}~hzbir>)MssZ(oPHK z$95*26|r!jH@nUeW!miMGPY49YSHhf8eNRF{D`Hg)ad0nb+Y^R@^F*=!=Y0uY@(xt z!9Mm3>QxVZL+I!IrOH!*P5pb0>m0$DFfcs?UzS%R$lQ}&YZIy>9r)>hma_%%#^_mA zhf2QB!iaOXvro7rAxaIcJ^bybQd)D>#4bOTg+#TC$n0X<;joDNe}D7!a7^jH20@I) zU$F-;eZo9~urqjTP=HZRCI~`-o8-mI7pPLCnYqKf`Tmx!u!gIEuS>}ks+K{$!O0Q5 zRRtY_n3xbOh`i|YP-8$jiF>d1BU}=}{64R_En;lYC>6!KY8eu5PPmh(mD_7(xfhX^ zmlB~eZ1^|^K20R{JOrlxeDJ(yakp1J#!5cp{ci!s|&AM{%gc9_(`7|^ zwa;xpCj*x>gm#{K3gc0rqSr^juW(+f8$E zzC5AR6ynN>JAk%0>0Op4y%YFcteua*KXYV&tx02lLUB49vi94Cv7>c(a?S*l?ScT-ElSm+Y% z7h>~j^GrjD`)R-Xv|haYaWhqcy0UlDmh4UX#@697cNYe>*2(~Te$f9 zPO0&n*Cc8$|MI?Qz*}n~*cH;+mZ3R&oTT?>lrG+qEqZx$v>@Q|Rk80A6e+l5aj@za zOwxZ^YQ0nBsS)SB7SO4AHflN_CpHmD-Q}D-oZas%2I6x}6(fYlH|%yV{CO=2-UlhwFQqTWHFWbJz^+Uz0?Rp%@w zF$N3TdR@&S8bX`_MJzQ*XE+9!{pLM^Mz=5~&yT#_c6_7@G^Tx(+N7GQ&d0i6JLGo^ znEc7zw#Ih?pK~%O02H*QRQ8RQzF2W%H@wMh^Q%>?6+_^+y4_R0Fs-~agIkT{mbRgr zzVm%M$RXET%t^Kq7@rcdLGIjXeZ$>1Kex$^eX|PX3z2TuOVv+S?2dO*lMw$q%-IXG zd%{1+4y4|$rpE6qb!D8c)PBq+Q7994;zlfSPdDhP7U^VywR4?5=fYPPa<|@6*Y3&m zTw5(AB!lAlE^%WJ`oJ3Id){sv4FsL;7H{?Wwld&NCe1*y@{nE%lNh(m^iNfCPpNZi z90EWO>-{5z`0>2Zeo8f-G7+yU0YbO|E;X`Rv%8WyU{GTBA$^`#h-khcV(a~I70wI| zteU}d9eYiZ-#`RWcWn2?w7yxiX*AxP)s@Kz$S~_4Up|_QdH>saSTGUtE3av*uxIdD zlu~k<=hNHgjAx>CwsALYBhq)lw`$J}_J#?HYMM)P4@xz#Wk2ID}yT{|K_&ha$V9O8D6 zy!lirolEntaH=+{FYo2oGzd@y32N`>($Vk}O906M&7%`sT-=!aY_ITQmi;>rCGG#~v%Mul}-CbRzAl?}ko7`9Yyb0^<=U zy$NTGJz{3?`|*^6mTPs%4*xK1-oL&PWALYmM}a=)y*K@(OK+Y$-t?$f^-l;y;)HN=#$5+Cwp7*WSYu>$@jUzRlh=0e0!VJA3 z{-js*ip;I^b(I+E7c-9Gfn&|6n9=V(!UoT(uP4vDDjC$Vt+lKV;u{;D<3=t+7uKDD zd{kqW5tx|KhckmTWK%@#D%j5pJvXlUZ7Fgzu`>68LH%p!=cfw6H7&|-mZ8VJVq5va zh0VjY&^a86xr)B1H-H48+(M#3m0P=s6E*D14%c>bs-@X$vOx6ML=k;S z1c-4Xsaoh`n9OI0ffh9+C}Ytkv)x)}nQmdV$$|Y#Dj0nz2ok6)dD!tz*lZ_SE$e%p z7`11wMDM_x^=^^uP8W*Ek4u4{pDtL`44Qi?*hTfzQZ!s-+Em=&(O1#VzczqI%P1qp zaTCBsm9LAwx(i>+Np3cDaR-ZXyiIMI)bo&cs0mm}9euZG_@#Dm%^?+o%Iy7DISer& zaJxcZdQZ@ww(A42rO{8tjh4oU2HNk~ds@+}5Wbg)}^x<*tm@cZc9DKe0*gx!!Pa&X`_& z>VTTuCl^98O9c1Cj4l{9V*UI@had3gS!2__zHqe5*ZtmFaf-^GXh_yUq~(rLWr;l! zdOVMyFlVYv72tCDIcEQ*rru?V(X-UI`w)uVxd-Ty>^jaI2Qe`BKDESDua+!M{)Shv zPhK&PvsV83z?|@@mQ8ns&nFm~-`~m3Y8B-%G0)KcT(K&`2#5h!A;p|423Yv89z(*| z%w?_nhrc@|RwqX`dDXPOlzN|m@2S1o5f|Hn_0vLl&%8t?f>pSIg;n9-{9_C`-pIbkJESGhv^&0YJ6bY_=vhGqzWP^ft4XR+(NrrzP9n3Cc zIEqlwX*b|q^v#uax2_i|oOotIX5JrLMp{~ZD?5=Ckp_|l%M*no+Tl86$To)U)TUXX zzYt^rmoMOFFkYbF6YKPzJknmP(O*%-5Sm08It^a|e6uQedk|+8Mb``Q+c!`*ay1us z+~3NCyoDCBh~c>7btQ%V$6@{_eefPsJCd;McqdH=s#iEt%}i7`$QoR4WJ~}Y>xkP^ z)@W%1c2_LqlJS=9qyLtWQNe2Bes{-^L}ub$dlVg;BA$ouXG%7X+Bw6NO&hIiou)^x zJBde=q4lmg((__DcqB%Z*c!ZAR4mZgCpcpp^ss7Xf<`!rDrfU3n2q zvip>@lUT9W4H3f!?GzB#5rHj9{IHqWD$gnSqcUq0M(d2g+>x4Z~Q*ydD<@a&(%Pl0(U4|O&%VFn*|C>o*{4l!AW)GPs~NNwWRNBMSsdWt zmz{DYlNF?jgL2B{8e4X%Ron2#k6AUhu9WlV$GP2@2y$tI4RmI>W~+{si#<`oQNsmA zK`7R1dx3hA_!>BkMF^^r*n{H!-yK zkvW!+oO6;zJsj6GLo;fB`fZL|sCm1oFW<@CNkKaKY=6nila~}O7f{oyE;RJB3z=o@ z**<(A2i;JnLTT{ib}}V^SH%NwW!102_)%N$!73C(8WQ!|i}?b}15QWF3o>{VQR_}h zq^FaPBbd2z3z_1YO5!K-!8fcCe%srljeStDCz#1)=G!x8)NIb^Q#Pb>jhU-kJArJw)c-X=zCplNv#f! zq=%Zif+w*0C|B-@=7-`TGYMRgnVvc}b{GoPJxnQ&*B#%sD?p$8a2%^BzZ|o;OFHeH zPvc@t%*-104$-=&P--WFBrLcZ2pG2wCM@~IjFkTsYm+D%@;O@%WAY+JB16xnOOfiZ(4$T%QQOI#R3&ej)@_ zjnK4tDHxh(S&l(vTTOIdh=5>U+Nbsi8bS0RQgFSj@r;WzlgL@{7FM!SJWIvj*|v#K zaqZDV#eo*rX(GkPoRPL&Jr}b1Qckgvh7i-l6A;ik?3h^HApDafFW#i})b^}h=Sy1o z*vL{m`FM-1@hnPoliDl$f72cBcpm6k-H6q#7K~+Iu>Wq>JUVYxuqAa$i)VL|H*e&V+k6cgG4 zxk!{T!x+_(X1;xxGF7J#!IhQS)W&k{FQY+3TCJtvw>c4t0+L>7NUb4>x|X%fhT;>c zhM!8(Z5ghC{ZMTdaSPFm9&Ve703R)?9|h}hGD!PZu8a8nuc)DJVERnqile@VBd>3~YSZu&Dy+8J;1cN}5L|ho)3@c9x7L^5@)y+ls)x02byEtt4w==BVjsURpj} zn>?e+SD1;{72hJvz`Dff21_+fXHhq+HfwB&4Fql4f`NA9wGj}CNPPl6zmE06V$nxN za>;CS6|b>G?hsX$nLW%W)&d63L$QmLXfMn`1wazr*T1ZnU{Of~XFzM`mmyVBU+g3B zq+DtDS8#>+d3x(ysJ0Y1xlpAS)AU9EcKKf6^_y2UO&2OBGX?jY^hnoB+N@G~$tPO5 z%11TL_oMQOKK&%+sRsg{$5{A7!(btCFE)NHZ?}xY0+FUvV5b2_y~}tvd$VlOz}a^- zO(fAHV_~ROdV8Kkt)Xq~a#l%#&UnKwhQ!0e2V!u#vw25^nom0Kps~O6Fx6dj>xHDR z2(n@=Wm!D|`kfcUcl5cWy&kB^VXwmr(!vi@qghtp^ zH+lalG}%~l&I)fJxPZcHw!WXHC>o39q-jv>nMA@zF}ASt00=~U*kyb_7mG05Qnb$U zJ}(d7dOxvDZtWx-Ya!84laY&^K?HF>U^Z<2*)psc3Qb%XqbfSY$}ZNY1B&dw)s#bB zYPGBsFw;Y(L|ZELDC>*FVH=5an@i$I{h-c(>c~B!PthLaDz%2)X2c{Ju$nLbp0BxD z4~SVYA8|xxVv#j25a+eSr&;DIf@__)jmh&;W!9e4(!J?u&7b@*8zP`J(QN4{s&zT2 zNqaY;^{x4F=o*-On%at$;rpk50Xv)L-d+9wqOn*#eYNnY0lwgJYwThUR-#{cmJO?J zcy9zb{L#8S%$bNO)^qq>z#jECi!Wxb*&>%zd>!Yj{qy*@c)%jRHl6Fth0AjmR*fK?-9nYotTG zZPetc{h^78JP$s=a_kZ#=1kCwHl|>G`Vs4PCX$Op@>-}^ty+zA4@vsk-|Nw~%Yh)4GbVtHx)c9@nEW4C-ze z1q+&n4zOyq;|;a^YY*a67Q6V{lnzqk{SKdep92W-M7-tiM;SLCzXNL_@EC~xCFDp8 zP(5BsYf?D(lvrTIro3FNu>T4gewOH4YRedilV#()X8@LLef>K&T*>C;8k7X1)^LO= z@l16_MLq)~Sw)lLM^LK6Vd;Fl_v?i|Y&%AtrQXZT5>wcVnVv1(Z9%JBDJEuYu`!ri zMsEIPh5@+I~2NB5$8*YrBaTRB_A z+cy*5msjg(M@O=h=6ug@y;iPrT9CYYS92D`l@WLp3sLOt)n1fSmM^AB*J2=C{n+}TAM@cDW8Un~Up_I8`gFV0qd!$#Bx|e&D#3Ibqsr3oHi(wiy>#G=EH&NE&PC-81Mez#NJAM0o;_l@<$%>3 z_Q@H2*m})Tx-$>^?&*T@uVf|QR9y8i4jN1%g)qYL%V#@=&Kc7W zJ2Q87I?{RU;p@W6vqo-i}vz z?u2X_BA9v(>gX&0h#4Aj?^R>!od zwH-z*G5iV9g{H&IG4Tuz4Y%`KC>qojNC1nm-SGkO?O#p?i-$xOqNI>s+l)S(dd%AI z;X27_Wy(pLu+SgPF%{kn`TGaemeh;r%l=ytvSSSf0nV{{SjW=+=JF=YqPl^3Z=;cIXzY3PTU4uP2-xNL<3Fd|3pvTOW=vo4N^|t1cu-1^sn3Za*d?rnS}K;Wqv!HYOA9sh@(7ZpIn5Ji}*{a!LI5(b^31Bc!l>Yd(v=5KmW(J zI7v#1H(CxZkLSr6qbT)j4Rx&AWX9t^rq>sA(AZOXz1_BVjKU;b>3-=sE=q$SRB@y8(6v8yl{fD!%DGw-!HBu! z&DtfqwPFS|91l*^q?r@^<7KY!@Q_+Z^68rb-~$PHMZThr;0378??pEjmArN-mLyO+ zia9Zp=VgA6Df0BW#waya12*v#B7I-qfzCdfn2`sSXHVB!!#Dba0+Q{2&V71_THJgU zWZ@}SZ1ZB;+P&5g^l#1W9rE{MXM#!B-eY0^Y^umiZ!C5n%(PZIjGnP-Irfxm(M0tE zM^ChI?OAq>elrbBb;AzHqH(KWBKd=-u}o(1XY|TQ5K-k~4l6H|@8|$!(tzE)Mmc$- zhLD!iIYRcEPpqLA7d`zUwWGW@JuPK@ZOm(bhd z3^ymeCd}wjdxiAMik2ib`OGhBO=P~vC-{LyQm)hL9kO-y+3Le5rnAE-6&;fIL#K*Y zudgqPurlRkfo&k#p=O5a5y?=0!P~>F)EBGLZO@S)EL7*ed@^0HW486# ze?@6hGeTL^kOu5{Gd&aYn#;Z^WY@}McO`V+@zDn7>dKJ+1tWAufPWu5Eysag1XzuA*J%Nt1x(eUMG(a z6?ju()P`A^{>H2tiR`3#{drgs6csa6bOV7Jhh_4BF-in$pUpy%O*GqtiSs;&9yB>J z>k-e8&0L1!T>~WDziO$*4Go*@;B#$b;ppD91Nm?(MS6obCnt?uw@g6^KJM-=7p8}R zmW(IGt3RM*jM#;kheEtUDQ1n4A4TcbHKICquDkcX=F_-5E`-T==q?h1UQ)gfQn=#& z(S$iBSVCQy&lYi~xzxjV0btY_YoKrvnB}p;_HUO)+<(?GoPIb4-V~Z)I<1YV!YTBT zi&3ptWFv)0#sQ+H_Jx{u|A^lSD$c#&7ON>zSp#bS!|eY>aUI$p@MaHr|= zICj9%(zCUnyowrhJ@Qd)x@|M&_(o$rWP|3=I34A5?jgN4^J3p?g&`mF?)GgnZgHpX zN9(h)gRo}E{w=zpQ>zyQ43}(u>8KoMxfwJZOniCb@|dKRy}vzbs5j#N?oIl8(MNLC z%YptDm3Le~?qIe-IX!1Vt=*yQ9D-x>IV2mf-w8jyy`nxLm;0Mj2uczN?Hv9i+}xV2 z!{3?04}{{Lr-GKl2IP|=Kyd^{F}7xlhZcvuksmoiy;saJRWsGinm%*tTcj(v^V2kk zDhv6uK+}z=UaK~D^~{dsV&Aj&%0ZF_)cN)60QB=0E>{v z=G#4CO5;Tt&pJEMPNa!{=h@GSn_Hh@@-nGkHf`%Vu&;;EMb;?Mfiqj&#V19uTMs_; zFq!TBX#fnLlafIPyzIVhiPJBieR}nRWHmE|`YqX0Ww`nTCeP0Ul+KHOBcuWwlOYOk zcX6~m3RE?o$b81Dt4|kBTtjp6^01)WIk^vpB&ytj|9LpA9*)Mi&HKA}^Z>}6a`+u? z{{}8Pru3?kD?W1@K)x}L{;J1NH~ii_<1Io_IlNchBwa0Ox{sfRWyn_2a=30$T!$I3 z`(?;Q;Q-%a34ez5$G6xSi%nC-I-J`p)1u~g?8ygei6yvEoN_0ED`!vD_2K2EmIb`u z{shdlTs9*tUxvl7P8IGw!hU0l9WxH>HT@zg7E+>(kuKXc;hmmuGMdsKp!^JS&7C?% z6N2IxXt?bxFL&esp{3*c+UtV4TxsQA=wk~v4Y=>U0lW-h>51~zyt}%}u1u^W{-OLD z=u8+Bba)f0JKS!V^dFHyTm|x2PCIwykV2h{lCLzl+_0%s>8E3Bj#VjNl2tTnSH-^f z6@oV78SKQTn_}{Od8XLw*?PwB-haMI9K{FYdj%#h-_*IYR@K*iqTDczmOCe7zMdGZ*RdDVqz9cn@#kZM?6&J8fL9G^JRNXGg_|HLn({@W}f_Jlt*mMezJQ$3N+{Q$FIs`8+#s(lRWpE8Y7so<$uqbqUyL zH6eR|#fwjZ82~XDG)eYq23f>t*wLNDwjbFtX*pZWk>&p+<8~@5F1IveglgJVA<5}< z=S?ZRY_x{IsTL0&6~F#JC7gL6RNvdcuVri_*@lv`Q)5?@eVy#vFk>*x5RpMlMkzA3 zvZNS|r3Kk%42J9^DrGDC7Hv{ODWblJ`Q3TnKkq%~KKGpGY|lC8c|I&FWqN}=6=&R&)eJ)sA*w zO6L5V3$cetv_7SG6g9?CySnt>P2JeC5~`xBZ~zpP?z~VW!Nl zE``-Td(gju%;OPtwl5EyE#FV?^4rSy-YYSv?AQ#5kn`mw{EXR-2NzGH-$!1iZ!9sR z{vwzG_uED23mIpNgp*2r(jeS~lNsG)v6I}@l+~zp&39U(9{ZQR(RxeOhxZbCf(!*P z#j&+*XW-5Abd%u#sxX|qwLTz+(dAk0&N!=5U=o}OQ5|26)ZnUnxy%i_h2ZYtF{>)p zw7Jt-AoF}lE>U+tE8@|GSnlec&WC=T8q$C}jIQAGOVR>y02bAIghlcVOz3oG60xx4 z+82+9cEC}O=Qz|q(R0tim6z{C#PU<$N&Wmr6w|JfLOeIS$;$$p%C&;ayz1`PKa4Hn zHDOtb3rrLhTmO#tL}aNy>RRC(wMQyY%0cQ@^Ks1EJIXCltOwfAtP=qOl&_D|QJ>eP zdc2Z^)_w@&4r*T8nspTxdM-&z(#^K0D0V)#*;b7S0_Sn%!#ue{YX^>%#%%cs?5< zqM6I_KF3c{hO~!lW{vJ=p|wniJ@0qR1xVIi8^`%Qs(q@s;Nj&U-7sYLdkj;@#N1{N z)$uHA?$XO;a~szy~WAV@((A;U9@WJr;Yexx+ljqaP`d3Y&-C8+x3RFH}`(*ZRAyK-_+Y=Oy|F8 zLcMwyE@zK34n6SK+{x~o9w#J=jFH3K@#FzBY7^8j?a$83U+H^HA;Ui4JhGV1@+oW*g}0#acR70@0GLf2)Gg@A{QVz=K0ha!rOYoc!0+;1%lqG9`=uw9>X$p7zqQ z^Ml7aO)dK$)C5wdBq6*6=xAvZYv_U@d8jv}8t)U!dTw4JW7l_6+rkDsMbHXwpYalF z(jguBPs8hKMV~Z>;7wInH3A-Atm2KnFxvyuZ@TbLIOr-1|3=z+pT!0EPo`n^e*f0g zDSG{HdV8lj<=Zn5nW5Df9dOsXyOX8> z;%2g_7#h~`9h`uApQcYFcsw%p+vrf(Od1I5P(Ahe6~6@le7lcHlX=}Tv|YNzTHr65 zJv!J;Rw#pwig`U~ZV)P~QHMp+l7J>u!3;>Wfdqc|nN$5|k>y2(q zo$%3aev1VN0K6NIkx^C0o7NpiLx!UT&=ol!md2m51Wyo$)z7!EjhL8UDz{|7qE%t2 z&OB3l+qT=lOgq>CdIZAqW6U~3%} z)cF~40A`H&5a?Rxs%mp{BQ|)T%*dM3BVcHLW`E@F=6fm^GNP;4Hty zfwLSyvGSOqYXjAOy`E9}XPN^VH)EZP}F=rkeodG6=1u&*OB^lqP%nJAS zg8F!i?q})Urs^H~k{AS#{S>xP#6X8i6;6A9(h7RZH*CoCRR=e8MZ5p|&ufkh0Kju0 zak`iJ#cQiE{SQuFI(p1%7mfihQ?fpDUxEGiyD_**Xf6o=ojT) znzIJ+IK>|nn-1jXV_>)R_|dl`5}5`W6{euODAs>#2vh}5a;86&OBs$fgb?n2va~$N zi1tVP5deyDijkSG@45HC$xfYA&0C{wa&ZriAVokg9sn;puL~jZM|tDKRDXAHDnvHg zG8+gwQZrntDm^>@K$EMymkTW2a^`yYWCy&UgaoV3wws*TVh)w5Va^q5a}%JCH0QPN zKmjwNVqOg#>_zbpx3nsboCFse&;rtBZxEpKAVKCp`dfO8-7Fl&X8bUmu1bFhI>^1s zW||x}33$|8INqemZqdynZIZv_%X7#|_4nE*^*+i*8h^tOl?+&z!*HXvkUE>T2zrqhK_$#4*QRIeEs3$)f&wClHVX-kq4WpSx9V&90 zz9W`kZq$E8RB%>)$d+kg*y{FC2oRQ;<-FTY&k$!t5Uq>sCOvtIdaKkhyoXJ0ojMG< z#e&ZL3ZMqG%k7fkG&eHApG5bkj{EN>;LVMRqGN&G!wtrK06yaZxu}DCm2QXBUEHA$ zh=Ye5KQxcc1e{WdEZzsZHOa0>)fMgujc+4H?ZdZ7k%8E%)!eZRJ>q1*bE1WEcnp0NiTrkWJsmWw4J?8;H@X zsrWzxP`}@2U#zlg5Gl2OmBZ|;O>W2|WYf37DV!}mV5rcb0fk?z!m-v;a~7?AL=H0_MMF{z?n&5vvipG>*%8Is8Wji zXr(|;q98i!N#OXOlJsd;+g5>X`8mkQn|!3r1QM}gFpUp3MrD`#ub+$x-gE>hmZE-VfZqeeU54LF4!7#CIub0)r z%yY*Mk~`ib?f2Tz+3m_|2g~SvNXJ8`8v=(UiAmB`zM< zL&a8c#J{@8%Q{r=O!otiq}q1B_6N{D-k#@Py;Kz&AY6KKdxPs`%|Ne3S7(Gavz=Gh z_sFRFt0c-5*oWEZ=M&G}23+surM1x}8Xutnp?G=xw>EfPMFF(h7R`p@H5>xQK8RZ?r;d0n$ zQ9WXH&8voF81k&LVEWK_CB+K1(Ku8dByItQEGMQ!n1_m}LT4)Cl~r@~zJ%sn`g^#t z!A#DH4?WVf*z-$Aja{dnVmJR}a!3Vs} zJQYC4T9RJ;7Sisk=`#*+IkMh5;m^QnlFT~P`KL*^_TGaj$mv~2vFkANIYqxW#zXlv zCu!?-%)*bg@O{=mK?$98gygU%M&G*TFdG6=5O|WJ98JeH5C0mFY?T=6Eu+>JhZ!2T z$r@zkJ5cKe;mPSWL@+?`NIn~4_D_15wdvQ+&Ar}`@tm&jB?+c`g zlVJ_TMX*3swzDO3xJptzM((^*3+_g;WdB7@p3K?qFJfyQA(~tEz7*%p@0>GdlqHNu zl;KDPD*>G^=-v?DeN7pDv@IJGmb4sk||gOnjl3}3llxj-~w!Ie?-qETzj=Pkcbkkd0%+O ziYe=w{#MiP(TBX9FW-JcykC~3?Vpo#wOIe)3WbbhV{|3dsA`^jonv)foi99mnaX?; zoB95#V{PC$qvt?Y{U;kY&)fmYune1e67NWfVe43bx4|h@nMBD z0>y?x+48`lL<~Yi%?b))5{VMkRf*K9VD*?n@JYB@&k1XK;q%3u)L^z1018(%y72p= zM{4fC)WlZjNf4R{C}y7GGyYiud!19e|I)Yl>;4=TVXxzbodeSVw7>4^hCzdhk9D!4 zmsra{@TfDJ)VLx)ecSfLSd4)2e}!eDFikHgD{KK_fA2rrv#Ym)K!X?f6H)E2>r87~ z&zUG$MA-kat@Ld?zwu6KWWn#pbuBQ%w?b7aJtjTARfTr;b;i`#yCNealK2ZQ0O+Q7 zg%s|5`QwbdQ&MOoZb&sy7g6sIcC7^EW*sb=guLlc!^+&n*Yr=Nu%bU92#e^$>LMBj z>~95gydVD5L_Rg@ng$zPy?&bJt6@y4W=wVccde(&?bx_bns?uDj((TLiOpyR}QLGfjdW0f3_B^i|9 zw5>PudnBU`ge#~+GXtAuyA^tnWgj|F4nt^A(leT7Na(UP{*L$=Jx6|`>SfK;%b21B zNr5)CSh@uCw}yrfc)0*t#x{Zt%>q5(f62|+U8qZ^vvR}4uJM^NmaFhHMnGJ1cFW7E7<_5HZB)FyWb%z%_qTr zBD>3B`q;%lrr;CGLmj0d8~^_jui=eIFsc**g-f(3(Y%C(xK*uZ?^Q*N27%?YXgy&I zt7HkQxy(w@LT%5lCZ~exfs~c*JRAKd){|)0Kysm|Z@)py0{|axm1f0gt>EcN)cRyV z{Hr25YsU@rL7Vr5)q>5Nh34bVXGjQxCSPeEQe8UlgaT%yAmS)BU^O3i`9J_96iOB+`j5`9Fqx)YmdF< zeZ*gLnZ2=SikM)(6-i$0HXe!?mEZ(!*p2FadK)=#P+0AoS^Er{o7{EDn?fUKx3}BNoyw(++{#_hI-Vm0hXu(J2e1H)hkHAMI(E`G1X6+y>)GeT* z>w07ZD2@DT3>E7-4gpqeUQdh}GwyqdN`Sa1y8U#|y@<5r$g3iLN1Q)KCIzeHwxqmmVq=mxv+6DL(K0~sE5NGLGG^Hjan?mN%DKKl` zwd<5ANj7c?On|3NP)68a+=-<=_T}x9Gz&|k+^b57RXM_DtW9LsH6-(g8d?Zpm;a{N zP3VgLAKFe1pArH4FlccWr)g7Aa?xGR1^4t4N{}t5ot!xz(ovsP+iY!Ua)mmMgot~LWEhm(*umR7xn-$HEH-At6VX(C3yqF!s2Hq7vN~NCkdsenN94IGd zt6&J40%|$TnT_F7Q*2J6tgE)_;B@;fn1!C#uC`)LyR^Q?fZ~ZSYUA(XE6zxR3IVF% zgz%fKVdsp+B$GaI&hkz$g9>?#_WJ literal 0 HcmV?d00001 diff --git a/white_patch_detect/capstone-master/functions.mk b/white_patch_detect/capstone-master/functions.mk new file mode 100644 index 0000000..d946cd3 --- /dev/null +++ b/white_patch_detect/capstone-master/functions.mk @@ -0,0 +1,12 @@ +# Capstone Disassembly Engine +# Common functions used by Makefile & tests/Makefile + +define compile + ${CC} ${CFLAGS} -c $< -o $@ +endef + + +define log + @printf " %-7s %s\n" "$(1)" "$(2)" +endef + diff --git a/white_patch_detect/capstone-master/include/capstone/arm.h b/white_patch_detect/capstone-master/include/capstone/arm.h new file mode 100644 index 0000000..21ba5be --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/arm.h @@ -0,0 +1,937 @@ +#ifndef CAPSTONE_ARM_H +#define CAPSTONE_ARM_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// ARM shift type +typedef enum arm_shifter { + ARM_SFT_INVALID = 0, + ARM_SFT_ASR, ///< shift with immediate const + ARM_SFT_LSL, ///< shift with immediate const + ARM_SFT_LSR, ///< shift with immediate const + ARM_SFT_ROR, ///< shift with immediate const + ARM_SFT_RRX, ///< shift with immediate const + ARM_SFT_ASR_REG, ///< shift with register + ARM_SFT_LSL_REG, ///< shift with register + ARM_SFT_LSR_REG, ///< shift with register + ARM_SFT_ROR_REG, ///< shift with register + ARM_SFT_RRX_REG, ///< shift with register +} arm_shifter; + +/// ARM condition code +typedef enum arm_cc { + ARM_CC_INVALID = 0, + ARM_CC_EQ, ///< Equal Equal + ARM_CC_NE, ///< Not equal Not equal, or unordered + ARM_CC_HS, ///< Carry set >, ==, or unordered + ARM_CC_LO, ///< Carry clear Less than + ARM_CC_MI, ///< Minus, negative Less than + ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered + ARM_CC_VS, ///< Overflow Unordered + ARM_CC_VC, ///< No overflow Not unordered + ARM_CC_HI, ///< Unsigned higher Greater than, or unordered + ARM_CC_LS, ///< Unsigned lower or same Less than or equal + ARM_CC_GE, ///< Greater than or equal Greater than or equal + ARM_CC_LT, ///< Less than Less than, or unordered + ARM_CC_GT, ///< Greater than Greater than + ARM_CC_LE, ///< Less than or equal <, ==, or unordered + ARM_CC_AL ///< Always (unconditional) Always (unconditional) +} arm_cc; + +typedef enum arm_sysreg { + /// Special registers for MSR + ARM_SYSREG_INVALID = 0, + + // SPSR* registers can be OR combined + ARM_SYSREG_SPSR_C = 1, + ARM_SYSREG_SPSR_X = 2, + ARM_SYSREG_SPSR_S = 4, + ARM_SYSREG_SPSR_F = 8, + + // CPSR* registers can be OR combined + ARM_SYSREG_CPSR_C = 16, + ARM_SYSREG_CPSR_X = 32, + ARM_SYSREG_CPSR_S = 64, + ARM_SYSREG_CPSR_F = 128, + + // independent registers + ARM_SYSREG_APSR = 256, + ARM_SYSREG_APSR_G, + ARM_SYSREG_APSR_NZCVQ, + ARM_SYSREG_APSR_NZCVQG, + + ARM_SYSREG_IAPSR, + ARM_SYSREG_IAPSR_G, + ARM_SYSREG_IAPSR_NZCVQG, + ARM_SYSREG_IAPSR_NZCVQ, + + ARM_SYSREG_EAPSR, + ARM_SYSREG_EAPSR_G, + ARM_SYSREG_EAPSR_NZCVQG, + ARM_SYSREG_EAPSR_NZCVQ, + + ARM_SYSREG_XPSR, + ARM_SYSREG_XPSR_G, + ARM_SYSREG_XPSR_NZCVQG, + ARM_SYSREG_XPSR_NZCVQ, + + ARM_SYSREG_IPSR, + ARM_SYSREG_EPSR, + ARM_SYSREG_IEPSR, + + ARM_SYSREG_MSP, + ARM_SYSREG_PSP, + ARM_SYSREG_PRIMASK, + ARM_SYSREG_BASEPRI, + ARM_SYSREG_BASEPRI_MAX, + ARM_SYSREG_FAULTMASK, + ARM_SYSREG_CONTROL, + + // Banked Registers + ARM_SYSREG_R8_USR, + ARM_SYSREG_R9_USR, + ARM_SYSREG_R10_USR, + ARM_SYSREG_R11_USR, + ARM_SYSREG_R12_USR, + ARM_SYSREG_SP_USR, + ARM_SYSREG_LR_USR, + ARM_SYSREG_R8_FIQ, + ARM_SYSREG_R9_FIQ, + ARM_SYSREG_R10_FIQ, + ARM_SYSREG_R11_FIQ, + ARM_SYSREG_R12_FIQ, + ARM_SYSREG_SP_FIQ, + ARM_SYSREG_LR_FIQ, + ARM_SYSREG_LR_IRQ, + ARM_SYSREG_SP_IRQ, + ARM_SYSREG_LR_SVC, + ARM_SYSREG_SP_SVC, + ARM_SYSREG_LR_ABT, + ARM_SYSREG_SP_ABT, + ARM_SYSREG_LR_UND, + ARM_SYSREG_SP_UND, + ARM_SYSREG_LR_MON, + ARM_SYSREG_SP_MON, + ARM_SYSREG_ELR_HYP, + ARM_SYSREG_SP_HYP, + + ARM_SYSREG_SPSR_FIQ, + ARM_SYSREG_SPSR_IRQ, + ARM_SYSREG_SPSR_SVC, + ARM_SYSREG_SPSR_ABT, + ARM_SYSREG_SPSR_UND, + ARM_SYSREG_SPSR_MON, + ARM_SYSREG_SPSR_HYP, +} arm_sysreg; + +/// The memory barrier constants map directly to the 4-bit encoding of +/// the option field for Memory Barrier operations. +typedef enum arm_mem_barrier { + ARM_MB_INVALID = 0, + ARM_MB_RESERVED_0, + ARM_MB_OSHLD, + ARM_MB_OSHST, + ARM_MB_OSH, + ARM_MB_RESERVED_4, + ARM_MB_NSHLD, + ARM_MB_NSHST, + ARM_MB_NSH, + ARM_MB_RESERVED_8, + ARM_MB_ISHLD, + ARM_MB_ISHST, + ARM_MB_ISH, + ARM_MB_RESERVED_12, + ARM_MB_LD, + ARM_MB_ST, + ARM_MB_SY, +} arm_mem_barrier; + +/// Operand type for instruction's operands +typedef enum arm_op_type { + ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + ARM_OP_REG, ///< = CS_OP_REG (Register operand). + ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand). + ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand). + ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers) + ARM_OP_PIMM, ///< P-Immediate (coprocessor registers) + ARM_OP_SETEND, ///< operand for SETEND instruction + ARM_OP_SYSREG, ///< MSR/MRS special register operand +} arm_op_type; + +/// Operand type for SETEND instruction +typedef enum arm_setend_type { + ARM_SETEND_INVALID = 0, ///< Uninitialized. + ARM_SETEND_BE, ///< BE operand. + ARM_SETEND_LE, ///< LE operand +} arm_setend_type; + +typedef enum arm_cpsmode_type { + ARM_CPSMODE_INVALID = 0, + ARM_CPSMODE_IE = 2, + ARM_CPSMODE_ID = 3 +} arm_cpsmode_type; + +/// Operand type for SETEND instruction +typedef enum arm_cpsflag_type { + ARM_CPSFLAG_INVALID = 0, + ARM_CPSFLAG_F = 1, + ARM_CPSFLAG_I = 2, + ARM_CPSFLAG_A = 4, + ARM_CPSFLAG_NONE = 16, ///< no flag +} arm_cpsflag_type; + +/// Data type for elements of vector instructions. +typedef enum arm_vectordata_type { + ARM_VECTORDATA_INVALID = 0, + + // Integer type + ARM_VECTORDATA_I8, + ARM_VECTORDATA_I16, + ARM_VECTORDATA_I32, + ARM_VECTORDATA_I64, + + // Signed integer type + ARM_VECTORDATA_S8, + ARM_VECTORDATA_S16, + ARM_VECTORDATA_S32, + ARM_VECTORDATA_S64, + + // Unsigned integer type + ARM_VECTORDATA_U8, + ARM_VECTORDATA_U16, + ARM_VECTORDATA_U32, + ARM_VECTORDATA_U64, + + // Data type for VMUL/VMULL + ARM_VECTORDATA_P8, + + // Floating type + ARM_VECTORDATA_F32, + ARM_VECTORDATA_F64, + + // Convert float <-> float + ARM_VECTORDATA_F16F64, // f16.f64 + ARM_VECTORDATA_F64F16, // f64.f16 + ARM_VECTORDATA_F32F16, // f32.f16 + ARM_VECTORDATA_F16F32, // f32.f16 + ARM_VECTORDATA_F64F32, // f64.f32 + ARM_VECTORDATA_F32F64, // f32.f64 + + // Convert integer <-> float + ARM_VECTORDATA_S32F32, // s32.f32 + ARM_VECTORDATA_U32F32, // u32.f32 + ARM_VECTORDATA_F32S32, // f32.s32 + ARM_VECTORDATA_F32U32, // f32.u32 + ARM_VECTORDATA_F64S16, // f64.s16 + ARM_VECTORDATA_F32S16, // f32.s16 + ARM_VECTORDATA_F64S32, // f64.s32 + ARM_VECTORDATA_S16F64, // s16.f64 + ARM_VECTORDATA_S16F32, // s16.f64 + ARM_VECTORDATA_S32F64, // s32.f64 + ARM_VECTORDATA_U16F64, // u16.f64 + ARM_VECTORDATA_U16F32, // u16.f32 + ARM_VECTORDATA_U32F64, // u32.f64 + ARM_VECTORDATA_F64U16, // f64.u16 + ARM_VECTORDATA_F32U16, // f32.u16 + ARM_VECTORDATA_F64U32, // f64.u32 +} arm_vectordata_type; + +/// ARM registers +typedef enum arm_reg { + ARM_REG_INVALID = 0, + ARM_REG_APSR, + ARM_REG_APSR_NZCV, + ARM_REG_CPSR, + ARM_REG_FPEXC, + ARM_REG_FPINST, + ARM_REG_FPSCR, + ARM_REG_FPSCR_NZCV, + ARM_REG_FPSID, + ARM_REG_ITSTATE, + ARM_REG_LR, + ARM_REG_PC, + ARM_REG_SP, + ARM_REG_SPSR, + ARM_REG_D0, + ARM_REG_D1, + ARM_REG_D2, + ARM_REG_D3, + ARM_REG_D4, + ARM_REG_D5, + ARM_REG_D6, + ARM_REG_D7, + ARM_REG_D8, + ARM_REG_D9, + ARM_REG_D10, + ARM_REG_D11, + ARM_REG_D12, + ARM_REG_D13, + ARM_REG_D14, + ARM_REG_D15, + ARM_REG_D16, + ARM_REG_D17, + ARM_REG_D18, + ARM_REG_D19, + ARM_REG_D20, + ARM_REG_D21, + ARM_REG_D22, + ARM_REG_D23, + ARM_REG_D24, + ARM_REG_D25, + ARM_REG_D26, + ARM_REG_D27, + ARM_REG_D28, + ARM_REG_D29, + ARM_REG_D30, + ARM_REG_D31, + ARM_REG_FPINST2, + ARM_REG_MVFR0, + ARM_REG_MVFR1, + ARM_REG_MVFR2, + ARM_REG_Q0, + ARM_REG_Q1, + ARM_REG_Q2, + ARM_REG_Q3, + ARM_REG_Q4, + ARM_REG_Q5, + ARM_REG_Q6, + ARM_REG_Q7, + ARM_REG_Q8, + ARM_REG_Q9, + ARM_REG_Q10, + ARM_REG_Q11, + ARM_REG_Q12, + ARM_REG_Q13, + ARM_REG_Q14, + ARM_REG_Q15, + ARM_REG_R0, + ARM_REG_R1, + ARM_REG_R2, + ARM_REG_R3, + ARM_REG_R4, + ARM_REG_R5, + ARM_REG_R6, + ARM_REG_R7, + ARM_REG_R8, + ARM_REG_R9, + ARM_REG_R10, + ARM_REG_R11, + ARM_REG_R12, + ARM_REG_S0, + ARM_REG_S1, + ARM_REG_S2, + ARM_REG_S3, + ARM_REG_S4, + ARM_REG_S5, + ARM_REG_S6, + ARM_REG_S7, + ARM_REG_S8, + ARM_REG_S9, + ARM_REG_S10, + ARM_REG_S11, + ARM_REG_S12, + ARM_REG_S13, + ARM_REG_S14, + ARM_REG_S15, + ARM_REG_S16, + ARM_REG_S17, + ARM_REG_S18, + ARM_REG_S19, + ARM_REG_S20, + ARM_REG_S21, + ARM_REG_S22, + ARM_REG_S23, + ARM_REG_S24, + ARM_REG_S25, + ARM_REG_S26, + ARM_REG_S27, + ARM_REG_S28, + ARM_REG_S29, + ARM_REG_S30, + ARM_REG_S31, + + ARM_REG_ENDING, // <-- mark the end of the list or registers + + // alias registers + ARM_REG_R13 = ARM_REG_SP, + ARM_REG_R14 = ARM_REG_LR, + ARM_REG_R15 = ARM_REG_PC, + + ARM_REG_SB = ARM_REG_R9, + ARM_REG_SL = ARM_REG_R10, + ARM_REG_FP = ARM_REG_R11, + ARM_REG_IP = ARM_REG_R12, +} arm_reg; + +/// Instruction's operand referring to memory +/// This is associated with ARM_OP_MEM operand type above +typedef struct arm_op_mem { + arm_reg base; ///< base register + arm_reg index; ///< index register + int scale; ///< scale for index register (can be 1, or -1) + int disp; ///< displacement/offset value + /// left-shift on index register, or 0 if irrelevant + /// NOTE: this value can also be fetched via operand.shift.value + int lshift; +} arm_op_mem; + +/// Instruction operand +typedef struct cs_arm_op { + int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) + + struct { + arm_shifter type; + unsigned int value; + } shift; + + arm_op_type type; ///< operand type + + union { + int reg; ///< register value for REG/SYSREG operand + int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand + double fp; ///< floating point value for FP operand + arm_op_mem mem; ///< base/index/scale/disp value for MEM operand + arm_setend_type setend; ///< SETEND instruction's operand type + }; + + /// in some instructions, an operand can be subtracted or added to + /// the base register, + /// if TRUE, this operand is subtracted. otherwise, it is added. + bool subtracted; + + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// This field is combined of cs_ac_type. + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; + + /// Neon lane index for NEON instructions (or -1 if irrelevant) + int8_t neon_lane; +} cs_arm_op; + +/// Instruction structure +typedef struct cs_arm { + bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions) + int vector_size; ///< Scalar size for vector instructions + arm_vectordata_type vector_data; ///< Data type for elements of vector instructions + arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction + arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction + arm_cc cc; ///< conditional code for this insn + bool update_flags; ///< does this insn update flags? + bool writeback; ///< does this insn write-back? + arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions + + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + + cs_arm_op operands[36]; ///< operands for this instruction. +} cs_arm; + +/// ARM instruction +typedef enum arm_insn { + ARM_INS_INVALID = 0, + + ARM_INS_ADC, + ARM_INS_ADD, + ARM_INS_ADR, + ARM_INS_AESD, + ARM_INS_AESE, + ARM_INS_AESIMC, + ARM_INS_AESMC, + ARM_INS_AND, + ARM_INS_BFC, + ARM_INS_BFI, + ARM_INS_BIC, + ARM_INS_BKPT, + ARM_INS_BL, + ARM_INS_BLX, + ARM_INS_BX, + ARM_INS_BXJ, + ARM_INS_B, + ARM_INS_CDP, + ARM_INS_CDP2, + ARM_INS_CLREX, + ARM_INS_CLZ, + ARM_INS_CMN, + ARM_INS_CMP, + ARM_INS_CPS, + ARM_INS_CRC32B, + ARM_INS_CRC32CB, + ARM_INS_CRC32CH, + ARM_INS_CRC32CW, + ARM_INS_CRC32H, + ARM_INS_CRC32W, + ARM_INS_DBG, + ARM_INS_DMB, + ARM_INS_DSB, + ARM_INS_EOR, + ARM_INS_ERET, + ARM_INS_VMOV, + ARM_INS_FLDMDBX, + ARM_INS_FLDMIAX, + ARM_INS_VMRS, + ARM_INS_FSTMDBX, + ARM_INS_FSTMIAX, + ARM_INS_HINT, + ARM_INS_HLT, + ARM_INS_HVC, + ARM_INS_ISB, + ARM_INS_LDA, + ARM_INS_LDAB, + ARM_INS_LDAEX, + ARM_INS_LDAEXB, + ARM_INS_LDAEXD, + ARM_INS_LDAEXH, + ARM_INS_LDAH, + ARM_INS_LDC2L, + ARM_INS_LDC2, + ARM_INS_LDCL, + ARM_INS_LDC, + ARM_INS_LDMDA, + ARM_INS_LDMDB, + ARM_INS_LDM, + ARM_INS_LDMIB, + ARM_INS_LDRBT, + ARM_INS_LDRB, + ARM_INS_LDRD, + ARM_INS_LDREX, + ARM_INS_LDREXB, + ARM_INS_LDREXD, + ARM_INS_LDREXH, + ARM_INS_LDRH, + ARM_INS_LDRHT, + ARM_INS_LDRSB, + ARM_INS_LDRSBT, + ARM_INS_LDRSH, + ARM_INS_LDRSHT, + ARM_INS_LDRT, + ARM_INS_LDR, + ARM_INS_MCR, + ARM_INS_MCR2, + ARM_INS_MCRR, + ARM_INS_MCRR2, + ARM_INS_MLA, + ARM_INS_MLS, + ARM_INS_MOV, + ARM_INS_MOVT, + ARM_INS_MOVW, + ARM_INS_MRC, + ARM_INS_MRC2, + ARM_INS_MRRC, + ARM_INS_MRRC2, + ARM_INS_MRS, + ARM_INS_MSR, + ARM_INS_MUL, + ARM_INS_MVN, + ARM_INS_ORR, + ARM_INS_PKHBT, + ARM_INS_PKHTB, + ARM_INS_PLDW, + ARM_INS_PLD, + ARM_INS_PLI, + ARM_INS_QADD, + ARM_INS_QADD16, + ARM_INS_QADD8, + ARM_INS_QASX, + ARM_INS_QDADD, + ARM_INS_QDSUB, + ARM_INS_QSAX, + ARM_INS_QSUB, + ARM_INS_QSUB16, + ARM_INS_QSUB8, + ARM_INS_RBIT, + ARM_INS_REV, + ARM_INS_REV16, + ARM_INS_REVSH, + ARM_INS_RFEDA, + ARM_INS_RFEDB, + ARM_INS_RFEIA, + ARM_INS_RFEIB, + ARM_INS_RSB, + ARM_INS_RSC, + ARM_INS_SADD16, + ARM_INS_SADD8, + ARM_INS_SASX, + ARM_INS_SBC, + ARM_INS_SBFX, + ARM_INS_SDIV, + ARM_INS_SEL, + ARM_INS_SETEND, + ARM_INS_SHA1C, + ARM_INS_SHA1H, + ARM_INS_SHA1M, + ARM_INS_SHA1P, + ARM_INS_SHA1SU0, + ARM_INS_SHA1SU1, + ARM_INS_SHA256H, + ARM_INS_SHA256H2, + ARM_INS_SHA256SU0, + ARM_INS_SHA256SU1, + ARM_INS_SHADD16, + ARM_INS_SHADD8, + ARM_INS_SHASX, + ARM_INS_SHSAX, + ARM_INS_SHSUB16, + ARM_INS_SHSUB8, + ARM_INS_SMC, + ARM_INS_SMLABB, + ARM_INS_SMLABT, + ARM_INS_SMLAD, + ARM_INS_SMLADX, + ARM_INS_SMLAL, + ARM_INS_SMLALBB, + ARM_INS_SMLALBT, + ARM_INS_SMLALD, + ARM_INS_SMLALDX, + ARM_INS_SMLALTB, + ARM_INS_SMLALTT, + ARM_INS_SMLATB, + ARM_INS_SMLATT, + ARM_INS_SMLAWB, + ARM_INS_SMLAWT, + ARM_INS_SMLSD, + ARM_INS_SMLSDX, + ARM_INS_SMLSLD, + ARM_INS_SMLSLDX, + ARM_INS_SMMLA, + ARM_INS_SMMLAR, + ARM_INS_SMMLS, + ARM_INS_SMMLSR, + ARM_INS_SMMUL, + ARM_INS_SMMULR, + ARM_INS_SMUAD, + ARM_INS_SMUADX, + ARM_INS_SMULBB, + ARM_INS_SMULBT, + ARM_INS_SMULL, + ARM_INS_SMULTB, + ARM_INS_SMULTT, + ARM_INS_SMULWB, + ARM_INS_SMULWT, + ARM_INS_SMUSD, + ARM_INS_SMUSDX, + ARM_INS_SRSDA, + ARM_INS_SRSDB, + ARM_INS_SRSIA, + ARM_INS_SRSIB, + ARM_INS_SSAT, + ARM_INS_SSAT16, + ARM_INS_SSAX, + ARM_INS_SSUB16, + ARM_INS_SSUB8, + ARM_INS_STC2L, + ARM_INS_STC2, + ARM_INS_STCL, + ARM_INS_STC, + ARM_INS_STL, + ARM_INS_STLB, + ARM_INS_STLEX, + ARM_INS_STLEXB, + ARM_INS_STLEXD, + ARM_INS_STLEXH, + ARM_INS_STLH, + ARM_INS_STMDA, + ARM_INS_STMDB, + ARM_INS_STM, + ARM_INS_STMIB, + ARM_INS_STRBT, + ARM_INS_STRB, + ARM_INS_STRD, + ARM_INS_STREX, + ARM_INS_STREXB, + ARM_INS_STREXD, + ARM_INS_STREXH, + ARM_INS_STRH, + ARM_INS_STRHT, + ARM_INS_STRT, + ARM_INS_STR, + ARM_INS_SUB, + ARM_INS_SVC, + ARM_INS_SWP, + ARM_INS_SWPB, + ARM_INS_SXTAB, + ARM_INS_SXTAB16, + ARM_INS_SXTAH, + ARM_INS_SXTB, + ARM_INS_SXTB16, + ARM_INS_SXTH, + ARM_INS_TEQ, + ARM_INS_TRAP, + ARM_INS_TST, + ARM_INS_UADD16, + ARM_INS_UADD8, + ARM_INS_UASX, + ARM_INS_UBFX, + ARM_INS_UDF, + ARM_INS_UDIV, + ARM_INS_UHADD16, + ARM_INS_UHADD8, + ARM_INS_UHASX, + ARM_INS_UHSAX, + ARM_INS_UHSUB16, + ARM_INS_UHSUB8, + ARM_INS_UMAAL, + ARM_INS_UMLAL, + ARM_INS_UMULL, + ARM_INS_UQADD16, + ARM_INS_UQADD8, + ARM_INS_UQASX, + ARM_INS_UQSAX, + ARM_INS_UQSUB16, + ARM_INS_UQSUB8, + ARM_INS_USAD8, + ARM_INS_USADA8, + ARM_INS_USAT, + ARM_INS_USAT16, + ARM_INS_USAX, + ARM_INS_USUB16, + ARM_INS_USUB8, + ARM_INS_UXTAB, + ARM_INS_UXTAB16, + ARM_INS_UXTAH, + ARM_INS_UXTB, + ARM_INS_UXTB16, + ARM_INS_UXTH, + ARM_INS_VABAL, + ARM_INS_VABA, + ARM_INS_VABDL, + ARM_INS_VABD, + ARM_INS_VABS, + ARM_INS_VACGE, + ARM_INS_VACGT, + ARM_INS_VADD, + ARM_INS_VADDHN, + ARM_INS_VADDL, + ARM_INS_VADDW, + ARM_INS_VAND, + ARM_INS_VBIC, + ARM_INS_VBIF, + ARM_INS_VBIT, + ARM_INS_VBSL, + ARM_INS_VCEQ, + ARM_INS_VCGE, + ARM_INS_VCGT, + ARM_INS_VCLE, + ARM_INS_VCLS, + ARM_INS_VCLT, + ARM_INS_VCLZ, + ARM_INS_VCMP, + ARM_INS_VCMPE, + ARM_INS_VCNT, + ARM_INS_VCVTA, + ARM_INS_VCVTB, + ARM_INS_VCVT, + ARM_INS_VCVTM, + ARM_INS_VCVTN, + ARM_INS_VCVTP, + ARM_INS_VCVTT, + ARM_INS_VDIV, + ARM_INS_VDUP, + ARM_INS_VEOR, + ARM_INS_VEXT, + ARM_INS_VFMA, + ARM_INS_VFMS, + ARM_INS_VFNMA, + ARM_INS_VFNMS, + ARM_INS_VHADD, + ARM_INS_VHSUB, + ARM_INS_VLD1, + ARM_INS_VLD2, + ARM_INS_VLD3, + ARM_INS_VLD4, + ARM_INS_VLDMDB, + ARM_INS_VLDMIA, + ARM_INS_VLDR, + ARM_INS_VMAXNM, + ARM_INS_VMAX, + ARM_INS_VMINNM, + ARM_INS_VMIN, + ARM_INS_VMLA, + ARM_INS_VMLAL, + ARM_INS_VMLS, + ARM_INS_VMLSL, + ARM_INS_VMOVL, + ARM_INS_VMOVN, + ARM_INS_VMSR, + ARM_INS_VMUL, + ARM_INS_VMULL, + ARM_INS_VMVN, + ARM_INS_VNEG, + ARM_INS_VNMLA, + ARM_INS_VNMLS, + ARM_INS_VNMUL, + ARM_INS_VORN, + ARM_INS_VORR, + ARM_INS_VPADAL, + ARM_INS_VPADDL, + ARM_INS_VPADD, + ARM_INS_VPMAX, + ARM_INS_VPMIN, + ARM_INS_VQABS, + ARM_INS_VQADD, + ARM_INS_VQDMLAL, + ARM_INS_VQDMLSL, + ARM_INS_VQDMULH, + ARM_INS_VQDMULL, + ARM_INS_VQMOVUN, + ARM_INS_VQMOVN, + ARM_INS_VQNEG, + ARM_INS_VQRDMULH, + ARM_INS_VQRSHL, + ARM_INS_VQRSHRN, + ARM_INS_VQRSHRUN, + ARM_INS_VQSHL, + ARM_INS_VQSHLU, + ARM_INS_VQSHRN, + ARM_INS_VQSHRUN, + ARM_INS_VQSUB, + ARM_INS_VRADDHN, + ARM_INS_VRECPE, + ARM_INS_VRECPS, + ARM_INS_VREV16, + ARM_INS_VREV32, + ARM_INS_VREV64, + ARM_INS_VRHADD, + ARM_INS_VRINTA, + ARM_INS_VRINTM, + ARM_INS_VRINTN, + ARM_INS_VRINTP, + ARM_INS_VRINTR, + ARM_INS_VRINTX, + ARM_INS_VRINTZ, + ARM_INS_VRSHL, + ARM_INS_VRSHRN, + ARM_INS_VRSHR, + ARM_INS_VRSQRTE, + ARM_INS_VRSQRTS, + ARM_INS_VRSRA, + ARM_INS_VRSUBHN, + ARM_INS_VSELEQ, + ARM_INS_VSELGE, + ARM_INS_VSELGT, + ARM_INS_VSELVS, + ARM_INS_VSHLL, + ARM_INS_VSHL, + ARM_INS_VSHRN, + ARM_INS_VSHR, + ARM_INS_VSLI, + ARM_INS_VSQRT, + ARM_INS_VSRA, + ARM_INS_VSRI, + ARM_INS_VST1, + ARM_INS_VST2, + ARM_INS_VST3, + ARM_INS_VST4, + ARM_INS_VSTMDB, + ARM_INS_VSTMIA, + ARM_INS_VSTR, + ARM_INS_VSUB, + ARM_INS_VSUBHN, + ARM_INS_VSUBL, + ARM_INS_VSUBW, + ARM_INS_VSWP, + ARM_INS_VTBL, + ARM_INS_VTBX, + ARM_INS_VCVTR, + ARM_INS_VTRN, + ARM_INS_VTST, + ARM_INS_VUZP, + ARM_INS_VZIP, + ARM_INS_ADDW, + ARM_INS_ASR, + ARM_INS_DCPS1, + ARM_INS_DCPS2, + ARM_INS_DCPS3, + ARM_INS_IT, + ARM_INS_LSL, + ARM_INS_LSR, + ARM_INS_ORN, + ARM_INS_ROR, + ARM_INS_RRX, + ARM_INS_SUBW, + ARM_INS_TBB, + ARM_INS_TBH, + ARM_INS_CBNZ, + ARM_INS_CBZ, + ARM_INS_POP, + ARM_INS_PUSH, + + // special instructions + ARM_INS_NOP, + ARM_INS_YIELD, + ARM_INS_WFE, + ARM_INS_WFI, + ARM_INS_SEV, + ARM_INS_SEVL, + ARM_INS_VPUSH, + ARM_INS_VPOP, + + ARM_INS_ENDING, // <-- mark the end of the list of instructions +} arm_insn; + +/// Group of ARM instructions +typedef enum arm_insn_group { + ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + ARM_GRP_JUMP, ///< = CS_GRP_JUMP + ARM_GRP_CALL, ///< = CS_GRP_CALL + ARM_GRP_INT = 4, ///< = CS_GRP_INT + ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE + ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + ARM_GRP_CRYPTO = 128, + ARM_GRP_DATABARRIER, + ARM_GRP_DIVIDE, + ARM_GRP_FPARMV8, + ARM_GRP_MULTPRO, + ARM_GRP_NEON, + ARM_GRP_T2EXTRACTPACK, + ARM_GRP_THUMB2DSP, + ARM_GRP_TRUSTZONE, + ARM_GRP_V4T, + ARM_GRP_V5T, + ARM_GRP_V5TE, + ARM_GRP_V6, + ARM_GRP_V6T2, + ARM_GRP_V7, + ARM_GRP_V8, + ARM_GRP_VFP2, + ARM_GRP_VFP3, + ARM_GRP_VFP4, + ARM_GRP_ARM, + ARM_GRP_MCLASS, + ARM_GRP_NOTMCLASS, + ARM_GRP_THUMB, + ARM_GRP_THUMB1ONLY, + ARM_GRP_THUMB2, + ARM_GRP_PREV8, + ARM_GRP_FPVMLX, + ARM_GRP_MULOPS, + ARM_GRP_CRC, + ARM_GRP_DPVFP, + ARM_GRP_V6M, + ARM_GRP_VIRTUALIZATION, + + ARM_GRP_ENDING, +} arm_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/arm64.h b/white_patch_detect/capstone-master/include/capstone/arm64.h new file mode 100644 index 0000000..0309f30 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/arm64.h @@ -0,0 +1,1164 @@ +#ifndef CAPSTONE_ARM64_H +#define CAPSTONE_ARM64_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// ARM64 shift type +typedef enum arm64_shifter { + ARM64_SFT_INVALID = 0, + ARM64_SFT_LSL = 1, + ARM64_SFT_MSL = 2, + ARM64_SFT_LSR = 3, + ARM64_SFT_ASR = 4, + ARM64_SFT_ROR = 5, +} arm64_shifter; + +/// ARM64 extender type +typedef enum arm64_extender { + ARM64_EXT_INVALID = 0, + ARM64_EXT_UXTB = 1, + ARM64_EXT_UXTH = 2, + ARM64_EXT_UXTW = 3, + ARM64_EXT_UXTX = 4, + ARM64_EXT_SXTB = 5, + ARM64_EXT_SXTH = 6, + ARM64_EXT_SXTW = 7, + ARM64_EXT_SXTX = 8, +} arm64_extender; + +/// ARM64 condition code +typedef enum arm64_cc { + ARM64_CC_INVALID = 0, + ARM64_CC_EQ = 1, ///< Equal + ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered + ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered + ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than + ARM64_CC_MI = 5, ///< Minus, negative: Less than + ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered + ARM64_CC_VS = 7, ///< Overflow: Unordered + ARM64_CC_VC = 8, ///< No overflow: Ordered + ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered + ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal + ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal + ARM64_CC_LT = 12, ///< Less than: Less than, or unordered + ARM64_CC_GT = 13, ///< Signed greater than: Greater than + ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered + ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) + ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional) + //< Note the NV exists purely to disassemble 0b1111. Execution + //< is "always". +} arm64_cc; + +/// System registers +typedef enum arm64_sysreg { + // System registers for MRS + ARM64_SYSREG_INVALID = 0, + ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 + ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 + ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 + ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 + ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 + ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 + ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 + ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 + ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 + ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 + ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 + ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 + ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 + ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 + ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 + ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 + ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 + ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 + ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 + ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 + ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 + ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 + ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 + ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 + ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 + ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 + ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 + ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 + ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 + ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 + ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 + ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 + ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 + ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 + ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 + ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 + ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 + ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 + ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 + ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 + ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 + ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 + ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 + ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 + ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 + ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 + ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 + ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 + + // Trace registers + ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000 + ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 + ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 + ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 + ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 + ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 + ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 + ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 + ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 + ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 + ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 + ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 + ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 + ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 + ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 + ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 + ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 + ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 + ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 + ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110 + ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 + ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 + ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 + ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 + ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 + ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 + ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 + ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 + ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 + ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 + ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 + ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 + ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 + ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 + ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 + ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 + + // GICv3 registers + ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 + ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 + ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 + ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 + ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 + ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 + ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 + ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101 +} arm64_sysreg; + +typedef enum arm64_msr_reg { + // System registers for MSR + ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 + ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 + ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 + + // Trace Registers + ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 + ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110 + + // GICv3 registers + ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 + ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 + ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 + ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 + ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 + ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111 +} arm64_msr_reg; + +/// System PState Field (MSR instruction) +typedef enum arm64_pstate { + ARM64_PSTATE_INVALID = 0, + ARM64_PSTATE_SPSEL = 0x05, + ARM64_PSTATE_DAIFSET = 0x1e, + ARM64_PSTATE_DAIFCLR = 0x1f +} arm64_pstate; + +/// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) +typedef enum arm64_vas { + ARM64_VAS_INVALID = 0, + ARM64_VAS_8B, + ARM64_VAS_16B, + ARM64_VAS_4H, + ARM64_VAS_8H, + ARM64_VAS_2S, + ARM64_VAS_4S, + ARM64_VAS_1D, + ARM64_VAS_2D, + ARM64_VAS_1Q, +} arm64_vas; + +/// Vector element size specifier +typedef enum arm64_vess { + ARM64_VESS_INVALID = 0, + ARM64_VESS_B, + ARM64_VESS_H, + ARM64_VESS_S, + ARM64_VESS_D, +} arm64_vess; + +/// Memory barrier operands +typedef enum arm64_barrier_op { + ARM64_BARRIER_INVALID = 0, + ARM64_BARRIER_OSHLD = 0x1, + ARM64_BARRIER_OSHST = 0x2, + ARM64_BARRIER_OSH = 0x3, + ARM64_BARRIER_NSHLD = 0x5, + ARM64_BARRIER_NSHST = 0x6, + ARM64_BARRIER_NSH = 0x7, + ARM64_BARRIER_ISHLD = 0x9, + ARM64_BARRIER_ISHST = 0xa, + ARM64_BARRIER_ISH = 0xb, + ARM64_BARRIER_LD = 0xd, + ARM64_BARRIER_ST = 0xe, + ARM64_BARRIER_SY = 0xf +} arm64_barrier_op; + +/// Operand type for instruction's operands +typedef enum arm64_op_type { + ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + ARM64_OP_REG, ///< = CS_OP_REG (Register operand). + ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand). + ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand). + ARM64_OP_CIMM = 64, ///< C-Immediate + ARM64_OP_REG_MRS, ///< MRS register operand. + ARM64_OP_REG_MSR, ///< MSR register operand. + ARM64_OP_PSTATE, ///< PState operand. + ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions. + ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM). + ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions). +} arm64_op_type; + +/// TLBI operations +typedef enum arm64_tlbi_op { + ARM64_TLBI_INVALID = 0, + ARM64_TLBI_VMALLE1IS, + ARM64_TLBI_VAE1IS, + ARM64_TLBI_ASIDE1IS, + ARM64_TLBI_VAAE1IS, + ARM64_TLBI_VALE1IS, + ARM64_TLBI_VAALE1IS, + ARM64_TLBI_ALLE2IS, + ARM64_TLBI_VAE2IS, + ARM64_TLBI_ALLE1IS, + ARM64_TLBI_VALE2IS, + ARM64_TLBI_VMALLS12E1IS, + ARM64_TLBI_ALLE3IS, + ARM64_TLBI_VAE3IS, + ARM64_TLBI_VALE3IS, + ARM64_TLBI_IPAS2E1IS, + ARM64_TLBI_IPAS2LE1IS, + ARM64_TLBI_IPAS2E1, + ARM64_TLBI_IPAS2LE1, + ARM64_TLBI_VMALLE1, + ARM64_TLBI_VAE1, + ARM64_TLBI_ASIDE1, + ARM64_TLBI_VAAE1, + ARM64_TLBI_VALE1, + ARM64_TLBI_VAALE1, + ARM64_TLBI_ALLE2, + ARM64_TLBI_VAE2, + ARM64_TLBI_ALLE1, + ARM64_TLBI_VALE2, + ARM64_TLBI_VMALLS12E1, + ARM64_TLBI_ALLE3, + ARM64_TLBI_VAE3, + ARM64_TLBI_VALE3, +} arm64_tlbi_op; + +/// AT operations +typedef enum arm64_at_op { + ARM64_AT_S1E1R, + ARM64_AT_S1E1W, + ARM64_AT_S1E0R, + ARM64_AT_S1E0W, + ARM64_AT_S1E2R, + ARM64_AT_S1E2W, + ARM64_AT_S12E1R, + ARM64_AT_S12E1W, + ARM64_AT_S12E0R, + ARM64_AT_S12E0W, + ARM64_AT_S1E3R, + ARM64_AT_S1E3W, +} arm64_at_op; + +/// DC operations +typedef enum arm64_dc_op { + ARM64_DC_INVALID = 0, + ARM64_DC_ZVA, + ARM64_DC_IVAC, + ARM64_DC_ISW, + ARM64_DC_CVAC, + ARM64_DC_CSW, + ARM64_DC_CVAU, + ARM64_DC_CIVAC, + ARM64_DC_CISW, +} arm64_dc_op; + +/// IC operations +typedef enum arm64_ic_op { + ARM64_IC_INVALID = 0, + ARM64_IC_IALLUIS, + ARM64_IC_IALLU, + ARM64_IC_IVAU, +} arm64_ic_op; + +/// Prefetch operations (PRFM) +typedef enum arm64_prefetch_op { + ARM64_PRFM_INVALID = 0, + ARM64_PRFM_PLDL1KEEP = 0x00 + 1, + ARM64_PRFM_PLDL1STRM = 0x01 + 1, + ARM64_PRFM_PLDL2KEEP = 0x02 + 1, + ARM64_PRFM_PLDL2STRM = 0x03 + 1, + ARM64_PRFM_PLDL3KEEP = 0x04 + 1, + ARM64_PRFM_PLDL3STRM = 0x05 + 1, + ARM64_PRFM_PLIL1KEEP = 0x08 + 1, + ARM64_PRFM_PLIL1STRM = 0x09 + 1, + ARM64_PRFM_PLIL2KEEP = 0x0a + 1, + ARM64_PRFM_PLIL2STRM = 0x0b + 1, + ARM64_PRFM_PLIL3KEEP = 0x0c + 1, + ARM64_PRFM_PLIL3STRM = 0x0d + 1, + ARM64_PRFM_PSTL1KEEP = 0x10 + 1, + ARM64_PRFM_PSTL1STRM = 0x11 + 1, + ARM64_PRFM_PSTL2KEEP = 0x12 + 1, + ARM64_PRFM_PSTL2STRM = 0x13 + 1, + ARM64_PRFM_PSTL3KEEP = 0x14 + 1, + ARM64_PRFM_PSTL3STRM = 0x15 + 1, +} arm64_prefetch_op; + + +/// ARM64 registers +typedef enum arm64_reg { + ARM64_REG_INVALID = 0, + + ARM64_REG_X29, + ARM64_REG_X30, + ARM64_REG_NZCV, + ARM64_REG_SP, + ARM64_REG_WSP, + ARM64_REG_WZR, + ARM64_REG_XZR, + ARM64_REG_B0, + ARM64_REG_B1, + ARM64_REG_B2, + ARM64_REG_B3, + ARM64_REG_B4, + ARM64_REG_B5, + ARM64_REG_B6, + ARM64_REG_B7, + ARM64_REG_B8, + ARM64_REG_B9, + ARM64_REG_B10, + ARM64_REG_B11, + ARM64_REG_B12, + ARM64_REG_B13, + ARM64_REG_B14, + ARM64_REG_B15, + ARM64_REG_B16, + ARM64_REG_B17, + ARM64_REG_B18, + ARM64_REG_B19, + ARM64_REG_B20, + ARM64_REG_B21, + ARM64_REG_B22, + ARM64_REG_B23, + ARM64_REG_B24, + ARM64_REG_B25, + ARM64_REG_B26, + ARM64_REG_B27, + ARM64_REG_B28, + ARM64_REG_B29, + ARM64_REG_B30, + ARM64_REG_B31, + ARM64_REG_D0, + ARM64_REG_D1, + ARM64_REG_D2, + ARM64_REG_D3, + ARM64_REG_D4, + ARM64_REG_D5, + ARM64_REG_D6, + ARM64_REG_D7, + ARM64_REG_D8, + ARM64_REG_D9, + ARM64_REG_D10, + ARM64_REG_D11, + ARM64_REG_D12, + ARM64_REG_D13, + ARM64_REG_D14, + ARM64_REG_D15, + ARM64_REG_D16, + ARM64_REG_D17, + ARM64_REG_D18, + ARM64_REG_D19, + ARM64_REG_D20, + ARM64_REG_D21, + ARM64_REG_D22, + ARM64_REG_D23, + ARM64_REG_D24, + ARM64_REG_D25, + ARM64_REG_D26, + ARM64_REG_D27, + ARM64_REG_D28, + ARM64_REG_D29, + ARM64_REG_D30, + ARM64_REG_D31, + ARM64_REG_H0, + ARM64_REG_H1, + ARM64_REG_H2, + ARM64_REG_H3, + ARM64_REG_H4, + ARM64_REG_H5, + ARM64_REG_H6, + ARM64_REG_H7, + ARM64_REG_H8, + ARM64_REG_H9, + ARM64_REG_H10, + ARM64_REG_H11, + ARM64_REG_H12, + ARM64_REG_H13, + ARM64_REG_H14, + ARM64_REG_H15, + ARM64_REG_H16, + ARM64_REG_H17, + ARM64_REG_H18, + ARM64_REG_H19, + ARM64_REG_H20, + ARM64_REG_H21, + ARM64_REG_H22, + ARM64_REG_H23, + ARM64_REG_H24, + ARM64_REG_H25, + ARM64_REG_H26, + ARM64_REG_H27, + ARM64_REG_H28, + ARM64_REG_H29, + ARM64_REG_H30, + ARM64_REG_H31, + ARM64_REG_Q0, + ARM64_REG_Q1, + ARM64_REG_Q2, + ARM64_REG_Q3, + ARM64_REG_Q4, + ARM64_REG_Q5, + ARM64_REG_Q6, + ARM64_REG_Q7, + ARM64_REG_Q8, + ARM64_REG_Q9, + ARM64_REG_Q10, + ARM64_REG_Q11, + ARM64_REG_Q12, + ARM64_REG_Q13, + ARM64_REG_Q14, + ARM64_REG_Q15, + ARM64_REG_Q16, + ARM64_REG_Q17, + ARM64_REG_Q18, + ARM64_REG_Q19, + ARM64_REG_Q20, + ARM64_REG_Q21, + ARM64_REG_Q22, + ARM64_REG_Q23, + ARM64_REG_Q24, + ARM64_REG_Q25, + ARM64_REG_Q26, + ARM64_REG_Q27, + ARM64_REG_Q28, + ARM64_REG_Q29, + ARM64_REG_Q30, + ARM64_REG_Q31, + ARM64_REG_S0, + ARM64_REG_S1, + ARM64_REG_S2, + ARM64_REG_S3, + ARM64_REG_S4, + ARM64_REG_S5, + ARM64_REG_S6, + ARM64_REG_S7, + ARM64_REG_S8, + ARM64_REG_S9, + ARM64_REG_S10, + ARM64_REG_S11, + ARM64_REG_S12, + ARM64_REG_S13, + ARM64_REG_S14, + ARM64_REG_S15, + ARM64_REG_S16, + ARM64_REG_S17, + ARM64_REG_S18, + ARM64_REG_S19, + ARM64_REG_S20, + ARM64_REG_S21, + ARM64_REG_S22, + ARM64_REG_S23, + ARM64_REG_S24, + ARM64_REG_S25, + ARM64_REG_S26, + ARM64_REG_S27, + ARM64_REG_S28, + ARM64_REG_S29, + ARM64_REG_S30, + ARM64_REG_S31, + ARM64_REG_W0, + ARM64_REG_W1, + ARM64_REG_W2, + ARM64_REG_W3, + ARM64_REG_W4, + ARM64_REG_W5, + ARM64_REG_W6, + ARM64_REG_W7, + ARM64_REG_W8, + ARM64_REG_W9, + ARM64_REG_W10, + ARM64_REG_W11, + ARM64_REG_W12, + ARM64_REG_W13, + ARM64_REG_W14, + ARM64_REG_W15, + ARM64_REG_W16, + ARM64_REG_W17, + ARM64_REG_W18, + ARM64_REG_W19, + ARM64_REG_W20, + ARM64_REG_W21, + ARM64_REG_W22, + ARM64_REG_W23, + ARM64_REG_W24, + ARM64_REG_W25, + ARM64_REG_W26, + ARM64_REG_W27, + ARM64_REG_W28, + ARM64_REG_W29, + ARM64_REG_W30, + ARM64_REG_X0, + ARM64_REG_X1, + ARM64_REG_X2, + ARM64_REG_X3, + ARM64_REG_X4, + ARM64_REG_X5, + ARM64_REG_X6, + ARM64_REG_X7, + ARM64_REG_X8, + ARM64_REG_X9, + ARM64_REG_X10, + ARM64_REG_X11, + ARM64_REG_X12, + ARM64_REG_X13, + ARM64_REG_X14, + ARM64_REG_X15, + ARM64_REG_X16, + ARM64_REG_X17, + ARM64_REG_X18, + ARM64_REG_X19, + ARM64_REG_X20, + ARM64_REG_X21, + ARM64_REG_X22, + ARM64_REG_X23, + ARM64_REG_X24, + ARM64_REG_X25, + ARM64_REG_X26, + ARM64_REG_X27, + ARM64_REG_X28, + + ARM64_REG_V0, + ARM64_REG_V1, + ARM64_REG_V2, + ARM64_REG_V3, + ARM64_REG_V4, + ARM64_REG_V5, + ARM64_REG_V6, + ARM64_REG_V7, + ARM64_REG_V8, + ARM64_REG_V9, + ARM64_REG_V10, + ARM64_REG_V11, + ARM64_REG_V12, + ARM64_REG_V13, + ARM64_REG_V14, + ARM64_REG_V15, + ARM64_REG_V16, + ARM64_REG_V17, + ARM64_REG_V18, + ARM64_REG_V19, + ARM64_REG_V20, + ARM64_REG_V21, + ARM64_REG_V22, + ARM64_REG_V23, + ARM64_REG_V24, + ARM64_REG_V25, + ARM64_REG_V26, + ARM64_REG_V27, + ARM64_REG_V28, + ARM64_REG_V29, + ARM64_REG_V30, + ARM64_REG_V31, + + ARM64_REG_ENDING, // <-- mark the end of the list of registers + + // alias registers + + ARM64_REG_IP0 = ARM64_REG_X16, + ARM64_REG_IP1 = ARM64_REG_X17, + ARM64_REG_FP = ARM64_REG_X29, + ARM64_REG_LR = ARM64_REG_X30, +} arm64_reg; + +/// Instruction's operand referring to memory +/// This is associated with ARM64_OP_MEM operand type above +typedef struct arm64_op_mem { + arm64_reg base; ///< base register + arm64_reg index; ///< index register + int32_t disp; ///< displacement/offset value +} arm64_op_mem; + +/// Instruction operand +typedef struct cs_arm64_op { + int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) + arm64_vas vas; ///< Vector Arrangement Specifier + arm64_vess vess; ///< Vector Element Size Specifier + struct { + arm64_shifter type; ///< shifter type of this operand + unsigned int value; ///< shifter value of this operand + } shift; + arm64_extender ext; ///< extender type of this operand + arm64_op_type type; ///< operand type + union { + arm64_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value, or index for C-IMM or IMM operand + double fp; ///< floating point value for FP operand + arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand + arm64_pstate pstate; ///< PState field of MSR instruction. + unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) + arm64_prefetch_op prefetch; ///< PRFM operation. + arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions). + }; + + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// This field is combined of cs_ac_type. + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; +} cs_arm64_op; + +/// Instruction structure +typedef struct cs_arm64 { + arm64_cc cc; ///< conditional code for this insn + bool update_flags; ///< does this insn update flags? + bool writeback; ///< does this insn request writeback? 'True' means 'yes' + + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + + cs_arm64_op operands[8]; ///< operands for this instruction. +} cs_arm64; + +/// ARM64 instruction +typedef enum arm64_insn { + ARM64_INS_INVALID = 0, + + ARM64_INS_ABS, + ARM64_INS_ADC, + ARM64_INS_ADDHN, + ARM64_INS_ADDHN2, + ARM64_INS_ADDP, + ARM64_INS_ADD, + ARM64_INS_ADDV, + ARM64_INS_ADR, + ARM64_INS_ADRP, + ARM64_INS_AESD, + ARM64_INS_AESE, + ARM64_INS_AESIMC, + ARM64_INS_AESMC, + ARM64_INS_AND, + ARM64_INS_ASR, + ARM64_INS_B, + ARM64_INS_BFM, + ARM64_INS_BIC, + ARM64_INS_BIF, + ARM64_INS_BIT, + ARM64_INS_BL, + ARM64_INS_BLR, + ARM64_INS_BR, + ARM64_INS_BRK, + ARM64_INS_BSL, + ARM64_INS_CBNZ, + ARM64_INS_CBZ, + ARM64_INS_CCMN, + ARM64_INS_CCMP, + ARM64_INS_CLREX, + ARM64_INS_CLS, + ARM64_INS_CLZ, + ARM64_INS_CMEQ, + ARM64_INS_CMGE, + ARM64_INS_CMGT, + ARM64_INS_CMHI, + ARM64_INS_CMHS, + ARM64_INS_CMLE, + ARM64_INS_CMLT, + ARM64_INS_CMTST, + ARM64_INS_CNT, + ARM64_INS_MOV, + ARM64_INS_CRC32B, + ARM64_INS_CRC32CB, + ARM64_INS_CRC32CH, + ARM64_INS_CRC32CW, + ARM64_INS_CRC32CX, + ARM64_INS_CRC32H, + ARM64_INS_CRC32W, + ARM64_INS_CRC32X, + ARM64_INS_CSEL, + ARM64_INS_CSINC, + ARM64_INS_CSINV, + ARM64_INS_CSNEG, + ARM64_INS_DCPS1, + ARM64_INS_DCPS2, + ARM64_INS_DCPS3, + ARM64_INS_DMB, + ARM64_INS_DRPS, + ARM64_INS_DSB, + ARM64_INS_DUP, + ARM64_INS_EON, + ARM64_INS_EOR, + ARM64_INS_ERET, + ARM64_INS_EXTR, + ARM64_INS_EXT, + ARM64_INS_FABD, + ARM64_INS_FABS, + ARM64_INS_FACGE, + ARM64_INS_FACGT, + ARM64_INS_FADD, + ARM64_INS_FADDP, + ARM64_INS_FCCMP, + ARM64_INS_FCCMPE, + ARM64_INS_FCMEQ, + ARM64_INS_FCMGE, + ARM64_INS_FCMGT, + ARM64_INS_FCMLE, + ARM64_INS_FCMLT, + ARM64_INS_FCMP, + ARM64_INS_FCMPE, + ARM64_INS_FCSEL, + ARM64_INS_FCVTAS, + ARM64_INS_FCVTAU, + ARM64_INS_FCVT, + ARM64_INS_FCVTL, + ARM64_INS_FCVTL2, + ARM64_INS_FCVTMS, + ARM64_INS_FCVTMU, + ARM64_INS_FCVTNS, + ARM64_INS_FCVTNU, + ARM64_INS_FCVTN, + ARM64_INS_FCVTN2, + ARM64_INS_FCVTPS, + ARM64_INS_FCVTPU, + ARM64_INS_FCVTXN, + ARM64_INS_FCVTXN2, + ARM64_INS_FCVTZS, + ARM64_INS_FCVTZU, + ARM64_INS_FDIV, + ARM64_INS_FMADD, + ARM64_INS_FMAX, + ARM64_INS_FMAXNM, + ARM64_INS_FMAXNMP, + ARM64_INS_FMAXNMV, + ARM64_INS_FMAXP, + ARM64_INS_FMAXV, + ARM64_INS_FMIN, + ARM64_INS_FMINNM, + ARM64_INS_FMINNMP, + ARM64_INS_FMINNMV, + ARM64_INS_FMINP, + ARM64_INS_FMINV, + ARM64_INS_FMLA, + ARM64_INS_FMLS, + ARM64_INS_FMOV, + ARM64_INS_FMSUB, + ARM64_INS_FMUL, + ARM64_INS_FMULX, + ARM64_INS_FNEG, + ARM64_INS_FNMADD, + ARM64_INS_FNMSUB, + ARM64_INS_FNMUL, + ARM64_INS_FRECPE, + ARM64_INS_FRECPS, + ARM64_INS_FRECPX, + ARM64_INS_FRINTA, + ARM64_INS_FRINTI, + ARM64_INS_FRINTM, + ARM64_INS_FRINTN, + ARM64_INS_FRINTP, + ARM64_INS_FRINTX, + ARM64_INS_FRINTZ, + ARM64_INS_FRSQRTE, + ARM64_INS_FRSQRTS, + ARM64_INS_FSQRT, + ARM64_INS_FSUB, + ARM64_INS_HINT, + ARM64_INS_HLT, + ARM64_INS_HVC, + ARM64_INS_INS, + + ARM64_INS_ISB, + ARM64_INS_LD1, + ARM64_INS_LD1R, + ARM64_INS_LD2R, + ARM64_INS_LD2, + ARM64_INS_LD3R, + ARM64_INS_LD3, + ARM64_INS_LD4, + ARM64_INS_LD4R, + + ARM64_INS_LDARB, + ARM64_INS_LDARH, + ARM64_INS_LDAR, + ARM64_INS_LDAXP, + ARM64_INS_LDAXRB, + ARM64_INS_LDAXRH, + ARM64_INS_LDAXR, + ARM64_INS_LDNP, + ARM64_INS_LDP, + ARM64_INS_LDPSW, + ARM64_INS_LDRB, + ARM64_INS_LDR, + ARM64_INS_LDRH, + ARM64_INS_LDRSB, + ARM64_INS_LDRSH, + ARM64_INS_LDRSW, + ARM64_INS_LDTRB, + ARM64_INS_LDTRH, + ARM64_INS_LDTRSB, + + ARM64_INS_LDTRSH, + ARM64_INS_LDTRSW, + ARM64_INS_LDTR, + ARM64_INS_LDURB, + ARM64_INS_LDUR, + ARM64_INS_LDURH, + ARM64_INS_LDURSB, + ARM64_INS_LDURSH, + ARM64_INS_LDURSW, + ARM64_INS_LDXP, + ARM64_INS_LDXRB, + ARM64_INS_LDXRH, + ARM64_INS_LDXR, + ARM64_INS_LSL, + ARM64_INS_LSR, + ARM64_INS_MADD, + ARM64_INS_MLA, + ARM64_INS_MLS, + ARM64_INS_MOVI, + ARM64_INS_MOVK, + ARM64_INS_MOVN, + ARM64_INS_MOVZ, + ARM64_INS_MRS, + ARM64_INS_MSR, + ARM64_INS_MSUB, + ARM64_INS_MUL, + ARM64_INS_MVNI, + ARM64_INS_NEG, + ARM64_INS_NOT, + ARM64_INS_ORN, + ARM64_INS_ORR, + ARM64_INS_PMULL2, + ARM64_INS_PMULL, + ARM64_INS_PMUL, + ARM64_INS_PRFM, + ARM64_INS_PRFUM, + ARM64_INS_RADDHN, + ARM64_INS_RADDHN2, + ARM64_INS_RBIT, + ARM64_INS_RET, + ARM64_INS_REV16, + ARM64_INS_REV32, + ARM64_INS_REV64, + ARM64_INS_REV, + ARM64_INS_ROR, + ARM64_INS_RSHRN2, + ARM64_INS_RSHRN, + ARM64_INS_RSUBHN, + ARM64_INS_RSUBHN2, + ARM64_INS_SABAL2, + ARM64_INS_SABAL, + + ARM64_INS_SABA, + ARM64_INS_SABDL2, + ARM64_INS_SABDL, + ARM64_INS_SABD, + ARM64_INS_SADALP, + ARM64_INS_SADDLP, + ARM64_INS_SADDLV, + ARM64_INS_SADDL2, + ARM64_INS_SADDL, + ARM64_INS_SADDW2, + ARM64_INS_SADDW, + ARM64_INS_SBC, + ARM64_INS_SBFM, + ARM64_INS_SCVTF, + ARM64_INS_SDIV, + ARM64_INS_SHA1C, + ARM64_INS_SHA1H, + ARM64_INS_SHA1M, + ARM64_INS_SHA1P, + ARM64_INS_SHA1SU0, + ARM64_INS_SHA1SU1, + ARM64_INS_SHA256H2, + ARM64_INS_SHA256H, + ARM64_INS_SHA256SU0, + ARM64_INS_SHA256SU1, + ARM64_INS_SHADD, + ARM64_INS_SHLL2, + ARM64_INS_SHLL, + ARM64_INS_SHL, + ARM64_INS_SHRN2, + ARM64_INS_SHRN, + ARM64_INS_SHSUB, + ARM64_INS_SLI, + ARM64_INS_SMADDL, + ARM64_INS_SMAXP, + ARM64_INS_SMAXV, + ARM64_INS_SMAX, + ARM64_INS_SMC, + ARM64_INS_SMINP, + ARM64_INS_SMINV, + ARM64_INS_SMIN, + ARM64_INS_SMLAL2, + ARM64_INS_SMLAL, + ARM64_INS_SMLSL2, + ARM64_INS_SMLSL, + ARM64_INS_SMOV, + ARM64_INS_SMSUBL, + ARM64_INS_SMULH, + ARM64_INS_SMULL2, + ARM64_INS_SMULL, + ARM64_INS_SQABS, + ARM64_INS_SQADD, + ARM64_INS_SQDMLAL, + ARM64_INS_SQDMLAL2, + ARM64_INS_SQDMLSL, + ARM64_INS_SQDMLSL2, + ARM64_INS_SQDMULH, + ARM64_INS_SQDMULL, + ARM64_INS_SQDMULL2, + ARM64_INS_SQNEG, + ARM64_INS_SQRDMULH, + ARM64_INS_SQRSHL, + ARM64_INS_SQRSHRN, + ARM64_INS_SQRSHRN2, + ARM64_INS_SQRSHRUN, + ARM64_INS_SQRSHRUN2, + ARM64_INS_SQSHLU, + ARM64_INS_SQSHL, + ARM64_INS_SQSHRN, + ARM64_INS_SQSHRN2, + ARM64_INS_SQSHRUN, + ARM64_INS_SQSHRUN2, + ARM64_INS_SQSUB, + ARM64_INS_SQXTN2, + ARM64_INS_SQXTN, + ARM64_INS_SQXTUN2, + ARM64_INS_SQXTUN, + ARM64_INS_SRHADD, + ARM64_INS_SRI, + ARM64_INS_SRSHL, + ARM64_INS_SRSHR, + ARM64_INS_SRSRA, + ARM64_INS_SSHLL2, + ARM64_INS_SSHLL, + ARM64_INS_SSHL, + ARM64_INS_SSHR, + ARM64_INS_SSRA, + ARM64_INS_SSUBL2, + ARM64_INS_SSUBL, + ARM64_INS_SSUBW2, + ARM64_INS_SSUBW, + ARM64_INS_ST1, + ARM64_INS_ST2, + ARM64_INS_ST3, + ARM64_INS_ST4, + ARM64_INS_STLRB, + ARM64_INS_STLRH, + ARM64_INS_STLR, + ARM64_INS_STLXP, + ARM64_INS_STLXRB, + ARM64_INS_STLXRH, + ARM64_INS_STLXR, + ARM64_INS_STNP, + ARM64_INS_STP, + ARM64_INS_STRB, + ARM64_INS_STR, + ARM64_INS_STRH, + ARM64_INS_STTRB, + ARM64_INS_STTRH, + ARM64_INS_STTR, + ARM64_INS_STURB, + ARM64_INS_STUR, + ARM64_INS_STURH, + ARM64_INS_STXP, + ARM64_INS_STXRB, + ARM64_INS_STXRH, + ARM64_INS_STXR, + ARM64_INS_SUBHN, + ARM64_INS_SUBHN2, + ARM64_INS_SUB, + ARM64_INS_SUQADD, + ARM64_INS_SVC, + ARM64_INS_SYSL, + ARM64_INS_SYS, + ARM64_INS_TBL, + ARM64_INS_TBNZ, + ARM64_INS_TBX, + ARM64_INS_TBZ, + ARM64_INS_TRN1, + ARM64_INS_TRN2, + ARM64_INS_UABAL2, + ARM64_INS_UABAL, + ARM64_INS_UABA, + ARM64_INS_UABDL2, + ARM64_INS_UABDL, + ARM64_INS_UABD, + ARM64_INS_UADALP, + ARM64_INS_UADDLP, + ARM64_INS_UADDLV, + ARM64_INS_UADDL2, + ARM64_INS_UADDL, + ARM64_INS_UADDW2, + ARM64_INS_UADDW, + ARM64_INS_UBFM, + ARM64_INS_UCVTF, + ARM64_INS_UDIV, + ARM64_INS_UHADD, + ARM64_INS_UHSUB, + ARM64_INS_UMADDL, + ARM64_INS_UMAXP, + ARM64_INS_UMAXV, + ARM64_INS_UMAX, + ARM64_INS_UMINP, + ARM64_INS_UMINV, + ARM64_INS_UMIN, + ARM64_INS_UMLAL2, + ARM64_INS_UMLAL, + ARM64_INS_UMLSL2, + ARM64_INS_UMLSL, + ARM64_INS_UMOV, + ARM64_INS_UMSUBL, + ARM64_INS_UMULH, + ARM64_INS_UMULL2, + ARM64_INS_UMULL, + ARM64_INS_UQADD, + ARM64_INS_UQRSHL, + ARM64_INS_UQRSHRN, + ARM64_INS_UQRSHRN2, + ARM64_INS_UQSHL, + ARM64_INS_UQSHRN, + ARM64_INS_UQSHRN2, + ARM64_INS_UQSUB, + ARM64_INS_UQXTN2, + ARM64_INS_UQXTN, + ARM64_INS_URECPE, + ARM64_INS_URHADD, + ARM64_INS_URSHL, + ARM64_INS_URSHR, + ARM64_INS_URSQRTE, + ARM64_INS_URSRA, + ARM64_INS_USHLL2, + ARM64_INS_USHLL, + ARM64_INS_USHL, + ARM64_INS_USHR, + ARM64_INS_USQADD, + ARM64_INS_USRA, + ARM64_INS_USUBL2, + ARM64_INS_USUBL, + ARM64_INS_USUBW2, + ARM64_INS_USUBW, + ARM64_INS_UZP1, + ARM64_INS_UZP2, + ARM64_INS_XTN2, + ARM64_INS_XTN, + ARM64_INS_ZIP1, + ARM64_INS_ZIP2, + + // alias insn + ARM64_INS_MNEG, + ARM64_INS_UMNEGL, + ARM64_INS_SMNEGL, + ARM64_INS_NOP, + ARM64_INS_YIELD, + ARM64_INS_WFE, + ARM64_INS_WFI, + ARM64_INS_SEV, + ARM64_INS_SEVL, + ARM64_INS_NGC, + ARM64_INS_SBFIZ, + ARM64_INS_UBFIZ, + ARM64_INS_SBFX, + ARM64_INS_UBFX, + ARM64_INS_BFI, + ARM64_INS_BFXIL, + ARM64_INS_CMN, + ARM64_INS_MVN, + ARM64_INS_TST, + ARM64_INS_CSET, + ARM64_INS_CINC, + ARM64_INS_CSETM, + ARM64_INS_CINV, + ARM64_INS_CNEG, + ARM64_INS_SXTB, + ARM64_INS_SXTH, + ARM64_INS_SXTW, + ARM64_INS_CMP, + ARM64_INS_UXTB, + ARM64_INS_UXTH, + ARM64_INS_UXTW, + ARM64_INS_IC, + ARM64_INS_DC, + ARM64_INS_AT, + ARM64_INS_TLBI, + + ARM64_INS_NEGS, + ARM64_INS_NGCS, + + ARM64_INS_ENDING, // <-- mark the end of the list of insn +} arm64_insn; + +/// Group of ARM64 instructions +typedef enum arm64_insn_group { + ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + ARM64_GRP_JUMP, ///< = CS_GRP_JUMP + ARM64_GRP_CALL, + ARM64_GRP_RET, + ARM64_GRP_INT, + ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE + ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + ARM64_GRP_CRYPTO = 128, + ARM64_GRP_FPARMV8, + ARM64_GRP_NEON, + ARM64_GRP_CRC, + + ARM64_GRP_ENDING, // <-- mark the end of the list of groups +} arm64_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/capstone.h b/white_patch_detect/capstone-master/include/capstone/capstone.h new file mode 100644 index 0000000..3ac1edf --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/capstone.h @@ -0,0 +1,771 @@ +#ifndef CAPSTONE_ENGINE_H +#define CAPSTONE_ENGINE_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2016 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#else +#include +#include +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#pragma warning(disable:4100) +#define CAPSTONE_API __cdecl +#ifdef CAPSTONE_SHARED +#define CAPSTONE_EXPORT __declspec(dllexport) +#else // defined(CAPSTONE_STATIC) +#define CAPSTONE_EXPORT +#endif +#else +#define CAPSTONE_API +#if defined(__GNUC__) && !defined(CAPSTONE_STATIC) +#define CAPSTONE_EXPORT __attribute__((visibility("default"))) +#else // defined(CAPSTONE_STATIC) +#define CAPSTONE_EXPORT +#endif +#endif + +#ifdef __GNUC__ +#define CAPSTONE_DEPRECATED __attribute__((deprecated)) +#elif defined(_MSC_VER) +#define CAPSTONE_DEPRECATED __declspec(deprecated) +#else +#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler") +#define CAPSTONE_DEPRECATED +#endif + +// Capstone API version +#define CS_API_MAJOR 5 +#define CS_API_MINOR 0 + +// Version for bleeding edge code of the Github's "next" branch. +// Use this if you want the absolutely latest development code. +// This version number will be bumped up whenever we have a new major change. +#define CS_NEXT_VERSION 5 + +// Capstone package version +#define CS_VERSION_MAJOR CS_API_MAJOR +#define CS_VERSION_MINOR CS_API_MINOR +#define CS_VERSION_EXTRA 0 + +/// Macro to create combined version which can be compared to +/// result of cs_version() API. +#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor) + +/// Maximum size of an instruction mnemonic string. +#define CS_MNEMONIC_SIZE 32 + +// Handle using with all API +typedef size_t csh; + +/// Architecture type +typedef enum cs_arch { + CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2) + CS_ARCH_ARM64, ///< ARM-64, also called AArch64 + CS_ARCH_MIPS, ///< Mips architecture + CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64) + CS_ARCH_PPC, ///< PowerPC architecture + CS_ARCH_SPARC, ///< Sparc architecture + CS_ARCH_SYSZ, ///< SystemZ architecture + CS_ARCH_XCORE, ///< XCore architecture + CS_ARCH_M68K, ///< 68K architecture + CS_ARCH_TMS320C64X, ///< TMS320C64x architecture + CS_ARCH_M680X, ///< 680X architecture + CS_ARCH_EVM, ///< Ethereum architecture + CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502) + CS_ARCH_MAX, + CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() +} cs_arch; + +// Support value to verify diet mode of the engine. +// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled +// in diet mode. +#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1) + +// Support value to verify X86 reduce mode of the engine. +// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled +// in X86 reduce mode. +#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2) + +/// Mode type +typedef enum cs_mode { + CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode) + CS_MODE_ARM = 0, ///< 32-bit ARM + CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86) + CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86) + CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC) + CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2 + CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series + CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM + CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS) + CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA + CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA + CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA + CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc) + CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC) + CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode + CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode + CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode + CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode + CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode + CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode + CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode + CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips) + CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips) + CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode + CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode + CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode + CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode + CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode + CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode + CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode + CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode + CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12 + ///< used on M68HC12/HCS12 + CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode +} cs_mode; + +typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); +typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size); +typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size); +typedef void (CAPSTONE_API *cs_free_t)(void *ptr); +typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap); + + +/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf() +/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf(). +typedef struct cs_opt_mem { + cs_malloc_t malloc; + cs_calloc_t calloc; + cs_realloc_t realloc; + cs_free_t free; + cs_vsnprintf_t vsnprintf; +} cs_opt_mem; + +/// Customize mnemonic for instructions with alternative name. +/// To reset existing customized instruction to its default mnemonic, +/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value +/// for @mnemonic. +typedef struct cs_opt_mnem { + /// ID of instruction to be customized. + unsigned int id; + /// Customized instruction mnemonic. + const char *mnemonic; +} cs_opt_mnem; + +/// Runtime option for the disassembled engine +typedef enum cs_opt_type { + CS_OPT_INVALID = 0, ///< No option specified + CS_OPT_SYNTAX, ///< Assembly output syntax + CS_OPT_DETAIL, ///< Break down instruction structure into details + CS_OPT_MODE, ///< Change engine's mode at run-time + CS_OPT_MEM, ///< User-defined dynamic memory related functions + CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode. + CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option + CS_OPT_MNEMONIC, ///< Customize instruction mnemonic + CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form +} cs_opt_type; + +/// Runtime option value (associated with option type above) +typedef enum cs_opt_value { + CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED. + CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). + CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX). + CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX) + CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX). +} cs_opt_value; + +/// Common instruction operand types - to be consistent across all architectures. +typedef enum cs_op_type { + CS_OP_INVALID = 0, ///< uninitialized/invalid operand. + CS_OP_REG, ///< Register operand. + CS_OP_IMM, ///< Immediate operand. + CS_OP_MEM, ///< Memory operand. + CS_OP_FP, ///< Floating-Point operand. +} cs_op_type; + +/// Common instruction operand access types - to be consistent across all architectures. +/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE +typedef enum cs_ac_type { + CS_AC_INVALID = 0, ///< Uninitialized/invalid access type. + CS_AC_READ = 1 << 0, ///< Operand read from memory or register. + CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register. +} cs_ac_type; + +/// Common instruction groups - to be consistent across all architectures. +typedef enum cs_group_type { + CS_GRP_INVALID = 0, ///< uninitialized/invalid group. + CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps) + CS_GRP_CALL, ///< all call instructions + CS_GRP_RET, ///< all return instructions + CS_GRP_INT, ///< all interrupt instructions (int+syscall) + CS_GRP_IRET, ///< all interrupt return instructions + CS_GRP_PRIVILEGE, ///< all privileged instructions + CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions +} cs_group_type; + +/** + User-defined callback function for SKIPDATA option. + See tests/test_skipdata.c for sample code demonstrating this API. + + @code: the input buffer containing code to be disassembled. + This is the same buffer passed to cs_disasm(). + @code_size: size (in bytes) of the above @code buffer. + @offset: the position of the currently-examining byte in the input + buffer @code mentioned above. + @user_data: user-data passed to cs_option() via @user_data field in + cs_opt_skipdata struct below. + + @return: return number of bytes to skip, or 0 to immediately stop disassembling. +*/ +typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data); + +/// User-customized setup for SKIPDATA option +typedef struct cs_opt_skipdata { + /// Capstone considers data to skip as special "instructions". + /// User can specify the string for this instruction's "mnemonic" here. + /// By default (if @mnemonic is NULL), Capstone use ".byte". + const char *mnemonic; + + /// User-defined callback function to be called when Capstone hits data. + /// If the returned value from this callback is positive (>0), Capstone + /// will skip exactly that number of bytes & continue. Otherwise, if + /// the callback returns 0, Capstone stops disassembling and returns + /// immediately from cs_disasm() + /// NOTE: if this callback pointer is NULL, Capstone would skip a number + /// of bytes depending on architectures, as following: + /// Arm: 2 bytes (Thumb mode) or 4 bytes. + /// Arm64: 4 bytes. + /// Mips: 4 bytes. + /// M680x: 1 byte. + /// PowerPC: 4 bytes. + /// Sparc: 4 bytes. + /// SystemZ: 2 bytes. + /// X86: 1 bytes. + /// XCore: 2 bytes. + /// EVM: 1 bytes. + /// MOS65XX: 1 bytes. + cs_skipdata_cb_t callback; // default value is NULL + + /// User-defined data to be passed to @callback function pointer. + void *user_data; +} cs_opt_skipdata; + + +#include "arm.h" +#include "arm64.h" +#include "m68k.h" +#include "mips.h" +#include "ppc.h" +#include "sparc.h" +#include "systemz.h" +#include "x86.h" +#include "xcore.h" +#include "tms320c64x.h" +#include "m680x.h" +#include "evm.h" +#include "mos65xx.h" + +/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON +/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH)) +/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c +/// if cs_detail changes, in particular if a field is added after the union, +/// then update arch/ARCH/ARCHDisassembler.c accordingly +typedef struct cs_detail { + uint16_t regs_read[16]; ///< list of implicit registers read by this insn + uint8_t regs_read_count; ///< number of implicit registers read by this insn + + uint16_t regs_write[20]; ///< list of implicit registers modified by this insn + uint8_t regs_write_count; ///< number of implicit registers modified by this insn + + uint8_t groups[8]; ///< list of group this instruction belong to + uint8_t groups_count; ///< number of groups this insn belongs to + + /// Architecture-specific instruction info + union { + cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode + cs_arm64 arm64; ///< ARM64 architecture (aka AArch64) + cs_arm arm; ///< ARM architecture (including Thumb/Thumb2) + cs_m68k m68k; ///< M68K architecture + cs_mips mips; ///< MIPS architecture + cs_ppc ppc; ///< PowerPC architecture + cs_sparc sparc; ///< Sparc architecture + cs_sysz sysz; ///< SystemZ architecture + cs_xcore xcore; ///< XCore architecture + cs_tms320c64x tms320c64x; ///< TMS320C64x architecture + cs_m680x m680x; ///< M680X architecture + cs_evm evm; ///< Ethereum architecture + cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502) + }; +} cs_detail; + +/// Detail information of disassembled instruction +#pragma pack(8) +typedef struct cs_insn { + /// Instruction ID (basically a numeric ID for the instruction mnemonic) + /// Find the instruction id in the '[ARCH]_insn' enum in the header file + /// of corresponding architecture, such as 'arm_insn' in arm.h for ARM, + /// 'x86_insn' in x86.h for X86, etc... + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + /// NOTE: in Skipdata mode, "data" instruction has 0 for this id field. + unsigned int id; + + /// Address (EIP) of this instruction + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + uint64_t address; + + /// Size of this instruction + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + uint16_t size; + + /// Machine bytes of this instruction, with number of bytes indicated by @size above + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + uint8_t bytes[24]; + + /// Ascii text of instruction mnemonic + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + char mnemonic[CS_MNEMONIC_SIZE]; + + /// Ascii text of instruction operands + /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF + char op_str[160]; + + /// Pointer to cs_detail. + /// NOTE: detail pointer is only valid when both requirements below are met: + /// (1) CS_OP_DETAIL = CS_OPT_ON + /// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON) + /// + /// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer + /// is not NULL, its content is still irrelevant. + cs_detail *detail; +} cs_insn; +#pragma pack() + +/// Calculate the offset of a disassembled instruction in its buffer, given its position +/// in its array of disassembled insn +/// NOTE: this macro works with position (>=1), not index +#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address) + + +/// All type of errors encountered by Capstone API. +/// These are values returned by cs_errno() +typedef enum cs_err { + CS_ERR_OK = 0, ///< No error: everything was fine + CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter() + CS_ERR_ARCH, ///< Unsupported architecture: cs_open() + CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index() + CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option() + CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open() + CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option() + CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF + CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM) + CS_ERR_VERSION, ///< Unsupported version (bindings) + CS_ERR_DIET, ///< Access irrelevant data in "diet" engine + CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode + CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time) + CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time) + CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time) +} cs_err; + +/** + Return combined API version & major and minor version numbers. + + @major: major number of API version + @minor: minor number of API version + + @return hexical number as (major << 8 | minor), which encodes both + major & minor versions. + NOTE: This returned value can be compared with version number made + with macro CS_MAKE_VERSION + + For example, second API version would return 1 in @major, and 1 in @minor + The return value would be 0x0101 + + NOTE: if you only care about returned value, but not major and minor values, + set both @major & @minor arguments to NULL. +*/ +CAPSTONE_EXPORT +unsigned int CAPSTONE_API cs_version(int *major, int *minor); + + +/** + This API can be used to either ask for archs supported by this library, + or check to see if the library was compile with 'diet' option (or called + in 'diet' mode). + + To check if a particular arch is supported by this library, set @query to + arch mode (CS_ARCH_* value). + To verify if this library supports all the archs, use CS_ARCH_ALL. + + To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET. + + @return True if this library supports the given arch, or in 'diet' mode. +*/ +CAPSTONE_EXPORT +bool CAPSTONE_API cs_support(int query); + +/** + Initialize CS handle: this must be done before any usage of CS. + + @arch: architecture type (CS_ARCH_*) + @mode: hardware mode. This is combined of CS_MODE_* + @handle: pointer to handle, which will be updated at return time + + @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum + for detailed error). +*/ +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle); + +/** + Close CS handle: MUST do to release the handle when it is not used anymore. + NOTE: this must be only called when there is no longer usage of Capstone, + not even access to cs_insn array. The reason is the this API releases some + cached memory, thus access to any Capstone API after cs_close() might crash + your application. + + In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0). + + @handle: pointer to a handle returned by cs_open() + + @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum + for detailed error). +*/ +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_close(csh *handle); + +/** + Set option for disassembling engine at runtime + + @handle: handle returned by cs_open() + @type: type of option to be set + @value: option value corresponding with @type + + @return: CS_ERR_OK on success, or other value on failure. + Refer to cs_err enum for detailed error. + + NOTE: in the case of CS_OPT_MEM, handle's value can be anything, + so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called + even before cs_open() +*/ +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value); + +/** + Report the last error number when some API function fail. + Like glibc's errno, cs_errno might not retain its old value once accessed. + + @handle: handle returned by cs_open() + + @return: error code of cs_err enum type (CS_ERR_*, see above) +*/ +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_errno(csh handle); + + +/** + Return a string describing given error code. + + @code: error code (see CS_ERR_* above) + + @return: returns a pointer to a string that describes the error code + passed in the argument @code +*/ +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_strerror(cs_err code); + +/** + Disassemble binary code, given the code buffer, size, address and number + of instructions to be decoded. + This API dynamically allocate memory to contain disassembled instruction. + Resulting instructions will be put into @*insn + + NOTE 1: this API will automatically determine memory needed to contain + output disassembled instructions in @insn. + + NOTE 2: caller must free the allocated memory itself to avoid memory leaking. + + NOTE 3: for system with scarce memory to be dynamically allocated such as + OS kernel or firmware, the API cs_disasm_iter() might be a better choice than + cs_disasm(). The reason is that with cs_disasm(), based on limited available + memory, we have to calculate in advance how many instructions to be disassembled, + which complicates things. This is especially troublesome for the case @count=0, + when cs_disasm() runs uncontrollably (until either end of input buffer, or + when it encounters an invalid instruction). + + @handle: handle returned by cs_open() + @code: buffer containing raw binary code to be disassembled. + @code_size: size of the above code buffer. + @address: address of the first instruction in given raw code buffer. + @insn: array of instructions filled in by this API. + NOTE: @insn will be allocated by this function, and should be freed + with cs_free() API. + @count: number of instructions to be disassembled, or 0 to get all of them + + @return: the number of successfully disassembled instructions, + or 0 if this function failed to disassemble the given code + + On failure, call cs_errno() for error code. +*/ +CAPSTONE_EXPORT +size_t CAPSTONE_API cs_disasm(csh handle, + const uint8_t *code, size_t code_size, + uint64_t address, + size_t count, + cs_insn **insn); + +/** + Deprecated function - to be retired in the next version! + Use cs_disasm() instead of cs_disasm_ex() +*/ +CAPSTONE_EXPORT +CAPSTONE_DEPRECATED +size_t CAPSTONE_API cs_disasm_ex(csh handle, + const uint8_t *code, size_t code_size, + uint64_t address, + size_t count, + cs_insn **insn); + +/** + Free memory allocated by cs_malloc() or cs_disasm() (argument @insn) + + @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc() + @count: number of cs_insn structures returned by cs_disasm(), or 1 + to free memory allocated by cs_malloc(). +*/ +CAPSTONE_EXPORT +void CAPSTONE_API cs_free(cs_insn *insn, size_t count); + + +/** + Allocate memory for 1 instruction to be used by cs_disasm_iter(). + + @handle: handle returned by cs_open() + + NOTE: when no longer in use, you can reclaim the memory allocated for + this instruction with cs_free(insn, 1) +*/ +CAPSTONE_EXPORT +cs_insn * CAPSTONE_API cs_malloc(csh handle); + +/** + Fast API to disassemble binary code, given the code buffer, size, address + and number of instructions to be decoded. + This API puts the resulting instruction into a given cache in @insn. + See tests/test_iter.c for sample code demonstrating this API. + + NOTE 1: this API will update @code, @size & @address to point to the next + instruction in the input buffer. Therefore, it is convenient to use + cs_disasm_iter() inside a loop to quickly iterate all the instructions. + While decoding one instruction at a time can also be achieved with + cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30% + faster on random input. + + NOTE 2: the cache in @insn can be created with cs_malloc() API. + + NOTE 3: for system with scarce memory to be dynamically allocated such as + OS kernel or firmware, this API is recommended over cs_disasm(), which + allocates memory based on the number of instructions to be disassembled. + The reason is that with cs_disasm(), based on limited available memory, + we have to calculate in advance how many instructions to be disassembled, + which complicates things. This is especially troublesome for the case + @count=0, when cs_disasm() runs uncontrollably (until either end of input + buffer, or when it encounters an invalid instruction). + + @handle: handle returned by cs_open() + @code: buffer containing raw binary code to be disassembled + @size: size of above code + @address: address of the first insn in given raw code buffer + @insn: pointer to instruction to be filled in by this API. + + @return: true if this API successfully decode 1 instruction, + or false otherwise. + + On failure, call cs_errno() for error code. +*/ +CAPSTONE_EXPORT +bool CAPSTONE_API cs_disasm_iter(csh handle, + const uint8_t **code, size_t *size, + uint64_t *address, cs_insn *insn); + +/** + Return friendly name of register in a string. + Find the instruction id from header file of corresponding architecture (arm.h for ARM, + x86.h for X86, ...) + + WARN: when in 'diet' mode, this API is irrelevant because engine does not + store register name. + + @handle: handle returned by cs_open() + @reg_id: register id + + @return: string name of the register, or NULL if @reg_id is invalid. +*/ +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id); + +/** + Return friendly name of an instruction in a string. + Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + + WARN: when in 'diet' mode, this API is irrelevant because the engine does not + store instruction name. + + @handle: handle returned by cs_open() + @insn_id: instruction id + + @return: string name of the instruction, or NULL if @insn_id is invalid. +*/ +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id); + +/** + Return friendly name of a group id (that an instruction can belong to) + Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + + WARN: when in 'diet' mode, this API is irrelevant because the engine does not + store group name. + + @handle: handle returned by cs_open() + @group_id: group id + + @return: string name of the group, or NULL if @group_id is invalid. +*/ +CAPSTONE_EXPORT +const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id); + +/** + Check if a disassembled instruction belong to a particular group. + Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + Internally, this simply verifies if @group_id matches any member of insn->groups array. + + NOTE: this API is only valid when detail option is ON (which is OFF by default). + + WARN: when in 'diet' mode, this API is irrelevant because the engine does not + update @groups array. + + @handle: handle returned by cs_open() + @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() + @group_id: group that you want to check if this instruction belong to. + + @return: true if this instruction indeed belongs to the given group, or false otherwise. +*/ +CAPSTONE_EXPORT +bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id); + +/** + Check if a disassembled instruction IMPLICITLY used a particular register. + Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + Internally, this simply verifies if @reg_id matches any member of insn->regs_read array. + + NOTE: this API is only valid when detail option is ON (which is OFF by default) + + WARN: when in 'diet' mode, this API is irrelevant because the engine does not + update @regs_read array. + + @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() + @reg_id: register that you want to check if this instruction used it. + + @return: true if this instruction indeed implicitly used the given register, or false otherwise. +*/ +CAPSTONE_EXPORT +bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id); + +/** + Check if a disassembled instruction IMPLICITLY modified a particular register. + Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + Internally, this simply verifies if @reg_id matches any member of insn->regs_write array. + + NOTE: this API is only valid when detail option is ON (which is OFF by default) + + WARN: when in 'diet' mode, this API is irrelevant because the engine does not + update @regs_write array. + + @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() + @reg_id: register that you want to check if this instruction modified it. + + @return: true if this instruction indeed implicitly modified the given register, or false otherwise. +*/ +CAPSTONE_EXPORT +bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id); + +/** + Count the number of operands of a given type. + Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + + NOTE: this API is only valid when detail option is ON (which is OFF by default) + + @handle: handle returned by cs_open() + @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() + @op_type: Operand type to be found. + + @return: number of operands of given type @op_type in instruction @insn, + or -1 on failure. +*/ +CAPSTONE_EXPORT +int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type); + +/** + Retrieve the position of operand of given type in .operands[] array. + Later, the operand can be accessed using the returned position. + Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) + + NOTE: this API is only valid when detail option is ON (which is OFF by default) + + @handle: handle returned by cs_open() + @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() + @op_type: Operand type to be found. + @position: position of the operand to be found. This must be in the range + [1, cs_op_count(handle, insn, op_type)] + + @return: index of operand of given type @op_type in .operands[] array + in instruction @insn, or -1 on failure. +*/ +CAPSTONE_EXPORT +int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, + unsigned int position); + +/// Type of array to keep the list of registers +typedef uint16_t cs_regs[64]; + +/** + Retrieve all the registers accessed by an instruction, either explicitly or + implicitly. + + WARN: when in 'diet' mode, this API is irrelevant because engine does not + store registers. + + @handle: handle returned by cs_open() + @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter() + @regs_read: on return, this array contains all registers read by instruction. + @regs_read_count: number of registers kept inside @regs_read array. + @regs_write: on return, this array contains all registers written by instruction. + @regs_write_count: number of registers kept inside @regs_write array. + + @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum + for detailed error). +*/ +CAPSTONE_EXPORT +cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/evm.h b/white_patch_detect/capstone-master/include/capstone/evm.h new file mode 100644 index 0000000..78fb7c0 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/evm.h @@ -0,0 +1,188 @@ +#ifndef CAPSTONE_EVM_H +#define CAPSTONE_EVM_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2018 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// Instruction structure +typedef struct cs_evm { + unsigned char pop; ///< number of items popped from the stack + unsigned char push; ///< number of items pushed into the stack + unsigned int fee; ///< gas fee for the instruction +} cs_evm; + +/// EVM instruction +typedef enum evm_insn { + EVM_INS_STOP = 0, + EVM_INS_ADD = 1, + EVM_INS_MUL = 2, + EVM_INS_SUB = 3, + EVM_INS_DIV = 4, + EVM_INS_SDIV = 5, + EVM_INS_MOD = 6, + EVM_INS_SMOD = 7, + EVM_INS_ADDMOD = 8, + EVM_INS_MULMOD = 9, + EVM_INS_EXP = 10, + EVM_INS_SIGNEXTEND = 11, + EVM_INS_LT = 16, + EVM_INS_GT = 17, + EVM_INS_SLT = 18, + EVM_INS_SGT = 19, + EVM_INS_EQ = 20, + EVM_INS_ISZERO = 21, + EVM_INS_AND = 22, + EVM_INS_OR = 23, + EVM_INS_XOR = 24, + EVM_INS_NOT = 25, + EVM_INS_BYTE = 26, + EVM_INS_SHA3 = 32, + EVM_INS_ADDRESS = 48, + EVM_INS_BALANCE = 49, + EVM_INS_ORIGIN = 50, + EVM_INS_CALLER = 51, + EVM_INS_CALLVALUE = 52, + EVM_INS_CALLDATALOAD = 53, + EVM_INS_CALLDATASIZE = 54, + EVM_INS_CALLDATACOPY = 55, + EVM_INS_CODESIZE = 56, + EVM_INS_CODECOPY = 57, + EVM_INS_GASPRICE = 58, + EVM_INS_EXTCODESIZE = 59, + EVM_INS_EXTCODECOPY = 60, + EVM_INS_RETURNDATASIZE = 61, + EVM_INS_RETURNDATACOPY = 62, + EVM_INS_BLOCKHASH = 64, + EVM_INS_COINBASE = 65, + EVM_INS_TIMESTAMP = 66, + EVM_INS_NUMBER = 67, + EVM_INS_DIFFICULTY = 68, + EVM_INS_GASLIMIT = 69, + EVM_INS_POP = 80, + EVM_INS_MLOAD = 81, + EVM_INS_MSTORE = 82, + EVM_INS_MSTORE8 = 83, + EVM_INS_SLOAD = 84, + EVM_INS_SSTORE = 85, + EVM_INS_JUMP = 86, + EVM_INS_JUMPI = 87, + EVM_INS_PC = 88, + EVM_INS_MSIZE = 89, + EVM_INS_GAS = 90, + EVM_INS_JUMPDEST = 91, + EVM_INS_PUSH1 = 96, + EVM_INS_PUSH2 = 97, + EVM_INS_PUSH3 = 98, + EVM_INS_PUSH4 = 99, + EVM_INS_PUSH5 = 100, + EVM_INS_PUSH6 = 101, + EVM_INS_PUSH7 = 102, + EVM_INS_PUSH8 = 103, + EVM_INS_PUSH9 = 104, + EVM_INS_PUSH10 = 105, + EVM_INS_PUSH11 = 106, + EVM_INS_PUSH12 = 107, + EVM_INS_PUSH13 = 108, + EVM_INS_PUSH14 = 109, + EVM_INS_PUSH15 = 110, + EVM_INS_PUSH16 = 111, + EVM_INS_PUSH17 = 112, + EVM_INS_PUSH18 = 113, + EVM_INS_PUSH19 = 114, + EVM_INS_PUSH20 = 115, + EVM_INS_PUSH21 = 116, + EVM_INS_PUSH22 = 117, + EVM_INS_PUSH23 = 118, + EVM_INS_PUSH24 = 119, + EVM_INS_PUSH25 = 120, + EVM_INS_PUSH26 = 121, + EVM_INS_PUSH27 = 122, + EVM_INS_PUSH28 = 123, + EVM_INS_PUSH29 = 124, + EVM_INS_PUSH30 = 125, + EVM_INS_PUSH31 = 126, + EVM_INS_PUSH32 = 127, + EVM_INS_DUP1 = 128, + EVM_INS_DUP2 = 129, + EVM_INS_DUP3 = 130, + EVM_INS_DUP4 = 131, + EVM_INS_DUP5 = 132, + EVM_INS_DUP6 = 133, + EVM_INS_DUP7 = 134, + EVM_INS_DUP8 = 135, + EVM_INS_DUP9 = 136, + EVM_INS_DUP10 = 137, + EVM_INS_DUP11 = 138, + EVM_INS_DUP12 = 139, + EVM_INS_DUP13 = 140, + EVM_INS_DUP14 = 141, + EVM_INS_DUP15 = 142, + EVM_INS_DUP16 = 143, + EVM_INS_SWAP1 = 144, + EVM_INS_SWAP2 = 145, + EVM_INS_SWAP3 = 146, + EVM_INS_SWAP4 = 147, + EVM_INS_SWAP5 = 148, + EVM_INS_SWAP6 = 149, + EVM_INS_SWAP7 = 150, + EVM_INS_SWAP8 = 151, + EVM_INS_SWAP9 = 152, + EVM_INS_SWAP10 = 153, + EVM_INS_SWAP11 = 154, + EVM_INS_SWAP12 = 155, + EVM_INS_SWAP13 = 156, + EVM_INS_SWAP14 = 157, + EVM_INS_SWAP15 = 158, + EVM_INS_SWAP16 = 159, + EVM_INS_LOG0 = 160, + EVM_INS_LOG1 = 161, + EVM_INS_LOG2 = 162, + EVM_INS_LOG3 = 163, + EVM_INS_LOG4 = 164, + EVM_INS_CREATE = 240, + EVM_INS_CALL = 241, + EVM_INS_CALLCODE = 242, + EVM_INS_RETURN = 243, + EVM_INS_DELEGATECALL = 244, + EVM_INS_CALLBLACKBOX = 245, + EVM_INS_STATICCALL = 250, + EVM_INS_REVERT = 253, + EVM_INS_SUICIDE = 255, + + EVM_INS_INVALID = 512, + EVM_INS_ENDING, // <-- mark the end of the list of instructions +} evm_insn; + +/// Group of EVM instructions +typedef enum evm_insn_group { + EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + EVM_GRP_JUMP, ///< all jump instructions + + EVM_GRP_MATH = 8, ///< math instructions + EVM_GRP_STACK_WRITE, ///< instructions write to stack + EVM_GRP_STACK_READ, ///< instructions read from stack + EVM_GRP_MEM_WRITE, ///< instructions write to memory + EVM_GRP_MEM_READ, ///< instructions read from memory + EVM_GRP_STORE_WRITE, ///< instructions write to storage + EVM_GRP_STORE_READ, ///< instructions read from storage + EVM_GRP_HALT, ///< instructions halt execution + + EVM_GRP_ENDING, ///< <-- mark the end of the list of groups +} evm_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/m680x.h b/white_patch_detect/capstone-master/include/capstone/m680x.h new file mode 100644 index 0000000..c8296e4 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/m680x.h @@ -0,0 +1,537 @@ +#ifndef CAPSTONE_M680X_H +#define CAPSTONE_M680X_H + +/* Capstone Disassembly Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +#define M680X_OPERAND_COUNT 9 + +/// M680X registers and special registers +typedef enum m680x_reg { + M680X_REG_INVALID = 0, + + M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9 + M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9 + M680X_REG_E, ///< HD6309 + M680X_REG_F, ///< HD6309 + M680X_REG_0, ///< HD6309 + + M680X_REG_D, ///< M6801/3/9, HD6301/9 + M680X_REG_W, ///< HD6309 + + M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9 + M680X_REG_DP, ///< M6809/M6309 + M680X_REG_MD, ///< M6309 + + M680X_REG_HX, ///< M6808 + M680X_REG_H, ///< M6808 + M680X_REG_X, ///< M6800/1/2/3/9, M6301/9 + M680X_REG_Y, ///< M6809/M6309 + M680X_REG_S, ///< M6809/M6309 + M680X_REG_U, ///< M6809/M6309 + M680X_REG_V, ///< M6309 + + M680X_REG_Q, ///< M6309 + + M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9 + + M680X_REG_TMP2, ///< CPU12 + M680X_REG_TMP3, ///< CPU12 + + M680X_REG_ENDING, ///< <-- mark the end of the list of registers +} m680x_reg; + +/// Operand type for instruction's operands +typedef enum m680x_op_type { + M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + M680X_OP_REGISTER, ///< = Register operand. + M680X_OP_IMMEDIATE, ///< = Immediate operand. + M680X_OP_INDEXED, ///< = Indexed addressing operand. + M680X_OP_EXTENDED, ///< = Extended addressing operand. + M680X_OP_DIRECT, ///< = Direct addressing operand. + M680X_OP_RELATIVE, ///< = Relative addressing operand. + M680X_OP_CONSTANT, ///< = constant operand (Displayed as number only). + ///< Used e.g. for a bit index or page number. +} m680x_op_type; + +// Supported bit values for mem.idx.offset_bits +#define M680X_OFFSET_NONE 0 +#define M680X_OFFSET_BITS_5 5 +#define M680X_OFFSET_BITS_8 8 +#define M680X_OFFSET_BITS_9 9 +#define M680X_OFFSET_BITS_16 16 + +// Supported bit flags for mem.idx.flags +// These flags can be combined +#define M680X_IDX_INDIRECT 1 +#define M680X_IDX_NO_COMMA 2 +#define M680X_IDX_POST_INC_DEC 4 + +/// Instruction's operand referring to indexed addressing +typedef struct m680x_op_idx { + m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if + ///< irrelevant) + m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if + ///< irrelevant) + int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits. + uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC. + ///< calculated as offset + PC + uint8_t offset_bits; ///< offset width in bits for indexed addressing + int8_t inc_dec; ///< inc. or dec. value: + ///< 0: no inc-/decrement + ///< 1 .. 8: increment by 1 .. 8 + ///< -1 .. -8: decrement by 1 .. 8 + ///< if flag M680X_IDX_POST_INC_DEC set it is post + ///< inc-/decrement otherwise pre inc-/decrement + uint8_t flags; ///< 8-bit flags (see above) +} m680x_op_idx; + +/// Instruction's memory operand referring to relative addressing (Bcc/LBcc) +typedef struct m680x_op_rel { + uint16_t address; ///< The absolute address. + ///< calculated as PC + offset. PC is the first + ///< address after the instruction. + int16_t offset; ///< the offset/displacement value +} m680x_op_rel; + +/// Instruction's operand referring to extended addressing +typedef struct m680x_op_ext { + uint16_t address; ///< The absolute address + bool indirect; ///< true if extended indirect addressing +} m680x_op_ext; + +/// Instruction operand +typedef struct cs_m680x_op { + m680x_op_type type; + union { + int32_t imm; ///< immediate value for IMM operand + m680x_reg reg; ///< register value for REG operand + m680x_op_idx idx; ///< Indexed addressing operand + m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc) + m680x_op_ext ext; ///< Extended address + uint8_t direct_addr; ///<, 2015-2016 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +#define M68K_OPERAND_COUNT 4 + +/// M68K registers and special registers +typedef enum m68k_reg { + M68K_REG_INVALID = 0, + + M68K_REG_D0, + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + + M68K_REG_A0, + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + + M68K_REG_FP0, + M68K_REG_FP1, + M68K_REG_FP2, + M68K_REG_FP3, + M68K_REG_FP4, + M68K_REG_FP5, + M68K_REG_FP6, + M68K_REG_FP7, + + M68K_REG_PC, + + M68K_REG_SR, + M68K_REG_CCR, + M68K_REG_SFC, + M68K_REG_DFC, + M68K_REG_USP, + M68K_REG_VBR, + M68K_REG_CACR, + M68K_REG_CAAR, + M68K_REG_MSP, + M68K_REG_ISP, + M68K_REG_TC, + M68K_REG_ITT0, + M68K_REG_ITT1, + M68K_REG_DTT0, + M68K_REG_DTT1, + M68K_REG_MMUSR, + M68K_REG_URP, + M68K_REG_SRP, + + M68K_REG_FPCR, + M68K_REG_FPSR, + M68K_REG_FPIAR, + + M68K_REG_ENDING, // <-- mark the end of the list of registers +} m68k_reg; + +/// M68K Addressing Modes +typedef enum m68k_address_mode { + M68K_AM_NONE = 0, ///< No address mode. + + M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data + M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address + + M68K_AM_REGI_ADDR, ///< Register Indirect - Address + M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement + M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement + M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement + + M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement + M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement + + M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex + M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex + + M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement + + M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement + M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement + + M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed + M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed + + M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short + M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long + M68K_AM_IMMEDIATE, ///< Immediate value + + M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches +} m68k_address_mode; + +/// Operand type for instruction's operands +typedef enum m68k_op_type { + M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + M68K_OP_REG, ///< = CS_OP_REG (Register operand). + M68K_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + M68K_OP_MEM, ///< = CS_OP_MEM (Memory operand). + M68K_OP_FP_SINGLE, ///< single precision Floating-Point operand + M68K_OP_FP_DOUBLE, ///< double precision Floating-Point operand + M68K_OP_REG_BITS, ///< Register bits move + M68K_OP_REG_PAIR, ///< Register pair in the same op (upper 4 bits for first reg, lower for second) + M68K_OP_BR_DISP, ///< Branch displacement +} m68k_op_type; + +/// Instruction's operand referring to memory +/// This is associated with M68K_OP_MEM operand type above +typedef struct m68k_op_mem { + m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant) + m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant) + m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant) + uint32_t in_disp; ///< indirect displacement + uint32_t out_disp; ///< other displacement + int16_t disp; ///< displacement value + uint8_t scale; ///< scale for index register + uint8_t bitfield; ///< set to true if the two values below should be used + uint8_t width; ///< used for bf* instructions + uint8_t offset; ///< used for bf* instructions + uint8_t index_size; ///< 0 = w, 1 = l +} m68k_op_mem; + +/// Operand type for instruction's operands +typedef enum m68k_op_br_disp_size { + M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement + M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement + M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement +} m68k_op_br_disp_size; + +typedef struct m68k_op_br_disp { + int32_t disp; ///< displacement value + uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above +} m68k_op_br_disp; + +/// Register pair in one operand. +typedef struct cs_m68k_op_reg_pair { + m68k_reg reg_0; + m68k_reg reg_1; +} cs_m68k_op_reg_pair; + +/// Instruction operand +typedef struct cs_m68k_op { + union { + uint64_t imm; ///< immediate value for IMM operand + double dimm; ///< double imm + float simm; ///< float imm + m68k_reg reg; ///< register value for REG operand + cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand + }; + + m68k_op_mem mem; ///< data when operand is targeting memory + m68k_op_br_disp br_disp; ///< data when operand is a branch displacement + uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order) + m68k_op_type type; + m68k_address_mode address_mode; ///< M68K addressing mode for this op +} cs_m68k_op; + +/// Operation size of the CPU instructions +typedef enum m68k_cpu_size { + M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified + M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size + M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size + M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size +} m68k_cpu_size; + +/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed) +typedef enum m68k_fpu_size { + M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore + M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float) + M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double) + M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format) +} m68k_fpu_size; + +/// Type of size that is being used for the current instruction +typedef enum m68k_size_type { + M68K_SIZE_TYPE_INVALID = 0, + + M68K_SIZE_TYPE_CPU, + M68K_SIZE_TYPE_FPU, +} m68k_size_type; + +/// Operation size of the current instruction (NOT the actually size of instruction) +typedef struct m68k_op_size { + m68k_size_type type; + union { + m68k_cpu_size cpu_size; + m68k_fpu_size fpu_size; + }; +} m68k_op_size; + +/// The M68K instruction and it's operands +typedef struct cs_m68k { + // Number of operands of this instruction or 0 when instruction has no operand. + cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction. + m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc) + uint8_t op_count; ///< number of operands for the instruction +} cs_m68k; + +/// M68K instruction +typedef enum m68k_insn { + M68K_INS_INVALID = 0, + + M68K_INS_ABCD, + M68K_INS_ADD, + M68K_INS_ADDA, + M68K_INS_ADDI, + M68K_INS_ADDQ, + M68K_INS_ADDX, + M68K_INS_AND, + M68K_INS_ANDI, + M68K_INS_ASL, + M68K_INS_ASR, + M68K_INS_BHS, + M68K_INS_BLO, + M68K_INS_BHI, + M68K_INS_BLS, + M68K_INS_BCC, + M68K_INS_BCS, + M68K_INS_BNE, + M68K_INS_BEQ, + M68K_INS_BVC, + M68K_INS_BVS, + M68K_INS_BPL, + M68K_INS_BMI, + M68K_INS_BGE, + M68K_INS_BLT, + M68K_INS_BGT, + M68K_INS_BLE, + M68K_INS_BRA, + M68K_INS_BSR, + M68K_INS_BCHG, + M68K_INS_BCLR, + M68K_INS_BSET, + M68K_INS_BTST, + M68K_INS_BFCHG, + M68K_INS_BFCLR, + M68K_INS_BFEXTS, + M68K_INS_BFEXTU, + M68K_INS_BFFFO, + M68K_INS_BFINS, + M68K_INS_BFSET, + M68K_INS_BFTST, + M68K_INS_BKPT, + M68K_INS_CALLM, + M68K_INS_CAS, + M68K_INS_CAS2, + M68K_INS_CHK, + M68K_INS_CHK2, + M68K_INS_CLR, + M68K_INS_CMP, + M68K_INS_CMPA, + M68K_INS_CMPI, + M68K_INS_CMPM, + M68K_INS_CMP2, + M68K_INS_CINVL, + M68K_INS_CINVP, + M68K_INS_CINVA, + M68K_INS_CPUSHL, + M68K_INS_CPUSHP, + M68K_INS_CPUSHA, + M68K_INS_DBT, + M68K_INS_DBF, + M68K_INS_DBHI, + M68K_INS_DBLS, + M68K_INS_DBCC, + M68K_INS_DBCS, + M68K_INS_DBNE, + M68K_INS_DBEQ, + M68K_INS_DBVC, + M68K_INS_DBVS, + M68K_INS_DBPL, + M68K_INS_DBMI, + M68K_INS_DBGE, + M68K_INS_DBLT, + M68K_INS_DBGT, + M68K_INS_DBLE, + M68K_INS_DBRA, + M68K_INS_DIVS, + M68K_INS_DIVSL, + M68K_INS_DIVU, + M68K_INS_DIVUL, + M68K_INS_EOR, + M68K_INS_EORI, + M68K_INS_EXG, + M68K_INS_EXT, + M68K_INS_EXTB, + M68K_INS_FABS, + M68K_INS_FSABS, + M68K_INS_FDABS, + M68K_INS_FACOS, + M68K_INS_FADD, + M68K_INS_FSADD, + M68K_INS_FDADD, + M68K_INS_FASIN, + M68K_INS_FATAN, + M68K_INS_FATANH, + M68K_INS_FBF, + M68K_INS_FBEQ, + M68K_INS_FBOGT, + M68K_INS_FBOGE, + M68K_INS_FBOLT, + M68K_INS_FBOLE, + M68K_INS_FBOGL, + M68K_INS_FBOR, + M68K_INS_FBUN, + M68K_INS_FBUEQ, + M68K_INS_FBUGT, + M68K_INS_FBUGE, + M68K_INS_FBULT, + M68K_INS_FBULE, + M68K_INS_FBNE, + M68K_INS_FBT, + M68K_INS_FBSF, + M68K_INS_FBSEQ, + M68K_INS_FBGT, + M68K_INS_FBGE, + M68K_INS_FBLT, + M68K_INS_FBLE, + M68K_INS_FBGL, + M68K_INS_FBGLE, + M68K_INS_FBNGLE, + M68K_INS_FBNGL, + M68K_INS_FBNLE, + M68K_INS_FBNLT, + M68K_INS_FBNGE, + M68K_INS_FBNGT, + M68K_INS_FBSNE, + M68K_INS_FBST, + M68K_INS_FCMP, + M68K_INS_FCOS, + M68K_INS_FCOSH, + M68K_INS_FDBF, + M68K_INS_FDBEQ, + M68K_INS_FDBOGT, + M68K_INS_FDBOGE, + M68K_INS_FDBOLT, + M68K_INS_FDBOLE, + M68K_INS_FDBOGL, + M68K_INS_FDBOR, + M68K_INS_FDBUN, + M68K_INS_FDBUEQ, + M68K_INS_FDBUGT, + M68K_INS_FDBUGE, + M68K_INS_FDBULT, + M68K_INS_FDBULE, + M68K_INS_FDBNE, + M68K_INS_FDBT, + M68K_INS_FDBSF, + M68K_INS_FDBSEQ, + M68K_INS_FDBGT, + M68K_INS_FDBGE, + M68K_INS_FDBLT, + M68K_INS_FDBLE, + M68K_INS_FDBGL, + M68K_INS_FDBGLE, + M68K_INS_FDBNGLE, + M68K_INS_FDBNGL, + M68K_INS_FDBNLE, + M68K_INS_FDBNLT, + M68K_INS_FDBNGE, + M68K_INS_FDBNGT, + M68K_INS_FDBSNE, + M68K_INS_FDBST, + M68K_INS_FDIV, + M68K_INS_FSDIV, + M68K_INS_FDDIV, + M68K_INS_FETOX, + M68K_INS_FETOXM1, + M68K_INS_FGETEXP, + M68K_INS_FGETMAN, + M68K_INS_FINT, + M68K_INS_FINTRZ, + M68K_INS_FLOG10, + M68K_INS_FLOG2, + M68K_INS_FLOGN, + M68K_INS_FLOGNP1, + M68K_INS_FMOD, + M68K_INS_FMOVE, + M68K_INS_FSMOVE, + M68K_INS_FDMOVE, + M68K_INS_FMOVECR, + M68K_INS_FMOVEM, + M68K_INS_FMUL, + M68K_INS_FSMUL, + M68K_INS_FDMUL, + M68K_INS_FNEG, + M68K_INS_FSNEG, + M68K_INS_FDNEG, + M68K_INS_FNOP, + M68K_INS_FREM, + M68K_INS_FRESTORE, + M68K_INS_FSAVE, + M68K_INS_FSCALE, + M68K_INS_FSGLDIV, + M68K_INS_FSGLMUL, + M68K_INS_FSIN, + M68K_INS_FSINCOS, + M68K_INS_FSINH, + M68K_INS_FSQRT, + M68K_INS_FSSQRT, + M68K_INS_FDSQRT, + M68K_INS_FSF, + M68K_INS_FSBEQ, + M68K_INS_FSOGT, + M68K_INS_FSOGE, + M68K_INS_FSOLT, + M68K_INS_FSOLE, + M68K_INS_FSOGL, + M68K_INS_FSOR, + M68K_INS_FSUN, + M68K_INS_FSUEQ, + M68K_INS_FSUGT, + M68K_INS_FSUGE, + M68K_INS_FSULT, + M68K_INS_FSULE, + M68K_INS_FSNE, + M68K_INS_FST, + M68K_INS_FSSF, + M68K_INS_FSSEQ, + M68K_INS_FSGT, + M68K_INS_FSGE, + M68K_INS_FSLT, + M68K_INS_FSLE, + M68K_INS_FSGL, + M68K_INS_FSGLE, + M68K_INS_FSNGLE, + M68K_INS_FSNGL, + M68K_INS_FSNLE, + M68K_INS_FSNLT, + M68K_INS_FSNGE, + M68K_INS_FSNGT, + M68K_INS_FSSNE, + M68K_INS_FSST, + M68K_INS_FSUB, + M68K_INS_FSSUB, + M68K_INS_FDSUB, + M68K_INS_FTAN, + M68K_INS_FTANH, + M68K_INS_FTENTOX, + M68K_INS_FTRAPF, + M68K_INS_FTRAPEQ, + M68K_INS_FTRAPOGT, + M68K_INS_FTRAPOGE, + M68K_INS_FTRAPOLT, + M68K_INS_FTRAPOLE, + M68K_INS_FTRAPOGL, + M68K_INS_FTRAPOR, + M68K_INS_FTRAPUN, + M68K_INS_FTRAPUEQ, + M68K_INS_FTRAPUGT, + M68K_INS_FTRAPUGE, + M68K_INS_FTRAPULT, + M68K_INS_FTRAPULE, + M68K_INS_FTRAPNE, + M68K_INS_FTRAPT, + M68K_INS_FTRAPSF, + M68K_INS_FTRAPSEQ, + M68K_INS_FTRAPGT, + M68K_INS_FTRAPGE, + M68K_INS_FTRAPLT, + M68K_INS_FTRAPLE, + M68K_INS_FTRAPGL, + M68K_INS_FTRAPGLE, + M68K_INS_FTRAPNGLE, + M68K_INS_FTRAPNGL, + M68K_INS_FTRAPNLE, + M68K_INS_FTRAPNLT, + M68K_INS_FTRAPNGE, + M68K_INS_FTRAPNGT, + M68K_INS_FTRAPSNE, + M68K_INS_FTRAPST, + M68K_INS_FTST, + M68K_INS_FTWOTOX, + M68K_INS_HALT, + M68K_INS_ILLEGAL, + M68K_INS_JMP, + M68K_INS_JSR, + M68K_INS_LEA, + M68K_INS_LINK, + M68K_INS_LPSTOP, + M68K_INS_LSL, + M68K_INS_LSR, + M68K_INS_MOVE, + M68K_INS_MOVEA, + M68K_INS_MOVEC, + M68K_INS_MOVEM, + M68K_INS_MOVEP, + M68K_INS_MOVEQ, + M68K_INS_MOVES, + M68K_INS_MOVE16, + M68K_INS_MULS, + M68K_INS_MULU, + M68K_INS_NBCD, + M68K_INS_NEG, + M68K_INS_NEGX, + M68K_INS_NOP, + M68K_INS_NOT, + M68K_INS_OR, + M68K_INS_ORI, + M68K_INS_PACK, + M68K_INS_PEA, + M68K_INS_PFLUSH, + M68K_INS_PFLUSHA, + M68K_INS_PFLUSHAN, + M68K_INS_PFLUSHN, + M68K_INS_PLOADR, + M68K_INS_PLOADW, + M68K_INS_PLPAR, + M68K_INS_PLPAW, + M68K_INS_PMOVE, + M68K_INS_PMOVEFD, + M68K_INS_PTESTR, + M68K_INS_PTESTW, + M68K_INS_PULSE, + M68K_INS_REMS, + M68K_INS_REMU, + M68K_INS_RESET, + M68K_INS_ROL, + M68K_INS_ROR, + M68K_INS_ROXL, + M68K_INS_ROXR, + M68K_INS_RTD, + M68K_INS_RTE, + M68K_INS_RTM, + M68K_INS_RTR, + M68K_INS_RTS, + M68K_INS_SBCD, + M68K_INS_ST, + M68K_INS_SF, + M68K_INS_SHI, + M68K_INS_SLS, + M68K_INS_SCC, + M68K_INS_SHS, + M68K_INS_SCS, + M68K_INS_SLO, + M68K_INS_SNE, + M68K_INS_SEQ, + M68K_INS_SVC, + M68K_INS_SVS, + M68K_INS_SPL, + M68K_INS_SMI, + M68K_INS_SGE, + M68K_INS_SLT, + M68K_INS_SGT, + M68K_INS_SLE, + M68K_INS_STOP, + M68K_INS_SUB, + M68K_INS_SUBA, + M68K_INS_SUBI, + M68K_INS_SUBQ, + M68K_INS_SUBX, + M68K_INS_SWAP, + M68K_INS_TAS, + M68K_INS_TRAP, + M68K_INS_TRAPV, + M68K_INS_TRAPT, + M68K_INS_TRAPF, + M68K_INS_TRAPHI, + M68K_INS_TRAPLS, + M68K_INS_TRAPCC, + M68K_INS_TRAPHS, + M68K_INS_TRAPCS, + M68K_INS_TRAPLO, + M68K_INS_TRAPNE, + M68K_INS_TRAPEQ, + M68K_INS_TRAPVC, + M68K_INS_TRAPVS, + M68K_INS_TRAPPL, + M68K_INS_TRAPMI, + M68K_INS_TRAPGE, + M68K_INS_TRAPLT, + M68K_INS_TRAPGT, + M68K_INS_TRAPLE, + M68K_INS_TST, + M68K_INS_UNLK, + M68K_INS_UNPK, + M68K_INS_ENDING, // <-- mark the end of the list of instructions +} m68k_insn; + +/// Group of M68K instructions +typedef enum m68k_group_type { + M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID + M68K_GRP_JUMP, ///< = CS_GRP_JUMP + M68K_GRP_RET = 3, ///< = CS_GRP_RET + M68K_GRP_IRET = 5, ///< = CS_GRP_IRET + M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE + + M68K_GRP_ENDING,// <-- mark the end of the list of groups +} m68k_group_type; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/mips.h b/white_patch_detect/capstone-master/include/capstone/mips.h new file mode 100644 index 0000000..3394456 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/mips.h @@ -0,0 +1,956 @@ +#ifndef CAPSTONE_MIPS_H +#define CAPSTONE_MIPS_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +// GCC MIPS toolchain has a default macro called "mips" which breaks +// compilation +#undef mips + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// Operand type for instruction's operands +typedef enum mips_op_type { + MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + MIPS_OP_REG, ///< = CS_OP_REG (Register operand). + MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} mips_op_type; + +/// MIPS registers +typedef enum mips_reg { + MIPS_REG_INVALID = 0, + // General purpose registers + MIPS_REG_PC, + + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + + // DSP registers + MIPS_REG_DSPCCOND, + MIPS_REG_DSPCARRY, + MIPS_REG_DSPEFI, + MIPS_REG_DSPOUTFLAG, + MIPS_REG_DSPOUTFLAG16_19, + MIPS_REG_DSPOUTFLAG20, + MIPS_REG_DSPOUTFLAG21, + MIPS_REG_DSPOUTFLAG22, + MIPS_REG_DSPOUTFLAG23, + MIPS_REG_DSPPOS, + MIPS_REG_DSPSCOUNT, + + // ACC registers + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + + // COP registers + MIPS_REG_CC0, + MIPS_REG_CC1, + MIPS_REG_CC2, + MIPS_REG_CC3, + MIPS_REG_CC4, + MIPS_REG_CC5, + MIPS_REG_CC6, + MIPS_REG_CC7, + + // FPU registers + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + + MIPS_REG_FCC0, + MIPS_REG_FCC1, + MIPS_REG_FCC2, + MIPS_REG_FCC3, + MIPS_REG_FCC4, + MIPS_REG_FCC5, + MIPS_REG_FCC6, + MIPS_REG_FCC7, + + // AFPR128 + MIPS_REG_W0, + MIPS_REG_W1, + MIPS_REG_W2, + MIPS_REG_W3, + MIPS_REG_W4, + MIPS_REG_W5, + MIPS_REG_W6, + MIPS_REG_W7, + MIPS_REG_W8, + MIPS_REG_W9, + MIPS_REG_W10, + MIPS_REG_W11, + MIPS_REG_W12, + MIPS_REG_W13, + MIPS_REG_W14, + MIPS_REG_W15, + MIPS_REG_W16, + MIPS_REG_W17, + MIPS_REG_W18, + MIPS_REG_W19, + MIPS_REG_W20, + MIPS_REG_W21, + MIPS_REG_W22, + MIPS_REG_W23, + MIPS_REG_W24, + MIPS_REG_W25, + MIPS_REG_W26, + MIPS_REG_W27, + MIPS_REG_W28, + MIPS_REG_W29, + MIPS_REG_W30, + MIPS_REG_W31, + + MIPS_REG_HI, + MIPS_REG_LO, + + MIPS_REG_P0, + MIPS_REG_P1, + MIPS_REG_P2, + + MIPS_REG_MPL0, + MIPS_REG_MPL1, + MIPS_REG_MPL2, + + MIPS_REG_ENDING, // <-- mark the end of the list or registers + + // alias registers + MIPS_REG_ZERO = MIPS_REG_0, + MIPS_REG_AT = MIPS_REG_1, + MIPS_REG_V0 = MIPS_REG_2, + MIPS_REG_V1 = MIPS_REG_3, + MIPS_REG_A0 = MIPS_REG_4, + MIPS_REG_A1 = MIPS_REG_5, + MIPS_REG_A2 = MIPS_REG_6, + MIPS_REG_A3 = MIPS_REG_7, + MIPS_REG_T0 = MIPS_REG_8, + MIPS_REG_T1 = MIPS_REG_9, + MIPS_REG_T2 = MIPS_REG_10, + MIPS_REG_T3 = MIPS_REG_11, + MIPS_REG_T4 = MIPS_REG_12, + MIPS_REG_T5 = MIPS_REG_13, + MIPS_REG_T6 = MIPS_REG_14, + MIPS_REG_T7 = MIPS_REG_15, + MIPS_REG_S0 = MIPS_REG_16, + MIPS_REG_S1 = MIPS_REG_17, + MIPS_REG_S2 = MIPS_REG_18, + MIPS_REG_S3 = MIPS_REG_19, + MIPS_REG_S4 = MIPS_REG_20, + MIPS_REG_S5 = MIPS_REG_21, + MIPS_REG_S6 = MIPS_REG_22, + MIPS_REG_S7 = MIPS_REG_23, + MIPS_REG_T8 = MIPS_REG_24, + MIPS_REG_T9 = MIPS_REG_25, + MIPS_REG_K0 = MIPS_REG_26, + MIPS_REG_K1 = MIPS_REG_27, + MIPS_REG_GP = MIPS_REG_28, + MIPS_REG_SP = MIPS_REG_29, + MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, + MIPS_REG_RA = MIPS_REG_31, + + MIPS_REG_HI0 = MIPS_REG_AC0, + MIPS_REG_HI1 = MIPS_REG_AC1, + MIPS_REG_HI2 = MIPS_REG_AC2, + MIPS_REG_HI3 = MIPS_REG_AC3, + + MIPS_REG_LO0 = MIPS_REG_HI0, + MIPS_REG_LO1 = MIPS_REG_HI1, + MIPS_REG_LO2 = MIPS_REG_HI2, + MIPS_REG_LO3 = MIPS_REG_HI3, +} mips_reg; + +/// Instruction's operand referring to memory +/// This is associated with MIPS_OP_MEM operand type above +typedef struct mips_op_mem { + mips_reg base; ///< base register + int64_t disp; ///< displacement/offset value +} mips_op_mem; + +/// Instruction operand +typedef struct cs_mips_op { + mips_op_type type; ///< operand type + union { + mips_reg reg; ///< register id for REG operand + int64_t imm; ///< immediate value for IMM operand + mips_op_mem mem; ///< base/index/scale/disp value for MEM operand + }; +} cs_mips_op; + +/// Instruction structure +typedef struct cs_mips { + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_mips_op operands[10]; ///< operands for this instruction. +} cs_mips; + +/// MIPS instruction +typedef enum mips_insn { + MIPS_INS_INVALID = 0, + + MIPS_INS_ABSQ_S, + MIPS_INS_ADD, + MIPS_INS_ADDIUPC, + MIPS_INS_ADDIUR1SP, + MIPS_INS_ADDIUR2, + MIPS_INS_ADDIUS5, + MIPS_INS_ADDIUSP, + MIPS_INS_ADDQH, + MIPS_INS_ADDQH_R, + MIPS_INS_ADDQ, + MIPS_INS_ADDQ_S, + MIPS_INS_ADDSC, + MIPS_INS_ADDS_A, + MIPS_INS_ADDS_S, + MIPS_INS_ADDS_U, + MIPS_INS_ADDU16, + MIPS_INS_ADDUH, + MIPS_INS_ADDUH_R, + MIPS_INS_ADDU, + MIPS_INS_ADDU_S, + MIPS_INS_ADDVI, + MIPS_INS_ADDV, + MIPS_INS_ADDWC, + MIPS_INS_ADD_A, + MIPS_INS_ADDI, + MIPS_INS_ADDIU, + MIPS_INS_ALIGN, + MIPS_INS_ALUIPC, + MIPS_INS_AND, + MIPS_INS_AND16, + MIPS_INS_ANDI16, + MIPS_INS_ANDI, + MIPS_INS_APPEND, + MIPS_INS_ASUB_S, + MIPS_INS_ASUB_U, + MIPS_INS_AUI, + MIPS_INS_AUIPC, + MIPS_INS_AVER_S, + MIPS_INS_AVER_U, + MIPS_INS_AVE_S, + MIPS_INS_AVE_U, + MIPS_INS_B16, + MIPS_INS_BADDU, + MIPS_INS_BAL, + MIPS_INS_BALC, + MIPS_INS_BALIGN, + MIPS_INS_BBIT0, + MIPS_INS_BBIT032, + MIPS_INS_BBIT1, + MIPS_INS_BBIT132, + MIPS_INS_BC, + MIPS_INS_BC0F, + MIPS_INS_BC0FL, + MIPS_INS_BC0T, + MIPS_INS_BC0TL, + MIPS_INS_BC1EQZ, + MIPS_INS_BC1F, + MIPS_INS_BC1FL, + MIPS_INS_BC1NEZ, + MIPS_INS_BC1T, + MIPS_INS_BC1TL, + MIPS_INS_BC2EQZ, + MIPS_INS_BC2F, + MIPS_INS_BC2FL, + MIPS_INS_BC2NEZ, + MIPS_INS_BC2T, + MIPS_INS_BC2TL, + MIPS_INS_BC3F, + MIPS_INS_BC3FL, + MIPS_INS_BC3T, + MIPS_INS_BC3TL, + MIPS_INS_BCLRI, + MIPS_INS_BCLR, + MIPS_INS_BEQ, + MIPS_INS_BEQC, + MIPS_INS_BEQL, + MIPS_INS_BEQZ16, + MIPS_INS_BEQZALC, + MIPS_INS_BEQZC, + MIPS_INS_BGEC, + MIPS_INS_BGEUC, + MIPS_INS_BGEZ, + MIPS_INS_BGEZAL, + MIPS_INS_BGEZALC, + MIPS_INS_BGEZALL, + MIPS_INS_BGEZALS, + MIPS_INS_BGEZC, + MIPS_INS_BGEZL, + MIPS_INS_BGTZ, + MIPS_INS_BGTZALC, + MIPS_INS_BGTZC, + MIPS_INS_BGTZL, + MIPS_INS_BINSLI, + MIPS_INS_BINSL, + MIPS_INS_BINSRI, + MIPS_INS_BINSR, + MIPS_INS_BITREV, + MIPS_INS_BITSWAP, + MIPS_INS_BLEZ, + MIPS_INS_BLEZALC, + MIPS_INS_BLEZC, + MIPS_INS_BLEZL, + MIPS_INS_BLTC, + MIPS_INS_BLTUC, + MIPS_INS_BLTZ, + MIPS_INS_BLTZAL, + MIPS_INS_BLTZALC, + MIPS_INS_BLTZALL, + MIPS_INS_BLTZALS, + MIPS_INS_BLTZC, + MIPS_INS_BLTZL, + MIPS_INS_BMNZI, + MIPS_INS_BMNZ, + MIPS_INS_BMZI, + MIPS_INS_BMZ, + MIPS_INS_BNE, + MIPS_INS_BNEC, + MIPS_INS_BNEGI, + MIPS_INS_BNEG, + MIPS_INS_BNEL, + MIPS_INS_BNEZ16, + MIPS_INS_BNEZALC, + MIPS_INS_BNEZC, + MIPS_INS_BNVC, + MIPS_INS_BNZ, + MIPS_INS_BOVC, + MIPS_INS_BPOSGE32, + MIPS_INS_BREAK, + MIPS_INS_BREAK16, + MIPS_INS_BSELI, + MIPS_INS_BSEL, + MIPS_INS_BSETI, + MIPS_INS_BSET, + MIPS_INS_BZ, + MIPS_INS_BEQZ, + MIPS_INS_B, + MIPS_INS_BNEZ, + MIPS_INS_BTEQZ, + MIPS_INS_BTNEZ, + MIPS_INS_CACHE, + MIPS_INS_CEIL, + MIPS_INS_CEQI, + MIPS_INS_CEQ, + MIPS_INS_CFC1, + MIPS_INS_CFCMSA, + MIPS_INS_CINS, + MIPS_INS_CINS32, + MIPS_INS_CLASS, + MIPS_INS_CLEI_S, + MIPS_INS_CLEI_U, + MIPS_INS_CLE_S, + MIPS_INS_CLE_U, + MIPS_INS_CLO, + MIPS_INS_CLTI_S, + MIPS_INS_CLTI_U, + MIPS_INS_CLT_S, + MIPS_INS_CLT_U, + MIPS_INS_CLZ, + MIPS_INS_CMPGDU, + MIPS_INS_CMPGU, + MIPS_INS_CMPU, + MIPS_INS_CMP, + MIPS_INS_COPY_S, + MIPS_INS_COPY_U, + MIPS_INS_CTC1, + MIPS_INS_CTCMSA, + MIPS_INS_CVT, + MIPS_INS_C, + MIPS_INS_CMPI, + MIPS_INS_DADD, + MIPS_INS_DADDI, + MIPS_INS_DADDIU, + MIPS_INS_DADDU, + MIPS_INS_DAHI, + MIPS_INS_DALIGN, + MIPS_INS_DATI, + MIPS_INS_DAUI, + MIPS_INS_DBITSWAP, + MIPS_INS_DCLO, + MIPS_INS_DCLZ, + MIPS_INS_DDIV, + MIPS_INS_DDIVU, + MIPS_INS_DERET, + MIPS_INS_DEXT, + MIPS_INS_DEXTM, + MIPS_INS_DEXTU, + MIPS_INS_DI, + MIPS_INS_DINS, + MIPS_INS_DINSM, + MIPS_INS_DINSU, + MIPS_INS_DIV, + MIPS_INS_DIVU, + MIPS_INS_DIV_S, + MIPS_INS_DIV_U, + MIPS_INS_DLSA, + MIPS_INS_DMFC0, + MIPS_INS_DMFC1, + MIPS_INS_DMFC2, + MIPS_INS_DMOD, + MIPS_INS_DMODU, + MIPS_INS_DMTC0, + MIPS_INS_DMTC1, + MIPS_INS_DMTC2, + MIPS_INS_DMUH, + MIPS_INS_DMUHU, + MIPS_INS_DMUL, + MIPS_INS_DMULT, + MIPS_INS_DMULTU, + MIPS_INS_DMULU, + MIPS_INS_DOTP_S, + MIPS_INS_DOTP_U, + MIPS_INS_DPADD_S, + MIPS_INS_DPADD_U, + MIPS_INS_DPAQX_SA, + MIPS_INS_DPAQX_S, + MIPS_INS_DPAQ_SA, + MIPS_INS_DPAQ_S, + MIPS_INS_DPAU, + MIPS_INS_DPAX, + MIPS_INS_DPA, + MIPS_INS_DPOP, + MIPS_INS_DPSQX_SA, + MIPS_INS_DPSQX_S, + MIPS_INS_DPSQ_SA, + MIPS_INS_DPSQ_S, + MIPS_INS_DPSUB_S, + MIPS_INS_DPSUB_U, + MIPS_INS_DPSU, + MIPS_INS_DPSX, + MIPS_INS_DPS, + MIPS_INS_DROTR, + MIPS_INS_DROTR32, + MIPS_INS_DROTRV, + MIPS_INS_DSBH, + MIPS_INS_DSHD, + MIPS_INS_DSLL, + MIPS_INS_DSLL32, + MIPS_INS_DSLLV, + MIPS_INS_DSRA, + MIPS_INS_DSRA32, + MIPS_INS_DSRAV, + MIPS_INS_DSRL, + MIPS_INS_DSRL32, + MIPS_INS_DSRLV, + MIPS_INS_DSUB, + MIPS_INS_DSUBU, + MIPS_INS_EHB, + MIPS_INS_EI, + MIPS_INS_ERET, + MIPS_INS_EXT, + MIPS_INS_EXTP, + MIPS_INS_EXTPDP, + MIPS_INS_EXTPDPV, + MIPS_INS_EXTPV, + MIPS_INS_EXTRV_RS, + MIPS_INS_EXTRV_R, + MIPS_INS_EXTRV_S, + MIPS_INS_EXTRV, + MIPS_INS_EXTR_RS, + MIPS_INS_EXTR_R, + MIPS_INS_EXTR_S, + MIPS_INS_EXTR, + MIPS_INS_EXTS, + MIPS_INS_EXTS32, + MIPS_INS_ABS, + MIPS_INS_FADD, + MIPS_INS_FCAF, + MIPS_INS_FCEQ, + MIPS_INS_FCLASS, + MIPS_INS_FCLE, + MIPS_INS_FCLT, + MIPS_INS_FCNE, + MIPS_INS_FCOR, + MIPS_INS_FCUEQ, + MIPS_INS_FCULE, + MIPS_INS_FCULT, + MIPS_INS_FCUNE, + MIPS_INS_FCUN, + MIPS_INS_FDIV, + MIPS_INS_FEXDO, + MIPS_INS_FEXP2, + MIPS_INS_FEXUPL, + MIPS_INS_FEXUPR, + MIPS_INS_FFINT_S, + MIPS_INS_FFINT_U, + MIPS_INS_FFQL, + MIPS_INS_FFQR, + MIPS_INS_FILL, + MIPS_INS_FLOG2, + MIPS_INS_FLOOR, + MIPS_INS_FMADD, + MIPS_INS_FMAX_A, + MIPS_INS_FMAX, + MIPS_INS_FMIN_A, + MIPS_INS_FMIN, + MIPS_INS_MOV, + MIPS_INS_FMSUB, + MIPS_INS_FMUL, + MIPS_INS_MUL, + MIPS_INS_NEG, + MIPS_INS_FRCP, + MIPS_INS_FRINT, + MIPS_INS_FRSQRT, + MIPS_INS_FSAF, + MIPS_INS_FSEQ, + MIPS_INS_FSLE, + MIPS_INS_FSLT, + MIPS_INS_FSNE, + MIPS_INS_FSOR, + MIPS_INS_FSQRT, + MIPS_INS_SQRT, + MIPS_INS_FSUB, + MIPS_INS_SUB, + MIPS_INS_FSUEQ, + MIPS_INS_FSULE, + MIPS_INS_FSULT, + MIPS_INS_FSUNE, + MIPS_INS_FSUN, + MIPS_INS_FTINT_S, + MIPS_INS_FTINT_U, + MIPS_INS_FTQ, + MIPS_INS_FTRUNC_S, + MIPS_INS_FTRUNC_U, + MIPS_INS_HADD_S, + MIPS_INS_HADD_U, + MIPS_INS_HSUB_S, + MIPS_INS_HSUB_U, + MIPS_INS_ILVEV, + MIPS_INS_ILVL, + MIPS_INS_ILVOD, + MIPS_INS_ILVR, + MIPS_INS_INS, + MIPS_INS_INSERT, + MIPS_INS_INSV, + MIPS_INS_INSVE, + MIPS_INS_J, + MIPS_INS_JAL, + MIPS_INS_JALR, + MIPS_INS_JALRS16, + MIPS_INS_JALRS, + MIPS_INS_JALS, + MIPS_INS_JALX, + MIPS_INS_JIALC, + MIPS_INS_JIC, + MIPS_INS_JR, + MIPS_INS_JR16, + MIPS_INS_JRADDIUSP, + MIPS_INS_JRC, + MIPS_INS_JALRC, + MIPS_INS_LB, + MIPS_INS_LBU16, + MIPS_INS_LBUX, + MIPS_INS_LBU, + MIPS_INS_LD, + MIPS_INS_LDC1, + MIPS_INS_LDC2, + MIPS_INS_LDC3, + MIPS_INS_LDI, + MIPS_INS_LDL, + MIPS_INS_LDPC, + MIPS_INS_LDR, + MIPS_INS_LDXC1, + MIPS_INS_LH, + MIPS_INS_LHU16, + MIPS_INS_LHX, + MIPS_INS_LHU, + MIPS_INS_LI16, + MIPS_INS_LL, + MIPS_INS_LLD, + MIPS_INS_LSA, + MIPS_INS_LUXC1, + MIPS_INS_LUI, + MIPS_INS_LW, + MIPS_INS_LW16, + MIPS_INS_LWC1, + MIPS_INS_LWC2, + MIPS_INS_LWC3, + MIPS_INS_LWL, + MIPS_INS_LWM16, + MIPS_INS_LWM32, + MIPS_INS_LWPC, + MIPS_INS_LWP, + MIPS_INS_LWR, + MIPS_INS_LWUPC, + MIPS_INS_LWU, + MIPS_INS_LWX, + MIPS_INS_LWXC1, + MIPS_INS_LWXS, + MIPS_INS_LI, + MIPS_INS_MADD, + MIPS_INS_MADDF, + MIPS_INS_MADDR_Q, + MIPS_INS_MADDU, + MIPS_INS_MADDV, + MIPS_INS_MADD_Q, + MIPS_INS_MAQ_SA, + MIPS_INS_MAQ_S, + MIPS_INS_MAXA, + MIPS_INS_MAXI_S, + MIPS_INS_MAXI_U, + MIPS_INS_MAX_A, + MIPS_INS_MAX, + MIPS_INS_MAX_S, + MIPS_INS_MAX_U, + MIPS_INS_MFC0, + MIPS_INS_MFC1, + MIPS_INS_MFC2, + MIPS_INS_MFHC1, + MIPS_INS_MFHI, + MIPS_INS_MFLO, + MIPS_INS_MINA, + MIPS_INS_MINI_S, + MIPS_INS_MINI_U, + MIPS_INS_MIN_A, + MIPS_INS_MIN, + MIPS_INS_MIN_S, + MIPS_INS_MIN_U, + MIPS_INS_MOD, + MIPS_INS_MODSUB, + MIPS_INS_MODU, + MIPS_INS_MOD_S, + MIPS_INS_MOD_U, + MIPS_INS_MOVE, + MIPS_INS_MOVEP, + MIPS_INS_MOVF, + MIPS_INS_MOVN, + MIPS_INS_MOVT, + MIPS_INS_MOVZ, + MIPS_INS_MSUB, + MIPS_INS_MSUBF, + MIPS_INS_MSUBR_Q, + MIPS_INS_MSUBU, + MIPS_INS_MSUBV, + MIPS_INS_MSUB_Q, + MIPS_INS_MTC0, + MIPS_INS_MTC1, + MIPS_INS_MTC2, + MIPS_INS_MTHC1, + MIPS_INS_MTHI, + MIPS_INS_MTHLIP, + MIPS_INS_MTLO, + MIPS_INS_MTM0, + MIPS_INS_MTM1, + MIPS_INS_MTM2, + MIPS_INS_MTP0, + MIPS_INS_MTP1, + MIPS_INS_MTP2, + MIPS_INS_MUH, + MIPS_INS_MUHU, + MIPS_INS_MULEQ_S, + MIPS_INS_MULEU_S, + MIPS_INS_MULQ_RS, + MIPS_INS_MULQ_S, + MIPS_INS_MULR_Q, + MIPS_INS_MULSAQ_S, + MIPS_INS_MULSA, + MIPS_INS_MULT, + MIPS_INS_MULTU, + MIPS_INS_MULU, + MIPS_INS_MULV, + MIPS_INS_MUL_Q, + MIPS_INS_MUL_S, + MIPS_INS_NLOC, + MIPS_INS_NLZC, + MIPS_INS_NMADD, + MIPS_INS_NMSUB, + MIPS_INS_NOR, + MIPS_INS_NORI, + MIPS_INS_NOT16, + MIPS_INS_NOT, + MIPS_INS_OR, + MIPS_INS_OR16, + MIPS_INS_ORI, + MIPS_INS_PACKRL, + MIPS_INS_PAUSE, + MIPS_INS_PCKEV, + MIPS_INS_PCKOD, + MIPS_INS_PCNT, + MIPS_INS_PICK, + MIPS_INS_POP, + MIPS_INS_PRECEQU, + MIPS_INS_PRECEQ, + MIPS_INS_PRECEU, + MIPS_INS_PRECRQU_S, + MIPS_INS_PRECRQ, + MIPS_INS_PRECRQ_RS, + MIPS_INS_PRECR, + MIPS_INS_PRECR_SRA, + MIPS_INS_PRECR_SRA_R, + MIPS_INS_PREF, + MIPS_INS_PREPEND, + MIPS_INS_RADDU, + MIPS_INS_RDDSP, + MIPS_INS_RDHWR, + MIPS_INS_REPLV, + MIPS_INS_REPL, + MIPS_INS_RINT, + MIPS_INS_ROTR, + MIPS_INS_ROTRV, + MIPS_INS_ROUND, + MIPS_INS_SAT_S, + MIPS_INS_SAT_U, + MIPS_INS_SB, + MIPS_INS_SB16, + MIPS_INS_SC, + MIPS_INS_SCD, + MIPS_INS_SD, + MIPS_INS_SDBBP, + MIPS_INS_SDBBP16, + MIPS_INS_SDC1, + MIPS_INS_SDC2, + MIPS_INS_SDC3, + MIPS_INS_SDL, + MIPS_INS_SDR, + MIPS_INS_SDXC1, + MIPS_INS_SEB, + MIPS_INS_SEH, + MIPS_INS_SELEQZ, + MIPS_INS_SELNEZ, + MIPS_INS_SEL, + MIPS_INS_SEQ, + MIPS_INS_SEQI, + MIPS_INS_SH, + MIPS_INS_SH16, + MIPS_INS_SHF, + MIPS_INS_SHILO, + MIPS_INS_SHILOV, + MIPS_INS_SHLLV, + MIPS_INS_SHLLV_S, + MIPS_INS_SHLL, + MIPS_INS_SHLL_S, + MIPS_INS_SHRAV, + MIPS_INS_SHRAV_R, + MIPS_INS_SHRA, + MIPS_INS_SHRA_R, + MIPS_INS_SHRLV, + MIPS_INS_SHRL, + MIPS_INS_SLDI, + MIPS_INS_SLD, + MIPS_INS_SLL, + MIPS_INS_SLL16, + MIPS_INS_SLLI, + MIPS_INS_SLLV, + MIPS_INS_SLT, + MIPS_INS_SLTI, + MIPS_INS_SLTIU, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_SNEI, + MIPS_INS_SPLATI, + MIPS_INS_SPLAT, + MIPS_INS_SRA, + MIPS_INS_SRAI, + MIPS_INS_SRARI, + MIPS_INS_SRAR, + MIPS_INS_SRAV, + MIPS_INS_SRL, + MIPS_INS_SRL16, + MIPS_INS_SRLI, + MIPS_INS_SRLRI, + MIPS_INS_SRLR, + MIPS_INS_SRLV, + MIPS_INS_SSNOP, + MIPS_INS_ST, + MIPS_INS_SUBQH, + MIPS_INS_SUBQH_R, + MIPS_INS_SUBQ, + MIPS_INS_SUBQ_S, + MIPS_INS_SUBSUS_U, + MIPS_INS_SUBSUU_S, + MIPS_INS_SUBS_S, + MIPS_INS_SUBS_U, + MIPS_INS_SUBU16, + MIPS_INS_SUBUH, + MIPS_INS_SUBUH_R, + MIPS_INS_SUBU, + MIPS_INS_SUBU_S, + MIPS_INS_SUBVI, + MIPS_INS_SUBV, + MIPS_INS_SUXC1, + MIPS_INS_SW, + MIPS_INS_SW16, + MIPS_INS_SWC1, + MIPS_INS_SWC2, + MIPS_INS_SWC3, + MIPS_INS_SWL, + MIPS_INS_SWM16, + MIPS_INS_SWM32, + MIPS_INS_SWP, + MIPS_INS_SWR, + MIPS_INS_SWXC1, + MIPS_INS_SYNC, + MIPS_INS_SYNCI, + MIPS_INS_SYSCALL, + MIPS_INS_TEQ, + MIPS_INS_TEQI, + MIPS_INS_TGE, + MIPS_INS_TGEI, + MIPS_INS_TGEIU, + MIPS_INS_TGEU, + MIPS_INS_TLBP, + MIPS_INS_TLBR, + MIPS_INS_TLBWI, + MIPS_INS_TLBWR, + MIPS_INS_TLT, + MIPS_INS_TLTI, + MIPS_INS_TLTIU, + MIPS_INS_TLTU, + MIPS_INS_TNE, + MIPS_INS_TNEI, + MIPS_INS_TRUNC, + MIPS_INS_V3MULU, + MIPS_INS_VMM0, + MIPS_INS_VMULU, + MIPS_INS_VSHF, + MIPS_INS_WAIT, + MIPS_INS_WRDSP, + MIPS_INS_WSBH, + MIPS_INS_XOR, + MIPS_INS_XOR16, + MIPS_INS_XORI, + + //> some alias instructions + MIPS_INS_NOP, + MIPS_INS_NEGU, + + //> special instructions + MIPS_INS_JALR_HB, // jump and link with Hazard Barrier + MIPS_INS_JR_HB, // jump register with Hazard Barrier + + MIPS_INS_ENDING, +} mips_insn; + +/// Group of MIPS instructions +typedef enum mips_insn_group { + MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + MIPS_GRP_JUMP, ///< = CS_GRP_JUMP + // all call instructions + MIPS_GRP_CALL, ///< = CS_GRP_CALL + // all return instructions + MIPS_GRP_RET, ///< = CS_GRP_RET + // all interrupt instructions (int+syscall) + MIPS_GRP_INT, ///< = CS_GRP_INT + // all interrupt return instructions + MIPS_GRP_IRET, ///< = CS_GRP_IRET + // all privileged instructions + MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE + // all relative branching instructions + MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + MIPS_GRP_BITCOUNT = 128, + MIPS_GRP_DSP, + MIPS_GRP_DSPR2, + MIPS_GRP_FPIDX, + MIPS_GRP_MSA, + MIPS_GRP_MIPS32R2, + MIPS_GRP_MIPS64, + MIPS_GRP_MIPS64R2, + MIPS_GRP_SEINREG, + MIPS_GRP_STDENC, + MIPS_GRP_SWAP, + MIPS_GRP_MICROMIPS, + MIPS_GRP_MIPS16MODE, + MIPS_GRP_FP64BIT, + MIPS_GRP_NONANSFPMATH, + MIPS_GRP_NOTFP64BIT, + MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_NOTNACL, + MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_CNMIPS, + MIPS_GRP_MIPS32, + MIPS_GRP_MIPS32R6, + MIPS_GRP_MIPS64R6, + MIPS_GRP_MIPS2, + MIPS_GRP_MIPS3, + MIPS_GRP_MIPS3_32, + MIPS_GRP_MIPS3_32R2, + MIPS_GRP_MIPS4_32, + MIPS_GRP_MIPS4_32R2, + MIPS_GRP_MIPS5_32R2, + MIPS_GRP_GP32BIT, + MIPS_GRP_GP64BIT, + + MIPS_GRP_ENDING, +} mips_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/mos65xx.h b/white_patch_detect/capstone-master/include/capstone/mos65xx.h new file mode 100644 index 0000000..772fba9 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/mos65xx.h @@ -0,0 +1,148 @@ +#ifndef CAPSTONE_MOS65XX_H +#define CAPSTONE_MOS65XX_H + +/* Capstone Disassembly Engine */ +/* By Sebastian Macke C99 is supported +#include +#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE) + +#else +// not MSVC -> C99 is supported +#include +#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) + + +// handle inttypes.h / stdint.h compatibility +#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) +#include "windowsce/stdint.h" +#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) + +#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) +// this system does not have inttypes.h + +#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) +// this system does not have stdint.h +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) + +#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) +#define INT8_MIN (-127i8 - 1) +#define INT16_MIN (-32767i16 - 1) +#define INT32_MIN (-2147483647i32 - 1) +#define INT64_MIN (-9223372036854775807i64 - 1) +#define INT8_MAX 127i8 +#define INT16_MAX 32767i16 +#define INT32_MAX 2147483647i32 +#define INT64_MAX 9223372036854775807i64 +#define UINT8_MAX 0xffui8 +#define UINT16_MAX 0xffffui16 +#define UINT32_MAX 0xffffffffui32 +#define UINT64_MAX 0xffffffffffffffffui64 +#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) + +#ifdef CAPSTONE_HAS_OSXKERNEL +// this system has stdint.h +#include +#endif + +#define __PRI_8_LENGTH_MODIFIER__ "hh" +#define __PRI_64_LENGTH_MODIFIER__ "ll" + +#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" +#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" +#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" +#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" +#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" +#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" + +#define PRId16 "hd" +#define PRIi16 "hi" +#define PRIo16 "ho" +#define PRIu16 "hu" +#define PRIx16 "hx" +#define PRIX16 "hX" + +#if defined(_MSC_VER) && _MSC_VER <= 1700 +#define PRId32 "ld" +#define PRIi32 "li" +#define PRIo32 "lo" +#define PRIu32 "lu" +#define PRIx32 "lx" +#define PRIX32 "lX" +#else // OSX +#define PRId32 "d" +#define PRIi32 "i" +#define PRIo32 "o" +#define PRIu32 "u" +#define PRIx32 "x" +#define PRIX32 "X" +#endif // defined(_MSC_VER) && _MSC_VER <= 1700 + +#if defined(_MSC_VER) && _MSC_VER <= 1700 +// redefine functions from inttypes.h used in cstool +#define strtoull _strtoui64 +#endif + +#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" +#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" +#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" +#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" +#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" +#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" + +#else +// this system has inttypes.h by default +#include +#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/ppc.h b/white_patch_detect/capstone-master/include/capstone/ppc.h new file mode 100644 index 0000000..97ce15b --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/ppc.h @@ -0,0 +1,1463 @@ +#ifndef CAPSTONE_PPC_H +#define CAPSTONE_PPC_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// PPC branch codes for some branch instructions +typedef enum ppc_bc { + PPC_BC_INVALID = 0, + PPC_BC_LT = (0 << 5) | 12, + PPC_BC_LE = (1 << 5) | 4, + PPC_BC_EQ = (2 << 5) | 12, + PPC_BC_GE = (0 << 5) | 4, + PPC_BC_GT = (1 << 5) | 12, + PPC_BC_NE = (2 << 5) | 4, + PPC_BC_UN = (3 << 5) | 12, + PPC_BC_NU = (3 << 5) | 4, + + // extra conditions + PPC_BC_SO = (4 << 5) | 12, ///< summary overflow + PPC_BC_NS = (4 << 5) | 4, ///< not summary overflow +} ppc_bc; + +/// PPC branch hint for some branch instructions +typedef enum ppc_bh { + PPC_BH_INVALID = 0, ///< no hint + PPC_BH_PLUS, ///< PLUS hint + PPC_BH_MINUS, ///< MINUS hint +} ppc_bh; + +/// Operand type for instruction's operands +typedef enum ppc_op_type { + PPC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + PPC_OP_REG, ///< = CS_OP_REG (Register operand). + PPC_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + PPC_OP_MEM, ///< = CS_OP_MEM (Memory operand). + PPC_OP_CRX = 64, ///< Condition Register field +} ppc_op_type; + +/// PPC registers +typedef enum ppc_reg { + PPC_REG_INVALID = 0, + + PPC_REG_CARRY, + PPC_REG_CR0, + PPC_REG_CR1, + PPC_REG_CR2, + PPC_REG_CR3, + PPC_REG_CR4, + PPC_REG_CR5, + PPC_REG_CR6, + PPC_REG_CR7, + PPC_REG_CTR, + PPC_REG_F0, + PPC_REG_F1, + PPC_REG_F2, + PPC_REG_F3, + PPC_REG_F4, + PPC_REG_F5, + PPC_REG_F6, + PPC_REG_F7, + PPC_REG_F8, + PPC_REG_F9, + PPC_REG_F10, + PPC_REG_F11, + PPC_REG_F12, + PPC_REG_F13, + PPC_REG_F14, + PPC_REG_F15, + PPC_REG_F16, + PPC_REG_F17, + PPC_REG_F18, + PPC_REG_F19, + PPC_REG_F20, + PPC_REG_F21, + PPC_REG_F22, + PPC_REG_F23, + PPC_REG_F24, + PPC_REG_F25, + PPC_REG_F26, + PPC_REG_F27, + PPC_REG_F28, + PPC_REG_F29, + PPC_REG_F30, + PPC_REG_F31, + PPC_REG_LR, + PPC_REG_R0, + PPC_REG_R1, + PPC_REG_R2, + PPC_REG_R3, + PPC_REG_R4, + PPC_REG_R5, + PPC_REG_R6, + PPC_REG_R7, + PPC_REG_R8, + PPC_REG_R9, + PPC_REG_R10, + PPC_REG_R11, + PPC_REG_R12, + PPC_REG_R13, + PPC_REG_R14, + PPC_REG_R15, + PPC_REG_R16, + PPC_REG_R17, + PPC_REG_R18, + PPC_REG_R19, + PPC_REG_R20, + PPC_REG_R21, + PPC_REG_R22, + PPC_REG_R23, + PPC_REG_R24, + PPC_REG_R25, + PPC_REG_R26, + PPC_REG_R27, + PPC_REG_R28, + PPC_REG_R29, + PPC_REG_R30, + PPC_REG_R31, + PPC_REG_V0, + PPC_REG_V1, + PPC_REG_V2, + PPC_REG_V3, + PPC_REG_V4, + PPC_REG_V5, + PPC_REG_V6, + PPC_REG_V7, + PPC_REG_V8, + PPC_REG_V9, + PPC_REG_V10, + PPC_REG_V11, + PPC_REG_V12, + PPC_REG_V13, + PPC_REG_V14, + PPC_REG_V15, + PPC_REG_V16, + PPC_REG_V17, + PPC_REG_V18, + PPC_REG_V19, + PPC_REG_V20, + PPC_REG_V21, + PPC_REG_V22, + PPC_REG_V23, + PPC_REG_V24, + PPC_REG_V25, + PPC_REG_V26, + PPC_REG_V27, + PPC_REG_V28, + PPC_REG_V29, + PPC_REG_V30, + PPC_REG_V31, + PPC_REG_VRSAVE, + PPC_REG_VS0, + PPC_REG_VS1, + PPC_REG_VS2, + PPC_REG_VS3, + PPC_REG_VS4, + PPC_REG_VS5, + PPC_REG_VS6, + PPC_REG_VS7, + PPC_REG_VS8, + PPC_REG_VS9, + PPC_REG_VS10, + PPC_REG_VS11, + PPC_REG_VS12, + PPC_REG_VS13, + PPC_REG_VS14, + PPC_REG_VS15, + PPC_REG_VS16, + PPC_REG_VS17, + PPC_REG_VS18, + PPC_REG_VS19, + PPC_REG_VS20, + PPC_REG_VS21, + PPC_REG_VS22, + PPC_REG_VS23, + PPC_REG_VS24, + PPC_REG_VS25, + PPC_REG_VS26, + PPC_REG_VS27, + PPC_REG_VS28, + PPC_REG_VS29, + PPC_REG_VS30, + PPC_REG_VS31, + PPC_REG_VS32, + PPC_REG_VS33, + PPC_REG_VS34, + PPC_REG_VS35, + PPC_REG_VS36, + PPC_REG_VS37, + PPC_REG_VS38, + PPC_REG_VS39, + PPC_REG_VS40, + PPC_REG_VS41, + PPC_REG_VS42, + PPC_REG_VS43, + PPC_REG_VS44, + PPC_REG_VS45, + PPC_REG_VS46, + PPC_REG_VS47, + PPC_REG_VS48, + PPC_REG_VS49, + PPC_REG_VS50, + PPC_REG_VS51, + PPC_REG_VS52, + PPC_REG_VS53, + PPC_REG_VS54, + PPC_REG_VS55, + PPC_REG_VS56, + PPC_REG_VS57, + PPC_REG_VS58, + PPC_REG_VS59, + PPC_REG_VS60, + PPC_REG_VS61, + PPC_REG_VS62, + PPC_REG_VS63, + PPC_REG_Q0, + PPC_REG_Q1, + PPC_REG_Q2, + PPC_REG_Q3, + PPC_REG_Q4, + PPC_REG_Q5, + PPC_REG_Q6, + PPC_REG_Q7, + PPC_REG_Q8, + PPC_REG_Q9, + PPC_REG_Q10, + PPC_REG_Q11, + PPC_REG_Q12, + PPC_REG_Q13, + PPC_REG_Q14, + PPC_REG_Q15, + PPC_REG_Q16, + PPC_REG_Q17, + PPC_REG_Q18, + PPC_REG_Q19, + PPC_REG_Q20, + PPC_REG_Q21, + PPC_REG_Q22, + PPC_REG_Q23, + PPC_REG_Q24, + PPC_REG_Q25, + PPC_REG_Q26, + PPC_REG_Q27, + PPC_REG_Q28, + PPC_REG_Q29, + PPC_REG_Q30, + PPC_REG_Q31, + + // extra registers for PPCMapping.c + PPC_REG_RM, + PPC_REG_CTR8, + PPC_REG_LR8, + PPC_REG_CR1EQ, + PPC_REG_X2, + + PPC_REG_ENDING, // <-- mark the end of the list of registers +} ppc_reg; + +/// Instruction's operand referring to memory +/// This is associated with PPC_OP_MEM operand type above +typedef struct ppc_op_mem { + ppc_reg base; ///< base register + int32_t disp; ///< displacement/offset value +} ppc_op_mem; + +typedef struct ppc_op_crx { + unsigned int scale; + ppc_reg reg; + ppc_bc cond; +} ppc_op_crx; + +/// Instruction operand +typedef struct cs_ppc_op { + ppc_op_type type; ///< operand type + union { + ppc_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + ppc_op_mem mem; ///< base/disp value for MEM operand + ppc_op_crx crx; ///< operand with condition register + }; +} cs_ppc_op; + +/// Instruction structure +typedef struct cs_ppc { + /// branch code for branch instructions + ppc_bc bc; + + /// branch hint for branch instructions + ppc_bh bh; + + /// if update_cr0 = True, then this 'dot' insn updates CR0 + bool update_cr0; + + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_ppc_op operands[8]; ///< operands for this instruction. +} cs_ppc; + +/// PPC instruction +typedef enum ppc_insn { + PPC_INS_INVALID = 0, + + PPC_INS_ADD, + PPC_INS_ADDC, + PPC_INS_ADDE, + PPC_INS_ADDI, + PPC_INS_ADDIC, + PPC_INS_ADDIS, + PPC_INS_ADDME, + PPC_INS_ADDZE, + PPC_INS_AND, + PPC_INS_ANDC, + PPC_INS_ANDIS, + PPC_INS_ANDI, + PPC_INS_ATTN, + PPC_INS_B, + PPC_INS_BA, + PPC_INS_BC, + PPC_INS_BCCTR, + PPC_INS_BCCTRL, + PPC_INS_BCL, + PPC_INS_BCLR, + PPC_INS_BCLRL, + PPC_INS_BCTR, + PPC_INS_BCTRL, + PPC_INS_BCT, + PPC_INS_BDNZ, + PPC_INS_BDNZA, + PPC_INS_BDNZL, + PPC_INS_BDNZLA, + PPC_INS_BDNZLR, + PPC_INS_BDNZLRL, + PPC_INS_BDZ, + PPC_INS_BDZA, + PPC_INS_BDZL, + PPC_INS_BDZLA, + PPC_INS_BDZLR, + PPC_INS_BDZLRL, + PPC_INS_BL, + PPC_INS_BLA, + PPC_INS_BLR, + PPC_INS_BLRL, + PPC_INS_BRINC, + PPC_INS_CMPB, + PPC_INS_CMPD, + PPC_INS_CMPDI, + PPC_INS_CMPLD, + PPC_INS_CMPLDI, + PPC_INS_CMPLW, + PPC_INS_CMPLWI, + PPC_INS_CMPW, + PPC_INS_CMPWI, + PPC_INS_CNTLZD, + PPC_INS_CNTLZW, + PPC_INS_CREQV, + PPC_INS_CRXOR, + PPC_INS_CRAND, + PPC_INS_CRANDC, + PPC_INS_CRNAND, + PPC_INS_CRNOR, + PPC_INS_CROR, + PPC_INS_CRORC, + PPC_INS_DCBA, + PPC_INS_DCBF, + PPC_INS_DCBI, + PPC_INS_DCBST, + PPC_INS_DCBT, + PPC_INS_DCBTST, + PPC_INS_DCBZ, + PPC_INS_DCBZL, + PPC_INS_DCCCI, + PPC_INS_DIVD, + PPC_INS_DIVDU, + PPC_INS_DIVW, + PPC_INS_DIVWU, + PPC_INS_DSS, + PPC_INS_DSSALL, + PPC_INS_DST, + PPC_INS_DSTST, + PPC_INS_DSTSTT, + PPC_INS_DSTT, + PPC_INS_EQV, + PPC_INS_EVABS, + PPC_INS_EVADDIW, + PPC_INS_EVADDSMIAAW, + PPC_INS_EVADDSSIAAW, + PPC_INS_EVADDUMIAAW, + PPC_INS_EVADDUSIAAW, + PPC_INS_EVADDW, + PPC_INS_EVAND, + PPC_INS_EVANDC, + PPC_INS_EVCMPEQ, + PPC_INS_EVCMPGTS, + PPC_INS_EVCMPGTU, + PPC_INS_EVCMPLTS, + PPC_INS_EVCMPLTU, + PPC_INS_EVCNTLSW, + PPC_INS_EVCNTLZW, + PPC_INS_EVDIVWS, + PPC_INS_EVDIVWU, + PPC_INS_EVEQV, + PPC_INS_EVEXTSB, + PPC_INS_EVEXTSH, + PPC_INS_EVLDD, + PPC_INS_EVLDDX, + PPC_INS_EVLDH, + PPC_INS_EVLDHX, + PPC_INS_EVLDW, + PPC_INS_EVLDWX, + PPC_INS_EVLHHESPLAT, + PPC_INS_EVLHHESPLATX, + PPC_INS_EVLHHOSSPLAT, + PPC_INS_EVLHHOSSPLATX, + PPC_INS_EVLHHOUSPLAT, + PPC_INS_EVLHHOUSPLATX, + PPC_INS_EVLWHE, + PPC_INS_EVLWHEX, + PPC_INS_EVLWHOS, + PPC_INS_EVLWHOSX, + PPC_INS_EVLWHOU, + PPC_INS_EVLWHOUX, + PPC_INS_EVLWHSPLAT, + PPC_INS_EVLWHSPLATX, + PPC_INS_EVLWWSPLAT, + PPC_INS_EVLWWSPLATX, + PPC_INS_EVMERGEHI, + PPC_INS_EVMERGEHILO, + PPC_INS_EVMERGELO, + PPC_INS_EVMERGELOHI, + PPC_INS_EVMHEGSMFAA, + PPC_INS_EVMHEGSMFAN, + PPC_INS_EVMHEGSMIAA, + PPC_INS_EVMHEGSMIAN, + PPC_INS_EVMHEGUMIAA, + PPC_INS_EVMHEGUMIAN, + PPC_INS_EVMHESMF, + PPC_INS_EVMHESMFA, + PPC_INS_EVMHESMFAAW, + PPC_INS_EVMHESMFANW, + PPC_INS_EVMHESMI, + PPC_INS_EVMHESMIA, + PPC_INS_EVMHESMIAAW, + PPC_INS_EVMHESMIANW, + PPC_INS_EVMHESSF, + PPC_INS_EVMHESSFA, + PPC_INS_EVMHESSFAAW, + PPC_INS_EVMHESSFANW, + PPC_INS_EVMHESSIAAW, + PPC_INS_EVMHESSIANW, + PPC_INS_EVMHEUMI, + PPC_INS_EVMHEUMIA, + PPC_INS_EVMHEUMIAAW, + PPC_INS_EVMHEUMIANW, + PPC_INS_EVMHEUSIAAW, + PPC_INS_EVMHEUSIANW, + PPC_INS_EVMHOGSMFAA, + PPC_INS_EVMHOGSMFAN, + PPC_INS_EVMHOGSMIAA, + PPC_INS_EVMHOGSMIAN, + PPC_INS_EVMHOGUMIAA, + PPC_INS_EVMHOGUMIAN, + PPC_INS_EVMHOSMF, + PPC_INS_EVMHOSMFA, + PPC_INS_EVMHOSMFAAW, + PPC_INS_EVMHOSMFANW, + PPC_INS_EVMHOSMI, + PPC_INS_EVMHOSMIA, + PPC_INS_EVMHOSMIAAW, + PPC_INS_EVMHOSMIANW, + PPC_INS_EVMHOSSF, + PPC_INS_EVMHOSSFA, + PPC_INS_EVMHOSSFAAW, + PPC_INS_EVMHOSSFANW, + PPC_INS_EVMHOSSIAAW, + PPC_INS_EVMHOSSIANW, + PPC_INS_EVMHOUMI, + PPC_INS_EVMHOUMIA, + PPC_INS_EVMHOUMIAAW, + PPC_INS_EVMHOUMIANW, + PPC_INS_EVMHOUSIAAW, + PPC_INS_EVMHOUSIANW, + PPC_INS_EVMRA, + PPC_INS_EVMWHSMF, + PPC_INS_EVMWHSMFA, + PPC_INS_EVMWHSMI, + PPC_INS_EVMWHSMIA, + PPC_INS_EVMWHSSF, + PPC_INS_EVMWHSSFA, + PPC_INS_EVMWHUMI, + PPC_INS_EVMWHUMIA, + PPC_INS_EVMWLSMIAAW, + PPC_INS_EVMWLSMIANW, + PPC_INS_EVMWLSSIAAW, + PPC_INS_EVMWLSSIANW, + PPC_INS_EVMWLUMI, + PPC_INS_EVMWLUMIA, + PPC_INS_EVMWLUMIAAW, + PPC_INS_EVMWLUMIANW, + PPC_INS_EVMWLUSIAAW, + PPC_INS_EVMWLUSIANW, + PPC_INS_EVMWSMF, + PPC_INS_EVMWSMFA, + PPC_INS_EVMWSMFAA, + PPC_INS_EVMWSMFAN, + PPC_INS_EVMWSMI, + PPC_INS_EVMWSMIA, + PPC_INS_EVMWSMIAA, + PPC_INS_EVMWSMIAN, + PPC_INS_EVMWSSF, + PPC_INS_EVMWSSFA, + PPC_INS_EVMWSSFAA, + PPC_INS_EVMWSSFAN, + PPC_INS_EVMWUMI, + PPC_INS_EVMWUMIA, + PPC_INS_EVMWUMIAA, + PPC_INS_EVMWUMIAN, + PPC_INS_EVNAND, + PPC_INS_EVNEG, + PPC_INS_EVNOR, + PPC_INS_EVOR, + PPC_INS_EVORC, + PPC_INS_EVRLW, + PPC_INS_EVRLWI, + PPC_INS_EVRNDW, + PPC_INS_EVSLW, + PPC_INS_EVSLWI, + PPC_INS_EVSPLATFI, + PPC_INS_EVSPLATI, + PPC_INS_EVSRWIS, + PPC_INS_EVSRWIU, + PPC_INS_EVSRWS, + PPC_INS_EVSRWU, + PPC_INS_EVSTDD, + PPC_INS_EVSTDDX, + PPC_INS_EVSTDH, + PPC_INS_EVSTDHX, + PPC_INS_EVSTDW, + PPC_INS_EVSTDWX, + PPC_INS_EVSTWHE, + PPC_INS_EVSTWHEX, + PPC_INS_EVSTWHO, + PPC_INS_EVSTWHOX, + PPC_INS_EVSTWWE, + PPC_INS_EVSTWWEX, + PPC_INS_EVSTWWO, + PPC_INS_EVSTWWOX, + PPC_INS_EVSUBFSMIAAW, + PPC_INS_EVSUBFSSIAAW, + PPC_INS_EVSUBFUMIAAW, + PPC_INS_EVSUBFUSIAAW, + PPC_INS_EVSUBFW, + PPC_INS_EVSUBIFW, + PPC_INS_EVXOR, + PPC_INS_EXTSB, + PPC_INS_EXTSH, + PPC_INS_EXTSW, + PPC_INS_EIEIO, + PPC_INS_FABS, + PPC_INS_FADD, + PPC_INS_FADDS, + PPC_INS_FCFID, + PPC_INS_FCFIDS, + PPC_INS_FCFIDU, + PPC_INS_FCFIDUS, + PPC_INS_FCMPU, + PPC_INS_FCPSGN, + PPC_INS_FCTID, + PPC_INS_FCTIDUZ, + PPC_INS_FCTIDZ, + PPC_INS_FCTIW, + PPC_INS_FCTIWUZ, + PPC_INS_FCTIWZ, + PPC_INS_FDIV, + PPC_INS_FDIVS, + PPC_INS_FMADD, + PPC_INS_FMADDS, + PPC_INS_FMR, + PPC_INS_FMSUB, + PPC_INS_FMSUBS, + PPC_INS_FMUL, + PPC_INS_FMULS, + PPC_INS_FNABS, + PPC_INS_FNEG, + PPC_INS_FNMADD, + PPC_INS_FNMADDS, + PPC_INS_FNMSUB, + PPC_INS_FNMSUBS, + PPC_INS_FRE, + PPC_INS_FRES, + PPC_INS_FRIM, + PPC_INS_FRIN, + PPC_INS_FRIP, + PPC_INS_FRIZ, + PPC_INS_FRSP, + PPC_INS_FRSQRTE, + PPC_INS_FRSQRTES, + PPC_INS_FSEL, + PPC_INS_FSQRT, + PPC_INS_FSQRTS, + PPC_INS_FSUB, + PPC_INS_FSUBS, + PPC_INS_ICBI, + PPC_INS_ICBT, + PPC_INS_ICCCI, + PPC_INS_ISEL, + PPC_INS_ISYNC, + PPC_INS_LA, + PPC_INS_LBZ, + PPC_INS_LBZCIX, + PPC_INS_LBZU, + PPC_INS_LBZUX, + PPC_INS_LBZX, + PPC_INS_LD, + PPC_INS_LDARX, + PPC_INS_LDBRX, + PPC_INS_LDCIX, + PPC_INS_LDU, + PPC_INS_LDUX, + PPC_INS_LDX, + PPC_INS_LFD, + PPC_INS_LFDU, + PPC_INS_LFDUX, + PPC_INS_LFDX, + PPC_INS_LFIWAX, + PPC_INS_LFIWZX, + PPC_INS_LFS, + PPC_INS_LFSU, + PPC_INS_LFSUX, + PPC_INS_LFSX, + PPC_INS_LHA, + PPC_INS_LHAU, + PPC_INS_LHAUX, + PPC_INS_LHAX, + PPC_INS_LHBRX, + PPC_INS_LHZ, + PPC_INS_LHZCIX, + PPC_INS_LHZU, + PPC_INS_LHZUX, + PPC_INS_LHZX, + PPC_INS_LI, + PPC_INS_LIS, + PPC_INS_LMW, + PPC_INS_LSWI, + PPC_INS_LVEBX, + PPC_INS_LVEHX, + PPC_INS_LVEWX, + PPC_INS_LVSL, + PPC_INS_LVSR, + PPC_INS_LVX, + PPC_INS_LVXL, + PPC_INS_LWA, + PPC_INS_LWARX, + PPC_INS_LWAUX, + PPC_INS_LWAX, + PPC_INS_LWBRX, + PPC_INS_LWZ, + PPC_INS_LWZCIX, + PPC_INS_LWZU, + PPC_INS_LWZUX, + PPC_INS_LWZX, + PPC_INS_LXSDX, + PPC_INS_LXVD2X, + PPC_INS_LXVDSX, + PPC_INS_LXVW4X, + PPC_INS_MBAR, + PPC_INS_MCRF, + PPC_INS_MCRFS, + PPC_INS_MFCR, + PPC_INS_MFCTR, + PPC_INS_MFDCR, + PPC_INS_MFFS, + PPC_INS_MFLR, + PPC_INS_MFMSR, + PPC_INS_MFOCRF, + PPC_INS_MFSPR, + PPC_INS_MFSR, + PPC_INS_MFSRIN, + PPC_INS_MFTB, + PPC_INS_MFVSCR, + PPC_INS_MSYNC, + PPC_INS_MTCRF, + PPC_INS_MTCTR, + PPC_INS_MTDCR, + PPC_INS_MTFSB0, + PPC_INS_MTFSB1, + PPC_INS_MTFSF, + PPC_INS_MTFSFI, + PPC_INS_MTLR, + PPC_INS_MTMSR, + PPC_INS_MTMSRD, + PPC_INS_MTOCRF, + PPC_INS_MTSPR, + PPC_INS_MTSR, + PPC_INS_MTSRIN, + PPC_INS_MTVSCR, + PPC_INS_MULHD, + PPC_INS_MULHDU, + PPC_INS_MULHW, + PPC_INS_MULHWU, + PPC_INS_MULLD, + PPC_INS_MULLI, + PPC_INS_MULLW, + PPC_INS_NAND, + PPC_INS_NEG, + PPC_INS_NOP, + PPC_INS_ORI, + PPC_INS_NOR, + PPC_INS_OR, + PPC_INS_ORC, + PPC_INS_ORIS, + PPC_INS_POPCNTD, + PPC_INS_POPCNTW, + PPC_INS_QVALIGNI, + PPC_INS_QVESPLATI, + PPC_INS_QVFABS, + PPC_INS_QVFADD, + PPC_INS_QVFADDS, + PPC_INS_QVFCFID, + PPC_INS_QVFCFIDS, + PPC_INS_QVFCFIDU, + PPC_INS_QVFCFIDUS, + PPC_INS_QVFCMPEQ, + PPC_INS_QVFCMPGT, + PPC_INS_QVFCMPLT, + PPC_INS_QVFCPSGN, + PPC_INS_QVFCTID, + PPC_INS_QVFCTIDU, + PPC_INS_QVFCTIDUZ, + PPC_INS_QVFCTIDZ, + PPC_INS_QVFCTIW, + PPC_INS_QVFCTIWU, + PPC_INS_QVFCTIWUZ, + PPC_INS_QVFCTIWZ, + PPC_INS_QVFLOGICAL, + PPC_INS_QVFMADD, + PPC_INS_QVFMADDS, + PPC_INS_QVFMR, + PPC_INS_QVFMSUB, + PPC_INS_QVFMSUBS, + PPC_INS_QVFMUL, + PPC_INS_QVFMULS, + PPC_INS_QVFNABS, + PPC_INS_QVFNEG, + PPC_INS_QVFNMADD, + PPC_INS_QVFNMADDS, + PPC_INS_QVFNMSUB, + PPC_INS_QVFNMSUBS, + PPC_INS_QVFPERM, + PPC_INS_QVFRE, + PPC_INS_QVFRES, + PPC_INS_QVFRIM, + PPC_INS_QVFRIN, + PPC_INS_QVFRIP, + PPC_INS_QVFRIZ, + PPC_INS_QVFRSP, + PPC_INS_QVFRSQRTE, + PPC_INS_QVFRSQRTES, + PPC_INS_QVFSEL, + PPC_INS_QVFSUB, + PPC_INS_QVFSUBS, + PPC_INS_QVFTSTNAN, + PPC_INS_QVFXMADD, + PPC_INS_QVFXMADDS, + PPC_INS_QVFXMUL, + PPC_INS_QVFXMULS, + PPC_INS_QVFXXCPNMADD, + PPC_INS_QVFXXCPNMADDS, + PPC_INS_QVFXXMADD, + PPC_INS_QVFXXMADDS, + PPC_INS_QVFXXNPMADD, + PPC_INS_QVFXXNPMADDS, + PPC_INS_QVGPCI, + PPC_INS_QVLFCDUX, + PPC_INS_QVLFCDUXA, + PPC_INS_QVLFCDX, + PPC_INS_QVLFCDXA, + PPC_INS_QVLFCSUX, + PPC_INS_QVLFCSUXA, + PPC_INS_QVLFCSX, + PPC_INS_QVLFCSXA, + PPC_INS_QVLFDUX, + PPC_INS_QVLFDUXA, + PPC_INS_QVLFDX, + PPC_INS_QVLFDXA, + PPC_INS_QVLFIWAX, + PPC_INS_QVLFIWAXA, + PPC_INS_QVLFIWZX, + PPC_INS_QVLFIWZXA, + PPC_INS_QVLFSUX, + PPC_INS_QVLFSUXA, + PPC_INS_QVLFSX, + PPC_INS_QVLFSXA, + PPC_INS_QVLPCLDX, + PPC_INS_QVLPCLSX, + PPC_INS_QVLPCRDX, + PPC_INS_QVLPCRSX, + PPC_INS_QVSTFCDUX, + PPC_INS_QVSTFCDUXA, + PPC_INS_QVSTFCDUXI, + PPC_INS_QVSTFCDUXIA, + PPC_INS_QVSTFCDX, + PPC_INS_QVSTFCDXA, + PPC_INS_QVSTFCDXI, + PPC_INS_QVSTFCDXIA, + PPC_INS_QVSTFCSUX, + PPC_INS_QVSTFCSUXA, + PPC_INS_QVSTFCSUXI, + PPC_INS_QVSTFCSUXIA, + PPC_INS_QVSTFCSX, + PPC_INS_QVSTFCSXA, + PPC_INS_QVSTFCSXI, + PPC_INS_QVSTFCSXIA, + PPC_INS_QVSTFDUX, + PPC_INS_QVSTFDUXA, + PPC_INS_QVSTFDUXI, + PPC_INS_QVSTFDUXIA, + PPC_INS_QVSTFDX, + PPC_INS_QVSTFDXA, + PPC_INS_QVSTFDXI, + PPC_INS_QVSTFDXIA, + PPC_INS_QVSTFIWX, + PPC_INS_QVSTFIWXA, + PPC_INS_QVSTFSUX, + PPC_INS_QVSTFSUXA, + PPC_INS_QVSTFSUXI, + PPC_INS_QVSTFSUXIA, + PPC_INS_QVSTFSX, + PPC_INS_QVSTFSXA, + PPC_INS_QVSTFSXI, + PPC_INS_QVSTFSXIA, + PPC_INS_RFCI, + PPC_INS_RFDI, + PPC_INS_RFI, + PPC_INS_RFID, + PPC_INS_RFMCI, + PPC_INS_RLDCL, + PPC_INS_RLDCR, + PPC_INS_RLDIC, + PPC_INS_RLDICL, + PPC_INS_RLDICR, + PPC_INS_RLDIMI, + PPC_INS_RLWIMI, + PPC_INS_RLWINM, + PPC_INS_RLWNM, + PPC_INS_SC, + PPC_INS_SLBIA, + PPC_INS_SLBIE, + PPC_INS_SLBMFEE, + PPC_INS_SLBMTE, + PPC_INS_SLD, + PPC_INS_SLW, + PPC_INS_SRAD, + PPC_INS_SRADI, + PPC_INS_SRAW, + PPC_INS_SRAWI, + PPC_INS_SRD, + PPC_INS_SRW, + PPC_INS_STB, + PPC_INS_STBCIX, + PPC_INS_STBU, + PPC_INS_STBUX, + PPC_INS_STBX, + PPC_INS_STD, + PPC_INS_STDBRX, + PPC_INS_STDCIX, + PPC_INS_STDCX, + PPC_INS_STDU, + PPC_INS_STDUX, + PPC_INS_STDX, + PPC_INS_STFD, + PPC_INS_STFDU, + PPC_INS_STFDUX, + PPC_INS_STFDX, + PPC_INS_STFIWX, + PPC_INS_STFS, + PPC_INS_STFSU, + PPC_INS_STFSUX, + PPC_INS_STFSX, + PPC_INS_STH, + PPC_INS_STHBRX, + PPC_INS_STHCIX, + PPC_INS_STHU, + PPC_INS_STHUX, + PPC_INS_STHX, + PPC_INS_STMW, + PPC_INS_STSWI, + PPC_INS_STVEBX, + PPC_INS_STVEHX, + PPC_INS_STVEWX, + PPC_INS_STVX, + PPC_INS_STVXL, + PPC_INS_STW, + PPC_INS_STWBRX, + PPC_INS_STWCIX, + PPC_INS_STWCX, + PPC_INS_STWU, + PPC_INS_STWUX, + PPC_INS_STWX, + PPC_INS_STXSDX, + PPC_INS_STXVD2X, + PPC_INS_STXVW4X, + PPC_INS_SUBF, + PPC_INS_SUBFC, + PPC_INS_SUBFE, + PPC_INS_SUBFIC, + PPC_INS_SUBFME, + PPC_INS_SUBFZE, + PPC_INS_SYNC, + PPC_INS_TD, + PPC_INS_TDI, + PPC_INS_TLBIA, + PPC_INS_TLBIE, + PPC_INS_TLBIEL, + PPC_INS_TLBIVAX, + PPC_INS_TLBLD, + PPC_INS_TLBLI, + PPC_INS_TLBRE, + PPC_INS_TLBSX, + PPC_INS_TLBSYNC, + PPC_INS_TLBWE, + PPC_INS_TRAP, + PPC_INS_TW, + PPC_INS_TWI, + PPC_INS_VADDCUW, + PPC_INS_VADDFP, + PPC_INS_VADDSBS, + PPC_INS_VADDSHS, + PPC_INS_VADDSWS, + PPC_INS_VADDUBM, + PPC_INS_VADDUBS, + PPC_INS_VADDUDM, + PPC_INS_VADDUHM, + PPC_INS_VADDUHS, + PPC_INS_VADDUWM, + PPC_INS_VADDUWS, + PPC_INS_VAND, + PPC_INS_VANDC, + PPC_INS_VAVGSB, + PPC_INS_VAVGSH, + PPC_INS_VAVGSW, + PPC_INS_VAVGUB, + PPC_INS_VAVGUH, + PPC_INS_VAVGUW, + PPC_INS_VCFSX, + PPC_INS_VCFUX, + PPC_INS_VCLZB, + PPC_INS_VCLZD, + PPC_INS_VCLZH, + PPC_INS_VCLZW, + PPC_INS_VCMPBFP, + PPC_INS_VCMPEQFP, + PPC_INS_VCMPEQUB, + PPC_INS_VCMPEQUD, + PPC_INS_VCMPEQUH, + PPC_INS_VCMPEQUW, + PPC_INS_VCMPGEFP, + PPC_INS_VCMPGTFP, + PPC_INS_VCMPGTSB, + PPC_INS_VCMPGTSD, + PPC_INS_VCMPGTSH, + PPC_INS_VCMPGTSW, + PPC_INS_VCMPGTUB, + PPC_INS_VCMPGTUD, + PPC_INS_VCMPGTUH, + PPC_INS_VCMPGTUW, + PPC_INS_VCTSXS, + PPC_INS_VCTUXS, + PPC_INS_VEQV, + PPC_INS_VEXPTEFP, + PPC_INS_VLOGEFP, + PPC_INS_VMADDFP, + PPC_INS_VMAXFP, + PPC_INS_VMAXSB, + PPC_INS_VMAXSD, + PPC_INS_VMAXSH, + PPC_INS_VMAXSW, + PPC_INS_VMAXUB, + PPC_INS_VMAXUD, + PPC_INS_VMAXUH, + PPC_INS_VMAXUW, + PPC_INS_VMHADDSHS, + PPC_INS_VMHRADDSHS, + PPC_INS_VMINUD, + PPC_INS_VMINFP, + PPC_INS_VMINSB, + PPC_INS_VMINSD, + PPC_INS_VMINSH, + PPC_INS_VMINSW, + PPC_INS_VMINUB, + PPC_INS_VMINUH, + PPC_INS_VMINUW, + PPC_INS_VMLADDUHM, + PPC_INS_VMRGHB, + PPC_INS_VMRGHH, + PPC_INS_VMRGHW, + PPC_INS_VMRGLB, + PPC_INS_VMRGLH, + PPC_INS_VMRGLW, + PPC_INS_VMSUMMBM, + PPC_INS_VMSUMSHM, + PPC_INS_VMSUMSHS, + PPC_INS_VMSUMUBM, + PPC_INS_VMSUMUHM, + PPC_INS_VMSUMUHS, + PPC_INS_VMULESB, + PPC_INS_VMULESH, + PPC_INS_VMULESW, + PPC_INS_VMULEUB, + PPC_INS_VMULEUH, + PPC_INS_VMULEUW, + PPC_INS_VMULOSB, + PPC_INS_VMULOSH, + PPC_INS_VMULOSW, + PPC_INS_VMULOUB, + PPC_INS_VMULOUH, + PPC_INS_VMULOUW, + PPC_INS_VMULUWM, + PPC_INS_VNAND, + PPC_INS_VNMSUBFP, + PPC_INS_VNOR, + PPC_INS_VOR, + PPC_INS_VORC, + PPC_INS_VPERM, + PPC_INS_VPKPX, + PPC_INS_VPKSHSS, + PPC_INS_VPKSHUS, + PPC_INS_VPKSWSS, + PPC_INS_VPKSWUS, + PPC_INS_VPKUHUM, + PPC_INS_VPKUHUS, + PPC_INS_VPKUWUM, + PPC_INS_VPKUWUS, + PPC_INS_VPOPCNTB, + PPC_INS_VPOPCNTD, + PPC_INS_VPOPCNTH, + PPC_INS_VPOPCNTW, + PPC_INS_VREFP, + PPC_INS_VRFIM, + PPC_INS_VRFIN, + PPC_INS_VRFIP, + PPC_INS_VRFIZ, + PPC_INS_VRLB, + PPC_INS_VRLD, + PPC_INS_VRLH, + PPC_INS_VRLW, + PPC_INS_VRSQRTEFP, + PPC_INS_VSEL, + PPC_INS_VSL, + PPC_INS_VSLB, + PPC_INS_VSLD, + PPC_INS_VSLDOI, + PPC_INS_VSLH, + PPC_INS_VSLO, + PPC_INS_VSLW, + PPC_INS_VSPLTB, + PPC_INS_VSPLTH, + PPC_INS_VSPLTISB, + PPC_INS_VSPLTISH, + PPC_INS_VSPLTISW, + PPC_INS_VSPLTW, + PPC_INS_VSR, + PPC_INS_VSRAB, + PPC_INS_VSRAD, + PPC_INS_VSRAH, + PPC_INS_VSRAW, + PPC_INS_VSRB, + PPC_INS_VSRD, + PPC_INS_VSRH, + PPC_INS_VSRO, + PPC_INS_VSRW, + PPC_INS_VSUBCUW, + PPC_INS_VSUBFP, + PPC_INS_VSUBSBS, + PPC_INS_VSUBSHS, + PPC_INS_VSUBSWS, + PPC_INS_VSUBUBM, + PPC_INS_VSUBUBS, + PPC_INS_VSUBUDM, + PPC_INS_VSUBUHM, + PPC_INS_VSUBUHS, + PPC_INS_VSUBUWM, + PPC_INS_VSUBUWS, + PPC_INS_VSUM2SWS, + PPC_INS_VSUM4SBS, + PPC_INS_VSUM4SHS, + PPC_INS_VSUM4UBS, + PPC_INS_VSUMSWS, + PPC_INS_VUPKHPX, + PPC_INS_VUPKHSB, + PPC_INS_VUPKHSH, + PPC_INS_VUPKLPX, + PPC_INS_VUPKLSB, + PPC_INS_VUPKLSH, + PPC_INS_VXOR, + PPC_INS_WAIT, + PPC_INS_WRTEE, + PPC_INS_WRTEEI, + PPC_INS_XOR, + PPC_INS_XORI, + PPC_INS_XORIS, + PPC_INS_XSABSDP, + PPC_INS_XSADDDP, + PPC_INS_XSCMPODP, + PPC_INS_XSCMPUDP, + PPC_INS_XSCPSGNDP, + PPC_INS_XSCVDPSP, + PPC_INS_XSCVDPSXDS, + PPC_INS_XSCVDPSXWS, + PPC_INS_XSCVDPUXDS, + PPC_INS_XSCVDPUXWS, + PPC_INS_XSCVSPDP, + PPC_INS_XSCVSXDDP, + PPC_INS_XSCVUXDDP, + PPC_INS_XSDIVDP, + PPC_INS_XSMADDADP, + PPC_INS_XSMADDMDP, + PPC_INS_XSMAXDP, + PPC_INS_XSMINDP, + PPC_INS_XSMSUBADP, + PPC_INS_XSMSUBMDP, + PPC_INS_XSMULDP, + PPC_INS_XSNABSDP, + PPC_INS_XSNEGDP, + PPC_INS_XSNMADDADP, + PPC_INS_XSNMADDMDP, + PPC_INS_XSNMSUBADP, + PPC_INS_XSNMSUBMDP, + PPC_INS_XSRDPI, + PPC_INS_XSRDPIC, + PPC_INS_XSRDPIM, + PPC_INS_XSRDPIP, + PPC_INS_XSRDPIZ, + PPC_INS_XSREDP, + PPC_INS_XSRSQRTEDP, + PPC_INS_XSSQRTDP, + PPC_INS_XSSUBDP, + PPC_INS_XSTDIVDP, + PPC_INS_XSTSQRTDP, + PPC_INS_XVABSDP, + PPC_INS_XVABSSP, + PPC_INS_XVADDDP, + PPC_INS_XVADDSP, + PPC_INS_XVCMPEQDP, + PPC_INS_XVCMPEQSP, + PPC_INS_XVCMPGEDP, + PPC_INS_XVCMPGESP, + PPC_INS_XVCMPGTDP, + PPC_INS_XVCMPGTSP, + PPC_INS_XVCPSGNDP, + PPC_INS_XVCPSGNSP, + PPC_INS_XVCVDPSP, + PPC_INS_XVCVDPSXDS, + PPC_INS_XVCVDPSXWS, + PPC_INS_XVCVDPUXDS, + PPC_INS_XVCVDPUXWS, + PPC_INS_XVCVSPDP, + PPC_INS_XVCVSPSXDS, + PPC_INS_XVCVSPSXWS, + PPC_INS_XVCVSPUXDS, + PPC_INS_XVCVSPUXWS, + PPC_INS_XVCVSXDDP, + PPC_INS_XVCVSXDSP, + PPC_INS_XVCVSXWDP, + PPC_INS_XVCVSXWSP, + PPC_INS_XVCVUXDDP, + PPC_INS_XVCVUXDSP, + PPC_INS_XVCVUXWDP, + PPC_INS_XVCVUXWSP, + PPC_INS_XVDIVDP, + PPC_INS_XVDIVSP, + PPC_INS_XVMADDADP, + PPC_INS_XVMADDASP, + PPC_INS_XVMADDMDP, + PPC_INS_XVMADDMSP, + PPC_INS_XVMAXDP, + PPC_INS_XVMAXSP, + PPC_INS_XVMINDP, + PPC_INS_XVMINSP, + PPC_INS_XVMSUBADP, + PPC_INS_XVMSUBASP, + PPC_INS_XVMSUBMDP, + PPC_INS_XVMSUBMSP, + PPC_INS_XVMULDP, + PPC_INS_XVMULSP, + PPC_INS_XVNABSDP, + PPC_INS_XVNABSSP, + PPC_INS_XVNEGDP, + PPC_INS_XVNEGSP, + PPC_INS_XVNMADDADP, + PPC_INS_XVNMADDASP, + PPC_INS_XVNMADDMDP, + PPC_INS_XVNMADDMSP, + PPC_INS_XVNMSUBADP, + PPC_INS_XVNMSUBASP, + PPC_INS_XVNMSUBMDP, + PPC_INS_XVNMSUBMSP, + PPC_INS_XVRDPI, + PPC_INS_XVRDPIC, + PPC_INS_XVRDPIM, + PPC_INS_XVRDPIP, + PPC_INS_XVRDPIZ, + PPC_INS_XVREDP, + PPC_INS_XVRESP, + PPC_INS_XVRSPI, + PPC_INS_XVRSPIC, + PPC_INS_XVRSPIM, + PPC_INS_XVRSPIP, + PPC_INS_XVRSPIZ, + PPC_INS_XVRSQRTEDP, + PPC_INS_XVRSQRTESP, + PPC_INS_XVSQRTDP, + PPC_INS_XVSQRTSP, + PPC_INS_XVSUBDP, + PPC_INS_XVSUBSP, + PPC_INS_XVTDIVDP, + PPC_INS_XVTDIVSP, + PPC_INS_XVTSQRTDP, + PPC_INS_XVTSQRTSP, + PPC_INS_XXLAND, + PPC_INS_XXLANDC, + PPC_INS_XXLEQV, + PPC_INS_XXLNAND, + PPC_INS_XXLNOR, + PPC_INS_XXLOR, + PPC_INS_XXLORC, + PPC_INS_XXLXOR, + PPC_INS_XXMRGHW, + PPC_INS_XXMRGLW, + PPC_INS_XXPERMDI, + PPC_INS_XXSEL, + PPC_INS_XXSLDWI, + PPC_INS_XXSPLTW, + PPC_INS_BCA, + PPC_INS_BCLA, + + // extra & alias instructions + PPC_INS_SLWI, + PPC_INS_SRWI, + PPC_INS_SLDI, + + PPC_INS_BTA, + PPC_INS_CRSET, + PPC_INS_CRNOT, + PPC_INS_CRMOVE, + PPC_INS_CRCLR, + PPC_INS_MFBR0, + PPC_INS_MFBR1, + PPC_INS_MFBR2, + PPC_INS_MFBR3, + PPC_INS_MFBR4, + PPC_INS_MFBR5, + PPC_INS_MFBR6, + PPC_INS_MFBR7, + PPC_INS_MFXER, + PPC_INS_MFRTCU, + PPC_INS_MFRTCL, + PPC_INS_MFDSCR, + PPC_INS_MFDSISR, + PPC_INS_MFDAR, + PPC_INS_MFSRR2, + PPC_INS_MFSRR3, + PPC_INS_MFCFAR, + PPC_INS_MFAMR, + PPC_INS_MFPID, + PPC_INS_MFTBLO, + PPC_INS_MFTBHI, + PPC_INS_MFDBATU, + PPC_INS_MFDBATL, + PPC_INS_MFIBATU, + PPC_INS_MFIBATL, + PPC_INS_MFDCCR, + PPC_INS_MFICCR, + PPC_INS_MFDEAR, + PPC_INS_MFESR, + PPC_INS_MFSPEFSCR, + PPC_INS_MFTCR, + PPC_INS_MFASR, + PPC_INS_MFPVR, + PPC_INS_MFTBU, + PPC_INS_MTCR, + PPC_INS_MTBR0, + PPC_INS_MTBR1, + PPC_INS_MTBR2, + PPC_INS_MTBR3, + PPC_INS_MTBR4, + PPC_INS_MTBR5, + PPC_INS_MTBR6, + PPC_INS_MTBR7, + PPC_INS_MTXER, + PPC_INS_MTDSCR, + PPC_INS_MTDSISR, + PPC_INS_MTDAR, + PPC_INS_MTSRR2, + PPC_INS_MTSRR3, + PPC_INS_MTCFAR, + PPC_INS_MTAMR, + PPC_INS_MTPID, + PPC_INS_MTTBL, + PPC_INS_MTTBU, + PPC_INS_MTTBLO, + PPC_INS_MTTBHI, + PPC_INS_MTDBATU, + PPC_INS_MTDBATL, + PPC_INS_MTIBATU, + PPC_INS_MTIBATL, + PPC_INS_MTDCCR, + PPC_INS_MTICCR, + PPC_INS_MTDEAR, + PPC_INS_MTESR, + PPC_INS_MTSPEFSCR, + PPC_INS_MTTCR, + PPC_INS_NOT, + PPC_INS_MR, + PPC_INS_ROTLD, + PPC_INS_ROTLDI, + PPC_INS_CLRLDI, + PPC_INS_ROTLWI, + PPC_INS_CLRLWI, + PPC_INS_ROTLW, + PPC_INS_SUB, + PPC_INS_SUBC, + PPC_INS_LWSYNC, + PPC_INS_PTESYNC, + PPC_INS_TDLT, + PPC_INS_TDEQ, + PPC_INS_TDGT, + PPC_INS_TDNE, + PPC_INS_TDLLT, + PPC_INS_TDLGT, + PPC_INS_TDU, + PPC_INS_TDLTI, + PPC_INS_TDEQI, + PPC_INS_TDGTI, + PPC_INS_TDNEI, + PPC_INS_TDLLTI, + PPC_INS_TDLGTI, + PPC_INS_TDUI, + PPC_INS_TLBREHI, + PPC_INS_TLBRELO, + PPC_INS_TLBWEHI, + PPC_INS_TLBWELO, + PPC_INS_TWLT, + PPC_INS_TWEQ, + PPC_INS_TWGT, + PPC_INS_TWNE, + PPC_INS_TWLLT, + PPC_INS_TWLGT, + PPC_INS_TWU, + PPC_INS_TWLTI, + PPC_INS_TWEQI, + PPC_INS_TWGTI, + PPC_INS_TWNEI, + PPC_INS_TWLLTI, + PPC_INS_TWLGTI, + PPC_INS_TWUI, + PPC_INS_WAITRSV, + PPC_INS_WAITIMPL, + PPC_INS_XNOP, + PPC_INS_XVMOVDP, + PPC_INS_XVMOVSP, + PPC_INS_XXSPLTD, + PPC_INS_XXMRGHD, + PPC_INS_XXMRGLD, + PPC_INS_XXSWAPD, + PPC_INS_BT, + PPC_INS_BF, + PPC_INS_BDNZT, + PPC_INS_BDNZF, + PPC_INS_BDZF, + PPC_INS_BDZT, + PPC_INS_BFA, + PPC_INS_BDNZTA, + PPC_INS_BDNZFA, + PPC_INS_BDZTA, + PPC_INS_BDZFA, + PPC_INS_BTCTR, + PPC_INS_BFCTR, + PPC_INS_BTCTRL, + PPC_INS_BFCTRL, + PPC_INS_BTL, + PPC_INS_BFL, + PPC_INS_BDNZTL, + PPC_INS_BDNZFL, + PPC_INS_BDZTL, + PPC_INS_BDZFL, + PPC_INS_BTLA, + PPC_INS_BFLA, + PPC_INS_BDNZTLA, + PPC_INS_BDNZFLA, + PPC_INS_BDZTLA, + PPC_INS_BDZFLA, + PPC_INS_BTLR, + PPC_INS_BFLR, + PPC_INS_BDNZTLR, + PPC_INS_BDZTLR, + PPC_INS_BDZFLR, + PPC_INS_BTLRL, + PPC_INS_BFLRL, + PPC_INS_BDNZTLRL, + PPC_INS_BDNZFLRL, + PPC_INS_BDZTLRL, + PPC_INS_BDZFLRL, + + // QPX + PPC_INS_QVFAND, + PPC_INS_QVFCLR, + PPC_INS_QVFANDC, + PPC_INS_QVFCTFB, + PPC_INS_QVFXOR, + PPC_INS_QVFOR, + PPC_INS_QVFNOR, + PPC_INS_QVFEQU, + PPC_INS_QVFNOT, + PPC_INS_QVFORC, + PPC_INS_QVFNAND, + PPC_INS_QVFSET, + + PPC_INS_ENDING, // <-- mark the end of the list of instructions +} ppc_insn; + +/// Group of PPC instructions +typedef enum ppc_insn_group { + PPC_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + PPC_GRP_JUMP, ///< = CS_GRP_JUMP + + // Architecture-specific groups + PPC_GRP_ALTIVEC = 128, + PPC_GRP_MODE32, + PPC_GRP_MODE64, + PPC_GRP_BOOKE, + PPC_GRP_NOTBOOKE, + PPC_GRP_SPE, + PPC_GRP_VSX, + PPC_GRP_E500, + PPC_GRP_PPC4XX, + PPC_GRP_PPC6XX, + PPC_GRP_ICBT, + PPC_GRP_P8ALTIVEC, + PPC_GRP_P8VECTOR, + PPC_GRP_QPX, + + PPC_GRP_ENDING, // <-- mark the end of the list of groups +} ppc_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/sparc.h b/white_patch_detect/capstone-master/include/capstone/sparc.h new file mode 100644 index 0000000..e33d173 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/sparc.h @@ -0,0 +1,520 @@ +#ifndef CAPSTONE_SPARC_H +#define CAPSTONE_SPARC_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2014-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +// GCC SPARC toolchain has a default macro called "sparc" which breaks +// compilation +#undef sparc + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// Enums corresponding to Sparc condition codes, both icc's and fcc's. +typedef enum sparc_cc { + SPARC_CC_INVALID = 0, ///< invalid CC (default) + // Integer condition codes + SPARC_CC_ICC_A = 8+256, ///< Always + SPARC_CC_ICC_N = 0+256, ///< Never + SPARC_CC_ICC_NE = 9+256, ///< Not Equal + SPARC_CC_ICC_E = 1+256, ///< Equal + SPARC_CC_ICC_G = 10+256, ///< Greater + SPARC_CC_ICC_LE = 2+256, ///< Less or Equal + SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal + SPARC_CC_ICC_L = 3+256, ///< Less + SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned + SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned + SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned + SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned + SPARC_CC_ICC_POS = 14+256, ///< Positive + SPARC_CC_ICC_NEG = 6+256, ///< Negative + SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear + SPARC_CC_ICC_VS = 7+256, ///< Overflow Set + + // Floating condition codes + SPARC_CC_FCC_A = 8+16+256, ///< Always + SPARC_CC_FCC_N = 0+16+256, ///< Never + SPARC_CC_FCC_U = 7+16+256, ///< Unordered + SPARC_CC_FCC_G = 6+16+256, ///< Greater + SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater + SPARC_CC_FCC_L = 4+16+256, ///< Less + SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less + SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater + SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal + SPARC_CC_FCC_E = 9+16+256, ///< Equal + SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal + SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal + SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal + SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal + SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal + SPARC_CC_FCC_O = 15+16+256, ///< Ordered +} sparc_cc; + +/// Branch hint +typedef enum sparc_hint { + SPARC_HINT_INVALID = 0, ///< no hint + SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction + SPARC_HINT_PT = 1 << 1, ///< branch taken + SPARC_HINT_PN = 1 << 2, ///< branch NOT taken +} sparc_hint; + +/// Operand type for instruction's operands +typedef enum sparc_op_type { + SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + SPARC_OP_REG, ///< = CS_OP_REG (Register operand). + SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} sparc_op_type; + +/// SPARC registers +typedef enum sparc_reg { + SPARC_REG_INVALID = 0, + + SPARC_REG_F0, + SPARC_REG_F1, + SPARC_REG_F2, + SPARC_REG_F3, + SPARC_REG_F4, + SPARC_REG_F5, + SPARC_REG_F6, + SPARC_REG_F7, + SPARC_REG_F8, + SPARC_REG_F9, + SPARC_REG_F10, + SPARC_REG_F11, + SPARC_REG_F12, + SPARC_REG_F13, + SPARC_REG_F14, + SPARC_REG_F15, + SPARC_REG_F16, + SPARC_REG_F17, + SPARC_REG_F18, + SPARC_REG_F19, + SPARC_REG_F20, + SPARC_REG_F21, + SPARC_REG_F22, + SPARC_REG_F23, + SPARC_REG_F24, + SPARC_REG_F25, + SPARC_REG_F26, + SPARC_REG_F27, + SPARC_REG_F28, + SPARC_REG_F29, + SPARC_REG_F30, + SPARC_REG_F31, + SPARC_REG_F32, + SPARC_REG_F34, + SPARC_REG_F36, + SPARC_REG_F38, + SPARC_REG_F40, + SPARC_REG_F42, + SPARC_REG_F44, + SPARC_REG_F46, + SPARC_REG_F48, + SPARC_REG_F50, + SPARC_REG_F52, + SPARC_REG_F54, + SPARC_REG_F56, + SPARC_REG_F58, + SPARC_REG_F60, + SPARC_REG_F62, + SPARC_REG_FCC0, // Floating condition codes + SPARC_REG_FCC1, + SPARC_REG_FCC2, + SPARC_REG_FCC3, + SPARC_REG_FP, + SPARC_REG_G0, + SPARC_REG_G1, + SPARC_REG_G2, + SPARC_REG_G3, + SPARC_REG_G4, + SPARC_REG_G5, + SPARC_REG_G6, + SPARC_REG_G7, + SPARC_REG_I0, + SPARC_REG_I1, + SPARC_REG_I2, + SPARC_REG_I3, + SPARC_REG_I4, + SPARC_REG_I5, + SPARC_REG_I7, + SPARC_REG_ICC, // Integer condition codes + SPARC_REG_L0, + SPARC_REG_L1, + SPARC_REG_L2, + SPARC_REG_L3, + SPARC_REG_L4, + SPARC_REG_L5, + SPARC_REG_L6, + SPARC_REG_L7, + SPARC_REG_O0, + SPARC_REG_O1, + SPARC_REG_O2, + SPARC_REG_O3, + SPARC_REG_O4, + SPARC_REG_O5, + SPARC_REG_O7, + SPARC_REG_SP, + SPARC_REG_Y, + + // special register + SPARC_REG_XCC, + + SPARC_REG_ENDING, // <-- mark the end of the list of registers + + // extras + SPARC_REG_O6 = SPARC_REG_SP, + SPARC_REG_I6 = SPARC_REG_FP, +} sparc_reg; + +/// Instruction's operand referring to memory +/// This is associated with SPARC_OP_MEM operand type above +typedef struct sparc_op_mem { + uint8_t base; ///< base register, can be safely interpreted as + ///< a value of type `sparc_reg`, but it is only + ///< one byte wide + uint8_t index; ///< index register, same conditions apply here + int32_t disp; ///< displacement/offset value +} sparc_op_mem; + +/// Instruction operand +typedef struct cs_sparc_op { + sparc_op_type type; ///< operand type + union { + sparc_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + sparc_op_mem mem; ///< base/disp value for MEM operand + }; +} cs_sparc_op; + +/// Instruction structure +typedef struct cs_sparc { + sparc_cc cc; ///< code condition for this insn + sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint. + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_sparc_op operands[4]; ///< operands for this instruction. +} cs_sparc; + +/// SPARC instruction +typedef enum sparc_insn { + SPARC_INS_INVALID = 0, + + SPARC_INS_ADDCC, + SPARC_INS_ADDX, + SPARC_INS_ADDXCC, + SPARC_INS_ADDXC, + SPARC_INS_ADDXCCC, + SPARC_INS_ADD, + SPARC_INS_ALIGNADDR, + SPARC_INS_ALIGNADDRL, + SPARC_INS_ANDCC, + SPARC_INS_ANDNCC, + SPARC_INS_ANDN, + SPARC_INS_AND, + SPARC_INS_ARRAY16, + SPARC_INS_ARRAY32, + SPARC_INS_ARRAY8, + SPARC_INS_B, + SPARC_INS_JMP, + SPARC_INS_BMASK, + SPARC_INS_FB, + SPARC_INS_BRGEZ, + SPARC_INS_BRGZ, + SPARC_INS_BRLEZ, + SPARC_INS_BRLZ, + SPARC_INS_BRNZ, + SPARC_INS_BRZ, + SPARC_INS_BSHUFFLE, + SPARC_INS_CALL, + SPARC_INS_CASX, + SPARC_INS_CAS, + SPARC_INS_CMASK16, + SPARC_INS_CMASK32, + SPARC_INS_CMASK8, + SPARC_INS_CMP, + SPARC_INS_EDGE16, + SPARC_INS_EDGE16L, + SPARC_INS_EDGE16LN, + SPARC_INS_EDGE16N, + SPARC_INS_EDGE32, + SPARC_INS_EDGE32L, + SPARC_INS_EDGE32LN, + SPARC_INS_EDGE32N, + SPARC_INS_EDGE8, + SPARC_INS_EDGE8L, + SPARC_INS_EDGE8LN, + SPARC_INS_EDGE8N, + SPARC_INS_FABSD, + SPARC_INS_FABSQ, + SPARC_INS_FABSS, + SPARC_INS_FADDD, + SPARC_INS_FADDQ, + SPARC_INS_FADDS, + SPARC_INS_FALIGNDATA, + SPARC_INS_FAND, + SPARC_INS_FANDNOT1, + SPARC_INS_FANDNOT1S, + SPARC_INS_FANDNOT2, + SPARC_INS_FANDNOT2S, + SPARC_INS_FANDS, + SPARC_INS_FCHKSM16, + SPARC_INS_FCMPD, + SPARC_INS_FCMPEQ16, + SPARC_INS_FCMPEQ32, + SPARC_INS_FCMPGT16, + SPARC_INS_FCMPGT32, + SPARC_INS_FCMPLE16, + SPARC_INS_FCMPLE32, + SPARC_INS_FCMPNE16, + SPARC_INS_FCMPNE32, + SPARC_INS_FCMPQ, + SPARC_INS_FCMPS, + SPARC_INS_FDIVD, + SPARC_INS_FDIVQ, + SPARC_INS_FDIVS, + SPARC_INS_FDMULQ, + SPARC_INS_FDTOI, + SPARC_INS_FDTOQ, + SPARC_INS_FDTOS, + SPARC_INS_FDTOX, + SPARC_INS_FEXPAND, + SPARC_INS_FHADDD, + SPARC_INS_FHADDS, + SPARC_INS_FHSUBD, + SPARC_INS_FHSUBS, + SPARC_INS_FITOD, + SPARC_INS_FITOQ, + SPARC_INS_FITOS, + SPARC_INS_FLCMPD, + SPARC_INS_FLCMPS, + SPARC_INS_FLUSHW, + SPARC_INS_FMEAN16, + SPARC_INS_FMOVD, + SPARC_INS_FMOVQ, + SPARC_INS_FMOVRDGEZ, + SPARC_INS_FMOVRQGEZ, + SPARC_INS_FMOVRSGEZ, + SPARC_INS_FMOVRDGZ, + SPARC_INS_FMOVRQGZ, + SPARC_INS_FMOVRSGZ, + SPARC_INS_FMOVRDLEZ, + SPARC_INS_FMOVRQLEZ, + SPARC_INS_FMOVRSLEZ, + SPARC_INS_FMOVRDLZ, + SPARC_INS_FMOVRQLZ, + SPARC_INS_FMOVRSLZ, + SPARC_INS_FMOVRDNZ, + SPARC_INS_FMOVRQNZ, + SPARC_INS_FMOVRSNZ, + SPARC_INS_FMOVRDZ, + SPARC_INS_FMOVRQZ, + SPARC_INS_FMOVRSZ, + SPARC_INS_FMOVS, + SPARC_INS_FMUL8SUX16, + SPARC_INS_FMUL8ULX16, + SPARC_INS_FMUL8X16, + SPARC_INS_FMUL8X16AL, + SPARC_INS_FMUL8X16AU, + SPARC_INS_FMULD, + SPARC_INS_FMULD8SUX16, + SPARC_INS_FMULD8ULX16, + SPARC_INS_FMULQ, + SPARC_INS_FMULS, + SPARC_INS_FNADDD, + SPARC_INS_FNADDS, + SPARC_INS_FNAND, + SPARC_INS_FNANDS, + SPARC_INS_FNEGD, + SPARC_INS_FNEGQ, + SPARC_INS_FNEGS, + SPARC_INS_FNHADDD, + SPARC_INS_FNHADDS, + SPARC_INS_FNOR, + SPARC_INS_FNORS, + SPARC_INS_FNOT1, + SPARC_INS_FNOT1S, + SPARC_INS_FNOT2, + SPARC_INS_FNOT2S, + SPARC_INS_FONE, + SPARC_INS_FONES, + SPARC_INS_FOR, + SPARC_INS_FORNOT1, + SPARC_INS_FORNOT1S, + SPARC_INS_FORNOT2, + SPARC_INS_FORNOT2S, + SPARC_INS_FORS, + SPARC_INS_FPACK16, + SPARC_INS_FPACK32, + SPARC_INS_FPACKFIX, + SPARC_INS_FPADD16, + SPARC_INS_FPADD16S, + SPARC_INS_FPADD32, + SPARC_INS_FPADD32S, + SPARC_INS_FPADD64, + SPARC_INS_FPMERGE, + SPARC_INS_FPSUB16, + SPARC_INS_FPSUB16S, + SPARC_INS_FPSUB32, + SPARC_INS_FPSUB32S, + SPARC_INS_FQTOD, + SPARC_INS_FQTOI, + SPARC_INS_FQTOS, + SPARC_INS_FQTOX, + SPARC_INS_FSLAS16, + SPARC_INS_FSLAS32, + SPARC_INS_FSLL16, + SPARC_INS_FSLL32, + SPARC_INS_FSMULD, + SPARC_INS_FSQRTD, + SPARC_INS_FSQRTQ, + SPARC_INS_FSQRTS, + SPARC_INS_FSRA16, + SPARC_INS_FSRA32, + SPARC_INS_FSRC1, + SPARC_INS_FSRC1S, + SPARC_INS_FSRC2, + SPARC_INS_FSRC2S, + SPARC_INS_FSRL16, + SPARC_INS_FSRL32, + SPARC_INS_FSTOD, + SPARC_INS_FSTOI, + SPARC_INS_FSTOQ, + SPARC_INS_FSTOX, + SPARC_INS_FSUBD, + SPARC_INS_FSUBQ, + SPARC_INS_FSUBS, + SPARC_INS_FXNOR, + SPARC_INS_FXNORS, + SPARC_INS_FXOR, + SPARC_INS_FXORS, + SPARC_INS_FXTOD, + SPARC_INS_FXTOQ, + SPARC_INS_FXTOS, + SPARC_INS_FZERO, + SPARC_INS_FZEROS, + SPARC_INS_JMPL, + SPARC_INS_LDD, + SPARC_INS_LD, + SPARC_INS_LDQ, + SPARC_INS_LDSB, + SPARC_INS_LDSH, + SPARC_INS_LDSW, + SPARC_INS_LDUB, + SPARC_INS_LDUH, + SPARC_INS_LDX, + SPARC_INS_LZCNT, + SPARC_INS_MEMBAR, + SPARC_INS_MOVDTOX, + SPARC_INS_MOV, + SPARC_INS_MOVRGEZ, + SPARC_INS_MOVRGZ, + SPARC_INS_MOVRLEZ, + SPARC_INS_MOVRLZ, + SPARC_INS_MOVRNZ, + SPARC_INS_MOVRZ, + SPARC_INS_MOVSTOSW, + SPARC_INS_MOVSTOUW, + SPARC_INS_MULX, + SPARC_INS_NOP, + SPARC_INS_ORCC, + SPARC_INS_ORNCC, + SPARC_INS_ORN, + SPARC_INS_OR, + SPARC_INS_PDIST, + SPARC_INS_PDISTN, + SPARC_INS_POPC, + SPARC_INS_RD, + SPARC_INS_RESTORE, + SPARC_INS_RETT, + SPARC_INS_SAVE, + SPARC_INS_SDIVCC, + SPARC_INS_SDIVX, + SPARC_INS_SDIV, + SPARC_INS_SETHI, + SPARC_INS_SHUTDOWN, + SPARC_INS_SIAM, + SPARC_INS_SLLX, + SPARC_INS_SLL, + SPARC_INS_SMULCC, + SPARC_INS_SMUL, + SPARC_INS_SRAX, + SPARC_INS_SRA, + SPARC_INS_SRLX, + SPARC_INS_SRL, + SPARC_INS_STBAR, + SPARC_INS_STB, + SPARC_INS_STD, + SPARC_INS_ST, + SPARC_INS_STH, + SPARC_INS_STQ, + SPARC_INS_STX, + SPARC_INS_SUBCC, + SPARC_INS_SUBX, + SPARC_INS_SUBXCC, + SPARC_INS_SUB, + SPARC_INS_SWAP, + SPARC_INS_TADDCCTV, + SPARC_INS_TADDCC, + SPARC_INS_T, + SPARC_INS_TSUBCCTV, + SPARC_INS_TSUBCC, + SPARC_INS_UDIVCC, + SPARC_INS_UDIVX, + SPARC_INS_UDIV, + SPARC_INS_UMULCC, + SPARC_INS_UMULXHI, + SPARC_INS_UMUL, + SPARC_INS_UNIMP, + SPARC_INS_FCMPED, + SPARC_INS_FCMPEQ, + SPARC_INS_FCMPES, + SPARC_INS_WR, + SPARC_INS_XMULX, + SPARC_INS_XMULXHI, + SPARC_INS_XNORCC, + SPARC_INS_XNOR, + SPARC_INS_XORCC, + SPARC_INS_XOR, + + // alias instructions + SPARC_INS_RET, + SPARC_INS_RETL, + + SPARC_INS_ENDING, // <-- mark the end of the list of instructions +} sparc_insn; + +/// Group of SPARC instructions +typedef enum sparc_insn_group { + SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + SPARC_GRP_JUMP, ///< = CS_GRP_JUMP + + // Architecture-specific groups + SPARC_GRP_HARDQUAD = 128, + SPARC_GRP_V9, + SPARC_GRP_VIS, + SPARC_GRP_VIS2, + SPARC_GRP_VIS3, + SPARC_GRP_32BIT, + SPARC_GRP_64BIT, + + SPARC_GRP_ENDING, // <-- mark the end of the list of groups +} sparc_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/systemz.h b/white_patch_detect/capstone-master/include/capstone/systemz.h new file mode 100644 index 0000000..5be27df --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/systemz.h @@ -0,0 +1,2601 @@ +#ifndef CAPSTONE_SYSTEMZ_H +#define CAPSTONE_SYSTEMZ_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2014-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// Enums corresponding to SystemZ condition codes +typedef enum sysz_cc { + SYSZ_CC_INVALID = 0, ///< invalid CC (default) + + SYSZ_CC_O, + SYSZ_CC_H, + SYSZ_CC_NLE, + SYSZ_CC_L, + SYSZ_CC_NHE, + SYSZ_CC_LH, + SYSZ_CC_NE, + SYSZ_CC_E, + SYSZ_CC_NLH, + SYSZ_CC_HE, + SYSZ_CC_NL, + SYSZ_CC_LE, + SYSZ_CC_NH, + SYSZ_CC_NO, +} sysz_cc; + +/// Operand type for instruction's operands +typedef enum sysz_op_type { + SYSZ_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + SYSZ_OP_REG, ///< = CS_OP_REG (Register operand). + SYSZ_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + SYSZ_OP_MEM, ///< = CS_OP_MEM (Memory operand). + SYSZ_OP_ACREG = 64, ///< Access register operand. +} sysz_op_type; + +/// SystemZ registers +typedef enum sysz_reg { + SYSZ_REG_INVALID = 0, + + SYSZ_REG_0, + SYSZ_REG_1, + SYSZ_REG_2, + SYSZ_REG_3, + SYSZ_REG_4, + SYSZ_REG_5, + SYSZ_REG_6, + SYSZ_REG_7, + SYSZ_REG_8, + SYSZ_REG_9, + SYSZ_REG_10, + SYSZ_REG_11, + SYSZ_REG_12, + SYSZ_REG_13, + SYSZ_REG_14, + SYSZ_REG_15, + SYSZ_REG_CC, + SYSZ_REG_F0, + SYSZ_REG_F1, + SYSZ_REG_F2, + SYSZ_REG_F3, + SYSZ_REG_F4, + SYSZ_REG_F5, + SYSZ_REG_F6, + SYSZ_REG_F7, + SYSZ_REG_F8, + SYSZ_REG_F9, + SYSZ_REG_F10, + SYSZ_REG_F11, + SYSZ_REG_F12, + SYSZ_REG_F13, + SYSZ_REG_F14, + SYSZ_REG_F15, + + SYSZ_REG_R0L, + + SYSZ_REG_A0, + SYSZ_REG_A1, + SYSZ_REG_A2, + SYSZ_REG_A3, + SYSZ_REG_A4, + SYSZ_REG_A5, + SYSZ_REG_A6, + SYSZ_REG_A7, + SYSZ_REG_A8, + SYSZ_REG_A9, + SYSZ_REG_A10, + SYSZ_REG_A11, + SYSZ_REG_A12, + SYSZ_REG_A13, + SYSZ_REG_A14, + SYSZ_REG_A15, + SYSZ_REG_C0, + SYSZ_REG_C1, + SYSZ_REG_C2, + SYSZ_REG_C3, + SYSZ_REG_C4, + SYSZ_REG_C5, + SYSZ_REG_C6, + SYSZ_REG_C7, + SYSZ_REG_C8, + SYSZ_REG_C9, + SYSZ_REG_C10, + SYSZ_REG_C11, + SYSZ_REG_C12, + SYSZ_REG_C13, + SYSZ_REG_C14, + SYSZ_REG_C15, + SYSZ_REG_V0, + SYSZ_REG_V1, + SYSZ_REG_V2, + SYSZ_REG_V3, + SYSZ_REG_V4, + SYSZ_REG_V5, + SYSZ_REG_V6, + SYSZ_REG_V7, + SYSZ_REG_V8, + SYSZ_REG_V9, + SYSZ_REG_V10, + SYSZ_REG_V11, + SYSZ_REG_V12, + SYSZ_REG_V13, + SYSZ_REG_V14, + SYSZ_REG_V15, + SYSZ_REG_V16, + SYSZ_REG_V17, + SYSZ_REG_V18, + SYSZ_REG_V19, + SYSZ_REG_V20, + SYSZ_REG_V21, + SYSZ_REG_V22, + SYSZ_REG_V23, + SYSZ_REG_V24, + SYSZ_REG_V25, + SYSZ_REG_V26, + SYSZ_REG_V27, + SYSZ_REG_V28, + SYSZ_REG_V29, + SYSZ_REG_V30, + SYSZ_REG_V31, + SYSZ_REG_F16, + SYSZ_REG_F17, + SYSZ_REG_F18, + SYSZ_REG_F19, + SYSZ_REG_F20, + SYSZ_REG_F21, + SYSZ_REG_F22, + SYSZ_REG_F23, + SYSZ_REG_F24, + SYSZ_REG_F25, + SYSZ_REG_F26, + SYSZ_REG_F27, + SYSZ_REG_F28, + SYSZ_REG_F29, + SYSZ_REG_F30, + SYSZ_REG_F31, + SYSZ_REG_F0Q, + SYSZ_REG_F4Q, + + SYSZ_REG_ENDING, +} sysz_reg; + +/// Instruction's operand referring to memory +/// This is associated with SYSZ_OP_MEM operand type above +typedef struct sysz_op_mem { + uint8_t base; ///< base register, can be safely interpreted as + ///< a value of type `sysz_reg`, but it is only + ///< one byte wide + uint8_t index; ///< index register, same conditions apply here + uint64_t length; ///< BDLAddr operand + int64_t disp; ///< displacement/offset value +} sysz_op_mem; + +/// Instruction operand +typedef struct cs_sysz_op { + sysz_op_type type; ///< operand type + union { + sysz_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + sysz_op_mem mem; ///< base/disp value for MEM operand + }; +} cs_sysz_op; + +// Instruction structure +typedef struct cs_sysz { + sysz_cc cc; ///< Code condition + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_sysz_op operands[6]; ///< operands for this instruction. +} cs_sysz; + +/// SystemZ instruction +typedef enum sysz_insn { + SYSZ_INS_INVALID = 0, + + SYSZ_INS_A, + SYSZ_INS_ADB, + SYSZ_INS_ADBR, + SYSZ_INS_AEB, + SYSZ_INS_AEBR, + SYSZ_INS_AFI, + SYSZ_INS_AG, + SYSZ_INS_AGF, + SYSZ_INS_AGFI, + SYSZ_INS_AGFR, + SYSZ_INS_AGHI, + SYSZ_INS_AGHIK, + SYSZ_INS_AGR, + SYSZ_INS_AGRK, + SYSZ_INS_AGSI, + SYSZ_INS_AH, + SYSZ_INS_AHI, + SYSZ_INS_AHIK, + SYSZ_INS_AHY, + SYSZ_INS_AIH, + SYSZ_INS_AL, + SYSZ_INS_ALC, + SYSZ_INS_ALCG, + SYSZ_INS_ALCGR, + SYSZ_INS_ALCR, + SYSZ_INS_ALFI, + SYSZ_INS_ALG, + SYSZ_INS_ALGF, + SYSZ_INS_ALGFI, + SYSZ_INS_ALGFR, + SYSZ_INS_ALGHSIK, + SYSZ_INS_ALGR, + SYSZ_INS_ALGRK, + SYSZ_INS_ALHSIK, + SYSZ_INS_ALR, + SYSZ_INS_ALRK, + SYSZ_INS_ALY, + SYSZ_INS_AR, + SYSZ_INS_ARK, + SYSZ_INS_ASI, + SYSZ_INS_AXBR, + SYSZ_INS_AY, + SYSZ_INS_BCR, + SYSZ_INS_BRC, + SYSZ_INS_BRCL, + SYSZ_INS_CGIJ, + SYSZ_INS_CGRJ, + SYSZ_INS_CIJ, + SYSZ_INS_CLGIJ, + SYSZ_INS_CLGRJ, + SYSZ_INS_CLIJ, + SYSZ_INS_CLRJ, + SYSZ_INS_CRJ, + SYSZ_INS_BER, + SYSZ_INS_JE, + SYSZ_INS_JGE, + SYSZ_INS_LOCE, + SYSZ_INS_LOCGE, + SYSZ_INS_LOCGRE, + SYSZ_INS_LOCRE, + SYSZ_INS_STOCE, + SYSZ_INS_STOCGE, + SYSZ_INS_BHR, + SYSZ_INS_BHER, + SYSZ_INS_JHE, + SYSZ_INS_JGHE, + SYSZ_INS_LOCHE, + SYSZ_INS_LOCGHE, + SYSZ_INS_LOCGRHE, + SYSZ_INS_LOCRHE, + SYSZ_INS_STOCHE, + SYSZ_INS_STOCGHE, + SYSZ_INS_JH, + SYSZ_INS_JGH, + SYSZ_INS_LOCH, + SYSZ_INS_LOCGH, + SYSZ_INS_LOCGRH, + SYSZ_INS_LOCRH, + SYSZ_INS_STOCH, + SYSZ_INS_STOCGH, + SYSZ_INS_CGIJNLH, + SYSZ_INS_CGRJNLH, + SYSZ_INS_CIJNLH, + SYSZ_INS_CLGIJNLH, + SYSZ_INS_CLGRJNLH, + SYSZ_INS_CLIJNLH, + SYSZ_INS_CLRJNLH, + SYSZ_INS_CRJNLH, + SYSZ_INS_CGIJE, + SYSZ_INS_CGRJE, + SYSZ_INS_CIJE, + SYSZ_INS_CLGIJE, + SYSZ_INS_CLGRJE, + SYSZ_INS_CLIJE, + SYSZ_INS_CLRJE, + SYSZ_INS_CRJE, + SYSZ_INS_CGIJNLE, + SYSZ_INS_CGRJNLE, + SYSZ_INS_CIJNLE, + SYSZ_INS_CLGIJNLE, + SYSZ_INS_CLGRJNLE, + SYSZ_INS_CLIJNLE, + SYSZ_INS_CLRJNLE, + SYSZ_INS_CRJNLE, + SYSZ_INS_CGIJH, + SYSZ_INS_CGRJH, + SYSZ_INS_CIJH, + SYSZ_INS_CLGIJH, + SYSZ_INS_CLGRJH, + SYSZ_INS_CLIJH, + SYSZ_INS_CLRJH, + SYSZ_INS_CRJH, + SYSZ_INS_CGIJNL, + SYSZ_INS_CGRJNL, + SYSZ_INS_CIJNL, + SYSZ_INS_CLGIJNL, + SYSZ_INS_CLGRJNL, + SYSZ_INS_CLIJNL, + SYSZ_INS_CLRJNL, + SYSZ_INS_CRJNL, + SYSZ_INS_CGIJHE, + SYSZ_INS_CGRJHE, + SYSZ_INS_CIJHE, + SYSZ_INS_CLGIJHE, + SYSZ_INS_CLGRJHE, + SYSZ_INS_CLIJHE, + SYSZ_INS_CLRJHE, + SYSZ_INS_CRJHE, + SYSZ_INS_CGIJNHE, + SYSZ_INS_CGRJNHE, + SYSZ_INS_CIJNHE, + SYSZ_INS_CLGIJNHE, + SYSZ_INS_CLGRJNHE, + SYSZ_INS_CLIJNHE, + SYSZ_INS_CLRJNHE, + SYSZ_INS_CRJNHE, + SYSZ_INS_CGIJL, + SYSZ_INS_CGRJL, + SYSZ_INS_CIJL, + SYSZ_INS_CLGIJL, + SYSZ_INS_CLGRJL, + SYSZ_INS_CLIJL, + SYSZ_INS_CLRJL, + SYSZ_INS_CRJL, + SYSZ_INS_CGIJNH, + SYSZ_INS_CGRJNH, + SYSZ_INS_CIJNH, + SYSZ_INS_CLGIJNH, + SYSZ_INS_CLGRJNH, + SYSZ_INS_CLIJNH, + SYSZ_INS_CLRJNH, + SYSZ_INS_CRJNH, + SYSZ_INS_CGIJLE, + SYSZ_INS_CGRJLE, + SYSZ_INS_CIJLE, + SYSZ_INS_CLGIJLE, + SYSZ_INS_CLGRJLE, + SYSZ_INS_CLIJLE, + SYSZ_INS_CLRJLE, + SYSZ_INS_CRJLE, + SYSZ_INS_CGIJNE, + SYSZ_INS_CGRJNE, + SYSZ_INS_CIJNE, + SYSZ_INS_CLGIJNE, + SYSZ_INS_CLGRJNE, + SYSZ_INS_CLIJNE, + SYSZ_INS_CLRJNE, + SYSZ_INS_CRJNE, + SYSZ_INS_CGIJLH, + SYSZ_INS_CGRJLH, + SYSZ_INS_CIJLH, + SYSZ_INS_CLGIJLH, + SYSZ_INS_CLGRJLH, + SYSZ_INS_CLIJLH, + SYSZ_INS_CLRJLH, + SYSZ_INS_CRJLH, + SYSZ_INS_BLR, + SYSZ_INS_BLER, + SYSZ_INS_JLE, + SYSZ_INS_JGLE, + SYSZ_INS_LOCLE, + SYSZ_INS_LOCGLE, + SYSZ_INS_LOCGRLE, + SYSZ_INS_LOCRLE, + SYSZ_INS_STOCLE, + SYSZ_INS_STOCGLE, + SYSZ_INS_BLHR, + SYSZ_INS_JLH, + SYSZ_INS_JGLH, + SYSZ_INS_LOCLH, + SYSZ_INS_LOCGLH, + SYSZ_INS_LOCGRLH, + SYSZ_INS_LOCRLH, + SYSZ_INS_STOCLH, + SYSZ_INS_STOCGLH, + SYSZ_INS_JL, + SYSZ_INS_JGL, + SYSZ_INS_LOCL, + SYSZ_INS_LOCGL, + SYSZ_INS_LOCGRL, + SYSZ_INS_LOCRL, + SYSZ_INS_LOC, + SYSZ_INS_LOCG, + SYSZ_INS_LOCGR, + SYSZ_INS_LOCR, + SYSZ_INS_STOCL, + SYSZ_INS_STOCGL, + SYSZ_INS_BNER, + SYSZ_INS_JNE, + SYSZ_INS_JGNE, + SYSZ_INS_LOCNE, + SYSZ_INS_LOCGNE, + SYSZ_INS_LOCGRNE, + SYSZ_INS_LOCRNE, + SYSZ_INS_STOCNE, + SYSZ_INS_STOCGNE, + SYSZ_INS_BNHR, + SYSZ_INS_BNHER, + SYSZ_INS_JNHE, + SYSZ_INS_JGNHE, + SYSZ_INS_LOCNHE, + SYSZ_INS_LOCGNHE, + SYSZ_INS_LOCGRNHE, + SYSZ_INS_LOCRNHE, + SYSZ_INS_STOCNHE, + SYSZ_INS_STOCGNHE, + SYSZ_INS_JNH, + SYSZ_INS_JGNH, + SYSZ_INS_LOCNH, + SYSZ_INS_LOCGNH, + SYSZ_INS_LOCGRNH, + SYSZ_INS_LOCRNH, + SYSZ_INS_STOCNH, + SYSZ_INS_STOCGNH, + SYSZ_INS_BNLR, + SYSZ_INS_BNLER, + SYSZ_INS_JNLE, + SYSZ_INS_JGNLE, + SYSZ_INS_LOCNLE, + SYSZ_INS_LOCGNLE, + SYSZ_INS_LOCGRNLE, + SYSZ_INS_LOCRNLE, + SYSZ_INS_STOCNLE, + SYSZ_INS_STOCGNLE, + SYSZ_INS_BNLHR, + SYSZ_INS_JNLH, + SYSZ_INS_JGNLH, + SYSZ_INS_LOCNLH, + SYSZ_INS_LOCGNLH, + SYSZ_INS_LOCGRNLH, + SYSZ_INS_LOCRNLH, + SYSZ_INS_STOCNLH, + SYSZ_INS_STOCGNLH, + SYSZ_INS_JNL, + SYSZ_INS_JGNL, + SYSZ_INS_LOCNL, + SYSZ_INS_LOCGNL, + SYSZ_INS_LOCGRNL, + SYSZ_INS_LOCRNL, + SYSZ_INS_STOCNL, + SYSZ_INS_STOCGNL, + SYSZ_INS_BNOR, + SYSZ_INS_JNO, + SYSZ_INS_JGNO, + SYSZ_INS_LOCNO, + SYSZ_INS_LOCGNO, + SYSZ_INS_LOCGRNO, + SYSZ_INS_LOCRNO, + SYSZ_INS_STOCNO, + SYSZ_INS_STOCGNO, + SYSZ_INS_BOR, + SYSZ_INS_JO, + SYSZ_INS_JGO, + SYSZ_INS_LOCO, + SYSZ_INS_LOCGO, + SYSZ_INS_LOCGRO, + SYSZ_INS_LOCRO, + SYSZ_INS_STOCO, + SYSZ_INS_STOCGO, + SYSZ_INS_STOC, + SYSZ_INS_STOCG, + SYSZ_INS_BASR, + SYSZ_INS_BR, + SYSZ_INS_BRAS, + SYSZ_INS_BRASL, + SYSZ_INS_J, + SYSZ_INS_JG, + SYSZ_INS_BRCT, + SYSZ_INS_BRCTG, + SYSZ_INS_C, + SYSZ_INS_CDB, + SYSZ_INS_CDBR, + SYSZ_INS_CDFBR, + SYSZ_INS_CDGBR, + SYSZ_INS_CDLFBR, + SYSZ_INS_CDLGBR, + SYSZ_INS_CEB, + SYSZ_INS_CEBR, + SYSZ_INS_CEFBR, + SYSZ_INS_CEGBR, + SYSZ_INS_CELFBR, + SYSZ_INS_CELGBR, + SYSZ_INS_CFDBR, + SYSZ_INS_CFEBR, + SYSZ_INS_CFI, + SYSZ_INS_CFXBR, + SYSZ_INS_CG, + SYSZ_INS_CGDBR, + SYSZ_INS_CGEBR, + SYSZ_INS_CGF, + SYSZ_INS_CGFI, + SYSZ_INS_CGFR, + SYSZ_INS_CGFRL, + SYSZ_INS_CGH, + SYSZ_INS_CGHI, + SYSZ_INS_CGHRL, + SYSZ_INS_CGHSI, + SYSZ_INS_CGR, + SYSZ_INS_CGRL, + SYSZ_INS_CGXBR, + SYSZ_INS_CH, + SYSZ_INS_CHF, + SYSZ_INS_CHHSI, + SYSZ_INS_CHI, + SYSZ_INS_CHRL, + SYSZ_INS_CHSI, + SYSZ_INS_CHY, + SYSZ_INS_CIH, + SYSZ_INS_CL, + SYSZ_INS_CLC, + SYSZ_INS_CLFDBR, + SYSZ_INS_CLFEBR, + SYSZ_INS_CLFHSI, + SYSZ_INS_CLFI, + SYSZ_INS_CLFXBR, + SYSZ_INS_CLG, + SYSZ_INS_CLGDBR, + SYSZ_INS_CLGEBR, + SYSZ_INS_CLGF, + SYSZ_INS_CLGFI, + SYSZ_INS_CLGFR, + SYSZ_INS_CLGFRL, + SYSZ_INS_CLGHRL, + SYSZ_INS_CLGHSI, + SYSZ_INS_CLGR, + SYSZ_INS_CLGRL, + SYSZ_INS_CLGXBR, + SYSZ_INS_CLHF, + SYSZ_INS_CLHHSI, + SYSZ_INS_CLHRL, + SYSZ_INS_CLI, + SYSZ_INS_CLIH, + SYSZ_INS_CLIY, + SYSZ_INS_CLR, + SYSZ_INS_CLRL, + SYSZ_INS_CLST, + SYSZ_INS_CLY, + SYSZ_INS_CPSDR, + SYSZ_INS_CR, + SYSZ_INS_CRL, + SYSZ_INS_CS, + SYSZ_INS_CSG, + SYSZ_INS_CSY, + SYSZ_INS_CXBR, + SYSZ_INS_CXFBR, + SYSZ_INS_CXGBR, + SYSZ_INS_CXLFBR, + SYSZ_INS_CXLGBR, + SYSZ_INS_CY, + SYSZ_INS_DDB, + SYSZ_INS_DDBR, + SYSZ_INS_DEB, + SYSZ_INS_DEBR, + SYSZ_INS_DL, + SYSZ_INS_DLG, + SYSZ_INS_DLGR, + SYSZ_INS_DLR, + SYSZ_INS_DSG, + SYSZ_INS_DSGF, + SYSZ_INS_DSGFR, + SYSZ_INS_DSGR, + SYSZ_INS_DXBR, + SYSZ_INS_EAR, + SYSZ_INS_FIDBR, + SYSZ_INS_FIDBRA, + SYSZ_INS_FIEBR, + SYSZ_INS_FIEBRA, + SYSZ_INS_FIXBR, + SYSZ_INS_FIXBRA, + SYSZ_INS_FLOGR, + SYSZ_INS_IC, + SYSZ_INS_ICY, + SYSZ_INS_IIHF, + SYSZ_INS_IIHH, + SYSZ_INS_IIHL, + SYSZ_INS_IILF, + SYSZ_INS_IILH, + SYSZ_INS_IILL, + SYSZ_INS_IPM, + SYSZ_INS_L, + SYSZ_INS_LA, + SYSZ_INS_LAA, + SYSZ_INS_LAAG, + SYSZ_INS_LAAL, + SYSZ_INS_LAALG, + SYSZ_INS_LAN, + SYSZ_INS_LANG, + SYSZ_INS_LAO, + SYSZ_INS_LAOG, + SYSZ_INS_LARL, + SYSZ_INS_LAX, + SYSZ_INS_LAXG, + SYSZ_INS_LAY, + SYSZ_INS_LB, + SYSZ_INS_LBH, + SYSZ_INS_LBR, + SYSZ_INS_LCDBR, + SYSZ_INS_LCEBR, + SYSZ_INS_LCGFR, + SYSZ_INS_LCGR, + SYSZ_INS_LCR, + SYSZ_INS_LCXBR, + SYSZ_INS_LD, + SYSZ_INS_LDEB, + SYSZ_INS_LDEBR, + SYSZ_INS_LDGR, + SYSZ_INS_LDR, + SYSZ_INS_LDXBR, + SYSZ_INS_LDXBRA, + SYSZ_INS_LDY, + SYSZ_INS_LE, + SYSZ_INS_LEDBR, + SYSZ_INS_LEDBRA, + SYSZ_INS_LER, + SYSZ_INS_LEXBR, + SYSZ_INS_LEXBRA, + SYSZ_INS_LEY, + SYSZ_INS_LFH, + SYSZ_INS_LG, + SYSZ_INS_LGB, + SYSZ_INS_LGBR, + SYSZ_INS_LGDR, + SYSZ_INS_LGF, + SYSZ_INS_LGFI, + SYSZ_INS_LGFR, + SYSZ_INS_LGFRL, + SYSZ_INS_LGH, + SYSZ_INS_LGHI, + SYSZ_INS_LGHR, + SYSZ_INS_LGHRL, + SYSZ_INS_LGR, + SYSZ_INS_LGRL, + SYSZ_INS_LH, + SYSZ_INS_LHH, + SYSZ_INS_LHI, + SYSZ_INS_LHR, + SYSZ_INS_LHRL, + SYSZ_INS_LHY, + SYSZ_INS_LLC, + SYSZ_INS_LLCH, + SYSZ_INS_LLCR, + SYSZ_INS_LLGC, + SYSZ_INS_LLGCR, + SYSZ_INS_LLGF, + SYSZ_INS_LLGFR, + SYSZ_INS_LLGFRL, + SYSZ_INS_LLGH, + SYSZ_INS_LLGHR, + SYSZ_INS_LLGHRL, + SYSZ_INS_LLH, + SYSZ_INS_LLHH, + SYSZ_INS_LLHR, + SYSZ_INS_LLHRL, + SYSZ_INS_LLIHF, + SYSZ_INS_LLIHH, + SYSZ_INS_LLIHL, + SYSZ_INS_LLILF, + SYSZ_INS_LLILH, + SYSZ_INS_LLILL, + SYSZ_INS_LMG, + SYSZ_INS_LNDBR, + SYSZ_INS_LNEBR, + SYSZ_INS_LNGFR, + SYSZ_INS_LNGR, + SYSZ_INS_LNR, + SYSZ_INS_LNXBR, + SYSZ_INS_LPDBR, + SYSZ_INS_LPEBR, + SYSZ_INS_LPGFR, + SYSZ_INS_LPGR, + SYSZ_INS_LPR, + SYSZ_INS_LPXBR, + SYSZ_INS_LR, + SYSZ_INS_LRL, + SYSZ_INS_LRV, + SYSZ_INS_LRVG, + SYSZ_INS_LRVGR, + SYSZ_INS_LRVR, + SYSZ_INS_LT, + SYSZ_INS_LTDBR, + SYSZ_INS_LTEBR, + SYSZ_INS_LTG, + SYSZ_INS_LTGF, + SYSZ_INS_LTGFR, + SYSZ_INS_LTGR, + SYSZ_INS_LTR, + SYSZ_INS_LTXBR, + SYSZ_INS_LXDB, + SYSZ_INS_LXDBR, + SYSZ_INS_LXEB, + SYSZ_INS_LXEBR, + SYSZ_INS_LXR, + SYSZ_INS_LY, + SYSZ_INS_LZDR, + SYSZ_INS_LZER, + SYSZ_INS_LZXR, + SYSZ_INS_MADB, + SYSZ_INS_MADBR, + SYSZ_INS_MAEB, + SYSZ_INS_MAEBR, + SYSZ_INS_MDB, + SYSZ_INS_MDBR, + SYSZ_INS_MDEB, + SYSZ_INS_MDEBR, + SYSZ_INS_MEEB, + SYSZ_INS_MEEBR, + SYSZ_INS_MGHI, + SYSZ_INS_MH, + SYSZ_INS_MHI, + SYSZ_INS_MHY, + SYSZ_INS_MLG, + SYSZ_INS_MLGR, + SYSZ_INS_MS, + SYSZ_INS_MSDB, + SYSZ_INS_MSDBR, + SYSZ_INS_MSEB, + SYSZ_INS_MSEBR, + SYSZ_INS_MSFI, + SYSZ_INS_MSG, + SYSZ_INS_MSGF, + SYSZ_INS_MSGFI, + SYSZ_INS_MSGFR, + SYSZ_INS_MSGR, + SYSZ_INS_MSR, + SYSZ_INS_MSY, + SYSZ_INS_MVC, + SYSZ_INS_MVGHI, + SYSZ_INS_MVHHI, + SYSZ_INS_MVHI, + SYSZ_INS_MVI, + SYSZ_INS_MVIY, + SYSZ_INS_MVST, + SYSZ_INS_MXBR, + SYSZ_INS_MXDB, + SYSZ_INS_MXDBR, + SYSZ_INS_N, + SYSZ_INS_NC, + SYSZ_INS_NG, + SYSZ_INS_NGR, + SYSZ_INS_NGRK, + SYSZ_INS_NI, + SYSZ_INS_NIHF, + SYSZ_INS_NIHH, + SYSZ_INS_NIHL, + SYSZ_INS_NILF, + SYSZ_INS_NILH, + SYSZ_INS_NILL, + SYSZ_INS_NIY, + SYSZ_INS_NR, + SYSZ_INS_NRK, + SYSZ_INS_NY, + SYSZ_INS_O, + SYSZ_INS_OC, + SYSZ_INS_OG, + SYSZ_INS_OGR, + SYSZ_INS_OGRK, + SYSZ_INS_OI, + SYSZ_INS_OIHF, + SYSZ_INS_OIHH, + SYSZ_INS_OIHL, + SYSZ_INS_OILF, + SYSZ_INS_OILH, + SYSZ_INS_OILL, + SYSZ_INS_OIY, + SYSZ_INS_OR, + SYSZ_INS_ORK, + SYSZ_INS_OY, + SYSZ_INS_PFD, + SYSZ_INS_PFDRL, + SYSZ_INS_RISBG, + SYSZ_INS_RISBHG, + SYSZ_INS_RISBLG, + SYSZ_INS_RLL, + SYSZ_INS_RLLG, + SYSZ_INS_RNSBG, + SYSZ_INS_ROSBG, + SYSZ_INS_RXSBG, + SYSZ_INS_S, + SYSZ_INS_SDB, + SYSZ_INS_SDBR, + SYSZ_INS_SEB, + SYSZ_INS_SEBR, + SYSZ_INS_SG, + SYSZ_INS_SGF, + SYSZ_INS_SGFR, + SYSZ_INS_SGR, + SYSZ_INS_SGRK, + SYSZ_INS_SH, + SYSZ_INS_SHY, + SYSZ_INS_SL, + SYSZ_INS_SLB, + SYSZ_INS_SLBG, + SYSZ_INS_SLBR, + SYSZ_INS_SLFI, + SYSZ_INS_SLG, + SYSZ_INS_SLBGR, + SYSZ_INS_SLGF, + SYSZ_INS_SLGFI, + SYSZ_INS_SLGFR, + SYSZ_INS_SLGR, + SYSZ_INS_SLGRK, + SYSZ_INS_SLL, + SYSZ_INS_SLLG, + SYSZ_INS_SLLK, + SYSZ_INS_SLR, + SYSZ_INS_SLRK, + SYSZ_INS_SLY, + SYSZ_INS_SQDB, + SYSZ_INS_SQDBR, + SYSZ_INS_SQEB, + SYSZ_INS_SQEBR, + SYSZ_INS_SQXBR, + SYSZ_INS_SR, + SYSZ_INS_SRA, + SYSZ_INS_SRAG, + SYSZ_INS_SRAK, + SYSZ_INS_SRK, + SYSZ_INS_SRL, + SYSZ_INS_SRLG, + SYSZ_INS_SRLK, + SYSZ_INS_SRST, + SYSZ_INS_ST, + SYSZ_INS_STC, + SYSZ_INS_STCH, + SYSZ_INS_STCY, + SYSZ_INS_STD, + SYSZ_INS_STDY, + SYSZ_INS_STE, + SYSZ_INS_STEY, + SYSZ_INS_STFH, + SYSZ_INS_STG, + SYSZ_INS_STGRL, + SYSZ_INS_STH, + SYSZ_INS_STHH, + SYSZ_INS_STHRL, + SYSZ_INS_STHY, + SYSZ_INS_STMG, + SYSZ_INS_STRL, + SYSZ_INS_STRV, + SYSZ_INS_STRVG, + SYSZ_INS_STY, + SYSZ_INS_SXBR, + SYSZ_INS_SY, + SYSZ_INS_TM, + SYSZ_INS_TMHH, + SYSZ_INS_TMHL, + SYSZ_INS_TMLH, + SYSZ_INS_TMLL, + SYSZ_INS_TMY, + SYSZ_INS_X, + SYSZ_INS_XC, + SYSZ_INS_XG, + SYSZ_INS_XGR, + SYSZ_INS_XGRK, + SYSZ_INS_XI, + SYSZ_INS_XIHF, + SYSZ_INS_XILF, + SYSZ_INS_XIY, + SYSZ_INS_XR, + SYSZ_INS_XRK, + SYSZ_INS_XY, + SYSZ_INS_AD, + SYSZ_INS_ADR, + SYSZ_INS_ADTR, + SYSZ_INS_ADTRA, + SYSZ_INS_AE, + SYSZ_INS_AER, + SYSZ_INS_AGH, + SYSZ_INS_AHHHR, + SYSZ_INS_AHHLR, + SYSZ_INS_ALGSI, + SYSZ_INS_ALHHHR, + SYSZ_INS_ALHHLR, + SYSZ_INS_ALSI, + SYSZ_INS_ALSIH, + SYSZ_INS_ALSIHN, + SYSZ_INS_AP, + SYSZ_INS_AU, + SYSZ_INS_AUR, + SYSZ_INS_AW, + SYSZ_INS_AWR, + SYSZ_INS_AXR, + SYSZ_INS_AXTR, + SYSZ_INS_AXTRA, + SYSZ_INS_B, + SYSZ_INS_BAKR, + SYSZ_INS_BAL, + SYSZ_INS_BALR, + SYSZ_INS_BAS, + SYSZ_INS_BASSM, + SYSZ_INS_BC, + SYSZ_INS_BCT, + SYSZ_INS_BCTG, + SYSZ_INS_BCTGR, + SYSZ_INS_BCTR, + SYSZ_INS_BE, + SYSZ_INS_BH, + SYSZ_INS_BHE, + SYSZ_INS_BI, + SYSZ_INS_BIC, + SYSZ_INS_BIE, + SYSZ_INS_BIH, + SYSZ_INS_BIHE, + SYSZ_INS_BIL, + SYSZ_INS_BILE, + SYSZ_INS_BILH, + SYSZ_INS_BIM, + SYSZ_INS_BINE, + SYSZ_INS_BINH, + SYSZ_INS_BINHE, + SYSZ_INS_BINL, + SYSZ_INS_BINLE, + SYSZ_INS_BINLH, + SYSZ_INS_BINM, + SYSZ_INS_BINO, + SYSZ_INS_BINP, + SYSZ_INS_BINZ, + SYSZ_INS_BIO, + SYSZ_INS_BIP, + SYSZ_INS_BIZ, + SYSZ_INS_BL, + SYSZ_INS_BLE, + SYSZ_INS_BLH, + SYSZ_INS_BM, + SYSZ_INS_BMR, + SYSZ_INS_BNE, + SYSZ_INS_BNH, + SYSZ_INS_BNHE, + SYSZ_INS_BNL, + SYSZ_INS_BNLE, + SYSZ_INS_BNLH, + SYSZ_INS_BNM, + SYSZ_INS_BNMR, + SYSZ_INS_BNO, + SYSZ_INS_BNP, + SYSZ_INS_BNPR, + SYSZ_INS_BNZ, + SYSZ_INS_BNZR, + SYSZ_INS_BO, + SYSZ_INS_BP, + SYSZ_INS_BPP, + SYSZ_INS_BPR, + SYSZ_INS_BPRP, + SYSZ_INS_BRCTH, + SYSZ_INS_BRXH, + SYSZ_INS_BRXHG, + SYSZ_INS_BRXLE, + SYSZ_INS_BRXLG, + SYSZ_INS_BSA, + SYSZ_INS_BSG, + SYSZ_INS_BSM, + SYSZ_INS_BXH, + SYSZ_INS_BXHG, + SYSZ_INS_BXLE, + SYSZ_INS_BXLEG, + SYSZ_INS_BZ, + SYSZ_INS_BZR, + SYSZ_INS_CD, + SYSZ_INS_CDFBRA, + SYSZ_INS_CDFR, + SYSZ_INS_CDFTR, + SYSZ_INS_CDGBRA, + SYSZ_INS_CDGR, + SYSZ_INS_CDGTR, + SYSZ_INS_CDGTRA, + SYSZ_INS_CDLFTR, + SYSZ_INS_CDLGTR, + SYSZ_INS_CDPT, + SYSZ_INS_CDR, + SYSZ_INS_CDS, + SYSZ_INS_CDSG, + SYSZ_INS_CDSTR, + SYSZ_INS_CDSY, + SYSZ_INS_CDTR, + SYSZ_INS_CDUTR, + SYSZ_INS_CDZT, + SYSZ_INS_CE, + SYSZ_INS_CEDTR, + SYSZ_INS_CEFBRA, + SYSZ_INS_CEFR, + SYSZ_INS_CEGBRA, + SYSZ_INS_CEGR, + SYSZ_INS_CER, + SYSZ_INS_CEXTR, + SYSZ_INS_CFC, + SYSZ_INS_CFDBRA, + SYSZ_INS_CFDR, + SYSZ_INS_CFDTR, + SYSZ_INS_CFEBRA, + SYSZ_INS_CFER, + SYSZ_INS_CFXBRA, + SYSZ_INS_CFXR, + SYSZ_INS_CFXTR, + SYSZ_INS_CGDBRA, + SYSZ_INS_CGDR, + SYSZ_INS_CGDTR, + SYSZ_INS_CGDTRA, + SYSZ_INS_CGEBRA, + SYSZ_INS_CGER, + SYSZ_INS_CGIB, + SYSZ_INS_CGIBE, + SYSZ_INS_CGIBH, + SYSZ_INS_CGIBHE, + SYSZ_INS_CGIBL, + SYSZ_INS_CGIBLE, + SYSZ_INS_CGIBLH, + SYSZ_INS_CGIBNE, + SYSZ_INS_CGIBNH, + SYSZ_INS_CGIBNHE, + SYSZ_INS_CGIBNL, + SYSZ_INS_CGIBNLE, + SYSZ_INS_CGIBNLH, + SYSZ_INS_CGIT, + SYSZ_INS_CGITE, + SYSZ_INS_CGITH, + SYSZ_INS_CGITHE, + SYSZ_INS_CGITL, + SYSZ_INS_CGITLE, + SYSZ_INS_CGITLH, + SYSZ_INS_CGITNE, + SYSZ_INS_CGITNH, + SYSZ_INS_CGITNHE, + SYSZ_INS_CGITNL, + SYSZ_INS_CGITNLE, + SYSZ_INS_CGITNLH, + SYSZ_INS_CGRB, + SYSZ_INS_CGRBE, + SYSZ_INS_CGRBH, + SYSZ_INS_CGRBHE, + SYSZ_INS_CGRBL, + SYSZ_INS_CGRBLE, + SYSZ_INS_CGRBLH, + SYSZ_INS_CGRBNE, + SYSZ_INS_CGRBNH, + SYSZ_INS_CGRBNHE, + SYSZ_INS_CGRBNL, + SYSZ_INS_CGRBNLE, + SYSZ_INS_CGRBNLH, + SYSZ_INS_CGRT, + SYSZ_INS_CGRTE, + SYSZ_INS_CGRTH, + SYSZ_INS_CGRTHE, + SYSZ_INS_CGRTL, + SYSZ_INS_CGRTLE, + SYSZ_INS_CGRTLH, + SYSZ_INS_CGRTNE, + SYSZ_INS_CGRTNH, + SYSZ_INS_CGRTNHE, + SYSZ_INS_CGRTNL, + SYSZ_INS_CGRTNLE, + SYSZ_INS_CGRTNLH, + SYSZ_INS_CGXBRA, + SYSZ_INS_CGXR, + SYSZ_INS_CGXTR, + SYSZ_INS_CGXTRA, + SYSZ_INS_CHHR, + SYSZ_INS_CHLR, + SYSZ_INS_CIB, + SYSZ_INS_CIBE, + SYSZ_INS_CIBH, + SYSZ_INS_CIBHE, + SYSZ_INS_CIBL, + SYSZ_INS_CIBLE, + SYSZ_INS_CIBLH, + SYSZ_INS_CIBNE, + SYSZ_INS_CIBNH, + SYSZ_INS_CIBNHE, + SYSZ_INS_CIBNL, + SYSZ_INS_CIBNLE, + SYSZ_INS_CIBNLH, + SYSZ_INS_CIT, + SYSZ_INS_CITE, + SYSZ_INS_CITH, + SYSZ_INS_CITHE, + SYSZ_INS_CITL, + SYSZ_INS_CITLE, + SYSZ_INS_CITLH, + SYSZ_INS_CITNE, + SYSZ_INS_CITNH, + SYSZ_INS_CITNHE, + SYSZ_INS_CITNL, + SYSZ_INS_CITNLE, + SYSZ_INS_CITNLH, + SYSZ_INS_CKSM, + SYSZ_INS_CLCL, + SYSZ_INS_CLCLE, + SYSZ_INS_CLCLU, + SYSZ_INS_CLFDTR, + SYSZ_INS_CLFIT, + SYSZ_INS_CLFITE, + SYSZ_INS_CLFITH, + SYSZ_INS_CLFITHE, + SYSZ_INS_CLFITL, + SYSZ_INS_CLFITLE, + SYSZ_INS_CLFITLH, + SYSZ_INS_CLFITNE, + SYSZ_INS_CLFITNH, + SYSZ_INS_CLFITNHE, + SYSZ_INS_CLFITNL, + SYSZ_INS_CLFITNLE, + SYSZ_INS_CLFITNLH, + SYSZ_INS_CLFXTR, + SYSZ_INS_CLGDTR, + SYSZ_INS_CLGIB, + SYSZ_INS_CLGIBE, + SYSZ_INS_CLGIBH, + SYSZ_INS_CLGIBHE, + SYSZ_INS_CLGIBL, + SYSZ_INS_CLGIBLE, + SYSZ_INS_CLGIBLH, + SYSZ_INS_CLGIBNE, + SYSZ_INS_CLGIBNH, + SYSZ_INS_CLGIBNHE, + SYSZ_INS_CLGIBNL, + SYSZ_INS_CLGIBNLE, + SYSZ_INS_CLGIBNLH, + SYSZ_INS_CLGIT, + SYSZ_INS_CLGITE, + SYSZ_INS_CLGITH, + SYSZ_INS_CLGITHE, + SYSZ_INS_CLGITL, + SYSZ_INS_CLGITLE, + SYSZ_INS_CLGITLH, + SYSZ_INS_CLGITNE, + SYSZ_INS_CLGITNH, + SYSZ_INS_CLGITNHE, + SYSZ_INS_CLGITNL, + SYSZ_INS_CLGITNLE, + SYSZ_INS_CLGITNLH, + SYSZ_INS_CLGRB, + SYSZ_INS_CLGRBE, + SYSZ_INS_CLGRBH, + SYSZ_INS_CLGRBHE, + SYSZ_INS_CLGRBL, + SYSZ_INS_CLGRBLE, + SYSZ_INS_CLGRBLH, + SYSZ_INS_CLGRBNE, + SYSZ_INS_CLGRBNH, + SYSZ_INS_CLGRBNHE, + SYSZ_INS_CLGRBNL, + SYSZ_INS_CLGRBNLE, + SYSZ_INS_CLGRBNLH, + SYSZ_INS_CLGRT, + SYSZ_INS_CLGRTE, + SYSZ_INS_CLGRTH, + SYSZ_INS_CLGRTHE, + SYSZ_INS_CLGRTL, + SYSZ_INS_CLGRTLE, + SYSZ_INS_CLGRTLH, + SYSZ_INS_CLGRTNE, + SYSZ_INS_CLGRTNH, + SYSZ_INS_CLGRTNHE, + SYSZ_INS_CLGRTNL, + SYSZ_INS_CLGRTNLE, + SYSZ_INS_CLGRTNLH, + SYSZ_INS_CLGT, + SYSZ_INS_CLGTE, + SYSZ_INS_CLGTH, + SYSZ_INS_CLGTHE, + SYSZ_INS_CLGTL, + SYSZ_INS_CLGTLE, + SYSZ_INS_CLGTLH, + SYSZ_INS_CLGTNE, + SYSZ_INS_CLGTNH, + SYSZ_INS_CLGTNHE, + SYSZ_INS_CLGTNL, + SYSZ_INS_CLGTNLE, + SYSZ_INS_CLGTNLH, + SYSZ_INS_CLGXTR, + SYSZ_INS_CLHHR, + SYSZ_INS_CLHLR, + SYSZ_INS_CLIB, + SYSZ_INS_CLIBE, + SYSZ_INS_CLIBH, + SYSZ_INS_CLIBHE, + SYSZ_INS_CLIBL, + SYSZ_INS_CLIBLE, + SYSZ_INS_CLIBLH, + SYSZ_INS_CLIBNE, + SYSZ_INS_CLIBNH, + SYSZ_INS_CLIBNHE, + SYSZ_INS_CLIBNL, + SYSZ_INS_CLIBNLE, + SYSZ_INS_CLIBNLH, + SYSZ_INS_CLM, + SYSZ_INS_CLMH, + SYSZ_INS_CLMY, + SYSZ_INS_CLRB, + SYSZ_INS_CLRBE, + SYSZ_INS_CLRBH, + SYSZ_INS_CLRBHE, + SYSZ_INS_CLRBL, + SYSZ_INS_CLRBLE, + SYSZ_INS_CLRBLH, + SYSZ_INS_CLRBNE, + SYSZ_INS_CLRBNH, + SYSZ_INS_CLRBNHE, + SYSZ_INS_CLRBNL, + SYSZ_INS_CLRBNLE, + SYSZ_INS_CLRBNLH, + SYSZ_INS_CLRT, + SYSZ_INS_CLRTE, + SYSZ_INS_CLRTH, + SYSZ_INS_CLRTHE, + SYSZ_INS_CLRTL, + SYSZ_INS_CLRTLE, + SYSZ_INS_CLRTLH, + SYSZ_INS_CLRTNE, + SYSZ_INS_CLRTNH, + SYSZ_INS_CLRTNHE, + SYSZ_INS_CLRTNL, + SYSZ_INS_CLRTNLE, + SYSZ_INS_CLRTNLH, + SYSZ_INS_CLT, + SYSZ_INS_CLTE, + SYSZ_INS_CLTH, + SYSZ_INS_CLTHE, + SYSZ_INS_CLTL, + SYSZ_INS_CLTLE, + SYSZ_INS_CLTLH, + SYSZ_INS_CLTNE, + SYSZ_INS_CLTNH, + SYSZ_INS_CLTNHE, + SYSZ_INS_CLTNL, + SYSZ_INS_CLTNLE, + SYSZ_INS_CLTNLH, + SYSZ_INS_CMPSC, + SYSZ_INS_CP, + SYSZ_INS_CPDT, + SYSZ_INS_CPXT, + SYSZ_INS_CPYA, + SYSZ_INS_CRB, + SYSZ_INS_CRBE, + SYSZ_INS_CRBH, + SYSZ_INS_CRBHE, + SYSZ_INS_CRBL, + SYSZ_INS_CRBLE, + SYSZ_INS_CRBLH, + SYSZ_INS_CRBNE, + SYSZ_INS_CRBNH, + SYSZ_INS_CRBNHE, + SYSZ_INS_CRBNL, + SYSZ_INS_CRBNLE, + SYSZ_INS_CRBNLH, + SYSZ_INS_CRDTE, + SYSZ_INS_CRT, + SYSZ_INS_CRTE, + SYSZ_INS_CRTH, + SYSZ_INS_CRTHE, + SYSZ_INS_CRTL, + SYSZ_INS_CRTLE, + SYSZ_INS_CRTLH, + SYSZ_INS_CRTNE, + SYSZ_INS_CRTNH, + SYSZ_INS_CRTNHE, + SYSZ_INS_CRTNL, + SYSZ_INS_CRTNLE, + SYSZ_INS_CRTNLH, + SYSZ_INS_CSCH, + SYSZ_INS_CSDTR, + SYSZ_INS_CSP, + SYSZ_INS_CSPG, + SYSZ_INS_CSST, + SYSZ_INS_CSXTR, + SYSZ_INS_CU12, + SYSZ_INS_CU14, + SYSZ_INS_CU21, + SYSZ_INS_CU24, + SYSZ_INS_CU41, + SYSZ_INS_CU42, + SYSZ_INS_CUDTR, + SYSZ_INS_CUSE, + SYSZ_INS_CUTFU, + SYSZ_INS_CUUTF, + SYSZ_INS_CUXTR, + SYSZ_INS_CVB, + SYSZ_INS_CVBG, + SYSZ_INS_CVBY, + SYSZ_INS_CVD, + SYSZ_INS_CVDG, + SYSZ_INS_CVDY, + SYSZ_INS_CXFBRA, + SYSZ_INS_CXFR, + SYSZ_INS_CXFTR, + SYSZ_INS_CXGBRA, + SYSZ_INS_CXGR, + SYSZ_INS_CXGTR, + SYSZ_INS_CXGTRA, + SYSZ_INS_CXLFTR, + SYSZ_INS_CXLGTR, + SYSZ_INS_CXPT, + SYSZ_INS_CXR, + SYSZ_INS_CXSTR, + SYSZ_INS_CXTR, + SYSZ_INS_CXUTR, + SYSZ_INS_CXZT, + SYSZ_INS_CZDT, + SYSZ_INS_CZXT, + SYSZ_INS_D, + SYSZ_INS_DD, + SYSZ_INS_DDR, + SYSZ_INS_DDTR, + SYSZ_INS_DDTRA, + SYSZ_INS_DE, + SYSZ_INS_DER, + SYSZ_INS_DIAG, + SYSZ_INS_DIDBR, + SYSZ_INS_DIEBR, + SYSZ_INS_DP, + SYSZ_INS_DR, + SYSZ_INS_DXR, + SYSZ_INS_DXTR, + SYSZ_INS_DXTRA, + SYSZ_INS_ECAG, + SYSZ_INS_ECCTR, + SYSZ_INS_ECPGA, + SYSZ_INS_ECTG, + SYSZ_INS_ED, + SYSZ_INS_EDMK, + SYSZ_INS_EEDTR, + SYSZ_INS_EEXTR, + SYSZ_INS_EFPC, + SYSZ_INS_EPAIR, + SYSZ_INS_EPAR, + SYSZ_INS_EPCTR, + SYSZ_INS_EPSW, + SYSZ_INS_EREG, + SYSZ_INS_EREGG, + SYSZ_INS_ESAIR, + SYSZ_INS_ESAR, + SYSZ_INS_ESDTR, + SYSZ_INS_ESEA, + SYSZ_INS_ESTA, + SYSZ_INS_ESXTR, + SYSZ_INS_ETND, + SYSZ_INS_EX, + SYSZ_INS_EXRL, + SYSZ_INS_FIDR, + SYSZ_INS_FIDTR, + SYSZ_INS_FIER, + SYSZ_INS_FIXR, + SYSZ_INS_FIXTR, + SYSZ_INS_HDR, + SYSZ_INS_HER, + SYSZ_INS_HSCH, + SYSZ_INS_IAC, + SYSZ_INS_ICM, + SYSZ_INS_ICMH, + SYSZ_INS_ICMY, + SYSZ_INS_IDTE, + SYSZ_INS_IEDTR, + SYSZ_INS_IEXTR, + SYSZ_INS_IPK, + SYSZ_INS_IPTE, + SYSZ_INS_IRBM, + SYSZ_INS_ISKE, + SYSZ_INS_IVSK, + SYSZ_INS_JGM, + SYSZ_INS_JGNM, + SYSZ_INS_JGNP, + SYSZ_INS_JGNZ, + SYSZ_INS_JGP, + SYSZ_INS_JGZ, + SYSZ_INS_JM, + SYSZ_INS_JNM, + SYSZ_INS_JNP, + SYSZ_INS_JNZ, + SYSZ_INS_JP, + SYSZ_INS_JZ, + SYSZ_INS_KDB, + SYSZ_INS_KDBR, + SYSZ_INS_KDTR, + SYSZ_INS_KEB, + SYSZ_INS_KEBR, + SYSZ_INS_KIMD, + SYSZ_INS_KLMD, + SYSZ_INS_KM, + SYSZ_INS_KMA, + SYSZ_INS_KMAC, + SYSZ_INS_KMC, + SYSZ_INS_KMCTR, + SYSZ_INS_KMF, + SYSZ_INS_KMO, + SYSZ_INS_KXBR, + SYSZ_INS_KXTR, + SYSZ_INS_LAE, + SYSZ_INS_LAEY, + SYSZ_INS_LAM, + SYSZ_INS_LAMY, + SYSZ_INS_LASP, + SYSZ_INS_LAT, + SYSZ_INS_LCBB, + SYSZ_INS_LCCTL, + SYSZ_INS_LCDFR, + SYSZ_INS_LCDR, + SYSZ_INS_LCER, + SYSZ_INS_LCTL, + SYSZ_INS_LCTLG, + SYSZ_INS_LCXR, + SYSZ_INS_LDE, + SYSZ_INS_LDER, + SYSZ_INS_LDETR, + SYSZ_INS_LDXR, + SYSZ_INS_LDXTR, + SYSZ_INS_LEDR, + SYSZ_INS_LEDTR, + SYSZ_INS_LEXR, + SYSZ_INS_LFAS, + SYSZ_INS_LFHAT, + SYSZ_INS_LFPC, + SYSZ_INS_LGAT, + SYSZ_INS_LGG, + SYSZ_INS_LGSC, + SYSZ_INS_LLGFAT, + SYSZ_INS_LLGFSG, + SYSZ_INS_LLGT, + SYSZ_INS_LLGTAT, + SYSZ_INS_LLGTR, + SYSZ_INS_LLZRGF, + SYSZ_INS_LM, + SYSZ_INS_LMD, + SYSZ_INS_LMH, + SYSZ_INS_LMY, + SYSZ_INS_LNDFR, + SYSZ_INS_LNDR, + SYSZ_INS_LNER, + SYSZ_INS_LNXR, + SYSZ_INS_LOCFH, + SYSZ_INS_LOCFHE, + SYSZ_INS_LOCFHH, + SYSZ_INS_LOCFHHE, + SYSZ_INS_LOCFHL, + SYSZ_INS_LOCFHLE, + SYSZ_INS_LOCFHLH, + SYSZ_INS_LOCFHM, + SYSZ_INS_LOCFHNE, + SYSZ_INS_LOCFHNH, + SYSZ_INS_LOCFHNHE, + SYSZ_INS_LOCFHNL, + SYSZ_INS_LOCFHNLE, + SYSZ_INS_LOCFHNLH, + SYSZ_INS_LOCFHNM, + SYSZ_INS_LOCFHNO, + SYSZ_INS_LOCFHNP, + SYSZ_INS_LOCFHNZ, + SYSZ_INS_LOCFHO, + SYSZ_INS_LOCFHP, + SYSZ_INS_LOCFHR, + SYSZ_INS_LOCFHRE, + SYSZ_INS_LOCFHRH, + SYSZ_INS_LOCFHRHE, + SYSZ_INS_LOCFHRL, + SYSZ_INS_LOCFHRLE, + SYSZ_INS_LOCFHRLH, + SYSZ_INS_LOCFHRM, + SYSZ_INS_LOCFHRNE, + SYSZ_INS_LOCFHRNH, + SYSZ_INS_LOCFHRNHE, + SYSZ_INS_LOCFHRNL, + SYSZ_INS_LOCFHRNLE, + SYSZ_INS_LOCFHRNLH, + SYSZ_INS_LOCFHRNM, + SYSZ_INS_LOCFHRNO, + SYSZ_INS_LOCFHRNP, + SYSZ_INS_LOCFHRNZ, + SYSZ_INS_LOCFHRO, + SYSZ_INS_LOCFHRP, + SYSZ_INS_LOCFHRZ, + SYSZ_INS_LOCFHZ, + SYSZ_INS_LOCGHI, + SYSZ_INS_LOCGHIE, + SYSZ_INS_LOCGHIH, + SYSZ_INS_LOCGHIHE, + SYSZ_INS_LOCGHIL, + SYSZ_INS_LOCGHILE, + SYSZ_INS_LOCGHILH, + SYSZ_INS_LOCGHIM, + SYSZ_INS_LOCGHINE, + SYSZ_INS_LOCGHINH, + SYSZ_INS_LOCGHINHE, + SYSZ_INS_LOCGHINL, + SYSZ_INS_LOCGHINLE, + SYSZ_INS_LOCGHINLH, + SYSZ_INS_LOCGHINM, + SYSZ_INS_LOCGHINO, + SYSZ_INS_LOCGHINP, + SYSZ_INS_LOCGHINZ, + SYSZ_INS_LOCGHIO, + SYSZ_INS_LOCGHIP, + SYSZ_INS_LOCGHIZ, + SYSZ_INS_LOCGM, + SYSZ_INS_LOCGNM, + SYSZ_INS_LOCGNP, + SYSZ_INS_LOCGNZ, + SYSZ_INS_LOCGP, + SYSZ_INS_LOCGRM, + SYSZ_INS_LOCGRNM, + SYSZ_INS_LOCGRNP, + SYSZ_INS_LOCGRNZ, + SYSZ_INS_LOCGRP, + SYSZ_INS_LOCGRZ, + SYSZ_INS_LOCGZ, + SYSZ_INS_LOCHHI, + SYSZ_INS_LOCHHIE, + SYSZ_INS_LOCHHIH, + SYSZ_INS_LOCHHIHE, + SYSZ_INS_LOCHHIL, + SYSZ_INS_LOCHHILE, + SYSZ_INS_LOCHHILH, + SYSZ_INS_LOCHHIM, + SYSZ_INS_LOCHHINE, + SYSZ_INS_LOCHHINH, + SYSZ_INS_LOCHHINHE, + SYSZ_INS_LOCHHINL, + SYSZ_INS_LOCHHINLE, + SYSZ_INS_LOCHHINLH, + SYSZ_INS_LOCHHINM, + SYSZ_INS_LOCHHINO, + SYSZ_INS_LOCHHINP, + SYSZ_INS_LOCHHINZ, + SYSZ_INS_LOCHHIO, + SYSZ_INS_LOCHHIP, + SYSZ_INS_LOCHHIZ, + SYSZ_INS_LOCHI, + SYSZ_INS_LOCHIE, + SYSZ_INS_LOCHIH, + SYSZ_INS_LOCHIHE, + SYSZ_INS_LOCHIL, + SYSZ_INS_LOCHILE, + SYSZ_INS_LOCHILH, + SYSZ_INS_LOCHIM, + SYSZ_INS_LOCHINE, + SYSZ_INS_LOCHINH, + SYSZ_INS_LOCHINHE, + SYSZ_INS_LOCHINL, + SYSZ_INS_LOCHINLE, + SYSZ_INS_LOCHINLH, + SYSZ_INS_LOCHINM, + SYSZ_INS_LOCHINO, + SYSZ_INS_LOCHINP, + SYSZ_INS_LOCHINZ, + SYSZ_INS_LOCHIO, + SYSZ_INS_LOCHIP, + SYSZ_INS_LOCHIZ, + SYSZ_INS_LOCM, + SYSZ_INS_LOCNM, + SYSZ_INS_LOCNP, + SYSZ_INS_LOCNZ, + SYSZ_INS_LOCP, + SYSZ_INS_LOCRM, + SYSZ_INS_LOCRNM, + SYSZ_INS_LOCRNP, + SYSZ_INS_LOCRNZ, + SYSZ_INS_LOCRP, + SYSZ_INS_LOCRZ, + SYSZ_INS_LOCZ, + SYSZ_INS_LPCTL, + SYSZ_INS_LPD, + SYSZ_INS_LPDFR, + SYSZ_INS_LPDG, + SYSZ_INS_LPDR, + SYSZ_INS_LPER, + SYSZ_INS_LPP, + SYSZ_INS_LPQ, + SYSZ_INS_LPSW, + SYSZ_INS_LPSWE, + SYSZ_INS_LPTEA, + SYSZ_INS_LPXR, + SYSZ_INS_LRA, + SYSZ_INS_LRAG, + SYSZ_INS_LRAY, + SYSZ_INS_LRDR, + SYSZ_INS_LRER, + SYSZ_INS_LRVH, + SYSZ_INS_LSCTL, + SYSZ_INS_LTDR, + SYSZ_INS_LTDTR, + SYSZ_INS_LTER, + SYSZ_INS_LTXR, + SYSZ_INS_LTXTR, + SYSZ_INS_LURA, + SYSZ_INS_LURAG, + SYSZ_INS_LXD, + SYSZ_INS_LXDR, + SYSZ_INS_LXDTR, + SYSZ_INS_LXE, + SYSZ_INS_LXER, + SYSZ_INS_LZRF, + SYSZ_INS_LZRG, + SYSZ_INS_M, + SYSZ_INS_MAD, + SYSZ_INS_MADR, + SYSZ_INS_MAE, + SYSZ_INS_MAER, + SYSZ_INS_MAY, + SYSZ_INS_MAYH, + SYSZ_INS_MAYHR, + SYSZ_INS_MAYL, + SYSZ_INS_MAYLR, + SYSZ_INS_MAYR, + SYSZ_INS_MC, + SYSZ_INS_MD, + SYSZ_INS_MDE, + SYSZ_INS_MDER, + SYSZ_INS_MDR, + SYSZ_INS_MDTR, + SYSZ_INS_MDTRA, + SYSZ_INS_ME, + SYSZ_INS_MEE, + SYSZ_INS_MEER, + SYSZ_INS_MER, + SYSZ_INS_MFY, + SYSZ_INS_MG, + SYSZ_INS_MGH, + SYSZ_INS_MGRK, + SYSZ_INS_ML, + SYSZ_INS_MLR, + SYSZ_INS_MP, + SYSZ_INS_MR, + SYSZ_INS_MSC, + SYSZ_INS_MSCH, + SYSZ_INS_MSD, + SYSZ_INS_MSDR, + SYSZ_INS_MSE, + SYSZ_INS_MSER, + SYSZ_INS_MSGC, + SYSZ_INS_MSGRKC, + SYSZ_INS_MSRKC, + SYSZ_INS_MSTA, + SYSZ_INS_MVCDK, + SYSZ_INS_MVCIN, + SYSZ_INS_MVCK, + SYSZ_INS_MVCL, + SYSZ_INS_MVCLE, + SYSZ_INS_MVCLU, + SYSZ_INS_MVCOS, + SYSZ_INS_MVCP, + SYSZ_INS_MVCS, + SYSZ_INS_MVCSK, + SYSZ_INS_MVN, + SYSZ_INS_MVO, + SYSZ_INS_MVPG, + SYSZ_INS_MVZ, + SYSZ_INS_MXD, + SYSZ_INS_MXDR, + SYSZ_INS_MXR, + SYSZ_INS_MXTR, + SYSZ_INS_MXTRA, + SYSZ_INS_MY, + SYSZ_INS_MYH, + SYSZ_INS_MYHR, + SYSZ_INS_MYL, + SYSZ_INS_MYLR, + SYSZ_INS_MYR, + SYSZ_INS_NIAI, + SYSZ_INS_NTSTG, + SYSZ_INS_PACK, + SYSZ_INS_PALB, + SYSZ_INS_PC, + SYSZ_INS_PCC, + SYSZ_INS_PCKMO, + SYSZ_INS_PFMF, + SYSZ_INS_PFPO, + SYSZ_INS_PGIN, + SYSZ_INS_PGOUT, + SYSZ_INS_PKA, + SYSZ_INS_PKU, + SYSZ_INS_PLO, + SYSZ_INS_POPCNT, + SYSZ_INS_PPA, + SYSZ_INS_PPNO, + SYSZ_INS_PR, + SYSZ_INS_PRNO, + SYSZ_INS_PT, + SYSZ_INS_PTF, + SYSZ_INS_PTFF, + SYSZ_INS_PTI, + SYSZ_INS_PTLB, + SYSZ_INS_QADTR, + SYSZ_INS_QAXTR, + SYSZ_INS_QCTRI, + SYSZ_INS_QSI, + SYSZ_INS_RCHP, + SYSZ_INS_RISBGN, + SYSZ_INS_RP, + SYSZ_INS_RRBE, + SYSZ_INS_RRBM, + SYSZ_INS_RRDTR, + SYSZ_INS_RRXTR, + SYSZ_INS_RSCH, + SYSZ_INS_SAC, + SYSZ_INS_SACF, + SYSZ_INS_SAL, + SYSZ_INS_SAM24, + SYSZ_INS_SAM31, + SYSZ_INS_SAM64, + SYSZ_INS_SAR, + SYSZ_INS_SCCTR, + SYSZ_INS_SCHM, + SYSZ_INS_SCK, + SYSZ_INS_SCKC, + SYSZ_INS_SCKPF, + SYSZ_INS_SD, + SYSZ_INS_SDR, + SYSZ_INS_SDTR, + SYSZ_INS_SDTRA, + SYSZ_INS_SE, + SYSZ_INS_SER, + SYSZ_INS_SFASR, + SYSZ_INS_SFPC, + SYSZ_INS_SGH, + SYSZ_INS_SHHHR, + SYSZ_INS_SHHLR, + SYSZ_INS_SIE, + SYSZ_INS_SIGA, + SYSZ_INS_SIGP, + SYSZ_INS_SLA, + SYSZ_INS_SLAG, + SYSZ_INS_SLAK, + SYSZ_INS_SLDA, + SYSZ_INS_SLDL, + SYSZ_INS_SLDT, + SYSZ_INS_SLHHHR, + SYSZ_INS_SLHHLR, + SYSZ_INS_SLXT, + SYSZ_INS_SP, + SYSZ_INS_SPCTR, + SYSZ_INS_SPKA, + SYSZ_INS_SPM, + SYSZ_INS_SPT, + SYSZ_INS_SPX, + SYSZ_INS_SQD, + SYSZ_INS_SQDR, + SYSZ_INS_SQE, + SYSZ_INS_SQER, + SYSZ_INS_SQXR, + SYSZ_INS_SRDA, + SYSZ_INS_SRDL, + SYSZ_INS_SRDT, + SYSZ_INS_SRNM, + SYSZ_INS_SRNMB, + SYSZ_INS_SRNMT, + SYSZ_INS_SRP, + SYSZ_INS_SRSTU, + SYSZ_INS_SRXT, + SYSZ_INS_SSAIR, + SYSZ_INS_SSAR, + SYSZ_INS_SSCH, + SYSZ_INS_SSKE, + SYSZ_INS_SSM, + SYSZ_INS_STAM, + SYSZ_INS_STAMY, + SYSZ_INS_STAP, + SYSZ_INS_STCK, + SYSZ_INS_STCKC, + SYSZ_INS_STCKE, + SYSZ_INS_STCKF, + SYSZ_INS_STCM, + SYSZ_INS_STCMH, + SYSZ_INS_STCMY, + SYSZ_INS_STCPS, + SYSZ_INS_STCRW, + SYSZ_INS_STCTG, + SYSZ_INS_STCTL, + SYSZ_INS_STFL, + SYSZ_INS_STFLE, + SYSZ_INS_STFPC, + SYSZ_INS_STGSC, + SYSZ_INS_STIDP, + SYSZ_INS_STM, + SYSZ_INS_STMH, + SYSZ_INS_STMY, + SYSZ_INS_STNSM, + SYSZ_INS_STOCFH, + SYSZ_INS_STOCFHE, + SYSZ_INS_STOCFHH, + SYSZ_INS_STOCFHHE, + SYSZ_INS_STOCFHL, + SYSZ_INS_STOCFHLE, + SYSZ_INS_STOCFHLH, + SYSZ_INS_STOCFHM, + SYSZ_INS_STOCFHNE, + SYSZ_INS_STOCFHNH, + SYSZ_INS_STOCFHNHE, + SYSZ_INS_STOCFHNL, + SYSZ_INS_STOCFHNLE, + SYSZ_INS_STOCFHNLH, + SYSZ_INS_STOCFHNM, + SYSZ_INS_STOCFHNO, + SYSZ_INS_STOCFHNP, + SYSZ_INS_STOCFHNZ, + SYSZ_INS_STOCFHO, + SYSZ_INS_STOCFHP, + SYSZ_INS_STOCFHZ, + SYSZ_INS_STOCGM, + SYSZ_INS_STOCGNM, + SYSZ_INS_STOCGNP, + SYSZ_INS_STOCGNZ, + SYSZ_INS_STOCGP, + SYSZ_INS_STOCGZ, + SYSZ_INS_STOCM, + SYSZ_INS_STOCNM, + SYSZ_INS_STOCNP, + SYSZ_INS_STOCNZ, + SYSZ_INS_STOCP, + SYSZ_INS_STOCZ, + SYSZ_INS_STOSM, + SYSZ_INS_STPQ, + SYSZ_INS_STPT, + SYSZ_INS_STPX, + SYSZ_INS_STRAG, + SYSZ_INS_STRVH, + SYSZ_INS_STSCH, + SYSZ_INS_STSI, + SYSZ_INS_STURA, + SYSZ_INS_STURG, + SYSZ_INS_SU, + SYSZ_INS_SUR, + SYSZ_INS_SVC, + SYSZ_INS_SW, + SYSZ_INS_SWR, + SYSZ_INS_SXR, + SYSZ_INS_SXTR, + SYSZ_INS_SXTRA, + SYSZ_INS_TABORT, + SYSZ_INS_TAM, + SYSZ_INS_TAR, + SYSZ_INS_TB, + SYSZ_INS_TBDR, + SYSZ_INS_TBEDR, + SYSZ_INS_TBEGIN, + SYSZ_INS_TBEGINC, + SYSZ_INS_TCDB, + SYSZ_INS_TCEB, + SYSZ_INS_TCXB, + SYSZ_INS_TDCDT, + SYSZ_INS_TDCET, + SYSZ_INS_TDCXT, + SYSZ_INS_TDGDT, + SYSZ_INS_TDGET, + SYSZ_INS_TDGXT, + SYSZ_INS_TEND, + SYSZ_INS_THDER, + SYSZ_INS_THDR, + SYSZ_INS_TP, + SYSZ_INS_TPI, + SYSZ_INS_TPROT, + SYSZ_INS_TR, + SYSZ_INS_TRACE, + SYSZ_INS_TRACG, + SYSZ_INS_TRAP2, + SYSZ_INS_TRAP4, + SYSZ_INS_TRE, + SYSZ_INS_TROO, + SYSZ_INS_TROT, + SYSZ_INS_TRT, + SYSZ_INS_TRTE, + SYSZ_INS_TRTO, + SYSZ_INS_TRTR, + SYSZ_INS_TRTRE, + SYSZ_INS_TRTT, + SYSZ_INS_TS, + SYSZ_INS_TSCH, + SYSZ_INS_UNPK, + SYSZ_INS_UNPKA, + SYSZ_INS_UNPKU, + SYSZ_INS_UPT, + SYSZ_INS_VA, + SYSZ_INS_VAB, + SYSZ_INS_VAC, + SYSZ_INS_VACC, + SYSZ_INS_VACCB, + SYSZ_INS_VACCC, + SYSZ_INS_VACCCQ, + SYSZ_INS_VACCF, + SYSZ_INS_VACCG, + SYSZ_INS_VACCH, + SYSZ_INS_VACCQ, + SYSZ_INS_VACQ, + SYSZ_INS_VAF, + SYSZ_INS_VAG, + SYSZ_INS_VAH, + SYSZ_INS_VAP, + SYSZ_INS_VAQ, + SYSZ_INS_VAVG, + SYSZ_INS_VAVGB, + SYSZ_INS_VAVGF, + SYSZ_INS_VAVGG, + SYSZ_INS_VAVGH, + SYSZ_INS_VAVGL, + SYSZ_INS_VAVGLB, + SYSZ_INS_VAVGLF, + SYSZ_INS_VAVGLG, + SYSZ_INS_VAVGLH, + SYSZ_INS_VBPERM, + SYSZ_INS_VCDG, + SYSZ_INS_VCDGB, + SYSZ_INS_VCDLG, + SYSZ_INS_VCDLGB, + SYSZ_INS_VCEQ, + SYSZ_INS_VCEQB, + SYSZ_INS_VCEQBS, + SYSZ_INS_VCEQF, + SYSZ_INS_VCEQFS, + SYSZ_INS_VCEQG, + SYSZ_INS_VCEQGS, + SYSZ_INS_VCEQH, + SYSZ_INS_VCEQHS, + SYSZ_INS_VCGD, + SYSZ_INS_VCGDB, + SYSZ_INS_VCH, + SYSZ_INS_VCHB, + SYSZ_INS_VCHBS, + SYSZ_INS_VCHF, + SYSZ_INS_VCHFS, + SYSZ_INS_VCHG, + SYSZ_INS_VCHGS, + SYSZ_INS_VCHH, + SYSZ_INS_VCHHS, + SYSZ_INS_VCHL, + SYSZ_INS_VCHLB, + SYSZ_INS_VCHLBS, + SYSZ_INS_VCHLF, + SYSZ_INS_VCHLFS, + SYSZ_INS_VCHLG, + SYSZ_INS_VCHLGS, + SYSZ_INS_VCHLH, + SYSZ_INS_VCHLHS, + SYSZ_INS_VCKSM, + SYSZ_INS_VCLGD, + SYSZ_INS_VCLGDB, + SYSZ_INS_VCLZ, + SYSZ_INS_VCLZB, + SYSZ_INS_VCLZF, + SYSZ_INS_VCLZG, + SYSZ_INS_VCLZH, + SYSZ_INS_VCP, + SYSZ_INS_VCTZ, + SYSZ_INS_VCTZB, + SYSZ_INS_VCTZF, + SYSZ_INS_VCTZG, + SYSZ_INS_VCTZH, + SYSZ_INS_VCVB, + SYSZ_INS_VCVBG, + SYSZ_INS_VCVD, + SYSZ_INS_VCVDG, + SYSZ_INS_VDP, + SYSZ_INS_VEC, + SYSZ_INS_VECB, + SYSZ_INS_VECF, + SYSZ_INS_VECG, + SYSZ_INS_VECH, + SYSZ_INS_VECL, + SYSZ_INS_VECLB, + SYSZ_INS_VECLF, + SYSZ_INS_VECLG, + SYSZ_INS_VECLH, + SYSZ_INS_VERIM, + SYSZ_INS_VERIMB, + SYSZ_INS_VERIMF, + SYSZ_INS_VERIMG, + SYSZ_INS_VERIMH, + SYSZ_INS_VERLL, + SYSZ_INS_VERLLB, + SYSZ_INS_VERLLF, + SYSZ_INS_VERLLG, + SYSZ_INS_VERLLH, + SYSZ_INS_VERLLV, + SYSZ_INS_VERLLVB, + SYSZ_INS_VERLLVF, + SYSZ_INS_VERLLVG, + SYSZ_INS_VERLLVH, + SYSZ_INS_VESL, + SYSZ_INS_VESLB, + SYSZ_INS_VESLF, + SYSZ_INS_VESLG, + SYSZ_INS_VESLH, + SYSZ_INS_VESLV, + SYSZ_INS_VESLVB, + SYSZ_INS_VESLVF, + SYSZ_INS_VESLVG, + SYSZ_INS_VESLVH, + SYSZ_INS_VESRA, + SYSZ_INS_VESRAB, + SYSZ_INS_VESRAF, + SYSZ_INS_VESRAG, + SYSZ_INS_VESRAH, + SYSZ_INS_VESRAV, + SYSZ_INS_VESRAVB, + SYSZ_INS_VESRAVF, + SYSZ_INS_VESRAVG, + SYSZ_INS_VESRAVH, + SYSZ_INS_VESRL, + SYSZ_INS_VESRLB, + SYSZ_INS_VESRLF, + SYSZ_INS_VESRLG, + SYSZ_INS_VESRLH, + SYSZ_INS_VESRLV, + SYSZ_INS_VESRLVB, + SYSZ_INS_VESRLVF, + SYSZ_INS_VESRLVG, + SYSZ_INS_VESRLVH, + SYSZ_INS_VFA, + SYSZ_INS_VFADB, + SYSZ_INS_VFAE, + SYSZ_INS_VFAEB, + SYSZ_INS_VFAEBS, + SYSZ_INS_VFAEF, + SYSZ_INS_VFAEFS, + SYSZ_INS_VFAEH, + SYSZ_INS_VFAEHS, + SYSZ_INS_VFAEZB, + SYSZ_INS_VFAEZBS, + SYSZ_INS_VFAEZF, + SYSZ_INS_VFAEZFS, + SYSZ_INS_VFAEZH, + SYSZ_INS_VFAEZHS, + SYSZ_INS_VFASB, + SYSZ_INS_VFCE, + SYSZ_INS_VFCEDB, + SYSZ_INS_VFCEDBS, + SYSZ_INS_VFCESB, + SYSZ_INS_VFCESBS, + SYSZ_INS_VFCH, + SYSZ_INS_VFCHDB, + SYSZ_INS_VFCHDBS, + SYSZ_INS_VFCHE, + SYSZ_INS_VFCHEDB, + SYSZ_INS_VFCHEDBS, + SYSZ_INS_VFCHESB, + SYSZ_INS_VFCHESBS, + SYSZ_INS_VFCHSB, + SYSZ_INS_VFCHSBS, + SYSZ_INS_VFD, + SYSZ_INS_VFDDB, + SYSZ_INS_VFDSB, + SYSZ_INS_VFEE, + SYSZ_INS_VFEEB, + SYSZ_INS_VFEEBS, + SYSZ_INS_VFEEF, + SYSZ_INS_VFEEFS, + SYSZ_INS_VFEEH, + SYSZ_INS_VFEEHS, + SYSZ_INS_VFEEZB, + SYSZ_INS_VFEEZBS, + SYSZ_INS_VFEEZF, + SYSZ_INS_VFEEZFS, + SYSZ_INS_VFEEZH, + SYSZ_INS_VFEEZHS, + SYSZ_INS_VFENE, + SYSZ_INS_VFENEB, + SYSZ_INS_VFENEBS, + SYSZ_INS_VFENEF, + SYSZ_INS_VFENEFS, + SYSZ_INS_VFENEH, + SYSZ_INS_VFENEHS, + SYSZ_INS_VFENEZB, + SYSZ_INS_VFENEZBS, + SYSZ_INS_VFENEZF, + SYSZ_INS_VFENEZFS, + SYSZ_INS_VFENEZH, + SYSZ_INS_VFENEZHS, + SYSZ_INS_VFI, + SYSZ_INS_VFIDB, + SYSZ_INS_VFISB, + SYSZ_INS_VFKEDB, + SYSZ_INS_VFKEDBS, + SYSZ_INS_VFKESB, + SYSZ_INS_VFKESBS, + SYSZ_INS_VFKHDB, + SYSZ_INS_VFKHDBS, + SYSZ_INS_VFKHEDB, + SYSZ_INS_VFKHEDBS, + SYSZ_INS_VFKHESB, + SYSZ_INS_VFKHESBS, + SYSZ_INS_VFKHSB, + SYSZ_INS_VFKHSBS, + SYSZ_INS_VFLCDB, + SYSZ_INS_VFLCSB, + SYSZ_INS_VFLL, + SYSZ_INS_VFLLS, + SYSZ_INS_VFLNDB, + SYSZ_INS_VFLNSB, + SYSZ_INS_VFLPDB, + SYSZ_INS_VFLPSB, + SYSZ_INS_VFLR, + SYSZ_INS_VFLRD, + SYSZ_INS_VFM, + SYSZ_INS_VFMA, + SYSZ_INS_VFMADB, + SYSZ_INS_VFMASB, + SYSZ_INS_VFMAX, + SYSZ_INS_VFMAXDB, + SYSZ_INS_VFMAXSB, + SYSZ_INS_VFMDB, + SYSZ_INS_VFMIN, + SYSZ_INS_VFMINDB, + SYSZ_INS_VFMINSB, + SYSZ_INS_VFMS, + SYSZ_INS_VFMSB, + SYSZ_INS_VFMSDB, + SYSZ_INS_VFMSSB, + SYSZ_INS_VFNMA, + SYSZ_INS_VFNMADB, + SYSZ_INS_VFNMASB, + SYSZ_INS_VFNMS, + SYSZ_INS_VFNMSDB, + SYSZ_INS_VFNMSSB, + SYSZ_INS_VFPSO, + SYSZ_INS_VFPSODB, + SYSZ_INS_VFPSOSB, + SYSZ_INS_VFS, + SYSZ_INS_VFSDB, + SYSZ_INS_VFSQ, + SYSZ_INS_VFSQDB, + SYSZ_INS_VFSQSB, + SYSZ_INS_VFSSB, + SYSZ_INS_VFTCI, + SYSZ_INS_VFTCIDB, + SYSZ_INS_VFTCISB, + SYSZ_INS_VGBM, + SYSZ_INS_VGEF, + SYSZ_INS_VGEG, + SYSZ_INS_VGFM, + SYSZ_INS_VGFMA, + SYSZ_INS_VGFMAB, + SYSZ_INS_VGFMAF, + SYSZ_INS_VGFMAG, + SYSZ_INS_VGFMAH, + SYSZ_INS_VGFMB, + SYSZ_INS_VGFMF, + SYSZ_INS_VGFMG, + SYSZ_INS_VGFMH, + SYSZ_INS_VGM, + SYSZ_INS_VGMB, + SYSZ_INS_VGMF, + SYSZ_INS_VGMG, + SYSZ_INS_VGMH, + SYSZ_INS_VISTR, + SYSZ_INS_VISTRB, + SYSZ_INS_VISTRBS, + SYSZ_INS_VISTRF, + SYSZ_INS_VISTRFS, + SYSZ_INS_VISTRH, + SYSZ_INS_VISTRHS, + SYSZ_INS_VL, + SYSZ_INS_VLBB, + SYSZ_INS_VLC, + SYSZ_INS_VLCB, + SYSZ_INS_VLCF, + SYSZ_INS_VLCG, + SYSZ_INS_VLCH, + SYSZ_INS_VLDE, + SYSZ_INS_VLDEB, + SYSZ_INS_VLEB, + SYSZ_INS_VLED, + SYSZ_INS_VLEDB, + SYSZ_INS_VLEF, + SYSZ_INS_VLEG, + SYSZ_INS_VLEH, + SYSZ_INS_VLEIB, + SYSZ_INS_VLEIF, + SYSZ_INS_VLEIG, + SYSZ_INS_VLEIH, + SYSZ_INS_VLGV, + SYSZ_INS_VLGVB, + SYSZ_INS_VLGVF, + SYSZ_INS_VLGVG, + SYSZ_INS_VLGVH, + SYSZ_INS_VLIP, + SYSZ_INS_VLL, + SYSZ_INS_VLLEZ, + SYSZ_INS_VLLEZB, + SYSZ_INS_VLLEZF, + SYSZ_INS_VLLEZG, + SYSZ_INS_VLLEZH, + SYSZ_INS_VLLEZLF, + SYSZ_INS_VLM, + SYSZ_INS_VLP, + SYSZ_INS_VLPB, + SYSZ_INS_VLPF, + SYSZ_INS_VLPG, + SYSZ_INS_VLPH, + SYSZ_INS_VLR, + SYSZ_INS_VLREP, + SYSZ_INS_VLREPB, + SYSZ_INS_VLREPF, + SYSZ_INS_VLREPG, + SYSZ_INS_VLREPH, + SYSZ_INS_VLRL, + SYSZ_INS_VLRLR, + SYSZ_INS_VLVG, + SYSZ_INS_VLVGB, + SYSZ_INS_VLVGF, + SYSZ_INS_VLVGG, + SYSZ_INS_VLVGH, + SYSZ_INS_VLVGP, + SYSZ_INS_VMAE, + SYSZ_INS_VMAEB, + SYSZ_INS_VMAEF, + SYSZ_INS_VMAEH, + SYSZ_INS_VMAH, + SYSZ_INS_VMAHB, + SYSZ_INS_VMAHF, + SYSZ_INS_VMAHH, + SYSZ_INS_VMAL, + SYSZ_INS_VMALB, + SYSZ_INS_VMALE, + SYSZ_INS_VMALEB, + SYSZ_INS_VMALEF, + SYSZ_INS_VMALEH, + SYSZ_INS_VMALF, + SYSZ_INS_VMALH, + SYSZ_INS_VMALHB, + SYSZ_INS_VMALHF, + SYSZ_INS_VMALHH, + SYSZ_INS_VMALHW, + SYSZ_INS_VMALO, + SYSZ_INS_VMALOB, + SYSZ_INS_VMALOF, + SYSZ_INS_VMALOH, + SYSZ_INS_VMAO, + SYSZ_INS_VMAOB, + SYSZ_INS_VMAOF, + SYSZ_INS_VMAOH, + SYSZ_INS_VME, + SYSZ_INS_VMEB, + SYSZ_INS_VMEF, + SYSZ_INS_VMEH, + SYSZ_INS_VMH, + SYSZ_INS_VMHB, + SYSZ_INS_VMHF, + SYSZ_INS_VMHH, + SYSZ_INS_VML, + SYSZ_INS_VMLB, + SYSZ_INS_VMLE, + SYSZ_INS_VMLEB, + SYSZ_INS_VMLEF, + SYSZ_INS_VMLEH, + SYSZ_INS_VMLF, + SYSZ_INS_VMLH, + SYSZ_INS_VMLHB, + SYSZ_INS_VMLHF, + SYSZ_INS_VMLHH, + SYSZ_INS_VMLHW, + SYSZ_INS_VMLO, + SYSZ_INS_VMLOB, + SYSZ_INS_VMLOF, + SYSZ_INS_VMLOH, + SYSZ_INS_VMN, + SYSZ_INS_VMNB, + SYSZ_INS_VMNF, + SYSZ_INS_VMNG, + SYSZ_INS_VMNH, + SYSZ_INS_VMNL, + SYSZ_INS_VMNLB, + SYSZ_INS_VMNLF, + SYSZ_INS_VMNLG, + SYSZ_INS_VMNLH, + SYSZ_INS_VMO, + SYSZ_INS_VMOB, + SYSZ_INS_VMOF, + SYSZ_INS_VMOH, + SYSZ_INS_VMP, + SYSZ_INS_VMRH, + SYSZ_INS_VMRHB, + SYSZ_INS_VMRHF, + SYSZ_INS_VMRHG, + SYSZ_INS_VMRHH, + SYSZ_INS_VMRL, + SYSZ_INS_VMRLB, + SYSZ_INS_VMRLF, + SYSZ_INS_VMRLG, + SYSZ_INS_VMRLH, + SYSZ_INS_VMSL, + SYSZ_INS_VMSLG, + SYSZ_INS_VMSP, + SYSZ_INS_VMX, + SYSZ_INS_VMXB, + SYSZ_INS_VMXF, + SYSZ_INS_VMXG, + SYSZ_INS_VMXH, + SYSZ_INS_VMXL, + SYSZ_INS_VMXLB, + SYSZ_INS_VMXLF, + SYSZ_INS_VMXLG, + SYSZ_INS_VMXLH, + SYSZ_INS_VN, + SYSZ_INS_VNC, + SYSZ_INS_VNN, + SYSZ_INS_VNO, + SYSZ_INS_VNX, + SYSZ_INS_VO, + SYSZ_INS_VOC, + SYSZ_INS_VONE, + SYSZ_INS_VPDI, + SYSZ_INS_VPERM, + SYSZ_INS_VPK, + SYSZ_INS_VPKF, + SYSZ_INS_VPKG, + SYSZ_INS_VPKH, + SYSZ_INS_VPKLS, + SYSZ_INS_VPKLSF, + SYSZ_INS_VPKLSFS, + SYSZ_INS_VPKLSG, + SYSZ_INS_VPKLSGS, + SYSZ_INS_VPKLSH, + SYSZ_INS_VPKLSHS, + SYSZ_INS_VPKS, + SYSZ_INS_VPKSF, + SYSZ_INS_VPKSFS, + SYSZ_INS_VPKSG, + SYSZ_INS_VPKSGS, + SYSZ_INS_VPKSH, + SYSZ_INS_VPKSHS, + SYSZ_INS_VPKZ, + SYSZ_INS_VPOPCT, + SYSZ_INS_VPOPCTB, + SYSZ_INS_VPOPCTF, + SYSZ_INS_VPOPCTG, + SYSZ_INS_VPOPCTH, + SYSZ_INS_VPSOP, + SYSZ_INS_VREP, + SYSZ_INS_VREPB, + SYSZ_INS_VREPF, + SYSZ_INS_VREPG, + SYSZ_INS_VREPH, + SYSZ_INS_VREPI, + SYSZ_INS_VREPIB, + SYSZ_INS_VREPIF, + SYSZ_INS_VREPIG, + SYSZ_INS_VREPIH, + SYSZ_INS_VRP, + SYSZ_INS_VS, + SYSZ_INS_VSB, + SYSZ_INS_VSBCBI, + SYSZ_INS_VSBCBIQ, + SYSZ_INS_VSBI, + SYSZ_INS_VSBIQ, + SYSZ_INS_VSCBI, + SYSZ_INS_VSCBIB, + SYSZ_INS_VSCBIF, + SYSZ_INS_VSCBIG, + SYSZ_INS_VSCBIH, + SYSZ_INS_VSCBIQ, + SYSZ_INS_VSCEF, + SYSZ_INS_VSCEG, + SYSZ_INS_VSDP, + SYSZ_INS_VSEG, + SYSZ_INS_VSEGB, + SYSZ_INS_VSEGF, + SYSZ_INS_VSEGH, + SYSZ_INS_VSEL, + SYSZ_INS_VSF, + SYSZ_INS_VSG, + SYSZ_INS_VSH, + SYSZ_INS_VSL, + SYSZ_INS_VSLB, + SYSZ_INS_VSLDB, + SYSZ_INS_VSP, + SYSZ_INS_VSQ, + SYSZ_INS_VSRA, + SYSZ_INS_VSRAB, + SYSZ_INS_VSRL, + SYSZ_INS_VSRLB, + SYSZ_INS_VSRP, + SYSZ_INS_VST, + SYSZ_INS_VSTEB, + SYSZ_INS_VSTEF, + SYSZ_INS_VSTEG, + SYSZ_INS_VSTEH, + SYSZ_INS_VSTL, + SYSZ_INS_VSTM, + SYSZ_INS_VSTRC, + SYSZ_INS_VSTRCB, + SYSZ_INS_VSTRCBS, + SYSZ_INS_VSTRCF, + SYSZ_INS_VSTRCFS, + SYSZ_INS_VSTRCH, + SYSZ_INS_VSTRCHS, + SYSZ_INS_VSTRCZB, + SYSZ_INS_VSTRCZBS, + SYSZ_INS_VSTRCZF, + SYSZ_INS_VSTRCZFS, + SYSZ_INS_VSTRCZH, + SYSZ_INS_VSTRCZHS, + SYSZ_INS_VSTRL, + SYSZ_INS_VSTRLR, + SYSZ_INS_VSUM, + SYSZ_INS_VSUMB, + SYSZ_INS_VSUMG, + SYSZ_INS_VSUMGF, + SYSZ_INS_VSUMGH, + SYSZ_INS_VSUMH, + SYSZ_INS_VSUMQ, + SYSZ_INS_VSUMQF, + SYSZ_INS_VSUMQG, + SYSZ_INS_VTM, + SYSZ_INS_VTP, + SYSZ_INS_VUPH, + SYSZ_INS_VUPHB, + SYSZ_INS_VUPHF, + SYSZ_INS_VUPHH, + SYSZ_INS_VUPKZ, + SYSZ_INS_VUPL, + SYSZ_INS_VUPLB, + SYSZ_INS_VUPLF, + SYSZ_INS_VUPLH, + SYSZ_INS_VUPLHB, + SYSZ_INS_VUPLHF, + SYSZ_INS_VUPLHH, + SYSZ_INS_VUPLHW, + SYSZ_INS_VUPLL, + SYSZ_INS_VUPLLB, + SYSZ_INS_VUPLLF, + SYSZ_INS_VUPLLH, + SYSZ_INS_VX, + SYSZ_INS_VZERO, + SYSZ_INS_WCDGB, + SYSZ_INS_WCDLGB, + SYSZ_INS_WCGDB, + SYSZ_INS_WCLGDB, + SYSZ_INS_WFADB, + SYSZ_INS_WFASB, + SYSZ_INS_WFAXB, + SYSZ_INS_WFC, + SYSZ_INS_WFCDB, + SYSZ_INS_WFCEDB, + SYSZ_INS_WFCEDBS, + SYSZ_INS_WFCESB, + SYSZ_INS_WFCESBS, + SYSZ_INS_WFCEXB, + SYSZ_INS_WFCEXBS, + SYSZ_INS_WFCHDB, + SYSZ_INS_WFCHDBS, + SYSZ_INS_WFCHEDB, + SYSZ_INS_WFCHEDBS, + SYSZ_INS_WFCHESB, + SYSZ_INS_WFCHESBS, + SYSZ_INS_WFCHEXB, + SYSZ_INS_WFCHEXBS, + SYSZ_INS_WFCHSB, + SYSZ_INS_WFCHSBS, + SYSZ_INS_WFCHXB, + SYSZ_INS_WFCHXBS, + SYSZ_INS_WFCSB, + SYSZ_INS_WFCXB, + SYSZ_INS_WFDDB, + SYSZ_INS_WFDSB, + SYSZ_INS_WFDXB, + SYSZ_INS_WFIDB, + SYSZ_INS_WFISB, + SYSZ_INS_WFIXB, + SYSZ_INS_WFK, + SYSZ_INS_WFKDB, + SYSZ_INS_WFKEDB, + SYSZ_INS_WFKEDBS, + SYSZ_INS_WFKESB, + SYSZ_INS_WFKESBS, + SYSZ_INS_WFKEXB, + SYSZ_INS_WFKEXBS, + SYSZ_INS_WFKHDB, + SYSZ_INS_WFKHDBS, + SYSZ_INS_WFKHEDB, + SYSZ_INS_WFKHEDBS, + SYSZ_INS_WFKHESB, + SYSZ_INS_WFKHESBS, + SYSZ_INS_WFKHEXB, + SYSZ_INS_WFKHEXBS, + SYSZ_INS_WFKHSB, + SYSZ_INS_WFKHSBS, + SYSZ_INS_WFKHXB, + SYSZ_INS_WFKHXBS, + SYSZ_INS_WFKSB, + SYSZ_INS_WFKXB, + SYSZ_INS_WFLCDB, + SYSZ_INS_WFLCSB, + SYSZ_INS_WFLCXB, + SYSZ_INS_WFLLD, + SYSZ_INS_WFLLS, + SYSZ_INS_WFLNDB, + SYSZ_INS_WFLNSB, + SYSZ_INS_WFLNXB, + SYSZ_INS_WFLPDB, + SYSZ_INS_WFLPSB, + SYSZ_INS_WFLPXB, + SYSZ_INS_WFLRD, + SYSZ_INS_WFLRX, + SYSZ_INS_WFMADB, + SYSZ_INS_WFMASB, + SYSZ_INS_WFMAXB, + SYSZ_INS_WFMAXDB, + SYSZ_INS_WFMAXSB, + SYSZ_INS_WFMAXXB, + SYSZ_INS_WFMDB, + SYSZ_INS_WFMINDB, + SYSZ_INS_WFMINSB, + SYSZ_INS_WFMINXB, + SYSZ_INS_WFMSB, + SYSZ_INS_WFMSDB, + SYSZ_INS_WFMSSB, + SYSZ_INS_WFMSXB, + SYSZ_INS_WFMXB, + SYSZ_INS_WFNMADB, + SYSZ_INS_WFNMASB, + SYSZ_INS_WFNMAXB, + SYSZ_INS_WFNMSDB, + SYSZ_INS_WFNMSSB, + SYSZ_INS_WFNMSXB, + SYSZ_INS_WFPSODB, + SYSZ_INS_WFPSOSB, + SYSZ_INS_WFPSOXB, + SYSZ_INS_WFSDB, + SYSZ_INS_WFSQDB, + SYSZ_INS_WFSQSB, + SYSZ_INS_WFSQXB, + SYSZ_INS_WFSSB, + SYSZ_INS_WFSXB, + SYSZ_INS_WFTCIDB, + SYSZ_INS_WFTCISB, + SYSZ_INS_WFTCIXB, + SYSZ_INS_WLDEB, + SYSZ_INS_WLEDB, + SYSZ_INS_XSCH, + SYSZ_INS_ZAP, + + SYSZ_INS_ENDING, // <-- mark the end of the list of instructions +} sysz_insn; + +/// Group of SystemZ instructions +typedef enum sysz_insn_group { + SYSZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + SYSZ_GRP_JUMP, ///< = CS_GRP_JUMP + + // Architecture-specific groups + SYSZ_GRP_DISTINCTOPS = 128, + SYSZ_GRP_FPEXTENSION, + SYSZ_GRP_HIGHWORD, + SYSZ_GRP_INTERLOCKEDACCESS1, + SYSZ_GRP_LOADSTOREONCOND, + SYSZ_GRP_DFPPACKEDCONVERSION, + SYSZ_GRP_DFPZONEDCONVERSION, + SYSZ_GRP_ENHANCEDDAT2, + SYSZ_GRP_EXECUTIONHINT, + SYSZ_GRP_GUARDEDSTORAGE, + SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, + SYSZ_GRP_LOADANDTRAP, + SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, + SYSZ_GRP_LOADSTOREONCOND2, + SYSZ_GRP_MESSAGESECURITYASSIST3, + SYSZ_GRP_MESSAGESECURITYASSIST4, + SYSZ_GRP_MESSAGESECURITYASSIST5, + SYSZ_GRP_MESSAGESECURITYASSIST7, + SYSZ_GRP_MESSAGESECURITYASSIST8, + SYSZ_GRP_MISCELLANEOUSEXTENSIONS, + SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, + SYSZ_GRP_NOVECTOR, + SYSZ_GRP_POPULATIONCOUNT, + SYSZ_GRP_PROCESSORASSIST, + SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, + SYSZ_GRP_TRANSACTIONALEXECUTION, + SYSZ_GRP_VECTOR, + SYSZ_GRP_VECTORENHANCEMENTS1, + SYSZ_GRP_VECTORPACKEDDECIMAL, + + SYSZ_GRP_ENDING, // <-- mark the end of the list of groups +} sysz_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/tms320c64x.h b/white_patch_detect/capstone-master/include/capstone/tms320c64x.h new file mode 100644 index 0000000..9f6d580 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/tms320c64x.h @@ -0,0 +1,359 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#ifndef CAPSTONE_TMS320C64X_H +#define CAPSTONE_TMS320C64X_H + +#ifdef __cplusplus +extern "C" { +#endif + +//#include +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +typedef enum tms320c64x_op_type { + TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand). + TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand). + TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops +} tms320c64x_op_type; + +typedef enum tms320c64x_mem_disp { + TMS320C64X_MEM_DISP_INVALID = 0, + TMS320C64X_MEM_DISP_CONSTANT, + TMS320C64X_MEM_DISP_REGISTER, +} tms320c64x_mem_disp; + +typedef enum tms320c64x_mem_dir { + TMS320C64X_MEM_DIR_INVALID = 0, + TMS320C64X_MEM_DIR_FW, + TMS320C64X_MEM_DIR_BW, +} tms320c64x_mem_dir; + +typedef enum tms320c64x_mem_mod { + TMS320C64X_MEM_MOD_INVALID = 0, + TMS320C64X_MEM_MOD_NO, + TMS320C64X_MEM_MOD_PRE, + TMS320C64X_MEM_MOD_POST, +} tms320c64x_mem_mod; + +typedef struct tms320c64x_op_mem { + unsigned int base; ///< base register + unsigned int disp; ///< displacement/offset value + unsigned int unit; ///< unit of base and offset register + unsigned int scaled; ///< offset scaled + unsigned int disptype; ///< displacement type + unsigned int direction; ///< direction + unsigned int modify; ///< modification +} tms320c64x_op_mem; + +typedef struct cs_tms320c64x_op { + tms320c64x_op_type type; ///< operand type + union { + unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand + int32_t imm; ///< immediate value for IMM operand + tms320c64x_op_mem mem; ///< base/disp value for MEM operand + }; +} cs_tms320c64x_op; + +typedef struct cs_tms320c64x { + uint8_t op_count; + cs_tms320c64x_op operands[8]; ///< operands for this instruction. + struct { + unsigned int reg; + unsigned int zero; + } condition; + struct { + unsigned int unit; + unsigned int side; + unsigned int crosspath; + } funit; + unsigned int parallel; +} cs_tms320c64x; + +typedef enum tms320c64x_reg { + TMS320C64X_REG_INVALID = 0, + + TMS320C64X_REG_AMR, + TMS320C64X_REG_CSR, + TMS320C64X_REG_DIER, + TMS320C64X_REG_DNUM, + TMS320C64X_REG_ECR, + TMS320C64X_REG_GFPGFR, + TMS320C64X_REG_GPLYA, + TMS320C64X_REG_GPLYB, + TMS320C64X_REG_ICR, + TMS320C64X_REG_IER, + TMS320C64X_REG_IERR, + TMS320C64X_REG_ILC, + TMS320C64X_REG_IRP, + TMS320C64X_REG_ISR, + TMS320C64X_REG_ISTP, + TMS320C64X_REG_ITSR, + TMS320C64X_REG_NRP, + TMS320C64X_REG_NTSR, + TMS320C64X_REG_REP, + TMS320C64X_REG_RILC, + TMS320C64X_REG_SSR, + TMS320C64X_REG_TSCH, + TMS320C64X_REG_TSCL, + TMS320C64X_REG_TSR, + TMS320C64X_REG_A0, + TMS320C64X_REG_A1, + TMS320C64X_REG_A2, + TMS320C64X_REG_A3, + TMS320C64X_REG_A4, + TMS320C64X_REG_A5, + TMS320C64X_REG_A6, + TMS320C64X_REG_A7, + TMS320C64X_REG_A8, + TMS320C64X_REG_A9, + TMS320C64X_REG_A10, + TMS320C64X_REG_A11, + TMS320C64X_REG_A12, + TMS320C64X_REG_A13, + TMS320C64X_REG_A14, + TMS320C64X_REG_A15, + TMS320C64X_REG_A16, + TMS320C64X_REG_A17, + TMS320C64X_REG_A18, + TMS320C64X_REG_A19, + TMS320C64X_REG_A20, + TMS320C64X_REG_A21, + TMS320C64X_REG_A22, + TMS320C64X_REG_A23, + TMS320C64X_REG_A24, + TMS320C64X_REG_A25, + TMS320C64X_REG_A26, + TMS320C64X_REG_A27, + TMS320C64X_REG_A28, + TMS320C64X_REG_A29, + TMS320C64X_REG_A30, + TMS320C64X_REG_A31, + TMS320C64X_REG_B0, + TMS320C64X_REG_B1, + TMS320C64X_REG_B2, + TMS320C64X_REG_B3, + TMS320C64X_REG_B4, + TMS320C64X_REG_B5, + TMS320C64X_REG_B6, + TMS320C64X_REG_B7, + TMS320C64X_REG_B8, + TMS320C64X_REG_B9, + TMS320C64X_REG_B10, + TMS320C64X_REG_B11, + TMS320C64X_REG_B12, + TMS320C64X_REG_B13, + TMS320C64X_REG_B14, + TMS320C64X_REG_B15, + TMS320C64X_REG_B16, + TMS320C64X_REG_B17, + TMS320C64X_REG_B18, + TMS320C64X_REG_B19, + TMS320C64X_REG_B20, + TMS320C64X_REG_B21, + TMS320C64X_REG_B22, + TMS320C64X_REG_B23, + TMS320C64X_REG_B24, + TMS320C64X_REG_B25, + TMS320C64X_REG_B26, + TMS320C64X_REG_B27, + TMS320C64X_REG_B28, + TMS320C64X_REG_B29, + TMS320C64X_REG_B30, + TMS320C64X_REG_B31, + TMS320C64X_REG_PCE1, + + TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers + + // Alias registers + TMS320C64X_REG_EFR = TMS320C64X_REG_ECR, + TMS320C64X_REG_IFR = TMS320C64X_REG_ISR, +} tms320c64x_reg; + +typedef enum tms320c64x_insn { + TMS320C64X_INS_INVALID = 0, + + TMS320C64X_INS_ABS, + TMS320C64X_INS_ABS2, + TMS320C64X_INS_ADD, + TMS320C64X_INS_ADD2, + TMS320C64X_INS_ADD4, + TMS320C64X_INS_ADDAB, + TMS320C64X_INS_ADDAD, + TMS320C64X_INS_ADDAH, + TMS320C64X_INS_ADDAW, + TMS320C64X_INS_ADDK, + TMS320C64X_INS_ADDKPC, + TMS320C64X_INS_ADDU, + TMS320C64X_INS_AND, + TMS320C64X_INS_ANDN, + TMS320C64X_INS_AVG2, + TMS320C64X_INS_AVGU4, + TMS320C64X_INS_B, + TMS320C64X_INS_BDEC, + TMS320C64X_INS_BITC4, + TMS320C64X_INS_BNOP, + TMS320C64X_INS_BPOS, + TMS320C64X_INS_CLR, + TMS320C64X_INS_CMPEQ, + TMS320C64X_INS_CMPEQ2, + TMS320C64X_INS_CMPEQ4, + TMS320C64X_INS_CMPGT, + TMS320C64X_INS_CMPGT2, + TMS320C64X_INS_CMPGTU4, + TMS320C64X_INS_CMPLT, + TMS320C64X_INS_CMPLTU, + TMS320C64X_INS_DEAL, + TMS320C64X_INS_DOTP2, + TMS320C64X_INS_DOTPN2, + TMS320C64X_INS_DOTPNRSU2, + TMS320C64X_INS_DOTPRSU2, + TMS320C64X_INS_DOTPSU4, + TMS320C64X_INS_DOTPU4, + TMS320C64X_INS_EXT, + TMS320C64X_INS_EXTU, + TMS320C64X_INS_GMPGTU, + TMS320C64X_INS_GMPY4, + TMS320C64X_INS_LDB, + TMS320C64X_INS_LDBU, + TMS320C64X_INS_LDDW, + TMS320C64X_INS_LDH, + TMS320C64X_INS_LDHU, + TMS320C64X_INS_LDNDW, + TMS320C64X_INS_LDNW, + TMS320C64X_INS_LDW, + TMS320C64X_INS_LMBD, + TMS320C64X_INS_MAX2, + TMS320C64X_INS_MAXU4, + TMS320C64X_INS_MIN2, + TMS320C64X_INS_MINU4, + TMS320C64X_INS_MPY, + TMS320C64X_INS_MPY2, + TMS320C64X_INS_MPYH, + TMS320C64X_INS_MPYHI, + TMS320C64X_INS_MPYHIR, + TMS320C64X_INS_MPYHL, + TMS320C64X_INS_MPYHLU, + TMS320C64X_INS_MPYHSLU, + TMS320C64X_INS_MPYHSU, + TMS320C64X_INS_MPYHU, + TMS320C64X_INS_MPYHULS, + TMS320C64X_INS_MPYHUS, + TMS320C64X_INS_MPYLH, + TMS320C64X_INS_MPYLHU, + TMS320C64X_INS_MPYLI, + TMS320C64X_INS_MPYLIR, + TMS320C64X_INS_MPYLSHU, + TMS320C64X_INS_MPYLUHS, + TMS320C64X_INS_MPYSU, + TMS320C64X_INS_MPYSU4, + TMS320C64X_INS_MPYU, + TMS320C64X_INS_MPYU4, + TMS320C64X_INS_MPYUS, + TMS320C64X_INS_MVC, + TMS320C64X_INS_MVD, + TMS320C64X_INS_MVK, + TMS320C64X_INS_MVKL, + TMS320C64X_INS_MVKLH, + TMS320C64X_INS_NOP, + TMS320C64X_INS_NORM, + TMS320C64X_INS_OR, + TMS320C64X_INS_PACK2, + TMS320C64X_INS_PACKH2, + TMS320C64X_INS_PACKH4, + TMS320C64X_INS_PACKHL2, + TMS320C64X_INS_PACKL4, + TMS320C64X_INS_PACKLH2, + TMS320C64X_INS_ROTL, + TMS320C64X_INS_SADD, + TMS320C64X_INS_SADD2, + TMS320C64X_INS_SADDU4, + TMS320C64X_INS_SADDUS2, + TMS320C64X_INS_SAT, + TMS320C64X_INS_SET, + TMS320C64X_INS_SHFL, + TMS320C64X_INS_SHL, + TMS320C64X_INS_SHLMB, + TMS320C64X_INS_SHR, + TMS320C64X_INS_SHR2, + TMS320C64X_INS_SHRMB, + TMS320C64X_INS_SHRU, + TMS320C64X_INS_SHRU2, + TMS320C64X_INS_SMPY, + TMS320C64X_INS_SMPY2, + TMS320C64X_INS_SMPYH, + TMS320C64X_INS_SMPYHL, + TMS320C64X_INS_SMPYLH, + TMS320C64X_INS_SPACK2, + TMS320C64X_INS_SPACKU4, + TMS320C64X_INS_SSHL, + TMS320C64X_INS_SSHVL, + TMS320C64X_INS_SSHVR, + TMS320C64X_INS_SSUB, + TMS320C64X_INS_STB, + TMS320C64X_INS_STDW, + TMS320C64X_INS_STH, + TMS320C64X_INS_STNDW, + TMS320C64X_INS_STNW, + TMS320C64X_INS_STW, + TMS320C64X_INS_SUB, + TMS320C64X_INS_SUB2, + TMS320C64X_INS_SUB4, + TMS320C64X_INS_SUBAB, + TMS320C64X_INS_SUBABS4, + TMS320C64X_INS_SUBAH, + TMS320C64X_INS_SUBAW, + TMS320C64X_INS_SUBC, + TMS320C64X_INS_SUBU, + TMS320C64X_INS_SWAP4, + TMS320C64X_INS_UNPKHU4, + TMS320C64X_INS_UNPKLU4, + TMS320C64X_INS_XOR, + TMS320C64X_INS_XPND2, + TMS320C64X_INS_XPND4, + // Aliases + TMS320C64X_INS_IDLE, + TMS320C64X_INS_MV, + TMS320C64X_INS_NEG, + TMS320C64X_INS_NOT, + TMS320C64X_INS_SWAP2, + TMS320C64X_INS_ZERO, + + TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions +} tms320c64x_insn; + +typedef enum tms320c64x_insn_group { + TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP + + TMS320C64X_GRP_FUNIT_D = 128, + TMS320C64X_GRP_FUNIT_L, + TMS320C64X_GRP_FUNIT_M, + TMS320C64X_GRP_FUNIT_S, + TMS320C64X_GRP_FUNIT_NO, + + TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups +} tms320c64x_insn_group; + +typedef enum tms320c64x_funit { + TMS320C64X_FUNIT_INVALID = 0, + TMS320C64X_FUNIT_D, + TMS320C64X_FUNIT_L, + TMS320C64X_FUNIT_M, + TMS320C64X_FUNIT_S, + TMS320C64X_FUNIT_NO +} tms320c64x_funit; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/white_patch_detect/capstone-master/include/capstone/x86.h b/white_patch_detect/capstone-master/include/capstone/x86.h new file mode 100644 index 0000000..f8fc09e --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/x86.h @@ -0,0 +1,1972 @@ +#ifndef CAPSTONE_X86_H +#define CAPSTONE_X86_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +/// Calculate relative address for X86-64, given cs_insn structure +#define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \ + ? (uint64_t)((insn).detail->x86.operands[0].imm) \ + : (((insn).address + (insn).size) + (uint64_t)(insn).detail->x86.disp)) + +/// X86 registers +typedef enum x86_reg { + X86_REG_INVALID = 0, + X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL, + X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL, + X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL, + X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP, + X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS, + X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP, + X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX, + X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX, + X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI, + X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0, + X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5, + X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10, + X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15, + X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4, + X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9, + X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14, + X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3, + X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7, + X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4, + X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1, + X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6, + X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, + X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, + X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3, + X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7, + X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4, + X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9, + X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14, + X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19, + X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24, + X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29, + X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, + X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, + X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, + X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17, + X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22, + X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27, + X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0, + X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5, + X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10, + X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15, + X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20, + X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25, + X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30, + X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B, + X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D, + X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D, + X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W, + X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W, + + X86_REG_ENDING // <-- mark the end of the list of registers +} x86_reg; + +// Sub-flags of EFLAGS +#define X86_EFLAGS_MODIFY_AF (1ULL << 0) +#define X86_EFLAGS_MODIFY_CF (1ULL << 1) +#define X86_EFLAGS_MODIFY_SF (1ULL << 2) +#define X86_EFLAGS_MODIFY_ZF (1ULL << 3) +#define X86_EFLAGS_MODIFY_PF (1ULL << 4) +#define X86_EFLAGS_MODIFY_OF (1ULL << 5) +#define X86_EFLAGS_MODIFY_TF (1ULL << 6) +#define X86_EFLAGS_MODIFY_IF (1ULL << 7) +#define X86_EFLAGS_MODIFY_DF (1ULL << 8) +#define X86_EFLAGS_MODIFY_NT (1ULL << 9) +#define X86_EFLAGS_MODIFY_RF (1ULL << 10) +#define X86_EFLAGS_PRIOR_OF (1ULL << 11) +#define X86_EFLAGS_PRIOR_SF (1ULL << 12) +#define X86_EFLAGS_PRIOR_ZF (1ULL << 13) +#define X86_EFLAGS_PRIOR_AF (1ULL << 14) +#define X86_EFLAGS_PRIOR_PF (1ULL << 15) +#define X86_EFLAGS_PRIOR_CF (1ULL << 16) +#define X86_EFLAGS_PRIOR_TF (1ULL << 17) +#define X86_EFLAGS_PRIOR_IF (1ULL << 18) +#define X86_EFLAGS_PRIOR_DF (1ULL << 19) +#define X86_EFLAGS_PRIOR_NT (1ULL << 20) +#define X86_EFLAGS_RESET_OF (1ULL << 21) +#define X86_EFLAGS_RESET_CF (1ULL << 22) +#define X86_EFLAGS_RESET_DF (1ULL << 23) +#define X86_EFLAGS_RESET_IF (1ULL << 24) +#define X86_EFLAGS_RESET_SF (1ULL << 25) +#define X86_EFLAGS_RESET_AF (1ULL << 26) +#define X86_EFLAGS_RESET_TF (1ULL << 27) +#define X86_EFLAGS_RESET_NT (1ULL << 28) +#define X86_EFLAGS_RESET_PF (1ULL << 29) +#define X86_EFLAGS_SET_CF (1ULL << 30) +#define X86_EFLAGS_SET_DF (1ULL << 31) +#define X86_EFLAGS_SET_IF (1ULL << 32) +#define X86_EFLAGS_TEST_OF (1ULL << 33) +#define X86_EFLAGS_TEST_SF (1ULL << 34) +#define X86_EFLAGS_TEST_ZF (1ULL << 35) +#define X86_EFLAGS_TEST_PF (1ULL << 36) +#define X86_EFLAGS_TEST_CF (1ULL << 37) +#define X86_EFLAGS_TEST_NT (1ULL << 38) +#define X86_EFLAGS_TEST_DF (1ULL << 39) +#define X86_EFLAGS_UNDEFINED_OF (1ULL << 40) +#define X86_EFLAGS_UNDEFINED_SF (1ULL << 41) +#define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42) +#define X86_EFLAGS_UNDEFINED_PF (1ULL << 43) +#define X86_EFLAGS_UNDEFINED_AF (1ULL << 44) +#define X86_EFLAGS_UNDEFINED_CF (1ULL << 45) +#define X86_EFLAGS_RESET_RF (1ULL << 46) +#define X86_EFLAGS_TEST_RF (1ULL << 47) +#define X86_EFLAGS_TEST_IF (1ULL << 48) +#define X86_EFLAGS_TEST_TF (1ULL << 49) +#define X86_EFLAGS_TEST_AF (1ULL << 50) +#define X86_EFLAGS_RESET_ZF (1ULL << 51) +#define X86_EFLAGS_SET_OF (1ULL << 52) +#define X86_EFLAGS_SET_SF (1ULL << 53) +#define X86_EFLAGS_SET_ZF (1ULL << 54) +#define X86_EFLAGS_SET_AF (1ULL << 55) +#define X86_EFLAGS_SET_PF (1ULL << 56) +#define X86_EFLAGS_RESET_0F (1ULL << 57) +#define X86_EFLAGS_RESET_AC (1ULL << 58) + +#define X86_FPU_FLAGS_MODIFY_C0 (1ULL << 0) +#define X86_FPU_FLAGS_MODIFY_C1 (1ULL << 1) +#define X86_FPU_FLAGS_MODIFY_C2 (1ULL << 2) +#define X86_FPU_FLAGS_MODIFY_C3 (1ULL << 3) +#define X86_FPU_FLAGS_RESET_C0 (1ULL << 4) +#define X86_FPU_FLAGS_RESET_C1 (1ULL << 5) +#define X86_FPU_FLAGS_RESET_C2 (1ULL << 6) +#define X86_FPU_FLAGS_RESET_C3 (1ULL << 7) +#define X86_FPU_FLAGS_SET_C0 (1ULL << 8) +#define X86_FPU_FLAGS_SET_C1 (1ULL << 9) +#define X86_FPU_FLAGS_SET_C2 (1ULL << 10) +#define X86_FPU_FLAGS_SET_C3 (1ULL << 11) +#define X86_FPU_FLAGS_UNDEFINED_C0 (1ULL << 12) +#define X86_FPU_FLAGS_UNDEFINED_C1 (1ULL << 13) +#define X86_FPU_FLAGS_UNDEFINED_C2 (1ULL << 14) +#define X86_FPU_FLAGS_UNDEFINED_C3 (1ULL << 15) +#define X86_FPU_FLAGS_TEST_C0 (1ULL << 16) +#define X86_FPU_FLAGS_TEST_C1 (1ULL << 17) +#define X86_FPU_FLAGS_TEST_C2 (1ULL << 18) +#define X86_FPU_FLAGS_TEST_C3 (1ULL << 19) + + +/// Operand type for instruction's operands +typedef enum x86_op_type { + X86_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + X86_OP_REG, ///< = CS_OP_REG (Register operand). + X86_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + X86_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} x86_op_type; + +/// XOP Code Condition type +typedef enum x86_xop_cc { + X86_XOP_CC_INVALID = 0, ///< Uninitialized. + X86_XOP_CC_LT, + X86_XOP_CC_LE, + X86_XOP_CC_GT, + X86_XOP_CC_GE, + X86_XOP_CC_EQ, + X86_XOP_CC_NEQ, + X86_XOP_CC_FALSE, + X86_XOP_CC_TRUE, +} x86_xop_cc; + +/// AVX broadcast type +typedef enum x86_avx_bcast { + X86_AVX_BCAST_INVALID = 0, ///< Uninitialized. + X86_AVX_BCAST_2, ///< AVX512 broadcast type {1to2} + X86_AVX_BCAST_4, ///< AVX512 broadcast type {1to4} + X86_AVX_BCAST_8, ///< AVX512 broadcast type {1to8} + X86_AVX_BCAST_16, ///< AVX512 broadcast type {1to16} +} x86_avx_bcast; + +/// SSE Code Condition type +typedef enum x86_sse_cc { + X86_SSE_CC_INVALID = 0, ///< Uninitialized. + X86_SSE_CC_EQ, + X86_SSE_CC_LT, + X86_SSE_CC_LE, + X86_SSE_CC_UNORD, + X86_SSE_CC_NEQ, + X86_SSE_CC_NLT, + X86_SSE_CC_NLE, + X86_SSE_CC_ORD, +} x86_sse_cc; + +/// AVX Code Condition type +typedef enum x86_avx_cc { + X86_AVX_CC_INVALID = 0, ///< Uninitialized. + X86_AVX_CC_EQ, + X86_AVX_CC_LT, + X86_AVX_CC_LE, + X86_AVX_CC_UNORD, + X86_AVX_CC_NEQ, + X86_AVX_CC_NLT, + X86_AVX_CC_NLE, + X86_AVX_CC_ORD, + X86_AVX_CC_EQ_UQ, + X86_AVX_CC_NGE, + X86_AVX_CC_NGT, + X86_AVX_CC_FALSE, + X86_AVX_CC_NEQ_OQ, + X86_AVX_CC_GE, + X86_AVX_CC_GT, + X86_AVX_CC_TRUE, + X86_AVX_CC_EQ_OS, + X86_AVX_CC_LT_OQ, + X86_AVX_CC_LE_OQ, + X86_AVX_CC_UNORD_S, + X86_AVX_CC_NEQ_US, + X86_AVX_CC_NLT_UQ, + X86_AVX_CC_NLE_UQ, + X86_AVX_CC_ORD_S, + X86_AVX_CC_EQ_US, + X86_AVX_CC_NGE_UQ, + X86_AVX_CC_NGT_UQ, + X86_AVX_CC_FALSE_OS, + X86_AVX_CC_NEQ_OS, + X86_AVX_CC_GE_OQ, + X86_AVX_CC_GT_OQ, + X86_AVX_CC_TRUE_US, +} x86_avx_cc; + +/// AVX static rounding mode type +typedef enum x86_avx_rm { + X86_AVX_RM_INVALID = 0, ///< Uninitialized. + X86_AVX_RM_RN, ///< Round to nearest + X86_AVX_RM_RD, ///< Round down + X86_AVX_RM_RU, ///< Round up + X86_AVX_RM_RZ, ///< Round toward zero +} x86_avx_rm; + +/// Instruction prefixes - to be used in cs_x86.prefix[] +typedef enum x86_prefix { + X86_PREFIX_LOCK = 0xf0, ///< lock (cs_x86.prefix[0] + X86_PREFIX_REP = 0xf3, ///< rep (cs_x86.prefix[0] + X86_PREFIX_REPE = 0xf3, ///< repe/repz (cs_x86.prefix[0] + X86_PREFIX_REPNE = 0xf2, ///< repne/repnz (cs_x86.prefix[0] + + X86_PREFIX_CS = 0x2e, ///< segment override CS (cs_x86.prefix[1] + X86_PREFIX_SS = 0x36, ///< segment override SS (cs_x86.prefix[1] + X86_PREFIX_DS = 0x3e, ///< segment override DS (cs_x86.prefix[1] + X86_PREFIX_ES = 0x26, ///< segment override ES (cs_x86.prefix[1] + X86_PREFIX_FS = 0x64, ///< segment override FS (cs_x86.prefix[1] + X86_PREFIX_GS = 0x65, ///< segment override GS (cs_x86.prefix[1] + + X86_PREFIX_OPSIZE = 0x66, ///< operand-size override (cs_x86.prefix[2] + X86_PREFIX_ADDRSIZE = 0x67, ///< address-size override (cs_x86.prefix[3] +} x86_prefix; + +/// Instruction's operand referring to memory +/// This is associated with X86_OP_MEM operand type above +typedef struct x86_op_mem { + x86_reg segment; ///< segment register (or X86_REG_INVALID if irrelevant) + x86_reg base; ///< base register (or X86_REG_INVALID if irrelevant) + x86_reg index; ///< index register (or X86_REG_INVALID if irrelevant) + int scale; ///< scale for index register + int64_t disp; ///< displacement value +} x86_op_mem; + +/// Instruction operand +typedef struct cs_x86_op { + x86_op_type type; ///< operand type + union { + x86_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + x86_op_mem mem; ///< base/index/scale/disp value for MEM operand + }; + + /// size of this operand (in bytes). + uint8_t size; + + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// This field is combined of cs_ac_type. + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; + + /// AVX broadcast type, or 0 if irrelevant + x86_avx_bcast avx_bcast; + + /// AVX zero opmask {z} + bool avx_zero_opmask; +} cs_x86_op; + +typedef struct cs_x86_encoding { + /// ModR/M offset, or 0 when irrelevant + uint8_t modrm_offset; + + /// Displacement offset, or 0 when irrelevant. + uint8_t disp_offset; + uint8_t disp_size; + + /// Immediate offset, or 0 when irrelevant. + uint8_t imm_offset; + uint8_t imm_size; +} cs_x86_encoding; + +/// Instruction structure +typedef struct cs_x86 { + /// Instruction prefix, which can be up to 4 bytes. + /// A prefix byte gets value 0 when irrelevant. + /// prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) + /// prefix[1] indicates segment override (irrelevant for x86_64): + /// See X86_PREFIX_CS/SS/DS/ES/FS/GS above. + /// prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) + /// prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) + uint8_t prefix[4]; + + /// Instruction opcode, which can be from 1 to 4 bytes in size. + /// This contains VEX opcode as well. + /// An trailing opcode byte gets value 0 when irrelevant. + uint8_t opcode[4]; + + /// REX prefix: only a non-zero value is relevant for x86_64 + uint8_t rex; + + /// Address size, which can be overridden with above prefix[5]. + uint8_t addr_size; + + /// ModR/M byte + uint8_t modrm; + + /// SIB value, or 0 when irrelevant. + uint8_t sib; + + /// Displacement value, valid if encoding.disp_offset != 0 + int64_t disp; + + /// SIB index register, or X86_REG_INVALID when irrelevant. + x86_reg sib_index; + /// SIB scale, only applicable if sib_index is valid. + int8_t sib_scale; + /// SIB base register, or X86_REG_INVALID when irrelevant. + x86_reg sib_base; + + /// XOP Code Condition + x86_xop_cc xop_cc; + + /// SSE Code Condition + x86_sse_cc sse_cc; + + /// AVX Code Condition + x86_avx_cc avx_cc; + + /// AVX Suppress all Exception + bool avx_sae; + + /// AVX static rounding mode + x86_avx_rm avx_rm; + + + union { + /// EFLAGS updated by this instruction. + /// This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h + uint64_t eflags; + /// FPU_FLAGS updated by this instruction. + /// This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h + uint64_t fpu_flags; + }; + + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + + cs_x86_op operands[8]; ///< operands for this instruction. + + cs_x86_encoding encoding; ///< encoding information +} cs_x86; + +/// X86 instructions +typedef enum x86_insn { + X86_INS_INVALID = 0, + + X86_INS_AAA, + X86_INS_AAD, + X86_INS_AAM, + X86_INS_AAS, + X86_INS_FABS, + X86_INS_ADC, + X86_INS_ADCX, + X86_INS_ADD, + X86_INS_ADDPD, + X86_INS_ADDPS, + X86_INS_ADDSD, + X86_INS_ADDSS, + X86_INS_ADDSUBPD, + X86_INS_ADDSUBPS, + X86_INS_FADD, + X86_INS_FIADD, + X86_INS_FADDP, + X86_INS_ADOX, + X86_INS_AESDECLAST, + X86_INS_AESDEC, + X86_INS_AESENCLAST, + X86_INS_AESENC, + X86_INS_AESIMC, + X86_INS_AESKEYGENASSIST, + X86_INS_AND, + X86_INS_ANDN, + X86_INS_ANDNPD, + X86_INS_ANDNPS, + X86_INS_ANDPD, + X86_INS_ANDPS, + X86_INS_ARPL, + X86_INS_BEXTR, + X86_INS_BLCFILL, + X86_INS_BLCI, + X86_INS_BLCIC, + X86_INS_BLCMSK, + X86_INS_BLCS, + X86_INS_BLENDPD, + X86_INS_BLENDPS, + X86_INS_BLENDVPD, + X86_INS_BLENDVPS, + X86_INS_BLSFILL, + X86_INS_BLSI, + X86_INS_BLSIC, + X86_INS_BLSMSK, + X86_INS_BLSR, + X86_INS_BOUND, + X86_INS_BSF, + X86_INS_BSR, + X86_INS_BSWAP, + X86_INS_BT, + X86_INS_BTC, + X86_INS_BTR, + X86_INS_BTS, + X86_INS_BZHI, + X86_INS_CALL, + X86_INS_CBW, + X86_INS_CDQ, + X86_INS_CDQE, + X86_INS_FCHS, + X86_INS_CLAC, + X86_INS_CLC, + X86_INS_CLD, + X86_INS_CLFLUSH, + X86_INS_CLFLUSHOPT, + X86_INS_CLGI, + X86_INS_CLI, + X86_INS_CLTS, + X86_INS_CLWB, + X86_INS_CMC, + X86_INS_CMOVA, + X86_INS_CMOVAE, + X86_INS_CMOVB, + X86_INS_CMOVBE, + X86_INS_FCMOVBE, + X86_INS_FCMOVB, + X86_INS_CMOVE, + X86_INS_FCMOVE, + X86_INS_CMOVG, + X86_INS_CMOVGE, + X86_INS_CMOVL, + X86_INS_CMOVLE, + X86_INS_FCMOVNBE, + X86_INS_FCMOVNB, + X86_INS_CMOVNE, + X86_INS_FCMOVNE, + X86_INS_CMOVNO, + X86_INS_CMOVNP, + X86_INS_FCMOVNU, + X86_INS_CMOVNS, + X86_INS_CMOVO, + X86_INS_CMOVP, + X86_INS_FCMOVU, + X86_INS_CMOVS, + X86_INS_CMP, + X86_INS_CMPSB, + X86_INS_CMPSQ, + X86_INS_CMPSW, + X86_INS_CMPXCHG16B, + X86_INS_CMPXCHG, + X86_INS_CMPXCHG8B, + X86_INS_COMISD, + X86_INS_COMISS, + X86_INS_FCOMP, + X86_INS_FCOMIP, + X86_INS_FCOMI, + X86_INS_FCOM, + X86_INS_FCOS, + X86_INS_CPUID, + X86_INS_CQO, + X86_INS_CRC32, + X86_INS_CVTDQ2PD, + X86_INS_CVTDQ2PS, + X86_INS_CVTPD2DQ, + X86_INS_CVTPD2PS, + X86_INS_CVTPS2DQ, + X86_INS_CVTPS2PD, + X86_INS_CVTSD2SI, + X86_INS_CVTSD2SS, + X86_INS_CVTSI2SD, + X86_INS_CVTSI2SS, + X86_INS_CVTSS2SD, + X86_INS_CVTSS2SI, + X86_INS_CVTTPD2DQ, + X86_INS_CVTTPS2DQ, + X86_INS_CVTTSD2SI, + X86_INS_CVTTSS2SI, + X86_INS_CWD, + X86_INS_CWDE, + X86_INS_DAA, + X86_INS_DAS, + X86_INS_DATA16, + X86_INS_DEC, + X86_INS_DIV, + X86_INS_DIVPD, + X86_INS_DIVPS, + X86_INS_FDIVR, + X86_INS_FIDIVR, + X86_INS_FDIVRP, + X86_INS_DIVSD, + X86_INS_DIVSS, + X86_INS_FDIV, + X86_INS_FIDIV, + X86_INS_FDIVP, + X86_INS_DPPD, + X86_INS_DPPS, + X86_INS_RET, + X86_INS_ENCLS, + X86_INS_ENCLU, + X86_INS_ENTER, + X86_INS_EXTRACTPS, + X86_INS_EXTRQ, + X86_INS_F2XM1, + X86_INS_LCALL, + X86_INS_LJMP, + X86_INS_FBLD, + X86_INS_FBSTP, + X86_INS_FCOMPP, + X86_INS_FDECSTP, + X86_INS_FEMMS, + X86_INS_FFREE, + X86_INS_FICOM, + X86_INS_FICOMP, + X86_INS_FINCSTP, + X86_INS_FLDCW, + X86_INS_FLDENV, + X86_INS_FLDL2E, + X86_INS_FLDL2T, + X86_INS_FLDLG2, + X86_INS_FLDLN2, + X86_INS_FLDPI, + X86_INS_FNCLEX, + X86_INS_FNINIT, + X86_INS_FNOP, + X86_INS_FNSTCW, + X86_INS_FNSTSW, + X86_INS_FPATAN, + X86_INS_FPREM, + X86_INS_FPREM1, + X86_INS_FPTAN, + X86_INS_FFREEP, + X86_INS_FRNDINT, + X86_INS_FRSTOR, + X86_INS_FNSAVE, + X86_INS_FSCALE, + X86_INS_FSETPM, + X86_INS_FSINCOS, + X86_INS_FNSTENV, + X86_INS_FXAM, + X86_INS_FXRSTOR, + X86_INS_FXRSTOR64, + X86_INS_FXSAVE, + X86_INS_FXSAVE64, + X86_INS_FXTRACT, + X86_INS_FYL2X, + X86_INS_FYL2XP1, + X86_INS_MOVAPD, + X86_INS_MOVAPS, + X86_INS_ORPD, + X86_INS_ORPS, + X86_INS_VMOVAPD, + X86_INS_VMOVAPS, + X86_INS_XORPD, + X86_INS_XORPS, + X86_INS_GETSEC, + X86_INS_HADDPD, + X86_INS_HADDPS, + X86_INS_HLT, + X86_INS_HSUBPD, + X86_INS_HSUBPS, + X86_INS_IDIV, + X86_INS_FILD, + X86_INS_IMUL, + X86_INS_IN, + X86_INS_INC, + X86_INS_INSB, + X86_INS_INSERTPS, + X86_INS_INSERTQ, + X86_INS_INSD, + X86_INS_INSW, + X86_INS_INT, + X86_INS_INT1, + X86_INS_INT3, + X86_INS_INTO, + X86_INS_INVD, + X86_INS_INVEPT, + X86_INS_INVLPG, + X86_INS_INVLPGA, + X86_INS_INVPCID, + X86_INS_INVVPID, + X86_INS_IRET, + X86_INS_IRETD, + X86_INS_IRETQ, + X86_INS_FISTTP, + X86_INS_FIST, + X86_INS_FISTP, + X86_INS_UCOMISD, + X86_INS_UCOMISS, + X86_INS_VCOMISD, + X86_INS_VCOMISS, + X86_INS_VCVTSD2SS, + X86_INS_VCVTSI2SD, + X86_INS_VCVTSI2SS, + X86_INS_VCVTSS2SD, + X86_INS_VCVTTSD2SI, + X86_INS_VCVTTSD2USI, + X86_INS_VCVTTSS2SI, + X86_INS_VCVTTSS2USI, + X86_INS_VCVTUSI2SD, + X86_INS_VCVTUSI2SS, + X86_INS_VUCOMISD, + X86_INS_VUCOMISS, + X86_INS_JAE, + X86_INS_JA, + X86_INS_JBE, + X86_INS_JB, + X86_INS_JCXZ, + X86_INS_JECXZ, + X86_INS_JE, + X86_INS_JGE, + X86_INS_JG, + X86_INS_JLE, + X86_INS_JL, + X86_INS_JMP, + X86_INS_JNE, + X86_INS_JNO, + X86_INS_JNP, + X86_INS_JNS, + X86_INS_JO, + X86_INS_JP, + X86_INS_JRCXZ, + X86_INS_JS, + X86_INS_KANDB, + X86_INS_KANDD, + X86_INS_KANDNB, + X86_INS_KANDND, + X86_INS_KANDNQ, + X86_INS_KANDNW, + X86_INS_KANDQ, + X86_INS_KANDW, + X86_INS_KMOVB, + X86_INS_KMOVD, + X86_INS_KMOVQ, + X86_INS_KMOVW, + X86_INS_KNOTB, + X86_INS_KNOTD, + X86_INS_KNOTQ, + X86_INS_KNOTW, + X86_INS_KORB, + X86_INS_KORD, + X86_INS_KORQ, + X86_INS_KORTESTB, + X86_INS_KORTESTD, + X86_INS_KORTESTQ, + X86_INS_KORTESTW, + X86_INS_KORW, + X86_INS_KSHIFTLB, + X86_INS_KSHIFTLD, + X86_INS_KSHIFTLQ, + X86_INS_KSHIFTLW, + X86_INS_KSHIFTRB, + X86_INS_KSHIFTRD, + X86_INS_KSHIFTRQ, + X86_INS_KSHIFTRW, + X86_INS_KUNPCKBW, + X86_INS_KXNORB, + X86_INS_KXNORD, + X86_INS_KXNORQ, + X86_INS_KXNORW, + X86_INS_KXORB, + X86_INS_KXORD, + X86_INS_KXORQ, + X86_INS_KXORW, + X86_INS_LAHF, + X86_INS_LAR, + X86_INS_LDDQU, + X86_INS_LDMXCSR, + X86_INS_LDS, + X86_INS_FLDZ, + X86_INS_FLD1, + X86_INS_FLD, + X86_INS_LEA, + X86_INS_LEAVE, + X86_INS_LES, + X86_INS_LFENCE, + X86_INS_LFS, + X86_INS_LGDT, + X86_INS_LGS, + X86_INS_LIDT, + X86_INS_LLDT, + X86_INS_LMSW, + X86_INS_OR, + X86_INS_SUB, + X86_INS_XOR, + X86_INS_LODSB, + X86_INS_LODSD, + X86_INS_LODSQ, + X86_INS_LODSW, + X86_INS_LOOP, + X86_INS_LOOPE, + X86_INS_LOOPNE, + X86_INS_RETF, + X86_INS_RETFQ, + X86_INS_LSL, + X86_INS_LSS, + X86_INS_LTR, + X86_INS_XADD, + X86_INS_LZCNT, + X86_INS_MASKMOVDQU, + X86_INS_MAXPD, + X86_INS_MAXPS, + X86_INS_MAXSD, + X86_INS_MAXSS, + X86_INS_MFENCE, + X86_INS_MINPD, + X86_INS_MINPS, + X86_INS_MINSD, + X86_INS_MINSS, + X86_INS_CVTPD2PI, + X86_INS_CVTPI2PD, + X86_INS_CVTPI2PS, + X86_INS_CVTPS2PI, + X86_INS_CVTTPD2PI, + X86_INS_CVTTPS2PI, + X86_INS_EMMS, + X86_INS_MASKMOVQ, + X86_INS_MOVD, + X86_INS_MOVDQ2Q, + X86_INS_MOVNTQ, + X86_INS_MOVQ2DQ, + X86_INS_MOVQ, + X86_INS_PABSB, + X86_INS_PABSD, + X86_INS_PABSW, + X86_INS_PACKSSDW, + X86_INS_PACKSSWB, + X86_INS_PACKUSWB, + X86_INS_PADDB, + X86_INS_PADDD, + X86_INS_PADDQ, + X86_INS_PADDSB, + X86_INS_PADDSW, + X86_INS_PADDUSB, + X86_INS_PADDUSW, + X86_INS_PADDW, + X86_INS_PALIGNR, + X86_INS_PANDN, + X86_INS_PAND, + X86_INS_PAVGB, + X86_INS_PAVGW, + X86_INS_PCMPEQB, + X86_INS_PCMPEQD, + X86_INS_PCMPEQW, + X86_INS_PCMPGTB, + X86_INS_PCMPGTD, + X86_INS_PCMPGTW, + X86_INS_PEXTRW, + X86_INS_PHADDSW, + X86_INS_PHADDW, + X86_INS_PHADDD, + X86_INS_PHSUBD, + X86_INS_PHSUBSW, + X86_INS_PHSUBW, + X86_INS_PINSRW, + X86_INS_PMADDUBSW, + X86_INS_PMADDWD, + X86_INS_PMAXSW, + X86_INS_PMAXUB, + X86_INS_PMINSW, + X86_INS_PMINUB, + X86_INS_PMOVMSKB, + X86_INS_PMULHRSW, + X86_INS_PMULHUW, + X86_INS_PMULHW, + X86_INS_PMULLW, + X86_INS_PMULUDQ, + X86_INS_POR, + X86_INS_PSADBW, + X86_INS_PSHUFB, + X86_INS_PSHUFW, + X86_INS_PSIGNB, + X86_INS_PSIGND, + X86_INS_PSIGNW, + X86_INS_PSLLD, + X86_INS_PSLLQ, + X86_INS_PSLLW, + X86_INS_PSRAD, + X86_INS_PSRAW, + X86_INS_PSRLD, + X86_INS_PSRLQ, + X86_INS_PSRLW, + X86_INS_PSUBB, + X86_INS_PSUBD, + X86_INS_PSUBQ, + X86_INS_PSUBSB, + X86_INS_PSUBSW, + X86_INS_PSUBUSB, + X86_INS_PSUBUSW, + X86_INS_PSUBW, + X86_INS_PUNPCKHBW, + X86_INS_PUNPCKHDQ, + X86_INS_PUNPCKHWD, + X86_INS_PUNPCKLBW, + X86_INS_PUNPCKLDQ, + X86_INS_PUNPCKLWD, + X86_INS_PXOR, + X86_INS_MONITOR, + X86_INS_MONTMUL, + X86_INS_MOV, + X86_INS_MOVABS, + X86_INS_MOVBE, + X86_INS_MOVDDUP, + X86_INS_MOVDQA, + X86_INS_MOVDQU, + X86_INS_MOVHLPS, + X86_INS_MOVHPD, + X86_INS_MOVHPS, + X86_INS_MOVLHPS, + X86_INS_MOVLPD, + X86_INS_MOVLPS, + X86_INS_MOVMSKPD, + X86_INS_MOVMSKPS, + X86_INS_MOVNTDQA, + X86_INS_MOVNTDQ, + X86_INS_MOVNTI, + X86_INS_MOVNTPD, + X86_INS_MOVNTPS, + X86_INS_MOVNTSD, + X86_INS_MOVNTSS, + X86_INS_MOVSB, + X86_INS_MOVSD, + X86_INS_MOVSHDUP, + X86_INS_MOVSLDUP, + X86_INS_MOVSQ, + X86_INS_MOVSS, + X86_INS_MOVSW, + X86_INS_MOVSX, + X86_INS_MOVSXD, + X86_INS_MOVUPD, + X86_INS_MOVUPS, + X86_INS_MOVZX, + X86_INS_MPSADBW, + X86_INS_MUL, + X86_INS_MULPD, + X86_INS_MULPS, + X86_INS_MULSD, + X86_INS_MULSS, + X86_INS_MULX, + X86_INS_FMUL, + X86_INS_FIMUL, + X86_INS_FMULP, + X86_INS_MWAIT, + X86_INS_NEG, + X86_INS_NOP, + X86_INS_NOT, + X86_INS_OUT, + X86_INS_OUTSB, + X86_INS_OUTSD, + X86_INS_OUTSW, + X86_INS_PACKUSDW, + X86_INS_PAUSE, + X86_INS_PAVGUSB, + X86_INS_PBLENDVB, + X86_INS_PBLENDW, + X86_INS_PCLMULQDQ, + X86_INS_PCMPEQQ, + X86_INS_PCMPESTRI, + X86_INS_PCMPESTRM, + X86_INS_PCMPGTQ, + X86_INS_PCMPISTRI, + X86_INS_PCMPISTRM, + X86_INS_PCOMMIT, + X86_INS_PDEP, + X86_INS_PEXT, + X86_INS_PEXTRB, + X86_INS_PEXTRD, + X86_INS_PEXTRQ, + X86_INS_PF2ID, + X86_INS_PF2IW, + X86_INS_PFACC, + X86_INS_PFADD, + X86_INS_PFCMPEQ, + X86_INS_PFCMPGE, + X86_INS_PFCMPGT, + X86_INS_PFMAX, + X86_INS_PFMIN, + X86_INS_PFMUL, + X86_INS_PFNACC, + X86_INS_PFPNACC, + X86_INS_PFRCPIT1, + X86_INS_PFRCPIT2, + X86_INS_PFRCP, + X86_INS_PFRSQIT1, + X86_INS_PFRSQRT, + X86_INS_PFSUBR, + X86_INS_PFSUB, + X86_INS_PHMINPOSUW, + X86_INS_PI2FD, + X86_INS_PI2FW, + X86_INS_PINSRB, + X86_INS_PINSRD, + X86_INS_PINSRQ, + X86_INS_PMAXSB, + X86_INS_PMAXSD, + X86_INS_PMAXUD, + X86_INS_PMAXUW, + X86_INS_PMINSB, + X86_INS_PMINSD, + X86_INS_PMINUD, + X86_INS_PMINUW, + X86_INS_PMOVSXBD, + X86_INS_PMOVSXBQ, + X86_INS_PMOVSXBW, + X86_INS_PMOVSXDQ, + X86_INS_PMOVSXWD, + X86_INS_PMOVSXWQ, + X86_INS_PMOVZXBD, + X86_INS_PMOVZXBQ, + X86_INS_PMOVZXBW, + X86_INS_PMOVZXDQ, + X86_INS_PMOVZXWD, + X86_INS_PMOVZXWQ, + X86_INS_PMULDQ, + X86_INS_PMULHRW, + X86_INS_PMULLD, + X86_INS_POP, + X86_INS_POPAW, + X86_INS_POPAL, + X86_INS_POPCNT, + X86_INS_POPF, + X86_INS_POPFD, + X86_INS_POPFQ, + X86_INS_PREFETCH, + X86_INS_PREFETCHNTA, + X86_INS_PREFETCHT0, + X86_INS_PREFETCHT1, + X86_INS_PREFETCHT2, + X86_INS_PREFETCHW, + X86_INS_PSHUFD, + X86_INS_PSHUFHW, + X86_INS_PSHUFLW, + X86_INS_PSLLDQ, + X86_INS_PSRLDQ, + X86_INS_PSWAPD, + X86_INS_PTEST, + X86_INS_PUNPCKHQDQ, + X86_INS_PUNPCKLQDQ, + X86_INS_PUSH, + X86_INS_PUSHAW, + X86_INS_PUSHAL, + X86_INS_PUSHF, + X86_INS_PUSHFD, + X86_INS_PUSHFQ, + X86_INS_RCL, + X86_INS_RCPPS, + X86_INS_RCPSS, + X86_INS_RCR, + X86_INS_RDFSBASE, + X86_INS_RDGSBASE, + X86_INS_RDMSR, + X86_INS_RDPMC, + X86_INS_RDRAND, + X86_INS_RDSEED, + X86_INS_RDTSC, + X86_INS_RDTSCP, + X86_INS_ROL, + X86_INS_ROR, + X86_INS_RORX, + X86_INS_ROUNDPD, + X86_INS_ROUNDPS, + X86_INS_ROUNDSD, + X86_INS_ROUNDSS, + X86_INS_RSM, + X86_INS_RSQRTPS, + X86_INS_RSQRTSS, + X86_INS_SAHF, + X86_INS_SAL, + X86_INS_SALC, + X86_INS_SAR, + X86_INS_SARX, + X86_INS_SBB, + X86_INS_SCASB, + X86_INS_SCASD, + X86_INS_SCASQ, + X86_INS_SCASW, + X86_INS_SETAE, + X86_INS_SETA, + X86_INS_SETBE, + X86_INS_SETB, + X86_INS_SETE, + X86_INS_SETGE, + X86_INS_SETG, + X86_INS_SETLE, + X86_INS_SETL, + X86_INS_SETNE, + X86_INS_SETNO, + X86_INS_SETNP, + X86_INS_SETNS, + X86_INS_SETO, + X86_INS_SETP, + X86_INS_SETS, + X86_INS_SFENCE, + X86_INS_SGDT, + X86_INS_SHA1MSG1, + X86_INS_SHA1MSG2, + X86_INS_SHA1NEXTE, + X86_INS_SHA1RNDS4, + X86_INS_SHA256MSG1, + X86_INS_SHA256MSG2, + X86_INS_SHA256RNDS2, + X86_INS_SHL, + X86_INS_SHLD, + X86_INS_SHLX, + X86_INS_SHR, + X86_INS_SHRD, + X86_INS_SHRX, + X86_INS_SHUFPD, + X86_INS_SHUFPS, + X86_INS_SIDT, + X86_INS_FSIN, + X86_INS_SKINIT, + X86_INS_SLDT, + X86_INS_SMSW, + X86_INS_SQRTPD, + X86_INS_SQRTPS, + X86_INS_SQRTSD, + X86_INS_SQRTSS, + X86_INS_FSQRT, + X86_INS_STAC, + X86_INS_STC, + X86_INS_STD, + X86_INS_STGI, + X86_INS_STI, + X86_INS_STMXCSR, + X86_INS_STOSB, + X86_INS_STOSD, + X86_INS_STOSQ, + X86_INS_STOSW, + X86_INS_STR, + X86_INS_FST, + X86_INS_FSTP, + X86_INS_FSTPNCE, + X86_INS_FXCH, + X86_INS_SUBPD, + X86_INS_SUBPS, + X86_INS_FSUBR, + X86_INS_FISUBR, + X86_INS_FSUBRP, + X86_INS_SUBSD, + X86_INS_SUBSS, + X86_INS_FSUB, + X86_INS_FISUB, + X86_INS_FSUBP, + X86_INS_SWAPGS, + X86_INS_SYSCALL, + X86_INS_SYSENTER, + X86_INS_SYSEXIT, + X86_INS_SYSRET, + X86_INS_T1MSKC, + X86_INS_TEST, + X86_INS_UD2, + X86_INS_FTST, + X86_INS_TZCNT, + X86_INS_TZMSK, + X86_INS_FUCOMIP, + X86_INS_FUCOMI, + X86_INS_FUCOMPP, + X86_INS_FUCOMP, + X86_INS_FUCOM, + X86_INS_UD2B, + X86_INS_UNPCKHPD, + X86_INS_UNPCKHPS, + X86_INS_UNPCKLPD, + X86_INS_UNPCKLPS, + X86_INS_VADDPD, + X86_INS_VADDPS, + X86_INS_VADDSD, + X86_INS_VADDSS, + X86_INS_VADDSUBPD, + X86_INS_VADDSUBPS, + X86_INS_VAESDECLAST, + X86_INS_VAESDEC, + X86_INS_VAESENCLAST, + X86_INS_VAESENC, + X86_INS_VAESIMC, + X86_INS_VAESKEYGENASSIST, + X86_INS_VALIGND, + X86_INS_VALIGNQ, + X86_INS_VANDNPD, + X86_INS_VANDNPS, + X86_INS_VANDPD, + X86_INS_VANDPS, + X86_INS_VBLENDMPD, + X86_INS_VBLENDMPS, + X86_INS_VBLENDPD, + X86_INS_VBLENDPS, + X86_INS_VBLENDVPD, + X86_INS_VBLENDVPS, + X86_INS_VBROADCASTF128, + X86_INS_VBROADCASTI32X4, + X86_INS_VBROADCASTI64X4, + X86_INS_VBROADCASTSD, + X86_INS_VBROADCASTSS, + X86_INS_VCOMPRESSPD, + X86_INS_VCOMPRESSPS, + X86_INS_VCVTDQ2PD, + X86_INS_VCVTDQ2PS, + X86_INS_VCVTPD2DQX, + X86_INS_VCVTPD2DQ, + X86_INS_VCVTPD2PSX, + X86_INS_VCVTPD2PS, + X86_INS_VCVTPD2UDQ, + X86_INS_VCVTPH2PS, + X86_INS_VCVTPS2DQ, + X86_INS_VCVTPS2PD, + X86_INS_VCVTPS2PH, + X86_INS_VCVTPS2UDQ, + X86_INS_VCVTSD2SI, + X86_INS_VCVTSD2USI, + X86_INS_VCVTSS2SI, + X86_INS_VCVTSS2USI, + X86_INS_VCVTTPD2DQX, + X86_INS_VCVTTPD2DQ, + X86_INS_VCVTTPD2UDQ, + X86_INS_VCVTTPS2DQ, + X86_INS_VCVTTPS2UDQ, + X86_INS_VCVTUDQ2PD, + X86_INS_VCVTUDQ2PS, + X86_INS_VDIVPD, + X86_INS_VDIVPS, + X86_INS_VDIVSD, + X86_INS_VDIVSS, + X86_INS_VDPPD, + X86_INS_VDPPS, + X86_INS_VERR, + X86_INS_VERW, + X86_INS_VEXP2PD, + X86_INS_VEXP2PS, + X86_INS_VEXPANDPD, + X86_INS_VEXPANDPS, + X86_INS_VEXTRACTF128, + X86_INS_VEXTRACTF32X4, + X86_INS_VEXTRACTF64X4, + X86_INS_VEXTRACTI128, + X86_INS_VEXTRACTI32X4, + X86_INS_VEXTRACTI64X4, + X86_INS_VEXTRACTPS, + X86_INS_VFMADD132PD, + X86_INS_VFMADD132PS, + X86_INS_VFMADDPD, + X86_INS_VFMADD213PD, + X86_INS_VFMADD231PD, + X86_INS_VFMADDPS, + X86_INS_VFMADD213PS, + X86_INS_VFMADD231PS, + X86_INS_VFMADDSD, + X86_INS_VFMADD213SD, + X86_INS_VFMADD132SD, + X86_INS_VFMADD231SD, + X86_INS_VFMADDSS, + X86_INS_VFMADD213SS, + X86_INS_VFMADD132SS, + X86_INS_VFMADD231SS, + X86_INS_VFMADDSUB132PD, + X86_INS_VFMADDSUB132PS, + X86_INS_VFMADDSUBPD, + X86_INS_VFMADDSUB213PD, + X86_INS_VFMADDSUB231PD, + X86_INS_VFMADDSUBPS, + X86_INS_VFMADDSUB213PS, + X86_INS_VFMADDSUB231PS, + X86_INS_VFMSUB132PD, + X86_INS_VFMSUB132PS, + X86_INS_VFMSUBADD132PD, + X86_INS_VFMSUBADD132PS, + X86_INS_VFMSUBADDPD, + X86_INS_VFMSUBADD213PD, + X86_INS_VFMSUBADD231PD, + X86_INS_VFMSUBADDPS, + X86_INS_VFMSUBADD213PS, + X86_INS_VFMSUBADD231PS, + X86_INS_VFMSUBPD, + X86_INS_VFMSUB213PD, + X86_INS_VFMSUB231PD, + X86_INS_VFMSUBPS, + X86_INS_VFMSUB213PS, + X86_INS_VFMSUB231PS, + X86_INS_VFMSUBSD, + X86_INS_VFMSUB213SD, + X86_INS_VFMSUB132SD, + X86_INS_VFMSUB231SD, + X86_INS_VFMSUBSS, + X86_INS_VFMSUB213SS, + X86_INS_VFMSUB132SS, + X86_INS_VFMSUB231SS, + X86_INS_VFNMADD132PD, + X86_INS_VFNMADD132PS, + X86_INS_VFNMADDPD, + X86_INS_VFNMADD213PD, + X86_INS_VFNMADD231PD, + X86_INS_VFNMADDPS, + X86_INS_VFNMADD213PS, + X86_INS_VFNMADD231PS, + X86_INS_VFNMADDSD, + X86_INS_VFNMADD213SD, + X86_INS_VFNMADD132SD, + X86_INS_VFNMADD231SD, + X86_INS_VFNMADDSS, + X86_INS_VFNMADD213SS, + X86_INS_VFNMADD132SS, + X86_INS_VFNMADD231SS, + X86_INS_VFNMSUB132PD, + X86_INS_VFNMSUB132PS, + X86_INS_VFNMSUBPD, + X86_INS_VFNMSUB213PD, + X86_INS_VFNMSUB231PD, + X86_INS_VFNMSUBPS, + X86_INS_VFNMSUB213PS, + X86_INS_VFNMSUB231PS, + X86_INS_VFNMSUBSD, + X86_INS_VFNMSUB213SD, + X86_INS_VFNMSUB132SD, + X86_INS_VFNMSUB231SD, + X86_INS_VFNMSUBSS, + X86_INS_VFNMSUB213SS, + X86_INS_VFNMSUB132SS, + X86_INS_VFNMSUB231SS, + X86_INS_VFRCZPD, + X86_INS_VFRCZPS, + X86_INS_VFRCZSD, + X86_INS_VFRCZSS, + X86_INS_VORPD, + X86_INS_VORPS, + X86_INS_VXORPD, + X86_INS_VXORPS, + X86_INS_VGATHERDPD, + X86_INS_VGATHERDPS, + X86_INS_VGATHERPF0DPD, + X86_INS_VGATHERPF0DPS, + X86_INS_VGATHERPF0QPD, + X86_INS_VGATHERPF0QPS, + X86_INS_VGATHERPF1DPD, + X86_INS_VGATHERPF1DPS, + X86_INS_VGATHERPF1QPD, + X86_INS_VGATHERPF1QPS, + X86_INS_VGATHERQPD, + X86_INS_VGATHERQPS, + X86_INS_VHADDPD, + X86_INS_VHADDPS, + X86_INS_VHSUBPD, + X86_INS_VHSUBPS, + X86_INS_VINSERTF128, + X86_INS_VINSERTF32X4, + X86_INS_VINSERTF32X8, + X86_INS_VINSERTF64X2, + X86_INS_VINSERTF64X4, + X86_INS_VINSERTI128, + X86_INS_VINSERTI32X4, + X86_INS_VINSERTI32X8, + X86_INS_VINSERTI64X2, + X86_INS_VINSERTI64X4, + X86_INS_VINSERTPS, + X86_INS_VLDDQU, + X86_INS_VLDMXCSR, + X86_INS_VMASKMOVDQU, + X86_INS_VMASKMOVPD, + X86_INS_VMASKMOVPS, + X86_INS_VMAXPD, + X86_INS_VMAXPS, + X86_INS_VMAXSD, + X86_INS_VMAXSS, + X86_INS_VMCALL, + X86_INS_VMCLEAR, + X86_INS_VMFUNC, + X86_INS_VMINPD, + X86_INS_VMINPS, + X86_INS_VMINSD, + X86_INS_VMINSS, + X86_INS_VMLAUNCH, + X86_INS_VMLOAD, + X86_INS_VMMCALL, + X86_INS_VMOVQ, + X86_INS_VMOVDDUP, + X86_INS_VMOVD, + X86_INS_VMOVDQA32, + X86_INS_VMOVDQA64, + X86_INS_VMOVDQA, + X86_INS_VMOVDQU16, + X86_INS_VMOVDQU32, + X86_INS_VMOVDQU64, + X86_INS_VMOVDQU8, + X86_INS_VMOVDQU, + X86_INS_VMOVHLPS, + X86_INS_VMOVHPD, + X86_INS_VMOVHPS, + X86_INS_VMOVLHPS, + X86_INS_VMOVLPD, + X86_INS_VMOVLPS, + X86_INS_VMOVMSKPD, + X86_INS_VMOVMSKPS, + X86_INS_VMOVNTDQA, + X86_INS_VMOVNTDQ, + X86_INS_VMOVNTPD, + X86_INS_VMOVNTPS, + X86_INS_VMOVSD, + X86_INS_VMOVSHDUP, + X86_INS_VMOVSLDUP, + X86_INS_VMOVSS, + X86_INS_VMOVUPD, + X86_INS_VMOVUPS, + X86_INS_VMPSADBW, + X86_INS_VMPTRLD, + X86_INS_VMPTRST, + X86_INS_VMREAD, + X86_INS_VMRESUME, + X86_INS_VMRUN, + X86_INS_VMSAVE, + X86_INS_VMULPD, + X86_INS_VMULPS, + X86_INS_VMULSD, + X86_INS_VMULSS, + X86_INS_VMWRITE, + X86_INS_VMXOFF, + X86_INS_VMXON, + X86_INS_VPABSB, + X86_INS_VPABSD, + X86_INS_VPABSQ, + X86_INS_VPABSW, + X86_INS_VPACKSSDW, + X86_INS_VPACKSSWB, + X86_INS_VPACKUSDW, + X86_INS_VPACKUSWB, + X86_INS_VPADDB, + X86_INS_VPADDD, + X86_INS_VPADDQ, + X86_INS_VPADDSB, + X86_INS_VPADDSW, + X86_INS_VPADDUSB, + X86_INS_VPADDUSW, + X86_INS_VPADDW, + X86_INS_VPALIGNR, + X86_INS_VPANDD, + X86_INS_VPANDND, + X86_INS_VPANDNQ, + X86_INS_VPANDN, + X86_INS_VPANDQ, + X86_INS_VPAND, + X86_INS_VPAVGB, + X86_INS_VPAVGW, + X86_INS_VPBLENDD, + X86_INS_VPBLENDMB, + X86_INS_VPBLENDMD, + X86_INS_VPBLENDMQ, + X86_INS_VPBLENDMW, + X86_INS_VPBLENDVB, + X86_INS_VPBLENDW, + X86_INS_VPBROADCASTB, + X86_INS_VPBROADCASTD, + X86_INS_VPBROADCASTMB2Q, + X86_INS_VPBROADCASTMW2D, + X86_INS_VPBROADCASTQ, + X86_INS_VPBROADCASTW, + X86_INS_VPCLMULQDQ, + X86_INS_VPCMOV, + X86_INS_VPCMPB, + X86_INS_VPCMPD, + X86_INS_VPCMPEQB, + X86_INS_VPCMPEQD, + X86_INS_VPCMPEQQ, + X86_INS_VPCMPEQW, + X86_INS_VPCMPESTRI, + X86_INS_VPCMPESTRM, + X86_INS_VPCMPGTB, + X86_INS_VPCMPGTD, + X86_INS_VPCMPGTQ, + X86_INS_VPCMPGTW, + X86_INS_VPCMPISTRI, + X86_INS_VPCMPISTRM, + X86_INS_VPCMPQ, + X86_INS_VPCMPUB, + X86_INS_VPCMPUD, + X86_INS_VPCMPUQ, + X86_INS_VPCMPUW, + X86_INS_VPCMPW, + X86_INS_VPCOMB, + X86_INS_VPCOMD, + X86_INS_VPCOMPRESSD, + X86_INS_VPCOMPRESSQ, + X86_INS_VPCOMQ, + X86_INS_VPCOMUB, + X86_INS_VPCOMUD, + X86_INS_VPCOMUQ, + X86_INS_VPCOMUW, + X86_INS_VPCOMW, + X86_INS_VPCONFLICTD, + X86_INS_VPCONFLICTQ, + X86_INS_VPERM2F128, + X86_INS_VPERM2I128, + X86_INS_VPERMD, + X86_INS_VPERMI2D, + X86_INS_VPERMI2PD, + X86_INS_VPERMI2PS, + X86_INS_VPERMI2Q, + X86_INS_VPERMIL2PD, + X86_INS_VPERMIL2PS, + X86_INS_VPERMILPD, + X86_INS_VPERMILPS, + X86_INS_VPERMPD, + X86_INS_VPERMPS, + X86_INS_VPERMQ, + X86_INS_VPERMT2D, + X86_INS_VPERMT2PD, + X86_INS_VPERMT2PS, + X86_INS_VPERMT2Q, + X86_INS_VPEXPANDD, + X86_INS_VPEXPANDQ, + X86_INS_VPEXTRB, + X86_INS_VPEXTRD, + X86_INS_VPEXTRQ, + X86_INS_VPEXTRW, + X86_INS_VPGATHERDD, + X86_INS_VPGATHERDQ, + X86_INS_VPGATHERQD, + X86_INS_VPGATHERQQ, + X86_INS_VPHADDBD, + X86_INS_VPHADDBQ, + X86_INS_VPHADDBW, + X86_INS_VPHADDDQ, + X86_INS_VPHADDD, + X86_INS_VPHADDSW, + X86_INS_VPHADDUBD, + X86_INS_VPHADDUBQ, + X86_INS_VPHADDUBW, + X86_INS_VPHADDUDQ, + X86_INS_VPHADDUWD, + X86_INS_VPHADDUWQ, + X86_INS_VPHADDWD, + X86_INS_VPHADDWQ, + X86_INS_VPHADDW, + X86_INS_VPHMINPOSUW, + X86_INS_VPHSUBBW, + X86_INS_VPHSUBDQ, + X86_INS_VPHSUBD, + X86_INS_VPHSUBSW, + X86_INS_VPHSUBWD, + X86_INS_VPHSUBW, + X86_INS_VPINSRB, + X86_INS_VPINSRD, + X86_INS_VPINSRQ, + X86_INS_VPINSRW, + X86_INS_VPLZCNTD, + X86_INS_VPLZCNTQ, + X86_INS_VPMACSDD, + X86_INS_VPMACSDQH, + X86_INS_VPMACSDQL, + X86_INS_VPMACSSDD, + X86_INS_VPMACSSDQH, + X86_INS_VPMACSSDQL, + X86_INS_VPMACSSWD, + X86_INS_VPMACSSWW, + X86_INS_VPMACSWD, + X86_INS_VPMACSWW, + X86_INS_VPMADCSSWD, + X86_INS_VPMADCSWD, + X86_INS_VPMADDUBSW, + X86_INS_VPMADDWD, + X86_INS_VPMASKMOVD, + X86_INS_VPMASKMOVQ, + X86_INS_VPMAXSB, + X86_INS_VPMAXSD, + X86_INS_VPMAXSQ, + X86_INS_VPMAXSW, + X86_INS_VPMAXUB, + X86_INS_VPMAXUD, + X86_INS_VPMAXUQ, + X86_INS_VPMAXUW, + X86_INS_VPMINSB, + X86_INS_VPMINSD, + X86_INS_VPMINSQ, + X86_INS_VPMINSW, + X86_INS_VPMINUB, + X86_INS_VPMINUD, + X86_INS_VPMINUQ, + X86_INS_VPMINUW, + X86_INS_VPMOVDB, + X86_INS_VPMOVDW, + X86_INS_VPMOVM2B, + X86_INS_VPMOVM2D, + X86_INS_VPMOVM2Q, + X86_INS_VPMOVM2W, + X86_INS_VPMOVMSKB, + X86_INS_VPMOVQB, + X86_INS_VPMOVQD, + X86_INS_VPMOVQW, + X86_INS_VPMOVSDB, + X86_INS_VPMOVSDW, + X86_INS_VPMOVSQB, + X86_INS_VPMOVSQD, + X86_INS_VPMOVSQW, + X86_INS_VPMOVSXBD, + X86_INS_VPMOVSXBQ, + X86_INS_VPMOVSXBW, + X86_INS_VPMOVSXDQ, + X86_INS_VPMOVSXWD, + X86_INS_VPMOVSXWQ, + X86_INS_VPMOVUSDB, + X86_INS_VPMOVUSDW, + X86_INS_VPMOVUSQB, + X86_INS_VPMOVUSQD, + X86_INS_VPMOVUSQW, + X86_INS_VPMOVZXBD, + X86_INS_VPMOVZXBQ, + X86_INS_VPMOVZXBW, + X86_INS_VPMOVZXDQ, + X86_INS_VPMOVZXWD, + X86_INS_VPMOVZXWQ, + X86_INS_VPMULDQ, + X86_INS_VPMULHRSW, + X86_INS_VPMULHUW, + X86_INS_VPMULHW, + X86_INS_VPMULLD, + X86_INS_VPMULLQ, + X86_INS_VPMULLW, + X86_INS_VPMULUDQ, + X86_INS_VPORD, + X86_INS_VPORQ, + X86_INS_VPOR, + X86_INS_VPPERM, + X86_INS_VPROTB, + X86_INS_VPROTD, + X86_INS_VPROTQ, + X86_INS_VPROTW, + X86_INS_VPSADBW, + X86_INS_VPSCATTERDD, + X86_INS_VPSCATTERDQ, + X86_INS_VPSCATTERQD, + X86_INS_VPSCATTERQQ, + X86_INS_VPSHAB, + X86_INS_VPSHAD, + X86_INS_VPSHAQ, + X86_INS_VPSHAW, + X86_INS_VPSHLB, + X86_INS_VPSHLD, + X86_INS_VPSHLQ, + X86_INS_VPSHLW, + X86_INS_VPSHUFB, + X86_INS_VPSHUFD, + X86_INS_VPSHUFHW, + X86_INS_VPSHUFLW, + X86_INS_VPSIGNB, + X86_INS_VPSIGND, + X86_INS_VPSIGNW, + X86_INS_VPSLLDQ, + X86_INS_VPSLLD, + X86_INS_VPSLLQ, + X86_INS_VPSLLVD, + X86_INS_VPSLLVQ, + X86_INS_VPSLLW, + X86_INS_VPSRAD, + X86_INS_VPSRAQ, + X86_INS_VPSRAVD, + X86_INS_VPSRAVQ, + X86_INS_VPSRAW, + X86_INS_VPSRLDQ, + X86_INS_VPSRLD, + X86_INS_VPSRLQ, + X86_INS_VPSRLVD, + X86_INS_VPSRLVQ, + X86_INS_VPSRLW, + X86_INS_VPSUBB, + X86_INS_VPSUBD, + X86_INS_VPSUBQ, + X86_INS_VPSUBSB, + X86_INS_VPSUBSW, + X86_INS_VPSUBUSB, + X86_INS_VPSUBUSW, + X86_INS_VPSUBW, + X86_INS_VPTESTMD, + X86_INS_VPTESTMQ, + X86_INS_VPTESTNMD, + X86_INS_VPTESTNMQ, + X86_INS_VPTEST, + X86_INS_VPUNPCKHBW, + X86_INS_VPUNPCKHDQ, + X86_INS_VPUNPCKHQDQ, + X86_INS_VPUNPCKHWD, + X86_INS_VPUNPCKLBW, + X86_INS_VPUNPCKLDQ, + X86_INS_VPUNPCKLQDQ, + X86_INS_VPUNPCKLWD, + X86_INS_VPXORD, + X86_INS_VPXORQ, + X86_INS_VPXOR, + X86_INS_VRCP14PD, + X86_INS_VRCP14PS, + X86_INS_VRCP14SD, + X86_INS_VRCP14SS, + X86_INS_VRCP28PD, + X86_INS_VRCP28PS, + X86_INS_VRCP28SD, + X86_INS_VRCP28SS, + X86_INS_VRCPPS, + X86_INS_VRCPSS, + X86_INS_VRNDSCALEPD, + X86_INS_VRNDSCALEPS, + X86_INS_VRNDSCALESD, + X86_INS_VRNDSCALESS, + X86_INS_VROUNDPD, + X86_INS_VROUNDPS, + X86_INS_VROUNDSD, + X86_INS_VROUNDSS, + X86_INS_VRSQRT14PD, + X86_INS_VRSQRT14PS, + X86_INS_VRSQRT14SD, + X86_INS_VRSQRT14SS, + X86_INS_VRSQRT28PD, + X86_INS_VRSQRT28PS, + X86_INS_VRSQRT28SD, + X86_INS_VRSQRT28SS, + X86_INS_VRSQRTPS, + X86_INS_VRSQRTSS, + X86_INS_VSCATTERDPD, + X86_INS_VSCATTERDPS, + X86_INS_VSCATTERPF0DPD, + X86_INS_VSCATTERPF0DPS, + X86_INS_VSCATTERPF0QPD, + X86_INS_VSCATTERPF0QPS, + X86_INS_VSCATTERPF1DPD, + X86_INS_VSCATTERPF1DPS, + X86_INS_VSCATTERPF1QPD, + X86_INS_VSCATTERPF1QPS, + X86_INS_VSCATTERQPD, + X86_INS_VSCATTERQPS, + X86_INS_VSHUFPD, + X86_INS_VSHUFPS, + X86_INS_VSQRTPD, + X86_INS_VSQRTPS, + X86_INS_VSQRTSD, + X86_INS_VSQRTSS, + X86_INS_VSTMXCSR, + X86_INS_VSUBPD, + X86_INS_VSUBPS, + X86_INS_VSUBSD, + X86_INS_VSUBSS, + X86_INS_VTESTPD, + X86_INS_VTESTPS, + X86_INS_VUNPCKHPD, + X86_INS_VUNPCKHPS, + X86_INS_VUNPCKLPD, + X86_INS_VUNPCKLPS, + X86_INS_VZEROALL, + X86_INS_VZEROUPPER, + X86_INS_WAIT, + X86_INS_WBINVD, + X86_INS_WRFSBASE, + X86_INS_WRGSBASE, + X86_INS_WRMSR, + X86_INS_XABORT, + X86_INS_XACQUIRE, + X86_INS_XBEGIN, + X86_INS_XCHG, + X86_INS_XCRYPTCBC, + X86_INS_XCRYPTCFB, + X86_INS_XCRYPTCTR, + X86_INS_XCRYPTECB, + X86_INS_XCRYPTOFB, + X86_INS_XEND, + X86_INS_XGETBV, + X86_INS_XLATB, + X86_INS_XRELEASE, + X86_INS_XRSTOR, + X86_INS_XRSTOR64, + X86_INS_XRSTORS, + X86_INS_XRSTORS64, + X86_INS_XSAVE, + X86_INS_XSAVE64, + X86_INS_XSAVEC, + X86_INS_XSAVEC64, + X86_INS_XSAVEOPT, + X86_INS_XSAVEOPT64, + X86_INS_XSAVES, + X86_INS_XSAVES64, + X86_INS_XSETBV, + X86_INS_XSHA1, + X86_INS_XSHA256, + X86_INS_XSTORE, + X86_INS_XTEST, + X86_INS_FDISI8087_NOP, + X86_INS_FENI8087_NOP, + + // pseudo instructions + X86_INS_CMPSS, + X86_INS_CMPEQSS, + X86_INS_CMPLTSS, + X86_INS_CMPLESS, + X86_INS_CMPUNORDSS, + X86_INS_CMPNEQSS, + X86_INS_CMPNLTSS, + X86_INS_CMPNLESS, + X86_INS_CMPORDSS, + + X86_INS_CMPSD, + X86_INS_CMPEQSD, + X86_INS_CMPLTSD, + X86_INS_CMPLESD, + X86_INS_CMPUNORDSD, + X86_INS_CMPNEQSD, + X86_INS_CMPNLTSD, + X86_INS_CMPNLESD, + X86_INS_CMPORDSD, + + X86_INS_CMPPS, + X86_INS_CMPEQPS, + X86_INS_CMPLTPS, + X86_INS_CMPLEPS, + X86_INS_CMPUNORDPS, + X86_INS_CMPNEQPS, + X86_INS_CMPNLTPS, + X86_INS_CMPNLEPS, + X86_INS_CMPORDPS, + + X86_INS_CMPPD, + X86_INS_CMPEQPD, + X86_INS_CMPLTPD, + X86_INS_CMPLEPD, + X86_INS_CMPUNORDPD, + X86_INS_CMPNEQPD, + X86_INS_CMPNLTPD, + X86_INS_CMPNLEPD, + X86_INS_CMPORDPD, + + X86_INS_VCMPSS, + X86_INS_VCMPEQSS, + X86_INS_VCMPLTSS, + X86_INS_VCMPLESS, + X86_INS_VCMPUNORDSS, + X86_INS_VCMPNEQSS, + X86_INS_VCMPNLTSS, + X86_INS_VCMPNLESS, + X86_INS_VCMPORDSS, + X86_INS_VCMPEQ_UQSS, + X86_INS_VCMPNGESS, + X86_INS_VCMPNGTSS, + X86_INS_VCMPFALSESS, + X86_INS_VCMPNEQ_OQSS, + X86_INS_VCMPGESS, + X86_INS_VCMPGTSS, + X86_INS_VCMPTRUESS, + X86_INS_VCMPEQ_OSSS, + X86_INS_VCMPLT_OQSS, + X86_INS_VCMPLE_OQSS, + X86_INS_VCMPUNORD_SSS, + X86_INS_VCMPNEQ_USSS, + X86_INS_VCMPNLT_UQSS, + X86_INS_VCMPNLE_UQSS, + X86_INS_VCMPORD_SSS, + X86_INS_VCMPEQ_USSS, + X86_INS_VCMPNGE_UQSS, + X86_INS_VCMPNGT_UQSS, + X86_INS_VCMPFALSE_OSSS, + X86_INS_VCMPNEQ_OSSS, + X86_INS_VCMPGE_OQSS, + X86_INS_VCMPGT_OQSS, + X86_INS_VCMPTRUE_USSS, + + X86_INS_VCMPSD, + X86_INS_VCMPEQSD, + X86_INS_VCMPLTSD, + X86_INS_VCMPLESD, + X86_INS_VCMPUNORDSD, + X86_INS_VCMPNEQSD, + X86_INS_VCMPNLTSD, + X86_INS_VCMPNLESD, + X86_INS_VCMPORDSD, + X86_INS_VCMPEQ_UQSD, + X86_INS_VCMPNGESD, + X86_INS_VCMPNGTSD, + X86_INS_VCMPFALSESD, + X86_INS_VCMPNEQ_OQSD, + X86_INS_VCMPGESD, + X86_INS_VCMPGTSD, + X86_INS_VCMPTRUESD, + X86_INS_VCMPEQ_OSSD, + X86_INS_VCMPLT_OQSD, + X86_INS_VCMPLE_OQSD, + X86_INS_VCMPUNORD_SSD, + X86_INS_VCMPNEQ_USSD, + X86_INS_VCMPNLT_UQSD, + X86_INS_VCMPNLE_UQSD, + X86_INS_VCMPORD_SSD, + X86_INS_VCMPEQ_USSD, + X86_INS_VCMPNGE_UQSD, + X86_INS_VCMPNGT_UQSD, + X86_INS_VCMPFALSE_OSSD, + X86_INS_VCMPNEQ_OSSD, + X86_INS_VCMPGE_OQSD, + X86_INS_VCMPGT_OQSD, + X86_INS_VCMPTRUE_USSD, + + X86_INS_VCMPPS, + X86_INS_VCMPEQPS, + X86_INS_VCMPLTPS, + X86_INS_VCMPLEPS, + X86_INS_VCMPUNORDPS, + X86_INS_VCMPNEQPS, + X86_INS_VCMPNLTPS, + X86_INS_VCMPNLEPS, + X86_INS_VCMPORDPS, + X86_INS_VCMPEQ_UQPS, + X86_INS_VCMPNGEPS, + X86_INS_VCMPNGTPS, + X86_INS_VCMPFALSEPS, + X86_INS_VCMPNEQ_OQPS, + X86_INS_VCMPGEPS, + X86_INS_VCMPGTPS, + X86_INS_VCMPTRUEPS, + X86_INS_VCMPEQ_OSPS, + X86_INS_VCMPLT_OQPS, + X86_INS_VCMPLE_OQPS, + X86_INS_VCMPUNORD_SPS, + X86_INS_VCMPNEQ_USPS, + X86_INS_VCMPNLT_UQPS, + X86_INS_VCMPNLE_UQPS, + X86_INS_VCMPORD_SPS, + X86_INS_VCMPEQ_USPS, + X86_INS_VCMPNGE_UQPS, + X86_INS_VCMPNGT_UQPS, + X86_INS_VCMPFALSE_OSPS, + X86_INS_VCMPNEQ_OSPS, + X86_INS_VCMPGE_OQPS, + X86_INS_VCMPGT_OQPS, + X86_INS_VCMPTRUE_USPS, + + X86_INS_VCMPPD, + X86_INS_VCMPEQPD, + X86_INS_VCMPLTPD, + X86_INS_VCMPLEPD, + X86_INS_VCMPUNORDPD, + X86_INS_VCMPNEQPD, + X86_INS_VCMPNLTPD, + X86_INS_VCMPNLEPD, + X86_INS_VCMPORDPD, + X86_INS_VCMPEQ_UQPD, + X86_INS_VCMPNGEPD, + X86_INS_VCMPNGTPD, + X86_INS_VCMPFALSEPD, + X86_INS_VCMPNEQ_OQPD, + X86_INS_VCMPGEPD, + X86_INS_VCMPGTPD, + X86_INS_VCMPTRUEPD, + X86_INS_VCMPEQ_OSPD, + X86_INS_VCMPLT_OQPD, + X86_INS_VCMPLE_OQPD, + X86_INS_VCMPUNORD_SPD, + X86_INS_VCMPNEQ_USPD, + X86_INS_VCMPNLT_UQPD, + X86_INS_VCMPNLE_UQPD, + X86_INS_VCMPORD_SPD, + X86_INS_VCMPEQ_USPD, + X86_INS_VCMPNGE_UQPD, + X86_INS_VCMPNGT_UQPD, + X86_INS_VCMPFALSE_OSPD, + X86_INS_VCMPNEQ_OSPD, + X86_INS_VCMPGE_OQPD, + X86_INS_VCMPGT_OQPD, + X86_INS_VCMPTRUE_USPD, + + X86_INS_UD0, + X86_INS_ENDBR32, + X86_INS_ENDBR64, + + X86_INS_ENDING, // mark the end of the list of insn +} x86_insn; + +/// Group of X86 instructions +typedef enum x86_insn_group { + X86_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + X86_GRP_JUMP, ///< = CS_GRP_JUMP + // all call instructions + X86_GRP_CALL, ///< = CS_GRP_CALL + // all return instructions + X86_GRP_RET, ///< = CS_GRP_RET + // all interrupt instructions (int+syscall) + X86_GRP_INT, ///< = CS_GRP_INT + // all interrupt return instructions + X86_GRP_IRET, ///< = CS_GRP_IRET + // all privileged instructions + X86_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE + // all relative branching instructions + X86_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + X86_GRP_VM = 128, ///< all virtualization instructions (VT-x + AMD-V) + X86_GRP_3DNOW, + X86_GRP_AES, + X86_GRP_ADX, + X86_GRP_AVX, + X86_GRP_AVX2, + X86_GRP_AVX512, + X86_GRP_BMI, + X86_GRP_BMI2, + X86_GRP_CMOV, + X86_GRP_F16C, + X86_GRP_FMA, + X86_GRP_FMA4, + X86_GRP_FSGSBASE, + X86_GRP_HLE, + X86_GRP_MMX, + X86_GRP_MODE32, + X86_GRP_MODE64, + X86_GRP_RTM, + X86_GRP_SHA, + X86_GRP_SSE1, + X86_GRP_SSE2, + X86_GRP_SSE3, + X86_GRP_SSE41, + X86_GRP_SSE42, + X86_GRP_SSE4A, + X86_GRP_SSSE3, + X86_GRP_PCLMUL, + X86_GRP_XOP, + X86_GRP_CDI, + X86_GRP_ERI, + X86_GRP_TBM, + X86_GRP_16BITMODE, + X86_GRP_NOT64BITMODE, + X86_GRP_SGX, + X86_GRP_DQI, + X86_GRP_BWI, + X86_GRP_PFI, + X86_GRP_VLX, + X86_GRP_SMAP, + X86_GRP_NOVLX, + X86_GRP_FPU, + + X86_GRP_ENDING +} x86_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/capstone/xcore.h b/white_patch_detect/capstone-master/include/capstone/xcore.h new file mode 100644 index 0000000..6db1f24 --- /dev/null +++ b/white_patch_detect/capstone-master/include/capstone/xcore.h @@ -0,0 +1,235 @@ +#ifndef CAPSTONE_XCORE_H +#define CAPSTONE_XCORE_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2014-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "platform.h" + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +/// Operand type for instruction's operands +typedef enum xcore_op_type { + XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + XCORE_OP_REG, ///< = CS_OP_REG (Register operand). + XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand). +} xcore_op_type; + +/// XCore registers +typedef enum xcore_reg { + XCORE_REG_INVALID = 0, + + XCORE_REG_CP, + XCORE_REG_DP, + XCORE_REG_LR, + XCORE_REG_SP, + XCORE_REG_R0, + XCORE_REG_R1, + XCORE_REG_R2, + XCORE_REG_R3, + XCORE_REG_R4, + XCORE_REG_R5, + XCORE_REG_R6, + XCORE_REG_R7, + XCORE_REG_R8, + XCORE_REG_R9, + XCORE_REG_R10, + XCORE_REG_R11, + + // pseudo registers + XCORE_REG_PC, ///< pc + + // internal thread registers + // see The-XMOS-XS1-Architecture(X7879A).pdf + XCORE_REG_SCP, ///< save pc + XCORE_REG_SSR, //< save status + XCORE_REG_ET, //< exception type + XCORE_REG_ED, //< exception data + XCORE_REG_SED, //< save exception data + XCORE_REG_KEP, //< kernel entry pointer + XCORE_REG_KSP, //< kernel stack pointer + XCORE_REG_ID, //< thread ID + + XCORE_REG_ENDING, // <-- mark the end of the list of registers +} xcore_reg; + +/// Instruction's operand referring to memory +/// This is associated with XCORE_OP_MEM operand type above +typedef struct xcore_op_mem { + uint8_t base; ///< base register, can be safely interpreted as + ///< a value of type `xcore_reg`, but it is only + ///< one byte wide + uint8_t index; ///< index register, same conditions apply here + int32_t disp; ///< displacement/offset value + int direct; ///< +1: forward, -1: backward +} xcore_op_mem; + +/// Instruction operand +typedef struct cs_xcore_op { + xcore_op_type type; ///< operand type + union { + xcore_reg reg; ///< register value for REG operand + int32_t imm; ///< immediate value for IMM operand + xcore_op_mem mem; ///< base/disp value for MEM operand + }; +} cs_xcore_op; + +/// Instruction structure +typedef struct cs_xcore { + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_xcore_op operands[8]; ///< operands for this instruction. +} cs_xcore; + +/// XCore instruction +typedef enum xcore_insn { + XCORE_INS_INVALID = 0, + + XCORE_INS_ADD, + XCORE_INS_ANDNOT, + XCORE_INS_AND, + XCORE_INS_ASHR, + XCORE_INS_BAU, + XCORE_INS_BITREV, + XCORE_INS_BLA, + XCORE_INS_BLAT, + XCORE_INS_BL, + XCORE_INS_BF, + XCORE_INS_BT, + XCORE_INS_BU, + XCORE_INS_BRU, + XCORE_INS_BYTEREV, + XCORE_INS_CHKCT, + XCORE_INS_CLRE, + XCORE_INS_CLRPT, + XCORE_INS_CLRSR, + XCORE_INS_CLZ, + XCORE_INS_CRC8, + XCORE_INS_CRC32, + XCORE_INS_DCALL, + XCORE_INS_DENTSP, + XCORE_INS_DGETREG, + XCORE_INS_DIVS, + XCORE_INS_DIVU, + XCORE_INS_DRESTSP, + XCORE_INS_DRET, + XCORE_INS_ECALLF, + XCORE_INS_ECALLT, + XCORE_INS_EDU, + XCORE_INS_EEF, + XCORE_INS_EET, + XCORE_INS_EEU, + XCORE_INS_ENDIN, + XCORE_INS_ENTSP, + XCORE_INS_EQ, + XCORE_INS_EXTDP, + XCORE_INS_EXTSP, + XCORE_INS_FREER, + XCORE_INS_FREET, + XCORE_INS_GETD, + XCORE_INS_GET, + XCORE_INS_GETN, + XCORE_INS_GETR, + XCORE_INS_GETSR, + XCORE_INS_GETST, + XCORE_INS_GETTS, + XCORE_INS_INCT, + XCORE_INS_INIT, + XCORE_INS_INPW, + XCORE_INS_INSHR, + XCORE_INS_INT, + XCORE_INS_IN, + XCORE_INS_KCALL, + XCORE_INS_KENTSP, + XCORE_INS_KRESTSP, + XCORE_INS_KRET, + XCORE_INS_LADD, + XCORE_INS_LD16S, + XCORE_INS_LD8U, + XCORE_INS_LDA16, + XCORE_INS_LDAP, + XCORE_INS_LDAW, + XCORE_INS_LDC, + XCORE_INS_LDW, + XCORE_INS_LDIVU, + XCORE_INS_LMUL, + XCORE_INS_LSS, + XCORE_INS_LSUB, + XCORE_INS_LSU, + XCORE_INS_MACCS, + XCORE_INS_MACCU, + XCORE_INS_MJOIN, + XCORE_INS_MKMSK, + XCORE_INS_MSYNC, + XCORE_INS_MUL, + XCORE_INS_NEG, + XCORE_INS_NOT, + XCORE_INS_OR, + XCORE_INS_OUTCT, + XCORE_INS_OUTPW, + XCORE_INS_OUTSHR, + XCORE_INS_OUTT, + XCORE_INS_OUT, + XCORE_INS_PEEK, + XCORE_INS_REMS, + XCORE_INS_REMU, + XCORE_INS_RETSP, + XCORE_INS_SETCLK, + XCORE_INS_SET, + XCORE_INS_SETC, + XCORE_INS_SETD, + XCORE_INS_SETEV, + XCORE_INS_SETN, + XCORE_INS_SETPSC, + XCORE_INS_SETPT, + XCORE_INS_SETRDY, + XCORE_INS_SETSR, + XCORE_INS_SETTW, + XCORE_INS_SETV, + XCORE_INS_SEXT, + XCORE_INS_SHL, + XCORE_INS_SHR, + XCORE_INS_SSYNC, + XCORE_INS_ST16, + XCORE_INS_ST8, + XCORE_INS_STW, + XCORE_INS_SUB, + XCORE_INS_SYNCR, + XCORE_INS_TESTCT, + XCORE_INS_TESTLCL, + XCORE_INS_TESTWCT, + XCORE_INS_TSETMR, + XCORE_INS_START, + XCORE_INS_WAITEF, + XCORE_INS_WAITET, + XCORE_INS_WAITEU, + XCORE_INS_XOR, + XCORE_INS_ZEXT, + + XCORE_INS_ENDING, // <-- mark the end of the list of instructions +} xcore_insn; + +/// Group of XCore instructions +typedef enum xcore_insn_group { + XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + XCORE_GRP_JUMP, ///< = CS_GRP_JUMP + + XCORE_GRP_ENDING, // <-- mark the end of the list of groups +} xcore_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/platform.h b/white_patch_detect/capstone-master/include/platform.h new file mode 100644 index 0000000..b0d1a2d --- /dev/null +++ b/white_patch_detect/capstone-master/include/platform.h @@ -0,0 +1,110 @@ +/* Capstone Disassembly Engine */ +/* By Axel Souchet & Nguyen Anh Quynh, 2014 */ + +#ifndef CAPSTONE_PLATFORM_H +#define CAPSTONE_PLATFORM_H + +// handle C99 issue (for pre-2013 VisualStudio) +#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) +// MSVC + +// stdbool.h +#if (_MSC_VER < 1800) || defined(_KERNEL_MODE) +// this system does not have stdbool.h +#ifndef __cplusplus +typedef unsigned char bool; +#define false 0 +#define true 1 +#endif + +#else +// VisualStudio 2013+ -> C99 is supported +#include +#endif + +#else +// not MSVC -> C99 is supported +#include +#endif + + +// handle C99 issue (for pre-2013 VisualStudio) +#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) +// this system does not have inttypes.h + +#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) +// this system does not have stdint.h +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef signed long long int64_t; +typedef unsigned long long uint64_t; + +#define INT8_MIN (-127i8 - 1) +#define INT16_MIN (-32767i16 - 1) +#define INT32_MIN (-2147483647i32 - 1) +#define INT64_MIN (-9223372036854775807i64 - 1) +#define INT8_MAX 127i8 +#define INT16_MAX 32767i16 +#define INT32_MAX 2147483647i32 +#define INT64_MAX 9223372036854775807i64 +#define UINT8_MAX 0xffui8 +#define UINT16_MAX 0xffffui16 +#define UINT32_MAX 0xffffffffui32 +#define UINT64_MAX 0xffffffffffffffffui64 +#endif + +#define __PRI_8_LENGTH_MODIFIER__ "hh" +#define __PRI_64_LENGTH_MODIFIER__ "ll" + +#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" +#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" +#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" +#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" +#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" +#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" + +#define PRId16 "hd" +#define PRIi16 "hi" +#define PRIo16 "ho" +#define PRIu16 "hu" +#define PRIx16 "hx" +#define PRIX16 "hX" + +#if defined(_MSC_VER) && _MSC_VER <= 1700 +#define PRId32 "ld" +#define PRIi32 "li" +#define PRIo32 "lo" +#define PRIu32 "lu" +#define PRIx32 "lx" +#define PRIX32 "lX" +#else // OSX +#define PRId32 "d" +#define PRIi32 "i" +#define PRIo32 "o" +#define PRIu32 "u" +#define PRIx32 "x" +#define PRIX32 "X" +#endif + +#if defined(_MSC_VER) && _MSC_VER <= 1700 +// redefine functions from inttypes.h used in cstool +#define strtoull _strtoui64 +#endif + +#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" +#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" +#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" +#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" +#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" +#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" + +#else +// this system has inttypes.h by default +#include +#endif + +#endif diff --git a/white_patch_detect/capstone-master/include/windowsce/intrin.h b/white_patch_detect/capstone-master/include/windowsce/intrin.h new file mode 100644 index 0000000..fde4bde --- /dev/null +++ b/white_patch_detect/capstone-master/include/windowsce/intrin.h @@ -0,0 +1,12 @@ + +#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN) +#define _STDINT + +#ifdef _M_ARM +#include +#if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) +#include +#endif +#endif // _M_ARM + +#endif diff --git a/white_patch_detect/capstone-master/include/windowsce/stdint.h b/white_patch_detect/capstone-master/include/windowsce/stdint.h new file mode 100644 index 0000000..014a163 --- /dev/null +++ b/white_patch_detect/capstone-master/include/windowsce/stdint.h @@ -0,0 +1,133 @@ + +#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT) +#define _STDINT + +typedef __int8 + int8_t, + int_least8_t; + +typedef __int16 + int16_t, + int_least16_t; + +typedef __int32 + int32_t, + int_least32_t, + int_fast8_t, + int_fast16_t, + int_fast32_t; + +typedef __int64 + int64_t, + intmax_t, + int_least64_t, + int_fast64_t; + +typedef unsigned __int8 + uint8_t, + uint_least8_t; + +typedef unsigned __int16 + uint16_t, + uint_least16_t; + +typedef unsigned __int32 + uint32_t, + uint_least32_t, + uint_fast8_t, + uint_fast16_t, + uint_fast32_t; + +typedef unsigned __int64 + uint64_t, + uintmax_t, + uint_least64_t, + uint_fast64_t; + +#ifndef _INTPTR_T_DEFINED +#define _INTPTR_T_DEFINED +typedef __int32 intptr_t; +#endif + +#ifndef _UINTPTR_T_DEFINED +#define _UINTPTR_T_DEFINED +typedef unsigned __int32 uintptr_t; +#endif + +#define INT8_MIN (-127i8 - 1) +#define INT16_MIN (-32767i16 - 1) +#define INT32_MIN (-2147483647i32 - 1) +#define INT64_MIN (-9223372036854775807i64 - 1) +#define INT8_MAX 127i8 +#define INT16_MAX 32767i16 +#define INT32_MAX 2147483647i32 +#define INT64_MAX 9223372036854775807i64 +#define UINT8_MAX 0xffui8 +#define UINT16_MAX 0xffffui16 +#define UINT32_MAX 0xffffffffui32 +#define UINT64_MAX 0xffffffffffffffffui64 + +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +#define INT_FAST8_MIN INT8_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN +#define INT_FAST8_MAX INT8_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX +#define UINT_FAST8_MAX UINT8_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +#define INTPTR_MIN INT32_MIN +#define INTPTR_MAX INT32_MAX +#define UINTPTR_MAX UINT32_MAX + +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +#define PTRDIFF_MIN INTPTR_MIN +#define PTRDIFF_MAX INTPTR_MAX + +#ifndef SIZE_MAX +#define SIZE_MAX UINTPTR_MAX +#endif + +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +#define WCHAR_MIN 0x0000 +#define WCHAR_MAX 0xffff + +#define WINT_MIN 0x0000 +#define WINT_MAX 0xffff + +#define INT8_C(x) (x) +#define INT16_C(x) (x) +#define INT32_C(x) (x) +#define INT64_C(x) (x ## LL) + +#define UINT8_C(x) (x) +#define UINT16_C(x) (x) +#define UINT32_C(x) (x ## U) +#define UINT64_C(x) (x ## ULL) + +#define INTMAX_C(x) INT64_C(x) +#define UINTMAX_C(x) UINT64_C(x) + +#endif diff --git a/white_patch_detect/capstone-master/make.sh b/white_patch_detect/capstone-master/make.sh new file mode 100644 index 0000000..d359bfc --- /dev/null +++ b/white_patch_detect/capstone-master/make.sh @@ -0,0 +1,142 @@ +#!/bin/sh + +# Capstone Disassembly Engine +# By Nguyen Anh Quynh , 2013-2015 + +# Note: to cross-compile "nix32" on Linux, package gcc-multilib is required. + +MAKE_JOBS=$((${MAKE_JOBS}+0)) +[ ${MAKE_JOBS} -lt 1 ] && \ + MAKE_JOBS=4 + +# build Android lib for only one supported architecture +build_android() { + if [ -z "$NDK" ]; then + echo "ERROR! Please set \$NDK to point at your Android NDK directory." + exit 1 + fi + + HOSTOS=$(uname -s | tr 'LD' 'ld') + HOSTARCH=$(uname -m) + + TARGARCH="$1" + shift + + case "$TARGARCH" in + arm) + [ -n "$APILEVEL" ] || APILEVEL="android-14" # default to ICS + CROSS=arm-linux-androideabi + ;; + arm64) + [ -n "$APILEVEL" ] || APILEVEL="android-21" # first with arm64 + CROSS=aarch64-linux-android + ;; + + *) + echo "ERROR! Building for Android on $1 is not currently supported." + exit 1 + ;; + esac + + STANDALONE=`realpath android-ndk-${TARGARCH}-${APILEVEL}` + + [ -d $STANDALONE ] || { + python ${NDK}/build/tools/make_standalone_toolchain.py \ + --arch ${TARGARCH} \ + --api ${APILEVEL##*-} \ + --install-dir ${STANDALONE} + } + + ANDROID=1 CROSS="${STANDALONE}/${CROSS}/bin/" CC=clang CFLAGS="--sysroot=${STANDALONE}/sysroot" ${MAKE} $* +} + +# build iOS lib for all iDevices, or only specific device +build_iOS() { + IOS_SDK=`xcrun --sdk iphoneos --show-sdk-path` + IOS_CC=`xcrun --sdk iphoneos -f clang` + IOS_CFLAGS="-Os -Wimplicit -isysroot $IOS_SDK" + IOS_LDFLAGS="-isysroot $IOS_SDK" + if [ -z "$1" ]; then + # build for all iDevices + IOS_ARCHS="armv7 armv7s arm64" + else + IOS_ARCHS="$1" + fi + export CC="$IOS_CC" + export LIBARCHS="$IOS_ARCHS" + CFLAGS="$IOS_CFLAGS" LDFLAGS="$IOS_LDFLAGS" MACOS_UNIVERSAL=yes ${MAKE} +} + +install() { + # Mac OSX needs to find the right directory for pkgconfig + if [ "$UNAME" = Darwin ]; then + # we are going to install into /usr/local, so remove old installs under /usr + rm -rf /usr/lib/libcapstone.* + rm -rf /usr/include/capstone + if [ "${HOMEBREW_CAPSTONE}" != 1 ]; then + # find the directory automatically, so we can support both Macport & Brew + export PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" + fi + ${MAKE} install + else # not OSX + test -d /usr/lib64 && ${MAKE} LIBDIRARCH=lib64 + ${MAKE} install + fi +} + +uninstall() { + # Mac OSX needs to find the right directory for pkgconfig + if [ "$UNAME" = "Darwin" ]; then + # find the directory automatically, so we can support both Macport & Brew + export PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" + ${MAKE} uninstall + else # not OSX + test -d /usr/lib64 && LIBDIRARCH=lib64 + ${MAKE} uninstall + fi +} + +if [ "$UNAME" = SunOS ]; then + [ -z "${MAKE}" ] && MAKE=gmake + export INSTALL_BIN=ginstall + export CC=gcc +fi + +if [ -n "`echo "$UNAME" | grep BSD`" ]; then + MAKE=gmake + export PREFIX=/usr/local +fi + +[ -z "${UNAME}" ] && UNAME=$(uname) +[ -z "${MAKE}" ] && MAKE=make +[ -n "${MAKE_JOBS}" ] && MAKE="$MAKE -j${MAKE_JOBS}" + +TARGET="$1" +[ -n "$TARGET" ] && shift + +case "$TARGET" in + "" ) ${MAKE} $*;; + "default" ) ${MAKE} $*;; + "debug" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_STATIC=yes CFLAGS='-O0 -g -fsanitize=address' LDFLAGS='-fsanitize=address' ${MAKE} $*;; + "install" ) install;; + "uninstall" ) uninstall;; + "nix32" ) CFLAGS=-m32 LDFLAGS=-m32 ${MAKE} $*;; + "cross-win32" ) CROSS=i686-w64-mingw32- ${MAKE} $*;; + "cross-win64" ) CROSS=x86_64-w64-mingw32- ${MAKE} $*;; + "cygwin-mingw32" ) CROSS=i686-pc-mingw32- ${MAKE} $*;; + "cygwin-mingw64" ) CROSS=x86_64-w64-mingw32- ${MAKE} $*;; + "cross-android" ) build_android $*;; + "cross-android64" ) CROSS=aarch64-linux-gnu- ${MAKE} $*;; # Linux cross build + "clang" ) CC=clang ${MAKE} $*;; + "gcc" ) CC=gcc ${MAKE} $*;; + "ios" ) build_iOS $*;; + "ios_armv7" ) build_iOS armv7 $*;; + "ios_armv7s" ) build_iOS armv7s $*;; + "ios_arm64" ) build_iOS arm64 $*;; + "osx-kernel" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_HAS_OSXKERNEL=yes CAPSTONE_ARCHS=x86 CAPSTONE_SHARED=no CAPSTONE_BUILD_CORE_ONLY=yes ${MAKE} $*;; + "mac-universal" ) MACOS_UNIVERSAL=yes ${MAKE} $*;; + "mac-universal-no" ) MACOS_UNIVERSAL=no ${MAKE} $*;; + * ) + echo "Usage: $0 ["`grep '^ "' $0 | cut -d '"' -f 2 | tr "\\n" "|"`"]" + exit 1;; +esac diff --git a/white_patch_detect/capstone-master/msvc/README b/white_patch_detect/capstone-master/msvc/README new file mode 100644 index 0000000..c7248fe --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/README @@ -0,0 +1,22 @@ +This directory includes all the necessary files to compile Capstone on Windows +using Microsoft Visual Studio (VS). + + +NOTE: + +(1) Visual Studio 2010 or newer versions is required. Open "capstone.sln" to + build the libraries & test code with Visual Studio. The resulted binaries + are put under either msvc/Debug, msvc/Release, msvc/x64/Debug, or + msvc/x64/Release, depending on how you choose to compile them. + +(2) The solution (capstone.sln) & all project files (*.vcxproj) are made in + Visual Studio 2010, so if you open them using newer version, an extra step + is needed to convert them to current version. Just accept this when + asked at the initial dialog, and proceed to build the solution normally + afterwards. + +(3) The capstone_static_winkernel and test_winkernel projects are for Windows + kernel drivers and excluded from build by default. In order to build them, + you need to install Visual Studio 2013 or newer versions, and Windows Driver + Kit 8.1 Update 1 or newer versions, then check "Build" check boxes for those + projects on the Configuration Manager through the [Build] menu. diff --git a/white_patch_detect/capstone-master/msvc/capstone.sln b/white_patch_detect/capstone-master/msvc/capstone.sln new file mode 100644 index 0000000..bb049d8 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/capstone.sln @@ -0,0 +1,238 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio Version 16 +VisualStudioVersion = 16.0.30204.135 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "capstone_static", "capstone_static\capstone_static.vcxproj", "{5B01D900-2359-44CA-9914-6B0C6AFB7BE7}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_x86", "test_x86\test_x86.vcxproj", "{9C69243E-C7DC-42A4-AB86-0696E51697C8}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_arm", "test_arm\test_arm.vcxproj", "{349B99E4-2E79-44FE-96F9-02D9B4EC0584}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_arm64", "test_arm64\test_arm64.vcxproj", "{CBE31473-7D0E-41F5-AFCB-8C8422ED8908}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_m68k", "test_m68k\test_m68k.vcxproj", "{5B880AB5-E54F-11E3-8C65-B8E8563B7B00}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_mips", "test_mips\test_mips.vcxproj", "{28B2D82F-3E95-4ECE-8118-0E891BD453E0}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_ppc", "test_ppc\test_ppc.vcxproj", "{0B78E956-F897-4149-BFB2-BE87DA3A6F0D}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_sparc", "test_sparc\test_sparc.vcxproj", "{9E735ABA-00D9-4114-A9E7-0568D8DFF94B}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_systemz", "test_systemz\test_systemz.vcxproj", "{D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_detail", "test_detail\test_detail.vcxproj", "{A510F308-3094-4FF6-9DFC-539CC5260BA4}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_skipdata", "test_skipdata\test_skipdata.vcxproj", "{B09819BB-7EF1-4B04-945D-58117E6940A1}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_xcore", "test_xcore\test_xcore.vcxproj", "{5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_iter", "test_iter\test_iter.vcxproj", "{48EB18D5-7060-4C54-B8B1-BFF077329604}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_customized_mnem", "test_customized_mnem\test_customized_mnem.vcxproj", "{D622418C-A872-40D4-8C86-F3D996A4C823}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "capstone_dll", "capstone_dll\capstone_dll.vcxproj", "{2171C0E8-4915-49B9-AC23-A484FA08C126}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "capstone_static_winkernel", "capstone_static_winkernel\capstone_static_winkernel.vcxproj", "{FE197816-EF84-4E8D-B29D-E0A6BA2B144B}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_winkernel", "test_winkernel\test_winkernel.vcxproj", "{C6E4974C-2CAF-499A-802A-FB906F86B4C8}" + ProjectSection(ProjectDependencies) = postProject + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B} = {FE197816-EF84-4E8D-B29D-E0A6BA2B144B} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "cstool", "cstool\cstool.vcxproj", "{A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}" + ProjectSection(ProjectDependencies) = postProject + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + EndProjectSection +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Debug|Win32.ActiveCfg = Debug|Win32 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Debug|Win32.Build.0 = Debug|Win32 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Debug|x64.ActiveCfg = Debug|x64 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Debug|x64.Build.0 = Debug|x64 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Release|Win32.ActiveCfg = Release|Win32 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Release|Win32.Build.0 = Release|Win32 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Release|x64.ActiveCfg = Release|x64 + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}.Release|x64.Build.0 = Release|x64 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Debug|Win32.ActiveCfg = Debug|Win32 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Debug|Win32.Build.0 = Debug|Win32 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Debug|x64.ActiveCfg = Debug|x64 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Debug|x64.Build.0 = Debug|x64 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Release|Win32.ActiveCfg = Release|Win32 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Release|Win32.Build.0 = Release|Win32 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Release|x64.ActiveCfg = Release|x64 + {9C69243E-C7DC-42A4-AB86-0696E51697C8}.Release|x64.Build.0 = Release|x64 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Debug|Win32.ActiveCfg = Debug|Win32 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Debug|Win32.Build.0 = Debug|Win32 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Debug|x64.ActiveCfg = Debug|x64 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Debug|x64.Build.0 = Debug|x64 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Release|Win32.ActiveCfg = Release|Win32 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Release|Win32.Build.0 = Release|Win32 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Release|x64.ActiveCfg = Release|x64 + {349B99E4-2E79-44FE-96F9-02D9B4EC0584}.Release|x64.Build.0 = Release|x64 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Debug|Win32.ActiveCfg = Debug|Win32 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Debug|Win32.Build.0 = Debug|Win32 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Debug|x64.ActiveCfg = Debug|x64 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Debug|x64.Build.0 = Debug|x64 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Release|Win32.ActiveCfg = Release|Win32 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Release|Win32.Build.0 = Release|Win32 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Release|x64.ActiveCfg = Release|x64 + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908}.Release|x64.Build.0 = Release|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Debug|Win32.ActiveCfg = Debug|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Debug|Win32.Build.0 = Debug|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Debug|x64.ActiveCfg = Debug|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Debug|x64.Build.0 = Debug|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Release|Win32.ActiveCfg = Release|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Release|Win32.Build.0 = Release|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Release|x64.ActiveCfg = Release|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00}.Release|x64.Build.0 = Release|x64 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Debug|Win32.ActiveCfg = Debug|Win32 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Debug|Win32.Build.0 = Debug|Win32 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Debug|x64.ActiveCfg = Debug|x64 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Debug|x64.Build.0 = Debug|x64 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Release|Win32.ActiveCfg = Release|Win32 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Release|Win32.Build.0 = Release|Win32 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Release|x64.ActiveCfg = Release|x64 + {28B2D82F-3E95-4ECE-8118-0E891BD453E0}.Release|x64.Build.0 = Release|x64 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Debug|Win32.ActiveCfg = Debug|Win32 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Debug|Win32.Build.0 = Debug|Win32 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Debug|x64.ActiveCfg = Debug|x64 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Debug|x64.Build.0 = Debug|x64 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Release|Win32.ActiveCfg = Release|Win32 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Release|Win32.Build.0 = Release|Win32 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Release|x64.ActiveCfg = Release|x64 + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D}.Release|x64.Build.0 = Release|x64 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Debug|Win32.ActiveCfg = Debug|Win32 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Debug|Win32.Build.0 = Debug|Win32 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Debug|x64.ActiveCfg = Debug|x64 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Debug|x64.Build.0 = Debug|x64 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Release|Win32.ActiveCfg = Release|Win32 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Release|Win32.Build.0 = Release|Win32 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Release|x64.ActiveCfg = Release|x64 + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B}.Release|x64.Build.0 = Release|x64 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Debug|Win32.ActiveCfg = Debug|Win32 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Debug|Win32.Build.0 = Debug|Win32 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Debug|x64.ActiveCfg = Debug|x64 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Debug|x64.Build.0 = Debug|x64 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Release|Win32.ActiveCfg = Release|Win32 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Release|Win32.Build.0 = Release|Win32 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Release|x64.ActiveCfg = Release|x64 + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2}.Release|x64.Build.0 = Release|x64 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Debug|Win32.ActiveCfg = Debug|Win32 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Debug|Win32.Build.0 = Debug|Win32 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Debug|x64.ActiveCfg = Debug|x64 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Debug|x64.Build.0 = Debug|x64 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Release|Win32.ActiveCfg = Release|Win32 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Release|Win32.Build.0 = Release|Win32 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Release|x64.ActiveCfg = Release|x64 + {A510F308-3094-4FF6-9DFC-539CC5260BA4}.Release|x64.Build.0 = Release|x64 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Debug|Win32.ActiveCfg = Debug|Win32 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Debug|Win32.Build.0 = Debug|Win32 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Debug|x64.ActiveCfg = Debug|x64 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Debug|x64.Build.0 = Debug|x64 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Release|Win32.ActiveCfg = Release|Win32 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Release|Win32.Build.0 = Release|Win32 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Release|x64.ActiveCfg = Release|x64 + {B09819BB-7EF1-4B04-945D-58117E6940A1}.Release|x64.Build.0 = Release|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Debug|Win32.ActiveCfg = Debug|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Debug|Win32.Build.0 = Debug|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Debug|x64.ActiveCfg = Debug|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Debug|x64.Build.0 = Debug|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Release|Win32.ActiveCfg = Release|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Release|Win32.Build.0 = Release|Win32 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Release|x64.ActiveCfg = Release|x64 + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE}.Release|x64.Build.0 = Release|x64 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Debug|Win32.ActiveCfg = Debug|Win32 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Debug|Win32.Build.0 = Debug|Win32 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Debug|x64.ActiveCfg = Debug|x64 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Debug|x64.Build.0 = Debug|x64 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Release|Win32.ActiveCfg = Release|Win32 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Release|Win32.Build.0 = Release|Win32 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Release|x64.ActiveCfg = Release|x64 + {48EB18D5-7060-4C54-B8B1-BFF077329604}.Release|x64.Build.0 = Release|x64 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Debug|Win32.ActiveCfg = Debug|Win32 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Debug|Win32.Build.0 = Debug|Win32 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Debug|x64.ActiveCfg = Debug|x64 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Debug|x64.Build.0 = Debug|x64 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Release|Win32.ActiveCfg = Release|Win32 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Release|Win32.Build.0 = Release|Win32 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Release|x64.ActiveCfg = Release|x64 + {D622418C-A872-40D4-8C86-F3D996A4C823}.Release|x64.Build.0 = Release|x64 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Debug|Win32.ActiveCfg = Debug|Win32 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Debug|Win32.Build.0 = Debug|Win32 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Debug|x64.ActiveCfg = Debug|x64 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Debug|x64.Build.0 = Debug|x64 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Release|Win32.ActiveCfg = Release|Win32 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Release|Win32.Build.0 = Release|Win32 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Release|x64.ActiveCfg = Release|x64 + {2171C0E8-4915-49B9-AC23-A484FA08C126}.Release|x64.Build.0 = Release|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|Win32.ActiveCfg = Debug|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Debug|x64.ActiveCfg = Debug|x64 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|Win32.ActiveCfg = Release|Win32 + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B}.Release|x64.ActiveCfg = Release|x64 + {C6E4974C-2CAF-499A-802A-FB906F86B4C8}.Debug|Win32.ActiveCfg = Debug|Win32 + {C6E4974C-2CAF-499A-802A-FB906F86B4C8}.Debug|x64.ActiveCfg = Debug|x64 + {C6E4974C-2CAF-499A-802A-FB906F86B4C8}.Release|Win32.ActiveCfg = Release|Win32 + {C6E4974C-2CAF-499A-802A-FB906F86B4C8}.Release|x64.ActiveCfg = Release|x64 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Debug|Win32.ActiveCfg = Debug|Win32 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Debug|Win32.Build.0 = Debug|Win32 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Debug|x64.ActiveCfg = Debug|x64 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Debug|x64.Build.0 = Debug|x64 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Release|Win32.ActiveCfg = Release|Win32 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Release|Win32.Build.0 = Release|Win32 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Release|x64.ActiveCfg = Release|x64 + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D}.Release|x64.Build.0 = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {D78E7A4B-22AE-46B3-9F83-E3C01A5E928A} + EndGlobalSection +EndGlobal diff --git a/white_patch_detect/capstone-master/msvc/capstone_dll/capstone_dll.vcxproj b/white_patch_detect/capstone-master/msvc/capstone_dll/capstone_dll.vcxproj new file mode 100644 index 0000000..7cd6181 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/capstone_dll/capstone_dll.vcxproj @@ -0,0 +1,218 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {2171C0E8-4915-49B9-AC23-A484FA08C126} + Win32Proj + capstonedll + + + + DynamicLibrary + true + Unicode + v142 + + + DynamicLibrary + true + Unicode + v142 + + + DynamicLibrary + false + true + Unicode + v142 + + + DynamicLibrary + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + capstone + + + true + capstone + + + false + capstone + + + false + capstone + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Windows + true + $(OutDir)$(TargetName)$(TargetExt) + $(OutDir)capstone_dll.lib + + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Windows + true + $(OutDir)$(TargetName)$(TargetExt) + $(OutDir)capstone_dll.lib + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Windows + true + true + true + $(OutDir)$(TargetName)$(TargetExt) + $(OutDir)capstone_dll.lib + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Windows + true + true + true + $(OutDir)$(TargetName)$(TargetExt) + $(OutDir)capstone_dll.lib + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/capstone_static/capstone_static.vcxproj b/white_patch_detect/capstone-master/msvc/capstone_static/capstone_static.vcxproj new file mode 100644 index 0000000..67eade8 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/capstone_static/capstone_static.vcxproj @@ -0,0 +1,207 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {5B01D900-2359-44CA-9914-6B0C6AFB7BE7} + Win32Proj + capstonewin32 + capstone_static + + + + StaticLibrary + true + Unicode + v142 + + + StaticLibrary + true + Unicode + v142 + + + StaticLibrary + false + true + Unicode + v142 + + + StaticLibrary + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + capstone + + + capstone + + + capstone + + + capstone + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Windows + true + + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Windows + true + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Windows + true + true + true + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Windows + true + true + true + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj b/white_patch_detect/capstone-master/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj new file mode 100644 index 0000000..5578fbe --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/capstone_static_winkernel/capstone_static_winkernel.vcxproj @@ -0,0 +1,180 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {FE197816-EF84-4E8D-B29D-E0A6BA2B144B} + {1bc93793-694f-48fe-9372-81e2b05556fd} + v4.5 + 11.0 + Win8.1 Debug + Win32 + capstone_static_winkernel + capstone_static_winkernel + 10.0 + + + + Windows7 + true + WindowsKernelModeDriver10.0 + StaticLibrary + KMDF + + + Windows7 + false + WindowsKernelModeDriver10.0 + StaticLibrary + KMDF + + + Windows7 + true + WindowsKernelModeDriver10.0 + StaticLibrary + KMDF + + + Windows7 + false + v142 + StaticLibrary + KMDF + + + + + + + + + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + $(DDK_LibraryPath_DDKPlatform);$(LibraryPath) + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_M68K;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + false + Level3 + ProgramDatabase + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_M68K;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + false + Level3 + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_M68K;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + false + Level3 + ProgramDatabase + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_M68K;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + false + Level3 + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/cstool/cstool.vcxproj b/white_patch_detect/capstone-master/msvc/cstool/cstool.vcxproj new file mode 100644 index 0000000..b2e4595 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/cstool/cstool.vcxproj @@ -0,0 +1,180 @@ +锘 + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + {A5AB9988-6B03-4F0D-8D40-9440BBC8B03D} + Win32Proj + cstool + cstool + + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + + + true + ..\..\include;$(IncludePath) + + + true + ..\..\include;$(IncludePath) + + + false + ..\..\include;$(IncludePath) + + + false + ..\..\include;$(IncludePath) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreadedDebug + ProgramDatabase + + + Console + true + $(OutputPath);%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + _DEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreadedDebug + ProgramDatabase + + + Console + true + $(OutputPath);%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreaded + + + Console + true + true + true + $(OutputPath);%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + MultiThreaded + + + Console + true + true + true + $(OutputPath);%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_arm/test_arm.vcxproj b/white_patch_detect/capstone-master/msvc/test_arm/test_arm.vcxproj new file mode 100644 index 0000000..0d18c0b --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_arm/test_arm.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {349B99E4-2E79-44FE-96F9-02D9B4EC0584} + Win32Proj + capstonetestarm + test_arm + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_arm64/test_arm64.vcxproj b/white_patch_detect/capstone-master/msvc/test_arm64/test_arm64.vcxproj new file mode 100644 index 0000000..86edb65 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_arm64/test_arm64.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {CBE31473-7D0E-41F5-AFCB-8C8422ED8908} + Win32Proj + capstonetestarm64 + test_arm64 + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_customized_mnem/test_customized_mnem.vcxproj b/white_patch_detect/capstone-master/msvc/test_customized_mnem/test_customized_mnem.vcxproj new file mode 100644 index 0000000..199e1bc --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_customized_mnem/test_customized_mnem.vcxproj @@ -0,0 +1,171 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {D622418C-A872-40D4-8C86-F3D996A4C823} + Win32Proj + capstonetestcustomizedmnem + test_customized_mnem + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_detail/test_detail.vcxproj b/white_patch_detect/capstone-master/msvc/test_detail/test_detail.vcxproj new file mode 100644 index 0000000..62f91d9 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_detail/test_detail.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {A510F308-3094-4FF6-9DFC-539CC5260BA4} + Win32Proj + capstonetestdetail + test_detail + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_iter/test_iter.vcxproj b/white_patch_detect/capstone-master/msvc/test_iter/test_iter.vcxproj new file mode 100644 index 0000000..f420de1 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_iter/test_iter.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {48EB18D5-7060-4C54-B8B1-BFF077329604} + Win32Proj + capstonetestiter + test_iter + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_m68k/test_m68k.vcxproj b/white_patch_detect/capstone-master/msvc/test_m68k/test_m68k.vcxproj new file mode 100644 index 0000000..8bdd199 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_m68k/test_m68k.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {5B880AB5-E54F-11E3-8C65-B8E8563B7B00} + Win32Proj + capstonetestm68k + test_m68k + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_mips/test_mips.vcxproj b/white_patch_detect/capstone-master/msvc/test_mips/test_mips.vcxproj new file mode 100644 index 0000000..55f08b1 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_mips/test_mips.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {28B2D82F-3E95-4ECE-8118-0E891BD453E0} + Win32Proj + capstonetestmips + test_mips + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_ppc/test_ppc.vcxproj b/white_patch_detect/capstone-master/msvc/test_ppc/test_ppc.vcxproj new file mode 100644 index 0000000..acc0aa4 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_ppc/test_ppc.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + + {0B78E956-F897-4149-BFB2-BE87DA3A6F0D} + Win32Proj + capstonetestppc + test_ppc + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_skipdata/test_skipdata.vcxproj b/white_patch_detect/capstone-master/msvc/test_skipdata/test_skipdata.vcxproj new file mode 100644 index 0000000..fd9bd4c --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_skipdata/test_skipdata.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {B09819BB-7EF1-4B04-945D-58117E6940A1} + Win32Proj + capstonetestskipdata + test_skipdata + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_sparc/test_sparc.vcxproj b/white_patch_detect/capstone-master/msvc/test_sparc/test_sparc.vcxproj new file mode 100644 index 0000000..02c200f --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_sparc/test_sparc.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {9E735ABA-00D9-4114-A9E7-0568D8DFF94B} + Win32Proj + capstonetestsparc + test_sparc + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_systemz/test_systemz.vcxproj b/white_patch_detect/capstone-master/msvc/test_systemz/test_systemz.vcxproj new file mode 100644 index 0000000..7c36dc7 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_systemz/test_systemz.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + + {D83F2A2D-D5F1-421E-A5B7-B47F1ECABAD2} + Win32Proj + capstonetestsystemz + test_systemz + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_winkernel/test_winkernel.vcxproj b/white_patch_detect/capstone-master/msvc/test_winkernel/test_winkernel.vcxproj new file mode 100644 index 0000000..0d06b33 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_winkernel/test_winkernel.vcxproj @@ -0,0 +1,141 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {C6E4974C-2CAF-499A-802A-FB906F86B4C8} + {1bc93793-694f-48fe-9372-81e2b05556fd} + v4.5 + 11.0 + Win8.1 Debug + Win32 + test_winkernel + test_winkernel + + + + Windows7 + true + WindowsKernelModeDriver10.0 + Driver + KMDF + + + Windows7 + false + WindowsKernelModeDriver10.0 + Driver + KMDF + + + Windows7 + true + WindowsKernelModeDriver10.0 + Driver + KMDF + + + Windows7 + false + WindowsKernelModeDriver10.0 + Driver + KMDF + + + + + + + + + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + DbgengKernelDebugger + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + ProgramDatabase + + + capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + ..\Debug + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + + + capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + ..\Release + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + ProgramDatabase + + + capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + ..\x64\Debug + + + + + trace.h + true + ..\..\include;..\headers;$(IntDir);%(AdditionalIncludeDirectories) + CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_M68K;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;%(PreprocessorDefinitions) + + + capstone_static_winkernel.lib;ntstrsafe.lib;%(AdditionalDependencies) + ..\x64\Release + + + + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_x86/test_x86.vcxproj b/white_patch_detect/capstone-master/msvc/test_x86/test_x86.vcxproj new file mode 100644 index 0000000..788c22e --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_x86/test_x86.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {9C69243E-C7DC-42A4-AB86-0696E51697C8} + Win32Proj + capstonetestx86 + test_x86 + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/msvc/test_xcore/test_xcore.vcxproj b/white_patch_detect/capstone-master/msvc/test_xcore/test_xcore.vcxproj new file mode 100644 index 0000000..fdbc710 --- /dev/null +++ b/white_patch_detect/capstone-master/msvc/test_xcore/test_xcore.vcxproj @@ -0,0 +1,171 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + {5B880AB5-E54F-11E3-8C65-B8E8563B7BDE} + Win32Proj + capstonetestxcore + test_xcore + + + + Application + true + Unicode + v142 + + + Application + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + Application + false + true + Unicode + v142 + + + + + + + + + + + + + + + + + + + true + + + true + + + false + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreadedDebug + ProgramDatabase + + + Console + true + ..\x64\Debug;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + ..\..\include;..\headers;%(AdditionalIncludeDirectories) + MultiThreaded + + + Console + true + true + true + ..\x64\Release;%(AdditionalLibraryDirectories) + capstone.lib;%(AdditionalDependencies) + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/capstone-master/nmake.bat b/white_patch_detect/capstone-master/nmake.bat new file mode 100644 index 0000000..4a77c6f --- /dev/null +++ b/white_patch_detect/capstone-master/nmake.bat @@ -0,0 +1,27 @@ +:: Capstone disassembler engine (www.capstone-engine.org) +:: Build Capstone libs (capstone.dll & capstone.lib) on Windows with CMake & Nmake +:: By Nguyen Anh Quynh, Jorn Vernee, 2017, 2019 + +@echo off + +set flags="-DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_STATIC_RUNTIME=ON" + +if "%1"=="ARM" set %arch%=ARM +if "%1"=="ARM64" set %arch%=ARM64 +if "%1"=="M68K" set %arch%=M68K +if "%1"=="MIPS" set %arch%=MIPS +if "%1"=="PowerPC" set %arch%=PPC +if "%1"=="Sparc" set %arch%=SPARC +if "%1"=="SystemZ" set %arch%=SYSZ +if "%1"=="XCore" set %arch%=XCORE +if "%1"=="x86" set %arch%=X86 +if "%1"=="TMS320C64x" set %arch%=TMS320C64X +if "%1"=="M680x" set %arch%=M680X +if "%1"=="EVM" set %arch%=EVM +if "%1"=="MOS65XX" set %arch%=MOS65XX + +if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" + +cmake %flags% -G "NMake Makefiles" .. +nmake + diff --git a/white_patch_detect/capstone-master/pkgconfig.mk b/white_patch_detect/capstone-master/pkgconfig.mk new file mode 100644 index 0000000..5c05acb --- /dev/null +++ b/white_patch_detect/capstone-master/pkgconfig.mk @@ -0,0 +1,12 @@ +# Package version of Capstone for Makefile. +# To be used to generate capstone.pc for pkg-config + +# version major & minor +PKG_MAJOR = 5 +PKG_MINOR = 0 + +# version bugfix level. Example: PKG_EXTRA = 1 +PKG_EXTRA = 0 + +# version tag. Examples: rc1, b2, post1 +PKG_TAG = diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/basic-a64-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/basic-a64-instructions.s.cs new file mode 100644 index 0000000..772bb2d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/basic-a64-instructions.s.cs @@ -0,0 +1,2065 @@ +# CS_ARCH_ARM64, 0, None +0x82,0x00,0x25,0x8b = add x2, x4, w5, uxtb +0xf4,0x23,0x33,0x8b = add x20, sp, w19, uxth +0x2c,0x40,0x34,0x8b = add x12, x1, w20, uxtw +0x74,0x60,0x2d,0x8b = add x20, x3, x13, uxtx +0x31,0x83,0x34,0x8b = add x17, x25, w20, sxtb +0xb2,0xa1,0x33,0x8b = add x18, x13, w19, sxth +0x5f,0xc0,0x23,0x8b = add sp, x2, w3, sxtw +0xa3,0xe0,0x29,0x8b = add x3, x5, x9, sxtx +0xa2,0x00,0x27,0x0b = add w2, w5, w7, uxtb +0xf5,0x21,0x31,0x0b = add w21, w15, w17, uxth +0xbe,0x43,0x3f,0x0b = add w30, w29, wzr, uxtw +0x33,0x62,0x21,0x0b = add w19, w17, w1, uxtx +0xa2,0x80,0x21,0x0b = add w2, w5, w1, sxtb +0x3a,0xa2,0x33,0x0b = add w26, w17, w19, sxth +0x40,0xc0,0x23,0x0b = add w0, w2, w3, sxtw +0x62,0xe0,0x25,0x0b = add w2, w3, w5, sxtx +0x62,0x80,0x25,0x8b = add x2, x3, w5, sxtb +0x67,0x31,0x2d,0x8b = add x7, x11, w13, uxth #4 +0x71,0x4a,0x37,0x0b = add w17, w19, w23, uxtw #2 +0xfd,0x66,0x31,0x0b = add w29, w23, w17, uxtx #1 +0x82,0x08,0x25,0xcb = sub x2, x4, w5, uxtb #2 +0xf4,0x33,0x33,0xcb = sub x20, sp, w19, uxth #4 +0x2c,0x40,0x34,0xcb = sub x12, x1, w20, uxtw +0x74,0x60,0x2d,0xcb = sub x20, x3, x13, uxtx +0x31,0x83,0x34,0xcb = sub x17, x25, w20, sxtb +0xb2,0xa1,0x33,0xcb = sub x18, x13, w19, sxth +0x5f,0xc0,0x23,0xcb = sub sp, x2, w3, sxtw +0xa3,0xe0,0x29,0xcb = sub x3, x5, x9, sxtx +0xa2,0x00,0x27,0x4b = sub w2, w5, w7, uxtb +0xf5,0x21,0x31,0x4b = sub w21, w15, w17, uxth +0xbe,0x43,0x3f,0x4b = sub w30, w29, wzr, uxtw +0x33,0x62,0x21,0x4b = sub w19, w17, w1, uxtx +0xa2,0x80,0x21,0x4b = sub w2, w5, w1, sxtb +0xfa,0xa3,0x33,0x4b = sub w26, wsp, w19, sxth +0x5f,0xc0,0x23,0x4b = sub wsp, w2, w3, sxtw +0x62,0xe0,0x25,0x4b = sub w2, w3, w5, sxtx +0x82,0x08,0x25,0xab = adds x2, x4, w5, uxtb #2 +0xf4,0x33,0x33,0xab = adds x20, sp, w19, uxth #4 +0x2c,0x40,0x34,0xab = adds x12, x1, w20, uxtw +0x74,0x60,0x2d,0xab = adds x20, x3, x13, uxtx +// 0x3f,0x8f,0x34,0xab = adds xzr, x25, w20, sxtb #3 +0xf2,0xa3,0x33,0xab = adds x18, sp, w19, sxth +// 0x5f,0xc0,0x23,0xab = adds xzr, x2, w3, sxtw +0xa3,0xe8,0x29,0xab = adds x3, x5, x9, sxtx #2 +0xa2,0x00,0x27,0x2b = adds w2, w5, w7, uxtb +0xf5,0x21,0x31,0x2b = adds w21, w15, w17, uxth +0xbe,0x43,0x3f,0x2b = adds w30, w29, wzr, uxtw +0x33,0x62,0x21,0x2b = adds w19, w17, w1, uxtx +0xa2,0x84,0x21,0x2b = adds w2, w5, w1, sxtb #1 +0xfa,0xa3,0x33,0x2b = adds w26, wsp, w19, sxth +// 0x5f,0xc0,0x23,0x2b = adds wzr, w2, w3, sxtw +0x62,0xe0,0x25,0x2b = adds w2, w3, w5, sxtx +0x82,0x08,0x25,0xeb = subs x2, x4, w5, uxtb #2 +0xf4,0x33,0x33,0xeb = subs x20, sp, w19, uxth #4 +0x2c,0x40,0x34,0xeb = subs x12, x1, w20, uxtw +0x74,0x60,0x2d,0xeb = subs x20, x3, x13, uxtx +// 0x3f,0x8f,0x34,0xeb = subs xzr, x25, w20, sxtb #3 +0xf2,0xa3,0x33,0xeb = subs x18, sp, w19, sxth +// 0x5f,0xc0,0x23,0xeb = subs xzr, x2, w3, sxtw +0xa3,0xe8,0x29,0xeb = subs x3, x5, x9, sxtx #2 +0xa2,0x00,0x27,0x6b = subs w2, w5, w7, uxtb +0xf5,0x21,0x31,0x6b = subs w21, w15, w17, uxth +0xbe,0x43,0x3f,0x6b = subs w30, w29, wzr, uxtw +0x33,0x62,0x21,0x6b = subs w19, w17, w1, uxtx +0xa2,0x84,0x21,0x6b = subs w2, w5, w1, sxtb #1 +0xfa,0xa3,0x33,0x6b = subs w26, wsp, w19, sxth +// 0x5f,0xc0,0x23,0x6b = subs wzr, w2, w3, sxtw +0x62,0xe0,0x25,0x6b = subs w2, w3, w5, sxtx +0x9f,0x08,0x25,0xeb = cmp x4, w5, uxtb #2 +0xff,0x33,0x33,0xeb = cmp sp, w19, uxth #4 +0x3f,0x40,0x34,0xeb = cmp x1, w20, uxtw +0x7f,0x60,0x2d,0xeb = cmp x3, x13, uxtx +// 0x3f,0x8f,0x34,0xeb = cmp x25, w20, sxtb #3 +0xff,0xa3,0x33,0xeb = cmp sp, w19, sxth +// 0x5f,0xc0,0x23,0xeb = cmp x2, w3, sxtw +0xbf,0xe8,0x29,0xeb = cmp x5, x9, sxtx #2 +0xbf,0x00,0x27,0x6b = cmp w5, w7, uxtb +0xff,0x21,0x31,0x6b = cmp w15, w17, uxth +0xbf,0x43,0x3f,0x6b = cmp w29, wzr, uxtw +0x3f,0x62,0x21,0x6b = cmp w17, w1, uxtx +0xbf,0x84,0x21,0x6b = cmp w5, w1, sxtb #1 +0xff,0xa3,0x33,0x6b = cmp wsp, w19, sxth +// 0x5f,0xc0,0x23,0x6b = cmp w2, w3, sxtw +0x7f,0xe0,0x25,0x6b = cmp w3, w5, sxtx +0x9f,0x08,0x25,0xab = cmn x4, w5, uxtb #2 +0xff,0x33,0x33,0xab = cmn sp, w19, uxth #4 +0x3f,0x40,0x34,0xab = cmn x1, w20, uxtw +0x7f,0x60,0x2d,0xab = cmn x3, x13, uxtx +// 0x3f,0x8f,0x34,0xab = cmn x25, w20, sxtb #3 +0xff,0xa3,0x33,0xab = cmn sp, w19, sxth +// 0x5f,0xc0,0x23,0xab = cmn x2, w3, sxtw +0xbf,0xe8,0x29,0xab = cmn x5, x9, sxtx #2 +0xbf,0x00,0x27,0x2b = cmn w5, w7, uxtb +0xff,0x21,0x31,0x2b = cmn w15, w17, uxth +0xbf,0x43,0x3f,0x2b = cmn w29, wzr, uxtw +0x3f,0x62,0x21,0x2b = cmn w17, w1, uxtx +0xbf,0x84,0x21,0x2b = cmn w5, w1, sxtb #1 +0xff,0xa3,0x33,0x2b = cmn wsp, w19, sxth +// 0x5f,0xc0,0x23,0x2b = cmn w2, w3, sxtw +0x7f,0xe0,0x25,0x2b = cmn w3, w5, sxtx +0x9f,0x0e,0x3d,0xeb = cmp x20, w29, uxtb #3 +0x9f,0x71,0x2d,0xeb = cmp x12, x13, uxtx #4 +0xff,0x03,0x21,0x6b = cmp wsp, w1, uxtb +0xff,0xc3,0x3f,0x2b = cmn wsp, wzr, sxtw +0x7f,0x70,0x27,0xcb = sub sp, x3, x7, lsl #4 +0xe2,0x47,0x23,0x0b = add w2, wsp, w3, lsl #1 +0xff,0x43,0x29,0x6b = cmp wsp, w9 +// 0xff,0x53,0x23,0x2b = adds wzr, wsp, w3, lsl #4 +0xe3,0x6b,0x29,0xeb = subs x3, sp, x9, lsl #2 +0xa4,0x00,0x00,0x11 = add w4, w5, #0 +0x62,0xfc,0x3f,0x11 = add w2, w3, #0xfff +0xbe,0x07,0x40,0x11 = add w30, w29, #1, lsl #12 +0xad,0xfc,0x7f,0x11 = add w13, w5, #0xfff, lsl #12 +0xe5,0x98,0x19,0x91 = add x5, x7, #0x666 +0xf4,0x87,0x0c,0x11 = add w20, wsp, #0x321 +0xff,0x43,0x11,0x11 = add wsp, wsp, #0x450 +0xdf,0xd3,0x3f,0x11 = add wsp, w30, #0xff4 +0x00,0x8f,0x04,0x91 = add x0, x24, #0x123 +0x03,0xff,0x7f,0x91 = add x3, x24, #0xfff, lsl #12 +0xe8,0xcb,0x10,0x91 = add x8, sp, #0x432 +0xbf,0xa3,0x3b,0x91 = add sp, x29, #0xee8 +0xe0,0xb7,0x3f,0x51 = sub w0, wsp, #0xfed +0x84,0x8a,0x48,0x51 = sub w4, w20, #0x222, lsl #12 +0xff,0x83,0x04,0xd1 = sub sp, sp, #0x120 +0x7f,0x42,0x00,0x51 = sub wsp, w19, #0x10 +0xed,0x8e,0x44,0x31 = adds w13, w23, #0x123, lsl #12 +// 0x5f,0xfc,0x3f,0x31 = adds wzr, w2, #0xfff +0xf4,0x03,0x00,0x31 = adds w20, wsp, #0 +// 0x7f,0x04,0x40,0xb1 = adds xzr, x3, #1, lsl #12 +// 0xff,0x53,0x40,0xf1 = subs xzr, sp, #0x14, lsl #12 +// 0xdf,0xff,0x3f,0xf1 = subs xzr, x30, #0xfff +0xe4,0xbb,0x3b,0xf1 = subs x4, sp, #0xeee +0x7f,0x8c,0x44,0x31 = cmn w3, #0x123, lsl #12 +0xff,0x57,0x15,0x31 = cmn wsp, #0x555 +0xff,0x13,0x51,0xb1 = cmn sp, #0x444, lsl #12 +0x9f,0xb0,0x44,0xf1 = cmp x4, #0x12c, lsl #12 +0xff,0xd3,0x07,0x71 = cmp wsp, #0x1f4 +0xff,0x23,0x03,0xf1 = cmp sp, #0xc8 +0xdf,0x03,0x00,0x91 = mov sp, x30 +0x9f,0x02,0x00,0x11 = mov wsp, w20 +0xeb,0x03,0x00,0x91 = mov x11, sp +0xf8,0x03,0x00,0x11 = mov w24, wsp +0xa3,0x00,0x07,0x0b = add w3, w5, w7 +0x7f,0x00,0x05,0x0b = add wzr, w3, w5 +0xf4,0x03,0x04,0x0b = add w20, wzr, w4 +0xc4,0x00,0x1f,0x0b = add w4, w6, wzr +0xab,0x01,0x0f,0x0b = add w11, w13, w15 +0x69,0x28,0x1f,0x0b = add w9, w3, wzr, lsl #10 +0xb1,0x7f,0x14,0x0b = add w17, w29, w20, lsl #31 +0xd5,0x02,0x57,0x0b = add w21, w22, w23, lsr #0 +0x38,0x4b,0x5a,0x0b = add w24, w25, w26, lsr #18 +0x9b,0x7f,0x5d,0x0b = add w27, w28, w29, lsr #31 +0x62,0x00,0x84,0x0b = add w2, w3, w4, asr #0 +0xc5,0x54,0x87,0x0b = add w5, w6, w7, asr #21 +0x28,0x7d,0x8a,0x0b = add w8, w9, w10, asr #31 +0xa3,0x00,0x07,0x8b = add x3, x5, x7 +0x7f,0x00,0x05,0x8b = add xzr, x3, x5 +0xf4,0x03,0x04,0x8b = add x20, xzr, x4 +0xc4,0x00,0x1f,0x8b = add x4, x6, xzr +0xab,0x01,0x0f,0x8b = add x11, x13, x15 +0x69,0x28,0x1f,0x8b = add x9, x3, xzr, lsl #10 +0xb1,0xff,0x14,0x8b = add x17, x29, x20, lsl #63 +0xd5,0x02,0x57,0x8b = add x21, x22, x23, lsr #0 +0x38,0x4b,0x5a,0x8b = add x24, x25, x26, lsr #18 +0x9b,0xff,0x5d,0x8b = add x27, x28, x29, lsr #63 +0x62,0x00,0x84,0x8b = add x2, x3, x4, asr #0 +0xc5,0x54,0x87,0x8b = add x5, x6, x7, asr #21 +0x28,0xfd,0x8a,0x8b = add x8, x9, x10, asr #63 +0xa3,0x00,0x07,0x2b = adds w3, w5, w7 +// 0x7f,0x00,0x05,0x2b = adds wzr, w3, w5 +0xf4,0x03,0x04,0x2b = adds w20, wzr, w4 +0xc4,0x00,0x1f,0x2b = adds w4, w6, wzr +0xab,0x01,0x0f,0x2b = adds w11, w13, w15 +0x69,0x28,0x1f,0x2b = adds w9, w3, wzr, lsl #10 +0xb1,0x7f,0x14,0x2b = adds w17, w29, w20, lsl #31 +0xd5,0x02,0x57,0x2b = adds w21, w22, w23, lsr #0 +0x38,0x4b,0x5a,0x2b = adds w24, w25, w26, lsr #18 +0x9b,0x7f,0x5d,0x2b = adds w27, w28, w29, lsr #31 +0x62,0x00,0x84,0x2b = adds w2, w3, w4, asr #0 +0xc5,0x54,0x87,0x2b = adds w5, w6, w7, asr #21 +0x28,0x7d,0x8a,0x2b = adds w8, w9, w10, asr #31 +0xa3,0x00,0x07,0xab = adds x3, x5, x7 +// 0x7f,0x00,0x05,0xab = adds xzr, x3, x5 +0xf4,0x03,0x04,0xab = adds x20, xzr, x4 +0xc4,0x00,0x1f,0xab = adds x4, x6, xzr +0xab,0x01,0x0f,0xab = adds x11, x13, x15 +0x69,0x28,0x1f,0xab = adds x9, x3, xzr, lsl #10 +0xb1,0xff,0x14,0xab = adds x17, x29, x20, lsl #63 +0xd5,0x02,0x57,0xab = adds x21, x22, x23, lsr #0 +0x38,0x4b,0x5a,0xab = adds x24, x25, x26, lsr #18 +0x9b,0xff,0x5d,0xab = adds x27, x28, x29, lsr #63 +0x62,0x00,0x84,0xab = adds x2, x3, x4, asr #0 +0xc5,0x54,0x87,0xab = adds x5, x6, x7, asr #21 +0x28,0xfd,0x8a,0xab = adds x8, x9, x10, asr #63 +0xa3,0x00,0x07,0x4b = sub w3, w5, w7 +0x7f,0x00,0x05,0x4b = sub wzr, w3, w5 +// 0xf4,0x03,0x04,0x4b = sub w20, wzr, w4 +0xc4,0x00,0x1f,0x4b = sub w4, w6, wzr +0xab,0x01,0x0f,0x4b = sub w11, w13, w15 +0x69,0x28,0x1f,0x4b = sub w9, w3, wzr, lsl #10 +0xb1,0x7f,0x14,0x4b = sub w17, w29, w20, lsl #31 +0xd5,0x02,0x57,0x4b = sub w21, w22, w23, lsr #0 +0x38,0x4b,0x5a,0x4b = sub w24, w25, w26, lsr #18 +0x9b,0x7f,0x5d,0x4b = sub w27, w28, w29, lsr #31 +0x62,0x00,0x84,0x4b = sub w2, w3, w4, asr #0 +0xc5,0x54,0x87,0x4b = sub w5, w6, w7, asr #21 +0x28,0x7d,0x8a,0x4b = sub w8, w9, w10, asr #31 +0xa3,0x00,0x07,0xcb = sub x3, x5, x7 +0x7f,0x00,0x05,0xcb = sub xzr, x3, x5 +// 0xf4,0x03,0x04,0xcb = sub x20, xzr, x4 +0xc4,0x00,0x1f,0xcb = sub x4, x6, xzr +0xab,0x01,0x0f,0xcb = sub x11, x13, x15 +0x69,0x28,0x1f,0xcb = sub x9, x3, xzr, lsl #10 +0xb1,0xff,0x14,0xcb = sub x17, x29, x20, lsl #63 +0xd5,0x02,0x57,0xcb = sub x21, x22, x23, lsr #0 +0x38,0x4b,0x5a,0xcb = sub x24, x25, x26, lsr #18 +0x9b,0xff,0x5d,0xcb = sub x27, x28, x29, lsr #63 +0x62,0x00,0x84,0xcb = sub x2, x3, x4, asr #0 +0xc5,0x54,0x87,0xcb = sub x5, x6, x7, asr #21 +0x28,0xfd,0x8a,0xcb = sub x8, x9, x10, asr #63 +0xa3,0x00,0x07,0x6b = subs w3, w5, w7 +// 0x7f,0x00,0x05,0x6b = subs wzr, w3, w5 +// 0xf4,0x03,0x04,0x6b = subs w20, wzr, w4 +0xc4,0x00,0x1f,0x6b = subs w4, w6, wzr +0xab,0x01,0x0f,0x6b = subs w11, w13, w15 +0x69,0x28,0x1f,0x6b = subs w9, w3, wzr, lsl #10 +0xb1,0x7f,0x14,0x6b = subs w17, w29, w20, lsl #31 +0xd5,0x02,0x57,0x6b = subs w21, w22, w23, lsr #0 +0x38,0x4b,0x5a,0x6b = subs w24, w25, w26, lsr #18 +0x9b,0x7f,0x5d,0x6b = subs w27, w28, w29, lsr #31 +0x62,0x00,0x84,0x6b = subs w2, w3, w4, asr #0 +0xc5,0x54,0x87,0x6b = subs w5, w6, w7, asr #21 +0x28,0x7d,0x8a,0x6b = subs w8, w9, w10, asr #31 +0xa3,0x00,0x07,0xeb = subs x3, x5, x7 +// 0x7f,0x00,0x05,0xeb = subs xzr, x3, x5 +// 0xf4,0x03,0x04,0xeb = subs x20, xzr, x4 +0xc4,0x00,0x1f,0xeb = subs x4, x6, xzr +0xab,0x01,0x0f,0xeb = subs x11, x13, x15 +0x69,0x28,0x1f,0xeb = subs x9, x3, xzr, lsl #10 +0xb1,0xff,0x14,0xeb = subs x17, x29, x20, lsl #63 +0xd5,0x02,0x57,0xeb = subs x21, x22, x23, lsr #0 +0x38,0x4b,0x5a,0xeb = subs x24, x25, x26, lsr #18 +0x9b,0xff,0x5d,0xeb = subs x27, x28, x29, lsr #63 +0x62,0x00,0x84,0xeb = subs x2, x3, x4, asr #0 +0xc5,0x54,0x87,0xeb = subs x5, x6, x7, asr #21 +0x28,0xfd,0x8a,0xeb = subs x8, x9, x10, asr #63 +0x1f,0x00,0x03,0x2b = cmn w0, w3 +0xff,0x03,0x04,0x2b = cmn wzr, w4 +0xbf,0x00,0x1f,0x2b = cmn w5, wzr +0xdf,0x00,0x07,0x2b = cmn w6, w7 +0x1f,0x3d,0x09,0x2b = cmn w8, w9, lsl #15 +0x5f,0x7d,0x0b,0x2b = cmn w10, w11, lsl #31 +0x9f,0x01,0x4d,0x2b = cmn w12, w13, lsr #0 +0xdf,0x55,0x4f,0x2b = cmn w14, w15, lsr #21 +0x1f,0x7e,0x51,0x2b = cmn w16, w17, lsr #31 +0x5f,0x02,0x93,0x2b = cmn w18, w19, asr #0 +0x9f,0x5a,0x95,0x2b = cmn w20, w21, asr #22 +0xdf,0x7e,0x97,0x2b = cmn w22, w23, asr #31 +0x1f,0x00,0x03,0xab = cmn x0, x3 +0xff,0x03,0x04,0xab = cmn xzr, x4 +0xbf,0x00,0x1f,0xab = cmn x5, xzr +0xdf,0x00,0x07,0xab = cmn x6, x7 +0x1f,0x3d,0x09,0xab = cmn x8, x9, lsl #15 +0x5f,0xfd,0x0b,0xab = cmn x10, x11, lsl #63 +0x9f,0x01,0x4d,0xab = cmn x12, x13, lsr #0 +0xdf,0xa5,0x4f,0xab = cmn x14, x15, lsr #41 +0x1f,0xfe,0x51,0xab = cmn x16, x17, lsr #63 +0x5f,0x02,0x93,0xab = cmn x18, x19, asr #0 +0x9f,0xde,0x95,0xab = cmn x20, x21, asr #55 +0xdf,0xfe,0x97,0xab = cmn x22, x23, asr #63 +0x1f,0x00,0x03,0x6b = cmp w0, w3 +0xff,0x03,0x04,0x6b = cmp wzr, w4 +0xbf,0x00,0x1f,0x6b = cmp w5, wzr +0xdf,0x00,0x07,0x6b = cmp w6, w7 +0x1f,0x3d,0x09,0x6b = cmp w8, w9, lsl #15 +0x5f,0x7d,0x0b,0x6b = cmp w10, w11, lsl #31 +0x9f,0x01,0x4d,0x6b = cmp w12, w13, lsr #0 +0xdf,0x55,0x4f,0x6b = cmp w14, w15, lsr #21 +0x1f,0x7e,0x51,0x6b = cmp w16, w17, lsr #31 +0x5f,0x02,0x93,0x6b = cmp w18, w19, asr #0 +0x9f,0x5a,0x95,0x6b = cmp w20, w21, asr #22 +0xdf,0x7e,0x97,0x6b = cmp w22, w23, asr #31 +0x1f,0x00,0x03,0xeb = cmp x0, x3 +0xff,0x03,0x04,0xeb = cmp xzr, x4 +0xbf,0x00,0x1f,0xeb = cmp x5, xzr +0xdf,0x00,0x07,0xeb = cmp x6, x7 +0x1f,0x3d,0x09,0xeb = cmp x8, x9, lsl #15 +0x5f,0xfd,0x0b,0xeb = cmp x10, x11, lsl #63 +0x9f,0x01,0x4d,0xeb = cmp x12, x13, lsr #0 +0xdf,0xa5,0x4f,0xeb = cmp x14, x15, lsr #41 +0x1f,0xfe,0x51,0xeb = cmp x16, x17, lsr #63 +0x5f,0x02,0x93,0xeb = cmp x18, x19, asr #0 +0x9f,0xde,0x95,0xeb = cmp x20, x21, asr #55 +0xdf,0xfe,0x97,0xeb = cmp x22, x23, asr #63 +// 0xfd,0x03,0x1e,0x4b = sub w29, wzr, w30 +// 0xfe,0x03,0x1f,0x4b = sub w30, wzr, wzr +// 0xff,0x03,0x00,0x4b = sub wzr, wzr, w0 +// 0xfc,0x03,0x1b,0x4b = sub w28, wzr, w27 +// 0xfa,0x77,0x19,0x4b = sub w26, wzr, w25, lsl #29 +// 0xf8,0x7f,0x17,0x4b = sub w24, wzr, w23, lsl #31 +// 0xf6,0x03,0x55,0x4b = sub w22, wzr, w21, lsr #0 +// 0xf4,0x07,0x53,0x4b = sub w20, wzr, w19, lsr #1 +// 0xf2,0x7f,0x51,0x4b = sub w18, wzr, w17, lsr #31 +// 0xf0,0x03,0x8f,0x4b = sub w16, wzr, w15, asr #0 +// 0xee,0x33,0x8d,0x4b = sub w14, wzr, w13, asr #12 +// 0xec,0x7f,0x8b,0x4b = sub w12, wzr, w11, asr #31 +// 0xfd,0x03,0x1e,0xcb = sub x29, xzr, x30 +// 0xfe,0x03,0x1f,0xcb = sub x30, xzr, xzr +// 0xff,0x03,0x00,0xcb = sub xzr, xzr, x0 +// 0xfc,0x03,0x1b,0xcb = sub x28, xzr, x27 +// 0xfa,0x77,0x19,0xcb = sub x26, xzr, x25, lsl #29 +// 0xf8,0x7f,0x17,0xcb = sub x24, xzr, x23, lsl #31 +// 0xf6,0x03,0x55,0xcb = sub x22, xzr, x21, lsr #0 +// 0xf4,0x07,0x53,0xcb = sub x20, xzr, x19, lsr #1 +// 0xf2,0x7f,0x51,0xcb = sub x18, xzr, x17, lsr #31 +// 0xf0,0x03,0x8f,0xcb = sub x16, xzr, x15, asr #0 +// 0xee,0x33,0x8d,0xcb = sub x14, xzr, x13, asr #12 +// 0xec,0x7f,0x8b,0xcb = sub x12, xzr, x11, asr #31 +// 0xfd,0x03,0x1e,0x6b = subs w29, wzr, w30 +// 0xfe,0x03,0x1f,0x6b = subs w30, wzr, wzr +// 0xff,0x03,0x00,0x6b = subs wzr, wzr, w0 +// 0xfc,0x03,0x1b,0x6b = subs w28, wzr, w27 +// 0xfa,0x77,0x19,0x6b = subs w26, wzr, w25, lsl #29 +// 0xf8,0x7f,0x17,0x6b = subs w24, wzr, w23, lsl #31 +// 0xf6,0x03,0x55,0x6b = subs w22, wzr, w21, lsr #0 +// 0xf4,0x07,0x53,0x6b = subs w20, wzr, w19, lsr #1 +// 0xf2,0x7f,0x51,0x6b = subs w18, wzr, w17, lsr #31 +// 0xf0,0x03,0x8f,0x6b = subs w16, wzr, w15, asr #0 +// 0xee,0x33,0x8d,0x6b = subs w14, wzr, w13, asr #12 +// 0xec,0x7f,0x8b,0x6b = subs w12, wzr, w11, asr #31 +// 0xfd,0x03,0x1e,0xeb = subs x29, xzr, x30 +// 0xfe,0x03,0x1f,0xeb = subs x30, xzr, xzr +// 0xff,0x03,0x00,0xeb = subs xzr, xzr, x0 +// 0xfc,0x03,0x1b,0xeb = subs x28, xzr, x27 +// 0xfa,0x77,0x19,0xeb = subs x26, xzr, x25, lsl #29 +// 0xf8,0x7f,0x17,0xeb = subs x24, xzr, x23, lsl #31 +// 0xf6,0x03,0x55,0xeb = subs x22, xzr, x21, lsr #0 +// 0xf4,0x07,0x53,0xeb = subs x20, xzr, x19, lsr #1 +// 0xf2,0x7f,0x51,0xeb = subs x18, xzr, x17, lsr #31 +// 0xf0,0x03,0x8f,0xeb = subs x16, xzr, x15, asr #0 +// 0xee,0x33,0x8d,0xeb = subs x14, xzr, x13, asr #12 +// 0xec,0x7f,0x8b,0xeb = subs x12, xzr, x11, asr #31 +0x7d,0x03,0x19,0x1a = adc w29, w27, w25 +0x7f,0x00,0x04,0x1a = adc wzr, w3, w4 +0xe9,0x03,0x0a,0x1a = adc w9, wzr, w10 +0x14,0x00,0x1f,0x1a = adc w20, w0, wzr +0x7d,0x03,0x19,0x9a = adc x29, x27, x25 +0x7f,0x00,0x04,0x9a = adc xzr, x3, x4 +0xe9,0x03,0x0a,0x9a = adc x9, xzr, x10 +0x14,0x00,0x1f,0x9a = adc x20, x0, xzr +0x7d,0x03,0x19,0x3a = adcs w29, w27, w25 +0x7f,0x00,0x04,0x3a = adcs wzr, w3, w4 +0xe9,0x03,0x0a,0x3a = adcs w9, wzr, w10 +0x14,0x00,0x1f,0x3a = adcs w20, w0, wzr +0x7d,0x03,0x19,0xba = adcs x29, x27, x25 +0x7f,0x00,0x04,0xba = adcs xzr, x3, x4 +0xe9,0x03,0x0a,0xba = adcs x9, xzr, x10 +0x14,0x00,0x1f,0xba = adcs x20, x0, xzr +0x7d,0x03,0x19,0x5a = sbc w29, w27, w25 +0x7f,0x00,0x04,0x5a = sbc wzr, w3, w4 +0xe9,0x03,0x0a,0x5a = ngc w9, w10 +0x14,0x00,0x1f,0x5a = sbc w20, w0, wzr +0x7d,0x03,0x19,0xda = sbc x29, x27, x25 +0x7f,0x00,0x04,0xda = sbc xzr, x3, x4 +0xe9,0x03,0x0a,0xda = ngc x9, x10 +0x14,0x00,0x1f,0xda = sbc x20, x0, xzr +0x7d,0x03,0x19,0x7a = sbcs w29, w27, w25 +0x7f,0x00,0x04,0x7a = sbcs wzr, w3, w4 +0xe9,0x03,0x0a,0x7a = ngcs w9, w10 +0x14,0x00,0x1f,0x7a = sbcs w20, w0, wzr +0x7d,0x03,0x19,0xfa = sbcs x29, x27, x25 +0x7f,0x00,0x04,0xfa = sbcs xzr, x3, x4 +0xe9,0x03,0x0a,0xfa = ngcs x9, x10 +0x14,0x00,0x1f,0xfa = sbcs x20, x0, xzr +0xe3,0x03,0x0c,0x5a = ngc w3, w12 +0xff,0x03,0x09,0x5a = ngc wzr, w9 +0xf7,0x03,0x1f,0x5a = ngc w23, wzr +0xfd,0x03,0x1e,0xda = ngc x29, x30 +0xff,0x03,0x00,0xda = ngc xzr, x0 +0xe0,0x03,0x1f,0xda = ngc x0, xzr +0xe3,0x03,0x0c,0x7a = ngcs w3, w12 +0xff,0x03,0x09,0x7a = ngcs wzr, w9 +0xf7,0x03,0x1f,0x7a = ngcs w23, wzr +0xfd,0x03,0x1e,0xfa = ngcs x29, x30 +0xff,0x03,0x00,0xfa = ngcs xzr, x0 +0xe0,0x03,0x1f,0xfa = ngcs x0, xzr +// 0x41,0x10,0x43,0x93 = sbfm x1, x2, #3, #4 +// 0x83,0xfc,0x7f,0x93 = sbfm x3, x4, #63, #63 +// 0xff,0x7f,0x1f,0x13 = sbfm wzr, wzr, #31, #31 +// 0x2c,0x01,0x00,0x13 = sbfm w12, w9, #0, #0 +// 0xa4,0x28,0x4c,0xd3 = ubfm x4, x5, #12, #10 +// 0x9f,0x00,0x40,0xd3 = ubfm xzr, x4, #0, #0 +// 0xe4,0x17,0x7f,0xd3 = ubfm x4, xzr, #63, #5 +// 0xc5,0xfc,0x4c,0xd3 = ubfm x5, x6, #12, #63 +// 0xa4,0x28,0x4c,0xb3 = bfm x4, x5, #12, #10 +// 0x9f,0x00,0x40,0xb3 = bfm xzr, x4, #0, #0 +// 0xe4,0x17,0x7f,0xb3 = bfm x4, xzr, #63, #5 +// 0xc5,0xfc,0x4c,0xb3 = bfm x5, x6, #12, #63 +0x41,0x1c,0x00,0x13 = sxtb w1, w2 +0x7f,0x1c,0x40,0x93 = sxtb xzr, w3 +0x49,0x3d,0x00,0x13 = sxth w9, w10 +0x20,0x3c,0x40,0x93 = sxth x0, w1 +0xc3,0x7f,0x40,0x93 = sxtw x3, w30 +0x41,0x1c,0x00,0x53 = uxtb w1, w2 +// 0x7f,0x1c,0x00,0x53 = uxtb xzr, w3 +0x49,0x3d,0x00,0x53 = uxth w9, w10 +// 0x20,0x3c,0x00,0x53 = uxth x0, w1 +0x43,0x7c,0x00,0x13 = asr w3, w2, #0 +0x49,0x7d,0x1f,0x13 = asr w9, w10, #0x1f +0xb4,0xfe,0x7f,0x93 = asr x20, x21, #0x3f +0xe1,0x7f,0x03,0x13 = asr w1, wzr, #3 +// 0x43,0x7c,0x00,0x53 = lsr w3, w2, #0 +0x49,0x7d,0x1f,0x53 = lsr w9, w10, #0x1f +0xb4,0xfe,0x7f,0xd3 = lsr x20, x21, #0x3f +0xff,0x7f,0x03,0x53 = lsr wzr, wzr, #3 +// 0x43,0x7c,0x00,0x53 = lsl w3, w2, #0 +0x49,0x01,0x01,0x53 = lsl w9, w10, #0x1f +0xb4,0x02,0x41,0xd3 = lsl x20, x21, #0x3f +0xe1,0x73,0x1d,0x53 = lsl w1, wzr, #3 +// 0x49,0x01,0x00,0x13 = sbfiz w9, w10, #0, #1 +0x62,0x00,0x41,0x93 = sbfiz x2, x3, #0x3f, #1 +// 0x93,0xfe,0x40,0x93 = sbfiz x19, x20, #0, #64 +0x49,0xe9,0x7b,0x93 = sbfiz x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x13 = sbfiz w9, w10, #0, #32 +0x8b,0x01,0x01,0x13 = sbfiz w11, w12, #0x1f, #1 +0xcd,0x09,0x03,0x13 = sbfiz w13, w14, #0x1d, #3 +0xff,0x2b,0x76,0x93 = sbfiz xzr, xzr, #0xa, #11 +// 0x49,0x01,0x00,0x13 = sbfx w9, w10, #0, #1 +// 0x62,0xfc,0x7f,0x93 = sbfx x2, x3, #0x3f, #1 +// 0x93,0xfe,0x40,0x93 = sbfx x19, x20, #0, #64 +// 0x49,0xfd,0x45,0x93 = sbfx x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x13 = sbfx w9, w10, #0, #32 +// 0x8b,0x7d,0x1f,0x13 = sbfx w11, w12, #31, #1 +// 0xcd,0x7d,0x1d,0x13 = sbfx w13, w14, #29, #3 +0xff,0x53,0x4a,0x93 = sbfx xzr, xzr, #10, #11 +// 0x49,0x01,0x00,0x33 = bfi w9, w10, #0, #1 +0x62,0x00,0x41,0xb3 = bfi x2, x3, #63, #1 +// 0x93,0xfe,0x40,0xb3 = bfi x19, x20, #0, #64 +0x49,0xe9,0x7b,0xb3 = bfi x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x33 = bfi w9, w10, #0, #32 +0x8b,0x01,0x01,0x33 = bfi w11, w12, #31, #1 +0xcd,0x09,0x03,0x33 = bfi w13, w14, #29, #3 +0xff,0x2b,0x76,0xb3 = bfi xzr, xzr, #10, #11 +// 0x49,0x01,0x00,0x33 = bfxil w9, w10, #0, #1 +0x62,0xfc,0x7f,0xb3 = bfxil x2, x3, #63, #1 +// 0x93,0xfe,0x40,0xb3 = bfxil x19, x20, #0, #64 +0x49,0xfd,0x45,0xb3 = bfxil x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x33 = bfxil w9, w10, #0, #32 +0x8b,0x7d,0x1f,0x33 = bfxil w11, w12, #31, #1 +0xcd,0x7d,0x1d,0x33 = bfxil w13, w14, #29, #3 +0xff,0x53,0x4a,0xb3 = bfxil xzr, xzr, #10, #11 +// 0x49,0x01,0x00,0x53 = ubfiz w9, w10, #0, #1 +// 0x62,0x00,0x41,0xd3 = ubfiz x2, x3, #63, #1 +// 0x93,0xfe,0x40,0xd3 = ubfiz x19, x20, #0, #64 +// 0x49,0xe9,0x7b,0xd3 = ubfiz x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x53 = ubfiz w9, w10, #0, #32 +// 0x8b,0x01,0x01,0x53 = ubfiz w11, w12, #31, #1 +// 0xcd,0x09,0x03,0x53 = ubfiz w13, w14, #29, #3 +0xff,0x2b,0x76,0xd3 = ubfiz xzr, xzr, #10, #11 +// 0x49,0x01,0x00,0x53 = ubfx w9, w10, #0, #1 +// 0x62,0xfc,0x7f,0xd3 = ubfx x2, x3, #63, #1 +// 0x93,0xfe,0x40,0xd3 = ubfx x19, x20, #0, #64 +// 0x49,0xfd,0x45,0xd3 = ubfx x9, x10, #5, #59 +// 0x49,0x7d,0x00,0x53 = ubfx w9, w10, #0, #32 +// 0x8b,0x7d,0x1f,0x53 = ubfx w11, w12, #31, #1 +// 0xcd,0x7d,0x1d,0x53 = ubfx w13, w14, #29, #3 +0xff,0x53,0x4a,0xd3 = ubfx xzr, xzr, #10, #11 +0x05,0x00,0x00,0x34 = cbz w5, #0 +0xe3,0xff,0xff,0xb5 = cbnz x3, #-4 +0xf4,0xff,0x7f,0x34 = cbz w20, #1048572 +0x1f,0x00,0x80,0xb5 = cbnz xzr, #-1048576 +0x00,0x00,0x00,0x54 = b.eq #0 +0xeb,0xff,0xff,0x54 = b.lt #-4 +0xe3,0xff,0x7f,0x54 = b.lo #1048572 +0x20,0x08,0x5f,0x7a = ccmp w1, #31, #0, eq +0x6f,0x28,0x40,0x7a = ccmp w3, #0, #15, hs +0xed,0x2b,0x4f,0x7a = ccmp wzr, #15, #13, hs +0x20,0xd9,0x5f,0xfa = ccmp x9, #31, #0, le +0x6f,0xc8,0x40,0xfa = ccmp x3, #0, #15, gt +0xe7,0x1b,0x45,0xfa = ccmp xzr, #5, #7, ne +0x20,0x08,0x5f,0x3a = ccmn w1, #31, #0, eq +0x6f,0x28,0x40,0x3a = ccmn w3, #0, #15, hs +0xed,0x2b,0x4f,0x3a = ccmn wzr, #15, #13, hs +0x20,0xd9,0x5f,0xba = ccmn x9, #31, #0, le +0x6f,0xc8,0x40,0xba = ccmn x3, #0, #15, gt +0xe7,0x1b,0x45,0xba = ccmn xzr, #5, #7, ne +0x20,0x00,0x5f,0x7a = ccmp w1, wzr, #0, eq +0x6f,0x20,0x40,0x7a = ccmp w3, w0, #15, hs +0xed,0x23,0x4f,0x7a = ccmp wzr, w15, #13, hs +0x20,0xd1,0x5f,0xfa = ccmp x9, xzr, #0, le +0x6f,0xc0,0x40,0xfa = ccmp x3, x0, #15, gt +0xe7,0x13,0x45,0xfa = ccmp xzr, x5, #7, ne +0x20,0x00,0x5f,0x3a = ccmn w1, wzr, #0, eq +0x6f,0x20,0x40,0x3a = ccmn w3, w0, #15, hs +0xed,0x23,0x4f,0x3a = ccmn wzr, w15, #13, hs +0x20,0xd1,0x5f,0xba = ccmn x9, xzr, #0, le +0x6f,0xc0,0x40,0xba = ccmn x3, x0, #15, gt +0xe7,0x13,0x45,0xba = ccmn xzr, x5, #7, ne +0x01,0x10,0x93,0x1a = csel w1, w0, w19, ne +0xbf,0x00,0x89,0x1a = csel wzr, w5, w9, eq +0xe9,0xc3,0x9e,0x1a = csel w9, wzr, w30, gt +0x81,0x43,0x9f,0x1a = csel w1, w28, wzr, mi +0xf3,0xb2,0x9d,0x9a = csel x19, x23, x29, lt +0x7f,0xa0,0x84,0x9a = csel xzr, x3, x4, ge +0xe5,0x23,0x86,0x9a = csel x5, xzr, x6, hs +0x07,0x31,0x9f,0x9a = csel x7, x8, xzr, lo +0x01,0x14,0x93,0x1a = csinc w1, w0, w19, ne +0xbf,0x04,0x89,0x1a = csinc wzr, w5, w9, eq +0xe9,0xc7,0x9e,0x1a = csinc w9, wzr, w30, gt +0x81,0x47,0x9f,0x1a = csinc w1, w28, wzr, mi +0xf3,0xb6,0x9d,0x9a = csinc x19, x23, x29, lt +0x7f,0xa4,0x84,0x9a = csinc xzr, x3, x4, ge +0xe5,0x27,0x86,0x9a = csinc x5, xzr, x6, hs +0x07,0x35,0x9f,0x9a = csinc x7, x8, xzr, lo +0x01,0x10,0x93,0x5a = csinv w1, w0, w19, ne +0xbf,0x00,0x89,0x5a = csinv wzr, w5, w9, eq +0xe9,0xc3,0x9e,0x5a = csinv w9, wzr, w30, gt +0x81,0x43,0x9f,0x5a = csinv w1, w28, wzr, mi +0xf3,0xb2,0x9d,0xda = csinv x19, x23, x29, lt +0x7f,0xa0,0x84,0xda = csinv xzr, x3, x4, ge +0xe5,0x23,0x86,0xda = csinv x5, xzr, x6, hs +0x07,0x31,0x9f,0xda = csinv x7, x8, xzr, lo +0x01,0x14,0x93,0x5a = csneg w1, w0, w19, ne +0xbf,0x04,0x89,0x5a = csneg wzr, w5, w9, eq +0xe9,0xc7,0x9e,0x5a = csneg w9, wzr, w30, gt +0x81,0x47,0x9f,0x5a = csneg w1, w28, wzr, mi +0xf3,0xb6,0x9d,0xda = csneg x19, x23, x29, lt +0x7f,0xa4,0x84,0xda = csneg xzr, x3, x4, ge +0xe5,0x27,0x86,0xda = csneg x5, xzr, x6, hs +0x07,0x35,0x9f,0xda = csneg x7, x8, xzr, lo +// 0xe3,0x17,0x9f,0x1a = csinc w3, wzr, wzr, ne +// 0xe9,0x47,0x9f,0x9a = csinc x9, xzr, xzr, mi +// 0xf4,0x03,0x9f,0x5a = csinv w20, wzr, wzr, eq +// 0xfe,0xb3,0x9f,0xda = csinv x30, xzr, xzr, lt +// 0xa3,0xd4,0x85,0x1a = csinc w3, w5, w5, le +// 0x9f,0xc4,0x84,0x1a = csinc wzr, w4, w4, gt +// 0xe9,0xa7,0x9f,0x1a = csinc w9, wzr, wzr, ge +// 0xa3,0xd4,0x85,0x9a = csinc x3, x5, x5, le +// 0x9f,0xc4,0x84,0x9a = csinc xzr, x4, x4, gt +// 0xe9,0xa7,0x9f,0x9a = csinc x9, xzr, xzr, ge +// 0xa3,0xd0,0x85,0x5a = csinv w3, w5, w5, le +// 0x9f,0xc0,0x84,0x5a = csinv wzr, w4, w4, gt +// 0xe9,0xa3,0x9f,0x5a = csinv w9, wzr, wzr, ge +// 0xa3,0xd0,0x85,0xda = csinv x3, x5, x5, le +// 0x9f,0xc0,0x84,0xda = csinv xzr, x4, x4, gt +// 0xe9,0xa3,0x9f,0xda = csinv x9, xzr, xzr, ge +// 0xa3,0xd4,0x85,0x5a = csneg w3, w5, w5, le +// 0x9f,0xc4,0x84,0x5a = csneg wzr, w4, w4, gt +// 0xe9,0xa7,0x9f,0x5a = csneg w9, wzr, wzr, ge +// 0xa3,0xd4,0x85,0xda = csneg x3, x5, x5, le +// 0x9f,0xc4,0x84,0xda = csneg xzr, x4, x4, gt +// 0xe9,0xa7,0x9f,0xda = csneg x9, xzr, xzr, ge +0xe0,0x00,0xc0,0x5a = rbit w0, w7 +0x72,0x00,0xc0,0xda = rbit x18, x3 +0x31,0x04,0xc0,0x5a = rev16 w17, w1 +0x45,0x04,0xc0,0xda = rev16 x5, x2 +0x12,0x08,0xc0,0x5a = rev w18, w0 +0x34,0x08,0xc0,0xda = rev32 x20, x1 +0xf4,0x0b,0xc0,0xda = rev32 x20, xzr +0x56,0x0c,0xc0,0xda = rev x22, x2 +0xf2,0x0f,0xc0,0xda = rev x18, xzr +0xe7,0x0b,0xc0,0x5a = rev w7, wzr +0x78,0x10,0xc0,0x5a = clz w24, w3 +0x9a,0x10,0xc0,0xda = clz x26, x4 +0xa3,0x14,0xc0,0x5a = cls w3, w5 +0xb4,0x14,0xc0,0xda = cls x20, x5 +0xf8,0x13,0xc0,0x5a = clz w24, wzr +0xf6,0x0f,0xc0,0xda = rev x22, xzr +0xe5,0x40,0xd4,0x1a = crc32b w5, w7, w20 +0xfc,0x47,0xde,0x1a = crc32h w28, wzr, w30 +0x20,0x48,0xc2,0x1a = crc32w w0, w1, w2 +0x27,0x4d,0xd4,0x9a = crc32x w7, w9, x20 +0xa9,0x50,0xc4,0x1a = crc32cb w9, w5, w4 +0x2d,0x56,0xd9,0x1a = crc32ch w13, w17, w25 +0x7f,0x58,0xc5,0x1a = crc32cw wzr, w3, w5 +0x12,0x5e,0xdf,0x9a = crc32cx w18, w16, xzr +0xe0,0x08,0xca,0x1a = udiv w0, w7, w10 +0xc9,0x0a,0xc4,0x9a = udiv x9, x22, x4 +0xac,0x0e,0xc0,0x1a = sdiv w12, w21, w0 +0x4d,0x0c,0xc1,0x9a = sdiv x13, x2, x1 +0x8b,0x21,0xcd,0x1a = lsl w11, w12, w13 +0xee,0x21,0xd0,0x9a = lsl x14, x15, x16 +0x51,0x26,0xd3,0x1a = lsr w17, w18, w19 +0xb4,0x26,0xd6,0x9a = lsr x20, x21, x22 +0x17,0x2b,0xd9,0x1a = asr w23, w24, w25 +0x7a,0x2b,0xdc,0x9a = asr x26, x27, x28 +0x20,0x2c,0xc2,0x1a = ror w0, w1, w2 +0x83,0x2c,0xc5,0x9a = ror x3, x4, x5 +0xe6,0x20,0xc8,0x1a = lsl w6, w7, w8 +0x49,0x21,0xcb,0x9a = lsl x9, x10, x11 +0xac,0x25,0xce,0x1a = lsr w12, w13, w14 +0x0f,0x26,0xd1,0x9a = lsr x15, x16, x17 +0x72,0x2a,0xd4,0x1a = asr w18, w19, w20 +0xd5,0x2a,0xd7,0x9a = asr x21, x22, x23 +0x38,0x2f,0xda,0x1a = ror w24, w25, w26 +0x9b,0x2f,0xdd,0x9a = ror x27, x28, x29 +0x61,0x10,0x07,0x1b = madd w1, w3, w7, w4 +0x1f,0x2c,0x09,0x1b = madd wzr, w0, w9, w11 +0xed,0x13,0x04,0x1b = madd w13, wzr, w4, w4 +0xd3,0x77,0x1f,0x1b = madd w19, w30, wzr, w29 +0xa4,0x7c,0x06,0x1b = mul w4, w5, w6 +0x61,0x10,0x07,0x9b = madd x1, x3, x7, x4 +0x1f,0x2c,0x09,0x9b = madd xzr, x0, x9, x11 +0xed,0x13,0x04,0x9b = madd x13, xzr, x4, x4 +0xd3,0x77,0x1f,0x9b = madd x19, x30, xzr, x29 +0xa4,0x7c,0x06,0x9b = mul x4, x5, x6 +0x61,0x90,0x07,0x1b = msub w1, w3, w7, w4 +0x1f,0xac,0x09,0x1b = msub wzr, w0, w9, w11 +0xed,0x93,0x04,0x1b = msub w13, wzr, w4, w4 +0xd3,0xf7,0x1f,0x1b = msub w19, w30, wzr, w29 +0xa4,0xfc,0x06,0x1b = mneg w4, w5, w6 +0x61,0x90,0x07,0x9b = msub x1, x3, x7, x4 +0x1f,0xac,0x09,0x9b = msub xzr, x0, x9, x11 +0xed,0x93,0x04,0x9b = msub x13, xzr, x4, x4 +0xd3,0xf7,0x1f,0x9b = msub x19, x30, xzr, x29 +0xa4,0xfc,0x06,0x9b = mneg x4, x5, x6 +0xa3,0x24,0x22,0x9b = smaddl x3, w5, w2, x9 +0x5f,0x31,0x2b,0x9b = smaddl xzr, w10, w11, x12 +0xed,0x3f,0x2e,0x9b = smaddl x13, wzr, w14, x15 +0x30,0x4a,0x3f,0x9b = smaddl x16, w17, wzr, x18 +0x93,0x7e,0x35,0x9b = smull x19, w20, w21 +0xa3,0xa4,0x22,0x9b = smsubl x3, w5, w2, x9 +0x5f,0xb1,0x2b,0x9b = smsubl xzr, w10, w11, x12 +0xed,0xbf,0x2e,0x9b = smsubl x13, wzr, w14, x15 +0x30,0xca,0x3f,0x9b = smsubl x16, w17, wzr, x18 +0x93,0xfe,0x35,0x9b = smnegl x19, w20, w21 +0xa3,0x24,0xa2,0x9b = umaddl x3, w5, w2, x9 +0x5f,0x31,0xab,0x9b = umaddl xzr, w10, w11, x12 +0xed,0x3f,0xae,0x9b = umaddl x13, wzr, w14, x15 +0x30,0x4a,0xbf,0x9b = umaddl x16, w17, wzr, x18 +0x93,0x7e,0xb5,0x9b = umull x19, w20, w21 +0xa3,0xa4,0xa2,0x9b = umsubl x3, w5, w2, x9 +0x5f,0xb1,0xab,0x9b = umsubl xzr, w10, w11, x12 +0xed,0xbf,0xae,0x9b = umsubl x13, wzr, w14, x15 +0x30,0xca,0xbf,0x9b = umsubl x16, w17, wzr, x18 +0x93,0xfe,0xb5,0x9b = umnegl x19, w20, w21 +0xbe,0x7f,0x5c,0x9b = smulh x30, x29, x28 +0x7f,0x7f,0x5a,0x9b = smulh xzr, x27, x26 +0xf9,0x7f,0x58,0x9b = smulh x25, xzr, x24 +0xd7,0x7e,0x5f,0x9b = smulh x23, x22, xzr +0xbe,0x7f,0xdc,0x9b = umulh x30, x29, x28 +0x7f,0x7f,0xda,0x9b = umulh xzr, x27, x26 +0xf9,0x7f,0xd8,0x9b = umulh x25, xzr, x24 +0xd7,0x7e,0xdf,0x9b = umulh x23, x22, xzr +0x83,0x7c,0x05,0x1b = mul w3, w4, w5 +0xdf,0x7c,0x07,0x1b = mul wzr, w6, w7 +0xe8,0x7f,0x09,0x1b = mul w8, wzr, w9 +0x6a,0x7d,0x1f,0x1b = mul w10, w11, wzr +0xac,0x7d,0x0e,0x9b = mul x12, x13, x14 +0xff,0x7d,0x10,0x9b = mul xzr, x15, x16 +0xf1,0x7f,0x12,0x9b = mul x17, xzr, x18 +0x93,0x7e,0x1f,0x9b = mul x19, x20, xzr +0xd5,0xfe,0x17,0x1b = mneg w21, w22, w23 +0x1f,0xff,0x19,0x1b = mneg wzr, w24, w25 +0xfa,0xff,0x1b,0x1b = mneg w26, wzr, w27 +0xbc,0xff,0x1f,0x1b = mneg w28, w29, wzr +0xab,0x7d,0x31,0x9b = smull x11, w13, w17 +0xab,0x7d,0xb1,0x9b = umull x11, w13, w17 +0xab,0xfd,0x31,0x9b = smnegl x11, w13, w17 +0xab,0xfd,0xb1,0x9b = umnegl x11, w13, w17 +0x01,0x00,0x00,0xd4 = svc #0 +0xe1,0xff,0x1f,0xd4 = svc #65535 +0x22,0x00,0x00,0xd4 = hvc #1 +0x03,0xdc,0x05,0xd4 = smc #12000 +0x80,0x01,0x20,0xd4 = brk #12 +0x60,0x0f,0x40,0xd4 = hlt #123 +0x41,0x05,0xa0,0xd4 = dcps1 #42 +0x22,0x01,0xa0,0xd4 = dcps2 #9 +0x03,0x7d,0xa0,0xd4 = dcps3 #1000 +0x01,0x00,0xa0,0xd4 = dcps1 +0x02,0x00,0xa0,0xd4 = dcps2 +0x03,0x00,0xa0,0xd4 = dcps3 +0xa3,0x00,0x87,0x13 = extr w3, w5, w7, #0 +0xab,0x7d,0x91,0x13 = extr w11, w13, w17, #31 +0xa3,0x3c,0xc7,0x93 = extr x3, x5, x7, #15 +0xab,0xfd,0xd1,0x93 = extr x11, x13, x17, #63 +// 0xf3,0x62,0xd7,0x93 = extr x19, x23, x23, #24 +// 0xfd,0xff,0xdf,0x93 = extr x29, xzr, xzr, #63 +// 0xa9,0x7d,0x8d,0x13 = extr w9, w13, w13, #31 +0x60,0x20,0x25,0x1e = fcmp s3, s5 +0xe8,0x23,0x20,0x1e = fcmp s31, #0.0 +0xb0,0x23,0x3e,0x1e = fcmpe s29, s30 +0xf8,0x21,0x20,0x1e = fcmpe s15, #0.0 +0x80,0x20,0x6c,0x1e = fcmp d4, d12 +0xe8,0x22,0x60,0x1e = fcmp d23, #0.0 +0x50,0x23,0x76,0x1e = fcmpe d26, d22 +0xb8,0x23,0x60,0x1e = fcmpe d29, #0.0 +0x20,0x04,0x3f,0x1e = fccmp s1, s31, #0, eq +0x6f,0x24,0x20,0x1e = fccmp s3, s0, #15, hs +0xed,0x27,0x2f,0x1e = fccmp s31, s15, #13, hs +0x20,0xd5,0x7f,0x1e = fccmp d9, d31, #0, le +0x6f,0xc4,0x60,0x1e = fccmp d3, d0, #15, gt +0xe7,0x17,0x65,0x1e = fccmp d31, d5, #7, ne +0x30,0x04,0x3f,0x1e = fccmpe s1, s31, #0, eq +0x7f,0x24,0x20,0x1e = fccmpe s3, s0, #15, hs +0xfd,0x27,0x2f,0x1e = fccmpe s31, s15, #13, hs +0x30,0xd5,0x7f,0x1e = fccmpe d9, d31, #0, le +0x7f,0xc4,0x60,0x1e = fccmpe d3, d0, #15, gt +0xf7,0x17,0x65,0x1e = fccmpe d31, d5, #7, ne +0x83,0x5e,0x29,0x1e = fcsel s3, s20, s9, pl +0x49,0x4d,0x6b,0x1e = fcsel d9, d10, d11, mi +0x20,0x40,0x20,0x1e = fmov s0, s1 +0x62,0xc0,0x20,0x1e = fabs s2, s3 +0xa4,0x40,0x21,0x1e = fneg s4, s5 +0xe6,0xc0,0x21,0x1e = fsqrt s6, s7 +0x28,0xc1,0x22,0x1e = fcvt d8, s9 +0x6a,0xc1,0x23,0x1e = fcvt h10, s11 +0xac,0x41,0x24,0x1e = frintn s12, s13 +0xee,0xc1,0x24,0x1e = frintp s14, s15 +0x30,0x42,0x25,0x1e = frintm s16, s17 +0x72,0xc2,0x25,0x1e = frintz s18, s19 +0xb4,0x42,0x26,0x1e = frinta s20, s21 +0xf6,0x42,0x27,0x1e = frintx s22, s23 +0x38,0xc3,0x27,0x1e = frinti s24, s25 +0x20,0x40,0x60,0x1e = fmov d0, d1 +0x62,0xc0,0x60,0x1e = fabs d2, d3 +0xa4,0x40,0x61,0x1e = fneg d4, d5 +0xe6,0xc0,0x61,0x1e = fsqrt d6, d7 +0x28,0x41,0x62,0x1e = fcvt s8, d9 +0x6a,0xc1,0x63,0x1e = fcvt h10, d11 +0xac,0x41,0x64,0x1e = frintn d12, d13 +0xee,0xc1,0x64,0x1e = frintp d14, d15 +0x30,0x42,0x65,0x1e = frintm d16, d17 +0x72,0xc2,0x65,0x1e = frintz d18, d19 +0xb4,0x42,0x66,0x1e = frinta d20, d21 +0xf6,0x42,0x67,0x1e = frintx d22, d23 +0x38,0xc3,0x67,0x1e = frinti d24, d25 +0x7a,0x43,0xe2,0x1e = fcvt s26, h27 +0xbc,0xc3,0xe2,0x1e = fcvt d28, h29 +0x74,0x0a,0x31,0x1e = fmul s20, s19, s17 +0x41,0x18,0x23,0x1e = fdiv s1, s2, s3 +0xa4,0x28,0x26,0x1e = fadd s4, s5, s6 +0x07,0x39,0x29,0x1e = fsub s7, s8, s9 +0x6a,0x49,0x2c,0x1e = fmax s10, s11, s12 +0xcd,0x59,0x2f,0x1e = fmin s13, s14, s15 +0x30,0x6a,0x32,0x1e = fmaxnm s16, s17, s18 +0x93,0x7a,0x35,0x1e = fminnm s19, s20, s21 +0xf6,0x8a,0x38,0x1e = fnmul s22, s23, s24 +0x74,0x0a,0x71,0x1e = fmul d20, d19, d17 +0x41,0x18,0x63,0x1e = fdiv d1, d2, d3 +0xa4,0x28,0x66,0x1e = fadd d4, d5, d6 +0x07,0x39,0x69,0x1e = fsub d7, d8, d9 +0x6a,0x49,0x6c,0x1e = fmax d10, d11, d12 +0xcd,0x59,0x6f,0x1e = fmin d13, d14, d15 +0x30,0x6a,0x72,0x1e = fmaxnm d16, d17, d18 +0x93,0x7a,0x75,0x1e = fminnm d19, d20, d21 +0xf6,0x8a,0x78,0x1e = fnmul d22, d23, d24 +0xa3,0x7c,0x06,0x1f = fmadd s3, s5, s6, s31 +0xa3,0x5d,0x40,0x1f = fmadd d3, d13, d0, d23 +0xa3,0xfc,0x06,0x1f = fmsub s3, s5, s6, s31 +0xa3,0xdd,0x40,0x1f = fmsub d3, d13, d0, d23 +0xa3,0x7c,0x26,0x1f = fnmadd s3, s5, s6, s31 +0xa3,0x5d,0x60,0x1f = fnmadd d3, d13, d0, d23 +0xa3,0xfc,0x26,0x1f = fnmsub s3, s5, s6, s31 +0xa3,0xdd,0x60,0x1f = fnmsub d3, d13, d0, d23 +0xa3,0xfc,0x18,0x1e = fcvtzs w3, s5, #1 +0x9f,0xce,0x18,0x1e = fcvtzs wzr, s20, #13 +0x13,0x80,0x18,0x1e = fcvtzs w19, s0, #32 +0xa3,0xfc,0x18,0x9e = fcvtzs x3, s5, #1 +0xcc,0x4f,0x18,0x9e = fcvtzs x12, s30, #45 +0x13,0x00,0x18,0x9e = fcvtzs x19, s0, #64 +0xa3,0xfc,0x58,0x1e = fcvtzs w3, d5, #1 +0x9f,0xce,0x58,0x1e = fcvtzs wzr, d20, #13 +0x13,0x80,0x58,0x1e = fcvtzs w19, d0, #32 +0xa3,0xfc,0x58,0x9e = fcvtzs x3, d5, #1 +0xcc,0x4f,0x58,0x9e = fcvtzs x12, d30, #45 +0x13,0x00,0x58,0x9e = fcvtzs x19, d0, #64 +0xa3,0xfc,0x19,0x1e = fcvtzu w3, s5, #1 +0x9f,0xce,0x19,0x1e = fcvtzu wzr, s20, #13 +0x13,0x80,0x19,0x1e = fcvtzu w19, s0, #32 +0xa3,0xfc,0x19,0x9e = fcvtzu x3, s5, #1 +0xcc,0x4f,0x19,0x9e = fcvtzu x12, s30, #45 +0x13,0x00,0x19,0x9e = fcvtzu x19, s0, #64 +0xa3,0xfc,0x59,0x1e = fcvtzu w3, d5, #1 +0x9f,0xce,0x59,0x1e = fcvtzu wzr, d20, #13 +0x13,0x80,0x59,0x1e = fcvtzu w19, d0, #32 +0xa3,0xfc,0x59,0x9e = fcvtzu x3, d5, #1 +0xcc,0x4f,0x59,0x9e = fcvtzu x12, d30, #45 +0x13,0x00,0x59,0x9e = fcvtzu x19, d0, #64 +0x77,0xfe,0x02,0x1e = scvtf s23, w19, #1 +0xff,0xb3,0x02,0x1e = scvtf s31, wzr, #20 +0x0e,0x80,0x02,0x1e = scvtf s14, w0, #32 +0x77,0xfe,0x02,0x9e = scvtf s23, x19, #1 +0xff,0xb3,0x02,0x9e = scvtf s31, xzr, #20 +0x0e,0x00,0x02,0x9e = scvtf s14, x0, #64 +0x77,0xfe,0x42,0x1e = scvtf d23, w19, #1 +0xff,0xb3,0x42,0x1e = scvtf d31, wzr, #20 +0x0e,0x80,0x42,0x1e = scvtf d14, w0, #32 +0x77,0xfe,0x42,0x9e = scvtf d23, x19, #1 +0xff,0xb3,0x42,0x9e = scvtf d31, xzr, #20 +0x0e,0x00,0x42,0x9e = scvtf d14, x0, #64 +0x77,0xfe,0x03,0x1e = ucvtf s23, w19, #1 +0xff,0xb3,0x03,0x1e = ucvtf s31, wzr, #20 +0x0e,0x80,0x03,0x1e = ucvtf s14, w0, #32 +0x77,0xfe,0x03,0x9e = ucvtf s23, x19, #1 +0xff,0xb3,0x03,0x9e = ucvtf s31, xzr, #20 +0x0e,0x00,0x03,0x9e = ucvtf s14, x0, #64 +0x77,0xfe,0x43,0x1e = ucvtf d23, w19, #1 +0xff,0xb3,0x43,0x1e = ucvtf d31, wzr, #20 +0x0e,0x80,0x43,0x1e = ucvtf d14, w0, #32 +0x77,0xfe,0x43,0x9e = ucvtf d23, x19, #1 +0xff,0xb3,0x43,0x9e = ucvtf d31, xzr, #20 +0x0e,0x00,0x43,0x9e = ucvtf d14, x0, #64 +0xe3,0x03,0x20,0x1e = fcvtns w3, s31 +0x9f,0x01,0x20,0x9e = fcvtns xzr, s12 +0x9f,0x01,0x21,0x1e = fcvtnu wzr, s12 +0x00,0x00,0x21,0x9e = fcvtnu x0, s0 +0x3f,0x01,0x28,0x1e = fcvtps wzr, s9 +0x8c,0x02,0x28,0x9e = fcvtps x12, s20 +0xfe,0x02,0x29,0x1e = fcvtpu w30, s23 +0x7d,0x00,0x29,0x9e = fcvtpu x29, s3 +0x62,0x00,0x30,0x1e = fcvtms w2, s3 +0xa4,0x00,0x30,0x9e = fcvtms x4, s5 +0xe6,0x00,0x31,0x1e = fcvtmu w6, s7 +0x28,0x01,0x31,0x9e = fcvtmu x8, s9 +0x6a,0x01,0x38,0x1e = fcvtzs w10, s11 +0xac,0x01,0x38,0x9e = fcvtzs x12, s13 +0xee,0x01,0x39,0x1e = fcvtzu w14, s15 +0x0f,0x02,0x39,0x9e = fcvtzu x15, s16 +0x51,0x02,0x22,0x1e = scvtf s17, w18 +0x93,0x02,0x22,0x9e = scvtf s19, x20 +0xd5,0x02,0x23,0x1e = ucvtf s21, w22 +0x17,0x03,0x22,0x9e = scvtf s23, x24 +0x59,0x03,0x24,0x1e = fcvtas w25, s26 +0x9b,0x03,0x24,0x9e = fcvtas x27, s28 +0xdd,0x03,0x25,0x1e = fcvtau w29, s30 +0x1f,0x00,0x25,0x9e = fcvtau xzr, s0 +0xe3,0x03,0x60,0x1e = fcvtns w3, d31 +0x9f,0x01,0x60,0x9e = fcvtns xzr, d12 +0x9f,0x01,0x61,0x1e = fcvtnu wzr, d12 +0x00,0x00,0x61,0x9e = fcvtnu x0, d0 +0x3f,0x01,0x68,0x1e = fcvtps wzr, d9 +0x8c,0x02,0x68,0x9e = fcvtps x12, d20 +0xfe,0x02,0x69,0x1e = fcvtpu w30, d23 +0x7d,0x00,0x69,0x9e = fcvtpu x29, d3 +0x62,0x00,0x70,0x1e = fcvtms w2, d3 +0xa4,0x00,0x70,0x9e = fcvtms x4, d5 +0xe6,0x00,0x71,0x1e = fcvtmu w6, d7 +0x28,0x01,0x71,0x9e = fcvtmu x8, d9 +0x6a,0x01,0x78,0x1e = fcvtzs w10, d11 +0xac,0x01,0x78,0x9e = fcvtzs x12, d13 +0xee,0x01,0x79,0x1e = fcvtzu w14, d15 +0x0f,0x02,0x79,0x9e = fcvtzu x15, d16 +0x51,0x02,0x62,0x1e = scvtf d17, w18 +0x93,0x02,0x62,0x9e = scvtf d19, x20 +0xd5,0x02,0x63,0x1e = ucvtf d21, w22 +0x17,0x03,0x63,0x9e = ucvtf d23, x24 +0x59,0x03,0x64,0x1e = fcvtas w25, d26 +0x9b,0x03,0x64,0x9e = fcvtas x27, d28 +0xdd,0x03,0x65,0x1e = fcvtau w29, d30 +0x1f,0x00,0x65,0x9e = fcvtau xzr, d0 +0x23,0x01,0x26,0x1e = fmov w3, s9 +0x69,0x00,0x27,0x1e = fmov s9, w3 +0xf4,0x03,0x66,0x9e = fmov x20, d31 +0xe1,0x01,0x67,0x9e = fmov d1, x15 +0x83,0x01,0xae,0x9e = fmov x3, v12.d[1] +0x61,0x02,0xaf,0x9e = fmov v1.d[1], x19 +0xe3,0x03,0xaf,0x9e = fmov v3.d[1], xzr +0x02,0x10,0x28,0x1e = fmov s2, #0.12500000 +0x03,0x10,0x2e,0x1e = fmov s3, #1.00000000 +0x1e,0x10,0x66,0x1e = fmov d30, #16.00000000 +0x04,0x30,0x2e,0x1e = fmov s4, #1.06250000 +0x0a,0xf0,0x6f,0x1e = fmov d10, #1.93750000 +0x0c,0x10,0x3e,0x1e = fmov s12, #-1.00000000 +0x10,0x30,0x64,0x1e = fmov d16, #8.50000000 +0xe0,0xff,0x7f,0x18 = ldr w0, #1048572 +0x0a,0x00,0x80,0x58 = ldr x10, #-1048576 +0x02,0x10,0x28,0x1e = fmov s2, #0.12500000 +0x03,0x10,0x2e,0x1e = fmov s3, #1.00000000 +0x1e,0x10,0x66,0x1e = fmov d30, #16.00000000 +0x04,0x30,0x2e,0x1e = fmov s4, #1.06250000 +0x0a,0xf0,0x6f,0x1e = fmov d10, #1.93750000 +0x0c,0x10,0x3e,0x1e = fmov s12, #-1.00000000 +0x10,0x30,0x64,0x1e = fmov d16, #8.50000000 +0x62,0x7c,0x01,0x08 = stxrb w1, w2, [x3] +0x83,0x7c,0x02,0x48 = stxrh w2, w3, [x4] +0xe4,0x7f,0x1f,0x88 = stxr wzr, w4, [sp] +0xe6,0x7c,0x05,0xc8 = stxr w5, x6, [x7] +0x27,0x7d,0x5f,0x08 = ldxrb w7, [x9] +0x5f,0x7d,0x5f,0x48 = ldxrh wzr, [x10] +0xe9,0x7f,0x5f,0x88 = ldxr w9, [sp] +0x6a,0x7d,0x5f,0xc8 = ldxr x10, [x11] +0xcc,0x35,0x2b,0x88 = stxp w11, w12, w13, [x14] +0xf7,0x39,0x3f,0xc8 = stxp wzr, x23, x14, [x15] +0xec,0x7f,0x7f,0x88 = ldxp w12, wzr, [sp] +0xed,0x39,0x7f,0xc8 = ldxp x13, x14, [x15] +0x0f,0xfe,0x0e,0x08 = stlxrb w14, w15, [x16] +0x30,0xfe,0x0f,0x48 = stlxrh w15, w16, [x17] +0xf1,0xff,0x1f,0x88 = stlxr wzr, w17, [sp] +0x93,0xfe,0x12,0xc8 = stlxr w18, x19, [x20] +0xb3,0xfe,0x5f,0x08 = ldaxrb w19, [x21] +0xf4,0xff,0x5f,0x48 = ldaxrh w20, [sp] +0xdf,0xfe,0x5f,0x88 = ldaxr wzr, [x22] +0xf5,0xfe,0x5f,0xc8 = ldaxr x21, [x23] +0x16,0xdf,0x3f,0x88 = stlxp wzr, w22, w23, [x24] +0xfa,0xef,0x39,0xc8 = stlxp w25, x26, x27, [sp] +0xfa,0xff,0x7f,0x88 = ldaxp w26, wzr, [sp] +0xdb,0xf3,0x7f,0xc8 = ldaxp x27, x28, [x30] +0xfb,0xff,0x9f,0x08 = stlrb w27, [sp] +0x1c,0xfc,0x9f,0x48 = stlrh w28, [x0] +0x3f,0xfc,0x9f,0x88 = stlr wzr, [x1] +0x5e,0xfc,0x9f,0xc8 = stlr x30, [x2] +0xfd,0xff,0xdf,0x08 = ldarb w29, [sp] +0x1e,0xfc,0xdf,0x48 = ldarh w30, [x0] +0x3f,0xfc,0xdf,0x88 = ldar wzr, [x1] +0x41,0xfc,0xdf,0xc8 = ldar x1, [x2] +0x16,0xdf,0x3f,0x88 = stlxp wzr, w22, w23, [x24] +0xe9,0x03,0x00,0x38 = sturb w9, [sp] +0x9f,0xf1,0x0f,0x78 = sturh wzr, [x12, #255] +0x10,0x00,0x10,0xb8 = stur w16, [x0, #-256] +0xdc,0x11,0x00,0xf8 = stur x28, [x14, #1] +0x81,0xf2,0x4f,0x38 = ldurb w1, [x20, #255] +0x34,0xf0,0x4f,0x78 = ldurh w20, [x1, #255] +0xec,0xf3,0x4f,0xb8 = ldur w12, [sp, #255] +0x9f,0xf1,0x4f,0xf8 = ldur xzr, [x12, #255] +0xe9,0x00,0x90,0x38 = ldursb x9, [x7, #-256] +0x71,0x02,0x90,0x78 = ldursh x17, [x19, #-256] +0xf4,0x01,0x90,0xb8 = ldursw x20, [x15, #-256] +0x4d,0x00,0x80,0xb8 = ldursw x13, [x2] +0xe2,0x03,0x90,0xf8 = prfum pldl2keep, [sp, #-256] +0x33,0x00,0xd0,0x38 = ldursb w19, [x1, #-256] +0xaf,0x02,0xd0,0x78 = ldursh w15, [x21, #-256] +0xe0,0x13,0x00,0x3c = stur b0, [sp, #1] +0x8c,0xf1,0x1f,0x7c = stur h12, [x12, #-1] +0x0f,0xf0,0x0f,0xbc = stur s15, [x0, #255] +0xbf,0x90,0x01,0xfc = stur d31, [x5, #25] +0xa9,0x00,0x80,0x3c = stur q9, [x5] +0xe3,0x03,0x40,0x3c = ldur b3, [sp] +0x85,0x00,0x50,0x7c = ldur h5, [x4, #-256] +0x87,0xf1,0x5f,0xbc = ldur s7, [x12, #-1] +0x6b,0x42,0x40,0xfc = ldur d11, [x19, #4] +0x2d,0x20,0xc0,0x3c = ldur q13, [x1, #2] +0x00,0x00,0x40,0xf9 = ldr x0, [x0] +0xa4,0x03,0x40,0xf9 = ldr x4, [x29] +0x9e,0xfd,0x7f,0xf9 = ldr x30, [x12, #32760] +0xf4,0x07,0x40,0xf9 = ldr x20, [sp, #8] +0xff,0x03,0x40,0xf9 = ldr xzr, [sp] +0xe2,0x03,0x40,0xb9 = ldr w2, [sp] +// 0xf1,0xff,0x7f,0xb9 = ldr w17, [sp, #0x6660] +0x4d,0x04,0x40,0xb9 = ldr w13, [x2, #4] +0xa2,0x04,0x80,0xb9 = ldrsw x2, [x5, #4] +// 0xf7,0xff,0xbf,0xb9 = ldrsw x23, [sp, #0x6660] +0x82,0x00,0x40,0x79 = ldrh w2, [x4] +0xd7,0xfc,0xff,0x79 = ldrsh w23, [x6, #8190] +0xff,0x07,0xc0,0x79 = ldrsh wzr, [sp, #2] +0x5d,0x04,0x80,0x79 = ldrsh x29, [x2, #2] +0x7a,0xe4,0x41,0x39 = ldrb w26, [x3, #121] +0x4c,0x00,0x40,0x39 = ldrb w12, [x2] +0xfb,0xff,0xff,0x39 = ldrsb w27, [sp, #0xfff] +0xff,0x01,0x80,0x39 = ldrsb xzr, [x15] +0xfe,0x03,0x00,0xf9 = str x30, [sp] +// 0x94,0xfc,0x3f,0xb9 = str w20, [x4, #0x6660] +0x54,0x1d,0x00,0x79 = strh w20, [x10, #14] +0xf1,0xff,0x3f,0x79 = strh w17, [sp, #8190] +0x77,0xfc,0x3f,0x39 = strb w23, [x3, #0xfff] +0x5f,0x00,0x00,0x39 = strb wzr, [x2] +0xe0,0x07,0x80,0xf9 = prfm pldl1keep, [sp, #8] +// 0x61,0x00,0x80,0xf9 = prfm pldl1strm, [x3, #0] +0xa2,0x08,0x80,0xf9 = prfm pldl2keep, [x5, #16] +// 0x43,0x00,0x80,0xf9 = prfm pldl2strm, [x2, #0] +// 0xa4,0x00,0x80,0xf9 = prfm pldl3keep, [x5, #0] +// 0xc5,0x00,0x80,0xf9 = prfm pldl3strm, [x6, #0] +0xe8,0x07,0x80,0xf9 = prfm plil1keep, [sp, #8] +// 0x69,0x00,0x80,0xf9 = prfm plil1strm, [x3, #0] +0xaa,0x08,0x80,0xf9 = prfm plil2keep, [x5, #16] +// 0x4b,0x00,0x80,0xf9 = prfm plil2strm, [x2, #0] +// 0xac,0x00,0x80,0xf9 = prfm plil3keep, [x5, #0] +// 0xcd,0x00,0x80,0xf9 = prfm plil3strm, [x6, #0] +0xf0,0x07,0x80,0xf9 = prfm pstl1keep, [sp, #8] +// 0x71,0x00,0x80,0xf9 = prfm pstl1strm, [x3, #0] +0xb2,0x08,0x80,0xf9 = prfm pstl2keep, [x5, #16] +// 0x53,0x00,0x80,0xf9 = prfm pstl2strm, [x2, #0] +// 0xb4,0x00,0x80,0xf9 = prfm pstl3keep, [x5, #0] +// 0xd5,0x00,0x80,0xf9 = prfm pstl3strm, [x6, #0] +// 0xef,0x03,0x80,0xf9 = prfm #15, [sp, #0] +0xff,0xff,0x7f,0x3d = ldr b31, [sp, #0xfff] +0x54,0xfc,0x7f,0x7d = ldr h20, [x2, #8190] +// 0x6a,0xfe,0x7f,0xbd = ldr s10, [x19, #0x6660] +0x43,0xfd,0x7f,0xfd = ldr d3, [x10, #32760] +0xec,0xff,0xbf,0x3d = str q12, [sp, #65520] +0xe3,0x6b,0x65,0x38 = ldrb w3, [sp, x5] +0x69,0x7b,0x66,0x38 = ldrb w9, [x27, x6, lsl #0] +0xca,0x6b,0xe7,0x38 = ldrsb w10, [x30, x7] +0xab,0xeb,0x63,0x38 = ldrb w11, [x29, x3, sxtx] +0x8c,0xfb,0x3f,0x38 = strb w12, [x28, xzr, sxtx #0] +0x4e,0x4b,0x66,0x38 = ldrb w14, [x26, w6, uxtw] +0x2f,0x5b,0xe7,0x38 = ldrsb w15, [x25, w7, uxtw #0] +0xf1,0xca,0x69,0x38 = ldrb w17, [x23, w9, sxtw] +0xd2,0xda,0xaa,0x38 = ldrsb x18, [x22, w10, sxtw #0] +0xe3,0x6b,0xe5,0x78 = ldrsh w3, [sp, x5] +0x69,0x6b,0xe6,0x78 = ldrsh w9, [x27, x6] +0xca,0x7b,0x67,0x78 = ldrh w10, [x30, x7, lsl #1] +0xab,0xeb,0x23,0x78 = strh w11, [x29, x3, sxtx] +0x8c,0xeb,0x7f,0x78 = ldrh w12, [x28, xzr, sxtx] +0x6d,0xfb,0xa5,0x78 = ldrsh x13, [x27, x5, sxtx #1] +0x4e,0x4b,0x66,0x78 = ldrh w14, [x26, w6, uxtw] +0x2f,0x4b,0x67,0x78 = ldrh w15, [x25, w7, uxtw] +0x10,0x5b,0xe8,0x78 = ldrsh w16, [x24, w8, uxtw #1] +0xf1,0xca,0x69,0x78 = ldrh w17, [x23, w9, sxtw] +0xd2,0xca,0x6a,0x78 = ldrh w18, [x22, w10, sxtw] +0xb3,0xda,0x3f,0x78 = strh w19, [x21, wzr, sxtw #1] +0xe3,0x6b,0x65,0xb8 = ldr w3, [sp, x5] +0x69,0x6b,0x66,0xbc = ldr s9, [x27, x6] +0xca,0x7b,0x67,0xb8 = ldr w10, [x30, x7, lsl #2] +0xab,0xeb,0x63,0xb8 = ldr w11, [x29, x3, sxtx] +0x8c,0xeb,0x3f,0xbc = str s12, [x28, xzr, sxtx] +0x6d,0xfb,0x25,0xb8 = str w13, [x27, x5, sxtx #2] +0x4e,0x4b,0x26,0xb8 = str w14, [x26, w6, uxtw] +0x2f,0x4b,0x67,0xb8 = ldr w15, [x25, w7, uxtw] +0x10,0x5b,0x68,0xb8 = ldr w16, [x24, w8, uxtw #2] +0xf1,0xca,0xa9,0xb8 = ldrsw x17, [x23, w9, sxtw] +0xd2,0xca,0x6a,0xb8 = ldr w18, [x22, w10, sxtw] +0xb3,0xda,0xbf,0xb8 = ldrsw x19, [x21, wzr, sxtw #2] +0xe3,0x6b,0x65,0xf8 = ldr x3, [sp, x5] +0x69,0x6b,0x26,0xf8 = str x9, [x27, x6] +0xca,0x7b,0x67,0xfc = ldr d10, [x30, x7, lsl #3] +0xab,0xeb,0x23,0xf8 = str x11, [x29, x3, sxtx] +0x8c,0xeb,0x7f,0xf8 = ldr x12, [x28, xzr, sxtx] +0x6d,0xfb,0x65,0xf8 = ldr x13, [x27, x5, sxtx #3] +0x40,0x4b,0xa6,0xf8 = prfm pldl1keep, [x26, w6, uxtw] +0x2f,0x4b,0x67,0xf8 = ldr x15, [x25, w7, uxtw] +0x10,0x5b,0x68,0xf8 = ldr x16, [x24, w8, uxtw #3] +0xf1,0xca,0x69,0xf8 = ldr x17, [x23, w9, sxtw] +0xd2,0xca,0x6a,0xf8 = ldr x18, [x22, w10, sxtw] +0xb3,0xda,0x3f,0xfc = str d19, [x21, wzr, sxtw #3] +// 0x06,0x68,0xa5,0xf8 = prfm #6, [x0, x5, lsl #0] +0xe3,0x6b,0xe5,0x3c = ldr q3, [sp, x5] +0x69,0x6b,0xe6,0x3c = ldr q9, [x27, x6] +0xca,0x7b,0xe7,0x3c = ldr q10, [x30, x7, lsl #4] +0xab,0xeb,0xa3,0x3c = str q11, [x29, x3, sxtx] +0x8c,0xeb,0xbf,0x3c = str q12, [x28, xzr, sxtx] +0x6d,0xfb,0xa5,0x3c = str q13, [x27, x5, sxtx #4] +0x4e,0x4b,0xe6,0x3c = ldr q14, [x26, w6, uxtw] +0x2f,0x4b,0xe7,0x3c = ldr q15, [x25, w7, uxtw] +0x10,0x5b,0xe8,0x3c = ldr q16, [x24, w8, uxtw #4] +0xf1,0xca,0xe9,0x3c = ldr q17, [x23, w9, sxtw] +0xd2,0xca,0xaa,0x3c = str q18, [x22, w10, sxtw] +0xb3,0xda,0xff,0x3c = ldr q19, [x21, wzr, sxtw #4] +0x49,0xf4,0x0f,0x38 = strb w9, [x2], #255 +0x6a,0x14,0x00,0x38 = strb w10, [x3], #1 +0x6a,0x04,0x10,0x38 = strb w10, [x3], #-256 +0x49,0xf4,0x0f,0x78 = strh w9, [x2], #255 +0x49,0x14,0x00,0x78 = strh w9, [x2], #1 +0x6a,0x04,0x10,0x78 = strh w10, [x3], #-256 +0xf3,0xf7,0x0f,0xb8 = str w19, [sp], #255 +0xd4,0x17,0x00,0xb8 = str w20, [x30], #1 +0x95,0x05,0x10,0xb8 = str w21, [x12], #-256 +0x3f,0xf5,0x0f,0xf8 = str xzr, [x9], #255 +0x62,0x14,0x00,0xf8 = str x2, [x3], #1 +0x93,0x05,0x10,0xf8 = str x19, [x12], #-256 +0x49,0xf4,0x4f,0x38 = ldrb w9, [x2], #255 +0x6a,0x14,0x40,0x38 = ldrb w10, [x3], #1 +0x6a,0x04,0x50,0x38 = ldrb w10, [x3], #-256 +0x49,0xf4,0x4f,0x78 = ldrh w9, [x2], #255 +0x49,0x14,0x40,0x78 = ldrh w9, [x2], #1 +0x6a,0x04,0x50,0x78 = ldrh w10, [x3], #-256 +0xf3,0xf7,0x4f,0xb8 = ldr w19, [sp], #255 +0xd4,0x17,0x40,0xb8 = ldr w20, [x30], #1 +0x95,0x05,0x50,0xb8 = ldr w21, [x12], #-256 +0x3f,0xf5,0x4f,0xf8 = ldr xzr, [x9], #255 +0x62,0x14,0x40,0xf8 = ldr x2, [x3], #1 +0x93,0x05,0x50,0xf8 = ldr x19, [x12], #-256 +0x3f,0xf5,0x8f,0x38 = ldrsb xzr, [x9], #255 +0x62,0x14,0x80,0x38 = ldrsb x2, [x3], #1 +0x93,0x05,0x90,0x38 = ldrsb x19, [x12], #-256 +0x3f,0xf5,0x8f,0x78 = ldrsh xzr, [x9], #255 +0x62,0x14,0x80,0x78 = ldrsh x2, [x3], #1 +0x93,0x05,0x90,0x78 = ldrsh x19, [x12], #-256 +0x3f,0xf5,0x8f,0xb8 = ldrsw xzr, [x9], #255 +0x62,0x14,0x80,0xb8 = ldrsw x2, [x3], #1 +0x93,0x05,0x90,0xb8 = ldrsw x19, [x12], #-256 +0x3f,0xf5,0xcf,0x38 = ldrsb wzr, [x9], #255 +0x62,0x14,0xc0,0x38 = ldrsb w2, [x3], #1 +0x93,0x05,0xd0,0x38 = ldrsb w19, [x12], #-256 +0x3f,0xf5,0xcf,0x78 = ldrsh wzr, [x9], #255 +0x62,0x14,0xc0,0x78 = ldrsh w2, [x3], #1 +0x93,0x05,0xd0,0x78 = ldrsh w19, [x12], #-256 +0x00,0xf4,0x0f,0x3c = str b0, [x0], #255 +0x63,0x14,0x00,0x3c = str b3, [x3], #1 +0xe5,0x07,0x10,0x3c = str b5, [sp], #-256 +0x4a,0xf5,0x0f,0x7c = str h10, [x10], #255 +0xed,0x16,0x00,0x7c = str h13, [x23], #1 +0xef,0x07,0x10,0x7c = str h15, [sp], #-256 +0x94,0xf6,0x0f,0xbc = str s20, [x20], #255 +0xf7,0x16,0x00,0xbc = str s23, [x23], #1 +0x19,0x04,0x10,0xbc = str s25, [x0], #-256 +0x94,0xf6,0x0f,0xfc = str d20, [x20], #255 +0xf7,0x16,0x00,0xfc = str d23, [x23], #1 +0x19,0x04,0x10,0xfc = str d25, [x0], #-256 +0x00,0xf4,0x4f,0x3c = ldr b0, [x0], #255 +0x63,0x14,0x40,0x3c = ldr b3, [x3], #1 +0xe5,0x07,0x50,0x3c = ldr b5, [sp], #-256 +0x4a,0xf5,0x4f,0x7c = ldr h10, [x10], #255 +0xed,0x16,0x40,0x7c = ldr h13, [x23], #1 +0xef,0x07,0x50,0x7c = ldr h15, [sp], #-256 +0x94,0xf6,0x4f,0xbc = ldr s20, [x20], #255 +0xf7,0x16,0x40,0xbc = ldr s23, [x23], #1 +0x19,0x04,0x50,0xbc = ldr s25, [x0], #-256 +0x94,0xf6,0x4f,0xfc = ldr d20, [x20], #255 +0xf7,0x16,0x40,0xfc = ldr d23, [x23], #1 +0x19,0x04,0x50,0xfc = ldr d25, [x0], #-256 +0x34,0xf4,0xcf,0x3c = ldr q20, [x1], #255 +0x37,0x15,0xc0,0x3c = ldr q23, [x9], #1 +0x99,0x06,0xd0,0x3c = ldr q25, [x20], #-256 +0x2a,0xf4,0x8f,0x3c = str q10, [x1], #255 +0xf6,0x17,0x80,0x3c = str q22, [sp], #1 +0x95,0x06,0x90,0x3c = str q21, [x20], #-256 +0x83,0x0c,0x40,0xf8 = ldr x3, [x4, #0]! +0xff,0x0f,0x40,0xf8 = ldr xzr, [sp, #0]! +0x49,0xfc,0x0f,0x38 = strb w9, [x2, #255]! +0x6a,0x1c,0x00,0x38 = strb w10, [x3, #1]! +0x6a,0x0c,0x10,0x38 = strb w10, [x3, #-256]! +0x49,0xfc,0x0f,0x78 = strh w9, [x2, #255]! +0x49,0x1c,0x00,0x78 = strh w9, [x2, #1]! +0x6a,0x0c,0x10,0x78 = strh w10, [x3, #-256]! +0xf3,0xff,0x0f,0xb8 = str w19, [sp, #255]! +0xd4,0x1f,0x00,0xb8 = str w20, [x30, #1]! +0x95,0x0d,0x10,0xb8 = str w21, [x12, #-256]! +0x3f,0xfd,0x0f,0xf8 = str xzr, [x9, #255]! +0x62,0x1c,0x00,0xf8 = str x2, [x3, #1]! +0x93,0x0d,0x10,0xf8 = str x19, [x12, #-256]! +0x49,0xfc,0x4f,0x38 = ldrb w9, [x2, #255]! +0x6a,0x1c,0x40,0x38 = ldrb w10, [x3, #1]! +0x6a,0x0c,0x50,0x38 = ldrb w10, [x3, #-256]! +0x49,0xfc,0x4f,0x78 = ldrh w9, [x2, #255]! +0x49,0x1c,0x40,0x78 = ldrh w9, [x2, #1]! +0x6a,0x0c,0x50,0x78 = ldrh w10, [x3, #-256]! +0xf3,0xff,0x4f,0xb8 = ldr w19, [sp, #255]! +0xd4,0x1f,0x40,0xb8 = ldr w20, [x30, #1]! +0x95,0x0d,0x50,0xb8 = ldr w21, [x12, #-256]! +0x3f,0xfd,0x4f,0xf8 = ldr xzr, [x9, #255]! +0x62,0x1c,0x40,0xf8 = ldr x2, [x3, #1]! +0x93,0x0d,0x50,0xf8 = ldr x19, [x12, #-256]! +0x3f,0xfd,0x8f,0x38 = ldrsb xzr, [x9, #255]! +0x62,0x1c,0x80,0x38 = ldrsb x2, [x3, #1]! +0x93,0x0d,0x90,0x38 = ldrsb x19, [x12, #-256]! +0x3f,0xfd,0x8f,0x78 = ldrsh xzr, [x9, #255]! +0x62,0x1c,0x80,0x78 = ldrsh x2, [x3, #1]! +0x93,0x0d,0x90,0x78 = ldrsh x19, [x12, #-256]! +0x3f,0xfd,0x8f,0xb8 = ldrsw xzr, [x9, #255]! +0x62,0x1c,0x80,0xb8 = ldrsw x2, [x3, #1]! +0x93,0x0d,0x90,0xb8 = ldrsw x19, [x12, #-256]! +0x3f,0xfd,0xcf,0x38 = ldrsb wzr, [x9, #255]! +0x62,0x1c,0xc0,0x38 = ldrsb w2, [x3, #1]! +0x93,0x0d,0xd0,0x38 = ldrsb w19, [x12, #-256]! +0x3f,0xfd,0xcf,0x78 = ldrsh wzr, [x9, #255]! +0x62,0x1c,0xc0,0x78 = ldrsh w2, [x3, #1]! +0x93,0x0d,0xd0,0x78 = ldrsh w19, [x12, #-256]! +0x00,0xfc,0x0f,0x3c = str b0, [x0, #255]! +0x63,0x1c,0x00,0x3c = str b3, [x3, #1]! +0xe5,0x0f,0x10,0x3c = str b5, [sp, #-256]! +0x4a,0xfd,0x0f,0x7c = str h10, [x10, #255]! +0xed,0x1e,0x00,0x7c = str h13, [x23, #1]! +0xef,0x0f,0x10,0x7c = str h15, [sp, #-256]! +0x94,0xfe,0x0f,0xbc = str s20, [x20, #255]! +0xf7,0x1e,0x00,0xbc = str s23, [x23, #1]! +0x19,0x0c,0x10,0xbc = str s25, [x0, #-256]! +0x94,0xfe,0x0f,0xfc = str d20, [x20, #255]! +0xf7,0x1e,0x00,0xfc = str d23, [x23, #1]! +0x19,0x0c,0x10,0xfc = str d25, [x0, #-256]! +0x00,0xfc,0x4f,0x3c = ldr b0, [x0, #255]! +0x63,0x1c,0x40,0x3c = ldr b3, [x3, #1]! +0xe5,0x0f,0x50,0x3c = ldr b5, [sp, #-256]! +0x4a,0xfd,0x4f,0x7c = ldr h10, [x10, #255]! +0xed,0x1e,0x40,0x7c = ldr h13, [x23, #1]! +0xef,0x0f,0x50,0x7c = ldr h15, [sp, #-256]! +0x94,0xfe,0x4f,0xbc = ldr s20, [x20, #255]! +0xf7,0x1e,0x40,0xbc = ldr s23, [x23, #1]! +0x19,0x0c,0x50,0xbc = ldr s25, [x0, #-256]! +0x94,0xfe,0x4f,0xfc = ldr d20, [x20, #255]! +0xf7,0x1e,0x40,0xfc = ldr d23, [x23, #1]! +0x19,0x0c,0x50,0xfc = ldr d25, [x0, #-256]! +0x34,0xfc,0xcf,0x3c = ldr q20, [x1, #255]! +0x37,0x1d,0xc0,0x3c = ldr q23, [x9, #1]! +0x99,0x0e,0xd0,0x3c = ldr q25, [x20, #-256]! +0x2a,0xfc,0x8f,0x3c = str q10, [x1, #255]! +0xf6,0x1f,0x80,0x3c = str q22, [sp, #1]! +0x95,0x0e,0x90,0x3c = str q21, [x20, #-256]! +0xe9,0x0b,0x00,0x38 = sttrb w9, [sp] +0x9f,0xf9,0x0f,0x78 = sttrh wzr, [x12, #255] +0x10,0x08,0x10,0xb8 = sttr w16, [x0, #-256] +0xdc,0x19,0x00,0xf8 = sttr x28, [x14, #1] +0x81,0xfa,0x4f,0x38 = ldtrb w1, [x20, #255] +0x34,0xf8,0x4f,0x78 = ldtrh w20, [x1, #255] +0xec,0xfb,0x4f,0xb8 = ldtr w12, [sp, #255] +0x9f,0xf9,0x4f,0xf8 = ldtr xzr, [x12, #255] +0xe9,0x08,0x90,0x38 = ldtrsb x9, [x7, #-256] +0x71,0x0a,0x90,0x78 = ldtrsh x17, [x19, #-256] +0xf4,0x09,0x90,0xb8 = ldtrsw x20, [x15, #-256] +0x33,0x08,0xd0,0x38 = ldtrsb w19, [x1, #-256] +0xaf,0x0a,0xd0,0x78 = ldtrsh w15, [x21, #-256] +0xe3,0x17,0x40,0x29 = ldp w3, w5, [sp] +0xff,0xa7,0x1f,0x29 = stp wzr, w9, [sp, #252] +0xe2,0x7f,0x60,0x29 = ldp w2, wzr, [sp, #-256] +0xe9,0xab,0x40,0x29 = ldp w9, w10, [sp, #4] +0xe9,0xab,0x40,0x69 = ldpsw x9, x10, [sp, #4] +0x49,0x28,0x60,0x69 = ldpsw x9, x10, [x2, #-256] +0xf4,0xfb,0x5f,0x69 = ldpsw x20, x30, [sp, #252] +0x55,0xf4,0x5f,0xa9 = ldp x21, x29, [x2, #504] +0x76,0x5c,0x60,0xa9 = ldp x22, x23, [x3, #-512] +0x98,0xe4,0x40,0xa9 = ldp x24, x25, [x4, #8] +0xfd,0xf3,0x5f,0x2d = ldp s29, s28, [sp, #252] +0xfb,0x6b,0x20,0x2d = stp s27, s26, [sp, #-256] +0x61,0x88,0x45,0x2d = ldp s1, s2, [x3, #44] +0x23,0x95,0x1f,0x6d = stp d3, d5, [x9, #504] +0x47,0x2d,0x20,0x6d = stp d7, d11, [x10, #-512] +0xc2,0x8f,0x7f,0x6d = ldp d2, d3, [x30, #-8] +0xe3,0x17,0x00,0xad = stp q3, q5, [sp] +0xf1,0xcf,0x1f,0xad = stp q17, q19, [sp, #1008] +0x37,0x74,0x60,0xad = ldp q23, q29, [x1, #-1024] +0xe3,0x17,0xc0,0x28 = ldp w3, w5, [sp], #0 +0xff,0xa7,0x9f,0x28 = stp wzr, w9, [sp], #252 +0xe2,0x7f,0xe0,0x28 = ldp w2, wzr, [sp], #-256 +0xe9,0xab,0xc0,0x28 = ldp w9, w10, [sp], #4 +0xe9,0xab,0xc0,0x68 = ldpsw x9, x10, [sp], #4 +0x49,0x28,0xe0,0x68 = ldpsw x9, x10, [x2], #-256 +0xf4,0xfb,0xdf,0x68 = ldpsw x20, x30, [sp], #252 +0x55,0xf4,0xdf,0xa8 = ldp x21, x29, [x2], #504 +0x76,0x5c,0xe0,0xa8 = ldp x22, x23, [x3], #-512 +0x98,0xe4,0xc0,0xa8 = ldp x24, x25, [x4], #8 +0xfd,0xf3,0xdf,0x2c = ldp s29, s28, [sp], #252 +0xfb,0x6b,0xa0,0x2c = stp s27, s26, [sp], #-256 +0x61,0x88,0xc5,0x2c = ldp s1, s2, [x3], #44 +0x23,0x95,0x9f,0x6c = stp d3, d5, [x9], #504 +0x47,0x2d,0xa0,0x6c = stp d7, d11, [x10], #-512 +0xc2,0x8f,0xff,0x6c = ldp d2, d3, [x30], #-8 +0xe3,0x17,0x80,0xac = stp q3, q5, [sp], #0 +0xf1,0xcf,0x9f,0xac = stp q17, q19, [sp], #1008 +0x37,0x74,0xe0,0xac = ldp q23, q29, [x1], #-1024 +0xe3,0x17,0xc0,0x29 = ldp w3, w5, [sp, #0]! +0xff,0xa7,0x9f,0x29 = stp wzr, w9, [sp, #252]! +0xe2,0x7f,0xe0,0x29 = ldp w2, wzr, [sp, #-256]! +0xe9,0xab,0xc0,0x29 = ldp w9, w10, [sp, #4]! +0xe9,0xab,0xc0,0x69 = ldpsw x9, x10, [sp, #4]! +0x49,0x28,0xe0,0x69 = ldpsw x9, x10, [x2, #-256]! +0xf4,0xfb,0xdf,0x69 = ldpsw x20, x30, [sp, #252]! +0x55,0xf4,0xdf,0xa9 = ldp x21, x29, [x2, #504]! +0x76,0x5c,0xe0,0xa9 = ldp x22, x23, [x3, #-512]! +0x98,0xe4,0xc0,0xa9 = ldp x24, x25, [x4, #8]! +0xfd,0xf3,0xdf,0x2d = ldp s29, s28, [sp, #252]! +0xfb,0x6b,0xa0,0x2d = stp s27, s26, [sp, #-256]! +0x61,0x88,0xc5,0x2d = ldp s1, s2, [x3, #44]! +0x23,0x95,0x9f,0x6d = stp d3, d5, [x9, #504]! +0x47,0x2d,0xa0,0x6d = stp d7, d11, [x10, #-512]! +0xc2,0x8f,0xff,0x6d = ldp d2, d3, [x30, #-8]! +0xe3,0x17,0x80,0xad = stp q3, q5, [sp, #0]! +0xf1,0xcf,0x9f,0xad = stp q17, q19, [sp, #1008]! +0x37,0x74,0xe0,0xad = ldp q23, q29, [x1, #-1024]! +0xe3,0x17,0x40,0x28 = ldnp w3, w5, [sp] +0xff,0xa7,0x1f,0x28 = stnp wzr, w9, [sp, #252] +0xe2,0x7f,0x60,0x28 = ldnp w2, wzr, [sp, #-256] +0xe9,0xab,0x40,0x28 = ldnp w9, w10, [sp, #4] +0x55,0xf4,0x5f,0xa8 = ldnp x21, x29, [x2, #504] +0x76,0x5c,0x60,0xa8 = ldnp x22, x23, [x3, #-512] +0x98,0xe4,0x40,0xa8 = ldnp x24, x25, [x4, #8] +0xfd,0xf3,0x5f,0x2c = ldnp s29, s28, [sp, #252] +0xfb,0x6b,0x20,0x2c = stnp s27, s26, [sp, #-256] +0x61,0x88,0x45,0x2c = ldnp s1, s2, [x3, #44] +0x23,0x95,0x1f,0x6c = stnp d3, d5, [x9, #504] +0x47,0x2d,0x20,0x6c = stnp d7, d11, [x10, #-512] +0xc2,0x8f,0x7f,0x6c = ldnp d2, d3, [x30, #-8] +0xe3,0x17,0x00,0xac = stnp q3, q5, [sp] +0xf1,0xcf,0x1f,0xac = stnp q17, q19, [sp, #1008] +0x37,0x74,0x60,0xac = ldnp q23, q29, [x1, #-1024] +0x23,0x3d,0x10,0x32 = orr w3, w9, #0xffff0000 +0x5f,0x29,0x03,0x32 = orr wsp, w10, #0xe00000ff +0x49,0x25,0x00,0x32 = orr w9, w10, #0x3ff +0xee,0x81,0x01,0x12 = and w14, w15, #0x80008000 +0xac,0xad,0x0a,0x12 = and w12, w13, #0xffc3ffc3 +0xeb,0x87,0x00,0x12 = and w11, wzr, #0x30003 +0xc3,0xc8,0x03,0x52 = eor w3, w6, #0xe0e0e0e0 +0xff,0xc7,0x00,0x52 = eor wsp, wzr, #0x3030303 +0x30,0xc6,0x01,0x52 = eor w16, w17, #0x81818181 +// 0x5f,0xe6,0x02,0x72 = ands wzr, w18, #0xcccccccc +0x93,0xe6,0x00,0x72 = ands w19, w20, #0x33333333 +0xd5,0xe6,0x01,0x72 = ands w21, w22, #0x99999999 +// 0x7f,0xf0,0x01,0x72 = ands wzr, w3, #0xaaaaaaaa +// 0xff,0xf3,0x00,0x72 = ands wzr, wzr, #0x55555555 +0xa3,0x84,0x66,0xd2 = eor x3, x5, #0xffffffffc000000 +0x49,0xb9,0x40,0x92 = and x9, x10, #0x7fffffffffff +0x8b,0x31,0x41,0xb2 = orr x11, x12, #0x8000000000000fff +0x23,0x3d,0x10,0xb2 = orr x3, x9, #0xffff0000ffff0000 +0x5f,0x29,0x03,0xb2 = orr sp, x10, #0xe00000ffe00000ff +0x49,0x25,0x00,0xb2 = orr x9, x10, #0x3ff000003ff +0xee,0x81,0x01,0x92 = and x14, x15, #0x8000800080008000 +0xac,0xad,0x0a,0x92 = and x12, x13, #0xffc3ffc3ffc3ffc3 +0xeb,0x87,0x00,0x92 = and x11, xzr, #0x3000300030003 +0xc3,0xc8,0x03,0xd2 = eor x3, x6, #0xe0e0e0e0e0e0e0e0 +0xff,0xc7,0x00,0xd2 = eor sp, xzr, #0x303030303030303 +0x30,0xc6,0x01,0xd2 = eor x16, x17, #0x8181818181818181 +// 0x5f,0xe6,0x02,0xf2 = ands xzr, x18, #0xcccccccccccccccc +0x93,0xe6,0x00,0xf2 = ands x19, x20, #0x3333333333333333 +0xd5,0xe6,0x01,0xf2 = ands x21, x22, #0x9999999999999999 +// 0x7f,0xf0,0x01,0xf2 = ands xzr, x3, #0xaaaaaaaaaaaaaaaa +// 0xff,0xf3,0x00,0xf2 = ands xzr, xzr, #0x5555555555555555 +0xe3,0x8f,0x00,0x32 = orr w3, wzr, #0xf000f +0xea,0xf3,0x01,0xb2 = orr x10, xzr, #0xaaaaaaaaaaaaaaaa +0xec,0x02,0x15,0x0a = and w12, w23, w21 +0xf0,0x05,0x01,0x0a = and w16, w15, w1, lsl #1 +0x89,0x7c,0x0a,0x0a = and w9, w4, w10, lsl #31 +0xc3,0x03,0x0b,0x0a = and w3, w30, w11 +0xa3,0xfc,0x07,0x8a = and x3, x5, x7, lsl #63 +0xc5,0x11,0x93,0x8a = and x5, x14, x19, asr #4 +0x23,0x7e,0xd3,0x0a = and w3, w17, w19, ror #31 +0x40,0x44,0x5f,0x0a = and w0, w2, wzr, lsr #17 +0xc3,0x03,0x8b,0x0a = and w3, w30, w11, asr #0 +0x9f,0x00,0x1a,0x8a = and xzr, x4, x26 +0xe3,0x03,0xd4,0x0a = and w3, wzr, w20, ror #0 +0x87,0xfe,0x9f,0x8a = and x7, x20, xzr, asr #63 +0x8d,0xbe,0x2e,0x8a = bic x13, x20, x14, lsl #47 +0xe2,0x00,0x29,0x0a = bic w2, w7, w9 +0xe2,0x7c,0x80,0x2a = orr w2, w7, w0, asr #31 +0x28,0x31,0x0a,0xaa = orr x8, x9, x10, lsl #12 +0xa3,0x00,0xa7,0xaa = orn x3, x5, x7, asr #0 +0xa2,0x00,0x3d,0x2a = orn w2, w5, w29 +0xe7,0x07,0x09,0x6a = ands w7, wzr, w9, lsl #1 +0xa3,0xfc,0xd4,0xea = ands x3, x5, x20, ror #63 +0xa3,0x00,0x27,0x6a = bics w3, w5, w7 +0xe3,0x07,0x23,0xea = bics x3, xzr, x3, lsl #1 +0x7f,0x7c,0x07,0x6a = tst w3, w7, lsl #31 +0x5f,0x00,0x94,0xea = tst x2, x20, asr #0 +0xe3,0x03,0x06,0xaa = mov x3, x6 +0xe3,0x03,0x1f,0xaa = mov x3, xzr +0xff,0x03,0x02,0x2a = mov wzr, w2 +0xe3,0x03,0x05,0x2a = mov w3, w5 +0xe1,0xff,0x9f,0x52 = movz w1, #65535 +0x02,0x00,0xa0,0x52 = movz w2, #0, lsl #16 +0x42,0x9a,0x80,0x12 = movn w2, #1234 +0x42,0x9a,0xc0,0xd2 = movz x2, #1234, lsl #32 +0x3f,0x1c,0xe2,0xf2 = movk xzr, #4321, lsl #48 +0x1e,0x00,0x00,0xb0 = adrp x30, #4096 +0x14,0x00,0x00,0x10 = adr x20, #0 +0xe9,0xff,0xff,0x70 = adr x9, #-1 +0xe5,0xff,0x7f,0x70 = adr x5, #1048575 +0xe9,0xff,0x7f,0x70 = adr x9, #1048575 +0x02,0x00,0x80,0x10 = adr x2, #-1048576 +0xe9,0xff,0x7f,0xf0 = adrp x9, #4294963200 +0x14,0x00,0x80,0x90 = adrp x20, #-4294967296 +0x1f,0x20,0x03,0xd5 = nop +0xff,0x2f,0x03,0xd5 = hint #127 +0x1f,0x20,0x03,0xd5 = nop +0x3f,0x20,0x03,0xd5 = yield +0x5f,0x20,0x03,0xd5 = wfe +0x7f,0x20,0x03,0xd5 = wfi +0x9f,0x20,0x03,0xd5 = sev +0xbf,0x20,0x03,0xd5 = sevl +0x5f,0x3f,0x03,0xd5 = clrex +0x5f,0x30,0x03,0xd5 = clrex #0 +0x5f,0x37,0x03,0xd5 = clrex #7 +0x5f,0x3f,0x03,0xd5 = clrex +0x9f,0x30,0x03,0xd5 = dsb #0 +0x9f,0x3c,0x03,0xd5 = dsb #12 +0x9f,0x3f,0x03,0xd5 = dsb sy +0x9f,0x31,0x03,0xd5 = dsb oshld +0x9f,0x32,0x03,0xd5 = dsb oshst +0x9f,0x33,0x03,0xd5 = dsb osh +0x9f,0x35,0x03,0xd5 = dsb nshld +0x9f,0x36,0x03,0xd5 = dsb nshst +0x9f,0x37,0x03,0xd5 = dsb nsh +0x9f,0x39,0x03,0xd5 = dsb ishld +0x9f,0x3a,0x03,0xd5 = dsb ishst +0x9f,0x3b,0x03,0xd5 = dsb ish +0x9f,0x3d,0x03,0xd5 = dsb ld +0x9f,0x3e,0x03,0xd5 = dsb st +0x9f,0x3f,0x03,0xd5 = dsb sy +0xbf,0x30,0x03,0xd5 = dmb #0 +0xbf,0x3c,0x03,0xd5 = dmb #12 +0xbf,0x3f,0x03,0xd5 = dmb sy +0xbf,0x31,0x03,0xd5 = dmb oshld +0xbf,0x32,0x03,0xd5 = dmb oshst +0xbf,0x33,0x03,0xd5 = dmb osh +0xbf,0x35,0x03,0xd5 = dmb nshld +0xbf,0x36,0x03,0xd5 = dmb nshst +0xbf,0x37,0x03,0xd5 = dmb nsh +0xbf,0x39,0x03,0xd5 = dmb ishld +0xbf,0x3a,0x03,0xd5 = dmb ishst +0xbf,0x3b,0x03,0xd5 = dmb ish +0xbf,0x3d,0x03,0xd5 = dmb ld +0xbf,0x3e,0x03,0xd5 = dmb st +0xbf,0x3f,0x03,0xd5 = dmb sy +0xdf,0x3f,0x03,0xd5 = isb +0xdf,0x3f,0x03,0xd5 = isb +0xdf,0x3c,0x03,0xd5 = isb #12 +0xbf,0x40,0x00,0xd5 = msr spsel, #0 +0xdf,0x4f,0x03,0xd5 = msr daifset, #15 +0xff,0x4c,0x03,0xd5 = msr daifclr, #12 +0x9f,0x40,0x00,0xd5 = msr pan, #0 +0x7f,0x40,0x00,0xd5 = msr uao, #0 +0xe5,0x59,0x0f,0xd5 = sys #7, c5, c9, #7, x5 +// 0x5f,0xff,0x08,0xd5 = sys #0, c15, c15, #2, xzr +0xe9,0x59,0x2f,0xd5 = sysl x9, #7, c5, c9, #7 +0x41,0xff,0x28,0xd5 = sysl x1, #0, c15, c15, #2 +0x1f,0x71,0x08,0xd5 = ic ialluis +0x1f,0x75,0x08,0xd5 = ic iallu +0x29,0x75,0x0b,0xd5 = ic ivau, x9 +0x2c,0x74,0x0b,0xd5 = dc zva, x12 +0x3f,0x76,0x08,0xd5 = dc ivac, xzr +0x42,0x76,0x08,0xd5 = dc isw, x2 +0x29,0x7a,0x0b,0xd5 = dc cvac, x9 +0x4a,0x7a,0x08,0xd5 = dc csw, x10 +0x20,0x7b,0x0b,0xd5 = dc cvau, x0 +0x23,0x7e,0x0b,0xd5 = dc civac, x3 +0x5e,0x7e,0x08,0xd5 = dc cisw, x30 +0x13,0x78,0x08,0xd5 = at s1e1r, x19 +0x13,0x78,0x0c,0xd5 = at s1e2r, x19 +0x13,0x78,0x0e,0xd5 = at s1e3r, x19 +0x33,0x78,0x08,0xd5 = at s1e1w, x19 +0x33,0x78,0x0c,0xd5 = at s1e2w, x19 +0x33,0x78,0x0e,0xd5 = at s1e3w, x19 +0x53,0x78,0x08,0xd5 = at s1e0r, x19 +0x73,0x78,0x08,0xd5 = at s1e0w, x19 +0x94,0x78,0x0c,0xd5 = at s12e1r, x20 +0xb4,0x78,0x0c,0xd5 = at s12e1w, x20 +0xd4,0x78,0x0c,0xd5 = at s12e0r, x20 +0xf4,0x78,0x0c,0xd5 = at s12e0w, x20 +0x24,0x80,0x0c,0xd5 = tlbi ipas2e1is, x4 +0xa9,0x80,0x0c,0xd5 = tlbi ipas2le1is, x9 +0x1f,0x83,0x08,0xd5 = tlbi vmalle1is +0x1f,0x83,0x0c,0xd5 = tlbi alle2is +0x1f,0x83,0x0e,0xd5 = tlbi alle3is +0x21,0x83,0x08,0xd5 = tlbi vae1is, x1 +0x22,0x83,0x0c,0xd5 = tlbi vae2is, x2 +0x23,0x83,0x0e,0xd5 = tlbi vae3is, x3 +0x45,0x83,0x08,0xd5 = tlbi aside1is, x5 +0x69,0x83,0x08,0xd5 = tlbi vaae1is, x9 +0x9f,0x83,0x0c,0xd5 = tlbi alle1is +0xaa,0x83,0x08,0xd5 = tlbi vale1is, x10 +0xab,0x83,0x0c,0xd5 = tlbi vale2is, x11 +0xad,0x83,0x0e,0xd5 = tlbi vale3is, x13 +0xdf,0x83,0x0c,0xd5 = tlbi vmalls12e1is +0xee,0x83,0x08,0xd5 = tlbi vaale1is, x14 +0x2f,0x84,0x0c,0xd5 = tlbi ipas2e1, x15 +0xb0,0x84,0x0c,0xd5 = tlbi ipas2le1, x16 +0x1f,0x87,0x08,0xd5 = tlbi vmalle1 +0x1f,0x87,0x0c,0xd5 = tlbi alle2 +0x1f,0x87,0x0e,0xd5 = tlbi alle3 +0x31,0x87,0x08,0xd5 = tlbi vae1, x17 +0x32,0x87,0x0c,0xd5 = tlbi vae2, x18 +0x33,0x87,0x0e,0xd5 = tlbi vae3, x19 +0x54,0x87,0x08,0xd5 = tlbi aside1, x20 +0x75,0x87,0x08,0xd5 = tlbi vaae1, x21 +0x9f,0x87,0x0c,0xd5 = tlbi alle1 +0xb6,0x87,0x08,0xd5 = tlbi vale1, x22 +0xb7,0x87,0x0c,0xd5 = tlbi vale2, x23 +0xb8,0x87,0x0e,0xd5 = tlbi vale3, x24 +0xdf,0x87,0x0c,0xd5 = tlbi vmalls12e1 +0xf9,0x87,0x08,0xd5 = tlbi vaale1, x25 +0x0c,0x00,0x12,0xd5 = msr teecr32_el1, x12 +0x4c,0x00,0x10,0xd5 = msr osdtrrx_el1, x12 +0x0c,0x02,0x10,0xd5 = msr mdccint_el1, x12 +0x4c,0x02,0x10,0xd5 = msr mdscr_el1, x12 +0x4c,0x03,0x10,0xd5 = msr osdtrtx_el1, x12 +0x0c,0x04,0x13,0xd5 = msr dbgdtr_el0, x12 +0x0c,0x05,0x13,0xd5 = msr dbgdtrtx_el0, x12 +0x4c,0x06,0x10,0xd5 = msr oseccr_el1, x12 +0x0c,0x07,0x14,0xd5 = msr dbgvcr32_el2, x12 +0x8c,0x00,0x10,0xd5 = msr dbgbvr0_el1, x12 +0x8c,0x01,0x10,0xd5 = msr dbgbvr1_el1, x12 +0x8c,0x02,0x10,0xd5 = msr dbgbvr2_el1, x12 +0x8c,0x03,0x10,0xd5 = msr dbgbvr3_el1, x12 +0x8c,0x04,0x10,0xd5 = msr dbgbvr4_el1, x12 +0x8c,0x05,0x10,0xd5 = msr dbgbvr5_el1, x12 +0x8c,0x06,0x10,0xd5 = msr dbgbvr6_el1, x12 +0x8c,0x07,0x10,0xd5 = msr dbgbvr7_el1, x12 +0x8c,0x08,0x10,0xd5 = msr dbgbvr8_el1, x12 +0x8c,0x09,0x10,0xd5 = msr dbgbvr9_el1, x12 +0x8c,0x0a,0x10,0xd5 = msr dbgbvr10_el1, x12 +0x8c,0x0b,0x10,0xd5 = msr dbgbvr11_el1, x12 +0x8c,0x0c,0x10,0xd5 = msr dbgbvr12_el1, x12 +0x8c,0x0d,0x10,0xd5 = msr dbgbvr13_el1, x12 +0x8c,0x0e,0x10,0xd5 = msr dbgbvr14_el1, x12 +0x8c,0x0f,0x10,0xd5 = msr dbgbvr15_el1, x12 +0xac,0x00,0x10,0xd5 = msr dbgbcr0_el1, x12 +0xac,0x01,0x10,0xd5 = msr dbgbcr1_el1, x12 +0xac,0x02,0x10,0xd5 = msr dbgbcr2_el1, x12 +0xac,0x03,0x10,0xd5 = msr dbgbcr3_el1, x12 +0xac,0x04,0x10,0xd5 = msr dbgbcr4_el1, x12 +0xac,0x05,0x10,0xd5 = msr dbgbcr5_el1, x12 +0xac,0x06,0x10,0xd5 = msr dbgbcr6_el1, x12 +0xac,0x07,0x10,0xd5 = msr dbgbcr7_el1, x12 +0xac,0x08,0x10,0xd5 = msr dbgbcr8_el1, x12 +0xac,0x09,0x10,0xd5 = msr dbgbcr9_el1, x12 +0xac,0x0a,0x10,0xd5 = msr dbgbcr10_el1, x12 +0xac,0x0b,0x10,0xd5 = msr dbgbcr11_el1, x12 +0xac,0x0c,0x10,0xd5 = msr dbgbcr12_el1, x12 +0xac,0x0d,0x10,0xd5 = msr dbgbcr13_el1, x12 +0xac,0x0e,0x10,0xd5 = msr dbgbcr14_el1, x12 +0xac,0x0f,0x10,0xd5 = msr dbgbcr15_el1, x12 +0xcc,0x00,0x10,0xd5 = msr dbgwvr0_el1, x12 +0xcc,0x01,0x10,0xd5 = msr dbgwvr1_el1, x12 +0xcc,0x02,0x10,0xd5 = msr dbgwvr2_el1, x12 +0xcc,0x03,0x10,0xd5 = msr dbgwvr3_el1, x12 +0xcc,0x04,0x10,0xd5 = msr dbgwvr4_el1, x12 +0xcc,0x05,0x10,0xd5 = msr dbgwvr5_el1, x12 +0xcc,0x06,0x10,0xd5 = msr dbgwvr6_el1, x12 +0xcc,0x07,0x10,0xd5 = msr dbgwvr7_el1, x12 +0xcc,0x08,0x10,0xd5 = msr dbgwvr8_el1, x12 +0xcc,0x09,0x10,0xd5 = msr dbgwvr9_el1, x12 +0xcc,0x0a,0x10,0xd5 = msr dbgwvr10_el1, x12 +0xcc,0x0b,0x10,0xd5 = msr dbgwvr11_el1, x12 +0xcc,0x0c,0x10,0xd5 = msr dbgwvr12_el1, x12 +0xcc,0x0d,0x10,0xd5 = msr dbgwvr13_el1, x12 +0xcc,0x0e,0x10,0xd5 = msr dbgwvr14_el1, x12 +0xcc,0x0f,0x10,0xd5 = msr dbgwvr15_el1, x12 +0xec,0x00,0x10,0xd5 = msr dbgwcr0_el1, x12 +0xec,0x01,0x10,0xd5 = msr dbgwcr1_el1, x12 +0xec,0x02,0x10,0xd5 = msr dbgwcr2_el1, x12 +0xec,0x03,0x10,0xd5 = msr dbgwcr3_el1, x12 +0xec,0x04,0x10,0xd5 = msr dbgwcr4_el1, x12 +0xec,0x05,0x10,0xd5 = msr dbgwcr5_el1, x12 +0xec,0x06,0x10,0xd5 = msr dbgwcr6_el1, x12 +0xec,0x07,0x10,0xd5 = msr dbgwcr7_el1, x12 +0xec,0x08,0x10,0xd5 = msr dbgwcr8_el1, x12 +0xec,0x09,0x10,0xd5 = msr dbgwcr9_el1, x12 +0xec,0x0a,0x10,0xd5 = msr dbgwcr10_el1, x12 +0xec,0x0b,0x10,0xd5 = msr dbgwcr11_el1, x12 +0xec,0x0c,0x10,0xd5 = msr dbgwcr12_el1, x12 +0xec,0x0d,0x10,0xd5 = msr dbgwcr13_el1, x12 +0xec,0x0e,0x10,0xd5 = msr dbgwcr14_el1, x12 +0xec,0x0f,0x10,0xd5 = msr dbgwcr15_el1, x12 +0x0c,0x10,0x12,0xd5 = msr teehbr32_el1, x12 +0x8c,0x10,0x10,0xd5 = msr oslar_el1, x12 +0x8c,0x13,0x10,0xd5 = msr osdlr_el1, x12 +0x8c,0x14,0x10,0xd5 = msr dbgprcr_el1, x12 +0xcc,0x78,0x10,0xd5 = msr dbgclaimset_el1, x12 +0xcc,0x79,0x10,0xd5 = msr dbgclaimclr_el1, x12 +0x0c,0x00,0x1a,0xd5 = msr csselr_el1, x12 +0x0c,0x00,0x1c,0xd5 = msr vpidr_el2, x12 +0xac,0x00,0x1c,0xd5 = msr vmpidr_el2, x12 +0x0c,0x10,0x18,0xd5 = msr sctlr_el1, x12 +0x0c,0x10,0x1c,0xd5 = msr sctlr_el2, x12 +0x0c,0x10,0x1e,0xd5 = msr sctlr_el3, x12 +0x2c,0x10,0x18,0xd5 = msr actlr_el1, x12 +0x2c,0x10,0x1c,0xd5 = msr actlr_el2, x12 +0x2c,0x10,0x1e,0xd5 = msr actlr_el3, x12 +0x4c,0x10,0x18,0xd5 = msr cpacr_el1, x12 +0x0c,0x11,0x1c,0xd5 = msr hcr_el2, x12 +0x0c,0x11,0x1e,0xd5 = msr scr_el3, x12 +0x2c,0x11,0x1c,0xd5 = msr mdcr_el2, x12 +0x2c,0x11,0x1e,0xd5 = msr sder32_el3, x12 +0x4c,0x11,0x1c,0xd5 = msr cptr_el2, x12 +0x4c,0x11,0x1e,0xd5 = msr cptr_el3, x12 +0x6c,0x11,0x1c,0xd5 = msr hstr_el2, x12 +0xec,0x11,0x1c,0xd5 = msr hacr_el2, x12 +0x2c,0x13,0x1e,0xd5 = msr mdcr_el3, x12 +0x0c,0x20,0x18,0xd5 = msr ttbr0_el1, x12 +0x0c,0x20,0x1c,0xd5 = msr ttbr0_el2, x12 +0x0c,0x20,0x1e,0xd5 = msr ttbr0_el3, x12 +0x2c,0x20,0x18,0xd5 = msr ttbr1_el1, x12 +0x4c,0x20,0x18,0xd5 = msr tcr_el1, x12 +0x4c,0x20,0x1c,0xd5 = msr tcr_el2, x12 +0x4c,0x20,0x1e,0xd5 = msr tcr_el3, x12 +0x0c,0x21,0x1c,0xd5 = msr vttbr_el2, x12 +0x4c,0x21,0x1c,0xd5 = msr vtcr_el2, x12 +0x0c,0x30,0x1c,0xd5 = msr dacr32_el2, x12 +0x0c,0x40,0x18,0xd5 = msr spsr_el1, x12 +0x0c,0x40,0x1c,0xd5 = msr spsr_el2, x12 +0x0c,0x40,0x1e,0xd5 = msr spsr_el3, x12 +0x2c,0x40,0x18,0xd5 = msr elr_el1, x12 +0x2c,0x40,0x1c,0xd5 = msr elr_el2, x12 +0x2c,0x40,0x1e,0xd5 = msr elr_el3, x12 +0x0c,0x41,0x18,0xd5 = msr sp_el0, x12 +0x0c,0x41,0x1c,0xd5 = msr sp_el1, x12 +0x0c,0x41,0x1e,0xd5 = msr sp_el2, x12 +0x0c,0x42,0x18,0xd5 = msr spsel, x12 +0x0c,0x42,0x1b,0xd5 = msr nzcv, x12 +0x2c,0x42,0x1b,0xd5 = msr daif, x12 +0x4c,0x42,0x18,0xd5 = msr currentel, x12 +0x0c,0x43,0x1c,0xd5 = msr spsr_irq, x12 +0x2c,0x43,0x1c,0xd5 = msr spsr_abt, x12 +0x4c,0x43,0x1c,0xd5 = msr spsr_und, x12 +0x6c,0x43,0x1c,0xd5 = msr spsr_fiq, x12 +0x0c,0x44,0x1b,0xd5 = msr fpcr, x12 +0x2c,0x44,0x1b,0xd5 = msr fpsr, x12 +0x0c,0x45,0x1b,0xd5 = msr dspsr_el0, x12 +0x2c,0x45,0x1b,0xd5 = msr dlr_el0, x12 +0x2c,0x50,0x1c,0xd5 = msr ifsr32_el2, x12 +0x0c,0x51,0x18,0xd5 = msr afsr0_el1, x12 + +0x0c,0x51,0x1c,0xd5 = msr afsr0_el2, x12 +0x0c,0x51,0x1e,0xd5 = msr afsr0_el3, x12 +0x2c,0x51,0x18,0xd5 = msr afsr1_el1, x12 +0x2c,0x51,0x1d,0xd5 = msr afsr1_el12, x12 +0x2c,0x51,0x1c,0xd5 = msr afsr1_el2, x12 +0x2c,0x51,0x1e,0xd5 = msr afsr1_el3, x12 +0x0c,0x52,0x18,0xd5 = msr esr_el1, x12 +0x0c,0x52,0x1c,0xd5 = msr esr_el2, x12 +0x0c,0x52,0x1e,0xd5 = msr esr_el3, x12 +0x0c,0x53,0x1c,0xd5 = msr fpexc32_el2, x12 +0x0c,0x60,0x18,0xd5 = msr far_el1, x12 +0x0c,0x60,0x1c,0xd5 = msr far_el2, x12 +0x0c,0x60,0x1e,0xd5 = msr far_el3, x12 +0x8c,0x60,0x1c,0xd5 = msr hpfar_el2, x12 +0x0c,0x74,0x18,0xd5 = msr par_el1, x12 +0x0c,0x9c,0x1b,0xd5 = msr pmcr_el0, x12 +0x2c,0x9c,0x1b,0xd5 = msr pmcntenset_el0, x12 +0x4c,0x9c,0x1b,0xd5 = msr pmcntenclr_el0, x12 +0x6c,0x9c,0x1b,0xd5 = msr pmovsclr_el0, x12 +0xac,0x9c,0x1b,0xd5 = msr pmselr_el0, x12 +0x0c,0x9d,0x1b,0xd5 = msr pmccntr_el0, x12 +0x2c,0x9d,0x1b,0xd5 = msr pmxevtyper_el0, x12 +0x4c,0x9d,0x1b,0xd5 = msr pmxevcntr_el0, x12 +0x0c,0x9e,0x1b,0xd5 = msr pmuserenr_el0, x12 +0x2c,0x9e,0x18,0xd5 = msr pmintenset_el1, x12 +0x4c,0x9e,0x18,0xd5 = msr pmintenclr_el1, x12 +0x6c,0x9e,0x1b,0xd5 = msr pmovsset_el0, x12 +0x0c,0xa2,0x18,0xd5 = msr mair_el1, x12 +0x0c,0xa2,0x1c,0xd5 = msr mair_el2, x12 +0x0c,0xa2,0x1e,0xd5 = msr mair_el3, x12 +0x0c,0xa3,0x18,0xd5 = msr amair_el1, x12 +0x0c,0xa3,0x1c,0xd5 = msr amair_el2, x12 +0x0c,0xa3,0x1e,0xd5 = msr amair_el3, x12 +0x0c,0xc0,0x18,0xd5 = msr vbar_el1, x12 +0x0c,0xc0,0x1c,0xd5 = msr vbar_el2, x12 +0x0c,0xc0,0x1e,0xd5 = msr vbar_el3, x12 +0x4c,0xc0,0x18,0xd5 = msr rmr_el1, x12 +0x4c,0xc0,0x1c,0xd5 = msr rmr_el2, x12 +0x4c,0xc0,0x1e,0xd5 = msr rmr_el3, x12 +0x2c,0xd0,0x18,0xd5 = msr contextidr_el1, x12 +0x4c,0xd0,0x1b,0xd5 = msr tpidr_el0, x12 +0x4c,0xd0,0x1c,0xd5 = msr tpidr_el2, x12 +0x4c,0xd0,0x1e,0xd5 = msr tpidr_el3, x12 +0x6c,0xd0,0x1b,0xd5 = msr tpidrro_el0, x12 +0x8c,0xd0,0x18,0xd5 = msr tpidr_el1, x12 +0x0c,0xe0,0x1b,0xd5 = msr cntfrq_el0, x12 +0x6c,0xe0,0x1c,0xd5 = msr cntvoff_el2, x12 +0x0c,0xe1,0x18,0xd5 = msr cntkctl_el1, x12 +0x0c,0xe1,0x1c,0xd5 = msr cnthctl_el2, x12 +0x0c,0xe2,0x1b,0xd5 = msr cntp_tval_el0, x12 +0x0c,0xe2,0x1c,0xd5 = msr cnthp_tval_el2, x12 +0x0c,0xe2,0x1f,0xd5 = msr cntps_tval_el1, x12 +0x2c,0xe2,0x1b,0xd5 = msr cntp_ctl_el0, x12 +0x2c,0xe2,0x1c,0xd5 = msr cnthp_ctl_el2, x12 +0x2c,0xe2,0x1f,0xd5 = msr cntps_ctl_el1, x12 +0x4c,0xe2,0x1b,0xd5 = msr cntp_cval_el0, x12 +0x4c,0xe2,0x1c,0xd5 = msr cnthp_cval_el2, x12 +0x4c,0xe2,0x1f,0xd5 = msr cntps_cval_el1, x12 +0x0c,0xe3,0x1b,0xd5 = msr cntv_tval_el0, x12 +0x0c,0xe3,0x1d,0xd5 = msr cntv_tval_el02, x12 +0x2c,0xe3,0x1b,0xd5 = msr cntv_ctl_el0, x12 +0x4c,0xe3,0x1b,0xd5 = msr cntv_cval_el0, x12 +0x0c,0xe8,0x1b,0xd5 = msr pmevcntr0_el0, x12 +0x2c,0xe8,0x1b,0xd5 = msr pmevcntr1_el0, x12 +0x4c,0xe8,0x1b,0xd5 = msr pmevcntr2_el0, x12 +0x6c,0xe8,0x1b,0xd5 = msr pmevcntr3_el0, x12 +0x8c,0xe8,0x1b,0xd5 = msr pmevcntr4_el0, x12 +0xac,0xe8,0x1b,0xd5 = msr pmevcntr5_el0, x12 +0xcc,0xe8,0x1b,0xd5 = msr pmevcntr6_el0, x12 +0xec,0xe8,0x1b,0xd5 = msr pmevcntr7_el0, x12 +0x0c,0xe9,0x1b,0xd5 = msr pmevcntr8_el0, x12 +0x2c,0xe9,0x1b,0xd5 = msr pmevcntr9_el0, x12 +0x4c,0xe9,0x1b,0xd5 = msr pmevcntr10_el0, x12 +0x6c,0xe9,0x1b,0xd5 = msr pmevcntr11_el0, x12 +0x8c,0xe9,0x1b,0xd5 = msr pmevcntr12_el0, x12 +0xac,0xe9,0x1b,0xd5 = msr pmevcntr13_el0, x12 +0xcc,0xe9,0x1b,0xd5 = msr pmevcntr14_el0, x12 +0xec,0xe9,0x1b,0xd5 = msr pmevcntr15_el0, x12 +0x0c,0xea,0x1b,0xd5 = msr pmevcntr16_el0, x12 +0x2c,0xea,0x1b,0xd5 = msr pmevcntr17_el0, x12 +0x4c,0xea,0x1b,0xd5 = msr pmevcntr18_el0, x12 +0x6c,0xea,0x1b,0xd5 = msr pmevcntr19_el0, x12 +0x8c,0xea,0x1b,0xd5 = msr pmevcntr20_el0, x12 +0xac,0xea,0x1b,0xd5 = msr pmevcntr21_el0, x12 +0xcc,0xea,0x1b,0xd5 = msr pmevcntr22_el0, x12 +0xec,0xea,0x1b,0xd5 = msr pmevcntr23_el0, x12 +0x0c,0xeb,0x1b,0xd5 = msr pmevcntr24_el0, x12 +0x2c,0xeb,0x1b,0xd5 = msr pmevcntr25_el0, x12 +0x4c,0xeb,0x1b,0xd5 = msr pmevcntr26_el0, x12 +0x6c,0xeb,0x1b,0xd5 = msr pmevcntr27_el0, x12 +0x8c,0xeb,0x1b,0xd5 = msr pmevcntr28_el0, x12 +0xac,0xeb,0x1b,0xd5 = msr pmevcntr29_el0, x12 +0xcc,0xeb,0x1b,0xd5 = msr pmevcntr30_el0, x12 +0xec,0xef,0x1b,0xd5 = msr pmccfiltr_el0, x12 +0x0c,0xec,0x1b,0xd5 = msr pmevtyper0_el0, x12 +0x2c,0xec,0x1b,0xd5 = msr pmevtyper1_el0, x12 +0x4c,0xec,0x1b,0xd5 = msr pmevtyper2_el0, x12 +0x6c,0xec,0x1b,0xd5 = msr pmevtyper3_el0, x12 +0x8c,0xec,0x1b,0xd5 = msr pmevtyper4_el0, x12 +0xac,0xec,0x1b,0xd5 = msr pmevtyper5_el0, x12 +0xcc,0xec,0x1b,0xd5 = msr pmevtyper6_el0, x12 +0xec,0xec,0x1b,0xd5 = msr pmevtyper7_el0, x12 +0x0c,0xed,0x1b,0xd5 = msr pmevtyper8_el0, x12 +0x2c,0xed,0x1b,0xd5 = msr pmevtyper9_el0, x12 +0x4c,0xed,0x1b,0xd5 = msr pmevtyper10_el0, x12 +0x6c,0xed,0x1b,0xd5 = msr pmevtyper11_el0, x12 +0x8c,0xed,0x1b,0xd5 = msr pmevtyper12_el0, x12 +0xac,0xed,0x1b,0xd5 = msr pmevtyper13_el0, x12 +0xcc,0xed,0x1b,0xd5 = msr pmevtyper14_el0, x12 +0xec,0xed,0x1b,0xd5 = msr pmevtyper15_el0, x12 +0x0c,0xee,0x1b,0xd5 = msr pmevtyper16_el0, x12 +0x2c,0xee,0x1b,0xd5 = msr pmevtyper17_el0, x12 +0x4c,0xee,0x1b,0xd5 = msr pmevtyper18_el0, x12 +0x6c,0xee,0x1b,0xd5 = msr pmevtyper19_el0, x12 +0x8c,0xee,0x1b,0xd5 = msr pmevtyper20_el0, x12 +0xac,0xee,0x1b,0xd5 = msr pmevtyper21_el0, x12 +0xcc,0xee,0x1b,0xd5 = msr pmevtyper22_el0, x12 +0xec,0xee,0x1b,0xd5 = msr pmevtyper23_el0, x12 +0x0c,0xef,0x1b,0xd5 = msr pmevtyper24_el0, x12 +0x2c,0xef,0x1b,0xd5 = msr pmevtyper25_el0, x12 +0x4c,0xef,0x1b,0xd5 = msr pmevtyper26_el0, x12 +0x6c,0xef,0x1b,0xd5 = msr pmevtyper27_el0, x12 +0x8c,0xef,0x1b,0xd5 = msr pmevtyper28_el0, x12 +0xac,0xef,0x1b,0xd5 = msr pmevtyper29_el0, x12 +0xcc,0xef,0x1b,0xd5 = msr pmevtyper30_el0, x12 +0x69,0x42,0x38,0xd5 = mrs x9, pan +0x89,0x42,0x38,0xd5 = mrs x9, uao +0x09,0x00,0x32,0xd5 = mrs x9, teecr32_el1 +0x49,0x00,0x30,0xd5 = mrs x9, osdtrrx_el1 +0x09,0x01,0x33,0xd5 = mrs x9, mdccsr_el0 +0x09,0x02,0x30,0xd5 = mrs x9, mdccint_el1 +0x49,0x02,0x30,0xd5 = mrs x9, mdscr_el1 +0x49,0x03,0x30,0xd5 = mrs x9, osdtrtx_el1 +0x09,0x04,0x33,0xd5 = mrs x9, dbgdtr_el0 +0x09,0x05,0x33,0xd5 = mrs x9, dbgdtrrx_el0 +0x49,0x06,0x30,0xd5 = mrs x9, oseccr_el1 +0x09,0x07,0x34,0xd5 = mrs x9, dbgvcr32_el2 +0x89,0x00,0x30,0xd5 = mrs x9, dbgbvr0_el1 +0x89,0x01,0x30,0xd5 = mrs x9, dbgbvr1_el1 +0x89,0x02,0x30,0xd5 = mrs x9, dbgbvr2_el1 +0x89,0x03,0x30,0xd5 = mrs x9, dbgbvr3_el1 +0x89,0x04,0x30,0xd5 = mrs x9, dbgbvr4_el1 +0x89,0x05,0x30,0xd5 = mrs x9, dbgbvr5_el1 +0x89,0x06,0x30,0xd5 = mrs x9, dbgbvr6_el1 +0x89,0x07,0x30,0xd5 = mrs x9, dbgbvr7_el1 +0x89,0x08,0x30,0xd5 = mrs x9, dbgbvr8_el1 +0x89,0x09,0x30,0xd5 = mrs x9, dbgbvr9_el1 +0x89,0x0a,0x30,0xd5 = mrs x9, dbgbvr10_el1 +0x89,0x0b,0x30,0xd5 = mrs x9, dbgbvr11_el1 +0x89,0x0c,0x30,0xd5 = mrs x9, dbgbvr12_el1 +0x89,0x0d,0x30,0xd5 = mrs x9, dbgbvr13_el1 +0x89,0x0e,0x30,0xd5 = mrs x9, dbgbvr14_el1 +0x89,0x0f,0x30,0xd5 = mrs x9, dbgbvr15_el1 +0xa9,0x00,0x30,0xd5 = mrs x9, dbgbcr0_el1 +0xa9,0x01,0x30,0xd5 = mrs x9, dbgbcr1_el1 +0xa9,0x02,0x30,0xd5 = mrs x9, dbgbcr2_el1 +0xa9,0x03,0x30,0xd5 = mrs x9, dbgbcr3_el1 +0xa9,0x04,0x30,0xd5 = mrs x9, dbgbcr4_el1 +0xa9,0x05,0x30,0xd5 = mrs x9, dbgbcr5_el1 +0xa9,0x06,0x30,0xd5 = mrs x9, dbgbcr6_el1 +0xa9,0x07,0x30,0xd5 = mrs x9, dbgbcr7_el1 +0xa9,0x08,0x30,0xd5 = mrs x9, dbgbcr8_el1 +0xa9,0x09,0x30,0xd5 = mrs x9, dbgbcr9_el1 +0xa9,0x0a,0x30,0xd5 = mrs x9, dbgbcr10_el1 +0xa9,0x0b,0x30,0xd5 = mrs x9, dbgbcr11_el1 +0xa9,0x0c,0x30,0xd5 = mrs x9, dbgbcr12_el1 +0xa9,0x0d,0x30,0xd5 = mrs x9, dbgbcr13_el1 +0xa9,0x0e,0x30,0xd5 = mrs x9, dbgbcr14_el1 +0xa9,0x0f,0x30,0xd5 = mrs x9, dbgbcr15_el1 +0xc9,0x00,0x30,0xd5 = mrs x9, dbgwvr0_el1 +0xc9,0x01,0x30,0xd5 = mrs x9, dbgwvr1_el1 +0xc9,0x02,0x30,0xd5 = mrs x9, dbgwvr2_el1 +0xc9,0x03,0x30,0xd5 = mrs x9, dbgwvr3_el1 +0xc9,0x04,0x30,0xd5 = mrs x9, dbgwvr4_el1 +0xc9,0x05,0x30,0xd5 = mrs x9, dbgwvr5_el1 +0xc9,0x06,0x30,0xd5 = mrs x9, dbgwvr6_el1 +0xc9,0x07,0x30,0xd5 = mrs x9, dbgwvr7_el1 +0xc9,0x08,0x30,0xd5 = mrs x9, dbgwvr8_el1 +0xc9,0x09,0x30,0xd5 = mrs x9, dbgwvr9_el1 +0xc9,0x0a,0x30,0xd5 = mrs x9, dbgwvr10_el1 +0xc9,0x0b,0x30,0xd5 = mrs x9, dbgwvr11_el1 +0xc9,0x0c,0x30,0xd5 = mrs x9, dbgwvr12_el1 +0xc9,0x0d,0x30,0xd5 = mrs x9, dbgwvr13_el1 +0xc9,0x0e,0x30,0xd5 = mrs x9, dbgwvr14_el1 +0xc9,0x0f,0x30,0xd5 = mrs x9, dbgwvr15_el1 +0xe9,0x00,0x30,0xd5 = mrs x9, dbgwcr0_el1 +0xe9,0x01,0x30,0xd5 = mrs x9, dbgwcr1_el1 +0xe9,0x02,0x30,0xd5 = mrs x9, dbgwcr2_el1 +0xe9,0x03,0x30,0xd5 = mrs x9, dbgwcr3_el1 +0xe9,0x04,0x30,0xd5 = mrs x9, dbgwcr4_el1 +0xe9,0x05,0x30,0xd5 = mrs x9, dbgwcr5_el1 +0xe9,0x06,0x30,0xd5 = mrs x9, dbgwcr6_el1 +0xe9,0x07,0x30,0xd5 = mrs x9, dbgwcr7_el1 +0xe9,0x08,0x30,0xd5 = mrs x9, dbgwcr8_el1 +0xe9,0x09,0x30,0xd5 = mrs x9, dbgwcr9_el1 +0xe9,0x0a,0x30,0xd5 = mrs x9, dbgwcr10_el1 +0xe9,0x0b,0x30,0xd5 = mrs x9, dbgwcr11_el1 +0xe9,0x0c,0x30,0xd5 = mrs x9, dbgwcr12_el1 +0xe9,0x0d,0x30,0xd5 = mrs x9, dbgwcr13_el1 +0xe9,0x0e,0x30,0xd5 = mrs x9, dbgwcr14_el1 +0xe9,0x0f,0x30,0xd5 = mrs x9, dbgwcr15_el1 +0x09,0x10,0x30,0xd5 = mrs x9, mdrar_el1 +0x09,0x10,0x32,0xd5 = mrs x9, teehbr32_el1 +0x89,0x11,0x30,0xd5 = mrs x9, oslsr_el1 +0x89,0x13,0x30,0xd5 = mrs x9, osdlr_el1 +0x89,0x14,0x30,0xd5 = mrs x9, dbgprcr_el1 +0xc9,0x78,0x30,0xd5 = mrs x9, dbgclaimset_el1 +0xc9,0x79,0x30,0xd5 = mrs x9, dbgclaimclr_el1 +0xc9,0x7e,0x30,0xd5 = mrs x9, dbgauthstatus_el1 +0x09,0x00,0x38,0xd5 = mrs x9, midr_el1 +0x09,0x00,0x39,0xd5 = mrs x9, ccsidr_el1 +0x09,0x00,0x3a,0xd5 = mrs x9, csselr_el1 +0x09,0x00,0x3c,0xd5 = mrs x9, vpidr_el2 +0x29,0x00,0x39,0xd5 = mrs x9, clidr_el1 +0x29,0x00,0x3b,0xd5 = mrs x9, ctr_el0 +0xa9,0x00,0x38,0xd5 = mrs x9, mpidr_el1 +0xa9,0x00,0x3c,0xd5 = mrs x9, vmpidr_el2 +0xc9,0x00,0x38,0xd5 = mrs x9, revidr_el1 +0xe9,0x00,0x39,0xd5 = mrs x9, aidr_el1 +0xe9,0x00,0x3b,0xd5 = mrs x9, dczid_el0 +0x09,0x01,0x38,0xd5 = mrs x9, id_pfr0_el1 +0x29,0x01,0x38,0xd5 = mrs x9, id_pfr1_el1 +0x49,0x01,0x38,0xd5 = mrs x9, id_dfr0_el1 +0x69,0x01,0x38,0xd5 = mrs x9, id_afr0_el1 +0x89,0x01,0x38,0xd5 = mrs x9, id_mmfr0_el1 +0xa9,0x01,0x38,0xd5 = mrs x9, id_mmfr1_el1 +0xc9,0x01,0x38,0xd5 = mrs x9, id_mmfr2_el1 +0xe9,0x01,0x38,0xd5 = mrs x9, id_mmfr3_el1 +0xc9,0x02,0x38,0xd5 = mrs x9, id_mmfr4_el1 +0x09,0x02,0x38,0xd5 = mrs x9, id_isar0_el1 +0x29,0x02,0x38,0xd5 = mrs x9, id_isar1_el1 +0x49,0x02,0x38,0xd5 = mrs x9, id_isar2_el1 +0x69,0x02,0x38,0xd5 = mrs x9, id_isar3_el1 +0x89,0x02,0x38,0xd5 = mrs x9, id_isar4_el1 +0xa9,0x02,0x38,0xd5 = mrs x9, id_isar5_el1 +0x09,0x03,0x38,0xd5 = mrs x9, mvfr0_el1 +0x29,0x03,0x38,0xd5 = mrs x9, mvfr1_el1 +0x49,0x03,0x38,0xd5 = mrs x9, mvfr2_el1 +0x09,0x04,0x38,0xd5 = mrs x9, id_aa64pfr0_el1 +0x29,0x04,0x38,0xd5 = mrs x9, id_aa64pfr1_el1 +0x09,0x05,0x38,0xd5 = mrs x9, id_aa64dfr0_el1 +0x29,0x05,0x38,0xd5 = mrs x9, id_aa64dfr1_el1 +0x89,0x05,0x38,0xd5 = mrs x9, id_aa64afr0_el1 +0xa9,0x05,0x38,0xd5 = mrs x9, id_aa64afr1_el1 +0x09,0x06,0x38,0xd5 = mrs x9, id_aa64isar0_el1 +0x29,0x06,0x38,0xd5 = mrs x9, id_aa64isar1_el1 +0x09,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr0_el1 +0x29,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr1_el1 +0x49,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr2_el1 +0x69,0xa4,0x38,0xd5 = mrs x9, lorc_el1 +0x29,0xa4,0x38,0xd5 = mrs x9, lorea_el1 +0xe9,0xa4,0x38,0xd5 = mrs x9, lorid_el1 +0x49,0xa4,0x38,0xd5 = mrs x9, lorn_el1 +0x09,0xa4,0x38,0xd5 = mrs x9, lorsa_el1 +0x09,0x10,0x38,0xd5 = mrs x9, sctlr_el1 +0x09,0x10,0x3d,0xd5 = mrs x9, sctlr_el12 +0x09,0x10,0x3c,0xd5 = mrs x9, sctlr_el2 +0x09,0x10,0x3e,0xd5 = mrs x9, sctlr_el3 +0x29,0x10,0x38,0xd5 = mrs x9, actlr_el1 +0x29,0x10,0x3c,0xd5 = mrs x9, actlr_el2 +0x29,0x10,0x3e,0xd5 = mrs x9, actlr_el3 +0x49,0x10,0x38,0xd5 = mrs x9, cpacr_el1 +0x49,0x10,0x3d,0xd5 = mrs x9, cpacr_el12 +0x09,0x11,0x3c,0xd5 = mrs x9, hcr_el2 +0x09,0x11,0x3e,0xd5 = mrs x9, scr_el3 +0x29,0x11,0x3c,0xd5 = mrs x9, mdcr_el2 +0x29,0x11,0x3e,0xd5 = mrs x9, sder32_el3 +0x49,0x11,0x3c,0xd5 = mrs x9, cptr_el2 +0x49,0x11,0x3e,0xd5 = mrs x9, cptr_el3 +0x69,0x11,0x3c,0xd5 = mrs x9, hstr_el2 +0xe9,0x11,0x3c,0xd5 = mrs x9, hacr_el2 +0x29,0x13,0x3e,0xd5 = mrs x9, mdcr_el3 +0x09,0x20,0x38,0xd5 = mrs x9, ttbr0_el1 +0x09,0x20,0x3d,0xd5 = mrs x9, ttbr0_el12 +0x09,0x20,0x3c,0xd5 = mrs x9, ttbr0_el2 +0x09,0x20,0x3e,0xd5 = mrs x9, ttbr0_el3 +0x29,0x20,0x38,0xd5 = mrs x9, ttbr1_el1 +0x29,0x20,0x3d,0xd5 = mrs x9, ttbr1_el12 +0x29,0x20,0x3c,0xd5 = mrs x9, ttbr1_el2 +0x49,0x20,0x38,0xd5 = mrs x9, tcr_el1 +0x49,0x20,0x3d,0xd5 = mrs x9, tcr_el12 +0x49,0x20,0x3c,0xd5 = mrs x9, tcr_el2 +0x49,0x20,0x3e,0xd5 = mrs x9, tcr_el3 +0x09,0x21,0x3c,0xd5 = mrs x9, vttbr_el2 +0x49,0x21,0x3c,0xd5 = mrs x9, vtcr_el2 +0x09,0x30,0x3c,0xd5 = mrs x9, dacr32_el2 +0x09,0x40,0x38,0xd5 = mrs x9, spsr_el1 +0x09,0x40,0x3d,0xd5 = mrs x9, spsr_el12 +0x09,0x40,0x3c,0xd5 = mrs x9, spsr_el2 +0x09,0x40,0x3e,0xd5 = mrs x9, spsr_el3 +0x29,0x40,0x38,0xd5 = mrs x9, elr_el1 +0x29,0x40,0x3d,0xd5 = mrs x9, elr_el12 +0x29,0x40,0x3c,0xd5 = mrs x9, elr_el2 +0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3 +0x09,0x41,0x38,0xd5 = mrs x9, sp_el0 +0x09,0x41,0x3c,0xd5 = mrs x9, sp_el1 +0x09,0x41,0x3e,0xd5 = mrs x9, sp_el2 +0x09,0x42,0x38,0xd5 = mrs x9, spsel +0x09,0x42,0x3b,0xd5 = mrs x9, nzcv +0x29,0x42,0x3b,0xd5 = mrs x9, daif +0x49,0x42,0x38,0xd5 = mrs x9, currentel +0x09,0x43,0x3c,0xd5 = mrs x9, spsr_irq +0x29,0x43,0x3c,0xd5 = mrs x9, spsr_abt +0x49,0x43,0x3c,0xd5 = mrs x9, spsr_und +0x69,0x43,0x3c,0xd5 = mrs x9, spsr_fiq +0x09,0x44,0x3b,0xd5 = mrs x9, fpcr +0x29,0x44,0x3b,0xd5 = mrs x9, fpsr +0x09,0x45,0x3b,0xd5 = mrs x9, dspsr_el0 +0x29,0x45,0x3b,0xd5 = mrs x9, dlr_el0 +0x29,0x50,0x3c,0xd5 = mrs x9, ifsr32_el2 +0x09,0x51,0x38,0xd5 = mrs x9, afsr0_el1 +0x09,0x51,0x3d,0xd5 = mrs x9, afsr0_el12 +0x09,0x51,0x3c,0xd5 = mrs x9, afsr0_el2 +0x09,0x51,0x3e,0xd5 = mrs x9, afsr0_el3 +0x29,0x51,0x38,0xd5 = mrs x9, afsr1_el1 +0x29,0x51,0x3c,0xd5 = mrs x9, afsr1_el2 +0x29,0x51,0x3e,0xd5 = mrs x9, afsr1_el3 +0x09,0x52,0x38,0xd5 = mrs x9, esr_el1 +0x09,0x52,0x3d,0xd5 = mrs x9, esr_el12 +0x09,0x52,0x3c,0xd5 = mrs x9, esr_el2 +0x09,0x52,0x3e,0xd5 = mrs x9, esr_el3 +0x09,0x53,0x3c,0xd5 = mrs x9, fpexc32_el2 +0x09,0x60,0x38,0xd5 = mrs x9, far_el1 +0x09,0x60,0x3d,0xd5 = mrs x9, far_el12 +0x09,0x60,0x3c,0xd5 = mrs x9, far_el2 +0x09,0x60,0x3e,0xd5 = mrs x9, far_el3 +0x89,0x60,0x3c,0xd5 = mrs x9, hpfar_el2 +0x09,0x74,0x38,0xd5 = mrs x9, par_el1 +0x09,0x9c,0x3b,0xd5 = mrs x9, pmcr_el0 +0x29,0x9c,0x3b,0xd5 = mrs x9, pmcntenset_el0 +0x49,0x9c,0x3b,0xd5 = mrs x9, pmcntenclr_el0 +0x69,0x9c,0x3b,0xd5 = mrs x9, pmovsclr_el0 +0xa9,0x9c,0x3b,0xd5 = mrs x9, pmselr_el0 +0xc9,0x9c,0x3b,0xd5 = mrs x9, pmceid0_el0 +0xe9,0x9c,0x3b,0xd5 = mrs x9, pmceid1_el0 +0x09,0x9d,0x3b,0xd5 = mrs x9, pmccntr_el0 +0x29,0x9d,0x3b,0xd5 = mrs x9, pmxevtyper_el0 +0x49,0x9d,0x3b,0xd5 = mrs x9, pmxevcntr_el0 +0x09,0x9e,0x3b,0xd5 = mrs x9, pmuserenr_el0 +0x29,0x9e,0x38,0xd5 = mrs x9, pmintenset_el1 +0x49,0x9e,0x38,0xd5 = mrs x9, pmintenclr_el1 +0x69,0x9e,0x3b,0xd5 = mrs x9, pmovsset_el0 +0x09,0xa2,0x38,0xd5 = mrs x9, mair_el1 +0x09,0xa2,0x3d,0xd5 = mrs x9, mair_el12 +0x09,0xa2,0x3c,0xd5 = mrs x9, mair_el2 +0x09,0xa2,0x3e,0xd5 = mrs x9, mair_el3 +0x09,0xa3,0x38,0xd5 = mrs x9, amair_el1 +0x09,0xa3,0x3d,0xd5 = mrs x9, amair_el12 +0x09,0xa3,0x3c,0xd5 = mrs x9, amair_el2 +0x09,0xa3,0x3e,0xd5 = mrs x9, amair_el3 +0x09,0xc0,0x38,0xd5 = mrs x9, vbar_el1 +0x09,0xc0,0x3d,0xd5 = mrs x9, vbar_el12 +0x09,0xc0,0x3c,0xd5 = mrs x9, vbar_el2 +0x09,0xc0,0x3e,0xd5 = mrs x9, vbar_el3 +0x29,0xc0,0x38,0xd5 = mrs x9, rvbar_el1 +0x29,0xc0,0x3c,0xd5 = mrs x9, rvbar_el2 +0x29,0xc0,0x3e,0xd5 = mrs x9, rvbar_el3 +0x49,0xc0,0x38,0xd5 = mrs x9, rmr_el1 +0x49,0xc0,0x3c,0xd5 = mrs x9, rmr_el2 +0x49,0xc0,0x3e,0xd5 = mrs x9, rmr_el3 +0x09,0xc1,0x38,0xd5 = mrs x9, isr_el1 +0x29,0xd0,0x38,0xd5 = mrs x9, contextidr_el1 +0x29,0xd0,0x3d,0xd5 = mrs x9, contextidr_el12 +// 0x29,0xd0,0x3c,0xd5 = mrs x9, contextdir_el2 +0x49,0xd0,0x3b,0xd5 = mrs x9, tpidr_el0 +0x49,0xd0,0x3c,0xd5 = mrs x9, tpidr_el2 +0x49,0xd0,0x3e,0xd5 = mrs x9, tpidr_el3 +0x69,0xd0,0x3b,0xd5 = mrs x9, tpidrro_el0 +0x89,0xd0,0x38,0xd5 = mrs x9, tpidr_el1 +0x09,0xe0,0x3b,0xd5 = mrs x9, cntfrq_el0 +0x29,0xe0,0x3b,0xd5 = mrs x9, cntpct_el0 +0x49,0xe0,0x3b,0xd5 = mrs x9, cntvct_el0 +0x69,0xe0,0x3c,0xd5 = mrs x9, cntvoff_el2 +0x09,0xe1,0x38,0xd5 = mrs x9, cntkctl_el1 +0x09,0xe1,0x3d,0xd5 = mrs x9, cntkctl_el12 +0x09,0xe1,0x3c,0xd5 = mrs x9, cnthctl_el2 +0x09,0xe2,0x3b,0xd5 = mrs x9, cntp_tval_el0 +0x09,0xe2,0x3d,0xd5 = mrs x9, cntp_tval_el02 +0x09,0xe2,0x3c,0xd5 = mrs x9, cnthp_tval_el2 +0x09,0xe2,0x3f,0xd5 = mrs x9, cntps_tval_el1 +0x29,0xe2,0x3b,0xd5 = mrs x9, cntp_ctl_el0 +0x29,0xe2,0x3c,0xd5 = mrs x9, cnthp_ctl_el2 +0x29,0xe2,0x3f,0xd5 = mrs x9, cntps_ctl_el1 +0x49,0xe2,0x3b,0xd5 = mrs x9, cntp_cval_el0 +0x49,0xe2,0x3d,0xd5 = mrs x9, cntp_cval_el02 +0x49,0xe2,0x3c,0xd5 = mrs x9, cnthp_cval_el2 +// 0x20,0xe3,0x3c,0xd5 = mrs x9, cnthv_ctl_el2 +0x49,0xe3,0x3c,0xd5 = mrs x9, cnthv_cval_el2 +0x09,0xe3,0x3c,0xd5 = mrs x9, cnthv_tval_el2 +0x49,0xe2,0x3f,0xd5 = mrs x9, cntps_cval_el1 +0x09,0xe3,0x3b,0xd5 = mrs x9, cntv_tval_el0 +0x29,0xe3,0x3b,0xd5 = mrs x9, cntv_ctl_el0 +0x29,0xe3,0x3d,0xd5 = mrs x9, cntv_ctl_el02 +0x49,0xe3,0x3b,0xd5 = mrs x9, cntv_cval_el0 +0x49,0xe3,0x3d,0xd5 = mrs x9, cntv_cval_el02 +0x09,0xe8,0x3b,0xd5 = mrs x9, pmevcntr0_el0 +0x29,0xe8,0x3b,0xd5 = mrs x9, pmevcntr1_el0 +0x49,0xe8,0x3b,0xd5 = mrs x9, pmevcntr2_el0 +0x69,0xe8,0x3b,0xd5 = mrs x9, pmevcntr3_el0 +0x89,0xe8,0x3b,0xd5 = mrs x9, pmevcntr4_el0 +0xa9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr5_el0 +0xc9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr6_el0 +0xe9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr7_el0 +0x09,0xe9,0x3b,0xd5 = mrs x9, pmevcntr8_el0 +0x29,0xe9,0x3b,0xd5 = mrs x9, pmevcntr9_el0 +0x49,0xe9,0x3b,0xd5 = mrs x9, pmevcntr10_el0 +0x69,0xe9,0x3b,0xd5 = mrs x9, pmevcntr11_el0 +0x89,0xe9,0x3b,0xd5 = mrs x9, pmevcntr12_el0 +0xa9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr13_el0 +0xc9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr14_el0 +0xe9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr15_el0 +0x09,0xea,0x3b,0xd5 = mrs x9, pmevcntr16_el0 +0x29,0xea,0x3b,0xd5 = mrs x9, pmevcntr17_el0 +0x49,0xea,0x3b,0xd5 = mrs x9, pmevcntr18_el0 +0x69,0xea,0x3b,0xd5 = mrs x9, pmevcntr19_el0 +0x89,0xea,0x3b,0xd5 = mrs x9, pmevcntr20_el0 +0xa9,0xea,0x3b,0xd5 = mrs x9, pmevcntr21_el0 +0xc9,0xea,0x3b,0xd5 = mrs x9, pmevcntr22_el0 +0xe9,0xea,0x3b,0xd5 = mrs x9, pmevcntr23_el0 +0x09,0xeb,0x3b,0xd5 = mrs x9, pmevcntr24_el0 +0x29,0xeb,0x3b,0xd5 = mrs x9, pmevcntr25_el0 +0x49,0xeb,0x3b,0xd5 = mrs x9, pmevcntr26_el0 +0x69,0xeb,0x3b,0xd5 = mrs x9, pmevcntr27_el0 +0x89,0xeb,0x3b,0xd5 = mrs x9, pmevcntr28_el0 +0xa9,0xeb,0x3b,0xd5 = mrs x9, pmevcntr29_el0 +0xc9,0xeb,0x3b,0xd5 = mrs x9, pmevcntr30_el0 +0xe9,0xef,0x3b,0xd5 = mrs x9, pmccfiltr_el0 +0x09,0xec,0x3b,0xd5 = mrs x9, pmevtyper0_el0 +0x29,0xec,0x3b,0xd5 = mrs x9, pmevtyper1_el0 +0x49,0xec,0x3b,0xd5 = mrs x9, pmevtyper2_el0 +0x69,0xec,0x3b,0xd5 = mrs x9, pmevtyper3_el0 +0x89,0xec,0x3b,0xd5 = mrs x9, pmevtyper4_el0 +0xa9,0xec,0x3b,0xd5 = mrs x9, pmevtyper5_el0 +0xc9,0xec,0x3b,0xd5 = mrs x9, pmevtyper6_el0 +0xe9,0xec,0x3b,0xd5 = mrs x9, pmevtyper7_el0 +0x09,0xed,0x3b,0xd5 = mrs x9, pmevtyper8_el0 +0x29,0xed,0x3b,0xd5 = mrs x9, pmevtyper9_el0 +0x49,0xed,0x3b,0xd5 = mrs x9, pmevtyper10_el0 +0x69,0xed,0x3b,0xd5 = mrs x9, pmevtyper11_el0 +0x89,0xed,0x3b,0xd5 = mrs x9, pmevtyper12_el0 +0xa9,0xed,0x3b,0xd5 = mrs x9, pmevtyper13_el0 +0xc9,0xed,0x3b,0xd5 = mrs x9, pmevtyper14_el0 +0xe9,0xed,0x3b,0xd5 = mrs x9, pmevtyper15_el0 +0x09,0xee,0x3b,0xd5 = mrs x9, pmevtyper16_el0 +0x29,0xee,0x3b,0xd5 = mrs x9, pmevtyper17_el0 +0x49,0xee,0x3b,0xd5 = mrs x9, pmevtyper18_el0 +0x69,0xee,0x3b,0xd5 = mrs x9, pmevtyper19_el0 +0x89,0xee,0x3b,0xd5 = mrs x9, pmevtyper20_el0 +0xa9,0xee,0x3b,0xd5 = mrs x9, pmevtyper21_el0 +0xc9,0xee,0x3b,0xd5 = mrs x9, pmevtyper22_el0 +0xe9,0xee,0x3b,0xd5 = mrs x9, pmevtyper23_el0 +0x09,0xef,0x3b,0xd5 = mrs x9, pmevtyper24_el0 +0x29,0xef,0x3b,0xd5 = mrs x9, pmevtyper25_el0 +0x49,0xef,0x3b,0xd5 = mrs x9, pmevtyper26_el0 +0x69,0xef,0x3b,0xd5 = mrs x9, pmevtyper27_el0 +0x89,0xef,0x3b,0xd5 = mrs x9, pmevtyper28_el0 +0xa9,0xef,0x3b,0xd5 = mrs x9, pmevtyper29_el0 +0xc9,0xef,0x3b,0xd5 = mrs x9, pmevtyper30_el0 +0xe9,0x99,0x38,0xd5 = mrs x9, pmsidr_el1 +0xe9,0x9a,0x38,0xd5 = mrs x9, pmbidr_el1 +0x09,0x9a,0x38,0xd5 = mrs x9, pmblimitr_el1 +0x29,0x9a,0x38,0xd5 = mrs x9, pmbptr_el1 +0x69,0x9a,0x38,0xd5 = mrs x9, pmbsr_el1 +0x09,0x99,0x38,0xd5 = mrs x9, pmscr_el1 +0x09,0x99,0x3d,0xd5 = mrs x9, pmscr_el12 +0x09,0x99,0x3c,0xd5 = mrs x9, pmscr_el2 +0x49,0x99,0x38,0xd5 = mrs x9, pmsicr_el1 +0x69,0x99,0x38,0xd5 = mrs x9, pmsirr_el1 +0x89,0x99,0x38,0xd5 = mrs x9, pmsfcr_el1 +0xa9,0x99,0x38,0xd5 = mrs x9, pmsevfr_el1 +0xc9,0x99,0x38,0xd5 = mrs x9, pmslatfr_el1 +0xac,0xf1,0x3f,0xd5 = mrs x12, s3_7_c15_c1_5 +0xed,0xbf,0x3a,0xd5 = mrs x13, s3_2_c11_c15_7 +0x0c,0xf0,0x18,0xd5 = msr s3_0_c15_c0_0, x12 +0xe5,0xbd,0x1f,0xd5 = msr s3_7_c11_c13_7, x5 +0x01,0x00,0x00,0x14 = b #4 +0x00,0x00,0x00,0x94 = bl #0 +0xff,0xff,0xff,0x15 = b #134217724 +0x00,0x00,0x00,0x96 = bl #-134217728 +0x80,0x02,0x1f,0xd6 = br x20 +0xe0,0x03,0x3f,0xd6 = blr xzr +0x40,0x01,0x5f,0xd6 = ret x10 +0xc0,0x03,0x5f,0xd6 = ret +0xe0,0x03,0x9f,0xd6 = eret +0xe0,0x03,0xbf,0xd6 = drps diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/gicv3-regs.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/gicv3-regs.s.cs new file mode 100644 index 0000000..de5cca3 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/gicv3-regs.s.cs @@ -0,0 +1,111 @@ +# CS_ARCH_ARM64, 0, None +0x08,0xcc,0x38,0xd5 = mrs x8, icc_iar1_el1 +0x1a,0xc8,0x38,0xd5 = mrs x26, icc_iar0_el1 +0x42,0xcc,0x38,0xd5 = mrs x2, icc_hppir1_el1 +0x51,0xc8,0x38,0xd5 = mrs x17, icc_hppir0_el1 +0x7d,0xcb,0x38,0xd5 = mrs x29, icc_rpr_el1 +0x24,0xcb,0x3c,0xd5 = mrs x4, ich_vtr_el2 +0x78,0xcb,0x3c,0xd5 = mrs x24, ich_eisr_el2 +0xa9,0xcb,0x3c,0xd5 = mrs x9, ich_elsr_el2 +0x78,0xcc,0x38,0xd5 = mrs x24, icc_bpr1_el1 +0x6e,0xc8,0x38,0xd5 = mrs x14, icc_bpr0_el1 +0x13,0x46,0x38,0xd5 = mrs x19, icc_pmr_el1 +0x97,0xcc,0x38,0xd5 = mrs x23, icc_ctlr_el1 +0x94,0xcc,0x3e,0xd5 = mrs x20, icc_ctlr_el3 +0xbc,0xcc,0x38,0xd5 = mrs x28, icc_sre_el1 +0xb9,0xc9,0x3c,0xd5 = mrs x25, icc_sre_el2 +0xa8,0xcc,0x3e,0xd5 = mrs x8, icc_sre_el3 +0xd6,0xcc,0x38,0xd5 = mrs x22, icc_igrpen0_el1 +0xe5,0xcc,0x38,0xd5 = mrs x5, icc_igrpen1_el1 +0xe7,0xcc,0x3e,0xd5 = mrs x7, icc_igrpen1_el3 +0x16,0xcd,0x38,0xd5 = mrs x22, icc_seien_el1 +0x84,0xc8,0x38,0xd5 = mrs x4, icc_ap0r0_el1 +0xab,0xc8,0x38,0xd5 = mrs x11, icc_ap0r1_el1 +0xdb,0xc8,0x38,0xd5 = mrs x27, icc_ap0r2_el1 +0xf5,0xc8,0x38,0xd5 = mrs x21, icc_ap0r3_el1 +0x02,0xc9,0x38,0xd5 = mrs x2, icc_ap1r0_el1 +0x35,0xc9,0x38,0xd5 = mrs x21, icc_ap1r1_el1 +0x4a,0xc9,0x38,0xd5 = mrs x10, icc_ap1r2_el1 +0x7b,0xc9,0x38,0xd5 = mrs x27, icc_ap1r3_el1 +0x14,0xc8,0x3c,0xd5 = mrs x20, ich_ap0r0_el2 +0x35,0xc8,0x3c,0xd5 = mrs x21, ich_ap0r1_el2 +0x45,0xc8,0x3c,0xd5 = mrs x5, ich_ap0r2_el2 +0x64,0xc8,0x3c,0xd5 = mrs x4, ich_ap0r3_el2 +0x0f,0xc9,0x3c,0xd5 = mrs x15, ich_ap1r0_el2 +0x2c,0xc9,0x3c,0xd5 = mrs x12, ich_ap1r1_el2 +0x5b,0xc9,0x3c,0xd5 = mrs x27, ich_ap1r2_el2 +0x74,0xc9,0x3c,0xd5 = mrs x20, ich_ap1r3_el2 +0x0a,0xcb,0x3c,0xd5 = mrs x10, ich_hcr_el2 +0x5b,0xcb,0x3c,0xd5 = mrs x27, ich_misr_el2 +0xe6,0xcb,0x3c,0xd5 = mrs x6, ich_vmcr_el2 +0x93,0xc9,0x3c,0xd5 = mrs x19, ich_vseir_el2 +0x03,0xcc,0x3c,0xd5 = mrs x3, ich_lr0_el2 +0x21,0xcc,0x3c,0xd5 = mrs x1, ich_lr1_el2 +0x56,0xcc,0x3c,0xd5 = mrs x22, ich_lr2_el2 +0x75,0xcc,0x3c,0xd5 = mrs x21, ich_lr3_el2 +0x86,0xcc,0x3c,0xd5 = mrs x6, ich_lr4_el2 +0xaa,0xcc,0x3c,0xd5 = mrs x10, ich_lr5_el2 +0xcb,0xcc,0x3c,0xd5 = mrs x11, ich_lr6_el2 +0xec,0xcc,0x3c,0xd5 = mrs x12, ich_lr7_el2 +0x00,0xcd,0x3c,0xd5 = mrs x0, ich_lr8_el2 +0x35,0xcd,0x3c,0xd5 = mrs x21, ich_lr9_el2 +0x4d,0xcd,0x3c,0xd5 = mrs x13, ich_lr10_el2 +0x7a,0xcd,0x3c,0xd5 = mrs x26, ich_lr11_el2 +0x81,0xcd,0x3c,0xd5 = mrs x1, ich_lr12_el2 +0xa8,0xcd,0x3c,0xd5 = mrs x8, ich_lr13_el2 +0xc2,0xcd,0x3c,0xd5 = mrs x2, ich_lr14_el2 +0xe8,0xcd,0x3c,0xd5 = mrs x8, ich_lr15_el2 +0x3b,0xcc,0x18,0xd5 = msr icc_eoir1_el1, x27 +0x25,0xc8,0x18,0xd5 = msr icc_eoir0_el1, x5 +0x2d,0xcb,0x18,0xd5 = msr icc_dir_el1, x13 +0xb5,0xcb,0x18,0xd5 = msr icc_sgi1r_el1, x21 +0xd9,0xcb,0x18,0xd5 = msr icc_asgi1r_el1, x25 +0xfc,0xcb,0x18,0xd5 = msr icc_sgi0r_el1, x28 +0x67,0xcc,0x18,0xd5 = msr icc_bpr1_el1, x7 +0x69,0xc8,0x18,0xd5 = msr icc_bpr0_el1, x9 +0x1d,0x46,0x18,0xd5 = msr icc_pmr_el1, x29 +0x98,0xcc,0x18,0xd5 = msr icc_ctlr_el1, x24 +0x80,0xcc,0x1e,0xd5 = msr icc_ctlr_el3, x0 +0xa2,0xcc,0x18,0xd5 = msr icc_sre_el1, x2 +0xa5,0xc9,0x1c,0xd5 = msr icc_sre_el2, x5 +0xaa,0xcc,0x1e,0xd5 = msr icc_sre_el3, x10 +0xd6,0xcc,0x18,0xd5 = msr icc_igrpen0_el1, x22 +0xeb,0xcc,0x18,0xd5 = msr icc_igrpen1_el1, x11 +0xe8,0xcc,0x1e,0xd5 = msr icc_igrpen1_el3, x8 +0x04,0xcd,0x18,0xd5 = msr icc_seien_el1, x4 +0x9b,0xc8,0x18,0xd5 = msr icc_ap0r0_el1, x27 +0xa5,0xc8,0x18,0xd5 = msr icc_ap0r1_el1, x5 +0xd4,0xc8,0x18,0xd5 = msr icc_ap0r2_el1, x20 +0xe0,0xc8,0x18,0xd5 = msr icc_ap0r3_el1, x0 +0x02,0xc9,0x18,0xd5 = msr icc_ap1r0_el1, x2 +0x3d,0xc9,0x18,0xd5 = msr icc_ap1r1_el1, x29 +0x57,0xc9,0x18,0xd5 = msr icc_ap1r2_el1, x23 +0x6b,0xc9,0x18,0xd5 = msr icc_ap1r3_el1, x11 +0x02,0xc8,0x1c,0xd5 = msr ich_ap0r0_el2, x2 +0x3b,0xc8,0x1c,0xd5 = msr ich_ap0r1_el2, x27 +0x47,0xc8,0x1c,0xd5 = msr ich_ap0r2_el2, x7 +0x61,0xc8,0x1c,0xd5 = msr ich_ap0r3_el2, x1 +0x07,0xc9,0x1c,0xd5 = msr ich_ap1r0_el2, x7 +0x2c,0xc9,0x1c,0xd5 = msr ich_ap1r1_el2, x12 +0x4e,0xc9,0x1c,0xd5 = msr ich_ap1r2_el2, x14 +0x6d,0xc9,0x1c,0xd5 = msr ich_ap1r3_el2, x13 +0x01,0xcb,0x1c,0xd5 = msr ich_hcr_el2, x1 +0x4a,0xcb,0x1c,0xd5 = msr ich_misr_el2, x10 +0xf8,0xcb,0x1c,0xd5 = msr ich_vmcr_el2, x24 +0x9d,0xc9,0x1c,0xd5 = msr ich_vseir_el2, x29 +0x1a,0xcc,0x1c,0xd5 = msr ich_lr0_el2, x26 +0x29,0xcc,0x1c,0xd5 = msr ich_lr1_el2, x9 +0x52,0xcc,0x1c,0xd5 = msr ich_lr2_el2, x18 +0x7a,0xcc,0x1c,0xd5 = msr ich_lr3_el2, x26 +0x96,0xcc,0x1c,0xd5 = msr ich_lr4_el2, x22 +0xba,0xcc,0x1c,0xd5 = msr ich_lr5_el2, x26 +0xdb,0xcc,0x1c,0xd5 = msr ich_lr6_el2, x27 +0xe8,0xcc,0x1c,0xd5 = msr ich_lr7_el2, x8 +0x11,0xcd,0x1c,0xd5 = msr ich_lr8_el2, x17 +0x33,0xcd,0x1c,0xd5 = msr ich_lr9_el2, x19 +0x51,0xcd,0x1c,0xd5 = msr ich_lr10_el2, x17 +0x65,0xcd,0x1c,0xd5 = msr ich_lr11_el2, x5 +0x9d,0xcd,0x1c,0xd5 = msr ich_lr12_el2, x29 +0xa2,0xcd,0x1c,0xd5 = msr ich_lr13_el2, x2 +0xcd,0xcd,0x1c,0xd5 = msr ich_lr14_el2, x13 +0xfb,0xcd,0x1c,0xd5 = msr ich_lr15_el2, x27 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-2velem.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-2velem.s.cs new file mode 100644 index 0000000..cf3904d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-2velem.s.cs @@ -0,0 +1,113 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x08,0x82,0x2f = mla v0.2s, v1.2s, v2.s[2] +0x20,0x08,0x96,0x2f = mla v0.2s, v1.2s, v22.s[2] +0x03,0x01,0xa2,0x6f = mla v3.4s, v8.4s, v2.s[1] +0x03,0x09,0xb6,0x6f = mla v3.4s, v8.4s, v22.s[3] +0x20,0x00,0x62,0x2f = mla v0.4h, v1.4h, v2.h[2] +0x20,0x00,0x6f,0x2f = mla v0.4h, v1.4h, v15.h[2] +0x20,0x08,0x72,0x6f = mla v0.8h, v1.8h, v2.h[7] +0x20,0x08,0x6e,0x6f = mla v0.8h, v1.8h, v14.h[6] +0x20,0x48,0x82,0x2f = mls v0.2s, v1.2s, v2.s[2] +0x20,0x48,0x96,0x2f = mls v0.2s, v1.2s, v22.s[2] +0x03,0x41,0xa2,0x6f = mls v3.4s, v8.4s, v2.s[1] +0x03,0x49,0xb6,0x6f = mls v3.4s, v8.4s, v22.s[3] +0x20,0x40,0x62,0x2f = mls v0.4h, v1.4h, v2.h[2] +0x20,0x40,0x6f,0x2f = mls v0.4h, v1.4h, v15.h[2] +0x20,0x48,0x72,0x6f = mls v0.8h, v1.8h, v2.h[7] +0x20,0x48,0x6e,0x6f = mls v0.8h, v1.8h, v14.h[6] +0x20,0x18,0x82,0x0f = fmla v0.2s, v1.2s, v2.s[2] +0x20,0x18,0x96,0x0f = fmla v0.2s, v1.2s, v22.s[2] +0x03,0x11,0xa2,0x4f = fmla v3.4s, v8.4s, v2.s[1] +0x03,0x19,0xb6,0x4f = fmla v3.4s, v8.4s, v22.s[3] +0x20,0x18,0xc2,0x4f = fmla v0.2d, v1.2d, v2.d[1] +0x20,0x18,0xd6,0x4f = fmla v0.2d, v1.2d, v22.d[1] +0x20,0x58,0x82,0x0f = fmls v0.2s, v1.2s, v2.s[2] +0x20,0x58,0x96,0x0f = fmls v0.2s, v1.2s, v22.s[2] +0x03,0x51,0xa2,0x4f = fmls v3.4s, v8.4s, v2.s[1] +0x03,0x59,0xb6,0x4f = fmls v3.4s, v8.4s, v22.s[3] +0x20,0x58,0xc2,0x4f = fmls v0.2d, v1.2d, v2.d[1] +0x20,0x58,0xd6,0x4f = fmls v0.2d, v1.2d, v22.d[1] +0x20,0x20,0x62,0x0f = smlal v0.4s, v1.4h, v2.h[2] +0x20,0x28,0x82,0x0f = smlal v0.2d, v1.2s, v2.s[2] +0x20,0x28,0x96,0x0f = smlal v0.2d, v1.2s, v22.s[2] +0x20,0x20,0x61,0x4f = smlal2 v0.4s, v1.8h, v1.h[2] +0x20,0x28,0x81,0x4f = smlal2 v0.2d, v1.4s, v1.s[2] +0x20,0x28,0x96,0x4f = smlal2 v0.2d, v1.4s, v22.s[2] +0x20,0x60,0x62,0x0f = smlsl v0.4s, v1.4h, v2.h[2] +0x20,0x68,0x82,0x0f = smlsl v0.2d, v1.2s, v2.s[2] +0x20,0x68,0x96,0x0f = smlsl v0.2d, v1.2s, v22.s[2] +0x20,0x60,0x61,0x4f = smlsl2 v0.4s, v1.8h, v1.h[2] +0x20,0x68,0x81,0x4f = smlsl2 v0.2d, v1.4s, v1.s[2] +0x20,0x68,0x96,0x4f = smlsl2 v0.2d, v1.4s, v22.s[2] +0x20,0x30,0x62,0x0f = sqdmlal v0.4s, v1.4h, v2.h[2] +0x20,0x38,0x82,0x0f = sqdmlal v0.2d, v1.2s, v2.s[2] +0x20,0x38,0x96,0x0f = sqdmlal v0.2d, v1.2s, v22.s[2] +0x20,0x30,0x61,0x4f = sqdmlal2 v0.4s, v1.8h, v1.h[2] +0x20,0x38,0x81,0x4f = sqdmlal2 v0.2d, v1.4s, v1.s[2] +0x20,0x38,0x96,0x4f = sqdmlal2 v0.2d, v1.4s, v22.s[2] +0x20,0x20,0x62,0x2f = umlal v0.4s, v1.4h, v2.h[2] +0x20,0x28,0x82,0x2f = umlal v0.2d, v1.2s, v2.s[2] +0x20,0x28,0x96,0x2f = umlal v0.2d, v1.2s, v22.s[2] +0x20,0x20,0x61,0x6f = umlal2 v0.4s, v1.8h, v1.h[2] +0x20,0x28,0x81,0x6f = umlal2 v0.2d, v1.4s, v1.s[2] +0x20,0x28,0x96,0x6f = umlal2 v0.2d, v1.4s, v22.s[2] +0x20,0x60,0x62,0x2f = umlsl v0.4s, v1.4h, v2.h[2] +0x20,0x68,0x82,0x2f = umlsl v0.2d, v1.2s, v2.s[2] +0x20,0x68,0x96,0x2f = umlsl v0.2d, v1.2s, v22.s[2] +0x20,0x60,0x61,0x6f = umlsl2 v0.4s, v1.8h, v1.h[2] +0x20,0x68,0x81,0x6f = umlsl2 v0.2d, v1.4s, v1.s[2] +0x20,0x68,0x96,0x6f = umlsl2 v0.2d, v1.4s, v22.s[2] +0x20,0x70,0x62,0x0f = sqdmlsl v0.4s, v1.4h, v2.h[2] +0x20,0x78,0x82,0x0f = sqdmlsl v0.2d, v1.2s, v2.s[2] +0x20,0x78,0x96,0x0f = sqdmlsl v0.2d, v1.2s, v22.s[2] +0x20,0x70,0x61,0x4f = sqdmlsl2 v0.4s, v1.8h, v1.h[2] +0x20,0x78,0x81,0x4f = sqdmlsl2 v0.2d, v1.4s, v1.s[2] +0x20,0x78,0x96,0x4f = sqdmlsl2 v0.2d, v1.4s, v22.s[2] +0x20,0x80,0x62,0x0f = mul v0.4h, v1.4h, v2.h[2] +0x20,0x80,0x62,0x4f = mul v0.8h, v1.8h, v2.h[2] +0x20,0x88,0x82,0x0f = mul v0.2s, v1.2s, v2.s[2] +0x20,0x88,0x96,0x0f = mul v0.2s, v1.2s, v22.s[2] +0x20,0x88,0x82,0x4f = mul v0.4s, v1.4s, v2.s[2] +0x20,0x88,0x96,0x4f = mul v0.4s, v1.4s, v22.s[2] +0x20,0x98,0x82,0x0f = fmul v0.2s, v1.2s, v2.s[2] +0x20,0x98,0x96,0x0f = fmul v0.2s, v1.2s, v22.s[2] +0x20,0x98,0x82,0x4f = fmul v0.4s, v1.4s, v2.s[2] +0x20,0x98,0x96,0x4f = fmul v0.4s, v1.4s, v22.s[2] +0x20,0x98,0xc2,0x4f = fmul v0.2d, v1.2d, v2.d[1] +0x20,0x98,0xd6,0x4f = fmul v0.2d, v1.2d, v22.d[1] +0x20,0x98,0x82,0x2f = fmulx v0.2s, v1.2s, v2.s[2] +0x20,0x98,0x96,0x2f = fmulx v0.2s, v1.2s, v22.s[2] +0x20,0x98,0x82,0x6f = fmulx v0.4s, v1.4s, v2.s[2] +0x20,0x98,0x96,0x6f = fmulx v0.4s, v1.4s, v22.s[2] +0x20,0x98,0xc2,0x6f = fmulx v0.2d, v1.2d, v2.d[1] +0x20,0x98,0xd6,0x6f = fmulx v0.2d, v1.2d, v22.d[1] +0x20,0xa0,0x62,0x0f = smull v0.4s, v1.4h, v2.h[2] +0x20,0xa8,0x82,0x0f = smull v0.2d, v1.2s, v2.s[2] +0x20,0xa8,0x96,0x0f = smull v0.2d, v1.2s, v22.s[2] +0x20,0xa0,0x62,0x4f = smull2 v0.4s, v1.8h, v2.h[2] +0x20,0xa8,0x82,0x4f = smull2 v0.2d, v1.4s, v2.s[2] +0x20,0xa8,0x96,0x4f = smull2 v0.2d, v1.4s, v22.s[2] +0x20,0xa0,0x62,0x2f = umull v0.4s, v1.4h, v2.h[2] +0x20,0xa8,0x82,0x2f = umull v0.2d, v1.2s, v2.s[2] +0x20,0xa8,0x96,0x2f = umull v0.2d, v1.2s, v22.s[2] +0x20,0xa0,0x62,0x6f = umull2 v0.4s, v1.8h, v2.h[2] +0x20,0xa8,0x82,0x6f = umull2 v0.2d, v1.4s, v2.s[2] +0x20,0xa8,0x96,0x6f = umull2 v0.2d, v1.4s, v22.s[2] +0x20,0xb0,0x62,0x0f = sqdmull v0.4s, v1.4h, v2.h[2] +0x20,0xb8,0x82,0x0f = sqdmull v0.2d, v1.2s, v2.s[2] +0x20,0xb8,0x96,0x0f = sqdmull v0.2d, v1.2s, v22.s[2] +0x20,0xb0,0x62,0x4f = sqdmull2 v0.4s, v1.8h, v2.h[2] +0x20,0xb8,0x82,0x4f = sqdmull2 v0.2d, v1.4s, v2.s[2] +0x20,0xb8,0x96,0x4f = sqdmull2 v0.2d, v1.4s, v22.s[2] +0x20,0xc0,0x62,0x0f = sqdmulh v0.4h, v1.4h, v2.h[2] +0x20,0xc0,0x62,0x4f = sqdmulh v0.8h, v1.8h, v2.h[2] +0x20,0xc8,0x82,0x0f = sqdmulh v0.2s, v1.2s, v2.s[2] +0x20,0xc8,0x96,0x0f = sqdmulh v0.2s, v1.2s, v22.s[2] +0x20,0xc8,0x82,0x4f = sqdmulh v0.4s, v1.4s, v2.s[2] +0x20,0xc8,0x96,0x4f = sqdmulh v0.4s, v1.4s, v22.s[2] +0x20,0xd0,0x62,0x0f = sqrdmulh v0.4h, v1.4h, v2.h[2] +0x20,0xd0,0x62,0x4f = sqrdmulh v0.8h, v1.8h, v2.h[2] +0x20,0xd8,0x82,0x0f = sqrdmulh v0.2s, v1.2s, v2.s[2] +0x20,0xd8,0x96,0x0f = sqrdmulh v0.2s, v1.2s, v22.s[2] +0x20,0xd8,0x82,0x4f = sqrdmulh v0.4s, v1.4s, v2.s[2] +0x20,0xd8,0x96,0x4f = sqrdmulh v0.4s, v1.4s, v22.s[2] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-3vdiff.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-3vdiff.s.cs new file mode 100644 index 0000000..2edd4e4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-3vdiff.s.cs @@ -0,0 +1,143 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x00,0x22,0x0e = saddl v0.8h, v1.8b, v2.8b +0x20,0x00,0x62,0x0e = saddl v0.4s, v1.4h, v2.4h +0x20,0x00,0xa2,0x0e = saddl v0.2d, v1.2s, v2.2s +0x20,0x00,0x62,0x4e = saddl2 v0.4s, v1.8h, v2.8h +0x20,0x00,0x22,0x4e = saddl2 v0.8h, v1.16b, v2.16b +0x20,0x00,0xa2,0x4e = saddl2 v0.2d, v1.4s, v2.4s +0x20,0x00,0x22,0x2e = uaddl v0.8h, v1.8b, v2.8b +0x20,0x00,0x62,0x2e = uaddl v0.4s, v1.4h, v2.4h +0x20,0x00,0xa2,0x2e = uaddl v0.2d, v1.2s, v2.2s +0x20,0x00,0x22,0x6e = uaddl2 v0.8h, v1.16b, v2.16b +0x20,0x00,0x62,0x6e = uaddl2 v0.4s, v1.8h, v2.8h +0x20,0x00,0xa2,0x6e = uaddl2 v0.2d, v1.4s, v2.4s +0x20,0x20,0x22,0x0e = ssubl v0.8h, v1.8b, v2.8b +0x20,0x20,0x62,0x0e = ssubl v0.4s, v1.4h, v2.4h +0x20,0x20,0xa2,0x0e = ssubl v0.2d, v1.2s, v2.2s +0x20,0x20,0x22,0x4e = ssubl2 v0.8h, v1.16b, v2.16b +0x20,0x20,0x62,0x4e = ssubl2 v0.4s, v1.8h, v2.8h +0x20,0x20,0xa2,0x4e = ssubl2 v0.2d, v1.4s, v2.4s +0x20,0x20,0x22,0x2e = usubl v0.8h, v1.8b, v2.8b +0x20,0x20,0x62,0x2e = usubl v0.4s, v1.4h, v2.4h +0x20,0x20,0xa2,0x2e = usubl v0.2d, v1.2s, v2.2s +0x20,0x20,0x22,0x6e = usubl2 v0.8h, v1.16b, v2.16b +0x20,0x20,0x62,0x6e = usubl2 v0.4s, v1.8h, v2.8h +0x20,0x20,0xa2,0x6e = usubl2 v0.2d, v1.4s, v2.4s +0x20,0x50,0x22,0x0e = sabal v0.8h, v1.8b, v2.8b +0x20,0x50,0x62,0x0e = sabal v0.4s, v1.4h, v2.4h +0x20,0x50,0xa2,0x0e = sabal v0.2d, v1.2s, v2.2s +0x20,0x50,0x22,0x4e = sabal2 v0.8h, v1.16b, v2.16b +0x20,0x50,0x62,0x4e = sabal2 v0.4s, v1.8h, v2.8h +0x20,0x50,0xa2,0x4e = sabal2 v0.2d, v1.4s, v2.4s +0x20,0x50,0x22,0x2e = uabal v0.8h, v1.8b, v2.8b +0x20,0x50,0x62,0x2e = uabal v0.4s, v1.4h, v2.4h +0x20,0x50,0xa2,0x2e = uabal v0.2d, v1.2s, v2.2s +0x20,0x50,0x22,0x6e = uabal2 v0.8h, v1.16b, v2.16b +0x20,0x50,0x62,0x6e = uabal2 v0.4s, v1.8h, v2.8h +0x20,0x50,0xa2,0x6e = uabal2 v0.2d, v1.4s, v2.4s +0x20,0x70,0x22,0x0e = sabdl v0.8h, v1.8b, v2.8b +0x20,0x70,0x62,0x0e = sabdl v0.4s, v1.4h, v2.4h +0x20,0x70,0xa2,0x0e = sabdl v0.2d, v1.2s, v2.2s +0x20,0x70,0x22,0x4e = sabdl2 v0.8h, v1.16b, v2.16b +0x20,0x70,0x62,0x4e = sabdl2 v0.4s, v1.8h, v2.8h +0x20,0x70,0xa2,0x4e = sabdl2 v0.2d, v1.4s, v2.4s +0x20,0x70,0x22,0x2e = uabdl v0.8h, v1.8b, v2.8b +0x20,0x70,0x62,0x2e = uabdl v0.4s, v1.4h, v2.4h +0x20,0x70,0xa2,0x2e = uabdl v0.2d, v1.2s, v2.2s +0x20,0x70,0x22,0x6e = uabdl2 v0.8h, v1.16b, v2.16b +0x20,0x70,0x62,0x6e = uabdl2 v0.4s, v1.8h, v2.8h +0x20,0x70,0xa2,0x6e = uabdl2 v0.2d, v1.4s, v2.4s +0x20,0x80,0x22,0x0e = smlal v0.8h, v1.8b, v2.8b +0x20,0x80,0x62,0x0e = smlal v0.4s, v1.4h, v2.4h +0x20,0x80,0xa2,0x0e = smlal v0.2d, v1.2s, v2.2s +0x20,0x80,0x22,0x4e = smlal2 v0.8h, v1.16b, v2.16b +0x20,0x80,0x62,0x4e = smlal2 v0.4s, v1.8h, v2.8h +0x20,0x80,0xa2,0x4e = smlal2 v0.2d, v1.4s, v2.4s +0x20,0x80,0x22,0x2e = umlal v0.8h, v1.8b, v2.8b +0x20,0x80,0x62,0x2e = umlal v0.4s, v1.4h, v2.4h +0x20,0x80,0xa2,0x2e = umlal v0.2d, v1.2s, v2.2s +0x20,0x80,0x22,0x6e = umlal2 v0.8h, v1.16b, v2.16b +0x20,0x80,0x62,0x6e = umlal2 v0.4s, v1.8h, v2.8h +0x20,0x80,0xa2,0x6e = umlal2 v0.2d, v1.4s, v2.4s +0x20,0xa0,0x22,0x0e = smlsl v0.8h, v1.8b, v2.8b +0x20,0xa0,0x62,0x0e = smlsl v0.4s, v1.4h, v2.4h +0x20,0xa0,0xa2,0x0e = smlsl v0.2d, v1.2s, v2.2s +0x20,0xa0,0x22,0x4e = smlsl2 v0.8h, v1.16b, v2.16b +0x20,0xa0,0x62,0x4e = smlsl2 v0.4s, v1.8h, v2.8h +0x20,0xa0,0xa2,0x4e = smlsl2 v0.2d, v1.4s, v2.4s +0x20,0xa0,0x22,0x2e = umlsl v0.8h, v1.8b, v2.8b +0x20,0xa0,0x62,0x2e = umlsl v0.4s, v1.4h, v2.4h +0x20,0xa0,0xa2,0x2e = umlsl v0.2d, v1.2s, v2.2s +0x20,0xa0,0x22,0x6e = umlsl2 v0.8h, v1.16b, v2.16b +0x20,0xa0,0x62,0x6e = umlsl2 v0.4s, v1.8h, v2.8h +0x20,0xa0,0xa2,0x6e = umlsl2 v0.2d, v1.4s, v2.4s +0x20,0xc0,0x22,0x0e = smull v0.8h, v1.8b, v2.8b +0x20,0xc0,0x62,0x0e = smull v0.4s, v1.4h, v2.4h +0x20,0xc0,0xa2,0x0e = smull v0.2d, v1.2s, v2.2s +0x20,0xc0,0x22,0x4e = smull2 v0.8h, v1.16b, v2.16b +0x20,0xc0,0x62,0x4e = smull2 v0.4s, v1.8h, v2.8h +0x20,0xc0,0xa2,0x4e = smull2 v0.2d, v1.4s, v2.4s +0x20,0xc0,0x22,0x2e = umull v0.8h, v1.8b, v2.8b +0x20,0xc0,0x62,0x2e = umull v0.4s, v1.4h, v2.4h +0x20,0xc0,0xa2,0x2e = umull v0.2d, v1.2s, v2.2s +0x20,0xc0,0x22,0x6e = umull2 v0.8h, v1.16b, v2.16b +0x20,0xc0,0x62,0x6e = umull2 v0.4s, v1.8h, v2.8h +0x20,0xc0,0xa2,0x6e = umull2 v0.2d, v1.4s, v2.4s +0x20,0x90,0x62,0x0e = sqdmlal v0.4s, v1.4h, v2.4h +0x20,0x90,0xa2,0x0e = sqdmlal v0.2d, v1.2s, v2.2s +0x20,0x90,0x62,0x4e = sqdmlal2 v0.4s, v1.8h, v2.8h +0x20,0x90,0xa2,0x4e = sqdmlal2 v0.2d, v1.4s, v2.4s +0x20,0xb0,0x62,0x0e = sqdmlsl v0.4s, v1.4h, v2.4h +0x20,0xb0,0xa2,0x0e = sqdmlsl v0.2d, v1.2s, v2.2s +0x20,0xb0,0x62,0x4e = sqdmlsl2 v0.4s, v1.8h, v2.8h +0x20,0xb0,0xa2,0x4e = sqdmlsl2 v0.2d, v1.4s, v2.4s +0x20,0xd0,0x62,0x0e = sqdmull v0.4s, v1.4h, v2.4h +0x20,0xd0,0xa2,0x0e = sqdmull v0.2d, v1.2s, v2.2s +0x20,0xd0,0x62,0x4e = sqdmull2 v0.4s, v1.8h, v2.8h +0x20,0xd0,0xa2,0x4e = sqdmull2 v0.2d, v1.4s, v2.4s +0x20,0xe0,0x22,0x0e = pmull v0.8h, v1.8b, v2.8b +0x20,0xe0,0xe2,0x0e = pmull v0.1q, v1.1d, v2.1d +0x20,0xe0,0x22,0x4e = pmull2 v0.8h, v1.16b, v2.16b +0x20,0xe0,0xe2,0x4e = pmull2 v0.1q, v1.2d, v2.2d +0x20,0x10,0x22,0x0e = saddw v0.8h, v1.8h, v2.8b +0x20,0x10,0x62,0x0e = saddw v0.4s, v1.4s, v2.4h +0x20,0x10,0xa2,0x0e = saddw v0.2d, v1.2d, v2.2s +0x20,0x10,0x22,0x4e = saddw2 v0.8h, v1.8h, v2.16b +0x20,0x10,0x62,0x4e = saddw2 v0.4s, v1.4s, v2.8h +0x20,0x10,0xa2,0x4e = saddw2 v0.2d, v1.2d, v2.4s +0x20,0x10,0x22,0x2e = uaddw v0.8h, v1.8h, v2.8b +0x20,0x10,0x62,0x2e = uaddw v0.4s, v1.4s, v2.4h +0x20,0x10,0xa2,0x2e = uaddw v0.2d, v1.2d, v2.2s +0x20,0x10,0x22,0x6e = uaddw2 v0.8h, v1.8h, v2.16b +0x20,0x10,0x62,0x6e = uaddw2 v0.4s, v1.4s, v2.8h +0x20,0x10,0xa2,0x6e = uaddw2 v0.2d, v1.2d, v2.4s +0x20,0x30,0x22,0x0e = ssubw v0.8h, v1.8h, v2.8b +0x20,0x30,0x62,0x0e = ssubw v0.4s, v1.4s, v2.4h +0x20,0x30,0xa2,0x0e = ssubw v0.2d, v1.2d, v2.2s +0x20,0x30,0x22,0x4e = ssubw2 v0.8h, v1.8h, v2.16b +0x20,0x30,0x62,0x4e = ssubw2 v0.4s, v1.4s, v2.8h +0x20,0x30,0xa2,0x4e = ssubw2 v0.2d, v1.2d, v2.4s +0x20,0x30,0x22,0x2e = usubw v0.8h, v1.8h, v2.8b +0x20,0x30,0x62,0x2e = usubw v0.4s, v1.4s, v2.4h +0x20,0x30,0xa2,0x2e = usubw v0.2d, v1.2d, v2.2s +0x20,0x30,0x22,0x6e = usubw2 v0.8h, v1.8h, v2.16b +0x20,0x30,0x62,0x6e = usubw2 v0.4s, v1.4s, v2.8h +0x20,0x30,0xa2,0x6e = usubw2 v0.2d, v1.2d, v2.4s +0x20,0x40,0x22,0x0e = addhn v0.8b, v1.8h, v2.8h +0x20,0x40,0x62,0x0e = addhn v0.4h, v1.4s, v2.4s +0x20,0x40,0xa2,0x0e = addhn v0.2s, v1.2d, v2.2d +0x20,0x40,0x22,0x4e = addhn2 v0.16b, v1.8h, v2.8h +0x20,0x40,0x62,0x4e = addhn2 v0.8h, v1.4s, v2.4s +0x20,0x40,0xa2,0x4e = addhn2 v0.4s, v1.2d, v2.2d +0x20,0x40,0x22,0x2e = raddhn v0.8b, v1.8h, v2.8h +0x20,0x40,0x62,0x2e = raddhn v0.4h, v1.4s, v2.4s +0x20,0x40,0xa2,0x2e = raddhn v0.2s, v1.2d, v2.2d +0x20,0x40,0x22,0x6e = raddhn2 v0.16b, v1.8h, v2.8h +0x20,0x40,0x62,0x6e = raddhn2 v0.8h, v1.4s, v2.4s +0x20,0x40,0xa2,0x6e = raddhn2 v0.4s, v1.2d, v2.2d +0x20,0x60,0x22,0x2e = rsubhn v0.8b, v1.8h, v2.8h +0x20,0x60,0x62,0x2e = rsubhn v0.4h, v1.4s, v2.4s +0x20,0x60,0xa2,0x2e = rsubhn v0.2s, v1.2d, v2.2d +0x20,0x60,0x22,0x6e = rsubhn2 v0.16b, v1.8h, v2.8h +0x20,0x60,0x62,0x6e = rsubhn2 v0.8h, v1.4s, v2.4s +0x20,0x60,0xa2,0x6e = rsubhn2 v0.4s, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-aba-abd.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-aba-abd.s.cs new file mode 100644 index 0000000..820e65f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-aba-abd.s.cs @@ -0,0 +1,28 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x7c,0x22,0x2e = uaba v0.8b, v1.8b, v2.8b +0x20,0x7c,0x22,0x6e = uaba v0.16b, v1.16b, v2.16b +0x20,0x7c,0x62,0x2e = uaba v0.4h, v1.4h, v2.4h +0x20,0x7c,0x62,0x6e = uaba v0.8h, v1.8h, v2.8h +0x20,0x7c,0xa2,0x2e = uaba v0.2s, v1.2s, v2.2s +0x20,0x7c,0xa2,0x6e = uaba v0.4s, v1.4s, v2.4s +0x20,0x7c,0x22,0x0e = saba v0.8b, v1.8b, v2.8b +0x20,0x7c,0x22,0x4e = saba v0.16b, v1.16b, v2.16b +0x20,0x7c,0x62,0x0e = saba v0.4h, v1.4h, v2.4h +0x20,0x7c,0x62,0x4e = saba v0.8h, v1.8h, v2.8h +0x20,0x7c,0xa2,0x0e = saba v0.2s, v1.2s, v2.2s +0x20,0x7c,0xa2,0x4e = saba v0.4s, v1.4s, v2.4s +0x20,0x74,0x22,0x2e = uabd v0.8b, v1.8b, v2.8b +0x20,0x74,0x22,0x6e = uabd v0.16b, v1.16b, v2.16b +0x20,0x74,0x62,0x2e = uabd v0.4h, v1.4h, v2.4h +0x20,0x74,0x62,0x6e = uabd v0.8h, v1.8h, v2.8h +0x20,0x74,0xa2,0x2e = uabd v0.2s, v1.2s, v2.2s +0x20,0x74,0xa2,0x6e = uabd v0.4s, v1.4s, v2.4s +0x20,0x74,0x22,0x0e = sabd v0.8b, v1.8b, v2.8b +0x20,0x74,0x22,0x4e = sabd v0.16b, v1.16b, v2.16b +0x20,0x74,0x62,0x0e = sabd v0.4h, v1.4h, v2.4h +0x20,0x74,0x62,0x4e = sabd v0.8h, v1.8h, v2.8h +0x20,0x74,0xa2,0x0e = sabd v0.2s, v1.2s, v2.2s +0x20,0x74,0xa2,0x4e = sabd v0.4s, v1.4s, v2.4s +0x20,0xd4,0xa2,0x2e = fabd v0.2s, v1.2s, v2.2s +0xff,0xd5,0xb0,0x6e = fabd v31.4s, v15.4s, v16.4s +0x07,0xd5,0xf9,0x6e = fabd v7.2d, v8.2d, v25.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-across.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-across.s.cs new file mode 100644 index 0000000..a735516 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-across.s.cs @@ -0,0 +1,40 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x38,0x30,0x0e = saddlv h0, v1.8b +0x20,0x38,0x30,0x4e = saddlv h0, v1.16b +0x20,0x38,0x70,0x0e = saddlv s0, v1.4h +0x20,0x38,0x70,0x4e = saddlv s0, v1.8h +0x20,0x38,0xb0,0x4e = saddlv d0, v1.4s +0x20,0x38,0x30,0x2e = uaddlv h0, v1.8b +0x20,0x38,0x30,0x6e = uaddlv h0, v1.16b +0x20,0x38,0x70,0x2e = uaddlv s0, v1.4h +0x20,0x38,0x70,0x6e = uaddlv s0, v1.8h +0x20,0x38,0xb0,0x6e = uaddlv d0, v1.4s +0x20,0xa8,0x30,0x0e = smaxv b0, v1.8b +0x20,0xa8,0x30,0x4e = smaxv b0, v1.16b +0x20,0xa8,0x70,0x0e = smaxv h0, v1.4h +0x20,0xa8,0x70,0x4e = smaxv h0, v1.8h +0x20,0xa8,0xb0,0x4e = smaxv s0, v1.4s +0x20,0xa8,0x31,0x0e = sminv b0, v1.8b +0x20,0xa8,0x31,0x4e = sminv b0, v1.16b +0x20,0xa8,0x71,0x0e = sminv h0, v1.4h +0x20,0xa8,0x71,0x4e = sminv h0, v1.8h +0x20,0xa8,0xb1,0x4e = sminv s0, v1.4s +0x20,0xa8,0x30,0x2e = umaxv b0, v1.8b +0x20,0xa8,0x30,0x6e = umaxv b0, v1.16b +0x20,0xa8,0x70,0x2e = umaxv h0, v1.4h +0x20,0xa8,0x70,0x6e = umaxv h0, v1.8h +0x20,0xa8,0xb0,0x6e = umaxv s0, v1.4s +0x20,0xa8,0x31,0x2e = uminv b0, v1.8b +0x20,0xa8,0x31,0x6e = uminv b0, v1.16b +0x20,0xa8,0x71,0x2e = uminv h0, v1.4h +0x20,0xa8,0x71,0x6e = uminv h0, v1.8h +0x20,0xa8,0xb1,0x6e = uminv s0, v1.4s +0x20,0xb8,0x31,0x0e = addv b0, v1.8b +0x20,0xb8,0x31,0x4e = addv b0, v1.16b +0x20,0xb8,0x71,0x0e = addv h0, v1.4h +0x20,0xb8,0x71,0x4e = addv h0, v1.8h +0x20,0xb8,0xb1,0x4e = addv s0, v1.4s +0x20,0xc8,0x30,0x6e = fmaxnmv s0, v1.4s +0x20,0xc8,0xb0,0x6e = fminnmv s0, v1.4s +0x20,0xf8,0x30,0x6e = fmaxv s0, v1.4s +0x20,0xf8,0xb0,0x6e = fminv s0, v1.4s diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-pairwise.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-pairwise.s.cs new file mode 100644 index 0000000..02aaa5b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-pairwise.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_ARM64, 0, None +0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b +0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b +0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h +0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h +0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s +0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s +0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d +0x20,0xd4,0x22,0x2e = faddp v0.2s, v1.2s, v2.2s +0x20,0xd4,0x22,0x6e = faddp v0.4s, v1.4s, v2.4s +0x20,0xd4,0x62,0x6e = faddp v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-sub-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-sub-instructions.s.cs new file mode 100644 index 0000000..2257c6e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-add-sub-instructions.s.cs @@ -0,0 +1,21 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x84,0x22,0x0e = add v0.8b, v1.8b, v2.8b +0x20,0x84,0x22,0x4e = add v0.16b, v1.16b, v2.16b +0x20,0x84,0x62,0x0e = add v0.4h, v1.4h, v2.4h +0x20,0x84,0x62,0x4e = add v0.8h, v1.8h, v2.8h +0x20,0x84,0xa2,0x0e = add v0.2s, v1.2s, v2.2s +0x20,0x84,0xa2,0x4e = add v0.4s, v1.4s, v2.4s +0x20,0x84,0xe2,0x4e = add v0.2d, v1.2d, v2.2d +0x20,0x84,0x22,0x2e = sub v0.8b, v1.8b, v2.8b +0x20,0x84,0x22,0x6e = sub v0.16b, v1.16b, v2.16b +0x20,0x84,0x62,0x2e = sub v0.4h, v1.4h, v2.4h +0x20,0x84,0x62,0x6e = sub v0.8h, v1.8h, v2.8h +0x20,0x84,0xa2,0x2e = sub v0.2s, v1.2s, v2.2s +0x20,0x84,0xa2,0x6e = sub v0.4s, v1.4s, v2.4s +0x20,0x84,0xe2,0x6e = sub v0.2d, v1.2d, v2.2d +0x20,0xd4,0x22,0x0e = fadd v0.2s, v1.2s, v2.2s +0x20,0xd4,0x22,0x4e = fadd v0.4s, v1.4s, v2.4s +0x20,0xd4,0x62,0x4e = fadd v0.2d, v1.2d, v2.2d +0x20,0xd4,0xa2,0x0e = fsub v0.2s, v1.2s, v2.2s +0x20,0xd4,0xa2,0x4e = fsub v0.4s, v1.4s, v2.4s +0x20,0xd4,0xe2,0x4e = fsub v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-bitwise-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-bitwise-instructions.s.cs new file mode 100644 index 0000000..7191ee2 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-bitwise-instructions.s.cs @@ -0,0 +1,17 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x1c,0x22,0x0e = and v0.8b, v1.8b, v2.8b +0x20,0x1c,0x22,0x4e = and v0.16b, v1.16b, v2.16b +0x20,0x1c,0xa2,0x0e = orr v0.8b, v1.8b, v2.8b +0x20,0x1c,0xa2,0x4e = orr v0.16b, v1.16b, v2.16b +0x20,0x1c,0x22,0x2e = eor v0.8b, v1.8b, v2.8b +0x20,0x1c,0x22,0x6e = eor v0.16b, v1.16b, v2.16b +0x20,0x1c,0xa2,0x2e = bit v0.8b, v1.8b, v2.8b +0x20,0x1c,0xa2,0x6e = bit v0.16b, v1.16b, v2.16b +0x20,0x1c,0xe2,0x2e = bif v0.8b, v1.8b, v2.8b +0x20,0x1c,0xe2,0x6e = bif v0.16b, v1.16b, v2.16b +0x20,0x1c,0x62,0x2e = bsl v0.8b, v1.8b, v2.8b +0x20,0x1c,0x62,0x6e = bsl v0.16b, v1.16b, v2.16b +0x20,0x1c,0xe2,0x0e = orn v0.8b, v1.8b, v2.8b +0x20,0x1c,0xe2,0x4e = orn v0.16b, v1.16b, v2.16b +0x20,0x1c,0x62,0x0e = bic v0.8b, v1.8b, v2.8b +0x20,0x1c,0x62,0x4e = bic v0.16b, v1.16b, v2.16b diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-compare-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-compare-instructions.s.cs new file mode 100644 index 0000000..2a3c749 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-compare-instructions.s.cs @@ -0,0 +1,136 @@ +# CS_ARCH_ARM64, 0, None +0xe0,0x8d,0x31,0x2e = cmeq v0.8b, v15.8b, v17.8b +0xe1,0x8f,0x28,0x6e = cmeq v1.16b, v31.16b, v8.16b +0x0f,0x8e,0x71,0x2e = cmeq v15.4h, v16.4h, v17.4h +0xc5,0x8c,0x67,0x6e = cmeq v5.8h, v6.8h, v7.8h +0x7d,0x8f,0xbc,0x2e = cmeq v29.2s, v27.2s, v28.2s +0xe9,0x8c,0xa8,0x6e = cmeq v9.4s, v7.4s, v8.4s +0xe3,0x8f,0xf5,0x6e = cmeq v3.2d, v31.2d, v21.2d +0xe0,0x3d,0x31,0x2e = cmhs v0.8b, v15.8b, v17.8b +0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b +0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h +0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h +0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s +0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s +0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d +0xe0,0x3d,0x31,0x2e = cmhs v0.8b, v15.8b, v17.8b +0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b +0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h +0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h +0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s +0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s +0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d +0xe0,0x3d,0x31,0x0e = cmge v0.8b, v15.8b, v17.8b +0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b +0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h +0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h +0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s +0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s +0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d +0xe0,0x3d,0x31,0x0e = cmge v0.8b, v15.8b, v17.8b +0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b +0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h +0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h +0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s +0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s +0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d +0xe0,0x35,0x31,0x2e = cmhi v0.8b, v15.8b, v17.8b +0xe1,0x37,0x28,0x6e = cmhi v1.16b, v31.16b, v8.16b +0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h +0xc5,0x34,0x67,0x6e = cmhi v5.8h, v6.8h, v7.8h +0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s +0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s +0xe3,0x37,0xf5,0x6e = cmhi v3.2d, v31.2d, v21.2d +0xe0,0x35,0x31,0x2e = cmhi v0.8b, v15.8b, v17.8b +0xe1,0x37,0x28,0x6e = cmhi v1.16b, v31.16b, v8.16b +0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h +0xc5,0x34,0x67,0x6e = cmhi v5.8h, v6.8h, v7.8h +0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s +0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s +0xe3,0x37,0xf5,0x6e = cmhi v3.2d, v31.2d, v21.2d +0xe0,0x35,0x31,0x0e = cmgt v0.8b, v15.8b, v17.8b +0xe1,0x37,0x28,0x4e = cmgt v1.16b, v31.16b, v8.16b +0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h +0xc5,0x34,0x67,0x4e = cmgt v5.8h, v6.8h, v7.8h +0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s +0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s +0xe3,0x37,0xf5,0x4e = cmgt v3.2d, v31.2d, v21.2d +0xe0,0x35,0x31,0x0e = cmgt v0.8b, v15.8b, v17.8b +0xe1,0x37,0x28,0x4e = cmgt v1.16b, v31.16b, v8.16b +0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h +0xc5,0x34,0x67,0x4e = cmgt v5.8h, v6.8h, v7.8h +0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s +0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s +0xe3,0x37,0xf5,0x4e = cmgt v3.2d, v31.2d, v21.2d +0xe0,0x8d,0x31,0x0e = cmtst v0.8b, v15.8b, v17.8b +0xe1,0x8f,0x28,0x4e = cmtst v1.16b, v31.16b, v8.16b +0x0f,0x8e,0x71,0x0e = cmtst v15.4h, v16.4h, v17.4h +0xc5,0x8c,0x67,0x4e = cmtst v5.8h, v6.8h, v7.8h +0x7d,0x8f,0xbc,0x0e = cmtst v29.2s, v27.2s, v28.2s +0xe9,0x8c,0xa8,0x4e = cmtst v9.4s, v7.4s, v8.4s +0xe3,0x8f,0xf5,0x4e = cmtst v3.2d, v31.2d, v21.2d +0xe0,0xe7,0x30,0x0e = fcmeq v0.2s, v31.2s, v16.2s +0xe4,0xe4,0x2f,0x4e = fcmeq v4.4s, v7.4s, v15.4s +0x5d,0xe4,0x65,0x4e = fcmeq v29.2d, v2.2d, v5.2d +0xbf,0xe7,0x3c,0x6e = fcmge v31.4s, v29.4s, v28.4s +0x03,0xe5,0x2c,0x2e = fcmge v3.2s, v8.2s, v12.2s +0xf1,0xe5,0x6d,0x6e = fcmge v17.2d, v15.2d, v13.2d +0xbf,0xe7,0x3c,0x6e = fcmge v31.4s, v29.4s, v28.4s +0x03,0xe5,0x2c,0x2e = fcmge v3.2s, v8.2s, v12.2s +0xf1,0xe5,0x6d,0x6e = fcmge v17.2d, v15.2d, v13.2d +0xe0,0xe7,0xb0,0x2e = fcmgt v0.2s, v31.2s, v16.2s +0xe4,0xe4,0xaf,0x6e = fcmgt v4.4s, v7.4s, v15.4s +0x5d,0xe4,0xe5,0x6e = fcmgt v29.2d, v2.2d, v5.2d +0xe0,0xe7,0xb0,0x2e = fcmgt v0.2s, v31.2s, v16.2s +0xe4,0xe4,0xaf,0x6e = fcmgt v4.4s, v7.4s, v15.4s +0x5d,0xe4,0xe5,0x6e = fcmgt v29.2d, v2.2d, v5.2d +0xe0,0x99,0x20,0x0e = cmeq v0.8b, v15.8b, #0x0 +0xe1,0x9b,0x20,0x4e = cmeq v1.16b, v31.16b, #0x0 +0x0f,0x9a,0x60,0x0e = cmeq v15.4h, v16.4h, #0x0 +0xc5,0x98,0x60,0x4e = cmeq v5.8h, v6.8h, #0x0 +0x7d,0x9b,0xa0,0x0e = cmeq v29.2s, v27.2s, #0x0 +0xe9,0x98,0xa0,0x4e = cmeq v9.4s, v7.4s, #0x0 +0xe3,0x9b,0xe0,0x4e = cmeq v3.2d, v31.2d, #0x0 +0xe0,0x89,0x20,0x2e = cmge v0.8b, v15.8b, #0x0 +0xe1,0x8b,0x20,0x6e = cmge v1.16b, v31.16b, #0x0 +0x0f,0x8a,0x60,0x2e = cmge v15.4h, v16.4h, #0x0 +0xc5,0x88,0x60,0x6e = cmge v5.8h, v6.8h, #0x0 +0x7d,0x8b,0xa0,0x2e = cmge v29.2s, v27.2s, #0x0 +0x91,0x8a,0xa0,0x6e = cmge v17.4s, v20.4s, #0x0 +0xe3,0x8b,0xe0,0x6e = cmge v3.2d, v31.2d, #0x0 +0xe0,0x89,0x20,0x0e = cmgt v0.8b, v15.8b, #0x0 +0xe1,0x8b,0x20,0x4e = cmgt v1.16b, v31.16b, #0x0 +0x0f,0x8a,0x60,0x0e = cmgt v15.4h, v16.4h, #0x0 +0xc5,0x88,0x60,0x4e = cmgt v5.8h, v6.8h, #0x0 +0x7d,0x8b,0xa0,0x0e = cmgt v29.2s, v27.2s, #0x0 +0xe9,0x88,0xa0,0x4e = cmgt v9.4s, v7.4s, #0x0 +0xe3,0x8b,0xe0,0x4e = cmgt v3.2d, v31.2d, #0x0 +0xe0,0x99,0x20,0x2e = cmle v0.8b, v15.8b, #0x0 +0xe1,0x9b,0x20,0x6e = cmle v1.16b, v31.16b, #0x0 +0x0f,0x9a,0x60,0x2e = cmle v15.4h, v16.4h, #0x0 +0xc5,0x98,0x60,0x6e = cmle v5.8h, v6.8h, #0x0 +0x7d,0x9b,0xa0,0x2e = cmle v29.2s, v27.2s, #0x0 +0xe9,0x98,0xa0,0x6e = cmle v9.4s, v7.4s, #0x0 +0xe3,0x9b,0xe0,0x6e = cmle v3.2d, v31.2d, #0x0 +0xe0,0xa9,0x20,0x0e = cmlt v0.8b, v15.8b, #0x0 +0xe1,0xab,0x20,0x4e = cmlt v1.16b, v31.16b, #0x0 +0x0f,0xaa,0x60,0x0e = cmlt v15.4h, v16.4h, #0x0 +0xc5,0xa8,0x60,0x4e = cmlt v5.8h, v6.8h, #0x0 +0x7d,0xab,0xa0,0x0e = cmlt v29.2s, v27.2s, #0x0 +0xe9,0xa8,0xa0,0x4e = cmlt v9.4s, v7.4s, #0x0 +0xe3,0xab,0xe0,0x4e = cmlt v3.2d, v31.2d, #0x0 +0xe0,0xdb,0xa0,0x0e = fcmeq v0.2s, v31.2s, #0.0 +0xe4,0xd8,0xa0,0x4e = fcmeq v4.4s, v7.4s, #0.0 +0x5d,0xd8,0xe0,0x4e = fcmeq v29.2d, v2.2d, #0.0 +0xbf,0xcb,0xa0,0x6e = fcmge v31.4s, v29.4s, #0.0 +0x03,0xc9,0xa0,0x2e = fcmge v3.2s, v8.2s, #0.0 +0xf1,0xc9,0xe0,0x6e = fcmge v17.2d, v15.2d, #0.0 +0xe0,0xcb,0xa0,0x0e = fcmgt v0.2s, v31.2s, #0.0 +0xe4,0xc8,0xa0,0x4e = fcmgt v4.4s, v7.4s, #0.0 +0x5d,0xc8,0xe0,0x4e = fcmgt v29.2d, v2.2d, #0.0 +0x01,0xd9,0xa0,0x6e = fcmle v1.4s, v8.4s, #0.0 +0x83,0xda,0xa0,0x2e = fcmle v3.2s, v20.2s, #0.0 +0xa7,0xd9,0xe0,0x6e = fcmle v7.2d, v13.2d, #0.0 +0x50,0xe8,0xa0,0x0e = fcmlt v16.2s, v2.2s, #0.0 +0x8f,0xe8,0xa0,0x4e = fcmlt v15.4s, v4.4s, #0.0 +0xa5,0xeb,0xe0,0x4e = fcmlt v5.2d, v29.2d, #0.0 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-crypto.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-crypto.s.cs new file mode 100644 index 0000000..491c885 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-crypto.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b +0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b +0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b +0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b +0x20,0x08,0x28,0x5e = sha1h s0, s1 +0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s +0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s +0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s +0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s +0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s +0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s +0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s +0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s +0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-extract.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-extract.s.cs new file mode 100644 index 0000000..64be78a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-extract.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x18,0x02,0x2e = ext v0.8b, v1.8b, v2.8b, #0x3 +0x20,0x18,0x02,0x6e = ext v0.16b, v1.16b, v2.16b, #0x3 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-facge-facgt.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-facge-facgt.s.cs new file mode 100644 index 0000000..c24b29b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-facge-facgt.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s +0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s +0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d +0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s +0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s +0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d +0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s +0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s +0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d +0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s +0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s +0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-frsqrt-frecp.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-frsqrt-frecp.s.cs new file mode 100644 index 0000000..17f3b56 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-frsqrt-frecp.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_ARM64, 0, None +0xe0,0xff,0xb0,0x0e = frsqrts v0.2s, v31.2s, v16.2s +0xe4,0xfc,0xaf,0x4e = frsqrts v4.4s, v7.4s, v15.4s +0x5d,0xfc,0xe5,0x4e = frsqrts v29.2d, v2.2d, v5.2d +0xbf,0xff,0x3c,0x4e = frecps v31.4s, v29.4s, v28.4s +0x03,0xfd,0x2c,0x0e = frecps v3.2s, v8.2s, v12.2s +0xf1,0xfd,0x6d,0x4e = frecps v17.2d, v15.2d, v13.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-halving-add-sub.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-halving-add-sub.s.cs new file mode 100644 index 0000000..df3eed8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-halving-add-sub.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x04,0x22,0x0e = shadd v0.8b, v1.8b, v2.8b +0x20,0x04,0x22,0x4e = shadd v0.16b, v1.16b, v2.16b +0x20,0x04,0x62,0x0e = shadd v0.4h, v1.4h, v2.4h +0x20,0x04,0x62,0x4e = shadd v0.8h, v1.8h, v2.8h +0x20,0x04,0xa2,0x0e = shadd v0.2s, v1.2s, v2.2s +0x20,0x04,0xa2,0x4e = shadd v0.4s, v1.4s, v2.4s +0x20,0x04,0x22,0x2e = uhadd v0.8b, v1.8b, v2.8b +0x20,0x04,0x22,0x6e = uhadd v0.16b, v1.16b, v2.16b +0x20,0x04,0x62,0x2e = uhadd v0.4h, v1.4h, v2.4h +0x20,0x04,0x62,0x6e = uhadd v0.8h, v1.8h, v2.8h +0x20,0x04,0xa2,0x2e = uhadd v0.2s, v1.2s, v2.2s +0x20,0x04,0xa2,0x6e = uhadd v0.4s, v1.4s, v2.4s +0x20,0x24,0x22,0x0e = shsub v0.8b, v1.8b, v2.8b +0x20,0x24,0x22,0x4e = shsub v0.16b, v1.16b, v2.16b +0x20,0x24,0x62,0x0e = shsub v0.4h, v1.4h, v2.4h +0x20,0x24,0x62,0x4e = shsub v0.8h, v1.8h, v2.8h +0x20,0x24,0xa2,0x0e = shsub v0.2s, v1.2s, v2.2s +0x20,0x24,0xa2,0x4e = shsub v0.4s, v1.4s, v2.4s +0x20,0x24,0x22,0x2e = uhsub v0.8b, v1.8b, v2.8b +0x20,0x24,0x22,0x6e = uhsub v0.16b, v1.16b, v2.16b +0x20,0x24,0x62,0x2e = uhsub v0.4h, v1.4h, v2.4h +0x20,0x24,0x62,0x6e = uhsub v0.8h, v1.8h, v2.8h +0x20,0x24,0xa2,0x2e = uhsub v0.2s, v1.2s, v2.2s +0x20,0x24,0xa2,0x6e = uhsub v0.4s, v1.4s, v2.4s diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min-pairwise.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min-pairwise.s.cs new file mode 100644 index 0000000..592a4cc --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min-pairwise.s.cs @@ -0,0 +1,37 @@ +# CS_ARCH_ARM64, 0, None +0x20,0xa4,0x22,0x0e = smaxp v0.8b, v1.8b, v2.8b +0x20,0xa4,0x22,0x4e = smaxp v0.16b, v1.16b, v2.16b +0x20,0xa4,0x62,0x0e = smaxp v0.4h, v1.4h, v2.4h +0x20,0xa4,0x62,0x4e = smaxp v0.8h, v1.8h, v2.8h +0x20,0xa4,0xa2,0x0e = smaxp v0.2s, v1.2s, v2.2s +0x20,0xa4,0xa2,0x4e = smaxp v0.4s, v1.4s, v2.4s +0x20,0xa4,0x22,0x2e = umaxp v0.8b, v1.8b, v2.8b +0x20,0xa4,0x22,0x6e = umaxp v0.16b, v1.16b, v2.16b +0x20,0xa4,0x62,0x2e = umaxp v0.4h, v1.4h, v2.4h +0x20,0xa4,0x62,0x6e = umaxp v0.8h, v1.8h, v2.8h +0x20,0xa4,0xa2,0x2e = umaxp v0.2s, v1.2s, v2.2s +0x20,0xa4,0xa2,0x6e = umaxp v0.4s, v1.4s, v2.4s +0x20,0xac,0x22,0x0e = sminp v0.8b, v1.8b, v2.8b +0x20,0xac,0x22,0x4e = sminp v0.16b, v1.16b, v2.16b +0x20,0xac,0x62,0x0e = sminp v0.4h, v1.4h, v2.4h +0x20,0xac,0x62,0x4e = sminp v0.8h, v1.8h, v2.8h +0x20,0xac,0xa2,0x0e = sminp v0.2s, v1.2s, v2.2s +0x20,0xac,0xa2,0x4e = sminp v0.4s, v1.4s, v2.4s +0x20,0xac,0x22,0x2e = uminp v0.8b, v1.8b, v2.8b +0x20,0xac,0x22,0x6e = uminp v0.16b, v1.16b, v2.16b +0x20,0xac,0x62,0x2e = uminp v0.4h, v1.4h, v2.4h +0x20,0xac,0x62,0x6e = uminp v0.8h, v1.8h, v2.8h +0x20,0xac,0xa2,0x2e = uminp v0.2s, v1.2s, v2.2s +0x20,0xac,0xa2,0x6e = uminp v0.4s, v1.4s, v2.4s +0x20,0xf4,0x22,0x2e = fmaxp v0.2s, v1.2s, v2.2s +0xff,0xf5,0x30,0x6e = fmaxp v31.4s, v15.4s, v16.4s +0x07,0xf5,0x79,0x6e = fmaxp v7.2d, v8.2d, v25.2d +0xea,0xf5,0xb6,0x2e = fminp v10.2s, v15.2s, v22.2s +0xa3,0xf4,0xa6,0x6e = fminp v3.4s, v5.4s, v6.4s +0xb1,0xf5,0xe2,0x6e = fminp v17.2d, v13.2d, v2.2d +0x20,0xc4,0x22,0x2e = fmaxnmp v0.2s, v1.2s, v2.2s +0xff,0xc5,0x30,0x6e = fmaxnmp v31.4s, v15.4s, v16.4s +0x07,0xc5,0x79,0x6e = fmaxnmp v7.2d, v8.2d, v25.2d +0xea,0xc5,0xb6,0x2e = fminnmp v10.2s, v15.2s, v22.2s +0xa3,0xc4,0xa6,0x6e = fminnmp v3.4s, v5.4s, v6.4s +0xb1,0xc5,0xe2,0x6e = fminnmp v17.2d, v13.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min.s.cs new file mode 100644 index 0000000..6b58bca --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-max-min.s.cs @@ -0,0 +1,37 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x64,0x22,0x0e = smax v0.8b, v1.8b, v2.8b +0x20,0x64,0x22,0x4e = smax v0.16b, v1.16b, v2.16b +0x20,0x64,0x62,0x0e = smax v0.4h, v1.4h, v2.4h +0x20,0x64,0x62,0x4e = smax v0.8h, v1.8h, v2.8h +0x20,0x64,0xa2,0x0e = smax v0.2s, v1.2s, v2.2s +0x20,0x64,0xa2,0x4e = smax v0.4s, v1.4s, v2.4s +0x20,0x64,0x22,0x2e = umax v0.8b, v1.8b, v2.8b +0x20,0x64,0x22,0x6e = umax v0.16b, v1.16b, v2.16b +0x20,0x64,0x62,0x2e = umax v0.4h, v1.4h, v2.4h +0x20,0x64,0x62,0x6e = umax v0.8h, v1.8h, v2.8h +0x20,0x64,0xa2,0x2e = umax v0.2s, v1.2s, v2.2s +0x20,0x64,0xa2,0x6e = umax v0.4s, v1.4s, v2.4s +0x20,0x6c,0x22,0x0e = smin v0.8b, v1.8b, v2.8b +0x20,0x6c,0x22,0x4e = smin v0.16b, v1.16b, v2.16b +0x20,0x6c,0x62,0x0e = smin v0.4h, v1.4h, v2.4h +0x20,0x6c,0x62,0x4e = smin v0.8h, v1.8h, v2.8h +0x20,0x6c,0xa2,0x0e = smin v0.2s, v1.2s, v2.2s +0x20,0x6c,0xa2,0x4e = smin v0.4s, v1.4s, v2.4s +0x20,0x6c,0x22,0x2e = umin v0.8b, v1.8b, v2.8b +0x20,0x6c,0x22,0x6e = umin v0.16b, v1.16b, v2.16b +0x20,0x6c,0x62,0x2e = umin v0.4h, v1.4h, v2.4h +0x20,0x6c,0x62,0x6e = umin v0.8h, v1.8h, v2.8h +0x20,0x6c,0xa2,0x2e = umin v0.2s, v1.2s, v2.2s +0x20,0x6c,0xa2,0x6e = umin v0.4s, v1.4s, v2.4s +0x20,0xf4,0x22,0x0e = fmax v0.2s, v1.2s, v2.2s +0xff,0xf5,0x30,0x4e = fmax v31.4s, v15.4s, v16.4s +0x07,0xf5,0x79,0x4e = fmax v7.2d, v8.2d, v25.2d +0xea,0xf5,0xb6,0x0e = fmin v10.2s, v15.2s, v22.2s +0xa3,0xf4,0xa6,0x4e = fmin v3.4s, v5.4s, v6.4s +0xb1,0xf5,0xe2,0x4e = fmin v17.2d, v13.2d, v2.2d +0x20,0xc4,0x22,0x0e = fmaxnm v0.2s, v1.2s, v2.2s +0xff,0xc5,0x30,0x4e = fmaxnm v31.4s, v15.4s, v16.4s +0x07,0xc5,0x79,0x4e = fmaxnm v7.2d, v8.2d, v25.2d +0xea,0xc5,0xb6,0x0e = fminnm v10.2s, v15.2s, v22.2s +0xa3,0xc4,0xa6,0x4e = fminnm v3.4s, v5.4s, v6.4s +0xb1,0xc5,0xe2,0x4e = fminnm v17.2d, v13.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mla-mls-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mla-mls-instructions.s.cs new file mode 100644 index 0000000..a9b3f39 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mla-mls-instructions.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x94,0x22,0x0e = mla v0.8b, v1.8b, v2.8b +0x20,0x94,0x22,0x4e = mla v0.16b, v1.16b, v2.16b +0x20,0x94,0x62,0x0e = mla v0.4h, v1.4h, v2.4h +0x20,0x94,0x62,0x4e = mla v0.8h, v1.8h, v2.8h +0x20,0x94,0xa2,0x0e = mla v0.2s, v1.2s, v2.2s +0x20,0x94,0xa2,0x4e = mla v0.4s, v1.4s, v2.4s +0x20,0x94,0x22,0x2e = mls v0.8b, v1.8b, v2.8b +0x20,0x94,0x22,0x6e = mls v0.16b, v1.16b, v2.16b +0x20,0x94,0x62,0x2e = mls v0.4h, v1.4h, v2.4h +0x20,0x94,0x62,0x6e = mls v0.8h, v1.8h, v2.8h +0x20,0x94,0xa2,0x2e = mls v0.2s, v1.2s, v2.2s +0x20,0x94,0xa2,0x6e = mls v0.4s, v1.4s, v2.4s +0x20,0xcc,0x22,0x0e = fmla v0.2s, v1.2s, v2.2s +0x20,0xcc,0x22,0x4e = fmla v0.4s, v1.4s, v2.4s +0x20,0xcc,0x62,0x4e = fmla v0.2d, v1.2d, v2.2d +0x20,0xcc,0xa2,0x0e = fmls v0.2s, v1.2s, v2.2s +0x20,0xcc,0xa2,0x4e = fmls v0.4s, v1.4s, v2.4s +0x20,0xcc,0xe2,0x4e = fmls v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mov.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mov.s.cs new file mode 100644 index 0000000..ef28786 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mov.s.cs @@ -0,0 +1,70 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x04,0x00,0x0f = movi v0.2s, #0x1 +0x01,0x04,0x00,0x0f = movi v1.2s, #0x0 +0x2f,0x24,0x00,0x0f = movi v15.2s, #0x1, lsl #8 +0x30,0x44,0x00,0x0f = movi v16.2s, #0x1, lsl #16 +0x3f,0x64,0x00,0x0f = movi v31.2s, #0x1, lsl #24 +0x20,0x04,0x00,0x4f = movi v0.4s, #0x1 +0x20,0x24,0x00,0x4f = movi v0.4s, #0x1, lsl #8 +0x20,0x44,0x00,0x4f = movi v0.4s, #0x1, lsl #16 +0x20,0x64,0x00,0x4f = movi v0.4s, #0x1, lsl #24 +0x20,0x84,0x00,0x0f = movi v0.4h, #0x1 +0x20,0xa4,0x00,0x0f = movi v0.4h, #0x1, lsl #8 +0x20,0x84,0x00,0x4f = movi v0.8h, #0x1 +0x20,0xa4,0x00,0x4f = movi v0.8h, #0x1, lsl #8 +0x20,0x04,0x00,0x2f = mvni v0.2s, #0x1 +0x01,0x04,0x00,0x2f = mvni v1.2s, #0x0 +0x20,0x24,0x00,0x2f = mvni v0.2s, #0x1, lsl #8 +0x20,0x44,0x00,0x2f = mvni v0.2s, #0x1, lsl #16 +0x20,0x64,0x00,0x2f = mvni v0.2s, #0x1, lsl #24 +0x20,0x04,0x00,0x6f = mvni v0.4s, #0x1 +0x2f,0x24,0x00,0x6f = mvni v15.4s, #0x1, lsl #8 +0x30,0x44,0x00,0x6f = mvni v16.4s, #0x1, lsl #16 +0x3f,0x64,0x00,0x6f = mvni v31.4s, #0x1, lsl #24 +0x20,0x84,0x00,0x2f = mvni v0.4h, #0x1 +0x20,0xa4,0x00,0x2f = mvni v0.4h, #0x1, lsl #8 +0x20,0x84,0x00,0x6f = mvni v0.8h, #0x1 +0x20,0xa4,0x00,0x6f = mvni v0.8h, #0x1, lsl #8 +0x20,0x14,0x00,0x2f = bic v0.2s, #0x1 +0x01,0x14,0x00,0x2f = bic v1.2s, #0x0 +0x20,0x34,0x00,0x2f = bic v0.2s, #0x1, lsl #8 +0x20,0x54,0x00,0x2f = bic v0.2s, #0x1, lsl #16 +0x20,0x74,0x00,0x2f = bic v0.2s, #0x1, lsl #24 +0x20,0x14,0x00,0x6f = bic v0.4s, #0x1 +0x20,0x34,0x00,0x6f = bic v0.4s, #0x1, lsl #8 +0x20,0x54,0x00,0x6f = bic v0.4s, #0x1, lsl #16 +0x20,0x74,0x00,0x6f = bic v0.4s, #0x1, lsl #24 +0x2f,0x94,0x00,0x2f = bic v15.4h, #0x1 +0x30,0xb4,0x00,0x2f = bic v16.4h, #0x1, lsl #8 +0x20,0x94,0x00,0x6f = bic v0.8h, #0x1 +0x3f,0xb4,0x00,0x6f = bic v31.8h, #0x1, lsl #8 +0x20,0x14,0x00,0x0f = orr v0.2s, #0x1 +0x01,0x14,0x00,0x0f = orr v1.2s, #0x0 +0x20,0x34,0x00,0x0f = orr v0.2s, #0x1, lsl #8 +0x20,0x54,0x00,0x0f = orr v0.2s, #0x1, lsl #16 +0x20,0x74,0x00,0x0f = orr v0.2s, #0x1, lsl #24 +0x20,0x14,0x00,0x4f = orr v0.4s, #0x1 +0x20,0x34,0x00,0x4f = orr v0.4s, #0x1, lsl #8 +0x20,0x54,0x00,0x4f = orr v0.4s, #0x1, lsl #16 +0x20,0x74,0x00,0x4f = orr v0.4s, #0x1, lsl #24 +0x3f,0x94,0x00,0x0f = orr v31.4h, #0x1 +0x2f,0xb4,0x00,0x0f = orr v15.4h, #0x1, lsl #8 +0x20,0x94,0x00,0x4f = orr v0.8h, #0x1 +0x30,0xb4,0x00,0x4f = orr v16.8h, #0x1, lsl #8 +0x20,0xc4,0x00,0x0f = movi v0.2s, #0x1, msl #8 +0x21,0xd4,0x00,0x0f = movi v1.2s, #0x1, msl #16 +0x20,0xc4,0x00,0x4f = movi v0.4s, #0x1, msl #8 +0x3f,0xd4,0x00,0x4f = movi v31.4s, #0x1, msl #16 +0x21,0xc4,0x00,0x2f = mvni v1.2s, #0x1, msl #8 +0x20,0xd4,0x00,0x2f = mvni v0.2s, #0x1, msl #16 +0x3f,0xc4,0x00,0x6f = mvni v31.4s, #0x1, msl #8 +0x20,0xd4,0x00,0x6f = mvni v0.4s, #0x1, msl #16 +0x00,0xe4,0x00,0x0f = movi v0.8b, #0x0 +0xff,0xe7,0x07,0x0f = movi v31.8b, #0xff +0xef,0xe5,0x00,0x4f = movi v15.16b, #0xf +0xff,0xe7,0x00,0x4f = movi v31.16b, #0x1f +0x40,0xe5,0x05,0x6f = movi v0.2d, #0xff00ff00ff00ff00 +0x40,0xe5,0x05,0x2f = movi d0, #0xff00ff00ff00ff00 +0x01,0xf6,0x03,0x0f = fmov v1.2s, #1.00000000 +0x0f,0xf6,0x03,0x4f = fmov v15.4s, #1.00000000 +0x1f,0xf6,0x03,0x6f = fmov v31.2d, #1.00000000 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mul-div-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mul-div-instructions.s.cs new file mode 100644 index 0000000..ab4aaac --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-mul-div-instructions.s.cs @@ -0,0 +1,24 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x9c,0x22,0x0e = mul v0.8b, v1.8b, v2.8b +0x20,0x9c,0x22,0x4e = mul v0.16b, v1.16b, v2.16b +0x20,0x9c,0x62,0x0e = mul v0.4h, v1.4h, v2.4h +0x20,0x9c,0x62,0x4e = mul v0.8h, v1.8h, v2.8h +0x20,0x9c,0xa2,0x0e = mul v0.2s, v1.2s, v2.2s +0x20,0x9c,0xa2,0x4e = mul v0.4s, v1.4s, v2.4s +0x20,0xdc,0x22,0x2e = fmul v0.2s, v1.2s, v2.2s +0x20,0xdc,0x22,0x6e = fmul v0.4s, v1.4s, v2.4s +0x20,0xdc,0x62,0x6e = fmul v0.2d, v1.2d, v2.2d +0x20,0xfc,0x22,0x2e = fdiv v0.2s, v1.2s, v2.2s +0x20,0xfc,0x22,0x6e = fdiv v0.4s, v1.4s, v2.4s +0x20,0xfc,0x62,0x6e = fdiv v0.2d, v1.2d, v2.2d +0xf1,0x9f,0x30,0x2e = pmul v17.8b, v31.8b, v16.8b +0x20,0x9c,0x22,0x6e = pmul v0.16b, v1.16b, v2.16b +0x22,0xb7,0x63,0x0e = sqdmulh v2.4h, v25.4h, v3.4h +0xac,0xb4,0x6d,0x4e = sqdmulh v12.8h, v5.8h, v13.8h +0x23,0xb4,0xbe,0x0e = sqdmulh v3.2s, v1.2s, v30.2s +0x22,0xb7,0x63,0x2e = sqrdmulh v2.4h, v25.4h, v3.4h +0xac,0xb4,0x6d,0x6e = sqrdmulh v12.8h, v5.8h, v13.8h +0x23,0xb4,0xbe,0x2e = sqrdmulh v3.2s, v1.2s, v30.2s +0xb5,0xdc,0x2d,0x0e = fmulx v21.2s, v5.2s, v13.2s +0x21,0xdf,0x23,0x4e = fmulx v1.4s, v25.4s, v3.4s +0xdf,0xde,0x62,0x4e = fmulx v31.2d, v22.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-perm.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-perm.s.cs new file mode 100644 index 0000000..7b6b40e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-perm.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x18,0x02,0x0e = uzp1 v0.8b, v1.8b, v2.8b +0x20,0x18,0x02,0x4e = uzp1 v0.16b, v1.16b, v2.16b +0x20,0x18,0x42,0x0e = uzp1 v0.4h, v1.4h, v2.4h +0x20,0x18,0x42,0x4e = uzp1 v0.8h, v1.8h, v2.8h +0x20,0x18,0x82,0x0e = uzp1 v0.2s, v1.2s, v2.2s +0x20,0x18,0x82,0x4e = uzp1 v0.4s, v1.4s, v2.4s +0x20,0x18,0xc2,0x4e = uzp1 v0.2d, v1.2d, v2.2d +0x20,0x28,0x02,0x0e = trn1 v0.8b, v1.8b, v2.8b +0x20,0x28,0x02,0x4e = trn1 v0.16b, v1.16b, v2.16b +0x20,0x28,0x42,0x0e = trn1 v0.4h, v1.4h, v2.4h +0x20,0x28,0x42,0x4e = trn1 v0.8h, v1.8h, v2.8h +0x20,0x28,0x82,0x0e = trn1 v0.2s, v1.2s, v2.2s +0x20,0x28,0x82,0x4e = trn1 v0.4s, v1.4s, v2.4s +0x20,0x28,0xc2,0x4e = trn1 v0.2d, v1.2d, v2.2d +0x20,0x38,0x02,0x0e = zip1 v0.8b, v1.8b, v2.8b +0x20,0x38,0x02,0x4e = zip1 v0.16b, v1.16b, v2.16b +0x20,0x38,0x42,0x0e = zip1 v0.4h, v1.4h, v2.4h +0x20,0x38,0x42,0x4e = zip1 v0.8h, v1.8h, v2.8h +0x20,0x38,0x82,0x0e = zip1 v0.2s, v1.2s, v2.2s +0x20,0x38,0x82,0x4e = zip1 v0.4s, v1.4s, v2.4s +0x20,0x38,0xc2,0x4e = zip1 v0.2d, v1.2d, v2.2d +0x20,0x58,0x02,0x0e = uzp2 v0.8b, v1.8b, v2.8b +0x20,0x58,0x02,0x4e = uzp2 v0.16b, v1.16b, v2.16b +0x20,0x58,0x42,0x0e = uzp2 v0.4h, v1.4h, v2.4h +0x20,0x58,0x42,0x4e = uzp2 v0.8h, v1.8h, v2.8h +0x20,0x58,0x82,0x0e = uzp2 v0.2s, v1.2s, v2.2s +0x20,0x58,0x82,0x4e = uzp2 v0.4s, v1.4s, v2.4s +0x20,0x58,0xc2,0x4e = uzp2 v0.2d, v1.2d, v2.2d +0x20,0x68,0x02,0x0e = trn2 v0.8b, v1.8b, v2.8b +0x20,0x68,0x02,0x4e = trn2 v0.16b, v1.16b, v2.16b +0x20,0x68,0x42,0x0e = trn2 v0.4h, v1.4h, v2.4h +0x20,0x68,0x42,0x4e = trn2 v0.8h, v1.8h, v2.8h +0x20,0x68,0x82,0x0e = trn2 v0.2s, v1.2s, v2.2s +0x20,0x68,0x82,0x4e = trn2 v0.4s, v1.4s, v2.4s +0x20,0x68,0xc2,0x4e = trn2 v0.2d, v1.2d, v2.2d +0x20,0x78,0x02,0x0e = zip2 v0.8b, v1.8b, v2.8b +0x20,0x78,0x02,0x4e = zip2 v0.16b, v1.16b, v2.16b +0x20,0x78,0x42,0x0e = zip2 v0.4h, v1.4h, v2.4h +0x20,0x78,0x42,0x4e = zip2 v0.8h, v1.8h, v2.8h +0x20,0x78,0x82,0x0e = zip2 v0.2s, v1.2s, v2.2s +0x20,0x78,0x82,0x4e = zip2 v0.4s, v1.4s, v2.4s +0x20,0x78,0xc2,0x4e = zip2 v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-halving-add.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-halving-add.s.cs new file mode 100644 index 0000000..91f575e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-halving-add.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x14,0x22,0x0e = srhadd v0.8b, v1.8b, v2.8b +0x20,0x14,0x22,0x4e = srhadd v0.16b, v1.16b, v2.16b +0x20,0x14,0x62,0x0e = srhadd v0.4h, v1.4h, v2.4h +0x20,0x14,0x62,0x4e = srhadd v0.8h, v1.8h, v2.8h +0x20,0x14,0xa2,0x0e = srhadd v0.2s, v1.2s, v2.2s +0x20,0x14,0xa2,0x4e = srhadd v0.4s, v1.4s, v2.4s +0x20,0x14,0x22,0x2e = urhadd v0.8b, v1.8b, v2.8b +0x20,0x14,0x22,0x6e = urhadd v0.16b, v1.16b, v2.16b +0x20,0x14,0x62,0x2e = urhadd v0.4h, v1.4h, v2.4h +0x20,0x14,0x62,0x6e = urhadd v0.8h, v1.8h, v2.8h +0x20,0x14,0xa2,0x2e = urhadd v0.2s, v1.2s, v2.2s +0x20,0x14,0xa2,0x6e = urhadd v0.4s, v1.4s, v2.4s diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-shift.s.cs new file mode 100644 index 0000000..11a27af --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-rounding-shift.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b +0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b +0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h +0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h +0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s +0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s +0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d +0x20,0x54,0x22,0x2e = urshl v0.8b, v1.8b, v2.8b +0x20,0x54,0x22,0x6e = urshl v0.16b, v1.16b, v2.16b +0x20,0x54,0x62,0x2e = urshl v0.4h, v1.4h, v2.4h +0x20,0x54,0x62,0x6e = urshl v0.8h, v1.8h, v2.8h +0x20,0x54,0xa2,0x2e = urshl v0.2s, v1.2s, v2.2s +0x20,0x54,0xa2,0x6e = urshl v0.4s, v1.4s, v2.4s +0x20,0x54,0xe2,0x6e = urshl v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-add-sub.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-add-sub.s.cs new file mode 100644 index 0000000..dc8e852 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-add-sub.s.cs @@ -0,0 +1,29 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x0c,0x22,0x0e = sqadd v0.8b, v1.8b, v2.8b +0x20,0x0c,0x22,0x4e = sqadd v0.16b, v1.16b, v2.16b +0x20,0x0c,0x62,0x0e = sqadd v0.4h, v1.4h, v2.4h +0x20,0x0c,0x62,0x4e = sqadd v0.8h, v1.8h, v2.8h +0x20,0x0c,0xa2,0x0e = sqadd v0.2s, v1.2s, v2.2s +0x20,0x0c,0xa2,0x4e = sqadd v0.4s, v1.4s, v2.4s +0x20,0x0c,0xe2,0x4e = sqadd v0.2d, v1.2d, v2.2d +0x20,0x0c,0x22,0x2e = uqadd v0.8b, v1.8b, v2.8b +0x20,0x0c,0x22,0x6e = uqadd v0.16b, v1.16b, v2.16b +0x20,0x0c,0x62,0x2e = uqadd v0.4h, v1.4h, v2.4h +0x20,0x0c,0x62,0x6e = uqadd v0.8h, v1.8h, v2.8h +0x20,0x0c,0xa2,0x2e = uqadd v0.2s, v1.2s, v2.2s +0x20,0x0c,0xa2,0x6e = uqadd v0.4s, v1.4s, v2.4s +0x20,0x0c,0xe2,0x6e = uqadd v0.2d, v1.2d, v2.2d +0x20,0x2c,0x22,0x0e = sqsub v0.8b, v1.8b, v2.8b +0x20,0x2c,0x22,0x4e = sqsub v0.16b, v1.16b, v2.16b +0x20,0x2c,0x62,0x0e = sqsub v0.4h, v1.4h, v2.4h +0x20,0x2c,0x62,0x4e = sqsub v0.8h, v1.8h, v2.8h +0x20,0x2c,0xa2,0x0e = sqsub v0.2s, v1.2s, v2.2s +0x20,0x2c,0xa2,0x4e = sqsub v0.4s, v1.4s, v2.4s +0x20,0x2c,0xe2,0x4e = sqsub v0.2d, v1.2d, v2.2d +0x20,0x2c,0x22,0x2e = uqsub v0.8b, v1.8b, v2.8b +0x20,0x2c,0x22,0x6e = uqsub v0.16b, v1.16b, v2.16b +0x20,0x2c,0x62,0x2e = uqsub v0.4h, v1.4h, v2.4h +0x20,0x2c,0x62,0x6e = uqsub v0.8h, v1.8h, v2.8h +0x20,0x2c,0xa2,0x2e = uqsub v0.2s, v1.2s, v2.2s +0x20,0x2c,0xa2,0x6e = uqsub v0.4s, v1.4s, v2.4s +0x20,0x2c,0xe2,0x6e = uqsub v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs new file mode 100644 index 0000000..e7c774a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x5c,0x22,0x0e = sqrshl v0.8b, v1.8b, v2.8b +0x20,0x5c,0x22,0x4e = sqrshl v0.16b, v1.16b, v2.16b +0x20,0x5c,0x62,0x0e = sqrshl v0.4h, v1.4h, v2.4h +0x20,0x5c,0x62,0x4e = sqrshl v0.8h, v1.8h, v2.8h +0x20,0x5c,0xa2,0x0e = sqrshl v0.2s, v1.2s, v2.2s +0x20,0x5c,0xa2,0x4e = sqrshl v0.4s, v1.4s, v2.4s +0x20,0x5c,0xe2,0x4e = sqrshl v0.2d, v1.2d, v2.2d +0x20,0x5c,0x22,0x2e = uqrshl v0.8b, v1.8b, v2.8b +0x20,0x5c,0x22,0x6e = uqrshl v0.16b, v1.16b, v2.16b +0x20,0x5c,0x62,0x2e = uqrshl v0.4h, v1.4h, v2.4h +0x20,0x5c,0x62,0x6e = uqrshl v0.8h, v1.8h, v2.8h +0x20,0x5c,0xa2,0x2e = uqrshl v0.2s, v1.2s, v2.2s +0x20,0x5c,0xa2,0x6e = uqrshl v0.4s, v1.4s, v2.4s +0x20,0x5c,0xe2,0x6e = uqrshl v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-shift.s.cs new file mode 100644 index 0000000..d4f7c94 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-saturating-shift.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x4c,0x22,0x0e = sqshl v0.8b, v1.8b, v2.8b +0x20,0x4c,0x22,0x4e = sqshl v0.16b, v1.16b, v2.16b +0x20,0x4c,0x62,0x0e = sqshl v0.4h, v1.4h, v2.4h +0x20,0x4c,0x62,0x4e = sqshl v0.8h, v1.8h, v2.8h +0x20,0x4c,0xa2,0x0e = sqshl v0.2s, v1.2s, v2.2s +0x20,0x4c,0xa2,0x4e = sqshl v0.4s, v1.4s, v2.4s +0x20,0x4c,0xe2,0x4e = sqshl v0.2d, v1.2d, v2.2d +0x20,0x4c,0x22,0x2e = uqshl v0.8b, v1.8b, v2.8b +0x20,0x4c,0x22,0x6e = uqshl v0.16b, v1.16b, v2.16b +0x20,0x4c,0x62,0x2e = uqshl v0.4h, v1.4h, v2.4h +0x20,0x4c,0x62,0x6e = uqshl v0.8h, v1.8h, v2.8h +0x20,0x4c,0xa2,0x2e = uqshl v0.2s, v1.2s, v2.2s +0x20,0x4c,0xa2,0x6e = uqshl v0.4s, v1.4s, v2.4s +0x20,0x4c,0xe2,0x6e = uqshl v0.2d, v1.2d, v2.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-abs.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-abs.s.cs new file mode 100644 index 0000000..d37976f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-abs.s.cs @@ -0,0 +1,8 @@ +# CS_ARCH_ARM64, 0, None +0x1d,0xbb,0xe0,0x5e = abs d29, d24 +0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20 +0x1d,0xd7,0xf4,0x7e = fabd d29, d24, d20 +0xd3,0x79,0x20,0x5e = sqabs b19, b14 +0xf5,0x79,0x60,0x5e = sqabs h21, h15 +0x94,0x79,0xa0,0x5e = sqabs s20, s12 +0x92,0x79,0xe0,0x5e = sqabs d18, d12 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-add-sub.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-add-sub.s.cs new file mode 100644 index 0000000..e66cd56 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-add-sub.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM64, 0, None +0x1f,0x84,0xf0,0x5e = add d31, d0, d16 +0xe1,0x84,0xe8,0x7e = sub d1, d7, d8 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs new file mode 100644 index 0000000..3d63575 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x10,0x81,0x5f = fmla s0, s1, v1.s[0] +0x7e,0x11,0xa1,0x5f = fmla s30, s11, v1.s[1] +0xa4,0x18,0x87,0x5f = fmla s4, s5, v7.s[2] +0xd0,0x1a,0xb0,0x5f = fmla s16, s22, v16.s[3] +0x20,0x10,0xc1,0x5f = fmla d0, d1, v1.d[0] +0x7e,0x19,0xc1,0x5f = fmla d30, d11, v1.d[1] +0x62,0x50,0x84,0x5f = fmls s2, s3, v4.s[0] +0x5d,0x51,0xbc,0x5f = fmls s29, s10, v28.s[1] +0x85,0x59,0x97,0x5f = fmls s5, s12, v23.s[2] +0x27,0x5a,0xba,0x5f = fmls s7, s17, v26.s[3] +0x20,0x50,0xc1,0x5f = fmls d0, d1, v1.d[0] +0x7e,0x59,0xc1,0x5f = fmls d30, d11, v1.d[1] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs new file mode 100644 index 0000000..57b2f29 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x90,0x81,0x5f = fmul s0, s1, v1.s[0] +0x7e,0x91,0xa1,0x5f = fmul s30, s11, v1.s[1] +0xa4,0x98,0x87,0x5f = fmul s4, s5, v7.s[2] +0xd0,0x9a,0xb0,0x5f = fmul s16, s22, v16.s[3] +0x20,0x90,0xc1,0x5f = fmul d0, d1, v1.d[0] +0x7e,0x99,0xc1,0x5f = fmul d30, d11, v1.d[1] +0x46,0x90,0x88,0x7f = fmulx s6, s2, v8.s[0] +0x67,0x90,0xad,0x7f = fmulx s7, s3, v13.s[1] +0xe9,0x98,0x89,0x7f = fmulx s9, s7, v9.s[2] +0xad,0x9a,0xaa,0x7f = fmulx s13, s21, v10.s[3] +0x2f,0x91,0xc7,0x7f = fmulx d15, d9, v7.d[0] +0x8d,0x99,0xcb,0x7f = fmulx d13, d12, v11.d[1] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs new file mode 100644 index 0000000..af5fc8c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs @@ -0,0 +1,15 @@ +# CS_ARCH_ARM64, 0, None +0x00,0x30,0x40,0x5f = sqdmlal s0, h0, v0.h[0] +0x27,0x30,0x74,0x5f = sqdmlal s7, h1, v4.h[3] +0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4] +0xde,0x3b,0x7f,0x5f = sqdmlal s30, h30, v15.h[7] +0x00,0x30,0x83,0x5f = sqdmlal d0, s0, v3.s[0] +0xde,0x3b,0xbe,0x5f = sqdmlal d30, s30, v30.s[3] +0x28,0x31,0xae,0x5f = sqdmlal d8, s9, v14.s[1] +0x21,0x70,0x41,0x5f = sqdmlsl s1, h1, v1.h[0] +0x48,0x70,0x55,0x5f = sqdmlsl s8, h2, v5.h[1] +0xac,0x71,0x6e,0x5f = sqdmlsl s12, h13, v14.h[2] +0x9d,0x7b,0x7b,0x5f = sqdmlsl s29, h28, v11.h[7] +0x21,0x70,0x8d,0x5f = sqdmlsl d1, s1, v13.s[0] +0xff,0x7b,0x9f,0x5f = sqdmlsl d31, s31, v31.s[2] +0x50,0x7a,0xbc,0x5f = sqdmlsl d16, s18, v28.s[3] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs new file mode 100644 index 0000000..59f49c6 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs @@ -0,0 +1,18 @@ +# CS_ARCH_ARM64, 0, None +0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1] +0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2] +0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3] +0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7] +0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0] +0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3] +0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0] +0x20,0xc0,0x40,0x5f = sqdmulh h0, h1, v0.h[0] +0x6a,0xc9,0x4a,0x5f = sqdmulh h10, h11, v10.h[4] +0xb4,0xca,0x7f,0x5f = sqdmulh h20, h21, v15.h[7] +0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3] +0xc2,0xc0,0x87,0x5f = sqdmulh s2, s6, v7.s[0] +0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2] +0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4] +0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7] +0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2] +0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-compare.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-compare.s.cs new file mode 100644 index 0000000..c7f4ed5 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-compare.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_ARM64, 0, None +0xb4,0x8e,0xf6,0x7e = cmeq d20, d21, d22 +0xb4,0x9a,0xe0,0x5e = cmeq d20, d21, #0x0 +0xb4,0x3e,0xf6,0x7e = cmhs d20, d21, d22 +0xb4,0x3e,0xf6,0x5e = cmge d20, d21, d22 +0xb4,0x8a,0xe0,0x7e = cmge d20, d21, #0x0 +0xb4,0x36,0xf6,0x7e = cmhi d20, d21, d22 +0xb4,0x36,0xf6,0x5e = cmgt d20, d21, d22 +0xb4,0x8a,0xe0,0x5e = cmgt d20, d21, #0x0 +0xb4,0x9a,0xe0,0x7e = cmle d20, d21, #0x0 +0xb4,0xaa,0xe0,0x5e = cmlt d20, d21, #0x0 +0xb4,0x8e,0xf6,0x5e = cmtst d20, d21, d22 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-cvt.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-cvt.s.cs new file mode 100644 index 0000000..24ee071 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-cvt.s.cs @@ -0,0 +1,34 @@ +# CS_ARCH_ARM64, 0, None +0xb6,0xd9,0x21,0x5e = scvtf s22, s13 +0x95,0xd9,0x61,0x5e = scvtf d21, d12 +0xb6,0xd9,0x21,0x7e = ucvtf s22, s13 +0xd5,0xd9,0x61,0x7e = ucvtf d21, d14 +0xb6,0xe5,0x20,0x5f = scvtf s22, s13, #32 +0x95,0xe5,0x40,0x5f = scvtf d21, d12, #64 +0xb6,0xe5,0x20,0x7f = ucvtf s22, s13, #32 +0xd5,0xe5,0x40,0x7f = ucvtf d21, d14, #64 +0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1 +0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1 +0x95,0xfd,0x3f,0x7f = fcvtzu s21, s12, #1 +0x95,0xfd,0x7f,0x7f = fcvtzu d21, d12, #1 +0xb6,0x69,0x61,0x7e = fcvtxn s22, d13 +0xac,0xc9,0x21,0x5e = fcvtas s12, s13 +0xd5,0xc9,0x61,0x5e = fcvtas d21, d14 +0xac,0xc9,0x21,0x7e = fcvtau s12, s13 +0xd5,0xc9,0x61,0x7e = fcvtau d21, d14 +0xb6,0xb9,0x21,0x5e = fcvtms s22, s13 +0xd5,0xb9,0x61,0x5e = fcvtms d21, d14 +0xac,0xb9,0x21,0x7e = fcvtmu s12, s13 +0xd5,0xb9,0x61,0x7e = fcvtmu d21, d14 +0xb6,0xa9,0x21,0x5e = fcvtns s22, s13 +0xd5,0xa9,0x61,0x5e = fcvtns d21, d14 +0xac,0xa9,0x21,0x7e = fcvtnu s12, s13 +0xd5,0xa9,0x61,0x7e = fcvtnu d21, d14 +0xb6,0xa9,0xa1,0x5e = fcvtps s22, s13 +0xd5,0xa9,0xe1,0x5e = fcvtps d21, d14 +0xac,0xa9,0xa1,0x7e = fcvtpu s12, s13 +0xd5,0xa9,0xe1,0x7e = fcvtpu d21, d14 +0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13 +0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14 +0xac,0xb9,0xa1,0x7e = fcvtzu s12, s13 +0xd5,0xb9,0xe1,0x7e = fcvtzu d21, d14 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-dup.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-dup.s.cs new file mode 100644 index 0000000..afe386b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-dup.s.cs @@ -0,0 +1,23 @@ +# CS_ARCH_ARM64, 0, None +0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] +0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] +0x11,0x04,0x01,0x5e = mov b17, v0.b[0] +0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] +0x29,0x04,0x12,0x5e = mov h9, v1.h[4] +0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] +0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] +0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] +0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] +0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] +0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] +0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] +0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] +0x11,0x04,0x01,0x5e = mov b17, v0.b[0] +0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] +0x29,0x04,0x12,0x5e = mov h9, v1.h[4] +0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] +0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] +0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] +0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] +0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] +0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs new file mode 100644 index 0000000..3127d96 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs @@ -0,0 +1,10 @@ +# CS_ARCH_ARM64, 0, None +0xd3,0x29,0x21,0x7e = sqxtun b19, h14 +0xf5,0x29,0x61,0x7e = sqxtun h21, s15 +0x94,0x29,0xa1,0x7e = sqxtun s20, d12 +0x52,0x4a,0x21,0x5e = sqxtn b18, h18 +0x34,0x4a,0x61,0x5e = sqxtn h20, s17 +0xd3,0x49,0xa1,0x5e = sqxtn s19, d14 +0x52,0x4a,0x21,0x7e = uqxtn b18, h18 +0x34,0x4a,0x61,0x7e = uqxtn h20, s17 +0xd3,0x49,0xa1,0x7e = uqxtn s19, d14 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-fp-compare.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-fp-compare.s.cs new file mode 100644 index 0000000..6941352 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-fp-compare.s.cs @@ -0,0 +1,21 @@ +# CS_ARCH_ARM64, 0, None +0x6a,0xe5,0x2c,0x5e = fcmeq s10, s11, s12 +0xb4,0xe6,0x76,0x5e = fcmeq d20, d21, d22 +0x6a,0xd9,0xa0,0x5e = fcmeq s10, s11, #0.0 +0xb4,0xda,0xe0,0x5e = fcmeq d20, d21, #0.0 +0x6a,0xe5,0x2c,0x7e = fcmge s10, s11, s12 +0xb4,0xe6,0x76,0x7e = fcmge d20, d21, d22 +0x6a,0xc9,0xa0,0x7e = fcmge s10, s11, #0.0 +0xb4,0xca,0xe0,0x7e = fcmge d20, d21, #0.0 +0x6a,0xe5,0xac,0x7e = fcmgt s10, s11, s12 +0xb4,0xe6,0xf6,0x7e = fcmgt d20, d21, d22 +0x6a,0xc9,0xa0,0x5e = fcmgt s10, s11, #0.0 +0xb4,0xca,0xe0,0x5e = fcmgt d20, d21, #0.0 +0x6a,0xd9,0xa0,0x7e = fcmle s10, s11, #0.0 +0xb4,0xda,0xe0,0x7e = fcmle d20, d21, #0.0 +0x6a,0xe9,0xa0,0x5e = fcmlt s10, s11, #0.0 +0xb4,0xea,0xe0,0x5e = fcmlt d20, d21, #0.0 +0x6a,0xed,0x2c,0x7e = facge s10, s11, s12 +0xb4,0xee,0x76,0x7e = facge d20, d21, d22 +0x6a,0xed,0xac,0x7e = facgt s10, s11, s12 +0xb4,0xee,0xf6,0x7e = facgt d20, d21, d22 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-mul.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-mul.s.cs new file mode 100644 index 0000000..7c79173 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-mul.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0x6a,0xb5,0x6c,0x5e = sqdmulh h10, h11, h12 +0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2 +0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12 +0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2 +0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15 +0x77,0xdd,0x61,0x5e = fmulx d23, d11, d1 +0x71,0x93,0x6c,0x5e = sqdmlal s17, h27, h12 +0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12 +0x8e,0xb1,0x79,0x5e = sqdmlsl s14, h12, h25 +0xec,0xb2,0xad,0x5e = sqdmlsl d12, s23, s13 +0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12 +0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-neg.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-neg.s.cs new file mode 100644 index 0000000..8194228 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-neg.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_ARM64, 0, None +0x1d,0xbb,0xe0,0x7e = neg d29, d24 +0xd3,0x79,0x20,0x7e = sqneg b19, b14 +0xf5,0x79,0x60,0x7e = sqneg h21, h15 +0x94,0x79,0xa0,0x7e = sqneg s20, s12 +0x92,0x79,0xe0,0x7e = sqneg d18, d12 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-recip.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-recip.s.cs new file mode 100644 index 0000000..f2b4099 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-recip.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_ARM64, 0, None +0x15,0xfe,0x2d,0x5e = frecps s21, s16, s13 +0xd6,0xff,0x75,0x5e = frecps d22, d30, d21 +0xb5,0xfc,0xac,0x5e = frsqrts s21, s5, s12 +0xc8,0xfe,0xf2,0x5e = frsqrts d8, d22, d18 +0xd3,0xd9,0xa1,0x5e = frecpe s19, s14 +0xad,0xd9,0xe1,0x5e = frecpe d13, d13 +0x52,0xf9,0xa1,0x5e = frecpx s18, s10 +0x70,0xfa,0xe1,0x5e = frecpx d16, d19 +0xb6,0xd9,0xa1,0x7e = frsqrte s22, s13 +0x95,0xd9,0xe1,0x7e = frsqrte d21, d12 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs new file mode 100644 index 0000000..01ed5ca --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM64, 0, None +0x20,0xb8,0xf1,0x5e = addp d0, v1.2d +0x34,0xd8,0x70,0x7e = faddp d20, v1.2d diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs new file mode 100644 index 0000000..8a3bc45 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM64, 0, None +0xf1,0x57,0xe8,0x5e = srshl d17, d31, d8 +0xf1,0x57,0xe8,0x7e = urshl d17, d31, d8 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs new file mode 100644 index 0000000..cf961f8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2 +0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12 +0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2 +0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8 +0x20,0x0c,0x22,0x7e = uqadd b0, b1, b2 +0x6a,0x0d,0x6c,0x7e = uqadd h10, h11, h12 +0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2 +0xf1,0x0f,0xe8,0x7e = uqadd d17, d31, d8 +0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2 +0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12 +0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2 +0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8 +0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2 +0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12 +0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2 +0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8 +0xd3,0x39,0x20,0x5e = suqadd b19, b14 +0xf4,0x39,0x60,0x5e = suqadd h20, h15 +0x95,0x39,0xa0,0x5e = suqadd s21, s12 +0xd2,0x3a,0xe0,0x5e = suqadd d18, d22 +0xd3,0x39,0x20,0x7e = usqadd b19, b14 +0xf4,0x39,0x60,0x7e = usqadd h20, h15 +0x95,0x39,0xa0,0x7e = usqadd s21, s12 +0xd2,0x3a,0xe0,0x7e = usqadd d18, d22 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs new file mode 100644 index 0000000..a1affec --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x5c,0x22,0x5e = sqrshl b0, b1, b2 +0x6a,0x5d,0x6c,0x5e = sqrshl h10, h11, h12 +0xb4,0x5e,0xa2,0x5e = sqrshl s20, s21, s2 +0xf1,0x5f,0xe8,0x5e = sqrshl d17, d31, d8 +0x20,0x5c,0x22,0x7e = uqrshl b0, b1, b2 +0x6a,0x5d,0x6c,0x7e = uqrshl h10, h11, h12 +0xb4,0x5e,0xa2,0x7e = uqrshl s20, s21, s2 +0xf1,0x5f,0xe8,0x7e = uqrshl d17, d31, d8 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs new file mode 100644 index 0000000..7d38d0c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x4c,0x22,0x5e = sqshl b0, b1, b2 +0x6a,0x4d,0x6c,0x5e = sqshl h10, h11, h12 +0xb4,0x4e,0xa2,0x5e = sqshl s20, s21, s2 +0xf1,0x4f,0xe8,0x5e = sqshl d17, d31, d8 +0x20,0x4c,0x22,0x7e = uqshl b0, b1, b2 +0x6a,0x4d,0x6c,0x7e = uqshl h10, h11, h12 +0xb4,0x4e,0xa2,0x7e = uqshl s20, s21, s2 +0xf1,0x4f,0xe8,0x7e = uqshl d17, d31, d8 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift-imm.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift-imm.s.cs new file mode 100644 index 0000000..6ad743f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift-imm.s.cs @@ -0,0 +1,42 @@ +# CS_ARCH_ARM64, 0, None +0x0f,0x06,0x74,0x5f = sshr d15, d16, #12 +0x2a,0x06,0x6e,0x7f = ushr d10, d17, #18 +0x53,0x26,0x79,0x5f = srshr d19, d18, #7 +0xf4,0x26,0x61,0x7f = urshr d20, d23, #31 +0x92,0x15,0x6b,0x5f = ssra d18, d12, #21 +0xb4,0x15,0x43,0x7f = usra d20, d13, #61 +0x6f,0x35,0x6d,0x5f = srsra d15, d11, #19 +0x52,0x35,0x73,0x7f = ursra d18, d10, #13 +0x47,0x55,0x4c,0x5f = shl d7, d10, #12 +0x6b,0x76,0x0f,0x5f = sqshl b11, b19, #7 +0x4d,0x76,0x1b,0x5f = sqshl h13, h18, #11 +0x2e,0x76,0x36,0x5f = sqshl s14, s17, #22 +0x0f,0x76,0x73,0x5f = sqshl d15, d16, #51 +0xf2,0x75,0x0e,0x7f = uqshl b18, b15, #6 +0x4b,0x76,0x17,0x7f = uqshl h11, h18, #7 +0x6e,0x76,0x32,0x7f = uqshl s14, s19, #18 +0x8f,0x75,0x53,0x7f = uqshl d15, d12, #19 +0x4f,0x66,0x0e,0x7f = sqshlu b15, b18, #6 +0x33,0x66,0x16,0x7f = sqshlu h19, h17, #6 +0xd0,0x65,0x39,0x7f = sqshlu s16, s14, #25 +0xab,0x65,0x60,0x7f = sqshlu d11, d13, #32 +0x8a,0x45,0x72,0x7f = sri d10, d12, #14 +0xca,0x55,0x4c,0x7f = sli d10, d14, #12 +0xea,0x95,0x0b,0x5f = sqshrn b10, h15, #5 +0x51,0x95,0x1c,0x5f = sqshrn h17, s10, #4 +0x52,0x95,0x21,0x5f = sqshrn s18, d10, #31 +0x4c,0x95,0x09,0x7f = uqshrn b12, h10, #7 +0xca,0x95,0x1b,0x7f = uqshrn h10, s14, #5 +0x8a,0x95,0x33,0x7f = uqshrn s10, d12, #13 +0xaa,0x9d,0x0e,0x5f = sqrshrn b10, h13, #2 +0x4f,0x9d,0x1a,0x5f = sqrshrn h15, s10, #6 +0x8f,0x9d,0x37,0x5f = sqrshrn s15, d12, #9 +0x8a,0x9d,0x0b,0x7f = uqrshrn b10, h12, #5 +0x4c,0x9d,0x12,0x7f = uqrshrn h12, s10, #14 +0x4a,0x9d,0x27,0x7f = uqrshrn s10, d10, #25 +0x4f,0x85,0x09,0x7f = sqshrun b15, h10, #7 +0xd4,0x85,0x1d,0x7f = sqshrun h20, s14, #3 +0xea,0x85,0x31,0x7f = sqshrun s10, d15, #15 +0x51,0x8d,0x0a,0x7f = sqrshrun b17, h10, #6 +0xaa,0x8d,0x11,0x7f = sqrshrun h10, s13, #15 +0x16,0x8e,0x21,0x7f = sqrshrun s22, d16, #31 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift.s.cs new file mode 100644 index 0000000..df9c71c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-scalar-shift.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_ARM64, 0, None +0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8 +0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift-left-long.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift-left-long.s.cs new file mode 100644 index 0000000..aedf137 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift-left-long.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_ARM64, 0, None +0x20,0xa4,0x0b,0x0f = sshll v0.8h, v1.8b, #3 +0x20,0xa4,0x13,0x0f = sshll v0.4s, v1.4h, #3 +0x20,0xa4,0x23,0x0f = sshll v0.2d, v1.2s, #3 +0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3 +0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3 +0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3 +0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3 +0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3 +0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3 +0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3 +0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3 +0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift.s.cs new file mode 100644 index 0000000..7fc3339 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-shift.s.cs @@ -0,0 +1,22 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b +0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b +0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h +0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h +0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s +0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s +0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d +0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b +0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b +0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h +0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h +0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s +0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s +0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d +0x20,0x54,0x0b,0x0f = shl v0.8b, v1.8b, #3 +0x20,0x54,0x13,0x0f = shl v0.4h, v1.4h, #3 +0x20,0x54,0x23,0x0f = shl v0.2s, v1.2s, #3 +0x20,0x54,0x0b,0x4f = shl v0.16b, v1.16b, #3 +0x20,0x54,0x13,0x4f = shl v0.8h, v1.8h, #3 +0x20,0x54,0x23,0x4f = shl v0.4s, v1.4s, #3 +0x20,0x54,0x43,0x4f = shl v0.2d, v1.2d, #3 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-copy.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-copy.s.cs new file mode 100644 index 0000000..60fcfab --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-copy.s.cs @@ -0,0 +1,42 @@ +# CS_ARCH_ARM64, 0, None +0x22,0x1c,0x05,0x4e = ins v2.b[2], w1 +0xc7,0x1d,0x1e,0x4e = ins v7.h[7], w14 +0xd4,0x1f,0x04,0x4e = ins v20.s[0], w30 +0xe1,0x1c,0x18,0x4e = ins v1.d[1], x7 +0x22,0x1c,0x05,0x4e = ins v2.b[2], w1 +0xc7,0x1d,0x1e,0x4e = ins v7.h[7], w14 +0xd4,0x1f,0x04,0x4e = ins v20.s[0], w30 +0xe1,0x1c,0x18,0x4e = ins v1.d[1], x7 +0x01,0x2c,0x1f,0x0e = smov w1, v0.b[15] +0xce,0x2c,0x12,0x0e = smov w14, v6.h[4] +0x01,0x2c,0x1f,0x4e = smov x1, v0.b[15] +0xce,0x2c,0x12,0x4e = smov x14, v6.h[4] +0x34,0x2d,0x14,0x4e = smov x20, v9.s[2] +0x01,0x3c,0x1f,0x0e = umov w1, v0.b[15] +0xce,0x3c,0x12,0x0e = umov w14, v6.h[4] +0x34,0x3d,0x14,0x0e = mov w20, v9.s[2] +0x47,0x3e,0x18,0x4e = mov x7, v18.d[1] +0x34,0x3d,0x14,0x0e = mov w20, v9.s[2] +0x47,0x3e,0x18,0x4e = mov x7, v18.d[1] +0x61,0x34,0x1d,0x6e = ins v1.b[14], v3.b[6] +0xe6,0x54,0x1e,0x6e = ins v6.h[7], v7.h[5] +0xcf,0x46,0x1c,0x6e = ins v15.s[3], v22.s[2] +0x80,0x44,0x08,0x6e = ins v0.d[0], v4.d[1] +0x61,0x34,0x1d,0x6e = ins v1.b[14], v3.b[6] +0xe6,0x54,0x1e,0x6e = ins v6.h[7], v7.h[5] +0xcf,0x46,0x1c,0x6e = ins v15.s[3], v22.s[2] +0x80,0x44,0x08,0x6e = ins v0.d[0], v4.d[1] +0x41,0x04,0x05,0x0e = dup v1.8b, v2.b[2] +0xeb,0x04,0x1e,0x0e = dup v11.4h, v7.h[7] +0x91,0x06,0x04,0x0e = dup v17.2s, v20.s[0] +0x41,0x04,0x05,0x4e = dup v1.16b, v2.b[2] +0xeb,0x04,0x1e,0x4e = dup v11.8h, v7.h[7] +0x91,0x06,0x04,0x4e = dup v17.4s, v20.s[0] +0x25,0x04,0x18,0x4e = dup v5.2d, v1.d[1] +0x21,0x0c,0x01,0x0e = dup v1.8b, w1 +0xcb,0x0d,0x02,0x0e = dup v11.4h, w14 +0xd1,0x0f,0x04,0x0e = dup v17.2s, w30 +0x41,0x0c,0x01,0x4e = dup v1.16b, w2 +0x0b,0x0e,0x02,0x4e = dup v11.8h, w16 +0x91,0x0f,0x04,0x4e = dup v17.4s, w28 +0x05,0x0c,0x08,0x4e = dup v5.2d, x0 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-multi-elem.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-multi-elem.s.cs new file mode 100644 index 0000000..e151688 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-multi-elem.s.cs @@ -0,0 +1,197 @@ +# CS_ARCH_ARM64, 0, None +0x00,0x70,0x00,0x4c = st1 {v0.16b}, [x0] +0xef,0x75,0x00,0x4c = st1 {v15.8h}, [x15] +0xff,0x7b,0x00,0x4c = st1 {v31.4s}, [sp] +0x00,0x7c,0x00,0x4c = st1 {v0.2d}, [x0] +0x00,0x70,0x00,0x0c = st1 {v0.8b}, [x0] +0xef,0x75,0x00,0x0c = st1 {v15.4h}, [x15] +0xff,0x7b,0x00,0x0c = st1 {v31.2s}, [sp] +0x00,0x7c,0x00,0x0c = st1 {v0.1d}, [x0] +0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0] +0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15] +0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp] +0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0] +0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0] +0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15] +0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp] +0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0] +0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0] +0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15] +0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp] +0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0] +0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0] +0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15] +0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp] +0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0] +0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0] +0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0] +0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0] +0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15] +0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp] +0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0] +0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0] +0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15] +0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp] +0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0] +0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15] +0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp] +0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0] +0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0] +0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15] +0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp] +0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x70,0x40,0x4c = ld1 {v0.16b}, [x0] +0xef,0x75,0x40,0x4c = ld1 {v15.8h}, [x15] +0xff,0x7b,0x40,0x4c = ld1 {v31.4s}, [sp] +0x00,0x7c,0x40,0x4c = ld1 {v0.2d}, [x0] +0x00,0x70,0x40,0x0c = ld1 {v0.8b}, [x0] +0xef,0x75,0x40,0x0c = ld1 {v15.4h}, [x15] +0xff,0x7b,0x40,0x0c = ld1 {v31.2s}, [sp] +0x00,0x7c,0x40,0x0c = ld1 {v0.1d}, [x0] +0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0] +0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15] +0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp] +0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0] +0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0] +0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15] +0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp] +0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0] +0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0] +0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15] +0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp] +0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0] +0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0] +0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15] +0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp] +0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0] +0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0] +0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0] +0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0] +0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15] +0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp] +0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0] +0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0] +0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15] +0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp] +0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0] +0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15] +0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp] +0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0] +0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0] +0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15] +0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp] +0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp] +0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-one-elem.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-one-elem.s.cs new file mode 100644 index 0000000..f920b62 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-ldst-one-elem.s.cs @@ -0,0 +1,129 @@ +# CS_ARCH_ARM64, 0, None +0x00,0xc0,0x40,0x4d = ld1r {v0.16b}, [x0] +0xef,0xc5,0x40,0x4d = ld1r {v15.8h}, [x15] +0xff,0xcb,0x40,0x4d = ld1r {v31.4s}, [sp] +0x00,0xcc,0x40,0x4d = ld1r {v0.2d}, [x0] +0x00,0xc0,0x40,0x0d = ld1r {v0.8b}, [x0] +0xef,0xc5,0x40,0x0d = ld1r {v15.4h}, [x15] +0xff,0xcb,0x40,0x0d = ld1r {v31.2s}, [sp] +0x00,0xcc,0x40,0x0d = ld1r {v0.1d}, [x0] +0x00,0xc0,0x60,0x4d = ld2r {v0.16b, v1.16b}, [x0] +0xef,0xc5,0x60,0x4d = ld2r {v15.8h, v16.8h}, [x15] +0xff,0xcb,0x60,0x4d = ld2r {v31.4s, v0.4s}, [sp] +0x00,0xcc,0x60,0x4d = ld2r {v0.2d, v1.2d}, [x0] +0x00,0xc0,0x60,0x0d = ld2r {v0.8b, v1.8b}, [x0] +0xef,0xc5,0x60,0x0d = ld2r {v15.4h, v16.4h}, [x15] +0xff,0xcb,0x60,0x0d = ld2r {v31.2s, v0.2s}, [sp] +0xff,0xcf,0x60,0x0d = ld2r {v31.1d, v0.1d}, [sp] +0x00,0xe0,0x40,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0] +0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15] +0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp] +0x00,0xec,0x40,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0] +0x00,0xe0,0x40,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0] +0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15] +0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp] +0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp] +0x00,0xe0,0x60,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +0xef,0xe5,0x60,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] +0xff,0xeb,0x60,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] +0x00,0xec,0x60,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0xe0,0x60,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +0xef,0xe5,0x60,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] +0xff,0xeb,0x60,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0xff,0xef,0x60,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +0x00,0x04,0x40,0x4d = ld1 {v0.b}[9], [x0] +0xef,0x59,0x40,0x4d = ld1 {v15.h}[7], [x15] +0xff,0x93,0x40,0x4d = ld1 {v31.s}[3], [sp] +0x00,0x84,0x40,0x4d = ld1 {v0.d}[1], [x0] +0x00,0x04,0x60,0x4d = ld2 {v0.b, v1.b}[9], [x0] +0xef,0x59,0x60,0x4d = ld2 {v15.h, v16.h}[7], [x15] +0xff,0x93,0x60,0x4d = ld2 {v31.s, v0.s}[3], [sp] +0x00,0x84,0x60,0x4d = ld2 {v0.d, v1.d}[1], [x0] +0x00,0x24,0x40,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0] +0xef,0x79,0x40,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15] +0xff,0xb3,0x40,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp] +0x00,0xa4,0x40,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0] +0x00,0x24,0x60,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +0xef,0x79,0x60,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] +0xff,0xb3,0x60,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] +0x00,0xa4,0x60,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] +0x00,0x04,0x00,0x4d = st1 {v0.b}[9], [x0] +0xef,0x59,0x00,0x4d = st1 {v15.h}[7], [x15] +0xff,0x93,0x00,0x4d = st1 {v31.s}[3], [sp] +0x00,0x84,0x00,0x4d = st1 {v0.d}[1], [x0] +0x00,0x04,0x20,0x4d = st2 {v0.b, v1.b}[9], [x0] +0xef,0x59,0x20,0x4d = st2 {v15.h, v16.h}[7], [x15] +0xff,0x93,0x20,0x4d = st2 {v31.s, v0.s}[3], [sp] +0x00,0x84,0x20,0x4d = st2 {v0.d, v1.d}[1], [x0] +0x00,0x24,0x00,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0] +0xef,0x79,0x00,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15] +0xff,0xb3,0x00,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp] +0x00,0xa4,0x00,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0] +0x00,0x24,0x20,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +0xef,0x79,0x20,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] +0xff,0xb3,0x20,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] +0x00,0xa4,0x20,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] +0x00,0xc0,0xdf,0x4d = ld1r {v0.16b}, [x0], #1 +0xef,0xc5,0xdf,0x4d = ld1r {v15.8h}, [x15], #2 +0xff,0xcb,0xdf,0x4d = ld1r {v31.4s}, [sp], #4 +0x00,0xcc,0xdf,0x4d = ld1r {v0.2d}, [x0], #8 +0x00,0xc0,0xc0,0x0d = ld1r {v0.8b}, [x0], x0 +0xef,0xc5,0xc1,0x0d = ld1r {v15.4h}, [x15], x1 +0xff,0xcb,0xc2,0x0d = ld1r {v31.2s}, [sp], x2 +0x00,0xcc,0xc3,0x0d = ld1r {v0.1d}, [x0], x3 +0x00,0xc0,0xff,0x4d = ld2r {v0.16b, v1.16b}, [x0], #2 +0xef,0xc5,0xff,0x4d = ld2r {v15.8h, v16.8h}, [x15], #4 +0xff,0xcb,0xff,0x4d = ld2r {v31.4s, v0.4s}, [sp], #8 +0x00,0xcc,0xff,0x4d = ld2r {v0.2d, v1.2d}, [x0], #16 +0x00,0xc0,0xe6,0x0d = ld2r {v0.8b, v1.8b}, [x0], x6 +0xef,0xc5,0xe7,0x0d = ld2r {v15.4h, v16.4h}, [x15], x7 +0xff,0xcb,0xe9,0x0d = ld2r {v31.2s, v0.2s}, [sp], x9 +0x1f,0xcc,0xe5,0x0d = ld2r {v31.1d, v0.1d}, [x0], x5 +0x00,0xe0,0xc9,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 +0xef,0xe5,0xc6,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 +0xff,0xeb,0xc7,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 +0x00,0xec,0xc5,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 +0x00,0xe0,0xdf,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 +0xef,0xe5,0xdf,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 +0xff,0xeb,0xdf,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 +0xff,0xef,0xdf,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 +0x00,0xe0,0xff,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 +0xef,0xe5,0xff,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 +0xff,0xeb,0xff,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 +0x00,0xec,0xff,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 +0x00,0xe0,0xe5,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 +0xef,0xe5,0xe9,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 +0xff,0xeb,0xfe,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 +0xff,0xef,0xe7,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +0x00,0x04,0xdf,0x4d = ld1 {v0.b}[9], [x0], #1 +0xef,0x59,0xc9,0x4d = ld1 {v15.h}[7], [x15], x9 +0xff,0x93,0xc6,0x4d = ld1 {v31.s}[3], [sp], x6 +0x00,0x84,0xdf,0x4d = ld1 {v0.d}[1], [x0], #8 +0x00,0x04,0xe3,0x4d = ld2 {v0.b, v1.b}[9], [x0], x3 +0xef,0x59,0xff,0x4d = ld2 {v15.h, v16.h}[7], [x15], #4 +0xff,0x93,0xff,0x4d = ld2 {v31.s, v0.s}[3], [sp], #8 +0x00,0x84,0xe0,0x4d = ld2 {v0.d, v1.d}[1], [x0], x0 +0x00,0x24,0xdf,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 +0xef,0x79,0xdf,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 +0xff,0xb3,0xc3,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 +0x00,0xa4,0xc6,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 +0x00,0x24,0xe5,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +0xef,0x79,0xe7,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 +0xff,0xb3,0xff,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 +0x00,0xa4,0xff,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 +0x00,0x04,0x9f,0x4d = st1 {v0.b}[9], [x0], #1 +0xef,0x59,0x89,0x4d = st1 {v15.h}[7], [x15], x9 +0xff,0x93,0x86,0x4d = st1 {v31.s}[3], [sp], x6 +0x00,0x84,0x9f,0x4d = st1 {v0.d}[1], [x0], #8 +0x00,0x04,0xa3,0x4d = st2 {v0.b, v1.b}[9], [x0], x3 +0xef,0x59,0xbf,0x4d = st2 {v15.h, v16.h}[7], [x15], #4 +0xff,0x93,0xbf,0x4d = st2 {v31.s, v0.s}[3], [sp], #8 +0x00,0x84,0xa0,0x4d = st2 {v0.d, v1.d}[1], [x0], x0 +0x00,0x24,0x9f,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0], #3 +0xef,0x79,0x9f,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15], #6 +0xff,0xb3,0x83,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp], x3 +0x00,0xa4,0x86,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0], x6 +0x00,0x24,0xa5,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +0xef,0x79,0xa7,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 +0xff,0xb3,0xbf,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 +0x00,0xa4,0xbf,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-misc.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-misc.s.cs new file mode 100644 index 0000000..6c7e2ca --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-misc.s.cs @@ -0,0 +1,213 @@ +# CS_ARCH_ARM64, 0, None +0xe0,0x0b,0x20,0x4e = rev64 v0.16b, v31.16b +0x82,0x08,0x60,0x4e = rev64 v2.8h, v4.8h +0x06,0x09,0xa0,0x4e = rev64 v6.4s, v8.4s +0x21,0x09,0x20,0x0e = rev64 v1.8b, v9.8b +0xad,0x0a,0x60,0x0e = rev64 v13.4h, v21.4h +0x04,0x08,0xa0,0x0e = rev64 v4.2s, v0.2s +0xfe,0x0b,0x20,0x6e = rev32 v30.16b, v31.16b +0xe4,0x08,0x60,0x6e = rev32 v4.8h, v7.8h +0x35,0x08,0x20,0x2e = rev32 v21.8b, v1.8b +0x20,0x09,0x60,0x2e = rev32 v0.4h, v9.4h +0xfe,0x1b,0x20,0x4e = rev16 v30.16b, v31.16b +0x35,0x18,0x20,0x0e = rev16 v21.8b, v1.8b +0xa3,0x2a,0x20,0x4e = saddlp v3.8h, v21.16b +0xa8,0x28,0x20,0x0e = saddlp v8.4h, v5.8b +0x29,0x28,0x60,0x4e = saddlp v9.4s, v1.8h +0x20,0x28,0x60,0x0e = saddlp v0.2s, v1.4h +0x8c,0x28,0xa0,0x4e = saddlp v12.2d, v4.4s +0x91,0x2b,0xa0,0x0e = saddlp v17.1d, v28.2s +0xa3,0x2a,0x20,0x6e = uaddlp v3.8h, v21.16b +0xa8,0x28,0x20,0x2e = uaddlp v8.4h, v5.8b +0x29,0x28,0x60,0x6e = uaddlp v9.4s, v1.8h +0x20,0x28,0x60,0x2e = uaddlp v0.2s, v1.4h +0x8c,0x28,0xa0,0x6e = uaddlp v12.2d, v4.4s +0x91,0x2b,0xa0,0x2e = uaddlp v17.1d, v28.2s +0xa3,0x6a,0x20,0x4e = sadalp v3.8h, v21.16b +0xa8,0x68,0x20,0x0e = sadalp v8.4h, v5.8b +0x29,0x68,0x60,0x4e = sadalp v9.4s, v1.8h +0x20,0x68,0x60,0x0e = sadalp v0.2s, v1.4h +0x8c,0x68,0xa0,0x4e = sadalp v12.2d, v4.4s +0x91,0x6b,0xa0,0x0e = sadalp v17.1d, v28.2s +0xa3,0x6a,0x20,0x6e = uadalp v3.8h, v21.16b +0xa8,0x68,0x20,0x2e = uadalp v8.4h, v5.8b +0x29,0x68,0x60,0x6e = uadalp v9.4s, v1.8h +0x20,0x68,0x60,0x2e = uadalp v0.2s, v1.4h +0x8c,0x68,0xa0,0x6e = uadalp v12.2d, v4.4s +0x91,0x6b,0xa0,0x2e = uadalp v17.1d, v28.2s +0xe0,0x3b,0x20,0x4e = suqadd v0.16b, v31.16b +0x82,0x38,0x60,0x4e = suqadd v2.8h, v4.8h +0x06,0x39,0xa0,0x4e = suqadd v6.4s, v8.4s +0x06,0x39,0xe0,0x4e = suqadd v6.2d, v8.2d +0x21,0x39,0x20,0x0e = suqadd v1.8b, v9.8b +0xad,0x3a,0x60,0x0e = suqadd v13.4h, v21.4h +0x04,0x38,0xa0,0x0e = suqadd v4.2s, v0.2s +0xe0,0x3b,0x20,0x6e = usqadd v0.16b, v31.16b +0x82,0x38,0x60,0x6e = usqadd v2.8h, v4.8h +0x06,0x39,0xa0,0x6e = usqadd v6.4s, v8.4s +0x06,0x39,0xe0,0x6e = usqadd v6.2d, v8.2d +0x21,0x39,0x20,0x2e = usqadd v1.8b, v9.8b +0xad,0x3a,0x60,0x2e = usqadd v13.4h, v21.4h +0x04,0x38,0xa0,0x2e = usqadd v4.2s, v0.2s +0xe0,0x7b,0x20,0x4e = sqabs v0.16b, v31.16b +0x82,0x78,0x60,0x4e = sqabs v2.8h, v4.8h +0x06,0x79,0xa0,0x4e = sqabs v6.4s, v8.4s +0x06,0x79,0xe0,0x4e = sqabs v6.2d, v8.2d +0x21,0x79,0x20,0x0e = sqabs v1.8b, v9.8b +0xad,0x7a,0x60,0x0e = sqabs v13.4h, v21.4h +0x04,0x78,0xa0,0x0e = sqabs v4.2s, v0.2s +0xe0,0x7b,0x20,0x6e = sqneg v0.16b, v31.16b +0x82,0x78,0x60,0x6e = sqneg v2.8h, v4.8h +0x06,0x79,0xa0,0x6e = sqneg v6.4s, v8.4s +0x06,0x79,0xe0,0x6e = sqneg v6.2d, v8.2d +0x21,0x79,0x20,0x2e = sqneg v1.8b, v9.8b +0xad,0x7a,0x60,0x2e = sqneg v13.4h, v21.4h +0x04,0x78,0xa0,0x2e = sqneg v4.2s, v0.2s +0xe0,0xbb,0x20,0x4e = abs v0.16b, v31.16b +0x82,0xb8,0x60,0x4e = abs v2.8h, v4.8h +0x06,0xb9,0xa0,0x4e = abs v6.4s, v8.4s +0x06,0xb9,0xe0,0x4e = abs v6.2d, v8.2d +0x21,0xb9,0x20,0x0e = abs v1.8b, v9.8b +0xad,0xba,0x60,0x0e = abs v13.4h, v21.4h +0x04,0xb8,0xa0,0x0e = abs v4.2s, v0.2s +0xe0,0xbb,0x20,0x6e = neg v0.16b, v31.16b +0x82,0xb8,0x60,0x6e = neg v2.8h, v4.8h +0x06,0xb9,0xa0,0x6e = neg v6.4s, v8.4s +0x06,0xb9,0xe0,0x6e = neg v6.2d, v8.2d +0x21,0xb9,0x20,0x2e = neg v1.8b, v9.8b +0xad,0xba,0x60,0x2e = neg v13.4h, v21.4h +0x04,0xb8,0xa0,0x2e = neg v4.2s, v0.2s +0xe0,0x4b,0x20,0x4e = cls v0.16b, v31.16b +0x82,0x48,0x60,0x4e = cls v2.8h, v4.8h +0x06,0x49,0xa0,0x4e = cls v6.4s, v8.4s +0x21,0x49,0x20,0x0e = cls v1.8b, v9.8b +0xad,0x4a,0x60,0x0e = cls v13.4h, v21.4h +0x04,0x48,0xa0,0x0e = cls v4.2s, v0.2s +0xe0,0x4b,0x20,0x6e = clz v0.16b, v31.16b +0x82,0x48,0x60,0x6e = clz v2.8h, v4.8h +0x06,0x49,0xa0,0x6e = clz v6.4s, v8.4s +0x21,0x49,0x20,0x2e = clz v1.8b, v9.8b +0xad,0x4a,0x60,0x2e = clz v13.4h, v21.4h +0x04,0x48,0xa0,0x2e = clz v4.2s, v0.2s +0xe0,0x5b,0x20,0x4e = cnt v0.16b, v31.16b +0x21,0x59,0x20,0x0e = cnt v1.8b, v9.8b +// 0xe0,0x5b,0x20,0x6e = not v0.16b, v31.16b +// 0x21,0x59,0x20,0x2e = not v1.8b, v9.8b +0xe0,0x5b,0x60,0x6e = rbit v0.16b, v31.16b +0x21,0x59,0x60,0x2e = rbit v1.8b, v9.8b +0x06,0xf9,0xa0,0x4e = fabs v6.4s, v8.4s +0x06,0xf9,0xe0,0x4e = fabs v6.2d, v8.2d +0x04,0xf8,0xa0,0x0e = fabs v4.2s, v0.2s +0x06,0xf9,0xa0,0x6e = fneg v6.4s, v8.4s +0x06,0xf9,0xe0,0x6e = fneg v6.2d, v8.2d +0x04,0xf8,0xa0,0x2e = fneg v4.2s, v0.2s +0xe0,0x2b,0x21,0x4e = xtn2 v0.16b, v31.8h +0x82,0x28,0x61,0x4e = xtn2 v2.8h, v4.4s +0x06,0x29,0xa1,0x4e = xtn2 v6.4s, v8.2d +0x21,0x29,0x21,0x0e = xtn v1.8b, v9.8h +0xad,0x2a,0x61,0x0e = xtn v13.4h, v21.4s +0x04,0x28,0xa1,0x0e = xtn v4.2s, v0.2d +0xe0,0x2b,0x21,0x6e = sqxtun2 v0.16b, v31.8h +0x82,0x28,0x61,0x6e = sqxtun2 v2.8h, v4.4s +0x06,0x29,0xa1,0x6e = sqxtun2 v6.4s, v8.2d +0x21,0x29,0x21,0x2e = sqxtun v1.8b, v9.8h +0xad,0x2a,0x61,0x2e = sqxtun v13.4h, v21.4s +0x04,0x28,0xa1,0x2e = sqxtun v4.2s, v0.2d +0xe0,0x4b,0x21,0x4e = sqxtn2 v0.16b, v31.8h +0x82,0x48,0x61,0x4e = sqxtn2 v2.8h, v4.4s +0x06,0x49,0xa1,0x4e = sqxtn2 v6.4s, v8.2d +0x21,0x49,0x21,0x0e = sqxtn v1.8b, v9.8h +0xad,0x4a,0x61,0x0e = sqxtn v13.4h, v21.4s +0x04,0x48,0xa1,0x0e = sqxtn v4.2s, v0.2d +0xe0,0x4b,0x21,0x6e = uqxtn2 v0.16b, v31.8h +0x82,0x48,0x61,0x6e = uqxtn2 v2.8h, v4.4s +0x06,0x49,0xa1,0x6e = uqxtn2 v6.4s, v8.2d +0x21,0x49,0x21,0x2e = uqxtn v1.8b, v9.8h +0xad,0x4a,0x61,0x2e = uqxtn v13.4h, v21.4s +0x04,0x48,0xa1,0x2e = uqxtn v4.2s, v0.2d +0x82,0x38,0x21,0x6e = shll2 v2.8h, v4.16b, #8 +0x06,0x39,0x61,0x6e = shll2 v6.4s, v8.8h, #16 +0x06,0x39,0xa1,0x6e = shll2 v6.2d, v8.4s, #32 +0x82,0x38,0x21,0x2e = shll v2.8h, v4.8b, #8 +0x06,0x39,0x61,0x2e = shll v6.4s, v8.4h, #16 +0x06,0x39,0xa1,0x2e = shll v6.2d, v8.2s, #32 +0x82,0x68,0x21,0x4e = fcvtn2 v2.8h, v4.4s +0x06,0x69,0x61,0x4e = fcvtn2 v6.4s, v8.2d +0xad,0x6a,0x21,0x0e = fcvtn v13.4h, v21.4s +0x04,0x68,0x61,0x0e = fcvtn v4.2s, v0.2d +0x06,0x69,0x61,0x6e = fcvtxn2 v6.4s, v8.2d +0x04,0x68,0x61,0x2e = fcvtxn v4.2s, v0.2d +0x29,0x78,0x21,0x0e = fcvtl v9.4s, v1.4h +0x20,0x78,0x61,0x0e = fcvtl v0.2d, v1.2s +0x8c,0x78,0x21,0x4e = fcvtl2 v12.4s, v4.8h +0x91,0x7b,0x61,0x4e = fcvtl2 v17.2d, v28.4s +0x06,0x89,0x21,0x4e = frintn v6.4s, v8.4s +0x06,0x89,0x61,0x4e = frintn v6.2d, v8.2d +0x04,0x88,0x21,0x0e = frintn v4.2s, v0.2s +0x06,0x89,0x21,0x6e = frinta v6.4s, v8.4s +0x06,0x89,0x61,0x6e = frinta v6.2d, v8.2d +0x04,0x88,0x21,0x2e = frinta v4.2s, v0.2s +0x06,0x89,0xa1,0x4e = frintp v6.4s, v8.4s +0x06,0x89,0xe1,0x4e = frintp v6.2d, v8.2d +0x04,0x88,0xa1,0x0e = frintp v4.2s, v0.2s +0x06,0x99,0x21,0x4e = frintm v6.4s, v8.4s +0x06,0x99,0x61,0x4e = frintm v6.2d, v8.2d +0x04,0x98,0x21,0x0e = frintm v4.2s, v0.2s +0x06,0x99,0x21,0x6e = frintx v6.4s, v8.4s +0x06,0x99,0x61,0x6e = frintx v6.2d, v8.2d +0x04,0x98,0x21,0x2e = frintx v4.2s, v0.2s +0x06,0x99,0xa1,0x4e = frintz v6.4s, v8.4s +0x06,0x99,0xe1,0x4e = frintz v6.2d, v8.2d +0x04,0x98,0xa1,0x0e = frintz v4.2s, v0.2s +0x06,0x99,0xa1,0x6e = frinti v6.4s, v8.4s +0x06,0x99,0xe1,0x6e = frinti v6.2d, v8.2d +0x04,0x98,0xa1,0x2e = frinti v4.2s, v0.2s +0x06,0xa9,0x21,0x4e = fcvtns v6.4s, v8.4s +0x06,0xa9,0x61,0x4e = fcvtns v6.2d, v8.2d +0x04,0xa8,0x21,0x0e = fcvtns v4.2s, v0.2s +0x06,0xa9,0x21,0x6e = fcvtnu v6.4s, v8.4s +0x06,0xa9,0x61,0x6e = fcvtnu v6.2d, v8.2d +0x04,0xa8,0x21,0x2e = fcvtnu v4.2s, v0.2s +0x06,0xa9,0xa1,0x4e = fcvtps v6.4s, v8.4s +0x06,0xa9,0xe1,0x4e = fcvtps v6.2d, v8.2d +0x04,0xa8,0xa1,0x0e = fcvtps v4.2s, v0.2s +0x06,0xa9,0xa1,0x6e = fcvtpu v6.4s, v8.4s +0x06,0xa9,0xe1,0x6e = fcvtpu v6.2d, v8.2d +0x04,0xa8,0xa1,0x2e = fcvtpu v4.2s, v0.2s +0x06,0xb9,0x21,0x4e = fcvtms v6.4s, v8.4s +0x06,0xb9,0x61,0x4e = fcvtms v6.2d, v8.2d +0x04,0xb8,0x21,0x0e = fcvtms v4.2s, v0.2s +0x06,0xb9,0x21,0x6e = fcvtmu v6.4s, v8.4s +0x06,0xb9,0x61,0x6e = fcvtmu v6.2d, v8.2d +0x04,0xb8,0x21,0x2e = fcvtmu v4.2s, v0.2s +0x06,0xb9,0xa1,0x4e = fcvtzs v6.4s, v8.4s +0x06,0xb9,0xe1,0x4e = fcvtzs v6.2d, v8.2d +0x04,0xb8,0xa1,0x0e = fcvtzs v4.2s, v0.2s +0x06,0xb9,0xa1,0x6e = fcvtzu v6.4s, v8.4s +0x06,0xb9,0xe1,0x6e = fcvtzu v6.2d, v8.2d +0x04,0xb8,0xa1,0x2e = fcvtzu v4.2s, v0.2s +0x06,0xc9,0x21,0x4e = fcvtas v6.4s, v8.4s +0x06,0xc9,0x61,0x4e = fcvtas v6.2d, v8.2d +0x04,0xc8,0x21,0x0e = fcvtas v4.2s, v0.2s +0x06,0xc9,0x21,0x6e = fcvtau v6.4s, v8.4s +0x06,0xc9,0x61,0x6e = fcvtau v6.2d, v8.2d +0x04,0xc8,0x21,0x2e = fcvtau v4.2s, v0.2s +0x06,0xc9,0xa1,0x4e = urecpe v6.4s, v8.4s +0x04,0xc8,0xa1,0x0e = urecpe v4.2s, v0.2s +0x06,0xc9,0xa1,0x6e = ursqrte v6.4s, v8.4s +0x04,0xc8,0xa1,0x2e = ursqrte v4.2s, v0.2s +0x06,0xd9,0x21,0x4e = scvtf v6.4s, v8.4s +0x06,0xd9,0x61,0x4e = scvtf v6.2d, v8.2d +0x04,0xd8,0x21,0x0e = scvtf v4.2s, v0.2s +0x06,0xd9,0x21,0x6e = ucvtf v6.4s, v8.4s +0x06,0xd9,0x61,0x6e = ucvtf v6.2d, v8.2d +0x04,0xd8,0x21,0x2e = ucvtf v4.2s, v0.2s +0x06,0xd9,0xa1,0x4e = frecpe v6.4s, v8.4s +0x06,0xd9,0xe1,0x4e = frecpe v6.2d, v8.2d +0x04,0xd8,0xa1,0x0e = frecpe v4.2s, v0.2s +0x06,0xd9,0xa1,0x6e = frsqrte v6.4s, v8.4s +0x06,0xd9,0xe1,0x6e = frsqrte v6.2d, v8.2d +0x04,0xd8,0xa1,0x2e = frsqrte v4.2s, v0.2s +0x06,0xf9,0xa1,0x6e = fsqrt v6.4s, v8.4s +0x06,0xf9,0xe1,0x6e = fsqrt v6.2d, v8.2d +0x04,0xf8,0xa1,0x2e = fsqrt v4.2s, v0.2s diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs new file mode 100644 index 0000000..77b089b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs @@ -0,0 +1,107 @@ +# CS_ARCH_ARM64, 0, None +0x00,0x70,0xc1,0x4c = ld1 {v0.16b}, [x0], x1 +0xef,0x75,0xc2,0x4c = ld1 {v15.8h}, [x15], x2 +0xff,0x7b,0xdf,0x4c = ld1 {v31.4s}, [sp], #16 +0x00,0x7c,0xdf,0x4c = ld1 {v0.2d}, [x0], #16 +0x00,0x70,0xc2,0x0c = ld1 {v0.8b}, [x0], x2 +0xef,0x75,0xc3,0x0c = ld1 {v15.4h}, [x15], x3 +0xff,0x7b,0xdf,0x0c = ld1 {v31.2s}, [sp], #8 +0x00,0x7c,0xdf,0x0c = ld1 {v0.1d}, [x0], #8 +0x00,0xa0,0xc1,0x4c = ld1 {v0.16b, v1.16b}, [x0], x1 +0xef,0xa5,0xc2,0x4c = ld1 {v15.8h, v16.8h}, [x15], x2 +0xff,0xab,0xdf,0x4c = ld1 {v31.4s, v0.4s}, [sp], #32 +0x00,0xac,0xdf,0x4c = ld1 {v0.2d, v1.2d}, [x0], #32 +0x00,0xa0,0xc2,0x0c = ld1 {v0.8b, v1.8b}, [x0], x2 +0xef,0xa5,0xc3,0x0c = ld1 {v15.4h, v16.4h}, [x15], x3 +0xff,0xab,0xdf,0x0c = ld1 {v31.2s, v0.2s}, [sp], #16 +0x00,0xac,0xdf,0x0c = ld1 {v0.1d, v1.1d}, [x0], #16 +0x00,0x60,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +0xef,0x65,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +0xff,0x6b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +0x00,0x6c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +0x00,0x60,0xc2,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +0xef,0x65,0xc3,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +0xff,0x6b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +0x00,0x6c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +0x00,0x20,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +0xef,0x25,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +0xff,0x2b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x2c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +0x00,0x20,0xc3,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x25,0xc4,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +0xff,0x2b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +0x00,0x2c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +0x00,0x80,0xc1,0x4c = ld2 {v0.16b, v1.16b}, [x0], x1 +0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2 +0xff,0x8b,0xdf,0x4c = ld2 {v31.4s, v0.4s}, [sp], #32 +0x00,0x8c,0xdf,0x4c = ld2 {v0.2d, v1.2d}, [x0], #32 +0x00,0x80,0xc2,0x0c = ld2 {v0.8b, v1.8b}, [x0], x2 +0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3 +0xff,0x8b,0xdf,0x0c = ld2 {v31.2s, v0.2s}, [sp], #16 +0x00,0x40,0xc1,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +0xff,0x4b,0xdf,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +0x00,0x4c,0xdf,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +0x00,0x40,0xc2,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +0xff,0x4b,0xdf,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +0x00,0x00,0xc1,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +0xef,0x05,0xc2,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +0xff,0x0b,0xdf,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x0c,0xdf,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +0x00,0x00,0xc3,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x05,0xc4,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +0xff,0x0b,0xdf,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +0x00,0x70,0x81,0x4c = st1 {v0.16b}, [x0], x1 +0xef,0x75,0x82,0x4c = st1 {v15.8h}, [x15], x2 +0xff,0x7b,0x9f,0x4c = st1 {v31.4s}, [sp], #16 +0x00,0x7c,0x9f,0x4c = st1 {v0.2d}, [x0], #16 +0x00,0x70,0x82,0x0c = st1 {v0.8b}, [x0], x2 +0xef,0x75,0x83,0x0c = st1 {v15.4h}, [x15], x3 +0xff,0x7b,0x9f,0x0c = st1 {v31.2s}, [sp], #8 +0x00,0x7c,0x9f,0x0c = st1 {v0.1d}, [x0], #8 +0x00,0xa0,0x81,0x4c = st1 {v0.16b, v1.16b}, [x0], x1 +0xef,0xa5,0x82,0x4c = st1 {v15.8h, v16.8h}, [x15], x2 +0xff,0xab,0x9f,0x4c = st1 {v31.4s, v0.4s}, [sp], #32 +0x00,0xac,0x9f,0x4c = st1 {v0.2d, v1.2d}, [x0], #32 +0x00,0xa0,0x82,0x0c = st1 {v0.8b, v1.8b}, [x0], x2 +0xef,0xa5,0x83,0x0c = st1 {v15.4h, v16.4h}, [x15], x3 +0xff,0xab,0x9f,0x0c = st1 {v31.2s, v0.2s}, [sp], #16 +0x00,0xac,0x9f,0x0c = st1 {v0.1d, v1.1d}, [x0], #16 +0x00,0x60,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +0xef,0x65,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +0xff,0x6b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +0x00,0x6c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +0x00,0x60,0x82,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +0xef,0x65,0x83,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +0xff,0x6b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +0x00,0x6c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +0x00,0x20,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +0xef,0x25,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +0xff,0x2b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x2c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +0x00,0x20,0x83,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x25,0x84,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +0xff,0x2b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +0x00,0x2c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +0x00,0x80,0x81,0x4c = st2 {v0.16b, v1.16b}, [x0], x1 +0xef,0x85,0x82,0x4c = st2 {v15.8h, v16.8h}, [x15], x2 +0xff,0x8b,0x9f,0x4c = st2 {v31.4s, v0.4s}, [sp], #32 +0x00,0x8c,0x9f,0x4c = st2 {v0.2d, v1.2d}, [x0], #32 +0x00,0x80,0x82,0x0c = st2 {v0.8b, v1.8b}, [x0], x2 +0xef,0x85,0x83,0x0c = st2 {v15.4h, v16.4h}, [x15], x3 +0xff,0x8b,0x9f,0x0c = st2 {v31.2s, v0.2s}, [sp], #16 +0x00,0x40,0x81,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +0xef,0x45,0x82,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +0xff,0x4b,0x9f,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +0x00,0x4c,0x9f,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +0x00,0x40,0x82,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +0xef,0x45,0x83,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +0xff,0x4b,0x9f,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +0x00,0x00,0x81,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +0xef,0x05,0x82,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +0xff,0x0b,0x9f,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x0c,0x9f,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +0x00,0x00,0x83,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x05,0x84,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +0xff,0x0b,0x9f,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-shift.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-shift.s.cs new file mode 100644 index 0000000..f8eac43 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-simd-shift.s.cs @@ -0,0 +1,151 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x04,0x0d,0x0f = sshr v0.8b, v1.8b, #3 +0x20,0x04,0x1d,0x0f = sshr v0.4h, v1.4h, #3 +0x20,0x04,0x3d,0x0f = sshr v0.2s, v1.2s, #3 +0x20,0x04,0x0d,0x4f = sshr v0.16b, v1.16b, #3 +0x20,0x04,0x1d,0x4f = sshr v0.8h, v1.8h, #3 +0x20,0x04,0x3d,0x4f = sshr v0.4s, v1.4s, #3 +0x20,0x04,0x7d,0x4f = sshr v0.2d, v1.2d, #3 +0x20,0x04,0x0d,0x2f = ushr v0.8b, v1.8b, #3 +0x20,0x04,0x1d,0x2f = ushr v0.4h, v1.4h, #3 +0x20,0x04,0x3d,0x2f = ushr v0.2s, v1.2s, #3 +0x20,0x04,0x0d,0x6f = ushr v0.16b, v1.16b, #3 +0x20,0x04,0x1d,0x6f = ushr v0.8h, v1.8h, #3 +0x20,0x04,0x3d,0x6f = ushr v0.4s, v1.4s, #3 +0x20,0x04,0x7d,0x6f = ushr v0.2d, v1.2d, #3 +0x20,0x14,0x0d,0x0f = ssra v0.8b, v1.8b, #3 +0x20,0x14,0x1d,0x0f = ssra v0.4h, v1.4h, #3 +0x20,0x14,0x3d,0x0f = ssra v0.2s, v1.2s, #3 +0x20,0x14,0x0d,0x4f = ssra v0.16b, v1.16b, #3 +0x20,0x14,0x1d,0x4f = ssra v0.8h, v1.8h, #3 +0x20,0x14,0x3d,0x4f = ssra v0.4s, v1.4s, #3 +0x20,0x14,0x7d,0x4f = ssra v0.2d, v1.2d, #3 +0x20,0x14,0x0d,0x2f = usra v0.8b, v1.8b, #3 +0x20,0x14,0x1d,0x2f = usra v0.4h, v1.4h, #3 +0x20,0x14,0x3d,0x2f = usra v0.2s, v1.2s, #3 +0x20,0x14,0x0d,0x6f = usra v0.16b, v1.16b, #3 +0x20,0x14,0x1d,0x6f = usra v0.8h, v1.8h, #3 +0x20,0x14,0x3d,0x6f = usra v0.4s, v1.4s, #3 +0x20,0x14,0x7d,0x6f = usra v0.2d, v1.2d, #3 +0x20,0x24,0x0d,0x0f = srshr v0.8b, v1.8b, #3 +0x20,0x24,0x1d,0x0f = srshr v0.4h, v1.4h, #3 +0x20,0x24,0x3d,0x0f = srshr v0.2s, v1.2s, #3 +0x20,0x24,0x0d,0x4f = srshr v0.16b, v1.16b, #3 +0x20,0x24,0x1d,0x4f = srshr v0.8h, v1.8h, #3 +0x20,0x24,0x3d,0x4f = srshr v0.4s, v1.4s, #3 +0x20,0x24,0x7d,0x4f = srshr v0.2d, v1.2d, #3 +0x20,0x24,0x0d,0x2f = urshr v0.8b, v1.8b, #3 +0x20,0x24,0x1d,0x2f = urshr v0.4h, v1.4h, #3 +0x20,0x24,0x3d,0x2f = urshr v0.2s, v1.2s, #3 +0x20,0x24,0x0d,0x6f = urshr v0.16b, v1.16b, #3 +0x20,0x24,0x1d,0x6f = urshr v0.8h, v1.8h, #3 +0x20,0x24,0x3d,0x6f = urshr v0.4s, v1.4s, #3 +0x20,0x24,0x7d,0x6f = urshr v0.2d, v1.2d, #3 +0x20,0x34,0x0d,0x0f = srsra v0.8b, v1.8b, #3 +0x20,0x34,0x1d,0x0f = srsra v0.4h, v1.4h, #3 +0x20,0x34,0x3d,0x0f = srsra v0.2s, v1.2s, #3 +0x20,0x34,0x0d,0x4f = srsra v0.16b, v1.16b, #3 +0x20,0x34,0x1d,0x4f = srsra v0.8h, v1.8h, #3 +0x20,0x34,0x3d,0x4f = srsra v0.4s, v1.4s, #3 +0x20,0x34,0x7d,0x4f = srsra v0.2d, v1.2d, #3 +0x20,0x34,0x0d,0x2f = ursra v0.8b, v1.8b, #3 +0x20,0x34,0x1d,0x2f = ursra v0.4h, v1.4h, #3 +0x20,0x34,0x3d,0x2f = ursra v0.2s, v1.2s, #3 +0x20,0x34,0x0d,0x6f = ursra v0.16b, v1.16b, #3 +0x20,0x34,0x1d,0x6f = ursra v0.8h, v1.8h, #3 +0x20,0x34,0x3d,0x6f = ursra v0.4s, v1.4s, #3 +0x20,0x34,0x7d,0x6f = ursra v0.2d, v1.2d, #3 +0x20,0x44,0x0d,0x2f = sri v0.8b, v1.8b, #3 +0x20,0x44,0x1d,0x2f = sri v0.4h, v1.4h, #3 +0x20,0x44,0x3d,0x2f = sri v0.2s, v1.2s, #3 +0x20,0x44,0x0d,0x6f = sri v0.16b, v1.16b, #3 +0x20,0x44,0x1d,0x6f = sri v0.8h, v1.8h, #3 +0x20,0x44,0x3d,0x6f = sri v0.4s, v1.4s, #3 +0x20,0x54,0x0b,0x2f = sli v0.8b, v1.8b, #3 +0x20,0x54,0x13,0x2f = sli v0.4h, v1.4h, #3 +0x20,0x54,0x23,0x2f = sli v0.2s, v1.2s, #3 +0x20,0x54,0x0b,0x6f = sli v0.16b, v1.16b, #3 +0x20,0x54,0x13,0x6f = sli v0.8h, v1.8h, #3 +0x20,0x54,0x23,0x6f = sli v0.4s, v1.4s, #3 +0x20,0x54,0x43,0x6f = sli v0.2d, v1.2d, #3 +0x20,0x64,0x0b,0x2f = sqshlu v0.8b, v1.8b, #3 +0x20,0x64,0x13,0x2f = sqshlu v0.4h, v1.4h, #3 +0x20,0x64,0x23,0x2f = sqshlu v0.2s, v1.2s, #3 +0x20,0x64,0x0b,0x6f = sqshlu v0.16b, v1.16b, #3 +0x20,0x64,0x13,0x6f = sqshlu v0.8h, v1.8h, #3 +0x20,0x64,0x23,0x6f = sqshlu v0.4s, v1.4s, #3 +0x20,0x64,0x43,0x6f = sqshlu v0.2d, v1.2d, #3 +0x20,0x74,0x0b,0x0f = sqshl v0.8b, v1.8b, #3 +0x20,0x74,0x13,0x0f = sqshl v0.4h, v1.4h, #3 +0x20,0x74,0x23,0x0f = sqshl v0.2s, v1.2s, #3 +0x20,0x74,0x0b,0x4f = sqshl v0.16b, v1.16b, #3 +0x20,0x74,0x13,0x4f = sqshl v0.8h, v1.8h, #3 +0x20,0x74,0x23,0x4f = sqshl v0.4s, v1.4s, #3 +0x20,0x74,0x43,0x4f = sqshl v0.2d, v1.2d, #3 +0x20,0x74,0x0b,0x2f = uqshl v0.8b, v1.8b, #3 +0x20,0x74,0x13,0x2f = uqshl v0.4h, v1.4h, #3 +0x20,0x74,0x23,0x2f = uqshl v0.2s, v1.2s, #3 +0x20,0x74,0x0b,0x6f = uqshl v0.16b, v1.16b, #3 +0x20,0x74,0x13,0x6f = uqshl v0.8h, v1.8h, #3 +0x20,0x74,0x23,0x6f = uqshl v0.4s, v1.4s, #3 +0x20,0x74,0x43,0x6f = uqshl v0.2d, v1.2d, #3 +0x20,0x84,0x0d,0x0f = shrn v0.8b, v1.8h, #3 +0x20,0x84,0x1d,0x0f = shrn v0.4h, v1.4s, #3 +0x20,0x84,0x3d,0x0f = shrn v0.2s, v1.2d, #3 +0x20,0x84,0x0d,0x4f = shrn2 v0.16b, v1.8h, #3 +0x20,0x84,0x1d,0x4f = shrn2 v0.8h, v1.4s, #3 +0x20,0x84,0x3d,0x4f = shrn2 v0.4s, v1.2d, #3 +0x20,0x84,0x0d,0x2f = sqshrun v0.8b, v1.8h, #3 +0x20,0x84,0x1d,0x2f = sqshrun v0.4h, v1.4s, #3 +0x20,0x84,0x3d,0x2f = sqshrun v0.2s, v1.2d, #3 +0x20,0x84,0x0d,0x6f = sqshrun2 v0.16b, v1.8h, #3 +0x20,0x84,0x1d,0x6f = sqshrun2 v0.8h, v1.4s, #3 +0x20,0x84,0x3d,0x6f = sqshrun2 v0.4s, v1.2d, #3 +0x20,0x8c,0x0d,0x0f = rshrn v0.8b, v1.8h, #3 +0x20,0x8c,0x1d,0x0f = rshrn v0.4h, v1.4s, #3 +0x20,0x8c,0x3d,0x0f = rshrn v0.2s, v1.2d, #3 +0x20,0x8c,0x0d,0x4f = rshrn2 v0.16b, v1.8h, #3 +0x20,0x8c,0x1d,0x4f = rshrn2 v0.8h, v1.4s, #3 +0x20,0x8c,0x3d,0x4f = rshrn2 v0.4s, v1.2d, #3 +0x20,0x8c,0x0d,0x2f = sqrshrun v0.8b, v1.8h, #3 +0x20,0x8c,0x1d,0x2f = sqrshrun v0.4h, v1.4s, #3 +0x20,0x8c,0x3d,0x2f = sqrshrun v0.2s, v1.2d, #3 +0x20,0x8c,0x0d,0x6f = sqrshrun2 v0.16b, v1.8h, #3 +0x20,0x8c,0x1d,0x6f = sqrshrun2 v0.8h, v1.4s, #3 +0x20,0x8c,0x3d,0x6f = sqrshrun2 v0.4s, v1.2d, #3 +0x20,0x94,0x0d,0x0f = sqshrn v0.8b, v1.8h, #3 +0x20,0x94,0x1d,0x0f = sqshrn v0.4h, v1.4s, #3 +0x20,0x94,0x3d,0x0f = sqshrn v0.2s, v1.2d, #3 +0x20,0x94,0x0d,0x4f = sqshrn2 v0.16b, v1.8h, #3 +0x20,0x94,0x1d,0x4f = sqshrn2 v0.8h, v1.4s, #3 +0x20,0x94,0x3d,0x4f = sqshrn2 v0.4s, v1.2d, #3 +0x20,0x94,0x0d,0x2f = uqshrn v0.8b, v1.8h, #3 +0x20,0x94,0x1d,0x2f = uqshrn v0.4h, v1.4s, #3 +0x20,0x94,0x3d,0x2f = uqshrn v0.2s, v1.2d, #3 +0x20,0x94,0x0d,0x6f = uqshrn2 v0.16b, v1.8h, #3 +0x20,0x94,0x1d,0x6f = uqshrn2 v0.8h, v1.4s, #3 +0x20,0x94,0x3d,0x6f = uqshrn2 v0.4s, v1.2d, #3 +0x20,0x9c,0x0d,0x0f = sqrshrn v0.8b, v1.8h, #3 +0x20,0x9c,0x1d,0x0f = sqrshrn v0.4h, v1.4s, #3 +0x20,0x9c,0x3d,0x0f = sqrshrn v0.2s, v1.2d, #3 +0x20,0x9c,0x0d,0x4f = sqrshrn2 v0.16b, v1.8h, #3 +0x20,0x9c,0x1d,0x4f = sqrshrn2 v0.8h, v1.4s, #3 +0x20,0x9c,0x3d,0x4f = sqrshrn2 v0.4s, v1.2d, #3 +0x20,0x9c,0x0d,0x2f = uqrshrn v0.8b, v1.8h, #3 +0x20,0x9c,0x1d,0x2f = uqrshrn v0.4h, v1.4s, #3 +0x20,0x9c,0x3d,0x2f = uqrshrn v0.2s, v1.2d, #3 +0x20,0x9c,0x0d,0x6f = uqrshrn2 v0.16b, v1.8h, #3 +0x20,0x9c,0x1d,0x6f = uqrshrn2 v0.8h, v1.4s, #3 +0x20,0x9c,0x3d,0x6f = uqrshrn2 v0.4s, v1.2d, #3 +0x20,0xe4,0x3d,0x0f = scvtf v0.2s, v1.2s, #3 +0x20,0xe4,0x3d,0x4f = scvtf v0.4s, v1.4s, #3 +0x20,0xe4,0x7d,0x4f = scvtf v0.2d, v1.2d, #3 +0x20,0xe4,0x3d,0x2f = ucvtf v0.2s, v1.2s, #3 +0x20,0xe4,0x3d,0x6f = ucvtf v0.4s, v1.4s, #3 +0x20,0xe4,0x7d,0x6f = ucvtf v0.2d, v1.2d, #3 +0x20,0xfc,0x3d,0x0f = fcvtzs v0.2s, v1.2s, #3 +0x20,0xfc,0x3d,0x4f = fcvtzs v0.4s, v1.4s, #3 +0x20,0xfc,0x7d,0x4f = fcvtzs v0.2d, v1.2d, #3 +0x20,0xfc,0x3d,0x2f = fcvtzu v0.2s, v1.2s, #3 +0x20,0xfc,0x3d,0x6f = fcvtzu v0.4s, v1.4s, #3 +0x20,0xfc,0x7d,0x6f = fcvtzu v0.2d, v1.2d, #3 diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/neon-tbl.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-tbl.s.cs new file mode 100644 index 0000000..e43cc32 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/neon-tbl.s.cs @@ -0,0 +1,21 @@ +# CS_ARCH_ARM64, 0, None +0x20,0x00,0x02,0x0e = tbl v0.8b, {v1.16b}, v2.8b +0x20,0x20,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b}, v2.8b +0x20,0x40,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +0x20,0x60,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b +0xe0,0x63,0x02,0x0e = tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b +0x20,0x00,0x02,0x4e = tbl v0.16b, {v1.16b}, v2.16b +0x20,0x20,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b}, v2.16b +0x20,0x40,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +0x20,0x60,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b +0xc0,0x63,0x02,0x4e = tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b +0x20,0x10,0x02,0x0e = tbx v0.8b, {v1.16b}, v2.8b +0x20,0x30,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b}, v2.8b +0x20,0x50,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +0x20,0x70,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b +0xe0,0x73,0x02,0x0e = tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b +0x20,0x10,0x02,0x4e = tbx v0.16b, {v1.16b}, v2.16b +0x20,0x30,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b}, v2.16b +0x20,0x50,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +0x20,0x70,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b +0xc0,0x73,0x02,0x4e = tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b diff --git a/white_patch_detect/capstone-master/suite/MC/AArch64/trace-regs.s.cs b/white_patch_detect/capstone-master/suite/MC/AArch64/trace-regs.s.cs new file mode 100644 index 0000000..dc91ecc --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/AArch64/trace-regs.s.cs @@ -0,0 +1,383 @@ +# CS_ARCH_ARM64, 0, None +0x08,0x03,0x31,0xd5 = mrs x8, trcstatr +0xc9,0x00,0x31,0xd5 = mrs x9, trcidr8 +0xcb,0x01,0x31,0xd5 = mrs x11, trcidr9 +0xd9,0x02,0x31,0xd5 = mrs x25, trcidr10 +0xc7,0x03,0x31,0xd5 = mrs x7, trcidr11 +0xc7,0x04,0x31,0xd5 = mrs x7, trcidr12 +0xc6,0x05,0x31,0xd5 = mrs x6, trcidr13 +0xfb,0x08,0x31,0xd5 = mrs x27, trcidr0 +0xfd,0x09,0x31,0xd5 = mrs x29, trcidr1 +0xe4,0x0a,0x31,0xd5 = mrs x4, trcidr2 +0xe8,0x0b,0x31,0xd5 = mrs x8, trcidr3 +0xef,0x0c,0x31,0xd5 = mrs x15, trcidr4 +0xf4,0x0d,0x31,0xd5 = mrs x20, trcidr5 +0xe6,0x0e,0x31,0xd5 = mrs x6, trcidr6 +0xe6,0x0f,0x31,0xd5 = mrs x6, trcidr7 +0x98,0x11,0x31,0xd5 = mrs x24, trcoslsr +0x92,0x15,0x31,0xd5 = mrs x18, trcpdsr +0xdc,0x7a,0x31,0xd5 = mrs x28, trcdevaff0 +0xc5,0x7b,0x31,0xd5 = mrs x5, trcdevaff1 +0xc5,0x7d,0x31,0xd5 = mrs x5, trclsr +0xcb,0x7e,0x31,0xd5 = mrs x11, trcauthstatus +0xcd,0x7f,0x31,0xd5 = mrs x13, trcdevarch +0xf2,0x72,0x31,0xd5 = mrs x18, trcdevid +0xf6,0x73,0x31,0xd5 = mrs x22, trcdevtype +0xee,0x74,0x31,0xd5 = mrs x14, trcpidr4 +0xe5,0x75,0x31,0xd5 = mrs x5, trcpidr5 +0xe5,0x76,0x31,0xd5 = mrs x5, trcpidr6 +0xe9,0x77,0x31,0xd5 = mrs x9, trcpidr7 +0xef,0x78,0x31,0xd5 = mrs x15, trcpidr0 +0xe6,0x79,0x31,0xd5 = mrs x6, trcpidr1 +0xeb,0x7a,0x31,0xd5 = mrs x11, trcpidr2 +0xf4,0x7b,0x31,0xd5 = mrs x20, trcpidr3 +0xf1,0x7c,0x31,0xd5 = mrs x17, trccidr0 +0xe2,0x7d,0x31,0xd5 = mrs x2, trccidr1 +0xf4,0x7e,0x31,0xd5 = mrs x20, trccidr2 +0xe4,0x7f,0x31,0xd5 = mrs x4, trccidr3 +0x0b,0x01,0x31,0xd5 = mrs x11, trcprgctlr +0x17,0x02,0x31,0xd5 = mrs x23, trcprocselr +0x0d,0x04,0x31,0xd5 = mrs x13, trcconfigr +0x17,0x06,0x31,0xd5 = mrs x23, trcauxctlr +0x09,0x08,0x31,0xd5 = mrs x9, trceventctl0r +0x10,0x09,0x31,0xd5 = mrs x16, trceventctl1r +0x04,0x0b,0x31,0xd5 = mrs x4, trcstallctlr +0x0e,0x0c,0x31,0xd5 = mrs x14, trctsctlr +0x18,0x0d,0x31,0xd5 = mrs x24, trcsyncpr +0x1c,0x0e,0x31,0xd5 = mrs x28, trcccctlr +0x0f,0x0f,0x31,0xd5 = mrs x15, trcbbctlr +0x21,0x00,0x31,0xd5 = mrs x1, trctraceidr +0x34,0x01,0x31,0xd5 = mrs x20, trcqctlr +0x42,0x00,0x31,0xd5 = mrs x2, trcvictlr +0x4c,0x01,0x31,0xd5 = mrs x12, trcviiectlr +0x50,0x02,0x31,0xd5 = mrs x16, trcvissctlr +0x48,0x03,0x31,0xd5 = mrs x8, trcvipcssctlr +0x5b,0x08,0x31,0xd5 = mrs x27, trcvdctlr +0x49,0x09,0x31,0xd5 = mrs x9, trcvdsacctlr +0x40,0x0a,0x31,0xd5 = mrs x0, trcvdarcctlr +0x8d,0x00,0x31,0xd5 = mrs x13, trcseqevr0 +0x8b,0x01,0x31,0xd5 = mrs x11, trcseqevr1 +0x9a,0x02,0x31,0xd5 = mrs x26, trcseqevr2 +0x8e,0x06,0x31,0xd5 = mrs x14, trcseqrstevr +0x84,0x07,0x31,0xd5 = mrs x4, trcseqstr +0x91,0x08,0x31,0xd5 = mrs x17, trcextinselr +0xb5,0x00,0x31,0xd5 = mrs x21, trccntrldvr0 +0xaa,0x01,0x31,0xd5 = mrs x10, trccntrldvr1 +0xb4,0x02,0x31,0xd5 = mrs x20, trccntrldvr2 +0xa5,0x03,0x31,0xd5 = mrs x5, trccntrldvr3 +0xb1,0x04,0x31,0xd5 = mrs x17, trccntctlr0 +0xa1,0x05,0x31,0xd5 = mrs x1, trccntctlr1 +0xb1,0x06,0x31,0xd5 = mrs x17, trccntctlr2 +0xa6,0x07,0x31,0xd5 = mrs x6, trccntctlr3 +0xbc,0x08,0x31,0xd5 = mrs x28, trccntvr0 +0xb7,0x09,0x31,0xd5 = mrs x23, trccntvr1 +0xa9,0x0a,0x31,0xd5 = mrs x9, trccntvr2 +0xa6,0x0b,0x31,0xd5 = mrs x6, trccntvr3 +0xf8,0x00,0x31,0xd5 = mrs x24, trcimspec0 +0xf8,0x01,0x31,0xd5 = mrs x24, trcimspec1 +0xef,0x02,0x31,0xd5 = mrs x15, trcimspec2 +0xea,0x03,0x31,0xd5 = mrs x10, trcimspec3 +0xfd,0x04,0x31,0xd5 = mrs x29, trcimspec4 +0xf2,0x05,0x31,0xd5 = mrs x18, trcimspec5 +0xfd,0x06,0x31,0xd5 = mrs x29, trcimspec6 +0xe2,0x07,0x31,0xd5 = mrs x2, trcimspec7 +0x08,0x12,0x31,0xd5 = mrs x8, trcrsctlr2 +0x00,0x13,0x31,0xd5 = mrs x0, trcrsctlr3 +0x0c,0x14,0x31,0xd5 = mrs x12, trcrsctlr4 +0x1a,0x15,0x31,0xd5 = mrs x26, trcrsctlr5 +0x1d,0x16,0x31,0xd5 = mrs x29, trcrsctlr6 +0x11,0x17,0x31,0xd5 = mrs x17, trcrsctlr7 +0x00,0x18,0x31,0xd5 = mrs x0, trcrsctlr8 +0x01,0x19,0x31,0xd5 = mrs x1, trcrsctlr9 +0x11,0x1a,0x31,0xd5 = mrs x17, trcrsctlr10 +0x15,0x1b,0x31,0xd5 = mrs x21, trcrsctlr11 +0x01,0x1c,0x31,0xd5 = mrs x1, trcrsctlr12 +0x08,0x1d,0x31,0xd5 = mrs x8, trcrsctlr13 +0x18,0x1e,0x31,0xd5 = mrs x24, trcrsctlr14 +0x00,0x1f,0x31,0xd5 = mrs x0, trcrsctlr15 +0x22,0x10,0x31,0xd5 = mrs x2, trcrsctlr16 +0x3d,0x11,0x31,0xd5 = mrs x29, trcrsctlr17 +0x36,0x12,0x31,0xd5 = mrs x22, trcrsctlr18 +0x26,0x13,0x31,0xd5 = mrs x6, trcrsctlr19 +0x3a,0x14,0x31,0xd5 = mrs x26, trcrsctlr20 +0x3a,0x15,0x31,0xd5 = mrs x26, trcrsctlr21 +0x24,0x16,0x31,0xd5 = mrs x4, trcrsctlr22 +0x2c,0x17,0x31,0xd5 = mrs x12, trcrsctlr23 +0x21,0x18,0x31,0xd5 = mrs x1, trcrsctlr24 +0x20,0x19,0x31,0xd5 = mrs x0, trcrsctlr25 +0x31,0x1a,0x31,0xd5 = mrs x17, trcrsctlr26 +0x28,0x1b,0x31,0xd5 = mrs x8, trcrsctlr27 +0x2a,0x1c,0x31,0xd5 = mrs x10, trcrsctlr28 +0x39,0x1d,0x31,0xd5 = mrs x25, trcrsctlr29 +0x2c,0x1e,0x31,0xd5 = mrs x12, trcrsctlr30 +0x2b,0x1f,0x31,0xd5 = mrs x11, trcrsctlr31 +0x52,0x10,0x31,0xd5 = mrs x18, trcssccr0 +0x4c,0x11,0x31,0xd5 = mrs x12, trcssccr1 +0x43,0x12,0x31,0xd5 = mrs x3, trcssccr2 +0x42,0x13,0x31,0xd5 = mrs x2, trcssccr3 +0x55,0x14,0x31,0xd5 = mrs x21, trcssccr4 +0x4a,0x15,0x31,0xd5 = mrs x10, trcssccr5 +0x56,0x16,0x31,0xd5 = mrs x22, trcssccr6 +0x57,0x17,0x31,0xd5 = mrs x23, trcssccr7 +0x57,0x18,0x31,0xd5 = mrs x23, trcsscsr0 +0x53,0x19,0x31,0xd5 = mrs x19, trcsscsr1 +0x59,0x1a,0x31,0xd5 = mrs x25, trcsscsr2 +0x51,0x1b,0x31,0xd5 = mrs x17, trcsscsr3 +0x53,0x1c,0x31,0xd5 = mrs x19, trcsscsr4 +0x4b,0x1d,0x31,0xd5 = mrs x11, trcsscsr5 +0x45,0x1e,0x31,0xd5 = mrs x5, trcsscsr6 +0x49,0x1f,0x31,0xd5 = mrs x9, trcsscsr7 +0x61,0x10,0x31,0xd5 = mrs x1, trcsspcicr0 +0x6c,0x11,0x31,0xd5 = mrs x12, trcsspcicr1 +0x75,0x12,0x31,0xd5 = mrs x21, trcsspcicr2 +0x6b,0x13,0x31,0xd5 = mrs x11, trcsspcicr3 +0x63,0x14,0x31,0xd5 = mrs x3, trcsspcicr4 +0x69,0x15,0x31,0xd5 = mrs x9, trcsspcicr5 +0x65,0x16,0x31,0xd5 = mrs x5, trcsspcicr6 +0x62,0x17,0x31,0xd5 = mrs x2, trcsspcicr7 +0x9a,0x14,0x31,0xd5 = mrs x26, trcpdcr +0x08,0x20,0x31,0xd5 = mrs x8, trcacvr0 +0x0f,0x22,0x31,0xd5 = mrs x15, trcacvr1 +0x13,0x24,0x31,0xd5 = mrs x19, trcacvr2 +0x08,0x26,0x31,0xd5 = mrs x8, trcacvr3 +0x1c,0x28,0x31,0xd5 = mrs x28, trcacvr4 +0x03,0x2a,0x31,0xd5 = mrs x3, trcacvr5 +0x19,0x2c,0x31,0xd5 = mrs x25, trcacvr6 +0x18,0x2e,0x31,0xd5 = mrs x24, trcacvr7 +0x26,0x20,0x31,0xd5 = mrs x6, trcacvr8 +0x23,0x22,0x31,0xd5 = mrs x3, trcacvr9 +0x38,0x24,0x31,0xd5 = mrs x24, trcacvr10 +0x23,0x26,0x31,0xd5 = mrs x3, trcacvr11 +0x2c,0x28,0x31,0xd5 = mrs x12, trcacvr12 +0x29,0x2a,0x31,0xd5 = mrs x9, trcacvr13 +0x2e,0x2c,0x31,0xd5 = mrs x14, trcacvr14 +0x23,0x2e,0x31,0xd5 = mrs x3, trcacvr15 +0x55,0x20,0x31,0xd5 = mrs x21, trcacatr0 +0x5a,0x22,0x31,0xd5 = mrs x26, trcacatr1 +0x48,0x24,0x31,0xd5 = mrs x8, trcacatr2 +0x56,0x26,0x31,0xd5 = mrs x22, trcacatr3 +0x46,0x28,0x31,0xd5 = mrs x6, trcacatr4 +0x5d,0x2a,0x31,0xd5 = mrs x29, trcacatr5 +0x45,0x2c,0x31,0xd5 = mrs x5, trcacatr6 +0x52,0x2e,0x31,0xd5 = mrs x18, trcacatr7 +0x62,0x20,0x31,0xd5 = mrs x2, trcacatr8 +0x73,0x22,0x31,0xd5 = mrs x19, trcacatr9 +0x6d,0x24,0x31,0xd5 = mrs x13, trcacatr10 +0x79,0x26,0x31,0xd5 = mrs x25, trcacatr11 +0x72,0x28,0x31,0xd5 = mrs x18, trcacatr12 +0x7d,0x2a,0x31,0xd5 = mrs x29, trcacatr13 +0x69,0x2c,0x31,0xd5 = mrs x9, trcacatr14 +0x72,0x2e,0x31,0xd5 = mrs x18, trcacatr15 +0x9d,0x20,0x31,0xd5 = mrs x29, trcdvcvr0 +0x8f,0x24,0x31,0xd5 = mrs x15, trcdvcvr1 +0x8f,0x28,0x31,0xd5 = mrs x15, trcdvcvr2 +0x8f,0x2c,0x31,0xd5 = mrs x15, trcdvcvr3 +0xb3,0x20,0x31,0xd5 = mrs x19, trcdvcvr4 +0xb6,0x24,0x31,0xd5 = mrs x22, trcdvcvr5 +0xbb,0x28,0x31,0xd5 = mrs x27, trcdvcvr6 +0xa1,0x2c,0x31,0xd5 = mrs x1, trcdvcvr7 +0xdd,0x20,0x31,0xd5 = mrs x29, trcdvcmr0 +0xc9,0x24,0x31,0xd5 = mrs x9, trcdvcmr1 +0xc1,0x28,0x31,0xd5 = mrs x1, trcdvcmr2 +0xc2,0x2c,0x31,0xd5 = mrs x2, trcdvcmr3 +0xe5,0x20,0x31,0xd5 = mrs x5, trcdvcmr4 +0xf5,0x24,0x31,0xd5 = mrs x21, trcdvcmr5 +0xe5,0x28,0x31,0xd5 = mrs x5, trcdvcmr6 +0xe1,0x2c,0x31,0xd5 = mrs x1, trcdvcmr7 +0x15,0x30,0x31,0xd5 = mrs x21, trccidcvr0 +0x18,0x32,0x31,0xd5 = mrs x24, trccidcvr1 +0x18,0x34,0x31,0xd5 = mrs x24, trccidcvr2 +0x0c,0x36,0x31,0xd5 = mrs x12, trccidcvr3 +0x0a,0x38,0x31,0xd5 = mrs x10, trccidcvr4 +0x09,0x3a,0x31,0xd5 = mrs x9, trccidcvr5 +0x06,0x3c,0x31,0xd5 = mrs x6, trccidcvr6 +0x14,0x3e,0x31,0xd5 = mrs x20, trccidcvr7 +0x34,0x30,0x31,0xd5 = mrs x20, trcvmidcvr0 +0x34,0x32,0x31,0xd5 = mrs x20, trcvmidcvr1 +0x3a,0x34,0x31,0xd5 = mrs x26, trcvmidcvr2 +0x21,0x36,0x31,0xd5 = mrs x1, trcvmidcvr3 +0x2e,0x38,0x31,0xd5 = mrs x14, trcvmidcvr4 +0x3b,0x3a,0x31,0xd5 = mrs x27, trcvmidcvr5 +0x3d,0x3c,0x31,0xd5 = mrs x29, trcvmidcvr6 +0x31,0x3e,0x31,0xd5 = mrs x17, trcvmidcvr7 +0x4a,0x30,0x31,0xd5 = mrs x10, trccidcctlr0 +0x44,0x31,0x31,0xd5 = mrs x4, trccidcctlr1 +0x49,0x32,0x31,0xd5 = mrs x9, trcvmidcctlr0 +0x4b,0x33,0x31,0xd5 = mrs x11, trcvmidcctlr1 +0x96,0x70,0x31,0xd5 = mrs x22, trcitctrl +0xd7,0x78,0x31,0xd5 = mrs x23, trcclaimset +0xce,0x79,0x31,0xd5 = mrs x14, trcclaimclr +0x9c,0x10,0x11,0xd5 = msr trcoslar, x28 +0xce,0x7c,0x11,0xd5 = msr trclar, x14 +0x0a,0x01,0x11,0xd5 = msr trcprgctlr, x10 +0x1b,0x02,0x11,0xd5 = msr trcprocselr, x27 +0x18,0x04,0x11,0xd5 = msr trcconfigr, x24 +0x08,0x06,0x11,0xd5 = msr trcauxctlr, x8 +0x10,0x08,0x11,0xd5 = msr trceventctl0r, x16 +0x1b,0x09,0x11,0xd5 = msr trceventctl1r, x27 +0x1a,0x0b,0x11,0xd5 = msr trcstallctlr, x26 +0x00,0x0c,0x11,0xd5 = msr trctsctlr, x0 +0x0e,0x0d,0x11,0xd5 = msr trcsyncpr, x14 +0x08,0x0e,0x11,0xd5 = msr trcccctlr, x8 +0x06,0x0f,0x11,0xd5 = msr trcbbctlr, x6 +0x37,0x00,0x11,0xd5 = msr trctraceidr, x23 +0x25,0x01,0x11,0xd5 = msr trcqctlr, x5 +0x40,0x00,0x11,0xd5 = msr trcvictlr, x0 +0x40,0x01,0x11,0xd5 = msr trcviiectlr, x0 +0x41,0x02,0x11,0xd5 = msr trcvissctlr, x1 +0x40,0x03,0x11,0xd5 = msr trcvipcssctlr, x0 +0x47,0x08,0x11,0xd5 = msr trcvdctlr, x7 +0x52,0x09,0x11,0xd5 = msr trcvdsacctlr, x18 +0x58,0x0a,0x11,0xd5 = msr trcvdarcctlr, x24 +0x9c,0x00,0x11,0xd5 = msr trcseqevr0, x28 +0x95,0x01,0x11,0xd5 = msr trcseqevr1, x21 +0x90,0x02,0x11,0xd5 = msr trcseqevr2, x16 +0x90,0x06,0x11,0xd5 = msr trcseqrstevr, x16 +0x99,0x07,0x11,0xd5 = msr trcseqstr, x25 +0x9d,0x08,0x11,0xd5 = msr trcextinselr, x29 +0xb4,0x00,0x11,0xd5 = msr trccntrldvr0, x20 +0xb4,0x01,0x11,0xd5 = msr trccntrldvr1, x20 +0xb6,0x02,0x11,0xd5 = msr trccntrldvr2, x22 +0xac,0x03,0x11,0xd5 = msr trccntrldvr3, x12 +0xb4,0x04,0x11,0xd5 = msr trccntctlr0, x20 +0xa4,0x05,0x11,0xd5 = msr trccntctlr1, x4 +0xa8,0x06,0x11,0xd5 = msr trccntctlr2, x8 +0xb0,0x07,0x11,0xd5 = msr trccntctlr3, x16 +0xa5,0x08,0x11,0xd5 = msr trccntvr0, x5 +0xbb,0x09,0x11,0xd5 = msr trccntvr1, x27 +0xb5,0x0a,0x11,0xd5 = msr trccntvr2, x21 +0xa8,0x0b,0x11,0xd5 = msr trccntvr3, x8 +0xe6,0x00,0x11,0xd5 = msr trcimspec0, x6 +0xfb,0x01,0x11,0xd5 = msr trcimspec1, x27 +0xf7,0x02,0x11,0xd5 = msr trcimspec2, x23 +0xef,0x03,0x11,0xd5 = msr trcimspec3, x15 +0xed,0x04,0x11,0xd5 = msr trcimspec4, x13 +0xf9,0x05,0x11,0xd5 = msr trcimspec5, x25 +0xf3,0x06,0x11,0xd5 = msr trcimspec6, x19 +0xfb,0x07,0x11,0xd5 = msr trcimspec7, x27 +0x04,0x12,0x11,0xd5 = msr trcrsctlr2, x4 +0x00,0x13,0x11,0xd5 = msr trcrsctlr3, x0 +0x15,0x14,0x11,0xd5 = msr trcrsctlr4, x21 +0x08,0x15,0x11,0xd5 = msr trcrsctlr5, x8 +0x14,0x16,0x11,0xd5 = msr trcrsctlr6, x20 +0x0b,0x17,0x11,0xd5 = msr trcrsctlr7, x11 +0x12,0x18,0x11,0xd5 = msr trcrsctlr8, x18 +0x18,0x19,0x11,0xd5 = msr trcrsctlr9, x24 +0x0f,0x1a,0x11,0xd5 = msr trcrsctlr10, x15 +0x15,0x1b,0x11,0xd5 = msr trcrsctlr11, x21 +0x04,0x1c,0x11,0xd5 = msr trcrsctlr12, x4 +0x1c,0x1d,0x11,0xd5 = msr trcrsctlr13, x28 +0x03,0x1e,0x11,0xd5 = msr trcrsctlr14, x3 +0x14,0x1f,0x11,0xd5 = msr trcrsctlr15, x20 +0x2c,0x10,0x11,0xd5 = msr trcrsctlr16, x12 +0x31,0x11,0x11,0xd5 = msr trcrsctlr17, x17 +0x2a,0x12,0x11,0xd5 = msr trcrsctlr18, x10 +0x2b,0x13,0x11,0xd5 = msr trcrsctlr19, x11 +0x23,0x14,0x11,0xd5 = msr trcrsctlr20, x3 +0x32,0x15,0x11,0xd5 = msr trcrsctlr21, x18 +0x3a,0x16,0x11,0xd5 = msr trcrsctlr22, x26 +0x25,0x17,0x11,0xd5 = msr trcrsctlr23, x5 +0x39,0x18,0x11,0xd5 = msr trcrsctlr24, x25 +0x25,0x19,0x11,0xd5 = msr trcrsctlr25, x5 +0x24,0x1a,0x11,0xd5 = msr trcrsctlr26, x4 +0x34,0x1b,0x11,0xd5 = msr trcrsctlr27, x20 +0x25,0x1c,0x11,0xd5 = msr trcrsctlr28, x5 +0x2a,0x1d,0x11,0xd5 = msr trcrsctlr29, x10 +0x38,0x1e,0x11,0xd5 = msr trcrsctlr30, x24 +0x34,0x1f,0x11,0xd5 = msr trcrsctlr31, x20 +0x57,0x10,0x11,0xd5 = msr trcssccr0, x23 +0x5b,0x11,0x11,0xd5 = msr trcssccr1, x27 +0x5b,0x12,0x11,0xd5 = msr trcssccr2, x27 +0x46,0x13,0x11,0xd5 = msr trcssccr3, x6 +0x43,0x14,0x11,0xd5 = msr trcssccr4, x3 +0x4c,0x15,0x11,0xd5 = msr trcssccr5, x12 +0x47,0x16,0x11,0xd5 = msr trcssccr6, x7 +0x46,0x17,0x11,0xd5 = msr trcssccr7, x6 +0x54,0x18,0x11,0xd5 = msr trcsscsr0, x20 +0x51,0x19,0x11,0xd5 = msr trcsscsr1, x17 +0x4b,0x1a,0x11,0xd5 = msr trcsscsr2, x11 +0x44,0x1b,0x11,0xd5 = msr trcsscsr3, x4 +0x4e,0x1c,0x11,0xd5 = msr trcsscsr4, x14 +0x56,0x1d,0x11,0xd5 = msr trcsscsr5, x22 +0x43,0x1e,0x11,0xd5 = msr trcsscsr6, x3 +0x4b,0x1f,0x11,0xd5 = msr trcsscsr7, x11 +0x62,0x10,0x11,0xd5 = msr trcsspcicr0, x2 +0x63,0x11,0x11,0xd5 = msr trcsspcicr1, x3 +0x65,0x12,0x11,0xd5 = msr trcsspcicr2, x5 +0x67,0x13,0x11,0xd5 = msr trcsspcicr3, x7 +0x6b,0x14,0x11,0xd5 = msr trcsspcicr4, x11 +0x6d,0x15,0x11,0xd5 = msr trcsspcicr5, x13 +0x71,0x16,0x11,0xd5 = msr trcsspcicr6, x17 +0x77,0x17,0x11,0xd5 = msr trcsspcicr7, x23 +0x83,0x14,0x11,0xd5 = msr trcpdcr, x3 +0x06,0x20,0x11,0xd5 = msr trcacvr0, x6 +0x14,0x22,0x11,0xd5 = msr trcacvr1, x20 +0x19,0x24,0x11,0xd5 = msr trcacvr2, x25 +0x01,0x26,0x11,0xd5 = msr trcacvr3, x1 +0x1c,0x28,0x11,0xd5 = msr trcacvr4, x28 +0x0f,0x2a,0x11,0xd5 = msr trcacvr5, x15 +0x19,0x2c,0x11,0xd5 = msr trcacvr6, x25 +0x0c,0x2e,0x11,0xd5 = msr trcacvr7, x12 +0x25,0x20,0x11,0xd5 = msr trcacvr8, x5 +0x39,0x22,0x11,0xd5 = msr trcacvr9, x25 +0x2d,0x24,0x11,0xd5 = msr trcacvr10, x13 +0x2a,0x26,0x11,0xd5 = msr trcacvr11, x10 +0x33,0x28,0x11,0xd5 = msr trcacvr12, x19 +0x2a,0x2a,0x11,0xd5 = msr trcacvr13, x10 +0x33,0x2c,0x11,0xd5 = msr trcacvr14, x19 +0x22,0x2e,0x11,0xd5 = msr trcacvr15, x2 +0x4f,0x20,0x11,0xd5 = msr trcacatr0, x15 +0x4d,0x22,0x11,0xd5 = msr trcacatr1, x13 +0x48,0x24,0x11,0xd5 = msr trcacatr2, x8 +0x41,0x26,0x11,0xd5 = msr trcacatr3, x1 +0x4b,0x28,0x11,0xd5 = msr trcacatr4, x11 +0x48,0x2a,0x11,0xd5 = msr trcacatr5, x8 +0x58,0x2c,0x11,0xd5 = msr trcacatr6, x24 +0x46,0x2e,0x11,0xd5 = msr trcacatr7, x6 +0x77,0x20,0x11,0xd5 = msr trcacatr8, x23 +0x65,0x22,0x11,0xd5 = msr trcacatr9, x5 +0x6b,0x24,0x11,0xd5 = msr trcacatr10, x11 +0x6b,0x26,0x11,0xd5 = msr trcacatr11, x11 +0x63,0x28,0x11,0xd5 = msr trcacatr12, x3 +0x7c,0x2a,0x11,0xd5 = msr trcacatr13, x28 +0x79,0x2c,0x11,0xd5 = msr trcacatr14, x25 +0x64,0x2e,0x11,0xd5 = msr trcacatr15, x4 +0x86,0x20,0x11,0xd5 = msr trcdvcvr0, x6 +0x83,0x24,0x11,0xd5 = msr trcdvcvr1, x3 +0x85,0x28,0x11,0xd5 = msr trcdvcvr2, x5 +0x8b,0x2c,0x11,0xd5 = msr trcdvcvr3, x11 +0xa9,0x20,0x11,0xd5 = msr trcdvcvr4, x9 +0xae,0x24,0x11,0xd5 = msr trcdvcvr5, x14 +0xaa,0x28,0x11,0xd5 = msr trcdvcvr6, x10 +0xac,0x2c,0x11,0xd5 = msr trcdvcvr7, x12 +0xc8,0x20,0x11,0xd5 = msr trcdvcmr0, x8 +0xc8,0x24,0x11,0xd5 = msr trcdvcmr1, x8 +0xd6,0x28,0x11,0xd5 = msr trcdvcmr2, x22 +0xd6,0x2c,0x11,0xd5 = msr trcdvcmr3, x22 +0xe5,0x20,0x11,0xd5 = msr trcdvcmr4, x5 +0xf0,0x24,0x11,0xd5 = msr trcdvcmr5, x16 +0xfb,0x28,0x11,0xd5 = msr trcdvcmr6, x27 +0xf5,0x2c,0x11,0xd5 = msr trcdvcmr7, x21 +0x08,0x30,0x11,0xd5 = msr trccidcvr0, x8 +0x06,0x32,0x11,0xd5 = msr trccidcvr1, x6 +0x09,0x34,0x11,0xd5 = msr trccidcvr2, x9 +0x08,0x36,0x11,0xd5 = msr trccidcvr3, x8 +0x03,0x38,0x11,0xd5 = msr trccidcvr4, x3 +0x15,0x3a,0x11,0xd5 = msr trccidcvr5, x21 +0x0c,0x3c,0x11,0xd5 = msr trccidcvr6, x12 +0x07,0x3e,0x11,0xd5 = msr trccidcvr7, x7 +0x24,0x30,0x11,0xd5 = msr trcvmidcvr0, x4 +0x23,0x32,0x11,0xd5 = msr trcvmidcvr1, x3 +0x29,0x34,0x11,0xd5 = msr trcvmidcvr2, x9 +0x31,0x36,0x11,0xd5 = msr trcvmidcvr3, x17 +0x2e,0x38,0x11,0xd5 = msr trcvmidcvr4, x14 +0x2c,0x3a,0x11,0xd5 = msr trcvmidcvr5, x12 +0x2a,0x3c,0x11,0xd5 = msr trcvmidcvr6, x10 +0x23,0x3e,0x11,0xd5 = msr trcvmidcvr7, x3 +0x4e,0x30,0x11,0xd5 = msr trccidcctlr0, x14 +0x56,0x31,0x11,0xd5 = msr trccidcctlr1, x22 +0x48,0x32,0x11,0xd5 = msr trcvmidcctlr0, x8 +0x4f,0x33,0x11,0xd5 = msr trcvmidcctlr1, x15 +0x81,0x70,0x11,0xd5 = msr trcitctrl, x1 +0xc7,0x78,0x11,0xd5 = msr trcclaimset, x7 +0xdd,0x79,0x11,0xd5 = msr trcclaimclr, x29 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/hilo-addressing.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/hilo-addressing.s.cs new file mode 100644 index 0000000..2d99128 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/hilo-addressing.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +// 0x3c,0x04,0xde,0xae = lui $a0, %hi(addr) +0x03,0xe0,0x00,0x08 = jr $ra +// 0x80,0x82,0xbe,0xef = lb $v0, %lo(addr)($a0) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions-EB.s.cs new file mode 100644 index 0000000..f4dbe7a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions-EB.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None +0x00,0xe6,0x49,0x10 = add $t1, $a2, $a3 +0x11,0x26,0x45,0x67 = addi $t1, $a2, 17767 +0x31,0x26,0xc5,0x67 = addiu $t1, $a2, -15001 +0x11,0x26,0x45,0x67 = addi $t1, $a2, 17767 +0x31,0x26,0xc5,0x67 = addiu $t1, $a2, -15001 +0x00,0xe6,0x49,0x50 = addu $t1, $a2, $a3 +0x00,0xe6,0x49,0x90 = sub $t1, $a2, $a3 +0x00,0xa3,0x21,0xd0 = subu $a0, $v1, $a1 +0x00,0xe0,0x31,0x90 = sub $a2, $zero, $a3 +0x00,0xe0,0x31,0xd0 = subu $a2, $zero, $a3 +0x00,0x08,0x39,0x50 = addu $a3, $t0, $zero +0x00,0xa3,0x1b,0x50 = slt $v1, $v1, $a1 +0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 +0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 +0xb0,0x63,0x00,0x67 = sltiu $v1, $v1, 103 +0x00,0xa3,0x1b,0x90 = sltu $v1, $v1, $a1 +0x41,0xa9,0x45,0x67 = lui $t1, 17767 +0x00,0xe6,0x4a,0x50 = and $t1, $a2, $a3 +0xd1,0x26,0x45,0x67 = andi $t1, $a2, 17767 +0xd1,0x26,0x45,0x67 = andi $t1, $a2, 17767 +0x00,0xa4,0x1a,0x90 = or $v1, $a0, $a1 +0x51,0x26,0x45,0x67 = ori $t1, $a2, 17767 +0x00,0xa3,0x1b,0x10 = xor $v1, $v1, $a1 +0x71,0x26,0x45,0x67 = xori $t1, $a2, 17767 +0x71,0x26,0x45,0x67 = xori $t1, $a2, 17767 +0x00,0xe6,0x4a,0xd0 = nor $t1, $a2, $a3 +0x00,0x08,0x3a,0xd0 = not $a3, $t0 +0x00,0xe6,0x4a,0x10 = mul $t1, $a2, $a3 +0x00,0xe9,0x8b,0x3c = mult $t1, $a3 +0x00,0xe9,0x9b,0x3c = multu $t1, $a3 +0x00,0xe9,0xab,0x3c = div $zero, $t1, $a3 +0x00,0xe9,0xbb,0x3c = divu $zero, $t1, $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions.s.cs new file mode 100644 index 0000000..81fe643 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-alu-instructions.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0xe6,0x00,0x10,0x49 = add $t1, $a2, $a3 +0x26,0x11,0x67,0x45 = addi $t1, $a2, 17767 +0x26,0x31,0x67,0xc5 = addiu $t1, $a2, -15001 +0x26,0x11,0x67,0x45 = addi $t1, $a2, 17767 +0x26,0x31,0x67,0xc5 = addiu $t1, $a2, -15001 +0xe6,0x00,0x50,0x49 = addu $t1, $a2, $a3 +0xe6,0x00,0x90,0x49 = sub $t1, $a2, $a3 +0xa3,0x00,0xd0,0x21 = subu $a0, $v1, $a1 +0xe0,0x00,0x90,0x31 = sub $a2, $zero, $a3 +0xe0,0x00,0xd0,0x31 = subu $a2, $zero, $a3 +0x08,0x00,0x50,0x39 = addu $a3, $t0, $zero +0xa3,0x00,0x50,0x1b = slt $v1, $v1, $a1 +0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 +0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 +0x63,0xb0,0x67,0x00 = sltiu $v1, $v1, 103 +0xa3,0x00,0x90,0x1b = sltu $v1, $v1, $a1 +0xa9,0x41,0x67,0x45 = lui $t1, 17767 +0xe6,0x00,0x50,0x4a = and $t1, $a2, $a3 +0x26,0xd1,0x67,0x45 = andi $t1, $a2, 17767 +0x26,0xd1,0x67,0x45 = andi $t1, $a2, 17767 +0xa4,0x00,0x90,0x1a = or $v1, $a0, $a1 +0x26,0x51,0x67,0x45 = ori $t1, $a2, 17767 +0xa3,0x00,0x10,0x1b = xor $v1, $v1, $a1 +0x26,0x71,0x67,0x45 = xori $t1, $a2, 17767 +0x26,0x71,0x67,0x45 = xori $t1, $a2, 17767 +0xe6,0x00,0xd0,0x4a = nor $t1, $a2, $a3 +0x08,0x00,0xd0,0x3a = not $a3, $t0 +0xe6,0x00,0x10,0x4a = mul $t1, $a2, $a3 +0xe9,0x00,0x3c,0x8b = mult $t1, $a3 +0xe9,0x00,0x3c,0x9b = multu $t1, $a3 +0xe9,0x00,0x3c,0xab = div $zero, $t1, $a3 +0xe9,0x00,0x3c,0xbb = divu $zero, $t1, $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions-EB.s.cs new file mode 100644 index 0000000..947ea25 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions-EB.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x94,0x00,0x02,0x9a = b 1332 +0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332 +0x40,0x46,0x02,0x9a = bgez $a2, 1332 +0x40,0x66,0x02,0x9a = bgezal $a2, 1332 +0x40,0x26,0x02,0x9a = bltzal $a2, 1332 +0x40,0xc6,0x02,0x9a = bgtz $a2, 1332 +0x40,0x86,0x02,0x9a = blez $a2, 1332 +0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332 +// 0x40,0x60,0x02,0x9a = bal 1332 +0x40,0x06,0x02,0x9a = bltz $a2, 1332 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions.s.cs new file mode 100644 index 0000000..286bc0d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-branch-instructions.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0x00,0x94,0x9a,0x02 = b 1332 +0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332 +0x46,0x40,0x9a,0x02 = bgez $a2, 1332 +0x66,0x40,0x9a,0x02 = bgezal $a2, 1332 +0x26,0x40,0x9a,0x02 = bltzal $a2, 1332 +0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332 +0x86,0x40,0x9a,0x02 = blez $a2, 1332 +0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332 +// 0x60,0x40,0x9a,0x02 = bal 1332 +0x06,0x40,0x9a,0x02 = bltz $a2, 1332 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-expansions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-expansions.s.cs new file mode 100644 index 0000000..b16331b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-expansions.s.cs @@ -0,0 +1,20 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123 +0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345 +0xa7,0x41,0x01,0x00 = lui $a3, 1 +0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 +0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20 +0xa7,0x41,0x01,0x00 = lui $a3, 1 +0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 +0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20 +0xa7,0x41,0x01,0x00 = lui $a3, 1 +0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 +0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0 +0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 +0x21,0x01,0x50,0x09 = addu $at, $at, $t1 +0xaa,0x41,0x0a,0x00 = lui $t2, 10 +0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 +0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2) +0xa1,0x41,0x02,0x00 = lui $at, 2 +0x21,0x01,0x50,0x09 = addu $at, $at, $t1 +// 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions-EB.s.cs new file mode 100644 index 0000000..7f9ee60 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions-EB.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0xd4,0x00,0x02,0x98 = j 1328 +0xf4,0x00,0x02,0x98 = jal 1328 +// 0x03,0xe6,0x0f,0x3c = jalr $a2 +0x00,0x07,0x0f,0x3c = jr $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions.s.cs new file mode 100644 index 0000000..b23d8d7 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-jump-instructions.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0x00,0xd4,0x98,0x02 = j 1328 +0x00,0xf4,0x98,0x02 = jal 1328 +// 0xe6,0x03,0x3c,0x0f = jalr $a2 +0x07,0x00,0x3c,0x0f = jr $a3 +0x07,0x00,0x3c,0x0f = jr $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs new file mode 100644 index 0000000..57958f4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x1c,0xa4,0x00,0x08 = lb $a1, 8($a0) +0x14,0xc4,0x00,0x08 = lbu $a2, 8($a0) +0x3c,0x44,0x00,0x08 = lh $v0, 8($a0) +0x34,0x82,0x00,0x08 = lhu $a0, 8($v0) +0xfc,0xc5,0x00,0x04 = lw $a2, 4($a1) +0x18,0xa4,0x00,0x08 = sb $a1, 8($a0) +0x38,0x44,0x00,0x08 = sh $v0, 8($a0) +0xf8,0xa6,0x00,0x04 = sw $a1, 4($a2) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions.s.cs new file mode 100644 index 0000000..561c819 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-instructions.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0xa4,0x1c,0x08,0x00 = lb $a1, 8($a0) +0xc4,0x14,0x08,0x00 = lbu $a2, 8($a0) +0x44,0x3c,0x08,0x00 = lh $v0, 8($a0) +0x82,0x34,0x08,0x00 = lhu $a0, 8($v0) +0xc5,0xfc,0x04,0x00 = lw $a2, 4($a1) +0xa4,0x18,0x08,0x00 = sb $a1, 8($a0) +0x44,0x38,0x08,0x00 = sh $v0, 8($a0) +0xa6,0xf8,0x04,0x00 = sw $a1, 4($a2) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs new file mode 100644 index 0000000..9e2a3ae --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x60,0x85,0x00,0x10 = lwl $a0, 16($a1) +0x60,0x85,0x10,0x10 = lwr $a0, 16($a1) +0x60,0x85,0x80,0x10 = swl $a0, 16($a1) +0x60,0x85,0x90,0x10 = swr $a0, 16($a1) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned.s.cs new file mode 100644 index 0000000..855b4dd --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-loadstore-unaligned.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0x85,0x60,0x10,0x00 = lwl $a0, 16($a1) +0x85,0x60,0x10,0x10 = lwr $a0, 16($a1) +0x85,0x60,0x10,0x80 = swl $a0, 16($a1) +0x85,0x60,0x10,0x90 = swr $a0, 16($a1) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs new file mode 100644 index 0000000..4351e68 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x00,0xe6,0x48,0x58 = movz $t1, $a2, $a3 +0x00,0xe6,0x48,0x18 = movn $t1, $a2, $a3 +0x55,0x26,0x09,0x7b = movt $t1, $a2, $fcc0 +0x55,0x26,0x01,0x7b = movf $t1, $a2, $fcc0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions.s.cs new file mode 100644 index 0000000..b64cdd2 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-movcond-instructions.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0xe6,0x00,0x58,0x48 = movz $t1, $a2, $a3 +0xe6,0x00,0x18,0x48 = movn $t1, $a2, $a3 +0x26,0x55,0x7b,0x09 = movt $t1, $a2, $fcc0 +0x26,0x55,0x7b,0x01 = movf $t1, $a2, $fcc0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs new file mode 100644 index 0000000..f04522a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x00,0xa4,0xcb,0x3c = madd $a0, $a1 +0x00,0xa4,0xdb,0x3c = maddu $a0, $a1 +0x00,0xa4,0xeb,0x3c = msub $a0, $a1 +0x00,0xa4,0xfb,0x3c = msubu $a0, $a1 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions.s.cs new file mode 100644 index 0000000..30adb5a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-multiply-instructions.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0xa4,0x00,0x3c,0xcb = madd $a0, $a1 +0xa4,0x00,0x3c,0xdb = maddu $a0, $a1 +0xa4,0x00,0x3c,0xeb = msub $a0, $a1 +0xa4,0x00,0x3c,0xfb = msubu $a0, $a1 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions-EB.s.cs new file mode 100644 index 0000000..d09bee0 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions-EB.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +0x00,0x83,0x38,0x00 = sll $a0, $v1, 7 +0x00,0x65,0x10,0x10 = sllv $v0, $v1, $a1 +0x00,0x83,0x38,0x80 = sra $a0, $v1, 7 +0x00,0x65,0x10,0x90 = srav $v0, $v1, $a1 +0x00,0x83,0x38,0x40 = srl $a0, $v1, 7 +0x00,0x65,0x10,0x50 = srlv $v0, $v1, $a1 +0x01,0x26,0x38,0xc0 = rotr $t1, $a2, 7 +0x00,0xc7,0x48,0xd0 = rotrv $t1, $a2, $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions.s.cs new file mode 100644 index 0000000..3353e91 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-shift-instructions.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +0x83,0x00,0x00,0x38 = sll $a0, $v1, 7 +0x65,0x00,0x10,0x10 = sllv $v0, $v1, $a1 +0x83,0x00,0x80,0x38 = sra $a0, $v1, 7 +0x65,0x00,0x90,0x10 = srav $v0, $v1, $a1 +0x83,0x00,0x40,0x38 = srl $a0, $v1, 7 +0x65,0x00,0x50,0x10 = srlv $v0, $v1, $a1 +0x26,0x01,0xc0,0x38 = rotr $t1, $a2, 7 +0xc7,0x00,0xd0,0x48 = rotrv $t1, $a2, $a3 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions-EB.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions-EB.s.cs new file mode 100644 index 0000000..385db92 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions-EB.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None +// 0x01,0x28,0x00,0x3c = teq $t0, $t1 +// 0x01,0x28,0x02,0x3c = tge $t0, $t1 +// 0x01,0x28,0x04,0x3c = tgeu $t0, $t1 +// 0x01,0x28,0x08,0x3c = tlt $t0, $t1 +// 0x01,0x28,0x0a,0x3c = tltu $t0, $t1 +// 0x01,0x28,0x0c,0x3c = tne $t0, $t1 +0x41,0xc9,0x45,0x67 = teqi $t1, 17767 +0x41,0x29,0x45,0x67 = tgei $t1, 17767 +0x41,0x69,0x45,0x67 = tgeiu $t1, 17767 +0x41,0x09,0x45,0x67 = tlti $t1, 17767 +0x41,0x49,0x45,0x67 = tltiu $t1, 17767 +0x41,0x89,0x45,0x67 = tnei $t1, 17767 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions.s.cs new file mode 100644 index 0000000..814f8da --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/micromips-trap-instructions.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None +// 0x28,0x01,0x3c,0x00 = teq $t0, $t1 +// 0x28,0x01,0x3c,0x02 = tge $t0, $t1 +// 0x28,0x01,0x3c,0x04 = tgeu $t0, $t1 +// 0x28,0x01,0x3c,0x08 = tlt $t0, $t1 +// 0x28,0x01,0x3c,0x0a = tltu $t0, $t1 +// 0x28,0x01,0x3c,0x0c = tne $t0, $t1 +0xc9,0x41,0x67,0x45 = teqi $t1, 17767 +0x29,0x41,0x67,0x45 = tgei $t1, 17767 +0x69,0x41,0x67,0x45 = tgeiu $t1, 17767 +0x09,0x41,0x67,0x45 = tlti $t1, 17767 +0x49,0x41,0x67,0x45 = tltiu $t1, 17767 +0x89,0x41,0x67,0x45 = tnei $t1, 17767 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-alu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-alu-instructions.s.cs new file mode 100644 index 0000000..1ee3337 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-alu-instructions.s.cs @@ -0,0 +1,53 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None +0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 +0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 +0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 +0x67,0x45,0x29,0x31 = andi $t1, $t1, 17767 +0x21,0x30,0xe6,0x70 = clo $a2, $a3 +0x20,0x30,0xe6,0x70 = clz $a2, $a3 +0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 +0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 +0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 +0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 +0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 +0x80,0x00,0x6b,0x35 = ori $t3, $t3, 128 +0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 +0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 +0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 +0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 +0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 +0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 +0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 +0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 +0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 +0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 +0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 +0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 +0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 +0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 +0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 +0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 +0x0c,0x00,0x6b,0x39 = xori $t3, $t3, 12 +0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 +0x27,0x38,0x00,0x01 = not $a3, $t0 +0x20,0x48,0xc7,0x00 = add $t1, $a2, $a3 +0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 +0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 +0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 +0x67,0x45,0x29,0x21 = addi $t1, $t1, 17767 +0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 +0x28,0x00,0x6b,0x25 = addiu $t3, $t3, 40 +0x21,0x48,0xc7,0x00 = addu $t1, $a2, $a3 +0x00,0x00,0xc7,0x70 = madd $a2, $a3 +0x01,0x00,0xc7,0x70 = maddu $a2, $a3 +0x04,0x00,0xc7,0x70 = msub $a2, $a3 +0x05,0x00,0xc7,0x70 = msubu $a2, $a3 +0x18,0x00,0x65,0x00 = mult $v1, $a1 +0x19,0x00,0x65,0x00 = multu $v1, $a1 +0x22,0x48,0xc7,0x00 = sub $t1, $a2, $a3 +0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56 +0x23,0x20,0x65,0x00 = subu $a0, $v1, $a1 +0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40 +0x22,0x30,0x07,0x00 = neg $a2, $a3 +0x23,0x30,0x07,0x00 = negu $a2, $a3 +0x21,0x38,0x00,0x01 = move $a3, $t0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions-64.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions-64.s.cs new file mode 100644 index 0000000..c3478da --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions-64.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x00,0x00,0x00,0x0d = break +// 0x00,0x07,0x00,0x0d = break 7, 0 +0x00,0x07,0x01,0x4d = break 7, 5 +0x00,0x00,0x00,0x0c = syscall +0x00,0x0d,0x15,0x0c = syscall 13396 +0x42,0x00,0x00,0x18 = eret +0x42,0x00,0x00,0x1f = deret +0x41,0x60,0x60,0x00 = di +0x41,0x60,0x60,0x00 = di +0x41,0x6a,0x60,0x00 = di $t2 +0x41,0x60,0x60,0x20 = ei +0x41,0x60,0x60,0x20 = ei +0x41,0x6a,0x60,0x20 = ei $t2 +0x42,0x00,0x00,0x20 = wait +0x00,0x03,0x00,0x34 = teq $zero, $v1 +0x00,0x03,0x00,0x74 = teq $zero, $v1, 1 +0x04,0x6c,0x00,0x01 = teqi $v1, 1 +0x00,0x03,0x00,0x30 = tge $zero, $v1 +0x00,0x03,0x00,0xf0 = tge $zero, $v1, 3 +0x04,0x68,0x00,0x03 = tgei $v1, 3 +0x00,0x03,0x00,0x31 = tgeu $zero, $v1 +0x00,0x03,0x01,0xf1 = tgeu $zero, $v1, 7 +0x04,0x69,0x00,0x07 = tgeiu $v1, 7 +0x00,0x03,0x00,0x32 = tlt $zero, $v1 +0x00,0x03,0x07,0xf2 = tlt $zero, $v1, 31 +0x04,0x6a,0x00,0x1f = tlti $v1, 31 +0x00,0x03,0x00,0x33 = tltu $zero, $v1 +0x00,0x03,0x3f,0xf3 = tltu $zero, $v1, 255 +0x04,0x6b,0x00,0xff = tltiu $v1, 255 +0x00,0x03,0x00,0x36 = tne $zero, $v1 +0x00,0x03,0xff,0xf6 = tne $zero, $v1, 1023 +0x04,0x6e,0x03,0xff = tnei $v1, 1023 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions.s.cs new file mode 100644 index 0000000..86c4ad8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-control-instructions.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x00,0x00,0x00,0x0d = break +// 0x00,0x07,0x00,0x0d = break 7, 0 +0x00,0x07,0x01,0x4d = break 7, 5 +0x00,0x00,0x00,0x0c = syscall +0x00,0x0d,0x15,0x0c = syscall 13396 +0x42,0x00,0x00,0x18 = eret +0x42,0x00,0x00,0x1f = deret +0x41,0x60,0x60,0x00 = di +0x41,0x60,0x60,0x00 = di +0x41,0x6a,0x60,0x00 = di $t2 +0x41,0x60,0x60,0x20 = ei +0x41,0x60,0x60,0x20 = ei +0x41,0x6a,0x60,0x20 = ei $t2 +0x42,0x00,0x00,0x20 = wait +0x00,0x03,0x00,0x34 = teq $zero, $v1 +0x00,0x03,0x00,0x74 = teq $zero, $v1, 1 +0x04,0x6c,0x00,0x01 = teqi $v1, 1 +0x00,0x03,0x00,0x30 = tge $zero, $v1 +0x00,0x03,0x00,0xf0 = tge $zero, $v1, 3 +0x04,0x68,0x00,0x03 = tgei $v1, 3 +0x00,0x03,0x00,0x31 = tgeu $zero, $v1 +0x00,0x03,0x01,0xf1 = tgeu $zero, $v1, 7 +0x04,0x69,0x00,0x07 = tgeiu $v1, 7 +0x00,0x03,0x00,0x32 = tlt $zero, $v1 +0x00,0x03,0x07,0xf2 = tlt $zero, $v1, 31 +0x04,0x6a,0x00,0x1f = tlti $v1, 31 +0x00,0x03,0x00,0x33 = tltu $zero, $v1 +0x00,0x03,0x3f,0xf3 = tltu $zero, $v1, 255 +0x04,0x6b,0x00,0xff = tltiu $v1, 255 +0x00,0x03,0x00,0x36 = tne $zero, $v1 +0x00,0x03,0xff,0xf6 = tne $zero, $v1, 1023 +0x04,0x6e,0x03,0xff = tnei $v1, 1023 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-coprocessor-encodings.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-coprocessor-encodings.s.cs new file mode 100644 index 0000000..d14ddc3 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-coprocessor-encodings.s.cs @@ -0,0 +1,17 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2 +0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0 +0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2 +0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0 +0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2 +0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0 +0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2 +0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0 +0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2 +0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0 +0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2 +0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0 +0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2 +0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0 +0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2 +0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-dsp-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-dsp-instructions.s.cs new file mode 100644 index 0000000..ec15295 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-dsp-instructions.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x7e,0x32,0x83,0x11 = precrq.qb.ph $s0, $s1, $s2 +0x7e,0x53,0x8d,0x11 = precrq.ph.w $s1, $s2, $s3 +0x7e,0x74,0x95,0x51 = precrq_rs.ph.w $s2, $s3, $s4 +0x7e,0x95,0x9b,0xd1 = precrqu_s.qb.ph $s3, $s4, $s5 +0x7c,0x15,0xa3,0x12 = preceq.w.phl $s4, $s5 +0x7c,0x16,0xab,0x52 = preceq.w.phr $s5, $s6 +0x7c,0x17,0xb1,0x12 = precequ.ph.qbl $s6, $s7 +0x7c,0x18,0xb9,0x52 = precequ.ph.qbr $s7, $t8 +0x7c,0x19,0xc1,0x92 = precequ.ph.qbla $t8, $t9 +0x7c,0x1a,0xc9,0xd2 = precequ.ph.qbra $t9, $k0 +0x7c,0x1b,0xd7,0x12 = preceu.ph.qbl $k0, $k1 +0x7c,0x1c,0xdf,0x52 = preceu.ph.qbr $k1, $gp +0x7c,0x1d,0xe7,0x92 = preceu.ph.qbla $gp, $sp +0x7c,0x1e,0xef,0xd2 = preceu.ph.qbra $sp, $fp +0x7f,0x19,0xbb,0x51 = precr.qb.ph $s7, $t8, $t9 +0x7f,0x38,0x07,0x91 = precr_sra.ph.w $t8, $t9, 0 +0x7f,0x38,0xff,0x91 = precr_sra.ph.w $t8, $t9, 31 +0x7f,0x59,0x07,0xd1 = precr_sra_r.ph.w $t9, $k0, 0 +0x7f,0x59,0xff,0xd1 = precr_sra_r.ph.w $t9, $k0, 31 +0x7f,0x54,0x51,0x8a = lbux $t2, $s4($k0) +0x7f,0x75,0x59,0x0a = lhx $t3, $s5($k1) +0x7f,0x96,0x60,0x0a = lwx $t4, $s6($gp) +0x00,0x43,0x18,0x18 = mult $ac3, $v0, $v1 +0x00,0x85,0x10,0x19 = multu $ac2, $a0, $a1 +0x70,0xc7,0x08,0x00 = madd $ac1, $a2, $a3 +// 0x71,0x09,0x00,0x01 = maddu $ac0, $t0, $t1 +0x71,0x4b,0x18,0x04 = msub $ac3, $t2, $t3 +0x71,0x8d,0x10,0x05 = msubu $ac2, $t4, $t5 +0x00,0x20,0x70,0x10 = mfhi $t6, $ac1 +// 0x00,0x00,0x78,0x12 = mflo $t7, $ac0 +0x02,0x00,0x18,0x11 = mthi $s0, $ac3 +0x02,0x20,0x10,0x13 = mtlo $s1, $ac2 +0x00,0x43,0x00,0x18 = mult $v0, $v1 +0x00,0x85,0x00,0x19 = multu $a0, $a1 +0x70,0xc7,0x00,0x00 = madd $a2, $a3 +// 0x71,0x09,0x00,0x01 = maddu $t0, $t1 +0x71,0x4b,0x00,0x04 = msub $t2, $t3 +0x71,0x8d,0x00,0x05 = msubu $t4, $t5 +0x00,0x00,0x70,0x10 = mfhi $t6 +// 0x00,0x00,0x78,0x12 = mflo $t7 +0x02,0x00,0x00,0x11 = mthi $s0 +0x02,0x20,0x00,0x13 = mtlo $s1 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-expansions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-expansions.s.cs new file mode 100644 index 0000000..2aeca0c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-expansions.s.cs @@ -0,0 +1,19 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None +0x7b,0x00,0x05,0x34 = ori $a1, $zero, 123 +0xd7,0xf6,0x06,0x24 = addiu $a2, $zero, -2345 +0x01,0x00,0x07,0x3c = lui $a3, 1 +0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 +0x14,0x00,0x04,0x24 = addiu $a0, $zero, 20 +0x01,0x00,0x07,0x3c = lui $a3, 1 +0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 +0x14,0x00,0xa4,0x24 = addiu $a0, $a1, 20 +0x01,0x00,0x07,0x3c = lui $a3, 1 +0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 +0x21,0x38,0xe8,0x00 = addu $a3, $a3, $t0 +0x21,0x50,0x44,0x01 = addu $t2, $t2, $a0 +0x21,0x08,0x29,0x00 = addu $at, $at, $t1 +0x0a,0x00,0x0a,0x3c = lui $t2, 10 +0x7b,0x00,0x4a,0x8d = lw $t2, 123($t2) +0x02,0x00,0x01,0x3c = lui $at, 2 +0x21,0x08,0x29,0x00 = addu $at, $at, $t1 +// 0x40,0xe2,0x2a,0xac = sw $t2, 57920($at) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-fpu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-fpu-instructions.s.cs new file mode 100644 index 0000000..335cd0f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-fpu-instructions.s.cs @@ -0,0 +1,93 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None +0x05,0x73,0x20,0x46 = abs.d $f12, $f14 +0x85,0x39,0x00,0x46 = abs.s $f6, $f7 +0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14 +0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7 +0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14 +0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7 +0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14 +0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7 +0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14 +0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7 +0x07,0x73,0x20,0x46 = neg.d $f12, $f14 +0x87,0x39,0x00,0x46 = neg.s $f6, $f7 +0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14 +0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7 +0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14 +0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7 +0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14 +0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7 +0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14 +0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7 +0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14 +0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7 +0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14 +0x30,0x30,0x07,0x46 = c.f.s $f6, $f7 +0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14 +0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7 +0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14 +0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7 +0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14 +0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7 +0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14 +0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7 +0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14 +0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7 +0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14 +0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7 +0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14 +0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7 +0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14 +0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7 +0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14 +0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7 +0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14 +0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7 +0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14 +0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18 +0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14 +0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7 +0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14 +0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7 +0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14 +0x31,0x30,0x07,0x46 = c.un.s $f6, $f7 +0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7 +0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14 +0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14 +0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7 +0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14 +0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7 +0x00,0x00,0x46,0x44 = cfc1 $a2, $0 +0x00,0xf8,0xca,0x44 = ctc1 $t2, $31 +0x00,0x38,0x06,0x44 = mfc1 $a2, $f7 +0x10,0x28,0x00,0x00 = mfhi $a1 +0x12,0x28,0x00,0x00 = mflo $a1 +0x86,0x41,0x20,0x46 = mov.d $f6, $f8 +0x86,0x39,0x00,0x46 = mov.s $f6, $f7 +0x00,0x38,0x86,0x44 = mtc1 $a2, $f7 +0x11,0x00,0xe0,0x00 = mthi $a3 +0x13,0x00,0xe0,0x00 = mtlo $a3 +0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($a3) +0x00,0x38,0x06,0x40 = mfc0 $a2, $a3, 0 +0x00,0x40,0x89,0x40 = mtc0 $t1, $t0, 0 +0x00,0x38,0x05,0x48 = mfc2 $a1, $a3, 0 +0x00,0x20,0x89,0x48 = mtc2 $t1, $a0, 0 +0x02,0x38,0x06,0x40 = mfc0 $a2, $a3, 2 +0x03,0x40,0x89,0x40 = mtc0 $t1, $t0, 3 +0x04,0x38,0x05,0x48 = mfc2 $a1, $a3, 4 +0x05,0x20,0x89,0x48 = mtc2 $t1, $a0, 5 +0x01,0x10,0x20,0x00 = movf $v0, $at, $fcc0 +0x01,0x10,0x21,0x00 = movt $v0, $at, $fcc0 +0x01,0x20,0xb1,0x00 = movt $a0, $a1, $fcc4 +0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2 +0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5 +0x05,0x00,0xa6,0x4c = luxc1 $f0, $a2($a1) +0x0d,0x20,0xb8,0x4c = suxc1 $f4, $t8($a1) +0x00,0x05,0xcc,0x4d = lwxc1 $f20, $t4($t6) +0x08,0xd0,0xd2,0x4e = swxc1 $f26, $s2($s6) +0x00,0x20,0x71,0x44 = mfhc1 $s1, $f4 +0x00,0x30,0xf1,0x44 = mthc1 $s1, $f6 +0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp) +0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp) +0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra) +0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-jump-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-jump-instructions.s.cs new file mode 100644 index 0000000..5e741fc --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-jump-instructions.s.cs @@ -0,0 +1 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-memory-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-memory-instructions.s.cs new file mode 100644 index 0000000..ac5b360 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-memory-instructions.s.cs @@ -0,0 +1,17 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None +0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1) +0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1) +0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1) +0x10,0x00,0xa4,0xac = sw $a0, 16($a1) +0x00,0x00,0xa7,0xac = sw $a3, ($a1) +0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1) +0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1) +0x04,0x00,0xa4,0x80 = lb $a0, 4($a1) +0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) +0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1) +0x04,0x00,0xa4,0x84 = lh $a0, 4($a1) +0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1) +0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1) +0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) +0x00,0x00,0xe7,0x8c = lw $a3, ($a3) +0x10,0x00,0xa2,0x8f = lw $v0, 16($sp) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips-register-names.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips-register-names.s.cs new file mode 100644 index 0000000..fb7cd89 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips-register-names.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x24,0x00,0x00,0x00 = addiu $zero, $zero, 0 +0x24,0x01,0x00,0x00 = addiu $at, $zero, 0 +0x24,0x02,0x00,0x00 = addiu $v0, $zero, 0 +0x24,0x03,0x00,0x00 = addiu $v1, $zero, 0 +0x24,0x04,0x00,0x00 = addiu $a0, $zero, 0 +0x24,0x05,0x00,0x00 = addiu $a1, $zero, 0 +0x24,0x06,0x00,0x00 = addiu $a2, $zero, 0 +0x24,0x07,0x00,0x00 = addiu $a3, $zero, 0 +0x24,0x08,0x00,0x00 = addiu $t0, $zero, 0 +0x24,0x09,0x00,0x00 = addiu $t1, $zero, 0 +0x24,0x0a,0x00,0x00 = addiu $t2, $zero, 0 +0x24,0x0b,0x00,0x00 = addiu $t3, $zero, 0 +0x24,0x0c,0x00,0x00 = addiu $t4, $zero, 0 +0x24,0x0d,0x00,0x00 = addiu $t5, $zero, 0 +0x24,0x0e,0x00,0x00 = addiu $t6, $zero, 0 +0x24,0x0f,0x00,0x00 = addiu $t7, $zero, 0 +0x24,0x10,0x00,0x00 = addiu $s0, $zero, 0 +0x24,0x11,0x00,0x00 = addiu $s1, $zero, 0 +0x24,0x12,0x00,0x00 = addiu $s2, $zero, 0 +0x24,0x13,0x00,0x00 = addiu $s3, $zero, 0 +0x24,0x14,0x00,0x00 = addiu $s4, $zero, 0 +0x24,0x15,0x00,0x00 = addiu $s5, $zero, 0 +0x24,0x16,0x00,0x00 = addiu $s6, $zero, 0 +0x24,0x17,0x00,0x00 = addiu $s7, $zero, 0 +0x24,0x18,0x00,0x00 = addiu $t8, $zero, 0 +0x24,0x19,0x00,0x00 = addiu $t9, $zero, 0 +0x24,0x1a,0x00,0x00 = addiu $k0, $zero, 0 +0x24,0x1b,0x00,0x00 = addiu $k1, $zero, 0 +0x24,0x1c,0x00,0x00 = addiu $gp, $zero, 0 +0x24,0x1d,0x00,0x00 = addiu $sp, $zero, 0 +0x24,0x1e,0x00,0x00 = addiu $fp, $zero, 0 +// 0x24,0x1f,0x00,0x00 = addiu $sp, $zero, 0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips64-alu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-alu-instructions.s.cs new file mode 100644 index 0000000..eeac44e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-alu-instructions.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64, None +0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 +0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 +0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 +0x21,0x30,0xe6,0x70 = clo $a2, $a3 +0x20,0x30,0xe6,0x70 = clz $a2, $a3 +0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 +0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 +0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 +0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 +0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 +0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 +0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 +0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 +0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 +0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 +0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 +0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 +0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 +0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 +0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 +0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 +0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 +0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 +0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 +0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 +0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 +0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 +0x27,0x38,0x00,0x01 = not $a3, $t0 +0x2c,0x48,0xc7,0x00 = dadd $t1, $a2, $a3 +0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 +0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 +0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 +0x67,0x45,0x29,0x61 = daddi $t1, $t1, 17767 +0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 +0x67,0xc5,0x29,0x65 = daddiu $t1, $t1, -15001 +0x2d,0x48,0xc7,0x00 = daddu $t1, $a2, $a3 +0x3a,0x4d,0x26,0x00 = drotr $t1, $a2, 20 +// 0x3e,0x4d,0x26,0x00 = drotr32 $t1, $a2, 52 +0x00,0x00,0xc7,0x70 = madd $a2, $a3 +0x01,0x00,0xc7,0x70 = maddu $a2, $a3 +0x04,0x00,0xc7,0x70 = msub $a2, $a3 +0x05,0x00,0xc7,0x70 = msubu $a2, $a3 +0x18,0x00,0x65,0x00 = mult $v1, $a1 +0x19,0x00,0x65,0x00 = multu $v1, $a1 +0x2f,0x20,0x65,0x00 = dsubu $a0, $v1, $a1 +0x2d,0x38,0x00,0x01 = move $a3, $t0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips64-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-instructions.s.cs new file mode 100644 index 0000000..be7cc23 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-instructions.s.cs @@ -0,0 +1,3 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64, None +0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2) +0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips64-register-names.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-register-names.s.cs new file mode 100644 index 0000000..24f59f8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips64-register-names.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x64,0x00,0x00,0x00 = daddiu $zero, $zero, 0 +0x64,0x01,0x00,0x00 = daddiu $at, $zero, 0 +0x64,0x02,0x00,0x00 = daddiu $v0, $zero, 0 +0x64,0x03,0x00,0x00 = daddiu $v1, $zero, 0 +0x64,0x04,0x00,0x00 = daddiu $a0, $zero, 0 +0x64,0x05,0x00,0x00 = daddiu $a1, $zero, 0 +0x64,0x06,0x00,0x00 = daddiu $a2, $zero, 0 +// 0x64,0x07,0x00,0x00 = daddiu $a2, $zero, 0 +// 0x64,0x08,0x00,0x00 = daddiu $a4, $zero, 0 +// 0x64,0x09,0x00,0x00 = daddiu $a5, $zero, 0 +// 0x64,0x0a,0x00,0x00 = daddiu $a6, $zero, 0 +// 0x64,0x0b,0x00,0x00 = daddiu $a7, $zero, 0 +0x64,0x0c,0x00,0x00 = daddiu $t4, $zero, 0 +0x64,0x0d,0x00,0x00 = daddiu $t5, $zero, 0 +0x64,0x0e,0x00,0x00 = daddiu $t6, $zero, 0 +0x64,0x0f,0x00,0x00 = daddiu $t7, $zero, 0 +0x64,0x10,0x00,0x00 = daddiu $s0, $zero, 0 +0x64,0x11,0x00,0x00 = daddiu $s1, $zero, 0 +0x64,0x12,0x00,0x00 = daddiu $s2, $zero, 0 +0x64,0x13,0x00,0x00 = daddiu $s3, $zero, 0 +0x64,0x14,0x00,0x00 = daddiu $s4, $zero, 0 +0x64,0x15,0x00,0x00 = daddiu $s5, $zero, 0 +0x64,0x16,0x00,0x00 = daddiu $s6, $zero, 0 +0x64,0x17,0x00,0x00 = daddiu $s7, $zero, 0 +0x64,0x18,0x00,0x00 = daddiu $t8, $zero, 0 +0x64,0x19,0x00,0x00 = daddiu $t9, $zero, 0 +// 0x64,0x1a,0x00,0x00 = daddiu $kt0, $zero, 0 +// 0x64,0x1b,0x00,0x00 = daddiu $kt1, $zero, 0 +0x64,0x1c,0x00,0x00 = daddiu $gp, $zero, 0 +0x64,0x1d,0x00,0x00 = daddiu $sp, $zero, 0 +// 0x64,0x1e,0x00,0x00 = daddiu $s8, $zero, 0 +0x64,0x1f,0x00,0x00 = daddiu $ra, $zero, 0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/mips_directives.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/mips_directives.s.cs new file mode 100644 index 0000000..07d10c9 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/mips_directives.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x10,0x00,0x01,0x4d = b 1336 +0x08,0x00,0x01,0x4c = j 1328 +0x0c,0x00,0x01,0x4c = jal 1328 +0x10,0x00,0x01,0x4d = b 1336 +0x00,0x00,0x00,0x00 = nop +0x08,0x00,0x01,0x4c = j 1328 +0x00,0x00,0x00,0x00 = nop +0x0c,0x00,0x01,0x4c = jal 1328 +0x00,0x00,0x00,0x00 = nop +0x46,0x00,0x39,0x85 = abs.s $f6, $f7 +0x01,0xef,0x18,0x24 = and $v1, $t7, $t7 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/nabi-regs.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/nabi-regs.s.cs new file mode 100644 index 0000000..0d14e29 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/nabi-regs.s.cs @@ -0,0 +1,12 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None +0x02,0x04,0x80,0x20 = add $s0, $s0, $a0 +0x02,0x06,0x80,0x20 = add $s0, $s0, $a2 +0x02,0x07,0x80,0x20 = add $s0, $s0, $a3 +0x02,0x08,0x80,0x20 = add $s0, $s0, $t0 +0x02,0x09,0x80,0x20 = add $s0, $s0, $t1 +0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2 +0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3 +0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4 +0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5 +0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6 +0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/set-at-directive.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/set-at-directive.s.cs new file mode 100644 index 0000000..f01a43a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/set-at-directive.s.cs @@ -0,0 +1,6 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32, None +0x08,0x00,0x60,0x00 = jr $v1 +0x08,0x00,0x80,0x03 = jr $gp +0x08,0x00,0xc0,0x03 = jr $fp +0x08,0x00,0xa0,0x03 = jr $sp +0x08,0x00,0xe0,0x03 = jr $ra diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_2r.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_2r.s.cs new file mode 100644 index 0000000..94b37bc --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_2r.s.cs @@ -0,0 +1,16 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1 +0x7b,0x01,0xbf,0xde = fill.h $w31, $s7 +0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8 +0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 +0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 +0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 +0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 +0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 +0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 +0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 +0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 +0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 +0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 +0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 +0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_2rf.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_2rf.s.cs new file mode 100644 index 0000000..2e95606 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_2rf.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12 +0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17 +0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0 +0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29 +0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4 +0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2 +0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29 +0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15 +0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27 +0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16 +0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13 +0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13 +0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30 +0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15 +0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31 +0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10 +0x7b,0x2c,0x79,0xde = frint.w $w7, $w15 +0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22 +0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0 +0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14 +0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17 +0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11 +0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11 +0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12 +0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5 +0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23 +0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14 +0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21 +0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17 +0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27 +0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15 +0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_3r.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_3r.s.cs new file mode 100644 index 0000000..99f5de9 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_3r.s.cs @@ -0,0 +1,243 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4 +0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31 +0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22 +0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0 +0x78,0x93,0xc4,0xd0 = adds_a.b $w19, $w24, $w19 +0x78,0xa4,0x36,0x50 = adds_a.h $w25, $w6, $w4 +0x78,0xdb,0x8e,0x50 = adds_a.w $w25, $w17, $w27 +0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26 +0x79,0x13,0x5f,0x50 = adds_s.b $w29, $w11, $w19 +0x79,0x3a,0xb9,0x50 = adds_s.h $w5, $w23, $w26 +0x79,0x4d,0x74,0x10 = adds_s.w $w16, $w14, $w13 +0x79,0x7c,0x70,0x90 = adds_s.d $w2, $w14, $w28 +0x79,0x8e,0x88,0xd0 = adds_u.b $w3, $w17, $w14 +0x79,0xa4,0xf2,0x90 = adds_u.h $w10, $w30, $w4 +0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20 +0x79,0xe9,0x57,0x90 = adds_u.d $w30, $w10, $w9 +0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21 +0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27 +0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14 +0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31 +0x7a,0x03,0x85,0xd1 = asub_s.b $w23, $w16, $w3 +0x7a,0x39,0x8d,0x91 = asub_s.h $w22, $w17, $w25 +0x7a,0x49,0x0e,0x11 = asub_s.w $w24, $w1, $w9 +0x7a,0x6c,0x63,0x51 = asub_s.d $w13, $w12, $w12 +0x7a,0x8b,0xea,0x91 = asub_u.b $w10, $w29, $w11 +0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15 +0x7a,0xdf,0x9a,0x91 = asub_u.w $w10, $w19, $w31 +0x7a,0xe0,0x54,0x51 = asub_u.d $w17, $w10, $w0 +0x7a,0x01,0x28,0x90 = ave_s.b $w2, $w5, $w1 +0x7a,0x29,0x9c,0x10 = ave_s.h $w16, $w19, $w9 +0x7a,0x45,0xfc,0x50 = ave_s.w $w17, $w31, $w5 +0x7a,0x6a,0xce,0xd0 = ave_s.d $w27, $w25, $w10 +0x7a,0x89,0x9c,0x10 = ave_u.b $w16, $w19, $w9 +0x7a,0xab,0xe7,0x10 = ave_u.h $w28, $w28, $w11 +0x7a,0xcb,0x62,0xd0 = ave_u.w $w11, $w12, $w11 +0x7a,0xfc,0x9f,0x90 = ave_u.d $w30, $w19, $w28 +0x7b,0x02,0x86,0x90 = aver_s.b $w26, $w16, $w2 +0x7b,0x3b,0xdf,0xd0 = aver_s.h $w31, $w27, $w27 +0x7b,0x59,0x97,0x10 = aver_s.w $w28, $w18, $w25 +0x7b,0x7b,0xaf,0x50 = aver_s.d $w29, $w21, $w27 +0x7b,0x83,0xd7,0x50 = aver_u.b $w29, $w26, $w3 +0x7b,0xa9,0x94,0x90 = aver_u.h $w18, $w18, $w9 +0x7b,0xdd,0xcc,0x50 = aver_u.w $w17, $w25, $w29 +0x7b,0xf3,0xb5,0x90 = aver_u.d $w22, $w22, $w19 +0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29 +0x79,0xbc,0xac,0x0d = bclr.h $w16, $w21, $w28 +0x79,0xc9,0x14,0xcd = bclr.w $w19, $w2, $w9 +0x79,0xe4,0xfe,0xcd = bclr.d $w27, $w31, $w4 +0x7b,0x18,0x81,0x4d = binsl.b $w5, $w16, $w24 +0x7b,0x2a,0x2f,0x8d = binsl.h $w30, $w5, $w10 +0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13 +0x7b,0x6c,0xa5,0xcd = binsl.d $w23, $w20, $w12 +0x7b,0x82,0x5d,0x8d = binsr.b $w22, $w11, $w2 +0x7b,0xa6,0xd0,0x0d = binsr.h $w0, $w26, $w6 +0x7b,0xdc,0x1e,0x8d = binsr.w $w26, $w3, $w28 +0x7b,0xf5,0x00,0x0d = binsr.d $w0, $w0, $w21 +0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24 +0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4 +0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19 +0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15 +0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31 +0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6 +0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12 +0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5 +0x78,0x12,0xff,0xcf = ceq.b $w31, $w31, $w18 +0x78,0x29,0xda,0x8f = ceq.h $w10, $w27, $w9 +0x78,0x4e,0x2a,0x4f = ceq.w $w9, $w5, $w14 +0x78,0x60,0x89,0x4f = ceq.d $w5, $w17, $w0 +0x7a,0x09,0x25,0xcf = cle_s.b $w23, $w4, $w9 +0x7a,0x33,0xdd,0x8f = cle_s.h $w22, $w27, $w19 +0x7a,0x4a,0xd7,0x8f = cle_s.w $w30, $w26, $w10 +0x7a,0x6a,0x2c,0x8f = cle_s.d $w18, $w5, $w10 +0x7a,0x80,0xc8,0x4f = cle_u.b $w1, $w25, $w0 +0x7a,0xbd,0x01,0xcf = cle_u.h $w7, $w0, $w29 +0x7a,0xc1,0x96,0x4f = cle_u.w $w25, $w18, $w1 +0x7a,0xfe,0x01,0x8f = cle_u.d $w6, $w0, $w30 +0x79,0x15,0x16,0x4f = clt_s.b $w25, $w2, $w21 +0x79,0x29,0x98,0x8f = clt_s.h $w2, $w19, $w9 +0x79,0x50,0x45,0xcf = clt_s.w $w23, $w8, $w16 +0x79,0x6c,0xf1,0xcf = clt_s.d $w7, $w30, $w12 +0x79,0x8d,0xf8,0x8f = clt_u.b $w2, $w31, $w13 +0x79,0xb7,0xfc,0x0f = clt_u.h $w16, $w31, $w23 +0x79,0xc9,0xc0,0xcf = clt_u.w $w3, $w24, $w9 +0x79,0xe1,0x01,0xcf = clt_u.d $w7, $w0, $w1 +0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18 +0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13 +0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30 +0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20 +0x7a,0x8a,0xe9,0x92 = div_u.b $w6, $w29, $w10 +0x7a,0xae,0xae,0x12 = div_u.h $w24, $w21, $w14 +0x7a,0xd9,0x77,0x52 = div_u.w $w29, $w14, $w25 +0x7a,0xf5,0x0f,0xd2 = div_u.d $w31, $w1, $w21 +0x78,0x39,0xb5,0xd3 = dotp_s.h $w23, $w22, $w25 +0x78,0x45,0x75,0x13 = dotp_s.w $w20, $w14, $w5 +0x78,0x76,0x14,0x53 = dotp_s.d $w17, $w2, $w22 +0x78,0xa6,0x13,0x53 = dotp_u.h $w13, $w2, $w6 +0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21 +0x78,0xfa,0x81,0x13 = dotp_u.d $w4, $w16, $w26 +0x79,0x36,0xe0,0x53 = dpadd_s.h $w1, $w28, $w22 +0x79,0x4c,0x0a,0x93 = dpadd_s.w $w10, $w1, $w12 +0x79,0x7b,0xa8,0xd3 = dpadd_s.d $w3, $w21, $w27 +0x79,0xb4,0x2c,0x53 = dpadd_u.h $w17, $w5, $w20 +0x79,0xd0,0x46,0x13 = dpadd_u.w $w24, $w8, $w16 +0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16 +0x7a,0x2c,0x59,0x13 = dpsub_s.h $w4, $w11, $w12 +0x7a,0x46,0x39,0x13 = dpsub_s.w $w4, $w7, $w6 +0x7a,0x7c,0x67,0xd3 = dpsub_s.d $w31, $w12, $w28 +0x7a,0xb1,0xc9,0x13 = dpsub_u.h $w4, $w25, $w17 +0x7a,0xd0,0xcc,0xd3 = dpsub_u.w $w19, $w25, $w16 +0x7a,0xfa,0x51,0xd3 = dpsub_u.d $w7, $w10, $w26 +0x7a,0x22,0xc7,0x15 = hadd_s.h $w28, $w24, $w2 +0x7a,0x4b,0x8e,0x15 = hadd_s.w $w24, $w17, $w11 +0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20 +0x7a,0xb1,0xeb,0x15 = hadd_u.h $w12, $w29, $w17 +0x7a,0xc6,0x2a,0x55 = hadd_u.w $w9, $w5, $w6 +0x7a,0xe6,0xa0,0x55 = hadd_u.d $w1, $w20, $w6 +0x7b,0x3d,0x74,0x15 = hsub_s.h $w16, $w14, $w29 +0x7b,0x4b,0x6a,0x55 = hsub_s.w $w9, $w13, $w11 +0x7b,0x6e,0x97,0x95 = hsub_s.d $w30, $w18, $w14 +0x7b,0xae,0x61,0xd5 = hsub_u.h $w7, $w12, $w14 +0x7b,0xc5,0x2d,0x55 = hsub_u.w $w21, $w5, $w5 +0x7b,0xff,0x62,0xd5 = hsub_u.d $w11, $w12, $w31 +0x7b,0x1e,0x84,0x94 = ilvev.b $w18, $w16, $w30 +0x7b,0x2d,0x03,0x94 = ilvev.h $w14, $w0, $w13 +0x7b,0x56,0xcb,0x14 = ilvev.w $w12, $w25, $w22 +0x7b,0x63,0xdf,0x94 = ilvev.d $w30, $w27, $w3 +0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21 +0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17 +0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0 +0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24 +0x7b,0x94,0x2a,0xd4 = ilvod.b $w11, $w5, $w20 +0x7b,0xbf,0x6c,0x94 = ilvod.h $w18, $w13, $w31 +0x7b,0xd8,0x87,0x54 = ilvod.w $w29, $w16, $w24 +0x7b,0xfd,0x65,0x94 = ilvod.d $w22, $w12, $w29 +0x7a,0x86,0xf1,0x14 = ilvr.b $w4, $w30, $w6 +0x7a,0xbd,0x9f,0x14 = ilvr.h $w28, $w19, $w29 +0x7a,0xd5,0xa4,0x94 = ilvr.w $w18, $w20, $w21 +0x7a,0xec,0xf5,0xd4 = ilvr.d $w23, $w30, $w12 +0x78,0x9d,0xfc,0x52 = maddv.b $w17, $w31, $w29 +0x78,0xa9,0xc1,0xd2 = maddv.h $w7, $w24, $w9 +0x78,0xd4,0xb5,0x92 = maddv.w $w22, $w22, $w20 +0x78,0xf4,0xd7,0x92 = maddv.d $w30, $w26, $w20 +0x7b,0x17,0x5d,0xce = max_a.b $w23, $w11, $w23 +0x7b,0x3e,0x2d,0x0e = max_a.h $w20, $w5, $w30 +0x7b,0x5e,0x91,0xce = max_a.w $w7, $w18, $w30 +0x7b,0x7f,0x42,0x0e = max_a.d $w8, $w8, $w31 +0x79,0x13,0x0a,0x8e = max_s.b $w10, $w1, $w19 +0x79,0x31,0xeb,0xce = max_s.h $w15, $w29, $w17 +0x79,0x4e,0xeb,0xce = max_s.w $w15, $w29, $w14 +0x79,0x63,0xc6,0x4e = max_s.d $w25, $w24, $w3 +0x79,0x85,0xc3,0x0e = max_u.b $w12, $w24, $w5 +0x79,0xa7,0x31,0x4e = max_u.h $w5, $w6, $w7 +0x79,0xc7,0x24,0x0e = max_u.w $w16, $w4, $w7 +0x79,0xf8,0x66,0x8e = max_u.d $w26, $w12, $w24 +0x7b,0x81,0xd1,0x0e = min_a.b $w4, $w26, $w1 +0x7b,0xbf,0x6b,0x0e = min_a.h $w12, $w13, $w31 +0x7b,0xc0,0xa7,0x0e = min_a.w $w28, $w20, $w0 +0x7b,0xf3,0xa3,0x0e = min_a.d $w12, $w20, $w19 +0x7a,0x0e,0x1c,0xce = min_s.b $w19, $w3, $w14 +0x7a,0x28,0xae,0xce = min_s.h $w27, $w21, $w8 +0x7a,0x5e,0x70,0x0e = min_s.w $w0, $w14, $w30 +0x7a,0x75,0x41,0x8e = min_s.d $w6, $w8, $w21 +0x7a,0x88,0xd5,0x8e = min_u.b $w22, $w26, $w8 +0x7a,0xac,0xd9,0xce = min_u.h $w7, $w27, $w12 +0x7a,0xce,0xa2,0x0e = min_u.w $w8, $w20, $w14 +0x7a,0xef,0x76,0x8e = min_u.d $w26, $w14, $w15 +0x7b,0x1a,0x0c,0x92 = mod_s.b $w18, $w1, $w26 +0x7b,0x3c,0xf7,0xd2 = mod_s.h $w31, $w30, $w28 +0x7b,0x4d,0x30,0x92 = mod_s.w $w2, $w6, $w13 +0x7b,0x76,0xdd,0x52 = mod_s.d $w21, $w27, $w22 +0x7b,0x8d,0x3c,0x12 = mod_u.b $w16, $w7, $w13 +0x7b,0xa7,0x46,0x12 = mod_u.h $w24, $w8, $w7 +0x7b,0xd1,0x17,0x92 = mod_u.w $w30, $w2, $w17 +0x7b,0xf9,0x17,0xd2 = mod_u.d $w31, $w2, $w25 +0x79,0x0c,0x2b,0x92 = msubv.b $w14, $w5, $w12 +0x79,0x3e,0x39,0x92 = msubv.h $w6, $w7, $w30 +0x79,0x55,0x13,0x52 = msubv.w $w13, $w2, $w21 +0x79,0x7b,0x74,0x12 = msubv.d $w16, $w14, $w27 +0x78,0x0d,0x1d,0x12 = mulv.b $w20, $w3, $w13 +0x78,0x2e,0xd6,0xd2 = mulv.h $w27, $w26, $w14 +0x78,0x43,0xea,0x92 = mulv.w $w10, $w29, $w3 +0x78,0x7d,0x99,0xd2 = mulv.d $w7, $w19, $w29 +0x79,0x07,0xd9,0x54 = pckev.b $w5, $w27, $w7 +0x79,0x3b,0x20,0x54 = pckev.h $w1, $w4, $w27 +0x79,0x40,0xa7,0x94 = pckev.w $w30, $w20, $w0 +0x79,0x6f,0x09,0x94 = pckev.d $w6, $w1, $w15 +0x79,0x9e,0xe4,0x94 = pckod.b $w18, $w28, $w30 +0x79,0xa8,0x2e,0x94 = pckod.h $w26, $w5, $w8 +0x79,0xc2,0x22,0x54 = pckod.w $w9, $w4, $w2 +0x79,0xf4,0xb7,0x94 = pckod.d $w30, $w22, $w20 +0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4] +0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1] +0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1] +0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp] +0x78,0x11,0x00,0xcd = sll.b $w3, $w0, $w17 +0x78,0x23,0xdc,0x4d = sll.h $w17, $w27, $w3 +0x78,0x46,0x3c,0x0d = sll.w $w16, $w7, $w6 +0x78,0x7a,0x02,0x4d = sll.d $w9, $w0, $w26 +0x78,0x81,0x0f,0x14 = splat.b $w28, $w1[$at] +0x78,0xab,0x58,0x94 = splat.h $w2, $w11[$t3] +0x78,0xcb,0x05,0x94 = splat.w $w22, $w0[$t3] +0x78,0xe2,0x00,0x14 = splat.d $w0, $w0[$v0] +0x78,0x91,0x27,0x0d = sra.b $w28, $w4, $w17 +0x78,0xa3,0x4b,0x4d = sra.h $w13, $w9, $w3 +0x78,0xd3,0xae,0xcd = sra.w $w27, $w21, $w19 +0x78,0xf7,0x47,0x8d = sra.d $w30, $w8, $w23 +0x78,0x92,0x94,0xd5 = srar.b $w19, $w18, $w18 +0x78,0xa8,0xb9,0xd5 = srar.h $w7, $w23, $w8 +0x78,0xc2,0x60,0x55 = srar.w $w1, $w12, $w2 +0x78,0xee,0x3d,0x55 = srar.d $w21, $w7, $w14 +0x79,0x13,0x1b,0x0d = srl.b $w12, $w3, $w19 +0x79,0x34,0xfd,0xcd = srl.h $w23, $w31, $w20 +0x79,0x4b,0xdc,0x8d = srl.w $w18, $w27, $w11 +0x79,0x7a,0x60,0xcd = srl.d $w3, $w12, $w26 +0x79,0x0b,0xab,0xd5 = srlr.b $w15, $w21, $w11 +0x79,0x33,0x6d,0x55 = srlr.h $w21, $w13, $w19 +0x79,0x43,0xf1,0x95 = srlr.w $w6, $w30, $w3 +0x79,0x6e,0x10,0x55 = srlr.d $w1, $w2, $w14 +0x78,0x01,0x7e,0x51 = subs_s.b $w25, $w15, $w1 +0x78,0x36,0xcf,0x11 = subs_s.h $w28, $w25, $w22 +0x78,0x55,0x62,0x91 = subs_s.w $w10, $w12, $w21 +0x78,0x72,0xa1,0x11 = subs_s.d $w4, $w20, $w18 +0x78,0x99,0x35,0x51 = subs_u.b $w21, $w6, $w25 +0x78,0xa7,0x50,0xd1 = subs_u.h $w3, $w10, $w7 +0x78,0xca,0x7a,0x51 = subs_u.w $w9, $w15, $w10 +0x78,0xea,0x99,0xd1 = subs_u.d $w7, $w19, $w10 +0x79,0x0c,0x39,0x91 = subsus_u.b $w6, $w7, $w12 +0x79,0x33,0xe9,0x91 = subsus_u.h $w6, $w29, $w19 +0x79,0x47,0x79,0xd1 = subsus_u.w $w7, $w15, $w7 +0x79,0x6f,0x1a,0x51 = subsus_u.d $w9, $w3, $w15 +0x79,0x9f,0x1d,0x91 = subsuu_s.b $w22, $w3, $w31 +0x79,0xb6,0xbc,0xd1 = subsuu_s.h $w19, $w23, $w22 +0x79,0xcd,0x52,0x51 = subsuu_s.w $w9, $w10, $w13 +0x79,0xe0,0x31,0x51 = subsuu_s.d $w5, $w6, $w0 +0x78,0x93,0x69,0x8e = subv.b $w6, $w13, $w19 +0x78,0xac,0xc9,0x0e = subv.h $w4, $w25, $w12 +0x78,0xcb,0xde,0xce = subv.w $w27, $w27, $w11 +0x78,0xea,0xc2,0x4e = subv.d $w9, $w24, $w10 +0x78,0x05,0x80,0xd5 = vshf.b $w3, $w16, $w5 +0x78,0x28,0x9d,0x15 = vshf.h $w20, $w19, $w8 +0x78,0x59,0xf4,0x15 = vshf.w $w16, $w30, $w25 +0x78,0x6f,0x5c,0xd5 = vshf.d $w19, $w11, $w15 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_3rf.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_3rf.s.cs new file mode 100644 index 0000000..491162d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_3rf.s.cs @@ -0,0 +1,83 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28 +0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29 +0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25 +0x78,0x33,0x08,0x5a = fcaf.d $w1, $w1, $w19 +0x78,0x90,0xb8,0x5a = fceq.w $w1, $w23, $w16 +0x78,0xb0,0x40,0x1a = fceq.d $w0, $w8, $w16 +0x79,0x98,0x4c,0x1a = fcle.w $w16, $w9, $w24 +0x79,0xa1,0x76,0xda = fcle.d $w27, $w14, $w1 +0x79,0x08,0x47,0x1a = fclt.w $w28, $w8, $w8 +0x79,0x2b,0xcf,0x9a = fclt.d $w30, $w25, $w11 +0x78,0xd7,0x90,0x9c = fcne.w $w2, $w18, $w23 +0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15 +0x78,0x59,0x92,0x9c = fcor.w $w10, $w18, $w25 +0x78,0x6b,0xcc,0x5c = fcor.d $w17, $w25, $w11 +0x78,0xd5,0x13,0x9a = fcueq.w $w14, $w2, $w21 +0x78,0xe7,0x1f,0x5a = fcueq.d $w29, $w3, $w7 +0x79,0xc3,0x2c,0x5a = fcule.w $w17, $w5, $w3 +0x79,0xfe,0x0f,0xda = fcule.d $w31, $w1, $w30 +0x79,0x49,0xc9,0x9a = fcult.w $w6, $w25, $w9 +0x79,0x71,0x46,0xda = fcult.d $w27, $w8, $w17 +0x78,0x48,0xa1,0x1a = fcun.w $w4, $w20, $w8 +0x78,0x63,0x5f,0x5a = fcun.d $w29, $w11, $w3 +0x78,0x93,0x93,0x5c = fcune.w $w13, $w18, $w19 +0x78,0xb5,0xd4,0x1c = fcune.d $w16, $w26, $w21 +0x78,0xc2,0xc3,0x5b = fdiv.w $w13, $w24, $w2 +0x78,0xf9,0x24,0xdb = fdiv.d $w19, $w4, $w25 +0x7a,0x10,0x02,0x1b = fexdo.h $w8, $w0, $w16 +0x7a,0x3b,0x68,0x1b = fexdo.w $w0, $w13, $w27 +0x79,0xc3,0x04,0x5b = fexp2.w $w17, $w0, $w3 +0x79,0xea,0x05,0x9b = fexp2.d $w22, $w0, $w10 +0x79,0x17,0x37,0x5b = fmadd.w $w29, $w6, $w23 +0x79,0x35,0xe2,0xdb = fmadd.d $w11, $w28, $w21 +0x7b,0x8d,0xb8,0x1b = fmax.w $w0, $w23, $w13 +0x7b,0xa8,0x96,0x9b = fmax.d $w26, $w18, $w8 +0x7b,0xca,0x82,0x9b = fmax_a.w $w10, $w16, $w10 +0x7b,0xf6,0x4f,0x9b = fmax_a.d $w30, $w9, $w22 +0x7b,0x1e,0x0e,0x1b = fmin.w $w24, $w1, $w30 +0x7b,0x2a,0xde,0xdb = fmin.d $w27, $w27, $w10 +0x7b,0x54,0xea,0x9b = fmin_a.w $w10, $w29, $w20 +0x7b,0x78,0xf3,0x5b = fmin_a.d $w13, $w30, $w24 +0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0 +0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16 +0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15 +0x78,0xaa,0xf2,0x5b = fmul.d $w9, $w30, $w10 +0x7a,0x0a,0x2e,0x5a = fsaf.w $w25, $w5, $w10 +0x7a,0x3d,0x1e,0x5a = fsaf.d $w25, $w3, $w29 +0x7a,0x8d,0x8a,0xda = fseq.w $w11, $w17, $w13 +0x7a,0xbf,0x07,0x5a = fseq.d $w29, $w0, $w31 +0x7b,0x9f,0xff,0x9a = fsle.w $w30, $w31, $w31 +0x7b,0xb8,0xbc,0x9a = fsle.d $w18, $w23, $w24 +0x7b,0x06,0x2b,0x1a = fslt.w $w12, $w5, $w6 +0x7b,0x35,0xd4,0x1a = fslt.d $w16, $w26, $w21 +0x7a,0xcc,0x0f,0x9c = fsne.w $w30, $w1, $w12 +0x7a,0xf7,0x6b,0x9c = fsne.d $w14, $w13, $w23 +0x7a,0x5b,0x6e,0xdc = fsor.w $w27, $w13, $w27 +0x7a,0x6b,0xc3,0x1c = fsor.d $w12, $w24, $w11 +0x78,0x41,0xd7,0xdb = fsub.w $w31, $w26, $w1 +0x78,0x7b,0x8c,0xdb = fsub.d $w19, $w17, $w27 +0x7a,0xd9,0xc4,0x1a = fsueq.w $w16, $w24, $w25 +0x7a,0xee,0x74,0x9a = fsueq.d $w18, $w14, $w14 +0x7b,0xcd,0xf5,0xda = fsule.w $w23, $w30, $w13 +0x7b,0xfa,0x58,0x9a = fsule.d $w2, $w11, $w26 +0x7b,0x56,0xd2,0xda = fsult.w $w11, $w26, $w22 +0x7b,0x7e,0xb9,0x9a = fsult.d $w6, $w23, $w30 +0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28 +0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19 +0x7a,0x82,0xfc,0x1c = fsune.w $w16, $w31, $w2 +0x7a,0xb1,0xd0,0xdc = fsune.d $w3, $w26, $w17 +0x7a,0x98,0x24,0x1b = ftq.h $w16, $w4, $w24 +0x7a,0xb9,0x29,0x5b = ftq.w $w5, $w5, $w25 +0x79,0x4a,0xa4,0x1c = madd_q.h $w16, $w20, $w10 +0x79,0x69,0x17,0x1c = madd_q.w $w28, $w2, $w9 +0x7b,0x49,0x92,0x1c = maddr_q.h $w8, $w18, $w9 +0x7b,0x70,0x67,0x5c = maddr_q.w $w29, $w12, $w16 +0x79,0x8a,0xd6,0x1c = msub_q.h $w24, $w26, $w10 +0x79,0xbc,0xf3,0x5c = msub_q.w $w13, $w30, $w28 +0x7b,0x8b,0xab,0x1c = msubr_q.h $w12, $w21, $w11 +0x7b,0xb4,0x70,0x5c = msubr_q.w $w1, $w14, $w20 +0x79,0x1e,0x81,0x9c = mul_q.h $w6, $w16, $w30 +0x79,0x24,0x0c,0x1c = mul_q.w $w16, $w1, $w4 +0x7b,0x13,0xa1,0x9c = mulr_q.h $w6, $w20, $w19 +0x7b,0x34,0x0e,0xdc = mulr_q.w $w27, $w1, $w20 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_bit.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_bit.s.cs new file mode 100644 index 0000000..882cd90 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_bit.s.cs @@ -0,0 +1,49 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2 +0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0 +0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3 +0x79,0x80,0x5a,0x49 = bclri.d $w9, $w11, 0 +0x7b,0x71,0x66,0x49 = binsli.b $w25, $w12, 1 +0x7b,0x60,0xb5,0x49 = binsli.h $w21, $w22, 0 +0x7b,0x40,0x25,0x89 = binsli.w $w22, $w4, 0 +0x7b,0x06,0x11,0x89 = binsli.d $w6, $w2, 6 +0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0 +0x7b,0xe1,0xf2,0x09 = binsri.h $w8, $w30, 1 +0x7b,0xc5,0x98,0x89 = binsri.w $w2, $w19, 5 +0x7b,0x81,0xa4,0x89 = binsri.d $w18, $w20, 1 +0x7a,0xf0,0x9e,0x09 = bnegi.b $w24, $w19, 0 +0x7a,0xe3,0x5f,0x09 = bnegi.h $w28, $w11, 3 +0x7a,0xc5,0xd8,0x49 = bnegi.w $w1, $w27, 5 +0x7a,0x81,0xa9,0x09 = bnegi.d $w4, $w21, 1 +0x7a,0x70,0x44,0x89 = bseti.b $w18, $w8, 0 +0x7a,0x62,0x76,0x09 = bseti.h $w24, $w14, 2 +0x7a,0x44,0x92,0x49 = bseti.w $w9, $w18, 4 +0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1 +0x78,0x72,0xff,0xca = sat_s.b $w31, $w31, 2 +0x78,0x60,0x9c,0xca = sat_s.h $w19, $w19, 0 +0x78,0x40,0xec,0xca = sat_s.w $w19, $w29, 0 +0x78,0x00,0xb2,0xca = sat_s.d $w11, $w22, 0 +0x78,0xf3,0x68,0x4a = sat_u.b $w1, $w13, 3 +0x78,0xe4,0xc7,0x8a = sat_u.h $w30, $w24, 4 +0x78,0xc0,0x6f,0xca = sat_u.w $w31, $w13, 0 +0x78,0x85,0x87,0x4a = sat_u.d $w29, $w16, 5 +0x78,0x71,0x55,0xc9 = slli.b $w23, $w10, 1 +0x78,0x61,0x92,0x49 = slli.h $w9, $w18, 1 +0x78,0x44,0xea,0xc9 = slli.w $w11, $w29, 4 +0x78,0x01,0xa6,0x49 = slli.d $w25, $w20, 1 +0x78,0xf1,0xee,0x09 = srai.b $w24, $w29, 1 +0x78,0xe0,0x30,0x49 = srai.h $w1, $w6, 0 +0x78,0xc1,0xd1,0xc9 = srai.w $w7, $w26, 1 +0x78,0x83,0xcd,0x09 = srai.d $w20, $w25, 3 +0x79,0x70,0xc9,0x4a = srari.b $w5, $w25, 0 +0x79,0x64,0x31,0xca = srari.h $w7, $w6, 4 +0x79,0x45,0x5c,0x4a = srari.w $w17, $w11, 5 +0x79,0x05,0xcd,0x4a = srari.d $w21, $w25, 5 +0x79,0x72,0x00,0x89 = srli.b $w2, $w0, 2 +0x79,0x62,0xff,0xc9 = srli.h $w31, $w31, 2 +0x79,0x44,0x49,0x49 = srli.w $w5, $w9, 4 +0x79,0x05,0xd6,0xc9 = srli.d $w27, $w26, 5 +0x79,0xf0,0x1c,0x8a = srlri.b $w18, $w3, 0 +0x79,0xe3,0x10,0x4a = srlri.h $w1, $w2, 3 +0x79,0xc2,0xb2,0xca = srlri.w $w11, $w22, 2 +0x79,0x86,0x56,0x0a = srlri.d $w24, $w10, 6 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_cbranch.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_cbranch.s.cs new file mode 100644 index 0000000..92e7cdb --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_cbranch.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +// 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 +// 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 +// 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 +// 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 +// 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 +// 0x47,0x00,0x00,0x20 = bz.b $w0, 128 +// 0x47,0x21,0x00,0x40 = bz.h $w1, 256 +// 0x47,0x42,0x00,0x80 = bz.w $w2, 512 +// 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 +// 0x45,0x60,0x00,0x01 = bz.v $w0, 4 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_ctrlregs.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_ctrlregs.s.cs new file mode 100644 index 0000000..fb587a7 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_ctrlregs.s.cs @@ -0,0 +1,33 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 +0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 +0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 +0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 +0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 +0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 +0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 +0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 +0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 +0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 +0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 +0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 +0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 +0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 +0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 +0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 +0x78,0x3e,0x08,0x19 = ctcmsa $0, $at +0x78,0x3e,0x08,0x19 = ctcmsa $0, $at +0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 +0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 +0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 +0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 +0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 +0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 +0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 +0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 +0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 +0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 +0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 +0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 +0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 +0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_elm.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm.s.cs new file mode 100644 index 0000000..c2ba952 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm.s.cs @@ -0,0 +1,16 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2] +0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0] +0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1] +0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4] +0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0] +0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] +0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] +0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] +0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] +0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] +0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] +0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] +0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] +0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] +0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insert.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insert.s.cs new file mode 100644 index 0000000..c9edc8e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insert.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp +0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1 +0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insve.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insve.s.cs new file mode 100644 index 0000000..7657969 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_elm_insve.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] +0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] +0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] +0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_i10.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_i10.s.cs new file mode 100644 index 0000000..ba799f9 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_i10.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 +0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 +0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 +// 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_i5.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_i5.s.cs new file mode 100644 index 0000000..5719223 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_i5.s.cs @@ -0,0 +1,45 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30 +0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26 +0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26 +0x78,0x75,0x0c,0x06 = addvi.d $w16, $w1, 21 +// 0x78,0x18,0xae,0x07 = ceqi.b $w24, $w21, -8 +0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2 +// 0x78,0x5f,0x0b,0x07 = ceqi.w $w12, $w1, -1 +0x78,0x67,0xb6,0x07 = ceqi.d $w24, $w22, 7 +0x7a,0x01,0x83,0x07 = clei_s.b $w12, $w16, 1 +// 0x7a,0x37,0x50,0x87 = clei_s.h $w2, $w10, -9 +// 0x7a,0x56,0x59,0x07 = clei_s.w $w4, $w11, -10 +// 0x7a,0x76,0xe8,0x07 = clei_s.d $w0, $w29, -10 +0x7a,0x83,0x8d,0x47 = clei_u.b $w21, $w17, 3 +0x7a,0xb1,0x3f,0x47 = clei_u.h $w29, $w7, 17 +0x7a,0xc2,0x08,0x47 = clei_u.w $w1, $w1, 2 +0x7a,0xfd,0xde,0xc7 = clei_u.d $w27, $w27, 29 +// 0x79,0x19,0x6c,0xc7 = clti_s.b $w19, $w13, -7 +// 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12 +0x79,0x4b,0x63,0x07 = clti_s.w $w12, $w12, 11 +// 0x79,0x71,0xa7,0x47 = clti_s.d $w29, $w20, -15 +0x79,0x9d,0x4b,0x87 = clti_u.b $w14, $w9, 29 +0x79,0xb9,0xce,0x07 = clti_u.h $w24, $w25, 25 +0x79,0xd6,0x08,0x47 = clti_u.w $w1, $w1, 22 +0x79,0xe1,0xcd,0x47 = clti_u.d $w21, $w25, 1 +0x79,0x01,0xad,0x86 = maxi_s.b $w22, $w21, 1 +// 0x79,0x38,0x2f,0x46 = maxi_s.h $w29, $w5, -8 +// 0x79,0x54,0x50,0x46 = maxi_s.w $w1, $w10, -12 +// 0x79,0x70,0xeb,0x46 = maxi_s.d $w13, $w29, -16 +0x79,0x8c,0x05,0x06 = maxi_u.b $w20, $w0, 12 +0x79,0xa3,0x70,0x46 = maxi_u.h $w1, $w14, 3 +0x79,0xcb,0xb6,0xc6 = maxi_u.w $w27, $w22, 11 +0x79,0xe4,0x36,0x86 = maxi_u.d $w26, $w6, 4 +0x7a,0x01,0x09,0x06 = mini_s.b $w4, $w1, 1 +// 0x7a,0x37,0xde,0xc6 = mini_s.h $w27, $w27, -9 +0x7a,0x49,0x5f,0x06 = mini_s.w $w28, $w11, 9 +0x7a,0x6a,0x52,0xc6 = mini_s.d $w11, $w10, 10 +0x7a,0x9b,0xbc,0x86 = mini_u.b $w18, $w23, 27 +0x7a,0xb2,0xd1,0xc6 = mini_u.h $w7, $w26, 18 +0x7a,0xda,0x62,0xc6 = mini_u.w $w11, $w12, 26 +0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2 +0x78,0x93,0xa6,0x06 = subvi.b $w24, $w20, 19 +0x78,0xa4,0x9a,0xc6 = subvi.h $w11, $w19, 4 +0x78,0xcb,0x53,0x06 = subvi.w $w12, $w10, 11 +0x78,0xe7,0x84,0xc6 = subvi.d $w19, $w16, 7 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_i8.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_i8.s.cs new file mode 100644 index 0000000..0b08f63 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_i8.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 +0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 +0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 +0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 +0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 +0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 +0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 +0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 +0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 +0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_lsa.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_lsa.s.cs new file mode 100644 index 0000000..098775c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_lsa.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1 +0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2 +0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3 +0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4 diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_mi10.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_mi10.s.cs new file mode 100644 index 0000000..54d62c4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_mi10.s.cs @@ -0,0 +1,24 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at) +0x78,0x00,0x10,0x60 = ld.b $w1, ($v0) +0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1) +0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0) +0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1) +0x78,0x00,0x31,0x61 = ld.h $w5, ($a2) +0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3) +0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0) +0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1) +0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2) +0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3) +0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4) +0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5) +0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6) +0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7) +0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0) +0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1) +0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2) +0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3) +0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4) +0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5) +0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6) +0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7) diff --git a/white_patch_detect/capstone-master/suite/MC/Mips/test_vec.s.cs b/white_patch_detect/capstone-master/suite/MC/Mips/test_vec.s.cs new file mode 100644 index 0000000..9303868 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Mips/test_vec.s.cs @@ -0,0 +1,8 @@ +# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None +0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 +0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 +0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 +0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 +0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 +0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 +0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs new file mode 100644 index 0000000..bc38854 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +0x7c,0x02,0x1f,0xac = icbi 2, 3 +0x7c,0x02,0x1a,0x2c = dcbt 2, 3 +0x7c,0x02,0x19,0xec = dcbtst 2, 3 +0x7c,0x02,0x1f,0xec = dcbz 2, 3 +0x7c,0x02,0x18,0x6c = dcbst 2, 3 +0x4c,0x00,0x01,0x2c = isync +0x7c,0x43,0x21,0x2d = stwcx. 2, 3, 4 +0x7c,0x43,0x21,0xad = stdcx. 2, 3, 4 +// 0x7c,0x40,0x04,0xac = sync 2 +0x7c,0x00,0x06,0xac = eieio +// 0x7c,0x40,0x00,0x7c = wait 2 +0x7c,0x02,0x18,0xac = dcbf 2, 3 +0x7c,0x43,0x20,0x28 = lwarx 2, 3, 4 +0x7c,0x43,0x20,0xa8 = ldarx 2, 3, 4 +0x7c,0x00,0x04,0xac = sync 0 +0x7c,0x00,0x04,0xac = sync 0 +// 0x7c,0x20,0x04,0xac = sync 1 +// 0x7c,0x40,0x04,0xac = sync 2 +// 0x7c,0x00,0x00,0x7c = wait 0 +// 0x7c,0x20,0x00,0x7c = wait 1 +// 0x7c,0x40,0x00,0x7c = wait 2 +0x7c,0x5b,0x1a,0xe6 = mftb 2, 123 +0x7c,0x4c,0x42,0xe6 = mftb 2, 268 +// 0x7c,0x4d,0x42,0xe6 = mftb 2, 269 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs new file mode 100644 index 0000000..53ab9cd --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs @@ -0,0 +1,35 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +// 0x7c,0x80,0x01,0x24 = mtmsr 4, 0 +0x7c,0x81,0x01,0x24 = mtmsr 4, 1 +0x7c,0x80,0x00,0xa6 = mfmsr 4 +// 0x7c,0x80,0x01,0x64 = mtmsrd 4, 0 +0x7c,0x81,0x01,0x64 = mtmsrd 4, 1 +0x7c,0x90,0x42,0xa6 = mfspr 4, 272 +0x7c,0x91,0x42,0xa6 = mfspr 4, 273 +0x7c,0x92,0x42,0xa6 = mfspr 4, 274 +0x7c,0x93,0x42,0xa6 = mfspr 4, 275 +0x7c,0x90,0x43,0xa6 = mtspr 272, 4 +0x7c,0x91,0x43,0xa6 = mtspr 273, 4 +0x7c,0x92,0x43,0xa6 = mtspr 274, 4 +0x7c,0x93,0x43,0xa6 = mtspr 275, 4 +0x7c,0x90,0x43,0xa6 = mtspr 272, 4 +0x7c,0x91,0x43,0xa6 = mtspr 273, 4 +0x7c,0x92,0x43,0xa6 = mtspr 274, 4 +0x7c,0x93,0x43,0xa6 = mtspr 275, 4 +0x7c,0x98,0x43,0xa6 = mtspr 280, 4 +0x7c,0x96,0x02,0xa6 = mfspr 4, 22 +0x7c,0x96,0x03,0xa6 = mtspr 22, 4 +// 0x7c,0x9f,0x42,0xa6 = mfspr 4, 287 +0x7c,0x99,0x02,0xa6 = mfspr 4, 25 +0x7c,0x99,0x03,0xa6 = mtspr 25, 4 +0x7c,0x9a,0x02,0xa6 = mfspr 4, 26 +0x7c,0x9a,0x03,0xa6 = mtspr 26, 4 +0x7c,0x9b,0x02,0xa6 = mfspr 4, 27 +0x7c,0x9b,0x03,0xa6 = mtspr 27, 4 +0x7c,0x00,0x23,0x64 = slbie 4 +0x7c,0x80,0x2b,0x24 = slbmte 4, 5 +0x7c,0x80,0x2f,0x26 = slbmfee 4, 5 +0x7c,0x00,0x03,0xe4 = slbia +0x7c,0x00,0x04,0x6c = tlbsync +0x7c,0x00,0x22,0x24 = tlbiel 4 +// 0x7c,0x00,0x22,0x64 = tlbie 4,0 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-ext.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-ext.s.cs new file mode 100644 index 0000000..e13b4c4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-ext.s.cs @@ -0,0 +1,535 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +// 0x4d,0x82,0x00,0x20 = beqlr 0 +// 0x4d,0x86,0x00,0x20 = beqlr 1 +// 0x4d,0x8a,0x00,0x20 = beqlr 2 +// 0x4d,0x8e,0x00,0x20 = beqlr 3 +// 0x4d,0x92,0x00,0x20 = beqlr 4 +// 0x4d,0x96,0x00,0x20 = beqlr 5 +// 0x4d,0x9a,0x00,0x20 = beqlr 6 +// 0x4d,0x9e,0x00,0x20 = beqlr 7 +// 0x4d,0x80,0x00,0x20 = bclr 12, 0, 0 +// 0x4d,0x81,0x00,0x20 = bclr 12, 1, 0 +// 0x4d,0x82,0x00,0x20 = bclr 12, 2, 0 +// 0x4d,0x83,0x00,0x20 = bclr 12, 3, 0 +// 0x4d,0x83,0x00,0x20 = bclr 12, 3, 0 +// 0x4d,0x84,0x00,0x20 = bclr 12, 4, 0 +// 0x4d,0x85,0x00,0x20 = bclr 12, 5, 0 +// 0x4d,0x86,0x00,0x20 = bclr 12, 6, 0 +// 0x4d,0x87,0x00,0x20 = bclr 12, 7, 0 +// 0x4d,0x87,0x00,0x20 = bclr 12, 7, 0 +// 0x4d,0x88,0x00,0x20 = bclr 12, 8, 0 +// 0x4d,0x89,0x00,0x20 = bclr 12, 9, 0 +// 0x4d,0x8a,0x00,0x20 = bclr 12, 10, 0 +// 0x4d,0x8b,0x00,0x20 = bclr 12, 11, 0 +// 0x4d,0x8b,0x00,0x20 = bclr 12, 11, 0 +// 0x4d,0x8c,0x00,0x20 = bclr 12, 12, 0 +// 0x4d,0x8d,0x00,0x20 = bclr 12, 13, 0 +// 0x4d,0x8e,0x00,0x20 = bclr 12, 14, 0 +// 0x4d,0x8f,0x00,0x20 = bclr 12, 15, 0 +// 0x4d,0x8f,0x00,0x20 = bclr 12, 15, 0 +// 0x4d,0x90,0x00,0x20 = bclr 12, 16, 0 +// 0x4d,0x91,0x00,0x20 = bclr 12, 17, 0 +// 0x4d,0x92,0x00,0x20 = bclr 12, 18, 0 +// 0x4d,0x93,0x00,0x20 = bclr 12, 19, 0 +// 0x4d,0x93,0x00,0x20 = bclr 12, 19, 0 +// 0x4d,0x94,0x00,0x20 = bclr 12, 20, 0 +// 0x4d,0x95,0x00,0x20 = bclr 12, 21, 0 +// 0x4d,0x96,0x00,0x20 = bclr 12, 22, 0 +// 0x4d,0x97,0x00,0x20 = bclr 12, 23, 0 +// 0x4d,0x97,0x00,0x20 = bclr 12, 23, 0 +// 0x4d,0x98,0x00,0x20 = bclr 12, 24, 0 +// 0x4d,0x99,0x00,0x20 = bclr 12, 25, 0 +// 0x4d,0x9a,0x00,0x20 = bclr 12, 26, 0 +// 0x4d,0x9b,0x00,0x20 = bclr 12, 27, 0 +// 0x4d,0x9b,0x00,0x20 = bclr 12, 27, 0 +// 0x4d,0x9c,0x00,0x20 = bclr 12, 28, 0 +// 0x4d,0x9d,0x00,0x20 = bclr 12, 29, 0 +// 0x4d,0x9e,0x00,0x20 = bclr 12, 30, 0 +// 0x4d,0x9f,0x00,0x20 = bclr 12, 31, 0 +// 0x4d,0x9f,0x00,0x20 = bclr 12, 31, 0 +0x4e,0x80,0x00,0x20 = blr +0x4e,0x80,0x04,0x20 = bctr +0x4e,0x80,0x00,0x21 = blrl +0x4e,0x80,0x04,0x21 = bctrl +// 0x4d,0x82,0x00,0x20 = bclr 12, 2, 0 +// 0x4d,0x82,0x04,0x20 = bcctr 12, 2, 0 +// 0x4d,0x82,0x00,0x21 = bclrl 12, 2, 0 +// 0x4d,0x82,0x04,0x21 = bcctrl 12, 2, 0 +// 0x4d,0xe2,0x00,0x20 = bclr 15, 2, 0 +// 0x4d,0xe2,0x04,0x20 = bcctr 15, 2, 0 +// 0x4d,0xe2,0x00,0x21 = bclrl 15, 2, 0 +// 0x4d,0xe2,0x04,0x21 = bcctrl 15, 2, 0 +// 0x4d,0xc2,0x00,0x20 = bclr 14, 2, 0 +// 0x4d,0xc2,0x04,0x20 = bcctr 14, 2, 0 +// 0x4d,0xc2,0x00,0x21 = bclrl 14, 2, 0 +// 0x4d,0xc2,0x04,0x21 = bcctrl 14, 2, 0 +// 0x4c,0x82,0x00,0x20 = bclr 4, 2, 0 +// 0x4c,0x82,0x04,0x20 = bcctr 4, 2, 0 +// 0x4c,0x82,0x00,0x21 = bclrl 4, 2, 0 +// 0x4c,0x82,0x04,0x21 = bcctrl 4, 2, 0 +// 0x4c,0xe2,0x00,0x20 = bclr 7, 2, 0 +// 0x4c,0xe2,0x04,0x20 = bcctr 7, 2, 0 +// 0x4c,0xe2,0x00,0x21 = bclrl 7, 2, 0 +// 0x4c,0xe2,0x04,0x21 = bcctrl 7, 2, 0 +// 0x4c,0xc2,0x00,0x20 = bclr 6, 2, 0 +// 0x4c,0xc2,0x04,0x20 = bcctr 6, 2, 0 +// 0x4c,0xc2,0x00,0x21 = bclrl 6, 2, 0 +// 0x4c,0xc2,0x04,0x21 = bcctrl 6, 2, 0 +0x4e,0x00,0x00,0x20 = bdnzlr +0x4e,0x00,0x00,0x21 = bdnzlrl +0x4f,0x20,0x00,0x20 = bdnzlr+ +0x4f,0x20,0x00,0x21 = bdnzlrl+ +0x4f,0x00,0x00,0x20 = bdnzlr- +0x4f,0x00,0x00,0x21 = bdnzlrl- +// 0x4d,0x02,0x00,0x20 = bclr 8, 2, 0 +// 0x4d,0x02,0x00,0x21 = bclrl 8, 2, 0 +// 0x4c,0x02,0x00,0x20 = bclr 0, 2, 0 +// 0x4c,0x02,0x00,0x21 = bclrl 0, 2, 0 +0x4e,0x40,0x00,0x20 = bdzlr +0x4e,0x40,0x00,0x21 = bdzlrl +0x4f,0x60,0x00,0x20 = bdzlr+ +0x4f,0x60,0x00,0x21 = bdzlrl+ +0x4f,0x40,0x00,0x20 = bdzlr- +0x4f,0x40,0x00,0x21 = bdzlrl- +// 0x4d,0x42,0x00,0x20 = bclr 10, 2, 0 +// 0x4d,0x42,0x00,0x21 = bclrl 10, 2, 0 +// 0x4c,0x42,0x00,0x20 = bclr 2, 2, 0 +// 0x4c,0x42,0x00,0x21 = bclrl 2, 2, 0 +// 0x4d,0x88,0x00,0x20 = bltlr 2 +// 0x4d,0x80,0x00,0x20 = bltlr 0 +// 0x4d,0x88,0x04,0x20 = bltctr 2 +// 0x4d,0x80,0x04,0x20 = bltctr 0 +// 0x4d,0x88,0x00,0x21 = bltlrl 2 +// 0x4d,0x80,0x00,0x21 = bltlrl 0 +// 0x4d,0x88,0x04,0x21 = bltctrl 2 +// 0x4d,0x80,0x04,0x21 = bltctrl 0 +// 0x4d,0xe8,0x00,0x20 = bltlr+ 2 +// 0x4d,0xe0,0x00,0x20 = bltlr+ 0 +// 0x4d,0xe8,0x04,0x20 = bltctr+ 2 +// 0x4d,0xe0,0x04,0x20 = bltctr+ 0 +// 0x4d,0xe8,0x00,0x21 = bltlrl+ 2 +// 0x4d,0xe0,0x00,0x21 = bltlrl+ 0 +// 0x4d,0xe8,0x04,0x21 = bltctrl+ 2 +// 0x4d,0xe0,0x04,0x21 = bltctrl+ 0 +// 0x4d,0xc8,0x00,0x20 = bltlr- 2 +// 0x4d,0xc0,0x00,0x20 = bltlr- 0 +// 0x4d,0xc8,0x04,0x20 = bltctr- 2 +// 0x4d,0xc0,0x04,0x20 = bltctr- 0 +// 0x4d,0xc8,0x00,0x21 = bltlrl- 2 +// 0x4d,0xc0,0x00,0x21 = bltlrl- 0 +// 0x4d,0xc8,0x04,0x21 = bltctrl- 2 +// 0x4d,0xc0,0x04,0x21 = bltctrl- 0 +// 0x4c,0x89,0x00,0x20 = blelr 2 +// 0x4c,0x81,0x00,0x20 = blelr 0 +// 0x4c,0x89,0x04,0x20 = blectr 2 +// 0x4c,0x81,0x04,0x20 = blectr 0 +// 0x4c,0x89,0x00,0x21 = blelrl 2 +// 0x4c,0x81,0x00,0x21 = blelrl 0 +// 0x4c,0x89,0x04,0x21 = blectrl 2 +// 0x4c,0x81,0x04,0x21 = blectrl 0 +// 0x4c,0xe9,0x00,0x20 = blelr+ 2 +// 0x4c,0xe1,0x00,0x20 = blelr+ 0 +// 0x4c,0xe9,0x04,0x20 = blectr+ 2 +// 0x4c,0xe1,0x04,0x20 = blectr+ 0 +// 0x4c,0xe9,0x00,0x21 = blelrl+ 2 +// 0x4c,0xe1,0x00,0x21 = blelrl+ 0 +// 0x4c,0xe9,0x04,0x21 = blectrl+ 2 +// 0x4c,0xe1,0x04,0x21 = blectrl+ 0 +// 0x4c,0xc9,0x00,0x20 = blelr- 2 +// 0x4c,0xc1,0x00,0x20 = blelr- 0 +// 0x4c,0xc9,0x04,0x20 = blectr- 2 +// 0x4c,0xc1,0x04,0x20 = blectr- 0 +// 0x4c,0xc9,0x00,0x21 = blelrl- 2 +// 0x4c,0xc1,0x00,0x21 = blelrl- 0 +// 0x4c,0xc9,0x04,0x21 = blectrl- 2 +// 0x4c,0xc1,0x04,0x21 = blectrl- 0 +// 0x4d,0x8a,0x00,0x20 = beqlr 2 +// 0x4d,0x82,0x00,0x20 = beqlr 0 +// 0x4d,0x8a,0x04,0x20 = beqctr 2 +// 0x4d,0x82,0x04,0x20 = beqctr 0 +// 0x4d,0x8a,0x00,0x21 = beqlrl 2 +// 0x4d,0x82,0x00,0x21 = beqlrl 0 +// 0x4d,0x8a,0x04,0x21 = beqctrl 2 +// 0x4d,0x82,0x04,0x21 = beqctrl 0 +// 0x4d,0xea,0x00,0x20 = beqlr+ 2 +// 0x4d,0xe2,0x00,0x20 = beqlr+ 0 +// 0x4d,0xea,0x04,0x20 = beqctr+ 2 +// 0x4d,0xe2,0x04,0x20 = beqctr+ 0 +// 0x4d,0xea,0x00,0x21 = beqlrl+ 2 +// 0x4d,0xe2,0x00,0x21 = beqlrl+ 0 +// 0x4d,0xea,0x04,0x21 = beqctrl+ 2 +// 0x4d,0xe2,0x04,0x21 = beqctrl+ 0 +// 0x4d,0xca,0x00,0x20 = beqlr- 2 +// 0x4d,0xc2,0x00,0x20 = beqlr- 0 +// 0x4d,0xca,0x04,0x20 = beqctr- 2 +// 0x4d,0xc2,0x04,0x20 = beqctr- 0 +// 0x4d,0xca,0x00,0x21 = beqlrl- 2 +// 0x4d,0xc2,0x00,0x21 = beqlrl- 0 +// 0x4d,0xca,0x04,0x21 = beqctrl- 2 +// 0x4d,0xc2,0x04,0x21 = beqctrl- 0 +// 0x4c,0x88,0x00,0x20 = bgelr 2 +// 0x4c,0x80,0x00,0x20 = bgelr 0 +// 0x4c,0x88,0x04,0x20 = bgectr 2 +// 0x4c,0x80,0x04,0x20 = bgectr 0 +// 0x4c,0x88,0x00,0x21 = bgelrl 2 +// 0x4c,0x80,0x00,0x21 = bgelrl 0 +// 0x4c,0x88,0x04,0x21 = bgectrl 2 +// 0x4c,0x80,0x04,0x21 = bgectrl 0 +// 0x4c,0xe8,0x00,0x20 = bgelr+ 2 +// 0x4c,0xe0,0x00,0x20 = bgelr+ 0 +// 0x4c,0xe8,0x04,0x20 = bgectr+ 2 +// 0x4c,0xe0,0x04,0x20 = bgectr+ 0 +// 0x4c,0xe8,0x00,0x21 = bgelrl+ 2 +// 0x4c,0xe0,0x00,0x21 = bgelrl+ 0 +// 0x4c,0xe8,0x04,0x21 = bgectrl+ 2 +// 0x4c,0xe0,0x04,0x21 = bgectrl+ 0 +// 0x4c,0xc8,0x00,0x20 = bgelr- 2 +// 0x4c,0xc0,0x00,0x20 = bgelr- 0 +// 0x4c,0xc8,0x04,0x20 = bgectr- 2 +// 0x4c,0xc0,0x04,0x20 = bgectr- 0 +// 0x4c,0xc8,0x00,0x21 = bgelrl- 2 +// 0x4c,0xc0,0x00,0x21 = bgelrl- 0 +// 0x4c,0xc8,0x04,0x21 = bgectrl- 2 +// 0x4c,0xc0,0x04,0x21 = bgectrl- 0 +// 0x4d,0x89,0x00,0x20 = bgtlr 2 +// 0x4d,0x81,0x00,0x20 = bgtlr 0 +// 0x4d,0x89,0x04,0x20 = bgtctr 2 +// 0x4d,0x81,0x04,0x20 = bgtctr 0 +// 0x4d,0x89,0x00,0x21 = bgtlrl 2 +// 0x4d,0x81,0x00,0x21 = bgtlrl 0 +// 0x4d,0x89,0x04,0x21 = bgtctrl 2 +// 0x4d,0x81,0x04,0x21 = bgtctrl 0 +// 0x4d,0xe9,0x00,0x20 = bgtlr+ 2 +// 0x4d,0xe1,0x00,0x20 = bgtlr+ 0 +// 0x4d,0xe9,0x04,0x20 = bgtctr+ 2 +// 0x4d,0xe1,0x04,0x20 = bgtctr+ 0 +// 0x4d,0xe9,0x00,0x21 = bgtlrl+ 2 +// 0x4d,0xe1,0x00,0x21 = bgtlrl+ 0 +// 0x4d,0xe9,0x04,0x21 = bgtctrl+ 2 +// 0x4d,0xe1,0x04,0x21 = bgtctrl+ 0 +// 0x4d,0xc9,0x00,0x20 = bgtlr- 2 +// 0x4d,0xc1,0x00,0x20 = bgtlr- 0 +// 0x4d,0xc9,0x04,0x20 = bgtctr- 2 +// 0x4d,0xc1,0x04,0x20 = bgtctr- 0 +// 0x4d,0xc9,0x00,0x21 = bgtlrl- 2 +// 0x4d,0xc1,0x00,0x21 = bgtlrl- 0 +// 0x4d,0xc9,0x04,0x21 = bgtctrl- 2 +// 0x4d,0xc1,0x04,0x21 = bgtctrl- 0 +// 0x4c,0x88,0x00,0x20 = bgelr 2 +// 0x4c,0x80,0x00,0x20 = bgelr 0 +// 0x4c,0x88,0x04,0x20 = bgectr 2 +// 0x4c,0x80,0x04,0x20 = bgectr 0 +// 0x4c,0x88,0x00,0x21 = bgelrl 2 +// 0x4c,0x80,0x00,0x21 = bgelrl 0 +// 0x4c,0x88,0x04,0x21 = bgectrl 2 +// 0x4c,0x80,0x04,0x21 = bgectrl 0 +// 0x4c,0xe8,0x00,0x20 = bgelr+ 2 +// 0x4c,0xe0,0x00,0x20 = bgelr+ 0 +// 0x4c,0xe8,0x04,0x20 = bgectr+ 2 +// 0x4c,0xe0,0x04,0x20 = bgectr+ 0 +// 0x4c,0xe8,0x00,0x21 = bgelrl+ 2 +// 0x4c,0xe0,0x00,0x21 = bgelrl+ 0 +// 0x4c,0xe8,0x04,0x21 = bgectrl+ 2 +// 0x4c,0xe0,0x04,0x21 = bgectrl+ 0 +// 0x4c,0xc8,0x00,0x20 = bgelr- 2 +// 0x4c,0xc0,0x00,0x20 = bgelr- 0 +// 0x4c,0xc8,0x04,0x20 = bgectr- 2 +// 0x4c,0xc0,0x04,0x20 = bgectr- 0 +// 0x4c,0xc8,0x00,0x21 = bgelrl- 2 +// 0x4c,0xc0,0x00,0x21 = bgelrl- 0 +// 0x4c,0xc8,0x04,0x21 = bgectrl- 2 +// 0x4c,0xc0,0x04,0x21 = bgectrl- 0 +// 0x4c,0x8a,0x00,0x20 = bnelr 2 +// 0x4c,0x82,0x00,0x20 = bnelr 0 +// 0x4c,0x8a,0x04,0x20 = bnectr 2 +// 0x4c,0x82,0x04,0x20 = bnectr 0 +// 0x4c,0x8a,0x00,0x21 = bnelrl 2 +// 0x4c,0x82,0x00,0x21 = bnelrl 0 +// 0x4c,0x8a,0x04,0x21 = bnectrl 2 +// 0x4c,0x82,0x04,0x21 = bnectrl 0 +// 0x4c,0xea,0x00,0x20 = bnelr+ 2 +// 0x4c,0xe2,0x00,0x20 = bnelr+ 0 +// 0x4c,0xea,0x04,0x20 = bnectr+ 2 +// 0x4c,0xe2,0x04,0x20 = bnectr+ 0 +// 0x4c,0xea,0x00,0x21 = bnelrl+ 2 +// 0x4c,0xe2,0x00,0x21 = bnelrl+ 0 +// 0x4c,0xea,0x04,0x21 = bnectrl+ 2 +// 0x4c,0xe2,0x04,0x21 = bnectrl+ 0 +// 0x4c,0xca,0x00,0x20 = bnelr- 2 +// 0x4c,0xc2,0x00,0x20 = bnelr- 0 +// 0x4c,0xca,0x04,0x20 = bnectr- 2 +// 0x4c,0xc2,0x04,0x20 = bnectr- 0 +// 0x4c,0xca,0x00,0x21 = bnelrl- 2 +// 0x4c,0xc2,0x00,0x21 = bnelrl- 0 +// 0x4c,0xca,0x04,0x21 = bnectrl- 2 +// 0x4c,0xc2,0x04,0x21 = bnectrl- 0 +// 0x4c,0x89,0x00,0x20 = blelr 2 +// 0x4c,0x81,0x00,0x20 = blelr 0 +// 0x4c,0x89,0x04,0x20 = blectr 2 +// 0x4c,0x81,0x04,0x20 = blectr 0 +// 0x4c,0x89,0x00,0x21 = blelrl 2 +// 0x4c,0x81,0x00,0x21 = blelrl 0 +// 0x4c,0x89,0x04,0x21 = blectrl 2 +// 0x4c,0x81,0x04,0x21 = blectrl 0 +// 0x4c,0xe9,0x00,0x20 = blelr+ 2 +// 0x4c,0xe1,0x00,0x20 = blelr+ 0 +// 0x4c,0xe9,0x04,0x20 = blectr+ 2 +// 0x4c,0xe1,0x04,0x20 = blectr+ 0 +// 0x4c,0xe9,0x00,0x21 = blelrl+ 2 +// 0x4c,0xe1,0x00,0x21 = blelrl+ 0 +// 0x4c,0xe9,0x04,0x21 = blectrl+ 2 +// 0x4c,0xe1,0x04,0x21 = blectrl+ 0 +// 0x4c,0xc9,0x00,0x20 = blelr- 2 +// 0x4c,0xc1,0x00,0x20 = blelr- 0 +// 0x4c,0xc9,0x04,0x20 = blectr- 2 +// 0x4c,0xc1,0x04,0x20 = blectr- 0 +// 0x4c,0xc9,0x00,0x21 = blelrl- 2 +// 0x4c,0xc1,0x00,0x21 = blelrl- 0 +// 0x4c,0xc9,0x04,0x21 = blectrl- 2 +// 0x4c,0xc1,0x04,0x21 = blectrl- 0 +// 0x4d,0x8b,0x00,0x20 = bunlr 2 +// 0x4d,0x83,0x00,0x20 = bunlr 0 +// 0x4d,0x8b,0x04,0x20 = bunctr 2 +// 0x4d,0x83,0x04,0x20 = bunctr 0 +// 0x4d,0x8b,0x00,0x21 = bunlrl 2 +// 0x4d,0x83,0x00,0x21 = bunlrl 0 +// 0x4d,0x8b,0x04,0x21 = bunctrl 2 +// 0x4d,0x83,0x04,0x21 = bunctrl 0 +// 0x4d,0xeb,0x00,0x20 = bunlr+ 2 +// 0x4d,0xe3,0x00,0x20 = bunlr+ 0 +// 0x4d,0xeb,0x04,0x20 = bunctr+ 2 +// 0x4d,0xe3,0x04,0x20 = bunctr+ 0 +// 0x4d,0xeb,0x00,0x21 = bunlrl+ 2 +// 0x4d,0xe3,0x00,0x21 = bunlrl+ 0 +// 0x4d,0xeb,0x04,0x21 = bunctrl+ 2 +// 0x4d,0xe3,0x04,0x21 = bunctrl+ 0 +// 0x4d,0xcb,0x00,0x20 = bunlr- 2 +// 0x4d,0xc3,0x00,0x20 = bunlr- 0 +// 0x4d,0xcb,0x04,0x20 = bunctr- 2 +// 0x4d,0xc3,0x04,0x20 = bunctr- 0 +// 0x4d,0xcb,0x00,0x21 = bunlrl- 2 +// 0x4d,0xc3,0x00,0x21 = bunlrl- 0 +// 0x4d,0xcb,0x04,0x21 = bunctrl- 2 +// 0x4d,0xc3,0x04,0x21 = bunctrl- 0 +// 0x4c,0x8b,0x00,0x20 = bnulr 2 +// 0x4c,0x83,0x00,0x20 = bnulr 0 +// 0x4c,0x8b,0x04,0x20 = bnuctr 2 +// 0x4c,0x83,0x04,0x20 = bnuctr 0 +// 0x4c,0x8b,0x00,0x21 = bnulrl 2 +// 0x4c,0x83,0x00,0x21 = bnulrl 0 +// 0x4c,0x8b,0x04,0x21 = bnuctrl 2 +// 0x4c,0x83,0x04,0x21 = bnuctrl 0 +// 0x4c,0xeb,0x00,0x20 = bnulr+ 2 +// 0x4c,0xe3,0x00,0x20 = bnulr+ 0 +// 0x4c,0xeb,0x04,0x20 = bnuctr+ 2 +// 0x4c,0xe3,0x04,0x20 = bnuctr+ 0 +// 0x4c,0xeb,0x00,0x21 = bnulrl+ 2 +// 0x4c,0xe3,0x00,0x21 = bnulrl+ 0 +// 0x4c,0xeb,0x04,0x21 = bnuctrl+ 2 +// 0x4c,0xe3,0x04,0x21 = bnuctrl+ 0 +// 0x4c,0xcb,0x00,0x20 = bnulr- 2 +// 0x4c,0xc3,0x00,0x20 = bnulr- 0 +// 0x4c,0xcb,0x04,0x20 = bnuctr- 2 +// 0x4c,0xc3,0x04,0x20 = bnuctr- 0 +// 0x4c,0xcb,0x00,0x21 = bnulrl- 2 +// 0x4c,0xc3,0x00,0x21 = bnulrl- 0 +// 0x4c,0xcb,0x04,0x21 = bnuctrl- 2 +// 0x4c,0xc3,0x04,0x21 = bnuctrl- 0 +// 0x4d,0x8b,0x00,0x20 = bunlr 2 +// 0x4d,0x83,0x00,0x20 = bunlr 0 +// 0x4d,0x8b,0x04,0x20 = bunctr 2 +// 0x4d,0x83,0x04,0x20 = bunctr 0 +// 0x4d,0x8b,0x00,0x21 = bunlrl 2 +// 0x4d,0x83,0x00,0x21 = bunlrl 0 +// 0x4d,0x8b,0x04,0x21 = bunctrl 2 +// 0x4d,0x83,0x04,0x21 = bunctrl 0 +// 0x4d,0xeb,0x00,0x20 = bunlr+ 2 +// 0x4d,0xe3,0x00,0x20 = bunlr+ 0 +// 0x4d,0xeb,0x04,0x20 = bunctr+ 2 +// 0x4d,0xe3,0x04,0x20 = bunctr+ 0 +// 0x4d,0xeb,0x00,0x21 = bunlrl+ 2 +// 0x4d,0xe3,0x00,0x21 = bunlrl+ 0 +// 0x4d,0xeb,0x04,0x21 = bunctrl+ 2 +// 0x4d,0xe3,0x04,0x21 = bunctrl+ 0 +// 0x4d,0xcb,0x00,0x20 = bunlr- 2 +// 0x4d,0xc3,0x00,0x20 = bunlr- 0 +// 0x4d,0xcb,0x04,0x20 = bunctr- 2 +// 0x4d,0xc3,0x04,0x20 = bunctr- 0 +// 0x4d,0xcb,0x00,0x21 = bunlrl- 2 +// 0x4d,0xc3,0x00,0x21 = bunlrl- 0 +// 0x4d,0xcb,0x04,0x21 = bunctrl- 2 +// 0x4d,0xc3,0x04,0x21 = bunctrl- 0 +// 0x4c,0x8b,0x00,0x20 = bnulr 2 +// 0x4c,0x83,0x00,0x20 = bnulr 0 +// 0x4c,0x8b,0x04,0x20 = bnuctr 2 +// 0x4c,0x83,0x04,0x20 = bnuctr 0 +// 0x4c,0x8b,0x00,0x21 = bnulrl 2 +// 0x4c,0x83,0x00,0x21 = bnulrl 0 +// 0x4c,0x8b,0x04,0x21 = bnuctrl 2 +// 0x4c,0x83,0x04,0x21 = bnuctrl 0 +// 0x4c,0xeb,0x00,0x20 = bnulr+ 2 +// 0x4c,0xe3,0x00,0x20 = bnulr+ 0 +// 0x4c,0xeb,0x04,0x20 = bnuctr+ 2 +// 0x4c,0xe3,0x04,0x20 = bnuctr+ 0 +// 0x4c,0xeb,0x00,0x21 = bnulrl+ 2 +// 0x4c,0xe3,0x00,0x21 = bnulrl+ 0 +// 0x4c,0xeb,0x04,0x21 = bnuctrl+ 2 +// 0x4c,0xe3,0x04,0x21 = bnuctrl+ 0 +// 0x4c,0xcb,0x00,0x20 = bnulr- 2 +// 0x4c,0xc3,0x00,0x20 = bnulr- 0 +// 0x4c,0xcb,0x04,0x20 = bnuctr- 2 +// 0x4c,0xc3,0x04,0x20 = bnuctr- 0 +// 0x4c,0xcb,0x00,0x21 = bnulrl- 2 +// 0x4c,0xc3,0x00,0x21 = bnulrl- 0 +// 0x4c,0xcb,0x04,0x21 = bnuctrl- 2 +// 0x4c,0xc3,0x04,0x21 = bnuctrl- 0 +// 0x4c,0x42,0x12,0x42 = creqv 2, 2, 2 +// 0x4c,0x42,0x11,0x82 = crxor 2, 2, 2 +// 0x4c,0x43,0x1b,0x82 = cror 2, 3, 3 +// 0x4c,0x43,0x18,0x42 = crnor 2, 3, 3 +// 0x38,0x43,0xff,0x80 = addi 2, 3, -128 +// 0x3c,0x43,0xff,0x80 = addis 2, 3, -128 +// 0x30,0x43,0xff,0x80 = addic 2, 3, -128 +// 0x34,0x43,0xff,0x80 = addic. 2, 3, -128 +0x7c,0x44,0x18,0x50 = subf 2, 4, 3 +0x7c,0x44,0x18,0x51 = subf. 2, 4, 3 +0x7c,0x44,0x18,0x10 = subfc 2, 4, 3 +0x7c,0x44,0x18,0x11 = subfc. 2, 4, 3 +0x2d,0x23,0x00,0x80 = cmpdi 2, 3, 128 +// 0x2c,0x23,0x00,0x80 = cmpdi 0, 3, 128 +0x7d,0x23,0x20,0x00 = cmpd 2, 3, 4 +// 0x7c,0x23,0x20,0x00 = cmpd 0, 3, 4 +0x29,0x23,0x00,0x80 = cmpldi 2, 3, 128 +// 0x28,0x23,0x00,0x80 = cmpldi 0, 3, 128 +0x7d,0x23,0x20,0x40 = cmpld 2, 3, 4 +// 0x7c,0x23,0x20,0x40 = cmpld 0, 3, 4 +0x2d,0x03,0x00,0x80 = cmpwi 2, 3, 128 +// 0x2c,0x03,0x00,0x80 = cmpwi 0, 3, 128 +0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4 +// 0x7c,0x03,0x20,0x00 = cmpw 0, 3, 4 +0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128 +// 0x28,0x03,0x00,0x80 = cmplwi 0, 3, 128 +0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4 +// 0x7c,0x03,0x20,0x40 = cmplw 0, 3, 4 +// 0x0e,0x03,0x00,0x04 = twi 16, 3, 4 +// 0x7e,0x03,0x20,0x08 = tw 16, 3, 4 +// 0x0a,0x03,0x00,0x04 = tdi 16, 3, 4 +// 0x7e,0x03,0x20,0x88 = td 16, 3, 4 +0x0e,0x83,0x00,0x04 = twi 20, 3, 4 +0x7e,0x83,0x20,0x08 = tw 20, 3, 4 +0x0a,0x83,0x00,0x04 = tdi 20, 3, 4 +0x7e,0x83,0x20,0x88 = td 20, 3, 4 +// 0x0c,0x83,0x00,0x04 = twi 4, 3, 4 +// 0x7c,0x83,0x20,0x08 = tw 4, 3, 4 +// 0x08,0x83,0x00,0x04 = tdi 4, 3, 4 +// 0x7c,0x83,0x20,0x88 = td 4, 3, 4 +0x0d,0x83,0x00,0x04 = twi 12, 3, 4 +0x7d,0x83,0x20,0x08 = tw 12, 3, 4 +0x09,0x83,0x00,0x04 = tdi 12, 3, 4 +0x7d,0x83,0x20,0x88 = td 12, 3, 4 +// 0x0d,0x03,0x00,0x04 = twi 8, 3, 4 +// 0x7d,0x03,0x20,0x08 = tw 8, 3, 4 +// 0x09,0x03,0x00,0x04 = tdi 8, 3, 4 +// 0x7d,0x03,0x20,0x88 = td 8, 3, 4 +0x0d,0x83,0x00,0x04 = twi 12, 3, 4 +0x7d,0x83,0x20,0x08 = tw 12, 3, 4 +0x09,0x83,0x00,0x04 = tdi 12, 3, 4 +0x7d,0x83,0x20,0x88 = td 12, 3, 4 +// 0x0f,0x03,0x00,0x04 = twi 24, 3, 4 +// 0x7f,0x03,0x20,0x08 = tw 24, 3, 4 +// 0x0b,0x03,0x00,0x04 = tdi 24, 3, 4 +// 0x7f,0x03,0x20,0x88 = td 24, 3, 4 +0x0e,0x83,0x00,0x04 = twi 20, 3, 4 +0x7e,0x83,0x20,0x08 = tw 20, 3, 4 +0x0a,0x83,0x00,0x04 = tdi 20, 3, 4 +0x7e,0x83,0x20,0x88 = td 20, 3, 4 +// 0x0c,0x43,0x00,0x04 = twi 2, 3, 4 +// 0x7c,0x43,0x20,0x08 = tw 2, 3, 4 +// 0x08,0x43,0x00,0x04 = tdi 2, 3, 4 +// 0x7c,0x43,0x20,0x88 = td 2, 3, 4 +0x0c,0xc3,0x00,0x04 = twi 6, 3, 4 +0x7c,0xc3,0x20,0x08 = tw 6, 3, 4 +0x08,0xc3,0x00,0x04 = tdi 6, 3, 4 +0x7c,0xc3,0x20,0x88 = td 6, 3, 4 +0x0c,0xa3,0x00,0x04 = twi 5, 3, 4 +0x7c,0xa3,0x20,0x08 = tw 5, 3, 4 +0x08,0xa3,0x00,0x04 = tdi 5, 3, 4 +0x7c,0xa3,0x20,0x88 = td 5, 3, 4 +// 0x0c,0x23,0x00,0x04 = twi 1, 3, 4 +// 0x7c,0x23,0x20,0x08 = tw 1, 3, 4 +// 0x08,0x23,0x00,0x04 = tdi 1, 3, 4 +// 0x7c,0x23,0x20,0x88 = td 1, 3, 4 +0x0c,0xa3,0x00,0x04 = twi 5, 3, 4 +0x7c,0xa3,0x20,0x08 = tw 5, 3, 4 +0x08,0xa3,0x00,0x04 = tdi 5, 3, 4 +0x7c,0xa3,0x20,0x88 = td 5, 3, 4 +0x0c,0xc3,0x00,0x04 = twi 6, 3, 4 +0x7c,0xc3,0x20,0x08 = tw 6, 3, 4 +0x08,0xc3,0x00,0x04 = tdi 6, 3, 4 +0x7c,0xc3,0x20,0x88 = td 6, 3, 4 +// 0x0f,0xe3,0x00,0x04 = twi 31, 3, 4 +// 0x7f,0xe3,0x20,0x08 = tw 31, 3, 4 +// 0x0b,0xe3,0x00,0x04 = tdi 31, 3, 4 +// 0x7f,0xe3,0x20,0x88 = td 31, 3, 4 +0x7f,0xe0,0x00,0x08 = trap +0x78,0x62,0x28,0xc4 = rldicr 2, 3, 5, 3 +0x78,0x62,0x28,0xc5 = rldicr. 2, 3, 5, 3 +0x78,0x62,0x4f,0x20 = rldicl 2, 3, 9, 60 +0x78,0x62,0x4f,0x21 = rldicl. 2, 3, 9, 60 +0x78,0x62,0xb9,0x4e = rldimi 2, 3, 55, 5 +0x78,0x62,0xb9,0x4f = rldimi. 2, 3, 55, 5 +// 0x78,0x62,0x20,0x00 = rldicl 2, 3, 4, 0 +// 0x78,0x62,0x20,0x01 = rldicl. 2, 3, 4, 0 +// 0x78,0x62,0xe0,0x02 = rldicl 2, 3, 60, 0 +// 0x78,0x62,0xe0,0x03 = rldicl. 2, 3, 60, 0 +// 0x78,0x62,0x20,0x10 = rldcl 2, 3, 4, 0 +// 0x78,0x62,0x20,0x11 = rldcl. 2, 3, 4, 0 +0x78,0x62,0x26,0xe4 = sldi 2, 3, 4 +0x78,0x62,0x26,0xe5 = rldicr. 2, 3, 4, 59 +0x78,0x62,0xe1,0x02 = rldicl 2, 3, 60, 4 +0x78,0x62,0xe1,0x03 = rldicl. 2, 3, 60, 4 +// 0x78,0x62,0x01,0x00 = rldicl 2, 3, 0, 4 +// 0x78,0x62,0x01,0x01 = rldicl. 2, 3, 0, 4 +0x78,0x62,0x06,0xe4 = rldicr 2, 3, 0, 59 +0x78,0x62,0x06,0xe5 = rldicr. 2, 3, 0, 59 +0x78,0x62,0x20,0x48 = rldic 2, 3, 4, 1 +0x78,0x62,0x20,0x49 = rldic. 2, 3, 4, 1 +0x54,0x62,0x28,0x06 = rlwinm 2, 3, 5, 0, 3 +0x54,0x62,0x28,0x07 = rlwinm. 2, 3, 5, 0, 3 +0x54,0x62,0x4f,0x3e = rlwinm 2, 3, 9, 28, 31 +0x54,0x62,0x4f,0x3f = rlwinm. 2, 3, 9, 28, 31 +0x50,0x62,0xd9,0x50 = rlwimi 2, 3, 27, 5, 8 +0x50,0x62,0xd9,0x51 = rlwimi. 2, 3, 27, 5, 8 +0x50,0x62,0xb9,0x50 = rlwimi 2, 3, 23, 5, 8 +0x50,0x62,0xb9,0x51 = rlwimi. 2, 3, 23, 5, 8 +// 0x54,0x62,0x20,0x3e = rlwinm 2, 3, 4, 0, 31 +// 0x54,0x62,0x20,0x3f = rlwinm. 2, 3, 4, 0, 31 +// 0x54,0x62,0xe0,0x3e = rlwinm 2, 3, 28, 0, 31 +// 0x54,0x62,0xe0,0x3f = rlwinm. 2, 3, 28, 0, 31 +// 0x5c,0x62,0x20,0x3e = rlwnm 2, 3, 4, 0, 31 +// 0x5c,0x62,0x20,0x3f = rlwnm. 2, 3, 4, 0, 31 +0x54,0x62,0x20,0x36 = slwi 2, 3, 4 +0x54,0x62,0x20,0x37 = rlwinm. 2, 3, 4, 0, 27 +0x54,0x62,0xe1,0x3e = srwi 2, 3, 4 +0x54,0x62,0xe1,0x3f = rlwinm. 2, 3, 28, 4, 31 +// 0x54,0x62,0x01,0x3e = rlwinm 2, 3, 0, 4, 31 +// 0x54,0x62,0x01,0x3f = rlwinm. 2, 3, 0, 4, 31 +0x54,0x62,0x00,0x36 = rlwinm 2, 3, 0, 0, 27 +0x54,0x62,0x00,0x37 = rlwinm. 2, 3, 0, 0, 27 +0x54,0x62,0x20,0x76 = rlwinm 2, 3, 4, 1, 27 +0x54,0x62,0x20,0x77 = rlwinm. 2, 3, 4, 1, 27 +// 0x7c,0x41,0x03,0xa6 = mtspr 1, 2 +// 0x7c,0x41,0x02,0xa6 = mfspr 2, 1 +0x7c,0x48,0x03,0xa6 = mtlr 2 +0x7c,0x48,0x02,0xa6 = mflr 2 +0x7c,0x49,0x03,0xa6 = mtctr 2 +0x7c,0x49,0x02,0xa6 = mfctr 2 +0x60,0x00,0x00,0x00 = nop +// 0x68,0x00,0x00,0x00 = xori 0, 0, 0 +0x38,0x40,0x00,0x80 = li 2, 128 +0x3c,0x40,0x00,0x80 = lis 2, 128 +0x7c,0x62,0x1b,0x78 = mr 2, 3 +0x7c,0x62,0x1b,0x79 = or. 2, 3, 3 +0x7c,0x62,0x18,0xf8 = nor 2, 3, 3 +0x7c,0x62,0x18,0xf9 = nor. 2, 3, 3 +0x7c,0x4f,0xf1,0x20 = mtcrf 255, 2 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-fp.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-fp.s.cs new file mode 100644 index 0000000..ace222d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-fp.s.cs @@ -0,0 +1,110 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +0xc0,0x44,0x00,0x80 = lfs 2, 128(4) +0x7c,0x43,0x24,0x2e = lfsx 2, 3, 4 +0xc4,0x44,0x00,0x80 = lfsu 2, 128(4) +0x7c,0x43,0x24,0x6e = lfsux 2, 3, 4 +0xc8,0x44,0x00,0x80 = lfd 2, 128(4) +0x7c,0x43,0x24,0xae = lfdx 2, 3, 4 +0xcc,0x44,0x00,0x80 = lfdu 2, 128(4) +0x7c,0x43,0x24,0xee = lfdux 2, 3, 4 +0x7c,0x43,0x26,0xae = lfiwax 2, 3, 4 +0x7c,0x43,0x26,0xee = lfiwzx 2, 3, 4 +0xd0,0x44,0x00,0x80 = stfs 2, 128(4) +0x7c,0x43,0x25,0x2e = stfsx 2, 3, 4 +0xd4,0x44,0x00,0x80 = stfsu 2, 128(4) +0x7c,0x43,0x25,0x6e = stfsux 2, 3, 4 +0xd8,0x44,0x00,0x80 = stfd 2, 128(4) +0x7c,0x43,0x25,0xae = stfdx 2, 3, 4 +0xdc,0x44,0x00,0x80 = stfdu 2, 128(4) +0x7c,0x43,0x25,0xee = stfdux 2, 3, 4 +0x7c,0x43,0x27,0xae = stfiwx 2, 3, 4 +0xfc,0x40,0x18,0x90 = fmr 2, 3 +0xfc,0x40,0x18,0x91 = fmr. 2, 3 +0xfc,0x40,0x18,0x50 = fneg 2, 3 +0xfc,0x40,0x18,0x51 = fneg. 2, 3 +0xfc,0x40,0x1a,0x10 = fabs 2, 3 +0xfc,0x40,0x1a,0x11 = fabs. 2, 3 +0xfc,0x40,0x19,0x10 = fnabs 2, 3 +0xfc,0x40,0x19,0x11 = fnabs. 2, 3 +0xfc,0x43,0x20,0x10 = fcpsgn 2, 3, 4 +0xfc,0x43,0x20,0x11 = fcpsgn. 2, 3, 4 +0xfc,0x43,0x20,0x2a = fadd 2, 3, 4 +0xfc,0x43,0x20,0x2b = fadd. 2, 3, 4 +0xec,0x43,0x20,0x2a = fadds 2, 3, 4 +0xec,0x43,0x20,0x2b = fadds. 2, 3, 4 +0xfc,0x43,0x20,0x28 = fsub 2, 3, 4 +0xfc,0x43,0x20,0x29 = fsub. 2, 3, 4 +0xec,0x43,0x20,0x28 = fsubs 2, 3, 4 +0xec,0x43,0x20,0x29 = fsubs. 2, 3, 4 +0xfc,0x43,0x01,0x32 = fmul 2, 3, 4 +0xfc,0x43,0x01,0x33 = fmul. 2, 3, 4 +0xec,0x43,0x01,0x32 = fmuls 2, 3, 4 +0xec,0x43,0x01,0x33 = fmuls. 2, 3, 4 +0xfc,0x43,0x20,0x24 = fdiv 2, 3, 4 +0xfc,0x43,0x20,0x25 = fdiv. 2, 3, 4 +0xec,0x43,0x20,0x24 = fdivs 2, 3, 4 +0xec,0x43,0x20,0x25 = fdivs. 2, 3, 4 +0xfc,0x40,0x18,0x2c = fsqrt 2, 3 +0xfc,0x40,0x18,0x2d = fsqrt. 2, 3 +0xec,0x40,0x18,0x2c = fsqrts 2, 3 +0xec,0x40,0x18,0x2d = fsqrts. 2, 3 +0xfc,0x40,0x18,0x30 = fre 2, 3 +0xfc,0x40,0x18,0x31 = fre. 2, 3 +0xec,0x40,0x18,0x30 = fres 2, 3 +0xec,0x40,0x18,0x31 = fres. 2, 3 +0xfc,0x40,0x18,0x34 = frsqrte 2, 3 +0xfc,0x40,0x18,0x35 = frsqrte. 2, 3 +0xec,0x40,0x18,0x34 = frsqrtes 2, 3 +0xec,0x40,0x18,0x35 = frsqrtes. 2, 3 +0xfc,0x43,0x29,0x3a = fmadd 2, 3, 4, 5 +0xfc,0x43,0x29,0x3b = fmadd. 2, 3, 4, 5 +0xec,0x43,0x29,0x3a = fmadds 2, 3, 4, 5 +0xec,0x43,0x29,0x3b = fmadds. 2, 3, 4, 5 +0xfc,0x43,0x29,0x38 = fmsub 2, 3, 4, 5 +0xfc,0x43,0x29,0x39 = fmsub. 2, 3, 4, 5 +0xec,0x43,0x29,0x38 = fmsubs 2, 3, 4, 5 +0xec,0x43,0x29,0x39 = fmsubs. 2, 3, 4, 5 +0xfc,0x43,0x29,0x3e = fnmadd 2, 3, 4, 5 +0xfc,0x43,0x29,0x3f = fnmadd. 2, 3, 4, 5 +0xec,0x43,0x29,0x3e = fnmadds 2, 3, 4, 5 +0xec,0x43,0x29,0x3f = fnmadds. 2, 3, 4, 5 +0xfc,0x43,0x29,0x3c = fnmsub 2, 3, 4, 5 +0xfc,0x43,0x29,0x3d = fnmsub. 2, 3, 4, 5 +0xec,0x43,0x29,0x3c = fnmsubs 2, 3, 4, 5 +0xec,0x43,0x29,0x3d = fnmsubs. 2, 3, 4, 5 +0xfc,0x40,0x18,0x18 = frsp 2, 3 +0xfc,0x40,0x18,0x19 = frsp. 2, 3 +0xfc,0x40,0x1e,0x5c = fctid 2, 3 +0xfc,0x40,0x1e,0x5d = fctid. 2, 3 +0xfc,0x40,0x1e,0x5e = fctidz 2, 3 +0xfc,0x40,0x1e,0x5f = fctidz. 2, 3 +0xfc,0x40,0x1f,0x5e = fctiduz 2, 3 +0xfc,0x40,0x1f,0x5f = fctiduz. 2, 3 +0xfc,0x40,0x18,0x1c = fctiw 2, 3 +0xfc,0x40,0x18,0x1d = fctiw. 2, 3 +0xfc,0x40,0x18,0x1e = fctiwz 2, 3 +0xfc,0x40,0x18,0x1f = fctiwz. 2, 3 +0xfc,0x40,0x19,0x1e = fctiwuz 2, 3 +0xfc,0x40,0x19,0x1f = fctiwuz. 2, 3 +0xfc,0x40,0x1e,0x9c = fcfid 2, 3 +0xfc,0x40,0x1e,0x9d = fcfid. 2, 3 +0xfc,0x40,0x1f,0x9c = fcfidu 2, 3 +0xfc,0x40,0x1f,0x9d = fcfidu. 2, 3 +0xec,0x40,0x1e,0x9c = fcfids 2, 3 +0xec,0x40,0x1e,0x9d = fcfids. 2, 3 +0xec,0x40,0x1f,0x9c = fcfidus 2, 3 +0xec,0x40,0x1f,0x9d = fcfidus. 2, 3 +0xfc,0x40,0x1b,0x10 = frin 2, 3 +0xfc,0x40,0x1b,0x11 = frin. 2, 3 +0xfc,0x40,0x1b,0x90 = frip 2, 3 +0xfc,0x40,0x1b,0x91 = frip. 2, 3 +0xfc,0x40,0x1b,0x50 = friz 2, 3 +0xfc,0x40,0x1b,0x51 = friz. 2, 3 +0xfc,0x40,0x1b,0xd0 = frim 2, 3 +0xfc,0x40,0x1b,0xd1 = frim. 2, 3 +0xfd,0x03,0x20,0x00 = fcmpu 2, 3, 4 +0xfc,0x43,0x29,0x2e = fsel 2, 3, 4, 5 +0xfc,0x43,0x29,0x2f = fsel. 2, 3, 4, 5 +0xfc,0x40,0x04,0x8e = mffs 2 +0xff,0xe0,0x00,0x8c = mtfsb0 31 +0xff,0xe0,0x00,0x4c = mtfsb1 31 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-vmx.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-vmx.s.cs new file mode 100644 index 0000000..087c082 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding-vmx.s.cs @@ -0,0 +1,170 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +0x7c,0x43,0x20,0x0e = lvebx 2, 3, 4 +0x7c,0x43,0x20,0x4e = lvehx 2, 3, 4 +0x7c,0x43,0x20,0x8e = lvewx 2, 3, 4 +0x7c,0x43,0x20,0xce = lvx 2, 3, 4 +0x7c,0x43,0x22,0xce = lvxl 2, 3, 4 +0x7c,0x43,0x21,0x0e = stvebx 2, 3, 4 +0x7c,0x43,0x21,0x4e = stvehx 2, 3, 4 +0x7c,0x43,0x21,0x8e = stvewx 2, 3, 4 +0x7c,0x43,0x21,0xce = stvx 2, 3, 4 +0x7c,0x43,0x23,0xce = stvxl 2, 3, 4 +0x7c,0x43,0x20,0x0c = lvsl 2, 3, 4 +0x7c,0x43,0x20,0x4c = lvsr 2, 3, 4 +0x10,0x43,0x23,0x0e = vpkpx 2, 3, 4 +0x10,0x43,0x21,0x8e = vpkshss 2, 3, 4 +0x10,0x43,0x21,0x0e = vpkshus 2, 3, 4 +0x10,0x43,0x21,0xce = vpkswss 2, 3, 4 +0x10,0x43,0x21,0x4e = vpkswus 2, 3, 4 +0x10,0x43,0x20,0x0e = vpkuhum 2, 3, 4 +0x10,0x43,0x20,0x8e = vpkuhus 2, 3, 4 +0x10,0x43,0x20,0x4e = vpkuwum 2, 3, 4 +0x10,0x43,0x20,0xce = vpkuwus 2, 3, 4 +0x10,0x40,0x1b,0x4e = vupkhpx 2, 3 +0x10,0x40,0x1a,0x0e = vupkhsb 2, 3 +0x10,0x40,0x1a,0x4e = vupkhsh 2, 3 +0x10,0x40,0x1b,0xce = vupklpx 2, 3 +0x10,0x40,0x1a,0x8e = vupklsb 2, 3 +0x10,0x40,0x1a,0xce = vupklsh 2, 3 +0x10,0x43,0x20,0x0c = vmrghb 2, 3, 4 +0x10,0x43,0x20,0x4c = vmrghh 2, 3, 4 +0x10,0x43,0x20,0x8c = vmrghw 2, 3, 4 +0x10,0x43,0x21,0x0c = vmrglb 2, 3, 4 +0x10,0x43,0x21,0x4c = vmrglh 2, 3, 4 +0x10,0x43,0x21,0x8c = vmrglw 2, 3, 4 +0x10,0x41,0x1a,0x0c = vspltb 2, 3, 1 +0x10,0x41,0x1a,0x4c = vsplth 2, 3, 1 +0x10,0x41,0x1a,0x8c = vspltw 2, 3, 1 +0x10,0x43,0x03,0x0c = vspltisb 2, 3 +0x10,0x43,0x03,0x4c = vspltish 2, 3 +0x10,0x43,0x03,0x8c = vspltisw 2, 3 +0x10,0x43,0x21,0x6b = vperm 2, 3, 4, 5 +0x10,0x43,0x21,0x6a = vsel 2, 3, 4, 5 +0x10,0x43,0x21,0xc4 = vsl 2, 3, 4 +0x10,0x43,0x21,0x6c = vsldoi 2, 3, 4, 5 +0x10,0x43,0x24,0x0c = vslo 2, 3, 4 +0x10,0x43,0x22,0xc4 = vsr 2, 3, 4 +0x10,0x43,0x24,0x4c = vsro 2, 3, 4 +0x10,0x43,0x21,0x80 = vaddcuw 2, 3, 4 +0x10,0x43,0x23,0x00 = vaddsbs 2, 3, 4 +0x10,0x43,0x23,0x40 = vaddshs 2, 3, 4 +0x10,0x43,0x23,0x80 = vaddsws 2, 3, 4 +0x10,0x43,0x20,0x00 = vaddubm 2, 3, 4 +0x10,0x43,0x20,0x40 = vadduhm 2, 3, 4 +0x10,0x43,0x20,0x80 = vadduwm 2, 3, 4 +0x10,0x43,0x22,0x00 = vaddubs 2, 3, 4 +0x10,0x43,0x22,0x40 = vadduhs 2, 3, 4 +0x10,0x43,0x22,0x80 = vadduws 2, 3, 4 +0x10,0x43,0x25,0x80 = vsubcuw 2, 3, 4 +0x10,0x43,0x27,0x00 = vsubsbs 2, 3, 4 +0x10,0x43,0x27,0x40 = vsubshs 2, 3, 4 +0x10,0x43,0x27,0x80 = vsubsws 2, 3, 4 +0x10,0x43,0x24,0x00 = vsububm 2, 3, 4 +0x10,0x43,0x24,0x40 = vsubuhm 2, 3, 4 +0x10,0x43,0x24,0x80 = vsubuwm 2, 3, 4 +0x10,0x43,0x26,0x00 = vsububs 2, 3, 4 +0x10,0x43,0x26,0x40 = vsubuhs 2, 3, 4 +0x10,0x43,0x26,0x80 = vsubuws 2, 3, 4 +0x10,0x43,0x23,0x08 = vmulesb 2, 3, 4 +0x10,0x43,0x23,0x48 = vmulesh 2, 3, 4 +0x10,0x43,0x22,0x08 = vmuleub 2, 3, 4 +0x10,0x43,0x22,0x48 = vmuleuh 2, 3, 4 +0x10,0x43,0x21,0x08 = vmulosb 2, 3, 4 +0x10,0x43,0x21,0x48 = vmulosh 2, 3, 4 +0x10,0x43,0x20,0x08 = vmuloub 2, 3, 4 +0x10,0x43,0x20,0x48 = vmulouh 2, 3, 4 +0x10,0x43,0x21,0x60 = vmhaddshs 2, 3, 4, 5 +0x10,0x43,0x21,0x61 = vmhraddshs 2, 3, 4, 5 +0x10,0x43,0x21,0x62 = vmladduhm 2, 3, 4, 5 +0x10,0x43,0x21,0x64 = vmsumubm 2, 3, 4, 5 +0x10,0x43,0x21,0x65 = vmsummbm 2, 3, 4, 5 +0x10,0x43,0x21,0x68 = vmsumshm 2, 3, 4, 5 +0x10,0x43,0x21,0x69 = vmsumshs 2, 3, 4, 5 +0x10,0x43,0x21,0x66 = vmsumuhm 2, 3, 4, 5 +0x10,0x43,0x21,0x67 = vmsumuhs 2, 3, 4, 5 +0x10,0x43,0x27,0x88 = vsumsws 2, 3, 4 +0x10,0x43,0x26,0x88 = vsum2sws 2, 3, 4 +0x10,0x43,0x27,0x08 = vsum4sbs 2, 3, 4 +0x10,0x43,0x26,0x48 = vsum4shs 2, 3, 4 +0x10,0x43,0x26,0x08 = vsum4ubs 2, 3, 4 +0x10,0x43,0x25,0x02 = vavgsb 2, 3, 4 +0x10,0x43,0x25,0x42 = vavgsh 2, 3, 4 +0x10,0x43,0x25,0x82 = vavgsw 2, 3, 4 +0x10,0x43,0x24,0x02 = vavgub 2, 3, 4 +0x10,0x43,0x24,0x42 = vavguh 2, 3, 4 +0x10,0x43,0x24,0x82 = vavguw 2, 3, 4 +0x10,0x43,0x21,0x02 = vmaxsb 2, 3, 4 +0x10,0x43,0x21,0x42 = vmaxsh 2, 3, 4 +0x10,0x43,0x21,0x82 = vmaxsw 2, 3, 4 +0x10,0x43,0x20,0x02 = vmaxub 2, 3, 4 +0x10,0x43,0x20,0x42 = vmaxuh 2, 3, 4 +0x10,0x43,0x20,0x82 = vmaxuw 2, 3, 4 +0x10,0x43,0x23,0x02 = vminsb 2, 3, 4 +0x10,0x43,0x23,0x42 = vminsh 2, 3, 4 +0x10,0x43,0x23,0x82 = vminsw 2, 3, 4 +0x10,0x43,0x22,0x02 = vminub 2, 3, 4 +0x10,0x43,0x22,0x42 = vminuh 2, 3, 4 +0x10,0x43,0x22,0x82 = vminuw 2, 3, 4 +0x10,0x43,0x20,0x06 = vcmpequb 2, 3, 4 +0x10,0x43,0x24,0x06 = vcmpequb. 2, 3, 4 +0x10,0x43,0x20,0x46 = vcmpequh 2, 3, 4 +0x10,0x43,0x24,0x46 = vcmpequh. 2, 3, 4 +0x10,0x43,0x20,0x86 = vcmpequw 2, 3, 4 +0x10,0x43,0x24,0x86 = vcmpequw. 2, 3, 4 +0x10,0x43,0x23,0x06 = vcmpgtsb 2, 3, 4 +0x10,0x43,0x27,0x06 = vcmpgtsb. 2, 3, 4 +0x10,0x43,0x23,0x46 = vcmpgtsh 2, 3, 4 +0x10,0x43,0x27,0x46 = vcmpgtsh. 2, 3, 4 +0x10,0x43,0x23,0x86 = vcmpgtsw 2, 3, 4 +0x10,0x43,0x27,0x86 = vcmpgtsw. 2, 3, 4 +0x10,0x43,0x22,0x06 = vcmpgtub 2, 3, 4 +0x10,0x43,0x26,0x06 = vcmpgtub. 2, 3, 4 +0x10,0x43,0x22,0x46 = vcmpgtuh 2, 3, 4 +0x10,0x43,0x26,0x46 = vcmpgtuh. 2, 3, 4 +0x10,0x43,0x22,0x86 = vcmpgtuw 2, 3, 4 +0x10,0x43,0x26,0x86 = vcmpgtuw. 2, 3, 4 +0x10,0x43,0x24,0x04 = vand 2, 3, 4 +0x10,0x43,0x24,0x44 = vandc 2, 3, 4 +0x10,0x43,0x25,0x04 = vnor 2, 3, 4 +0x10,0x43,0x24,0x84 = vor 2, 3, 4 +0x10,0x43,0x24,0xc4 = vxor 2, 3, 4 +0x10,0x43,0x20,0x04 = vrlb 2, 3, 4 +0x10,0x43,0x20,0x44 = vrlh 2, 3, 4 +0x10,0x43,0x20,0x84 = vrlw 2, 3, 4 +0x10,0x43,0x21,0x04 = vslb 2, 3, 4 +0x10,0x43,0x21,0x44 = vslh 2, 3, 4 +0x10,0x43,0x21,0x84 = vslw 2, 3, 4 +0x10,0x43,0x22,0x04 = vsrb 2, 3, 4 +0x10,0x43,0x22,0x44 = vsrh 2, 3, 4 +0x10,0x43,0x22,0x84 = vsrw 2, 3, 4 +0x10,0x43,0x23,0x04 = vsrab 2, 3, 4 +0x10,0x43,0x23,0x44 = vsrah 2, 3, 4 +0x10,0x43,0x23,0x84 = vsraw 2, 3, 4 +0x10,0x43,0x20,0x0a = vaddfp 2, 3, 4 +0x10,0x43,0x20,0x4a = vsubfp 2, 3, 4 +0x10,0x43,0x29,0x2e = vmaddfp 2, 3, 4, 5 +0x10,0x43,0x29,0x2f = vnmsubfp 2, 3, 4, 5 +0x10,0x43,0x24,0x0a = vmaxfp 2, 3, 4 +0x10,0x43,0x24,0x4a = vminfp 2, 3, 4 +0x10,0x44,0x1b,0xca = vctsxs 2, 3, 4 +0x10,0x44,0x1b,0x8a = vctuxs 2, 3, 4 +0x10,0x44,0x1b,0x4a = vcfsx 2, 3, 4 +0x10,0x44,0x1b,0x0a = vcfux 2, 3, 4 +0x10,0x40,0x1a,0xca = vrfim 2, 3 +0x10,0x40,0x1a,0x0a = vrfin 2, 3 +0x10,0x40,0x1a,0x8a = vrfip 2, 3 +0x10,0x40,0x1a,0x4a = vrfiz 2, 3 +0x10,0x43,0x23,0xc6 = vcmpbfp 2, 3, 4 +0x10,0x43,0x27,0xc6 = vcmpbfp. 2, 3, 4 +0x10,0x43,0x20,0xc6 = vcmpeqfp 2, 3, 4 +0x10,0x43,0x24,0xc6 = vcmpeqfp. 2, 3, 4 +0x10,0x43,0x21,0xc6 = vcmpgefp 2, 3, 4 +0x10,0x43,0x25,0xc6 = vcmpgefp. 2, 3, 4 +0x10,0x43,0x22,0xc6 = vcmpgtfp 2, 3, 4 +0x10,0x43,0x26,0xc6 = vcmpgtfp. 2, 3, 4 +0x10,0x40,0x19,0x8a = vexptefp 2, 3 +0x10,0x40,0x19,0xca = vlogefp 2, 3 +0x10,0x40,0x19,0x0a = vrefp 2, 3 +0x10,0x40,0x19,0x4a = vrsqrtefp 2, 3 +0x10,0x00,0x16,0x44 = mtvscr 2 +0x10,0x40,0x06,0x04 = mfvscr 2 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding.s.cs new file mode 100644 index 0000000..74c6b98 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-encoding.s.cs @@ -0,0 +1,202 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +// 0x4c,0x8a,0x18,0x20 = bclr 4, 10, 3 +// 0x4c,0x8a,0x00,0x20 = bclr 4, 10, 0 +// 0x4c,0x8a,0x18,0x21 = bclrl 4, 10, 3 +// 0x4c,0x8a,0x00,0x21 = bclrl 4, 10, 0 +// 0x4c,0x8a,0x1c,0x20 = bcctr 4, 10, 3 +// 0x4c,0x8a,0x04,0x20 = bcctr 4, 10, 0 +// 0x4c,0x8a,0x1c,0x21 = bcctrl 4, 10, 3 +// 0x4c,0x8a,0x04,0x21 = bcctrl 4, 10, 0 +0x4c,0x43,0x22,0x02 = crand 2, 3, 4 +0x4c,0x43,0x21,0xc2 = crnand 2, 3, 4 +0x4c,0x43,0x23,0x82 = cror 2, 3, 4 +0x4c,0x43,0x21,0x82 = crxor 2, 3, 4 +0x4c,0x43,0x20,0x42 = crnor 2, 3, 4 +0x4c,0x43,0x22,0x42 = creqv 2, 3, 4 +0x4c,0x43,0x21,0x02 = crandc 2, 3, 4 +0x4c,0x43,0x23,0x42 = crorc 2, 3, 4 +0x4d,0x0c,0x00,0x00 = mcrf 2, 3 +0x44,0x00,0x00,0x22 = sc 1 +// 0x44,0x00,0x00,0x02 = sc 0 +0x88,0x44,0x00,0x80 = lbz 2, 128(4) +0x7c,0x43,0x20,0xae = lbzx 2, 3, 4 +0x8c,0x44,0x00,0x80 = lbzu 2, 128(4) +0x7c,0x43,0x20,0xee = lbzux 2, 3, 4 +0xa0,0x44,0x00,0x80 = lhz 2, 128(4) +0x7c,0x43,0x22,0x2e = lhzx 2, 3, 4 +0xa4,0x44,0x00,0x80 = lhzu 2, 128(4) +0x7c,0x43,0x22,0x6e = lhzux 2, 3, 4 +0xa8,0x44,0x00,0x80 = lha 2, 128(4) +0x7c,0x43,0x22,0xae = lhax 2, 3, 4 +0xac,0x44,0x00,0x80 = lhau 2, 128(4) +0x7c,0x43,0x22,0xee = lhaux 2, 3, 4 +0x80,0x44,0x00,0x80 = lwz 2, 128(4) +0x7c,0x43,0x20,0x2e = lwzx 2, 3, 4 +0x84,0x44,0x00,0x80 = lwzu 2, 128(4) +0x7c,0x43,0x20,0x6e = lwzux 2, 3, 4 +0xe8,0x44,0x00,0x82 = lwa 2, 128(4) +0x7c,0x43,0x22,0xaa = lwax 2, 3, 4 +0x7c,0x43,0x22,0xea = lwaux 2, 3, 4 +0xe8,0x44,0x00,0x80 = ld 2, 128(4) +0x7c,0x43,0x20,0x2a = ldx 2, 3, 4 +0xe8,0x44,0x00,0x81 = ldu 2, 128(4) +0x7c,0x43,0x20,0x6a = ldux 2, 3, 4 +0x98,0x44,0x00,0x80 = stb 2, 128(4) +0x7c,0x43,0x21,0xae = stbx 2, 3, 4 +0x9c,0x44,0x00,0x80 = stbu 2, 128(4) +0x7c,0x43,0x21,0xee = stbux 2, 3, 4 +0xb0,0x44,0x00,0x80 = sth 2, 128(4) +0x7c,0x43,0x23,0x2e = sthx 2, 3, 4 +0xb4,0x44,0x00,0x80 = sthu 2, 128(4) +0x7c,0x43,0x23,0x6e = sthux 2, 3, 4 +0x90,0x44,0x00,0x80 = stw 2, 128(4) +0x7c,0x43,0x21,0x2e = stwx 2, 3, 4 +0x94,0x44,0x00,0x80 = stwu 2, 128(4) +0x7c,0x43,0x21,0x6e = stwux 2, 3, 4 +0xf8,0x44,0x00,0x80 = std 2, 128(4) +0x7c,0x43,0x21,0x2a = stdx 2, 3, 4 +0xf8,0x44,0x00,0x81 = stdu 2, 128(4) +0x7c,0x43,0x21,0x6a = stdux 2, 3, 4 +0x7c,0x43,0x26,0x2c = lhbrx 2, 3, 4 +0x7c,0x43,0x27,0x2c = sthbrx 2, 3, 4 +0x7c,0x43,0x24,0x2c = lwbrx 2, 3, 4 +0x7c,0x43,0x25,0x2c = stwbrx 2, 3, 4 +0x7c,0x43,0x24,0x28 = ldbrx 2, 3, 4 +0x7c,0x43,0x25,0x28 = stdbrx 2, 3, 4 +0xb8,0x41,0x00,0x80 = lmw 2, 128(1) +0xbc,0x41,0x00,0x80 = stmw 2, 128(1) +0x38,0x43,0x00,0x80 = addi 2, 3, 128 +0x3c,0x43,0x00,0x80 = addis 2, 3, 128 +0x7c,0x43,0x22,0x14 = add 2, 3, 4 +0x7c,0x43,0x22,0x15 = add. 2, 3, 4 +0x7c,0x43,0x20,0x50 = subf 2, 3, 4 +0x7c,0x43,0x20,0x51 = subf. 2, 3, 4 +0x30,0x43,0x00,0x80 = addic 2, 3, 128 +0x34,0x43,0x00,0x80 = addic. 2, 3, 128 +0x20,0x43,0x00,0x04 = subfic 2, 3, 4 +0x7c,0x43,0x20,0x14 = addc 2, 3, 4 +0x7c,0x43,0x20,0x15 = addc. 2, 3, 4 +0x7c,0x43,0x20,0x10 = subfc 2, 3, 4 +0x7c,0x43,0x20,0x10 = subfc 2, 3, 4 +0x7c,0x43,0x21,0x14 = adde 2, 3, 4 +0x7c,0x43,0x21,0x15 = adde. 2, 3, 4 +0x7c,0x43,0x21,0x10 = subfe 2, 3, 4 +0x7c,0x43,0x21,0x11 = subfe. 2, 3, 4 +0x7c,0x43,0x01,0xd4 = addme 2, 3 +0x7c,0x43,0x01,0xd5 = addme. 2, 3 +0x7c,0x43,0x01,0xd0 = subfme 2, 3 +0x7c,0x43,0x01,0xd1 = subfme. 2, 3 +0x7c,0x43,0x01,0x94 = addze 2, 3 +0x7c,0x43,0x01,0x95 = addze. 2, 3 +0x7c,0x43,0x01,0x90 = subfze 2, 3 +0x7c,0x43,0x01,0x91 = subfze. 2, 3 +0x7c,0x43,0x00,0xd0 = neg 2, 3 +0x7c,0x43,0x00,0xd1 = neg. 2, 3 +0x1c,0x43,0x00,0x80 = mulli 2, 3, 128 +0x7c,0x43,0x20,0x96 = mulhw 2, 3, 4 +0x7c,0x43,0x20,0x97 = mulhw. 2, 3, 4 +0x7c,0x43,0x21,0xd6 = mullw 2, 3, 4 +0x7c,0x43,0x21,0xd7 = mullw. 2, 3, 4 +0x7c,0x43,0x20,0x16 = mulhwu 2, 3, 4 +0x7c,0x43,0x20,0x17 = mulhwu. 2, 3, 4 +0x7c,0x43,0x23,0xd6 = divw 2, 3, 4 +0x7c,0x43,0x23,0xd7 = divw. 2, 3, 4 +0x7c,0x43,0x23,0x96 = divwu 2, 3, 4 +0x7c,0x43,0x23,0x97 = divwu. 2, 3, 4 +0x7c,0x43,0x21,0xd2 = mulld 2, 3, 4 +0x7c,0x43,0x21,0xd3 = mulld. 2, 3, 4 +0x7c,0x43,0x20,0x92 = mulhd 2, 3, 4 +0x7c,0x43,0x20,0x93 = mulhd. 2, 3, 4 +0x7c,0x43,0x20,0x12 = mulhdu 2, 3, 4 +0x7c,0x43,0x20,0x13 = mulhdu. 2, 3, 4 +0x7c,0x43,0x23,0xd2 = divd 2, 3, 4 +0x7c,0x43,0x23,0xd3 = divd. 2, 3, 4 +0x7c,0x43,0x23,0x92 = divdu 2, 3, 4 +0x7c,0x43,0x23,0x93 = divdu. 2, 3, 4 +0x2d,0x23,0x00,0x80 = cmpdi 2, 3, 128 +0x7d,0x23,0x20,0x00 = cmpd 2, 3, 4 +0x29,0x23,0x00,0x80 = cmpldi 2, 3, 128 +0x7d,0x23,0x20,0x40 = cmpld 2, 3, 4 +0x2d,0x03,0x00,0x80 = cmpwi 2, 3, 128 +0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4 +0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128 +0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4 +// 0x0c,0x43,0x00,0x04 = twi 2, 3, 4 +// 0x7c,0x43,0x20,0x08 = tw 2, 3, 4 +// 0x08,0x43,0x00,0x04 = tdi 2, 3, 4 +// 0x7c,0x43,0x20,0x88 = td 2, 3, 4 +0x7c,0x43,0x21,0x5e = isel 2, 3, 4, 5 +0x70,0x62,0x00,0x80 = andi. 2, 3, 128 +0x74,0x62,0x00,0x80 = andis. 2, 3, 128 +0x60,0x62,0x00,0x80 = ori 2, 3, 128 +0x64,0x62,0x00,0x80 = oris 2, 3, 128 +0x68,0x62,0x00,0x80 = xori 2, 3, 128 +0x6c,0x62,0x00,0x80 = xoris 2, 3, 128 +0x7c,0x62,0x20,0x38 = and 2, 3, 4 +0x7c,0x62,0x20,0x39 = and. 2, 3, 4 +0x7c,0x62,0x22,0x78 = xor 2, 3, 4 +0x7c,0x62,0x22,0x79 = xor. 2, 3, 4 +0x7c,0x62,0x23,0xb8 = nand 2, 3, 4 +0x7c,0x62,0x23,0xb9 = nand. 2, 3, 4 +0x7c,0x62,0x23,0x78 = or 2, 3, 4 +0x7c,0x62,0x23,0x79 = or. 2, 3, 4 +0x7c,0x62,0x20,0xf8 = nor 2, 3, 4 +0x7c,0x62,0x20,0xf9 = nor. 2, 3, 4 +0x7c,0x62,0x22,0x38 = eqv 2, 3, 4 +0x7c,0x62,0x22,0x39 = eqv. 2, 3, 4 +0x7c,0x62,0x20,0x78 = andc 2, 3, 4 +0x7c,0x62,0x20,0x79 = andc. 2, 3, 4 +0x7c,0x62,0x23,0x38 = orc 2, 3, 4 +0x7c,0x62,0x23,0x39 = orc. 2, 3, 4 +0x7c,0x62,0x07,0x74 = extsb 2, 3 +0x7c,0x62,0x07,0x75 = extsb. 2, 3 +0x7c,0x62,0x07,0x34 = extsh 2, 3 +0x7c,0x62,0x07,0x35 = extsh. 2, 3 +// 0x7c,0x62,0x00,0x34 = cntlzw 2, 3 +// 0x7c,0x62,0x00,0x35 = cntlzw. 2, 3 +0x7c,0x62,0x02,0xf4 = popcntw 2, 3 +0x7c,0x62,0x07,0xb4 = extsw 2, 3 +0x7c,0x62,0x07,0xb5 = extsw. 2, 3 +0x7c,0x62,0x00,0x74 = cntlzd 2, 3 +0x7c,0x62,0x00,0x75 = cntlzd. 2, 3 +0x7c,0x62,0x03,0xf4 = popcntd 2, 3 +0x54,0x62,0x21,0x4c = rlwinm 2, 3, 4, 5, 6 +0x54,0x62,0x21,0x4d = rlwinm. 2, 3, 4, 5, 6 +0x5c,0x62,0x21,0x4c = rlwnm 2, 3, 4, 5, 6 +0x5c,0x62,0x21,0x4d = rlwnm. 2, 3, 4, 5, 6 +0x50,0x62,0x21,0x4c = rlwimi 2, 3, 4, 5, 6 +0x50,0x62,0x21,0x4d = rlwimi. 2, 3, 4, 5, 6 +0x78,0x62,0x21,0x40 = rldicl 2, 3, 4, 5 +0x78,0x62,0x21,0x41 = rldicl. 2, 3, 4, 5 +0x78,0x62,0x21,0x44 = rldicr 2, 3, 4, 5 +0x78,0x62,0x21,0x45 = rldicr. 2, 3, 4, 5 +0x78,0x62,0x21,0x48 = rldic 2, 3, 4, 5 +0x78,0x62,0x21,0x49 = rldic. 2, 3, 4, 5 +0x78,0x62,0x21,0x50 = rldcl 2, 3, 4, 5 +0x78,0x62,0x21,0x51 = rldcl. 2, 3, 4, 5 +0x78,0x62,0x21,0x52 = rldcr 2, 3, 4, 5 +0x78,0x62,0x21,0x53 = rldcr. 2, 3, 4, 5 +0x78,0x62,0x21,0x4c = rldimi 2, 3, 4, 5 +0x78,0x62,0x21,0x4d = rldimi. 2, 3, 4, 5 +0x7c,0x62,0x20,0x30 = slw 2, 3, 4 +0x7c,0x62,0x20,0x31 = slw. 2, 3, 4 +0x7c,0x62,0x24,0x30 = srw 2, 3, 4 +0x7c,0x62,0x24,0x31 = srw. 2, 3, 4 +0x7c,0x62,0x26,0x70 = srawi 2, 3, 4 +0x7c,0x62,0x26,0x71 = srawi. 2, 3, 4 +0x7c,0x62,0x26,0x30 = sraw 2, 3, 4 +0x7c,0x62,0x26,0x31 = sraw. 2, 3, 4 +0x7c,0x62,0x20,0x36 = sld 2, 3, 4 +0x7c,0x62,0x20,0x37 = sld. 2, 3, 4 +0x7c,0x62,0x24,0x36 = srd 2, 3, 4 +0x7c,0x62,0x24,0x37 = srd. 2, 3, 4 +0x7c,0x62,0x26,0x74 = sradi 2, 3, 4 +0x7c,0x62,0x26,0x75 = sradi. 2, 3, 4 +0x7c,0x62,0x26,0x34 = srad 2, 3, 4 +0x7c,0x62,0x26,0x35 = srad. 2, 3, 4 +0x7c,0x58,0x93,0xa6 = mtspr 600, 2 +0x7c,0x58,0x92,0xa6 = mfspr 2, 600 +0x7c,0x47,0xb1,0x20 = mtcrf 123, 2 +0x7c,0x40,0x00,0x26 = mfcr 2 +0x7c,0x51,0x01,0x20 = mtocrf 16, 2 +0x7e,0x10,0x80,0x26 = mfocrf 16, 8 diff --git a/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-operands.s.cs b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-operands.s.cs new file mode 100644 index 0000000..b5e5bd1 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/PowerPC/ppc64-operands.s.cs @@ -0,0 +1,31 @@ +# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME +0x7c,0x22,0x1a,0x14 = add 1, 2, 3 +0x7c,0x22,0x1a,0x14 = add 1, 2, 3 +0x7c,0x00,0x02,0x14 = add 0, 0, 0 +0x7f,0xff,0xfa,0x14 = add 31, 31, 31 +0x38,0x20,0x00,0x00 = li 1, 0 +0x38,0x22,0x00,0x00 = addi 1, 2, 0 +0x38,0x20,0x80,0x00 = li 1, 0x8000 +0x38,0x20,0x7f,0xff = li 1, 0x7fff +0x60,0x41,0x00,0x00 = ori 1, 2, 0 +0x60,0x41,0xff,0xff = ori 1, 2, 65535 +0x3c,0x20,0x00,0x00 = lis 1, 0 +0x3c,0x20,0xff,0xff = lis 1, 0xffff +0x80,0x20,0x00,0x00 = lwz 1, 0(0) +0x80,0x20,0x00,0x00 = lwz 1, 0(0) +0x80,0x3f,0x00,0x00 = lwz 1, 0(31) +0x80,0x3f,0x00,0x00 = lwz 1, 0(31) +0x80,0x22,0x80,0x00 = lwz 1, -32768(2) +0x80,0x22,0x7f,0xff = lwz 1, 32767(2) +0xe8,0x20,0x00,0x00 = ld 1, 0(0) +0xe8,0x20,0x00,0x00 = ld 1, 0(0) +0xe8,0x3f,0x00,0x00 = ld 1, 0(31) +0xe8,0x3f,0x00,0x00 = ld 1, 0(31) +0xe8,0x22,0x80,0x00 = ld 1, -32768(2) +0xe8,0x22,0x7f,0xfc = ld 1, 32764(2) +0xe8,0x22,0x00,0x04 = ld 1, 4(2) +0xe8,0x22,0xff,0xfc = ld 1, -4(2) +// 0x48,0x00,0x04,0x00 = b .+1024 +0x48,0x00,0x04,0x02 = ba 1024 +// 0x41,0x82,0x04,0x00 = beq 0, .+1024 +// 0x41,0x82,0x04,0x02 = beqa 0, 1024 diff --git a/white_patch_detect/capstone-master/suite/MC/README b/white_patch_detect/capstone-master/suite/MC/README new file mode 100644 index 0000000..b39d13f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/README @@ -0,0 +1,10 @@ +Input files for testing Capstone engine. + +Format of input files: + +# ARCH, MODE, OPTION +hexcode = assembly + +Format of issue file: +# ARCH, MODE, OPTION +hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count \ No newline at end of file diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-alu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-alu-instructions.s.cs new file mode 100644 index 0000000..98e8665 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-alu-instructions.s.cs @@ -0,0 +1,47 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x80,0x00,0x00,0x00 = add %g0, %g0, %g0 +0x86,0x00,0x40,0x02 = add %g1, %g2, %g3 +0xa0,0x02,0x00,0x09 = add %o0, %o1, %l0 +0xa0,0x02,0x20,0x0a = add %o0, 10, %l0 +0x86,0x80,0x40,0x02 = addcc %g1, %g2, %g3 +0x86,0xc0,0x40,0x02 = addxcc %g1, %g2, %g3 +0x86,0x70,0x40,0x02 = udiv %g1, %g2, %g3 +0x86,0x78,0x40,0x02 = sdiv %g1, %g2, %g3 +0x86,0x08,0x40,0x02 = and %g1, %g2, %g3 +0x86,0x28,0x40,0x02 = andn %g1, %g2, %g3 +0x86,0x10,0x40,0x02 = or %g1, %g2, %g3 +0x86,0x30,0x40,0x02 = orn %g1, %g2, %g3 +0x86,0x18,0x40,0x02 = xor %g1, %g2, %g3 +0x86,0x38,0x40,0x02 = xnor %g1, %g2, %g3 +0x86,0x50,0x40,0x02 = umul %g1, %g2, %g3 +0x86,0x58,0x40,0x02 = smul %g1, %g2, %g3 +0x01,0x00,0x00,0x00 = nop +0x21,0x00,0x00,0x0a = sethi 10, %l0 +0x87,0x28,0x40,0x02 = sll %g1, %g2, %g3 +0x87,0x28,0x60,0x1f = sll %g1, 31, %g3 +0x87,0x30,0x40,0x02 = srl %g1, %g2, %g3 +0x87,0x30,0x60,0x1f = srl %g1, 31, %g3 +0x87,0x38,0x40,0x02 = sra %g1, %g2, %g3 +0x87,0x38,0x60,0x1f = sra %g1, 31, %g3 +0x86,0x20,0x40,0x02 = sub %g1, %g2, %g3 +0x86,0xa0,0x40,0x02 = subcc %g1, %g2, %g3 +0x86,0xe0,0x40,0x02 = subxcc %g1, %g2, %g3 +0x86,0x10,0x00,0x01 = mov %g1, %g3 +0x86,0x10,0x20,0xff = mov 0xff, %g3 +0x81,0xe8,0x00,0x00 = restore +0x86,0x40,0x80,0x01 = addx %g2, %g1, %g3 +0x86,0x60,0x80,0x01 = subx %g2, %g1, %g3 +0x86,0xd0,0x80,0x01 = umulcc %g2, %g1, %g3 +0x86,0xd8,0x80,0x01 = smulcc %g2, %g1, %g3 +0x86,0xf0,0x80,0x01 = udivcc %g2, %g1, %g3 +0x86,0xf8,0x80,0x01 = sdivcc %g2, %g1, %g3 +0x86,0x88,0x80,0x01 = andcc %g2, %g1, %g3 +0x86,0xa8,0x80,0x01 = andncc %g2, %g1, %g3 +0x86,0x90,0x80,0x01 = orcc %g2, %g1, %g3 +0x86,0xb0,0x80,0x01 = orncc %g2, %g1, %g3 +0x86,0x98,0x80,0x01 = xorcc %g2, %g1, %g3 +0x86,0xb8,0x80,0x01 = xnorcc %g2, %g1, %g3 +0x87,0x00,0x80,0x01 = taddcc %g2, %g1, %g3 +0x87,0x08,0x80,0x01 = tsubcc %g2, %g1, %g3 +0x87,0x10,0x80,0x01 = taddcctv %g2, %g1, %g3 +0x87,0x18,0x80,0x01 = tsubcctv %g2, %g1, %g3 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-atomic-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-atomic-instructions.s.cs new file mode 100644 index 0000000..73b1f93 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-atomic-instructions.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x81,0x43,0xe0,0x0f = membar 15 +0x81,0x43,0xc0,0x00 = stbar +0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2 +0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2 +0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2 +0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-ctrl-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-ctrl-instructions.s.cs new file mode 100644 index 0000000..2f8f209 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-ctrl-instructions.s.cs @@ -0,0 +1,11 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x9f,0xc0,0x40,0x1a = call %g1+%i2 +0x9f,0xc2,0x60,0x08 = call %o1+8 +0x9f,0xc0,0x60,0x00 = call %g1 +0x81,0xc0,0x40,0x1a = jmp %g1+%i2 +0x81,0xc2,0x60,0x08 = jmp %o1+8 +0x81,0xc0,0x60,0x00 = jmp %g1 +0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2 +0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2 +0x85,0xc0,0x60,0x00 = jmpl %g1, %g2 +0x81,0xcf,0xe0,0x08 = rett %i7+8 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-fp-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-fp-instructions.s.cs new file mode 100644 index 0000000..0ec023c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-fp-instructions.s.cs @@ -0,0 +1,59 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, None +0x89,0xa0,0x18,0x80 = fitos %f0, %f4 +0x89,0xa0,0x19,0x00 = fitod %f0, %f4 +0x89,0xa0,0x19,0x80 = fitoq %f0, %f4 +0x89,0xa0,0x1a,0x20 = fstoi %f0, %f4 +0x89,0xa0,0x1a,0x40 = fdtoi %f0, %f4 +0x89,0xa0,0x1a,0x60 = fqtoi %f0, %f4 +0x89,0xa0,0x19,0x20 = fstod %f0, %f4 +0x89,0xa0,0x19,0xa0 = fstoq %f0, %f4 +0x89,0xa0,0x18,0xc0 = fdtos %f0, %f4 +0x89,0xa0,0x19,0xc0 = fdtoq %f0, %f4 +0x89,0xa0,0x18,0xe0 = fqtos %f0, %f4 +0x89,0xa0,0x19,0x60 = fqtod %f0, %f4 +0x89,0xa0,0x00,0x20 = fmovs %f0, %f4 +0x89,0xa0,0x00,0x40 = fmovd %f0, %f4 +0x89,0xa0,0x00,0x60 = fmovq %f0, %f4 +0x89,0xa0,0x00,0xa0 = fnegs %f0, %f4 +0x89,0xa0,0x00,0xc0 = fnegd %f0, %f4 +0x89,0xa0,0x00,0xe0 = fnegq %f0, %f4 +0x89,0xa0,0x01,0x20 = fabss %f0, %f4 +0x89,0xa0,0x01,0x40 = fabsd %f0, %f4 +0x89,0xa0,0x01,0x60 = fabsq %f0, %f4 +0x89,0xa0,0x05,0x20 = fsqrts %f0, %f4 +0x89,0xa0,0x05,0x40 = fsqrtd %f0, %f4 +0x89,0xa0,0x05,0x60 = fsqrtq %f0, %f4 +0x91,0xa0,0x08,0x24 = fadds %f0, %f4, %f8 +0x91,0xa0,0x08,0x44 = faddd %f0, %f4, %f8 +0x91,0xa0,0x08,0x64 = faddq %f0, %f4, %f8 +0xbf,0xa0,0x48,0x43 = faddd %f32, %f34, %f62 +0xbb,0xa0,0x48,0x65 = faddq %f32, %f36, %f60 +0x91,0xa0,0x08,0xa4 = fsubs %f0, %f4, %f8 +0x91,0xa0,0x08,0xc4 = fsubd %f0, %f4, %f8 +0x91,0xa0,0x08,0xe4 = fsubq %f0, %f4, %f8 +0x91,0xa0,0x09,0x24 = fmuls %f0, %f4, %f8 +0x91,0xa0,0x09,0x44 = fmuld %f0, %f4, %f8 +0x91,0xa0,0x09,0x64 = fmulq %f0, %f4, %f8 +0x91,0xa0,0x0d,0x24 = fsmuld %f0, %f4, %f8 +0x91,0xa0,0x0d,0xc4 = fdmulq %f0, %f4, %f8 +0x91,0xa0,0x09,0xa4 = fdivs %f0, %f4, %f8 +0x91,0xa0,0x09,0xc4 = fdivd %f0, %f4, %f8 +0x91,0xa0,0x09,0xe4 = fdivq %f0, %f4, %f8 +// 0x81,0xa8,0x0a,0x24 = fcmps %fcc0, %f0, %f4 +// 0x81,0xa8,0x0a,0x44 = fcmpd %fcc0, %f0, %f4 +// 0x81,0xa8,0x0a,0x64 = fcmpq %fcc0, %f0, %f4 +// 0x81,0xa8,0x0a,0xa4 = fcmpes %fcc0, %f0, %f4 +// 0x81,0xa8,0x0a,0xc4 = fcmped %fcc0, %f0, %f4 +// 0x81,0xa8,0x0a,0xe4 = fcmpeq %fcc0, %f0, %f4 +0x85,0xa8,0x0a,0x24 = fcmps %fcc2, %f0, %f4 +0x85,0xa8,0x0a,0x44 = fcmpd %fcc2, %f0, %f4 +0x85,0xa8,0x0a,0x64 = fcmpq %fcc2, %f0, %f4 +0x85,0xa8,0x0a,0xa4 = fcmpes %fcc2, %f0, %f4 +0x85,0xa8,0x0a,0xc4 = fcmped %fcc2, %f0, %f4 +0x85,0xa8,0x0a,0xe4 = fcmpeq %fcc2, %f0, %f4 +0x89,0xa0,0x10,0x80 = fxtos %f0, %f4 +0x89,0xa0,0x11,0x00 = fxtod %f0, %f4 +0x89,0xa0,0x11,0x80 = fxtoq %f0, %f4 +0x89,0xa0,0x10,0x20 = fstox %f0, %f4 +0x89,0xa0,0x10,0x40 = fdtox %f0, %f4 +0x89,0xa0,0x10,0x60 = fqtox %f0, %f4 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-mem-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-mem-instructions.s.cs new file mode 100644 index 0000000..fd0651a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-mem-instructions.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0xd4,0x4e,0x00,0x16 = ldsb [%i0+%l6], %o2 +0xd4,0x4e,0x20,0x20 = ldsb [%i0+32], %o2 +0xd8,0x48,0x60,0x00 = ldsb [%g1], %o4 +0xd4,0x56,0x00,0x16 = ldsh [%i0+%l6], %o2 +0xd4,0x56,0x20,0x20 = ldsh [%i0+32], %o2 +0xd8,0x50,0x60,0x00 = ldsh [%g1], %o4 +0xd4,0x0e,0x00,0x16 = ldub [%i0+%l6], %o2 +0xd4,0x0e,0x20,0x20 = ldub [%i0+32], %o2 +0xd4,0x08,0x60,0x00 = ldub [%g1], %o2 +0xd4,0x16,0x00,0x16 = lduh [%i0+%l6], %o2 +0xd4,0x16,0x20,0x20 = lduh [%i0+32], %o2 +0xd4,0x10,0x60,0x00 = lduh [%g1], %o2 +0xd4,0x06,0x00,0x16 = ld [%i0+%l6], %o2 +0xd4,0x06,0x20,0x20 = ld [%i0+32], %o2 +0xd4,0x00,0x60,0x00 = ld [%g1], %o2 +0xd4,0x2e,0x00,0x16 = stb %o2, [%i0+%l6] +0xd4,0x2e,0x20,0x20 = stb %o2, [%i0+32] +0xd4,0x28,0x60,0x00 = stb %o2, [%g1] +0xd4,0x36,0x00,0x16 = sth %o2, [%i0+%l6] +0xd4,0x36,0x20,0x20 = sth %o2, [%i0+32] +0xd4,0x30,0x60,0x00 = sth %o2, [%g1] +0xd4,0x26,0x00,0x16 = st %o2, [%i0+%l6] +0xd4,0x26,0x20,0x20 = st %o2, [%i0+32] +0xd4,0x20,0x60,0x00 = st %o2, [%g1] diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-vis.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-vis.s.cs new file mode 100644 index 0000000..10654aa --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc-vis.s.cs @@ -0,0 +1,2 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0xbf,0xb0,0x0c,0x20 = fzeros %f31 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-alu-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-alu-instructions.s.cs new file mode 100644 index 0000000..dae91b4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-alu-instructions.s.cs @@ -0,0 +1,13 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0xb1,0x28,0x50,0x1a = sllx %g1, %i2, %i0 +0xb1,0x28,0x70,0x3f = sllx %g1, 63, %i0 +0xb1,0x30,0x50,0x1a = srlx %g1, %i2, %i0 +0xb1,0x30,0x70,0x3f = srlx %g1, 63, %i0 +0xb1,0x38,0x50,0x1a = srax %g1, %i2, %i0 +0xb1,0x38,0x70,0x3f = srax %g1, 63, %i0 +0xb0,0x48,0x40,0x1a = mulx %g1, %i2, %i0 +0xb0,0x48,0x60,0x3f = mulx %g1, 63, %i0 +0xb1,0x68,0x40,0x1a = sdivx %g1, %i2, %i0 +0xb1,0x68,0x60,0x3f = sdivx %g1, 63, %i0 +0xb0,0x68,0x40,0x1a = udivx %g1, %i2, %i0 +0xb0,0x68,0x60,0x3f = udivx %g1, 63, %i0 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-ctrl-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-ctrl-instructions.s.cs new file mode 100644 index 0000000..8e63807 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparc64-ctrl-instructions.s.cs @@ -0,0 +1,102 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x85,0x66,0x40,0x01 = movne %icc, %g1, %g2 +0x85,0x64,0x40,0x01 = move %icc, %g1, %g2 +0x85,0x66,0x80,0x01 = movg %icc, %g1, %g2 +0x85,0x64,0x80,0x01 = movle %icc, %g1, %g2 +0x85,0x66,0xc0,0x01 = movge %icc, %g1, %g2 +0x85,0x64,0xc0,0x01 = movl %icc, %g1, %g2 +0x85,0x67,0x00,0x01 = movgu %icc, %g1, %g2 +0x85,0x65,0x00,0x01 = movleu %icc, %g1, %g2 +0x85,0x67,0x40,0x01 = movcc %icc, %g1, %g2 +0x85,0x65,0x40,0x01 = movcs %icc, %g1, %g2 +0x85,0x67,0x80,0x01 = movpos %icc, %g1, %g2 +0x85,0x65,0x80,0x01 = movneg %icc, %g1, %g2 +0x85,0x67,0xc0,0x01 = movvc %icc, %g1, %g2 +0x85,0x65,0xc0,0x01 = movvs %icc, %g1, %g2 +0x85,0x66,0x50,0x01 = movne %xcc, %g1, %g2 +0x85,0x64,0x50,0x01 = move %xcc, %g1, %g2 +0x85,0x66,0x90,0x01 = movg %xcc, %g1, %g2 +0x85,0x64,0x90,0x01 = movle %xcc, %g1, %g2 +0x85,0x66,0xd0,0x01 = movge %xcc, %g1, %g2 +0x85,0x64,0xd0,0x01 = movl %xcc, %g1, %g2 +0x85,0x67,0x10,0x01 = movgu %xcc, %g1, %g2 +0x85,0x65,0x10,0x01 = movleu %xcc, %g1, %g2 +0x85,0x67,0x50,0x01 = movcc %xcc, %g1, %g2 +0x85,0x65,0x50,0x01 = movcs %xcc, %g1, %g2 +0x85,0x67,0x90,0x01 = movpos %xcc, %g1, %g2 +0x85,0x65,0x90,0x01 = movneg %xcc, %g1, %g2 +0x85,0x67,0xd0,0x01 = movvc %xcc, %g1, %g2 +0x85,0x65,0xd0,0x01 = movvs %xcc, %g1, %g2 +0x85,0x61,0xc0,0x01 = movu %fcc0, %g1, %g2 +0x85,0x61,0x80,0x01 = movg %fcc0, %g1, %g2 +0x85,0x61,0x40,0x01 = movug %fcc0, %g1, %g2 +0x85,0x61,0x00,0x01 = movl %fcc0, %g1, %g2 +0x85,0x60,0xc0,0x01 = movul %fcc0, %g1, %g2 +0x85,0x60,0x80,0x01 = movlg %fcc0, %g1, %g2 +0x85,0x60,0x40,0x01 = movne %fcc0, %g1, %g2 +0x85,0x62,0x40,0x01 = move %fcc0, %g1, %g2 +0x85,0x62,0x80,0x01 = movue %fcc0, %g1, %g2 +0x85,0x62,0xc0,0x01 = movge %fcc0, %g1, %g2 +0x85,0x63,0x00,0x01 = movuge %fcc0, %g1, %g2 +0x85,0x63,0x40,0x01 = movle %fcc0, %g1, %g2 +0x85,0x63,0x80,0x01 = movule %fcc0, %g1, %g2 +0x85,0x63,0xc0,0x01 = movo %fcc0, %g1, %g2 +0x85,0xaa,0x60,0x21 = fmovsne %icc, %f1, %f2 +0x85,0xa8,0x60,0x21 = fmovse %icc, %f1, %f2 +0x85,0xaa,0xa0,0x21 = fmovsg %icc, %f1, %f2 +0x85,0xa8,0xa0,0x21 = fmovsle %icc, %f1, %f2 +0x85,0xaa,0xe0,0x21 = fmovsge %icc, %f1, %f2 +0x85,0xa8,0xe0,0x21 = fmovsl %icc, %f1, %f2 +0x85,0xab,0x20,0x21 = fmovsgu %icc, %f1, %f2 +0x85,0xa9,0x20,0x21 = fmovsleu %icc, %f1, %f2 +0x85,0xab,0x60,0x21 = fmovscc %icc, %f1, %f2 +0x85,0xa9,0x60,0x21 = fmovscs %icc, %f1, %f2 +0x85,0xab,0xa0,0x21 = fmovspos %icc, %f1, %f2 +0x85,0xa9,0xa0,0x21 = fmovsneg %icc, %f1, %f2 +0x85,0xab,0xe0,0x21 = fmovsvc %icc, %f1, %f2 +0x85,0xa9,0xe0,0x21 = fmovsvs %icc, %f1, %f2 +0x85,0xaa,0x70,0x21 = fmovsne %xcc, %f1, %f2 +0x85,0xa8,0x70,0x21 = fmovse %xcc, %f1, %f2 +0x85,0xaa,0xb0,0x21 = fmovsg %xcc, %f1, %f2 +0x85,0xa8,0xb0,0x21 = fmovsle %xcc, %f1, %f2 +0x85,0xaa,0xf0,0x21 = fmovsge %xcc, %f1, %f2 +0x85,0xa8,0xf0,0x21 = fmovsl %xcc, %f1, %f2 +0x85,0xab,0x30,0x21 = fmovsgu %xcc, %f1, %f2 +0x85,0xa9,0x30,0x21 = fmovsleu %xcc, %f1, %f2 +0x85,0xab,0x70,0x21 = fmovscc %xcc, %f1, %f2 +0x85,0xa9,0x70,0x21 = fmovscs %xcc, %f1, %f2 +0x85,0xab,0xb0,0x21 = fmovspos %xcc, %f1, %f2 +0x85,0xa9,0xb0,0x21 = fmovsneg %xcc, %f1, %f2 +0x85,0xab,0xf0,0x21 = fmovsvc %xcc, %f1, %f2 +0x85,0xa9,0xf0,0x21 = fmovsvs %xcc, %f1, %f2 +0x85,0xa9,0xc0,0x21 = fmovsu %fcc0, %f1, %f2 +0x85,0xa9,0x80,0x21 = fmovsg %fcc0, %f1, %f2 +0x85,0xa9,0x40,0x21 = fmovsug %fcc0, %f1, %f2 +0x85,0xa9,0x00,0x21 = fmovsl %fcc0, %f1, %f2 +0x85,0xa8,0xc0,0x21 = fmovsul %fcc0, %f1, %f2 +0x85,0xa8,0x80,0x21 = fmovslg %fcc0, %f1, %f2 +0x85,0xa8,0x40,0x21 = fmovsne %fcc0, %f1, %f2 +0x85,0xaa,0x40,0x21 = fmovse %fcc0, %f1, %f2 +0x85,0xaa,0x80,0x21 = fmovsue %fcc0, %f1, %f2 +0x85,0xaa,0xc0,0x21 = fmovsge %fcc0, %f1, %f2 +0x85,0xab,0x00,0x21 = fmovsuge %fcc0, %f1, %f2 +0x85,0xab,0x40,0x21 = fmovsle %fcc0, %f1, %f2 +0x85,0xab,0x80,0x21 = fmovsule %fcc0, %f1, %f2 +0x85,0xab,0xc0,0x21 = fmovso %fcc0, %f1, %f2 +0x85,0x61,0xc8,0x01 = movu %fcc1, %g1, %g2 +0x85,0xa9,0x90,0x21 = fmovsg %fcc2, %f1, %f2 +0x87,0x78,0x44,0x02 = movrz %g1, %g2, %g3 +0x87,0x78,0x48,0x02 = movrlez %g1, %g2, %g3 +0x87,0x78,0x4c,0x02 = movrlz %g1, %g2, %g3 +0x87,0x78,0x54,0x02 = movrnz %g1, %g2, %g3 +0x87,0x78,0x58,0x02 = movrgz %g1, %g2, %g3 +0x87,0x78,0x5c,0x02 = movrgez %g1, %g2, %g3 +0x87,0xa8,0x44,0xa2 = fmovrsz %g1, %f2, %f3 +0x87,0xa8,0x48,0xa2 = fmovrslez %g1, %f2, %f3 +0x87,0xa8,0x4c,0xa2 = fmovrslz %g1, %f2, %f3 +0x87,0xa8,0x54,0xa2 = fmovrsnz %g1, %f2, %f3 +0x87,0xa8,0x58,0xa2 = fmovrsgz %g1, %f2, %f3 +0x87,0xa8,0x5c,0xa2 = fmovrsgez %g1, %f2, %f3 +0x81,0xcf,0xe0,0x08 = rett %i7+8 +// 0x91,0xd0,0x20,0x05 = ta %icc, %g0 + 5 +0x83,0xd0,0x30,0x03 = te %xcc, %g0 + 3 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv8-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv8-instructions.s.cs new file mode 100644 index 0000000..fd7e5de --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv8-instructions.s.cs @@ -0,0 +1,7 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x81,0xa8,0x0a,0x24 = fcmps %f0, %f4 +0x81,0xa8,0x0a,0x44 = fcmpd %f0, %f4 +0x81,0xa8,0x0a,0x64 = fcmpq %f0, %f4 +0x81,0xa8,0x0a,0xa4 = fcmpes %f0, %f4 +0x81,0xa8,0x0a,0xc4 = fcmped %f0, %f4 +0x81,0xa8,0x0a,0xe4 = fcmpeq %f0, %f4 diff --git a/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv9-instructions.s.cs b/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv9-instructions.s.cs new file mode 100644 index 0000000..c1a0aa1 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/Sparc/sparcv9-instructions.s.cs @@ -0,0 +1 @@ +# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None diff --git a/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good-z196.s.cs b/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good-z196.s.cs new file mode 100644 index 0000000..1a4e211 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good-z196.s.cs @@ -0,0 +1,589 @@ +# CS_ARCH_SYSZ, 0, None +0xec,0x00,0x80,0x00,0x00,0xd9 = aghik %r0, %r0, -32768 +0xec,0x00,0xff,0xff,0x00,0xd9 = aghik %r0, %r0, -1 +0xec,0x00,0x00,0x00,0x00,0xd9 = aghik %r0, %r0, 0 +0xec,0x00,0x00,0x01,0x00,0xd9 = aghik %r0, %r0, 1 +0xec,0x00,0x7f,0xff,0x00,0xd9 = aghik %r0, %r0, 32767 +0xec,0x0f,0x00,0x00,0x00,0xd9 = aghik %r0, %r15, 0 +0xec,0xf0,0x00,0x00,0x00,0xd9 = aghik %r15, %r0, 0 +0xec,0x78,0xff,0xf0,0x00,0xd9 = aghik %r7, %r8, -16 +0xb9,0xe8,0x00,0x00 = agrk %r0, %r0, %r0 +0xb9,0xe8,0xf0,0x00 = agrk %r0, %r0, %r15 +0xb9,0xe8,0x00,0x0f = agrk %r0, %r15, %r0 +0xb9,0xe8,0x00,0xf0 = agrk %r15, %r0, %r0 +0xb9,0xe8,0x90,0x78 = agrk %r7, %r8, %r9 +0xec,0x00,0x80,0x00,0x00,0xd8 = ahik %r0, %r0, -32768 +0xec,0x00,0xff,0xff,0x00,0xd8 = ahik %r0, %r0, -1 +0xec,0x00,0x00,0x00,0x00,0xd8 = ahik %r0, %r0, 0 +0xec,0x00,0x00,0x01,0x00,0xd8 = ahik %r0, %r0, 1 +0xec,0x00,0x7f,0xff,0x00,0xd8 = ahik %r0, %r0, 32767 +0xec,0x0f,0x00,0x00,0x00,0xd8 = ahik %r0, %r15, 0 +0xec,0xf0,0x00,0x00,0x00,0xd8 = ahik %r15, %r0, 0 +0xec,0x78,0xff,0xf0,0x00,0xd8 = ahik %r7, %r8, -16 +0xcc,0x08,0x80,0x00,0x00,0x00 = aih %r0, -2147483648 +0xcc,0x08,0xff,0xff,0xff,0xff = aih %r0, -1 +0xcc,0x08,0x00,0x00,0x00,0x00 = aih %r0, 0 +0xcc,0x08,0x00,0x00,0x00,0x01 = aih %r0, 1 +0xcc,0x08,0x7f,0xff,0xff,0xff = aih %r0, 2147483647 +0xcc,0xf8,0x00,0x00,0x00,0x00 = aih %r15, 0 +0xec,0x00,0x80,0x00,0x00,0xdb = alghsik %r0, %r0, -32768 +0xec,0x00,0xff,0xff,0x00,0xdb = alghsik %r0, %r0, -1 +0xec,0x00,0x00,0x00,0x00,0xdb = alghsik %r0, %r0, 0 +0xec,0x00,0x00,0x01,0x00,0xdb = alghsik %r0, %r0, 1 +0xec,0x00,0x7f,0xff,0x00,0xdb = alghsik %r0, %r0, 32767 +0xec,0x0f,0x00,0x00,0x00,0xdb = alghsik %r0, %r15, 0 +0xec,0xf0,0x00,0x00,0x00,0xdb = alghsik %r15, %r0, 0 +0xec,0x78,0xff,0xf0,0x00,0xdb = alghsik %r7, %r8, -16 +0xb9,0xea,0x00,0x00 = algrk %r0, %r0, %r0 +0xb9,0xea,0xf0,0x00 = algrk %r0, %r0, %r15 +0xb9,0xea,0x00,0x0f = algrk %r0, %r15, %r0 +0xb9,0xea,0x00,0xf0 = algrk %r15, %r0, %r0 +0xb9,0xea,0x90,0x78 = algrk %r7, %r8, %r9 +0xec,0x00,0x80,0x00,0x00,0xda = alhsik %r0, %r0, -32768 +0xec,0x00,0xff,0xff,0x00,0xda = alhsik %r0, %r0, -1 +0xec,0x00,0x00,0x00,0x00,0xda = alhsik %r0, %r0, 0 +0xec,0x00,0x00,0x01,0x00,0xda = alhsik %r0, %r0, 1 +0xec,0x00,0x7f,0xff,0x00,0xda = alhsik %r0, %r0, 32767 +0xec,0x0f,0x00,0x00,0x00,0xda = alhsik %r0, %r15, 0 +0xec,0xf0,0x00,0x00,0x00,0xda = alhsik %r15, %r0, 0 +0xec,0x78,0xff,0xf0,0x00,0xda = alhsik %r7, %r8, -16 +0xb9,0xfa,0x00,0x00 = alrk %r0, %r0, %r0 +0xb9,0xfa,0xf0,0x00 = alrk %r0, %r0, %r15 +0xb9,0xfa,0x00,0x0f = alrk %r0, %r15, %r0 +0xb9,0xfa,0x00,0xf0 = alrk %r15, %r0, %r0 +0xb9,0xfa,0x90,0x78 = alrk %r7, %r8, %r9 +0xb9,0xf8,0x00,0x00 = ark %r0, %r0, %r0 +0xb9,0xf8,0xf0,0x00 = ark %r0, %r0, %r15 +0xb9,0xf8,0x00,0x0f = ark %r0, %r15, %r0 +0xb9,0xf8,0x00,0xf0 = ark %r15, %r0, %r0 +0xb9,0xf8,0x90,0x78 = ark %r7, %r8, %r9 +0xb3,0x91,0x00,0x00 = cdlfbr %f0, 0, %r0, 0 +0xb3,0x91,0x0f,0x00 = cdlfbr %f0, 0, %r0, 15 +0xb3,0x91,0x00,0x0f = cdlfbr %f0, 0, %r15, 0 +0xb3,0x91,0xf0,0x00 = cdlfbr %f0, 15, %r0, 0 +0xb3,0x91,0x57,0x46 = cdlfbr %f4, 5, %r6, 7 +0xb3,0x91,0x00,0xf0 = cdlfbr %f15, 0, %r0, 0 +0xb3,0xa1,0x00,0x00 = cdlgbr %f0, 0, %r0, 0 +0xb3,0xa1,0x0f,0x00 = cdlgbr %f0, 0, %r0, 15 +0xb3,0xa1,0x00,0x0f = cdlgbr %f0, 0, %r15, 0 +0xb3,0xa1,0xf0,0x00 = cdlgbr %f0, 15, %r0, 0 +0xb3,0xa1,0x57,0x46 = cdlgbr %f4, 5, %r6, 7 +0xb3,0xa1,0x00,0xf0 = cdlgbr %f15, 0, %r0, 0 +0xb3,0x90,0x00,0x00 = celfbr %f0, 0, %r0, 0 +0xb3,0x90,0x0f,0x00 = celfbr %f0, 0, %r0, 15 +0xb3,0x90,0x00,0x0f = celfbr %f0, 0, %r15, 0 +0xb3,0x90,0xf0,0x00 = celfbr %f0, 15, %r0, 0 +0xb3,0x90,0x57,0x46 = celfbr %f4, 5, %r6, 7 +0xb3,0x90,0x00,0xf0 = celfbr %f15, 0, %r0, 0 +0xb3,0xa0,0x00,0x00 = celgbr %f0, 0, %r0, 0 +0xb3,0xa0,0x0f,0x00 = celgbr %f0, 0, %r0, 15 +0xb3,0xa0,0x00,0x0f = celgbr %f0, 0, %r15, 0 +0xb3,0xa0,0xf0,0x00 = celgbr %f0, 15, %r0, 0 +0xb3,0xa0,0x57,0x46 = celgbr %f4, 5, %r6, 7 +0xb3,0xa0,0x00,0xf0 = celgbr %f15, 0, %r0, 0 +0xe3,0x00,0x00,0x00,0x80,0xcd = chf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xcd = chf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xcd = chf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xcd = chf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xcd = chf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xcd = chf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xcd = chf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xcd = chf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xcd = chf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xcd = chf %r15, 0 +0xcc,0x0d,0x80,0x00,0x00,0x00 = cih %r0, -2147483648 +0xcc,0x0d,0xff,0xff,0xff,0xff = cih %r0, -1 +0xcc,0x0d,0x00,0x00,0x00,0x00 = cih %r0, 0 +0xcc,0x0d,0x00,0x00,0x00,0x01 = cih %r0, 1 +0xcc,0x0d,0x7f,0xff,0xff,0xff = cih %r0, 2147483647 +0xcc,0xfd,0x00,0x00,0x00,0x00 = cih %r15, 0 +0xb3,0x9d,0x00,0x00 = clfdbr %r0, 0, %f0, 0 +0xb3,0x9d,0x0f,0x00 = clfdbr %r0, 0, %f0, 15 +0xb3,0x9d,0x00,0x0f = clfdbr %r0, 0, %f15, 0 +0xb3,0x9d,0xf0,0x00 = clfdbr %r0, 15, %f0, 0 +0xb3,0x9d,0x57,0x46 = clfdbr %r4, 5, %f6, 7 +0xb3,0x9d,0x00,0xf0 = clfdbr %r15, 0, %f0, 0 +0xb3,0x9c,0x00,0x00 = clfebr %r0, 0, %f0, 0 +0xb3,0x9c,0x0f,0x00 = clfebr %r0, 0, %f0, 15 +0xb3,0x9c,0x00,0x0f = clfebr %r0, 0, %f15, 0 +0xb3,0x9c,0xf0,0x00 = clfebr %r0, 15, %f0, 0 +0xb3,0x9c,0x57,0x46 = clfebr %r4, 5, %f6, 7 +0xb3,0x9c,0x00,0xf0 = clfebr %r15, 0, %f0, 0 +0xb3,0x9e,0x00,0x00 = clfxbr %r0, 0, %f0, 0 +0xb3,0x9e,0x0f,0x00 = clfxbr %r0, 0, %f0, 15 +0xb3,0x9e,0x00,0x0d = clfxbr %r0, 0, %f13, 0 +0xb3,0x9e,0xf0,0x00 = clfxbr %r0, 15, %f0, 0 +0xb3,0x9e,0x59,0x78 = clfxbr %r7, 5, %f8, 9 +0xb3,0x9e,0x00,0xf0 = clfxbr %r15, 0, %f0, 0 +0xb3,0xad,0x00,0x00 = clgdbr %r0, 0, %f0, 0 +0xb3,0xad,0x0f,0x00 = clgdbr %r0, 0, %f0, 15 +0xb3,0xad,0x00,0x0f = clgdbr %r0, 0, %f15, 0 +0xb3,0xad,0xf0,0x00 = clgdbr %r0, 15, %f0, 0 +0xb3,0xad,0x57,0x46 = clgdbr %r4, 5, %f6, 7 +0xb3,0xad,0x00,0xf0 = clgdbr %r15, 0, %f0, 0 +0xb3,0xac,0x00,0x00 = clgebr %r0, 0, %f0, 0 +0xb3,0xac,0x0f,0x00 = clgebr %r0, 0, %f0, 15 +0xb3,0xac,0x00,0x0f = clgebr %r0, 0, %f15, 0 +0xb3,0xac,0xf0,0x00 = clgebr %r0, 15, %f0, 0 +0xb3,0xac,0x57,0x46 = clgebr %r4, 5, %f6, 7 +0xb3,0xac,0x00,0xf0 = clgebr %r15, 0, %f0, 0 +0xb3,0xae,0x00,0x00 = clgxbr %r0, 0, %f0, 0 +0xb3,0xae,0x0f,0x00 = clgxbr %r0, 0, %f0, 15 +0xb3,0xae,0x00,0x0d = clgxbr %r0, 0, %f13, 0 +0xb3,0xae,0xf0,0x00 = clgxbr %r0, 15, %f0, 0 +0xb3,0xae,0x59,0x78 = clgxbr %r7, 5, %f8, 9 +0xb3,0xae,0x00,0xf0 = clgxbr %r15, 0, %f0, 0 +0xe3,0x00,0x00,0x00,0x80,0xcf = clhf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xcf = clhf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xcf = clhf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xcf = clhf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xcf = clhf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xcf = clhf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xcf = clhf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xcf = clhf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xcf = clhf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xcf = clhf %r15, 0 +0xcc,0x0f,0x00,0x00,0x00,0x00 = clih %r0, 0 +0xcc,0x0f,0x00,0x00,0x00,0x01 = clih %r0, 1 +0xcc,0x0f,0xff,0xff,0xff,0xff = clih %r0, 4294967295 +0xcc,0xff,0x00,0x00,0x00,0x00 = clih %r15, 0 +0xb3,0x92,0x00,0x00 = cxlfbr %f0, 0, %r0, 0 +0xb3,0x92,0x0f,0x00 = cxlfbr %f0, 0, %r0, 15 +0xb3,0x92,0x00,0x0f = cxlfbr %f0, 0, %r15, 0 +0xb3,0x92,0xf0,0x00 = cxlfbr %f0, 15, %r0, 0 +0xb3,0x92,0x5a,0x49 = cxlfbr %f4, 5, %r9, 10 +0xb3,0x92,0x00,0xd0 = cxlfbr %f13, 0, %r0, 0 +0xb3,0xa2,0x00,0x00 = cxlgbr %f0, 0, %r0, 0 +0xb3,0xa2,0x0f,0x00 = cxlgbr %f0, 0, %r0, 15 +0xb3,0xa2,0x00,0x0f = cxlgbr %f0, 0, %r15, 0 +0xb3,0xa2,0xf0,0x00 = cxlgbr %f0, 15, %r0, 0 +0xb3,0xa2,0x5a,0x49 = cxlgbr %f4, 5, %r9, 10 +0xb3,0xa2,0x00,0xd0 = cxlgbr %f13, 0, %r0, 0 +// 0xb3,0x5f,0x00,0x00 = fidbra %f0, 0, %f0, 0 +0xb3,0x5f,0x0f,0x00 = fidbra %f0, 0, %f0, 15 +// 0xb3,0x5f,0x00,0x0f = fidbra %f0, 0, %f15, 0 +// 0xb3,0x5f,0xf0,0x00 = fidbra %f0, 15, %f0, 0 +0xb3,0x5f,0x57,0x46 = fidbra %f4, 5, %f6, 7 +// 0xb3,0x5f,0x00,0xf0 = fidbra %f15, 0, %f0, 0 +// 0xb3,0x57,0x00,0x00 = fiebra %f0, 0, %f0, 0 +0xb3,0x57,0x0f,0x00 = fiebra %f0, 0, %f0, 15 +// 0xb3,0x57,0x00,0x0f = fiebra %f0, 0, %f15, 0 +// 0xb3,0x57,0xf0,0x00 = fiebra %f0, 15, %f0, 0 +0xb3,0x57,0x57,0x46 = fiebra %f4, 5, %f6, 7 +// 0xb3,0x57,0x00,0xf0 = fiebra %f15, 0, %f0, 0 +// 0xb3,0x47,0x00,0x00 = fixbra %f0, 0, %f0, 0 +0xb3,0x47,0x0f,0x00 = fixbra %f0, 0, %f0, 15 +// 0xb3,0x47,0x00,0x0d = fixbra %f0, 0, %f13, 0 +// 0xb3,0x47,0xf0,0x00 = fixbra %f0, 15, %f0, 0 +0xb3,0x47,0x59,0x48 = fixbra %f4, 5, %f8, 9 +// 0xb3,0x47,0x00,0xd0 = fixbra %f13, 0, %f0, 0 +0xeb,0x00,0x00,0x00,0x80,0xf8 = laa %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xf8 = laa %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xf8 = laa %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xf8 = laa %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xf8 = laa %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xf8 = laa %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xf8 = laa %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xf8 = laa %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xf8 = laa %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xf8 = laa %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xf8 = laa %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xe8 = laag %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xe8 = laag %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xe8 = laag %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xe8 = laag %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xe8 = laag %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xe8 = laag %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xe8 = laag %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xe8 = laag %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xe8 = laag %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xe8 = laag %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xe8 = laag %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xfa = laal %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xfa = laal %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xfa = laal %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xfa = laal %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xfa = laal %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xfa = laal %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xfa = laal %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xfa = laal %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xfa = laal %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xfa = laal %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xfa = laal %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xea = laalg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xea = laalg %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xea = laalg %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xea = laalg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xea = laalg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xea = laalg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xea = laalg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xea = laalg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xea = laalg %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xea = laalg %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xea = laalg %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xf4 = lan %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xf4 = lan %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xf4 = lan %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xf4 = lan %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xf4 = lan %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xf4 = lan %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xf4 = lan %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xf4 = lan %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xf4 = lan %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xf4 = lan %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xf4 = lan %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xe4 = lang %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xe4 = lang %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xe4 = lang %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xe4 = lang %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xe4 = lang %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xe4 = lang %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xe4 = lang %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xe4 = lang %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xe4 = lang %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xe4 = lang %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xe4 = lang %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xf6 = lao %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xf6 = lao %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xf6 = lao %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xf6 = lao %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xf6 = lao %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xf6 = lao %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xf6 = lao %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xf6 = lao %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xf6 = lao %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xf6 = lao %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xf6 = lao %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xe6 = laog %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xe6 = laog %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xe6 = laog %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xe6 = laog %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xe6 = laog %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xe6 = laog %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xe6 = laog %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xe6 = laog %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xe6 = laog %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xe6 = laog %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xe6 = laog %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xf7 = lax %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xf7 = lax %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xf7 = lax %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xf7 = lax %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xf7 = lax %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xf7 = lax %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xf7 = lax %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xf7 = lax %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xf7 = lax %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xf7 = lax %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xf7 = lax %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0xe7 = laxg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xe7 = laxg %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0xe7 = laxg %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0xe7 = laxg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xe7 = laxg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xe7 = laxg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0xe7 = laxg %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0xe7 = laxg %r15, %r0, 0 +0xe3,0x00,0x00,0x00,0x80,0xc0 = lbh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc0 = lbh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc0 = lbh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc0 = lbh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc0 = lbh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc0 = lbh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc0 = lbh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc0 = lbh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc0 = lbh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc0 = lbh %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xca = lfh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xca = lfh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xca = lfh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xca = lfh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xca = lfh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xca = lfh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xca = lfh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xca = lfh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xca = lfh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xca = lfh %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xc4 = lhh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc4 = lhh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc4 = lhh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc4 = lhh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc4 = lhh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc4 = lhh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc4 = lhh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc4 = lhh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc4 = lhh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc4 = lhh %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xc2 = llch %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc2 = llch %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc2 = llch %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc2 = llch %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc2 = llch %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc2 = llch %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc2 = llch %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc2 = llch %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc2 = llch %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc2 = llch %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xc6 = llhh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc6 = llhh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc6 = llhh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc6 = llhh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc6 = llhh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc6 = llhh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc6 = llhh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc6 = llhh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc6 = llhh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc6 = llhh %r15, 0 +0xeb,0x00,0x00,0x00,0x00,0xf2 = loc %r0, 0, 0 +0xeb,0x0f,0x00,0x00,0x00,0xf2 = loc %r0, 0, 15 +0xeb,0x00,0x00,0x00,0x80,0xf2 = loc %r0, -524288, 0 +0xeb,0x00,0x0f,0xff,0x7f,0xf2 = loc %r0, 524287, 0 +0xeb,0x00,0x10,0x00,0x00,0xf2 = loc %r0, 0(%r1), 0 +0xeb,0x00,0xf0,0x00,0x00,0xf2 = loc %r0, 0(%r15), 0 +0xeb,0xf0,0x00,0x00,0x00,0xf2 = loc %r15, 0, 0 +// 0xeb,0x13,0x2f,0xff,0x00,0xf2 = loc %r1, 4095(%r2), 3 +0xeb,0x11,0x30,0x02,0x00,0xf2 = loco %r1, 2(%r3) +0xeb,0x12,0x30,0x02,0x00,0xf2 = loch %r1, 2(%r3) +0xeb,0x13,0x30,0x02,0x00,0xf2 = locnle %r1, 2(%r3) +0xeb,0x14,0x30,0x02,0x00,0xf2 = locl %r1, 2(%r3) +0xeb,0x15,0x30,0x02,0x00,0xf2 = locnhe %r1, 2(%r3) +0xeb,0x16,0x30,0x02,0x00,0xf2 = loclh %r1, 2(%r3) +0xeb,0x17,0x30,0x02,0x00,0xf2 = locne %r1, 2(%r3) +0xeb,0x18,0x30,0x02,0x00,0xf2 = loce %r1, 2(%r3) +0xeb,0x19,0x30,0x02,0x00,0xf2 = locnlh %r1, 2(%r3) +0xeb,0x1a,0x30,0x02,0x00,0xf2 = loche %r1, 2(%r3) +0xeb,0x1b,0x30,0x02,0x00,0xf2 = locnl %r1, 2(%r3) +0xeb,0x1c,0x30,0x02,0x00,0xf2 = locle %r1, 2(%r3) +0xeb,0x1d,0x30,0x02,0x00,0xf2 = locnh %r1, 2(%r3) +0xeb,0x1e,0x30,0x02,0x00,0xf2 = locno %r1, 2(%r3) +0xeb,0x00,0x00,0x00,0x00,0xe2 = locg %r0, 0, 0 +0xeb,0x0f,0x00,0x00,0x00,0xe2 = locg %r0, 0, 15 +0xeb,0x00,0x00,0x00,0x80,0xe2 = locg %r0, -524288, 0 +0xeb,0x00,0x0f,0xff,0x7f,0xe2 = locg %r0, 524287, 0 +0xeb,0x00,0x10,0x00,0x00,0xe2 = locg %r0, 0(%r1), 0 +0xeb,0x00,0xf0,0x00,0x00,0xe2 = locg %r0, 0(%r15), 0 +0xeb,0xf0,0x00,0x00,0x00,0xe2 = locg %r15, 0, 0 +// 0xeb,0x13,0x2f,0xff,0x00,0xe2 = locg %r1, 4095(%r2), 3 +0xeb,0x11,0x30,0x02,0x00,0xe2 = locgo %r1, 2(%r3) +0xeb,0x12,0x30,0x02,0x00,0xe2 = locgh %r1, 2(%r3) +0xeb,0x13,0x30,0x02,0x00,0xe2 = locgnle %r1, 2(%r3) +0xeb,0x14,0x30,0x02,0x00,0xe2 = locgl %r1, 2(%r3) +0xeb,0x15,0x30,0x02,0x00,0xe2 = locgnhe %r1, 2(%r3) +0xeb,0x16,0x30,0x02,0x00,0xe2 = locglh %r1, 2(%r3) +0xeb,0x17,0x30,0x02,0x00,0xe2 = locgne %r1, 2(%r3) +0xeb,0x18,0x30,0x02,0x00,0xe2 = locge %r1, 2(%r3) +0xeb,0x19,0x30,0x02,0x00,0xe2 = locgnlh %r1, 2(%r3) +0xeb,0x1a,0x30,0x02,0x00,0xe2 = locghe %r1, 2(%r3) +0xeb,0x1b,0x30,0x02,0x00,0xe2 = locgnl %r1, 2(%r3) +0xeb,0x1c,0x30,0x02,0x00,0xe2 = locgle %r1, 2(%r3) +0xeb,0x1d,0x30,0x02,0x00,0xe2 = locgnh %r1, 2(%r3) +0xeb,0x1e,0x30,0x02,0x00,0xe2 = locgno %r1, 2(%r3) +0xb9,0xe2,0x00,0x12 = locgr %r1, %r2, 0 +0xb9,0xe2,0xf0,0x12 = locgr %r1, %r2, 15 +0xb9,0xe2,0x10,0x13 = locgro %r1, %r3 +0xb9,0xe2,0x20,0x13 = locgrh %r1, %r3 +0xb9,0xe2,0x30,0x13 = locgrnle %r1, %r3 +0xb9,0xe2,0x40,0x13 = locgrl %r1, %r3 +0xb9,0xe2,0x50,0x13 = locgrnhe %r1, %r3 +0xb9,0xe2,0x60,0x13 = locgrlh %r1, %r3 +0xb9,0xe2,0x70,0x13 = locgrne %r1, %r3 +0xb9,0xe2,0x80,0x13 = locgre %r1, %r3 +0xb9,0xe2,0x90,0x13 = locgrnlh %r1, %r3 +0xb9,0xe2,0xa0,0x13 = locgrhe %r1, %r3 +0xb9,0xe2,0xb0,0x13 = locgrnl %r1, %r3 +0xb9,0xe2,0xc0,0x13 = locgrle %r1, %r3 +0xb9,0xe2,0xd0,0x13 = locgrnh %r1, %r3 +0xb9,0xe2,0xe0,0x13 = locgrno %r1, %r3 +0xb9,0xf2,0x00,0x12 = locr %r1, %r2, 0 +0xb9,0xf2,0xf0,0x12 = locr %r1, %r2, 15 +0xb9,0xf2,0x10,0x13 = locro %r1, %r3 +0xb9,0xf2,0x20,0x13 = locrh %r1, %r3 +0xb9,0xf2,0x30,0x13 = locrnle %r1, %r3 +0xb9,0xf2,0x40,0x13 = locrl %r1, %r3 +0xb9,0xf2,0x50,0x13 = locrnhe %r1, %r3 +0xb9,0xf2,0x60,0x13 = locrlh %r1, %r3 +0xb9,0xf2,0x70,0x13 = locrne %r1, %r3 +0xb9,0xf2,0x80,0x13 = locre %r1, %r3 +0xb9,0xf2,0x90,0x13 = locrnlh %r1, %r3 +0xb9,0xf2,0xa0,0x13 = locrhe %r1, %r3 +0xb9,0xf2,0xb0,0x13 = locrnl %r1, %r3 +0xb9,0xf2,0xc0,0x13 = locrle %r1, %r3 +0xb9,0xf2,0xd0,0x13 = locrnh %r1, %r3 +0xb9,0xf2,0xe0,0x13 = locrno %r1, %r3 +0xb9,0xe4,0x00,0x00 = ngrk %r0, %r0, %r0 +0xb9,0xe4,0xf0,0x00 = ngrk %r0, %r0, %r15 +0xb9,0xe4,0x00,0x0f = ngrk %r0, %r15, %r0 +0xb9,0xe4,0x00,0xf0 = ngrk %r15, %r0, %r0 +0xb9,0xe4,0x90,0x78 = ngrk %r7, %r8, %r9 +0xb9,0xf4,0x00,0x00 = nrk %r0, %r0, %r0 +0xb9,0xf4,0xf0,0x00 = nrk %r0, %r0, %r15 +0xb9,0xf4,0x00,0x0f = nrk %r0, %r15, %r0 +0xb9,0xf4,0x00,0xf0 = nrk %r15, %r0, %r0 +0xb9,0xf4,0x90,0x78 = nrk %r7, %r8, %r9 +0xb9,0xe6,0x00,0x00 = ogrk %r0, %r0, %r0 +0xb9,0xe6,0xf0,0x00 = ogrk %r0, %r0, %r15 +0xb9,0xe6,0x00,0x0f = ogrk %r0, %r15, %r0 +0xb9,0xe6,0x00,0xf0 = ogrk %r15, %r0, %r0 +0xb9,0xe6,0x90,0x78 = ogrk %r7, %r8, %r9 +0xb9,0xf6,0x00,0x00 = ork %r0, %r0, %r0 +0xb9,0xf6,0xf0,0x00 = ork %r0, %r0, %r15 +0xb9,0xf6,0x00,0x0f = ork %r0, %r15, %r0 +0xb9,0xf6,0x00,0xf0 = ork %r15, %r0, %r0 +0xb9,0xf6,0x90,0x78 = ork %r7, %r8, %r9 +0xec,0x00,0x00,0x00,0x00,0x5d = risbhg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x5d = risbhg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x5d = risbhg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x5d = risbhg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x5d = risbhg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x5d = risbhg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x5d = risbhg %r4, %r5, 6, 7, 8 +0xec,0x00,0x00,0x00,0x00,0x51 = risblg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x51 = risblg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x51 = risblg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x51 = risblg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x51 = risblg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x51 = risblg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x51 = risblg %r4, %r5, 6, 7, 8 +0xb9,0xe9,0x00,0x00 = sgrk %r0, %r0, %r0 +0xb9,0xe9,0xf0,0x00 = sgrk %r0, %r0, %r15 +0xb9,0xe9,0x00,0x0f = sgrk %r0, %r15, %r0 +0xb9,0xe9,0x00,0xf0 = sgrk %r15, %r0, %r0 +0xb9,0xe9,0x90,0x78 = sgrk %r7, %r8, %r9 +0xb9,0xeb,0x00,0x00 = slgrk %r0, %r0, %r0 +0xb9,0xeb,0xf0,0x00 = slgrk %r0, %r0, %r15 +0xb9,0xeb,0x00,0x0f = slgrk %r0, %r15, %r0 +0xb9,0xeb,0x00,0xf0 = slgrk %r15, %r0, %r0 +0xb9,0xeb,0x90,0x78 = slgrk %r7, %r8, %r9 +0xb9,0xfb,0x00,0x00 = slrk %r0, %r0, %r0 +0xb9,0xfb,0xf0,0x00 = slrk %r0, %r0, %r15 +0xb9,0xfb,0x00,0x0f = slrk %r0, %r15, %r0 +0xb9,0xfb,0x00,0xf0 = slrk %r15, %r0, %r0 +0xb9,0xfb,0x90,0x78 = slrk %r7, %r8, %r9 +0xeb,0x00,0x00,0x00,0x00,0xdf = sllk %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0xdf = sllk %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0xdf = sllk %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0xdf = sllk %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0xdf = sllk %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xdf = sllk %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0xdf = sllk %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xdf = sllk %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xdf = sllk %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xdf = sllk %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xdf = sllk %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xdf = sllk %r0, %r0, 524287(%r15) +0xeb,0x00,0x00,0x00,0x00,0xdc = srak %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0xdc = srak %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0xdc = srak %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0xdc = srak %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0xdc = srak %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xdc = srak %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0xdc = srak %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xdc = srak %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xdc = srak %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xdc = srak %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xdc = srak %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xdc = srak %r0, %r0, 524287(%r15) +0xb9,0xf9,0x00,0x00 = srk %r0, %r0, %r0 +0xb9,0xf9,0xf0,0x00 = srk %r0, %r0, %r15 +0xb9,0xf9,0x00,0x0f = srk %r0, %r15, %r0 +0xb9,0xf9,0x00,0xf0 = srk %r15, %r0, %r0 +0xb9,0xf9,0x90,0x78 = srk %r7, %r8, %r9 +0xeb,0x00,0x00,0x00,0x00,0xde = srlk %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0xde = srlk %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0xde = srlk %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0xde = srlk %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0xde = srlk %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0xde = srlk %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0xde = srlk %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0xde = srlk %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0xde = srlk %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0xde = srlk %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0xde = srlk %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0xde = srlk %r0, %r0, 524287(%r15) +0xe3,0x00,0x00,0x00,0x80,0xc3 = stch %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc3 = stch %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc3 = stch %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc3 = stch %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc3 = stch %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc3 = stch %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc3 = stch %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc3 = stch %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc3 = stch %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc3 = stch %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xc7 = sthh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xc7 = sthh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xc7 = sthh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xc7 = sthh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xc7 = sthh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xc7 = sthh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xc7 = sthh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xc7 = sthh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xc7 = sthh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xc7 = sthh %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0xcb = stfh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0xcb = stfh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0xcb = stfh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0xcb = stfh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0xcb = stfh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0xcb = stfh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0xcb = stfh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0xcb = stfh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0xcb = stfh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0xcb = stfh %r15, 0 +0xeb,0x00,0x00,0x00,0x00,0xf3 = stoc %r0, 0, 0 +0xeb,0x0f,0x00,0x00,0x00,0xf3 = stoc %r0, 0, 15 +0xeb,0x00,0x00,0x00,0x80,0xf3 = stoc %r0, -524288, 0 +0xeb,0x00,0x0f,0xff,0x7f,0xf3 = stoc %r0, 524287, 0 +0xeb,0x00,0x10,0x00,0x00,0xf3 = stoc %r0, 0(%r1), 0 +0xeb,0x00,0xf0,0x00,0x00,0xf3 = stoc %r0, 0(%r15), 0 +0xeb,0xf0,0x00,0x00,0x00,0xf3 = stoc %r15, 0, 0 +// 0xeb,0x13,0x2f,0xff,0x00,0xf3 = stoc %r1, 4095(%r2), 3 +0xeb,0x11,0x30,0x02,0x00,0xf3 = stoco %r1, 2(%r3) +0xeb,0x12,0x30,0x02,0x00,0xf3 = stoch %r1, 2(%r3) +0xeb,0x13,0x30,0x02,0x00,0xf3 = stocnle %r1, 2(%r3) +0xeb,0x14,0x30,0x02,0x00,0xf3 = stocl %r1, 2(%r3) +0xeb,0x15,0x30,0x02,0x00,0xf3 = stocnhe %r1, 2(%r3) +0xeb,0x16,0x30,0x02,0x00,0xf3 = stoclh %r1, 2(%r3) +0xeb,0x17,0x30,0x02,0x00,0xf3 = stocne %r1, 2(%r3) +0xeb,0x18,0x30,0x02,0x00,0xf3 = stoce %r1, 2(%r3) +0xeb,0x19,0x30,0x02,0x00,0xf3 = stocnlh %r1, 2(%r3) +0xeb,0x1a,0x30,0x02,0x00,0xf3 = stoche %r1, 2(%r3) +0xeb,0x1b,0x30,0x02,0x00,0xf3 = stocnl %r1, 2(%r3) +0xeb,0x1c,0x30,0x02,0x00,0xf3 = stocle %r1, 2(%r3) +0xeb,0x1d,0x30,0x02,0x00,0xf3 = stocnh %r1, 2(%r3) +0xeb,0x1e,0x30,0x02,0x00,0xf3 = stocno %r1, 2(%r3) +0xeb,0x00,0x00,0x00,0x00,0xe3 = stocg %r0, 0, 0 +0xeb,0x0f,0x00,0x00,0x00,0xe3 = stocg %r0, 0, 15 +0xeb,0x00,0x00,0x00,0x80,0xe3 = stocg %r0, -524288, 0 +0xeb,0x00,0x0f,0xff,0x7f,0xe3 = stocg %r0, 524287, 0 +0xeb,0x00,0x10,0x00,0x00,0xe3 = stocg %r0, 0(%r1), 0 +0xeb,0x00,0xf0,0x00,0x00,0xe3 = stocg %r0, 0(%r15), 0 +0xeb,0xf0,0x00,0x00,0x00,0xe3 = stocg %r15, 0, 0 +// 0xeb,0x13,0x2f,0xff,0x00,0xe3 = stocg %r1, 4095(%r2), 3 +0xeb,0x11,0x30,0x02,0x00,0xe3 = stocgo %r1, 2(%r3) +0xeb,0x12,0x30,0x02,0x00,0xe3 = stocgh %r1, 2(%r3) +0xeb,0x13,0x30,0x02,0x00,0xe3 = stocgnle %r1, 2(%r3) +0xeb,0x14,0x30,0x02,0x00,0xe3 = stocgl %r1, 2(%r3) +0xeb,0x15,0x30,0x02,0x00,0xe3 = stocgnhe %r1, 2(%r3) +0xeb,0x16,0x30,0x02,0x00,0xe3 = stocglh %r1, 2(%r3) +0xeb,0x17,0x30,0x02,0x00,0xe3 = stocgne %r1, 2(%r3) +0xeb,0x18,0x30,0x02,0x00,0xe3 = stocge %r1, 2(%r3) +0xeb,0x19,0x30,0x02,0x00,0xe3 = stocgnlh %r1, 2(%r3) +0xeb,0x1a,0x30,0x02,0x00,0xe3 = stocghe %r1, 2(%r3) +0xeb,0x1b,0x30,0x02,0x00,0xe3 = stocgnl %r1, 2(%r3) +0xeb,0x1c,0x30,0x02,0x00,0xe3 = stocgle %r1, 2(%r3) +0xeb,0x1d,0x30,0x02,0x00,0xe3 = stocgnh %r1, 2(%r3) +0xeb,0x1e,0x30,0x02,0x00,0xe3 = stocgno %r1, 2(%r3) +0xb9,0xe7,0x00,0x00 = xgrk %r0, %r0, %r0 +0xb9,0xe7,0xf0,0x00 = xgrk %r0, %r0, %r15 +0xb9,0xe7,0x00,0x0f = xgrk %r0, %r15, %r0 +0xb9,0xe7,0x00,0xf0 = xgrk %r15, %r0, %r0 +0xb9,0xe7,0x90,0x78 = xgrk %r7, %r8, %r9 +0xb9,0xf7,0x00,0x00 = xrk %r0, %r0, %r0 +0xb9,0xf7,0xf0,0x00 = xrk %r0, %r0, %r15 +0xb9,0xf7,0x00,0x0f = xrk %r0, %r15, %r0 +0xb9,0xf7,0x00,0xf0 = xrk %r15, %r0, %r0 +0xb9,0xf7,0x90,0x78 = xrk %r7, %r8, %r9 diff --git a/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good.s.cs b/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good.s.cs new file mode 100644 index 0000000..3cb6a4b --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/SystemZ/insn-good.s.cs @@ -0,0 +1,2265 @@ +# CS_ARCH_SYSZ, 0, None +0x5a,0x00,0x00,0x00 = a %r0, 0 +0x5a,0x00,0x0f,0xff = a %r0, 4095 +0x5a,0x00,0x10,0x00 = a %r0, 0(%r1) +0x5a,0x00,0xf0,0x00 = a %r0, 0(%r15) +0x5a,0x01,0xff,0xff = a %r0, 4095(%r1, %r15) +0x5a,0x0f,0x1f,0xff = a %r0, 4095(%r15, %r1) +0x5a,0xf0,0x00,0x00 = a %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x1a = adb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1a = adb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1a = adb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1a = adb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1a = adb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1a = adb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1a = adb %f15, 0 +0xb3,0x1a,0x00,0x00 = adbr %f0, %f0 +0xb3,0x1a,0x00,0x0f = adbr %f0, %f15 +0xb3,0x1a,0x00,0x78 = adbr %f7, %f8 +0xb3,0x1a,0x00,0xf0 = adbr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x0a = aeb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0a = aeb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0a = aeb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0a = aeb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0a = aeb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0a = aeb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0a = aeb %f15, 0 +0xb3,0x0a,0x00,0x00 = aebr %f0, %f0 +0xb3,0x0a,0x00,0x0f = aebr %f0, %f15 +0xb3,0x0a,0x00,0x78 = aebr %f7, %f8 +0xb3,0x0a,0x00,0xf0 = aebr %f15, %f0 +0xc2,0x09,0x80,0x00,0x00,0x00 = afi %r0, -2147483648 +0xc2,0x09,0xff,0xff,0xff,0xff = afi %r0, -1 +0xc2,0x09,0x00,0x00,0x00,0x00 = afi %r0, 0 +0xc2,0x09,0x00,0x00,0x00,0x01 = afi %r0, 1 +0xc2,0x09,0x7f,0xff,0xff,0xff = afi %r0, 2147483647 +0xc2,0xf9,0x00,0x00,0x00,0x00 = afi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x08 = ag %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x08 = ag %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x08 = ag %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x08 = ag %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x08 = ag %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x08 = ag %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x08 = ag %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x08 = ag %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x08 = ag %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x08 = ag %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x18 = agf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x18 = agf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x18 = agf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x18 = agf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x18 = agf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x18 = agf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x18 = agf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x18 = agf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x18 = agf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x18 = agf %r15, 0 +0xc2,0x08,0x80,0x00,0x00,0x00 = agfi %r0, -2147483648 +0xc2,0x08,0xff,0xff,0xff,0xff = agfi %r0, -1 +0xc2,0x08,0x00,0x00,0x00,0x00 = agfi %r0, 0 +0xc2,0x08,0x00,0x00,0x00,0x01 = agfi %r0, 1 +0xc2,0x08,0x7f,0xff,0xff,0xff = agfi %r0, 2147483647 +0xc2,0xf8,0x00,0x00,0x00,0x00 = agfi %r15, 0 +0xb9,0x18,0x00,0x00 = agfr %r0, %r0 +0xb9,0x18,0x00,0x0f = agfr %r0, %r15 +0xb9,0x18,0x00,0xf0 = agfr %r15, %r0 +0xb9,0x18,0x00,0x78 = agfr %r7, %r8 +0xa7,0x0b,0x80,0x00 = aghi %r0, -32768 +0xa7,0x0b,0xff,0xff = aghi %r0, -1 +0xa7,0x0b,0x00,0x00 = aghi %r0, 0 +0xa7,0x0b,0x00,0x01 = aghi %r0, 1 +0xa7,0x0b,0x7f,0xff = aghi %r0, 32767 +0xa7,0xfb,0x00,0x00 = aghi %r15, 0 +0xb9,0x08,0x00,0x00 = agr %r0, %r0 +0xb9,0x08,0x00,0x0f = agr %r0, %r15 +0xb9,0x08,0x00,0xf0 = agr %r15, %r0 +0xb9,0x08,0x00,0x78 = agr %r7, %r8 +0xeb,0x00,0x00,0x00,0x80,0x7a = agsi -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x7a = agsi -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x7a = agsi 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x7a = agsi 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x7a = agsi 524287, 0 +0xeb,0x80,0x00,0x00,0x00,0x7a = agsi 0, -128 +0xeb,0xff,0x00,0x00,0x00,0x7a = agsi 0, -1 +0xeb,0x01,0x00,0x00,0x00,0x7a = agsi 0, 1 +0xeb,0x7f,0x00,0x00,0x00,0x7a = agsi 0, 127 +0xeb,0x2a,0x10,0x00,0x00,0x7a = agsi 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x7a = agsi 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x7a = agsi 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x7a = agsi 524287(%r15), 42 +0x4a,0x00,0x00,0x00 = ah %r0, 0 +0x4a,0x00,0x0f,0xff = ah %r0, 4095 +0x4a,0x00,0x10,0x00 = ah %r0, 0(%r1) +0x4a,0x00,0xf0,0x00 = ah %r0, 0(%r15) +0x4a,0x01,0xff,0xff = ah %r0, 4095(%r1, %r15) +0x4a,0x0f,0x1f,0xff = ah %r0, 4095(%r15, %r1) +0x4a,0xf0,0x00,0x00 = ah %r15, 0 +0xa7,0x0a,0x80,0x00 = ahi %r0, -32768 +0xa7,0x0a,0xff,0xff = ahi %r0, -1 +0xa7,0x0a,0x00,0x00 = ahi %r0, 0 +0xa7,0x0a,0x00,0x01 = ahi %r0, 1 +0xa7,0x0a,0x7f,0xff = ahi %r0, 32767 +0xa7,0xfa,0x00,0x00 = ahi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x7a = ahy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x7a = ahy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x7a = ahy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x7a = ahy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x7a = ahy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x7a = ahy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x7a = ahy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x7a = ahy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x7a = ahy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x7a = ahy %r15, 0 +0x5e,0x00,0x00,0x00 = al %r0, 0 +0x5e,0x00,0x0f,0xff = al %r0, 4095 +0x5e,0x00,0x10,0x00 = al %r0, 0(%r1) +0x5e,0x00,0xf0,0x00 = al %r0, 0(%r15) +0x5e,0x01,0xff,0xff = al %r0, 4095(%r1, %r15) +0x5e,0x0f,0x1f,0xff = al %r0, 4095(%r15, %r1) +0x5e,0xf0,0x00,0x00 = al %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x98 = alc %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x98 = alc %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x98 = alc %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x98 = alc %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x98 = alc %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x98 = alc %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x98 = alc %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x98 = alc %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x98 = alc %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x98 = alc %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x88 = alcg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x88 = alcg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x88 = alcg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x88 = alcg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x88 = alcg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x88 = alcg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x88 = alcg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x88 = alcg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x88 = alcg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x88 = alcg %r15, 0 +0xb9,0x88,0x00,0x00 = alcgr %r0, %r0 +0xb9,0x88,0x00,0x0f = alcgr %r0, %r15 +0xb9,0x88,0x00,0xf0 = alcgr %r15, %r0 +0xb9,0x88,0x00,0x78 = alcgr %r7, %r8 +0xb9,0x98,0x00,0x00 = alcr %r0, %r0 +0xb9,0x98,0x00,0x0f = alcr %r0, %r15 +0xb9,0x98,0x00,0xf0 = alcr %r15, %r0 +0xb9,0x98,0x00,0x78 = alcr %r7, %r8 +0xc2,0x0b,0x00,0x00,0x00,0x00 = alfi %r0, 0 +0xc2,0x0b,0xff,0xff,0xff,0xff = alfi %r0, 4294967295 +0xc2,0xfb,0x00,0x00,0x00,0x00 = alfi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x0a = alg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x0a = alg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x0a = alg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x0a = alg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x0a = alg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x0a = alg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x0a = alg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x0a = alg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x0a = alg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x0a = alg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x1a = algf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x1a = algf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x1a = algf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x1a = algf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x1a = algf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x1a = algf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x1a = algf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x1a = algf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x1a = algf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x1a = algf %r15, 0 +0xc2,0x0a,0x00,0x00,0x00,0x00 = algfi %r0, 0 +0xc2,0x0a,0xff,0xff,0xff,0xff = algfi %r0, 4294967295 +0xc2,0xfa,0x00,0x00,0x00,0x00 = algfi %r15, 0 +0xb9,0x1a,0x00,0x00 = algfr %r0, %r0 +0xb9,0x1a,0x00,0x0f = algfr %r0, %r15 +0xb9,0x1a,0x00,0xf0 = algfr %r15, %r0 +0xb9,0x1a,0x00,0x78 = algfr %r7, %r8 +0xb9,0x0a,0x00,0x00 = algr %r0, %r0 +0xb9,0x0a,0x00,0x0f = algr %r0, %r15 +0xb9,0x0a,0x00,0xf0 = algr %r15, %r0 +0xb9,0x0a,0x00,0x78 = algr %r7, %r8 +0x1e,0x00 = alr %r0, %r0 +0x1e,0x0f = alr %r0, %r15 +0x1e,0xf0 = alr %r15, %r0 +0x1e,0x78 = alr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x5e = aly %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x5e = aly %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x5e = aly %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x5e = aly %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x5e = aly %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x5e = aly %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x5e = aly %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x5e = aly %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x5e = aly %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x5e = aly %r15, 0 +0x1a,0x00 = ar %r0, %r0 +0x1a,0x0f = ar %r0, %r15 +0x1a,0xf0 = ar %r15, %r0 +0x1a,0x78 = ar %r7, %r8 +0xeb,0x00,0x00,0x00,0x80,0x6a = asi -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x6a = asi -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x6a = asi 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x6a = asi 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x6a = asi 524287, 0 +0xeb,0x80,0x00,0x00,0x00,0x6a = asi 0, -128 +0xeb,0xff,0x00,0x00,0x00,0x6a = asi 0, -1 +0xeb,0x01,0x00,0x00,0x00,0x6a = asi 0, 1 +0xeb,0x7f,0x00,0x00,0x00,0x6a = asi 0, 127 +0xeb,0x2a,0x10,0x00,0x00,0x6a = asi 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x6a = asi 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x6a = asi 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x6a = asi 524287(%r15), 42 +0xb3,0x4a,0x00,0x00 = axbr %f0, %f0 +0xb3,0x4a,0x00,0x0d = axbr %f0, %f13 +0xb3,0x4a,0x00,0x88 = axbr %f8, %f8 +0xb3,0x4a,0x00,0xd0 = axbr %f13, %f0 +0xe3,0x00,0x00,0x00,0x80,0x5a = ay %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x5a = ay %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x5a = ay %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x5a = ay %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x5a = ay %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x5a = ay %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x5a = ay %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x5a = ay %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x5a = ay %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x5a = ay %r15, 0 +0x0d,0x01 = basr %r0, %r1 +0x0d,0x0f = basr %r0, %r15 +0x0d,0xe9 = basr %r14, %r9 +0x0d,0xf1 = basr %r15, %r1 +0x07,0x00 = bcr 0, %r0 +0x07,0x0f = bcr 0, %r15 +// 0x07,0x17 = bcr 1, %r7 +0x07,0x1f = bor %r15 +// 0x07,0x27 = bcr 2, %r7 +0x07,0x2f = bhr %r15 +// 0x07,0x37 = bcr 3, %r7 +0x07,0x3f = bnler %r15 +// 0x07,0x47 = bcr 4, %r7 +0x07,0x4f = blr %r15 +// 0x07,0x57 = bcr 5, %r7 +0x07,0x5f = bnher %r15 +// 0x07,0x67 = bcr 6, %r7 +0x07,0x6f = blhr %r15 +// 0x07,0x77 = bcr 7, %r7 +0x07,0x7f = bner %r15 +// 0x07,0x87 = bcr 8, %r7 +0x07,0x8f = ber %r15 +// 0x07,0x97 = bcr 9, %r7 +0x07,0x9f = bnlhr %r15 +// 0x07,0xa7 = bcr 10, %r7 +0x07,0xaf = bher %r15 +// 0x07,0xb7 = bcr 11, %r7 +0x07,0xbf = bnlr %r15 +// 0x07,0xc7 = bcr 12, %r7 +0x07,0xcf = bler %r15 +// 0x07,0xd7 = bcr 13, %r7 +0x07,0xdf = bnhr %r15 +// 0x07,0xe7 = bcr 14, %r7 +0x07,0xef = bnor %r15 +// 0x07,0xf7 = bcr 15, %r7 +0x07,0xf1 = br %r1 +0x07,0xfe = br %r14 +0x07,0xff = br %r15 +0x59,0x00,0x00,0x00 = c %r0, 0 +0x59,0x00,0x0f,0xff = c %r0, 4095 +0x59,0x00,0x10,0x00 = c %r0, 0(%r1) +0x59,0x00,0xf0,0x00 = c %r0, 0(%r15) +0x59,0x01,0xff,0xff = c %r0, 4095(%r1, %r15) +0x59,0x0f,0x1f,0xff = c %r0, 4095(%r15, %r1) +0x59,0xf0,0x00,0x00 = c %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x19 = cdb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x19 = cdb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x19 = cdb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x19 = cdb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x19 = cdb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x19 = cdb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x19 = cdb %f15, 0 +0xb3,0x19,0x00,0x00 = cdbr %f0, %f0 +0xb3,0x19,0x00,0x0f = cdbr %f0, %f15 +0xb3,0x19,0x00,0x78 = cdbr %f7, %f8 +0xb3,0x19,0x00,0xf0 = cdbr %f15, %f0 +0xb3,0x95,0x00,0x00 = cdfbr %f0, %r0 +0xb3,0x95,0x00,0x0f = cdfbr %f0, %r15 +0xb3,0x95,0x00,0xf0 = cdfbr %f15, %r0 +0xb3,0x95,0x00,0x78 = cdfbr %f7, %r8 +0xb3,0x95,0x00,0xff = cdfbr %f15, %r15 +0xb3,0xa5,0x00,0x00 = cdgbr %f0, %r0 +0xb3,0xa5,0x00,0x0f = cdgbr %f0, %r15 +0xb3,0xa5,0x00,0xf0 = cdgbr %f15, %r0 +0xb3,0xa5,0x00,0x78 = cdgbr %f7, %r8 +0xb3,0xa5,0x00,0xff = cdgbr %f15, %r15 +0xed,0x00,0x00,0x00,0x00,0x09 = ceb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x09 = ceb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x09 = ceb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x09 = ceb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x09 = ceb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x09 = ceb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x09 = ceb %f15, 0 +0xb3,0x09,0x00,0x00 = cebr %f0, %f0 +0xb3,0x09,0x00,0x0f = cebr %f0, %f15 +0xb3,0x09,0x00,0x78 = cebr %f7, %f8 +0xb3,0x09,0x00,0xf0 = cebr %f15, %f0 +0xb3,0x94,0x00,0x00 = cefbr %f0, %r0 +0xb3,0x94,0x00,0x0f = cefbr %f0, %r15 +0xb3,0x94,0x00,0xf0 = cefbr %f15, %r0 +0xb3,0x94,0x00,0x78 = cefbr %f7, %r8 +0xb3,0x94,0x00,0xff = cefbr %f15, %r15 +0xb3,0xa4,0x00,0x00 = cegbr %f0, %r0 +0xb3,0xa4,0x00,0x0f = cegbr %f0, %r15 +0xb3,0xa4,0x00,0xf0 = cegbr %f15, %r0 +0xb3,0xa4,0x00,0x78 = cegbr %f7, %r8 +0xb3,0xa4,0x00,0xff = cegbr %f15, %r15 +0xb3,0x99,0x00,0x00 = cfdbr %r0, 0, %f0 +0xb3,0x99,0x00,0x0f = cfdbr %r0, 0, %f15 +0xb3,0x99,0xf0,0x00 = cfdbr %r0, 15, %f0 +0xb3,0x99,0x50,0x46 = cfdbr %r4, 5, %f6 +0xb3,0x99,0x00,0xf0 = cfdbr %r15, 0, %f0 +0xb3,0x98,0x00,0x00 = cfebr %r0, 0, %f0 +0xb3,0x98,0x00,0x0f = cfebr %r0, 0, %f15 +0xb3,0x98,0xf0,0x00 = cfebr %r0, 15, %f0 +0xb3,0x98,0x50,0x46 = cfebr %r4, 5, %f6 +0xb3,0x98,0x00,0xf0 = cfebr %r15, 0, %f0 +0xc2,0x0d,0x80,0x00,0x00,0x00 = cfi %r0, -2147483648 +0xc2,0x0d,0xff,0xff,0xff,0xff = cfi %r0, -1 +0xc2,0x0d,0x00,0x00,0x00,0x00 = cfi %r0, 0 +0xc2,0x0d,0x00,0x00,0x00,0x01 = cfi %r0, 1 +0xc2,0x0d,0x7f,0xff,0xff,0xff = cfi %r0, 2147483647 +0xc2,0xfd,0x00,0x00,0x00,0x00 = cfi %r15, 0 +0xb3,0x9a,0x00,0x00 = cfxbr %r0, 0, %f0 +0xb3,0x9a,0x00,0x0d = cfxbr %r0, 0, %f13 +0xb3,0x9a,0xf0,0x00 = cfxbr %r0, 15, %f0 +0xb3,0x9a,0x50,0x48 = cfxbr %r4, 5, %f8 +0xb3,0x9a,0x00,0xf0 = cfxbr %r15, 0, %f0 +0xe3,0x00,0x00,0x00,0x80,0x20 = cg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x20 = cg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x20 = cg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x20 = cg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x20 = cg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x20 = cg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x20 = cg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x20 = cg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x20 = cg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x20 = cg %r15, 0 +0xb3,0xa9,0x00,0x00 = cgdbr %r0, 0, %f0 +0xb3,0xa9,0x00,0x0f = cgdbr %r0, 0, %f15 +0xb3,0xa9,0xf0,0x00 = cgdbr %r0, 15, %f0 +0xb3,0xa9,0x50,0x46 = cgdbr %r4, 5, %f6 +0xb3,0xa9,0x00,0xf0 = cgdbr %r15, 0, %f0 +0xb3,0xa8,0x00,0x00 = cgebr %r0, 0, %f0 +0xb3,0xa8,0x00,0x0f = cgebr %r0, 0, %f15 +0xb3,0xa8,0xf0,0x00 = cgebr %r0, 15, %f0 +0xb3,0xa8,0x50,0x46 = cgebr %r4, 5, %f6 +0xb3,0xa8,0x00,0xf0 = cgebr %r15, 0, %f0 +0xe3,0x00,0x00,0x00,0x80,0x30 = cgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x30 = cgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x30 = cgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x30 = cgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x30 = cgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x30 = cgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x30 = cgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x30 = cgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x30 = cgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x30 = cgf %r15, 0 +0xc2,0x0c,0x80,0x00,0x00,0x00 = cgfi %r0, -2147483648 +0xc2,0x0c,0xff,0xff,0xff,0xff = cgfi %r0, -1 +0xc2,0x0c,0x00,0x00,0x00,0x00 = cgfi %r0, 0 +0xc2,0x0c,0x00,0x00,0x00,0x01 = cgfi %r0, 1 +0xc2,0x0c,0x7f,0xff,0xff,0xff = cgfi %r0, 2147483647 +0xc2,0xfc,0x00,0x00,0x00,0x00 = cgfi %r15, 0 +0xb9,0x30,0x00,0x00 = cgfr %r0, %r0 +0xb9,0x30,0x00,0x0f = cgfr %r0, %r15 +0xb9,0x30,0x00,0xf0 = cgfr %r15, %r0 +0xb9,0x30,0x00,0x78 = cgfr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x34 = cgh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x34 = cgh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x34 = cgh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x34 = cgh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x34 = cgh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x34 = cgh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x34 = cgh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x34 = cgh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x34 = cgh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x34 = cgh %r15, 0 +0xa7,0x0f,0x80,0x00 = cghi %r0, -32768 +0xa7,0x0f,0xff,0xff = cghi %r0, -1 +0xa7,0x0f,0x00,0x00 = cghi %r0, 0 +0xa7,0x0f,0x00,0x01 = cghi %r0, 1 +0xa7,0x0f,0x7f,0xff = cghi %r0, 32767 +0xa7,0xff,0x00,0x00 = cghi %r15, 0 +0xe5,0x58,0x00,0x00,0x00,0x00 = cghsi 0, 0 +0xe5,0x58,0x0f,0xff,0x00,0x00 = cghsi 4095, 0 +0xe5,0x58,0x00,0x00,0x80,0x00 = cghsi 0, -32768 +0xe5,0x58,0x00,0x00,0xff,0xff = cghsi 0, -1 +0xe5,0x58,0x00,0x00,0x00,0x00 = cghsi 0, 0 +0xe5,0x58,0x00,0x00,0x00,0x01 = cghsi 0, 1 +0xe5,0x58,0x00,0x00,0x7f,0xff = cghsi 0, 32767 +0xe5,0x58,0x10,0x00,0x00,0x2a = cghsi 0(%r1), 42 +0xe5,0x58,0xf0,0x00,0x00,0x2a = cghsi 0(%r15), 42 +0xe5,0x58,0x1f,0xff,0x00,0x2a = cghsi 4095(%r1), 42 +0xe5,0x58,0xff,0xff,0x00,0x2a = cghsi 4095(%r15), 42 +0xb9,0x20,0x00,0x00 = cgr %r0, %r0 +0xb9,0x20,0x00,0x0f = cgr %r0, %r15 +0xb9,0x20,0x00,0xf0 = cgr %r15, %r0 +0xb9,0x20,0x00,0x78 = cgr %r7, %r8 +0xb3,0xaa,0x00,0x00 = cgxbr %r0, 0, %f0 +0xb3,0xaa,0x00,0x0d = cgxbr %r0, 0, %f13 +0xb3,0xaa,0xf0,0x00 = cgxbr %r0, 15, %f0 +0xb3,0xaa,0x50,0x48 = cgxbr %r4, 5, %f8 +0xb3,0xaa,0x00,0xf0 = cgxbr %r15, 0, %f0 +0x49,0x00,0x00,0x00 = ch %r0, 0 +0x49,0x00,0x0f,0xff = ch %r0, 4095 +0x49,0x00,0x10,0x00 = ch %r0, 0(%r1) +0x49,0x00,0xf0,0x00 = ch %r0, 0(%r15) +0x49,0x01,0xff,0xff = ch %r0, 4095(%r1, %r15) +0x49,0x0f,0x1f,0xff = ch %r0, 4095(%r15, %r1) +0x49,0xf0,0x00,0x00 = ch %r15, 0 +0xe5,0x54,0x00,0x00,0x00,0x00 = chhsi 0, 0 +0xe5,0x54,0x0f,0xff,0x00,0x00 = chhsi 4095, 0 +0xe5,0x54,0x00,0x00,0x80,0x00 = chhsi 0, -32768 +0xe5,0x54,0x00,0x00,0xff,0xff = chhsi 0, -1 +0xe5,0x54,0x00,0x00,0x00,0x00 = chhsi 0, 0 +0xe5,0x54,0x00,0x00,0x00,0x01 = chhsi 0, 1 +0xe5,0x54,0x00,0x00,0x7f,0xff = chhsi 0, 32767 +0xe5,0x54,0x10,0x00,0x00,0x2a = chhsi 0(%r1), 42 +0xe5,0x54,0xf0,0x00,0x00,0x2a = chhsi 0(%r15), 42 +0xe5,0x54,0x1f,0xff,0x00,0x2a = chhsi 4095(%r1), 42 +0xe5,0x54,0xff,0xff,0x00,0x2a = chhsi 4095(%r15), 42 +0xa7,0x0e,0x80,0x00 = chi %r0, -32768 +0xa7,0x0e,0xff,0xff = chi %r0, -1 +0xa7,0x0e,0x00,0x00 = chi %r0, 0 +0xa7,0x0e,0x00,0x01 = chi %r0, 1 +0xa7,0x0e,0x7f,0xff = chi %r0, 32767 +0xa7,0xfe,0x00,0x00 = chi %r15, 0 +0xe5,0x5c,0x00,0x00,0x00,0x00 = chsi 0, 0 +0xe5,0x5c,0x0f,0xff,0x00,0x00 = chsi 4095, 0 +0xe5,0x5c,0x00,0x00,0x80,0x00 = chsi 0, -32768 +0xe5,0x5c,0x00,0x00,0xff,0xff = chsi 0, -1 +0xe5,0x5c,0x00,0x00,0x00,0x00 = chsi 0, 0 +0xe5,0x5c,0x00,0x00,0x00,0x01 = chsi 0, 1 +0xe5,0x5c,0x00,0x00,0x7f,0xff = chsi 0, 32767 +0xe5,0x5c,0x10,0x00,0x00,0x2a = chsi 0(%r1), 42 +0xe5,0x5c,0xf0,0x00,0x00,0x2a = chsi 0(%r15), 42 +0xe5,0x5c,0x1f,0xff,0x00,0x2a = chsi 4095(%r1), 42 +0xe5,0x5c,0xff,0xff,0x00,0x2a = chsi 4095(%r15), 42 +0xe3,0x00,0x00,0x00,0x80,0x79 = chy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x79 = chy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x79 = chy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x79 = chy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x79 = chy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x79 = chy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x79 = chy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x79 = chy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x79 = chy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x79 = chy %r15, 0 +0x55,0x00,0x00,0x00 = cl %r0, 0 +0x55,0x00,0x0f,0xff = cl %r0, 4095 +0x55,0x00,0x10,0x00 = cl %r0, 0(%r1) +0x55,0x00,0xf0,0x00 = cl %r0, 0(%r15) +0x55,0x01,0xff,0xff = cl %r0, 4095(%r1, %r15) +0x55,0x0f,0x1f,0xff = cl %r0, 4095(%r15, %r1) +0x55,0xf0,0x00,0x00 = cl %r15, 0 +0xd5,0x00,0x00,0x00,0x00,0x00 = clc 0(1), 0 +0xd5,0x00,0x00,0x00,0x10,0x00 = clc 0(1), 0(%r1) +0xd5,0x00,0x00,0x00,0xf0,0x00 = clc 0(1), 0(%r15) +0xd5,0x00,0x00,0x00,0x0f,0xff = clc 0(1), 4095 +0xd5,0x00,0x00,0x00,0x1f,0xff = clc 0(1), 4095(%r1) +0xd5,0x00,0x00,0x00,0xff,0xff = clc 0(1), 4095(%r15) +0xd5,0x00,0x10,0x00,0x00,0x00 = clc 0(1, %r1), 0 +0xd5,0x00,0xf0,0x00,0x00,0x00 = clc 0(1, %r15), 0 +0xd5,0x00,0x1f,0xff,0x00,0x00 = clc 4095(1, %r1), 0 +0xd5,0x00,0xff,0xff,0x00,0x00 = clc 4095(1, %r15), 0 +0xd5,0xff,0x10,0x00,0x00,0x00 = clc 0(256, %r1), 0 +0xd5,0xff,0xf0,0x00,0x00,0x00 = clc 0(256, %r15), 0 +0xe5,0x5d,0x00,0x00,0x00,0x00 = clfhsi 0, 0 +0xe5,0x5d,0x0f,0xff,0x00,0x00 = clfhsi 4095, 0 +0xe5,0x5d,0x00,0x00,0xff,0xff = clfhsi 0, 65535 +0xe5,0x5d,0x10,0x00,0x00,0x2a = clfhsi 0(%r1), 42 +0xe5,0x5d,0xf0,0x00,0x00,0x2a = clfhsi 0(%r15), 42 +0xe5,0x5d,0x1f,0xff,0x00,0x2a = clfhsi 4095(%r1), 42 +0xe5,0x5d,0xff,0xff,0x00,0x2a = clfhsi 4095(%r15), 42 +0xc2,0x0f,0x00,0x00,0x00,0x00 = clfi %r0, 0 +0xc2,0x0f,0xff,0xff,0xff,0xff = clfi %r0, 4294967295 +0xc2,0xff,0x00,0x00,0x00,0x00 = clfi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x21 = clg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x21 = clg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x21 = clg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x21 = clg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x21 = clg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x21 = clg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x21 = clg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x21 = clg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x21 = clg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x21 = clg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x31 = clgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x31 = clgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x31 = clgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x31 = clgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x31 = clgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x31 = clgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x31 = clgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x31 = clgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x31 = clgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x31 = clgf %r15, 0 +0xc2,0x0e,0x00,0x00,0x00,0x00 = clgfi %r0, 0 +0xc2,0x0e,0xff,0xff,0xff,0xff = clgfi %r0, 4294967295 +0xc2,0xfe,0x00,0x00,0x00,0x00 = clgfi %r15, 0 +0xb9,0x31,0x00,0x00 = clgfr %r0, %r0 +0xb9,0x31,0x00,0x0f = clgfr %r0, %r15 +0xb9,0x31,0x00,0xf0 = clgfr %r15, %r0 +0xb9,0x31,0x00,0x78 = clgfr %r7, %r8 +0xb9,0x21,0x00,0x00 = clgr %r0, %r0 +0xb9,0x21,0x00,0x0f = clgr %r0, %r15 +0xb9,0x21,0x00,0xf0 = clgr %r15, %r0 +0xb9,0x21,0x00,0x78 = clgr %r7, %r8 +0xe5,0x55,0x00,0x00,0x00,0x00 = clhhsi 0, 0 +0xe5,0x55,0x0f,0xff,0x00,0x00 = clhhsi 4095, 0 +0xe5,0x55,0x00,0x00,0xff,0xff = clhhsi 0, 65535 +0xe5,0x55,0x10,0x00,0x00,0x2a = clhhsi 0(%r1), 42 +0xe5,0x55,0xf0,0x00,0x00,0x2a = clhhsi 0(%r15), 42 +0xe5,0x55,0x1f,0xff,0x00,0x2a = clhhsi 4095(%r1), 42 +0xe5,0x55,0xff,0xff,0x00,0x2a = clhhsi 4095(%r15), 42 +0x95,0x00,0x00,0x00 = cli 0, 0 +0x95,0x00,0x0f,0xff = cli 4095, 0 +0x95,0xff,0x00,0x00 = cli 0, 255 +0x95,0x2a,0x10,0x00 = cli 0(%r1), 42 +0x95,0x2a,0xf0,0x00 = cli 0(%r15), 42 +0x95,0x2a,0x1f,0xff = cli 4095(%r1), 42 +0x95,0x2a,0xff,0xff = cli 4095(%r15), 42 +0xeb,0x00,0x00,0x00,0x80,0x55 = cliy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x55 = cliy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x55 = cliy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x55 = cliy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x55 = cliy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x55 = cliy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x55 = cliy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x55 = cliy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x55 = cliy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x55 = cliy 524287(%r15), 42 +0x15,0x00 = clr %r0, %r0 +0x15,0x0f = clr %r0, %r15 +0x15,0xf0 = clr %r15, %r0 +0x15,0x78 = clr %r7, %r8 +0xb2,0x5d,0x00,0x00 = clst %r0, %r0 +0xb2,0x5d,0x00,0x0f = clst %r0, %r15 +0xb2,0x5d,0x00,0xf0 = clst %r15, %r0 +0xb2,0x5d,0x00,0x78 = clst %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x55 = cly %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x55 = cly %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x55 = cly %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x55 = cly %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x55 = cly %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x55 = cly %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x55 = cly %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x55 = cly %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x55 = cly %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x55 = cly %r15, 0 +0xb3,0x72,0x00,0x00 = cpsdr %f0, %f0, %f0 +0xb3,0x72,0x00,0x0f = cpsdr %f0, %f0, %f15 +0xb3,0x72,0xf0,0x00 = cpsdr %f0, %f15, %f0 +0xb3,0x72,0x00,0xf0 = cpsdr %f15, %f0, %f0 +0xb3,0x72,0x20,0x13 = cpsdr %f1, %f2, %f3 +0xb3,0x72,0xf0,0xff = cpsdr %f15, %f15, %f15 +0x19,0x00 = cr %r0, %r0 +0x19,0x0f = cr %r0, %r15 +0x19,0xf0 = cr %r15, %r0 +0x19,0x78 = cr %r7, %r8 +0xba,0x00,0x00,0x00 = cs %r0, %r0, 0 +0xba,0x00,0x0f,0xff = cs %r0, %r0, 4095 +0xba,0x00,0x10,0x00 = cs %r0, %r0, 0(%r1) +0xba,0x00,0xf0,0x00 = cs %r0, %r0, 0(%r15) +0xba,0x00,0x1f,0xff = cs %r0, %r0, 4095(%r1) +0xba,0x00,0xff,0xff = cs %r0, %r0, 4095(%r15) +0xba,0x0f,0x00,0x00 = cs %r0, %r15, 0 +0xba,0xf0,0x00,0x00 = cs %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0x30 = csg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x30 = csg %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0x30 = csg %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0x30 = csg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x30 = csg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x30 = csg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x30 = csg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x30 = csg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x30 = csg %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0x30 = csg %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0x30 = csg %r15, %r0, 0 +0xeb,0x00,0x00,0x00,0x80,0x14 = csy %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x14 = csy %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0x14 = csy %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0x14 = csy %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x14 = csy %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x14 = csy %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x14 = csy %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x14 = csy %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x14 = csy %r0, %r0, 524287(%r15) +0xeb,0x0f,0x00,0x00,0x00,0x14 = csy %r0, %r15, 0 +0xeb,0xf0,0x00,0x00,0x00,0x14 = csy %r15, %r0, 0 +0xb3,0x49,0x00,0x00 = cxbr %f0, %f0 +0xb3,0x49,0x00,0x0d = cxbr %f0, %f13 +0xb3,0x49,0x00,0x88 = cxbr %f8, %f8 +0xb3,0x49,0x00,0xd0 = cxbr %f13, %f0 +0xb3,0x96,0x00,0x00 = cxfbr %f0, %r0 +0xb3,0x96,0x00,0x0f = cxfbr %f0, %r15 +0xb3,0x96,0x00,0xd0 = cxfbr %f13, %r0 +0xb3,0x96,0x00,0x87 = cxfbr %f8, %r7 +0xb3,0x96,0x00,0xdf = cxfbr %f13, %r15 +0xb3,0xa6,0x00,0x00 = cxgbr %f0, %r0 +0xb3,0xa6,0x00,0x0f = cxgbr %f0, %r15 +0xb3,0xa6,0x00,0xd0 = cxgbr %f13, %r0 +0xb3,0xa6,0x00,0x87 = cxgbr %f8, %r7 +0xb3,0xa6,0x00,0xdf = cxgbr %f13, %r15 +0xe3,0x00,0x00,0x00,0x80,0x59 = cy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x59 = cy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x59 = cy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x59 = cy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x59 = cy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x59 = cy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x59 = cy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x59 = cy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x59 = cy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x59 = cy %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x1d = ddb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1d = ddb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1d = ddb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1d = ddb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1d = ddb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1d = ddb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1d = ddb %f15, 0 +0xb3,0x1d,0x00,0x00 = ddbr %f0, %f0 +0xb3,0x1d,0x00,0x0f = ddbr %f0, %f15 +0xb3,0x1d,0x00,0x78 = ddbr %f7, %f8 +0xb3,0x1d,0x00,0xf0 = ddbr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x0d = deb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0d = deb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0d = deb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0d = deb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0d = deb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0d = deb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0d = deb %f15, 0 +0xb3,0x0d,0x00,0x00 = debr %f0, %f0 +0xb3,0x0d,0x00,0x0f = debr %f0, %f15 +0xb3,0x0d,0x00,0x78 = debr %f7, %f8 +0xb3,0x0d,0x00,0xf0 = debr %f15, %f0 +0xe3,0x00,0x00,0x00,0x80,0x97 = dl %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x97 = dl %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x97 = dl %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x97 = dl %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x97 = dl %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x97 = dl %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x97 = dl %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x97 = dl %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x97 = dl %r0, 524287(%r15, %r1) +0xe3,0xe0,0x00,0x00,0x00,0x97 = dl %r14, 0 +0xe3,0x00,0x00,0x00,0x80,0x87 = dlg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x87 = dlg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x87 = dlg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x87 = dlg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x87 = dlg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x87 = dlg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x87 = dlg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x87 = dlg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x87 = dlg %r0, 524287(%r15, %r1) +0xe3,0xe0,0x00,0x00,0x00,0x87 = dlg %r14, 0 +0xb9,0x87,0x00,0x00 = dlgr %r0, %r0 +0xb9,0x87,0x00,0x0f = dlgr %r0, %r15 +0xb9,0x87,0x00,0xe0 = dlgr %r14, %r0 +0xb9,0x87,0x00,0x69 = dlgr %r6, %r9 +0xb9,0x97,0x00,0x00 = dlr %r0, %r0 +0xb9,0x97,0x00,0x0f = dlr %r0, %r15 +0xb9,0x97,0x00,0xe0 = dlr %r14, %r0 +0xb9,0x97,0x00,0x69 = dlr %r6, %r9 +0xe3,0x00,0x00,0x00,0x80,0x0d = dsg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x0d = dsg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x0d = dsg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x0d = dsg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x0d = dsg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x0d = dsg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x0d = dsg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x0d = dsg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x0d = dsg %r0, 524287(%r15, %r1) +0xe3,0xe0,0x00,0x00,0x00,0x0d = dsg %r14, 0 +0xe3,0x00,0x00,0x00,0x80,0x1d = dsgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x1d = dsgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x1d = dsgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x1d = dsgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x1d = dsgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x1d = dsgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x1d = dsgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x1d = dsgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x1d = dsgf %r0, 524287(%r15, %r1) +0xe3,0xe0,0x00,0x00,0x00,0x1d = dsgf %r14, 0 +0xb9,0x1d,0x00,0x00 = dsgfr %r0, %r0 +0xb9,0x1d,0x00,0x0f = dsgfr %r0, %r15 +0xb9,0x1d,0x00,0xe0 = dsgfr %r14, %r0 +0xb9,0x1d,0x00,0x69 = dsgfr %r6, %r9 +0xb9,0x0d,0x00,0x00 = dsgr %r0, %r0 +0xb9,0x0d,0x00,0x0f = dsgr %r0, %r15 +0xb9,0x0d,0x00,0xe0 = dsgr %r14, %r0 +0xb9,0x0d,0x00,0x69 = dsgr %r6, %r9 +0xb3,0x4d,0x00,0x00 = dxbr %f0, %f0 +0xb3,0x4d,0x00,0x0d = dxbr %f0, %f13 +0xb3,0x4d,0x00,0x88 = dxbr %f8, %f8 +0xb3,0x4d,0x00,0xd0 = dxbr %f13, %f0 +0xb2,0x4f,0x00,0x00 = ear %r0, %a0 +0xb2,0x4f,0x00,0x0f = ear %r0, %a15 +0xb2,0x4f,0x00,0xf0 = ear %r15, %a0 +0xb2,0x4f,0x00,0x78 = ear %r7, %a8 +0xb2,0x4f,0x00,0xff = ear %r15, %a15 +0xb3,0x5f,0x00,0x00 = fidbr %f0, 0, %f0 +0xb3,0x5f,0x00,0x0f = fidbr %f0, 0, %f15 +0xb3,0x5f,0xf0,0x00 = fidbr %f0, 15, %f0 +0xb3,0x5f,0x50,0x46 = fidbr %f4, 5, %f6 +0xb3,0x5f,0x00,0xf0 = fidbr %f15, 0, %f0 +0xb3,0x57,0x00,0x00 = fiebr %f0, 0, %f0 +0xb3,0x57,0x00,0x0f = fiebr %f0, 0, %f15 +0xb3,0x57,0xf0,0x00 = fiebr %f0, 15, %f0 +0xb3,0x57,0x50,0x46 = fiebr %f4, 5, %f6 +0xb3,0x57,0x00,0xf0 = fiebr %f15, 0, %f0 +0xb3,0x47,0x00,0x00 = fixbr %f0, 0, %f0 +0xb3,0x47,0x00,0x0d = fixbr %f0, 0, %f13 +0xb3,0x47,0xf0,0x00 = fixbr %f0, 15, %f0 +0xb3,0x47,0x50,0x48 = fixbr %f4, 5, %f8 +0xb3,0x47,0x00,0xd0 = fixbr %f13, 0, %f0 +0xb9,0x83,0x00,0x00 = flogr %r0, %r0 +0xb9,0x83,0x00,0x0f = flogr %r0, %r15 +0xb9,0x83,0x00,0xa9 = flogr %r10, %r9 +0xb9,0x83,0x00,0xe0 = flogr %r14, %r0 +0x43,0x00,0x00,0x00 = ic %r0, 0 +0x43,0x00,0x0f,0xff = ic %r0, 4095 +0x43,0x00,0x10,0x00 = ic %r0, 0(%r1) +0x43,0x00,0xf0,0x00 = ic %r0, 0(%r15) +0x43,0x01,0xff,0xff = ic %r0, 4095(%r1, %r15) +0x43,0x0f,0x1f,0xff = ic %r0, 4095(%r15, %r1) +0x43,0xf0,0x00,0x00 = ic %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x73 = icy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x73 = icy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x73 = icy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x73 = icy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x73 = icy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x73 = icy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x73 = icy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x73 = icy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x73 = icy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x73 = icy %r15, 0 +0xc0,0x08,0x00,0x00,0x00,0x00 = iihf %r0, 0 +0xc0,0x08,0xff,0xff,0xff,0xff = iihf %r0, 4294967295 +0xc0,0xf8,0x00,0x00,0x00,0x00 = iihf %r15, 0 +0xa5,0x00,0x00,0x00 = iihh %r0, 0 +0xa5,0x00,0x80,0x00 = iihh %r0, 32768 +0xa5,0x00,0xff,0xff = iihh %r0, 65535 +0xa5,0xf0,0x00,0x00 = iihh %r15, 0 +0xa5,0x01,0x00,0x00 = iihl %r0, 0 +0xa5,0x01,0x80,0x00 = iihl %r0, 32768 +0xa5,0x01,0xff,0xff = iihl %r0, 65535 +0xa5,0xf1,0x00,0x00 = iihl %r15, 0 +0xc0,0x09,0x00,0x00,0x00,0x00 = iilf %r0, 0 +0xc0,0x09,0xff,0xff,0xff,0xff = iilf %r0, 4294967295 +0xc0,0xf9,0x00,0x00,0x00,0x00 = iilf %r15, 0 +0xa5,0x02,0x00,0x00 = iilh %r0, 0 +0xa5,0x02,0x80,0x00 = iilh %r0, 32768 +0xa5,0x02,0xff,0xff = iilh %r0, 65535 +0xa5,0xf2,0x00,0x00 = iilh %r15, 0 +0xa5,0x03,0x00,0x00 = iill %r0, 0 +0xa5,0x03,0x80,0x00 = iill %r0, 32768 +0xa5,0x03,0xff,0xff = iill %r0, 65535 +0xa5,0xf3,0x00,0x00 = iill %r15, 0 +0xb2,0x22,0x00,0x00 = ipm %r0 +0xb2,0x22,0x00,0x10 = ipm %r1 +0xb2,0x22,0x00,0xf0 = ipm %r15 +0x58,0x00,0x00,0x00 = l %r0, 0 +0x58,0x00,0x0f,0xff = l %r0, 4095 +0x58,0x00,0x10,0x00 = l %r0, 0(%r1) +0x58,0x00,0xf0,0x00 = l %r0, 0(%r15) +0x58,0x01,0xff,0xff = l %r0, 4095(%r1, %r15) +0x58,0x0f,0x1f,0xff = l %r0, 4095(%r15, %r1) +0x58,0xf0,0x00,0x00 = l %r15, 0 +0x41,0x00,0x00,0x00 = la %r0, 0 +0x41,0x00,0x0f,0xff = la %r0, 4095 +0x41,0x00,0x10,0x00 = la %r0, 0(%r1) +0x41,0x00,0xf0,0x00 = la %r0, 0(%r15) +0x41,0x01,0xff,0xff = la %r0, 4095(%r1, %r15) +0x41,0x0f,0x1f,0xff = la %r0, 4095(%r15, %r1) +0x41,0xf0,0x00,0x00 = la %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x71 = lay %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x71 = lay %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x71 = lay %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x71 = lay %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x71 = lay %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x71 = lay %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x71 = lay %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x71 = lay %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x71 = lay %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x71 = lay %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x76 = lb %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x76 = lb %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x76 = lb %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x76 = lb %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x76 = lb %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x76 = lb %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x76 = lb %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x76 = lb %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x76 = lb %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x76 = lb %r15, 0 +0xb9,0x26,0x00,0x0f = lbr %r0, %r15 +0xb9,0x26,0x00,0x78 = lbr %r7, %r8 +0xb9,0x26,0x00,0xf0 = lbr %r15, %r0 +0xb3,0x13,0x00,0x09 = lcdbr %f0, %f9 +0xb3,0x13,0x00,0x0f = lcdbr %f0, %f15 +0xb3,0x13,0x00,0xf0 = lcdbr %f15, %f0 +0xb3,0x13,0x00,0xf9 = lcdbr %f15, %f9 +0xb3,0x03,0x00,0x09 = lcebr %f0, %f9 +0xb3,0x03,0x00,0x0f = lcebr %f0, %f15 +0xb3,0x03,0x00,0xf0 = lcebr %f15, %f0 +0xb3,0x03,0x00,0xf9 = lcebr %f15, %f9 +0xb9,0x13,0x00,0x00 = lcgfr %r0, %r0 +0xb9,0x13,0x00,0x0f = lcgfr %r0, %r15 +0xb9,0x13,0x00,0xf0 = lcgfr %r15, %r0 +0xb9,0x13,0x00,0x78 = lcgfr %r7, %r8 +0xb9,0x03,0x00,0x00 = lcgr %r0, %r0 +0xb9,0x03,0x00,0x0f = lcgr %r0, %r15 +0xb9,0x03,0x00,0xf0 = lcgr %r15, %r0 +0xb9,0x03,0x00,0x78 = lcgr %r7, %r8 +0x13,0x00 = lcr %r0, %r0 +0x13,0x0f = lcr %r0, %r15 +0x13,0xf0 = lcr %r15, %r0 +0x13,0x78 = lcr %r7, %r8 +0xb3,0x43,0x00,0x08 = lcxbr %f0, %f8 +0xb3,0x43,0x00,0x0d = lcxbr %f0, %f13 +0xb3,0x43,0x00,0xd0 = lcxbr %f13, %f0 +0xb3,0x43,0x00,0xd9 = lcxbr %f13, %f9 +0x68,0x00,0x00,0x00 = ld %f0, 0 +0x68,0x00,0x0f,0xff = ld %f0, 4095 +0x68,0x00,0x10,0x00 = ld %f0, 0(%r1) +0x68,0x00,0xf0,0x00 = ld %f0, 0(%r15) +0x68,0x01,0xff,0xff = ld %f0, 4095(%r1, %r15) +0x68,0x0f,0x1f,0xff = ld %f0, 4095(%r15, %r1) +0x68,0xf0,0x00,0x00 = ld %f15, 0 +0xed,0x00,0x00,0x00,0x00,0x04 = ldeb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x04 = ldeb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x04 = ldeb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x04 = ldeb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x04 = ldeb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x04 = ldeb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x04 = ldeb %f15, 0 +0xb3,0x04,0x00,0x0f = ldebr %f0, %f15 +0xb3,0x04,0x00,0x78 = ldebr %f7, %f8 +0xb3,0x04,0x00,0xf0 = ldebr %f15, %f0 +0xb3,0xc1,0x00,0x00 = ldgr %f0, %r0 +0xb3,0xc1,0x00,0x0f = ldgr %f0, %r15 +0xb3,0xc1,0x00,0xf0 = ldgr %f15, %r0 +0xb3,0xc1,0x00,0x79 = ldgr %f7, %r9 +0xb3,0xc1,0x00,0xff = ldgr %f15, %r15 +0x28,0x09 = ldr %f0, %f9 +0x28,0x0f = ldr %f0, %f15 +0x28,0xf0 = ldr %f15, %f0 +0x28,0xf9 = ldr %f15, %f9 +0xb3,0x45,0x00,0x00 = ldxbr %f0, %f0 +0xb3,0x45,0x00,0x0d = ldxbr %f0, %f13 +0xb3,0x45,0x00,0x8c = ldxbr %f8, %f12 +0xb3,0x45,0x00,0xd0 = ldxbr %f13, %f0 +0xb3,0x45,0x00,0xdd = ldxbr %f13, %f13 +0xed,0x00,0x00,0x00,0x80,0x65 = ldy %f0, -524288 +0xed,0x00,0x0f,0xff,0xff,0x65 = ldy %f0, -1 +0xed,0x00,0x00,0x00,0x00,0x65 = ldy %f0, 0 +0xed,0x00,0x00,0x01,0x00,0x65 = ldy %f0, 1 +0xed,0x00,0x0f,0xff,0x7f,0x65 = ldy %f0, 524287 +0xed,0x00,0x10,0x00,0x00,0x65 = ldy %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x65 = ldy %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x7f,0x65 = ldy %f0, 524287(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x7f,0x65 = ldy %f0, 524287(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x65 = ldy %f15, 0 +0x78,0x00,0x00,0x00 = le %f0, 0 +0x78,0x00,0x0f,0xff = le %f0, 4095 +0x78,0x00,0x10,0x00 = le %f0, 0(%r1) +0x78,0x00,0xf0,0x00 = le %f0, 0(%r15) +0x78,0x01,0xff,0xff = le %f0, 4095(%r1, %r15) +0x78,0x0f,0x1f,0xff = le %f0, 4095(%r15, %r1) +0x78,0xf0,0x00,0x00 = le %f15, 0 +0xb3,0x44,0x00,0x00 = ledbr %f0, %f0 +0xb3,0x44,0x00,0x0f = ledbr %f0, %f15 +0xb3,0x44,0x00,0x78 = ledbr %f7, %f8 +0xb3,0x44,0x00,0xf0 = ledbr %f15, %f0 +0xb3,0x44,0x00,0xff = ledbr %f15, %f15 +0x38,0x09 = ler %f0, %f9 +0x38,0x0f = ler %f0, %f15 +0x38,0xf0 = ler %f15, %f0 +0x38,0xf9 = ler %f15, %f9 +0xb3,0x46,0x00,0x00 = lexbr %f0, %f0 +0xb3,0x46,0x00,0x0d = lexbr %f0, %f13 +0xb3,0x46,0x00,0x8c = lexbr %f8, %f12 +0xb3,0x46,0x00,0xd0 = lexbr %f13, %f0 +0xb3,0x46,0x00,0xdd = lexbr %f13, %f13 +0xed,0x00,0x00,0x00,0x80,0x64 = ley %f0, -524288 +0xed,0x00,0x0f,0xff,0xff,0x64 = ley %f0, -1 +0xed,0x00,0x00,0x00,0x00,0x64 = ley %f0, 0 +0xed,0x00,0x00,0x01,0x00,0x64 = ley %f0, 1 +0xed,0x00,0x0f,0xff,0x7f,0x64 = ley %f0, 524287 +0xed,0x00,0x10,0x00,0x00,0x64 = ley %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x64 = ley %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x7f,0x64 = ley %f0, 524287(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x7f,0x64 = ley %f0, 524287(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x64 = ley %f15, 0 +0xe3,0x00,0x00,0x00,0x80,0x04 = lg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x04 = lg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x04 = lg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x04 = lg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x04 = lg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x04 = lg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x04 = lg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x04 = lg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x04 = lg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x04 = lg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x77 = lgb %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x77 = lgb %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x77 = lgb %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x77 = lgb %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x77 = lgb %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x77 = lgb %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x77 = lgb %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x77 = lgb %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x77 = lgb %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x77 = lgb %r15, 0 +0xb9,0x06,0x00,0x0f = lgbr %r0, %r15 +0xb9,0x06,0x00,0x78 = lgbr %r7, %r8 +0xb9,0x06,0x00,0xf0 = lgbr %r15, %r0 +0xb3,0xcd,0x00,0x00 = lgdr %r0, %f0 +0xb3,0xcd,0x00,0x0f = lgdr %r0, %f15 +0xb3,0xcd,0x00,0xf0 = lgdr %r15, %f0 +0xb3,0xcd,0x00,0x88 = lgdr %r8, %f8 +0xb3,0xcd,0x00,0xff = lgdr %r15, %f15 +0xe3,0x00,0x00,0x00,0x80,0x14 = lgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x14 = lgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x14 = lgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x14 = lgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x14 = lgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x14 = lgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x14 = lgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x14 = lgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x14 = lgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x14 = lgf %r15, 0 +0xc0,0x01,0x80,0x00,0x00,0x00 = lgfi %r0, -2147483648 +0xc0,0x01,0xff,0xff,0xff,0xff = lgfi %r0, -1 +0xc0,0x01,0x00,0x00,0x00,0x00 = lgfi %r0, 0 +0xc0,0x01,0x00,0x00,0x00,0x01 = lgfi %r0, 1 +0xc0,0x01,0x7f,0xff,0xff,0xff = lgfi %r0, 2147483647 +0xc0,0xf1,0x00,0x00,0x00,0x00 = lgfi %r15, 0 +0xb9,0x14,0x00,0x0f = lgfr %r0, %r15 +0xb9,0x14,0x00,0x78 = lgfr %r7, %r8 +0xb9,0x14,0x00,0xf0 = lgfr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x15 = lgh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x15 = lgh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x15 = lgh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x15 = lgh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x15 = lgh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x15 = lgh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x15 = lgh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x15 = lgh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x15 = lgh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x15 = lgh %r15, 0 +0xa7,0x09,0x80,0x00 = lghi %r0, -32768 +0xa7,0x09,0xff,0xff = lghi %r0, -1 +0xa7,0x09,0x00,0x00 = lghi %r0, 0 +0xa7,0x09,0x00,0x01 = lghi %r0, 1 +0xa7,0x09,0x7f,0xff = lghi %r0, 32767 +0xa7,0xf9,0x00,0x00 = lghi %r15, 0 +0xb9,0x07,0x00,0x0f = lghr %r0, %r15 +0xb9,0x07,0x00,0x78 = lghr %r7, %r8 +0xb9,0x07,0x00,0xf0 = lghr %r15, %r0 +0xb9,0x04,0x00,0x09 = lgr %r0, %r9 +0xb9,0x04,0x00,0x0f = lgr %r0, %r15 +0xb9,0x04,0x00,0xf0 = lgr %r15, %r0 +0xb9,0x04,0x00,0xf9 = lgr %r15, %r9 +0x48,0x00,0x00,0x00 = lh %r0, 0 +0x48,0x00,0x0f,0xff = lh %r0, 4095 +0x48,0x00,0x10,0x00 = lh %r0, 0(%r1) +0x48,0x00,0xf0,0x00 = lh %r0, 0(%r15) +0x48,0x01,0xff,0xff = lh %r0, 4095(%r1, %r15) +0x48,0x0f,0x1f,0xff = lh %r0, 4095(%r15, %r1) +0x48,0xf0,0x00,0x00 = lh %r15, 0 +0xa7,0x08,0x80,0x00 = lhi %r0, -32768 +0xa7,0x08,0xff,0xff = lhi %r0, -1 +0xa7,0x08,0x00,0x00 = lhi %r0, 0 +0xa7,0x08,0x00,0x01 = lhi %r0, 1 +0xa7,0x08,0x7f,0xff = lhi %r0, 32767 +0xa7,0xf8,0x00,0x00 = lhi %r15, 0 +0xb9,0x27,0x00,0x0f = lhr %r0, %r15 +0xb9,0x27,0x00,0x78 = lhr %r7, %r8 +0xb9,0x27,0x00,0xf0 = lhr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x78 = lhy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x78 = lhy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x78 = lhy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x78 = lhy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x78 = lhy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x78 = lhy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x78 = lhy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x78 = lhy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x78 = lhy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x78 = lhy %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x94 = llc %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x94 = llc %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x94 = llc %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x94 = llc %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x94 = llc %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x94 = llc %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x94 = llc %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x94 = llc %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x94 = llc %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x94 = llc %r15, 0 +0xb9,0x94,0x00,0x0f = llcr %r0, %r15 +0xb9,0x94,0x00,0x78 = llcr %r7, %r8 +0xb9,0x94,0x00,0xf0 = llcr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x90 = llgc %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x90 = llgc %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x90 = llgc %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x90 = llgc %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x90 = llgc %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x90 = llgc %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x90 = llgc %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x90 = llgc %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x90 = llgc %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x90 = llgc %r15, 0 +0xb9,0x84,0x00,0x0f = llgcr %r0, %r15 +0xb9,0x84,0x00,0x78 = llgcr %r7, %r8 +0xb9,0x84,0x00,0xf0 = llgcr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x16 = llgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x16 = llgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x16 = llgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x16 = llgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x16 = llgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x16 = llgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x16 = llgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x16 = llgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x16 = llgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x16 = llgf %r15, 0 +0xb9,0x16,0x00,0x0f = llgfr %r0, %r15 +0xb9,0x16,0x00,0x78 = llgfr %r7, %r8 +0xb9,0x16,0x00,0xf0 = llgfr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x91 = llgh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x91 = llgh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x91 = llgh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x91 = llgh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x91 = llgh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x91 = llgh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x91 = llgh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x91 = llgh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x91 = llgh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x91 = llgh %r15, 0 +0xb9,0x85,0x00,0x0f = llghr %r0, %r15 +0xb9,0x85,0x00,0x78 = llghr %r7, %r8 +0xb9,0x85,0x00,0xf0 = llghr %r15, %r0 +0xe3,0x00,0x00,0x00,0x80,0x95 = llh %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x95 = llh %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x95 = llh %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x95 = llh %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x95 = llh %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x95 = llh %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x95 = llh %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x95 = llh %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x95 = llh %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x95 = llh %r15, 0 +0xb9,0x95,0x00,0x0f = llhr %r0, %r15 +0xb9,0x95,0x00,0x78 = llhr %r7, %r8 +0xb9,0x95,0x00,0xf0 = llhr %r15, %r0 +0xc0,0x0e,0x00,0x00,0x00,0x00 = llihf %r0, 0 +0xc0,0x0e,0xff,0xff,0xff,0xff = llihf %r0, 4294967295 +0xc0,0xfe,0x00,0x00,0x00,0x00 = llihf %r15, 0 +0xa5,0x0c,0x00,0x00 = llihh %r0, 0 +0xa5,0x0c,0x80,0x00 = llihh %r0, 32768 +0xa5,0x0c,0xff,0xff = llihh %r0, 65535 +0xa5,0xfc,0x00,0x00 = llihh %r15, 0 +0xa5,0x0d,0x00,0x00 = llihl %r0, 0 +0xa5,0x0d,0x80,0x00 = llihl %r0, 32768 +0xa5,0x0d,0xff,0xff = llihl %r0, 65535 +0xa5,0xfd,0x00,0x00 = llihl %r15, 0 +0xc0,0x0f,0x00,0x00,0x00,0x00 = llilf %r0, 0 +0xc0,0x0f,0xff,0xff,0xff,0xff = llilf %r0, 4294967295 +0xc0,0xff,0x00,0x00,0x00,0x00 = llilf %r15, 0 +0xa5,0x0e,0x00,0x00 = llilh %r0, 0 +0xa5,0x0e,0x80,0x00 = llilh %r0, 32768 +0xa5,0x0e,0xff,0xff = llilh %r0, 65535 +0xa5,0xfe,0x00,0x00 = llilh %r15, 0 +0xa5,0x0f,0x00,0x00 = llill %r0, 0 +0xa5,0x0f,0x80,0x00 = llill %r0, 32768 +0xa5,0x0f,0xff,0xff = llill %r0, 65535 +0xa5,0xff,0x00,0x00 = llill %r15, 0 +0xeb,0x00,0x00,0x00,0x00,0x04 = lmg %r0, %r0, 0 +0xeb,0x0f,0x00,0x00,0x00,0x04 = lmg %r0, %r15, 0 +0xeb,0xef,0x00,0x00,0x00,0x04 = lmg %r14, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x04 = lmg %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x04 = lmg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x04 = lmg %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0x04 = lmg %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0x04 = lmg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x04 = lmg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x04 = lmg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x04 = lmg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x04 = lmg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x04 = lmg %r0, %r0, 524287(%r15) +0xb3,0x11,0x00,0x09 = lndbr %f0, %f9 +0xb3,0x11,0x00,0x0f = lndbr %f0, %f15 +0xb3,0x11,0x00,0xf0 = lndbr %f15, %f0 +0xb3,0x11,0x00,0xf9 = lndbr %f15, %f9 +0xb3,0x01,0x00,0x09 = lnebr %f0, %f9 +0xb3,0x01,0x00,0x0f = lnebr %f0, %f15 +0xb3,0x01,0x00,0xf0 = lnebr %f15, %f0 +0xb3,0x01,0x00,0xf9 = lnebr %f15, %f9 +0xb9,0x11,0x00,0x00 = lngfr %r0, %r0 +0xb9,0x11,0x00,0x0f = lngfr %r0, %r15 +0xb9,0x11,0x00,0xf0 = lngfr %r15, %r0 +0xb9,0x11,0x00,0x78 = lngfr %r7, %r8 +0xb9,0x01,0x00,0x00 = lngr %r0, %r0 +0xb9,0x01,0x00,0x0f = lngr %r0, %r15 +0xb9,0x01,0x00,0xf0 = lngr %r15, %r0 +0xb9,0x01,0x00,0x78 = lngr %r7, %r8 +0x11,0x00 = lnr %r0, %r0 +0x11,0x0f = lnr %r0, %r15 +0x11,0xf0 = lnr %r15, %r0 +0x11,0x78 = lnr %r7, %r8 +0xb3,0x41,0x00,0x08 = lnxbr %f0, %f8 +0xb3,0x41,0x00,0x0d = lnxbr %f0, %f13 +0xb3,0x41,0x00,0xd0 = lnxbr %f13, %f0 +0xb3,0x41,0x00,0xd9 = lnxbr %f13, %f9 +0xb3,0x10,0x00,0x09 = lpdbr %f0, %f9 +0xb3,0x10,0x00,0x0f = lpdbr %f0, %f15 +0xb3,0x10,0x00,0xf0 = lpdbr %f15, %f0 +0xb3,0x10,0x00,0xf9 = lpdbr %f15, %f9 +0xb3,0x00,0x00,0x09 = lpebr %f0, %f9 +0xb3,0x00,0x00,0x0f = lpebr %f0, %f15 +0xb3,0x00,0x00,0xf0 = lpebr %f15, %f0 +0xb3,0x00,0x00,0xf9 = lpebr %f15, %f9 +0xb9,0x10,0x00,0x00 = lpgfr %r0, %r0 +0xb9,0x10,0x00,0x0f = lpgfr %r0, %r15 +0xb9,0x10,0x00,0xf0 = lpgfr %r15, %r0 +0xb9,0x10,0x00,0x78 = lpgfr %r7, %r8 +0xb9,0x00,0x00,0x00 = lpgr %r0, %r0 +0xb9,0x00,0x00,0x0f = lpgr %r0, %r15 +0xb9,0x00,0x00,0xf0 = lpgr %r15, %r0 +0xb9,0x00,0x00,0x78 = lpgr %r7, %r8 +0x10,0x00 = lpr %r0, %r0 +0x10,0x0f = lpr %r0, %r15 +0x10,0xf0 = lpr %r15, %r0 +0x10,0x78 = lpr %r7, %r8 +0xb3,0x40,0x00,0x08 = lpxbr %f0, %f8 +0xb3,0x40,0x00,0x0d = lpxbr %f0, %f13 +0xb3,0x40,0x00,0xd0 = lpxbr %f13, %f0 +0xb3,0x40,0x00,0xd9 = lpxbr %f13, %f9 +0x18,0x09 = lr %r0, %r9 +0x18,0x0f = lr %r0, %r15 +0x18,0xf0 = lr %r15, %r0 +0x18,0xf9 = lr %r15, %r9 +0xe3,0x00,0x00,0x00,0x80,0x1e = lrv %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x1e = lrv %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x1e = lrv %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x1e = lrv %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x1e = lrv %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x1e = lrv %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x1e = lrv %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x1e = lrv %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x1e = lrv %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x1e = lrv %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x0f = lrvg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x0f = lrvg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x0f = lrvg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x0f = lrvg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x0f = lrvg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x0f = lrvg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x0f = lrvg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x0f = lrvg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x0f = lrvg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x0f = lrvg %r15, 0 +0xb9,0x0f,0x00,0x00 = lrvgr %r0, %r0 +0xb9,0x0f,0x00,0x0f = lrvgr %r0, %r15 +0xb9,0x0f,0x00,0xf0 = lrvgr %r15, %r0 +0xb9,0x0f,0x00,0x78 = lrvgr %r7, %r8 +0xb9,0x0f,0x00,0xff = lrvgr %r15, %r15 +0xb9,0x1f,0x00,0x00 = lrvr %r0, %r0 +0xb9,0x1f,0x00,0x0f = lrvr %r0, %r15 +0xb9,0x1f,0x00,0xf0 = lrvr %r15, %r0 +0xb9,0x1f,0x00,0x78 = lrvr %r7, %r8 +0xb9,0x1f,0x00,0xff = lrvr %r15, %r15 +0xe3,0x00,0x00,0x00,0x80,0x12 = lt %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x12 = lt %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x12 = lt %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x12 = lt %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x12 = lt %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x12 = lt %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x12 = lt %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x12 = lt %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x12 = lt %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x12 = lt %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x02 = ltg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x02 = ltg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x02 = ltg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x02 = ltg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x02 = ltg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x02 = ltg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x02 = ltg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x02 = ltg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x02 = ltg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x02 = ltg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x32 = ltgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x32 = ltgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x32 = ltgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x32 = ltgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x32 = ltgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x32 = ltgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x32 = ltgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x32 = ltgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x32 = ltgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x32 = ltgf %r15, 0 +0xb3,0x12,0x00,0x09 = ltdbr %f0, %f9 +0xb3,0x12,0x00,0x0f = ltdbr %f0, %f15 +0xb3,0x12,0x00,0xf0 = ltdbr %f15, %f0 +0xb3,0x12,0x00,0xf9 = ltdbr %f15, %f9 +0xb3,0x02,0x00,0x09 = ltebr %f0, %f9 +0xb3,0x02,0x00,0x0f = ltebr %f0, %f15 +0xb3,0x02,0x00,0xf0 = ltebr %f15, %f0 +0xb3,0x02,0x00,0xf9 = ltebr %f15, %f9 +0xb9,0x12,0x00,0x09 = ltgfr %r0, %r9 +0xb9,0x12,0x00,0x0f = ltgfr %r0, %r15 +0xb9,0x12,0x00,0xf0 = ltgfr %r15, %r0 +0xb9,0x12,0x00,0xf9 = ltgfr %r15, %r9 +0xb9,0x02,0x00,0x09 = ltgr %r0, %r9 +0xb9,0x02,0x00,0x0f = ltgr %r0, %r15 +0xb9,0x02,0x00,0xf0 = ltgr %r15, %r0 +0xb9,0x02,0x00,0xf9 = ltgr %r15, %r9 +0x12,0x09 = ltr %r0, %r9 +0x12,0x0f = ltr %r0, %r15 +0x12,0xf0 = ltr %r15, %r0 +0x12,0xf9 = ltr %r15, %r9 +0xb3,0x42,0x00,0x09 = ltxbr %f0, %f9 +0xb3,0x42,0x00,0x0d = ltxbr %f0, %f13 +0xb3,0x42,0x00,0xd0 = ltxbr %f13, %f0 +0xb3,0x42,0x00,0xd9 = ltxbr %f13, %f9 +0xb3,0x65,0x00,0x08 = lxr %f0, %f8 +0xb3,0x65,0x00,0x0d = lxr %f0, %f13 +0xb3,0x65,0x00,0xd0 = lxr %f13, %f0 +0xb3,0x65,0x00,0xd9 = lxr %f13, %f9 +0xe3,0x00,0x00,0x00,0x80,0x58 = ly %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x58 = ly %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x58 = ly %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x58 = ly %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x58 = ly %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x58 = ly %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x58 = ly %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x58 = ly %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x58 = ly %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x58 = ly %r15, 0 +0xb3,0x75,0x00,0x00 = lzdr %f0 +0xb3,0x75,0x00,0x70 = lzdr %f7 +0xb3,0x75,0x00,0xf0 = lzdr %f15 +0xb3,0x74,0x00,0x00 = lzer %f0 +0xb3,0x74,0x00,0x70 = lzer %f7 +0xb3,0x74,0x00,0xf0 = lzer %f15 +0xb3,0x76,0x00,0x00 = lzxr %f0 +0xb3,0x76,0x00,0x80 = lzxr %f8 +0xb3,0x76,0x00,0xd0 = lzxr %f13 +0xed,0x00,0x00,0x00,0x00,0x1e = madb %f0, %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1e = madb %f0, %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1e = madb %f0, %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1e = madb %f0, %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1e = madb %f0, %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1e = madb %f0, %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1e = madb %f0, %f15, 0 +0xed,0x00,0x00,0x00,0xf0,0x1e = madb %f15, %f0, 0 +0xed,0xf0,0x00,0x00,0xf0,0x1e = madb %f15, %f15, 0 +0xb3,0x1e,0x00,0x00 = madbr %f0, %f0, %f0 +0xb3,0x1e,0x00,0x0f = madbr %f0, %f0, %f15 +0xb3,0x1e,0x00,0xf0 = madbr %f0, %f15, %f0 +0xb3,0x1e,0xf0,0x00 = madbr %f15, %f0, %f0 +0xb3,0x1e,0x70,0x89 = madbr %f7, %f8, %f9 +0xb3,0x1e,0xf0,0xff = madbr %f15, %f15, %f15 +0xed,0x00,0x00,0x00,0x00,0x0e = maeb %f0, %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0e = maeb %f0, %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0e = maeb %f0, %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0e = maeb %f0, %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0e = maeb %f0, %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0e = maeb %f0, %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0e = maeb %f0, %f15, 0 +0xed,0x00,0x00,0x00,0xf0,0x0e = maeb %f15, %f0, 0 +0xed,0xf0,0x00,0x00,0xf0,0x0e = maeb %f15, %f15, 0 +0xb3,0x0e,0x00,0x00 = maebr %f0, %f0, %f0 +0xb3,0x0e,0x00,0x0f = maebr %f0, %f0, %f15 +0xb3,0x0e,0x00,0xf0 = maebr %f0, %f15, %f0 +0xb3,0x0e,0xf0,0x00 = maebr %f15, %f0, %f0 +0xb3,0x0e,0x70,0x89 = maebr %f7, %f8, %f9 +0xb3,0x0e,0xf0,0xff = maebr %f15, %f15, %f15 +0xed,0x00,0x00,0x00,0x00,0x1c = mdb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1c = mdb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1c = mdb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1c = mdb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1c = mdb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1c = mdb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1c = mdb %f15, 0 +0xb3,0x1c,0x00,0x00 = mdbr %f0, %f0 +0xb3,0x1c,0x00,0x0f = mdbr %f0, %f15 +0xb3,0x1c,0x00,0x78 = mdbr %f7, %f8 +0xb3,0x1c,0x00,0xf0 = mdbr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x0c = mdeb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0c = mdeb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0c = mdeb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0c = mdeb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0c = mdeb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0c = mdeb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0c = mdeb %f15, 0 +0xb3,0x0c,0x00,0x00 = mdebr %f0, %f0 +0xb3,0x0c,0x00,0x0f = mdebr %f0, %f15 +0xb3,0x0c,0x00,0x78 = mdebr %f7, %f8 +0xb3,0x0c,0x00,0xf0 = mdebr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x17 = meeb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x17 = meeb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x17 = meeb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x17 = meeb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x17 = meeb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x17 = meeb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x17 = meeb %f15, 0 +0xb3,0x17,0x00,0x00 = meebr %f0, %f0 +0xb3,0x17,0x00,0x0f = meebr %f0, %f15 +0xb3,0x17,0x00,0x78 = meebr %f7, %f8 +0xb3,0x17,0x00,0xf0 = meebr %f15, %f0 +0xa7,0x0d,0x80,0x00 = mghi %r0, -32768 +0xa7,0x0d,0xff,0xff = mghi %r0, -1 +0xa7,0x0d,0x00,0x00 = mghi %r0, 0 +0xa7,0x0d,0x00,0x01 = mghi %r0, 1 +0xa7,0x0d,0x7f,0xff = mghi %r0, 32767 +0xa7,0xfd,0x00,0x00 = mghi %r15, 0 +0x4c,0x00,0x00,0x00 = mh %r0, 0 +0x4c,0x00,0x0f,0xff = mh %r0, 4095 +0x4c,0x00,0x10,0x00 = mh %r0, 0(%r1) +0x4c,0x00,0xf0,0x00 = mh %r0, 0(%r15) +0x4c,0x01,0xff,0xff = mh %r0, 4095(%r1, %r15) +0x4c,0x0f,0x1f,0xff = mh %r0, 4095(%r15, %r1) +0x4c,0xf0,0x00,0x00 = mh %r15, 0 +0xa7,0x0c,0x80,0x00 = mhi %r0, -32768 +0xa7,0x0c,0xff,0xff = mhi %r0, -1 +0xa7,0x0c,0x00,0x00 = mhi %r0, 0 +0xa7,0x0c,0x00,0x01 = mhi %r0, 1 +0xa7,0x0c,0x7f,0xff = mhi %r0, 32767 +0xa7,0xfc,0x00,0x00 = mhi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x7c = mhy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x7c = mhy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x7c = mhy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x7c = mhy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x7c = mhy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x7c = mhy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x7c = mhy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x7c = mhy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x7c = mhy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x7c = mhy %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x86 = mlg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x86 = mlg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x86 = mlg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x86 = mlg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x86 = mlg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x86 = mlg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x86 = mlg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x86 = mlg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x86 = mlg %r0, 524287(%r15, %r1) +0xe3,0xe0,0x00,0x00,0x00,0x86 = mlg %r14, 0 +0xb9,0x86,0x00,0x00 = mlgr %r0, %r0 +0xb9,0x86,0x00,0x0f = mlgr %r0, %r15 +0xb9,0x86,0x00,0xe0 = mlgr %r14, %r0 +0xb9,0x86,0x00,0x69 = mlgr %r6, %r9 +0x71,0x00,0x00,0x00 = ms %r0, 0 +0x71,0x00,0x0f,0xff = ms %r0, 4095 +0x71,0x00,0x10,0x00 = ms %r0, 0(%r1) +0x71,0x00,0xf0,0x00 = ms %r0, 0(%r15) +0x71,0x01,0xff,0xff = ms %r0, 4095(%r1, %r15) +0x71,0x0f,0x1f,0xff = ms %r0, 4095(%r15, %r1) +0x71,0xf0,0x00,0x00 = ms %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x1f = msdb %f0, %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1f = msdb %f0, %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1f = msdb %f0, %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1f = msdb %f0, %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1f = msdb %f0, %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1f = msdb %f0, %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1f = msdb %f0, %f15, 0 +0xed,0x00,0x00,0x00,0xf0,0x1f = msdb %f15, %f0, 0 +0xed,0xf0,0x00,0x00,0xf0,0x1f = msdb %f15, %f15, 0 +0xb3,0x1f,0x00,0x00 = msdbr %f0, %f0, %f0 +0xb3,0x1f,0x00,0x0f = msdbr %f0, %f0, %f15 +0xb3,0x1f,0x00,0xf0 = msdbr %f0, %f15, %f0 +0xb3,0x1f,0xf0,0x00 = msdbr %f15, %f0, %f0 +0xb3,0x1f,0x70,0x89 = msdbr %f7, %f8, %f9 +0xb3,0x1f,0xf0,0xff = msdbr %f15, %f15, %f15 +0xed,0x00,0x00,0x00,0x00,0x0f = mseb %f0, %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0f = mseb %f0, %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0f = mseb %f0, %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0f = mseb %f0, %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0f = mseb %f0, %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0f = mseb %f0, %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0f = mseb %f0, %f15, 0 +0xed,0x00,0x00,0x00,0xf0,0x0f = mseb %f15, %f0, 0 +0xed,0xf0,0x00,0x00,0xf0,0x0f = mseb %f15, %f15, 0 +0xb3,0x0f,0x00,0x00 = msebr %f0, %f0, %f0 +0xb3,0x0f,0x00,0x0f = msebr %f0, %f0, %f15 +0xb3,0x0f,0x00,0xf0 = msebr %f0, %f15, %f0 +0xb3,0x0f,0xf0,0x00 = msebr %f15, %f0, %f0 +0xb3,0x0f,0x70,0x89 = msebr %f7, %f8, %f9 +0xb3,0x0f,0xf0,0xff = msebr %f15, %f15, %f15 +0xc2,0x01,0x80,0x00,0x00,0x00 = msfi %r0, -2147483648 +0xc2,0x01,0xff,0xff,0xff,0xff = msfi %r0, -1 +0xc2,0x01,0x00,0x00,0x00,0x00 = msfi %r0, 0 +0xc2,0x01,0x00,0x00,0x00,0x01 = msfi %r0, 1 +0xc2,0x01,0x7f,0xff,0xff,0xff = msfi %r0, 2147483647 +0xc2,0xf1,0x00,0x00,0x00,0x00 = msfi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x0c = msg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x0c = msg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x0c = msg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x0c = msg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x0c = msg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x0c = msg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x0c = msg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x0c = msg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x0c = msg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x0c = msg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x1c = msgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x1c = msgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x1c = msgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x1c = msgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x1c = msgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x1c = msgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x1c = msgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x1c = msgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x1c = msgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x1c = msgf %r15, 0 +0xc2,0x00,0x80,0x00,0x00,0x00 = msgfi %r0, -2147483648 +0xc2,0x00,0xff,0xff,0xff,0xff = msgfi %r0, -1 +0xc2,0x00,0x00,0x00,0x00,0x00 = msgfi %r0, 0 +0xc2,0x00,0x00,0x00,0x00,0x01 = msgfi %r0, 1 +0xc2,0x00,0x7f,0xff,0xff,0xff = msgfi %r0, 2147483647 +0xc2,0xf0,0x00,0x00,0x00,0x00 = msgfi %r15, 0 +0xb9,0x1c,0x00,0x00 = msgfr %r0, %r0 +0xb9,0x1c,0x00,0x0f = msgfr %r0, %r15 +0xb9,0x1c,0x00,0xf0 = msgfr %r15, %r0 +0xb9,0x1c,0x00,0x78 = msgfr %r7, %r8 +0xb9,0x0c,0x00,0x00 = msgr %r0, %r0 +0xb9,0x0c,0x00,0x0f = msgr %r0, %r15 +0xb9,0x0c,0x00,0xf0 = msgr %r15, %r0 +0xb9,0x0c,0x00,0x78 = msgr %r7, %r8 +0xb2,0x52,0x00,0x00 = msr %r0, %r0 +0xb2,0x52,0x00,0x0f = msr %r0, %r15 +0xb2,0x52,0x00,0xf0 = msr %r15, %r0 +0xb2,0x52,0x00,0x78 = msr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x51 = msy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x51 = msy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x51 = msy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x51 = msy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x51 = msy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x51 = msy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x51 = msy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x51 = msy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x51 = msy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x51 = msy %r15, 0 +0xd2,0x00,0x00,0x00,0x00,0x00 = mvc 0(1), 0 +0xd2,0x00,0x00,0x00,0x10,0x00 = mvc 0(1), 0(%r1) +0xd2,0x00,0x00,0x00,0xf0,0x00 = mvc 0(1), 0(%r15) +0xd2,0x00,0x00,0x00,0x0f,0xff = mvc 0(1), 4095 +0xd2,0x00,0x00,0x00,0x1f,0xff = mvc 0(1), 4095(%r1) +0xd2,0x00,0x00,0x00,0xff,0xff = mvc 0(1), 4095(%r15) +0xd2,0x00,0x10,0x00,0x00,0x00 = mvc 0(1, %r1), 0 +0xd2,0x00,0xf0,0x00,0x00,0x00 = mvc 0(1, %r15), 0 +0xd2,0x00,0x1f,0xff,0x00,0x00 = mvc 4095(1, %r1), 0 +0xd2,0x00,0xff,0xff,0x00,0x00 = mvc 4095(1, %r15), 0 +0xd2,0xff,0x10,0x00,0x00,0x00 = mvc 0(256, %r1), 0 +0xd2,0xff,0xf0,0x00,0x00,0x00 = mvc 0(256, %r15), 0 +0xe5,0x48,0x00,0x00,0x00,0x00 = mvghi 0, 0 +0xe5,0x48,0x0f,0xff,0x00,0x00 = mvghi 4095, 0 +0xe5,0x48,0x00,0x00,0x80,0x00 = mvghi 0, -32768 +0xe5,0x48,0x00,0x00,0xff,0xff = mvghi 0, -1 +0xe5,0x48,0x00,0x00,0x00,0x00 = mvghi 0, 0 +0xe5,0x48,0x00,0x00,0x00,0x01 = mvghi 0, 1 +0xe5,0x48,0x00,0x00,0x7f,0xff = mvghi 0, 32767 +0xe5,0x48,0x10,0x00,0x00,0x2a = mvghi 0(%r1), 42 +0xe5,0x48,0xf0,0x00,0x00,0x2a = mvghi 0(%r15), 42 +0xe5,0x48,0x1f,0xff,0x00,0x2a = mvghi 4095(%r1), 42 +0xe5,0x48,0xff,0xff,0x00,0x2a = mvghi 4095(%r15), 42 +0xe5,0x44,0x00,0x00,0x00,0x00 = mvhhi 0, 0 +0xe5,0x44,0x0f,0xff,0x00,0x00 = mvhhi 4095, 0 +0xe5,0x44,0x00,0x00,0x80,0x00 = mvhhi 0, -32768 +0xe5,0x44,0x00,0x00,0xff,0xff = mvhhi 0, -1 +0xe5,0x44,0x00,0x00,0x00,0x00 = mvhhi 0, 0 +0xe5,0x44,0x00,0x00,0x00,0x01 = mvhhi 0, 1 +0xe5,0x44,0x00,0x00,0x7f,0xff = mvhhi 0, 32767 +0xe5,0x44,0x10,0x00,0x00,0x2a = mvhhi 0(%r1), 42 +0xe5,0x44,0xf0,0x00,0x00,0x2a = mvhhi 0(%r15), 42 +0xe5,0x44,0x1f,0xff,0x00,0x2a = mvhhi 4095(%r1), 42 +0xe5,0x44,0xff,0xff,0x00,0x2a = mvhhi 4095(%r15), 42 +0xe5,0x4c,0x00,0x00,0x00,0x00 = mvhi 0, 0 +0xe5,0x4c,0x0f,0xff,0x00,0x00 = mvhi 4095, 0 +0xe5,0x4c,0x00,0x00,0x80,0x00 = mvhi 0, -32768 +0xe5,0x4c,0x00,0x00,0xff,0xff = mvhi 0, -1 +0xe5,0x4c,0x00,0x00,0x00,0x00 = mvhi 0, 0 +0xe5,0x4c,0x00,0x00,0x00,0x01 = mvhi 0, 1 +0xe5,0x4c,0x00,0x00,0x7f,0xff = mvhi 0, 32767 +0xe5,0x4c,0x10,0x00,0x00,0x2a = mvhi 0(%r1), 42 +0xe5,0x4c,0xf0,0x00,0x00,0x2a = mvhi 0(%r15), 42 +0xe5,0x4c,0x1f,0xff,0x00,0x2a = mvhi 4095(%r1), 42 +0xe5,0x4c,0xff,0xff,0x00,0x2a = mvhi 4095(%r15), 42 +0x92,0x00,0x00,0x00 = mvi 0, 0 +0x92,0x00,0x0f,0xff = mvi 4095, 0 +0x92,0xff,0x00,0x00 = mvi 0, 255 +0x92,0x2a,0x10,0x00 = mvi 0(%r1), 42 +0x92,0x2a,0xf0,0x00 = mvi 0(%r15), 42 +0x92,0x2a,0x1f,0xff = mvi 4095(%r1), 42 +0x92,0x2a,0xff,0xff = mvi 4095(%r15), 42 +0xeb,0x00,0x00,0x00,0x80,0x52 = mviy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x52 = mviy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x52 = mviy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x52 = mviy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x52 = mviy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x52 = mviy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x52 = mviy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x52 = mviy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x52 = mviy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x52 = mviy 524287(%r15), 42 +0xb2,0x55,0x00,0x00 = mvst %r0, %r0 +0xb2,0x55,0x00,0x0f = mvst %r0, %r15 +0xb2,0x55,0x00,0xf0 = mvst %r15, %r0 +0xb2,0x55,0x00,0x78 = mvst %r7, %r8 +0xb3,0x4c,0x00,0x00 = mxbr %f0, %f0 +0xb3,0x4c,0x00,0x0d = mxbr %f0, %f13 +0xb3,0x4c,0x00,0x85 = mxbr %f8, %f5 +0xb3,0x4c,0x00,0xdd = mxbr %f13, %f13 +0xed,0x00,0x00,0x00,0x00,0x07 = mxdb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x07 = mxdb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x07 = mxdb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x07 = mxdb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x07 = mxdb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x07 = mxdb %f0, 4095(%r15, %r1) +0xed,0xd0,0x00,0x00,0x00,0x07 = mxdb %f13, 0 +0xb3,0x07,0x00,0x00 = mxdbr %f0, %f0 +0xb3,0x07,0x00,0x0f = mxdbr %f0, %f15 +0xb3,0x07,0x00,0x88 = mxdbr %f8, %f8 +0xb3,0x07,0x00,0xd0 = mxdbr %f13, %f0 +0x54,0x00,0x00,0x00 = n %r0, 0 +0x54,0x00,0x0f,0xff = n %r0, 4095 +0x54,0x00,0x10,0x00 = n %r0, 0(%r1) +0x54,0x00,0xf0,0x00 = n %r0, 0(%r15) +0x54,0x01,0xff,0xff = n %r0, 4095(%r1, %r15) +0x54,0x0f,0x1f,0xff = n %r0, 4095(%r15, %r1) +0x54,0xf0,0x00,0x00 = n %r15, 0 +0xd4,0x00,0x00,0x00,0x00,0x00 = nc 0(1), 0 +0xd4,0x00,0x00,0x00,0x10,0x00 = nc 0(1), 0(%r1) +0xd4,0x00,0x00,0x00,0xf0,0x00 = nc 0(1), 0(%r15) +0xd4,0x00,0x00,0x00,0x0f,0xff = nc 0(1), 4095 +0xd4,0x00,0x00,0x00,0x1f,0xff = nc 0(1), 4095(%r1) +0xd4,0x00,0x00,0x00,0xff,0xff = nc 0(1), 4095(%r15) +0xd4,0x00,0x10,0x00,0x00,0x00 = nc 0(1, %r1), 0 +0xd4,0x00,0xf0,0x00,0x00,0x00 = nc 0(1, %r15), 0 +0xd4,0x00,0x1f,0xff,0x00,0x00 = nc 4095(1, %r1), 0 +0xd4,0x00,0xff,0xff,0x00,0x00 = nc 4095(1, %r15), 0 +0xd4,0xff,0x10,0x00,0x00,0x00 = nc 0(256, %r1), 0 +0xd4,0xff,0xf0,0x00,0x00,0x00 = nc 0(256, %r15), 0 +0xe3,0x00,0x00,0x00,0x80,0x80 = ng %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x80 = ng %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x80 = ng %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x80 = ng %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x80 = ng %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x80 = ng %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x80 = ng %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x80 = ng %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x80 = ng %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x80 = ng %r15, 0 +0xb9,0x80,0x00,0x00 = ngr %r0, %r0 +0xb9,0x80,0x00,0x0f = ngr %r0, %r15 +0xb9,0x80,0x00,0xf0 = ngr %r15, %r0 +0xb9,0x80,0x00,0x78 = ngr %r7, %r8 +0x94,0x00,0x00,0x00 = ni 0, 0 +0x94,0x00,0x0f,0xff = ni 4095, 0 +0x94,0xff,0x00,0x00 = ni 0, 255 +0x94,0x2a,0x10,0x00 = ni 0(%r1), 42 +0x94,0x2a,0xf0,0x00 = ni 0(%r15), 42 +0x94,0x2a,0x1f,0xff = ni 4095(%r1), 42 +0x94,0x2a,0xff,0xff = ni 4095(%r15), 42 +0xc0,0x0a,0x00,0x00,0x00,0x00 = nihf %r0, 0 +0xc0,0x0a,0xff,0xff,0xff,0xff = nihf %r0, 4294967295 +0xc0,0xfa,0x00,0x00,0x00,0x00 = nihf %r15, 0 +0xa5,0x04,0x00,0x00 = nihh %r0, 0 +0xa5,0x04,0x80,0x00 = nihh %r0, 32768 +0xa5,0x04,0xff,0xff = nihh %r0, 65535 +0xa5,0xf4,0x00,0x00 = nihh %r15, 0 +0xa5,0x05,0x00,0x00 = nihl %r0, 0 +0xa5,0x05,0x80,0x00 = nihl %r0, 32768 +0xa5,0x05,0xff,0xff = nihl %r0, 65535 +0xa5,0xf5,0x00,0x00 = nihl %r15, 0 +0xc0,0x0b,0x00,0x00,0x00,0x00 = nilf %r0, 0 +0xc0,0x0b,0xff,0xff,0xff,0xff = nilf %r0, 4294967295 +0xc0,0xfb,0x00,0x00,0x00,0x00 = nilf %r15, 0 +0xa5,0x06,0x00,0x00 = nilh %r0, 0 +0xa5,0x06,0x80,0x00 = nilh %r0, 32768 +0xa5,0x06,0xff,0xff = nilh %r0, 65535 +0xa5,0xf6,0x00,0x00 = nilh %r15, 0 +0xa5,0x07,0x00,0x00 = nill %r0, 0 +0xa5,0x07,0x80,0x00 = nill %r0, 32768 +0xa5,0x07,0xff,0xff = nill %r0, 65535 +0xa5,0xf7,0x00,0x00 = nill %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x54 = niy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x54 = niy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x54 = niy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x54 = niy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x54 = niy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x54 = niy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x54 = niy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x54 = niy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x54 = niy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x54 = niy 524287(%r15), 42 +0x14,0x00 = nr %r0, %r0 +0x14,0x0f = nr %r0, %r15 +0x14,0xf0 = nr %r15, %r0 +0x14,0x78 = nr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x54 = ny %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x54 = ny %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x54 = ny %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x54 = ny %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x54 = ny %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x54 = ny %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x54 = ny %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x54 = ny %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x54 = ny %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x54 = ny %r15, 0 +0x56,0x00,0x00,0x00 = o %r0, 0 +0x56,0x00,0x0f,0xff = o %r0, 4095 +0x56,0x00,0x10,0x00 = o %r0, 0(%r1) +0x56,0x00,0xf0,0x00 = o %r0, 0(%r15) +0x56,0x01,0xff,0xff = o %r0, 4095(%r1, %r15) +0x56,0x0f,0x1f,0xff = o %r0, 4095(%r15, %r1) +0x56,0xf0,0x00,0x00 = o %r15, 0 +0xd6,0x00,0x00,0x00,0x00,0x00 = oc 0(1), 0 +0xd6,0x00,0x00,0x00,0x10,0x00 = oc 0(1), 0(%r1) +0xd6,0x00,0x00,0x00,0xf0,0x00 = oc 0(1), 0(%r15) +0xd6,0x00,0x00,0x00,0x0f,0xff = oc 0(1), 4095 +0xd6,0x00,0x00,0x00,0x1f,0xff = oc 0(1), 4095(%r1) +0xd6,0x00,0x00,0x00,0xff,0xff = oc 0(1), 4095(%r15) +0xd6,0x00,0x10,0x00,0x00,0x00 = oc 0(1, %r1), 0 +0xd6,0x00,0xf0,0x00,0x00,0x00 = oc 0(1, %r15), 0 +0xd6,0x00,0x1f,0xff,0x00,0x00 = oc 4095(1, %r1), 0 +0xd6,0x00,0xff,0xff,0x00,0x00 = oc 4095(1, %r15), 0 +0xd6,0xff,0x10,0x00,0x00,0x00 = oc 0(256, %r1), 0 +0xd6,0xff,0xf0,0x00,0x00,0x00 = oc 0(256, %r15), 0 +0xe3,0x00,0x00,0x00,0x80,0x81 = og %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x81 = og %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x81 = og %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x81 = og %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x81 = og %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x81 = og %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x81 = og %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x81 = og %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x81 = og %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x81 = og %r15, 0 +0xb9,0x81,0x00,0x00 = ogr %r0, %r0 +0xb9,0x81,0x00,0x0f = ogr %r0, %r15 +0xb9,0x81,0x00,0xf0 = ogr %r15, %r0 +0xb9,0x81,0x00,0x78 = ogr %r7, %r8 +0x96,0x00,0x00,0x00 = oi 0, 0 +0x96,0x00,0x0f,0xff = oi 4095, 0 +0x96,0xff,0x00,0x00 = oi 0, 255 +0x96,0x2a,0x10,0x00 = oi 0(%r1), 42 +0x96,0x2a,0xf0,0x00 = oi 0(%r15), 42 +0x96,0x2a,0x1f,0xff = oi 4095(%r1), 42 +0x96,0x2a,0xff,0xff = oi 4095(%r15), 42 +0xc0,0x0c,0x00,0x00,0x00,0x00 = oihf %r0, 0 +0xc0,0x0c,0xff,0xff,0xff,0xff = oihf %r0, 4294967295 +0xc0,0xfc,0x00,0x00,0x00,0x00 = oihf %r15, 0 +0xa5,0x08,0x00,0x00 = oihh %r0, 0 +0xa5,0x08,0x80,0x00 = oihh %r0, 32768 +0xa5,0x08,0xff,0xff = oihh %r0, 65535 +0xa5,0xf8,0x00,0x00 = oihh %r15, 0 +0xa5,0x09,0x00,0x00 = oihl %r0, 0 +0xa5,0x09,0x80,0x00 = oihl %r0, 32768 +0xa5,0x09,0xff,0xff = oihl %r0, 65535 +0xa5,0xf9,0x00,0x00 = oihl %r15, 0 +0xc0,0x0d,0x00,0x00,0x00,0x00 = oilf %r0, 0 +0xc0,0x0d,0xff,0xff,0xff,0xff = oilf %r0, 4294967295 +0xc0,0xfd,0x00,0x00,0x00,0x00 = oilf %r15, 0 +0xa5,0x0a,0x00,0x00 = oilh %r0, 0 +0xa5,0x0a,0x80,0x00 = oilh %r0, 32768 +0xa5,0x0a,0xff,0xff = oilh %r0, 65535 +0xa5,0xfa,0x00,0x00 = oilh %r15, 0 +0xa5,0x0b,0x00,0x00 = oill %r0, 0 +0xa5,0x0b,0x80,0x00 = oill %r0, 32768 +0xa5,0x0b,0xff,0xff = oill %r0, 65535 +0xa5,0xfb,0x00,0x00 = oill %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x56 = oiy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x56 = oiy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x56 = oiy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x56 = oiy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x56 = oiy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x56 = oiy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x56 = oiy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x56 = oiy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x56 = oiy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x56 = oiy 524287(%r15), 42 +0x16,0x00 = or %r0, %r0 +0x16,0x0f = or %r0, %r15 +0x16,0xf0 = or %r15, %r0 +0x16,0x78 = or %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x56 = oy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x56 = oy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x56 = oy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x56 = oy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x56 = oy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x56 = oy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x56 = oy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x56 = oy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x56 = oy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x56 = oy %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x36 = pfd 0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x36 = pfd 0, -1 +0xe3,0x00,0x00,0x00,0x00,0x36 = pfd 0, 0 +0xe3,0x00,0x00,0x01,0x00,0x36 = pfd 0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x36 = pfd 0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x36 = pfd 0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x36 = pfd 0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x36 = pfd 0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x36 = pfd 0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x36 = pfd 15, 0 +0xec,0x00,0x00,0x00,0x00,0x55 = risbg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x55 = risbg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x55 = risbg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x55 = risbg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x55 = risbg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x55 = risbg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x55 = risbg %r4, %r5, 6, 7, 8 +0xec,0x00,0x00,0x00,0x00,0x54 = rnsbg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x54 = rnsbg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x54 = rnsbg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x54 = rnsbg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x54 = rnsbg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x54 = rnsbg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x54 = rnsbg %r4, %r5, 6, 7, 8 +0xec,0x00,0x00,0x00,0x00,0x56 = rosbg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x56 = rosbg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x56 = rosbg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x56 = rosbg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x56 = rosbg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x56 = rosbg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x56 = rosbg %r4, %r5, 6, 7, 8 +0xec,0x00,0x00,0x00,0x00,0x57 = rxsbg %r0, %r0, 0, 0, 0 +0xec,0x00,0x00,0x00,0x3f,0x57 = rxsbg %r0, %r0, 0, 0, 63 +0xec,0x00,0x00,0xff,0x00,0x57 = rxsbg %r0, %r0, 0, 255, 0 +0xec,0x00,0xff,0x00,0x00,0x57 = rxsbg %r0, %r0, 255, 0, 0 +0xec,0x0f,0x00,0x00,0x00,0x57 = rxsbg %r0, %r15, 0, 0, 0 +0xec,0xf0,0x00,0x00,0x00,0x57 = rxsbg %r15, %r0, 0, 0, 0 +0xec,0x45,0x06,0x07,0x08,0x57 = rxsbg %r4, %r5, 6, 7, 8 +0xeb,0x00,0x00,0x00,0x00,0x1d = rll %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0x1d = rll %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0x1d = rll %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x1d = rll %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x1d = rll %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x1d = rll %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0x1d = rll %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x1d = rll %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x1d = rll %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x1d = rll %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x1d = rll %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x1d = rll %r0, %r0, 524287(%r15) +0xeb,0x00,0x00,0x00,0x00,0x1c = rllg %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0x1c = rllg %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0x1c = rllg %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x1c = rllg %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x1c = rllg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x1c = rllg %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0x1c = rllg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x1c = rllg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x1c = rllg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x1c = rllg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x1c = rllg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x1c = rllg %r0, %r0, 524287(%r15) +0x5b,0x00,0x00,0x00 = s %r0, 0 +0x5b,0x00,0x0f,0xff = s %r0, 4095 +0x5b,0x00,0x10,0x00 = s %r0, 0(%r1) +0x5b,0x00,0xf0,0x00 = s %r0, 0(%r15) +0x5b,0x01,0xff,0xff = s %r0, 4095(%r1, %r15) +0x5b,0x0f,0x1f,0xff = s %r0, 4095(%r15, %r1) +0x5b,0xf0,0x00,0x00 = s %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x1b = sdb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x1b = sdb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x1b = sdb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x1b = sdb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x1b = sdb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x1b = sdb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x1b = sdb %f15, 0 +0xb3,0x1b,0x00,0x00 = sdbr %f0, %f0 +0xb3,0x1b,0x00,0x0f = sdbr %f0, %f15 +0xb3,0x1b,0x00,0x78 = sdbr %f7, %f8 +0xb3,0x1b,0x00,0xf0 = sdbr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x0b = seb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x0b = seb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x0b = seb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x0b = seb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x0b = seb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x0b = seb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x0b = seb %f15, 0 +0xb3,0x0b,0x00,0x00 = sebr %f0, %f0 +0xb3,0x0b,0x00,0x0f = sebr %f0, %f15 +0xb3,0x0b,0x00,0x78 = sebr %f7, %f8 +0xb3,0x0b,0x00,0xf0 = sebr %f15, %f0 +0xe3,0x00,0x00,0x00,0x80,0x09 = sg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x09 = sg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x09 = sg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x09 = sg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x09 = sg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x09 = sg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x09 = sg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x09 = sg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x09 = sg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x09 = sg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x19 = sgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x19 = sgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x19 = sgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x19 = sgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x19 = sgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x19 = sgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x19 = sgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x19 = sgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x19 = sgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x19 = sgf %r15, 0 +0xb9,0x19,0x00,0x00 = sgfr %r0, %r0 +0xb9,0x19,0x00,0x0f = sgfr %r0, %r15 +0xb9,0x19,0x00,0xf0 = sgfr %r15, %r0 +0xb9,0x19,0x00,0x78 = sgfr %r7, %r8 +0xb9,0x09,0x00,0x00 = sgr %r0, %r0 +0xb9,0x09,0x00,0x0f = sgr %r0, %r15 +0xb9,0x09,0x00,0xf0 = sgr %r15, %r0 +0xb9,0x09,0x00,0x78 = sgr %r7, %r8 +0x4b,0x00,0x00,0x00 = sh %r0, 0 +0x4b,0x00,0x0f,0xff = sh %r0, 4095 +0x4b,0x00,0x10,0x00 = sh %r0, 0(%r1) +0x4b,0x00,0xf0,0x00 = sh %r0, 0(%r15) +0x4b,0x01,0xff,0xff = sh %r0, 4095(%r1, %r15) +0x4b,0x0f,0x1f,0xff = sh %r0, 4095(%r15, %r1) +0x4b,0xf0,0x00,0x00 = sh %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x7b = shy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x7b = shy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x7b = shy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x7b = shy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x7b = shy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x7b = shy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x7b = shy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x7b = shy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x7b = shy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x7b = shy %r15, 0 +0x5f,0x00,0x00,0x00 = sl %r0, 0 +0x5f,0x00,0x0f,0xff = sl %r0, 4095 +0x5f,0x00,0x10,0x00 = sl %r0, 0(%r1) +0x5f,0x00,0xf0,0x00 = sl %r0, 0(%r15) +0x5f,0x01,0xff,0xff = sl %r0, 4095(%r1, %r15) +0x5f,0x0f,0x1f,0xff = sl %r0, 4095(%r15, %r1) +0x5f,0xf0,0x00,0x00 = sl %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x99 = slb %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x99 = slb %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x99 = slb %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x99 = slb %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x99 = slb %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x99 = slb %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x99 = slb %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x99 = slb %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x99 = slb %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x99 = slb %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x89 = slbg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x89 = slbg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x89 = slbg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x89 = slbg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x89 = slbg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x89 = slbg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x89 = slbg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x89 = slbg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x89 = slbg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x89 = slbg %r15, 0 +0xb9,0x89,0x00,0x00 = slbgr %r0, %r0 +0xb9,0x89,0x00,0x0f = slbgr %r0, %r15 +0xb9,0x89,0x00,0xf0 = slbgr %r15, %r0 +0xb9,0x89,0x00,0x78 = slbgr %r7, %r8 +0xb9,0x99,0x00,0x00 = slbr %r0, %r0 +0xb9,0x99,0x00,0x0f = slbr %r0, %r15 +0xb9,0x99,0x00,0xf0 = slbr %r15, %r0 +0xb9,0x99,0x00,0x78 = slbr %r7, %r8 +0xc2,0x05,0x00,0x00,0x00,0x00 = slfi %r0, 0 +0xc2,0x05,0xff,0xff,0xff,0xff = slfi %r0, 4294967295 +0xc2,0xf5,0x00,0x00,0x00,0x00 = slfi %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x0b = slg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x0b = slg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x0b = slg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x0b = slg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x0b = slg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x0b = slg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x0b = slg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x0b = slg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x0b = slg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x0b = slg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x1b = slgf %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x1b = slgf %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x1b = slgf %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x1b = slgf %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x1b = slgf %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x1b = slgf %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x1b = slgf %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x1b = slgf %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x1b = slgf %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x1b = slgf %r15, 0 +0xc2,0x04,0x00,0x00,0x00,0x00 = slgfi %r0, 0 +0xc2,0x04,0xff,0xff,0xff,0xff = slgfi %r0, 4294967295 +0xc2,0xf4,0x00,0x00,0x00,0x00 = slgfi %r15, 0 +0xb9,0x1b,0x00,0x00 = slgfr %r0, %r0 +0xb9,0x1b,0x00,0x0f = slgfr %r0, %r15 +0xb9,0x1b,0x00,0xf0 = slgfr %r15, %r0 +0xb9,0x1b,0x00,0x78 = slgfr %r7, %r8 +0xb9,0x0b,0x00,0x00 = slgr %r0, %r0 +0xb9,0x0b,0x00,0x0f = slgr %r0, %r15 +0xb9,0x0b,0x00,0xf0 = slgr %r15, %r0 +0xb9,0x0b,0x00,0x78 = slgr %r7, %r8 +0x89,0x00,0x00,0x00 = sll %r0, 0 +0x89,0x70,0x00,0x00 = sll %r7, 0 +0x89,0xf0,0x00,0x00 = sll %r15, 0 +0x89,0x00,0x0f,0xff = sll %r0, 4095 +0x89,0x00,0x10,0x00 = sll %r0, 0(%r1) +0x89,0x00,0xf0,0x00 = sll %r0, 0(%r15) +0x89,0x00,0x1f,0xff = sll %r0, 4095(%r1) +0x89,0x00,0xff,0xff = sll %r0, 4095(%r15) +0xeb,0x00,0x00,0x00,0x00,0x0d = sllg %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0x0d = sllg %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0x0d = sllg %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x0d = sllg %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x0d = sllg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x0d = sllg %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0x0d = sllg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x0d = sllg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x0d = sllg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x0d = sllg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x0d = sllg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x0d = sllg %r0, %r0, 524287(%r15) +0x1f,0x00 = slr %r0, %r0 +0x1f,0x0f = slr %r0, %r15 +0x1f,0xf0 = slr %r15, %r0 +0x1f,0x78 = slr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x5f = sly %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x5f = sly %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x5f = sly %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x5f = sly %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x5f = sly %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x5f = sly %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x5f = sly %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x5f = sly %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x5f = sly %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x5f = sly %r15, 0 +0xed,0x00,0x00,0x00,0x00,0x15 = sqdb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x15 = sqdb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x15 = sqdb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x15 = sqdb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x15 = sqdb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x15 = sqdb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x15 = sqdb %f15, 0 +0xb3,0x15,0x00,0x00 = sqdbr %f0, %f0 +0xb3,0x15,0x00,0x0f = sqdbr %f0, %f15 +0xb3,0x15,0x00,0x78 = sqdbr %f7, %f8 +0xb3,0x15,0x00,0xf0 = sqdbr %f15, %f0 +0xed,0x00,0x00,0x00,0x00,0x14 = sqeb %f0, 0 +0xed,0x00,0x0f,0xff,0x00,0x14 = sqeb %f0, 4095 +0xed,0x00,0x10,0x00,0x00,0x14 = sqeb %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x14 = sqeb %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x00,0x14 = sqeb %f0, 4095(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x00,0x14 = sqeb %f0, 4095(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x14 = sqeb %f15, 0 +0xb3,0x14,0x00,0x00 = sqebr %f0, %f0 +0xb3,0x14,0x00,0x0f = sqebr %f0, %f15 +0xb3,0x14,0x00,0x78 = sqebr %f7, %f8 +0xb3,0x14,0x00,0xf0 = sqebr %f15, %f0 +0xb3,0x16,0x00,0x00 = sqxbr %f0, %f0 +0xb3,0x16,0x00,0x0d = sqxbr %f0, %f13 +0xb3,0x16,0x00,0x88 = sqxbr %f8, %f8 +0xb3,0x16,0x00,0xd0 = sqxbr %f13, %f0 +0x1b,0x00 = sr %r0, %r0 +0x1b,0x0f = sr %r0, %r15 +0x1b,0xf0 = sr %r15, %r0 +0x1b,0x78 = sr %r7, %r8 +0x8a,0x00,0x00,0x00 = sra %r0, 0 +0x8a,0x70,0x00,0x00 = sra %r7, 0 +0x8a,0xf0,0x00,0x00 = sra %r15, 0 +0x8a,0x00,0x0f,0xff = sra %r0, 4095 +0x8a,0x00,0x10,0x00 = sra %r0, 0(%r1) +0x8a,0x00,0xf0,0x00 = sra %r0, 0(%r15) +0x8a,0x00,0x1f,0xff = sra %r0, 4095(%r1) +0x8a,0x00,0xff,0xff = sra %r0, 4095(%r15) +0xeb,0x00,0x00,0x00,0x00,0x0a = srag %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0x0a = srag %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0x0a = srag %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x0a = srag %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x0a = srag %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x0a = srag %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0x0a = srag %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x0a = srag %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x0a = srag %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x0a = srag %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x0a = srag %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x0a = srag %r0, %r0, 524287(%r15) +0x88,0x00,0x00,0x00 = srl %r0, 0 +0x88,0x70,0x00,0x00 = srl %r7, 0 +0x88,0xf0,0x00,0x00 = srl %r15, 0 +0x88,0x00,0x0f,0xff = srl %r0, 4095 +0x88,0x00,0x10,0x00 = srl %r0, 0(%r1) +0x88,0x00,0xf0,0x00 = srl %r0, 0(%r15) +0x88,0x00,0x1f,0xff = srl %r0, 4095(%r1) +0x88,0x00,0xff,0xff = srl %r0, 4095(%r15) +0xeb,0x00,0x00,0x00,0x00,0x0c = srlg %r0, %r0, 0 +0xeb,0xf1,0x00,0x00,0x00,0x0c = srlg %r15, %r1, 0 +0xeb,0x1f,0x00,0x00,0x00,0x0c = srlg %r1, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x0c = srlg %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x0c = srlg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x0c = srlg %r0, %r0, -1 +0xeb,0x00,0x00,0x01,0x00,0x0c = srlg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x0c = srlg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x0c = srlg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x0c = srlg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x0c = srlg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x0c = srlg %r0, %r0, 524287(%r15) +0xb2,0x5e,0x00,0x00 = srst %r0, %r0 +0xb2,0x5e,0x00,0x0f = srst %r0, %r15 +0xb2,0x5e,0x00,0xf0 = srst %r15, %r0 +0xb2,0x5e,0x00,0x78 = srst %r7, %r8 +0x50,0x00,0x00,0x00 = st %r0, 0 +0x50,0x00,0x0f,0xff = st %r0, 4095 +0x50,0x00,0x10,0x00 = st %r0, 0(%r1) +0x50,0x00,0xf0,0x00 = st %r0, 0(%r15) +0x50,0x01,0xff,0xff = st %r0, 4095(%r1, %r15) +0x50,0x0f,0x1f,0xff = st %r0, 4095(%r15, %r1) +0x50,0xf0,0x00,0x00 = st %r15, 0 +0x42,0x00,0x00,0x00 = stc %r0, 0 +0x42,0x00,0x0f,0xff = stc %r0, 4095 +0x42,0x00,0x10,0x00 = stc %r0, 0(%r1) +0x42,0x00,0xf0,0x00 = stc %r0, 0(%r15) +0x42,0x01,0xff,0xff = stc %r0, 4095(%r1, %r15) +0x42,0x0f,0x1f,0xff = stc %r0, 4095(%r15, %r1) +0x42,0xf0,0x00,0x00 = stc %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x72 = stcy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x72 = stcy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x72 = stcy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x72 = stcy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x72 = stcy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x72 = stcy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x72 = stcy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x72 = stcy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x72 = stcy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x72 = stcy %r15, 0 +0x60,0x00,0x00,0x00 = std %f0, 0 +0x60,0x00,0x0f,0xff = std %f0, 4095 +0x60,0x00,0x10,0x00 = std %f0, 0(%r1) +0x60,0x00,0xf0,0x00 = std %f0, 0(%r15) +0x60,0x01,0xff,0xff = std %f0, 4095(%r1, %r15) +0x60,0x0f,0x1f,0xff = std %f0, 4095(%r15, %r1) +0x60,0xf0,0x00,0x00 = std %f15, 0 +0xed,0x00,0x00,0x00,0x80,0x67 = stdy %f0, -524288 +0xed,0x00,0x0f,0xff,0xff,0x67 = stdy %f0, -1 +0xed,0x00,0x00,0x00,0x00,0x67 = stdy %f0, 0 +0xed,0x00,0x00,0x01,0x00,0x67 = stdy %f0, 1 +0xed,0x00,0x0f,0xff,0x7f,0x67 = stdy %f0, 524287 +0xed,0x00,0x10,0x00,0x00,0x67 = stdy %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x67 = stdy %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x7f,0x67 = stdy %f0, 524287(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x7f,0x67 = stdy %f0, 524287(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x67 = stdy %f15, 0 +0x70,0x00,0x00,0x00 = ste %f0, 0 +0x70,0x00,0x0f,0xff = ste %f0, 4095 +0x70,0x00,0x10,0x00 = ste %f0, 0(%r1) +0x70,0x00,0xf0,0x00 = ste %f0, 0(%r15) +0x70,0x01,0xff,0xff = ste %f0, 4095(%r1, %r15) +0x70,0x0f,0x1f,0xff = ste %f0, 4095(%r15, %r1) +0x70,0xf0,0x00,0x00 = ste %f15, 0 +0xed,0x00,0x00,0x00,0x80,0x66 = stey %f0, -524288 +0xed,0x00,0x0f,0xff,0xff,0x66 = stey %f0, -1 +0xed,0x00,0x00,0x00,0x00,0x66 = stey %f0, 0 +0xed,0x00,0x00,0x01,0x00,0x66 = stey %f0, 1 +0xed,0x00,0x0f,0xff,0x7f,0x66 = stey %f0, 524287 +0xed,0x00,0x10,0x00,0x00,0x66 = stey %f0, 0(%r1) +0xed,0x00,0xf0,0x00,0x00,0x66 = stey %f0, 0(%r15) +0xed,0x01,0xff,0xff,0x7f,0x66 = stey %f0, 524287(%r1, %r15) +0xed,0x0f,0x1f,0xff,0x7f,0x66 = stey %f0, 524287(%r15, %r1) +0xed,0xf0,0x00,0x00,0x00,0x66 = stey %f15, 0 +0xe3,0x00,0x00,0x00,0x80,0x24 = stg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x24 = stg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x24 = stg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x24 = stg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x24 = stg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x24 = stg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x24 = stg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x24 = stg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x24 = stg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x24 = stg %r15, 0 +0x40,0x00,0x00,0x00 = sth %r0, 0 +0x40,0x00,0x0f,0xff = sth %r0, 4095 +0x40,0x00,0x10,0x00 = sth %r0, 0(%r1) +0x40,0x00,0xf0,0x00 = sth %r0, 0(%r15) +0x40,0x01,0xff,0xff = sth %r0, 4095(%r1, %r15) +0x40,0x0f,0x1f,0xff = sth %r0, 4095(%r15, %r1) +0x40,0xf0,0x00,0x00 = sth %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x70 = sthy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x70 = sthy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x70 = sthy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x70 = sthy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x70 = sthy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x70 = sthy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x70 = sthy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x70 = sthy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x70 = sthy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x70 = sthy %r15, 0 +0xeb,0x00,0x00,0x00,0x00,0x24 = stmg %r0, %r0, 0 +0xeb,0x0f,0x00,0x00,0x00,0x24 = stmg %r0, %r15, 0 +0xeb,0xef,0x00,0x00,0x00,0x24 = stmg %r14, %r15, 0 +0xeb,0xff,0x00,0x00,0x00,0x24 = stmg %r15, %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x24 = stmg %r0, %r0, -524288 +0xeb,0x00,0x0f,0xff,0xff,0x24 = stmg %r0, %r0, -1 +0xeb,0x00,0x00,0x00,0x00,0x24 = stmg %r0, %r0, 0 +0xeb,0x00,0x00,0x01,0x00,0x24 = stmg %r0, %r0, 1 +0xeb,0x00,0x0f,0xff,0x7f,0x24 = stmg %r0, %r0, 524287 +0xeb,0x00,0x10,0x00,0x00,0x24 = stmg %r0, %r0, 0(%r1) +0xeb,0x00,0xf0,0x00,0x00,0x24 = stmg %r0, %r0, 0(%r15) +0xeb,0x00,0x1f,0xff,0x7f,0x24 = stmg %r0, %r0, 524287(%r1) +0xeb,0x00,0xff,0xff,0x7f,0x24 = stmg %r0, %r0, 524287(%r15) +0xe3,0x00,0x00,0x00,0x80,0x3e = strv %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x3e = strv %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x3e = strv %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x3e = strv %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x3e = strv %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x3e = strv %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x3e = strv %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x3e = strv %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x3e = strv %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x3e = strv %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x2f = strvg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x2f = strvg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x2f = strvg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x2f = strvg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x2f = strvg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x2f = strvg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x2f = strvg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x2f = strvg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x2f = strvg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x2f = strvg %r15, 0 +0xe3,0x00,0x00,0x00,0x80,0x50 = sty %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x50 = sty %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x50 = sty %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x50 = sty %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x50 = sty %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x50 = sty %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x50 = sty %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x50 = sty %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x50 = sty %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x50 = sty %r15, 0 +0xb3,0x4b,0x00,0x00 = sxbr %f0, %f0 +0xb3,0x4b,0x00,0x0d = sxbr %f0, %f13 +0xb3,0x4b,0x00,0x88 = sxbr %f8, %f8 +0xb3,0x4b,0x00,0xd0 = sxbr %f13, %f0 +0xe3,0x00,0x00,0x00,0x80,0x5b = sy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x5b = sy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x5b = sy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x5b = sy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x5b = sy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x5b = sy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x5b = sy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x5b = sy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x5b = sy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x5b = sy %r15, 0 +0x91,0x00,0x00,0x00 = tm 0, 0 +0x91,0x00,0x0f,0xff = tm 4095, 0 +0x91,0xff,0x00,0x00 = tm 0, 255 +0x91,0x2a,0x10,0x00 = tm 0(%r1), 42 +0x91,0x2a,0xf0,0x00 = tm 0(%r15), 42 +0x91,0x2a,0x1f,0xff = tm 4095(%r1), 42 +0x91,0x2a,0xff,0xff = tm 4095(%r15), 42 +0xa7,0x02,0x00,0x00 = tmhh %r0, 0 +0xa7,0x02,0x80,0x00 = tmhh %r0, 32768 +0xa7,0x02,0xff,0xff = tmhh %r0, 65535 +0xa7,0xf2,0x00,0x00 = tmhh %r15, 0 +0xa7,0x03,0x00,0x00 = tmhl %r0, 0 +0xa7,0x03,0x80,0x00 = tmhl %r0, 32768 +0xa7,0x03,0xff,0xff = tmhl %r0, 65535 +0xa7,0xf3,0x00,0x00 = tmhl %r15, 0 +0xa7,0x00,0x00,0x00 = tmlh %r0, 0 +0xa7,0x00,0x80,0x00 = tmlh %r0, 32768 +0xa7,0x00,0xff,0xff = tmlh %r0, 65535 +0xa7,0xf0,0x00,0x00 = tmlh %r15, 0 +0xa7,0x01,0x00,0x00 = tmll %r0, 0 +0xa7,0x01,0x80,0x00 = tmll %r0, 32768 +0xa7,0x01,0xff,0xff = tmll %r0, 65535 +0xa7,0xf1,0x00,0x00 = tmll %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x51 = tmy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x51 = tmy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x51 = tmy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x51 = tmy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x51 = tmy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x51 = tmy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x51 = tmy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x51 = tmy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x51 = tmy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x51 = tmy 524287(%r15), 42 +0x57,0x00,0x00,0x00 = x %r0, 0 +0x57,0x00,0x0f,0xff = x %r0, 4095 +0x57,0x00,0x10,0x00 = x %r0, 0(%r1) +0x57,0x00,0xf0,0x00 = x %r0, 0(%r15) +0x57,0x01,0xff,0xff = x %r0, 4095(%r1, %r15) +0x57,0x0f,0x1f,0xff = x %r0, 4095(%r15, %r1) +0x57,0xf0,0x00,0x00 = x %r15, 0 +0xd7,0x00,0x00,0x00,0x00,0x00 = xc 0(1), 0 +0xd7,0x00,0x00,0x00,0x10,0x00 = xc 0(1), 0(%r1) +0xd7,0x00,0x00,0x00,0xf0,0x00 = xc 0(1), 0(%r15) +0xd7,0x00,0x00,0x00,0x0f,0xff = xc 0(1), 4095 +0xd7,0x00,0x00,0x00,0x1f,0xff = xc 0(1), 4095(%r1) +0xd7,0x00,0x00,0x00,0xff,0xff = xc 0(1), 4095(%r15) +0xd7,0x00,0x10,0x00,0x00,0x00 = xc 0(1, %r1), 0 +0xd7,0x00,0xf0,0x00,0x00,0x00 = xc 0(1, %r15), 0 +0xd7,0x00,0x1f,0xff,0x00,0x00 = xc 4095(1, %r1), 0 +0xd7,0x00,0xff,0xff,0x00,0x00 = xc 4095(1, %r15), 0 +0xd7,0xff,0x10,0x00,0x00,0x00 = xc 0(256, %r1), 0 +0xd7,0xff,0xf0,0x00,0x00,0x00 = xc 0(256, %r15), 0 +0xe3,0x00,0x00,0x00,0x80,0x82 = xg %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x82 = xg %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x82 = xg %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x82 = xg %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x82 = xg %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x82 = xg %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x82 = xg %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x82 = xg %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x82 = xg %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x82 = xg %r15, 0 +0xb9,0x82,0x00,0x00 = xgr %r0, %r0 +0xb9,0x82,0x00,0x0f = xgr %r0, %r15 +0xb9,0x82,0x00,0xf0 = xgr %r15, %r0 +0xb9,0x82,0x00,0x78 = xgr %r7, %r8 +0x97,0x00,0x00,0x00 = xi 0, 0 +0x97,0x00,0x0f,0xff = xi 4095, 0 +0x97,0xff,0x00,0x00 = xi 0, 255 +0x97,0x2a,0x10,0x00 = xi 0(%r1), 42 +0x97,0x2a,0xf0,0x00 = xi 0(%r15), 42 +0x97,0x2a,0x1f,0xff = xi 4095(%r1), 42 +0x97,0x2a,0xff,0xff = xi 4095(%r15), 42 +0xc0,0x06,0x00,0x00,0x00,0x00 = xihf %r0, 0 +0xc0,0x06,0xff,0xff,0xff,0xff = xihf %r0, 4294967295 +0xc0,0xf6,0x00,0x00,0x00,0x00 = xihf %r15, 0 +0xc0,0x07,0x00,0x00,0x00,0x00 = xilf %r0, 0 +0xc0,0x07,0xff,0xff,0xff,0xff = xilf %r0, 4294967295 +0xc0,0xf7,0x00,0x00,0x00,0x00 = xilf %r15, 0 +0xeb,0x00,0x00,0x00,0x80,0x57 = xiy -524288, 0 +0xeb,0x00,0x0f,0xff,0xff,0x57 = xiy -1, 0 +0xeb,0x00,0x00,0x00,0x00,0x57 = xiy 0, 0 +0xeb,0x00,0x00,0x01,0x00,0x57 = xiy 1, 0 +0xeb,0x00,0x0f,0xff,0x7f,0x57 = xiy 524287, 0 +0xeb,0xff,0x00,0x00,0x00,0x57 = xiy 0, 255 +0xeb,0x2a,0x10,0x00,0x00,0x57 = xiy 0(%r1), 42 +0xeb,0x2a,0xf0,0x00,0x00,0x57 = xiy 0(%r15), 42 +0xeb,0x2a,0x1f,0xff,0x7f,0x57 = xiy 524287(%r1), 42 +0xeb,0x2a,0xff,0xff,0x7f,0x57 = xiy 524287(%r15), 42 +0x17,0x00 = xr %r0, %r0 +0x17,0x0f = xr %r0, %r15 +0x17,0xf0 = xr %r15, %r0 +0x17,0x78 = xr %r7, %r8 +0xe3,0x00,0x00,0x00,0x80,0x57 = xy %r0, -524288 +0xe3,0x00,0x0f,0xff,0xff,0x57 = xy %r0, -1 +0xe3,0x00,0x00,0x00,0x00,0x57 = xy %r0, 0 +0xe3,0x00,0x00,0x01,0x00,0x57 = xy %r0, 1 +0xe3,0x00,0x0f,0xff,0x7f,0x57 = xy %r0, 524287 +0xe3,0x00,0x10,0x00,0x00,0x57 = xy %r0, 0(%r1) +0xe3,0x00,0xf0,0x00,0x00,0x57 = xy %r0, 0(%r15) +0xe3,0x01,0xff,0xff,0x7f,0x57 = xy %r0, 524287(%r1, %r15) +0xe3,0x0f,0x1f,0xff,0x7f,0x57 = xy %r0, 524287(%r15, %r1) +0xe3,0xf0,0x00,0x00,0x00,0x57 = xy %r15, 0 diff --git a/white_patch_detect/capstone-master/suite/MC/SystemZ/regs-good.s.cs b/white_patch_detect/capstone-master/suite/MC/SystemZ/regs-good.s.cs new file mode 100644 index 0000000..9ffbaf0 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/MC/SystemZ/regs-good.s.cs @@ -0,0 +1,45 @@ +# CS_ARCH_SYSZ, 0, None +0x18,0x01 = lr %r0, %r1 +0x18,0x23 = lr %r2, %r3 +0x18,0x45 = lr %r4, %r5 +0x18,0x67 = lr %r6, %r7 +0x18,0x89 = lr %r8, %r9 +0x18,0xab = lr %r10, %r11 +0x18,0xcd = lr %r12, %r13 +0x18,0xef = lr %r14, %r15 +0xb9,0x04,0x00,0x01 = lgr %r0, %r1 +0xb9,0x04,0x00,0x23 = lgr %r2, %r3 +0xb9,0x04,0x00,0x45 = lgr %r4, %r5 +0xb9,0x04,0x00,0x67 = lgr %r6, %r7 +0xb9,0x04,0x00,0x89 = lgr %r8, %r9 +0xb9,0x04,0x00,0xab = lgr %r10, %r11 +0xb9,0x04,0x00,0xcd = lgr %r12, %r13 +0xb9,0x04,0x00,0xef = lgr %r14, %r15 +0xb9,0x97,0x00,0x00 = dlr %r0, %r0 +0xb9,0x97,0x00,0x20 = dlr %r2, %r0 +0xb9,0x97,0x00,0x40 = dlr %r4, %r0 +0xb9,0x97,0x00,0x60 = dlr %r6, %r0 +0xb9,0x97,0x00,0x80 = dlr %r8, %r0 +0xb9,0x97,0x00,0xa0 = dlr %r10, %r0 +0xb9,0x97,0x00,0xc0 = dlr %r12, %r0 +0xb9,0x97,0x00,0xe0 = dlr %r14, %r0 +0x38,0x01 = ler %f0, %f1 +0x38,0x23 = ler %f2, %f3 +0x38,0x45 = ler %f4, %f5 +0x38,0x67 = ler %f6, %f7 +0x38,0x89 = ler %f8, %f9 +0x38,0xab = ler %f10, %f11 +0x38,0xcd = ler %f12, %f13 +0x38,0xef = ler %f14, %f15 +0x28,0x01 = ldr %f0, %f1 +0x28,0x23 = ldr %f2, %f3 +0x28,0x45 = ldr %f4, %f5 +0x28,0x67 = ldr %f6, %f7 +0x28,0x89 = ldr %f8, %f9 +0x28,0xab = ldr %f10, %f11 +0x28,0xcd = ldr %f12, %f13 +0x28,0xef = ldr %f14, %f15 +0xb3,0x65,0x00,0x01 = lxr %f0, %f1 +0xb3,0x65,0x00,0x45 = lxr %f4, %f5 +0xb3,0x65,0x00,0x89 = lxr %f8, %f9 +0xb3,0x65,0x00,0xcd = lxr %f12, %f13 diff --git a/white_patch_detect/capstone-master/suite/README b/white_patch_detect/capstone-master/suite/README new file mode 100644 index 0000000..fc9b59a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/README @@ -0,0 +1,35 @@ +This directory contains some tools used by developers of Capstone project. +Average users should ignore all the contents here. + + +- arm/ + Test some ARM's special input. + +- MC/ + Input used to test various architectures & modes. + +- benchmark.py + This script benchmarks Python binding by disassembling some random code. + +- test_*.sh + Run all the tests and send the output to external file to be compared later. + This is useful when we want to verify if a commit (wrongly) changes + the disassemble result. + +- compile_all.sh + Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) & + report the result as pass or fail. + +- fuzz.py + This simple script disassembles random code for all archs (or selected arch) + in order to find segfaults. + +- test_mc.sh + This script compares the output of Capstone with LLVM's llvm-mc with the + input coming from MC/. This relies on test_mc.py to do all the hard works. + +- x86odd.py + Test some tricky X86 instructions. + +- ppcbranch.py + Test some tricky branch PPC instructions. diff --git a/white_patch_detect/capstone-master/suite/autogen_x86imm.py b/white_patch_detect/capstone-master/suite/autogen_x86imm.py new file mode 100644 index 0000000..1e6fb67 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/autogen_x86imm.py @@ -0,0 +1,90 @@ +#!/usr/bin/python +# By Nguyen Anh Quynh, 2015 +# This tool extract sizes of immediadte operands from X86 instruction names. +# Syntax: ./autogen_x86imm.py + +# Gather immediate sizes to put into X86ImmSize.inc +OUTPUT = "../arch/X86/X86ImmSize.inc" + +f = open("../arch/X86/X86GenInstrInfo.inc") +f2 = open(OUTPUT, "w") +for line in f.readlines(): + tmp = line.strip().split("=") + if len(tmp) == 2: # X86_xxx = nnn, + name = tmp[0].strip() + if name == "X86_INSTRUCTION_LIST_END": # no more instructions + break + if name.endswith("_DB"): # pseudo instruction + continue + if "_LOCK_" in name or "BEXTR" in name: # exception + continue + if name.startswith("X86_"): # instruction + if name.endswith("16mi8"): + f2.write("{2, %s},\n" %name) + elif name.endswith("16ri8"): + f2.write("{2, %s},\n" %name) + elif name.endswith("32ri8"): + f2.write("{4, %s},\n" %name) + elif name.endswith("32mi8"): + f2.write("{4, %s},\n" %name) + elif name.endswith("64i32"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64mi32"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64ri32"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64ri8"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64mi8"): + f2.write("{8, %s},\n" %name) + elif name.endswith("16rmi8"): + f2.write("{2, %s},\n" %name) + elif name.endswith("32rmi8"): + f2.write("{4, %s},\n" %name) + elif name.endswith("16rri8"): + f2.write("{2, %s},\n" %name) + elif name.endswith("32rri8"): + f2.write("{4, %s},\n" %name) + elif name.endswith("64rmi8"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64rmi32"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64rri32"): + f2.write("{8, %s},\n" %name) + elif name.endswith("64rri8"): + f2.write("{8, %s},\n" %name) + elif name.endswith("32ri64"): # special case + f2.write("{8, %s},\n" %name) + elif name.endswith("16i8"): # special case + f2.write("{2, %s},\n" %name) + elif name.endswith("32i8"): # special case + f2.write("{4, %s},\n" %name) + elif name.endswith("64i16"): # special case + f2.write("{8, %s},\n" %name) + elif name.endswith("64i8"): # special case + f2.write("{8, %s},\n" %name) + + elif name.endswith("i8") or "i8_" in name: + f2.write("{1, %s},\n" %name) + elif "8ri" in name or "8mi" in name: + f2.write("{1, %s},\n" %name) + + elif name.endswith("i16") or "i16_" in name: + f2.write("{2, %s},\n" %name) + elif "16ri" in name or "16mi" in name: + f2.write("{2, %s},\n" %name) + + elif name.endswith("i32") or "i32_" in name: + f2.write("{4, %s},\n" %name) + elif "32ri" in name or "32mi" in name: + f2.write("{4, %s},\n" %name) + + elif name.endswith("i64") or "i64_" in name: + f2.write("{8, %s},\n" %name) + elif "64ri" in name or "64mi" in name: + f2.write("{8, %s},\n" %name) + +f.close() +f2.close() + +print("Generated %s" %OUTPUT) diff --git a/white_patch_detect/capstone-master/suite/benchmark.py b/white_patch_detect/capstone-master/suite/benchmark.py new file mode 100644 index 0000000..62262a3 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/benchmark.py @@ -0,0 +1,128 @@ +#!/usr/bin/python + +# Simple benchmark for Capstone by disassembling random code. By Nguyen Anh Quynh, 2014 +# Syntax: +# ./suite/benchmark.py --> Benchmark all archs +# ./suite/benchmark.py x86 --> Benchmark all X86 (all 16bit, 32bit, 64bit) +# ./suite/benchmark.py x86-32 --> Benchmark X86-32 arch only +# ./suite/benchmark.py arm --> Benchmark all ARM (arm, thumb) +# ./suite/benchmark.py aarch64 --> Benchmark ARM-64 +# ./suite/benchmark.py mips --> Benchmark all Mips (32bit, 64bit) +# ./suite/benchmark.py ppc --> Benchmark PPC + +from capstone import * + +from time import time +from random import randint +import sys + + +# file providing code to disassemble +FILE = '/usr/bin/python' + + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, "X86-16 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0), + (CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0), + (CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0), + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0), + (CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0), + (CS_ARCH_SYSZ, 0, "SystemZ", 0), + (CS_ARCH_XCORE, 0, "XCore", 0), + (CS_ARCH_M68K, 0, "M68K", 0), + ) + + +# for debugging +def to_hex(s): + return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK + +def get_code(f, size): + code = f.read(size) + if len(code) != size: # reached end-of-file? + # then reset file position to begin-of-file + f.seek(0) + code = f.read(size) + + return code + + +def cs(md, code): + insns = md.disasm(code, 0) + # uncomment below line to speed up this function 200 times! + # return + for i in insns: + if i.address == 0x100000: + print i + + +def cs_lite(md, code): + insns = md.disasm_lite(code, 0) + for (addr, size, mnem, ops) in insns: + if addr == 0x100000: + print i + + +cfile = open(FILE) + +for (arch, mode, comment, syntax) in all_tests: + try: + request = sys.argv[1] + if not request in comment.lower(): + continue + except: + pass + + print("Platform: %s" %comment) + + try: + md = Cs(arch, mode) + #md.detail = True + + if syntax != 0: + md.syntax = syntax + + # warm up few times + cfile.seek(0) + for i in xrange(3): + code = get_code(cfile, 128) + #print to_hex(code) + #print + cs(md, code) + + # start real benchmark + c_t = 0 + for i in xrange(50000): + code = get_code(cfile, 128) + #print to_hex(code) + #print + + t1 = time() + cs(md, code) + c_t += time() - t1 + + print "Benchmark - full obj:", c_t, "seconds" + print + + cfile.seek(0) + c_t = 0 + for i in xrange(50000): + code = get_code(cfile, 128) + #print to_hex(code) + #print + + t1 = time() + cs_lite(md, code) + c_t += time() - t1 + + print "Benchmark - lite:", c_t, "seconds" + print + except CsError as e: + print("ERROR: %s" %e) diff --git a/white_patch_detect/capstone-master/suite/benchmark/Makefile b/white_patch_detect/capstone-master/suite/benchmark/Makefile new file mode 100644 index 0000000..b336899 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/benchmark/Makefile @@ -0,0 +1,12 @@ +# Sample Makefile for Capstone Disassembly Engine + +LIBNAME = capstone + +test_iter_benchmark: test_iter_benchmark.o + ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ + +%.o: %.c + ${CC} -c -I../../include $< -o $@ + +clean: + rm -rf *.o test_iter_benchmark diff --git a/white_patch_detect/capstone-master/suite/benchmark/test_iter_benchmark.c b/white_patch_detect/capstone-master/suite/benchmark/test_iter_benchmark.c new file mode 100644 index 0000000..7aa7c02 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/benchmark/test_iter_benchmark.c @@ -0,0 +1,100 @@ +/* Capstone Disassembler Engine */ +/* By bughoho , 2015> */ + +#include +#include +#include + +#include +#include + +static void test() +{ +#define X86_CODE32 "\x53\x8B\xDC\x83\xEC\x08\x83\xE4\xF0\x83\xC4\x04\x55\x8B\x6B\x04\x89\x6C\x24\x04\x8B\xEC\x83\xEC\x78\xA1\x90\xA3\x4B\x01\x33\xC5 \ +\x89\x45\xFC\x8B\x41\x04\x0F\x28\x05\x80\x30\x20\x01\x0F\x29\x45\xD0\x0F\x28\x05\x50\xAB\x1E\x01\x89\x4D\x90\x89\x45\xB8\x0F\x29 \ +\x45\xE0\x56\x8B\x73\x08\x57\xC7\x06\x00\x00\x00\x00\xC7\x46\x04\x00\x00\x00\x00\xC7\x46\x08\x00\x00\x00\x00\xC7\x46\x0C\x00\x00 \ +\x00\x00\x85\xC0\x0F\x84\xCB\x01\x00\x00\x33\xFF\x8D\x64\x24\x00\x8B\x01\x8B\x0C\x07\x89\x4D\xBC\x85\xC9\x0F\x84\xA6\x01\x00\x00 \ +\x8B\x43\x0C\x0F\x10\x00\x0F\x29\x45\xD0\x0F\x10\x40\x10\x0F\x29\x45\xE0\x8B\x01\x8B\x40\x08\xFF\xD0\xF3\x0F\x10\x65\xD0\x8D\x55 \ +\xD0\xF3\x0F\x10\x55\xD4\xF3\x0F\x10\x6D\xE0\xF3\x0F\x10\x48\x10\xF3\x0F\x10\x00\xF3\x0F\x10\x5D\xE4\xF3\x0F\x59\xCA\x8B\x4D\xBC \ +\xF3\x0F\x59\xC4\x52\x8D\x55\xC0\x52\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xD0\xF3\x0F\x10\x48\x10\xF3\x0F\x10\x00\xF3\x0F\x59\xCB\xF3 \ +\x0F\x59\xC5\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xE0\x0F\x28\xCC\xF3\x0F\x59\x48\x04\xF3\x0F\x10\x40\x14\xF3\x0F\x59\xC2\xF3\x0F\x58 \ +\xC8\xF3\x0F\x11\x4D\xD4\x0F\x28\xCD\xF3\x0F\x10\x40\x14\xF3\x0F\x59\x48\x04\xC7\x45\xE8\x00\x00\x00\x00\xF3\x0F\x59\xC3\xC7\x45 \ +\xD8\x00\x00\x00\x00\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xE4\xF3\x0F\x59\x60\x0C\xF3\x0F\x59\x50\x1C\xF3\x0F\x58\xE2\xF3\x0F\x58\x65 \ +\xDC\xF3\x0F\x11\x65\xDC\xF3\x0F\x59\x68\x0C\xF3\x0F\x59\x58\x1C\xF3\x0F\x58\xEB\xF3\x0F\x58\x6D\xEC\xF3\x0F\x11\x6D\xEC\x8B\x01 \ +\x8B\x80\xF8\x00\x00\x00\xFF\xD0\xF3\x0F\x10\x10\xF3\x0F\x10\x58\x08\x0F\x2F\xD3\xF3\x0F\x10\x40\x04\xF3\x0F\x10\x48\x0C\xF3\x0F \ +\x11\x55\xA0\xF3\x0F\x11\x45\x94\xF3\x0F\x11\x5D\x98\xF3\x0F\x11\x4D\xBC\x0F\x83\x8E\x00\x00\x00\x0F\x2F\xC1\x0F\x83\x85\x00\x00 \ +\x00\x8B\xCE\xE8\xE8\xAC\x86\xFF\xF3\x0F\x10\x65\xA0\x84\xC0\x75\x53\xF3\x0F\x10\x06\x0F\x2F\xC4\x77\x03\x0F\x28\xE0\xF3\x0F\x10 \ +\x5E\x08\xF3\x0F\x10\x45\x98\x0F\x2F\xD8\x77\x03\x0F\x28\xD8\xF3\x0F\x10\x4E\x04\xF3\x0F\x10\x45\x94\x0F\x2F\xC8\x77\x03\x0F\x28 \ +\xC1\xF3\x0F\x10\x4E\x0C\xF3\x0F\x10\x55\xBC\x0F\x2F\xCA\x77\x03\x0F\x28\xCA\xF3\x0F\x11\x46\x04\xF3\x0F\x11\x5E\x08\xF3\x0F\x11" + /* i'm test on the ubuntu 15.04 vmware, + * Sorry I haven't linux under the physical environment, + * so the results may not be accurate. + * + * original version output: + * bug@ubuntu:~/capstone/suite/benchmark$ make + * cc -c -I../../include test_iter_benchmark.c -o test_iter_benchmark.o + * cc test_iter_benchmark.o -O3 -Wall -lcapstone -o test_iter_benchmark + * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark + * time used:6.017613 + * + * rebuild: + * + * bug@ubuntu:~/capstone$ make clean + * bug@ubuntu:~/capstone$ sudo make install + * bug@ubuntu:~/capstone$ cd suite/benchmark/ + * bug@ubuntu:~/capstone/suite/benchmark$ make clean + * bug@ubuntu:~/capstone/suite/benchmark$ make + * + * modified version output: + * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark + * time used:5.003864 + * + * if we don't output format text string,like this: + * //handle->printer(&mci, &ss, handle->printer_info); <-----cs.c line 700 + * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark + * time used:2.059570 + */ + + csh handle; + uint64_t address; + cs_insn *insn; + int i; + cs_err err; + const uint8_t *code; + size_t size; + + err = cs_open(CS_ARCH_X86, CS_MODE_32, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + return; + } + cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL); + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + clock_t start, end; + double timeUsed; + + start = clock(); + int maxcount = 10000000; + insn = cs_malloc(handle); + for (i = 0; i < maxcount;) { + code = (const uint8_t *)X86_CODE32; + address = 0x1000; + size = sizeof(X86_CODE32) - 1; + while(cs_disasm_iter(handle, &code, &size, &address, insn)) { + i++; + } + } + cs_free(insn, 1); + cs_close(&handle); + end = clock(); + timeUsed = (double)(end - start) / CLOCKS_PER_SEC; + printf("time used:%f\n", timeUsed); +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/capstone_get_setup.c b/white_patch_detect/capstone-master/suite/capstone_get_setup.c new file mode 100644 index 0000000..a166645 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/capstone_get_setup.c @@ -0,0 +1,82 @@ +/* + Retrieve architectures compiled in Capstone. + By Nguyen Anh Quynh, 2019. + + Compile this code with: + $ cc -o capstone_get_setup capstone_get_setup.c -lcapstone + + On default Capstone build, this code prints out the below output: + + $ capstone_get_setup + x86=1 arm=1 arm64=1 mips=1 ppc=1 sparc=1 sysz=1 xcore=1 m68k=1 tms320c64x=1 m680x=1 evm=1 +*/ + +#include +#include + +int main() +{ + if (cs_support(CS_ARCH_X86)) { + printf("x86=1 "); + } + + if (cs_support(CS_ARCH_ARM)) { + printf("arm=1 "); + } + + if (cs_support(CS_ARCH_ARM64)) { + printf("arm64=1 "); + } + + if (cs_support(CS_ARCH_MIPS)) { + printf("mips=1 "); + } + + if (cs_support(CS_ARCH_PPC)) { + printf("ppc=1 "); + } + + if (cs_support(CS_ARCH_SPARC)) { + printf("sparc=1 "); + } + + if (cs_support(CS_ARCH_SYSZ)) { + printf("sysz=1 "); + } + + if (cs_support(CS_ARCH_XCORE)) { + printf("xcore=1 "); + } + + if (cs_support(CS_ARCH_M68K)) { + printf("m68k=1 "); + } + + if (cs_support(CS_ARCH_TMS320C64X)) { + printf("tms320c64x=1 "); + } + + if (cs_support(CS_ARCH_M680X)) { + printf("m680x=1 "); + } + + if (cs_support(CS_ARCH_EVM)) { + printf("evm=1 "); + } + + if (cs_support(CS_ARCH_MOS65XX)) { + printf("mos65xx=1 "); + } + + if (cs_support(CS_SUPPORT_DIET)) { + printf("diet=1 "); + } + + if (cs_support(CS_SUPPORT_X86_REDUCE)) { + printf("x86_reduce=1 "); + } + + printf("\n"); + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/compile_all.sh b/white_patch_detect/capstone-master/suite/compile_all.sh new file mode 100644 index 0000000..6666b2e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/compile_all.sh @@ -0,0 +1,30 @@ +#! /bin/bash +# By Daniel Godas-Lopez. + +export LD_LIBRARY_PATH=. + +for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do + echo -n "Compiling: $x ... " + ./compile.sh $x &> /dev/null + + if [ $? == 0 ]; then + echo "-> PASS" + else + echo -e "-> FAILED\n" + continue + fi + + for t in test test_arm test_arm64 test_detail test_mips test_x86 test_ppc; do + ./tests/$t &> /dev/null + + if [ $? -eq 0 ]; then + echo " Run $t -> PASS" + else + echo " Run $t -> FAIL" + fi + done + + echo +done + +make clean &> /dev/null diff --git a/white_patch_detect/capstone-master/suite/cstest/Makefile b/white_patch_detect/capstone-master/suite/cstest/Makefile new file mode 100644 index 0000000..23d8334 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/Makefile @@ -0,0 +1,13 @@ +SOURCE=src +INCLUDE=include +BUILD=build +LIBRARY= -lcmocka -lcapstone + +all: + rm -rf $(BUILD) + mkdir $(BUILD) + $(CC) $(SOURCE)/*.c -I$(INCLUDE) -o $(BUILD)/cstest $(LIBRARY) +cstest: + $(BUILD)/cstest -d ../MC +clean: + rm -rf $(BUILD) diff --git a/white_patch_detect/capstone-master/suite/cstest/README.md b/white_patch_detect/capstone-master/suite/cstest/README.md new file mode 100644 index 0000000..a9880da --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/README.md @@ -0,0 +1,78 @@ +# Regression testing +This directory contains a tool for regression testing core of Capstone + +## Dependency + +- MacOS users can install cmocka with: + +``` +brew install cmocka +``` + +- Or download & build from source code [Cmocka](https://git.cryptomilk.org/projects/cmocka.git) + +- Build Cmocka + +``` +cd cmocka_dir +mkdir build +cd build +cmake .. +make +sudo make isntall +``` + +## Build + +- Build `cstest` + +``` +cd suite/cstest +make +``` + +## Usage + +- Usage: `cstest [-e] [-f ] [-d ]` + - `-e` : test all commented test + +- Test for all closed issues + +``` +cd suite/cstest +./build/cstest -f ./issues.cs +``` + +- Test for some input from LLVM + +``` +cd suite/cstest +./build/cstest -f ../MC/AArch64/basic-a64-instructions.s.cs +``` + +- Test for all cs file in a folder + +``` +cd suite/cstest +./build/cstest -d ../MC +``` + +- Test all + +``` +cd suite/cstest +make cstest +``` + +## Report tool + +- Usage `cstest_report.py [-Dc] -t [-f ] [-d ]` + - `-D` : print details + - `-c` : auto comment out failed test + +- Example: + +``` +./cstest_report.py -t build/cstest -d ../MC/PowerPC/ +./cstest_report.py -t build/cstest -f issues.cs +``` diff --git a/white_patch_detect/capstone-master/suite/cstest/build_cstest.sh b/white_patch_detect/capstone-master/suite/cstest/build_cstest.sh new file mode 100644 index 0000000..5b4ba4c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/build_cstest.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +cd cmocka && mkdir build && cd build +if [ "$(uname)" = Darwin ]; then +cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install +else # Linux +cmake -DCMAKE_INSTALL_PREFIX=/usr .. && make -j2 && sudo make install +fi +cd ../.. && make diff --git a/white_patch_detect/capstone-master/suite/cstest/cstest_report.py b/white_patch_detect/capstone-master/suite/cstest/cstest_report.py new file mode 100644 index 0000000..17da395 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/cstest_report.py @@ -0,0 +1,102 @@ +#!/usr/bin/python + +import re +import sys +import getopt +from subprocess import Popen, PIPE +from pprint import pprint as ppr +import os + + +def Usage(s): + print 'Usage: {} -t [-f ] [-d ]'.format(s) + sys.exit(-1) + +def get_report_file(toolpath, filepath, getDetails, cmt_out): + cmd = [toolpath, '-f', filepath] + process = Popen(cmd, stdout=PIPE, stderr=PIPE) + stdout, stderr = process.communicate() + +# stdout + failed_tests = [] +# print '---> stdout\n', stdout +# print '---> stderr\n', stderr + matches = re.finditer(r'\[\s+RUN\s+\]\s+(.*)\n\[\s+FAILED\s+\]', stdout) + for match in matches: + failed_tests.append(match.group(1)) +# stderr + counter = 0 + details = [] + for line in stderr.split('\n'): + if '[ PASSED ] 0 test(s).' in line: + break + elif 'LINE' in line: + continue + elif 'ERROR' in line and ' --- ' in line: + parts = line.split(' --- ') + try: + details.append((parts[1], failed_tests[counter], parts[2])) + except IndexError: + details.append(('', 'Unknown test', line.split(' --- ')[1])) + counter += 1 + else: + continue + print '\n[-] There are/is {} failed test(s)'.format(len(details)) + if len(details) > 0 and getDetails: + print '[-] Detailed report for {}:\n'.format(filepath) + for c, f, d in details: + print '\t[+] {}: {}\n\t\t{}\n'.format(f, c, d) + print '\n' + return 0 + elif len(details) > 0: + for c, f, d in details: + if len(f) > 0 and cmt_out is True: + tmp_cmd = ['sed', '-E', '-i.bak', 's/({})(.*)/\/\/ \\1\\2/g'.format(c), filepath] + sed_proc = Popen(tmp_cmd, stdout=PIPE, stderr=PIPE) + sed_proc.communicate() + tmp_cmd2 = ['rm', '-f', filepath + '.bak'] + rm_proc = Popen(tmp_cmd2, stdout=PIPE, stderr=PIPE) + rm_proc.communicate() + + return 0; + return 1 + +def get_report_folder(toolpath, folderpath, details, cmt_out): + result = 1 + for root, dirs, files in os.walk(folderpath): + path = root.split(os.sep) + for f in files: + if f.split('.')[-1] == 'cs': + print '[-] Target:', f, + result *= get_report_file(toolpath, os.sep.join(x for x in path) + os.sep + f, details, cmt_out) + + sys.exit(result ^ 1) + +if __name__ == '__main__': + Done = False + details = False + toolpath = '' + cmt_out = False + try: + opts, args = getopt.getopt(sys.argv[1:], "ct:f:d:D") + for opt, arg in opts: + if opt == '-f': + result = get_report_file(toolpath, arg, details, cmt_out) + if result == 0: + sys.exit(1) + Done = True + elif opt == '-d': + get_report_folder(toolpath, arg, details, cmt_out) + Done = True + elif opt == '-t': + toolpath = arg + elif opt == '-D': + details = True + elif opt == '-c': + cmt_out = True + + except getopt.GetoptError: + Usage(sys.argv[0]) + + if Done is False: + Usage(sys.argv[0]) diff --git a/white_patch_detect/capstone-master/suite/cstest/include/capstone_test.h b/white_patch_detect/capstone-master/suite/cstest/include/capstone_test.h new file mode 100644 index 0000000..1299190 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/include/capstone_test.h @@ -0,0 +1,65 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#ifndef CAPSTONE_TEST_H +#define CAPSTONE_TEST_H + +#include +#include +#include +#include +#include +#include +#include +#include "helper.h" +#include "factory.h" + +#define cs_assert_err(expect, err) \ + do { \ + cs_err __err = err; \ + if (__err != expect) { \ + fail_msg("%s",cs_strerror(__err)); \ + } \ + } while (0) + + +#define cs_assert_success(err) cs_assert_err(CS_ERR_OK, err) + + +#define cs_assert_fail(err) \ + do { \ + cs_err __err = err; \ + if (__err == CS_ERR_OK) { \ + fail_msg("%s",cs_strerror(__err)); \ + } \ + } while (0) + +#define NUMARCH 9 +#define NUMMODE 33 +#define NUMOPTION 41 +#define MAXMEM 1024 + +typedef struct { + const char *str; + unsigned int value; +} single_dict; + +typedef struct { + const char *str; + unsigned int first_value; + unsigned int second_value; +} double_dict; + +extern single_dict arches[]; +extern single_dict modes[]; +extern double_dict options[]; +extern char *(*function)(csh *, cs_mode, cs_insn*); + +int get_index(double_dict d[], unsigned size, const char *str); +int get_value(single_dict d[], unsigned size, const char *str); +void test_single_MC(csh *handle, int mc_mode, char *line); +void test_single_issue(csh *handle, cs_mode mode, char *line, int detail); +int set_function(int arch); + +#endif /* CAPSTONE_TEST_H */ diff --git a/white_patch_detect/capstone-master/suite/cstest/include/factory.h b/white_patch_detect/capstone-master/suite/cstest/include/factory.h new file mode 100644 index 0000000..588fd73 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/include/factory.h @@ -0,0 +1,25 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#ifndef FACTORY_H +#define FACTORY_H + +#include +#include "helper.h" + +char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); + +#endif /* FACTORY_H */ diff --git a/white_patch_detect/capstone-master/suite/cstest/include/helper.h b/white_patch_detect/capstone-master/suite/cstest/include/helper.h new file mode 100644 index 0000000..1022303 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/include/helper.h @@ -0,0 +1,32 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#ifndef HELPER_H +#define HELPER_H + +#include +#include +#include +#include +#include +#include +#include "capstone_test.h" + +#define X86_16 0 +#define X86_32 1 +#define X86_64 2 + +char **split(char *str, char *delim, int *size); +void print_strs(char **list_str, int size); +void free_strs(char **list_str, int size); +void add_str(char **src, const char *format, ...); +void trim_str(char *src); +void replace_hex(char *src); +void replace_negative(char *src, int mode); +const char *get_filename_ext(const char *filename); + +char *readfile(const char *filename); +void listdir(const char *name, char ***files, int *num_files); + +#endif /* HELPER_H */ diff --git a/white_patch_detect/capstone-master/suite/cstest/issues.cs b/white_patch_detect/capstone-master/suite/cstest/issues.cs new file mode 100644 index 0000000..2d2468a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/issues.cs @@ -0,0 +1,436 @@ +!# issue 0 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_UNSIGNED +0x66,0x83,0xc0,0x80 == add ax, 0xff80 + +!# issue 0 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_UNSIGNED +0x66,0x83,0xc0,0x80 == addw $0xff80, %ax + +!# issue 1323 +!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL +0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = lr ; operands[0].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: thumb jump + +!# issue 1317 +!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL +0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: thumb2 jump + +!# issue 1308 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x83 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF + +!# issue 1262 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x95 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF + +!# issue 1262 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x94 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF + +!# issue 1255 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdb 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu + +!# issue 1255 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdd 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF + +!# issue 1255 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdf 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu + +!# issue 1221 +!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794 + +!# issue 1144 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, #0x4000 + +!# issue 1144 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, #0xffffffffffff8000 + +!# issue 1144 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, #0x4000 + +!# issue 1144 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, #0xffffffffffff8000 + +!# issue 826 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x0b,0x00,0x00,0x0a == beq #0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 1 ; Registers read: pc ; Registers modified: pc ; Groups: branch_relative arm jump + +!# issue 1047 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp + +!# issue 959 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728] + +!# issue 950 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax + +!# issue 938 +!# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None +0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp) + +!# issue 915 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax] + +!# issue 913 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm + +!# issue 884 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax + +!# issue 872 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41 + +!# issue 861 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 4 ; operands[0].type: P-IMM = 1 ; operands[1].type: C-IMM = 8 ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: READ ; operands[3].type: IMM = 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 ; Groups: prev8 + +!# issue 852 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax + +!# issue 825 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm + +!# issue 813 +!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None +0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801 + +!# issue 809 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x29 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 + +!# issue 807 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea] + +!# issue 806 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0x0f,0x35 == sysexit + +!# issue 805 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8 + +!# issue 804 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rol $1, %ax + +!# issue 789 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x8e,0x1e == movw (%rsi), %ds + +!# issue 767 +!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL +0x0: 0xb1,0xe8,0xfc,0x07 == ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, sb, sl} ; op_count: 10 ; operands[0].type: REG = r1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r2 ; operands[1].access: WRITE ; operands[2].type: REG = r3 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: REG = r5 ; operands[4].access: WRITE ; operands[5].type: REG = r6 ; operands[5].access: WRITE ; operands[6].type: REG = r7 ; operands[6].access: WRITE ; operands[7].type: REG = r8 ; operands[7].access: WRITE ; operands[8].type: REG = sb ; operands[8].access: WRITE ; operands[9].type: REG = sl ; operands[9].access: WRITE ; Write-back: True ; Registers read: r1 ; Registers modified: r1 r2 r3 r4 r5 r6 r7 r8 sb sl ; Groups: thumb2 + +!# issue 760 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = pc ; operands[1].access: WRITE ; Registers read: sp ; Registers modified: sp r1 pc ; Groups: arm + +!# issue 750 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x0e,0x00,0x20,0xe9 == stmdb r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r1 ; operands[2].type: REG = r2 ; operands[3].type: REG = r3 ; Write-back: True ; Registers read: r0 ; Groups: arm + +!# issue 747 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x0e,0x00,0xb0,0xe8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: arm + +!# issue 747 +!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL +0x0: 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: thumb thumb1only + +!# issue 746 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x89,0x00,0x2d,0xe9 == push {r0, r3, r7} ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r3 ; operands[1].access: READ ; operands[2].type: REG = r7 ; operands[2].access: READ ; Registers read: sp r0 r3 r7 ; Registers modified: sp ; Groups: arm + +!# issue 744 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = pc ; operands[1].access: WRITE ; Registers read: sp ; Registers modified: sp r1 pc ; Groups: arm + +!# issue 741 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x83,0xff,0xf7 == cmp edi, -9 + +!# issue 717 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT +0x0: 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 == movq 0, %rax + +!# issue 711 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xa3,0x44,0xb0,0x00,0x10 == mov dword ptr [0x1000b044], eax ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x1000b044 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1000b044 ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: eax + +!# issue 613 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0xd9,0x74,0x24,0xd8 == fnstenv [rsp - 0x28] + +!# issue 554 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xe7,0x84 == out 0x84, eax + +!# issue 554 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xe5,0x8c == in eax, 0x8c + +!# issue 545 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x95 == xchg eax, ebp ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x95 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = eax ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: REG = ebp ; operands[1].size: 4 ; operands[1].access: READ | WRITE ; Registers read: eax ebp ; Registers modified: eax ebp ; Groups: not64bitmode + +!# issue 544 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xdf,0x30 == fbstp tbyte ptr [eax] + +!# issue 544 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xdf,0x20 == fbld tbyte ptr [eax] + +!# issue 541 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff == movabs rax, 0xfffff88000000000 + +!# issue 499 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 == movabs rax, 0x8000000000000000 + +!# issue 492 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xff,0x18 == lcall [eax] + +!# issue 492 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xff,0x28 == ljmp [eax] + +!# issue 492 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0xae,0x04,0x24 == fxsave [esp] + +!# issue 492 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0xae,0x0c,0x24 == fxrstor [esp] + +!# issue 470 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 == sgdt [0x80490a0] + +!# issue 470 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 == sidt [0x80490a7] + +!# issue 470 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 == lgdt [0x80490a0] + +!# issue 470 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 == lidt [0x80490a7] + +!# issue 459 +!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL +0x0: 0xd3,0x20,0x11,0xe1 == ldrsb r2, [r1, -r3] ; op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: -1 ; Subtracted: True ; Registers read: r1 r3 ; Registers modified: r2 ; Groups: arm + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0xe8,0x35,0x64 == call 0x6438 + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0xe9,0x35,0x64 == jmp 0x6438 + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0x66,0xe8,0x35,0x64,0x93,0x53 == call 0x5393643b + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x66,0xe8,0x35,0x64 == call 0x6439 + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643a + +!# issue 456 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x66,0xe9,0x35,0x64 == jmp 0x6439 + +!# issue 458 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xA1,0x12,0x34,0x90,0x90 == mov eax, dword ptr [0x90903412] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x90903412 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = eax ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.disp: 0x90903412 ; operands[1].size: 4 ; operands[1].access: READ ; Registers modified: eax + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0x6c == repne insb byte ptr es:[edi], dx + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0x6d == repne insd dword ptr es:[edi], dx + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0x6e == repne outsb dx, byte ptr [esi] + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0x6f == repne outsd dx, dword ptr [esi] + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0xac == repne lodsb al, byte ptr [esi] + +!# issue 454 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0xad == repne lodsd eax, dword ptr [esi] + +!# issue 450 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xff,0x2d,0x34,0x35,0x23,0x01 == ljmp [0x1233534] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xff 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x2d ; disp: 0x1233534 ; sib: 0x0 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1233534 ; operands[0].size: 6 ; Groups: jump + +!# issue 448 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc == ljmp 0xbc9a:0x78563412 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xea 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 2 ; imms[1]: 0xbc9a ; imms[2]: 0x78563412 ; op_count: 2 ; operands[0].type: IMM = 0xbc9a ; operands[0].size: 2 ; operands[1].type: IMM = 0x78563412 ; operands[1].size: 4 ; Groups: not64bitmode jump + +!# issue 426 +!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None +0x0: 0xbb,0x70,0x00,0x00 == popc %g0, %i5 + +!# issue 358 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xe8,0xe3,0xf6,0xff,0xff == call 0xfffff6e8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe8 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xfffff6e8 ; op_count: 1 ; operands[0].type: IMM = 0xfffff6e8 ; operands[0].size: 4 ; Registers read: esp eip ; Registers modified: esp ; Groups: call branch_relative not64bitmode + +!# issue 353 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xe6,0xa2 == out 0xa2, al ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe6 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xa2 ; op_count: 2 ; operands[0].type: IMM = 0xa2 ; operands[0].size: 4 ; operands[1].type: REG = al ; operands[1].size: 1 ; operands[1].access: READ ; Registers read: al + +!# issue 305 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x34,0x8b == xor al, 0x8b + +!# issue 298 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf3,0x90 == pause + +!# issue 298 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0x66,0xf3,0xf2,0x0f,0x59,0xff == mulsd xmm7, xmm7 + +!# issue 298 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xf2,0x66,0x0f,0x59,0xff == mulpd xmm7, xmm7 + +!# issue 294 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xc1,0xe6,0x08 == shl esi, 8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xc1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xe6 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x8 ; op_count: 2 ; operands[0].type: REG = esi ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x8 ; operands[1].size: 1 ; Registers read: esi ; Registers modified: eflags esi ; EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF UNDEF_AF + +!# issue 285 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x3c,0x12,0x80 == cmp al, 0x12 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x3c 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x12 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: READ ; operands[1].type: IMM = 0x12 ; operands[1].size: 1 ; Registers read: al ; Registers modified: eflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF + +!# issue 265 +!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL +0x0: 0x52,0xf8,0x23,0x30 == ldr.w r3, [r2, r3, lsl #2] ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r3 ; operands[1].access: READ ; Shift: 2 = 2 ; Registers read: r2 r3 ; Registers modified: r3 ; Groups: thumb2 + +!# issue 264 +!# CS_ARCH_ARM, CS_MODE_THUMB, None +0x0: 0x0c,0xbf == ite eq + +!# issue 264 +!# CS_ARCH_ARM, CS_MODE_THUMB, None +0x0: 0x17,0x20 == movs r0, #0x17 + +!# issue 264 +!# CS_ARCH_ARM, CS_MODE_THUMB, None +0x0: 0x4f,0xf0,0xff,0x30 == mov.w r0, #-1 + +!# issue 246 +!# CS_ARCH_ARM, CS_MODE_THUMB, None +0x0: 0x52,0xf8,0x23,0xf0 == ldr.w pc, [r2, r3, lsl #2] + +!# issue 232 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x8e,0x10 == mov ss, word ptr [eax] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x8e 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x10 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ss ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = eax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: eax ; Registers modified: ss ; Groups: privilege + +!# issue 231 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0x66,0x6b,0xc0,0x02 == imul ax, ax, 2 ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0x6b 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xc0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x2 ; op_count: 3 ; operands[0].type: REG = ax ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; operands[2].type: IMM = 0x2 ; operands[2].size: 2 ; Registers read: ax ; Registers modified: eflags ax ; EFLAGS: MOD_CF MOD_SF MOD_OF UNDEF_ZF UNDEF_PF UNDEF_AF + +!# issue 230 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xec == in al, dx ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xec 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: WRITE ; operands[1].type: REG = dx ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: dx ; Registers modified: al + +!# issue 213 +!# CS_ARCH_X86, CS_MODE_16, None +0x0: 0xea,0xaa,0xff,0x00,0xf0 == ljmp 0xf000:0xffaa + +!# issue 191 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0xc5,0xe8,0xc2,0x33,0x9b == vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b + +!# issue 176 +!# CS_ARCH_ARM, CS_MODE_ARM, None +0x0: 0xfd,0xff,0xff,0x1a == bne #0xfffffffc + +!# issue 151 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 == lea r15, [rip + 2] + +!# issue 151 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0xeb,0xb0 == jmp 0xffffffffffffffb2 + +!# issue 134 +!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL +0x0: 0xe7,0x92,0x11,0x80 == ldr r1, [r2, r0, lsl #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r0 ; operands[1].access: READ ; Shift: 2 = 3 ; Registers read: r2 r0 ; Registers modified: r1 ; Groups: arm + +!# issue 133 +!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL +0x0: 0xed,0xdf,0x2b,0x1b == vldr d18, [pc, #0x6c] ; op_count: 2 ; operands[0].type: REG = d18 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = pc ; operands[1].mem.disp: 0x6c ; operands[1].access: READ ; Registers read: pc ; Registers modified: d18 ; Groups: vfp2 + +!# issue 132 +!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL +0x0: 0x49,0x19 == ldr r1, [pc, #0x64] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = pc ; operands[1].mem.disp: 0x64 ; operands[1].access: READ ; Registers read: pc ; Registers modified: r1 ; Groups: thumb thumb1only + +!# issue 130 +!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL +0x0: 0xe1,0xa0,0xf0,0x0e == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm + +!# issue 85 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0xee,0x3f,0xbf,0x29 == stp w14, w15, [sp, #-8]! + +!# issue 82 +!# CS_ARCH_X86, CS_MODE_64, None +0x0: 0xf2,0x66,0xaf == repne scasw ax, word ptr [rdi] + +!# issue 35 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xe8,0xc6,0x02,0x00,0x00 == call 0x2cb + +!# issue 8 +!# CS_ARCH_X86, CS_MODE_32, None +0x0: 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 == dec dword ptr [ecx + edi*8 - 0x6640001] + +!# issue 29 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None +0x0: 0x00,0x00,0x00,0x4c == st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/arm64_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/arm64_detail.c new file mode 100644 index 0000000..266659f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/arm64_detail.c @@ -0,0 +1,136 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_arm64 *arm64; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + uint8_t access; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + // detail can be NULL if SKIPDATA option is turned ON + if (ins->detail == NULL) + return result; + + arm64 = &(ins->detail->arm64); + if (arm64->op_count) + add_str(&result, " ; op_count: %u", arm64->op_count); + + for (i = 0; i < arm64->op_count; i++) { + cs_arm64_op *op = &(arm64->operands[i]); + switch(op->type) { + default: + break; + case ARM64_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case ARM64_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + break; + case ARM64_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + add_str(&result, " ; operands[%u].type: FP = ", i); +#else + add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); +#endif + break; + case ARM64_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != ARM64_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.index != ARM64_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + + break; + case ARM64_OP_CIMM: + add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm); + break; + case ARM64_OP_REG_MRS: + add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg); + break; + case ARM64_OP_REG_MSR: + add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg); + break; + case ARM64_OP_PSTATE: + add_str(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate); + break; + case ARM64_OP_SYS: + add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys); + break; + case ARM64_OP_PREFETCH: + add_str(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch); + break; + case ARM64_OP_BARRIER: + add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier); + break; + } + + access = op->access; + switch(access) { + default: + break; + case CS_AC_READ: + add_str(&result, " ; operands[%u].access: READ", i); + break; + case CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: WRITE", i); + break; + case CS_AC_READ | CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: READ | WRITE", i); + break; + } + + if (op->shift.type != ARM64_SFT_INVALID && op->shift.value) + add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value); + + if (op->ext != ARM64_EXT_INVALID) + add_str(&result, " ; Ext: %u", op->ext); + + if (op->vas != ARM64_VAS_INVALID) + add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas); + + if (op->vess != ARM64_VESS_INVALID) + add_str(&result, " ; Vector Element Size Specifier: %u", op->vess); + + if (op->vector_index != -1) + add_str(&result, " ; Vector Index: %u", op->vector_index); + } + + if (arm64->update_flags) + add_str(&result, " ; Update-flags: True"); + + if (arm64->writeback) + add_str(&result, " ; Write-back: True"); + + if (arm64->cc) + add_str(&result, " ; Code-condition: %u", arm64->cc); + + if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, " ; Registers read:"); + for(i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); + } + } + + if (regs_write_count) { + add_str(&result, " ; Registers modified:"); + for(i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); + } + } + } + + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/arm_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/arm_detail.c new file mode 100644 index 0000000..f1d6402 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/arm_detail.c @@ -0,0 +1,150 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_arm *arm; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + arm = &(ins->detail->arm); + + if (arm->op_count) + add_str(&result, " ; op_count: %u", arm->op_count); + + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch((int)op->type) { + default: + break; + case ARM_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case ARM_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); + break; + case ARM_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + add_str(&result, " ; operands[%u].type: FP = ", i); +#else + add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); +#endif + break; + case ARM_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != ARM_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.index != ARM_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); + if (op->mem.scale != 1) + add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + if (op->mem.lshift != 0) + add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift); + + break; + case ARM_OP_PIMM: + add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm); + break; + case ARM_OP_CIMM: + add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm); + break; + case ARM_OP_SETEND: + add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le"); + break; + case ARM_OP_SYSREG: + add_str(&result, " ; operands[%u].type: SYSREG = %u", i, op->reg); + break; + } + + if (op->neon_lane != -1) { + add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane); + } + + switch(op->access) { + default: + break; + case CS_AC_READ: + add_str(&result, " ; operands[%u].access: READ", i); + break; + case CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: WRITE", i); + break; + case CS_AC_READ | CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: READ | WRITE", i); + break; + } + + if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { + if (op->shift.type < ARM_SFT_ASR_REG) + add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value); + else + add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value)); + } + + if (op->vector_index != -1) { + add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index); + } + + if (op->subtracted) + add_str(&result, " ; Subtracted: True"); + } + + if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) + add_str(&result, " ; Code condition: %u", arm->cc); + + if (arm->update_flags) + add_str(&result, " ; Update-flags: True"); + + if (arm->writeback) + add_str(&result, " ; Write-back: True"); + + if (arm->cps_mode) + add_str(&result, " ; CPSI-mode: %u", arm->cps_mode); + + if (arm->cps_flag) + add_str(&result, " ; CPSI-flag: %u", arm->cps_flag); + + if (arm->vector_data) + add_str(&result, " ; Vector-data: %u", arm->vector_data); + + if (arm->vector_size) + add_str(&result, " ; Vector-size: %u", arm->vector_size); + + if (arm->usermode) + add_str(&result, " ; User-mode: True"); + + if (arm->mem_barrier) + add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier); + + if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, " ; Registers read:"); + for(i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); + } + } + + if (regs_write_count) { + add_str(&result, " ; Registers modified:"); + for(i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); + } + } + } + + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/capstone_test.c b/white_patch_detect/capstone-master/suite/cstest/src/capstone_test.c new file mode 100644 index 0000000..c09eccc --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/capstone_test.c @@ -0,0 +1,367 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "capstone_test.h" + +single_dict arches[] = { + {"CS_ARCH_ARM", CS_ARCH_ARM}, + {"CS_ARCH_ARM64", CS_ARCH_ARM64}, + {"CS_ARCH_MIPS", CS_ARCH_MIPS}, + {"CS_ARCH_PPC", CS_ARCH_PPC}, + {"CS_ARCH_SPARC", CS_ARCH_SPARC}, + {"CS_ARCH_SYSZ", CS_ARCH_SYSZ}, + {"CS_ARCH_X86", CS_ARCH_X86}, + {"CS_ARCH_XCORE", CS_ARCH_XCORE}, + {"CS_ARCH_M68K", CS_ARCH_M68K} +}; + +single_dict modes[] = { + {"CS_MODE_LITTLE_ENDIAN", CS_MODE_LITTLE_ENDIAN}, + {"CS_MODE_ARM", CS_MODE_ARM}, + {"CS_MODE_16", CS_MODE_16}, + {"CS_MODE_32", CS_MODE_32}, + {"CS_MODE_64", CS_MODE_64}, + {"CS_MODE_THUMB", CS_MODE_THUMB}, + {"CS_MODE_MCLASS", CS_MODE_MCLASS}, + {"CS_MODE_V8", CS_MODE_V8}, + {"CS_MODE_MICRO", CS_MODE_MICRO}, + {"CS_MODE_MIPS3", CS_MODE_MIPS3}, + {"CS_MODE_MIPS32R6", CS_MODE_MIPS32R6}, + {"CS_MODE_MIPS2", CS_MODE_MIPS2}, + {"CS_MODE_V9", CS_MODE_V9}, + {"CS_MODE_QPX", CS_MODE_QPX}, + {"CS_MODE_M68K_000", CS_MODE_M68K_000}, + {"CS_MODE_M68K_010", CS_MODE_M68K_010}, + {"CS_MODE_M68K_020", CS_MODE_M68K_020}, + {"CS_MODE_M68K_030", CS_MODE_M68K_030}, + {"CS_MODE_M68K_040", CS_MODE_M68K_040}, + {"CS_MODE_M68K_060", CS_MODE_M68K_060}, + {"CS_MODE_BIG_ENDIAN", CS_MODE_BIG_ENDIAN}, + {"CS_MODE_MIPS32", CS_MODE_MIPS32}, + {"CS_MODE_MIPS64", CS_MODE_MIPS64}, + {"CS_MODE_M680X_6301", CS_MODE_M680X_6301}, + {"CS_MODE_M680X_6309", CS_MODE_M680X_6309}, + {"CS_MODE_M680X_6800", CS_MODE_M680X_6800}, + {"CS_MODE_M680X_6801", CS_MODE_M680X_6801}, + {"CS_MODE_M680X_6805", CS_MODE_M680X_6805}, + {"CS_MODE_M680X_6808", CS_MODE_M680X_6808}, + {"CS_MODE_M680X_6809", CS_MODE_M680X_6809}, + {"CS_MODE_M680X_6811", CS_MODE_M680X_6811}, + {"CS_MODE_M680X_CPU12", CS_MODE_M680X_CPU12}, + {"CS_MODE_M680X_HCS08", CS_MODE_M680X_HCS08} +}; + +double_dict options[] = { + {"CS_OPT_DETAIL", CS_OPT_DETAIL, CS_OPT_ON}, + {"CS_OPT_SKIPDATA", CS_OPT_SKIPDATA, CS_OPT_ON}, + {"CS_OPT_SYNTAX_DEFAULT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT}, + {"CS_OPT_SYNTAX_INTEL", CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL}, + {"CS_OPT_SYNTAX_ATT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT}, + {"CS_OPT_SYNTAX_NOREGNAME", CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME}, + {"CS_OPT_SYNTAX_MASM", CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM}, + {"CS_MODE_LITTLE_ENDIAN", CS_OPT_MODE, CS_MODE_LITTLE_ENDIAN}, + {"CS_MODE_ARM", CS_OPT_MODE, CS_MODE_ARM}, + {"CS_MODE_16", CS_OPT_MODE, CS_MODE_16}, + {"CS_MODE_32", CS_OPT_MODE, CS_MODE_32}, + {"CS_MODE_64", CS_OPT_MODE, CS_MODE_64}, + {"CS_MODE_THUMB", CS_OPT_MODE, CS_MODE_THUMB}, + {"CS_MODE_MCLASS", CS_OPT_MODE, CS_MODE_MCLASS}, + {"CS_MODE_V8", CS_OPT_MODE, CS_MODE_V8}, + {"CS_MODE_MICRO", CS_OPT_MODE, CS_MODE_MICRO}, + {"CS_MODE_MIPS3", CS_OPT_MODE, CS_MODE_MIPS3}, + {"CS_MODE_MIPS32R6", CS_OPT_MODE, CS_MODE_MIPS32R6}, + {"CS_MODE_MIPS2", CS_OPT_MODE, CS_MODE_MIPS2}, + {"CS_MODE_V9", CS_OPT_MODE, CS_MODE_V9}, + {"CS_MODE_QPX", CS_OPT_MODE, CS_MODE_QPX}, + {"CS_MODE_M68K_000", CS_OPT_MODE, CS_MODE_M68K_000}, + {"CS_MODE_M68K_010", CS_OPT_MODE, CS_MODE_M68K_010}, + {"CS_MODE_M68K_020", CS_OPT_MODE, CS_MODE_M68K_020}, + {"CS_MODE_M68K_030", CS_OPT_MODE, CS_MODE_M68K_030}, + {"CS_MODE_M68K_040", CS_OPT_MODE, CS_MODE_M68K_040}, + {"CS_MODE_M68K_060", CS_OPT_MODE, CS_MODE_M68K_060}, + {"CS_MODE_BIG_ENDIAN", CS_OPT_MODE, CS_MODE_BIG_ENDIAN}, + {"CS_MODE_MIPS32", CS_OPT_MODE, CS_MODE_MIPS32}, + {"CS_MODE_MIPS64", CS_OPT_MODE, CS_MODE_MIPS64}, + {"CS_MODE_M680X_6301", CS_OPT_MODE, CS_MODE_M680X_6301}, + {"CS_MODE_M680X_6309", CS_OPT_MODE, CS_MODE_M680X_6309}, + {"CS_MODE_M680X_6800", CS_OPT_MODE, CS_MODE_M680X_6800}, + {"CS_MODE_M680X_6801", CS_OPT_MODE, CS_MODE_M680X_6801}, + {"CS_MODE_M680X_6805", CS_OPT_MODE, CS_MODE_M680X_6805}, + {"CS_MODE_M680X_6808", CS_OPT_MODE, CS_MODE_M680X_6808}, + {"CS_MODE_M680X_6809", CS_OPT_MODE, CS_MODE_M680X_6809}, + {"CS_MODE_M680X_6811", CS_OPT_MODE, CS_MODE_M680X_6811}, + {"CS_MODE_M680X_CPU12", CS_OPT_MODE, CS_MODE_M680X_CPU12}, + {"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08}, + {"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON} +}; + +char *(*function)(csh *, cs_mode, cs_insn*) = NULL; + +void test_single_MC(csh *handle, int mc_mode, char *line) +{ + char **list_part, **list_byte; + int size_part, size_byte, size_data, size_insn; + int i, count, count_noreg; + unsigned char *code; + cs_insn *insn; + char tmp[MAXMEM], tmp_mc[MAXMEM], origin[MAXMEM], tmp_noreg[MAXMEM]; + char **offset_opcode; + int size_offset_opcode; + unsigned long offset; + char *p; + + list_part = split(line, " = ", &size_part); + offset_opcode = split(list_part[0], ": ", &size_offset_opcode); + if (size_offset_opcode > 1) { + offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); + list_byte = split(offset_opcode[1], ",", &size_byte); + } else { + offset = 0; + list_byte = split(offset_opcode[0], ",", &size_byte); + } + + code = (unsigned char *)malloc(size_byte * sizeof(char)); + for (i = 0; i < size_byte; ++i) { + code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); + } + + count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); + if (count == 0) { + fprintf(stderr, "[ ERROR ] --- %s --- Failed to disassemble given code!\n", list_part[0]); + free_strs(list_part, size_part); + free_strs(offset_opcode, size_offset_opcode); + free_strs(list_byte, size_byte); + free(code); + _fail(__FILE__, __LINE__); + } + if (count > 1) { + fprintf(stderr, "[ ERROR ] --- %s --- Multiple instructions(%d) disassembling doesn't support!\n", list_part[0], count); + free_strs(list_part, size_part); + free_strs(offset_opcode, size_offset_opcode); + free_strs(list_byte, size_byte); + free(code); + _fail(__FILE__, __LINE__); + } + + for (p = list_part[1]; *p; ++p) *p = tolower(*p); + for (p = list_part[1]; *p; ++p) + if (*p == '\t') *p = ' '; + trim_str(list_part[1]); + strcpy(tmp_mc, list_part[1]); + replace_hex(tmp_mc); + replace_negative(tmp_mc, mc_mode); + + strcpy(tmp, insn[0].mnemonic); + if (strlen(insn[0].op_str) > 0) { + tmp[strlen(insn[0].mnemonic)] = ' '; + strcpy(tmp + strlen(insn[0].mnemonic) + 1, insn[0].op_str); + } + + trim_str(tmp); + strcpy(origin, tmp); + replace_hex(tmp); + replace_negative(tmp, mc_mode); + + if (cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME) == CS_ERR_OK) { + count_noreg = cs_disasm(*handle, code, size_byte, offset, 0, &insn); + strcpy(tmp_noreg, insn[0].mnemonic); + if (strlen(insn[0].op_str) > 0) { + tmp_noreg[strlen(insn[0].mnemonic)] = ' '; + strcpy(tmp_noreg + strlen(insn[0].mnemonic) + 1, insn[0].op_str); + } + + trim_str(tmp_noreg); + replace_hex(tmp_noreg); + replace_negative(tmp_noreg, mc_mode); + + if (strcmp(tmp, tmp_mc) && strcmp(tmp_noreg, tmp_mc)) { + fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" and \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc, tmp_noreg, tmp_mc); + free_strs(list_part, size_part); + free_strs(offset_opcode, size_offset_opcode); + free_strs(list_byte, size_byte); + free(code); + cs_free(insn, count); + _fail(__FILE__, __LINE__); + } + + cs_option(*handle, CS_OPT_SYNTAX, 0); + + } else if (strcmp(tmp, tmp_mc)) { + fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc); + free_strs(list_part, size_part); + free_strs(offset_opcode, size_offset_opcode); + free_strs(list_byte, size_byte); + free(code); + cs_free(insn, count); + _fail(__FILE__, __LINE__); + } + + free_strs(list_part, size_part); + free_strs(offset_opcode, size_offset_opcode); + free_strs(list_byte, size_byte); + free(code); + cs_free(insn, count); +} + +int get_value(single_dict d[], unsigned int size, const char *str) +{ + int i; + + for (i = 0; i < size; ++i) + if (!strcmp(d[i].str, str)) + return d[i].value; + return -1; +} + +int get_index(double_dict d[], unsigned int size, const char *s) +{ + int i; + + for (i = 0; i < size; ++i) { + if (!strcmp(s, d[i].str)) + return i; + } + return -1; +} + +int set_function(int arch) +{ + switch(arch) { + case CS_ARCH_ARM: + function = get_detail_arm; + break; + case CS_ARCH_ARM64: + function = get_detail_arm64; + break; + case CS_ARCH_MIPS: + function = get_detail_mips; + break; + case CS_ARCH_PPC: + function = get_detail_ppc; + break; + case CS_ARCH_SPARC: + function = get_detail_sparc; + break; + case CS_ARCH_SYSZ: + function = get_detail_sysz; + break; + case CS_ARCH_X86: + function = get_detail_x86; + break; + case CS_ARCH_XCORE: + function = get_detail_xcore; + break; + case CS_ARCH_M68K: + function = get_detail_m68k; + break; + case CS_ARCH_M680X: + function = get_detail_m680x; + break; + case CS_ARCH_EVM: + function = get_detail_evm; + break; + case CS_ARCH_MOS65XX: + function = get_detail_mos65xx; + break; + case CS_ARCH_TMS320C64X: + function = get_detail_tms320c64x; + break; + default: + return -1; + } + return 0; +} + +void test_single_issue(csh *handle, cs_mode mode, char *line, int detail) +{ + char **list_part, **list_byte, **list_part_cs_result, **list_part_issue_result; + int size_part, size_byte, size_part_cs_result, size_part_issue_result; + char *tmptmp; + int i, count, j; + unsigned char *code; + cs_insn *insn; + char *cs_result, *tmp, *p; + char **offset_opcode; + int size_offset_opcode; + unsigned long offset; + + cs_result = (char *)malloc(sizeof(char)); + cs_result[0] = '\0'; + + list_part = split(line, " == ", &size_part); + + offset_opcode = split(list_part[0], ": ", &size_offset_opcode); + if (size_offset_opcode > 1) { + offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); + list_byte = split(offset_opcode[1], ",", &size_byte); + } else { + offset = 0; + list_byte = split(offset_opcode[0], ",", &size_byte); + } + + code = (unsigned char *)malloc(sizeof(char) * size_byte); + for (i = 0; i < size_byte; ++i) { + code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); + } + + count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); + for (i = 0; i < count; ++i) { + tmp = (char *)malloc(strlen(insn[i].mnemonic) + strlen(insn[i].op_str) + 100); + strcpy(tmp, insn[i].mnemonic); + if (strlen(insn[i].op_str) > 0) { + tmp[strlen(insn[i].mnemonic)] = ' '; + strcpy(tmp + strlen(insn[i].mnemonic) + 1, insn[i].op_str); + } + add_str(&cs_result, "%s", tmp); + free(tmp); + } + + if (detail == 1) { + tmp = (*function)(handle, mode, insn); + add_str(&cs_result, "%s", tmp); + free(tmp); + + if (insn->detail->groups_count) { + add_str(&cs_result, " ; Groups: "); + for (j = 0; j < insn->detail->groups_count; j++) { + add_str(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j])); + } + } + } + + trim_str(cs_result); + add_str(&cs_result, " ;"); + // list_part_cs_result = split(cs_result, " ; ", &size_part_cs_result); + for (p = list_part[1]; *p; ++p) if (*p == '\t') *p = ' '; + list_part_issue_result = split(list_part[1], " ; ", &size_part_issue_result); + + for (i = 0; i < size_part_issue_result; ++i) { + trim_str(list_part_issue_result[i]); + memset(tmptmp, MAXMEM, 0); + + tmptmp = (char *)malloc(sizeof(char)); + tmptmp[0] = '\0'; + add_str(&tmptmp, "%s", list_part_issue_result[i]); + add_str(&tmptmp, " ;"); + + if ((strstr(cs_result, tmptmp)) == NULL) { + fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" not in \"%s\"\n", list_part[0], list_part_issue_result[i], cs_result); + cs_free(insn, count); + free_strs(list_part, size_part); + free_strs(list_byte, size_byte); + free(cs_result); + // free_strs(list_part_cs_result, size_part_cs_result); + free_strs(list_part_issue_result, size_part_issue_result); + free(tmptmp); + _fail(__FILE__, __LINE__); + } + } + + cs_free(insn, count); + free_strs(list_part, size_part); + free_strs(list_byte, size_byte); + free(cs_result); + // free_strs(list_part_cs_result, size_part_cs_result); + free_strs(list_part_issue_result, size_part_issue_result); +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/evm_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/evm_detail.c new file mode 100644 index 0000000..635d309 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/evm_detail.c @@ -0,0 +1,30 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_evm *evm; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + evm = &(ins->detail->evm); + + if (evm->pop) + add_str(&result, " ; Pop: %u", evm->pop); + + if (evm->push) + add_str(&result, " ; Push: %u", evm->push); + + if (evm->fee) + add_str(&result, " ; Gas fee: %u", evm->fee); + + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/helper.c b/white_patch_detect/capstone-master/suite/cstest/src/helper.c new file mode 100644 index 0000000..0236551 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/helper.c @@ -0,0 +1,267 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "helper.h" + +char **split(char *str, char *delim, int *size) +{ + char **result; + char *token, *src; + int cnt; + + cnt = 0; + src = str; + result = NULL; + + while ((token = strstr(src, delim)) != NULL) { + result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); + result[cnt] = (char *)calloc(1, sizeof(char) * (int)(token - src + 10)); + memcpy(result[cnt], src, token - src); + result[cnt][token - src] = '\0'; + src = token + strlen(delim); + cnt ++; + } + + if (strlen(src) > 0) { + result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); + result[cnt] = strdup(src); + cnt ++; + } + + *size = cnt; + return result; +} + +void print_strs(char **list_str, int size) +{ + int i; + + printf("[+] Debug %d strings:\n", size); + for (i = 0; i < size; ++i) + printf("String %d'th: %s\n", i+1, list_str[i]); +} + +void free_strs(char **list_str, int size) +{ + int i; + for (i = 0; i < size; ++i) + free(list_str[i]); + + free(list_str); +} + +const char *get_filename_ext(const char *filename) +{ + const char *dot; + + dot = strrchr(filename, '.'); + if (!dot || dot == filename) + return ""; + + return dot + 1; +} + +char *readfile(const char *filename) +{ + char *result; + FILE *fp; + int size; + + fp = fopen(filename, "r"); + if (fp == NULL) { + puts("No such file"); + exit(-1); + } + + fseek(fp, 0, SEEK_END); + size = ftell(fp); + rewind(fp); + + result = (char *)calloc(1, sizeof(char) * size + 1); + fread(result, size, 1, fp); + result[size] = '\0'; + + fclose(fp); + return result; +} + +void add_str(char **src, const char *format, ...) +{ + char *tmp; + size_t len1, len2; + va_list args; + + tmp = (char *)malloc(sizeof(char) * 1000); + va_start(args, format); + vsprintf(tmp, format, args); + va_end(args); + + len1 = strlen(*src); + len2 = strlen(tmp); + + *src = (char *)realloc(*src, sizeof(char) * (len1 + len2 + 10)); + memcpy(*src + len1, tmp, len2 + 1); + free(tmp); +} + +void replace_hex(char *src) +{ + char *tmp, *result, *found, *origin, *orig_found; + int i, valid; + unsigned long long int value; + char *tmp_tmp; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + tmp = strdup(src); + origin = tmp; + + while ((found = strstr(tmp, "0x")) != NULL) { + orig_found = found; + found += 2; + value = 0; + valid = 0; + + tmp_tmp = strndup(tmp, orig_found - tmp); + while (*found != '\0' && isxdigit(*found)) { + valid = 1; + if (*found >= 'a' && *found <='f') + value = value*0x10 + (*found - 'a' + 10); + else + value = value*0x10 + (*found - '0'); + found++; + } + + if (valid == 1) add_str(&result, "%s%llu", tmp_tmp, value); + else add_str(&result, "%s0x", tmp_tmp); + tmp = found; + free(tmp_tmp); + } + + add_str(&result, "%s", tmp); + if (strlen(result) >= MAXMEM) { + fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_hex()\n"); + free(result); + free(origin); + _fail(__FILE__, __LINE__); + } + + strcpy(src, result); + free(result); + free(origin); +} + +void replace_negative(char *src, int mode) +{ + char *tmp, *result, *found, *origin, *orig_found; + int i, cnt, valid; + char *value, *tmp_tmp; + unsigned short int tmp_short; + unsigned int tmp_int; + unsigned long int tmp_long; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + tmp = strdup(src); + origin = tmp; + + while ((found = strstr(tmp, "-")) != NULL) { + orig_found = found; + found ++; + valid = 0; + + value = strdup("-"); + cnt = 2; + + while (*found != '\0' && isdigit(*found)) { + valid = 1; + value = (char *)realloc(value, cnt + 1); + value[cnt - 1] = *found; + value[cnt] = '\0'; + cnt ++; + found++; + } + + tmp_tmp = strndup(tmp, orig_found - tmp); + if (valid == 1) { + *orig_found = '\0'; + if (mode == X86_16) { + sscanf(value, "%hu", &tmp_short); + add_str(&result, "%s%hu", tmp_tmp, tmp_short); + } else if (mode == X86_32) { + sscanf(value, "%u", &tmp_int); + add_str(&result, "%s%u", tmp_tmp, tmp_int); + } else if (mode == X86_64) { + sscanf(value, "%lu", &tmp_long); + add_str(&result, "%s%lu", tmp_tmp, tmp_long); + } + } + else add_str(&result, "%s-", tmp_tmp); + + tmp = found; + free(value); + free(tmp_tmp); + } + + add_str(&result, "%s", tmp); + if (strlen(result) >= MAXMEM) { + fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_negative()\n"); + free(result); + free(origin); + _fail(__FILE__, __LINE__); + } + + strcpy(src, result); + free(result); + free(origin); +} + +void listdir(const char *name, char ***files, int *num_files) +{ + DIR *dir; + struct dirent *entry; + int cnt; + + if (!(dir = opendir(name))) + return; + + while ((entry = readdir(dir)) != NULL) { + if (entry->d_type == DT_DIR) { + char path[1024]; + if (strcmp(entry->d_name, ".") == 0 || strcmp(entry->d_name, "..") == 0) + continue; + snprintf(path, sizeof(path), "%s/%s", name, entry->d_name); + listdir(path, files, num_files); + } else { + cnt = *num_files; + *files = (char **)realloc(*files, sizeof(char *) * (cnt + 1)); + (*files)[cnt] = (char *)malloc(sizeof(char) * ( strlen(name) + 1 + strlen(entry->d_name) + 10)); + sprintf((*files)[cnt], "%s/%s", name, entry->d_name); + cnt ++; + *num_files = cnt; + } + } + + closedir(dir); +} + +void trim_str(char *str) +{ + char tmp[MAXMEM]; + int start, end, j, i; + + start = 0; + end = strlen(str) - 1; + j = 0; + while (start < strlen(str) && isspace(str[start])) start++; + while (end >= 0 && isspace(str[end])) end--; + + for (i = start; i <= end; ++i) + tmp[j++] = str[i]; + + tmp[j] = '\0'; + strcpy(str, tmp); + + return; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/m680x_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/m680x_detail.c new file mode 100644 index 0000000..a5b121d --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/m680x_detail.c @@ -0,0 +1,137 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +static const char *s_access[] = { + "UNCHANGED", "READ", "WRITE", "READ ; WRITE", +}; + +static void print_read_write_regs(char *result, csh *handle, cs_detail *detail) +{ + int i; + + if (detail->regs_read_count > 0) { + add_str(&result, "\treading from regs: "); + + for (i = 0; i < detail->regs_read_count; ++i) { + if (i > 0) + add_str(&result, ", "); + + add_str(&result, "%s", cs_reg_name(*handle, detail->regs_read[i])); + } + } + + if (detail->regs_write_count > 0) { + add_str(&result, "\twriting to regs: "); + + for (i = 0; i < detail->regs_write_count; ++i) { + if (i > 0) + add_str(&result, ", "); + + add_str(&result, "%s", cs_reg_name(*handle, detail->regs_write[i])); + } + } +} + +char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn) +{ + cs_detail *detail = insn->detail; + cs_m680x *m680x = NULL; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (detail == NULL) + return result; + + m680x = &detail->m680x; + + if (m680x->op_count) + add_str(&result, " ; op_count: %u", m680x->op_count); + + for (i = 0; i < m680x->op_count; i++) { + cs_m680x_op *op = &(m680x->operands[i]); + const char *comment; + + switch ((int)op->type) { + default: + break; + + case M680X_OP_REGISTER: + comment = ""; + + if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) || + (i == 1 && m680x->flags & + M680X_SECOND_OP_IN_MNEM)) + comment = " (in mnemonic)"; + + add_str(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment); + break; + + case M680X_OP_CONSTANT: + add_str(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val); + break; + + case M680X_OP_IMMEDIATE: + add_str(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm); + break; + + case M680X_OP_DIRECT: + add_str(&result, " ; operands[%u].type: DIRECT = 0x%02X", i, op->direct_addr); + break; + + case M680X_OP_EXTENDED: + add_str(&result, " ; operands[%u].type: EXTENDED %s = 0x%04X", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address); + break; + + case M680X_OP_RELATIVE: + add_str(&result, " ; operands[%u].type: RELATIVE = 0x%04X", i, op->rel.address); + break; + + case M680X_OP_INDEXED: + add_str(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : ""); + + if (op->idx.base_reg != M680X_REG_INVALID) + add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg)); + + if (op->idx.offset_reg != M680X_REG_INVALID) + add_str(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg)); + + if ((op->idx.offset_bits != 0) && + (op->idx.offset_reg == M680X_REG_INVALID) && + !op->idx.inc_dec) { + add_str(&result, " ; offset: %d", op->idx.offset); + + if (op->idx.base_reg == M680X_REG_PC) + add_str(&result, " ; offset address: 0x%X", op->idx.offset_addr); + + add_str(&result, " ; offset bits: %u", op->idx.offset_bits); + } + + if (op->idx.inc_dec) { + const char *post_pre = op->idx.flags & + M680X_IDX_POST_INC_DEC ? "post" : "pre"; + const char *inc_dec = (op->idx.inc_dec > 0) ? + "increment" : "decrement"; + + add_str(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec)); + } + + break; + } + + if (op->size != 0) + add_str(&result, " ; size: %u", op->size); + + if (op->access != CS_AC_INVALID) + add_str(&result, " ; access: %s", s_access[op->access]); + } + + print_read_write_regs(result, handle, detail); + + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/m68k_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/m68k_detail.c new file mode 100644 index 0000000..a3dfc74 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/m68k_detail.c @@ -0,0 +1,116 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +static const char* s_addressing_modes[] = { + "", + + "Register Direct - Data", + "Register Direct - Address", + + "Register Indirect - Address", + "Register Indirect - Address with Postincrement", + "Register Indirect - Address with Predecrement", + "Register Indirect - Address with Displacement", + + "Address Register Indirect With Index - 8-bit displacement", + "Address Register Indirect With Index - Base displacement", + + "Memory indirect - Postindex", + "Memory indirect - Preindex", + + "Program Counter Indirect - with Displacement", + + "Program Counter Indirect with Index - with 8-Bit Displacement", + "Program Counter Indirect with Index - with Base Displacement", + + "Program Counter Memory Indirect - Postindexed", + "Program Counter Memory Indirect - Preindexed", + + "Absolute Data Addressing - Short", + "Absolute Data Addressing - Long", + "Immediate value", +}; + +static void print_read_write_regs(char *result, cs_detail* detail, csh *handle) +{ + int i; + + for (i = 0; i < detail->regs_read_count; ++i) { + uint16_t reg_id = detail->regs_read[i]; + const char* reg_name = cs_reg_name(*handle, reg_id); + add_str(&result, " ; reading from reg: %s", reg_name); + } + + for (i = 0; i < detail->regs_write_count; ++i) { + uint16_t reg_id = detail->regs_write[i]; + const char* reg_name = cs_reg_name(*handle, reg_id); + add_str(&result, " ; writing to reg: %s", reg_name); + } +} + +char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_m68k* m68k; + cs_detail* detail; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + + detail = ins->detail; + m68k = &detail->m68k; + if (m68k->op_count) + add_str(&result, " ; op_count: %u", m68k->op_count); + + print_read_write_regs(result, detail, handle); + + add_str(&result, " ; groups_count: %u", detail->groups_count); + + for (i = 0; i < m68k->op_count; i++) { + cs_m68k_op* op = &(m68k->operands[i]); + + switch((int)op->type) { + default: + break; + case M68K_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case M68K_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm); + break; + case M68K_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base_reg != M68K_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg)); + if (op->mem.index_reg != M68K_REG_INVALID) { + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg)); + add_str(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w'); + } + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + if (op->mem.scale != 0) + add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); + + add_str(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]); + break; + case M68K_OP_FP_SINGLE: + add_str(&result, " ; operands[%u].type: FP_SINGLE", i); + add_str(&result, " ; operands[%u].simm: %f", i, op->simm); + break; + case M68K_OP_FP_DOUBLE: + add_str(&result, " ; operands[%u].type: FP_DOUBLE", i); + add_str(&result, " ; operands[%u].dimm: %lf", i, op->dimm); + break; + } + } + + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/main.c b/white_patch_detect/capstone-master/suite/cstest/src/main.c new file mode 100644 index 0000000..fc706d6 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/main.c @@ -0,0 +1,352 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "helper.h" +#include "capstone_test.h" +#include + +static int counter; +static char **list_lines; +static int failed_setup; +static int size_lines; +static cs_mode issue_mode; +static int getDetail; +static int mc_mode; +static int e_flag; + +static int setup_MC(void **state) +{ + csh *handle; + char **list_params; + int size_params; + int arch, mode; + int i, index, tmp_counter; + + if (failed_setup) { + fprintf(stderr, "[ ERROR ] --- Invalid file to setup\n"); + return -1; + } + + tmp_counter = 0; + while (tmp_counter < size_lines && list_lines[tmp_counter][0] != '#') + tmp_counter++; + + list_params = split(list_lines[tmp_counter] + 2, ", ", &size_params); + if (size_params != 3) { + fprintf(stderr, "[ ERROR ] --- Invalid options ( arch, mode, option )\n"); + failed_setup = 1; + return -1; + } + + arch = get_value(arches, NUMARCH, list_params[0]); + if (!strcmp(list_params[0], "CS_ARCH_ARM64")) + mc_mode = 2; + else + mc_mode = 1; + + mode = 0; + for (i = 0; i < NUMMODE; ++i) { + if (strstr(list_params[1], modes[i].str)) { + mode += modes[i].value; + switch (modes[i].value) { + case CS_MODE_16: + mc_mode = 0; + break; + case CS_MODE_64: + mc_mode = 2; + break; + case CS_MODE_THUMB: + mc_mode = 1; + break; + default: + break; + } + } + } + + if (arch == -1) { + fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); + failed_setup = 1; + return -1; + } + + handle = (csh *)malloc(sizeof(csh)); + if(cs_open(arch, mode, handle) != CS_ERR_OK) { + fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); + failed_setup = 1; + return -1; + } + + for (i = 0; i < NUMOPTION; ++i) { + if (strstr(list_params[2], options[i].str)) { + if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { + fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); + failed_setup = 1; + return -1; + } + } + } + + *state = (void *)handle; + counter++; + if (e_flag == 0) + while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) + counter++; + else + while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) + counter++; + + free_strs(list_params, size_params); + return 0; +} + +static void test_MC(void **state) +{ + if (e_flag == 1) + test_single_MC((csh *)*state, mc_mode, list_lines[counter] + 3); + else + test_single_MC((csh *)*state, mc_mode, list_lines[counter]); +} + +static int teardown_MC(void **state) +{ + cs_close(*state); + free(*state); + return 0; +} + +static int setup_issue(void **state) +{ + csh *handle; + char **list_params; + int size_params; + int arch, mode; + int i, index, result; + char *(*function)(csh *, cs_mode, cs_insn*); + + getDetail = 0; + failed_setup = 0; + + if (e_flag == 0) + while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) + counter++; // get issue line + else + while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) + counter++; + + counter++; + if (e_flag == 0) + while (counter < size_lines && strncmp(list_lines[counter], "!#", 2)) + counter++; // get arch line + else + while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) + counter++; + + if (e_flag == 0) + list_params = split(list_lines[counter] + 3, ", ", &size_params); + else + list_params = split(list_lines[counter] + 6, ", ", &size_params); + + arch = get_value(arches, NUMARCH, list_params[0]); + + if (!strcmp(list_params[0], "CS_ARCH_ARM64")) + mc_mode = 2; + else + mc_mode = 1; + + mode = 0; + for (i = 0; i < NUMMODE; ++i) { + if (strstr(list_params[1], modes[i].str)) { + mode += modes[i].value; + switch (modes[i].value) { + case CS_MODE_16: + mc_mode = 0; + break; + case CS_MODE_64: + mc_mode = 2; + break; + case CS_MODE_THUMB: + mc_mode = 1; + break; + default: + break; + } + } + } + + if (arch == -1) { + fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); + failed_setup = 1; + return -1; + } + + handle = (csh *)calloc(1, sizeof(csh)); + if(cs_open(arch, mode, handle) != CS_ERR_OK) { + fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); + failed_setup = 1; + return -1; + } + + for (i = 0; i < NUMOPTION; ++i) { + if (strstr(list_params[2], options[i].str)) { + if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { + fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); + failed_setup = 1; + return -1; + } + + if (i == 0) { + result = set_function(arch); + if (result == -1) { + fprintf(stderr, "[ ERROR ] --- Cannot get details\n"); + failed_setup = 1; + return -1; + } + + getDetail = 1; + } + } + } + + *state = (void *)handle; + issue_mode = mode; + + if (e_flag == 0) + while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) + counter++; + else + while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) + counter++; + + free_strs(list_params, size_params); + return 0; +} + +static void test_issue(void **state) +{ + if (e_flag == 0) + test_single_issue((csh *)*state, issue_mode, list_lines[counter], getDetail); + else + test_single_issue((csh *)*state, issue_mode, list_lines[counter] + 3, getDetail); + + return; +} + +static int teardown_issue(void **state) +{ + if (e_flag == 0) + while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) + counter++; + else + while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) + counter++; + + cs_close(*state); + free(*state); + function = NULL; + return 0; +} + +static void test_file(const char *filename) +{ + int size, i; + char **list_str; + char *content, *tmp; + struct CMUnitTest *tests; + int issue_num, number_of_tests; + + printf("[+] TARGET: %s\n", filename); + content = readfile(filename); + counter = 0; + failed_setup = 0; + function = NULL; + + if (strstr(filename, "issue")) { + number_of_tests = 0; + list_lines = split(content, "\n", &size_lines); + tests = NULL; + for (i = 0; i < size_lines; ++i) { + if ((!strncmp(list_lines[i], "// !# issue", 11) && e_flag == 1) || + (!strncmp(list_lines[i], "!# issue", 8) && e_flag == 0)) { + tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); + tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_issue, setup_issue, teardown_issue); + tests[number_of_tests].name = strdup(list_lines[i]); + number_of_tests ++; + } + } + + _cmocka_run_group_tests("Testing issues", tests, number_of_tests, NULL, NULL); + } else { + list_lines = split(content, "\n", &size_lines); + number_of_tests = 0; + + tests = NULL; + for (i = 1; i < size_lines; ++i) { + if ((!strncmp(list_lines[i], "// 0x", 5) && e_flag == 1) || (!strncmp(list_lines[i], "0x", 2) && e_flag == 0)) { + tmp = (char *)malloc(sizeof(char) * 100); + sprintf(tmp, "Line %d", i+1); + tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); + tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, teardown_MC); + tests[number_of_tests].name = tmp; + number_of_tests ++; + } + } + + _cmocka_run_group_tests("Testing MC", tests, number_of_tests, NULL, NULL); + } + + printf("[+] DONE: %s\n", filename); + printf("[!] Noted:\n[ ERROR ] --- \"\" != \"\"\n"); + printf("\n\n"); + free_strs(list_lines, size_lines); +} + +static void test_folder(const char *folder) +{ + char **files; + int num_files, i; + + files = NULL; + num_files = 0; + listdir(folder, &files, &num_files); + for (i = 0; i < num_files; ++i) { + if (strcmp("cs", get_filename_ext(files[i]))) + continue; + test_file(files[i]); + } +} + +int main(int argc, char *argv[]) +{ + int opt, flag; + + flag = 0; + e_flag = 0; + + while ((opt = getopt(argc, argv, "ef:d:")) > 0) { + switch (opt) { + case 'f': + test_file(optarg); + flag = 1; + break; + case 'd': + test_folder(optarg); + flag = 1; + break; + case 'e': + e_flag = 1; + break; + default: + printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); + exit(-1); + } + } + + if (flag == 0) { + printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); + exit(-1); + } + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/mips_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/mips_detail.c new file mode 100644 index 0000000..c859ab6 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/mips_detail.c @@ -0,0 +1,48 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins) +{ + int i; + cs_mips *mips; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + mips = &(ins->detail->mips); + if (mips->op_count) + add_str(&result, " ; op_count: %u", mips->op_count); + + for (i = 0; i < mips->op_count; i++) { + cs_mips_op *op = &(mips->operands[i]); + switch((int)op->type) { + default: + break; + case MIPS_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case MIPS_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + break; + case MIPS_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != MIPS_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); + + break; + } + + } + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/mos65xx_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/mos65xx_detail.c new file mode 100644 index 0000000..ba5c51e --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/mos65xx_detail.c @@ -0,0 +1,79 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +static const char *get_am_name(mos65xx_address_mode mode) +{ + switch(mode) { + default: + case MOS65XX_AM_NONE: + return "No address mode"; + case MOS65XX_AM_IMP: + return "implied addressing (no addressing mode)"; + case MOS65XX_AM_ACC: + return "accumulator addressing"; + case MOS65XX_AM_ABS: + return "absolute addressing"; + case MOS65XX_AM_ZP: + return "zeropage addressing"; + case MOS65XX_AM_IMM: + return "8 Bit immediate value"; + case MOS65XX_AM_ABSX: + return "indexed absolute addressing by the X index register"; + case MOS65XX_AM_ABSY: + return "indexed absolute addressing by the Y index register"; + case MOS65XX_AM_INDX: + return "indexed indirect addressing by the X index register"; + case MOS65XX_AM_INDY: + return "indirect indexed addressing by the Y index register"; + case MOS65XX_AM_ZPX: + return "indexed zeropage addressing by the X index register"; + case MOS65XX_AM_ZPY: + return "indexed zeropage addressing by the Y index register"; + case MOS65XX_AM_REL: + return "relative addressing used by branches"; + case MOS65XX_AM_IND: + return "absolute indirect addressing"; + } +} + + +char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins) +{ + int i; + cs_mos65xx *mos65xx; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + mos65xx = &(ins->detail->mos65xx); + add_str(&result, " ; address mode: %s", get_am_name(mos65xx->am)); + add_str(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false"); + + if (mos65xx->op_count) + add_str(&result, " ; op_count: %u", mos65xx->op_count); + + for (i = 0; i < mos65xx->op_count; i++) { + cs_mos65xx_op *op = &(mos65xx->operands[i]); + switch((int)op->type) { + default: + break; + case MOS65XX_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case MOS65XX_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); + break; + case MOS65XX_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem); + break; + } + } + return result; +} diff --git a/white_patch_detect/capstone-master/suite/cstest/src/ppc_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/ppc_detail.c new file mode 100644 index 0000000..7a2ab88 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/ppc_detail.c @@ -0,0 +1,91 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +static const char* get_bc_name(int bc) +{ + switch(bc) { + default: + case PPC_BC_INVALID: + return ("invalid"); + case PPC_BC_LT: + return ("lt"); + case PPC_BC_LE: + return ("le"); + case PPC_BC_EQ: + return ("eq"); + case PPC_BC_GE: + return ("ge"); + case PPC_BC_GT: + return ("gt"); + case PPC_BC_NE: + return ("ne"); + case PPC_BC_UN: + return ("un"); + case PPC_BC_NU: + return ("nu"); + case PPC_BC_SO: + return ("so"); + case PPC_BC_NS: + return ("ns"); + } +} + +char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_ppc *ppc; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + ppc = &(ins->detail->ppc); + if (ppc->op_count) + add_str(&result, " ; op_count: %u", ppc->op_count); + + for (i = 0; i < ppc->op_count; i++) { + cs_ppc_op *op = &(ppc->operands[i]); + switch((int)op->type) { + default: + break; + case PPC_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case PPC_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm); + break; + case PPC_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != PPC_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + + break; + case PPC_OP_CRX: + add_str(&result, " ; operands[%u].type: CRX", i); + add_str(&result, " ; operands[%u].crx.scale: %d", i, op->crx.scale); + add_str(&result, " ; operands[%u].crx.reg: %s", i, cs_reg_name(*handle, op->crx.reg)); + add_str(&result, " ; operands[%u].crx.cond: %s", i, get_bc_name(op->crx.cond)); + break; + } + } + + if (ppc->bc != 0) + add_str(&result, " ; Branch code: %u", ppc->bc); + + if (ppc->bh != 0) + add_str(&result, " ; Branch hint: %u", ppc->bh); + + if (ppc->update_cr0) + add_str(&result, " ; Update-CR0: True"); + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/sparc_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/sparc_detail.c new file mode 100644 index 0000000..54c6bb4 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/sparc_detail.c @@ -0,0 +1,55 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_sparc *sparc; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + sparc = &(ins->detail->sparc); + if (sparc->op_count) + add_str(&result, " ; op_count: %u", sparc->op_count); + + for (i = 0; i < sparc->op_count; i++) { + cs_sparc_op *op = &(sparc->operands[i]); + switch((int)op->type) { + default: + break; + case SPARC_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case SPARC_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + break; + case SPARC_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != X86_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + + break; + } + } + + if (sparc->cc != 0) + add_str(&result, " ; Code condition: %u", sparc->cc); + + if (sparc->hint != 0) + add_str(&result, " ; Hint code: %u", sparc->hint); + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/systemz_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/systemz_detail.c new file mode 100644 index 0000000..b9d24a0 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/systemz_detail.c @@ -0,0 +1,57 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_sysz *sysz; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + sysz = &(ins->detail->sysz); + if (sysz->op_count) + add_str(&result, " ; op_count: %u", sysz->op_count); + + for (i = 0; i < sysz->op_count; i++) { + cs_sysz_op *op = &(sysz->operands[i]); + switch((int)op->type) { + default: + break; + case SYSZ_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case SYSZ_OP_ACREG: + add_str(&result, " ; operands[%u].type: ACREG = %u", i, op->reg); + break; + case SYSZ_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + break; + case SYSZ_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != SYSZ_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.index != SYSZ_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); + if (op->mem.length != 0) + add_str(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); + + break; + } + } + + if (sysz->cc != 0) + add_str(&result, " ; Code condition: %u", sysz->cc); + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/tms320c64x_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/tms320c64x_detail.c new file mode 100644 index 0000000..f6b0b91 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/tms320c64x_detail.c @@ -0,0 +1,107 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_tms320c64x *tms320c64x; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + tms320c64x = &(ins->detail->tms320c64x); + if (tms320c64x->op_count) + add_str(&result, " ; op_count: %u", tms320c64x->op_count); + + for (i = 0; i < tms320c64x->op_count; i++) { + cs_tms320c64x_op *op = &(tms320c64x->operands[i]); + switch((int)op->type) { + default: + break; + case TMS320C64X_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case TMS320C64X_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); + break; + case TMS320C64X_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != TMS320C64X_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + add_str(&result, " ; operands[%u].mem.disptype: ", i); + if (op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { + add_str(&result, "Invalid"); + add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); + } + if (op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { + add_str(&result, "Constant"); + add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); + } + if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { + add_str(&result, "Register"); + add_str(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp)); + } + add_str(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit); + add_str(&result, " ; operands[%u].mem.direction: ", i); + if (op->mem.direction == TMS320C64X_MEM_DIR_INVALID) + add_str(&result, "Invalid"); + if (op->mem.direction == TMS320C64X_MEM_DIR_FW) + add_str(&result, "Forward"); + if (op->mem.direction == TMS320C64X_MEM_DIR_BW) + add_str(&result, "Backward"); + add_str(&result, " ; operands[%u].mem.modify: ", i); + if (op->mem.modify == TMS320C64X_MEM_MOD_INVALID) + add_str(&result, "Invalid"); + if (op->mem.modify == TMS320C64X_MEM_MOD_NO) + add_str(&result, "No"); + if (op->mem.modify == TMS320C64X_MEM_MOD_PRE) + add_str(&result, "Pre"); + if (op->mem.modify == TMS320C64X_MEM_MOD_POST) + add_str(&result, "Post"); + add_str(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled); + + break; + case TMS320C64X_OP_REGPAIR: + add_str(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg)); + break; + } + } + + add_str(&result, " ; Functional unit: "); + switch(tms320c64x->funit.unit) { + case TMS320C64X_FUNIT_D: + add_str(&result, "D%u", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_L: + add_str(&result, "L%u", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_M: + add_str(&result, "M%u", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_S: + add_str(&result, "S%u", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_NO: + add_str(&result, "No Functional Unit"); + break; + default: + add_str(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side); + break; + } + if (tms320c64x->funit.crosspath == 1) + add_str(&result, " ; Crosspath: 1"); + + if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) + add_str(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg)); + add_str(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false"); + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/x86_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/x86_detail.c new file mode 100644 index 0000000..f545687 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/x86_detail.c @@ -0,0 +1,344 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +static void print_string_hex(char **result, const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + add_str(result, "%s", comment); + for (c = str; c < str + len; c++) { + add_str(result, "0x%02x", *c & 0xff); + if (c < str + len - 1) + add_str(result, " "); + } + +} + +static const char *get_eflag_name(uint64_t flag) +{ + switch(flag) { + default: + return NULL; + case X86_EFLAGS_UNDEFINED_OF: + return "UNDEF_OF"; + case X86_EFLAGS_UNDEFINED_SF: + return "UNDEF_SF"; + case X86_EFLAGS_UNDEFINED_ZF: + return "UNDEF_ZF"; + case X86_EFLAGS_MODIFY_AF: + return "MOD_AF"; + case X86_EFLAGS_UNDEFINED_PF: + return "UNDEF_PF"; + case X86_EFLAGS_MODIFY_CF: + return "MOD_CF"; + case X86_EFLAGS_MODIFY_SF: + return "MOD_SF"; + case X86_EFLAGS_MODIFY_ZF: + return "MOD_ZF"; + case X86_EFLAGS_UNDEFINED_AF: + return "UNDEF_AF"; + case X86_EFLAGS_MODIFY_PF: + return "MOD_PF"; + case X86_EFLAGS_UNDEFINED_CF: + return "UNDEF_CF"; + case X86_EFLAGS_MODIFY_OF: + return "MOD_OF"; + case X86_EFLAGS_RESET_OF: + return "RESET_OF"; + case X86_EFLAGS_RESET_CF: + return "RESET_CF"; + case X86_EFLAGS_RESET_DF: + return "RESET_DF"; + case X86_EFLAGS_RESET_IF: + return "RESET_IF"; + case X86_EFLAGS_RESET_ZF: + return "RESET_ZF"; + case X86_EFLAGS_TEST_OF: + return "TEST_OF"; + case X86_EFLAGS_TEST_SF: + return "TEST_SF"; + case X86_EFLAGS_TEST_ZF: + return "TEST_ZF"; + case X86_EFLAGS_TEST_PF: + return "TEST_PF"; + case X86_EFLAGS_TEST_CF: + return "TEST_CF"; + case X86_EFLAGS_RESET_SF: + return "RESET_SF"; + case X86_EFLAGS_RESET_AF: + return "RESET_AF"; + case X86_EFLAGS_RESET_TF: + return "RESET_TF"; + case X86_EFLAGS_RESET_NT: + return "RESET_NT"; + case X86_EFLAGS_PRIOR_OF: + return "PRIOR_OF"; + case X86_EFLAGS_PRIOR_SF: + return "PRIOR_SF"; + case X86_EFLAGS_PRIOR_ZF: + return "PRIOR_ZF"; + case X86_EFLAGS_PRIOR_AF: + return "PRIOR_AF"; + case X86_EFLAGS_PRIOR_PF: + return "PRIOR_PF"; + case X86_EFLAGS_PRIOR_CF: + return "PRIOR_CF"; + case X86_EFLAGS_PRIOR_TF: + return "PRIOR_TF"; + case X86_EFLAGS_PRIOR_IF: + return "PRIOR_IF"; + case X86_EFLAGS_PRIOR_DF: + return "PRIOR_DF"; + case X86_EFLAGS_TEST_NT: + return "TEST_NT"; + case X86_EFLAGS_TEST_DF: + return "TEST_DF"; + case X86_EFLAGS_RESET_PF: + return "RESET_PF"; + case X86_EFLAGS_PRIOR_NT: + return "PRIOR_NT"; + case X86_EFLAGS_MODIFY_TF: + return "MOD_TF"; + case X86_EFLAGS_MODIFY_IF: + return "MOD_IF"; + case X86_EFLAGS_MODIFY_DF: + return "MOD_DF"; + case X86_EFLAGS_MODIFY_NT: + return "MOD_NT"; + case X86_EFLAGS_MODIFY_RF: + return "MOD_RF"; + case X86_EFLAGS_SET_CF: + return "SET_CF"; + case X86_EFLAGS_SET_DF: + return "SET_DF"; + case X86_EFLAGS_SET_IF: + return "SET_IF"; + case X86_EFLAGS_SET_OF: + return "SET_OF"; + case X86_EFLAGS_SET_SF: + return "SET_SF"; + case X86_EFLAGS_SET_ZF: + return "SET_ZF"; + case X86_EFLAGS_SET_AF: + return "SET_AF"; + case X86_EFLAGS_SET_PF: + return "SET_PF"; + case X86_EFLAGS_TEST_AF: + return "TEST_AF"; + case X86_EFLAGS_TEST_TF: + return "TEST_TF"; + case X86_EFLAGS_TEST_RF: + return "TEST_RF"; + case X86_EFLAGS_RESET_0F: + return "RESET_0F"; + case X86_EFLAGS_RESET_AC: + return "RESET_AC"; + } +} + +static const char *get_fpu_flag_name(uint64_t flag) +{ + switch (flag) { + default: + return NULL; + case X86_FPU_FLAGS_MODIFY_C0: + return "MOD_C0"; + case X86_FPU_FLAGS_MODIFY_C1: + return "MOD_C1"; + case X86_FPU_FLAGS_MODIFY_C2: + return "MOD_C2"; + case X86_FPU_FLAGS_MODIFY_C3: + return "MOD_C3"; + case X86_FPU_FLAGS_RESET_C0: + return "RESET_C0"; + case X86_FPU_FLAGS_RESET_C1: + return "RESET_C1"; + case X86_FPU_FLAGS_RESET_C2: + return "RESET_C2"; + case X86_FPU_FLAGS_RESET_C3: + return "RESET_C3"; + case X86_FPU_FLAGS_SET_C0: + return "SET_C0"; + case X86_FPU_FLAGS_SET_C1: + return "SET_C1"; + case X86_FPU_FLAGS_SET_C2: + return "SET_C2"; + case X86_FPU_FLAGS_SET_C3: + return "SET_C3"; + case X86_FPU_FLAGS_UNDEFINED_C0: + return "UNDEF_C0"; + case X86_FPU_FLAGS_UNDEFINED_C1: + return "UNDEF_C1"; + case X86_FPU_FLAGS_UNDEFINED_C2: + return "UNDEF_C2"; + case X86_FPU_FLAGS_UNDEFINED_C3: + return "UNDEF_C3"; + case X86_FPU_FLAGS_TEST_C0: + return "TEST_C0"; + case X86_FPU_FLAGS_TEST_C1: + return "TEST_C1"; + case X86_FPU_FLAGS_TEST_C2: + return "TEST_C2"; + case X86_FPU_FLAGS_TEST_C3: + return "TEST_C3"; + } +} + +char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins) +{ + int count, i; + cs_x86 *x86; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + x86 = &(ins->detail->x86); + + print_string_hex(&result, " ; Prefix:", x86->prefix, 4); + print_string_hex(&result, " ; Opcode:", x86->opcode, 4); + add_str(&result, " ; rex: 0x%x", x86->rex); + add_str(&result, " ; addr_size: %u", x86->addr_size); + add_str(&result, " ; modrm: 0x%x", x86->modrm); + add_str(&result, " ; disp: 0x%" PRIx64 "", x86->disp); + + if ((mode & CS_MODE_16) == 0) { + add_str(&result, " ; sib: 0x%x", x86->sib); + if (x86->sib_base != X86_REG_INVALID) + add_str(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base)); + if (x86->sib_index != X86_REG_INVALID) + add_str(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index)); + if (x86->sib_scale != 0) + add_str(&result, " ; sib_scale: %d", x86->sib_scale); + } + + if (x86->xop_cc != X86_XOP_CC_INVALID) { + add_str(&result, " ; xop_cc: %u", x86->xop_cc); + } + + if (x86->sse_cc != X86_SSE_CC_INVALID) { + add_str(&result, " ; sse_cc: %u", x86->sse_cc); + } + + if (x86->avx_cc != X86_AVX_CC_INVALID) { + add_str(&result, " ; avx_cc: %u", x86->avx_cc); + } + + if (x86->avx_sae) { + add_str(&result, " ; avx_sae: %u", x86->avx_sae); + } + + if (x86->avx_rm != X86_AVX_RM_INVALID) { + add_str(&result, " ; avx_rm: %u", x86->avx_rm); + } + + count = cs_op_count(*ud, ins, X86_OP_IMM); + if (count > 0) { + add_str(&result, " ; imm_count: %u", count); + for (i = 1; i < count + 1; i++) { + int index = cs_op_index(*ud, ins, X86_OP_IMM, i); + add_str(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm); + } + } + + if (x86->op_count) + add_str(&result, " ; op_count: %u", x86->op_count); + + for (i = 0; i < x86->op_count; i++) { + cs_x86_op *op = &(x86->operands[i]); + + switch((int)op->type) { + case X86_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg)); + break; + case X86_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + break; + case X86_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.segment != X86_REG_INVALID) + add_str(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment)); + if (op->mem.base != X86_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index)); + if (op->mem.scale != 1) + add_str(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); + break; + default: + break; + } + + if (op->avx_bcast != X86_AVX_BCAST_INVALID) + add_str(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast); + + if (op->avx_zero_opmask != false) + add_str(&result, " ; operands[%u].avx_zero_opmask: TRUE", i); + + add_str(&result, " ; operands[%u].size: %u", i, op->size); + + switch(op->access) { + default: + break; + case CS_AC_READ: + add_str(&result, " ; operands[%u].access: READ", i); + break; + case CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: WRITE", i); + break; + case CS_AC_READ | CS_AC_WRITE: + add_str(&result, " ; operands[%u].access: READ | WRITE", i); + break; + } + } + + if (!cs_regs_access(*ud, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, " ; Registers read:"); + for(i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", cs_reg_name(*ud, regs_read[i])); + } + } + + if (regs_write_count) { + add_str(&result, " ; Registers modified:"); + for(i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", cs_reg_name(*ud, regs_write[i])); + } + } + } + + if (x86->eflags || x86->fpu_flags) { + for(i = 0; i < ins->detail->groups_count; i++) { + if (ins->detail->groups[i] == X86_GRP_FPU) { + add_str(&result, " ; FPU_FLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->fpu_flags & ((uint64_t)1 << i)) { + add_str(&result, " %s", get_fpu_flag_name((uint64_t)1 << i)); + } + break; + } + } + + if (i == ins->detail->groups_count) { + add_str(&result, " ; EFLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->eflags & ((uint64_t)1 << i)) { + add_str(&result, " %s", get_eflag_name((uint64_t)1 << i)); + } + } + } + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/cstest/src/xcore_detail.c b/white_patch_detect/capstone-master/suite/cstest/src/xcore_detail.c new file mode 100644 index 0000000..d4f51f8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/cstest/src/xcore_detail.c @@ -0,0 +1,52 @@ +/* Capstone testing regression */ +/* By Do Minh Tuan , 02-2019 */ + + +#include "factory.h" + +char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins) +{ + cs_xcore *xcore; + int i; + char *result; + + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + xcore = &(ins->detail->xcore); + if (xcore->op_count) + add_str(&result, " ; op_count: %u", xcore->op_count); + + for (i = 0; i < xcore->op_count; i++) { + cs_xcore_op *op = &(xcore->operands[i]); + switch((int)op->type) { + default: + break; + case XCORE_OP_REG: + add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); + break; + case XCORE_OP_IMM: + add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); + break; + case XCORE_OP_MEM: + add_str(&result, " ; operands[%u].type: MEM", i); + if (op->mem.base != XCORE_REG_INVALID) + add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); + if (op->mem.index != XCORE_REG_INVALID) + add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); + if (op->mem.disp != 0) + add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); + if (op->mem.direct != 1) + add_str(&result, " ; operands[%u].mem.direct: -1", i); + + + break; + } + } + + return result; +} + diff --git a/white_patch_detect/capstone-master/suite/disasm_mc.py b/white_patch_detect/capstone-master/suite/disasm_mc.py new file mode 100644 index 0000000..ff5875a --- /dev/null +++ b/white_patch_detect/capstone-master/suite/disasm_mc.py @@ -0,0 +1,188 @@ +#!/usr/bin/python +# Test tool to disassemble MC files. By Nguyen Anh Quynh, 2017 +import array, os.path, sys +from capstone import * + + +# convert all hex numbers to decimal numbers in a text +def normalize_hex(a): + while(True): + i = a.find('0x') + if i == -1: # no more hex number + break + hexnum = '0x' + for c in a[i + 2:]: + if c in '0123456789abcdefABCDEF': + hexnum += c + else: + break + num = int(hexnum, 16) + a = a.replace(hexnum, str(num)) + return a + + +def test_file(fname): + print("Test %s" %fname); + f = open(fname) + lines = f.readlines() + f.close() + + if not lines[0].startswith('# '): + print("ERROR: decoding information is missing") + return + + # skip '# ' at the front, then split line to get out hexcode + # Note: option can be '', or 'None' + #print lines[0] + #print lines[0][2:].split(', ') + (arch, mode, option) = lines[0][2:].split(', ') + mode = mode.replace(' ', '') + option = option.strip() + + archs = { + "CS_ARCH_ARM": CS_ARCH_ARM, + "CS_ARCH_ARM64": CS_ARCH_ARM64, + "CS_ARCH_MIPS": CS_ARCH_MIPS, + "CS_ARCH_PPC": CS_ARCH_PPC, + "CS_ARCH_SPARC": CS_ARCH_SPARC, + "CS_ARCH_SYSZ": CS_ARCH_SYSZ, + "CS_ARCH_X86": CS_ARCH_X86, + "CS_ARCH_XCORE": CS_ARCH_XCORE, + "CS_ARCH_M68K": CS_ARCH_M68K, + } + + modes = { + "CS_MODE_16": CS_MODE_16, + "CS_MODE_32": CS_MODE_32, + "CS_MODE_64": CS_MODE_64, + "CS_MODE_MIPS32": CS_MODE_MIPS32, + "CS_MODE_MIPS64": CS_MODE_MIPS64, + "0": CS_MODE_ARM, + "CS_MODE_ARM": CS_MODE_ARM, + "CS_MODE_THUMB": CS_MODE_THUMB, + "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, + "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, + "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, + "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, + "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, + } + + options = { + "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT, + "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME, + } + + mc_modes = { + ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'], + ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'], + ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'], + ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'], + ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'], + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'], + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'], + ("CS_ARCH_ARM64", "0"): ['-triple=aarch64'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'], + ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'], + ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'], + ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'], + ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'], + } + + #if not option in ('', 'None'): + # print archs[arch], modes[mode], options[option] + + #print(arch, mode, option) + md = Cs(archs[arch], modes[mode]) + + if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' : + md.syntax = CS_OPT_SYNTAX_NOREGNAME + + if fname.endswith('3DNow.s.cs'): + md.syntax = CS_OPT_SYNTAX_ATT + + for line in lines[1:]: + # ignore all the input lines having # in front. + if line.startswith('#'): + continue + #print("Check %s" %line) + code = line.split(' = ')[0] + asm = ''.join(line.split(' = ')[1:]) + hex_code = code.replace('0x', '') + hex_code = hex_code.replace(',', '') + hex_data = hex_code.decode('hex') + #hex_bytes = array.array('B', hex_data) + + x = list(md.disasm(hex_data, 0)) + if len(x) > 0: + if x[0].op_str != '': + cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str) + else: + cs_output = x[0].mnemonic + else: + cs_output = 'FAILED to disassemble' + + cs_output2 = normalize_hex(cs_output) + cs_output2 = cs_output2.replace(' ', '') + + if arch == 'CS_ARCH_MIPS': + # normalize register alias names + cs_output2 = cs_output2.replace('$at', '$1') + cs_output2 = cs_output2.replace('$v0', '$2') + cs_output2 = cs_output2.replace('$v1', '$3') + + cs_output2 = cs_output2.replace('$a0', '$4') + cs_output2 = cs_output2.replace('$a1', '$5') + cs_output2 = cs_output2.replace('$a2', '$6') + cs_output2 = cs_output2.replace('$a3', '$7') + + cs_output2 = cs_output2.replace('$t0', '$8') + cs_output2 = cs_output2.replace('$t1', '$9') + cs_output2 = cs_output2.replace('$t2', '$10') + cs_output2 = cs_output2.replace('$t3', '$11') + cs_output2 = cs_output2.replace('$t4', '$12') + cs_output2 = cs_output2.replace('$t5', '$13') + cs_output2 = cs_output2.replace('$t6', '$14') + cs_output2 = cs_output2.replace('$t7', '$15') + cs_output2 = cs_output2.replace('$t8', '$24') + cs_output2 = cs_output2.replace('$t9', '$25') + + cs_output2 = cs_output2.replace('$s0', '$16') + cs_output2 = cs_output2.replace('$s1', '$17') + cs_output2 = cs_output2.replace('$s2', '$18') + cs_output2 = cs_output2.replace('$s3', '$19') + cs_output2 = cs_output2.replace('$s4', '$20') + cs_output2 = cs_output2.replace('$s5', '$21') + cs_output2 = cs_output2.replace('$s6', '$22') + cs_output2 = cs_output2.replace('$s7', '$23') + + cs_output2 = cs_output2.replace('$k0', '$26') + cs_output2 = cs_output2.replace('$k1', '$27') + + print("\t%s = %s" %(hex_code, cs_output)) + + +if __name__ == '__main__': + if len(sys.argv) == 1: + fnames = sys.stdin.readlines() + for fname in fnames: + test_file(fname.strip()) + else: + #print("Usage: ./test_mc.py ") + test_file(sys.argv[1]) + diff --git a/white_patch_detect/capstone-master/suite/disasm_mc.sh b/white_patch_detect/capstone-master/suite/disasm_mc.sh new file mode 100644 index 0000000..8de5a15 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/disasm_mc.sh @@ -0,0 +1,11 @@ +#!/bin/sh + +# This script test all architectures by default. + +find MC/ -name *.cs | ./disasm_mc.py + +# To test just one architecture, specify the corresponsing dir: +# $ find MC/X86 -name *.cs | ./disasm_mc.py + +# To test just one input file, run disasm_mc.py with that file: +# $ ./disasm_mc.py MC/X86/x86-32-fma3.s.cs diff --git a/white_patch_detect/capstone-master/suite/fuzz.py b/white_patch_detect/capstone-master/suite/fuzz.py new file mode 100644 index 0000000..8e0f329 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz.py @@ -0,0 +1,124 @@ +#!/usr/bin/python + +# Simple fuzzing tool by disassembling random code. By Nguyen Anh Quynh, 2014 +# Syntax: +# ./suite/fuzz.py --> Fuzz all archs +# ./suite/fuzz.py x86 --> Fuzz all X86 (all 16bit, 32bit, 64bit) +# ./suite/fuzz.py x86-16 --> Fuzz X86-32 arch only +# ./suite/fuzz.py x86-32 --> Fuzz X86-32 arch only +# ./suite/fuzz.py x86-64 --> Fuzz X86-64 arch only +# ./suite/fuzz.py arm --> Fuzz all ARM (arm, thumb) +# ./suite/fuzz.py aarch64 --> Fuzz ARM-64 +# ./suite/fuzz.py mips --> Fuzz all Mips (32bit, 64bit) +# ./suite/fuzz.py ppc --> Fuzz PPC + +from capstone import * + +from time import time +from random import randint +import sys + + +# file providing code to disassemble +FILE = '/usr/bin/python' + +TIMES = 64 +INTERVALS = (4, 5, 7, 9, 11, 13) + +all_tests = ( + (CS_ARCH_X86, CS_MODE_16, "X86-16bit (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_16, "X86-16bit (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_64, "X86-64 (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0), + (CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0), + (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0), + (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0), + (CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0), + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME), + (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0), + (CS_ARCH_SYSZ, 0, "SystemZ", 0), + (CS_ARCH_XCORE, 0, "XCore", 0), + (CS_ARCH_M68K, 0, "M68K", 0), + ) + + +# for debugging +def to_hex(s): + return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK + + +# read @size bytes from @f & return data. +# return None when there is not enough data +def get_code(f, size): + code = f.read(size) + if len(code) != size: # reached end-of-file? + # then reset file position to begin-of-file + f.seek(0) + return None + + return code + + +def cs(md, code): + insns = md.disasm(code, 0) + for i in insns: + if i.address == 0x100000: + print i + + +def cs_lite(md, code): + insns = md.disasm_lite(code, 0) + for (addr, size, mnem, ops) in insns: + if addr == 0x100000: + print i + + +cfile = open(FILE) + +for (arch, mode, comment, syntax) in all_tests: + try: + request = sys.argv[1] + if not request in comment.lower(): + continue + except: + pass + + try: + md = Cs(arch, mode) + md.detail = True + + if syntax != 0: + md.syntax = syntax + + # test disasm() + print("\nFuzzing disasm() @platform: %s" %comment) + for ii in INTERVALS: + print("Interval: %u" %ii) + for j in xrange(1, TIMES): + while (True): + code = get_code(cfile, j * ii) + if code is None: + # EOF? break + break + #print to_hex(code) + cs(md, code) + + # test disasm_lite() + print("Fuzzing disasm_lite() @platform: %s" %comment) + for ii in INTERVALS: + print("Interval: %u" %ii) + for j in xrange(1, TIMES): + while (True): + code = get_code(cfile, j * ii) + if code is None: + # EOF? break + break + #print to_hex(code) + cs_lite(md, code) + + except CsError as e: + print("ERROR: %s" %e) diff --git a/white_patch_detect/capstone-master/suite/fuzz/Makefile b/white_patch_detect/capstone-master/suite/fuzz/Makefile new file mode 100644 index 0000000..3370df3 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/Makefile @@ -0,0 +1,85 @@ +# Capstone Disassembler Engine +# By Philippe Antoine , 2018 + +include ../../config.mk +include ../../functions.mk + +ifneq ($(CAPSTONE_STATIC),yes) +$(error Needs static capstone.) +endif + +# Verbose output? +V ?= 0 + +INCDIR = ../../include +ifndef BUILDDIR +TESTDIR = . +OBJDIR = . +LIBDIR = ../.. +else +TESTDIR = $(BUILDDIR)/tests +OBJDIR = $(BUILDDIR)/obj/tests +LIBDIR = $(BUILDDIR) +endif + +CFLAGS += -Wall -I$(INCDIR) +LDFLAGS += -L$(LIBDIR) + +CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) + +LIBNAME = capstone + +BIN_EXT = +AR_EXT = a + + +ARCHIVE = $(LIBDIR)/lib$(LIBNAME).$(AR_EXT) + +.PHONY: all clean + +SOURCES = fuzz_disasm.c drivermc.c fuzz_harness.c driverbin.c +OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) +BINARY = $(addprefix $(TESTDIR)/,fuzz_disasm$(BIN_EXT)) +BINARYBIN = $(addprefix $(TESTDIR)/,fuzz_bindisasm$(BIN_EXT)) + +all: $(BINARY) $(BINARYBIN) + +clean: + rm -rf fuzz_harness $(OBJS) $(BINARY) $(BINARYBIN) $(OBJDIR)/lib$(LIBNAME).* $(OBJDIR)/$(LIBNAME).* + +$(BINARY): fuzz_disasm.o drivermc.o + @mkdir -p $(@D) +ifeq ($(V),0) + $(call log,LINK,$(notdir $@)) + @$(link-static) +else + $(link-static) +endif + +$(BINARYBIN): fuzz_disasm.o driverbin.o + @mkdir -p $(@D) +ifeq ($(V),0) + $(call log,LINK,$(notdir $@)) + @$(link-static) +else + $(link-static) +endif + +$(OBJDIR)/%.o: %.c + @mkdir -p $(@D) +ifeq ($(V),0) + $(call log,CC,$(@:$(OBJDIR)/%=%)) + @$(compile) +else + $(compile) +endif + + + +define link-static + $(CC) $(LDFLAGS) $^ $(ARCHIVE) -o $@ +endef + +fuzz_harness: fuzz_harness.o + ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ diff --git a/white_patch_detect/capstone-master/suite/fuzz/README b/white_patch_detect/capstone-master/suite/fuzz/README new file mode 100644 index 0000000..0e63793 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/README @@ -0,0 +1,2 @@ +This directory contains a fuzz testing harness for Capstone. +Run "make" to compile this code. diff --git a/white_patch_detect/capstone-master/suite/fuzz/driverbin.c b/white_patch_detect/capstone-master/suite/fuzz/driverbin.c new file mode 100644 index 0000000..57eea2c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/driverbin.c @@ -0,0 +1,76 @@ +#include +#include +#include +#include +#include + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); + +int main(int argc, char** argv) +{ + FILE * fp; + uint8_t Data[0x1000]; + size_t Size; + DIR *d; + struct dirent *dir; + int r = 0; + + if (argc != 2) { + return 1; + } + + d = opendir(argv[1]); + if (d == NULL) { + printf("Invalid directory\n"); + return 2; + } + if (chdir(argv[1]) != 0) { + closedir(d); + printf("Invalid directory\n"); + return 2; + } + + while((dir = readdir(d)) != NULL) { + //opens the file, get its size, and reads it into a buffer + if (dir->d_type != DT_REG) { + continue; + } + //printf("Running %s\n", dir->d_name); + fp = fopen(dir->d_name, "rb"); + if (fp == NULL) { + r = 3; + break; + } + if (fseek(fp, 0L, SEEK_END) != 0) { + fclose(fp); + r = 4; + break; + } + Size = ftell(fp); + if (Size == (size_t) -1) { + fclose(fp); + r = 5; + break; + } else if (Size > 0x1000) { + fclose(fp); + continue; + } + if (fseek(fp, 0L, SEEK_SET) != 0) { + fclose(fp); + r = 7; + break; + } + if (fread(Data, Size, 1, fp) != 1) { + fclose(fp); + r = 8; + break; + } + + //lauch fuzzer + LLVMFuzzerTestOneInput(Data, Size); + fclose(fp); + } + closedir(d); + return r; +} + diff --git a/white_patch_detect/capstone-master/suite/fuzz/drivermc.c b/white_patch_detect/capstone-master/suite/fuzz/drivermc.c new file mode 100644 index 0000000..a6a0163 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/drivermc.c @@ -0,0 +1,130 @@ +#include +#include +#include +#include + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); + +#define MAX_INSTR_SIZE 64 +#define MAX_LINE_SIZE 128 + +int main(int argc, char** argv) +{ + FILE * fp; + uint8_t Data[MAX_INSTR_SIZE]; + char line[MAX_LINE_SIZE]; + size_t Size; + char arch[MAX_LINE_SIZE]; + char mode[MAX_LINE_SIZE]; + unsigned int value; + int i; + + if (argc < 2) { + return 1; + } + for (i = 1; i < argc; i++) { + //opens the file, get its size, and reads it into a buffer + fp = fopen(argv[i], "rb"); + if (fp == NULL) { + return 2; + } + printf("Trying %s\n", argv[i]); + if (fgets(line, MAX_LINE_SIZE, fp) == NULL) { + break; + } + if (line[0] == '#') { + if (sscanf(line, "# %[^,], %[^,]", arch, mode) != 2) { + printf("Wrong mode %s\n", line); + return 1; + } + if (strcmp(arch, "CS_ARCH_X86") == 0 && strcmp(mode, "CS_MODE_32") == 0) { + Data[0] = 0; + } else if (strcmp(arch, "CS_ARCH_X86") == 0 && strcmp(mode, "CS_MODE_64") == 0) { + Data[0] = 1; + } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_ARM") == 0) { + Data[0] = 2; + } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB") == 0) { + Data[0] = 3; + } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_ARM+CS_MODE_V8") == 0) { + Data[0] = 4; + } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB+CS_MODE_V8") == 0) { + Data[0] = 5; + } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB+CS_MODE_MCLASS") == 0) { + Data[0] = 6; + } else if (strcmp(arch, "CS_ARCH_ARM64") == 0 && strcmp(mode, "0") == 0) { + Data[0] = 7; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 8; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_MICRO") == 0) { + Data[0] = 9; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS64") == 0) { + Data[0] = 10; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32") == 0) { + Data[0] = 11; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 12; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 13; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO") == 0) { + Data[0] = 13; + } else if (strcmp(arch, "CS_ARCH_PPC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 14; + } else if (strcmp(arch, "CS_ARCH_SPARC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 15; + } else if (strcmp(arch, "CS_ARCH_SPARC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN + CS_MODE_V9") == 0) { + Data[0] = 16; + } else if (strcmp(arch, "CS_ARCH_SYSZ") == 0 && strcmp(mode, "0") == 0) { + Data[0] = 17; + } else if (strcmp(arch, "CS_ARCH_XCORE") == 0 && strcmp(mode, "0") == 0) { + Data[0] = 18; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 19; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN") == 0) { + Data[0] = 20; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6") == 0) { + Data[0] = 21; + } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_MICRO") == 0) { + Data[0] = 22; + } else if (strcmp(arch, "CS_ARCH_M68K") == 0 && strcmp(mode, "0") == 0) { + Data[0] = 23; + } else if (strcmp(arch, "CS_ARCH_M680X") == 0 && strcmp(mode, "CS_MODE_M680X_6809") == 0) { + Data[0] = 24; + } else if (strcmp(arch, "CS_ARCH_EVM") == 0 && strcmp(mode, "0") == 0) { + Data[0] = 25; + } else { + printf("Unknown mode\n"); + //fail instead of continue + return 1; + } + } else { + printf("No mode\n"); + //fail instead of continue + return 1; + } + + while(1) { + if (fgets(line, MAX_LINE_SIZE, fp) == NULL) { + break; + } + Size = 1; + // we start line at offset 0 and Data buffer at offset 1 + // since Data[0] is option : arch + mode + while (sscanf(line+(Size-1)*5, "0x%02x", &value) == 1) { + Data[Size] = value; + Size++; + if (line[(Size-1)*5-1] != ',') { + //end of pattern + break; + } else if (MAX_LINE_SIZE < (Size-1)*5) { + printf("Line overflow\n"); + return 1; + } + } + //lauch fuzzer + LLVMFuzzerTestOneInput(Data, Size); + } + fclose(fp); + } + return 0; +} + diff --git a/white_patch_detect/capstone-master/suite/fuzz/fuzz_diff.c b/white_patch_detect/capstone-master/suite/fuzz/fuzz_diff.c new file mode 100644 index 0000000..f0f39fd --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/fuzz_diff.c @@ -0,0 +1,237 @@ + +#include +#include +#include +#include + +#include + + +struct platform { + cs_arch arch; + cs_mode mode; + char *comment; +}; + +FILE * outfile = NULL; + +struct platform platforms[] = { + { + // item 0 + CS_ARCH_X86, + CS_MODE_32, + "X86 32 (Intel syntax)" + }, + { + // item 1 + CS_ARCH_X86, + CS_MODE_64, + "X86 64 (Intel syntax)" + }, + { + // item 2 + CS_ARCH_ARM, + CS_MODE_ARM, + "ARM" + }, + { + // item 3 + CS_ARCH_ARM, + CS_MODE_THUMB, + "THUMB" + }, + { + // item 4 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + "Arm-V8" + }, + { + // item 5 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB+CS_MODE_V8), + "THUMB+V8" + }, + { + // item 6 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + "Thumb-MClass" + }, + { + // item 7 + CS_ARCH_ARM64, + (cs_mode)0, + "ARM-64" + }, + { + // item 8 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + "MIPS-32 (Big-endian)" + }, + { + // item 9 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO), + "MIPS-32 (micro)" + }, + { + //item 10 + CS_ARCH_MIPS, + CS_MODE_MIPS64, + "MIPS-64-EL (Little-endian)" + }, + { + //item 11 + CS_ARCH_MIPS, + CS_MODE_MIPS32, + "MIPS-32-EL (Little-endian)" + }, + { + //item 12 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN), + "MIPS-64 (Big-endian)" + }, + { + //item 13 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + "MIPS-32 | Micro (Big-endian)" + }, + { + //item 14 + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + "PPC-64" + }, + { + //item 15 + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + "Sparc" + }, + { + //item 16 + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + "SparcV9" + }, + { + //item 17 + CS_ARCH_SYSZ, + (cs_mode)0, + "SystemZ" + }, + { + //item 18 + CS_ARCH_XCORE, + (cs_mode)0, + "XCore" + }, + { + //item 19 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 (Big-endian)" + }, + { + //item 20 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 (Micro+Big-endian)" + }, + { + //item 21 + CS_ARCH_MIPS, + CS_MODE_MIPS32R6, + "MIPS-32R6 (Little-endian)" + }, + { + //item 22 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO), + "MIPS-32R6 (Micro+Little-endian)" + }, + { + //item 23 + CS_ARCH_M68K, + (cs_mode)0, + "M68K" + }, + { + //item 24 + CS_ARCH_M680X, + (cs_mode)CS_MODE_M680X_6809, + "M680X_M6809" + }, + { + //item 25 + CS_ARCH_EVM, + (cs_mode)0, + "EVM" + }, +}; + +void LLVMFuzzerInit(); +int LLVMFuzzerReturnOneInput(const uint8_t *Data, size_t Size, char * AssemblyText); + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { + csh handle; + cs_insn *insn; + cs_err err; + const uint8_t **Datap = &Data; + size_t * Sizep = &Size; + uint64_t address = 0x1000; + char LLVMAssemblyText[80]; + char CapstoneAssemblyText[80]; + + if (Size < 1) { + // 1 byte for arch choice + return 0; + } else if (Size > 0x1000) { + //limit input to 4kb + Size = 0x1000; + } + if (outfile == NULL) { + // we compute the output + outfile = fopen("/dev/null", "w"); + if (outfile == NULL) { + return 0; + } + LLVMFuzzerInit(); + } + + if (Data[0] >= sizeof(platforms)/sizeof(platforms[0])) { + return 0; + } + + if (LLVMFuzzerReturnOneInput(Data, Size, LLVMAssemblyText) == 1) { + return 0; + } + + err = cs_open(platforms[Data[0]].arch, platforms[Data[0]].mode, &handle); + if (err) { + return 0; + } + + insn = cs_malloc(handle); + Data++; + Size--; + assert(insn); + if (cs_disasm_iter(handle, Datap, Sizep, &address, insn)) { + snprintf(CapstoneAssemblyText, 80, "\t%s\t%s", insn->mnemonic, insn->op_str); + if (strcmp(CapstoneAssemblyText, LLVMAssemblyText) != 0) { + printf("capstone %s != llvm %s", CapstoneAssemblyText, LLVMAssemblyText); + abort(); + } + } else { + printf("capstone failed with llvm %s", LLVMAssemblyText); + abort(); + } + cs_free(insn, 1); + cs_close(&handle); + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.c b/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.c new file mode 100644 index 0000000..8b70e48 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.c @@ -0,0 +1,266 @@ +// the following must precede stdio (woo, thanks msft) +#if defined(_MSC_VER) && _MSC_VER < 1900 +#define _CRT_SECURE_NO_WARNINGS +#endif + +#include +#include +#include + +#include + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); + + +struct platform { + cs_arch arch; + cs_mode mode; + const char *comment; +}; + +static FILE *outfile = NULL; + +static struct platform platforms[] = { + { + // item 0 + CS_ARCH_X86, + CS_MODE_32, + "X86 32 (Intel syntax)" + }, + { + // item 1 + CS_ARCH_X86, + CS_MODE_64, + "X86 64 (Intel syntax)" + }, + { + // item 2 + CS_ARCH_ARM, + CS_MODE_ARM, + "ARM" + }, + { + // item 3 + CS_ARCH_ARM, + CS_MODE_THUMB, + "THUMB" + }, + { + // item 4 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + "Arm-V8" + }, + { + // item 5 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB+CS_MODE_V8), + "THUMB+V8" + }, + { + // item 6 + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + "Thumb-MClass" + }, + { + // item 7 + CS_ARCH_ARM64, + (cs_mode)0, + "ARM-64" + }, + { + // item 8 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + "MIPS-32 (Big-endian)" + }, + { + // item 9 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO), + "MIPS-32 (micro)" + }, + { + //item 10 + CS_ARCH_MIPS, + CS_MODE_MIPS64, + "MIPS-64-EL (Little-endian)" + }, + { + //item 11 + CS_ARCH_MIPS, + CS_MODE_MIPS32, + "MIPS-32-EL (Little-endian)" + }, + { + //item 12 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN), + "MIPS-64 (Big-endian)" + }, + { + //item 13 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + "MIPS-32 | Micro (Big-endian)" + }, + { + //item 14 + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + "PPC-64" + }, + { + //item 15 + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + "Sparc" + }, + { + //item 16 + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + "SparcV9" + }, + { + //item 17 + CS_ARCH_SYSZ, + (cs_mode)0, + "SystemZ" + }, + { + //item 18 + CS_ARCH_XCORE, + (cs_mode)0, + "XCore" + }, + { + //item 19 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 (Big-endian)" + }, + { + //item 20 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 (Micro+Big-endian)" + }, + { + //item 21 + CS_ARCH_MIPS, + CS_MODE_MIPS32R6, + "MIPS-32R6 (Little-endian)" + }, + { + //item 22 + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO), + "MIPS-32R6 (Micro+Little-endian)" + }, + { + //item 23 + CS_ARCH_M68K, + (cs_mode)0, + "M68K" + }, + { + //item 24 + CS_ARCH_M680X, + (cs_mode)CS_MODE_M680X_6809, + "M680X_M6809" + }, + { + //item 25 + CS_ARCH_EVM, + (cs_mode)0, + "EVM" + }, +#ifdef CAPSTONE_HAS_MOS65XX + { + //item 26 + CS_ARCH_MOS65XX, + (cs_mode)0, + "MOS65XX" + }, +#endif +}; + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { + csh handle; + cs_insn *all_insn; + cs_detail *detail; + cs_err err; + + if (Size < 1) { + // 1 byte for arch choice + return 0; + } else if (Size > 0x1000) { + //limit input to 4kb + Size = 0x1000; + } + + if (outfile == NULL) { + // we compute the output + outfile = fopen("/dev/null", "w"); + if (outfile == NULL) { + return 0; + } + } + + int platforms_len = sizeof(platforms)/sizeof(platforms[0]); + int i = (int)Data[0] % platforms_len; + + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + return 0; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + uint64_t address = 0x1000; + size_t count = cs_disasm(handle, Data+1, Size-1, address, 0, &all_insn); + + if (count) { + size_t j; + unsigned int n; + + for (j = 0; j < count; j++) { + cs_insn *i = &(all_insn[j]); + fprintf(outfile, "0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", + i->address, i->mnemonic, i->op_str, + i->id, cs_insn_name(handle, i->id)); + + detail = i->detail; + + if (detail->regs_read_count > 0) { + fprintf(outfile, "\tImplicit registers read: "); + for (n = 0; n < detail->regs_read_count; n++) { + fprintf(outfile, "%s ", cs_reg_name(handle, detail->regs_read[n])); + } + } + + if (detail->regs_write_count > 0) { + fprintf(outfile, "\tImplicit registers modified: "); + for (n = 0; n < detail->regs_write_count; n++) { + fprintf(outfile, "%s ", cs_reg_name(handle, detail->regs_write[n])); + } + } + + if (detail->groups_count > 0) { + fprintf(outfile, "\tThis instruction belongs to groups: "); + for (n = 0; n < detail->groups_count; n++) { + fprintf(outfile, "%s ", cs_group_name(handle, detail->groups[n])); + } + } + } + + fprintf(outfile, "0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size); + cs_free(all_insn, count); + } + + cs_close(&handle); + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.options b/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.options new file mode 100644 index 0000000..9fda93f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/fuzz_disasm.options @@ -0,0 +1,2 @@ +[libfuzzer] +max_len = 4096 diff --git a/white_patch_detect/capstone-master/suite/fuzz/fuzz_harness.c b/white_patch_detect/capstone-master/suite/fuzz/fuzz_harness.c new file mode 100644 index 0000000..b69d3ba --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/fuzz_harness.c @@ -0,0 +1,222 @@ +#include +#include +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + char *comment; +}; + +int main(int argc, char **argv) +{ + if (argc != 2) { + printf("Usage: %s \n", argv[0]); + return 1; + } + + struct platform platforms[] = { + { + CS_ARCH_X86, + CS_MODE_32, + "X86 32 (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_64, + "X86 64 (Intel syntax)" + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + "ARM" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + "THUMB-2" + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + "ARM: Cortex-A15 + NEON" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + "THUMB" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + "Thumb-MClass" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + "Arm-V8" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + "MIPS-32 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), + "MIPS-64-EL (Little-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 | Micro (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), + "MIPS-32R6 (Big-endian)" + }, + { + CS_ARCH_ARM64, + CS_MODE_ARM, + "ARM-64" + }, + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + "PPC-64" + }, + { + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + "Sparc" + }, + { + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + "SparcV9" + }, + { + CS_ARCH_SYSZ, + (cs_mode)0, + "SystemZ" + }, + { + CS_ARCH_XCORE, + (cs_mode)0, + "XCore" + }, + { + CS_ARCH_M68K, + (cs_mode)0, + "M68K" + }, + { + CS_ARCH_M680X, + (cs_mode)CS_MODE_M680X_6809, + "M680X_M6809" + }, + }; + + // Read input + long bufsize = 0; + unsigned char *buf = NULL; + FILE *fp = fopen(argv[1], "r"); + + if (fp == NULL) return 1; + + if (fseek(fp, 0L, SEEK_END) == 0) { + bufsize = ftell(fp); + + if (bufsize == -1) return 1; + + buf = malloc(bufsize + 1); + + if (buf == NULL) return 1; + if (fseek(fp, 0L, SEEK_SET) != 0) return 1; + + size_t len = fread(buf, sizeof(char), bufsize, fp); + + if (len == 0) return 2; + } + fclose(fp); + + // Disassemble + csh handle; + cs_insn *all_insn; + cs_detail *detail; + cs_err err; + + if (bufsize < 3) return 0; + + int platforms_len = sizeof(platforms)/sizeof(platforms[0]); + int i = (int)buf[0] % platforms_len; + + unsigned char *buf_ptr = buf + 1; + long buf_ptr_size = bufsize - 1; + + printf("Platform: %s (0x%.2x of 0x%.2x)\n", platforms[i].comment, i, platforms_len); + + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + return 1; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + uint64_t address = 0x1000; + size_t count = cs_disasm(handle, buf_ptr, buf_ptr_size, address, 0, &all_insn); + + if (count) { + size_t j; + int n; + + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + cs_insn *i = &(all_insn[j]); + printf("0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", + i->address, i->mnemonic, i->op_str, + i->id, cs_insn_name(handle, i->id)); + + detail = i->detail; + + if (detail->regs_read_count > 0) { + printf("\tImplicit registers read: "); + for (n = 0; n < detail->regs_read_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_read[n])); + } + printf("\n"); + } + + if (detail->regs_write_count > 0) { + printf("\tImplicit registers modified: "); + for (n = 0; n < detail->regs_write_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_write[n])); + } + printf("\n"); + } + + if (detail->groups_count > 0) { + printf("\tThis instruction belongs to groups: "); + for (n = 0; n < detail->groups_count; n++) { + printf("%s ", cs_group_name(handle, detail->groups[n])); + } + printf("\n"); + } + } + printf("0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size); + cs_free(all_insn, count); + } else { + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + free(buf); + cs_close(&handle); + + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/fuzz/fuzz_llvm.cpp b/white_patch_detect/capstone-master/suite/fuzz/fuzz_llvm.cpp new file mode 100644 index 0000000..7e713cb --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/fuzz_llvm.cpp @@ -0,0 +1,41 @@ +#include "llvm-c/Disassembler.h" +#include "llvm-c/Target.h" +#include "llvm/MC/SubtargetFeature.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +extern "C" void LLVMFuzzerInit() { + LLVMInitializeAllTargetInfos(); + LLVMInitializeAllTargetMCs(); + LLVMInitializeAllDisassemblers(); +} + + +extern "C" int LLVMFuzzerReturnOneInput(const uint8_t *Data, size_t Size, char * AssemblyText) { + LLVMDisasmContextRef Ctx; + std::vector DataCopy(Data, Data + Size); + uint8_t *p = DataCopy.data(); + int r = 1; + + switch(Data[0]) { + case 0: + Ctx = LLVMCreateDisasmCPUFeatures("i386", "", "", nullptr, 0, nullptr, nullptr); + if (LLVMSetDisasmOptions(Ctx, LLVMDisassembler_Option_AsmPrinterVariant) == 0) { + abort(); + } + break; + //TODO other cases + default: + return 1; + } + assert(Ctx); + + if (LLVMDisasmInstruction(Ctx, p+1, Size-1, 0, AssemblyText, 80) > 0) { + r = 0; + } + LLVMDisasmDispose(Ctx); + + return r; +} diff --git a/white_patch_detect/capstone-master/suite/fuzz/onefile.c b/white_patch_detect/capstone-master/suite/fuzz/onefile.c new file mode 100644 index 0000000..74be306 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/fuzz/onefile.c @@ -0,0 +1,51 @@ +#include +#include +#include + +int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); + +int main(int argc, char** argv) +{ + FILE * fp; + uint8_t *Data; + size_t Size; + + if (argc != 2) { + return 1; + } + //opens the file, get its size, and reads it into a buffer + fp = fopen(argv[1], "rb"); + if (fp == NULL) { + return 2; + } + if (fseek(fp, 0L, SEEK_END) != 0) { + fclose(fp); + return 2; + } + Size = ftell(fp); + if (Size == (size_t) -1) { + fclose(fp); + return 2; + } + if (fseek(fp, 0L, SEEK_SET) != 0) { + fclose(fp); + return 2; + } + Data = malloc(Size); + if (Data == NULL) { + fclose(fp); + return 2; + } + if (fread(Data, Size, 1, fp) != 1) { + fclose(fp); + free(Data); + return 2; + } + + //lauch fuzzer + LLVMFuzzerTestOneInput(Data, Size); + free(Data); + fclose(fp); + return 0; +} + diff --git a/white_patch_detect/capstone-master/suite/patch_major_os_version.py b/white_patch_detect/capstone-master/suite/patch_major_os_version.py new file mode 100644 index 0000000..d5036e8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/patch_major_os_version.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python +# By Daniel Pistelli & Nguyen Tan Cong + +# This script is to patch DLL/EXE MajorVersion to 5, +# so they can be loaded by Windows XP. +# This is the problem introduced by compiling on Windows 7, using VS2013. + +import sys, struct + +if len(sys.argv) < 2: + print("Usage: %s " % sys.argv[0]) + sys.exit(0) + +pe_file_path = sys.argv[1] + +with open(pe_file_path, "rb") as f: + b = f.read() + +if not b.startswith("MZ"): + print("Not a PE file") + sys.exit(0) + +e_lfanew = struct.unpack_from(" +# PPC Branch testing suite by kratolp +from __future__ import print_function +import sys +from capstone import * + +CODE32 = b"\x48\x01\x05\x15" # bl .+0x10514 +CODE32 += b"\x4B\xff\xff\xfd" # bl .-0x4 +CODE32 += b"\x48\x00\x00\x0c" # b .+0xc +CODE32 += b"\x41\x80\xff\xd8" # blt .-0x28 +CODE32 += b"\x40\x80\xff\xec" # bge .-0x14 +CODE32 += b"\x41\x84\x01\x6c" # blt cr1, .+0x16c +CODE32 += b"\x41\x82\x00\x10" # beq .+0x10 +CODE32 += b"\x40\x82\x00\x08" # bne .+0x8 +CODE32 += b"\x40\x95\x00\x94" # ble cr5,.+0x94 +CODE32 += b"\x40\x9f\x10\x30" # bns cr5,.+0x94 +CODE32 += b"\x42\x00\xff\xd8" # bdnz .-0x28 +CODE32 += b"\x4d\x82\x00\x20" # beqlr +CODE32 += b"\x4e\x80\x00\x20" # blr +CODE32 += b"\x4a\x00\x00\x02" # ba .0xfe000000 +CODE32 += b"\x41\x80\xff\xda" # blta .0xffffffd8 +CODE32 += b"\x41\x4f\xff\x17" # bdztla 4*cr3+so, .0xffffff14 +CODE32 += b"\x43\x20\x0c\x07" # bdnzla+ .0xc04 +CODE32 += b"\x4c\x00\x04\x20" # bdnzfctr lt + +_python3 = sys.version_info.major == 3 + +all_tests = ( + (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CODE32, "PPC branch instruction decoding", 0), +) + + +def to_hex(s): + if _python3: + return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + return " ".join("0x{0:02x}".format(ord(c)) for c in s) + +# ## Test cs_disasm_quick() +def test_cs_disasm_quick(): + for (arch, mode, code, comment, syntax) in all_tests: + print("Platform: %s" % comment) + print("Code: %s" %(to_hex(code))), + print("Disasm:") + for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000): + print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str)) + print() + + +if __name__ == '__main__': + test_cs_disasm_quick() diff --git a/white_patch_detect/capstone-master/suite/python_capstone_setup.py b/white_patch_detect/capstone-master/suite/python_capstone_setup.py new file mode 100644 index 0000000..5243932 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/python_capstone_setup.py @@ -0,0 +1,4 @@ +#!/bin/sh +# this prints out Capstone setup & core+Python-binding versions + +python -c "import capstone; print capstone.debug()" diff --git a/white_patch_detect/capstone-master/suite/regress.py b/white_patch_detect/capstone-master/suite/regress.py new file mode 100644 index 0000000..a634ae6 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/regress.py @@ -0,0 +1,750 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +import sys +from capstone import * + +all_tests = ( + # arch, mode, syntax, address, hexcode, expected output + # issue 456 https://github.com/aquynh/capstone/issues/456 + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfc16, b"\xE8\x35\x64", "call 0x604e"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123fc1b, b"\x66\xE8\x35\x64", "call 0x6054"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x9123fc1b, b"\x66\xE8\x35\x64", "call 0x6054"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfc26, b"\xE9\x35\x64", "jmp 0x605e"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfff6, b"\x66\xE9\x35\x64\x93\x53", "jmp 0x53946431"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0xe4b7642b"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0x64e4b7642b"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xe8\x35\x64\x93\x53", "call 0x5394641c"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xe8\x35\x64", "call 0x641a"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xe9\x35\x64", "jmp 0x641a"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xe9\x35\x64\x93\x53", "jmp 0x5394641c"), + + # AT&T syntax + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfc16, b"\xE8\x35\x64", "callw 0x604e"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT, 0x9123fc1b, b"\x66\xE8\x35\x64", "callw 0x6054"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x9123fc1b, b"\x66\xE8\x35\x64", "callw 0x6054"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfc26, b"\xE9\x35\x64", "jmp 0x605e"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfff6, b"\x66\xE9\x35\x64\x93\x53", "jmp 0x53946431"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT, 0x9123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0xe4b7642b"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0x64e4b7642b"), + + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xffe1, b"\x66\xe8\x35\x64\x93\x53", "calll 0x5394641c"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123ffe1, b"\x66\xe8\x35\x64", "callw 0x641a"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123ffe1, b"\x66\xe9\x35\x64", "jmp 0x641a"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xffe1, b"\x66\xe9\x35\x64\x93\x53", "jmp 0x5394641c"), + + # issue 452 https://github.com/aquynh/capstone/issues/452 + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6C", "insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6D", "insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6E", "outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6F", "outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA4", "movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA5", "movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA7", "cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAA", "stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAB", "stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAC", "lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAD", "lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAE", "scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAF", "scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6C", "insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6D", "insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6E", "outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6F", "outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA4", "movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA5", "movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA7", "cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAA", "stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAB", "stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAC", "lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAD", "lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAE", "scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAF", "scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6C", "insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6D", "insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6F", "outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA5", "movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA7", "cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAA", "stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAB", "stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAD", "lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAE", "scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAF", "scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6C", "repne insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6D", "repne insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6F", "repne outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA5", "repne movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA7", "repne cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAA", "repne stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAB", "repne stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAD", "repne lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAE", "repne scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAF", "repne scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6C", "rep insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6D", "rep insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6F", "rep outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA5", "rep movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA7", "repe cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAA", "rep stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAB", "rep stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAD", "rep lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAE", "repe scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAF", "repe scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6C", "insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6D", "insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6F", "outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA5", "movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA7", "cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAA", "stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAB", "stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAD", "lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAE", "scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAF", "scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6C", "repne insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6D", "repne insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6F", "repne outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA5", "repne movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA7", "repne cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAA", "repne stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAB", "repne stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAD", "repne lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAF", "repne scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6C", "rep insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6D", "rep insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6F", "rep outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA5", "rep movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA7", "repe cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAA", "rep stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAB", "rep stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAD", "rep lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAF", "repe scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6C", "repne insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6D", "repne insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6F", "repne outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA5", "repne movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA7", "repne cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAA", "repne stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAB", "repne stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAD", "repne lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAF", "repne scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6C", "rep insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6D", "rep insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6F", "rep outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA5", "rep movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA7", "repe cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAA", "rep stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAB", "rep stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAD", "rep lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAF", "repe scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6D", "repne insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6F", "repne outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA5", "repne movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAB", "repne stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAF", "repne scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6D", "rep insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6F", "rep outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA5", "rep movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAB", "rep stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAF", "repe scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6C", "insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6D", "insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6F", "outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA5", "movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA7", "cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAA", "stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAB", "stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAD", "lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAE", "scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAF", "scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6C", "insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6D", "insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6F", "outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA5", "movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA7", "cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAA", "stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAB", "stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAD", "lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAE", "scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAF", "scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6C", "insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6D", "insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6E", "outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6F", "outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA4", "movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA5", "movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA7", "cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAA", "stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAB", "stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAC", "lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAD", "lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAE", "scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAF", "scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6C", "repne insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6D", "repne insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6F", "repne outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA5", "repne movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAA", "repne stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAB", "repne stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAF", "repne scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6C", "rep insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6D", "rep insd dword ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6F", "rep outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA5", "rep movsd dword ptr es:[edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAA", "rep stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAB", "rep stosd dword ptr es:[edi], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAF", "repe scasd eax, dword ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6C", "insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6D", "insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6F", "outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA4", "movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA5", "movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA7", "cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAA", "stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAB", "stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAD", "lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAE", "scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAF", "scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6C", "repne insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6D", "repne insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6F", "repne outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA5", "repne movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA7", "repne cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAA", "repne stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAB", "repne stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAD", "repne lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAF", "repne scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6C", "rep insb byte ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6D", "rep insw word ptr es:[edi], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6F", "rep outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA5", "rep movsw word ptr es:[edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA7", "repe cmpsw word ptr [esi], word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAA", "rep stosb byte ptr es:[edi], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAB", "rep stosw word ptr es:[edi], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAD", "rep lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAF", "repe scasw ax, word ptr es:[edi]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6C", "repne insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6D", "repne insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6F", "repne outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA5", "repne movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA7", "repne cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAA", "repne stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAB", "repne stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAD", "repne lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAF", "repne scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6C", "rep insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6D", "rep insd dword ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6F", "rep outsd dx, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA5", "rep movsd dword ptr es:[di], dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA7", "repe cmpsd dword ptr [si], dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAA", "rep stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAB", "rep stosd dword ptr es:[di], eax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAD", "rep lodsd eax, dword ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAF", "repe scasd eax, dword ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6D", "repne insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6F", "repne outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA5", "repne movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA7", "repne cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAB", "repne stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAD", "repne lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAF", "repne scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6D", "rep insw word ptr es:[di], dx"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6F", "rep outsw dx, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA5", "rep movsw word ptr es:[di], word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA7", "repe cmpsw word ptr [si], word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr es:[di], al"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAB", "rep stosw word ptr es:[di], ax"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAD", "rep lodsw ax, word ptr [si]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAF", "repe scasw ax, word ptr es:[di]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6C", "insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6D", "insd dword ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6E", "outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6F", "outsd dx, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA5", "movsd dword ptr [rdi], dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA7", "cmpsd dword ptr [rsi], dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAA", "stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAB", "stosd dword ptr [rdi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAC", "lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAD", "lodsd eax, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAE", "scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAF", "scasd eax, dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6C", "insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6D", "insw word ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6E", "outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6F", "outsw dx, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA5", "movsw word ptr [rdi], word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA7", "cmpsw word ptr [rsi], word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAA", "stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAB", "stosw word ptr [rdi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAC", "lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAD", "lodsw ax, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAE", "scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAF", "scasw ax, word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6C", "insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6D", "insd dword ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6F", "outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA4", "movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA5", "movsd dword ptr [edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA7", "cmpsd dword ptr [esi], dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAA", "stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAB", "stosd dword ptr [edi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAD", "lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAE", "scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAF", "scasd eax, dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6C", "repne insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6D", "repne insd dword ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6F", "repne outsd dx, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA5", "repne movsd dword ptr [rdi], dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA7", "repne cmpsd dword ptr [rsi], dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAA", "repne stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAB", "repne stosd dword ptr [rdi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAD", "repne lodsd eax, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAE", "repne scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAF", "repne scasd eax, dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6C", "rep insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6D", "rep insd dword ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6F", "rep outsd dx, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA5", "rep movsd dword ptr [rdi], dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA7", "repe cmpsd dword ptr [rsi], dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAA", "rep stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAB", "rep stosd dword ptr [rdi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAD", "rep lodsd eax, dword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAE", "repe scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAF", "repe scasd eax, dword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6C", "insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6D", "insw word ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6F", "outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA4", "movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA5", "movsw word ptr [edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA7", "cmpsw word ptr [esi], word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAA", "stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAB", "stosw word ptr [edi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAD", "lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAE", "scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAF", "scasw ax, word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6C", "repne insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6D", "repne insw word ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6F", "repne outsw dx, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA5", "repne movsw word ptr [rdi], word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA7", "repne cmpsw word ptr [rsi], word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAA", "repne stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAB", "repne stosw word ptr [rdi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAD", "repne lodsw ax, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAF", "repne scasw ax, word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6C", "rep insb byte ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6D", "rep insw word ptr [rdi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6F", "rep outsw dx, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA5", "rep movsw word ptr [rdi], word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA7", "repe cmpsw word ptr [rsi], word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAA", "rep stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAB", "rep stosw word ptr [rdi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAD", "rep lodsw ax, word ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAF", "repe scasw ax, word ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6C", "repne insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6D", "repne insd dword ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6F", "repne outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA5", "repne movsd dword ptr [edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAA", "repne stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAB", "repne stosd dword ptr [edi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAF", "repne scasd eax, dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6C", "rep insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6D", "rep insd dword ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6F", "rep outsd dx, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA5", "rep movsd dword ptr [edi], dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAA", "rep stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAB", "rep stosd dword ptr [edi], eax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAF", "repe scasd eax, dword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6D", "repne insw word ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6F", "repne outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA5", "repne movsw word ptr [edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA7", "repne cmpsw word ptr [esi], word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAB", "repne stosw word ptr [edi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAD", "repne lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAF", "repne scasw ax, word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6D", "rep insw word ptr [edi], dx"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6F", "rep outsw dx, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA5", "rep movsw word ptr [edi], word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA7", "repe cmpsw word ptr [esi], word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAB", "rep stosw word ptr [edi], ax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAD", "rep lodsw ax, word ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAF", "repe scasw ax, word ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA5", "movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA7", "cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAA", "stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAB", "stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAC", "lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAD", "lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAE", "scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAF", "scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA5", "movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA7", "cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAA", "stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAB", "stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAC", "lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAD", "lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAE", "scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAF", "scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA4", "movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA5", "movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA7", "cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAA", "stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAB", "stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAD", "lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAE", "scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAF", "scasq rax, qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA5", "repne movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA7", "repne cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAA", "repne stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAB", "repne stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAC", "repne lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAD", "repne lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAE", "repne scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAF", "repne scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA5", "rep movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA7", "repe cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAA", "rep stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAB", "rep stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAC", "rep lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAD", "rep lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAE", "repe scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAF", "repe scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA4", "movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA5", "movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA7", "cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAA", "stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAB", "stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAC", "lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAD", "lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAE", "scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAF", "scasq rax, qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA5", "repne movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA7", "repne cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAA", "repne stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAB", "repne stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAC", "repne lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAD", "repne lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAE", "repne scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAF", "repne scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA5", "rep movsq qword ptr [rdi], qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA7", "repe cmpsq qword ptr [rsi], qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAA", "rep stosb byte ptr [rdi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAB", "rep stosq qword ptr [rdi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAC", "rep lodsb al, byte ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAD", "rep lodsq rax, qword ptr [rsi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAE", "repe scasb al, byte ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAF", "repe scasq rax, qword ptr [rdi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA5", "repne movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA7", "repne cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAA", "repne stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAB", "repne stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAD", "repne lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAE", "repne scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAF", "repne scasq rax, qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA5", "rep movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA7", "repe cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAA", "rep stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAB", "rep stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAD", "rep lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAE", "repe scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAF", "repe scasq rax, qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA5", "repne movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA7", "repne cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAA", "repne stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAB", "repne stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAC", "repne lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAD", "repne lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAE", "repne scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAF", "repne scasq rax, qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA5", "rep movsq qword ptr [edi], qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA7", "repe cmpsq qword ptr [esi], qword ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAA", "rep stosb byte ptr [edi], al"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAB", "rep stosq qword ptr [edi], rax"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAC", "rep lodsb al, byte ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAD", "rep lodsq rax, qword ptr [esi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAE", "repe scasb al, byte ptr [edi]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAF", "repe scasq rax, qword ptr [edi]"), + + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x05", "sgdt [di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x05", "sgdt [di]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x0d", "sidt [di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x0d", "sidt [di]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x15", "lgdt [di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x15", "lgdt [di]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [rip + 0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [0x80490a0]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x1d", "lidt [di]"), + (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x1d", "lidt [di]"), + + # issues 702 https://github.com/aquynh/capstone/issues/702 + (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0, b"\x85\xC8", "test eax, ecx") +) + +_python3 = sys.version_info.major == 3 + + +def to_hex(s): + if _python3: + return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + return " ".join("0x{0:02x}".format(ord(c)) for c in s) + + +def str_syntax(syntax): + slist = { + 0: "", + CS_OPT_SYNTAX_INTEL: "intel", + CS_OPT_SYNTAX_ATT: "att", + } + + return slist[syntax] + + +def str_arch_mode(a, m): + amlist = { + (CS_ARCH_X86, CS_MODE_16): "X86-16bit", + (CS_ARCH_X86, CS_MODE_32): "X86-32bit", + (CS_ARCH_X86, CS_MODE_64): "X86-64bit", + } + + return amlist[(a, m)] + + +# ## Test cs_disasm_quick() +def test_regression(verbose): + for (arch, mode, syntax, address, code, expected_output) in all_tests: + #print("%s %s: %s = " %(str_arch_mode(arch, mode), str_syntax(syntax), to_hex(code)), end=""), + output = "%s %s: %s = " %(str_arch_mode(arch, mode), str_syntax(syntax), to_hex(code)) + md = Cs(arch, mode) + if syntax != 0: + md.syntax = syntax + insn = list(md.disasm(code, address))[0] + output2 = "%s %s" % (insn.mnemonic, insn.op_str) + if output2 != expected_output: + print(output, output2) + print("\t --> ERROR: expected output = %s" %(expected_output)) + elif verbose: + print(output, output2) + + +if __name__ == '__main__': + import sys + if len(sys.argv) == 2 and sys.argv[1] == "-v": + test_regression(True) # quiet + else: + test_regression(False) # verbose diff --git a/white_patch_detect/capstone-master/suite/regress/LICENSE b/white_patch_detect/capstone-master/suite/regress/LICENSE new file mode 100644 index 0000000..dd85900 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/regress/LICENSE @@ -0,0 +1,30 @@ +This is the software license for Unicorn regression tests. The regression tests +are written by several Unicorn contributors (See CREDITS.TXT) and maintained by +Hoang-Vu Dang + +Copyright (c) 2015, Unicorn contributors +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. +* Neither the name of the developer(s) nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/white_patch_detect/capstone-master/suite/regress/Makefile b/white_patch_detect/capstone-master/suite/regress/Makefile new file mode 100644 index 0000000..bbc73c7 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/regress/Makefile @@ -0,0 +1,10 @@ +LIBNAME = capstone + +invalid_read_in_print_operand: invalid_read_in_print_operand.o + ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ + +%.o: %.c + ${CC} -c -I../../include $< -o $@ + +clean: + rm -rf *.o invalid_read_in_print_operand diff --git a/white_patch_detect/capstone-master/suite/regress/invalid_read_in_print_operand.c b/white_patch_detect/capstone-master/suite/regress/invalid_read_in_print_operand.c new file mode 100644 index 0000000..144ae94 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/regress/invalid_read_in_print_operand.c @@ -0,0 +1,14 @@ +#include + +#define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8" + +int main(int argc, char **argv, char **envp) { + csh handle; + if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) { + printf("cs_open(鈥) failed\n"); + return 1; + } + cs_insn *insn; + cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn); + return 0; +} diff --git a/white_patch_detect/capstone-master/suite/regress/regress.py b/white_patch_detect/capstone-master/suite/regress/regress.py new file mode 100644 index 0000000..2e4f253 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/regress/regress.py @@ -0,0 +1,34 @@ +#!/usr/bin/python + +import unittest + +from os.path import dirname, basename, isfile +import glob + +# Find all unittest type in this directory and run it. + +class RegressTest(unittest.TestCase): + pass + +def main(): + unittest.main() + +if __name__ == '__main__': + directory = dirname(__file__) + if directory == '': + directory = '.' + modules = glob.glob(directory+"/*.py") + __all__ = [ basename(f)[:-3] for f in modules if isfile(f)] + suite = unittest.TestSuite() + + for module in __all__: + m = __import__(module) + for cl in dir(m): + try: + realcl = getattr(m,cl) + if issubclass(realcl, unittest.TestCase): + suite.addTest(realcl()) + except Exception as e: + pass + + unittest.TextTestRunner().run(suite) diff --git a/white_patch_detect/capstone-master/suite/test_all.sh b/white_patch_detect/capstone-master/suite/test_all.sh new file mode 100644 index 0000000..443f442 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_all.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +# dump test output to /tmp/ for diffing +# this is useful to detect if a change modifies any disasm output + +# syntax: test_all.sh + +./test_archs.py > /tmp/$1_arch +./test_c.sh $1_c diff --git a/white_patch_detect/capstone-master/suite/test_c.sh b/white_patch_detect/capstone-master/suite/test_c.sh new file mode 100644 index 0000000..ccc88eb --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_c.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +# Run all the Python tests, and send the output that to a file to be compared later +# This is useful when we want to verify if a commit (wrongly) changes the disassemble result. + +../tests/test > /tmp/$1 +../tests/test_detail >> /tmp/$1 +../tests/test_skipdata >> /tmp/$1 +../tests/test_iter >> /tmp/$1 +../tests/test_arm >> /tmp/$1 +../tests/test_arm64 >> /tmp/$1 +../tests/test_mips >> /tmp/$1 +../tests/test_ppc >> /tmp/$1 +../tests/test_sparc >> /tmp/$1 +../tests/test_x86 >> /tmp/$1 +../tests/test_systemz >> /tmp/$1 +../tests/test_xcore >> /tmp/$1 diff --git a/white_patch_detect/capstone-master/suite/test_corpus.py b/white_patch_detect/capstone-master/suite/test_corpus.py new file mode 100644 index 0000000..817efb6 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_corpus.py @@ -0,0 +1,129 @@ +#!/usr/bin/python +# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014 +import sys +import os +from capstone import * + +def test_file(fname): + print("Test %s" %fname); + f = open(fname) + lines = f.readlines() + f.close() + + if not lines[0].startswith('# '): + print("ERROR: decoding information is missing") + return + + # skip '# ' at the front, then split line to get out hexcode + # Note: option can be '', or 'None' + #print lines[0] + #print lines[0][2:].split(', ') + (arch, mode, option) = lines[0][2:].split(', ') + mode = mode.replace(' ', '') + option = option.strip() + + archs = { + "CS_ARCH_ARM": CS_ARCH_ARM, + "CS_ARCH_ARM64": CS_ARCH_ARM64, + "CS_ARCH_MIPS": CS_ARCH_MIPS, + "CS_ARCH_PPC": CS_ARCH_PPC, + "CS_ARCH_SPARC": CS_ARCH_SPARC, + "CS_ARCH_SYSZ": CS_ARCH_SYSZ, + "CS_ARCH_X86": CS_ARCH_X86, + "CS_ARCH_XCORE": CS_ARCH_XCORE, + } + + modes = { + "CS_MODE_16": CS_MODE_16, + "CS_MODE_32": CS_MODE_32, + "CS_MODE_64": CS_MODE_64, + "CS_MODE_MIPS32": CS_MODE_MIPS32, + "CS_MODE_MIPS64": CS_MODE_MIPS64, + "0": CS_MODE_ARM, + "CS_MODE_ARM": CS_MODE_ARM, + "CS_MODE_THUMB": CS_MODE_THUMB, + "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, + "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, + "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, + "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, + "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, + } + + mc_modes = { + ("CS_ARCH_X86", "CS_MODE_32"): 0, + ("CS_ARCH_X86", "CS_MODE_64"): 1, + ("CS_ARCH_ARM", "CS_MODE_ARM"): 2, + ("CS_ARCH_ARM", "CS_MODE_THUMB"): 3, + ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): 4, + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): 5, + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): 6, + ("CS_ARCH_ARM64", "0"): 7, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 8, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 9, + ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 10, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 11, + ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 12, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 13, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 13, + ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 14, + ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 15, + ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 16, + ("CS_ARCH_SYSZ", "0"): 17, + ("CS_ARCH_XCORE", "0"): 18, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 19, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 20, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 21, + ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 22, + ("CS_ARCH_M68K", "0"): 23, + ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 24, + ("CS_ARCH_EVM", "0"): 25, + } + + #if not option in ('', 'None'): + # print archs[arch], modes[mode], options[option] + + for line in lines[1:]: + # ignore all the input lines having # in front. + if line.startswith('#'): + continue + if line.startswith('// '): + line=line[3:] + #print("Check %s" %line) + code = line.split(' = ')[0] + if len(code) < 2: + continue + if code.find('//') >= 0: + continue + hex_code = code.replace('0x', '') + hex_code = hex_code.replace(',', '') + try: + hex_data = hex_code.strip().decode('hex') + except: + print "skipping", hex_code + fout = open("fuzz/corpus/%s_%s" % (os.path.basename(fname), hex_code), 'w') + if (arch, mode) not in mc_modes: + print "fail", arch, mode + fout.write(unichr(mc_modes[(arch, mode)])) + fout.write(hex_data) + fout.close() + + +if __name__ == '__main__': + if len(sys.argv) == 1: + fnames = sys.stdin.readlines() + for fname in fnames: + test_file(fname.strip()) + else: + #print("Usage: ./test_mc.py ") + test_file(sys.argv[1]) + diff --git a/white_patch_detect/capstone-master/suite/test_group_name.py b/white_patch_detect/capstone-master/suite/test_group_name.py new file mode 100644 index 0000000..7a746f8 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_group_name.py @@ -0,0 +1,247 @@ +#!/usr/bin/python + +from capstone import * +from capstone.arm import * +from capstone.arm64 import * +from capstone.mips import * +from capstone.ppc import * +from capstone.sparc import * +from capstone.systemz import * +from capstone.x86 import * +from capstone.xcore import * +import sys + +class GroupTest: + def __init__(self, name, arch, mode, data): + self.name = name + self.arch = arch + self.mode = mode + self.data = data + + def run(self): + print('Testing %s' %self.name) + cap = Cs(self.arch, self.mode) + for group_id in xrange(0,255): + name = self.data.get(group_id) + res = cap.group_name(group_id) + if res != name: + print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res)) + print("") + +arm_dict = { + ARM_GRP_JUMP: "jump", + ARM_GRP_CALL: "call", + ARM_GRP_INT: "int", + ARM_GRP_PRIVILEGE: "privilege", + + ARM_GRP_CRYPTO: "crypto", + ARM_GRP_DATABARRIER: "databarrier", + ARM_GRP_DIVIDE: "divide", + ARM_GRP_FPARMV8: "fparmv8", + ARM_GRP_MULTPRO: "multpro", + ARM_GRP_NEON: "neon", + ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK", + ARM_GRP_THUMB2DSP: "THUMB2DSP", + ARM_GRP_TRUSTZONE: "TRUSTZONE", + ARM_GRP_V4T: "v4t", + ARM_GRP_V5T: "v5t", + ARM_GRP_V5TE: "v5te", + ARM_GRP_V6: "v6", + ARM_GRP_V6T2: "v6t2", + ARM_GRP_V7: "v7", + ARM_GRP_V8: "v8", + ARM_GRP_VFP2: "vfp2", + ARM_GRP_VFP3: "vfp3", + ARM_GRP_VFP4: "vfp4", + ARM_GRP_ARM: "arm", + ARM_GRP_MCLASS: "mclass", + ARM_GRP_NOTMCLASS: "notmclass", + ARM_GRP_THUMB: "thumb", + ARM_GRP_THUMB1ONLY: "thumb1only", + ARM_GRP_THUMB2: "thumb2", + ARM_GRP_PREV8: "prev8", + ARM_GRP_FPVMLX: "fpvmlx", + ARM_GRP_MULOPS: "mulops", + ARM_GRP_CRC: "crc", + ARM_GRP_DPVFP: "dpvfp", + ARM_GRP_V6M: "v6m", + ARM_GRP_VIRTUALIZATION: "virtualization", +} + +arm64_dict = { + ARM64_GRP_JUMP: "jump", + ARM64_GRP_CALL: "call", + ARM64_GRP_RET: "return", + ARM64_GRP_INT: "int", + ARM64_GRP_PRIVILEGE: "privilege", + + ARM64_GRP_CRYPTO: "crypto", + ARM64_GRP_FPARMV8: "fparmv8", + ARM64_GRP_NEON: "neon", + ARM64_GRP_CRC: "crc" +} + +mips_dict = { + MIPS_GRP_JUMP: "jump", + MIPS_GRP_CALL: "call", + MIPS_GRP_RET: "ret", + MIPS_GRP_INT: "int", + MIPS_GRP_IRET: "iret", + MIPS_GRP_PRIVILEGE: "privilege", + MIPS_GRP_BITCOUNT: "bitcount", + MIPS_GRP_DSP: "dsp", + MIPS_GRP_DSPR2: "dspr2", + MIPS_GRP_FPIDX: "fpidx", + MIPS_GRP_MSA: "msa", + MIPS_GRP_MIPS32R2: "mips32r2", + MIPS_GRP_MIPS64: "mips64", + MIPS_GRP_MIPS64R2: "mips64r2", + MIPS_GRP_SEINREG: "seinreg", + MIPS_GRP_STDENC: "stdenc", + MIPS_GRP_SWAP: "swap", + MIPS_GRP_MICROMIPS: "micromips", + MIPS_GRP_MIPS16MODE: "mips16mode", + MIPS_GRP_FP64BIT: "fp64bit", + MIPS_GRP_NONANSFPMATH: "nonansfpmath", + MIPS_GRP_NOTFP64BIT: "notfp64bit", + MIPS_GRP_NOTINMICROMIPS: "notinmicromips", + MIPS_GRP_NOTNACL: "notnacl", + + MIPS_GRP_NOTMIPS32R6: "notmips32r6", + MIPS_GRP_NOTMIPS64R6: "notmips64r6", + MIPS_GRP_CNMIPS: "cnmips", + + MIPS_GRP_MIPS32: "mips32", + MIPS_GRP_MIPS32R6: "mips32r6", + MIPS_GRP_MIPS64R6: "mips64r6", + + MIPS_GRP_MIPS2: "mips2", + MIPS_GRP_MIPS3: "mips3", + MIPS_GRP_MIPS3_32: "mips3_32", + MIPS_GRP_MIPS3_32R2: "mips3_32r2", + + MIPS_GRP_MIPS4_32: "mips4_32", + MIPS_GRP_MIPS4_32R2: "mips4_32r2", + MIPS_GRP_MIPS5_32R2: "mips5_32r2", + + MIPS_GRP_GP32BIT: "gp32bit", + MIPS_GRP_GP64BIT: "gp64bit", +} + +ppc_dict = { + PPC_GRP_JUMP: "jump", + + PPC_GRP_ALTIVEC: "altivec", + PPC_GRP_MODE32: "mode32", + PPC_GRP_MODE64: "mode64", + PPC_GRP_BOOKE: "booke", + PPC_GRP_NOTBOOKE: "notbooke", + PPC_GRP_SPE: "spe", + PPC_GRP_VSX: "vsx", + PPC_GRP_E500: "e500", + PPC_GRP_PPC4XX: "ppc4xx", + PPC_GRP_PPC6XX: "ppc6xx", + PPC_GRP_ICBT: "icbt", + PPC_GRP_P8ALTIVEC: "p8altivec", + PPC_GRP_P8VECTOR: "p8vector", + PPC_GRP_QPX: "qpx", +} + +sparc_dict = { + SPARC_GRP_JUMP: "jump", + + SPARC_GRP_HARDQUAD: "hardquad", + SPARC_GRP_V9: "v9", + SPARC_GRP_VIS: "vis", + SPARC_GRP_VIS2: "vis2", + SPARC_GRP_VIS3: "vis3", + SPARC_GRP_32BIT: "32bit", + SPARC_GRP_64BIT: "64bit", +} + +sysz_dict = { + SYSZ_GRP_JUMP: "jump", + + SYSZ_GRP_DISTINCTOPS: "distinctops", + SYSZ_GRP_FPEXTENSION: "fpextension", + SYSZ_GRP_HIGHWORD: "highword", + SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1", + SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond", +} + +x86_dict = { + X86_GRP_JUMP: "jump", + X86_GRP_CALL: "call", + X86_GRP_RET: "ret", + X86_GRP_INT: "int", + X86_GRP_IRET: "iret", + X86_GRP_PRIVILEGE: "privilege", + + X86_GRP_VM: "vm", + X86_GRP_3DNOW: "3dnow", + X86_GRP_AES: "aes", + X86_GRP_ADX: "adx", + X86_GRP_AVX: "avx", + X86_GRP_AVX2: "avx2", + X86_GRP_AVX512: "avx512", + X86_GRP_BMI: "bmi", + X86_GRP_BMI2: "bmi2", + X86_GRP_CMOV: "cmov", + X86_GRP_F16C: "fc16", + X86_GRP_FMA: "fma", + X86_GRP_FMA4: "fma4", + X86_GRP_FSGSBASE: "fsgsbase", + X86_GRP_HLE: "hle", + X86_GRP_MMX: "mmx", + X86_GRP_MODE32: "mode32", + X86_GRP_MODE64: "mode64", + X86_GRP_RTM: "rtm", + X86_GRP_SHA: "sha", + X86_GRP_SSE1: "sse1", + X86_GRP_SSE2: "sse2", + X86_GRP_SSE3: "sse3", + X86_GRP_SSE41: "sse41", + X86_GRP_SSE42: "sse42", + X86_GRP_SSE4A: "sse4a", + X86_GRP_SSSE3: "ssse3", + X86_GRP_PCLMUL: "pclmul", + X86_GRP_XOP: "xop", + X86_GRP_CDI: "cdi", + X86_GRP_ERI: "eri", + X86_GRP_TBM: "tbm", + X86_GRP_16BITMODE: "16bitmode", + X86_GRP_NOT64BITMODE: "not64bitmode", + X86_GRP_SGX: "sgx", + X86_GRP_DQI: "dqi", + X86_GRP_BWI: "bwi", + X86_GRP_PFI: "pfi", + X86_GRP_VLX: "vlx", + X86_GRP_SMAP: "smap", + X86_GRP_NOVLX: "novlx", +} + +xcore_dict = { + XCORE_GRP_JUMP: "jump", +} + +tests = [ + GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict), + GroupTest('arm64', CS_ARCH_ARM64, CS_MODE_ARM, arm64_dict), + GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict), + GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict), + GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict), + GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict), + GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict), + GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict), + GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict), +] + +if __name__ == '__main__': + args = sys.argv[1:] + all = len(args) == 0 or 'all' in args + for t in tests: + if all or t.name in args: + t.run() + else: + print('Skipping %s' %t.name) + diff --git a/white_patch_detect/capstone-master/suite/test_mc.py b/white_patch_detect/capstone-master/suite/test_mc.py new file mode 100644 index 0000000..7303b45 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_mc.py @@ -0,0 +1,262 @@ +#!/usr/bin/python +# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014 +import array, os.path, sys +from subprocess import Popen, PIPE, STDOUT +from capstone import * + + +# convert all hex numbers to decimal numbers in a text +def normalize_hex(a): + while(True): + i = a.find('0x') + if i == -1: # no more hex number + break + hexnum = '0x' + for c in a[i + 2:]: + if c in '0123456789abcdefABCDEF': + hexnum += c + else: + break + num = int(hexnum, 16) + a = a.replace(hexnum, str(num)) + return a + + +def run_mc(arch, hexcode, option, syntax=None): + def normalize(text): + # remove tabs + text = text.lower() + items = text.split() + text = ' '.join(items) + if arch == CS_ARCH_X86: + # remove comment after # + i = text.find('# ') + if i != -1: + return text[:i].strip() + if arch == CS_ARCH_ARM64: + # remove comment after # + i = text.find('// ') + if i != -1: + return text[:i].strip() + # remove some redundant spaces + text = text.replace('{ ', '{') + text = text.replace(' }', '}') + return text.strip() + + #print("Trying to decode: %s" %hexcode) + if syntax: + if arch == CS_ARCH_MIPS: + p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) + else: + p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) + else: + if arch == CS_ARCH_MIPS: + p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) + else: + p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT) + output = p.communicate(input=hexcode)[0] + lines = output.split('\n') + #print lines + if 'invalid' in lines[0]: + #print 'invalid ----' + return 'FAILED to disassemble (MC)' + else: + #print 'OK:', lines[1] + return normalize(lines[1].strip()) + +def test_file(fname): + print("Test %s" %fname); + f = open(fname) + lines = f.readlines() + f.close() + + if not lines[0].startswith('# '): + print("ERROR: decoding information is missing") + return + + # skip '# ' at the front, then split line to get out hexcode + # Note: option can be '', or 'None' + #print lines[0] + #print lines[0][2:].split(', ') + (arch, mode, option) = lines[0][2:].split(', ') + mode = mode.replace(' ', '') + option = option.strip() + + archs = { + "CS_ARCH_ARM": CS_ARCH_ARM, + "CS_ARCH_ARM64": CS_ARCH_ARM64, + "CS_ARCH_MIPS": CS_ARCH_MIPS, + "CS_ARCH_PPC": CS_ARCH_PPC, + "CS_ARCH_SPARC": CS_ARCH_SPARC, + "CS_ARCH_SYSZ": CS_ARCH_SYSZ, + "CS_ARCH_X86": CS_ARCH_X86, + "CS_ARCH_XCORE": CS_ARCH_XCORE + # "CS_ARCH_M68K": CS_ARCH_M68K, + } + + modes = { + "CS_MODE_16": CS_MODE_16, + "CS_MODE_32": CS_MODE_32, + "CS_MODE_64": CS_MODE_64, + "CS_MODE_MIPS32": CS_MODE_MIPS32, + "CS_MODE_MIPS64": CS_MODE_MIPS64, + "0": CS_MODE_ARM, + "CS_MODE_ARM": CS_MODE_ARM, + "CS_MODE_THUMB": CS_MODE_THUMB, + "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, + "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, + "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, + "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, + "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, + "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, + "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, + "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, + "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, + "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, + } + + options = { + "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT, + "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME, + } + + mc_modes = { + ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'], + ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'], + ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'], + ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'], + ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'], + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'], + ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'], + ("CS_ARCH_ARM64", "0"): ['-triple=aarch64'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'], + ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'], + ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'], + ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'], + ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'], + ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'], + } + + #if not option in ('', 'None'): + # print archs[arch], modes[mode], options[option] + + #print(arch, mode, option) + md = Cs(archs[arch], modes[mode]) + + mc_option = None + if arch == 'CS_ARCH_X86': + # tell llvm-mc to use Intel syntax + mc_option = '-output-asm-variant=1' + + if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' : + md.syntax = CS_OPT_SYNTAX_NOREGNAME + + if fname.endswith('3DNow.s.cs'): + md.syntax = CS_OPT_SYNTAX_ATT + + for line in lines[1:]: + # ignore all the input lines having # in front. + if line.startswith('#'): + continue + #print("Check %s" %line) + code = line.split(' = ')[0] + asm = ''.join(line.split(' = ')[1:]) + hex_code = code.replace('0x', '') + hex_code = hex_code.replace(',', '') + hex_data = hex_code.decode('hex') + #hex_bytes = array.array('B', hex_data) + + x = list(md.disasm(hex_data, 0)) + if len(x) > 0: + if x[0].op_str != '': + cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str) + else: + cs_output = x[0].mnemonic + else: + cs_output = 'FAILED to disassemble' + + cs_output2 = normalize_hex(cs_output) + cs_output2 = cs_output2.replace(' ', '') + + if arch == 'CS_ARCH_MIPS': + # normalize register alias names + cs_output2 = cs_output2.replace('$at', '$1') + cs_output2 = cs_output2.replace('$v0', '$2') + cs_output2 = cs_output2.replace('$v1', '$3') + + cs_output2 = cs_output2.replace('$a0', '$4') + cs_output2 = cs_output2.replace('$a1', '$5') + cs_output2 = cs_output2.replace('$a2', '$6') + cs_output2 = cs_output2.replace('$a3', '$7') + + cs_output2 = cs_output2.replace('$t0', '$8') + cs_output2 = cs_output2.replace('$t1', '$9') + cs_output2 = cs_output2.replace('$t2', '$10') + cs_output2 = cs_output2.replace('$t3', '$11') + cs_output2 = cs_output2.replace('$t4', '$12') + cs_output2 = cs_output2.replace('$t5', '$13') + cs_output2 = cs_output2.replace('$t6', '$14') + cs_output2 = cs_output2.replace('$t7', '$15') + cs_output2 = cs_output2.replace('$t8', '$24') + cs_output2 = cs_output2.replace('$t9', '$25') + + cs_output2 = cs_output2.replace('$s0', '$16') + cs_output2 = cs_output2.replace('$s1', '$17') + cs_output2 = cs_output2.replace('$s2', '$18') + cs_output2 = cs_output2.replace('$s3', '$19') + cs_output2 = cs_output2.replace('$s4', '$20') + cs_output2 = cs_output2.replace('$s5', '$21') + cs_output2 = cs_output2.replace('$s6', '$22') + cs_output2 = cs_output2.replace('$s7', '$23') + + cs_output2 = cs_output2.replace('$k0', '$26') + cs_output2 = cs_output2.replace('$k1', '$27') + + #print("Running MC ...") + if fname.endswith('thumb-fp-armv8.s.cs'): + mc_output = run_mc(archs[arch], code, ['-triple=thumbv8'], mc_option) + elif fname.endswith('mips64-alu-instructions.s.cs'): + mc_output = run_mc(archs[arch], code, ['-triple=mips64el', '-mcpu=mips64r2'], mc_option) + else: + mc_output = run_mc(archs[arch], code, mc_modes[(arch, mode)], mc_option) + mc_output2 = normalize_hex(mc_output) + + if arch == 'CS_ARCH_MIPS': + mc_output2 = mc_output2.replace(' 0(', '(') + + if arch == 'CS_ARCH_PPC': + mc_output2 = mc_output2.replace('.+', '') + mc_output2 = mc_output2.replace('.', '') + mc_output2 = mc_output2.replace(' 0(', '(') + + mc_output2 = mc_output2.replace(' ', '') + mc_output2 = mc_output2.replace('opaque', '') + + + if (cs_output2 != mc_output2): + asm = asm.replace(' ', '').strip().lower() + if asm != cs_output2: + print("Mismatch: %s" %line.strip()) + print("\tMC = %s" %mc_output) + print("\tCS = %s" %cs_output) + + +if __name__ == '__main__': + if len(sys.argv) == 1: + fnames = sys.stdin.readlines() + for fname in fnames: + test_file(fname.strip()) + else: + #print("Usage: ./test_mc.py ") + test_file(sys.argv[1]) + diff --git a/white_patch_detect/capstone-master/suite/test_mc.sh b/white_patch_detect/capstone-master/suite/test_mc.sh new file mode 100644 index 0000000..5430f5f --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_mc.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +# This script test all architectures by default. +# At the output are all the mismatches between Capstone (CS) & LLVM (MC). +# While most differences coming from the fact that Capstone uses more friendly +# number format, some mismatches might be because Capstone is based on older +# version of LLVM (which should be fixed in the next release) + +find MC/ -name *.cs | ./test_mc.py + +# To test just one architecture, specify the corresponsing dir: +# $ find MC/X86 -name *.cs | ./test_mc.py + +# To test just one input file, run test_mc.py with that file: +# $ ./test_mc.py MC/X86/x86-32-fma3.s.cs diff --git a/white_patch_detect/capstone-master/suite/test_python.sh b/white_patch_detect/capstone-master/suite/test_python.sh new file mode 100644 index 0000000..b3cfa5c --- /dev/null +++ b/white_patch_detect/capstone-master/suite/test_python.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +# Run all the Python tests, and send the output that to a file to be compared later +# This is useful when we want to verify if a commit (wrongly) changes the disassemble result. + +../bindings/python/test.py > /tmp/$1 +../bindings/python/test_detail.py >> /tmp/$1 +../bindings/python/test_arm.py >> /tmp/$1 +../bindings/python/test_arm64.py >> /tmp/$1 +../bindings/python/test_mips.py >> /tmp/$1 +../bindings/python/test_ppc.py >> /tmp/$1 +../bindings/python/test_sparc.py >> /tmp/$1 +../bindings/python/test_x86.py >> /tmp/$1 diff --git a/white_patch_detect/capstone-master/suite/x86odd.py b/white_patch_detect/capstone-master/suite/x86odd.py new file mode 100644 index 0000000..e9148e5 --- /dev/null +++ b/white_patch_detect/capstone-master/suite/x86odd.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python + +# Capstone Python bindings, by Nguyen Anh Quynnh +from __future__ import print_function +import sys +from capstone import * + +CODE32 = b"\xc0\xe0\x02" +CODE32 += b"\xc0\xf6\x02" # sal dh, 0 +CODE32 += b"\xc1\xf6\x00" # sal esi, 0 +CODE32 += b"\x82\xc0\x00" +CODE32 += b"\x0f\x1a\x00" # nop dword ptr [eax] +CODE32 += b"\xf7\xc0\x11\x22\x33\x44" # test eax, 0x44332211 +CODE32 += b"\xf7\xc8\x11\x22\x33\x44" # test eax, 0x44332211 +CODE32 += b"\xf7\x88\x00\x00\x00\x00\x00\x00\x00\x00" # test dword ptr [eax], 0 +CODE32 += b"\xf6\x88\x00\x00\x00\x00\x00" # test byte ptr [eax], 0 + +CODE32 += b"\xd9\xd8" # fstpnce st(0), st(0) +CODE32 += b"\xdf\xdf" # fstp st(7), st(0) + +CODE32 += b"\x0f\x20\x00" # mov eax, cr0 +CODE32 += b"\x0f\x20\x40" # mov eax, cr0 +CODE32 += b"\x0f\x20\x80" # mov eax, cr0 + +CODE32 += b"\x0f\x22\x00" # mov cr0, eax +CODE32 += b"\x0f\x22\x40" # mov cr0, eax +CODE32 += b"\x0f\x22\x80" # mov cr0, eax + +CODE32 += b"\x0f\x21\x00" # mov eax, dr0 +CODE32 += b"\x0f\x21\x40" # mov eax, dr0 +CODE32 += b"\x0f\x21\x80" # mov eax, dr0 + +CODE32 += b"\x0f\x23\x00" # mov dr0, eax +CODE32 += b"\x0f\x23\x40" # mov dr0, eax +CODE32 += b"\x0f\x23\x80" # mov dr0, eax + +CODE32 += b"\x66\x2e\x0f\x58\xc0" # addpd xmm0, xmm0 +CODE32 += b"\x2e\x66\x0f\x58\xc0" # addpd xmm0, xmm0 +CODE32 += b"\x66\xf2\x0f\x38\xf1\xc3" # crc32w %bx, %eax +CODE32 += b"\xf2\x0f\x38\xf1\x8c\xcb\xef\xbe\xad\xde" # crc32l -0x21524111(%ebx, %ecx, 8), %ecx + +CODE32_MEMREF = b"\x8b\x84\x91\x23\x01\x00\x00" +CODE32_MEMREF += b"\x8b\x04\x95\x23\x01\x00\x00" +CODE32_MEMREF += b"\x8b\x04\x95\xdd\xfe\xff\xff" +CODE32_MEMREF += b"\xa1\x23\x01\x00\x00" +CODE32_MEMREF += b"\xa1\x00\x00\x00\x00" +CODE32_MEMREF += b"\xa1\xdd\xfe\xff\xff" +CODE32_MEMREF += b"\x8b\x04\x91" + +CODE64_MEMREF = b"\xa3\x0b\x00\x00\x0f\xbe\xc0\x48\x83" +CODE64_MEMREF += b"\xa0\x71\xfa\xff\x48\x85\xc0\x48\x89" + +CODE32_ARITH = b"\x83\xe0\xf7" +CODE32_ARITH += b"\x83\xe0\x10" +CODE32_ARITH += b"\x83\xe0\x00" +CODE32_ARITH += b"\x80\x23\x10" + +CODE64_ARITH = b"\x41\x83\xe0\xfa" +CODE64_ARITH += b"\x48\x83\xe4\xf0" + +CODE32_IMM = b"\xc2\xb8\xc0" +CODE32_IMM += b"\xc2\x0f\x92" +CODE32_IMM += b"\x02\x2d\x00\x00\x00\x83" + + + +_python3 = sys.version_info.major == 3 + +all_tests = ( + (CS_ARCH_X86, CS_MODE_32, CODE32, "X86 32 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_32, CODE32, "X86 32 (ATT syntax)", CS_OPT_SYNTAX_ATT), + + (CS_ARCH_X86, CS_MODE_32, CODE32_MEMREF, "X86 32 MemRef (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_32, CODE32_MEMREF, "X86 32 MemRef (ATT syntax)", CS_OPT_SYNTAX_ATT), + (CS_ARCH_X86, CS_MODE_64, CODE64_MEMREF, "X86 64 (Intel syntax)", 0), + + (CS_ARCH_X86, CS_MODE_32, CODE32_ARITH, "X86 32 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_64, CODE64_ARITH, "X86 64 (Intel syntax)", 0), + + (CS_ARCH_X86, CS_MODE_32, CODE32_IMM, "X86 32 (Intel syntax)", 0), + (CS_ARCH_X86, CS_MODE_32, CODE32_IMM, "X86 32 (Intel syntax)", CS_OPT_SYNTAX_ATT), +) + + +def to_hex(s): + if _python3: + return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK + else: + return " ".join("0x{0:02x}".format(ord(c)) for c in s) + +# ## Test cs_disasm_quick() +def test_cs_disasm_quick(): + for (arch, mode, code, comment, syntax) in all_tests: + print("Platform: %s" % comment) + print("Code: %s" %(to_hex(code))), + print("Disasm:") + md = Cs(arch, mode) + if syntax != 0: + md.syntax = syntax + for insn in md.disasm(code, 0x1000): + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + print("--------") + + +if __name__ == '__main__': + test_cs_disasm_quick() diff --git a/white_patch_detect/capstone-master/tests/Makefile b/white_patch_detect/capstone-master/tests/Makefile new file mode 100644 index 0000000..f57eb3e --- /dev/null +++ b/white_patch_detect/capstone-master/tests/Makefile @@ -0,0 +1,175 @@ +# Capstone Disassembler Engine +# By Nguyen Anh Quynh , 2013-2014 + +include ../config.mk +include ../functions.mk + +# Verbose output? +V ?= 0 + +INCDIR = ../include +ifndef BUILDDIR +TESTDIR = . +OBJDIR = . +LIBDIR = .. +else +TESTDIR = $(BUILDDIR)/tests +OBJDIR = $(BUILDDIR)/obj/tests +LIBDIR = $(BUILDDIR) +endif + +ifeq ($(CROSS),) +CC ?= cc +else ifeq ($(ANDROID), 1) +CC = $(CROSS)/../../bin/clang +else +CC = $(CROSS)gcc +endif + + +CFLAGS += -Wall -I$(INCDIR) +LDFLAGS += -L$(LIBDIR) + +CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) +LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) + +LIBNAME = capstone + +BIN_EXT = +AR_EXT = a + +# Cygwin? +IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l) +ifeq ($(IS_CYGWIN),1) +CFLAGS := $(CFLAGS:-fPIC=) +BIN_EXT = .exe +AR_EXT = lib +else +# mingw? +IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) +ifeq ($(IS_MINGW),1) +CFLAGS := $(CFLAGS:-fPIC=) +BIN_EXT = .exe +AR_EXT = lib +endif +endif + +ifeq ($(CAPSTONE_STATIC),yes) +ifeq ($(IS_MINGW),1) +ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT) +else ifeq ($(IS_CYGWIN),1) +ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT) +else +ARCHIVE = $(LIBDIR)/lib$(LIBNAME).$(AR_EXT) +endif +endif + +.PHONY: all clean + +SOURCES = test_basic.c test_detail.c test_skipdata.c test_iter.c test_customized_mnem.c +ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_ARM +SOURCES += test_arm.c +endif +ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_ARM64 +SOURCES += test_arm64.c +endif +ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_M68K +SOURCES += test_m68k.c +endif +ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_MIPS +SOURCES += test_mips.c +endif +ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_POWERPC +SOURCES += test_ppc.c +endif +ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_SPARC +SOURCES += test_sparc.c +endif +ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_SYSZ +SOURCES += test_systemz.c +endif +ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_X86 +SOURCES += test_x86.c +endif +ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_XCORE +SOURCES += test_xcore.c +endif +ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_TMS320C64X +SOURCES += test_tms320c64x.c +endif +ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_M680X +SOURCES += test_m680x.c +endif +ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_EVM +SOURCES += test_evm.c +endif +ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_MOS65XX +SOURCES += test_mos65xx.c +endif + +OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) +BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT))) + +all: $(BINARY) + +clean: + rm -rf $(OBJS) $(BINARY) $(TESTDIR)/*.exe $(TESTDIR)/*.static $(OBJDIR)/lib$(LIBNAME).* $(OBJDIR)/$(LIBNAME).* + # remove orphan files due to renaming from test.c to test_basic.c + rm -rf $(TESTDIR)/test.o $(TESTDIR)/test.exe $(TESTDIR)/test.static $(TESTDIR)/test + +$(BINARY): $(OBJS) + +$(TESTDIR)/%$(BIN_EXT): $(OBJDIR)/%.o + @mkdir -p $(@D) +ifeq ($(V),0) +ifeq ($(CAPSTONE_SHARED),yes) + $(call log,LINK,$(notdir $@)) + @$(link-dynamic) +endif +ifeq ($(CAPSTONE_STATIC),yes) + $(call log,LINK,$(notdir $(call staticname,$@))) + @$(link-static) +endif +else +ifeq ($(CAPSTONE_SHARED),yes) + $(link-dynamic) +endif +ifeq ($(CAPSTONE_STATIC),yes) + $(link-static) +endif +endif + +$(OBJDIR)/%.o: %.c + @mkdir -p $(@D) +ifeq ($(V),0) + $(call log,CC,$(@:$(OBJDIR)/%=%)) + @$(compile) +else + $(compile) +endif + + +define link-dynamic + $(CC) $(LDFLAGS) $< -l$(LIBNAME) -o $@ +endef + + +define link-static + $(CC) $(LDFLAGS) $< $(ARCHIVE) -o $(call staticname,$@) +endef + + +staticname = $(subst $(BIN_EXT),,$(1)).static$(BIN_EXT) diff --git a/white_patch_detect/capstone-master/tests/README b/white_patch_detect/capstone-master/tests/README new file mode 100644 index 0000000..e5d3efb --- /dev/null +++ b/white_patch_detect/capstone-master/tests/README @@ -0,0 +1,31 @@ +This directory contains some test code to show how to use Capstone API. + +- test_basic.c + This code shows the most simple form of API where we only want to get basic + information out of disassembled instruction, such as address, mnemonic and + operand string. + +- test_detail.c: + This code shows how to access to architecture-neutral information in disassembled + instructions, such as implicit registers read/written, or groups of instructions + that this instruction belong to. + +- test_skipdata.c: + This code shows how to use SKIPDATA option to skip broken instructions (most likely + some data mixed with instructions) and continue to decode at the next legitimate + instructions. + +- test_iter.c: + This code shows how to use the API cs_disasm_iter() to decode one instruction at + a time inside a loop. + +- test_customized_mnem.c: + This code shows how to use MNEMONIC option to customize instruction mnemonic + at run-time, and then how to reset the engine to use the default mnemonic. + +- test_.c + These code show how to access architecture-specific information for each + architecture. + +- test_winkernel.cpp + This code shows how to use Capstone from a Windows driver. diff --git a/white_patch_detect/capstone-master/tests/test_arm.c b/white_patch_detect/capstone-master/tests/test_arm.c new file mode 100644 index 0000000..eedcc98 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_arm.c @@ -0,0 +1,354 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +static csh handle; + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + int syntax; +}; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(csh cs_handle, cs_insn *ins) +{ + cs_arm *arm; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + arm = &(ins->detail->arm); + + if (arm->op_count) + printf("\top_count: %u\n", arm->op_count); + + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch((int)op->type) { + default: + break; + case ARM_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(cs_handle, op->reg)); + break; + case ARM_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case ARM_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + printf("\t\toperands[%u].type: FP = \n", i); +#else + printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); +#endif + break; + case ARM_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != ARM_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(cs_handle, op->mem.base)); + if (op->mem.index != ARM_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(cs_handle, op->mem.index)); + if (op->mem.scale != 1) + printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.lshift != 0) + printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift); + + break; + case ARM_OP_PIMM: + printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm); + break; + case ARM_OP_CIMM: + printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm); + break; + case ARM_OP_SETEND: + printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); + break; + case ARM_OP_SYSREG: + printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg); + break; + } + + if (op->neon_lane != -1) { + printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane); + } + + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + + if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { + if (op->shift.type < ARM_SFT_ASR_REG) + // shift with constant value + printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); + else + // shift with register + printf("\t\t\tShift: %u = %s\n", op->shift.type, + cs_reg_name(cs_handle, op->shift.value)); + } + + if (op->vector_index != -1) { + printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index); + } + + if (op->subtracted) + printf("\t\tSubtracted: True\n"); + } + + if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) + printf("\tCode condition: %u\n", arm->cc); + + if (arm->update_flags) + printf("\tUpdate-flags: True\n"); + + if (arm->writeback) + printf("\tWrite-back: True\n"); + + if (arm->cps_mode) + printf("\tCPSI-mode: %u\n", arm->cps_mode); + + if (arm->cps_flag) + printf("\tCPSI-flag: %u\n", arm->cps_flag); + + if (arm->vector_data) + printf("\tVector-data: %u\n", arm->vector_data); + + if (arm->vector_size) + printf("\tVector-size: %u\n", arm->vector_size); + + if (arm->usermode) + printf("\tUser-mode: True\n"); + + if (arm->mem_barrier) + printf("\tMemory-barrier: %u\n", arm->mem_barrier); + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(cs_handle, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(cs_handle, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(cs_handle, regs_write[i])); + } + printf("\n"); + } + } + + printf("\n"); +} + +static void test() +{ +//#define ARM_CODE "\x04\xe0\x2d\xe5" // str lr, [sp, #-0x4]! +//#define ARM_CODE "\xe0\x83\x22\xe5" // str r8, [r2, #-0x3e0]! +//#define ARM_CODE "\xf1\x02\x03\x0e" // mcreq p0x2, #0x0, r0, c0x3, c0x1, #0x7 +//#define ARM_CODE "\x00\x00\xa0\xe3" // mov r0, #0x0 +//#define ARM_CODE "\x02\x30\xc1\xe7" // strb r3, [r1, r2] +//#define ARM_CODE "\x00\x00\x53\xe3" // cmp r3, #0x0 +//#define ARM_CODE "\x02\x00\xa1\xe2" // adc r0, r1, r2 +//#define ARM_CODE "\x21\x01\xa0\xe0" // adc r0, r0, r1, lsr #2 +//#define ARM_CODE "\x21\x01\xb0\xe0" // adcs r0, r0, r1, lsr #2 +//#define ARM_CODE "\x32\x03\xa1\xe0" // adc r0, r1, r2, lsr r3 +//#define ARM_CODE "\x22\x01\xa1\xe0" // adc r0, r1, r2, lsr #2 +//#define ARM_CODE "\x65\x61\x4f\x50" // subpl r6, pc, r5, ror #2 +//#define ARM_CODE "\x30\x30\x53\xe5" // ldrb r3, [r3, #-0x30] +//#define ARM_CODE "\xb6\x10\xdf\xe1" // ldrh r1, [pc, #0x6] +//#define ARM_CODE "\x02\x00\x9f\xef" // svc #0x9f0002 +//#define ARM_CODE "\x00\xc0\x27\xea" // b 0x9F0002: FIXME: disasm as "b #0x9f0000" +//#define ARM_CODE "\x12\x13\xa0\xe1" // lsl r1, r2, r3 +//#define ARM_CODE "\x82\x11\xa0\xe1" // lsl r1, r2, #0x3 +//#define ARM_CODE "\x00\xc0\xa0\xe1" // mov ip, r0 +//#define ARM_CODE "\x02\x00\x12\xe3" // tst r2, #2 +//#define ARM_CODE "\x51\x12\xa0\xe1" // asr r1, r2 +//#define ARM_CODE "\x72\x10\xef\xe6" // uxtb r1, r2 +//#define ARM_CODE "\xe0\x0a\xb7\xee" // vcvt.f64.f32 d0, s1 +//#define ARM_CODE "\x9f\x0f\x91\xe1" // ldrex r0, [r1] +//#define ARM_CODE "\x0f\x06\x20\xf4" // vld1.8 {d0, d1, d2}, [r0] +//#define ARM_CODE "\x72\x00\xa1\xe6" // sxtab r0, r1, r2 +//#define ARM_CODE "\x50\x06\x84\xf2" // vmov.i32 q0, #0x40000000 +//#define ARM_CODE "\x73\xe0\xb8\xee" // mrc p0, #5, lr, c8, c3, #3 +//#define ARM_CODE "\x12\x02\x81\xe6" // pkhbt r0, r1, r2, lsl #0x4 +//#define ARM_CODE "\x12\x00\xa0\xe6" // ssat r0, #0x1, r2 +//#define ARM_CODE "\x03\x60\x2d\xe9" // push {r0, r1, sp, lr} +//#define ARM_CODE "\x8f\x40\x60\xf4" // vld4.32 {d20, d21, d22, d23}, [r0] +//#define ARM_CODE "\xd0\x00\xc2\xe1" // ldrd r0, r1, [r2] +//#define ARM_CODE "\x08\xf0\xd0\xf5" // pld [r0, #0x8] +//#define ARM_CODE "\x10\x8b\xbc\xec" // ldc p11, c8, [r12], #64 +//#define ARM_CODE "\xd4\x30\xd2\xe1" // ldrsb r3, [r2, #0x4] +//#define ARM_CODE "\x11\x0f\xbe\xf2" // vcvt.s32.f32 d0, d1, #2 +//#define ARM_CODE "\x01\x01\x70\xe1" // cmn r0, r1, lsl #2 +//#define ARM_CODE "\x06\x00\x91\xe2" // adds r0, r1, #6 +//#define ARM_CODE "\x5b\xf0\x7f\xf5" // dmb ish +//#define ARM_CODE "\xf7\xff\xff\xfe" +//#define ARM_CODE "\x00\x20\xbd\xe8" // ldm sp!, {sp} +//#define ARM_CODE "\x00\xa0\xbd\xe8" // pop {sp, pc} +//#define ARM_CODE "\x90\x04\x0E\x00" // muleq lr, r0, r4 +//#define ARM_CODE "\x90\x24\x0E\x00" // muleq lr, r0, r4 +//#define ARM_CODE "\xb6\x10\x5f\xe1" // ldrh r1, [pc, #-6] + +#define ARM_CODE "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00" + +//#define ARM_CODE "\x86\x48\x60\xf4" + +//#define ARM_CODE2 "\xf0\x24" +//#define ARM_CODE2 "\x83\xb0" +#define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c" +//#define THUMB_CODE "\x70\x47" // bl 0x26 +//#define THUMB_CODE "\x07\xdd" // ble 0x1c +//#define THUMB_CODE "\x00\x47" // bx r0 +//#define THUMB_CODE "\x01\x47" // bx r0 +//#define THUMB_CODE "\x02\x47" // bx r0 +//#define THUMB_CODE "\x0a\xbf" // itet eq + +#define THUMB_CODE "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0" +//#define THUMB_CODE "\xe0\xf9\x4f\x07" + +#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01" +#define THUMB_MCLASS "\xef\xf3\x02\x80" +#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" + + struct platform platforms[] = { + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char *)ARM_CODE, + sizeof(ARM_CODE) - 1, + "ARM" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE, + sizeof(THUMB_CODE) - 1, + "Thumb" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)ARM_CODE2, + sizeof(ARM_CODE2) - 1, + "Thumb-mixed" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE2, + sizeof(THUMB_CODE2) - 1, + "Thumb-2 & register named with numbers", + CS_OPT_SYNTAX_NOREGNAME + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + (unsigned char*)THUMB_MCLASS, + sizeof(THUMB_MCLASS) - 1, + "Thumb-MClass" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + (unsigned char*)ARMV8, + sizeof(ARMV8) - 1, + "Arm-V8" + }, + }; + + uint64_t address = 0x80001000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + if (platforms[i].syntax) + cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(handle, &insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} + diff --git a/white_patch_detect/capstone-master/tests/test_arm64.c b/white_patch_detect/capstone-master/tests/test_arm64.c new file mode 100644 index 0000000..951f7d2 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_arm64.c @@ -0,0 +1,285 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +static csh handle; + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_arm64 *arm64; + int i; + cs_regs regs_read, regs_write; + unsigned char regs_read_count, regs_write_count; + unsigned char access; + + // detail can be NULL if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + arm64 = &(ins->detail->arm64); + if (arm64->op_count) + printf("\top_count: %u\n", arm64->op_count); + + for (i = 0; i < arm64->op_count; i++) { + cs_arm64_op *op = &(arm64->operands[i]); + switch(op->type) { + default: + break; + case ARM64_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case ARM64_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case ARM64_OP_FP: +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + printf("\t\toperands[%u].type: FP = \n", i); +#else + printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); +#endif + break; + case ARM64_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != ARM64_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != ARM64_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + case ARM64_OP_CIMM: + printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm); + break; + case ARM64_OP_REG_MRS: + printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg); + break; + case ARM64_OP_REG_MSR: + printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg); + break; + case ARM64_OP_PSTATE: + printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->pstate); + break; + case ARM64_OP_SYS: + printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys); + break; + case ARM64_OP_PREFETCH: + printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->prefetch); + break; + case ARM64_OP_BARRIER: + printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->barrier); + break; + } + + access = op->access; + switch(access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + + if (op->shift.type != ARM64_SFT_INVALID && + op->shift.value) + printf("\t\t\tShift: type = %u, value = %u\n", + op->shift.type, op->shift.value); + + if (op->ext != ARM64_EXT_INVALID) + printf("\t\t\tExt: %u\n", op->ext); + + if (op->vas != ARM64_VAS_INVALID) + printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); + + if (op->vess != ARM64_VESS_INVALID) + printf("\t\t\tVector Element Size Specifier: %u\n", op->vess); + + if (op->vector_index != -1) + printf("\t\t\tVector Index: %u\n", op->vector_index); + } + + if (arm64->update_flags) + printf("\tUpdate-flags: True\n"); + + if (arm64->writeback) + printf("\tWrite-back: True\n"); + + if (arm64->cc) + printf("\tCode-condition: %u\n", arm64->cc); + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(handle, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(handle, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(handle, regs_write[i])); + } + printf("\n"); + } + } + + printf("\n"); +} + +static void test() +{ +//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] +//#define ARM64_CODE "\x21\x7c\x00\x53" // lsr w1, w1, #0x0 +//#define ARM64_CODE "\x21\x7c\x02\x9b" +//#define ARM64_CODE "\x20\x04\x81\xda" // csneg x0, x1, x1, eq | cneg x0, x1, ne +//#define ARM64_CODE "\x20\x08\x02\x8b" // add x0, x1, x2, lsl #2 + +//#define ARM64_CODE "\x20\xcc\x20\x8b" +//#define ARM64_CODE "\xe2\x8f\x40\xa9" // ldp x2, x3, [sp, #8] +//#define ARM64_CODE "\x20\x40\x60\x1e" // fmov d0, d1 +//#define ARM64_CODE "\x20\x7c\x7d\x93" // sbfiz x0, x1, #3, #32 + +//#define ARM64_CODE "\x20\x88\x43\xb3" // bfxil x0, x1, #3, #32 +//#define ARM64_CODE "\x01\x71\x08\xd5" // sys #0, c7, c1, #0, x1 +//#define ARM64_CODE "\x00\x71\x28\xd5" // sysl x0, #0, c7, c1, #0 + +//#define ARM64_CODE "\x20\xf4\x18\x9e" // fcvtzs x0, s1, #3 +//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0: FIXME: handle as "sys" insn +//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000 +//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] +//#define ARM64_CODE "\x20\x78\x62\xf8" // ldr x0, [x1, x2, lsl #3] +//#define ARM64_CODE "\x41\x14\x44\xb3" // bfm x1, x2, #4, #5 +//#define ARM64_CODE "\x80\x23\x29\xd5" // sysl x0, #1, c2, c3, #4 +//#define ARM64_CODE "\x20\x00\x24\x1e" // fcvtas w0, s1 +//#define ARM64_CODE "\x41\x04\x40\xd2" // eor x1, x2, #0x3 +//#define ARM64_CODE "\x9f\x33\x03\xd5" // dsb osh +//#define ARM64_CODE "\x41\x10\x23\x8a" // bic x1, x2, x3, lsl #4 +//#define ARM64_CODE "\x16\x41\x3c\xd5" // mrs x22, sp_el1 +//#define ARM64_CODE "\x41\x1c\x63\x0e" // bic v1.8b, v2.8b, v3.8b +//#define ARM64_CODE "\x41\xd4\xe3\x6e" // fabd v1.2d, v2.2d, v3.2d +//#define ARM64_CODE "\x20\x8c\x62\x2e" // cmeq v0.4h, v1.4h, v2.4h +//#define ARM64_CODE "\x20\x98\x20\x4e" // cmeq v0.16b, v1.16b, #0 +//#define ARM64_CODE "\x20\x2c\x05\x4e" // smov x0, v1.b[2] +//#define ARM64_CODE "\x21\xe4\x00\x2f" // movi d1, #0xff +//#define ARM64_CODE "\x60\x78\x08\xd5" // at s1e0w, x0 // FIXME: same problem with dc ZVA +//#define ARM64_CODE "\x20\x00\xa0\xf2" // movk x0, #1, lsl #16 +//#define ARM64_CODE "\x20\x08\x00\xb1" // adds x0, x1, #0x2 +//#define ARM64_CODE "\x41\x04\x00\x0f" // movi v1.2s, #0x2 +//#define ARM64_CODE "\x06\x00\x00\x14" // b 0x44 +//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000 +//#define ARM64_CODE "\x5f\x3f\x03\xd5" // clrex +//#define ARM64_CODE "\x5f\x3e\x03\xd5" // clrex #14 +//#define ARM64_CODE "\x20\x00\x02\xab" // adds x0, x1, x2 (alias of adds x0, x1, x2, lsl #0) +//#define ARM64_CODE "\x20\xf4\x18\x9e" // fcvtzs x0, s1, #3 +//#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2 +//#define ARM64_CODE "\xd0\xb6\x1e\xd5" // msr s3_6_c11_c6_6, x16 + +//#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b" + +//#define ARM64_CODE "\x09\x00\x38\xd5" // DBarrier +//#define ARM64_CODE "\x20\xe4\x3d\x0f\xa2\x00\xae\x9e" +//#define ARM64_CODE "\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5" // DBarrier +//#define ARM64_CODE "\x10\x5b\xe8\x3c" +//#define ARM64_CODE "\x00\x18\xa0\x5f\xa2\x00\xae\x9e" + +#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" + + struct platform platforms[] = { + { + CS_ARCH_ARM64, + CS_MODE_ARM, + (unsigned char *)ARM64_CODE, + sizeof(ARM64_CODE) - 1, + "ARM-64" + }, + }; + + uint64_t address = 0x2c; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} + diff --git a/white_patch_detect/capstone-master/tests/test_basic.c b/white_patch_detect/capstone-master/tests/test_basic.c new file mode 100644 index 0000000..0103d57 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_basic.c @@ -0,0 +1,388 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; +}; + +static void print_string_hex(unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("Code: "); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + printf("\n"); +} + +static void test() +{ +#ifdef CAPSTONE_HAS_X86 +#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +#define X86_CODE32 "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng +#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" +#endif +#ifdef CAPSTONE_HAS_ARM +//#define ARM_CODE "\x04\xe0\x2d\xe5" +#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +#define THUMB_MCLASS "\xef\xf3\x02\x80" +#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" +#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +#endif +#ifdef CAPSTONE_HAS_MIPS +#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" +#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" +#endif +#ifdef CAPSTONE_HAS_ARM64 +//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw +//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2 +//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0 +//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] +#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9" +#endif +#ifdef CAPSTONE_HAS_POWERPC +#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" +#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +#endif +#ifdef CAPSTONE_HAS_SPARC +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +#endif +#ifdef CAPSTONE_HAS_SYSZ +#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +#endif +#ifdef CAPSTONE_HAS_XCORE +#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +#endif +#ifdef CAPSTONE_HAS_M68K +#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28" +#endif +#ifdef CAPSTONE_HAS_TMS320C64X +#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" +#endif +#ifdef CAPSTONE_HAS_M680X +#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" +#endif +#ifdef CAPSTONE_HAS_EVM +#define EVM_CODE "\x60\x61" +#endif + +#ifdef CAPSTONE_HAS_MOS65XX +#define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" +#endif + + + struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; + }; + struct platform platforms[] = { +#ifdef CAPSTONE_HAS_X86 + { + CS_ARCH_X86, + CS_MODE_16, + (unsigned char*)X86_CODE16, + sizeof(X86_CODE16) - 1, + "X86 16bit (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char*)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32bit (ATT syntax)", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_ATT, + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char*)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char*)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (MASM syntax)", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_MASM, + }, + { + CS_ARCH_X86, + CS_MODE_64, + (unsigned char*)X86_CODE64, + sizeof(X86_CODE64) - 1, + "X86 64 (Intel syntax)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char*)ARM_CODE, + sizeof(ARM_CODE) - 1, + "ARM" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char*)THUMB_CODE2, + sizeof(THUMB_CODE2) - 1, + "THUMB-2" + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char*)ARM_CODE2, + sizeof(ARM_CODE2) - 1, + "ARM: Cortex-A15 + NEON" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char*)THUMB_CODE, + sizeof(THUMB_CODE) - 1, + "THUMB" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + (unsigned char*)THUMB_MCLASS, + sizeof(THUMB_MCLASS) - 1, + "Thumb-MClass" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + (unsigned char*)ARMV8, + sizeof(ARMV8) - 1, + "Arm-V8" + }, +#endif +#ifdef CAPSTONE_HAS_MIPS + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_CODE, + sizeof(MIPS_CODE) - 1, + "MIPS-32 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), + (unsigned char*)MIPS_CODE2, + sizeof(MIPS_CODE2) - 1, + "MIPS-64-EL (Little-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6M, + sizeof(MIPS_32R6M) - 1, + "MIPS-32R6 | Micro (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6, + sizeof(MIPS_32R6) - 1, + "MIPS-32R6 (Big-endian)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM64 + { + CS_ARCH_ARM64, + CS_MODE_ARM, + (unsigned char*)ARM64_CODE, + sizeof(ARM64_CODE) - 1, + "ARM-64" + }, +#endif +#ifdef CAPSTONE_HAS_POWERPC + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)PPC_CODE, + sizeof(PPC_CODE) - 1, + "PPC-64" + }, + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)PPC_CODE, + sizeof(PPC_CODE) - 1, + "PPC-64, print register with number only", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_NOREGNAME + }, + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN + CS_MODE_QPX, + (unsigned char*)PPC_CODE2, + sizeof(PPC_CODE2) - 1, + "PPC-64 + QPX", + }, +#endif +#ifdef CAPSTONE_HAS_SPARC + { + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)SPARC_CODE, + sizeof(SPARC_CODE) - 1, + "Sparc" + }, + { + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + (unsigned char*)SPARCV9_CODE, + sizeof(SPARCV9_CODE) - 1, + "SparcV9" + }, +#endif +#ifdef CAPSTONE_HAS_SYSZ + { + CS_ARCH_SYSZ, + (cs_mode)0, + (unsigned char*)SYSZ_CODE, + sizeof(SYSZ_CODE) - 1, + "SystemZ" + }, +#endif +#ifdef CAPSTONE_HAS_XCORE + { + CS_ARCH_XCORE, + (cs_mode)0, + (unsigned char*)XCORE_CODE, + sizeof(XCORE_CODE) - 1, + "XCore" + }, +#endif +#ifdef CAPSTONE_HAS_M68K + { + CS_ARCH_M68K, + (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), + (unsigned char*)M68K_CODE, + sizeof(M68K_CODE) - 1, + "M68K", + }, +#endif +#ifdef CAPSTONE_HAS_TMS320C64X + { + CS_ARCH_TMS320C64X, + 0, + (unsigned char*)TMS320C64X_CODE, + sizeof(TMS320C64X_CODE) - 1, + "TMS320C64x", + }, +#endif +#ifdef CAPSTONE_HAS_M680X + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6809), + (unsigned char*)M680X_CODE, + sizeof(M680X_CODE) - 1, + "M680X_M6809", + }, +#endif +#ifdef CAPSTONE_HAS_EVM + { + CS_ARCH_EVM, + 0, + (unsigned char*)EVM_CODE, + sizeof(EVM_CODE) - 1, + "EVM", + }, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + { + CS_ARCH_MOS65XX, + 0, + (unsigned char *)MOS65XX_CODE, + sizeof(MOS65XX_CODE) - 1, + "MOS65XX" + }, +#endif + }; + + csh handle; + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + cs_err err; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + if (platforms[i].opt_type) + cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + print_string_hex(platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t\t%s\n", + insn[j].address, insn[j].mnemonic, insn[j].op_str); + } + + // print out the next offset, after the last insn + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex(platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_customized_mnem.c b/white_patch_detect/capstone-master/tests/test_customized_mnem.c new file mode 100644 index 0000000..913586e --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_customized_mnem.c @@ -0,0 +1,86 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2015 */ + +// This sample code demonstrates the option CS_OPT_MNEMONIC +// to customize instruction mnemonic. + +#include +#include + +#include +#include + +#define X86_CODE32 "\x75\x01" + +// Print out the input code in hexadecimal format +static void print_string_hex(unsigned char *str, size_t len) +{ + unsigned char *c; + + for (c = str; c < str + len; c++) { + printf("%02x ", *c & 0xff); + } + printf("\t"); +} + +// Print one instruction +static void print_insn(csh handle) +{ + cs_insn *insn; + size_t count; + + count = cs_disasm(handle, (const uint8_t *)X86_CODE32, sizeof(X86_CODE32) - 1, 0x1000, 1, &insn); + if (count) { + print_string_hex((unsigned char *)X86_CODE32, sizeof(X86_CODE32) - 1); + printf("\t%s\t%s\n", insn[0].mnemonic, insn[0].op_str); + // Free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } +} + +static void test() +{ + csh handle; + cs_err err; + // Customize mnemonic JNE to "jnz" + cs_opt_mnem my_mnem = { X86_INS_JNE, "jnz" }; + // Set .mnemonic to NULL to reset to default mnemonic + cs_opt_mnem default_mnem = { X86_INS_JNE, NULL }; + + err = cs_open(CS_ARCH_X86, CS_MODE_32, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + // 1. Print out the instruction in default setup. + printf("Disassemble X86 code with default instruction mnemonic\n"); + print_insn(handle); + + // Customized mnemonic JNE to JNZ using CS_OPT_MNEMONIC option + printf("\nNow customize engine to change mnemonic from 'JNE' to 'JNZ'\n"); + cs_option(handle, CS_OPT_MNEMONIC, (size_t)&my_mnem); + + // 2. Now print out the instruction in newly customized setup. + print_insn(handle); + + // Reset engine to use the default mnemonic of JNE + printf("\nReset engine to use the default mnemonic\n"); + cs_option(handle, CS_OPT_MNEMONIC, (size_t)&default_mnem); + + // 3. Now print out the instruction in default setup. + print_insn(handle); + + // Done + cs_close(&handle); +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_detail.c b/white_patch_detect/capstone-master/tests/test_detail.c new file mode 100644 index 0000000..2c080a5 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_detail.c @@ -0,0 +1,379 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; +}; + +static void print_string_hex(unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("Code: "); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + printf("\n"); +} + +static void test() +{ +#ifdef CAPSTONE_HAS_X86 +#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng +#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" +#endif +#ifdef CAPSTONE_HAS_ARM +//#define ARM_CODE "\x04\xe0\x2d\xe5" +#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" +#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +#define THUMB_MCLASS "\xef\xf3\x02\x80" +#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" +#endif +#ifdef CAPSTONE_HAS_MIPS +#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" +//#define MIPS_CODE "\x21\x38\x00\x01" +//#define MIPS_CODE "\x21\x30\xe6\x70" +//#define MIPS_CODE "\x1c\x00\x40\x14" +#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" +#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" +#endif +#ifdef CAPSTONE_HAS_ARM64 +//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] +//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw +//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2 +//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0 +//#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2 +//#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e" +//#define ARM64_CODE "\x21\x7c\x00\x53" +#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" +#endif +//#define THUMB_CODE "\x0a\xbf" // itet eq +//#define X86_CODE32 "\x77\x04" // ja +6 +#ifdef CAPSTONE_HAS_POWERPC +#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" +#endif +#ifdef CAPSTONE_HAS_SPARC +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +#endif +#ifdef CAPSTONE_HAS_SYSZ +#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +#endif +#ifdef CAPSTONE_HAS_XCORE +#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +#endif +#ifdef CAPSTONE_HAS_M68K +#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28" +#endif +#ifdef CAPSTONE_HAS_M680X +#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" +#endif +#ifdef CAPSTONE_HAS_MOS65XX +#define MOS65XX_CODE "\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80" +#endif + + + struct platform platforms[] = { +#ifdef CAPSTONE_HAS_X86 + { + CS_ARCH_X86, + CS_MODE_16, + (unsigned char *)X86_CODE16, + sizeof(X86_CODE32) - 1, + "X86 16bit (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32bit (ATT syntax)", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_ATT, + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_64, + (unsigned char *)X86_CODE64, + sizeof(X86_CODE64) - 1, + "X86 64 (Intel syntax)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char *)ARM_CODE, + sizeof(ARM_CODE) - 1, + "ARM" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE2, + sizeof(THUMB_CODE2) - 1, + "THUMB-2" + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char *)ARM_CODE2, + sizeof(ARM_CODE2) - 1, + "ARM: Cortex-A15 + NEON" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE, + sizeof(THUMB_CODE) - 1, + "THUMB" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), + (unsigned char*)THUMB_MCLASS, + sizeof(THUMB_MCLASS) - 1, + "Thumb-MClass" + }, + { + CS_ARCH_ARM, + (cs_mode)(CS_MODE_ARM + CS_MODE_V8), + (unsigned char*)ARMV8, + sizeof(ARMV8) - 1, + "Arm-V8" + }, +#endif +#ifdef CAPSTONE_HAS_MIPS + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + (unsigned char *)MIPS_CODE, + sizeof(MIPS_CODE) - 1, + "MIPS-32 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), + (unsigned char *)MIPS_CODE2, + sizeof(MIPS_CODE2) - 1, + "MIPS-64-EL (Little-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6M, + sizeof(MIPS_32R6M) - 1, + "MIPS-32R6 | Micro (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6, + sizeof(MIPS_32R6) - 1, + "MIPS-32R6 (Big-endian)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM64 + { + CS_ARCH_ARM64, + CS_MODE_ARM, + (unsigned char *)ARM64_CODE, + sizeof(ARM64_CODE) - 1, + "ARM-64" + }, +#endif +#ifdef CAPSTONE_HAS_POWERPC + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)PPC_CODE, + sizeof(PPC_CODE) - 1, + "PPC-64" + }, + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN + CS_MODE_QPX, + (unsigned char*)PPC_CODE2, + sizeof(PPC_CODE2) - 1, + "PPC-64 + QPX", + }, +#endif +#ifdef CAPSTONE_HAS_SPARC + { + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)SPARC_CODE, + sizeof(SPARC_CODE) - 1, + "Sparc" + }, + { + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + (unsigned char*)SPARCV9_CODE, + sizeof(SPARCV9_CODE) - 1, + "SparcV9" + }, +#endif +#ifdef CAPSTONE_HAS_SYSZ + { + CS_ARCH_SYSZ, + (cs_mode)0, + (unsigned char*)SYSZ_CODE, + sizeof(SYSZ_CODE) - 1, + "SystemZ" + }, +#endif +#ifdef CAPSTONE_HAS_XCORE + { + CS_ARCH_XCORE, + (cs_mode)0, + (unsigned char*)XCORE_CODE, + sizeof(XCORE_CODE) - 1, + "XCore" + }, +#endif +#ifdef CAPSTONE_HAS_M68K + { + CS_ARCH_M68K, + (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), + (unsigned char*)M68K_CODE, + sizeof(M68K_CODE) - 1, + "M68K", + }, +#endif +#ifdef CAPSTONE_HAS_M680X + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6809), + (unsigned char*)M680X_CODE, + sizeof(M680X_CODE) - 1, + "M680X_M6809", + }, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + { + CS_ARCH_MOS65XX, + (cs_mode)0, + (unsigned char*)MOS65XX_CODE, + sizeof(MOS65XX_CODE) - 1, + "MOS65XX", + }, +#endif + }; + + csh handle; + uint64_t address = 0x1000; + cs_insn *all_insn; + cs_detail *detail; + int i; + size_t count; + cs_err err; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + if (platforms[i].opt_type) + cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn); + if (count) { + size_t j; + int n; + + print_string_hex(platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + cs_insn *in = &(all_insn[j]); + printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", + in->address, in->mnemonic, in->op_str, + in->id, cs_insn_name(handle, in->id)); + + // print implicit registers used by this instruction + detail = in->detail; + + if (detail->regs_read_count > 0) { + printf("\tImplicit registers read: "); + for (n = 0; n < detail->regs_read_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_read[n])); + } + printf("\n"); + } + + // print implicit registers modified by this instruction + if (detail->regs_write_count > 0) { + printf("\tImplicit registers modified: "); + for (n = 0; n < detail->regs_write_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_write[n])); + } + printf("\n"); + } + + // print the groups this instruction belong to + if (detail->groups_count > 0) { + printf("\tThis instruction belongs to groups: "); + for (n = 0; n < detail->groups_count; n++) { + printf("%s ", cs_group_name(handle, detail->groups[n])); + } + printf("\n"); + } + } + + // print out the next offset, after the last insn + printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(all_insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex(platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_evm.c b/white_patch_detect/capstone-master/tests/test_evm.c new file mode 100644 index 0000000..1b21f27 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_evm.c @@ -0,0 +1,126 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2018 */ + +#include +#include + +#include +#include + +static csh handle; + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(csh cs_handle, cs_insn *ins) +{ + cs_evm *evm; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + evm = &(ins->detail->evm); + + if (evm->pop) + printf("\tPop: %u\n", evm->pop); + + if (evm->push) + printf("\tPush: %u\n", evm->push); + + if (evm->fee) + printf("\tGas fee: %u\n", evm->fee); + + if (ins->detail->groups_count) { + int j; + + printf("\tGroups: "); + for(j = 0; j < ins->detail->groups_count; j++) { + printf("%s ", cs_group_name(handle, ins->detail->groups[j])); + } + printf("\n"); + } +} + +static void test() +{ +#define EVM_CODE "\x60\x61\x50" + + struct platform platforms[] = { + { + CS_ARCH_EVM, + 0, + (unsigned char *)EVM_CODE, + sizeof(EVM_CODE) - 1, + "EVM" + }, + }; + + uint64_t address = 0x80001000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(handle, &insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} + diff --git a/white_patch_detect/capstone-master/tests/test_iter.c b/white_patch_detect/capstone-master/tests/test_iter.c new file mode 100644 index 0000000..f215ba9 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_iter.c @@ -0,0 +1,321 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +// This sample code demonstrates the APIs cs_malloc() & cs_disasm_iter(). +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; +}; + +static void print_string_hex(unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("Code: "); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + printf("\n"); +} + +static void test() +{ +#ifdef CAPSTONE_HAS_X86 +#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" +//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng +#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00" +#endif +#ifdef CAPSTONE_HAS_ARM +//#define ARM_CODE "\x04\xe0\x2d\xe5" +#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" +#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" +#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68" +#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0" +#endif +#ifdef CAPSTONE_HAS_MIPS +#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08" +//#define MIPS_CODE "\x21\x38\x00\x01" +//#define MIPS_CODE "\x21\x30\xe6\x70" +//#define MIPS_CODE "\x1c\x00\x40\x14" +#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" +#endif +#ifdef CAPSTONE_HAS_ARM64 +//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8] +//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw +//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2 +//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0 +//#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2 +//#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e" +//#define ARM64_CODE "\x21\x7c\x00\x53" +#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" +#endif +//#define THUMB_CODE "\x0a\xbf" // itet eq +//#define X86_CODE32 "\x77\x04" // ja +6 +#ifdef CAPSTONE_HAS_POWERPC +#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +#endif +#ifdef CAPSTONE_HAS_SPARC +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" +#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" +#endif +#ifdef CAPSTONE_HAS_SYSZ +#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" +#endif +#ifdef CAPSTONE_HAS_XCORE +#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" +#endif +#ifdef CAPSTONE_HAS_M680X +#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" +#endif +#ifdef CAPSTONE_HAS_MOS65XX +#define MOS65XX_CODE "\x0d\x34\x12\x08\x09\xFF\x10\x80\x20\x00\x00\x98" +#endif + + + struct platform platforms[] = { +#ifdef CAPSTONE_HAS_X86 + { + CS_ARCH_X86, + CS_MODE_16, + (unsigned char *)X86_CODE16, + sizeof(X86_CODE32) - 1, + "X86 16bit (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32bit (ATT syntax)", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_ATT, + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_64, + (unsigned char *)X86_CODE64, + sizeof(X86_CODE64) - 1, + "X86 64 (Intel syntax)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char *)ARM_CODE, + sizeof(ARM_CODE) - 1, + "ARM" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE2, + sizeof(THUMB_CODE2) - 1, + "THUMB-2" + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char *)ARM_CODE2, + sizeof(ARM_CODE2) - 1, + "ARM: Cortex-A15 + NEON" + }, + { + CS_ARCH_ARM, + CS_MODE_THUMB, + (unsigned char *)THUMB_CODE, + sizeof(THUMB_CODE) - 1, + "THUMB" + }, +#endif +#ifdef CAPSTONE_HAS_MIPS + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), + (unsigned char *)MIPS_CODE, + sizeof(MIPS_CODE) - 1, + "MIPS-32 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), + (unsigned char *)MIPS_CODE2, + sizeof(MIPS_CODE2) - 1, + "MIPS-64-EL (Little-endian)" + }, +#endif +#ifdef CAPSTONE_HAS_ARM64 + { + CS_ARCH_ARM64, + CS_MODE_ARM, + (unsigned char *)ARM64_CODE, + sizeof(ARM64_CODE) - 1, + "ARM-64" + }, +#endif +#ifdef CAPSTONE_HAS_POWERPC + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)PPC_CODE, + sizeof(PPC_CODE) - 1, + "PPC-64" + }, +#endif +#ifdef CAPSTONE_HAS_SPARC + { + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)SPARC_CODE, + sizeof(SPARC_CODE) - 1, + "Sparc" + }, + { + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + (unsigned char*)SPARCV9_CODE, + sizeof(SPARCV9_CODE) - 1, + "SparcV9" + }, +#endif +#ifdef CAPSTONE_HAS_SYSZ + { + CS_ARCH_SYSZ, + (cs_mode)0, + (unsigned char*)SYSZ_CODE, + sizeof(SYSZ_CODE) - 1, + "SystemZ" + }, +#endif +#ifdef CAPSTONE_HAS_XCORE + { + CS_ARCH_XCORE, + (cs_mode)0, + (unsigned char*)XCORE_CODE, + sizeof(XCORE_CODE) - 1, + "XCore" + }, +#endif +#ifdef CAPSTONE_HAS_M680X + { + CS_ARCH_M680X, + (cs_mode)CS_MODE_M680X_6809, + (unsigned char*)M680X_CODE, + sizeof(M680X_CODE) - 1, + "M680X_6809" + }, +#endif +#ifdef CAPSTONE_HAS_MOS65XX + { + CS_ARCH_MOS65XX, + (cs_mode)CS_MODE_LITTLE_ENDIAN, + (unsigned char*)MOS65XX_CODE, + sizeof(MOS65XX_CODE) - 1, + "MOS65XX" + }, +#endif + }; + + csh handle; + uint64_t address; + cs_insn *insn; + cs_detail *detail; + int i; + cs_err err; + const uint8_t *code; + size_t size; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + if (platforms[i].opt_type) + cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + // allocate memory for the cache to be used by cs_disasm_iter() + insn = cs_malloc(handle); + + print_string_hex(platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + address = 0x1000; + code = platforms[i].code; + size = platforms[i].size; + while(cs_disasm_iter(handle, &code, &size, &address, insn)) { + int n; + + printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", + insn->address, insn->mnemonic, insn->op_str, + insn->id, cs_insn_name(handle, insn->id)); + + // print implicit registers used by this instruction + detail = insn->detail; + + if (detail->regs_read_count > 0) { + printf("\tImplicit registers read: "); + for (n = 0; n < detail->regs_read_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_read[n])); + } + printf("\n"); + } + + // print implicit registers modified by this instruction + if (detail->regs_write_count > 0) { + printf("\tImplicit registers modified: "); + for (n = 0; n < detail->regs_write_count; n++) { + printf("%s ", cs_reg_name(handle, detail->regs_write[n])); + } + printf("\n"); + } + + // print the groups this instruction belong to + if (detail->groups_count > 0) { + printf("\tThis instruction belongs to groups: "); + for (n = 0; n < detail->groups_count; n++) { + printf("%s ", cs_group_name(handle, detail->groups[n])); + } + printf("\n"); + } + } + + printf("\n"); + + // free memory allocated by cs_malloc() + cs_free(insn, 1); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_m680x.c b/white_patch_detect/capstone-master/tests/test_m680x.c new file mode 100644 index 0000000..666161c --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_m680x.c @@ -0,0 +1,399 @@ +/* Capstone Disassembler Engine */ +/* M680X Backend by Wolfgang Schwotzer 2017 */ + +#include +#include + +#include +#include + +#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) + +#define WITH_DETAILS + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + + for (c = str; c < str + len; c++) + printf("0x%02X ", *c & 0xff); + + printf("\n"); +} + +static void print_string_hex_short(unsigned char *str, size_t len) +{ + unsigned char *c; + + for (c = str; c < str + len; c++) + printf("%02X", *c & 0xff); +} + +static const char *s_access[] = { + "UNCHANGED", "READ", "WRITE", "READ | WRITE", +}; + +static void print_read_write_regs(csh handle, cs_detail *detail) +{ + int i; + + if (detail->regs_read_count > 0) { + printf("\tRegisters read:"); + + for (i = 0; i < detail->regs_read_count; ++i) + printf(" %s", + cs_reg_name(handle, detail->regs_read[i])); + + printf("\n"); + } + + if (detail->regs_write_count > 0) { + printf("\tRegisters modified:"); + + for (i = 0; i < detail->regs_write_count; ++i) + printf(" %s", + cs_reg_name(handle, detail->regs_write[i])); + + printf("\n"); + } +} + +static void print_insn_detail(csh handle, cs_insn *insn) +{ + cs_detail *detail = insn->detail; + cs_m680x *m680x = NULL; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (detail == NULL) + return; + + m680x = &detail->m680x; + + if (m680x->op_count) + printf("\top_count: %u\n", m680x->op_count); + + for (i = 0; i < m680x->op_count; i++) { + cs_m680x_op *op = &(m680x->operands[i]); + const char *comment; + + switch ((int)op->type) { + default: + break; + + case M680X_OP_REGISTER: + comment = ""; + + if ((i == 0 && (m680x->flags & + M680X_FIRST_OP_IN_MNEM)) || + ((i == 1 && (m680x->flags & + M680X_SECOND_OP_IN_MNEM)))) + comment = " (in mnemonic)"; + + printf("\t\toperands[%u].type: REGISTER = %s%s\n", i, + cs_reg_name(handle, op->reg), comment); + break; + + case M680X_OP_CONSTANT: + printf("\t\toperands[%u].type: CONSTANT = %u\n", i, + op->const_val); + break; + + case M680X_OP_IMMEDIATE: + printf("\t\toperands[%u].type: IMMEDIATE = #%d\n", i, + op->imm); + break; + + case M680X_OP_DIRECT: + printf("\t\toperands[%u].type: DIRECT = 0x%02X\n", i, + op->direct_addr); + break; + + case M680X_OP_EXTENDED: + printf("\t\toperands[%u].type: EXTENDED %s = 0x%04X\n", + i, op->ext.indirect ? "INDIRECT" : "", + op->ext.address); + break; + + case M680X_OP_RELATIVE: + printf("\t\toperands[%u].type: RELATIVE = 0x%04X\n", i, + op->rel.address); + break; + + case M680X_OP_INDEXED: + printf("\t\toperands[%u].type: INDEXED%s\n", i, + (op->idx.flags & M680X_IDX_INDIRECT) ? + " INDIRECT" : ""); + + if (op->idx.base_reg != M680X_REG_INVALID) + printf("\t\t\tbase register: %s\n", + cs_reg_name(handle, op->idx.base_reg)); + + if (op->idx.offset_reg != M680X_REG_INVALID) + printf("\t\t\toffset register: %s\n", + cs_reg_name(handle, op->idx.offset_reg)); + + if ((op->idx.offset_bits != 0) && + (op->idx.offset_reg == M680X_REG_INVALID) && + !op->idx.inc_dec) { + printf("\t\t\toffset: %d\n", op->idx.offset); + + if (op->idx.base_reg == M680X_REG_PC) + printf("\t\t\toffset address: 0x%X\n", + op->idx.offset_addr); + + printf("\t\t\toffset bits: %u\n", + op->idx.offset_bits); + } + + if (op->idx.inc_dec) { + const char *post_pre = op->idx.flags & + M680X_IDX_POST_INC_DEC ? "post" : "pre"; + const char *inc_dec = (op->idx.inc_dec > 0) ? + "increment" : "decrement"; + + printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, + abs(op->idx.inc_dec)); + } + + break; + } + + if (op->size != 0) + printf("\t\t\tsize: %u\n", op->size); + + if (op->access != CS_AC_INVALID) + printf("\t\t\taccess: %s\n", s_access[op->access]); + + } + + print_read_write_regs(handle, detail); + + if (detail->groups_count) { + printf("\tgroups_count: %u\n", detail->groups_count); + } + + printf("\n"); +} + +static bool consistency_checks() +{ + return true; +} + +static void test() +{ +#define M6800_CODE \ + "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39" + +#define M6801_CODE \ + "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39" + +#define M6805_CODE \ + "\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c" \ + "\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe" + +#define M6808_CODE \ + "\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62" \ + "\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10" \ + "\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f" + +#define HCS08_CODE \ + "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f" \ + "\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82" + +#define M6811_CODE \ + "\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01" \ + "\x1e\x7f\x20\x00\x8f\xcf" \ + "\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f" \ + "\x18\xce\x10\x00\x18\xff\x10\x00" \ + "\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f" + +#define CPU12_CODE \ + "\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00" \ + "\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52" \ + "\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00" \ + "\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00" \ + "\x18\x3e\x18\x3f\x00" + +#define HD6301_CODE \ + "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39" + +#define M6809_CODE \ + "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81" \ + "\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00" \ + "\x11\xac\x99\x10\x00\x39" \ + \ + "\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10" \ + "\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86" \ + "\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00" \ + "\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00" \ + \ + "\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96" \ + "\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00" \ + "\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00" + + +#define HD6309_CODE \ + "\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2" \ + "\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d" \ + "\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34" \ + "\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00" + + struct platform platforms[] = { + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6301), + (unsigned char *)HD6301_CODE, + sizeof(HD6301_CODE) - 1, + "M680X_HD6301", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6309), + (unsigned char *)HD6309_CODE, + sizeof(HD6309_CODE) - 1, + "M680X_HD6309", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6800), + (unsigned char *)M6800_CODE, + sizeof(M6800_CODE) - 1, + "M680X_M6800", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6801), + (unsigned char *)M6801_CODE, + sizeof(M6801_CODE) - 1, + "M680X_M6801", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6805), + (unsigned char *)M6805_CODE, + sizeof(M6805_CODE) - 1, + "M680X_M68HC05", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6808), + (unsigned char *)M6808_CODE, + sizeof(M6808_CODE) - 1, + "M680X_M68HC08", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6809), + (unsigned char *)M6809_CODE, + sizeof(M6809_CODE) - 1, + "M680X_M6809", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_6811), + (unsigned char *)M6811_CODE, + sizeof(M6811_CODE) - 1, + "M680X_M68HC11", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_CPU12), + (unsigned char *)CPU12_CODE, + sizeof(CPU12_CODE) - 1, + "M680X_CPU12", + }, + { + CS_ARCH_M680X, + (cs_mode)(CS_MODE_M680X_HCS08), + (unsigned char *)HCS08_CODE, + sizeof(HCS08_CODE) - 1, + "M680X_HCS08", + }, + }; + + uint64_t address = 0x1000; + csh handle; + cs_insn *insn; + int i; + size_t count; + const char *nine_spaces = " "; + + if (!consistency_checks()) + abort(); + + for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, + &handle); + + if (err) { + printf("Failed on cs_open() with error returned: %u\n", + err); + abort(); + } + +#ifdef WITH_DETAILS + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); +#endif + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, + address, 0, &insn); + + if (count) { + size_t j; + + printf("********************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, + platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + int slen; + printf("0x%04X: ", (uint16_t)insn[j].address); + print_string_hex_short(insn[j].bytes, + insn[j].size); + printf("%.*s", 1 + ((5 - insn[j].size) * 2), + nine_spaces); + printf("%s", insn[j].mnemonic); + slen = (int)strlen(insn[j].mnemonic); + printf("%.*s", 1 + (5 - slen), nine_spaces); + printf("%s\n", insn[j].op_str); +#ifdef WITH_DETAILS + print_insn_detail(handle, &insn[j]); +#endif + } + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } + else { + printf("********************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_m68k.c b/white_patch_detect/capstone-master/tests/test_m68k.c new file mode 100644 index 0000000..9eb3710 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_m68k.c @@ -0,0 +1,212 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char* code; + size_t size; + const char* comment; +}; + +static csh handle; + +static void print_string_hex(const char* comment, unsigned char* str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +const char* s_addressing_modes[] = { + "", + + "Register Direct - Data", + "Register Direct - Address", + + "Register Indirect - Address", + "Register Indirect - Address with Postincrement", + "Register Indirect - Address with Predecrement", + "Register Indirect - Address with Displacement", + + "Address Register Indirect With Index - 8-bit displacement", + "Address Register Indirect With Index - Base displacement", + + "Memory indirect - Postindex", + "Memory indirect - Preindex", + + "Program Counter Indirect - with Displacement", + + "Program Counter Indirect with Index - with 8-Bit Displacement", + "Program Counter Indirect with Index - with Base Displacement", + + "Program Counter Memory Indirect - Postindexed", + "Program Counter Memory Indirect - Preindexed", + + "Absolute Data Addressing - Short", + "Absolute Data Addressing - Long", + "Immediate value", +}; + +static void print_read_write_regs(cs_detail* detail) +{ + int i; + + for (i = 0; i < detail->regs_read_count; ++i) + { + uint16_t reg_id = detail->regs_read[i]; + const char* reg_name = cs_reg_name(handle, reg_id); + printf("\treading from reg: %s\n", reg_name); + } + + for (i = 0; i < detail->regs_write_count; ++i) + { + uint16_t reg_id = detail->regs_write[i]; + const char* reg_name = cs_reg_name(handle, reg_id); + printf("\twriting to reg: %s\n", reg_name); + } +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_m68k* m68k; + cs_detail* detail; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + detail = ins->detail; + m68k = &detail->m68k; + if (m68k->op_count) + printf("\top_count: %u\n", m68k->op_count); + + print_read_write_regs(detail); + + printf("\tgroups_count: %u\n", detail->groups_count); + + for (i = 0; i < m68k->op_count; i++) { + cs_m68k_op* op = &(m68k->operands[i]); + + switch((int)op->type) { + default: + break; + case M68K_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case M68K_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, (int)op->imm); + break; + case M68K_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base_reg != M68K_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base_reg)); + if (op->mem.index_reg != M68K_REG_INVALID) { + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index_reg)); + printf("\t\t\toperands[%u].mem.index: size = %c\n", + i, op->mem.index_size ? 'l' : 'w'); + } + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.scale != 0) + printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); + + printf("\t\taddress mode: %s\n", s_addressing_modes[op->address_mode]); + break; + case M68K_OP_FP_SINGLE: + printf("\t\toperands[%u].type: FP_SINGLE\n", i); + printf("\t\t\toperands[%u].simm: %f\n", i, op->simm); + break; + case M68K_OP_FP_DOUBLE: + printf("\t\toperands[%u].type: FP_DOUBLE\n", i); + printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm); + break; + case M68K_OP_REG_BITS: + printf("\t\toperands[%u].type: REG_BITS = $%x\n", i, op->register_bits); + + } + } + + printf("\n"); +} + +static void test() +{ +#define M68K_CODE "\xf0\x10\xf0\x00\x48\xaf\xff\xff\x7f\xff\x11\xb0\x01\x37\x7f\xff\xff\xff\x12\x34\x56\x78\x01\x33\x10\x10\x10\x10\x32\x32\x32\x32\x4C\x00\x54\x04\x48\xe7\xe0\x30\x4C\xDF\x0C\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75" + struct platform platforms[] = { + { + CS_ARCH_M68K, + (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040), + (unsigned char*)M68K_CODE, + sizeof(M68K_CODE) - 1, + "M68K", + }, + }; + + uint64_t address = 0x01000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + assert(address == insn[j].address && "this means the size of the previous instruction was incorrect"); + address += insn[j].size; + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_mips.c b/white_patch_detect/capstone-master/tests/test_mips.c new file mode 100644 index 0000000..5645a48 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_mips.c @@ -0,0 +1,182 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + int i; + cs_mips *mips; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + mips = &(ins->detail->mips); + if (mips->op_count) + printf("\top_count: %u\n", mips->op_count); + + for (i = 0; i < mips->op_count; i++) { + cs_mips_op *op = &(mips->operands[i]); + switch((int)op->type) { + default: + break; + case MIPS_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case MIPS_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case MIPS_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != MIPS_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + + break; + } + + } + + printf("\n"); +} + +static void test() +{ +//#define MIPS_CODE "\x8f\xa2\x00\x00" +//#define MIPS_CODE "\x00\x00\xa7\xac\x10\x00\xa2\x8f" +//#define MIPS_CODE "\x21\x30\xe6\x70" // clo $6, $7 +//#define MIPS_CODE "\x00\x00\x00\x00" // nop +//#define MIPS_CODE "\xc6\x23\xe9\xe4" // swc1 $f9, 0x23c6($7) +//#define MIPS_CODE "\x21\x38\x00\x01" // move $7, $8 +#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" +//#define MIPS_CODE "\x04\x11\x00\x01" // bal 0x8 +#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00" +#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" +#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0" +#define MIPS_64SD "\x70\x00\xb2\xff" + + struct platform platforms[] = { + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN), + (unsigned char *)MIPS_CODE, + sizeof(MIPS_CODE) - 1, + "MIPS-32 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN), + (unsigned char *)MIPS_CODE2, + sizeof(MIPS_CODE2) - 1, + "MIPS-64-EL (Little-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6M, + sizeof(MIPS_32R6M) - 1, + "MIPS-32R6 | Micro (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN), + (unsigned char*)MIPS_32R6, + sizeof(MIPS_32R6) - 1, + "MIPS-32R6 (Big-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN), + (unsigned char *)MIPS_64SD, + sizeof(MIPS_64SD) - 1, + "MIPS-64-EL + Mips II (Little-endian)" + }, + { + CS_ARCH_MIPS, + (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN), + (unsigned char *)MIPS_64SD, + sizeof(MIPS_64SD) - 1, + "MIPS-64-EL (Little-endian)" + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_mos65xx.c b/white_patch_detect/capstone-master/tests/test_mos65xx.c new file mode 100644 index 0000000..5a81d3d --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_mos65xx.c @@ -0,0 +1,169 @@ +/* Capstone Disassembler Engine */ +/* By Sebastian Macke , 2018 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf(" 0x%02x", *c & 0xff); + } + + printf("\n"); +} + +static const char *get_am_name(mos65xx_address_mode mode) +{ + switch(mode) { + default: + case MOS65XX_AM_NONE: + return "No address mode"; + case MOS65XX_AM_IMP: + return "implied addressing (no addressing mode)"; + case MOS65XX_AM_ACC: + return "accumulator addressing"; + case MOS65XX_AM_ABS: + return "absolute addressing"; + case MOS65XX_AM_ZP: + return "zeropage addressing"; + case MOS65XX_AM_IMM: + return "8 Bit immediate value"; + case MOS65XX_AM_ABSX: + return "indexed absolute addressing by the X index register"; + case MOS65XX_AM_ABSY: + return "indexed absolute addressing by the Y index register"; + case MOS65XX_AM_INDX: + return "indexed indirect addressing by the X index register"; + case MOS65XX_AM_INDY: + return "indirect indexed addressing by the Y index register"; + case MOS65XX_AM_ZPX: + return "indexed zeropage addressing by the X index register"; + case MOS65XX_AM_ZPY: + return "indexed zeropage addressing by the Y index register"; + case MOS65XX_AM_REL: + return "relative addressing used by branches"; + case MOS65XX_AM_IND: + return "absolute indirect addressing"; + } +} + + +static void print_insn_detail(cs_insn *ins) +{ + cs_mos65xx *mos65xx; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + mos65xx = &(ins->detail->mos65xx); + + // printf("insn_detail\n"); + printf("\taddress mode: %s\n", get_am_name(mos65xx->am)); + printf("\tmodifies flags: %s\n", mos65xx->modifies_flags ? "true": "false"); + + if (mos65xx->op_count) + printf("\top_count: %u\n", mos65xx->op_count); + + for (i = 0; i < mos65xx->op_count; i++) { + cs_mos65xx_op *op = &(mos65xx->operands[i]); + switch((int)op->type) { + default: + break; + case MOS65XX_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case MOS65XX_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case MOS65XX_OP_MEM: + printf("\t\toperands[%u].type: MEM = 0x%x\n", i, op->mem); + break; + } + } +} + +static void test() +{ +#define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42" + + struct platform platforms[] = { + { + CS_ARCH_MOS65XX, + 0, + (unsigned char *)MOS65XX_CODE, + sizeof(MOS65XX_CODE) - 1, + "MOS65XX" + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + puts(""); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_ppc.c b/white_patch_detect/capstone-master/tests/test_ppc.c new file mode 100644 index 0000000..f0eceea --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_ppc.c @@ -0,0 +1,186 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static const char* get_bc_name(int bc) +{ + switch(bc) { + default: + case PPC_BC_INVALID: + return ("invalid"); + case PPC_BC_LT: + return ("lt"); + case PPC_BC_LE: + return ("le"); + case PPC_BC_EQ: + return ("eq"); + case PPC_BC_GE: + return ("ge"); + case PPC_BC_GT: + return ("gt"); + case PPC_BC_NE: + return ("ne"); + case PPC_BC_UN: + return ("un"); + case PPC_BC_NU: + return ("nu"); + case PPC_BC_SO: + return ("so"); + case PPC_BC_NS: + return ("ns"); + } +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_ppc *ppc; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + ppc = &(ins->detail->ppc); + if (ppc->op_count) + printf("\top_count: %u\n", ppc->op_count); + + for (i = 0; i < ppc->op_count; i++) { + cs_ppc_op *op = &(ppc->operands[i]); + switch((int)op->type) { + default: + break; + case PPC_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case PPC_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case PPC_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != PPC_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + case PPC_OP_CRX: + printf("\t\toperands[%u].type: CRX\n", i); + printf("\t\t\toperands[%u].crx.scale: %d\n", i, op->crx.scale); + printf("\t\t\toperands[%u].crx.reg: %s\n", i, cs_reg_name(handle, op->crx.reg)); + printf("\t\t\toperands[%u].crx.cond: %s\n", i, get_bc_name(op->crx.cond)); + break; + } + } + + if (ppc->bc != 0) + printf("\tBranch code: %u\n", ppc->bc); + + if (ppc->bh != 0) + printf("\tBranch hint: %u\n", ppc->bh); + + if (ppc->update_cr0) + printf("\tUpdate-CR0: True\n"); + + printf("\n"); +} + +static void test() +{ +#define PPC_CODE "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14" +#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f" + + struct platform platforms[] = { + { + CS_ARCH_PPC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)PPC_CODE, + sizeof(PPC_CODE) - 1, + "PPC-64", + }, + { + CS_ARCH_PPC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_QPX), + (unsigned char*)PPC_CODE2, + sizeof(PPC_CODE2) - 1, + "PPC-64 + QPX", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_skipdata.c b/white_patch_detect/capstone-master/tests/test_skipdata.c new file mode 100644 index 0000000..e27798b --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_skipdata.c @@ -0,0 +1,184 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; + cs_opt_type opt_skipdata; + size_t skipdata; +}; + +static void print_string_hex(unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("Code: "); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + printf("\n"); +} + +#ifdef CAPSTONE_HAS_ARM +static size_t CAPSTONE_API mycallback(const uint8_t *buffer, size_t buffer_size, size_t offset, void *p) +{ + // always skip 2 bytes when encountering data + return 2; +} +#endif + +static void test() +{ +#ifdef CAPSTONE_HAS_X86 +#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92" +#endif +#define RANDOM_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" + +#if defined(CAPSTONE_HAS_X86) + cs_opt_skipdata skipdata = { + // rename default "data" instruction from ".byte" to "db" + "db", + }; +#endif + +#ifdef CAPSTONE_HAS_ARM + cs_opt_skipdata skipdata_callback = { + "db", + &mycallback, + }; +#endif + + struct platform platforms[] = { +#ifdef CAPSTONE_HAS_X86 + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char*)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax) - Skip data", + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char*)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax) - Skip data with custom mnemonic", + CS_OPT_INVALID, + CS_OPT_OFF, + CS_OPT_SKIPDATA_SETUP, + (size_t) &skipdata, + }, +#endif +#ifdef CAPSTONE_HAS_ARM + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char*)RANDOM_CODE, + sizeof(RANDOM_CODE) - 1, + "Arm - Skip data", + }, + { + CS_ARCH_ARM, + CS_MODE_ARM, + (unsigned char*)RANDOM_CODE, + sizeof(RANDOM_CODE) - 1, + "Arm - Skip data with callback", + CS_OPT_INVALID, + CS_OPT_OFF, + CS_OPT_SKIPDATA_SETUP, + (size_t) &skipdata_callback, + }, +#endif + }; + + csh handle; + uint64_t address = 0x1000; + cs_insn *insn; + cs_err err; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + if (platforms[i].opt_type) + cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); + + // turn on SKIPDATA mode + cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON); + cs_option(handle, platforms[i].opt_skipdata, platforms[i].skipdata); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + print_string_hex(platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t\t%s\n", + insn[j].address, insn[j].mnemonic, insn[j].op_str); + } + + // print out the next offset, after the last insn + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex(platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + +#if 0 + #define offsetof(st, m) __builtin_offsetof(st, m) + + cs_insn insn; + printf("size: %lu\n", sizeof(insn)); + printf("@id: %lu\n", offsetof(cs_insn, id)); + printf("@address: %lu\n", offsetof(cs_insn, address)); + printf("@size: %lu\n", offsetof(cs_insn, size)); + printf("@bytes: %lu\n", offsetof(cs_insn, bytes)); + printf("@mnemonic: %lu\n", offsetof(cs_insn, mnemonic)); + printf("@op_str: %lu\n", offsetof(cs_insn, op_str)); + printf("@regs_read: %lu\n", offsetof(cs_insn, regs_read)); + printf("@regs_read_count: %lu\n", offsetof(cs_insn, regs_read_count)); + printf("@regs_write: %lu\n", offsetof(cs_insn, regs_write)); + printf("@regs_write_count: %lu\n", offsetof(cs_insn, regs_write_count)); + printf("@groups: %lu\n", offsetof(cs_insn, groups)); + printf("@groups_count: %lu\n", offsetof(cs_insn, groups_count)); + printf("@arch: %lu\n", offsetof(cs_insn, x86)); +#endif + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_sparc.c b/white_patch_detect/capstone-master/tests/test_sparc.c new file mode 100644 index 0000000..369e077 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_sparc.c @@ -0,0 +1,152 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_sparc *sparc; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + sparc = &(ins->detail->sparc); + if (sparc->op_count) + printf("\top_count: %u\n", sparc->op_count); + + for (i = 0; i < sparc->op_count; i++) { + cs_sparc_op *op = &(sparc->operands[i]); + switch((int)op->type) { + default: + break; + case SPARC_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case SPARC_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case SPARC_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + + break; + } + } + + if (sparc->cc != 0) + printf("\tCode condition: %u\n", sparc->cc); + + if (sparc->hint != 0) + printf("\tHint code: %u\n", sparc->hint); + + printf("\n"); +} + +static void test() +{ +#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" + +#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" + + struct platform platforms[] = { + { + CS_ARCH_SPARC, + CS_MODE_BIG_ENDIAN, + (unsigned char*)SPARC_CODE, + sizeof(SPARC_CODE) - 1, + "Sparc", + }, + { + CS_ARCH_SPARC, + (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), + (unsigned char*)SPARCV9_CODE, + sizeof(SPARCV9_CODE) - 1, + "SparcV9" + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_systemz.c b/white_patch_detect/capstone-master/tests/test_systemz.c new file mode 100644 index 0000000..6bdcc6f --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_systemz.c @@ -0,0 +1,145 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_sysz *sysz; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + sysz = &(ins->detail->sysz); + if (sysz->op_count) + printf("\top_count: %u\n", sysz->op_count); + + for (i = 0; i < sysz->op_count; i++) { + cs_sysz_op *op = &(sysz->operands[i]); + switch((int)op->type) { + default: + break; + case SYSZ_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case SYSZ_OP_ACREG: + printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg); + break; + case SYSZ_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case SYSZ_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != SYSZ_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != SYSZ_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.length != 0) + printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + + break; + } + } + + if (sysz->cc != 0) + printf("\tCode condition: %u\n", sysz->cc); + + printf("\n"); +} + +static void test() +{ +#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f" + + struct platform platforms[] = { + { + CS_ARCH_SYSZ, + CS_MODE_BIG_ENDIAN, + (unsigned char*)SYSZ_CODE, + sizeof(SYSZ_CODE) - 1, + "SystemZ", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_tms320c64x.c b/white_patch_detect/capstone-master/tests/test_tms320c64x.c new file mode 100644 index 0000000..86a6d76 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_tms320c64x.c @@ -0,0 +1,193 @@ +/* Capstone Disassembly Engine */ +/* TMS320C64x Backend by Fotis Loukos 2016 */ + +#include + +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_tms320c64x *tms320c64x; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + tms320c64x = &(ins->detail->tms320c64x); + if (tms320c64x->op_count) + printf("\top_count: %u\n", tms320c64x->op_count); + + for (i = 0; i < tms320c64x->op_count; i++) { + cs_tms320c64x_op *op = &(tms320c64x->operands[i]); + switch((int)op->type) { + default: + break; + case TMS320C64X_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case TMS320C64X_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case TMS320C64X_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != TMS320C64X_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + printf("\t\t\toperands[%u].mem.disptype: ", i); + if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { + printf("Invalid\n"); + printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); + } + if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { + printf("Constant\n"); + printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); + } + if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { + printf("Register\n"); + printf("\t\t\toperands[%u].mem.disp: %s\n", i, cs_reg_name(handle, op->mem.disp)); + } + printf("\t\t\toperands[%u].mem.unit: %u\n", i, op->mem.unit); + printf("\t\t\toperands[%u].mem.direction: ", i); + if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID) + printf("Invalid\n"); + if(op->mem.direction == TMS320C64X_MEM_DIR_FW) + printf("Forward\n"); + if(op->mem.direction == TMS320C64X_MEM_DIR_BW) + printf("Backward\n"); + printf("\t\t\toperands[%u].mem.modify: ", i); + if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID) + printf("Invalid\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_NO) + printf("No\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_PRE) + printf("Pre\n"); + if(op->mem.modify == TMS320C64X_MEM_MOD_POST) + printf("Post\n"); + printf("\t\t\toperands[%u].mem.scaled: %u\n", i, op->mem.scaled); + + + break; + case TMS320C64X_OP_REGPAIR: + printf("\t\toperands[%u].type: REGPAIR = %s:%s\n", i, cs_reg_name(handle, op->reg + 1), cs_reg_name(handle, op->reg)); + break; + } + } + + printf("\tFunctional unit: "); + switch(tms320c64x->funit.unit) { + case TMS320C64X_FUNIT_D: + printf("D%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_L: + printf("L%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_M: + printf("M%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_S: + printf("S%u\n", tms320c64x->funit.side); + break; + case TMS320C64X_FUNIT_NO: + printf("No Functional Unit\n"); + break; + default: + printf("Unknown (Unit %u, Side %u)\n", tms320c64x->funit.unit, tms320c64x->funit.side); + break; + } + if(tms320c64x->funit.crosspath == 1) + printf("\tCrosspath: 1\n"); + + if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID) + printf("\tCondition: [%c%s]\n", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(handle, tms320c64x->condition.reg)); + printf("\tParallel: %s\n", (tms320c64x->parallel == 1) ? "true" : "false"); + + printf("\n"); +} + +static void test() +{ +#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24" + + struct platform platforms[] = { + { + CS_ARCH_TMS320C64X, + CS_MODE_BIG_ENDIAN, + (unsigned char*)TMS320C64X_CODE, + sizeof(TMS320C64X_CODE) - 1, + "TMS320C64x", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + continue; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_winkernel.cpp b/white_patch_detect/capstone-master/tests/test_winkernel.cpp new file mode 100644 index 0000000..6413b1a --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_winkernel.cpp @@ -0,0 +1,172 @@ +/* Capstone Disassembly Engine */ +/* By Satoshi Tanda , 2016 */ + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../utils.h" // for cs_snprintf + +#ifdef __cplusplus +} +#endif + +EXTERN_C DRIVER_INITIALIZE DriverEntry; + +#pragma warning(push) +#pragma warning(disable : 4005) // 'identifier' : macro redefinition +#pragma warning(disable : 4007) // 'main': must be '__cdecl' + +// Drivers must protect floating point hardware state. See use of float. +// Use KeSaveFloatingPointState/KeRestoreFloatingPointState around floating +// point operations. Display Drivers should use the corresponding Eng... routines. +#pragma warning(disable : 28110) // Suppress this, as it is false positive. + +// "Import" existing tests into this file. All code is encaptured into unique +// namespace so that the same name does not conflict. Beware that those code +// is going to be compiled as C++ source file and not C files because this file +// is C++. + +namespace basic { +#include "test_basic.c" +} // namespace basic + +namespace detail { +#include "test_detail.c" +} // namespace detail + +namespace skipdata { +#include "test_skipdata.c" +} // namespace skipdata + +namespace iter { +#include "test_iter.c" +} // namespace iter + +namespace customized_mnem_ { +#include "test_customized_mnem.c" +} // namespace customized_mnem_ + +namespace arm { +#include "test_arm.c" +} // namespace arm + +namespace arm64 { +#include "test_arm64.c" +} // namespace arm64 + +namespace mips { +#include "test_mips.c" +} // namespace mips + +namespace m68k { +#include "test_m68k.c" +} // namespace m68k + +namespace ppc { +#include "test_ppc.c" +} // namespace ppc + +namespace sparc { +#include "test_sparc.c" +} // namespace sparc + +namespace systemz { +#include "test_systemz.c" +} // namespace systemz + +namespace x86 { +#include "test_x86.c" +} // namespace x86 + +namespace xcore { +#include "test_xcore.c" +} // namespace xcore + +#pragma warning(pop) + +// Exercises all existing regression tests +static void test() +{ + KFLOATING_SAVE float_save; + NTSTATUS status; + + // Any of Capstone APIs cannot be called at IRQL higher than DISPATCH_LEVEL + // since our malloc implementation using ExAllocatePoolWithTag() is able to + // allocate memory only up to the DISPATCH_LEVEL level. + NT_ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL); + + // On a 32bit driver, KeSaveFloatingPointState() is required before using any + // Capstone function because Capstone can access to the MMX/x87 registers and + // 32bit Windows requires drivers to use KeSaveFloatingPointState() before and + // KeRestoreFloatingPointState() after accessing them. See "Using Floating + // Point or MMX in a WDM Driver" on MSDN for more details. + status = KeSaveFloatingPointState(&float_save); + if (!NT_SUCCESS(status)) { + printf("ERROR: Failed to save floating point state!\n"); + return; + } + + basic::test(); + detail::test(); + skipdata::test(); + iter::test(); + customized_mnem_::test(); + arm::test(); + arm64::test(); + mips::test(); + m68k::test(); + ppc::test(); + sparc::test(); + systemz::test(); + x86::test(); + xcore::test(); + + // Restores the nonvolatile floating-point context. + KeRestoreFloatingPointState(&float_save); +} + +// Functional test for cs_winkernel_vsnprintf() +static void cs_winkernel_vsnprintf_test() +{ + char buf[10]; + bool ok = true; + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "") == 0 && strcmp(buf, "") == 0); + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "0") == 1 && strcmp(buf, "0") == 0); + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "012345678") == 9 && strcmp(buf, "012345678") == 0); + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "0123456789") == 10 && strcmp(buf, "012345678") == 0); + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "01234567890") == 11 && strcmp(buf, "012345678") == 0); + ok = (ok && cs_snprintf(buf, sizeof(buf), "%s", "0123456789001234567890") == 22 && strcmp(buf, "012345678") == 0); + if (!ok) { + printf("ERROR: cs_winkernel_vsnprintf_test() did not produce expected results!\n"); + } +} + +// Driver entry point +EXTERN_C NTSTATUS DriverEntry(PDRIVER_OBJECT DriverObject, PUNICODE_STRING RegistryPath) +{ + UNREFERENCED_PARAMETER(DriverObject); + UNREFERENCED_PARAMETER(RegistryPath); + cs_winkernel_vsnprintf_test(); + test(); + return STATUS_CANCELLED; +} + +// This functions mimics printf() but does not return the same value as printf() +// would do. printf() is required to exercise regression tests. +_Use_decl_annotations_ +int __cdecl printf(const char * format, ...) +{ + NTSTATUS status; + va_list args; + + va_start(args, format); + status = vDbgPrintEx(DPFLTR_DEFAULT_ID, DPFLTR_ERROR_LEVEL, format, args); + va_end(args); + return NT_SUCCESS(status); +} diff --git a/white_patch_detect/capstone-master/tests/test_x86.c b/white_patch_detect/capstone-master/tests/test_x86.c new file mode 100644 index 0000000..4d983a5 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_x86.c @@ -0,0 +1,487 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013 */ + +#include +#include + +#include +#include + +static csh handle; + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; + cs_opt_type opt_type; + cs_opt_value opt_value; +}; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static const char *get_eflag_name(uint64_t flag) +{ + switch(flag) { + default: + return NULL; + case X86_EFLAGS_UNDEFINED_OF: + return "UNDEF_OF"; + case X86_EFLAGS_UNDEFINED_SF: + return "UNDEF_SF"; + case X86_EFLAGS_UNDEFINED_ZF: + return "UNDEF_ZF"; + case X86_EFLAGS_MODIFY_AF: + return "MOD_AF"; + case X86_EFLAGS_UNDEFINED_PF: + return "UNDEF_PF"; + case X86_EFLAGS_MODIFY_CF: + return "MOD_CF"; + case X86_EFLAGS_MODIFY_SF: + return "MOD_SF"; + case X86_EFLAGS_MODIFY_ZF: + return "MOD_ZF"; + case X86_EFLAGS_UNDEFINED_AF: + return "UNDEF_AF"; + case X86_EFLAGS_MODIFY_PF: + return "MOD_PF"; + case X86_EFLAGS_UNDEFINED_CF: + return "UNDEF_CF"; + case X86_EFLAGS_MODIFY_OF: + return "MOD_OF"; + case X86_EFLAGS_RESET_OF: + return "RESET_OF"; + case X86_EFLAGS_RESET_CF: + return "RESET_CF"; + case X86_EFLAGS_RESET_DF: + return "RESET_DF"; + case X86_EFLAGS_RESET_IF: + return "RESET_IF"; + case X86_EFLAGS_TEST_OF: + return "TEST_OF"; + case X86_EFLAGS_TEST_SF: + return "TEST_SF"; + case X86_EFLAGS_TEST_ZF: + return "TEST_ZF"; + case X86_EFLAGS_TEST_PF: + return "TEST_PF"; + case X86_EFLAGS_TEST_CF: + return "TEST_CF"; + case X86_EFLAGS_RESET_SF: + return "RESET_SF"; + case X86_EFLAGS_RESET_AF: + return "RESET_AF"; + case X86_EFLAGS_RESET_TF: + return "RESET_TF"; + case X86_EFLAGS_RESET_NT: + return "RESET_NT"; + case X86_EFLAGS_PRIOR_OF: + return "PRIOR_OF"; + case X86_EFLAGS_PRIOR_SF: + return "PRIOR_SF"; + case X86_EFLAGS_PRIOR_ZF: + return "PRIOR_ZF"; + case X86_EFLAGS_PRIOR_AF: + return "PRIOR_AF"; + case X86_EFLAGS_PRIOR_PF: + return "PRIOR_PF"; + case X86_EFLAGS_PRIOR_CF: + return "PRIOR_CF"; + case X86_EFLAGS_PRIOR_TF: + return "PRIOR_TF"; + case X86_EFLAGS_PRIOR_IF: + return "PRIOR_IF"; + case X86_EFLAGS_PRIOR_DF: + return "PRIOR_DF"; + case X86_EFLAGS_TEST_NT: + return "TEST_NT"; + case X86_EFLAGS_TEST_DF: + return "TEST_DF"; + case X86_EFLAGS_RESET_PF: + return "RESET_PF"; + case X86_EFLAGS_PRIOR_NT: + return "PRIOR_NT"; + case X86_EFLAGS_MODIFY_TF: + return "MOD_TF"; + case X86_EFLAGS_MODIFY_IF: + return "MOD_IF"; + case X86_EFLAGS_MODIFY_DF: + return "MOD_DF"; + case X86_EFLAGS_MODIFY_NT: + return "MOD_NT"; + case X86_EFLAGS_MODIFY_RF: + return "MOD_RF"; + case X86_EFLAGS_SET_CF: + return "SET_CF"; + case X86_EFLAGS_SET_DF: + return "SET_DF"; + case X86_EFLAGS_SET_IF: + return "SET_IF"; + } +} + +static const char *get_fpu_flag_name(uint64_t flag) +{ + switch (flag) { + default: + return NULL; + case X86_FPU_FLAGS_MODIFY_C0: + return "MOD_C0"; + case X86_FPU_FLAGS_MODIFY_C1: + return "MOD_C1"; + case X86_FPU_FLAGS_MODIFY_C2: + return "MOD_C2"; + case X86_FPU_FLAGS_MODIFY_C3: + return "MOD_C3"; + case X86_FPU_FLAGS_RESET_C0: + return "RESET_C0"; + case X86_FPU_FLAGS_RESET_C1: + return "RESET_C1"; + case X86_FPU_FLAGS_RESET_C2: + return "RESET_C2"; + case X86_FPU_FLAGS_RESET_C3: + return "RESET_C3"; + case X86_FPU_FLAGS_SET_C0: + return "SET_C0"; + case X86_FPU_FLAGS_SET_C1: + return "SET_C1"; + case X86_FPU_FLAGS_SET_C2: + return "SET_C2"; + case X86_FPU_FLAGS_SET_C3: + return "SET_C3"; + case X86_FPU_FLAGS_UNDEFINED_C0: + return "UNDEF_C0"; + case X86_FPU_FLAGS_UNDEFINED_C1: + return "UNDEF_C1"; + case X86_FPU_FLAGS_UNDEFINED_C2: + return "UNDEF_C2"; + case X86_FPU_FLAGS_UNDEFINED_C3: + return "UNDEF_C3"; + case X86_FPU_FLAGS_TEST_C0: + return "TEST_C0"; + case X86_FPU_FLAGS_TEST_C1: + return "TEST_C1"; + case X86_FPU_FLAGS_TEST_C2: + return "TEST_C2"; + case X86_FPU_FLAGS_TEST_C3: + return "TEST_C3"; + } +} + +static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins) +{ + int count, i; + cs_x86 *x86; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + x86 = &(ins->detail->x86); + + print_string_hex("\tPrefix:", x86->prefix, 4); + + print_string_hex("\tOpcode:", x86->opcode, 4); + + printf("\trex: 0x%x\n", x86->rex); + + printf("\taddr_size: %u\n", x86->addr_size); + printf("\tmodrm: 0x%x\n", x86->modrm); + if (x86->encoding.modrm_offset != 0) { + printf("\tmodrm_offset: 0x%x\n", x86->encoding.modrm_offset); + } + + printf("\tdisp: 0x%" PRIx64 "\n", x86->disp); + if (x86->encoding.disp_offset != 0) { + printf("\tdisp_offset: 0x%x\n", x86->encoding.disp_offset); + } + + if (x86->encoding.disp_size != 0) { + printf("\tdisp_size: 0x%x\n", x86->encoding.disp_size); + } + + // SIB is not available in 16-bit mode + if ((mode & CS_MODE_16) == 0) { + printf("\tsib: 0x%x\n", x86->sib); + if (x86->sib_base != X86_REG_INVALID) + printf("\t\tsib_base: %s\n", cs_reg_name(handle, x86->sib_base)); + if (x86->sib_index != X86_REG_INVALID) + printf("\t\tsib_index: %s\n", cs_reg_name(handle, x86->sib_index)); + if (x86->sib_scale != 0) + printf("\t\tsib_scale: %d\n", x86->sib_scale); + } + + // XOP code condition + if (x86->xop_cc != X86_XOP_CC_INVALID) { + printf("\txop_cc: %u\n", x86->xop_cc); + } + + // SSE code condition + if (x86->sse_cc != X86_SSE_CC_INVALID) { + printf("\tsse_cc: %u\n", x86->sse_cc); + } + + // AVX code condition + if (x86->avx_cc != X86_AVX_CC_INVALID) { + printf("\tavx_cc: %u\n", x86->avx_cc); + } + + // AVX Suppress All Exception + if (x86->avx_sae) { + printf("\tavx_sae: %u\n", x86->avx_sae); + } + + // AVX Rounding Mode + if (x86->avx_rm != X86_AVX_RM_INVALID) { + printf("\tavx_rm: %u\n", x86->avx_rm); + } + + // Print out all immediate operands + count = cs_op_count(ud, ins, X86_OP_IMM); + if (count) { + printf("\timm_count: %u\n", count); + for (i = 1; i < count + 1; i++) { + int index = cs_op_index(ud, ins, X86_OP_IMM, i); + printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm); + if (x86->encoding.imm_offset != 0) { + printf("\timm_offset: 0x%x\n", x86->encoding.imm_offset); + } + + if (x86->encoding.imm_size != 0) { + printf("\timm_size: 0x%x\n", x86->encoding.imm_size); + } + } + } + + if (x86->op_count) + printf("\top_count: %u\n", x86->op_count); + + // Print out all operands + for (i = 0; i < x86->op_count; i++) { + cs_x86_op *op = &(x86->operands[i]); + + switch((int)op->type) { + case X86_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case X86_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); + break; + case X86_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.segment != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(handle, op->mem.segment)); + if (op->mem.base != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != X86_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); + if (op->mem.scale != 1) + printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); + break; + default: + break; + } + + // AVX broadcast type + if (op->avx_bcast != X86_AVX_BCAST_INVALID) + printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast); + + // AVX zero opmask {z} + if (op->avx_zero_opmask != false) + printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i); + + printf("\t\toperands[%u].size: %u\n", i, op->size); + + switch(op->access) { + default: + break; + case CS_AC_READ: + printf("\t\toperands[%u].access: READ\n", i); + break; + case CS_AC_WRITE: + printf("\t\toperands[%u].access: WRITE\n", i); + break; + case CS_AC_READ | CS_AC_WRITE: + printf("\t\toperands[%u].access: READ | WRITE\n", i); + break; + } + } + + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(ud, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for(i = 0; i < regs_read_count; i++) { + printf(" %s", cs_reg_name(handle, regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for(i = 0; i < regs_write_count; i++) { + printf(" %s", cs_reg_name(handle, regs_write[i])); + } + printf("\n"); + } + } + + if (x86->eflags || x86->fpu_flags) { + for(i = 0; i < ins->detail->groups_count; i++) { + if (ins->detail->groups[i] == X86_GRP_FPU) { + printf("\tFPU_FLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->fpu_flags & ((uint64_t)1 << i)) { + printf(" %s", get_fpu_flag_name((uint64_t)1 << i)); + } + printf("\n"); + break; + } + } + + if (i == ins->detail->groups_count) { + printf("\tEFLAGS:"); + for(i = 0; i <= 63; i++) + if (x86->eflags & ((uint64_t)1 << i)) { + printf(" %s", get_eflag_name((uint64_t)1 << i)); + } + printf("\n"); + } + } + + printf("\n"); +} + +static void test() +{ +//#define X86_CODE32 "\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x78\x56\x00\x00" +//#define X86_CODE32 "\x05\x78\x56\x00\x00" +//#define X86_CODE32 "\x01\xd8" +//#define X86_CODE32 "\x05\x23\x01\x00\x00" +//#define X86_CODE32 "\x8d\x87\x89\x67\x00\x00" +//#define X86_CODE32 "\xa1\x13\x48\x6d\x3a\x8b\x81\x23\x01\x00\x00\x8b\x84\x39\x23\x01\x00\x00" +//#define X86_CODE32 "\xb4\xc6" // mov ah, 0x6c +//#define X86_CODE32 "\x77\x04" // ja +6 +#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" +//#define X86_CODE64 "\xe9\x79\xff\xff\xff" // jmp 0xf7e + +#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc" +#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff" +//#define X86_CODE32 "\x05\x23\x01\x00\x00\x0f\x01\xda" +//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng +//#define X86_CODE32 "\x64\xa1\x18\x00\x00\x00" // mov eax, dword ptr fs:[18] +//#define X86_CODE32 "\x64\xa3\x00\x00\x00\x00" // mov [fs:0x0], eax +//#define X86_CODE32 "\xd1\xe1" // shl ecx, 1 +//#define X86_CODE32 "\xd1\xc8" // ror eax, 1 +//#define X86_CODE32 "\x83\xC0\x80" // add eax, -x80 +//#define X86_CODE32 "\xe8\x26\xfe\xff\xff" // call 0xe2b +//#define X86_CODE32 "\xcd\x80" // int 0x80 +//#define X86_CODE32 "\x24\xb8" // and $0xb8,%al +//#define X86_CODE32 "\xf0\x01\xd8" // lock add eax,ebx +//#define X86_CODE32 "\xf3\xaa" // rep stosb +//#define X86_CODE32 "\x81\xc6\x23\x01\x00\x00" + + struct platform platforms[] = { + { + CS_ARCH_X86, + CS_MODE_16, + (unsigned char *)X86_CODE16, + sizeof(X86_CODE16) - 1, + "X86 16bit (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (AT&T syntax)", + CS_OPT_SYNTAX, + CS_OPT_SYNTAX_ATT, + }, + { + CS_ARCH_X86, + CS_MODE_32, + (unsigned char *)X86_CODE32, + sizeof(X86_CODE32) - 1, + "X86 32 (Intel syntax)" + }, + { + CS_ARCH_X86, + CS_MODE_64, + (unsigned char *)X86_CODE64, + sizeof(X86_CODE64) - 1, + "X86 64 (Intel syntax)" + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + if (platforms[i].opt_type) + cs_option(handle, platforms[i].opt_type, platforms[i].opt_value); + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(handle, platforms[i].mode, &insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/tests/test_xcore.c b/white_patch_detect/capstone-master/tests/test_xcore.c new file mode 100644 index 0000000..12cc1f1 --- /dev/null +++ b/white_patch_detect/capstone-master/tests/test_xcore.c @@ -0,0 +1,140 @@ +/* Capstone Disassembler Engine */ +/* By Nguyen Anh Quynh , 2013-2014 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + const char *comment; +}; + +static csh handle; + +static void print_string_hex(const char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_xcore *xcore; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + xcore = &(ins->detail->xcore); + if (xcore->op_count) + printf("\top_count: %u\n", xcore->op_count); + + for (i = 0; i < xcore->op_count; i++) { + cs_xcore_op *op = &(xcore->operands[i]); + switch((int)op->type) { + default: + break; + case XCORE_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); + break; + case XCORE_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); + break; + case XCORE_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != XCORE_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.index != XCORE_REG_INVALID) + printf("\t\t\toperands[%u].mem.index: REG = %s\n", + i, cs_reg_name(handle, op->mem.index)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + if (op->mem.direct != 1) + printf("\t\t\toperands[%u].mem.direct: -1\n", i); + + + break; + } + } + + printf("\n"); +} + +static void test() +{ +#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7" + + struct platform platforms[] = { + { + CS_ARCH_XCORE, + CS_MODE_BIG_ENDIAN, + (unsigned char*)XCORE_CODE, + sizeof(XCORE_CODE) - 1, + "XCore", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { + cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", err); + abort(); + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + abort(); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/white_patch_detect/capstone-master/utils.c b/white_patch_detect/capstone-master/utils.c new file mode 100644 index 0000000..7ca0425 --- /dev/null +++ b/white_patch_detect/capstone-master/utils.c @@ -0,0 +1,139 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#include +#else +#include +#endif +#include + +#include "utils.h" + +// create a cache for fast id lookup +static unsigned short *make_id2insn(const insn_map *insns, unsigned int size) +{ + // NOTE: assume that the max id is always put at the end of insns array + unsigned short max_id = insns[size - 1].id; + unsigned short i; + + unsigned short *cache = (unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache)); + + for (i = 1; i < size; i++) + cache[insns[i].id] = i; + + return cache; +} + +// look for @id in @insns, given its size in @max. first time call will update @cache. +// return 0 if not found +unsigned short insn_find(const insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache) +{ + if (id > insns[max - 1].id) + return 0; + + if (*cache == NULL) + *cache = make_id2insn(insns, max); + + return (*cache)[id]; +} + +int name2id(const name_map* map, int max, const char *name) +{ + int i; + + for (i = 0; i < max; i++) { + if (!strcmp(map[i].name, name)) { + return map[i].id; + } + } + + // nothing match + return -1; +} + +const char *id2name(const name_map* map, int max, const unsigned int id) +{ + int i; + + for (i = 0; i < max; i++) { + if (map[i].id == id) { + return map[i].name; + } + } + + // nothing match + return NULL; +} + +// count number of positive members in a list. +// NOTE: list must be guaranteed to end in 0 +unsigned int count_positive(const uint16_t *list) +{ + unsigned int c; + + for (c = 0; list[c] > 0; c++); + + return c; +} + +// count number of positive members in a list. +// NOTE: list must be guaranteed to end in 0 +unsigned int count_positive8(const unsigned char *list) +{ + unsigned int c; + + for (c = 0; list[c] > 0; c++); + + return c; +} + +char *cs_strdup(const char *str) +{ + size_t len = strlen(str)+ 1; + void *new = cs_mem_malloc(len); + + if (new == NULL) + return NULL; + + return (char *)memmove(new, str, len); +} + +// we need this since Windows doesn't have snprintf() +int cs_snprintf(char *buffer, size_t size, const char *fmt, ...) +{ + int ret; + + va_list ap; + va_start(ap, fmt); + ret = cs_vsnprintf(buffer, size, fmt, ap); + va_end(ap); + + return ret; +} + +bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id) +{ + int i; + + for (i = 0; i < max; i++) { + if (arr[i] == id) + return true; + } + + return false; +} + +bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id) +{ + int i; + + for (i = 0; i < max; i++) { + if (arr[i] == id) + return true; + } + + return false; +} + diff --git a/white_patch_detect/capstone-master/utils.h b/white_patch_detect/capstone-master/utils.h new file mode 100644 index 0000000..d8fe2cb --- /dev/null +++ b/white_patch_detect/capstone-master/utils.h @@ -0,0 +1,72 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifndef CS_UTILS_H +#define CS_UTILS_H + +#if defined(CAPSTONE_HAS_OSXKERNEL) +#include +#else +#include +#include "include/capstone/capstone.h" +#endif +#include "cs_priv.h" + +// threshold number, so above this number will be printed in hexa mode +#define HEX_THRESHOLD 9 + +// map instruction to its characteristics +typedef struct insn_map { + unsigned short id; + unsigned short mapid; +#ifndef CAPSTONE_DIET + uint16_t regs_use[12]; // list of implicit registers used by this instruction + uint16_t regs_mod[20]; // list of implicit registers modified by this instruction + unsigned char groups[8]; // list of group this instruction belong to + bool branch; // branch instruction? + bool indirect_branch; // indirect branch instruction? +#endif +} insn_map; + +// look for @id in @m, given its size in @max. first time call will update @cache. +// return 0 if not found +unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id, unsigned short **cache); + +// map id to string +typedef struct name_map { + unsigned int id; + const char *name; +} name_map; + +// map a name to its ID +// return 0 if not found +int name2id(const name_map* map, int max, const char *name); + +// map ID to a name +// return NULL if not found +const char *id2name(const name_map* map, int max, const unsigned int id); + +// count number of positive members in a list. +// NOTE: list must be guaranteed to end in 0 +unsigned int count_positive(const uint16_t *list); +unsigned int count_positive8(const unsigned char *list); + +#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) +#define MATRIX_SIZE(a) (sizeof(a[0])/sizeof(a[0][0])) + +char *cs_strdup(const char *str); + +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +// we need this since Windows doesn't have snprintf() +int cs_snprintf(char *buffer, size_t size, const char *fmt, ...); + +#define CS_AC_IGNORE (1 << 7) + +// check if an id is existent in an array +bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id); + +bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id); + +#endif + diff --git a/white_patch_detect/capstone-master/windows/README b/white_patch_detect/capstone-master/windows/README new file mode 100644 index 0000000..8d3ccbe --- /dev/null +++ b/white_patch_detect/capstone-master/windows/README @@ -0,0 +1 @@ +This directory contains code specific to Windows platforms. diff --git a/white_patch_detect/capstone-master/windows/winkernel_mm.c b/white_patch_detect/capstone-master/windows/winkernel_mm.c new file mode 100644 index 0000000..a9f87ce --- /dev/null +++ b/white_patch_detect/capstone-master/windows/winkernel_mm.c @@ -0,0 +1,128 @@ +/* Capstone Disassembly Engine */ +/* By Satoshi Tanda , 2016 */ + +#include "winkernel_mm.h" +#include +#include + +// A pool tag for memory allocation +static const ULONG CS_WINKERNEL_POOL_TAG = 'kwsC'; + + +// A structure to implement realloc() +typedef struct _CS_WINKERNEL_MEMBLOCK { + size_t size; // A number of bytes allocated + __declspec(align(MEMORY_ALLOCATION_ALIGNMENT)) + char data[ANYSIZE_ARRAY]; // An address returned to a caller +} CS_WINKERNEL_MEMBLOCK; + + +// free() +void CAPSTONE_API cs_winkernel_free(void *ptr) +{ + if (ptr) { + ExFreePoolWithTag(CONTAINING_RECORD(ptr, CS_WINKERNEL_MEMBLOCK, data), CS_WINKERNEL_POOL_TAG); + } +} + +// malloc() +void * CAPSTONE_API cs_winkernel_malloc(size_t size) +{ + // Disallow zero length allocation because they waste pool header space and, + // in many cases, indicate a potential validation issue in the calling code. + NT_ASSERT(size); + + // FP; a use of NonPagedPool is required for Windows 7 support +#pragma prefast(suppress : 30030) // Allocating executable POOL_TYPE memory + size_t number_of_bytes = 0; + CS_WINKERNEL_MEMBLOCK *block = NULL; + // A specially crafted size value can trigger the overflow. + // If the sum in a value that overflows or underflows the capacity of the type, + // the function returns NULL. + if (!NT_SUCCESS(RtlSizeTAdd(size, FIELD_OFFSET(CS_WINKERNEL_MEMBLOCK, data), &number_of_bytes))) { + return NULL; + } + block = (CS_WINKERNEL_MEMBLOCK *)ExAllocatePoolWithTag( + NonPagedPool, number_of_bytes, CS_WINKERNEL_POOL_TAG); + if (!block) { + return NULL; + } + block->size = size; + + return block->data; +} + +// calloc() +void * CAPSTONE_API cs_winkernel_calloc(size_t n, size_t size) +{ + size_t total = n * size; + + void *new_ptr = cs_winkernel_malloc(total); + if (!new_ptr) { + return NULL; + } + + return RtlFillMemory(new_ptr, total, 0); +} + +// realloc() +void * CAPSTONE_API cs_winkernel_realloc(void *ptr, size_t size) +{ + void *new_ptr = NULL; + size_t current_size = 0; + size_t smaller_size = 0; + + if (!ptr) { + return cs_winkernel_malloc(size); + } + + new_ptr = cs_winkernel_malloc(size); + if (!new_ptr) { + return NULL; + } + + current_size = CONTAINING_RECORD(ptr, CS_WINKERNEL_MEMBLOCK, data)->size; + smaller_size = (current_size < size) ? current_size : size; + RtlCopyMemory(new_ptr, ptr, smaller_size); + cs_winkernel_free(ptr); + + return new_ptr; +} + +// vsnprintf(). _vsnprintf() is available for drivers, but it differs from +// vsnprintf() in a return value and when a null-terminator is set. +// cs_winkernel_vsnprintf() takes care of those differences. +#pragma warning(push) +// Banned API Usage : _vsnprintf is a Banned API as listed in dontuse.h for +// security purposes. +#pragma warning(disable : 28719) +int CAPSTONE_API cs_winkernel_vsnprintf(char *buffer, size_t count, const char *format, va_list argptr) +{ + int result = _vsnprintf(buffer, count, format, argptr); + + // _vsnprintf() returns -1 when a string is truncated, and returns "count" + // when an entire string is stored but without '\0' at the end of "buffer". + // In both cases, null-terminator needs to be added manually. + if (result == -1 || (size_t)result == count) { + buffer[count - 1] = '\0'; + } + + if (result == -1) { + // In case when -1 is returned, the function has to get and return a number + // of characters that would have been written. This attempts so by retrying + // the same conversion with temp buffer that is most likely big enough to + // complete formatting and get a number of characters that would have been + // written. + char* tmp = cs_winkernel_malloc(0x1000); + if (!tmp) { + return result; + } + + result = _vsnprintf(tmp, 0x1000, format, argptr); + NT_ASSERT(result != -1); + cs_winkernel_free(tmp); + } + + return result; +} +#pragma warning(pop) diff --git a/white_patch_detect/capstone-master/windows/winkernel_mm.h b/white_patch_detect/capstone-master/windows/winkernel_mm.h new file mode 100644 index 0000000..ed743f3 --- /dev/null +++ b/white_patch_detect/capstone-master/windows/winkernel_mm.h @@ -0,0 +1,23 @@ +/* Capstone Disassembly Engine */ +/* By Satoshi Tanda , 2016 */ + +#ifndef CS_WINDOWS_WINKERNEL_MM_H +#define CS_WINDOWS_WINKERNEL_MM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +void CAPSTONE_API cs_winkernel_free(void *ptr); +void * CAPSTONE_API cs_winkernel_malloc(size_t size); +void * CAPSTONE_API cs_winkernel_calloc(size_t n, size_t size); +void * CAPSTONE_API cs_winkernel_realloc(void *ptr, size_t size); +int CAPSTONE_API cs_winkernel_vsnprintf(char *buffer, size_t count, const char *format, va_list argptr); + +#ifdef __cplusplus +} +#endif + +#endif // CS_WINDOWS_WINKERNEL_MM_H diff --git a/white_patch_detect/capstone-master/windowsce/.gitignore b/white_patch_detect/capstone-master/windowsce/.gitignore new file mode 100644 index 0000000..49fbbf5 --- /dev/null +++ b/white_patch_detect/capstone-master/windowsce/.gitignore @@ -0,0 +1,13 @@ +# Object files +*.obj + +# Libraries +*.lib + +# Shared objects (inc. Windows DLLs) +*.dll + +# VisualStudio +*.exp +*.map +*.pdb diff --git a/white_patch_detect/capstone-master/windowsce/COMPILE.md b/white_patch_detect/capstone-master/windowsce/COMPILE.md new file mode 100644 index 0000000..d83b5b5 --- /dev/null +++ b/white_patch_detect/capstone-master/windowsce/COMPILE.md @@ -0,0 +1,124 @@ +This documentation explains how to compile Capstone for: +- Windows CE 7, a.k.a, [Windows Embedded Compact 7](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-7.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html). +- Windows CE 8, a.k.a, [Windows Embedded Compact 2013](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-2013.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html). + +To build Capstone for a different platform, please refer to `COMPILE.TXT`. + +# Prerequisites + +We support the following scenario regarding the build machine: +- Build running on Microsoft Windows. +- The C Software Develepment Kit of the target Windows CE **device** installed. +- Only for Windows CE 7: + - C compiler toolchain installed, targetting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old. + +Before building Capstone for Windows CE 7 (respectively, Windows CE 8), the build script `windowsce/make_windowsce7-armv7.bat` (respectively, `windowsce/make_windowsce8-armv7.bat`) needs to be modified. The variables specified in the rest of this section are set in this script file. + +# Toolchain specification + +The following information need to be specified in the build script in order to perform the build: +- `set WINCE_TOOLCHAIN_ROOT=` is the path of the root directory of the Windows CE toolchain. To build for Windows CE 7, this should be set to the Windows Embedded Compact 7 toolchain. To build for Windows CE 8, this should be set to the device toolchain. +Examples: + - For Windows CE 7: + ```bat + set WINCE_TOOLCHAIN_ROOT=C:\WINCE700\sdk + ``` + - For Windows CE 8: + ```bat + set WINCE_TOOLCHAIN_ROOT=C:\Windows_CE_Tools\SDKs\SDK_HW90270\Sdk + ``` + +- `set TOOLCHAIN=` is a semicolon-separated list of the paths of the directories containing the binaries of the Windows CE toolchain. +For example: +```bat +set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386 +``` + +- `set INCLUDE=` is a semicolon-separated list of the paths of the directories containing the C header files of the Windows CE device SDK. To build for Windows CE 7, this should also include the directories containing the C header files of the Windows Embedded Compact 7 toolchain. +Examples: + - For Windows CE 7: + ```bat + set INCLUDE=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Include\Armv4i;C:\WINCE700\public\common\sdk\inc + ``` + - For Windows CE 8: + ```bat + set INCLUDE=%WINCE_TOOLCHAIN_ROOT%\Inc;%WINCE_TOOLCHAIN_ROOT%\crt\Include + ``` + +- `set LIBPATH=` is a semicolon-separated list of the paths of the directories containing the library (i.e., `.LIB`) files of the Windows CE 7 device SDK. +Examples: + - For Windows CE 7: + ```bat + set LIBPATH=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Lib\ARMv4I + ``` + - For Windows CE 8: + ```bat + set LIBPATH=%WINCE_TOOLCHAIN_ROOT%\Lib\ARMV7\retail;%WINCE_TOOLCHAIN_ROOT%\Crt\Lib\ARM + ``` + +- `set LIBS=` is a space-separated list of linker directives controlling library search. +Examples: + - For Windows CE 7: + ```bat + set LIBS=-nodefaultlib:oldnames.lib -nodefaultlib:libcmtd.lib -nodefaultlib:libcmt.lib coredll.lib corelibc.lib + ``` + - For Windows CE 8: + ```bat + set LIBS=coredll.lib + ``` + +# Capstone binary format + +By default, the build script produces a **dynamic link library** (i.e., `.DLL`). In order to produce a **static library** (i.e., `.LIB`) instead, the `SHARED` variable needs to be set to `0`, i.e.: +```bat +set SHARED=0 +``` + +# Architectures supported at runtime + +Capstone supports the following architectures: ARM, ARM64 (AArch64), M68K, MIPS, PowerPC, Sparc, SystemZ, x86 and XCore. However, Capstone can be configured in order to select which architectures need to be supported **at runtime**. This is controlled via the variable `DISASM_ARCH_LIST`, which is a space-separated list that is a combination of the following names: +- `ARM` +- `ARM64` +- `M68K` +- `MIPS` +- `POWERPC` +- `SPARC` +- `SYSZ` +- `X86` +- `XCORE`. + +By default, `DISASM_ARCH_LIST` includes support for **all** architectures supported by Capstone. +For example: +```bat +set DISASM_ARCH_LIST=ARM ARM64 X86 +``` +will produce a Capstone binary that supports the following architectures: ARM, ARM64 and x86. + +## Features customization + +Capstone has a list of features that can be controlled when needed. Each feature is controlled through setting a variable from the following list: + +- In order to produce a smaller binary that provides a **subset** of the features of Capstone, but still supports all the selected architectures, please specify the following: + ```bat + set DIET_MODE=1 + ``` + By default, this variable is set to `0`. + +- By default, Capstone uses the default system-provided **dynamic memory management** functions (e.g., `malloc()`, `realloc()`, `free()`) for its internal memory management. However, Capstone can instead be configured to call **custom** memory management functions provided by client applications. In order to enable this behavior, set the following: + ```bat + set USE_SYS_DYN_MEM=0 + ``` + +- In order to produce a **smaller** Capstone binary, support for the `x86` architecture can be more **limited**. In order to do so, set the following: + ```bat + set X86_REDUCE=1 + ``` + By default, this is set to `0`. + +- If the **AT&T** disassembly style of the `x86` architecture is never needed at runtime, then disabling support for it can produce a **smaller** Capstone binary. To do this, please set the following: + ```bat + set X86_ATT_DISABLE=1 + ``` + By default, this is set to `0`. + +Please refer to `docs/README` for more details on these features. diff --git a/white_patch_detect/capstone-master/windowsce/make_windowsce7-armv7.bat b/white_patch_detect/capstone-master/windowsce/make_windowsce7-armv7.bat new file mode 100644 index 0000000..6927659 --- /dev/null +++ b/white_patch_detect/capstone-master/windowsce/make_windowsce7-armv7.bat @@ -0,0 +1,179 @@ +@echo off + +rem *************************************************************************** +rem * VARIABLES TO SET FOR BUILDING * +rem *************************************************************************** + +set WINCE_TOOLCHAIN_ROOT=C:\WINCE700\sdk +set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386 +set INCLUDE=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Include\Armv4i;C:\WINCE700\public\common\sdk\inc +set LIBPATH=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Lib\ARMv4I +set LIBS=-nodefaultlib:oldnames.lib -nodefaultlib:libcmtd.lib -nodefaultlib:libcmt.lib coredll.lib corelibc.lib + +rem *************************************************************************** +rem * CAPSTONE CONFIGURATION * +rem *************************************************************************** + +set SHARED=1 +set DIET_MODE=0 +set USE_SYS_DYN_MEM=1 +set X86_REDUCE=0 +set X86_ATT_DISABLE=0 +set DISASM_ARCH_LIST=ARM ARM64 M68K MIPS POWERPC SPARC SYSZ X86 XCORE + +rem *************************************************************************** +rem * SANITY CHECKS * +rem *************************************************************************** + +setlocal ENABLEDELAYEDEXPANSION + +if "%WINCE_TOOLCHAIN_ROOT%"=="" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT +if not exist "%WINCE_TOOLCHAIN_ROOT%" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT + +if "%TOOLCHAIN%"=="" goto check_dir_exist_TOOLCHAIN + +set CC= +set LD= +set AR= +for /f "tokens=1-8 delims=;" %%a in ("%TOOLCHAIN%") do ( + for %%i in (%%a %%b %%c %%d %%e %%f %%g %%h) do ( + if not "%%i"=="" ( + if not exist "%%i" goto check_dir_exist_TOOLCHAIN + if "%CC%"=="" if exist "%%i\cl.exe" set CC=%%i\cl.exe + if "%LD%"=="" if exist "%%i\link.exe" set LD=%%i\link.exe + if "%AR%"=="" if exist "%%i\lib.exe" set AR=%%i\lib.exe + ) + ) +) + +if "%CC%"=="" goto check_dir_exist_CC_LD_AR +if "%LD%"=="" goto check_dir_exist_CC_LD_AR +if "%AR%"=="" goto check_dir_exist_CC_LD_AR + +if "%INCLUDE%"=="" goto check_dir_exist_INCLUDE + +set WINDOWS_H= + +set INCLUDE_SC=%INCLUDE% +set INCLUDE= +for /f "tokens=1-8 delims=;" %%a in ("%INCLUDE_SC%") do ( + for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do ( + if not %%i=="" ( + set INCLUDE=!INCLUDE! -I %%i + ) + ) +) + +if "%LIBPATH%"=="" goto check_dir_exist_LIBPATH + +set LIBPATH_SC=%LIBPATH% +set LIBPATH= +for /f "tokens=1-8 delims=;" %%a in ("%LIBPATH_SC%") do ( + for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do ( + if not %%i=="" ( + set LIBPATH=!LIBPATH! -libpath:%%i + ) + ) +) + +rem *************************************************************************** +rem * COMPILATION OPTIONS * +rem *************************************************************************** + +set OS=windowsce +set OS_VERSION=7.0 +set OS_VERSION_NUMBER=0x700 +set LIBARCH=arm +set MACH=THUMB + +for /f "delims=" %%i in ('cd') do set THIS_DIR=%%i + +set SOURCES_ROOT=%THIS_DIR%\.. +set TARGET_DIR=%THIS_DIR%\bin\%OS%_%OS_VERSION%_%LIBARCH% + +for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MAJOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MAJOR=%%i +for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MINOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MINOR=%%i + +set TARGET_VERSION=%CS_API_MAJOR%.%CS_API_MINOR% +set TAREGET_NAME=capstone-%TARGET_VERSION% + +set CPPFLAGS=-D LIBARCH_%LIBARCH% -D LIBARCH=L\"%LIBARCH%\" +set CPPFLAGS=%CPPFLAGS% -D _CRT_SECURE_NO_DEPRECATE -D _WINDOWS -D WINVER=%OS_VERSION_NUMBER% -D UNDER_CE=%OS_VERSION_NUMBER% -D _WIN32_WCE=%OS_VERSION_NUMBER% -D WINCE -D _UNICODE -D UNICODE -D STANDARDSHELL_UI_MODEL -D _USE_MATH_DEFINES -D ARM -D _ARM -D _ARM_ -D __ARM_ARCH_7__ -D __ARM_ARCH_7A__ -D __VFP_FP__=1 + +for %%a in (%DISASM_ARCH_LIST%) do set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_HAS_%%a + +if %SHARED%==0 ( + set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_STATIC -D LIB_EXT=L\".lib\" +) else ( + set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_SHARED -D LIB_EXT=L\".dll\" +) + +if not %USE_SYS_DYN_MEM%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_USE_SYS_DYN_MEM ) +if not %DIET_MODE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_DIET ) +if not %X86_REDUCE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_REDUCE ) +if not %X86_ATT_DISABLE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_ATT_DISABLE ) + +set INCLUDE=-I %SOURCES_ROOT%\include -I %SOURCES_ROOT% %INCLUDE% + +set CFLAGS=%CPPFLAGS% %INCLUDE% -nologo -Zi -MT -Oi -GS -GF -QRarch7 -arch:VFPv3-D32 -QRfpe- -fp:fast -Oy- -W3 -WX + +set LDFLAGS=-nologo -debug -incremental:no -manifest:no -version:%TARGET_VERSION% -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS% + +set ARFLAGS=-nologo -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS% + +set SOURCES= +for %%f in (%SOURCES_ROOT%\*.c) do set SOURCES=!SOURCES! %%f +for /d %%a in (%SOURCES_ROOT%\arch\*) do for %%f in (%%a\*.c) do set SOURCES=!SOURCES! %%f + +rem *************************************************************************** +rem * COMPILATION COMMANDS * +rem *************************************************************************** + +rd /q /s "%TARGET_DIR%" +md "%TARGET_DIR%" + +set PATH=%TOOLCHAIN%;%PATH% + +rem %CC% -c %CFLAGS% -D DEBUG -D _DEBUG -Od -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES% +%CC% -c %CFLAGS% -D NDEBUG -Ox -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES% +if errorlevel 1 goto compilation_failed + +if %SHARED%==0 ( + %AR% -out:%TARGET_DIR%\%TAREGET_NAME%.lib %ARFLAGS% %TARGET_DIR%\*.obj +) else ( + %LD% -dll -out:%TARGET_DIR%\%TAREGET_NAME%.dll -map:"%TARGET_DIR%\%TAREGET_NAME%.map" -pdb:"%TARGET_DIR%\%TAREGET_NAME%.pdb" %LDFLAGS% -opt:REF -opt:ICF %TARGET_DIR%\*.obj +) + +endlocal +goto done + +rem *************************************************************************** +rem * ERROR REPORTING * +rem *************************************************************************** + +:check_dir_exist_WINCE_TOOLCHAIN_ROOT +echo ERROR: WINCE_TOOLCHAIN_ROOT does not specify an existing directory. +goto done + +:check_dir_exist_TOOLCHAIN +echo ERROR: TOOLCHAIN does not specify an existing directory. +goto done + +:check_dir_exist_CC_LD_AR +echo ERROR: TOOLCHAIN does not specify a valid toolchain directory. +goto done + +:check_dir_exist_INCLUDE +echo ERROR: INCLUDE does not specify an existing directory. +goto done + +:check_dir_exist_LIBPATH +echo ERROR: LIBPATH does not specify an existing directory. +goto done + +:compilation_failed +echo ERROR: Compilation failed. +goto done + +:done +pause diff --git a/white_patch_detect/capstone-master/windowsce/make_windowsce8-armv7.bat b/white_patch_detect/capstone-master/windowsce/make_windowsce8-armv7.bat new file mode 100644 index 0000000..6a7157d --- /dev/null +++ b/white_patch_detect/capstone-master/windowsce/make_windowsce8-armv7.bat @@ -0,0 +1,179 @@ +@echo off + +rem *************************************************************************** +rem * VARIABLES TO SET FOR BUILDING * +rem *************************************************************************** + +set WINCE_TOOLCHAIN_ROOT=C:\Windows_CE_Tools\SDKs\SDK_HW90270\Sdk +set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386 +set INCLUDE=%WINCE_TOOLCHAIN_ROOT%\Inc;%WINCE_TOOLCHAIN_ROOT%\crt\Include +set LIBPATH=%WINCE_TOOLCHAIN_ROOT%\Lib\ARMV7\retail;%WINCE_TOOLCHAIN_ROOT%\Crt\Lib\ARM +set LIBS=coredll.lib + +rem *************************************************************************** +rem * CAPSTONE CONFIGURATION * +rem *************************************************************************** + +set SHARED=1 +set DIET_MODE=0 +set USE_SYS_DYN_MEM=1 +set X86_REDUCE=0 +set X86_ATT_DISABLE=0 +set DISASM_ARCH_LIST=ARM ARM64 M68K MIPS POWERPC SPARC SYSZ X86 XCORE + +rem *************************************************************************** +rem * SANITY CHECKS * +rem *************************************************************************** + +setlocal ENABLEDELAYEDEXPANSION + +if "%WINCE_TOOLCHAIN_ROOT%"=="" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT +if not exist "%WINCE_TOOLCHAIN_ROOT%" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT + +if "%TOOLCHAIN%"=="" goto check_dir_exist_TOOLCHAIN + +set CC= +set LD= +set AR= +for /f "tokens=1-8 delims=;" %%a in ("%TOOLCHAIN%") do ( + for %%i in (%%a %%b %%c %%d %%e %%f %%g %%h) do ( + if not "%%i"=="" ( + if not exist "%%i" goto check_dir_exist_TOOLCHAIN + if "%CC%"=="" if exist "%%i\cl.exe" set CC=%%i\cl.exe + if "%LD%"=="" if exist "%%i\link.exe" set LD=%%i\link.exe + if "%AR%"=="" if exist "%%i\lib.exe" set AR=%%i\lib.exe + ) + ) +) + +if "%CC%"=="" goto check_dir_exist_CC_LD_AR +if "%LD%"=="" goto check_dir_exist_CC_LD_AR +if "%AR%"=="" goto check_dir_exist_CC_LD_AR + +if "%INCLUDE%"=="" goto check_dir_exist_INCLUDE + +set WINDOWS_H= + +set INCLUDE_SC=%INCLUDE% +set INCLUDE= +for /f "tokens=1-8 delims=;" %%a in ("%INCLUDE_SC%") do ( + for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do ( + if not %%i=="" ( + set INCLUDE=!INCLUDE! -I %%i + ) + ) +) + +if "%LIBPATH%"=="" goto check_dir_exist_LIBPATH + +set LIBPATH_SC=%LIBPATH% +set LIBPATH= +for /f "tokens=1-8 delims=;" %%a in ("%LIBPATH_SC%") do ( + for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do ( + if not %%i=="" ( + set LIBPATH=!LIBPATH! -libpath:%%i + ) + ) +) + +rem *************************************************************************** +rem * COMPILATION OPTIONS * +rem *************************************************************************** + +set OS=windowsce +set OS_VERSION=8.0 +set OS_VERSION_NUMBER=0x800 +set LIBARCH=arm +set MACH=ARM + +for /f "delims=" %%i in ('cd') do set THIS_DIR=%%i + +set SOURCES_ROOT=%THIS_DIR%\.. +set TARGET_DIR=%THIS_DIR%\bin\%OS%_%OS_VERSION%_%LIBARCH% + +for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MAJOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MAJOR=%%i +for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MINOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MINOR=%%i + +set TARGET_VERSION=%CS_API_MAJOR%.%CS_API_MINOR% +set TAREGET_NAME=capstone-%TARGET_VERSION% + +set CPPFLAGS=-D LIBARCH_%LIBARCH% -D LIBARCH=L\"%LIBARCH%\" +set CPPFLAGS=%CPPFLAGS% -D _CRT_SECURE_NO_DEPRECATE -D _WINDOWS -D WINVER=%OS_VERSION_NUMBER% -D UNDER_CE=%OS_VERSION_NUMBER% -D _WIN32_WCE=%OS_VERSION_NUMBER% -D WINCE -D _UNICODE -D UNICODE -D STANDARDSHELL_UI_MODEL -D _USE_MATH_DEFINES -D ARM -D _ARM -D _ARM_ -D __ARM_ARCH_7__ -D __ARM_ARCH_7A__ -D __VFP_FP__=1 + +for %%a in (%DISASM_ARCH_LIST%) do set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_HAS_%%a + +if %SHARED%==0 ( + set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_STATIC -D LIB_EXT=L\".lib\" +) else ( + set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_SHARED -D LIB_EXT=L\".dll\" +) + +if not %USE_SYS_DYN_MEM%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_USE_SYS_DYN_MEM ) +if not %DIET_MODE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_DIET ) +if not %X86_REDUCE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_REDUCE ) +if not %X86_ATT_DISABLE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_ATT_DISABLE ) + +set INCLUDE=-I %SOURCES_ROOT%\include -I %SOURCES_ROOT% %INCLUDE% + +set CFLAGS=%CPPFLAGS% %INCLUDE% -nologo -MP -Zi -MT -Oi -GS -fp:fast -Oy- -W3 -WX + +set LDFLAGS=-nologo -debug -incremental:no -manifest:no -version:%TARGET_VERSION% -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS% + +set ARFLAGS=-nologo -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS% + +set SOURCES= +for %%f in (%SOURCES_ROOT%\*.c) do set SOURCES=!SOURCES! %%f +for /d %%a in (%SOURCES_ROOT%\arch\*) do for %%f in (%%a\*.c) do set SOURCES=!SOURCES! %%f + +rem *************************************************************************** +rem * COMPILATION COMMANDS * +rem *************************************************************************** + +rd /q /s "%TARGET_DIR%" +md "%TARGET_DIR%" + +set PATH=%TOOLCHAIN%;%PATH% + +rem %CC% -c %CFLAGS% -D DEBUG -D _DEBUG -Od -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES% +%CC% -c %CFLAGS% -D NDEBUG -Ox -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES% +if errorlevel 1 goto compilation_failed + +if %SHARED%==0 ( + %AR% -out:%TARGET_DIR%\%TAREGET_NAME%.lib %ARFLAGS% %TARGET_DIR%\*.obj +) else ( + %LD% -dll -out:%TARGET_DIR%\%TAREGET_NAME%.dll -map:"%TARGET_DIR%\%TAREGET_NAME%.map" -pdb:"%TARGET_DIR%\%TAREGET_NAME%.pdb" %LDFLAGS% -opt:REF -opt:ICF %TARGET_DIR%\*.obj +) + +endlocal +goto done + +rem *************************************************************************** +rem * ERROR REPORTING * +rem *************************************************************************** + +:check_dir_exist_WINCE_TOOLCHAIN_ROOT +echo ERROR: WINCE_TOOLCHAIN_ROOT does not specify an existing directory. +goto done + +:check_dir_exist_TOOLCHAIN +echo ERROR: TOOLCHAIN does not specify an existing directory. +goto done + +:check_dir_exist_CC_LD_AR +echo ERROR: TOOLCHAIN does not specify a valid toolchain directory. +goto done + +:check_dir_exist_INCLUDE +echo ERROR: INCLUDE does not specify an existing directory. +goto done + +:check_dir_exist_LIBPATH +echo ERROR: LIBPATH does not specify an existing directory. +goto done + +:compilation_failed +echo ERROR: Compilation failed. +goto done + +:done +pause diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.pbxproj b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.pbxproj new file mode 100644 index 0000000..9d0f370 --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.pbxproj @@ -0,0 +1,3460 @@ +// !$*UTF8*$! +{ + archiveVersion = 1; + classes = { + }; + objectVersion = 46; + objects = { + +/* Begin PBXBuildFile section */ + 05354FA41FC62FCC00920005 /* m68k.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3579F1BC2C14E0094BB3F /* m68k.h */; settings = {ATTRIBUTES = (Public, ); }; }; + 0537EAAA1FC6284F00F06BF9 /* tms320c64x.h in Headers */ = {isa = PBXBuildFile; fileRef = 0537EAA91FC6284E00F06BF9 /* tms320c64x.h */; settings = {ATTRIBUTES = (Public, ); }; }; + 0537EAAC1FC6286300F06BF9 /* m680x.h in Headers */ = {isa = PBXBuildFile; fileRef = 0537EAAB1FC6286300F06BF9 /* m680x.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC07A86E19F6061D00254FCF /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC3A28E31AF29C0100FC9913 /* test_customized_mnem.c in Sources */ = {isa = PBXBuildFile; fileRef = DC3A28E21AF29C0100FC9913 /* test_customized_mnem.c */; }; + DC3A28E41AF29C4600FC9913 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474EE519DDEAD900BCA449 /* test_arm.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E6C19DDEA9500BCA449 /* test_arm.c */; }; + DC474EF119DDEAED00BCA449 /* test_arm64.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E6D19DDEA9500BCA449 /* test_arm64.c */; }; + DC474EF219DDEAF000BCA449 /* test_detail.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E6E19DDEA9500BCA449 /* test_detail.c */; }; + DC474EF319DDEAF200BCA449 /* test_mips.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E6F19DDEA9500BCA449 /* test_mips.c */; }; + DC474EF419DDEAF400BCA449 /* test_ppc.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7019DDEA9500BCA449 /* test_ppc.c */; }; + DC474EF519DDEAF600BCA449 /* test_skipdata.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7119DDEA9500BCA449 /* test_skipdata.c */; }; + DC474EF619DDEAF800BCA449 /* test_sparc.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7219DDEA9500BCA449 /* test_sparc.c */; }; + DC474EF719DDEAFA00BCA449 /* test_systemz.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7319DDEA9500BCA449 /* test_systemz.c */; }; + DC474EF819DDEAFD00BCA449 /* test_x86.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7419DDEA9500BCA449 /* test_x86.c */; }; + DC474EF919DDEB0000BCA449 /* test_xcore.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7519DDEA9500BCA449 /* test_xcore.c */; }; + DC474EFA19DDEB0200BCA449 /* test_basic.c in Sources */ = {isa = PBXBuildFile; fileRef = DC474E7619DDEA9500BCA449 /* test_basic.c */; }; + DC474EFB19DDEB1100BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474EFD19DDEB1A00BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474EFE19DDEB1C00BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474EFF19DDEB1E00BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0019DDEB2100BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0119DDEB2300BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0219DDEB2500BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0319DDEB2700BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0419DDEB2A00BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F0519DDEB2D00BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F8119DE6F6B00BCA449 /* arm.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24BC19DDCE2F00EF8EA9 /* arm.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8219DE6F6B00BCA449 /* arm64.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24BD19DDCE2F00EF8EA9 /* arm64.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8319DE6F6B00BCA449 /* capstone.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24BE19DDCE2F00EF8EA9 /* capstone.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8419DE6F6B00BCA449 /* mips.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24BF19DDCE2F00EF8EA9 /* mips.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8519DE6F6B00BCA449 /* platform.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C019DDCE2F00EF8EA9 /* platform.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8619DE6F6B00BCA449 /* ppc.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C119DDCE2F00EF8EA9 /* ppc.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8719DE6F6B00BCA449 /* sparc.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C219DDCE2F00EF8EA9 /* sparc.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8819DE6F6B00BCA449 /* systemz.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C319DDCE2F00EF8EA9 /* systemz.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8919DE6F6B00BCA449 /* x86.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C419DDCE2F00EF8EA9 /* x86.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8A19DE6F6B00BCA449 /* xcore.h in Headers */ = {isa = PBXBuildFile; fileRef = DCFE24C519DDCE2F00EF8EA9 /* xcore.h */; settings = {ATTRIBUTES = (Public, ); }; }; + DC474F8C19DE6F8000BCA449 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC474F8D19DE6FCD00BCA449 /* cs.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249D19DDCDEE00EF8EA9 /* cs.c */; }; + DC474F8E19DE6FCD00BCA449 /* MCInst.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249E19DDCDEE00EF8EA9 /* MCInst.c */; }; + DC474F8F19DE6FCD00BCA449 /* MCInstrDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249F19DDCDEE00EF8EA9 /* MCInstrDesc.c */; }; + DC474F9019DE6FCD00BCA449 /* MCRegisterInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */; }; + DC474F9119DE6FCD00BCA449 /* SStream.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A119DDCDEE00EF8EA9 /* SStream.c */; }; + DC474F9219DE6FCD00BCA449 /* utils.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A219DDCDEE00EF8EA9 /* utils.c */; }; + DC474F9319DE6FCD00BCA449 /* cs.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249D19DDCDEE00EF8EA9 /* cs.c */; }; + DC474F9419DE6FCD00BCA449 /* MCInst.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249E19DDCDEE00EF8EA9 /* MCInst.c */; }; + DC474F9519DE6FCD00BCA449 /* MCInstrDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249F19DDCDEE00EF8EA9 /* MCInstrDesc.c */; }; + DC474F9619DE6FCD00BCA449 /* MCRegisterInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */; }; + DC474F9719DE6FCD00BCA449 /* SStream.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A119DDCDEE00EF8EA9 /* SStream.c */; }; + DC474F9819DE6FCD00BCA449 /* utils.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A219DDCDEE00EF8EA9 /* utils.c */; }; + DC474F9919DE6FDA00BCA449 /* AArch64BaseInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23DE19DDCD8700EF8EA9 /* AArch64BaseInfo.c */; }; + DC474F9A19DE6FDA00BCA449 /* AArch64Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E019DDCD8700EF8EA9 /* AArch64Disassembler.c */; }; + DC474F9B19DE6FDA00BCA449 /* AArch64InstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E719DDCD8700EF8EA9 /* AArch64InstPrinter.c */; }; + DC474F9C19DE6FDA00BCA449 /* AArch64Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E919DDCD8700EF8EA9 /* AArch64Mapping.c */; }; + DC474F9D19DE6FDA00BCA449 /* AArch64Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EB19DDCD8700EF8EA9 /* AArch64Module.c */; }; + DC474F9E19DE6FDA00BCA449 /* ARMDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EF19DDCD8700EF8EA9 /* ARMDisassembler.c */; }; + DC474F9F19DE6FDA00BCA449 /* ARMInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F619DDCD8700EF8EA9 /* ARMInstPrinter.c */; }; + DC474FA019DE6FDA00BCA449 /* ARMMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F819DDCD8700EF8EA9 /* ARMMapping.c */; }; + DC474FA119DE6FDA00BCA449 /* ARMModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FA19DDCD8700EF8EA9 /* ARMModule.c */; }; + DC474FA219DE6FDA00BCA449 /* MipsDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FC19DDCD8700EF8EA9 /* MipsDisassembler.c */; }; + DC474FA319DE6FDA00BCA449 /* MipsInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240319DDCD8700EF8EA9 /* MipsInstPrinter.c */; }; + DC474FA419DE6FDA00BCA449 /* MipsMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240519DDCD8700EF8EA9 /* MipsMapping.c */; }; + DC474FA519DE6FDA00BCA449 /* MipsModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240719DDCD8700EF8EA9 /* MipsModule.c */; }; + DC474FA619DE6FDA00BCA449 /* PPCDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240919DDCD8700EF8EA9 /* PPCDisassembler.c */; }; + DC474FA719DE6FDA00BCA449 /* PPCInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241019DDCD8700EF8EA9 /* PPCInstPrinter.c */; }; + DC474FA819DE6FDA00BCA449 /* PPCMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241219DDCD8700EF8EA9 /* PPCMapping.c */; }; + DC474FA919DE6FDA00BCA449 /* PPCModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241419DDCD8700EF8EA9 /* PPCModule.c */; }; + DC474FAA19DE6FDA00BCA449 /* SparcDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241819DDCD8700EF8EA9 /* SparcDisassembler.c */; }; + DC474FAB19DE6FDA00BCA449 /* SparcInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241F19DDCD8800EF8EA9 /* SparcInstPrinter.c */; }; + DC474FAC19DE6FDA00BCA449 /* SparcMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242119DDCD8800EF8EA9 /* SparcMapping.c */; }; + DC474FAD19DE6FDA00BCA449 /* SparcModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242319DDCD8800EF8EA9 /* SparcModule.c */; }; + DC474FAE19DE6FDA00BCA449 /* SystemZDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242519DDCD8800EF8EA9 /* SystemZDisassembler.c */; }; + DC474FAF19DE6FDA00BCA449 /* SystemZInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242C19DDCD8800EF8EA9 /* SystemZInstPrinter.c */; }; + DC474FB019DE6FDA00BCA449 /* SystemZMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242E19DDCD8800EF8EA9 /* SystemZMapping.c */; }; + DC474FB119DE6FDA00BCA449 /* SystemZMCTargetDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243019DDCD8800EF8EA9 /* SystemZMCTargetDesc.c */; }; + DC474FB219DE6FDA00BCA449 /* SystemZModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243219DDCD8800EF8EA9 /* SystemZModule.c */; }; + DC474FB319DE6FDA00BCA449 /* X86ATTInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243419DDCD8800EF8EA9 /* X86ATTInstPrinter.c */; }; + DC474FB419DE6FDA00BCA449 /* X86Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243619DDCD8800EF8EA9 /* X86Disassembler.c */; }; + DC474FB519DE6FDA00BCA449 /* X86DisassemblerDecoder.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243819DDCD8800EF8EA9 /* X86DisassemblerDecoder.c */; }; + DC474FB619DE6FDA00BCA449 /* X86IntelInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244519DDCD8800EF8EA9 /* X86IntelInstPrinter.c */; }; + DC474FB719DE6FDA00BCA449 /* X86Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244619DDCD8800EF8EA9 /* X86Mapping.c */; }; + DC474FB819DE6FDA00BCA449 /* X86Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244819DDCD8800EF8EA9 /* X86Module.c */; }; + DC474FB919DE6FDA00BCA449 /* XCoreDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244A19DDCD8800EF8EA9 /* XCoreDisassembler.c */; }; + DC474FBA19DE6FDA00BCA449 /* XCoreInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245019DDCD8800EF8EA9 /* XCoreInstPrinter.c */; }; + DC474FBB19DE6FDA00BCA449 /* XCoreMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245219DDCD8800EF8EA9 /* XCoreMapping.c */; }; + DC474FBC19DE6FDA00BCA449 /* XCoreModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245419DDCD8800EF8EA9 /* XCoreModule.c */; }; + DC474FBD19DE6FDA00BCA449 /* AArch64BaseInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23DE19DDCD8700EF8EA9 /* AArch64BaseInfo.c */; }; + DC474FBE19DE6FDA00BCA449 /* AArch64Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E019DDCD8700EF8EA9 /* AArch64Disassembler.c */; }; + DC474FBF19DE6FDA00BCA449 /* AArch64InstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E719DDCD8700EF8EA9 /* AArch64InstPrinter.c */; }; + DC474FC019DE6FDA00BCA449 /* AArch64Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E919DDCD8700EF8EA9 /* AArch64Mapping.c */; }; + DC474FC119DE6FDA00BCA449 /* AArch64Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EB19DDCD8700EF8EA9 /* AArch64Module.c */; }; + DC474FC219DE6FDA00BCA449 /* ARMDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EF19DDCD8700EF8EA9 /* ARMDisassembler.c */; }; + DC474FC319DE6FDA00BCA449 /* ARMInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F619DDCD8700EF8EA9 /* ARMInstPrinter.c */; }; + DC474FC419DE6FDA00BCA449 /* ARMMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F819DDCD8700EF8EA9 /* ARMMapping.c */; }; + DC474FC519DE6FDA00BCA449 /* ARMModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FA19DDCD8700EF8EA9 /* ARMModule.c */; }; + DC474FC619DE6FDA00BCA449 /* MipsDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FC19DDCD8700EF8EA9 /* MipsDisassembler.c */; }; + DC474FC719DE6FDA00BCA449 /* MipsInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240319DDCD8700EF8EA9 /* MipsInstPrinter.c */; }; + DC474FC819DE6FDA00BCA449 /* MipsMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240519DDCD8700EF8EA9 /* MipsMapping.c */; }; + DC474FC919DE6FDA00BCA449 /* MipsModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240719DDCD8700EF8EA9 /* MipsModule.c */; }; + DC474FCA19DE6FDA00BCA449 /* PPCDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240919DDCD8700EF8EA9 /* PPCDisassembler.c */; }; + DC474FCB19DE6FDA00BCA449 /* PPCInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241019DDCD8700EF8EA9 /* PPCInstPrinter.c */; }; + DC474FCC19DE6FDA00BCA449 /* PPCMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241219DDCD8700EF8EA9 /* PPCMapping.c */; }; + DC474FCD19DE6FDA00BCA449 /* PPCModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241419DDCD8700EF8EA9 /* PPCModule.c */; }; + DC474FCE19DE6FDA00BCA449 /* SparcDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241819DDCD8700EF8EA9 /* SparcDisassembler.c */; }; + DC474FCF19DE6FDA00BCA449 /* SparcInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241F19DDCD8800EF8EA9 /* SparcInstPrinter.c */; }; + DC474FD019DE6FDA00BCA449 /* SparcMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242119DDCD8800EF8EA9 /* SparcMapping.c */; }; + DC474FD119DE6FDA00BCA449 /* SparcModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242319DDCD8800EF8EA9 /* SparcModule.c */; }; + DC474FD219DE6FDA00BCA449 /* SystemZDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242519DDCD8800EF8EA9 /* SystemZDisassembler.c */; }; + DC474FD319DE6FDA00BCA449 /* SystemZInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242C19DDCD8800EF8EA9 /* SystemZInstPrinter.c */; }; + DC474FD419DE6FDA00BCA449 /* SystemZMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242E19DDCD8800EF8EA9 /* SystemZMapping.c */; }; + DC474FD519DE6FDA00BCA449 /* SystemZMCTargetDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243019DDCD8800EF8EA9 /* SystemZMCTargetDesc.c */; }; + DC474FD619DE6FDA00BCA449 /* SystemZModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243219DDCD8800EF8EA9 /* SystemZModule.c */; }; + DC474FD719DE6FDA00BCA449 /* X86ATTInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243419DDCD8800EF8EA9 /* X86ATTInstPrinter.c */; }; + DC474FD819DE6FDA00BCA449 /* X86Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243619DDCD8800EF8EA9 /* X86Disassembler.c */; }; + DC474FD919DE6FDA00BCA449 /* X86DisassemblerDecoder.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243819DDCD8800EF8EA9 /* X86DisassemblerDecoder.c */; }; + DC474FDA19DE6FDA00BCA449 /* X86IntelInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244519DDCD8800EF8EA9 /* X86IntelInstPrinter.c */; }; + DC474FDB19DE6FDA00BCA449 /* X86Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244619DDCD8800EF8EA9 /* X86Mapping.c */; }; + DC474FDC19DE6FDA00BCA449 /* X86Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244819DDCD8800EF8EA9 /* X86Module.c */; }; + DC474FDD19DE6FDA00BCA449 /* XCoreDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244A19DDCD8800EF8EA9 /* XCoreDisassembler.c */; }; + DC474FDE19DE6FDA00BCA449 /* XCoreInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245019DDCD8800EF8EA9 /* XCoreInstPrinter.c */; }; + DC474FDF19DE6FDA00BCA449 /* XCoreMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245219DDCD8800EF8EA9 /* XCoreMapping.c */; }; + DC474FE019DE6FDA00BCA449 /* XCoreModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245419DDCD8800EF8EA9 /* XCoreModule.c */; }; + DC5BFF4719EE547F008CA585 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DC5BFF4919EE54BE008CA585 /* test_iter.c in Sources */ = {isa = PBXBuildFile; fileRef = DC5BFF4819EE54BE008CA585 /* test_iter.c */; }; + DC9921181BC2C227005BE5E3 /* libcapstone.a in Frameworks */ = {isa = PBXBuildFile; fileRef = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; }; + DCA357831BC2C0290094BB3F /* M68KDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577B1BC2C0290094BB3F /* M68KDisassembler.c */; }; + DCA357841BC2C0290094BB3F /* M68KDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577B1BC2C0290094BB3F /* M68KDisassembler.c */; }; + DCA357851BC2C0290094BB3F /* M68KDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577B1BC2C0290094BB3F /* M68KDisassembler.c */; }; + DCA357861BC2C0290094BB3F /* M68KDisassembler.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577C1BC2C0290094BB3F /* M68KDisassembler.h */; }; + DCA357871BC2C0290094BB3F /* M68KDisassembler.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577C1BC2C0290094BB3F /* M68KDisassembler.h */; }; + DCA357881BC2C0290094BB3F /* M68KDisassembler.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577C1BC2C0290094BB3F /* M68KDisassembler.h */; }; + DCA357891BC2C0290094BB3F /* M68KInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577D1BC2C0290094BB3F /* M68KInstPrinter.c */; }; + DCA3578A1BC2C0290094BB3F /* M68KInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577D1BC2C0290094BB3F /* M68KInstPrinter.c */; }; + DCA3578B1BC2C0290094BB3F /* M68KInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577D1BC2C0290094BB3F /* M68KInstPrinter.c */; }; + DCA3578C1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577E1BC2C0290094BB3F /* M68KInstPrinter.h */; }; + DCA3578D1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577E1BC2C0290094BB3F /* M68KInstPrinter.h */; }; + DCA3578E1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */ = {isa = PBXBuildFile; fileRef = DCA3577E1BC2C0290094BB3F /* M68KInstPrinter.h */; }; + DCA3578F1BC2C0290094BB3F /* M68KModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577F1BC2C0290094BB3F /* M68KModule.c */; }; + DCA357901BC2C0290094BB3F /* M68KModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577F1BC2C0290094BB3F /* M68KModule.c */; }; + DCA357911BC2C0290094BB3F /* M68KModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3577F1BC2C0290094BB3F /* M68KModule.c */; }; + DCA3579E1BC2C0EB0094BB3F /* test_m68k.c in Sources */ = {isa = PBXBuildFile; fileRef = DCA3579D1BC2C0EB0094BB3F /* test_m68k.c */; }; + DCFE245519DDCD9200EF8EA9 /* AArch64BaseInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23DE19DDCD8700EF8EA9 /* AArch64BaseInfo.c */; }; + DCFE245619DDCD9200EF8EA9 /* AArch64Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E019DDCD8700EF8EA9 /* AArch64Disassembler.c */; }; + DCFE245719DDCD9200EF8EA9 /* AArch64InstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E719DDCD8700EF8EA9 /* AArch64InstPrinter.c */; }; + DCFE245819DDCD9200EF8EA9 /* AArch64Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23E919DDCD8700EF8EA9 /* AArch64Mapping.c */; }; + DCFE245919DDCD9200EF8EA9 /* AArch64Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EB19DDCD8700EF8EA9 /* AArch64Module.c */; }; + DCFE245F19DDCD9900EF8EA9 /* ARMDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23EF19DDCD8700EF8EA9 /* ARMDisassembler.c */; }; + DCFE246019DDCD9900EF8EA9 /* ARMInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F619DDCD8700EF8EA9 /* ARMInstPrinter.c */; }; + DCFE246119DDCD9900EF8EA9 /* ARMMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23F819DDCD8700EF8EA9 /* ARMMapping.c */; }; + DCFE246219DDCD9900EF8EA9 /* ARMModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FA19DDCD8700EF8EA9 /* ARMModule.c */; }; + DCFE246719DDCDA000EF8EA9 /* MipsDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE23FC19DDCD8700EF8EA9 /* MipsDisassembler.c */; }; + DCFE246819DDCDA000EF8EA9 /* MipsInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240319DDCD8700EF8EA9 /* MipsInstPrinter.c */; }; + DCFE246919DDCDA000EF8EA9 /* MipsMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240519DDCD8700EF8EA9 /* MipsMapping.c */; }; + DCFE246A19DDCDA000EF8EA9 /* MipsModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240719DDCD8700EF8EA9 /* MipsModule.c */; }; + DCFE246F19DDCDA700EF8EA9 /* PPCDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE240919DDCD8700EF8EA9 /* PPCDisassembler.c */; }; + DCFE247019DDCDA700EF8EA9 /* PPCInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241019DDCD8700EF8EA9 /* PPCInstPrinter.c */; }; + DCFE247119DDCDA700EF8EA9 /* PPCMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241219DDCD8700EF8EA9 /* PPCMapping.c */; }; + DCFE247219DDCDA700EF8EA9 /* PPCModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241419DDCD8700EF8EA9 /* PPCModule.c */; }; + DCFE247719DDCDAD00EF8EA9 /* SparcDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241819DDCD8700EF8EA9 /* SparcDisassembler.c */; }; + DCFE247819DDCDAD00EF8EA9 /* SparcInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE241F19DDCD8800EF8EA9 /* SparcInstPrinter.c */; }; + DCFE247919DDCDAD00EF8EA9 /* SparcMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242119DDCD8800EF8EA9 /* SparcMapping.c */; }; + DCFE247A19DDCDAD00EF8EA9 /* SparcModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242319DDCD8800EF8EA9 /* SparcModule.c */; }; + DCFE247F19DDCDB700EF8EA9 /* SystemZDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242519DDCD8800EF8EA9 /* SystemZDisassembler.c */; }; + DCFE248019DDCDB700EF8EA9 /* SystemZInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242C19DDCD8800EF8EA9 /* SystemZInstPrinter.c */; }; + DCFE248119DDCDB700EF8EA9 /* SystemZMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE242E19DDCD8800EF8EA9 /* SystemZMapping.c */; }; + DCFE248219DDCDB700EF8EA9 /* SystemZMCTargetDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243019DDCD8800EF8EA9 /* SystemZMCTargetDesc.c */; }; + DCFE248319DDCDB700EF8EA9 /* SystemZModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243219DDCD8800EF8EA9 /* SystemZModule.c */; }; + DCFE248919DDCDC000EF8EA9 /* X86ATTInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243419DDCD8800EF8EA9 /* X86ATTInstPrinter.c */; }; + DCFE248A19DDCDC000EF8EA9 /* X86Disassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243619DDCD8800EF8EA9 /* X86Disassembler.c */; }; + DCFE248B19DDCDC000EF8EA9 /* X86DisassemblerDecoder.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE243819DDCD8800EF8EA9 /* X86DisassemblerDecoder.c */; }; + DCFE248C19DDCDC000EF8EA9 /* X86IntelInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244519DDCD8800EF8EA9 /* X86IntelInstPrinter.c */; }; + DCFE248D19DDCDC000EF8EA9 /* X86Mapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244619DDCD8800EF8EA9 /* X86Mapping.c */; }; + DCFE248E19DDCDC000EF8EA9 /* X86Module.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244819DDCD8800EF8EA9 /* X86Module.c */; }; + DCFE249519DDCDD000EF8EA9 /* XCoreDisassembler.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE244A19DDCD8800EF8EA9 /* XCoreDisassembler.c */; }; + DCFE249619DDCDD000EF8EA9 /* XCoreInstPrinter.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245019DDCD8800EF8EA9 /* XCoreInstPrinter.c */; }; + DCFE249719DDCDD000EF8EA9 /* XCoreMapping.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245219DDCD8800EF8EA9 /* XCoreMapping.c */; }; + DCFE249819DDCDD000EF8EA9 /* XCoreModule.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE245419DDCD8800EF8EA9 /* XCoreModule.c */; }; + DCFE24A319DDCDEE00EF8EA9 /* cs.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249D19DDCDEE00EF8EA9 /* cs.c */; }; + DCFE24A519DDCDEE00EF8EA9 /* MCInst.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249E19DDCDEE00EF8EA9 /* MCInst.c */; }; + DCFE24A719DDCDEE00EF8EA9 /* MCInstrDesc.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE249F19DDCDEE00EF8EA9 /* MCInstrDesc.c */; }; + DCFE24A919DDCDEE00EF8EA9 /* MCRegisterInfo.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */; }; + DCFE24AB19DDCDEE00EF8EA9 /* SStream.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A119DDCDEE00EF8EA9 /* SStream.c */; }; + DCFE24AD19DDCDEE00EF8EA9 /* utils.c in Sources */ = {isa = PBXBuildFile; fileRef = DCFE24A219DDCDEE00EF8EA9 /* utils.c */; }; +/* End PBXBuildFile section */ + +/* Begin PBXCopyFilesBuildPhase section */ + DC3A28D91AF29BEB00FC9913 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474E6219DDEA5F00BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474E8419DDEAA200BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474E8F19DDEAA700BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474E9A19DDEAAC00BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EA519DDEAB000BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EB019DDEAB700BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EBB19DDEABC00BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EC619DDEAC100BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474ED119DDEAC600BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EDC19DDEACC00BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC474EE819DDEAE400BCA449 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DC5BFF3E19EE544E008CA585 /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; + DCA357941BC2C0930094BB3F /* CopyFiles */ = { + isa = PBXCopyFilesBuildPhase; + buildActionMask = 2147483647; + dstPath = /usr/share/man/man1/; + dstSubfolderSpec = 0; + files = ( + ); + runOnlyForDeploymentPostprocessing = 1; + }; +/* End PBXCopyFilesBuildPhase section */ + +/* Begin PBXFileReference section */ + 05354FA51FC6305300920005 /* module.modulemap */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = "sourcecode.module-map"; path = module.modulemap; sourceTree = ""; }; + 0537EAA91FC6284E00F06BF9 /* tms320c64x.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = tms320c64x.h; sourceTree = ""; }; + 0537EAAB1FC6286300F06BF9 /* m680x.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = m680x.h; sourceTree = ""; }; + DC3A28DB1AF29BEB00FC9913 /* test_customized_mnem */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_customized_mnem; sourceTree = BUILT_PRODUCTS_DIR; }; + DC3A28E21AF29C0100FC9913 /* test_customized_mnem.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_customized_mnem.c; path = ../tests/test_customized_mnem.c; sourceTree = ""; }; + DC474E6419DDEA5F00BCA449 /* test */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474E6C19DDEA9500BCA449 /* test_arm.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_arm.c; path = ../tests/test_arm.c; sourceTree = ""; }; + DC474E6D19DDEA9500BCA449 /* test_arm64.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_arm64.c; path = ../tests/test_arm64.c; sourceTree = ""; }; + DC474E6E19DDEA9500BCA449 /* test_detail.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_detail.c; path = ../tests/test_detail.c; sourceTree = ""; }; + DC474E6F19DDEA9500BCA449 /* test_mips.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_mips.c; path = ../tests/test_mips.c; sourceTree = ""; }; + DC474E7019DDEA9500BCA449 /* test_ppc.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_ppc.c; path = ../tests/test_ppc.c; sourceTree = ""; }; + DC474E7119DDEA9500BCA449 /* test_skipdata.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_skipdata.c; path = ../tests/test_skipdata.c; sourceTree = ""; }; + DC474E7219DDEA9500BCA449 /* test_sparc.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_sparc.c; path = ../tests/test_sparc.c; sourceTree = ""; }; + DC474E7319DDEA9500BCA449 /* test_systemz.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_systemz.c; path = ../tests/test_systemz.c; sourceTree = ""; }; + DC474E7419DDEA9500BCA449 /* test_x86.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_x86.c; path = ../tests/test_x86.c; sourceTree = ""; }; + DC474E7519DDEA9500BCA449 /* test_xcore.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_xcore.c; path = ../tests/test_xcore.c; sourceTree = ""; }; + DC474E7619DDEA9500BCA449 /* test_basic.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_basic.c; path = ../tests/test_basic.c; sourceTree = ""; }; + DC474E8619DDEAA200BCA449 /* test_arm */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_arm; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474E9119DDEAA700BCA449 /* test_detail */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_detail; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474E9C19DDEAAC00BCA449 /* test_mips */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_mips; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EA719DDEAB000BCA449 /* test_ppc */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_ppc; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EB219DDEAB700BCA449 /* test_skipdata */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_skipdata; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EBD19DDEABC00BCA449 /* test_sparc */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_sparc; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EC819DDEAC100BCA449 /* test_systemz */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_systemz; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474ED319DDEAC600BCA449 /* test_x86 */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_x86; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EDE19DDEACC00BCA449 /* test_xcore */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_xcore; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474EEA19DDEAE400BCA449 /* test_arm64 */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_arm64; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474F6819DE6F3B00BCA449 /* Capstone.framework */ = {isa = PBXFileReference; explicitFileType = wrapper.framework; includeInIndex = 0; path = Capstone.framework; sourceTree = BUILT_PRODUCTS_DIR; }; + DC474F6B19DE6F3B00BCA449 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; + DC5BFF4019EE544E008CA585 /* test_iter */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_iter; sourceTree = BUILT_PRODUCTS_DIR; }; + DC5BFF4819EE54BE008CA585 /* test_iter.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_iter.c; path = ../tests/test_iter.c; sourceTree = ""; }; + DCA3577B1BC2C0290094BB3F /* M68KDisassembler.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = M68KDisassembler.c; sourceTree = ""; }; + DCA3577C1BC2C0290094BB3F /* M68KDisassembler.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = M68KDisassembler.h; sourceTree = ""; }; + DCA3577D1BC2C0290094BB3F /* M68KInstPrinter.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = M68KInstPrinter.c; sourceTree = ""; }; + DCA3577E1BC2C0290094BB3F /* M68KInstPrinter.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = M68KInstPrinter.h; sourceTree = ""; }; + DCA3577F1BC2C0290094BB3F /* M68KModule.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = M68KModule.c; sourceTree = ""; }; + DCA357961BC2C0930094BB3F /* test_m68k */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_m68k; sourceTree = BUILT_PRODUCTS_DIR; }; + DCA3579D1BC2C0EB0094BB3F /* test_m68k.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_m68k.c; path = ../tests/test_m68k.c; sourceTree = ""; }; + DCA3579F1BC2C14E0094BB3F /* m68k.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = m68k.h; sourceTree = ""; }; + DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */ = {isa = PBXFileReference; explicitFileType = archive.ar; includeInIndex = 0; path = libcapstone.a; sourceTree = BUILT_PRODUCTS_DIR; }; + DCFE23CD19DDCC9500EF8EA9 /* libcapstone.dylib */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.dylib"; includeInIndex = 0; path = libcapstone.dylib; sourceTree = BUILT_PRODUCTS_DIR; }; + DCFE23DD19DDCD8700EF8EA9 /* AArch64AddressingModes.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64AddressingModes.h; sourceTree = ""; }; + DCFE23DE19DDCD8700EF8EA9 /* AArch64BaseInfo.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = AArch64BaseInfo.c; sourceTree = ""; }; + DCFE23DF19DDCD8700EF8EA9 /* AArch64BaseInfo.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64BaseInfo.h; sourceTree = ""; }; + DCFE23E019DDCD8700EF8EA9 /* AArch64Disassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = AArch64Disassembler.c; sourceTree = ""; }; + DCFE23E119DDCD8700EF8EA9 /* AArch64Disassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64Disassembler.h; sourceTree = ""; }; + DCFE23E219DDCD8700EF8EA9 /* AArch64GenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = AArch64GenAsmWriter.inc; sourceTree = ""; }; + DCFE23E319DDCD8700EF8EA9 /* AArch64GenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = AArch64GenDisassemblerTables.inc; sourceTree = ""; }; + DCFE23E419DDCD8700EF8EA9 /* AArch64GenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = AArch64GenInstrInfo.inc; sourceTree = ""; }; + DCFE23E519DDCD8700EF8EA9 /* AArch64GenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = AArch64GenRegisterInfo.inc; sourceTree = ""; }; + DCFE23E619DDCD8700EF8EA9 /* AArch64GenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = AArch64GenSubtargetInfo.inc; sourceTree = ""; }; + DCFE23E719DDCD8700EF8EA9 /* AArch64InstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = AArch64InstPrinter.c; sourceTree = ""; }; + DCFE23E819DDCD8700EF8EA9 /* AArch64InstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64InstPrinter.h; sourceTree = ""; }; + DCFE23E919DDCD8700EF8EA9 /* AArch64Mapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = AArch64Mapping.c; sourceTree = ""; }; + DCFE23EA19DDCD8700EF8EA9 /* AArch64Mapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64Mapping.h; sourceTree = ""; }; + DCFE23EB19DDCD8700EF8EA9 /* AArch64Module.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = AArch64Module.c; sourceTree = ""; }; + DCFE23ED19DDCD8700EF8EA9 /* ARMAddressingModes.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ARMAddressingModes.h; sourceTree = ""; }; + DCFE23EE19DDCD8700EF8EA9 /* ARMBaseInfo.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ARMBaseInfo.h; sourceTree = ""; }; + DCFE23EF19DDCD8700EF8EA9 /* ARMDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = ARMDisassembler.c; sourceTree = ""; }; + DCFE23F019DDCD8700EF8EA9 /* ARMDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ARMDisassembler.h; sourceTree = ""; }; + DCFE23F119DDCD8700EF8EA9 /* ARMGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = ARMGenAsmWriter.inc; sourceTree = ""; }; + DCFE23F219DDCD8700EF8EA9 /* ARMGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = ARMGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE23F319DDCD8700EF8EA9 /* ARMGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = ARMGenInstrInfo.inc; sourceTree = ""; }; + DCFE23F419DDCD8700EF8EA9 /* ARMGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = ARMGenRegisterInfo.inc; sourceTree = ""; }; + DCFE23F519DDCD8700EF8EA9 /* ARMGenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = ARMGenSubtargetInfo.inc; sourceTree = ""; }; + DCFE23F619DDCD8700EF8EA9 /* ARMInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = ARMInstPrinter.c; sourceTree = ""; }; + DCFE23F719DDCD8700EF8EA9 /* ARMInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ARMInstPrinter.h; sourceTree = ""; }; + DCFE23F819DDCD8700EF8EA9 /* ARMMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = ARMMapping.c; sourceTree = ""; }; + DCFE23F919DDCD8700EF8EA9 /* ARMMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ARMMapping.h; sourceTree = ""; }; + DCFE23FA19DDCD8700EF8EA9 /* ARMModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = ARMModule.c; sourceTree = ""; }; + DCFE23FC19DDCD8700EF8EA9 /* MipsDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = MipsDisassembler.c; sourceTree = ""; }; + DCFE23FD19DDCD8700EF8EA9 /* MipsDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = MipsDisassembler.h; sourceTree = ""; }; + DCFE23FE19DDCD8700EF8EA9 /* MipsGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = MipsGenAsmWriter.inc; sourceTree = ""; }; + DCFE23FF19DDCD8700EF8EA9 /* MipsGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = MipsGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE240019DDCD8700EF8EA9 /* MipsGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = MipsGenInstrInfo.inc; sourceTree = ""; }; + DCFE240119DDCD8700EF8EA9 /* MipsGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = MipsGenRegisterInfo.inc; sourceTree = ""; }; + DCFE240219DDCD8700EF8EA9 /* MipsGenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = MipsGenSubtargetInfo.inc; sourceTree = ""; }; + DCFE240319DDCD8700EF8EA9 /* MipsInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = MipsInstPrinter.c; sourceTree = ""; }; + DCFE240419DDCD8700EF8EA9 /* MipsInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = MipsInstPrinter.h; sourceTree = ""; }; + DCFE240519DDCD8700EF8EA9 /* MipsMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = MipsMapping.c; sourceTree = ""; }; + DCFE240619DDCD8700EF8EA9 /* MipsMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = MipsMapping.h; sourceTree = ""; }; + DCFE240719DDCD8700EF8EA9 /* MipsModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = MipsModule.c; sourceTree = ""; }; + DCFE240919DDCD8700EF8EA9 /* PPCDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = PPCDisassembler.c; sourceTree = ""; }; + DCFE240A19DDCD8700EF8EA9 /* PPCDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = PPCDisassembler.h; sourceTree = ""; }; + DCFE240B19DDCD8700EF8EA9 /* PPCGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = PPCGenAsmWriter.inc; sourceTree = ""; }; + DCFE240C19DDCD8700EF8EA9 /* PPCGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = PPCGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE240D19DDCD8700EF8EA9 /* PPCGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = PPCGenInstrInfo.inc; sourceTree = ""; }; + DCFE240E19DDCD8700EF8EA9 /* PPCGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = PPCGenRegisterInfo.inc; sourceTree = ""; }; + DCFE240F19DDCD8700EF8EA9 /* PPCGenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = PPCGenSubtargetInfo.inc; sourceTree = ""; }; + DCFE241019DDCD8700EF8EA9 /* PPCInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = PPCInstPrinter.c; sourceTree = ""; }; + DCFE241119DDCD8700EF8EA9 /* PPCInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = PPCInstPrinter.h; sourceTree = ""; }; + DCFE241219DDCD8700EF8EA9 /* PPCMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = PPCMapping.c; sourceTree = ""; }; + DCFE241319DDCD8700EF8EA9 /* PPCMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = PPCMapping.h; sourceTree = ""; }; + DCFE241419DDCD8700EF8EA9 /* PPCModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = PPCModule.c; sourceTree = ""; }; + DCFE241519DDCD8700EF8EA9 /* PPCPredicates.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = PPCPredicates.h; sourceTree = ""; }; + DCFE241719DDCD8700EF8EA9 /* Sparc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = Sparc.h; sourceTree = ""; }; + DCFE241819DDCD8700EF8EA9 /* SparcDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SparcDisassembler.c; sourceTree = ""; }; + DCFE241919DDCD8700EF8EA9 /* SparcDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SparcDisassembler.h; sourceTree = ""; }; + DCFE241A19DDCD8700EF8EA9 /* SparcGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SparcGenAsmWriter.inc; sourceTree = ""; }; + DCFE241B19DDCD8700EF8EA9 /* SparcGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SparcGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE241C19DDCD8700EF8EA9 /* SparcGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SparcGenInstrInfo.inc; sourceTree = ""; }; + DCFE241D19DDCD8700EF8EA9 /* SparcGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SparcGenRegisterInfo.inc; sourceTree = ""; }; + DCFE241E19DDCD8700EF8EA9 /* SparcGenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SparcGenSubtargetInfo.inc; sourceTree = ""; }; + DCFE241F19DDCD8800EF8EA9 /* SparcInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SparcInstPrinter.c; sourceTree = ""; }; + DCFE242019DDCD8800EF8EA9 /* SparcInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SparcInstPrinter.h; sourceTree = ""; }; + DCFE242119DDCD8800EF8EA9 /* SparcMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SparcMapping.c; sourceTree = ""; }; + DCFE242219DDCD8800EF8EA9 /* SparcMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SparcMapping.h; sourceTree = ""; }; + DCFE242319DDCD8800EF8EA9 /* SparcModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SparcModule.c; sourceTree = ""; }; + DCFE242519DDCD8800EF8EA9 /* SystemZDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SystemZDisassembler.c; sourceTree = ""; }; + DCFE242619DDCD8800EF8EA9 /* SystemZDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SystemZDisassembler.h; sourceTree = ""; }; + DCFE242719DDCD8800EF8EA9 /* SystemZGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SystemZGenAsmWriter.inc; sourceTree = ""; }; + DCFE242819DDCD8800EF8EA9 /* SystemZGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SystemZGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE242919DDCD8800EF8EA9 /* SystemZGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SystemZGenInstrInfo.inc; sourceTree = ""; }; + DCFE242A19DDCD8800EF8EA9 /* SystemZGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SystemZGenRegisterInfo.inc; sourceTree = ""; }; + DCFE242B19DDCD8800EF8EA9 /* SystemZGenSubtargetInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = SystemZGenSubtargetInfo.inc; sourceTree = ""; }; + DCFE242C19DDCD8800EF8EA9 /* SystemZInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SystemZInstPrinter.c; sourceTree = ""; }; + DCFE242D19DDCD8800EF8EA9 /* SystemZInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SystemZInstPrinter.h; sourceTree = ""; }; + DCFE242E19DDCD8800EF8EA9 /* SystemZMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SystemZMapping.c; sourceTree = ""; }; + DCFE242F19DDCD8800EF8EA9 /* SystemZMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SystemZMapping.h; sourceTree = ""; }; + DCFE243019DDCD8800EF8EA9 /* SystemZMCTargetDesc.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SystemZMCTargetDesc.c; sourceTree = ""; }; + DCFE243119DDCD8800EF8EA9 /* SystemZMCTargetDesc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = SystemZMCTargetDesc.h; sourceTree = ""; }; + DCFE243219DDCD8800EF8EA9 /* SystemZModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = SystemZModule.c; sourceTree = ""; }; + DCFE243419DDCD8800EF8EA9 /* X86ATTInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86ATTInstPrinter.c; sourceTree = ""; }; + DCFE243519DDCD8800EF8EA9 /* X86BaseInfo.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86BaseInfo.h; sourceTree = ""; }; + DCFE243619DDCD8800EF8EA9 /* X86Disassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86Disassembler.c; sourceTree = ""; }; + DCFE243719DDCD8800EF8EA9 /* X86Disassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86Disassembler.h; sourceTree = ""; }; + DCFE243819DDCD8800EF8EA9 /* X86DisassemblerDecoder.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86DisassemblerDecoder.c; sourceTree = ""; }; + DCFE243919DDCD8800EF8EA9 /* X86DisassemblerDecoder.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86DisassemblerDecoder.h; sourceTree = ""; }; + DCFE243A19DDCD8800EF8EA9 /* X86DisassemblerDecoderCommon.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86DisassemblerDecoderCommon.h; sourceTree = ""; }; + DCFE243B19DDCD8800EF8EA9 /* X86GenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenAsmWriter.inc; sourceTree = ""; }; + DCFE243C19DDCD8800EF8EA9 /* X86GenAsmWriter1.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenAsmWriter1.inc; sourceTree = ""; }; + DCFE243D19DDCD8800EF8EA9 /* X86GenAsmWriter1_reduce.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenAsmWriter1_reduce.inc; sourceTree = ""; }; + DCFE243E19DDCD8800EF8EA9 /* X86GenAsmWriter_reduce.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenAsmWriter_reduce.inc; sourceTree = ""; }; + DCFE243F19DDCD8800EF8EA9 /* X86GenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenDisassemblerTables.inc; sourceTree = ""; }; + DCFE244019DDCD8800EF8EA9 /* X86GenDisassemblerTables_reduce.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenDisassemblerTables_reduce.inc; sourceTree = ""; }; + DCFE244119DDCD8800EF8EA9 /* X86GenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenInstrInfo.inc; sourceTree = ""; }; + DCFE244219DDCD8800EF8EA9 /* X86GenInstrInfo_reduce.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenInstrInfo_reduce.inc; sourceTree = ""; }; + DCFE244319DDCD8800EF8EA9 /* X86GenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = X86GenRegisterInfo.inc; sourceTree = ""; }; + DCFE244419DDCD8800EF8EA9 /* X86InstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86InstPrinter.h; sourceTree = ""; }; + DCFE244519DDCD8800EF8EA9 /* X86IntelInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86IntelInstPrinter.c; sourceTree = ""; }; + DCFE244619DDCD8800EF8EA9 /* X86Mapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86Mapping.c; sourceTree = ""; }; + DCFE244719DDCD8800EF8EA9 /* X86Mapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = X86Mapping.h; sourceTree = ""; }; + DCFE244819DDCD8800EF8EA9 /* X86Module.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = X86Module.c; sourceTree = ""; }; + DCFE244A19DDCD8800EF8EA9 /* XCoreDisassembler.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = XCoreDisassembler.c; sourceTree = ""; }; + DCFE244B19DDCD8800EF8EA9 /* XCoreDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = XCoreDisassembler.h; sourceTree = ""; }; + DCFE244C19DDCD8800EF8EA9 /* XCoreGenAsmWriter.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = XCoreGenAsmWriter.inc; sourceTree = ""; }; + DCFE244D19DDCD8800EF8EA9 /* XCoreGenDisassemblerTables.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = XCoreGenDisassemblerTables.inc; sourceTree = ""; }; + DCFE244E19DDCD8800EF8EA9 /* XCoreGenInstrInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = XCoreGenInstrInfo.inc; sourceTree = ""; }; + DCFE244F19DDCD8800EF8EA9 /* XCoreGenRegisterInfo.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = XCoreGenRegisterInfo.inc; sourceTree = ""; }; + DCFE245019DDCD8800EF8EA9 /* XCoreInstPrinter.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = XCoreInstPrinter.c; sourceTree = ""; }; + DCFE245119DDCD8800EF8EA9 /* XCoreInstPrinter.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = XCoreInstPrinter.h; sourceTree = ""; }; + DCFE245219DDCD8800EF8EA9 /* XCoreMapping.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = XCoreMapping.c; sourceTree = ""; }; + DCFE245319DDCD8800EF8EA9 /* XCoreMapping.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = XCoreMapping.h; sourceTree = ""; }; + DCFE245419DDCD8800EF8EA9 /* XCoreModule.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = XCoreModule.c; sourceTree = ""; }; + DCFE249D19DDCDEE00EF8EA9 /* cs.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = cs.c; path = ../cs.c; sourceTree = ""; }; + DCFE249E19DDCDEE00EF8EA9 /* MCInst.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = MCInst.c; path = ../MCInst.c; sourceTree = ""; }; + DCFE249F19DDCDEE00EF8EA9 /* MCInstrDesc.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = MCInstrDesc.c; path = ../MCInstrDesc.c; sourceTree = ""; }; + DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = MCRegisterInfo.c; path = ../MCRegisterInfo.c; sourceTree = ""; }; + DCFE24A119DDCDEE00EF8EA9 /* SStream.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = SStream.c; path = ../SStream.c; sourceTree = ""; }; + DCFE24A219DDCDEE00EF8EA9 /* utils.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = utils.c; path = ../utils.c; sourceTree = ""; }; + DCFE24B019DDCE1E00EF8EA9 /* cs_priv.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = cs_priv.h; path = ../cs_priv.h; sourceTree = ""; }; + DCFE24B219DDCE1E00EF8EA9 /* LEB128.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = LEB128.h; path = ../LEB128.h; sourceTree = ""; }; + DCFE24B319DDCE1E00EF8EA9 /* MathExtras.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MathExtras.h; path = ../MathExtras.h; sourceTree = ""; }; + DCFE24B419DDCE1E00EF8EA9 /* MCDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCDisassembler.h; path = ../MCDisassembler.h; sourceTree = ""; }; + DCFE24B519DDCE1E00EF8EA9 /* MCFixedLenDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCFixedLenDisassembler.h; path = ../MCFixedLenDisassembler.h; sourceTree = ""; }; + DCFE24B619DDCE1E00EF8EA9 /* MCInst.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCInst.h; path = ../MCInst.h; sourceTree = ""; }; + DCFE24B719DDCE1E00EF8EA9 /* MCInstrDesc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCInstrDesc.h; path = ../MCInstrDesc.h; sourceTree = ""; }; + DCFE24B819DDCE1E00EF8EA9 /* MCRegisterInfo.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCRegisterInfo.h; path = ../MCRegisterInfo.h; sourceTree = ""; }; + DCFE24B919DDCE1E00EF8EA9 /* SStream.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = SStream.h; path = ../SStream.h; sourceTree = ""; }; + DCFE24BA19DDCE1E00EF8EA9 /* utils.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = utils.h; path = ../utils.h; sourceTree = ""; }; + DCFE24BC19DDCE2F00EF8EA9 /* arm.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = arm.h; sourceTree = ""; }; + DCFE24BD19DDCE2F00EF8EA9 /* arm64.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = arm64.h; sourceTree = ""; }; + DCFE24BE19DDCE2F00EF8EA9 /* capstone.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = capstone.h; sourceTree = ""; }; + DCFE24BF19DDCE2F00EF8EA9 /* mips.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = mips.h; sourceTree = ""; }; + DCFE24C019DDCE2F00EF8EA9 /* platform.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = platform.h; sourceTree = ""; }; + DCFE24C119DDCE2F00EF8EA9 /* ppc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ppc.h; sourceTree = ""; }; + DCFE24C219DDCE2F00EF8EA9 /* sparc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = sparc.h; sourceTree = ""; }; + DCFE24C319DDCE2F00EF8EA9 /* systemz.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = systemz.h; sourceTree = ""; }; + DCFE24C419DDCE2F00EF8EA9 /* x86.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = x86.h; sourceTree = ""; }; + DCFE24C519DDCE2F00EF8EA9 /* xcore.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = xcore.h; sourceTree = ""; }; +/* End PBXFileReference section */ + +/* Begin PBXFrameworksBuildPhase section */ + DC3A28D81AF29BEB00FC9913 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC3A28E41AF29C4600FC9913 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E6119DDEA5F00BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EFB19DDEB1100BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E8319DDEAA200BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC07A86E19F6061D00254FCF /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E8E19DDEAA700BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EFE19DDEB1C00BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E9919DDEAAC00BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EFF19DDEB1E00BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EA419DDEAB000BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0019DDEB2100BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EAF19DDEAB700BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0119DDEB2300BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EBA19DDEABC00BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0219DDEB2500BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EC519DDEAC100BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0319DDEB2700BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474ED019DDEAC600BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0419DDEB2A00BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EDB19DDEACC00BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F0519DDEB2D00BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EE719DDEAE400BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EFD19DDEB1A00BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474F6419DE6F3B00BCA449 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC5BFF3D19EE544E008CA585 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC5BFF4719EE547F008CA585 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCA357931BC2C0930094BB3F /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC9921181BC2C227005BE5E3 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23BA19DDCC2D00EF8EA9 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23CA19DDCC9500EF8EA9 /* Frameworks */ = { + isa = PBXFrameworksBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474F8C19DE6F8000BCA449 /* libcapstone.a in Frameworks */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; +/* End PBXFrameworksBuildPhase section */ + +/* Begin PBXGroup section */ + DC474E6B19DDEA8600BCA449 /* tests */ = { + isa = PBXGroup; + children = ( + DC474E7619DDEA9500BCA449 /* test_basic.c */, + DC474E6C19DDEA9500BCA449 /* test_arm.c */, + DC474E6D19DDEA9500BCA449 /* test_arm64.c */, + DC3A28E21AF29C0100FC9913 /* test_customized_mnem.c */, + DC474E6E19DDEA9500BCA449 /* test_detail.c */, + DC5BFF4819EE54BE008CA585 /* test_iter.c */, + DCA3579D1BC2C0EB0094BB3F /* test_m68k.c */, + DC474E6F19DDEA9500BCA449 /* test_mips.c */, + DC474E7019DDEA9500BCA449 /* test_ppc.c */, + DC474E7119DDEA9500BCA449 /* test_skipdata.c */, + DC474E7219DDEA9500BCA449 /* test_sparc.c */, + DC474E7319DDEA9500BCA449 /* test_systemz.c */, + DC474E7419DDEA9500BCA449 /* test_x86.c */, + DC474E7519DDEA9500BCA449 /* test_xcore.c */, + ); + name = tests; + sourceTree = ""; + }; + DC474F6919DE6F3B00BCA449 /* framework */ = { + isa = PBXGroup; + children = ( + 05354FA51FC6305300920005 /* module.modulemap */, + DC474F6B19DE6F3B00BCA449 /* Info.plist */, + ); + name = framework; + path = CapstoneFramework; + sourceTree = ""; + }; + DCA357791BC2BFEB0094BB3F /* M68k */ = { + isa = PBXGroup; + children = ( + DCA3577B1BC2C0290094BB3F /* M68KDisassembler.c */, + DCA3577C1BC2C0290094BB3F /* M68KDisassembler.h */, + DCA3577D1BC2C0290094BB3F /* M68KInstPrinter.c */, + DCA3577E1BC2C0290094BB3F /* M68KInstPrinter.h */, + DCA3577F1BC2C0290094BB3F /* M68KModule.c */, + ); + name = M68k; + path = M68K; + sourceTree = ""; + }; + DCC6C94C1AA6BA9C001E94C1 /* include */ = { + isa = PBXGroup; + children = ( + DCFE24BB19DDCE2F00EF8EA9 /* capstone */, + ); + name = include; + path = ../include; + sourceTree = ""; + }; + DCFE239919DDCB4900EF8EA9 = { + isa = PBXGroup; + children = ( + DCFE249D19DDCDEE00EF8EA9 /* cs.c */, + DCFE24B019DDCE1E00EF8EA9 /* cs_priv.h */, + DCFE24B219DDCE1E00EF8EA9 /* LEB128.h */, + DCFE24B319DDCE1E00EF8EA9 /* MathExtras.h */, + DCFE24B419DDCE1E00EF8EA9 /* MCDisassembler.h */, + DCFE24B519DDCE1E00EF8EA9 /* MCFixedLenDisassembler.h */, + DCFE249E19DDCDEE00EF8EA9 /* MCInst.c */, + DCFE24B619DDCE1E00EF8EA9 /* MCInst.h */, + DCFE249F19DDCDEE00EF8EA9 /* MCInstrDesc.c */, + DCFE24B719DDCE1E00EF8EA9 /* MCInstrDesc.h */, + DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */, + DCFE24B819DDCE1E00EF8EA9 /* MCRegisterInfo.h */, + DCFE24A119DDCDEE00EF8EA9 /* SStream.c */, + DCFE24B919DDCE1E00EF8EA9 /* SStream.h */, + DCFE24A219DDCDEE00EF8EA9 /* utils.c */, + DCFE24BA19DDCE1E00EF8EA9 /* utils.h */, + DCFE23DB19DDCD8700EF8EA9 /* arch */, + DCC6C94C1AA6BA9C001E94C1 /* include */, + DC474E6B19DDEA8600BCA449 /* tests */, + DC474F6919DE6F3B00BCA449 /* framework */, + DCFE23A519DDCBC300EF8EA9 /* Products */, + ); + sourceTree = ""; + }; + DCFE23A519DDCBC300EF8EA9 /* Products */ = { + isa = PBXGroup; + children = ( + DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */, + DCFE23CD19DDCC9500EF8EA9 /* libcapstone.dylib */, + DC474E6419DDEA5F00BCA449 /* test */, + DC474E8619DDEAA200BCA449 /* test_arm */, + DC474E9119DDEAA700BCA449 /* test_detail */, + DC474E9C19DDEAAC00BCA449 /* test_mips */, + DC474EA719DDEAB000BCA449 /* test_ppc */, + DC474EB219DDEAB700BCA449 /* test_skipdata */, + DC474EBD19DDEABC00BCA449 /* test_sparc */, + DC474EC819DDEAC100BCA449 /* test_systemz */, + DC474ED319DDEAC600BCA449 /* test_x86 */, + DC474EDE19DDEACC00BCA449 /* test_xcore */, + DC474EEA19DDEAE400BCA449 /* test_arm64 */, + DC474F6819DE6F3B00BCA449 /* Capstone.framework */, + DC5BFF4019EE544E008CA585 /* test_iter */, + DC3A28DB1AF29BEB00FC9913 /* test_customized_mnem */, + DCA357961BC2C0930094BB3F /* test_m68k */, + ); + name = Products; + sourceTree = ""; + }; + DCFE23DB19DDCD8700EF8EA9 /* arch */ = { + isa = PBXGroup; + children = ( + DCFE23DC19DDCD8700EF8EA9 /* AArch64 */, + DCFE23EC19DDCD8700EF8EA9 /* ARM */, + DCA357791BC2BFEB0094BB3F /* M68k */, + DCFE23FB19DDCD8700EF8EA9 /* Mips */, + DCFE240819DDCD8700EF8EA9 /* PowerPC */, + DCFE241619DDCD8700EF8EA9 /* Sparc */, + DCFE242419DDCD8800EF8EA9 /* SystemZ */, + DCFE243319DDCD8800EF8EA9 /* X86 */, + DCFE244919DDCD8800EF8EA9 /* XCore */, + ); + name = arch; + path = ../arch; + sourceTree = ""; + }; + DCFE23DC19DDCD8700EF8EA9 /* AArch64 */ = { + isa = PBXGroup; + children = ( + DCFE23DD19DDCD8700EF8EA9 /* AArch64AddressingModes.h */, + DCFE23DE19DDCD8700EF8EA9 /* AArch64BaseInfo.c */, + DCFE23DF19DDCD8700EF8EA9 /* AArch64BaseInfo.h */, + DCFE23E019DDCD8700EF8EA9 /* AArch64Disassembler.c */, + DCFE23E119DDCD8700EF8EA9 /* AArch64Disassembler.h */, + DCFE23E219DDCD8700EF8EA9 /* AArch64GenAsmWriter.inc */, + DCFE23E319DDCD8700EF8EA9 /* AArch64GenDisassemblerTables.inc */, + DCFE23E419DDCD8700EF8EA9 /* AArch64GenInstrInfo.inc */, + DCFE23E519DDCD8700EF8EA9 /* AArch64GenRegisterInfo.inc */, + DCFE23E619DDCD8700EF8EA9 /* AArch64GenSubtargetInfo.inc */, + DCFE23E719DDCD8700EF8EA9 /* AArch64InstPrinter.c */, + DCFE23E819DDCD8700EF8EA9 /* AArch64InstPrinter.h */, + DCFE23E919DDCD8700EF8EA9 /* AArch64Mapping.c */, + DCFE23EA19DDCD8700EF8EA9 /* AArch64Mapping.h */, + DCFE23EB19DDCD8700EF8EA9 /* AArch64Module.c */, + ); + path = AArch64; + sourceTree = ""; + }; + DCFE23EC19DDCD8700EF8EA9 /* ARM */ = { + isa = PBXGroup; + children = ( + DCFE23ED19DDCD8700EF8EA9 /* ARMAddressingModes.h */, + DCFE23EE19DDCD8700EF8EA9 /* ARMBaseInfo.h */, + DCFE23EF19DDCD8700EF8EA9 /* ARMDisassembler.c */, + DCFE23F019DDCD8700EF8EA9 /* ARMDisassembler.h */, + DCFE23F119DDCD8700EF8EA9 /* ARMGenAsmWriter.inc */, + DCFE23F219DDCD8700EF8EA9 /* ARMGenDisassemblerTables.inc */, + DCFE23F319DDCD8700EF8EA9 /* ARMGenInstrInfo.inc */, + DCFE23F419DDCD8700EF8EA9 /* ARMGenRegisterInfo.inc */, + DCFE23F519DDCD8700EF8EA9 /* ARMGenSubtargetInfo.inc */, + DCFE23F619DDCD8700EF8EA9 /* ARMInstPrinter.c */, + DCFE23F719DDCD8700EF8EA9 /* ARMInstPrinter.h */, + DCFE23F819DDCD8700EF8EA9 /* ARMMapping.c */, + DCFE23F919DDCD8700EF8EA9 /* ARMMapping.h */, + DCFE23FA19DDCD8700EF8EA9 /* ARMModule.c */, + ); + path = ARM; + sourceTree = ""; + }; + DCFE23FB19DDCD8700EF8EA9 /* Mips */ = { + isa = PBXGroup; + children = ( + DCFE23FC19DDCD8700EF8EA9 /* MipsDisassembler.c */, + DCFE23FD19DDCD8700EF8EA9 /* MipsDisassembler.h */, + DCFE23FE19DDCD8700EF8EA9 /* MipsGenAsmWriter.inc */, + DCFE23FF19DDCD8700EF8EA9 /* MipsGenDisassemblerTables.inc */, + DCFE240019DDCD8700EF8EA9 /* MipsGenInstrInfo.inc */, + DCFE240119DDCD8700EF8EA9 /* MipsGenRegisterInfo.inc */, + DCFE240219DDCD8700EF8EA9 /* MipsGenSubtargetInfo.inc */, + DCFE240319DDCD8700EF8EA9 /* MipsInstPrinter.c */, + DCFE240419DDCD8700EF8EA9 /* MipsInstPrinter.h */, + DCFE240519DDCD8700EF8EA9 /* MipsMapping.c */, + DCFE240619DDCD8700EF8EA9 /* MipsMapping.h */, + DCFE240719DDCD8700EF8EA9 /* MipsModule.c */, + ); + path = Mips; + sourceTree = ""; + }; + DCFE240819DDCD8700EF8EA9 /* PowerPC */ = { + isa = PBXGroup; + children = ( + DCFE240919DDCD8700EF8EA9 /* PPCDisassembler.c */, + DCFE240A19DDCD8700EF8EA9 /* PPCDisassembler.h */, + DCFE240B19DDCD8700EF8EA9 /* PPCGenAsmWriter.inc */, + DCFE240C19DDCD8700EF8EA9 /* PPCGenDisassemblerTables.inc */, + DCFE240D19DDCD8700EF8EA9 /* PPCGenInstrInfo.inc */, + DCFE240E19DDCD8700EF8EA9 /* PPCGenRegisterInfo.inc */, + DCFE240F19DDCD8700EF8EA9 /* PPCGenSubtargetInfo.inc */, + DCFE241019DDCD8700EF8EA9 /* PPCInstPrinter.c */, + DCFE241119DDCD8700EF8EA9 /* PPCInstPrinter.h */, + DCFE241219DDCD8700EF8EA9 /* PPCMapping.c */, + DCFE241319DDCD8700EF8EA9 /* PPCMapping.h */, + DCFE241419DDCD8700EF8EA9 /* PPCModule.c */, + DCFE241519DDCD8700EF8EA9 /* PPCPredicates.h */, + ); + path = PowerPC; + sourceTree = ""; + }; + DCFE241619DDCD8700EF8EA9 /* Sparc */ = { + isa = PBXGroup; + children = ( + DCFE241719DDCD8700EF8EA9 /* Sparc.h */, + DCFE241819DDCD8700EF8EA9 /* SparcDisassembler.c */, + DCFE241919DDCD8700EF8EA9 /* SparcDisassembler.h */, + DCFE241A19DDCD8700EF8EA9 /* SparcGenAsmWriter.inc */, + DCFE241B19DDCD8700EF8EA9 /* SparcGenDisassemblerTables.inc */, + DCFE241C19DDCD8700EF8EA9 /* SparcGenInstrInfo.inc */, + DCFE241D19DDCD8700EF8EA9 /* SparcGenRegisterInfo.inc */, + DCFE241E19DDCD8700EF8EA9 /* SparcGenSubtargetInfo.inc */, + DCFE241F19DDCD8800EF8EA9 /* SparcInstPrinter.c */, + DCFE242019DDCD8800EF8EA9 /* SparcInstPrinter.h */, + DCFE242119DDCD8800EF8EA9 /* SparcMapping.c */, + DCFE242219DDCD8800EF8EA9 /* SparcMapping.h */, + DCFE242319DDCD8800EF8EA9 /* SparcModule.c */, + ); + path = Sparc; + sourceTree = ""; + }; + DCFE242419DDCD8800EF8EA9 /* SystemZ */ = { + isa = PBXGroup; + children = ( + DCFE242519DDCD8800EF8EA9 /* SystemZDisassembler.c */, + DCFE242619DDCD8800EF8EA9 /* SystemZDisassembler.h */, + DCFE242719DDCD8800EF8EA9 /* SystemZGenAsmWriter.inc */, + DCFE242819DDCD8800EF8EA9 /* SystemZGenDisassemblerTables.inc */, + DCFE242919DDCD8800EF8EA9 /* SystemZGenInstrInfo.inc */, + DCFE242A19DDCD8800EF8EA9 /* SystemZGenRegisterInfo.inc */, + DCFE242B19DDCD8800EF8EA9 /* SystemZGenSubtargetInfo.inc */, + DCFE242C19DDCD8800EF8EA9 /* SystemZInstPrinter.c */, + DCFE242D19DDCD8800EF8EA9 /* SystemZInstPrinter.h */, + DCFE242E19DDCD8800EF8EA9 /* SystemZMapping.c */, + DCFE242F19DDCD8800EF8EA9 /* SystemZMapping.h */, + DCFE243019DDCD8800EF8EA9 /* SystemZMCTargetDesc.c */, + DCFE243119DDCD8800EF8EA9 /* SystemZMCTargetDesc.h */, + DCFE243219DDCD8800EF8EA9 /* SystemZModule.c */, + ); + path = SystemZ; + sourceTree = ""; + }; + DCFE243319DDCD8800EF8EA9 /* X86 */ = { + isa = PBXGroup; + children = ( + DCFE243419DDCD8800EF8EA9 /* X86ATTInstPrinter.c */, + DCFE243519DDCD8800EF8EA9 /* X86BaseInfo.h */, + DCFE243619DDCD8800EF8EA9 /* X86Disassembler.c */, + DCFE243719DDCD8800EF8EA9 /* X86Disassembler.h */, + DCFE243819DDCD8800EF8EA9 /* X86DisassemblerDecoder.c */, + DCFE243919DDCD8800EF8EA9 /* X86DisassemblerDecoder.h */, + DCFE243A19DDCD8800EF8EA9 /* X86DisassemblerDecoderCommon.h */, + DCFE243B19DDCD8800EF8EA9 /* X86GenAsmWriter.inc */, + DCFE243C19DDCD8800EF8EA9 /* X86GenAsmWriter1.inc */, + DCFE243D19DDCD8800EF8EA9 /* X86GenAsmWriter1_reduce.inc */, + DCFE243E19DDCD8800EF8EA9 /* X86GenAsmWriter_reduce.inc */, + DCFE243F19DDCD8800EF8EA9 /* X86GenDisassemblerTables.inc */, + DCFE244019DDCD8800EF8EA9 /* X86GenDisassemblerTables_reduce.inc */, + DCFE244119DDCD8800EF8EA9 /* X86GenInstrInfo.inc */, + DCFE244219DDCD8800EF8EA9 /* X86GenInstrInfo_reduce.inc */, + DCFE244319DDCD8800EF8EA9 /* X86GenRegisterInfo.inc */, + DCFE244419DDCD8800EF8EA9 /* X86InstPrinter.h */, + DCFE244519DDCD8800EF8EA9 /* X86IntelInstPrinter.c */, + DCFE244619DDCD8800EF8EA9 /* X86Mapping.c */, + DCFE244719DDCD8800EF8EA9 /* X86Mapping.h */, + DCFE244819DDCD8800EF8EA9 /* X86Module.c */, + ); + path = X86; + sourceTree = ""; + }; + DCFE244919DDCD8800EF8EA9 /* XCore */ = { + isa = PBXGroup; + children = ( + DCFE244A19DDCD8800EF8EA9 /* XCoreDisassembler.c */, + DCFE244B19DDCD8800EF8EA9 /* XCoreDisassembler.h */, + DCFE244C19DDCD8800EF8EA9 /* XCoreGenAsmWriter.inc */, + DCFE244D19DDCD8800EF8EA9 /* XCoreGenDisassemblerTables.inc */, + DCFE244E19DDCD8800EF8EA9 /* XCoreGenInstrInfo.inc */, + DCFE244F19DDCD8800EF8EA9 /* XCoreGenRegisterInfo.inc */, + DCFE245019DDCD8800EF8EA9 /* XCoreInstPrinter.c */, + DCFE245119DDCD8800EF8EA9 /* XCoreInstPrinter.h */, + DCFE245219DDCD8800EF8EA9 /* XCoreMapping.c */, + DCFE245319DDCD8800EF8EA9 /* XCoreMapping.h */, + DCFE245419DDCD8800EF8EA9 /* XCoreModule.c */, + ); + path = XCore; + sourceTree = ""; + }; + DCFE24BB19DDCE2F00EF8EA9 /* capstone */ = { + isa = PBXGroup; + children = ( + DCFE24BC19DDCE2F00EF8EA9 /* arm.h */, + DCFE24BD19DDCE2F00EF8EA9 /* arm64.h */, + DCFE24BE19DDCE2F00EF8EA9 /* capstone.h */, + DCA3579F1BC2C14E0094BB3F /* m68k.h */, + 0537EAAB1FC6286300F06BF9 /* m680x.h */, + DCFE24BF19DDCE2F00EF8EA9 /* mips.h */, + DCFE24C019DDCE2F00EF8EA9 /* platform.h */, + DCFE24C119DDCE2F00EF8EA9 /* ppc.h */, + DCFE24C219DDCE2F00EF8EA9 /* sparc.h */, + DCFE24C319DDCE2F00EF8EA9 /* systemz.h */, + 0537EAA91FC6284E00F06BF9 /* tms320c64x.h */, + DCFE24C419DDCE2F00EF8EA9 /* x86.h */, + DCFE24C519DDCE2F00EF8EA9 /* xcore.h */, + ); + path = capstone; + sourceTree = ""; + }; +/* End PBXGroup section */ + +/* Begin PBXHeadersBuildPhase section */ + DC474F6519DE6F3B00BCA449 /* Headers */ = { + isa = PBXHeadersBuildPhase; + buildActionMask = 2147483647; + files = ( + 05354FA41FC62FCC00920005 /* m68k.h in Headers */, + DCA357881BC2C0290094BB3F /* M68KDisassembler.h in Headers */, + DC474F8119DE6F6B00BCA449 /* arm.h in Headers */, + DC474F8219DE6F6B00BCA449 /* arm64.h in Headers */, + DC474F8319DE6F6B00BCA449 /* capstone.h in Headers */, + DC474F8419DE6F6B00BCA449 /* mips.h in Headers */, + DC474F8519DE6F6B00BCA449 /* platform.h in Headers */, + DC474F8619DE6F6B00BCA449 /* ppc.h in Headers */, + DC474F8719DE6F6B00BCA449 /* sparc.h in Headers */, + DC474F8819DE6F6B00BCA449 /* systemz.h in Headers */, + DC474F8919DE6F6B00BCA449 /* x86.h in Headers */, + 0537EAAC1FC6286300F06BF9 /* m680x.h in Headers */, + DCA3578E1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */, + 0537EAAA1FC6284F00F06BF9 /* tms320c64x.h in Headers */, + DC474F8A19DE6F6B00BCA449 /* xcore.h in Headers */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23BB19DDCC2D00EF8EA9 /* Headers */ = { + isa = PBXHeadersBuildPhase; + buildActionMask = 2147483647; + files = ( + DCA3578C1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */, + DCA357861BC2C0290094BB3F /* M68KDisassembler.h in Headers */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23CB19DDCC9500EF8EA9 /* Headers */ = { + isa = PBXHeadersBuildPhase; + buildActionMask = 2147483647; + files = ( + DCA3578D1BC2C0290094BB3F /* M68KInstPrinter.h in Headers */, + DCA357871BC2C0290094BB3F /* M68KDisassembler.h in Headers */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; +/* End PBXHeadersBuildPhase section */ + +/* Begin PBXNativeTarget section */ + DC3A28DA1AF29BEB00FC9913 /* test_customized_mnem */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC3A28DF1AF29BEB00FC9913 /* Build configuration list for PBXNativeTarget "test_customized_mnem" */; + buildPhases = ( + DC3A28D71AF29BEB00FC9913 /* Sources */, + DC3A28D81AF29BEB00FC9913 /* Frameworks */, + DC3A28D91AF29BEB00FC9913 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_customized_mnem; + productName = test_customized_mnem; + productReference = DC3A28DB1AF29BEB00FC9913 /* test_customized_mnem */; + productType = "com.apple.product-type.tool"; + }; + DC474E6319DDEA5F00BCA449 /* test */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474E6A19DDEA5F00BCA449 /* Build configuration list for PBXNativeTarget "test_basic" */; + buildPhases = ( + DC474E6019DDEA5F00BCA449 /* Sources */, + DC474E6119DDEA5F00BCA449 /* Frameworks */, + DC474E6219DDEA5F00BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_basic; + productName = test_basic; + productReference = DC474E6419DDEA5F00BCA449 /* test */; + productType = "com.apple.product-type.tool"; + }; + DC474E8519DDEAA200BCA449 /* test_arm */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474E8A19DDEAA200BCA449 /* Build configuration list for PBXNativeTarget "test_arm" */; + buildPhases = ( + DC474E8219DDEAA200BCA449 /* Sources */, + DC474E8319DDEAA200BCA449 /* Frameworks */, + DC474E8419DDEAA200BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_arm; + productName = test_arm; + productReference = DC474E8619DDEAA200BCA449 /* test_arm */; + productType = "com.apple.product-type.tool"; + }; + DC474E9019DDEAA700BCA449 /* test_detail */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474E9519DDEAA700BCA449 /* Build configuration list for PBXNativeTarget "test_detail" */; + buildPhases = ( + DC474E8D19DDEAA700BCA449 /* Sources */, + DC474E8E19DDEAA700BCA449 /* Frameworks */, + DC474E8F19DDEAA700BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_detail; + productName = test_detail; + productReference = DC474E9119DDEAA700BCA449 /* test_detail */; + productType = "com.apple.product-type.tool"; + }; + DC474E9B19DDEAAC00BCA449 /* test_mips */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EA019DDEAAC00BCA449 /* Build configuration list for PBXNativeTarget "test_mips" */; + buildPhases = ( + DC474E9819DDEAAC00BCA449 /* Sources */, + DC474E9919DDEAAC00BCA449 /* Frameworks */, + DC474E9A19DDEAAC00BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_mips; + productName = test_mips; + productReference = DC474E9C19DDEAAC00BCA449 /* test_mips */; + productType = "com.apple.product-type.tool"; + }; + DC474EA619DDEAB000BCA449 /* test_ppc */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EAB19DDEAB000BCA449 /* Build configuration list for PBXNativeTarget "test_ppc" */; + buildPhases = ( + DC474EA319DDEAB000BCA449 /* Sources */, + DC474EA419DDEAB000BCA449 /* Frameworks */, + DC474EA519DDEAB000BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_ppc; + productName = test_ppc; + productReference = DC474EA719DDEAB000BCA449 /* test_ppc */; + productType = "com.apple.product-type.tool"; + }; + DC474EB119DDEAB700BCA449 /* test_skipdata */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EB619DDEAB700BCA449 /* Build configuration list for PBXNativeTarget "test_skipdata" */; + buildPhases = ( + DC474EAE19DDEAB700BCA449 /* Sources */, + DC474EAF19DDEAB700BCA449 /* Frameworks */, + DC474EB019DDEAB700BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_skipdata; + productName = test_skipdata; + productReference = DC474EB219DDEAB700BCA449 /* test_skipdata */; + productType = "com.apple.product-type.tool"; + }; + DC474EBC19DDEABC00BCA449 /* test_sparc */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EC119DDEABC00BCA449 /* Build configuration list for PBXNativeTarget "test_sparc" */; + buildPhases = ( + DC474EB919DDEABC00BCA449 /* Sources */, + DC474EBA19DDEABC00BCA449 /* Frameworks */, + DC474EBB19DDEABC00BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_sparc; + productName = test_sparc; + productReference = DC474EBD19DDEABC00BCA449 /* test_sparc */; + productType = "com.apple.product-type.tool"; + }; + DC474EC719DDEAC100BCA449 /* test_systemz */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474ECC19DDEAC100BCA449 /* Build configuration list for PBXNativeTarget "test_systemz" */; + buildPhases = ( + DC474EC419DDEAC100BCA449 /* Sources */, + DC474EC519DDEAC100BCA449 /* Frameworks */, + DC474EC619DDEAC100BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_systemz; + productName = test_systemz; + productReference = DC474EC819DDEAC100BCA449 /* test_systemz */; + productType = "com.apple.product-type.tool"; + }; + DC474ED219DDEAC600BCA449 /* test_x86 */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474ED719DDEAC600BCA449 /* Build configuration list for PBXNativeTarget "test_x86" */; + buildPhases = ( + DC474ECF19DDEAC600BCA449 /* Sources */, + DC474ED019DDEAC600BCA449 /* Frameworks */, + DC474ED119DDEAC600BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_x86; + productName = test_x86; + productReference = DC474ED319DDEAC600BCA449 /* test_x86 */; + productType = "com.apple.product-type.tool"; + }; + DC474EDD19DDEACC00BCA449 /* test_xcore */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EE219DDEACC00BCA449 /* Build configuration list for PBXNativeTarget "test_xcore" */; + buildPhases = ( + DC474EDA19DDEACC00BCA449 /* Sources */, + DC474EDB19DDEACC00BCA449 /* Frameworks */, + DC474EDC19DDEACC00BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_xcore; + productName = test_xcore; + productReference = DC474EDE19DDEACC00BCA449 /* test_xcore */; + productType = "com.apple.product-type.tool"; + }; + DC474EE919DDEAE400BCA449 /* test_arm64 */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474EEE19DDEAE400BCA449 /* Build configuration list for PBXNativeTarget "test_arm64" */; + buildPhases = ( + DC474EE619DDEAE400BCA449 /* Sources */, + DC474EE719DDEAE400BCA449 /* Frameworks */, + DC474EE819DDEAE400BCA449 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_arm64; + productName = test_arm64; + productReference = DC474EEA19DDEAE400BCA449 /* test_arm64 */; + productType = "com.apple.product-type.tool"; + }; + DC474F6719DE6F3B00BCA449 /* CapstoneFramework */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC474F7F19DE6F3C00BCA449 /* Build configuration list for PBXNativeTarget "CapstoneFramework" */; + buildPhases = ( + DC474F6319DE6F3B00BCA449 /* Sources */, + DC474F6419DE6F3B00BCA449 /* Frameworks */, + DC474F6519DE6F3B00BCA449 /* Headers */, + DC474F6619DE6F3B00BCA449 /* Resources */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = CapstoneFramework; + productName = CapstoneFramework; + productReference = DC474F6819DE6F3B00BCA449 /* Capstone.framework */; + productType = "com.apple.product-type.framework"; + }; + DC5BFF3F19EE544E008CA585 /* test_iter */ = { + isa = PBXNativeTarget; + buildConfigurationList = DC5BFF4619EE544E008CA585 /* Build configuration list for PBXNativeTarget "test_iter" */; + buildPhases = ( + DC5BFF3C19EE544E008CA585 /* Sources */, + DC5BFF3D19EE544E008CA585 /* Frameworks */, + DC5BFF3E19EE544E008CA585 /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_iter; + productName = test_iter; + productReference = DC5BFF4019EE544E008CA585 /* test_iter */; + productType = "com.apple.product-type.tool"; + }; + DCA357951BC2C0930094BB3F /* test_m68k */ = { + isa = PBXNativeTarget; + buildConfigurationList = DCA3579A1BC2C0930094BB3F /* Build configuration list for PBXNativeTarget "test_m68k" */; + buildPhases = ( + DCA357921BC2C0930094BB3F /* Sources */, + DCA357931BC2C0930094BB3F /* Frameworks */, + DCA357941BC2C0930094BB3F /* CopyFiles */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = test_m68k; + productName = test_m68k; + productReference = DCA357961BC2C0930094BB3F /* test_m68k */; + productType = "com.apple.product-type.tool"; + }; + DCFE23BC19DDCC2D00EF8EA9 /* CapstoneStatic */ = { + isa = PBXNativeTarget; + buildConfigurationList = DCFE23BE19DDCC2D00EF8EA9 /* Build configuration list for PBXNativeTarget "CapstoneStatic" */; + buildPhases = ( + DCFE23B919DDCC2D00EF8EA9 /* Sources */, + DCFE23BA19DDCC2D00EF8EA9 /* Frameworks */, + DCFE23BB19DDCC2D00EF8EA9 /* Headers */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = CapstoneStatic; + productName = CapstoneStatic; + productReference = DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */; + productType = "com.apple.product-type.library.static"; + }; + DCFE23CC19DDCC9500EF8EA9 /* CapstoneDynamic */ = { + isa = PBXNativeTarget; + buildConfigurationList = DCFE23CE19DDCC9500EF8EA9 /* Build configuration list for PBXNativeTarget "CapstoneDynamic" */; + buildPhases = ( + DCFE23C919DDCC9500EF8EA9 /* Sources */, + DCFE23CA19DDCC9500EF8EA9 /* Frameworks */, + DCFE23CB19DDCC9500EF8EA9 /* Headers */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = CapstoneDynamic; + productName = CapstoneDynamic; + productReference = DCFE23CD19DDCC9500EF8EA9 /* libcapstone.dylib */; + productType = "com.apple.product-type.library.dynamic"; + }; +/* End PBXNativeTarget section */ + +/* Begin PBXProject section */ + DCFE239A19DDCB4900EF8EA9 /* Project object */ = { + isa = PBXProject; + attributes = { + LastUpgradeCheck = 0910; + TargetAttributes = { + DC3A28DA1AF29BEB00FC9913 = { + CreatedOnToolsVersion = 6.3.1; + }; + DC474E6319DDEA5F00BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474E8519DDEAA200BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474E9019DDEAA700BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474E9B19DDEAAC00BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EA619DDEAB000BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EB119DDEAB700BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EBC19DDEABC00BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EC719DDEAC100BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474ED219DDEAC600BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EDD19DDEACC00BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474EE919DDEAE400BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC474F6719DE6F3B00BCA449 = { + CreatedOnToolsVersion = 6.1; + }; + DC5BFF3F19EE544E008CA585 = { + CreatedOnToolsVersion = 6.1; + }; + DCA357951BC2C0930094BB3F = { + CreatedOnToolsVersion = 7.0; + }; + DCFE23BC19DDCC2D00EF8EA9 = { + CreatedOnToolsVersion = 6.1; + }; + DCFE23CC19DDCC9500EF8EA9 = { + CreatedOnToolsVersion = 6.1; + }; + }; + }; + buildConfigurationList = DCFE239D19DDCB4900EF8EA9 /* Build configuration list for PBXProject "Capstone" */; + compatibilityVersion = "Xcode 3.2"; + developmentRegion = English; + hasScannedForEncodings = 0; + knownRegions = ( + en, + ); + mainGroup = DCFE239919DDCB4900EF8EA9; + productRefGroup = DCFE23A519DDCBC300EF8EA9 /* Products */; + projectDirPath = ""; + projectRoot = ""; + targets = ( + DCFE23BC19DDCC2D00EF8EA9 /* CapstoneStatic */, + DCFE23CC19DDCC9500EF8EA9 /* CapstoneDynamic */, + DC474F6719DE6F3B00BCA449 /* CapstoneFramework */, + DC474E6319DDEA5F00BCA449 /* test_basic */, + DC474E8519DDEAA200BCA449 /* test_arm */, + DC474EE919DDEAE400BCA449 /* test_arm64 */, + DC3A28DA1AF29BEB00FC9913 /* test_customized_mnem */, + DC474E9019DDEAA700BCA449 /* test_detail */, + DC5BFF3F19EE544E008CA585 /* test_iter */, + DCA357951BC2C0930094BB3F /* test_m68k */, + DC474E9B19DDEAAC00BCA449 /* test_mips */, + DC474EA619DDEAB000BCA449 /* test_ppc */, + DC474EB119DDEAB700BCA449 /* test_skipdata */, + DC474EBC19DDEABC00BCA449 /* test_sparc */, + DC474EC719DDEAC100BCA449 /* test_systemz */, + DC474ED219DDEAC600BCA449 /* test_x86 */, + DC474EDD19DDEACC00BCA449 /* test_xcore */, + ); + }; +/* End PBXProject section */ + +/* Begin PBXResourcesBuildPhase section */ + DC474F6619DE6F3B00BCA449 /* Resources */ = { + isa = PBXResourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + ); + runOnlyForDeploymentPostprocessing = 0; + }; +/* End PBXResourcesBuildPhase section */ + +/* Begin PBXSourcesBuildPhase section */ + DC3A28D71AF29BEB00FC9913 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC3A28E31AF29C0100FC9913 /* test_customized_mnem.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E6019DDEA5F00BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EFA19DDEB0200BCA449 /* test_basic.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E8219DDEAA200BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EE519DDEAD900BCA449 /* test_arm.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E8D19DDEAA700BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF219DDEAF000BCA449 /* test_detail.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474E9819DDEAAC00BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF319DDEAF200BCA449 /* test_mips.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EA319DDEAB000BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF419DDEAF400BCA449 /* test_ppc.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EAE19DDEAB700BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF519DDEAF600BCA449 /* test_skipdata.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EB919DDEABC00BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF619DDEAF800BCA449 /* test_sparc.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EC419DDEAC100BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF719DDEAFA00BCA449 /* test_systemz.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474ECF19DDEAC600BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF819DDEAFD00BCA449 /* test_x86.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EDA19DDEACC00BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF919DDEB0000BCA449 /* test_xcore.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474EE619DDEAE400BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474EF119DDEAED00BCA449 /* test_arm64.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC474F6319DE6F3B00BCA449 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474FCF19DE6FDA00BCA449 /* SparcInstPrinter.c in Sources */, + DC474FBD19DE6FDA00BCA449 /* AArch64BaseInfo.c in Sources */, + DC474FDF19DE6FDA00BCA449 /* XCoreMapping.c in Sources */, + DC474FD719DE6FDA00BCA449 /* X86ATTInstPrinter.c in Sources */, + DC474FD019DE6FDA00BCA449 /* SparcMapping.c in Sources */, + DC474FC119DE6FDA00BCA449 /* AArch64Module.c in Sources */, + DC474FC319DE6FDA00BCA449 /* ARMInstPrinter.c in Sources */, + DC474FDE19DE6FDA00BCA449 /* XCoreInstPrinter.c in Sources */, + DC474FDC19DE6FDA00BCA449 /* X86Module.c in Sources */, + DC474FE019DE6FDA00BCA449 /* XCoreModule.c in Sources */, + DCA3578B1BC2C0290094BB3F /* M68KInstPrinter.c in Sources */, + DC474FD619DE6FDA00BCA449 /* SystemZModule.c in Sources */, + DC474FCA19DE6FDA00BCA449 /* PPCDisassembler.c in Sources */, + DC474FD919DE6FDA00BCA449 /* X86DisassemblerDecoder.c in Sources */, + DC474FC819DE6FDA00BCA449 /* MipsMapping.c in Sources */, + DC474FD119DE6FDA00BCA449 /* SparcModule.c in Sources */, + DC474FDD19DE6FDA00BCA449 /* XCoreDisassembler.c in Sources */, + DC474FD819DE6FDA00BCA449 /* X86Disassembler.c in Sources */, + DC474FC519DE6FDA00BCA449 /* ARMModule.c in Sources */, + DC474FC719DE6FDA00BCA449 /* MipsInstPrinter.c in Sources */, + DC474F9319DE6FCD00BCA449 /* cs.c in Sources */, + DC474FCD19DE6FDA00BCA449 /* PPCModule.c in Sources */, + DC474F9519DE6FCD00BCA449 /* MCInstrDesc.c in Sources */, + DC474FD519DE6FDA00BCA449 /* SystemZMCTargetDesc.c in Sources */, + DC474F9719DE6FCD00BCA449 /* SStream.c in Sources */, + DC474FCE19DE6FDA00BCA449 /* SparcDisassembler.c in Sources */, + DC474FD219DE6FDA00BCA449 /* SystemZDisassembler.c in Sources */, + DC474FC919DE6FDA00BCA449 /* MipsModule.c in Sources */, + DC474FC019DE6FDA00BCA449 /* AArch64Mapping.c in Sources */, + DC474FBF19DE6FDA00BCA449 /* AArch64InstPrinter.c in Sources */, + DC474FCB19DE6FDA00BCA449 /* PPCInstPrinter.c in Sources */, + DCA357851BC2C0290094BB3F /* M68KDisassembler.c in Sources */, + DC474FD319DE6FDA00BCA449 /* SystemZInstPrinter.c in Sources */, + DC474FDA19DE6FDA00BCA449 /* X86IntelInstPrinter.c in Sources */, + DC474FDB19DE6FDA00BCA449 /* X86Mapping.c in Sources */, + DC474F9819DE6FCD00BCA449 /* utils.c in Sources */, + DC474FC619DE6FDA00BCA449 /* MipsDisassembler.c in Sources */, + DC474FCC19DE6FDA00BCA449 /* PPCMapping.c in Sources */, + DCA357911BC2C0290094BB3F /* M68KModule.c in Sources */, + DC474FC419DE6FDA00BCA449 /* ARMMapping.c in Sources */, + DC474FC219DE6FDA00BCA449 /* ARMDisassembler.c in Sources */, + DC474FD419DE6FDA00BCA449 /* SystemZMapping.c in Sources */, + DC474FBE19DE6FDA00BCA449 /* AArch64Disassembler.c in Sources */, + DC474F9619DE6FCD00BCA449 /* MCRegisterInfo.c in Sources */, + DC474F9419DE6FCD00BCA449 /* MCInst.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DC5BFF3C19EE544E008CA585 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC5BFF4919EE54BE008CA585 /* test_iter.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCA357921BC2C0930094BB3F /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DCA3579E1BC2C0EB0094BB3F /* test_m68k.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23B919DDCC2D00EF8EA9 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DCFE249519DDCDD000EF8EA9 /* XCoreDisassembler.c in Sources */, + DCFE246A19DDCDA000EF8EA9 /* MipsModule.c in Sources */, + DCFE247019DDCDA700EF8EA9 /* PPCInstPrinter.c in Sources */, + DCFE248C19DDCDC000EF8EA9 /* X86IntelInstPrinter.c in Sources */, + DCFE246F19DDCDA700EF8EA9 /* PPCDisassembler.c in Sources */, + DCFE245519DDCD9200EF8EA9 /* AArch64BaseInfo.c in Sources */, + DCFE246119DDCD9900EF8EA9 /* ARMMapping.c in Sources */, + DCFE245719DDCD9200EF8EA9 /* AArch64InstPrinter.c in Sources */, + DCFE24A319DDCDEE00EF8EA9 /* cs.c in Sources */, + DCFE248019DDCDB700EF8EA9 /* SystemZInstPrinter.c in Sources */, + DCA357891BC2C0290094BB3F /* M68KInstPrinter.c in Sources */, + DCFE24A919DDCDEE00EF8EA9 /* MCRegisterInfo.c in Sources */, + DCFE248E19DDCDC000EF8EA9 /* X86Module.c in Sources */, + DCFE248319DDCDB700EF8EA9 /* SystemZModule.c in Sources */, + DCFE248D19DDCDC000EF8EA9 /* X86Mapping.c in Sources */, + DCFE246919DDCDA000EF8EA9 /* MipsMapping.c in Sources */, + DCFE24AD19DDCDEE00EF8EA9 /* utils.c in Sources */, + DCFE247A19DDCDAD00EF8EA9 /* SparcModule.c in Sources */, + DCFE247819DDCDAD00EF8EA9 /* SparcInstPrinter.c in Sources */, + DCFE245F19DDCD9900EF8EA9 /* ARMDisassembler.c in Sources */, + DCFE24A519DDCDEE00EF8EA9 /* MCInst.c in Sources */, + DCFE249619DDCDD000EF8EA9 /* XCoreInstPrinter.c in Sources */, + DCFE246819DDCDA000EF8EA9 /* MipsInstPrinter.c in Sources */, + DCFE247F19DDCDB700EF8EA9 /* SystemZDisassembler.c in Sources */, + DCFE248919DDCDC000EF8EA9 /* X86ATTInstPrinter.c in Sources */, + DCFE24A719DDCDEE00EF8EA9 /* MCInstrDesc.c in Sources */, + DCFE246719DDCDA000EF8EA9 /* MipsDisassembler.c in Sources */, + DCFE245819DDCD9200EF8EA9 /* AArch64Mapping.c in Sources */, + DCFE247919DDCDAD00EF8EA9 /* SparcMapping.c in Sources */, + DCFE248A19DDCDC000EF8EA9 /* X86Disassembler.c in Sources */, + DCFE249719DDCDD000EF8EA9 /* XCoreMapping.c in Sources */, + DCA357831BC2C0290094BB3F /* M68KDisassembler.c in Sources */, + DCFE247719DDCDAD00EF8EA9 /* SparcDisassembler.c in Sources */, + DCFE246019DDCD9900EF8EA9 /* ARMInstPrinter.c in Sources */, + DCFE248B19DDCDC000EF8EA9 /* X86DisassemblerDecoder.c in Sources */, + DCFE248219DDCDB700EF8EA9 /* SystemZMCTargetDesc.c in Sources */, + DCFE247119DDCDA700EF8EA9 /* PPCMapping.c in Sources */, + DCFE246219DDCD9900EF8EA9 /* ARMModule.c in Sources */, + DCA3578F1BC2C0290094BB3F /* M68KModule.c in Sources */, + DCFE24AB19DDCDEE00EF8EA9 /* SStream.c in Sources */, + DCFE248119DDCDB700EF8EA9 /* SystemZMapping.c in Sources */, + DCFE247219DDCDA700EF8EA9 /* PPCModule.c in Sources */, + DCFE249819DDCDD000EF8EA9 /* XCoreModule.c in Sources */, + DCFE245619DDCD9200EF8EA9 /* AArch64Disassembler.c in Sources */, + DCFE245919DDCD9200EF8EA9 /* AArch64Module.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; + DCFE23C919DDCC9500EF8EA9 /* Sources */ = { + isa = PBXSourcesBuildPhase; + buildActionMask = 2147483647; + files = ( + DC474FAB19DE6FDA00BCA449 /* SparcInstPrinter.c in Sources */, + DC474F9919DE6FDA00BCA449 /* AArch64BaseInfo.c in Sources */, + DC474FBB19DE6FDA00BCA449 /* XCoreMapping.c in Sources */, + DC474FB319DE6FDA00BCA449 /* X86ATTInstPrinter.c in Sources */, + DC474FAC19DE6FDA00BCA449 /* SparcMapping.c in Sources */, + DC474F9D19DE6FDA00BCA449 /* AArch64Module.c in Sources */, + DC474F9F19DE6FDA00BCA449 /* ARMInstPrinter.c in Sources */, + DC474FBA19DE6FDA00BCA449 /* XCoreInstPrinter.c in Sources */, + DC474FB819DE6FDA00BCA449 /* X86Module.c in Sources */, + DC474FBC19DE6FDA00BCA449 /* XCoreModule.c in Sources */, + DCA3578A1BC2C0290094BB3F /* M68KInstPrinter.c in Sources */, + DC474FB219DE6FDA00BCA449 /* SystemZModule.c in Sources */, + DC474FA619DE6FDA00BCA449 /* PPCDisassembler.c in Sources */, + DC474FB519DE6FDA00BCA449 /* X86DisassemblerDecoder.c in Sources */, + DC474FA419DE6FDA00BCA449 /* MipsMapping.c in Sources */, + DC474FAD19DE6FDA00BCA449 /* SparcModule.c in Sources */, + DC474FB919DE6FDA00BCA449 /* XCoreDisassembler.c in Sources */, + DC474FB419DE6FDA00BCA449 /* X86Disassembler.c in Sources */, + DC474FA119DE6FDA00BCA449 /* ARMModule.c in Sources */, + DC474FA319DE6FDA00BCA449 /* MipsInstPrinter.c in Sources */, + DC474F8D19DE6FCD00BCA449 /* cs.c in Sources */, + DC474FA919DE6FDA00BCA449 /* PPCModule.c in Sources */, + DC474F8F19DE6FCD00BCA449 /* MCInstrDesc.c in Sources */, + DC474FB119DE6FDA00BCA449 /* SystemZMCTargetDesc.c in Sources */, + DC474F9119DE6FCD00BCA449 /* SStream.c in Sources */, + DC474FAA19DE6FDA00BCA449 /* SparcDisassembler.c in Sources */, + DC474FAE19DE6FDA00BCA449 /* SystemZDisassembler.c in Sources */, + DC474FA519DE6FDA00BCA449 /* MipsModule.c in Sources */, + DC474F9C19DE6FDA00BCA449 /* AArch64Mapping.c in Sources */, + DC474F9B19DE6FDA00BCA449 /* AArch64InstPrinter.c in Sources */, + DC474FA719DE6FDA00BCA449 /* PPCInstPrinter.c in Sources */, + DCA357841BC2C0290094BB3F /* M68KDisassembler.c in Sources */, + DC474FAF19DE6FDA00BCA449 /* SystemZInstPrinter.c in Sources */, + DC474FB619DE6FDA00BCA449 /* X86IntelInstPrinter.c in Sources */, + DC474FB719DE6FDA00BCA449 /* X86Mapping.c in Sources */, + DC474F9219DE6FCD00BCA449 /* utils.c in Sources */, + DC474FA219DE6FDA00BCA449 /* MipsDisassembler.c in Sources */, + DC474FA819DE6FDA00BCA449 /* PPCMapping.c in Sources */, + DCA357901BC2C0290094BB3F /* M68KModule.c in Sources */, + DC474FA019DE6FDA00BCA449 /* ARMMapping.c in Sources */, + DC474F9E19DE6FDA00BCA449 /* ARMDisassembler.c in Sources */, + DC474FB019DE6FDA00BCA449 /* SystemZMapping.c in Sources */, + DC474F9A19DE6FDA00BCA449 /* AArch64Disassembler.c in Sources */, + DC474F9019DE6FCD00BCA449 /* MCRegisterInfo.c in Sources */, + DC474F8E19DE6FCD00BCA449 /* MCInst.c in Sources */, + ); + runOnlyForDeploymentPostprocessing = 0; + }; +/* End PBXSourcesBuildPhase section */ + +/* Begin XCBuildConfiguration section */ + DC3A28E01AF29BEB00FC9913 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + DEBUG_INFORMATION_FORMAT = dwarf; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_NO_COMMON_BLOCKS = YES; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.10; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC3A28E11AF29BEB00FC9913 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_NO_COMMON_BLOCKS = YES; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.10; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474E6819DDEA5F00BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474E6919DDEA5F00BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474E8B19DDEAA200BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474E8C19DDEAA200BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474E9619DDEAA700BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474E9719DDEAA700BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EA119DDEAAC00BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EA219DDEAAC00BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EAC19DDEAB000BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EAD19DDEAB000BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EB719DDEAB700BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EB819DDEAB700BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EC219DDEABC00BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EC319DDEABC00BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474ECD19DDEAC100BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474ECE19DDEAC100BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474ED819DDEAC600BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474ED919DDEAC600BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EE319DDEACC00BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EE419DDEACC00BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474EEF19DDEAE400BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC474EF019DDEAE400BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DC474F7B19DE6F3C00BCA449 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = NO; + CURRENT_PROJECT_VERSION = 3.0; + DEFINES_MODULE = YES; + DYLIB_COMPATIBILITY_VERSION = 1; + DYLIB_CURRENT_VERSION = 1; + DYLIB_INSTALL_NAME_BASE = "@rpath"; + ENABLE_STRICT_OBJC_MSGSEND = YES; + FRAMEWORK_VERSION = A; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "CAPSTONE_SHARED=1", + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + INFOPLIST_FILE = CapstoneFramework/Info.plist; + INSTALL_PATH = "@rpath"; + LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks @loader_path/Frameworks"; + MACOSX_DEPLOYMENT_TARGET = 10.9; + MODULEMAP_FILE = "$(SRCROOT)/CapstoneFramework/module.modulemap"; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_BUNDLE_IDENTIFIER = "com.felixcloutier.$(PRODUCT_NAME:rfc1034identifier)"; + PRODUCT_NAME = Capstone; + SDKROOT = macosx; + SKIP_INSTALL = YES; + VERSIONING_SYSTEM = "apple-generic"; + VERSION_INFO_PREFIX = ""; + }; + name = Debug; + }; + DC474F7C19DE6F3C00BCA449 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = YES; + CURRENT_PROJECT_VERSION = 3.0; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + DEFINES_MODULE = YES; + DYLIB_COMPATIBILITY_VERSION = 1; + DYLIB_CURRENT_VERSION = 1; + DYLIB_INSTALL_NAME_BASE = "@rpath"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + FRAMEWORK_VERSION = A; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "CAPSTONE_SHARED=1", + "$(inherited)", + ); + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + INFOPLIST_FILE = CapstoneFramework/Info.plist; + INSTALL_PATH = "@rpath"; + LD_RUNPATH_SEARCH_PATHS = "$(inherited) @executable_path/../Frameworks @loader_path/Frameworks"; + MACOSX_DEPLOYMENT_TARGET = 10.9; + MODULEMAP_FILE = "$(SRCROOT)/CapstoneFramework/module.modulemap"; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_BUNDLE_IDENTIFIER = "com.felixcloutier.$(PRODUCT_NAME:rfc1034identifier)"; + PRODUCT_NAME = Capstone; + SDKROOT = macosx; + SKIP_INSTALL = YES; + VERSIONING_SYSTEM = "apple-generic"; + VERSION_INFO_PREFIX = ""; + }; + name = Release; + }; + DC5BFF4419EE544E008CA585 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DC5BFF4519EE544E008CA585 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DCA3579B1BC2C0930094BB3F /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + DEBUG_INFORMATION_FORMAT = dwarf; + ENABLE_STRICT_OBJC_MSGSEND = YES; + ENABLE_TESTABILITY = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_NO_COMMON_BLOCKS = YES; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "DEBUG=1", + "$(inherited)", + ); + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = "$(SRCROOT)/../include"; + MACOSX_DEPLOYMENT_TARGET = 10.10; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Debug; + }; + DCA3579C1BC2C0930094BB3F /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COPY_PHASE_STRIP = NO; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_NO_COMMON_BLOCKS = YES; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = "$(SRCROOT)/../include"; + MACOSX_DEPLOYMENT_TARGET = 10.10; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = "$(TARGET_NAME)"; + SDKROOT = macosx; + }; + name = Release; + }; + DCFE239E19DDCB4900EF8EA9 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + CLANG_WARN_BLOCK_CAPTURE_AUTORELEASING = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_COMMA = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INFINITE_RECURSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_NON_LITERAL_NULL_CONVERSION = YES; + CLANG_WARN_OBJC_LITERAL_CONVERSION = YES; + CLANG_WARN_RANGE_LOOP_ANALYSIS = YES; + CLANG_WARN_STRICT_PROTOTYPES = YES; + CLANG_WARN_SUSPICIOUS_MOVE = YES; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + ENABLE_STRICT_OBJC_MSGSEND = YES; + ENABLE_TESTABILITY = YES; + GCC_NO_COMMON_BLOCKS = YES; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + ONLY_ACTIVE_ARCH = YES; + }; + name = Debug; + }; + DCFE239F19DDCB4900EF8EA9 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + CLANG_WARN_BLOCK_CAPTURE_AUTORELEASING = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_COMMA = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INFINITE_RECURSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_NON_LITERAL_NULL_CONVERSION = YES; + CLANG_WARN_OBJC_LITERAL_CONVERSION = YES; + CLANG_WARN_RANGE_LOOP_ANALYSIS = YES; + CLANG_WARN_STRICT_PROTOTYPES = YES; + CLANG_WARN_SUSPICIOUS_MOVE = YES; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + ENABLE_STRICT_OBJC_MSGSEND = YES; + GCC_NO_COMMON_BLOCKS = YES; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + }; + name = Release; + }; + DCFE23BF19DDCC2D00EF8EA9 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + EXECUTABLE_PREFIX = lib; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = capstone; + SDKROOT = macosx; + }; + name = Debug; + }; + DCFE23C019DDCC2D00EF8EA9 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + EXECUTABLE_PREFIX = lib; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "$(inherited)", + ); + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = capstone; + SDKROOT = macosx; + }; + name = Release; + }; + DCFE23CF19DDCC9500EF8EA9 /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = NO; + DYLIB_COMPATIBILITY_VERSION = 1; + DYLIB_CURRENT_VERSION = 1; + ENABLE_STRICT_OBJC_MSGSEND = YES; + EXECUTABLE_PREFIX = lib; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_DYNAMIC_NO_PIC = NO; + GCC_OPTIMIZATION_LEVEL = 0; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "CAPSTONE_SHARED=1", + "DEBUG=1", + "$(inherited)", + ); + GCC_SYMBOLS_PRIVATE_EXTERN = NO; + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = YES; + ONLY_ACTIVE_ARCH = YES; + PRODUCT_NAME = capstone; + SDKROOT = macosx; + }; + name = Debug; + }; + DCFE23D019DDCC9500EF8EA9 /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + ALWAYS_SEARCH_USER_PATHS = NO; + CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x"; + CLANG_CXX_LIBRARY = "libc++"; + CLANG_ENABLE_MODULES = YES; + CLANG_ENABLE_OBJC_ARC = YES; + CLANG_WARN_BOOL_CONVERSION = YES; + CLANG_WARN_CONSTANT_CONVERSION = YES; + CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; + CLANG_WARN_EMPTY_BODY = YES; + CLANG_WARN_ENUM_CONVERSION = YES; + CLANG_WARN_INT_CONVERSION = YES; + CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; + CLANG_WARN_UNREACHABLE_CODE = YES; + CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; + COMBINE_HIDPI_IMAGES = YES; + COPY_PHASE_STRIP = YES; + DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; + DYLIB_COMPATIBILITY_VERSION = 1; + DYLIB_CURRENT_VERSION = 1; + ENABLE_NS_ASSERTIONS = NO; + ENABLE_STRICT_OBJC_MSGSEND = YES; + EXECUTABLE_PREFIX = lib; + GCC_C_LANGUAGE_STANDARD = gnu99; + GCC_PREPROCESSOR_DEFINITIONS = ( + "CAPSTONE_HAS_ARM=1", + "CAPSTONE_HAS_ARM64=1", + "CAPSTONE_HAS_M68K=1", + "CAPSTONE_HAS_MIPS=1", + "CAPSTONE_HAS_POWERPC=1", + "CAPSTONE_HAS_SPARC=1", + "CAPSTONE_HAS_SYSZ=1", + "CAPSTONE_HAS_X86=1", + "CAPSTONE_HAS_XCORE=1", + "CAPSTONE_USE_SYS_DYN_MEM=1", + "CAPSTONE_SHARED=1", + "$(inherited)", + ); + GCC_WARN_64_TO_32_BIT_CONVERSION = YES; + GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; + GCC_WARN_UNDECLARED_SELECTOR = YES; + GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; + GCC_WARN_UNUSED_FUNCTION = YES; + GCC_WARN_UNUSED_VARIABLE = YES; + HEADER_SEARCH_PATHS = ( + "$(inherited)", + /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include, + "$(SRCROOT)/../include", + ); + MACOSX_DEPLOYMENT_TARGET = 10.9; + MTL_ENABLE_DEBUG_INFO = NO; + PRODUCT_NAME = capstone; + SDKROOT = macosx; + }; + name = Release; + }; +/* End XCBuildConfiguration section */ + +/* Begin XCConfigurationList section */ + DC3A28DF1AF29BEB00FC9913 /* Build configuration list for PBXNativeTarget "test_customized_mnem" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC3A28E01AF29BEB00FC9913 /* Debug */, + DC3A28E11AF29BEB00FC9913 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474E6A19DDEA5F00BCA449 /* Build configuration list for PBXNativeTarget "test" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474E6819DDEA5F00BCA449 /* Debug */, + DC474E6919DDEA5F00BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474E8A19DDEAA200BCA449 /* Build configuration list for PBXNativeTarget "test_arm" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474E8B19DDEAA200BCA449 /* Debug */, + DC474E8C19DDEAA200BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474E9519DDEAA700BCA449 /* Build configuration list for PBXNativeTarget "test_detail" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474E9619DDEAA700BCA449 /* Debug */, + DC474E9719DDEAA700BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EA019DDEAAC00BCA449 /* Build configuration list for PBXNativeTarget "test_mips" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EA119DDEAAC00BCA449 /* Debug */, + DC474EA219DDEAAC00BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EAB19DDEAB000BCA449 /* Build configuration list for PBXNativeTarget "test_ppc" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EAC19DDEAB000BCA449 /* Debug */, + DC474EAD19DDEAB000BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EB619DDEAB700BCA449 /* Build configuration list for PBXNativeTarget "test_skipdata" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EB719DDEAB700BCA449 /* Debug */, + DC474EB819DDEAB700BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EC119DDEABC00BCA449 /* Build configuration list for PBXNativeTarget "test_sparc" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EC219DDEABC00BCA449 /* Debug */, + DC474EC319DDEABC00BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474ECC19DDEAC100BCA449 /* Build configuration list for PBXNativeTarget "test_systemz" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474ECD19DDEAC100BCA449 /* Debug */, + DC474ECE19DDEAC100BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474ED719DDEAC600BCA449 /* Build configuration list for PBXNativeTarget "test_x86" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474ED819DDEAC600BCA449 /* Debug */, + DC474ED919DDEAC600BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EE219DDEACC00BCA449 /* Build configuration list for PBXNativeTarget "test_xcore" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EE319DDEACC00BCA449 /* Debug */, + DC474EE419DDEACC00BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474EEE19DDEAE400BCA449 /* Build configuration list for PBXNativeTarget "test_arm64" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474EEF19DDEAE400BCA449 /* Debug */, + DC474EF019DDEAE400BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC474F7F19DE6F3C00BCA449 /* Build configuration list for PBXNativeTarget "CapstoneFramework" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC474F7B19DE6F3C00BCA449 /* Debug */, + DC474F7C19DE6F3C00BCA449 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DC5BFF4619EE544E008CA585 /* Build configuration list for PBXNativeTarget "test_iter" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DC5BFF4419EE544E008CA585 /* Debug */, + DC5BFF4519EE544E008CA585 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DCA3579A1BC2C0930094BB3F /* Build configuration list for PBXNativeTarget "test_m68k" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DCA3579B1BC2C0930094BB3F /* Debug */, + DCA3579C1BC2C0930094BB3F /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DCFE239D19DDCB4900EF8EA9 /* Build configuration list for PBXProject "Capstone" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DCFE239E19DDCB4900EF8EA9 /* Debug */, + DCFE239F19DDCB4900EF8EA9 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DCFE23BE19DDCC2D00EF8EA9 /* Build configuration list for PBXNativeTarget "CapstoneStatic" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DCFE23BF19DDCC2D00EF8EA9 /* Debug */, + DCFE23C019DDCC2D00EF8EA9 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + DCFE23CE19DDCC9500EF8EA9 /* Build configuration list for PBXNativeTarget "CapstoneDynamic" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + DCFE23CF19DDCC9500EF8EA9 /* Debug */, + DCFE23D019DDCC9500EF8EA9 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; +/* End XCConfigurationList section */ + }; + rootObject = DCFE239A19DDCB4900EF8EA9 /* Project object */; +} diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata new file mode 100644 index 0000000..e42776d --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata @@ -0,0 +1,7 @@ + + + + + diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Dynamic Library.xcscheme b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Dynamic Library.xcscheme new file mode 100644 index 0000000..1770b38 --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Dynamic Library.xcscheme @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Framework.xcscheme b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Framework.xcscheme new file mode 100644 index 0000000..77d6c56 --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Framework.xcscheme @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Static Library.xcscheme b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Static Library.xcscheme new file mode 100644 index 0000000..8d7dee6 --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Static Library.xcscheme @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Tests.xcscheme b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Tests.xcscheme new file mode 100644 index 0000000..6465ef7 --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/Capstone.xcodeproj/xcshareddata/xcschemes/Tests.xcscheme @@ -0,0 +1,259 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/white_patch_detect/capstone-master/xcode/CapstoneFramework/Info.plist b/white_patch_detect/capstone-master/xcode/CapstoneFramework/Info.plist new file mode 100644 index 0000000..d3de8ee --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/CapstoneFramework/Info.plist @@ -0,0 +1,26 @@ + + + + + CFBundleDevelopmentRegion + en + CFBundleExecutable + $(EXECUTABLE_NAME) + CFBundleIdentifier + $(PRODUCT_BUNDLE_IDENTIFIER) + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + $(PRODUCT_NAME) + CFBundlePackageType + FMWK + CFBundleShortVersionString + 1.0 + CFBundleSignature + ???? + CFBundleVersion + $(CURRENT_PROJECT_VERSION) + NSPrincipalClass + + + diff --git a/white_patch_detect/capstone-master/xcode/CapstoneFramework/module.modulemap b/white_patch_detect/capstone-master/xcode/CapstoneFramework/module.modulemap new file mode 100644 index 0000000..b6f231b --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/CapstoneFramework/module.modulemap @@ -0,0 +1,4 @@ +module capstone { + header "Headers/capstone.h" + export * +} diff --git a/white_patch_detect/capstone-master/xcode/README.md b/white_patch_detect/capstone-master/xcode/README.md new file mode 100644 index 0000000..7c5295e --- /dev/null +++ b/white_patch_detect/capstone-master/xcode/README.md @@ -0,0 +1,26 @@ +Xcode Project for Capstone +================================================================================ + +The *Capstone.xcodeproj* project is an Xcode project that mimicks the Visual +Studio solution for Capstone. It embeds nicely into Xcode workspaces. It has 13 +targets, two of which are the most likely to be of interest: + +* CapstoneStatic, producing `libcapstone.a`, Capstone as a static library; +* CapstoneDynamic, producing `libcapstone.dylib`, Capstone as a shared library; +* test, test_arm, test_arm64, test_detail, test_mips, test_ppc, test_skipdata, + test_sparc, test_systemz, test_xcore, testing all the things. + +The project is configured to include all targets and use the system +implementations of `malloc`, `calloc`, `realloc`, `free` and `vsnprintf`. This +can be modified by editing the *Preprocessor Macros* build setting of either +CapstoneStatic or CapstoneDynamic, whichever you plan to use. These settings are +all at the target level: no specific overrides were used at the project level. + +### A Word of Warning: Static vs. Shared Library + +There is a bug in how Xcode handles static libraries and dynamic libraries of +the same name. Currently, if you integrate the Capstone project in a workspace +and both the static *and* the dynamic libraries are built, if you try to link +against either, you will *always* link against the dynamic one. To work around +this issue, you can avoid building the dynamic library if you don't plan to use +it, or you could change the *Product Name* build setting of either. \ No newline at end of file diff --git a/white_patch_detect/libs/capstone64.lib b/white_patch_detect/libs/capstone64.lib new file mode 100644 index 0000000000000000000000000000000000000000..3e175ae0a67832897ae538ac33b6a04107c99776 GIT binary patch literal 14395262 zcmeFaO^9sYyWe#NPK=SLAc|3l@E@2s@N`vob+<&%uDxr&zw-azTrMGUtnRKpr+=sV zRhKmYE#-=F{XzZxk^kYpd}qIZ@SphIven0%W zfA{ZsXTSb`x&7<@4gbLJzB~Sob8w`ABMlsB;79{U8aUFxkp_-5aHN4F4IF9UNCQV2 zIMTq8297jvq=6$19BJT414kM-(!h}hjx=zjfg=qZY2Zi$M;bWNz>x-yG;pMWBMlsB z;79|9H1IqB!ax4*Z`SY6WRrLHyZPgP(fw9G+`c>hj&pFNfg=qZY2a^+20s0j?%nZs zoP#3`9BJT414kNo`01Z|XTPu2uiS6*ul%KV$KP=djx=zjfg=qZY2Zi$M;bWNz>x-y zG;pMWBMlsB;79{U8aUFxkp_-5@OK6c{P^Ged+(0F;~X4m;79{U8aUFx?^hc5m;UcR z{my>>@*n-?et+)I{P}ms-*FC(G;pMWBMlsB;79{U8aUFxkp}*t(ZKKikN?-ZzZ-x5 z>i_x2-r4V8{}29z`~4gL>p%PM_&d(Qkp_-5aHN61b7IMTq8297jvq=CQvH1O~IM}P9&@pqhqBMtoiq=A3`5C8T%{rzYE{eSY# ze*gI&eLen;b8w`ABMlsB;79|1;A!B$xcz_M9e>9;IMTq8297jvq=CN?8u+jO$bb6I ze*fKH`pd`PaSo0&aHN4F4IF9UNCQV2IMTq8297k~X<)h8d|Z9I+djYB|L@}6_2bLK z^T(&h?cMX;>+0Z7inkxP4^NxBhv!@O|L4uk%hS8No5{oSe)aC|Vf*m$_U_^4o&7nv zyLtEF!^b50_#vN%a1kwfJq{i?g_DhrDl7SMR&hWYK2xp`rBh zyRxd!ns_MNUH`Q=XLXvzML$rs8-te4(zc$bNj8_h2IWJ%=(8keW~}yiU!Dz%qDdC> zdN-Q&+K=ZvuhKkAD`sd{FDNbAwoUVTY#GGvoimve~KoyG?$* z`UE+zHpzOq-F~EF&r3-1oi8XKZXaFm!$*g2d|ExX%jfIQcMqR_^YXOX(C#n1!c+I5 zUnu&`%hgz?r}pyU#(np0+dnaK=hdFO%;L06s(JmkQ{PYgPQ4hC zEKSRbz4rdY*|-^26EdYO{5pzFIy1xLWbe>wUc}j)u0Mmz=o2cQ@%h zByn-GeBRd^qGG;SbV-^;eI3$EJ<`g@kL$jt z{djY?U2gCF{}7<$50+$Of3ia#9_>H3o0Y5fY4iB<^wESOdkTYn_~;((|9UIBU#{ti zJ!V6Fq)YPGTVqxdz6a-hd-3s!a}N>Dn&AJ)Vq*^g!Gh12v-)8k`-y{1!joiFF z|8c`mc7JR?F0ZdwTQ?6|&VS=RR%bj=3>9dlN9PN%07`E+^Sr3yX!TVdR*Sr>;w0Ki^)jimxSN;J z)!M&VmStDB$voP;_YbQWR@>!qv^nt)>ji@x`bD&v`iD*3G;Loe(PknK+cvM}c@y0| z$iu$O*o9Xz@)mJ&Q8V(*xqq+gyJFtdd9<1Nhke_}d6lHm=F~qNvZ2n(Jc~A-txV%Z z-WMGbK620g)oI)h)lkmch$F*4P0FULVmiP5>}O<}^a#hpP(|Nl<)&#}S4rRJ(bdM2 z*fee8bQt13`XUoO%@)m&%)2)FvhveE&C<47*ui(Tlos;1=NvD}=wbEA_bgv5vaVU= z(e?Ug|FlS&p(xsl1zgJ0Zk}azK93M@{L^yYH+@=V(fZ~`dD@m4nobwpzsQKIxE$J~ zNmwswp-P)#KIbIcK1&OAQuI}g27n0T+pUv!Ubgcg+P+-L)3hqOco?F`7k#&BQW$s= zt+z4{h(8&#GpE0Pw@&L}DEnklMyr)4`DvR}L$YAjx3W8?kVpZI*1Rk2wnLY-6=(nI zMxH`qEz8;PuJo*{>T14dqlZU%*e|j?Td?rkXU{RFeU>LfT(fOX{Jxp?Wz&`=q_Y*C zG40zD)v;$Hx1JSDhqkENIXq``;x`#j2P8p6w(Vzqx9fZKvXm*??x*)Ojtc}$B#fK8 zS3kDXc#-DSqMAovHZr(VwseYM;HKTL(P^^iV)l%6`PuK*(?x+Aw}7bDN-3u)`g2^D z1C;XQiQ+UZP|$}(Y(0?x!t z7D>uz$gj#N+aS%*RO!gIKCUyy(=2#=r;nSWsMEfVt~b|y5l^c)&gW@Lw}Y9g=ts_x zZ&TuF@wDP;k<>->^Xi+lUDbUa&pYTNcwEPAT{erkHS+35S*OK3ubMX6tnOva>awld zp(>)avaQp)%A2-<53g@7^zEvuiVBtwACR6jc@rl|(%1~jQZjaI8*xJ;OV5r@o1rbc z5;1D2q;}d4Y0(GLyGpW(<-c2zph`?!QpZM;Uo+Z?8Ol0`qf+{-7i z%had@wGCd#WGEN&riES7K~Gd?aUK_OTlUtrY#b~u^&*cs!Pf!ZpT+eeYZgqc2|IpT z&K7Z3=WVj!{gavh?AfAR)ZKubyn48igX(Ni#aY~NaNi@m==)uRg$R2SQ=t7x9)$yz)zZmL~HC&Kz6+pQJx&QY?lAdkA`wQ{yb zW_Pm`57^~J6>&<=rYzF zs~FQf3WY99!=aEO^x6B*LJm!nlxf$n!I?E#mNxC?6$cbV9<tV)^; zDH3tl`YIKwGMN`9bQ(!)J(_w z2$G$i+p|8UCC-Skx1PRceVxWIgktQKpYqwzwP~5f*;qph`Z6txGLLS;0iI(T$l92r zjH7m|t9>4qkZa4?Y?HXY_H=n3cV*FV3b>LVg^5?P_TxC|(W!D{LOgEv zkI~kOuIaLcd;CFEE;tzl?P&bkzduc((7bKTzMpkw7xP8k0;d47)mSw3JLD|Q^Kwyg z&{&0=r=SOCC8|hPn8lmI?LlGHWC$Uc6s+)R8`kWaW|+?xg)6)cYtB$X`#i@4?>ai= ztJ>Ka$7GUTjjv!c&Za}Q8DU2nq5eYcpiE@Qu-nxNM+ zl$oR+7UTMSm_A*Hm4~$N6OQ*?+f0b-*xTx3oZxiXEU(}6bi6^hgv{xKd1HKQXWhql z^g9=`P_^gpL&ZKp{KlXa{orNR349tRICRkuUJaV0FmrC;Eg`)u|QQd=ej)1lDO%NEsKCY$vRkmfjaPmmyITQ zifD;k5M6o6Xp)y@QJbIWP9N4S?v$Qk>cb&Ts;p?DA3PVBlyh`_);xN>-xE9!5w#Y` zA4|`DCS`)KnpG&QUg?;Wi@YchN|02fI!2N_W-Hz3L!{BP<<9##!{7u+`b^4?dk ziwav?v505cW%Aqae_fMt<$ED zZa&MKMqxRtxzvX_%Ksc6+857%CVk#kotYr6^i511SQ{E-8sFy7WCLDGW=Xz|l>srZ z!+?&e&@)*i4b;Q}#rIWyMqUG)7@7 zVorqHC%-P!WIm*6fj!{m#*@V~$=i9(L42(ypQOmqGBIjwh0>=L8 z&(3H;KZb5M*t^?1PuJ6=s(GC*;9c`WOX_)x_>f0GJb22UqF}*si-dFdLf{11~S|{M3NaU-Hd~LCq_XVdmL-Pml6eB~LF~`_Zg`5_2 zVS%uOc~qa~Y^Ma9-0hR!5Yt88!n0ZTSMfhj7d1R$!5-f}NqKW3--JjaHZp=CcwAMynA09=c9{W(2l#@hl7UaghXvy z&>zh_wYQmv+b7{UMU6qE=!^~c6J}a8eVp_uh8#J^rv+zYf%!LD$!Ro&Zz7ap%wNfA zHZ6u2GjY3M9)xz#-BWl8J5vt1X^9UwM%#>T*Rrq5m?NGu2@|65fikb>^8tIrjq=_S zC7t>i?gSi9)vtI#AGHO^La$&GFyyrW6BFxGkV)l(EIa|XnvrCp(4XkP(0USL7G-52~aRS+j>c7TD1x8ii&oh zgQr;;5o@LuoUR`q$4q1gZs++*zE&?V z?jwUS53(=nVvg>BP3QVYSvS@aV+^eR>PMON8dG0ca*VBX2h<&_(Xwtg%GK*0%UgwN zb*((Pna3!%NN4x=La9twAJR+W3%u}xFM68YNIz05C9F^h8&Zm)zJL8isr{4dL;tY(|1n1B&!Z=YT~ z{kBL6IAChNCdW`)afnqM=Qqlg+qP&BDUj12L^NyL3a4Pp7Ltx(>>6qWIW~ZhPG@`D z7|ah3!lJr4MzC^#$?4J3ak^$^^1sqUvqP*$gh>$AwS{z;W1Eh)pM*xbg7ad*tD6&< zM~uF3vnq|Al+Sk6fW(je^@l5M*0kNKh|$UPY0Ify^7Q&j&YP}-btXuMw_@>{;^V;7 z3GckW7b@!pc2x$K{NamW%B{57w$KTaBRsChu7c^>Xip{`hy*SUZ0Kvz z?WR2rJwza69Tfz7oUwQc7@P7URBYTBI4ajFB_rm?oOxKMMZ28ZxzG7HL~Bt*d76Qx zL#+AXL1?jJ z`p!D&L(>%lrhC>+&XA$Sris@zy1f^kJmBq2d-Qa$9{Zl1#&h&FtoG4*edA?nJY+qR zHf}!5iT=dFLq^lMsO@`xAg6JPT^KDs`uYCe^CKR2m^T-(^}|mmk8xCE`DB11u%E_R z&h~_ZKHaSRqMpWOo`9C3k#E9hPU&01Aeph=XUNkw!V#ipX4e2s-Hj0qM{OO|N z)Qw^4IP3N88cSFLH)4ss7I3=g>U!wAEczBW)DTOCI>lMX#CnEwia|IlK-EUK*N>iC zpQdOy2K>dSv+|so$34gl(0aGmpY`nwb6{h}4dvsfX+GetVl5E?WQlRj7obj%@YhPn zDd#=sQ4{@ifA6)e)3hCWgwrDW;rg4`YEDy3d92Noq8d)KMY}+;sjUeiV;rLZU-01F zs*nCO%P^C~Jic0A%i3gZiJ=9;WHA0jIL$iLiaB~CGZH*Da|sT4wt|-pPeErRopOY& zm2sXj8!bje81f3MC^r2!i}5KQ>SBRo7q+wXT!Y7am9xQkpL{h34p`Ai_LP`UPO)Vn zYT$f)df9rb%Bj5^FFI7y$BpNpJT9>*4D;wt4H&2RnTp=*vy4cnEyp}x&cPY2ALU3q z&2jXau@?x>lfK>Ksla9Cy4e^uyzPjtkJH{JqS{0ElRgyYPDbNfxMp z(O}~-ZvNTZ7EX&KW0bX-29&@HT;-V|L2ohd`?ia;!TQ5-2MSBJLy_lj8ry2ym1oHK z+;O5~Te8jLB`6-(c+No1)9>JI{5aKsu_vJ90u+)REijazgS9z_5yM{fBs(p@=b#E3 z?-jtxDKZ}hA5#`jPNXNL!Rbo?9891-PUbPYeqkFzI#?z}8@D(Jp>Ta0C2|0b5`B5p zIVl$nJ_-XHolNy@X0Vxa3ZOa*Rh8K4@_BFYkW+mdCmistUC=aKmFj7 z>wu~t1`Y>2V|36{C2Bq`zgr13>69M z-Luj+URUS@OVT=^6O76=6Q0;w$|gaoZaN4SI^KBl27}S18K?@nE$2K69Oo+v1_lUy zjJFcw9$WrJ3{s~sunM8u@Ey-y4mkyRR^l#XG{G^7pPMrfC>2v8{R2DJ)_AF{+cHy# z@)Z!cIWr}m?$a7XUdNHfh7y6J!Iy*wE4DU-9GW>!TpBT&l06JC4e##YYyH{1X;+Iw%abDN3xw_}}0I`gYmng`M)OyG~#^ z)L@-Z#>069?}29-T;BbitWATw-nVSZZ{R~bO*I2z2>18TMRrk#}vCyZ0V;hR!5|^+}f6Y+qB}H0>}FJB&?ouGG5Ht+1P|cCLrJl zu@5C^8;E^vR(3tYw+&wVoq?0UD`Hcnj|_ZL%sO-KSGmIg3v?kdTK=k!aWsD@;C>S zjzFjoj?)gCCh9MSmy?s=ZDfKuvxUGR%ZV~Eudx@f5F+?>1(tyU5rX}oZ4@0&2y7Xw zy(}AW6lP^8jDUo*;Wo?hbD^pPk_GPb8mn(&pA=rjW7IKhVUY4x#@^v4$NL6sPvLJJ z2OVy8n89b|nmu|cU`m6kiWU8|N5x>K^5`}Y%lm`?f(Gm#(=DUy7e$Hyp78dS^u)O} zYYeiiunfM(D!pjf-bk|gc9!)Vb-+FD6?BI8oo&ox7G9>RuP_6q44xSjdgyUQVrD|D z+TK0*Ie|aSOB0j=EY2x1V%sgS?=i8$QTo1~gV96T3uNkHp3K3%!f1m1FyNo5!O7S% z2;ao@gQm;5xD7O29;0VK5C((s9Rwc+f)|cLBTvEOqEF)3Iw*T&z|dV{o}+L5@XJN$v~}CXxt-;vcYgdoFes$4Ht0 zXQNv~z3o5B^Byc5IsW+JvNuCotX~6g=$lnt> z&p~dP3zTINQxMM`2yAYnTKfaeo>y_pux?*e#5#*v5OCwP|M(QlLdzl4W4N(?>UTTL zN(oSqFOZEs?=k$ryls}ZI?Fu_))pjJ1q>7i!_$idV(|XZ#0}ad_5cx2&Irm$8`uDIDOM7DTmh1YE>U#7Gkl!Wm%S7AXlJVJU{?mSHW(i|(eEPI)u=y?`1O5E+!XkWngCdJz`)o0X z1`BY$Hb4G6<2go8^FG_=@&^OBV4NLT&Mam@P&%iO1Se@?0#cwCI7A*?ej{3#?w?Wvri5Z3oW{pb>1Y^hfB5SAk7)QbC8}!8uzX zprAW+hR+S&$A*rf2j2Ds&RY7PgN5Q?cm34%8;p&FB}K%DinaF)RS zNSL8-Zj_TO2Ee3Af};NPyz~bUAZV-xRmOo2qY~BtA8h8fd2O=@F{F6+%uVBnS%@da z+>ig!!94Z5#1YIvKmvz_g9-8D^92=Y95Oie&k*0RPvQVK4y^BYIo2xr^ZfI*1i|pW z$qC4wMpRx-;CYjD4bP1;Yd;D6F~P!Z7JYwM81BEf^I3@mNHE77pmLM#gLXQ6v&@@q z7Fn!pJ_oapDGaSs7d=Z-9F+hOc&_t<0kbj}x(SNcGS5H>0O9h!5l`?OECPJnjn^OF zXP5~Aj^XRT?j?KO@C0DlFnrM+*;^SjNK{$;WJSxdg}7+l*LF(O zPxL#Zw%{@85zKM&Wbj%~nnZ(vq5*I)1q-aBg45#Ns-hn^_acs-Wi|gSUdKR-GW!|9 z7&y_PDz=2S0|*xwHyR|Y);ko=EJ6h<0Z#je>$UcC01$)S%~`c%6@iR4Fn(xi;^jjC z_a%NuT%5KhLYtuHL8qF%dGbw^v@^gy9lq?=wc|A@o@1Qm*u7mZ#Rmm$pPe!X>|#=> z@OO-Tgn!pg1rjU7S)TVPP;<^9T;(Tzl2NUT-uO7}=s5v~aSl~sOvHpIlZk4Co{u@m zCR2u0%oL(!Cb8OzXi@NxAqL})BYhz;ej@FlwGV(bZMj}Q zNjFQ-dx)vd_&pI$NMt%V9l{HYe1!TzeX-@RW7%=3?*qTa*2Xj-{>gN*Se!#}NSg+2 z2f-WF!NqZCxD2=kV(Zw`MsC8wV6(*hS+FYlxR5PMEd~al=TEGnjtd2Z{fK*kWs#Gv z?2*GN$mBL~teuquj_n@B=K+=>vUEi>9zh<6F^D~~y-Zb43BGmx6kbx5_>XJWadY!5 zAroi#FEZjUF!0_#>AF`$cMTk|#`&MTXtY&`z+8% z#GB{G@ck-BSp>d!zj={)z;N58magYD@ZX&=Bvc9@OeR*zkpOZH-7@VRJxo1)R$UJ> zvy)OOJ4&>w(DBAn?N1yB#M96UKk!iygk&Px2ipk{bom#Ze^CP!|I z)}a7WBiv(_&Rp{{4K-O8oT2pTZgMN+3H$-^-tbtoukRB(4h5lw(0zTMlO-Vr+)a-@ zCz29iqLJa#R<=cr233|IFJ1$$;~9D+3gHm=oDw;kAaBtQ(NOtWes zVCWI2ai!TZ%ArPh7LE@fy0$E`U22RI+2CA;kHNC^V6@CH%x({!Lk{?bF-Oymwm($R z8;%^>SM3UxmzcKg*pJK)ws8`Lf) z3*VFNh2tEM*}^=Ofk~qwSxlXo84NZ#@%?G%7F`U!^_BMJyN;|l;-lBV7kfs29@qnx zupa=tiJ_@oUM&p&*|m0Z(3)ka7+~DS z$#hvj-{K)G-Hz9u0|$UbpeJ+S>5N%4!RV;u1Epn0s$|}XYgi;i8ja&UJt*zToMCv_ zv2=D&I)F<+VcnIUAC?+Q7#DzXGU-n@pLYYYi{nf(OWhpY0){uYg0jPKqYO!pifbHH z4oJX*InapK&8ohiaB9v`^^GIy`zgeX#AgTawaCexS#cai{j`=mRcE+SkQ1Olv%iR( z-vMap<{bQH8V~`cV>cqdAz;C2biDZLF}K6Hx4}t*?|cr;Iy;M=44kLHyiu)9PLOR! z%)o#G;5;pQ!eHcv>`;BN_NhRCya#}Lfj+hUs&UpFFvdFENunnh&lh0tot;SaBeEXk zElROlmlIDpI6o``%AJIIA`yoNhRG1c0SfF419g@p2ppz9iXI1|5uXco%yr<6I3o)P z5w8e3ulL^`MNlJ!1z|=_?8Yk`4pS(=2n`*R)VYc~aEqJkKrrn|kP>%DDAvBd-=p1` zGHxf2*b|Y)a^}-AjNE(`iL56C1c(G+lIuW#X3LV|46C;FQ`!eHZ{7)00A9ADNbokU zbv^stvlFcIsp{|?!i20Y(U!w@^w>`wA8{71=1@EH5y;+=iTVMm`(PWWM24H&0^}U}{1u zr2t+X6c`z}+z4BVx|xBi%FTpxYkSb2xw9BN7cgWZjaFL?(;*U%ox4b9e?^rQiUMo|vc?nLtnr*kv(8Z9l)<%D$Z?F&a9Ek#VB5hD8+;uuoF~ zr=1adjJ5_WhCwI`m?7WeJ9o+st0&`2kQ!k>NVoQJPlYogXAoY1Ul?_MlNn5~Sk?n( z688mT5bf&e+0%2<;yS{X%4!5>?JVi$oIH*Y0_z6_q^80bK9Y`pqZ=|jCp2ZGqXp=l z2n@F3>qoKM%}6C=36nS{NilHsD!m$TUzp9>5wtGg&@DQ1OPXU(OrA5)v3Sfd$*}ju zRW!r(llB?NV+2`4dQniIa&r*9lKEA48KJoFTEdE76&70*3;POF4QgQXFk3srcu~=M20JpyhI=mIT{F-Sp!?x$){?MQ3Wk>8a!%jJ z*9VEIoRRg;f`wor_HCWQe!yPM0p^<00xiEJS)OiCPoCQSrV*o;7S$PF`&?EqN}3zh_fZJUhM&`%J%v?wu; zzlL%W*{FLQsaP;vZ?!2fSI|02kBu)VAk7-USt5S}QEXMLOoz4|b zG#C;{Hn;b+DaZ;GK0q3)A=HEMhOkfM0g&uxqF&F4X({>|db0ylARseCFSVA9&~YT8 zbxv^0aX^77$--EXDr3T(Y}*8q;*8(~gBjzPx6Q9jVIM^pf{#$}Sqo?e44W}GKBC{i z7rUsN@VN1*E)4F_5`$2-IRm;0-Fl*pkSYJjc@BayZ%MxcPAIH!b@WcM!YTjaR#3N6Zy9gnWoQB~J~ZFOFSl0gs7|1PN!vAmqaWLOnndUqh_V zj08O`0LgJVq@@y+0_h9kxibYA`7&s93V2Id@99Ke9(776VpiUO;VV*|m zF1cE9G2{Aqh3o1;WPVTFR2Z{O43u?3-3R$YiXjt|f*NEV0fEXS(v&g=LP>$Z59Ss^ zF3^vg$d!{6&3sq&<8^{I1dhl@>Ii5Mb zZYB^Lpwiaxu#! zl2(;Nm8MKK4hm|b1`sN@UxHkjGoWqkbo{xlyIO;AJ+Kutg$Sj+!pgrO4F|Mq3neuO z(J?)#j6NSsJG0SZy)*+a(=JO3B7j}UuC=DLy983fNt~CNZ^+WtWReB1%h_cg(E_4d z@BNYDp>7RkW6D?|;SB>otKFn~No49uXB91JlV$9knTh-O0X@5ccK1t9V) z1JLscEqNp94BsosqH#C4Nz`7EfV!#iOQ9K~zWEgd6OMR=$PSf!4n7X}i&S64OIv|9 zMKm{|6{BJGNvH%L8d5&7R|er0p!Lk)`!!}Tb2cgbi2}0};5>zkt{y}eBMuJOvZbC_ zJv|(lNstQwUZ5Hna6z?WByaBo0-l6JR-m0Ff9hjW&-A}th)2$SQ?c@gi> z3^ST}13=W_P1UGN0^$$$ zU`u+-7VV!bsAhbVFOWcDZg$RFvJnczZH5&O>l+iYxv_gxqy{N8xw-<$*%+DjiQs=C zHn2=%IF^WmS=*3p2`7ddg+zPLh`S;q4^oudQQA~TiVuWg>y>&dW+Y3;+so`a{!(kOFo8?E20B)RL1&`2_Pk^#jDEW$;JsKeNVaObv@egkz3 zv_6!}@uAzPM=V)%PU>TT@^P{_5kZGu0;j%{D1jNc$qr(`BEG!hvJFpg;OG_$Y@2Rp z%E0l=5FTY9(h#aX<7OxlNZE-R!eeJWf)b`YZZrt;a@%tvP7I7=AUN%8jy4$EfofEx z--dLC*fO^Nw8hUXoi*byXE28yP*tr#mYo5B^;jT>9llcX!eNzgb1US=8Bvp)$4Huk zGblhwv=hR5rQ!-9GDuy7bUPZ+agZee(HV)ss7eZkm<*$Y&)}yIkgp`N#JX?6*H5<( z>ZhEU6BIv6SSH9gETK5?@U+PBff{P=W(w1-6%{4g>3| zs!aj5RmTjJGa=J> z-hMl*lW_MyKA0|wnL!xuxy5+nis_B(AGEf}!OsClaJr>f0nS&?qb-+Hn+7+0GGv$a`hE`RXMiG)A_oEiJYZU#K*pBqh* zBhDe@=zyoPbMAg4fEXdjfn&tkd5%GjAaM-bV+XX3rOmUf47Mj#;yA}3PmVAS(s4nh z4xts~f<=y}P9Vsi8`|Ac(7qlhh!hlakY$`r2TH;D0?Y@-V_Rwy%sr2$1f2&;q$Cvb z&q;?ue%MiV+pGl#bPjhzN;2)yO{m{#t^|pMPP-oHaB}VdGz73k`DrGQbHpJtX2M@r z-<~GA)_9r`&^dAFHPWsu4@P*>*Ej>+%hgLT9)D1<+v3+m$1aub#K_Pv5xcrcz0PZIIx_uEXvk7sY^&HfS@;)NZ)`fkx~mGb6jmL zvG{UOHoG+y3c*uWg3olGEPN_nmp(Tm@O(6eKp?U_m~;^e+-DF$bxBE+nxJpmVHygE z=j>3jkn@?%ft{U_u4@aEdTh&o^5^L}rUzgRaAPOx>MkWs0@@A2M5V8D;QjrR)0Ur3;5Kkv;t|-mYqb=db4H-alA-I>nVMx2kgAou z1(4I|sQ2>yIYv+VFbaEWwW0vl0a#>gOb`|4rRh~fQE^m$UQW(Dxc1xybs@sw@q|8v z(#*3@%mSd60~h9b$-z=v5@Xjhkz&qE(&yN1h0ZP*@Kw}uWJk~iMjQ$+I5%N>!0Jo# zAHX@fp~!F1q08HPnwvq^vqG>#7iHG&-G!NcrrCjZ9e{BtBpH{+32nBXh1$9sYh)pm%^6S@0&;vw8LaNP|!zn6R zC(pTyscH)pnz3*CoeE?ukUqy$R$qe>VrB=9e&g(FRXE2Kh>HZ>1^po~OrKXkYRM}A zTXS`^HPXkCbd|Zje|pv!m~&I~YVcFc4(#(q_6|}sVLY%k?xpxngb#o~TVT2n|DbJAy$a0Cq#Bs!o%5X>; zLM|v1Bpm5zYsMl5JFJaBMD04aOE+3efItaLr>&Wt4>i#wvmjN>gb8}*m=!}s% z{EYSh4`GkoIQC8T0KjaP7{`dpz9Yg%LjX4y^T8@zYe5P3J0bDYnlWTqIr80*8JH_e zOa=`{TElfn;T*jh;6M0|!Qc!$!B*f>Y&rYM07{}S(zcCtbUb*6FgF{>_~3jY>I-H- zcrbn2ELEhncrYyLX7GJ@hOYdYwp_a0wOAh9#*&E0b27nm*E8(kmh**c8Ke&IQt}|~ zs8{)TOP)wf&X&K4Db?A*@Mw-#_MG`XltMW8I+yAV7XNguEFLHkS$|D*K5$f@6DL99 zej=vE{Uel!8J?IycH{URSvgPOvV*ybMvgM7hMobvh#iOonUsjsst2?v7U}=L3JhY#Z-&-_bfG zAjW4&4-TdGu11L@AcB#Cb5Je8g3}0NpukiCAyGW{BuE6j;~G+ z6_%U$M*5IWll+$yF>ukb2QpCN$}lK{aCW;??1<+WQ&8lw3XT*iJAud`GC+@LV0xgf z>vAF%!&Dny&d%8&CwV*t*39B@c{eBY*8ztUN@3;6Cx zQBp$oWdtWi^W@fA_6|x?4?oeeAo2nGvNhnxtapCRo}Mkso8C(x}%1_`l^$I2MzO`gTH?cj(N-EYmw^ojefsqYdAH4 zpcwAwW&NV8ng9^Ep|jdRZo)z@Kx`v98BFQvfy2W0`ob~}kWBcEAq&r;2<$ReYqMJg z0D}uIDQ(ZTJ#$?)19`LSY`K=}1}dpD6uy}(nM04<5GU+KX_qIW4F9FY{7yY_@r@CGUHBdxeLKK>jw(p)#_7cKHOz2(JW+a&(JE(mh;LMI3 zOtcakE0sW(7tU42%x+}~FI*ZyEbUgv1QK^E*4Z_5+Plqw6GTq@;zBQcMa+`LFUCy$5CtD2)OA58IoZP7E@|o z>1R1oDMDJegs#R)K5s;+yjY+wkl+GU%QdJ(vp{(zbv&0#;SWS>kj`_X4ag2l9d}Q< zjDXa@J(FAptNP2s)AbjHc3fEeCng3~($!L;Ny(#Rx25c6Lp1*j(9ghENn5gOP^K5F zR7Fy4w=?3k-ENe& z^aLa6>NF8;fmMgZNyaliac#Y4g;)>CG;IMNo7FA10(*V>f?I)zIwD|ttfe!U5f{Kk ztdR99iozr;B4;Fb*f34&B>^wmU|Iqmaz0S&hY}6&OTrUyR`2$mOreP(^q(aeJFi8= zwL6Ed+b24MNWCDT0OjpEsFlcLOGXF?1Dbr#OH?PlAYlvmD2sV>wRGR1FOgyr&(f|NvLz|%EbsbmSU+lmWN(N2 zLuz9;v{pe3JuYQutFcQd{T?s4&X@boEC$9_D`*hyEF&n{H8{Bldf0F}S&nJ@*5pEo zhA7$|wRyEgLIJr-(b@c+HBq~P69ewb?ZlhI^&;k;{IT|}LubWB z6_ZneYiszH+YmAvpd?AtX!~n4OL-UQMa4`Yy}Yp+S%0#U;~O#?`k}w#f)Lnl4qW4{ z7y2oZ&5=;oMttCxpcZHivlEY`p`Xg_YC-FTqr$ZokqrvX(-!i;XK{hGyun9jJJ~r@ zv=<kObcdiKcE$JctFtB=9%G}Y#^}5m^90-wNr%k9Y;DQ??2~)BXCkab? zETUn}>;QE;Qur5wqPW7AkPLMvt^f)Y_qq3`?!iZ(Av0b2Y z&>pEcF`a_XADNoWpk1QY*yK9#B+xU6;Y^W(ZCGwY3K4>;<(3V&|5!^Gl2AO99c~WU z?QrcOxOX&HCc_C6%Ho@zOLiHqVKMjP6oCpfchkIbQ*}7Z!Wm=oUDQ7HXpwwrwLg=D#8b< zw^}-4=821P;9TRkv=-5FM4;{@JhhKsbf~mo!-!6EdWITSI&Klh-Mr)Qfu>I4GP{}_ z%-%?A(v1#r3_}eG;cpJD0zg6enDgx$msByXGZJ+fIUE<)^#`GkJP9mjM{7dYm;eb7 zuqd6emJFFB?4X0NX|g8U&td1W+qrBuJ2I5c_i<|(d4VF2b?dMD1S1nbeskiEMfxdlYG^KwgPJxWeJ3jiDwzWk8&{KzFBc@wh1SfUKOW=S zp!w31bhH=*;I|7-{v3aTtv~&^pJ?at(2$mZT!M}cbx#sL4!_3P0X;o%qnq}yB{Lz> z_`4!qE_5;CKTS#+ox?hXU(Dyk(5y(j ze9IAlkOoo2prP^DjkUCg#HW&9#+`UJy(-l*-eh4~_jryg0|4>IX=r3Pc0*=kK>8<_ zxY@i-wi1W<1$QHouFI5~kweLB3H_i6Q z2)pB6K#sNB?V$jLV+iQBWoUHs^eO}ZwIds1?x6FbN%)c*vr72dsK*-x_*J>&R#_4= zv&>H;|B}so8DnT7pNj2R$6{rnDI@8O-GE`!NSm@Sm)sv`(VY9`lvwLaEa2Sshf#J{ zPpFZyfsjDU&0x|J!makR$UCyTj79+ao}cDRZkHx4OK+4lYV=yheHR_D4en^!{DgXb z?WgRLl%K%iAO)&9>!FwFFUi`0;%TSL&Me~B?vmUy^A1SRuFdN!kH){`hy!R~sZdSe z3!p8OkE@qWW5_^&%1mM9qo!7TAojA*L|0*S<19BqGWUc`Gw5E8(A=Ay7_W&&B!wFd$6{2C1^7vTD`Y}Y}cmD z3m1pARA;%R)-hIk;ZE8J|5?fOEw>Fh2!G}TWx_L21954ccV^H5M2lRKM z_$ApW7G#tg)h!tKR}Un)Bz+;lZ5*qRiyNT!r2(33qREb`B|GG0-T>PHwCgr4`mqET zTmtYTFSIjt9;&97r0WM|hh5FIod=-EvVPqCf*F?tw&V96br*3gbYwN$E5c$;ytJeU z{M`9(^CBnIC3gt3XHC2|(Ey8wYzHnsAp(@ll#W3L#*0hRJa9oTAlkQjGB3E`NnV8Y z!pR#i>hii|rZJQPJ+*q^IF+u!Lg0bqK7k#qJ}5)r1bATDEfoV})Ft`fN!M)_c1LGy z!MzB631pJcT{B^fWlFn1vB^7bnEY`|2lbkg5Mr`gy6q6PAS^;O%=lcA}(+ zd**w)Hnj}gpruQXPG(nk&lagA{Tw>3uC#M_*H5WuMvihZ!h#MAmY0Y|1Odax-RBgw zeQDX3L4fbXK5{Gxn;>_x84LN`?Zbf^_L6{ZRLPv_9H%;{hyNodr1PzwPMPI7CR32J z7dSR3=OR8UP>^8k3|tTDDyRp#9C$fx+V=vF#wGYn?zSBTUgucTG2nr+I63Ma8k#Rr zg^?Bv&Ts4mPA(+DO|6K-hCSMiU8kB<$AFpe$hx!db1-%S%4-X4a$=s^&@O>y19dhZ z@7ScC05$onas%`1C`mH;UE0Numh#4R(;Onw6%vn;+|JCNw24p_;GjK*+ zl6QE)QOoznddeY5u0d)@+qL7;27Ljr-a047ZW-jz#3IVr&8EBSi%cg`XerDGn?96_ zA44)0T#|s7aEsi;uS18=CEgS>J3^kjeoC7_C5g!~EYa9c6+r+?nn%@S0+Zi0#Ql3m#?uzD5=F{jO3#73C1yVs_wW8981Oy2o?vp#fXn25%i^s8@%U?fwAK) zRPF-Whv;Cl)Q$C&1d(MsRB~It(b=hEZ@DlyH4bTGhw}(cU|B7R+hlEb-_tTM_;!h& zTL*G~Y-Ia2h!Vh-p{3pTwBA6He=qkb(_&FIm}mFQQ&xdHl*x7M0Db11d(iWgGOkcJ;NET*X;He*s^ount&58 zQD})g1GHeAz$ozE_p>9+nj~{}s5pD9QW6L!%uw#UG5z_gcl};c#I`kj?XH?E5n&>@ z@yzWuGA!}_Tw=-Lc2-NW2O}^nk=ElPN6WnVwnWM#xTh6C-$cP(J()5>ipfsmH1<)< zmws}cJ*X>Zr5dMN&M6WxXXGifbJ&Ki$nQ&xb~(0V>&sXs{T#@D!A%c4Mu2Q4Olcq| z5F|ftXv2<3KL;po9OQf^wi`E4L_8kAXFe z9mj?lhj&z=asj1C8dzqGp1yM(Q##lkBV!DmQJacBO$0lblLFOjCA&T9*&(I5=`$8> zVAQ{zyokG!Qt$)Bw>U85i=`eF_DpF-)B}Xzd*zqfN&&Q3EXV8jrzoW`P21x4PCJqP zZ$*}S%REgW8SSI8lPM*XZs7W}eW|b&D{V>0Vu|fs^i|;7q!jlH4nl_q9b488FA{RQ z1DK6oKP{g>uQm$TY$9&H>``(|KA~Ts&_k)+2h^F6{8l$;x#WsOCwki?-yBRbQ8(yg z)Exu1){yj`;+qJRo+a3}@4_x7w@#oAqG z_BCQfZM?!1DMh)$YlbzloOP7H zOypb3o=H+#RJb=yX?$B=-6bSA%NrM4vYRUj8EPWpCsA0?$oAtskp;{N?aK*XqUHOM z*uAZRx+V6!ad~%?ql8168Lme#E3O;RT5U zC}Pab`-uvc-ZDlJ%xz?|nC?xB?fuG=wa}Am8e0p8>StkvGfJu2jxW zzKboAE8>g=T1eiD8oMY(cO?Ff@w&R8TY{DeZbt|oZBte^>@)fOFlDkpySm|b3CAJT z2D92gxjYwNYPsUeWnh@ehF6&To0mpUW=cShtULTbbF2Tkq*8x_z%Dc(Ki*+hwPHUc(C{$WUiJ84{>Lquj1 z4S*WSqD!xK6CF@HfOms6yUgX}XFE8l0F>e|vtTWojnK3~%Y;f1JIHt6TK03*MgRzU zuDvzRK)y{tvs>9n6a!{U?VdAV?5UFC+EUiQI2`JGGCh%Aw+KLWQW7stWv6+64BI9h z3Df0Fp1We%E!5`B!TUDuaD)+R>!%3<3TZ=K%!Lqln0+qiJHeD<4c3pH1`kqP7`Syfd+h{jgVEz;lb+uf~iXZ6FgM~Trm_wABz+xVNg zp80mr^Nc$VkRc#b7ejJLX+|m}fQRqC6$d>hQ4i^j%yF_?5H;|%2q+!iX0vy{)egT6 ze3=YajC)^O2ZjKH^}-a0x7q<2a|JbG8G^BG&Qa>}T(FIR##zGo(VW7#UqUM9_8Ky_ z8|-47mX~lzaR zJiFq6)Czje83L)j6$dL)&~t7=Hc{)Xw$2*qxdC;Uy>;{&21-X8SzZ$GKCIYCYA4g6 zYoyFTi!whL(X$_`-h@&=G%f2yUd8-}t9Lz1kivwi5(Ya14Hhy#(qr|t`!N72@ z)<9{X*GI8Hjmts`B@G4aFF?xqs%3kf|Luo{{srGrQcr zaqYPoe+OVAZd%4OE-1FEOBc->N43U-V(ugAoe=Z1n-;NswGqjbxZ1%4%!Rxtx$p zfyOiU-wujNQ#L1BnV!E5Ea*8}D4q>i>Rat#S_s7_>c|C^zfp_UZjeYot+6C~Qq*r_ z=O?hjB{&}?B^6lP2scg2#aDL7L+K+*!(hY z#lgT@0A_?ajw@yiSwmjw8d;mbfQ(Dxio?e7M1W~^3;LZEj@n@Sx$J3NlCg0m2aL}} zjNyklAK@-)6ry%dVx+lwY8;)jt+`Qn-;GllHLp`c@neGWH!DtHvFE!4lI( zV9&S~!rUJW?33F>N=!talq41($9=n8Z$pMX!~kyr*t*(>W-S^|uwIiR$~PVijBKKP zp6z_auJMCnV)nSM#y1{}8?OeYRZAQ~&kqe>d^-isG3=b_W6zZwz@>B58um~>?w}Z< zgj<5gQ_wXYkRqoHj;NhCe(ZTryTJO0Z0{QnmV`XU1eTbQYCMSoHK~h0P=Ql1wueIz zLJYSk<(5L!ITiQi(mdrY@K191Xnnt?lw&m@k-Y7rxAtY;y9nqYtjo~oyMr|a z4DJDTg9AllyVwuDi_nO;htJZ!??x9`mpde3CT|R!cK+bQ;c*KppO0&%&E09Oxqd6-`4 z4qu{)@;d$u$OxB&jB?{xF0?~^OqBhOY{%&fi}Ru7;uEINHy?Bl{Tm$YxaB|sGW}tF zyUW$Vc*oV91iXmP*F^(;?3T~f4_2QnEM_vc1He%S^~3TGY`Mb%@5^Od(mt?3;;_bT zx$9prJ=}Us#z(Totsd?!-d~)5e0Y4?YeLi~S!+5s|HQuiaC*TM<2)XB=GcBvPEw~7 zot@>`S&subuS2$G27qoVd3x!&i@2nodr@}HkJPQxk3|(zulZVc%Y)XS!y|Tu>kYUQ z)0YR+16yfH)I4f(Mje6H!RLE!qDFMscaP2IW0I_#ur6YcwSDa$&IuCmI^kgNy7AVX z4!fYGIx-;2Zh8Z|0_BiL=8md;d9eJP2JmbPN8FbOiiZv^VxR}b39{st7=vbtIKUHzbY+;PmMq=ppRmj}#)gd5!6Wa^u5Klnbn zCDER{;g9Vr^#S)r?looMZTMmLxtTO4bBC^;cXD=-tqrrw^zDw0gOdl#V!abKcAQf? zhZ&x9{|+9w@4a@8Bzc5inPq9$y93fEc!T*h)6%{?m|QH7+^}iJqkVZWI;_M42`Tpn z7lxEz@{usXlUTX;;Ci{fiy$p>09e@0j&mKz1-K|oW!Zlo#;n6f1;mU^G^kr!JD0+9 znT%z?3;+fD@}T=1JA`8c`S#_(@Ih<>!nSMujCNf6LOVTT0}wZ|PWtW#2Y-)UkjNua zce@6hOcfX{d4a3kFvyHw*u5Y_NluOpfQcZ zau$oXPn@X!+(&kbHN=GbKJbF}feU2@LbBQHZ{&P1OcHr;ak9aj-%jcSf&tP>x)i$r z;^uDqy{ynj7Rm@al0Li-`#``L>Z;M?+bDR!4|9MXT5M^SE7&PdNZX1}jWNHy5sJkF2fy9YZbyT@;U|2E zxWy7LrS%ljbxKJny4o9@ye}jCH0JZS>lCF8*@L`cNkCmnXl*0tN88vD z&S<3#Ar0E-xg!}lGk8Px>452nC_t{k+S`TM1G==l!R@r%I>XBC`*E#45)(TaNCb1 z;2XR_x&iKM)A<+~$M0OsK60z;M-J|Xk9Rlk-u`}k`p6v(xW2|G=3M{yu)JTnKkx4E zS2uUd=hesU-Osy6R^Pv1e{EKuKH^6jYsiC1_=JpatMxBD8edyKUVq_6BUkPk^qsOl z-4~Y|FjHpM-oCSL-`vb!zr}BWEdMA;{QrM#!RvPqpISih{^@U)^2eVBQP4Yt)9!`x z{(kqrU#~vx{`Z^hYTxYdJU;P%dS#PBf1W;0C&8by(|6yPZY$ZYKHaY#p8elh!lj!676VlV5Utr+(Achm}ZZLRr70I21CjdKV2mVaBVwHG1`0*Cmg%B2mvb5+!28~T=Etf6XAZ8joZ`GA3q6T65s3ZE85v~(=VcKJvVWQbo3Bu9 zUvxgFcpXVtf}sqV&c9o9B&yFr?Xyy~t(H&7Iz`E{z=I`AwCf+hfUlW8um?{ks6-hEo@Zw+^_l>Xny>6q*%3PRx-#luA?T4 zbZ!+M{h@M}7laH$*G?Gs?Gum0tzLxeI0vGCUd_35j?fg>{zltJ@9Qma!O1PY0znc3 z@Yw+_fS{rdsxeGb8LPaCtUSgtKKuY0Xy>X79Hy8)W zUI+|gRPy}i2>XRC;D{LQR=xmyL5`%o7;AX)I48V?d~zfX*mdw^7Ifh}Pr2#{Akt1v z+P8RKEPx7GT(1$LRo*V`Ey`8GgYZ~!4wTg9=JpWT0{ zAa8;7HG|Pko%97=N4lmKefq=Y_iK3pe~$agc%XJK*nJn=ibU=o=T&B&>ztD@C+_rH+aIAn_p@Pzbf9z{iHaW4ZFjI zZbW;G!`eK2-^QiIj3KZ<9pl7~WEC`W$;4pC<7m11>3Q|xEaaI)_K;P@E-U&GZtz_x z?vFaLw7}o&M#9zR;nSWhuw0Toi9Lzi3TK{+aQSfls}H}L$M${xGYtHZ*n^-F(F`#$ z{L#hx@So>gL}ZW>2k->u&-dRB-`h9VM5H9ehE4llf2sGB*VyPwX!H4(#tyQOD`@aB zAS?ZHebP-5q?$(GeyJD-50D+MIjW+c?(cv34R@z=Ob34cz1{%22!M>BxkGyTJxCPm z82lJXtc|`Mv}u|~X|n%ELd74ROOjc?2?{4JlwHGDN44Q($eG~|+J&~WzNF~i-j=|7&mKCbNz!j&U`LO2h3%#s1Ba>!s(row!o#9aLkXP1x(NC^FX;@ z8sSh%xpIfu{QqTas7Rm{kY`LEVrkw^{h+H2=1;Rk6OC)y)bIToSzRs0^gCLX8j<4* z^WXX{;T^yEiEQ}yfBNI6_2boYjX?tr@%9W%vN4n0pKbDS{_E)kEq*JHl3&kG4<2O$ zK&))R{l*~n>=K+o z0TeioJQ{(Np-6Gb4hpKjOX>u(Iq)DPxCj3p&`~mR zA(?m+#7QkNB@lbE^v5aPw;U> zCk3})v=y0EJx@6)$XLngkVIawJt5IEcM+r5UikJJoGb+N*U_asLvthWH;X*`KH&-( zFzJX&UR6CoZQ-hC0{E7`ZeJ1Sk=liv{u%Kxq^)8Hhz$j#4te6?Y2WlA4m-P}EL!{8 z6H?7{jRV%6rRQmrxIPrk|lLNsoGB zh)lqj+^Q4qH6e%!Qk4uT6DpI;1*uiY13{b&Sg2V`Z)cbg%1g=(Od~h)9m3EsgIk7T zeUk-7mL!*O@DMl}h;B&>HDMhR^5yr@Qkx_zFOd~yZT90K%`EU_T)tY*8BJ)Yskd+p(E4r2S#k9jM_8?-e z!-r)~lA`EdyVTpIU2|f6^-aWO_Bw87p)RZ%m^(=MCKsPgINTR@-DY&{^^FOLN^Cy( z8<+YJKRs9Ckp|sEXC@?svTL>q6nZ~)asrWI$*dmwu*OMm7NdK8$W6UmY+NCRN_99R zsjHA9?}Y92E(fAE8-&h%7=j3p^O_{V+kL zkOLT0&Qjj2=1EV8WD))FvwyRKClPtPh}P0imW{}9xa_U8$z~@&mQzm|$#IO=aKj@oqQ-jLh$#$){zY~=o51)3Em=?P&BU);cK&0?o!Kh@CD!2;Rt}43H z@1R(L`Rbw*f1XY%9-_(*(UlIJNDS=bB(Rk>Ys*fI2|Bu+_(>wE91tUpz;8bV51~Z! z%}@0qy0$I*Qmb1!G5np;wLY}$RpgT;zqeGcQf@#6aI*TQ53#v|@QbeeDL+B2BfEw{ zkG*s;K}P3pQw!pdHyc7TSY@K)zf4lf*ot3TYU)7 z*1RK+(s!724Vx{a6WK+C;j&+0=lUWEaiIhf1ql1$E-A7Sa0k~9-f}bH04M$srGKe! zHe~y@ONw4)XK|5ifs>WB(CUap>}*y|A7XumBXjBMou}=d+b_8Of;+q9L*zZ@0v5ZC zLOw)t46c&n)|h4RZ~&fbz!9yUx7au)0P}+(-`wQmrlT**1@|4X&zACZzq0BOk+3}wkKHb zljl1;C2F7pI@hO>HETapjjz3{|XvqKx>sWvG{KuYxr8NwQ9PT`Y zqjNqZ0(rvWsU`7+qyO+p+vSc{LhEbJBW)L>uZ6!Mf9m8|-Z@%kF@qLJi)gmG*R?J& z%#MU?a}<=IT@t>MQshR&qbZkw@v>pvMHrc4*d+J}l;rZ8c7dB#Nt8>gx|Aep?la87 zcTd_c+mIwnLax>Z2wf#F5xUEr&J7o00J?>tEd9wgjWL|D`4h&gWC}OLBM>bE$^&h0 z!Q!Z1I$Q!nNcxLj5iHt3elbu+`1Ryn!<8Ty6dZY;qv9Y(0^y!|q(m76rT}1L1y_Sl z^j)-1vcV)c(`6b6V&*!|20DLu@=O3)LIi_d-71|E%hA_%xyJJUqwL<6+S-z>QSXQO zAE2g@1oNuI`6K}m`)=P=GWWW4qA5R#ilK2n~(V57{$YwrqKG zoqv0@BU8-`hY zA*OxX(F9V^e&BM5JJ+P(K(pTL@9W`o!%3h>rAl@B*H!+l(r$;A2fNSv&d>1PQEzX< zDOzLVnPa1Snd@BbDBprJd~rK~Kx=>^&w&g^#d0&n=u9~Acj^Q=bL_|?_N`Hl4<0=wQ6Wt0m*EK5slpl*)|6y>o z))ZJG`>9pBc#7HFp~p$Rg34QXb!)rY7^_s}GK6t(0)n$q*6$*xDr_q?NC>C|7ZkQn6x}{A*ZdPEo%n;=Bt7YmN7; zWWV&b^T-9sk?8hocj2M=+lrkItdUrI1twu})WH@8S*k^W1Gj zwxk(Y5yQww5s9`bD4gVjjoaW0?o4gfkp zBK#-!3UpeP7&`BL0C#J9uwH1ObMPhKLb8_vA~)s3hj<1tSV5dt$>5EzN%yN>gJs?a zp19_5cPjk6_>?aJ*FwQY(&?@i9A0_W>i`7SG*5E8F}@cOe!J>aDQO72*5SdF2jLPp zivRr(FF_}J@2F^7AD;)@cMZI=uS!!SmmcH3v?kgD>mBpsqINxY+rM*T3XAs%^HmTX zHd5?xJS+U-+jYFK{@Ht|RXpUhvaI~Btb-FTtt@5r8POlkRt|&SLz}2BPLQ;+N*3zG zJLL}K3(v%|G$z5D-PL2Rdx2jUVW0}+syckLHeh0F#z1pI3DxVg)1tNQ8VNk6yaT;v z)iZpswBGxt95%wr)0Y5V*K}7Y6(5#9{WWWBQ|T0#Gpz&lNvVD;sBh`7$$LY*_Idwl zi@@lj5@+V8v}WWo$v^TWzooyXp&T3zXnvXY5bcK&3BDTTwqZdXDEZXfiMV^>}5 zsCubQyL*Zqr286yP440Sf5LTuO`l1VZcVRp;&lYo@J6Gdi*%AP^;qA+By;f{&a09W z5PzOShQn&{`8DmG9)>HhYb+s+k2teCK3uS_yVS3)@RTL7Ksed`fQ?m#b_#pZq-U0C3RE+}ewT*BbLuuDX--JcdD2 zW)&Dp1uk-x(Snxqs_uXR!Qqo=C}c9GkB@l=B@g0qcv(PR{uY8)-R{3eB5#f02{Ua? z-*(Td>K^q?{ZgKT=sIT%Fi$0eVx2#W7F#72@eHn#*L2+6^>^@lj0Q`xF-+$1CSlxa z&H9|r;3~lsmhWR8AvnZyq>Ab$7`qs+Y7@g(V4ZKQ+ggbtoA^KS*AyfH4;`=Jp~}r- zP;*os|N0sawqtWwv%Zgc+#Ew4Ilgjm87x%uA>?Z7G|d*ZT*6F3sq;L9Xj^LyKzQK( zI-g;Wf*{d(Zd@1=Oq)}uE-yI%>NNx&bsi)eF4D|`23XD=wk+1E(b9s|NqX@u4rnF5 zN4B=B>AlFuI~-5MHhH$u>zJ#EcMhf(M{xqXT+)EPYz!Huu14xW)bz}b^{EnV+d=7O z%tU@oBJv_VGw!rU(qAfb^JSUuo8%L!(pd?k4~CV3RBaamn)>NGwxQ z6g;Sp!4zJr9jGeO&dgnbKCFDd@k_wo^CH?zH{_R`~FqNj$ z|3-RlOzLyc*OT}?9olN(Uu2`e{AeCQ`efk+@a!~)^6 zGb=|4ALKC4SCYwyIHeqw=k`oN;;aO5&qF77P0mu|0jZh$bopG>4+I$T-#DQ0oU|9= znti;DGYIw9b(SdoQ^ai`qYZSPeif$`q*65dWnH^VG&ooKT=PH@L?{etk>`xd?xAkT zcaL9&H3A$zuo|iYD=wZPear8GZ(?jjzakK7?ss_->%0v>asZki?iLCxi+&q}L&${Q0ZPMjHw;bMP<*Cc=P-~b zQoJhf!Tjl;auzY}T})Hvt>}z7Mbnbe{jEAp>*hLaA(T~_iNNOLZMXs_SRTq6nB#EKqU#fn8~$O@fSSHQ+jrrK>?|m7)l^zC@UC3jVDY6sA1@ol`^)X?zL4 zL~yMR6>s3v=gcqZU&M#xc3h|F*D6DeW$8l%<6-SoAV*lAF^)D!t|IjCXuMl&Dq_xJ zpaL?!=kw}gv$@4b|D5Z*vVj#%GLW&PPnCkIvJq3K>DNYDIC^Xia+jH*ADm8?Z!V(kga!&0l+p+#L zeRrmwS$*I1BAvxEISJ}umj6YL*q#zdX$gND{?J)*wo04hIo-mus-N0(ihp~KO~IAt zh3>M2>7ksd=$F^$Zl-@>qafC>(HBoS=0)``C6VV`kR=5uS7F{0?8UgziAhz%V_M#` zLzd9#Jbli@FLfC0qYV08rthjPk%B<3NWL%`96*ts5?rx0hYX##qHadX`5LYziy@4= zxDAK3)jRVh9PZ)G7_U<$k-*+=F3E=oG(_Ls@Tyq@?3#)wE?iTI?V#GSBJXnAiZdms zzt6pf28Mw``tdH2T683#hunSlTO8?H(|m?}+Orc}vLdzwMQdb7psI3?U+yD(aTyV0 z9~ch+816BWS8x40rY{%YhdFjx$vC+hfPO$0Bj_vYNM$F_17ma zxtQL44amUd15FBz{7ZOHuHtOfNeIly=kqesU4>i3l=$n@O=^P;cN=Ww2qaIT+#!2$ z6T|1Snl|Lq!gYqN;PSlk2*Sswh-~X}C8&AIU*eP+X;O2{Z$lKji+wtxx2Vrw2~iMd z_~Ej+ysyI(An4-mVlYB3d-b*w{u36!<&vx{NxJ**-Cq+BC_P7(JKxeVQ#2ZvAG*tD zmOn4&^X*-}B|Tayzr4`f@UTY++yoo>YA^SZ!f^Q*QOgXQ%3;Hec-@Mr{iJAeaGdM% zDOsLcfq|>K3=ff%onCzJ)*7Ev($DJo{%JV&MjB^wV3a^!WV+bpBV7{9xq1#X&Sl%~ zkYVMT3^yN{z_1b>kt;W=Ji-VY9z%T92yQ^ECvQ5cypl}1MJF2iG&HNPPi zF}?fmQ$9B`Vq@4+Z$OOt%9h1FK@$I|~60e%$J#1b4hPw>uT`q2(TJnd; ztJGBliLE*lqF{T(@Ky~6zb-+Dy3Azg>TGAnjw0Z{1M?QRW~4o;#1&2C!&+2>Kn zR5!BXb$kr_KtNHd0RQdkBF;^JJ@eE|8ZbL1hdvNR4s*tFjOFdJ#Ij(Fl=$Fgj<)gi zk8q9)4WWX^H<1W6ZP!>=7}6TbnM@XepP=T?4l zBxihand?<4k(N&l;tf{JXq%)5j|yS^ziA(~ZKxCIZJj8w)bR4FQ6VVwE_||)%c>S! zzW5q3@bJA$`Ys&VBT^%`|IW!d(XDK^{Ez!ce2yF}$7f}d{_2+THf1^cwX%*8-uP?f21j6_ zkKfaPxy-v_z2&@fh9SFB;e4j6ZeUfvqjvzxZ@bHUO2q`+rsN@ww9?tdIuxYbMTqaR zsE+G2{j1*$5Kk!sXv%}$r=i!jHP5R?*c zw1-#^J2H@*(A(Rzy4bBHpr!HMOQ2sPi4vvm*7lv=B*WQ)>!?0i>B;T4=e%=~8|m8k z>pc9N?^_m%PWP8-2JBy)V*Dj7KK_n-bHG&In}h4%oQ!ZtwhR^XnsB1aS}(}k8`U&w zWS3A(Di59z)M!U$j>iLoz4$aB0WNDPE!D)9L~!l0!%s4WH`hHNmA|>j(l$HKm)D+C zGhT}!JfzW%W(B1g>On5UW~lzfVc?IkFmY1CRZT7JK4b$)&cv73b!hAu*D| z6l-4wJU*&c6tnqU{Cky0nG`LA9VDaVdPsWu>q1Ys(HA!nc)6?~rmAOvGWnAzmQI}J zHHG`JE1avM^Rngx32CJDgFK%63Z_mBU^Rx553(LE(ph23t5c70y$RrIM0sCNRQpEu zC~s1sTH%V{C@c+zQ5M0j6!qfGc7I)`ss(#{8350S_d)CxSnh0!1*=%m|CN{e_*Y(5 z#0K3EV1CXMLYqQ+W{9}?8IMU`O%{lHa@pix|lqigVUxQ1_8@xPyj>SzSSGkg8 z>aVl*XUQ-jzr#Izym0BN5K-{D_*e_%-aJ%lm5A*@5r5c+?HejK3%00UoFMWX)dMuB>Z$hp^gYbLUbXTf?BvYKJ*f%3aE)C=ZV_=^Fai> zpm3Y-ds#u3UVJJ%QD)NFB3k% z$!>$Z<+5HYd(?tNLoqkXac0F-DPJmna-Wq_(^Eva$B3OkHX@5M|Mx+G8SP`V&ZHVS zlEFi88D;YbaLo){p{Hn=+Zk&Lz_ZD`+SreO#a7tY3*`j2-A`V{n&%nnRZw%5 zCre$$P2_!aj`N? zecpv25^#H{t!V3=FDm+yV*!%k>xE%tjdo}`)pE!wbGdq*E05GHaM-E)@&$XKJ$eojYwt?=}aJ z(%rTO73J4mMc`dd-~kAvHhe7l0|1f=g&L{gAdLJan^alnn~xC=+3X++K#|}nZ{mEP zOB+=v(_P+$0@MBk!geklR&BBYWX%Fr7x^#_lFUCe#7x=J_1LPN^K-)qjm zWvnP96!}3*=i5yr-A67HAWg++H zbbq;e$aSW|M@4RfgK{2m*Oj_@^{0R5J66I+t!@GCao8T4(%%5j~qhVd?BG_b|iB{>Xs;=_*{jxkGmUt>&d+v@9{3+Y) z04u3GLQpKhRh}Do6b4<%BLtwO6(V&xI^2@o)}T-BCSM056OXVC+bpFRsoR)qO=B6q z1RH%sg@mk@GD9I)7za!gf~o=t-92Mqb#HT!gZ`g8GfD>sh{Dr&e#t2=dXhsCpX59Z z56#e>?OiEXM`COd6}6BRc^UCgEKEw8+6X~gOtB08C!M5>}5JJ4rbykfCR~gSPw3rIQd{DI-U=^PdNeC8or z7mcAzbdIYgyxUc{esR~$u&tvOLXxiYJlRUwIL74LP5SfFnsZK8`Fq`PJIT};naaO{ zp)}H=9ZLjcr8X;H9>3w#382s-4`IgZK#76_{_A5-nlihsBLJMrz5V`*xv!jO839oS0AIDHh-IE|F;>i6&{x!}ysTel> zCNU(*TJE7t|4VLdgkS(r6-eCVEWmjQe)B*ai80(Rmp@rPMegAv)LlvKT0Mz~l`89r zS^~Bw9ch)!1man5E^oY1?*`9$JHLCt9``Zp9l!hE`$gA^+_i&RCjcQYy$9mu=MDU{v zutO2F^pceVqa*ebon9nzbDw|h(3VN{I-jEmlRO^%fd(XVcLysY2{x;+>N@i2{&p^F z4Jx{LOen!+-fnqW=TQkX;&dxwG};2Ce2(feT%tT$1cxhxlmGG+*_S;1$kC!>#RO=xM<6@>c#z7`Z$e6HGdGAVC=z&gOD4}5_ zCAmfXB?R0!0FKG*Y^#5kT1_jBp6St*Al-MTwyIwdjfCd&ZE(3p$E+G|uUem*bS8-@ zZBuBIrn|~x?wHr3`WF)4EgqN2{?tp}1ayc>?=mcbBN*$_Wx+bjqktwNWGP;BMoip? z+w*|d5ulYdsxx$O^hhk6` zCbMxfOhV#LEaUUnh@X(dp(_HV%g)Ix&baj0+`V)6N#R4STn2%Jt&_x2lwOr#&V|9k z%=Vd`-KyO_&&v`Dz%AH8L{MN$3$DHdf3;wNRUN#tq3daDvwWe1l4C|?BXi- zjUrg#76u=mC+|IHqD3Rte6CB}_QKn$qO!XQnTrzcywAFzQPE;+Rh3Vcw?0u3sk*wz zjCuLg`JvF<2Fc?SznyL$kXo^E{x$6g^Vll$!y%QwI^`!Az^BaDxD3i;(50VZwUQer z#awBet2`(1O{50PwaHhn{>@Tk1!6{p#Apu3lbDxj&N5(^5#%tAOmKo1nvZCPEcFKF z37e+w6T3;^{JlG#Dmuna5~*i_@Cfykb$|_g?~Y(>7GQMM*4`#OHK&FojIC2E!|c|1 zN=CRGxER;+RJKd%5HBwl_gq1ws6*KDl9QvRQ^re~q-C750FV`NhzGkFX6kluVT+5H z?_LeNtu|-HWB%g7A-IG?kHi(Wn8FaN#uhuBawa9zxo{xGEIu5~En%|>gVV8O*zVOq zoJO9I=vz8jYN1FdDkfE=8s317pxBm6p++O08=HkYS{CqQUS?j3TU?B)d~P!Qg~Ls+ zo-&3Y6t2HjQBfZM%9qDBw6HwjQ)Ub~fZA3_EL^=LY``+`V=Ca!ArT`LI~OzJHmJlS zDS?uhudH4O(2S~jfmjkbs}6TQ!2%$gU|e5vm7xD2nJKg3cZP#R4q1`A4S)BNd-X)> zq?JoQza+`*WCyLUh#n}^aSq`MihU~U^ZhdKz0>MRU^Fjzekz2(M3M1&ehOay=md^J zVL+^&HHo7W`b!!|xc5bFZF3;0!Xi1JVo{ywZO%zA1UEfTmru8hcpa%RjfVPewZ*Cv* zGBI6VSw%D99V#UQ)Ij5Hoj7wa=2W=r2}7$o_K2WGhhp~zCgfYrsWuYPVltDDCj)p? zyj^b-#^mIr`k2c*I&AYEiYUY(CZ{tG>Nc>pWm~}OIe^X^zLR_3W!8eVl(15Z#7c+h zfl^E5n@TSk2fVIOtTD+l>Au*N+C(@JD+79;CR1spq!)5B=pokwi>`8rSNnJwvv5k@ zna{(kea_s1npmtcIN`U8ml$rB3)nak3!+?BYkpfara?Rht__t1 ziFJQnjl{r#cMoZhwDm%Cw74z6@Wrbo2_;V1)u+rARI4D>(5OG%n#Us9fnM-6I#R+Z zSFOo4-la&zNcR=F1s+I8@;N2Kqx2Yh-Puv4B-KE~aeJQ-5{*(^;_88T|2?OS`U@pG z!M9FZF=Zg6!%9}&r8xp=YvODY)YryDo{^*=SymNcIgtd9wQUxA3qK=HBCvU&(uC7^ zn|xJtK0M$`wf{F)ng(jpJ5?8Uo2dmvrY&5L3gqr$?@`*sml5LN6~%Tsvk$~W_3pWG z&J-8W5VS5+fMjH#j?kU!R7e2i4D~`f!;^ds`HvC!ZO*5!5`jD^&4J30VoltCj^S1b zqeQgo4et{xQU>4B2&9K|sS&U($$YEisk?lj+DK1Km-7_X;o5ehjdR->9vD3xof@k9 zhkO!we7P0AP?k)LRBeIr(lq#I$e7L8JPqBIsrd3k7xAmHT z?W%l+DZY&I)KSrjoX*09Pu*ghsmE3I?70*6JJUS@kERrrKgS+sF=m`eq|)0=p`7u* zs2!JLMJ`xK8?n@io74Pjly^+{MY8zjJ{%Kt7Hki!T%4s`RA&e3_D@aDOWHtmjM)(m zk;e|iX}m?Jps8JsWIrTsUzDx0Wd`wzQ2<|OQ&;K(&-B!`){ zI8V!g`~7Q#+G90KYNeTP&lwJm>nA)xitEqV!1+9UV}xMF01lG(chE~$@|$HT24g+m zA`Zh*G(Mdx=ep$KVTB~u8M%&?!&NU5{uV4ZmpRTd4Q21^nCY(1HgzX8Uzb<;Uh;Ed zHRoet)5DoO2FuWVD(^+;9`iydM(%(m|K6=~5RoSmBKh-(U&q@x3W%vzGq+*b)24Kn$=}>6VyYNms;&#y`&7)Oh+aBDf=U4>S|SW=CiLB&AVsV?Mt*+MQ})sN)( zNch5WOyg~;g^a7MS9P>5^e$on*U9Bzp)=T@Bj@Hi;lxGFKr%#KSJ~xIv7Ec@=z6IG z&($C$Vm0PXkO{2vv!|B`v0aznkoG7{w_Bbn*g%0&K95;=GUlc25ty#|{T{x9>jH91 zNJji6D(YMpuCW9KiKW?43sJnUIzTgvtVNI#PLdS0EdpS7z4U~D4}V`LUw-T)H#`as zkc#vEuG_s1QS44vM6nt#PU%RA!%&4d#T4!{JGGoiK#xH z-$#+mSXqQ4i@eX5%b%H(rcz&C&iyOzol;OSZ4q0mi`JjcnnbvY2Xd*@98vbrL zD`B{=HOSM$bKp>8f+>W+J%25eu)@N3HJW6GO>e*#WBJ0lKBqI=@g|)CJHkFH>I7=( zpo24(v4;ym(glin_!=AXzr-{>=l2}{I*nlU&HUtb;!5+Kstma8wgrNvF5Qx>#k9`9 z=OWJdP}95TgkQ!xQg-|z%N+S3%s@RnO%E>hQ)dQDyEZ_q5>PL1kJ3dN$8Gd@%jp8Y z6Ycl9vQBw>D&&d;3^S{j!wheRL=+1r3kt?N^vY(q6sF}Nt+NOY?O1LRF*U8N_L^{i z6(eQMV_PWnBNJN^#d7;`c&Q6FK%!%W(C*JU`Bm?s=rUI`1N_CA!RO9>Vvj z;4EHOG5c<@gxl-Juu(LULoTBYAnvZSJ{X+b@tYh@Clq}$386ZB^Zpe2N+GH?;}H0c zNmp?K8#?*az1ATQhZRtV(QP6p9q~X}wX(H&dy*@M+p5J15{J9i_60wTivg zU9a9i9O25Rj>jU4{ySX(bSsWO&y7tD>A^8& zGLVAmL(|gzy+XxPqP@+=$2b#ECkM4pX!AS;qsM#Vcr|#ntP=1Uizx_Ap4z<9=rNB~ z&T*=Vo@Lb?$?7Sq|4u{F0?8g1C0fiR&&8(3yvU`XhSgDhExR_HUDcF|+)6=Po#!d9 z$a&-W*Vz@j*L7lZuvqhZ6U!EhQwlXC^ zF91kh`J(Rr(2J^vFC&wGzeS3sc{1X(7`Oc`GGLpPY~>KexB;q8l>50q>o6c>W7k!p z3uubX*!_JSM$!aT0h#YbBiq4N*Ar$OV}B?PBpO{fLO!RYwZM@b;6e?o4u3BPi0Wee zGc)QsGBqEk#pgK=B83({Coy@9F{j+8a$8V@9OV)MR~rS!%+lJi;P6zV3TT0n^!$5J z-nO)e+5LLoT^9}Oti^afz6A zp4F%som_3oPfwKLRC=?U#p0wY(5d?;s)1d_%oP8o55u+S*(Kr5%BbGRS>&doW1M;~ zh;BU3@rlSty^;6L!(#uK!ca-86z4qeQx(Zo@^*36oq^6R0a>fQ=p0qo8DYLmfnQvl%-YF=ZFNPhkD7 ztLQ(RnMYt^&Tk`*iiBA$gYGiHKBT>>FwU@%-?@jc=}^1shLaux z!K^At%e2Xuq2+(WDvf4Bst5dUsaCV~DFN{@fRU$x(`;5kK46TSNLWBZs(934layv5 z1u~sBX)JO@59sLzpR!Xf2G@&mW3e%{-QVj|gz8wgj}*-KfI_Zqv|Wq&E+EVUDLF>o zAUhg!)ByA3XG>*PtdZ{TA#Nw)lRHOj zEb@c7EL2qsb7i{gny^%pnpQ&>n~NJz|Eb4$jjhS4G2r0UlIp}!ZR2Jq_Rdimp)jhs_&ZHpOaoos`A|| zYS?`tMP(w(9ZgAq@u78zVOD;my)x{q!%g~MN}^i5WK5!9o#v(xS*|&f&0}O=OeTw@ zCM%Gd>PT>ky@JQuArUCDR6dKQEgO>e*TLhMUTO1d2V&_M_202>5}$56B*pb(X;l7S z9}SRQDKW0bKYqH8_aa0G;;IB;7xU8IMi-LY`@4_E5VgsAHzC{(Do~LsrmHlWb3GPY z_1{6hWSK<|F)f&@!k^+=^LM-J$dJ{J;;Q!x57izh-mZMxb^5OgFZhd9tjo{N-#rqX zQ$cEeeBPhpL3ORH_sWw+r$O0@vn_FjO0yUrB?7X!6`W`5s4+Q4HE5pa+f~YEyH5IL z;SY72+I2{AN#pU$^EuW2v-|`yS;*Keltxv%mtw`!`9(fIHjh#&eigc3cU?<2r9cq6 z?xdE~IewX5o78j0?N+`rQ9LbHTS5;v5DcO+jqprES z9#*P4_REo;Uep(g#B&kC1Y?D5pfwO$t&>>)@R)@vTX`liJ_Q&#Ci)_X<2G>^MuHm<@hh-?V z)vt~1uQX3S4k>V%ROW%>&|OzneOlm%*A4Tdx?x``$Wj`tEbx>HYf$f1V>~P;AEQWuEfr$2kJ6YB|jz+Z`TDa6%M2;w;UVUCE z)9hGRDD)`*Le@*l4|$8bqzaZrDVCjJeg;`=bbyr?AZeRN4QS-eYL9#4BtVrg_hJz+puCp`DI5 z>573;W*Ut-t+7pGJ1TeCtPaWU-^EMS$Am(I)0aMFycecJwI-`P%wK6voUk&BYHtcv zig6~Dz-C7(QR^mrsM{*Z5doYew?NDb?Af<9+NcZd8j1@_F{< zE8w=C|Kct%VO8te&8Z`2$AZB%K2|!rj~U2nzhu5nvlfW3eA-nX=wQ$A-|(!8jgaF> zNRQd5bhRL2umiT%c8P(v&?29+tX|0}cd~wCoQ#t6cUboz2!++1D!i;iA*`NwLpc&o z?Ii|H{^}g2L_xIeuAJR@(JO1$3CHs9(WeedbfFlrIa?=M`bdP??JtQ<9TSeCM#dMA zB+u2!VW)>z**98tF$!l6sVZqk#O+p9^(6LY&eATBQZvO{mEEhvM~pHYNG3q`(-`OO zg161A|B7h3Kn+KdbVunWv9|F%jIFg?tK_EJjWZ8f3ey)~U#?^E@Ow_mb3ho%a1TQn zL&2F@Oqm$XYSrxaM$@RpY@vAI5*RlrdIesov}*N zUoe}7K?Xx`+)CgQhLBHhxf+D#IpooZW-Dz_K$%I*$F#4sP%I`wYU7S)8oSUIGMI9W zIVn(Cp;U3;FQQ~`JhP`Eq2+jH-^Z~NO5ws>94L2~zbkP|Xto$4S@<%Z6(hJzWL1#l zFjLc#zyhdZxa56`1KPOEppH1|L@j92;;YYHd^JO;uX=Vny+cOG%t(qdgkRrWR{v5W z2@F`b7*6%)JC@ik_dd3SjEy{oQNFnBXids_`oCnt|`_HTbpj zU%5Bd$w2{?FPSXDDxDio4$I?TiJ7P>P+8HK-8Xp<(Nv<|Tdek%&H*g7YtaUY%07&u zbt8M*;P1`=3$|%jmN=vXFrObC)AlVtyE7Scm6KdL2jELLzdCm8Q&M8`B*F4N_(G>M z^YZ+u3zKC42s1d4D`y<22BIocZc~>@&H3VBN&v}%bwU$khdp-)jDFiM!+8Ns)y1^uV#LW%!)S zu$~j9-7IP>b7#5?ygI%bhP-|vw`Aj4o*!=mtwCBvlR+B4_{!GCGRLA*8Yb%M(G=Bo zyARz=z+(4xznMLSFuSunlu>0+$MFrPS`6uvsS?jNH>W$dJo6m3lG^Sd~y zF_bl7sO^4zm1qhRZ=V9i%4p~F@9M$X&=DtNOuLK_O><=+bppmXmp)@_vh{e8oyo=o zz(K<9Z{E{C1}rEH;=XpuZ)1!pJ&8(Gj)-m!f9a331{soL`8af(k5!yCE7tuzKLFpo z+46iXObXLmZc;azhhp>AC|pjiyA9@^c-|41b#7y&I-B|<>`tG)ceY=t5;)7M1qXNc z7dT7D78?KZ-@N}!lQ>y^v(izPl_g=+JF4qUh^USXzxcdz*gYk>Dr8SuRCN6*3Ngn5 z970r!62&}Rlv1GWP@}Hgb`B>1Q_}}g=}SL8k}7J)_-BsT98UTe%1jC)%Ifto!4;@a zKCkph&7c@6Y*B0b3PN|ITI3GDty!@XNyt!sy3MAc731J{4-Z&lZ}I25zna$1J6*y3GbDu2{W#WMAEgyZ{yH8+hUWpB{TVq zpJH23vC%BExWIzp*mlNV^AuI%%E5BGt58B^LH?{_m;VggT}MWWJ?$`kiUyfu+_WPM zj@qUjwF3cSQ=rMp_asl(4>wy%1ZWuBj@3h?1BzApFveMhz24jH@a;&Otf7Qp^>hVM z=Y2|LS0Q@6S2sQy>T&5Rd7j-`$5pGeB_v}GvkY-er=SGLRk&P3FJc@pvAtOp+jO7_ zR-Y2`7G`#7PQ5!dJ_8|_e0a{Ux|&0^%?)(R_vK@Pv%Hr?TX$VA$0{9RZoBtVji}#@ z>wJN{zxJL7RS{$Tgs$4S$chSrnE}-Qd@qT1g*%Qf<}lX3ETlT~{qp@k-Q>EG&TJu; z>(OOxteYV;5qMO@yL^5HH}u6eYdq7*R4zsLf=^wm3E%Qen(?9%~Ari=(ZP^my_UB!!PY_ zKL-OcOQjc(%g6ec1kx1rF8hX!(JHkx!=2aMrW-aiOqICO_D-o`TThCOWQCSD)6oKa zV4Z9gpi;FC!xK%gB#)IlFnq;f8fJJxhKY-4XIGjamYfd=HHbO=Mn_ffK?z{jnq%W) z@lK>z)l4(GEiX8%ULRNz)p1uM4q5((`Iu;zvn?giwrlc#Cn|v?HQ23k;{p}+K@~HV zNP*x!cIJeXA~BirqlH6(6i&3$fdOG}wd~rk#(Y4mw=uuDNC6M|Kzm-v9Ji7v8m4a| z4TulG>1nB=9K^YPfdIor=${isW?p+DA6!?pO1!zA0pvX!3jOIe$4V`*s=f-ZI!eYw zl1lwjd4R>A$y=Ri=TYTaHM(J(Cun6fwwe*{Dqnm61eZ1f*|N@qJL7{>`mwdGE7LjH zlgairbta90eehQ|=ZdX%Hre`m+$5AwWG3_%c%>r83s%EZ)lJPsNfnR@Gv5;0%|_=+ ztZr2*x@`I?jLBQ=>0Lx(M)Ti~pQE&DA`zszs@7GZoH0?`8oTr33}V%K<*jI0Xfkfj z>j2F+*FTp!iL{9~%o!A0DoYSK)Ki7eGoegHBSr$C&YJFnLc}-mDSdDg!NY_!7o`fP zVy*Ttj}ssty2@^4{`>8W0Hs@KopTk0$390oSL|QnjjAysIX_VpN6f8S+xSM9P9OM% z!YWOWwE1q}))qVF=xR}pAI`fi#3@HtDhZ)w;huy)=2nN2 z+~tNB^&qwy$d8gz#Yb12*q?9AHksDu!6m1EQq68kn}0F7L!NjdJFWJ&R$?V!bF2h6 zaONfY+G*!qUuoQpwQiV`Ae z9!a`R6Kt;?fqzYuJX$;z)m2MwVf6Fxo5;&x2~?2=XC+712MS{=cs8|{`Bdn*Qtgb4 zsg3i}t;mDm&bP+eAVXG7al;)c&ky1&$u*dlm((s#<655mpHDH3WMVYcv{pG&JZpIFu!=-Bi zJ8txZpd5-^DY;er+kJzcUXhAg+B(NjQzV%ed3xt#6fsQ5JE=dfBnVsCjXHQG2a%ytj~t77)9E8(5&>Mt+9y>uVL zVrYn||Ee|J40yiBoFV&xyFJAV&dIU*%HnL!TdD2<88lPUS$47!XMFZL1$%czvmY%F zSd3Q35$7hH4%xYU5^nzR(*(i~RC?9!XF}s)eNcx=&Ff>XguQAfTG(DCpz=l{0`Y8F z^{#SdB1GTWuY7IIUY-L!r~VMb7r>_W5ZF&FwZ33$+c%=f3;0neYnlMykh z?$sov8?m>e8x(J|Zq@BF1PUoa6$tiBXB7D4eqD52-^eWvYw-JvAHRwCexhbryUHeX z`7s0M31N5vVAV#sRc;zZP*}E=o++R>Uy$?xMU(|yD<==PTq?ZGy?jOYg`;YP(g;Z@ zZ#LO88xHg4cXTUx({YmTeCO;0~nitmLbpWL`g2M z>q@8aP((x8X6Btvk%_20FMfN-S52U{+ZwZ3Rjf#wHtd=ir?OH4&tJM_sKEm|M>Ek+ zc`WZyRZ-E*SgPrs)yM6N`y*nzU=DNRj^bhYJnslRVcRQHURMxq!0*D zsTC*}34W3f;3`#()ym&vp73lyMhaV6U=`bjQN>Ozzp8kR`Ba)kY01$}#!u0veu4vX zd_p6jMW>P8nCxqyXl9*^o+{EpJ|KxjG-cu2Oy5A>BbvOI`fLVANRUhB`Pj;ao0z z^J}&OpAf4&!W~({;&DR29FEH&D!jkLfwW_Q47MIAU4_Mjub{zNL)JP4KOf8qfRWv* z$IW9|j{wIwcfB6B`v4dUcyK-yI2b#vN-sE$E&9HT+MtO>2^!vEYBy&g=Uib!>7%vx zNH5|*H4Zw|GH@J<2__npDe|q(2$oM|xF#G0jageh+XrDW4i$5u3AH7f$_W$I0bDfT zbDcx^;}s&2T=9Z!gA9wIf?2#AaC{uP{?c&EH0G3x(o=_0R8}Q~(??pndi>m+N%ub+h;N9v} zQzvlvflx~HXZT5dkSDNO3LNA)cec*cSc%wm{!?_w@^12RbxzYdp&6OZmnK9&%t`99 zVw((^)ma=WEUOB;zdq%HqZBQSpD#T8JaE89j^;%a(QN}hE2)ffO4QY-<3p>ySkM)H zb20L9=gvpWpBmi`MIhn>O)Iaf0Ms~99Z!4E!pfQSz={N^I>Ei-^}AQB5`_SKB1wN! zn`x5?7>Fe+DVc(rVm^GJrnI$e<7;*wpw7@`tcmL8LzJuI$zrQLb>9#@v1IK~d&)WI z5CIHJN}^)4{0%iAj#^_?+7@9fHG-wYSbn+D&2t`e8+>1A$W`wE9H}jxmxNcHkHJov z2rmlREeF7f6Z=DdLST16t~KmocV&RA+=W@{Ko2R|>OHj}>f{nV+CQL1RVaSNp!tIP zB=`0iOR1v#`>=1V;|(LN>{jW>u-;rRRaws!&#syPvI(RS7N;# z9ZH+(K(KIE^2J#mkalzVu7i*~(F9L{Zqp~?`Q$f5Zp4(lUj=XZQ2IEWmZ*5Mm9c4g z%#f0j>nI>EzrhLBF{gRQ9R{Vfr0!tlK9-}F?@`StPaOts)omy(QIDu-)#2=j>b_Bm z>8QN`!IyNRj$r2Mr-fpL%jY*vq;%EDH^Xq5Z?4c)w^)0#+^+oK6vlp7NWK^BCh$xc zzd37e*QaQSInh{>TdRz;-XpD&ifdvD)?4%c<2Q~a5RW$H5L+2sY!5tP_**qLFZ&jw z3kgvg4NPz7bgXGy_D$eXS@1sMQ!g+t_P&z{Gc{l<2uWpfE3I>pMdA}Qbb_s?c5~$f zVh}MnRnaf`@4e$G$I{69RsnAcqs_58hAyHGF6Mk7u1&-$*r@Q+hE(R8 z(^kZ~X$n%w9GvK6ptT}$jnGH_eAu)I^#p5MlIFTI)U;z1EgD3DOo#m)OWkZ+ZJ31?- z?Wbv`^DAZ7vLt=JZl)@TW_3Am>~yT$*~x+5kkW03dA^3mP-4D1Jj5O`>Z&2>SSZ9{ zj+w+^RaNb6i8hrmUl(symjc%t7GKhW1r{@htZ2t7K z5I7O@Io1OpxE$?{ML1#HY)tNEeIrUEeIT||_|5e6Rt$UhSTSn_^A>05ImAxoHD{h5KOYCl+(R~xZ$x=8|(1>ab zbLEoh6R#A%F zIBT0ZhUA3H#lje?+WxUfbQITH6;Ro-S^4ApN?aghBJF+<#TU5s3(qx)Sd$av^cjYF zS^S%*^!I^K=~Q7)jc$UQd0IJMXmRwH`d-Zq5rkQ^G*pV_PTr@CE zB`S)PncuJtRLi!YBzZp*bWl(tGe$(O!}0mpL`A?cEJinjCYEs5a&LwP*aVHu)`3t} zM3e_D`T|B42ab*DVEI$N^zOWH?uwye*yZ;r4O%`v=)9FvbtwRuwg>Hl!ITuTBRk!& z)y{zfv*8o+bsN}~zoAumWrC}uC##|-r;_ZPT24ttsIf{;bq=S+UZw;pksokk0CzP} zeOz!VSgG2$_Kgtjo1AJFqB5i6&5jr8gE^V@Dk?0C_!KXwo0TeDb6)O$ENW;$^-ri6 zs;eHKpz0_nEwl@;n+EQb2!jHFGVSHZ#BXRpK`XMsN6D6&IE3`^E8XS7h{I%PjYB)v zVbChqW5HERS&{cT^=wO{rc#b+!BtEY%cpTXfgJo%CG6{7?GZO#5_^1^I4`W5)UA7rY zgovhIIzKo&-BnP#IGY2gfm>5ymZ_{4%t6F`EE#O)N7eh}t(biIp4uP1(=MLYSVfbB z`bL^QK3DZ*E$y9RR>f24PA|u>FiYLAlXQ|ot*zF(`DZkFFj-sJb<;gAe|qP%1Sjh> z&mo~8L@2n;(?d80)t*8op<<{$o<vFSd9H3|%R^-3n#H)x*AScA{(@jHp0@Ig z7?JYk5?Si8c?CZ5A!REoBFeRJbcPuVT`dFG{l>Ac8%jNoMh~Qi>dm_`EFOkIsj<3Fc)Uv3X~eP^rCFPgOJqn<_rl){qWpy1 zpf)iTj+MCz4^_*l!xE-zKi-Wlyx&YUijMiW=)~gao)lVfPYr*9wC2s9hH6iM+!)aJA&a;LEe1n$f z8+M3K@GlkJn)V9_S@#Ls04DRvU!U>-Ti?rGn$}gp?supDA)08 z`C)vaze{Z}c8pJ;B+9ov!Q0<~Q))L*kJcq(*Qqm+dRu0cGJWb3S%hi_RPg&{H>E0m zn#9!KB@fpa^>WhlB&|b6~0+1y|xhlx+f!y_Nnpdb4HELx0b38dl2v%(4 z!l32r%s7lXvXtSHXB|NIbvlt6$;-@Eh?xe}Co^e<;_#QVlbZ(`4qY!{o%$pzyc*sTw)zO zj`_ThXX@07>l3Ol4azJ~EzDuz|C-1*f;itYRt|C;p}B>y+nev~D9S8s;$_sdS^6BOsPLZAv_)4F2^ZO%EYK6(3<$_1iK*BoHz=FN_(T_;?q zozoHRtb?TK$S)w~q-Lz6YzQaI;b?1ZIFNm!^Bam_+ldKltZNFYU0T62ZMDaH(htKV^Hzb#5IU;nQWgU(Ori3IN*xf}u_Ag$e64O=EG))|61tieM!f<-w-PwC8%=i;p)0JjI|?sjs#cOWslcz|>mN{)a3R4%1` zr@I?6q2tnbYNWgGz(C39G|r7h5KEUhEi8U|5dgz3>eWIUP={*_ghlHlqaR)cm;o^a{nT5%VG+sW28}b4pq<>mB0gB#slDX;Cm8gtW!B7 zfOXrAb6O(MjnE#mBLOcfSzV#Zan0q;v$;n=Z4OD~Y5%aVx@#Rls>v3Qqs*z9t*eyD8)-)u=B2&Kn$ z(xjWO4q(6m>)18;1Lb}RQF1=3mp6cIag5Uo8kU-(-ogr(pw%C1qz+%3OT9e8o5mfz_d@`%Zw4oyTCPg1 zK_L|FL=5YpyFKhgD7KjE0c%+&>LqV0;n?n$Lyd*pK&FMkiFva!@Hwg*SBuDF2sG?g zVp!bQ7WH zCLy0%j#Q;bi;>=ZMM`{71X09SG%u#&=kiJqvybC+4`(R3RC_<{0Y^K3|_HMZ+y`Q`*7g z>!|!^5_=0Lv@`C6l?gJx8jz^<^Bsnz(hv*d9&d`S>8!Hg>j^q@EDuTIhBa8sLcD2- zAnzV8QHku+yDp^Ip5qWM?v_VI$rctPy+!0{LwUMdYE*lQLH3sQX&eg{3f%TT2N#2bPUzKY54lE^SZcgHX zzxfK8#_6w!LTas*oR!CrGlx-tW?A?vJD$!N{728mVrDkKAio1Q6JI%hTWpn|lvt5v zx_FjF4#_%n+Lf%aZ50qVnOT|n3YdFne&$fIepbG@cr>^=| z>ih-gyg{dcIh(~0^T``Ts~U|Xy0*R0N9EPzh+|zjGoD7Ca^jj3?!m%bcXLXps3d^e zIq$@Z_aRkuI-|8&8(6Fu?k?WiCKhhnrfgNrw*EF629-Q#1=4B6PEa3Vu9cB}0|Zuk zFr?a+LGDsZ>&gN!MVOHGKHazx6%rB^&hiGREqTp-O@x={UqsTvmosulV(dc6(+#9w zexz@#*tZb6{2eN!+xm0)P6IY$bfjy9WWG}tsdFkz#6{U6@UD{U!F61(uJls%wR)>Q zIBbX!U=)qP0>SS;k=9sJt-4T2jfXbvOP{7g;;Q&tYH9&+cY98~7R3O5gE>`o8#AX* z!7&T7SO;13yN*nDeCUSt9iCv00frq&rFnv)#qJZLVa#ROojxce^P^D<_EsGWS@^pS zI6H)Uvg9>Cxf|sLwQ0nstCg7QZR-{M?s0AxpLEYw9e4!<^@%V)-qblO_LGsRXX|DT z!x=D-8?d@WMpm|{Wxextc5H6op6`GhyJy?gJh{oZ)OWfeP#XmtsDr7XxR^LW zxi&GCP;F`6{2c&Y;nn5Sy!npGg@V5q+vhS|PT3?G2$Vx_di^O%j@AM1I3NrDd2+zl zX*>v|5x3hA<1KuciusOyHbjjqky$L5~og5RLQQ1EU$whK=f zUUkFar(w|2zIA}4kHEFilco8Oq1zDu?(ND#)NhpsH;n3rDnb$@!sf*|L_D{l!kNB; zb8Gq0;H_@#kmA-?u{rEUFJiC_-MqE=Z82zVqIhl$y6e6KbzR2awJc&NiYx@+ZapsEJOrlcNhRrwQUPmWUN_j!GA^&1G1r-* zA=HOD%i8&u^GME{kbnxL#Yf={ZgBgn*nJVObWp?w#iP>OSWrLvg(1Bv<&K(F!*1LM z^Sc3%I@#K*FsJ;%To(t2I=>KYd7Y6VH1Q>*9Q>Cuz;6eGB(1iy3wNl?1Z*h%(UWu0 zaL71yuSIlGYW_8%2^eETK%w6%G_)dz6BI8lo9np&F;0DeZ37skbvu4vNLa zEnPSs@vSQJ$6~F6rTISj5y%~{cd;Y;AuJH;uu71ZqZ7T`o}lOO)>#?cnBE|$Mp>dr;osAl6x0SgSE3v)N@i1zL(X5jor_6YFq;KGO zL%!y(AVEH15w>;ZS-^5eBW^g`qU%wrb+yU6jKjtZmUmpm7R!a5--4CwS8{l18uBCk zo=RkR`BC>6=mu5xyu9I?kKnK+BJ$Hf@p&-q91IJ;r+auDaW%ECTRClfQMiC63p44J z!w$)bY)e}$h8IvB4^KB1|5`*^!`n|K>WRdmHSeR|VcAdxfj?M6pUsiTb;xUUAh*KJ zH?GmfoQ9?V>-Dw5T36*AdRiO8TD$Rpr+UtA7mVC~syka@I+eg|ANf|kmXGEVPW#hO zw>O{u{v55%Hcr(NXvDKT{JYNw1A z(UU&Y_Hg-#-H$Qka-mCZTR)k9swkk1vT%9omNEK&7QbK*N9f1P4Wsp^p0yldasF~2 z<;xYfQSh~J94m~9?_>)^q>4$80&*oKDJNg7VU7hmtrUv57?TzvleFjPnRn?uKi zju5pn&o%t`{B%`+^lX^ zcQA!zQBXiix%c4bH&@SB7hj)lU;eWgl#Su152kn+@;4SOdi2Bd`9)2E0=)0OQU5dl z^bjHShmv>#uKcyO_bk>Ua<)4o7PeCNda3ZwhUp?zM|MXPbuWG*i>pxu|{`7DP ziomY0r|xg{ySuwPf4KVm^_hP5)k96v;8$!NO}7nz_~77oe;W(rXsU`=TE4~J=a=UX zm(_CTiCuiT|NQ*&@jp=*f^q@u+a~aSJbf|+WHzs<0h+Lnw=d84U+-RSA7dAZnE|vC z48k@*%~i>A{;$8EPnA+C{#222{rKa>evHA~QpV@fP)vi2=a<_D3otq+%%|W%j#wiu zwHGn}gI9VoRf4Z58OXj|WS5ucFT+5bPL&g@>xJ0IQ@VA-~W&wzyJUKb#wLdFE9G=uiMMv+SBK+kNgtMMdV_ zyL?!Ga~DlAXc`^qg+`j<_0#%``fq=i3F||lp3nLE`QmT>@y}tCD*dTsxlQ#?m%G3F z@id5rWTt6ox8M86_xh{5JBrq?3**sF`q$%Av%tf}`uE|(^UIGb)=&NW>1(rDKQ7-s z-1?ix^QVh{-6(=Rzq81GT>1Q1M(zK3T_YsL&{$FD{`2GM{wNMKh<5H{z{aLW%>)k`UJ zcltG!BCRAuMp~4AKMg-bwu)e@P7VM3$53PN!5k_8cJ7CZ_CXj!$_k!xJ#6m}f=+vZ zOZRnn%MVI{_jGpJoZb$H$%jKti|`e;r=Rnp{jybMHFtS&hLlW;e0mcX0oKw)khPm( z$9>RZqDpMHrnh-fZ9Y$ zK%V_JFS?(J=aJ+^m^XNCYx+4ZQXAnh;F{eIhua4lqlT_LxxDC5E;X;|=e!7?JW|*) zy@`uizkJiHO1mEEGIj-$iVFB=e%g(3B2r2Z}TGNy1wW0 z=}lY&Pwz@r>`y-rd-emRc%2yR>$|+Thm8vZncn6_n&3NnflP1WqPmDVNAzrZGo0%m zqzOdp&eYF&QT(a1iAX0eA^|!i_olbQ#kDQpCZT6Ko(30WjS$e8^S^MTK>&YEiM(P_ zT!!n>upZWcDzI>S>3W=3OM>HocI5RWuF652Qo%ZKhj<388YxCp`s;CCB_OcPx0+tB z#npZF!`1c69flcPBQ}Jx0GGNR=T&XhbPaOfwYYk)dtm#?^?tt?%)}ZVlZ7FAxr`T< z7uhV)5S#xoMn~Ja-6FM4Z}ScYT-Ftkc^$=tYb0CMlR8THEI*dvn(9n>Wzf;x)z`QR zP*A2T?mmCctFuF$iM+(HVb%m&C!C`Sw!aL2sy5clIgdUDqiC)4cQ6IT?6+~-69P2A zCi4@w)vgVVrXt$QxGf-9bPOH&T3*G{q_0Wuo@jhEV@Bd?t$QhH!0hD^H>{m1)mDCC z(&EQBu5t@tq3gB5QC=f}fyp8gb2tq@b|!IO@`2amya58B)&-QPM|p#4O{+f2-wszt zxMOyiaN}AK@#DUua_h9i5N!P&PT2_W_{7x_irGSQ0^u+(K=a*pvjCb*zThT#nu3^cHk?|0&>hFzD+@Fb6&d$@j zetwF@KHgKTD{9wM^0FHTW@zuE$a|BKD0dh)^0p-o!@O7^F%FzA{7JRN-nIYuUA^f_!_2HISRI}Ah4%YLKVNL|$mjPa>`v#G6F8=qmLjoIC* z^ENM@XE&o_2J5vsSKmLb= zcAQ}I>Dq^GzK+V9aS*EW@5VuFq^;+c1FP>f%tz3%PFlJCK7RKYOrVg&I2(p|PGnY{ zzxc8B_j$egHAI!z1!uYc_x^Wzg6?G* z+AsO{`c5k;=8w7_zk5PtRXkJn{{AtqA84LcEr08J+~?$Yhk~VUG}p{bJSVH9y+)b6 z?&uxEWOr3l`FqPD{~ph+^{o_FcHZR}^L94VsHXjLeB)Hcd-sSZS-%`lBo&5X%va&T z=R!xjLMssi)Gx=I!I019@?h;gdHr<1&~f+o_j!N(i)xh8WXS-RIQJdAD!uO#}Js|cwZzEK(czS`un_3@j<1u%MRzCb5ffM zTm5W2zRF&>XN4RdGp|?KcImm)g2?+EpDBV+ELICE|DM>t-q{|<_2F@JuyE{4fP^OGrYz#8ZY|PxXH*EoEIt^1o1nNEgy$CVaEV&risZ-07;-{8t% z>I=o{B#wMa*Hzj6eg?*148LaMtnSv*Zv>Z!uDooGgQRO;kq z`d>c8Z$N)$qz)yP4U1av!V%?!Jsh|Un zS%;g$KW_!wte)QOgB+40v@&3k)y{h4oRg&ENR(f5_w_m3%N!FMred+x4&0m%*sEd+ z1(tsNy!)VxtWE$ejLF{s2A-bjbl^8SYduljaB@(>N$rCeD#TEq`b4r06E1a8KR&KkIvE!evCd#k1uTP`W&m#xQK{ z3H}(Kp!E8xvSjh1!~CyBQBO{V|CtV4}9fKii9ABVUu<)eE;Qc3T02|bE#6bjv*Ld?x_#$4zC)Nnz*=7Hqh*`#Baq!x0cJw$cP{fgYC2(p z5@@xZ?&5c<8w{lTo5@Nc(zdC>DzH>qtphzH# z?+iw0qYTI9KGRsI#hvZ*;}JIK6sv+P5425C9B><3j68qV)3uM{MBdmsKDDw4WGz05 z<9$O5Bco7#M;GHTScHvwSvGRvTW)-hXWt;=sCcdn(qg5?x3sXHIptqBM9km@&Wqfu zI-}=LUtcai|2<4DZX?Q;!twUX58W%vF$-=`{*jdadcM!cfSIw$)cQUA#b315hJn(= z;+WICa73RjbD$3Bwv_zua(MHGgtno?Wdz&0%z;vW3ht^&X&>eA(sfoeQZ{w5&SNzA zLC)lgR7~Z~OHL)J6?MSMIhLy_zQqoT%j?jr(nJ;~c>Jm)~ow(*TN zG4qxWKiJ9*Rt%Y!U$OXBj-gZnO(q4YOKTNtL-hz*TQyUQZ{<{y1Hso`hF4c#a(L;u zS4-EO=_h&gFJI4Nf8kitdE~{INhbK~fSPUS(V?nK3VHES0BRf5tt#VeMYXBS;dRU_ zl4G7fTG`jv0ikb@JmS7D*4hIz{9}dwDe$b`qszg#OuXjLZCOsFo24CoPRsQt{__4Q zQqE#HzI31MD}?3HISuY^Z^~B~z<@v1g3ETn$l5S|>3)y;nM!44Pp@+}tb#v*whH}) zKCg>0J|mY!(5Zm<+7!>-J&WnDvT`|XtodN&XGQU$)lmk7$=-PWn%2dquwTes4UJEI zc0MFlW>d^L#WbjdKRzAKw%Jqzsj4F|;`LqUL5%rqO5m1oqvPer0OfaOLH6Nc_IUdk zcVkEs&!@%ms%p%-@#ULmo=^3OAucDEx%hbb!^@0%ayAw@_F!zZ3&GcD|1P$MbnP-F zU;jGn{#CS*_^`en{~UN8?Pfo*Jb23*#R)Zogz$$p4Ney(v#13>*6AP22K7pqnai^u zm)9`StMl^llCr?b{*g>lIHWR^hf{FKkn$WM$?a|LAOXL!90vY?^u?CI-l{JAB)!NftJ>9jq|QjdSNDlF7rLjNOh0~m{^>D} zkg|`cI~$9ipOIJzy%tzCWca6VR+9r&%koDzKYz3GY5+-HVlRIF%@ZE}4#93i_VYK3 z(B}lJiTnD~Z^{|!Sx1`Tv&Dggh}}* zQTfxC>G+k4>4$+=KYgkWMJ0mew_xr_MA!2Eu^88hW@+tPxe3_d&re2Hg7Tfi$a?(M z$0SaWA5c~rFG!NQzdHqI{35}Et(go ziTG(YH;m{GZI#6u{rU4h1=;&e$+dmC4DH(){qq2NM&MvEW52kCf;TK8M_5~{zxadd z-!413FfMJ?yj_!jp70YeysMA175(!)aDzE&WWb8C@exyCVU=rB?bLwuyUSnW_8-pV zuoeSb7QEhV`MbaP>s^UpcISGrYMaUb{mpmu2-kz69;I!e_x{`xQ6A#u*opSH|La*w zG*vRV0ftK>zWw@&zkb)9>ib$|xGm!M-nFWL=wvUq#Jhie#<8g;e{Fre|JP?SGZn;s zY}@6Xfl($;no;z5p^u-KzZE?MaF<0nB?dgs+4DyT2Cd ztIy^xdYa{-{m#?C2Fk$HbT#|(&e({9b>k5;`hn#M`_2!*N)>o=KfAU3JA*^R8u?rT zuv?kGdtDt_RKCkvw^QW3!9nh$D~)t#6Ta@N-`lb?o%G0ZIf3egeD~f;zxkbI`97DK zerFg}JyQy{hCA!=>(|`Eo3A!9u+tYi;knjKqwSPPLwnB-TCwPq|YjWTDzwCNB?ua>+h?Rxxj+!n==H#+YFt;@{9DsK zL|1*XYN~m)KX%ctcYpo4RD|$g>FvA@)9?PA1Iyz_*A3J4zZS-UmZ3-R`I_Zn>HW?G zY)!GXp(g&mpS9mTPMxTLqVjovETR83o|QyVpVw^Z-D=}0zTQ?c%`xb=!fzi*GZIeC z!Sv-9j^1xKD2feP0%kjGn3Pj$9N;S*z8fCs?Ifzb@(I(_kYiSj4Zfh$2N{<58 z`eIMN9oOH!3s7VS$B0)q?CZB*&P7hd6yOC`u|`(eM3}d9(Y#2%!hbhZrz+@ofuwI% z`0xMxkO+A3uG{JP&bhKRJ=I>m@HX8;e=Nb@uWvfQNW)d|_W9dujQ`HO>1isDh!gR~ zX8igEw!w#|jIpALGOX{9r!Q1S8~bSC04!hl_Y>v|MTjgJ887kk!uatz1Ly?N5NOj6 z#ai^8rGZI{fc+1LP+d(WY$YbGJt}xWHv6~bd3ZlCBvAo{?+_0Ipr(zi8^OcM>YL~0H z$G&q+w-I@(edl?#?>H}uZtB6xuUp|wNJA_1s8^3g`M+j{pnGv>7Eg7#N}#emB}5BX zr(jZV|Ge6FNc*;4IPE)MRtaymr-*cj4GJUt%+k!q0{iu9rmk^#Dy_kD`+3uB{dT3{ zs_8v}m9&Iyew^s>gWZaT(rYDA+j#-Qy#ED+^lB2e7_?Qw+3o4RTpL1gb4-4AM1MU1 z`^crl?C4(1DdjnBi4>=84A!rQS&abR9-?#`g%y8C@u0zLcCZ5c27dmy{jVUx?J3bveNRDz25xCP z-+eZaiRJ}rZ(b@>v+~f*0p9Ao_8sp3H>Wi1e07RM#wutTPPgBAb=yj2&{!Qlk zCr{;flfyw*OHd*bochJ6g{Aqi9l903g(fDk*wkNEdHEe#2O^Dg&W)dWwIJ{OjxQam zlbK5q*KYfHN`LimzI3cav=m)f+##xYyBY?!(>G`bpY9ehtgW>bUq}u7cEQT^rRSA! zqn#-^9LnTdW~b7T?|Ys*Q#n<8P1dMA+e)jZzND3W)sD9>trRcUmr55({@nZg!s7gT zu(8Mx4lCfSQK&g8L-XTre`Q4d5)7F-O`F!&2;|+hu*)l|CbjLCE?0b~U4A%i{e=gH zsj|}J0YO>pMZ)0Kki7eNijok%iwJHY^g3JVmt>IP4VauY!RcG05--;+A!WmW{z85|+m{u0t@h%l z#|V)*(|=o zW&#xZb>*2w)*<||fOcNZ*SiBT+lA26lU>a0iuQqi@*y>y#Txpu;u$kj2DG`f{m6$a znFo9Tbv;-=&3di)Lvt;$^r&h6^Q)bFcO2&E{#vx~Y8!85(fGS38Ysu9#8e_^;*?#%)|0%T5%7aq8sh+ zQ%trqUM=!FLr!%K?}SBO#6}hEtzayDOG&M|qlGCd1nbRI{pziJ3oCa2^|zi^Gt9fC zIHmybH5mVSFaG+sG?S@bNDGhPd9?^`m+YN#F(Tv3rM}X-@GaR<1F04q7r(XYdyxWYE#=z5vFgBcUpLicFJr7_X!`C0?oy9YF16hEs|B>XQyt$<5XBb1 z^}O=8j-^biqTbrQTyrN)~d_!@MwOdQO|M=m$Uq?g%YalQ^i?6;i?wO$#}5o*B0-!>TezGR^yCi zKvgLFO4d+?Fj+YvuOa-EANXqv#doYeY0EKObRvwG=XjP(N=@>r zOa7D+!al3vJ3rR$yVmfORt>qYCCIa?g(7dO3YJ&nw|-dOcW3Ji(s@$s;@WZJy(;<&tml^9mNAzBb>VDVALP+KSHC9@j?qr4u@4?bTL(NR`Bd zQcH%RCi*o9dS@X0+A%sGQOd=yt^SZ&5b7Yh#EV{Ins=7S9>hpLl%>`F@*26X_AM2c zi-BA*aM+tt5!>9R{jzwq*I#>gM0W9m4y$iX8_3sRd-oxC)eFvEkFnQpz5ioGSs?bW z7H&0zzcp7SS{B7s_#}Nf1mc=V%lC8^1IWvPa8v}&vHm!fuZ*wQl?(T?s7<0 z9?1i2Fa0@Q56_?TV!!eV_NKf=tqN2`){tDT2t@6H$x1PO>HJ-;JON6F_ck|QBifaR z#Ga88d38`%o&a>Yvn|pPi|KydIPcEe(JtNtNub4aue`Yxx*e9V_2O$QkEGI4#VEv0 z+XSrqkm{)pXiXLRyuRDJU(;#xbXz^~a+R!VxlW`v4|xjh zYtOHX>-}Flf^U_yRGq-DYwO(+IXTjcQ>(+pkFET*(@i?={@cEGx$-mW8-kIi2S{g1 z-hD{ros=C)IMcg5uRPnTxT|T$GQ@aY$?p#2nfRT|(Q-&uo^4>g;BNVlUtU-8`|pN7 zbfV3`|4-SSX2sDYX~TXOQwu1O1L&7B$pOgud>eQUqeK^y5Fnwh)qj_HBe07X-XAu2m6OIPK^7Kt_gpNSn`^-wuZKNay;AxrP`=2`w<6J^pd5-t> zeZui*0L?-MwGz|vz5l~=S{+6yQL`?)_5AC)fFzNl1~#*-=lkcUVK)#k2)glH-M_zn zPn8IOg{_n6$NR^*z*weH7E{Lg{&iWYdOnVBA!R*x^ZV;Km3xBp(EhB<@BPoMfntFE z+!`*sasKst65DlNR@+y;_kVa!aBg`V<*acYcI)})^S7YQE_KL}B~yzGwnN;-@cc+C zC#R<5sW;JsSK`@#2>^PDOh>`|vkHXWyOw;Wo0ZZR`BSgB($eo{@Pdcq*GptZ>34x_ z7J#&`m3-viEhoch->sj?D^8H~KDaoO0+jhmwtRixYB1Kh34C#sn!IwPcQ0HG^cNlK zu=#q{Q+^}I`k^oq3N0n>&k_jI8$mSE?@8p>5+~B{fcA;C3CFyaIF-LV8%{272fL+z52$r zAPP{c!%{n_;w8??8(C?7s+>-vr#GVR`K6N~Uk(zN?i#%hy)FV3 zQJ&*=w9ov6`MsJ-qn4(M`EPTReh>4L>i0yje;BXMn?VXu;a2DN#yUiGJT!bFyOgW_ zac(D&8zDhhvoyCPH1pi}90Fdb!MXU$`s%);Qy_yR@5LMA1=R$EHUJUQ+};?&lIgL4 zE*Sgv=VPwZ5(Hb@9P7Zg|1(Vju9@o49L3dtUEk=Je5jjrtnV9RXi$N`GyQ*;pSP$z zRFc%ar=a$fUOr9lp7Qte&OPN~>C&^=j9OiL;_r6Po;_~cnXWFd*UooLc~92h$#BLE z|4<>Y_TWqN`$=;=ui!^}V**BdG&PIqqE1?J;6TIvs34Ym^3;I$a>*rh**%?^7`%|* zetfK7m)ZxL7jfOyUI=?90#t{QJpbe0^_RNdYas)lq4SrNCz`e~h z`b!J3+*B0hJz2Hvb4KNlivQBF@`r$AH3~=w?j7}L&{x4z{<^Od?F35rRIDx1a(9#J zz}gdLnd%ptS_*U|K9Bi+Okl4rYKOtdEMjo{_>iw2oBxd8=Ha3uX>~@}JZ_*X<736< zimRIHfcyM)Uze*RNll|70_5&P-Rur)7$&wi-0h{S<3lYy<(~|0&eD5fK?Z5fy|->y zXB-`#qmS!d9ho!l^C@%({jn0YkXE=+&Tb`Cs2L#BD$-T*AdN` z9%~(lNv7#a@s>*g!s9FfnRSkY9vm{wGVT+ZDyPEiVV-L_S4mI1k}=?J%r|j^PT=q& z$Y}Ijk3qva3*}0Q1v>C6S=6-EA2&I3x4F0E!L__ zqL=HB+u!wTD%OtY(0y^OMC!o;fL>v;9}<7kP#LT)Sc)He`KtCRGE{~LHE}}?(~cBd zIV@Kd{jUQ@Yj(Jdu9JI-KVk9=av1_==lQpCLJ2v%EFVo>e2y2eb$u;y3~2tUGq{}Y z^2l^snJ`{(jMQbQqfN{_Q0)e12@_XyCV&Sc9kPGjrmOiBMdKf{`mVV?} ztTudJs?u=7w32J>v=pc4$#!*7SKZX0OTyAW`&mIaJ1_;rnt7h@I!RuII{@AT?!DK# z3QK+*ZEX^wc}J%pryCf?-BligLnX~l2anq%@z(e>98o=Oa+fRcZXoBh3i`2E^?(j0 z&9bEX{^;bZv`f`Qc>0HYl@C@;qYmYFX@`I)@!$jLyiXkfJFwq{gz1t$@{EaW=`+s7 zk38cIj;O?eEdG$z!TuiMMT+|FYbWduur`we#(VkWS6y{(?8t4jI(cpz^7SwPw(rv1 zx`10~Bu>EBtMf__UBIQ%D(NY>XIZ8Lz}*kwyCLDSATdL?xfQKD!XwR zE_;-FQyJ3wjj#&+Z9s-<4^Y=n{=MQu^2g>@&d?q4ag2sI4nALHg3G*XS_A6Pa&@0x zLT}Mbja0a~%r6PJh%k9%jEikb^VzW=wMX(VGM zRwp{hg#wd4sX?M(r>?m2;`6VmP?~y=Lo0ZwBT){y2Ejt8f5}~>AW%WCQ&RPCliwlI z9%nz8Wm-TrL8FZjpMl)vf#6g+8;7!cm*(z#>UN>*h#HahjMWP-Gc>H+A5QL`?i8!R z#ravH_=$ZHVv^u=^^o2?vFT8nkArk78|+T>Mr4RYd-0?+xV$MPeIeB<3+ZawtA)k* zIJ#uq)^*aqTniy_ZaB_q>M*z2zj*(}fAjeC-Gm2j3od`81)=Tfp-RuEO{bYhlgp*C z$0XBYvuG5DuywpUUxu%-7%HA&Smet(6dr1v;OM2vMAslNL86Sh$JWUJUq6I6v>aUD zXJUmaH>8$O`#vWvvm0J4rUXFe-oGnP)a#BheII^t*>FU zJj-gl%bJ1=5d#`YTXqCPT(@B7BMZu|A{LEgnW@^8R8Uu!0~-@W9BNIx>j+4MY+`La zFMg)w*1e1(fB}+~RUzt12w6`jm@C67O-G+BbuhtOlSR=z!uprdp6FL*{VsEiu_lS1 z)5N=u_443SnMKd5^y*`<1e$pSPfOBOS3uGOptzO#lE&xq1{$Ovr?!mUW6l7De@BDM ztiQO7a^^!F3pD4h`wl+V4oCjV-F3CpyWGCBF{RBH&+-=+lB3!B`e~l!VOwlcomU}u zX6i=mm>P2m@ZEK_$Xur66^N6I|0cF`tXb@6WE0SQzRVH8=-0(8o3~wkx;OekPlIt+ z-J;9=rERNE-e@{hX9-n$coYS$SX%4ydIPpENUc+qW^l#2sR1pC9nP1>P%|YdyPQFcvg3e7HzPMX#~U$%Bmib&pV5*e%z;GqEccni>cl^`#tlIN znpn7zGba^aoN$$fEA3k%wtx_kvKr$~ZEL$K1&2eZ`z|L#%4Ml~qk`;{yF{|q`IVF^ z+siziB~+g&2L%lz@$}hB-xpZrgZuyemSj#OI%_?pCMb6%>Pj**@=e$*soQRMwnl>b zT8A2w=md9F7)b-cl9C!T7qY?cX*YLS^PG13G!EpM=t)yS>w3fW35iq=*{&dyFJs)+PxZ#{o=kfUbtF6EwjCg_6@t z;PRQA=F2Q|tq<(Z&u?kx7v#cmT;^%a@8;3eUml#|WAdAIr3xG$ zMdp&znwXM^G4U#-@~hQ+6tPMmDw6n15{n>96cpem509Bc=%S=F0aiZGR}%h8s%AWn z;grjaL)$7XlmSZP$obuZaAspKvjeQVWQrUq&xke2?~a}_V{FC>wk|6roRacnLw)I@ou_ngRuGEU5nYaUb@iv)Uc$h+Ya_hA?G?t^cR?U5b;Bb z^z%EUeu;JrL)%C?)jIlqFEy~S*7?`d$VDH=_9l-}m;YXlPWZ?^XERZ^DG=;zDBGJ~ za*SW{Nq@b{)@>A&XiLiAddPkXF<3D@p@gpwc^`#*1)2DKtjJznzYX&k<^=WOKFb!D zwWT1=taj_y?3Sg*uVi`RjGNg;I5)Z=T%=YtU6&;yJ9`fonKNn@KGuUdw7Aqyy}MZm zPO*%_hDuc8d2Lyh4p_iE5>nw1w3W-LEloE}fF&iz<>bC}nROeu5X`pxZg@DyWA-hR zFi!`z&~n9{$0Yo@TdLk6oKwbpIj4<>;>ezN{LK-wQC%3d)4)>wD3p7{2AE z9PK(9-Jr#>WP1fW`EONndgLM{FS=|!T%?WeX}X}Nykq5hZcD4l3fOpjUaRT^~bAsib=c^bD=sF^xa4un$Tw}SLi{dxDm`MWyAa{xOY52wk` zuZ77Wu^hSp%{aeD5K=0U?fre9II-VP7%!BByQ{CscXnep(g{5K{{25`+rc{>&LUSWT!m?Qh|uun_ObZiyaTts&)@ zZ}%ay?;iD4mvlLiJaKo4Y9~w4V6ppnf3ie->MJ*#DiLKq%~a0gF&i?Y3%RA!qS#!I zCKh*`qO|_(sG*Qw@$ja@PF>SwN3cOxrWA|sO+?VN8(I#2|Gr7y3@zA;|Crv=em#e< z_$8_2vq{P82?Bsk5gahB6xVcpxnX?{ex2X^H?2O&;n>NUS*3)vt^G5j2cw5dhuNCl(V!Ft*(!VtQUdpLh+R5PY z?%^`+FO-X+whU|=A~26%hdLn#g6cxY*XmN45t0%1rT$?v?GX+#(B(w-;`!5SFQaOn4PKN zmHYQii|)D(a_pw#p*YsfMT?&KZZt{=CkvUJxDV4Oit*SBcb8Xb{h<+PsOjgnEB%}u zqJ5CpU$$)X-icnX$I~eCB}5W;01qgrtGnUludjD$yG|h4P@aQ1XJ=K9PjASMq@CTJ zRs*m{EfMe#T@LSRTAdS451#8n40)8`wND%in|pTGtBb=g8jU4vqQ0JqI7t>9o9!C0 zr2HNM|4AUG3-qNRdQS&P*&abW4`+AP`_a>PO@PB83U_%P=1N9Yc+b4%Ix(wg%^)5h z=?8>e8Yh@79nV5>ySlHQn;vXmIY%^yh#lqC+~_~HfUe8pNZBJjUQYrr6wil;vn1-E zB&>mD$Li~DS-&gqjO%5oopHb&op14zIZ>Afq{|N2XH!l8q8;`Pg;Lr zP~P(hgR=<}@iY2?b3`V{!{d2cH~DGuD|iXQ2uk~+(S#=4fM|kgBu!>!d-YLAwG^(j zK9Tz-c(92mT5Ek40PYb*kzHwDW@tq21N!-Sle%p8IO44jg*U!iO}m~X9kCsU`uFc_ z|M%vuf+-5y^XzWFuCu&>iAYl@)Gg|dX3_yg6GA65?fLkKSmT3>^{*bto|@g@w_zw{ zd$l)*^RL65B!pi%52qL1$c6!u_VwyAGd&(Vw%_tN#*>-JT+*42jm9r@otO;3CMpGH z9=`gtU*SoSP$Q&c{S#e1_dg@kAB@dd^O>p3EFsibaFU_Lx&G-Y6w10)2^0BHdrNP%aBTq$tn`G^_ zL%y_Fxv`6?^K1q+B&u4lW#nuGwdG8Mp3Er$U4aY3$>xtvyX)}N7q3eiJ|6{8DZnP7 z2qz{i$y(BIpjutsCO1frD^G!Y^wSWoOe%%8d4euPX;6QsQa>+dn4ghWbd#KxJ#dM9 zg3_3-Tb^^*)!Ohn7AjAtbSWYBBtXD|i{bD z{d(21l9vigp~;AZT-+pYX>X}a>qvr5EW@w-dix@TBXB8Rkq(96-AIr(ghCEo_97W0 zED_gpq_Zai%^6L?TKzOzsgR^pRF3fUCgK!Um@C#`#9o}I2F$%xC?;}R$b^;xr8g@& z(~24$@Ewyv{CPaGFK7c~rn8=8)JhBi{fG17BJ*+~em))k zn6D2l>JhS%wM&NcD(2nNkV=Y7C@g$}>5#54!j)p?LRD!OHRaPbhR-r~H&I()W{?%3 zuYXN?AuwUNNY46Y0H9Q2;M3CsC|K}gi#XRKHuW$9j^{0XS|1GUXYc^;$wVkyi#_B0 zVYVdED^x0TIpTunSD8u(Mh-P@$}oS@_O4aQ+7-TtUzf>k-GeyD;TM_8Bx8QRAlp*V zK6p~LPr%VQyRLgr3Lx~>3vu3XkA~`#mRT@cB$}Qb(d9(Vu1n04tr5}N)^!^4YJmk) ztrD34hmfK+b{K6-^(FVDhiR2;eL^Kls#ri4>qTLmNyfxXfZlR0AY1#APa{(xI;e&U za(4Icw2x8|)X}iJs7i^Ph58`}g(wniOzXx|AOo3|AEDN?{_^7kPkm&6Z!Quu+-Rml z2@KV+_1%r&jZii+G@dkH+288%qLPCulh#?0u-F}xiLl!9cw|D^c0z$!oz@5K&xR@| zVjq(yzb6lT$h3C6s4V&S%y3~6!_2P1e$)TCWCP@6HP^Kd7%BM==S!j=9dkzlb(8SE z+$iV+RJz%QJN))0bqwxP6Evq6c8XEmSJk?&P-r{?M&aWv0_z{*2AfT| zsK5Qp%7q(h>6Zc-hI^Ni+50LLBnr?@%TcQ|)|bT^iRYn)I{W#C3b^oX$C6}4u`lX? zwppoR)h4p+OV{JIi2CJl$yOE24X#3CIZ%Hj^g5Su7aa6D1qk{h zo*dD4@Xc3u59d|n^+%wa0+@=x&Z4sqYfa~R5}V)rGC9uOIAX{N+}&JV=M=#HNaQI@ zkFp}kozov}fXQ0OawDnMZfN->uf9wpG2}iz1lm-Vrp3+1nH$cyO|-bDzmuunA8W-k z)uS7Y+}?k#>T;hgy@<3wzyFzbDGCbYhOY*keJGJa0KAkDBl(hu3PcZ!y$F`;oMPCY40TO)&g}*e zjC7hNlDU{g0=jrrlI?vtlSg#eh%-=r@)JtP)CU)#*4puCUabX2a|ZHSO*HNiPLABp zmVdC%@*2|#Fqrd)``_tcMk$KE9U<79*hFoUIg4q|NGu9dIs+P5vqmC;nzfdEV0{YT zVy0Vhm2n)RRB3~ zk%iDSsy_mcn8WIGGXDEh799mV%!;-Uf&l0Iv7Tf9QW{iW)BtcR)j5uGQZoDD*5^2h z`Q3d^+L9ZZte3VzpW7!8INj1w3j%eR6KCZm5<24oKwe%1(`AWFAGDks{3lGB-&-k17|e+b!JDqt zJQO~e)#d&X(X`?bENmgOdsfCus(pDPrz`d4N(eP0g|dc;M&yhw8Gz<-)ACC7VV5p+ zk}2MvFZpEh82L)1be=!_%xC#X(Khu4Sp_YmZyX;6rXfFNaf7A_azRItT;%#NAMy>h zB;{rj2k;?F2uZq9<-(o`UsK{2$M^{EQGERRTjuw$SL9V-?BUhREc93buwakcfxDK| zxzAq^aRrVF`;kJ0{bwI)JWA(olo?`xlDN(~!v}?<8WBZ2~=(cOU)CKeyMM za}asj)ix86c6zMej`v4!sH*vW@jZDXO%N+*5cCCJ!Q(brCKun+h)#yAzQ)7cp0tqW z5+x`_{e9D-HR?9R=P&^-f3ygl<)o=*oPf~9tCHTwK_nj&D8&z%*6Cy>c_T{LI9{`7 zv9CqF-2ccrkt>tT(LSA62P}CVoHSQiw+N=QP;xHl{OhrsM5(k+fyQux-hXcom!{`9 zO=FWTFRJgpuiRFNm2EBVY83B%n28PL+KhBR!(DF%!lPk|0_yeZFuMuRG^h41f zMK6lq&+ho?DL6*>9MY)N87W~Nu>=U`l*L`Be(RNWb&o=qi^N3M!AG6;>Mkxbq}Iu3e!6BXxkbkuQp?d zheQH!cIoyvQ=px?iNw*&KHC1~Naf}visXLZv^;Wnm1-&TD9ICvQXQjxDN7K-36*ll)BbH%^1VhJStV#& zqlta>&e0aw0Sum$pCB8jtfZo0q+FqWomb_ch0`5dzf6y~V^Kt_w`zH1KKtB_ED~&& z$3uE!6`bxkfj|-Pb_z@T&Z5Mmwq%{3k;Nn?*l?MjmCfvnfJR9(+aqkNq%XNcBH)A}4;m)xIi8y0ZeXCI>v6tJf(k z?2d}Dg_N&`J>|ubY-17h`*^rMJ58qhzLZ-D6D9P_FPS0)?ogJauHokU=bUO1H~5NT zp#`5?%c`Q-B+-+?dTQ$uF8lrYHOpaeaZ~t?XPWL{2>X3n3Y#KbL za=iVK3`ovxxnw~eNzm+D7?Ph{Y&^O7I}&z|5hx;{hviZ85UOzFAZduL3W)s?1tuI& z&fopx>22CKS~heTQGnRDpUFS7FYFZ78wX8sOXm@+0-S-b2dix5>+VN?6nrLXP{XfM znZ7$y4)B;yG2hbLxE+OdoM>6uSKoJICwD1~7p0ygh^nF&UxE zw#~E;)R6iP?#$+Vz0d3EjyNQg;TZE{Ys|v=!sNvj-I9pjHdl5fLzC`_+N)IB=PxZ~ z%FWv3^Cmk~U^Bv(VM`|Qv#$tD>LLerp`2u->`xBYiq1DBP~Xbx+GlR8S*>9xL=-ul zM5j%DFcpH<*k)6Xhm=R|j>ZF&sKA|L9&VMb_f|C1E_#xPVAPG;ni!bSmGCN5qLRXt zIhe%x1xgHYV+=`u+lSdm{?owYBz#ZWqdO$dp zq_WMaSJ>{^eQVv8(Hu!^vwSBLNYp^jXWEgW>Xvt4pNm-OnP@>{{UlC_LZ!4uZ}W0` zs@Ad(If!ji^814h(&^EQlId3pqRr}$U&)+e{Kto4_) z)>AM(vQVA**q<+X1S9I5vOIaBjP`M4sx+TT%Vv)9aj|iE zkY-c!CHB2Y34(xk^M&U~Y1BuN(j)k$Eee7y?!pLSGfJF}kUQYQK} zPZSn2l$J)ye$V<0q--VsQ6W(HMAhi_Sp%w)Y(ddy5<5E4RTSqt8l0*@_;s1qMkcD# znSf7=m!&}GK9heY`y$xu&DD862nyBI2y?eI1E?m!{>hP~m5sE9auD)f<6y_af#Jw| zwge|a%v0{Pt-~(ufkNjcZK5#v^M|WE(YcgQseg#A9TM1=dZP+PvRZQ#6Sc`UmCOx2 z!tv$WN!tSyb;*jAtIMPT;QJCY>}i>4>um-mM=PvCJD0`Z zOwfQ)YHR_Po<$j-kZ71{$|eq%)=d$E0%%OM5$9=tB9@7XH_SCZF_xSf!LV>8XaC5) z5^G)DS!Xfkmiq1v*fZ?#_dPQ+k4$`59w`{GhV7;mn2RA#fEC6wKW|#ka1~G=y{)*| z(jKVr6TUBX&PI?`5cc(0NRGF+2$)3G@-Bf8C;%(LuauFz59kC>mR8<~-!!%$LyB!s z0ViJ`TcBf!qZi);H*H!^g#Zy}E5Vyq=JWnSUOvBBQ8!!O$Nj|#A1=qlHVGu{!UDm| zd8gKv@O1u;F1Zj;qUhBcWXhpd%icjbjY5+czX~t$Jo#eSyZW7K^zL(b%NRH;B>>On zgFK^|%=T@GzpDmUk%qkn2WcrZYKR5ZRZ*9dkis?l%j1*97|5Zuj?5 z;ow$cZp-pojpu8bWJRMg)wDfu*2IMa+JfGcV>kO!3&XcrWKUbOULg=^uAy%lTh>}+ z|AN6PA?|jD*gn&Wg68;=WVe?IyL4Z|f$WSDmHSGyPg|-r0>&qerm+eWy0*i~GMR$O-2TPcxGN78brM$NNHLtkj*$4qW^FXjWd1ojSR-nZT2n0o@ zN_fhkvu4019W8WwauTW4m&v?R-L3c@={AE-Cw>hdb*(zM>`qJFh5Hrw!^McAY$n~r zVLu7Hfgs%&U7aXwec&zSnP<{s!`Bhz1VV9wXsF2cG;e}RAaIWoR~nTr9V_s7_!JjJp|)hk9VqsaI3sxd z`xo%YY>&95udnqkT!)9K>L3Tw*5Kzww84x%=j8JPHS*@lPv0nS$+2`0XHHp?QIx0B z#vU93Itky7O?u`kJBZ#o$FO^h@Epyhg*~8G`VvdiHnpPyZUJUF2^Z?G@L!~5I-q$k z14i%1uhX0B&)@1Y9Yk8Pg^%s{`sFff{|BIcp_GKy z2P0aas@FKOUmqDQRm(n5{LAl5OgG<33b4gvuk zN7*U_`D`3Oo14${o$*w&@H=uofCF+Usk;dN-z{_Fz+Mp{Qgs^b=X?GZBQ1&qW9+8Y z8v6nix&yLZ_qmev8+%+${%;3%Q*%v@NOCLw7KdFs*rDEL2$S$?`aWuEs4oEc)Zuz09r- zxPPfa2z0CTrgIV?N=IUq&ET^_e4svTIA?#vYP93J2hcbcVk_ZvVb5MCe~eo*QSiW8 zj@8Jv(E;d@W8lBQa0}V|PIMi`O`PY=aTTqp8s>pyDToGWC*c5~r?OcI#18E3&1p)YI^e|ubeLW^i)7shyfOmYPPT&?#9P^` z;d;V)TWd(SF~%lwpqkS`WdP5G*?aE6{H^&ks`s0W;}Ble ztT>3mB~h?ohY=so48WQLKPVss&oVL&p!Gr4ECu)xO-MS!fwH4RSqQ<)4e{n79h8N1 zP-=^lclnzUkvExql7vgIZ48Ch3nROl&!yQehI2i65JJ>^MvjS3eSSzux(AT)qlh2d zXh=S-p}2}1J~C=69MWniZIr|g5ugz7&%B1Z9K+BrWLN}I9>zw?tw>yn7q$|74uOBk=iWb%yXKaOXHj@vuFVNmhO=O&|;3#!oq7Ia@ zfQEAeH%wDTX+Sw5iV!Q`lGiY!WFtw?{8f~pe7ZJE{%H9oPpWq!8#v5Dn}X$q4qI$U zRzf7xjx~jNXyfr5z>qowJ`yHM3_g{%exw_o;6y=eA!<&O{`yfs7~@dD8IJ|Su9oq~ z5v^fyD27+o{`W68S?sj^4 zm;o0St&KS!K+|94%8!pK87V7Ld$!Zd%M#W~AbQ79!$D4Ky5&bY2gqE67u$N-I*0DT zV-W$cC_ESWM1ABdl~G%m_lucNW~wRz;qOU1PP5ZludoBTMPMp=$5xLD3mG}Cf2gwUVV{BqAyr@0Ft${lGc-NN&miCW1Q96Wr@I3-PU zsP9hsM>?alesus1MLgzl!i$QMhDJFE>5#ssH^LlTRWWer*_TYK6=%dPV z$kLKeVh&+)=68ZW;1mhpaXHR;kEANdnG_ss_Wfrvi$01~96_Pj8B2fXjuh z%h62VQ)(n*jUS|;r52q9Qn9C+lhQgxqm|>w70~NN9^s$0UDFI?1GQb~R4HbdM#bSdok5NkHd& zqPuEqg5{PC$`hBdAOWz6s1%Pue(p$e-Yhwx(k84$YgJWj*>Rh-P~wiD8Z?gAXM`Kc zVFFKE7T;#$Q17@0&HcwOr5!Ejz(;iygeF$j5MWDB;=PVITR9BH`*t#p*bGR0-jiK^8J1x5d zzZgglWXiCOStZYR!(IK;jsu65qvN^S;I1Z6I^xB%p{QHh)|(|fVX|9Ig&vj|;$ko! z3Py$vwbOs{v!E9P9IhF2yty@Ijb-7du(6-UoCtO?fb0a9Q;CEl2c)RQP!|JcJKiYr zBEC`tRO?waj3=P$W0_;Ep3MkihGYuPz3pmb)}kx4^kmE>%$Bl}nbEl`u){9ca@OD= zl`0kkFqx1k<=5<_d+Y8|iDw0xA+AV?x`THMplEx7?9{A1TwlcNAI#DDZ|(2r`0xI3>H!~839iu`Ro|!A2OGQ9whk+SuHk{jW|Wy6WID}Amb}R-1*kC zuwD!#acQ3tDZI^6wNJhR6YGGCsaZ7uUkg#$G1I0?KH!k32M0EP84vZ);xu;mgI(+t24MUkkL&Hruag)~!|J#{i95!fjgvuRU_KD^y-a{zXF{^9F^3n6O1zBVtZx&C zf*jgU!?;-;m%Q(-e$|>cV;KZOiCUIW$FqlL5>+9gHyie1$@yI2)xwo3q!ubg>(i8x zHO!R=VR9Xswuz-hQ_;xW7LTr6xrX(Y10Zhd)`r_P{Ty%4OHK`kq!m1Ft5POuu_P@Z zeF7ZY4*WTthPN2H&~`gtteI+Vo&XkMnO7Nj{xlDQMU`CT_T$Y9N)xBxfEC0jg!p1r zpy0r?smX$p<5^zAleaeBE12LKaFfV-i@HZ2i8 zs?2HryO+0?WvT0VAPl=LR$N$lCR8m#CLs73lx08wvw!wX6cP!&ayjUwF~u}rCvZ#kDA-%RWUG3lTzd`lH5^Daj$A5aAm zDjW*F6xQ+L{PLeKBQLK!efi>m8nmRF?Z}?d(hA4aSCr7!XA@fuMC~PUmLOr= ze@5u5fkgDp7~^X;{QR~kNxL0)KdS8|r)=N!9uLD>Q*3jeaP$61xXa?X7(Fa|)>z^|vrsrRpKX0y2@Bfj2 z_O1M>r+WG0pX-a}@4N3mZ~ysr`t`E>8NaK4eLcPX=kD_J_5H);UAgU#=I*CY|BMFz z{QE;N6`J8@@TvBu+>@552^997S~Kr~`J`P6Cw%ID`j=#+|F?a`o;)LdO-KQ$Pw*bU zoJu%~%x#Sl?1BD*HXvA;%7*u3#K_`h(4^+AduleKj0;Rst+D6?`V+TLZb8^No|YmC zsk8<)txMeTFyoCUNHx)Jtes;yF|zO>`X_Xm4)3=XaL(!1yHES|$HF`Knlh?S|NfLZ z^mMqk1t(R#OWWN2T4Oz-^9`p*Gm?5#y8;qNYB^8Jdp>=vrJP;pyWoZ`W)#lUSE(=D z$bSG8o)gZxVl31(;T8CPGk zihKQoIy~UI>KnMA%lgKD)O!m_^2%wBz42e4{(LDB|H8~Uw zKuokiQyyGI1>GPm2V6Qq2O!{0@o_o{ecMc;3pEuSlNR0g6>3XFi4G_M z5Z=BADPqAL5=a9Q0NVGCM4L6vRP7KL&G~E6mnN)|-P)%>e;=ZPynT6erCz=LMjpdx zBf0%pJ;;6jTyc2>P*(W2r>2!n^{IaXoVa-N%Jdun6{t8-^%#$|phWgZpn6e=fyA_L zS|iy93_vv4?4}exO-?N*yJ$$tH;^#-7P}yPN{55sEb}b|wO>5tBp}DjSe=UeG~&}7 zTZKlT_!e>jP5Z>1_N8!XaTE_W!>zO257z?E=XN8W%>++`97zUjXOdaoz8FX-YlUE9 zH0_(l6R6bj@zi^NkpO1XJc6^6Joln_HV}0ngc(9C_!M=Hgjm*RNT)U9xrW%QJ1xR{y1$udVvWlXc`1UJ= zAg5F+F;~R)xCUEEbaDWfGQf75k-r>TR3b-eOd0vhi3KpCH2bJ+()pzsS|!4RfE$eb zcdJ?My~58Vo9e(yzmMUc-Mn}O9Bf`-7!0MI#f!-^L3!1&fTm2jML+URB}U2W^XlEg zrO|;B0owsckO}xS__S%Fxe!WJYLq5TFTNbAn8Gp;`0!XVF{L9aa6NAA8Hx;9MIk#g8tI?TCcgK|ZF#x@Cx$Tap7w`TB^6NN((>o!qeKi1CF;j_Q%bw$EUK^*D-UXV`C&e6 zDPkelitv4Y(&r_mOMEo;>*cHhf^fbFlGqMA^S%T5G~;n-T2K3xXic^?{0)g4@!}6J zCMDl4x)^%2sWfe$(G>)sLk`?BC#q1er*sHmb<0(VL+IVF+}6-Zx@7b8%TH_QHwR4- z=o8uoG%ru<8LdA!bcljr=r3zoeE04&aIM?dvPejhqU}82 zj0l+@3K5s`tcJ!jSC*rsGKJAm;47c6%15~Ys%JQo0*T{E_}7nr)TRq~_ylJt6Z`ml zYSM*tzK@PwWpppN?#B^XPO~j4!fAPWcLM7Ye3aMEX%zhZ+vOjA71%`uV7t*oo-M^k zuqK*56fN#kGt%9+(v+-aB$q{&PvGIam=QDWn0>kv&d3&W2S zS~(nmq8o&Y`tk>$slcFYwWFZqmp@s;M3ng@X*DpNU*6~98|uOsd-L|9agXZALM0Yv z154JtB`t?oI8c3pufPWGy}S>bLD^5?ps&sZ=wP6D778g(zqaU8ZE6($hlC8w(3f9< zb|fYJiHkS)6M=y1k&D7p8w$YFV!ieu@Vs2?fNFvs-y9CNES#SLuM}`)FNSk;5+(A5 zSp*dH%i%~Y0d2Egv==P!<1y5exlVjB-5rgkMF%>LROPxfc$zQXf2`WjiD*oOH)lbu z7)JlZnCl-1KAJ2aOCE|H`s3Q^amp8eF$Jz?J6xiD>1qZK4U5?^h~HRIsFWNaYAB2yDDp zp4aJe9ZaOCWiRiu=@cbC@sO8HM!y58mvS2#(ec_EI+rqj89xm;=!5Mo%MX1){^uD z1{?$0N_qQhj6uZUpwMt5$p@2Hme=S zOS9T6@t0ZX#IgBXzMJnW5Y-sCSjc}GFMnQOmFu2pfl3+lb`Q5w>6Iy#NAw*itRoy} z%_$s?oH*e3|4r>bLePg4 zf7eQfbRr!vY-jGBb2$;M;EAFvM4zg33=XNmN3V{I?IE1iSbaY8bSD0?JxY<5Ysg*O zW)E*H+9ZUhHp4^3BA7ZKWeIrr3ln$` zsT~d!&#=Rcw&Bt5Sb)($Pi`SRd3zKsaN_Tnj%Pryffy;zfQo+KGf?71(@L;SnajJL zk=+IK6HsGh@4a(uG6%Gq=GVRc76t1UpFZ9~l$B+bK>1XqQ5Rrs`^Odq>$UOJ5Rl(R zA^A{~n?F79?@A`4!90qR=}ucRdA@_M(bj0N(8Zmq10XvP?O$-1*B{z!bTAT!iDiOA z^4e6wa!lkk9vrFzgNRq^sRO&@T@OLX*9yKVAP&5scRd7=M-zksG8CXq?|TRq!DPrA z+W=(Tyyu~bfbRTTv&f%@@zTuv43{KP`KCbP}>IKS~1! zmkp}0@Pj`-JNE1}KMM{|PzY>(0}KAQ@1|#`6d$OH+C@Ko_bm$BO}O>6;tG$O$#${+ z`gEG}RG!Lo!>z*=+^p9hpMJJt(}Bcgu*VM7cGiD=x{f>&jU&P!PFw5^{>o<2sv7Ah z$08=t@RIlB#k+UQ?|1sG%KIXkcfpmHFB?fzT0y`M`TZmzcT1YT%6R}dq;V2I4Quzq zD%&J9bMuXx_P!iZ&urlQM!7tIav{4kI$99r?uD)2sR`k>d{Qyq{2gN;a`4HAn97q@ z@#-rl1+F>(Rl?qR@zXpVJ&b2VX{j;FzrA$wW74XNrll# z1FG59nfHwRGhxl9urX!|6ut0|tD!JUQ6=<>?KyshUc{}$_Eg2kT;JLtDAN#QX!mj6 zo*&FSGAUnc>2lsyG|g9*pHZ&UZ{uv<*-9;v(MmzjDXUQS=Se3{#DKj!{wjWy6MB^f6EW=K4t`}+Dqy4mi-2s8 z!z*h|tjMvUwi(fzYpw8oEflglp0B+}g3VA>Xfy6V5DMpwrm9MwW8dD|Ty`I1SasB;e-8U+tomT#c23GmyVP&StHVOyp zHZJvIn@JSuRPl~DE>F|jZF8mwj&L~u6T}yU{^F;VA|g{>oK0A(Y{DN-pHLPSeLUkeQEmD7CeM-29=%YZt8A&U&Ltf+znUW? zIr+OI@-*Z2uM|JYI@7=Tahm|J^HQ|NKbCeQ<)ob4ok9P~GD}JqH`de?jc?ERD>K!h zPbJzIk+e+xSKp_8M=31<5(oK@Tf7{c@W>CDcCmt6_4(D^m}&B>LN)wT+vxS{vz7=7 z34%NcZuGWNwN#UX&*~4iBh*(HdnVflAVO#Y+k}MIKRdVBT5z=8RIe_Mc=BcgoNKqq zuPin#<#@)6MUwq-vH^J+cuqUAdhJ~@Cy$4mVO+0GO2r#9VD&=BZMfkd50G*rNzxIJ z*^Kn+tmV(!nuw_7!2#f|%iX>S1IYDULswKs3`#PvXgQlb`LPXof4omJJv<7Z-?7<}Yw6gb;Y zy}hTMu8SByJAtVHQTvR!TZUJr@rKV_-n!B<2|pIS0U=K-wYMV}5d~{nYEcHd@}`b+}Pq`FbaPoyfo><-Rm?cXI#z>f6H9XVq-`Q>Cf2 za~akHID^yZq_Q2JHGg$@)avM+5{3_oeBo?KBh*0x%H(btx4flLZ(c@VkLqc66YWtZp53+Tj>UwP z==UiizY|ffl8A1FpaLTCbr+le%L6CF2ndO)HfXhJy487VD3G0_Szjf+53do65>p}n z0^&+5ZL!W*hwJy0_1!Vedy9|N497)r??CRN8*^T(cC{8!?Ai z;P-3@&0{o^lv~)^li2?A`aiYgIZLjh=z`T%8cN`#pG;;tLhcFj*hsV!eT^YUU z#+txC9fth2yc_WC0{SbmS3>)ITbOPJ((V=XhO4j`I)CGo9yo@e>rg(mFG!NBt(o}g zO5LlLq;Y1Ryn=sX+nWK*;pOm9(G#Atb*#R8pz`g_AX>giuqoC^_F=p&r92~c5x7lp zlA`I#A7&uTGhPN5YY`)FANxEcrNW#cz(>PW{yS^g48X#Lzk!LwetgdZl1AkWvl+rl zeAfezV2&86!TaC05%TiXp*QaRC)4}SI{|J@WsLO1aEH8WQ1X1$gQL6%W|d7SO2r%M z{f1tK0S8ccak2jOz{dlihy!Ub6#c)8Fb}LCn~2CXwEdJ>`ikA=ryxVP&%8UN<6H7H z)5VdN3eZPwLgWCwW4;`!GVb{+B4wr=%-u*{NoLv%0IlhVB1QzCD7q#*dnS(sjyM$j z=oB1Y(|0W8$q~O3qq?m9dzMm~hd83_&$2%6J2}!tAx&u8R$7UD*%Hxi(s=?FQg!)O z+Q0qw%KkS48G+0nPUY~7zK1}SVaOv6J7X7?`STIb7I|6P1cYPjU0;Ccugu&uYSij4 zpO|6T3JxNfB05I?VUMF*3L|n9*8RJ<1XOQ@4vdZPEWT&>>M}tAi2`$*yzdJf-8|UE zPxoGKtvC?CZUN^()%Sm*>S#^|zD3En@jSXL%zc zOo`c^%RjP3O@KA_<+9C@ls}X722YOBWaH3*pk`;I^6+dy*-bo6#pdUu5O* z0nG-F`Qn-r2|)}V(na~XaCvyfA1ipno}^G-)KJ6o#Uou|t?1xBU4$RVOp?m}*smL> ziP4{G5-?k&sc&rnXSCO=^VIQ8BDq!Kr)vkbkS* zUXutK#(5oWN2o&7X=7C{>mlikbn;TxkDxE|RlQC`TsMQ8)>ZJcbBQG0TlcjS2#sJ} zqoZQQ*61(~r*J=Ih@IC>>?k@{;6=*aJf^Qfe^`LFHHowgayvavI)I|A>nNc%Dk!-D z?khv;KmXh&0-$r+09cl*W zc`LZ!ruf;KBsi~AbEY&-z)>DQBq~!+u>eqw`Rt{u5-%C8;`3JzKk6G`a4oc28~jfK zX6y(Xk#12nd|knzI&*nbh^U$$U&RgXxSREr|Ug%IKk0EXB+Un{y$hu=qkCp3-|I0y%>) za5DL>htR7)R{L5y@!*WrOci;WuZm?254B)9%ST9U{X%}k(%cd!5mEw%qZaq(@ve?R zg0fz62=&YFbW!ibXb>>ap)Flq4x!K;D!%!ZwpdT?L#;j*gZuNuUe*MohJiT!O}e_# zwRAe7Q#^i10|OuxIg%^GO;dx09q2ujlD+)f)dt_6OL<7<7h%UbKqfhRj~l~1}HUGGagpt6lF0PRSsSQej2`l3d5lc5x}`@7S+nq5uV z!LGm;z*Y0B0}~vUr19OYL|(pp0#a`SNQI%AF9Q%$TsWpgwMH`ANZbx& zgonhYx{S;9X2?FiyG+e%x)AB+h<+B*p&oIU1p^h~4X*A_D@W;$R?*)XLX%Ca)a^2E zJB^y^n}^Chx+4m|g3UuONsPi}+0cP01!kl2#_rgrDKLph*kyVN*y6QBhrnXUbb<}b zGLt@dky(G2o(t(+@ZlmiCF}Yn9~1b^|6blz#iL7EFP-gUI*BypVGByw1~iz~TM7jb zWC3eSmFRnX%vu3$7Sl{JT;;ke)!*KN;v%pFeq`GiUS!xX4nqJDEeBi6(EFt^OyyL?;R! z>PUgeM`yADrYPfm@ck~&5;QZ!5*fWV=SO`B%|~9RM1_0k<@vH^vP+=(7g~;`%ak>x zg?1qew(e9hkYgfjarq;W;PgmJ=27JBp57$p6NS-}fUCSZPu;t^Iswx70v+W0uXJ<* zDVRol9HKPsr96ysSj6K=W=;NtO4yq=_hiC z$86?{d~&9A3Nmiu*EdNPf$Y+%m@;;eg=bd|u1-%B&2Kl~)7+0lf2TxA_>n)?bv>GD z3kgk*Vtbv43Tzq21$~#!oyhx0gRzO0aG^)!%O)wk=m=l?QiX6=(#0X*JLG+ld5?1q zQw*oF+-W+;4c)BH#(jv}MOI42MjG z3zzHEj~RUuWsWV>f73!KHQ0ApM4$`j~KoaD?f-f}nKdoa1q7G@= zU?(_@Tl-EucSApVyiMaiQ9_I*q04*{v~%DEwIo+}=jrgtVX~1-xck;do@|I`tucZ# zCSIb`m3WlAbhMKgQeappUuQd9XYK&(iy=o0pSPriUbX;%n1YC;nmb*&B4ZFn^AN-7 zlbrcVk7dG|dyP@VSsc0%I#3q`T0JA|1BXQTlERXB z_gq8HCCtcBj`K?dQ>8-UF#uE2O8{~6#EUn6&#IuFsn`@RM2nZqVIt5@fF0kp-m#MU z1}ipBWgZ_4K{7A!wy>?SF7y3SqPi;F-;^?f#+y08`aMkUH3*mTfz&WxTP zJb!nmc_bPjsa-b9@4pgJNn{}|w5>qLX(Z9WN2_Ao)I)uKFbLj@i|kPALJ1W5lQ46kQFdKFC@KQEw*4Zz>bepz zIc?~=KlA=F{hd`>)~z(r`i}MCa556~7+hUvE)ZdWF#{u(B(ak91l9~R%V26r_GxXz z&tEX+vWd5z@@bWNwDS-7*GGu56epZ_@?}naOU`uul8-7jG6F{$A-Bw41vbeu8-L!? z4kgT6s-U#93IVh ztFP`8ckR(9#5gFm_y7Cty#Bm*82;k`2|hnP|57K^6Lz6W0%i%7{_Ac=y+c-;MCY<= z50y>34j6A8Em0^qb%T21OggCXrvxu;U0+TPqhjLmE(a}oGFl~_*k?lbD!-p%70oUz za6T(Nb&HBSDMdKsKb4R54g(St9#gm#D!1uLeBp{m88?q#6Q=;O%|*J7<>AOl%Of1f zv9g{IU`2ecs!oqSt>G*Yadvi{!g{WU7Aeeo^YeFN`>wN(pg)H(+4}By#%~9-I%qE~ z&xje*fUj`@q-Ahj^?|JZFa^`RbVbD#!+vkicXT57$SN()1n{KRjRWrzEDhMGpe!k;FS1(e^md z|4-{hM-wQfRI5-4^M?h3VB3Y+d6DT#Qw4d4>T*M~OoTF)zB_>}TqazVo!(fX7-%qT z7*EXachcGKluHDZ7Kji-S6l!>21#7^qR2_0oj5MO0dR#*Ss#%Mot`R?dU|_ zZf^2Ihd+10xg87I`u(xw^XO#|d1`51lVhoq>tI!UnUz=d1Qx?<-6(O1uqG;!cv*PS zS}I}>dN24T;6v>$4LxarAida2=JlA?N8P5O3X;Tm&+lIdkn^Pt&h9QxtJkA9S<0W^ zgj0cMFpnSpTwv!GH&}kZ^CAzfI7aVV*Xay;4itWp*Lh{2Qv`Z`b9$fnj6DG%?)S$3 zPqklrgaH>%Ab4W&=>UtBu^y05OIkzacOI$4(JC%|HGCq9qOg<47CRBvj&9dP*2P(J z$@Un0Vsw!)!YECvV1dbTo|vnaFzZE|&EwTXkr108|DJU$G*UdiDNN9_u|o%mD8e49 z&~`ntix@v~TGIICRI9B;wWYULl_EGfpD#%qY$L6v!>Hd0%RG*CzOJ1$$W$Jq*7E3b zKn>$j5ShwEt|Nhbs-idlOs>+N9v50ZI@ICvPs8MG70`}^gy+{cR0e6`7cKL$$H5^8 zDZ4+MPl-5%s<}hL4#Fj?&d`HBcp`0d5>lsAb+q2`VsdgMuoebpq7g-zLe|Vw4dgTP zJQ6VC@oCouoJ7Bc-tODO zJTc4>tp^Xtj=bK9(9970Cn{`@Q;b)whxdHBPD*A^fOR6FoM%#h_H6vSt!^?NZH(K+cCK5}P;=f_QH4(ph&M zMng2!U`nO$@^3)@)As{lR^If*QKZ?D6!)hOd6mWJ1OKKRqO1X`htaFFG&#A<0%t+X zAEy3w&9Y?Wpc=PXRs=5nufTwHt|&2nG~w9(&z!{5JjhZ9hZjiX?g0x=n)#EFPABepK!New~>R%?D6nI_*x1Gz4mJgjN!DuAL%2 zwD2Ug>_#jJ*kdf)>5n{4A>ipWx+>`5ntb>@EI_vk=56rKG_PO{&|^!uDCGw9m`lf+ zJcU`2a~gV_69AEkx^Oe4ac)G5PMAxvD@n3|@{Uxz@GGA^rdx%s8EC%bMo0>sX%o)~Tr-^y<`TPdNUyKo2z+9(MFKF*wtuLq1R7T8b1k#FA5E+H zm7HGVN$cNNois7G5V1EmtyhVvQ_IP;+xxr&eeg<0njA4Werm;5m%7jEu$qj*bNut> zF406^6YA+$EUJj{f9mS>QPa+|bz|PwH$1vo9+AvMbuJvth6rCu81KZe2wEd|d zrGyU>Imj*F;7if2%ORp)CjGmQa2Pbv>63HnqDqCn_-gclBh=((CO*?whDZ0|hAP{U zrop0_EeW2mfPB8rPkS+4wb>}){mdWNYC?TK78gP3Obc+dZB$eto$s~CO20#W!HLw1 zXU8Vc7Wqf*>_dBJ87l0BNQ~hI$RCf0`jH06Xq}2)`E>szETnL(U{Ke25fS>~IPw!i z8%(K>{S!eYjncyP*)om$8e9Z~8J-;0Q~ri?gWOPPyPtjkByfX+TXW`JXVN{{@HI$S zDukGC%tUM_(Fo&9?0MP`0U0&v)ROaWq2Sd0hz?JYsUC!Qc~yB~U!wexEZf!K3u@1= zng`0sVYH-D@zA;<(^q07)$n|;bp$!rq;eFg@Votlj5D23iJgZpH`j^a=<7T`3u{Gx z$Qxx1g$bQagKDucVv1arLJ~$q3gz~7;}dP>**O1x`@ea(3vyF4M`2D>l~2@y!eJVO z$@hobyyxH%2`dSJ7PrM1WQMFnuE`B++piAq{zA8J*&Wi2p=}YFWheD$$%Fl_jX;LyJn* zj`=Ell^DZiN(1T(X;@%(`|auZe^P*@FU&u4s&rfxNzYWWrh@akHG@i$E0WPM>TttS zi_$c>S`SIC#$BIfom@-sWnrU-5m#k=p9TbsVTvDzYLU*36wft;Y}V;1Vo%>t$u9~M zF3a27%cRry-G~}mryveg>k0YGhYV@+yUV1z5s(Elr<5XyBtJ2cR^KEqwSNzdd93ar z{8X8!khu>?t#G|1(KzSDL4+a8smWgm%*x|1vduer7W+!xshqq747Z##;f9dmk$eY| zxy8TroIh4bSj1_TT>JW9t=9m>8UdUfV*A=+Fys-ad0+ob_T)ap{{)H_RpLQ>DotK* z$JH7HZb^p0sjIfVKT-rJ9R>%G6WG2ZQEkqZRu(L4MLIr;n}^^wf*)TJsq8C&&_R({ zZKP*q@cXh+BAtmhAHlc2!yO{OFSxIKy)2~n#R%0I6?Lus868-{$L*02BZ(yU`7R-e ztpr5N64XuGkKSRj`nJoKs%rLS+vr9jAR8~euYo66+GA{DH(m#;m^07 zJ^uO~TichL097ntI=T0A%IE&ka-tZ8FR+Q(!J2T1J05(g$Y)jqTp9emS zSpRlxY1EuVhd`L-!CYI%c|V#A9ZmyYxU50?j`qu}3pzt6=h;=~83EU5j$0hqNf_7J@ngYQU6ss#;XFki98mpEDqWDVanTlFNb<*tusbDlt(jHqria zvXYLsFTIQ;W)xjr#mP!!wUjx<7MN}&Prkzst$kpe`Ri}FE%E*mqH@UxDD;*eSz9xT zeTg9EF)t|y>X zXv=oAIN@90VRkAoDQEs?>&#;;Q_mGMEPLqpA)*O{h!X|tZr?f4)fil7oVYd-AkGOd zi;N_`k=BNSeNd4`DQLDJks*VA%rS$tl*5yloA?r@Giqc<=Aj!%Xu=c3jkA;0nEj1} zGH#5*blUUOMO3)i(32l2xv|Yh8!Z{;UQgpL~oz@aY>X`dH^$SZb1ybVL@r(DOuqPLw*d>&zE^8Hw?Dv*m2sbSNF=s$@HKORYlRm&2J)%o4`c<*i*KRO-=B&s@#l>d-U=|`Q){EvL|Mybv7 z{>X{7JXEmJ-1~=hTi>bZLv~RFs_$>_+nX&S!7X;UiC&WKe*gKPDbVK+{eM!0B$Rbr zOWIfCAPz!L^t>1x>ysdXcY2oKA%RI`~}Gk&e?MFlh_2i@3AUN<=mC&97$}Xp>(9w~^KvJCUdrop-}s@`Pql z@7h~_!y&C${`8Ay#ZXvIxL`!jUfku~qlO2XzL?&NyK?>j6L2a=O4*CMD|UOyClM=s zdDDS1U+S<3{mZ+h(^D*A|I_|gKJm2c`Vf z)tv-4DbJRmdwy6S8%1+mLa~l7AC>_{(1fQYvI?FL`rt^DaFKxW^eeXotivN3GZvi2^2n4A3(G|^RRo@2JiKra^j2PNr$vj;4?|a938I%TzcR2;e5Wg# ze9?-VcOTXz+bl6q*je%Emrpxkq*-W8j(M+~lQHl)9EK+JsfW2$Rme|FP_Hz&#(uf) zOuhZv@j$v37mI*ktjKn+V9`N%>F##E9udi%TH8Pv;rDGGD68=H1G=1u{tNO`hU2iI z;P}p`eMiVYK6Q&L*q@*JA3kZ{8J8Zv-(_y7kqy&eI^m*~-?Ck~a(pApMaf`XCe41x9ksZk`bWh zm0wT#$(uhT-jxgSM+AV+Lq>3H1NJQkl46bt2c<<4(VxAq&T|Q2aueByC9(hQ;ZY3q z6dS^ADJ3<}-dAS}C=ddJAhfe%AJdM%LM9skz{?BD?P59Vzgpt#V+0s6N}5iVJE z06XIOAfsWviipyun)A4K2%?)W$;O@Uez^y;lO~6!6Yc3LC$fyGQK$jwDxek#R^vwY z*6S7#EVD3`Gf}TnJLIWA&G^)fbIY# zGFH!0p_8k642)$q-=zYw&U7q)?by}(uhrEJZ$&S?h#lRfZh;+zynu2rIN_V(K2X^jgUgia(3$giI0}L1Q{5*WD>9#eFdp20PJ=^99B6v0T>h@*uN`_OPwk0K z$eXK}PUR9EGZol(q}sx|;L*I#D>0A8drcu_T4ZR?Bl(Y_C7H^37i4(}&7I|4lnW9i z?b4j{T5_YTu?toH`9x@75J^UYlqn&mv()lorBHkD>ntrp@DuQ1K9-hU+SMw`-v`%u ziv)ev&WW^yJYm@)(HKy{W*&l!qGQ?hkujOy8yVk>b?ca~>N+BYDgwGSJ*&fuD5_Ab zg0_7lU00F!b_T{A40$oF_a{4`2=8NKxYa^V>~j7+pu02Ux`A>MYf~0M;;Z5X+)Q$%F%}5vViM zlCoXN8$bo0=V9odnRkJl5Ep`$9KNM`yj=!3#F;j@cu48{T{&_jQK--VxvlgKi~%Kw z`~KoA@e`Mq(hOWaKRvC)0bT(DcBC9$-6zY~<%#9v8&j&&`t>oyPfo(TFkw{H97$k7f!+5rgtT5k!bky=~)7M=}Lr> zD=j)%_(L$T%ISd>D6u(2Sa;ulS25J3l)?@_iQLm9FuK#BfS4l^lS<2IRjhBsRL)Z9 zwHxp*$GDy{&ODx@;S9`xC{(!d>*zsE$v!H%IcfLd-z@b~QCux&r~cTnQNKj>yt=!r z8M9qQ5td7`Wz6zE{-ZMZZYf;{=EOI9T1$qySU$eYt$&d@R~O>S7{*#~>vTHRQja3y zN|VU)wHv@Wl=Qfqj-fK>6Ht+X&Gj`U0d{BF&^bgVl|?~UjEMmlVnZCT&Q;t;C|6aV zElTt?lZ>kyIzcAxl76k%x8kv|^}ke}-4z~3rQG9JXL&=R#OsOdTwL)K)|ZH7%j^=@ zHSV;$5S0XiHIt_n?A2czvV@s29}?$(x-11uxkB*hOf2FwhE9Q`<|jhr7nS)3Bb0guzM?XqC(Brif22%NFNfD;_@Kj|<+M&a$+M@i4ONF0!`N z)dVqMWQmj{GP@EQrEQRn4++sk`6IWPPg?Elnp5T|W+x>k=AOt$nWK8n2!zP;O876X zuK`=eTAh7Q#Hq}Ye2nre?@tH0hesSj^)pBrmX&$*&}KjegoMlPNM(+)h4l>`oMCd6 zMXNXDy5|RP_*19+*N)hGu(wv65V5h@73%tu(iUh6ml-3VH^Ku2vlT4d+$KTQqgBLa z4YzuIwzAwiWPDi>RRwv5BRxemfD1DDnO9__Q%oQ#xt^W2Dh3ru^TByfhCS*L;i`E9 zF6JU*VfN&xt;LrbtG)6R*A=C&<3zMDA$sF6l{Wgo+R;SiJvb3E;UWat;*veJCt$21 z2e!ozd(tlD4?q!eJ=@Q{Nj;u%6o2}v-kSGZ$8ExbIdWv<3B`10_BDB_y$mZ6_jfLgAU|v zcbrjqdTk#JG&$FCUfur^=tOCSu{<~+zt5#{idhRM<@Y1DaqRMaG=}h^&Pj9dh>b$*@O)wMyf+`@%>X?c`&0?U3hb?7CmpCBF~q1%ws-T^wRPzSh_~ zZ3LdzSeNv^Ag&Y1?dbVBpHyq0FgVAGKGpCc2cwh#{ugx1JD+QA&CxHptx{iX|AkZoG*I?z%Nq`w)5^!3VZxS~fBA0esnQoBX>Xg9n0fNwv$oHCY#^ zc^rIiZYXcH{o`#1QK+1141Y??Oe12WkdyT0;`U=bF4rQM7zjY2QWf@Vsz)l90+r+Z z?A^Px%a|lYqQ)-1x%^PwUu)tXPY?Awc>n%WlD>W)?+es19QtUQmIN24hE*tTme1LA zvBugj)0x*Zz$ns=0>~`#k!>ktZJIJurCNGnNh-=(*k%vvb$RWC9Ol^LA-=pz7q>O# zMd4o3WFo>oHwV&_f27MKsi%(YEgCCC*XZWByTAL>NhLimzs%usf`7;oB0N|pQKXdQ zOM1;3kmeCUJ~Vcwq>iAhi>i~7@#dys9gckgDxw+CCDRh1r!>s)`oDSere5{dm;*<$ zcVZ_sEFyDKr49;6NaDn@^a%+)c50;1Bmz>jqyh^WyuCiVN<1PgYES)o_kpdB@{O9j z77m+9WDv(^shg2|AN+3u>UF-&aZ3fTcLcmSGShmD9hhRog5??(5-k9pRCF#pv75w- zvYwziaMZ>$ss^|=R^6G+2>IecUAFP5s^}5XDg!C~97QZ~4!LsEoIe4@cXU7w`TccO zb=Nr4rNYuuU%koq%QYavio#Poqt_%jAmeE&G>sdv=5;s|ZcQ~Ca0_{s$S{SYF2=yQ zL0qQkst3XTfV+Z=>dj`2d!9jOe{j{#cIxKM45HgJJGgc$CJ9;^W(+1x!=VZ85(coy ztYVU50@z({g$-iH%tSCQME&e{%$3`j9*eCKz7xz_xj{w#l(*LM!3w@TeA?3;$VzB6K|VsVX;CL51Tk*Qkn9-wIEtjH9h0kh^727YKy zuPfIsN22VZX0xpC%9}DzY!Js+U5|Bf0_G!OUvJG!rDrgMFe+WW`*`-co?tR01o818 zcMs~(xek#5&^}CkGCs5Hy8ReIY|^()HCcDo#ZEciSn6!~_KQP6Dva5}iSlM#2mUDV zKuE;x#m#N%nhWxv9P+`0bs5*eWKV!Z#cA$p^r@~&Kw68{4`I__9%*G<3f=JhC|13Rl*ktB82B_p_} zN*4|0%Z#tKf#|%DBf*tvNANXq4r6=|vIe~_wAN0i5tkiN4-5|`g1Y%H+LOuOhLt*Q z=q$mQeRgzp+Dv-RfhZipl<{p6JnMoL1j?~i1u61+oR;A@cj7@Z53Y;!RXmFCB6u*x z9j-?byIT%xv@epdT@Q~n7ihP4GrzI!9je@J)4X{{45Z;&(aD4{HmH>8I;5mCj&*#M ztfcG1-Jy7hP}E($UQ{dCI**D>1fncPmF!@W9foiZ7?|QgGTy9<0|X?+ks524hb!PL zB2{OLnmA2-A~0U!T+CPzdkjhP%oRo02U9j%+DgO?8YvrrR4e#c7vH2L zlMQ#mnB-n}+P$gAvXB+NCb@{+PEL%n0a=JTXUmp7p60SaB|hLtDZeKp*M^9VZMD0q zRq*ryy=NmXgi;5bq(O>w<=g%f)n02JdgwsRjW!rX*o6yrE^Sxn#MX2 z3~25{wg>yOPqCtztNf!F;; zMBe*kKHgv(k)9nlD^KKl*M3AdN2MTSj;mWjN8W_@03njec{YN&(wib-!UtJqoyGa) z-l61x2+A&x@{zQ;Crgd0G~sefZ1*S&=uOBdr@${~+d1pHn}vBfNeZI%?s% zBz87|cT6a~GltCjX%kYo48G18K^eYIGZzWWQ4wbMB2?1(ya|Lv#05{)oFos@MM*%W z^|@5a_tVXQNC6cav702GpX%jz6N-TNT0x4h&zT8JluY&yZHb*^ zoaV_Er7sg6Fpw;ou~M-5}=Mh#glWe6JREZGT51!BEmZhd4I?E5t6lY3_gCR|M>%k1GO{d zzpA-&5HAZEh`HQ+l142I;dM8kE*>Wb@si>YQV}q3-y$@RFqR)o)u;r z2qjE~?^D`?Uj-Qi=Kf7C+(Olbpd4P86yv_)hPV?pdZo&$b81BcE};k9-tX)ACBz4! z=r(!5+*_&RPRfwUFZ({}=_?1vY)9_gW>Gn31t7sx%&7pbTnS650zTS^Nl#aRl>@+G z=zybgNf}X)$C5BbTck+-6^30!=NY>1*3)Vdz{9C?aB%*rs^lv?fPAarjLh73$f?Jo zh5J(kze-DP!vQ#c^J2Nqn0~=RPnEby*#Ij%t;{BY%#|ywh)3R|c_;<+rpoY@BlxKh z#7XA&iGPnAz=xt%t`j)k3Jiduy^3UcF~Nq3B^R3i>hoW#1Cs_mWnW}I&5H?2Ofr3B zLF9#xEEZ^#2$|VT<$x$#X(=+Bxq|Zih$4TT7sv?={m*%Dlee2B00`cZQ;`=4#{0hB zfQ;nDWW;3pSHAKlGsy{-WZcKTnMqEBj2%W{k@Ex^vEnpfU=Ry)nHTef3mN8|25O++ zifnX>u@WTjUMD#qfXV$KQatjy3+GmrmIL*5UUw0}yDGcj$XAK~Io9A=uT>`;ng-@StPHjWqn1?1NeV26TFOdh20>)a|(<}SNIiJ zM?zF04JGp<ev&nGi{jYB5q5#V{TUxCpFhn{yGmq;BA0d3+1^^ zdre7L!T}=k?W<}LSP8Vp_JAly>KA_GOjG+mjTu*?TbE&s~)=oYa(`1HD3vs69O zUBq$ORrQ{=DoTy>+Qz)g0e^lL$uYtZfi$)lhPW!0X*CK4cjrkc`#H=M(&z7fn}9IH zRe>y+P{;1pQ+3EyxYEj{pvJX;{nR$#JvdP&1AHL;>}25bFp}F>c_gPoS=nX=-`+HD zO9Ku-W}ET4@=FxwaUIa*-TPeRfYXk|Wcs*iLO;Y?o^rSC55CP-|5Y!NZLGcEGSdJ> zc*&Hor|+^8PK1~JaHQ?K^K>y;B`OY~>DueJ*OeFiO!IL(hY(5Q7V#`fj^O=tmJ2_~ zuMg15z=2D4{Z;12ZFUFVtnt4?8+B3PH~fO^`j2Gp!88{8j&8I|4?JDv>&y}MV* zgSNUagiq})OPp(?`56Nq^LX5~MP!6pjRGt5rdgc>l_lA&bjhGxyR<{XWVLx}3T zgS))V{LC*xxLWsWAYbLiW$$7-L#f=OkcHiVzPZC}bvDqO1(|bpD=L(Kjta9vTr`p+ z*y6^erabPxt{TxQz8Od16%b`tX)=Q4_e2Swin>e{byqU;qBX{TN?a@`TsSpAnY&yHZWYW+s>mMcl>$GIFAY1;2_dJ*i@i>w zQnZ|?QUb+Z{glSXJQf!A{lQ(c&FD2M4G~{=*%!CU%0?9nPJ5SP?^o4@pYS+n6Eb&C|(xw!*XA6gHyh(+0R|Sy5 z2aEy~w^{T6+=xnARLFNJkzh68J|L<@2t{T!D4K`+0vYa_$VHVS0QxCVW+x;92B;19 zSV*260S2*XBDS3d)&xhL!t#R~Zy>KO)43oFAG|cs<_{Mi(^4vrA+oMGR?|)ZAhs{? zL(`2sk`Tb0C7%B-yF*upmVoOY%fCz67OO)*PbD?U21(nUZM*_U=yBeLRMDA61neZIk+HiN0Q<03POn6W*g=?&G6C6Z< zPaHXksbD@*d}T{~+bppwnp`V43vH*j6;NgrR0mCosSv+&R^yFP=KJ_$OVDms&ueAZdEiE<>p3_ zex6c6AYovL9O<%3=@B|ccOo0pPGiY%{7H_|_Dbbg_VjJcsmrq*CFyKY#YwQL^R_O7 zh(%|pSYp$8e_2;;Ewmo+3(P0C?=C7;L^5*52u6MQ; z$Hs1CEZ@HU^ggkO@YBdMa~5bmjYfDFj3C!3lTB${Yk`a>^v?T%Vpxfz9I1%L@J&JR zxK6(d8E|>(wp^84YkmrR7wuca^!`Bls^4In2-^P85+QO}$0M`6id zy-jIPYXr2kLrG}C3u#`Ee?%X#5*lanlL-;s7O3eEv8B^hM2M&o@`Are<1D{~h(;zg zds-awY1KvfFyMKe&X<3NWvmdlJFDLlPpMktA`u{qt~6-}f#^ICzc%>PT>k{13KZCL ztq;LdRW^a9Z1j;_hu2bMfq>Ept&JDv)7yMJtVJxe2n@p!_?3nu%v~f<_~WlGKG&m4 z5dj4#BGfwqG}E+HwDX9g@6-FU%=<^~BuueUu<uR+Xg|s2@OwdXb9^9MnwEnGc9n}TV|Eri z>Lp4TjWUY1T-9RMn5Y5qxR-uvnNXORC!aLalV|oWlo5Shbm355hO_>@>dvaT!@={|Jn(( zTR7z9dfK!z6ay%LJl=m*6+$Hhkijl3TQN~bNqG)Z=F%%?dX)ew7J?Ob69~;J566v+ z7qI+(lb9hAVTk<`(z=l_r{TB|P>uKv56aSnH5=E|Z?nF=#_A|es2nO;%u?Ij`7EuY zEbSmAETndqqbV;55X1vkH?Q9|LY%Lh=SD8WT|lMP$+~;e4H+t9X_MFqv!)z38i1JM z{JsJu@=)T|e0Q5T8GxiJl!!^&ONP)jh=5`|S;RiIJ4H|ocah^D>^P0zO@kzK)Kn_cyegen*1M-bjSmu=yM%@RFMOj$#Sci zBsRsy$T=6HT`!YTJyl@~7rD;CJ_Ye(EAH5-&6L8jv`fPyy1G zlQ;wkNMxx~G}#l^u(GWcg6i9>6tBsH+8vdw@e3lX&P%;(iIC-rowo|r`e=_@VilX_ z0e#C!6aNs*oVE~$io6nG2XSbnVXAmZ9|CZwIQqQegLhMTAIL|_f@Ng#7o zGGL+uaKbDkJpauH{i7u#knq+8Kx1S!Kp`p;0G9O7S=<@US5Fx?ms)2@!96eZI0> z*8%pqAjo~-FwsZG3uVZ(=-1XTiGiUqeY0 zMIOCtzJMg+dK~)N>(_6qL|SKR8$}$5&Rr?<17`%U8m7gYzfKFaPd{>EM(0*AksbUm zy&>2_CwlgDk%tpgk=JU=c9C<7*6!ClZe~6sQjrZdL+j&D_a>=BI1E) zBA)H|LLd3TK0{lSktGWn-c|34uZ)hy&~cfdH=yZ5G1ka_2qLO8Q1?e93OZS+k0{c7G2!5v#(g|4x~UI=&{3dgKU9^5 zi1KXIHJ8#>4$LZ(*1;9apQnnJyLuub#d4R+&zd`8lXAHp$dHum;N5p;saDjwTYn&4 zyVlxjnRkU|ZnJTqRj3G`>IC@;<)eymh<%=L%GSY`(Ny8D27Fhzkv?5&*p(2zMkux!p7q50jb!+c&}n6P~6hZ1@^< zxv&rCE=~nlvc>RZ^@OVe-0lr=-o!K#OB0~(@o_JVt(n-3yoXEfSUJD`&DCv9Jz5vx zcycPjAby$lZJDkeMUv7O!15|)bF+jSBM;ZjR_6GN~H6?vQD!VPYXK| zKH(w}V*1@#mXt~iRs8)sF>JHox83N`%oGd$zo`UKc>rw_Hm$+#rE|s{GwJJl&&HaBP;PIZxjJEREVFI3|?gJRfH_d@jT( zhf;omVuAfmIqTDamyQ8esk5RD>mdh196}MD zr##7~;f+&8>TL|MR-uBPS6%}y?jjF|tuwmj5h&NQe;86P%o#VIs=<2W6c(lcDfu>X z-`^)2f+wR>sDna(%eJX9M!dNjE@-M*YgNtP;0=RRDBZls={y365`o`JipD-~o*epibZg9~^X)%IsO%uO? zm*OvyqSf_N1tFsApnZ#>Z|%D}6BZy#b$%cDOV?JVzoJzb1tIFN4$r5q~-y{Bn8! zFaPov+q=I6VRE`?9qgdkcIIy<+~xJ{C;1V-J-fXOXYjVTUjb4tZ$G}YU0wz-bonhK z497e1_m5XE&(6;;Zf?3aYP52^P=l4@ZxNiF-d)5h&z}V}@p5VA`r_To4g+zXiSfb( zT{@Kk1_Py85EyvZSpfU)L7gwCy{N;0++A>chEf8! zC+bgL@Zjxls@lB51q55fRWPe0u=6GW8Dq#6S+2uc9h9PO;Gu}G%RHzknILiwrB*ld z+*wYhBX!KW0d3WzU`6l~uYdsBNJ%vFksF zT>`&ZJrGkZP&yWNWjU?vDu+~9h#YVY)|RRfVl9t%0(2<19;E}A(sY_O?P}<;L~F;d zUnY-^C^PZS$NYg`t*)=;eu0G@OLMf#0{InD>&dVxj@Z#4@!g@HI#<^7IO=#sra=B# z_A{umD1??0PFH#B!gSkVN`CpdUN~0c+*ZL$*vH3YB3xCenwgfeF&|Ooa#2%ZgDL54 zvHVpkz$%-JN2i>}*A1Z@7Svl-1%|RT)+i568&}_|S<9&XG!f<#q2=jq#hWoID>lVB z|7=>@Vhd-iQe&uBPl*8)fDQ${=Ea9z!M@7O-0{|Gqiex7S z8ks2?X@8%TnA5e26i?LWjc7%nsJStY0cE5h&KBuNNQ8*2V^9=`eKc5PCOI2HRRF|T zfdlmRCd;JN5s#y!ruk+~s}%)lOT^>nhRXZ_k#7s0?J`qYVfz$MzUxHJJJtufTwP}--a@1cjp4gc&hek}Sja|6iTsk2Y zOI9EutA3!W^O57$!Q6?3PHAe{NWd}F%W_&qe%~ywZ&p5I%~N&G0ZX7%OT!7Pyvreu zZD%-fFOs!UzG!DMp=@zr4rA__@t~rzWw{cVd)tRRr)^|$T9ob5P97ww^06VIS5?$Y zi^!$5Ka7kNL8ULVvIC+;u3CYlw&7 zxDqI>lJ9+yl_EYN*8Z|*V(a#GLq3?}UC1Pn$9Yi4l4SP!K_HY#Cm1LfoHfq%s4yyi z5FGSoJIH`|M#?hrW{{9vTmmW226>Z`^40+lMM|BZ{V;OW17%%S-Z5j3*iZ84WzET1 zcl`?JJr1}lm#nIFt{?Ba)~Mz*hyx*i5fK<*SZP03FS9A>h6fvM4G!r~w1L{eJ>qJe!>lZH?$^oxH z9+_rNxbBchcZH2oP$WPS?H>uq1YG}U+SmgEAp=IeFT>32wZWJIE|tPpBvc*^7i3gy zfZlR_`Tp$YR|}eNNa~TxPm73g=B3{_ghDX{J6#v@zP#NKy2aHb)A-fd&4tEm!!FVR zL+Ip3=QhN0<3!nR!T!5CU2cg3s6Z8EHqGl7U$(KpUd97xQOTA=?;yOnY0CZx^waL90Bh6c5 zL!SHIky!WA9tFO;iB!snffElUkD%)>NAhh<4sG@*ED)4wmLrO(i?nwxmQm(7#mzty zjd&pE{d77!$dW-8((^!zPzK@HKq=)kX;|j6N0vhB<-F6-p{kh1RuCDG>UO z(=5I{ziyuj%9kJkMRLy2pW^xAFN;pL_T+lXGYSJqs3<)RW{W#j&KuWWr;y!y4E&be zGSsWk*Lqsc*1iIn)Ssd&Kh(Iqa*@eoR%y4V*lh&^a1WTjp}U4WIDQJ2n=_uCwb81L zTZdftgmRquWq_^jxFwDXB6`@kx)HQm+Lnr~kV>PP$3kW_WZq)V7ED_7?9dH*O6wM9 zA}cw-`%L_MqGjtC_68lB9p#KMyAc#y@@*o(Iu;-lqy7Sb+yffj(%vzJ84W0fy-eQ4DuqbZk0h~Jo3h{EzJkecA?fVUpTwYoPv#JwIve{1v%Je zkKZ&J)Ru(pD7wDjpH{)z;u{2TNDOpJf1kV(J6PZ)^=SM7_Ts=7wh=;o#$IjTpei9W z7Im=W-FD;?5Q-)FecpIGZ|GDI1Iw+teBGOvRD~%gdMEf6q($CjRoj}fi3P~-VtVZe zph4`GlEJY&eHV-?9Gpkxc|q{0R28aFoRZzESxSN8KqDawyPd++ULb}8CLn>gaXFpw z$a2FZ!+`*BF)l>FqLX_6h?;{Os{nA)(|S;k2BIFV}ph3uJ~Xl zj6Co`xWdXUr%W`DfzwODMHl3v5%!b?bq@g!F+Fx7cp*pb4}wBNTH8#sL-l12A5?%) zG#H!1ULHi9>X^p?vJiW9o`dIMz-RjU#l<)CKYsn2oAkFoQyYCWcOrQ4FI}92zS-lo z`1C(Jv#~Kl~TX)9vf?x9h7d1j_8U9t;X!^brtJ0e}lBvb+zWXGl^E zUR7)BvLsn12N{!Z^N#^nwI_)!8B~`=)6%8HlE1B1*5xR!D;H)uNEX~>n6^^pWLc#w zjAb$2Fv;A8-&Xx&83et{f~3#SRbg3{tKqcYkprLJWG98}Cfw*%dNVANVjY<7^N-w0 zpwEv6pVQ}XCSbMFiCe0Prcox$5`MOx;t z7DdB^^D6x)1r3m(llXJBNiGA;cgol_Z>wUn%mNMsO*xZS>Bq2!7^@nG>2tFbdaTqq_I-zG}5e1)ixJ4N5-)7K@9aS<9BR@80&93ao5I8Ay*i+K1 zx|~BX>XF@H{Hx$`cn|3E+v>F9#tSf#C{cdbz&9B3$M9RqINGk;6em^XaAHJz_VdYS2 zK3oNp$PFAGI&=11zhC9fpaG~rKuOO@xhsV3NYv>5;MbYFO4i9AlpXRalZ3vF`(MH9%7{vJh$=ZI8qbz0FV~ zFd*b#3I=|g!AhjMGVi$ryvhU<_rh@`^!rsNuCP{hKKOTEWmumG>{h*1vx&G;U6jz} zhRe7gD*;y|bO-O|RTqRA$b!z5%ptr)tRkE&uQE3cxd;WZI+!x&MP4J+i!n0P>+lNC z0gxw#fX|tC<%dhmW;=VEeC#WPHcU#M^S3Y3whW7~KuMgJCoEicI67hbd7Fu&(XksJ zA)5&aze*IcY{So)$pkqI>)`|aoY^VFrl=-vo4i0$y2TpFnSGTPQ`WV#eO21tWfUUQ zlDW=hm7zFR;IACX8HUT8=LW~cP9u6>Wjc)cb%yM5(0*zx?#lRBRaACXVO95zu5{)7b zvnmBEV`~Y^a)^-iTwdYnE4U4&mVbp8BSi!vT4o*LqpZ>HXm2xz#1Xc{ z3&0rnITI3;lJlCxc$@by$AiS85#1o~SBG8PdXKeR5A7A+19(?_(4X_dBe-07*QA@@ zR9oT7^ca%Ygst#ZW*sL&lHalSNdqGq4V!_qlvr)h_qldxv|@YmL;v)K#I4@HLO!0$-J4hu0XkNG8>ue7sodb_>7n@GNOMR@#ljT$Y`_}; zT>emZ%W4$P&`#hH)y=(n!1%YzTR(usR8=z|HgX1~%^P2eWr~;r#j+yGHQxYNk0J+z zTReJ9jgW_AK?xO3>0PT5VnA3&(xAwMN9Kr zVycVONW^O%(}ZwO{+X%_$|X`wFRQ~uyaO97y@gmwi8F#70LrLO9IzmXROYe+IVYf` zQ&!q481UWEwhM=F`m{%&)yPs-eDxfPa2?>ukXc|#DYMbi))Dyv(}2{wx^BAUz}tjIvxf^0)oFfJE%U2>mIf%?+fkC= z7NvN|F<~Sh(nh21Zx7|_NTbQ17WxzGMBMo~?LUetGkl~QU8igV*dlNmRb~{inS#ar z4Ev3qVwQPFNmCZ-%8!9mDZ)lgH3cN_cVJ7`C3c15YGFFHchW4q8g-V$^?bZbKeP01 zi#j7Tn=OS|`PpFi3UJDAM@pB^>Ksn<^?M9e?7T_?p|NOk1e^%2+&ZQnd-c?0+l~c?W2XMM;PkI~5 z^ALDi#IomIX)b|NaUA!dB<-dEB>9^~a5vQEr({H6>TGI(tU<3A$;Lw)zPlRz>vt6+ zhvD&Tkr+53RgCrew^^Sl)!m%$5!ov`X+aiPCZf8O|3&c@`-E#YO7wJr?&- z?BmqTu3p*U%i32CT0`$$S>!?VvxE+%vKq)S6;>mJJW15G-N+b>O5l-MR%Otd&>D93 z@QgbKQ@4WulspX?lx35GXge|=sJ1tb^$PkFkQ^`#Eq1(LcljE(5fw0u9dABgR(4$5 z--~kE^nj2&HpQZ&qssxcaJoBP3z?tk$;f2(zEW^NBjE!=ZG-enQ5#u3zMyx<) ze3^6bHNa|x-ko@p7~PYe5bAEz?di6t1M&Lhs7&uiOt#x%9COW@Gq8#P#`=CvTgavT zWWpz1j@H~vxHz{1UADDnYl}wt-Q);rrGFsf`7PB^_DT27eo9z~I_Y)IL36HIn<~4*`?W$l40i#(? z?MDO!JpeD~19c534}gBYoRD{k8H74Zc4T7;dDr~zWM;#oN~N@>wINT;HnH}`iIpP% zxNnG4>T<~}tD~XO5lFmG=c*Fa%fcGd52hlOBcLb=1_7w_51~n@kd&J>(Txr*UWuC) z$ON9S3n)Dy>LMqp3{K8Pn!(2VDPDIC{)Jp2%Cy<$RTT81QdXdQI)u`A#%hiV=kFvy zY9ICs-ZZbcW2DW(77F_^1ZsOkOXoh_rLvYSow$c~#!lksZj+JM1R+z3U@nEgOI+@X zaHO(R6e(|(WjvwWkGWk!1mtmI&eQP_-J101H7Md^&gBBNkXJo?vaIg7p%p!1@hy!+ zj9|`sIZ-z5RH+nK+c!NF4CR;vEa8Xtl!j5GHa($1K&F&M<=)08e4O$N@I&HqK~$WF zam#6y3891P6QfVuP||_s7Rz$Q(h;&PaWg-yGU<`IW!=*OH66Nz(uKX>98fYWcvVBk zZj}{gz(bbA*uD8q4530sYoT+zU$^7>&QM`JfPEn)&(c0!hkpsxMJ8lf$@B$Z7wbvf zJY%Sp7nNocI#)_=g=?@b!n&Ise4!X@FV}rn^h2R`k(H?rRbqw1MwMI3^EoxO$MP=Z z#eRxD>IPq@iZSm-(f1ISxhdgnz%1qKd5|Xv1;e4uf>`8t`U315EFm|kkVHwuswBsL z;ws(Aocsl#Y3v=VN-or8RbnoTAC$pzHYHktHWa!tb(qEeNliuag~$LAX02kj&X~rm zPVSeTlD|+db}z2{pIX@y01g5D-|f*nbIL43h;-$kVO2BM7t}|n_=Bz>)`GW zLU6=j>rPq^ygHWfpt)5_G#8CJniLKJlaR(LXG5h~wuBOmnR-47JRdpg-Rf0gw(b%u zQ(Cxqxe=r<6yB!&J38ODL#52Hce}_JT|0jO`X*pf3lqNov^al6n}*ll7bS2tf5FlV z-cZ7G@N@n`o@>}GI@L6PA(s{6xNzFSA*qkRRfBKPQ7SQE+>Xi>BlMiU#|KyGgQCfSZz(%G$=`KL0l7Ca;6vlA2hlq5uDqNG#hdF!@9}^I!d@>MSX9M>HjNz+9fJH@&id|T}u>rtL)7r-+O0)N({a2@QHXyGVA z5_g3(4b~K(cEwQubz70VTuucAnov;~GN{p1lLazV3B;*)j+T}UWcFC~8+uC_2s zH-Jw)ia5niq;_}9k&Hj##jf-hX_OC>oZre|Rq!-qUytE<~+@hHUOCO1^6aqZl=lRFGN{S|C5O5Th z#JJ?P+d~OSNeOX#4<#{;3TDNLOG9YI?G~JZ-r)K`tKM#oG$$Gry)w2z;u6tN2M16v zx^tikh7IT&F!J~)I`n}mz&Cb}6&sAGh&O!%hW)4vty;-U^wkk>@CA${q{QUQfw~~% zhTvML`*u}F$n=eRU;H(U1>O3lv4z)YEG}p!9?}ysNNkPh;Bwxjb=h#Af`uDcI|YHE zZr=@R)FF8mcZT+?-*D&Qc?~T$o}@L~7=_j_4Gf4vgSyNc3hK#Q5J}zjQ-#{bSh>)s z9yuFzU4#wMNJ5;#V9Pcvl3KKh(^U_*L9)UJ%N1v@3WP4o{p7taQoLb`Hq z(1wpF9l=mNoCRTyBCjH#zPJ50X*Cl7RJKO9aq8wbukFax0pFjQR4XQWFFy4ph3E~d!BKg}b%Dxkk-)6I{lu2Ck(qcV#6Xlq|m zkKHn#Rw3Z_JoqgYAj`j{JpcKdDc67Ylla>YFC&eAY5wW^GpRg&ZGHfJ^v&hXZ3OYn zKJ>!^8X)~tngT%}C@=bd{rX_Kl>d7C{(bZJF0gR>`ugjui}TAj@DLt&y#Mavz1ory zdRSkZC21|Ir6IP05|M05%TkeLI+Ymjx^f zLZB63!oYEot)717l^6IB6~z+2u1I@4=E8`Ct>x+lQJhDD$COT{>3XyXk`Ol(h1H~Y z<+n*u-s6Z(UQTb1Wj~8sKOLNO$M^&n$W zUVPhoB#Pb1WazW}8jGAv@4#tTTkW~UP*Wbn8cadfTE4^jLwN$Px)ce!gw# zxh{EJc_*Pp>NReh=Ns#Z^NQ}F(K%uK_gylKsm>e`fr6Xk+uz&f) z)3pnYn@%H$M}lfc!t&fZ zhw*7)+h{sP`)rE76xu+MS};_+QP*LU2<6fNDVB+qTM+B1AT*a%9({r&+%z^tW*G3h z;bp2gzg46QD7yJ3kKXgg;z(7ZBYMwnWre@ESgAMfO*ekdX%b@gY&kzuM@Y#p3VZk6 zm-$(EN`ytupS?)W6mkty?0Ehxxm-8JqDjdl80TZTUhvfBNa1VRxD?W^zvS561Q7tZ zF9K6$W69r1k5LOq(m^mAX=lZu1nmRhTtz?JcRUZiA5%l6Oh_ z%9I^>Ut~dqCw#SWcXm;OS+)dqvw%jv6lUOMqC$~mZ_tDD7M2&QvE?Gg z4!$EUXZ~=dJ`}ho7p2RybiPS5k6iM5=hK$xR45At;Ur0zJPqz)0o#F(A&j-_>AfXX zJ2FkjOX?1g9N{?wyHU#WZWr*JFTVO>dpCNHKkO|=7+*-7XUN|!fDq66Lcpj}&w`>T zVbAMBCaJ6&I#97kcIAS*aYdGPH@2LGWmxWF5G*8XMeIx&)^uvXB_ELg9e^M(3jil@2SbSBy7d?IH;RCd7s z2oOsjlqK}9LXiDf*u0+d-)W+9(mOV}ygIvCes}TWvZ_ONeIuNA9rWT+jsgG{K?=$1h0JH=lbx60ny?W?_`RMliVO(duGl1qGo}4LM zpul(fP%gM4+z!j)=`Wu?i_vxl;m9GrU8KY2^H8T{q4Fq)6W}vkjm5b7tS?5wcZj$k zh=kB+ux#f!9qN|u6J$CP>kR}3LB7j}y8~qm-6{fcl4I{Xbm>cVZbf_rf=}1woRHgx zbDh8h%8$Dya#Sg^JJ?soa!AzUl+x#S_|ydhws(PA4dZDVa*(T1D0g?D*n-lQ;fsIv zHxyIhTS3qdS6^)`mSWM#d`Qp3#$GMt$UoF;cjI|<#2jUUl*0QjZtgp+D!=SU^Y!3di{Aa{T!p%el9QO%S0M7)usaZ#Fa=IiqCfAx6YEf8#LtNsesE$>4Q_9s zS_SuaptHSxQPyF>VdH$WMwQC%eb6@88yKCb}~;d|R*0-le5p{p;LKXcAr0%OAPV|A68 zD2Gpfy&z)$Ybh2He0y*9+s_<4x(A$RgetcC?YZP*(hr!)aC0+dCw`r?X+65z(`|16 zi#YU~N%=Ih`tSO5e;~b2%p}{JsO7pzLmzp3mnSO$SLKe1E6&I8-1S}>bJvu7c>b!02V)v(7zL<7A6z?fqpzCVQR$MV+Q?G^bM2%f&)7YuqR!>Z0wOLADY=Ehu2lQHaLNZsIm~ABh z0Y9=@eg~Fr7juu*i?uf>+1nJ4pDryOfHMe>Wi9TFVf~pKd+%UhdiMhx`w1en+yF9q ze_!Cb5%f6narxGxf~b0NS~? z7ScEbR6ii(AD1odEDoes9PJgbjAjgvuS7cnG5jL)IHM!mDhtTR8)&406N;@{EM=dH zPwa=@41~G58J1kK=MA9uy>fV6Vb=aSK2F1yo0aiX1w)8TZ#R7L#5(p{kbnUdPYdla z_v{@hF7rs9Yv|3(%{n}#K(;FZ%9SfK9oDjyu6CrT6t$mv z`}%QaYUPq-xIm!~4Ys!@AD8dFIq+{mM~Le~BiX)qf**Tx;IIntiT)g(uQBio9f2Kv z;GBD0vb6jp1XD(Oxrp?+;c=#JGGFi;)bfKsI?;;k)%Q5+@wMoUVWQA#7bf4E#p5ls zV}Lr%#~~57w=AM zlKv_A(yoQtZ0ZL}iR!P#6O?Qv)X53t9{~$}hI)KoRR_E4$cf~!X+Z1rw&n8$8~~hS zcst>{Y=!Lery%Q3eqYR?x2>LNqMgMQ;0LdhrEHJ=CzzpK2-xIN_=v;t`3%{z6SI?| zMFj?;-4suZp=D{IWQXj%_qWv(Dp+q8U=4`LP-NS+c>Wj!I7x*J;n1Vxz z-Yk^95!Q2GKs_;rmXc6DxDFzcx*fygTf6tYa>5XA?q89gIIUWa9PP;E9FZ=)5j-Uw zS~_Y0j7-U3?(OX-q-?X6AUvg!6{B){;5~a+1Tgb)L@D);%qND>n?>ld0FOdKHHYpK zie$?Tvb*II^8DVTRp)owUVJjY1GT)jxJpOrm(2N4T8mL}h zwmkQH39pb(ixIMw3(wvUAlOuv76yG!x;=g$Xy+ihS<(Q2;=Xiy_O50pfRxqobIS?O z9>Zt~GN7m(&s>L=7iC?G(3bq#=fx-J*lR&Vy@1Q2gyuOszLKq60l*Up{KZ(&aN<*U zn&!L~LZt*k$@A}>Q;(k!?MhA*bcARAzOn^u-gaZ>l6IgTMHGiP9#y@e6IyD@npk2gU93C&`LIO zn9xGS&3^}e>`{TQ6c$?WQ}0sr6e07)Oq{D^-{N8Eoe__7LraCohK6%gbkMvfo>Jx8 zT{Ye3@s6bQJ{_LWy?SFflx}xiYJ)eD;i=QMT?--L6KJks`03H%aTiH%7N8y`fk0;# zy}kW7DVqx_Y|>M;Yz?6i^Uq}`+5+?*xtm0EZvcc&eP|?03Dzt59?1#U{aD%A_fhyxY~lknczh8uFC7dd z`bBDUe*#ajbKaB(gF|QawoH=;#_+hApdG^za5xZ9<-G1K<>O7XqfiQxgq2Hwe&^jOgDq0!7lu=eIOx5)5^=8gXgrBv}0{?@hf;e-L^J${z<5{Jmv-7E3gH@Dw^B1yV-H14rGn z_6=y@-6J4LJ$>Pe=h3?zjNo51kGB4QubqP7V%S9}-1DJ*cb*z5f6F6C=>4Xbsxgm6 z+&K!7S2xiYiyvS)%&VmnGGlPM5zlm=qrUsnaU^h$0eZd1QO^>e4dq=*x0M;cZ(`Yb z*0`G8Ed6yX{Ugr&-YPze^3Awl1^R#NNq_hU*v*Ylh71UtULN1QZS$;gHIl*oAFu%c z@_UluS+q|_*D-DLKuLto1<=m%SyCpS@W%r{S+HJ&Qrsihvl`3V+wp*>3ig#ukb8|i ziz~7or?DZhRe5?E>j}W;HI}6O@c^X2M7HkzsFmkQ=9XqBB4}hE#Sz;Z*|TVtmFD9C zq)9mww)#D}^Q^|&1%TzeAHa9_NcOC@+JTLsy@9p5cd`58d0V_CnM7i#baH9$&GLDR znKsjKu;-cq^W;I*?SUxyB6IgT9d7Y>KgWNoWM)Uf33;%|2eJ)vlZ(f_CdFz=!0V8n z>o%QbFgy@YpW9qK?zIVkktxmAf9O{6dVZYjb_(_Uud}Hy9_Kbycsm%o?6~(ulQk*M z$0?;^Xg8`>9~I2zsku4zcQ`l@a;xwU+;W8iODi?td~u$6ZMqBC0_IcKilp0=aXTD{ zO@lfCub@7z5_w2f+YW5+X?k4w!ec2T5w#kq*iX#lSW1pCy!jaJ&fZ<*PEN$$is4Wz zWtM~d?jm<0eokR>wksfdPfTUa@_RO%|m-jM6oT0!$5V93J1MT^WcDcfm{zH z(5H#QmLypAu(bCSk)vvX*xbry7t75gWV`~y6XZABPzu+k4L8DJqeF>ebuZWql}|lC zINF~Mrzu-M=RS`y&FOZ)@ZH}H3u(5qAk$c4DiAzXIh_Iz=h5awEyyq7s(GLW$biAg}X5oaO$*a$##Gb$*9 zFkhtD?`aVx1E@#vlFEhiSv0Vp#dQTwmo0c!Buvxdr*m*R*bVeH!@e)Gwimi+3j{G8>`5ajxTOX0x$WfvR`S7N z09w&x9#9jEZ1GJ!k$l6Wbi8A^W8%MiHK&7pvbU>4^H`#3=0EQP?^fwNE}_rtK=oVr z*VWjQG>bfodc;j_IuY5DP)o7gScIn_Q@p;ny;q7ol&b3wzh8x-_lF9IM%ent>zPjU zbo+;(IRPji+!uO}ueMsC+W@U&SLeg`;Y~HAma=G_jHQuBk&h?O057Y3BHDXzk=Fe? z=)+HXDrzwdK+hb_@!<*NrU#^aJK@ZE$58+;KwD;Fp*v~PE}jlf_PH4&L%)=BNIT#$ zs=xr=2Iiy9`!|Bect<+^aKybFfIF#+;ED&X6Vri;8Y7x^-0C00*JyWuLRsQ*A@Ow+ zot@^*L`U0EDnicK*@tI|lTnBtK!%|=_s0CFI2r9hxhFPNBhBZ)qw|zZ2pv3%+RdOK zeh1S42Rl6yup7rhlfC}fVhKW2`@lvI(eoUhpFqfl;2-us)jiU@AL}8?a)3sRNSwzK zl-s3(x;S#)E1CWASsOhrHWW(m9I-}>=_j1it>-ALO+4io_$;>P%9E)4nc1WuFfio?~2+)K$S5{Mu%H*iQCza zisu;)aAkTZA~isFGtl2EG(IYol!ykaOPM-3uG>mf__>!o=0L;=QQ z$~FL$1Qob?x~n=|)SGyHc3BY_S5KqR?jD#OaCzs839bs3P<%}KTZ5vv3Rjt<5^@{J zzV!AKl*nkZcN#xeY_+wW{nI@#oi0!>E)s6snq!l)$MxJ|&8bc`p_Ho2?)QYUw&qlT z-Vxz>FEYT|+RmwHFEtYaz%x-`O*<{JR^gsAM)f(@np_ zR#It@EwzQJQwfFe+B43Zt6bG`O}S^mtl%8NI#Mr$Yg|%+H#{o8FV}Gb5J0uParwP6 z&N>I{(Kc7O-Z!VUdT^7P;)qic+@^^wmQJ4a$?jA@5%|2)dBrwdpD=uk z-37Yg)(0Cs>+ERv>lE2~+aCci zJlOZR`QoOxrhrIYTsRfGm8)*A4d7(BP@;VIq#C9+z|QW7EIOUFmgsg0dKfT%;ZJ<9 zvDnKSr?U7?RWvM8J(u9z5YH^zz%J;un@;uPY$zdhusu<-@cMm^IFZa6fT*)?Qfn#=shovH-}D!5 zJXG%@$^mt)#~6paVAOuD0#{FQby1`ft)V8uRC#aYj{fX0Ab#JlSUvK9x_K!0^0ljMqtoJ z$)E0^YFbmO!z!rKQ|Ojx0No!W5FwX^MQcBs>U6>xfD>Q@XXkg9>{cyoZ`VZIi3|A$%FQ|YGLRREy2ruSBLT-AeZ0xq z#%2V6V(j^emK^Du_PyOIX#M=ENZ>?WM+SYzN_M(d+WnhxX;3ni4&Qy11`mA}2r$3! z**!v?9B-@o7&!g zs@)OObkE|rY5Oo%gsZY6Vg5>b5)Wf}baQ)_YCvxe_vl~yB1dLlB|3?rq%f)?^Zx9z z#~Rej$i^&^A=WF+7+9;gUT5MQHMVZak;>Ph)$1yDf8rH`+e6{Q4>kRUZYK`eaDp6jRi5mq16$gBoj`;e0B9#jTz{pQUeDUB>%6rifI|$;_FUIa+sL#112&ApROcUVGY4<&>?NC~<_ZC<`x{?*0BRq9XO?7h8iW8B=FpQodHYiESLqGWE2^XB{} z@&A_C9pw|z#j`T^L^Ce6T|w4l_N~tf9yi3026Mr@+3X5LO{sA!j0)b1jt6z4^5!v$boLlAj_8 zZ(?eOlBOU5;A97qW5owzQNMwmuR-{N_9xG z$5_hpRn22-Urn*7s}wu)MQOZdGpR@%aF*T2;R?gg_&p3UlJ~d9v(0*JC@7d%by*R zs#Ms;Dx}p@(hR5~U8$SGd6s3coyCf?aL%WYHs2xq?y#3GrjRHW!S57$n|8KB`56tH z!+Ul(lbvY_YMWB(C>q?^_jj9}I*&b6!Va*@aa z&E4ix`g%U~Jk03<4THIJ&bZC9z{0fGuin4v-7mL9{i|yow^geb%$dFmtd=9binH0;1rBU zh5r(7hHssa7?o|=ALaN&(IMOU{p;)AeQe9Uk7$v|e0}dWv31ObL0}aTp})I)K!X97 ziO$Y%EVpHG>%mS;^M%pLF!jY5YNpjY3F9RM^1@^x0rN9fzdbhB#nkgNrS$~1i2(k1 zeba9fq@}R9B00-AlPF_YIu>iXvzT9E&J$OWW0&*As^@2?c2VU1eZ1*xD0wVX6?Bfp zT*vbD#4&^=uw5!h#3qXQr8bp6mi*t{rOP^RzpO?k-z#1(0MS%2+w=d-v(B zQ&CojoLQEk=t8->!`+>OxbV+8DL*?tP{kD}^PF+h^iIt|H3P1P*=ESk7`B8Cy3Epd zmfPivsx~`3BIRIc4=Fw&fx5!j=2S`hWGJwE!o@b%s?(i7-Il3xW#W!Ij=#$yg55-I zZ8b*c(@SlN%sPc`S)LV2rzyC#h!yQD>t$osd%@OdX9~6r2bPs>528^dnuC2BoZY)L zY^k)RFeUkM8`mymNt;%|Q4k_lZ~k2xCtDKiAn9523t;L*g#u&|hxnfXmncsj|UlJt;AP7Zs81i#a5= z2L8kSw#)lCGdv}Fs@Dp|ggpEkaHHkNS?wk={w4Y%|D zF_f39_ZN4!zqz`&UXG)zE=RoM?sp^(dGPwxH~dPM@7dIwT^#Qy@T`m*59#ZdXJ_lH zulqL}@2LK^ui#pkr)GVBywu;)R ztIhtj#M`QVy{>6W$w*sDF2N3h!b#FYe7M zyg#Q=?{M+X@XR-jGK`U0}M@c3y1t+u=0=sD5Bxi_LYf9linu2e{Dc zc=l%P>4#C~Z;9NB7**ljvXT1Z!J7Qc8 zobI-1H?e4_M@5yNTqs8_bNQv-^mhg$_&16ME?$c6?!7b~!I&1wHn>@NS&GBGJa7I} z{<4tZJG&x54|aCiUA=#K`SFa%q4#;KiW^xp ztoHWg&FhQnm0<4XnH}qzUhk^ut}qnU6ig!PhbRj+tIE|D3fNFYri zh=GuCqA!?C#?zh~2qmzRs@?`YJ&JJ0;4Q|!^Egs7F%Cp(94ICkLw-}-OL_42q^K@~t|oL+K(5uF4ZSIzHW%bXY#^$eg?7rKX{Go|bYSc#(&E zj862bX<6NSr1F&1i!=}(q4zgxSZ6XH8`F*=q4AU}!3DZ`D(6n(TQZGguHu0Xp}RM@ zbO|dvKR;z)REVtKFbEw3W%l50c^EJl^7p=5xow6K!JsM@D06fr!-)7ZV&=Wo;E zyT@=zkVkV9QNzx7^>BYGz3I+iCQ1&ciD zzHOg!$_`0-?A$F;^YnCwJhoBL>dp1HJ%$CZy{{(6K5O(neS0_<4);y~svm|R7r@&8 z7S~KwZ+p!~b#IBRyObO^<;8^Z-WGf*0y8dRbH-_&4#}bb)?M5W@`Oe#L=LyYbR9d_ z8>|dKDQ{x(PF>Y5_*4uzFK>iqLW3+arDMq~HRylSohawIFuUb`S&0yUNIUCwStol8`Sg=T{r6bQ*#TZ_w&d+pp{Y_8ePpVJb|CNSz~y&tbI3CO&A#sUz3XTfBdH#?kz3+k|eyA+!n8Dd*GG^+%g4h4*M1eumJ6)7gTxYVnAo&Ofb+?`&SN zBDrfWsi_*op>UmFT)vL4GgTwS4x8m@yEARx zUGkRYz$9NEip}2bG^eid7fs_ZE?mAv$G!UIiahE!F67u2EJx9dm+DC+|9D%3*r8ih z<%Z0On8BfrsBv+9-3#mRwQG`VetT1U+=-t7JXY9zr4KYO^l6^?u=R9TwQ!V z@0~dsXW}}B&_APEm;o}?4rJo6r7Bs>De) zkEfC(oR%^28O@uM0eqV@C7LEkyh-Jvx!R3i;7MnG1|6 zKCz=|Y=TTvb#lehb0&3?r9ZEz-NQ;y_UEhf>psyA6{|X&?o!08XE*T74M*D{m*DUR zqf!HU^Wy%ZY&N8E72iJ`9vp}$>xS0fLm;Gv99k@Bi@x*3jt)Yi3a;qp9U`-N zJfx}}?3e95qiJ5S<82lwDaPfB@bS%?-q*(j6GvNNmYbWa^ULg69t{M=hP9)!WAty| z9#dTzg7#;-KZcgqQ^;|suf+`MnCjD9!AU;KPT zc)E8YBA{H(oq>IJh%|(wh*;tHxxK#r+*?rT^U~fUV5gj*{S|Y=WF2HqS?q$9OmpGf zVYeyA)NEqSvZrc5`07Uw(B`p%wLDSy_yb+Etfp{IG#?hZg z#`h)sybFez%`0!QQ@I}M#nZFP7VDE-3d$5#K~XzqG;O|?7cY^bXr8lq<;TMvMWzos zWqS5F4{dk?jE^=}Mt;`|FdVrb;3RdgW<%@qk|aVm-Yz0%HnFC00o?8YAzI=r2%@%+ zry}1wsW+Qg^LV=F95V7?7M`&lqlU@iSiQi|X;|?4`cy>x9LjF4jQS!gOe5M_D8KQz z_z7~n{%A1bz8HZ6oUy~b#zS_<1E`HJH;wa34wYvj9BwW+c={uk(YM2CTP7wdtpE6U zdQigYx_S3?IdVnUU5NeM!;#pW<#|`VxH9kAdN)I3R~%3Rj$n0 zdiNEoacu8B0r{vlYdkB8T%dqg~s|>oJzFxH?Y76gq!QAeKm5-fw@~OLKhdat8SJJW9AbIAPf8V(;I-fldh(6&_|0MMY<+LmP8!(ukPFqw#Q=d}uB_Kxe?; zQGmEWnoj~mYe0ANV;&CZi{v()Be4S+^J`bL6 zPc+YmvM+|Sz^{vMuWxRdf)>I#o=>B~?%YIBzORhy`E=W5xbr#&`TD~X!HxCBzs;7f zPaZLMBpoAUkoSF;qm?oP>PoI5V3B>p*xjWk)@jR~|mpzl8sEpb3pkMQR zN01r0J8!>F-xG2E0zx{Auj4)D*L)x0oKd1{wtf5b7gH>_mZ3WOzv$v@n(tYJ$EV$m z?C$jqe_^}+q{n!BM>g$jefsU6ZXfx)V?WE+ir(?ybm!z4rqx`w-jfdCH>0qp;dShN z?|UKiC)*4@*wYG?>F4DK3iG4_2UFq7Fqa zm*u(d#rAxt=JmEDuNimrmv1B!JkmMK@-f~9bLH`?+5fdPr+SU+SvIL zdwbD)Rj$W_iK@N4i=Aw>byxx;*j1@OT_x33h)mHnsfY1<;A(U7^{*-)C1} z_AK3AaC;F!+AZ+e)r%tkD~%=tkbMyov^|smvhRCi*p-C04aaja$k1%_AR+4$(X%M_ zMO?<>2n7TOL=lsAaZ)kOpmT0vZ_lk*xRowmy}NvWSuSyPn`l97;>1K(;La#`$8sD0Ijz9PG=-jNGmHY6i#U7t|kQ)xmLdh6#?&lsuGX z8QFd@gqOGX7n7{!=Mt$nZy>f*ZUA7wk;vzAlfSr==Z51FG|6OeEJ|qGeLGlk{=%2n zX|<1;K&Ol#WhsKv?XJ}VesfFfc3n`qJ#!`lp-Pi&xxWVa>E=SRU95HB$=d)y$_TFoMZyn6q+6AwKyM8!Hr)zigd zhVGQ<#O6XdhUYS0?VxmiK`fI>ij>;36VEtS@ga z-}US-T3`>5aNh-0yaXoHmoLQI>9#X)L5JX%Oeog&5l6+GP#wQCFO1PirGv#Z!(x%A z8A;AUuj&h7R%l*0k$oj`eLl-R8Q_*G$PiIqp(H=BuY@HFwBd4y7DE2?8A_`CB*1O5 zAkQP13d5NU`7`HB6+>uV;5>6pD;C$g%d1Fc%Ze&s#XYVjVMN^|2+1DLdSlGAGAS`t z9X~C%yC2x%j^vbWl$?pMZnf%qdqb^ivG83KrMJ5KZXKvM2x<<}5azS^(N;)7PUNyW ziG01q8~t%OF&H$MS?AQ~1>b6e(LIn{7jN`JZ^0*WL4mjEdMP7qPgie@UA#&T<5+HwuE0+`KGX_G-LlPRtWmks8*DF!DihS%_QxR$MZh*CRU4JN zavLtuN82=^+D3n*PKMFZfot-7q(zy^>jEhiJcpq07%7?9t!?h*NYEVNT;3qDW?Qv+ zLo%~~-7fAoXu8~=OI!vdQ75YRN6K7sAdNLn!Sk1Iude!MHPA&`ty3^Xz4oboeCWnq zQoZIY*Y4=);25yQ6b?Y8M=KOSBm!j<{FdTx@4ev|*_lMjcPGN{Q!L_%htLofy)3ue zRxd+ga*V{?+CD^6QhZyoeWhtHR5)-G_rYl924G_Mh8p7?E^Jy=jc{&i{ zWt`&doG5~@nG!&0>mDJ%_#DN(m117mbefc zAnxqOx|F%}b2*GddMO)J$U=%j$x-Q14BitP02}R$rhPLQd_`g10)c5vIr2So&{T0T zW~BK{mitoO2_})!Wo!OMFC{=9&M%=-9fx(PG_!HOoLt>re*AFr_3g*&vu`d2U%i07 z`10MybK1hq?d!{rFAH|#o0lKE_XdNl!Pe4Ozx%VB^Ro}VueR4$w}1I^`AK<-}|S3(*ECzjW4&BH@|%GQU zzwmp1acODk`oH~$m;Qqv{Ub|%>+ScK{*S-@{iW4^_4`YI=YRkGrT^l8`14DD^Pl`j zmwxuY{bNi2({KLqrGMh`hf9C|Z~xKK-}vh1OMm_EeYv#$Vt?sB`rAiK|IoiPUV8Jt zOqTxUA5542_@DpFOUnm;b?NW?h1W}O{@TUT`0stQ^iTcf!_pTg-!A>#fBAap-~DfX zz4TZ9?|*UW^N;?erN8x8|Hjh)^*{d2rJwwt|H{(O{{4S#>7V&u|MjK+@_+s}mj3?# z^KUNwt$*&{TKZ@I!+(3}FMa>tTl$ax`~P(5?nnRG(*OJBKVSM!{``Nv^k4nm|8D8% zFDxzn$3oE|Dk`n-{SfA%3D9v z{(NNJcR%pX@0T&n|NaAg{@DM%=l4G>eMfKIS25yf=@0$;r)B){xA-;s{hro;;?F_1 z?)~`ppDTY3YDGUmk2;#~`|bO)Z{wRk_V=LHAC_-^sP`Y2R-=cY=8wy>_*=}k`!!mQ zKLtgC{z0wzvu;j5E-UvlzsKsun1V7tG=ra(FS-%`+@FIde&nq`(N^?4=ZGKATKsA0C*|!Q z;;~rIKP^3Va|nKkemhFUyFV-6M2|s_;I{ZCXdG1OXdUAZD*U{BS83IK5#xw{gBsmP zy4HgtL7AU=`n}TL{Jn0*(Oa}U=epqIpvIs2Z?{|GzdtN*)fEcMGpp&=lG@Li;lCpS;dNVJ1}-o{Hdc=_kH|1zKQ-j zKJ0eGoQmDJ=F)z?ULDtkJPRHO*%=gwwn7reTOmt>kApAgZv_u^9QPA%bo1;ac_%%( z{yScbS^r!c-?v&F-^V&f%h7I7=1>W%p(G??3ii?70|mj5Nj@ zt;M@B=J>s%$(%CLV~jmciuj`A)i?p8_incYS!6` zj4!$w#7ur(`s{w2KMDR0I>+&V0?TGJ{xx_Cqv*3Z4Y0R~2DMsC`V6+!<=Vyh}V@5Hu_$TNV|HO&YtzVq9ohH=L zt9$EbdXFXu$)%r;pamTZrwiMsT-(&RM>UaN+*1LbcM;Gl@J+!Xi)ObI}6#tF?b!T6< zrrjAFt##6BKK7Vz=r=*#dE1?=nE!3wU;H=d(b4zM`E&dd{mePO`=#5z-IH$2LGS1% zDB7Kb-F}N-y48(V;_3YN*aaawyOult=z8i_JpLRfM98-I>h}vhW5iuQaVm8DH0P>0 zJ%buS`{1}}CI0E=JJ)*Rmrk#WKgB!IZuHwp`S~yNuRB@NwbN0kqe%B{NB#egv3LJ& zCA;$bIul2ZC)0`IIF6E;*h(yG>`{8HdkM5g`so&cLOt-P!hbLe4}#>q03QGeQvKKG z^TqC?`j$M-%3?P!cyQilpMCaw>yE^IiF&bW%~B_#wW>T|T`TzQ&u1q{N%Pd4^^0nZ~?DZD>S|s}`}J>REHuJxTSVm40h)R9hH7)}ng)6f;ws z*gx&7ezb#Xkxn$NP^B?qj1@h{ex^EIS)7B;HML1A>t?QRwQt%X_5R=UZwGyGia+oY zMGqQ7p8}p$SFK{z`c5>N#@DS#l#k9dR;5+}J#osxUuabQ=#J~(zzzw%w9~?VT5t3l zI~BMp+Qr-j9XfyY6#eLT%scfO_%H30UV{X~>Qzu0C#xD7FZHiEr5lsl#5)&##cz$S zR{BdEci@I@4hecSL%~<@9-^RPmg3)HuL2&_Pg+r$XY?L7L~~BKTYD$m^LIb5KIX39 z(R=h2y~Jm=4en9%id_{%rk0vhjINaiP4&Zd-m$}h4bm>Dc2LxTHPuVkSM;g3Blbl7 zYCkoTv`?CY=K8n1&MMcQ2gC%l>V*-eQvZKXPq9;Jwt_*eLy)3x)Q|9Vf~kNB{f-+N ze`{r`ud;w;wM|kAozZVO$-m-Xjia?Dn2q%YRuk^fc=490uKH3*>}xb;SDB zcg!NKM*pTgh!aeleS&q(BwCC9Qhm)RK}nJvXatoT_w6#Xj7|~zCrSX@}RXytepcXZUfG%5^uy%l!lA z948}MSU=iDVNQJ?*i2*T@3h8LFXkyYOKTJKra9@{17@PWR;eDewxB5li^341SJE#2 z_UHL%{enkfz^=X45fGvM*G%tl_&=a9denKwsL@{g8}$MvL~F&&RGw~=de<%ljK*JqBmVYhicYshb5tG8 zOMS*FbYEk3f;^q6eg}o3USpS3UoF&DJE1vh6>1x2s#DbeX}#LZsIS*Vr=+{1f7OH5 zseO&vL_N()eMS%Ibx=vP(u#DZItR^1^VR7|!l70{DXAB&Hug>D5Hr_o)MuL0-(9h} z#*dxQZfaKQSM-VQu=+@EfnZT9(29db(x<==(Px^c)~EJ5r+7(Y{!t#SqyKI%^htb9 zsu|;SkRU9hod_sSyO=1M4*t4(r~YD><1FLvxNUmLwC-4a{43bdF2)Iv;&6=+VEz zQGwe<*Q>tvNvE#%+M&O?_8{s^we_RcTFL)*U3u)J<`l1e%v!&LZxiNGE6pNSruoKB zXr%b8zxCH|xnqGZG<&UE|Ery93RYB4bJvfg^xBtzx_B@2y;d!_i&@3}((JWjjU?=p zdJ0)otSe4Rqs1$to`1#vQCD@+++q$IL1XAApgY!}u>$|8$C#raT=ms^TKzBiq#3DB zTAlvY9;$%>+9tv(zEiD`cW8u=Mg^wp zFoI_GOIrRloa+w_l$OTO zP9*(s*d+*pG_D{duu;-Hs(xSs;qTaMtvOCJ)zus%@fXMVtLu!Szj&Q>BV(U+8{)Kt zHFW|i7Yql59lNBN#BGexh3nKVQ4RVlAWRu}UZofhTsipB_hw~pt;QEN{9D$bwQFAbw%ZBu71H%Yx&GD4 z;wPY1W$IJ&i&IvQ(L$rfEz#fU=Wo9I#m{X5(*8Yn?g!?fUNuhqtJ-lJ;{4(!{_5v( z0)}J%)JnH2?zmQ%C>50jITc91oT^Qqgx#^=BN?3Q=i3!2h0Y%>DHu^)%Suh zVKqUl=C74Y{-9Cyjm}fQHBxZsYL#B1SZ$nMz(87mtTlE~Ed)_&`Dp*+-Bmm7 zzwWelLGx5ua1NT4W)nD6<@ynf2PEk1^s?VNU8-)j%F4z*16qh4ww$!gf| zM7^jLu%OmD5v@q8iBW|oqmRIUsc)@H`}>RQuBuf!*`S`(n|caJQLDHqX`bmk^|vT0 z)li!RgX%9~S3!nmq}c^k7cdmF*EsqVe?_fy;#!0HRekMbP~?AoEz|5`#cHYXwI`|- zXQOpT`*LVCR@|n!RR{dQ)46-_&R9 zwtCa5q!&)OB~B&g60J2$ttaNJHN-sht?-C`ghyhgA;IjyAYO{>>hqCf3|euQ0ue$q~Ay_$=l zMSTi_(q5{kfNb?7ycg^KyX#o7V>-F$Eihc*Bh66X#E)>H-VE7B#tby87$^2hy~i!n zDg$!GXKO~9jZRpy1kFRc7$+($pc||m*II(E(AzGYrt;Y97%6Z@C#~t`r~OEful>;~ zV}@Fzuvb8Oq8zlUfK|;;bZOu%zwbFPQ11rQgv7*=&tt;L_t?u8@Ps~#@)ORt5 zn1}W+c0zrN#!5e0MeKma4cW8mXa}@@)l*y9il~O>sMW^#Xk^ui6W54pt5X*)(jJC% zC{`vqS9_q=`q7C8RK~pxor9zz8b|9_U+OiWNPTH9V^+~VZh4|bG{>}4nxSy3{{Cxz zs~5Fa4e>Z>&QU+@N1Sr>68u_x6Sq?3={r%|ak5&oIR9VqBNr z&t@V{FYs--Jx#m$VMvN$XE{CT>=Yq*C3Tn5k-M{B(kGFQQC)uQ9~S2%{ya z)+%&Taog2WdN17qQF5a2Vl7?2`jp1dC)NAwE9}K-O9L(F)tyN298jR11jliAqerb( zkfs{RdOGH&83}`ms*5|PQ`8JqH~1Re!Pw7$60JC}f=)!=1pTNz2yCogwXV3MDouN< zI%=cdV~skAz*VvPT1|hCH5;w9)42y!Xr_VlVs>%Y^j*4PY7w*5ZIrZIzx92rM6=Mo zXik!Wi__JbG$++cYxwuqJ^6v}qGi(7YR_~s!9i#p+A~38-1Rs^wbBRyjoR7Nd*~7L zO*&Q8(-?t0#4Tus+L?4ybUSrN(kjE&NZh#2HuhDprX7nnBTh45JjPaCN%vJN=A&B_ zvx>GcW8F{9D87+JmTIS)7^N{|jS+Rz&T2(*57TL@okoeD_#|FAU_YdIx~YOzmB#1j zIeHajrxVoKs8leZnW)#W=hw~z6`-~O1L;iv{yHZ?xZ3=hk<_2O1Jpuu((cD8$Ih!> zdU=9}iy6h6s(#c%;A!czH78M0A)nS?nveE3<{2g08U3%31Xp?&V@~?5J|*E!yQMZ7 zA-)M{iO+$P0_N3Q?1V;&HKbb}HPlAy)cw@Hsde0es2}rDss7gQsI7aWzco+Eze3)h zMu=8|PmSMcm0~{HYn`q3P~QeNkQJzURGC`o7XFIAgfW5})3-6MZj;VH^&~k8ZEUPn znkem6!axDd`c8Kyc0-?Ilyt_jVbJP?JN0ky)1lQ;o0xh0R!g;uJ~fvZStZ|J`-s~Z zJEb-{d)-HkA&d}Er8(%cB-62*`W1}Q3P|EqrQ)MhyqdXzhWGf=(Bb| zW*)feudZuSN!&TDP`j_)>ZpXER|JRZJ^s~a?XqYRwGW66OcM3flg8AXRsO?O=A+%v zjg9_QE?IZ%b5IoGVWW4|i8Ig{2i}NxJXRVbq~B>AjVcOTedxO%_)EA@XQ+J?RL7k4 zTc;8jB+6pt0ckOhIH5R=Sdo6mjs_g2yAe>UF;$}7Nv9nYOTe+-zId0@U5!)I+_VPu zse7kVwTt_tx$AG~9n)@pt!0_a#Qro=d`#UK*_~ z;9gLiW-I$;^_KdL-qkWjh}T>AK)a{1sH`uLSkFIr>f~qkjWtG_qdC_$FTSfJ#xB zDh-H?9TBvM(@l6>d#_$KhHg&aJIy3+ufC1{b>5nH!alJA-IAcB(n-a9f_BkK1(d|< z0&ZjWYA5*k9ph?N8b#}mIcrY(q%zS7VTmbBt(gl$#EYn%iroz9gy34bIrXI756(k> zsb~FG4{8y;tM2#w_3P^nYB!=*%td``9Kn3_pwIE0M%F&Y-=e&=0=3rY+BJRBDGI-8 zweh0GT;g?#`uaBd6nv<)<`#X#Tvej}^jo{7?}QHnLXx&zf5*yISN}&JaWm9PGmILl z8NP}7BnS$Opi_+*q`sm&))RL*<|M6E%s3rd24+AHmuP9l79)$04}-;%khwbrUVP#cXJP#$H0-(!~2!>jf0{ zh?b%zexTo2i7<$2e}5fGPdW&8(6Rk@9$C(N@{{!-M{jHwVP7oY> zrFvSW;4o;J*h|5rW*_x_&3F2wS*bA ze?Wp}lTJVOLi0~6PycqWYwWiAivH6l%}(FN>F9=P##*U*jh|Sb>S>Hvo%+!Ur=OTZ z>~?$>lqU)*U_16wm_jWzLd@cO`qHeTT%*U>`c^AWw^4f)@3m(8{k65uFjgeEQSI(0 z`d3-BinVG@dfU@q`ZjhzqXz5>ccuAhc7nV#O5lm;Gy2fF^b@mHANoINY3-(9Lu=A! z%_bl^>I*_O;|`Mw#6&I8LOVY{T*fT zqjvffCF(n%T&2I}r>m(x;})k{q9vr^4yul2-FY8O3sW$AnU8*O3*sa}i_qeNZZBh}Q8b~3e$vgjkeP2Z#*qcpWi zf2kLpU#cDD>325|)kuGNTg@#-`2N~Q^#A>}tQ)JpLor(P@^?@asfQ?uQ&gYPK8+gv zr&jvz7eBWYy#5`hAK%4qmBqZgG(Jb)`kY2cpHr(;u77-NV^-+AlQB9(bx-N@-%{hR*(FMCUUsZO*=?b0{VWBirMe7;^kjnkD0YXAA#zx?yM zyH+uWfOLKKPwBfTkKbu!sZ4*zc>cXZlghP<)Z+i|zrKEbjy)H(^ZmNf32d*w z18;Tpqg~Ll@vVB*3<4MGufXQ|t#Y-Hj!`w@9g3G-+)H|mQY+0SUM`(l;8OioxmKY6 z)#vy8tq2ysyM9XF1g);VR6o|D@%5wL^b_-mRYW~mqQn^51&yV@VoY()G3(eTQMtlD z+G}xMzheA22d!Q!6#k7>YRrzRi+;W5n03rE_D?iensxLOyRV)^y#`mH6~ydf|JCAq z{*O7wNs3>HT4~LxKT(;QUyP&Lnz_z9bpB}_8bND~b;s`OJAKkium1JstA_ekKLIuR zCiYkLqlJE}MvSc;i#ez~amX_zf=}~#r(VT(fFyMifzutlzN)^({J4|LS}+Z}p(RV;(^%Mmyo9 zw71bmw29ujmg+J7ic`=G)MLz7Hzzn9^&uP(XRjFr^%7%iHfkf9CGB18ZufVrF>0z+ z+#-#mQPL{Zv+DS&^_S)-u1Dosn?A*lTEzb`bM=%y#b^B;^tb*F>1On#dfn-1CMppW zX?B8d^{llfi9=eoFs*8&nWr&hZXs{f+G5=3S$)U;sdm~Ql}1gCq`%VX=-(&{>7~9^ zf12_4*H)=Tw2RrQ@0g9gO*^F$eU6#MD4I>|b^MOIAAPExO5>X}>+U|r>BZ@$(N#M} zR=L`zRjNk%{5{`j4RI@CM*19M1l+|O(q8J{1iku3laPxKNi zihYTj9{p)AV$GUOaKkZ<|JE$io%crYN6V38`F$p41KHbG=_eny|8b$x}Zz+ZQQ)nCeAeNq!9$%fL;Z@>Fb{7BRJ+wcA(|Np1!zxq}s`uPp#@_+Mx`u*R1_h0_}i|_u$ zKU3P(`)|KXKmQkN`*-}WfA#b4IN_iX{!ifS|KNZ9t4~_}-=e|Q&#%7w-+3SYE&uD^ z?&sg~jU?j#`oH?~zj6-$Gym&fefl^2{4cEXmteO4iSzlJ@BWAD@A$00yRv_Up6p-p z|G&ciLtg0rl7HjVFRuF`Idc5`H{ZoipW6NZ{!1-VjsNlI_G$d?-&lY5Ti^T#+C>dQ zpiZ)X`t)hikbY=Hg6Kbop8Y(|M`W!c`gNB^{_}V_u1GUgW?gcw&yz9nt6OqceeK$k z&53~Sp%Z9MokL`CN>aprZE1Sd1XFK16(Sve-D?t%=G zU7+62WlLVznn3tRt4Fl;q9juB7u%j{(l%^aqwQUEb*rju+1^EVu(G;Za1xWO3-|k( z1(Q*Q_}Tx|)gu=HIVs6-_{Anffa~#upKRY%oK0tB;v(19os})>RZbq1?2GN=tR0bz zxm{&nx@^LqNmazAk*%a_JSV#r3z}rNRz^ydg5c{}m;CuNS%OH4Te4_diqgWBBQjmv z7$mUGm+hF@{DyqXe+E91tdPZr*uiHjBfk4IC;Q5-D_c&MBj#OZYb&b@5~LFtpTo8d zZ%OS!bKvYZle()-@N)7^k!Ozycx~eQlR>Y@Hdb{>hT{>Lr{21<)o2B5mD6l%WdxgM zLrB47W%H67OYnI{pZ&S`W=tBrX+uhf$F9#Cf}OJh0&joq2EQ3k>*b^>$Js|W(v8x= zj0t?69lU1UkWRH8WoNHRg4D&7@YWk2h}0qEASAN3*Ibamifg;;l}%Q&n#2-&A7|0# zqdCyN_Abd;I$MsjvsYBcsS)Wszx>E1x3+qcmrTi3mz}$vx*0dKvLOXt_UaR8#}k60 zFS3glk{y*?bcDI~=A;^_2+^P2*{sNF-H=eG&JOS0=#v=-M?TJM?S&-vTaEy{QwLEu zHh7-rq<#KE11oUN_&!^d!VF$T4WPhy2s|E=7s^ps? z*$Oy!*a1FO!H_fX{nm!htI?v&iO;?9Lef^`lNIRQ3yC+cq;LYg!n<84ugapz9xvUd zA3r%{~gEucq zlF5PlHr~9P%qmjMlA@|Rm1#+=^(py~-o4MVEl6!V$sWB=o_sFlC|i4<;G@x$jrurQ zpH^@&+=^Nn)6tz4@Y=kob<&Z@rqNKqd@* zw)F)qN3$spO!n^08*(w{WCj27$w9y2B_oSU_TjtK=AW zl8)fZ&~OZ;q&OqR&)FtlOv+i&mSBCGd@-35Yo6pDTOVn{bH!7Xz1loUc2mvE={VbX zO_EcO$>p~3$&+t{$EnTMK8_M90(jZQX9TfFN|;slVX#y{3Xw5jo{|ES$}nCd(wt^T z?{>vRL0Rgd?h*4h)u@Fg0lR%zCluDRIRGHC$WT*@=>UU-Nz*pxMxJbL)hveq8Bema7cR*Mw*r1&dxZh&{8@(ng++qPLz3;fG z8wkzuq$1blrQ<*;Tuxwg#@V~Epp-&?<^>n6V>WMUo{VP9;cu}=g4npvnQ<4!aAhe#nCfU`KFl$A*JlcX z&qt$4cJMwSsOQTGZ;nq?m}epe)hEjJTawl@JNIg?pb_CRj^5{dF`JRxIoo^lIoOco zh1rWY2f-n!kYE%RYN^3gYH&uf?U; z0qym!tbJ05bm1oI?A>eXc9RS_+jz|iB3Dn{tJg$SJJM6R?bV!-&#lU{uf8Up^hJpr zboXKN6#rvG)tMPnE;=NuWGNYDc)py<; zmCO=UlAXNfVzihjAM4I*E)YgcXVCp#b4d!o34K2Le|wvht$3a4X-f>iX*yFm2? zFVxxjIE7vGbbM5;+z;?8$4^h?}`!*=IW>4s%r( z4U$T4J{#vNa2vc*)i_=Ui9liINEW@{W&(GN5b>LLK~hTI|Lnoebh#?aNi#w$YZZ|d zk~n>a_`$lQaET~to_)5{Z}Oa1ZHcJBYk~sn7HQCj_lcZ=*RIaKdCj7R%s`~^WoVe7 zDakgwoQ|`5uL@}m9)t4o!WudAjC`^0J`(Twq$2(G+H205c1~u{?BX@&6L<}z5?ilH z_HOh72&23vO2OF-Msedcm$UJrAoKf+*F@2vB;ncKYmzIwAX#*F=Y=iTVaC=Ols7H- zYB4XflXtlykL(yG_uMN4H54$pJL|F?kI<4#%k0VcEJS0l1qi7>jBIKVN8`s`v0V_U5bo1af z(eNS_o@d{Bh1_L0s-taEi!!DW&e(XD?At=vW$T4-*gQ!{ZoJEST0q208(cI<9>yIu zYU^@I8ssv2^{s->tkDu=U%lrUxyKiXnm67v?8+R`O7`x}7rYF}H?y_ZMD)Z9SZ5cn zxhyK!6;P=Ugld*F=F{xtHJeF3%8|&Qdxd&yksj@QAT%LxC*XGPvxSmep$Yx)!*3B} zRwxNxywA2NiX1`F-ur~r%F%{ocfCSVdxP_{M;mB0T2|nvX|}OGSBN(ta!8EaE36<2 z5Ej2$pJ);a&U%sE+dNm38uUcg+qE~Jtn$@pfqKxJa}g0Qwb{EDP9eo61#+OjD1>qw zUDcyzB5(smF^3o}vz-ry02@R;%8ouQiLj@Ls}H@x)x6-*%uYTSobISbtbXTxLQo-P z#M;7}SEG3~AGg_4uMnDq^UGemPw*Xrmpa>fpY?cE%tlrA)GLHwCv$c7;mwgQ&Ct$f zpN(5%>QF>T&=1~xK5JH_V9suRN{a~$G^vcg42`o|A?zLt6P_I+K$tV(%$>Ji&S3VC zEkF234GJ?@*zDd5S7R7`gxKGDh0UbZE3oPM9Kcs0rT|R742`i~wrItQ+;o_CfQ+?7;SVQdLUT&7^_ifu+}oo`Deyay zR>lWIRMHgO^R;QjsET2a9*Kj|W|TJb@m%5`le<&8!omiX*wd+_A_s_N$N&yUvNO3U zrIe4+9j@O_wzLUdp!WZ2qAFEgA<+h_fA(EKUQ@$?Wb2JD0wr&?fT{U<*KyfYJiqgAPnXN+C8V4Uf^9C`kH< zPBca73WXb#!tU+a&Zj1${0fHpZ0yNk4DkSe0unGSB&G2Eg*5!V>yB0wyw2uQU_0VBFdH`+;i9<}0N$EVt#%P2+hp!m37lcvs?9ByqRBpz|IsgabjVWzw_7a(T zr;-?qXQTPNk&)H#557Gx3N11n3~d}FXX7^KH9*1Jp?JDLdxy%3F3u(?qkPV!Il7BU z$0=RR77On2*;vZKcwR!qL$0hc7i)^dSdFr#v!uFPNp1G>0Fuw#1?*C7N{|> zUPM#e;rhXN!Feo@f|-be!WFE=g27CEJs2-@C}dc(2h(~`IxP`l)*zVPiuL?9$lNx! zK8Gc=V#7XsJULJ`*g?$@`E4J3-W zGYoiM$JhzLz24crQ#ym3fva|OFd1<%D&#(ICM_Lc4GYTxHMYO;e#djPlPCnvriY>~ z+@|Q!%h~S6WQ?5vx)+vVS9}6yM?06j_09qVDCUK*d-G@zL8-uc22Eh-3p@vl1x>ei zgg?p0Ef%4m>$^^oIp7{j;tf^dzzY3~VgVBD#UCAM($Tb{&+>PVSCbQkhQ0WEI)SAC zb)c{Cr4>yxYmh;Gz3b$61N4psvWyDF${#xnic+Y(>UCZ>22qo8IRX#EB%fZr?s8P3 zoY)$mRN2b5OR7DRV(iVI83<$R7E_1RRa z)J5JWh1Kis%_dgOF=@o8Z(~Yy>aIY-2<>)G^+821O6)AM-$*O%U{Wud8Ol-ai-R@T zdbUFLcDlXTfHOEj4fwY99iHVpXsA?rxekF#`6!bKwCkOBT#(s!O-gP>Wr{Z zGEx^S%9_`YlYcZELurE{8V_yn2F$ThFS!?AO^Gp>%*W8m+<={#7gCDuut24^F>3~u zVt0Z5?c2@)Vh*~7Sk3NDy+Pdu3ILdV-*^1GN|z|@SEyb)Gp_-!f59?9?eB&YDMb_p z!GAHyDs`vm=vmvhTb~2wrA3Ww^tp%Hv5jxxwE>@_Z_jcyo1g&TW;jM`5I5)=?))hN z#i5Tuk$8OaGj1>`kto$TzQF_?CT1NVV1ErM#cqk6+?u3`x)K$k>Hjhis5!j0h%zur z;@xqqxMCtX?C}2CUPL%w#I4BUw-231!2lC~jOY;_pPfLNU>>(D*yEFvI5Ka?GLw~< zXmS9NRwMFivsXV+D48qv!HUx0G9NATX^R~8;!s6ti6tovdS1w200QCM>z3KDiRR_(;gvF>(_8iM#$ezo==YY&)#d!i~ z_Lg8UU7|8WqjB`Q6+9e5N=UDl4ue8{B2a=+KfL?VL(vr@sQm5yH?P|+=HQ6;-j>x9 z%!oM6of%XPa!lwKOLUvNvoR%<@=E4oXoyeNZH*Z{c0iA2qczB9a?{|loO>WS8;=lw za#`N(8s{_ogb-^%ggAYa&k#mS&bJ@91wciPe?|yR z%}YsNb49Qi`es5}N--3LFN7R1a+uN;zy%$7?^k!pOT}3sz48sg!wR|=bIBijrBiq> z#L+K36o%)`65fOh?aaDo@NDJ*nn~usAo-Djw&g=5nOYc)49WZoDX^Sok+W*Cn zR{Ort-yyO^l=6DlyCY{U{HBp70Jw8J?tX6G{aY%O{=uZ?1NuabgV4aGB(Og%<^~YLj=aEeHIhSg#LotJQ{9p!78ut% z%=*nT|+h z#tneByfyw6)(VmVPVDS2FytzikRFaF!zq%ABT;?ADbHOl88*Jv0^Lf7|=Tt!< zZyt;e#ayn&SEA02X2(CEv_VXVb%DvPDWxhDHJH)YR^h;sV`O!9o^~pITLEXXckXps zA=(l3c6MRbv>s#l52bhNT~C|~uxEfLaIqDLubQJI$xbd_LY%jp;cf{v`5+C z)^Fn+t{?RPQW(EsbGW}2y~^ff@8xuXG!z;v`{sgIu6?cx3Ax127^d`_{JigEVz@QyRO^2*{Z5uQ;Lyha6G}(Shi|I@bu~3H(#+c$H2Q`dn`QTCl^pi8JWiXU9XHn+Bg~N7P$7Ba%#|L8r;mUC<^fm?Ge8=y38@Qg!D^y*g+Fp@Vv5B!bI z0ZBAg&rs}6#}x~>I{X(=rTdvI(E4Ek1p#9$m27`77J?Ws4fUW{pv{(d$)l52#gdyY zzv4&N=oE0U=c6^#9^A@&&pq5hi~yLaLm!I0;B(h22cgzIad~T*?gKqD;l+nbWk(hfrurNDzcQ ze)#~P#b}C_V(XVrrLcX-C0$Af#fC8$(&Iz-4@-y;T-T=Ay9){dn|uZi z0lE1cmNmg)P{BN%yx(TtV(5?D*WVc^Ot>YqR(ltDU=ab7;zxY!K`$CIWYu_;nS=14 zL}W3QMs7dwIRGNk$$_}-RRembMFCL1Izd^D&_PPPadBRW%R{IKh=Hy1O4YdFMLeQhZ^F37R9Dzw zs2Kj2?}nQbvt~7h7`=>18Ga`2Z|mJJN$vq_#-y z_O4Wu=b(a&9L)J*fUF9uP*GK8TS@5xBmOyrpzGAIoEdWy3BBMtE?fmLS7N%mpL_}c zHQu7q8To=|>KS@uZ}$0v3g;ihCtz!fz%jtu5p@eH{@dPsF+5u!XhbDvFCDH&;|Z4T z*~xr+2XaWd+7NBc>26Rhxyc0gKyT$U!!R4QC&YjYz$@s&3bH@Db&~`pg{Qp2{ z1&4t%F39@mkcQ45tu(?PGv^#&j5%+|@-}kGQq{~S6AT-8;Y^HGHCQ!ZNseIMXijW; z=Dbj2J=Svpo3YyX(PP8F>uwQh23W5kpC4z>ZmXa|d=Syhn5W7BMIDR|C%QeEU{hjM z_y!)Xz28t2B`6rt_?TM@J+#vqYG58YTS<*g3-mWSu7mLac+YZ9$U6@^V>+q z>gs&TON&F?$;spz(up&=hI`4s{LwZDeT1+h@4XA6Y8(~_@WIV@D?gm$YwUio8*;)2 zKc;eCBJ+Ir#{l{e&op}2INGoANA$UBkJ0mgswt$<{i!JPxfhVF1HnXI@q zu*JUddan^AWji;`fvLl|QpWiH$kbp#B)5nMdiw^RK+HSIo^O3-HMTO16vM7u#77@{ z2P85dPWPatM`BOE$D{9W4T;s_@bl&ZM7EI~W3(3+71rEvoGD?x{4u~Vov;tMXl~s+ z18;jU3NqynCwywurZ8%N@Q2C#q1G{0gyh}%Ls!p<$1{h#c=3l0*H2_U_)mN|;Zvji zRXh)P5kp`^o`AGvZ99JyF(gLKM5Lm`5*$9ZKBe&gG=gdE59 zfS4fmoYXKQ1Toe!V}F6gmLj_s%{DhPUPArS3YoAMpysN=Wh-^NWxG)pmJIpcCBF;F@Tk8mhsJ4aKj3( z5a>DWgDVp{IN4(COchD#9R1)FJ7A-I>J`2U3mCh-Ki3@n2)#Ref@5uYnQ+j&t4F&= zNUX3`!K!uVhmXs34!;Oz<5cf#q)>h^UguM<2fQn40xq20_ypf--U5`Q-(2U7o&-)7 zsnF5=^#_Ejnjo=2FXB)|DfB6ViHApfuyN-WH!KOHZ7?=5(#ayIJDO;GMr5stf(E@f zW&{bB*RU5mzsr;^xE~09F2)YRoE3NrVlaanwEp z^!e}`j^!P%C0f}B^Di6FE7}iS4ID}^Nx)kVsmm8*+`^#18Y45~DYw(n-u{1_%iDX4480%|j2+FnXU>7-F2A z{wJy)n}$mH_IF3g#=EkuwL>rT`JBNM1X}O8_du;5nvPEqz8ezoS4;zm75WUEKFwKgavcer6_}3 zEWp9vYf5Ddj>*lF&jR(?asffScXNN-M(X*LX}moF7!#xDX|5oAxOsr-S! z83hYR>hAq9nYDO9qgO*bWKY)&KL#A@v3u;n{0bK_>^GoLd^Ad7@sUTn+2U-4wH5MY z>{@JXP&iP-5TZx7r-(HWF#Fml1!*HB*tn1jT3Y6QSRVQA%&{^jM5ID!*n@`Dpu9%1eBGE# z5BCOtCkoBp5N?+qA@0bE8ZI)lr<*+-wKl`p5$KL4^ymncmXaaoKP!;TbBZ~zN z(=c2cH=UOUGaiA6kz9s3$7Bw-02KUgeo86+pYSwCi&8LvK0{51AnM*90ZMT(l0mWy zf#7?Q>tJluyMU-45Xd2ix)|Sy(x#dtM#{GDz0w5|6=ZDp{_r7+;2l9dyLDw3MB4%f zbDqOz6ZKGv#I?bc&M80qFChSGB8S>rarL8^LEoPoXCYD~)*&l9yUi7>GukT!ym>cX z03&I533m77IF|Pj0z%Y=#T*zA@Bm{jaLeKBfWAO6Qo{(`I_)%_~y|bhg6&!Tm$#A!V0m4ZDInM9R ziO_Rp8a7VT!U}_?F`hoSqHErwy2J(pQscd&ZRS|Pp={@cJ{i+6UqK5N#Pm73IC+l6 z!l*)Mdpdns4|piy3smv4{n#tTH-~$5bj>~j1R3;0CwM1XU0KkJ%>k)A;V|)_bS4nxBFGr(W$Q)&germ>L*jF!%X7cc^rHdFflFA4mv*s+k!PHoX^_v?4rssYm?ubb6*Sg7b`Cep8O7B z&QGK!?2xxEh{Lv>khMsSPcCpp8v>n!N8a{iyu(J{$VdZ zob~`A;;;r=_i91*286i91q_3LV-MP)>92tU@h&#JPSAU-2M86n^Oqa9glU;$9C2~p zl1OtzV`h8K&h9OszcH-j$#T1y1@^x9<|AEkn-%N{P`R=ZTbH#1WgssEm0yOReJfES z5X1;kjEn2>RKTtTs5~BTIxK~O4Q2_5aXzf7vkERhich@V$f(iZvr(d7&YJnRgP;xvQ)kfUc7G9kYYsQ9POai3BZQlFy z1npf;xZ_-JyM~JL1EmV(=@v;C*Yl7e{Csn_#3j}~ND}ck_s5%3^pX&nU(Y@VOk&VY zfK=T}ihLAf42HQw{-iJQH<#}n)Vc{Kmbg9vlw8eW2mb(>LKhZ!@29rRR}*UUqJQ|7A*E_ZsLyx)o+7xy_W*)) z?F<920w{_rzj4QXgbX~$aE~93`{Zgtgj&K!IPODRRwGhC5puNmUxA(@B(>vTN=di? zp}T*!>xLEu8L~_REZp;ectI8N#RBwTNMnhIs{D?@FGkB@lFU;^h@RuoOK~2=qLZ~b z9fj^YN3(&hp$B}jDe4IZ;J7^l>K~3ukkQIp8+Yg)_)>~50}sQ=SUSwd=Flscwm79r=?Z_Nkct`Q zN0351TA@@od*csag-9?1*0{PW8alyD65AzwDc^g*MuZ&{vDo|h3$-LR7vUmDcs}{v zKmxqN4g?X1-?`WKRiTC!PgY+ z{NBVJ6gI?Gmq^Rk3^fLkCDEMk59UfUVuWH*>1!sV1m!SGPR8=oLqB4X_wK|Hj|(iL zEE*iqU_OYv0ZsMSM+0MGxO_g%<(1AoUVxys+I8p{tMW$iL~Y#f2m>S- z1(X{ey8&4w@pbXYIlIEO!EqD97CGW4J9|o{gC`D$)6uw!%{VpLr4iFYM8eQz*opMfQ~$UYjON95$85q+b&cwaQvSth#d~XQajiTt)XgWwY#GDwbZXW#DiTr>I8ThYv zU(k$I1?rS%w`)U)fE99781$cos*#% znFB~r2Gi3GH z4*EL``BfrSL~Yi)jmQq=Zn1Vr7#aiuPjSv~y{iScjEY%y+n6G_eT!ADJsMn(M&Pe-jl1!Js?}CX3!m;9{|2 zB@S@!vabrF4Iw4kIsFRfg`gEA^6D~9+-&i%$As@}G5-hch$l!}3J~?ppIU6H@hc!O zfg=)}A30jY{AU-9DX8KcVK!T8$3^sYbZts}G7t{ye^UsAT6zfsso&Q{RrU zmqv|;9gcxli^;p9FGDDpJ_{E*)c0)O+8x3aii9{uC^;RF07Ig5Lox48_OhuI5L4V) zL!D$!BDyg1J-c*`SBU^6BIf)$V1P#^9s~f_2&6stMVVnuAS&0cgaDtSrN;R7Y-yMV zgzHAu&(&VLUl|w`cO^_AFuOK33a#9dv|%jJgQ6*#J{+lpP=?Q-6DxuUp?q>49wvbR z-3XR;&LL8Y%Nxi413WqwiciJ49r3{V*B8A<$pxHpmj-3m6YL>fIj z8$Ly2f~_Yk=D{*R4JeflFTxb#eW8Cx#8Tw!Ei5)wkt`H4&G&~)zHjJhq0ap=ZSi== zs|edde|W(_5P4H2v<}JR(9b}eon7?U;`)zm0Y(T94k1;Gg&M5c z$?0mW<}hkOgLd}tc35GP1q6Ei>z$8QE8qfBh(qtv*Mvm8X1nVl6a>5YWrAjI9Ti~E z1oMl~_|w|aT8o&G_(-S=-u!}NID``?R z5swG&m-qp&sUR;8E7;B!D}u@*9`^7IylNot>QI*v6O*+aoMC9OK_q7x;RIY@ zKh5k;b_9SbsW-%b3|CaVec*$ z_ro_6W|*)FD4ku-Lcnhz4cxVJT98tB6!6@WlYQ7k5hV=P=bFy1Fm*Jv15qs=JRKs)9mfNJ2rlgag7uf-i90(a)(xwsg%qcI(&!OBKm#zPeE` zA=D}?EWm0#^n+dVf*=Nvaz=x-D>N#y{Mhb#-C}=yl{mRR1hZ7UXR#H2afvIXn5Rna z;h}Q~Cx*)+vb)RLI4~4bgoHvMeX!(M14@A`Or0(+oFLl*fmskpU(UTAYFw7!S@&*d z0=O6XDf$@=|Nianw!*I>Fq$6~XO zc$OD%KTpOXuO=v|;nU%&4E!jSDH*_i^|Li`;|iyFIgsstG~hvwNo{WhJP^ z?0~E9Q^sHi+d5g%7@ELRU7RHBp`{8Nklh6kjL(d?#klIiJiE6#jy9+EgOOs-YA!#!{{SNMJIE1 zcXvWfq7_HG_2NVT^p*4z*i-Bc5v%|`bTzm={^;8vDH>vFP?}vhRO&=}0j8e)aw@tK zYIWW-H}s$sWQij7!>_CemL)F1z_q<{c&cHh$tre^6p0*~lU`tz{bXrp2Uvi?4!|v5 zT(h*o35awAka@1_0qGFC0GZp<$qy56cNA=j`Q{gn2o+Eayj+ezS6HBk@&WhxJ}5!3 zVr#uPp@_T#q8owG`A>eghyx8F0^0CUEjVKpm0WSRZk~pj^J+%y2tpb-P}g|G5Va7t z#`xG30r3dEh0zg7VyV2STlWleqbTqV=c7-fO_9{pBLcxx0jISgwk!unt zB@8Pzlb0WR9pJnu?e}{R#mvx?C|vNv$#EZU4`l5G%el=A<|7ER(UiYAp@-OKF^9&1 zjP`9n=!|jz7Tq~goNUl5akt-`-NiluNjqYKwZ~6DE{DVyvDU^irwmA%SMmHZS`QcD z*@P`R)_)$n1qB^Jr4R?bIiW}?@)Bj|>0up8!IF3koIV=@#x4b?TmrqgSf7xe7-;f} z?43ZD85({i@V-4JGkU)1ujDR37+;XM~fy?KXRS)P8cgAy^k<~y~@OMS4Ojo zGqPynh=hpZ`ebz95Nd6L&I4BX%{1*4rw3C~42e)c)L#e&VtV>&CisvoWXpXp z16gWMkbx1V;MH*(#k@YkLAY^rgo}!i6v~k3&75i|t_VxU^?iNru$xK=s|f@7_F*y7 zDVDP|hmK!PZ+I1JLO3&uE2W3`__$e)*p&ndxIL0TM80FGaSh{nH^A=-J zV0L@zFcHONIaZ8a-f{;Z(suHoqmm#wH>(N?ckT5fbxjU-yb1D1oeutO(~pCphIF11h!)W#%+upHU`!>l$a#xn=AO$;%6 zh!D*iMkQdBkNb{mA0ovhtQqS3i#t40OzhwVQlG5{(5AS={#*FR4dE%q&QH1J&*yC? zI#My{gXnWxkJznZ9LJ%F@7MOoQp|f?^P(fl^Q}U_h*XJ})4ex`xa{D_jNa&Wcl3LL ztf|2q47}7sKy&aniW_+k`RT}p8RK09^X7;}-w1W!JQW(qUl{zR3B@3t(vN?%JBWoX zYDtu1J9Dt16Vd+6`?&AT1XFA!(V~-~ce22E0zDS*kwDZDX}w9(b0h_M!Jc`<>t}MGbu)niRzW(H+i3mp~;yE zu1Ou?Nip(U`P&}cJ43~gVX{yAFb;=eIF1&Jd_rB@+6g0xBnZbIXa>Wm6ch0XSs>4b z!Tw~l#1!Hh7wceT6ruA;nxWbck9PRV0)rw#u8i3@gazCVrW8%tDs&$6K>EwoREheb3$UVKU@sN5egC25@r(e z?^Ab`p_ws;0tKN9um^%-*e-<9w`X%xqwg98l^lyr%t9$5clo`Ltiv~uX%M_!w`Xe? z6J!8|Dv9~6nF!Dcj~%Kcd5QU!5DgY}E+F`mS=$bYoQ3rZ7xvi0$`oVihuP-N?fMZPSoIyMSwZfHuPa+%0%if6qrPmvg{mmg1rRVRpOKOR*A_iV1kbD)goZ4Hf8}x zZMH|p_}G(-0F-OA2zxdt7BP?AMeo^w#DzOVc!WQMT?UFl)hG!G{rh1@sbcclC{(IF z>R1GkO_Vot`(`q%A)a$1{CA+}PCZydZN|NXd3ZO2V`|G;oo8+54=hmuF>YtONp8~V zBd82L%myHRadrh3uOOQ1&uZ(x5JL|678w;U&|{AZf-+Rxa@P7&@90PxgV!1y)?uq6*r!r_Y~M^&MJJ15SwjM!Jl3m<5%(irK0NeR zMF*soKzr?x1E~$7Rj`?dM{|Q3PHGrA8Ks|2W^F?86nj?QFydUu_kIq2hZHLP+DwOlli8?%QM%v_H^C;l)QAkej+ zUrqBnoDdI4325ZO<~N@co{$e4`*BmDQ=8CbN{9`c==)7{b`(RSBheJ>H%OHuo38sMSy8Mvo$rQCR5#R#LIy3VgoyinXIW05F^f$g^} zdW2FTM*Uu5B?u*s=IZ#|D+XOvND@iU;LB-n_nusvEXvlg0BXncrvmf#c)a(VGy0sX&nVB6Ng8>4#!pq9cBD3sin_+g>4nOitJmD zMgszcA94P;b5u=K49sE?@^-=cX^>UJ}(%5XD^jYNlEXisihFo)R-H+3 zjv$|BXx#3iamNT_gHro#v$xAYv^HG4p+*irxsZxfDx})Pa`EAEwpSFdYdpWPT1EJ0 z&>(;PYi1fTCXSL(;b1ZZUcdAn2Z{-s#Dlp%o7!kdF)@;1Okdshlwv~g&arAd{N%DO zieVE#ZQHdA%;>s8UAM?sj}au?1R_FkNn9mL*Q6o52EkZwdh5Ykq!M?B=+3qf=R#1s z@QJglh!+(9OE2K7y=iD0Fe-#T0RZiZCZQsyCMzA!KsLm%x+Lh7tSV^}=(vfF2K5E_y+Qr^?-)!zK+D8_M9sjlFg9XLzgK=hVe;@*uy zq(i`cxXd0q4XD9tOvLp#VTJn?*6DCP-##3#%dW6d6!YV&1vei;o|5=Tk@Vfai{kkL z)c`cn_P(?FrMMw#6)ZGkz#~E6 zfs%HnN*EFsc7%a1%$j?e4RM7+R*Ho4ZGHA@j7=pW*ikrb%=&`bn3mx5DUQ$a8t(Ow zo3Lf>uTJe6`c8*)yEOqKfnPB4mYKst4@KZMkG2EycIyNyo+KC=K>3q5#lfDmgs{Ab zGH+k~TF&7UWSDcXNZ~{BslW=sIUR0$H-169Bec3qq+eVsDuC?qTmqfT+4O3~vo&oo zeWNN?v;Y)=MndGsTX6jVq;|%r<~Xkr=9%aG!3;`<`4XU%_ab-isZA;v?*!HZ2|urf2hJN}>8MoP zqN$x$0=SXRD$tdgBn(lczzbr{y*1xuN{Nqz0^`+ffGEXIe2N|r(TWK)NQHtq3bSLE z?9^~X!^fS=ijdGY4=+X}7jP3>51cuKS45hHjR}WobT;yW6{#tC1Kgd6+H;~+!;J2? zW^qF?hG6J6L7z~x!8#y+Ud9^TW z6ceUT<_`qx?RA0$#H8X@y_%KQ5J4775Os3CHKJd%Bi8aDn#0Aiz;!^l^l)%( zp>hsSMc&`KMH78PhmrMC8Z%!HbUCTYklj3*Q!llF2`oF6^vzHqCSN%b6d_#RcSc%m_5*sNY?z+ zu#vfH5!aiok?T|9hQcsQ0cdukL+lQTQ;C`rZJfh6HaU1F;aT7=x76lxuRvAg_B6~f zMT3SG8X$BJ9BT8DHfR~3B6_tkQ<2;G#XW(BfHC|Vk`>rM-zp>}6YTUvaT)K9KQD4m zB*AybUS-lhPn5m+V73%=4Te>|Bk3NlUZB2IGKLWMABExCqJ7c^56lq)^~1AsU`p@8 zT4BkbTm?vs)t1oe=pUZHIq*Y5Hdv+OQRXLv28|`eo<122&RjijEbr*CC7C#0yk)pkNpOOkwMYOA7J3zW9w;t_UqbT(+;<599b0 ze;zpkado|COcF>)1s1=(^?6_@g*ICnR107`B$hOW&4@0xcV-SmF?xprB_h_@-bsu7 zfzpPNe%Y6<6aZ)#o^Nk`vkBsjIO3`qav;S13DQbRWy>r%RD!srl8_%?o$w{J8}U12 zw7=f?BB89vPR_IIR)<4G9HbY4R`3vtD#d-8`8|247K(Z1F=diphT#*q5|r)GXNcZy z>12P$?3HjPT&b6in89Li1fj!jU(ADPC__G!cUN-Gt_?mPgwSL)0E1m_WYs8-k-(jM zVmz|qpmPE&Vb$yvgyR-B$(_G@@CjmscFlH&(T;6*LBv*Of|cHrGl%59BGQN=!}V|# zwlcDL6jx$Fu7_ye5xr_pcCKxs7#=+mG!+L|o)giFV}^T2{9%B?^8$H^vJ9@-*N?aj zlR@-FJ2Px&RQv#C_KzIKFafj@X=P;}a(d|8Dya>x4^0TUZN8F2vg%x=B{)>M+)q+! zJlf!#p1*nD1P9TZj9K~M#-CVHD5AE*WRnzEz90x-h^)B~${!3W5WEwEnrJjVZXcDH zVxz;wJ-JMSJQBp9CojY8kDoqSC-N?beL$7#GlV@xCk)-GJhZfK^%B;z7~!V zdX^kxm$N@TMTz_agHxez!(bE>Wk7ZYN3(JqVs}DXA?0&iTVik(qZpCC_QR1T<|yPr zD#urj+@i=(pWNWs^7Gg~_?5sp2*U}Ku%7K{C`(_69hEw4;tfj#39M&N7Dt216S8Ar zA$|Mo;mAADvq&ZAo8crBrhSSs)-Z}h+nj` z(j7ZbK^%YFDiPum-?i5XUe!|EVYp?FJr>Ha(@YTYt39L2Wd!$yynAbIGfa^CC)>XB zgPWKXHQXJ9ij>3-nsPucWJ~C7e?w$0kW0kaCvv*aM5)60PMnOfjyPG6+yHAFIGJAG zD})2^a69+=AL3Pvi69zV!c+R8QM1ImUdk+^pQ(*qF2&IOMsQ#~PP7-&Zk+Z#xF=wu zQUf3@xv^WRcN@tXv|kVVaQ!6TR2m#V1$=O@D?=00liMJ0Dp8D7C}?`lO57K?_ zY%tiJ5p@&@bTWk4#^g4Juy{Q^`uvD1i>@`i8$NxQJgZm`4Gv>8IokWqVq=2$G8Djv zWl2Y6#P@}x*gCa9Da0AZ7<&(+N6$o}Alw{hW|3Se z#?*a|vJKm4KT6>k?1g~LN27?)^<#plv}2FG+ltf+sXie1+xEUwr|6JF`=v|hQDzT$7O~byl~~uE?T>0 zvYHap;o$zJLlUN;onxtlVEk&Jj}KI-tb$0zobbSb0}&HaRZj~xR7T$U2&;+H-u!7P zCc7qYEa%z7Vr03RlV@EQ*^e0ubX4tlG(7aM7$)I_5CQ@9C@YvyefjcFlkA^94Pkjf`m%f_%bv_~eO{f(t>7%Em&3P#aSqd3-%WBH5ZS zd?EcWPso$`2n~@Epy6N#xRPEQImwa$0&*9%+fG_^f{w$?I)vnu1PqM7!%Id{MCo#b}2zrSH*{S zjn6PbLnN_JjzdZ^dSR0UCjQv^8l|y-Nd}}$AV~%?OqJwDzIUAu_PXq;4szX_HX4;B zL8}xj*svuz;Rr5+m;Jh@pT<5KmKCiqsRjKEDy&a%$;h5Ddob7`1Q47a@&w^qH%=(A zh(tq(+5FDUdkEiDkYXHetfxHzC-7L{(LmNoqopA+$yE<}#*M^Bm8&mrB2<|RWJ~P) z3iPWS+f%Q0!x14%ecnGCK@N>Do`MzeV|QH1+R5IGN9-O9VhiPXFipo)=gA_*4ogDb zqsF>wCwxehIHU`hD4UiM`wDo1Asu|-@v&E1If|fyA9}|3r25GrZz3_^rw?O{2!@Q> z8IJMd-eJR%nAzNXPPFHxQ4*?|!2I%5c=5@g??X|`i|9e5=mf7M5*6y%cEl|^M=W%i zdJkRA2_P%Wl*5zrg#-;k&B$&^Iq~I>jwF$>5)OuVlF#O)H6$1sa^|aS%M~M_W@5U_ z?%P~nsf<%Dp~zuf?|q6$nFuz_?z+>_5VtgJcEPB(eN4W@jprJc(jAwmt)NTb$nDXk zy#!dm`V&$Zd9+{V27CpxFVA;-SWApK2>J@6-?MI~n9Nt`MDP#r(}ZUyLk@#ef4YGLVJ^QPK2g$zeF1)|Jv0(%XL}h3eH2h zLdbF8kb>_SaTSQ`)RV}9R!GS~LJT0qhlC4gC*T!mwt-zB{NJw0ZC;!JMfXoc)q*R# zcG{85b>$c*YmU-9vW6v>8!;A7sr!Ga7;kK-9&$zcDS(*p;6+SyS{w4jPeEy2p!j>Y zgs9;oLI~ht?}h14fZg#-LZ26&J)5$#(AWH>^;F@c{Ff9-W|*$Dp#(KutUI%2bFh z$_>2Sy6XW+43Wj7>PMI3vnMJJj?q)GKsPo)B%w981cK8c1!|nYfoyrts+44d1gN~q zaokOVV#pLUJX=rVJ|uiRaZ^BHmpkWkDTc6wVu0!DO@x$=vWdk1+;1TE>%`R%$9Qlk z#Hor<^jD{?;=1X6g^+xqMvy4jHGkv|n@Q*ba(9CXxKxCp@~v9CRuQm38i7GL_|2yY z(4oqtcF(G~!hN4$Ib4?0+RvF2MOh*?#fcC6oKQM&`aQ`7x(U)Jql-Y8<4YxCKS5qZ z{JUo-wW0SA!<;SJ!;mgmBFK8cIm4GeM?tO%k}Zu-rppACWqXgC~=a2^tAmNG=EnsdJB;gI~q`bBXD1AB_`3 zmxy;b!uI5>Bp=Q3Yz2q)oYN>KX_&%D_TO1Dr{Obt~70ApYE(PLGQxV-3VnCDpsL>v#|~_|jsKh)T$=Fndip83q4# zF=35Vas-nni$tT1kTWXKJ$m%dpADJd$WF{F02yOP>znMR%YqcL7&5t8BgH6_31ABL z{l{)5WV<4p8}okYsjMiLJ(Q5!^P^jFk-0*Mn)f+rPAA78v||CA8-++$kd zA`mGlY}DDUjxlz@R#g!pU;UvWg9Ru-CLre@ecp<*f|I#0w&5}yGRTSyE<^BR&vlK2 z@oKYgq$HLuVSbjEgHy>oVL6`;@A&6WB!!=1CbhHz_l|#P~J$JkZ@pMZ0M6% z$~ebBPha2r51%?7K-eSG;K^0x=*7^1Ax^|w&}-v@$y>(Z@7|2GSH2n)&b)>_s|RwK zz%D|OgNFSi5EJOGNN{L`uoCAYv;eVsD(xZ0>;M)gL3(5F1g4W5x9D(oE+nt9HGscV zmZu+kwS}A!K_QuN5QhQ4Uzxz{JxdFM?vlY$GKijH3%x1{mC$qIWA4~M$b%qHfQno5 zD^rvrhoh75MJkkiG$h z=WmAiiPVS!6&cCVkABRui=MujUQBf&}91 z2k0O{QliD1KvJUp^ykYddohQ6B6fT27@#I5#-&D8R#q10P<5fWxp-HyXi3Z1Q98Hp>51A9yP3{P&uG_-~Ku0yV!Xg?#;_!!}v@JQYhLC zX)!m0vKCdCSDV2^fKA9sF;)XUBm}2uBS887xzoplsWd^f1Y5^QxxD4KuFX5~dMbnkkC%^qAK_>1p*%R1?dUoSdx(HIkI&7*H$11T zis-Ys?`z7oR4+~j?6PTj{+h;2GI0ZwP2W>Zq{66s9gZbEzFlnEAlL2gtR#5OT~m1V zZK?=m;%7@hDRLH_Ks0M3OT8WJ(`7<*#O2RJOmK=?gy@cgH&}JUG#J1y zk}Cb`x()E17e@vdg!LE)tTDQtrcJKZMdW7eESPfHaBa$V;HJGk6v5 zr&k!?|1egwZh7K+psJt`pF7wx4B80HJHRxC(|Zk5^Q}!7`7r6Hv$lS! za32%Uva5K6Qq~1+I4Lqe^1l75Q%U)#TUhu_Pd9pG)Twfa3t?co6XQf`uoJ0Jp@l{P zQahK`19l6h;f~_U$ZhnqkA*mto7^v@ap$igNikKMr$%+KIym4?s~p>>j|=b=NX6e| zr@OJEhb)|K`$0>?vKwhYrXe%##=x>8s#Ys7!3C;q)H|kDQ z;($m>u+#=U4A1!6r4l)dpmcN8p&1+z>DcKUl=dl5B1j!?EhXS*4)45DUPy2~@+hozNUeKqFNK;=wNbW4K!*bmb z7$L<}e%g!O2x1F!TRn|^@-rOj*`l|wPtKDI_**|767Bx*i=NhPL)>C=ft=CD#;{Zs zq-maT=w)ko_JS!ldedcXz)18{{Bn8=6%EQYSs?V3mw!ICWzlC)%E47=8`k;|%JqJU zAG)ah6tfBfBM5ozAVj^!u1Y^l{7q*I3!|_0y?TIbG+(E zQ&ne}hCGi8C(HDUkoKmYZ8tM^P8L$@XCxTPHvWgaZy^>cGs4NE{L|8@D# zwh82;50_wFk`8Uqmkj+mJ`<_jA2nk(T_h7y<1sws$PoerVb=`9z=p8bt{sYX&C04oPuGXLWkGY;MVgA(R za4BS&1Cr60?AKl?s)@YV)w)I0QXi+7WkIfGQvkDJylFuPQcxRiHd0Gwm+X%xxogd42kUztl=4vn$Wy%bb5EZuZd1m!dO$ApQ%D2{h1aDlA^A>4;y<9msl20?7HAt`eV!3fG>97R;P;FeW$tr+$;OJ$;Z=;jC}l=aoD- zMUjp@=&N&bkD|&m7;Eah*aU7Qskz>t>7AxU6?@gL7rl)=g&`8856|VOC`JSksh9YE zHJBQ~EK6&D4*Ui5Qs-W3;&sTf8fL`YChO;amZxGE?TslMxNsR|4O}L7FMrh9067Up z#H9Su6GhG&Q0_*$d8z~w8D6YEq2>CvJzZ5+qO>4Ekd}IOSVdyxotptBIFqB^jS!-| zZvVAntqYHqrtcTQU!!y;uo$nH3l#(UALI@!XOy;y8Duw~Z`-$4*(8Jv7fe>a-j63j zQ3i!CN%!~uR_#9Y-bp02H4GK8PP zL)OnG>VG5|%A;>+i?RsCOZm#%bt}DQI3)}mi4McGc#L$H1Gs4w*)#sdaYUlEd8mQ` z!@g3U^?JCf`1tW&Quh6|4xj*4RgsAiJ zB7I#U;P9a5_DE1mP|Hm&@vicX6mlP3xKy%mWoj1Mn&~1 z0X#Z_aJ`a;L@Cqa3ERG)gQ%a-v0?8A=@-MiNVz&@tbYz(fbK15lfykg*H9^wI8jcw zXHdB|60z>#|7zUF&E-pRFTY>5P=j&;ks_-nyW9_f84?Icj(yhKzuO5X{n~yCH+B61R4^l<7G*HT~u4E>#10q!)YY8k^}$-dPa=h(yd% zHe7+Kl!%Aie{Y?F1>FT6x9exP+JIVzNK4?Chr6~McH3Dxq2pn<<#0&!gqo*7uu?Ya zrUZA+nxf^lO4xp3>fwj>zSl39HnrgCb917JCPKA>jdf$itp$1mm1tzL_i8wnVVO#o zAjZk2CQt#bAVhXzTr+1CuikIJX|#Ny2Ga4-`}O{+ZPh|Krm~7OyzMD5i0;X4yJ^M- zrDo7rpba%P^(H0+o+|G7(KW#fl&TY7n~dr3mG16cd;?a!e-0E4kQ~JL@wuL@(2+Gw zwsUwkw?KKFM0pEJS*!8_VSkY(ETMMo!tn955!pzR_f~T zhz75okSZxc+nm*^XQW%V9Q)4Y;M8m33EfRcqCvYZCnDYecVbvmwTXIV%6dL_3Eo2I zKDm34-;h+)Kqg#jqH~+K!eof(Xj-QP&yVT7Na;;dU#g#hulJTF6plE|x6ggDBzCcg z_)@on=_7ln%oNNv6i+V9h~4EY2NuqPu8_R3TXv8`lu%q@I-wB^96_1~G|>1AVym`s z`cb=Y)6nFMcf4?G%8#dRG|!w85`@7T0LjbZhQjIe^jnv-+x6~E4} zyy>(oeusvkk)pY2a9v1EPb}%c-g9c`=)WkWTgic`44xyR%C*xrHv;F*5qpwl16h!D+btaxEE z^zTJKvJ>w^z5zp7j}ySo?R_;(-$Ew}fD@u~yM^lL)C8pPl#%(b9=Tg)i!d-9&zC`o z`JC>D&^pB97v6OJ0w3T5obB8V!fDPAs2c7JkwIp{QOa z=$PF&P_=at+*7N5klVISqT!r5dHf&4)==+wkYaLIb^+eX<{TrQ%;Qj$t)Z7NTryJj zyv%>Hf{2p9y&>X857;CBjV5~2!t|yiNj99V*S1dQxocwXlHbNPHOEd?r)j=I)Vc9E|eCXJ`pS4TlAyP8sIJqBAVZHcj zKRVI@-jc*rj*4g7e+>lA6`|<7ryEWy-u_SfoPI^QJdPmedjN9C=xXg15a#~6Ev1qr zTH)bX57&WmMAerG7Pp3Huacm%H-~Bw67GzGw2+vg|C$ymOxoICw}Xh>W{KGl?GgKT zx~+Akl!RYz$^koP;z%oit6sXs?%WPaQ(LRqC5=g-QL@qt?)p=2iF0IwRqm^oPQg-h zh;WJ-|Ixbqddlc`rY)(n(>JGFpx$Ehpb&k!Wkl$v#9eE0+POZwfPzS#T#q&J-~hc2 z!LqQaJ`!$UHFa^lx)`6sc6987CywlM71e1}6ZYyK!?4meTKGX>`kG9;>$LV1)k`Wwv4nQ473q(+c3OLzpF^0Jr6I!jf`T>`(Pl6q@uDNa~NMcJO{>7 zS+HaPvVJzkA3YwmFax$l!j;&eFbcj=Hd#kLjaKo>S@1tT7UzQF3h!i-U;9!+Ka}8F z214KTOsRRXm=p26_LL@7@DN&UAnMvvh7pvVG-jq}5S>}J2@aotrt`hBBKly_qSnEA z_*V2r{8;bUP&@=!#*T5jx@$VAqL)31%&?cbvz2uE;W0I8v-P>BMHw^S*uH;l`6uds zCvq-7OAdZ}@3)7j!S%i4ZCgW%y5ji=DZRH7r<{x+HKy+UYop*q7kRL$k-TkAml#45 zz1<+}EwmDWFOYm7&riMnl%_v*CpkT2SLT=<+WOvZ)t-~Qa{6+$3mnLIyj# z<)Hx{5&;DNIAiPK;2Y-urNZY+n;OH4Vj@2C(s^*@>cp$lW@}*c$w;5!t%n2iqmSX? zf;4ujCWi{cbe3}f0!aVS^L?a{Cp6&O0rw&Znm(RpaNSW9`I=qwg%=+3`|yx-=-^_= z3zYlr&QMq_P6jXc?hMcm-impvJ2uHph;ecb-P{saQ*lQsU0+&?N^?G-1#R}BdJ)&- z9Cyv(6myk5Ai||ZX2PO%;s5C73c)zJz{mbI`l7itka4!22iN~XjJG`FO0WoZCA)fk zWs3avkgyyJ!f73C#-|rHR5{qR_&{FHA<;IyKeE74(67fn^F5b2=ke z-DCikc*+wEI8@L9My1t>NghBs!|DS4NRfGO!Nv0ElwU18?5jsPsF+93grNnzD zoesvijcyt>2_+LjL+16NGZ}^#io${{w-ulTdJy3cxrUw)&0UZk9fTnYyl?@e9EU_| zGp`Jz-oe%gy!4jOA!F8^gjN#*bx0ZF76@W`%k!M~L@VskV2okeKl2AKuNAA%{Xjrd zPH{buBAiDz7h7jX^-aWI716^R->!N`f%BMjxc{cJA#%n0gmd`Qmz_&9Ogdfk0T6FP z?>1B5$9o(K%r7*Q*L+8YXf!1&T6fwPC3No}kLoum2N5Q%+^v14kQ!smPV0@C?&La# z0nj_EM>tc*F->W{KM&hjKZk?#-K6v|yf;}5PW;Z}P_3X-p`#F5^ngyLfuY-Iwew|= z6BDHavqU~z99z#4@wrPAi`-?#dV|}hrX>;D{x9sRR7$18!nw?63JF> z=XuacF?=GS3o3ePeWWEAUirn810CKRg$Wmt7GoO&uo%ty6fCa0$B^OFOD)q^toHJf z2P!k1?hSo4&`((EV;_7iEP|d!YGKF1EI7~b7-{h{y-)aq!yjLyCyW-3x9t^(Ftv9{ zrSWB5UJ8d*CgAyE9MrkjvP6j%&~ZJqeOcnw&o3Z18|@xGyaIYM8XIwA#X|ie>DVl6 z+_@dtI!J0O=rka9eN|Tmj%O5qj^aG_vw% z=Cv7?udoY;e#qnugF{>S`{sD6DL7DJo=d7PK&qrPQBdVEg3C3dAH6&#=AtW4b2FCM zWU5c;s;qw-{#wX0l~ca_(K98DNTo??{d?PcL6%bJgE;)v^?plmpi)j2kUH*5twLn7 zFIbwJhwiAnM9vj{(Y(2ByQDp7noOc_t$*(qq#=gRnf%Qk!!T7EQGJ4my8V|CVLWy{ zfYj?oTH34xM-ZI*8g+0EFi1&@y>7aGd+8bIh!JVJ9Uh`5RMOv8xc5UOiPFtW)X;xT zAHi5OQcaOysT@rtr>Og@Dm2%c43n`K{z3o18$hXIPP+42BF>u52h~_fx z4TUOi!#|p!@xIalBJQu?Uh7Z2luG(VHD{6fZ6hn0kQnXdwX>8W_wZi$=Sk{}h@f#|`_*^6|lmMW1tkFz`} zoitdF2n%W^Q4cvyTS5^ZN1!i>NfVVg0Jot$Jwgf#W1d3$*TLbEb6>2$HO2CH~5wGx-Bg)@1 z$%WLm%?23aKowvbsHrT(MCdnJ1ZuSte`bf}Y=-VPtS!nXuAK&J{nfApUY}B?>rXw5 zu&+>LN=p`q6F&T$ickucdo?7=rjq>o#|AbeN2$y4N!OR-Un@gO4xh_ct`m=Mg))NH zuxX_&&=^!o;{3iP6e)m9@0oTBU66#1&8uT7&T!lIYnR+zopc$1r|*48rPC#YmODQN z_?)ED0cXgO9>n68j`{^4+HiwoME*d|JO{3Rubn=ax|+b_*6TK*HWz{oTmyVl+nHJs z2S+&AL}!;Q*==4HvUI^Q8s*u`a`7O_&-IM7c}Z;c+j~x3pI^V{Y|bo79`qVZYXjl| zH4pE7tRpKcxeJB9dG5!vQHqkZ!fZRTQi77IV&siphx9^9A@l9vs;b%DcR}SU>-sap z(fEWu4E9;xjUonLfJNB;coD-2xcIwtWoj{XOyviuLAE2x;_^Kxps2Gzl&=@m-ds8$ zhvlbs(qTc==J6QGEl^?`M~y(Gl*6sMeXh$~t+1w_oIXKD9SNZkXHC7EP_Gs#Izi|B zlhDrVGDkg*iGJ#!MMJwUY8TAKUH7k59fP7CC~YvTD>Vyx_oPIy z?=!=?;D{rwP@xBM7`b4gYgbzZW0nRH+)am~@*9bP?xKfg2enJ3kGJYo$p$4N{nzBN zcBiW9uF|s!!+#F+bYHu0Mf{&`n&0@=VV4^2v|Mr|hO8kb202XBV4WGtTsbHE>D5IC zybPsLWv;>UAD;RfNzx)C%T+yeQKv%6NvcXq#I|jzZ)V0AiOn#a&WD&Kh8vy6x;>WY zhCr;>6%z{4id*z_5=!CzO8Gsq*cH{z>VkDaWLV^c1?3Art3PUU%+Gawn7(Fdcl`x=8kO)%pjXKzMv$?RJQ${IXT7N0aDG-;D z^y3-#{z~pHs5rvjcSGa~F;j!WUFBx?mwHO1D>(@-1^lcQ;Av8`^r{-%iq8ZB2pe#_ ze?9~iUW$VCrOi0^XjgKSmo@Ov+_9_`Q_In4+h%9kUb%p7db5~UpmWmBpZY7ASqUDK zrO>(NP!cst|EZlAhR+rjp97xK>m1D5wY!rGMA`Rk#+lKR5#beex$b}GxTvOuvbl%qF`+8O<1Ov_8(?L<$t zbaaNU9{yD~=PG?Kq#Pof)^nQ>fr5LgeCy69rm#}z8JOeu?WWbZXcZ%B?IL!lxJk;B zq6>palDePn@+9`j$GZ8}Z|;^ncgy8dys5~Jgs?c8gZHse#_c=; zgcB$7!^1Pak|~`8-@7DZ1{M|5CC{h$_+#@KcfDY~PnofgD>~!qL%4HE7k=y;<2qBQ z696Z5a?CiiUFA`@J#`JvV6=ch$tPY!-2=vTUgKH4d_&Z&=?nu5!v#Fr)jIwhB!^xA zkN#YEukj1~eD{XN!(V#(sgP4>NkhiA6aGHJ76|ZZEZ)mF-`m&G%C-FMwe)OeR(Fp# zh8+EwFnqlysafqSdAksU4^!^%Lr;=PfPDR{-v`GVC?&>y`-4pm=B)D+mUb zx2&2DTJi)<<~d!}ltp3Wd<@SCz59cZ&uJiv&W?n(?VI^2--r z(C^8;;(vW>d+j3cqZ^USAa_VxaN)(DpD+bc z64UL8(#2WRVoose?cOg^h5Sa8U$X0Mq|X+|kyf2pBz>MZj`oc5J8ftCSDPUv{`TqB z)36XqILXgJKfd2?KC+R17ebSYl!~m1&McEmq?6ptu6%A z{H?c=CNl0o?WI-$nXK&x+)R6rDe+u@s=p7R3ZQ!X%YIikjk~HSRAJmlFyrqfAyqi< z+`hFCQO4!guqD>-Z-cYILDRRLaK+Q}a2aCmuJrkw_S=W=HbdzqPlZDL^5ydPzGble zbfP=idHdEG7JsjZiA@7~-Bj>m9Oj1!>w3@_tq!ar3}qNRPo0K({#9F?N9xA@9B!ox ziVCnif}5(a`Z-!H(m2@p3PR}jXVfwBt?!T|naM~=>NK4_>9l?I>fiQP^ZT?laG-7vNI&cWs^b_asTc6g!Wu?Xo7uMRc&H_rdce{tnreclbBJcaTe< zb{+pQPn(QT<^5)QryMW`4hQyP8B31wTsgsHn`+ez^IT=Q?%&=k&h!{%8JcNN_-aLYTq*0pG!UmBM&n|9q1W?I_075ziHEDhoP52iq?j3|(7`#0&sa7}t_1=} zIv*ZYWrnQ$eXl&%`A8_0l`jl=bzETx~Xf2rS#4KcKj^!JPoI!um#HO4ZoUwI@BvRq}`sm=tG=QD`U`!tgRR(xv9 ziT8TB5O5--np56B&%Ulf`fa3gVYm!5uQi`1&;sqd>M{V=N+hYo5{DOW+xtg*CMZok=l!`n0PUcHdCym2)c|~67 z=GzAZH`}LfMIkb%%H?2GPxRjiHj}d1x*YehClh{5u3?)s%F|(O3e7I7SElF7FslgK z`LVwK+}n{}pCrx{vJKYsL_$yVwxn=A{h!*_vfxA>Ba3@q?M7y#uTGXujXR_x#qiB%~EvK7LBq4_+z+o)tkU`4y6Q<&f+KZ6!F9;{;~+Ss?+;>gM+~WBy%cf z={XX!_QW(7y=13KHVC=p{vGBBIZAP8*bG`(*7GsCS8C>X$*)D~o9&bTck&M=@2xEk zm{kWFZH73R<>ye7q<*EaB&th&dFXpFCl$fJdKyj#8KBfOlz>!^Ft&C65+;t?gDYoNkOuk^y@>{9vcUgo<>`YW$E`+slJpw@}Augau#88 zo$Go3FK@$W{C3+6o4B-P%)bG*Gg%+B|rk%4iH%0rOr&E3u2N4k3^ zSqCbdLk~8u#qTsuA8SP}8y~4^6O3DRdfZbgqAjmFHTb`Eza1SQt>=jW^BYB9y?-JH zxeTnu4$1CTiSW(U4>skZs9yK(c*Uj;HUNzW6RgBWO=q z#=%f8clC;hC3|?U{NHRJurdBg>UQqhblIIucTj`E1ht&)jwA|K!hlk z^`Yx*{k=jQcRkREOm7_*1i5|1z$q9X90>@Djv*kyco_Bfni#9q=gx}?20z(0lv7c< zG)SAy^ezoUMU~ugXLKF`v4YU?Mmeyo`;K-w?MFTVy6$=R`OMsn}j>v z2f)|jyhh39@u{n{jAM7Er{S%M>-9y);(^&#PGj#ANGi3i0|@%y{!7dy-c+1Q9J{~- zu2AL^2?3019;gvb$|a@7vluD zlU5c7)&4wy<*;MS6>y+jYzrVTF=m*>M+o*$DyYdJZ(W9UPGZz<0Vx zuCcDl$Q#DzK^f7g;vaPh9#|IqZl{GYEPu(7lMoW&Se1@StW|UwCKcLZL(k-n6vBZH zb9wdjtLzG)K0miA68$|lJ$e6}#Qg}Uy*oLSA(RBU?^CU1rdUX7HNUq{ zSGpXext5xVI;5&UfD%775!y2~PN(u>DqSuo-HRuwn^ueKAQ)~bw(Y9g8Bl~Ib!R?*t%^urj7c2mCzwqc zLvl0B2KV-P{dG7M%FsyYU8Ifg@Ox3!0H_Wr8R?#8UbskuyQ&LSA5!CbhereBb0vId zbTWN4MEvIY@@{wzU2mcxLEfq{nZG}bR;^6P?T|J!F5fZLZnXTczsIDUm>o~ojfhGf z0noY6jO|O$n?yB9KY<-)=pN|IG3@A()7Av$K8S2U+f5Bjrhn9H{yHf(G0 zB9?%^zpXp!K!(?Xolci;pK6-rWa2H?=1T>g5|zvSbPutcJ1S5^B>JWb=5Fb9mN}64 zk;U})9e^ok5(KGeqO;Oz0mA2`1~GPitUq7(^qj;OzDO|o(zpdLb+sEg{2PT-J8BYg@T7Vs(VSF zUPX6M%UG)~ot9Le5ggpHcpQ8dTT>Grwh)eA9w~8YE=#Uno4l<6p>Jg;=gF51yN9Q( zAP?lnXQ}*$qfViR(X-p$dpgq%nW9`y#iqv>k_3B5?_c>8J#DDw=Lfo+Vam2=E19ba zssaX!JDe6o4XFzr5y-87SJD|#PA1pa!KQ~p=v<}uKi*23U{C?KWoG~sWkQdz6L^4{9rYb@uA*Jq7F2TCF)P9sja5IF@f@zwWKqr~ zi?yJ9=xIYtKv+t^@%q%e%9cgGjNn%gLG|ot1!!%^lz4$}{IvDDUlr8u?_uNv0cLif-1P8V?6rO$oh#h$RO93) zbS%r$uzzA_z!hz0C}!_TLphMG>FxQB|k{WNH+U}aa+ls z;yEz#-Ar{Q(W+mHNjMYnKG&_wVU!~CT;@3tjP-0B?y&I7v$-C-^-d{hw+I3 zAXOQ<@=Bh0wDUmX~R={WKNqxvnqeyokwPKhEOAEcjNnQyDa)^okn8| zGwF7Ft0N$vEXX0LD!SiPAIX_#$`q`VZq zZ!#*^w~e*_|M8`!KPrvhZL=c|z4rj$mfCw-*7VSKz+zx6dTCqejws`gt`tK?1R z*4h-=cn084(H&IPHY;&IGd5$zwo&v>{W^ zN*y=`>%FbK3>A8gOwk~8HJhty+7pbX$rwL6gIaE?0C7kV1v0y#P{C z_6ZE;_Ti-$z&PJZdD!)J$r{XM6_Qaj4pmJOIReN@Pa;c0wK4fntTGFWaj$sT|g;Yogk;4PN5fr!vAL< z%17p4qVV#Cqn+5lSH;JPZu2R5A2ui;@JzGTo%i?q#)RgfnybZG9HBr@@d00 zrn9g@Ul%2ytE`f#Ar5L5tYSkLrkEWNjnL5O&E^ur@I0cMWN{0^faV@zp2XR>>;y1! zGpYio!t6Ks$vECN058x_d7lIYP>@gH?_a;X)@D9LzgZE|^ZYK4oEbk$iQ$C()T$h6 zY&>bM`(5pwW9iD0E`$Oo``x3y~zX}utaE3biJl(nT! z1b2p?THfJx;I?{kWZD|WKb&Ku$Myud>c7VnJe#Tm)PU3>Qba`9C+U*gfz4!`ZdKAB zma%+Zx?LAKb551q)gEC+a0&%eVatpC(9hRn<7E@S$(`0EY@8fEn!xqvszaO^#-<|4 zkwe@I2U9#1woM8;eF#wQxQ?lbZ27JkIWuPifmEd4kI_UrjS~}zmfXHS2c5&uOW=E9U8S`|E$fU1(04XZqy$G2~2Cth1qeFj5$WAx`6!L-SD&?Y`PYN2)Qo)_uIbU z4^JaDCV~$#)bArHz(Zln?px<~Mgjt)8Pbit*5?nIL?Y)D!M#-~XW)5h0jJ*I5ATyM za?wrFUatBy_l0v0RSwTV z=}Su!0nbzK6WxIH=iw+j`MK@--O4^-%e4j?0WI&zP5!t5iNWw$ZXAsOEHKDHe;fV(T`u>Ye*M~u`Bl_wZy!ABW6R!yB z=QuXGNJvH$M9xtE_Nu0x89&>1u+<9;`061!SFXP2faizTfhRiw!GSv9`@b8(UQgRTsm@ck^ zkEBo*r#TSgX0XR9Ul;ITEAVC5F#NK;L^3J2?Ri5NBF$)=9qRM3(orB>2UU0t@sR63 zQfY5vU*js(xsjbA+vs~G8u}cs)FI<{MAW!cjb}$BRa`YG^jtS!s7b)o4cqT({WO1% zbpX+rC`t8v<8s>q%&XU7uPYMS!}&DNAlUMOkF*iuq#!|xxN2V=@#TC$;;Z&)R2*M%_SrHwz9{6Px8OM8!kGEJ%nG#&nGAzOL z0n|r3%0b$PH%^OJe$41?xob*z^q9u^Fq>`X6b)aTM3_5HQ0-6SE9{Y|7PU_8%q-O#l0)ml1VeZd=q}Wzw@F6|NAjynIU=7#H36wJx{EhhB8aE7^Hj zzsa7mCg66S51Hy;fTA%zxIZ_dQW5j~3L_!-v` z+qnx()sUa4+$H=V{OhgE0fG%JrnqYOUOtNK!&K5-rjy*ia9$BrA>UP+#;;~d=Hu@O8xd%TNrJl<|?cOsgynYuibV~^~w7$L#w%yyA~Ic zeQ!Ph07WS%XeC-R#ht_~jml`S@yn-aDeUma?aq>f zpHUpciWiZ*=Wx}`sWja~jSB_krOzCQc$p(jKEEfFvecxcWa651Dk4u`9!GS%VQGHA z4klvFWkb+GhISQdOmwPG{W_;glA#UZ?ewpo>9r*1lb_20`F1Z~J6?Hl2kg5G)P zRAevPLXtY7TA{NWpTTB(by}Bx8mH>^N`!7TF3G%+IB{C$l z++fTRfmwFBsF5PON4t8Ll7wrzx@sHladXt#Hmsm3|WrDur^{umPM>5hlMns1(fP+An+d_JvLv<*J6D$}0{r0B$+t7qF4g_cK#;sgiYavUfLX;&Q=X#OY zQhFoBzHKQ50lR4ZQ(F2{KgVQ8RwY%;!}B#lP3zdrX2@#kvWljVD%qjq&J4;R9QB@W zU&dQDWm`F_YJIPZEJJ0NIb+c=3##eJ4DKap<0K^b>%9e;P^|(Lf4F~YOMpDDdvGXx zuTQ;4mudawsFJklv^~H@-19R{($4UavOg`MgbON&`o_R+r(wZj(I)8kk&B8W=w=%< z1r(yY*wWQVmZ9e}onCVPhD_9FIL(e!Uj-n&Da(3{c0i_Y0+2t~el{*IbZ9@*YN_WR zBfQEeAMZTEQ0g8>W#Pu|@mj{hzZA&q$&p5UwgWA_&X7{ws0m&x$Yu|zekWSI?k>_Z zkCs%K5UW0xBG6}4gfryVYhb7Bvzj+zRfNmb@ z^iZsIV2=6$5K`1-{lH{P`v+&&?&1^S4>yV>pUsWcL)M1ttCN7mE<(RMM)+78I>Hu| z{a~}9snz!$z_W2`MMuL%$NSa8J%(WO`|uq8jBc;&VT-fPa4bmKN&8)s@9CcL+-e{RGr$wBBc#qo)kf-7!|vfwr~#2~Tva%7ZBZG67w@ zw(oTZk=B}fpFDp^Eg!RIsF1eIFF*O1SQM0l0uPNFkGA&NMUpG*M zWkYh}{CMa8uKw@;Ti(qvsTc%v8NJU#FkoCaVLZsUhs(~f0MYcKKsmDGn@=nyu&V}P ziXF;HIzBm(K$dt+pT>d%jH?sFCQCxE4}z*0l0~t|L#^krZtOC%h*w0ChUd#4lbufq zb%(FV)Z#T82*2T>#G_`%<`VPA0o2^OcS%$N(m^*cK|lYLAiE=&>FL@{_2L#?NrZ5{ ztJV}^9RDN&NX+){k|WlWe1f%ylc{omd$}Kvr{O{Or`je8vo}cvF zj1wu%-S#qAdU|xfj0ILI08i2uo4QGpiS0GKhn$J$yUYGn5*a!nOyGO<44dii4wZ^3 zpzC&c8+E+8W}piWs3!qdRdxI<+^zNtGA=d5PXUMa?C6aMDL9{Ew*oL_VkjI5b8-{IG$7igIph?m{;fiG|uDIfp z<bO0`GahUR1Z`qb(wvN=v=GF_ls?} zHhK!9kiVyfVZZmp*(PVH_?8KK8vY)~1|P*~?*=zBeX0}>Py)zl9KIJU4~)ouyB(gx zScyL;x<%Xg+^PYIS-d#21o6TdM%X!B;mO+GM2el|yQw)4;m_sq9 z>BZkJ3&!CFBwl+TffF$m2p4&~GGe;Ztq2LkiT?h%j12Y7_!EM^4eL|WPmfKPKbvQB zS!W_mDU_%FOsdq)B^Ss8;S#4aO8GG<^c7^sH64_^P$$yUB}!gj8qJfx1smCg5rFPp zG8dBz3#Tf!S-mE>iuShpmAj#Sh5VL#A_`f!^c8~{KcfsNCK*W~paX83)s4yc)X%@* zmbfZ}{5_lCwiCYfw0VZtbk@b?Jjt&OM%tRIGq7p6BF)vA#?x{MbTDjA;^}&J5qF^e zR~AghUdt9&7oFU`crh0!(-3lc8@VV-=T2ae*$sbnNP7aXP#5*H<8V*skvy%KXXh(F zuMZ>iFH#3=#z1(ZN)si!gKYj`ev}pMB4q|5XgG#fh<7hE4jkFjd`uE!mje>qzPFXC z7FAK|ZyvjM+br6+$2iHks@w6w!m>G`ULj4CDb#5RM4u9A)o{I?c^?D=h4w1H%P~9& zp-84h=zX>6`AMCSYWFFx-p`li=WwN};A0^llY!yn|9gJOMB)8FGKTc9BNu8|_<*hVJX342NA;MI8Pj(scz@I{lttY> zG{SUphF=BWCHmLwk2u)A%N6lQ8%Wka8a-R3feDTmfP)Ii$$x{H|Q?>C#SSFk9@Fk;5%c5q*f zGsAenSFbnU`btm(sf{Hd=Jjf`RmOpMzJA8yK$&EUbpyX$;_atEclc6$gpu>KmQXY@ z`n+L;s9>kVf>O~-yg(-ksqqd4yYIn;;%xtD=Mr|%7r^-*d48!zqwAh*UFOc>4w$4) zVxK63wAG=A_C#B5>{_{DF~{uya?s~Mp64ZRZoYSkC%xwAHbua5piUUaNl0X>abTMi zeX#hkR2LrJ8r?!MbB`zHxazh&vlF^%{N(8J3_LdD3YjPL@5f;2xv_Jw9V*Jr_nv>g zs*b6$QR~;132^e%i0!(V#}uS=;)&9z+*G&KlWb=E6sAoT!A(_r;)1+W+Gmjw87?;9 zA{Z-Y>7ns{)u!_>&)mzcsy;hW#;Kq6+5gJU^mpjZlKU#aSL>g-#)ad8^tCoNl~W)& zDQFeu5~FO80mcqD&3-4S)msQ4nNAJ@gHQdnRQFNFx!dajx6{y6Z#9=#@bbQEWm`yb zFrqJ;ukF&nFZF$jt8-T!XJ!hh50I^uWx=7_7*kKy*MKL;$kp>vwik+Q<*?w~wX;s0 z7mDqY&vsl*gT$7t9_ifI*T!b>Vg%{}n;hd!6GBcA^Y(MiuQwp%k42_AqxTU&FPcv^ zae7cmJ_l#`qGF=|{#1Jq>GPZK?$sVYpTk1Y4iNT-=O`c(>E@d6T$_S-8tSEO}sg7KBKQE-Fx*K$sY;NUt2&cPfm-};mi5anfxDz2Y$ zca*Bg(j+30jp-FYVG~Wu1k38wb&D%NV+3vU+O(CeF;3fB0YnUJUAH(c1p0#w|1!H;ZJb+9T|RWeXTACNVBqq z3d`yU=pZSh<0iZOelt8CgBJ@4Vaf^aiJqs6ZGtVShG86Ji>ftgp8Q_lt4E99#Xo)h zvF;-#gwf1w;@g#+{Y>dI_5n+yher!VQa(B%xT|1@FlkTcoU;a*n-=DOUVC9+vL~o9 z%>7e)eyTZ-aZ!LPH=DcOa%kh{F#ptV_ZR3LLc~NLObsP_;t=O)774@dhMW!`lp+sk zH_-8a{tJ$LT9bk*pedMIRyTN`5_*48{uU5-+K?C{kWuRVW&O3`pwlB;!xbep|M>FO zkLT-=T%Ww6N?D%L_{43QC{}$&xV-1fkj-SRddnzWM0A*xYa!tiySa=lMGd7h;zv8A zJzsa%2?m*?bu*}}Xm~GFf&R#Zbn*mA25S$-#wTmk=`?&vv`k5)Zg@A#xW+mrcoOWP58k}1#8yxN(QA0Rryl~g%;o1Vca`@$Rf;Mt!M(#I=q;k}CVEZW zJ{Mt4xZ*Uj4AzruXobLz^9iusCcnO{HW4%9TpF=%S~;}M(0xR8FBs`xH=D|9A&{LD z8F4EJvHQ@8-vwf{BYydN8khTup6EXf`74u;ybP_>|xVsSNqFv5d>K$sY$7${*AWwjJ5!zFehQS_s`&6=^Jnh zVJg3cmI7Q(X?x1?dL0)m@$lUoOx1qnK`YgjO>tKw_0szXR!yslAM$NL z$^l;CTO5Jpsh@&SlgP3RUHX+l|<4NI#v&SaM>R+hjbTi`HL5xSh8HxQD}XM)B^Hz?p5(-@Q1IS(6?b8iCH3gB+Hf z`lNB?I@rv56?EYzJkdWuN=inf-B(I%(rrJ*-Sf78ZvDOQg>>H1Zex;Y>b-!{i3FAw z9P4fgBKlPg;K)HsuKQ=Klrct6@&0KLBBP=PT8vI1oyE2%*p;xw@FSkP(9Ja>fyX=l zj*Q&*pw=~06{$VgycPXpVMC&kfNH(hR@le~@)0kZ9M^k7{zw4<5kpg`_c;^ZX~`|D zjDh=Do--Q;2ijTZo&T-Jk7!jTdQm`D4opt20&!ub)~3UA)GcXzCkh&%X5bUulL@rz zE}=8CgMyBS@;2tQnGyHJ!BopoyH4j`g3pA)NH=w|HR$<*E2oJ4y%P_(q5G6(1u3KG zs)_}Xy`~7{6gyHkzMz%?^L-zJku$>36ZI_Zzv~1V&-E)2a{1mK6YHgHT;c==y`y(h zBB;fR&^;e%BQ-&YPNgtGmW-5z@$K!ZKdnBRhc5NOyYMP^_ zylvA=e?mjVj8Y;$aM}X9VlqtGn#c0F6jR9U%Ux{f>Q@o_;q0hC-4C+?w&-LKapGDwK6W#breOI5Q zA*vEwvvAXyI@R+_GA7QubKUQ0avb-=9Sw;(R>pojUCy~C&S_VM8s}8RUsBywu^L{8 zP9GDmQ2lmo38{VRSy6lXFRfijF$@d#w7y^WRdc3@1ieL(vX!jZfbavcT8R(NPZLCp zpW~B&=SI#LsoL~u=9?=etk0z1@%1A1Em0%MQM~c4m@(0`i=`UNZ&O zva2Lg?w()DMoZ_qjP27HiJohmbDNHl8>wM*g)da3PWiOK8pw8?;nwWjK_lBJo*YEE zYwAqdehYYyZjSt0?uPzdCx@wtl+e-QrPqv$K?ykfhWf>(6O!*#0== zH!lxu6m4aRMRX@RO8uINu0=Ofpc4P+rP^=La(OB(a*S`Go&7CzDs`CS>W{};Cip@# z>*;B~jiJA1EhSQtr2p?DF2AKa$WQ8AAw;-9sTp_C-9W$k`_WxUAWUIdD$r>byY5$RQmaGIvD8!Y95hJLzK^U>hMjehz6`1nxIH?~#Z$&s?D-G^sz*>3 zGm@4BXEK}IuoPMLtV;;M$3w=tz3ulT7J?_VJGrBMV`{f~oVFoJvA2nWd*NeUq$sJq zYKx$2d?2yw>y9LmeyA=8HPon8Pw|;?cc0y)vwMfnXBRMAx_Yjy*9L{pAd--oDL30< zTE;D;)O*~~!WaqSgjk%M=hI8SKYdI0BAf7K5M?<_bHsf$+qc*J(OP%8M`^lAKY4u4 z;Vx>0@ShC!YyZ8Trn^jXV4Pw6p~4Jcp4f%BS95!G)RJ zBLr|dMUuT-I5|AkXd`~@oGMgI?7*Amv9#>5anGNoXW+s`x0969!~$z2`!nn<{^DYa zJo}I3ktcQ~RD(f1cR{D| z6|V;XzW$?c2oAZ6AbtUSqD(S~h(9XLr%0#am<6fylN5}uHv=Xnv2~FIiuQ)%pSx>= z+PWT^>5czLw;{7O;_d*neHHwNJMW|JfpNQ;I}%mmzkQq)W-YmWlRq@0lrLvuk1 zX|X8*G4;nP(?ESM=~NQ)8-k(reA+9bWDfj#T=YYtWT}h@DXKRQ{-AVGKyyN7^&E5> zC9lC38cedmW%mT~`qH)|y*QdPo|6Rj!>69*oM-4?yp9e8kYTaPWeW6L>X=9vdB`oB ziuiu-X;5ng?(jZiRc<6u(n2-w*?~DwMuL^aMnZ2VF%F_LG-Y`j(3X3nd*^0+8X2Y3 zS5f>9#67wKeX8j}tWC$X9lZbMZ7lTJi4@>ea@pI2vaT#DFpo*?Ww+*M%zwPNPM0dS z-_Y=kIG_KxM?BCGBtHhV26hE2e{jx`;+#X1dPj0qLL3{+%D!#++L zA4X!ht+*Icp?y;PU$6UXwenaV5D`jr-#a`h0Ag!9|Gc{yb^>Gw`7wrMv}+Xk^bJ<( zF`GwI8C66q6xIjHW6!Olrqjrm2cjc63bxNH%{LxQtJ4qUbsuef< z?XihexO1dybAAUhl%b#m-h8@go40U~o zQfj`H&cZE*%Z{UQs_$c>zoDVr;zFg{S*rh?_ve~^WlHE|?5fTb6=W~C0=oMwCQ4M> z2UH3*KBzr{^0s4ike#O#6k6YY{!$wV4>rFMWn3o)RA!C$Z5#V^8f;vV!Z8qvD=bUmw&eoY0R|5cSbqrkxri zTkii94RX16zF!aMyCX>u0eT%?SI5EJKr&sd_^r#QmM45WZKqK@M%t2AMx0+I_9?3^ z82?>a{DNc-PZ2buAMs#T$0zw;g(j2~H;RLt_FJu_kr0sB$ zfEf5C=cE!u4PvC5_v?x|Ntw*|4{g0G0zMT?;0#KQ@aq4u8M>&Sr=HP`FzvlMffBQ> z&10zxFj^Tdl-6@51oZj*wF``*%MOLi9v-(HdW;RGz;DVez4tT)SDGruty|r6$Q-!B zhw)vnHg)(ZB1zFj4)L0`t0^VZOSL9aHd2^9PW}wcLr!RjZ!}rTWV5lT*Tdhd8jc_`CP7 z1JKNZC~b&{+ek@Oqeh8(Qm0WVTF>Vbkxn_<3ICxG9}@4UDwY{Szqgkd@QL9lDniGr z>yk_&^@Woxy(q1pParl$265A}lbYK{&Tg)mF@7jyx9vsb8Wd_xiHv?()d5solhnNG zNKmgaq_AZ7Br@t&(5hE^9r3(<(PE+WoM=7eF+&S;3WLhJR0!O^4wt5uM-srv@4xy5 zCx7^#q9~msk*y-79`VS2S>^dlxSgwZ;N|Ns1p!0ud3tMnF~c%~Oxyc#^JvYk0m*TW z^FzxrLIxzgX`g7%GIhnZaW6Y2BNT6O5!d73udLJ9Xn_ zuR05zg%e58um+c0#1vUG*KA(PBA4SS2Ea{y#!2ai`IS9wp6vN)Gr=3yFl(^3& z_I(&vyB@ixqzdz`N~cAO4le5S@9cm$stZL;d_bZKUrAU-s2M zoMgpYY}q)&A=$c?)v<~)GxpvJeJq>Z?&e%KZOzrtMfIXD-K@+5I{o^ zI>6!jUy;zE$ish7d0pc=r%hc!UtWjiuhbBf{0YQdAT5OfSv+FX{0!gizmd0c&V4+K z;K_HbP=D`l;h$QnX@B;4LC0Kz(f<8gwtx980y1raA}^C~1Z zW2!newiGEwiO!d?O*Tk|W?L%hgzDw1XaK0x8`gIFGL((DY?0b!O#a4 znokkf?agC>KDr@mH>$u_fY&oka7{rHXj%858lFT`Z%$}f;4ClwbJOc}lYS(8g|2DS0& zTSDBfLHJZIqF}LpF3(Ucc{u8SzxrjSqjz%dY~=!JGaP}G2%5fqd+(GxsVPLoU_d#e z{S`{(bQRsXdcW`FDOnzwB~@z?H0{kt=D?G}L-{h8=M#wVIkz{6V4oco!6-QZRiH$H z461Ts=EJjSV3Dm2E7*U5ak^OEh`Rb4Rws$y zvynD^)YZ@j>zi<@;Wf>AcfY1~_R#1Yyi}^o|4;8CvgpqcYS`7@A zl7p-aQ4t?#tG_l$QM5bBPaKJQeNckJ49lP-q&IxhfdYn|0HKw0fC{R(;b^d&<8zd8 zq^p{?AB`Bge_>K#qTYVFEFdA{D;2Z?Zei>Cr8L_0HYk{0)c@Pu$I>cwr`0C;SjXfY! z8#c+>h_8940UAbmP$MDRoT|^hTBRxNyZp8RtddqZ$HNeTyrB?w;&Y9oxBlyX)A| zIK0cjynh@bV09v#p}pzce3}*eL%k$No)ZyYYZzz6-O0JqnpJ-B_mbGK;ozYqnHa@&R)xlnBtCZFt)@x|)Zv0#pFajX1`g$MId|ENN9PS3g z>b^i+Pp#eUP)i1KIN|DZ0ImlIK*uQkdXUEM#=2d^Wg=~oE-&8(lZ6v1!wgh;LzV3L z1gSW9Q@DN8hQPQ?HAvYx9mdJCk-v@x({rycNL({D{v7C_E`}v)l@@v-5e}E0p2f%^ z(GH_zHatfm)-G5eeq>#S;++dgVSM24!=X_6QZ7fau}9C z47R>)wFI5E1e4*2k5m%n$RyWN1EVQYIcCO>Wy(%?{)3dF3cPbkAnQJoLUU26X}3S^ z|2F6(*D$*#``@n*?nK|>emlNB{l~oHR6FT&JZvj_T%-*}cER+tX`Wyqf%)HWuG*Y% zo91e>CqJ>DPi{%DAO`zS#-Qhpi`t{3ArL#GO~t#lznN#?p-D`$$(I8=JdO zG&OS8Wus4(EKJvVU;dJgY-^yR*Sp~oJ3T@MamLauqbHBgET1d$Aa7pYf)0ikn$bw- z(A(|z)Otc{V{+HW9PjdME~V;8rteEnA2OI|0lfBhKb#Jna;J$Xh7Zc`)Tsm&LA9N* ztc6Pfm)i1}iL`;}UjQhuVwB?}JX5YE*oWq~TObLw;eCjx10W~YwQmPWa7ATu$lB@j z>6WBc+dC1nS`h<@B8_rc8%C~gPkC7=u_Vann^qoPN=7o6IW|KZ9F_6M`w_Tv`*g84 z^+NQPxx9})=EM6Cc{ySwqJ=WNKi5y?9X8PrS1hG005TDd9on9wRMIbYG6?w$-j0H9 z*MRvk(fxd>QJ10HXFcR_&Hcf|p7iI#txbbmj?Ha|_t-mnsoemyKi7!DoPQET zdcBxM40y+0sL>~Qsk?;)c=lme{383$6}}5sFTV}9JTX_^MOawZ-wMJ}OhDOQ`=i%q zfoa`(RKu|rk{Wp1wDoiISTe&y@vFZkn4|E`G7j5kg{7}Lc#1xLtH*PgWWN-7P=Tl@ zSy~DkFXaa$g?iZ;nO)>((=fE3)#Xl7%C^0K9P+xxkx1c{mTNG4$U@pfLDraoT3)ea z{AJ6Pu=?XY>Bk(Cm2-S){*(a%YpZF2pxx>ZQST|ogXJUaNj+9MHO7I=^4n=^TxMgX zdr7*E`Mr;w-&SX)79N4-+1C!=%M^o{p9AvLYsx^#HcWKL218u4i9Ps~= zyW=mZi}iDK8Ba7%ezeQR>;<(wP74Bc7bIF;xx!#V(IM{VKwEHa=psCI+8b?HP78ZA zg^KmCwy0fzzFNTGX>9F!*IRFB3)5aSp>= z!DCP7z7`Y<%N4r7@Eq0gXH!aGGb|%KTKA;*`a@eK-8a={0#5amYuq>E$4pG4b z##0lQnI2?Wj6)T`0cnTS8#;w@E8%_a$Fds~Xo!)315#O6c0*h)**zs9HZ9{qE%t!@ zPg3Lcu~z_fUNiP^rUvzCnJ8?2P)aI(hv#b)Dh)nSntI1kEs`!E^b zJ5<%d35cbl2}Oyi=Q%2j$4M1DynX54t2on7kl1}3yz~{6j?@|t%RN{Ij+ybE2y-KC zVWog=8C9HUXZPcecK4|>LRX+Pb)BXf8Yv=tTUCLzO}OG*rU{MfbB)v|&+L4`AbLNe zo4BRyHuaSKYl%heg+-C(QspZX-0^g?`S6dY!9MVPWzhE$V>eSyH&FFIQ{r%_PEAWL zGh`75kkK%4&lLPRcD;y7w(;a`lFx&xxvC2~9Grw)g8g$5QxMr$?Xfg+rB>}!Uxx`J z>sh9y4p+BHG%+8(R{^r>Ir$U!Ma?ov5KQer-s7esiApS7H)6L-uNH&=Dc$$Vg!c5) zZdQ)ucGM=fSJ6(!M|FvlfapVaq6L$#auX!-_j(^nc644(0$Fr%!Ri#`4JVy2rrv}I zEZj7kTw17~AGWqsS)i5STF_(&7;Rj7so#^^o?a-EVoo_HD-jiLuXTYm^r7>s9HU7| zM>DyR7>N8smsS9k7TawJP9+%5E|kBFas293Qkd#cT#ME`0S*y5Lk0SpEHf3sz7O10~qqs&w zH#rHHcCWt(Q_d-*q%YkXNh>(TlQPL6G4+1bje}e(V{<*Ud07$enApyq({*qVOneG* zKw2P;Z3kBPE3j(JO{wJG0aD>Bz{v!D^^Q@$B3-bX1OC$2Oe9B%)lB`Uhv(2)a0I7Z zdr!7op43K|1W&_BAl9>pJ_fn?t2Q_)Ak(ENGt?E0G&m{Lp^zj;RpCvVK0sgO+0e*( zr^1xfSmt^g@^aDXOS@2c@F7iMT-iGffM8|A^YujDlWPa!G`C=-21$W9+!>fMy#JAF z1{jf+wY?d20Msr|It9q`M{P!J7=^Y|vhJ$iUxnqqh+-0g>iLI}QVMbXf4})r;Udyd zI;)@r;zjidBnjh;bC6UP4$t=(1=il@dk56ifS?*N_?V@=b3r(ORevvkG`x@YoP^9L zOV>MB5=RCBXuBE0V>u;d?Dip$WtdMQiCTwn*l^eS{b{&N0#TkbtS{K&fVUI(v8UN} zCA>)y$Wtqb(jJj_nRJ@&hg)8F3>&wtJ`ZZM2pnoBVBlc_4zHstI%$cWo6SvQK?)QJ zRtYDP*Z)+@E8UQT^ADB&AEEHJn1u=(8#FonADh$%GU!~<3DWpDWEqF< zn2C4GT;7lmw1(s%@BEOREZut_P@3C!f%89MZ+5O$;kC4d+bPEGi5S8y<2tE+sM$YKv`LCv~`rz=4<|7-GPLLnhsSnPT zoym1hJvlzMw+~1Vgv{{oELCy*^BHwVk>ymG_hA~gRjW#c^VO!K{$aCypu7^nIX1H0 zEFVz(#)hAwo0pH%zP+b&XyixYzr0pI03V17?Kck6-Q(NvFKAsWT$(sig#-B)d>fMN zsZZ+iQ6E6-=R(OzOt@c{)}`0woV}R%4;$@YFu0;~ch&vl_`1@AY7&u&TE@md&=>BA zdp0R)eB9^x;56iYYlxNCUqQoNhh1iL8h&UtbhH`h`>;oUzLcwA3q-ryh4|vL4-+Xyl z{_QvSa0_55yOW7yOIo`(hROfYf+Gp4=hBS)lWN6mi}-c0VV;EI?!bpFjWn zYk%jj-?qU8`{e5;M^bNt{s0V5rDxhO!osP9kDS67|#bw@+G>h zMyRk{Kp$wnyPFmkV?o_E5G=t*etheiZU2Idm8uet!d4j`#coF4){MLt-t1pUKketp%L-P7tq=CQ^W!7x^1*7-!VFSy(>6G)+Pxfy2&1+gRF5cZmsv|6mOnpo z!rLLUNzoCTPt$;2LCt~D&Eb7XAZ%)B(c+>85m)`b(vsVIVgyKOq%x(OhJSH*6n$FP zZI`b22doWoJJu0&*xO1if%n={xVnCWsfZEIVw;oTg z7LJuo9}nYWqrzc?A^>+{jW4AcyX}L;5u@o2c)Kmk+6Nbh2k;&rY%c$*9URc~FhuIf z)DK_2l$J>J68Z63NvvPZ4&>aQ^E3MQ?JMrLBL2nKFE6zz()-1>09}M7QJb4ooJJ`& z#Z(1T%d}79V}C(&%du+geH%5`Ehk~_IJAb44=$*iC77c^Skdct%!az}r~+{b`mI#j zNu=;tGgtis=Uysh&M{}hv?D*L=F}VD?|ww9IqOsH5*(>idF;q8JQeF^JFpX~ z5gl=55XXy`%lPtjBkzY-O9+4}$V;pLZ~GQ)Mua@?=$_U6*#`^@rhdr17k~b7{XEc3 zeVphcSA0}S%6jjI_$R#v%A{HULDlsyQrQMHdmd6#8OOoa;v>@Z!-R@^So?|T&`DeW z;zD?6qLZ`g<)?(Imr&#yrMb!%MiY=N)|w#u`>j`ixYK+hK?DZw4Wkw48D}lXC_#W) zfn(ChN*;E8*!g`8gtd&)pG+Np=>xLf_JQkxEl99gFrN=Bh*IC52v(mVvh4DWl6Cgp z@Grz5$RapMc<&YHZgWy{YwiCuP#=-25013dD8xyu)-k#Q|ME-*(rjlX!z})7@i;uTQ9!Y1-GUTFH`#>{g&KQjKzIi}CKn0hB*WXg1Pw$g+ zHNVSXQAxg)1GTTP9Osbbe7(LYfv0U5a_SWJNeY77dsB}in;AXskdXUuN;i^9L|;hh zXHS)YFfw|K*FgL69e5L(-`a9_KmOHcisY*vZa*_9mHhKB(wRHXW_s9^hse$ zpqps&l4x#ZgltR1Ah?14-Z|)3AF0B8pb0P>CSN{y3mmT9NUkKtsfIfKh2&of%cmf& zZ$L8h^gI(A$S(FK!cA6_B`W%H`CQPrN5N&aN}e|AaHgk@k#Zwb*w@A%vUW<@h5tIV z+u0^e$3IMqkYtI<_#d!~=jqkKG7g4W)^@%xJ(yqKT~s{kT)2!12(D~<26VUcd+QPJQPY=2Y3A&(G`a_gajJAd01H`LxTd%g_f4uwwki2%~P z`2aJ4hb4l0eSWAZ@vD6ahDp4fGQCKT^q4^(S=c`P2NKI*KWcyXH$&8ZaI6ZPgkq#J zHl>QN?E^xbUF*bwOLDHS7~S}_6f=~LAD=rg=tH2@*fTVXmo=wm)|8=?vYz=<Kn*MMq?) zDWV)~i3vQI`x$G<%W!ZOvUG<|ttjcS*fra3Q_25{LwWb3sP{gwb=7lCuUn;tP{*HtOQXR3y)pg^-EV3~VGj+s>;X=EuKL?I zP~!)g!WU5v(5Klsl=`iWJ=Z`DS>WeY*jN2r$%`uXpRz+e#iSr*9#UuZ>S49H7zW)U z*>N|8O!&vHBYkboQegat_buN#rP)X!vj6{X3Q@v6+lYnOaPYWL+iz+%y%hLRvE2mw z3?C@}y1=ZklDAdhw5@qMrm=Tzdya zu0j-8Kl0#2sT5r*+hx5B+D zbHj+F8;#P3nKq8=ZJMjHbh6Nq1rKEuH?)7CXDuSGHcjI2FQNjR#fk~+xgvP3_#|KP zRP3qk5TkdgBuu%@VLwQYJHC^LH`rxb`%6J?VsbEC-Rtv1uo}sAZ+kTadH`wp3Dl|y z-RUJilreT1Nnma+|M~Y?4qc*;qfq7WOv()jQu1G_%s&()w$Z@VGuh1qTc3*t;sckE zGE?vJqcsn==Ym?5OM-gI^hO=$Nc~ziGRKOt+PKnDlc~0urnFE6ooS-ByJRY-_3TB^ z853!O=Nbdvdq(OftjuZZhCOqn{S7%#W=yuKZV%a9vA#@XT)ThtPS%Y>)$NYxVlW}H z$gGAoI4 z=ee9#7@E^}bOH}s=RnPuP_J5FzEXrZ`mml6;idp2hoh>#e}|3e-!Q6vdAlW8lL|rH zP9nR_UENNK!c;%N6tlHDR}h^alDI5kZrb6?k<7_!OuOVu?-Kd0QzC?lYX&{*Z5PH7 zwoB-QLpe@9&;)}ebZfk{qn`>eRJtq_;(K3oC~*LTbPf3YToMi*b;2VOMor;y`N#g; z657;3eum3|xT&0kx$;)SZeQqi>k^PAxxTLI9^bJPXT%Z?9U!*n1PaA6agSa7z2yA2 zv>^JqVNgdL zUmmj0$@%Gt(&kX83ET~@$50a^Wh6!nPqHyJ7GTQggZx+5C_fmz3%Aoh9LfxQp!y?f zuG6XL%R)9x@MfiRB!>?U_bD_%k6+wvZCdD}5CcsjFUim$teTURPzB=pP8-19n;MMp zPwcd@++&-=Ykcr2^BPL)l-x+O@}+)yakoA5ea!lA4;3`-Wo`e!}O|!NsFG zFCi(P{@`v#AFRt`qvT2`FD}q8!8Aga&I3XB6d!(U`m_sB&y=78P*GFpgFsoie_APQ z8(>5@1#>#@+N^^hNn|)wET|9YEDhRSoDM9m{O9ZnmRXM4Z- z>#~iPzGjD0=R=n0u9p?R`~d$hp%bEA*&-htk=>k#4MX0;2P;Gz%JXu+!|D-5I*P2& zgc|i*DUDmE#hxqf%Uz|wh`qRW?J-OlXC`yyTu-Ph-)i+xyfrP}XLpJ;jAPm-}RM+5d>;FXKH)V=}T6^Ql*q*7l2mOymfdd9hK5;aH)%8Bq8+WS2 zm{zvzJ7xUi6;T3k+57)T*S&4mbtFrI?T^V15GfsE^C<~{xL-$i^-I6xAOY}F0!R=b zDW<-@r^VV3EI?L`lc(}1w6NETi-)_px%vN;K;jE*6${1JvrbbmBeg*DkMo;&qQq1@ zq0Tc6R@AJw&gTo|2^4{sm3`k9cXu}uRw|^%vFW$k-G>u0RZ15=UY14L6w&-;|#QG*b&SSCLdVo3{H9O(l&E5N^xb14Crz4a8LcH|Cn6Uz3-veBui`G9a zO^81Thf9dzcEd2Iy{IU#;i|2t|UjjsmhfUtQ#5|MkuFB;4|X=cG7Ltzs~lhI46>MEYc0D)T@0r!X~!>(+6% zehHdBqZD0V|9$s<`fXCGDD&fqY3pK*`3W**@8?v6JPU>Kr2Mi{eXCg4y-n0vzFSuy zyl~mb16z>XXw|mY096RQju9(gwj}}3r9^fl7WxX*y#gkl^{{=~w9-b!IK;^&+Ez^y zUMR9t*2(4u25C=!_Z+udYm3a`?0Klvbjb(#4%AoYLoFFlQA8|G@0|6n!h#(QyrHvn>{0G8xaAXT ziNl4$C(kodMm1Md9rYo>WTnQ==0AR*SR8Jnf@DeC6xnib3k@<2kjJf3W=UN#MUiwR ze>d|H_EK#o{k?EXDrrO70}c~PcKqC0TT-Md&Rm;*R0twS!axtgg z75F(}V$u`*C%6B1X1Z@?-G`9z;-#6yzKC>)Ksn~04iBUDv^H zK{IjDKYxARORJ5v;v>HiNw8^P7fcSm9^Pgzpr2O#6&Beg3CMa~2LwA}K=B`{S@nxO zH`k_=j%)tv`N#eZjee+-vb$-Z(;uiw6wY0!^Pj&yo1V}!5H32X(HnvJx3FI1XT(hCyNQ>y$GQ7#Q9@Rsa~ zY}G!cTt!-5gVyr#rWZyDCknUw-UfS9wqs8PSq%1giJpFCqKlM^BBLhp>B);81Lbfd z-CtJs$QS9cc$$Xx$?AymA>c zj`uwAXFWi~AXF`s=#nJzQW(UV{3Lq*)@e@(4arJSl5U$5VF|`A2Mz+zCF`>9Vgm<5 z`6dH>}&$B02s}xFiQLN>e^|97Z7oR>EBS>ZWqyjGl z1FWZe2t-xIzL0fu@4%uGYTWjh6M%Ps2g)(Uos{O!_EQ-a394pe5Qrug5dPHE|M!J% z3AMc9Zwec(Q~p_4GHY9fGp0sBW}IY(2{t`@o_h07ya|}ix!%M&Qj?jv^14Q@r%-*x2A*PJ(e*KhiERc+TVf^QFszJ+)e1| zzS=KmleGxW+;&6)mIY+1h8SMI))rEimcGCxE)`YsSXy(vf{!!fnhdWn^>J9r$^Z!xm(4t{t(e z{IBQ-znK)#U+9XAcL23}cN>=IMoDI&*)x~XjGuoYMV-w8j&DFEMRt-pw=4`wrlG|@ft?DdN zq8CZf)G^!F@m}UzSbcr}vC(=NxyWM6~H2-F}B%$(U$EWK}+tx1-y+8ZKVK zh2DWp$S`mYo{w?(_^H`$8cDmqh4v!{T=y|*j`N1%l)c^MYO-+JZNpR8vMIqKNpnEN zb>~&Y^8V9r6?%DkLMcd|E>Bzm;;VG@G<=(qgWf1a3ToFPly=SxV8aTEbK0jpkL}_r z)D-RVUIVe(EBkI1f>?s$nQDWJp?2dS`w=YFW7)`VeQ&1cc^;63;s|>#&B>b9#Kg7~H z6X2ioP6#gikgu)!dJhQj521n5BdyD2;0XMy(t7yn730dt>JBz4(f{|9w`2cwts+g3 zebSk}eUU}@nqxc61L~UP6_SFP915g5)h3F9hZ;aHZdC4f6L}}qRIcB?y061@I*S|7 zX%?jb#u9`*`2{@=c*Tn{ab35%n^Jp}WEr`({smbvyt2_RVz3Ry_L{jnbPx}D5lQ)7 zziBq0vQ3d4Cv(oKQ2NoI&CyaL0s^n|K!F=WXOwPSe{b7~g!DRCUSxeHYed6HEt`Xq zTff%}1xkWB;HFe=8#b%rz8*3AyAOS|08}SOjLOI`_Y^4mGUg6=LZnxgB76&_#zyVb zGu-${gzWB}6{BD5BgGSI9Zvss^?5fSS#|>CleoP6+!v{L8W7wFH+#iMm=Oh%*uVYH zO$n0vQ>g63Ooj{bzCKVonhOSVrJy;P0V(05Q>JTqq8uBM2)rP{quT1uavh}mjJ=w@ zecyZgU`vFG;ZMru-y0XbRgGY65RVCD-;)($Zzz?#$+-e1w13ztDp@l7{aQ#_nlv&H zNn4e5k}TUI?J2V#IgQ#sBJ)x2`0a^Pd;n2)?OWPpq3XmLKrso!G+yTO$1Qrm<(KXm zODjp+18RlBX-T8Lql*fP@!x*FB_|jhnxT=lZ&zy$zB*x@sNfZp@sK{BP9iu9G7t;yP&@V zoG5+%_zDkmO%9k34a8UBTIbN?;`lfVMaGPFV~hLWr!U9baTJ zng_Ju6zDmdIR$lnqef7mLx{mc``A1SrQ~E?cpD=<)f-fG96r80iEY)EQZ5GgmX;ZQM2nePp1ZXJ(dv|+xb<=BpaHP$#Fgp8cGFQ|d!64S$ zDQM3@`H)+M9TW8b-5#a^geJD~U%w!59Jsu|YN{eH-nNY0iv#YT&8X7j;`&Wv&ZJ-I zCW>b7o?L7O#5VBm_`Xxjbs*I(&Xw+#DZ2Z;&KuX?(Oux{woG)uod%k;e6#8m@j|?; zd`O061e<*hk=)1w^GiQpUUfwdbm&kC`ohZm(vhIFRyr*YvgqWrW#B~kJtEiU%Ucko z&M?3cBK9&$D`(rkx_LTT`oXJBv4?)JTIGBSHFXG&9A-Gu{ijak8MI7{rI~JM+D*r2 zILyr4kI(Pg3h1qHv`K*PUGB)9MI>YComUKB*4aA!`2N=)6}QRk9+0OP{=`ImNVhPY$54sxE*dCSccZWXSMTOY^(Zk5 z`fh=muD^clDh$k4oh_v-s2a~EmW*LEi6Wad-L`7Q)fa|7YXRE@h>Xb@c!+0z)rmW_ z9My_UR%}_d@_b=H%0fccPfW&-dmEg1aJ=W2g+@5;*7e=}yK>1?x21JBHdc_83QO4x zjS#6{!FST&Olf}z{T32hno;YSnP0Y+ntCS4C!eskdO0qlok5}K&4;ty0 z!lnBmT@n!d+1JmyK;l9C!>%(Ncyj3rFN=T$y&@A^C6D&gI+BU4D$W=yC}WlqKyn+Pxu>1lwR zi;H<2qIp19y*+3RLIj3NZ3!l1G>gA`Ia4V3hgx7tA0&J$_39TgGbro>N0%jNE9vSL z6fvK-pKlvO(n4wvhu+HP4E2-%G*UT?YBp7W>PL;*$bhBHvN{RAFtE+J;o01(nyz~h zO0=bKHw&FaaIdVOm2%P`R=jKZtwYzo&K5EDlF-u=a&EgJY$q33QH-*vV+Akd7E)f` zdqGJQwg((8)lYQ?snXZp99=-s?H^rqOIALeU#x7n_`QHO14;W)ggk*RSi)PHn}|sg zLiHvIJQua>0X3tt#c>5BMykTMPdY0*mp z)8Fd1&~d;+OA9if!(?8S2BI)*J=m+&6MLn1_92v&oW#@z{RMb8Eq@brO@gfkw2D57 zPZ0g=o{A{p02-1`|Jvzvk+HUoVM;Kv4P9ZI!6c%AaCP_brvH?pBD`7q=hMx{X*Xy` zh>q`Wzl(!WQ$T)H9bRZN-@pFdzK!aA9BE=N_qSK=i`g>d@nq%`*G?#4{P^i(Avk(aAqjAqA-r#{+h*ugy%TQUC_QO! zKuZOxi1EHB+2t2noY3^)Kk$P-bg_y7faPJpph-B|6O2;&xA+Z5qZaBM^Dtmg=#cGA zlTLxsqsI*k&`T?&iopqwF;~xeuH>cYMM;iG8%!pSWP?p-+L2(UgMaSRheisorj>DM zV)H^%J$xrG*0xW&Rqa{S!6F_0_#Nz(Hk#&&gY>Qcln_v(7?&{C)u*fJiQ`a-#82|J zoiO9dQ7>Q-MyrYXaYdK1PYSK0toj860h&%_M!hAPyf=Pq>`DwetXmCD7k>>TpbLLtM@UBtsn}fk+jNvf2>ZGoR`z# zakY=eKc&{h5Bm1SBL!C-y-u?vNMu~G={IoLtN_W5%lB8kW8nHwcROaddu3veFrCEQ z0R!hEgd}w+*bI{XgnSTR6O={K~?N;9tb5A8W>`2(@C zD{cF$&PF4NKvd6AglBG@Pmo;}uZ;kp7ZXFDWHxWWjC5F{*o-`%m6P?HqU0k*YdY9b zlU-JL$+Ol1(}=?W_furpFX~2&#v%e5h$8voGHtTUirYB__cu7J(}09 D?vZQ1T4 z@@CBUfa{3M^pBIBgw905)SUGI8As*9OO#cHN-~@?v;~h09N7oM-a@^{dbvhcsbU13 zN`!?@OmaG%_tp;1yu?XE%xE}(au6ZyJdrjy=aYnl zfgPELbiDa7FUvTTD);hMt;0(ANr_9)i?1Ih4xu{#?dV}H2X6Xt4j)Bg~)%wT2GQuv}uJNTBOx?VqEm5mM9ytw$uH#q_k zt6Za|5|i7TIIt%M$~akFlmolKI%JW?ozjaNYASRbdh+4AFB=;8Qu<0$h6G9l-7X-p zb?O71-qyCDq$0n{LSTqb33mhP8bq;!9o1V7&ww=UVe~DhlJ?Nn5d>Ul_U>eb4v$sX zvEEkXL;EU6H0I7Z;bYa?%QQe`7j7N1-c{we9EY;0J}{m~8ylT501Jz<=X4N`WD%u{ zm$;zrM!>DMs^FT<212)d5;m)$wceqp}3*4G@2fqZRyPv6z|RS3+D^n6KP_S@S@0@rMkNfAqo zK&C%Xl*Ji8cF|o-KCBiTqQy|cpL`!2z|P z?!{Ghyt9=cNH?X)WjjCM6 z>Wg)}IOCN`F#yIyVUj_c6oys39Gt=K$A>px=6I905^2CuonD`T9HI|-80j%MWjI3~ zRkj#BTKcY^*xKKucRgBQPB13E6Fm&h3V#^?<#9RW$Y{XQPs<(G9u)ezBt7#ntaiaz zOp1z0dod8|lo2v=LXtO5(QwPKr6nRUnt=zu`_L~&35BZF>8l@4SaQL(1$4om zqAk(Cfu6DL!XBcg5YfA5&uWw~!glWe9PIY1ab6>C&BqAXQPxqx6Dby9hx*frOpWS+ z^Z?=mDNJGp>^gR_lw79(9YHw5Tbp*vwH2(fxR)Wkfp$v0;`S~kV z@qPpW`WSpa_(wgJdm1hZcE^5c`tGp~P8^eUY17O4Q#kgJ^&@$WSssv11h_B?VOhsA zj|SwQlKa>6sZB6R;#9zdV6I%f_dUl>?HJ0%_q)rceH|ab)_wapDJ_O&K$qaqZxW;R z*+M*3zF~S3p7dKC(1tZ#V{O|E9ZL_LXj?XyWc$**a_w@)3NCR`M(dOIF*3zAKaZR{J-7f^$?ePsPEyZ+_)$WN2cc=hhx-PKiH ze2l*v5!lYAe0$d)E;C|A5;AL^H9evFEuCzW8CYv9)JKxfNU@?<{x+Rb^R6{9{U zmYD_!y*PgT^h9o9Aj#$6hTox6J>&ZRXOQpsRPIiIk#js1R2>tj;bz7Ikj z*hT{xO-qNzb_)6*N9>~Q+o}9=D$n2D&CFE-_4@d54#|#xZC4LwxeFInXMLp$XF*0m zU?K(w^`BY5BvB;<>;fM-(I6BKf!!I`I85!{BN@}16kojigcVZ&?=iv0T?x`xcMeih z_>Q%>I#g=SR#2oU%YMRs5Ai_)oDHIJEk*4-kgp%U-MlTIB{(rU<~rR~Yn7(6=X6(w z3)yj_2F?_d!~c4cQgfvtkh4a)JX&KYO~NqPiQNTCsB?iTOx|0k!oQvrTG^ozBmzny z()&+!V6t`9+t6c#mRGaX7bmcl$X5zMFE3l=9-UIOj@oxaH>arvfG4fUlr)WGT3K$D z>Ocm&2eG|--Mt{8LbBm}>(!^LFWuqRz`>^KFQupXTeaV`wgS6g7?0A^x&%%raw&o| ziNVUscp6aH8-l>snW>_q8r#Cx4;a)GY63sn*(Xn)y3qcO^#44KjA8Ptbv~JowEq@> zlC*3^3h3{NS_&n~DL?8zMUs#@3$onP6;wERK&I}W*4I~UY-nyDaEyi$W|>^&UkcW_ z2H&1QD+)h|aEfzBp1$W%GjXyugZ*mdA5COT-T981%C~O7#zRhE6$hy=Ay+ghgkXp( zqYZEy+_pEob~1$3k`Yx#-_w;8vO2CMF6-|gmP$H=8+FGtl{2i%mIV<^C4u|4Zdrmk zj%TvY7eA*!3~GWmstd8c`vqWkc#`LmGk5dXquVRmIQ(b!1AgT{J$2Fyy7UM)gHKF< z6+p4g57Ad(s;5!V58NEb_}ye%4jp?z6gy0Zy3799+WtCTJ}V>5OR2Sa`Jk${WzaA0_6=-2G(yCxg`cSA^Ycs zF3TlHQEqI%uNCW( zZ~!cF90F)eHUylEPRShE`z_w4@-Ceue8;C*lRN`<^0=+1)>@>Bw&W8~!egTQw9qix zO362>7)7Rhm77viYaM3qRP|>r2(RiM8Pre5u6J33-r{`^Qmrc7Z61LGLG2t}#CO4u+v_lT!kU z`a$G^e>3%YL7kO8qkk|UiT)1qa6Wwi+$yeW!$qGe24J8Y-0=@H5(% z!pp#VW7S6J+P{G*rKwBD|JDRNsw92HOa#+NOF%xgD z8hScaW8yh>v2S<6Nk_JdO7)>v?LS^ z=w33|mX$|21u}!|WhWB`_jkBPU#n@hk+r#-2B^ZH3iD%9-}KgZ_Y5uxaCW+11MzPv z6&`MKlgiZKDbtX)eEa^}Pq`X}{hNoBgciu6&mN<`OQ3i0x}VqAp8}9TY&;kpj{6DK zO;q3@bx#7uQ~1NKnzZ4kuPR_f^`my-P>w3zK6__?gEUnMyx(kZg^@7I;8bs}e(%y$ z1Bkq&Zj|U@y4LHW(xNeka6R`6#Au65Ka^}DlYd?VF z32=cZ|DyPCSu>*E!~Mrh4QZ^h17~`$;nWe=4MbL}Ye1#XsG)ESYhUXqU_C(ZnvqP2 zMgt%g0pmp+;o5T;xtpTZKzg$*t$P#>xQ-;dVX0~ey0>7G1ase}x56h+Z0&BiYH0|G z0>nrtdTK%1dom!91n-O}y>^d&CNeZa3cd2Cil{S^*C=n`b!@)A7d12lt3-9_&BdSX zd>f#2g*gYNn&fRsg+aa@b$PpwH$5e(-%3lKA(hlCDC*{dTJk3itnd@G6qA6uP>cI# zF%-@~hHx9sUgRWe>z?7$&yRu1=7ZI{(go4vZtw@M>|8;8B{DLeVrE%U<=;?2NdptLoF1ut6 zM$9uQv(lbWqKnVB_5beqpMK(0*&b*{%>$>W252yddsBQw&Y{jGH579EZqiXE+jB)` z{Iwu%z&zFxk30Z6T@HX%d{U4m0sXqA;sY&l0Jt(j&t5`MSNm^n_);YYkFNQ zz8$#lDDA2nPf}yFXnJ*X|NgGi?9RV6fZ~*)LVVDea6;*9*0KObj)oo%oH@ zfIjE!hWa>WsW%+jB@aqujr7^AfJj}bkP~W-TB&jyG+;bI0O6p`ni!Uw`E~@yI`!;g zY-`u`>h|J#O6Tb618WRqlSEbb3g>#}dQX3eycyXD*P8nBo)9Tb0B&G_*_DwQ zaW(``jP3-s1D>#lIMRBaPmzLw6Mp6>=Dqn+xg^Cs=n{~pT-!Y#>MFNLL5*$LUWRSH zwReObJ0Q1y;(&U*)JzgwSDj!HLrdB+3sJLdjV~eys*aNH3{ShS0`UV1HKgFbZk2ME zaUQ7|WB&~W_dWyZ{)zaJ^(sC#JUO6NapH7xsT38&&ijaHxnCO)Y6bQwS*^`8xlAHctNYy!xl}FIJ0NLqp)>t`^-o${?tUqXISQb;st$V-TLmXr=PtJ4*0*`!H3({WIZ}il zCo6Z3%!Xt)mT@|Y;&SqX(q1p;jE4k&stJ(`6K&LwoI{(oi8Q^s{xGZa`U$ZH-2mjm zsm_HA-{vu%9XmjCy!Oz!{p&xXvjG@RB^%BzK8&%z?~RcHjZbM>jf~4(BV-2T7lhPH zi1t}Lv*Q<&$ve4QigEMR+`BiIi|g@ZlFW_4rf;gJ@x zieK6K2AF_Cy802=OaiIBE#zK!CeUO_q}^W3i8RCD`!%xAO%PxjkOc{@(F3{PjY2C8 z%!CUmo_ySym>G~8cf|dZA~2wWB4$vQB=vM+&qEeXCI8LWIZ?;B0CW?)UVON2UYP;B zZiv+=X(|VthNw0GyaF0e6EV{Ou_cvs&i)kcYMXna_K$y>9au2zxetfJ*Z|2X)PXq{ zI3I2CpoRsVrsN#AHP>d+#D$#_qep|nR>{gYmDhE~^U-oATei)fFa?i=UB7xFbFH)0 zF;M@Z75r2rVR_wy(s7Bd8i{rAL^7#;GmniM1udhFxi#$A{dDCh29enW*y*hMzB!YM zj|9DlN+IVra9}{rkFi<}}wE9B)7bskGq=fU|Qpdqi@IVPSG zxhy{TI6*!0N&!WRsq_DS)gAwke$KXufULK@)BPCP zj3(nIB0f@uv3T}v;17}tMj_*GOm&wE#qr9y{As5#ZOQQ907T=$z3jt{y~g|0NQ6(* z={H&<5bV^-eVAMU8}(c`#jCJc8<=9zm5L)j20gf+e!_7O42;eCwvtOKPe^nJu?jV` zZ;nGi3x3lmg6Qy%{sFN)A098D{lfD@#cGEU;{*~+-*=>)@m_BG(8StCp@1f-y#$QU zYT-eY#D*6I&5qO0p_;7Fga>fSdo2gMedhEsxO~49~EXCt4LS*%`v*} zO(L&_AqQ#s{xct0G^agJl5sa7}vR$?i?x`{tNx!g3An0TiG%#SJ#ui z<9Qmm+SzeV-hJph)>hQ#NQ{)K!`>+;I|by8qBPaKxm z>D!YmoyJGFSbV<0PHuk$DS`OyBIY%D7ik$BXYj|9+W`16F(dLJ$=as$p~y)aTXGNdkj?=NuCmg4FhVtOQ=srsH`Vv0(qe?x zDm?&rA?b$eM+1?O(GV9mkh?PfwN%2|!|$F{k$;Z_6|<79unslLHRcyvRdTNI3q4VZL307{PLf>UMJmF=}QeTWoj$9A<#UO z7~&|6u9&^=_5k7{w^vtBlrA?kKtL{{cKi1Fmmj4A@rlgmNOToF)pJK!H$;s--oCkq zbJtFm7KQ{bWX3Lm_e>OY{nnDke7vSMkR9ShtAg;kABvt~B;ljL=k3LBUza)GuHQ1N zh%U#k{)EP~q4k`JNOSh38sZVmG(zS;AianKmiM%=rR2r+w?9NFuZwk&5%eE(j>$a{ z%8a;|s7eRhCRNfKRt=V{$q4eMrf!~5uSR1kq0z^0caQhq#@3-D9hHkkd9GKT(k_OU z+c(>?98S-WC7}zt1jXg489CifuPUI><^9J37LBNbR#ULf)V0M0ufJ9j>Po{aE6s`x zCHy;K(0VsvZY8raLc>-{=iOIecICe^BEx6@{Pphk{&P8`M%=VVVT_FCvb`5b?2~_4 zYupqacS9;x$z&uHp6Fs3kqA$JK!&$(DtB(=K(p*o2r#vKG5}6; z8^`_n(4CcxoTS4*Xvss*=GlvsKGk-VL*lO|ya?f}mk;^&Y;QybpC$&`1_=c7Emlbr zf^I^c5sGokCl!aoKd0ikBjg+%UP}1F2&pmRZ{L+rTvg#}26Um$Whp%|U2msqZ4lF4 zNTK2M8^gZY@5C{#g9?&2^tMuo>aczlrT_QSV?xfzjw%8v_5ry0Uq=uBWw#F?lvD}_ zCbhBL7zML!Y;S6JSM46A6;9FXRYWKm-sPnxPeioj6sD7BmD95uD2|LS`u8L~z(>g9kn%UGF+A)?VgL_V2Av7`>V z3}gdMo1VFxV~oaRPKZ~f;q3^z8j{%%6p*qB)8n1m@xCIqmEomNGE8cg*zk;C{uD11 z?MYcgA9(#>-CkjNMY?hN(j)29bU=22e)&)-Fn?mJ%71ZsH z;e>ma``&jSWiPd$`WR4P2JleMCDw1H;MoB6kS=sZa>pY||-( z3XKkQ6y{P)~F$Hn5s)Waj3Ho}GdHO{%X# zfF$kvrs0Sx%7)>YwjZqI<=~^CxlKs$EtP$vCD!hk)RZW2l z7Lt{m(GzWojn{4ioFZUh_FYfgYekZ~drKLcG(;__j2Z%R&TEd?^bBDP?0M$%_RnwX zX6k#w7m@$D`W}8u9SK01W*g~I!K0i0mWU-MY;Bkx!GaBxVG3!oQ%hk-&)TlLLlNP6 zgVrr8y{?{&tF_!8{WV6MSF<)&r z_9$sCe8b1=aFXHcslczMszx~c?7fj6x6h|N zrNtNj{d7eBEn~b9IjvNGtTBO#v5b%=5XBFAXK~OyL9&(TrJP$9P)uPJne&*XQKy6#mVW5GQf<(HE&MN9JkMs)hIyL0+moTfC1{W@!m zZukxi1inyEwEH%g8L{0>+7ro!JfjX?;GB*7*R*kuwNF48OC|%VTRxHfBs|7KP}waM zcm$~ZHGci3CCHuMLJu3TQztuF-2tfgW<%+Ba>9aetoybF<7kH&CjMCJeg@Za|BN4% z{@>H}$iYg*ES5`XagA;S(MHKj1|rbzV{zcd>oasj-LKYf-HUUkq9R>=7VqI@9czYQ zSK&}RsY%<|Un3Oi#$UXY(hJ;pt!8Ln4@GmG)Mx$9&ZZ)uLx9>6k3E0<9RvdDQjWF5 z^M1PTjiirYHb`28mzmhH0tj-5trySV{S@k}R5*x*$v557{HWhj$LH>R{p#aWa3gZM z>RXYWhv;=#G2N3?V^Y>)$Uk*a%?2^NGg-jIV{(0^#%+YBn>O8c~zbr4Jxbf%MOA&(03zQ0)!O=(Wa?wS$eg(aA53H<(tB_fGnZ z>3cJ`nb|-VeytKBrY}aZt~s)Yhr}~qeFXNuDN!nqm;=CyEtgPWdgS1k>ykw5T=e7_ z#*O`7mZ#kyLTz?}1e>p!XvQ0HV>j*W08$e`Da#@-j;z91x1Irwind4wzIyxLuU9Rm zvZ1BO5oAZvUoNIT!-Q01g3n!zN!T?gzO&EnAR;ZNVR~u3MWl`7wl4w*|6cn&T}PB?B!*#}nP|{_2jtV zu0UwzfBjV!kkY2~b0#k&<9;=|Ymx(Qw1}Jc4ZTCxM!hOEht$%wnKN>#r;~{YO0Y|% zWg-o1>?oTNs-W=Szn=(|M$T|~yt=|2jXHYTQ~iWxW*b3=f%vMfa#Z?;zCjOp>y1|zwk z8Q&0zn0kV2h#?P9+|0qy`RZdqH+?UKnv2t3=2`oBfLq~S!-G)TpaqqHKS&eGz?}OOmoKbga*hfDPbHmoU$3x*nCFRKt#9a|MQ}*0l5Jn zo45Xsv(*I%8!Qv?%(aH>x3{&qMFun>>=W|9+ea5^(K`h9j_bpaNVcOvl-sXG6*njh z3pAbTvHcng&?y_eY~gGOHTxwQFPU;6{D4v_v_LwNY{PC!Eb^n;^={~IBu(I^SQfW7 zQTj6C(r_KW-6lq_x0dR&U3fuHk%e8R!^H#48G=rq>Y3fm1BzE$N(sJS-@dO~%pJOi z-4(bvTfbcU6m9bW*419^IVlvBTMvOe7Ui-hUB^Y_|5m2Ai$qv1nUcm0g(P5b4iMHt!teyya%+2UIT!$Y9i3R1b zTqgMK1b`87>|(Jdmr3VuFW?k$_I}RmsL18=vJArsD`}Dq-FGA@ht0UUYeg6%O4|D`t+g(5KsqqjqT>$mkut`rmJq8T|2~Ps6dC=WAwb34Qw1k=^Ae4|ThD zAEqBV5trtkUz)`<`UDFl!DeVVTRnNa-jjXA$pPHb!Wy%!{CTh?g-BFZN1sdD6snH(v`R)^UT8tX45 zn!^v9l zbk~vax%)=nv_FTqn##9f5>S}>XXIsvCN|3}wn zK|*uC_B?6kutSq?WTZ<-aYI%Yi3W_Y_)T@n)xn^o0LEcFZ+>(#gq7Jj#iv??)XSkt z;pbKmvw;nkX98$Ni}U;04Iiet&;lp@EMC38RqtJD%^MM;KRB^Z^n$tjDX>-RBL@$C z`S;6TWRpOYyUM9G`HP`$pKnj-ggRikT;xRWY993mg&MfXpYYu_Xmax3 z-f!Tx1-|TsJQhUjq_a+E_2M5Z0FK-1)!4zFJv|}p*?2kWuvoA;3cs|by*!qpZ?Wjb zrNcq~8uQ(MO*VMPb?w~(LiM|y@K@Aotbwb3w-deNH-!ebZxTKAW;h{ouB&TuA+YM+ zemV|gx`<%2wA21~Rmo}uQ%X5XZ--O-n{z~#cmKV9{-dv!J@l4+0{{j#tzRv&N}|j4 ziUQ39WlUuj1(n4*f654mSQys{L zb3&0}2u|j%sGp&`N-W>JCIoA*PLD;9IpSf0=;;nY)XohX8e5{XI*}wY@aO%tfBnK@ zX?PpeD_owTL)tUQJ5si`V8e*n^?F)y@6dS_)rF-|=3dh9wfvEk&zoQIljIH*|Kv1} z;*$2blqJe-QZ=(G4JY`61Zsw^eY$|u1t=8&SYOMqHPL=U$vJUTNy>3DZ|Y>q$+CC1d@Ls?a9~@HqMiA@bhbOwGPF2&gNl zkiC3&`{Ix3-Vp#QJB!DMSbp6cE&ccuXxp(vzixU1J;mr`EM-o=T3sncV*X(_j0Ee% zVW47{D@i1BdGq6Rj;GUj)JcWVYRj30mvr} zoG#9O z!=tM8Kr8MrYji zcXe$U;f5lCF0fR&+eQ$P;j3>y{p#=@U@}p3PZB5H-D~ZQP(>D>4+rK;z4(@_C^Go^ zP?ZT8Eqrh{*YKT+vKhVufV#sLAii74Y#eM8GNVY~PyTh+jbk@d(n{UxtSbJxp3*{W z5>VUy@jdi0AXu#X6UrrNFSKyD4DY)oh zSiFEfVQ(yJQhpZt`8M(xmPq8h-j2`TZ~OUU8ttv59*JQrt5P%y{4@ z^$CtVJS8V4Fh{uW7UFzrfEc^(Zaqt-LwJziXQp<_eQ`R1do_e!mYe!dS9Sis2 zBo0LsGjUi*L4Wi!`iUXsKvRDIIdw+cPtb%NNeP*HUB4c`iPTr_HA`1YHXGdM9bwa; zI!-$8T}bEOa#`)F_+A7miY&reMLME7Ha1}2FbCicK6^^dOjbv5SQ^nxTGzcyQ?H6O zeXYLfl|11~3g$Mqhzf<&1F>%tri|)h`UMkFQ;Cpq4Z( z1RT#lewB`i$^^YZFu`Y{bbUT#?4WvbcFR}Qk%D83B17LBv>CU@@#7C_;ht&HFPH2*w~0poriqxz%O|7)gyy(g#dc6OyH*v72^)ZJDHwU9bZ@%y$hbJYVlRDbnLLwTsH4s7pk!uFJaU?r>EUlzTe!BlZu!zx9h z&tCMDN8d|Me{@BHYS*Fzw2^KHKYdbB-3XIf%sVa!iOT+Kkw6TWXbG%47!l;@QJF%j zk@uV)(n${ScOZ3FU;4Efux%xG&fhGLy@6kINE410%zy9aU;xu}p9hCpjLik|0_@50LPS_g3qkwZT*fckeq+=EH)A z(gZJz+`r40I&|;qVQhO1D(F0tvaW47@bkIUguXlSxbXDb(_%QOO4M?g=$mVP^j$5j zB3dZ@f*ww#4Ejv@5ak2qfg>uV}KuYAnhDIRIWaIG- zQVP9)!pJP7t6I9FP53l&mEQ?)R8vh}A|*~s0mjFwU*Di)uXF|RcLDFp{@C0CT9-sp zef`f>`VYm3t1sEx)77VHRSO53=Qb#B8$crfM@YqDXzPM=5rn9_VE$7;2s^-r(%T5} zY|fe=y*?sx@?#+KY_;EEMgy6tuv0F!NgJdo-Y4L^;@L`<<)j=qm%CU0l5i4p_?I{m8+sj{@ zpV<+7r+j1-Urf*VekrS9#b16jXaN4ARUU_X?1Qo)yzujMkD+Pu_U-NTJ$qD{1IRA- zZBMBDpO{B3^v%bqJ>rH&PdI1$Ztr-PjeX143ChBWi>_D+V|#|QhNSqi5!>p}Ki(u^ zGDz!_$iW6Lh7Dusfk7e8*SrO4IS3G1U4DbT40nlJei#%;w$MJw%GCVcadXp{T=Ohn)^-ZR!U}+gx5R%eLM2O zvBitd!iP7{?!Wz3Z+#p_dUT~TJNG?1BtLOs0S>10`g`wqWPP0kc*5#$eyT8m9LeCq zX6~N-HfIPmjltH&dHv^#j{CS@2`y`>Y#!+VIMS78l`56#^L^M&Us8-voVe|XpGuK zxCnPQ-&g$%EE(f)&0^^}RPd-5_fmLt^`$Q3uy9^~ow6AfR%GMl5D+;A({5A65^=^ur4xO9jdpfD0qm$IR$aY+9fAza5 zKR-SsE08&uQUJ$kFDm|Ds_@H6K7Nh80qVC&N&Zfg^I9jdw0Ip?!ChSi$EpX=PM4ym z_Z>LKYV7FSk%)XQn4wfjRbPhaE$jVk+6KANWq^)WAMP~%By%}} zdpKn;X}FW|eU`;8k4a$@Ayz2U2vth3WFzX3hZJH8qM!zN*odYzNvK=cqSFXVLrDC`QST~~ecF3IOnwZm?(yh#|H_Dy}T&}t!~ z_gu?_YGfvQh&$K199%=?)@OX(R5UlH6}eSC`d%mTetlUD@ivIv2!gl7+V7vv0b8L$ zNKC43`LaJJ^+c%#SOlNvSb*Fdr+}mNE`qFG1B16^SDmQZ&7FGxWWoikN)JxfpIf)* z=wHo6T)e&MJs^`&l3SKyI$-B0IC1*L^;bWdLZWv(#R>;(nW8?(N(z-zB>VCt=f-!% z^E7!2@4oH;LaW;v(d@4Ky%ba!308c9c!<%7s^2kkj<1(aoS(kBQXY?rl19XLS?6R7 zCLTEDb~q<8Blufr+J9|$o3_bFZg+5T;@%VyjR0#>SlW<(!VQ47jaa`c;!lV+0!9N% zy}?4NjVg?E2l3n-yhOA0)=0s)#9B$-JW0pMUMEBANT%aS*Vh|?MDq50=-1me^=!H7 zm6H+7PFiFeDvKyi%O@@VxdgScUT_Q#tq%)4bWf zYSJ99!MX3bR#?MN*&9C0I~lby3z{*xIFgbde2cmx@jwoa&T-flr1bZiIi3=8b~y0! ziwQp`0E48 zLyB%9Qkgy1#6%-0uC*J-O7w1YdHGbA`^B@L(=;c0TnwHlZKzasPp__J&>^1|q4Dmj zdESVld+vxu`19SgAJ9(F$@6|s?BEGvhfa+4cXETD`t&1-AVNA}13)O6gXT=U8KCEa z!cWf};!+Pa>D+pCg+>%owV5bE1^(A|nNA3A@){F^d4n(gj64=kFLoi3McXW$b@eL; zZan2bg8;SJNWt}pYWuH|TOcS&+%7ED}kHOtP5*n9*YSICswFzkgr; zzlk|SYeef0$8c=G4x2FOb?*g_41Z_(1bG|3YXdG&?*xaPqz6a3GcW7a`}PzkUhqk& z?&GJ4$t8b?rK}UOc51T#kBbqODmWUH@cwY0o!n6z+}|dvhwz~X+fwPMXs`?cRc!%) zy_^;9lp*)}L_r7{yX*HFE?04h4ocxpJGysQZ>EaMh&b#<@%o!THdRdk!Vbu0a%-;N zN(@%~Y=rHwS^{Xm-M2^=X^C|{{NcCe<{(Eu-%LeSprd)S| z1h{YwdpEn!B??lZ`2=UCLn#{18GKrleTs;TVZ-43_OrpsprTVw#c(m}qqxMID$se^ zPlasgPO6(!+A_)(O9^#De5+x*Sv#hWZ@}MYcjfqHcY-p?VGV1Jlr6l&CHM=9D5Y zk&BQavI?~qSs?<^fTaaSC?iESdNUGgquz^H@#D@`<4lex>Is7z({mtnLHmH-}G`taKo1Uz=v(6k5d$T;&*QP zr+QRIc6C}!0jo^okU@%9B`k$mY_IMABiYrrPsS!+clQ3MdE^?Ai*ON78A++ss ze5rp*L|X0fIn#bqF6F|;ig6g{&q3x8Jt_{rmM57k1+CcEGE-|u{`Xo1P{xi1a7#2i zt*O}PFckrVJKvC+Qk--Uw68Co{Y*x%59m53;Yn2V?!HI@v?%4w<(L%&e@*HXD;o41apDuhHAay@&S0d)h@fnT0-n1Z!Zxmw; zp`CA&HpJ;U|4D`2FhO6Q_m+@n-U}!{SYP$6)DomXz{cb4$WQj$oq@0vro?y$@|hls zGPeB8C?G8**$vuUII4szKBz_SG>}LYRm{yc0NB=@qu9zZFhhgj){}sBj=<=S7!GD1 zOnwpaDrLeU)!QMdJ{%D01Zv#nsmSqcE7aTJ<^MH#`8puMfaT27?e6MRZ95}00l-JW zr|&+iF0sX4Kdv7D9qbYa=c&q$2u|)V(*MIu*X6HIkpz}>^7yDep5%?`NV*P2F;?fZ zNyY6c1>GIu`17<<8?{rGq8=02#*l2jjDWWbRx<^KIs=_^w$qgaRP?sr&WKbqpk|o; zI__jt;Hs%qA6IPcE~##s%5arsnR=h>oGS+pEfhie@9Ocs0TQFmz;hqV)CIu&*R=nP z)AB^*>ddColg2ZNYcBh(aUI#*y^+$+5*ZMmbzmWZcM<=NgLU>jtY4s<_Cba~@!PmnERk=)P>A8QdJo0>k+cl5D8 zeXV`9cXqmexMqG#s$F14Nh3AM2yDONmm1&S(F$+L+;rJeH13Y})v-p?Wh$*YL(1TX zETXj&rgye4l|ekqwH-gG?mx704T8*37${S|_e?{><8h(q0Cuq2)(izXqlF>J-9Bk8@2@Ej=l5FjN0r6j>fMhdA&!=0ZuW zbR~9qs|z06oBv49_9Rxb;#VzAg#we#3ISH5v|e{GhBtxb=rXDEf8K&7$eT2eRk$wH z-8K!!J7-9>qrMb-v)}p{gWC0yknhP_Ncw^TY{${|s^Y!KUijAdmoW{!=IUP1747=m zef^vzOYm=!=bN;Dkt<)_4tK9& zFf#L8f~bqcTHLp_P{w!$23^;o*YD^#6tQlQSg?)M@^LWg@NfY z@Fd-&qI?qteH_J^Ky^-k8RuusukCaxCe)s~Strhx>UK68M&Mk)Ho*1_dq|h;@TG>C z|E!N$eU4I;ZHoKj&X_n)akr(shC1ujm%hKj6g!(Z4{H>^n|y5;(=OHmrJiTf>ebC? zm!2u>@`c&yTod=5GNT|&IQ90f-Ca^Cdr~l}WM@yl!r1T1; zVWuVGuqoK`Nh3(^eMJC9b$^m3sT{3?%7tLcISI>->z#mkMuB@&B&FWS?hy2r*8!~otsG>q%*#!4tY^*+YvJ1y_ifoc(Ql}|ZM@i;k zQzj#QRm%ajc{GgKQX+FD6u;>=kdTZZuGx7y2MW!3Wi-c~g%5q34F@W2_?Vq`&~+C; zjs_mGq@a&}10_oV!AACVB7~erbs#n2xf^FI;@In6wg}H$HB2w1#wFt%FYb9chRV)& z;25FnM>w+FSskqR>6(qO;=}dy)@qpc#6Iib;jRt}))3@_*YoK~;uXUV;+}ep1U8rb zJ12X{>zL>Z7~gXsly!*K^(A+`-xAl4-aH96zD|El7>8K8a2?C~`^WMdV7md=bUVC_ z4DCy}54${h8%zbkKGFUXyp)GR8WGk9Vjo9%nz!NLx$F}pO=1#`)geD1W%kTc`xGvQ zBZ>2ap{M_?6CdX+f(qf#m>GmG{iVVN)QbIAl;USR4f9P^D5Pzvel1vt0;3_K730)T zZ*3^T1xxr;;$SOX;oIMML7%^w4oo-&}mZ`~9DtU`QV-xA(xE$)rC5 zjw}0c2U*vGI}h($tke+3@-c4d&Fv>Cs7E`p;ttB#3JF{GtUMh50yRXS#ISY5p&r+2 zrLP5=6brDhIm$w=R5Qr0j6$qu@2;O}Js2K}uOl5jO8^@peYh(LIXLOvW6Y4E+sF^x ze0_WO$5US5Dsd`~sHq;`Uk*=(#30na7K-NkM~Bo<_yH6U&9%z3yGIU(A=Jqbe1o~X z{YulfEd7dvGHomCm%gBX{AZdN5gftJ_@!^}{^#cx)vbY^@`CbCii0cd8fYu>br*_G z-35lgKVXjR*tt1`A#4G80z;$L{P8w01fj++h#xU&_!@E4j@ZZtvgCvA#-ls9%B=)S z6Vbp^{;Ar}1GOU$_tcArC*>gBeYx(rmF3k_)hiF~P~k!=<$#;fFn%QpzyJ8WE-*u( zkjq#tDqH1<8#+^CsXl)Bttz5fZ5=DCh5;qR_-3sxvQ=-X7+(>8e(v`E`R(J`^&qa0 zO2hR_PKN`fL;=n|61B(`dt}`Y<9W0#=2If$w6&=y z;bGqTk3%{(rDH(t&wpVn^`Sgfifs7PugaoV7)%r%HQ#b8QNk|i1w#S}mwg_k>-9e> z>f{*zuYdphKijYV^V`bQ>RpAW7gEq9tzk&Xu*H0^ihuM|(t)tGhZX5B!OvAfu*UuF z>sDRS)grYJa)K>?(>lS14vF**MnedGeH<`y&~Mz*f8A;0PVl5&gT&~5#F)OP<6;Zg z_=BgRi1G)1B(HPXYb+Z?CwV#_;Q#n_n#J z@n{ASRAwys`MG7MAq8G~TzbXMIFfCSmAHJ`k~(4~F<2qdlW%*b)+Aa)}! z^|Mh!`Pkus4=^X+U6-FB^=Qz|g?3%Cb*t3(p&ns)2v4RG21DXU9Z+)1+b-qMuT=1F zs!3aOu&yVDg~5F(C7v#^WUQr%V^^e?li*nMzZ>o`1a4Z_L*?}!{rU_s$-=I@$KOAy zT7IP*i8d?X|K{sIhQ7=SuMmX2b}W_}gU5|0Kf)IU%&+%Q?RZkhLO?00e?532-A~4^ z9v)eDx)E#tuK#G%gK;E=d)saX;1J3_%9Da!mi>6`hUS1sv1ZLbSO2S(>O$q5%1T{F zKeA`*msFRFC=vn;xxez2_$&Y=_*C8kJXHIfSizCH&G=^n1AoM!R+6R0xQb)B=V>M$ z#-c=8FlTf+0;CxfU7+y3|K*(kfRJ8D+s^TEC8oH7B_D5teb!fFU&G|zk%cV4`a=D! zzWW#rM0=t2$F)&#ox0mVE6e5mS090h^2sJXOi54V3Bt<>{n~X=LQiA_$J7E8(!(QLJ{Tm^iOO!lCavCURew zu&AC5nbw+-9qyvh1u~vAJy(jEq{lH}en@Rh4ImBah!)+dbyV;e;~F})39$OVeY(B) z^TYHSNZw=v7|HR5eI@PisiF+Em@SF|kF&wRz)sdEG*r6|8kVe{59or+4zD8i)sE5_ z)8UhsP`hGFa_yVs8Ws|q)XZZ!iKocV9y5gNnXhfSvyE_~hCj z@>y6Iu8einY|lIf;^B^)6ZQY*c_aKQf<1d&TK%s|p`x!a|AMLkhjhKx{fkZvA-5rz z5Rv1aF36%p$bdvAn0vJYk;T>+y^w+m)Q&Sm3!PW~?~RdKo_$ZFXVJJH$jOvm@;8A| zxX+nOg~3(4wc-ltAL^3o1ZGFMij(z?lL%Yyl>RH+o|#$>x!+3sgHVx!U2fr^(-l z2`^i#!H`>uSFRT1;?HmQMPM^TYh#h*9X0diK_YuOZlZ*wKpoTGv#L=}Hf2KAEaaXm zS&hhEGS%NcT~x)zO7{U&BZe@QLBBt*(jY?|2#lT&Z=Pstt(VtW(uj8iv(F@Gbp9cUt(@%cwNA&S0 zm}4%*V&g&=x;)wwgrBX!XAOe#V)60HF4IL1b7`$T(UAE{ZI=27dFT*8e(6Y%>N!L& z;o00>!J$k2bHxg1yc)KOJ^lWwuQ|nNTzre6Hu)iz>Nk>@k!XjyzkNc(^GD_AUh^5& zE8L&Sy*$B_&lbG=@_hO|`6=|}%p0ULgx;EpO0d@D^ZN=t z(_kG4B@SBlR=?qaX5T?B!8czoKmYZZdR_%wmrS8?nQ-98+xaO0yo0$!IzRfi4(!(L zsP_AS!*@=H?=lFJ zWfapQ5(#cdVgz3;l!h={teDwuLpJf$>VIzJ34g7us^h;gQ_;5mT-&tO{wcTeTDkv^?H)I;Z@14&OR7u^u&Pp4ubQ6oRqJ;QzjBCdz3nK3=I$qm_{w>7~Bu56odwV&V zHjxXq8$#EJRWCYLrA|+D5AL*Fynju9P`IG6GcRq}pjvnw1D58Y%|xF^^>)VUFQomX4i5K*4|0g!Aovyj%c^Xc|_zvK=CZ2(ny-2bt5p!jm zR+6Z)fza;J=r!e&|4!G8-A6jWYL89>R1H>l{mYOJ@zO0SC{51!)0Brvh8DK{&}q8C z7kb+W1D18|EB8L(3GkxN9(HFhtL6*TnVs~D4}ad@v{OrY4-<~`7LfGf&vzfoS0>don~{cEpK1+K$4|@X2;FfZtPg zp;)?hU^-K7p%}z#`uP?o#jX3YOieENpPedsH>M{FCtlQNml2O3J@ySe;m!5^)qhG@ zXoUc&hdpz1{rT=<%9pN`AMcJEZw-sDeul-d-p(|uN@#+yFuypEN?Nrw&kopm%F+m~vrcbBMCJLzatT`m&UR+HVgT z$DT!NA~C*TnO?B4+BC$Cu7T+C=_%T$T6CneVnGHV*i-ISYft2Su5rHX`D$9v!w5cS z?<^ih?{0+o^E1S;Y+i}vpVLuADi%^_+4i9b0^Ui?(C~&B{Gf~1M~U#t(h?gny!&j8O0a* zyt0>sZYY{&W(OIyf6XIt1s;-f70n{@9r-!|{3z5f74H>|_AqaU62*NKHft5h=0T(- zI_RTbO}S%rXgeY-W)GEYBCD>T>Dt-C@RqeNTBD(3@$payzW)0{9ew?lE=QEhvkQTO z_sz;W&|htrG{A!msC$K8HyJEY)zbH`Q)~zHijExFoV+&|_kR`A0aOOUBjiHu-7H(y;WIuBqixM?Fqb#wo|*Nb-+h48rE zx7TmJ_IfEx-b~%;jqKm$Phir4>Ldl3iOHVG)vff)JVe7tm_8bnlm@FY(qN*XvBxjJ zd|TD@YyBWalEidQRA-E^1opV|3q9V)l?jeCx30KuXp*UXs^9AmqVQD`6@Qyd&v(T@Z+@N=vf8R={M9#4*r%)LYD1Ke zn(uzHnUvfd!v_j^`z$F57W)OUcp{L!qFRmc=K5aaM&;*g2o$VrQ5-c}1rQu+ail7c ziCMVxwfkw2?vRvo2p4&Y{)1Z-d$3KH)I(RpuPn6W$jL+aS@!-=dRZPke()3BY7eoS z@waHq>RZ}2$0Ih2p>s%-Ra;#B>6Y2-p ze%v4WZfx(6mwctq#08Ph|Mn1z3#NS7Rdr+z6@;M~#CslV(o;A(a5{sFDd@zeR(^6* zC#2nfa{Ucy0+>!s_TRxcMKq@$FkHMie?cE{DgsumtwS<`~Yv zb^jXi`E@JVEK27S2&~y_F`7@MuUCgwGT@3sJ4*u_p`DSR%9TXTx7UkLau)IOwTn>E zg3mpqcenlOgUE{Qn4S_&YLqjA@ZWzr>CteP;2H=qCSv0f7+1*#xCexb*MUVNrx(_`dm_vE1r?UNz9|KCh_9p>-U;`O0SAZ;@S;R zydoF(*h%Dg1J;}-s$YXOvy19-I+xg4aE9kU&%m*as>bX|C`CoAjr<{ZUv`5{#?$;b zp@#J7sBFVMtOoa|y6UXdVrWunq4FNV)$V`MAI85$$`12J2Iu~2fmV6F|4^ckG#lq#tRXg;pOu@e5nAEr%gY*vNV=en~m+#6_@(y!@I$-M=LuCu$%o@>J-0W%JP2 zfL;uy??mRt`_s(9ofuH<=iRJwa|aF4&3-L?zHIi|00`Dn*2ut#^QJ1I)zL2S3oCv7 zrX5Bbg7QgCC#s>F@$GS&YRkf@s>7dRXdFnB!8Z^S6k5qRwwLUSvLYN zS4zVZrE-*EM*idTZC!l97{Zc%FyU;8JgV;x3dQV*$u<@mTa ze%v_^UEa2e_Q-L()ipR#2jw`5wbtm>SF0bn@~CQCI5T z5ICjjZxEv)l-$1+X=9R#;?v)L5uYC8$8M+h)Vov#e{L#z8dhk7^*~aut&ow3!9HBv zzdx>+c0=eOoZsdB8=SC{NdTNYpfzo!j+qCP9m)Tte4r;EiHW)usnM_h-nf5u^?U8s zV}|HBt(r#43XEUx!I?%t9E4e1kv{zNe|9WrprN7t)|0injYf#RJb=E*#(GNGpQ~BD znZ!WHe#fSlq8Ne21Mj6{%IV%sV0=mhk;lMWv$| zNI@Rz?Zq#{I|U)?>$yBj`P{U%OeKbYFt&kK_o+cQ*D7rUAW`M5Tj2QE(xmiiU^CzP zZan61Pyt-n31YZPQi&o^dX);S9$R9K z#8zRc77n20`L-Zrxr(Ru?knbWmv*JHj&T(?^kGQ6hM*AElP)zyhQPO^n0+F^7KGg0 zcUmR-4hnoZt;^!{`=9S}Xv27TDh<0jmbtQ%6ACZ=KOVO+HCMbW7s7JyH3V?7N$wA< z{@@?gZxOTO50ICCbMfWd$7;8^LWSMYy=zaJ=HrtL4t^E6B^jRtY8Xetps{?XRDXW_exi{Ivm zLbRZb4i4$Z+c)>myM^b9Xa#u~(d>h9tLxdAqE*~Fe{Ce)$Nzeod8fiDmB0jM5@z<` ziNuQflObn2mnE;Ln!%2^)(>{Se^()|+(f=Kl$VWKrlSKTd@*HftfYt1m=-LSUGVX* zQe9k~(4`5-cX&*ne&I2ZUWuR_g|EemKbu|#E#|cgYWciQZW77hy+C*$jDJ6NjG9Ig zd+DR5zNV}XcNZ;DW_G2UX6x;*xQe>3@bm|Bc8B&`nG{OQG1T@;W;F) zep|B=C~O8pW$3OMsvaY%8;~re3*4a+j^oa6~oY1nY0Cp>57ySeD7nOMINTBj|;1%_m-=E z?8;8fdB;N{@A12hwF>7-jI0VNLigw{e@qSn4HIn*OxJ==zAv`|7gy7EsX00PPjhxT z8LYDioP0GHCbNECEK4ti=a@@z11Z4V~TBCpPzIKRf6n83ya#a0E^wg;yPO)nzh<~F8nV%29q zVMGp8WUwAQw2oCJIinDu_9d-te}>Xe32#aZd2}3s&P<{ixq*~{ul=81xYHxlE|z|c z-S_FBX~+oKCF`Wbbh;_RQ0IqOtv|o45IG-n!xJ85UT@x3oG0IXNKSy%L%2403^g-2 zJcatX;?g` z#TBbn7iygAqp&Q}&rhm@qE{ppy*_jmce(-)apKd#q?eLVh*|p<_m?#GjYmpg0e;s7iJ%w<)1vFj0{O3(}hQ)vyF}%OgTjFs# z`Jjs90~n8cx)DD^M~bw^Q$HZawcr}c$e*|e#)3~7B^`t$qL$#&XZJm3h#%&+K77;$ zR#i~F1~owhW@@3MQ$mVJ##8tG8pr2wWQSn+u4#25pLP~z^FO)>g-@PoaYGGlDbbtj`7!rp zllPPHi!a|dh5X?Tk8`2v-rxV#Z*rGK!{;E_*Qwjg9!uEp_?hS1uSJdsLF@jM{Rc6sHY2Ps_z(A;Hag$l zl@{mdCi3}h^ey}Cd0n%{lg3p0Ily!;2?q#yD-*tp9^nCophpFWJr=x_nJTlHC(o|<}&5)#CU zuI*L-B19D$EHBvj<+(Z$qG-6%OGcz;*a+!=IB)dzf4W`IWoWhTSkw|MTfd6T{f_3k z@hg5|Hc1MRusGNX>*S!`>kzWsigVz}!Zcd34P)VD#p$8R4V?{uGssMsXqo4ix)g3oe-HEj z=0dXM*+1W4OdL$J`_=7&4%CfeOdb$ZCx+va87R=im|C$zdGQ6Ncz#tN^-BU)n>(cb zO^kws=`J#cLcA%Ukt-W>{TNIdJ4=D#0)535cr-dMm15C8Cp$9WrYRq0OlLYt^P7e3rTH;)J9B`qlMux^O7iwGJ%H6mkN(>XE5 z`aXQLBF2c@YD1a#QGJAtP!mpKVtVZg|0tdKmYUU>JjA0 z*uK^jxwx0Ix&A(E0yua=+3-Ey6tekp>j*vZ^^)hgzrVOBDvL2ouWy_CRE!u$<748* zQm%TrrO*5cD&3g6`-}U6Bwq@cdaYMxmMSygI_u}`V{I;m zPj&F%P92U$IgkHm|0!KL()-g2NdkZGPnNo)2L!xc-1wJI9r>5r&L}kpkW|8hDKvfQ z6tWo!^>dm1R8(V}CQFLNhoAhzfvlGbt8(A@Hf3*TllXF*AHT1zC@(zh$?x?X#Sry= ziChQtaMSam=Ok2XaCe41`JZ}j@09$_gG3B{hR5jpC2?dvg>qK!8DFF_D=*=3JKOHa ztoxJJRL0nQl78#GbaD4b{T_{p@eQMg%dN-L|DB$JA-ybjSgu2KwM)P7DY^pKEzyEmm`}4}ry$t;uv;Lnc+IU>9 z*Fb49oFgMM&eo$_=P`~VwTzgtnWknaJpmNaIFjRN)mDcvhklbZlyLY5HLvrpuS+3e`>vW>>B z@Nk&%i+5$ll>((4A=vg);pmr)q~bMNOEk0=L-@}b+IsvVY5IuJ4Q_Wrn)aZ0_5lX+ zwJx5YP?48AO89_94@Cwo)BbWtPEO$*zRDl(Ui|UXl16L=g)`{dV)yDuMCs`eJ1Dp! z(7MDEUm_|fjp7Neb#>a~(Glg$dh_C!Q&wPw=fe9P&_WuLuWAZ8mU;oZ)B}>s^%su$ zk`@aEqKMBen&nS)x{Pl-y-9k$Bkb;Ct9jkk=p!nK#BK+KRi{hk!D~5ytylj$dcYsQ z^==S!@96IkUvMY~wcnzCP9}pd_@J1!6=xt=Xc&j-;Rv%PgevE6=p#MQ*ykgUZU_6(& zAmqBGman&o%HTZ=j#nRUp9=nZECmh3#C(EcEqu`02T1ttlN~2N8|0>~Ngx*eb#em^ zzi=Lt9y?0b{Eu(HFo`5wSZ_5RZ{G3wrV#9Frk zdLHL)Z>IyRnT^nB@9Ib{?FAhkWX$_-WyGOrI+fdZobhK*<{Yca{il}gGEAGFUk6Nw zP&^7>vm)!$?HcRX&mxt(W7H9pF)yCdc@I@DAFcSuPP`7tF zNoH{diZ+Tv`NXf|7eA&2UP6z->I&>0*1yb)F%1=L)%BK}Uh1_>&#qh8Rvimp$9R`( zPi&e_$DOw9Uz)uAa+m3F*ZRG+IqQ$XI+a>myG&oYH{wer{akVzCf4ZLY*mtEJXE?h z79~aMsLnX>Bdk_#sGHZF-g`pE4t2GQO_hFB6)AKy%W7etgxV)_1y zj_p+tF@SD~vGG4NbNi+8EyB&N!npU(WdFI@_$|37DMy4<+2tZVyXd;yla+qQl+ z=NUuT-Ya%|e-xBRN&FTyG)bx3zWVcI6$;2K03^J3oa5CZ37}9zj&Hu1%mI{;>JUGN zM5qG3aUC8IMd_l{+)-?@3nt|CNA$xMe|}phBjzS_TOx=p6M1)MZPN+RP)u*JgaGmZ zdi++&Ln^juao}BjF_ZN^qAZDmM`w^aTTTh33H?6-1~>`f3^pYpSnla?%He)H>^|Ua zQ?P&=7L?A}7+!LK1%IYo1R#ZUc>;0b5pBj=B|1PcIKe%iRr_Ui3!gI|@s1oIZS)0j=v{N1-z$m69%gVR)QwNPUy$#UVv> zY4RlWjsPVK#h@k_{NbW6x>%&3-~rUZ;5#y*05XDLP<{x8!4m5A3LmGh1Exv=rcYSB zJZc848z2TSt4zqg_-$a`kGv9bD9lrw?bcmLt-Ex2!Q$E7A6_N9QSBt?GzQ3DA+K{5 zW~3PS8u|jfhA@FjjUhUz{FNQ^J1qisAb`|unF;Y4z>zpNMb95Fd0KEVw{@Eiah$+m z%%1mJQ}21GQ{XTFW)kK>4`n7`Glbw;!h0|O+*egBH&bbQ1-)Q+1s$ZM=`Dmy2;FB; ze+}o8?|CB641!K62r3Y1faP-Hu+P5MH#a=8wD6SkD|t&3b0bN*f(*D2%r%7m4JPVz zDxGvh_zL5v-YW~(=0{RoSc7tN9dLQ+e(9gN`KD|rp^XsOKTQ~D4Tu$`;)ByAS+*Pr z8f1;0TVX7vh~9f$k0!zZpWcv67TnmOI*EC8LP~j# z;Ad&F1Pq~21d*9MO#m?hHK}62`aK}XS`l59`#J%qggKoqXn{jMG6atmHtvSNzF?Rt zvS1bHnC2K&aM`*Sk*?WlF+l!dW)PVv0wfB1a|16EEfp|?C8Be0S~T$85&*F;sgB*_ z8AYB6!7f+R@#5Mb#8g-M3uZss+xdll)$TJ{1-QKsPyyDa=ZBn-PoxQ)PvxI(W|Hcg zq0l{(md2^ykeQ;40S4}{J(L*byR<(eo)>&xr4~tAQH)6(Ff6}1uCpl&7=Q)Banx=m zlpm{wG%}atCd@qg4VZGaIrSiQn{7r(H~HiuZDPEBKoUeTh`4|K%~3sl!7wo~XJ`y& z@S3{(h_fNp5db(3!xL${;I`oVD_aQgy!3Z| zk`%T)>R~-srP2vlSvZEI`dB#Uy6A14(-mMO)O^JoDcJGPP!~Sa@&GgyW)N5z7NL=G;CPN>Zl-J;tHJYIlL&Zzgywm0Q9z zStx+Dww_7xaTc+LsKbjfnMmQR1BU(xj zW$Dg|hrlQ0anKNJXmf~~T$;dxSJPa#zkL0yFDF2aP3d*BsAlCf!LXA_hvmZ7(4DDo zpfsSSS2!7bSj0S*x@h#FvlSwaqZ?_gNK4HT%e{;9Yz!8dFOU@{C_iX%u67|36tP{( zLgfcQcp!~g2~6Wp#yf~D0;dwdu+1SNFumbA0*>Tvyfvu#b@`6dCNx2CooqzZiGYb_ zE+Y>|d0jaJ>Lf#GOyGn1*h7tG=w=SdKkF<}(4%t=ZSaD`37wKjHb~z7>u(?Ht&%K& zdZC>KY)%K3-Rb#tqm(ISf{?BO6Y}ap)2{JMz@9G6E}2i1p&ILgqmQNPV)rMf7OGiC zUXa==Vo@eeMN}-I(~ck)0f<=VS2z`53y_E`I~jIQrPTNijv)L75CqTn`?Z2}-4Gh3 zqc`abAO6)rCNM&MAe)F(ECq>esY!uyN?OYnJ|f#je+Ld5nh%$qLmOPKU}c zwRz62!4V_>7$#FGEU2ew2tvL;EUwbaSge>O;30!RG~YSuFOH1ow>7U$`WfCHPO(4y zW-PAduQ)YD%*X9TN{IGK%`Kp;hLDfV>~F5mBV^?CSwqdau&8MhbR(coAa5886z8LN z>~$Enl;M-8^ZiEk#KQDVR9U(oig~rw+JtI%n#l+A6OslcVquAg3P=u}*Csk6vY;M@ z=7=t@@0v5{eMA2Ue0rA=IipR4`)HLTU>$7YT|@Y8sL=y#01nr=V}`qv?^2+ULa14+ zjXogs)uVQcD7Z@^Jejqj*bCftF0On-_5IC)7KB3B#oIcs>AN~x`HY+#x|3QrDMZo= zj1qZb6w=?QSWP{goW5p)?iUFf1yx}M7ykx?!?WvStWe@Npz0wh!n$xF;CfDpUK2!~ z(bwUKsja*0&(4etQg@wd1<~%58gAf6%qT~~$#D@xHqSil0CCWEc zwnHme<@v02$X20Vo_Yo6cF;FX?Irk>AtR*pqZF0O{8*AQ$qNd2oF~mIf3u_s2nDkh zLR!Dh1iKRFTu%PS&IYll)5sOi0?m(mlA%UlLj&mMW}iSSkMouC!3%y)qL z36pzwBYM9n^*+Qr{aG-jlRK^E#GtRSc^A)q8Hx7_MygAOLAS`T5cS&cGF%^{Mis$GPtifUarDG&>jEiLn*a)LQm#``!?kRf0kGpg(rc9 zt7aV#4aw=5M3I_m3OKm)8v4Q>y>)TN_i7~}E4YV0UuNC^qOe;YIN$!Nr zrIpMI2Py%f<{W66VtXU^>g&(c)Rfp4fvZyoT_k{RX*;XFTMSn8{ALHT<0!DBZdT3YD=@g1CuoTXs*E0shc8i^9B9Gn^l16)-d+>m($5)bK@bcPAxb0rfJ z(t$Wr5@{lLS%k>d27}(3vIQXEAxvzYLdatA<&g~dQ)KQ`#UW27!kP(~;)SB+`o_l) zfWVzSh-ILqYj`F~Ri?s$Xq?2-Il-ii|9r zTBZ3D@V2BW#OV{t^B2{$;)d_&(gEh!y{Kta$9EHm1Dsdk^r4nERHg!)fcl_N23l7p z2`Mh<*2HHMk3%aTzN3#i){FRvkqrlrJ+PGFz=iM+FPoz}`AG_(OlaVRCrmUpI+`Hoghh|Chm{UZi)r=X-DJ9Lcwt}tB1=8!`vq#^7pClc0LBuJ7tC->+BV)n?> z>Qag*eX{-Um;1LvCH?6?0w*!Z6}hKv>3IWEh6;ReW)6{92067wnbLv-hDdS%#a2+V z6WBSmO9J($gAXR$lY-@^;0jQ3Voz03cqKbi*c($Eny_uniegXE7X-N~dfOVv=^R37 z_KCOCYVEpi@P%n;=PKb{t+HMmnh6pb90)`?j-$f~nNpMkaOq|H*ra<>sC)aAu$MYS z9SK5?3#`tf*%>;dD#yG@p{N`eOyaJ2sU8p|Ep)G7mlXE) zNdliPJXzbr%cELuaD&h}OTWu1!={cP+#$3oC3Pw2t?OtT(S%~v$AJp`RZ6U-X#z#H zC}&q#UNglg5{D2$hAT0V&9|!f?S`)~ya6hPSJAg6?GK-wLytC~-;hHRI|lge8MRcW z#2fG>m{`&X!Mk+dl(Yb6$btgK6P44NSfM7I1Sp2F_zKe4TMdk+8aS%(qVT@u!DzyL zz+;7@$Kn@?Q9yhuuE^KfFd^nxWM8#cl~E1?+meI=oV?SL3mo=!y8ti2P8F4;^RtFH!ld53GkX(+{UhPHNe3R@4#8w!P+Vac@fh55Wc?}bevl8Js=Y|FEy7yF>4S^+O@BwXY#|vAJ;;>w1x!c78`{T6=A|9cOoWOg zG!^q90;4n-XP{4fPf$%2qFITbY)N`s2zU$AL4x*r)#yD$Pnl54Y0{>k`9RR3RD(6C zM-I&uEuyRKY~6w^m6|||FHs%BjH(xaKF~C=_ASSw*iRmU7?tIb47K!AW$+68h;RVYh3*Pdtu_~FDzKg;#04A0eCdr& z!8Z*k=m0D4Ds9HqJaf^M%)J~s5v-c_=O(8uU?vm{bzMi@EJLB5y?{RJm;+V~0cvC; zGPi`#DVa-929S-QGelC6@xH6h0q#MHf$JS9+dbz7wgI*&={R0P!fgAB9_@xm8SOks zx%l!GlhwrJS&}?MKA@EeENEjK?`uW0-g}?6|Ktsw*>UNR55Zbex*kqA%70OwAI03L zU7tf=N2VEuebqz2=GAg|$SBOMEI)hRa@gw7E`=v`UDGaP!KTa_W0lJ-;diD zlAFXr>~AQCl@@VT@%t!wfBEkV%@M!;Oe9Ue3&5Z(Loxw5Tmv`QJVYR4-bE-xiG)K2 zN%^Fon5zCG%#eANA&_m<2L~5FuGuFcL>hb7@s*W(e6Y zUVk;uzsBWD)Af(aGUSe9XuQeY5XJu9RaQXj0g#^EAkw1C#cbd?v z$B+|PxtcPQ9FPfuMh5C33J1_)7Z24NqHMngQ@x~u@z707SvcJAhec*mJs|3 zajELAwZj80cLf_RxkcI6PwKv{vquvGHi$%YgR=M}p0zPeAi4&*N;s9JkIq+%5SwLV zX_-xw|BFwyef@&_^aUu_*DsR0)Gs!New)r%1Np6ZYNK<%B^@pWRr}59aJ=jCe$e+x z1(F+k0Q-lDF6D_)w$u+&9!-tp!`;5a4k24XFb0Rj=!~}02)!hFiwFh)Q$PG_wZpLN zXcqVZC=rn)(rcr%OF0;QcQBl|G7}1S+CqTcMmw~Q2*V0mW5KtrH!gN2it(kgy;()t zf#7obZr_}OV8maLvU7UM(+WhLgX=Hx)?($8jApe$6t>^A*{Eavdf?BcLytNL*8&(Y zI~IbuF)dYK#*u^2X`?Kp(;_msJO|e`We$Fu2pS6C7;SA63%eCNd(1LODm6McrE6hS z*@EmT7=8<_|40Hm3aPB+kOE6?>Gqjxa>846N358D;kll;r z=!``Tp$-HZOc5e0R`?@!p}T5q3bGk5!Egw>;I|j3qHeax?FDG+(wNvpmUWI#=*(k*r0?zJ3H^sBp;2E6izw+yxR4 zfzkwNcvai7lvZQ+U~iPax&AHQe-MCDbk7U1ISM1LwvY(`n~WZJg*6?@ABzE&OJLq8 zA(DpY75uZnroF2?US^6PN!(skoD17uFt|ytV+%P9dDtyC@%s>tAV*y|jUM4=M%*JUbfo0vmLAifZTI zsU|{9Y=)3b1rj4N@_XA+H8L`j;FGw3Nb(ba*P?vZgg$82NO*vGemlJ06A*ko)ZKUt zzI-GFZ&Ik((frAlly8Wa=+>{35dzZ&HS%mhV=1-?R^mzU{!>U%`QYLq84;Ml*$q*k z66aU-l_E?GQ3AG|HXPfYN^vx-mV&|DbQPG?tu2Yu5TUz!51T=>b+hb2tP`LVLqg(8 zk+WEe10${=awNG-h_DnzS2a;2Jihpf_{!4hqmvpURSz}+#N6GE=!BKD)d|r$IfrVS zp6psC)?^4BT?9`~_DFkBtN!g9!FshLlE%r9{i{xf&=TQ2_Z{^Pp_ z@WsLmoGxml=aC$elMc>9^PmR3!C*!b1@==mw;0Gor0)DYbR2ZV62 z6k7&|84h_5GO`+4JQ?~>V^&gi0oqW^{^jO8cb2Hi0)#=asA#gMMrojP`*esvb!zT2cz(gS6o1lO$eXdM!qkOT(7xirM^TLmbD zK$AHXVPuc#cGo22-JIzSw8R5v%{a+ci?oSOc#y!&;wq^1jm)G$ZwYT7;ApC(0XG&V z$JxBfpojSjjuj?;jnuk$v_%}zMwL*oJrr$QggmX3G>bmhOC8jBC0}BFPOmTN{8lcZ zh~wH4rtoXgTfrTc%^{kn*|3WMaC>LUs`>V5UY%o-%H3(z4%GoNU99nL1`RzaU_u2h6{(u$DINA$FDdw> znBQlTFBl12Kr>pZ#Kg<1@(=NGsI~+b01}u=Njf{a*}*Gjc4W6SSJHfTNUxvX>%q^i zb8LJp^YiadI`}a}Ys}13i6_#3z~$2F=e1l`CAJ$vq_hF9#gmmmmeb?^rV=~>3}%bRSr#s;CKvCm=)MTIb5ZBm6cLYv+qx1 zG?Xj>Bk|6y*2ErZ;^RZF#g2|&M{gE7$@ghp#G&y$MlRSxJb`e?QlKvar`dD~&U4L@ z=80oz1Hv`OZr5NwOPvt|Q}XWIn~d?#Xd>fCw0?Blj$;B3o|qrfCxqBA;O<+(J+jJg0?>j>Iev`oC3t;cLaLzqNbmcMs@CCJzM z6y2eoUf#a`CaTXGY{9IkiC&-z@Ub9zUAU{mo&ezr(~qbHiE?zgK=2UaEx1+fk|ZAX zr0W|ryv{GGhaj3~dkRFHjJC)5Z8|;&F$m=XjnBm_X^v^RO)m+Ixt1j0M(Cza8JXKd zU5tofZ$`r|KwlVHr$cl0sZBvrDi6;(A-%7^m858*6(6XXJLqB2mxM|UcyxC!A5eqQ zhnw=>&5o80Dk?wh%~9^++tvhUnC8@0Y1(0LNu??zK}6sq!&B`CGd8$8`!Hv_IooubGoU_n zmm~VxWN}`D7;(bDy->~K6uxLOvOZ|Fsbw9@2{$&{5^gb=>kFOJO}9b#BCXqy%?TX*uE;eAf#QjY?|w88pzvdmGID#in>qy{wxYp}YYJFc;A-cU zqch9An&nckWHQK%jbDs_|cnY06+1FzPs1Nj>n>{8mtm z0!p9|qG^#opWlhejH4yI@b_=ex4YN%{rxSB9azZ<7dVv6F9?4!949hb-ItZ(>zr~G z>8blKZ3>DaNuQ7}KVc&Liw9-{I#WVbz89c2QNXuGj5K64z-}%9`YF)u0oHt6P3wt450sNP! zmD7dYybj49LwMQm{r-#nzp88r4GxGOQe~i6jXU(bcb?If5t%}0MojH)vKhJ|%3bK; zRFvq1PyU~L;z^QCMw(kHLhm4N?3?Syp1cG zfRGvxP2wBW2ej-d!gOVs!ib<(4x0`>D?NIy1l5W) z;6kX%^J<=Qu7GO*wmk0HRzbmm_SYbL6JL=K2KwA5;@e1yX3o)Eg4-N;4AIZ<}H&^xvsXQUL#)KOu z#RtPt#ce?`=V(O#fh8nyPKb3nQF76YQfY!^ULJQ5eR2^vE+|1{H#O+a=8Zv<7YKbN zSk6^P*-xS}%ilKT*mx3fFmOI@3x>$t#eGXO46+R%zh9}`y*q8c{R1{vgwX1iPsL9c);0Ikjtf49 z4RZw7m#kg2&59tli1A`${}#5jkt1WF2%xyMK2sexDOeKhJkBkT4{Gh=f=Y=gQN*F0Hx!t_Olo`RN5hsURGYsp14RUo^8 zncD)UZVqS3AX9iQNpdjA+EKZ?bW~^#IfgMg?fp+tIrwFJI7kTmUK7G1x95TtV{Lg# z2*6&Panv%!y-@Hp4Q+FAXgM|ODPa|^4vPKaBcTz?z~)mu2rBbH)%1V28(cZSmnuLu z>Mf>V0VR&wG_t2lBZHY06#;{+TjEY|79I&f9vuYbBf)T7-hg&96s8w?_KVe{~)tD2Hc@&V{$M}04h2*T-219qSO`quHR&J2HO zb*HruT`4Z@;03N7$8;AZT|i6f+rtTJAu$RX9~(D||f&yXtnc z+1~F6a#b>(-;p*VJt2*_q9^68B3iX%kS9@WG{hm`4xh|e2QD)lUeZ;Xt?AJgH18;3;TlS zO79TZuvpwr2Rmc!dQ}D5xdXyBL+#5Q%nkbOKHRk`xR*QNBMfjnYqOWME_<}WpcF|3 z?_0Y=`xcGnUt;QE*^hWc-Ig6PHJmi@1|m$?w0NIE;KcDUN#-EMi>W9KuWrgQSS zTUu!hNNWsRFO84)o9k%Z&zux}SgBut3ywHj?Xb4LyInP~krIZF=kCmow`&Gyn*fyn z3n1rGa_P(sq5;sLkYetcPZt)|WEMgaZi`gJjVME)Odu5XG}x#QzuzvaqNhU=3J`(-NL5)nyLryMygBj&w)0$S zJ!*G2qpFo-$Xfu!rL>zC24Re>T6E;wMZKLp zN@J*WDcn8@(svRyII_dBv@wj{_t%ahax@`wCG3{*xX(5i)n9HN;WF;bV@5mc}J`n^pZ;mqTDg*su`s(B|WK~ zU+OKECdYK#V_H*)k!51dF>YTNYj6;^UBDGyvmH8LKZ6h|4Jptf0e{h8882MJVyP^S zwsBYKJzh~9PID37+ir(5df#pbI2;8TCU=O&&{g-56rp<*wIj7LbQQw%QXu%iv2a45 z8+?H^rjlsqz6R7L6RUp!<~#!#gNI5QFrKX)H&LR%&BW8A@dM4ct(L_k})bE+dl?~MCq zw+fZ-uq}(Oj>ga~_w8oI%7IP{-No#c@u`cm2kMDFRM6wcOMPaGT1`v2Cmg_KR<~1x zb=*U!jo^e6SGnWHwmOO~zd6pF_@L(cpU*gh(R>M32hOb8zUltvbh81>RTofa_DwW~ zd7pNpth!U0-S7v@9fj@Fe9&N(wTpDC4xxLa8-NQ`#QU{fwweP@ff+^5QlA_F;&wm6 ziefejE!7*8!5I-@cMBOs3h9KJ-$i(~FHdlzY@fF;C!Nk2lMe(TC%rIhXQO>>qOrn6 z4KJre+oHE^ze6-uDCWSV`a~vi{BCwX#{rZwrQVSgY*%-7mF5sQOz9>e*Bga>&iFO^ zdOjG@kCcXf`$I{6((J4XZr?boaIlPMV<93fit?OU;i}sv@hR!p3Y)rfKkV?&NHsfr zVWFb9+#ipwR`^_6gW%`Na!1c?H&pF&;cQ95b3nuP)X(sb2 zlq$7@-R>ybtxgedzJx!$c394gA-+Q@WY)!2?;6Zp&_<4qT@r?k6j=L|Tg6MFXVz!d z-C9fCKqpa1%V^5f7;SCFx(c$z7-B4G5UxGFi-yL6!u~#t?=^LM#*>NOcMQW7q)_#d zcNI#DIkDRXQM~xw&#bjooQnm$Ua9dABdaM7-Rv4K7SdNw$l>hqY8PvY=40F=^^N}; zKw@33X)c=P3&)vaEy^=?v6ZHa6rQvpxRO}Mcb_g&i!>~fH;-aiXKrENonG}chZN^C zdW-h$YBdoxA4AA{#R=?u(Ch&x+cC-(VDIB?b4IS)tqXe~Er1$?%$c=_-eO8oru0O1 zc2C!s3^a@MLZDPKUcv4oPiT-wX3{^mYy1ul`-D~&MNYYE^bJh_>cUwa(OS2Q#Aud; zk$)nr-SKW|7ZG;PgLEh44EcZ)Ze2&df|+G1;i05$g@7AC^ad0MmL(> zlZ*iK^>(fBG_j zWC8yY&t&@sH2Dsqjr2mNqh$0B?U!5gAW3mxWcTR^)tW6 z_CQ87hSda8PGEZ?F{HS=Qyd~qasm;~oHbTO`pix{%%kM}qb`Q4#HHUwLDUTMdeY@I&o~>3?uQ)hg z>3CgqIx$5ClO?$U3Fid1@Ahzx(d&@44#yNH)?WF{35}+mz`}&S?|yf8jc{hdTM8~% z&b2+4=N_yr5}|>G5LYrHku}hMKJ0SS@sCbV@Eg~byZsJUI?-)#MSW&nzMb(rqA^TT zn45s@A(qR0#zkG4PiX^4-?4a`ozqEnqvcabnqge4&tAJ&jNY9B4hjUF6=7HKj9@h3 zG2dNa5)wKneR0$`(g+6H0$B$P+Fjj=+3j-xV!M9F{n+ ziQNfGBw(2Yx(UGe_q*z3a(ybrFoj?2YJxf#8}2gtJHlmJU#Ir-s85sJBAKp)Fxgo- zAN2}~rpVQ#N2hP;U0m>tbe^Z-bO`VIqKH-mNdASx%hTpmZPwTHoIRl>E;m@hzn>S+ zJ$8Rfwjd=0NpSz#C@tJ-3rI~V3LctfWaElC`W68G7x&T#kdwq=o#_+msk&W7*LS~; z9Z~d?-ndWGxiOvDmaub9jkXHy(xZLzwZLEQCjOvUdW#R>5yt|NcQ|%goAu>1577N>a@U3xdC^c9&v)F zB$)lv!a2OSxu*-73FW&7K4&cRi0}Ku`UcsTX>3k;01kdsTEhXF_ zJ8!gEN<*uu3oS&N^2{1q=|<{%PBEX)eV0n>;(N|1ttKeel$UIet6V8hZ_=Z$`J^vR z;pLr6y>oeLi@Rq*$IF#;!F7Y|yq+>UbGqC4%Q~;; zVwo)HUMzu!$V@-8p4v{F^p*@3fNlYc3zF{QdvZkBe{6#yM}1aXMOkVdI?LG$JhX00 zoY@V^WSjH|^3Dgtf)(IfXQ8m76WS^ve<$m6>@0#H)Ll*Jh2hty^XXoZyu!XM5c{3? z-U@~a0)P&KR^e~ETX=8-EQw?Ky<6&&izg+4lx()*vGrAHk7L>0M7L$6E|x*z>t5Uz z#)zTq_!!R90w@?n@5Q~CK#n%2*{oZfO<0_Zm!i?c-WbUMdw_d6(@ z@XJr55x|6IFHSCm1Ah5obOjO~Apfw=myrv|Xo>E(YpGQ(j*)ijI0n>4*2PJ?iElRm z6wDNR!}wqG#m-~_tenp>O5P;?EmO7W{LcAsuzJ%Clw3RdCxI9fF+7SehUKO@*trkO{uK&Q_}HZOsSE}Nrup_y_m^vnZ#)ivR?2g z>;t!1%ShLSVRGGc063y3C8zOOHwTaFmcv=Tpft^mvn%R$+7s2a>eFsqu7eq-TSl7e z2%D#rqWSmhe%(yKE|B>8=au8UI4{zcYC6e^is*lFT{fiHuwWkCl=FFEb548n$r##O zP^EU=FOG9HSV|YY!shAzJYt2}gw(H}&wp_puwObt_(Me1cfGW_$%C2p=$Ag7N%uy# zKg;#II4>zg^x(<;&mCVx)UL`bf(7y?36e79B+sbub~Hyq~(94a>A;Ok)0yBPk7lG z^4x^0Am*%xeK~`2q8_UrjJr&DbgyZDK~$A-MOoEO8^PQQ4x}-SHHkJt*s^}y9=G@J zhu!IK-!{+ubT-5yPaFWirsBHItTOLsy&2^?j$1fNEdJbW#my?s2zQQ&BK1!6aXhZ? zr3?Cczx~0R$UpT)15=0(FRe40-q!3RaM;6HMr)edKKl0yMx7gEWm6XeuTBWj+io*w zR)KC%DQTnn!R@psjSvv_OfqK7Mnj~z)4^R5wt=duz7ab~5jz;jLz#2AmrW@BA9e%{ z?I571z_BJzIvo(RQ&&SU$Ezh$_iyYS&T5V0V=&V(`4OucK7b6iEHs|=5KB~e!!p>o z`OIX{@{U$Pv}>+yzJI^U7{8QJz>bC6XE)!!U!-&jx|Zg8&99)i^JYE32mJxmgFH4` z&rYvk_IwK4DNUUux)j~3(|Vez&Bkae+^6PO_)RYuOr-oj&POdN-f8BHIDw&b0cmEv zOtYH^Fai%q2qqvdYHfFP8kbVubFxj7Az)(>P0`eL5_8%+oWsgUj7vbs&%5LOcE4Z0 zY+v7xv})bH2n*D)np}Ph;1h654UqJ6H-)I9mUBFX`8ZwDbE39Voi>|xP`TL(?wA2? zNA19LyO|Onb4c8X;N$Mr#oGU2e&NcV(L_uPlISRRx|xpF&wIE6@MGfz)`VoIo7n}R zN6wf^+WM4rx|bbTIvv5Tm&m}PxBNfMe@c5+Vy_Jqc-?NM4&H)HB}5mntGDfM^JC&V zwDy*?H9hEInEYo8%ir$t>Gb@1Jl*}RJ6bGy1QPqWW|Zd?jW533A7LOOb2}gYc{~2& zkK5s&GyYP2URS*l(S8yxjdphf4Pli)`}(>3daOCAR=o*_2)Ny%8pkuNgk~VrSrhQJ zBN0UJU__Zn_I~>M<@Mp~m*?&C>)~&E;W&w}qwm=a8mz`QC~32X-l?g~WS8_VzmDF3 zV)hA9F0^ceH`2f}sAr}8I=UxOc*!->N)!9|bl5&@4_m6@?sg|>F?ia&?Nxh{6^jXv z>RiNN!w@#%J(^#u{Mrm5p`F>7_7%%9EQ`nO;nEm#sCeKOr2eN`NDBEJ^P1XIggTMd zc2RO9^FT6PX?5xAn;6n&F|+(H`h%EDv6UslNMd!~6N~8T!SODB{q5TQIu)dTY$@GH1BF`nn?U*pxqCzhAOUreFTBBO5w z52VxPGhORtb#@0j*l$19FC4)ge{XhM{#9MK>vs zQ)X)Sva2r3dLzhnMv~4M?H=6L=SN_-zJ4j#9lw6L+n&B}w>TD=UldMo>epC|V}; zdV09$(zU)XmX7em!1;axs`vG#V9PZ>S-q)*SZ3V z8JwR{%tA30Op%8=m_a{`_L&g+(Vy(`bWayec&Hmjw1gu8j-B4e+xGCh+h4zJ^evWS z+IK^^{p0O;xPAHO{^Ohe7NYSKkJnEm)3|=u-_qBB{&Rzvr+>{rCL43Id8cFrBOh?H z)1Jjggq2=Uf2i+CjptI@p?|zRuaEyl{+aRQ&_DvduinMXE|m8pkN~*x_iH*n9j>aj zIxBh}lAnVcjBD?o-*&X1s7 zWS!PvTj=8a?kKf`eoNx#6WGzY&GF@Vz1gfc<~E?>a)`X3b)^4zben;G9z1gpgpYdc zwbSu<{eCpBG^NCZz^mJe$G7(%8$DS=B7s6w*JCo?>F3B^)pv%?YfRsZY8mvV8G*r~OP$ zpH?{@TaL%G8XxT(p*F&PDQ8U|tW>v58IxU6BTvoK@P=!auoRAGHR7 zjt4~tPwMV%eZ1apuT<+5%x0Kaa4?X&+iz!QJY6o)DD&RibFokLtbumJVo2HUA}xaK zZd^Jhh{PERfg9~M@rH+X3K|+HfRhlL+4`X_MG+aAEPlCbyz{fri z`80cigd!cdXg{%jIQowFdTqvhoeE!MDNyx}8IM7~@`i56huV-~BuUXNT&yOcwHGmCb1XGlDT{cl&6^gG<0&C$VM_maemcmpdC~`GJRkIF zU(!3B?i${1L0)u;ALE2k?I~KC6CT5PMdz1Cy9xp^|73WUDcyX29M>OP3}FT2mT#%o zn2_OmdwSlzkjZ)fu3vT4ALWqrg-$^0^;SzO;oV}CyutTczaw)On8GP`Ee`ML@3+d? zUMVE$Uy z;Y5uJY!L7Y*SQ@T9`u|s24JR|LNozcY@uiF^yC2Bq#+D#@5^bg;wJc^?7z_%0Gw|r zT{NxM%Ql(xM+tOk)!_B!n80`rUjlbO7WPV+Y8>gen86S$ElxSattJ@ykghF^w3Mw{ zPfunEMI4~S?_cNKZ9k$ zjE!axDrhRM;p7(xk1_4^c9>FV28v=_ZKo>gyTaFkD047pJ0WzK!5|RKe#If9s|=Jj zKaOJjM-~^~F7apF9C|HTxmNOkB$;xWaD3mqqa3J))ilsAC>y}SU7b}uNmJ0Q@IHu8 zefG9jMXAgKfDjKL;_f{^Y>vBQ=;E&LPX822?L?0h7J^pP!~#aikec(tW_>n`JY5V4 z!*EntfV!5Mk|+X+!2%J_a7)n8l!qa%C~;g)c!amE*T%Z06C`92Xaz3}_TP*sfR)&IU8kx2(K3=*`s5K%WnC;*eok%*qo#Bx27~!>-xrT{EML@jM@+ zqRMlviboA84X3lw0GiP?2aG;`xr_IFd1HF?=^=wVBW)pUi~ToNwp@k#R51J<(>ckdXK;TRCFfRiwZLrqy>num&drZmsSQd8mGWyfgvE# z*{}6cuIO!uonI}G7BMq;(FIh|+kWi7f2V1%iD?k!OyK800!kQ|*w9w*t67p$R4zSc z3&~^b4qhT1R7f4o4n{yTyx>A^Z#W8)(ylG+&Y+P0-chT05mA1?blu^dvp5w_19Eu7zTOc?q|+ zqbI?F!^B#K2b*Cft2sQR-duYlnqY(g5Xi-fbM6%2nUgxFTTD8gPRili5fItNprt5U z1fw|aS{g8GbJ&m(CB^vcw85g4u4sF)!y9ptJ991R10kOYB5ZF*59`;I{=?;{?3CxD zWq%<-F!T;?f>mt*=mD)DbFt6fYWCTJ^4lDsu#+vHV*8A5vCva=z7v14Tzb&(u|OA0 zT(nR&cFGsDJ0bv&O2f@O7Y8D0LaPF4+bBUx(F$s}EyiPliHJAR+k~uatZ6}A`$~EU zp>xivO&Vr1`@oNiSYv~7T1;^>;ejuw(WvhQ1W_5Ol|p?#S@peGPWu$amZ8-~`wAh2 zq$1#mC3${AmMQZ_W-0>;~5|Gy0hUC!#izZB&leP`=uskLVjxnQb2M=~;>0*SLTu{;ubXc=*t=wxQ}Tu@DuC-& zD;f+=h74jIH!uHi#QjgTE?pAmN@#XM)EGa7Ow4TckNaokz39o9QrbBdwO3eucF1!H zqr%Mb^|yyN@>&3YNE_+Pr3)U^H*O;wvE@wU3@|I4G|(B*$?@DfEvZR_#6p?o1=3PK zX*nIEgy+3YvxTx;L7Y2r&AQOC?|Yk*z&oGf#<>uJ-!EFK(>E5wZ8?=4v44Hs-5U+P zgu84(d-`fS>ub@XR4GBAQHYq$H*L>KIRy?2u@vWlx7(iFS)!UpmXBX|H2+bVQ^7WU%w16Ur1pVUzSW>-)OOr&ahUUC`>$ ziL=f7-BE{!sNuq&1h-LYMIDZ(?-s?-%)gJB?rhA|QMykNg@r+2btbkWgrFGP<&n_w zzJ%=r(>5MYFh0$eh^Ba!)k*k`Xp#1k*lr^DFAN%6Hd6x3s^^2MZz)_q0i< zyCN@`FoF|3g7^l%05Po`Z)WJ{Zko#t|wkSe^O)oM> zNzU;A?)MM-_u~^$VSNMG1&LhK@3lbHR;g0$ZKkAd7h**`youP9+^xO|TZGDCN)nue zAwjOUKb9PYF%X};9d;kP{q}LIeJ>;vop{Skmc$D5ooPnf9}S82d2885X^3>^eLNI@ z^8LFvo_n$qW9%%+OS_oE-UN5~Hj|KqGxb{6ftE{C9HL;_TDv_1JlZGSUTp*IZBvN9 zBIxQ4vEK&T3*>kt>4eaA5sGOvM=L;$pdq0|O30|9M8on40emguyF($U&YzE_&3xtJ%mrI~^J1B6>P*#$+ zYze_7y%=2?DhYjTrzIkVyp86=f1(Pg{VK@Hu+?I}5)c+f8$48N0Y&wJFkzMURji z4mqYMyo8ye8H_+uwhSicw;dbq-DE6tAdG}9T1F!%d{>VV=PN>7bAoi`X);4ZpV1;Q z__#+Kz0C1?pf674&cs{9?J8FhhO7S3a)CwR;Y$i z$z-mc_4@<>Ga1GcW8AIRW*GCylt|sIuy$;Cm#gPA9j8W07Df&cX{1Ug%Gb*kK|ZX} zQs-Butb9#PBaH3U6xe4IQW{d!%ig=cJ-pSXe@V=V@Z!gV#8$39U8&Q@y_du|G7+Mi z01RqKw8`(t;o#}G*}Fgd9?#xt2rh^t9u9F$>vD?(M!o@#NjZgfB?(s-9A8pYoX5HOC-R=)xxVrLuxcP({s)R5eL)#u6xBJ(p%DV7h zXG2OG{UR}Pvq(dFhtlQB!9({)WHmx_^ve(aJE{Cy?lK#%kQUB-AeB;SALZN1uc)2v zQ(;m~gLx4MPf;vLv+ZM4xud*WxedvO3Go5H(DBivc$okpA&lTH1rch;vShgi#6HUv zv+pg9=7uD{jz3Piv8;918B03plaX;%GR%n=omy!rnL{|;iExgCOw!fRwH8c&MG-8QK_;J zgbFu00{5eLyoNM!Ba#zXfc^+QZf{?|8ObvmkS_#i+1qVy-yUkad_?jBmE+HdyIMsK zxH)9^5HC9Wv6yHrQ8`_GqKrJd9Gc!*e7%Bb#~&d-G_7++6Cye}j8-QJ9UNXcLX~yO zvk@FqX?Q5p|9X6WuxEsU7pF_q*x7h{BoRMc}a?vHZ-Rf6!k-|jYYZ@uDU%F;y| z;p>&fQ0md+AwW<8&6X-wFZg)4f@@NME=6`%JKjl;$z-#Tly;J*rl-ImuK;bj@S=Bi z6}*hAA*ltS?Q{iJ&8PUis4pRB-sk2hL9w39l#Z#_ob|z(V)T9NjxH;t-wS5VbjHY? zoDnrC2SA@r!t9bAnh4!UQ7yx8H7GL96O#FR<0f z<@z&re24~)M}ooX!lK3T|70$PM`(;eRnDm$_>$JvGeQLAqm5)56TYE5+u2)B+nV+s zi;M?(S6ywi_ZR{ithFlJO9_J>T0Q_A50$wetv%~iCB4aL3ILT-gCM6hgiXH2`xz1pbNh1#e#r<77Li5{tRoge zY%-4YfLV_DN=V!|zV}h?lBb|bfze_5huJV5$b@(j+;QxdLYHW)HdoKc|3QpjU2V3* zWCo@n!+FKQ6l-asSt9fp$=rhfbry#13Lje-u&MXwq-2~F{5X7$P8Fq7APPZHizn{^ zgW52gKoOW@JXA;ax{96gE}&{B!~qK_DT+l)N$|1>g%MM?FW#Qx6HRJsIwo>n-Tcbj zJO>_?5*d+Qbv$gNo0H%a#%==kULL$3&7qtQXs$wwZ!Zu~OGpGYeN!P08B>co+B7f0#V_; zqOTEiOF<*J1+#hoq(_L0v+BI^LL5{`@l){_E5aqcpiAu(;HY%cng z)Va4J#17EM7+)-#PVmP>V-lr}my56pl_K7{+dJz{%P}aT2=ap8+*LlU9@&y&5#p2u z66^4?Ihtn!g@BR78-MQRcFySL2~CJM-~6++>X0tLK+K$lg>x1kktw~xY2X5oq1=aB zcYwI2Wnlpx@y|9l&nfvr_w=@nF9ytuQf6R&l6kox`~(t4B-#Z=7-y`zQ6q3Xk<#=^ zERK8tttQ9K)v|m~PQB_WB;Gb!kX#hZ-+z6yzEKsRCRYeR=W4Lbv0((y2QYa~Mm1UX zDJh;XSvGGW#P$Uwgt*BBRs0qcPu5%w8v(heso=WKd3f+Mal|Mnb5C(+Upq7)+!jDL z1!i7PohLnV1yao^o5_nr4fBw%;rH~2BX%LV-K~*3c&Oxm!B|&nLW;U9OHG{G=J6HV&|_NHui}OiMlki6MnL1$1WnNrg1!dm+*!2~)1TF|p?T$pT2uMZE=%7f-5GAlyStK6$kX42=7EzEL=ph#5#ci!*rPv6wgLHSZXDdIX@ZDw_j ze+1s!DLJBv_d9})`fAPvbVXv12ZgQ=IL;Gw6{0G_&CQz79S$W%PFmg@n>Dhi=Rhif zLZijP)kbnbA__zp2o1V`%F>n`TGE??dRir*WUIPB9T6llwMb^v*y1~{>%KFXixG%x zP%_S&kz;2jfLJ7eidmuMWBE8w=xKmvsnqzjxf&A!K$bfY-s=BkzoyG$N@Ba5AGa+2}1exNM8Q%BhpC=_>Uz_DU;8Ex%#B@7)fsd zNF7WIBagKo`!`QW zDpc=xWp0j2NJePCa%e^bEavc(iVH_V0o8astZxrW1T0AL0u&d}bchd`p)J58Vnh^b zOTuqjZAtkh05|8ON!1ns19S5wUhRao0jx|Re$2=L$Msn^UK@u!j$+_2)3tz;O+9u2 zifY~`2|O0~9f;?%ZUvD(xZQ#aFDq=0BVsfe<~V|q$X`oULUTZuuEZ<4;gF;Q`gb-c zxEx@xW`qx`RsW`Dp7wP^#E%OKU~a^#z8q1mCCM&tFi4U{&-{{*A8~W1Z6$d9wA;Vx zn@uH;E|SPtjCj?;$!4f4|V~E^ef!f*=ChL)?nzxBW?iui7>M zK$C$sc5hegQ8NGxV5$~_7DJZWtFcRAf1~@1XGY-=yy<5zNgz;m^ z$I?K|t2VV%As{wC- zj@VY91vp`bydo@~g}RJ$p$V}@LZ(Q3rY_1eK*ZD#;GLk#W0?_5*PsE}K%;%dPn4&82Z`voR@ zy;s5g60>lc3#q||vv(KYW=LYSvdzpMpi3rQQoSnhZ>F_o0zvTr-VVe!k%XgV{9tI% z3FJ~h=xtJYwz)c^l6wknSnyaELPL>+X*G{&i})9iL-RHWrhqJ(80R# z@SzFL`EcmfC$l@!5pjt;k*L=G2_%iFv*YS98iWL7b+wtpbV4OJb$*z~kL`8g+-5SP z#)P>J?_ek-4o z^AleU0}5Gv@!uO*L6ROteE^t61gN)qsOae|%oR>(E(y?QaO$gGTHfJ}E zwC~K&$i?Es;hhZEJfW8ti1^d`ZhbiHR2?WILTt{Zrf11U%>Y&<25ECtZN)awgdXGz!>1VaaOy>$CzDAH*Gf60+Dp z=4<&@8r4@j)O-zAhUO?iywnysAvFtH(#LR4aSSJeZ(#{_Otk>UVTC*s;||Zs+e>27 zXoD!rser;ZET%Ayc~TaE>q2nKtEPDCBfME)0?D!f0-UiqrkunZHF93>JvyIC>u$cz za-3w@f&cY8P%l1a<(%p@FS9{~A8nkOmIo84irv;J=3L{^_?ln{LRmZqM;K+S6N)-# z@Tz&G>V{^7E__V+kWN;`d&df&2)?9xyxMa^vsaU(opSDrITxQ@&v_04nS{BkxF`gc z8Tp83Bhadm8;MR4&T>HgWc9Uuw&Wj#WmewX&zhFRFtZNfqVgm6OJctUEGQmRfxGiMVX`A+%Ji_n&3X5 z69m$u^i_~JL}Pv?Ck)2A7jgDlijV!A;UTa#4n*j5u*H1Y=W; zW84Ql>JL*bb|iW2i8voc0>KpVB=il%b?HMoQOOvyEpk9FQto`W<|G_;x6kX!o=%}P zUgUU*k|1zpv(|0k`&GI?T8ga|zE=l=@9|1T1ftdVYHj&mD*A?EzT!anl*LnBrXS2?n1>7!h*sSyJxUQ`;eD{4= zK^b{d*P+sUOnapKX0sJLuZS2}am@GdGR#)g&J;S%hFJNY$Y4rslH1w1Nb$*nxjsWK z0Ynj!k5Vpu{duzT!P1`r(gap~ZU@;PxOntd#W140MSegua5@(*Lr#)^p4n2U`+Q12 zYgNXn@=aWyWEpNb8Kbg>U(>xnq`X;aWxf&z(l@Zrda~DW_5q1!qOha9mK@(#=OycWiv;7Pdp$Q zQUvVI9Nyfk#+vgztfy3U0V#+xM~x>Kbk<-#L@hmVgxhnBa$mF;7O@<)-MV(vCJ>LY zm5`t!3f!>Fx=q+fiv(Bt>o4nyG%2pk<}ny#K=BZO<$cWbPsCM2L=_?-%BXTZTyqs|bJ?zpb!VO zdO>CBaXsDQk- z*^A9lusIq?MGBS+hOZQoF11xZnd>S0&Z!a-$xa6bi7QlwHrLNHveyD!@}@#;3QUK3D{bCd^#eU$|~h@N?1^rboe+y9`rzUZK0vnT!DU~1(z#hDZ@zGegv0H zO_dPZvDr@)pKs(V@Kv-o9GD94RzXqVm>-Q&C`=`-ba!}#)&wTkJN10x2&@y~ zq<`8hr#WTmbLr(>Rq7hCfIXT3332GlCxP6UkRczeNXgmuTO9L*81y;Q{~{S-)V})t-;wryptQN&wn6 zD?DEjGDX2Vs8rMV5@OOYtpvdz+cz*G$pI8&*|nG)-gV53;ZJRv>wd3 z-Pgo3z$JPddDz*B7Pl8A&mjI3pcnJ8IrJz=z>g*V0rUy1>n zg_mGzPRn&~5XcLejj;q=1duH(Z0sv8>Enw&cBQ=?T(l)khB1IbETg8qX;nfUG0W%8 z563L6@)~ImKLv0abx~MyXR7n~A-NR-=xhY9hie0e%Ud?R=$^16wZIWRBS_k)U_A)R ztMaj&f2AgPNl(i;P-TgxKi$RQbOu5yjcy47&V9Q5c#bf@d`}JtG8B(BLU+WH1GzvQ zAkorxE~se9mjqRirc(*RLy#CH9(iIy@(@xOS<`^f)33gQh!$%*oOPKweO58$q3jk6 zT@V#!W8(WG>>Vt$)HPM=Bn1JngrF2#Tuw;j)~k|H`C&SP%M(V*)5DQwH>H;wufPgY zS8_?d5R(~0eAAWlr52s@}wk|27k8L_Y!OqA2dU-heNtOs225uV&I$?v9c&8 z3PBK}tyo*Iozd?J6^iT#siqn`Sd&DwqjnJVcjR@Bo+u z27T-d2bG`^W90Z`3FWydg^41~c|d%sVJsFPX1OvTG4wftmK3CkJd%v`(!@a}?s6_-OZEH`S}o53dS=0L?AR%d z&BXxy*wDT#@lg`6I70&hTWbSj2u?e`PPh+xNY>vG)g zwl796al<`q!vP^LNbp{uX7nw2|Ho`$+wIN`Z|`^DvLs;$Wn zK-$m)$4l4s+m$;V`Ug;-1J)zbRG&=qGZM{EQlLVi(YmNZvmUJgh*nZZ{(O=(0tWP{ zX^KD-j_GZOb6&(GZC;A|z=FmBw$YU;lEx3FB=G4GRD>r8+eUMUkV^YfxEm%};01b; z=?;&J?t4D1-%n4(?>M$oemoK+?+q; z_ZiVm4=$l9{Bie-wJqfb#AQ&~dTdHM%MS$3N={m&^Y(QY$zOhu1Bj!qV0i`}jJ+v8 zz_XODX(u`Wol%8Z4=6V7FWIJtyT=O~5q3zduJVAAj&3}lkd6$f<&%~cxS~6M@*9vK zJbOfqyD+r*Jy8Jv+)uS2A%?UVO2Mj3N03;RvCe%+0)Tw+Irbp2%n#tVSwgVGOTJ!u zNt|DT2u^W-gxIASjm)eN@gRNQj>Rv`!yui5j~}8;4pW?qS5CWh>4f$Y_$Y1Xq%WpO zfG|%^P0$CG>{rN4^Lql*U>}0$zH(|?k8J|=ig>A|Y!}6Cez2e)DIt+a=!d{*c}e9_ zF@|Xhkp($p$+(BwtN0n_0z$hq%osKtO}*DijzVWb3b)kRS54wt(q|kR#|mC-rnAH4 z_fi!b%r(9L^h(X9kUc=aC)5O;-fBh?4DyL!wQ=7@s|~ACRXG-7n4xp5*M+_1|O8VM_T`Mk&o(qCY(EOtkn2RoB=FC7==j#Tx zA9UHpPP{s(T{a&LamJV{Oz!Z5U(64nDJ8jJ!p}Mgl=WD0VhvQCLh*mDActR0p=3pC zIEI}Lhj>mkJ{TL%ydo;WdT`v36d-9B7+#$*iLPo~>3Py0(BNd%`|EoAzkmJFAN~ae z;!@87ju178P$xeWc77?P&Fn)z2jGR-=SX%rUl3r9<{;DDf$X+r$V#y!$PupwuOh%z zMm6|o2DF3HW z%mv058;RDxtZGO|o0rOGh|^+U$Z?g4)jwEL`3=?Y0t4;+f`NtsG#V_VJy=+SD~)f; zNM=!UA?;4yo_~1fE83+?(w=kS2q=|SqY;Gu0j35DTt7&=5VSj{DGOoQ`lixW(h}WI zsAcX=nf7Q1BL{?n+M{=8;WbKfMxU=GfTlUtuq4LMCEBOjnC%Jp#yZv6l<4%@e)wsCbe~ zSrFKM*P90sET#It(ov1FjxLULG$!gQwOJ3leN>&raHu_(ZZOq-8uzn+awyIPwV_^1 zpZp}9O<*;zaH&!zr^22*i8>m5c;C6|_P%Z#vzkO!0F;%%naD9sA(n)Ki$qC4l$pd% z)+2OqUmTD1nf{>ll%svIor%W)PRt-BaRDMJBYS8?*$)r-IKiNeu{2 zpYt?Dp3rcz-1SoCq>m+(_8E-wVSDQRU+ZHsmW~vkUgJ~%_?MwUL-wy z`fN$2H5efLtnpCh#7)4CBGjSYsY5%n9szPX0TDF{F`U?z$mv8(+#;AHdOTW2(BvHk z{FUVPIynmY0_6BmUef^q&iU9>+EB+1e67kqA_W< zqJ|*s1qnBpAHZk|KG%_QeC*yJk1=t3og?qN?vb->xE?tBI9w1s&C1Z@ z_pl8CRw+!lx&_8BCZvgm*l=<=ghZG)pTGVJ41xdeBY~ye$d9L}vnk0pvBoZ&$Xo!I zI5qd=R`+)Y*j(Z<>w9Bh&~O?K&%5{YI-1)e^=Q3hnxNEu(n_ky71TOWCQz=;we=Wt z3Vx`=>Lb=9&_N)}OY>^)@e4T1fSN&(q44nR=P>d5dE}>)eon+O#Iu=L%?xUO3qc)9 z7(oBs{?eNhiyyOI(#xxeq}SeqU@Lx%guk~R(u>^jBUamx_n?|V!kpr4by`K~h>INz zfH5vH>W?sv%HUiT1ju0-r%HK&bT5Yy50tnlrENGZ<*V4x6ZeoD2=seypq-3wuA#hm zI>pJBAmX##Z{8!qVMN}a9<-SzhM#$-DZ~hH&0m@aeF6#e!-PqbmXb5T za{4j=P+agO2t3vIkK9-UCBL9CC_PT(*m*@Mo2g~vjquRHi3`L^ig8GnTDT{7lirO0 zj>>ueWaSjU5LyvLnH`aqLog4~YnNb$h+#ct&9Tm$xcU^jP=@8=G3|bop6)S4BST~t z#`Ce;GvJ02rb}Udy6grsD2PM>kNQ2zu|Hhd^dY|x=1H=u_{_*Hta z^Jk{y*O+)iHb4bR2&>a@Y1p}#l2*h1xpeGdyBAhLpajq&bb7TE#I!Knhr@MklXkos z%wS-ea1ZKTu-Xpwq%R$%0L7PgwTZl(TBsCyeDHEohTmnNlffJ=6HGhrEEfUh%1-2# z;NvsUb&kDEj$}v*loDTM5%~EK+mlMYp3C!$Fj#*5`h`Y0U%!Aws^ZM@LwaArHsOP8 zmjgsxG3t{@1DkSq)sb!)Q!uGvvkD0cevdr?{NGVj1%|5fmt|mDZ+UQp>2$#+Dy3$; zBc+rybyf&GgPkULMUuoZyODGEW|ez%OVXWDufU6gvh2Mc3Utzi3D0uSUVuN0si{|x zx*Gr_&?1y?6>mn;_(L2e0%0*Cs$Ij7xkzRcAc$czI(&>)bkI6WCqCq+H1fL`J<7=o ztSEON*&#XlF80loW_+|3pmnL>HrZ@<2WoVm#CX!BP23sVa5RRoGo%$oge#nxwg*U; z3SOizn)a_&i5ZOq!YGGIhCK7`aC)Z`-9Kx|sHiGtum?Y0LINrW8P$ah${ zmr)vdkC-+-35;6V(w({a@Xy=vAAj8P=g)A+Rp)`+80U?Wa5?LQJH3gecM9fWA0;8F zq|1IDPp0bwfif@^g$F6K+M*a|WAKp+;v9DmKX&`GI9s_fu^ng)oG};%`imJUfK2Li zN1T#YS)lEJnV^XKI0xbfc6zrNYM-P;xxKGrQ9v6y*s}mzqvWGKQX(g`aDmwZR3)+0 z3x~`Mn{ESO36NV#vkXAQB8|ET7m!yp2cdGz9o=p=(|ndM2}dO2MV&{| zFd%w*<$zF(S=l0!Xi`YeN{W0+VQZs4+>LIrq&u9{`hMQkTMXc~T|&cB>Vx=Zq=Eo2 z2vAJ9S}jAP_6N@qN+LN~`XIE~qBMa^rN_7N&03@eE(~2~$gFwuq(NliYC&`;<~!bz zBN4In-Fc5(0Pt!gPv|f4_Hd;msQdy8M>x$~lB0d0wUQvRJjW@hj@@-^#V-i@&oU{y zQv*{tCmxGwKzC**(@ruPG0cszA@&HK*uN+RXCU?_KPmCHoSkvGG@cqbheVme1r{fMycb za-LV4nQI0Ok2Wn)`n?}Nj^EdTVxUoylA@t+Itb=cEX2DI=N5aC#CmzwW4TDDE(pg6 zDv9INMKeMSOMIEAdN8`$EPNV1W~2`TEV-x%Gjd)?6oI~hk)~l=rwLE940O5j=Vik6 ziGTzEZAW!9BBMggXxm{$>G4WT?~e!+5Bz;V}w2 z=%6Ca847;#D0iO2W;&!03pZ@r?rdt&k&H6yE&d- z59`ORGLdM10CV+yk~o zDhIL7X|QXcf8}Z#FCREQOp#=f!}h(l$zkr8;c`L}#T!r;{L5S6%a)e0R;J`72`EDw z_x21HO_~f_phDh*FtSfkQ5CGbwz*z@0d2YP%oq=^#i}4Q3XB%Z9m{Ut0h_|zSIgxL zNPr85Y3AiNBZm$R1hkRN^w&5E0oJDWN+}JCA)awDye@JV_C{!SU^;MSN}DFp^GdN# zI-$DWIdol2Gmz}?M-iGvt8co9F=}u|j=iN+FY!JQ@UXN=aWmKHHOT=H7^1O`2kf@z zjB+Y?#&l31X%V)eE5X$<2$&er7ZgD|G-KPOY4wW}10A2^QwkAW!|%#d1$dm3Qxpwz z4B0)Ms({6XE(55@Vnh1_XMaJK7uq5*3pynMGAQq<(NP{)9LOdu*N4hN0?QyxoEsON z@{HE@(k#5PRwUG|Ev$^%Ibm)^>U9b}k;bIf7b;`$AG?=lI>Ee3|79h~NWn|_jq+gQ zfH>R-cyCgxS{8>IVwarkC3GZ^Jcz^iosPP(gi?>oVc7vO?U%b<;pqj>iBZw5g=<&} zA{Z-w`(PlJfkJ(YNAQFKC8we+ z{KA!X>yt?Woc>7^7nPzT7U}G*0m8+NiTJUO^ENLE7;QL0wIVcNEEa`;4so89Xz9EvZehuc^GyI$|6chluEbn;7dRsYw| z{l9Meef=BEKK`+NEFP`z z{ucxmxALFx+y3GH>DSM<$sd2lpZxhp^vUD)G$&_pc)ypW`Ke!A%E!0l5?*e18}r%g z+bx_R^p3AS-M`+ke!G|5sru~j`u=wN!eo^nneW}5&DYQCH}|~q_wvEVVf#pzBU!#; zSbk%ae^Tjk@_R=8#_b__r}AgqCLXnXfJwB(DJRrT=IpTNBKa`p`Szk((_mRS>7c~ z4Be;Uw>c5Zx=o*-^YKThVMV9#_#^Fwu}3-7`Xd)HBk3w7|l=kE9`*V zx$Mf~->haDL?RcDV{oid3c3bGjrl^y&r8KxPkpHKWsNUI+e?Kif?X*2R79fc_PoN zeRx&-klj`PB_HZv%2v%qL{)c`tr~y8Rq7YJV|>l-XfN4`2s2mwM`WS;gqewN!bkQl zeBf`xf1Q9B?$<}~EVuz{W}dr+FWijEF0dcPzu?u9_354}oyR}l*(CPv?k4<%Pu+tW zuKx4=&Rv6DR@?N&XVs>6ALvc*K2V!p{&uG}@&5|P*8N$E%JQ#65R>kca6IHvbv)!x ze(29XX`kEm-7%b1_ve1MmZu(Hev&_Bv6WsZJ}TeA{jFZX{aw9*{OMl6|09fF{*vLB z1C|ep@yb7q9C9C&a!CFvhyN#T@oBvVZ>a)1PnDjt3F%|A^kL{IGnx z;uH0L#V6Gp`VZVYhJS{)^nc5H()PJ{zWhZ)NcERggsDH>#8+3AGvq%i=E(nHW~un7 zoG1TxHB*11KcD}ECgjiEGv@G4Y}KO}L+&Hdxc(nuQp&&NRn{lg;FZsjf0@Tap;{&)CFm+tuG!-v)D`%m=i`cKpgyARyL z`uwu!`=Rz+w>E4STF8254U^y zqx?6L5K>n93m<>NF2zHT)!u9-x%pFct^V4Zy#2%B&$sRU?tyM04PTG<+h*La?t~yocoae6UI72gldQkf{qanquj7eVD!Zx=rME$N1JNkfD*cNy}&q;4;j#y)iZ~INZ6ukV_bsCwb1J7ajlcDK-En+b18Fo z%-;Z9DDhp9YVFalM0ZJ)j4mz0YxTzrbK7W1$*$dT`6st}j44rWFDV^`ZFlLHHEC>Y zw(f_!Yi*%w+mimOrRkZ*rtaGdhrpy8x$U(zJ(KI8Pe(4kC_#6#3din_V`-k_aHOGq zdQ8b6TJ4sq54o}r{TmRT2DuuJIpd5B&!0wTH$10tvxbctp6O}MXy{fOHEDX5-0XYI zxTa?ocQ3(R%9xU3{5|sFV;YoRIn**+-OHT{?cVEMA2TnCwk2cw2iPh!_pcb7k5E_# zV~3Yi=q_z|l!B$=Z){6@_m~pA!K7rge-FyBE1ePjIy7q<6d9JFxXqgKx$z$yo0(y; zVHfgAuvt^HTSWoQn&QM97RbFW2vCu+lkTDdg0d+fD%rxql07^wo|pv1g(=iG?4iE# zs42iTSppQn6c!Zb@R+UmF=S9&*BTUCnnUBuF8?Nn);NIDT|Dol$DENo)FzL($s=+T z?-99C!-h?pHqFRr)}(PmY3h57WgR{ovj$8bH2ag1W`D1(zT~}?T^_k_*Sajb$4j5J zjakQ6uVRsHRhyV~oF)G>7=VAkyA0Pl?w{*X7RHh_w>+kn)u8{7;W+~bDMK0hJe<<6 zrB$mX_Zu`^^&57oW!0^us=T544H>BnYEfu2hCG2;982R|xe3Z9)I4`VgD|nrF3bUfgwb>7dd5Mr5={%b1KjoL%#a zyU_PtV@d~>W%M3020#DJ=utKnUlkNLZrJFY;x?rtMvTQB$N1vjZHjxAmJT0N+@%LL z8=cvp@i`5eG;GwQN%56KMizI(gJRqk6w{frf8z#tH*!|S3CK^-H+Tbv47bEUt6lTr zHxF*yP&{C4|6zSf>EHFi$ZdMIjO|k7 zv;P6-%ljU!kU?sOsTqwJb9MjXWFxK|@q6k1EWP5TglIqD{}{)-7)i!#FbcCT_$n2* zYWSNZ%}3#zl2K*Waqa(e>Xm24o=bpzW31TY|5N_bSZfg0Fa4?0yGHrp!*${oeU?{_ zaaq8hg|e-xY%9l}fj+fI*2SW^7}r^)*Nn;Ngh%SdjT#nTfS)#u9Z-VJ1`QiDZrrdT z%Hpy8N0$}%$E_ery4deOYJ8tD4F+4aV(G=%FE4y3yX!sY##i)SeCVp$R=r40ufY{M zUFwj}x_1qDdD2harvBBU!^5kVR{O2?@FPpqaJ6t;%{h&m7d3hMl{!6M-qPXp+OK3r zN>6^jhG%30hsYe?fAf|J?{~fMk7@&cZk|){{ui}3MRN?@*d1B+hOTFy+vf6P{z^M* z&v}(MK6p*-jYsBEdwTJKKQ^8>vE6qEF8utQJ#YSTO6~vFiM~wbg>!$*%lwzdA3O8x zw=UiFQJMYN;QQv*d^OVwy_23%sdCi}%PK#ymSxSRjeb?|@oAc6rI+8*GG@hI&rGZN zMyeCf*O8X#<0kU)D*32^)$jV)4j(sW;YNMnHGH2#ckR<-mD8zj9R!|38)sC-M>7mM z`PExmTIp%8X2u3*#cJN`88;?n2hl8Q@Y3NZjv^9p#=b_1v z{S7)4^bQ*NO=EmKc#>u1c!ECZ8L9EmxI1awrZe%e>txG1k;ld6BisfI!fkspo*vZ* zqvp}5+s?wrs5+K)0*y+KJ&94DctV--DA-*z?8~$9@#-mNl1(u3H_u3O@@eGVH1dUW z@bM>(%vxR%M%Kus$>?7((*_uL4-LHMTzoV<-5ppdIT>}m1I?H;^j;d;?Z5aq=ov~e zFSIG z%;Zt=Ld1KB#+@@0A5XP3cl_G%Sj}$cICU(&6r+~VsG?c;7~V?lOYJeFIBq=VNyecO zOKC)%+4%SxBXZ?J!BK+Z4CXi$rmZ)IEu&%aoA5EMwI|RG<`@$OiCRvh*3H4k6>ZEt zuO5QkWezmwj0Uctfph2LZuz;iKhjY*@A8L}%zK1?GA--?e{+L=ee1{nDckL+JT zU=NI2N#mN{fsgGS%zd4>eC`=%=1LDaHx(*PURGx+#0VOgy@GLEAYv6^)g7Ip5! zPj{!LRmRndResa)mbD`r8@D`*k5QN54si^nv_}GX3 z@xGLnRkI=7yAP4+(uO)ON9Q-GbDih$F|-)_quaSjBINTqbyNVn3`s=`p-6Y;BA)9Uo;Lw7g)d%6;Q!NSi?#~{S9aDzY9FhBp$rK)v_&Y*E) zBZE2^{#It6A*EN29SE1lOP5ux%Z>hL8~y)dRkgm=wvHE=&dz}GLTzkjj5`LVZ?vi7 z1&s`211mj&Gne~gK|DGbQ94qeH))?r=f!(IvfG@23+!XDr>69lJD}>?2VGx9*Q!=u z9koeABWMPcpI?W+CMd&V0LZG=qLw|nw(8!7C#pwRtS@-siRy*USqb_|g}x^MsFj#( z{HbQu^KCsb!Mm#Lduy_94WHJkRyUnsqqB?zk3&LVYg@+)%a!5!lD%mtlRtqI{D~IK2et_Y}(I&UFt;Gx*N8phOM@hUPM>q$(v@m&eY}kC?%^NvUnS^(re=sl-gaMHdWvD==%;M zIIS_1;M-T)%`a(;q&`iGi6N<;MpEXUaRO{NDh8dq8w`%I(vLpHa=!?jQAy76R5;zq z@j7XbCV^_0xj#hb7}%Qhi*abp0>VL>f{E=Xg0X2c%~&q%YSrJ6fOat1@@Js#f~oIu^c3=if;8!52h0 zmf|rh{u$jNcz|zBu0lt6t9&~A?9HImr`JiI^5~FMS^7_}=L6ZzR5PYs@)J0zYF(_e zX>2k+8Mcwy)~bzZY=G!n3&-L-+o&lm;Y=h}%^FI(l>99LA0#ir*%^PTS|dz9=9&;N zwiS4zL>IjEu@An7=3SA`C+RR1_w3oF2fl)6)AYI5J<9dA#n^2y6Kc2V3~%k!OyDN~dM2vE)K&*F!_Xv+(xz5z%u^Sg z)=oDW(#3^hmobtPR!APpPD7Xd8R#<}58_fLZJ>PCp(c%{{{Z?{vx@6n(|>Tk(aGgq)oQJU znroPZbkQa{KC4r04cIQwHgo!pw$e)ik5hg0;-w?ix112(F2cX)l!p_#@WP*}RtN3h zyf&%=(-qp(*gT=uwbGmT9M&ry)$1Y1K?KLHXt*+uTBn25&2{ht9Q>993ym%k)5iqw zW_|P_h)DmBeYerRO?Z_MHla<8&8xIit@P_dqG)^+{epyhkkGE?n1 zbPcX{;_B8h;D798<>e^;|NB!^uROiZqVl4Q^1rR3CN&1uKD}zC+$!ZOD5ILiwJY_m zZXH{cHnMI}OccfH_png*uZS8 zb6qr^L6(M1rnkc1bfJ&tFHmcvo|W?1+yvfUtm`~gclnelnN4O)nNr=#IQ7)V=-J76 zu`Y^pUaf1P&(Wu>pE2d9>UdBEu${@>N!-aETxb2{DwVAA8>zh$8&sU0>G>GlvrO&JeA|giq(>mqFSsMKHO2gW=zhe zHjCS2_PwYh{>pr;8S>p&*Ar1`+Q^z-|37G|oR85x(~Dx~Aj~Uuy)v?s>|WtGTLa=` z1+mN0>?-GDG{tG*g<2H*FD4JPiel$6q(>@1(zN7)AX+XCK$?~5PPYPfKBH8ji()N% zruB^F(@Lq`p{Lao-=ZEq{O?!l1x2woG=~=e&`zw>x9f_x>WVk(iZ_xg^+M-u&r1D} z)O4aTytLevx{F%7KrEY!;B9wZ=MBG=x|?b5384K?D;06DQZbrVYFC7Ludef!v0T;S zd5^<<^nVJ2(G;c|!hBHIc~kBKl7?D5A8?$#0df9m@klusO>uhg5~+tLP~QDWFA*7= zmxvTCmx$!7mPk)yiSWGi;w3_xN4i9;dPTAFC0Mj59za3U&UGN^P_MmcS5LI5=N{6^ zm!gByrXF_f49=il6Rc&+Ze4FZmF07A)N$I?!!`?$9VzLI&Ta5Sy%lw8-mxAs!*Q}Gr(e^cC`G}1sg7LRXSNq@GezsnBwzaV zkkdMI#+3CQzO6DP-#dtJ+sq_i*%1k^H~DtRq)=nwiF2mvk>>nLW>G9r6uXpiO(4%# zGuyivURD$$r6*Y#0^==c{mH*?7>;<>6}(xm8eh4nla_O z>R|m{b!SQzPM)+-re!#ju$^2$H(>i#YM+z=WLR)uRDKdhcW&rTS!a1vpOHnmG)+zs zRU?U_-)F&5^Q0)ML)2V|nv*4FXNj3g5q{c6YNeu6NYNavNM335B2~_8DTq`#Go>I> z@$;Cz0NSSwo2V~xn6UGMBk@>yI{O&9?qg9s5QNtlRU?V&2M^G4DQm$7)gkIZh+32-7G#P0m7*(Q zf?8ub7HLK1bS#j9cslNvf{f`{%$fIxGtQiI@W4M=5(x)f_OSsOF_nTtmDil!x?8z)kvA&3=c>ckBX2m zHmHuwpGW4;Wr=69#M3JCxiES6>*sXl&NE06bHO|I(>ir~7ag4@W#9`l90}ZukJe*5 zqodl>H?Wpl;GVTmHIkP5-~kfuUokhioDb57noG9B-*j%VPVbx<{uj#uFU z>A%3~V}t6@@ga1)pC#VS61$X?Eiifa@b|S8=Urn?b{(0PJ*?$5xMwX?jihBKJV3%W zmVgbaL(8Yo@^O~bN#fr1W2<$G|s-4ahRoc(fEW>_;b?1Ndju9}}g4;0G3L{IzM zEbr0cpr()<$cMczH3sK%Y~uork8*s^4`*MIvx8Y6_g!_XF?}|nCn#+x(0H z?+)ZOWWfn8@|n@!K8$LRvntuXYp5n{&QaNF4OPx2X~&|K8BsM7qtoF5j!s0ujHnJq z$AVFfY*8&cc`NfD*{`lF>Y?xgsv))U8meso%0N&1xD-IOH6U{hxjvXrHTX;2$1=%R zZGS#lusO$RKDC%nHd>hvRU`3f1P|bokAnG79en-+KBr}iQ?kX$3Q=R(wTUdwMBznr znz4p53`A$4r(G}Gdo<3_h#Yqyuc1?nHFUBMqo(96!=KUFusQWKqq@wf8CsbURU1$pD)8rX0c=iO^T}sE7owHtUhn`u7olK2R0p3k!KZPyXsGz~mi;c4#U&`b zd>TU!-4fA3=xl?}rRZrl&Gw$i&enV!cOWmIh7vLX3cr3&p4k%Q{cL|?m%-*V)x^$X zV#R1>VpNSpY#=;YN>IV z%gOce?`aJq=Pmtd4TsG+U(-5|X^lWD)1qo5TI1jWw5~$Iw5SeR7l2lWY|%~u8!!7^ zD~kyzyudmb>#MT?>^k(cJEa`MJ8NK$JCN5`yCYp+6UlpLe`43e=5*4;E@Waipp}VH zH4?Ge@Bm`dP%ts7gIISE>#A_wBslSj}%b(V*usJ<7tsYG4HncJ=sz#!<5FSA5ZWK(5>Y#N6XccFRgaWom_Ip4U52Ek_ zD>l|wKLgle^tAh?9N+tCV2(SG*H_|5*VjYjy`Mj^C9pYtHL*TSY$;lq7*!(?dkh{x z>|qp4jOrjZ2*gSht~IjLsu6U#^dTzrLO%=R^Hz zt%J=OqG=6gT2G;sX;C#2t+(L;v|dBOw5SeRlR>LITU?(luFDqJDs1n-YLCx09;%mX z?auY?8l#8m*SP@cDekq{PCitBBkZC26c)7`L0A-3BZ>M99w6!i)`AVHL)0vYnvpH0 zXN##y(LR`<)_80-d4`$%s+=S&YY@|GXDV{knny^7#mba z=653V+q1>3*Kr?_)v_WTrgj?A8);#Qmv`Z_R%Z%HO+ zyWbbgV`;x26icIOBx&iDSlXXSX;g=_`H*&Bwzwx-+@*9?h6$RDNx4t!GAHF8DT^oN zE-A~Hlm(pmQEY?&NH<|M|8DY|bnCe7lJm^+YQ(qG}{Yec%CTE6u>MQ&8lf{)Nynx=2+W3BbhXJTRdfIQL0NSAenajlW!AH;6efSI@ zUpxHyl)&b^rTO5mhe6grv@##6M&dIX9^hyw3g$y~@Yw@CA7qR7vc+zNXpHPyCX2Bs zyof%4q~tC8#|EOS(bL|W?cI|;)`%Q;Ag`hKBxh!{+lSFL}_G(5SF{ANl zWkytu#ArG^fYA*om=V>%=qoV#B3tZJfNqriX2@bD3NN59q&8kdUmJjCp{IQy1<=uY~LH^Jr{(0ukYpE+n{K2(jw=U#XKpW9I|AF6}TPvG-Iw)jr* zxli`HUl#LGc=`MQJ;?=h$l$X8J?&po_OU~nkK+#H1@xVSOn}1A^T}sE3(5N-e`1SZ zbAHjper941pp}VHH4?Fv@Bm^-F@z(>XJe%8R|9M-h{W?GM*L?Aubt%lM1NYlU~^8;w2o(5yV1(Ds2Yh@ zF8;0+Xq|?FX;B@t5}`SQ8^bL5Vau+rb2a483HPUazsgv=$|9{<%m8x;&KJ11^U>-a_rVF z7@NQhGQgA=VEP+i`e`tI^ycNEjQE~e(P@d$&aet}WQ(RVl1Rd zU}y!oPYteNUEL9cbx}2vt|9OMU42;&HmD9=GoWj3j+m1pX6J~RO4LwTv7bm$g(PaO zzo>d-MCI_}F6 z_vDDXa>SiE;&vrvDmvH;Q}*fmv>N9gFi$?-xl7IwKi;`huh-kYdjDpuI)xl#qcr48k59NplbHpMA<8D~N%9z)s znuNJnACe$=u|8-l&_$AjF|jLH$USh(LZ})^$Z~jqkOiDSHmD9EPeRDr9I+-xtj-au za>PodWd%BTwXD@zoHa-^`G{z>A!d~!W@QC2>sZXg@XTVU8cEF4@Bj^~Spznx4lx@b zW_^x$Hb*!);wh!XffYiHSy^u=dDc+kXeD$eIV|_Krz+@pfpt6szpR6*k#uZ^2c*A& z)5iwYq2pEPcqK<{%n>gs5wF7J74eD|VJ@wWz8YStpkWJZ*aEk#fvS--?1l%VzKv7I z2GybA9cb8*Bev&=Z8>7AlJPFA-c_~3U&eMV!`Wsms;w1->|`PD!7&S=Y9t|F!2|OD zi1Wt=)gj~)2-%w>_T-2Ua>RQ%Vz<(=A06z^a_lDV(&EdRy;_d52e~E>eIH0YeCT^m zANqDnIsfX=_buW%pH(>Y$rgR+`;>VcL}%tf)kr-4f(Kyu2?Zbes16?AfX9Ix@l}ra zB1h~~F#d)Wtc;!PfF@zC&#xp1KJb&Gp`TRMSG7qmg}bN~=gEG^KpUKvy8{5)PP8I$Na4Z=>{;H9|Va=BD0v z$QC`TH5o=LbY>V-jRd0$Jb*!a6g;a`2aFQ|>0oFZ`%+JQ*U=NWYEdA!D8?x@G< z`E)OqPvTUI;DA%5YNS+);Q^`kD z=^tDRciQN8YK?RCL%2!kX*bHnrJNMnm=Xr)d*w((qmk21+el#|I> z<6OY0_|R<%Y)+$GBqhHYZ^(?MqLmp@H4>xS-~ni6qTuPIIvAY?MlEth^IXv^S2R_a zZkN69kj0%SyqH=Tm|7W_=AozEGS_=0)ylx+4rENt4NT2)`AG`jMK<+8b{9Er<&W%c z*qoLc+4+p@9<(wtszyS#1Rj8F0SZP&bs)O{$U5YTb_&)~*>9OFmZR{(>L7LUgSXBG ztQF{KcS>1Poi!|T=W%`T)k!-aJ`a!sc|+d@f`@kD!(LP&E=C2Ohv@4GQK% zb?~_ue0t@I9=W2MLiCL6`m8LTL*Yf#%RrPc5Uoc~`_h#4l<-I7`d~yojOEnL2iNoD zH{p+K18mNv8rLO^>jktjE~-Yt^$|P(*G?3Si|W9218_~u6%%sB_*`*~BDPod{#X{D zpzso#2vu}lKnJSH2C+}k)1H*;z2u#&i8<~--UBB{?2K%@f$SO|WS^1a$^OXp!RAcT z$jTYn=V)bQRE>n}M|c3TuTd~Essq_gKsGB^%*Ykf6|bLU*Pmta3kolgT_22VhJkCk53XOy?_7Uezrp6*tZ~g@T)(50aZxoAuH*2cDB!A! zf^ktDxb6q8dvnFzxnf?fxI+=EEqfm?ixW_IiQNlT$rZNHAa){p+6!{M*WL>?F~=Rq zE9`EGosrEmklo>f>?Cr$&>z{!usI7fviXdx4q6!*RU;wGg$E$}4+=&`bs$>-WXp2J zl3cM^@v>#t`m)GF;pMeVO63*yh`}o#J?)h#ydKfK%oXPPU|dTKT#J2h#mVm@{PVpv@$NLM#9w`9)PP63dTis;BtWLsa)}7u2`EZ)+l1<%HAzx@m~~PVoyO; za)mu-5IYY&?PpVt`p;=%jysT7*pm`FBU@`ATjPW5d~*DpKeCpvInQcj&oHu9Xk}zn zjfCtXcmT5YC>R;lf$S9^+n6g}$`vmtUPZENS6OsJ;pMeaO63){#o*N)J?&Rhcx}Ogh_o+EvdEB5A!J&M=0vg-s{ zT!+HT>k}Zr_c}AIDH-vPS^Tw$&c#b4!B(w zccAbx`@vXahYV(SqNn{!uJ=pALzd$}xDpzz|0*|buy zASHl+7?BtWd7iGVfWbrZzFSi=tmOQl8Hn?p> zPy0CA`zWop=H|EqdD&Hy@CjV!%A>Hx|~ipblt(>t=*iNZ_dBx5C=W)Rthp7yCJL{8I0%!8Nf!vkbDjX%vF$h)vP zr)nUlFp&4q%0Q?Z3CQR003aWsU?5ZnkQ@NXvPFhs@`dd8r7XTe;boF#tdjZ$ll|yv z4$$?#bv2gpHve<)wW=GYoaE<^bStqg^#k)Rxc2SE8A1w)}apa?)I zP(*%}oqm(W?->$dfI2C5NW81n5)F~;aMer()fn{K>mWwIYR?!z(D>+ zD+8fwBq05(FpvZa210cJxe!1)+M>NJ+S;PEA~OJ1yOk{;V4g(}Fgt2_PJ4Hy&~KdD zx{Tsz#Ey2_B&ASyqM(szYKqBwlZe>uhnYEymg6Y9;X%bnr^N z-jH~mA@N$R#Tln1UagybBvx33lUV2$L}j5=jU;pzJV4(z)`tzML+A_$ooarFT? zo9%y=_z*T{mOe|&WJY_?%8aNQiP3&|0Gdxx@L7WDV01ee-D-=u3eW-B?`v6ngTf2w zR(Fc&N`0OI=v(x(?@R$SPXjXdaMuU(nd`&nAo-f-&*y)zId^J4cQBvt(8_$M8i~(e z@BltPqhLN%2cHMPXQ3_T+u}Zj=x^Eeuq^Nn@DxM~At`xL{*ZwvhMx9f+j|gvNF#FG zfxL$1Yc9@xdRwg_{PRhc{g6K+`iHih#hTHB%qShL%!sOy7}bUcFsg=v8BraK9s#3= zZLwSdI$riWK^7;X@UEeUr5?W9TWtV32|evcQvj{jfXp@I`rtLR+=tJ}98m!3;kIvX@4#~sMa=xL3{Stk$F{PpS+x?L@)hU9pIKe9%!InQfk z>ls;Nv@$ZPMnZNzJOJ6*C>R;lfouzqZMMZGTfD4zwUk|3$)Yt1FR#r~60fSQ2Cug0 zX}_MrYpdpEt}53Duc}Q3u9tmqwI{z@{c&}G&3RqpdW~^)L@VQ>Y9w5};Q_e1pkQ27 z2d?*kYqu?S+Tv|nyrqa;EPG!fi%U^>iS34}d~jkrl({e4vrN&&V!EDr;uW^v;58CG?XOaJ?bp1_73TWj751rt>ti2WrQ~qwZqUg)6Om=|9%X{eo~L8H z%znm{Nf|+Z!$IDdOlDE^wi^~j)kvb;7ssq%El@{wh?)seH|B|Hd18uE^f)P+WKPG8 zT9G*&)1)Atjww=*F&(ow^R>y$sTwKsm*4>jJDe~!sE*99|>D&(m>}%>JLJ<4zW}5kYu5s2WMsc6fl6S6K@-s18y0L)5)_ z;_f^#Pbqo}Ca5*`j(fEtb2{#pf_OUSNkPVR%;(H^z!_&w)kv9t1P@4f7blDjsw49y z$b500cpy(KRGIIE$-7@K)|opGAVtgteK-qs>J|SoDE_&Zl$VMuWi21WJ!_$ABrRXV z10?KY3D}@Iw5)`d6?tNr67mh&y+T%KA?6e;J2D-Qu#Ruxopn$(l8)ct0qK9w>0^WH z(D4LxJf0^W%M*_(DZj(y-MJsvQk=((IeGNRv^>dL{(yVdLe)rGs^YJqLP87$pA4xE zEzdy9(|KZ@5^^-!y+WSWLd-c?cVs%AWgW-BJL{loBpr3&0Xk}N`q-d4bi525FXo92 zd1AeiLNB%P?%^+LDb5CCPSzipmW{0CRJdm?RE?x17aky?E=#}$)uCkzv~123o0Je6 z?Oq|9wGeYoHXWIc*H}k=cxN3{jijRqJRto7P9GaohmIZ4u{}?0%M)9blrv@5vt&W9 zxba?>ZkMydKLgyEr@uWt8$IoJ^1MfjotlE<4&=k$HjTmAitW@Fy)+|dJM%!U;@70- zz~;P@r@khAn;A7nD>I^MBu4Gv0chx*J-q)>9gOyX(Fb|rJq4(}?AJjS9Z`4zeIT{X zuwKltKQ;hefS&f=6hI$qK;|-WeefCWJs&<7lCO{b`E-KK*{k_{#C$rVmHALL5}zyJ z0epI+U_Mj_pYOouV4nCUPaIH)`pB-vD{;Jt4nk7$Uhqc)5xq6X{vpqMbo)^wa@>Ku zhQ5)Unb83sM*L!(AN?88i*lSFG^6jCQ3+a^5mh5Ga$kls433zQ`!bwA!05L;aYz9g zgAQO>CX0%1!ud^V<2CfR0qANBu>VQ{^tT3Nt|8Y4^Eu?hhhK#Aw?7|#5zb$l&!5ak zy$FY@k@&bTxVa(8hw4~EN9W^39QmShzNnO+yxW^0+0aXHK#JaQ<6T2l^7R_3p0AHX zv(eM8mhU|pSI^fsita#OLzUqKH;T-t61G#1L-fKMyL!Iwafn`f<5bI6$Dw2LDbbtJ z%4>+Kkr>?r4{&rF3SL802cr|fsCK@nr2x4v%`x7I;{{Y(YU4F@vH^%*n`57p0_bE7 z$Xr9N59U+LhtC4?b+SL7g|Im%X+9@1A9^7U^Py@aJ}cn?d>%rOxQQAe3$J;kVyp<$F(L*_w~z4&()Nx`a%C!mrp}pBa;k4Er$Pf4y(PykNWoR8ahc1> z_3`g%@r!i|{b|u_ahw88E6%j&g*d#vs2YjZHh94L+KhtN7u7-QEYNC_FB&OeZ_0k| zn{wz~I9^~)jP=#b0JZ}??X&Z}C%I-CnBxxQ_0{M|*B8Bo$8P3NjNZHBoUMs9Wn%Qg z941E9NW?yY2N3%J1rwt>h@A&wEflU#Wv9<%u@8k8R|{i(wK8yhj-GbQ6kM$|E^~dk zKK}js`huLd@~8DBY)(r}>wKp56<`$S&YD;!CiW*SYN#jT*siN-75uGZ;i`bU#^dT zzrL!G^WOfns>9~=(zJRqtr}=$T2zfhD-Rw3sU8YmUsMOJk)Sm^UkuF`gY(5eg)JXe zyCmOysIIj;L)|sT57k|O{7@a+$%pEpzsxFSQH2P?qNo~4R5N&hsD`Ws8&rp=t0Af^ zUyRNdqm-g^V1ioXv0<53WX|SjDTrp%86^c7j}5Qk%$vg*XHL~fnRkE(Bzztxj18(I z^GV43hI}zGUrfjs<5ltS+)(N3l z8dW1nOTYsZ(L1AfrBNNyW@ko20zU=@y;2b2Cy*KFhsHr(W?| zu;L4%Z)YvT;hwcnHIkNV-~kdwu>@>T9a`>&mU;Q&4kct9+Py;NX(8qm+;L<&?qMC{ z;hl9*HIj~L@PPCua{AbyI&?e$9Sift{Cshrk}@48?`m48r8x7AIl1r1v^>aKZiIW* zLe)rG?tlkKn8OmVL3L=kpwF z&U($~Ip(t-t;~n2k@#$Z2k?0j1)n9T4nAAJXLG*TlrLUZh+dOjUzf#J6kbG|At`yw zzSThV2721B;~v3WLt8Z>#~sLPXp`j3j9&I(MDOpixB4@B6E^2{&FD2|v>mO?h^mno z?STg{+J%A{Q5}rl0izxHV!HxFujE3%y|VZig%{8csg2jrZUfLK=xOgt0km5KGS`sn zgZXUt;qxi^+U?KhGuWJ6n$J$=vk$GzhpLhId=C%MeEi@mod6G5Uo}uLEvkdo&!F{VzW81N zJ5lyKNfsxg@B;hMSYN*y!01J5_Mw#h?^g}XaR>7H`u<4Q*D2)vSASxs!sZ;(#C~C7 zr=gXJQ8f~=`tSf^nJAbT)j{lU5c^Z%%9EY)Wf4c=#r3DLzG89x48H(9Z7c3Qp2y{uK=Dt@;}uXuB;xO%34m}#l^vr#n?ty1^}tr8SWi|U}&KHgrm zjf>WC(K0U1i;EWVro&34md2#y5 zE&T-#rv;i{rC-5)=l3#MLgvFOZeh^mpO(3_{= z=vov^h3cTv4OEKaqDx$Kii-;r5_%&Qh)Euuh)0p;VXlZS5(hDHI!PSF#JNE7ASmwN z@9EA$rok}_p=u-{^ui_xxf2Bop*n;VLr5YnE{TiYanVx=SqQ6rMatYJDrn)q-gAjD zwY~M!_WZ}GO??O7Vgz-rs4%s%MNjSJOynVSW+GILMC5UJ01dufomxh9+T7>vRc%4?9zh!_H($!dRTMS;zr6W+7CKB%~7lIxmFK%bi#V)gk0A z2)Q#ZZjXyw<6>@H%u!m>(ZRkaZl7yT?44SUb31ZPPVB8x4^Qk|J+X77oPRa3RT0m* zr^3X_7Co_dGmoRunR!q(5|5MN0X%A=U>;Nlj|ahHQCuvDi~Hl^UIn8LtYBqK>>^FV zoY(~t1W)Y!#>Cz$Nf;Bmn1!4I$1H@Zk%Z*K1BBG&{INlG2w4LmtK(u-T&#?X6>+gF zE|w@carCj*#_a~KqKoJZxmqi7Rw3Qw+^&?8cy3qdxm~6=mq>B{YML7$w6nItG|Lt} z&5tvkGtimoP&E>r^WXtc&P2h}Om)zC9(10Ii)Z5E>9|-I7f&cO{1T=$E|+e^y@JP#vlMj#Ph*i(lg6r?~hbF1}MaKYi%FJ4mvXrsz%~LFAD;O z=TY#~Q5`%g7ql0Z3Ph|x9FB{>6pUA41uNsSpi%*y1^GVOoWNKCohRgP2M-$u(!V4L z;{7{05@t9z{ParIZgv`+<`ROImRGR72BA9R-JtAxrdw`R{&@g zpR{}gn^UVmJ!v_X8SOj;EUKgMQfdTM$z{~kpi~1r?XwEJ_f1VT zCC44e%jgV=nlXt2etgBxYYKdj)g;GF{gE9Dn{$>%b|xdMg;qvJ)kw(d!2_1c$tV~Z z)q$)fkeyc`S`>)pidTm0nkkDc6kcBENvXW5+8DgD(bI07!mEwuWv(jM2jgmC;A-xJ zD~J5H@yC@5o6}n3YQ?y0v@$NLM#A-9cmS?5Q7|s516Nnzx~M>OE)W+Mh>nWbd9wHU zvS^9IOY9=3O0KXT2C-J?X?HL1-oW+H#2j}ZudvP%J0rW$K-SR*S!;6K!yj22*qrVf zSvN-37Ojkos*#X&g9jkH00kqXI*?rsWS13)OAExsidT2pwTCQvqVV#%OiJYy*4NVDZKh>UgipOeK4*|4O|!d;Ob3&`}*U$7&fPm#&rebx&*C^i>i@u4TJ~ax*P@L zqB?Mm0Ip#LVn~4)R3J(eF?uZ+dJmSx5ENcw!=Ng;!bTayhM}ijTHt-8H%b$8+=0Bp zhDhv;Y>))g zQKop&i@MNtrYvTm@bVfbrSb}!Xz-eip7wPGcp3rX}r3K#0 z@MQ)jcOdV2izI7Cw!lDkzYntK$?-COWE)^}mTF{67}*PGWn@&1gzOD?fO`2tG;B~E z$kqVa>H@KPkU_&uO~Dw^Wg6KU|g#VTq}KW z?I6ET_~UvTHfOEI^*G~t2d#{Ys*!Mg1`nV_Z%gA9Ms?tN8Mt075E}}_`U3H6fp8SG zeR9C(viJgp7ut&umRw}77|^~%PkU2=_W{}~8k*w{%gdM`)j@Cv2yQPB+X}?i0`Z!{_nYkfyDa`d z;l;OID(5w~)4=y9dfM-#;M=M3nQPAV!SuEn#I_pSuldmXi(>5br$;YFbKcSP-e!7- z(aQ9w8i^jgXAJbJp+1MxkQ21qIA8ROk8H#$@7*!)d$(B(5lY~NbK=~3-K37C?WT#wN z*eJX!>2qTx9WaR0M^Afy3Xubvh`EwnA08liH2#1;5PB<`vtI-Gih1s z-~p?IUXRABgz5nDBY=EgApWPAG?o46m1F4M4274;_r@yu#b9y{dfGo1c%LNxqM11E zKwc&P^I0X$$-yuFP|k(T`B_8xiJ`PWD?_1bBq;QfGN`0?r!f?&1InL(^1C9^L3X0o zlcDbgD7-{|H&)4EgUE&GY5!e-C$93+>2kWfJZung2YQx9CmM9vpF(HYoWC`NznB8O z?TjfA`yji?ZoKPrg7m8Yi$p>{qV6~4el$!dIrjrWQ<3{I% zLU|COFWPHk+x?Y~{OJQdcCDoweO`jfk6q>Klujw6r08v9td6RY)Qy7&IHEU#u{x?l zT_)7kD-{1J6sIX^<6(kqDXl+AtEZ)zJN1902$JWVrnlX%GqO1IYvGJDr)s3kZ-fVA zemy6Q4XPvaLS!B<6nTZhE)+Q``5CZ!=OwO_ck+-W9o%VNY&`{fUUGD!&%7AFy^^yd zSmSKOWQ|mfr15@ufV4YU8aAj7jb}k)lS0v`P@JIz&W8!&joE3U1)8(dNY99KhTe8( zrzvN?0M0mbsz%EENq9iQt2kk7P#u|{hs;|Pispr)naX^f?D~`}o<`w4g0w)A$un=O zLj7#pK~KA7p?68P(xM%AARkkkYo$&zy{*o|&ycfLg#cCY+4i%rIV}s-v+eVl(Q{~J zMpTW&Xfr$j%?l`a-=jJhT>wTM3Pn2w=vCQoi!5G4;RVz|>fuYe&IX{@(bMjf0;sbF zWUdO=2k*1(eE4i7U!DE=yaAijN%Ogo`D{Zg^Py@aKJUW=`0PNze5ejS7lTi)LeZm8 zbW?~vkX=8N#U2!1M7xrP!3qL0wizO>N0<0Ld9#~sLPsE6j_bko~v4ecdo34cZ( z!{%J78C}ARK0zxpqG}{Y2jKyXzC^){s18O~f>GZ>afJf(KiTg)S$vPe3#hNu!)vI- z0Q4hz+5-x4$dN~ufppw2F#x#(dEs2)1LbFOP~s2e7ucKu8cKhLatN&qg{qOD9DOuH zu~0A+ssqYZfKpm0Mih!+g<^<8bByd=O%~Nrc+r$XRdVf=8E9&vr#+_7dsZnk&?E=a zS!IOFm;ScxutN2l-XXf#=e#1nX2o%*6Q;N}g)8$1c|2^+7!7hXgFFGP43esmKxV)L zLf1jTAgK$&-VBI06^dDf zVn(5ut~fTAz0Z|J3lv_CH$iN2HQs7)JP$qXTT(dQsyRBzfwUTDX=2U{4RX3}_F0X_ zRZj97;no!NR)3srU~_KKIOj6XwrFLXRE>nQD?9*aM-+^c>cDv)aNbiW?kW^_Dwf@3 z*Y2|Dfx^r39#=1|$pr?>Ug&AhPhq)0vozOa(g&@{yEMu>j}+yl6mx+;$^>lAe2wyc zMtK=p86{Q!0cH7P7XH*Mu3f2jb?exowExyAiq$HL9ZLjjfnJXU-o20zMG5yl2LB#Z z!YNA3m@>1z(=CD5RuZ^arNSALj<=fNm zeQ7S7VmUEa{L6`9O*zd5QifTC)M^EKR`UT6!;Lx4mGC&LenXNX7k9m8gQ$D1Yrz7+ zOk#e@AID5O9GTu`>ZXE=@|pEJ%el+vf%Q$7GHox_hDbrBQ54H#a>ytOxq_ltoX8b` zTt3JRPl%xjF*u2>uqf65mQr3$79YEskB0V9SWdDrb{3sv^U>&(Ca~!YrO&KpS0(ru za|RzamS7KRNyg!TwVv)4vC9v}_R{)tloD7gxp!2pKV!RCA-4vJ!pd!{!>_W8(IB{BCNx6iek-( z<~d;25H!an#MKE=mZaIdDAod&2`0_!k;`?UDH~myXmlnp&8sENiBkK2oiYiHjTNC8 z+MRI;LQt<+xg2`lKMXZ^W4BzNVKu*&aGeis@K6+M32w+UADIxhHgc_-UE4A_8Wn-u z1x2xrMD7CcX##SSlFTkFigiZY)FiXkV>>m!5qV4lGiq!-7R=C?k49$_=zO2yOr^bB z(cvQzA7<5Y)5>W!Jz+J6k9?G*=OQ_%6$V<(r;y+xmP4BnlH^<}2T3`z zNKS&~&}IZVmlwr~NzUa+{T#@do0M~feH$w&Uq*X4ouK9-XLk?p%$GfBjnRzLQXl*F zgi{q~woUcjGux))aXh>&0kgbXr}G^;_H%BBk16VCdKaaCrCM)z$k6;&DCOn>e0ZrB zqu?|IJ2PGt-KtD&X#YC1S($DG9EYY4xI0N~Xi;o;+h@}bfP*VKWMX_k$2Cww2W~=0( zY`pUj1TLyBd#L?f?ik75&T`so>NQ(Uny%&b&}wq+hF0^35sw=u;E0C6`S41+%tY#A zsXj%q>lp;PM*&ej33H2U?Q#?ZgzJ!g5uiMg5RWIsV@W9GlV#Vb+|_={g!2sYdm3{tLB^vh#df(=K9s5}?QzSG+;Xp?@HV`JP1A`QA zWLAmi2M)@VgR9W5ZOQNWhK3I$V{fuHZvfN)-Y6X z@ZY3^Ev|zaX;so*%j{D$iq_ni9%ZGY`wik{TQ%Lvem&Dd#@mdpZw7VU&Ru6@CDWRg zW%X$_dQj&fV*p33^ilW$bSyRnw$7#f`wd4RWjdNwPlBm^>F5#t%uy1^4KP7ZNxu=s zsN<4)Zc&lvghZYl?0#mb`}>spyF=X1gDpVV9l?=r3yr*3MP7t{K}Z(_yT3ow{iDkL z$`JP}U<(koEI9I#(8%jlU1bA6sAxNO5zh`*)Q4w?f>%8R}z?^6`F%k9T1UNO4!F`_Gj7k3-yl6zby} zKvI9|AFa;c9{|-y(D2($#Q3cH*C~B#cY6Qov22^Z%6m;M_vtOO-nz7imFa_+TI1JBLk!OTNo*wLeYN-2p%Khyj?r()HK-k>i$a6v?FHn*1 z3yFMBu=~40-7iz_9}02*AZ!7`76nD-OQ%)J{lg*dmxuaTr+lmp@v#QBfD~7Ux_?f& zcS77h73yP?^6^q|8ZQL7h{c|VDPV2K(q4hl=M1zN%^_!??JA`=g5$m(7WXaxxI4n* zex%}lfQ|t(@*Ye9yZLUI0#WRR(FeuHXbwTKU#0X#aNK=iaS!;%{W?7E&noT@=oo50|G0<3sxnN0qN>5@Gl|v1;~uZ# z)(Ufeg1_??7^kB{8Pgk6>0c-A2w z{>0LXVN7LJo{a|~IOPphNe@CVWBq%QE`co|>HaVUB;60DiVwWpjQhYCrs#5I_fa$q z#vn!4C`D!H6{Ki1YyoMHf+;ZVkuZj(JzUui~}tXDXW!`YPOD@=0`o3VmNl=zCxbnCQD;s*sg@(srkcoRXD0*S9OXky&zeE`%{? zE?20em!ek?uZLg@$m~HC**~*I%3dKeOxHRUer-tjHLwLRTMbh{W~)?W|IAh@yI*E6 zsLa-*Ul5pQVGGF2fhi!fr$QrdQITH>iM%n`{Y#1IL3BL!n0Inav6u|X871=+t-O64evsl_^Fb3@<->Re!pjXgh_zJdw%)U^O{WIIA z>=iP@Uh=yNe<&pU&#(nB`w^yq%)VEV{WJTYvRB9~mi7mXLCh-WCa*x!a)X&!umxoH zw~Fka*`LZ@Au}+mslrza34b(f0nDldWky$g$HEvS{3I3m_>joQ1-nP~^^}j(LwuYH zTR`@8g5Af`GGGkKzP^f_6B0Qq*gdjusC)?Y3&^k_$VDuc50ktEs4%m!v_>$dCSMjy zYm8=N$4q_xd%jAk1v&<#)EuUO#n=p{u&a`$%I=eLOBj7pZiVKMlrK~%cRihMI02>rRO4X^o5E|9 z-6!QqF#4oC8O7ChU*&Z#ItHM;8>WDi z=fM<)@(yM9NqGT`J}ECmb4bb$tCW|aV?bU@R9t_Qim76qK)C~^fRwkx6ozt}viqd`E{r}YzlY|Kls{7`e}aw`@{+fddsW;Nl(?nb zqijY_@|H4|whu<1oIXc$NKQYioPI#Z0F2+kR3Tk?uXzxrz`OHrU<_k?K-mpF$s5sM zVD!;*2+bjS((UAhWXujs`Y?P1CjFO6DrExPyXQZY-6!eF2s=xEo!ky6yF;aPYjE7TVR7&Dk2^0s?t?1sLUat6i1{!DOvHUK1?<$Z zw8b#`pm+$)At+X2A*YciJh zJd8f5HlR5K)oUu{&FC1A*CrL$e_wf7*?sbQ9Y&wLwxT&CulH46yU{TKr)liALYl&?vvM7F#6=RAI%|omF6Wc_=e|s zI(m+xLtzWRJQ$`5a$4~rZXiqn-&^Cs)io+|SxDs3!R|+ex}U7v-w@({B5VP|CIm+w z9~ya1qi!2IPy)Qk>{((_l88iJJ|iaQ1?rf`^6#d zAAl`D*utR5e2Mmma=#+P{jyLWPbwdehxm95wty5L4R!yla{qLQ`*oo{HYy)4hWOY3 zTR@8IL*2io+;0wXzbVwm+seoG;54=cxroKK!W3{^iKV>*qt9V*Cz?YJgCD7sJ_wHc zURd0{{&7DJkNdrfdk`H1X5<@~0uHeUU1B^Z>enfK!ia%9KzXiuV6c+a{|G0mL z$2}%Lc_yloABdtdOaUk=!4!z18jL}g$nuYy9UeEX;?@syUf}P%Fx+`l<-7?x28e1D7WZubxXr@jp0DDz2y@=j z-+8NW=be=Ej_4R5s(o18&i-+`gvafv;&uyj-pk*4?{Md(%K30_NAEQuYypA?!{oa( zW3hoS1?;7CO{gN5g+v}5?0!_J`^n1v4I%C)!WJNGLU82qp^;~)$Tx;Wo)+wWN~rtW zmHS&l+}{jafUui_BJ-uwJ<9#O5chY4`glA8VA4 zM}yONB*;Z9_ApEVYde`Ug>;A~ zuOQocJ9^Grtziog+!7|=S&YTbgDLEhQ43`^9?f**uLojj9brse@X4PncUMUlp_ie~ zlXMr@0y68QBKtoyxW}8;d?9h{^5Hndxh|^v@2i?0y9KqHW0mn zzzl#bU^cIWDS%mDm?}J0ma_#WqgCY6kjNu~-46?OU#{Fw3~@gJwg6${gCk#~BKyzA zSY`K_jY%*D&Bkn%^bGV0nvLnO1t6cQBKv1HS=lROhAFvQg}*Z-{Ozy>FuN6|fXwEq z$o`qlQT7U%#nSG9F^Jh>mGmO?3SzbZwt&p;SCRcQyI0vOWCmuBtMIEs!molYfZ0lz z0y0|xQ{YbkmcbZytX!h(71EBSt%WfN=mw?eIrItw`V4FVX+I59VA|_o3`_e7Wv`Gn zXm3@yZ9%`F+&04&klQAh0&{y=#r9tbFDkoVZaYmH@jdA znz219^7|o?-wk#TvR^14pN07N1h#opMJtOrC^ix$zCkMwpF)Z$B{&7za zk9($y+Xx*4P@Dl%z(fd`!j?#ZvR9ahSlU@I`k-ox<`7h^RLbX}V?bUlR9ycB(p=en z@@fsEPhM@%9FkWzmDfe+7=W@fOaUoh2vZo!j>_(na(5VgQtpA~kd&`bDPM+;0eM}j z;`*b!SlNB@>I0)sUVYIVlGjL;*D!PpKsf}afRqQp6o#@y*?m$jh0!PFQD_cHd4fuL z96AQ%b+wA?kFreJee${vMxVSUqB$h587i-7=opaK6cyJ$uSv@8lh;fbee#-x=8(LW zsJtFT$ABqb1XDoD3t$SH;`^1|C*`Fu`lP%J%^@j2u2No&jsbbCQgQuJu2goPyw<|# zlh+ey4#{hy%IigR3_!U7rht^!!xVUB_$-WJoE>HN(X$CgA3d+2IYiIfO3!w53`lw# zOo2&ng)uDY*Oc8S>33lCNqQ%mLz3RBlKv1K118~pn0)onb?(RhaX$%<`<06Od6@J4 z{>~4CJO4>J{~jF!MEx%;?$7>le+iHKmx}v)nDf8=ogWT&eoA5T;`5|J&y;$eh@Aji zfZ*CN`Oac2RtqM%@Qj5;zgFV!IkHsbdLfbj6YT!9Q1?Q)kB7L=gDpUq9UM6)G;&iF zxk*UmM#1jS2z7tHa^C{|0+MeY?7dmA_gGp>7=3p4R%i~{-7i!rbqJ2zE-Y>*|G1sQ z<6ffT_Cm)16g^-HSfJft3Rs}Av`b<1L6Jan2#WqHrM|&&uLz4fz&~zDc-+w{ZYeqj zpcnyD0E%HSg`FgZD0_u{IhHmCMjupVXbwSjgG%{2bPUMrS{2v-3SykH`{Y#)qfcIw z&>WK2T$R^N=oo-<7EA#t&wwcm<#c8DN%ZOU3m^d8e}b zz5_)o@#!xakqpuhF)GhonBr|uZ|uY zixnlTAtT3(9Al(06R*Oj%Yus&R{wte2lLB(>8Sy|?3&*5o7Nj+tf^^u|1|!$GVu?; zB&-qr#`PI8z-X;e3C}wQAg46EZ+l>Z-?yDMh)a6Q@|A{j_w+XlabvN*a6Z73;uY-O z(^MRkHDZpGF)NL7Ib7v(7|k3irH@fL3{O}i`;9PPR!px^j>U$$0b?$vvRG^|HH|VL zEp;K45)0#9+;|grjmpU4S~rX9+$<)#SzPaCQLeHW=M`MOf^)dKVh&|NIZO!1VT!vV zrnxyxcXPN=t%ykpYq`le|5OVpB@&AvwHvx~L*xvtVk{}?93!+)gOo9W5 zh3uOsd)NuGN&q8-fUH3hHW3N?DzYgcA|fInsJJ1mvM74pxh_|6L$8Xv*IjYD`hU-< zo~r6ecVFr6?|J?__on*PsXFJppQ`EU>5QGJyqe4Gcq{C9H`wu3s(4E(#H)9f+)T?| z;;oj9lGZC0H)4mDna|9Y&$SLGtwG@8N%S~wxf654No%os#nWj??9G`hAJTdoS4n&9 z)`HOJiRJ^Ra#u88FXYz!TZZ8PQrFYyq3ny(U2u&$A zpC5~5zgtR5-eV)W$3}Foz3lfXsXLv^j+f$Ha>?gWS$Md6C=w3eiPTd}9ud2y-4&M{ z+4tGm_uJVmJNu({_QzEAhbm-$pknsDiP`DpPiKZlT(VaWoz5?pP^j9Z+O=Db?a^j% z(+-{1z4Y3O(UGAYlJP|TE^UT=zSa74)4jt+O)VNIlMZ;#aXf~{0@r2?LrNzVI0~$^qH8PYM$_!h};-i zTz7TdJL~SQJ1MzVB%0f(Z0h{#w^!diEZF#!TQoTHfUF_;kkr7(8a|B<@b(F%`ndF~u`@OeG%E|7kXi9~`H2Cih?u zBG>Rj!_9|02HS!D;m^%uOlgH=RKw{PH)#?v|21yesCAQ8jT$#1Rq1Hgp;{17q$^7}q{@W_uGnje9#Q6w09$F#f4=Hhglug8%;! zp(FiIjk6bkJTsmPg}|I|2pA;?nz4JkdGLTDUl3);bB zClpUlPyr(pw1N+y&J>)juRjhi)W(z;>OMva>`9X4|8q+#7k zO3SWj)q+nUMNJxxnlK?Jat7QReb*RF*DDhksKlQ}VP5tG! z!5S8Y#HfGM8E}2r+X7UuQby?`FysY$*&B8|uz`qH0ZLO^GC#Qzqz#gW5se@|Z#Fctsh<=t= z!X+o#2K@6P*;hsOmE(j2-`T5Ev2g~EoiwUsdTFHR*s{`LjT;T?KB;KJ)KSGaY}lw_ zlO~NCp&d50XiC|zq7t0^rj&sRHc??w$)wR^$27b;bY}SNf3BMKcHbVqR~z+Hn>r2N z{^aac!2(a`$Q<%e-d4$5FJJKAwq5VO=dNnMp1u0i3N=D)nNjnGCT;SY?*B(>|0BX< zUdL|veS7mXIccgr=`=a%342nRn$#+eRVI&-RI#5~eIwQ<~*<>fR%-Z=ar&2_WK{D#;w1 z>>MlAgqB@eQpVO%A2S z3rmrO-C`HENlj?hyH;yO={k;NAJE}^LuyUNs?N8FC>(u0*eBJ=I2)9WE-aCMc?h4UDpiSu zLglrgbvYfB<1`;iDPPqdpK)$ZO{%#eF#tXkOmd&UB7*s!VtNC6{wB=tpB5^dHhQ|9 zmi{nSr4$;Mii9`NK_6Ut3_9=GRqaD5No!NX&Cz4CFm!nCJtNDX&M57!)F zPD`wGHBD@ijvt+>g+ggkqdhT}fqbQtDuQVMFl%UHOZ@T1@*G^I#%N+Cg7ZBxHg`@m zbJoMuwKNs~6;G)A7^c>xsi)D@ni=7mV|i*kWsyOLlCGnf)h@!1!?=4=$B}fdW2VMK z^KPPfCj@@{h^w~RJTE*J>6T*>G{*DkS&cF4W}0<>L;P4-I}|#HW~GGZV%9y5RHi&i zww|V)))+rNIoB-mFOYfKG1FXpnz?~yzTX5t(y^3UUIuc$#WRa4R@x8~H`2uY&G4g7 znmsW&z8GIPCz?5F>Mb;Natr*Zj$Obxc`D^RH;XpF^u!I<64N%(v}kYq!1L;ieN!VV zT=PP6nn{Ny-bxd#KKRi$77ArB)Ff;;n%JHvPO6Zw4d!j8d4v1nNBz2?P`X@tdtNWc zJToKByp3kIxg0-^U}mOc<|X)BYSTtnc;$D(v@JBPWGH@A#m3RE#LR5G63uC5KALzt zP5g5hethVdSQisVm=n#Vpov>);tlvrRQ?z?ozB<<6EBHSp@}O&v+kf-Pffv(td?pP zz%+@VPGeSLncHYy|1$je8T0fjpXSxVUx>pizXF#Y$ag2ryJ8-Gyndrm#NoMt!TJr{b)#Ka?H4kX0%*@A646hLKn!5g0lqWY0h~nls5>8 zcF?r$3-Mzcrr9rAO4Q4oW5OU&J89PIi}2&R_U0?^DSGp?)~vaeYRyW{piXkO(?A^a=v zj5GSz7vdoFD1N+KfE{)fCWS*auhuj0p%8Z^8>vZW;=O7|F2?VqNq=Ed8=909s#%mc ziRZM(sASAJM009Cjvqa68fsmStE*NJt~s%8h_^=fNo6gXbsT{|1R1X{3)A+{w8aPT z<33F5dNrl0R8+Upq=KZ9f~2y7q7DFx@P`k$fA$>3tYKN-$9;Us8~?v><6^LGq1AzDiGT+Jx%wTwJ80)Ij=&Dg7l+ z;>Q<=(jcBbc|$?crh?>}*Coz(On#guPdI`f?S`8rY$ynCDhTf=NZNxCbIlNr>04>~ z=%?}HQOETC1xZ#x(!qk{Lr}2Do=*6r1Qnwm>fcW>Ry~6s&2c){_)x+Q;9KsP?U;#& zRfWnIJc}RKI%e)K2wMf=DxswqdWRxmsvZYGEPWy5MW=;=;)#xXdn|Qi@z>APoLh3(fssL#l+<=n9%N zF)B#K^jlL4$ClvNAP8AYhO81=Z;WqgjL*VH?7FR#nr_|AU>76U&#|c}uxXP*yhlw% zbyY$Obf{KFq|@PwnUNYB&W53sx_Hx7_iH9jESaR=@=HMvzsN+r?NIMC5qz$A7bls7 z(egy4h8AMzvlv<>bc-&iX(JOeLM8)#7oz|Z>aoRMB$|y z26&{^*4w3!j}G!%DRYF_tV zcoT>(Q%VzDDI}U+Yl$FL3}p z;aa4pH8wR?hwnzihk0tx*M@I};cH>|&JLwy;KDaSlDg2JtYl@Qiq{}3<^75TO641{ z8k>i)|6&9Kn?Om6W~}9kCMfE|xR@}CT4@wzZq#$&d!k{SL9c!WgVRGPH{&nt;CAPv z5`5y7OSu3+U*~)abwrauH7w<|0x$ZBbe}j>{yQe%U&{CR$mbzli6P-{a_}WOcw_TL zSQF8wr*cWOjqyL!|ERHz^UQ7B9L^NIz>V=DR4d#YXQxf6p>_#>O}Kr##<(Bn`0Ot) z3G9#l?c29*-rlNB>Ntnmq(e0|&plBfsbnAlT!o}hC?(VLyrdS1UUcsv zN43zth9jm-ESyq22FpxA@Gl&?`EN0`FC#smRtxoSg3#E^GC1vI{Hqe0r&XD+EUfZa z+;AB?34cR;?5M)YBk&8CV!V$OPQv@i=n}k}(fKq~z6f#fnnLM|Q{!(r*h1x%Wc-w` zTp-((YR2@6`v5_zgjVZnnwX5wgKwwyb?9U|8^XE6bean-;JjXR>R;G9zjK$urdS+$ z`S2+@1+JS14CvjzX_H2sS~R(pjqTBf_Tt3xOA4Ts*02AQX6dWTlf zlHh$(or?Q*GODAK>cezWRi8_#kaD_)!oO;vnJp)dom^^@qcW$O?~17Pq@D4FjG8*V=;{$u zsK_W{Rta6Fk(m3PBrn!3Izg+q(i-s1*FJOUtAVFA`0~`uFn(MNb)t3<7I1vGEZBX;D2N46!V&_ zTIdIQNy?3etM*VzJMWidp-x8Vzu{!FbuyD?GU`~TT}{lZuXOw-+b4_WNm;(-EL#%K zMBV$FXQG&lMv6dt1HAmOL>Wo0&{lULU1)=0Bxs7IAfZxU8D;W4{T=HqTFs8!5m)DZ3 z<_hJU3cGTyu)X-+SaN0MTMDa^?OBQADta2eAeMYud=|d6m7J1$0fpa0QxJ}hchDFr zgNoP#19@y~KMk{wEgUEFgo898KI9OL6b^L8(DHJU_5a(y{Ot0S)Z5GRBjtaF@|)He zeRgJ*5bKRi0NDV}B{ zr5VF%=QIK? zyI`+cm!~b6|84bw^ux+e+c|$}1jh>_R&N}yqT~4yt0#_E)A8I0kR4z~<>z8{uSQGe zMUfduR7WYQO+Hd{mkknI^7E z6IZI@`@tJ)XD-JmUA#3CRmPX&Dp@@*$Ca}B|GgYzSX6%`VNqlT5;X!5pk)Ya!2#J2 zH3_07q=|89;%cR6BwSEyEXM?`$Xt$bQV=i4)l!hL93@E3v0N|? z$VTNeQTg;VF*Qw;rip7*@ul#_dYH>GT^DanMV0a8D3#Uoa$F;;|KH1TEsLUW2eK$K z1Bog}1Zbh}yzxt(Y>1i*QFGG7>@+b;DVhrx)Edh%M=LUyW408;%P~s|GL~Z=S3VEH zxNO)OBA-w2oUb-hGaZY@HISPOn(FVLmOw$j;Y zZX{Hmi8Db{oRh)>7j>N43j@_FeK~7ch48F}%s^T;Ap*3lV+lAQ8(LOD%gQvdLJ7GQ z{Z1h(wGeX&R-BrS)vRMPqO%S%1L@d>2q=FmmyZLop<^R-tWOg+rHQpl3Vp-U`Ql!$ zrC2u^YqIv#wA{j4b|XA%Av2Jc{fGbw_p<~XkPR(cpk;HK*rbG5=ywX)tc93svgy=x z+|D{4MRe9dW*{BUA_B@k%;n>NZ0Oht9e1UPJJZA+O3HI^IbY#-X(`s7#+ux5YFc)& zmgf-#9 z<0C{s`R{P~I3OE39)XUB)5L>m;(jINgdF;@Y(7Clr=s%XxE5_cuX3{Wuw0cTp{0@7 zqiMLV+8pWC6Cppv$e5MpJX<`fDa0r8Y41Ue!MY#ExIp8xToa_CV4qR2N7F#=+v=ev z^s^~)hdPt*bNDPP4I|}s+kR&B1$vngnSmJnga`=#H5z_rA{&gJ1f#=g;-CWbvmAF) zHou^80y-?UEeWlP#GW<){fd#XrxE}?tpSMraScW+1AL zk+E0PoM*S!G$PBM$b0BT$(b2F@4~1C1$)h%QBC-)S2d$on9&*NWkzHMVuWw65~JE^ zcn^^cM(=>pTWR8$0+c1koiCegG)_QoNo~A`-ZKD2Ffw*L0nmFIkhzEK7|iFG3!f;( zde5Ct4t&;e&F5X_lZ#&FLuMd8jS&HS>Z4&kWP{J=;PYvk_&7~`q!2ZcLz~K`85$>| zPa!G3hrTipHOI)Q3x>_^k6Zv2&T&9P~0VG6NA?jtC&O5DgO}8^q2Bu}p<)g&cH)Y*wOi;>tAk zSJc3DBSyv|3Amyfm$|>}7=NGEDheKTr?nbBE23#-Gp#k~Wm;qgqO}DPKx+dUrbRYr zT?ktB(nU-GyIqdkDw{jdIDyqO_Lne#ZNtdeMd{8rK%s$I_C(%au~Xe&cT#lWPHa1T z)?{ zkuJKWi#&zxU+~7dq#HNYdui=f4||W%P4#XzK)R`(hvWE7^$mVE)$>`@F(hG8WCjxT z5h6g;JFEo;&&Wj{FX%hreh>a`x&WN8kvElr6jYoKjPBJhP1JeHYQyZr;8$`s}fw$ zY%Izct;<}LVkwIkrAW#$7G)e)ej0*t0{j>!ANIopq2INJm3NK>0B)9|vSZ$6V-`lP+ebi&;v_#c(-y z(;O|unr*DftW(o6kF_*Hc-BH@AT5_70wlCx2{<4dS{6gg!gMiT3AqgYP9Y1m5OYoD zpPG&(tfL*Gvko!?>FA9JD8CDrj{~xyV-<9)OcyKC#WE$Oj~tpWo4#nA@4qYMs_;FZ zwZ{AJ;j)1>0*1j*rpJb z%AsYlnTp1VXa^+4KT_>65KY6#*zR=aD`}5LWZ4sW4{ev6nb9^EM$;+S9(P7F;InpX zMt3u#ndoIkWCmii2ob<&4jN`eHW)nwMh~Qmy$aA`IS$W4qTx%?H~~E%wecQ$!~nDm zBV+p#06n4snS02N!F=|*@L5i=9&zWh0zPY>=JPP~xdFY*hs;2HZb1YHUWB*)z$P<8iUM{}jyoiq!)TnqUNiRBn+C8aFfw*5;q~{X24>k4d4Iifs{89nivFfM zu_N$V$274wnAlV3WnyFoBK9&OfY|eBm>Ah0_8y46t8l#{2fZqr*U&g|y=&~R4-8!Y z!pPXa6L5W?ahdzej`8>R*XtDg19w_)z-Rqi(|Vt29YZhEA~O)J3-D!o(8@r=w8#dn zSVo?xlOb|4L?lC;pCK|c;&)?X7!a$M5&Pc$$P}S3htxmG5+@1ReM-&J?{=9}@Uu*qE=wngYys}~}xRWE}~TBuMC{rt=B>C`b4 zlD~1Sn?Yh4U@%i5GZ2+a5CMT2p2$zgrbA{RI(-oV zbn?(J9kM~EBj~ix5SL|$wi%*LhG?bGT#f;NC%M!oF6}iJ^Cfec#6p|KYAadLrm@-> z$E_q7+ClcW3_G!|en`T)$PA=wEFwVHRV)VwWJA{g=o*?KhGdAr8DgLkH4a|9PNb-d zNYqewQA5x@pFW90)Zh&4|ADM&AiBS+j&7x6IO`aXxU7TBKsx3l0?MDs<>P>C=okwf zV=_c>hA7GqBQivxlCl5;V&fBD(_^$6s~F7Vw|9!<8u9I&5qiHC%4P9*O*{81{=?Fc zHNL`rl|6dDj$lRf&>cQ5n!8iSb!nSprx7ZHHrM>KruBO5&SgU7xM@lb|%AVcg` zF#d!Wtc(}gK25^hpASh8eCm6^SlGRigmLP#Sjb-p%tFWvBqX&G3#o~Qg^&#)PeaI& z4Dm#UIFum{WQfOJcr+dIGh^7xs|U!wY*rFYIGd&fi+tEabDE zsj#rJM=$I@n8*1T%sj{p#N#4Fz{2LDVIE|I$IIYxG()_YA)e0=&ng%KUa&G2_NXRd zF6@gE1TXCK#=<@;Nf-{;HBwsdR9IEnqgVB9hS33o z83vhwVDv@=Fvvs0t4cOtd;l2lXNcp9L?846kzCJ<>Du#sjlo>c<9a>qi{%fw)O-Zs zQppTd>M%q=sROt|9FUDtzd)&Rk^Qh&`5Co{xPs@m)2&^fXxM?2qA(*9sZ3((7q$PC124I%)|QZ&4rWP{P^nR%j0rZ_EAq-2Vu%=jIVwQ}@2 z+1!N2iK$AaJS!2V8kri?%@`T0p6R@js*$Phq}US~(`g8TJ1Kl(PRZmuDf}ri3H^!4 z)>GgbnXbq-z-Lv@RLH7jlG2UnWn^RqLbe?d5a>2EjErm`s|{qeGR0X6)?ISk4%zHP zg3-Oq#CexVPx#QOy{0T)v(MLj~#aJ`2J!1X#B#zi)8^#rc&nWAf^=#nWq zDPr%-(f^js2WXtcxJ~RW8WRrNHCek(~#hHBKWN%g9pE%gD$KgzN%Dzz)ko!^p@6 zvZ+8;nklZy6eWsROb)Fpn|f%Ryh^21-eEHgUiC3DHa&sY49&~jVRj70b&Y|m#0A%d z6nBO@t_JW~(>1PXjO!xwGA=R$;c9~jz||NH<02cl76RA&Offf8%*hn96|qa?=(e)C z6pfSEe5i`=uq6hu%P=ywIN_|nL=&^@iM+$+O6-hmj)82p3$k_;c!@i*_V8JYHL^vF ztOI%(8JU5Q^+5z6%R|G+$Of`CK(;DVtjrWE6t8?aw6AO~N8{wRN=oG&c9X%YA4bO3 zCGfgQ^D=js9fNVLG;pnO!PTGQ-sFyJ0DRUujcYCA8i-!TMP?veMTh`g1!x!-*}!!N zaNV9MZp#$6W{O)Bu~Bk#v1~@8aT2>7s^U9ryFu(~jEvox>HJ;Cc1_H(C-M%vO=4$c zw;IT9aX~hY0&jOmHXc6fPK|6EBb$I;Mn+~JWHS)~$gV-d$jAn=p7{84Po~(NDRwDd z*UF)@WOE%FC$D>e0KeB+5}F^0-EZ)^9wTFW6L{UPd6_%Rj={KgXR6-~?ZW8z?}p+Z zgvu%G{qD5p!e{N(wC-bC_*)c`7MX!)twsdUT8xHikqughvB3^zipMj>qnToVrr4*L zt&tPf%4QuJC$odb9y?+%y9py>Pi8uQNq9svv+Rky#~wHK*rUcC+ix82bJ=eVv*x#jE_yyadnh&^Wmzmx@ z=w*6j2BLQu5kSvE!}Q1oy>~$GtxR!DaeG3Jdr~$>&^Woh1wHXo+j|DLr!X>hJkxnA z?LE!SvM2JkJ0{^1xL)xW<2i%6DiO3fX}2E1;ZI zM1GNjewEE{Xq-e&8oT5VgUIg~8T&nf$RC=Bxl8OAj$QHx&Huw4$baFpe%C;LV<3N` zmw}KO2uM+722y~AfshR#=Vs-JbF#$QS>ntrQ8O!kQ*RW!u^L(O24-`*fq71rzB6}r zmOP)(cbv||vHcw<`TJ(Pi(55yC!SMw!28)==Vj3(Wr%=46Ic`u$cDOX zsLRR{8CfDtNt+56WJ_tSNLrSbX0BWYy5nD5Nz=#nFA^eL`7{LM%E=5=`2s{h!Lztv z9FUF5FGS__vP3LP)X5S#s`!QQI@hJ1F5Ze6>rzKAfnJv!-RZI}G|utgBQ;=+OOTT_ zk{L+jdPIP<8(A6-$cDzI(AYRjT%09@61V{_h&NWJu@-2q&c#v+Z9YrrV|#U)apfBk zj4LNIP~{IG0t(*A1>=BhRNfwyUzR1>W{EagqE(h?q3VAS1Dp$VnXcbzi$dv*m|i$- z^jcW0viO!Zy>wdWZkHwEFA~Ww`*mQ6`;d<%k{L+i(})0NkFhcwkPV5wAhAc5=$0k& zvP9=B(NRhK2L?DL_An%NGbH9|EmmhOv7_#Gkyv3D_GY2aAu9_dGmy|X5CQs*vOXM; z4WR=dv|pC!n%zNT0s z-T8b2pEW}Bxr+IGi(ckKW*|QQMFjBq2@Ufh8+;~$&-g4cHcO0Ai2jsA|B?+J`I>-e zJS4?0$|oC$@K-8Av63w3NpP}8WZ4sW4~^AatTFmn?IHaAicoB_JELUytP;&=5;ICc zFEb)D5TmmZ0gS4lVMb(w(F`z}mL4Nj>~&Zi$CE&9tODxC| z^Rh&_qI97g-9R=Mp>a}L1Xb~EwA`T75F=yDvhY@Q0A~sOIT*UqS*|Hr_C(%B3p5&Q zo;*?WuUE@;zuHobDDZN3WR2momT6>58CetbGBPp)A!~;SK-LlsBO@EgZUVBkSz>jT zxKZ(HFNb!JO-D3NUTdW!-c=h6UY#*AwmyN^2F=UdRdx*CRjUnLH@e`;qqrN~adm~y zTCZ{4%(%LtmvNC92-hG)0IuF>7#G>VwH>&&Wr?j>VoR3TtcVSkqpy(75HwC=+n_4G z!*&|P@Hg#4u^m~sQZRPdPEE|RC-M&4s?k_m3}l;izuI9#Dez8rWW(UIc4%aGF|y(4 zWn^RqLN*Q&fNUfhMn*P}Jpg2Tv&6kwVvpiAUJjign~7+gy!J{-yu%(gcum5{*h2}t z9@f0f9cIVi9d@sQYmW=A5{mnGQ6(95{UJXKu9^nmCEc(ec-dbkeb zA{)3a$<7n4vqj5n(L7r;&5nPXqzBN%GPC72X-_Aj*4g^gWXo*1zv!a4IgX#83*-Y4 zt0|7-&$94+Ky=$|s$~(9uqZMEiK0iyAkZ?_f&;Q4suM(Y$QJFg#idHoTDYKAD(Xy% zI%q}aLbj8FNR@S|6l6R$p)*&$4#Bu`G6Pk<6%kOddUOrhsJss<@0BfjWQ%UuB2N`h zkF1H+HJ788F5c>aD&wC~y2=Bh zR6YWg7iNp$*M11Q0{)>!^$9tb@!zI+`K^%5T8sTQSyTNE@wzx|H%9G=| z%BC9{C!n2D+mg@|k=Q*3pzatM+mit39u3IcCUy*dN4v{~PY;T9k2{~9@L78_pWV!- z7kZfwnSuCRi3s2`2o3Wg8+;Cc&tuub$`+3(MD&at3^g8!<3#irB*i}q9ySosQ*&a6 zvYltQ!y1ugPvkvhNzTmZ5f?`MV4cJ6jOal*)*;R4ATugPFEb)D5F`6xIO7qB8QBlR zc@~WRku9E5fJ!j{fIOds^AD+w_s|OlplO&Fdp-fs3mTBQhwK>4=P4IH{2-hc-1+c> zaGuwEo?|}hK{#Xv;$uJHMm-3JZ0w;oz~^7t;?->NvO;7$1P7$(2{+C?^e;$?@1eI0 zM9T@$o7v8@@mm^^Wl!Wi^s3~{j9zwOL=U`)z2(k`9(!ZGsTmz(Mk~?Fdx*?Hj5Z`T&gH&lblOAp4;?#xrr8fZmtdcn_U00MTP}Vjm>{I-voXd&rK#e2%;D zxs76-aOXph#j!rpd_H78^gtZuLuMd8yAc6=?nJ|U$OfPPfX|oN;&a94e?9%?OX!Jj zpl=O6{Pde|63)}#YCe`dkvGui5;6huzkZK@*M%Q{^Q}8Ee*Dchn%LJ&?14BjG6NBN zToT(CCq_1i{S0D1DqQw6at_L|^avd1cKXrSPQMzs=qWj|UlMTrs&Sdy$&T^&Y4L+~ zes!lskHxWm(X>u7EqWjh?=La~(K?C<*k8|};r&H6XeCARL?|NuRKWfz$JtNHp=aSZ zfrTP^e^sKJQTAWbcoidKDG}$JT&0MiNW1Y9*WE^~j`G5-Gk`h? zt=bV$O9A^?jyoxvU(h&#)i(B5x&iE0jEtp4oNs{X8kl8Il-nSm#(b4^&B)EVLZmWcBi;#ORa z3SWiEXK6i=iWh~SL8H+NQD<6hnTsfJ6DyPRzq4JSjFb>E@<%Otxcti}1h#{(SdXkiLI}O*BTSHMI zR)o)`Lv-mCuLUbUAo?oSG6CUP3z>nmOh*Jrn9LGzKsK}#LrYOaj8H;mpx-H^NDDES zV8p5E7|l9nB0B3JGmwsjh=B5EbNM(R8#*RI$ApL&7ZF!0DU0B8?xqP^iZ#wyldDfn zO9^XPjPR_5%s^V!Ap#`az!GpkHnfyM%an+itc2Wzey5NrT8OzOlTS^@RMv4bqO%S% z1L?RE5m5fETs{uShK||LF)JcwM#OX_WxE`Dmuz;RalZe~lB>e^4a<%9-<=p4n-g*F z%yLb^vM2IOY^KIwO~-NKeZyT8tla(mmL9fc&C&0-*E6Ht=w(J^24b`i5r9TLf{Sc0 zS^`FkB4U98^oSg{UpDk8E+?QxQX5|YFE;?u!?j||5&$jNfXr=T$KbQ)0vA4yQLN?e zd>)6-TBi9dWj+Vc%Y4WT#OFCg0G}t&@Vf-r;Bzzhtc!>>5rO{_ME;@c^5^By7i9Ay z8YiN4kQD#OzR^JR5=O>0M4YdrjT(__ zX&4#XpMcBKxXkTj$N2lSDpPRFomLh2to@qSBTTC*dYKlPfoPqB2-sgW&@e5sLF-A- zIvf!P6|mZJ+_|zj4~-MpVPk(iZ2+SOt;L>7c>O)Cfm!xM-d_h#b$_K%^rzj4rNd`E zrHLJ3Vj1XVVq^v)Ru>UKEQ*GSkqu%mfY@^iS3NnXzHBZ;QQxEf$&?4<-; zM>Q^Uf7vnq{{Eteyv2^X)1pVbSubf?FETCld^R!z(JDb)&?-j5w8#dnTG2dlR#co3 z6*Z!wT2xex#!vM0h^koaXzYFaBU4xUa@bi>eUtEvs63O=N5L96j(^>)T9m$WOaFm~ zRTbUO64h`2?gOIBkkzUkO?*JK?9mVWIwwkEreZMfAu;|`M*rv1CO(62 z8^W_-k}|(9FLQa^GVjnkk9HNykKRVb_Qw^=Cbye zAo#R%xpCUbmn4kMc?Apk0)bfwnSq2P<3Hzx5PG;13n3dqMnTBPsJJRBu8fLdQBk0@ zq+md7bTn4Qmc#EVBefjsD%2WZ*ej(TUf5xJVGE?3zqPPckk1-jVPR#DUf5#hQ5A!k z2bqC*oQDYDQ4+fNTi49zw2*iff}{MpR6Tin6GfqU7+ynaZQF-|ZJ| zA9{zpPAjsmMY-{{ogpRh+D_AJTc!`ENO6B_nH!=!tGvQ8%O1VVbC}M>7|e9Y3`FNL zL;#d#3dgU)i$SsE3KqheuH%#Vt>3JpJm>3VymFDEWbH5YTG7fUR>(hH51o^Kq_ zm0*ljU%|TQX-=$*%s{&62}F=X4`br(E1yUd+W=iRN5#6RSQ8biqGF}eH54PUDdY}j zT{pYyT4(55V`y1r9IvdPYa{C#7S}~)AYG+W7d?!Kb&-wr+6rA;qGEGYY*LEK;EHWa zxHQ_LMOm9sWqcEFlB#GE)5nUC-HeS z*nq(dgUmoMwjl!6?N&6rZe#<-qkyqLD)uQ7ccLGNjCI?uF_`PNufn=L#-(mY04|lx zK&3v22q<+ISBL|$QR*`&_35ZM5*1HG#i6J;plW^y17go5yy~9TWm`v#)q6s(o^?o` zKj_2e0d#wR*mPd+?MFWAxe7}sd-T#h%RDR$W*%e);z17!0)~TVc#)*`Fr9hc z(*P`cBF(mr83bN8RLAdo9;aaMMFFkicah$M&pIAe-$ilU_E`d;&ov-(huAUra^gc5 zKHpQU&)xa_0H5`l=JP4@`4PR$hs;2Hs#a#*AvDZ~Z14%?IdlunnU ztI4K18YiVcp(?(Ol5_Mns)3QQq#WnxrsN#j2z)=vvM2I3`a_~-Ourc~q+eW+)uh15 zIj&pk4EU_19JQswIkduOqL-1883`(Kv}^ zKvjH)MGRscFfx{%@(Zno!BJZ#?iJg(1XCSNXf~+G2j<_T11fP|yk)6-TI-{47 zkr@ct<%j@e-O(^IvVrVEAgh-nVmYFY;?++M?Jt`FXq>$2NvV9^5(ck<7#X`LftS#{ z%pGROU|cZ+R~;8zgD9?W$2Ax}>mrS-0pq#?y^M>@K)6OD0&opS!??%>t~S8cDo3=) z5zTT$6Ge<33x?5G%VsPZC$Uyg72jc(8pOt9WUOtD^OoMFnwVuz*RVrOK{3}j7Q zkWHk(m%1aH1fSJbBfEr=m7tfAkr@ctVnhIhIcOLe*+AA6$hzc+PC253;zbYY!qBC% zS%${RtBaJ%JFJJnYdJ>7y651ox4d*Hpi74y1}}ReGwNh8>fpj?1qJKj&gcgCtnQjo zH)gaFz08QrK#Vpa0)($c!;HuVqXA&lFGuvv5q%V+TjkKrvbhb7lTkl|(O`qo7L1Gy z%E7NV3`TvF`kIbw$5 zbyN=hr)*wEw&$1J?`}T(45xx$d}LgU>40 zxaKgff1#Igkr@crM~DDQ^t3eIVPpf>D&Sg~BUa>yWjSI=j##9iosbhgmdz(w)7PJElCa^7=y82J9c z$k^5de0OMk=AN@-FuhF%v5m&@dKY^Cr5ty-)1wEYSz9%|+nL^9=w*6j2BPQj+_BxD zw<|~NP~864bH{c;Pkh_mYjES|j@^^vytj9+=4ROwdE4!f@ClrHt`R?M>|S>${IIcm zG?YCIMLlec%s^0b@u(kcsVp?SrO3vXdI(S+P(UH2)EIAoNr;Yo7-4Fax2dq46#uGZ2vGhyWn;cr*q=Hh>%kkb^nm zamA#C97m5F!|+yUoJiY85qqLzYxJZ^FS=9c1)ueTrtmydpr@TN1u_FsxEc|ltPl-TAR81u z28EAu#0NRz{Ty*z;TQ{V?A;ux=_=Cnk)i1Wdwb9?+TXXq(62ji$MrA%j?Z!3>GBX% zzU?ZX^ZE&^qo<9rIx+*Pn}G;WM^6M}b!0=`*HHIWj`$)+e5Rz$gbT8zv?7xBm6m3{ zsK1aR`0e2{eQf_a;~TF0S_I?D$qZEaVnjgY*K@%*ARCqcipo#sh@W!A4>{sHRs0fo zo$GQ^7jON9D(U1->+*wM0=+KZ=}wn*sqkOq{KguWBPVMlGmyqx5dqTHu{0cz4UI{; z_-|Kp#h*Fi4<&FjTo7-pPAFI1pEFnIPbr00=MQ~suTF9E@<<(Gm)m%|IS5(T4-(=e-hdv^k{b-zLkgB=*owsJLzA0&8WUNN6b4%9LqAhzO zpHnL%2=3Ie>Pq@py$e4|!D`YUL#=pk`!V>e8oBC5WOZirIC_~8nSmHRg9t!#7!AMn z$OfZx!RVY^akc{VtQ_~8Y@SEs1aywn!KcgN!^l`H*ZIP!s}WiDMBYOY&BZ!jAFDm|J_W1m&gkFpSuxG%0%r69dYKWK zff#*_2w?On8fHW`7+nlTB3Cp}fWDFAzLm{)Xq*bjEptT#VJRgSw_=& zzlj0Jp2!=gfeVzMC_oc;C_lqzHP%oXF_e?&Whi6@f>O0ALkXc_C}ac5Wq{H)SG36$ zt#U;Rh30fQx|(dNqj92X3sv#G)4@Pf6C-2obDi%h9Sk(_iS(}0#^y`^wQZ|hzROR) zW^JLnUEWvZuUT>4>4_yio6>b~2U!a~tGx!wk}C%1ih;SJzv9?Nj=n@T zZP7S64uRPCZoJaqco{~@{z2`tBJmgb&}$DlnqN~0Wkswjt0&hhRj3*fWHX_R9bU_z5u?@a>XaP;zX|aFixU z_1WDN(Z0&HJ_LaI^t`-|Iq}0dk0m=E{X4WUju++|w-TJ58kadEKwQJ64^~OB z|AVGV^)Y)uN`AOC(tMZel#v@}_Z{as>5(VLi(QUpSE)W`Q=Ya?sQKYbv3Q`BAHIws z?Wq7s(~=v4Kdj0H0HkHnL}2Y0rAnP2ZqGZFc1n<)+C4wqiPo??0EOz{s|~s0k6iIv zuJ|RsQ+rr{I(BO1IvC!Q=J3|CcWRh=dqXU{^ARnnj`fS%PED$VZP2<(onSi^d9YJ4 zn|5knq)Dk`{b6iZwRuuFP1XNX8qB6Nmm|$-b*$gyYe3Rao98snbGk>K|FwCf9L%OX z{dtRIhZA2%dW*>1yhWsFxkV&r^_m)BY!P0UfxJcN@Km=*gF1La*p5w$W-A(6cD8|J z3bxDSI$~0t_{Yt=Fu!@>p+VUId0(Wv99J2s9kcy7<;;*vN zpf;tnkIHu-64y*-pqhV>HGdPYnQYX28*09_j<`kD{3H5f8&M(t0A{FsHA>{tQP#?+ zb!#1ZAUv07-GXEM<$D^}s{@a2vxRH@2@$wfGEcSE)wxhxiWNswf`<8$jasjX;a7z* zF)f`D^fIJGWMOD2Zl>W@168KF_<%YhH=ly!x1z zA8t1wxy^V4u&ZgWt2vp|YO*Y`gYGQHMk)Ub|FT<6q3Io6Qu2DD-rQK3Ti!OMNXL^q zyG*X~KW5j*?EG+-0V!>+K^PR6AMWZFhIvhO%U>T8^TXY6T?E~@%Hq`?gTnwP-Cps_ zF1)^`V6|ryh-vZF?rqH|z|N*u0~U4`H1UzOd6A3ws?D^1QxY^WqEZm{%Y3 zaD~LWt_`MZV19T2oi_$T*L3KbQy^x?bq%uS7`u3Z+#-W@C&VtI0E%U>T8^TVUCi=jI|T+FLI7l#3M z@!0(E)wJ4UvD&M!+G`5Ls`zS;v)0h5kuMc;Tir~##ycxz|G-6|ve*W@&{d9wT@Qsk zZ=w#x3y|GvBZZsf6>gJjxLXj8=S_B*SB0+;P|Vbr>+Je88wKTuuVG;8f&nYb50?_K zG61^{z-}uLx5j}@wQe(jZIgR%n(oBQV>=Zv-B~_QVv0L#*|$0<-i5+>-b}A~ar%yV z^)W9$d@WuccOrmY%`9CFULHGTiPz~)dv)%nsk2?uX~=tAYu$}hJb8}GWMhe3XV=GU zTnhdp7<^(UxESFea23BNMbHu>TqB;?Bl|gq1!2sC$qZ!HsyO9JK_AMh)Gqr*hoc-;d3LMEIm{{;E~V>Ta?q`Y zHV2Sa23X@Bz}P9S5$YoXRIJ5p?3Bk44#lG5CXaB;@{n6C^)VR}Z>C7e^}z$idNOFI z+z&IzPPqjE5N9JA-YH~br!2xwd9pwpRy$=A`mHDF(+Ztru_2!3{I{apNtMSy#MD^) z6mi(GA^rgZa_((DbK|E8$K3jui(0o}9&3IopyoRe0CBdWVa;Si^Kxi@u0TAaG;c${ z^_-#kMb3XGx}BPN3~P?R2%d3hehHf8T)NZYH8=huaLlcbxu{j$*LcC9IXS#8H9Hgz z*9g~0s+@FFYGMB5vauzTO8b|UOc^nzIJ6`wR3#;pdvj{&wB+zcW9ThjLpSlz0ckR7 zIDC0psIbG7F}=o?mWA;50+Lgzgu^AMlRgT2EK^bJ2og&*Y;ek6Pz!mjepe5G&Z z5|w#^Pv&vn;ji`$f2|5X-6#B1_&kJ_dS|}IH}gD|d5%x!+1}x2`G#Mv!Y}a&zX(1L zVGF!6^L|^c!msoRzrr`hEh@%(pBOj6=TYKX-|)Aq@SAa2`5=__A4%(I-xAIC>#o>q~I)un>vr8 z+c>+0adz7psv^&CI2j#LB^~z8d(bcMQ|@`6_Rsr@%6k+8JyzsJxI9j=&%@=3;#D|Z zP`rk29~AGZlHT&pd(1EIareCM`RDyY<^2=`Jy3iMmj{ZE;POQAC7doOzCyPTil0D)!c(u z_YZ!q3SJ8XJw%=5m-jsPys7?qvsKt_gd<=OMToT&}w(9L|Hw<5h~&@L-jBfKTRr-r@WDh99ZI z7y5)B4xfjxq28H?_+}obGLP}eT;mdqu z%u_Mu_{5kEpGS$ae8VqM;TQUZpYI!EwTiLQyNnfHA;RHhaCz+QaMBt$UEYD#qTA<; ze5)#Hqj%o*et9>$=e^B8@7*fz4h-~Ik?nAKyv(=3<%wc9oGvK#pxXzXhQyz}n$ z%e&7#?<4+spHO)ZVxR|#$Ki5CL2t%Sy5~LOpZ9r{_Zh$7FSrMP(LeYbD)?&{=ppJA zzr4rX^SGudnK}vgI+EgdNTPhNBUAZ}dmTA^uOpmP56;95U!Dsm-ttMU2yC`Z2rO`^@=|med>&=Dh0C+-HgNit-Aef@ zlnvU$Rc%8t&a1W|@KvZSnb&!+3ZFnVHyj?Qd`9YPa089sM8~PrV|-EE+$|fj(h03s8^Hlmd zKIvz}=fP|iTppFpRGHl?o38wBm90>fEyXx5FpJ^ysB9rz9+l1a&3u!}yv8T{+_sX^@e}&4zN%z6& z^(wJc(fcsUYco6qpGRd6sLbw_?N$B?mEl$L50(CiPx>d|^I&!eE|1C%sLbw_J*NB> zDhnq)1E&|WS5(nQG0KbCi|~0=_PomMUfHwCU!gKEdt0SH=9B()_&k`s2A6APbj9}$ zoL<5|RGHuR$$Z>9JgWav#rVu8#wYN3RDZ%dd^qVVIK8U>L1q5dC-c|d;Zgk`D#ouE z=TYHFuMpwzPjJagfC?)cPWmsLiN)jo@1N*4Hd*5R-)fohOUEjio+X_Im+O*;!zpn2 zU6mv$ze~y0;dCjv2D*JpK3A1o3j;msI?FHbdG2{r{qxpQd86KWvsGUA7iX68yYRRG zP8S|Abo=n=rRwUAfgZc6D_kC^y1?bPgq@V%rR3glx|G}p-99A`Q6&$;K##fxsJ!kd z`zgOmT?KHu)HM{{K6Q;%b&bYA50sRJb@r%O%uquZyZCsa)bG0+3! z<8W0dSAN!f6fVzC=lkLGW4urK4L$J>qEEu!Rc4@ zGs^E$^eb?>6#Xi?eTsfp75x?ldMv^*xLoznCFXJWyzlwv{aEGw&@cEW?!iCx5B{AB z{xt@Ai2BMe@AvL`fAG)yo639AFZl27!T<0NeqL7m%J7^l$C5hk&z%jQhu|~ea$Uu6 zxF%e3;~5)^US)j4D55fF`DD&;3olPBX>Q@k#o-&M@b!Gc$Kdl2R>v)~JV)fXWmdwP zsmzUiGGFW+UigOZpu%6~6TU5c9>UsqXKtl3C!DM88*MF=-)%*EtIB#{oN;<^?4@q- zc~q7Mm&ab}tTMY-)=~N0DjTRO>*toe65spm>z%!icl2=5AUIu4k%Q4~Fi8AJc9kk= zxOd*6etAc@=N;*vcaq9G9s@lVVk}%93o!;Rj~8_~sRT|J6qC{IgJPyCX_|N5GQYgn zy62tcpLeOsy9fh4P%MDU1I0YJ{N7m0mA}HC3@0sv(*@OXbo-#XS(UsN13l_mt@66R zR&G>&m%7%&=~CAQbo9mQQ|V+@at9hbw1(O_{O+h#n|j!#wM>2 z;qXSdJkBfOq^)qeoCfbex6f&Cw<>9;ciy}F^6qiZdyjwKgDUT180fJg7F-^u*hk>< zL~#gC7Ziul?StYuRnkAa^FHO5_j&icFZky@rt}N$-2-J?@wHBlo-~{PTXT@_vbd9w`UU^RJ@~Kw z!ILBLD~(XZQ`Db+c~daYWf3c(+h-B0tGrb)(34mV_uw`CgQu$CwK33RrE2-*O>@ti z?w>cR@}BP(JjXqFu7B{hDtK$>K<70fd>(?E!{rJ(9BvAi$E%dC3039}KAGEjhriS} ze7*|b%O`vf_&kJl^Uj>-n|ZLxJisS&Kkx8;eZya+!VmWeKNLO>VMDw!^QF^h6~4$P z{0QF|B`U@QpBUrd^CniFwkQ~*1+ZQGG7IkCyEVlx}eyIZXXnPsFJpL z=iTg=cbj|OJN@(CtMcx~Ko1nV;BrMlZ^rkz=iTd{_Ysx%A-~}J-Gf{H!H=lmhcVDY z)IqcNCotpGRe>Dzp1dqjQzNLS=Zzy-=mE z>y!Qh@ASDUynFhn@>fV7PHF(B7nl~RvZfg21*S249;TorCB%hdvtb}DmQ zpUiE%!?*Gc-&=+6;S;_ad>+E`yfb%JncY{Tqw>3~Mjtr6R^tj)^gxXAT8;kjc_6=B zWp=MDU->Ikh9xOh=|}pczY0DNW>>=HQQ0t+*}bv?<*!g#IB7JTUd$$|q9ric4Nk8WyIW=6;gfm0cX*I}P{r8m6XRa^JgVR0 z9X_1&5S(7sKc+J8_sP7^J3Oj?R>gSQC&m%@JgR@fD||S72rj=JdqDXs?22&Gb8vbI ze@zwrGDdlAn4|Ey?uu~uMU~lozdo=06)FR>cUAhgFwTR^G4JfJdq>B2ec(*gjqfzS zhi*e?;xEuYRVAJ9&ikQX-p}0ge(s+)oD;vM{SyN{Q2YUx$3pxDm){ooMfoc%1Ri{l za%I{KFIh-za%|*9QU8_}HD>2XmkViKAKBSk<(DJqDFfQm@5q3Ebsuz}bM zV(=h-WDpJ>pr0>PF&OFdzgnA6Lhb`Pi5qS3?Yb*OH{>CKMQ zx1nPLlW;4VJmaD3+%4YY-ro4Q_d4U=-I(!h-p221-1uXT@rTi|fuJ60Y}_5*<38T_ zxX(D_KHZq{-QLEZZQS^$j`5G&9bI?CK0sRo0l$YP&shuv-a(U0JT0;4(@OlD<6CFs z|1>i4mkpc$yixPNJLZ3B#QaZaYap;68XkFHqa!C~+E+3>in8XGsod)#2-n+@8+3C!=EnD7vGm0Tf-) z)YwU)v(sL0Uk)VnLZb(&-l%Q_)ey(!Ty$)}uYu0E-d7O)opukuhN98KuhUW8h+hSc zUt`g+0hDK;sR5Tqp{X&H`A)ls%V(j{!{xJ4-H6L&j>{9!u>rqIoN>KTj(6HU{F;PD z55Fd(x)Hy=f?tV&#DwoNkHvz!iHSeRGT}$7{E5nh#H634ob(HqEdqhS=P;aKIkmdD zG{5Y8UL@E$ddg)%K6RQkUl;NRVLwJwztWo8vWg;FXV_EyLw6s|#vDF9wMc9MxBr7) z{by8F7fvghqAkhUA_>h&fuwI6Xl_D{`xj z@Tb$PMIb5sj;4R3@TQa5ZSqyS650aQLX&k3# z!em({PO-{ztE{rh^JJM+ZIv}#5|Yw!2JJcv0@jLCM+5@JSQ}hJAR*E2)*=Z*pKlF) zfi#tHp<`->Wy)T>3i&b3%M^@UVi}oh8JQ=`#7nJmzExgkm6yvh=?be{#3lKEaee{AJnCf%=yqF1p0$iT=NQ>l-^kORMv{$YJdR;B zuQ=+cE@h{6KchqMzE?l@$`upBXZB9STKWCE7kshS{OtPM3reOIPcEz+KVfQ3aS>Lx zuO}B5Rn^p1R+NhJq8c2l3d(Dy6&K9t+_7Lp>6FrdQHS$N~pU9HTrSNu6Y;J5(Y;kO5?1tEe*b{AE%?=u= z#?f{8#~8+;y^1T#tJ;;7?3kJq_~#$PNHls)C@rdOmz}*hF@T@O;+kodQ`(i67zyAk zYuc4mmloGfD@6t79(@9{Xw&uAuDEQuSX2#TJ#w~ZAIv)a9gP2pfpPVGCLd1f z*g35K<#fsJ*1l_YPId>qHXP2$&hFe9T|0N~(q6Wl(~KAfjFL;wz5IjHu77V$zU7Tg zLpNW)XInIuzXOXw8%HD`Y*5<+DTaZw7ys$Jse)*?jrXkCVUmNzociI&W^9b>*ULDp zm(HE~6(Fc=ngH$3>1VO0CNgyefzke)einafN>4V7MGf_{=79Pgf^jzTLKtu87L4?s;#_=FiUQ>Q81{orglu%&U~OKZr`qC%9LpMNVp?vXI7P#lua?j1Ud%2@XZsC)H~wD zACc?>jC}+e+IK|hx%l0T((2rb36<@N4N+2AV~BBOhB(9MV2GNMDMKquN)3^BF8QX=syU3hK@AEzuv4gJhtN?jBDBniqB`L(UAYbxvN@Y|2Y{7PY}Aohc+TQpMoXh5 zej=k^*@Ox7Q!BYh8am4rmca&dOu(g$J{cs3gCIHh>=fGBi(GovL zqdZ}y!s5z`+M=?G8W2L_qW{Uzet@)}!&#(m9kjEhc5~ypl&NJEwH?|Q)*8lC^lfhZ zkwS09C^^vgJiN={+TT-#_8m5HW(@^sM7ZkUVBEmyzek>Vnj3$jKl<{~Nrs{|9;#{L zeQq%n_u7h08);k4&UPhV!|cMbT4y>2!qAzvp~D(!Tfv5MI+G(CV)c4nCs z=&+qSY^M%F>kyV6Owc@Nr!}7d{Tp-4iO_$8Ja~gVI7#bpoYbGB>1S)ry`+OxE(de8 z4uhnAwWi-*YaS-`YhC&s_?OJ41%3T`Tj#t$C(4e_$c~GU9Tx<}%%GTVPktA3I>uU? z!$0MF{Ml>ve0{Wt8Ak?ep4!oD+k8r2fbCZZ;pNzwr~!r*M+zzbh0uzS8F!pWXz|@ zXp5iIGY*wAGT7v*ZVSnkA)12pmVJ|ZMizHDUG`@a+-SwZ+w>CX+s81RXz~Jij240U zK|2CJ*Gp(e0PPh(dzpCkBK6ZT&`{8yn zT(?Enx6-#bHp%9c4~LFv+E(H(TSxIIVOb#f$3hl}2hI*iVRDn|xuej;n=XMsl{%B?|hmlNdz z3>4cIG`CWq6h_m7tm{GkVc^((dQ%g->2iwfK4xf4@Pm9d1_cNd?&{+cF zb1i=IFH1IDNmi6To%z1c0-t?Z(ze4VKzy>-wYoLxoc{vmHX8nr=4`oW@;px8VAK(t#%t~`4dR99EA9JPy4-^)=~19 z88qlNiM&q%hC@JiZ2Mt=W7eOq=zJPyle&% z=2KL2={X>ejprJRU_w4Uz06AmJ+4I$dh&iG^$%LOIbceAt5SE+(5ihlB3DmhSzIE`Av_9v^-Yv{*|cN`CtI<9$J+&&=9V8c6;S=+r>M zHcG^}+JpZ0A5SH{5Pd89a&&LzYtcQKYjSSN>6&;%IFgNLRBMxeO5Ps+Ec|(RU--}P zZIO+UTca;TUqa_sqpw9@kG=uLZJDoR?#bMn`A}?o?2*`x*yFJ$V>`3+T>1RpwWW)WZKhwaSG39=xK)gul}0*KTEm?cP^3C{O9*sQXRbCpJz$mp{ z-+PKQ(ESwYKh_@mKl~I)k)TINZL_ZUJ7x8_-ktXBb$}G+=PR9QbGXFERu1rUkePH z|KP3x{+b)~l)|$KhdFAZF;yVSYyxzzriTLZDFGb?|L?l9e@I@SDZR}+1aC7>!5gsN z_PeiUW^cTEsyl(-?;byU&W5P_O-_P*cay>Iap*<6$=8?O*EHw%G_lPu~2?Cvv)FckCcPlGFHARJbVM zTt$6Z82GQRqNahu{#-@v6^0Ss&#S0kv)w$Ls~+ttYVvNw_^qLS+EvsKg@#e`X9M=M ztEgr0?TiBVl>WbV74?7P1ysBLy=$lK!vqfSbV{o!%q97dC5=Rk2~?rPg`B(&+v4%%qAZh)}=?^vzq;t(CM91n>?{@daGdv zW>Q&tZ0#RUoO)6J@4h_klWy<4@JFy!d6uuJ%S+3Pt7aC~uzN`bnUCLibLOz?dbGK1 z^i98<*XkdCMiDW6R-bJiyS(J_OMVt7Lu{%24> z(b8WD{SiTPF$2HB`i$|bihZEN?kfNg>J1Y zN$VYa_NeY8s4C476BvEiqT&OP8_Qlk&b)J?+m zvZb~>CD1Q5(DEEzE#A{5q}VM&~hTH+Cvs=bZAg4_Gr{KZ;O{l z@lNA7*PwMSO@)W_t|7gTafqw?5!atbv0h*zhPw<(h|wNTY2`rcTGG0UKI3-fQHF6O zX(a{fptadGlpY=pww%-s%E8O0N9#`h4Kh!-H1)|R%@w5iUVFTxVk%X5sTgxFYZlk{ zv>g<$BgOkW;^lO_C1%A$dosRoE9zsC>Pk|r>Wr6UWPwtpF^|G;GXPF}!gYb#^`sUV zikInl=c)20IX%!aOIOqBkm4#*G*8FNuo!L?G1LSk94Yo>#fo|Zc84BT&NS-I7>1Xu z;|(KKPQ9f!*rlhBNSdojv-@zoJPyq?mu7dY=R9pfy*1 zfjv=I)5jylHKh1=0bV|IDaN39j;^Rr1u3p2#YOm-d)IZ8= zb33U$NotdzrjBOh=*RfJ{d!#O=P=%K8ZYHhyj%*k7FKwZbu~P{x9&UA1AO@rb8_`j z3h*XUeMlRz%26#UDY5k0J7AuM-YOb0^cY?~fL_QN@|Q8{o-Xd^+MkS(V z0lrUaX=kbXxxc&B=)tD_VR2HrgM6I611~)_rN7)tx#i_9rTa*!<>Po6uPGT6m=zEl z955_i?H*FQh1BM0Y6t0Rm~;8)RZ?tCb@CH<*#Iqj!kg<_NKB5)`cA|V$mPY9 z%lDAhZfM!b)l%2OSmfb?K$E64*#^dXn8s@RBwhk%tFeyIwJ;XPWsP+>#=3&W+C*B% zLCYTNXk80qNgfND$kDoBv@JARm#6SDP8%(x>tQsDqcz?tT%fXdLl^+ir ziu?HUQVI*{tvKd3h6y5OG96R&BbZKggQ6sc(uZ@rb_3Kj#%PPlD zodAr(=q1z@vIw!rIPuy+;gXyd%09b-&tp2gBAI zV+ZoVkiU*|dQmw~OWm!u)gj7ijt)2(R!3=VFzZb5QD_^XwRP6oS{X^Hc&`^n$a!yD ztsf6a|v^(&M1 z;nqh3Je&xL#$F!rbTwj*espLF>(f%$Puj8Y4?)#wJJtYw$LfT}XPk&fN!1+b!XOMCUq>DkkLQ%qjITKB|y_3GBE8}>aTA+c#V zVq_+jw=t#{9gvF=)|&_`sf9;QIQMkaA*wa{zs(p%D-7-Rygb@S`rRX8?01RE z)KHjuhfNhJQyuijDfXSzwn9oW{u=M#D=h77sK5L&7KJ%(>Y7~qdIW)gR z`|Q4*JC5OFQ~$m=$oyj)Y+@uGjCZN=2LX$XIwlgEkHIFX18&d8^|o&fJBf5KI)BO_ z_vr`49L%h9P<-7;O2%!eI8)ZmG{;g$So#c>nj51>)|S^Gj^fT8XIRNYLEx{ck*`SR z=+`tyK(8;ID)A1o0<4N{Rz18bSJD9zc}r_EO{GKUE%uqHQrYj_S3mNdgaOV-nO0Od z1^EDts)H<#c4<2=rq%kef2Xkox-<{)d#r74l+%jD!OiRriv~K7B~UnGt?>`I@|Q@ zQeIY7W6cSjiSd`ThMqYT(d8|!Kno|(*ZA#ISO{Id2-BQSADf?Fi>v=~1bVi81gouI znbfcTdCI!a?_>()+?Q;%AZ2>-#3IHQfh$doK8l9En^9OpRTG_voa=}dXv{6sW{27#v2eX4XYK1Tllfgzy-Tk|06DE!4GwX|7E8Jo=m&DW2PEiu~n`hG!&7iYiNi`FwWU-Y>Np{-DB(=X97&^Ao9<>)aS zhPM8yP2YE$5H=j->9!konC|wG;UkZ_XU6s`t0}4}XQnG;&!pab5#)MXas^22V-gFU z9h}|UPS6b7s z{!nE#IbKLBut4b;TWJV)D6XoZ>v_91Xt#FZRy;N@9A8vjT~=BR)eO7wT|rlI#l@&g zx9grg!wRAhcl4@hue07KoM87z>`Ia1hz_+OcBSD}xupksR#lPxk#@&hJ?b`(B8#27 zW)r!wcFzr-wfA4WN;nKkF5@5OfCi@hpW=cDHg`a}o1&b7Nn!hq3B;g<$RXIe)~>(0f%=t>_tMiF z9fgJ(Mh+zkUFiwxH}?K|sz=?Zk?5zc@zDKOyZfMqo0hSk^3B8o+n4L?e33qGwCfi& zQ2!iXTj|STXqqt=kP(G7HKp?K^oc#w|8zkT@Z}`$i;vp< ze{G=tZs`*32B+J7J6p*m*>tk2PxP){md|@AMId*99k#-i4Yu^PrV|VH(3yC#t#Q;) zimGTD-k{LV^o1Q&A4Z`V)!GVIXbDLdeRzXgRt?Q3><$b6t-~L-Y3ck^w&G6>)Ngf; z5faaCTVZoU4R<<;NLPSx?iE{QQ-dwDoEGWUYqm;tLk&N&zcS(I;sbxpjq{w|R&uSk z?QF7Uz?rqz?Uq{`Y{^wEmbsm_(yCFEc65f4RNl867B|$ei>`m=5d$dzUr({qtF!`- z9cgV?qi&FGrb}auPm?Kak)LPzv|Tf?Yy#c{!b+8GrAj5F6~Icn>GDyw_edkUO8d}m zSs@Yh zV<*QeD?hM<-AOx#`m#%NW0AEJ$bPHr(QcGbimRp;T8F6@?50`D5o@=3!*1%O-&ArE zV};$^wejYb&f%V6e`foV)?MP}#$%R$DiP<|&ZSuQ zm8+^tCzN6>J?Z;pvbh-!(f|Kk{p{en+vr@^vY=Js=w##2yoALmSi2`LFqXcJG!EZJ zTADJzTGZ@Jtj-g=CIxF_+>~r|UzUOnXYrSdXj6T;$n!f-p2L*n1&V2y5)8B48KyKZ zFd??m9%cm%b1n}ZY4#Vc>N=rY ztOJ(W!2(frO>rq;4#PLFzDveJF5e}arw2F8Ss2Flys$Y0+ly&?PS`vR+e>Ksk}!~M zXGV2LLwiW}g4vm)@P9~eve-SJzLZth8G~?8B>D=fj|{529Tdq3Y8-+Z6BMI^Vx$vM zUo;_F8BvfT8lxiW0QZxPQ52OqS_VW>nImOD6qV)qne2H#7-P>#^yT?*SO9`S>@YS+ zhUca5yf`R|f}$`e&T^a|f!5fm`g9a4=glH`X-`L?^q!~VEb0BfPsaofDj$PzP$c>a z3SVrZpvH16*dQ4}l_RLhK~WYI=Q#*H43)9N*dQ66&w%ICg3ii^)-j;22CcDNeLAKo=gnGpX-`MB^q!}qN_zkA z(}9&q-~twpl|hl{E2uhHfFW8Vn|FDV5mX(5niUim2F3Z#bXu5T4Huig`h`v|im+Xman@^Ofi3 zJh+It;2nF8ay_<&j!u_^@yRzF3HXbww1U_WbaeJ~tiS>n7Q;NpLZYu&u7?E}x|&14 z2FZx!D#WrVC@y!VU=`}!fhd{fyIHfT`=kmu+DLi=qrxfU;&2KvisN|8F8#Y z9M=Zr@^|+BLElDn@7&j_P_U?*nvQ491DrQVtEY~VCZ=c0UIPEmMw^7Q&8OI1hNP9 z?m%coGwaespOf1TERNebj@MzG;~>#j93Q~~+<%MR#|FuWV;kbQCn)X?iaVW9K9*fS zk;SJd=ulMm4z5LeVbw?T9yu!ujD_KtNvq}E5T?Z#>pnxz*!@BG(ZW;|Y(+lo-K{W~ zcVZhCXnd4wkD&;b30p0UT{06n1q z>1krw;4|8G4?e$>ttY(s{DC&}am8l`^Z66C%!fo@eCTU+;6p!;!F)&tpBKRAxuDn` z6uTTmhsdtYWYHXj8_{zJiLOQ{hhEkYC8KBTrJ(!h_Oe1`T8f-QyCr94w9A803o`by zH=~wlGhb4SUSvjxqLvwv=!;PrEP&BbD3}q+VDu&!?G1`O4xn_|?^s#T+U;&Ydu42# zL+@yS!sr=$I}Xr03Xq;dmJQ~!$AeFVY`x>nCyF-nZN=v;=97t9=0l<{J~^-eK3OQ3 z56R&3Irw}U6dwo0hYq6lvTFxfbVT7s^eIBJbLcA#Q780_eHnBgjlWWeOiPh-=wr#5 z8GY!%s52S+%9~Law3%NjMqeH017Z$+iWE9MZWH9;xjP?b^w+^6wvR{8$ z3_#%qv`@yyIrOszXdrsVeu@M1vjU{&kY$7UeCxqy5ZU_Kn@=v<%%2pWADPc-sAWDR z`r#}poCO)A{&dIu|TT(M3#{1 zoX$;4krU_-37G&je*JEr*~XFegjCNn+nH!H1F6oL4L@ImKnqaI#7Oi-YyvF6&^aiW z7|9^kG`_m7|tvk?4!o3|IiI^H4A?l0oZ8&}x+`4s(Fbl>N?^#RVwbz*+&A zonOajz%E43*wLx(liV>1m}x0;ejO&M??17N$oetf#Acz*JX#Suiiur}S|&!KFJhO& z0*K8+!Nf=gv2+j%Ik>KnofgUBN)&EfAuYec8m_C*GnNsDE39zo`DNMIe_D&lc-WiP z6115aiq^4AYbk1(7Ky%S-3SYywE_jxA{n%@Ke4QtE~p? zCiIM*nCdLC;vnI9#0+Ec8k{O}Q^mkk(ci)LDq3UxQnj1vgH`Niu9ahS zQ+=QXkZ!8?$F_Y_eR*Ry)lcW3UdJFD6p6lq`Un;f)LR@2Hb_QLqYzYnsu-Rs@|=i1 zMiZjdZX4#Si1gVUE(4<3H1lLY+O4+H?D;1!#-5Yt%k%GH0S6E=VvOVb4`_8y$JxqxvjASwDTStEob;aW;*OEt^IhEf)6oIXI0AS|;ymdn;?RD^ zP#hYGzCue%XNNHz5cbJ zQSV-EHOF!k%yTRx`idnC3kV^|Az*`K#4;VROidLvP9PD~y91f30@0_S=D^~Z!Er=k zo#PXw@vuTzJ#k^3Plk*QOmP#pv zOObc6%M}K5A-3c18;&4jOTEvx`DinjsPpY&W;7DD%!ou^j0#}^XvU!6^DW6>v=WR~ zq>5`DK3Hu&gytp}eHvUP(upHj4$ zs}!H>nGgMTAM+v67oTca0G~-Hm=DR|vjKe8r;3|X#X1L3jqF-0i>WBwh}I({`z_Tb z4be38jBQMH?@5~!BGXdj9J*O@W=88g7)>W*o4gs#K%2QyF}jTz%|tCTBGDJ4OJMxZcw8>wOK^tLPbfFAmrH3YVT=mW}<- zuh+=<``)znpv`(Bs^84{6@$Owt_kO+nB zyRk8Jh#en_?X%u8h3Ug#nIUx(IuepcGI}eRfo=QaZt0;7v)AG+;_OT_gz9zlZgF3- z$0y&kcZKcO_r8gKJG8D1Mm3KQkw_C|MCtV(tEO)s!;nv0V<8IWM092JM#0~TN? z8wFD#8B{ugO8bz=4vBUl(KaO7gv1FBn3K^b);Sbw5t8pEV+5wX1}0kr(@q1^R)J}w zHcx1j5x-}4==8$SX6JfzWR0TJiRtu4XQo4`?w!26$ltI>~4Eu0gBQOZZMWU~` z%3uL;ox|Z^gJi^&kGRH##F&s69TFp*peCUe`-u#yEd@2sJE$?JoL|<{tfd#lflikM#$%tbj;+PN;B_T0BB+dzmvz<`pqC;#_ z+&(=)MPrtLxqW+QyqqJxy>pJr*R$ocG_X&*^K}8nGbh!{S6QR-wTyWzL}%tfqAwoH zVF4JfM8Ww=GI-R0$9W-984~3oG1-B!0W!A?j2Lc23^#Q8Sb+cUvj5m18G&p@AR9wsLrAO- ziJL=WofFF!=n%U-6#HAhoY|0oco7JIjoeXEc4t-x^JoEN?hdx=O z4t-mg$2aKAJV^A#<1bhMh96Pzp^s$nxDPz;4T-HGaaTy(;lTJCtzf0?WcMl(dVX$| zAo$RCmo~9?ND|ti?|u&C9~kC9Nc0s*N)ryGB?=CNWCZdA0@)D~kA}p-7P`z#O~52_Gw8% zo7fjQkajT4fsp7ckRGsrKsvDh*dQ5!>_s4ZLgLksc-e{KWHiOzjJr(PqXIEsg_rh} zzAPi5Ddl$zbOmBX+Q59$*&;zcjZ#PYqw z8zjTkFW~BDA@NB_eB^k07MfyT#qElpDTmEZw0ZmJ|H!-*VMz0^;i$=+AX;u;igOb4gQqY`0C zPE(k!MbB9CH20NMa+((JKz4ml77w9tBMNJXT5E{5qi5{6xO{5ujmWaWh>q3LDa`}d!(_L$ zH?Bv}W*(<-WiqZuQOmeU^o8qPSOBiqP%ti%f$KEj8k8mmq=|lMqK`xDJ=yzxS$u%P zO>7XNqU!?M1BYtFK19#hkTmxt?@&d|v=n&{93ZhXvVIz}J|4(EBEv(yk$sFdbBIDV zn2~*gT1G~qFJwQ!0+4-$f{~F7WM=@`s5FtECWbq_ew1B*lEu#`+`LA~P}WDP$s5@*Xfw+cvWbi=1+|QfL|@2S!vc_{qhMqt16eJQRi}xnG*RL3 zipj3W%i;tSZeG~vTF zvH>U<8OcDl1jw#R6N}Qs#vKhNE!vx=M!18FsbCYXo}6mc{Y9TJh2|%(B6_ z7HPOH_rR4;cCYrvH4<&+GKFg?;~Irp#zmqpT*a^eT;otME|P(3EpXkKCT>U**Qbf= z9AYK1cd0BUpl}nr5mDJ0cC$uoB6`MdN^?K!xLFZ1Ek(|-8zgo{cD;t|IuB%%$neeH z$R?xByh$Nj$H=CjmXVR@3)xIq0J8H?Ffx*X>@>Xn*_uk&Ts3uJL23OBFK zK!E2u3yeA8*qs`$S?C$NBaYXdikF^YmJPCXG8WIp*k{qr#G!j&}QDD zXx+}VW}}vAk?4!o5?BDO`6!qc$)NQJ5^Q^#crZ}di>pz%nQhl{ zY=_3|8uW}kmgas)xI-~BEk(|;2elkCwH&)o+rHN$->#)Wc6bw9jyCf#MetE3xB|6I zkVIbu*TVt`-hhG$k_>{+gW$7i;+ZtDGfh0@;Ja1!-XM$HP`L3uD~Xj~Cj0G>#p5X4-1Z_K`_T4|#_b98jJ=)azLoZl;$~WkoOXL8d;&Mb z-YK6X1Mhf4c?xaj+X~8C4CQImG87VhL3tS#0OeT}425Js`3O)xaEQDjJH0B4*HE~L ze4u60ry7wx=o$MYj>xBqh@MH74HuBtN&i!CAbZhfexiVU%s}2iEdwFZ7m!b20YKhG z!9Yj`kZ%Fx>ooC|!{k%h?=x9^j>664Yb{H@*O+{Pp0Ryt?i+XCD<-C;$XW80N0xj^ z2EO-(@)g?5eG1BV4COzlWhf;2g7OP20LnfT425Js`4v!pc8L5cJN+h$-%+@U{H$fk z9~zNA&@=XX9Fad15j{&R8?G$*ll1@a2J#o$%-sAV7|`T|mXFasHff`O0> zAV;MS5J#ko!_&o~>7qrteN(Rlt+C{Ec>}W(-M~B|UEP^GJY617=rc}-V%z$RlYHKc zv$)wpRbrj8?G3N(b#yw-(zzIoqa)E*bhWSmLsK{?Y>?Iu(o|^r%%!5*{@_ZA+O{4fWU%McV2nK{(U<3QVF3@YS+hUY!u`6=n5N4n^iF1n7ut2;#270 z4l!2?aiA7re-(?_SB2PHReOY3FAIlopt~?C2TG!^K=;4`;(MOs!v@I+G#`NuPZxRV zVyF}1>$2-!S-gS5ePS4nfalSBpLyZf=ydf=<4yF8jY@YPUPfzlEJZ$5=1B~k!9&%y zb8+<+85^CBq_6+z=WVo^qtcz{7$cd{JE&zwB>H0X1uOu~hbZ_gK{6Pf4Mqj&Vw?l$ zOWE%$S^Niu8&H8Y#k43vkp}2%^o*So2dGE^()V!72J;!`!RH&YRpia*TeO+yC_aVE z=R4Fg9}<1>`3n}n=O+}*hh*@X0zQ+{#l&oS?Ry97-T#mEMdJ(PmaCM&-;X3AN0KL|=?r!2%dHN5PCp z2BYapeCC7CymT=qU0jkbE_Nujk-blpMOzeZ zO7jqvoko{wl-i+ZY+*W1RoiitFzR~HmCj{~l4&V&8qHB?%uD2fnjf!Ttm>VV$|l2? zc_Yg~o4HUSTfoTLqn448=nGj-SOBsvC>R;ZKz22dEln4T)5VnzuU@iiZ&~y~;pVke zhQwL5T;tUbJ!99#@mj8U=~-pj;H+A#;kwcT*8sA++#AKWN z8WwCKeIc6!3qUp=1tTLF z$nFBNJJQ9Lbg{|dHCc9@B8zeqZeDlDkT}Ec(Rfv$XKZU6uX_|PJ;N*;oMBruT$?;_ zRg&F%ym3{b&D^SR-OaepLoMSX@j!76qXnYpVrc;sw73rAA{n^4XABTsGeqYM(J@1` z&#>Q3(gHNGP=-vCUUVSpnxWoJcFvIbMHj^#vHcibAa4(w?XhjIWzpyY(LFNAmrF4S z2SuWD=|QLlk6)aT#Ka zL|>l23kz^~4?Bzv zlHvJz@VqiZlxK*^j_2>8$-Q4!D$mVwxQMx+7jv?5z5bVt1N9db;aJ{>d5)#pZ!BNI z0z&whL%;^fh-ErrnVKPLoIw7AdUqgGRUrBl)ErnGGdPZ~VV&b3(bt^(1`BY1AG?nY zk`YH8;+T~oF3b?;JE8oJCil)gONC-ysLjdw2NugE9Lpat&#{o`E0(7C8Y)5vpx~1s z$%y4r#412rLz}rK!?|g7BQxrbT4qF|FGl@g0cdE=9^U^*2BX`+=++EzivwtY>^D#rgHX5u z-6~^SU_2I%ZPozgqGxPV9H7k#ke()%4L+mY;=$)MvbEWp&tSBfn-rgo%x4H{nGcD+ z_?!(3;4>Np^C2009s-{SGQ|BEVw;1A*2qCuZAlzAq6ZL?{a)}94H2!H6MHzreRO+7 zAu=sR&Y}AyXJ)j`gAp&R^N2SiS}4bSSTWkpj7m|zYcZUs!RW~h z@wfx11|0yX!If~Hl(BIRJ);4d2EEv>I6%)RKza^YHki-j9(;HqoM*iG@IpAd6rY{U z$5{x6L|=TY1#X;$a7acDy#_w7WQdnC#0w50Z4n%hq7`o3IrIubvU6y!hUjua^m>N- zXuMY;GA%{Up_e3QX7qvwBU zi(`JM_8Xh9t2L!vJ}n_vNaZbrd;NCuz(fX|m1;&X@3zpZ}rCE~FY=v$2suYU7Q z+;RF_#mBT1Ie|WxkO@%Z*YEacU3mGMZ@r1}@;BcoVqY_{yKQ15`Xcs_B(}{aMly)~ z1Y$opxU4mD9+rJ+2^@Di{h+1OuNp2|B`5Yv9Ijs#E;>7+S}BLt!f^xpN6W7yx*28t zlE%yE8A}YiPjX3NbtlVGUK=X@M;fW=MLB0N!6Ro>rCWf6Wr-U#CN(<&NF%o?d z`v4YT=q(gXjARgN24YRa_T9S=Wv7p1@i7WFuBKs13p@setk;DTX@s@3~gqzqSc&feU4hDMWQcSKfwZMeS?B&kqlZ#gVvE@(aHh#v+Vba zEPh4d26iNX*~hP-2JAQVjHQI#C%~WrW?G7zU#%qd{U`Q2Sr2*>`vYxeiXwIl6Z;dj zOpHWd#16t2-$BgauiayVWDv^$v2+L5!Ln0RSsa4GjVoQtuc(Hr8G6Pdak!!im!4mi zjs2(9oQy}kX(gl0j3`=Rrqu$qOp8Qcv`&BpK*~VD`9(5lbqB4kVbM7(I)+7i2U`|e zV>w~{rn-vV>}=&2-&D5%@=bMY+c(u4{bW`T4yr8%;h;$L6;xMPKv2$FQY0g&J_xE; zSezObCp!^!qlmg&5y_kCDk6P0Pn7}DY?>#_fVA6&ecAKww&x`J@_eB5{8V-rA&?Bu zhr;v0VUZga1H+=f&=Y6y|geZ7_!7 zNg>f!Xyaf35z(4aoM|K@v{48xKP-laMV=GanP@`H+P&O-6_-9K!(~`JDS0w1ZBjy)14;;XePKFK31C8(yrPe>b3KY*yHvnHMVx zrlrWc*bIfioQCcA`-ZoXv5URWx3t)nIZK^yFJeZUP|J)+^u=f!EC7wO1Q*F*G#`xS zg~c2P(0#Js{j#8?xZHr|$=LV;_%aO;Ev^;AcdlKhw96DAJxwedeDs{-!RJA;b(uGx zhtOs&RD2dNpY5n+J|z0$vkMl$=P?w#Uy}?z*MQHmuviinS2>8DkzIGo;#m}KM9UD8 zeaX8*L-ZVa#+HZOd(sMp$g~tWhn7gr%;+i)MznrcY=t+Y7tm%dSB$P@MlYh48IkCV z(L1mJMte{&Ba*>r4H&Hsi&YLFT9OO>-jl`qDBOTn%h))FZqfjKfS$2+ae!`8fb<-) zY%rfy9(+C|TUbHV>mBAtXfxL-K5LoJ$EamKB>LjB4;B#jmnfJI$>6gYd^U!~28Yl0 zvfmG~par|!d^RE;JAv-d`22*PvD@SJu{#tW(^BLF+8`klpvKSh_C24U$@(4M#C}1W zdAlOEg^B%&S|&!KFJcKznAo2%#KcGjv3o&mtAi_1c1n^(6BKS-TeWn$U&D0}ddBXH z!*##HrKgi+WB+L#Ovdl`rqvW}=6#CRHl}q5YMB;^zGxi@3&^h)D3}(>p!FDNJrWk% z9biYven-pV7!+<`k7)Vzga(WjT8lj%xBoq%fSHye=hyZF&95L?f5MwsD%#A)6|o&m zEQDGnMxrlb$HM}MMNlv?l0obl5ZmeCIze{Il0_R7Zd^OH{CZBqbs~Dko{huxoWiB& zmt|xB^NSXFi#_K}i|N_E(?I%g*kKWMldxq(9?9sfU^2GtkGnOC&_{0R3m#@uRPQ9J z-|g=L(X|-WJTel$K(wq;3w|9DpGv^SAzNpa3Q!sQs3Z_CbsHB5RC?bLpaZE%U z zR@SJg&0-=qqcamB(HD`sVF5&F!6_y}GKh2pk@gXh9TDv!qOC(@D_Y%C+g{-?vk|QQ z9=o07L31m=kH$0GR^rfRwiCy35A1RrB>IZuF<3wxa-k_~kc>D^K^#3IqFY3Cae~-^ zCU+1$R1kW8cJqv(OT8FQxm7%}8V#K4H?9}#^cqPG*t zE9ej#8i{?SAAE9EFy=t`N|#Y|@aZq3;rmd1RfhJK;WTjYaj#_kI>s}H*2_&B8El8=?;u9&5_z&oM&(#U&1g4LZYug67h9j1VW2DaUdikkYWT<6cL3HaaKf}84+WhSd!2o zRvL*NY=y&Tl_C|6SqNY4i9Jik!xMX^n%J>2oc)^ErWnsGtv9iZnFoo! zcpL)@;L#EV^B@^KD!^k(L`;f^i4ifufk8_-ft5C~Qxpk(Vkb!uJh2nCiJc%xXcJq> zfdpZg10m5@AhduJ0y&ob#|Fs={hH=>aL>HB-ZaY^HO;e_&PnLZbV&3?=Tuk# zl#UDq8zh6yWuUVlA})=Hxe+ltBI+D8ya>}p)=Up4E(;VFeWov!Sa_!AYBN1s+pd#f zv{}EL#YHO+AskwaiPKlENEBO+xUPwaWf8F?BCd*vMNV92q9>9Z9o?CPa3z^;<$%T;R` zqRVVoNrtO;!PPq=VoOA9a=fLbieg*iPAqpQhs`b8ylwhFGH=TudIy?R8Hmx6K{e>^-Vx&wN-O zKj_WoL#S@}&8GW$?|zJD?yNU;vPMna)6By}XXZhoFCMg55HLK9f~SsT@OTM4UWkb2 zB4T$$>~di2L@QWnmjy2<68Z!_rzX(ctsO{rNfO!#;$;qG7YuVCB>D=3mK8!E&$Iv7 zAQ^$Yi9q&7#GZ(F)rsPD*>$fh-az5L^RgFC(s7g)bA2bGKAiLxddA+4;EkFDa0VTD z-cbNdOOdqAJsN>mwW#g;p6`&ccOrmR|FcN%qRo6e;(QkAEoSr{YMBv<1qlBnRqZa5H3q;-Tn-Zdw2z)=vv=ljw{*b5{({I|2^os|wmSi{~ z>X}l9qRk9Mos=@7G{c9XmXVR@3t0v%z|b)$7#YbxmK+@*nngv^s5mHU-?j_Ot`S*8 zQMh?Ei&B*GLvDv^yfV=<)-sOQp^BHDRhA9L)ila?`}iivL9mS@Fduj9J@7cPd#E?A z)@UWG4IkqlgEz?B*mDN%8BR2=CLJ5~1XDT`hx+{985 zm7QT38nNE!89O%Wegl`Gh?$lmXIP5F&d83|kR9oPtPdH^@J7}bZRW8GSvn)@hgwEP zqAz5_VFAc;Q7|%+fh-Hij*p7gQIYBJ8X>#p%VH!7H?QMmsC?XNtMM9zp0N|-c(ql$ z^bE6XFs{}bu1pVHqseYtZ(L`f%{)=zYQwn3pq6ow=nK~bSOBiGP%ti%fvX#Eb%}~j zQPCkPavWl`EEsxEltmc|H?b~=%FeKpHDZ&|Gu9*OzNL4vB4%2OoMD|Lc1G4gLzd%# ztegy=?2W7fZDtRJtUDvCL@gsD(HFA$umA`bqhMqt1K9u|>lYP$qN10>ix%oa*M+jU z427FlKN%`#SgywFa`cQ1isG)fymS~xmkzlaFH4ab_0bsh@?dlY8O!x%v0bf+4TlltVZExG+bjeT4Qu0dd5aY z@rXlXG+JY1DKeuxjnPmKMr+8}Xm3Vq(PoZPj7Bn}b*N=VB>G}x!U7oGiGmrC3`SL8 zR1p|ruoz+Kz2b?%#4cZ4zK5B z*B4~*A__OJ3uLIg>(yzzUP8~<#c{mq6fgbYZrNa5Gc{b(J#f8DcI&)xy@EFLVufoK z<9ZdfjEh8HxITgfP@>h+IKxN=uB(7+QB+(W6$_(cepJkJpnWVAK9R+zDBRE%Auv11 zmTJ&GL(kZfsQU)mQU%Sl6gkN*m*kn+LXFydZF`;v!Ov-srQQU;K%2Ql5nRj!X-zaH zNTM%-zrq3t(&A-IkYo^C4T7tpVr5jUh>B|+e80)wzsuqe6mER0WaON4Yc+g-qGxPP z9KN**pPqA;4W_qJBep`@zSe`@Uo^&AZ+f&anz=^NyOHVrgIcCXqAz+4tUI<5^fpAr zdWYM;tvj{>@z`m%MdQZnj%|**@9k|-+)PW6({85 zEH*}>FDRK<>IW&6j)GH)WTezqK)K5ya-8hcS{5-B?o7H%%cN}@k>k-bc5fV!ZHkDV zNtO*4kP}FMn>P?z70tX?0l9~P&}wL$B_#R+(g_v-gqBBRAS46GBLK2JDjsy0be8>S z$uV^Aio(rgyOt$8G$!59Gxk{2eJ62;Vq#i~oFxx>WJz~2u)`Zl544$&DJYLJl#@}* zP)PIzg%&A8l(cplLm?SZb^^*%4v~Sf6D?1MzPTveM4r;JWVc4-H1v!;6U7}@dFgZ( zU0&|ih**lQ)EG=kyS*t4L7VxEqOgl8&}wH)fka;vCc*+DD@4H*NCt(ELE*!wct0xM zjf%G&9A#*Yy%m))okKBwsKxZYl^*n<{ap(TJ?_9A*MImkK5wf^k3~@VwyRv{^%IVc zRvY8!Nc0um3|K&Pv?3TsM>3-O8qs|f6<CWTN%ZCUd{}_zv)Ey5kPOd%h37v<#g9?(eN=qsIKKd`?s@rHIdA?5 zFX`Y;^YXo#0yQt+sY;J|srQYX-#Et0F($`IqOTZN!2&|NnnS||$%rwKiSMpP#a~hJ zhZEopXhQJX?EIqw)Mw`}H6!L9YTKHfgiIQ6HH@+6B>M9FURZ#kE$lEhNQURl;Ca(b zaZsj6%Cv8?ZIfN^lg0fg+((e6nd;2jB2(RzG|@Aboas)<7Mbd%q@~Em)PrCIcj`DN zlhn3z7Jh(?wV)qEt$%O(LA064na+*K=FI3J)G{LyeKC3(7J%ka6uj?|3`R$R(Gi*A za0k#%*>9IDoV=K)ca1c1#?g6a`4n3d;ubIoyNKvt%p9o6mD-GmlYx zj%Gg3qn7!Q=!?&rumCyYJ#X!MONCuQs0HsH!=$0wEWQtA>nr5p?z2iS4UMfxXO(UiU;4IfmrTCP&+EFYYLD}Ze9VgD z&R|S&D;lnsH^?KaJa3gie??U9YzRgV2Ust*l%mN(A6Xfq2G&NCTjKh!c# z5`Ezu1`EJB2nFLL892`c&eBX#oGFSNmcwP&5wgff;bvKC#Y;IkNn<$*J!55YEGH?J zdQRFlC?|^*%Ax~BIhMwpUcB5BC?B9BmQ&d9_pZtehUk7k+M zvNp__L(jtJBpcz>RL&Ul(JW|ndpe6Itl4qf7tHxF*{GX`Q_2uBcQkj3O-$K7``|>Q zZa&oy<_2e+kx5z59+{XI=x9EG5f)k_WOUn=WtjJ~vzE`%t~;}gEL7(OI+4endG5Cu zhS7_hA_)s}_O7+G=vYg2_+mHer1!YioRd5R2j8yn_wg*(h)zt8b4<_t7cn)-g7(Oy zyg)Y$^JJDgj7*!|lRVDu2F8gt#4f7XHOYcDjdQXaYF^+JOde?E1x{s1o9jVRv}8i? zn^idhfOJ_T9#~IC=?tA0=*5{znc^o?bMpdyX%2G%=v8Fu%UR;ZEb)Anc-GF;)6AD$ znfew*GnjNZwX95ijcSJ?SZ>aPwLMwpvtF6HhiSjv0PTOvRE&d6g*IjCFbuOd%Y0Ew zS0{P)@-XlGSHnP?h8d1w-pn$em-~RE;Uv$SJkGlfjPq~FBg26BW6__S`eOHG%K*Z zj<)wD59!UlyVtO;dwfV}9a2Q|8RD1`trJ<(668lWzzxZ5tCjvBD7PLwnoopPMmv9Q! zqdy`q(286=0&Wf-J3!=(vwS=FyPw|w zf1aO5@9fMubIyC-IXgQ$yZ2^j0b?;~e!qr6y@nMi?ehwFW4{KqD>b%9qdv3%hoqPo z+ate##eS)tQ?PIj?b*+|@chg1cg)&xtq!OwtTDJ9h6uIb%V*Eo$gVX?((E=~TuQ?J zao-SFUS;%!DfA7`5AFqw?E!<%#7N0h$mR3r{9-5*^c*!xk}A!l(UP<|$jc;Y3xsg5 z2q6)cVwjF(#DSXu_*f2%tl*T>ncmjpR8C}E73_SPS)yVX|2b`sxcrc8xXp@ zC(XW~1~J65#2Qi%P-0!4qxvYZuzK=kBe8~?iPcUYE)t_TtL>T35rO%{Vyy%Dq{Z4W z_`I$_D=g4Pnw~piNe0QN0)1o?1c}Hywm9fjiqt7VijQJ>uXY0+gW97}A5}nWoO0qKf@iA=wwlY{8bYdowYwUi9QDP0*3bRLMhy(xd{ftzq5WFVtO)8 zvVk?7)YG6EfvR2kS=NnFT^tzIJ=ubfFUJZ%^_T*!%;dS3UMBeE=bS! zD0CPAl%Z_hmZJ^@lnH<`&BT$XPZJbSdhdu$+}vh+Y|3n+{s!`!&-~J10Ded0sMit& zBjC3NerFVDH=3?T>Nhr}z-r*98qFykaF#3nwCFR?vB`N_C|PTMo))nn8UqWWI7hvn zf+$81zm3SyW|yd&0c)-at6ZP!3QLV);P__~Sn~5elE64@bEd;BE!J@+eVAbcSbp)#( zu+9RkB_^x}eTjh8Y))K8ekU`(bQpl&={f2&@;e=VL*aL2fwtUqeS^LnuAdas@h`3P zmC`lfM&@^QV18%js58j#O!#dLzqguB8ym5F({Gg=)2cKPSA-N=T=lx0LT;P|CFY*0 z0fgN+7Y1Nw4hn+7>VR?~psX#>)(AB72+f)%X!NxOz>;&AeKcO%R&Azjy_5>r2DvhE$Gk;XrYxM7qV(Fpcv%cB#tT&g;bkcdAf_b@0uHDS zERn#nxj@?};4DMCzR{1DW3BYf1;CPo|B097P+?f^4iL*K7=WFX3<3_Q4lEk5Y%kEZ z3M{M9?%P$MZv`CrCW&seucA5md|HhsQ7RLz+n}!R63~r{1g#;BTc*a_{WXkr*LErQ z8}G1GjEnP5HUMkU&Vr_DAOo--1^{v$3YM5uN6_sM^xgt(w+Q+!wEONY(04ZpT552; zb_zN+z)-VJoo8EXTeiia-|I%$X0l;v7=-PW3EKh{M$EndiJ^TI5JTH8j2NnenC>9v zK!LVj5JS5pz6T2Q{Y{8*$cCLz*B`J6&SPf7E`JSvo2(y@rvTc(G>jP8aFAsK?f$Z$ zsTxQ&&@Kal-iLw(O?3pFgrM~T?T`q1KiYi{7wCtY1T8iEvuwBzhMINq%ZB?&<6$?# z4*F{tgy}M24?u+x^N=4gLF%fo7)4djRnPUb^sEjm&Z()dsIIEZtFNvt8C$L_^e7?0 zO5Cks%2`3`8cFpIC)Kq~H7}f7Rn^>Zr8uQ_?BI&JdIf(XA_#wIR#h5n&Qjnt8?wRG zr6m*LNQllppG1Qp%BZfbERlPi&qM#O!9)K(qo=3QN9`0;D-_`sW zVZPMGdty>mT$|2`6Vvq7rWZHL)f^@#l~vL93ZZAHNQcaU*}?e zt*eb4!p2q?8(ScAfVj!k{5`__ZWr@AU2Pl^Htu(Zai5b3RlOG?hj~Ty9ENacd0oTA zdS$+_Wx60@7Q~eowgheb3(S`|f^E3cp`K(SeH3AabDM6NntC zI0c~%6=d*fbr<5vjdmqXDZ zs025^SK9mS;O@7x@SEsnyoOMIQzZL&F?yUzw6!o?i7BvLD6AE?uN+WG~W!7BNe+Kw4q`* znq8>4UqIUL?027=--GskA8_}3RQNptMF%P#g2j`_xqT;-)Dv2r`(Jmw>SQr zyYV-K@mHbf5Y)?Veoxr@ebe3V2g2{WZpJ^fH~x{kabKjlY>JEYOC`VSR$Is%0*-;m zb`(`L8lrv;W5$%%rdBspVXwnu?vS))dmWKNF70*1vb_$~b2)@f6TUGHLR|8?3eZW= zlJegVbRuL9pgTh30J;N2StV2L5nlnJTSV=I+$N%K5IRNFPejxgT22vN1DONt-Viy$ z?g^nA?CwI|3^v#<64(l$=Y(wpWX-Szv2h+Q%r{{*PF3@TOmaO58))nzS|MDIadBM+ znZrPjhNu}TzSA~Jcy5BKk!R=iLM|aQvvWLzPGeawKu>~}6JOPkIUuVPp6!uM5b|co zFkG{Q`x!3oZ-mT&v*{2yAe$;Y+asGSZ?RmXj$nALDE8OpLalZpH2VS>9x z*@Hsf44LYA3PLB&UKXHVfR+{;R29@*1E-V7Nydt10a;o|;v$Q(F(6(U+Xh8VR8dt^zc>;2I}zl|#{i%2J3NAeTVoMrE;(+d!^>&<65&G`m1<5Rhx3=zyz6 z__e39O2}<+O@`10*Az6n;F>3J&4!`_m5mTNK%N1S8L&zjd{FYMn?1Rt-)4gbR!E{t$Is!!p8XtnF8C-s^ zsYB#=cYX*$H;xYqxfG9iBYF%%n|K~Wvr9ZLiFlreq66sT5IKT=20}N`PYJmV=$9e1 z0sRV^T|mDpK)(e=he0?2k!?J*#C*@*@B8k4KNEgGb~FCDz40&Hjh`0AzlEYhP+zi{MvK>Xd%moooJSnm0 zEMpr+F~W0{i{}VC^L%0nvolX3X8sCc{&E-d36MDi7H8*~&k=3yJd40O3(tuzo;y05 z@8D`aS(v}Z#e8qb90KdnxKq_+fTj1t*l)c{) zcfXaw?|3LW48%By90pZyXzhKg!5yHGJzKx%OITj%C?n!VrY?tT{vzw@Bz zK*b!09H^KDk=uoJrjR$wN!7CmLK~`XMzaf5w+hHBq3D2Xx$tX$t}GRD8(gfa4{|Y|37JD+{hd9hyLuijJm1?{0g)d))mV5q=+pqQi(BhR9)xeE=dyDjtE*hKfhg>_Wve0@9Pt zejj)9`>eg+2*0mE(SeFrAabDMC5RlUcoRY!D&9h~3l$#=NFO-+eb3GBC-#0n zb@%(N@Oui14pe*vku4Rpq4Ax)-|yZ1{wnm8~1q4mBtw;It2BXo8KU> z?H~rD*<}zzh2Ib;Ix^PE-uSuh#xE7dFM^^&P;K1&hS~cKclYZRexu!tx3xDO>u$Wa zFy6yo(SJ<{nM1%`AhIP|Rg)lcI7?|wC_E>-c<$qD{%TkA*~0uF7xS5rIRw_<*>k$9 z=i$P0o{Q%p&gOGm%@+&vMK0zGAae+8gp+5sbSf9-N4uCG(b$&2#oU$Ib5|d%rik z`@K#0T?Ivl5m^C|!)d+@B1bB2htP(KHE4FBVv~S$m$Tn>Zhkl0``zO1cdzif3yKa@ z?10FY3c48IWAAsLyWa~8!qVf;}jIs|pZ&F|y(exGpn`<(FmjGOW2 z?Tx?SZv4Ww<_hEdwtlJPcin0YnM1&>AhI1rRXqnHw=JU(A(ysh24EY665t{Tn`J{R}#&hBG{d3*O>A#dhh^;`j= z6ER%{vLt9Z5t9g+!)SJd$bqvC5H;IY=A#8p`UuaxT|D=6Hs9UV{9s`|)5Uy$$Q%Mo zclMkrJll^(ijdokMizulqj9YOoewRi(HIJu1Le8GvpuqGA#a8ZLsBN(m$mYJKRwz8%BO58?&5)^{atNI`s}`UqLd%J>@sK$n8z(&5BO4>+&5(h!8N&SyF7Bs6 z=D^t$h#ZhLK;-xeKpli`bLAu<3_L;Cm$nCIg64>s7o)flpkU3<+T8M06)75P= zgia&2Q+VFy;`wf8^I-NqVPl_*jlGaLpx^CmUiBP+&~-ZW;TqkT=T;)$g@MpH@{!n`~Aw@uM%sn zY5#(v0~LQjS2P(rLa)5jZL~f8T5^@{JmqBO)IR?!xkgpJsFNdN7t_0!N{#=U_ zavNM%LTH1l1DaiM^%A(cL(zfCt`Ipu?hKI|m7Rp#26Ar*Z6IHbW*5l)1>`g+I^gOj z{Mu8QEaW!020&1m9TXivuZ74F^co1=K;I_h zHlQ~`Xajl^nq5He7NB=P(P0p_L1Y^bt#kL-``zpA_kQ7bznk%c_QoG@H-1zYKLSOE zpdNDbd(7VNWA1*R6@H&`Gk)CO_;c>YKNrS7@mKWQ5&H--hk!qT$aWM}^*xAq;z@}` zZ!59q9N!7gU%Pld>1_T>SM&c7=6`iD|1)F`f&J+0`LwHNPn@}mJmcc|FK6?AxS9_Y z=0oBf!Jh?@!>9y93aAl#{1y`ZKH3EtbR1Sy8 z0dhV>Zd48xavR7+5ZXY#4$Ur*#|g;gP;|gmD*W10St8^%xGEsD!8IPuF1Q|TAEN}R zL7u1DUxpvt4GMaim!4;g@>wc9LBYp)J@`3Ro~x?r!|m}*v$~1IOuU+AeKEA_P%RbwR)|K1*8WOOiLq;_zCkpe+81J{_Vm?3zZGzx7+zbT499%CkP?)B z$o)dRgY496gD||liHczFZee({VYr21I7L-AHt8i0?-Yi&H;;2`fl^tTX@5@dGA+`c zHhzVkEFz8e2^4#q+uQA8?_PU*2L-+Z&FR|jV($Tadk+bGdUJb+T~(GDl+@KPymreNZ(&Lh{!T!8ucDKi^e^wcr>Lx!VdaUaBQi8~g* zBW_jvJ#q8nPsJUK|0eF4_#fiFjh`F8Bz|N3f8uw>-@r z#O;qe9Cs}4@wg}Bo{l>n_k7$7aUaKh8uxkJmvJZKPQ`r__g&l%algmSjh~MJS`oi0 z{`UAg;_r-KAHM;^wIzNB25e9Kz480w55ymgKNNo?{#g7o7`*4>UyOe_{+0OG<4?rD zjp6(t{=@i><3El6JRYeN|8@Mg@u%Z|j{hb8Hw^h7@qfmjiJz4)H(`FlLJaE73AZFH zO<0a$U5x==ldv{n9fo&9!X^yx77XsTgdGXH680qAlW;Ev`u>CmFxWcM;0Ol%DAM4G zgr^do!N5P4@It~%39lr)hLm_S;q8QXkqGZ22|hw9e1`P+3Tg32!e0rEzJ~C$cs={e#rEG(QDYm`+6%YYt{Q&CGBetX}9}3#K#SIaZNAn4P+5tOdVd2wy)H zOJa7&bTD1ezn1tPf1`w8`TZjdS9MD2;g$Y%>Yms$sYha`#LiM94m%|#cI(y+Wm31E zomr1j=MaagQZ|3=;*ZOF{C%L+*0*49R661ZYwd2O%Qv|dHI zwbf&5ODeq?XsPqIo7$sW`=YFh(%R~}>M`}+;T3faB@?}Q^$lee)kR5(oq86fR##Rw zR8`bZD;l0!lwVyvv92g94~Lz)bWG~mv2$Xl&Yg=!S5y@ZsIIFY(W4u?!jvX;ESoqn z)_W0auc0%NdLR>+%2SBt=Uf0G+ISMZ@2=)cQ|Tw2X@SoYCVm8meG`AE%Ynm*BYi z|ME&|Vl1w!$L(^HD{EcH>e1ujr0oCFiR0y3E3d7suB|PvsjjW>Ra1)*u2(L|h>jTD zMLm5TSWiN(UKri@ScCF?GOG9&HvC-7R$*5t^x4<~D=d^(vd<2@Erho<*0ZwB`Y@!+ zwYcf2o>J!>R8e17)G4tjv#NArLs>ZvJ0^BaN=i&bS=3NkTVGUKjTx`D9&{jeic71j z##D^$I8HfVednd+H@uTO@Q={4UwXw~`OX(@)&*vG3bV{iKAPLTcj|TL{N?HTexDXk zY@X8Q&VOgpvUF_IA5ZkTDgE@RfuHw$|D`{|+f=p>DC)}c%F>!?#dQo`a8caj8}5$F zy`%RPJBM%iZBm;vff+@_bo13UaG!r})oTxw2oM!&S2^vrbFt-@|pMOoiY4OMjwHFV;Xm-X#hQd>F>+aIO%4YdZgj@(#k z7{@kA80(jt+;4E|!2SbqU>fT>uB57LV!0o-0V&yOgVQB=G2CLBVX@A#I50VTaArzc zN=mwAv9xZSpSje$0g|n7ZtKlUIJySQ*5KrfL1}~gXJ!nvY*k{&{ETJgq{+yd5I4oL zmYbZG(=RI}dtkO@t(yJ)F+Y1bx%rtn*%H1cu}%{fQ!|q@GP3&(NXv%l^7@jBiFL$2 z;5Ag0Oh&b2v_Fr=aJ1tAryJzmAPlArN=_Y+KB)ho?DXWcX;mea6{S|HRF+iXPo!0r zS0ROP^{T2cto7p7G7M`sS=Mrr)3OJorR8MyOHQkxAN^*1Q*tx=cAZ>aTZawNzFkL` z*H0-g$3dxKt`9fY-!M1RGMAn_AZ_r#oWbdt;BO53V`a3axJFp)nw6cJH7F-NH@R<@ z(bMY9>Fg}7f6SPU5{k^}uv@?M%+!G?g9arhP6bUFiAhrp7cF_0qed5>=+YxMH6uMe zbKv0QzKMOiHtlvc@AfF`*5;b9z}E+CO?1ARJG{@04c#&--g>y#~ z{E2v{q1U^zj6(yX8p)pS`Z zu|rN*Q_s*2_&ACyXS|p^ZOdg?};Yr#8SH{m!>-uTJQ7 z8}-`X5g$u0R+NjVSFpMSy>vfUa(LtnU&B)x&+3GaFL2GXK!&2{D}FuY!Ka@1rk>LH zVG=$fFqBr$%h8j5CwX#RY4i9xqT?OZ@o*P>;E!PPjzQ*N&~Fq=9c7=?buD$R>4uM1 z$O7h*btRv%_>CJ-+BD(1quZU-t!)-QrXxo)?M0XdxKujMma7w+J!rVgr^6K&NEBaYy zKJ|;i+siofoAELb{_duJBWB~{jceo+|7-N4@12Q$VjdldUR$YG)f{}>+((>CF>Te> zUE3;6dU%ya>amS_bf1flv->Ja0#6jo667a^`Dq4kIJ#}8ZkhA&u?5|Xla?Hfko(AF zP*C`uDdL%rj~kQaGw*jetC2g(V@4f!QpbB1;^W>Fx#LCfc(cq#vFtJzJ$F&h1vlg4 zvwrd{*b+VIOBXn2n+2GMe!HpPuqF8TE=@jRi5L3fg4IvPN_Y%RLF} zQ~o{0*cGAQUg{UI93Q?6MQKeV;lXz#)Yh;01t?F}L=C>4i-#iAZ9KYJvl#*X0q;Fc zu4|gkqtR<0^-9}@k99a@t+f0qR&Ct^uOOJcWICzez0~i$?f7UID$gs_uXP-9j616n zk(Hyrwb^uAhkstl4XQaT32i=qw(ac1+K_S;~dP&+vs|rJcy6?3Xor; zhzzB5A=5YR(v;aA>{dWyF7&sP{x_tbfVrd{>8t9XLQm^z)&+N}Rn-g=b(n_^JE+65 zhw(819nNDNl-9M}0sc@iZKJR?5p`IA4m+vC_#^n(gANI-!}%43o(YAX%0f?dp=VN| zr>@Y`Q0SRb=$TgNxuMW=Q=w;Op=Va1XHKDKUZH0J;EZMts%y%t1e!%KzKe`6I*N}{ z%xE`_BZfjk3e>X;Jm(asp#`2+1?ts>o`Hqx8W<^OMoK4E*Odz^i(zFqS=sgkKH6WW zD8tB#iq65U_ZKQ-Dke@W#$)p;Wp+!pU)flR9($-q{?qt4gdUB*DFe{wEKlzap7N2N z)-Mz)brULTaN|%?Tt_dB%=QE^#>>!kFLizP1$-1>H@JN=Ia69sG~%NdMFh4bP``)N zAAK1gp`-9osInN(hNqAM&)Eg42s6DqVoPlCaHWN`Dl_;|NO zQ6>=ZprGUePePH$SLA6ulL0BKs4J<%pPcrz2%&MTN56Zi-)$e@

    `nBgHHXNC0c zpk|F!r;k(t=bQphXu(BMplDoP6V zP>He70=4x985w(3!#pEaqUZh8^Om3SaUXg%rZU1?v=DI`;oZ%Q)RvDe#+@?#NpH^7 z9TzCdL9!6`7e3lo;EK-BDy?_24wOmFdptlrQvSxr0;$J6tjE~e>V}%;T@F!~@n`Vy zh1BJs<%IPU=lW(WNDot&Rmir+jPZ)nk8t7j7ZCEWhy{OWyv(nUPJJ#w_BOs@^~pw` z$3>qhwcyaN(<^c4w2ZbyM^6xrsMB%Qsk#Q+ne+$1=uU=)cok@WkQ|*$Tc+QmPh%es zO%y>&>(|UK=G!8?3;syELd%fGp<(E9qzXsXtV^)c`ePGXU2#ciX?Y!=RLRlp==Cu5 zYPb@;F0ECRY+~Uo?7d}o&&tfrD;}EOzqnIprSTn1zj!kx*mIr|s^n#1w#CjqI(~=o z#lKMHnr3aP(yD+>%jU{NSs08o4QYg{d^lFSwpBxwd11xHw5`kTD9ej$s&O-k?GTtg z4=$PM#{aF7pASU!m35ty5=*;vnTp=Oo51=ziGm-BQ^c8qcLKavmmw>TfR7O6S}Xjd zBq{tbgu1eKO-*SrQXOsQ>Q25&FJ0P=@)Vre++!^;3;z34bWp$Nxmq8~d zUjIVaeSzd@FSbs;!s@GuHeVhI)nceV1JzJvL02OOi$~WMM0r@db&&>E1(d#Fbgd`GG5tY1y9r~7GGiVnTrJFH zrHqh_oeSB97% zD7j7IOOoRYK@7PTm7TguR9*lOd6d6cECRr06F{m>+e>s}XX6UXGI=dm4N*>6rUzuo z!=%CQ01H@V>d>4fIi4(}gERB<2d5XOXQySRWJ_8|!Q>7K)=gCtvD{qf!CVQLt1tpD zdLhd$P)cfRv81WMyOgs%!E9xB2s7!67)C zzy-q`-84qI8(Q^O$@%4J6W0v>wm`|Ms9}uo z1vRD^FXwANPJ-Zraf-3X#MuGC0Sqp_rH6Rat<1s+E>3@1A`CUDz+?Gh+CP`*Xbn1c zg=J(8#;vP)$qH4zqKrl&HI&j=?>DLV(!RNjhKXOHS++lk(Z#>uKG-H{G9U7-7BL^v z)cG=UGeqfcV&o6aB!odq@Sg=rUJb5?#bYN{kH&sB9^=p=jC1n}ydAxgYz!1<2rY>^ zCk^c;ogB#sG}IX6@~QRZc!#$ZvCT2h%x^9J24u<$sYG<_LlM#i89nHFihrR>N4v&r zx>xe?GcSrq%pCYF#h9Z^$^BdsqKvRyC&`|};UuFYQmMGEoB*30rjKurIS28wZiKA9JWft zGg$K?Ev*yjQmsB0rv|qyRPv_5c4dL%VC}(1bBJ;a4Hljn7UvDh%uP$lPf;3Q!bplK z=kM;6RGdr1cGQgdH{13QC0|00pv4JrF@lbxyfxM%u+_n|b(w8D)*F&7G}APL4DIbH0rm9&svrAD8* z7?L;GXbmuDEIgN&rmJ8K)j(^g}g{E3Z&A<33MYb?h0J?G zakEO-9rd9&+ydpAn279@{CsJAS^;vFH9no>TcFmE^%AkB50`I&D3rQkShOcjHEt>2 zHPdHu7|Rj5_TfL+m?)L;Zd8N*G5D9?&hY-lIki-@T^3mqrX zFw@naU1aY!NB=mxFY7^#7)#94+ryN;#X0O1jk-LXOL+ewxo;=D*W>pznD5&f4}+7F zdnWh9ic#?dg?QU4alv00>ky|zy_Xgvl~*WJO0k}wAkL2E0QC+~gesSJ=8JW4vRz}c z73Uzq3e?I%x_2j2not~AGotY|KjsrMO`|20nqK5IQ?#{08FyD#6`V4=y*m`2C*ez?CgPmZ+AbotDnyX9^o`$wea z48?7LxqIMgi9x+D85vl|R$}a;@|+1}x4j@l8D-JXS-!V!3tz{jT*p}`ay=WeMdomr zcNOAFK~qk?NR)n={hQqfv72(NVMo#;C^J6~3;KpSBua{j_H#$cP2$FzbNz%3! ze{_}`kGdRA^H3$$I2pM|T5m9qVM+Y#^=rl=-5O1KSrh_{HG&``-L{$3?MgN?#<=Xh zX-c*^NP@@VvRlF5(!*Jfx0JE`tu3y?mgAUeu`w_oU_bN{Kl8)PT}jM=jV*W(xQv>4 zj&}s}(({L5A{G}Wg8aTlOKY}rj^>bXWia~;Pam3x7uuvQXDh+KJFe!6trM5la~}g& zh%(%wD@jiNOW}Ng6}v&$GbV;K6GP4*$vp*n)VP#dC-ppY;a+L^N=cQSb;NVDtE~-1 zcI#wqC*Hxf6ZaLU4;HBJ7N}nos6P~_e-@}M3)SdCwOt`LexGC4mrmX20@Idd$DPAy z5yGy7Y#R8;9MEM>f(p8H;Y}oSXD{2_*;{O$=NKbt#-&BnL^&dP3e_+W1xjvis@*Af z1{bCfB~?rioiVeB6;v=dJT)RKHK(S$7O!g}S)Mo78z=3WLzGn}K1zkHP-e@TAh_sB z622w^6Y@3~&7+0+`B}IFO-$|9WdvK#r>A1cdx2_iZRnlNC}<%EXfDT;|LTxt+f@N;pBvHQ!f z&zMAWktdI^eg3Y(PTt780?80sLAxdx%Zb*$Qmhp_z+EO`&OFt5v%>#Ag zD#l=z0gE*T4dHnGr3nqjOFM#vE@0tHun?RzQprlCFEsjZULHoqEW^E%s+=vBt^72Q z?w#pmP`Ah7RI9e`LySpbtvRB@~O}sPqrFEl-?Fm zIeFc>;&Hrnfo}y%dwRnXHucdb-!!z%rtM~9A&iL#Z?QuA6H|MEqvQp)Sz%3GiM$JL z>#P&Kll*+-LICPVcj)XXHlCE5=W4I!jhMM9H1>>ONG`$>=luDwatBR6xCYYC5H!%O z6P?M7x)lzR5T(jOm69soBwPi9v&?RMnQ%Ry&Tyr6XumdWa!K(-+IK~IoyB~ID9=di zAIxuJ{WBO2eihqD+{0%kzdzXvLX7$*!AVjIQT&1MSyNI-Zd0?ar_*QdxBju@^o*Id%n^xKV1VWnCMcR;Pfk<7N)J5jf zJ@Rxq1;ndoj39c5jDMKlIH`R4dcdUmN1oEWm2Q-nZXes$_H4TVlL#NKLeoZ^L;E^o z#WcBuCdV6078Rq}n)GLKQSe@R>A8d+bmKX0@fiBLn7Q>631}z1$kKOlb4(jhPB+K* zwWna0S~DT`o8kQ{6YOF~$&``CGcc%MZ>rZfZwwyNe0#@ugIQdg=n8!ba6^@c#08&o zd=IxAq9oA>vo#F%Nu)~w?Z(~T72}9S-UL7?HKE*V*Z3Bj*r#Gp*joBiGrMv`{xG)i zolhx?==xvYmFyQcS%vH{ofU;mDIHhB&M{hdhA1gkip%RkO2~m?&CI@sBCVV8Ev003 z?GGaZ&Erh}eQjECS7Cvm9U5_CPY*wrQN%P|4$IEV?4O;U zCM{`cA|7I*q-`no)d&eF85m$0m#>6p17n8&>k+t|0c)j+HQ7ZP+{f__wAfl|(mm+6 zj13KEFdlT!3>Li4y1#YG_P3#k$4_QxY#}f1v+&+QJm2!Pxjp_EyPd(G7$=jB`~c3Q z;MUdy1sj#Uc$N^V3}rXS*!LYXv1F{d-w|nYbIAyEy=yH#_L#!?*11?wHWiefG9@z{ zC0mVqH-0wJ6K?zqRWj|GgZoQQU3-Yfu2V22K8l5H@DKb>#);g&+3ie*l@{{z=$7F9 zI!ly{P@J$LJNH3sm%^8(5CIK^C=(q6Y0-z5OZqwFc|xyJKLo^{hq zivH-xuTp-^!R^e4zD_}HWHz5>(+218V{^_Zl){m>7^1-M(lC7c%6d^DxLmBc$ClUU z)X=vQa~nqEtx_!TF_4eL<}v1Jw)r9eT4$QrXV^8a&qF}$DFIaHnyPDUTc4%77k;tF zzBBMWO%41$nZgMkBBoA*sSu^C>D_f^o_u#r&$O4DEEqRZv|zCWyZYceqaz0G4+l|hB^SQqoB%lJtpWG|M(4d-;! z&b~@h6E(GyrY31>XHD&*sa-X-o2GWx@Q5QtTwSrvDP35JpX(*C@&l+C$Z{-MCwV04 zHL5gACa)mr4UjLeKSKAn7~)<$UqY47ZQ72HOk=O$vdmgzW>yce(6F{er1i$x@SQH= z$saH*tDh7R-N7BEQ8Ql=DJ~t&%wNDM3{koW^X%m#$udE|&3sXVuNiMMGjx?hdtdoh zTP!u#nBBU&i_aAgwAgCsOHM&>3VT-K_hQa1$c`UaJ}(r@X?kT!ET`#?{0=eq@M&R# z31gL$;A-PC#N016)gRzbi0K7}T(hm8p*aro7TTAa?fdw;4571^z_FKYN_II)E;Clt z%xk%+f11DZz#4Bb8}H&qN^2TS`!AWIom|AHdHz!23#RODE*oQYdxeY6p%eS+LdAoJ z*dZRQSVBB_d==usv(^v~uCE~;ygw4+!J7#o9$cG3JXpVnupgJgWzH;H;;l=?gO`dz zJlN9@@!&WGe#L? zls}+>+CMew-#5`S^=I*RvL*g+iD?2ag2Sjvzqf*ipdP#x8`6^Yl{~m|;|Q;3c(8?r zBg{u0yeNbtyx8l(H-T_eQK$r6Xnc|1%f9U3r3)r(;p-4V=j9CYw!_+$e?PxHS}V~S zi7(!JtH*e8-r#HZLIEp0(!h7Pf;t*sf4@rlD!rH9lQF(YUv3(un+)nS37uk$PG0_% zd105o`9oTD&jVWG0Msk-kdqwZ2L2t*G+S_sG5FRbwlvELP}2 zA9bCDu0tHU;!ES+%jva?%VCAT`h_>p$fEgN-|NS;*-Ccjz;1_>d|$qoe|OwlQD;k~ z@id;g%tM!}*e%dM=)?4=*8=p?=nb}i(23Nj&l>bOt0R5M8<*48oOXtLxC?hDCCaS;j%b9 zL%S|qD-730hHKY`8&NiPg_w@BaEZQOVE38;=C1B?Tz19>fw*Mw_T;o8J-ZM*TY!%@eA%7YUY6jcKXsst7g%SaXr4ycZxrX#4S;o9VItzJYl8X`n14aZa~B6&C_ z^MKfJ)boI(;kbbzFNHCNoT>pKuZ0Bwu3&(1Ky@IW2jp|YwOQfX%y8`{0lp4W-*9<2 z=2+nMSwLwH$4ri%4aZF!{r?`0`79{>G!zetssROsn;Z&iDvJdNR7X%t5Y*yuZBe+k zKtwbPB19_<$6_lYc{mpFfY@*>-~ma)v6La74P$ILs2ULRrLX|Nc#sRgIG{R^-v;EX z!?l&++H!$>8ASf)^=b>bz7h~I7VN}cZbA3$rP*ngS80sGOwbu~k~(aDzlOn36lePF zESBXk&tjo!K(X8j3kYE~3jqgIM=a|Q%i3^ljR<5N+WiArYXu??!J2;;$9fjWdRS+1 zP&J@9cESSSZ({IqKy}2i6>)3{*EWS~8$>AdD}Vkc_ZBM@eUmgM8~$A^+gL2SVV=c8 z)qr9-3=0ThKMMf|R7Whk5zEeSZMz6WN4tL@JFP(EG1>m_;@HFDco5cE98?V`j%Q#2 z@Q*V1IG{S>xF2!c7p~nKuH7R-c@`r7GyFa)6#ZUlOz!!2u^eQv9EW)p3snP(z`u**Ar{A*u+HM3YCv&(3JZY$E`yH) zsw0la5y!D`?a^@UhzR8~uKGDIzCb}!QRDkqizeeM<@zx`DhriGUf)yUSXZt04ju%P zUqaLOWVruq@s!1a*^y0qk6JY7M{tY<8k^;k;EIfWMaG^A2Xm)eDM|F%nZC}RMzWKT z=}(43lds#JU>u!7E8~c&0de#TEWrGCDA@c?b#U||IC?%@J1z+NmFxY+i{DZB6ZAZf zZK1N<>w85a=s(c(z1)PLS1f|$G%;+jE81}ze*R0gUa{xr56JYFEq-2N{QQYl#t&5k z;)i}g3H;#cKIez(;O9N?^G>+-R=9RTP;@p|J%<;eDEujU2O-gFgmUOZiK14}^nDQS zKf8TsQKTCkSq{C$d1f4)u;J)jGWMZ8N39{#Kd?A@pK){^S{X-F4TvNBmLhR(OmB`Uc{jAC+Kq?8_S_n5=#)i}oI{2U#?PlV{In%o zr|kKOg-kzb@$(hqCl0NQAF2k#PbXLaKkZR4ey9$9egQu}g=;^AYu^islDKMTUUWg> zPti{Z$;_eOC5pO2)Aw7r|7`rbMUifFWI6N$=b3Tzy$wg*$k^}p9Ce3G|IOm)SH@8f zv@(vU8W2aRumFy(M!`6uIyh1yGPJ+LwLb+xX3xY80{ zEJfi@S34=cG>NWd(DZd^LYHRICFhr6gMzU|b+FY9Y;}pyk_2HJx!xvTY)0WvSQjb3dP;>5GWey(&MFAkva zr|TLizxqjZ-49J)N)x*JS#-(yW!U)V`E`(t_p@i~0m$?ei>+kF)*-Yqwx}8qTd%MXZHr0pX*xXdV z+ig?5kOlQ7oUov%8cc723aBqI6@B19`~8;-Ifl1KA; z9uSSDUc>{Ew%SS=^3P$6A*X6U$bWAF2Mf;ssC_H zu)ymTKxyvcj^*gtE^awT&vtQ}4@YM_<52OGL_F!JVxj#CS1dHD1{7Lw5DV>3Gc>9r zv<8G$7okmx(5gjTEg(Y7(xB8?amj-+iHF4orJ9E&4a#JO{45w_$f+6-@(VfgPzD%- zLUkaY0pvGEXwxIKsRH>$5c#LmjTUl!Iv|>Rxl=9Z&DVlTv%TDzES8I5p2b4dfMW5& z0zwF9A>e@Oh-EHfnH`}uia^?;-9M1oRv_{aH2%9d=CL?pVV%W6)qvvY2n&GkWAJf6 zb;Pj*aV(C|7DZ?aL?~B5+cX~`tFMG&&&-L3%b#fEmzi9H0ZbCxaq#( zP%^f`{(74SnSPgby33`Ob#&YO!iJ+UI>3ggRL62Jm$vI@$VEjC6!_Q)}^|(Dh zw?L*pX7O{3@v{W2j3257#Lrq-06(ixFn*{Gex3(E$0M|71V49jy>+};kHVjyo3_ewh=P@MT@Z)7-O5z${3?+ zK#c8%1u(W11!IirVC)Sr_L`t;4_DgDi+fP`)AgE^PH#zc?SrQ8%_elcWzi+4lVRhZ zvvn^Sf6Jb&{gCNzT5O$QY~6=e#uilrV(SPjfUO5mFt(@;wmt@1A4X{J3&I}ZdXMtr zC<=eVK9ut7Gl{Tc(DZ%UR{{?82d`l^$J&dl^3s}@Tco5DZjpz=z1NRzHge)^{qvhoL`2G zf1Y1&knwNr**XE4{*A@f*Nm+<(aPAOYCvoy;HxQMD-s1`i|Sx2DKbM#jMO?tY8@iA zD=*L4+_36k-oo;TP82P9F`a8Yuis2tLmkEvfzR!_?H;t8*j;b0w4+ zD^v}LmEN!bLy0IDD^v$7DPW~o)h}|;_c9P**Pi@8yZ?V|v$Jj}MGGm9T0kM+{3t)%-q9kL7 z>R=}u>ssv~2S<&c|z`41-Q_aVSZSPcC`8t6Qi^DnXpRf2rlA=#( zman|U%Gb$^k3~>sd{8wYK5mBv(6AH*%U7y{k4Eq@BT~CDQkx#BO%-IUffQUx<2u7) zLQd8jIT0*br%MSsl`|m?>?{_@9WcxSp=v;Z?0^LXau>so1F9pCB?x43q_!whTM((u zi`3?bSaw3eKbFN-Eczk1{BBB zumJdvGWa;4I^x)fIPQwn) z^&Q~xu&HmqHTCV|;ryei?_2oOA8I!B@fK_9dyw(*9h4a#R1JuazhD70{EUK4eN+b@ zPk@idBDJHD+9Q$L!-9;zAq7{`N%okS492OsZ&k9Q)q zw<5I@k=pBm3=L9nB@OI578CNozQu`P1A9Um*w;A|(!jpY0_h0DED)*&6i9DaKp>qN zejHF8fqafYK8@5qj?_LBQCtm?@5?63luxZd^pAnk9MTVYBs8S#j)7JnMx+koNmmOG ze;Q@2tl?7sve~He7Hd?$U}U5~nUO)&fXK*#1#pmof{iNGLB_WrH9?z53cp8i4?-S@eE~Mhm|K*y$=EqjAgB2Y*K;7#&yE5pe)}I1MWM|_E8~c&0dcev z7GP)*3O1Zn2S=BHql==nHc{I7QCe$3(<-jLnisdC@Tch_iKcLgrrV(D3ybn!Nrg)^ z866o-Z6un`k77G1>@Kpk4Q02J;c$D()F(1o0ACJE7@|Ym!s(7FqJiW7uF9v1l89c9E@k zdwzC9rpH*Npq24M)qwcXVFCQ?N5S}^I{3K?{Af|yl~G!ILD7R;^&wt7jKZHH zO`<4CqUZ=TeVv-*Q<6PJh7Cs1l~Ovjx1sA1vYTX2*Q1c>oh-T%8C^%w%IKnMKy-Zo z3!v)_6pSvagRW~q*RUupFG?E{rR505KIGaT@#13?{)`PnRJ1OjiK;+i>=S7EMn?HB zc?&GYbfY6X1M@iTjItpTWjQvKeM*K4>?!*UGJT{)*$772=V)b=Q8ggSeu4#1_B9Gd z8P!2q87LbarHzWxt`~g$%vFEk#jhy*`5MhbWhdcSiLc+F=^N98udxV$&PMRm}%0(32l(w0PNi=(tfg0bFQ`)XcXgTkM&Wr)hmu+ZvZ1Um8D4EqSu$k$DvPp}jItE8GRmkL5M|l00Ln5@ zFv_S7%I*SX>!P%^QQ8{8R}NRr<;4&b{(P1fyPOweQ1~;p2T_?BwqIgw95j9RM)^PM*l#hW8y#7O?c%gE%63SUZL^_lJQ?0^ zPuT>>^m{GJ_A$yPqLoob)qp6Q1`D8U5(-8c)j`>{xKq=kv_nzaLBZE_u6hG6ZbaeF zmktW>TxX#&$Ll*H@ihaQzK5Ieb;ROJ&M?CUqw7$Vcs6tp+UBz%^G2wV%pS34YZhes z!xmc)F}7x-m9a(DfY@3A3t(#j3dR=I!PfIgu;WqMGf~=8QQ8wx+GB#VmAu0$UaUsp z&)IP)$6k^+yA_(g7o+?i624?{rW+kujy)sg*i%xDJs}-GW|MEXk&~C~8N3}b{Y8tx z7Z`(U(8?I3YCsHbg9R|S9tC5N>R|9)F!*+q_GXm!MwIrNpl>_Z-ocBVDE#Srn@7$j zwGSlvc0tqkeiQmWu;`Oh&alB!?oElYH>Bg&Y}ngPK0dH#Zx3Yp`xbleG4}SNm9a_<3t&%2!PuiZ*!vRfeIBKKDtJ4_^&aEJ<0$-j`yBC@Q`;$tw>F3o`vji;y1} zA#bCV5kl2~2>BcqK*$Fu7$H;#A%B99|3+!Q3r@b^dSCM5D-`~m{8!47GZH5!q3QcO z%75eTjKzs=bYxlbyG@pyA_HgaN%4`}*YM*A}o5-oQ4EjzYM(4d_wOyMHw8?g9i4z86SFt)rj9IJL3G?UU4kCvGB&C zqiR6W)x!d4n#h8}0o4)Rm58o=w03#4mLNiFfCypp(0Wj4?XA${k-Hqt=8G!{*0J#* zp#wuc8O9iLss@C7E-V1>4Gb_2s1D@afV@kzmK3ceMr$1f_<4}}k4qN|yq+YDOQJOd z*0^-E8g0gf^!&b$)Sbn+5I$LqR1GM`+hGBrEn}hKfa-{`FJinVTI(IH^%McFfe67% zqjQZFpgcOgc_?&V={>DuV|0=k@;hLRA*X6U$nS#%0N%j>>(Bz4ycY0Mk;rg zx-iW1`bwn>!#mLQjgI!8UP>i)jE?M5S;T2z8C+l;i^bKuWUSQwD)Am<`e^GaQNlQS zAFYfdss_Z-Nmu|ipP*n@395sm3E-$AS{o|}I>q(A=EXNC{0XWshM2CLRT4qpLep2- zgrF*mAo&b8Y%qSt+VJxo*{ZVV=X=QXN{gR~jGxnJW&BVzAb$RW1@Q9=3dRrB!Ot}C zGbLJUh}P-^MSpYEGrYhrYB!;13PLg$}ah~5Og8eyNDMT zqwvq6**qS$`dT0nbO|(l^P3Q~z#>S_A;SjCp+*~iE+tzF?D+|UOrLM@Gmr5Tj#kDG zRRiLuJuHA9FAByF)xpnd@Ut>nTOO?~jn-}vEM391ujEAs6#gu&L{w%P-7c}z5t_c+ zqH(D@Lhpt*_NJB2?G{VA(UGOma*G;$DW9m>Qt3PD=7K^UUjIIG_Wpq(BAi9Rb0_e&@!RVqo z=-Lmu_C;%ZqqW`9+D^gPwOo4yFGiy9XKWv$GBfOciLnA``VK^6r66V4{T5@o(UE1? zUW*!iw?x@at6gMRAsN2kp0Xmy^aB=U_c6+@Lo1_oAdYFgAGVGYdR~0mUN1O0<%;HPVFvAARum>f&4%^UGO?Hpj z(^UhRe$=AtQAXD!v@*J=`fusFlYSt2E`C}71^u`Vql@aGtA9*}mL8*}#%L)qTHhG+ zKAV1k#@8-}r%5tRMCmc&W?4^-;rT^(lPNepMt7D+yn0_8o4;k@`UBAeVhGE8IAK9i zHK3sACuCsgW)=$$sE(j=5L8x-HYi5R6cMe02+{J0(kP-VDikc zE$1*h|z|}X!$YPPywEPvc}h09*z+fczrlfn)fLA z96cM3p&b3fIkW!9?{yclpy=0bSWr|AC@ABHV|KDw5FOPK)Mx}XDn`3LMk^8#-A54> z$ip$pibx)g>v=$IIEr{c(r}bA$9TzlWoW1@#1+u;HL;Kta6>3y9?z77Grjj-VP4 zR9%cVDMqUn5xoKtqLt2$Ix8Z1I41Fc*l<+yfTZD=%#gndV+=V}148}*ECBEc1{eoa z2l5#}eq)R_Jw}@WF17VwoMIHHtvKLA!q-v#mhnA!z(}am-_Jd<*L=4ypze$A4e}@PA^4}j?osyXbVIr|Aol^!2;qqpTWlg)e*-! z#IZI;TN9(*CPJYfwedg0*IJ?IYosx`?cc?+p2ZRY^DGvs1{6yIEFgr-SO_?vI%3(3 zST@FJcZooJX!j3fqZNoeCU^b2IJU4jE{Am%2UP=#qcbc3{*??q4ycYeb|a3RG1~SR zZL0{S3s>#R3;Ky0|8?n3J}T@rzry1R$>DwFQKU>^mv7j3r*|fLaqCww^H~#t~Hm;wT*!Kn?w74?F*;4vroGNB75Q_X&bB zxL$u=3_#&e(EU8Ng~~CnPnQVFgr@Is6M}S$AURD88|;d9pAA0)$(C-<&mhS3!xle> z7(av2%J`vbK>S<}3*cus3dRrB!Oyec=jj;j$r$Z%K@t5%4pgO|#PO%-X@q3n3qCJV zM8BHjdoIR*c6;8UNH;pN9D0)T%s6`7h9maFI?vm4L_d_HKWA}toN-i+R>l!k1LDZ| zF`Nl7#5gj34Ci%l^lFUuvLL7q3LwbwmvCO?v9TO_QzB?G`uR>YA?QtuAUTH&8;qZq zZTMk7g!867KkSEaPFVcB!T1qBghSPU_%VLqM*I*C)saJ=fS-?Iv=3sm_XI`KkKlkQ z`h^?+9Qp_$nK|^iMA2fR=(8CA+4ysdBHif7a_9rjGvnwz8;` z^eN+LDOy<$Q8gfr?tleEyb=Y=A*zF;Z^6;mG1^H%kny8A(r@DU6ZAEYjpfj3i6Hvf z9N+g%2s&*MB3P@7oARtl6L69UOh=HJp3W|~c zx2k)4W_D)=-v0i+&!fAmsw;fEI!y20>`}&tUWmi^P%|xj-iHR@GZ6*jLv7&m2k`m5 zhIT^XbGo1Rrr)~nXZh8|j5(d8jx$G#U#ydbuLRhf1L(CldZu5U12X)S7W6_K&M#`F zh1N!BfTB-PaDGu6Xq^qTvi({`1=uDbC*PDq@4~SHmJPrX`E{-du+JbFsp7Y8a_1U= z>9Ql|S4DyPnIlGT;fb7Uj~KmoN3UWab`B#(FU(=YsF@aG`=J4deSv}zqc#w`7>He{ z;QCq!9T3GgD6DW@Xv(kZCb+(ZWTaXWT-6P@%=smCoH<(Gk@D*HXnhZ!Ud=$ODx-A} zR7Q)MX`yuj8i3YO6pR+NfmR4;1^ikK1=w#w?srj~L}3LiV9KwE39vsP8OiZmH^7Ji zm@YeVe%1J2^XpI29k4Q9NHtJ!eo-4}-2$|3_G>r!wFZ9eMg?0G+{g`n^QF2GyMB|*F}_rn0P>|e z>WNEr*KcMu;h^$hgoC1HT0!MQ1ANH@NV|JFyT2h)AIZl;rR{hFhZafjN(kAHbQ$C zp*`f+9`tK*6<0A>h}m?P`;ZZrc~Bk{Vez2EMOdamX~Uk!p^QDJW?G)pYp3A(!|X6B z)Q0De!SfD&t({*hRi4wEq^#-G!SGyf2Ny9Syq1<4uBV;_Q(q9>kz?ry^&AT|(~9K@ zXg~;EIRsRwjaVK>EM5FsClyF<(5-=VF#<6UL8t#Mj&2-BA86+|sF_wA1E2x!Kf~^$ zLT$wHB;x4p*LwN29x9Z9U|F-Nw-Jio%QPlE{v=v@n_n4S+_yf{WU~Xc#bh-LK)#9K^3Um(3S) z3q(P$;<5ttx`>S*u--HQL@(Ehj7S3LO#>ivnn)eIdJeV0=OfbfraeB3z|%(<_zY)! z7K6(8P%|xj)<6UBS%!jl32FnM@xW)SUmN4s-c}H;6{71zu^xpLqOk}m@klkv1knaa zMke~LGij0mkuE!O4vi5wGe&RQU_|flicGS{XcKt)L<6GysF@Z%KSKlJK8%9#p*HZ*fzN!uHdo>Ei;(+O6!gL_ zD?alPPa=U9neaIQ$;d}Zb8L};k1jiM0?id56F~0!eB#dMH`2by9Dt@5ONl|5P&z|&V6Xsuwh&H|OuqGnoXT>uTpugWMGEouX;jX-O?Ut6mHyHLno zB#MhsSOHsa%C9XZ!01J5khXwfU)^j!v8I~gtYel}{Rg;p2n1zM#j7%gf8tr~&G+GPRll7Ln%pj{l$ zE(|0N3-pSrNFWe7A|IJ`Y$}-2+zjKp^=A(Sl;U@XH^dV0uEBbBLO0p+aw-f}$r;Fe=mrDm8)16#*?0(82*N zs34&?QUNjX2-%eIxWd50oDmTL2VtUz1ssHl9u#;GDDv-nYH=U~pqK-pW?F&J3!4zg za1$D zDMKqL#?W5Nh)jeqBSOuz5cv=qfC#;CiV>kU5NQBJZVYHe0qwegR-h1>4X$-)Z#3Z0 zix6z$8T&ec2aT=xdo&)|0s)6wpk`WeEQ1EbAzn0v3bhf(ZHS{uKx-V( z8mSv{nJFB%l>5Fb;tWtW3*JYXb@M zu(lFF@Ul~4T6T&B5~k#QgabJY#T*DV(+VU5f6j|Q=;clv2(=MNR|L{Ipmhvrj|Q~% z0j;fyB@+UXZh^=JG92DjIve5W9pP(YU>_Cn@W8e=2DYsT=Zprn0_^GCQU+E~jDdZe z@i+^@j0ZK-!sB9S03K(fU_7V|Je~p`eFEAO0j+01>#o3{S2+PI)4=vIkT4JI69Nbx z*q)|=?Jkfo4eZk#NHr+tK&Y8kAW>*QAeXcMs8Ab$3`QV>0@}cU)<2;24QOQn?O7EL zznp1EAW~jNbSLeQgN%sufp9l5w*5s&Jhpv}u`M&I&x+vAXqaomJ$*>ZFbj$?%r7xI zS3;Q4p=Mg>+yD&#0;WH-XOZfc8c}do7^78qi)=(C|x`21{J-AzX$VxR^)! z4FL;}^lPS(e$`ZeSpZ`i^^qJGz0HZ^qGnog(Hn>m4!w+t)0f(aYa-$rAJE1Iv@rqg z?SM8)#Z?ReB!$Rej%&PqTw_gfjWNaYwy8cUC9X*vR~$w-E^4L~S9fSYT=X&`j*Hre zYdYe3KcGzsXz!_rdVm#~nRGOI-v~;d0xuIu{GN!4l9(PVJeHReJDz!y4@SLVQlFWU zyn5T%E!mqC#!Bx)rW&322)F+J=C(E}*SZKF@(b z%{s&51VU1c7E8jp7$2Op8k2t&^~~hMj+oKkZ%Lpfq=GOMX^JO?i9r?6xN%UZ{Z}Zqx3S@ z!vW*lTwg#kawvcYH37hXXyrL<0HDi`)LTDbLSVls>cqY0m!#})0HCFQi+eA4`k{dO z_SQkh=qpeeBWk9F5xofr(0qe}2bi-m=Pdam0Thf6 zwSiA|u(4J#s8tAR<$_vfFmVl4QAk%3MK%g6N)>}f8l4j~(x@^dBWDM#&rRn9DG~TS zN|zlujVeG1uCExTazVbn;-~sd(6OZOL`tO8*`)ZKplwQ>1D<|%P^DDmAdPSpP#H36 zrUh9IXn>-NQ7~lG24vL$*~LNa!k~7(!pkp21EL6`u;O*G2$i$yQWIVwNJcJ6!s}84 zFLPE&9SqlnCb-VGfh$aUFSUm&2R!`}1Fq@}R|Hgsi<)V{RRj%y>uMAX7qtOb6maDR zwVa?93Tgp`*bPGZMp4v9VMQz#Q6(0tJQHFKAQ`C@v_8P)8Hnk!BWGBSfSn-=nIH?; zK-Q2H=h;Jc6L@+p1G1V7StC#xGHRv;**(wz$Zkc!kWm|uT?@#r4r*5gwV1-|ULks) zD4LKi;kwEMSIh>k=A^g49{b(E zk3llhBxt?TyVXEUmmN978VcAMvic^-Zm@x@6Dhvc93!KAuC3tdLkzfHVz{<}%5YILEw~Oq z15l#3rE!K)8*sf1xJCuFkwI-lP#YH1URR)fBRYI5itkWZK^uj@5=r)s3AFDa85t9_ zUZA~WfTqiioMa;f@{HOD6Kcau_1A3>JV-{~u}AO_c={Lv!O@H$y%UWQq-I(Oo`eP< zNG~sA1gQ-K-v@$Ig4%mQZBkI1py2yMNdGB{zff4=n<66ToSR{S?{7#(rYFHS!+_76 zb5aMR_nrx{Nv8S)8}$Am8#C6re0oh=heujwm81teLdLlu0X0h~z>tvOEcq6$T>aOp-b* zfLuZSSJ(qWZ$;CW8-OfhKEHRY+z8X2bDpg zW?G=oOUe)>y*rITp*BGI9H4Afh}zgZ3j582Y#aH?F7nJ3faDqRmTC`Px;y=k*tk zj@~xL(NQz4=z2o~qN6v0adgy1bblhclR@pbpmtn^)(0$vEkbKUp`A2BGf(Q@L=e0^ z95?Fn2uDt}C93wT;it%k|fTCd>8YFh8n)Q0C5 z!}AM6+W8^vT;=&ZAv#|a3s6{BkPGGD(A{?RkZ~!gLo!k=WKGHHM$o$K$ZP8PMx^?= zMqTZ~3rSgZ`Z3hhyX}v_)2oHlMPyaRXc4H45jE4o=u>C_G)qzN+@m%y3IZd4NV{AC zv|7lm5ye^*R)G8>9zN3Lm;hP_$w)W}pd14rb5=+lJZCSr!Dl_`%CX0119*Daz$e7` zYy_3@p=Mh6?1l#5^BD@phuXj=27GFVw7ig3Q$h5F5Zxn+FHu+_s*R8mr?9Ql|P@aK{UelMM1t2CDQ(qG#)3h{>`{9bp1Y_qS3 zk6E$qG{q2~N9OLZ2l9OI^xF*}n=+6WfXYBpGc6$f&;Zj_Q819y29W;&koSkQ`$F11 z3dMjB4T>U!!iwVkGE&bnd=K1&Vh$uD45zouqXv$8q9bKv8v`-DwE<)+gKU$Hrc+MhE${UlgUasxJNGsgeIl6yjG>pBN$O5zitY z6SYpWj3~3~Lfg`)J})}CUqAXRykEA*U%fhKjJ`CAUIm{CTRy{6_5#tHGDF#EmKjCwW*K*RuhtjB!i&;Eje<2%yd{mDl|BdaS4TZj zkni$dLmpqtV?W*F@zf`$sD&4DHs~RH(OOG1{9!j}!h4)G`(@vb#Wx@Ru83MJs+d-A zOl$uSF=a*3yIJO4-U66e6}5&DN?^B&?W}XK6Li8ZXkeEWMQ^fmy%p5EyhRv1pmmq` z1_o(b3P=W8A|d!;RSW_&!CnZC>$<6cM&LMMTgdMFh@jPBk;72#?GCoFY{HUsL217PGQRNLm!*P|&b*8;~@v ziBFMhY7J{99+cmOfZnhsrna9wz`MKphVZ8>H5XG^_A(uC8`VUe0}z7bwEuSgDjNwE z-cpk+ya!F}Gd0ul`B&ldPYIu?4WGNg=dLxi&dTTGphr5vL;L`yr|dPj$gab!R|0z1 zn)E_=c2Vz)`gp4UoPB!(mM-khzMg;v_LZ9dtFMm{zTGk6D7v6ve5nmzZ_aD1-IS*_ z$V=ec19ZJXp86WE#J7H)z;_todsAKlUm*yG7n|{IoJXd5LKFK;&C~c?HVXlI&W@j# z(LCF8&RxDDdLR9hP=KNjdn(&-xkZb{+MUJP?ZpX~pCXrUFQ)BCZdm#E6?^nMlPMhc z(i@7PBQT?RlPg` z`koi_6gDsRL`A<>mC8H{hvX^;^B-WHLoGVJ!tz;_+|`P%uPe1AUFPw4;c3fa5!(nb zSxJM0Gl+a7h`<>#XpFLU_j31Q*?o*%_pzcoWYB$roy0_vpdmu=X${e2D1h?!Q1B2@ z8$;9uLljp-G(`waMWM%wF--~{W|!Uvfnv_YraB%=(1REO!I=(Dq*bwy#=M&s^jt;% z(nI4+Qqu}~JP()V&!2yH?!bPp#$u$wPy?}95aZCGHLcL*Kmqj3M!}&`8=-YWXl+zz zb3xSGAp6FL@(_vVx^~4ZJP-6}dyaBGs*w)GSh^PbJ%y!ATR`kbxvCTUF)Mo^u{$#R zBVu>5vKJA%GqV>HyNi{*gxFn~{V}m0x3ZTKyBo8Y5xcvUy`0!Rn7xA7J+17O#O}rH zRm6V6%Kn7dy_x+fvHMurtBL(2v)2&&DJy#|v7cu4I$}R#Wv?gpv&`N=?B}fPjl?cv z_9kLKZ)I;Lc3)<1A$C72`!izqXZBWN53sVg5qluBKPUDJR`zz#nq?HWWdTZxNW0?e zkq}4$p4CMdY^r#RFsxMZ6=49Wl2L@AqDp2F28AkFMS!0w<%$3_Rmv9uQmRxa0(ew8 zs|YYrrD72Pp-QD9gie+0A_Pg5%0&o=DrXnL@!OHheobRc`(p*pkjdbz_XH6;a(Hs+CZk z6JTmKs@q}(uVZz9JZ$cV28yeKoba!J11>lRNcSL2$Dv|6G7Q1|Va1-v^~GjJ9##$y zEguy!ukd(cgZh6SBPovLTT(I@O8yG)oQ~XP-!+rFDzQrWBcy`wNWl=SP!sr(3`H84KQ&zWgX{dM!4O3Y!pu&0|J4V?ib4XuluNp8sqW@nFr}9+P-NXebN)Vin4S z(1#%jB!vD75C+GsLJvXc=bVJGNv!90t4P@(5ws_FP`}mD$jIWnzVZW&#eUNG2gD<< z7SjNW*eM9%A$A3s2sY!5%U^6dW%mPI*%3#!c|p4R7D4|>e!R+Sd;VJz&cBEza#K9f z&!MxQuuI2PezY$8o1|3+R^H?P=%5x zH%23sKaq7`L;@)zYTH8&a8z`xMyB5>HYpbec4RAz?1;h0%n;`0Oit?RkdBVSa`z5= znHkC-FB9q#(lVx4k|}ksu<3oNt&>8Pk#?6!kH)YGW%_cEksB}`g;flT-&UIua#wgT zm_Qmwe+nUUI*3j*24$A(rV4bmWV<$rODCb!&=PVnZAj&kl*k23>PDpxboD_8M&tp) zsR=4)D>c*E%C3Y0=+RJcwo)6}`av;%MXp$zUaY-etW7D_-YeE7spPFA`qV`cnOjT< zRMp=D?sNE1S|ztXz>D<{26*m*=E|pskgFg}%UL~WWSre@tmYO&njhw8!sg_ly=hv) z)xzh^^y%D<_cRkZ1GwY1%W(d@+`j#G#*ER(hesy1h)w89IDH+#Q2M}PdR!`7c`oGN zhhNj_yD`f`x92b8ak}2BhnDCQ+0MPLg0iMj(e*~^I=y&M|FNO`<*cl}K@kh_Sc}!^ zL4685Nc=622oB!N3F?zTpBLnD;q9|&RA{`JVwh8GinJz1akL-v=vX$5Ok)TjEoK)> z)q+u|V_wb20b@3@;Q8~t*RXgLRDCvk5bJwx*Zc)?y5B->8+0BE8f|}#f|ZsYigQ+t z{1vbOE?j7W?uF151qsbt9ke}NBYzbO+-3-{m8;-O)2QIxPP{qnqRAtcfa*KI1sbN1 zK)e&gW|@VEHVP-`=B(^)LyMTIWC8U1h%TTe9X3m2{wETXW@Kt%vAeWd&F+VE^dn%k z5Uyh(T_m+MCxe1U21RzokVB>cHHbCxKb8GjkoD_ulS7A!vH=%i_F=N(W&8MxQA1rO z=EN?V6ZlBPm?oMilx3~{jeXdfm473irU*Nl1~U;>wrbk4}BgbC3Hmk5Y2Qpoi0!S zJ)KeTrbBJ4E*r4vtWR}l4eykI4gdOO{9$W!fgo5gLz;}DB}#(s52wQk?@{AIWY z^WZKCR}LGQ(Su~RaeovTk%bq80Uq3TYqK8Gr4wkRkg{x0VClYGN64D=`dZsre^e6QJo7l{7_^9S4Y ze~I{enE$dJ{}tkY$^4;`Z}IOn;_qet8r#7;_ zBOVOCE!GYcYx`C1j}@ZhL@^14egF?+n{w6KlUXDGAGw~r3wGpivHmSxFX9nkPmC@M z_rz$Om`uD1E%n2gM|)yo9u4aE6%OdQg1CzQAu0Ox&B$41sR}p-?<1*=F-UD>T~kS_ zqFIWbDE5=o7LwY+Qty*gC9_mjNPSIGa{`c>!zaCIB$aKJ@mQJ!gT?xO8NB(nlzuQ&KgcUc!M`j$TPjREOhI8(aORS%3FGU2 zl9!pFM^AC*`KT5i<*H6pPn;ZBNF9X{g7*=AsF!0gu)!oeywbmf@<)(Njb<^a^0KNW zR#gu3NW+=Rro8e)d#9gbY0>=O#TC(7`Rgf&^)+Rf6W_>L?yh7yI+i zk|Nt6f~a?ro#VykF!)0>3{E~}BmGvY64$u$nsU|oNI6U>9MQzBq`3L`&ggHT zX^SL3@xjsWN&EkQ91mI@IW3Ndt?~k_Gfb@`)YmkbELkYgRF5=2K)6}CD8NPVKcbO3 zagUNnR$;}sCz?q4pFo2AuP7pao@vS-C+R;md!|acBJ4y|DPM$Lf+`h?aGszeCn=4JV@4HJBR8K>M2XLGj>P2M{$sRn z@{y1qE5*?UHT&(NI6c&2Hj0ZT`Z;1~s3r>fiQvd(aelBJE6)^(Pn0eNProRR@hb?+ z(YuUDLLpCC`p5JLE3aoRhg4xT9?Kf2;wXv!uo*xja!EW=za@P)zJA#z`gr34xHp;a zHL<=+ZL#s^y%*#Y&HV#CJt8@Av6o#&zA)I;IVMoCm*M!w-}erZcEo#090Zk!-pq3n zk%vg&G9`ettO9*>(#Zh_C|(+;Jn?e;g+VL>{x}mMg_}2sMnTjsB`*Xn!Tf*(CgL2L z=-?DvlW#L0dU`cYwy(&;atD!fSZw?gSC@4Kj%1Zlf2apZGEhcTpch-e(m_ zUe8&$Mt(b1*UTy#$J&2Feg@6A=|bv1BvprEpmg(u^V?(2sJ1^qZTQv#VgN#L_?uAT zN?vf|#JxGL*W$$i*iYtf=adlnrnr73sZT6Z4-&CaT-VIRhlq$#f?U~2xvuGrJweQP1J19|bvj2TF9G*{j=KjmVJ&$KYe_Y zl0HH*GQ0LNt~22u<=apZIW7az*;G9dtyw+VgWgkC>R*9INs zVDtkC(f23!o|H*)Gd_ig+(R~A4{?$VB(6*n3pOfb`Kerf93KoOK9w6x){J=SBc62> z?`XtJe~mC&u@WIrcd0V zqhEF+t^{_hlYXcgpSKFPI@765EGy^%9E}i~z}R{+HWu?9|0I+^DMjJI)y^k*=yWXG zHH4wo5bT!Jj2ii!IW1o!S!1%0EIzfAV-W+B^R#b2(;d$_yw-~DZ%|~n#C0(+$Pj{X z7>JlQoiJ?@X)uz^7=fCnZ5Np-Z;?pKgNosrbsi%#_S5ID^7&;Hnaqkp7wnI*8nfPv z@uk+|Sj!A=%2MyL5Q$vv!ueeh2RcA8{h)Rs*1af5XpT#=GgP2O)A}d6=6o%j-%SQL z9-@(k=IL3MDlNWleeQV{sLDnfT2rU1eiLmH_>3EKvr%Hd&~N5Vi?a(~pAv&Ik(_Nv zB4Rp+^Lua*?pi>AS6YW0w?5% ziiDF#0&)16WtFg7?LM%I$klFzxjg|=;*RWt1t|fnF_>mPC>y$~_ofeZd zOkK8-$dV->;xQOg7yc|G2|AfJ?CHIRCOv2?iG~v_@<=?9fVK)W@XdYU#d;EOIb5A1 zlYRrqHHhoto0sx%bq^t{4p;K5BbE|u!s4K{k$h`lIcW8f&TS%=G0x_t>`5uInarwV z6i(7}_zT|RFtr6tJUkSd4)BF7F`ZiAQ4hofu;|Z+rjv5|Uqf0NHH|`4FJx>PVSI6) zv8CTMPjB@sgyATZG%JrGq8~5ET^#~J<8xb`;`k}>qKw#1Qgs2<9y~(>K6+3Qk?tUl zfs}FjH;$w`A;Od2{0OlNL@ee29O~&e&FOqB215s6h@R5HwEO z>NMj;6X_3l@d~ z)b&aw$lwA-9GQC3iawZ^AgoJxq#8sslDG7Ms@7lC`WnY0y(~e+AK%d>#t_CJ8`?P} zYNiuX6(~SR=WrybP#Yn=hLB#3YcH!X&J}VO2=?pdJz+RT1O+X%s~Lb#hsM zmHx$d|JmOQ(LXh5Uq+mG!eM#KD#l;=!NTa0%di}UZoWUO>Z0A)2dY7eF?%gd%r1ih zKy@h!P6KKKvtht&gaYhxAyflJWK>)qK`10$RRxImmd%ZdWziB3u8FNGh(7vTj90+~ zx%h;MHVQQJUt-Z5Gq$fBh=@%OfB%HFsc<9@M+9Un=@WrrLRqd=nR&6BB<)2>MEJm? zmHxd&O*c)vWC^Eh_p#qmGQS^a)9a4}H1-@w1H9A`c;c611Wr@ZlojF_x1<;?5g7cBu$j5h( zkF(<1jJP%}u1$?=lT~hBCpug&iXu_mAd31ZBD3TAWSfL-0G>XZ6Rlv89FT^fiS?ZB zZVEr-P;UYeaYF`v-E8!tbTJ0Q_`8-{AY#3mn`^q7YeL+);*@E^E!SMBHkwn{d2tCD1#f@X zCBh(n%3YVCl-7aB9C_g-;nAn5xOfwpisrtWaBMPNIp7J5M^UUG^6Kk9@JXM?S6_?e z5Vimbd{A^yzJ`q`g&Am~7nBCn(* z5>I{p_b72iQkuAlM})_~#eT8`3uYp@I)a4c>Pr0#0L#jF!ePqMm%#X{YZ*=qCV`Z@ z8S&|yk?`UCr7(kD(Ed2ITNj}ym|%2IGMjprmA_ohf*uf!EHqD6_nR-1uOkz|STCyC zBc7Lr*S6DC-F@{UcNg-p$>aXGR63>etZRscAJ4Sb#j zAt~q-;KijF`au49GL@W#9B1Ojqpwv$UWysZSYrL{XO)wS2gh!?85;ySGT?eM#@%e7 z#r2rsZ1VNki_q+JJ!TqQr|U68aq{)pOQhIxJ?7*eR%k;_@*UYLgpi!Ftbpb{e@HJT z>Z`<;6P5Xir}v@6kaLt7iRt+o7}%CEJu#GTph3XW_omgxJ&YviEJFKuI%ko$pa9B8 zqTsU#wQ&}ih_lG*xb}%Uf{X$^vM#QFVsp%R8$5j-wz7G_{4H1&M3thy0z33t`rKg@ zt}*Ber$+u}T|FshE^IMPW#Q8OK&CP4w*nTUdYr#66^0-(0Vwa*k#?}8rL5!XMn0ctXM`VIlq zmjFssDXds3PzX ziLu~>gmINs#CQZKuRintB*iph`4mLp3^i!1AtgV+&Q!j`q!ZB8K{L>A*4f!vFYG`K>}<5!G2cDR&W%m(_hD|q@6z5TCwoR*o9*mv5%!=4_O_xCxuvD} z?7KJJ5FJ&yVuWks2BCdl?s)l;=ly-p^PAvtkZ%h4(YZMGj>TJ?c;Uw&!-;L=5oI4W z)5*S_PyjtUP;mB98`-xA+4px``!lYcRN1#ni0($ApXBWGl~CU=Krm(BzsNqp_!5lB zskjhM%D%5i%PHIJ%P0}9?6Zp4W#9f3)9~kO5RrXQgT^=@bSg@`posP=&fJ5Ym0CMhxO z*bIBY`O;pNlRYE*%Guc~FYG}L?45;%HTx=-Bu-wgZcz5!X3f6S$_J5sqb%8nL533* z$s@`>YNnHYXF~z>R7SzsM{Q)^T4Z0<678ZA?E;m3=Lpd%C?c1Z@L(jKoX!PJzkoCH zUiRxe5J=(_z8KxZQ&=4tDHs<}?@LOAa8gEIL|QJf&B*)Y$X#p|F*3y%xvD9q5nnYB zkttAv#wDcWBHN5?Chc76WXH(J%k1o2F6=-J?D(yA>@xCxX)oYp&xk8%XD=k|K@IHX zI4Lo1D|4+PbPzFL+gukY;VifUV$tTTG-~Z(AfBPlB{d;p9c(yLi&XrFRpga8Xa-v$NqLu^VTZ;hdK=v=0*a3=TrEmxRS z_ertDCpXyu=fx<#_jo+aHuS3G8mh;`9wy)=fo!xkjPi_7fq-6!=%T`@E5XOrg`b6E zXha|2Y8_OQak&D$BFVUbc&4~Kn2bvS8y0^;#9s|Ui zu@oKyLJ2%tvaz}_X2k>aLPQl6&Rh+?!s8k=qQ%_rT2zzq$V0E1$#{Txrg#`%?MfUr zWxmv6ll5To^thCbP27@A?sr5>!bjx`O{O0-;4>>JUuLO%iL=ps7`5U9dLg2W3a1Ld zSNIg75iQ|<*P)t>PYk_kC*uR+nc~wTIbW`1Q`f`P>2aZa*;y+IkE)4$Av|`~0v?NV ztn+7aP9k3(WMf4zX2k>aLPQl6&fEaL!sA9XqOG`JeN>b2xEj5#O2z}kGsUBIG9Go= zR0EhgJs$0W$ILu8JZ9wqkAX>e3{-eL#Ks!Jm=zDu3lUXRICB&D3Xeu;L|b#en^8^1 zBOkr4O~wPnGsWYfWIXDzsm3sMW_bLPj7Jr7e*8*!tWLsXwZh|JHg*e)S@8h95K%>i zGflu(c-)Fcv<>&W4b@~ku1BxJWIRATQ#|6ycwEP(n!?oS@u2y#B6&KiV zJmx4o9${m*!7RZxfHIr~r`)~~FYX6$R<=rG)-c`7? zXJgG_%!&)>g@`UHocRy<3YQjWL_2W52T)DMr3rd9PR0eqGsPt(Pi|pTEn({Pcu=1F znVctF4Z_psV`A7x|3FlNOA^g=`x70$%LS9p}55q*sNJ&0;D9=D^{ZOM3m zc&2zfkenY)*;Ff-Ix{@}Nyfvn@BT}8>`KayT`E61vayF?%!&u-g@`IDoM{cd!sB5y zqMf*3dsO9VwgXW+GxbqalTo@Gy6#Ly3B)r+sU#VtyV%rYFm-yA9zxcX)k&H~{0F}D z070jd=j#BaX-OzeQz&&|V;y14iW2CBh$)z)sWUY)Bslc26$zBkOMLMx#ShFy zcp{>Tw+N2_RPhzzY)6%hA{>ILl39e)4OOy=u&q<2ToLv&s+2FnLQa(mMOeY8a#j(h zELAENAy=tVsR)BamFyyn3;iWD`4shYEL~C6FQvyA^;`~t$H{5BM5qp-bS@EkK>_si zK*5iX)J7_7#U(sc?vGlhMT5oK6mh^QXF zLDZk(djw;2Y*4ekM|fT$Ih_1GZTF;`1U7mGHwisbZW88kgd<>-=Y$GH(BC9yp5%yn z(Z4nF=d=7sqO(ykpJ{#w&RgK%Z-@X*6cO=j^G1PG_$>GPFRIZ6TzwnWWKaj9SN~*C zK|E7XQ!XI}NKi+^*y%x)*AP}P)$u3g8X^IvaSfq!WMg2=3Z|gHLrz%0T*&fciJkgTB4IGcgCxP6fNJz3RxuIPWH1M#*PvuDK|E719d9sRl%P(6(bI!kX1&9( zg6n*TkpS1Y!&tfGgVwRsw^dxWvX9_p~7Z61e5raDwBnj^Os79Bt zifO1OgZm144M_$U#4`mqcMKoUhH z4CX?RB$ywe8ePdM7NMF9<_Po}mJB9{X9{M@#mjIB=3*E-Gca-WVg=LkXl=QANr1Up zfw_t!TLNQNFa`Z%a>4@UCoI2|=t*D-&N6TSCLoC-5(aZQND|Bys760!6)RCq26Gg8 zjZ6j;#4`mm<<{mc3FayoJ3W~4-o^^1<@wWcZ<7GixVKr&k$nPVRxkzqQ*y!r<{Fk? zP4px%1!oO7027cz5eb92795~A{xb#`ak!^%AE0}`5iJY*2xt`@W6Fmt`!Px>1zyu^wM8aTx29gAG zE2_~AtYRCg$zYC0ud&Hsf_SE2I^GwJlc0VMqo)T|-WXXyRY#_j8>0lM@2cs(kt5s= zV^&ZFeFr&V0d*70?<9H>sDiT#9DoXFqKJe+-3^ii^$S#^n_0ykRFgq{7riDXg9_rA zf|`<{lO&j5!r1A-l-EsGFfG&Fa@~{w)3|Qh!jbKTF)NsY{uMc40rNAK-$(Q$Fa>8n zH~UNidI~8r{w+ zjvLeyMBTyE-%w44cm{M$ONJQ4Gle+inrpg*_;(mPJ;d^&%L=jcMOOmiX$s<<9N9@2 zvqCKBe~=RvhgeBG2(1*&K0i47Tci?H)ir9u%_ZK|AAgq4OW z6^k%Ss8Xp2BTSX-A`B|sk&#c)XF04>s1nb(asuB|4nETrS#QXsb46AT3ZN$g1z(X- z8)>v3S7hImXkV9T`%1LECEA`6ZMV88D=+$-g+kxWmtu$6!-^mzJRFa|r~M8%3r;pT zk?%`{bkeQZ`K0E1+gq_CGTkn)iWqk^#_iFC(sp@VI7r(F>mpEbEe1VkR3$BYY_G+B zkcO%`88WWLs!KzaEQT%-hM)(AF0&f4x#21JQ5wA5$)FKg4QbFCnO_)$9vBQ-wUkXx zd@W#5zYX-&{^_CoqtamLw4&k_B-80D``-YpvGhYZW3%(Q;WbthA=bHS?YgOlx*h>3qW*R890D8aWSR4Av{FCHMg2%u9q%d~6I^tR1JA+5cU;v^Q|hOgT!YSgCX@b9UonCly}rVz3<66|Zj@;@7b}3 z2R}XR&CJ9q*2C-j1Z30d=EdqZ&Qn3GZ&-{rDVNqe+gIj)E`954_kf$-L-uwLyW9Ou+5HuQ4p96ImID+&f#nFr z?_k#>>#J^SHv?oByOovQiV$>wq5@d9P*nDLeP`R-J;&Yd zMau5^ZptsVS6Na5J!MQ`76c7c7Taie+NKj zk4^)W`o1pe%UpH5qIA6EqT@yI99(?CRsArf{xui%ue$0Ot#piXc4MTI3a@trSPr@E z^^F13W(Rr)WS5;_vT|vXv)u`9cBk0eo$79Pp0Ya|f(|3{0ay;xd?r|qP|OF@28snB zyFjr_xwORD?jkq4%kAy1aJRcb*f}lfCU%J^nU~l&uce_WF-Ggq*f3R2nqr39Dmn4pBu}dteWZAcBgXa)%9$2=c z==IhFt6|T!ZA-h|)TL)<+;#X8HzWbR>$pPkO?MqZzU%P%t_CwX;mbl`V#{l&oW2oK zru?@!T?C$k)7OFJ;B*04ceL(p?{Pga-6Fb1@ogfy2~4Mm?otum4k@RIZUfK3?IvJ3 zy4@H|H@6!peu~>byMywr9ps#RD+Mpbw+tTVHcEXGsv)npwc?pfKaLAD-b8yT)7@Q6 zKMtP5Kz9Kv#Vc{s)=61T@~TW^=VOX*@+^^^Pk`w(md`7vpM{hYUQdJP;MtSPvb|@$ z6+gu@4A(2l{7Ww8Uj)wqvlqZ}@N9sxZ0}h=#kccpr1ESyq{1nf;zO7(7VfLkRdN-t;Fxv^9gJ;{7WqZ%IDSnD)!0bC^{(y`5{opxZ z_7zyRp3#Z#doY~>KdLMraj|^JSv|b}UFkUPqT?6v9K1i~tlsN838s_xrS0jhhzavQ?C6yL_>2f(y(xh2RhE|)5oABLcV zUk@p}_E0{k_%?pE1=Gf_b|Aa>)l>P^4T26(b_L79<<4NaLD^C9ZCvgJrj5%_fb8OO zU*+<15OnbC8D-ZV%BK|H#;<;0+W6HUWEa0)SAM+;K?f*b2Ft4x!g#W%&1co5wPrcFGXKz4~|kBVm(1Rb2-0hXiF zpM&Y<^j5{Uar#RzZJgch!k&ET)oYfb&s=q_2zs*H`6Yv}YYwT>fk+Ph$R?CaFhKg@Dq7Nv~nnTW% zbe3Fd2A+dw_k!h+OLr^F_MY9T_;#MPR-Qd*XFZGWKI6{TTRLm^`W^<;X5zI0*@Qvz zBUwk~QU_J%=ISfR1upB0}*Y^~dHc&hbvI`UgluLb` z?UuRO9cXX&1$Vo{mEG4N=m5n~upFRx1uVCXb%^4pqF(&Ob9waIUOtqm){4=4azBsZ{zZ8Fl}6(1G0Jd+W55$WEa1h)JSaiH`lNTT2|4Uz;l4P0az*FG~gxf zMz9<{x5mZQ-OBPEE|!}*tH0G%eX&yC!bN>^@Eihb=4|<1SIcdb<%e7>Kj^GJ?yA1C zQvaBX`VQbZ1lG>ka;dB3UdnQJ7t4=3tMB5f{yC-oX&3cRg69xeZzs#*dpAmbUl;Xd zt~y>(I$m0sI{gEK&OSqA4Tm*zOz{m{+s0(-l}Genz1T#AiF?uRJnA-+3q1XyFc06J?3urPi6Oa2s%J<0xVl7=tAQ!d%J(T+s*JN4g(&) zi}Fk`ZNSU|*#*pVl=5r{Is{eG&2ANYyXU&wt*Y!^=%&1yz4Ger%EL-|0D=xd)o`<$ zV{bR&ZdX%wYq}|~ZLj=FcjZl#@|&%K)-xe^4gog+%QiK=-W$Pkn5A?kRF>~>vE0;I z{jIL*ibtn8@8qiEDW#*gi;iC4Ik?!vRsHiy{j)CWpLW$TSm}7d*^L2CD!kr)U^(Qr*Y^^b zHjCyEkX;td;mW1go$U^Fvpd4x?wjs*Cn&pPA?Pq7W59Bl=5K@L2*pG&ZJ?M0vI`V5 zluPeB+nwTOcc#7FS?+chD!cO`=m5oBuxz2A&G;jGyNlfIu26QDx+!02uY8re@=Z$l zdI&lMwbsq$we<=Kspass9ZJcrS|4lD=E3cyOaRu-cLOqwdo zOeRCJ}&A@XA>|STfcPq>Gqj9I=+l)p_Fr7x@5#@AiNI8v0EASj3 zFHx55Ju6oH6wfduk1O+?UCeg`&jGVX!E*4dy|QfYSzE&bJxLxA!6EJ8Q>xeZWkP8{cU@ z46-TEQy}Qz^m|}AIz0(YH>W2kzKzqFHla;g`mSA z%m&Lg9y;gh_I4M#+g+yYE^$-7++O(#cjX(D^0g3j2x_&P-HrBkH@Vy0uIz4gQ@+Dq z`A&D`zbNHDSp_XOVn2fC5bzPOY)8@SJp`6WJX2!Px0U#Fj=z-UlP;Ejb5?)cReiZo z;w+aDvgE2IFfVuxft_-;{Ew^UbCl(57t0mFbHJ?vSkAarRq8KvcK&>4?dLjc_xh@V zX*1ocgX}WhL&_z;v)#+x?1t^_=D6FfqwLm(pu;%kf#m>nO|Tq*_WG^@(*}yVAiF?u zy>h9**={{IyG8bPZ*aHURM~9;K?f)rgXI84Be2{yiH3@wGMBx++rhMf>JE@yplYF9 zz8``Pe%+_++MgiqQG6S}9stwEua+RY_|;zdRSH1|DBFPL;BsrQ+@Nfw_%<$g0Mo|h zM?rRRxuZ+mGMBv`K7;_7ZZCz@&Aq#JYt^fDN7E}gD`$e8>CIf>z|JD( zDkmmxTt1hmd?BLF*dxm?Ww}?O@ENqYps-o7O%VtbHiC6J6xLg1OghXcY=@Ks3f_#J zZp__IOki+J&BXTHsHWZ76@Nk45DXE#$uspwK;4ysu8?a~+Ob2Y4n0b{nMB1O^mHaI zJ-T)1+|I-jf42uW8s{b4xGB%UjRs((C@4ytV(u;`1sT5kiZA#0@Q!P*_s(KZrw*OF zm_6yiucE#kjMk5)Fe>{hXTX!@P()Lu1r(9O2V~h&mc?9>fo8>?$9tA`>q9A-A>I;8 zI#|nt(Bebyhm~}^*wems=SS%M*NGQDh3J6Ys@T)>5rTv+-|)KZYtQAEI+aQ{+7_S3 zZnP^t*OTGP$Y@`D0hf;!pHBudI?A%MEW66Gn=E_CvX?A-%koKCJ}t{#h%h`-He4q_>ZN8|3^9S zwj8~2#o4qh`o%(e#M^7rM>xG=W@se zeYB0UoJ$|V8xMwhzVIev0lcB1*Nc%bC_j?)MS`BWM6@$M7G7sA6>`31();D2%v>SM zl~iK!UnTjUNcyL;y;_!QBz-NFJ{qf;G8K$Bx?e#ddZ!nAx_0T_qbp`RF9n&2H=T`T z_WKyfHXTgMfX3u0#h!=x{b(kRczOJL#hwnGyLUFxujU?;Y|y9qL+H+;Pm_H;K7ilEM=NV@iE)txrE{yt1b{NEFx4Tg50g?2*;Ru%~$VK&ON-y~=2W;t6w zle2ZJoJHFNgc+a9_I6qBkmXKU?vmwhS$-kQJ+k~#mV0ISl`QvhNkg;F5gN{^@1?^> z;V`XsKM9AkPKeye`c33g)?c#yw`lwRk-6}%4CIsy&=VKSkyn;JS!Tp}70t{PWk!~y zmy_-CvRy&Soh8ePqAXWQlv&xbU0Ian&z9vmqRglw^_lAG+H^i8?0zx#EDQ5NGlHhY86Tz;d%AQrPvG`dk#m6YFmle4a&cyGq99qkS;uYj zs9fdpmCF(PPdm0Z>kmw)Zl%4FRuXh6U%3MQM+sOBe?CKNfj`bGRz@IRiN-Y}80R&@ z7Zx~W=F0L4h0{fG4=25`D|x*a#8YRYnAzvW5qkF?=1r9*5KXvC;+~GBosDG`A1_sp zds3&`rEw4DK20&&??PVRWpPjIUadQHZ2hp<93_KxQbsNd@m+)XC{OPY@%io)@s)2O z+T|ZW8}XNKDdH{nu%MS~Bk1KGkvOy!@%!4zvOP-LmpX`c#-p-)OqLyG*-4a{on_fY zmR)7}IF(pKyUBKUQD*g!WlvFN^g>B%_Y<<+Ta=l7M49!ZD1A@K@@ZK2=A^L)&%-pP z9Sx67_&+T!i3wN^6L1JGFqCkE9TIMkUBV4actr7vCr2b)f18Bso50Yt%ZoLqEG6OK z&uj394n=Rs1#g&`=o!O#qLZJm+WGTxiu05Qw0ym89VOl+N6J-af}DjDKbVQ1;Uf(FkIq;U@jVUV=xFgCBr2~tEA>U$IE)iwM$Ff{1%VkvJDPg&6uMlPC zN?ESrk{q37n3fOp;z%_Ei}53mbSp)M7^gaM{+^Z?wWM?TR00|g1cv-W7t*FW*#?W* zj#$hQ4p~lMa(c~mn;!G5lYqeUX6Vi-4(>v5ofZt*@7=ViV>%hcG#-woC1Mr1meB_HA-d%<4b0QNP1Y{nt|cL8<EO&s8)r_P&YA2IaZITqjh`#a^JICxa;9Pl zB~r386-tsfbAe2`lGHu7a*6%c%F72KQ(ZdaFA-<_KnY(VWClz4jF=fJ;WJZaxP;G$ znGs3PmGmnly{4qslJq=DuPy0UN_tGvuafk-l76+MUn}YLBt2i!3nl$JNxxpwZ;wvhA(WV@wo7t3~Bwo7FDLD_C4+YiZhYuSESw%f?|BeGp8+ihjLoou(4 z?GCd2sBAwb+Z|=QlW1pjmh>)6rpOgvR&kmjThKt<0TH+==EJ%A`hbG zqswJbZ8~>}oW;N54kqPaWOHws&Ckkgeokg{nHl0H<@Uz7CLC4HEr50~^2l0H(>-;(rElK!@&kCyZ?l0H__$4UBlNuMa` zlO+9JNuMm~QzU(=q)(Id>5@J}(0#MS==(m9<%hDIEy|2JGMnd$tjL-t=vnh6e}Say zlD<&VKa%uClD=5dmq_}@lD<^Zmr43^Nnau9D7>7PmZR!QF`>7Psbc0teBA^AHce;1cDTY8o7?UrRr>tR2Gx;f0C zt~N8MkK+t_(ryMl3Oer=X9oe=}f-6y&DiN{AA6znyLr1an80Pt=bfWLPDSS>yo z<+42$`C#YqRO)=;h4nhzR`{Q~4Q?8?Ve62#{^ADotaNi>{Lnc4`~S{}Khm?!W39S8 z+_q=;Hm&g!nknrzt#MJ(rE{s)sdabUg2p>_@6{&W``WAH_m*}nZQZ>zo)D9G3G_@KpF%uz$|a!IPn1g1f@M2Iq&52d9O9555u_7+M^DEwnd0 zA+#(!IrK(&MrdI8aA`}+Zg0sa^KgZwW7j-me70L*az2>(d`fBmEV z@A$|1$N9(mC-^7%-}O)Szwe*spW*+&KgU1UKi|L5zu5n=f2n_&e}(@O|EK=d{}ca{%!v4{$2h({;&M|{9pSI_`mh{4-5s6g(FEIrvNP*Whss-|xXcf`0}737!h}3k|@a3p$|eIh8BeM(6Z2q(8|#I(EiYY(6^!Q zLx)0#LqCL$hJFs64D}BW#6Z3lek1&5_^t4N!=uCRU|1)FCu3lzg=d972+t1B4bKlR z4lfI@#vrc`Zwzk^ZwYS;Zx8Rnu_f_YgETsb z^f{LEbIysJW09XDgL8-Fj>;XKJ3jZr+}XMFa~I^U%w3iHY3}OWHMwhZ*X6Fy-H^K} zcT4Wp+~0CvjINIMuQ{ydzM4C0?W#31Z&u#Qyj6Lh-MhV&BHTLt-C9Y9ERH7&{vKDfV;hm)P;xiP-P4ld(Tzf5rZZ{TnN* z^L(9tb^6yCQ0Ij@FV=af&dYUPtuwUF>vi6!GrZ25bw<{CtInu8)jZWb7nR*~vBz^x z{We`Xb*x!zy{ArL!g%VpEp6SSb}TkD!&@dPy}ER)-RThzElq+_8xQYodh{v< z0hdDP<$ac_mj7zE>CiFUwjI-`XNI>kiCX?+nRXqSMmJI!-e2om1khla4xO2tiGT4q zE)|ylSf;c$)3WeyhPQ9+WMeGTy${P^TYyZsJ2y=KunZPT`ma3xpW%Hu#TF5+taEie zzv;g^^Y9kC)``Wgz4ltaKfg}Bf_!E@RFN?BdL9|r?xp>u`Tx$&p0w-z zJEr}2`@CS}zU6Ii^m@+EF7F{;>;|s~Pptf(8E+yG+Ih(VR;(hhl9-d+OOTnGBv;>4 zr9Q_gaVNQPQIF>u8UWLON={-=EK;>S&m@GZl9Tuox9MDuXNQxV90QUY)WYKleoZyw zKc!EO191kzx2c8JKu8XdYLvhoI+k`T3^po^-`%ZCyKb#J`5S}M-G4>z{A;7}J39P7 z;?4uSieioXdqNN}h$x~U7jjC@o&*@AgQyhgB1O80L^n5K%#FsDOp0 z7aO`N*WL@)hTSVRq^Q`yt0>?9eP?%e_GEXjobP*{FV90}XWn<-dH=teEoaYWDJm;1 zFP%^k9bQsCW9*dZkct`OOG-z#ZrSS8(cMd@PMtBWq+<5y;oV0MEiIi=KDz%9Y_@9K zqV=gQ+O%xdrp@SaCDTUt!B>qVJGSR@Yf|R<{EPwYe9Y14Aaf>2Dj4v%W#HbQOj4;|5qI~=mn2HTC za3cOy;NQ5`hUnP`KK+LpqW2K|n{9|*B^3k5P3|>g8Uo1e9=L0b?b83t>k23D!tx3{ zZR5Sp;PmapOUF&dXygAcM+>})5%^-gw5+UndTCijr|D&w{tDx`UX4#4*EaId2uw+9 zES7qWE1#WVtj4mYp9aH^!J(`{Q-gk2R>uPnD4X%`=CZA(Y^$u`^7xCIU@eU(nKr(3 zR(Z5vNk#eSRxL;OomMnu#`t1vwrJU+b?cTbQI4KbR8}#%2vdg=T(GWig*k0P$;1|u zjJlDJwlAOa(V(;b$Ql1@r@Uq#eRKTu%mUBi$Q<&iK^;!(e*V#aX0`jYbM@!f&N{yI z$U?f2o>}w9^PMm2xqr`DU!VHv_CFdPe@27Mrz~&{*Nu!?)$idmA6i*hw!K%Iejonc zv`%>wqp)xa{XgwCG5!vJLLt8Ir2i`(*WcA^Mh&B~KAyb5%RP+BO3a~=UAep~zJi$9 zB&*KF=>c$cJk7s9-U4D&?n3uwcK z9joIn=4O^ps|uzWz~D70MrDV5{EFkWWKzfK1m`V`c!Ia1K4w0;-auXZV`r>g#4-JW{6? z9t>68bUM@#FRU>ttpWHo$TW;b3^fZ2jymRY$7xjt?1X-+so#h}_*IZHjFaWm+x?n( z`spK5PrN+`-)o+OU(ccEKRi7fCXwodDtmr+bi0GPm7a%RwXks9J@NOvNS)?-H+?+n zcqeuIYczg+;ptdC8L87n@2F1&bzDOouNi}1PhioxBi2R7h9)JNJ`>byE%kc748Iz8 zP`v=Au8BOgUg>GBqkcmw@aq8jxqCkK`;q#UPpiV^ER1&-^&2@Czur4T-|@Gh-yyx9 zI*y);UUyTkY4h-Fac8wJ{fI6#QidAI)8iiM(P2J*)#_pxNx4vPl%R3yr6|8D=?%v~ z_fogM3-D_ly4gD|4b)Wcqr)Ik>#5g!3-RmHuKJ$$DmtF2chu*MI^sP@M&k`a*wBO*&jM6MeV zxp73K&b>}Vd0C@^y@OzDDA=bD<5ydJ0;+KVrGckBes9yi@1P-tgM0QaY}Ll7{0Ir- zvES^hV~reRVS~a#y2j+|rsBfsrTo}qIYJx@H~i!nSN<=Tnnty@YJ}FUwGkSi`=w0^ zOG@!@Btq7cA!`~nHUAEpe`6YMc<z2 z(J-yj`?b=HEsX5yIEJcg>#0*qr@2RPnq53qgABSL<(HzkOne+`Ce2$e1?5@@*O%d% zW2_oZk2MwYGn_buA8(7uag%A&Qp+WZE?pYXvpFO>0q>edzcYpm>NdDLPuh?{M&*74 z=Sdp|=M}??X5jwpRP-3{jB<=K$|09Vt9IHb$D!llp+)6|^Z>EJ4-R9b9ODO{wo7OZ z28^A`302u1+3jd z=P?H4QcvcdV-yD)YZ^bg!rE%OjzZAOoAl~?HjYKk3d=G67~a48ph>gK2jhtcBgR5+ z7>1GY{NIcsT3QcCQ8~u-{>^nMm8oN=V8`I4_yYDX{AAa~sVQw8$kVA>2ef4V9i>UU zS?8tic`cFio&pTO4}Tk#^w2kcY8u&YkJfsJhUidpME~xPQ$ly-yH6R5r(BH69gd1W zp*O%-(^~&9xQ6s>4cs z*#6Y|wbyLN8`;0(V?-K2b)AmKJM8@~7fHSYh}qk!^0rUd%C{GM-zDD?XAMro5oDU2 zYJBv=b7pwTENWD)f~;jYM%FZ5Yyl$e+cJ}pt&#l~4wMM2hqdhWBgzQ?R#%$^{BcYX zCgB5T5^4q7Y8tK89GpE^n*%yX9dL)!Ip$!rV|W$P-5H~j{$c<>ImTXEIsE4YsxkYm zV5*7}G5r9XBF00*4GK{_)n4JoqHH58i=Jt%q;+1?_^+E%EB$a=2exL~p{bXCXle)J z3?*}LD;#gtTI-LzXBN!B*`*`xPRIg-&1qtEDI6$2o)5wIP-7<+ckR-uOBe6QczMFL zKgD4ChgYBi%VBa!``k8t%-(>;zSq5Tt#3XSfvZLKfq6OHT-eb$<~>{1x} zBh;rHszR96Y#iU_W^} ztH^B;c^4w%!K`yCrj|ojQTw(R+Y?Tr@Ke+H%boC6`juZj^!uK!MEHSlqq4|Z+u!&# z_H?cjsllC&!r0D+G%j}Tl4|O*5V4ICG^o3#hfXJZ+Dt8(UT)6`ov`tfeI?!Y97`VpaGhQ_ zfo||GqUUM>sS#XuM@dtB_>dtLc+z1iTIq3X{Nxz9RU5POsveK+Ta9X^&>GysQO|EM zt7y{LGIv+{&IP6KNLfbq0_WV0BS_&iT$;)xqekV;z_JQw_3TlO3xCSuOHX9`5zN=} zN&h!DIGvl+1FCLiMDJW0-bj`8d1<H89b@Iez3a@v1l+w9Uz76T#L~3qSUi92+Rmr!ork~ur^^5%)kW|ZES*`V}m?lOx z4);}e=PHNMT;%&bL}g#(q{1$AWu?+xfpmA{!X8I6Z8-f{{tqL&N$`QG&^>C?viJeR z8hRMW1%~hl*WFf zQPZfKethmbL_a>)L8hlW2O@p|(Ws<9$>I!GdycMHQfe3d0FjT@_!rNlxE&ndXMEaBzL1)UhZ#!C_-}jc<#CeJ>0nd3(khx>PM7iW z=~bh$p=14mt#o-lZfsdu2|h>T9+6|bT6U!m9*v#0m6)i3)4^fdcr?H6P+Z~PJZq>e zxzPS|3FpH^z7y~Mw!{Ue3Pd~GY24)3II<%=r%$JBhB}UeecDD0rikr3wj|EyI-Wy( zTQ6uWeJ_M-k>fhrukpuI;K>)3aGm71?)7c`%RxS2%Gikx@gOo`vb$a*l zZytXJB}L~O47I{>F7$0Zvm@pVVd*md4mJdP?_B6~ctzX& zWvnfZ>A7IjxAw`ti1;saI<#qxRgZ@)rx%VZD;!@^PRr{-$JjE=Sm3NDnS$kXiU+j! zcIK|AjCQgo9RKbC?SHi5%p}A$j`ui*G7gt8m4lqNb)9LglLnjA!;a-A-l_0MnZ?t_ zJH}a#@y5QG|HATeJYGvkzINtyqjMmU!k%{g*9EknFH@oz103I-_EM4|+BwZT{F^%u z;$4sw$OZqb)8W)W%lGzlPQp%!k(WC?o@P~JXX2v`?K-<1Ro^iRmr;e&p@X*k=t{6~ z`q+{(^nBiNX#2k$?%~skO8!NsOB~T6Fvn= zDxW)s(}D~YbU>C@8(0E3Ab;yDui|O=vq5?vj8WOg3G+pmahBXsCY4N}w@TpSr_-yE zy8vzdw>YNugPm-#Z0Pdn3&+wX&@!7>r>nlD)8$nmZ@}=bSnRZ}ZOb1B72&TO!yQ3} zSQqD5AZPs>r^i2n413h+SaM(H>@n{K85+q@^2oH+8Q^xAl5Dj!4E}LyU+C*!1obqw-s4j1Ga8iRuzdrhC8BWj?2M zF@W<#eCZ5wTx&iUr(KY(ce>pskHFk#j??&)_xvd7PIavNLaooL1l_f=+3DKa)m1W{ z&Lw*sOVdEhIrc6o_1YhGbBuDK zvj-kWweto>Mw>I6bXzoUU2UUNMH4igKQwD-q<}V$?>*EQiib)MAO8Epj2{>&qQK)Z z%*AS$;(?I~<{W33*)+^V9)>oLbeQQ-Q`t6RAV_616f_*yF=Xr9UZQ2LXpt+L=ZdDe zw#v$Oa5L-WZd=%`0#793W4hHcchS84wTIC!t3~emc~?iVy&!5e$M$mCo)@*6V*5JU zzA_4A+n7=1iRgWH%SCe&!|?CyZWOUon_NnvJqBS>RLw}#nNk!z63(Ki4pE&Ts$;Hb zpDWrbMcrY7TB)cZDeCAdYJ>D^8^cJI)m{oBRaRRmh*a5`pT?Q@Krqgnsu^W|4k7?S zA5It>R7d7Lk$LxA(JfbW$rWd)I8*$GI#D&!9_DRLw|KB_cq}#jFJzREMYwAZkpm7@aFdDMeSp1hv|9jByp| z(=l2K;^`PA1!>bUmNTD=U_2dE%_#F_h=7Fg%^MQN2Gx;y2{NCUD~fYPk;?p9n7sS- zL^pG*7%5^dc*ibsQ#Y@qqtlg9qw*g(612fFDKc!~nKRCYquSFavlja6LDoXmjI`W} z2#~OXC18W<&{7I5Q**_IO2}31f;)))5iwY zq2prcn3*doaz&YvLVs)I-MMGFQmhJXPRfo<%WT%N3E^1_RWs7^7$QKz11td>REL(! zq25lr;iP)L&uHKu_9MopDUItDPKv~uVwKK z3OW>3eu`_+u5)WtvsTDiS!7%tHE+(vb=B(V+5Hf57d*|Ia=k~3n_UV{M?UOb?_#i) zV;dJ}e3WaAp(xn56zt|)klSC|XidM{U~HoY*>=Nb-INPYdEK^(8SOzUGoornjDAG~ zg#R7|AK$4CMr*+6j$E-?0XiW44$9&;6kb4gNNtOZAFx^LTs~`=&mpujAF5`=hyDf#eCSVYnGe;$=bzwnU#{4cD>f)Z zwWRCOvdBTDNRSxhTAV9+TR54Qb`0jT)rU`vVr}#16Nk-u(&h66^GTqU`A{_@KCKV|dWEfmMAeKKbw>m+IvoWwqB>{fP(o@9en-+KA+}_j}@Qc(r<(;MxyZY`4oDb1@wi+=UjN2JJXKSU$}fMyCW~4 zk0oRR6n_2goY_WE^e_C0od=t>(fsWYYJ@E9+%c`rZp9ctV6&y)C9;@oSUd(4W}luvrIOV!tx6E6~cssG1S6C5QlG3s5jIs)N{{AohpCwNyG?Ba3Ay zytw|*)|Wx|>+I{wYvE}gPQztH)r~)Wec3Vo{`y)@!Hp5f#;=&h5@SrQaG^tVQ7kRwL>jziMm1*1^-viF!|f zwOwGA-I3Qk$fG-=Ef2*sK#= zTJ@OLqiAJXRLzLiJBR>UucBaDR0k~qTFs)OASzN(kyO~;h1JZ9YB$xJx!SD)dyUae z^^^^eZmK7-?c7wqIP9i+3l{Z024PWD%}CUjhyYO^vleVn9irMnRGX-16&0r_MPI=L zwc2gNHm)LlHd{$SG@I5bQjm75tvzS{HG*;GRLv;!pAZ2F@8*QDL3L!_6`6OAiqoT_ zQ&eF6Z0=exKaW%hg*x9W7X!FL=Hd`qIf>FCDN4qzyj zM%9d@WmjWqha72ChqOMB)+;J{M8%m(S9O@6S(}tzt}cC2dPrG3DQ8Mq+NAX5%#T7a z&YY?lWnNEap2G=aQmBs1&q3w`qoRLQ^i!Fi0F!q)4RkZN`Xfcm2p>!Pxv5vZ7Bs5d z%N@*G>LWaBp=w52qKE(q4Os#P9GaohmH%NV@y`VN{eTDFdYIKv@hz;XVIOm9xV4e9E-*?>X=^FN%6sW|>RDvODrFcA<;G zD#3R8eZ#>Ntjzy>I|MfCBKLedof!>9D>I^MMvMv(0cb{|;PWlj!RQh&x;QFkDnJ)V zzp=6yhr$c!VyTTUP%hH|6~WWIG!4*YE+BoG*fIF%In#&Fc#3tIKc8aQtV>-!bC}Nr zv@##6X2hoq5x{3M3g$y~@L2>t3!`FwRLoU~%B5?CEM}naB3cMZ&PVno8lsu-G#5v` zd(sjYk!5$}H8fvxW=3;;7|o(!OZ*vK44bvsWpp(&nvGUwMAeKK(M#mO=n53fi0WW; z0~lQw71t_2S4ltoPXpwBH3~1F>!dbbLpN%G7Q@qAnFi=a7m&V&>=?}FS|2`3DAtYs ze3rsyt#tX|9ZAUZ8niMWs%FIJ7DPax8&EJGs)NrR;Ild^ZdH74m43I$Vl@gcpViRg zETFX-pWESSu1VX+*1CKwyCW~4TP0)y6n>s}?)lt7(bxJDyAw8RjZ5rKCbkBxOpK}- z5!-|aAa*wjCPsA-TMuIQC|sMR(|xkIAB7heUMx$W4tY6k(s2C~p613hT$@~6`f{>k z{C!$mDEKCSS`WZxZFFgEU|J8Nm1$8mBU;-K0kpQFU|LiMt%pJD!Km1xfc;DQJtd2$ zQFwtpsI9L@HDJ%c)7+Z2|2^sgv+Rz%zP23c`g)e4Kk85HIoPbNF0n_L*z;&*VpPqD z*uN10#9l?g#HbEp+d%9Ih3hTp^tLSCLE**qgtoq()^NQGPxGlXTu-~W^z~)O`1|YY zJqrG`Kdl|GSx>pN{>8N3M=R5!YDTn@c!LROHA2C(s191yW4%PRn25y0;i&jCD*jO9 zOgNY|V&+@+N2Vw}99Au+?s{2~m^_lvN5R83M*3v_XLSACH9$ExVf}$-KFIx8+vmwQ z?Nedvd%CTQ(pRfZF{)J~Mpc?9BTl~$+b!MCGz|HT>rpWh(+ti`g{m1*ISmmIs3i)f zLUm9%0aT8UiMlaSCnjpg#L+QPGv?eCI~_jei81p#8;nU{j@Q7{)xgxjw(}fd?U({{ zw7Xdo9>I+GGqa-86+>GmR-q$XTsrlcPB%C+9jazTXAmNQ4!u#B=};YXVxW^76OCh{ zQA{+9iIWtXbKn4Y@-ub;amjVL=(|i~iG|o$jU)?VV>Q&aPm*AWj{THjoOKPxAgqh3 z8R;rP1n9bekiCm}nmpZI!6Wuwp-vqMDPaPX3}gqIsUYlWDb&Vf_zd zO>NQqV{LpuS2|8-9Ty@l>!4~zI_4n)(x1)gV}t6@(FZzu#YB&oI5Q@?#zbc&Wj-9t zv(onIUalIe2bepzcg~b^#J6|4y6d&GoEFmLvrl{1E8fRqSZ7sPud>BmuYH-v)o^AW zRLzLTDntN=Whi*PQXM>ofX6v8F)$|j$3#B`<0e?aN}JbnToU?X9VkKYV(qUj(0-DH zHnBrl$ju1MLa3UNkoAZFA-8k>*q}OuTmT_sVq$bmjEaeoF)>_e*#HNxmNBjtYcvvd zZV`>r#EjI$46h<)EQ{HQ$Sj7c8Hsre5uo9ptN|NThnUF_Gbtt}#KicR7^jq2utKOd zE0Z)O6Er2`T_toTIV|_KaaD9&$T}WJT-HI=jC8z&2uS}aP9GaohmLaSxF{w{V`8cj z@iI(a5f`~4^rcnmt6^#t4Hc~66@+CCRLw}k`-p(l-{jP>L3L=j0vaxhi8(PbJ0@l+ z86UvvT~(L)%b4TJux4wEYE~5?l`P~#1ZE*r%}B_%h=BY*{7k=`S?tQO79m&X(6>0__6$}9@SZNb`pG!iY*i8}yPwWP5V(*nCw29rq zLRug&3!!R8LQX>j2x-IlV}t4t@)(3{jfsb2;z6b2bePP?(=JoCx`i!AwVlzU~3A+5)&%&Kg0XVqdD-QdhHsG1Rs{)hkuy-@J1QXMd! z28@5j#FL7|0JH;g+@hRI!9I-vPSpot=D}ut5>ty^ zH6upXBLdJ|je@6>>R_}RjCRGu*D>*BOzc#cZjjz9WU&&37t<~c(>@K;jqo)0#=KWj z`!q~;N5=HEhUrV~z`WB3*(wUW&mY-MuvvRuWP2Fd&1hw0RLuz4-G~5Wx1(TWR0pzO zfb6H3*soySBmM4`#d;K8SU*Xfd}H^Z25SR6%>!v`>Yxit-+Am9d=lI5!)GJKI_S@5 z6KvK2m(Q=vXER!v4^=bbV<7_gJb;4vP#t`-;=P0s7k|aXA%*C1>H35$oq(O=qfI^=`vUlg}`+;p- zS{WBrGs5*5A|TLvC>R&jfvYKS<;R5?7kP0Jk2|;C{v*9Vm&HyLUSjzmM%M*&pb{Ff zFW_l5k9#k9g-gt`JMtcAO6-g*FV45@_&!b??db=tFDbC_NA?wLR&y6wGe-6`S{WHt zGeY(=A^_Q56pW1OK-K}s+QmhixM-z#{UTj|mBj%RUS93A71l}Pbr7EBscF1AxxDlh zX2)P$Z8Ti1d~p3naXb0r`Y&wOsV=ULjO%x_GA^oSgzGrGArrW2qF`K92d>`0)iW-- z$3?fe=%R=nFTLx@;sg|4Vm+bCSz%{s#OlM->>Kx9d!OYJv+Rz%!n#ZBjI5i6tcwq_ z6Djan{>V;(&FbqS>%+(zpp}tPH6vt6L;$kJC>R;lfov#{4UUUJaWO#gGNo%u7WpW= zyar3De3&1h@hX6)IXsQm2$z?>!t5A~YmkO(fDf*w6nBI_u4b@V!(Cj%7*}(&GA^oS zgsT%G09Pv%jEm~PH6FOe#l;12F(xiXD`KZf@6%;*1`02+aZu%~u!$P6&hRuRq#gAq zy2LEIBd@RvBz8tNMng8*2U!;iJkcLnSJsMGhU-EfTtg^s zg+H#Luvz6Ut}@0o46Tfdsu|%bLImI%g@SQW9k{Lpt}Ei=vbdNN7qb~eovSHfmp>(W}rwC19fX;C#J zTGt^0XkCSZX;B@t?!W?D9T&I8#m#ZCDlS$kX4lIOH^^cI3NN$O+8SG{FBFL;%6n zD3~DCLGXSM+#DAh<6?bW+@tW_E4|mtVgm{&&$=NY@ z$!*k#t=G2i@u9bg#(2P=-e%aWEiS!(GQIoI%Jit35xu7o0rV^sOpofI_c-W178hF; zw`Zi^v$A*&g_ql7(BmB1wrSj+ho|{u+r9o?s|1p_QRfH6ti*BLbkjj)I|39Z;SFlxGx?ccjz1vUm@Lm&h~PN_tTvvICyx z3u#1NbcyII$&TRx@;>!{(I3bMuvss-K%QqHAEK3kP&FeUUn2s5e1?L7P#r+F1IQb3 z@tR`tjr7|ki*HeQnY^K`lD9P`yWwfR75Cn_d)sAV*&TV6yymk?_E3Pg{h{oI&3em) z@^6N+53LM^su@8!hzNl4BMOE>bwK$5PWo7 zAuhgCWX8j4?u*MCnC<8W=FhG?>qmQ~&@)ay*o^3l2L8SozpU@vM!csi*z;sVxQP`k5)cpl@hvMS*xcE&;n*kGKOKBZR+96k(K6AgL*?Dl~H+S3q zBH=J+J`=$>bE;;P`Fun`!gDxbY)~DU*Gk~84iln!LR3qLNW!_*vjA4_ywpgjJ6u-v zggnmEyi~)s{fL!2FA=xVXI{w9^Y=(cCn&W=7?U+pH6x9y5CMU%Wog);Iy4>+jdc^E zPD0dH0&ju|;k8Cor;e0DBCXo)wmm!bIP;qkj5DWdMwvf|2uOH6CyWiMBlBEj z-Z&u|B}Bu7I4L3OtNb5=gLi@&yZKv(qCfeWr*XB$5yN zMOorjjK>nGnvuj85CO`bU}e~#IwUrO#DauKB}6hI5(yDg5?_RaS7L!CF{MdNx>~G+ zD>3Fa`$(*^3Y)XgS1>9IrD{e(cOU}vy~+BpL3Idi1EH-F;*^9CO5*#{^#fUah{Ahf zXa&Iw=(Ep)sM#LxDs=uP`XhLn?GoO@OM8uu-H}g~r$`LEf`z-SF0MYNVD0H!+p1sv zd;*)*E}?Ebw`E43qLmp@H6up55dmnvK*47Ts)JEyFgiUUIw?SVq~Bgy>_g!NbhtR{o|K~_UbQUBz7v%#rL=kwJ0}|eY;6N9VWq0H? z)W_vw^>Vk>8p413W|#y08C8SL8sIYO&y2Fs%8aO*5u@V~0gQ4`Fe9pi(FiaamJmY} zpnB5p1XmAJ?zF|yWZ zWn@&%2w4|I0J07!7#Y=ptOCf&5@LEnOjEqNO4n|(I1`1JSDBQ=t7?|Us|P&InQ6Rc zxxDmMWyj!EHC@9s%?DR6iaX06S8v#?nJ%swjH?e?85dPE!ZjQbfU7?W#zl4Dnh#ua z6QVL9E>DO{6|oW0d!#JRMd2kj7pj~Uc9lkK6g06?Ps4zRDljXxOZUF0uuT?0mE`GOA{TY%(GM**Fx8jOsvk9gtm{5Z5Hc62mD-et`r)ox-uR#PP ztX^G1b!6TgnKw;}{G>3GB2OhxudFev+sX5EG=(_u@_)Rq zTd=5gjwq^TB+7nq%m&s1bySC_wh+}iDOx5)3#I5mQq)|Zj@GUseL7l7K|CETq#$iN z+HvL&Ihj*6qs*U01SD*6!q}iXGVg-S&q#{XlH$~)=%A8+4py_SJ{@Pc$y=u(OJ_Px zmD%%jbdcHq@9F5uqMpYfyvC@Sk*I$o0<^r$TChQNi0TbdJ(Hq)Qgl;_-hv5gwY{UK zt4N=Y?otp>M>i=*n~px5`P&G_nNu~R%s)c}B)o$Y#s<}q`5*77;Rvlgmmq-8H6K*Con0UK0@mf_GcG${rv zA^Xto6*ANnqEEr#BhxX0b$o~Dtb?i<>G&@qApIXXeQZ!2ItroV{G>Q9Db7_=euv4s zbD!@@vCh-x0GNd}R6hli|*%{YB*P#rohgN`{#F*_+{DJgBGYdcxcD{j2krE}!0@MD0LN%y8z2Y8xS zB)vzAN|%CVcjUv~Y!`zy3)|^0dg(~PDw7~r^`_OSuvu3m)lI9*nNcUSG9#*H#Hc4C z08M8Uy#G-hj23~>!lan50QHi7y=Bn{g%{95scn(*Ow?SW0qP4+b8#A=B`zR+nb;K36lJv(d_YsG1R&HalD9bh9u{+;O!bBdTWlkI_W*S-R>f??2f#KR!PpxXr&J$ezDH&{*35FIo4{I z(QVAA7_H2Rsu?jVlfo}V!HlR5M)!cxT}iQ40V1)W2!F<;G@ZlHXZ1Cs9FTz>x^0}A!%*N=U)pl4k``WmuhFrO!U_}oshp7rNLuf?&Rarr#WeCUNZ%!jHO@!5n3;ByxW z=0kPxc@2DCNs5;gpUu)Q@a;FRK##M4-qiT;+i%`TJ5Imp^0DlWyntSkkO@%u^}F+| z3%~y6O@Cti`kOagVy`o?2cd(BQ8goCPf8M785Gb_9mL)Rv9}d2`yDy|lD_l`9Pe^^ zTU$==Yq;nwIp&TuT<^QM^yOs7`1`c@#X9f%)1uenSUX%=?=dZUAr8}`YDTo)LDDmwxt}a_C(+USOYT>+4Gm*xT?lzeqcVf9V3V?2f#?J~`6$ z^$tb<(x2G7uvuTY#C9^V_t473sG1S6ornNpAERJmR0px$Aht{4`a(K=DT}XAcyaC0 z*4I7_*Vphg_om_6=i<`WmmTBpudiZo-JeYQT|IGzv*&TU({dlD7>vxL& zn?JEXV6zUo#11gALuh4URLzLkQTW4m5HtAC?y*625c>0w2nb5)1qod zwDJ)FkaAJ*`l32$H8gQk-4yjrQO^{|na)l10$9zurhZf1)o#@{Ny*G?hxahxzVsE*9fK<1~J z;#5;~P?^)4q`b@NG&ghWRHTR*;bUnBH}$I5f>mD--I=vaL3q|e)r_>vLIg;d&JwUe zb!h1hE!|AfMG3hW?Oq|>Tp{`tbU88|Jy^$VL}wjT%}B=rL_qqNar)SxI&_>39cP)M zk12X7DGOopuBNkGDOMkCPI?`gmj0~eDuib(RLw}s3PgZ}Yghs{s17ZIp=FRM1}Gsb z(e4#8$Q7c`$$%r%F@$y8i0G_?su}6H3lWh1ZJa(fs16&kwuFNqm1>GuscP_Qxn=UaN&mUX^+ zz8%esHldXnQ8gn*TM+?h)GN5C4n`BeXuK)LDL{`(zsF=juj29o8ZWi+=k*c|5WQT> zoRkKr#08`;6FUYUJ;(X*d4gh<`15%ZHfxg0XCm|2hF0c7)r|POf(YRA3<^F=P#t_K zz^BX<(@il=A$nE1z9x&;QFsxRL6Y;4eU^sk4S1R}P4AvG%SB|_9eE8+mzfo~ke6BXdRf^9~((h+k&b=Wnxs#h*(y2CUyvcm>AVTYz2s2uW(h9 zPT8`kj>3!UdTlwa(r_IGPxHn!T&rAM`f{>k{C!$ADEKOWS~X#_Zggp_WLmY*%CxAO z5v>yt0qg4+6ikcipmir`-ENB86tMcz??hRggu)B#c5QvF(}2;7*37kO``y2kuCIm^eVsqClVP*gy2REnu|{ZRVpPqDSPBt9EQW%KQ60oKfY`kXSH5&AkVR7z zUR?KT>ua-ys~J4aO=-9`ySViAWykpY>x*9UW^VSUC1A5QxwJMitrloyT2#%5Rw*KY zRxt{uMRm~n5ww0V#doIIYl_{b*rmwPE2_+&O>>+5k*PO59QK1t!1~T!Y4lNWuZ@u& zciU~!Be(Pi9@Z{2zf7MN_xrs}R{K=g+Ic~A1xB@gHq&1aEnB*u>AWENC#Et3&P;`> z8Bv*s2%vHa3Z_DJP&ouDznkJWQyehGFA530kqX4*N63D}<9C;bz9N2;IQRs1K;j@K z)-RF=L9ze7=T8>00D)NuRWlNDJ0d{HO3oh}RELlnsa~RbN>odUNJ<=5LhgXotd;W4 zZS_?89Vh;jUoAy4Fo&4hNJ>rZ;r}_c>F?lMhe54csr0FpE$-CTOp%bg;LJp*nh}u) z5dncVpx~*cI*8N*k>gV0*pxUXC2~^EO{j-p^-k?^E)MHhFmOI&A0v4X6k5Rcduemf zij}U->z}RLw}oGl&2k@_Z#9d_EdB=l)*B|-3E=M)Ko4?9AV&=zNV7P1F{ zSqN1#5>gF+&I=**awir-bqF~VLb|3z=ae`-B|4=WsG1R-&WHdgZ5awSs170*h6XSzt6>9N{&p#-DN`efGC)zL-OjC9c(h#-ev z#>C54zLChB30)N_QI-evvDwn!0baYW2^K}JuU6vAaQew7JQ~{HDW!k0DWv(b|4zhF>@ocGz7BPLSFg!0O z4!q_~zc9KOLt0l>S-i5vUA&bHV>X<5@lrJ-81oSUlYAKpo@A;6##Ml^ASLE05)04{ zL~?G2(wbf1V$j#@Ja=yGtJ+1J>OutIRH>R#s@Ed|QeDg$VuR{PbvaU9mJ&--VzJ8h z2AIt2(@reQ+=Q*A+Pp3Pe=={YFr;;Tm3fmb?z~;cFm8e~!=P$LFxDXg7~F<}=Z)%s zaT8$Nm=Y@#iM!AaMB2RF=wi_4ZAF!NyO~qH8v!^~s%DhxLx_M>H*kj7pgK~$8>y~K zi8U#4M@ph5747Mz&}RWss2FAD;Of1%*1qdItO0gwArVslDtOo{ah#>=pRm3CQhze_@& zz|HOiS{t3T^*J3&0aLS8{&7DCmGgwSh+AmmNX9~)GM5DP*cO^HWR;vuEted+pv zEIvfxz4P)YlBDA(z0CE=6t3j$|Bn4*c$!b7@Ig%i7(qv#CtU!R-I01*k7xuQ(o{S5 zJwK&jPo@B^>eCOO!Dc;?QcpiT&W!$pR%S%ij2O|IfPm&J6g=5f2cze~=-HHbS^?T8 z{l1gM_b9x8o|W48PWnq4p#AVPUrYn^k_$**A$APDoOs%Y&rcNVC4W9Y!)Cqc@_B*z z{DM~IL)DD<)UsbBfP(o@9eh3mpHEWaqm=j{C3YxEM@#P9LM(G%M znxChf`FO66?c$$BvydU8Ha*0`XM_yqEC3Z&ktA^}nA7p1z;J^Hl zb%)LR(?xcOk@Y|;Bcp0Y$j(6oAnS{Qkx?DUYUcM6N9Bv`e36y!+$tL^U5ChGC<-sH zqw+~54(!iF&76Gqz&;F~=F$0HUOD-6Xol1N+WHE!V=%7le7@<(cQUdN+quo=9OH*m z+?;&hWBdr%tfTYQF}_wlsT_$`#zobPa7{o21UerDJ0m+@Lsr)Z*;ESL$RF7> z*sPOXWDOZvDOwpBRWm|%6(Rt_6(|@P)qyMtWQlwc%NMzd7rm$pu2;)qF$yoQgp|rF zEMMcb1fFIpA9uawrNbz?bja6u*&UftOkuOotj>5~RrN*e8#^?@snr-v(6^F*CoyN%S z$c$QOjGFr}x|4#n^JlaMHmj}6s0}k(i&kbt)r=TfhyX@gP%tB^gV8`R>Yp$A<%_=g zqPN2Ixb%KP7Ehw^V(Jf7&aO9D!?X>a<~jM^%kaS(Cc7i=di^A8M%GtD*4qc!zbNov ze`HU=W}V|A8^p+-Mk^zuYDUQ3Km;I@FGRxz)q!j@kd4Y0BlE>@#p_M!x?L9kM&ac( zN=oHjuTbOl7Cg-{X}k(uUi!h^j={J_YPg2`;Ch?l7W(6Q2R3Vri|c&G^)6Z&7gaOD z^(7*J61^>rR~XfSYZ`D($rqFJ#iV>OAzzGF(7uu#zLv!|D7?_7K$x@0F4Cawf~Pq> z-+Ke?A{UxvcjQGjS(0aJlQe1*wC(Xe1iz(0F7hY18#ZgYOR$s)?m;UPq-sV4e?tTi z`~d|Mq&f&*27+_)#q4}BD__h|`2H)sf0xA{D7^UQNaeidDm8qE;AviwhOg4ar>{9X z2Gg6Z5u2rL&+wu5Cyi0*Pwy|-tSel4movS?Xk~g-&4?boXAJbx-#d0S=v|dB7AS82 z>%C)FL65WSmTKJiy<P}IxD zsG1R!goM%<1urS8V@X{PD9aU*Jn58_g^9wul9p>LX{AOa1y6HD8j+PQ5q%}uF+4!> zssBoUAoNx=YlREs1_nZJL*rFK)r^3&Lj_`AGzE1?Cj*sZ$~iBoT?dR{s;i$KZW-zYm|+Db_)MK5xKg9dP;l%6#5LEAydhMtnX( z1n_wq1@oag_+%B}zXvQ3f8~oq3em^X^%Gfqio%P?C~((M^#b=c+Gp@IvkSaCPW1wH z8_lvi@*4Wf0_{S< zjHnJq$AD2zfv8pB+-Lkj`t6s+k0`u=asbG=&sbLj^fNroV+(M|kw=yZblk720kS*t z!l@;L(6)l|D+Q?Q59I)C*0C;>It=9?S{VveGlEj97DF*mFchi-%0B?*JH({Q=|AnU_0ni0fP5djceqF{(r2gFkWu|t7qS0LIHh*pYYC+U5fEKWz^<=6pYowMQT z8pqD?G*3(8c)H8cayrs#Z08cQ+PENFxy?SSQM<}O)&GIAa*KhVI-`%THoUfR z?7*xu8Vroo85lW+2-X3;J4f^q>qpopi(>~y>YAHISPuVY0U zqKuRWrA70$CU8_b-W)Yz+uRz}jLH{bw>FKScAQ?fCeDVnp0%DD@L$?oS+6F(%X=wh zUNoZhqWLSS>j|2%E{rdy?Cz~;KseOb9HM>>Cu$B2;P6VyETQl>QTUTIV;>k_PnnmH z@lG-})Qt2X^s6az0U2*0r~HwXvU7xc%w2lp|xk= z^TFDL(P`rdfY0UGqs{PASaWEZ|g(Oc?BXwxQvBsqo!H!gqr$KvsarK4VISu`pspva@j% ztB7RXjArfV7QxYNjZsq`-*7Nmt5Uinc-+-t4#gLZ$Rr@VHyU#(mO%+->3GzM{r`5sm>Uo`)#_#j`L4qIeZX9~7^l zIRwSKDy6rA$K4(_?tA{@?g$_Eb2aX#a1224F-*QFj>(E-?erh_i|}!Gt8u>x3%X%qeB8g(xPOENKkOgeh=#6^qodB{Qw=xxTz#p@KK_I(n`N3t$TnoPx<$a3qq1DPS+fVYs~-xlPE( zt%Ad!5*ogn3g0;-{OPa-2vk-`>K(9g^b)IIQ*HR;Rmbm14F|1hb=%@zo3!% z(rKg$KP)8tkkA-oRg5tqF-F4{km9J&@Do+|@gd>Ig~ph!VoVKAV5f=O@|KLxD2R|z2oQ$i*JWI)Q-ip8$Aoy@l zPLar;Fr7JL!i3_o?xi!P;a*3UbB82`8ybxjcd3!nyuOkePo2^ew8tFMwi zJ|yY7!AaMF$#>~RBDG=aKlWn(jE{yfOi@i`_fd2rj6sUxN>MJnv_0B04UJ(7NV^eC zfoV5{F)Zzql)XyYpnbZ^trPr$a_b0NmE5ZFJhxZj)2JpQk+#aF4Sf-Apz%qxuNt~n z$k07t3s{|J!c-+Id8e(b8aXYiO1U~aE4!ANvpUa$F=#G_s-(|>R}im(umxn+Uybaa zSwCg3k{PCJtQvky$nc|K3t%=1rhv>ws*(LO8?NkrnO&$dn*_fgFcV-4$ZR}J0hx^p z9l1h{d{M~ArNQB+hK8?H;V%mbKPNc+Y!%+0>nvsW<9dx6esRd~i(m`jx)7!SuJhH% z{+Z2H_9~f0vX;RZw3pnZl3od~pv7{?~7k{R}ryVdY(Lx#T-wg6_g z!xWI&ZE9ry%x+QkDw##H?tw9g*%p=beeeomwh6X?%r>Zz{WH5)*{fs*W|kU$Ysl~q z!xq5oL703qqZ9t)Fa`;KMveThkddDZ4v*|#RWV))iSYt#0ogwn96plu8jL~NzpX~z z9y0P9!Qqkp$127L@C(RrM^K1JL&Q-P% z4;=R|HLm~8c}UrPcw{5450C0-4&l*E<&_V|fGISCQ_h1aYzpJb?vrwJ7=2O}Xbwra zqe{6Q90R7XjT+YyD7#Ny!(sHvYXq7@@+ww&je}zV$_ro$NO=rQVJJr{ zyHCm!VDw3OBAP=|E>kI&!Z9GPscKw*lou+yPhRCP`s7uC=8(MRs=Tg%V*tv_U@(Uj<_r2W@Yu7S}<&ssEx==rD8vl)&7 zNpFNHFzNL$h9!NEvil^x1xBBwA3$?R(od+QAA@7SBy5GrR}WocKIuR1w(xPESK~et z7W@VO;4g*;|F;VM1{?!Ky%sj^TmIv|9X{@dYTO-R!9Vg3{&9Hl11k8>UPsT}tRGMQ& z6eCqi!-B^h5;pF+{^O1cA9s=(w-}BAD2iYTKrt4kuoG*cvR7G?k*pFJeNatCa|o&# zD&;ab2IMtejqAU!OjCBByk^4alh-UXhvckk>V8Tz`~Hl-(z<8({RwYXzD^@;W)`oVZR(dK^7R(fY6jV6F#K z6*=Ab5O*9*0pDBW##LO6oEtK71^pAB1pu(N_j=1a5@ zD*Vup@Pk8RT%cl{9}?p{*aA{KH#GbN6}~7W{MgVKr7FghkQkF;3rKNNX!sc_d|62N z>7g+$S25-Ur!hMyL?ki`rhwy0B6+G_RuyNP>kGmm!+(*>755h43#TJ+X zP}~nwAd0Op`k;6e%^@hBRw-=@9`}i`ai8%Y_u24qUsvP40>=OpFTv!Cf^KNM;Xm%1 z;p4ui#(g_1_zwTz?}rE9se*q7#{f~EgpK=!|F~a`yk;HKEthdrb&ifZ%#C`7X^!FxO2kBz0!Z&x#8n3RpVX_#{d*p!Q_jAPR7^xkGm{<+?8tF z>%)TI=pTGlc&RHg2SH}8orqdpC1z5ge^c=Uhv3qHM0L=h$?#(;gPK7Fb2&= zdzEw>cm*xfR>OYyr$phbbVlPHJTT%sMK2mCPbp zJzxxCHb5oa4_-mc`ob2FS#LG6e`YZRLJlnVGCe39HxNGhQbv12*6+% z!ww09l)XyYk*qN=1_7O{6itLz5YS@S0@5ymDKPD^FovaFsO(kJ2JKlYw+i?Lhu{tc2Mx`KC>mH&?nX*nC$-B(hPB?7v>uD|?m9!0d4~{G;#-;POcD z=nn-)k7PXoW4dlU)BGfwHKFNWpueC}dNz36r^Cj5(SO{R!pHrO8ut@82B7!|rhtj~ z0H&}dvP0RcOhhE>a~OS4?L>13s(mWu-Ea)ZYnK|=e}R0h>^^yY2cu73-=jGsuR|)Y z|H3f<^^xN4Wmz9 zIcN^atD(y4L^uYZJOQQvl*hvqmU3NX_euF=7=2Q1gyxWxO_g#2jsbba)VThuGFRDs z@=C$zlUF{PL-J~)@@fgkfV^6$asBgZuIxT}wT00quXbn-$!n0xt3MnArnnzW0V(%| zDQt>+E4xq1=fLQb@?bQFq9MnAE@x}g@k_xwg6#o1&_QvbmX0C4$5qf*L&W5AA43#Nb_Ba(Hj|G0I-$8D^}JsFMxtD*r+0V$mbQ`kx3 z1ZA(XFGsSP!03Z27tJB4nyQpja16*RsmArcf=DR4PhQPn^vSC^nnUvHr1I(j#{iV= zU!i2xG>0EpGec=rjppacsFz;vU!9tY3#J|Q`FmjVUa@}Rogh)_RX1AzkY|3 zvpS7v)2;i8H{Mw~A$nf7EX3&9Y4q+j)~;LcA3c6X(S?Pj<0i}~FB*&26j!Mijh$Xz zQ97+yOdVTZQCv29YWd8f(HFOGJ9=>Ol;W}F#iJdE7SqR%Ga4BGFd7>*>UXM)-VmK1 zy*9cz{&@U>`0I&>;$Oxei9e9o9{)K0cKn0Hd+{BK&*KN;-^RaB?2dn%wLE;k^Cv`N<#Sza@T(f0*}k{L#E$;+yjh#+M})Cbs2Wm-sAi zUE-O%^@$tu?oTYt+mm=CZ(ri&ydM+a<;~B#ChyL?|K@GT+md`B@8i5z@}5qf^T~C| z_mX!dA51=){3iLYuT?> z{bTLQ=#|lV(7zyhRdiAGYH(N{y$(cHMsJMX6umWiNA%9EbVu~V=qJ(t zL_d#y5&bgyb@a#RN3kzr`(wYw{)iopZ3gd$zTyi|2Domz9+snzAye= z{QLM1@%`~1<3GiJj{kyLI2ivU{%8Dfd|qM!$Sz7OPAp9*)+O#v+?!aRxG!;k;(^50#OsM2i4PJVC3YshOnjZ#mDruwlh~K| zKJjDXx5WIsg_w)$@@~jmm3MRAt$C~S?!e5f%Uh4R*_^i}?}5CB@*c^1G;dqpGkGs# zo?g#;GwwU|Ic9JL=JKZGEy>$3lXoQ7U@q5T9`8x6Pi{uR$NpuvltCHMxa;Za@zF#v?wZ>k~d)@ zw^7e(ktO8n`C*@lQ@E`fepidEDeyR;!agO_xS5VD)go2GNT1@1*{3@D^m~LW+Aoe% zKAT(cCMCpKG*UD3Ci~zBK|eL{uUcdwrRDjd98PJ~pqA@0&z=Kn`)IUbOrGLRQ2E*OKz^?ww;un8xc2~$s`%c= z@7xU}N>NdiWD`Y^ST7$)2q+ekElD=Jo2)7(~D-rm(cYp*GMP-!Tb(Ad(l z)7WiLGmVD5#^x49n@i)>3*SEaV4u+`dGxXdBWtv(?`)V?JImkR*(5%r^&K6}ZHG>1 zP_)MOE=7wsE82ldp`vv)wnW<-n-s0;Q2gu0zc~ep7AyxQTBB%XI{qzDw9@A8syXvZ zd)iT0IoH4cD8qRHg&Xj zc2Dc*Ls{BQL`6(c#>^anU^ZrVg+6+R;(Q7guvHyzmA*4VzNYizi=yQ_B6#M)3>LrYI%6T}GWuUZFXEQD$p>Ro z_wgUJ`QK{MyZaA$^r}UpV*kygW9i{5|9o`+BZJ?6Rq^TG@4oP7_NX(*rR8;NQ)@%V zlDaNly^Pv%k6eDuxY&jJ?0)^stA9Og)NVVcWfUHF(o;YzZhwB`Bgg!7z;S=?TekYf zmBW4?b;f_IsATH$#UoEEm{wJI_v2&qN1iInRh43(87;CH`=kzqp~J zSXnky$zYzbN@Ia&Re5n^D&TwvSQ;%4m&7V7i(5KVSX|%$%PRt9 zp$ebBxGR;#76%v#g(|~Qe@SuY#1s}=9bkp8qO78_%vanwDFv|20Y<`+NVF>KFYYWz z0c>}G;Q)MzRRxMW3sV3)9AH(n%2!t54;FV$P60g30me#W;nGl9X>n&!3Sg%LtgNam zFNuW9iaV#I0CqXRXn8am2%}{>r=|dQJHTK`Y0zKh4;6Rrl>*q~081-^F<*IEMRDie zDS!)YU}05hnLp+Wqh%&pO_M?0=OWR47CFdRw7eo(QbkQ;wT+BiY$FSN;fh#!S!G3W zM?;Fjm)O9P;mA@)l+|_0ENf~*#jVvgQ`6>dH!Q!Uw z6lEXb;DWJ0Amj^`7B@Af03K-r3#&qrXebn`DDJY6a?wXQ$kIS0<}ay?7B6VBo(CCu zw1W&re8E@@jxVsE92wbbBMX9M{)+MtSZ_{M&8ux-p)XKYRbE*cF0OC1kg~~ZY~+-v zKM*Smg+s+y@*8SK7$QkytcT84CG|>$~Pz zZ8U_8UM!4WXG051gVBmWAQ~&4Q{R)q=qejIB^)V@R)))?#dDhRr*syYV7ac>+u*`- ze}nf1Ib2auQC?BuBcw%uT-P-=v>@aUm-;G8LV%h!$_^#$ z!vcG&jh$Rs5iBXI@`Z{US~{Cd_hmwFv!O*ne@Uc-2mrJrmD$@Jtgp;h?u&-12x~w1 zaux2dv4v%UKxt(pPzLPM6s>=!jhtK_DK8HPtHQ+%oefqTl`DIf4J``$LcVBuDF)Zh zhQb2VtXzS+9c-wwv?5dzEN;YKin98O3{BY3DY2?hFjO8YD{gFR>$XFH+^z4i!Bfk9 z6(x}n+PCr0COia(nzfKy?Oq!_Iauz;02S~RH#RTqO3@PcIZ&UkyfhYyU_#Km(CRrd z5BJ;9sTdneD+4}2JDa+k8q0Nfz(!B5@cGJ0fSS%{y?a>smZE< zjC{mFVmy!HS&IN^l`bP6b&w#e98-@lkf}<4%tjUkLV<8)EC`!zjm>Q-y4d3mHe6X5 zsPN&Dl)H`G$DXjU1?8boSy?$^T+?BuQ8|7*X#b@#L!=-^rAF9xd-35~`8Ty(74f-+h52GVAw{X#FH>?IO3>hcuWV!y#)DE{Bor)et#4?sDj<8c!NHcrg0V=n#Lux- zACR$MJJ?uRRj8bH3tH#5+mD!x{l>vo2FtOWiWRpmXzf~HR#%38>p)AfoT{p*0JdvM zo7J>3_B$I}7>b5ULq30HvC{@J3Ew-&GGCRyG*})gZnLLHGIFDXtVHB22}FyXg^vvU z!3GwTRt2IFA9!uIV!Rw*ezbu_i0}S#zdu^s-qURdSlOeW9Be5DjsOA|VePOfV}G`> zQ_8{><-t%{6=9vYDNlBOvB8te%3`I_V3>nbg_mD#Xkj>5QC{hb#mH`ouJxOZoE#)l z5#TzSnyglppMl>UWX$gmN2@T@cQ&+jqGabZfLP;E0guNjV%oO%d0BFSO5c@f`NZ*|{R%WGwAz z_aWuHM75z)DnkB}a@u4Aw4=+auFQeQ1{al8gv$cqvT_c#Sdi#w&>xCaVjhDX%z0Lrm*c_a4l)*vMX^O!38WPe zWaKa#SyWbDS{@3Qqto;g;)dJU$B*!7nPQjmBvtYuvXt`bsO2kZEft7P-&n90k^DpQGIi_ zy=asTZ|8txmC<0R)K@CNmSq_{#sOCa@u*?GF2GiRl)>3HxDYE*?B!u=ayIH<{PRGyjtm=Th}iB^f!+C49OacqdB9uR22O2G^Mv! z!G9UOD~j=lZ_gd0jyylv01o1`rOtoqSmgg4+4nH>UxfVC*-G8Qxr@wVTX0TjNCx4? zpup2esAP&VbGs*36e}6(Sz}mXHXGUG%F|Wn&UHHFdKU)^djE&4PR{+2bFnLDM^er+ zC}&FsKC+PA$r(b_JXSIrKkl3L@&!L>d_Qc0STPw=Wu0nfVIURZ^-?^0U6Ad3fZG)Hp zJRh5f;!Z{;_-K{qgE4yYk5;QqIdL=d=Ux z@d$F}x^hm#pTk`^x6hOBN4Co;Tf2de&Cqe2C(*kDo z;~{cJxhW{)m6Y+cgYj`MI-OJEBxIb1KfJeaZgNXduB#~5qn-H3n`-9*F_Xrko>H#l zYFsrdy zb}T+l-rs(fM(xN(?z*FrI>$=NG4(inY&Km{#*2=EC_&}WpP*aV)u(zhQP6diEp$9S zu0}TVp{0Vtavqrsa%vUjdhG;!98oMkc^gnzgPc)rGs<{9WxQ!QK5i+IGiIVh`paUr zZ*_8!G33Nwv{ZUeJQ*LK_~a<~2a3Fc=WOWXppJZNDBq0J@bPUxeqf20wXS?}T`A`c zlyk%x__!e`=cKwO+&S&Gt3|#WDPPVCeB_rZ%1CMnm90gl$6XG}!J4SKiLyOL+2$jg z6V0fipWrv!7j`9g=Q+rAGvx}b#K$FgWSwsL_D*ah{nERYOQw_Z-9q`^xegya)pA^+ zd~6*0m?*5v_N)n+)>5X2R^j72WZH^6^RVBLqb9EKGedQF4O7=v-%3Y>hh!-LUbqz^ zJdFv;J@|Mhj>9~Ma6;x9Y~%ttTXQ2Xi!zNuINyL^(0eas%0W=sjWRJd*HA|qRwnH6 z)?w?ktqwVtWe!0`kbvSYpyK|x7a!dej($|;Q9U!ZkF&zKIwj6l7@Lng#4^GS^r`WM zWTNO{eEbR%1-!=Ul?L4b$z2?9`tgfZAXNuB05!N{1LuHs!6K&|K!wEXr{T3AAzhTP$eePu`8{@(d7L+kx zT}#iTiISmXQPLJ>Ns+*TdY_W61VF8s<*%v^)`cqdIz3oZ9hj~3?rT+L4vIZ~OkEuv zui{hKrn(O7qJe}i)NBj5#B0{ODM*&`w(b-YDG3CmLiRx+Giu;(cWYN+!Ni6slNZDI zZg*_;9j&uoogJgIWjZ@nXUFO6c%7Y~vlDf;TxTcg>|~vtqO*C1 z+H9!v4RwK`wis%wp|%-nyPS2c3X{cR>+HI&khPu#D7a8heLtSF1OAYmKLp{P! zk2KVy4E1P3?KSW`UTsq5tDaFesZ;6+MPTb8se1;4rBXi_3+)|d)<9^cUe{76XD);K zD%*1D40kV?3~hzO>t0ejYz|eH-2cj}rBdfX`?_hiELfx0)D_63HbeciRAoTqCu(=7 zzczEz!&cW)BdoY$_1Tr^qV`iy*0+=Nv#R8(ErNEM6~B1Ep#CTE`78iGN|mdc zQKP$@(*gL}VWm7YN#bP!lpEc-{ql2pfRce9E~~Rod$zW=w>fiM8vimf5R`hS<578H ztO9H2S7}^TdISlC%L5^O}F8ZKdD7-LqXXRXTi!qsIp8V zbqN6ZPJVZL-VNm=W;KHcK<5foGw{fMJ)4hwt!+)MaBe7~3I5Ac9+jBlQA#RtXXuAZ zRl;B+XkcB~u$TSv-D43oBU7?g`-C2C_+!lgWU!EH%!?f#oa8W!L&qvyUY0*{1PV&^{|^(E^o{dQWtg2Q>6R>?_xGEokm&r0<i>iOPSZHXHw0E!%qxd_t&|-N1*gd~V zz~VQi#YkY%6x}_2I~wZKEutbNXy>G6pvmuDk~iXsmDt!0fY}a}1u~P_(Cuzkts28C zS(nH4`=I|#GF}~w$|Kk;sLygL=jMXe0)I+*F?33`GQiY^2)3K*y1JU`8X7>>rxsbS zNV!6lF?mFyLGj56CDlKh{_*^y&RoL`JuL;(;r^xR@`+`|j^cU&RE?buZ|%irDbyQLlyKqtqrFLjbJK-?f9eDae_-Lyt(6?xl; zmfr81)uP9-PrYf3ecJ|vFi&xZxK`-@l}bh=kcTqr5x+`m1Q~frav(bB6muUMGfni* zBCCJyk?MAqvbWRzv7`yZGbpRjQ3u==eGJ;yoUV)E+x@H@3jK+8^od|fYDb^VQOleI z@fbBNq)FpctBTw9xtFDQT%#@)HBu`zpomOaUoJoBQ~}MYzCRL9nqEB!z*nXR=8*56 z@f-ob^%B`W+5BcuUM(q0D&;Lc546ioEzKx(*D`op5ODYeOquHz;D^ASk)=$K>K=1Hnhznrw`MVYvs%PK{_X@+PRB+s{>xInlWJC3CCBF~XvdqT@n|Kr z`CYIa;WcaM=xW6m>aA*JTh+=m^I~fSZSEQvE>tq;uS#N#-PVpbR$?x29G<$@@WiXi zmB!BY>mhlUdPOE`j^JHPyVSiup#GQZORmt_l{&jhXIJa&8l7FMvz0o#PG_rhcD>G4 z>uinAZqV6{I=e|{H|y*covqc`tvb6+XSeI@4xQbpv%7S5x6TqeyGLjD>g+z9-LJC; zboQXm9@5#vI$Ni+M|Ae6&K}d*<2rjnXHV+vDV;s7vuAYntj?a(+4DMkL1!=O>?NJO ztg}~i_NvZa)7g5Ry{@x2boQps-qP9II(tWF@9OM5oxQKK4|MjS&OXxF$2$8&XP@fq zGo5{|voCb^rOv+6*#@0`t+Q`*_N~so)7ker+o-c2boQgpe$v^`I{QUuzv}Eao&Bz} zKXmq|&i>Nb-#Yt8XaDL!sWr?~!!l~vkQz3$hGo{UtQxji4coki4Xa_pYuJby zyiH_V)UYjU*j6=cR1Mp@hHX>BM%S=yYuI)*Y)lQi+EA}C)N2iOrJ-JDsH+V1dP7}p zsA~-M21C8kP;WBSn+^3ALtSgAw;JkghI+f9-eIVB8tPq!dbgn_4D}vEz1L9hGt~PH z^#MbD&`=*T)Q1gqouNKrsE-=zV}|;;p*~@#Pa5h|hWfOjK4YlQ8tQX~`n;jOV5lz| z>Pv?DvZ20WsIMC8YlgbsP+vFHHw^VnLw(Co-!{~D4E0?@ea}$eH`EUd^+QAb$WT8v z)K3icQ$zjCP(L@+FAVidL;cE7HyG;IhWd@6eru@T8S3|jy3tU7Fw`Fn^(RC9*-(Em z)L#wtH$(m1Q2#L0KMnOSL;c%O|1s2m4OOXCS*@zps-9XkqgEYKs}8MIGx6%MR^6;t z-Mm&ER;v!LRY%|*X05tKt-58cx>c<@s#e{)R^6sn9bKz#TdQtYtB$Evvuo8HdgmB+ zMh$t|L0e|0NWmf`Z<*1w^C{_RrkS+-Jnx1ltEhJ8>DW3fo<3>%bn(Jbej!?1ym#^5 z$_eyFD5IAty?f(1%fNF!hbG_jjN|e96Hh7r8>STZy_vBQN4WZ#2G|2TO#e6UI zTWfEa`Jt-O-Q(GOsQ-|1)9zIyEai^_u)hMF zPb!cmaU;=qD@0iAQjX*A?3Upm2SvjYv{Gg7EWE)xOmFScGZ*R;7U`Lb^~@!D=2AU# znVx&O-n(A8Qdg}YsaiqOvr1R5*E3e@8Ef>68}tk-NUBzl%t$Lps*maF^&@>`|3Omi6C~Asf~3lWNr~yXE(&zjd6BUoZTE}x5U}nIJ-5@Zi}k-#M!-Zc3+&`A7>B5*+X&maGb4+vq$3W(Kvf7&K{4mC*thMID0zIo{6((w+InG{*vsdHnwK!WJXRpWE8*%n#oV^uiZ^zj?arSPUy%%Ti$JqyQ z_F7?7dz}3dXMe`o-*NU&oc$YTiouw{RD*d8mSM0V1{-RyOoL?^Y%_yx zZm?kn8*Z=>2HV15TN-RDgN-uS)&|?gV51GTt--c4*cgLl8!QJWOAMB4usnlpZ?GK< zHr8M}8f+(njWgKJ1{-g%e1q*`uw4zdo56NB*d7Mc3^u`F|1;P`gH1A6fx!w5HrZfB z2Ag8AsRrB2V0#;En!)xl*uDna&tUr-Y`VdU4OU_>pTYbF3m7bDuu_AS8LZr3A%j&I zENrld!J-DMG+33vVg{==m~OBdgUvA5OoJV0uvrG1ZLqk(41?7g>>z_3Y_K|m9b&M0 zgUvBmgTWfXhVr2lqap!$gPp?XPm-2qcT)VSL3~;`hELAuWd;5RK0}^9BPh!I2aROU z448C)1shM;H>;adFTFN80hnItjaeyn&FnX3v=uOwPbTpzILO!8*^J{kO79NVT=Hpq zeNa6KTdwv3fp%5jmpq};B~PY9{f(q{FYu!%^_e|;a13TI@)Khc;4`eijZIVc4%g?< zzH54kAC{=W`$E^NqjrTU7mZP-*HwuF;X3B)^@ld`vDSTXTpaN-&y9;gce$#lo~*Gu zD&z3_*{lNJopjIV*PssTC5K$Qms6m;%&Z_@eI)OF(+1z;rdsSCx^|^#+vz0JG%ZBJ zK`?1=J#MFDoWHZOr~&UZ7uYlQ6&T9j;zRk5eOg~?`r~1FomA;yP+la{OWJCO^uF7_ zp8ybZ09XgRw*WqZewAe2hYe||58!l$@~Wi9dq~$I20GetyIFm6eedSH6o6kO1GL*H z*{4^*Z<+b2TVONM)h$|}zu46Ks(r~Xq-e5nk)x&;o$_Aco=|6)&PT+ytLq5JdC)&= zX2)CwCq!I@9}M-uW_BDtDXGRg8%%ZVm$~0786#3`-PmX8onsi|(bn(qww~!sQ3~Wu zxouI_PG(t%D0nmDes6cXlJQ51eIM)eu2WPLMZL?5dS0R(-nrKFbiSn9)Kh<@_c(TU zRiW&Xlzv%ByE>c8;jCs7D7UxpX?}OSNhzJVacy(czOP{sD&C8@oBJC8?v<(?=<|xe z3q-xcVWE6zW=H5AlX3?SkSaDF%6BDYB(RtKAngbB_h!8j2PaKI79r2Fk_^8M^{rNB{?^R3+NX`wD@--wQgRnBfcia`Td2F_ z_WlUdU(BZ6=}?W1-^|028cce{$S_R#v>#2Da)fDwX84E2T2rM>QF$m0f^+C2V_&iqW1Yuh?X(or5*Oq>bLkQSWl6=c1A9O=gO+&zo(G zCpEbP9in8+!?&NB+wiN$&5d;(_4s{BeAl$It_`P9=eFY*F`e~NdQU(t-XBZ++$hx@ zC;cRTMnLle7pKW!wNOhmnwDcH#;L2YjPiBfi%?V?yQ?i&B^bQf!3{&3I zXeW-pR>`wwCdZj2QKU#Z?nMFdPg6~s*L_B=(*QWcq?<2-lcMtv(BC7~l;XeSXb#lp zI*y82mlWK0Q8G592)JgiapEm)wSUM-KhSC10y!*E)T_0k9@e|jYIo547W%)XiUK0< zaUKNqXOcRi&+tip&;Yx{RP%=wfys{KnNW^4i>7=@Mh*xV9CEHCDAXj+-DlVX=ArjG^Ezn)I@chh4)XHJd3|y3eu6Af2|4(0c3Y(LLdBoj6Ux)H{sc`=0Tq=Av^e;*JP^Ifg$|R^4nraFnbSlFR zBGk}NTJ1Ee&vyW5!|oJQE#AJm=1p|cen0D_SW{a=JAM|6#`1D&4l=cWWtQ@=RWAST zfqNrTrwDMM`Hr{_zpjH{?y+}TceRF?FC?$=V<~<)!qKsdne$LB5zU$ zu)aiWPj)iV{-5#o-zdKfrFoeBGL#zV8mTB^N-Bvqil5liT1TKj)MdSdL&+OnN`}C`g-G<9uJnoQzR`z<-kg{ia2 zk9P<)x^W-WsH209meg1kx~|W?EM=4wCu;bVLFy|M?;n&33I^n2c0e)D^HVJC9oAdL ziPpoQJ0s8}oQ<+4pj#u8pH5cLn?qEtLF}jxQ}*e5GfUap>Kpu!^^{JDgll2wB6_z$ z=P$({=}>yFwf5(inYHHg6xxciV+@@pIb7CGmX!1kxZSCFi66s|U3EHHm1ojbRvoLW zm=Q(rqBpdBl%nP86IKx6!OPvO6c{fz^?Z4i^ejw*LkEsoSYOwIZ@qz;j-kABWhwti zEr1qs9nqzYgQujmBF1`qtr&rBJCi^jkCM)4UJv~ZW`)Gzm{ezM_XjFykIPfQmOU=h zV&Yq=a{K_gy*{UL^+`#~PmD>OYgg!}I!{APPuiz@3i@rN-pL0|d0y8I!fu#B58jl$ zCN2hJv#pN4D#cx#L^6G)%|~C-iNWJw>)zQh{P2B@ek}qk9%_OstnM_+swbVrb#FU; zg=&81Se`T``IPZ7F#SBAK4K9Et2m{DECHvN$$gAQz>}rk8Fr12bc$tHvnq5@Bq<`^ z19h*InNEn={eC2r9ZsPoe)%ZeMAY%N*|O{BTCV5H0}Xxi#2#p9+PvKEd-SC{yX(;l z&~vQ5PHQ{&`OJK%zn8j(>-$bI1z$x~_`!m?_)U7{I5k5BWxc23h||j;4~Gn=Qm8d! zFg>35Ze^rN2guQ9N4XZQkobo=7&O2Qn2W4E_ZL~B!)vA6;(h1@1p`2v(2fR~E zn(I9R^dUdz`(80iz~rw_1!)b?DfOaIEPQENu+G`I zW8L9E>|i>{*IM>Y=32DWqS?BRAEd3PW;)nvrtZEsGXj0zQ_mH@=3o!sG$Z;7J`Gdu zC=#Jy0jxGyR@e5uiF4}`e+Ya*iNGyk=uJMREk;k`TL>RpPr_1(lxjRZ_M=5{@Mn_` z3NFdtdOHzDYsV~Vm{-rkida9s=rjSg@ZB?)IWXvRo>e?__8>$LU9L0;*{x%bL)1E@ zRtMvYL)Vwv-hg_!S+-aSyO%>b(0^hzF5e`aBoDg_;Y(>DnC6>Opn9G~b#aQjSecuq zaK^!1P8AGYt~*DbV2Xwg{D)(Zj_)*f+s@OL(gRZCiLWw$trE=UScZw z4!>&^IRV;`Q?5K`*$h=JbAKyZoW*Okd@mV5n=z^1P0TuHWk=hX-|&7s0h1aWpBBT! zOJ;rXpkgR+_mT$GxX5Z~=#zWV6VSgdvBj6p5?NEBA7kd{Q^=(G!D_gzTSv#{w$vYL zP4c|LZG44Nvd+JNDOn!}>+hMhr&%m&@7kv5fOY&j9kv)7%t%hJ8F}-oW~J~pG%2{A z1Eas2MrpA^C;zebv7^f=(7)_ZR+$ug8=-zisxw%XYP<)u515(p?#n&Q$Dk~8x<`@J zD{1Si&aASSq_{_ujnJ<#?Yib!?wCpM1rByfD3DK~Zm(qg(>E5{M|Yh)!X3cjx9CP$ z%05od0QIhC_&KOOHpj_(z~@4HoJkU2p}Stnj6$=GG`|ZZ9)cy-L-5xG5f)sx@y^e3 zo$rLX-!)A`SrMzESbiiOmwpfG5z-XUy&u^M?G!6BPSqwg_LETKJA(3$Ento*wf7+a zR9N|I@C_!{()JxV`XnC-#K!xF)-X^jwGsNB9h~SD!s%l=-CwnxZrP`|V(z~B5{kb= z>Wugn743T2^XJj9cdQSTb}i{zis*Q>#q-g9Z)PbIor3UPN%!{CI#{|)hb10uVd^-` z)Ws?8;vJD(EBYdjR4Z!#r)m2@OlC1BgB#nJg-7(HFL11c@DM&Oe}{fOOj&6zVnr`I)$-)hRJXH~)2zZnI1oNFsfX-<+C5_e_$fShd_4%I zeIkGHp`@XK_I+q&aHG{5elzo%(a8NspNsugl| zP19l8*KJ7JhZW;ljlAnf zM@h~w{l#&MKHrn0*VsK$sHa2y_NbqL`6M2F4L_RE4%6+ny-2KSz zzV6Q34c*UDPP|!>oS6ab%aWERG?Kai>Xnk($D@q|7z)4@62P9d+tHpn_jM8i%_Zf} zq=-P9UDg+k>l)^8ueTBpGrrbt`X%0exyO5YAF#DN64C(^$vS}G8XWIQ?BpfpNhb$=9~t`3Y(w_3{M z2T~qo&0Bm+W5QIx_?1G_hX`7g7GUY z^j(~B5}Iz2dnSpuTbeSy6v7VzJkf?MiWaAF}TM*3bQ0 zMbR|4S6bM!&GFcNAl6x$)BDxXpU|Tf)I7|{U~7ey!^bP@c+qVsPL+BSt-El>qq!3~ zAGH7{Z3^(GWm@dBJ#JZx7l+V!QC^K;)ebdx7fXmCflg|D^`{@ z{c4V~HKN+DSy?*!Q~bpJ5naYS4um5>`Lp=e`Uu=0VWSka&2D~ym;9ZmR|j7CuMtTk|cnfmrqG=~?#104rZ>{)(jrfXjF zT>8m9yne6>>~K1t>GMUF>XaE)4bhe8r`0~PG|T(d>@Z0jXW~(%$-@6CwsdXsKCu)( z^`}_qvmR8@pr2Ve4(m@by%3a&!udmbx<%1${V6(xDbWY+vt|MOfpcA8y^; zZk979SP|_8OL?MGhvr5KvR_%6qx;pYH2brto4KEZWi<6Qadw7$$G)GaY(qy+o%sa6 zU>QHkF>dy@H!am_kxMMF@t25Er{^r)H5U6=pyB?J7RP6r_dDpX_)?DLmS(uA0rd#z zyvrYJ>Grofomq$bt#Ymvb(rha{3T0un`zKI7B3##Q!SI-reA`Zx2;UO7Fr$BoLKE= zX?E^cGtSfqQ|5udVamg1`A#r7-YR^Id4#Z|vuQ5=AjLdUx08h$Kk%*K_XhDtU-9w@ ze*_jQKsAG9WvKHEB@3bou~~>7i1US*0dav4hd^u*;!udKLd=BNCd4d=_~m0Vwi(0@ zA#M)wFd+_u*eS%}5W9pp0wR8)l(LP4*dxR(ATAW*mJk;SaVv<6g*Xc05+QC4aj6iu zfq1wOM?*Y9h}%LuQi$6@JW7aTARaBmY>2%OGx3*m6_2N(1Ai(VWOzJ{B!LT$r==4T zsPK3&7s^z?gvZl45fX@iGzk)TfK&hpG(akZ1QsAoh6EBI6+r?AkfuNa1(2pf0t1lt zf&>B}?F|Y3dou8cS0TcG5~&pU@A2S`f2IQWJsJ4hs1V^k#4f5M-1m5zx*@@PNR5!- zJk(r-^PUX+1ybCF^ANc^aNgs=56EWXYi;Nls{Jo(TS{f+GZinsGa18==hHt`rTdKQ z`a^8DNkk41>VP)9(0T?$3vDL;iMnh9 zi7Zkcx{KbeZi#=w7xveNjYs|4n6*j7Y#?Y<5`BT5i2iy-e9*{RAZe`Xzg`DHOXE@h zh=ZY}@u+`99keta351ATXr-iC%OQh8)ej0aXHckyL7^IfqOr1n|C(HOQq7j;0zso` z|27VVmPXToIhr>pR5MUC?)G2Wd}wLh?H{oKS{irzN3=jo<8J?m)=eVXHi>B8B%))J zh{J%O@xT9?c0x9{=3K(i+<6oAI*)KPgC3x~ z^9O0`fUQ~tEK@kHx2@G6Jcm=HGrL)2}7%^0Wh}^hSpaDVAc|bR#*dIZY4}?V9afV zIbdMS?SsJFK^R)C4N#vu2}A3(0WfzFhE{3=VD2Uitp5Qf%i17PkY z46W1#z}!a|TB|wFw2*f0Gq>rz|36?KBrL7$1}OU>!WaW%9wrQ}`v$PHZV;G927!5W z5cPSCFto}XpgxZihSr%PBGcM8Wz2oTDsL0GCkaQZ(gDhRiZF)^jCtBBZvZ>b5QbK* z17Myd46RuQz&z(JtKUBLJmF|%+t(J~*n_6`g+X9m>>p$8?)APj2+YfbX-ruk+s-S5 zp;h!I+U-@s(OSB%Z?>)127y^m7+P@;VCVHgVBR1Mt;q+l^X4EhZxM!8?E~0(n=rI) z9{}?XVQA$(0Ono7(Ar(}pnjjF_Xdf3e~`Ej28sL7!VTcVM}xq8VqrGn=cj|jeP-bX zsMqI%zSta>5H*r&d-FQotXhJ zzia}NiJ!&>B_O#62NCFGLOE3qqU#@kJs258_KgoCxt{Ax?t$iVzDR zzAD5*h_4B8GQ{;lEQ0vD5T`(VLx@u$zA41LAigEUy&=9W#Ay)U5#l}&-xcD%5Z@Ex zeh}Xm;{Fgn5aM)*9}2M;;zvR(f%vfyeGoqpq95X?LJUCsOo%~2;#p& zJQ$)<%a1bEL1aQa1fnX$dWaq&&ViUA#0H2%gxCmis1TbVW(sjG#4I5m3UMJx6HADaP~c>1 zrh+Kx8B*UhkB&4UOnNfr)b~I{nDk`MX~y@;7b1m72}MgiL_|u@5Qt<3q0-}-(*g;R z64G2q2$YaWi#Q31j3G=Sdnbtqlb)Qb8%C(~3~iXV0DmtlQ$euw3~6ZTY=Vqv z2}Mh12PqIQd4iw2Ld5iBG_)+meMC%T=xm_lTnL%KbT;5if0+t`re|nlLwyU?4Pn!h z+1S+9%}-zj77$7yHW3D)ltcm`l#)mQgi_B?9F}ZuLju8+5~4JOQyeHe z47U+YaeHw$KOcv9$`jlVL{!hvxt&coYMH4Zriug=fvD;k0tcye5mr4JkRc+h^4nAz z;wqOZF9NG)C?K3%gjSKD90;yF(M{wayn2Q-xABHTd?mS=KnSoTcPxU82&aYTIgL2$$y#7Dj#%p%f+Xcfu=NaS5gi%P z)-$xFancm36yhxuje8ND2)LxE$FDbKDhRoxsHfw1h`C&*8Y1X=GFlqxR3CyaiF6l1 zm$Ei5Bs&PZfVcKg*FoF`24`S16~tZK?&_HX8G)B>6B>cnGqkn7p@A?6y&^#x1YacP z5vBphk!dIpr-A9Fh=DjwA{j@VhRE9%aT+<%He?2o+LPIhAiya{ zu=Zq8s-=O7L%&N0KwZ#kq+_OOcDPG z;hv1eytNU+JwuiXC%v`O{5KO{3zd?X7}N3MJ$S^&r)S9go>uDjMYxlZxrKpueE)y` zSG7ZL#+WO5tH$>Jqf`}+m^&&r%QHT+_j;<+$l6h!nZuPWs?-%@s#v^=&DIrMbtV6- zF{P2Jtte$wvD*A|$CNBT_Uhrvw6n+H)Z}7!5R}jEXSilRDZZKgS<-26b_MBi5lS$d1cnz;584x7_T`c)2jIaumB3m zd4(ZR8Z~c1%^R|{`fRN(TRX_Ed^NQB`^(MI;8Z?Qk6K#IQ73B8o8ur+`%O2;T<#S9 zOp$Pkl4&_r4-4>RHunVrrQuX7oLZ2rHD_yw+8)h;3f@Z1vB2?2ZjNT*5O0n{g+o$v zwDFoZz!+~1N~TrwPFO&Nn|XyHP#QH~jG8aZ*1EH`&TOs2u6!4?`60PE7CMzrbfcD5 zb99Q@^XBLfwcm7eEa6UdqY&;CCDU@M7Z%{lV(tqBO2esMICWIEc0{(e)b{8YsNk*C z97j1G$<1+uaELd@QsI!)9LMmQFM}~&b4sRF^V4Ag6~<5Rp~4U-jhdf?nxB}h9iOco zYuEe?sNB!>iB8QE$D@j93;tjq>r_4e3W`q0j8%Gb5eW(rlh}+Cd_55W?I-0O8S;c*M8s@n#luXN)*I)rI zJkMQ#Kxz1LBYatttzBh5`o%=z_wEXxO7Et}SdG#Ss z8h+dfKW@*~Zq3$iv0eE@KtC0i&v2no)cY>xqQ%QHJ&D^zt1MSe8k?WU#=Pp%v5_!L zehy^*-P!JFk#JbBGV-u@t3yNL7RZ>O@hDe-qR7}6WGs;l=Dr`U6wqfO%2ooT`x3gu z-Pu5jdD~r_qpxt6b41CsIQkhDVE$WNczmZcIC>ZyJ(#WCZxi&3!2K#Nzv1F0=t1Gz za%IKX{6{5%eg`uDktBj1bqJEXiD`q6X!ob!=MS>=Xlj1`gf8)j!_PX-&tJI9`JrT5 z{AA%rF~JXhb4Tz)Y4Gy`_<1f{dnQ|Z%BE;D0o`0&hT-C-=sCDVvk~e;FG~~+2QvSq zY=&2MOjUZz$r{-uRbcvT7j$Y&(ZGpR-BTA;lQ7$ZiqtUqV zK16A7^cFaJBU@W<6O<=#+l$K%xVQ;=L-@w~(7O^rV}ZwpSL+b<8YVrL&>!GnFI^qXE$6pKa>VPUx1&_vb9gLwU2Cy3Iw!J zTqfha1tiV|i<-iJOBJadjdO2N?-GPWT#M^m9oeC2TT zCFf`_+~pimGA)k$umFzs#f5W3X>jx-INF%4ePqQkv36Gu z6`*PBw{u^9VXE=AISX8ljs`e&?R>#)5hT0T0q8!rDm%Iy2R!VTbpsV zT5*@NMai_-S_}(d>o8n6Ta*S{+kmZ6Iog&sVM_#Vskj`Di<_`fAk6At+ew5S0c8HR zIqpGjJBP4@nUVLeEd}d?XY5F_zFlg@j)E?+t;5)8&e+ko%Ne6&T8y0n3t;ScTsUKt z24i_(%xlwissNoPE~n$-rpqh!udxzcX8@VMLlRwM9lGTHW!e}#TPw);*wk#D30-0b zhpp{7TW8@eXN!_)v2{5tfUOH~;cQVFZ0!cNcFEDk+k{;qa94`URk*kb+ePYMdrE{| z4P^cvIqm^)PlvFCnUVLe@&C1dT|?IQOwHJ}&?WY87~7pQwi0(aW0Xvbv0GpPjIG9n zGe&7JRshB(+H|cIpj*Y|HeB3vO_cgqkwn++K;}dKwqb7Nx;f6l{fav`~&#mZJr2+Fpe=KaeABs)rrl z6CtyY(WZKtNg!>i2O(RV>gNx%sb0yQdL4yurzn}0Qy;?uoO+x40)f(SY6hIrbF>3; zv?|-9PoRRg(zc=QcqF&x0m30_%|w-ONZM+f$!q>8jPaUNGOe2b01K$_m%PFdD2ZIUHKoObvMVsPURD|s3i?4)Ese9d%lZ1OVpn4;`VKhLcHT(cuQix z>8R(f{eq&nYm`jOwG0n;?JvtUO2f5zaBXgm)|jKsvHcnX6?~Q&Wv=6w+$fF0E#4?| zgj-UhH1nDdg)v@pN~Trwtwqg;@d~3+D2XkE4=JL10Eksikp zxe2=dn;(n0A3MQ1_k)sY`7r?&Q2l&feF&6>AHDG7s2uHx9BrxX%KxBp_oky9R}x1^ zZL;*g`Em^RWg^UTUnrTDFZ;m)T$sXLfIw;ZasqrgE=OBtJF-9SyB#^saYSyDW&h2O z6S*JLVV(Oy$+Y~4!UC!vJTJ% z6VnEdp68|Dr;%)3nwp;`=n|JW{9MfWnTxxeA4;ahPbVyZpZU0OekcuoR)L?DIodTj z+Eq41T>{!IEYNiK2x-=C96iKS^sGiV|i<-iNLcJadk&O2N@0GPWi) zM~k6LtadoMo^!MWcR5FtOpBuvU;!K*jSJ_9(%|SeaI`i@yV)k_M1fl_E+^sQCTOkj zjrXBDC4x={GXIVwg6?z(lKYTpgY$E93Vu!@TX&}B=TzttcR2jq&iOeFcR4?lOpBk3 zU;+G`jSJ_8(%|Po@N<8TcCXFP#R7MUxLk^ho1gpPkJW+JN&H*}Wd6fR&)7PLpM;r_ zcc6O($wbh=`L6_j8QTz#@4_B7`ql1&KRY^*pp!F zaht9i1n5R_xd|6HU5`uM=^2Txn}N)KI*G1l9J=K0WZD=!Tepz$XHv7Z7P`dK4qH!g zwr<5;&K4!pV(Wfb09$wB!r7uU*m@Ogy_}=HXcP8;z&$7~58>h_>}9Ecy)F^Q8F#YUW5fO_B1Y>F-n86 zcfr`(HeD|X(97cT3NCKC-j@2;2NGSc0-67Q5?voSbjkh8v@!Vp^%@!fAT?X-p-a5) zu=O5i>vi1aY*8{Tw#MVHn1d}ZE}Sh&gRSx2Qf-`9+tI7-;MMZHn%8UX#^wW%zl%42 zqq$@nONYb8d7Vw@9lauw(Nb^+$kuVUJnyPyS7M2{Y+S;N+gH(QapUk5C*P!1VZq9h ztH;u-)!k8QVizwZsiBme=<{Fmj^C#!;*D#*mz>!HV9p99(_&>GSb(94xNue|4OS+D zl>)Ce(W_1HYI}OM-M!kbHZl7GlRw3qKf){4lKDhTfkeziiI@ozF?%}1?CyxW4#*K- zGu!MGqv*txKJ17)4m(Ahof3dKJCsa|ofs^Dol;ylJCp`HC17W|SKH64?c>$<_G(jY zY7PJZLr#7u0DIdrR_EK@9aE^OT{F`&ErXxL=e^%dciw zfM17jcOXz2e(CTl?$u^_wV7V6#&&8xw0KU0Q+twA@zhSu!tG;eB@U-%deQ%9aGz>$ zd*g82w*9E(ek_1p?gu5)^5a-oK=qgK>O-J3{Fnzn=6bb8uQtc49pcpvwp}?6fc*JM z&-7f!n?xfxx3+iYh&JNeJBK*^^j7~4a+Kps;s{jK z+9FyiIkQ-DW?>&^j^WO%hGp&yCDU@|Zdia1H*+5#P#Vsh3}=>mwG+JBab9hi?MVV! zI4ZTua>*L2M+>d);m-|76?J!E${OvwH7HbDdreQTwLy;(3Jg}%GFBmcrMcZ8B@IWlGlcVr|k+!0E{kw@Xk zI^nUfbfSm?0rtd-Xq)@RKw<> zyu{;u8dltK8ul^H$MyhoJ}8+MAA7C3_sYEr&ppc#niX+P~rqlGHoMmaNU6q$IdPpgVM zPOHAj$tVGslR?R}$cVxMI4H%1w<@JU#s?tdJ+JnT%|s>cgCfzM|D(C*dkzh9d%oke zr#V^vkXN+|26$B|nO0S6VF6XG;WdOnX;k$~RP}SO_NiC<*skqCP~~q(dK5o*DxCOK zYPXO7KWVpm6q(r2r`^OIr`^8dWXu7WlR?R}$Y_HFaBwItyxk}bGB$#Y@4VVKHWTf* z4~nFA`_7?3ZntmxwA&B7svR)Et4hhVs(K_WpsGE*h7c%?s{Vnh{^r$w@oGQWwLMBe zj~16+TVF89N!-Z2u zX;8KeC>xclZE2IWQsAx=msPm9$r>g6P?JwoJj# zYO=LmYJS#0m)O?fXEf*M2HfTRP%Ifnx*j0A<5Sc1AaseH9lFMGx*oz^ zP8TK9qU$|a09~))!s((k=&Ar+<+)mEt`^AEd^Th63-kx#@*ys6#>(Lp%?s!Wj7p4s z1Y~|B*FEKpI*cXEjQj~K6|{580up7u6qJ2ThNGz|`vkf~#Gx$ADf<+6Ic1bgi?SbK z0hDdPg;PdpP<9|Fn~|&Ox!M6XUq1=x&*Jh6E^fYN2v_+-7?=3^70CSANqof}zT}6{ zw881pCAtnsLDz3&H=dfV-=Ry)cIcYL>G}hAIbD=Yi>|GPa=Nl`;dD_NbR7!1nsT*< zT&+G=tFsv!CD2=o%Qm>U8Eb-9Ru7vmF*X{={N`Nu+^SvM%_%+)$_wKkitd;#4> zTz199%~z*zmG`hk5?{LknZGcJuSE`Dat||YaJo7qy4q6EwL95el$x$Rpi3-t=<4Bg z?TNdbE=s0F*ECoFU6XL(bWs{~9S6FWo~|Vrt5Yp-Y_LPd zvPxJ0Wu>@q$|w!W&IDy=7ry>bTz;N=!)aQ>7q2~x)O9< zo~vD&t6iL{U1&4bD9}yfG8Y#&W0%7#tA|}9F*Xm#{Ht@_?>eq=7)zKLc@Mi((9S8l zSfcF06qL;;!`GyyYyotMs~yU&;*_=EE~ku=X;HQW7C_lyxNyoS4azF8{J9}lTb-+| zviVvnpofdg5xBVdx&aj6z0Pvw*s=MyNPHayWd6-beBI*kCHFAX2B&LvuKjLk70}kZ zA!{MjOJ;9L&DJr{C2n@ux{0&340kzOluV1QGhqR2ornu(i_&20L3FVDbG3VOwM4FV zSFU!4&DmKZ!`b3;4lZua?w9)5I*GG$fy{q6*Zq=kox@qe%*gxLy;2`bNPX-sNxmaR ze>;x~S(lo@^Px*T>@fHcXYc~t0Ir}T z-2h$UMTfl?ID0qZE@zLDX|eYZEP%ZPE}T6|gT1%F-W$2vdYiY01#X?VJc5gxw>RLA z724jFczYDc{C9HQTWRk)yd}(xyxXl8!Ey%47{6~l*geOirkXT}}uk(;}oHlM@ohg%d()5HdQiRNFdF+bU1n zB2OEUXKm^=LYqH4Pi$Zo(FW$$dCtz5#KAe(2L#QSE9;)xN?P5e&T{r&&8 z*S2}oN{6B}?j0r5@~#^eV5o&V1%cA=ZhLr_o2TXEX=7~HdZ2>a!nM7~wOq$Fx#eaUz3-IrG?jHn7!%-cM9+0P1@bfL%s!z?&chDscarmj@ z{CtnQoF7W2#n0cc0DgYPh4Vvc@Y4c*=I3ei^0c`&MgIuszv7}~B~vsXE?JZEc8MYe zWPV$oI|#Nr6eY}zybsNDcuCB4WV;WkWUM_kM;_=BZ4O7RoTCifdDi(Y=X8HxNXE`G%oHw)Fb@itG%TXLE8eEza)vEr4B)IA2Mz5KGcq{EWqg^FwLyb0YXTK2JL~Pdg@0JKAPx zcY)qRT=vAp&C>Dk%IZcZODs(QGXJDJ3|03dN+`Yi&`jrKhoyv>k$0nG9cmKCh(OI> zuO98(x4YCtGJJAs$|gaVILV=GIj5`ucR6L0OpCJVumH-Y;=(DTG$=a#o-Y1@*e%ilUeQ zd#bvsYbMj(he&HCByEt7>k+>S%z(}sEOXHP`2Kxml;+-hVQhetPry37K^ew z7-birmQhB~ z8PO_;5G{{rFh$hgib(CqzC0j`DtZnNNO^3+AclN3j4|X?ObGc#SO8%8=o%^mc`lHT zNH=oQjbZ7=5DA_hSrZPc-7&%fAI$+uag8#Jqi5YQgri?P@9LvGuX_{=ik^1Ef}&zV zL75MZxr@bu=%|dK#v`cwbYo1qktZX1fFjCOyCdIJRsH`c|0JcJ0>vXI|Xto zCWQPMSODNC1B^FR2J(x5{K9mjFx{A(ZcLQmpM^A>rFO@K7Wil(P>SxD%+a&%n8?u| zy*r9oP|v{$>kcX=6x8dmfLQjhSn!6*2x>ZlnwoBurW;daL~lTZXqC}1)rv^%j#3^F z>y9ZrAf-FX8S*z_j3K9DLdZXX1pt1B0md6D1Np^3UY%}KrW-RQ@_$1VJFcrOa*_5z8frr6Jv@lY#sP^|668 zSb?ZrQ1{Q`n9bt&4%S&5R7@z2KVSjy4>I_8LuJGfK^$|^jVscP%Va2jLKHi==UAac zuTc8rvVRuK)hw37FwbJ4VnVT`;Af}^LC1le45^G*79y7U>Bd|c$Z@ET4P?F*h}tJ} z|5+T1SRBn^oy9@LgyKkp1;lXzgO4{YTJ?e~x*=WOw7QLP)El*o zBPu4u(GXYwHT29LHvXs#j_v|SccvS6NP>oPyZt+ZBRxpc&p4 zN6>bQAT>=)8|;jBhYdgHk*)3a{EUDsy3OL}ZpP0@)G~gkm=He~!UFi2fCJ-)%HZb- z@bg%@@o2j7u%w8dkporbkvOpwJ%*6Pwct|O79vjP{mlT3#pe!chu%U+B8T2nC|X7oy_+688^32! z6g3;N9D0NE%s6_@h9i35P53=~j_9#B(RVG5-eDYFi&~aLR7{AYn_vMEUylRJAu5BT zPr=bA>BdKrAoHO)$}@3d3HpS`#&YNjg&=xtPWbaUg1)c_Qgg_(!T9;ehM!x>)))5t z&|`6;pIiKV#`vKJ;xK-wm=HhPU;+HxjsxR|%HZce;OCokQ86L5UWEnZ*9$nX{Gu}0(!E2CBk9K9lCamfp82F4dKOMB zVMmnwN~W7p=3mly6Pn>9Z|q4f*=ya&G8?k|`um^e7d?e1oa_bbjaN?e+?{BWSFW5q zUJ8^Rn8O&OVnU341`9CsAr6c&Duc1+U@XNe?%sXQmA>GIeK^F@mExtez=xq2Nv#yR zzJzADWgK0tEV|VEGHo1tetkv8TiLU(%ntpliKY*8^Gwtj^Lu=PC-j4djI zty96)$zG$iB(=5i?Fvk8uEn|#|2{G0bKYRyc8vEHj-cT8grGv3{lCEZ4DTN=7!y%Tg zc1nKv6}p;3Gwh3_%Wu)8=9g*X*x719#{KqewS+9{v)J-7wpyWs%*lG_8ASoRO zmS0o`TfMP>Yk_GouA$JkAElR$P;9q+|Wb=PlZ^ov}i5%r>odYcjPo9b3XYH#-C0a0&8&*1?n zw+#m|M`JS?SCCNSiMFvgHmF(Ksi*eM{N!T{q9m4W<1ATRV9lfA}7 ziJYD!6`M|l7V_w1KtzwQxpblhz42PG@dKiZSS%GV&tjosLa|%|3kacxg@89yMl7X> zWs29hNCq++^|66Wu>w)M;G%yPM;VLbQdnnkP%)u67Qh1FUx@?DCMqM2O2jeKYm|G9 zX)=_B5XENGOe>UVxzZ=o{#h(lES5zu&tjosLb0rd1;nzPg@89yMl5xR(5OYs~fD2=ikeCudw@uS1IS;t?-^7Ej?^2 zI>$QSUdcGxhFZoE6%*p!@WMQ86KoK86Kw^bQV;BPxTV4dCcj zud!YdM33Zx-oN?bQygLmx|PSqa%i(c&}YyLZ;B&mvqg}aL#7SJ&w3kvJ||mvf~egU z<`{v#T<>Ropa*uv@^d%h z5eamk!q2bJ4Bs0!#_qHDiJA>r0&V3a6G86hd2!F@H?n@8J!8K^7QNSE>>kG0A=EO) zsF)CAo+ga3zhHrsm?HJwZw z$IezWGXAJNTPcu5AF)I?ialHOh_~p=7F&B6Tk`pAR7{AiYS;x^WjHXls0_AR`-U1P_>5Ga(b8u$ z_ZcZZakq>fQ58Pf7yiV&WEw_a4m-hT-6Tx)@tKS+1zY01__|wjAARMPe&7*JLG>PD z^~Ym)cZ}=XaHCk*Ren(ETEEq`-lKMH{4@AA z!)df*qpsyOR@Zi5jNA@o#t0P?V&nl>03-CkDaHtu!AMsylI=4xeMV=W(MdA06VlkO z&9>->W+GT|joq2^L4C`AkH&ho6Q@Jz*={V32Vs}RLB)jP*bNJagFk2rZ>Wqo&P5!3 zd`2&y(L)CD3`DU(^s$0a^Rt(23_Tjf(3i#VtcZb%3B~Xxk6{mkju@zn7)Bt59G@}F zXAJQfgM7vS8Od8v2Q>OjulLF7_ibZiYA{SJQ{W%YLJzo19&(NlTYlEtlx#d zXl|q2nIhCV-D|K4YxU80|AgNix2M6kI9O z&Nzz+wOhw>BG|MuTA6l6aVC`HJf8*f4GgnDsF+Y7N%%Q00-=XHu|TMdKuQouvCk;- z85j7B0-rHS#*z$$aG5XM%nXN}Rf?@}qD8%=n;ULVUD=1@MuI1LK3r;G+tBRQQY;K4ZGim@3JjM>&BjrDH2BCe)6d z!HHlUJ6-A6shkO=W2;#pr@=4_go+6TLJx34AZIfCctd3bawP(}+-F?sGcNHN4L+mJ zXIw19VGn1z$`}6A9JHh840*W~QS?&46@7aN4~g|{gVncn*4vADaL3fmodGX;Rikd^ zHC8vzVeFg@WyTH_6JnR5T+~5o*qNI zEVg)2dwLBw{8EQ^xKVa8Qs~a-*}DHZx1js)Rij;nP#G*m%w}%?_+hYvs9WcP4QZXT@J7ED(?_vn?hRT5YJfJ@3GoJAoPy37~ zeZ~_K^MgN;Lyb=?b$ zk0_KGA5=_;4|-S-Xm}C_)^$_{A8&w<*L=n+K4Y)Xcu|tE2U2jQEDK(kA2pclRkuI_#+=K)Hng>)6Da+ML^VSNUfvqC=9%SEr#Ai1A{6w}6*z@xAKiXB_q!fB1~wB}>h@b_;%Ji9;+)e9O&&ib0=pj-H5;-tI?SnNH2t9rq~C2QOC`e|zimn#4_Q?A%aqdm)WavB zmQhBwD`rDm0BgVB}ZXLtM9O^~LrjTxBDJ7NR|$?oy?bcG;`rdo8hVswR3%jlwF zLUf%A3!tkj4va1;gRV0`S6jc4<~L6D8z)P~`f}}l{LmkVSjO5SDv@F73S$GH89vh= zdjXejF%~r&vJ6Y(v@^<1RVX{zhO&WVINhGIL6Akyv?y!GC>xAgMi~_oqHGK-fU+DM z7-dujWgS3ShTjPJjez89ELY9vhjBQ>@|D3uW%E`ig|G3@44)OpS0{@vHN#9BjINME zSHOm@31qjEJzeKR7Cp6Y6XoiRTao3wK9VXM#AxGiMY{)nosBqNZhNEl9SdKkM%OQ&nw>TQc zIJy?Kj3X*0#L>;LfWTMbz&N5ZILZe{WBf**-^i65t>>z@@WZV*#Bwx7;b?-w(QVKS zkN4vv4uzu$3P)x`#!;TaQLYU~8_3uMdyY0j79DSKG>&n!3AKzPDkj8H6c)hI{Wvg= zs0@y3z)_XosPG#z{Kj-i(_>tl9tws=Pv8(sQx&2TL$6MuX%{rZwf@*;c%4F%*^mvr z3eGj7Y=%PFbQ{W^B*S&~lsyGmwAP~RVn*51sAZH z_H?}kS@bH4t~rdZw^7UJqGCdHeE|z#iJq3mGK|Wg>pIZ2+;1%N8%zAgBEPXflD3aG z_>v#K!XcKl5sjEcD+Sf)NII-Y#C>sv9?5EZISYRfenKP$jSBg z41Nt+bfv}M3dSHk6OA!Q#e^6<1Pfr09$v;6q%s)16%4NT8|(bWTEDSI()S0~{*xaL z;}A>VdLB8;xs3{ae?c?6A&$O{7JX{YnKl@E>lDV;D(~0Wu=h9l*l5olJs2&z!D8<= z#@-RsGWMvL5PJ^K9lIOsZS@;lByUH1?$}nuBhv03g*W!xvF-lYdwcg-yhY81EbX>% z@`*V4TqE|dv3u-EVGkSIZjrK$ks=>9M#Y3k3E)vbNU3%>u#}=QQfeni*&!JTa-|SI zgmH+?q#a5oJ*+U20nPA3ag01{F`{OYX(NV^_SF7idqU``Xwio(LLOv<(9_UZmQXPv zLb|~M2%*QLF+!*eLY@L4yZpxEl9TRSj~+P&^`1DyaTOz(whuCV^2yS$fCO~Ql4g{oP%0M3KbI~g&tCdDCya0j1($^lszEjdCABy zu0)R~gKiEEv5Y*gWXWEIk@KJ#e#wtJu6*fq0WB~0DvX#7V^U)THQH;>!br%XFIg_YLi^SVO&!!<^B~yiVZZg>{5a!#hWs)ZW5}tP5b{N^ z0OWHRV7#F+kRJl_-~7fee&Z*<@uLL47}D5&`ON|!{RJp#a;JXz$?5{DUw*VIZTh9r zFLM51F)o8o79$lCig7(GAhgviG`yiQV$=ip?W*7S+ix6}0p0=;f>(Oyh!vpPJAYd} z5pPc z21yB6XWmu;>!xHBn&Fm#*pzG)ux?744cVO96h?5Tj^$*s^g`!WO84d+v2Ts_cC~7uj zIh1bk5^ZO_mpSxrG8VSy=u^m|A&a9RJ%_K zN`ijidOz~RK^$TU>crz=Ih3Uk^fNTWnE^~Wd}f(S^L~~>klBzWPDdM3ekB80_N4p< zSv1ok90_e3e9l8K)U$V{fkAhab+tA(qF92v%g{1qzRS zp&2fWVNkeps%Pv;=WqJ|&Yayf>pj^&4Z9AddFGvlS4oS|?z9-86uI4);c zT&g)KY*0>?SX37OQz|Es&l&bqPKGR6Zc#a%QCWamMkN*hDU~Y&dAgCOXAp%3=sN)V zz6u!o0>+qNuYqTf&qy$%Mb!&V1&EuQyFOD(bhr<9Ro?o_4}o}RXAZnGpUvWV(O zFoE75#sKw@9)txtv`XH z5+2Aopx$gnb1l{3hux^-=&{zE*K#B#-=4txT_DDzjOjZT(=Y!+OienV^|<6by%*g4 z5Qq&UAh`R1`T5nskKc(qzr|gX4ron&&WR;8Pd^u(2e$I`zKo>pjYzWC;t9bnR(S`2 zq@})i!ul~PrRzMsKg(3glteN$Cr=+leV7A+{) zUWNcqqnaDg!ZU-r=onc}3*4$8-m?I>B7ydf95hhV29Q$kiz&Mzcfu0GOvQvS|I9J} zATU!InAZdIx}dREV*Um7;TwSve*ja9tOP^`9k8zTMb`!Cf$$7sbS>U*qW1?|jvTW*lajG`-Zoz*T>)9m^7K9oIxHjty)Wiug5DRw1HbDC04TWZEx`f8MD7v`7 zyuE_%>UA9vHpr#9ma%Z&-M-8%1Ml+TRIomz^E{!D6G2r0=vz}@tS&IF7bH%~(+k2k6@<^6ylcMShcSN=a`JkFMxQ!d zeNqiN^x6yryfh=ahO%TlHcFDnyOd=3M-|}}1)UbpTauwcaY@F=Y*@ldp)h(=0p4{2 zuY8Ppd)~rHzaY9A9v);Kh?rkn!h)jR37%O#jS`9F$(TRypf~e&|9)>a9Kw2$g7PBR zI2g)YIN**z&s({RV%D!QXKxQJXQ-OLK@e#)uN}>GGF-1>6!;X_kso>Z8VK6w&s;q3 zGc%g`^H!5GUo1^IdJAvH+<6;XhPzDOg}AiHjo|;75gqi7>@>HvSIfo@l$0Jz%cF5e+`hyO=Hefb9%HYbi)O+5Bi3m+- z#;7=YP(;HQ8AsRS!Dk{(*=!)kx6Z~lb(NXImB(tU3vB7#c-~iyYtjL@^Yj|5G%^13 z^oy~s#axr8*RrW|ZDLbrC!;Yj6!PlUsT7ON_~Y|2QJe2!ogoi4Ky~h^$tTCEX1?*P&u$c??%&I2UJG=WLciV zbbrrKA&2FGmGJ3>LLvUlrJQ;=y7Zpy8L%Yxc8yQw1e`Zbru9g2Z{X|z6m;5(G$m^r z3%Co}!!An$SVObsWXUs5??A-_RyL87VE}ec!hv-XmC;FM=%mhtMkm=xr=mWbIT;H_ zEN3Ej(Rr>jF*=^k$#hC%r-g8bLY&IBuv6KV3|ctS;wO_qZ3_zwDisrfdL|42YCDDy zZ>S8Y(*ZS0;-t$7$ox1&v*NqFI|CAcEZnV7h|La9rop7HFuI_3c!Mw+uoN?w6_CJ1 z25MP6RJ7tr(pROWYr5V_Z{=y`S)EptS5seJT~(J~UtL=~txQ|&(NdDNzzu0y(N=*He;T){>!VN8iU!n98(Cggui;_XN%)g`x)!OyF939X6l5c-ONuMtNQ#cb zN?F%OLNv6xwz61lbpjKe2T^`~ZCP=p(&|KrT6qAnKzg3&;(3Cz`Ejo1r%LlBF6N6N za|o=++4BXio~xwinJ%8ooy|{kHGiozKg-2@J!B4n)jE5warJz)^gPGK^A*nKFLO1& zRGMGpVtxT+4uQ>c^33vWg*3n1#r!f?8#hTCYg}xshRgxt^{(b`ljhgEm|y2=W2>}r zhl`EPkU2oy=xY96X?~lF`MX?gJR)s8=nUflClk7UKSU1mitc$7!m(v_4Hfm;LS567 zlQE0c>z*j8mDx?l?6y%$;qx0Nqh} zM2=Lv0ig{QZ=%|TiVr2E_niH{RP2Mufr`%|a-`xL2yLkN z7S%3P{30P8boTp$o8MpU{r=|eS8FRy%6~)Afr`Tr*;3KUqkHtWw()vU?Go>C(r;5J zIvQ_oZ@h)O@l&Mn)=+c^>I65xr`r2%uN>GyOuuSG$<6gv=qZnNFVB(rLCd z-{4}t&eg`%(#9MY8&^Q)0P!+c^NXbU`7Y+?y4qMFZ7g?&vCPSYt}lVeA-8qUN(gPv zK-Z(%Wk$YPLR#zWca59h_4a;marb+d^t%O$4n1-^L=MAz6GVH{&na8{g}0{9n@e zn^1HJ>UB52@7Vi&*WK?Y((i|E#{X?^{8M-1_+!oN4vDS@PLD~YnDdqoGKYZEA+qg7 zU2g}`z=o+)%W4NzH&o$XhezBY@v(ayr%SnVufxyob?BZ92;&nz5`Yk=ylxV7Hnf!d zj{%(tnFHv~5IKPE1W|7BYnhz81t`a#PnqH`g0fZYcoN7%g} zbc5YP${WE3+l3O_Wav3zn+RDWY)P!2CrI;gtOj&_oRlf9FUActb`mX@uBW=VE``jY zqo+XB2o=B6c9HZPhbqFe^Fk?CkcsS^0ijc0)=SVAL(7S;YRDXrRZ7qH$Yx4;BV_2V ztEKxnF7B^@%z?AZAaX!9TY9!fHcQIwkS&wQ7DLa8n1zrzAe#@71G2fUo>xoHD_uNa z=WKqttN9Jm{4Fl#Z+13+lQeJ7>y1)w$Ll@P{oO9^w?gK?>lTO{c)eYEwnw%}${Qim zJ@-QBG)f+opdW&kQ!?y?%mLXB>DeCHeNx^C8Ai$fN%zmVxPKZl2hN^^$N||C(z89X z$E3UwGTrk$gif5jEv-jvERkUmykK2|H9e4?)er%C-gr_&p)_${?6Gv&>xmI z4nfZW;creRbp02I_!6K|&+4APAdCl(`@esqT1m3_`@hZ45KG5qXE;J?0+DT(>v|GI zZmSYq%55OGfY1hVOH{i+K1D)q4MhiBC%E}N)!uI#cfSGY*X!)}OzGEtaGoLMHhcsj zwBaL!Y8O66NL<6A=#W)IA#$Ks$C#oFCkwC zMF(8VrC)n0mr1z|u2m4);98Ap7hIbpuG^sKK;O&qZs|9UN?cNIl`;hrzogVX_d#fb>3&qZV0v0&+66@i8Xt$K5nO() z8HLF4>iiK1-8gKTQTp9+M1F|6yIpoqH z>DeCH04cXaHclcNW9PjIyZ4#r>^;}ny6zbdq0JOI0o4iz@t0&p5>lbF-^p%%FS7Sr z?C!Tx`ketqhmM#IkwZsJg~(x0>z*nIZK$Y5wF?!qC8P#tzjbbYFSYl3nY-V`((eK& zI#4kWA_pq2hRE&2dX!Ij?YlZY{KUS`lavNN0Ahf}C zBdT3+-63&pf}#VJ8z6Fkd@Dq5RIZnD8^~KAw1Ipls$C#IAR*reMF(8>NWb<}Zj*8w zTstAO!Sx`jU2yeD7iZ+2=`o5ivuJn79BA$eQKN7MuqiGZB8ShdapP)`^xWUYb6;ok z=eU|5CC!g;F`omOLtw+4Jr8m9JVAQSckw*N*?gX>`C@7QLKpLekU0c4+1c|%SI_0r z^HdklrOxK3xSFq(=Br)IS3>3x*i0wS{ChXje1nVmI#(N4OB-`sY+M1E1H{W*%`cMX z=ewAn>uO_#w6Wa9#xlqpATDt=zebv0FjrGnj);XEb^|cT=%qzNQ1B5oy z;6_xtOoMkzNOwB>y~EA#HhaI@-Tm&8ejkIPLytTPk;4@GFhq`2JPDx<6;Gksg^E2A z(*HU8eb&wIi}rqBa`*d=^!pYR9jJH%A_pp7gUFGJcOkT);yqNmQ1O|B^og_IkKFuz zZtwRCcfa3Bzu!R7fr$;gA*jFI z{3dyAJ24s6E}hsy`b~kNBV#S?jkj_)-bNZf8Hx@;;rGkVe$(vzp62e?EB&@}Gw!oD z?sqrdM;h-Ls~Ec`gv=q}t`ON0t?StkIgCW1P+BxtcGM<_lfSPln7Pu!&Bd+0v;@nxEog{vuZ!Rno>x7aQe} zIY6A|YQA2Yzu3imwX2OQrH#v+Va#?iq3g3Ca>#AnGY3MOGtgD2cA2~uOGpcx{mygq zyTsn_Qg^>=q~BFgbm)mYKZ;zkHaWnq1z42Gvji2NbD~uC-F{u=D-b#hcA>ft}+4iEYH;2gWmQjk7E4OBb<2DE- zz{wECC%pK|@|hC!>CjU0KL+$^kU1c0BR$*SG&)7f8zI9Pw}W&ac5xqcc8^EuxDw-) z@<#4;Pe%xyi0LMgWkbt}m`unVdb2Y`4xDv@sL^d@-do_Luk_r<#d9xb^F3V6kCf(f zT+9!H%ptHL&YlNJ&-TeMK+0`;BNsxa-Z)=^9tSO_-WUs+1LdQoXM1F$q`VO_bV;dn zU+m((2r>uGE`Z1ZS%LIyk8F~ZH$tX+${=*&tXhJufR+bW;8zBQ{ zbENyrUEE&^nFD8+K;(d|0V2n*0MtR~HdkIO<&9wLo~s~qB6OLIXfd>$2we!71MK+_ zIl`U`p&RUolsAG6w%1B*H$cw`+bYN$u&sp15!-drw|yoomvTF78zr_|q348cJ!B4< zunr+Ts%MI zY#!)ekT#xkvGELK4(OkDGOz1TLgbdQPe^&Atk6AsAan}+O$qunXgMX!E0Eb{g|6?F zp6&DXMJaED44i!^-M91fQAgmx2Yy?sJg9b|s+EM?9EuLOQXq1} z)l|xDaHT?M(}l;Q+67lTiK{IX9jHu$$N}=H5V=7ya9t|>+EaOnl-uCC3PKxP z5mdY2S|M>QhoS?O%OG-qyaXc0mEj@?-FRLguGgwQ6Q>rw3z&uucE^-y#Gy$&Kr z&}$)d1HDGdZ9s2;&<6BIRJ(xQCP8n7qC+Qafyg!H{&na8{g}0{7Y&4^H{~0J7S+g<`D2F5ZU&k zu73m(Pdp{D=-W!{bB^z&=Wks+f9-63zpME_r1{@m%>M$JLtsBSd;ZbYvnL={kw;uS z|Ltu4u&enN(tJw55qwjK9C{@gB8OhlJuM-$8Sbr6?K0d?m5@$y_Isk6-!}Gs)7w+>kcUIj0oPFJ*M0>tSjug1jfBt!S1zhua1}^g z6QSrp2HKS2=_>xMrZ* z1=rWWm82(mehi$6=i4MD9pp#PPv-GwI(m|lf8piiU)iyhuIpdHaDH_|ZAn>v`DN@O z!R85xKNe)46f0Pl;MAh)pF=dbtggPis+gWLY}@?PSRKX2Ja&3&mDCEbzk$|}*)_FA zvx+N}M{>4GhB#SI{?0+%goHmh3312eh{;NmAZMkid2D7LQ`nJM_zPBCSol+ll?XTs zhafr{3%|wcC^l3Uw4fsk=vg;mvXc-TTpSc9$tq|yUc2HKgcT6*;1y)@M?kko1M8qS zxU8bQvb?^mR#D|Y=vhlv>TAoZrYR!+yFI|D2@4pNVFws9A!uaaT(OE-P>`;9z{8>f z>Pzagc?DW+*)(k-J!Xj>;o6|pfM8PxpYOPUs7YoMjPb<#BjEomGiEiY)n z#>uq>c!af{lzg4Ey0}2ADy~!?VolGtrj_!t00 z#|?D!5Z*OtUm62dW4}=c1I-vxQPJF_uz@O*fbvvj#fu!ph0S8s#_0Z=?=38CD4AJQJ!NV`T}d$>eBP*B zQe0D4UtLvZR2J7EjSDO5W|b7q?%uUy<&d}Ov%}(hR@vidD z_g?4S?tjd`!~b$%r~eE8L;f9sPyN675BR?ieCb9sJ(E zI`o78NbpDh{Ln%Fp}`d8@o&;y}ILSKcR4DAcO z72icbE4m@6+Dh-ewU%hs`qv8Ti&<5?|9$$e&qeP_fzlZ z-Y>jgdiQ$|dguEV`j+~x@vZQ!^4;iL=eyZ=m+x-hHs6!Jr+vG9ANW4^{pdU7JM25+ z+v?wr4%z8{5Z&=GI_FdWXXu)J=#;Ph-}t}v|HuEG|9k%r{vZ7Z{XhAC_Wyzo``v%o z|F{2$e_mh#I$?2OY2cc`wSg6Zm4O=qYXdh0)&nFi~2R{pb5&SZU6bgPD{4V%o z@R#7P!QavKhl76wj|8s{%?~XMEk@@q4P6tuHnalWyBZz6Hnc9Z9^HIfXd^m$Gdg)o zXlv;1(Du;1q5IL{4~8B_r$>tJRaS(~IBx7mDH5tn@u0@Kh%2=JTCgaA8n=;mAtk1Y5DN3r;Imk z!gR(zXRA|pDXYdA1in5fwAH~hL;sp#OValeteAgY-SGQqSxN(rW|OQ?Z6n z|B)UDH7JA2E6Qqn`v>&It+u$*I}|l_-uAP5cJEM_TV7IIT~|G|-aDbZuA#WX zn_u5hT3%h4otf3Ea8Pw+WkXeY{iTHy1{IF0uCAyn%+1H!tgfB2dv)%TnboCB;gs^K z!r|3*^%Hw`XQ!r;?9QbX6@Kr@fMe8OT2oe9UZELN>8$tK_s>1m=o}Y+4iu*}an38Q zEty_8aZq(_8Q%{suPd&rE32G>s5+NuMrn1OW=t;EjPtcFno(C;ky~9_rWtwDu+?Lm zlC2p-hC?TJoMsHm$9Ab^3@xwEn=)f)Llq40_k)Y;i}Akte>^!0^hI^`xX_3_S+gKw z;8#zX0iUJ+qff^Lfl*dlTU}dQR#RPD-@B$3sZg(-IJ8~cDP8rZccXi*LoBpVqpvLqbtkmQ|M2Tv}Ae;3XFZp1tk%!04O$bi8ZA=HD-FeIzlX zh?uTpn9Vb9EPeLsU&hS;`B?8mYj2-;P-uR&%CDX+F7knEl51$bBpVz51CzGTg+Kp-1VIY zZc0C}W!~5G&tE%b$E~d&zC-^X7T6<)49v>z$xz>Q-cL`bZWui2tu24wyz|QwuWkL% z|71CS8XHztrA`IoiZP$nbuPz*bb{V{*!tbm9_!HQ`1y5XU)Xy_QtNZm5+^L)vFa7` z=L!0I6W06?yt`woUo*$F8F1WtJ5sMt(~64FdBqjxIITf~)lV&|=6|9I7kf?cJ02}^ z3NCk-(VGZn4lOydqCfsX$qi|q)Enas;PR%*zWp^`wBL{BXPNESq5W9=DTrB9FEQQH zU6v-vq?ZPV%jwN1oD?Ut*|Va*mh8DcP49A=o>~^urmiTq)wR^>W1J!*XQQdrvM*ZB zj%isF*Aic&*CG`-!$wlj+-jMFmbrL-GjQ_gVjZraW}9(I7@2`JjoIwRG<|SeJ@q2B zSv=B})G)g(c7s}I+G#vSvtbAi{hL)+)tH#GK+N^jum}D+SHzEnQJ5MwA#x7FW7pV* zs?YXlx{8|ScEIjkG|ixFV4ZLZYo||#yQOG^7==HpRTf&Up;kLOV|VQ-nszd^O4cK2wLQj_8Xh^r zj~%o~(=6=1I#mVvUoi7rOiQ)%sU?07p+)|kja^%Gr4?RV_%9}k^snwPq-dvb~82e_&$*?Q}+}2MI?F`>}>qjU4tyyIZK;`J=JxfOT(M-t}g? z5i#vlkJJ)B9?>Gb$6)s?TAmTpvNwKxIBRO7kv|B{Zlh+^1=t;j#IZ)=>FF4WYBSXz zHQYcA|BLIH$mcN)!)SPs+EDEZYPgXaF24}F$B}fF$1F7LjUPhHni}5|)M^v8daf3` zc0FV(5R>HvPNh{m%+1s;zaG2a(9Rn9)UGwYBZiURh?n!=?{;c8aV~cMI#(U|pP*ek zwVj+tC!y6H)T(M8c1!!pvDDh9r?&TL(o;-}E!3jNeC&?vr)eRcD3~S4Pgmxr5xfa- zbSE{-S%BSUG&2V+IU1q1QOTg7@M|8#vk<#0`l}=FTR1CG8>)Rq4ez3c_b$fn{sC&k zX7G5W%0`juax_}vw?$fH(NgU84OC~rKjCr%Ygy7LzVPF)cEq$( zu~N(J)Up+>@*>-Zs4WR=G`6Mei9)oyhuXDWfn9hgF8!z{Jo*kadOjvVb+RUE@FOTK z@_*E92AWy383EmgPnT!a#i#QWw7QR44c>y?dJI`BEkE?@sfUzSDxK8seros8o!B*u zRp%9Irw5Q@+*zHBtPG8IP@|`}V)p|Yok)=->4(r_|7M)GhnE+1$;Lg{B%F>hJ)Vf% z_ufpycI}fX*rsi}OiK9( zJ5I1K!HfRC@L$8_@)Jubjm=TdaD_+ z&un^#3_Z1;4BHZF4byYb9g!fm^&Z?gIlEHR+L?qdwqQv@(at0^7wxX5c1tiXMIJ`G zNZbGa38je7Nd3%0t`cg2e-Pm368Q7H06+R-ysL90lx%v43_X?dMB|w~Y%E4n9X9+O zU;MF}3f%jX+?);bKhh|i-5%ykuypcLZzX#=Owwr_>Zz1#rlF(QIY@S%>Hs^3Z0vk* z*}=?HlUGw#i;r$&fc!)Tnw|v%%NxuAp6ux|Nzc8LCSS^T6UeBtX*rdZb|!u%6F%I! zj?Fj7;vNmN9tYuy92#uyU2`#_2WN=-*Q>cHEy}}`| z_bcoTvqDW$pwUbzppDOWGIf|tZ5{?w(JR~nr7734MoI2u@h`F%$$`ZyuN1*1Gu~*F zsN~TMZrS7^yIKC5EMGPPmIurcVKd8~c+0<7={PcWL^R6B|B}(&xiH$~D!kiaSMI(}A8!L(wwgJXYqC9c>Ei{0mo^ zy?Hj8W5vTw(J9$9l|9xu8RwCu{UxyUz&r;_G%F~U+|p$}S$nk%)~=f`;^PwnOBare zI@z>0(wV9SWa`anFjcWY(}pSoj&&tBMX6$$av#A9$>3k*FqpFtD_+ZBvSN@HEyAE1 zZHvfQT?LGV7iro+W=u?0d5lWhsv zySoPVKBbHAg_;#|Q!>U9#gn?@F3VUq)mWo(yOa#hrH`4K*zc!Ta{my_AYu7ue)uhFzCEVCA!dg_ytHTJ1u5w48X`FgIW3H)i1 z8*$#emJAKO8irn94t&$GENIr0E{t@#$kCq%GW`YG4WM)JXY7Q0pRikwPk*(!&6>cN z7Wn|yt|M#bE`YT(+_-2@*7PRVPu4>;rG#mhLAy@0OVRRrR#Zfv8M03#%8F{L@nJ++Z5^5&4|A+p zVYqS5Il63!;-a>=dmTP7b{LMh+fu{?MX|?AnGpEs}|)7-Q)={6+T*6a+mK1nnR@ z6D0HYV|(F41JNuMq7$WP&}c=ZL-d_xad?gz)Y%B?l}-(yw@Y>r7QtA?;>x=tECu;0 zT$@i{bxVu*w8-_i&hxZ79*=)f(k?}N z3I`s;;G7BhMHO9Y6#|9{LJ+3%ye(OrA7D06nR8zE9B%mQ?SXbOdktf;zVDnWVCbN$ll@SSMt zH(bF&_f-{3jH?NdZs?ysdcfF0Y-HvmLw-aIEawPjhJ=|req>yi+z0vN()1vhi0!gL zkdLuoW_43wo(Py@C({>l>D!JV`C>j2k_#qj=ADGPviiIlx)*{;hx!4Rju=?@1s%+O zYndIMqlRy2$^AQNxWQ9ZQHC$5dXm|_q*XBfD!Rp^wFllHyZ+-D?4=CWK&;$7no@huZf8CoPHrk@iXC8wW_`Kq|K650X8j(;t* z;~Ui_Zw+WuYs)PDcY;RzXcGJnwfOI<^eRB-$^I+B_fl(R-#rRc*P?9;?UuBmIU|R_ zwVeDeloaKUJ3oG~d4J#}L#CS-8)iINE2aTS7Dcv5xtveRcewu#y zy*_x`A!zx^t~xmjAIHRvZT^vt9NRPvyzZqWqFbQBe)w`xmmXMGjjpaMr<;lW`(^d( z$L{UM-&F12zgPcW{L8_S)qobkDKiytk`dbX7L&ts)bnB{gij;=V5|6 z$dc(Wx`GFoqWvygjU1fSJwJAGxe8_{Sw6E>m#4wvh2Syv7K;{nM^KmVCj53J&frD( zK2}jl3E+Gw;OyxCrkM5I$Hz za~&TONi-hDo{aH;Kt@`DWT~@2OUPPN&M03HE8>$VjSl9Y(s;bm9@ylXu#PM)6t=CVOS)8(s%^b@lVO5?ojBy4c!#YkV8Ii{J7EQH)7!-=$xL7 z#OdCZrOw1`^v~xacc|~jDY2`ofs-NoTE>(!%EtJ`=(XqyQ(w!2{e!}lOGRDG?S0AXvtF7(y4GhD~*v!(;NOnIif7OhN_FM zZqV+*dInz+ESgeWTU(AFEoqT-(W5WPlp33b)vTOPb3p)Iba9^Y8>V2`=akM?nDP)) zNw7mqog6e6ZM z)M=@u(-f}Lb%TBu?OJGi*;PePVgg+YAVqQ}pp$>>3UWVY`E_YpzoI<;eY1R|dGWL| zcBYN}UK;-d+5B1>?ulS4C!y;^ZrHGzDxEN9F~V?HMn*mCckazXWDov4jxaM~E&(n_wknwt9v< zRZITUX1*3*E3r)F!qmsi)O8Z~fWd=f7Zq*bso3(=MZL=MLH4I?iZyUncU<1aT!qYq z%3dX{F?wWLkAjR=;hZtLK9P*kpvzaXC#!p$-48LA_D`bKN6t98JRZOYQVVULqohHZ z(Wyg`1_ffapXMk_#^3&ppVQ2*FUcv5){r<)qO0k%pkTiV#T5-@bu6FxDxU7snV$zK zb4@1AGXbO_g-ll`oQ=UM8y*CE1)Df(X$j02)M%M>!!ZpY^ZP6gBdCRTS~ku!I2m)} zbSB2X6m7WG>*@j|MN6KJZ+@0n;g_-HrA0Nx_^m-1F7}G5aLWdSiYvN>u=8&(og@~f ziMu+O86r)%{TA9M2A$y8g0h{M0qH)1Ie_3(rb7$BxmJoON8>KLk@Mf$K6{#fipAj5nM*@H*0z+#nUaljzeWM>Gc$z&dvKV)3o zU4b7!(#ve}M4p2qy2eS-4#|K=4(>TVc2q_nuT=f16Mz9>h4eQu4-3(lG5HJRr%U*u&fIAB#bFt~D$_Qe@cXeZ`o-Rv>b^180sV zx`vX&>3GPBW$XO$17k`18sbrw7@Wq9ws)Z5l?o&CV) z2GONsIsL>M-(?U(r%&U`6s?`4a3s4y*S%J`XL<)rt)s;^W_5Z-K?5zz@8I_Ep;05k z@LdFpuzt|Hoy}R*7SaKOFwW&=GTkLkF>f-}<}uRfo(yC1{IprcMHN`4!zKL^9sg3a z7nPGda!sD(M?yA4&L#K`nKhT-=8v|0JoQTVo|&^@Y?AP>)wcGrNm#|#kEWj~;B-UY zH}HT{v_E8~vsFm^t+=b<=~Xtt;xvbbSgZloU@LevbUG1dOYV`r@%O7AgF=nfcEBL@ zMoT7KJupcHd4m9XhC00I&aS-ZrB(Z4N#N)~3V(Fz)vpKTt(nl&Mflf3>&UKpkbbzD z02c*uBw2KqfmF?|Muk1&d+(y!*k3iovQ{Mt)SXHCk_ug4H1 zj~5D$b&V^N2RFV7G=D=O2RKc9-!Q8Wb>mqu6IM%v)g5+~@3S#C8&R``!xx;}7FuE2 zB_-2~Syu3~=Rm82)N>;-J=!7yH)-OCcn?7i?E*M#O$0pC1)lykwJ92Xz#-;Xob=@! zdjcHgS{UehP7bbCkgbyK28@bZa-R-yj@4A1LFnRsSnLN`{4PhOKsmrgnxeIocO2N= zR_ptO)*aVmEji0^wOeGJkZHa99qYZ$n1^tek`F4nqi*t{o^qNXrsJe@_S3GC`uLl@ zbjvMY+`5=rQ9Mn|tf%wnQZ%}A&#lu<7fCkVB|fiz9oC{H<|v_0I`A(=8)gxyen>%| z9$jdOveny6XKKm+ZJfRG{+P9zOox;2K>=_zy5yE0?Z~^56kV!$C!TlOrJ~dR>dX@^ zraDEVkK06UDbdnrM9n3a_?a)JLw2>H+&8B@A7|zHxSnxqz>ffC4;xE-)&H58qzV;M z)Mft}XmD*>t@`Ox3vJ#&;I6y04qvW{TqT0J%C7R(d}z+5ABIA8zEHi{w)Q1j=J_HOMupRqyT?p$w(i;nrVZy zmV<<5owE4FcuqdXkz9<^XUdvIHvdp7Zh~A4osLom7Z)+h&IcgfDRwdp|4b+6MBnt z$v&I97bmd~94cAguN8gYN{&K)iLVSmGJazptRj(S<{5g8=;hT8_5Ic5t8BJbH0$Xu zPL+2-*{N|q2bny8-5`tk%=8+h%0ZSYOXQ-1ZokMy8{Jf0C&wlqD7Oh1tDOX^SXg{M zSuC_~5@&I4Ae*4SlKr;YmXHn456D$k~!wTB<)T8m)DxAI%Bl*|1S)Kf*e43Vo(ITGSmH zKxYu*-R#{5g=8383*gHFWmTm@c!>}m=|Npj>tfdLPmB6P4)qUk*EHRZ61uDM*(r&9 z^F{PCLUOI6WRRIW({Yl5treohKnB)|qFxBDQ8JxYC%9!+UW=B`356v`Q#dS4bCA!A zhQB)0XT(huCa*I@yPfhZ!@1il1lyei_sjIB1pvUmC7Nt=l+2M54*OrCNv)IM7Zwjs z8JdgmuZ4E8)HcJ|BJ6B4dqVc!yFzlOqa??YnCA9~M(f8@LeZrtXXR5NSm7jinccyx zn_fN@D=?5!BU;p0*<*THCq&D}3m3=*`byd7LbBLVlAgtH(6afeOz8j4uL@=K`-I>Z zC&8?NVx;jN`AW37*h$c@3pnA<*(keK%rPCD1U1|g@5G0NgP(1$U~e(wnpI3UWiA)C zb+g(c_9`K|&f=(SHVwZ6!oxL=k|*R%Iu7by(PU~jHsQzJy4xzm2l>3jNWWZEwwY+1 zZN!wcT?iLh7|Kg&mi$IYu5y%YF%yzwGcQ}PHm5Z(zZ*=kx6qcGDaG~H3&XeZ7)ojy zip-Junh?#ge40u4z7R!erWdDxqLL}>Ylrl z*5gTb^z$?=vRFu3niBLErg1h-<_TF}nW-kiUBb^D9K%#At~Z2er)kjq0F@8cYlO*q zGiuJ$hoVvYE+UJ~nf_cM2|7vwri7a^KNo4C?Kb^eQ~d(rJk9(hrKYxQYFT~BbdGH) z7dNN*jJ{ulhc703vC&b-))pI{rI_3X+v(V-J_*|i*wV0_iR}z*EwGWS6}Dt-&9I$_ zjp|Orb}F`XY{z43hpjobme`tNBb`&QrD8h{TN7+2V@tty61LXOH2Soh)cRwiBSFi+ zM$pJ)du#-eppjXE*9Th%Y-ECTMuk! zVa%!bV~D!qycVg-dj2 zVKcA=vGv48RAyoeU?aNx*nHUV2sHW-8Fb(gl^z`sbiiXTs;j^zWOO7sz5as@lGqysvo4(OEf?@hUC;{(*GHhwU5R2vs4HvY1a4_4%V+sLm}G z{C|Z_$Vs2x*J3-?{#$FdiSIu(_J7Ce*!AH}aXO+8RXd-?>4<(*bv}vH5q+uZd>p4^ z*Plhu5iyDWR5`rJloMZMTkT8L*H4g<4sG-0YCoy|3Qb+I72ikOOc~h_cIZg2_&%yJ>q#bbMIZg2Qb&D+ z(}tWk2@6gcvVSNJ6{{N8kB|v0c6jeqx-%PpS_5rgj^7lBD+he2nM6ANr9Mq|pN0>SS zvnm^D%7hI%(u?e>cz2>KWF!~*g5L+tI>JR5Z#T;VFP5+RN!SElDhqq@zCJf)q$7NF zH{X-JFR@WuA*XZFvD&^Zt}WR~$3`!*y$PFYyCurUYI}KHTe3s_Cv0CICvS!FvD#i8 z*OqLHbpYXBA16;mnbv(yeESs{%`eo~^rCpx{J>IQp7RN>Dhntw@~6rsDzf9_WV1~f z;m*cJKIugI?4%p#p9Z+$OxC3?1#DQ)99y~30c?o4bdr_)d-yGP@6I&_?{Ei>B- zZaShYxH$pu!`MXp6qD0jbPi;MgI@9Hrf*D{z)E(6F4t?Fcr~6@FUd{VCXv#n1g_TW+m!EMp-Teh53o zNiUi=RJ;dJ7CeyrWNfrnJQfVw&9>Y!x1-v=$COjfQH<}HW$Jf&QLM-6>rvPFFB)P-b+h8Df3y<0oA zD|OV)v?qoGc(_|wGQsH65Ybc7u`(u?9%eXc>7 zWHi+1MekMYWN2cN2wvE2*Nl38~GCWNKdp;ZN>MUu%&YI6xtGI8n*FRj-~xCW_$7*-(K}|m#If_ zPz-mPWzi=Ti-?`@P<~Qe^tuh(VQgeS-8_;G*{37DMErCl`&HOfj;O7Wm6HHyEDJnTcPw}wf!?v;dD*nDa--teZOR2dbIr2AL*s>V;b{Dd3!PH=|w!=hmCxR_9=KzZQR-yLoV76 z!#mNImcK`9J635sTxm<=Tjh{qCtUO*Eb92D_ry6Z-TPt_SU$r$YD4EKdeQst=6m8o zZI@}*69@aSsqH9+M6d|IWb@WIn`B>{=Hs!@WtWIyV_ZAx%S5moGVKtSYvODYmLJW! zcr4$T_0(>q`Ci0DI1|D0FU2N}0hMcd|B6``kL3lW-MYATbg4&kmKbyK`O-m=iGC-J zDQ9+IBfqrKIi1Ejy@+eVKsG7cXF`rQA6`F*2ceSU0k_j4W(sfqtz zhJU}|A9LExYsQhrKmPw9{sm*)xw;GOWEzZn+Zp#X>Vcj^oH0CRE{nx{XWi3L=QcP; z{GaE^Wvzb`#su4*iMqQ!nKFL%Gv0uO%i$8gpK~!B|FZbU|9L&RtZko$F~PR)MV;FY z=8@O^%UXY`v;KVr>+_h%oTh*JEj&i@d>zCU(Py+M9E*PD)iTrbeV9Obc* z>$QXj;|a8+QFnC&{wmS#GUVI`>s*YwtDkei{fYftFPInFrFgje(ISkaKl*8pfB2Z* z3x5}Y)hqC8Us$4n@02L(P|;pqD1#n(w1=hh4}VC4DUt_q;7%S2VlV1`4-QJw%HC)X z4wof*`jqTJ2qo6RPF11@hw~CWILMXg!7g8-2Os!K^k51~^Z;^+o^;6`BuI&Me2UT= zC5nlRTc^Fe`wT-XkkJ*m>aD=QiVpaPy|)6{QUQ1sI7;A0e=910s{&`a3S<{jqymcy zc&(_YY%gzRf*X0p069`#-d{p7_3zvI@RB1S!Rrhm=7f!x1IO zar~sOQG!PKudITv7r|)0JVQov1moanu1Vd&Xo%&T7cfK~A7ef;b1_sNNdp>rw2KV6 zVT3P_tfkwpx_xsqpUwL}`>(0KxlPZ@o14xQ_t#V>j z*{V$yXY_0;pVU;o-MBK8z+%Q~93WMZsn+;AZxc&9K_i&76*Cnm537 zp}_0Z%eXnQvB_u-v+(jrtWm? zX2t7WpfZ?_os4>!jvb8pWlzVR64W?sM1rE3D5zcF0kLc+v7ka5K^=gg_N!L=RI9zh zh;~I6qIITYKO2!d9s8JoWIFaT0XfrgpeV=tuZ?n=iIg7-4-kykOPjreHk2O?iSy)#~6-{9)+zM!M5+q!q6Zhst0&4mIj!Iu17KmpvWFNKklDvk8i3qM-1)8wPc> z#DWTK1l5e7rdF$CtJRb+qT|tpXr1YpY9n%|<5&}rOve-xkTV^}i}Go3CW%Bdk@C~v z0fO&2dmZm5YUfi+)t+X z8ATM(gC@3_WoM+lhaEt_V5Ij@0icI1AU92XA96;UAH(NY`g%B?&u{3{4_Q8ogwOA2 z6+Sc*@!>Dyf)8GBXZX+tpXb2mnQHY^wR$2%)X@y>WQxuxqKKYBNW28c#6p}-< z!RR$GdbL`;90IB{sPX@5n@p$`maVf0=MqmAh7^LR!ZqfdWk8GR~@2B1|K(M-f> zI6Q#SCMbjvZ7}){jJ~N>Uxk1+H{-T2MI(wRpl?iUl0!c_fJR`X_d@}oA1xp^hkPHx z=c^b#ThiB$@q9+2Pyb-~d@p?df>z-}GZCK&@Bltrp%6Z_!Dk8h{86ob3;9emdb4c19t@XoFaXnnu;GCb+w@ml?FTDfU4T#nrBcLE@N= zNIN^Y_QgoAQvt5d7MGh&zK`XnwI7{#j;FOh`gA8ttE1350IfocW+GZg!vkm?fjq#!e)VvG9gC4(_nPQQu7?Gt{S_s@x*F=sPwemX z-XosaRP^cYme`s?>^QUvF`9{poeB>iHUotaqYYwpAeIVo{lg5JWs1{KL~*5@{7O5x zPRB^Ez5rL+;&SuL_p$u6&Y<&jJgqa)r|T`PwS?ALXcbyC6VbX19zg2?6hezOXyrg_ zof_3E1a`R@cZDggL=gqHj+0+~9AH;rq_=KO^aR+)0@MDAl3%@AnqODbd!Kk>*Pu_Y zYl-z1V%MToh|x?$>{fUHu^UhbG1?&355)S0xNb9pZa2jpD5ALfI{CGsgX>O=^foBK zwV}o3=9lkd`Sa^8I^Qs!);#p-4J@txLhEj{3N4z6XuSvzp!FmQp+y_C#(>tS8a1*; zji^yugxFp}ueW)Pb5nhkja`rQbBs6DNB97FQ+*56gPZE-FYTuKRua@J*oXv0Gf`0Q z!vlhPU1C9nHiDXfpvKjxu{EkGjOYV&AzJ6Q;W!(SJDX!oK%7n8WCC(-wM`V|AHta^ zr{;@|42qm}Jz;UEFPr zdbx{RJRSY<9Y;C7B?-Uj*hND75u1|GXeJ7+O{IkPdk`9Jgtj+A+p|XPUZZvm<7$g8 z#OzGUo;EIbQg%0C$)xOR!g3~MA5q>8&O|xQM9Nn;$~%i-ObTr%KLpATs!<2jsQp6a zYoIHdP6t`#`T$78jL5NcKP$cXTCl9>Uhbh1%bIX6vCvEuOBx;!LbZf|3T?!46k<7| zMjaLgl0kbkkRxm$?i3u>vN(>GII{3AanMW@$9nJp`JTu}g*M`7MjTUX)Uh>cN*KzY z(G|_6sWudStTQK5S{BRk5=&pWmsn^fiX{&Z2w@`$0TtSacmSGhQONn0HW*z5MiWADW5y910KMvo8waLmPbNfX}rx z>gpPGWr*l7GxTs%9DyQ==vssne59J|AUYBwy&Gzxd(vEsNc$^F4qa_H3!^Jz7#&4t zbK@BujXr&YWpuqTItH!6h-M;2C&B|59fv{~(FUVC!05IbbxR27Br|TNDNaTa1$3K< zO>$_S1Lzct^zJGEG|vKZbIA80d~S*1b1Hq!i|6wX^y#}SpF4%mEVK$Anu+*a1P|bI zHVWZG8+;xFpZPWFzL3wwX54I3T!JFXXFlQy5@?ab=TeOH78dMdi!2}QuP6z0pMgw3 zOFz#C_k1p+_eJrZH?C4z61;(tEN1*Hadkn@+xu<)?Kkoj(;%>o)Z1CoQcfgx2k76;W_GK~pS15e2r`$*)%&U<)zQd%0l$d&L6N{)&=c&$l$c z7Sa1F@x&fNpMKdA`==0l7_CB#W+GzG!vlyti9(3c2C+9m?DY`W3ue$_Q@n^GitBYJ zzus|hy@Zk8+XcAZvAEp)@_j6Se*Kfq--)O7GWzt}meyNB>lL&LEt-jF^}_FsfmRBI z(4q}my;6;;A*C`YRi9FIDV0hEcVj&a@YYFr-}oPy(tJ3qA!TnuXHw=!#*c#as0WX` z)urZ4y8<5(r#0vlny=)i#c!%&o_upY752M!=v8Tcwb~n7)$62aa-zzzTrTljh7T(% zGvBy+DF(AH1`8FMiKq;Q2RQ1BLa5LNl?_0pUrO~&sr6E-PfGPpsXv8aHo+KgqmL;u?pzCZ*K2DK#;r#)m=ei(c#}Ca69P zYEpbq+oE|oKZzr#i7Dj&1c_-pn!l++a~Q{DiDN(bl{jc7ieoxFK>jfz9~Ih&V{gQ< zXG-m!QoE+q&MCEH7|ID4;O$$mPw#1?(Yu3raC>K0Ge>fJXJ?zQJDO=Ju}??ybtbl_ z_btj-(_-^=AK`H_1`7|GiFlk355RC53dvX6;Bgpu9FkH8rPKi_wOz3?k>&`cD^WAFg^ z4~l$LXd{lZ5yzP+b$Uw83WInYUC|)Uv_ZJ3b$VijT_SJ4~Is!QU-xY&lFFLaXX{GvcEmq7jn#}Ww5M1gz) z577UX=tqS%0=W@^+>lapQtH~2x;mw<3}g8e1H7A4-hbT7nHy|4dJeP(hrVk~JaXu} z+8+9@G~q1Qq3;W9Pv2a0=rb+$(07yY_!5JK2hBu0{(uKy_#TBE`e=j4-QaOoO5KrC zx24oAA&mc^7p$C}>@G{f&Cfdw2s!lK=1lA@hJ=^v%|wCpY%77Rf7;urynhvSkq!B_7UN+76uCsnu&Pyfd@=%0}A0m8$6x^k7rWqsg!ymr5+1mDD;Ar zGqKND67Ix4WkATpKH*I4V}^t?vCm5&>%p-ELNieygW&;z^cVf8&_*DyB9NC;>ZO!g z97eGTy1ds4E>m8%f#{c@GMLiECK67md}81gh#zT*`Q+K6!h9QLudK02{aVqinie~& z{}LEOF<4;GOax;LJb*zX3Yk^ffbkAsyp>XKge0~?I}n-q{4=jT-?A9o`Fz99r+=~h zu1IZy1CdHIk<`iX0IB0eAu6;X^;1awIHf*JsrN&*JD|(^ykJ-S*b3GkI`j5^tIXRj z*rfivXx>bVowv^f#;zDFFlZ)%aUeW^!Cok2-e?2HH-Pa~N_`QMI0)@PqfHHFWOXcay* z6Y&5I(fQCksC5TD4ZKstpm{Ylhxuiu+MS5v3hOy&OdIG16PRAfI~0Bl3L+ zqP3iKs*S<*0R8rg$Mqok^x76zgWy_#R>4Ix5w5r30l5B&LU7RruD<}+mbI#}R&8FZ zhK0o5HlyD$#k(k?#I{6Kye{A#IL0CN9!7ejYonLEV=OW4uPA$9qroo7Hg}K>i$V52 z9gm4e_5u3zXp3x=Ao~!lf{bP&WZ%I9kbRCqkkJORzXI8WS~ad#jSYEyZ-)M0iXTx# zc}*~(%1$`R;q?ZVu&MU>bch$_gieH~(JVx+fE zZS>lEUrS8;D@um#X0QvgT^wXP#USfW$NR=3>w!MKk43h(AnS=%K}ItXvR?22WOXP6 z8Eqgt9LNr>RR`Cq14CY(8M=-s{)8gR>rfM_WY|#-uN+2tM;7op%JOnE%=aO<4t8)I z7=x=f{T>yMYhCo|BQ35Y1Xmxl3ND(7a1DY7;94Jr;Gzv&Cji&9TGd>urq-%sLt=x? z=uJ$KM-e494N(Odc9KJEQ;hUZEI8_)WQl2iMai&cgI$nKb&wq!gKRT8J}DmA5cKI2 zEwUMcY$#d<8O=n;hirSYB?1`91{KEC<)AF}TLj?>X_f#-mT4ZE>9?xF(=gaM4VJYd3fRu1P2a z7j59W0=O=#RhQJNi)+<|A+g=f=siraCyFSs%MewNVOKlE_Qpu>s@mvx9amdo+FwyJ z>=J`rkX`H`yD$dXzI1$bJhJ`Jr?0Zet`ubZqg9a6OoZ$hcmT3PPzW;GK=v1W{JF7K z-B7FMguJGhp?@>Qu_&UvZUh2+uQRi3dfL0y;WZT_y;}-+-D-Kc8Rq*CTsPE)-wn;d z=-|7d;Db;z-QF5c>v;6(TP&@ch1N8*3N4z6Xq^cUpmh=op+y_C9z=r8uT}TeDqXAY zu2px1%+4|^oNbD8P(+!{cXDiz!|Ys)^cL1eza(5_nQ4DT$+7#K9MevY-R;!xipjV0 zxRFKi1kXpGUT6s}5P}z=RS42dMDSX80KrR82tnE)_$&xMU8|m~Rgc%IM?-wqnbC7h zaXpGCzNby(a!`B0!FK~jde0Z&d%@y!Q_lAxDfgs9>~W|5Xbio%+{O#>^ln6-e%{i1 zPUzi)R-s2T5xoWQ0D2mQ(4!4{uYumHwd&=N+d?yLktrTR5#{zO;t39IZ#vu_#z^mt z+UTvcH!U~quPABvvVl)2LLoqC1IU_njcWBewOXB8wN7=Z3vTM|j$W^-&fLJHX=njVmIND!=LWMS> zTMN zN{loU#dtnEAhgpZG*oCK#(s#gZ=G7NPW1@`yZ~JY-kF`gHb8fF)-$0n`E(y!_h+ZS zD8CTSL^;hw%5R4U2%aN?QK1dxn?ZTLP7SV81MAerb!x*<{~Z_*ouItcuLnaYPsH4D z2HLsM8`sG#ZSFc7+UA%kk_U;*!+t{~#Ch1Bgh(?{h>ySnBD+r_Lxna%9EA`^)~OM7 zYKuBGyiN@bLwpniq9KlSLLA|QxP^^H54Rx>waqah7G>dR3G@kURRX1%DA1ST0r5R6 z@u5N+fsR9L>tPO6(Ah!pj4IKm544O95Jqj# zDvW3*V$=;Dz^F3{VMH5@jsl}2>eOK&pw-Q|HB7N4if9fUVd9Zbds7@h-7(TTrU1|s z3&_nO--qPTVKIDq(ASiBK0VQ=kFk7?7CzNz6+Sc*@yWph_@q$?AKKt^68OxhQ`76z z@pbCBkWz0mdRP1Q;_vTt01G92-#-v0Aw4Z5M;E0>>MCFt4^I! zr%nrb4KYK9nqnA=D6g|jNRn0OJG?f>NbkG?Uguk0ZdUm|B&*JFaGe%|tC4=skH<9v zefm6$>s-OLC0Yd+%|y5+!UJ%PK_R$k1J~8Sb!DBpyiQ$Or)G!5{%S^VYl`hqM2TIA zsDcc;&LK7lBfV?uaHZg6*mahe_E(e)yWFDDmpaI1+x9TSwx{Fk;*m{8pT5>2yGD@h zfL1|9GZC_V;Q`2YMIp#&1KDjrc1xYQsZPxedF^M0?r(|%P(*p%VnUJ(yVK!yAVzw3 z6!5y!@^UlG_aPZ}lY?t+46cLd_s)1+2cu8lVR79qxDG+9;G)@5TwC)6(I?>50x0-$ z9l=E#xCYfXssZ(Cqk6SLz3NvVe46A7XuMRtNs}Qw5DloepC&h|H~Gbj;tfz=$P488 zY26R?;9V9=eL?i#dTKcl8v|eozMszm15Uq)5 zb4E18M&wT9rY0apr8hAFIj>C^F3Qh=Gf_@6k@73x0fNI<*U*OYF;G6LUX83*BkI)_ zp?JQs#`E0i7-hxlkx&_YMj2t$%XDmE)X$uL{4(Cxy_E#Tx7|okG!q5ozc}W4i3QQo zMo<$F)VO*zwq7-b5#7#+#<$}sjqZO|wLuD`>lZ<+qj%|(lWlzU064b-kh)f5~ zL_s|d4~XS)i3Jtf2x@NxwP(HBy}ex%r(<^$kW9y}CLm`z_7UZa z;Y^g%Or-oRc!1!SMKCI~q5KdiKd4?EP_On2mA{Ry=ze{WRjvYZ? zUl4t$#PSZ@ODr@K#qv2kAcPMj1XO4vmZK2M5%ub@Fpz(vJsQXnHV}6T4r^H)M@t-E zz`MjjGf^DBzysueBl1z9jX0VS$JBatY`vNihVm=AqC59g8;U;GnUg6ki{*HU5U)OvMt7z$r%6WzmS*--SU&YYawvRKZLSZd&2VxgHRmR|6H z5Z00qP@#=j&P6O|*Q+zbKs>ZZ13B9U;?BvLEsNtkiDMmjmpEu9ilaX~K>oTS9~Ih& z<5I*iyIx&XuPz8f*}x3l&=h>dP4v2SwwV=q4DgD2d(&!TjPx$Aj~*?quoSevq8#=v zvKaIQs29HIWdNOBQ4ey(H?0PuPhVai-n6<*7!5+JFrt}=(H8IkG<;`|?0>Yu=z1`^ zu3lXe0%|nlMwntt6j4Cenb>BQElhhiI)FxEq&K$!(2W+5nYjQvFGR$5k-S*v!FWb|QI3AVGMX=p_CTvJqM3-1 z|1zBY;7AzxFT;5Zj2@|14~2jZ!vFv(`6ir4Ol*=vPdb2(#CqNn1%RHkfZQDNeF&e2 zV))35aGs3kBQL^v!t!}s_=GRQp_zz}|AL$FML4vPL;nPy7wgpv_3F70k@FH9km4I| zqB-;;LJD%|RR__jMD$91^l1F5MWp=|C5K)xoQ2VIF^u@a8}HS4Mttp!e#J6+Ss0y$ zR>>ini5Oi74~Y0I6p}--~5>d@YWC&+>U!`0#}|!iQ!eK6Bv#e6B_zd}xEuzrp9Tdi6=j zXIXE*`3&&{3G|i2N8Wz(Wx;X!E6YdwD@p==VjvUH(y!lxXI_kCOJ1z=b384+7DxYNY5gd)_(B}XFPe#HJqr)Wug6eGe$fW4@^qtGQm_69fjwu& z`ESbMyKthwmN@yVj6GMKcktKfwba)uWL7q77Pu zKx;r+ZIo6Uq*cEVTMoV6`f2y3x{Y0LOp)SH{?M!np{ zEuM~|M`5;-&_-cXGAT3@g*FKu5E0)QC7DJWp-n(&YL^;hw%K6$UDBo2Cqe2_XcZBlEX*DUWwhfi@O;XWxnrxNp zNsx#ckz?t$R(kQZVDSs0cam84hkJ>IW};Y*f(L|fu!MjLZN#!WV%asVb`AqM8tu_Q zcC~@HQ?PT(;@CstI0oJ&4w{MLm;n!v|92FUO|%im0f=M2wAv@F_6kEe5na)2+Ruif z_i^TAua?Dfpu}<#+)FGp6UA~4JRp`?5&|l;5zAqS<&d;GC=BFWv_}Iu#0KKd$w4iP z<8X=NJb0HlXeNr|YIuPB*&-hm+KA&=#4#nUj!vs1!%(g`DfcSDP4}WtVIi;Oq0l8`7 z`;epO^cX(((bp;QeC|h|KH2h_DSYOmRrt_M#ODck0H1{@WWS~jKIekZ*=coVTAdyu zdeRJi$`ntdh$1>0AqAJb7dVKX!AS4?baYR;z#`KAijqTT8qUJ#^cY5bf0uVbJfr8( zr_Z;H&J#w@qg5EuOvLC-cmSi9Q3xa2V01YcU7A+2LqL2b7skD9ig!>%0bOchlN`Fr z0rW0LdRGv2E-F2&@B$1A28CpxnLi=#q!bqijqKc3}gaY z`guOM=kp`I-x5#kC-mu?EwP(~*w1JcVl)#Gt7t34eupC=MjOQL0)e)^ii)JEPYrq5Y zs|yODMH{phg4Tm+H9rKlrWx1W6g^Nxfj#Kt*TW7lzG%&Rs9^tl*aFl3ijrURTbf_h z^!{)>u^RO0hb*y0LM(+=Ax1M1v31}9#4;#^7;O-H62u-4as9~*%9)}!iYTtfo&0*n z!L=?%dQTVNddA{%^UL?K{Q1R~ym`;W)8Z@M^wXBsQ$j0zKO4-8>}Tdyb<`INu5GqqVewdrL} zZQ(okuEIuj@1m(SEp}>iLgZ=;79ung5xE^6K!h)x5+bxgWCIZCmr;E)YQ2o=6B4-t zz0s-dXL0Dh2sZePy`JI0xix=}CNtZ|;BaPkLy6-~_?0+lCW>PrJRlD9qA65pBaS@c z7@Sc9Giu{7h(+j%1~J$M;pXSS*cdi0ieXcU;h`V~nu%gqY+`s^q$38}h+!0B7@1Kc zGHQ#A8lF)@!$@Al0B=mj``kVFjI_b%5zxxZC?0&aFww|;sNpt4hnjFo9DJg0vVH~I z(_@Nq)3n&!94$Ov#bB9Jnu&OP0uR8z_gzVD(gu%-;4warhn=kq2`4%KDuH|k#}Ww5M1fS|&v_9DU+yG<&_*D;A&^}%YNw3a zA)~g>sO`d7+F*dUN5*UKha+c|U2HgdCuj{Ob_WxWOzie{Vz)ElEZ4+#!1nYWMH6dU z?8NRaJUU{q@SvH9M-O-ak5y0z58B{yAb9MbQTt}p-Wj!L2!pS30xM@?_qQb6iQU(L zkcr*fnbm(E{+3b4WYkd^bwoxTmQja< z;mFIGj>~wz`aA7bJVXA?Mx>8{++c2xG9k&_9%1M9Fk3yu1h-t%ydLD~j5<4`&djLO zGip{C*Y+5Rq%avQah)3<*V#^7XF9Q*?$l=$#dU$iH93fjW}>(bGjZ`{L=qQm%-7|J z>(Y#xolzHs5gm>$@5+Kpqf2d2dNx!BNqmusib>3m6=ji^6PLW^Exa%~8k^Kt7A3D~ zvB`Udz&HkjWs+$of^h;oV3PliLSWDaj5&aDZAM)kl9+*ZATo11o;iE1#o*@b)pl>D>WOe5QfVfV>c58Qlt3zNNWBeGZ^@{eGHPz9mai)E?kG61++qdmo1A%@+bZ*R zJ~pZED4I9ZV(0C4fpGx_3k;fxU|atkXJM6<&1hMjN%nD^i@;*3q|zK%c~H{<0xO|`ew#Hob)oQ3v-u-=woQGk{k7EYe%(({E(LXOUhPMsK54 z7|~3`h;IS{nh#LOWYY$t55egDjCwZ&#CHQ>+!vZg!WCo{UUDXLIJDgA+{f;6hg+BE8dkzRQ=`njnh%S4d-QQBWo(&#sXS}^_M z>_|VwAX|lwE3&aEwJQ2_c{WU`vMgt~D_R8^%|yuR;Q@|%pb%uVfvhUqs5)g;hpcLs z4Q|_|&CrY~vM8dwI%OH9dB|;5hgSnedaD%hTGjG$v&xH@FzZlBx)X$Rjp0?TnH z*aO$5-&Nyr^+KOs#p3EBxIDB9E}DsO<>3LiHb5b`XaiR*aMfg0&#da6RcnOAHZ`L+ zGsO@TQDQZSD#);UhuBbz^w!EoKfu*nV%lF(GOVY;F37q&$kvEKHjIwz$MskA>2)ox-hyjev>#uXGMb5yodgena2yIjMjOZ)fo$`v8kSW< zLSB4P7lxi}ic?TTd2Mb&l?)r{@H!PEy)Co2>uoL_Ch^i?q{GW!Q5X$#7!8SG^ba~4 z8P8}I`t+8T(FkF58d`-B%|whYh6eH4 zhtWib(PbFvO~~Ra4u{c1hmpUcFlurbjfr7&Ih{?6XLJSn^aRUjyfC^Ft-^?AB1Re> z!01*K!iY8)9SlYXX4U>#wQpAK9b&rIjOI(hu+se~qL>auRKc!yn1g9PMtX;4qnF`_ zIhgzvW!Kx^uoh(dI>`2pLG}P09~O`7LG#q%hly#8iFm0hpd;q?MWddC&;YPP)GgS+oTa2?~|Iw}U& zV)|{4$Mqum^l=u~RKfKUS_K!)M7Z9E2T!Z1J~)mH7l!5&8m~L>ZGii5kmXG ztni^JK0*6FSqnA6M9R~ zD)eY3qF3U*V>f`_oUFPwk##WAyQ_f6JWIsQB;Q8_$e+0Wym%mdE1JH`0=ZLw@NH<4B{UNO*$^H8gs(>v zAhZGGK>(SbRriHVHZtS*$}tQdfFjCdzLO=393}%X(p#8~-bq|!nP`7S$&&kGvSbh) zEQ*IR7=3!7g|a}PY=TySLNgH*zN8FM^4)0yg*Ko(4k(X?L`IlFd_5V)jzke9@~D#~ zPdP;Xf|1^nS=@0omrgtI^71K%h`(YaHAZozr{XD$MxTDtQg}ir@NH*8fo38Kd&2`F z+X;nGpbZKifWmuO^-fm3l~r$qIQBuW_j=aEv@>IR&xz?BKRx(G`&&L3e%*mPu1n+@ zpEqn{%u7(^wySy1>xU8@-!>-E(M%NG(eQxi_(m{^jy9tE0?~b*Ri9?n$6;v4pbKG} z&~{^JpWD#fo%&M~gq$8ewsrsOj4ws`6gU&*G!rR52_B$)st87fHkAJidz>+hkG2Y1fPw{{BbynJmNW9FskFLHj77*EAEB}STwVw?>R2<;pR z4HepmvAh9)yP8#hWYuqBfR~^P!8^0F#0Kcj&L4J0^l!HA&rU@HH+U(WiE^5Wl-~sp zaCDOhMuj$%cY^W`4XRy(YSR$hWSeJ(-ffC|P(+U)9UAPJw@ZV)DXB5it7?d*WS0he zQ_^2ij;Zb71b6BrC)?P1cox2w&bsi&P>b(v--kY3)ezo@>@1A#N2@TRnTXM2@BlOm zP{_VV8;sTjqtzSKY9XM<&A2B_@g#~Upw&%0a!J?I0rV6`dOZpN^|XN8tnhsZpVeac zJWXFcnQ>p6;u{oEKz&R+l0)k|fWE^>uWthmIp)Z+ zCy)E2|V){lqsBl>h-3+2xOkbnGZl%1{Ut+JKS=l)(*Z zV1wGYL2VeK>10NCHboVRD4M~DD#)E74w_Xk(%Y;ddR7_Ypb1vwS!JNlmw#=$af96D zm-o8c=9u$}`I;5Sol%(LZrt3Ec#x~3Pj6;HZYm(xK&ybHnFwSW98yDf$N~IW-492(i&Z+-=E{Lsy`QH^#dNwVfdf9PG6ENGoM8s zWb69lD|6D_AKn(^^t{}h>C^dL`1Go>bWM$9j9!q#S_2=;al$&SJ%8r(@2kq1XW*1F zn(n&GAaC!U^QX11ENecA?W3e4+|KwmIjlXtvZ;IneJ{3fvcHA;fluVh^gSZh*PI>j zc&;pm=BDxusdyuq`IF#Ps9}#MCy2wa2$drY=Nyg%pqG%T zi*xGvoO(8=o(?kgFM4q#Q(tE^qqvTwmY=ErWa}6NE8R`-_Hs@?9ha#u3+*>b&|X%i zVmruGtj$c_8k>1Fr=NGyHB6pYWixNC&}OhUH!~KSc`c`(HT!^}5hl-TvYod|Y-d@? zW5U7O+|D>jk^1t&{m7<>*|wyJ3EHHH;T-N$y2GIEeh~9s%Z^n-q7CjSvJq&1@7j(QI`PBK#ER} z9zLwBY$yi}8qu3uxDK8~GtESrzcZS@3N+J(=0l(rl^L{mAz)%s7gJPzYbz(7HvR zMm4;T8rmn|dpO$l&_3Z~yguI{eGK1o$ai?3fUg+{!T6(0%eS!)H+2L&iDsHD)%@4V zP31c_mG3~UJ3{Bdlkt`2WVQcfU*}GG|H(YO4>)`>M(oUCyZBAe{zDah1ZDDx!;a{O ze>ef`>g_+-_Tm;n|Cz_H-nF71J)nCx98$#3?*1UK$9ZqiA@se6#K3Bj81`-|-;3h* zMhr(Gh9iOi_VJFHtdE!skW64|nbrU)`|4xZW_s2(hGe*SC-~;eF#?Bdv!3kO zl{uqz4tpxbm*@VzY*x*;VsP0ile<+;tSVczsiOP#P367D5zNO|m6tWD53%&~&(kzG zdr+P3)Cc-;lEPxpCuj$xb!4N)SjH5^ZML^;_TRGE&+KN`)ikhKXMt#8?&?=c8W z`iVqiB#@XFi9f+tqxu0$U)`pf1~devY`h|{IvZKFrPcjx)NLl}jFCXy=A!O5QTK~g zw}qxbc792A$J*HTF1C8F*Rt8TPMobx$J&Fxmhj>SHp z6oi$5RW$)kqld~=mR&7VIY#6dBY_-T?LbZ?d^M_aEd8n6#v?x?rz7RC54?m~Wnkf< z)oBgBoHjny@L zT46imgwj;Lk7g6(4P2cYqo}kw2366{Nh?k%UKf~>{{HE3f3RQ0Z|f>;gI1F@R^>A6 zD(?>8qjJ)vIUeSKt{lQM+5uiSR09b?ens^}2tHQW z_k`m{)g4PeNB{0|I_6_zWzC(LqwIsVirGonKByW^Kr~eZ7$d>tH=lsBk%*{;KRmCC zr7xm+2D)%2=9!U`A=k}bJqF0B%Bbr?bzBL%i|jH!^X99umgZoH9gsn3eDKoRTZ=vl zBJ_t!fPoJ=$+j7k<=Q#x<9hl?(+AI8%g`~m)CTDQ+GK;0))m2K`PmjHdf6<(=KTOB zK=UoAXllo5CJE}O3_U!j%RHEdB=ay2E@U2h!Dpjtz%rPJyV2!wdYn+%59F(u!;~b1 zhbD@-ClF&Al8AXA5R-#XJduoLAZ8J|u#qRJsSnzTu3U2jM66N~)Z~oVt6d*l1IvYQ zn>K$cE9-mhuCIZ!HKL0YI3$7-j1Ih3ZZR)v2^iS zpwl!Y(fM_tb0B=;A!;lGo!?L(bd;x=HAm%rU z*$fSut(dojr~@lB>7r zR3Tng#eb67&E@#74cmHlG6}sYHbxvv;6e@srXdNAN_dh(!7%v5+fK0zaI{C4w>cU# zTQMU+Nh#%>m{NknM*ng%4n%57UFb;4@=$$3h?OTI9pk z$cO)R_CIMhcfwlXK#m|c{wM4P`0R#571>px5O$^^3A@$cLfCBypN*;!%Ya=sbP-d1 z;i-p%kSB6Ls5G-V(pR*4pvW{NQPd+)G+Gq>#ZlDLSF~B-(Vc@pOAhY7qA|Xr>Ohfc zNTO)1K+)EsXe&n%@7a-2x{whE`TJ6NrAun8uPYtsG7U*|tsUqZ51)-{8!Usl>*ebj zQb>w}K#JK1U09Cxc}+kEbIJ>JnT8~~dI!2DiLPz2R1>iX#I1||++=P~vkxK$>_AH{ zn);yP?FcjI3w8~~4vyFKg_VKU-iALx$pC*`R$fmYPSP5Y46`iRLkIA({_?PyEUpmVxH2 z%tpqVVjC3Rk?0OMFRaoW4T$~lk4OD+g+s0a=V=WlHx9*EY95b5G@FJbnkT`9Xg&r$ z8`V)*2Aa1w8`;qmJE8EVqC4Qcph|NzAojyQYTmhU$PeHgTy0OmSZdw{g=jVnNi^>P z7ovGOd^W1%u~f%l5eVN8{hAHjFWHN-N)9qbt*caYHb_svFv{CMkY^f_$U8WYcM^Q! zrLtHC$__!7#|F&>Wc8Obe>G|ZcxYUAMW>*fcjSxKZWDI%#(YtChp?M>+l#uphTTWT zb*IDbqtG3ShTQTB!)+$wAh)AY$h4YHI*_B_io!EY*cr1iCJuE;jgAC~3_hFe*Ft!QNr6Xu>vJbfRt0 zr5HkF7Y6!FLlS+L1p2OqPyAFimg;gW0)3ZK9~&@x++Bxg4l(-V19GIT(@?ezx&}k2 z@3KIjX-J~)dgEyh3b`hsjoWkAV+;7DJ1hgCH<*EQQFu3^okzTMKYnWGvE@cK--Kq( zKDGv@$D7fk=?H-^z_RRs+hCck-GYiVnoH{&*a2_1qQG}zG7jc#GTfVsUdKJ2Ya4Vc zSIFHgOR38sIqY@Cwg%k79*OIAR3b9!2i(riK{6yKb!_SmG)Wx&F$LutVZrF`WGiD3 z&)wmft#_dn_X5q<#f{twx*N@!D6n!gtb4cuFSbmaEu5}Aej_{GR9??;(wL&VunD}r z7fXMN@P`ffTEy)1^U#cO4YE07B-orM-#;~#d)V9qvbp=QRQGam4;KE0*U@ZY0^?sr zcEAEy*m#b#%FJ#12icVKJNjt4nK}K6Dormlr_X_O|7K9R+zh(1+jZG+_blre8CK4* zF~d4^tm=0{mf5Ienw$+cm9HltL`6&Q#ghB_cw~v(*9VBlAQ?a4hoyRmi-lPDAo^*x z_#oP32RsQ2Yi;0wc$`f+zhh%fH~hX>)5~&zaEC1gM8qA=VzI!wc8qSevTz)3B~y7% zfHgb9KnJV@(o{Z3z#1b#hUM`%5y9fSHSYx=z)N_rRL^kn6c#?%O}!Ukc-KwBGYqd} z%bJI*j(v=Spo^b4HOJ1J{sR9(=!NWPeEa)K7KyN#=4vz~zwnXcrgi(ynf^&yb1PUc zya!n!X?Jz@WB(hB#ps8uArhT2S{U8DYs%rEx~aS;;&TWt!__&5oKh*b=JJ zjFkQ=Q(K{H+mGsmy{jgz&7zcE_K|1NmIL3;ZN%4?p4g7Y9Y=HhAeHmWDF zRF7lf&qecO40Ce)8FX=_9ndUFOhYmyTjQ6n?`*|*&#XQCzm15L=6L$Lsh>bc}6f9Y4qGkmh(Dzle^Gt*qnMcpcIluj4n-k!ocfzsKv4=6D@{h>nd~ zS;v3kbx3o(jwPaF?N-)Nc5UqOLz?4tlyi+`9{<{vIR1Uu%E!Noc>U5`N~CC8+CjSi zcIM%`Av{6{$6;L679591#RIBb8laWD?KVr>c6f3sH94()a%vktInw-pG&${-256a+ z^HVElZ~J&a(j1>$9hRp5e|>^G#_N~n#1q`wkUPbTl;(KIodvRL%ybfuO*U?3E z?BB{dR*Bak&G9-`6&;gWSx47+9nu`HV>QuH;?ld*vM#+>?5N&tg|^+=IlX#3J86z* zw}$B7td-|*&3GNs9IvCh=s2R4b@YhWA!=YOceb*QRJ;yp zj@MBuI<9PG9d+?Kq&Z&4TB75^R@PA;uS1&Sb)-edmaVKK6R$&><8@?3M~P!zc*5`g zzjV3X5U*dF<%BPn)#g@53C&A6PKP%(+I6hPt&dU5yoBgl6n5yM%y+S3NBy-!`v1=Y z>lFsJw7XcP(yFyTD0uN{CC&dI(`ucN{(oIswf2?DpW>%hn&Xdnxe(5OLu&Sp*DuZg zovGQ{Gq`R%0cnn(!9FsBXSDLUQ^o6$=6D_JiH?(6S;wE_bx3o(j=rK}YAfqlKVFA4 z$Lr`PI(S}gox@J2rJtt5GyO_GP51xr4Xm~I#tq_UU7BNO9gpXJjv2?FC}Ft?zQvJm zxFiAc@--K$<$3v9i`9y}d_%-)WnR9dVYN+Oz9(U|ZC<{rV6|OdzAa$2eO_+Zv)Umq z_sm)Cn3vnutai%Fonuxz=j9$Lt5tcqWyxxnyxg2)b(Or_=VEo$yxfgpwQF8(h_Jd^ zUhYY-+AS})1z24@FQ3v`T_Z0acv)RDFP}MC?Vgv9eXRD#%O@{Zd*O4n?{&s?D%ec`gQXF_4Rmx!4d3`5M$4j+#8= zV;=b%##`T94caE)A0BeRxA@-XXwh8BK0M%U0h1w=$v5oY2;an?!Qfj{{3Y(7iD)Uy zjhCg=$KfwAU`4;{AG|G^@CEFy94G$#Z#0L=io0=%uhO?fDKg}FfmK5vX5%B5+RKgF z)kcZ(f@=&-57wM7+X|&TdSNhb0gN79;+xwa zstRyP@j~2%i-xZzDmD^8P~CVF()*L|&>l{6N&9qx^BHrb28|+BN46 z5vB+1fr|02=?QH`0&+4YjCfD3v4RuQ1RqHzzVlOt40OzIbc%Q6Z##=>U*Mqg+Xl#w^Wscue#6>*dY0 z?fq{XN0Al9`+PKy(Dtd1Q63*@@t@iFo=>FlfbKtqhG$23WDh7u*3{0SOEZGNKabQr zM&tN?O_s0JYRBjKYIb@;1>LKHO1S*NqAj=7Z9C+ zo=CnLk3n? zR#eBW@j9eAUdL^sg9qf8OYiV2i&B@~D|S@BeTBB&+BtnkJUeNQXLqOQFMNn>Md$FY zcpcIluVbF*D13-)MRnXAuS1&Sb=)I53Lhd{Q5`y7hcw6QxL0%(K18;nI_`_tA`Xw|kc!_4dn06zUP5W!F z*s=cMkoo_Ma2^T6i8*a9Glg3FL&2l*DJ0GRe^ThNkokW}3bpnX$m8+TD9!OlvL`|$ z{|#yQWW0W9{%=ad)}FVg;^UU)_<4I;=B@CNuoXQMJ`=A)n&WjmD>@1v30qMe&&BJI z=6D^?i;lua!d6tr3-LOnIbO$N(ZTcN3Lj$dG}zKky5T8%WuA0j{BH}VwfDT2;%8Wz zV`mtTf1N5&_|+62|B~;fWU}+}1r@91dHF($)r!1)x5H{>UcO#owM|~W;b66GUcO{t zwOwBB^RwDMFSpuR?U0wd-K=)Z%ME8%JLTn`FRPvNa(9!}s=VB6WVK8F+90-7@^XiY zt*hqcJ_@T{^KvVL)z$KHH-Xh|dHF!k>gsvY91^w8(1rynJ9|wMSk) zGqKt;FCSZ2tjD!)U4L$-!&6W7@k$HEF_aRJ%;6GRMv2WVPzkWnZS?+sT zN*#}X(NXvSlic4L{4<*H)oI0b1>Z%!Co5L68IL1;0?Xst_Bk$jU5xp(@aa-}qpRU- z1dcu&3;Xq}rU&dK^2IB+71YVhubWRrgMLB_pZsd$EBg|5;e!(NW}f_tZoB9S5q1aL zE`A#6GrA5v6h8S?syDoC7(Dq!g@{2jZj|W(Z7E$GYdS$&(YA9kCJeS+D@?;zj3y~| z?<1~V@X*(P7iKCXX2vO)+b;)Z853ge;A8&$zdcy*TPiGg-iybQ-~j|i00`#c1$o|! zYw&rmj>|zs#%O&$n#zl@AJ_-B-;lxMtL(~ z`_FrA#b?8K1h>z7@lYO6j;yJjW0htEfqx#Fi=OwA!z&JBoqd{LW6(;X`OVT?C#Crv zoCXnVibu4agN9W!x5<{JJljPNe737f5;8b{1<>bY6D)Mr+V6`$Y$5K|?oBnG#mp=ViO2b0+oM3^FIv zAF!q1*)CDh(yIl&Yq0rTyj~5(*(l_dWwddk~PCx2Z*B&qo7Q6UEH7>>> zY|jO~{KYqKD4Gf}`pyE3<_j$fDaI&2V-vwhhXF>ajbh|4*|-=*5tPc$)$om@rlEx| zu9Ix!@7KW7%_syTZD9OTFph*0HG+#RxEPK_fbll7-d!j(JAI7E#;st{C4bh&#W;%X zxuBOnRpYrge7!N~4_t+pMfP`4Ch$=XDu|-d{#JqvldWLu_o7`g%rqoH!=J)|r~6R| z8uQaQ9zS6=stHh{#&I#0izX}rG!J5hNNAcv07#`>Y%bnxDVgxt85bY9( zX-E>t!*Bsl5227iXk(6d!WJ6U4p^$~x!4YiAcjZGDvzS@c0+r?^&^G04Km$4n8LOF z3=R($k7ISs)&1;9We4mIi(;NYmzy0svppB|KE>@uFIhQQ4o%^WavCVB{|mdAnd$cf*zK zg5&0k?B2DoyKT_TUmwz(19?|0-T1&NI>u0_2*67vLZK?~_)mJ|)QU%LdAU5AgOOP@V!+;}T(epd#V$8t_^m+ehQCnstI;XNBHAcrXfkH@yD;==}Q!HtS~=@a_G(9G!)uM`tKVf@Gy3ZKMg2=>Wz#u9vFab)SJGymG`7+(l~k}EgWH-3&) z#cQn+s(x8Xs(z)a<9t=}(_n?HdX!KkzY13Pgmx=%;xC5fntet8Vc3O=nwiKYRN+Ox zW!_3qRmLOK@xH2Z7{#i1Brl<=f-9^9Rh3jV%~#bXR@J{st7^NFRJEh3>AtG=ajGVk z;M8FyDdJD9v3DQdpG^vtcYl2olqRVVtYy2h&F z=e!cER$ED`x>40hzN*#ZR2^4B(HbjB(VA2=(^u3zPEm7nX-@q8x|MM>;E&(sPWDyt zSM7?j+&mc-Jx%d4yM}{T!Z|NRMW^_RYU32ik9U@sy}Fg8ioe#EJJnak-{&jh)ckVk z+2hahd4-Q5x59ZZLskFqRb^vU@iRdQRt+mj)!I}w%U9JaPSu1GiaZWp2|2Y66`kfQ z`cs^u=C4X~%5jClhqqf{_V|m2xzl}B>&B|${jUqs}*^R9cXm-7p&tL5du&T6;398FnW zJuinbR@cbOv4hn$^RmOT+C49O39CKwlAf&g%u7zNTAi1P7>&a%0px=4`@vv;@L@Rk zywIPNcoWhzB>7afF+uIDz1e7& zTU!1%I9^XQUW`Wbeegv=P1B40d^QxXOu-iU8wPQp4Elrtu2`159{4L-Do`$24kHoYw^ZY~BMs+omsVlj-oQq4b2xh*~tTzIM zcRkvRW_}JD&CFjH)HJ;m&HR>dq3NP<=5Ih7wTe8ooF?_wDGtaI#8!XIQ~xMZI(8 z`D3dsa7HqvolS+OcZdkF1CGrtIpX66?LHBB!?Grv1rXu2qz`G?U)ZF_JVg)>iScIK%u zn0aR-nu?2NegXaF0`Gg#d*RHN_Re5}$%=aC%)Df?+8AfS4G z^hp|-h9qfpFkHaXfhZ)6Xd{jI=k$&0DJWA+{M${Ojk+Ts^#YJiK4E^Q;@AA94g=tjU zJA(-(E9#wTbQEz!PBp~9@jTTOk3YtZ-Je{M2VYarCzER$l1%PYxPYf)QOM-d#^mx3 zcpKHLP^Mny;w3H?V-Za5ab~?{6yBR?FPhvp&}b(2^`NHdrD$@GhYL*?g_HXh+NfH%zqNpG`$qf{ONF^>7sDvKSvw2oxyDs&OD{rnWx5J=ADgb zDlVG&kLfoTct4BY3unHxcLozoR@6IZ{_NItb`G5trcr5S1YTO%d2kj|_R~l}K=t|P zlQc37Nz&+IxPYe%QOE&=Hqz*OXlhj7VyV97;!7_6jYW_~{LNNEImlytFo%y2) zt{Wsz%;@mjWph{F9nDY5ZNgtxm7j9f+$OvY{u!kxz8p$&zrbP~S5Q{bZ4Z9CDz`lt zflVt;{FPjx@Ncpix6M%k2y)a>r=!mNsrkVdaurqm>Kizs#HivomnBqTCtfM4uBEEq zd{x)Qsj4fXi0iBjPS;b>@4h1bes=Nfol%<8+?Ay2MymS5S9MdYs*_8rx_Kq3x`nF# zZ5ssykv;9ba12ohwNde|S7s#_YmQK93tIIx5^!TGibv zNfm$HJXh|k(s8Orl-U37T}g`WqoN95(fx6Xwk)A&{z_8x02NjGiXMzp)cktsnOm@u zR4t^cHomGwv8wpQRS8xPtt3?sQ&n4E)gy7LYD*}3l!FWZvb7b?dyi33J73Y`af+Jx zxN8YjPpl+WPf}HTU)57_stzfk=;@WD=ou>N;46AIPEqser8zyv6$<|zxD{sad8+E@ zt9l_;)y&eW7Ox~#FH%(}U)4)-s)m=Cy?=6W;omE_0;iX$sI#x=l{iK6>~slLuX2Tz zaLxHIs;cr;y%wwLzS6Vz`btvu2K?d+z@Pjpgv+=YUcB=QKxyPvepOzs;90HB%VjgG zee!ax%IYS0xkzMnbY8B^Se=}g%OO_x&&xFktHaZ zFXtLDYiY_sUd%o;<>)FVzhBMEp-s&7Xv#4~%uQ&@4lU+rnzAQ}Ihm%Uu$cd#DfuJj zY??B0{KD`JSh)b#TQE2#_`)#weDOBg<)fczNb=F|eYn8p-bEoFq-f)#A77N!s8&ZB zsnxhxm5VM|1RwoAFzbDY!t06lqB{sZ&}i-;bPsFA&!NkQLkUfG6K*E>l*k4=T0GQz zt@sf(q`9HO`wZ1+V+0>l2|uyAw`~}J{S3!Qg3oZymNetC9|--=aBI?UF7W;-y%*kR zDD9mg`*9R_=f};@TIP%-OFR2FoP}Uq?by&4=#%`AU=n?;_zhgZ(^n`YKWHOA_+qF= zm4-6478kW#)L;?h$G2v^?@)NX&|Z`uYopQRM?+X!W`1xp@%iyRHl(?s!u;^i#t43( zlEVC805(4uNsu4TmNerk%8xAl<^u0O(R*Qjl=jZxgDH)AXMX(LGH2vh+S#vg7J~8f zL$qTb*@f3(Zr zDEPZ>jt?C4L!-%$^}|}vF-o0d6a9HpJLZJ9ITDebHsoZ&BRByI@p05b&R=fI!gfHT*TL;28&X-JX- zUEl(qI-`&rpp6{hGgpmjFt(!xaLhCbdzNyFbl&IN;>;;80GpX-G27DY$^AY7{cfv@y+m;IC1Q#CFsO zF1FxeI2OS)*P8X}PnS1Z<-iTU=^u-MGDNq(7WzoYt5;X2!N3s_^Y~*Hm z*vMZoY-CU%P2NZ5fcMChQ5;7-ljkMuxnP9OiCEri|h+ zD?6Q(MSlWh_Ke^$E6ac~ImqntK1Dw#59Ow-d(9{zJ%K>U5 z2k3TnaG)G^0;O~+p;IwVA_w~LerKRap9XqN4on4+=Rl>bO_8;Ky#6DDB1t0e56* z#u#R!DS>e^Wik}d_zoaZ$`np$N~R2k3TPULf@KP|kty`JWpJP#b^;gCsfJEfIEhRd z!ut(HkvrGDIe$({3SXJc#qitLU_&V8UrfQHiu8x5Ri*jFD+qbY#jXTC=kA zNm;}d3*kiabj1>D`~t`$8CYl-rVG)Ou{+5y4+>}qOGuQGffJgN4CPP(O{FMUGEf`I zKp$)j4qOX6fu(d>LZ?MIiDanY{U)PGzX9}^WLN0 zPKFyn<3UU%ucDKIf(a)BMJ1Af+!EtQF-9iCv?EhS(VCS_CuPysHD=EUM6O zxG{z`Xi8w5Oj!;EG`_VYN}0k5P05r7sDP$A6f9GyjZC4}tq%^|4m*Kc>2x!lZo)}q zN+a(#14a5e&|@;?E)aR9td_M^vi6UeLI(AjG7~04WHK^SynXHgjbfRl3OI<}NxaTN z;u53RYaz$IzFXGT$eN4S{5w5nuP;@dQhx-po;-usm#G2~UJHpU$m{6*ry&aGKaG{h ze*#-%8I4?I{s)gt8DU^nHs{EcQ9_uN%{?+@lxJpT^Nvgz4Z2y`{3BCFxnx#$C6viD zR>vE;umC(ZuUXnQ=_&PMsDP%0DA>HFHs21R;- z^D?dwy|9jiB2(yEl6eT^fByCwnQ@?y??zdM?jh<9#+lntGC!At+Ic%#Osem8=)5;;|V7z zsB{X3KE`8Vu#a-iW`5JBSR~(BNUuag{S-?my_uBKy3PqrS=Voe3YfbU1;drv7=QY6 z9{80691J{0r$_1Z2u@=B@8JFJM3Mds=rQa1Qy}sca+j<>e&#f+JZ6gOEvVvA?KrZi%sx<5 zj~|&b8bf_Rr0j_!Q%0#_R<;w$01S&8x}QW-4!1LXULj1t+eMI%@NQD!%oIZQ0`{&d>diopy zkx!pbW$hDL`^V{{8jGAh`(QFeCZng%7oc$ro+q!Olbx^#PagtBOdoPf3@1SpIelJ` zA^v-f1gKu4oIWo?EwY3;jq!Wg6xEkd#iM%V|1zpqk4%|4Aeug}9hovp2t7Ka?DZp4 zMtNpd_6C#zWd7`Umm>B7f}b^S8A1rDH3&84~>$&YRboEGN((bI5|D?4_2} zc?=rNC*m~GECQX^I*&5vAP z17u*wG$5ou9jU0m{~{@x_IyG#W!l@AAuwQ}V53ZJO#AyW?c?CSnAkLt(yyDiV{VH$ zEBLy^a^bwgUgkY*bLr{03PpAu_R^Sg2Gw?W)6;Yubm1eiaNgTKs)UsEb$ww&Ok%?Au zcHQK>%K8RtVVo5gpJ3Tmu(r7ct0Tb6t0^s+4nvZ4)G@@$18Zlnrw23BE1 zU3p2B((72T+IZmPdD8ND7t3SK>PNe(uaN3XUDTI=X9%p=Z25dw%hl5IG#AU2X7!U@ z)z6aZXSk?u0M8Iuo!N4&tK~V;^5rg;FEy*5?W%sURDYF=`YXXR1UAoPndRFuseY-8 z`X#P9Zk9T3bkVT_JcEnZxvIZYs=v)e{VlFK)=M30U39Dg&*0)}SM~Qv^&4H(Z*bM| zu+*{D?8bv86}J5VScY}Q_B;aSsPg*8=?&Hb+p^>1v5Ga=o)E~&>SkkgTWuxq^$m;B zF6q(}X1hDw>^`NpyW8FF%hK)(5HyU)KClc+>|U^pP`m=B28vffc7ftu>C#(fyZhbj zzNfeQzPsIn((dOFG(d3xECUpufMtZ@D=;-s90J(|il3xQhs}1sbF=%i-tI5%cC93_ zDgOyU0~CLNrG=u6$M)Ds+IT%6yTp5xwA&nlM&&K_%3HZBKS3&Q2SGzn$GF)&QE&Go zce|%ZyUA|KJL;8t-IaHd$~!^O5LB9*-P81TySm%Wl6EuPl=sjp@9D05gj7B}QZVA0 zFc&;Sz(c^&W{+(T0?RNgT%ZSSEEWHM_CIq{6lrfn~^T+p`=@%?@-O$Sy1LtHQJ z5HyU)-C!A}`CVWcp|}@J4HO$ec7bB6bZLv(?)`3dx9RO}celG!+T8&`0~G%OOA7^U z#!u?)?sB)gSK58XP5Es3PD3qFT2^@uebZAyWJ0@-FMxTf2ddfk-PHr zWO3Q#PmV~XhO<2c*GNu6!xqmS@M-<9X|G~ z!}fFnGdkgeelW4+^^{I$LQ2X12&Xf^GdSH1EQ8Zs!OAb0srR@Gm~IiBD*2j-dVy(* zXn>5UAEZnXoeiGB?K8nLx_t(iZf^IM{1~@^c9HaLBIHcIjR!Brw>UP=W2O2iRQD)2A>>TJ zECA2o*?h1Jp3QZ&yh2)D?qc~`v-+j3>Q_nix4Wpn)vW$zsa}ukO_Hy}b+a^ouZ#Kh z;2CgT2bKZXyQO8lXLm_{jAypzJ}^zQ@jIs@7bf0ALE(rc?L`qW-m*pUx1Vevwh$hJliWR>pgo`@?$&$ zW^YUL`(4bx4xRzCSHaSHMpu0AfN2W+V`=#V7t8ON)x-O*q>e9KbbJP$!TV3m>TS;< zFiqb7AT59AV)+}hdU*eb)bShS3?BYsQeoRafyFNYVn){X{141%=kfgaPmq-)i+=vw z@?>%8*y3cPOU=O24!Lc|f#r5pVoScpL=&PlCQxd6-*5tX&}4cF9JFI^r3L4#j~(ykuLb0uHn*90&%eoX|~#jh#SuW|?)pezN;;BpCAZcr9WzQ*NB zFf}eu1=+>rM(J`L1Py-GO1pX}t0iCK*9F0A&y?gUgqLuL9Y{R!Ufb8PeUDB^RA!vZ|cCZXC z-wKu+ls8Mh#^p6&YFxe>WEYq3lP+(9V2oe16GW?{9ZEzmhtZVVKCh=-X{4>;l;(o|j}i&qL7Q z^mAYto!$eco72xozQ*a7!PGeY3dk-_zbl=73xbA0*bkOA9=gPQPjB~qce@9q-H+Xr zf2LRdxx4c3rSfkeXb9?%o87~DyFa+w{axDq#ZCEt^~(QnSAJp#abPkNRM zIc0f>$fY6R89W;VmLZpNq-DKl*^;mGY_#<3T%Gl1?Ad35*?PWNyX_eRre=v83$lVi z^etJjbg9T}ccPo!3-xwO-0fCLyHg=(7>Frg83v*PEW@O>J=I`ppr`@a1&W!{rAD*e zdN;eX^mb>v+g&K_UI{@16!X9`Krsg_w~h4*$&blN+p`Ev4OELkc7f^!>GE|DH2Ael z+SSjMYb0Oe*NtFm{JIHb7r)j@zwUyd0m@Zi8C<>tEH@}`lYEWK>%i2wd=JPjE|5yE?g3UzIN5B8%LL2t zxiubK&|gx4U23eGP&JC|&`}0L4pS8KHO+Obrxof$Rds z$I_(_%y!>%v-^qO?x*f{zmayof}jD4FTv76K@T*()!Y5f-R>{a?vHNDf7L7h&0V?2 zE3P#DhM*y+Ki%xcd9{NW53d$gjKSHV> z?xH>yJVRhZ%$5haS{^Gc7rIzJ*Q~z4ReiBkU*w{GB6xQm}ydB+cUs21>^`Np zyW8FFK52K4oAT%N%3p9-eq4&U!Z;=+B9$Wct+wD90&WeKb`)*9C0K5cj1nYYc{DQ= zk3lE_jt4V3;l)>$PmxY1LrTg22&WUlGkA8Aw5)$yhM>GWtwnMPw2cm~KvO3QlBMo4~)XBd() zX}-k8d@*|ERS5u#4qw zX7%v?S*c^Ui;i938NAHEaM^FR{<>K^zUu>Kblmt(^ZOtxfkuCT{<(DNQ?uQV-Ryp$ zxBI2LUCSq~Y5#|WplY?l}`5M25f~oN<7i1T|MoYiWg`mN&0%=$8SH9$H{2BwM#;>s;yZCjH z^s5?zh9RB~mciwzV7U$P6v@}PTnDDc<$91^T)teodmPx;sLeK!^60i&|F9OSWWq1{sZa7~l`I>l^gQ6Ku*Ienw#Yn)yMrpD>jAiFrdQ96wmV44PD9a!3U=sI_k-tK01yIZB*EpE!U>6LGH zSH4p!-vL2GX8p&_?vr}EyWH*Wm3E(TQ~sP@`962$pGoDPL<&Yc5&H-{L%<(^r5#1v zeh)03cuHc?x0TrE9N$XIhg>WlG^_u@RsHW${Vy)+e*(`C*bipQ-@97&_{CM^-!7K_ zG^_u^RedX|KEZEvzByQiQHcl3Fe3*Vg={U39W8LhYq_^AN-EOM1 zn*u?@ICccf07VC|j8LS3sevLLWEUt-mo9ZR+wJ0JH$!i?ySv?Uq}?+iXn^7junbW2 z2Fq=e=qdRzbJ_Ov15*Q4e~?|E8ZKQP3PFQkgQZ>l6~sWv*Z7qOrpB*)kX`&bPx>_; zf(9tZf@N@dG+1s>j*@(h%SB*nTs|LU7ni35z;bG#kDkCkm~+kUJwKGUpetSc=qtenkW z66|b9{IwvDO19$bB5Wz z2-ZKL@O-3$~{C9hBV{ljDMow3Q8`)sQC^%bO#ax8%{vxwI z4MmjUl)2SKq^NEhd|5!RTB6suHrn=dkViJC{>8EP>$Hi38#9>}>fH#j$dvWdQ!DqDhe>K?_!U$bMvQgKEoS;ZG3rj`mYR#lPSn!TUtu-xiamS$6 ziYe`VQ zLn~E>;%Vjd5OG*cVPs8xC2bPc zg639m1^(1TycKMVckXwE49$ZKMPWd%5K=u9sqSGZ6^9m{o?yUiuigA z!2;?|yHbDZemU>1nm>VepRaVELsF3-UO}Wt5E1c0rPGyKiE9*zB}`&^<>YDwQoN3o z$l4jcLg~C*-}zc&=aow58%PQ}k?lZv9NSRtP$X_8i2*cu8{vL zt9YlVti6|YqAlV+)c6*0KWeQkqCJ2b-y*i4#L-{G z-1Y24O)Hj`t&iqx3lyNyyCX0kb2a;&~1= zVdiP-5@n{5nR!Ymi!t-0;ONY}3Z@A8B@!G}K6wP&h2-$Rz{oku_~WxzqUDduRaBnK zJhwfs5v#70ID9<`j^h*Sv9;V3fJ3bXyLfvNHF7`BvkSFmbjjd(8Z{Ab2z5)vln47T zk!uy>95&mtgBUe+m6MAZ*KvTjw&!u;$?4^+b++dTBFA1mV5DCFM_}_DNnz`hi=buU zDsB%^bIXvDe7aaxBOAOooSt!>cTi)A?0MIzQ6j%e{i++Qm_l``y-bYyhLXAlu!L52 zA^jq8*vQW(TgY@Ph0=dN(JLy;r_r2QaiKT6t9lJ>Kt{UT|v);i&zjT-mfBWZDx7B6efB)7SwwUD#~Njpl?TFP20$!#rZZ6vL&q#Z43 z$4J_-lGaYvj+5NuCG7-BJ5kb3lC<`cmMCdSl9nuKCrerfNjpW-I!c;X(o!VNCux33 zOO>=VSxcAPPLg)2q;;0GE|PYdtaX*#fTVSkw9_RmL(;lSTBf9B$yyJGOVjFeWQR4d zoEBU4j&m`4KyrYX*=1#Q<@ItB<4)4HKOsiGx|9WIy|6zbden@w?GK2mOnEjr-y>q7 z*eUQ=n9`iZ@GD|8;Qk{#FWH^%0C>%2X547h_&zuWwN|ti#*Iad?St{-P-{oelH$js z#^!CaNvN@T+pH8dmif)fM6G!_YHZ#%tB|zGk~T%sDkW{Ipf#H&YR#uhZk0nLeEXqp zRg{-BG}g&&k^WeVeKs*-w*%WglNdVC&mcw&xV@R4*rDi2bUv`7OW3ub++@YdKZ-;~ z)|Ho8b7=|0=5A%!o)JXFny=t*dvb}Ght1fzGN8XJ(`b8!61kApUcsQT^$a3%PGj9* zT4VY4A+IRF9!YF|b2FnnY6-SIdBiQKEsfAPkagh?MIv^nLShUqshl1W!?{EqQ9c>Z z^)wdpiOZpJvQl0G4QFQ9I=M*>Au3C7uAL>g?HNYo5sg)& zYYL}TsyErTr+`=rX6gjMqr_%ynydd|vuZ>K+HK=Jvr*%F<|R&zlCO>w>h{c9Vrciw zYT~dY3-7V)-ht@hJu^I8OHt!{<~6ACUFTX^TZS6nGnY%+ zb&__yq^*#&8zk*UNxMnXR!Z8mCos#yXr0tTlrzCB+q&+Qb&q(gGlD0?E_Db4wlD1FQ zo|oJgB<)2>dr8t>mb6zS?Nv#8P1as_xHPR6pl;kV=Mz)6e9t9@X3q=~J!;0;_T@y4 z-ZL*HqHfPzObpsH!}F5unV*2p_spMA<9p`MsPR4X7u5Kk`73IC&-@KFzGr&w5qoAF zYJAU(7q#ZiP~&@Mb4hC#iSQpKn`6Dr6_RPaXjo33)3*Qh|zh@p|cB1#p&xvZ@Ge0GE%%1rLQDgVa zuZXPQGruF2vS)^UrUw+7J+mhgjXxyl?Ia(iTo&raDczlzQQ5`rWltwY?A?EW$hp-K ze`A!ck7*z6<#bUp1v_YeP`OhBP@{Q8PMt%t9P`*~^RtMlbE+>fVx8(kWP?-LPM1ih zhJ(tT8iAT{DwkxVoU*JSzhM|cOr2AMh~Z2S`IIDwh+3Cgc=EtwSB~}c#61H~zWw;) z#QC7olkagT#bbssq{ZY=Au)9holA^phYEu1e0Iol%dAfK2N!*#Z@>p8n^RN z$85}09=7mjFz0bb_ZY?mV!$xFzIO1TY?OMUIIWMguW4 z0V2Fv>%|CNf?7L^o&;Ws8ov&`3^jiBdAY1zA!|WdnD~RCWePV=P^8tnuuWwNt_$z*@Hk1EVt9<0x)>fMMobKkI8yNDMX!;_pG9m7*Z*2M4v=sbp3P!loi zBWY6%dx@!w;aOtD#PGC3)y41<@nU0mk&~lic$vtW7~TP$$M6AaB8Im}+7!cnV(Mae zoft7Oyy{SOF}z2-*cjgBK9m7{d*2M5L==?(CSJe16_8V$^8~YtKzK#7?*8Y&S|H;~)vi6s({Vi+O z2BF24HIJ;t$y&UuHIudGverV@5@hWtS!*e4tz@mWQ=@I{2Y6!~mG6nE8k9e`cox{n|!DSOUHn{#=S`*xGaCmSdQ4_)ClDsLn zA;i=LH;5Q9!R0tqU2yrtiw!Q1lcR$xAaZPQBe=9CxC!9!;4VN-1UHW4O~H*JrY^Wb zV#EY@u0z!YcOLO#gPX|7(ZQWh8wdrlTf;D<^qVaHYi51y@3hnBa;X zsxG)n;>89xg_EO$n?~f=;HGkEO>m9i@Ze^nCW5Occ~fu~5mOgj4KZSZt8%Ei;4UU! zY;ZF;IXbvmM2-z^CYRO(HxC>h+(OhuaC1oB6x2t(ZbVH4cP+`Af?G;VU2sc?5fj`ZhpG$idg8?fcO5532X_OJ zV}o14r8U9b2@b!sy9YH2F3z*wsnI3T?bOp0=B>okg?TeEV#2)1q3Xh1L%f389ub?B z?YWzidq$C0b8__U_9{+}24x+QV?kNVrF%u`zKfG1vBJ&ygP`-Pnyskui{Ndj@r&T? zsPWGfA4ZKXhY7v=Q8%KunV35CHWDKSy$udkhu%ZP(_c{T1d9*wv#9X_-s9BB#mA|u zX@DOirq0Dji4o)CBMw#P;%?%_4)D{Q96i9hI5~QNpXB7|0e*(au><@RmyQ|9S3u_z z`c2e0ByTx2g5)LYXM*GfV(K8-M~oOq_BvD@BySK;frNci;WbW-j{H?lj*fgkkz*r& zol8eXPT!D39)AoTkNykPc=TU7HH!X2>T8PrePZgOf0r0B(ZB6bbkC-w<8zln3c5AvJn)xDSa#tl8rOkv-!rEl3%7BvGZ^wS+eB@Xqd4?(xH z50{#^wpy}p`C3-1>Jv`rT{*1pxUB4)6)(JYb%po5Y!804FsN_Q!PTKJZoRLltg&=j zam}QP#`@BdhMKyVc4NmdEQ@{1CNc+zBck1`P`DurJzxjXgy`B1_@8Q&+ ze4A2#^;2cK-sfMC`jvlM>ev1~sfYdFq|Q%Wnz}0W_tXuk z52S5LeK&P)>dv%RQm;ap>ba8)vedG{=W6$)<3rndgplO0fZ~PS9uqD7XgfA-sOPh2JemD zmEK#ucY0TOS9|aBuJNw*uJf+=Y7HZqW5L*Yu?wr`@L^_-}8Rx{mA=?_fzj@-Y>jgdJlW&rz}WWoN{%_vXtvn zHl#e1@=nSpDc`63mhwl+-ziu67Wx+ZmiVsrE%jaFyViG;Z>{eh-+JFB-)7(az6UT& z5BauYkRJ6t=G)cz2tiZ1Nge{4d0u-w=tOS z`9AV}jKMvCp*-mO%6G{3weK6>x4!Ru-}?^xe(?S1`w7GRtM3orpT56+^ZZw0=ob1H z`>*z2<6q`q?!Uo*lYgcE7XR)3RsOsDYy4~d_xRWQH~a7NZ}D&SZ}V^WKjIJhpZCA! zf8D>||Caw9|HuAM{h#^2@E`Pl<^S6Mt^ct9H-9j79)^5D>S7H0^3>~7Z%Vy6_14te zQ}09)tVvyuG}x5-KD^_A4uQ}?I7jU@RX^~2PU zQ$J1pEENfvdMNdq)bCS&O8q(YS0vIOssBs;J9SRl{ImsW3y~^|)2>dtCT$s#Wd+h^ zW!f!iw;^fnOk0h#S%Z{Wm$p9b-n30=_oY36^x2xW9Vrw-a_vAG?L>0zPJ1S857KF0 z+6!qfrM;5&8WQczw71jVMS8uD)cObsb^uBDC6eul^quLu(w|DduG67TUw8Vk(@&jl zJoTniUp;m6X#14H+9VHf3zixG&>@j0ZCw%Gj2%J>%hwM=}zvBds(fvzns%pDcmhEbcxBvbdX>0YTFC=!$$XFI<2OY|cn(5uD$}CzWIHeoD^;z05 zqZ|Z$FA%-#%c&aiuUl#5^wf&Uj7B}lykr*)(@vx*7JQ8AylQDGXTUr+izQsPcXs6sTC-zskZ_XE3LpdE6WPhmrchH0L!gF z!DJi_I3{IUfk8tdlRw%D3@OAh%L)vxY$%vCb#P-f6!7}Ml7*nHFXVrYwM5*4c4)PJ0wl&VVA7M;AA3g zj_VNI)o3k3g44hDW7}X=Yv0A9bFdjcfJS*5J9p)@1WpS!u(I8<_QZI@>DEy#N0nf8TG z?HzJ*ySSnwin*#}`t+Jo=2d0-Z6B4M_2qfL9(aA))k!O7wA(eY=^3A2(lBMv%!axW zj^e@|`yafys)7?=$cLs1w~6 zAvpy@hGdI=WiI_rRr}@T4<1@Dcu+P6Bx`z|*a*)!cd%@5l!-fnShRh0k7BxkNDDs(uvWH>{4j#zl`<>xfh?s=!e#DPBo4zDO zUmpx9ugFTATxTcm~i-4bp#Wlkpa0IPi9AN9V_Guo)mO&?a~goTjym=}6(=9=Gt#MJGXm!@EcS@(sMElq^uTFEqSG-> z493C8j;c-SdJA=}?S)foWC63ux{}Qk@TX(}PISWcMz>q3TS`7o7pJLt)4GG*wzJwz zMTa`#5B6BW&NjpAPMvWFpTvjW={G#0pK6hM z;;#o;!M^9>^b~rY9MQ8c{`}mGikO+7gKl?Hx0>^CItqyso{7mFF%#8psy*tsiaP#P zgwrPx9n;bALbanh6x4AwbzFJ@PX9sDg)MeR$G-SWI5R4uM}m6YMZI>{;nV@QDdDN# z-3vdJUeRu@p?-x8IQ@ct;h9hU+TkVPnE5fd41>M9so(gyIK6SUI`Kb1zYc0YxsFai zueH>xdLB-T&yjPfU5efI)D%lvis-S9di0);(^35_D~%@#Rtd7xgV~93Z!8SmL)~(( z#Ayw>Ig^$Q4Ojc9U{Fx_b54k70Zy0pS7+WK7%Npfs$)hSH&Dm>7UJ|kw%V};EMBIf zQLLIAiJtdT&#M;WbYOtG3jP-+SFxU@F##5$-$v>;W+_hJ4pb*B;j$&7pXw|1+(bRw z;JHNXYK z!mAlMdH}B%olzg1&XdsVe(E)F9Zt7l%7)YOU7y|dH>H;fC-r-P`n`7#PK~3~b%pxb ze&iT8RxcwfN2e{+Y3F*JzC)*DDY7{GH}trk-qAI*vY36~5{K;=%j2=g{S;IdJciSQ zSQrxeL*BO9t|Z~SnrPv*B>X1{zXjpuj_?{1uB@jYCsT*Ho;b9vU^8f6M;(rR9H%U- z9>+Ny?om4Q>LEKMpu;`X;eP5cLFw=?bzpD1$}2A^!_Du+ay-FOy=#fS>#1-2lQUgul*EGyU(|*Q-=}^aRix7P}t;vr|lb3)#y6>irVDIy`<~J zr*W#hz_QvgKkT=dh7S!IqP*Ei8b&^Y(?`&7EZ6V}({Kj8{$vzhM^iSYc63cPz2v8= zyc(Zkdg2l&n3Dj+ChGp;D>${CgzTp79;Dn&p{77UQ<2 z+qZT0TmpxiwPmlnsV{FR#v_s9lG0LoNy6L~am;iwRD4bjZ-{5HEBbSLXM*68yGRMLB~^I4RvgdIb;z^()8O*_6gdCQG_fjp#!=r1Ou^A2F9oJ2iY;hin)+XHS1Z!mP{M?a+#iIrdDej(S1>eE4h>t(wJxAlWykqi9 z>x=Oi94fwrF8pg{_0!OlXZHk+Gv;t)Z$uD>I|C zSC5(K{hKhFYhoo>6T<#yW-9)-$78Jdh2wJyMh#-Yjm*K8(#{F)SOjwBc$h0IZ=hE^ zSiu>>RJxvgYy0BLnn{f`agO6LC0G|Irh6-g?(0@m$wNz?PLsT^fN|{O=R^^vfkG29?%dY~V=f)kx?BYj{{&AH{l0tY4J6sr?FS zbMYOA{{6c5>nD@LnIHZ8pV9ve`T=BoeDEWzEI}lQ7fVY#^nMf8J2bbuqPd$DpN36kojP(yu*zA%pM&9*|w#zi?#ss2n!jg(I!t_fXDqc?^V$CYCnhiw9Nc zQC93&X(OzR3R~&kQ?WvMGKLZYpB2EXyF`)QBD%4#M|6cS0r`tLcuXGCi7?-ow9*>!iB{u$}307fYLtS}E6@4IpuT*5n zOgILaa1SDHWjzsqi+EmAT#q+@l+i~u$Wk6#E9*aQ%#%+?&yqTV+%GyD6GMyNnr`9C z9Q2+xKEmyhDqmq`iC^!xD(cG1rB4qbB>d3}491W!7CjV1o5S7P+Yipo8$>=r8vo*3 zOtA8EoL#1vFNV0_;HDA~<-IJ*`U&|tBd5%&$5Lro*tMbQ3mO}~=tJEWF+88^$no8A zHx!kP{EkY7MTz^e*TMv%E0ENF(eLPFQ;A(#MPJjX^JxWKqxnQ{@ud0mT^Na>x#|*| zfe8B3=+HAd^jRkIXkxfWrrIG9+G?CNtzcwvZhpQMyamI?lH3DrK|mySlAP%!xNfk5 z`voeEZp^Rqu+A6P*OwQUmZH;V!j-+@7TGw_X$nmSr}is>V5bUKN5im#-p zO;;r}uf>I=Smj=TlQ&_tXl3OyHKn!n^p;1VBT*P$Q8<%68wD72Neu0~1m{` zMT>SdeZ`M2sq=yT8yLC-D=!SZntZL`M=4E5_NGZI_y;=RUn?s+mKc8+PgM=6C6k2` z>n&JpWu2H$v#Vsr%wo3G9^`}LvFJ91Ei>VF@|xC|UOm(`hF;oBYYe@$m)4kqa7f+N z3yZceKBGMYg0?FB58*k=J~>$3CwoG=4;u-(^O#gpS67L<9xK?9!<}I5lL<4bJFX1m za*&UXd)W0$A2NfOE!(=Kz16R{fIr1AM0%7=E@#0-KJDlC<<7%?9wOdTiW@XuryCSz zj>@D(V^Y|OEcMzf1-$2#(LoZ((HVi!Id3AZf(C0+asng0z%EZ!y z)t4)$r5FDatlThy>UNP}#ZSQpNtM+zN~Twq71x&Fn?U8bAuF!N-3($E*WU}E=R+^@ z?ytxlAh)Ut4`;$Vz{BjCWkGv!Q-o;|Y{q?PWqlZ+Rg>+s9r!rJAJU|d6Ja=mX#4pX z#uKdZ;V3fIJU9uwnlLXrM`d;c;CtCL?cR&#X$k|RS`}9lI{;mS0y%}n`2_<9(E}v5 zB(nWK9-0o0mlth_?Rk+IU+TyS)(xbnVC3lHf)Q45Ergk#IG8wp^yvIT-1O!2>M@>e zm4kAy8~u$?nMgBSAL2n{^kVB^6W+!Nn*+e6mGw+lc_T#&Ui|rydywAR`OAEyIIUDyM)JqC{vpalA@h05dO_8%DxRwHMjSohmR68H%NXowEP8s8 z+7FkHuvk!0fyZ6{VDp$D_PbffbDQHvhaVI;6Pyx;8IA8ldw69nt#Wz76I(~T?@UP6 z;*F4aIwAzuYiKXAi(_1UIPqn0;RI`Rcou z>q&VZ*am0~3-i>ebrehtjeH!)Z<4BnsR1tB`0mDw6TGEdTwBuR$u|tT(=h>YYfc#( ze{|GS3fl1((py;(Cw?kuJZ1oHMae9h1iM!xk@9vtmF*x`815 zY>VB-!kf9JXq07I+Q}w8xU4BRKW+)3WJ^7HAdW8GA;f~!^ z+>ZfoaG0lVOU(e;XSnR89K?Y170c!U4ejiS11sxG>Z@2DtQ3-u(nc?y-WHcmV%%fJ zaI8EN7b(a%=jq3df_{U6o~>RT$!;q}w=>+?N6Uv5Y!mo``xu|i?z1BvU|)@)KFo%C zu^dObbe2Qd8o=BtXEC2McM3OdFfmrJuy{%?6w16YBA7v3i|K8 z_4J3hX zjOh4_fqrV#{YD*A1ei!{e!pI~e@F}BD&V!uDe2mYeVCL`wx$>DClA-dF?7(cUk z`0&&GW%*SnrJXR=2|b&fk&vs)n}W06$Qc&qIO_I@PPdPtB%r$tj><=ZvE0OXfjvU0 zr@u7Eo>A6{9#@YMdNAPh(e5XLv&hKtcIS_Z*z7JB^1tyr0~z80!T8z4xOjk=8XWe| zMUOfYqkk3x=f>HzxJK*;R4x@L4U@Z${ zgm15))0e`+QX^-Fe8j<>x=(bO+>y{uqp6Z)L6G&X(3T7CZCoC87L^uyQAH-xjQm zycfUl^u}>I4sy+lBO6CL4sw}7qwxFUXosUGj(#{Ol(TUV zY!q@Pj?-{-!$DA_;h?b3z|jK-g-dXE#}UAhilYw>f)anuCEkyN;PT-}!GT{r)AvpY zjw3mOH+v%b1h3=m;QdZ{Wh7tK9efUV->@gkOHSqOYn}4@qf#0FB}cC8D9#t zI{cjl_}8h9{su#Qu#Xc*!4hsyluK|MO#JfUyqw|qZz_u&JwuKe$@*m_uoMq2bM!pm zl)pK6+u4=@Dh_ zVjiC;MIB`@1MdDp_p7g2uf z_;sqI=SRo>kB(fOL!Y>W<0Q&$*FQj8M=%FJ#G&#MhkvD0+8Zup^p#Hkl$PAD?9P#8 znTNMqJN?=_JmpHp^m^jzlnV=8w# z@*5pHe>>~BD3hJ|L|N{%MOo$KLAH~}`A%8v&<8kWbEiyo%85=sh_XC^<1x|63t2k( zFwrTWNZ@#iGT@B+&J7nbJli?t9;bYwHP`!LGG2p^as1Yi|J1?fT?d~7j$ao!@ioKu zTS(q1vGvkpQM|y)o{pmoM+uHv99|rCIJ!GWSBFNjlW~;ez+a8C>v52rn>@(~d6Fx| zK{iyK(K6)AKgm#^Xc^K?{!p2PBNGSNB)`=dDXv}$k91Ky(R5W`AC0_9^E>=Jlml^O z;~0lyFpgXt!jEVTS&Hqq%2vP7$nqN(#kl_eV$I7Hua)ag)Z z7o%N*qY?+@V>F-I~Q9nAS;ShbRoHmt&mCB=d z$i9#j{*oNkiATPwGQ^t_MI)WjF$ta2mu%A*sd~syfjePEb3fg>OQhY!e1EqWXwD zECHSR2zjEbZGj*8r_!lT{*fP4|0h1p(P$a!FYpxh)mQ{gH@{V1NC)XI!9n=Yq4Grx zDve~tT%eNjK;^4`h!}-G)Fzu^UI_YZ16||*?RzvQg*;(hqM@lW(K({>)ErUiq?dRq zP2^29P0bILM>=NVAWSG$VT?Ihq39>*DoutVsvq zEp+;wdLha|IP#n_2jyrSwBJ#k4(c-!hmakE`am4CAEw~2aELJ$IU&|F@~WS83cPMdrn`Uo6kkNOP2LG}er_)R>LA^s2?)ORe7Y#by*eMlF{ z`EdvvR8pU89HX3rd>~nB|64x^8}dIJ2lb;m^_`A`a;5}_7!wtTuAqByl;R+)&cmVh zJCZ(=(3k9$;Lz!$xk2MZc}jDbY?2)LQ;vgp!oE75FLx>mTg?+rH6u zsUMAp&Sno6n@7@*Fj3b)8Z-4;kMfD|7W=yJMa1-Py-c2C()neqxT!qEBq9` z2pYv7O{4i%fwvU{`siV`vp*Ki7LHi0B>DCpNY`h z2Jo(iu3o(4@H{Z-#RFDc^RC`n)}&VufPH@7(pn~-F4|?hO)n;3{ONU!PwyyT?b=e- zrq>m)c0HG;Hy1GVWwm6D-eJI+^{h#6Ghoe9)};3uP-i%YFY&gp=oJU#c;7lS=v4;@ zh_no0)wuHlsMC)P2uVVWvO0rMaoTEKWW3-}Thud^dX`e}q11aS^Tp`Hyhu#|(HLYvUtW8z1r7_-GajhR4P;dK;fl;1x6;8z1f3_!!s5 z$HF!~R<-dFERxfM3uOps3lTpa$@u`ih{aji4qXsPTz`v5A4vGNK%?5G{`=ks=x&jwlQ6x3KtIi8=#JRb;U%yVis$@6oe0T2vj4x>VCcwP?AOA`YniGkw8!1>bo zQQ)SZqYg)D*!fTiycEMx%)MvBaX$C{pNFG@1%=ONc~I1BQcxw(fLJE5SWuxhf~rDL z(-H%fiGj&7qDf#OT4gw2hGQ}hNEwc5=6NZUvEiU*lRU431~^>F97cuO z@O&mbpOF}7NDR~^25P1A_ypTZ&sB$GM%ejK1H2T&QOCV!!%@q<|L5VD#e%{Mws}z0 zY*JA8H5mmplf{AxwGmVhL0z60xHK^^TShboEJUje$K~OO)Zw_42gHVBHV;S{jycTp zxlqQ2gPKk9{2FM0!}xI|97cuO@O%+GzbY|sWny5S^!!?|BIos0Vb4QX!bOY)o7nTh zuBWe})oG5`3Z9IWAPZ}fJ!Zjx#ykkhnZB6CvJC23EYxgLEVn`fLRi5J5267wdk%24?2cizak|T>_8H?j~XlHRyvq^DmfCjj~nz@e(wGqck#BpO{U`1l! zIvEN+L5`Z-H-uC zAWEYCqbi-np^iscPxKnO3g5Ky5uV%dyXHYNr($Uydk9vR5S za3JcKY&fzw?qhMh3GFNnYBnj3PoV+szsuZ5h1!T?JL1@y7 zZ&9%Io!Y?YNnrFuVqk{^=oc>cD=&US5ed)}Jhp|_GH?2B1)$#{nf_E1K)b^LscGWq zU_06l4L<)RUAy)8`~hC*sW3jf7(V|4mEl9pCgDSG#s)t4$vVe}+Q8=};PXOaU|(Wj zuY~9*F4~e8tx!Zl^a4Vns}ahfR~3j_Lo)r9#K_g{)i6XMrz6XueH>?o(OwNkZAjUx zdW_nF7kVX((aQ{@qd{dDQL{-HoeT}Y=mZojho}vV-T_8$B?k6OfI4uwQ+Ux4MI=CP z@z_`ny{`b|g=G4BQ2@Ok21v~zM+d`azXqQa()GR`A0K$3_rmzR%kc4o%J89Plkn*d z4Zx=}3Wg80fzOw~=kvtCfyBTk5~55ln#GGAC?X;H93hDuI;23<6O!p)B}T5shr$qr zoQ^Dq4se_qMxSUf>P5;9=`rdJUg)bZMh6*2eL!UxQL{-H8c9PuL@F(98Xc4Fk zF={pmu?lE_q6<+l#HbC#5|Rc7nkR{;E0ej<6kb%Kh=i+o5(SAh8UDQ23p4ht#(O) zVi-_G%Sii4dc-aV zFLYuUu@e|#SAfb8qh^y3TLKM0jD9e}5TiB_>j1=(C0ti?p{2aI21O)X$x42C6}Ya2 zWO~OaxV&Mw)ckUE{Cl*Pk#esdt>xf_I)>3Yg`q{il3{33vq@;(2@ODNB?^WXwSiV= zpw%fUkR}0J#pPD>;w}`CfOS&xtE&Ro8c3#}mK3=Gb`1j-ayqj7N;}g0x|_6j)g!hR zywGW3#JVuV)`7|pqh^y3djJ}M*u5wiV$=p=nLsQbCUuEGNJ=uAzJ0JVPQBTbu`cA0nuoN3V1-u zqqeck^Ut7+c}~qHdHw@5z~O_;VN|FM&o6}M7bFFWk^&Qx0^_CgKY|-M92bP04;8^n z+EQpZCUWoDQ{3^~d-fDJb~v)|8HbHeN#rLTB`maGV2XuC%_fBwk6-;DqW_7|sEyF3 zAhe34Kv_~?l8mbvScq8}l!|a%>Y$YIu-KqX;$bO+Qpr4T4rR=9YBtI9fU5~vMv|^s+*0ESlfO-}SHJcQR z7a9;kA`1Z(Y9p455ldrIpk4-&0(xX1jp0DlA*esHIA*dqe9+F~pk|Ze=mrgNKb^Uc z3bheO5OG|d6u2}gFk6OlI#`j}ba^rpU#s11Cc06sgC0{@Zt+{)!{*XWOuU(}5O+8{yffw2zM(hoS z*lti6V$^IBVlP7j5PJ>UDQ23l#!g9HBL zKuU6;V{)KFav(WbJdI67(fm0tS8{rrWPUH1 zPQYX;z+@=EbW?!o8V06IxO%E9M(mzhqSGIyL%m|q;gm2sJsCRL5N7C5vq|WTga)89 z7zIOz+CV28==4htoShsvGdXZZa-g?_hF;DA@Hj4=3739hT+}IZHiw0hCUhppf|4e5 zhEng%fuRg?zGXOo#We~>SX|U>Qe2hLfVeJX;h;io#8rs6CME~QCkMtR2S&@FrhgH0Zn^dkeNHT`<%UZwf#Q-mv3IqTF-i(^*rzAy`H`HKKq=zkCM#I8OaRgWah&&CqrVOWR}AN za#+kcphGf}8H;4bjL+2{$koTmB-TOYOk%v9gj!k;xaKe}BZoU6q&|WXq{E{n0p$J+G!XMD@8RWBas=L z$VYI@iI5m5k#FDu_;)aVbVx=b3z5kDTzy`yJ~vmNldI2?xqJ%)?de?Yzv|`8d^;Uu z9@waf%rH851?T$8s7Ry z1|KhgkEOZ#l3e}STz#=5ACDIrkkjNQ~ zA03jB$W|n>C0BnxSKlnNI0q{21L4$Eh)capeqnFQ;+qevqeOF z8f9NuBc$h;MBnED{6!M?*)F{e|m4%w?l5%O1$Jzo#}7mfGLBxReu#)~5nJU?*yr6X{?z_Su;l zd(p>z0p4Y-Ta?4d*@0Y;llg_~;m{d>=gP08?PrcgV3au`F%U-+-~rU!gNB!rWN=g^ zuT-y;r&q|+v-0$Co^?lLqOhJMnupLhX{wYbb|s=IC(ov7GAy-fdCn`ToILwZiaC*K zssJarlfoNwRvzC;;dhZ?jHgpJg&gPPxl%S2I-^>iq^xQlW%@8inKBXsQT7Bpz|rGq zm@<+<*|DIkW}aR{k~LS@Jt>-bXq;r#6nXOJ1jj36Jq1gxcAm4QjMRmJJC29y8v0ybpaiLZ575oho#mg z&w0t))@IBwC-M{NtfsK8C7NT=I2r4XtgH&_r7(6JEVZ6_&TH>pHe-f4kt^(4K|52{O`+^67s_gr z<6iER9S@z+)28eOrmPM|nKBXsQI>=UP?nE|DI*z_4FY8Y^7Q_BdSA(xCQMHj%_(S{ zd<_t(a)sTZ@Rfq4c5@nEx7d8C6=wQiy80`0^>v}EF8RI1ovu@%Gj6u&8q9Rn!zj~5 zVj#MT;Q@4=j)v(X8FY;RUBmM9@;rS=o_?oftg)~@M>Hj9oQw@aR#t_LRv0@MmfEPa zU4OLAm|;%j3M&`1Gi5^*%I^yQj+MTi{&>5p_%0@C}O)<)pkr;@wi{Js2m7-zF zNCsu&LD>U&`nWv(UddOPFuhnb?a(;+dO)Pg6*fuX>k?RM6Vv#bWb>s~nCXM*8mG{8 zuM1u6$?qh0x;j8-Otk5mz;t!QDAPq^AiA!F2hi084bw$3=$Z+-rswI8<>`;+=?_cB zt`pYXMbiU~ld%` zZiLR5ZBsUjDeH|_WW#S(vBK&(r5gzHS$$cZlXrG)}%2 zf&zT5GbS`Vsy(CdH3XL0;xxXVvH4Of%=E!@&Cipc4b6kK_1Td1MyQu*cuNHU~4oQW{YI7^$H4XWuE?Go^IsnFXZVQxH2U7P=~GM2^uZ;!L1Ap2(qHSs-U5p8t~+}Rp)=mG*?XJWTZB<&kHkRit%3)z zXP{yBNCtZ!gT1YJ`WDICYGJoVG_Rs@^0pQESXZ;@PpOjq3M2brsr{A4$bOplr=j+w;t($t+L96BDiyN2?=muu3eEZJaG5KOYq3<{y zjlTIEC-HeR&f-ROdl1hlTj~95uiE*vO4lPAXGdb7>;}OD9QEd;&>ky=AaEzeF(UAYr6Y<+R1j@>suNGM?BH^UhtCovH65%2)OcQ9adNCxs0 zke{5dC-e10z8;g{M?&jdmy>PqMp9XqguMjzy2R{3mvtdK$KNB>b z15$f{Q$vSjWVF^2+KI*$JwvbDBtniqEKL_s!KggONWBXN;W0 zK**ni2LPVOfYBit$j<}vl6<{!zTPNbKRaJGE-ZEcrk*}Yh zuQ!z`u7!a!#a2p+EtM2o*tr^Gcu}m%C|q$_!yR2$9(7Z(n(>*oXDrj zGC>1Za9g`CFRnfzXPxp<^qC+1Y=h3|m@hxa=)fFp$0&0|Vjzybg$GdcIT}7okPMEl z1V>%-^)8a2?}XiM(R`1_Nl;gFiRqyP-4ud;fTebI8bRG`g4842^uhdeapC7j^3~0q zpP!&JuD1EPiuu`tQRaulK>Qql2k`S78s>*&@Y5Uo^vc(7$k%&FivBB14~iy)AHs4{ z)C(zD7v=pFio&qe`sO<~!G1PHhB=XI=mwh?qlev>H54Id{oFaqg3jn`bJT}9%El;j zL}DP0YQh6Js)mL+A{iXr0*(gf>jNc0wS?WVqB#zYlc2#OAAYxYyFyTHSZcSW5p=sv zkXl2g53ZqsF8mx%zHWEtrw(++Z8kr*GCwC^l=&es5I-q+06$SQ%n!-nXEgX3nXeDe z*N5iocT1M)3hPrvQxA=krIE>UPs)!tqb*Jof=!|=8%EmBd^)bqnkr;@w^WXuLosEVmBN>!U0%a5O z^#}9y`z2pZglSXJG(+R$Yl29Lt7?kES94fulhgQ`V)La|mFa`4>OqCB`(5ZNCBIYL z>1qj`G1;c;A*SmBj51v$2BNDIJb&k zPR3>-E33kuR2b_5OKomGt`w9Cd(vjiFeh?_&9JF49#<%vW{=AXyPO<9=}uW!=#05G zWlu0=S74MWBQX$Vz2E_qU4w=xBN>!E3(6Mf>x=UB1(L5Dg=ufm^g-j~Yq3a)E9`lN zufDL(dVWtnRutf@83tZ^xM}D7or>j47#uA&Z=a{aWFv@h1c%*b)Ob>`2 zfkz9Vp@-`*T_l69;(}7WVS#>DfqrIzUcbP4H%Skm(Q*q!nKYq|s9}NqZt|=GQD1aX zd?xy<=>mCW)TocX^(+hD2Shh6AS|O0gp(pMP*U^=88{ltxu8Qbl4^#eniS~g7U<{5 zj3z>bY(+-RDWfKKM(RSID-xotjB`Xn%3~AGXXKOMjFFQV2>DES0ATs(8j^v$Es(b^ z&|4MgEerG(5gXl;WxS^=f?9;Kx~&&$z5pdT}Q=pmlheGw-`PrKoyNDP#e z`QVtRI2U9`GLq_uq}mtg?F#fVnbC8UQCoF6+S?ha%h66G#LH185>l3<6C+<@Atx~q z@-^@Pzy2*S%jVxXknfd}NWj&nhWWF&P1lIl^QUss@CBQtszDrBo19X;%f)aAHNB*e>c zjYvpYj-HHsGn_GU5(6RM0S^GYg#n{OGLYW{f zs=_c9i?sKM~jAsKl*fIP+(==T=r_sCS}p*GGVe4L$%aj&u__Z(R+4{|Oi z!ae6gVxU}-@PHIf;uO#!8M!=!TqYLi<7FZm#+`{wv=dR+Wc-okF`4r?8QwV$5(DLN z20Q@%sSF<-l99*b$YWZ8{z!p7Ri<*LFl`_jdc=+Mx^$XY75*CF%mVwS)!DGrW)wJg zi>sjH&3SKj@_)Ih$Dk<}zJ`5@BnJ) znLT{`kqnNW0!L34=ub$3N`+lZ(OiJWNzjubw=tpBQEj0@P%Bt!3(^Q$XcMHCiRpvS zXivECb0PU!=*~}T=!^w6Kl7QNHW+1oNDRc!mGA(5I-y~HNCrPIfu9ux`tkyOnWTuG zkpolZkvL9@Rv;zoz2GYfMfB7h?d1aJ?)HjJkzr2c8d@%RW{#G*aKsPRdBvS0dQgt> zvdz&-=BPVHnIjSdab!LW=SDbUj?9PQyaA40FVJ6=1Pz1%2=aUq&g&vKuAvPIK{sQb zwmyxZ4K_h)4VgZepI2S@;RoStaOZ~~gtOk}XC3n+AB00`7iZIU4Kp*hMkahwG0 z5V>&;?NSJ$$L46CrxCQvCP=Lz(+Bgj&4r)G$=5D-e(13{#^*LaJDDGPAP)0GVjzAN zzytW1gNFGb8T@ghM%As?%Nep2}1r{DaTwom_L^JAD3xq!YABojgY z*YDPMUHI`gKe;o;kH7iRX6y%M>^X}u5(6>zl3;9^#Tdz8>^Cs>tE9_(M$XH^mL7rQ zET>yG#>x-Vkqh&|IdghfAJ$J{*ipndeNR$$#2j(ziBnDz^Cp^H>Cuo>4lEGM2 zFjhHg-M#x<80`|x7igSxRgO|w;KNWHN!1m)zJ#TglSWr{n=ZA!Odp3|Utf{)>h5fP z4V{r=vsI1R`Ua!S7Kwq_`VAhy){khIEt0`jZLoE0RIe!s+b8UP7tJ4NoP-?@V_uf;(gTp)=~(j2+L6{f$v(jKn~URm2~@ zgRv0***!WWgRufImM`h5B#bJHrV1J-UHM9V#TB}$!cvQ+(G|DpQtQj~arkUiBj<5< zwsN2|Vm4b*W~(|znJp3nv2_YOfTRL6Twf%Etzxj%Fsh#w)z6IT^(Ad7XtmR$>P>Y! zcjGLx#`vbXNg&@;N8h@s?)%NG#++0=1mUDe43tzuctBF}SyCh;sb)y3NmM^Ks-Gh> zYD5_on;D6l>UKuzYMv_+qSZ9c5eX@`4bNxf#TIfB10ioIke|zdkpjs;-WJGPNA*@w zy=7EyA;Dh&t#dhA+u)5>KuL!@Ek{d%Uffg{==m;g=5l0w73LyNtu;dNqL3IUwJz|0 zjOdwBTxldDwT?)weN=B3)yrgFmqUe|m3z7E?Yz`QX(!U+MJW?$DT~sHk#~hNMowZN zrEQBXOn=|(#hqo=Ya*B@CfeL0uWaL>7r7$}!X z@PJ&#aSG^=j9dmHmz$z`Kbgow7EQq-Y{ivMzb2 zDim#kr8Xt%Jd&o`6dC43uA%XQXXfYu7mn!pUD{N4j^2jOm|}A@nK^m~qs$SBfjHU@ z58!AE8s>;(a5MuPJs#DkNrLE+T(J98G@qey67;ypjcaJOLeNfFYO~S^nr#!L){yCg z`I+Xz&*$U|PY`u`hq((nW0uX&Oy=hcj50qY2IA*uctGCYp<#YV20shI&-|!9PxAAN zu=`as^uR7BKl71~RX~dsetv_c_H^1Yw%F#!Feh>W%@ZUOLH_4?>z>a(^1j%evEQLH zp0*iV#EkucQD%(9K#WByFk^qi5i>?I7+VU)mPop?gi*F=Dxh)FwL~eWKcx;Q@@r&@f{pgRu=@Y@MX*6k(JSOt!H(`IWUvn8L;Mq(hg`oS;Q>W+rlA{lJejFsv&V){`r zJtwADjp>zR*4;9CM3r`IOxt0;Wok)Z4yzHfZxS9A6FV8b70f~3`np@y7=7iI{=mbi zjNx^}>Yl@WK=dF)HI9v?KOkC+*bn@w6{BPZ!X! zwDoN|j3Oj!y~jRH@Ih-U{vM52ww|CvS=k1h$Mf*Zd5{<=kJa#iJj8>h&>|~6Vz)F`muwhl-D6rMGaWvwbhFbjt^!tTVXqMR@WNhhFYIL^ox@t#%7|xl&sbP7 zVlV7<%tsX%Gan=d;^TOD03S!8VLnI(AAP|`@0i{zrr!|Ldq^_qQBL4WS=in-6Y9eD z5=8LA-k>aO55a`8u>ClZ6X2K=Au&)Q^Z+L$auVZ5hh!vj7ZSN6rr#FRZ;9!HWBS0D zev?dxAI@}lO#90`XfL8O;y=_6wLu$W#hso{q(-DR$HJK|-G z&5OFyqXaFy(j%0W9;Wom1u@F1-^+Q?)0{Xj5(DK$Par}%^e`qaU-3jDZ3^;wD5g)0 z>EmPi12KJ^%>PV-&8ym{80siEV5lSpf@(g7XsiX5WI%luP#4GaMKOJWL`#n<(w3y1SQguWjYZ13 zE%<-3Zc`A_Sdy`BV#Hpz=a`JCFlI7H3`E9kc)+?%L&NJvGRQDM#tSihsbpdf#zB#? zZZFt0sOz>gW8GFT)FJoSW)TbCBIwS+?T0ng*rmu(Y+8*KF9v8fEoX*{f%~EcOq2v-uK+z29s)ulJTCp0O@t>BNY=bZ;;p28@{x5(Du; z4+{bfFQeh5BN=?W3qIbC>6>Eu#+bfdlCch2aHU)pylpd~F5o760ga8yM!H@wp`0K# zb0X{Em=hr}P$KkLAtdq^<41>NB=Rv5*&5Tg#Ps)N79R@Jt)lq|jq}dSR)C~^lpf}~ zJ!XG7=@VFL+hTa5CJ4BccAo7v0fsq|W*b`+2Hsb)w(fgwCuiGZAT9H|NIRf2w#DRk zkv?ILKE)_=L}DP0=t)4J<_k2u*d&9aFTv5Sn7&gIM9&6--4CMq5sj0eT_QKWlm3lD z&>mQ7U#AiDjZKhRA*K($oY?8Y&oAWb8+U$wh0gfe=I1NsXD>#X9})xcQ>7B;9YVwW zkPLnff}aC1eSb{af(pap(J{NSq3R??)Nt zL@uNKf@-GePvt=R-G#EF$Z;g@T2eRgUxB zKE4T35x%hl^S)ypfraGvXm`4j&>2VBbX8}%G>kG`BnG0Z1Rg-wnP`|Ul0jD<=sGd3 z*NN-3d7^28#>v=;$jYj)0)?@ru+&b9JKw++*o+zGM6R$pf_A2?wnEvl zE|fJR#|7?`oe!OHl1*7YQ`Q`#Oc{xRC~F4~psW=dri^4zmI7rb$Ms}fPe{Hl5vJ`$ z(*cc>uaiZpyl>T0`05Bt?bI~B>e+m$6=wQix{?ZA2^YFLk>7gmbX^LaajH#MU8buu zMwu=W1JTt39zfR>XqYaNL02Qtb#`2D5ZBL$>!(Y`=&@k1zCkoS(Ks198(CQuc8 zjj+@j$DOzI&aoLY%!yoK4Fv5>*%=CDr@K(rha8{dPFY{*jK(%)#Y|a0j51{;2BK^< zJb;9|(J*BsgR)Xk);z8^i|b7!U-Y0ZnBF6rv1pupH5aLJg|$-nx)+w(1##T<7MBiP z=+dE;!k0ObIclbG)Wn6O`^Z@iGetJ6dsWHL^RA1$>69x zIBFNy%i?-l$=;HYn0?;Y2B#q}E`O)G>oJroR+ zUP9xfsV}m!4!wa2O)Fuk4Tw80!v`ufnG^ZY>n*ru%6ci3-QYsm%j9^VJ7upxXAH0@ zyNM}Vg;A!A#6Xm7f(K+T9*Bkx$)M~mPKT2@Bo(R zX=z+xB!jL8K-ajqes5gAC$5i<>mwy;Ux*1`ismacPSVC9F{{WXD5QN2OKp7Ic>`^N zO`2g&5p__@EZy;!JWZxp)jl;i|dcX^{H`vvZU`%Vf~kA_M>sqH%(;DH8)eC?{8RYGt%grY160Hoauwv zdqiPus?wkA!rlRjG1HwrdN7(X!)9+fvv&}q%pQq>*zPtY;SJX=ls=iGf(S0UnUqRcM$6lEK0kVBzz){#jh#5!bg# zI(kB@eG(TrT}?TCuH^KYSswI3`wo*B`nUskTo3Yhe74zxE)PNF+pgj{uU~R@^t3U~ zj>JIO-3kxLj-Cj{*^!Lwen57+;%2jcpEnc!nk zA$etW4%!K-t8>6!5o5pIH&-W;pn#9V86zh#5b~w)07r`$Fghdyc~u~~!3aHo!IGTZLUv+xRX zR-JwfHS^x~i_jT433(&38guj#MwufL199{QJb;>2X!zJ885|u4j%p?JVvvsxW;pKgYQ6^CtPKkah^@&xlH7-7-b?!3`ArU9uT??8YYrt5P2bpyda^MCiLc##h5USizb1_ z$>IfOrlHmN9=O6{5|&z>!vpBN01eYgGU&V>baqeZ*CzCClFN3&^b*muN8{wOyO}T5WG{uwjY(rC zRH^<_N?(!Em#6e)Df8OwG~=Zd?Nw*cOQ@jX+7!(HLvxCV$&h$2@(PWf-XSZ+>NDVN zRmxbFnm2qneHK1EClo#LM6MWPRSL5jy^*2?t6I2n%<#QAq4JS9rL-Y;wb@9!q0Y)- zm9j$RqiMV~D`cDw*(uEKkX05w(^!EB_m~k18m&)-jO7g0#2jz9E)_~)xGda&5TC_s zzbF(6H6c(W;enh@2br^Iuca~kVK>GEdR%J`&uN3rw;}MpnsP*xIlam`ZTJT{RY+lW zhwQR&BZPT9o*j_eW< zvAIM<(xOBJ&+?e+pp*!&OGhpd>Kc;{sf8^%}g}3>@0(l(z^Iaw65N)uJv|v zE)0xjb#Z7%83CR~H7pU*n$}%OZTUF5z-?X^eNI3a66k1~^P7c2P06UZWnGH!Bs?)@ z5(8oWRbc+f!b~zS4*=%=b@jdy^InW=eSi=@fEg+u4~PsMuL;TfXQ7yVh( z|2d~kQ?@Q1$XI`a2gXX`kz&1(_#KE9N7D}t^GhHl5XOzB_2k!h zO@5oy6Z}phe$TIG@hc1g7=M&$^IKYvLJfu|#!TXoV$SMX7QV79d<9{>5;*g^;`=IH z^*UWmoL3ojy3+REFxnLsSCd&ca|qaf%Ly4Lb{*AhaDDub6TmfEovyYPw+PM{GqhHX zNPY4E^|jbi*w1yQ5xB>BuQ;E4cjp|a8zhGt%EH$ZxEqi|0y)I21bS-8u12gYh@=80 zEW;9j(#uHFn9vjofh*i*w~$cX$f&3r1XcMI)DxCyG8Zg5Bm?0oK&V*=%clyXhtU|C zU|Xly<&Rj?9z{pfx|&)LZ&90NQCmKZOzJ8oSeqhyWy&8T?{#Ud=$I(qzCDBsmD4!P z<5rmI9AYc&(oX!Cs!>j%%Ud&`qH)w>)(rl?B4^rk$ z3^GIBSyihQ@TMkSsT<~!9agg_R6GMl;G{l76hZ)qB@A&ke3j}m@oJ(w*B}8Htd@gE zEUB7+mFJCajzD)FqZ2{^bj=yvlZ@^O8(j;71mezYiMw#blB)5+UEqUmoKN#tRtTQ#QIb8qv9u7OA}AF*vYD2P&DuEKADih@m!3c_|md0881H;RqoB99-=H z&SLl~)feH_T*^x{;!nV-LU2e2zL>KtOTw2{hb2rn&%gk1+A|y>1b}lX!&w4f_yiTN zCY;U&2~=5Wt)Qpci9XBrya09?0~103U{^7)7Z})58`#x2p_GMt8Z-oWjb5Q(1S%@_ zpyec|coe4;&49?|Z=Mc&gZmZcSPdR4Udc0Fq*tj5*M{%bDOMR|53%7(WI|`OKHAIZ zS`aLKRWn3igS0eZl{KNCMsTfh)2@Gq3dO6*A|>r^V!W2a69_|DctD2=DYh#M5A2X# z%s^9&g)V9b8r3%>8R{T&l0Zt63CxX|xheg_SKY$9Ld@(u(VaGI41nVIXGjvYpbr1tV z)?pc3@H)H;pZGHsyjtt<0#q6;kCH0sLHSW)o8p4lj3ENE+yWy8f`ED10`mcU;z8Yb zwZN=_3PCmyrmYy~ZOR}EfH*2*_4tgKtXL1%zhan7{EGDMA)U0(U`sB(vv7)mAUO9}IKPBX{Gkk9Eu23S zK!UH78|l-^?JEosm|rX~Vju{Z-z_lT!e^=eHC`<+`w7f$3>Y+ub+cNoyQ=hB-Vy(* zWm!k>-*N^`!wj}L1OKWS%1A`a<#BoBAHZD8$ZBbNcGU=bIU4`CvdhExmrY}Js)~aC z4#9|ygK)uHffxuvM;1KsR`4Tymg?W*)uN*kRN5X47&M9%v08!>u1Y1vbeNPt#Cff} zvYbUzG01k5I{m9=SflU(TF8gcKxe&YEU%L8L!CwZ&@|$Q{#7&IX_i;TENMs<#2fu% z?i!lh{RC9RT@D)NP7DO$?ijdW?)JiGss0OIE$(VUMKl$ppL)m$b;27$mRQZ-OhmOT zL}DNaqT?+@e=wqb3ZgnDqVv*scQOK7yt$i*{xlJtU?CC%K@go}A^MvU{iPtHdv?T8 zG@TYSo6BbzqG|DoceU`v?K zLBp8EKoHDL;DRw92cP)93|=kFO+}FAqG^FfI}vJuc@%E#8Dx!mw@xah=_adkibl0) z(iH!PifhA`Ft zuHQc0WHxvnmJqdZ5^M=`2Q-XX3%1< zWDOGQTgZ-m~U0Xi;8 zi#CThnT*k+BGm+?MKB|Hy)AfRAPBtv7Q8dyvs6DFuNJbKpwei-pclXrXZ{n=BLWAw zsUuY_HQkZVn4K-vbYnh4U0JH>ZhMBhhE(6|rjAPWEl^9)fE$ho-p)iG#M`ZCcv;0j z5Z;Ev1uttO_{5(E;#F^e7mK_R1c3$+-XJYnzH$j?Sz-mNlP%B{!-~+2w9tuxAn3+g z=+1-BQoRJPdSkp;=m5h>sAk^%plcAx*R(iGd)HrdW_#F{GAw)mz}j z!Znp}(SUh{f=A^GA*)I~T+E0o8aalGPK*^_2os|0VGExa2!ii13*W`?S*l-zSG^5h zEPRg>J{rL4(c#*}AQONEK7NDj7^~Wp#){j)gz!zb@QHyS_?{A;=Aq$h5|VLyt|KDg zx&3&xfX)|&3(#ntF-|*Pv_8FSr@dt%4PS;~gLE`%ogSZt#vn&Xgc1zJ8(slPL|cpw z4~k3cPNaahXVBm?F}8#FESqbWLaVsP_u7iP(u7nOe&s$J@wQh3u^L`Z8qVuEbQ~}W z8eU1tVm3)}AEB0Di1RoDOAtN_FO=Q$G)g(J=i2a0qf0T0dx0W4yWv|wFJRapDlplZ z)^eIa7h59FBV4W${6_XE=67yR!4lQ!f=7xYj6R%RhSJO3crn*Y=Rl(|aLAA7(r-Re zpwsak9pdeD1ja*+4% zXJw7F`!T3ZOX1^ad|X#P_gM371$}eIny@k&5+CZ~bG$wD5oxhOvq)(8Fgm=ZjoA}z zHsJ=QS&8<5tMhvNwH(WZ)AhLq&0*J%Sgy~LV_co}haJ-&Aew07$on05!Pi-*B}3)4 z>R_!Ew@9(RsE(!v*-{Novz(r95P@Tc(_d>1tyLbyFX7NXTnO(;7L6HBf3q~S*3~DE z8vb*#XjIcD5)B`-W;S=uq#si?XKssQ=JUcK-M2A^zo6lrJlquyA1e9>4mzJaZ1{|v zqG2_oykW}Qb~Wg>9dGrBFqyy66-M%pB*9dRe-Q6~4>%iurxaNW1kBS2bLl_8EI2v? z9EBU;1>RbAsF>pQD+^zM&knc<@RcI2Pe;kNNsXsvmIYUYT5C8VW5_;P6$mXp150;S z%$`y_xh#B<)8*q zw?owwCs7ve*P%-B6O>O%@^Ok&j;jJAy&mSe9A&yUXCkTC-Ot*JYUWpnlbx`^8VjniiR?; zoy&*)+d;cuKbH^xXSg$qjK6?_LgV$s8*cj235t!21L7zWE2g;MAdV)nLW-|*A&wz2 zyZBKqNBPFC{2mOum!x&!>$t=$9}9a~mJ4KI-ABVm_;zlgoINgM_Wyyhy#L=0+M_HV z_-D9X%JM;YMB(vzqSD5bSRuv50dWF}*(okOh!aW7O7UF_h?7X9dqDS5H5}>p!synF z*O#Z4z#+aqh*y0vy)43ub@PtCN^Q`<;op6bmrhyHhRZRN?}x%o@$)34tReae_ThN$ zjqB=XatuO-?{VU-KoKte_}kgmSVMyx^UXT`QZ{9R(aTL zzD&ua?38Bx-$+S)_g6lfQ%P|us965)V(Up!`O^Lpf`VZ(=PC#dgJ1FJz|Cz`CJvsJet-a0Bw{8Cc z4gY)4=6?2XE;@0EQ$%;H9s4bPE%{%~t;?=N-<|$fV|Lkx=eggy-KZ&Y1a1>=#Lh(&n^>x+<6S_v>}*@52x`NborC? zJsa|b&+_@3t^CokK|se0pFjX6BjLeweexn<%`!C~CM_ zPF|Za`H0@KnCDdo_9Jp|$SYEDUX^c(`0Bc#;ro;Tn0w>@27Idu?9*=X2b4j|%47Y% zJr8puF{|0mBgJ`OCFt*V@TToOPRp*ZjsNzVX zCp7*JLiwhDMz+hA{uZxlidPkj{5FZ%Dc*Y^zC&VG@jJZcypd}E_1S8-kR5N_?_#31 z38HrNWh?1RY31RxJ@)lPn|kzd2cN7F>OGqAr@7G{MaDE879H`w%a-~9?43(^=sW)( zN_<-mbGEXjZk3Zi%$WQys~&M_Y7uBLycMu<0DnYzr0i@y`nP9eAHeu)EAi!qa{6OA z=j#8&pzE~H;R2p^qT$1xWL&3x28X5k4!r8y=;dR)Sl4O0U}DfH9nPe%E``$0|A~g5 zLrLDhz>MOZB&4jNuQ0?{gW`H@Lv8q^aPn$P>xu0K*M6b$x9Hl;j7QgIGA6Fd7RB4( z_4P#B7+tA-jR;H*2M$CI{f#9&eT#<4AsOU+3!L~1MZD@?(#tNqSmf-sqJD?LU`z6& zi28#Sm1IQy84gSJpD5rD^s*Z-R@9%YsJ~$Fh@<|BNoC<$W#O8XWi7<|3nQiaA9&UG z(aT=En6ZupAxDd4#b8JaJ%Llh0d%!1%xm!1XuW6#Ee}>_HO>!o;-GKC*?-MyU6wyd zP8^rz2Qk$kw^(bshAgM2`&W}L!r2l2ULF3@3zzN&;gdzfm+1V><&3YLUQTBpjePSn zhYmkNn}$aNizop8_VW_>5LKIp&-eK%mwZzv+!2@TYVN2{s>MZcfTNckLFDf!D;ZYf zzeCNc);J51xYFqB$*CF?7v}V>UIseJ=S#l z+Tpm3(CWFMeO-0C76PuHEKX;&tP)1n1{9OS zl;v(C1hwR=b3qhTYg`c_xFFsn^W)64Hjz-<6yAp5Jb;de#_QmC2iC1!nxOGU7*l;(vXJ_+GovH){NEDSph1 zzdIv-+$a9`0ptI`QRMFFzIS*X>XYJ-+FL|s< zHb)7VNd-)nnN%df%A^v6RLabx3dc~_q^?gURmnOtlVc8*Ni~iVFq0fimYGy1!OG+) z2&q%eOloipHIsTinH)pbnVDoCDwCQVC157CFj;1DED2U7$3aNxW+umT3^kL}d@`v+ z)|r{erB4n%6st@=O_XBN@PIvpvt|d=)`Roni7-pWHk6I@5=*GsrrV zuS0@4lj2*Kp$$l|z?=mk)xZSPklZ`KoaF>Q)U8&+r!DH{ zl<>Y!-RdR0rBU~&5FGjp+sG8!9FAMBx5I5!w-=GyV$AOql6tS77#hiKr`8m%NdXdIj?;BOK z-elIqH0ulDkZZwL>n@vJKc0NJYtjF3Lh+@DOQ@SLS*A091S{)-5K>LebOv(_6_MY$ z^JcORaE7>r;#=I_N`eLEHVCO^CYU?Oz2kJ{cemqCvJL>|E{<}DqseQt8G^|&le*guIeTy;Bw+%`Aej$*g!YPEpI>z3MRvd$!kzsqjDb@93&8^e(Tl5|f7 zOuwQU>kjjf*Fg7To?MFiNU)Y-9E4P<$=L(s-ceL7eK>oNtX(*x@A)5!v+*1$AZHUY zVES=3(H-U?Ih%xelCy_MusE9x0eihA(vGar?n`?;@4K{rhe~+YrEa){H%{tCN_cam zZdM6zEY!^|;lrA`6-xNHpl-zyu4U?0D&ZxflK}-!S)m_=pq>osSSN!Vz~Pg@G%~-y zT;In?Xk`l1Asljd_Bys_U~+La)6-0Hd!Z@JJ{-4RoBkYfYi)i{s4?bJjMiq1c^pGM zw*AgyPqFnOYRwDL{38mr;BZ2DorV@-vP^yv2^PUmLrAqTlYi!)#CVn`A1-sxsUVgR zh_)t(rKGVIYME;G0t6f!7IdmmjjE9j4z5G0=THe(A$7wgTshQ@l<)#mH>-rxrEYc! z2c_C4-zm%UOAyrB&*j?32XIFr8rS|xGQY?~{4xn;rmzZvguj}E>ZWE5nO$rOuR#cW zh`i2|50~n-hZD-HNZ-I@na(;AtaR2xNVPN5*~l>t7txz+9q_Q(bVQ-vI-F2mht1nZ z6zZMB2~~kkUoIDl?_#p#c{2$X&+kDPV70#N@P#n^T{Iy)BT2gyYV9(-7-Wc?IEO6dI|KCO@mV#WjPp0u zlyN+NkiGz1+!6CAd^X&1Dq`RWQ{g|`q~B12r@hwqH%LYzN8{;QS0akum0r5w#Y$)& z4EQS-;(cdr`pO(x(yz|oqH|fopegc84hGFNzguB`0!|OlcDbBNyH3fR_Xp;2wpYWY z`n{2?@WeU=p>Vi*xO${gWKx~0%K8uL*{|=w_JjHj=yrYg5UyJ*XNM9G)d^M13Qtu` zANDeRgiYI@AiRdd7oQNis_B61+w>ebC^RN3l$BjM6b_a5uNXqqi=b=M@7iv?5lE`4 z)F4$Gs7m_{=+jM|RfAO*Le+lIfbQM;D6@`%s(J(K?Y@Jr`ySH$wLb2< zLFbX!Ro;=W@QvJ8M!wM}a!+sf*ZaD^O}f9?$NeDaJQ5q=9l5`6(@r2D|Zy$6Lx zg+t-&Z0ur#@Uu%8R(7{AcDI?K%3^=RX0%2^dc`~LO24?Ty2pLZKkhp+?j{&|tjI>F zJhs^NPHK6EdL)(f zi+iej+0<3Z_ToHvYnyURt!3igbSc@ zUBz%XAF5`9d-Ui&;QW4r`{G_l#JWQg<9i*sQm@?Wi1WRUaO7kt(+j>l0VPg(4J7FL zuu|&Z0lEk}574JUW;WBlzthVBK0mAodu;=M$KeK=fTP=qY~&mU^j-! z6Lupg{a~Lh^%=0ic2|k53+%kGb%rhjTNbZ#C+R+o)kHYlLF$yyH{k{vpG14g&^>%Y zUk9DXLSF+_1}brIa<%vOY4hJF*+4 zJ_8w+Yp4uA#3%fn(0OonJ5(OXZk3VUk=-oyZpiMH$i~3Vi#IPx@%a z8QC4#3aQUP7LKfi(u=cqB*08GegT`1hgn;A}Hg zuE^+$?_(&v65lB!@9>Gd&D%ZDe?c?K1=seKx@^&AN?1s_{{Vy`|Pd<@<@OBUM z`=yURVCR8wpO=epcrR4q5+Gw`!;!zCOb3tqzXvd^6j}QH->P}mrDLT$Pe>J@a$WLp zI14JjtCFzPyFji6r3>U74EsPnPC~8;Ll0av{NmPjk9)j-+=Pr9^^SXzjO%`I=1IK^ zAB9l5@R7u@4 zlG^PT_h5^j;j9uaekEE79JMlSM+ ze44lWdcN+PNcSZ^?i)krkys<|$Y;yQX?wMKqpg9|yRB#&iL4dultnj~G0hvsBVI1T;i*u0 z>?`5O3@BZ;!I>EL*#_rJNKbmleZnv90{6HJ{o}5baaX|5V?~xj<*~&sgUXYNm!Wi_ z;uQ@0P_a%zdfhwjtA26UyT{$&A9st4`yLEEsCXAD4=Ub<%9Dx@p>&~QD~5fj*eN0H z@Q%C9FYf2=ad-L0{Xxe44u&37d;^s$6?8-6NB6it`N!QSVRL|tf=cEW@FfA5v$3#m0{?~SdP2%>i*7;m(Gucp+{0R{o>Yfk9&fD+^CG3 z@8>+`?mX`Ays>oN&}rzrCWOu-;WMFfB|03g50%GJO4o!kauc7(=X$$8$JhNu(tT?m z_pPAwNUWuIJIToHeImE>c3ooiF!yzD7EK1%@6;;V;L% zlX}%X?rZ*WH_Eu{{G7k(?tGKK^I9?M3Zq8MQA&>U)=|)TB%A}4>neuBRiW~`WmH+} zm0L3x;5G;qz_C!K7rgbA<&z}nTv#df?*M%QbRNi#myz9X8XYI~8OU(PP08?@PxwOb z@NwzhJ$zK^Gs1@>b)obkrh!COA68z(6hY^)nx{eK!C5`1GHxr2)dDBy%E*mD9 zB=s4{uq4;X@ZEgEUj>~9XIDVwf$VY_*&W$sQlEh=9O(|F7iaw>=-#mM;;a{R9>{Kx zk=>E?kopW{;B1Hte}_-_+o1E{>=vjzkPU{)^D6)Yq4e7;Z<6{9*x|_CP~g8kfDN{%N^B3o&I{W_=sd8EhsqP%12VRIC5)4LH*7N{ zw#Q-Tg>4#i9+mJ2RIae;>^2KZuN8YrMxN^vd5*VxF#DYJvDnAQBIrEOFYtCBjx2%F z3;hZi`30ZIOTFC#{TtH9Yd${KK<9yem6!W)_+_a4D)uF*&!~!UWF3@ViEoym--eY} z!EA!gwJO5ljWV)(y{?z~3}oQ!6B&Lh>^ykc;vM~cZ}0f750vS7<2%jUF{~t-{sH<| z64Ea3xI6vge(fIj8~?bWxOGi?0EQk^?1#!@A^wEQuS9;A`izCZgAd}aR7EiCLsfMN zxhf1ja8-uN4_8I0cfoZOlrBqnG=_a}Iu%M6T=g*QgR5BLIva)_R5pOh1M(SA`B8bg)Vn}# z45bU?b1>`!xut~M9EKjan#s8CR5p=%7hD%W>4K{jhJA2#kht2x&;wVQjO&i8t<<~V z>IkI^u1*;C!F7|w)fa{yOWYeO56Hcs@>}8?q}~Pc04QA`55%w!7tk}HbOAjR!#oZKu5%Z<$6e$f z_jwujSwH7X-JLJV`r=jDH z*k{mrB)kJE*HsLMw?QQePbn<=wi18N@uQ5q+b8n3-tNElb^oVyzt6}0Ug$g$`^7u* z9^c53gmo2p&?oW%Z}sSDl2Nn5Hc~X&t(uE2Q!#-5}M?$LS9k;Gu+#>h5r~Ah} zSH^7&Lk}t%LFGZk*--hNBpOJ4#<3iZoCl=~RZTGLLse@D`2rYv;3}1I-LD{;OT7!O zHc-0YYKvhXT$f8+onh!fWhbaSAa{VukIGA=-UV`3C|w|5fnguWH%Q3cVd#PDS{c`! z%5GBcf~zN#F1UJO*az1use({eI4iO?brK%9o0av3Xd~;)c0IL`tn3X!&fdsv^>8@+ zQVO4G_8UCl+V1Up-p&sRHcv?6u^=m?TETh`PA%c^a;TbjA2_II-){7rVb|%)oHmM& z;e2|ko>d*NSHY^qt^EgFb#u4g$|E_eXG5JG&VJQHU4fLZdns|p#U*LAyg z#a|FMgF+;)Ad`OtG*CL|54+~wd-v?qb5QpIimCX6p1$N|(14zOuUAy!@Ad$rw4Mdy z{CXZRnnID`pv1b0$;WqpQQ47bSE_KT+!MQ!qX9Pp%P4x(5eQ|GVC5(TCRjbJSWWh{nxR-dMpn1lkD$UT zKT1OvDO9oRIm)D&WFY|9gtFB<#p(&$N~L0Arp&FW=Rb?DPyRaB^60ju~rG}csFqSbe5g zZMUsd9x6q4LV>Vno$ZKO1F0b9(TMpu3@GMTinm?v-eC2eV)eCcrKXC!UDcVW`HQdJY=s zm>G`LH0Rakc|$|xq4Hy}pvbefGP{}{oG50GqS@IYo?T1KK1rFKOIFSM4Zenc z$e@Dx1iz+qYKV*ZW0dH}iusx{KS5Tdz5C(E4o1;*Ix97y>2<|)HT-d6dXX|+Co3n3 zr_zvvS>yJk35IBprOvn5Kn5SOu8s@QX4TTt!g{*BsxWOK~J0_E=R9gh{n32 zCr%MppeIfdSDHPl>GtRYJsuM;unnS>yo?5~9Uv4|D&OyiwcT0lC1h%+ta#)2!+aZ6i7HcoTv94*!QY#1Lf~zKr4QDW2mK7 z=AFs&?k3IP>#P+Ig~Vz4J`D4PO!j#6n33!W=rJP|CR$?^CRt;ZCR<~brdVT*g@tC1cpr;Cmh(FGhfC??Zk;sFj8HBU^ zu!<;v@^YNfLi}R^?eIe|;c#Re>3d$MEO|I`KaKS#XJXeA>lb-|hwG<}Q+-sgP`x7m zU#WU!{8y!VRsO#+Mrnlg*a@D81KK&WBFoX^HHjFqx5DaWy~sVP`j@P+?3J?jvh2Mg zd#kKo)@rjyd_9YPXh8Stm7^jYUQB}n2Xz}XcwlH49m%NmP*FI%h{jzgH1oq-IP*wY z4?}Tz{Wf|ci+8ME*1J|Od$a7lXZ0$)FMA(Yy~q};m-V65%ibz`ADKPMXD#}nGG&n` z@X_-c4YyUtU+3{PJf2w;bYj~;I;KYM3%pDfNV$oWt@`v)ib5!{hC87XYxp^OlszHa zK{HeY0@*em?tjr>c4cl%;qb>a>_Ro%e+QMd&3x@}ifu$V{W8NT3OpR%<#cN9NxU8Z zqB#A@-RTeRPIr4d-Oo8wYGk2zOeiao6`|j07Gv}i)MAW&C|8Wp@9&B+ z`n^OkM!(Z2#^`tC#2EcNofxAZ!xCfk!&+kOX!OL!Rs+3bDQ?y==+)vAMornPC40xp z9{nJ;m_fgXEoRWqVT&I98n)=sk70`*{T8<9(NAHE9{m!w=+O^hi(XRpPL{ot?42rm zy6n+UV2io*3)rGZKY%TI^!wMMN557qFw>6}i!u7GV$my>J^H0$F-AXBEPC|omtrpc z_@x-5-@X(*`sqv2qhG!hJ^JBG(WBqJ6g~RcOVOiWy%atA=|JI`emPK#(GLfT9{p~h z=+Vyxie6jUqaQ~TbLqFygqD69P4wuO(L|4a7>#;#sQtkud5Ju%QRvI~aNoxzoUuFX zb(XL^HB^fH4NY19R(*TmofY2fe1;z(OIi_d(>k2H@OwY$!y(y%w$%>4ZiJTp!vvg3`~kg%O5+Wz5<-=m*Y1oSFR-Uv!rv z9Ht*TbJ?lr*UMbDq?}MyzM=|+s`WkYxU+j+SbXUjP0ydS>Am}UL@#d|!P&G$ao2BW z8ec#9bl2+!Uwh+K{jTXTc;L0&@Ka_P^0nRi4;<95Z+E>se=Z zy`+2Z?%f7U-U z{FC_R_}0V+@hyqZ;``#?#D7eD8~>*8yZG$F-SJ(8-^br9{2~5+;g9i2$)Dl}3-`oF zB!7~MpWK*yEV(8*EBRV-cJhPdoaA%K7m{BkUrv6JT%Y_fxh?r! za(nXgF<3Y?r(aF)N(MO}xqcfs2qqCy3qfbQVM(0HrL>ES%jy@ZGKDspeLUcuRW%QNk zs_5$ItI@U5H=^sJ8=@Pdo1$+;--*5#eLuP-`cZUS^wa2P(a)p1qF+XTj*f_pirp7` zFg7tZCH6?{so0X(s@Uq-$Fa|2dt!gY_Qwv!M#jg)$HwoC-xnVjzd!y!d`kSu_`>)i zEYXtq^H`u|SgyCRKp$Y4w#7e-@5HiwfkpZ@{#|@`{QLM1@gL(q#rMR2j{g$>HNF=M z_%_N-?-Ji9eoXwF_#-i* za1@qveBs2xDTNOgK3e!#;dCtS?813i-i3wF6h2$Hq;P5B3xz8SR~N3sQomXFR^dB^ z?-ssaxTWwTEdGwdPYZVz?kfDU5QSE_yYPp?J%xJFbl*RMOWhe~;MY9s+ zu?j`=T5@f29m-^5a#Ql{X+^wdEa-=$2q3D z>fX9_|G%oP?$>!~OJ}v7J=LJiK>D-T-Dj*fC~GR%;9G2#PIpPxvx+00&cF!K0UIM2je&u3)u%d zCF0yG2j&*}gMF|y(Z5>wuSVn;rRDiYIh@t5bK6YqU)#=Yy0+`mrfr+{S|bkIwrSI; zQ>V<#F74a4ZNsJuP9%mAW9o|OtM?Um`Qz{P?tJ&2;rHIWcW2BT^VEudxDM8}sDxjoj)D}?-jRL}x0nN?igE!MAF z{;2ZO>E(s9GY6ohA~R<}mrl9)!%K?FODjsJRc4MashC?hD|1Zc+^Hp{`R&@Y?V8`W zboT7Ib4n@~=8x~2Ken`VRz?2sF*t17p>?~it=qS0+rEANl#)65gGwtZCwA$?SF@sa zt*6eK70bkx+Yprt%ZjI#%re9@x=`-<`kBY8T^5rso6c3xxl9(87tP40;P?;EOXtoi zZe3)EsihV8ADxyMVuI1$5EWBr!BlLBk<;;CCH|Yz&Jg_v!DskbLkt{){}vizKuP7u zDKiJmor3`KxL;vqA&yJ`FR$WG&IR{l6S5@Qy(gmzS58mlv0n zmREKwE62oF8mA0scIK20kt?v0jCNQi4VzUxHP?t@LDRp+<4?jS*0_a1KdWlu<`88| z{@F^l)s}5lm0X^BQFE-K2_xp9Ew}R{I+fK2hS;*HFs(;4qLZr-L74mHYoGw z7L`}#7nNcoEUyF=tf+#b(mB&grnjD9G>E*nXWgRrMh*G3?$n>UWw(6qi&M)|3p}4A zbI8X>bw0cA`6vFK*73uhHJ{l$|J2gs3+YCBa?`KR^jzHk+k--JZGVDezaQ7*neA4!DlGZNX=Ps+qWs*xeR1k7Q>? z>i5>WC1-jKb!>Mge)O$t7)_)`yJJm!MSot!oa$g&0?f74u`~Yv&s8y8j7;iSli<9D z5$VrPwT}9jIp~VN>^7=~=i4nV3qq=P&5_2=^?i zo@r}zyoowK(g8p4|9F-iYdDiZfAKP}LUq)~q^^IZu4SF@qaIcPkI7wW%%AY(JHSa^ zaGlZZX6hCljvw>m`nowBi`1`!FT$v9IvwhWKa@ABtP%Jz$~26o3^ff4jylrU(`el! z57-U;Hd4O{qwpg)VHju1ski&J^z_q5q@K4@&u-`9$J6Nf7f;V7af~>v+L_-M-EO09 zrRU*C9V{I8O#CG~QoohnO&^as-cB9=$j6UQJRNJsBlUaf9rdZ8j+?0CRg>{!7Z#m6 zVgqz+Vp5{XV5rw->h(-Hel)`^vU}<`Fp;O$D>=iCM>u26e z=y;CaQJ*vFxQ#mAzY;$l=%aW10v+?YqeD?2auj-Qr=C}=!jI3+(Raaj(epCySyWBn z81%b``i;8^Kfdm#pRmMbou{9kEA_mWdY*JOe%#w%?@77d=US4@+=5fq zU6zmLMC!k-_0n-tzXzz_2Y2Jg+|l~JLj69@!5Wi;;fbDobuUJz2dUE&Tk+!?bUKBU z)rh=}9))=ZZe9zf&nlgQ+maG|4&Z(UJYU0==VP4MRT+QBk6$L>7m72`FH(2M_(;{n z$kK_C)e|F|CPubSjNCUdvSVW8-HDO+CPo_NMe5IxQRR(|3it*B?xTQJ58+3@iFizS z0VR^YdScqOPWRfzFYSj99yO+5bpL?`ZQC1F?;(BswlY2KWc*feW#fVZy4&QtsN#aM zQrtil<0&P+O#wIjt7|O%UoN$c8XeRK?b>N0G)DJJnirImPMJFmAsfn&wT;@Ee`n3V z8T_lp4=k=6+^>N4myM@z4z-ON-425W>m!_n-|+tA>g%EfI}xTE^nPtMV{0S5CU#VH zmpyxS=^S@Ir@2nYt&~yK3n@RJY2ZP{yA$b`KNa{MWx?#ivV!*Q=y7X$nt>O0R5idw zHzGkS)wc-F^EwXB*NrcliwCE(k?vGyl#}Er>DNx=CE91~*aF@s z2G6O$v*TLOn~Cr50QuXvPpWPF=3;HzQOo5Ngg-X6sGUfO)X;9=O|Puw;} z`VL8HdU@&GvVu7Pj1N2bE@P%qbrUk%!>kVGA_w{`g?!h^d}|x&ZqRmm%qEcdEL1~r z2|a1=JFBpQwt>Bl&_{!fwT+6FeMS%Gl{mVqQT4O45{E)XzZQMR6pS1-wqQ)&h_QVp z77Xt*X1GyxC&Kb#O~<%PX_YtwtJQM1lk!n_=Gy9ur5>UiuAH_QS?z6&VEbL`*GaRT zYNY>yPc})@pl;>y?LPbD&w!3MFcs;$tIwK!521Vq!1qm_w&z-dMW+r-V`4ib^@)Rn zzK(KCOG@9ZP6LNmG{pGYaS`ypFJPB^()fHzq-aDT2He*jp?rigH&h;<2yhTF?NhMC`9pW`_wR2 zrWS{FJG zkp%`@)ZFM*Fj77w7=zzB6;3bi-K%Y{UfzcZ^0IF~OX%IZYwxb~Wt+4bwKJneR{AD+ z0^*WT{q%bUr(gP4K4jDR(79hAwxt+euPdC!v^;v)F?oe?aj!++RsCsUw z_WD&Xiectyq<~nF8Ua$*j;GUj@Ypf(yBGwIGw8a zSKIi(U5NVDQ5(rz+1R;Tq6ro zeq7tAb?(^VW7@ZC)3;NHiM);V?~8rq7?Nj~nnwB;!D`*@lhl3&wdoD<;3{dibsn0j z$*u+GFBr`&XKDLqThLeg=i5m89A`tbFDJN*(XJ+G;833Hob6?xfO}!S+Zl}e+F1ej zJI~VjdKix^l9IF^V5l5BAjkcjV+U^*+Qu5et>Sy$Tg6Ttl5Z99t=e-dXIB7mQKt?I z?6pUH@vpY=hr9OL>UYNtA?|Cs$)a0FEWIM`x4Kte+Nx<-!xOKsy! zeZlDa?^)vSa1RF|aR@U%f1=a1J@ z*dSA=Z9K1E!RbC+t-v%yY_BAb>Z>WH%jUuMvrEb7vS54&JFo3$m%uL9UVUg-ykV2oQX#n-;jdcCbh;hH$Y9WTe$k9Vo&>pTeC5K__Y9JLMD0wY#tt4iLff5Afc0m$BVB{l zz1T^x{pi~CC0z%1#K9lK+^vKz1-PIh-FI;lf*V?z_qxVU-7Cs)gKGn)4?y@=+vwvx zI|~Mn7~6lCwoA}`*!ONi`iGlZFx7FFOgsG+t+|no%Te`BqS`i}fkeK}q)cjQq4ev> zUyStT!JA@%d&Qu6`Uauu8f*2NLrSUD&NN*$`M9^(dA?Kjh>AlF~9jw#ZMuX(b$KWyg<)c2tba%EO`dufM zGu@ZsUtOb}zoE9V(Q{S68dB%vI~ei=O`txVO<_Axv+4J_8L<7TG1I{`fbCn?rtcdy zk>$E^!~625W;`C2`0E;1`?OV#?^jZR?{)J;-RO8uC5_JK*Mg!cY&}Ju(6x=;NsG5% z{{el*4bv}jn1(8~Ur-wKnUwziW=UFlggye^fRWblRCG{#6+IzPyK_Bg_?#{pQ;RDL z@tbC&YMztazx|sR@SfYg9pyTgXUZB+eDn7QnZaW-*j|U3u1$Kth>1YeO zl`JZ&pbs*RwTWZ>gst=eWlCXrc}a0O#>;SwSIVyRv8i^0*ZAF8@Z>vZxXy4~5BawK;UJ$jt8lu5ys6X2vR4P5 z>LAoYr}=LG=GMJ1ZpFfii{X2j5JeF5NQ98w%Qp>KfKRyw)#bC!tAal6yrC7`{evkk#M zJ6AXzUer#18S4SZ^mMT4OZzsUi1@E{I<#+xRgW*1mK97XFPK_VLCb50V{8*<%yrh2 zOu=$G#RA#~I&)W4PAAze$G>kt`>$;|GYN5%<2{9;OrfWBqnx%aJ!!3z2AkAB9Lx87 zQsG;_#dD@Q#`%u%`oWn0f{Kdb0!H$=Gq2m7jYJB2!tvh{(0;y5iLj1veD~Q)Nrvd? zH1G9q?m3E2K~f+W{8LVcu7Q@X?dhC>lM*AZb9y|%stV`f0~4J(2OL#jF$$MarPHCa zw*2TGv7oH5q#Qk;aU44QFNeGMa-x!d&gpo2K>K8M&PzNmI~^tj8O~D+k)G}&xi_3H z;{z?Z$|9M*<#cHlWVo&R1C+YPUzE4KxbAY|jPD`utCjG#9n0uI%a8V~x%2RX(`n#n zY$tpPl2kr+3}*)!DrrNOcNAO?rWVh=FK2OQyEI`Ogo(cZj~v?R{LXZUE?iBuuSJX z$9qpe`yl&C+q^=$xmo1oa<7f2Le0=+j;WgqyLbU@1z$R2bPlvkSGQO)-TR#`%Q&qC z0L~NfsWZqa?RYazx*^-@bh}0Fz}#n%)A+sj`Y7qncC3d(txu^0-L-PB)3u$et7Ix& zOAb1g7J-&??Nd_fwLb*cH7Z!IY~1IFt)TNtJ|d*1x<(iKB#?f$IHL`bP>Rat7TDX; z9>eSKquhH2FtK<18y)kf;bw~yrtO_!?{{(@Cv%a%{FEOTUvWZ?bk-E^ zr9o@4(`U7cHKhoDI0939r%QLc3;wR8u#z_1l}@LJ?UjhNhKnk17E2x50r_OdowD6d zyiqc}X)dbQ9MfcbDEqU7TqbLrkQp{eiT-`3(;H{W?LzVE;aK(rT3$~gYfsEfr{}A7 zPdSwRkh`ui%g)bLwcJVWX@^pI@wDQ~q8T#xRnm+v3K}P$S5<}L|KGon8CB_xZ?77e zS@nl8vi(WZPW?;m8u40H+bE;@`KQ(xU(YysWZFf|M@A-%jO2|mP>wOoisl1`jXZ^F z=Z%cyoAa9YS-EseJ)>J?b2OblHf?Mqmkv)IIMx`8FZLcg_UDJ0IxJY(SV@0Z3qM+fpjv?D+3=nNHMC%OEDnqo$uvJ!d zgqztgWA}XIQkWrz++ z5&npQ)JjE7NKqG8QG29c&lpFltWHu8sj@mqL8Qvg{A|t~e;pw+r)o->pNj}UFo+Yz z0o9Rte`MY_L-ffIy)r}(mHcQ}&F1=a^mUWB`XEbZI(o_Mc{+N??Em+43}8`XFbGcv zRZ|jGhzQV<$69beb%+`cQA0Dt;0!TPDVhQk)N0c))K#QU$6zUlr(>WLq)o>N&b$c0 zICH9|lzBNKAmI{D7zb2G<`a?m_zW>NLyXQ4qg3)0u$sC0bc}bCx5gq%XF5j9?0Gsy z$?X64bmXxp{2hQ4Mb(rtq!e8a6Vz(cG1*n5Pe;BK z#M3cJ3eu*dkTYL`U_2dEO)2xWh=7FgdqX6Q1F9qQ5@bF-LlkF-B9-~oFnQ1G>2Bs$ zF;c`_@QGdIrfyzNyVK>FM%7=i6ST*k6dAYToVml`sLu46tYsa-vlgnRq~&HrfQ0od z0S8ovmQrY$ogpq%LT*93SIBHvh&}}u9-odf*0B-MSqD{9(yOO-aimhyV!>vIHDZ9a=7hmP<0k z#Y%{UcCV02Tp{|LTzq^wE@K^!B0B4!YDzj@Km?@!1gDP!szb*W(6Ky2EX@#?D=9C+ zG%{8kpBCeJ`Si39oIw0`V4VxhFGVhd?sB#m&F$-Xe+Av z5ci_Jm(;3Zt(UX1(zr6yyeR|sRU0#h4MoWP@HB7C@a`5jxfGm^yzO1D8po51L{46#uGIwJj!%Hn4fUO=}=Z7Yp+ndTiDp#Q?t+>!+74i}KVOzaqZMce4Z z=NF1~hd-ZRVY9Zld^R(m-_Xi@sG1TV`dcjUp+9tHK2!&vzk$zv8RDJ{u}vYWBVA9F zMO_qLME5}w-Hp&1+Myw;2T$|C4Dar?!$oA-9eEAiBRMmpZ9a@nqF_7x8P$i)deCL` z05dunt;~q3DKYvBB7jjN6wHX~VDu;$J(3}IDnQMoUvpVxpzs2EL~7$Tv|9s|2~YE} zBtW}eK>8Z8V=$kcK767SYqvk27;M&KE}vb@Ckw62hpH*@X^RNplZ%4+P#t_;0H5bF z#4{PIhHsr3~+G{IZM4vODq`dPZ_)Mo;-L>O{d_ z_Gi=?HtQvq5&p;Pkk$pQ%!sNfG3tv52-F<~Gom^ey#YqAWr#frP(SI{Uls#Ucmcg8 zwecF-s{tAaPxGxLKzm(4`WmuhFrPg>du#QTcRcAVT>`M^)LgAV&oo2|Q z1cevZ7us?)Yd9 zUyCXFQGa5W!e$+DiT%XHE<-C5qiRaTRwDw4El0t`s19PkgV?VM*Ba?`l`Phx@Z$Pa zTVDn}ue0wfuZE|2ED4v9sUH04>&uSu=hxRd3T|W~M)mv5YhbgExwQUZTGyhLX;C#L zTDKtrXx)f{X;B@t>SPWOwK7G`Oy_au?b2_PEH=lsP<=tzL-p1y>TL|dqNtjZs810AqTXjMIG{R2b%dz)nWAl`I7=z|3?``6 z9vilI73s6tRtloow9b-(v`1~7IP=dDj5DWdN|}F;2uSziHDQ8gZBhofy7WouCuQ-ZoFipvlQNhyKLNow zbE>A4c|)0bT}~L2LUm+*E;1jPDTZf?p(^v!VDc`fk#6SJaHNPC;k|UIn|k$oL8IEU z+|jJ15yG<;s-~nR6A>Vx2}{5M)uCkqw2aFXW0a66+Py-?xkB_Q7;}6&CbEtgqO%UF zrlg}aA|QQ})5ihTq2mJRn4Br{GsPq&h2F;HT}_i+DOSEVCzFm(OCf7%gYc|{swrvd zfe4V$i6!8G>d-O`TBc@-DN0CBw0nh2b%p42GUfPmOlKXv5S?{UH6PZRBV{oPh4=b9Th0nU^C{P^zvsf!yeQMVGRs{Gmfew0u?t-c zRtb)ipBs**VCDYT+cB_N7rEElGG;Uut;~q3DKRQQ1fZFSg0Ht!2cwI@XhEi!rvP0b z{R(9<1%(&T0;!E}P!?-|ir{Hpk_2e63rJrkb`0J<=lSrNO0gFE^C^bSy2RzPi1|!I zEAydhN_@%@0eohnU_Mj_pOxUVB2z5O6iXDM3h7!Yi@7Mgh*m(7^O1eEhG-r<%~hG+ zGikMp$g(@~8d@efGovLwjOJ6Y)&7hYz-Fy-8C}VY7NV6IQ8gt-D-Z#UE8Z8V=$kqefX@VSl9dW zSp%E3!R51_`CNro=0nw#`1}gjOa-)s%?c zg9spYCkiG;br9PMVs|NA_e!VxWN|+VFD|@Fmp&cxa=J&u^*4B$+mmqJ`8c>(!h3|g5ORZ}AN zZ$tpGmryVytsC0>+1;(*PHM(A5X&dgo{gGUv`W?zrNn0 z;7|C|+6$ZYxJ&DwOzUm5GA*j6L@SOr(tuV|6ikcipj9(EK-7qeNK_ol6u)PRUllnM z4rZ;W`I`NaDU-e&RwJsOdRdXE+{x&p;4vE`eKP+&bL)~#K)EE#`W4N*$$eMP=bLZZ zr^0r3_1Th1zglg9QLS20s?tOmG5UGTZs~iDVaVUOo)9H5E#b^msG1U$vk?J-+Mr-6 zR0oyQK;_h^Xb=_kqoQ6^oER0gqs~*Y?(i{BkD6cEU`zsYss^Tk2Btoao$mqGiz+ZD zx`(yl5zL4`Gb=j1F|>7hH9E4zrPGM%^no+ep=wHWMj-;|3_!tjs17<&(8-93W>L{J zDw;&a84At0Z~#2{89SG_WVl@PQ>K~3LTs$2k_EA`nrO#oNH9dl{+3~kb&bX#tc$8C z=_)}4=(>RA;DGAT)gHRKMMamW=oA$ll&G1o;yjU}T9K%3{-U~|d8vGoX?2QX{f}c! z9nkz;J$yh{I=Zut3lW!fP&FkTOA!I-FXZ%bKy~OC1RVpSqF+>;6BWIqqNkFw3=Zay zq;q{u3Z69Tgks-`4lD2dr;Y=vL&IgzusA9fMa9CXn6G5K z1FLscE%ukO$dzF&)E3qJYC@`5$h!#4La3UOkS`Gd`G3UuP= zqGE~CasUqI+Nk-Femk?um1C_$uFlrCLh9kIZ<)LGEs=8m)YkVE#aLsVQB71ubqKiwLN-Um?NM=SRNN93e^pwVz`?vL zYW|{6>}FSvbvtr(CiYgThbQ(HcVho4<@~9MZHDozyQ)pBY;h;{PUg`Z&dh_VDe-89 z2$mSI{nbI9n2~8<~ zVxT(^TWP?2($ykO{x-_Jv&N9tqt#|rwz#uuF^oQNW*AgW3C3_l0D}Q2cvh(n7*7Dk zKcnI?MPdZnfk@8hS#hn?YY*ak0vOOOr^W~&d@p(64>sf8yp8kI_Z-p4rdb!%X$rg9sUSb$i;LI?nni7mT zhyVuDQSiJ`9WY)4j6G5DiXu^pb|BK`ZI6pVpSM@4&D-moY8e7>s#HxW)y0T_ROfPr zIG{RGeGjR=6BT=-;!Tz9rPB2>SyZ8*Gs*qJ^*i>o(U)aEjJjWpxg4J62T|P0Nulj% zfqv);wd{^`vRZpxrPiA`#%EsMWt>NpODNcfQNXGGMVO_qSsz5z*E-&3M$6F3jHsFt zqiYcXXs$%T(@AwOIsiudqvG?Z_%tf^DNNT%@Ab0SfWnJuzlQ0shUt2Enuns^JE_AO zCc7hJ`dq{GskSli^Fek41wQPL>_*tELoTv|jO-?~GBT>BgzQd40J2+AFfytG*^fZ> zeN=p_VBIDC?v}+?6kb^0OP%~+_oxPI8$8V;No(q;3rjzF>==9z`__lgc8Yb>pU*w8 zSw~zxKQW(s(aLAPc>ue$()YJj=_lj(3aD0KDho#acjnW&%noFv(jVg46G3&l~16R zaZxoTTpu9<0=_g!tmIGpRUqBm`(1?8k zPqS6bd&?_aVwT;J&p=aRXJpwieq_hbabjps-n2fYz``HdXRukVTx2a7+2?3wWK>NF z*$;>SWQR~NGO7bvXCUhs6YXQ7t>X2gbp1&dM^Jcqb<|c^H;va(c$!_4cy)7m=_|~R z!MNIMxZ3*Q`kCT(^T+jH*sQKDt}cx07ql`is-}eN6uey%xN4(dTvP|Hfxy*2Ci=!i zpP1;Sh@C3E8_MD|6kcNep~_idLo{NI;AswydGEc4xWp{GBd@T&5<4U7qao|%gY0w) zJj5T_8L(M{U1Wn8S!1*^GODJ8ERG03)(izBqdJg{1+vjGF)AiTC|;&?O~@h#g_qZ8 zDV4YR2^z0lc$(vrcujD5=_|~R!MH|gxJLNkYC&-)_~U8`n>F6WHI8w$LM!8NF*+N7BvWrkKGO7bv3*4u!iHTJ)u~PB6Sh_Bf#U&`byw(5#ey_9ASej|B(|BD9 zPxI;|Uh7<5`UYD%=O zK?Kmc0tM5eI%wU71-3CJZjOnYV&aCF*r1qQD?3~#i}fhH%rD) zFhQz=;Qb(YZ%k~DiLEhlm%?|q^xi6qZ796>?v=`UQ+rUuw;i7514;NEbn)p+&W^!L zZo5Wot9E>s550S6j0gSc-3y!bfJ^UhOz%FlGCiuMMDGbi06hx@)1x}*Jqmh{#Kca; z?MdnPlq{Y`;pO%S^f+7FZjIYB@H8Kbc^{?icDY%0M_zV2C42%m%sDBar2xDAp*#nh z^_UA~7ejd-tqg^#DM5K15dh_1C>RRW0p)2xc~TL1Lpr@Fi?>jCi9D&Tq~|mud*Nw5 zn?&R}mx#WS>=+&(Z&Uy0{DHg!oAs;<hD zFDoWrNWcBE_!5Pe$t&6_d0k_20G{S+G4F%B*Ig!--H}(x%RZ~*AO(2cAIc%vtk+y9 z|7IwM(aKP$ni7mLe-Rj6xCuNlTa`assqSR0P;gjd>0en z#Kc#M%v4y-!!h{)vm-sg{K1uHeP^!}`i|2#HY55)1OL7mKdi6ZM!csi-g&8&rJitE zHM8VCPxDd($M#pO+M4OY!UXZ!>@;u%>a$Z{N+FR}J@?q2orawGO$f%BQ#GZ`cOU{1-pUE%fa=IR z1DQ9=5>2y2lPqyYmT08%|2rJK6V%Mj-)f3P=|W5s)Wn?&>x?XZphl-oBe&USiuj8} z^2>giEO95sV~JEvN#e7J0A;&a84jopi7g>9H%lb4L_AAmWr?Vg_#7O(5_2_)2~A?$ z)naA25~FUjkHl)LuoVk^5u>tDs-`4#FCswStE>+PREN;^5ZX3NoRuYnlK8fCeMc7W zqVQfA+CuPh`s}kj)9i$I6*_+t{T@8cj#=LArISX-?#P$Qvm^#y!NNUOH&^dduuk+_ z+v>mi`2aSnW0rdG+<_T=h*oAq)sz?=Km?%q1O;Cus18Ow!Kizd=%xT2lzxX~aTtXc zP0LX0G(ca$)9jrDsE-RsKf~=9%%__VpRXxaAAdgIz-IM!`SfBw-=dZIP&Fk! zzas+p{Dgw}P#t`RfzOaEF(^w6P>BAJuE%77|Jg?pq9Ksv+?0>h5Jli=j>z(Ef+Jl- zmfexp&>)wKHNZVqYY6}2JHs65&!`4$)(Dr;aAuT_R%S%ilo*|g2w+qf1v8>L7)=19 zaam%F0@P6YohFM$D7b_`xaV|@6WL9r(J^Jxs5 zmFM!A$b6chmHALLB|f=`06v*0m=D##XFB*4XNjULQJ5tP6r~o@yQM5zq3}{FhAL+n z&D1EhhNoGQg-eyZmYz*_Ix}5Lmfew;QIU(rDwG>F|8l3mZC6XG4F#U*kE|_hR*8#j z1|w^SRz^nEl#um81R(2-f{{@j$SQ%XJWG^ii8+c_Z|T}c7U!Vw@+y~-cva2Uc=dy) zIWLLVe3zHLs_YoNs>(E6b9`_Opt$q>aSepcn&;x0%eV%im2puuC0yeX0l0>vU|duO zu4TZrBui9fiA%G@C5qSt={->vc__TZmOz!W!miMWO@gPnA`5p4+6ueEC1%+jd4*NE zXsk;$WS6+@YK5Igfv@mKmJge?!bP^6k)4lLMn=_?kj+E{Ae(}Mkx?DUt^u;Ev&2&-ki`gi=ysnm#c!jOkc+G*Qd0i5(^)4@ch1oH9g@!39DDvP#u}KLgp>vA}21)xX4z?(<^Jtns)L$9WC7CtsG?Od`2;4_BlQ3(izAAvDT%UQ9J7tJKpoW~sslu|i;FgK(ON0mL5f=G)6vdVq)$g1DTt?| zwG^aHM@P>5?@s1aO)2xI5CI8WoG=ckj?8-@^B!?=c3gCgi_R+fr(rc4=+n`|P2M^i zSvu3vRc6oA(OG8yzo(-&i+Tow@EW6PN}~Ra2+;BZYrz54A!;B*^^c3banVO9dJQJ1 z)y|Iot|EOp`bt4O9et!AZ8`>V=C30dXHM0WGXDq>knmnk7zb2G=A)4Lh`1OQ7eiF$ z|AEPSUXO4yw}v4_%mw|hhPbI$|6}9oFNi*uwS0{5tc9v6X*q-lknkBxzyZ~vWjwTu zjf>Gr$YHd5g^YED=u!4~%I{u3YNdG%d9|u&2jsoa7KQ7LTi##Re z7nr;!_xY|A>pX2v@{Ui-1+3*)gl8>OO-V~_{23}FL{RX>km}G<3@t@*QK*E}LAzH- zkt;->lfvWEF^zSci0G_?swwGcj0n)tfYZkT)uCe!bj*s2nQ<{gNuih8c+c=zt`uvg zHYYQVPfIClITPVo3sqCn5=R6`XwDLFKy_%TgqHHSC{sdAw0nh=yF&CiDLXzLb6H0M z(OCyoQ_|5M5s-dMP9FzUhmOV2u_!JU#>IRkrGs?sC<}VUjrYEEk(?F&8emo2eQ4Dg zp5|q7?`~1$Qn2ifyzMP?FF#WDqGfb<(Ei$N&7fL2ItD~%^J&D9#9!SFO!B>`IP0@9a> z9fPlE%Y66@p;)W^`3!~4TIKS&lKBinEAydhN_-|G0{Dza!F;F=J~xBUO>uEUTx?K? z=p8w5)n19?MRXG+IiCe@)ezBJbIgr#@9uW1i^#G&@*289a%M&wd>HYIb#C=%L@&y* zHoA;%VMfJhWkys@iBY)}ejy5GM0GH_3ykiFi_Hp9h4ibG#at9#KzB%OyoR=Efabx| z+?oVvn+r%^Lv{@2v)P9azX)fWKOcS(&Q_Pt-OOhpMrS@$O^J{Ff*bWB9IAuQKfq^4 zTs#mL_bWu&OK`B1=nXesL^~kKSwjzNh*lG#opJAO{IHA2vODq`dO&h!M)&(LT0_Ae z_Gd(|y|H$>j2>b}YthP#sG1U^n-BqtuSLOYi0WYUI2i4Yi(Lwk{n8xmoj6`VyQMZ> zLr-ad=(RcKlSzP{aslaU$d18$cKPtRm0~^R&xc-%V?F8ed4l=S3vrkaRa4?~4zSCm41P5zj+aQoCWl%#)sd2^Geb_{i@5yvODqudR{^%K;ifA z&Uan-^*68j6XVz4yy6o37Zck79ZZa>DG_^2lGw?hfR5@Q_9lqEu5j7!$oZ%ArB~p1 zm(%Ooa(Y|CMQ_P5_a@(Y9QY0(RDm=;x2qV*~w z0Mhd)czsbFv_1x{kK*D31#FM>v)`0M@51o{`$$_~pK8Efho|{T(jNY)3(T@R^7{JV zc-Pk(6#Y|wVsFA`ec}?^$Hd-3D-)w?O2qad0*Jkjf{9Tb#14Sieue83>GY{AK11Qf zwO?Cbhc#TE!_z#JgzK=2OJ84hj6c7=zM$ZT{b}uo%{t`LI>@xXL@U#xYD%338XKcnyh`$1b@KWo7L3s3WC(*FLl3(T@R^7{Jjc-Pl2 z6#Zv^V!y&>9d(HvVPe0bm5EU`C1NMw58pw|;6J;^0o6h54-orJ;i@H_YRjSy3NNnT zwDlD+-Onv2!qYTN@BKo=R1cQ*^<~HS^XscF1&^4BQT=mFJ=iS#>cjaT-5g_DC!v*T zQ8gu6IfwvA87O#tQ603Jn0TmeibkerXo^!z=b?HotY!mKf2i(iw;Gx98p#jUajYJy zQMdvd~%Ky_r^3YoVsMUE*|&8DQ@-YsPldGsOf`j8jtXl&*Kl z;%*e)>u;W%6@G3wS-bvjg{OJG>0OzVT?&@nkx#J+E(U8Hj+37oZlhq6{jaz5vMuX; z_j;SpjP5}zGoorrjCLXd(5P2%Q5}q?fzeb`Oi_RymVS@Of?mbt1vFJ^BmjUnX`8-aV)I@YzMNO8oge2Aeg*_#i|p=wHeUPJ`&c@hO*C8!QQ zmEcouiZWBoQHWlWt}n~tUnsnY$|1@5$Ua{~^a?!9d8YSFn(rdA?2f#K$|PrIG{=V# zy}!$x@6TutY}P!N(OhQqZ?rNas;0!~Lqq_hy(pLw)xqd8Fj{PiMG6qTk_&$Sk;TU- zynq%(5`R9Q!e(9W@~L7zpP`lcP&Fk! z-ys5YA4I`?s181>!RJa-T%q`UFa3Uy1--D#%jZhyaTd^8jn7Z;G_OiJ$JV-hEW0Bw zperO~0u+9ocb@qiq3CPTChKc=*RwhQ(l!&F(WMaP|5EG+1h^+^)YZa~< z(kWdQHBoqRU8^mp8#G)ez|*`w3D*rSE`2%KG5$QQS`_>Se_FL+v#xh(ZD3k;(8{!^ zni8$k5CQA!Bos`G>Y#NyXx(axTNJQH((iOxoPoj%>{e}kZP9?yi`LA|N$1}d7no&t zmHZZcBa)DtxSumDbXrL z1kfr*!L+CjTHk@zH>UW?6o*W4z!duxIeJBv`GaZhwm&irq%Vhk;}WpGvR4{?6g*^O zq_4XjFzG9|^amc+el)*8pBBIMdzq~Esj!{%g6K+&YW-j)zaUz+^gYLULG<@bWiFhV z3RP30vJ??OswZil0q!#1ua&B=klq5R)GvhZ2upTps$0_*vrM3)m5f zgP2%9N*)Bo{`;QaS;%q(W+7BfNyx2;03jPVe;iO9LTV)jh?)seBOxLQaZCxh4OX*G z!aKJ$6Uk4U_)~t31j)c0VrnA^HMPh7=hP;@gKrB4wdy32r&hMOQ(HShLhgVw6QOEK zM0Owo0&PRVQ%iLaX$T^xB*e)HaZ*CmO*jvs{tl~mYEN--SSN#l^BMaj$%CNK0=C~v zTNkZZ>DtVm#yb9ixU7S!Dd~6;5uii9XbJ~ZhmOBM$C(MyI3Z3~BA$ZDE86=fE zE5PHe3D|tRZ?b+H<5{h$txehDuFaOr;~hBjoKiI<9$z8? zFwpz1cx_T0JUW6$`-Etl5N9QXP%sX_3Rc>-)7~YaPitEVg14QsBnaMige0LY&Q2`k zAOf=xs-`5Q2L7BELg?jAEQIP1at?&_PKcff(LEu$B}5mcB^?fCzl8aPKC!)BIaW{P z>P&2RsfQ=Fn>(>xq?|uBv9&Rt)vwyb$`*HG`!bI@aAqD(1?H_i&UH_ot@0HPW*tSDR+p;!gAVOy?{(Gaag?M5iYr07?gjf&;39P6_BtPl)1# zC`yRJgeXvG_$5sF_Dr8kT&BBR^qDS}Sa_z3w3#l{jte9hZPsV9uHKF=s-~oi-arI7 z^fD%1zVeMk<~-=COo;M?C`*Vr2{B9QIuD*$6mkW#u1bGh<(jTCP0JkZcvdxC^I2EE zql>C3>8g;rE_8HJ9rJY=bS+MZMG3J`DXN6YygcdFXt68GT7)c}MZ8d|qD4#}D-6%e zi39I>lW&X`U`XroYKvF4xQn-nVJw6*FJ7vq1Y;Q@V3HT3;7O)BU|azh%M)U$BC#Cp zKqTjOEUnq)E(U$gE_LVDzN=lysjff(PL--DrFtzQAk|fzAr7dHRM#QZwF$8%Ay%nu zuY<|FHtE8$)=k)2qs`l@|0nZy1BSG&tu}A6#htfn7{-loW*AgW3C0#g0E1gl@VrqS zFm42l>l0$VB5?=Wfk>OT>s<``ysfV`Z#QwOcOn3%O4XE7{W~Hc)oq+14ycY)??kFw z5@J(A+?Eg<6XIr-^FQEV-ko&TZE@4KHfghWn>%~fM!A2`hs~SO9QZlGL4}i!032|>iY)^=-3dRetf|Yh#aKB4J zpTK+F3ADCr8|hX_Lc2gb$U|hq?f)J7`|vb(CGbH_0+>KM&tonC%kD_Mt%o!Mf7ety z&pkh+V2>pLt@^hgK7!5Kl~CV)c$69a2d&JAswpv|Hvs|7XDE2GsSZZZfYDP4@q_|& zSo(b>i?3050X-$P@ssrDH9+6O(|j%o(DN=JeTCRD_;%t6A3onxtmpmt`~aKvoXh7~ z=JO+3nGaP{;#0?dkpK$jLv`@^2z)+Bi1!lWorKt{D4i(1>&l`Y3NNJ(pvqZB`!q@? z!PERW;r-mS&!uG99eEkOCs8w|ceE2}uMe{N6nLLMvXf!6K6a7)hmkcvDg!o+X%9O5AS;SCyc^!~ac~yO_@yddy`Bf6HuU%gHs+qWTsg+$KBY+!P7i3$IGj34sFeF`nI0F!t5A~D?NuFI`Wf@G{kluvpIYG zc#2y$$9IpP0GoAUj@skvpAY6umkx?DU;y{*_BceGXL-C>)b;0#YS*$|g<&`C+ z@(Rn*c&&z~naIIYZ+Yu5iEbToG+uT`W)#&JW%w{!L&0+V8C?aNm2erE%xEoInGsb} zVstYiK=^eim=V>%s2v!!$q}t{L@UMU7U{ZC7Pq4CGHRnS>Zmcg4W4F)9Q=wyW7JV& zWOrmntu;oid>GwM!8-ag+60@`!DZB*8Er-@Goorrj4VU|qX$qhBdUYZNH7|nBZlUP z!8u}}!t|*0-X)92PS1b&-u?WKW=#kx?}zWUn9skjWRK;ehHumJei;a>T?OF<$X{Rl4qx#lKN_ zc}vcu=H_yUC&+AIij7THA_wEgfj z%W}LA&@OVJS$0QWWHTjsrZz*PHcdO8>O=5L8ss8>f(Kx;%3Ok_Oz|_ba4`rj$`K25#QYpFSK<4w^!`N_zoPKsTO^h9nyb?A{RU6-vLt*}EjLXFsb?Rc&az29k!Dt~%^z-C?M(z}%D9YZVAqiRa@=sjbgm;BzbD?#sy9I;$+ z`(N)Jy8?QgWw%D-#_t_lo#TDBx5njW*&TV=Etl{KoO-Vjzie!cKNNo1*lHKbDu$w7 zHb&KypkzrX%~0@?qB@q;wSclt5y_TLaaousyeny)wvskzL=x~c*C!F#;1bbSk{!bX zB!~KM@CQO~MYGnsK(1pT^fokJB~(obNJm7#Dxue-F%YT)$gKc!OOE)fV$wVR@Lpxmj543tjvdNTM9M&TuLr?yJAYea^?)7+MWC$93=>3q7q z+^!L^J9?JJQ0lbZpTaQMtZgoZtxSR5cE%K_ni7Q>hyY~;D3}7(LE&jocrr&ko+EbW zh+PUt39RO$Ia1RFr0Gdb)8qE?pkK7_w!zS^JNT;)^w@Qm+vxKWRDSF#-}CwmtE0D# zu{x@zq;3HsKpnjijMY&c>iz|FFXf0Aa>R2=+CrEhTS_Y;X)n3b^ppApDS|H#&$-9; zuQOiZ%r8bT&YY?#Wqt)BAoEK(VH{8$nZJ$9-^vkh=-77ge@36+z7?U+pH6@L=AOfVVXK6T~Iy8O^jUVNR4|2qN zO5jGAAYPlDk6eNJ?0n$Pi1nU(Y|qX<&iqychY3e^IQX{(N46%{t=p`HA_widN=B)s*f)S-I3SOA1)W`H}_brq5n{@nz_JQ{r4ju!)B%Ds%K|4a!J}gv@#>Aro`xLL_nbZ zD3}q|!RRC~s+%k7eOK<1`38kbwK$Gpq!a28t01B zbH!;2&56>xt}N=I@S-_WTRRyVn)>iGo9BA3Dj6CYrz2fe8ryv7i=U_GsxN+?<~I9W zSLCl*v1W#1ich8CGW$&b_K-FxuRpPXrC+EDvsTx_t~=Oj>5~aGsHSq z!|oc#p71o!PU6_z&Tfpe zA6gkFRa3$_3K4*F5DLagb>JKToc(geIk}>@VtKA~9W9G7D7-BD*?MVB4%S$XgQqzt ziRECIrM@Pe7_=tOaZ&a@UX*z>=3sx6lVGz3xhMxR%Jb05D5?5CP*y!);9vdxQ)`T` zXPi7Ttw-aLk@_PeClSH=pjVhTK$PU!7mJfeMjDv2@~j=>S1x-tf&Wj-(t1YKvkgHH zA5kXCO=;!QomtqGPBoWK+`Xh$4WsHg*sWQ4)Q-#R&a7duHnK{n0sl*z%Ny3l@A95c zn5!qYTe)llbv<1(&Pc3S`eQwsoQS=&&d{t4(Dj9c9lRZ-gYJzrhsJPtF=19w>>DX| z6U|6pbbcveZX)Af$#|w_q%X_9oG`bNaU&UMEY22ZV%{1d682?4T za|Ag=zMUdxX!feDG#&T{zgH4wqdYj>M@})#DIHLDWVKn*=htW}km0pkJEO~-Jj_{^ z=2vw)hvHx#w=myBMoYKGhIT8>GjiEE9_;+C?VJnek&y(=fPs%No3o5=7g9?OFEBbx zVS%+A8EHWatR)uM3@ot9JW-w}%A94^$|}!W(PvMB#htw%k6cCWVj8w}xA|0@m3t`_ zZLG>XtUOwM(0>^gdP(Oc_Y z{nY5AS*x8@=XAT6BJ|5$PDTGP*8!SQj-u37l32Ry7%0OH&Rs#_hH5?Rk*}ro&*$?n z&FChbW(OKB15Fs4E)Tkxi}Jc-LV=5R2crk{(?O&M2+%=V4-82M={+E2*vQC)Tvj$w z($5=PLmsp;7vyzEvRF5~fAqkt&_RtJSUc#Jm&;4(JZf{6HY3mHrA>$K(ykGyY@T66 zA}2*oN~@JNw|T+HvdWUuITd3nOUnzV7aJ?njN0i&*1YD%2{j@MHP?%STob)AUsRc}9D$9!tXKTGqf$5|)Bzd+Pxl72%or1%62n|0#h3^{@z7K2x!g>Xd+#_`4 z5o+Y2AtMhC4nHt7e4YwFJ|z5D*aC!&4jy?_=*Wd?m;zC}1fvg%m(d)8;!Ty( zYr*602^;q<|8e(*kNdG2_d_@apm-l9Ulb>$Mbh^9kNZjZxChj@UxWoe=pX!0c<`T8 z@bBRmAnMz&agX?qdo+C9Kh(Ith6O+7AKb_cT_GoCI=4@?;20pPCQN}dRToB|m02%* z+=go024TTZ^AFxAJa}sryrtLCb5EEHTY%sMOum96kvL2NXDPPfPHN=#AtSd94u4i? z_&zFp&yeulVG9t}EqLTEp(77gBM%4}xnFSjb3((9R^dm6gdYxDfUu!KBlE4(L=}Eq zNcb_KF$z_T$ssZFVGBrcQfT<;D*V)t@KZu#l&KiAgVVS$C`2Su0#m@+j-*`#qtAI> zj^>an&?1%6g5YuIg^hcO|G108$GuXGy8?~@GqMb(fYW>lOo1p?!RUixHJU?EtXC;r z6FlzKVdHM_ANTt3ac@`SZiHh1iko5bML`$iP5$F<4j*@$8uzZS;M@I!-xD7EAr*WF z90No>5H{{k|8XAa;H90>o@rE+oe`Z6Ky;^3N zu0l2ZVGCe338sL|CaRJBGaIk$ewkgUGMfRvATZNl3&?CLOaYlq2_3mojeJqa z$fd#IXNQKbQsEbegkKaKexVBQ&vm}C`*FQW4ZkX6_?55)a9sgY0M}(|WdF>TD0{Wc zB57-33_440R7r1uSI}a(4z_^Iu2CcVXLhx+SIZ1%$(?HW%^}0z4qE`TTVV>w>=re$ ze`bGG_G+0$((ZyWh}i=w>HFXn#Oxl}0y5jCM)uF_Ze_2Q8JJmW_?;oc{{yxFW;uJHjzw z3frr3{ZY16cAvbu!swG%H#CRjHAv;vAC3Vi`@$5Eavzw&Q1()GpOgo~=#%mgG>4=- zPNh5=jsba%Qserg9HHz!d5wqBC$9-;4#}%n{wOb0cAvZ|VD!nW63robEm3)02FC!Di(v{#c@a!uC>JWb zPs&SS^htRcnnO}vt5RMA$7*@WkCdy_xJfASk#eQ7X*tP{l##TnVf4vq9hyUOx?Sb8 z5sm>EZ-%K_y7IH;O)v$1I==zNFvc5{UDM-y5Zwf$kDkqF4$<>BrRQEa1|+>5rog1P z!WfqHUCQp0^aC*ZB>f5cP7{xUcz-`+E4e@2YY4h6R7mKluCM!H=lmKX@HIPqV&*EkN)$F!|16 zB=QwZa^YzUi_S8BV0284{9DM#zxaih8_Umr;mO3|Pt0=e<7#Dj)~ZKXP1pj2)qp8L zSOlhEVGY&D4MIk)9~{13X!uMOzFA24rmzJFYZ5&28EWLDz1n`z)=1g?X0(;cEEj&- z_TWLDfGr@iI7|V^v((7`nMIY|FS8CRv$lSt*W_oPX9bTgf}=;$I>P9)MRr27#vu74 zSud4R_uz56g^k* zJ0@)0JpXYgg^xQ!jav-I02DC7i|Pv0Op1;Rg=?)x42Va z3i!P>9$dxL$QdCcHwzBmG&HE2BcIe0*)yVBaMs5=vzIAB$-YR^L zknm^279gx^@W`D*M;@d`?jJI8-{A0lLc^b{!jA|EKMb}2VMBsO=3BH0D*V`x@S{Ux zT%cl{9}?p{*aA|_3k^R_g)a&TUlJH6=P9w z8ViF$L?ZKH3fNa7X_vw1vkg|EIb<8WQl+#ac-&=S3+*Tg65EAf2OJK3B8WqdqUU(1UH1qcWFi9qZ+wg$jEJi!?z9%-&2J@J0yHp*aC!g4jP$n zo%*TpeL}+b3XL&b#TXJ2V-RcsDGmq?KSqTg6%u|#XpDRnBQH3O2|*zuk#R5utnEnJ z`7ruifhMCl5^L!%#+y;^3t z;?_<$*ZP`?;Nfe)7BGASrZ6zaf`^Z!)j{VVFsG@^P6^5EWY_{`^CXx8lCBGrOxll0 zGd1#=AtN^q4u5)R_?9YsPDpqYwg6$-!6V1i$o`8VQ`xHtkEFGNF=#eAsifP(D`=Uv zg)IR2S!!he%!IO6%M8o3uNuC0$nZU33t-kArhv@4sgeCN>!R${GK-}3gE5HN2$l3u zcm**V3|l~E1J%g>ne|upYMFuA`D*w{A;V9EEr8j0m;y2z3sc}%07kG_G)QI z(k8{}!a|sQ)27>-%V7+fv6X7%qACf9~>Up-=$(~35l@@wt(z!3kn~JY=kLn#ony!)mB9$ z?QR%@gg>Z~z8_ve3+7(fd{;#zvR#erzh1X0d$r8K>`^uR!|)5>@=);Te-DlxN!tZu zvTl5*`7tzWLX&@i{;W#rso-&+2pjh~|8buWANN0M+z;RwfZ{!v0w&@en8KFGUS+Q~ z5s|cyVe~<@56vN{4y%+8z%d}N{c2qQ1@gJF`{eZ%j6QjNjpmTNep7k<7mfiakHQp? z@=q{@q5MJFeNz4%MxT`bKyygSb#k1$^AmCc^Gb&)EUz?W_sQ!-7=7}pi{_BLny9=^ zhhqTB(_jifc`8g{DK}7dpOnvp(I@4mXbwr)R4He{F(9v~8rOeSW+=N)UI`d|^2$MT zNM7w#UTxqQkXLIpu76&wl-(z<4lw%U)e+4hd5uze4TodE6c2?dAmza@g-!85W%o(> zTo`>)9*yRZl+RZwPl97WUK7>0{wT*QyH8$|Vf4wX0L>wJm8!gE!7%{kOqc>vo&i(f zo#8YX!#Gb>b{{=uF#71Z2+bjSE>(IK!7(7|g)jvsJs-xfq~|KTPtupc=#z96nnRLa zrINk^jscUf9422qbf3H0f7~_U<6fu6T^AO7y?^ix;lXcH!Eb?MfT+KQjeEQQxSPVq z-KxgDGc5Qv|KQuhgFmB!Kk0S!JP~^wwgADqVe*~DNMsjGa^YzUi@vSIzvp;Gjr>x` z$S(wke=aoqJ1YEJA>rSEEkM|7!6WYp9eJM``J<4LKL`&0UTFA(D*S%<1tkA@aP&`u zqes#X!RT|kA4YS?>Hd>S>HFYuzYQDri2t}p!^f?W>)f#!xq&GD2u|s@u$0mf(g#IN zG>4$5uTrWD$AA-~4om?jMkMWI|8X0HkK0U*dnOzMRz+i&0#Z61rm%~|Y06&hT#lqQ zhtUUB2AV@qwNNQ1;24lsT#f602a%=hK6$l-(I>A~Xb#D%o64&*90O2xgef59_ArH^ zY^&@(DW46aPs-iV9Fp=tm2y8g2IO^)8rL6XZ)Nw%YY>b+c@0K$NM0A_(Fs~3ZBAZu zE=##QDS|gn{HJ4vhEH8@q>$dVdqjF(cF}2EVAYY7gGk9*LCY88Zs!Or52_ZCFY>sm4j^ zC)6`eWPih`JEu{j&Lu;-O=#bz@A_BXSTim2ygq4o=Xn2a`3E*x`)|HKf9l+#3kyo8 zOq*L#RESq4SF0BlmQ_@i&M6kN3o9y%%kyVf%qz-Y(5XZI=;B$$g%!p5jzjCRsZ)%` z#$SwPMy*EOsxq(3T$Xut=Do2;V-LpumG$@7r?H1(4`%I&y&ro$_D@wei4#COCWj(-vVXZ*AHi}APPAH)yFKa778|0w=tyy}#Q zVbnO~|B&_`V0Ii;!nTab7%+xqfdzJ~kub?dns8?ZSh%-y_wByjEG*Hi8BLJJp5(bB zS@tHAGnky0oWqiH&N(bO=bSSv>3^&5ty4#A>3^Q@`}C~AE8bJLx^kU5;o1{tPHyiW zz3*wyKJ90x{rt3Fop$NOy(jKV3*3L=ffEm!crYz-*~Fu0lgCXwe&UG}Pnmf7#4{$I zIq|HCXHPtL;&~Gk-tX`I!QLP4{n6eZ@BPW%pYHwH-kK5_C%lTV&}>g3ZV zpE3EY$!AYKck=m@FPMDE-N26-#hlbpWgcLzK`zv_`Xl<`_#VA?E5_Z_mzEL-S_o<-`w}@eT_;j=z+*2m8J z#95y_>uWcE#C*=Pua8lfWr^{`pW#DUv=7ZKmX$DB~SUx zYxmydj_5Pan0zxXlgsK$sW( z71!N!dRMo*;l8+br9B7#>Pv+ix4q%MaOqX{oVH%Gyf&uw%()aJMymwXU>^gIA{96!RhI953OyUn{5qu?>gUUx0t1=bC%cF_fA}g znw@Pn!sWH~J!h|)-RomNdH37?*IxD4dzsyu?B2DwvvlNKQ#k)ri`(04n}^R?+H>~u z)^N|+cVF9c_FeW&?>T$8yk2cBuk1OyKFmM6{Bvk(&)IPXQ{8FL+36km=i)tQCu_U) zq4SfYn-nnm_h@lO%f81MbrOzAgF7B?KxYw$BZyh?HA6x!^{IQd6}>7q ztZZ-X?B05Nhpyk%dW>by35+;^43MeiT>K|@Z5t3&doQM){ic) z@UQ0_IA?0=zybdI+@ni7yXP)#u@vs?p0}~Gv9x{hdBby#>^c3E%bz>>uBSg|vU$>N zZvMhMKl`^Ao^jLb|6dh)(QtRij0RKYji0dmu6zIL4)^=hZPORM^m$kN{Ta>wSw&S* zPd|Q*hfm$Qo__s%uXo3HeIUKz8Sg#w|EhY!UFOkwOIw?(Yoj`T;bWKm%NLsB4_90M z^{w~a;tSt7<30a(1@qmM+;s7N$)Ycb9#i{Wu5q^E@rnno9aU`|$!!XI0tD61rwZ zhNQ0K6C7ElVG{?m2=+IHdh`O+HDHO%(S72IY!$k0zh&$gt>#MO^i| zY^>vE*W^%m#+^{rXddoK52}ZWu$W>x+kNdtT8D^>>Vh`qKoRF8f)(U*|N_ znw>uS=l|1@aj!_?v==~L;;HD zUsh$FhXY7oHJ>HqOco|Z5cSLM>h|!WaXqhKzWphqZ-2I+Q)U$`%edcN_0{t^3M`^{ z5M+a{w5I-`=Q=RW^Q_;LaaS5sgU=Iix(u>9=m&%Dj(2oE-;r5a2Voso-5u}fe1Rj& zD9ZbB97FoX#|sr1HvOv3qVA4&biT-ub(~gBS*P6{@92E7Bg?Ez1~e$7@7G`A$Sf=4 zD(Lg=(n@;Bz0{HUASuHl%piS3?q!Z_2E8P%8FD+`k@R1VOw(RsmTgGiNP4-DQ*{`n zVXxQkN|CxVUm@UhSY%C8773tT=JW@>Qpl;Sh|;_W!mj+bF7j0ZPDf^)i&&F}-o5J8 zLQW-NP!9TopgZ&p;@1c`oi#z(gjLjC+Bx8vzpr&9P1LKRJcK;xAz$Z6w%$R}i`lJq zraa{99ht;@P0;H>PJ75VI5H^ND6=YqobixvbYz%Ty);h&XFcGX6j;Qp#c=}J@sMwJ zWYkOgsX50i?aX<|w>YxQsxZqdw*H-Y5BXL{_Ul0r7dboi&Vq-0n~*bX>FFSjD#(Mj zkM!F0c869;KByCxBv9K)8hwXD>$=}7Qw{*2wwE;ePKP$^Fgb(SpthSd`Ywl-IXg@c z&j9^|HdCwx=}u9zmz;u&OGyr0%kJkiOTEO*zP#lKp+zJ4oN>$U(2^ z_wy!)w4bl1=ldO56?IS)WdUiwUXveiWS;hWy(Z&O_`o zi!>cH6{K&Je%O)y0V`uw4j_G_^dpW8IfTT$EQIup(vLbaih6YxL>%h8qx54!&ZKpj z_VUow(>qE(?$9jj4E|4o_R=a(k_yr{NI&n$un7l2RG6cXouT^Izu?G-y@uNnC!uXSK{feB zM+O7d=O8E`eS`E%j*NRfu4Or(Z;XCfz^S6l`kb$t?gh3r^``h02j*cK^pc|PUSJzj zgI{%Ep96K0a(}zPwxtHY=D@O-WN8*u-3x3}YVhk0Y?>f#fMpu`bpAbrP_ z0@607CV$|_CaDT;q&cK*O-=sLk%O8ea>{P7v0)E5!FEgFh8;x=y%i2K`>wEu8wdf9A-h%8II22avuV`ne+q zSrQjf7()7b=ogNxYA%Ig${AVqcKz$WbYvc&_d#g@>Fc3iIkL!ug!6O)>Fc3i3pvZK z&Q-TayTjev?+fz-{6{f94e6`tZQ*Nm5u#MDV7ey1ez zh`Vytj3uT|BJq1AG04g&jr9hAKROLb;YJ0dlD zszaMz*o%`WHmF@RGf3fhZHH<0s*WA> z(q2E~7G+r5W1791V~Ym8PQVq?u(r!Idzxdp=yI6mVrp31XPUjbW4Y*})Z-dySlelu zy@q4UxK}ZW+5vXZ_L^p|>DVYL;;hc=wp`n7nmygIA(x4`Va+ggu>GdlYdN+ldMKDU z+rUoQU0JhdIJWKuJ$j?9!<4VzuI<>Wj5yYE!ZGFg`t3T7Mem&k1&18N`ugo}99s<1 zEN?jH7}nQs*L7?jqhqZ(>KNA7Z-499ev<_CfYXj)ef@Sl$CfEAR&n4ltgqj$@7O39 zgjH|Qj`b;DzumyGVO|wYzz$@}_4V7|Iktffdv#lfXh!b>*Rbo&( z4m7&op-EIlae%H4)D8oU-o&8{t~~3-r9tf|(CAr$&PKf;2(xh11-?;mQ^$q{N0pSf z0gCmmx;Im7$TG^o#-O&p^rCQchX!R-WpUkht#{GAg=3SLt7eG0)Rb#`OqY90$HoKG zWog^F-bMFp$EImq=DmK~58g%h9LHu&(kp|y?OyMqdn?B>$@2anYe|I~MfPaC?W=bzTjkq-Rh& z7&O{-XoGI2W`{7S9Sa)mIke2#f0>#FwL?LpfkXQND``?>2DKwWqoG6dK1Yi*i4AH8 zf<_~U7Ex1%S&$gijsuOx4h`Zoig&)lt@KTGsZLW(&s_gFdRrxNce7VVdnbb`aJ@(aVdL zwLPZU(y{Q>IhKF?+Jv3JS6qhs^5N%A6TCxmy= zy^~{$rmo98XlI0X(fudK4to72ta(c}b@27uogG^hC}x|Yoxk35?p+*PhlSBSwu_B- z(Y>o2F1xrDc4-Mi@C-LYxXLn%|VbI7~s-ovpaY#!8Y9lVR~ zxsL5qhqBjizshS zdg*h8L51c+R|K7o;xtaetf5txJ*~Q`NS-mHJVtl9;3E$UIWx%62{z~}XjO~qRz0Fn z^Dt}{XIj;Vt|=7FX=&C2TGfZ1uh0bBF*5{dRUdkRLVMVO&;y_|K6G87L0a?&Sgz5k zK6FFSY4)2kh-yA-{vuDSZYna4i;V4oR`rovLe6l9Wot0HLx&0tVl+!ltL^ony9({)XBf})a(nLM_$0tQp~o?J=l_Slzwpy(J_xZI!{Tsp z(bH=WaAc75ld_30VqCN%;quDv?}3i2;*^_VmP2lM%6yO`gC2@>Y^NZH9`eCL&eTyB zqx28EtBZ#$sz<^@1f5Q*u&Ft!b{ChIJcT|~$Qh0^Xc0L2Kpr2Xy3mISIvqqQFOZDc z#bw{uKU~P!$ZWL++qR%SoIJvTNzTAxz#7zkl13lt&@fKol5G}r=qvRyhh`O~MvQHP z`bvG2p!1kwB|*Raq~Xy+Qr)YVUVWPxT9@1NXh+8lnkTjmQ!unGThosbdZrF}v(BQF z{*ngMP5W3uXR+4EFoNK9cg?Z7As**g^e9=8mOO`oZjZZ6vyT@R%{VqFMW11~yyffN zCkR@0G0zR^tft>qhRZ8U>o|yw3%{CajW>;2zyWZ-sIUT)8m z1TMQxT%c-X$%kISEZkrGlSQJ_FEW(hDEdYMp5mY4;5xwa5Q`H7uWi^duj}$ufrDNb zgE&Up!CfnIz${-R$+y*5XrF;`xHkW*K`Dk5nyc zhlZ}i3xw@dY)b5*eZy`HFYpYy7YaO6V>=NsrVVV{OxNK>g3b-l)+W8asqTvE4gGO1 zRy0>Z9_ukgZ)sb$re7lTe8xLffPKb@J|<1Z6@F2J6- z2}4tt;YqsXzl5HN3(O!w^d8W@Zh5(&vth;wgd1dw`nu&6!gl&84=@oIUW)a1%PR$* zVSz-4-YX1j$DHn#R|z`XB>i5_Yv7@+qcWxS$auA&(wz z{`t2%G>+?jiV=Kwb?J!xevQ7vp+&%k&q)&3j78h}8hxjr(@h>FSr}4*bxZ1xdY2=y zVU6pUZFy;n!hdR3n@ ziYfFW-|hB;f=;tdXDB0RGdT+A-~W)1vvnQzaO7dgY-}B~r+>Wyd|22{iVss8Q+7nU(vc0Y^$pa{;05>w2%J){D}1x{4s&&xQd4y?>SYrC0kne^2del zppQrgDBeb}XFL0Zu(O!_S51XmhAG&VtE>Fq!gk_1j~iY9M+IA0x5Xy~p2ZNjU(_s0 zrr^WlO6Y<=C2WTWJ=CkX3AC)Q;7)Xcq*20y14dq^CY!cs-F9CP zcrG7c?~V1?xM)l3qQ59~2b1Fgi^Zs=H@7_f{UrzE=8)BWGxtnA?Ea(c@nwPMsx0Ya zt~u`T&7+=A{EE<>tTAs^#!%c8ZI?}5^j8I*%{UhYF^)q9wsqFM_%+9t1JtKjBDbuq zvSz<7Y$uM>nn$Bi%h?L+I($ReSz|39W3teeYwN4a{id+fSgJ8T+WOiW=+)(0Le5qt zyK%!4=F-OY(6B!-O9a|H<&VNrN=6GL;_+!?AR>0HM-xqozj_NE7a7h@!qNKg5IiS38bZ-BF z;GKjOsmw8P!2f(rF7mopeyCu&kmq=I90S{K(eRH1o{dBNB8`H7720-;Zj>Jj+u<~Y zJ!Xktntl}5ixui$uFNK`tg)(4T8|R#* z=_${5{Yu#RB*kTqO{%+eYDeoQQ*9wnYX?r#L=B zM@;HM}7;l@)UcK;@h3sHt zhk3j4w;^POJn`zq>?#6Jr+toB0izog-+0RFuez!uF$PB)l0vQ>^N?2)ayAJ$a&YE0 zq^t~jc{)w8Sv9~K8|N5UJ3KXeb;n{{j~WC`@+z>srE2yX!gi{Vy)#IR235hj5w7Xr zvh1U{>9bWB*0=nhF7Ry9>*XwzblKW5nSZ(#*HSDGKm-uzwXE;!&JcE{&#ktKF< z7&ovUHP;q&Hs>6}#KTd?e4J;czK&z7goAm?gQY3fewwcC-v~RCmQjzV5~{l`{idsM zU4_;h3NY|BsQoaF{;iO|pyCy5#oj3O5WAj`vuGgtvAKO2g|IDE*Y*02#pM%A z89c#FND)sH+`yqZH|DV78E$2h7-t^#?}T08np#v5&x=Muxwyo_Gv@WGa6{o|lRkfP zo}&%#JEq;pu~;MLTu@LQOdS_1ApLnab}WH3&{}aRSXUYm&HlZxGYRTq+_S6h`uTFu z(S0%DP#!EQw0*tq>LF1dX!J}$XVKeXC&Dw^>Y?GTZ{X||w!^zd!t>$iNVIKXJ=-P) zp5q}bt>Tb6u;#d;^%Z8H(6cynbMxZru)4CbVLL-N#D2#HK}#AjBtxvb4N4Ho+WH2;~9kQh2x=NeV=zzf#>j6CjbhjovUk`C;7aa3C&vB6a$_c ziKwu={_sIca zIkFcKp6pq7l?7nMK4$4!9CR=SF$t<2zHf7lC{^Prt>GzwXNtTIn}#J|b#u%1wVor> zf_5sl~S_?TWL(CrkPqCdb88hB-Q+cvW<`1S(NVWZFw%_Gz5kYzwF zbov9kj^??thk+R%$T)ISThl$EX99xXV9rRd92aW>JwO9Nd95i>PherTdR#Z1E;tl= zAuR|v5t;BVBf2x=+595mJ3(HU6^X^`_(_^N7I>aO0Wk)v4F49Evh{5t5gZ*Fepw-r zL{>)|@wg_s=Bd!L1GG_P`(S?Y`jlM^^gzvoolEf+88mn%tr}L`r*+A>&>hU^a$Mko zF3PAyITh(%FBBXTM+f7^5o~uW4fh4cl851hEm3!CN6OXRSSpkd7p+w?s4Z2am7sHR zgtI>@Zui&;71m!jP;^@LYvW!qqHWolu7#crapB>88s8OFW!=h+VzKuPu-9){TdrpB zAZ#Zvk!`5*;g#K?TtjrL{i9>?h~)}^X6}eFcd$1x4c}40LB?xn+#A8R78<^jz`W?u zcLApLN7n6nq|d4UBxDBzzyRCtyn93&iRfbQtl*5Dwc#Aq!oE7(Mc^6CHuEGRx|2HC z>yEywLJMqfaLeYL;XTUT&7nuI12n+~|7T%b|Q5$5{p$s6CWvbWzahBFLM{c)Pk? zOt-@!A+gsY;9Vb+B}lvP>Oz+sItYq{_k*_3>2d37blIV_RvGs3Poh+-;M3@eL-C^Sk7L_j_yU1v%ptbI4ZOSN?xnin)&-p{ ztC(tF9cxhAa(XS>aBR*6I;zYBg0&-3vzx+p@`(A%Nr5RmM8`GmXx(sI0?%YI*9zn8 zZD7xs*cNm)pnZdodnTkURafCcLFeKDN5>2;*iobTmU*EYct_EUihhK#_=vWPnWl%1 zMyJ9x58eK;la{@!=rm%TK)FAnePtgNdVvXog?n8=kMyjT*Z1^ejzX?} zZz95jQi1WXIry7;fjhmi{*iyz5_pR6^`p*fC2Z?ziT@CZ`Pg`Mq}ZGsJ8_umec@7t z6XKIgH7#}GIMw*Q1)oL%*`W6hy5}$2d$L}_?<3??#A+X*%z_-xK)pNOSHS5((GYwF zTf6h+tymX%KOv`rFiKbiYDiC!_ZM)6$M~9;r>uMa(s3KJPOn!F5Og-^g_xeOH=j?C zNXzO4;DN$UB}7+kG89os3XAWM=~+U0KItI> zPU9v@L{iKb&zHNGF7ly5PI1r1A*<{`dWw9QfCNGb@JQpi%c;V2kq>v|z(gW3;SbN3 zH+M}w!jWvRRX;`Jd%irOYx0qftg|HT=Y%FYU*69(d6^@tDl3WXM;pm=xF#PZXMjRu)g{})3GToKrwor?gg7$yT1B9%ds3oh)RS3 zqG5gYeYRt(BI#v0!w1w?-RC$o>2s3ru^t%KSKa3dJAgXQMt8aE347xJ9K~zW-{QA2Wl&;(H96hUvN>xvel5gD?@29y=}eF(FsuklYr=t zW8Bt5<1cb}${Jc?T5fS$7mdHz;Za=#ETseo8&$@(oyK1x_)N|#VneKMgIiR8h8L2YF+Zn9A5P}TV>`mN4W1Z|I6V#5|+f`;4??K?=xTS@P5EK zEH$4w!foAkWnSU%yhofE?r8@m}X( zZX6g+b75{_`Fwu-L9^)+6!nS)f{6>Li^EAnLM&%RH zP}y;%7ri$*cF;4P(3mV5*49|FZ+2|WD+XFrRvcJcVa>k9vFN-)9w%6FU~PRh`&MCR zu!q2Vo|EVL;t^{_u4m2L1f3>^dNwct;nx?f0$d*$-Yz6Iti%v)vR-$6dHF)$)95>d zoipktZ0>8=jpIvVpsp`;?-ZKw>^ZhweA>DMQ`dEPmyk0IvmokWoXbm&Jz?k%d$&Ue z*?`j(zA>N&$A>$OzDLk$eEs`DObj8=F{yw5y^bt!upqEj(j|+PhkT!qv*?YD<#lRE zc`eZ0^?qSFTpFh{>;%Y);wkk5LUuxI0*T>EORe%iZO_Yk)P7LlX@W-MAxCW7bqN=) zKkGw6&fua-^kl5-)(*Zn(-k$`YM6r_@{>Z&7Q~OL@UQ8vZ!HgPsk;9^<=BdtTWNuRqG9a_)a<7ni@#-U z9y43kw`6?AvBVsS!yI2YQ?75x_^hxqX`lH`JTF-9>*VJIoy8}Lu%?VwNIL{|Z9gxl zu^B3`BhOk^?n8RKenH?F0{mds!ciX$mv7bjqM)-C$rmc~uxwCYD||^$cCVtJe|alzOnrkN7m>iN`k<3*S&5nUlnqO*Vevq=jgI_jKoATtgqbf2;0ePf+9vNwHqf} z>b@)RY~8E5q!LJKW6e1?>I#2Pu}MnS5R7sS>#M}~6&qrPW1?omdOz+5iX~hqJ2bIh zVSVNPP}una@#1j-#7m&HL=~e1eP;TR!_E7JiK^S;YkphNA1j~i#k`GuhKS%h{CXE}ybI|uASplkk1!CB%kUP*bqIl3f@<)doCs?fF24nmpTWgK~$>Erzkd%R^3RC*gp%?$N z;IlmaR#>SUeA%ly`io-&jAcnqRJN?ILG~Q72FJ75j1bp^XB$(l9U6MEIYrn`5tB** zMPJKGujrw1IR_Jml`9E8+NNM>Y7L(%@EpN1Qts&^_^1@E$I;~-jVUVbb10cY`*BO*-O#>WoZA*2hvs$+9Zu*j8VTJ6|j-i zI|0vQ-EEvsRxY$9>oz;h(M5so6GQhgZR@P*t2??O8HRbQ7}K^Un!bjkvG6Pi2sf(9 zVNu{{`kIc8Q2gN$KdQ-LQF>|mbVnyfH${NxwkC%~m!;`z3Ed%-3RzLGmEJanskYjB zh@K(v9A1X0zY(TMg{`g#to3Y-o(>37K?IrKK( z^#xua{vI|~L@nIjFjLmmMDLq75Pr_Y`QdqnniyVu33NaHozOU$1~{bV20kv|sGIMG zj*XJCV01IZf#rsz;Tt(PjtEfR<0`prjzPW#xv_&yGP(f~l3LhX^4|+QPq0N2$j~or zg*fNi>8SUL2}ef*G@d4&)i$;%M|Pwp8b4F;IZO;Q!c8!q41UzsTesd`p*smTJ5GA0 zt)VTfTVztfWgE`d?n~QP^7i6@AGcvV1ip? z;KbwD_K?lOSMtproP{X)QR0kX-?Y7jgUO)AdofRBZOOiB+)`jd`*T|ukmY21h{j>O zyXYO`Y{xd{A(P~aEo=Kjv*$RL*C)aiwx8#ETC=xuY!(hsY-0nvJ=~EnPntd8ShC#o zY8L61wcn=MgO1Jmy^M^EtQ*4}@3&1k7M)i(C<#wySl_ozJ2qgzXO)>yu)aFXIJPWt zv^C~`+bp5Bmvwz-9b03+OrUGi4sLDMY{#(!4Ek`m;P?RRtM8n!7}KHE>9u{#;%O_P z2l2dvi=-elXWPkYrPc6)z;kszAaw`FN-E($c-`8;BpJ#3ytR&L+i-e9-$v-!ydoqs zw}Y0ptZt0k3cJ8oTrqy==vME3L}s<#ApXJe1utw-VGa=^UKSV4-_G%677?-*rQDd8 zEk*OUcRYb)c&A1uGve31_31hu@2~<-WIDdB&$_ohJ;!6XhS`>xTqE9FpFsE-PP?rJ zp}Xyrb@~Ju3OdKR4ew&su#GLu_+>5CofJ9RysToWN$QrZ&0Ush&yhD4niv(>6q&`8 zZEH+w^;05b2W4eJxI)s*U=l2$*YqGv1)gn4FNvWh+6JC%eOkCo*g1U8$?HVaDp-yZ z_8DJ)UM_S8+v}(x=2lBzXw}@h8ij+gy&lAUE}f=mQ9)_AFYp}UZ?S|m+LWzhN7h9x zq3cl!-NARRSK`Ip(xS1_MOO+o&g29*9>G@Oq2YnRb9sc)phv6|>al*rTaQ}k4u&+S zt$0^7w6`9Og3|$3#~gWE*jJA`2s}@GP?B#DNfek9jg+m=DF3K%4w_u~+HN$sEnVYx zba;XDGC6_UuGz$!+V-Tz?s2_Wlv7>m-jY|+ta`fiF2c#G$OdraFF z)b!njp5-Kl`x4exlr1}mUXAbJSPbY$)V?a z9g6`BmK4NpGpx^V;*hW%VkzO1gjT0z?P*L8r6mW~u?ZQ`&fKFikTkpOSS+|pDq+e! zDw9RCE5gpAI}2izvIf4ySK(D*=gfmNaUbcA6AsgQ5FHkJnh3y2PTaJv+bQ(=e?-Vx zawsKz%m583-=;fmO|gCaD9OFjvUV72_I$+-O0te%TtKR z0~Fy{a0A*GRt@et5LabPka@P6l|9G|6nJgO;_EOn?4G zjwSpYuXZ@vn{s_K{kX96F;Tuvh7=TPMkg!ULcNw$umwz&ODJ&FHK=mql7 zp{8aMZ!fJg)Gn0mQJ;nXUHCZ?lp9+Vs@|#&?JBHG{|})Tc>g72Jm&8$J>1=~`>8Jd zQpXd^FD8x`cU@CD{Kj}nY5v~A&vB0?`Rb@Lhvj`jSLQwfFO)Th27;xvg=6UNt;~HL z&-*5xJ%pSzl`*`pGWQdH4yAlQ=gAO$Yhy!ZqOQ&Tg`UBPibS|ZyRf`sC%9fX9^lZy zAWn@Azg10o)|dwh+QDx(iqV&iw3v3J=&j*F4kr3P3!=FP8I`AC-=f+07GBo0zBjO_+-4M$t=C!Sb58Jt}`}r~l zljLE5XN0Bg!l&s+2|Y{Fm5@sZV{{dj=MV=g&S#o^jAMg@lpDkZ z0F`Y@qmLD|Ly$sanr14z=^9yg^y37c%gFRJ2zVgeUfou-{<_BtJ>RC$B9%Mz&eHap zICbfj>ci#krOd8Wu^$!}L~bO!H|+32e?^`w z_*{+qBuQd98TW$S`&vY<{>k212Car;OEj0Wr2h(&#LCm)iY$u|IpY7l%z#$>YX*{Fs z_f_LL4#u(+V*@j74eYDNa}`XUaI&Z{n9R$74}PA52}YO^8EM4YmeW;!zGE}qc?rgA zo*ZZmUzK0rV65y2CyD!T3;SyELItN-{SG2ijkQg0m0#rGIK!EP?P>)3>ilAX=Ls^O z;5KUX{N~al?@W3kzQo}SxE^+g^!Et2ov87bIy@@sK4uq;r4eo`qw$wHoRB-5__-*J za5=AN{J$I?hc$L$c=n8NQLSnGJDiMnEXBl|8sXlSd5y#41~b+M>zEPlZJF0P zJj>%jkDzfD_tpJ%f_HedFkz&jk2?LQo)fPZmcZrQBh$vTqIuD>pQ$&IHwaD1y(S?D zR!hq}fG+xt0^?T3b)9XJcO-kr(wCDr2|0`6f|Dwd)*%;d74%a1X2+HZCIqQ@;efTb zKFz*GSYpuh!hS>AQCMgErmOo_fw2PS3~7RU0s9OE-zMm6mggK!329|eyEN!Jyxp;Q z(-Y;#tY)yb<23sYVdn|NQxH#=a(7l%S9X_d6l6VN-YIz1jR#pTHQ6dGzqxDmaoWl9 zT_RF;xdh_NXufj%6T1h-8=v0B-mN4^pohi^+gOn}=#hAjlE9OPy@4B~NZ8|p{*CvF z#6p1LW59!^2-q>8uO9CczEk3lMfi1gdGnNLJ3#mA`vsm$QL7LKd&J7Ksvh7Ua4_*z zYEqt#V0nx#dDR(t<`7|EUq60E;Az5H#({Yq+gY;p z)l1-Kg`BN9dIbYKtT~*ET2a^cbBbk2BbqpAy_UAU>a@=bI~|jmp2SvUAX~DhVO@hS z2su9>PCY}Eq(;lD!$XUrN70MV7adOIO-?2?`MQ=5pA7$!;InmFkYJ2uaA$c#JU8_B zec7=@C?;bjNyC=6B?P)gzanS{qepz-nJ7EUJIc0Dykc5Z8(S@jJhO{?VJ>|YFD3(aXmnUi%C}|@^BdnLW?cX;^!F6a%LV~}u*`31U)kRmdb+?956@4^9$H!qSO8E9L(6p1^pAv|AQdtqk?^BX5snzXE^*#B{8)gw0oBgUXsv88M92SJIcO=6oWZ&6W#=@0v( zu%vUsiis@hrda##po{&JpeRI`kHqIQs02CC#r|2?8Q!*db|)6JVLc!A7eO&?Chm{f zXn7(l4rj*I(fnz`m)*1;(0;Yy zr)E2<{`%;8btS;(_IUVW;8_X#30mSBB2jhmMI{|Bmz|M>sg)JcH>zuj$aKiVEm<9y zibw1;(5vU^Le6lv3wVN~SC7cmSr33~Ih4129xOTGf%;bOGX$M(uvEa{$$aC^xc&6+ zUt7o-Lcy?ips|Cr3$p(G>o}Cfo2xTUbD+N8{~JL&ICx^~M<@hy6_ewHKKoo(!FUdm zw1zogU^@#m{I>$n;LeQ(hWzzIzpLl<97?R&K|~C{Hh`sPF}l8>9W-8~?&KkKc)>}c ztKL9hlM0X8n&IGgA^kgt5;%{oi3c5WeA#VDx9$xE?ZgApJrGs6+n!HsSLjx_k%F;e z$e$T<^*mgg@Px80NZo}VT3Y@a)J(zGqGHMEB+ z-C8$wY{U7BS!wF9C0(Z3n>n_sdJREyOf9y&Rya3ztZ4?KT``AY?TFOn-a^=EB1ZSn z!I*CFEh4vc)|I&8Fw%tiU{2qU>j-HZ}H+oQ`6# z_Rcvdw5;#z=7gO|2q{m5W}?};XE8m2<^?rs7TnB%P z6?lddUKA44tgDoKx>I_BPKV6pm{3jKqs#X2qUUHJB+l^xVUGx7xVkITSr-}#ir*vZ zG~=+jdlEnL$g#Xk69$Wu+U_NMn5U;>Vdsd78sod#U2UV^*{UF5wzCbWB7?l&GlGr6pR`UckE~c+mbbW2L)q4K}sm%FH*8B za~l3f1@lnGd5!Rn2KJSFM}Zg6?-7y+kM75OkZ0u!qJ?$nc)r)YqCI^ykMmrB=7E%^c^wd?rTrP`e)8{G^rx+46DsY8`|oNG<{D;4+v65Fn3^`qFTfM>|iwD zm}Z;m8`yTQhR+k2wVrtLjQN)K4*7d2n5>sg*tQH>S6i|k#ft(j@Djkdq19U}!VM`~ zkF!G#$BG*zEv+}kZRr|c5`2DuZ5BEqhH=YF>3ShpRyfiA`-FnFxGi1dD}pcJr=Os8 zOUJm&sibSOs`!%JF%71kquRK9XdI5j^W$k#L@ z?46?#c0{CzK!c?vM#wz5JF&ItspD4XptGj0X*t#t(pd6V~ELBIre+_TT*Zj8dMCIjN*hdZB z{=l|LqGz=ZT2XVMNGuS1r^1|vrW(aMkq1@%3p>K2J0kuvfpbm3=237IaUjsYFcgUe zc7_CX%_s&lRq}qruJF99hAcB=CA7cb{A~3v92JQL;$x%7HjB5Z(h>hJ9CLh%y=~Nt zqaB|t$J|AZ$AgL}#O&a0`6?NpZlmLluTz$LGDrw-FISqsSaX@JvaEOiB7E5;n?;bNMA9{%a6%Ai-KPI45(^oZX@aqg#>G&Dkk;Su zZ^D;dGHK$Xhx)4h1-?PTRO?^(caf;N2~pih?=lLuJxUE|2dkbw{~;n}7jqx%YhOiUb^6Z%K)BN8Y(Gh^{e zTC~xR=nm9Ba$gZCyJ%sGim=kH2z7E%gY=KwPfPTOiI1t4ldy|{mbkx2U;~?w%$axS zVtoQ2Yq#c3Cc1Wy6Pdb;!7Y)0 z2wE*NC#l`zl~5RwCJ+O3Cv=k9Jwb$6hEM^ur|fa%WJ}XC@rfc(bqlOdvw_JIfJOZB z^1*30TJ!?(BrVb-JS1sZm5A+9E%Ia$nGbW6WB7!RC1k|t^W{?nC$j)gBPL|in4da0 zEh73Co~lGhy3Mq=pD{Ik&@1sYk(lS{BWsM8>*&L!p>&=8Q*i1O6JWU^gusY5b@F}n z)0GHD1R;TJtORxPNjyU&=1rCW4EGqtZD+{(rR(%e!A%AR%x{gsy3|QTbUQsuiJ;TO zovUOv+Wz*6JX?tniYFlEko}SAgI>$a8_?GEX&jI2!e--52!-y;ww=ZcQLBHYD5o zi0Fx;f9NGjiu}ta>8AQ9Jz2EWOGS$6)kGcX@kAvb3R>SCWjP@2(_$rmBz9S^S&k*15e zU`!~YcG`_ZPBtE1tEB2a7F{NBu6)$V#>4AGis}_6h3;te99PeNk#4=$iwM=@fSj|4 zsvlBosBVWhC@FSMG?c`jJE3~^x3tt7MGF5TGMHfWH5QVV(+kj>1g}U-L)2Zo$;Z5I zHvKhkRw79+Nl~}jdg(UPB5x6qc{Ivou^LTRnoP#DuGCuvr&5?b5);C9r=C3e7v82s z@U9@F9f9XYjiqOf7J0jf%wv|%t9IS)YE(*Ac3r7=2u`IiPOD3E3T~$Wl@byC3-44S zRT}XXsQ*VI%uTPzyOapQAbT0Et@c+=vgN#6MCOB{AF~>^CkFE!c7W*bc#q(GN0t!d z+nmtlJFJNQj`u1NcFhnU22RO#!H{3kBJWcoNmg(RFxT_ZubgDhdB2DZu=lTVj&D0; z^REwN`gr*PEtBK*GWvLtv0tNQJ}5F=(^Fzj^vo{MipUhvhw={zKj`9u&Yo`0GA*yC zi2jKWD-jGuF+?&K^|6dPlxdldh|B^pP1w+||F+e#pP{SuQQ^_SF?EeYv;7IRqUfLa zm=Ym!1@D=}D7G?cf6+1@7nudZb4A39m7kFTtgH12;RoF^CJ%Re1hB0oBKjx(TZ!O| zG%(2nZMF0~(K4S@GN^e`LJ~sReTw&YJ|!{>T6pd|Rmve#28x;S zwo`PqKBGj4s!8OQcBQl9(JS*=C4)5u83l;&tUkr}JD*cBC@cwOWiE;gFlN2p_I2Gp zuVqMoQRZ00C>h`Hd_iOu&XQO^NWL(G_VOtF{uIEYd7;l1MX+E_Ue~f2*nLyo8)I& zA^S^O=vPXJ2~8YHVg`-thR}ubL0ah7S}0ElmrPJ1E#&*9-zcGqWYr~kft=7m|2O?s z3x&k{C;rh1LcU-6of7JE1R!dj`lf^aZ~DC!N_b!7rBMCSg)$a&L;Q~j@xVd;?RsFA z=~2(RpV2-02Q6V%Ljs>U3Hvo#;*TORhenpLq%626~B z@=B(vlQbm?ua>cI&sydRB2#qdioj?)-tww0lQh9qluX1;9Rq&%J4$7(>vmO#v(FF^kluJmcSaX7a2{mm9UdgOPnqeofO+)T;mMyGO*|` zzLsO7jLh|zzPGF`SF>k0mZcU;NmhcBMeMk?V{tufB3!3h)>rOz9Gh1a`5cVSW<%L( z>Pq~Lz;gvpdt`H<|2LLMd1c?g^qO&9p*tw;%0YrZ(6Noxqmt-d7yY*mCV4Xvqm0JM zgmbZLmxiyWV7$D0#>t|EeP4Ke1(W)OLC7*>!i@MzzJY?NN7*ArMhp8&{yTx^F=h-* zU^w9QMZVBJ(CZO@coV_z-XT5X4bS(ZoPHCiNh0C5{?RHz_z@%?q>-cVd>_#7Kdz@yBl?nh*{>4v<8 zqDdXp@0l9_Rq;pCy`|9eIr(}pwimu}MdjKYcMn75jY5pFB5@maw;1PDXR zZM4JS-es{PFnKB}iZ*7d23FB*^_R{$o?z4jN+K~{%d2pwqT^EU87yb{9uE-ZVsM;k4S}goEeLJD?j0>AIGzavJofYqPaeIO1Nv>It(!_iv zMu$f?tgol8cUSOP!jz`?^_nK!IlAdt)O*5q$m7~1ypzHXU6xDTH-UrER$|qFugWpv z7s-g#aH!xS#aRUx+!prrdZb{S3iFisZ3gy^*I2=1*u#b0tSTzRt*%BQFuO|KZ-`t0 ze9_LDxXJ2nNrmp@L@TdrqsQGizO`yYndqW3foF+-*NIm=&xxn;1A2>c>1CRT-eUEv`?xp$K@nuZjC!A+Syox-l`Nr|6!Fpwbk7`@K${wcq zI|$z)@&|FZ@p*=K>BIEL{-c9Sv?PSwZY$$YM|4LA<2gWB0%HJXO7^w+odljs`$R%B z3%y~7)-6R3z<+XZg!+I7Q`X9sw$^2uzO&HtWc7)0N@=^(Bn7jD>xJPi4#yohAjM%j z2z3rIjo(%94zJO)wz2y)b+J{^?RPhU=L^oXjnTB9m_3l7Hi0Lwh1CvFpz*}l;Ycu%1_AsP$}Iaw-Odc0QZPyA;GV{Fgc zfVuA**p{r}^8}v7v4j)nsN1E^`ec1CVLRM2h*yxd-RSb4>4Fy>90oNBu83?+EnEUL z4IdJCz6jEoyclK*99my-Ev>s{N$`b$L@s3PG2PPQ8+JhH8Mf^Bn0NG= zC$w=$l2~g0iFGZI?5WCfXL&7rp~UWEhKjecB75ZnQ0 zI^%(2C9K<}mbh3X=E*Z$Vp%+HAD7)wSLqUmM+pJvOWdQ|@?CmEjsJ_osl6GWmi9Hz zzd9O+L>zr_SRWVeYo31-9G`?<(j(Os2VnEDI$FB^*nd|NF&Q*CotZsjEa7XO{}71| zp*h2iPs zk$z*`u}5u9G<{!3_xtRO82^sTwhgK2`w87)i{=_(?0!s5EUZ8B{tk|@;U{WEJFmB7 zlhN=492{U!#Fevc@2w3xnKb-Bfia^_$?Hm59#fC8$CVY)isJ__E*pm)(Gz7`W-!`m8&b z1Kl`J(h?2s_{On)^aV)RDrt!)i^M{MgBT|g+d@ulpg-X$iYJ0*WnyQHe?ZFD{8NRW zBPkmBD~%Pk=>cg_J*Je$Nbaqw)x z7YJ`xVkyy&!q*iolI;^s)HkuZ%=!kqs?0p zcZ7BVs&pN?kDl-7JTSRE+D-zt718hu986MR+%89>7uv3Antq|s#Bb(=Xngpo_t+N1 zHjEzZFH#b5l9fd5F<&~Cur<;WFIEzm=S9qLv!acy5`4e$5+y-kxfv(CK$yCw~eatmpdFg zgOEgPX1=z0pKaYW{tCh8@DpLpCrk7g_q>$6Qs{ZJoS}9!jcE#(NKCr$R|&o_z}cSj zpIMs>?vj`4ar|n>*IADvRBV>l5pOH6`PVp}P)p{hYo_^#w{4^O*E+t&9>~O}vb^XR zH2*rsljeukF%Frd@+Gvr=3no44i+I!2Da^wUgWF)8-$;)NT!lC?ajp0Uy9ew`9_B~ zAt|SDV;fgTO4sbCZ_ZS-V(v(Oyu0+@EJGf8mCYL}8W$+&GCjlWIsxui#=sk+^GTHG@--!3$%uQ{rX zHV8v|N9H>m&OVNTO?y%|xVPosDfk=)R9FR=x2iVfxvweTqcN+}1_oA87IYg%4B#~9nF74__9l|9OGm>rlmT1 z*ZHWzQ<5L1t%s78uoco09}|fMT8CYy-SXQC$%xby`ncl>HBWvgvoeiv+qWA3gy8cv zYQ!4d>X?_(b?g7P!^sFi3>&gBjf%g>mag$n3SM@(BawM{+_}rNr~H8a+)s(bLXZ$$ z$7F~$KY)Pny8fRQo}d~Hs^QVvXPiaU4A;N#8IeF=PIix;u`n>d;9pxmD>xloWFgvF zv-enwsPT%Uf8cXU0+YV1pSKfWEMcdBmiW9#%=II)DzvW&#tzAMO#6bPaV_OsVI2Ia zkjpcqr}`Hijgf&-ij4;Jae1cF^p_l6#0^^f_MyU*ZM#>~Uv_jqLm?K7KlHfwg8dao zH{=NDrzXsjskirn{Z&WfbCHn(&1~U@wk@b@@-;^n#)CT>chYh11^ercu2W8GGx+?U&$_}cs1jwU1} zp@fa$Uz>r+SMTpQn&>gT8q3u&?W^~99i5|A>ETR0rhWDPo}&kxANnTx{HP|rdVk;1 zIE|8df`pOKnBDm5{R2l22ph}GYP-fj`^x^I(DN)u_zkp2Ny^@svW4pv=|>LdVVrQg z#$C!(Wy5=4{ISDxa(CcI*|xaBZL{dof8ub`9iq2u(cw(c7Lso)DuM(`8jagHl9 zyuemoFLpl@evYdpn@9V^M)4O~T93q^I~pglxXRj>K|}lc{}+xXpe`}0+Q&Xa+nVdL ze<}1l5&8oHFdFq2^iaA~f9S6qo}{=mn;2pv+7_p zhm7X`$MN(~9b&;KylouK|H1JE>0TPF#x3u?s{GOMy!CQ?Z(p=bPaXGesDE;NUgns{ znCL}qUmcgrgs#t@9dB|;R+t-(cx(ymsMP#l9M98s$l0?!GLc-`Wxdt>o)v2%zkvA- zFS^8@Z|if^jRwu1;&@aN=OMa9{gczkhDlwa0N3JUL0v^RYFtnB~&_{OU z#GzaBYQoQ(6i|fXXje>l+35A;Jx%brsz&`!AeB*NylJtn?r1h{LJS&rYnowY{w$hrtwy-ng)MT!<77vn}M~7Rwj-Z_)#zrGG zZV%f=^XakY_!|d@=^#m3Wzo*ou3ay*e)qbLC80J3r@7fXfbC?~@ZUO^tll9mVW!=H z?bm7edJZP7ca8^?8QH+LM>KqWf#T+b!Rzt&QI+#?} zm`b$c0NB@CdmW5{Z^OfQ+gnH0eRZC6aLx6a5Vq#Zta4W9YV33HAn5f-&taA~U|*g0 zJJ^I+!0^V*OJHA}ZzAwq*5G2zv}oa@tG3d5gq`JR!Y~j8&p5nMw95{t>6;2Y&&#Gs zVn2pu9n{Oo%^YpQ!VKE`r72qKt?8Q!Jx5*)qKLJ+${~Sjef7SDqiYP!Q3;sij-l-c z(e=Kiqj_T>!(FS`G_-9&O`q*(qi7&kn^}>EDpjGT&k?#q_Za*OK9R3TeS?!BF@G;*v9(44epRmQY)-#5-W$Ri`3Ejz~oJ?@-AX%55 z(UqQdEa~D2)ZQM9hdbWMIOAaAVxqJ&w#%e$^iIZEf#)i$&~qZ1k6`Z?b{yTXt>T|K zF53Hrb3%9U6XNNiJ)ct%+vWNb=LMc4B@K6+_I*w#oYalCAT)NBykV!Uxs0Jbo7Alx zT;qg`0-_zMJKiq8jlgpRt;e`#v`FswyZp9}HWt^t(NYHN>+ydOnDw_|P`73{RNB`b zw{vii_t*eQN=h%Hc=vqa?Hz0~TjM0s_M&@&(JkF|a8}f8+QvP=lx*v);hw;AxWe`vPOjhUN~d zBy$TMh3%Kd(JIYSNn{+=+jsU6FV_;ySHf3aW6?_DZL=JYBwPkoeU=%Bh|$dUxoSsd zFCK}=-B$ldtt19Sz9D+7>EBjj-TN7hk{~p1L=J1y$s-BxhulFVu*V@Hc969D%1FZh zA^#{MXvxzmC9k>}C3_54odAbWET}++oeZf>;c`h3rla4hLA1_u5MkupJhP^eLc9du=5$}LPBk^B#@%@;EdQ(=n;Jvg%jftoe_;c!mSO6#_y_d z90xIzVXJF#@lDbA-4sq-HL_mOh9lfp`rQ@I+Ls0<`V;unytnT6PE62EQ{mj;lhQ;a8sWau|5@-3S*M$v43#Y|7Ad+z&r@*4A%L4%3rl%Vx2aJD3T1bm5 zX%Q^*NONRb)Qb3iWm!ac_{HR%tnWyikONkapB07oFkj_4!{WAdjjt-4C>>>L9>Pw{ z0;}=E3J)t3>_%B|Vj5VD9}%3O<79u}k=C@(kW6H1a_OaQO-lq}P7r0&Kw}B}1zO^K zErHII5JIM}M-tKrTH*pN5us=ub@f=n_Z#b4g1{-nmo}YXB-BLHzpOP%o|T_613P#$(+;OccH>77RIt& z7)|*y>omS2IKkEp51kM%M@t=3QYL_DNWL>I<)Xf5sf)CfN%)$W*B19%F1n1CIX-snDw~(@JsHHAZQVpJYEEM{?RL~qP^)Fhg&hR@oMvCsY z{NMGjB2{%Gys~4$jEj_OK;6avrbTf3CWD`=p8FLo^6w%t$B~OS`2G(? zr|f~8W5={@ElpqQXu@Sgb#0vO%`A{1t?7F!n&9&EJ_o>-_LY4fMH6iyArjGumKm?h zzOSMQfHR1Vq4^2(QPcMmdY(QG0}K(MPe_BPr|c^J z$U_v(G0eo~8`HLIO+QrVg|bO`8#a4gdzf{B5cEytVTwm5iT^6iJ?3rsnt!F&QwaEw(6;FLz@ z^ltd0M*lrNH|ss_Q6e#8+zjd*Wzt29l4(z?)gLWrhme~bGPrkLbZBi;^elR~JVszs zak4J(Jbcm4>hRFw(C4lGSclUps4Z}KxM=6_$?(SsKAVs{J;HGSd}C<8P~Qw5FKnm& z{|Gw|_^OKR@xOZkjj{rY1v{Wvut5SLU?a&(ze!&5k`S=m7a(AS5KI73R>iXRE_PAu z9n0EXU3>RucXjQ(ch_G2-??+|+%q@N&woF=`MADw?#!Hi&YYQ1k5HGTr_KD^irXelJjGDvcmET*b~8aUjd^Ot#8J;c-;d}DV=OP0?0VBr= z5U#IY%IVZRq*-M^sfutbONLFlrE_@-en|){Nq(^bo>vOfE67 zB_uK2JHy`V(%w!kKFTYwmm2Wmj5_;M!(9bSx#htmr*a;b8Q>C+OWU{zsxbsM_sB>s zzTALMVvW23$9)$1+mQ*9ChiIYJ(+7BX~W<^ddB)m(2_QH#L(=u^D;FTPXRqY&XOeboiQ|B zVU=_)cmXsoz~!O)T?U%sAU9Bua|hsy7f>WK7*ZJTHW($Gkfsx%F0H=5KuliB*S`cf z_1yZ#(g0daUP9j!LsRXbvz$IZ_3`=f>?QcUF*q$X9BZOU25>ob3I1;bKC!j|s@D)F z0&c=Y$)fuV>?Drft5c2vJ6UC9`X$ltkD=)|WcQbY<9wM_=7WA9hAyW)jr&d;0%+a> z&BLMx4Kysuu+vyiEX>C>iy{okqK6Dd2^6fRBv`2s6pJEoNtTCW@GABoxceo57L%9I zkHpYyvTzuSCS3J#Sd{PMkH+8?Y&?}$ay1a(ibeUrA2Z<8Rq3hXaT^700#M1K#|`YH zOf|=%>)6BrwlmJ)B#WMiq3hKqI+ZI0J)alR@(}&W7`mLx4XPHdk^K7_R&fR^?eSw&~gnlN5Zd9$wyeFi= z zlki^)r}{3iyl;B0FZml%gEiasu(Ux}d`>(h0mwD)N6c=i(f)fk-DTI%Qs40Ken zDBsurYru=sY_3$Yzrr(n!Wl_#`kDbQA)=$0t(tKG{tJWtdJIlmaCuF&I&&Cs$+!zS z^EYDfa(4LHETnLv!1G)5Hw`$~+?H`?kf-`Wfwvu!EX}-SP$ttjh=*4lxnM|-B!kSi zWB5!173@mYOQ+z4Pm=KO#PE~@Jvv_~MFjBi5+wY)F}zn>=Fyr<-VMC;N)rA(1J9F0 z4W+fb$V1f>gw6x}#c@O+m;Am#nT(uyH5F>xP)%uW{waMB!`IXihy_<{1n_YTA*b}A zfrks6V`B%ITpfft9rOF*A>@=kGAIpGxdf6YPjMr`oLELrybKvKeQa<_=xw95q>;J} zqli^VQTikXS1%QNRjNRtz~es2bMRL^=g&$8%2C-imqy{#r%88~_cLC#|82;iIM{?wAfm4goUZHDY+KgXf8L)tarAjJ3`OzovnQ z3u$uV$`C=joCrluslcG%a)?F13dc|y6fZ++&{_tkMBUSe*U_pfRv~3$?HHT~1j?wT zX{i>Akl=$2I4*~WP#PlB9=M!n4btWO&0yeiYE(C2ID$3;5sF;)Is!#ikLV(gA~3mX zi84f>sOL-Y22m9DS13ab3PzxcEAHu)inRh89ZgLdfnf#-m&03xJj|g5F?2Z*j^xO? z0;iT#h>LGSi>qBuKAiOg4%_h_FFJ*mUAvroIKvGNE{F5VT!O7>pj}RcBFVPCK&c{* z!|iGlt<)r@fJE8Apg@5#I-jdTU#MM9G>Rm^h61IYfPlAFLZ7Q$PClHC3=S@*kxSQk z3@PA_aXAr|bU7mo7A~g>m7%FpE2S-Ma&{XV99#}Qhn-waYVC5OVI&PU5h!GRET=(p zRJ)vfD4QA-q>aNfIC$+5B9{{(Nom{6AQfYRIpn3b+%YjGYn3i%a|2wGspgJTJbM8A z7YX+kF*p~far#4bne*+x$hfzR!OOXa7UQU02+crIbwS#Rkp^5DJI*LlVGKTR7Yrm( zM;VmK^_A@U*2d9-8A6))(J_1`qpEtUhgZ9tyzpDa@MYCi+%}@#AqwE*CCKk@9mA6n z(Rr!*rGQ79@_v7efyd=!D!3U?J#GVn(xtd!BbU65LE*g*kBCC`*r_Sa%|E4WWB8gH z+Ip$2hwyQYM=oJI1FsxE)rm}q5GavZg`Cp%1_hTxBXDV*daFpyNoi2L45>k54NeL7 zMG;VXTIs|pq-^XEgOmGK(DbaOdTzW33BIEN$K}-3sjlESSTk#oE@vl$fy>F1apof& zAus|4MJ{`1fl|l2k+jX~cp=Dg@}le_P^zdZ5XESX4zirQDB}zYMu6wd*g?}u7ifjw zXON^37;lg;xHJ$|aF)(+WO0lmIZ`Nam>T{=HL)o!1}?{pBXNoZ4j0W4Fj2A7I4YUQ zi!;IC;BpX^8gBOvZ~~WOP$Z=%3Y03&t8fTd8+N58@oFSWu|eUPAL7@rV4{;8Gl*Qv zB!R*58`yygbM?UE;OIe^<#-8qaDcpQTwNwBLxVMC={J-n$=RFabyWjBL@uyKKHB|FCfO6YM6k`%Vx z4N@@|Uvr8_wT3Y>Q-qTqXAc8hf`KRGs?p}_FY1ST#^4+*=W4F{NX5+8rQT1C!OOXX zfY32gue{);1{_;Q7hGLg7?@~}6S-GO)G~uIxxTc9t@SuqFhfXlS{}pG%)+zx>LDzx zRC(dkF??BhBMrK$lRbcsYoPM`6*0U=8zyflXv3&HPBecBUuod+I9$8O9Xr}qYmXD5 z$R$@9l*v_<=|+#ztez6KI)ax&RLAf&+(6EA1156I3twa4;exu!l{q}h!N#y)61tpd6iI+~fl^P`4R3^oE?2vpd^pn$4lbwOQ!h#D$jP{z2ur%0 z83v2VaZN!*Ra~4=E+@i~v)jwy;Bx2+PqUj8YRq4W&fWrr4Px#HR<|4~B@0|mG>RnK zJ_ZG8^SH68HVkMZmlGjLY1`Kz6>$v#4T}}!Qy0%37j9V&962Vn{JdeQl;fs+1Ig`3 zb!y)yGnGcAnZ4!#DY+k(i=pW`<jzwKdB0TF- zc!O8SO~Ld}sprq5Q}hEAUC!2YSzrJss%xLiYB@DhG!McoUOmZa^oFkAP()vd91zc_;)I8AIUit~_&HY#=AFcSUK1GXg+HAC)s$ z5`*#-0|$d?LKhd`OV9&j&^qqpt>Olr_ zLRm#aJ%@+O6y$_F#5&l3@;+HzIY-QC0qXn94$fr;yr{ais*!_ywNv+-AIYE;g1^U* zTzSRGE_Uv^yYsR35Ccj78Czq7gHyYEW_KFhl>9n02Bz;Bqm0fgV56E6_%H)pM0m{+ zZSH67T@)#Tob7S}$?>B`t`M9`LslNz9&R8f(8^Fzn?_*z`Z}XFFUhbYV$e#q7T7MR zRG|4J=ExYdf)^urbGbr+7UkjCQ3iA(&ayF6#r-9KPKah8b@m@ItjEzq`r%6h*k}q8 z_UIUvy*i!{_o@TfhzJt)m>AZhX4=5cDX{T;CG4>VwwP1lUKRTp`q_wZZIWTf8Q3Bo zGppc&VjAO28=7R;@i8Pv((r(2*zA02dqNCI=2MFpV$6H^=uwNKa5wY7e2}NdkQJm8T$r1lx^PZD z$TMQdG?68@kQ0K>&o|E%266(e<+Zfml~3*K?#SmS&orPDNqrg{8*zUNcuO$)tQ4=a z3~Uj1`f@OXg6f=wi}PsiisPMBv^O=8Kuf)8SUq)q&#ZZSZp~?$)Ddf>20Cl3x;#~o zT7Lg9;)ax)I!E9X*YOe+wTgAn!@e1SB9hANyTP2)2c%oZqvG|KrQ z%1VJ!%q`)y^!PSRRqvwB-g8oGsV@>|N z>!wlzm!CS-NjXoBa)&&f{0OsLkpCMes&71|zOl{#^NnZu#xbK){*pNdhQrTK9qkMn zs9;Ah@JZ?)b}8Ub2}m0~cIwpBK=-jx&VHkvA?I0meZGx(vckM~E&i-KP-6ChdA)_X zFoAiB!mJ<6pHD5!L%}>^t6;8rmG*$ADzu}v*&Ouu_L(Y_F$(f#}5QmTA z&zK>p)W&*^A>xd!8Lw|af8y)_aZXo=BX;4>!1Yt9Z4}}lMVxK6c7}A>h;q#BKs`gD z?mUh^cY?aDLR~|lmVvr5K#hi+C8(nYU7;{PFXYc98>UiQTZ7(eVaDW9cxNiShbQpo z<&9FQ4FWu8CByw2B-R*>7h{bF>nw$J`b7RL9Fa<`udoI>w}SPKHI!VQ8tiO^_R%E% zJhri%WD%G@TbPph3iBL=dEaFI{I-e2Yy@+iF^UAL`V;-0kxJjU$uh85U{!HIa%1!Au&X9d2nxu|Gyg(tI z*UF#5?Ng~u1ERVJoI+d_ATH=P;1uvyD!h_u{24qpmD)tJKEzvY;mHvd=7kD#({}z` z4(4VS=7Q~%O7+wJa?mbPXqlP(`3xzKwZCyYXUO3aO^&A!S1H7|X7T5taT0L`h$|$b zWQ9V!SRpRx0S60sA+1>38MCOM(7E>T#QAH<(Ok(_Xz5Tn1ukK@nnQ>EgsH`W=_B=L+boetLJ3ajyW{>(2mx>O0u z-eXf{Bn#sTg)!m;{(J_;7%eDR2{q1s!8rY<*Tz6sDzvdD^5-9A)fI@AzrNzPdSA@r>7<2t{~ndso~2ZGhkk$F!wu+KaW&ME4VY5 zF9w*i`YkXE-n9y^cm;o+t&+N~=<lZer;l$qHU9a$d zJ&QjDHL27P#R=E>0Hj~61xjPBNV8g@U2!&lJkVlettL8RMk>Ppp*uQ5b`)5WoC@zog?G5?4Yscs^hKw(VkIgzbUkLKpVQB8q&@9&VF;8A*IJTsZ>XAFOyw3zhhQs z>WDQ7tN{HOl0K^tue_H(8}6M-jhzbOz|@dY;b5JM{9u}0vq2gZAYH%$pHoP?-N&DY zKw7?Hpc-$$pgnvi>kn-6ok@&1R1G_9$c<`nsMP0E%7nB72Bt=)me*~NN#yb6mf}9J9T`ZX8b$x$0G`F^!xld9=zqJrGmu{x^Oe+YQ}P|P(dn9e#&vpc@ zo@^MK~AQE2_Igwj=cjQAwUG#1|FfvH#=GEuE=UX#&xU5gF4$ zd`TfXzwl?`+*GPIf!J*!+H-wbVLtN*f6m!2mD)9ddAP#l0RVs2QX`aiAYcDcSlhTx zYWYcBsnkJAG@R6sCQVP3d+G^l4*s-WD)nDQ$~XA`%TxRFPoHR+7`pd#ci-vmVbj-C z^mG(u9JNYE&Dc?c4^Zi?tMXM><)5y~C|#8!x+?2)RT}3GX`hkmS?Dv(=FYiB4fYwH zO1-H@J$4;N-F6=Tv?3L-Fg0YK2%)CC+d^192C#S61>qot@I-_#H$rIdSy*0fp}eie z_;w>uz5``MIKuo0A=}rPKzLsv4BQxm$@61`10sadB})?spDKhcHUZ%M(5x=+ zA*rmVP-9K*1BF_$DX0$%)I|by2FLLmgGU<-qGIqH3bA=J5C?Z-b=0b0@PPs`+Yt|? zFy2!bFKiCR9$;(~V$2j6Wn2_6dlnh78R>hJ>|=%Z{ubaJ0G_tRsUb&dQQ|B$xv$?b zYZm?c#)N+i+9wLFXC!EMgSN|lOmM(}P{*A21F<++e?u9m@B@*FypH+4vJ)S0NArPk z3;3t49rcMp&H{hnkTXKN(B0iRyQ^bSC%*1rr8QcdKVbBC)#ycILH@QUm1+%`?yPr$ zlNwl%`s^Q0;Cb3I+19eM8RH8}dV5pL*T9S&&F^mgmIbNd-O4r9H?|c|!0IZB(1`I?5T z-^Qh8>GZVJ^0lMkCo#kIj)*={U)r8+n!y3x-fsDkMVl6+E;8eIGs+uUntHp%C=LLJ z9im2Q%P>IriJ9^n?`&9*I%P=!Qdtir0L!EmHI@_>jkiAb&Cr6>2MZJ=ZEFqLGK*YQ z1qG?Pqs)9;Jumo3Z}-f32a5?^zj;AwEi+>%lgZAo2AKz4_Rbi((1Mp0R9Ry{L8@9$ zfq7=9SyQ-X&4SdHa}}!k4SI`l4~HYm76q$J*TC_BmJ;BNbqZ3ohXw$gZmOVZqilxt zh3hsdNIidW0DwT0X43s6V#4|bsnzk+>05!E5HXV$D`;m0YaAGS#*jNZL(|$O)qcYY zQu|8@Xk|#Tq^IER*uLOP!GtsE={z1O08ac{LF(lB3ZTBe9iFv%)ziAHPkcS7AoZ_f zLZ&rmo0?k+OR`xhKwFF|NX^rOl=Fab8k%&?6k|Ni7(-$)uFteIdvdvVu-pa5h9f|Z zB)gyG`?nggX>4WyIs8Uj6r`@~C!FX(Krl&-wV>7_YboO=Fx_rB*_THaq_&B)p$vtx zh;b~6FgRBDo}$7IvCwYR-J7R~S=Zjs*xY2Ht{ylz)lxsJ&tFh`~1>?r&@ei!ji)AMb>B&)+)Yd|Lv?f}n;b@rK8Z(!U;Y_QvQGdeRcMbEJ8(YeHrTnE? z%xO}k+R7~EeuqXq5RjCny*i&cmUPP*ZjE$)D~8Wjmo^Dax&RA#hsAM(H{ENkU=ze^ zRRSiH?zT*l3(PH%RA7XW3hVa`ndYKqMMq_++nX!6*&tgXCb9+d+|uZMYXi@bu@fQy z9(M~;^Ak#7P4oYlLTMy=>84VPQI{fl51R4YU_yge;kPzrrD5!54rg1&Lajr{@6T9^ zipFRa4UH{geqT8SsY$Uw!R63VbV)~X?#2bF>+~dBJ>|~C*N0$wUkprdSxfN*i;Km4 zyf3kMn*lGe`up&kfv9HMQ7&zrEiQ~kcZ&~DAlYiKy{OQVq;u9TNPV&}__3m;LQbrX zUtWmm0tcG{PmivM=}+9OAhoaYO3D>0TPgtVLzmVe^i@MJLBfHqqC)X|&**~G!_qm- z=(fE5wz!7xwEL-OZ)q+qZ>cFNTuM-3t+91TL8?=GH@IBUWZU~kq4Dw~BQoKGn#wFf zzsn-lkAJUeXjL9eE^`SGzx+KQGtMB3=k1l|ac>M@xt?TsTT5%UrZ4~z%e)*XIVzZ7 zV{?f`pd*>wsy;Fi|-&=<0H9F zt0B8e1jWxleotMdS=QK=ZfY$mwDtO1B}< z9Ag2hJw*g1c%8teDK=L&WLvV*W84Uz4>eK{ge`5> zRJQ}*zjX><1=VF9Wf%w?1l5BSuAF4nM5*>9-)55gm_ca4Z5Os~O};WQbV{XdRnsg9 zI2%*HY;i!SO8O;`QB4OG2;0u}4OI0s<{5ws|-OZ+qPS0p%Ag@=;*EQkbn#nTwF8&k%*3V|z$i z!Mr5{Pelo;lG7oM65qI*ncNJr5Y^e9`XwkbJQ4P(@hp3=7!JQ5e5AI_hc6~6u7qG?Z6UNB<%vvm zPMl|{d_j7k$8aDI8f!@Umx%YrU=7RTSS-xSV9I;h*jH zYp96Fl-z|G{yo%=X+btAetZ+#BtKyw;1KAngZMkw3`CUO8j^~L0C zvLpVNAl)Ih5Jj1kZED^^hK|sIc~!cls8EXa`>Z=F^%n6kCi+mu|EXIkH38=MVrh70 z5Fm^*$teCcT|8k?PeNx-hw6LA;-zW`6g*`8;9}(K-e`r~oEZgk5@sY;{8)RPI){?M z&Zn&L!$6L*6)k0Qh1Iy+vxHSqS-cf%Pep~k3}c=4@@l_Qa4tib^H|7ruf+27W8rwc zTpV853b1crZ3h@bpnOUghTDSm0-oi^*atVZ&1f%6gsam5c|Z$iMSF(YlP&sNv-Y=R zA~pox-nIZ`(D42kB(zClp<4m4pN?B<(kkW`zdZp3?=h;SGM0)azcFhOaW1Uh#E5w1 zbg!^IBNgx=L}_Rk7nLHW_1P*r96NwPu8C%-(l%vWt?Jm{nBuqE1yes$wF_I8TF8J` z*$J{-h0D*MYfFhY&8GWB!wqQoyIM`M*+fQ?W_cMS?yB~dP1Ig)2BJN#9~Ksh`r!x` zKRhaXC|s4k_o_O8pz>nManHp==)5!C)Ma_0B9g}`G7QP4?ey#d!jFc=AZ#FD)1@zI zZGOUytsnELy*b;`*end?y-f8VvAsWR{W( zJs7RDsfdV}3}RS5>xy*?QrE}i$TpWwv#Jq8p~Tqy=c0;56pT&l4Ma;& zzGwuR9Dhnn2l?=$cQuu_Q`2#^n3gWM^R#N?^x;6how8JQ9g^q5>%@Yx~SuaN)%{YC;5|>Q|YE z6!YV8Mx_IdwkTJGG~aH-sJXF~3ln4t(g8h6wMB|@OEo{S)=SZ*iJ`)KIEO?cbT;a~ zB3AcA_4x;+q&i$WF9#U6AijSMi~lpyDHKYJQs@|Dgwa9z@VwFcOtvs>=c5yt=#R!s zXG_y%b{Tp)W_%|R_>~ej1`(E+%qhftb(UIY?db7(rI!7ig=FT93^U7cWLjxWix9tc zV8?f{gerI2RH`Z#W`AKNqW)eK;_-tC@hWiepM|9y3LUl>)ME{XOR+Y)5^`#b5$&C$ z94nEgoQhE%Y6K+{Sgq=`jI8ctj3RAO8tg5ZGY1S#JvYkl>Y2HC4!SU0r~U=0f${fL z^+2q0HQ%}^S^vvgA?ff@>_`}`$+I&s55c+5SfIcZ>#Q(QmK_btd;=%NOG?-Mn5of; z_}emgM-hAfYQ!%r!bpp_5AwIrSmZjzTe0FzSnzRjb$>XAfvk(&Z&ZwT*rs3!!evI z&rr>$UL~eDYh*#{DH#T3+ovfTD?oN840=4W87f%RA%Yau9T3N>4Ykuvg~??MhT2mX zD66QPxV`6f2{G++UFx^WKJHb*?pPMB2o*adR>Gj7fcPYLS zfI)>kaMnq+I2FK0MeYH=#}^TRD-U3WE8C-ChZ^}-TW^7c2Vl}(yp5ReX!IFnpV2<8 z$>Pq*Nco-#yTfPnmZIhVFUIzCS~;s!s7I0Xhx<=Gv4^%T^Zr@O3X@SfXQ|v?aHGno z3pF39k5{W4(4J}kef86sUQLRto|MzI{#%v* za|z{kiPbA8iA(aIhH|}crW_dmUKrXtT}W6ZhW}V0zGy{KEIwtrGh+>FvNysWT61vf z<>^(Oi)zyTA{^UF9pq68X;3n+Dyh1pE)C=t$nFzHFrrP9L=j>~%>C{Ob060sErGlU z#r(I?RpvPbZZs^*N}R-an_W7My)9Coabn^<8CDwg*H*i#G$vXm{e zUFHPMurNDWEU2pR8=EW^{0A0n8|5f| zWepP)pFfWI4Ufxm_1V%k=`8O-5UzUy*AjVg|kW<~YW<@bXOm_JdR@z3dsjQG*v$1mczrMd>jo4{okhQ2$N$}~Bu%J#*?H%Ba|>EcwW z+OL*cbSLrFhGxN-Y5C()R$L^FkovS$S3466v^r+0uDsbQHVm=o4cSLN9@gKb;Jk=q z-9ql>rO}+}2^KFW6+gkKPgzT|pwC1|P!|sonp?|RUC$Wb7%EYhqDEtftXZhEYiuX2 zdhJT=WQmb4>Zru6dKb!G>v`;1WQ-Uzq_gE*(MAw!$JjR`3YGn!674EijdW8-_*<(^ zNYx9k`uFLkr`S8HY1$`TMl{zF4>X+tf>S&dYVqf9jl9>YP{Wod4E2 zuhluP*Ew(0Id9fEZ`C<(*E#RhIq%jv@6|c)*Et{5IUm+JAJsV@*EyfmIiJ=!pVc{^ z*EwI*IbYT}U)4EZ*E!$RIp5Yf-_<$a*E#>IbAG6EeynqTs&js>bAG9FeywwUt8;#@ zbN;Av{;YFSp5u6q>p25FXQ1Z{@|-n1XHCy3@SL?gXKl|J>^Xn)oOL{Bi02IToME1` zuIH@hIm10?eb3pzb2jvxjXYp9zb&i0-&)^m37oE<%9C(qg0b9V8Zah@~Ya|%7D$a5xm&P2~C_MAzc zQ{p+3J!gvN?CLqYdCu;hvxn#G={Zw9r_^)GJg3}q(wS*J zp6AqiPJ`z(dQQf3nmni3bF!Y(;yJCJ)8;wTJg41rrhCo|&)Lg!_V%28JZE3e@jWN! zIUSxe({pBd&TP-=^qe`KGuLzW^PDcv+23>KdCq*#>Gqrjp3~zw3q9um&*}A?KF?X? zIg34KiRT>XIZHj~AkR72bC!9|-#zCL&pFg{4)dJlo^!b89N{@fdd^Xv^AFEC+H;Qa zoMS!bIL|rWb58J_6Fui7&pFw1PVt;mJ?AvfIo)&4@SGK%bEfB<LhyDNP6Oy51rchC0SbA0z)-#yQF&-dL6e0QbqUg*0Q`R*#;z1Vjz@!d;( z_cGtT+;^|=-79_fD&M`@cdzl?Ykl`R-@V>*d_~ zoZFCd8*^?Z=Qics=A4_&xh*-jHRrbF+-W(tJ?Bo(xifO^UO9K~oV!oX-8bj@IX9Pc zJ96&KoI5M$&d#}=Id@LZotty_%eh@ScmJF_FXztBx!pN;LC)>TxeIgd0Xerf=l12? zMUXL-lg=v9SMva#s!jf`0vW3UaR(3=$wX9_6|5A_ArXDWE`@ZRQ)pWsk+lvy6&F{iI0fAvX`wX7k+t1{PNklv|Ux&QeDy9l&A## z%q-`al|*$?6?t3E`!VVO!*wpl>%pzr>c$MQlgVNhQy)Cgc;}#d-j2&(#Vx18W;eRI z2;GAkj9l|f0>9hzRLQX`nuDf1yRU5oWPc-a+gTcRgEm^35A8XMici$}Hlu=FBaf~n zGtccu({~wtpgD>T@cRPhN@9a24M8bps5C?7rHi5I)#f9*PdmA(JD7P4Gz3wd^+elp zqH`d~eql7ETeHQ!fbJ^$1E({&yG>La^r_4BZ_dxJ8{(_e8ai{fRCo_^k#VM9s7y5s$#0wv zea9On2k8Vm6|z`;26D1I5;avnfWy728f-zmiy$=Hg&doXw@|~G9%qdeP1Ee(@1`d9 zahUW`4-T7fx{`fMwSc`Cl{4sZ3Ht3-rB292F*ANz&?T$3D`-oR3CAvw4^NnMk9NtDASLYAbG0L)baQBLgY+^_scU`m%f{p$ zT`~#1i8<{S3w~L&X>9LhAe^mn!qmSqbUTS~O_+wLvRS#bAlH(ItQ+hys4{1s&GkM$ zf1q46on}GBRM75K7PB~T4XSFZD(v=YrvG66pVsN3>cywW+3v;Pg|f^~T6Qz7HP|L& z;ASxTATKC2(XpA$$d=7<*sU|-g|lfZ8UH_4eMU5=8SP4=<(BjRn9@$cl$6j+nR}S7qws_-ib_v_D1Z?31*a|`>P|J zRIT*NLRf1VhDLrGY^5}pH<#Fw<{@d{1PtNUqs%ma{ABUzEWyL5h+8E+b1hTsPMrmu3v|2?UPkYSHt2Eg`)7U?mQXBQ&gZav$k!1fVu93SurzNl+c3_@m$FW!#?Q^V?V~&|Q^ zvGN0rNLLaXGz+$@MxL)UK3sK^CO0G2!s)%B?Y1u8!4;iYNs~KKb-M-=HQgvyT=qU& znok5B2ptf^|25d=uH$a6KGy7=7s=C2sjpQB6+MV=+__QIBa`4bAwB2IT2_V=kI2S}J8@ z%`}v8Eqi02SFB+k9`i^O(5sH+-E#8KHfO+7~PgMeVQ<=lD^N6S@E>CLcZs9&$EYAiodr{7+A zC9jcS8RVqCL?y2=LK2@85#RqCTJu|CZmOw4fb7fM4o~Xl_#&yB@1dLPOUfl$j+Q{Z zQ{!#ej5=Rz_3%w$neSPFs)}T!b*vzo*f4Uc>IMcCsft-HB_UsK7D6aT*H5A==v_89 zKQa!0Xhs`%@sS!Fz^P$46`bbMjU)o%+rb5?gAJd9dktjFv^A_g)=*rlrSc$>Sf8Sq ze@00TU0`9;z9ots*u!bs7jWpz?tZ!xU$DTG1sWO?lK3o^_C7DlubL;*oNabVKSLlg z(uO9t>TX6H-jJ!GHS;}*NH)?Vd(+AURSsgzuVknmculKd(uA#hDrpcCg@m1fxiXAr z!rm&FWY;yRXmn>Zv7!w-nJ_ zn8z~(ZS9uqJdbNy%gS}5V^Pw9%_G%4+89`+km|r4Lko(2jOG`_(xAdzOCI)TPUmTt z8>U}U&VM6_KHdZb`W6IX6(=AwPl|O1nWq?hCq90Vwkbi1$PAgF6|uaAS@~RBO&UXF z?$`jo50`XDiV_5U54vBcC$EdSl|_Y1?PBf_Vulan?q$G~zSt#$YUp@u+`y6)*H2ZN zAFra+qf*HBx*b;C#X44qR7#OKVL^Yu{OuO0Pk7x(V4P&Yejy@UrZpg2T~pbT=zP2k zqP(s<=825`%52LxX+ihEw2jq5UeQAAW~Bc_1blYX)1V@AOT<+kxT`eGs!K_JcO{nj zF(Ya9rGYEw9t#OG7GJ)9ENM-xkoq`>FM6F29gNc%_z^t+Mb-*Dh>MjJ9sHT@3KEkGHj z1ddNxzLI{f^8#e!s922Ebv~p9lENP%!)uvIR?-+-PZODmfmH9yPLYErCsy~ySbG|$ zj3h`3q>ql~D(g;$dX91&su|my@e)lnZ}Z`=^~@UEiV9~*p=l;vS=X$aY|p-Ap^rr` z^CC|AC!dI%&%vVBeRf(dX(`Z6&&oV&4g-Ujm{1Ybh0IhRg^4Qx8tZTSoI?5{P zxfrHT7a>#BY%HUV0VwoDlke(dK^Y0~7U4)X@>>bFbt_u^dT4aoNr)1=3wz-5D)i)3 z;V^Bvyepa9cKXMlM+sax_v86_f}x5|r33RW9ne`&W{R|E>d=7D_zN&*|I`9eR#sGK z8=Vax-Alm)s7fLcR)J;`D|;`fJgTxJ9p2saa2sn@L71>OvStm5RsRR3?;mA}cpSB9 zY9D5QiVX3MFh&Xc`|Ln;PprW9(ou`VOHAVg)v6?yU#||sNN5;88!kfDzX_y_!`j9n%0?c><3e8%_K^#?Ie$B;lb1?F1rG81s-I4AeOq8 zYB|X>FjdPUsZ7+d-#{pj)*&w~e+h~G7;)ai7}jvV816_rxN0P=Z^jO)T4RutSi*L_ zGKO*LlMmz#oIsbJhdTDrWFKRDl8H1#%Ok z60M0);vkG~F5*KzU;hBSc)T$xEa7cS1qs#OU@loJA*i)vL_=rd#%O zJxFm&XhKv(OsH)FoDDG{1%{m*6jQEB{JuYooMBw2N~@KllIr;{{N}2-OvK6f=@z$K ze&0j;Rj&0EpI(J!>Jjp)x{Bn^*v2gTI!jQva?Bok2!is2@k4ns;Tjf3jsJ+3W z%pz3gA7*vYB?op~@DcMb64O-oItlW>!7BbV)=6z?sq5=xIMhMxIw`c0DjDa3Pae$z{dURNK?J=|o9HSO&1q>n58DOn{&H9_ z?%%>t!qP_AW-Z(kmk#P+4BO6jM1-d0*#$Wj5#KcOH6-kTokv^0^ib7(X8&zvXb&5MD=zNRMDQpL@bbvv7hZ)7TJ3DE1{<(=Ups#LM(C0 zA6eu+3s1CH6n9ZRml?=CsNuPm8YXVg`xRMzG1Nkpg-B)Z_76xp;Iz>fgpus#BanRe`;TW@XwK$zeu(aPZj8fr$kjbTAGq` z$xheS>glEZN}JpBQO@@auc{L{Lj`m=Cgy|+DJ(Db32ayquCuVl_K!ah`243)#JJK6 z9S(OclzG7Ti6WSJ9If|^`wY@)i-fDONo^*TQFZTxZ@vTPFub3Q?YAqr7$f_x_8~e^ zCXh#kB`4FUU2Et?xZKGyPPfC!Tl7|ZDFJ-!{h9vQhG^w%3d(5lMSgt75IksiwAMBr zlK-q#vx$h=d~`1;c2Zy^%k)NL(rNMCI&DQOvNiQ~@51%`_;Jh&)e|kbaXR1r&V)jh zWm&6#Y9+|uCVa7dp1%ch4;8*R=wp_a@BlRW?pR$bo6Bcd6X-+=UlGxcZW9%&pF+6s zMj*qrrGBCKVNb%D$zdE+j+!U3)${rA8b()%@wj+Pu~>XzKaAP$iREQ2h4)$ByUh_l zgWG($9IKVvNQJ#Q5vAQB1`2wPtd#L3W_pXDL2&aSH5KbC`!e4T#D==gUn9?NXEs&n z^{ZO>`e*aIBAc6AEXi}A?=aZXX{kxno+s_cqiD(OzzBpLYIY#@2sWV8$QDf!tt6wS z9xxQqx+hX)9SSA_xh+Q*q#lYa8SBlT=xu|?IzO~DKv*379ZU0eI7WLJPpCIoB2vZx z=OzbG<(K~TrC%ZG16F-OxgMMBTT@^d6OcpI=~V};5T;`w#+C;tQQ^vCEUi@(Jsh_) zDx!rt5uiM$Kt2+)_E4N$(Z{HhVhOViiPinV=xxgC=S>s0f~{8=n7}<-iC_W0FVn8E zRJGR0nCT5-rVn-Os@iYW{U~yM)yU^(B5V(?QWES|o4k#AT$eTeO(UuE81t_vXKrV#(P{m-8EJ@}@qPz8e+eQycB3&4g4TN@GgE?frYrK;jSCRl z15Jd`s$HwSS^X-8`uW5}xDhJ3w>$yC9Up-ymIaPFny(cEp22j_)54>oXuA>iH-zUC z8J4kq2HB*d)?vvGiuj6PTEh1ljNR6@gh5zm`SauW!U*A=lehg$;uVuIrtX<6v-gG)Z8_`ktOV}fY}{i;%+jzOSa3zLmZRvre}9a;L1 z_S`Myq$t)2oykPorwBr+E`Tzb2~UQS&&6&dcosnV?q!hidZFx=x(-FtFO%+s6Wek< zYanrt7_xwbk@rI2cYaf$3jEgqXJFAl1q`AZ;jKgRGb&TD(iQZ`L$Wu5#!LC z-GMWBQ8Ii(cUDh#ch7?OJxlf0-N1od?!J6aZhCukWD2T1Xd(<{`+{AKerEv2khutoYHn-+gS%RF<|g^~ zI3{p@EXftwiU!#fxgiU>PezM{HR>DE5{yPtkF_O$RR8>PikF5vtqmZBvyl$2gg0x50dNmsrfz5k0#|cN%iO zP#7qg!%BU5p8nB|dz9{SBL}WckZ>6`d9tqYHa4q}%nlCEM__g_THhA-J&5VQ3cx{@ z4Gd1j$st}F$ul$3!GteTNSJOMOr=$y>393kB>!@_BJffRFc~Zimid< z^%@;uA5vAXlbxO~5~z0DKtU`mD=E(ab75%H)n1|1S(f6c*<@2ELF}5)06G8jvDRBl ziX%LF%iW4;j)v+pjR{iOMU>=70ec8yJRXod*swqsiQesKlW`(%L>UcJwl~K19F3DRdvYB1Ox!=zO5O3snDpUe zLl{GgF6&{Y78(1YiYQ!CCr$0k0K6(1Hbe7bR}y!nQQ+lpO~KI;-5!Cplb+2uHGn)7zwZbR+Oz}GHEaSkF$?u3*7sprr0lev0;?wrHjErkc+a9m%B5(`1raIJ z>DI(mxPKt({}pLxc+N<=rQHa+e-*YvyV5X&wfMRZF6AP<)QrCA)+%N=P-0C>9b%7c zi)$B5+shKy;2J$am3t7=9kl6H`e`L2Ct+5*q|M|hG)d7Xv6qt~i=MT^mvb@cty&pN zRk$eeZs)s?7}LbAMOOME<>Rl^UnMG{)+uJY7D3T@#-Lo5Ts%OdYYoc~ytt8{SDPp+c)Lf29PPvn4~I5EJzN!5*rh^j zi_V-Ehq&yCV8Mb&Tks-{Vr~|NV*IYOM%~&hTL=zSp|}>AECGt$=)W3C{86N5RCQ!> zb}_=Zh7rc#QA#oTjYvX$to8l&S#Mwog)-Y_pCkw-Q>sF((z9WVG=#qT*UrGd?avX*Po|Hi@Ar)d-0H;6et(yE%!p zuyb@l>IT7LBI(vL!NuwD_;O<~1G|d@lM=Kh>hkwkU6ddOt^D>`>NioCW-$(~${Oc4 zWHn>f8E$$=Nw}GXUL_2RM|ZPSxwX;idO--?KbEYB-vBX=G(k$xC6efK|9~*1$Seml zSc%InY_hD(nJi{(oJ;8|Zj-)A# zn?suLm~fZ`E7InT#h+HjW2hY`Qd}#Q`kEoOGkRF5Ue_>cm_-d&h(eFHiI(gCf$H;U zt>cZEQmZ0x6o%|G z5=J+$s0n*|A@+1$Ozy-d#+mf_wI)%bTzE*(us znH>eSHjDVlpJvMHyF< zZ0llOA|LO-bZsisIof+kI`Bi*ADsGpde?%!1%CH}P9A7qz6NiJ@t=a!=_bBY+me#V z-!t_Y`d4n_x3^FJ#cy8J%4D9=wq$ZO67`OjDCVx~7M4JiL%2F)>Z1B>wnoU*|Cr#B zN#WO4Q%d#+NcOWb^zX-{LTt`hV-9qhHmA3TXv@+9wIP3nPEfpb`7}G9FF;bZiIhxn zt4Z&32~%+_;nb<3iV{6EU>mP*F_1YknT%>teNXHUXElxtZE3I zC!kqB2Ld0o4aj(CFBb8LrlfwQPflSw5|!O!uNZhuyCLBsSbUiDb+8$CC`Wh)H`lB) znd;`?`f_U<{}v*)vqYd1+z@Z`@+U-X(@>7MF)G1^Lr}_tjVG$+7-^<4%Z7R)uzQ{2 z@24@n@rFUHFI3+n7{4?UiO9L@wi;c~7O;a*vn4ugs!$UWKfQu7_e7ExR95A$&mnjB z#8yHXYP;8ZOAOF5V?))!+*WBr$DlWF%AA=hrKI*$jQlHc^e#~RNRHP2g<{**}%i5FGv zHCeuXA@#)%6HBR7R`TUkLaE=QTZmw&{LM#I z=NVe4fG!&dxh$DH4IxemWByQtC0o8BbD9!MpQ^~@vG5n5^0$fVK{jZ=vEOVRfk|2w z%ZH{prxb;stwlyw#4^^{Y&-BDVC`?_3!K@s0=p|fzSfFr3QGt(Wkj>iDExSjGHdKz zrnA=RqLYZdMrn1XZ!ST|BT?jyLsOvov@Aog3`4L^_+$9k=6H(@Jpil~0gP|J16NqT z&*S&`W?h-e=0p>~hOBHOBZ!E!$^qoM4nhpyiE_=NJYmc?)I+I4AdiFc zKh{Nlu!h38DFTf~x7rM)R0%PB$|1QYc83buj9jX>9dR{@Lf_pZIn*jw6g_vHs33gI zs=hFThV0=oUa{~-*t1OPJa3lL3TNx$8z}wx=KhADcTs%ecS4Z$qA)YDN4N+pzuc@Q zOq_$`^`l=C;obfGwxL~l=wDk~iW?dhTV!>Wf*@Zn7J0T_8V@Sk6MKY} zy%f5g_R=!;tOVjDbYpX~EG1H^c;98I@nI@tiuI$SDbb8{0uE)Bu*51hBnS|rxTyFa zM%GBp)7I>B%zjZA1?1~HeVI7mx&B$94C{)p0GEVuu-911-klhJAR>IYHilGPI65PK zdk;hC1qHI^Mzz~!nc3CsjO-psWxC(>I~O4nO|kF5*-`SeBb0yQKW-2an?9;ySB}>u z2s+IOt|~p)4EzqsdP3*2`ZZr`aXaECZjL!<_WLdKwLYI17dew)ligb9=@22M(^Pd2 zh28lu6RUHC7a1gVOUGnklhomYU1Q;G^{SiI2`}uLAo5CtcS59jRrc=FS%~Mou}Lhg zme+*thiZ%na*BRd{a}Le(?z{KXzU1Dti-_I6M8NUBMq)l&(}ZjU!skHdTu1)Gula} zrF_g`dbzkAxrig{rW<)AYabjdM(6^qTerH=jf;|*A6FL3Ask??)-~Evb-9%_{$NcNwNZDZ9d}#}Yp2S^RjX`GNcbhJYqd_U)IH$p5kHIl!I*5@N0cSm&*6(T3(V{x_(`cB&B8B;Qz#Ng9*DFI?jIyjTSO77+B!+x?6w?%+c0!_!C4?| z6E;&{=^~cD6xVlnf=a55Tc%U*sQ|iHsYshXv|;aB)M4P>kE(PD>8OPN_Z!C?oJR{w zCW$C;D_ryjafEFj0X}dvcEar81UKHJ8DbSRM0c~L>V!??{i=MgLmAN@Q67zq8Rn2P*SBHcaT%Q0m^h6y-`o#%B*oCetkS? z)|)WvR+V)Jrg~FYFKTXNyJ)5_ZI2gFxZCh!jL?y*el)#%2##$xCjVVK2CA#A^5rLVON1{X>s zX1b2DRZ3lI%iatE&Y6RbRw3DPGNl7L#MPQ7Vi2 z>7+L}A6tK%Rvx`CscK$Q6FjMG$u?{3B4q$vayyZHA2!xowPKxWy)(v7z9Ocg7;5q zinf;7hvRo5oV+v$*MsY_t(grXnpheW0W;Go`yocd>OW0I3}YWUb12vnXMh&PSJbG`^{T_&g$nl4GHF^JKS*k3f)<5HykT!^1IG#o#8G}exR z-)8(jwG=n2Q?~q9rWYNs>G+re&FXzI$>z@?L2;~+Y8$`~Y|p`W>}G~9PhKQ)A;T9+ zP6P_A14Til6)<9uP$qTHzA(=>K!Z$=5~hr55VjNCo3Ux_v7@Bf*>Yblk~Z8(8uw&k zMolqy4#6*Y%S&K|?U&eR!+S6)+| zh`fJfl(nMRLgjQ?h2#h3jl!42V+4o!?11aP3^6sdu+fHlHnG`u308KH6mJ4sO9JO2 z-?L&fo($L?#)@AUv4BNbCAAc>#q&{s9$v51|H|YEEM!?6(-AgEKEA;OcMJV+xpk!G zLL_V7oTjVpsJSXqv zs0;8L7sT4C4-HtZp%StlZpfi(P1$xUAlw0)RTUcx$ya$S`y2GD%S@g*A;OyW*36&8 z+kF;KNL}hIP0yLk=I&S(>oe-vixQcebVB7bEj_U9(~oGuO;M<(f?sKWhvNWN=^xdF z1D2a}`R#>xop{g&FX;U-CxH(kcbXO10v&;1zoh^^%(mJsaqz5Yscv79db}a?JI5GE z%8#hN_OB=u%zWSMQ&3yj4zf z5F)U|VsO4B>J`YiaSRoh+(gUrGC+=%&M+=F$?-nL84e9-)-t|6TbDG=2Ot(-Me>x0 z(VO_~=eUHB$OiX<87~@*(CQqxV*AOmVs!ZzBl4B%Q6B3yB6U0D9tm9+E3qoRt5Ej_ zos6iw&XSEADL!6k6_JwHsinYvJFJ>P1}ot&!|*+%f6FElux9S!+9qQ}VnDVQXF?Lp&Avo?vI6{32mr zcOJ!&LL)PwA#0+-D^++OLa@2Ic%q(wKufAx5>@fXQIfAM#wL$gHN(@YpbCsVtyVWV z$|0_%zQ1#%ALVsitCT2voQflOJ}jcOtLq`OBd|lw3DncF#!=Ol%8RvsM`m8M2oAli zITSnwBfHooI*BirTT zjbvj~OPT6TQCT{X^bH5y4TKJ9R>za2EuRfyrLo4S7uy$hFnJZ$_}?Ph*2R2TiWvpO zYD1@Tvyqr6A`OFBHT_gjht-l^*P=juBDA4lPsTPcVSqcdbywF{SjPE5}Ysf~UAD7I$+3)4KJn8J*ZT&R{6| zCU$R@k;Qx+e+2^}tL*22ezhG$hMhT5ZU^IqD|GR=rp=0yuS8|Oj8!%hSvhHr&q3B6 ziM6tg+b!&;yca^@-2?tMH>zh5E&g5vf7gmi5y8`>7JKJ0fxY7hg8E@pV37;Bmj&GP zSL_kOG92#wJu;-(cG79<`Q10Mq@S8-MD@Rfg&NB%dL+%in8Jc;#jqcO*&B}R9f?2~ zO$Qx(Qf%)nXis`X2362j2 zrqWW6yHSs^Q8=Prn&PJy0ikBJGv4c{qkc`cg!Ab63rq%AH z02)rEb4|;3h1b0cm@YnarcPc;n``S6m)89VL#~VpIdQ+URP(h))5oegAD*O47Fl|T z6He4hSnBaEk{JC0DhWfbAE#irm~v-JPh!lOM+C4)M)rS2DF94AK>N%tk$t3My3 zGc}5Ta8rV^m!N^~2$RU(v~`2U3E0Fvj4k3cy1tD>d|?$5@=q(_)GzoXqU8++4o-bC zeb(Z>MLpf@WX_HbC$1A6PV9(feMSWZSx?rS2P5d0#0nQRU|aF#Kvb^Wgp$#7-Im3= z9KGAlGA2sgrA<2?V{&^Sh+Jz2siYKcj5Ybtj>7sqI8sdn_FODz&HXNcDnb$;ObQwm zA32FJNZMr@%rZ$$PwSkvsEz2@P z#Xd&jbcmmb3|>L(?vSFBI9oH534Rg!Y?@lr$)_nB5u69j?|8X{SdZcNKP+d?{*Vy7 z9BW*u*QlzK4dv`{TCXMk$vQXfAA?F0c?jX>IbnRI9`u&K{Xzw3NRWTlW_&3J3t8A4 z6B5k3Gj)g`XU{@kIdLHX@ zx>Sy&hx{H#{i@ESdGuR4x?N#&hv1>f>4hu}X1Pt4eKJ{tv{C=WMlFb}P@3&sTd|&H zdA~)>Fo|PW6p-K9m$Y$AES>7o02wbo!))rT+1NMoT+cLCn4DeJ4J0XlfIl^I%Y!pP zRz2%l^mjr)syYt$*(JfV7`ohiT0Ji<#pQB7Jw4WZb^V(iwB3!1SrNu5s*hZX)DM`J znpoZP68Kv5?UG&<%&4oKRbXk!&p<5KpGGRVV%CGvrf#H)72n6R!$I10_BPDYC6-xg zA{V!O^gygqWt=UL2sBx=y^1jZtFV9^+_t1E?)olIYpPA`YTOy6O)5zhTD>X4K1fFb zVPxbQqj;Rzr8(*vVTkjSkz>F{3$rJ z(o{T6o0dg|KcT|VsK{nFIUazcKi7oas#SWNNaY^l*TbVwNnfhql_e^f@45;9CpKq3*kCOVXe!_kwOKq0JZ3^rA>k^%F?P z)Ho6u)84Vdt0>J@`27y8cOc1kM&Hple&`%ZjI}ABSz(e!_B5LMT@U#KtGqromSLxj z-AFMMlX79~020F&61w;X;v!dTTppKitL(cGwtQ zU?M&<5yx}0tv5lgW{dp#XwE*d<^<>a?5g>{;r5LtSWq`@sF!c-X4>_b(IdvrMGfq> zwcn0a|DV_nR859OtD-{qr9Tey6eO>eRh7RkN_^ zhns2w6*PSk(=L9!N5LR%KGBL$=|=0GEQdVI^&yvibLvg+IFJ;=&>8cBYPiZLfJyV9uQ6y7ouI1WMOOQHXs zas_e2hvlX&#;$%CZ!{a{AwE@&T`81-Ajt*1F zQ_K`=8rYLE%pS-Tk2OojCzMh!F|lePzrGZi!l;Q%*#;SkOd82%r_DgU{ib%TB;ah= zc$WqY_xXaITgmCo5Qb^SLhImKXC_wIdMB#!XW(LZk<~gP+JUov#TW+pxWg1gV6Og! zx3x;f$zdPI{*8!ZZk0aUb(@1RSZ@i9Q}L?gKq=wkfY>bXPFXtf-a#jqK~41aWl$Xp zv7e_!_H(B^|CY?kFsw3Ll`SK}6I?q9zHAu)Ku9j(ug|D^E-XW(_WI9?mqZyY(N^&j zOG=rlh00Q7?0O9{^G2*Nff<$EOvmv1>7trEzF7MC?}#hLlJ==u|)DAEOm=j zsj}?oZB(f;IxMVChMzYhX%`#KsZ=-PmdPH2I#zk1#egRJuxE<=Wq;$T^m9l;_tuAj zX9$tw91cW~EBqf;ew9%csFX?DDYT2i&FTyCR2azaq203hFyZ7F;R#VU=?I^}NAwvH z_+{+5q0fpwd%JXIV`4s+=JOrKiK@GiSwK*Q-hg22PXh^o3)Ka&BK)EO?N@$I7PC`!G zB(%1M3I+9-7lJp(YCo3jpv&20E$UAh#ePbX5)P`@JclHo)56dNkm`4vu^_`EF#^bo zu9H2RtjS0ARj%+}%cP3e^mR}+w#hc!+7}?3p+Arug0arz4ZczDoe67B`H4~bTVNN% zgYnjvD$CssoqokGhBG~5o29JAdH(Hk9f4VjUwHSdsPnBfX=!!M(t^twirSA!V-&6n zOl(%?rEVZhxjk|7?iej891X^+@QQcSa_)*wX-wbtXiRbm@X320~eJ&}yUejbe)<5<^U?mN)B=;P(;V~27eX@iTL6kIaH=mrV|K$#fCI^Z+lj} z6zPANw(iOX4-IJ3eKG%#Q~;7iHJ=%@)_{_>@snnBPDay8=3KRsi`nTQSfq#M&z?aO z-%S-Ham_k1QG(n7&$xB^)1XU$KrgiY?@Z`_eqkgVLNToM4!c78R?IA%-Mi>v**1>} zB$9FU)f2{4HEBKV) zhMIaiL;F1ayr67m2fB_S+#Z;vv=>(^w;LFGrG^5UWeeZab65ft92Ri4${yBgVxa50 z&?MCC7?7UJ*LODhpEMsgCU7Mt@OGL7Nlzu&U8wDdFa{YN6NWxTFVYcc*A3p`NXHLq zWzCoYb=I!m@qu zJSUgSH)@((KwoFanKn086cxTMV5TRh@^Yx_sI7YaSLBRdj7dhvw9Ue7xq9E-CzLc+ z)=ir+vvbDena$mky7rk|a?Db4OHv4Gd{L#2E24G{r+Eh|BTNw5_NUA_opM4Rkr2(f&$gSay_`jtZW~2@F+v7ubN-(&NzNbyQf=USls~K8m>H zMoq!eZ93N(Nq=Zr7IEp6cl&r)XqL^pA4p7mZ{+@=n#=?;YoXQ^e$y;$WSB*eQyZ(s zx8U58^s5rkA?V%ysXKQY%q9SM9{K&1pqop36%~U{9Ljb}uwTg!(6At^(2We?;b=6# zpTMVKYJ;(xe(on@oAM^(Ejj+%jehX==!e;8*bV&{6#$5g825LF2;@UPe`Ht|!F|kH z&Hh8e+G`Xx^9vR3W&C_U+~d=!f!i$Z#+dhWVGslpnpMp}cP1zNMD75$$nXsG7V}RV!12FCd-@9q`7)tx4)#!?+*zQBHe95rG`M)PRy#CXAUpvq|;? zXoWE6qLf)&sOVyYv~tndUdh)lPY6I-Jc@8_beh9)o~Oaa-sS!aKyywoy6ka;pOM?O zL9^KTEo1gUv!nw5LJyb{%t%H=uk7!b*`-mhi_T^Ig<@}-ucj&C0mRJPu=x-n_P%@O~9V?v3c|J|i(B1PRRK>_ zK=eK!SD|MM6S5mk*D&L^Jp=V6@!nP0+|_n?ss2hOC8pH@^8qO3dipbIbJ3y;N{;4p zyEsbA@ru#*guqo$gsVe3RI;Hu8QO?YH`NZzI~C)aPQ`!SW#~>JQ*yF8ey3AsYmN0j z1}WUrJk_&&l&3c)WSvx~&EGAHh%OHbA@w5KA3e|DuZw=1o}HMjwyge)yl{{U29r<$ z=&-#d=d+e)2Fq!%ofEgiYQ9ca$ep53vTBBrHV*+>j0}zAzKB7*7qKPr+9oBwBhYzP z8j?W$N$rJj=SSA>Gw(90E64Aup40-`Bcn%6YQOcq{Q^AMUP^Timr$o< z&Txufk!{~Ta=-3oQH)Zfq1EU#5PG1RYI^sF{>@>`^iu6()9qa))W7hrN2^IJH-VE?s9*?r`o z{pv^@^Hd#AyOKQpp;s`T+1_hPflpPog~0;c=3?g@38u}#v`)mlq4iqhq#R6p{S%qS zvKg&#*#@fNVKk%({m`2lq@aOrF>? zY5zi3&&*L&W2I&VoyBLVXYV4Q zkqHZw{AG`=jXQstzEcL3%$V6T?V!oiN>1zpg!AchI0*6bV2Pj?Mt3F!s99Ydi~Md% zqZY|LsxL3c%5EJ&r8Vtms2#!wd~aZI<^DLEY zN0_i*LakaG>~{QfDCfyRIrA=0tU+xgb2vW}Vr10gf2{t{lr4|$8d0W;K8}MeKas*# zs@}Ae6ge8?+5mU4q|zbJMHsBRmhT}czm{B>Yea^#N#? zo;Wm;Y=)~PyA6068?{ZkGa09LGra26WHHqAdW?UN-DC8M+3E;mBsq#0iR;t7-j>*RLN}ksPm#t*CR_Tvl>Y zH1z5gNldBNJjEJasMd&(jb$>M(7!L=cUmWD;-1dQv!=|LS#nIDzBw_dd#K@fnKpoI zL9h}wA=86JoDnP@JZrVJt>0ts zFNWuh<%N1lc-Z62TcU;);Wwh}_8r&oj-{ijyZDg}54DsBqUaA=+!vG7O0zDoKPY}g zI(|srRjb?)d}m3om!W7=e`P;Z{`1rmyK8nc>6tpn#(60`NG_BOb`7Dwz-Qj^tI=K| zS1z;UY8KnG^Dx;ZusPkyyWP-G7hGuI!n(QQ-I~Eoqe7;qIt5eVVpLH@{NE z2<6efZo!FOk+*8+<}Z64E`JV)s*VKO~KuU-X9X#lB*YXTdrDT-o_2@ zl`eOyT+lJWW_2EibB&2ACFin@1>b-^9ht1hAw^fxf5=jN+Z zau21Nf|~ejr&AMSH0u%2{NSUJ=8g7e(Pnk8Fr&S=@&#nj^zZ z_IcDCZwHtz@TQd}gEb2OhGFd=^2|-rb6mgvd1g8+s0yn=3$DBt#Y_BP_0(_@h;`*{ zrXTz);B{scr|je^hO{p4xY(FzHhH%gjs4AQRXCI{s-tJJJGwO~0YLT=GP{gVfq_jr zc7{Y*t-fstMMq&2Dc?8Y$aM_keWiHq1^{=$=Wf*{s?WVz_%pQ#XTj9J4D-(manMBl zTm-OoY-KNFSATpY(6OE`bBE%?*^HMx8iRW$9kxFCV2<&L^5^*FAw9z%QU=6ZK5&Ub3wNsQoimYk-8CO+16Wa;PihT zO_X~i8ahjL+|T4s^0{x67E0T8Htci=ywz1Z(5* zKJ{rX0nen->=sf9tEMZK78+|VcnDy1RzMNA<)akvMnv_ePpPd(eSgk*JeSpL3Q z{e#Bud`AScbV&@F{F`1PU-k7+_G{d{XmS6v#E9 z#CN7y3GP2JK(ZR%c~)aeGb`v-tCUABW7|oqztes-f-6w|_rmn);-VK|M;^9%m}%QGa?Din*)CPoK*$!0;d-b4?0GE_as{7HWLy$Bzz99foIGk}hy-Y2NmhY+q^C zDjhO1wz@HEb!k8gzY%M#`7iKdv&1Vjxa&)eO`V2Yn3M(~nf8%SA?qR9YLdM|Z8*nb zI8S+@O`FLP1?m3nD*d4(M!FlZ_!otRtE6?QTDU3}?m#`&Dyd^t(tioP{@Un%<{)n~ zKls9c77oaPmX>`zsI_AzUCE7r<3}E7#(Fsbe}PZbluPZW=`Z#hHZb1|#iujO+6`nl zGdg&p)_;M2 z>zE!x$*&Go4-yY%%Mq7^5dGlO7Zep}6KG@P57@sATRUd<>+p(aW2%B&MooDGXP27` zCgke@DGm)k^GsT6#SosK5G74ME3@cd;Hd_M0sVg=%Mk!;b94-LHE(A%7pEqh?8%wA zbRyHy85%1blxvqVRQ4jM?15SA&9+~A2>>4LeSf)ct!b3wB3#@R=?eQ3g|dXo68b=f zo(^+%3+NZYH4Zeceq)y5)*xTsP}eNLcm%vpfWu;<@-*o3f@ht=Y)OBpfoy@1oEhW! znnuP_Ryx9DEw=+S+k#t7>T@k0xf|d5PG&yEHEY{5m0z4aN$Md}Pb!(Q^Ykk`p5oWc zO8$Z#C68;nbnl38XLvaBt*Np#=WhT>M;jbbD65^~ z$6(1(|IZKAfd0eJ*6>RqIk%#=?uRp=_mZr%)U8@|LDzN;fm@yLW)o`YzCf8a3BIf* zuYFk?&vrGyDGB+k9y|zW4p0%Lli{_%~|*N*HJ!|G*x-9_V3W_)2p#S(!IM+v?QO0dP73x*nyv#xJsDsyiga z)|sGwyt*}lqp5qji0L{OUEq(QOUFlDNood@ z@J6fr=cr4aK_=&ml|I}AG);@^*0V>CGXL$AhVIQCS#aqpJzj; zmH5d8CfVusn$$3VgNY6ZYh6>*T3wx2sxTk1o@RptRW)pk<6FXn?!eN0Pe-X-(xJ_3 zc%31^Lpq|AJ$!#G-f>%RW0|<gvREo zYIz(E$)AbPmor|C3OeJ}x(2g3X65MXc`Q%wL6(PlEU2bcO(!9Qn&vymYjOmFWVe_0 z=HnsT0hCt2n9qq6AZdi6ey}5Gacj_^hJr3K8ILtD9aS_*irU+u4us7Nja0>TXtYH?u5{U#6StG_t(ho zEYI8x+&m$Q%kfM!Sg5A<+NH?ruQ(k!OYW3VC+;R<2E(Ef%K3k_Jj23^EvLAmw(P(ik-nK-2}wM(hHu zgC0EX>6;unuxA1{W>4gs=p&#^$<3%rN%AO3YxGyHE07NgGsC?LN3gyTzHoI*Cg&pk z^Ap$XuU^t<@jpa+UjQXxj6$}-8*PAthG41bgfa=r!OUmAr+-ql%3bs=M%MWvBI0jTB!b)$-lpd-hn10`^k zy=o=O<lXUDuHKc=eMb0IbJ?aZyz!4K393Vd%oTL0^2;8Pd?WIESCKhfTc(>6D}2 za1Zl2FN7`Bf$K8xM=`i*22;}rU5(*Y#`ulbh^n-0OK@j-RH46fhY|$X{Ph92y5plB z%4LS$P3hr(jxMeqQN#5kxArg#%vdu_uskzAG0da7#UHb`%|e^}<$oAmJ|HM7)JqZ2 z9ROrs6nOskuiIgj>;>#5Vl-&RSKV-i;N-yO#>dX5fx|s@-T-ht$A%jS7f=Dk%CLkqia;U?y zz2RWS#ewZ1DPPvddYQb^V%T0s_*p6{ceqat>|TD=q(lmx_w5Pw!rz8G|EX1<4nx+^ zN1)k zq80Wd1pGq+bJ}|D$RM`PsjCq`?N^s2Rejs;vU9e?LUbaVy?ojDZ zHu^S){(16IQ{)s;fWDQ1*9U#DBPS}^I@g|OUEsgTAv29mQKM4zm$&hk8<|WN?6$Lz z*Ocp@n8A=V^_ymXwW1yiPk6_$*WPN3w#W9*2oYJnrLLi?jQ<-a`8~Yw^x$Ih61Azp zeuuH_8U&?5&!EGDpx&*i-Ak5Qze9R=e-$*%71mf?YeLt0wB2Z{Hs5(2>-oidyy~{5 zy#C4rY+^<_S4n@WS-imx(P$5t`Uizbw=JFlaUM>9{(HP(I7rvzspq7qPMaK;1 z!{c(vpk)bt&|@Sw34{AMR3`{dY7MT&bzUCr14=F33N*XT;dw{JUkEWZ)4u@o8E=yN zMW?y$$0O_!lNnf9rdiJ;pxS|{9Z?0Y`(D3#HO&Yz8~T4^0M}}OEw7@C z*_?c6MsvPPW0%U-3Hi3l8W1>)v6bLuLYiK|O?z?ml4pN_+{$eUF!_EZ+4HR{15Q6B z#XF`UNC#thA?!-WGs3#w=3wNoY)IYsHh(VIHBN3CzTmXTFr_NTXKKx_z9k2~MG+Xg zWRHe~GXUe8lT^7ol4c3u@~GMR-eop(0hIO_bD?f!-eWY`C(>Si<-x&~-I)AG%v6vfQ#2gv5{Q35VQZ1YchpcK1jkgO;N@h~>>A7dl#&Qy&@l^Dl+ z!EvV1losHQ2=GA{inLY|R2!$dF6KTzeMU;tq=5$V@Xzcd3|#NUB*tZMr#M@8AIMWM zQ?*Djf3*Q6gSH~sGZ8E-nKLZS@vKnvZ?tF)6vJ&}a$AR4o=;&JFQ;_Sw++!`cQ_;Y z-J7}`O)=WC2ilSk!HnE9rO{UkYBr3<;V#ioDD*0}Q$O9M)8xub^Ws~GF23~!H^vmp zweUxuCSOciP#R}22Db7?bmr_=*(~RtO!nFkS-46+o4;8KEi6q8fZ6K#oPz}%o;pEx z`n5{Ej|n`M(!Hccm8i(%!iQnvf23>SPtkCuTg!US!5l0Ly6eI}@-@17?Wsh5O9Yza zAWez%7G^&@{er7+!V&8aoXzyV@>H7M{162_hbA@@e+plB?=JRZ9oWuO=>m*49(5zW z-V)48LWA@ur$XgB@z$57sLVHHk}kyZ4IB(2`~@(-s`;-SZyD>+sC)!p?@i5`ZwCFkvuLPRaZb3~@mmT0>P*TopDN zPh?bMwBESpP5P@hpg4a-TNY7Qo4v^E@N#G9i8V-Esps`Q^ZM11Dca6Ana)nTVeYH= zITeh5J(wxAI@g>e-HgKCMXbJV8oEf@#_Go$^l?gbbDOxSNC2cYnr6zPI1C>B<6MeqXs% zF;+)kljOJF#oP%iTC4#)lMd(v#6R>{TVdOsRUrN4gUh${xtkfhAAy#V%m<^a6a52csX^Nnc&*dL29IZ5FizxlszqYt(*+}+Xn?*f%} z?SQQ(XoV+y9gU(fy?#9y#osZC9RnOXFcwDE8+ExHRQ^sOQK7aRCK}#!5prBH;1GO6 zM5UIy2evWCqcVm?E7sOVK4fI^5rq5bAWX?8g#IN4GCxM38|qKBWfH|F@~xX3dyypT z7_#+hAj`pC&JL8F9lQ~$ivA&_{f}Tyu0|kp)NL6)epY1l#By@rK)wG*xX-;IDsiWQ z4T$WG#STic^{xvh>f*VPddU%x@$&-|A+V;*9W}cEMJtC{RNBTmQm8w_0($Rt&2L~f zTc+URE+4Xq+%p+#g%_kdPHQH54X$+mlwlXDW^(O`*>`y!n_JkFs&>8>`!#)o&PIFx z(vsw~s)d({py^rOH*#Am&2UT>@<#^uQ7|2Hs0HnWPDKXSdwr{6SKo|$X+}OwsWN)6 zRrw{1;ssBSl7lIvcU^K@Eqf44y4OKkjutL+%%Jd1phz*5dg-K|SPFX|@Z(S&=gs+;l_FlYMGqX8(c| zUlHCREzh=5?|6ZCd|5B6D`!!vE4bG$yni*Gy`CC!I9Evm*mRW}g_D0Im@&+S?zJ|k z8Uk~9IFW-7zccmPgYiG}raOAg7V9Xxow5?1^8n|Ioe{!RGer$Af&~9QNdB6PN9m}E zoC;JXxHIZIIY5DU)~3cxe*YQJf6ZX(yu@7Z@dWxkF){SC159QU;R%*$vKpe1&oc~f z!>C|3>3bp~zFny>rN`!us@>4egJX;)Pm59JE#!MfjA^B!zyR|11hoeT4WJ3DE_S$r z5iFBphrbb4n}^(Ldxat%mX`E^bQ~1$ZM@HHROq^#)d9GFr@7Yg-tlLkcxRHWIkj`^ z-B-d6)Jjf*wXPc?IQF8AG0tI`p7NIJA*!bb$E5yzBdqlh{{zpyjf~#LY4vqa<@zRD z{IW049tjKxpIBCx^?5^ZRbN=B_WmFV71TKDnZ{FbwUQHcIU?x&PD@P#fs1)f-QjA+3Ko7Tdt#U0Q8~RMgh|;q}2@QrD?| zu=HTU^dJp(fAg)hsY%o9n$3O6Jihd}FPFb%!q5iL@wzm2NUlyZE82f(|B}J+L$0m> z2+fw39m7}7%!oeWm+nB68u}0T$x~8S$BiDw&wUM0>`)MiNojDtwXUPCp?VCW3Dv>< zFqJJM-j~bK5*@?6jjb%`Mc1`Vc0t*{FJi+Ghm@FmWHkLkc}I0~o}9Mwe{$Yo zaq#Rl4OI#csXzCBbmA_gifyiv5Zp@yVzuA;884lzgUP0qwd< zSoous@jZf!VE}@QN&3N`^i!%b308kmkr6nxD$2M2fm-e3M@`AMD3%7Fry2S#=9@|0 zo^R^0UBwr#>ivsZv+E1uU8rME{hr^^wOry}J&*1UN+#i9??{5LLY>^BtKYFIXtq`g zC2j-Lb8*9iW)IlN$H00zCE1f+YI0#i9t^Bm#h0%!m5sSHf zW@m-FlIy0;R3Ew&h1o<8RKPv+n^PF)Wyw@4v!P;%%rv&ipyO3$?`Afjxkd&womv&) z=HcMxyku3Rd$mbwu0(2a4ds(5f-!b^I7`|;(V_CvCQdL^8+UpDTJ(cMT4@e3&Nhc= z!!BR(eqlmG+4wx1HY|k{@iztuxm1Bo3(iA4Tc)JcA3V(DF3%i{+vy!*#TK+DZNL8b&+IctE0eGkoQM=5H^eadWa}YEkSXgm8e;ZP{dKpdEois#T$( zim-)%X3peu;(k{lBm8`*VH2MfLsuSHEPxhQ4DO z`dzy3zT57X+kHyzuqnCQr{s1zAXj-nuIhl?M+fCTJ}CFeLAjp~$}Ku5_sc=K0aJ6! zPR$LOnj1PbH*9L|rK!1%r{y-CmfM{FcjY$g%5C12+oCI1+LbHo%8lsCjqJ*8-IW{F zmD{E(H@Yi#c~|a=uH2PfxvRQzS9j&E>B{}1D|bUz?#8a%OzJ-6}n+@{lWn@`VeIXyRgdai7GZshdb zPSbN$({p2|=kn8YthRpfvvZfs z&Rse?ciC(}V~=1mzOR`HQ69l!_DBgQ75=^K<~;)ETq)HfiB-ikvnR-Aph=rWw@16? zI=NjWB$wX6D$Wf937H`c<%<}~linf|8b8(2_zj`)e|m1>_IR|i?*)ZBPWf}mff^t1 z86N$EkU!M8Q;vquQAXg79BXp7DL*(h&dnV{GBz>__HWfd=oU;%dqoy(JMROaM@iof zoAA2?|NN%T?-BuKe9mYX*i7v#;!eNWPJ9!maY{lwx%S*v2z`x*e<>?~Op(!6O#LB0 zb+%lqTM?n*0qcQ8HStmcxM;YNK)Cx6I!o19M$%u);sX+X4`yDjm1|vI{%Mk{am?TH zrZJ5Fk>oMvAswSKfIoy^%yZs^Xbgv-KfV&qWOt>0a>7#QvihNY<$>?FmU3`6q-hRf zYV&l&mV}f_XI8?hR#BRu67YnU+T|RKi7MSp(D&Jr}J`@o8Iof^~$sYCjas26_O=-wm z-`uJNI0XCZ2+$)Ki0-IAz84Agi~7NaV{!uANN0a^{9KZ9o9VbFEwNEUIt{a$XUxhq_taagD?!3fh$5AJ(oD;!FA(}oAxtCjK}E4y zm3Dq`dkXBJx{orFT|+gRRWRO#9+>$|<|fgxfbv@^2bi9px9Gbqd8$>@Ojt2>Jp}dH zK0>7Q4O713QxgS2SRIj+4pInj!vx*)^-_+0kL<_D`TF~y#S6Ef*i_a=e z09fv#G2H7MK&e&hNYc98YTI2a4k-E85Dr~b%NZMbgYzFn3n9vLleDC;1>dnjlqDZd zYJAl2PhdSS?Gl5N{TYrRsb_zo5u^3rr}m_Na}j^v6|_b?ZhIzk{7=$qizDw$8*Z8P z>_h}l1hpwtXse%!*Ig%uOA_mjY26+b_})&txU9@i?jDLL4tw@NfQoLYgy-+ z^tnM-n6-NEB6Ousz^D$np}a#oj++t6W&yjCI&z}}r-9!0Y2Qs5|14V(GYB=g)a(Xv z4mx8^f3au}`Ow=Pgw+#R5BwS9!7JWEqGxdfCbhDjg>BjMAd@)I3jlMoZP{N!07obo z7fX;!K6=bX*#{u?r9NzytSe`30%ZM#p5L2DaxQ=q`m)(+*hp=>FIGa8%#z$I_w&c+j-jQ;bJY_&;IDJrsjbg~pDKe}~t@KGy z;0;W=Ow3Tr_ylO?(~9e{81dAideg?N#Z8SeabatcCT`N%*>;3>Y`UhrgJtz6q0}or zw^y`x{saPhYRE>2 zF=!+G20eK_>zK#&m}~z=A>uvL-?)^d+ksKzd=$TZL(zs`WmwOyMNt$`z?yue(Q1W?i|4cc8u^!iO&lu2C z7|{Aww>&*kQ=7}=H`X$a1#eo8CnM#b6E-My@YHGQX^lgRUr9xnMze@nw#~Gzmh!cO zJZ{&>(JEUv@G>0a%j6@%Y|SSc_{5=3uCjIR6XP~h_ztoi?Ec(ckf-+okHM4e709H! zSSGV)`Z!#2ws&Q6fZA5hE|4wV==}Ya!3r^7#gA+o(1=}o1xEW|SL5{}v={}wABimV zCPhRpE-K@p$KqqJX->`75igy1Yy#|GYYLAMjZR`nCg?sD%)7-kiQPd29c|GS@%QeA zGrjhAqejnqKQz9)QR&X6O#9^+yQTFodclW-woT^sa@Vqc`)#~^slcvX3Hk)BT2qGf zoxDj&Cswh~l&;Q6T~nuaP3t^l-x-r8PTQA@z52=(vU7HZhe|rVOo$VnM-Dwq3!~(eUVRP-9cEC*ZxXsaIXkxM$GT(CoMYk0n*-0 zT@z<+d?;b?dLIq*{Y zSB|7M4Xeo!r)0A*Q*?7GDn2wtZ$|9d3eZ&SOpe1LU82#jASq9+u73iAa}oqQM7nZV z2>S>K8)&szfkk0IAJp?Z8Ss41(8{Z9_%RT3S}vj<89cd~LBZZVDEt;No|2+%2@%xW z&tMI2QJO{{&lX$LwF0U(I(3K{I(8A-HX)!k%a$$MeE`rtE{@RMKw@guwuFQ~uMtWd zk};&s0jSk8ltzAJS8NuRzsN!0nCiAdwQhVd9wE#K!Ag?jt}>ORZwv-i)G)Kf87DHz zj=;>gMT1HM4J?9dR|Pq^5)JRiwW{>xBUh$cp7J-ZR~QOqTZ; zY+(b#Fq#_LI@_rRQ!4NZ=H6&jz-?-&ugyaR)-uZ8%WZ43(evA*lML4ssrRfxhHYz& zt}ZH3KlnRA$@USOxHAO;VFId48Ej=5(p6RaizT%&NFBu&v2ZwCpr$=qJvuisg(a!P z8D~lB`6yJmhLDhgcoxD;n`vwzwK&uyZi8`K}jC!3I zoI(9~@?ZLK8Qx${(7uWW*Q`S=v4o3PMxnHpXL=Ydfk6Hn#|Yv}39$*+8_|Ks)pQF5 zc9%2R^7T=HGL@@Hdfe*eITtE4H&P)Ym|f|Qu7)}sGBjTsO0icNh?%s-oQ5x~H!{DQ zulyDn85N}2P5IsV#mhczApBkraX7-9q}D=;$7;Y6HOS>yjtz^vR>o(Yh|jt>vfV(f zw8bxm?-pFlDH#;&hvvhU&yN)jSa~M;{vV?_y*1@BQmIVSTAhC#jj{C0*sXI?QWv5P zVt*Fy56_&d+wvM{_9UEM-wi^})>fIbwR8FY#Y#|(<@g4TEYX#u-!S-3 zlye~oZE&szySPNjph>Pr(`@ihK5?5`2}#FhfPZBO;TAroXm7Lkjh#VEv6@n9=f{gO z_J?A@A9;OC&y9<9sA*Jz1gs+$Rxmegbh;^cT-Rwws^)l_6%TyTckV6S1^&qgJ| zxuPWc2b*FCub4cdt16c)j2c-fs?@JRR!H(uVn`tyRSJGynsT%>Hcs{iv>yBgQ~OVn zLgLJ!jX*0|#?L~YmP5}yI{99UDy|SAx|V)_dT`STI!;SR;8>z;h3apA%eTJ|$m*3$ zLDt3KYL!EywgOE_)V!|)gYsTFO|(JE+@Ns>+-R);G9CG(8e6?t^51uA7{GmK=d=gU zpUbB(6;7^|LYdWDX7HV9(ZjI;r)laMVDdcUpo-dftb~I)AwWr5PYm3tseVE1c%L`I z_KFOW3_=W7hl!%$c@1TasLfLJ)5ll^dj{LFRYJLUtf7{!ZYgKI)cRP&h z)ilML$$pigdh05HlK@GWqxH^n@HJyYEICG6=V=4D8S(9w^_cbz58)6G5BOv=qwj-F zv!iadmOFG)b6)@oaDe(r?<4Uma#_$}2ukLDt=0lw1X(K2rzG ze(UL>)R9c&*o%7F!XDs}kv#hIn0BZ7LsoI;MAeg81Z`wjqJtZG8Pqn6Hmx{LLIkI3 zS4y>j{?l*ppx?wYhT6Ijs*qtg(?44qZ-?cZKViBX2jy~`B~^BHP9DtuQxG7*2N%g^ zRNzTm={gx;_0h3LiK8Sxm!fJCV*G!RYXg4oDTAw&SZcM}2yuQEY}SQt+Gfr~>lUUo z+a*ej){kY@uO<{M1K7f6M@EHXwi8Sa=zNr=C)zr0JJZ+wbqu{KSxMO;Fo)=`V=ebj zB<0HQEbn?A5%o_+#H%IOkOlx+ln3B;u8g==(-@tWgT;1QWXhBNj(^qtk|K+TwMcBJ(+kg z&U{(HZHNc^D3wf5p5VRJ*Q!vR_j>;&2@-4@0iLMTkvWhzUC}Ke`P;?iU*h4N&-dGu(bGScfBoG@WB5G$Xv1g}5g|9o>O#E`Lp+ z@X4qSIAk9r8N#q3I#VCUkaX}BWLM+71v|PfVWmYK6#HXGJI1dN*(QCg%{(q=9#1O= z);`*UzxmO|u+!$?zogTH9>wjz!KUG<^nTX5e=1Ku3iI$6L0D>3#SliRAtXI94VGPi z2VGC|W0%(Tn?p(Uw@ksj@OPZ?%0_XyB~)) zESP5Ev($Tz$0UCY9*ccg+ZCi81aB`0DU_2tg+ld6_R+$r9l1BXBF!KECXXB9?`+()m{6zs1qh7!_=KEx6;O9qteEUj`U_DtHJ zPo3#^2uX_sX=_~TLaE*15r5tyW|%`Wgi zLFUyx%m{>#UbIIeX5s(Wk7Z7_>ToW_8+QgwCMZi5NxRV1n9ne4bYOdNPXBnU?n)ED zxl_TJ9TQo*=K_Owm&&+Xl1xry24g-$i_jf~OFXL4@b3}iPio_haM9pr2V%TIfiRuH zjj0ZhnzUd6!r6*bSua7_zDU9XL~LJBPgqbI=R?7QnaO)hcT4kFLK0;sZ}WpggBEgz zloVD_!>cf{y;BdJupFNfP&)o36z6c2SFEHyNqt~_-tn|u;*1m9m<8Ui$ObjGKL_%k zlY~ulrFBKPY6L&SM}`Fag@Zux8JwF0Sbe$8Itp@+hj(N9l2|#T)ye#Em_ICa$U=C{EU(J)*B3y1L{3~_iDVuhc|3BfhFuB`Rpq*->=<;Vj}JK;$FK`l3^imi!^bp7{q z*7`e7W~m75p5yAM?g>>_$@)X`uy1ReQL%uNt_*%Qc>*vT83HrRUKZ9voQm8)>61&N7uQs7ct z#a+%-gdQUq>a{wEu)HGNOM)?G6L;M^ds_{2GY#gYy@yRjuT43Fg!iwLzQfqlnSsJU0)UEx?}{;uFDP zR5vzi@lVA7?+Df}C6Kz2{qC5@+JQ$)RDyyUC_EB1|HJ1QYh-!FRl876PjgS?|7r00 z$>B;{h(3nM_}HL^ay`~mU9I*hns{1_QJOni;C32Lza=`^CUqf#`LYf=#=np-aFSM( zxWBCB`4mHaN~@#Wyw?efjZnz{cn2-LR;JESt5L}?XGg%3!zeoKz9B2|QN6eY*%GO$ zRbaOqlKzjLpfAMNQ>=vCPSroD8fQZ8R}jJ3iuzew{s|4Q^mM7UTo+DXi+(-k^M(cP zUo-kS4DC1~VoL&HYQi6YEVnDR(wfk_5#p8 zP4ciseN@IE(4orTnVuDm=s=a$VJocRiNEA2D z7C-)gJGmxi$w>=gV@l)t@%)NNIr6egE+tfoRE#B1J5sHY;F2&Wa>+WL+n9wKVkT2N z&ZGs8Win@kJQ>_V4dZ(ja&I+^%I2n;hPq1A&~jPEF(?|WD+cpqQoZO1to9%AN3N1M z<3pCg@PA6J&~+tGD5-{}4iw|JZowAL;WulE?T#1zry43454dPt`WpkydA)bxgj@iT zVHuNP8S{L_Yg4m^kCl*OS4P+-Wxpmr_$kI45|(@OR6^)L2>XYC%pHTOute;6{KHg(xF1Y(m0$(ljAznof2_cg0h6IsiRoangOx2{Ev>mDEASJUX6~%}3G`dfqjDu5Z*OhtnPPU~jvmmbq^ooN8B_M| z+Utc1!DkzJ2E$CyBLO$(+Ts4(L1d_4*-i)aMq~=f0@VeOaITZ+-5o`rOy` zxgY9tKi22|SD*W}KKEOF?)UoKAN9G#^|_LUT&^Lvb3<;IhFp0=uA(7V*^sMh$W=Gw zY8rC)H017W$lceFyT2j#Ktt}qhTKC9xrZB&(@TM^IXvI;D9Ck^l^ z&(LNkB_^jUnbu0taC5;p%F+C0e$WSJ;+bP{1Bp;yk2c}9@6;ehVGUOWU+8jDX~NRP zrhQTCWs;@mI8C8i8mNu1H8BUF1ZzjYEN%~YB#`-6z+}qB^Q^NP%tQeBjI16A0X0MU z9#xp7ewE29yvyTPj2YROwiFYZ6U07Vnh{Z?rBG3-Hcn3^1{KXZ;_q7n8Vd!QNt#U64a6`>f|tlB*kpT@C;)(FM0<) zL0O1l>%X8nD+W9&OekPhN(%Qw!PZcx3k^sdK9ol6f$oat3gNZ;NXxSh%UK>FaORS% zdeOTugTw85nB`cX<@h>!pR};jZp1aiHHXGU4@XcnydQ_q?g$_9cYoWuwcYttdt{{~ z^jy+18SXQw?Dj!yDk#bZm2Hsd_LK?c6}~ zKb`Q%V<5No2y(h@P8(>h2!DSpJGvHso=AOQ7z1obQeWvDWUUO;+{(MgxerOxIqv7u zW4{ki*%ls3ysL$DH&35SI8ojTcQfQSDbS^+?0u6@p<}nD2}7I*wi|+VHG!2SpJO;U zjfQ7g7TJn;ZwU(B8ZMs*F7;Tb%SYimh1v!U zXQ%Rwp&20XC}8d8IDlY_WJM$}B^POQ@(dQ^9JT6hTg_}R{fx{9g#aE0Ri4)ac?z|8 zIGHRR1Dq?=%y2Nk{zL}VSXFJf8vtq}>|9)98=Yu7k9kZ?Z6~7@Pauoq0<`zuwdOMz z+<}q$gF@7_+j^px04h$>VF2kaW|`W>ynuOroH{U9|KbvAdLGrd{oT{x1ynGe;bH#% zZy^hT;#Zh;_&1vlpN2S-tDBA9k3nBPO9(}BC@r(&Pz#l~zz}(9rDg2yH+=L$FJ|`D z(=b&}U@QnaEV1&mX@)Y6c2jZL6$~zr8lG90Xv6)X0c;C#0choxK1$h zB1Ou)cUB&v3gG(Fu~C7i=i}qNWsL1cksKU0gw{dUF<#F6{s0@)9a@7>Wtyd)<9WNO*T3+ zY0f$5W?R4l$z_WZ)w%3Hnd$Gr2;3Pm*;rAd*#lSovmwwi38g`H9Hw?=nhe`D-b|?F z_5+!fsS&_j@-4eJFcAD|j{4v(gx24=9ew!T%)7x}6L2w;-Zg$iI#cW9VPD>VaY`HH z!jMF~S|=Cd(uc%v_?|ahYNB-Og}wty{@XAMv!6kPGiefW&8O)u{_>HlVQJg3DvkxkzQbd6sHzqe@O4D z4i_bME^4T72+;W7pf`p3x+YV6aUPFv_9p35^E&IfJXSehStXH@xkI=Uqs%$HbfFeH z*-+itY;PyLi6z`3%HOpMH1YXcyyRO?spWKb2Gv^l^M9rOUNAAcSGzS6=!hzU49GsS zNuk!a1T}dysv&o;?`n{DC@ONYCROS2PU}d&!s|cNlhUIkm{!)c36AvF;3o40vQrgm z6jx)ObwODnAe`zo%5W3IIL~uRD!T0=|H4X~oLVGpPKu6(eT6xmW2zHeLAmzBKa<8; zF^WM-(zQYNV2qmt`0ytq5{1_GbP8_tXFtkz8V%+%-P*^&74G!vUc<#Ub#0~QBdf8y zJS$Xw^s2D$vRccf`pjlR=H}Qg*8BGqc@r9!HX+dC+yfrBepn4j>EtzOc^PN??3U%N zjV=}5x^2mv|8ZcM<>}j}o<|!;L9{lyOA(ACJsBaaZ25{0!Uz&)Zi7b1Yq8OjQtIPk_e^m1UpQV*u#Lpc*}(O6G~+0Zbrdp59ubO?DZls+n76Z* zuD>DA7AsweV3+j3;I1>!^VttmD@09qe#h|5`RMxDak##eEHkB_81DvIHLz1U0X2Bj zlalH&hLns3*!PV~>pXfU(flkc+u%*1siPr3My-e3p1hBT#H!93O-Y_+Ab)?+`tge4kL9*i~* zP^K(!mGDVR;iqEB1AK(xuA$8y5uS=v?^G|sbc)V(u7*sXj_Z~b@?{6A*Wkz3= zWjdO1_tj1PTL2d%&$^W3JXL;3_EEQh^P-+9(A{QkXthxk+b&Qbubg zvJf8leqa`I$+RBCT;6f6C1S?uFM@^DMOT{auxjRV6TbA{F`pu+V!ppK&o@a4lJ8HG z5!EShq=A7nRJCf-Pys-^pMKwEF`N@t#<&v;)tV%XLJH5jNcF3`z{UqtBg#PQx|q-x zj`Xxvw%UVN^#Jm%(J>Y{yKcm@V!r_;?@Smod1mY6{ie*AIk~5aI_^$sy>xvVl06-O zLMl1R*oM&3+Zd-*<_TAGK2zg;E`;mCltu6AYVl3S#NQ#&O9fr8%$JVLBnzetCYZB1 zmI@oM{Xn?)ibqY{Yh|YJuN04Pzd>ii!`8;8^A5b)cBM3zRn@NW4y5{3Dsicl%G3}w z@qDSMd2$q=4xP44WeVDNUqmSB>R{|+5CFTnL7w!el&QLz#Xt+5cH5dCfCKrFX{xo+tSA4fm63DSg2j|108RZx;b> z%@{U`^pG@_J->Gf?C_!_*Ov5`^|>;;)PG@ zD6(`uGI+Qfnmj&eqx8#V(Um0bM;TuVDM1%0+3K#X$Os-7!7ho%)MBg#P82lW(VdzI zMtx&GSa(;tDd^=b6=wP;s}H4kHv1E!5^M5{zoIZ$^rF~wB4+biVi@k=ov-79C+M{u ziQ1i&tbL(YP8I2=KeF=w^h(JmGMSbUJUk>dec3?|sl2x_`cK_U0V_;SvxzaF)kx)Y zoCnomeO(=U1{yZ2=(?5RY=KTvwFH4mNz#1sqi8! zBTuPY*qr%^zuze$RC4`pUN7rHzW zqdf~5obEi0-|Dma@ExAyA#X{tHj<}erIiHM!!$V>8g87wj`Q*<)t7tV?Hm!7R;z zjQ5fd%BWD7Twx=uxfB|?|U}r?+r9`Y$uTU;{dK~f3lMwtoSrE_*_M$0#~>5 zS%jo-^tdm3lSVC;MOyEv_m`J)aG^|n<9NQYo(ox|TTX@PmUA=^af_jX+_`Ce{0fk* zi*&}zcbL!6`9H{ZeU~7nY^^%JuT;C0=lkmwk(O@Ol%8ir%2MaX8;Y{S=OW1yqIqP9 zhHZRDD=Jn=AkqHRtfs7zpjGWg&4sWKAl|~fO@zsPiqs7Z9 zuYksASGpGRZcSg}I;Iq-8ty`Q=f@CJ_Vcu54aCAHgs_OKJk1>r$6+2bgT6Xn&2B?B z1Mw!#x?TS&xwYJw@ICzKvm#3~kXFl3kN0sxa#S0NX;{e~^2q>UUOissI zy;_9*Tp2OGN9(-{>#05Ew!tqsW&`J`M-FUU?%=HHzXx;=Iy z?>*4Kj_BTH!dhPU;>AADrX)r9Hs~nFmNt*M8fgq=3e-*~T{BnB#gEYE?er)YGL?Pw z?>zO_VtJaMY#huU0OYK39na$4r6L&G*cElFSsmUw)mQ=a!F=Ww%wT7OExiPuS7Nburawwi%*MW} zG2D~9GW%F5bDHbFDD+hUfaD%v_ML*YzJ#^58Rf{T^4;ji&4CBWc6Zhumgg5&MR?*w zc}vmh*1pVkK{63x&poDV*e=ZBCT&svLJTpgjDueeReLKd5Sz`}mX~!0ZIyyb25j{8 zHD0oVT0l_HE33&jT!u{@6jaTh;jG9U)Os0RJ5f(PxfGR=D~nFXhJZ&4?&ONc$t<nk{)s+$(UOuX99o}F`|uvr7rI6~>2 zLU_vwelz+j2yA~3uNPMn>udB|_CSS3g{6>-3$zR_UeLiQ7RYYB72y$Uf8}UV7p2Q0`DOuC|9{p zv_`{#wB9{|)m*5jMZbN`Uw>ylcPgxO&Q48cH5}csVT>|F;(i@8bk}TZ1v7$;M6*c}jL*c{` z{iNC`vuFM}{As%kC-%Ku1HfDYAKpFUmv60Rb5sulUwbAyo5VVqQ9O!qo|^_!yN;Js zf=+!b0)V#&q}28PG@awl7=q~qSLOPom`QGebsw!4IdM~xZ8M(gV^;g#7|dV87wsas|1)dxVu*$JmbBZqVv_6t;7U zA7De3blp`W_!=ddrboc%v*+K|5Iu>@4V|{txDPSEw-ti4PcY13JD9^-X|jdaJGjj- z``K8;(MgJ&X6c#u{9{z*-4ubuk_n-xPzb8D0~Wg|z)->6FCA3*3S|6hq6gzzYYG({ z-cf&BhAv;E)zGD^tRDV>9{$Vm0oMyAyPvZ)iJ&hMSDznWSvzJldnI9T^?e4EtS^_4 zOzoO6YU^3EK<3RoG7l(Ouh)O?U-G}`Iwd#B+zObG`6@*kWz{jSe|`Tn-Ik4?KJ$e z7{#Hf>^ZD#7VjN||4AH%D-lw%J)IF;tig?Sa2Q`z1N#XkjX|oh{{N!{+u~@OBTuTZ4 zJEGCi$}y!K0krThg592>K`80UDod~R^?OigY%pn*J`>g6j6T+jj6bZ={vruibhPph{KaEIqg*1fsw`ipwBtb3>PkO! zs;6<6nMOQI5LrGO?Or5pZGKb6c!_as6?QxQPqOUKM>F-EaI_t7j+vh8&D2#m`NN^6 zxNH%2cTbpypsV)4auEDO?IonioSNgw{PhZ2S&|Aflcb!E#w_34kCX;?^P7$0T*J9e zn_N4I3I8Jnb5q{B3^3lR;vAZChd5_tF;hb$q>r5~VH!Au(>%Qe%93DKGObl9m#20R&D=F6DDuvETg%-tpLplKISZBe6{vL0xOJ zAJu4v52ltfaJ&&V$@V&uJve+twuQ#E7%%u1Usxyn07uz|uP}yr6u;Q4SH;lNJq^8h zJ)y+1TVk{2qu`Qf^y+K%JHE%+t{<36d37e^BITA>L@N0 zTHQwlu3?W6_$=7Ned)Wi$EF7H_IXiFlO8#!p!651^>Tl7#Q3I zk^T}H5Z4(@R5P8x+TRx0fj_FCGfOL@g_{Rm?eHh%v^RMZyxbvzU2K$W;Ndc8`L5}< zOtMk#!X!182M6|TUccxD#~Fuq_e_~KbKg!{yd<|cuE(LMe+`yw@3Cs39V;#>YWWmx z84$bpNX?P;q*Jkt=^?tyTn+TE{(V>8w0KBcOw1)O zg{|SqXr2r$q=8MSm&)taeUar~l=3FYzA$dq4NKByJAMc?D^Ul;;rZ?YPkRnwFF1{{aq~7xgjAgV$Xf*8j%t}(0H zLT^3&k$x=cUhx;Q;IA;H3L=Wc5{xF@`b$l@m6}wEqVPiYDX=iqPNaz_Qr7gM6QskG^IyE2iq@?nlJtmFo1MI!~$!2m&BI)eT8Atf&Vf+Nb}V zF>D*hAi3DAFSwWy+>-Hdv1m~n^a_%zi0b2-XFH0UU7?%dearhvaUHAO~nX*Av(j zINn3S->&uu;v)=xU#IJ>#U})wMcKbJ$mBP1^rAMf9<^!8M-IcO!QV*6=MFu1F_WGQ zV62KOJt+Y<0a$*aUh!X|=lhj#T|068gSC>176gU6e7kQ8fR`D06>) z^SQMcHM}}(Fcm1*ou5d2X!T#q11H}&yJ77!)3_k21~47|2ZE&#n2(D z*|N#ruc1RFDLxVcs-Vjv!``6dDb9ttz9ZyH10DSu-5*p&^Mg?%UDfFLG71$wO8Xzk zElrQ6>@F>IlVrMj!%&>YcoPw10@3?f5+ zY`N&t5{IT?tBb*naC$C9i5W~e4|4EefCb0-%r5A@$Yxp?czJc9zIwu#>ZbBSfqpw` zvDaV<-zAZ@JF%3Oj!4G9npG=H_MTVx^6E}Hu7!ozk-2;lF~m1UwZyMRxO~Vf$+at) z`qu3z`FlP!xx6H5H2!SPI*jyBC2KAfA(@**&j&JA&cr5pE$|0njgRO-QkG?RlZG(H z4yz5e!uDQ9v3Z*196d#A(&>cg7b*wAkr%tA_&cA!S?hz8@~DOAK!(r8T|w8~#pba$ zg#`UAh)_}p2+_drznQ>AK8)Z97aF71=nsO3Z{qvYT}SPw@_b-<6NTs(bn}ASeJm;a zCdQ6d;n{j>a^-S;b(Idso&)zzjh}BVcVpL>`wa@PTWYU5;MaQa5Uy;aSkIB3%Tn_^ z3FzKDvnSwOkbceSM1F?^XHOoWxFOHmIFTLnd%`th>SLGjo)r_%8n>*pOnY#zYorX^ zg-iy_564W~)D8rRl&}M_DyF%0>e?&orP;7eDE%FX$xW320SLzf%}^to1RuFHnPEKq zX>IZ^rZ~<_F`@SAJ@+xgf$1PBTvVt9c^E_3%#;yTWo!IS!=wGrdOVj9FfMynezaCJ z&d5U4P-eqHmQiS{mGdCRad4y)E?sB@{TA?WVd4?xI=>7H`W^OndSW?E`O5l+OrPBE zQ1D|TT1yb*LIyRwPl4+j0^-()TWzY)ezm}QP7Z#ReS)$w$gv_53RGW;&RVU0?(q#k)PnBW79Vz zjyp6i()N5aZy8baLq6prASJo;_~oorL!2us9f=#V+Xe3q<{Vy_f0m!0%G5vW&5aeM z_iFKCn+3-yi-b2(IQ#~I%1e43$V|Dt3pL=az}bA%hV)VrQV zK^HctmO}BiELtbtk(?Y+^FEV>`qR_$U26$bjStuh!Cj>hK2uEH7w>YWC&g^lr9FSN z5&wXXxG5M2=L+PoW*DbbrQa9apPU-7&TkO@V~&r&YO)d7M>yBd^C5BBSV@!WR<-D7 z@#Q7M^O`y=LqDDeO5Yg<)>>LdQZ$Tf0pt43eU~I-CJP`fgBNA9S%#-w!7q02)$3_n zdKkC2M96j4G-bNq-NNO4qZ%oqn}sjv>ZXQn>$HY$v)=w0tTUf1I>-JU-}^BsDU_R1 zvh2N`IS)2u%Ux-g*M#PIX10Qgx}|bjG*hqmbTS6tg$yq?U&J}F>+J&v=9IS5#!I2V zi?ufDhn;BS(ZMkhrtof)5d9dt`MXxv4*7*~O248}A16N4_asE;8KN3PHE!iuMSQ@M zf}#06Xx<5iQzi#P)JwjAR<0NJr^>S(e~)G=kEb}0W_RWO7_A}eGo3za$IS2j`GP_7 z!+pqp?OF^yLXphx9t3^%P|KHOd@>?>L>4fK#U%-5lVq*Dqa@KZ$&s}bW$pGx(I%*2 zV?VegE#U_k?~LRN?w~_fhu%O9jtxL7hjSQXCLaD2yj?mbY)6f>3EKmQk|vFhGx>)7 zd3td$VlvXzwl!omiasoAl509=54#_aB0ZFnDA@`xM(Fhr#IGS}mS{MhxiB1mH$3=t z0jfIu{m#aNn-=wv4;j6ouTzL|ZN^X;uG1RR4)MkgzwR zV09`Z`7PbxYL==KJ&4_r>(d$AF)>3ow)0nT)m%xYH@j~DlW#EYAgdSyka}sib9&9P zU2Ceq&Vj~Urx%r$ts1@ZEb24CTbaI8T01vkh%cwL*XWHoAbQfL@0YNAj7|d~7LM9$QWF zEur$?ThB7|prys8I$o8rjMg;Ok z#;O%W82jC3#Q`O2je`$NK4dCnV4IW-tX}kQ1dt({M}Z7Yaf}j8B9%AQn~=*@7P7(J zD~x;tFEUifW*kmHR>yk(EQ^{!)lU)EsE{zhZ?=@xWH${izzB~GAyq{~!Cv&b1+OSg zV0+(vrp%b)YGS5AfTC#60c3VG4n}-XQVgqA@N)djqX7_PleN96c1Ms!PL+cciC zA^8fVwI4|>Iv~CN&Jck9P`}oEgQLU-nBPIymuX6gYE8baTp!H5iwXY}}$Pn~KL~*iC9J?bsZo|Ol1-@buFNUS@)hxADEw;{dOA-uk_<6|D1(yiU zv{%^%mEFk!1J_TP!b>@I@_F*d6eifZggXB0>X??`d0Mrt3D1(C&iyHiO=GCWab*IN zYW>$H@>$jg_9&=3teP3+G(NX%6ggGLbxk@$dN)!%F_3@mD=ynwvHv@HdT}rz*Y92G za`Z?SV?v7!S*OrPc8g1c)}k7 zFt<*ihjyi|t7-$8%VPx5Kw&O1jFQyVaEG0Of;$ND3!bg(yn+>saqL{VZQDX z#`H5g3DEZr#6FDJu$mB^gyL$GSICElp z#Co9T9e_%ln{NeX@M{i}doXfLsXxdbA6XZEcx!wKh0V70{fdy;J)^2rx1@z!N`{Z3 zD<63fB~inssh(pM7ricRX_k;*Gq& z;ABV~Oe|vJg!!0aLlgicTQ)~*e19wMZVw#|7(;vn)Y#g8yg5IH4RbZHzw_zsQ%C9c zRlGaZ)4vo_a&d-Sy1f7oDRwA}p~){RFW~UjRy+*nC!eJzC*sIfVAbN0?ntKNF58j( zgEhxhiGRNKOCq})6T3`Pt!C)Qy zk^Oz+xF=vPFUR;zdidKqg5dzzF3l;}*VMr>o;M~9b zf1HX2y9OZUZ%Py8=2N9^|3(!*@fgEl?9$PlJ$k3O2AC;0_n2Hwgr@$&&5H!8efyk; z9h_#pMWz_$TLk`CG*dKBj@Ijy9fn>!6KzSrr1*}$O@Nb|qr{S3FB3v7kJS2vSxN=G zo#sAFbFRZn4*xZ@D*-GNIR=t0PqiyJmpT5f$H)0u7Y%F1xCi6gqZc?+UwH&H8*Ds+ z%bb~pP{*)RTL%{ps~w@1`vV42ruI{c&bXdS>h;s$TO}a!;gHUfoB<}5DwheksZYFz z<2X+d(@fRsFJQpsDM%!FP4+gl?&kQ(23{lFwm;Xx$hL!C@DospQBL2WClzu6R6o4{ zb$ChVXOsxHLINA;3`uXbQzzhAu1>_%=udD516~pu_F@J#C9R-OGHeMSto0ZYEDs)J zW_cs7qchmJM4tW}t{UrOFx>saVvH}ZXl~Upiqzb{sKd@;INcJ6e@YR{c27RdKsG|D z#|8t0M7xBL8ph2Cd&6KAg$8#=r5N9vBi;W0v zHV%gF8a8Rnc@0G$6xkE*I76R~fPsCT_2@oNLV#nKXfsQ*f5>vFw4vn)&x2rVt2cUG zN{6no?ns>MLrD;TGLQ<$VE%eo#}S6Vcygy#;{%lY+C&?gJ4TJ1*~M*NW=WR9R;NY- zsuU7lX)ZRBwu)nvfyi;_qAJlFc+Dfdtw~WJID|F%BWw%W?cY85)LYRd!#1m1+v+ej z1)fI(o^#`(Nx=+l9JS;YvT9dG{t)vdO3RjjHa;5!BNw-2>}XRa)T0Ail~XiddmSJf z8~JVK#?hN0ng2|U8dd%OvK%9L%hKv|K9q5Kp#k7Pes)-ZW}k^@aeiFQ?LDA*oOV*lc2sb2hmQb8yfZX z4B0&MK4Yw>^RDM2|4B|I*u%P;A(6jQ`vNwyndym4`NC)&?!J}`zyBS8{W{PLT}R6Ip)%<5kooisgykhL5CG;b>^b&@1)U4(vQ<=i5blH z0OdD97wH!>zMULGpzjx;jUOet424Kyyli1`6}0hmZxLnuJF#Z zYC3>y|B;%|0VhQ^1!emxD^xYvCS>|}P2^s^Kn6<4UAZ%+>AZUcuR=c4W6H2}r6eYD=IOF9yVx=O_6TEI|S+ra?y zR>@LutxBf#-k;h<8YN4cClvfw}qeWl)GcrX1Jx>T_$SKD`!_{Y;S#MVZ9p)Gup6pwj~^ z`{p_L7xSC%K;_Fd)A8NfwSUPW$zM{;OTC`2@6cbHfPHV&I}R8KJ!!?h=d4lEIk~52 zT35-5OQ5T4-W^9h`y1}4=>E#`;KYtut2sT7;WZYK&VpW>d3d8mMdM95rA>Z}XV5Ez z(2JeWUP=I_6AsJ^wvHY<|7TEZCCq&-4>+|ARCZ`Roekui5m(#vk&<&UU)6g!8q--_ zg(ifGtARY5mkJ}@rhwQeVXTA+eBnPUwLj)rJq05dgshF+tzO+$S*wecD?s+M6cucD z?U*w@^G879>lC&184)x8W>C8=Sh2B`yD{QZgV)Z>_EdYOnaelW!?cD}3Y3hF(1$TD zL=IJ2LrFSnAzb%=w7qAT6jjtM%vw{^3`0gi6lGvQ6by(F6Oz+Rozx^T(3QHX4Jd+& z8FS7#2h3v5Suvv^qM#B4R8$O@6&3M2Jp(h$d*DQaqSCIUqg@>1;#e2c zT^#4)co!$QIMKyPE>3oFii;U8PIYmbi_=}4;o?jeXSq1r#W^m{b#b1H^Icrv;zAb} zxwzQHB`z*?ahZ$DU0mVfN*7nTxZ1@vF0OTPor~*T+~DFy7dN@M*~Kj`Zgp{+iF;Y zLB=DL{Y;$0W> zUA*UFfs6NDeBffCi$yLzbn%gkk6kQwvBbqv7t36H;$pdr6)sk~_|(N`EI!RLZDKhr9dlz)&gw=+6uH2XfMz~U=x8&1v(0J z64*?jv%uy8TL^R!*iv9Cfvy5o0^J0<3sejA5a=newLmX{Z3MOz=q=DkU^{{B1$GeF zQJ}BDP6GV|b{5!0U{`_N1a=qLL!iIFo&tLb>@Bd5z`gOnPBL$`i93?PSV4A?u0>=m(D==N) zIDz8@P7pXz;3R>Q1x^u|A#kd|X#%GUoFQ5Me3A`*YTi_LeR|Q@ZcwOKPfj0%-5||_Kw!k|Aa|PxJyelwY;5~r_0`CiaAh1wi zk-&!n9|?RcuvlP;z*2!_0-p#h7g!;%Qs7g8&jdafSS9d&@VmfTfjjnN1XeI#(N|Z@B66F#Z ziRKa&5-lVuC0a_fl4vc_Mxw1mJBjuZ9V9l9*i@pUL??;OBsxoMF0q9~7l|z;wvy;7 zQ6i5(^SO6(-jPhw|@T_kpu*iB-0 zi9ICxOYAAJm&D!@`$+67F+gHJiGdP>BnC?ikr*m5Ok%ji2#Jvrqa;R4)JW7yxDrA_ zN+<~}VI;B=VsCvm>S1rirZTqJR^#3d4!N?ay!xx^I`S4vzZaka!X z64y#xCvm;R4H7p>+$3?c#4QrHO57$fQ{r}sJ0$LuxJ%-0iF+jOmAFr0mc;!M4@f*H z@sPyB5|2ncD)E@a;}TCuJSp*%#M2VbNIWa?oW%1IFG##7@sh;L60;>SSIm_ z#Bzxh5-TM>mH15JbBR?FUr2l@@s-4CiLWKTk@!~PJBc+C-%I=;@uS2~5EbkWpx^P@&L5p;DoxLMw&V3T+hH zDzsB*uh2nZ6NOC`Ix2Kh*i50b!sZHFD0ETSQei8Ft_oEO-4wbjR4epQ=&7)^LNA4F z6t-39t6z6t{r z_EQ+BFi2sr!Vra_3d0nJD~wPWsW3`mv_g$St%9o{6r_Su&U?cSqf(>oTG5A z!g&hkD_o#(p~6K97b{$%aH+y&3YRNfp>USfQ{|;Zudr6h2p2rSOHq zmkM7gtXBA1;Twf-6~0qgqwu}L4+=jj{G{-+!Y>NHD*UGKyTV$9KNS8{_)B4(!ruz( z75-6ZrU4CVlxa8`v*hXVpjouo4G`7>&USkK19X0xD z?4;38V`q(BGGzuDrXdJ3>n8x86lQoXeI8tMZ#!(tmHKu7Ct#ORTu^Q7gj?*|^ z;{=TpHBQnvS>qIq85*Z*oThQQ#u*xCYMiBUw#GRc=W3j%alXa{8W(C@q;avvB^sA% zT&8ik#uXY@YFwppwZ=6X*J@m+alOV38aHa(q;a#xEgH9K+@>*8<93ZZH15>6OXF^h zdo=FVxKCr2#{C)(XgsL#kjBFrk7zuq@tDTr8c%3EsqvJ?(;ClcJgf1X#`794XuPQL zlE%v#vo&7Pcva&yjn_5a(0EhhEsZ%EZ)?1xF;`=r#=9ExHQv)$pz*%O2O0}C7HNE_ z@sY;I8jCfSXe`xOrtyi!a*Y)lD>XjV_)Oz-ja3?7Xnd*hmBwm~uQk5W_*UaPjWrtI zYy6<`qsC7fKWqG=@vFvf8oz6-)%Zi>PmRAc)@l5$v0mdJjb;Wgph1~|V^D68F=%d3 zVbH>$(x9b5D}&YsZ4BBPv@>XL(7|96gG~)O8gw$)%%HQu<_23BbTQb{U@L>J22}># z47wXs8}u;fX|T0HFN19iwl(N&(8pjqgY6A=Fxb(cufa|R{S0X+s=;Xn zryHDMaHhdo24@?bV{op)c?RbjTwrja!9@la8(d;=sljCimm6GRaHYXj23H$gV{om( zbq3cP++c8{!A%A?8{A@WtHEssGYxJxxWnL1gS!mwHn_*&UW5A#W*OXX@PNUC1`ioL zZ19M|qXv%|JZ|uW!IK7089Z(9jKQ-8&lx;#@PfgM1}_=BY%ts46@ym|UNd;z;0=Q} z4c;=CWAL`YI|g$N<{7+eFyG)kg9Qff8+>4}&|s0lhXx-Rd~C4TV2Qy}gJlMv7%Vqf zVX)HRQ-jY8J~vop@P)yb245MhHu&1$8-s5RzB5>3@V&tg20t47Wbm`WF9yFF{ATdG z!CHeq4E{9u%V3?s-v;Xq{xN8l1+rikWmz~`lxLC2qInh-S+vNaGK-d3w92A&7HzU< zn?<`U+Go)ri%qiFG>eW|bjo70EIMbgc@|q_(Ity5v)C$&u31!N(JhPaSyX4yBa5C{ zY@J1~EVjvF+bnu#(I<=Tve-V09kSRli@sUxltsTRcFy9=9M8(}>>SU@@!TBG%klgi zFUax2952f8;v6r@@zNYG%klCYugLMr9Iwjp>Kw1h@!A}(%klagZ^-e+9B<0;<{WRy z@zxw~%W-Cox950Aj(6sGSB`h*cu$V^=6GL@vvRyY#|LtJFvo{-d^pEPa(pz$$8vl; z$0u@pGRLQKd^*Qxa(p(&=W={L#}{&ZF~^s3d^yM2IlhwPt2w@wi^=zLn#g z9N*6IogC-pI4{R{bDW>!dpR!1@%$Z=tgi*o!h$B%OSILE~~F3E9ej>~fVB**1B zuE=p^j-TfES&pCQxGKjla{MyKuX0?S2WWQdwbl+i@g$EYdpyPC z43DRJJk8_j9?$T2rpL29p6&4*kLP+k&*S+XFYtJw$BR5(?C}zhmwLR++wF1 zvpnAK@d1wydVI*^!yX^;_^8LnJU;I636D>De9Gg~9-r~}tjFg(KJW1bk1u+B$>Yl& zXM23b4f?;h8B{KMm)9{=*V&g0)6*L(cOV>6%dNuOmt9iQbs zGd`R9tnk^wXQj`UK3n;0?X!)~wm#eWZ11y!&rN)8>a(NIPChsD+1cmjKDY4M#pjkj zxANK5XO+)xKD+y@_SwT{PoG=+?B#PCpWFKE?X!>1?R;+Ua|fS0`t0j-C!hU%?(B0H zpS$|p&FAhu_wd=@=bk?I^0~LqeSGfgbAZqNd=B(E$md|6LwpYPIn3v9pCf#Z^f}7s zXrDDcYkj&tg-_{I`P4p*&#cceKF9hT=X1Qz2|oAtInn0G|}1 z20lZdkGupJ)0!%jelX&+&P#&+~kq@ACqm7y7)&=fyrR z@p-Aw%Y0t$^9r9=`n<~L)jqHBd9Baud|vPK2A?GLk1cl*4@=e<7f^Eu1s{XQS?`Jm5-d_L^+5ucCxe9Y(LKA-UUq|c{(KJD`vpU?Vy z&gb(!U-0>&&zF3@>~prySA4$e^EIEZ`+URan?B$2ImhSQKHu><*XKN+@A{nY^F5yn ze7^7V1D^|hF7o-I&yRe5>~pctB|ew>T;}r=pUZu&@VV0Gr#?UP`MJ+kKELq!rO&T? zuJ-x0&u@Hw>+?IGYkYq1^9P?l`uxe~&pv=v+l!0LcK0`?5Jb--Q$w+Xmyz}^A-1l%s*_5pVY zxMRS+0e1@6FW}ArcL}&_z}*7w9&nF<{R8e9aIb)S2izy%z5xdW+%Mq3fP(@K4mc#> z(161N4i7jY;K+cZ0*($?6RUa|9}$%9uV-r zfCmLUIN+p!xqx0kKVT3r3>XE>2aE$I0Sf^S33zD0!vY>2aB{#S0v;J~O2DH6P7OFM z;L!n(33zP4=>d-mcznPU0-hM~q<|*}JSE_afTspLE#T<^&j@&Cz_S9L9q^oh=LS44 z;Q0YB2zX(@ivnI8@RER+2D~ib3j zfVT#`E#S<6w+Fl<;GF^Q3V3(Gdjj4Y@V+p{4L<`0oMln zBjBF_{|dM+;NJn)2mB{svyceMkYypAkmVsWA)AM+2-zZJWyqExTZL>LvQ5agA=`y) zAF@NpO+s!OvSY|jAvX)zIppRcw+PuK^)9 z+lK5NvQNnELT(>&hmbpl>>F~Yko`jL9CDYCyN28?hCG2{Uu4-9!w$b&;p3YiP(h4e!PA;XYS$b85+WD>Fv@{o{+hCD3f;UOo7 zJR;!Fc&IoyG$kRfe9`cNk zXNEj0Vd1=VYLS7#7ijY@^yej0?A+HH}ZOH3F zULW#?kT-_BDdf!|ZwYy8$lF5B40(IVJ3`(W@~)6~hrB1`y&>-lIVD{jmqNZAa(2j9LcSXEwUDoe zd?VzWA>Rr)C*<29-w8Q4^1G00LVh3ehmb#p{3+zm zA%6+^YslY1{vL8|$Uj2<8S<}?>q7n=a(&2uLN<$th>Tbk(TP|dF%z+Q#EOV5B34Fh z8L?Hw))Cu8Y#Xs%#P$(8MBF6erV%?v>=bdch@B&D9&w9^T_SE7ajS@3BUVN17O{K8 z>WDoe_Kdi7#9k4%iMVaV-Vysm+%Dqw5qF5VW5m7@cZ%3A;?5CwiMVUT-6HNDagT`o zBkmb-uZVj`+$Z9`5eG!vFXF(6gCY)&I3(iGh{GZdk2oUY$cUpNj*eIpu{NR`QACsx zRYV=pM9fAU6LD2Sq$M;-rYVh+afLVh}Nm7)8uSj3Xuy z3lR^Acxc4KA|4)ba>OGd9vN{;#G@ikjW{jh(Gib{cx=S!5s!;_e8dwXo*40@h$lxp zCE|>Tr$#(2;^`63hNvl8Bc^ye#775wD1N zWyGr@ULEn8h}TBEF5>kOZ-{tf#G4}C9PyTjw?@1z;>?J*N4z8Aoe}Sfcz48mBHkPE zzKF9T-XHOShz~}5DB{BrABp&A#K$5&9`T8YPeyzy;?ohIiTG^9=OR8I@r8&lMtmva z%MoWsd?n(m5nqe=dc-#(z8UeYh;t&o9r2xrb0f}+_-@4c5#NirAmaNGKZv+6;-ZKj zM*Jw^#}OAtToQ3<#AOjbiMTxCiij&Cej4$!h@VGX74eIRUq<{Y;_8TBNBkz@w-LXK zxF+KF5r2sIW5k~#{v7d_h`&bsE#mJH*GBv!;-3-!inuP~-x1eG{3l|wJdr2!EX&i$ zvpmmCp3N;cW}Yqbtjx1zo~`n1ooAao+veFW&-QtC$a9lCH_fwSo}KdCEYHq)Zl32B zd3MQj%RINrvumDJd3MXQd!E&K_Q4%(HKv zJLTCg&z++%3=D^V}oP{(0`1=U#d4o##Gz?wjX;Jon3UV4j2W9GvHnJcs5v zEYIP2j>vOlo}=;{oo7v+wRyUEiaceWDo>rK$upbhm^{bkIWEufc}~c4|2!w=c|e{A z=6O(_2j@8{&s>ovv{Pfjq^&_JA*FoD7NN(Dm4vmmPH!jzDz*b`D9%rp z$*r<=NK5KUb!)RlB9?TG(!RFBX>Q{JR9&4>3B&QRwhpeQks{Gjyf!c-wzLIME9#4@ zisi7SwM~OW6^Q3 znl<(2Gi}ZBDUI+jgNpUQ>62e+;qh*|-nOJfte>r*>%E~js;)7$*i>6ug?PRd(2)A7 zWZ9Gh{|;NB7B+sp9-L`xy>7pLW@>XAD&SHZ=xet(r=e!@zbQ_(w{?}HN~+b1-MOhs zxBG0x>&%97L<^KrMRvmU6Xn&mR=uH~u-HskIs?|Ty+*Az7TxZ?Ymnbq|e(I6kY{7hx?s+QhWqr-Ap(cgrp+&-v^d|1NK>Mo! zM#F1|4oO!7-eG~1D=`E`ETld^+Zuse8+OsyEs=&xnbo(M^@gHu@|+lI=bfb9QEr#; z=Ei#b(m(aFAaC9XhLM9xOR@_V3j1s<9xigJjxS}`yvdfSKG<+VL-p7?qPO(g+FSXY zu%QFv7+a9tgz9XWZNa#;K~ZYm5@SR7{#f77S7K?OuzG$@y(PC?K~2avzP5$3 zziw>xC=RPnV`6;K#x`Qcsz;M5EA542X5#` zkVOLj^vZ8*=JfiXhafeK94d}L`lzmsd}6xXw%B=@F1CHn)+_&zdLUIpU)Q3L(ne#8 z=r3qEGgGQiYwVf5)da}4wAa2P^@i>2t`|3eD?4&fKQ}wVRya2_wVYu${$c~ZiuTze ztfZv9yS2`3>lRUD#gcoTY8@UaK`@Wn|jbp93qNCztewpEn>bc>2YYn z@+7RqAGUFGMbBPG*Y_{_mAkBfDmD@T)Ge0OZ4XlYqw0(j@(ig z`Is%jzcT%fIwH%Ilz+GHI3R7?>SuS9dg|w`FMceI{|!x7C0g3aYQbR*y*swIV}mF9 z*K~(@*4K1t@HN??)2vG?bq6O|bGr73y2|z<8(M0)6RlgH*x+Xd4N8YHPBR;BHlB=) z`I^L|t87bGF5S`RS~pbE6FA#8i7ah+y&c7rf?IJ`Tg>`o4*QMoH-$b2;*E;K~do=dIY?u~j+fPy}nQH@+g$-16<2JD6mPQqO*k?x9 z*^J^qsZy&r%PP*+|3av3n5hS8+OeH&QJUG{O6nA_RErYpN=DSLq>ezKq5J(Fn;Tpx ziYHiX#;PfL^wb9SuomyPnvI|fLY0O3uN&g&qKhsy;^VE2-=d^_OpLJO$x^F+)oT9Sx^Oc)c(82@ zYr@ghx7e`K7;D!t5tfA7ds>-HZ|K*sTwyj_Y1sEnyYFl39Z`|F%?!(CZNy*SfR^s- z{mU+MR-Js5W$|yq=F-MWXsf2+8ClYp@rK34&l@3FKUlNQy_fW0j_qbcsfL}FL|J|8 zE}v`sgjMq~W~^OoN=|tzrA(<+ zp}`wNyC$*B?e@htG=}+>J+PjlA+68rZHwpVl2GM8s4i#OU}Zt0A+2lUD$_S3 z-dp;$Qm4_%8oR3ceaa@hP^Vf|-FJi8DCPdU+3xR=4LVv(imkl=#oVx|Re?M8M%yw@ zS%$$PJwghB%7Xl?M(b0@=w{Lh$xhY)z1pCPrr$31j}5B$y;a30OV&`r4ZXSj{OJvU zwn|zmmsK_;zoJ1wEV_&24ym;bu-frp%1mtF;!i!Xzm>t-2J2`BO-QY+hh5wIrRrN} zB}z#JceDE2p^1U7Yn>_yE2kABkh+az_s1Lss~ zrLAq8n5)N`O+ZRByV(|Kccyy~>tI|Gwp7^Uu2r2Ws%LJiJt8g@|q`nhugm&;oNBtkSKrdNqwsZsBhS_5pQWA|0 zuwY!;6c0ANFU7+Ei-*hW&8a(KlBMb?P2PXCTR48h8tci+jw<*~8XA|{5AByyx(2?Q zbYQaDBKPPGH#&9HEX9k460`fEO)if~Wf1kPs`V*s`tU!pnZ`biLf+PKAPKmhx1Etx`7)mb^hPkmz>?OsX8KnCL|=Q?WT5V z=!V@me<*FXue68!b14d%Bx+;r6Wgctp6EdB^`Ixz=UK%j z(P9=>Le;j+`tmn7exr^>vI$*IAN!3@Hbi|zJ5u5f2U`99z0Q%?wAdzUskQBI;c;b? zqb&{gf42vFMcRWEH8U-v->kFTFO?e=Nnh#_otDzAR@R@TBMG~KCfWZm>rmgQH>P6; zH#zv;*3iD*7;B|7`)#d>9lcR@Bb$ubo@E7hLBkO@bg7qS0c-3j@7%Dqq6JMcxTFJ_ zE9^0yoX!)QSg92@(0MEs2yKk0(t_w@pINxE=edrlqKLW@W4nh{>pL3{#YPtOjNzqE zRoKv?*9L^!YwafYrRNm2ts(lWOT|*obD8z*tLu~Z33k7hG^ZhdsIg{lTB*b=ad8Qr z7Fl`uO*6zas$R7T;)^N7TZ3({Ez+vq-AZzOy}ce>e{WqM#+Pm}XU*xOY3yxCmQ%~^ zX!U$p{k@KjAcmFN{kyD#T~Z?J`g^m|jAvgf?tTq%kd<~i5LsehacJWb>=d~sLHJw? z|H_TUkwohqT=KiD?aKcHMnx>aShx!WK1{ z!Xm3-ao}6&&idQV@Hd*6jgma2w?)a!)FSG69#da&t$lc+A$~Fab{m|EUsl>B+*pd! z(hKo_tnIk4{`>W_4eIELvuPlFZzzpPz5ui=abkFnWN!_D2UR=jtmtc{&oTEbD%!m6RypyJAo z%TgoK!?If1JzSO2LTlAFTwSE?(ON54y&*8P>`bMfc+`51>Gf`<`1UcSY(C}q$PJwe_ONJKc%GOhN(1> z)TdTf$EMIx5;3K>`>|E_KK0v`YG}5^%U)o2dv$$UIk>iDLR1kBH#E_cp?YL$r^BtH z{E~{Z?C*^AfGH()8)r3QS_5S2S6LFOF0zohzg}gmC9<4m!*|(vdg;WUw)T;JO#-PV z?(%Yr@NYK&uQ*etlpS7Jv%1GdlQno)Q=%(tw4#Qfaw98KYO8Inhv=FT#vscen)>sb z)@(hOl7vk=n{vl?wNlut&i&L_5=LuNb%_jau(Av`+Jud$s`DV}nCUgE=GoLTib|Tc z+<)73bZbCoz3VT@N#@u??bMi)^e<7a>DBfe8V!IH!)r$k8DoDQFZpG;tu?R<{{!D8 z0n#28-0wD~R~rWFmExkG&97cfMGhNyG*iB$msNnfQ&0StzpS*+h?FO?t*t@JH=Mg=5+73>KHP*F zu$=|R^7;TMTb#L(e!(D%@3{?DyUx#)UV`?u`qQQEfiXkuaN@B>gr!$+C$((ZtfM>K z-s^hDOrK<5-fYI|_I1BkS{XMw%sRT_rrAPlbz}6#fM%3Cq-1Hc>>2*qXeY-GE)Db# zv>u^TgA6TOW;!UFZiRPp!?x;uXOnngh4n_w>W!m~80`s{>ZNb(W6K@a(pS)>MuX-V$x_?YR%A& zY0uLblr-TVzr?zpa~gh-s3YSo&fsl=zOOAZ7j2~5wSOxm%POP2@4r8@=bTTO@45&!ZNJ;u2dYc9`d=pD47=I>=^$r=_$>ia8vNH; zqwsNk3Ty{2_e)`^$Y*zSgWaq96|ywH{m@#z6PhGMMWVCx>z7%@+p-aF#kBBWKj@uo zG1oe^(z-nJUpE0q*oAf~*>$OkPq+I$rQV7U|M#)1w9)jXQ;L_qHcu(d^nbQ#^3ZJY zPet1BLE|Ru)^Fz&ad`1}yY&t3#r}?5`df6)dX^s={#-XHE4_bX|NL@82AvAci^q@- z^m^C@?y}Jb47OwXN=($1)(6Z>xu_-%W+$uFqf1onU*el(b?lE6s*1%}X;96yr`@s9 ztrtUvI_p&8`;WD8{n-t>DFz_LT7wj3R@>~=G`g6gD%;UymfS8C2CcKvg=nm~D+;@z z=&nsOHrvBS9(9CVQ=6Sp$HVpM=9P6kT>n@eE-~YUUd@_)P%~q3^F=k84{J92sHWHQ zn%b2$__Aj6uWI&LU6c8`rujEDTYOuy-FG!xuc?`_(D}ZGKh;$KTr>EWnlWo@`u|bG zKWke2Ra3F9rsLl=eb(2YS#3MiR*k4Fm$mJVsO6EhoKnl9YB{x*(`tEiEsv??v9+9D z%j0T!d@WC?<%zXCsg@_#(o%x;>OQ_HA6UzwX7XSmLpF3)l^XSg_f&H|V3yZpedSm;*#iw~^LQnzB6%THV`cbye3>-fN&&s^to*IDJVjt`7q zxm@jLQhZ=sGAj(2f78Uux%Hsc#53Kx1 zQ9ebKA0^7C{y*dc%WUKW<3>I(=NjQ$D|nq?9UoZPjiT%(QFgN^yG8I;!P~@6GezIq zMc+IAn-9#nU+@8uc~F!+B>1ps^@zwkD)^Xi9v99NBJ-rk)bW8i&j{yPk$FyJo)>&U z@I}Fw1YZ`MEm+3~#@9r<*9G4w@`3R!vB@0aye*t}gfmw-^Mv!RaOMl=J>e`6&ilgo zKsXD9vq(4}3g;u?d@P*B!dW7mrNUVzoKJ+aTsSL)vr;&p3g&MTxK%TX)c`#>9mkerF2?Kr@J->WUKy?d&-KvB=?rwM>_jTXMl9}lg>cNL9(6?tYWC_ zHcVCwmzfcbd|<38@`2Hn6p~U>Noq+WnUx$PIaYF9kq^w7Af5dsCrTb5d7$J$k_Ssp zlFUhZlD=dh8A?WydC6EZkt|3aB6+CfVUmYSPL@1E@<_=kl1E8Sm7FGdwB#|8$4X9@ zJWld>$rB_`lsrlDWXV$`XGoqZd79+ul4nSsDS4LU*^=i-o-28ttc;3fijH#16*EOX zFsDK}EtFHK*s_EVjO`TLE2o3na+3{wV3|(J+3Y{~z}Qu>O0k<_cU4`js(YxmJyqMS zmD5W(+bC|U*jurW;&zJLEAF729hK8pRqUiH`l*VYRmCo<^RBA%ZpztRIeRFlzjF30 z@_})0#eGzpeO0Fcs>Ob)#XyxAq?!*d@_}WB7Wu$3!&TV`l^Lm;k5ZY@DpRA%YE^}+ z9HA2Pht>oP!h(R-B|-QhzKX{z#cRe6T0JX2Mkr7F%=)#s?Hb5+H8 zs``9Yb%Cn5P*q=~sxDR)m#FGXRn=vx`Q^&FLh(w)t5ox=m2-{awTjoN%Ij6-4XWZs zReh7Hx>;4+qN;CIRkx|;GnI3@;vI^2s^)ho=WfM&6z^4)_o>QRs^WfC{eY@^P*psn zsvlNWkErI4D(5l9#}%JY&7V}xQ;JV3KBJsxmGhk9^NKI1iWgPIORC~!RWVzYy`swg zXFjm9xvFfQa^6+WeC52SoCS*SD}JE3P;rsshl(F5eyq4yaf#wme(is>kQ5{VLTy#Rt~oYt`c$)&5)6zK#!!b$no*e^i;DRJ)&5_g_@^Usc6#s{8M% z`&!lg57qroRq>bNI>o;g*DL;`*h~|e)GX8GjxI0P^EwNs^?ZrbUtooem$ z(4Bhfs;zZZFYRojoo%(#TRVMpr|q<}z3#Gu?y{rq(pNh>=`Q`Wv$J+~(ax^g*-dxY zU3cC?ckZt{?5Ul-w6nKvy^n6cuPz&)%l6al2kO>?GzaU<5Z!sG?m0}i8?HNz(49u= zcB3>$Yu4y?wYrn5I|oJ;&lT4#s2OP|uQRdEBsx>jnL~8uP@OqUw>n(6nyfQNXy-_snW8gC z>C9A}nWi&G>sH6;R>x{i*E~-1cwKgaE;~_|outc7)@7$?&d@wn^EA!VwR47c&eS|h z^K8v?G|$yMPxE}u3p6j(&PAFRYhI#xsdg^Y&gGg{Xy;1Jt2D3Hyhig{-Qqgk;(E;+ zG;h?rN%LmSTQqOgyiIea=IxqyXx^!Lmv-*f&OO?>S3CFVPP25?{kqEoy3>QY(?h!I zVcq2s-RV)?=`mgPxbE_V?)0SY^pvi8T6cLycY0QrKc~x|*JUs0vKMvPOSuTA{nF)SW)ntv}OUKG$7VY3B=F_N6ZW zN|&$J1DcX zW1MYGm)@pJAH(eow>PbJFs*hpE&7@kJDG}prfg@!T?}_MEp{_4b~nx*#_4a$_B3UC znJ#;qF8dhnYdFBP+RwBaXj%+1Ee4y4A*O8T|B4SRqfN$`s;sFRW15dO&Bqn_z^W&h z>itdIiKguV#yQY92bs*lCNs%oawg-MG#?oAhH)bw7!NhA4*P$?2bQ_iG{4R`GmSIL zRL(V(YfPKA*)|P)QM+YlyjVEZyvk3!2I7Xq9zz zwvEZoxXq5Dn=u|^vK_}}gK^nS$7eGWvIFu`rKCd3>11M|pgl$KpJe zpZ^6+<+JkAL!L76UODqb!CKBNL+{MvE9NW3-CVI!2oqZDX{H z(LP3p7@Ne{G)Bi5onmYjqjQYSV{8$lON=dJY!#zxjH(#jVswvD9ivB#o-wwL(JRI_ zF}97-J4T-vd&U?LW4{;!V+@KhIL43|Lt_k!F+9eI7$akhiZMDyO^n(YZVVAa#!xYI z3=<<8V@!;(F~-FhA7es{{bNjwaX^d%V;mIY;24u)~wxGTopG46?RZ;bn5%!+Y;j0a*o z7~`QB565^U#-lMFi}84jCt^GqAm>uJl7_Y{7 zEyn9H-iYyLjJIOUiSc%fcVf(qF)zluG3Lj3FUEox@5lHc#=;njVtg3mqZl8@SR7+X zjHNM_#rPz~@)#>(tc>w#jL%|x9%EIEFJgQd8soPZzsFb`+g6af4 z67)>4b%I_Awn?yUg5C-GB-k#&_6c@Kuw#P033f`*FTrjJ_Drx>g1r;$lVINj0}||) zU`T?Y35F#Yo?t|RkqJg67@eRdL2Uvzfk+?|s02EJNsvu2Cc)SQ;}VQdFd@PI2__~u zAi<;rL4q(rlpvoVPLL!hBse_5Z11g9oAEy3vt&PZ@(g0m8wo#31V=O#EW!TAX;NN{0-ixOO%;PM1lB)BrcRSB+6 za7}`H6Wo_zR)YHzJdohQ1P>*6IKd+c9!>CAg2xj)k>JS$PbGLd!7~Y-P4HZT=M%h; z;Kc+lC3rc(>;$hQcs0Rm30_a|MuImJyp>>1g0~aAlVEOwc?sT4Fh9Y22^J)HKfwnH z7A9Df;KKwTCHOeO;si?)EKRU1!6ylpCs>hSWr9x=e3szz1gjE!k>JY&UnN+b;Ohk6 zB=|PLcL~-c_&&i834ToQQ-Yrp{E}d8fk|B(V10sr5;Q9S1+aj!0-OTM z3&<4Eynu=VS`<)OK+6JJ70|kXHU+dTpj`p&3+Pb5CIxI-K*s_)6|h+WoeS8!fGrB> zQoxo4Y*j$l0;&q=RzUXxstf2*K+giUE}&Nd+Z3>E0lf?8Q^0lwY+t|*1?*Tr-vV|j zpkDzy7qCkKyB4rp0lOElM*;l{*t3AW3fQ}VeG1sOfB^;USHQpm1{E;4fFT78Enrvy z!wVQuz{mnd6)?JhngVJIa0?Ix$O2RW2NrNp0S6Z_seoJoUIBgqK>=X_Q33e^;sTNa z3I!Zez;Oi}U%&|koLIm~1)N#HS^pnH_t=1Ep#WgGJ8W&)uGzN2Y&*{NKDII2wr$%s z8qyeMGk4B^xV~Q*`ef*vpNhT$1TWEh!YREE(R#$*_q zVO)ms875?ym|;?e$r+|(n3`c)hUpn*WSE&@R)*Ob=46=JsI|9*q32{h65Q6W;m4LaE2op zj%GNP;oA(yGn~k9GQ+71-(~nQ!%rDbXE>ALY=(0g&S$ug;pYs$WcW41Zy7FTxRl{? zhASDaX1JE&dWIVrZf3ZZ;dX{Q8SZAdm*IYf2N@n_c$DGy41Z+!Gs9mQ{?71EhJQ2s zm*Fu11RfW7Lf}b(rv$PHWEFT?Ae%sTfma1y6L?+V4S_cW-V%6Q;2nW?1>O^QU*H3Q z90EB7atY)X$Rm(fAfG^ffdT>r1quli7APW6RG^qZae)#7B?U?elolu>P*$LvKzV@* z0u==+2~-xSBJiQWM*<%Ud?HX)pqfB+ff@oe1!@V@7N{doSD>CieSro74FwtrG!|$g z&{UwAKy!f>0xbnv3A7eyBhW#hqd+Ht&H`NoGyz?}5HJNS0b9Tka0NU8Umy?&1tNi1 zAQ4Cfx(aj?=q}Jhpr=4Df!+dr1o{f}6X-86Kwyx-V1Xe5Lj{Hj3>O$7Fj8QYz-WOn z0%HZn35*w*ATUv2lE7qvDFRakrU^_Jm?1DzV3xpafjI(m1?CCN7g!*$P+*b3Vu2+B zO9hq*EEiZIuu@=^z-oat0&4}<39J{`Ah1zjlfY(yEdpBwwh3$(*dee}V3)vdfjt6y z1@;N-7dRkrP~ecjVSyt8M+J@vd@FEV;Do?Qfl~tC34AZ`gTRjhKM9-`I3sXY;GDpD zfeQjZ3;ZJRtH5sp7X>Z}To$+@a8=-%z;%He0yhP23EURABXC#Xp1^&92LcZT9tr#| z@Q1*k0)GkoE%1-PzXJaWJSKw3<04OpJSp;&NEVT-B2SBC6Ui>}jL5Sh&xt%Q@`A{V zA}@)&Eb@xTt0J$7ye{&F$eSW>iM%cHj>x+r?}@xG@_|SWk(?sAL~@Jd5y>l(Pb9xc z0g-|tg+vOA6cH&ZQcR?{NC}aWBBex1iA85phL45nm(_2}L52SR@fiMY@V~6X`C} zL!_rjFOl9NeMI_-^b_eXGC*XY$RLryB11%miVPDOE;2%7q{t|d(IR6+#)^y+880$H zWTMC=!v8a!}-u z$YGHqB1c7ziF_+^T;znvNs&_`--&!L@`K2aB0q_o7C9qwR^*(>d65euKa2b#@~g;i zA{Rw2iCh-BB63yan#gsL8zMJFZi(C$xg&B{H+KGvc@py_ z7Dz0VSR}DnVu{33iDeSYC00nRlvpLPT4IgFT8VWM>m@cwY?Rm}u~}k^#8!!I65Azq zNbHo@C9zv#kHlVyeG>a64oDo7I3#gc;)ujiiDMGqN*tFsA#qaTl*IQEKS-RGI3saZ z;+({Ji3<`xOZ+17tHf^-7bPx9T$Z>ZaaH1)#C3@q5;rAoN!*sWBXL*ap2U5L2NDk@ z9!dNm@u$RJ68}j2EAgMiV=~A*F7t%UlQK`qWRc1G|211Cn@o0@XJnq0c~0henHOYU zlzBfd@}iE z3dj_cDI`-^rie^YnPM`Sf+_gQ<-Km&1G81w3KNj(^{sD zOk0^xWj>erLgq`EuVmWEw3q21(^00AOlO%cGGEJlBa@L4WJDQBMwU@zR2fZ1moa2a z8B4~Nab#Q>PsW!CWI~xpCYDKLQkkwY-DJAU^pNQ((@UneOdpxPGW}%w%M6eiC^JZA zu*?vdp)$i{hRckQ87VVLX0*&0nXxkCWX8)(keMhmNoKOl6q%_q(`2U0%#fKWGfQT+ z%p94yGV^5S%Pf#tD6>drvCI;gr83K8mdmV=St+whX0^;3nYA+OWY)`Ukl84+NoKRm zA(_K6M`Vu59FzH0=D5rWnUgZ7WWJO6UgigxA7y@$IW2QW=B&&)ne#FiWPX-E1UEvvpXBD1PcwXTJg%=fGQg~V66@^z7 zUQ>8o;SGg172Z;KTj3prcNN}KcwgZIg&Ybw6>=%$R>-4}S0SH5euV-G1r-V@6jmsr zP*kCqLUDx>3MCavDU?3Jnz+DKu7SqR>>KnL=}g778sDS}C+vXrs_p;Zudr6h2q@ zLg7n=uN2xTv{&e$&{3h2LT8083STRHqmWUM6l4WWL02#oOa)89R&W$t1y8|Oh!kRl zt_s~0x-0Zh=&8_4p|?UGg}w^?6#6R+P#CB%NMW$T5QU)%!xV-qj8GV-JpRkEpMS9wO|S(WEho>zH6h<)K#gcQeUNkN<)=KDvec|s5Dh+rqW!cg-T16Rw}Jk+NiWu z`BddImCseaQ2A2jE0uOC?NvIcbX4i2(pja8%GWC2sAN{8jSvPWgF%089-DhE^!svJ@|ta3!vj*XW?pQKOSa zXN@izUu%4$kdJOT*T1G+Yf&!`BEjLXAix)<`r`jjkHq zG`ef_(CDerOQW|&AC0~m{WSV(4A2;;F-T*u#t@C68pAY(YmCqssWD1pw8j{Xu^Qtv z#%oN_n5Z#HW3t8+jj0;bG^T6J(3q()OJlai9F4ge^EBpbEYMh}u}EXF#uAOC8p|}6 zYpl>%sj*69wZ5dW3$E15Y=M(0_b=X9Rec|qqzotJc8)_FzeRh`##Ue|d;=S`irbl%o^N9SFg_jKOZ`9LR! zPEMU%I=OZ7=;YPOr;}f&fKEZ3LOO+Yis%&8DW+3gr-V*Pol-ibb;{_J)hVY_UZ;Xi zMV(4Im36Agd$fsi#w4r-4pGoklv1b(-ij z)oG^FT&IOjOPy9at##VywAJ}k=QEwpb-vK~Qs*n3b~^2KI_PxN>7>(Hr;EEe>Ganb zpfgZskj`M8Av!~KhUpB~8KE;$XOzxpoiRFNb;jw8*O{O*QD>6QWSuEGQ+1~4OxIbg zvqWd9&N7|lIxBQm>a5aPt+PgFtDb&l(t&^f7dO6NPB?{$9A`BCR5ozps(b*|`K z)w!l~UFU|*O`Tghw{`C5+|{|Kb6@9y&cpu;G{|C*)!=D^YzEm4o-ugV;5mcm4PG#K z(IAIGPJ>(qxef9dDOqgh5GzQU;|B${3V2C}&XK zpn^dqgUSX~45}N{FsNft*Pxz3eS-!D4GkI@G&X2r(A1!rL34u^1}zO*8MHQNW6;*1 zok4qp4h9_!IvI2}=wk4-!8ZmO1JOV-kPQ?A)j%`Q4GaU*z%sB690S+DGw=-pgU}!{ zhz$~h)S#>(GMH>I#bBzzG=u2|GYn=L%rcm5Fvno7!90Wc1`7-p8Z0tc zY_P;&slhUX@wJG zu*YDp!9Iii1_uld8XPh>Y;eTjsKGIVZw-zcoG>_PaLV92gYOM~F!<5nCxg=lXAI67 zoHICYaKYebgI^4OHTccoqQNDD%LZ2rt{Pl3xNdO6;HJSXgWCpo4DK4-Gq`W?z~G_5 zBZJ=!{xtZ@;BSL}4E{Cv&)_i=OddCR!sJPlr%bY#WHou(B%4WglV?nxHF?hDd6O4R zUNm{hlr$-2Qre`9Nm-L}Cgn{km{c^WWK!9riphs2ADMh? z@`*`RlWHc_O=_6bG^u4$+oX<3U6Xny^-UU>G&E^s(%7VlNmG+%Ce2M+n6xx$WzyQD zjY(URPfb2E`P}3SlP^uaGHGYh-lT&`N0Uw_olUx!d~NcLNybDl5lti$*+el>O*9kT z#4s^UEEC(rF>y^i6W=5-2~8rC*d#GYO}d(NGwE*9!=$H4FO%LTeN6hA^fT#iGQeb@ z$sm)#CPPeynhY};ZZg7Tq{%3g(I#U|#+r;X8E-PdWTMF=lgTDiOs1MlGnsBO!(^t( zER)$Lb4=!%%rlv9vcP1a$s&`*CQD3~nk+L}ZnDB;rO7Ij)h269)|#v{S#PqzWTVL@ zlg%buOtzYAGudvk!(^w)E|c9RdrbD4>@(SKa=_%E$sv=&CPz$;njACv*5tU!36qm1 zr%b*x`QGFQlOIifGC6H>#^kKYIg|4y7fgOO`NiZ{liy4(np`ruY;wiqs>wBz>n1l$ zZkpUOxovXCzlk=^1Mi)SsKvv}U(1&bFgUb1-E;uVWmEnc&D-Qo?4H!a?>c-!I~i+3&F zvv}X)1B)CMIW2No1m5*8&bN?DY)C}UC9 zqMSu}iwYJMEh<@5wy0w9p~XiQA6tB4QPrZFMRkiB7BwwuS=6?uV^P2#i?1x&S+uw4VA0W{lSOBX zE*4)~d}EQZ5G+Is$wIbJEL024Lbot1Obg4xws0(53(vy02rNR2$Rf5#EK-ZE7Tqkm zTlBE#Y0=A~w?!X|z83u~`dbXJ7-%ubVz9*!i=h_7EQVW*uo!7E%3`#|7>ltM<1EHo zOt6?}G09@G#T1LF7Sk-ITg%i=`IJES6iW zuvlra%3`&}8jH0S>nzq=Y_Qm9vB_ey#TJXL7TYYgTkNpdX|c;2Pm8}S z{(wNvaxL( z8`s9O@ofT|&?d5pZ4#T*rmIaio9;F}Y z?%Le5xo`8p=Aq3ao8N8zu=&&GFPpz@{;~Pj=0BUq9B_Et;R%N)9iDQ?;*izhX@_hM z*&Uv7c-G-Lhvyw$aCp(-C5M+CUU7KU;WdZX9o}$w)8Q?Lw;kSbc-P@QhxZ*maLD11 z(;=5bZihS$c^&dO(I}kzrz5BfewQl20ILK80s+0VYtHxhmj7W97a2gaTx0`&SAX61c!+ZlN=^H zOmUd%FwJ4Q!wiR+4znC)JIryI>oCt@zQY2Cg$|1x7CS6)Sn9CMVY$N!hm{Vi99BE5 zaailH&SAa728WFfn;bSfY;oA?u+3q+!w!d?4!az7JM3}T>#)yZzrz8CgARur4m%ui zIO=fB;ai8}4ksK=I-GL&&f$B99~^#k_{rh4!x@LO4(A-sJ6v%1+2I$5UmbpPxae@n z;j+UOhpP_P9IiXuaJcDk%i*@e9f!LP_Z;p!JaBmE@W|nJhd&(tbok5RZ-;*z{&o1z z;V~Cn9(Q@dDdbYvrHD&Wmtro( zT}rr=bSdRh+NF$3S(kDyxqR&MiAzhzy1I08>F(0QrKd|Tm)857bLsCgz-6GzAeX@|LtKWs409RoGQwq~ z%P5!8E@NEAx{Pxf?=rz#pPF*-&`)bTynYWa>eDU%QctlE;n3my4-TP?Q+NEuFE}_`z{Y$ z9=beo`Q7CYmp@(pa{1fkAD4e!{&RWE1CPf&p740m<0+3U9$7t}_Q>Xu-QyXLXFZK$o+v6RNcRk+oc;Dj#j~pI3J#u;E_Q>Or z*CU@tevbkk1w9IR6!s|MQPiWDM{$o59wj|Wd6f1j<5AY5oJV<&3LX_bDtT1)sN(UV z$44F?dwk+i)uWn6b&nbzH9cy1)b^<3QP-oMM}3b59t}Mjc{KKD;?dNjnMZSv79K4< zT6whgXyeh=<5Q2%JU;jM!sAPiuRPj$wD;)X(b1!mM`w>N9$$NW$a6DWO&%^f!JVKAiBlbu$ho z%vCCt(#~zQp9{W7@dmQjM=yAy7u*VUPqaMdRzV$fn zal+%I$0?8RJihn%!Q)4dpFB=`obfp8an9qs#|4j{J$~`{)#EphiyoIeE_+<@xax7u z`dBNvJpO<`I_IbtURiD>`M@WKPfnj)KDmAJ_~iA;=ab*3fKNf6LOz9kiue@uDdtn$r-V;QpHe=h zeaiTh^(p65-lu|3MW0GOm3^xCeCYF$&&NKW_*C_&=2P9LhEGkOT0XUX>iE?4spnJQ zr-4sHpGH27eVX_*^=anQ+^2<4OP^Lgt$o_~wDtMa=QE$reZKJd(&sCmc0TQWI{0+- z>EzSdr;E?mKHvCcd;}lSNAi(<6d%<`^U-|_AJfP3v3(pL*T?hmeFC4*C-RAX5}(wk zt4}wd?mj(ydiwP8>Fv|Ur>{>xpZ-1rd@&q@s?Ri^={_@jX8O$Xne8*jXRgmYpZPuud=~mF@>%S&#Am6` zGN0u>D|}Y^tnyjyv&Ltw&pMy=J{x>C`fT#q?6bvZtIsx{?LIqvcKYn{+3mB(XRpsb zpZz`ud=B~?@;U5t#OJ8bF`sXJj{BVOIq7rC=R2S8eSYxy(dQ?h(>`Z>&ib75Iq!49 z=VzZ^e17%$&F7-eC7;VaSA4GeT=Ti^bHnGR&n=(ZK6iZX`rPxm@AJUtq0b|q-+lh@ z`P1hwpTB+n@%h*1KcB|}2zWf;iGU{qo(jkkkTu}xfNTNT1D*+ZHsHB{=L22{croCm zfR_Va33xT&wSd2HUVt| zJ`MOR;PZel0=^9RDxh6J`+yDs9RoTAbPnhe@O8j90hs_HKn#!qw^)RtKyJSR1e|V12-bfQ#} zc{(IpNcNCtLY@tIF68-;7eZbPc`4-OkXJ%p4S6l(^^iA0-VAvwrygNY#*PA=N`_gwzbF6;eB-PDtI5dLi{g8iX_qX%x~p zq)ABAkY*vxLt2Ei3~3e8I;2fV+mKH~J`4Fgq!2ko2~k6|5Iw{QF+;2nJH!cbL%a|_BnSyZqL4Tw2}wh`hI9+*9?~PE zXGpJ*-XVQL`iAri=^rv6WMIgkkij8CLWYJ63mG0VB4lL9sF2YiV?xG;j0+hbG9hGQ z$fS_TAyY!8hD-~Y9x@|jX2`6N*&%a6=7!7*nIEzsWMRmnki{WOLY9Us3t1krB4lOA zs*u$oYeLqBtP5EmvLR$+$fl6ZAzMPWhHMMj9-v&KSTZs`8(vF zkbgt|3wbPph{q$IhBML&wG>&Kz(KMo2MDvIi5iKKHMYN7+6VW!}(}>R^K9Be! z;>(DyBHBf?kLVE5F``pM=ZG#5Uq^fsk%4lBVsgZkh^Z0NBBn>oh?p5MD`IxUoQSy*^CIR) zEQnYbu_$73#FB`m5z8W$N34ig8L=v2b;O#8wGrzg)<`y%#79Edm=aVX+&#F2=j5yv9FjW`~0BI0Dksfh0)zK{4J;>U=e zB2Gt~i8vc^F5-N|g@~Uceu?-s;Djrla@vzX6gzKHoU=Bt=?G3{eI#B_}56w^7TOU&0X-^65MgcvbK zijiZK7&S(V(PNAlGscRsW1JW_#*6V|f|xKSiiu;Am^7wqOt+ZsF+E~>#`KEm9n&YK zZ%n_K{xJh$2F47E85}btW@yZ?nBg%aVn)V{iWwa|SD9Wy6pZp^%x`7sM(7RD@!Ssb$@W@*f_nB_4mVphhiidh}ACT4BS zx|sDb8)7!bY>L?&vn6J0%(j^AF*{;*#_WpO9kVB9Z_K`!{V@k(4#pgcIUI8&=4i~Z zm~Uf_$DD{c8FMP;yO{4|eu()o=BJp`F=t}V#+-{eA9Eq*=a^q&evSDp=3>mHn9DI& zVy?zqi@6?iBj#qzt(e;}cVh0w+>5y%^C0G7%%hm!WB!QwGv=?DzhnN1`8Vdjn8y-G zcs${WgeMc8O30FsHR0)mYzf&Do=JE%;kkt86JAJoG2x|zmlIw|cs1d*gx3?^NO&{h zt%SD|-br{j;k|_S6Fx}Dk&rVXS3>TDJPCOd@+IU?D3DMvp-@8Mgdzz=6N)7iPbiU4 zGNDvL>4Y)~WfRIJluxLTP%)uWLgj=i2_GhWl<;xFCka&(swGrUsF6@Jp;kieggOaz z6Y3?@PiTGb;36ZnFJw0Opp@f1SLUD&=T|nBf(6t66^#g!AC38NB5 zCyYrLn=me6e8Pl;i3yVuCMQfun3^yxVS2)hgqaDm5@sjNNtl~3FJXSdf`o+$ixL(m zEJ;|JuqjR~6)HYaRJ*qX2{VSB=kgq;by5_Tu- zN!XjPFJXVefrNtzhY}7a97#Bua4g~5gyRV(5>6(ZO873}`-C47eoXi&;dH{8gtH0f z63!=FNccJ7mxNyveoMHRa4F$(!j*)p3D**?C)`N5nQ$xNcEX*6y9xIa?k7A*c$n}g z;rE0;68=p1E8*{ie-i#p_%GqH6jB~fc_QV>l&4a%q-0HbIwf05_LOH*o=tf!<@uBs zQeI4XDdpvqS5jV0c`fDjls8h|OnEEi?UZ*?-c5Ng<^7ZoQgWo^Ov#m!J0(v_-jsYP z`BMs{6ig|UQaGhZO3{>JDaBJtq?Al4l~OvTOiJ05aw+9gDx_3QsgzPVrAo?&DIcYL zobpLZ)s$)})l+Ju)J&6@ zo#LdpDPD@75~PGFQA(VWq@*cbQ@W*ePwA1;Go@Eb@030%eN+0S^iLU(GB9OO%HWhC zDMM3+r3_CQkuox6RLba-F)3qH#-)r;nUFFuWm3xIlqo4wQ>LX%PnnT2Gi6rF?36hv zb5rJ}%uiX6vM^;)%HotIDN9q9r7TZbk+L#nRm$p=H7RRT)}^dZ+3-KQ&O5$};_Jir z0%8Od1+k%0EQkt7Km;44l0eGMy-6r45fBiihGq|9#je6e?*uQa7!ZA$;IDg9bg`t_#t8%^mqo6>JJrI$CQS2U&HZc4w?lzz7<{a#c0{igKF zrt}9*=?|OItD4duHKjjpN`KOn{Kbz9)n$qi=(tkCj z|87eE)0F1q`K{wDH^Z-4<4q!*H6WAH_0=t0TU{|mk;G1OWKAv_6I}3Fi-#rK@lhhC7=`x2W6lfi~u7+ z1*im7pc-UA4akBVs0DSP9*hE`!5A*0UQj*g9%_FI0Q@rlfe{lD3}Tk z1BZiYU^0o({~0yl$Oz^&jma67mI+zIXicY}Mtz2H7@KX?E<2p$3tgGa!l;4!ciJPw`! zPlBhw)8HBKEO-tq1J8pOz>DA|@G^J>ybAsYUIVX#H^7_VEwCJ{0B?hLz`Ni*@IF`x zJ^&wrRp2A=G57?03O)m$gVo>*@Fn;Pd=0(<--0#ZJMcYN3w{7Uf}g<8;1}>K_znCH z{s4c1bznXC3;YfK0sn&kKuRB5NT)$7&>FM>8-TW8Ly!kH0_{M1&;e`=HUS;MreHJB z33LXVgDzkTuqD_EYz?*nUBR|sJFq?I2D*bDpeNV?>?UU$7t89}ES0kz!31)%Wpb^XgbHO|?A1nYzfFr?C;An6RI2IfSn!rMEJXi!y04IWzz{%hg za4J{~P6MZdGr*bPEO0hB2b>Ge153d9-~w6H}E_7 z1N;frf%V`o@HhAe{0sgADSeVAod&HyYtRPpMWl3Fup!6;8-aG9J?H>72AhD6U{kOe z=ma{0%|REi1=td71-1s;fUaO$upQVQbOYT%56~0r0CogBft^7wunXu7b_KhE-9aDF z7xV*rfc_vK3;+Yco?sBz3k(KBz}{dVurJsT><@;5VW0pMf+A21NFVun-&%7J(DMiQpt~ zGB^dC3KoOY!0F%&a3(kloDI$a=YsRV5^z4a09*(z0vCfzz@^|aa5=aFTnVlMSA%Q7 zwct8%J-7kf2yOy5gImC@;5KkOxC7h??gDp%d%(TmK5##H06YjD0uO^nz@y+XuoOHF zo&ZmRr@+(T8SpH44lD!DgBQSy;3e=fcm=!){s&$IuY)(ho8T?59IOCugLlBY;63m@ zSP4D=AA(ijBk(c!1bhlU1D}J{;0y32_zHXtz5(BYHQ+n&Jy;8V06&7Cz|Y_p@GJNY z{0{yAe}Z*jJ@^a!4gLZDg8x8DUv)~SK`YQ2v;iA{wqQe$2Q~ujKzq;uYz#I59l@qx zGtdci2AhK}fNw~pw**^(t-&^+E7%rn2et>@KzGms@YSvK4q!*H6WAH_0=t0TU{|mk z*d6o%eL+942j~y-!2mE2>ey})2F1ndp=0sDge!2Vz;7zPSJAt(aHpahhH;h+qZ zgArgPr~s9q3RHs(r~z4!1GS(I)PqrAG#CT;@LKu+a3DAci~|keU@#s`029F>U=o-N zrhr4iRB#wL983e#!3;1H%mTAPBbWo`f_Y#*SOAUyM}nik(cliz(5x5v!0xkuYfy==a;7V{6 zxEfpot_9bD>%k4+MsO3j8QcPH1-F6Q!5!dEa2L26+ym|f_ksJt1K>gM5O^3o0v-jA zfu-Pa@C0}gJO!Qx&wyvab6^>G9=rfv1TTS?!7JcZ@IUYxcpba}-UM%f%m{(Z}1QJ7yJiO`g~kE4O)TLpbgjnv;`Z2Jg^aH2ik)UU}LZe z=m<6in}JTCGuRw-0b77A!B${vunp)6wguaP?Ljxt9rOS_!46RC`Kp`js#h?U~g5jVH zl!FmqB&YzDpbAuj45$HFkOQ@#4%CBDU^Ey5#)1RDf#4u84m5y+!FVtMOazC3NnkRV z0uBXJ!C~NVFbzxxGr&wR3(N+MU=ElI=7ITO0XPC23626sgJZz4;5g6(7J}o!B5(pY z5u5~02B&~i!D4V4I31h;&ID(Hv%xvwTyP#(0?r2)fD6Gz;9_tIxD;FlE(ceDE5TLZ zYH$s>7F-9e2RDEl!A;<1a0|E<+y-t3cYr&=UEpqT54acH2kr+CfCs@t;9>9xcoaMa zmV(E@6W~ek6nGju1D*xXfo0%%@B(-dyaZkbuYgy<|G;bDb?^pw6TAhMgB9Ry@D6wv zya(O~E5QfgL$C^b1U?3zfKS0^;B&AVd;z`$UxBZ|H{e^a27Cv;2W!C(;79Ni_!;~H zeg(gQ-@zZ?Pp}TG2Y-RT!9U<%@E=I&yS?c&Xa!n>HedtL7HkOez($}QXb(Dojlm|M zBiIyd20DSxU~|v~Yyq|eTY;^?HlQom7HkK$2i-t-&;#@YJAfU*PGD!y3+w`VgI&RH zV0X|5^acIE9-u$S2Lr%BuqPM<_5y>!5U@Ac2kZ;>1N(!aU>GO>g`fx&gAz~*hJ!Lt z4n}~HpaN8aDo_nFpax_?4%C7=P!C3d(O?W13l0DWf`h;~&;SkwcF+yHI_H-VeME#Ovg8@L_Z0qz8MfxE#y;9hVaxF0+K9t018hruJ@QSca8 z3LXbffG5FI;A!v-cosYdmVxKN3*bfY5_lQB0$v6G1FwPC!5iRB@D^AOR)Dv`JK$aL z9(W(D1RsD8!7A_(_!xWwJ_VnF&%tW&1^5zt1-=H~fN#MX@E!ObtOY-SAHh%HXYdR7 z75oN%2Y-M+!8))W{0067|A2qNe;}oAD5uk)6=)6GfDJ%fup!6;8-aG9J?H>72AhD6 zU{kOe=ma{0%|REi1=td71-1s;fUaO$upQVQbOYT%56~0r0CogBft^7wunXu7b_KhE z-9aDF7xV*rfc_vK3;+Yco?sBz3k(KBz}{dVurJsT><@;5VW0pMf+A21NgE3$%H~<_74g%vq12`Cr2NS?Va0r+LCW9&9 zP%sr71`Y?)z;rMJ%mlN*Y|seifVp5Em=6|!Bfyd1C~!151{@2H15IEdI36qlCx8>d zN#JB~3OE%k2B(43!5QF8a27ZloCD4U=Yb{Qd~gA{5L^T<2A6Mn%1Go{~1a1bmfLp%e;O7x)|e1O5g7fz&BN8ngnfK^w3EXbUz3d0->Z4zvdyz{X$`&=G73 zHUphNXRtZw0=58Kf~~;TU>ndCYzwvn+k;v`%`+@zzP%sP>fI?6Nia`k|1;arZCd zg2TY!U>cYXW`LPs7MKkh!5lCb%meem0&oO45*!7N2FHM7!EvAoECk1cMc@Q*A~*@0 z3{C;3g2mu8a5^{xoC(eXXM=OVx!^po1e^~p02hLbz{TJaa4EP9Tn?@PSAwg+)!-U% zEw~O`4{iWAf}6n2;1+NzxDDJ6?f`d!yTIMx9&j(X58MwP01twPz{B7X@F;i;ECr8) zC%}{7DeyFS20RO%1Ixhk;05p^cnQ1=UIDLy|AE)Q>);LWCU^@h2P?qa;2rQTcn`b} zR)P<}hhP=>2z(4a0iS};z~^8!_yT+hz5-u^Z@{-;4fqax57vSoz>nZ3@H6-Y{0e>p zzk@%(pI{wW5B>swgMYxk;6IQ$RY-$YpfzX%HUMqGh9D1Y1loc2paa+#YyvuhO~GcM z6X*;!2VKAxU`wzS*cxmDx`J)Nc3^wZ4Ri-RKu@p(*b(dmb_Tt`E}%Eq73>Cf2Yocd6U+j$K_i$0=7M=(K3D*b07rtOz|r6sa4a|uG=YWSc(4eZ08Ruafs?^0 z;8d^}oCZz@XMi)oS>SAN4mcN_2bO^I!3E$#a1po|Tmmiymx0T{72ry66}TE)1Fi+v zf$PBy;6`v0xEb66ZUwi2+rb^+PH-2v8{7l#1^0pb!2{qy@DO+yJOUmCkAbD&aqt9q z5gr z3O)m$gVo>*@Fn;Pd=0(<--0#ZJMcYN3w{7Uf}g<8;1}>K_znCH{s4c1bznXC3;YfK z0sn&kKx(m&2CYDA&<1P(+JX&19@q%91MNWvurb&KbOf7%%|Iv68Eg)^fGxn5U@NdS z*amb3+k)-D_MjW+4tju|UUQ}UzYuzp{b-}UzpBEGt=SGcboNj*pV~f1hqy^s3rIoq5!c1=9 zbbIR;HqA@1iPXPANw%^)zeepl%G_fAZSqnZ&GjxQs;|xE@^j^b209NpeB->-gVVU8 zvT}4oCYP-k)i~AMVXL-zsZ2G$msjN)GU{bXO-*WHyHEt{C8O*S-V;izD%Fcj4jIhP zAJE^C!~L7(rFNLgbzwuCpHFI)mwL``XvyeIekM2F%6aEa@=|N&cn{&Pi}Q22u}&{4 z)r(DLb3v}GK##A?4bOKjm?csFmE{7uQLk=PmDDs;*JN_0FE?zEm)g80x~Q_QB2#RB zexh|=ib|c=4kT4PcDfbS#@+H#jeZ}B%j+eF{`rHQPOeZZN$|WIWOFsy+Wf(poE_4R zJ@Qghq+0$XYD;ppRh2bkotwO*rxYFST_BAtt|=Ha(3Qmvo9Cr2@g!YZR9!hB->TGK z67xk<_~XKgqRQOJ0j`wRrSeiIRq``ZDy*)nvi~{YO37PcYlaMFm z{sVoTOtke|we@r}T#l5#*IjOC^zPy7bmR01rVAT($V+t&^sS=*AlIztN!PAE%#-4b zxzaUhY6*htEwa|QJ!)tOqO>%BH;pPIkbq{hY> zGaKfnQu3gvaX6 zD6JdB3ajLN>9@={BD%`eD~sLW_!%&)&m_lu)G*XN1~YHLff#Tl#OYc(ca zY(r2kN5dDWDd!*O4@zN0Nma3&w&O5=-!d;%YcHrQ_8oz9n+J7OmkMr^Eg9ZWlj z!0EWtR}?vGrQAo3VEX)^8)_rn@WPMdv|jI+m#Tl6`eJ@E(@V!>9wxQIGl+Q`?=fpX` zoPpEN?WDBNM@s7@q4{=7FiV0S?OR<{vGPxwBR{IZ)S`wVYp_%@jMz|B>X}J@h~d49Q%0k-B`Y^+M8X zxe#YsvX6#in&T2{TF59~lTZ9M2vk+YRheQpOjRgMt&g)GO@K-ZDsm;xgRYnVU+<(@ zUJ#j&mAL`uKy_;;-afdU0 zB+zbD?WnxZ^r<$>pQH?gvJ8zR zLm!auWaz`CjO@Jf^&?wdTjQkPm3judg#-1euFusJPIt-&e@k^XOSnC6&S>4<9Qlh+ zjbFm?d5vuz?ur!PuZ_l7LoEN~3~+_A`n~#&Z=BvRebV%X3FGC>CpD&03%hkveouzK z#<(wU9-pwRN;RfS>;Rb|+a%#hX=-uYhwW~W zY>OS)mPxkkrZ%!2)x+}XbU+@oEa5h8Q`P16L-|poNM>(Cz$Ws) zLv#E%Jez44P+V0#Dz)&Bupo219$xLJ_9)+5Otph>k5qep=(XfWtK?{He0WdtIVwqJh_P-qlhDcXg=a-)@zC> zm-rKIg)7a5bG3We@%&5P@@Q%PsQ z9#DTKhhZ(DF)vE!gY1YWyzj*tZ1zw2k5~3wuM4ca`zqwKw=`^@Z#TAw{nW^lt-xz! z5_U+xmR)`7dCd`pB@LQSMrFz(>FOuZ)Vs7?)v2tJ&1q`bFQNC2ICn{`9z18Z*4a zd2U*{aj6%dM&`=OOKY=kx_Gl>x=|R|6HPu`54|ght%8GT&KxnbaTZGMPo) zD0edTmZnMFqB!i?O{2PPwc&Wx&^`?vL{9b}^{Pm>=U4*&_TF?+&c&S;?E}0!?k+Ff#Y1HX4>O=9+w&?1oY1B0rw9_I8h2aYi)WV=622hnNw6NCK*j zby;!3_ffVD4@#Yn4BM!ws^`SqAn}2k*)6<8&u?s$)tV+Auitk`#8*iok&vIJn6`OB z{dJ$_;dQ=DU|-(^vL&S@wMAuBwFTyJS4v~1g&sX;3;nOjowK9B86q^y-Sbl8 zqv}~*CO5{3c+aYQwm!(X{5pH!OTFC8wBkT%MoBznqim9_dfcQb+Zw-4HlG|?f-^U$ zR1kl})9k{E95!P|rK_y*-e}b8{fU?}@(1eATL;-HfrZJQx%(ugsegOVF7q-O=f`nm zx;CxMN$F(O_2vezN$)zFYdqcbCW2Nw=jp1E;aD(>ux+?Q!|_d2I8s*cr{&g}j+E*= z*yxRy9uQw*gVt6`sfYXefXgcz<;-+$kv2?^oIs{jy|qqvOBqP9GfZxVdZWf@bWmZ= zY8KVl=qw#Qs(80i6z{aykS&lChzbYy$va&cdHf=#qe`%&pGj~g1TEJxhBFU-PVHW3 zMwqgg+O9c(6Oeb+Q0db?>!_$#O z$w18QarnGS5bkGrbgnhc_iP7qzMAj&2c?=eBi zhdjkt#{o(-P7E)JJx#O1(3jowQoO|zwOC6j&2qed)aEyWDOzz(@{EE^zFIQdtev#r zoR_PR_evO{+^TCIjniM*O|GK$-n&*#@dERN}D&B<1@t2#*t8e55 z_v&n-264Cw-|WZt`;O%}{%=F2Vz&joE*hy)XwhJ+2pg;GtmO08qoqpj65p_%c_}sz zc=sM#lC7@GWJ+ZBk>qyO1^>i-a~)HIx^;b|#+tPlp;XE9UJ;&}ZKE7Vxm!GaPe%7cHPQK>$pPvHyNhJ~ z6j!f|G}&9UV!6_>-IVG{yc-cJj7n~f#_S@EIVP%CgzJ5db$=vxIlv2h#RWT+YNGVq}ZPQVcVKSf)U6 zmlJSpFE&%Cz0}WGmPS*);{&h?(?S3m^+v?&F)^sV^N%m zE6TaWyVXjQQ?XT5*N+{oD{QML$f7nd7A1e6xw0Pzoyp@AnbhNfQPgW{s`Z)Cj)HWP zH7t+&Pc7d0eNRc?G7}!khgT)%SpUc~bq%K^WWz>C$4Ze#$6ZxB3*9-#qw4F9-t+y% z#AbE=leL&QEgE2=kJi;aFXImLYZ~T$vC!%&yuf0ba;{`{rjePmcw-&J50Y7#aW%5@ zk{au2ewNOyh@3>Oq_)b=vyPKqToL;-wVan14= zCe!Bz9LU$V{K=nEPd_CCm;dPQ}Hpsw`I!Du{n9Y$3K^r%V191u=gBU0dr% zfcA~u&&Emz4Lri#Y_h2;NMpPxldaayD7#AVn1akD#^bQsqpG;$aEdhe9ixP?D64^u z7SQ*Ww(}}kStXh(5wnTkYl@qxnrE$6V+Q$gv!qBVx%ug0+4mvQAdV_5uW~GR z6E&b+q(i0U8bmX|_v?>&<=q!Vkg+>S(64e+N5x|Bn(xZtL&@QqAPKFgE|7aMt!qvG z={tOHn@FYaD-+stxV-wweo|L5x|Yed?cvuN=4yYK%d&%=+SNT8<^3Y*MFnbS>%vu% z-M&`ASeUiz8&^uhI!0Pf>|)Im6}MN-*37JHv}j+O$>kR(x92E!^$XfrftPicEYDS2 zU-9c~<@u#>*5GZKaI?jYiKYD`TC3ovNpc)z;464!=te_( zD+nB7)x(>!nhTzndR$;up2Ez=b%1{;IUeF9m|?^)x4KOE<-2|?&X&}c+j`{?+3CTt zudYyO+>ymIYUbC`plO?rGtC>J^!?*-9Y^8UJhMPTd@KBE&_H*C(m?(X>zpnAOh z;}v@9b(l`ojP;IoZQ@*jpL_G z8aA~5(4h?t(`HT_KdoWT+(V|$Y?w1~{EW#BGyThk4I46SNb1y9saCD?y7x%!AWs@j zq!au2ddQ8P$|c=?G@ z-6s{E>-@`&N)d+8|B%(5^*lx@?lev#R_(l z{M&eY|E#jVpcsCTozN*%x-*g|HIr+M(oTP8PjXtgLOD6-TlhBV?XFMgOc!0jsn-4# ztZcFA(;4|1snyDOetG*p(?8l725?#$}9Z7Fg%e~)D+h^ zYW$P#z_C4nNVU}H#Ln?@bANd@SXN=Xd5}_zW#0cU)tow0X(Z4~KXr;`+!_C|#kSJE zROYr6+=ySC#NISvoV3HsgUmU`Z1~6j>r$mbP}vNpC*9&c9UX0_Pa z-^|r0;iaP=vpE&Iqj}u!`t3R69i$2@Z@W8?cb4gK#Hc@tm71|OU(p+&aI|+gQ;;uJ z1ELb+<Q(m|T{GQ4>dHZ6{!O&wO5L&3r>$gVoN^sJL@vHC z=#Z^-4V8$C!g%P`H*e4oZ5$L^s_Qc~<#T5y=7}?vh;Hinr4bot<42>Ewu@hT(iGR7 zJ};0dzY~f{iszRuJ$J?0oZHF4@>p}tpphW4JP(#0ee36nG|Aivkr?1tgMrF3&Y)`f!mh2CX;Aw{QHWK;vf?_s==+{z$D8BcO~T&VcC?nkY#%vV-C^wLQL5P-FC7%hr?JPqMen=bOmmC1;2uRn&{Mcu8~mMg&Bcl z;*}))#Z24QX_9P>KSE=*O*fH?+@~SxJd1v0ODakVawQE?HWuDYhvq5S9viz!c8R$q zoTbv%Ii|;TnqDW0L~pCFyGI3Z)|<7UY@TtJG`f}l3})4iM>|BfpB=eY1-e9NUM@9# z-6}hK97f5Uq8%znO4%DCZ>Co%98=gxqj^c3!iMz+>&*UA2D`OUt4y(8(6#>ZXk}a+ zvF#hIx62~w?fT2xwesWS@M68%W$%B8lHgAwU(c9JDjd@#1 z;75N7$U7~r__F%3-iSv6v;j0F+02gu56xm>BD*{z+=Xj_#0lV47Sr1zxz{pPkx2&(!*$F0^dYqm@6;V95@=_B^tub<0O$C z&2G4uuO{9X`g)~q=%;C27y0@L&SnSOvghQe3;rMXOsc$L1B1~O%% zlDAXQv}1xoQl9gq77DV5=_xz8$G}#o zSrEwOgSjIv!c=FIuSay0bsy;EvAiBp zk}Ws;X|7a`%87`+_C-|_cWA#;j=I=H8E@UgTNSe-yhhnXQ|v_im;Bk6Wxdd+G8I1Y z5m>P|clRpruD%b|9FuQP`IqUctXs(WP07=t)*hmAqn-D>EPcN(8f)Ks%W7KKjnYN> zcZc;pxn>(^J4z>JxE{Q=+kx;oPLh4TzLSYu~QZzd(x9#R&?WP+^+8Kv98@Hw5G1y_4k(*gqPHU4roC zu2Y?+pjF{(yu5v#rhB&ecS_?qI?=mvP(AXd`A+i>)Z_a^iL(5rHi6>ToKn=;s!qNi zM~|?EX?n4buGl5AS9fFZX)@T(aSye2QRwE#^VGxplf@j@#I{gyT5ZO{RVBwkl`0v? z_ztSNUN3_=%5kq&V%CgABrHFa6xl5dTgVbSB--g&h9j^UYV7rnq6YbhwZyhk)ee67 zqq-sA$Z3Wm(eB}(WYmj5mgbVPWb4m`Zk&|eYlFF9XF2lrMivUx?!;!gRC1+17~X7E zuN_+h*;nrBk2usS5NR=yB778Tu91(py&{y-*u<+6?@CVPQM_cMLKrbkBX3hC@P%vn z$rAi<*;h8Q9B)I5qrmsebb7k7@*=J?94AUz&sb|8jJ%wp@{UR(Uk+DY6L}xy&iiA{ z4v$N6lF%)r+s7u|s;izKOJLJtr|Q)#y|!9Qe@%h!YtN8X!!EHSGC~$o9>x9Yx>{bJ ziALiWg{LRX6tdV+_wE|(W&T|Y3kN$B#9q4XzJ3L-LW0$gD)N8qhZ=2mZE2cQper7CjRh_CUtV@^)=fs! z+P7_G*lrzalE(WMUrwb}1w}=UoZ3rHHNF;C)z@dr-MvBgX{a~xG8E*%VN|u*I+faV z%8L=k!^&ftB2fkhRIo49T+>^3%8z`<$N^?;;ULL!Vd&W?$+jS@&s3zGYYno6tsCzs z7(C<))K^?NxFg)1Y+FmBW&T=m^MxwTu;5HlPi4Io8@<|Ot)sU*58u7;F39LL>OyC- zSg1t%U*90j5iPhK;{XqqU2fz^v}$;5vUYi&1bSUnsD7?$R?6(pnd3Eqw-J(Q^v{~U zpXx8bvQJAQa6LVXc^Si(j4SQ)!`wk?*bA;d>O64Xuzjc>!`491`*76QfzP*>) zH#MG*XqOCo&>iReiUh@HO#DW$F+73k%2f3{Y@JGY9I&gQ!b;1 zW(TXUR_`v(hBB1qsz&UTqYEYEvC#!AM>`eLHu{+ZA-zWWRX(j8Bo^A zKF^JnTfGQY9ZA$Z( zM<(i4i1(CVWW6SRLnQYOAf=#+W!R%jx6fo?ae4vO4SL4Hrq*ceWG2a4(@VJ3CdXIM^9LTj@6HcBzK(Z0|`G)p|vX zZYIu1_(=~u&CAB{*R~S=opkL2XRfVY*y`jTnrt`5)kzlS5__9h$cepTb6o4G`$$z= zMXui8M=;h&A`g)gobM}9MUl7n)5`dF{XO4w_S8sDLv{91uAH})v3(oN;4}>Wa&oi7 z-zpThmqw{Uw*LV6p2z{RGjN8Thz2H|+$r;hvhgFWGgi28&XM>)&X|wGhONapxRtQ= zYVDc6kBst7tJOcqO>X0B4TWI0tH)><+xmHw4lQs@=};+h&nS)8yvjX_ee;#8l`w%(~4!XmGw~zGrZ+&y~Xuv(79I5ARE-um6cXz5w{_2kf_Mw^Y?Y~X86SDtNQN@_#TPHMxap}o4Vq88~93lj?N zrd6Lw!&^B{$&0jMRm~RQ4v||b39^2>q3R~7>S-nu2+n*kau_H*=hIKV8F`!E60huZ zR6qH`n|}p|4LMG$O0Aq1I9T54*ZEJ5Z+=&<^(fzCmgulg=T!}kvf0vFl4;n}8saI= z0BIc|awF$SdjFY@@-5zJ&z&;YC1En8ixLY*zxB`=4JL0? zgB9R?$6*!jSxraAdmdgx(JX6xR#M{|-m%a0w#S;zd@i5a+YiG^$f%+u3aY0o5cl_; zrq);7Si3|*zq5IP&zt|*MsBJA@p>HReCJ%4*ssuEX(&gudu{bD(NRTi!rnm%dx5b) z4kUI;Lf5JKyT2{s{l5luwFYtRNS@^t3`;8thAVf8)NN}C?$E%Q>W!_ObE4hL@}^t( z`DI0|{wkU}9U&ENh&+%6KV!4-jdaf+%rX)xX#TiHZO?@MJ2C6KS5G`5OyF~)*(7Zf zft3;+UnBB|Ieyp5QSfbL09%Cj7&Op%ee4L`;CSC=Ref-GNPn(D?&P;CSY}PWLpN8g z`z;z4<`?dPBBSIK>-|(1ryNv1-8sg?N`_zeo}vS=oD)s@tNL-2U+v1srkxr4hl&~( zM;T1TSe-kmE1YhxSB~|s=P4EToGohyt7Er@(}ezmraA`=b z@#GtzzSRBgc+RwNTY1W_B7cq}@U|=46s%m%a{F*l+&2>!YD}6UW%Aza(%~EC`Mvf0 z10$Emi-qzbiHXV+8uWLJ8}S+udlE-dgXNLV^<#>6n6$T8Z8h{41(&Izh5CMtN{^Fq zz9PT%PdM%H&SYt!7}TIj_Yb~8kTVw))s}k&1ZxfQYqQ;FCHKHA*Q2^c8HZO#v1Qrg z<%pm3b(+jw?ZrJ>v+1Ga`h-9Ms_Uy|RkpWZ$e6E>v^JO)n-;cJ3p->Pe6O^YVY9j! zod=~|$5>YsIB*3Ms{kL#50%@?!bMX@lWx;hm7$s>Urf47igISGC}Yd4lI|rX=^MEQ z2_aaRaBhE&B7PqmCR9}NN7m*XXDd|P@&9;xBbSbH_8*0V%NrRAUCq>Fn1q*SX9dx* z3dse%!!$1#7DZcLJF$awtp=H|fcrM+t-X&*yfQdQ+3R(Fz7m`RWaYnsZZIHLBDVx} zfqr~7n1jnH+P~{7?cjT6-h;y_xVq`q*~ZBHo`|}sJ&5_m@lBeSkt%eHj>cQHG|ibU&3Ve3n_3wGExkjVK43sU237DBQy zg1wcgjE`c2zn11Y%4a3f*6|how9Cy1Ch3x{fojC3<#|&_n_V3%9a(O5#M?fM%{e8H zJ=NlgQA8V2ZB%4qDRZZ|IFC@0Y2aL0_2kg6>plJ!{KJb9+p3^wRFW&Nbl)Nws=D_3 zPWFS#x3;{G5}=p-B@lddvkC5Q%0yodM}Dxo7QMShe(%shs+g8>M&ojM$c9KSm=h&7 zl|L=5DD{1oigh}^chJCQAO5&m8Ok4C9>NXCM9g@PQE0r;1PkZKJgID9kl9tZFIQi$ zc0U>vXuK29tP*XjVaY}DNy_fr^#T3L$8beS@y5w%eTqo^1 z*lM|-oYD?)| z8NsBBT`-PSext^G=x2x}wFS;P>;AgOG*2^FdUxk2uc?(k`$DX))a!p%z?_fR=no91 zjJP{IR%mE0a{M9{RBL$awA8XwY&In|!Rr>L^QXvcK1kYTZmeUN`^hjr3-eH3j_f~3 zOPSH6qF9X_64|Ye9;nC+H@5q^0{jP2@~strjdG&yzMt~%kygafJ1XWecSyX?#&a~u zQ59)-NBK@NqgTBddUd9uys|R2a1Wj4t035>70VoFgtK1#t!E*TI#`*nRhD^Pl&zE& zmD!YbU)`p==}dw4_&8yAk$l7zzDxA1Q0sg4=KskR9%ofDp26G8K9Nf9W+uJO)|Std zt684tj+uZPvF$0b9UK`x6IN$zpOMq}+xJ<)NAN`oM zWwg`v^KNlA!BUhv1ZOIpxXO-@)1kB?{0_dQR%bN2rd21&Q11=R0B@Gi;>~3TZQ}}% za=j{@5Mf$=w|wxwQG_7~xZ(6*>CXS6^rI-b_|#8LyV~>brT%Nikp=4A_!Qr7^L(jh z*Q_dAdG4fv_$+Q2FM7z^nwFg*fxi;vXTc#0nbQ953orBZm={~P%B>Z&R6RpI8b%?dg|{-a(7@~pp?I3l=lYZFq`eqmN*)N<=M)N*X3kRutFjIRnL9q zv_-`k=f3jDy^Tnu+1kfu8py`y^CKOsD7FK+zaraRj_1{3SjmiZGlj2jqR|YC3Qoir zsV;2n&d};@LFOS1%gs@Cu6neN)l5{s+9@$OCrB4Fxq{+CKAdKkaDJ9=eb|p~b%g`+ z-9_7NMavI2sjX5e8O2s{QsCv%$vN#&$_mbolWBK`@{`i&zEN;Wo+fgR zROki=1coADEcUuj{T9JC>dHlX`^%XBlve z>H)p{DwX^!Ik9VVi=`G1xdL)_hK-kiN}^?ktn)RjSqg3qVGoqW1oK?0R!>Vj=fq7M zUYm^gKWl6^szwHsg>bz&XJeW~cuxyPYM;?rHagZ(UA8bg@3<|M+CGp-P{ORvaSB`N z!at*VfNHDWm&g*IZyPIHxy__a8WtXC#&%<6ZI8yrrc#%Ch|RY03H_r|C)r=i>CzH; zvY%r2qaaS4HXi6Q4d2mj$Gm+7&8D-f)S|C#n<=kyRk*v(w0?xH{n-yxI=Ro8I@Bsq z?UoCNiw$z#$4VNia~W$^Z>v-|KMEzIJ;P#UEAr*tb-{BcbJgLW=&qIF&I%QWd#%Xk zDoyMDrv#9%etUM~8Kq|!RwLHSFn)=&COD76xp|#*=18lT&F3N?NHa?vwF(!at^MCD zh4~~50e)f2JtUw|ZMiaz+)hL*lXm|dYg<`?K0{)9I!<~vGU|q89UjK+Soj^X@Oo>7 zt{-_=7I>o_c-F$rL-I7(m-#8Cjv>K8*g^P5S>{e*0;=VL#I*So{rpi>DNw0Puh2Vk z9;O=B>S*1lxZLjb>L~Zo-?S{$$3)3@iDn=FMz_dv9&xnpL`{Fgco>7Q=zJ<>s)ljv zpbV?(YOveV2;gW{*FUqinmFyRShhOCsH*o_Pj{|;yHe$|tvPFIEHkuX{z;Zx;~5U` zzUW)1=G~Vi>ct&#d<%=ori~rd#=jG(PiVXLDdY5%4I{hr4j*??xO?QyXUG1;+qS8V zSWZ&YRW5~ZQ+xJ>KW5?0J9*bM=sRiEMXuiovoVIx@u};iVL2~Chc6G?CO@DE-8pJf zU2(qg5|6ji4%JAmM3}&3vBYexu(u|%gS_dRHaNNZf3do}*bmU&22oZuOh?v8_LX*Y z-Q?{qjqIW*t@jp9k~!~cWia=e2-#opD^k!^x_z&xCZ&wmv5v*E|E1C7(cj)`x<8pe zwyK+W=Vr0AV*lvo+B)DE_SL%i6ze_0Q%kMjUXt@@<4H$BNH=hk0~)Za|FXfmvX_*|dyiDdWGY(_vGkYOeZ zC_UwvCi?k@cM7eur(v0rkpKK;@~V=C{zf_^%(sSm6uv4_+{jGTy1fnxO9$BC*U}E) z#})e41>PrqjnT&E15_|OBZ%I7mao}KQ)@L?Gb0~SRh{raZ%XTX`HoY`WzFGscowTC zT_Vq1%WeUqKTpaxck${!yf@E>za8(hKtDeomZzF+wCSc_`$gk6(hl2L4cnGhF!3bc znRp#3+3XbzPlbBre1zi?hR0XY>Uzf34vJ*ife`r9_Nozk}VX31)qAHZ^&K{^4Xmxix?FMXpS=k3d3kKW4g153Qecel-J zsmygDhf`6)J1eW*HDqu}YZJEwNv>9@PCg864+$Hb;8UF>3{sdo-a><6UZQtN+? z+>Dn?n6apppII4d32V8DdeXl7>%${GVHct{Bt*gWLiKQk&5D@%xY_q0B}6MC3(8Qh za0C3Hjob9ywT01cHrSPt>nd-s+u5KRo^zDU3Z^Nr&a<+u%=h=++o63|4se{^NDvfu z97TUhDRg_kau4$YQ_}8iTQv(b3cjK5JUy%hr6zW~_AhE5bbT65( z$3_O{{P{U@T}PO#E<8`z3DYZ;+r1igK#L4^uS;KbV83dD17!&rwG)@VlG*(mO4=(h zO6#1A<=`H=!l->SyE#~z|8aB+?J|(!y1U&Abc=;dPYpZ8S=l=EAvzdsv?^7SFMC;7N< zyb0%25+0Y&8t3G#-n+_niTf$}h0h~}qyAG>!RvfZQT0rk;0^9dsaoy`YbB{w^)KJ#X&k6!PWw=0-t6hdkPkabKkv(IM8WY-OSnH$w_lXVZpgXPOkjm9UKQJZIctD$)-_Lkn6Hf~vc zprUZSpXO;Nw_5;zSQ*|4HKD7j_s*-c^Rqtkg{vb!qA#vF{VP=#Jm1NZJ)2AT`uB8I zYrl%D6;34~ruCDg`}cUEf>Pk`YvgWFX)cOzo zmCiZd=W6Yb`>XfYMsrH%yHFKUjsykQLi43&8H>|laIUNme1TtO0 zv3)R{1^xL5uPP6=s4`u{_NOm!oxXJ`Ue34c%Q~b~8UyiS~3io72pZm5+)v zVMNjBv1YcEmM*MrRwlOnC{+Ml92H4CP4$Xy*3+$#Pn_-RL=~SmODy@b7hyO4|S0Y&tBqHQQQru#)O8Th1esFKU%(bbhr1P*!1=cdnG| zXGh^=w5l#fW?iKy7e(qD?N&F6xK0W@DClsJ&NRzf%e+|Ky*Zc~>$|u)XTN$o4c1ek zOJ|wwABtxb?Npy8qL0a^-DwFs(maj-j0&w{`q`;$`h=>e~0g zdr$0zbevwbhVhR`D8$&3n&cbv*XRb-QOwiC$WEb;(hWAZF)f}#JI-;wV%rn3=T5v} z(Oquu__%-mQDolNew^v@ZtCYP(I|QQSY0pEUh|ikHt`7GXtdh@rc#e*oTgaK-BC@s z-uJ-es*+~h#kRI;!PLm`MlzwdI@VdHcTDqsWUQ*~tXrHA-@^Z_u)PUOxf@3EF3MVQ z=S$pohv`ljMpW^!J?O+@Qs6T6F&XED#hc|Vi+!v1X3vhdyiqsr8Ev)X8!z7XAnmApvW?ahtWwA1@;m-`0Khidl@Q4C@I zwArg7C&@`o^y7kOLGCukWqQh{v5k5AAdT@pD!;UmotTFwdt047T#Ef^GdJkfrJLob zMe>8~Vn4`))lSszmpuN6^e^M25!Xod`q=tXa)Zg)N)CVbRV3Wryn%>L^;tC0p8}8pwSlPw*gPOktA97Rt zjW$`FCRcWI6n_T|oI8^;lewUsqVE^YK zJKrQ5Art$~PvVP9lY4Kf6ez~W6}ACNU84$H5B=elv6d)M1gEr^2d9+cJsD-++HX48 zs{}VYh^>cG(XV_V^2R{8!N;k^l`G;bvYMce*-}=v!dfk5*f$JpUfSqi;@s%U9!lrK zYy{m8rqRwtlVtks;@)X(H#ptixoVnJW4dFB{?ez-EMAu>-sBHUMR7@0y>0JC8kjcD zQ{3n=S@(a{OC`Mn1r%l7?Vx?7J;#J8Q9|`T()d(6@(N0D)-djozIrZOVPRXlNKm zNF2;Fu92rd)f02z1`<=fZ#ARXvpSq8$^|JJ7@zmC{LE9v3uvc_x2_`%GY{#h@yNHT z!yB^h#=7&RIJ?AR_l|>3xQx>z^sU@W5?{zTN>}_H&h5eyn`y^5sqn9nUGWlSfnx{t zvZuRE4kVwFIB}$tmZi_}!)8J90Dzxm^<{qas;bqiACVuqRq9$A`*FVRRZ?T6_@gdZ zW+#2Q(VVny{besSF5a{dY};zKm$FtV(dn^_yiZqqb92+2?{%wbq4p1ULi=k{{yCN5 zXe%jl275dG`e)!KWK$f{VQxEC*>5*fu+poI-u4{Zi{lmGzcTT^MiJiHRk?nDG>)(m z)bJ7~=5f~VC6T^G>AmA!{!)TpVsl5n&Fv`tO_I{TQGwt4s)-})gOwch4LA5{+l3@( zI(m*e`oCmoaf=N7WO1K)A}*}u^f)VnVwue4{%;jUxx_ltzY_6|{@4VswL5=%vVJ}= z%yaw&A!q!aP>S&I$8 zG4W3HS5MuDc8^lE`Y3d3sHQ3VinUjWV|LqcEvYGL)9o7L`@iYR6Wz?_ht0 z((@wUrTb*vn(VJqxp#b}u9Vg2AV({N!OFKs#!o1yW4Cv7@89H9b_vqy_%%i^5paCt zX-cfyMVX$d`Ww@nrYPAj4mAo@%@W3QH8btrlCQVUe3A73azBG({;dhDdC0#K#sV{@ zWFL0!+(QHUX=Hzy7G|(T8n$y|^J?jJ*Y2Wl|3k3t&`zkJ4ABM3gbwRbkmJ^Zf(@=bE1 z<*PMn`^2Lbc^bV+>b#lrg_P?w-u{z1pyB}*rt z?k!{A!P7j}xf2QXN$TdG{wAMf&50uduL_MX*w*L<&$N8aDK-&gYlV@~H+u4-xNY89 zxrxBFTDkUFj+b#`$B!DuYo{S*Zx0z~{5bm9MyjxnCp+zmq<`+R#y_WC(*~8uoyQc)xOU7%qpeJjk0I&IR6E|U$?-oB3C!E7M5W!D&z6$d z-Oe=2saAH8k)SWZNnrP*&OS3vz4_nWMgC7>9602QV-4@b>y8dpEo%ASqsaWg4yx7RFjK$ zn@h_2q9GF0HBmJ74*f{(6mG3-;BnJTDNtp;4G&Y)%GFh&`gn^t&Z}={DIPA4ht)gf z(#sKTL)OSt?)If!Do^0_qm#nzjgFaUu3{`PPiC@3)PPcN7lo1HQU?*1T6L9ihLaL3z+lVOls8cPqK?4z7PMc3i>?U2u;d3fZCKh_kbrJ~)oH zoX+ls{7a?&wUKuXPrq2Xw( zmCwvpZLZulHJexCQj0cZOJQnZRhLxi+TMJz?IV+p)H$*nrj&mlXRQ4VVdRKr@UGB+ zPmY|Fx5AZlQZGv9W||SQfBvRM=$5c*SCMZQfZMBEe+FXFhcz6xG*(hs6w6(ymeZ)! zlKR@%wQ2*8)3uBoYqu~=1g~y7Lw>w6+UNaN<+QF=Eq@mkXLeDu`k1-CYPHdCXDhfY zik*OJtaXXk^;auG?GpN0oqRAL-%8`ORQuG|W0;PY*XHJqpF3}k2CG2t^Xp&x)EEEH zFWTc}tfRo&=b{?0(GcFhOGW9LRLJ`(M6;#*339X-NA4wdv^KJ>mxH+|_SgEjk(<=5 zQ>Oo7a-FJ1>r~cD?W&6oGj+4@#WZxwUiYfp`jLKy=uJJWtUgd4{BE57kr1f%V>SPH z$@;aZ*Z#EKO^^1FmIOho$k^<+M82Y(okv!e2MgMR@8{mMcFZ#+Uimp zc(&1>FNk!l*`BWVrD=;J?}ILSCxf#�p}Kd{CcIq5W36Vn18UBVSl8&_}O~0-P-c zIH7{@$H{uyz2qFUd8Zt~`0(!GIWmcP{j++&NnQ>ceziSu!B@&-FARcXez}{9{3$ni zZY<|;dzl^1UnHlGj1#o6bC{%jup>i%+GHj4j0D*j_aUK`E7bZbKLh8ZWr=#h-D>)O z;X=87OU^{bOFrGgEiB>NUABS8%b`3HE{C zk#8Se<<|xhO0iIv+!tkkVF}Uk1zqH;v+=;WE2#Ht+$*xPUE&#kNrxkFv}U}We*3YEY`TjblyKF*Jl912x3e_QJRU4FKE zbb&lEa|kCSFTxZ1vq*1WL`9)f?YmCt`#bSmCO9G9jp~DS%^^m{dQ3h?7#cZmqD%V5 z!Att!O6eTMrSE)S?|lWrNh+$8hIWiIc;#6YwxafkgwQq4;JuYhH<}%*>BG1vSkwo{ zsahH5Nyhs`kI=C~nWAzV(Z0|#-UxCs@8miET?BQ~y3%~v#QNlVL-bm)4dw?bdAli= z2VW{oyp6VzQi3OA!E&$eaG|sd~0JS5l(Wt*oVt)-0qU%5kU;I8At3>CG3> zK7sHPrA{m!t_t0LwshLk#|W-c3-|NwEvW6*s=yp2idV_vdKpK~nM!U$7V9Y!eZl8y z8%o_gahd$Z_mMp*%?yeVuGgrRzHMx?EZz{bOXf2bmktRgYkD_ACTW`Z{6=l6cWL&{ z%4GkQmFVrHp;|5as5>)>fzdom1BV_t9_&KZ9M?K>o$kmzqwby<4ZZ3v&6iTYlv_zemi=#+u-j+7)Sffz8FiJ8|Y^U1v znR1+lD2=Tubkf+T)7l>qPp8TXYMe$+R*0S!y9wr>?t5jg$#3>>=Zc=Fk{dNoU~wo8 zQ+$5IdC>NXQpJHn>QFu#LT;4Z-Vn~h-KBvIm0dm+p6{MKGq|Tzb66ZYTlm7!wThje z1%mVUm^lwFmOk~0WuwEjv~S58%3?|9<{2|xrAF2(l zij(&WeXhyQ-cFIVcZ`14M(L8#<(eo*YdMd|x4zKQl*?#GZ;jAJo@8?cyx-T~{I*V_ zZQ~__a_`jX-O2Q1-Tv;#b%!~e;}Sbb1dHP=N$+@Sp5@s88s$jiLOJL&1^G4Q&V>Fc ziQx8Fd$r=`{{1EzgJ<(*dp#3IxL7UjXJb>aO65BAb0x8p%vHSn=1oP6 zVtu7+F7bn)cj|{z*!oMBu_n0}&GF=wip7(S*9-QCIGXpOyxxh4T*nJ@iN&NZwGZb$ zM|OIP!}+{U7v1UiL`4;4s`llV=k%YV~-nGN|(yUQ#81UD5Y=YUf(V1avyLwj7%$WYp5du>d$R z$`g~hWR0w?vr%wTGzGPUUz#Ts|Jl(8?-hGQ0-eI~4DN_4TO}66Jx(O4cU_nduz=m2)Rce^E`@J2Vz@EGiLn+|y3S_AZyb zls8YdTw}ORPWj~My{EdwPQb5KhNyO|!28Ou>G?gffRvx(>V+@&3kMSv^bR*(m-3y~ znC)z-OPh4+l^&^~4b`*ePMtYpPHyhZ#_>}o4IA2j=+K6SX)`B|*NJd*51Bf%A$ZSv zrhnbAVMB%uNuAm%r86YE_ekxa6C8rb$VL(y89$Nh-^*`cl`8W#uwSC~9Tgc`bSj@C z?+;~W-)2KK4d>O>`s|m9-sdZLog2;hDhjgZw|!*IYi(TR-T6e~EK?X9YciWJe6MBX ze5q79pgyscu%{hIBibKHBwr`>CVH2LXxI;j+YH zzc_91W117H>ljs|nfe%yP4~}NTUtj^i>jD>k9B~P6lmsJyNFHDHLrJM9#_V# z@jr#=+$yD}92j|IZ+4+zZ$|bB`MKA_%!oDS#Pq(u3QJubkF9yVogyA9Z~atU+tSc; z0I_vnJ(aojiLPLAF0oc~wiLWNR${M&=G@^P<%Y+_Dy$=F5_92Cq`zH#)hkPy=&`Eu zy%hw*L@XRA>p9o|NgrBER4jgxSG_uJ74P=D!K{@G>zhcnW{z!BvXN5SZc*ozK4;h( z=oT4ShUgIMizFmZX^i~A*6mYU=PT9@8W=>|&%$WiCUzbfZM?8*cBj-VFLE2D+Cf%n z?s>0zx6bxX-w$K(jcOdA{+%7p8oZ_A#QPXONjE-=0-(P8<0S0G^6t~)US&N0?DT6( zwQxyASTNL%#et?|_=Fm`$c}lU61Q4IzTWe^`a+C5-8)eCT@)F6P%6+&)AVh%rtZTc ze}vMy>k-$=Zf00#6nuz1QN4acqdOrA-NE9F7kr)VJb`z?{AHTjFm`iTJFUP8Y-8uW@%t45{L_7m()f`r^jm%mWD@}2QL zWB^{k@G}4-!YaA@@1sZY^-^cQ#6^1A>S)%JE3;ASEKMLr#F`tt4x1_M@9qx&RpYop ztfTS^Elkd*$Tw8m!44A^mI__xevbzIX6wtE9go*eS3DZjK=gW_>2+XV?r?Y3G8^s>iR!YUge8a2nB9y?xdl9>2n? zknX75P8yv)=E86geW{pXJX;O_FkZgVWIK}I`BRf`J(ZYK(on(Et zTfLX@IG$<~8O>jTUId?OiE>^y;2tFXxW+G1)K$0{Mr+lW?(`STs>-VA z{LVtm0h%FHc-`O(`Q#b&cWPMncPz4n{W4ceM`!z`5$oGdwPul+eAoVylp1!Gg3&{_&hv8J2X%R+Yhe;k3i>`b|VemOf62|qb+wdZ|hDn+q>V)sf5`R@&i ziv8?W-q+4;hI_8ASP*L=37t15F%5cO@%`v{8HOG9_71C5`e}%A2fdELd-c(J<7x6u zKZPpd?cecd#P$w339fT2c5l|~HNx4EJx|i#I}u)5D)L`0&+zyE(RJ2wUKQOR--{?J zieig}Aa<}Ih@#>qyRgN6cPV2B545HV2f?(XjH?(V>j2eG>Y`}aOG_s%`%e)sph zo)>@ky?gJ>iO>0*GiPR$n0?&zkfp!62e|w{mtfSFNNL7k;x0JGNu?+{HoaA@^eK#K)1g~V;eJzm4&M<9|vw@Kx;#lSm)$67uw4P9QZI{@K z>-KQ!(ZJjrmsroagxe~qi`j>Oloxss6&QmBbrlY8A`Aw={Ev)bULehN4lgrTEWe8- zZlW;RPUZ zOQK2EgX3K%ef2|qcO|u04_)TohUOC!CYq0foJgVX; zZePDPvH3{pmrSauuqacOJkHp zsTY~xyMZ&xUJSpf#N_BZ0=?G;C?gFTqM__{hFhD+m>X~nbGa1(A6J*mb9^{it#GJG zw6;YY9|nge;=02dv^t*TRaa@fg@xW%(Wjs~pdz3-dsQ znXRo&vu7SKz2FFU)j}0lEiB;dwq-cGt>=PD ziTbugH7!wXOH|hq)we{smS{ptG_fU`)DrF567AL!?b#AdX^Hk~iKewg(_5mMEz#aB z(LOCvYfIGD5+qMv3(f6a>io)!HwD_XWS zTB$W!xiwn9HQJ~(8q^y7*BTYHMNwO{R9n=OWAfUf<=Ud<+oBcQqCRcWDs9oKZP99N z(Hd>hnr+cKZPB`I(Ryvs25nLQw&>*c==ApJ?DpuK_UPR9=$7{A*7oSG_UPXB=z;d= z;r8gU_UOs>=$ZED`S$3|_UN7V=>7I+QG4`Jd-Q30^hJC0b$j$@d-PX(^mlvoPkZ!l zd-Pv>v}{MTd`GlGN7SbyTDc?Y+YznO5v|%0t=18(-Vtrn5e?~xhIK?EI--#s(as%F zQAbqT5smJM#&ks09Z_9Jl8-8-T^I-;hIXwQylzmDjDj%a>Iw4ft8 zydyfQBRaMtI-w&vr6W4MBRZ=iI=3Ubpd-4tBf6|3y0Rm>t|Pj>Bf6m@x~U_&xg)y0 zBf6s_y0as?yCb@%BYL1CdaxsUs3Ur$BYLzWda@&Wsv~;3BYL(YdXCX{Mr(FP{W_!d zI-~xb(ZJ4Vo6e}PGaA|%4eN|{?2JZrM#Y^`S!Yzy8IA3XYC5BF zol&kcYV3?AbVidpqg^|r-8-Y3JEL1Vqgy+p+dHE>I-`3!qkB7}`#PfsI->_WqenZV z$2z0OJEJE%qo+Ef=Q^Y3JEIpmqnA3Pmph|%x}x>Eq7AyD{$0_AUD1H9Xkb^gQCGA{ zSF~wYv{_fQc~`VWSG09kv`tquxGO5`iiUJW!@8p3UD0-3(TJ{S`>tq*uIP8rIg;Jm z(I4{9U-Hl2@=pPaH&G=2^pJmg%0ElXKg-EK%gaB#<)0PhpFZ->D)P^&^3Q7W&l>X2 zn(`0unFM+EQ^@8mfu&4dzhi%xT!`~-W36Vu`x3}M3=}RQW+cKkc`Ak|5B6zGtwa=E z=06Q$wy(++JdDSSBAWKRMZWO6ir9gM#mij!*-22r>TLWsk>O_I|2y5!U$Lc;O#kDg zIL`-NA`?1M%nQpHp2$@q1`Lu03LQ1~C#XJ=u;%!l89BRE4|-$h;|EE=3nyQikBp)$ z_@j>zWertY6FGAJb^Nj=v2dKpljf6{-Vj1I7Z=iMsk`UK69)$*AEr5yNNZyD5ro=B zE>6nkk-`y8sBk+ar6Ty+Z)vTZ)dPvudTJA)i^qjbEi|&37$>x@xw|;2+1N7#$!23M z>`l-$^Jh@Qpfqg93vD{ldKsI2*%wb_=c7?mA!{j{1Onq$SrMfkz_IYMzJXDc)EBaL z9C9PMt?wN}%1q&CByyY;yrtWu_$6|k9ToKr%~pB_Qq3Hh=&NKb_lVhDgBS9h@~ri1 zN^;Gry$g<7%dgT+Z<+&tSURbC@2QhZ7CViK9)rB~@*mF6k!JGM>*BAvErj;Y^A*tC z!-?3*&b0Avh}hpwieZ`3?GDIvFHIQZ6LGQ|U7mn09-+-Alwh?Xe#R(f`*H${xg^JC z9B*LA_lCk*y}LnN3w|o5Q=KMwu8~rfrLD2wOpbSN1~j@~5?cpjtq65qxl>(IDgDKt znEeaki&BGgd8cu%t!V(dG|f5U)f8>COEIEX({&nS@5|Z9X>v ztI6zD+x|kY;v@Z~o*O>w|9)-Ur2xNQbU35vW-l%>!dxQBH2_;lMN& z$bL@}hJ_@7T0`6FWyfLeEp zN4sJY!)D2F<=_I|HZI%gC~eh;#wb14m0ZnyKL($lQbaE&tzDVLj!pT<@!=zKa5{Be zyZ-+zU%A2)<{~(`F_>kb%+D(qVU)Rv#p4uE?TeSJXk}7t3&-tJ&kfYNift*}e-@g9 z&qFh{dYPXahdi3;=zOb?`ncXJM~c|Zg*mFdhlD`ld!0CKM%%_>*!BFpM{EbrBA%&H z{v}bmaHxsWx8Pk5c=MBP7Fo7uu*!wj$AyOY2iQYJjJ7|Yfr(b9sP7NL*SP;XKyZ2x zR!LQnzD8sxWc6Gi$03g8_b_gWWgO&}(KwmNF0uWO$Z|}|{zK7@3(z#<7y^MV2qDwA z37I93y+F@m6D}nw;s}XM&F%_<<(*2Z&PtWU)`W_jmWl-8qs>e1KH1ecu0J@}4CO(5 zcekKi>aGn!VY+3oG5y;U?Ux%$}2c5=y-xyx$QOV_bduvpSl_IZk&r zu(vm1ZkCcjlDGe7>`D;Nn9~GcqfBz%d;-lsRI?2S}W^?M2NRCM%qoOVtY*V){yQB zuXpz+xx+tnOj;Fuxi2*Uk3S}At&8SP2*@3;)~IQHM>;w+Wf{rpwvMb%!ZeQcUQ2&` zCcF9?pM4ur6Et6h(<)P|*3vCgJU$|yY7()UM+Ep?fv@^SDso;oB6uQ?X4 zl5>I0X~&C+vs>tQu>$J8sHAeDd`|@rLU~@F_-*7~H-y5y+j(J0Y#*ZW>A@VUN~<~N zzFwK+PMGA8dLZuPLPLx`XB>SqnTQLRc!#MB%*J5u^8J;yC1aapT~BLaEuvU~ufo;K zAr%eJ(l%?asKKu9g;S}6IO{iI98eQlR0p;Ym9lj z6+n7FjL$ERbsv#0AT{pKkk5M|AlPfAjwBu|4A7b5np%wq^O^DeX_DXwk2d=CF#3%Q z!kf$8jsguX)}9`3v#@3xG0(9sFuSYKGDV9UDO#)+ut2Ig-B{UND9S)bjT4S<+*>Aj zu*rn<%_i6KYkNk3&TX`+UPXrMBnVLKGBIO=^N~cmue-S8wX|Km3IiIOdcWLj#tAA~ zjyD4DA1QeEahXAQe=^UOg5US6G$6BvwI2R*L^4ozS$VJ3Q~8Xc-mA6ZPg2&1xehA% zEY_ZQfJv_1*?azlx13D1_)@94j5 z!LJ^G$$BKCvmQPHVg8g9C9@q_4LJDno;8tLWNPZOpiRenW3MVHudK=*gZVAP>j=XO z?W=;y$`oH?d`HiOkBx@gSL1q!u9&>aJo~DE zC}@?-O8{mQ5=RG3b3vA=+WZ*x+@PC#^zyFJE2osa*fm1D5Z(oR>jj6oSj?iJ*m7xy zQ<^;%(ftsxU1~Q<8uehr2Q~-I(8y6h?lBsdg_LLeVY%y)hB3t|Kou==&Y}M=!4C1m-)kQbY!ZSrj0| z^Ak2Fo!!~fO#gw;U6emiUXw}K3*ZlH1y~}MQOHnU{}>v*IJLZF*N>h`L`Jkr8dKel z8ppMj!(K*Kbf>R673Uqnye6dUpwy`Rxt$t%Hf9jD&chnw^OCe_--?4B)#@s15{ae7 zPuFO^kn||V0~UfUW}S#zTpEy-aOl{i8u(J6>(j}=GZ$uV#<(Z@90e;D@>MvT>P|>P z9>7_8`m6vzx7$XVDY#r6@W+uzDd*Lf(bpGVupCJEQnnsvI;`jMiPe>wWm_n+H~6$4 z=J=RTcLlYrL2pFVUL4e)tI)-|<3XJ_Lxr`dLb+LliH=VIM_SQ*@~Xyu4}z=FVBcN6 z@)jmo)ID{RgwUA$*+Eytb zy?;Q@?75u-LC&9p#>#TUkbsQqqq6N2$Ou_WCPbePY|KeZXRPPuXA5t_kpE{**B2AC zQ|^Lh4^U~6=U_fZG7ge zGdQ2Hv3eebvzcwP+gKrz0yO_)D}X5qc)R5ihYTpT!SD}AlYpdU+-Tx`Dgui`$Q~cx z@?#c6k7ou4Yg3bgh$(Y?h{7*VU&3X_5K+p|CLUJvn)QO_!pUYzREMCpBLm-c)rq|9 z>~k#V56{mVa2ng@u`39>N#f70;l<4LSe*HdS;^vsEZ*8hh3&xDw-cj>pJs1E*a5?@ z^-;Bk-8p8qZ%a;q?epJXIM=WJyYz|xcApuk7>QWk?2fON;E-ciO*qodylx(glvrhCQP;x-V zcC)1NeZF{n>QM1kv~G6ke2YI_nHOgDfO=tJPlQ*|XC#@a63@mY7yrdk96*i(j@dmi z1&6#KKqC)T!HN_plry7!Q<_mz+n_nd21s~vpp~-6qfmjTl%;xv;qmTp>OlrMrZLld z9aTwghUMTR&6d`IzMd9hi=+dYd``~KZ3+HRUdP!x0rjN*H8PEDa%`Esf#yPjTVZO= z$;zi5!0FiX;MwBK}F>TNE8;Ka-wO_NrSxc*JPs2eP;wpL;OGI{ zzpWu{$!l&434)X%+!6XlN2_hfvUGxm;RI4O)<>|`y;GN$J;SpE za(GJ$1i5<7)7M9ntOByb_=2xOWbN$@zVT`xOwy+$2PZ14JrIqZ7h^O#iW{p5q=Ae5%`^x4vS5YW zX01)+NYbF2jOXQVe_9!@dp?aOR6_C=D7FHZE=(b|wz|<;;(s9PDj60esg4@u9Q^ij zrSc+sQqj_g;GPaaHZBbXKup(PKW0%LT$)m!63q|9hLcpWP?1?3qkbT$p6Id7oe83U z`yK(@lZ@U&LdIVE4PXO$P$Fg$lT#ffTbRK=jx0+imw7=GR`9fE5IH$~R!e3xX0Vcp z3*8mPI#I!;A$T!Mv+H~*2@IaZmF3E6N{qK%kM(?&ie5UNoe>*%u44H6rxBRuO(o=k z3~^Z8F3wc}#Y{n|_H3k68(XKl#m{rJEOEaTJN+>&U$ZW*-jSnFP#!)%o}8i5RE>XN z4tEC)Kyni%qr>OgK+>ln0CL)j-9S5<0DQCt?jg(~Q<+tJISNdd# zgWjp?sL}UAy~l^qkDbUBvAXm&4DqcI3VfOKZ0EuKA5{iSE^bN$11WQkia9~j3Xsc` zN-jnHuZQo~$*P9_{=s~ILYO%GNmu0#W8Oo8_IyRmmO9QraeF4@Ro?B6r6v>7PV^Wh zfVWgq>3l%!thx1tmiQrKX_iplyJhf()U(KWS6W&QaY~(a~V^8Bmp)-XOo`{ z0NHwZLdP)WBwPaxGht+Jrn#=q_q*xr83F#@qlIrzZR*DuHc57S3vjb{<8b35N>x#=!8po} zV9s?WAZa&RfnTpp(KK!qQy=J!X7)*32(a*{mzV;~iS#1csJhPrC&rUDAv<9iS1u|>h6vG}?QBeNpx z`4u&es_}VrZwO;KFIAr7#9His6AHI*m`2_~pb1p;L^=s}cQKNpy40G~Zx7?jqq6ob zqc=3hVpIq_k}~Ydo#t(0 zcmo;4O05!}P;`b-can5Hnwp%Tieu|mR|8RYpUfzUg|=$m!9XiQ;Yf~ywVe1m>ME0S zG7MRVnkY9Rg=)hEfbL_dwUOJ@R5h@2X-Ly7+~cg2*}JQ%GL`!!l!?9$*bZ~7qNWjA zg3shDeNx`9j>gDjVjTpaOS3XBmb+ZElP!hRcS`MwhI4Ho7h_e|r@@YcZOzXs@`;<{ z>V)e$gFxz3r!SK|B#4}Yyu^00M=dNy->CX?9Gl7n_qtiWgk)_ z;5c;)ko~dNqClI0S^A{4Ctr@I?~;On3j_N1%LoI_CO5ID^$a37P_re!29MyU%$lR7 z@d07JGDJ%0F%@9ak^X1kVL{?^Zl$o*R5U(fCWX!!WU1aIA;P4BslJD(uMPk$XHWYa zM-5^*CUa)YM0g3fp{M#gJiOX*QsK{bnm5Bqzx3%_gB;dkveU5y?wP@jr5PPHm{&iK zBNrrdR5jsRhP}1N zY1zr#YBm&{0#>gcgLqY0QLfBw1U4?UACHVm{UDt3W7zhkAjrBN5MAw0TkpXTq`rZ^ z#pQQ%4|hT(pLaoiA8B#V2} zL#JQUhgnpn;3MZ8i~VQ=xgPX7({pvss78&g`UStEh>O#y%DTU@&PuF%QZPMf?J@!9 zer#{4_-8u5;+`m_$>}_>#G8PSVD4}?Lz~RUCx%Fo%jL?bNrqS<8#@kAOVuvYsKISS zu==P*;*7YK+#%1cH0t*g(9!MT_jobQ9z4H0j~pLxCX`j}u8wa3n|qBGGFwB|K?zM^ z8Y}_~-?q52p}Mw|bR*2>Qf9MSaCFDSvh}pNP_dlmd`YjX#qT?*34Ip}m1?|o`8q^; zy8qEf=B(5HigP_}Bk<_F2;7O`UFU(LDkqJ1l3ppju7KQ544#in!B1nC-vgYvgeE7s zcVMvUO?N_;pGy(eb4VXL0SLOT&ME-o0n~Gu!^z#i$0pJim_(-*#tFW{Ba9e0~LM7umvl zo7jZ`n>a5qcylLs^S^|psFMveli3A^FgJN7RE5pr`P)o*g9P+#hy0=7{Ur{1xnf~N zYoQWi4+;XE$zMS%OYQX;3;D}dUDqG1>iS#Z86yG|;u+&mu-4FdSmP0?ke%4Lc|lX=dSgYq)f89ez?V&iZWDFR3rq~4T0 z7++m4lgL|7IfTTZkBMi@&)zHAK|I?hxU4hws9bSb)-p6lKpks$UX;n$`Sz(FHAJKn%Vcwd`47kY-Bdyc|WD}zCqqhWoKY= zWN?#kUAkVc{}gfj5RgQW!l3zi;K)YQ_|zHbM8 zKoa3yjqFLqRq)|lsV?8P^X1RdFIUvllM<4EQ~2(E;k)&Pg@l+;;QtgQ{2I_dK81Rc zv49B>^}ZfKr8V71Wj6S*c6fJbJ;_ISbt$jz3^jBP?Uq`wZ9H8Fi9cV}4f2z@e+a*S zD|#e-BpH0z1OFV7AZ1_!-J|Lm5Q4^(5Rh_l*qhC{{zF`Ax_~dWPdUsZSwo@T3N?-oey&}tF(*3_jT=_tWNRg8?w8Na?*{?oID79s7*Y1n<`z9s-T3K?;^4Hk|h`K?yNYoXa^G=i;OmOb(5?79I zb9H*tz_pMJY;)zZNLXhN(vaCB4V>HwES8mK%TTM4$X(>UobCQ~IePL*s!hUJ0Fn+5C<6%DgZO2y z&vF4u;Hq)Uky(4+2Ohb*QWB`(JXJ)j=Jhbe#w!BaI^J8SnQ;xcvupT$ylW`ezc0=2 z@1}lE3RhO&z~ZeEaF{3d7YcLA&_C_$#g+W3FK@Z`!EkFjB^xY|4RinDD_u?O7)KE5Q%1w zwsI$8=3anjkjCn%NaMZ_C9a1-n|D*LgiPa+s!!}l>1&HHhIr{nI-2x2PGlT!#NNY| z(`6hZz%q({VmnHBFJ(=3g5Tt-zBU+}eNLscEKvYs`bArU!XuP_1cIgBavuJ1XX=YI z6j1}yzPu(V`gK|cNzU0f`B63c`P5HbGGkh-%f(lhf4L;C+*@FJ550s5d z+GW%<4nvkdJA4^K%~k!-$jg@m?UYy2$fERf8A6m(FhzUR`oUqng3(Mwu1Gv1dyC3- zxW(Z9_VN8!$*!Y8rTPAB#Sv1;!=SGL@$erNEA(>h>KQh4kf^3rR3Ih@Af+4Gh zBnl&&Of?ck7=YdvcC(oQ$6Td>z2gDK79aL&vaIu2260i)qeNHwX($OOK~@m-YQi|v z{j{1--hv)SB*-djJ#ul3miKw&Qg`^EDECy^s{R_Vn(@g1W!*os|K}bC`E{svxy2^^ z@oMPXTY8<|9}xvmn!@k)fc9-(tNthjiLRzYWHn~GOQ?w!l_7;t3YFHKO)c|ctyYQY zH3HpkLE&S}E!4~4X`g3t)M&aA0qzv^kmP~JUOva7{z?N1tz`!8b|;)XshF0d?Y0AR z6YRP@ku!%ADqnh)=?zP1v@}ec-_Irj@2z5@6phUBnlDf^x+cM_xUl33S`M?!T$kt3 zyA@gUJECkK)Y_oht3Ilg6iI_sK((PTsL^@mSemI&UW+^r3b8}F1T*I|{g2r3j4wgC zg&r-8&8aW+H^G6fV*S8j#Dy)@42b_JI;*jsL~Q=r>fI4jTZyV>tdFOPb>%MowLxh1 z1npeaa?+3b%y&3fy&iAUm9Oc>9gKNGqM(q^dhMup-Mdncf_Y6F&7R)UI-PryTBmdr z9JNeA&z|cN;})7bGvC%SB*!aq-ydG|5%q&lK zQDv`6khiKLv;KAyCi-Rw>8u@@iH;zoj|^Qs(*306bRi=sSCxUJaWvcOeGTP-U)vq$ za95FoI7$E$;7mINKjyags=Cod%FjQ+QyxxqDqDa&T{RZIAsT(uTdynI84^Db1HL{@ zBG~JMbvnpWUugtQ9!(ggELB@~97y<@nEWjHWX>-C+(+PeBvE$ajgH0YLhk?^af38+ zuuRNamzL1BXvP7yNAVw}*5T?mYJ4Z~ z^QMVngBK^ct}(*nfY6nkj>gnA4N)TQL_xraxju>c+^ie(N$fj2zELZVIfNq+uwGGh`(1@M~M}eV5O$a@^^`{Adh?uSb4A(n;@?HHD;xXpL#2l|8-lQpa&H4^ zzoiz#w4l7mRe~5FRI|30-Di!~-OB*QOLt79)ykgyR_J5AY=y&a5pcf_{_(yRu)l%KpsL+t2w?c>2-V)Z=FW+hln$er<|QY znAtTuhzCvz=~!~pm!8uPAm(i$TDY?~l*#RePEHA>U(sb|A^s<1TAR!_0B(GwlA6n{ zK;54X)uk&b1M0gmhM56X*c4!Hn>hn(J1a4J*-l`UvIL1AksV#|3MUaoAQ12*KVVq)^~Eu7ZO1q1d+vS-49_bRYEY zh~vyu4cQ&Rzl-=og6Mr9v)ot4;6`O?DYCg)jX_!rI?|MzUH?WpuMvhfGzLY(cgCJ% zJL@6Z9UU;|S34G?`dbpCsMij?3cp+)VwWos%DS*Ev@YGV=N^*^s!J-{X3uGAnLeks zV`}@f=>E>4XftxHqy1HQ!p(aKryqrE+>SAD}D-x&1a?trOP zKTqK2rG0d&o>*I6uB^I+$aIm{MI7|>^a@bJcvH5BT}l(4dmwa6>ClBnLn%e$(R2b> zLuyoHebUyMn9k}Rtl*3g%D`)2^f z`eGVI0xAx|fOa!^Mr;S>4G)oOY!PdQK}y4ThKZesVy=%PQr>B3E8S`v?2x5K~)`RN&LPl5iGMWnD z>yMOSC(|@<+7-82H?YOhdfo0Y8ev|Ma>XQZS5CPM9(A9WL}T6&W9t%_w@JMSXs)T# zeES_FaX>d#n=PTekJ&Dl+7+2xuBxsD>MyX?cukgZmvn9hFK%4p8#Yt_D^nc4$W^wC%C3gq zUXn^XF>m#f9=znO6gg#QiY;buk3#BQ?3JBZwAVA=unHro(#YT%)z!Myt(o5*53c1q zK#U&`!mrLrgFa{Y*`n&7MEwr}L#$)L*{E+6KNkky$Zlyl9gn!nk+J#`+5e%V&RSF^ zHVP>2LRaaKx=M@WM`0ZmN$^S!oivHwb!c;h)l>||O2X$M;a$Qw8)J%O@%l1G`?3;6 zyfIO|r4Z0N(8Gx9IMk8-1JHDksk9_zTJ?gXDYERFB31l^j{R?;k4pn6$2(RyAV%5u zSUm58m^@9ab4=2iubs^(W?Z2&1rnZ2{(BuTuw_tz)U1bZ+hV-nB;>zC3Tbt&VxckX z6AYqmo?j|GCcbWi0FC6enoHqK(d&e;KbDn?3=OxI^4D zN4pUq=@)R)HEd*RPzO;d+%Plq?pw7EXYL<#NSZ~oE-KSVISTVzN^_nn&a_cRb0egt zHh>~HoG+JKvFG1^}x)xw`r-i@wEy$!++5>*!?_W-bz`A*r?aJLBYg#5|0}^Gu ztaO$>gE;*}8ZP3}mL`82^NxMBo5`}D#+A2lvECv4N!dxPNMPG;zG;O!pAbfyEb^Ph z<>7p5^E3>y_RaoOCDYfD$@u|zsf!m5Q55efpm&cTF_E~D)+0!3T!;!WAQ?-)9ninM zOSB!13sY9SI%Sn#Ld@u{d3HR1znuH~+@xID#7b&5A%N}!=h?&VzZPs_Q5`?Lq|&@uoH}!ewr}}6(Bm{ei2NPO zzfdgwHF4#*YC|NqOH&h|Oe>|yv!AHl;@8PA<|prQ7mfl6@v5{E$RYq?=M=s(7gk*Y zbRU=IQ4+#6vVQ|r|3jq%cvnaVHo{h()}hC-I`!qvu$Bt~RJ)c@>SU&6^k1y?o^+aQ zq07`K`r#RyIZ1NpiFA~x_aBcS`vn?Sl=<}_7}aqZR29NxBhEK~;dyCFAiKSd#s3W# zd{l7}TWK1I^tysSP8`i?jrtmU;fW6fw|1=7=fvK#)l}9eknFE$bhdc#9_Fwlm|RT* z%|iy$Cqo08;&4R=m{hIx`tYNx^e)(`dg|<^dHBWjHVO|j+gezUtMK>C^)A@%|NoH= zs?5ML9U7l9wkyNf*j@pf%olVoMp){h!!IPqmkMeyz6$66F|{Z;b4gyLb)LhfuGI!3 zMyCYX8+%#SM_RX3mbnaJ?`1h(WI}8E?BT=a&1;%6ZCcm#*|VEkr4UoFVAJH*y~{!o z#TB)5B3*^izn0=#{(}9sKwOo3z-_$Elzwjl!rlylRRAhZFLm@Cfz5p#f5YW<#v-fv zz+0)1{4sD^1luE`RV=q8ze&Q0lGPm8*1CEpgRNK|Or*HOuZ~ycxay9=qyEeq_}9Ro zP-*4O<=uXCBnn+R#alE|!!i5{Zf}N)Ezo1twKpAPKVqzJ1hokBc1!Z=RfiPxoH3xF zscH6{X*1iKrna}XwzoCSZQjq{UJ#a`d$9!lnOlOMW!ijaiTL8rEeBdi8 z8OyCJ7ER9uv5yZWxu8X3SKne1bCV?p>@CUS~0W&Mz3 zOFQn5LyGFFxp+$USWT23>W`8>-naPm$W~zvQU!6xuA8R9&ne-Zr5ul}lgVqxT|#2{ zxSzd0m|XkIAh^eQu~)lR0EdyLgz-08KQ9@9+o)#_e*c>RD-7hgNti$-KViU>x1h8<~Qg?LU*Bw7HS^|akEO1J^e9Cd4|zn7{(w~aoq$a zWw^CdrBZ5UC0$eV1JUV&DFMi;d;<)A+ z9MiSqS-*RxKMND-EL={RZ{Js7Wv5%T&ud%!6`-H)A;N7!v5V7B0}g+s*$v8+gFlo_ zUC9IcgapP_fVI86NNhYQBruL;WtRi*i_U& zigYE5M@+hB4_SiTQ)ik~2}w1xixrRIST*SoyE*pd76!Rvi0*z9q=ov6cw%{<%ee}R zoMCNjXVwb63!dJRqufTwNp2nVf6+6P5^{HPU)G%t#ngWcGvhsx%k8lDK5NT|?>xCdLoh zkcAM#UgBLb%9>sPI{pgC=E|TZ8to3WeUOxR5Tfgb@eM+>q?nHUQLGv*PKTTnCMf!9 z*Et^7DGa{J8+|QB4e4}Df9pVxb(@-nn^Q1?wUVJFbvIWj)LG8~D0g@$K+^zRR8`4% zLJe9Ba&WM5Pbj4lt^wmTto)bcOF;-gTOM$YM+VDz;Hsh@(c;!Vz|yHYjS^Ha(*7BZ zZIke-Zm83#Xk*imOS%$K-h_`M8r~E%icL5O)(mB3-mYrG1 z`~q8px(gTGFhm^A8_27E91Z|Z>J-1oRn(VC+F+LO?x*T^w8Fn4%s|`!mqf(h+!!6J zwrpb}HZ&^a{AEpg75h@0sy*?Hq#)wvV6Ep>g4G>q&MySlEm~>cUxQFJDr1R4z_l&3;N{>Pw(Tb>Rc?>4iiBJ&4=*z^R7+#8pA{o}V$h zPmJr;RLN~z#`B~k-akOmc;P@MYCeZ2tQ~$YpHwx3b>BdnALrL|l6fXIu}mH5Pv&~C zvI?n*2{7Bx_aT-sIU%?;c$}KZ1F+lcj8-^JSW9CCRPuNDgrhpxw}HJqU^^@N+@ZA8 z9%ItZBpTxiiEBcV);j7iY6N#vggHY64p;IA>WtEVgP*h*rejNt&oataQc@ekZe9c) zLImDYMNi3dwC$WkmVZ{4_>kK{?s%;o$P$u;eyJM?bLDDJHJyX-qf50v6UB`{m*Rmn z0w{$8Hp~eG^MIwDG-k`C;OZk6gV>W);fZNz2)-YYKImP5)!1tFhZ}&1kB8AEM^jrz z9mD|74XK4c-9_1D2`+S47@NiHx(ZJ9v>)1xf$SVJ6*-7YOYjny z%EKDT4$5GffFA5mq-3vn`PeDssk^ zPhctwlkc;!(-NIwjP46XcI6;=x(AdF5* z7orO@`+phVH|h9lB%RRVwuTY*3|3QDTFE(Imi0DcHh%}V^Ji43Ib4NTUY&_B!jSYh zmjk}<*D8oFC^lKcdVFVL$N>qZlS~vEhL(mW6Db)h3$S(p=^XUDu_B(nbZW+N3~tw& zj+J$ZWZhkhQ{! zsL!6qXZ!iOO05JIbFAe-B#u|7907Yt@&;ValLi4W}`It}KVk$Fw0IM+Y zbyFLng|alWOnERSv@l(MOP0UwPU2y(u3x=y=Sr);_1Xyx;Tr#IRcX}_eSymI{4}RY zf}>PYi|d-Cf%-2_qXJHQ_KYb^$%ToPY$)#ozs`MKC_UQ8HbVN{KE)LKLSID4N4t7#5tpxCuK!We% z?@u!T=2lw`Lj3}Qy_zlvWJBpt3KN^BDsw9)##v85W0Cg&jw=A)mBCHL3m);RsB0=O zuP-ZOEjIYb0JL#mcd(_NSr;hSR8fYKI%y$MQ+y39c*#tW2$JdD9K0c!g5s?lDA5hi zKM)lz?I%)ER9KxG4T)AGX<;rug_3M}ag`p09MXNaPGW7TVQsMU2@PnR*r)-mjY+&5 z@JcF3G^SbRTu55=V_+9j9?I;u%fVXL3t4ip*%W&S?{7<%Cq`HsdxfD7S7Y;aF+I5t z(bGF2>%+WR|I16#M}q42WNHrK2r-SA{mA`ZQwfVqrBt@_XXw~d^h#5yHOttm;*Y0tE!J`U1vl{`=+KA}c*79b5Bh?r?X>Z8N~yMS;Vx>`Zk2>>_@sGC;#Hc(=!Gb6vU zk`d{X7}B3XGI61HT&7OD8|-SMfCsM8jvQT2=_tTzQou8DOKFkO@$!DS*Tvpq<e@)1LMC^k*9aBb54neNzB9R6$}I8catzw*GS5VYJvfU8|9=r;D3~#BWfL$68A?L9Z6+-ruKqMQBr5>M0{qP z67o8X;*S&or12%g7k32#>QhkdwlaGM5YSIKk;DQ`Ar2y34Dg&2M@379cFAdX^E8F; zCNjMXg&&eoc($+@3^@b-zJ5qXausYNu%(0r5RlQScLD|MfzboJmiV$xIs`#MlV!~3 z^LGUyO7zr<+7lt3ucH&Sd{=^0>i&n=G~fAbd@!TS|FkX_;VY#fJaGZKnWLnTy}}5} z>paj0XStOS^hQbm>0Z{;+YbGlrUFz_U$o)#7YdA8 z^RDSuy)E~D3T-Toh3ziX_AF1?bqVot{oq=plkOxHyDwn@-gTr^SrXVZ75E&Dt?kLL z>vuM$b0C)Weqd)g$bAh$)ABwFXQHmS}>5)bi_lP6nLT0`oH4O?Lw3mrV^D zjC3HP{`@us@n34WE_iDQxR&4F$}s2HFs0>E`}y`v^HFPvz4O+Hu;oBFa!pX73rVXha>0D~wlDEXS6r*`E09e>vXKD+Zz=GZk z%){@tQnoSz&hdHhs8V*|DG8s7H*J$dJ2~T1BANQ*Q;9>rcz24ug{HrGHqMM^mS+UA z#+8(|()b(0`^EcvV{ub?C1#*LFdqCJ=Dd-EKdl>_jd%`BweOB4W`x-jmj+=3I|m^X z>GWFG7x?OLj%LW-!8-lri6G6UA?q8rkN)jA?0$v7f?VsNom3kj@?t_lSoX?fVB0YC z?_-f9H|DubS8C?t1cyT8aYZHd>(>mtG(^{AGf-C+WUeB{mc%8i95t7agGgh{MJBoT z1z2M_1shWDNp0ORwY&(qJWTDOHdmjK&BC_BuRlPxsZ*cp?u#p%MwE!6J>@#GV_UP? zSFz3mV*WiB00NBlU%wCOe#eD2xw@xtL=z^$w#qQgk*v$C7Ba+=`of_qLmY*1FHTDf z_RS?kw1xi7Wuxs;k;8at4?ihKaLKF;1D(c{P7NU&j&9=hNN{(w2@kT6Y>3UZgoZ^S z#0Uv5GewPKQU2AzWu=Erm(#{Et<5#CI}po{#U}uHLxXI_>fCt`UeOq=Lyq_4b~h!~ zyZhrdL2_A-o`~qiY23;?S^IV%;kPh>^0Mk`-3@aIU*Acagp~f(*DuBGd#_r-2Sq-TyD(!9CE4GoQGFoJn946qN4wtg55R5wg@@}&-vE%*bUm z8sK^&n=)mr4fXbH_p33|wH*%O=JBB~dU^-K-lsX~$#s#KYNkT_6w*5`csVt)A=@bk zyc7LC7r@AsN2NNdO>#>HFgm;d;i*6G;?K8_h3~4H8Mb~tcJ_P7!Q4I-;)kL8lZa4_ zLG)vaHF^Ax*Pjw#DBk7BwY;WN>Zksog+UwN6_eSPaxsw8CyizBHh;>TmSqRDZGZi$ zbo+tHV&3CjKPIfmuM>Nn8^Prm*iAvRvbQXk=^9v>@9h`U09p8uIH0WN9hlJwNA9F? zmEyAc?K~`YY^IDB=(`!ljpPFNsBl0nEsu}%FrXUB?~HwNG`^MJ`ZZHbN%q@=TrH)PoOj7DAJGP3Spxg>|}WjtU^S(xyE@G?*2uR zQdn0TLqhSm2iIKoF5f{6pjfNE+Y0*?eR>vcoVTfD_I|UcPHAfndrG!t3&H1ZPs#NO zl*4MxY*yrR=PISR+@GApHUa)cgg!fXr)=$_1Mmy|x5F%5}J9;ZU2}HH6y<>GGvJY9L!kxfc@ne3A#qU9c8Iw!&e~3%21p zcPjKMO(`JNVXZmajrAHPdSnct(s*K0#m~{~6=|x-R?m{$1pR>;2zz}1B6lm2a;7^l z-6sRY)faBdpN4gW9{`~xv8v*1JFNg4B$~_+kIsiHK|J%^mjJ`|34FMu%IM>Ka;il^ z7_PnnqGcP;ieSEtMr%fCccZkKYQo`Mwtcckemu|Q>w*#ajMt3kHjL=JBzVDu3zg*l zM({T#J!5g*JJT_=62Wm{B9(BS{NN0u9JV0^(Eyh20?^D}y@kY~D^mdAYFi5sy>N!z z+gu*vLeY52k-D_|Ff?Pk6ir*RC%BvoqLu{K?oaAATdBXrh8_&0RrV5@pIfk#{z+Au zEi<+CN=}C%gq;&Pd6haB(g1o1BKXWt!0oa!fKfpr)uQp~|0%FNi>I9!vz=Nw$2_D$ z-$OLk^uJWd5u4h@_vg2p6CJtcF*#Suf>B?FcWa0da>}JcU=wRr#p+HB&p^gFxXO*LSjI=GXZppCY$c);_Z%N0yc8@lsn0zG_}1<%+;rT&j3loQ=*jwN-kVkg zUoZ0VplIX{MGIa~fHWRTZI9I2od9P%c?OD@Ru>B5abb%V{)yzsp?2AaH?QRuJT+lVWW%kSirprP8O^p07&hn2I{KT%R1^oXH8m}UTQL0Fd zu6#-N`wB^{lAFzplG_MYWd`tK%Qh;y8p!)Yr3AKowkxdSgTzadR$2)KO2(t`(-mF7 z%e%&kr%h>tFz$E}PEZvhYPej*R(ozj0AHonAbo>MJXKi3H)am5 zkdxQ5UBg@of}KkapS}EiFYNpW_Z@xlbil-VK2#GdCD*W>V!!)iDYYRughT&zi1>p? zu2)$~O?g#iNrMHt6&bEK+| z!D-Q0+f3>Je+3D~8nmFgI|4i_GXq{^{B{XG*F%G*e92O;Y2fB5iCe}eb4|$XCHRT_ zW7T9;KXk6!_1=BK=QH(idDjI$|3GhvE(Vf;~I=b}(# zcGVG0my0l&2Ax7D8M}VyE`nyy^fOYFa7$SFnP$Foe`1@`2=5f63}Zbedt9I{lPOJ9 zwdWTozQKIzvJo~eMH$q%jUaoJN>*L6W3G@M40wE>j!0VH4Fwvt~cFbvp~U3SXBrnU{P)J<9SEF5XQH1Wu2;1DRzZE<05Jg4(e5V2BRjrj6m z!Vxk#bunWu>(V8bG|4%jftXdAf$lLYPM=V?4>P z>!cxH`YP0W=VLN!r?Ey1PUnXQ!c!kl8d-AgYM612>dyxujVt_+-EE*%RpZRxFGGpx z(!jbQ-E2xUx!zdR@mhjQ30)9;)26d+e;9WlmUR`f6i}Np`xn+m=hJdR-Q|$U@v_z% z_V-?e1S(Q?C0!BHC9jyYV%towL$$3Zx`Tvm<{IcO)l&pku8N)5r z6&fq@t1z)^G=#=6$$0wmc-u0br^u!NxunzB!wl@`_&D8%gNBg)E%17T2i_v7mT3<9 z8TNH_BI`H?NJQ3S|B@K+MoIzY0F()t{RG;|80K)Mfr9^E}^ z+M?ODpk}`iBQYU1o>2eI1e}B5Lc7L(i*?8&HgG+Nr5+a)7nT&HMrT0!8#T7sjn`e^|CocTSVK1Y`IkU2Ccp)a&k8K|#Z@LIbZmrWWA|Y`$M~el?;&B2 zr8b?f7}dvqRJG#^hqn(MGDS_gj4`dItUlZ(md73D5(IA5_LHBku8MRvPS(cksSn5S zo%&$p2sge6UJd0AZ2aR)xH1wd!-6aISfxcHuf^he#`#xZ$o^P6g(+8}<(-lelsh;o z>2}qG@?s+T^)8fg5O7t^5H-vdsWU7L^xp3ga12FT+AtX8f#xgX(E5oF_`*v%Z*|8l zs)5c!=cBa5viFr-io7Nm4~&a@rg!09Jn)iaBuVftmg}R{oO%#XzD>Ly<#@7<6FRbO z5uz4^m=!X;y3FY)FHyBU$I}rxoS7F{PW&fS>WpCJhy-S!N$ zk?LOF660e;vR&iyb3KRjw%Sb(4-&A}a9HIoTDSLi&I78x40@8Ss73)}iKO?XiGqN> zHnw#^;ql6iWho>}@$bQj_g4x^^rPES2BM!9XNVs6G7bLEVu`;cXRJ{+GuzE3VrieH z@2@VQaYgywDZF}0@Nr29>>Xa7xT% zYR$!A;I@5WyQE`^?aDRQBQ-rsb_{FRxR409c}n}`nr0g{P5`La2=Gb& zoQBULK5<>bk;1A`hH$L_OIpEVmXrZ4+iC-{z7F>9I{CeeT4bvx%B|8(WkT8d9Kzh= z3XJ6rS}p8BnAyHQUX;lZvFcCXLYiBJ^n!H|gU)Xe$N%ug6fX#5`oedWl{d$kxWY~! z^#47CX>`z%bn7WK9g7SvR>c6{CNi!Jo~6If<(b`4BgEB;Om z!IeNV0J4X8Z)yfoEp5#!GwwlPpPZ%EN_-Dsri)Z8k+7pX54GJD5qFLaW+hEY`aFm` zkjeOvEsoDMRCAhUy^=@)Grlcdg;1@f78qAUa?1n*l?|@4GN;Boqd#mkge^J$E!(L( z7wr5#Z&pb#)$ba|oUYSP@;3FU75I6k2iTfYd#l#-%y&y?AmB`LU0zddu1>RqH<|Nc zVIfXVq08dLCwSVGhR=4hWv3S&zi#j}@TkG>ht*{CU;ybkZ^^~QnLVvr0>)o?FdAKE zz^DpgUzgC1nA0W4mTNgc=T1tk8APXLSHtcPyk~xDXPLsuBCKqf4J2uiR-4$_IQpxx zSNL0HGO6NFN(JjH<8Uk9`V9*(jw?L=ms4smhO-Q@VJDyDNWsJ17HKyYUW~p5q(&U_ zY-PqTFw;|0N?tln_r8t9D3(^k!*(qvXkmD}r|M>FykC*mM)xp)`OjD>hsdt{`cldv zp&+y=A6PRBriP{O50)O2AX+91{0dO}-4Vi?+RWDUNyOyGG^DY)jYfp9a4N?Zwxno7 zYqJsUvxJx^-vMCl-!j?uWPXlK1sqM9WdKbJ@HIJ#ccQnn}ze7%R9-Kt!XS@Fa zqMu|gE>p`CMczjq;{woTTXSy*XOBqBJ)F{K&tLismbzzZ5HW|;1ao;z=9GYnau&Z* z*Zrs~w_SB*UC!yUkVTqzlcQ=^<+n>T!zEGmc}%t--vci}s(3H2(WH~y?8BNF^)4ux2+Nzt7VPiYL)v)YMRGS*?}*oieX zKp0Ldw`Bb45xUA87b#2r17OqL68&-XEUuXHo{9=xxXN?rxxS zub>ToCXX51O!Tp47(@BQWcO|WhesL2P=`77wRo6mHaio{ndlQR2G8E+I*oPrk$>IY z4Jj}KTpJl|8Cj6VI=QiKNdZF5TcsfWT{-?XoNgFh>sD# zqA7%!T=WfO_m;;V$-^_ZUv5w6otLVqc6{}ac$rDf;a#+JkMg)icW#rtm7^cF_=REg zv|7wV7~0jw!0K<;FY+}&^{Lf)%~Od;6W-&xSG7<#1y7$&4x`EJBHj#{ylDfbEK@3} zEx>H|4d~)-GSLxr1MubXkbNiJ+4;+{gMgS>Ua(RR&Nb9m8t-@sRDUyNHQ=S~P#Zy& z=hylaLGsseg!S|@*`BeSgTV9&YNoico=3zqi_*{!uXjslN)WR7_7EL+N=?eXn1FM# z4>%3Aav@?^5c!dKv!}JY?$%}>!}MmSBXD~PITq4ng6ly)#s>@=qbE=R2RJ8jYjKWj zx$;kZdRQEf;=6D2Oyz8X()$^MQej$6YG;h<^vshg<Ad zwF2rq%>O9sTXu!w6XL|KNmZxFTF8T-$5Y+~WDkO+o}2RHcfJZgm&31YnWhf4@2qUM zI4N$+@qfxhzu>tUsR^aqVomqpDm=B5!WFr5PwFBDd@jac-=8i1CXF|&R@PP66Yh3K z+JjQ9I*#P3E2e;SG@9MtWD4E&bG=8dFflQvBs6qGtnb5;_DM~EZf_lhUt~n*dl3pN zB!VlI{)6`(6hedJl_tmC7$96T%?zM~lp)mL?@wy5y@^bXxy&|^^ZEWusr03kYCbU! zxo;mhd|9UD>U{k7#elQI;&e*3AH)BsRn!r0Hf^P95fG*n@T>{2APSSv$pDpYEMbD} zDTyyC8KPMHHvD*fioTrlZ4Gcm(D(V6Ts6|-l~8;&hOMXsza6uVvK)-T=w=5<$L?Wv zb>%}Ubz5dHW_M+vf6`X#isZ(UdXd9CtDZ?ZUbT|8;F;xhg@KWpVa%eu@LqTzJ@iVO z(M}lSu#9_jpV6F+k8}o`az{;SZ(IkV_6fyR8H!z2?trm==S?c{RK8=@HtL`NZLv_r znqs*qvA+W4c_MW~SuM|RaoZU3{HmG~lq6FH9SV~;CR9FrHL9|0ju!4$40m%M;3~K= zl&y4TAIu5B;+2UHCtM^f{g`y47w|eim@EB@60Wp8Y=SS`rPL&+ideW@3ngu>W+WKq zY(|gx6!i0E2)vBRW$W3DW&|;>HPvESuCiKR9I_@_TuUPuokh0M?f}LzC-r+5xMAid zaLc({zozg)nbRSz&TA(?AjYaB%&(Ma%e)b5_{gVM#issM3VHc1c$aS(P_BOt?ln!n zIc+X9nEw>-e=KAu^@WA#B-CuaMGnng{gv4h0iQwl|0ZihuC3Zd04JFl%_nFZWl55 zyqf$~nCsa}q2QY*QVN{@z|pr%Fd@WsMA}W&=OmQ-ZKxNPnR?+`*xq}(VlzHd9@`0W zzgx_0{iSm{_CJJ&PfDn*&cy%9Qc?ZA z-7(aKCYoitg@zH!-cAuC4tIHK*a0<^+95eL=#O2+XbyGcK~|RJI;mDuYWkSyz99HL zOCnO?3yyz1HKz${&7IOTYvycjPg&5hj7#&WeI;wQ8Me9~+WIqC7rW665?+CMtsFj9 zQop_WloX!dN*p}w%__|7*V`Ul^-ZRe>3*EeR9+0mD{G!^$_Q^#iLy8LQK3n(bz~8C2gS$Pv}i z{Gj~wRh)QHJjQSolPP8tfvK%|>_LtHWyr&5l~=eR>W= z2btHEy2FUI%-2Td$NJh9fy~ymzDDGS2a(qybE+Yl(`|+I9+_BZaaX$aQ50b2D{D$_5>fWF3G&?`owtiEo(N@D$Syzt zXL+{4$r)BjOJEyY`f4j3AtSWlPr_aY1?%uP!Wio~8o@uiHTUlMRjERD=`Kl@GUP(d z;TqA)SZR(0p0YCf)r}*;;}3CM%>y z?*{;0Un(KXW;`X}(-H82Y1A0qAnWN$jUSN4_EOsR6=c)*ITO&@H1Sj6l9COmR~(0* z_A|~N?@veMIhPHI4nSeHuHFVT zUYKy6I=4C2eL>CrKWN(hDy*`sEX`o*iS=&8P7Pl(;7DP?_#t`5(OqD9lN|G38w>TWndOXSIK5wEhNgL|ykTTEHOYJf7msV7=3Tb{ z^}oloA@9_)NqF{B-h8Vk)K@lSTYjcv!4q_qnYI@>KtfIEUg-G8K~nBuwd?|H8Nzxw z7M7gKpGgD@5y|k>0NB7~-RK-3V3Ee!yxy83AmD`%p=H?uB+kU3t%(&|Iyv~YCgX)C z0b?&4BEUq|Bnwfb5=U8+`pxpI#E|D_O6p&RYD(q?kWD9xgS> z2~C9>OB(rcg0|Ys(H!?8pRKe$40Uy3D>?RmJM7?nZe!55Hyi#Mg<&b_@ zefi#fe|ckE(jm{^j@YwUlXxg8Q?X-!?p*ow?b%VKO}Xi6{Y;|4q9Ps_$48>KG}}Fs^$jp?pnbc|0~HuH`d^G>C}$ zW$Ggo4aEgbGt5}n#4-URFm#7x>ish?^IcVC1T)cV!w-VRzo!y+d)2itCn4^y60B~h zFDhw}^Zsp?TLoBGyng4H zZzk(rG*eHsgSdpaG}oJJkzAHw!t2{;?2|a0aN>ZCz2*G4eNs-4_HhF==TlI)APBfh zPEN3%_AdgCG}Z9IS*c(u2H8u8#KabaXQ=09qKj+OMV2Im);y#)m~>xYXfC<63mog> zwSO9u!Co?PZ8vPDIwR0r2A*$5oV$AmaEn12-yX(+Zu2hgZb8y>SPiqkD~?DxACdH* zt_3u16QHle-3*pFEbmmH@1Dfs;8CR}V)nxrdZavuRY&%z=mAV4q#mpCBY&KehF>`& zWVKX8Zl!OpjELr9_G|k=$YL6T=DGo!Ngar!U-D)%p{TOKIPPGA-(iVKB?Y(4CqBWj zHcvLiN-q-V5f=1L7yyQ))1=WPHucWrPtU>tPu721c7aU}ET@D05!Qf@lU^ch2%uVDJ08^wG@8nISpCeH-PDMGZfLh8ST>yh%-(_wM?EYLS$h-NQUkX=IQlPI{i# zBZXDG6e!eGSoS#wA-v#GB(&lM``;QE>8A+1l;d5UK#k%c==o2E0O>I{@P;mgBqs)4+^gQbixR*m{C~U>>n)6;~G? zlQXNUa|jrnf$i7SX0oh>{N1~WsFKTdpkZc;J0h=>w9Ak!W=bDF;4MRq6ar(kpn4|4 zxLZL#cUKx1Tbtj1_iU#$S60S`N9~l8Fx)#*G^MyU&N%lP#HDG9VB5_4DX?d8phLca z!dP7iF15sYrSE?+KTgKreoS(%^!P31Rym;MYrCi+n)YQ19W<(u*45eoCm3G59FFr% zQtgNrE)+=VH`Tzv=LD?gBmph0H$kb^@S|;td70lPIH(ogo6D7LTcn8Zx!Bv=X_|ra z*NnDT^Bx8epKl<9$mR;N%16r(S!bxK`C~4#*DEfh+BM!4D&$Z!?lCaU$@fsHcqLVM zvT@$FR}MkzudCcFTTmNLX7-3jnjEdFMn(g0fc-L1>neZNEZ@O0_6nvW)*+`hpj@T? zCs5mlp?2%;+_3!iaOyS(XgDD-WRc)~;N->Fg8hNP)OIwB-i8NuHMI$!SebsK2l3bq z!f<^p9{OWmbST4pK5J!mck)(P*A_wgfD-Q5+||y89V5dNv4wMjnqBc!re(PApQ!oY zw4Bpe9OuVMetYuBGU+1~MYd~Z23ou@*d!*IISOSoqxd)cKAr~}>KpB8DRQ#i+FIFh z+j0`yde1iS2sCoU_^Bd zpZL*Xd3x%YA&fbu@kC+*Qa;HPNH&ImpPUL(cGP5y=tpE(oIc?Wk+NoX1y39hd`h52D%s;c%9zTA;b&KIqr9vm^x;h8_>3z!`}ExiMt|R~)Vtt@Mmg(d_=v&t zXepSKY>v97oBztD!9-D>huC9E4#rQH3l<|OW#%&HeXy4MjZuTcnx#$07QXiJvZUT_ z6{;p!Rw)jJM{xhSg6H3W=XE_7ugI(F9}E}YI^+9BXs7VyT4$zX#pMkm+zRV>CGZ(C z8g~MZ`t$*~$_IhH6>Ih;OFi!?1dRJ#j1qPN1XnP0!y-}}ETTbIEu@fdS=n6_EH1B2 z=&f71&|Q4hWL*EG9s*ujF443>?}Ga$)wR!_Q`a@KZO-(rCTTCZ#P1^E#3)yNuC2El zR_BupJ{H7MUQ(+yIg5EuOzCn`ao5;!AC!4lU)Sb72pjAl?8UylE%#+C!?%^O45ZP8 zvnPV}$#S33-`&{W&@@K4+djyZjNhF}jCk6A(06@nda)T4;&X2ya$t>lc_ksahxd6l zh~e@IV&&$E8{&zwK0*mZXAON&-7Ci8tLVtpri0x@2E?0Pmo;&1SI7(>WafLNbDLaN zU)xw$S5~iPw*s^KFhPV|Hy61TqqaAa_~EagH?FZAByxKl()mkCzc$xTh7xmj+V*HafL!BaD2K-&@(5=dy zk5eN@uhcOwdC%R+ug%gH)j2y}IL}CbuZ;kUOwyV)^jDPix z9~1x0V}`BR%1a^a``z~y6H0BuH5hb1TQLg?MD@BjRD`lhO?akxOZ-n;B|gp7?R#U=$_|oj#H8e;;$Ei6!-u>KaOlwU>_@K&c@m9~gcNBQ`S{PQFs) z2m~Ks`fBi(gV@&u@w&zc%gdIBz4Q$axZK@7FdOmD)83_4XVr(^#e2r2o=hanc<~K* zNSQ`1iKs2cZKpv zqaTbRFRxQSnHtx#Xsa{7Jqa1T%Ks*JrJ5$BWihzrJT%L(rGbv^gDDJ+SFsvP@qzHm znW%Yc&_Pn}VM6MeCsD)nBuq$D&5OHF6Dls#B-2$zbUf@SL^JXEn5%eXP#@}qro7uG zam{UDw)5VRc^9U2I0vH&1>eKk?g`dT1}GZ_sgkOHJcMrZFT9zg+3y3s>5V&LBM1BvH)KnfM_sv|9*KcWSX_ z0_mCv^-&KGjm5*awWMtzB%oiASGm+2>y$*EKwk4z&Lr)lnp`d-V4R;$BB|v=EY(c^ zS*v%!?UQs~cxI9pJ`_GZUfN#NmuC>r9#2PYkHH(nsCzgQsO17Kqk(DUlpU>N9pF58 zSz2j+evMFlerl!JI|TnhR&x!l@)c`Qo|@6y#G8ME>(ZZw1`d2F_iV+>WSb{0B4MDqxk9x-pZJL8^Xf7)zGm^+yf@G5e() zs(NB=jrzb7Si|N%%PK8xDwnGll{!vf3U4{E_(D*|#9zZTHX(2pf4ZEGyfp3gU#2aXA?^mT;z&`IALA&m2I zD-7Al?slAQy+kb-j`op5_`7A2->8tAb1Y}@<8A4Hh+aYxl~h+_K)a@%!QoCG9n~Wb z;yiQGfbOmW?6QYv$zf;D8G4fa&XzEf2h#71=KOXoxb;!);c4K5+u3aJQ-a>rDy3~q zw%=#!E6d>kzj*$~{m`{qPUB%{Yk6iW^0n_j0BSlt{k~sk>9T?MX~xj0t<+r;uLQM_ zNqp%H$lWx{y{Bf5WAUxK4SvYtmM+CjL5$0K6Bm@WwzW5qd01Rqoa;&)#tc58esWJb zx>|p$$2hC)eoSGlgu%iOwF4i3e3l7VZ$>@?^E*#LS15m2_W3txy^i-T?sldyr!_nu z!tg_oaC&5+##QN&NH+ev;N{{r84jH3k2b z?7__OQ5@kg%{8goDBXSnY>o=pT+YITLd`FM%F#X?_PWVy?6KQo|%2}{rQ(Ko|AKSXJ88nBw-}Uk_*J+@=|g_LH{?P8a#nKjq;T``T)Bfq~A>+*8Gc2KwClXwTC-iHPCwq6eO z6ifFW`h9tBft)|2d?NBcOY_VIVInZ&(KP-L3i2dV>6C6TDkFOpUwfBQAQQWRkskXbn zV$|aRn=SRIb?x&>40ebGLhh1_iq+3yq$7P`A?^UszUorg<~BmGhE>RH> zuv44OtwyJU@XdZ^aX7zpAIfRMY%7~gHJFyii)h0s0eStoR=J4Zt=V(u_7c+-vAtv3 ztjQ%umG&%Uqi(^8tCy6#!j>JNR9Roq_9oJdYsVR2r+zov=c;XPfzIk-Ida z3F?#+x)s@fWMhS_F;6Fb{X!CC6l~)TWvulCTJlSKVya68D{G`2ODgn@*w_^zXiOXQ zLB$4s-7@t+RNYAKHk{gTLk_PC>$4dJ#WRK@=|?gjVNM=M)$NamekZqWQ@0Sq!${n7 zS=jL~cO1z@x{NK4_cEvshtuT)<;ZP(K5x?iN2VBia2?JrL(N?{*)>BZr((BbKMScC z+jKl6V$NW~rw363i&aep8DWn=&=WJ{Z8e#4Ip0S?-u=QKyS)LS4(95~H^N{G)m8Ns zvN@Bv5O7>rr7=|%<0gndE@hRzRRKj7mnc1ICa9R{=t6BxeNBr{q8DKc6_PEC9;@l} z6*#QlJaZiQJ{PjuJ6lZ{lktd=V?Br!eN(QetyD8sp~&Tq ztn0P;_7rE2^x!vgB%qcU0ja_~1N&jyDoj_So7te1Lgny54Z*YNHx!JUmE`1f& z?pq7Z&6Rb9X0fWxsN5rNCTV5XWjx?Ue}uh`*tSuVI2dqhRFK|H8t@hn{dk{M#Hku* zXCKSzal}ZzgnX5`kJ+PTMn_eFbMlJb`h@=l%srJ}k`Ll=~R!7s2v-tj3R$ zytWqTV6DjZSg_z(`G`3PtVOUjkF@*r7OAa4WVfV|JPdDn-0PRmMP~b;a>$!P@E*!d zou$Ck<%{}Z>$gd7Z+D^M6BTQ*B1>{`t!ilycrYJmJztB@u7lRFzYyMDd1}bC1kk5~ z9wWzogol;uUxR~PRzHFIDppQ3bSh%%SF<@E1Kl0%wjGB!dzU72kV;teVhRGb-W?A_7qLx1w;xyXxJW&)vKg@7vdWf+% zc`ADOA_%jaLk?8bT_Y;2>;cy9D~p9=MyW+@;D-$Ywihbr&ITYQ;>-t2Hq9mB=tWvq zfKCOX_%e|4wqN^@`Y7m4xt-A9i6NLV2|RNMN`C55V##4S|22L_n!rDCdXEG=_boY1 z%TW1}{!D0Yc#14fjj4eWqIivETVDodT)rXZ@&rF8($J#g3zIOh`5ww`^w%Btd>^iG zcBXx12s+pM3mXmlWWSn2Qp_NZ1)k%PnF_f4VJoRzF9KgJ5}R7HjgO*3c6WeLA7;Zw zLHxPr*mG3lfEN4Nc}G>*X|w){T(87~hk3O|r!5)MzUn>n`K+)KZEh*F4gQRU6k#tfNT8bU6?I9 zvbhAIE4#6bkBNXTzE5TVia*Egu5b;E`u-~n{r+5!Y*s7^GB#rM?(pBYCosjQd-Lfx zr1Q*!1M$>9K$n+0jrX({ryFe1Ml%>aTFdYML`8J-7-DCj35}*+N(PMUGr6CF@Eb|H zabj1<|6(M3y2NR;+%$g|!~22Ztuo6D&)x|y*Qb*>eog21`LGUk55VXD9Msy7K=NdI zUgPn~qXiK%Rg9XpT}v?jT88hDS`B05TgcdrOU7LqNgCIQknr98;-X!0Vy3WdR{G?bBxO)!wn+tVtycdw@;EN9z%If7ZvORb~hAnp=3K@Yi98 z+dJc_uh5C=voV?qDR(s6`jhDJ`xOX(&w>%YJxn!9Ry1A8$Nv#n6ZT_su}z6Gxz zO7>^4YP!q_lf8;T-X3(0*i#Xjc69C=@1bS4cd@=rtbCt*oRor(*2e^oATHQWtcuIf zW`&k=I;VraYbhi2M{ML%^Dx4f?Sj}HsW^o)n2`TTVTY#LL|sp`FVc83_|b-DjUqcT z*i#fpN6l-$!`naZA=MTEp9<{9qWHWzIyfymWr*vLLePMTy7i9 zBq!9ApTci_8iJ;LvsRkJ7}jlJc*Y*n&@}9G0Q{9a7;-Hklz%w{lejJ5oU?8l2bhRK zM^YrAmbp+_(+ucj$q*6OD;xxxlOFoi+7$rcb=ILbRyWp{Rp^%VD;jtd2<6DPgu&lX z&PP4On2vTP53X>369DGJ+~Vr}29E@VYHa20+!Ejqrk|5(U?b#kv~iR9LoNtZ3icI} zstr!C&?1xl`=fjp_;}p5R@HSifA^&hG3d9m0pn71fVwMIaKCt}(zIRITxTO5`7mD+ zyDw10%2|@#Bc-#4-BqdfgDBilZfz>78Y4RVF?8#2p;V@Nv|R3sY>8^@Ego>GH>q{2 z^2ED2VB0EV>qS*yPzGWir_j#iOQd?Uc;`90pbshAB=W~UF^s#yk~9zJ`yt))UzX%D z1=dYtRdQ@8aB0mT?U2k7-#!4)`810#%{gXEobbgHXUr8(je$A->cySKHh%M5>FTZ| z$$pt*7#0n^>Qy&~2}~rhi(zXcRdQhxYq6ZS{wQrR9pgVE&j7MYQ7y}l#)KUOp;b`D zSj`R1MI?#+wW7HK72xf|#LOn4@p}c(HSi@j&Q?Ic^K(_C)2Ujx_X+tb+`^4E-P;C= z7hl12x3!XReLZBt{xp2_I~Enjl&RkFBbmwzZYtx`L10*5k=rqivxG9np~)`%<>DLw zE2|6TWd)gyYGa~%c=I)`!yiVFF!B&KJStacvxTD><~7*n(?VUMe8rY)^eQ=Ee4#M6 zbIL@s@3Dv9_n2G!kJPv2yo>2bxpx@emCHSAN=Bm`A(18^U||UKY|23V`Z=`v3l~h8 zLyuk3r0US9ErP5dNcFmB!mE7!5UuSl)RZrI2WSGZyXH=wHoJY& z?3puX&uZVlSy>$-9WE23 z`KFIroAZFtUM?LLj%jGdIg>2LM!|mCP-6Oviq&}a&^MdoWwQxz2-DlHoe_O2d9}giSOQMwzf< zuWDufi_YzkL3Ra)yv0Npkw3oC&B1LdOV79}(>NudOgB;7a3Y8iAuAGBM_$+mqYLl= z^z-GH5Md`u62-98+ z?$XRuN1p=$lwEV64%aQKVEBH}e0z_i(_PrtzkWQH=47 z3L&cwn~TxNyOd$!w@vM(S_-VHE2!Tn=rZi>&NGE2pUp9G<93gDKiY}JIMSIL{{Jm~d2YD*?f zLizvek1TyJ0|B#Vug|Zy;v*~aN5Xb#G_5Oe$4~nFK8L;~B5aO^eH=2(>1cd`68&f< zeV$?Ko=tm)ocA#24nvMSqBjD{x?R((?#bo^^I& z&l`&mY>nW@1lgJmGkb1D_{|@X{sDC+fPpo&m%BX}@q1r>KT`TR9lL&n4|_A0vf1Mp z8zpIXWFa1NDqd8~FaXxt5^%z78Dphl{CA*qmC8sX&UPgRdVcQq-JKs%F!vV<{;-n| z&5vs8*|!WUurUJqNQ4;;EKgv3r?7lw!Gjwv)~e40T*lNc^BAeoX(pa9*mL zrUK_6oL@q0z>e&=ih`8Er3Pi?`nziZWDxZiIxrxAq-Ioo)IN405A@7IDC6cu89+lq2kJ{;es#)bH9wau1~Dv7R(_HvdnU;+8f+}bN(gp zz9PRUr#k`1@`-n%JSj+`E3OvmRRd{yQus*@mFRNj&2b@}LjP>aqEQmt^;yfW^vE;| zZ!q~t!QR|>iu)Q&V=R9Nu<=At#+ZA6H{(MH)Mieh%dwaP63a_Ca*g5?$Cv>c{UCz| z<9Xfgl*!sE2HXb6cqV|ab_-jvXgva}E!4o{LLO)vKp*8G1%0%AssLX?o83F1fM&ruWzP$g3fDb0m zmqr`IZP>$uautg%oaoEiogZpd%z=t{XXY>H&(DD#nUFx++<1OJOw1yyfR~oL88fMJ zAXgY&Q%yOuT8FFn`58CStR-E%NxT&^oso^f*IC3nelNhmjtZ+;o+|t^s@5w9H!kT^ z+CCF#ONyaQ=*lEeZJXH^=NlU7<1T(W6^#EX02iITsED{QA=+=pJ6tuda~d{R|Skw?FiDfJEG=Fia{ zq5aPik1nY-Gd4$gYUyyQfKV1avaHW-SYhjx_?`+QG1!5`ovm%e~M!`xK*ttPvX1Y3iQZqtjY zn<^FF0GQd%zn)~g`u6F(|JHnZCab4Eu_j8gSqMprE8>oapWmJQZXfZbF9RR%ICClpG*8fI0Vx2)h`e`r`?POl%31AbJ5_$G_EaxN#E zxUv}inGZm_%vZr|EsT@6rVybQp5X!KU_t66j4lGcSZLG|Z6@W4hz+ zY1yEqD5MU!S6K|#Q*nJ47J4?toSVo4c<44l7W!aD>PUJGmo{Mr+FUhIh! zS>UKVuoPagsc@Yh01P=)?B_VjA1Z}&BNHr_?MgIilym@5`Smpz*a5-(+(x~!pEptM z5mpHHthBPu3tZsV^I&ksx;~-+m}8j@ekH86o--LZ^LLpc?mW zbGt_b!PoKi|GC)5vi0aNe+&5iu47*<=A?@X%FB53dRn}qBtYoEp@_H1V+)53BZhM; z=+euoklPoI%9LiJL3jE^PKjxnjZcvIr*&B8H=CsrSC^#)-SOi{l=xLKSeu42-o<$i zG1?&@%(DTA8%NtS590T&0pd148}2MsEaWcc^0_lP+wrnX{9(#(+k};_ZX7B!c{~d} zB{<6Z_(Zcgj5;xo2K;$TvCO@&lK$c4mCXYOi?=uM_GcUmF|7*8TE}a-72;VZ0^ewl z;b7!)ic=Mn8f{YZ{tlkAQtr83p+Hd~?Hru?DQ_bHI= z)!Z(q(9#ZZ2%87BGCXn>iSgOo>xqz-w^K4Dky^WFFrxuZ4YG|8<1Uo#Ed;pU2-9hV zT%nv|O^#qT?^{jD4o}XMhbJrez|(@B7;F^UvL)>0da1A+!Pot1S7t#b_*@>tmw$a9 zEB<5VkXzFb6R6>j>AcLXK-Huw<=4xs9v-Rjg z&ex-pCx~Sb+f0#L{tBYl=v`fNQOg~3LF68Cs^Tb=Ot(M8lqWlgFd2KBkBZLOJi)Mc zb}L)i5O3mM%+h}AGj&^#v zcl?5khSo>!7i5}c?)6cPdH#myEzajwbhpwhx{3$4xtzJ-CGY;*l2|jjIyoYoh zihV=)bAP^H1K}#XVvjtIG5r}VpeWUPh+yao0R)a}fIE(AC=9M+%)eWzKc>!{QWtaI zy=SkI>cQ+aPP8qYN)}A@n~fv8`ByHok}BC&w4c5MTDe1}m8M!EI(fVZ#q8g`q+Kpm zO8OW^{g+_u1*677L#_t(dk6`*8WuoGm995|3xSRsS{5a*wj8;j$M@o300 zmfjY|bJ|I5GEalt9`7;}PRlu7CnfwPmN3+ZV~s46&FjdCo{P}Fl0#&7OQ)S07-8RB z({0d5L@4HPBuajMHizccdS&Z>ftSzcwumoKSzdGYVs#JoY)#mnz)FAi>%$4|+=2>G zzW;lq^R-wAt%^F;*~p?U6U^Fdn@9V&(=h6tT?WM62SuM}CC`h=e?RBq)~vycEkB6h zaT}E5Y3K3_W6Ml!q!8AY7~!@7dVJ1QsMec+&zFI;*!dJ4aIR+@H_5DP@uiNd5$jjz zxx`Hbuiz~sg_4*1BUn2&0?5pLvjw+k!WuY){O14_wi7 zPrmG(F-qvq<1T(u0{K69$2jJ5x6(CBn3`1i+axq@Qa&F;^v$K1n64PnicD$4;2bNP zrT?vAea7Y~mMjoZI(s*=f3Ns7n9zc9kl|f5)U>6&K{vcOj*(s&Y$GddsMIRGEIg=G zsWf>jX`7Q#>7yMeQl<<3O7QsvNF1B{YDe$s7OEb)n_--uhgSF~*s-FqKcMf=>*QIK zKHe6G@u&Acj%B!KZqx;Lzka+K#*@-s1RjK z)b&0u9{|S$O4%s`DaH*Uln(|Ira`;-$h6YZk`IqhO8VQjKC|a^l`LGkq_pRPk*k%K zEa=OFy-P|~S?bcQ7koYb@~s!#Fye}>7mVEC)!H6kn?{6p_(Cnu)O6`XZwTQg9v-;f zC6dswz(ac;Bo>wSJdBQ9ue39&yImRO+$pTM%RI!X+lw%xy>p|t02GCgPb0;@<#OB2 zNXN@1d7a3z?~orgEADW%i1f>}z~bul^%-Wvqb|?=4#bi|@^?jMn&iCNn5nR{Nr-VR z7sPTtRqtZVLyL|MpETDKDVX4!mnq(8qA~fzQn1F0bB;i1L{m|}p;AQn&mcmZCsiT% zAIR@yr>Bl_vx9{m%FlcYz?XVO&B$_hq0eMQe2^fEW%wjrF!^r=T$Qtm>;@_!t*hV_ zcLWIM%#)_cy}|EuvJ{%%Qt`X1;w`_CKN%1JmgJvHUh10!76Pzq1&`D+0RtA6^$^Z+ z^;|of>skg8i70ooACm1WG|wTR-Idqg;z&llL4ZrkwhB?>==osf)#6>20Y$}f%Oll97_((aAWC)zXF0JE8ztF~##VZT;XQt}Kecv7G#21Cs$j-pJ{ z<3#p%I>EHs?ZQa7>pmVB`WS4)~Opwe8 z{M*C}bF9lLOLbl7m$>0?YRyk(C$*|Zwmw-GfzQn$G`|H{eEc<>;*8wp(v-q_Ik*?F zxXpAZVuzvxX}r;l~fqlPAt_HP|&7RT&hjk;$7(dWIs@UoY`t$lxuqeL;KjT zbF^nMnsvTOsbx_;;A*Jl0K1ZOQ8NWAK~xJ_$k+S`vi2CoP&y28ov3EhO`QKVlQ}^e zdR+MU6|VC)$Lp$S(Nd^t&*-5T&u)xoMen}hev`y+v+>>A`-z5vurQUg8RWh3Y zbF|dx(G2k(?-De3QG2iJW9etxk(z7HjDwSg^$Tmex=OX$o}3DG?nisJ_i`mvHNm5p z%Gs>vRyj^*SBY7uPzrJ~VBHbiAQ)kNsU!$b0bUP;r7^|)_7U-|KG@PiDVHYPxs=N1 ztV>Uo+IL}!c48fPr=x>Cj59lT!trd&e9y>>ZcL18_cdkq;76!Ri_=202JH71#2L6N1d`v0webR|tDdc)(ZV=|eJ$d8SfQ zf#Nm05;8DdI7PQ=nLCm4cpeA4Pta#u@$Nzc`OtG{^~rg>%zcE#8MbeM@{^0ynvpp^ zsWj?a-0{UCKy%l0$>QQtmU8_-@3@OwN%1hy=8=$sGHNYl+@HCx8CZW^1Fa2J;p&6@ z^*VkTEu<>cJQzfO!b>+l(k_*CGqSlaS%9doGB>RWMIS_fT9dO~!tg+Lm%}IhB-X?x zN{k>g-Xq>J4gsy=Y`>er+D>eL)8II&>gp)92nb|i@Tqv*l{fyUIvO>wwz90H%#>_};PxnHc&H>4oHUbPe-|dv9^O8tUPjH! z@#-7HtKDVVt>WEgH}=V37_M$YE&Jx{^(q((L1>M&YDuaztsmqaYsRM#PFzFeadr)5IO#o~u z`vTOny}FYCUx;CE-te`ga~3P&__h%!I5soShBn%$EBpG4{OY-4AJ|+*VBLkZu;0l< z?3Q|NM+Ju3J3kg(ST}sYHRaOHv<~4TX9rDWDz*!RF*d1>zo3sx$?#KecJ2*h`5@N{ z5{YiBGKw4UT$|o?pqwH5g;k0SOeEPIMA6Ya}Yt64F3nUzf{1MO>&KuN#C?*&ncS~ zpWK{du6gZfpA*h*?!wv4uk6{)LBZ>pZi0olKKIPN%a+{i1`GYt9i3NawADePmRM^K zeKj0!rJU~AB2MR4h0y1qI2}@PXat}jpgTfbcuB}tPW)-A*Ne*$g zI90|(J)qakIX%-+_-%;&mHdzW{*lg2Y|k6kck9*=ZDbsV-@GyZdv?NgVZ^HZ>0Fm*0bu_jE$Cw{u9h+revp4MBzd@F=og;=`BmM5DHMmr_xz_7;qO>D*oL9e>N9 zF#4$wiQ(EVi}uRSW3YR8BQT{V(n21>2(I+>l;Tl05b=d&S;)Tw5F2M8cjv`}6Zy=! z_A`Yt)2~8)<#)caVx}{O1Zsvon@{W*4BeddjnVUhK5SikD|97}aygE{60gb$e3pk4 zV_Oam|EbS8QP&gkkTLL(gWT(xptj30Lv{Iq350*5P&2uzx??-8Ys( zSMP5UdCD%EV93Yk@{iN*Uo!Cjgs)py++EkxU6B2PO!lT@xRm_|$bL`fjQu5MN|zsD zcuR6Uv$Uj$Kn=yY+~Pi94|B)1x&|4|W5d3%$@3N;p8breZXlQ%VOSRTMdW2ZjSdP&$8`)}h^ow$l*OH6e-7Wa&W=o9KhTVexSrfEyEC%-$U9lB{)^N~Ddcc{!iGW=>* zBRd}fpEuKJq7}bk2?K|;Qw13!@IP^b?>b*&>Wx*-w~XH|5XAI1CrW{JmX8ESfY z4Ja0*8vLlv%_W@uR?h$*&uTG79(8NPcwxv2Mh$#R zn8DX!`Qjbmb6BHwf;D=CHv10BpB{`kp08C+yP?0JTPrxe#+Bp>FHF1eW%7W5rBX#a zH-l{7gz;4m8dt}zWJqJ2%O8)M7ZN$Fe*$fuGkc@Lwu25umM`;=gVID?#9i}lz7 zYQ0SceW`6{rTQG43iK`O)QPJtB5$-0%;XzKCrr0WV{2**O=M=*wXO^(=&ry2Aq0nu z8jL#QN7@^ktE#J7Dn_>q65=T1k?*Z7G*>o525?tm^sRWS+aq%}$qz;%o?07wUQv;| zQKouCv8+3p%d~vW8m;kSSYcgO=OyX$_Go-IEZP!i2Xd8FGCGIR_iRnif1;#-)|}w8x&9nJYU8_X9kQX0c3824JdCA zq)+&@vU#}p%^c`DIEOcqXoHGL@_)d$2fQct@odwC=?WF?Y-M{#r$S z#fIpOe!DOGLj#lFs z8oF~~$_3wy3wzOng>4e=OGYH53H zF;K5ipXx-w7{32z@Ro&9m2&&>Nc`kpIq=v*^oY_t2JDmt2T%<%3K#MPUw=OAOPLI* zRIY9NP|KD(7`(O5<4SVfmk%5lY~O%tLGLkq0jYW=ch{zu2p2$TJ>DLCDbGJ;`#u(} z*X8)KV*^7pwSdjEb!NXuEyrhORf}-8(=NZ#w9UZUiyf_Yz7h2Sh;yV<5Up1J1%RqKkxIQ{ii+fqSQ*t(|L)h>5+oyAx0fw%I+Jt7(rc8_2 z!@>gE^yFy5Gx^AS8J5-HuQ`2Nxn(UJ% z)6--|n#@d-S!psmP3EM@zG>2#CS7SVH%<0Sll{}=fHawxCI_a;L1}VunjDfQho;G4 zX)-@e7Np7HX>vrG9GNCZrODB0a!i^WnO-@OZQ`6+M zG&wy@&PbCp)8wo)IXg`jrO7#Ia&DUZGfmD*lk?N$f;71>O)g54i__$iG`TcQE=!Zk z)8vXYxiU?zN|US8UEU1@T6n%t8n_om5xX>xy>Jdh?2 zrpZHT@^G3wk|vL)$zy5qc$z%HWZReCw>{}>PrBNZx$Vh*?aBV8QT&H4#IzO4sFN<{ ztHu#sILkPqMs_+IM^z~$DIvuCE00dn%5;##iL1ehSvk&-i;bFly#xrHo$<)#sxm{^ zr4Igr^LX9G8?EK!)-(+sPHJr%XNa~^xG2keDhS#?XgMy_%Is|j zdv0flAF2lobC5p2nkP0FKA+eI49bcL#G6jQ`E*G~mY3Sg4=%xzedKa_U8XuuUpO-g z$G@duTt&x5m+-(N0k}bcqBGqySo6PfA7@+T#v7x1f`%)Iv6|4=_NkW3GmDXSINd-s zI3B4M?-f!h-+;nxmZ-HgN^bi;Ks-4JdJNt*$9Q)gKsw3UZ7CWyoqG${3-x$HR(n{DE5bN_MKd&1;V)lqo z5ApkBtlw2(Y0b^DGPrNz*BwHAhp%b3B9;Va5oxDYbKtO>ESB5qwd{hORH${x3Z~U+ zUBOa}2w|K#;4dNLLPoSlpo#;Bl-IP>HB?fw68NGy_Pe2d!X!`3&Ji0&Qk$Q`68FgU zy{cJmSucycZVmEku52k(NOA4XlC;X1W<7hAzTe3_&k~!rE}4eZTuqU{$)Aajep2{k zDP0Uvo zbwyd!2V|8Wj|v>-^YLSHyNx2YR%B%}gQ+7cab`R=r zTDC@^=YuHzY5DL>4PKP%`jZiyBr+g-FC#3Ja`in_H6YPr2)V2i3dCg zW@lft`{>h;6K#RJU=i-FpK^f%lTd|g1I|vMBeUGhS;DWk#wf3y%$k7w02PI+wO)u- zZy@AgZ`G8kg89f`S!K2^)KuBXTad&jK~Qd2*v6xB)l9`!iBK!*skqfoVa#5r)tq4E zWKpW+3)aQR@61yMbbnW2&pPm^xdQNAS&;s~YoPue8HkaIQn|d|+-Y6dhQrG3ljd}F z%$T@$``iQPOu;1Ab2V|SW*EIYuE$oc8h#%f+Pj|ZxtdoOcdDn#nB*-X1K=}{5=_@1 zb8=a3JuV|BY0pxu+EnMH(lnj@e*^DuuJ?jI%USMjD-^^29ns&^Wug(Y z8)w^`X@gshG+x1hTN!P~6(PNyIUSOxqMBM=*Grw1c?VkfRiKULUJ<3H4g7qXd%x+0 z1NfoGlDd7*M=lD+2&!;QR#|HeYw}P?RFSEas@0DWp|#V@&!sywV%$(?qv8^ZL2wlniG^qIPc0lxWBpVWOy|wvlb+Jv!DP7%{cIvLu zIIiXSCx);~He1^)MgE=HuKy%xjA;RaKCU9QKP$}CE7FPf zZ#|z__ODIC_GHbXIs>wvRDAh(_D!J7DvWvxtA^Y65m+~b8YoB4fQs5 z?ax|C0(2)NZA5U5b#?S63VR-VBep#P#@eDo7=ZlihwzI%oE?XqZO4tpP^OT2*ip~R zN=3ft0_Iiac$V)f5H~uyiW!|T$Ji9bL#9iR_{5LwUmO<}m`brwHzF7D3ygkw`4J?- zXdT#THa~-pT_th>?uegmYPTGs8|l;r5c5qABn(`N)_gqM47s_YdDu+CpRk`Zni02W z>@Dsi`7qe?u3tMA&QNSwQKjI!3~DhpSKcf|D`k5(qgcZmB}UgJhOs|3c~Xu94UGy3 zhGJCz{6ElKe&G+`{2u2lEss=iy*{4wF%2hLi3Wftr&zGe3Xx-*`3}Q4T{to{IvoKrl63_k(uv{6>qLQ6Axm3$ymo1i|*{eAVRf9#;bvA~uofrUH(h{!Uf=O59 zY}=$r*d~@+EZ-o=ode>VIvz>MKIQdKN$nlxm_oD#vjs3UKXaO^<%7r) z9dZyKFo<5k)GL~|7p6XhA@uMnm%)WEF;MC@1*QMmGdM%wNC~iB3KbeL=C4C!;d-T; zHIySUm23G46kP{EiA#c0f;8b)PqFq=Kz?p@6#wF45-F^o>#j zOeJcio0YraPm1bFW>w{^%dCuUC3V#@J?D=v$!@&j{-9ZtCeAH6Vws*LBjMaVRxc@e zaAOk+uNantt=-6<&xS`_loMssKT`@d!MG>nKf4_;%?!~?%Euye9t$E2+zM)Dg5w?ZEEQIaa(J`1_L6jB3mnam(k1HVWIVm5wV z2QvAR37FGG0ln>ke=)uU8aXShoPpNXXm{r&*6tXwi=@+YpE8KOg1VbCEwXIkB*b@2 zE*^s?64XEKm6Y7aPI~`cIM6Uz&`B`JmpFS{b6aqhv}Enq2@KmxhrSY6LuN&1-+s@u79&YVhOw zP}-d@T~-*Wkn8}~Zv(H_+&JGk6ZH_npN~>6mMdu65KF^ciN(9!PcUxKw>C4pL~wZ8 zJt)f3gOz(mzTVerN%h!@FI<&d4u=#X{VadmP8xs1Q<~Zvtn`YDMWBBikQL)J zl~H>J<~63iLHxEnza3OO2bJ#rH{%~3o-t|MxcA(7JaJhLWj@a==eHCYo~y!3T-r+~ z43@)HT@XJJ^;7wq5B=g*+#d!vq7>quz%yx(Bo`Fv3&(CC0vZ{#MHR74FTvD3OV0O^ z#Jk@DF#jFJp4s_s@zl;lPLtGoY{p4E@i^}}-J8mUCQ6B#YLq(sfWe%eB?>Cy%hb&U zNzaDG=9X8P=-m$#_(^J;xrZvsca0-vy(PoM=CKkj*8mOwv@w~fY}Gk}b_mLzL2|~G z$`tYm4C<3y2TU=Nx+}B>1^BN9d&irLHchGk!c8sA6m1zFhevrZsIrMNqMrBD(C4X2 z^xp3Y=|5v=i-=_aGu(z0;z5|xgZ?!>hZk)=^u<5l6X^n~=t61nwe``4kG%tOUE~H2 zny1gXjYjNCd%d=&k zny7~t;~fCXpX7DZoFkUT^$mKtZnidncznR+5Z32$f9a}8P{@7gP0^6w0v#}g#&$ng zCNXw{5uE4QXluQ4#D4;T^#RF8RhiF=Vc*2c-xx1hWj94ntFmry1x9H?v+i~&M-b%9 z%spXu39%Ou)DPK~N4+^4FZEf{$TrHqc5)hEvLrUwt0UKo$WJVC!4KzNX|1O&W%(7y zdWRKyV>NDFAL8xJkB_SbjjveTlyR1Z&zlqSlpkmpI+^dk=NvF-QY8_goJ#o1a}No{ zVWyPS7o;n!$4@Q_(z0)lFE{v=Q5+>gceY3L1=k;&=skCF_DWs#kqy&VgRkEku$9LCd^ltSKE`lfidB28+fh*FKM2*{O}M_+ zfkQGJiDdl%PVg9~5{B}a(qHwWPtk|pEe6y#w6N(cU>KxSusxEno;?G@Cib|98_$bS@6(m)s#y z8)P0VJ_I*`=MMAIwO&8lCzB@p9>6*%k1`5{v20XJ_&Jj>> zf5Jq2>eR@({QgOigA5);YFZ5*awRWDaB#9%pE*cywJZZuoq{Ifx4B^CyHdxaX5Ysl z-PMD8tsYlaCq>WF-W%~VLPn)G8(;!kNfelWvua{TtdA+rY#nJA`M$@CY5DY%U#)zEwkWH43^(U(QbH2K{O@ta(YO;Nek zGN}?xJTp1?5tErPo0crQ7|j#-vkNlhwmBcAGk-IaSLAXS9?~Rv$RRAqQNh^EJ<0-%6&2H0NB z?bU1&rux2-!yp_3g4&p7f+&st#zMw%w%laFMe4Zp7YOTtO4j=L@!QCGl}@7*uE;pz z2A%kZ6}>PVy|P#!R%$k@xwU%(JzS!F#8deD*Md@+X7*$Vg=s86r~aL}KU2S%u?6w^ zodMh`1u_{NNsYP+kU1&$qB>pl4gPZ{r%GI~&i8c^^dfYrS1>BViMg}mL##8gsVeQi zoKj1jxC#qC)6t2np?ze2KS5`wdF*jrV3blni{kwdl&afvIBn?E^BzpifdZ9A*cK^# zu7qjVDlQpFk!ZUrI5E3r5|STgTj&v2ecD{08&tQP?5(992!3 zj}hy+2v57E`nqwnE)-O#eiDNi67-7Oe8o%7L9M1MrRb)r_j$xI#tX|-E;?z*HCv24 zSM`sWtWShOUHo1p)t~l7YR#@f`NukXQfQ&cu&HPfWVww)S{sud032gNk^fb zb8?ngZOCk#uUnVt?ikE4&T3zP9X^onkPv5O+94fuAF??wNFp{YI-;>1ws?1t8YwHu z_dY~u@8|kw;?8MGsVWe{YYvpnp0--cVJOwsZY|laR=1&?!o>On0LV5Alt(xM>)%g! zBv%p2*g`${OsU#1d|ucpddT=Z=?zlP z$E41Gj7L}_*LlmP#7p)^<)?-<%m6uZf6uUze<)STc9?+?rJQ@9P|G|0uWX_eH4N31 zpFf<3yUMsXW)YimO(PyLTcT>y^mk0BfBuMJ5OTBf1%BQ*c%4yIErlvsHTXOq7?n4@ zgN28tcgyh8ak;xBR*4!Ge1X4QoNE{fJEcP_p_-gxN0r1Oj3$XA{modCIJ1LkxGm18P0Gty$Kei|%#}yBR81f6 z{4aFre__B}45W7=Td3&UUi%%)%a?D6Ih~E)xgh_NxtIh#p(5VD`BY;*ZQGJSEB-Ca zdIPBkrbC~c@_cmQ3U7tJFOCi+m%)GSk*lep$3agwWP#U+0Ey}7xM+Vc>Dc@m1`VYe zeukwF=}rx8IgnJ9b5O%6))i;l&sq_m1UPSN_PKsjdrC>AGRQp;*kxgXIirz9E<)@} z^#OguBN(1jHw7oBpaj23f}=#b8@y(7N5I^65@uDLVm<*#T97YqrbyChf52e>u(Ne1 zJ~+*6y{;DS9$4RgF7d=*4KI-Ic%9tR03}=QUK>16oqu15R3G=g2;Qxmwrz?~*UN?4 zXdFg;U6XJqj|2BFTKEY+WEf{~IRA3Z9{-8HbyTzyAr!RK7m*2sQ zI}ALA3J$XwQ&aTf?u`gX4a_yE%UT9$Qq2avm3a06pjXYkWgTZRTkB+d&3kdU^Tgb2 zgL$DXZ(+?Ng|j3h<>_6Nu(=eic+0L6WmK>;!oc8#MzBTpvP;%fjnd3*F!1+Qa3SU_ zv5@>xNzcLki@Nu99gwx}>k94rHlott>prH`U_kCOOl6<-?2^VUgvMrkI&bYNxdIQ zRNJ2Yy(g_El95w=n7{sCE?T(O=w=lZo)0;gUFY#ci+&wsIatx%%q^)KbkD*K_jZbF z&#Xxa9K;*mkRW1=TOR}d2Rbv&Zx=)Aqjp};qP>fAT+PxTLa$Z=x!dyxx-qT=#!i6%bsxeecLUTNYeoL56& zVp(TtjUqS0#s11dB%Dr$(h&X#0`|nV7CAr67+b8t} z0wXEqcM-+zIhHk&qi&U8u?#SMZ^&S~22%8%h+EEVz+< z2xeTq(7R{IZXO+CBa`$RBuL>+DEGWFySH@tI^U?f9j?a{5m;)0AZk z-Mt!VotzW2hPI-O+;1UhD}^*hqvxFB9d|MDbsbS4RE6ZU*BK;2ozB-4vY^^0gEDy$Aky9}Wl(c;> z14xWiQ*r@)WZsuDp$&88!@cSah6R}aXE{t{32Eu|YI$Ow+|+SINy+yu<~u&1Kx#Ho zrRm*^ww#kMw>>mx_WImrL^gT9iKQ&@c& z9%-V7Q(aIaO!-l)bg&duvHhKeBzo>^T(7zEwXQH~pqga|?)}M(OvRVZYz~>)%sahu z8}BFq9?xp8mAyIzLsi$XdA#^{SG6%=G)>^uS9eFYW5VpXh8D6(^A0Kg#Z2wgU?(;o z5PQS_;SINQlyoeH8UXHeWY;$|{W0lI1&l}bqX(CazEXLYU(HfeUld4<%H6;RR=!3mtZb3{?|i@o5A z#|i?SA9@h;`V2JgDW&RSh%Bg*XwiXiTb+}OJua}kbTZKt)5{%3ymdsW6y8rO8;QFD#(o9=>4(>~2 z-xP%zBG;)Ka&`_Yb&fR@a~n#`D1IY4ye0>>hB{rC*$YMJk&%%o3p-_*UL`AS>uz*) z*99EtuM7BNn{NIYm5)Uqxv|p`|Fzz~oAwDNh?GKG0pSk!b~`TGA36`a-8Of$?ucMS zWlzJ^9v&;c)Y|_t-+d%@vVPX_3xBx=TC}TE{cwvWE=StW{lpdHa};;0BENGl)^WW9 znY8G-gOvf9$HKA$F$!R3vF7_1D`GU$HxSin(q0@Vmt*)IL%F1gI2%Aw8r_4Tu9W#K z0-$;Y6mtkKj@F;i*I0eRM^^FFg&(d!MB77kDyb-ab1sByg@TV#Z8rte9Zj*kI}mmnVkp7=#e9BZ zK3_!Ol^-pWOIHVc4O7OJ5p7Ak{>joccsFeObtuKU887@p4qjPp$IK$C-Ug}KJQq<) zZw#eICm^9M105=lZ^AwaYg#9mbhSCi+9On(x_vds&-PplEA9Sagv%9O8_N0 zUBNh)SK6QrX$G2bjf%dyYb)9dUEIoZ08bXNN(Q-}DKle}$)rk14vxxVh@Dx)P~fY}DGn8$dQ_MCwC<_t#U+I|B>?{J$;Wp%pYZf{1=KWrA@<0p(88{K_% z40{{XbD*?$^2NmOd5GT;LCxDd>u;2FVJpC<)M+3UV>-(?ncsG@7-Dj$<+Q7<7>&fz zvX+`Q*}27ROBDjnHni49_jcaSlD-@-JA;k<(_kK3Q_tG8z*GQn0MmYdj*S3JL8HW< z3Y`59*`^&w-gTCwjUl%AA(%=LUmYY?>@Mtir($~+Ph5mKf0LzZSaf!1rH60A!*7@y zd!{ui%2+>#p*)&AQ3tw9|1gyR4ObBlnS-)4Z;&q1jREyQPG_x2JL`a-Xcwu(hF z?-IUyn`5!2CxC6!FWiH;& zPl#Uvysw^RSWLztTHO7}8O{zSg%|%WD%FLB>GEh#?fX;Sr*5%{cO$__H z???F~^7~PwckI`rV0|pWF(*cr_)g|mc<7tl(b?iIy^Kw0X@k$ua-b(p(ca8*t>K-j z2?tH)#Fn|p&MNy8lJ(5>35?O(BONU2gZ?eN!p0SyP*bUteeufwb{f@U?g){qzB3Y8 zF=&*v3ZYYX^6NdGp6ADk+j{6lXH-#}c;H6qaukQ`pm>uwJ!uQUpw3T%Qz4Px3iFD5^$k9tyCSt zuLD$f6I;L>F$`P4>jMxc_wMYPcF>gex&CIIt#XNJd^#CDx*%aC ze!olXQ{ru;p0A6;`#wU%2oPJry0e`5`m({OQP|H|?GlT1)m_AbQ9L&kacvdW#H3d$ zr4pXZdc2jzo7oxIaX&!FU(v9jM@{D$JqDuoTg~h~QP1AFv=RzdnRrh3O%T zE2}D0)mNlts*UiP=)_Zgxx@XH5(&0Ib^p$iTK=?1FlC{76XDMNa_ur;Eh*`9xP-y^ zQl%+-($cq`1>p3{&Byox@$#b>#Gt?{AdF<+bm`BTOZ6%_vYZ@D*MVIJamswYPt43O z{zr<*bNXw(q;@aMAVIG>FYU_62o-crW(bD3rdw6D)2m|d17J(3TbR*N1Cbl>;~NH= zV7fsRUp>13u2AFu93CJy&aX2}&`G1gP}(jbsWuqap}Cx!&DOmxYte2C!!vpI}mh9CXoTMw1x$#(v<#s3evp_D3`5$DAeG9JZM7 zfF8X{E-auu^Cr#iG%e4L^6GP5H~&hImzlgd6C7;rpF3z9HCy*e7iWEN=xh}2 zMaKus#jsM}2SNpYsP#;*y3uUVhs}zOu-R86i8D>##bmYzGe%j|^!=%nrCkH|o|mtk z+5SysQFs-LaC5#0xCvc!yE=^L^Dseo9F9b|H0BigF-J1U_*&~%c*he0nT?W)8EghB ze;1}-1&)Ntug~NU%SVqAn8vO`y*6X`n*`l6#~Tz5nd>I5)3b|IY(>Ua?(Cl&we1aL z3IxRPE?==%$unEgH(|*3#`n{ygO?7-Uuqh;*DY_e^hdS zTFCiy=G-9XoOK*kJJUBa=R$_+4l29Zh`b$e-#DZTO;o7(#L>9ep3=n{JXSO6VA`AK z>Soj6#^j_?oWQD1_Q3>7VM3CkOADVMBDpk6QFE=RsZf?`-4o<`RT1#a?Jx z*`R)6C2(q{TAC~j5Q_dHD|4`e>PAC+q%i)2o!uA8I-osL+8g5hZgn_J{}5fTxF*bV-bLN6>vMhk7Xf*y)nPoDAgcn%jjr zJ%&|CdEbvwe3$Vs+wml>Hz+`R50$aIRWP;i?_$5_DT~mX$bX_3GvzBxIHE@JB5!yg zOY1hq6@PsY&XSy9Ir?5bWP8K$1AU**x(^h-!Bpnis3-D0XMnIj3jnssg7})@@jP@y z_7I9-%%AI1jv%5ZP>wq8|EBe~X$;rz0LZhS$&$FygdD{$ueq6A*1(E(zmbaMR zg$j`OMy1yE=t$nx-Xtq@xFN4 z=%fD&*QKtHVo|>LDeU%YF71{!*ovBck=r1lnY(sIF4$QtSnuFttH;^y0745N!8d%H zlhFJaqTD5FCOWIj&A~Z_C}nyh260c-gkuuw-6{O#NM{FWoaWG@Sc63v z=OF>kcuDL)-XWNpsPNL*gVK>lfy<}ejBLvuZZlTDZ%N#6T~nUWuxI#%*jmw*AA`TG z=F;0ji`=%ksHA6CzoNp|j^e`CWhi|8rjKDI=Z2iH-CMSZqsH{RiIJ^UWqa*S%CcG^ z)XRr=U?6_CUA<%mFZs7KfP!HzQm{LtE6;@`G<4DQGE(Zj&APoxuG|s!J!j4&x2=An zr{5QJ_s?|J3aHdg667U->2r?;qR*XJ?G(mvqD;B?zD8qs}Abfmd6Z;U1;gIEXoBr;lqt{(jAADq zxG~3ac627_205!@{JThUHM*62v()cPAXhU5Q*b*Uj`RwlyoiHeEq{>-?`?=AXEm2s z9pyB1RP1U$W~49rQ*GFgbP@v*+6Btsi?$>F#@hP{No1#$g(#jweU8ls2#xe%p49)( z7~%nQ49XYE07G@S?oHNxhW*VhoQ~dJSgu#ehvP?0ncF;N?`d6gr*xK0nlz=W%Y>K< zu6LVKXr^O8tt|tGOp`J`9t!k_7`-_-RW8PUCBiv7_?C(^Yq1cPc_adw=M#ZkCt#hZ z!j89Kz|*?bI~|QZi{ky2Lxj!JSfG(Y+7lto4R&5naf;HI*D&-->2~51K3Af2uY{#A zTNu&4%=TotD)QVtv2;k?_h72!`BYsDCuMm#Gu^nm5KV#Q(J;cYEDIP8TUhrf74I@4 zp*j0nZQ!uB4tHK5sQ*?thQSHwHH38uW06LLv4TOm0HHjDy&!2-e&;X-nTZ+9>xJ2jdg(%!&}mUWC0i zbCBgnX)ZL05Y}=L)^fWV8!wM<;b>=U%jXE&Xm-10CdvdCW#SwDes=MlFL=duA&xf{ zO13@*Wfo&yk@xH!yg@CS5Yn($#Z+EYmSCByA~FLphW|#13-nB`auptJsEf+0DzL^V zUOX3%)GHXjjj&9MJNbs0*!}5Jo84(tF_9netP^vuX>M$>V-=4)N_OO`oPj`r)urpp z!KuFXxZt~kU=o^#H!_lo!*tUL74@7GR)KaYv)wwtPkG#3@f2jbSw5AJP|}|{p6N^v zpRp}oqhqtr6PgUq)hLusRx@Ow1^-33hX-t?!+wqUaZ5DyTL&Pf%)h9zshPNBQP4ud zHLjs7NL?;NW>Zw)l7YJr`;*xC^C5Dv+gzCgkSn|`9`fL@3)2XFYNi*k&I<9d6LZPA zqaWf!Un8^ILo|?w!)kTbMr=1^k)i3@s9fkO45C-icbDUg_P1wl(5vL`k!CN*v>nEK zp6SDh+q(Hzau1ybg-i!?cZ@=*^%em5Z7x8nwoY5w=2`&g)w#ZM=eADdFONLF3$|-Q zEI6q&-}6wl_ZmD3x*(#NBKtu?1&&8Q`g_`2C^NN50mzQ&$0-iYt?Vwlw(e!1)kg>@ zGRms3YAZ12E9D5H*tP);`HxB%8BY|$#4covS`@|4YALy|U61GvMs%xJYw$*<7S}|j zk8r=)g7r8T_aRH9}AiR1i3?u?Y#HI<|N0vgm5 z9x>G2B|nq~-^xR$XXaGH)%Je7QH=QqIKpe070?E$%5D>@FAc*CjtcoNTZpbAnvcnW z9Ub)8Z_WwPZHp48GOTKi4q)7X+*a{1kv;JgMSq>Vp{Jxeb}C{P9n9iAzb}d%N=cP7 zzPDs{%#^t63ic7GR8Uqx5A9$5P zo>+@pAyy9wt2O8`NN&~bgBtymK|9FLW@%C1nQ=JOOT1yz=|EQk^}wp<2K4i(GdYph zu*K)yy0@n7)zMkpZHYP>igaC9VgJe?4-{z$SGA(i;BE2}E5<2~xYTPlT<-Ajv2j_U zaEM^G1Zp43*@d}CUiYT$ht*HbAAo)+4SxnnwWJ1#P0=h30_jW=wjJl=g*OO4RyGsN zhu=o?+u)!N_PV%uCC@?~j?Pre-2b3H{0aK>c$k+dWv^;#Z!M_9YqOc${W+7UZmyW1 ze%~7+`J@*hIFMym=y@RQV{-!Rn%sXIAE1kyuj4B_iw8_=^-i_%bTLnqcALgH(oN!OCDj@vp#ro6fJC9;q2@FhoS&jwp`Sp$V{A2Y3E0*Qu0yAGPlPk)MhM&|O% zvM!P)eGa-@?t(sd53075rHQj12%gP`8iu@P!x2L6Ls;0FucpaAs+Ia1a~SSd%1{np z$Yoz8A?rN!eG?JixX{aeQB&_@;Y8!&P}JF(7}-7O*_pWve7UqDi#sEywS~})9=UB& z8C4yK#8(P$;yiOzeM?od0Qj-sL)+*O+jE&?MCw(ofuk|b=@^grHxH)sT4~gj{PIiv5oe?KSsdlT}g#L6qYV%acHcfvvWu6>wfjqn2oAq=_+fq&13{&FnUQDO}-dqPvM z4JH!eOdPCKxD`;%6UBE7OB^dB+95pfM*f=aE=cAfD1~@2E^!yXy{&_ROG-;irgrq-yL0w_bJ}N3oH@l@=&4+53GB@0&KM)y@F?@$;tq>v0PB*O~H@IvyBLb78a8Bs`fDkM7>l3fbP$U;(9 zNXiRIMIosyBvpl^x{!=2B%=#SO(7XmNNNj7T1e^&Nqr${C?t)Aq^XcJ7m`9DX(=SF zg`};Jj4dSN3d#6FGNF*{T1a*)B)b=qJqk&CA=$H#Oe`dO6_QDXWO5;yQb;-q$=-$J zzCDw*CnggoCetS-`*f5}?y9i>NilpfPj zdTdAO!j978I!cf4C_SO0^u&(RlR8RI?kGK_qx95{($hLhPwyx_qoef9j?%L_O3&^9 zYL*15@Aj97k|l>3N<8^TZsQopXl3PBVmxPicLg4I6J`I>m#VHzx5{imwOsSFvEYH8 zWL4C$570z!N%o=Wrp+^kAk_&7`3)&N7h(yv3zg+<1B2N&Cr_hVq6=^Tg>4;c z)jsnDAwvC(1?rJU1|~};zIr`~@UZ-<$>a*BwK3nF?IdTn@`~*m#CT|wRSz2|NeRIhre$Y(&@tiiT}@z@0`%;$n5xjYj=E43M9pl3!(}!&~J!v z-mzppoIvQ5+fpMLYY(q#KE0-y`V`h+zZ!1;=c=Lg|gI!;NDO^74^j)LZ&GB(_|>fi^nTy~?JOn>|Ek_#=k%4g}?I|BY-n zJIcIH#Qs;vZPUf9#fM5~VWRijxi*_*ys9tU2sw0Ra&Q&FLT#2Hhn>`#7as?_h*iH> z1-#wW#+CBaP^q9|D^TjdxhU!xndBP_WtAqcDlP-*iEmwybTL5vo zY^p7VjF$&$`UtCWv3N#5#B)brI?s6y!;XrS+BP8C9s%vlMJFAoRza5tW;r`4|QVke1tBxKX#Zn(ID@s?H21#Vs9KzAD;oc#%)N z<*?b-DQL4Bfl0g`Wvip~;&8+?BwN{TwlmIQRo2RbG;=gecg8l&TvrI9tZ0^k9Eu=^ z1ee91+7bw{M(2=l+c8iQTrCHu?M86Yea%h4DSFrd3Z|_p8Q52jkVI_78$wRbKbs2g9K3?iz!-X9> zr7{`d7?+O#XW{dcLR$AQh}?5jm}-?APo>Mnqu_TKQN`)U4J; zL~Q_h%0pdhx|-uUGS&Ysvse%|t?CPr-~0e3F{P!Yj(^{da~0!k8mp$zT(aPA$N~D= zvveh9F4lO`XbG?`v6L_PeZfobAJ>Ln9C)(31_sF zqX6cJ$wba-i0|x;6n@C<6B7d8)yD9JfcpmZ#xRTr;KC(IDxYMY^NXRIkw%{L{XU$i z)m+2T74xVV&#N%JPb6{blm|C!U@XhpH5ts1x`Qvp<=r=kwrExHL(5s}zg*hlgl=4(NPF^i&uT=G>$kP91a+F1-NmAINqCLWbqVPDOpa~l9Lm_}k*z4+ zSU!LTi5+{lffB+DgfP;ZL7cw26e}2?!-eTYqw}@q@ZTp2*G%*zXIKNMJsAwvM#rZ3 zQts+*PISD)>yFuN6)QLt&+%Jzwz@6SBusO_M}qex z%(SID;+y@k$&dX5zKMoh+R;34dOmAfLv(}YKd_rr@VZH&TW51`M>CgqbEeUn*>9zv zoFtetaIWv=w63nqUOA>f=6EKudai^vD3^7F`=Nnv*@(Eh3l%Oi1XN6O1b_ayCWb{# zZc?z}iHyP8d>9vuK+5D-Hp2st$dJKTA=xv%>SGt8=ui1Ij$(d<%Z2LLvVy{@{ z`XJI{$b1dE;I?0gI&`)_>wQ(&=+8=sGf@i*Nn72BCF@ zWwDizQl?8-mgjsVII$+TrnfrYu4yLwj1Ey|t38!LJ0JuGe#20?&Fe5IZ9B!+Q! zwsP5yh!**Jh~f1*Z?+X>auMHteFXZkTx(@VdQ`!!ea-VnBrVD{JBx&p$0-+7Lv1d;x z(6|{%Y@C_1sZ7#2+N05iT}2@&2p$Sa*E3?$R4zJK-UlXkj{qcg2#6D;ovu%W@Qq83 zRJEk4aZ?jqVp;|Q-L#N+76H%A)dcx8OW@xS(7iDLf3vxACcwVA#{2Hf-nhKaP!R1` z*MsK_bwM#iODXudpz)1r<*iWNF0`bOt1`ZOJs&eIDzorhe`y1>U_<~+*EqpFsF(Ue z*ye*$p&J2isgZqI#zIETn$7tWozcG?VZPwZ-bhMws_h`18%s#ex(y43KN>_X$??bR zK+0v@3*cF=$(vJKW7L)XaZGxxuvT>q*&)L}(@-n=}r@;x@)AQ6J z>7wN^$mk^(yEtTtqP;<2^$AV}hN+Y*rt%ev{&Z|^ky>ntz3ms4)B#hpSNb|RthIBS zAaxUE3wgyOk^11sGxd@2MSt{XTySuyskN2sZ7^`7e7v?#PXrH#BeNwLjQML^4N^*g z7z&VW6?=^MCb^T*t*Nuk>NeU^c**#mL3iF3E6@J1s*pSyd+8NG-`r;_59QpBmHs=Q z1*#dWL@3|R2konpi3EM(EG64sf#0 z{l>_ont#TcG=|l4J1lnfsMAyg<`%?ST`&@}E%G?LCz4_dfuHT`y|L8Pn>a6+!aMx< zT8`-)Er^FX3`{>-u!U~VAb$d1cv;k)>b%Eb%ymhQCbScV+eqyi%8C!m&?Gfm{!$A6 z1WQH)&z0ST5nn=gA<)06q;TY{U4lmS0Xq(fUKrG)Ej!H+g)pOmk3WOJ?2eNx=er71 zIM796v*xy&!vK}EFjw<=n>VbS2OIV3$9)m#0ohRZH}R1H7NLG`GRC#?KQ7+Hna2yt zGW)QbE>c>TVIZFb>~kB@V!cnp0+!12C8Nu90JS$P;EwFup$@*Td{E{i#3*}%&>jBC z>^A!%KJXMH9q1O`CbY~F;$b?uyqtrq%OS<&XfO)6Yw#&%gDE;?a6jh$vV*?R zu*e4EiXIInT)If?L!0d|F^L4-TPJ)4ztrN6=}II&m=FC&LQhS~L(2Q?!Xxb-VaxPk zqlZzTky)a_6k|o&c`2&>Yhbd~H6}n5`gIwyS~oXV+cPvW_Ct_Vq8}-bE@Yj=BVXz% z#E?wEM{`X(rB7KsH zd%TU3sRwt!be9CnGA=Sp_e2NbhXO>8<^;z8e^kJ~2@*U$kcRkp;Fl=tHPVlo-2oX` z6>y|=60{2>_#_nG$Osk%eBky^nN2b63$BwsM?23IaXM`?jN7X-m*KH=<`j%r{=4}4 zIf6`_ip|hq9OP?@ra-z|_G0(89 zS8QETXfLa1AKP5hLMZzUCwCyKJ*k`{c_dZU95R;f=~I++h%icShu06BgGx=563g;6 z(r_O|UR!&*U~i39S)o%P40C;wB=XF!ElmqC4(Uvr)io>YB>NSuS^1A+#Q_UUjE}m@ zMK}s1_|(4C7Uc|Asx$`g@rXn10=-_;Z~YP1bxz6AFaWiB@Su76krhb}{pMYR?b6X$ zI7k8ZZn%YIh1kqRPR6d)5cffJJGne?bRh2{^mN0(XxN66boMEx-WJx|T+LKh(<1bt zggFKhU4K=Zt<9+DJKZOmNuke-Fymw6E&8r45M#F)2}_=T?| z;UGVGItccQta}q5n!t$riw~6*SJxlI7oK(d%%;@?VLe-L^8KcL#U44IOYQxJN-G|M z(jBbmYR#ZRWwbv3!K*js^k<+vz`F{=+|T=!jOi(xejS##oW~vD$$JzVrAR+Fo$O0* zk)J_{5o|ZX=s~Fa?ashS*y%1pYm?U7%Ud^n=1tQ>sYs8J0lg`xb8{vA!ljx_K$|DT z0+WA#AM$!q@JZ{FqBPa!=;Axhw=}d391?Adk7NW@xiBey4mqr)kmZJo4`iG}Ld^o` zz~}ixwzIPi>r>py+umW=1L4-GC@;SgtMZ%k&CRr2?j#YWj)Lu0+N0p<1J{TAxKC0 zkb7CE8Nx-{6i}m7q_uF9r-WRm8M_^tT7&P1Yn!FAnSDVqzT42XS0yZJUpNHo|Js`F zm{IM6#NRdY?X=+I{n05dIMl$L%*cC4xF($}^?M5N_ClV0%ficeqhUK->`)!QnnrQ-!%$jy1lC*{P`#SYw^ieW?^(=bu2Ig@BC&XV zFMQ{jY8lkV>rbq}iy44c7Gx*7fgtC?Tn+?;8On>7e-2YVT_Ci%07|Rq4=mA}Zh%<{ zoRsyB3~t*98M9l!i@@y)$_|s_}#;3}&D@4YOH4 zcFu(bn2IBP5_Kxde@w9kDTMnJ4Z2Uf1v<*!j+E(!towe}KFrbfY@j+|dmSVBM1T?Z zcC)__a(Jhq7S~HHC84UXDp{FzyEDWo?)oZ~7h4A)dOb&Lo8pLzREFbp?w5|yZd1vr zY=m2U)vG&TVCIvld%P_?gb?IUr3RyP<=9o|z&tT$lR}p|(2q&?2~#3U;c}9q9jhZ4 za*dEax)^N;UB?<$%W%Woo>O!@_iE7a3QvK2XdR_BmSLq|^44W`$KqX{K{(_VJs657 z)Gpo~jON`;7pe-iRpUoh)t40toB^@^T_95#T>n!SakQ8lo26G7L&Q-pL}$}oGP3;z z`&q?nzB{jBu|WFXPPpcu;$ zIvF5)JILE#7lITIiG^h%1}rSTO7rN4r5`6PU5oPztbB)T0HzC%jCdFE{pZ4;nwU1q z#B9Upx684pswv}@a`WYMH1uy5MA{ZML$)UnKuyJxP6QJ_%pW1KZL0^QoT_=`KwoWC zbkzK9*5u%zTAWb`yhwcIKj_wSLST(1)RVi})3Jk>9B<=}Ig%5hv~>`qZJ6IGHH1PF z<9~t*rNJ|>5SbXH+D^tZRAg#P8D*3pxB{2`a*#kHCB$(p*I)#&PuOZV<}+}67Mmba zO7girxO2TAdbuxUHO9DnG&pHGXGtk9CZlj&7>2#YQm@pCjN&R`8F?gT-v41f{JeS~@}i@CQ30%J;B^hVj8IKqEr>N&P~ zRB_AZ9kAucLK*@Eax0r{C5bN$KsHC`{DSHHKlbheN{XUy8~zTP$zZ~ailQh8OEeQr z2g9JmLMwuX8u2PeEI!Y4EPHhO!xS;Yym~indRGe`VHhK+n*XnSB@gXTgxA4=yPa`m-Z8usc40 z(2uz#^yVPE#vH%X*l%wJ$Hi6HWqxsQ6fQ%$;G-PgpDw~X)w7>93auXMzv~8nNSXMT zSij-mxgxwbxQY3MJ~{-SpXTo1@4mo+PnRVexTfL+uqQrt$DWU;$Ly~Lg5j#oAk}nT zitqBzD@q!lmQ*8UTy84=5IYHfh+TW!4Y+|j zr}?;9NpqW@Ij?!nhVHRV-RphOy}{=0HMVt6+1@?*>+T2b>YlQ@d)lwv)An?4kk%vR zydL#u=Eq*lkF3d$yqh2SI6v}re&m<@NYaQ%?Gce)BO-%FM23xs6po0rDu}c#h@4Xp zxuhU6v>;Mg5E)YtnOYE8SP)rO5LsCeSyd2utT57IWTfTDNY=>6+EI~pqayE&imV?M z`J^cFX;I{}qR5V-$j+k34@Hrb;z(+7%XRT{}EjkGR}v?-0WEseA*jkGU~bSRC?Dvdl)8kt=hnNu2h zurxBaG_s&H@^EQnVQFMhY2=a8$fKo^#ifxYNQp+4MI$StkyX*i+Gu25H1bX~vOXFq zE{oh<7P+S^a&K8=W?AI^vdFBm$n3JnoU+K0vdB|qk(bIMZ_6M=Ki}AYezX51;k}Dw+J73_f3SOoKY$ob zCJy#4!l$o1T%u>zKSy&L@aY8)*P56_WiTEft2sOV);{1IK&F|_D5cuFF zyter`M*QH-NQO*6^7xUQ>E zR|h|c)7^PD{o-Cx;;WyI%38Y13>#Y8PaCw(+HcO|He97F4c`vCyqQC;$8kN zKI@V2vWMVJSR9Ou`gL`Gx)$s}gVEa4H+&Ufh- ze&^d_qpQP5m;U(D;)D-JGaP?r1snbkS6C4Yg>Lfwh}|N%S;Kw|Uub=UZrl)m;FFVG ziNoD?xYIT+*xY{S>n(Vhb_{g~5&Id1#CxVga13b`41@VF$^HY~+i~q&GZ@FRt!ila z!&Zb(OULl%$sO+Wmu=y3%^cjX>B`YnFZ-FJVBlfj%F%##(YtoV*UDmsKFEuq*9+rg z0lS6MsY~K*o&&J@?qF}|KOlUI$7U^;_Owp0fkGD>M2F`sZTf6Y&<#3T+C%f97MzUX z=V_r25=Qg?VYj~zd(N5ROCdMW5US?>hP9IJK7-$TKeRZn7(kdsTzPm+KE*2?vcB zUhs6@mg&(2Uv;_PY~Y{h*`i>eiX(gv%@TxnowfMDjEIkiai~UP67CPJLFYf`&({8~ zS>KCCCA>pN<81oAJB;@0f;~Oqu15!)On-OBHk)?Z??ZA4_M98SuT?(|u-`?{HoVlg zf}XaoZ5z;UV7L9hxUC93-adX(>vd6hKl}pSQ8TxA@qXaW$9ED=sW;(W z*%j=^J@6y%q0#VtsQjA!`WoFB{_K5$o{ojbB)XCdHDM!q@n!WQexNg<7n`6LSI0kM z-3D|D|M7u+UE{3K4wd-%iJ<9~!AZ=0?K~#`5=JDO&~;6CWWb)1_!pw%@gA)R4$1vm zwZTv*c))KnUilE;ZGJi;;d19$Z2d3oKzQSHFQ+hJxG)s2{8|6XG1Ti4p5r+ZFTLDl z+Fv>CcZ+2MPSEv3$3E_2``w){$8m3$ZeZF4aKiDeKSs5?L#Mg$rS%}Zy7z+{IJl4G z?nQ*&vJUupvW^2Pievag@Em;M8Gcejhn9Q%p{2urm5nR+@ID#*G)8C>JFsK!@~2C8 z?8V<4?)U6Tf0XIzMWFot(8=_XEn~N*;Um;bL^{^xBDskr5cmC zzl3#n)5EW-A;v&|g@;l2X~+GK`a^NF+8f+O=w*K_g>z8C5b!eGMR=V(uBTe;c6WH> za1#3c-e7pd?|TmQ?q2lnDd7_~rkVIST=)z%1-Ixnhu?bth^Ox6B^+csV=p+CyK%q7 zzfijYyYX^fQ}I{Q_Ph0dF!JjK;}G1{u}?^-v1J&FO$r~r|HC!wP8`M3f==s-Cv@zF zVyKb=^!$S0G=_s=uWo(&gilia&|?P%1@Ks%ecD3jndk92dMG{?3%sjef&EysjDu*)U50LCa4)dbnNr3g( zR;Jra?E4zBLY*-Rucc9NTIt%aRp_kJ1$+J^f4oTiKA`Zvv9mFT7XR2c{yCJt1iQt9 zp$`&8tDvq8P`-=h`JkaZSCHu`Wu0$P;Scly;>(do;3JG@<#^Pr2fw)Pc@qUNI z&q5W3d^dzYbZ#ClJV4lnBgN|YIs89e*EYkc^wPu*=SVo=AYZ?E{;#(9FE(7dK&c_AQ0PZn|9-a4lo^}f+vzqBr;UYUd;z#d7pOi^BGyWJ% zZ|fnZ#D_-u;qdgWYozW-;ZGleE4Usww)IuV<2f`O%iZ0ue>@4f3`g``?Bm`&F^K3B z?uP#8;8wxMwL3n^LH}Ng{;k&2Te!T#uPG*cFh0Tn>wJF&;U%)u46>oAJjU+B{(|4aJYr&QujH}1UPxx7kzz-lEuf4Z(cE5=0a zcaO*WDvla#RhP!vwXL=RB(j$JtVaKybyi3BlM6icPw^{EXsb339bP^(w=ib4J?=Aa z{I4?S;MnEw(r00<6x@?{?Y`RosyEyAw6AUSzogIb*U~xV)u`uLU;dtdNv}IGk`yZ( zn>VyD7sWIDX8W+Qd>dx_O19pjR=R$w?F(=I&&f}^E+1Zidi(eq_H?qJEyrsas`p{J z&pEF}Himeyyo$V%T%S4GXYOlnZ&G12#$I^Qr|I>Zb-xb*Ft7ao# z^DFNDm-MFlUE!!-NBZ@a1-}HszI)SWJo0ZDOM@NNb__KBJ-^DLf6ci%$YHZL`c=yR zE#nvWdboqxnau6&WkG4ZjQPHvMS3TKcW;x=dFWqrE{Nx-y48NA83TDhX{pcrW}h+b z-!j(N?_l$Yf?WYel((9@9k!q_AHQIRUW)oEqVe5Ho1N~nCJw{_!fg{fM-f)q;&Uea zYtGTFupNB0gS*Pe^W}eQuaARv<}ZE5FaMTN)!Bda_!e#RYn1(4#yPFgN!+;mz)$fH zIG^-y8Btcncl8OsfuGqVrrLwtuK#B0bya1@&=FVox+6-C1s!{h&zc(Vqr7VSJbvxB zFzH`&Ru1yVc5Z&LUnRe-J631s=9b%U&lQ*E+OEF9XYb;H%60k`KJk#jzOwj7{}G>g zQ@jm@xpwUR*5_RFuQ~Izhq7%y`mR}R`&z4ZcJ{K@UMp#`b}5#d;VYiS*N_vf9IB7% zI-hlQe4E+{KlE7(xt2TXEAMTeH`l)@=o7qzt9;krs`O~ABD=ymYJ$(HtsJ}~IC8sB z!u3Ay>|kHicAoRwna4Kd$6LPMXDw5O!?W=eVO}|pT9bU06?$FliI4qCC${$csXh;9 z`J5*Insc0TSe1QYitFo_wEg&7e52oZqbzPETAr7mSCLb|w%x+)nznk6i<2T4tKr|c zeP;a6#X^v`Z=Xw%{W|;7lS+psMItHo?*RNe82=jK-$D3y6#gBEe@EiqA^10Li&c*0 zRxQ8O@+&R3X}Mj?ueJP!%j2-_3HWy+{vD5hr{G@`{5u){n&RI`{2PUTMfg{Ye@FA+9mx0b(Z`5Twbu|i$^OT)hm{2TYJ8uFc%-)p%;%bi;OpyiKR z?&5O)jv2Ry+xb7)IpcokHvY#Qgx5J1|E|ElEAj6t{JR?euED=?rkLZN>WBj1UI%2MKV%q+<-5WLs$dhjSQ0! zj%S#H@Fs?-2q!R1LwGa8bcDAs%s@DiVJ5;!3~M5s%&->1DGX~PoXW5c!f6caBD|Gh zJ%qP0tdH<^h7Azj!LT91I~g8;@Ggc2BD|a7K?v_*cre0y86JXgI>SZ??_+o(439+k0K=mY&SrQt!Z{2ZBYcqIF$m`}JQm?RhQ}eC&#(!?hZr7@ zZ~?;;5I)SXDZ+&ePeizg;YkP|Vb~1eqYO_*xR~K72$wKyj&Lc%76>0>cq+oj8MZ{Y zjA1K;%Nb@NT*0t4!Y3HELHH!Ywg{hM*bd>-4BI1ohG7SU&oVp>;Yx<5BYckG83>zRj>Z!nF*0AY8|=C&G6a_CmOxVQ+-*GVFu!J%)V|ZeZ9C z;YNo25x&oG0K!cS2O|7{;YA2PWH<=nM+^re{Fvbogr6|H7~!W3FG2Vj!%Go<&hRpX zn;Bk?@C$}R5pH2P4B=LW*$BU6I2_?u408}}W0;F@JHtGLUo*@{_zlAm2)|`mfbctp zg$TcAI1=FwhNBSfWLSjo2ZqH6e`HvKa2LZ;gg-HiBK(izcU<-@DGO72=_7^gYZv=V-fzv@Ct-~GrSVvK89BzOd95nsaGS6FuVp~ z4Tf&e0Vaz!_5f4F>&R5mMk2^f6Ky~Ori(T%0W(A!o`9L6jZ(mxq77ESTB40vz}lh> zUBEh`jbOmKq77ugdZLYI!1|&MYrqDgjc&k(q78Du14J9^fCq{;#PY~ylO~rZSiQ;_nB=I4#nP`JCG~;CPVe%AlA=zA9 zM79uZpoVo%6(1#Aii^os;u11Tv_Tx!Z7n`Vwh%p zl003s!5`K=LwuS%Q?#KVa?cWNLZ4cS9{gX}53N%j)oB72K(lYPXsWM6R| z*-w0j>@Th-2Z-;I1I72qi^L7&AaNr(SbU!xB5oot7C#^_5kDj^6+a>`6F(*|7e66~ zil36h#LviV@pE#xxS7lmzaVqPEo7d!mCP5vBu9u}kp<#5vQXSkjugKpM~UB%MdG() zvG^TXB7RSniaW@txRWdse;~`nAIX@wi>v_ClW=vAoSa>Niwj&FASyzHYXd~ph;V6; zoQ!FO^dwvvAhKLs7$Axw!gWD%%J8Tq;<^BdwhAr_l9O|66EVKf+8c0sdFUlTa72|pU>4o;1a6Mq*ScJG9NKVePd|VD7 zF=kD~<$#4&6qf_Zsrk{^XvDZ4NKVeTvbY>bPIk58Y9Kk;Rf>y&aB7Frd!DzMOMz*T{T)@oc8SZJ-rRY7v{ zD61A11&FLxToWL&N^wbm$m+xu0V1ms7X*l`MqCddvI=oIfXM2@)j)Deaj{j1s{sqG zMqCY8XjS5Bz(T7NR|6JWrMMcf&}zlifQ42qt_Cc$dT}+7oa{Om7Xyf_Z*eVv-Pd(3 zt_3W#ZQ)wLLfaOu1uV2};ab2#+ZL_`EVOOmS|B+sR&ip>lK@-|IJ7e0dcYyefGYxr z)&^V?IJ7a~s=%SG0oMf%?F_gwaA!!}>n z!?s_~!x~WE!&=Zl$g(}6p@+5L01s=yfgaX^gFLJS2YXlx4)L%SH1e<(9O_{$ILyOZ zaJbOgT5yDiwctn~bqwE?qZC{E(Tc5MjTKwFj!|sQI##i@>Nv&Ls3wZ7O~)&?CY_+z zTGSMA8n)}+l@mQ|%O`o*rki=#womr3ji2ISTW{`Rn{VM^+dtLA8qm_iTF^>x?@E@3 zwV<_!wV;iMwVZaJ5bgp7+(Rql|uwD1AobO>< zzQDsaeW8bKySs;NyoZNvy{Ct5zL$q>zqf}qppS>Ops(QGm3|)9g8m-Xf&m`Z0*tU- ztFx>H7+(|C0*tN+YXQdAgtY)8Yr%zp#o3IrEFR9dwZ%D%+gO~-xUI!`h*5hk!h9E=W+BGQu6BzH7`L*x zka3p9BN?~07-M8B-^Su1#%(PwMvU4=BP?;@X%=Es>}t0dLt=|tS&Z?p#aR}YGj44$ zM#8Rki!ltgxUI$gY)TP-{#hdu(Z3r1A>KdD+b?Zh|Nj(3|J^?;>&w&()?^L1b07Ji z{Ik-2yMF2G3@`sDb@?*k_5OEadoBOfKi^0Hw)E}z-(CJ!+qS&=|Cj$Y#`gbj{_BYC z|KI%QKV$#4{O|U;f7@?dIu5k|uYH(p2lb7$jr-Vkvhe@^r#rH(<3GfH`9EFv|5UmE z?!y#*o&PERf7-79Zu|fLhxz~0ALem5OQ+}g`!&~@%Dt{1mh_KF?;Clq%O<_YGqg$X zn;6=p_XLJE>3uUpoAkbgp-p;EWN4G#lNj2h_hg1P={<#^O?ppdXp`R47}})wtqg6_ z`!3usxoAkbep-p<<$zby%g`ph=P|TN@A(XE()%HX zHtD^9p-p-}%+Myi7c#U-??nu4()$sHHtGE+L!0zo%+MyimoT(R@1+cF()%%nHtGF1 zL!0zo#?U6cmov0U?-dMf()$U9HtGE&L!0z|ilI$X<+NAdehBoQFk)cg`zt7Mny*DwmN$(FB+NAe~3~kc;BZfBV{V_wE^!|jQO?rRI z&?dbAj7iO?q!HRlDoAlnt&?dc;vfWI#O?pQd+N5_4hBoP)%y8Veq$Ha|OA)UnQ^o7ZH1T>eUA%$J z5N{+i#qnfK@g}mCIDxD!-b~gJZz1c76UlnwB(lCZnQS0VAsdQQ$pge`@Q; z$B7S+O~l#c@!}lv1o1(#sW_KBQJhDfB+e(Bi4Tz{iwnq8#D~e|;zF{8xQIMee1vQ% zK1#L{7n51y60)_plx!nDMz$3nC)&X7%JLCXyJvmT(m%K=Pj~pa!AP0*Z z$sywV20b@-p!w@^bNGa;W$TIZXVN%oaZ*hl`(+IpStASNwv^6St80 z;#P8m_$65&enl3F+sKjPc5;;XHCZHnLl%qQk|pAIWU2T)85MVsW#UeOEIi9eDR z;x4jM{E4g*e+vDjl4qKLtZKVPF^McL0&EHC9e_xB*%$=k=KfU zlh=v+$m_+Vh&%t@AV$a=#Tw*zF`2wcOd%(TspQRK8hMMDPEHgv$Vp-*Ia#bpP7!O7 zQ^nfkG_ekOt5}!3O{_=WF4iaS5F3zpiVexT!~@8?#RJKE#DmCt#e>P|;vwXHVk2^f zcqlnjJdC_wJe-^*9zi}J9!bs?k0R%YN0SeVjmf#$w$PK$VbIy-kMJdJ!#Je_=AJcE2eJd=D;Jd1ouJez!3JcoQm>`1;U zb|P1aoyph4F68TCS8}!3ja(z1OTHnVN4_bZPrfByK)x+rNUjyTlk3DDF}=;w9wg z;-%zf@iOuY@p5vDIF#Hf4kN!5v&pZ-;p8?khukjal3$B?sD{7x(&zZVP1 z9pXrGr#OoIK`bJF6pP7SVhQ<^SW5mZM#*2qGIFW zy<#=_r#OcEOB_r7EnY$H6R#wbhP!LtaaWNM@oKV$cnz5>jw4gVYspmcIx$oz17s6%HhH`_hde=ikZdZ>B~KLRktd1s$!6k1`PFzN|7nhTG#K09^LE@U7U z4iMLq1I2gAi^TWHLE;8-u(**NBEC;vEN&t%5kDX=6+a{|6F(v^7e6M4il30f#81g= z@iTI`_&J#)ZYFcZFUUM`3z;u&B}a%~k_F;dBz_gu?a$lDk>Yl8l=wASBz{BU3r^j- z-;yQbcVwyfJsA~ukY(advRwRujEO&z72+Hqsa%w z#^hY_7;>I?EID61j(kXLLM{-GCm$A1AQy^F$wlIceUA%$J5N{+i#qnfK@g}mCIDxD!-b~gJZz1c76Ulnw zB(lCZnQS0VAsdQQ$pge` z@Q;$B7S+O~l#c@!}lv1o1(#sW_KBQJhDfB+e(B zi4Tz{iwnq8#D~e|;zF{8xQIMee1vQ%K1#L{7n51y60)_plx!nDMz$3nC)&X7%JLCXyJvmT(m%K=Pj~pa!AP0*Z$sywV20b@-p!w@^bNGa;W$T zIZXVN%oaZ*hl`(+IpStASNwv^6St80;#P8m_$65&enl3F+sKjPc5;;XHCZHnLl%qQ zk|pAIWU2T)85MVsW#UeOEIi9eDR;x4jM{E4g*e+vDjl4qK zLtZKVPF^McL0&EHC9e_xB*%$=k=KfUlh=v+$m_+VWM2P@5%NZ{2030#CT|i`$O&R9 zd9#>C-Xf-x6U7X2l9)+O7Hg7I#9HK3u{JqPtV7-^)+KKf>yfvM^~pQL2IQS$L-H>1 z0P=3}K=K~(Ao5=EU~;;62zj5_h@2rFO3oAyBkvavCufOAkPnDQlC#C5$T{NC5%DDQQL!1hSUj0rBA!An6`PZf zi7m*-#Z$>;VoP$l*os^sW|2>bt;r|FHsn)cTk>hK9r=vdo_tp9K&})|BcBsbC!ZJ3 zAYTyABwrNIB3}~ECSMlMAzu+YlCO%L$W>xz@-?vw`MTJZTrGAZ*NEqmZ;0oSZ;I!W zZ;2O>Z;Ka_YsK#5IEKiG9coVqbEj*pGZ)>`!hI2aq3#1IZ7? zi^z|}LFC8cVDb}j2>GdaG5MKz3HiBrDY;p^jQm2poZKP~CAW&h$S=ig@+)yTxlPO= zw~M*t*J2*|jhIhUH_61@oKV$ zcnz5>jw4gVYspmcIx$oz17s6%HhH`_hde=ikZdZ>B~KLRktd1s$!6k1 zA_q3SA-(EW|A@S$ej!Q}W1-9d3B>o87 z@o}=9xQuKsE+_Fv;I8lr5`PHp_yl>n_#}CT_!N1j_%wNz_zZcr_$+yjxRUHBK1X&E zpC>zuFOXft7s;;TOJq0kW%69{74kgsRq}js6?uX98hN4kI@w)ZP4*DikUhmW$X?=` zWN+~;vXA&S*;iak_7m5U{l$040pfacp!hC%k@y}tNZddU7B`YZ#P`XI#ZBZT;s@lV z;)mpA;z#7=;>YAr@e^{G_$iq!ent)#KPPj<&1A0l1(_#qA@jwp@aTHH;J5q~AeiocOph`cBUb|GIE zyOOKLZsZ#AT=EU^Jn~KPeDW>v0`hI~LUOIxom?mOAm0&tlIz7@T@;$K+xk2np zZWQ~G?~DD(P2vFZ192evp?DGbkvNF_SR71#A`T%x6)z?~6E7h@7cV6@i~0o@fNbKIFYO;P9p1zlgS3+6tbZ>l{`S4Mjj~MN**NMMjkBQP97rOK{gWa zBo7tuA`cVqCJz_yA&(I6C65%RlShg7kw=R&$j0JK@)+@c@>p>ed7StF*+iU89xu)z zPY@p@n~HPE6UBMtN#cC6nfMTSvbcaeMSPfSE-oZnh>OTm#Yf1N;-h3MaWR=CE+Jcs zOUX9kV`N+Lak8DbjBGD1Cp(BM$kW6p$kW9q$uq>K$TP*K$+N^~$g{;~$#cY&WJmEi zvXl5c*;#yn>>|EMb`@VDyNNH8=Zde8=ZUY9=ZmYz3&hvR3&q#T?&4~)hq#99DZWAW z65k|yi*J#A#J9=5;##twxQ^^EzC#WW*OLRqcgc&y_sBuw26C{tksKnvPhKo;A}C)yO#G3=FQ~b7cafFi zPb7Yd+~xjEjuw9*tHs^q81YvUzt`y2{f)dr+(TX|{!U&c{y|2 zRIxTWO{_!SD%K@$6YG(;i}lGn#0KP@VngyS@c{B}@j&t(@gVYE@nCYgcnEo)*od4V z9!ky>4uFxmY}zTq2%AE)|=TkBKeF$Hi00WnxQmx!8(aA!d_Dy*Pa~fbPbZ%j&mdnA&m>fL4Psw%qu7spU+hnA5(khUhy%$F#f!*~#6jf8;$ZRw> zA0=Cfi^(i;3E5g)O12RnBio9PlkLQ1WP5Qr*+E=Eo+ds)o-RH~o*_O(o+&;}o+Um* zo-IC0o+GX#JBrVdoy6zK&f*JX7x6{1tN0SxO?;U=SA2y$Pkfa;UtC3AAihRkD85d1 z7gv)##5H73@eQ(<_$Jv~e2eTOzD@QO*OL9jb!30>9ddxUo*XE?OI{?tM-CD-C za00^^!kZDM=4TJL_!gI(n}cwoC1>Zl-`$zSWUFH`!ZiF^dDJk)!`7WD#4Kl;hvnP~ zWMZ9I<#4y!Z6RC!?J!!9Yb)MiE9MsxcRJYCkaL%n%FZpVMtnEoTG@HA+`OEk>{ta- z?mSNted1FT8m1M_ag|5n(NKVNvu~yxWFco15 z;#qE8#O}2`5XfH1Y$y%oT-F>9%Xtt;%`SI8Ei~6MhU1sY%aJh;$QWLflV4b5zvwjI z%7KN5A9CdoTO$_$>BuOKje;IlF{^qZV$^`2J$IX36sP4r0%p40Dwq9e$dE(26|aio`}|+Z*{L zkUZSpw5ME&3akEUhF16)hSs=e5vC3wTVTDh(&C(K*Gtb?k(}Z7y9Cd>Ft-fh3$8?N zSsvmSEzZv=uv%Vn=|$PLotItlA`4$(Xz%Z<2s3hu@{1~C_N!Z~z*=Hy)LQx)Qc`n@ zMp#2$=Xw^dW^#pXWewxe_CpVExFT-ndJ|zN_g$XxH&vy$%yS*G`V)(BvOWmz2~ENi3Bvfb=`pH*a8o1jcreTm!L2Qar@ zVom$d7cQ~FAH_3`9|xJG&?kZHo&Gdlv=aO*$h7|Y9C96F>uvV1)xNNDt~s{W7N2D+ zZ3R+timlX_OpnH_iC=lxez48M_K)pAEv!+UQ!t`cJ1hG&QZkeRegoDNJ6Qg=NJ!5q zEiQCNvhM=f_P>YH@{wsR*kM@)_uFGTeU|MQKLFVMO6^$tqhecsmlev1Rue?I1<1^)s>m(Nav#~rQOx46Q*K2-9=3E3#YJkHBQQj6C~@*K}cF6~bBw({c-W z5UlNCYu7R4Bg+mxb%FH!LaCmU!QSusTFZ4x0}rdBA&_cSAU?n{Tn)g14#=?e53*9Z zQTHAktk~8*1aV4vo*iczS$R8aS^A+K_Axk&sK~Qc9uCyB6G(PWg?r17aJfjZ{r^Zq zepa>nO|qj5MLKRC4Wt&0bbD`Oi}QyUSr;GU))*eEux1_$xZOHxIu6Rn$BCAiOXz<@G3E#3gIUUbECHJv~*eM#5@}-w4w@23ayeXC^f&N)LvR^=EN#o zL)v(`A1!R_6vaMe=lph1T7I-V&pyxXnFZJ{26bQ-%bn)3tV68+)1i#~@{-)b65I3{ zF0(vVQEG4DnNB6K>?(VuXF0|2Hkr<*@+zXXy>p<9{202g)H=PRV@a%nJ=O_K&9Bb3 zlAT>vwckV+ux38lt_||LA|XA$THEXfWl}EpT(0eQDil5sOv@irlx3ZGzRNSXALP3L zOt*8I+m|m4WbNw?rIwbvoF0lTy(i*~s$ivFaawL~Fs)jv_3^NrzCikjyo#9nME5fl z*pSfn+x~&9yg zggDJ&+d{F2y@C<|pWqmd;!vrrV?rFYVisFQ8IVzF=RkK3oP!YL!O?K6BG!esP(deZeS(G9F_aEUg^xDiq6 z$ee2XsnYR?(?;SKSq(S2B38o$L@6WP*zIPQXz%nbF3}w&Cb~r1TPL|hcT}J3LN`#G z!qE1ksSNE6o5s*udn>}^k(Pg(i!A$gL}?@ObF0>tJ6y6Az0;CM;mXF^ewT;sGZsCkTV=jtTjL?cw!#9$nJ80{7jsoV9I};N7_yaL6tZpO5!kk2 z@uMy;R#2E0v89=V9wS52O}l7ua>-3y4#S zvh5`JqLnGi%`LML&PzZ>QEqW{PR#ONcE#L}8^3}u6=!$bCtp?E3h^o{f^>whxzadZ z;`$6>T2UTPtgD%B`|uis=|%Y%UD>DW4VU45miSGCsYN4l?cny7OLo6e{I*LjbjfR7 zT;$?)E-rS%gm(}pyYu;aL@7AoppJJfME@Xs4`EtSX|6kGZ1AuKZ}hOfdf&tPY7>xJ zRO*H(A26ddYEAwSNVg1LhgmTkxvfh-wqh1rWuE{kMKL=te9F*X{bw$8w;Vo4m|D$S zESnLh6^+etr=%}{TE*G1QTXujJ=tQ}#o5*FY`fLN>ibe~hyAZSEN2^#UhMmMyUQx% z-IA|8tlT$(tKnM@%lQtl3m{xSxB=bw-i5p%+7Ysq-{~D=`5$0^0pcq7F-TB}T}VjP zDE22?Td&&s?`O-i9zgsH;tbatS(ddMv~f>Kh3QvimgzD~>si(w#A#97RI~lzcMq%a z4-b2*_X3&G?3_`tSg!fcxZQn(zq~7B&VO^|Tz44W=V8?*4R;&FM+t}k=~2AFZu2z) z*(Q>q49lx@nJIBvZYqd&=epLUF|Vj_M2YRo>CEF@unZtIio-rKGMP~|!d`4m538;g zkP*ejbzYg})sEBFs}rXcuIo9%9ct^vX@%>@X@whr=~24`GBtFWHY{|X$^%@c(J~JV zWc3_G;gf1Qm@7hV#Y2KjTd|Q726b*5he9=@#ny8ye3)C;65M6#;jT13E3T#^yxbAt zND5V1y+?VuyrZGaD0V8`S+h=ROji~al)KW$z!^~tOA9J(NttQdv1Bn0$FdJ9LP$Z0;NS`Meg|9+{5<2 z79LjYRH8iFYG~`;Px=g)~J6uDJ8h7#N=ok9t2 zmCi^=jq)7P1u>2>xIT4nRadcsS0dfO6zm;n+PMhbRhPS0e;$;E3^%YmpDR^i=d@AW z1uB_aW+%i81KDY|yNVVRxjP3vlv&^o@jV0CakZC<78SUny_H$yiuMU)Mf*aT+=*Ro zzmP4zzg&X5TGplkupL;<;6RWERvW@!6lA)(2E}Pr4G!qe97E!?+>1f$7Pl8%;$eHs zrGPatR=`fW%)5xb+!wY64fU`(hk4izlI>yF#n>lZyJOY1g&e8UH5&(MmsjaJFHftD zwbk&s!>f<_&m#_;c#qwMXMrnL$u2JRuttm&+>6GM0H>dWs%ifY;iv8 z!Y9}+)QD0C#I}D#4aK9g-7OIunv+vX^6csYLpp?R?6ZYD1ej==ossVRitK@lYjAcf%D`Pf{84KVHR5gMh#w%P|&QRDV{7RSYY*k$a z){N#9q2*<6SGn5dyK{=YQP(gZrCya>Y`3{P zA#5Qk-UVhx^UHIhh3=lj-63b8+IwKU2;>9zDl=Bb!qZ{YRURuVxAxozVnaCK+Q4B3 z*MxwXK&@y&F-C-?F?UA0-(?qO#pp%_^t>oN5 zR&t(KrD=X3+rmQ>Heu^62xKK6_Hyej3}ovqg4{_vR_(?SkA!UPc{F4zzc_BU6EBI| zoe!3VZ0kSfJ(l%99x3)$*l9=EH1Mcl6bCqlOMpM=wGP~l2H1#yVsMmkUXOm|{_ z2Er)9-t}h@rXkF>O|JB?3ytU8Dy30gM?4RuqMWgsFY-YiVm>t8uU>0CI z%oZr6ywn=Fm7z7`ON6QArR8?8`U-JIxlJCsKHV0lo%6N_bZ5P<DeH8`)L#P0A#JnU_$;bFa)3|Oojj&H+X2|wgtO?h&{1Tir?M2n{378j&wLwB{B-BEQthVh`N1cQe ztEDbdYO{>3W=ZvsloBhjS6v@rDnffN8Ys4Xt09ZndwKwq%dNDOtwML2?#S{75-jYQ!ot^Pj25m z(Zkk1$;0;DW*)Zho(y1n)_bQ|nD35r%@Lv_+`a!6h%qr$5#=4VQ(YG3*|A1T#A!I; zyBFWe!(LyO!H*1D12)OPaY7p>gYAE9wU+Cnb{yC+WlH?py1@`b!*7+TwR2}s@ zAx^2xwf(WPCFfVTPU?a1JNf4>GOj1yGtR z3S0=JV!L+4=#Ds(*Q>6#dxUJg)iW?JDtd)%`Mu%vD%{0zYxfCcd40Xyo6s+i<@JYZ z+IrUCwkr(?Cs>JrNT^+v@R-&`NXk$WN(}NP;ty&K_9ghF)(}rVs&z5gz}DaIS*=T0 z%x+a#Q!b6u_Up??|IF6qaauEng6II9frbULJbd!-BHhJEv3rrj!wFUbLupJ2xe~5G zZpfC8Sxa97pFPMACs>IQNT^peyu1`o+u>oh{8m{VkXnG$`tj7l)>+kdw8XPm3CZo+ zxa5&Yt`jfq-Y)E|32C-1oa=0I49~BW=fz^K!8pH%ldKeGJ2?;MpFk-MCs>In65O;K zZqeqJ*^#u&7jY>_C=V5h#;gbi2&@)G+-VvIv!E8VqV zcI+901hx%Rdu|jr))(=Qn_S_GAc3=gR|Z8iLwHqC#7_`jjTBBS1~2*=UnqFgWn8!r zw|;HBkY2-e@j||d*ZV?Phc~%zNJz0xzY!_vRrWB6?c?JES>8=v?ya8?$ntK6(yH{} z$t@n1GZ9Fw$}6{n{3OM8?4OJ{qbjdD%BD<-)7F{_*0fyznVA+&uoAZ-p$!11TJsg% zo0w#6o{pqUmU8`jU%W_GtJW@QMkuLuE0;7gw3gL!f2au7vZPs|B&=mg55(7U@7L^5 zkyfo;(wuk_8tsxEj3;HaZsn5ZhAOg(=Y@)(B1@VdPqK7jU%Rb)vEkW`Pa9>;Uv zO%MMg)ygi6ukMfiixLX@{(2-aRbBRI;_6o8;>3dLxFw0H>bs>{J=Dy{5|gaP$F(j> zh2HjM|46m6%j2v2)8LAPg8ub9k(jF2^JL=cR^wBN1@(HKPE6J7c?PMr-}$b5HeQ|I z?#fV-Hu_v>E!*Prp(5Jc3!x-!>&5t5Zufa9R7CsT%kdZ-vv;QE!J=w3^n2 z3#qHth11km?}S!#owYt(NWJxLD9v}*d!aPnUmL=eSt~Y%3#rH652g7o+Z0OkefEJ* z3w;DW+%L_x@e$HopZQ(u<4_^rXP<=A)MuZDSG1Zw3l~zKeI8CzpKT7U==$u7a3S^C zmQb4Sv#p^t-)CQjE3;O76)vPc+ZIameYQQ6=KJhxq-9j$?&Vmw_k0tl)%A%0%;9ve?i2 zCtAs05);eZtJuANqLutLA+Z(f{B8e4E4e2zk#+vQf1;KA1Bw2%u-M*&6f5&5QZlN7 zNAv!Q({leN{hqilPRmWowKFvC!s2l{4HqIvs^gP1TBxyKnvIi_!)X`-*tJ;7erYyv zPDPsEgvJzUp<;eWk-lG=Z6YI_rcGq-mu8!&iL{z(vOCS!LPC0#f4-$QlnMEZ@;Y$s zs)WZa>LRI@PjYW@y@V9&tNKVuM;Sho(IAlJHS}`3@d1G>??6fyzz0Ei8WYdRx(9I% zW@dh6iCy9zLg}H6MuDuFL%rN44hv*?heMfF#YNeu#zx{tFt-R-Hqem}Hd(9|90jJ? z^PqNxb~M+-Ll>NjYwR;^#bbb)RuWT(?g9B@LkaHD)#H%ho-O6%Vv~4&rF$g&_)vnY z;e=3vtDz|p&~*3Qi@oP3!m80GO;7UKnl)|avpH>ga-7x=r})yEIBo8;c?I4gPAh#X z=w2Rf5xDofWjMh~wDJjl_B0C#uC?LJ#47S+?rohi+Xb_rxn=<4NOUbjG&cP@m+k1j8Cw;#`AW_4-4-CRE( z!uG05ZF?8EEdS8Xg@No-oQAmEf;~AE|-(5gF?3a!7#UD8lqhPgwMswEpaoD zmq4~9+%~ahTpFjlrxKL4zPmh-+?v2JW%2PKyzQ<5RU@ncm^-uPy1OT~jT{(V z$@?wVb7)9B!AfApA)a8{!n8;{!Rj0lN~p3r3XtG8Vg)b@i!)0!xZz@DM(&qpn;M0* z`k`{g!`(Ar*sBwhN8{6oiTC|#u(qM!61HSpFGX6ds_=w1KC#v%_J>-?FY}68yUGLE zHn4l!D+!*b!c*IUEgut=fo=PEge|ab8&iR9+wsYAJhl)@v6+-H!8&{lYi!82jVnU7 zZCn|$ZR0A~USDz4&#zydkYd}o1}W|pN3Di&5cV^y;qK^O8>emWx;U-y^>NzPZU9-6 z=|-uv*!pgKAgkvls5Z8uTVIwmAu-9Szd2aPbPHrHD=l^{n;569J}FKsJULEl%M{RB zR$6SD3c0P9Q`oNC>dZJT z_kNIVwk^(r*yak?<_BQ5xq=Ot9Zs#2`RS9qHqd6vUt)vA;ro(iWIy~8xi9;hnpNBTmF)e zZM#e3c6TiwgYg<{eOvwUc(!{ka2bqlvur-gxICO-8(0xeuq`|hN^qNaGL(RW18!V| z6ReJ>k)Rjh3Op0C%I=+wYjICt@P@Ut@s+cI6Eii-hnq@^tf}G zjc?x!C)l*oTk!<0@-`B%FWD-wT({2JgcMt8U1%lu65k0YSVPw%0S&cUT!D8(w*2>C zx0PIM#+BIMt3ZlN*ccS?kFUP(E79|-n|ujA{*7usNJz0B`4B01xBYWAAH`|?_i>z7 z_>(xTk)H;12h-2uv~@p^)7IS_r>*;isONOH#A)kpjnmfsGEQ6ftAK91+v2o!x5sJg zejTT+`;Cap0y~U+8>i)d2in_$M|a&!-1i|{-8(|I%6Eor>;C}T{uDg=`y&#pdvQ%< zo7)wqRrgbzw)W2;w;pqi`z2({-yOHB?bnd4y5B;!@_S&mM$a_;9!{|K{}E2GRrZDw z+-LdEP=ed-{t72p9e)Q27z*2q+!s!;N|W+@J1S$Y;gN8HwY)|+!B$BQ67;xKN;ttb zn;K5ARnkHUuIcHa1lRP8aDvs5i3EFh^w3mIlLfvk-!gQ8VdQL8vD7k~MzHLcp#5+9#$6Ua)o z)r#fWuAX*rT5kKGtku)OXYxt5(|o4e7f%mlE1nS)b=963r{$g%l(lNlmiTb~If3kT zbqr+db%N}z(DV77&{9yggBSE_7H{}1)mqPZR>m(hce4A zaRn|2Cs>IKk%0R27)N&q=g-hX|2@Jf?)cCXDfk$$44?4p6)xnC8NEX({8NBF;S^U< z-%v$*FtA^^kgKRaQqVr!S+<@W5Xjm-5W=y5e>`vzkXeNX|5~+iBkw^W+t7J%+%cWrZs$FFdY}wznyXx^ETsX;U zz$0*>B)1X#fnGStO64L6uQPa15MMbE*z)t^c2(e+IiK&^QUKSga?dBLrwS8Ntd5c4 z6j#frgcK`-NA7$*>M`873Z+;XJbf2WarKlYq*xjJL7%lR=AT%^m)3Z@_Ljr7tNcON z^&KAB3@2GFxTS?zTa^kX5GwzXYGv^~0|{k$AAj^eQmt%tVyY$)#{47I%8uPHmGxfn zk5nsrB~pV|#e!EQCRwSgk(7Zy)6i3S*TiYL<4FHx-L-LA?sWlO$6p_(<=y~hR>hx- zyAe*W!coO_@c2Mh_9ib^(S$&jcQcexWk(OU;w^Dn?nJO=Rp^ndN#O)5F*%;V3+gH1 z1S>HW37J)6^YB!VdthxET+6xA&hIF3D^gPRCmgpSP9HrS-vD5r@!M_P(dEHozIV{U zW4?F7X`{>enD1S-YIXK-{EahKz1xabXXlhv;!6SGdtC1DybiPm4~tqPtC z%o?7T{rWG!t}XUXzX+%;#+O7?WqjEaU-t&S0>;~7DX${Mx5d25TNS((m^HjETU)IB zYS`N1&R}Z*w#D%cv53!=zv-Fha^C`jwz!nHk)pOZuk}_1>jJZecVx81m0u6Lwphd7 z1=JSfdm^ebZt&!pbt4#WixqeuDZVY{P2Q^DgTSoeL)qG5_kKr{(#ypOEHSf{s#k zKl>!>D%SQ(u;z$h&E4^|U<{DCC* za;@ilWA-AE`-;wn+G|1*&ms`iIDxZNdJ-|-ekzp z9ijUmdBd9y`CfPOKOejak?+0XM=5ac4X@dxh&L&6&}e>?Lida}eu?p>M!whK{IEst z6_WlX#+x8HMqBxTyjhZ?`;#BXn0k1e zH)V44Tc&@>Ti&$EvHF+1=}n#-O&zoI2cK?!hy-Aj%rSva(&zou4Uy1ZDdCQw^ zIr=TrzvL}%#^qT3OWyS6U5@Twrnh<1F8ht`^$oM^&AS}kpZt$&Z{p?XW&hLGn|aw^ zi{HOY5pVY8pnsV+y!n^!btgYa-QW#BiZ=(dFHHY3Me2KR1ml;y<;}!=uRHmL8U}Cp zVZGUy{X%~KGI6{anPaq-UnOr^=IH+9$MNQ6j$Zb|coQ?n=wBv^H#hVBY`p$u-ty*W z_TTdRmwC&ZqdEF5>0jn8Z=UAZ{mZ=R&DI>`gn zo4nayhu^=HgyI=*1cS;)v+Qnf~I)=*3z7;;87w+5Y0_ z=*2ny;;1(!(TmUfi*utFH~5S5q8B&%i}RxwH~EVTq8B&&iwmO{xA=>T zq8GRNi;JTdxA}`pyhZOyoY%n<_8BHK+Id~le4D%X@ZSBp_cUj}UdN1|ri=Gga^)uk>DaGhapWdZhPq zxOwUIMsH^B;qu_9*A=~4#D|ZpSk^p7>h(l#F6;j0`;=ZU^d_SA9v-PV{X3hdLcLz+O|v=V{?!+++nHG^P0C)E^XC2N zZ?f>Zo0%-6TX)&Pz24?8$^PwiHt&1RLrvAZj%L2~YS!U(GVi;gL%N%*1zr!6*Csu$ zd&%qa-fORKd0)dE(!GK~UeEFujPm-GzhFXny~->M>2At+eaic0x=gs?EqPta%w=Z2 zf#`K7Z%W>7ra8Q>6hA?CnLWenM)4C2?P8Mix={RN-WGd9OzJVU*rPp)fCm1gCns~j&t5tuQK-}vx z@e>Ug=>LP)VZ2s<#yq51d3xM9-uM^q{$G+zW+_Rbxbfn8y((_pxN+n!UOe-DT=};^ ztQVCihRW=Tco9_=PsER?vU(yxM3v1G3Gb`i@~VKB*S3({@_GN3$on&K<0Q#&|CQ0P z>zW@+uPlsN5KFJ^Va&o<7QwP8mc_6vj%5ifOJZ3H%hFhu!Llrt<*+P|Wd$rNVp$2x z%2-yxvMQF+}sQ=pq_TeTdNv(3D|W77-Ad@z8JEuc zW5;Vz>mB{`j(&rq-)MY#tKBAq_QOrkZ8k1Lqimd?SgK%app=>gm`Nf$k`D z$Dlh7-3!pY2;EE2y$sze(7g)XYtX$8-5b!o3Ec_kPC|DIy3^2|f$l7HZ$bAqbpH$I zLXWMZ-U(-8A6-Yi3*CF+oU-os!&z(HA3*mZbRQXK?h5$helSi?4gDfgDXv^`>%ubZpz~vyu0)9;+cEOG0%gRhK>z#cOSU;CZ4(T93fr;=n@)d z?oXSmWd415|1(g@(RMuXGMJy@So*U^5zPo<^|qRoXX`gU#$);yWv=j)FR>qEz{T+rn<&OEMY0X=3&lYulCprlc|ENt+1mRtmb((3OF%EOh0dD-T@- z=qf^23A)PARe`RmaTOwO-)hi31l_~XJpx^I=xRV$6S`W^)rPJPbakPtXI#a|+qXV+ z4WMfXT_flkL)QelrqDHmt~qoqplbR;P5cW(Vx<{qK>|9Z*WJKc@zoxXd2 z@!~~w`445f{)aN%{zIAW_saO^Vx~U+t9$jCA6lOtG0T{9?>I@!9sStl5_{$RvI%0g zMbDUJ{p$d+%PH&Yb+3$RY5$tPSzqjSH|vX&Bv!lkrsdX4*;sk@F=eZIf8I9r>Sx*| zzPwWI1@|?!n)l~F7htS;<=>U|t|?mIJBaFMym=Zq@cxxNC3b&f&GX3q@o8>(Wt{S? z#vo(O6Up|mY$D0QyQ~uQ$-%}}SFCjmJ;b;gk=;<^YTkEY?{5qnJu(l34W}Xjj4a%1osWBSkD^Q!29!s=@WjN zOb^`_&pFsJ4tA`A9p_-99PD^w8?tto;9w^@*hvm{vV)!CV5b_}h_%Bs2Rq%t&Tz0Z z9qcRzJKI?E>^s;m<~Z274tAb{o$p{5IM{{8ny35iaovm${@5OCoLg#qQ|?z9Z=U!E z?Yzptu6D3%9PC;LyUxL`H`aWo0k-odruv;ALRtLMy!ESf3JB)3~+F_@I z-Q{3+JJ>xAcCUloXKX9h4*MPK0S9}~!5(t3haKz@V_UO!IO<@JIoRV4_5}y~qJw?O z*f!oD98X>|zHJz99iyHwww?C}#-5W7_LPG??O@M1*s~7yEo0kYgZixle^c&+JW9{~>gZ<9I ze(zv^aIil**q@9w-$4Z9&(99_7YF;RgFWwHe{--GjD3Q&!$k*s$-!QBuvZ-HRR?>` z*eAU|xF6jx{wdaOHy!LP2YcJW-f^&Z9c&77&9Kw`cJucp<=S3K=u$zK8oD&lrG+jX zbm^hX09{7tGC`Lax-8ITg)SR(*`dn;T~6q7L6;l4JkaHZE+2IHp(_AgLFfuWR~Wh? z&=n2m)`wn$E*8#O*R_j7S0bEK)?G53wboqK3kTcM*q%yUrFXY- zu&s^lbw94(AN(swiDHgEZH()E-O|pGtHQ-?|&!GJQWezL%ioC>?aT&H)RKSe`b&JpKiFfZ^cQHFVsI_ zyqSq6X8y~>#cIbVp?eCtPS8CKU1#XJK-U$zZqRjyu7`2YSldI{2YW)-%eX<2a=by%4K{9g{7!Tb9 za&2Osf?Og}<{yhGt+S7%q9&U>eH9!-TXGqe%fm~hMk~T=D}$9-t_m-e3|5EN zRt9UZT#My8EZ2*a8Q_AxXL{hhC4bu~=b_L4=aL(OlBW0i=Xm#y>&;Twb#DC6B{u~n z^LuOX&$rDw?=6L0=jQ)ha!XLsw5Gqmn)l**e__|R^*@!`CZ%MCzL9<7B3u1@uTW{Mrhn45B{8Hq6d+kfT<8bRKudlHDTI2!{^BXLG5xK~YX?^bgDr#{A zbzanx2#zn0GHHl-6 z!J^gz8CRst;v2I!j1S%Oqzq|5>wQ(9|HB}(Q1 zj;WM*sYS{xz`lIo(M1~3G8Zt=X+_J7z!9=YCsO7Fjw!8Lr57bL0{dCsy9%LRQ^*kL z2gJ-JN@fp^sg#z=EmGzWjv(`hlo^C0$h;zD4&ewgpGcWS*q6a}vRWy>NSQ}CLd*gp zWhUVWvY<$rOE`ioBvNJ*jvxz*l=*~XN~<S9<7vkrA5k|!ZG71ty4y%%qko~ zmK7=U3P+ITj0AJ2mWQr_abOPBiqKUu&OG-LvmVNMXl3ZC80Q~h23Pf!^Tn#rJ#1Xm z341#$89pLX=4Osr7iHbmMat~VF{Ki-29`BN%1q8NV=8N}g=KA#GV629n3F<}Tk43E zd7mT5x*}!f=a^Eddp#`ci1N%)A=$aY__M2wVH8&3I zH!YxRX_vupEu$vsgZd#AL;iZzns_@#%U^SL&uw0AfI+60b zGiJ-0Z>#vD&%JM(s8=!9ODXvk8h;D>_l1DEo0*P zy)@Px#~o7QJNsIXa^|s9|k}DfyF@ozk-V!)rfwtnF|>wETil%x(ODdK`Rk z2_^qSQsNga|Abz9S+imu7X2&KM?{|wrnr4H$`6va(`eZ zC!F+2(HCLtQ%?G{lm0+7`R3$@SbijueAn<}EI%=_hxccXjLP-WPaW)M#=`H8eePht zFm}ZKeErc@$@Ls`Um6F#hjdOQihXo!tggLUXWNnF7m{x>VXT6_%-WIVm*HG+3q;DZe`z zvptoV>99;MQhuK@W=y5-8L-T#%SoYi&xB=WT`GBI!7{5ZCxzyj4a@8zWNSqRI*BIP$$BeZ7`EQ?}U z49nso<@a49t z*ONl~Y9%LKS+xAdF37uzldc+GPYTVunv;G=wEW($eQnkMO&N1eVE$*W^+Y}Fq#tq8 z)kVv%34=^(IO&>Bx|V49tzwW#Z6{sFN!Jza-Tt|E_aeCRt!$loPP)F6ZXnw02l3*i z@c#V!js7`;l1W3+@@-cC8ukP8ZX`NBtYu>--NZ>Z742QTNA2CrNjG=WEkt`4(@`cZ zopdWF-CDFa44_QfIO(=dx}9k6Q8<)Idnet&Np}>T#AFil({%m)(O8B|?_Z-H#qu#M zAII_uUHbPe?v3oG7Ew=P`IIh|QJ@o+Ph;6xWK!4%x;W{sPP&`uWH6KNPP&Ja?kPGs z%%qo-?(L-eh)w}B>FcEXIqCkQQ^HIJIO%~-`WexwU?zi{^k64FM09GCNg)}z9{8y| zRCF4c_b?|t+)0lRoz`R$bF|%Xf3&^-e9TCZ>1??%RE`pv-j+(t(IPY0Qi=Jj$c#Wf zCo+>Ql{1_%A~V}kS^HR#S!}7q949iXEtR@QVL2Yl30O|Va+1hwc8xZMZuiMpPQh|2 zmea7DE;2i)(F`nSVmS-T*;vjInZvG;(m&^7IS+!(qgHj6A_OC`@OB1_s*$#bj7 zQb2AKS=yExL-X7&vWzX2Ja>pJ3*=6bw0V0g+X0spNT3WHlp$D_?%O0+KSMK@HZw;t3OTKD+ckj<+kBZ&3DrzB5`t_k%i(Y2sH?WE5*=}(;Wr=n{I zdHbJyR{MUYtM#GV>vLTOSE25ozkQ)gYt83G)iL>*{lovRvw2E7STcL2lF64r$pW7D z=YKLKgC$c^$?PjBSvNwPe2vsMqUzbPl&34d6)aiNO`U3};gK$j4@M8-u;4!(C0cFQHkG6|MRu}mhC zd{Z(xmMO4IiDfF0O@lEpYs;z_KKkrLZiGWf_qz z%+?Hk8_}G3nd=b#>{sT@%Q|i>E2Ub7mNHi(!j_V6?nSim{KwCO$JXx+&{OiD6%b(l|;4!va-nbw)8T#=iRO%vV$g-^N*@HZZ$0BJDO26 zgNJe4M?`kCYi9MN>PXcM?tb=3Ll118sn1 zLy?aMF~c5hHNvtnmQAp1D)I@Cr~GTc%Di20nSxjwaC zwtuYaG;M+sg_RP@=+ah7JQcLBe|=H8{?!gk`SxK{Cp)Hc^|*t?B(kH(r|p1YXNVkNq<#Ek^!m`_ zr!EwNr{0Vo7q^-!E!E^^RS$cKy>OGFN`V=6sn zsmQ^$RMx%>%jF`6*fEv0ufTF8maDK_Epn)x=Zet%Y7LfaMGgZo*I~I{)w$Vl`H;EhxVs6HAi^x$R=2k4Xi5v}LZpU(m$Y(*!omlP?`5cJ38_PW+$AFl7 zvD_zeEQq-u%L5|EftUxeJR~v-#5|1U5s~9T%%fNy6FI?-sf*;LiOBgN z=BHSGCUOCY`8k$fh+GI_p2PA>k&En@%1HYamS2lpY{yjk(l=OsD{_e)Q_1r?EWa1I z6vX@i%O6E912KQX@@J9DLCjyU{8i)%5c52izlmH4VqOrr%9ctGxrpT@k*n>PN)Ne= z?;_WMn15h-L*#l8^Cp(JL_QB<-p2Bd$PIQ(r7zvZ@=uW) z?U+hm`U}gyMQ*ZVDtZ2c<-Z~~gP3u=yV3EYh%_^&$BWtmV#dQVzR0b1Or<>&V3`oh zL?X9=wI{|h36@DkZU<{mhGlXrQ;6IF)}9i}R9L1Kxf85C4VG!KOeb;|SbKUbGhmrf zSy1F55VH`Lg+(3)F^gbXROAs5vly1eMIHq)OJG@26K~`;e4+ z)s!+%+7=gUp7AwH<~z{-J9*^pPOR@4RhN>l*>$j<;jDpFO;N8$h*b;4s*O|~r0OD7 z52^a1BGs`0iq#OQMo2YAstHm}k!q$Z?_K*j)#g~X(52NITO!p;RHQA{T94(ut35H$ z#!0u;wN;yTNVP|*15zE4dQ?=T_Iq59<-M!5-xE&yNnKm**9obok?M?87o@r()lFC4 zyY^nx9m^iNwA!tws7TwlmmbS|S9?CDx0CLpYb(#bNcBUiKT-okMQWLWdMxiH44QVkJJRDCL%QnsmY=u)o}`nH5I98NKHp-22wMTnuXMCQ73|LtB3ub#~du@ zVmS}X`65r+c`8qgF2HgjmW!}lEb@&AXEsZaT8h*%q?RMK0;!dv-n8qeoNcbca<#~i z=Vg`gcny|ov0R7cdXXpWx+{4;kL3m|H)6R-1i@+g+aM1BBb9vAtcEtR^zAo3$yE)PAPeNp7cK)x)J zjGwPy`Km~AjQkpwuVeWJmTzKtLgXi=J{pk{o;JsnFmfv$xrPqq4dI2Sf0l6 z43=j_l5O@DmT!yv%&xogdH+8w-w`S8>9{4{m6D%>Y~I82eUV@Mhko&alqCDzhgg0j z@|;~mWhD6+%TKWU6wA*RY6~6ZN&- zUjFya62&#Y{1yG{U*Ds6Kj3&jV)+wV^Up~Ag4g;hig#YrH+K6eqxWxEUcmAqmX}0+ zYv-x#`IoW0g5^~#uZbj|GS{*E9m_wkydm;CyFIOO<|b0Nkh+c39i;9e^(Rt)A@w&> z{~+}*QgOUlnBql6+Cp(feQ$3^q_*WN+k|TnS1)deB+cA|q(_onv%XC<#7x{~wr&9L}SZ2gB z6PB4p{%Z2{=d{ltJ*|*;wmdELj5&*w&KhX5cliC+zXGnr&gP`Ei#{K;?*nJ8&*7wV zivA78&gGtrLkywtxax|9D zV)-1FW3U{H<+$)t>CI8$wbh%)V>uzbR5F+tURxPV!g4Z}Q$(J!pSx17W=zF$n#j|3 zOy$bMbS!6xylOthf~$Gznaj*Tn)6Cu2WOa8o6ZV!aOF;oJ3EjjntkSK#hnxA;L4dA zcWxj}TwjOHcb@2LrX7rleTUn>yRDoV&zDly9ZM~cQolQvS}3K+d~%DhTr85zC$|L4 zr6S3Ea?7w>E^>rvv6#O^pzKX6uv{rJWIj11<|-^#i~PgRQ@P&02FtY~L*}Sc@?3}I zdXXV>)G0Ba$8v+nkU8paR&Br;@{MAGGvZArS1o@JS1|Gou?A> zFqTI|-T*O=iVT^}PFedgERT!4X|H{J==sVESiUH7iXBtQ^Cc`_7J19W94(&;!QBmI zw0*@%zbg8+ov#x2H7s8jdB={qGPGUa!17IzQ|*{ayPm-Eq{xt20+pDjuskjDuAQgS zo@cN;D>7u}K_$<(uzW}4pC-?H_n6}(F-L>uj*5SEC!e>ymW6J!cmH$A52WN@q3blg z`hn~G@IROQNJ@sxu&A`%$5?(MGGvBDCFZACekSs7yWc47|2dXlh@54|RPsEB<<}zr z31UX}N@|MY$!i{UplU2Vx(KEBAeW#_|^|f5q~= z$msLFpf*aLzhQX+%ZpfE5*goaPi1txjO7)P2|&!NSY8vE5X8KW1u_4|@*k1OK+J!!jFZG0 zXQGmWm~pX`U-gbk0b<6Nm_#NJnG(cIh-D&?sX)xcSSAsf8pKSBWipXzK+NP=rVyDH z#7v20Dv{|x%+y$>5t$yuOp9eYkr_bD^jKyPnGwXyh-D^`nLy0USY{EK8N|$rWj2vn zK+Nn|<`7Bdwa$rUE|FwT@7!4C5ji(FZuF1olq)HDvCJnjtKFW;Cv1K!3y36hdKbj9 zkVrD8cVR4xh+GKTvnZCuL}s(wQ#lSPj%5jv*+I;bSe6o*!;YzJ_tIFF5t$RjEQ@71 zk-0$3@>o_7xyat`%JFAKEGvmzY{yjg&B|C-5xK;UspMG|%W5KXgZ6v~%ZEkg0WlxJ zvbxBnpzbxWtSNFCh*=BE+9LCUy4S(7uE=~KW<4zHi_8yVHo&r>$O0f{BP<(>Tn@HT z6D*sGTmfP>!?L-^f}rj#uxu%^5Qy0d%hn=Sg1Wa6Ss1LnEtc&>76CEaW7$DuQ4q5u zmXC@o24X&j<>MlYgP2cX`J~7aAm&q8b`n_<#C#gd<^Jm|d{!DzY?)*$vC?BFli7 zJ+SO4vMh+%3(MXj%Ym4Euj z^Hh$k24guyJ#2k&~vmz^*y62Mn6Xve4 z|4Mm!>p3Sq#z~KTuwEb96URB1h;lA5J}6P*e*5^ZO#3MFB1~{DG10liBq>oj_EyX6 zeJG1^4^_HS%z>PJN!(@q8<^L(#6p2veY^c*KW*GbP4T`hJGFnuPtpKd)>I$ugW z^q>;T9=kwFJ#0$F-kXB;D0|ex@O6okBvwye6kht-#A^S=;kEKR+e^Z0D~qM!rIN+6 z@LI`Yd3deFUg4xyie4Yr+d46Oukv}l3d_|Z9|=YS|7z;^(9wL2$m+IKp4DC}vIdar zMAigyy~tWXJ}9+$S<2IYkvXD7qNUvWXLa@DQkZj%U7^`Rpd^)*C}g%4a?WDd_!ad z&_CZ48S)!wN}eaMJc;Egks-fFmMsH#HHkSVr8S)!wO5NYV@?DW3 zzk#O2d=Ja_MTYzaniBH^EI$-^0JQu^Sbi+>Ac*-1mY<3|1Y&-M<>w*~gP31nc~0aJ z5c5kczY^Kd9z({59(#U`s`>v@w73#Y_NAEDT9oz1!!kaW z39w9vWg;vSi)?Xk9PvLv&9{bv_P0icBvPW~gGwkZmsCo%GNsJE60GNe*YA_*^{_HZ zt}7*r6uMNdbEed#wdPd1Qr4VWm&%&c=u(N97Rz*jgr64aol9hp5--Q~wr8 z5V4*jXe*^2Go>Q5WIHU|W7$FE<6!L_v3wNE$3#96tUY#XS)VMAi+(b;_GWF5ZeR1e z080B#lTr)qx#7H7+O%hNria%`Z=DfdTU&W%c08R(P#sF+04rvY0FKsh|bJ zem2hwBp40m2RcF@UV!DoK!OYw1v)|oi?Li1NRYwOKu5@68J5cf2{Kp_=m;6C#Bx<2 zK?bV>9U+4?Sgs8u$Y5QdBV@21%jW|LGT0F42pMd|a#J8d2AcyNA%iU;ht*#PXELt{~=VEYDzhR%AD@_P4Nn8_WNR>~61JIYNI& zWDi>^SD@a-@;xly$MOS_Jwcuy>e4!&`AAnvy+78a74H*Ky-a@oof31#8ukePQ_;PH z+Ju##1rm%lp9ea^X!8Y@=K={b_%hHDGWZJ1uLB7(_$JU1GWZtD?*a)j_&(4PGWY?@ z9|H+8_$km4GWZ$GUjhj-_%+ZGGB}UrZ-E3ETnKc83@&1MDUcw8%YlxN!4;8x%y{6B z1ZMQ`M+fu7iE@wls+8ypMv!ZP1UX+1bcCFL$MTOrf(&j1Izk3FvAh*XkiqRhN66p~ zmUjaQGWavl5iP=1#Oj$#PQi8B@~SV|6H5UP=x!CB1v5E+wl=$-$;%a7N)D z6IiWX1IwBshk%&1u&ga|D2Q1H%Z4I{ftZc3Y%Fp(h}i_orXojxn9Z>7RM|W2bU`xU0yCwp2a^yJ6W~m&&&adWf84uYI9> ze#M%%r6-oXL{0`Vdt=#0v+NG!Szjmd}Ws4q^_%aWBF_# zK?ctSIzk3xupApmkiob>N5~)w%khB(8B7RtgbXHPIVq4JgUNx8kiirzrv?&aFfGs# zGMJ9#j6i}6W(GP!2D3!YGUEY=J3G)3;?4;qh&wmX5#r7ZB#1jd&=KM;2qcKRFwha= zE(#=wyExDh;w}j!h`Th<5#lZrIXn1#2z#x0IhHH1T#4l>k#mAP!+wsf4y1V%;d5+F zpd+-@S}fNE5@fJG&=E3t9?K1Z1Q~1$bc75xVYxYwAcHM|j*!7tEVl&`WUxKZ5i;0; z<<3BY40Z)NLI%6B+!IKU!QMbe$Y39q`vVCwI1uOv85|Tj7k-W%3Uq|HhXZL|MHoGf z1Uf?8qk#l*j|DnH+~a`+abE~@gt#vT62yHe&=KOk97quNl|V;``>M!!!RJHR&#~9A zd>zX-uzXYGd^=C&8~7)%JSlR49aFi!aSF@RA{W{*l`A11o3@sT}^)uS+Z554uv~{isVT-cO=d1^GR2?>sMhb)bVIcjX!8-$bv`w3WpLk!yjx zC~{pOA2>E#61`s2*0%sJi+tXeO1oYWxxq;D7kbywpN-0@;Z-TM(Uj2dQmUn{NvTby zl(|D$$onho{rRn)D#knhH)*YPUYF9FO={cwpqa4)#xD`?9!yNygh?{r+~+|2XM?MQ?|h#7XYeFN)?J z*Gb0JmU*zui)B76^J7^6%Ys-I!m==yMX)T2Wic#^V_5>rl311sFO_r1 z(&4o=-j%_!Ys6Mk^AjD zl^)X)%T`#n#;t!M( zF9h*}Bl5M9f2`-To^jHHob+HPJwfz~THe;@+C(fTVL2JgDOgU$avGM?v7CYBOe|+% zIUCD4SkA?A9+va5T!7_5EEi$97|SJCF2!;gmdmkRf#oVJS7W&b%S|F*3dSY>6V4iw zHj8>WP!Ig1-!A%sN~ihj+s_h7ktm%;n5$=&a{`MiFpoOK+NQm;Ff zIxeN&h+XP|d&mn?;!TGVuSTP(lR<&@Aq|2>vJVEH4K zKVkVZmcL;6E0*W6{0++sSYE{Pk}kuHqnDlZ713|QG5V^LzNTwsjJ}TL?^ynUC%`fxmWi-T zjAarmlVX_+%j8(5z%nJ4sjy6~%P?bf8Yi7r^#ANJTIo~iuuP9-1}rmTnF-6xSZ2X8 zE0)=?%#LLaU7DU^J(rdf%UoFI#xjq{cR;Vpi)B76^J7^6%Ys-I!m==yMX)T2Wic#^ z>r&};C9o`sWhpF6i+tDabxNLPuq=yZIV{VId=KPV0n3V5R>HEf$oI88Cxl*usp6!o ziv9q`uI8j468#~J{jigMMD#~6c6BFRL-fZmc1iEE|&GM ztdC^_k)MG)8)DfA%f?tX5&5~DXPD!`rcSzSuCH!atxMZu^fkG6qe($oPgy-EGOww+21E)IR(q9SWd%oI+ioAoQdTuk>A++ zyK){r8_PLZ&c$+`$ZtWO^RZljQt3DweNd`8t+w=u#Pz-_)hDADs|+%==zXtY=Y`m?yD3h2?21 z&*)Ow?q{)l3(L2${2!L@VEL{tm2LDMmhWTv0hS+%Tn75mM_7K0k^%N#7Cut9=f!IrJ>^E|z~{`4^UdWBCu3|LRidXK_-Rr%gjzNs)1}j3@FuX!-b9 zCcrWwmWi-TjAasCD(#sR%Vbz47x|mr^2)xH0?U-TRBDt8%hbA5@=SweT9Fq(-P2*2 zUYAPUGhmq!%S^gdS}8M@Swvn0t&~;dB_Ok5nO&Dkd*;A0CziQ%skCQqk(WW;^N73x zWL_-u=~8K>{8$#ivY;-NRw^X&s$F*_&%#(1!Lq2xYxde_gnqsk!?L(8l^T`6vZOAR zJWF9&TI6-R?#ebQgJoG=Ds?Z1WqB+s=u)XsMJy|c{2jDXWh|@cQfZ~CSXR@eQul|j zd|2ckcHNa;_Xw8Nb*a?729`B-spMG;%i1Du*mYO(tb=7;EbEE93D#a8%LcksdPqYo z8|hMMrN&q`(WR1SQ!JZ_ycV2)`m>rSc{azgg)WsmTVmNtTVvS<%eGjy6M5Zk zPo?hdvFxBrWgB(G@=;wXc|L~a<05|tb$ONfLpFobla-=SmtvL$I(YjP>^sLCg>>4R+e-6tr zBLB8yDr+B$#$sp1Qc@WD( zSRTgm2$n~&Jci|QEMLI#MJ!*!@?~8rqvI=BzKZ2*SiX+s8(6-H9y#_f#o?Yzr^w@EWgI`8!W%or7}i;hvoNJ{($9=SpJ0N&shF~<*!(t$MQEUFJO65 zmtn@yOHTT-==k<=w9==pV0jhGYgk^#@^>u%!14x`H?h2hCL z+PzN6GbNU(L?!|;Q)8J1%d}Xg6Peh~)B3fA^hjk8l_Wx}j7Vh?mDG;4CUnHgjAa%q zvtpSI%j{U@z%nP6xv;*9vM`oKuq=vYF)WK?Spv(F zSe6o*+}`fWd3$Lr%V1d+%W_zj$Fc&J6|tR8smvL=?bu&k|1WxLnGvM!eOu&ggKrM=yiW3C2RHWZo4j;YkW5tfayY=UJ|k*PtR z&9H2aWeY4@icDkYIXUzgtQD56MW(f5D%+?HmTj?Yhh=+_=|G+xu#^4I)?PcvLBZHu^fQqKrElZauAk-MP|0!Q`wJ(U^x`aVOS2was-wmu^ffvXe^%< znFX}`b6AeSax9kPu#CcTJeCu%oQUNlk)+R0#&QalQ?Zhk} zks&=<$@3tVhp;@12Iu&#?R)%P&NdK7S6&FR}az%dfHg2Fq`;{0__SvHU?K>GMBg`4g5uWBCh~ zzhZeF%iplPfaOIjFJXBZ%PS(u9(NVXYgk^#@^>u%!14x`H?h2hN{B8 z#qv)q{}LH8GAMcejpaXB{)=Ut)aH55ke;mM85hfVSjNXPfyf;8ah-C8k`T*8SSH3Y z36@E*OonB0kvZ*FQqDV4V3|^6E<2{uLsDUxT3@>oGYyt$Mdk*1ro%G5$UJsTrPpP^ zG9#9mu*{5Q7A&)3nN4I~yOoq)mmSL-BJC$TKgN`9v15 zV=C>LAIkz*7R0g;mW8n_BC;T;dr>TlVObo@5?GeRvXsa|cHNcHrZkpiuq=yZIV{U# zSpmz6SXL5Q*ltf{KdOvn6)dY_Sq;mFuzVQHN3g7pWet%ogEIVM?5z9xh zd`u+i^N(Zs1eQ-?`4pC&uzVWJ&RBNAvMZL|uxpGAEPG?w2g|-#_QSG2 zmIJUHC^F;>MLCmt2FpQM4#skb$dHji$#W={!>}BVJz2?fB$lJF9F66(B8%F` zb;=pab6AeSax9kPu#CcTJeCu%oG7xG-JZ%B$|Ni&V>t!OsaQ_KayphXu$+nIERn@Q z%g@Gg4wiGVoQLInEEiz85X(haE*44p{1PmeVz~^<NuN)EWkM_yVVM}qBv>ZJ zG8vZ1u}mS7Z1wfmd&tij%5ohTZ$xo zz7>|Ov2257TP)jQ*&fRdSa!tnQIVw2KZfPwSU!Q}lUP25WhX43#g`eJcnR86w6^) z4i_2Hla)M2U^x=YQCN-^S;;=GQ_fJH#qv2U$6z@Y%W+snVL2Yl2_h@o?WvrhOvG{$ zmXooZg5^{!r(roA%NbbC6j=qd{46YIV>t)QxmeD_az2&|uw01cB9WxeFUE2SmP@f* zhUIcBS75mk%T-ve7D@X28Z6ghxem+qSU!*C1}ryXxe3e7B1xa$g5_2$w_&**%NhOE zVfhZ0?~1Hux2JN3@*bA&WBCD=A7c3tmLFsJ36`H?`I*RvK+AuQTP(j5N&5WvSpIsbCSlJxmMu)KlgO)PI=c^k_+Sl-3*Pb~k!@^38v!SY{`WRHuJ);#}7WLzxcVHqFG z1Xw1-G7*-Eu}mT|C*Mg}F%lvt+1GBuWIM27TFCC{{2ro%El zmKj7oY#-MtXDAu5%!FlTEVE#l70YZ`W*7O0-Ac-NM-D7=imYzORC-7*EOYB?S7PSD zGOx%QAkTbQ<`-Ghj;Zvz0$3KrvJjSqu`GgRQ7nsztYx>7((8(2SwduOJEqb@N@7_` zU%L{sG?ryV)&Y5z#j>2px^_&ZJHC}mQ_U719h*8Wi>1x!t!A(AHlM^ z$oh8OmC>dKmNl`gg=K9l>tIqRsuzV8Br?BjV<SuCH!atxMZu^cBdGONA+>7NtEcau10Lz0|9>Vf4mPbUAK7SO;V^|)?@&znk#PTI9 zU&itkEMLX)H7sAp@(qz>k9!l#6Ihi=Q+4wmm? z`JTv-kwMAxeJnq~@EWg0=9F|{V`4yI5 zWBHB9W_Bwn=N;c-`JKq-c1)#*e2?W1`r4J4KVtcl$QB^apRxQ!WJ^1y((8W3@;sKm zVR-?|i&$R5^0LTQb}K2p?h2MyMYgtMDm~;Hme=*QD=~k^@(+=1K%O_SyeYD+9aCw~ zTUg%4@(z}FvHTOuzeKhJb^ja7f3W-)%Q)%G^PeQoxLC#$+1{?ZGTOw)G69weu}p+z zVl0zjnH0-pB0Jdasq9C|u}pzwN-R@hnHtM9Sf<4?9hT`ub_6Y-0n3b7X2LQvmRYdO zie)w|vtyYGP$rEQ4iPEX!e89?J??R>ZOrmX)!rf@M`KtBE9g+(TGCjO8O(R>!gimNl`g zg=K9l>xc|FLs8D8>S9?B%lcS05E(KuD0w!-vJsYzv1}qTq$ewRHpQ|Tmd&wjA@WiC zxK24kX^CYkEL&sQ2Ftcsw!^YLmK{VsX1AwuhSCwsN3nbi%g3>N0?Q|{dSUxTC zanSOevFw6nS1h|>*&WLsSoXxS7nZ$6l0M%D%f49l!?Hh?1F#&31ePPQ9EIg*ET0ug`uuZPj=^#)mgBID!g4&86R@0!X8V>t!OsUpc9 zHx0|_SkAz5CYH0XoQ>riEazf5Ph`mTdF692>y$H;)mW~W`J~-S%6Z2|EH{aK%8se@ zkj+?b(bulT+=}Hkk)1%E+p*js@@YG!((86&xeLqPSnk1cFP8hT+%K}T-AYQYJAmau zkzMSVN)I`NQBej>um2Hd5O2T`b=d*&D=sAIlF!_5m?J#PTDN zeL>8RvHV1&+CR5SA59o@Z2HtmeBc5M% zsl+@lvOie+Z@N_0enFSY+AoS6V6S~sXx%S~90=rPk-pSyoz`4^Ud zWBHHBQ6SHMv5b@6JU>ce#>Fz8$k8Cr_*f>uG9i|UL_Q1hOpIj`ER$lHOyqMQ&*WI9 z5IM$O8Rv6jnMapOo_Vp% zCvqytGe4FEL{0-S3yPd>WM(<1&k*a(e!cXRSZ7X!f)a(567xe#6qXV*KsH6NEQ)0@ zEQ^br3Gys~Wl1bcVOd(_EGS!#V#qv2U$6z@Y%W+sn zVL2Yl30O|Va*{5UYax@doPy<4ET@SKIV)0n-E=HxU^x@ZSy;}-at@Yrv7CqHd@L7W zxlor%uUmxWVl0McceEK5dNpgA==o4D7rg-L6`~i~I?RZ^(n+s!(yN{H z8qtej-fNxoIw!r}Nk1=ov6i=WWoHAH8$~VwF*jkkStRWjTb%S(U2hJ(va=1#?O5)> zawnF%u-uL19xV4_xev?zSRTOgAeM))JdEWLERSM&49nxXRE{%V!16^bU&8WbEMLL$ zRV-h_@^viV&}EoUxHp~j3DNXZ=%kZArE6uBJdNcUEYD*37M5>g`9Cb*!SY=!-^22K zEI+{VLo7eS@?$JN!SYiqKg05KT`HsG7g(Od@=Gkg!t!e@zrpfbEWg9@dtHVZC4X?z zKZ*`H=2f=pPgwqpQazl=7d6id8D1lv)lmOC)-Qt(Cne zu`ZQXl-fmw#8hNbJ*KkuWV%#hCdV>`$TM-IZDW7$Ot}}F(n+Us(y7C1>uOONU78l# zEZ0?HJyDm|NvCtt>78^2C!NtrXL8b+opcr_oz+QabJE$JbPgw-(@E!Y(z%^<9w(jG zN#}FY`JHqDCtc7<7YeVf(V;MwMX)T2Wic#^V_5>rl313)vNV=uuq>-f^GT+B>XdWR z<(+he@Y?EE6-AzfpOlrHbY&-9CA_wBuByv0pOn>{^g~YiVJH2FldkThYdGnePP&$p zuI;4jIO)1hx}KA+@1z?z>4r|ak&|xhq?*ivJIAP zv22HBdn`L(*%8Y}v3yLIVLmAzchXNd=_kW$t6x1Oa;1Gft(>QJ!t!ZdDrd=^vFxHt zCC{!{b`!bEuDgy$`PI{D+9_^%`b<)o{=`l`vtdkz+q@$elcqcs} zytY1RCSo}W%gIBUZZiIZOHq?bAA@Uhk}EDvIN2+PAF*V*m4QNMqA z#7Q4@(#M?iaVPzPlYY@jzvQG}cG9mn=~tcfYfk!gC;f(#e$z>xaMCB8^eHEO+DV^r z(r2CYTTc4z@Y?!B{2!L@VEHbV?_v2qmLFjGA(kIu`7xHCVEL)Y_4WvEuAV7Zr9N}g zpF8Olj`UfZdqm%y0N&oDme{s^kI_dLH`Zp(i z!AW0q(wD+(YXrZHsbDd?}v8*O?qdkHv_Z1$(@?k6=!LmA*HL$FSWi2dgi`-r&bN9YpT7Yi6YK zeU^^84pX~Fo%CbjwN<;vbr~k-Cq(aoHGERnVQTo4lkOB=TQz)ImtktyS@d35!!EiG zQ^T%Kx?6Z{)v&uR!_=^cX!2}wPb_=s(qv%e+8fJ0BFT5B`(oKomu7n@zp2sRNe|Gq z(gp*ud`6chU#ndQ=~7wyV3GUm93RO&tv%SpOa@|=w26p;r&-KSzXO_xgDr(-!o zmrC7dVmV7B`3#wjF1sF1}DAINpEt} zo1OF)C%x54Z*$Vyo%9YTz0*nWa?-n<^d2X@*Gcbl()*qC0VjPhytYP%Ls%Zh@(7kk zu{?(5aV%fJ@Gz%V2TuA!C;gF={@6)>;-o)y(w{l$ z&zI^l3YK#gym&jD(BNzu)K=pH7u`-JYpXuDEHTX$MO$dDs{hspWkB8IB46}EfOWb{M31vRoKb=ebB_&=6SC2SJVqItWTl9-YJIt;7 zPf#j9pIi4|DfN=$y5g9*Wuv5&!@A;1sh7>V;v|VUJ8e8C9beb}Rh&ez<{-v0A(n}- zOpK+pP*g~3DK$!pVDY%SW)R zj%5ujYhqao%i37h(Pfx1x~`M1C;C-;j8^(oeJmSb*$~S{ST@G836@QkDJ(nbQt5S1W7!$Y zE?9OI`MTZf5=CEKQmz1Xb1u>S!6lR{Ks}sG^pp~BgsX>j1*n(kH=*t=x|glPeAe`F z(tVwDKPTN^bZ?mV04F`rNk8MH2Z=tRtrLkywtxax|9DV)-1FW3U{nOJ!@0)1|UCqjagn9Is0y<^++aKo6OSX8V>t!O zsaQ_KayphXu$(FKwB7Q`)|{nFWoypXr4ns%MeauN8chWC7=@*^!OHTS_ zC;f_(e$`38=A>VD(r-BFH=XneCw_CqKAk?42fX#25~{zTVdM%z!F^k+``b0__UlRoF9zjV@HIq9#R^fylW zTPOXUlm6aG|KOy5bkaXL>7SkSFHZW`@Y)(}&tv%;mKU(Rh~*_LFJpNH%d1#k(`A^^ z_PUe)UG#g}XlrfNKd`)^OOvk^^Cp(JM7|I5yp81@T`GCr#qv*)AAmgn!t!rjDtZ2c z<-a071bN2EY@V?tGOjL_JmX;*U*tzxp2~S$0wRh7AKum^vCwTt&A7h zu*|MYFQ3phLf)8q-#0p+D^KTldkKe>pAKAPP&1UZs?@{kG=B%aH?qHc#f`M!v>;o z+#RQ=v0?AMqFAu^uGo9|ED=yaMNv>xEU1XR*QnTg@4ffld;MnTWs}{#dAa{2?~ViB z=XWGC``g)>+1Y*jUc#}Sie5jS4tA{#U~(W#ZU~bb!Q>#A+!!V|fyqr_ax*4h2Y0Q( zDtdDjy@iV2Qblj2qPJGj+o=L`Y;uJxQaePMIWi6k5bV`tLXo!=wnp$u`2pF6@9#l&Z+1VRP<04JxoOp zkEes(_C%OG2_{d5$q_I)5++Z9$x~tSG?*O4u(uA6qPiw2D5H>9-}n zgNiu|CdbI6@CpkWS{Jx6*Kt+G3qCZm6AFJq3RP?7R`ZE>%xr+WmMSrQHzlx`W>+IJs`3+2d3zOf$ zW zg%iaLFgYVkc7@4q@nm#2?)`1^nN;-5DtZruVZwV6rDn&co#A!05eTa$cC6kI65>(S>~WhRHrMDXi{VnCuIabud{U zPYSEMK}Gjd(Tys4eiglditZmz2djHQm|O@Z7nVt(8nZCD2$Np|6}~7;E+&&PXM)95 z^b#t1fQnvHMK7hImyV}{%2@^`mxamYWKyV{ad`md;>S7Q3> z(DnsQuQ@BjP4Jspz#;^g1efT@}5aie6tuZ=j+F zs^|?>^hPRrkc!?|MQ@^_H&xM_#nZt~I2a~3hsiBqa!Z)p3MRLP$!%bATPD8^_X~5L z6wYbesp#!h^bRU|M-{!3ir!g8@1ml2Rnfbt=-pNH9x8fI6}^{=-djZvQPKOT=zUf6 zekyu@6@7q;K2Sv;q@oX2(TBv-!Tx+GOdbZ4hr{F%FnJ_Q9tD#}!{q;9@)(#r7AB8_ z$>W*)F1(JIdj#Q|={XgBf=tJpX@{!lVJdpKiat?ApQNHsR?#C=^vHNRSi`5lspv5(daQ~*TScFvqQ|M|b5-s0jhD*6T$eWQxLNk!kRqHl?(gW9_lCU1ku+hOt!n7k7v^D-H; zrtebGcQgH?w5El#z&$E@vP{REKkrr1_o?XnRrCWY`au=_kcxg-ML!Zx2W#X}n0yQ- zABV{&WHP3npH$J$F#VIMXY+4j8!6MJJN;>XpI%Rv>gb$n#tL%sY{fla;GRD>9rNhs z#(c5jo-c9FU%++yvWk91reoIat19|675%!3enUmSsiNOf(Qm8hcjD=wM&E_W_h9mU znEXH{W7h45D*7X)e+BFLV-@|0OvjutKULA6sp!vD^cO1nOBMZM*$mOs)x&Yr*8&Fu4v)t_zdv!Q}cd zxdD@Zhu4vqGuS{Cy`hTUNJS4)(HpDiO;q%zDta>&Jy=C=uA;Y4(OatMtyJ{ZDta3g zy=^=l>}%V>(POzz6$KjD56bMD+tMenYn_fXM$s_4B`^xi6Z zh>G4vMenPk_fygPtLOt%^noh+AQgSEiata|AF84cQ_+X3=p$70kt+Hq6@9dd{$D&D z?9a!*{V4wEOsybmVt zhsg(E@@WJ<3F!?G>z6O)8!{i$<`6f)h#biymUkJY==WUpL z2PWTz$@iFS2l)9uOnv~9AHw8EOtugGoYeID`5(jNCouUbOnwHFpTp!AGHITj2W#_7 znEVPRzh<%nkoj+5@>`hv4ko{c$sb_yN0}5d{}W9943obw*)hz#u!sB#lfS{_?=blX zlbrxR|AfiEVDfL6{D;ZTfS>=uX-=|pzll4r_ z0@!ST$$l~^oGuz+a(*Uf4gC~sE&!ALVRAv3TnHu?hRH0GvjMR$0+Wlv z!Q|>Nxdu$G36pCvIVTYN+Az5eOs)%)>%rvuFu4JfbA_=FZ+hJv2$LJaj2~2JZlbgw;kk7#|xj9U30h3!YIX5uxTfyYkFu4s(ZYz_*yl)4S+r#7zFu9{l z3iG}bOzsSmyTIhGO!f%pT{zS329vwXq%cQ&z~r7Vxfe|C&16p?_8~C2k4y@&?+cUr zF*y(5=l(ExfJ_R09te{M!Q{a(c?gre!q^2r4~5CYVDfO7JOU<kDsEimur!sK}{c|J^z zhsg_I@3n%~UWKyW5>t#}~c>|M;!00#1q%itTGAWFHGn4ZJqu(Nv z!sxfkq%itzOfCS7e!ENxqu(Ku!svH0**_dzc(Rv=$-9_b5U_bSOy0xfLV(T5FnKSN z3j;RqgUS1u%!W3F%s&8=56a~5rn}-pF!?Z(i-dj(HXo5mA)-fRQn2}$ObRw1XL8Zd zPoX}afXOGBTnw=J6ihzN-{a5e4EK-Lq7$Z@4)1{OfDDN6xQZ@ zF!?@{%L6t)fXNS;Tp_e6%+W_M`LRq2`TPVXKV@>o&`-hUXEG^7^tnt5HouTb!RD7t zt`zzy%==d``8AU(hc<=Lzk$hbWm1U!JDB{Q$yGu>1)D#>ic#nEVqa|ANWCVe%iC{1+zwgUL)U^ZidGpEXRb31q$< zOty!~4lvmfCOg4oXPE2)lQY2Nj7+W-W?tAoyTW8QCf5dR&IFS)Gr106a~7DKmC1Dh zo3p`WcP7^ZY|ajob1=C+U~^8GoQuf~0Go5eWDh0>0ycZX?f0g%|<3S4gD0z`C)Pa znH2o&50eWrxf$T+LNK{7OlDzn5he!%el7}=i^1gLFu4Sin@fHQzeRh1ie6HtCsOTC z;`;AcQ&W@SA3C=zrJ|Qs(aWglWmWWYDtdVpy@HBfQAMw$qE}YYtElKz6HQR?*w2=xtT>cJXwu-)#?*JHX_QFu4;< z?hKQ=z~rtlxf@LGE|W34?H($6Po}pFciWg9aW56Uw~8L3qW4kJ`>N>uRP_ET`T!Mu zpo%_7MIWr94^h#Fs_4U1^x-P{2o-&#iasiy4tB(&Ve)@4c??V*3zNsegUJ(M zawwBqg}auy?-$OW!&LNenVu-05l>XnC#mR@RrClIJyJ!VqM}b#(Wj~CQ7Za$6@7+^ z9vx2ytN%=xJPRhrz~oq%JR2s@k;#}7$v72#F4J3sYx_JEeZEY`tnKkC`T`Ywp^Cmp zMPICq8Ca;9at6=hKn7jriua(J|wSAq6zMkoA zz_opYioQ{%WA0>bQqec7=v!3utt$F96@9ykzC%UdsiN~L`YsiHw~D?;MNd}I_p0do zRP_BS`T-UFU_2e{cMrkj!!Y>>Og;*ekHO^QF!=;bJ_(ag$z;rK`?QLFhUsm?-8N=N zd{#w2r=p)%(J!dz7gh92D*9y={fdfyRYkw1qF-0hZ>Z=uRrFgb`fU~cj*5O)MZXtM z2Rq{XF!=#Yeh8Bv!Q{s<`3X#Z3X`9~DaD;cgqVBQB|;mr~J7tLSA^^s*{?ITgLUie5oQuc)F| zQqe1`=v7qosw#Rl6}`HOUPDE%siN14r-L1FZJ1mKCf9|@^N*tRrF~p zdX$PjJ)REsyE9;NG)$felV`!?7?>OjlV`)^IWRd+CS!Knb5-6`6_z6 zioQTaU#OxlQqdQy=m{$N5*2-^ioQ%mPgK#DtLRB8`U(|&rHZ~vMPIF=uZgFF9r0S2 zybdO>hshgY@UyY}O`G1Yc zy+SW8lf8IdMZXbG2VT6%i|Fjg2LTcN4U_-C zK9_CfmVedzkD1lO35n1c;~;Om>FJE-*O*OwP#UpUBrr!=m|R3Ag*jRjCKrRr#bI&@m>d9;OUk4$M@zxv(o7x&%+WG1 zxvWeIbF>^xE)SC{z~qWBxe`pSER(_)8e-x0Oj@x7iLRw};6cU~)&8+zBRkmdW8w?|OED$z7Su z0duq)Oztj|!W``ZlY7GCUNE^gOb&s`ePmLYqkUm=KPFEA=4gMIJU}J|KM#b-gP0r& z_<1l)9wL)MEgcGzhr#6GFnI(_9to32$)qqxN5ka*m>dSo(J?T2tV{}XbR0|`50g2V zJOL($!sIZS6y|6+OrFT(aA1y3g2|I*QkbI=FgX$?Pl3r(Ve&MX93_*&9Gwo6XE1r9 zG)Ka3cpj~y&y;CluFitVF)%q6CeMb+b6|2DOr8sq=fULpGHEJBnAPzr`U0j;3M)pa z!V6_mI5%G;lY-5QWm2#?fyt9YKMg75;1U&msZ1Mx1>2XY=!r~^0R6sPMNg9H7{9Mj z(N{7(Qt~_a{=-!;d9_TM9b^*yWV(3&M%Xnf`dSrzor=C*Mc<&JZ&cAYspy+k^erm- zRuz4lioRV%-=U)KRMB}AeV2;9TSea!PY3I9GECkJllQ^o{V@3eOg;#c55eTaF!_i~ z#_Y0>s_4gLQqeD~ z=vP$qt19|675%!3ej}a^cEmSf@-3Kr8z$d@$#-G$J(zqSCO?4551BkQ+_hrP;vcE# zk7atId`A34MSrTIKU2}4tLQIO^p`67D;52z8@=uu*o*exJlYhhHKQQ?(O#TOxncn7muubwQ z#9jlF?O?LKOqxmwX0roKc4Tr?SRpZY@tst3XBFK=MbDt3XH?N$RdhEMJ(G%_Sw+vH zqGwgnv#IFrDtdMmJ%@^(Q$^3EqUVmMgZ0=0CVRrD(M!bB z!LBs`CYOZCrC@Stm|O-XmxamYU~+kwT!G0m!d)xoPJ2Zay^>6uv!U>**UBn-6{bgr zeqYe^+_@@Dt_G8Yna@I$#X(K zg?sF6nH&d@+c9}AKyJ_Ec>uWsljnz|uq*BelRLrW&P0m>k07MZoC$z~sI#xgV1k1EcQ`lLx@$flN*SMn4E94~EG@n7jlS z{ZN=Z3?>g}^3rg0VgEb=CXbZK;Z66?qhRuACNBg0{2xpnBa_0Od@M{JCzC?#$HQcf z$%#PhC&1)TnH2mS29v{?yd3cJM3_8DCIvrFhRG33P6GTK36rPDq~PbNFnJo2R{(yF zg2~fmQtkXIm4KgT!sJ;pDfl@CCdV>)72xODGAWFH4wF{{Hpju_xiER2ObR>L z`7k*iCNF@=3t{pin7kM!C&1(-FnK9VUIvpBVe)dB6zX#lOkM$#S2B4GQ1e&8SOg<`;!W=yYlaIsX6EOKC zOg;sZPs^k*N6*0IvrJwO%+Yf&`8-U%Ad|u#@*+&W1d}f_c>@spD=_&gOui%#z7LZhz~qN8`H@TtHUBY8egc!9GI?WI^Fq~q29uw| z{sH-+;qTswY($)9CXsHIiJr4JLnw z$v$7&E(DD90~dS2PXf8$^T$7)5m;274fqMCfhN2OBlP5&-O6c0VX@j zO$=P7CJ50_F zlXJl2oG>{TOwJ9HJz%n@ObYcm4@~xg$$6Q)9jN*FV6rz%_K``U=4)ZHFHF|KWIaqa zz+^v|Y=p`AVR8YO><^O*!sJ3SDb)PJFqwtPMVPz;sQE=qDeNI@!{jRnGouP@UR>0~{LPuJe>Z`nXa4^+_`s_2bW z^dJ?zv5MYAMQ^I2H&fArRrKa6dW(2E`1=A|!sJ#kxiw5~1C!grXBEARir!U4@1~-6SJ8W@=si{RUMhNT6+J{n@1vskRnhyY z=>1jn0V?`H6@8G3J~*BZ_Pax1@=%yO3?>hU$s=I$NSHhdCXa^6|H)*`ZhMT1K9=cw zz}@yZ6@9!+$LzK_6@7w=9;%{;sp#P<`a~6dl8QcAMUPO?BUSV%D*99veVU3MrJ_$) z(PyaW(JK1Pcskf^&w|M@FgX?`&xXl!U~(Kxo(q%b!Q}Ze8ME7tSJ4+RJz3gqgIT>0 zCNGjn<8NT|Vwjx3t%YPd~bGxioQ`r-=v~%R?)Yp=v!6vZ7TY96@7<_ zzEef#RrFo)bgQ_$j{+TeSJzrKdqvlQPIyb z{aDHGOqWLTSNN>rIhcH2CWSn_0Fy5=`8eR`OECGeObTn@6_|WgCWY8vgUQ#Kd;*C5 z4VZjWCWYAFg2}gKQi%N>n0%MXCxO`CgUR=0QteFG3;i_toW$2r@AKH-RP^sE`VSTTr;7edMgOg$|54HZs_6ezbf(sP z4;P)w8Wr76MYmVc9aMBj72QcicUI9|;_2W_KLbq82$Nl5vKvg!1d}tvv1J{8?tMfXwBwJN%=imp@9 z_3?DDYc;@RKbUNU$@yV&0hsI$lMBM+LNK{7lP`q3mbv#Ao_S|g^dd5C&W3{RMOE}- zOurcV9i0z5)zs8v_=nCOi^Jp+FgXAwmxRfsU~*}gTm~kWg~{b$a(S3s0VY?3$(3Mo zWtdzACRc^Y)nIaUnH26b*MP}2VR9{)TpK3Wfys4Yay^(_A0{_o@+Dxm83>ab!sJFU zIS3{J|$)-bsZOl}L4+ri}aGAZmfJHX_QFu4;< z?hKQ=z~rtlxf@LG4wHK@`Et112$|m#Cii0U6~N}+Fgb+DS3{c@@iRK_47LwU?hBLq z!Q}ohc>qiv2$KiF^`%( z5TY)EsEe6;I~-9sO-+EwOPG8Iuz4v=UdH6RfX#_8c{xl@g2^jj@=BPz3MQ|H$!lQp zS|;BEGJhRRUJsKuz~qfEc@s?D43oFO7t zz~)^rc{fbn!{kT6=#ydcUYNX(No0=hhsg(+MCRy0n0$!IkHaiYYFbMV!{j3{`6x_2 z29uA&@(z66sm!{jS6DV%Lyg~``o@^zSe z118^u$+uwgZJ2xqCf{Z96JWP_4<_G-$q!)iLzw&sCO?MBPhj#>nEVVTKZnULVDd|t z{0b(&hRJVW@>`hv4ko{sNnyA70VaQh$)8~IXPEp2CVz#=-(d20nEZpuPs80t$o!u$ z`4^L)0XF}J$$yyqJhUl%BJeLv{s)tpzUI58$mlgN*$yV#!(<1T>CTE4o*`&=+NH%#_`$(}Gd z4@~xg$$4RNKA7yyN zlRp6D(oFsckjpUn6F@G@`5Qp4$mH)KDa_GIO#T6oD>M0L zNDgm0N2|c(sxm3~xf)EaE|Y?vYry21O#TJLz7|ZbEt5j*>%io?GAYEq9!##!ADI+( z#eHFNKbYJfCJ%tg17Y$Ym^>IJ4}r-;Ve&ATJRByEfXO3a@+g=*8Yce-lgGg1u`(&_ zipRm^@i3W#$rE65C`=B6$>A`0B21nnlftfeGE9zO^51Y*6lQZIOr8Rhr^4iEG8x=8 zkAkSvA?ggK{sS^I8Ya(#$+KW`j7$cZ84FQoL)1A;WjgY2`dt27r^9&FnJM7UJR2HVDb`}yc8xcgUN|7c{xl@g2^jj@=BPz z3MQ|H$!la%*sZUH$?IV9dYHTcCU1nvn_%*0n7johZ-vR*VDfgDyhA3+87A+A$@^gPewcg!CLe^!hhXwyn0y2#ABD-sVDfR8d;%t) zgvqC1@@bfSMka+l`dOHK4kn+6$roVqMVNdECSQihS77p0n0yT;Ux&#zWHM%tep5xi z#dP~{j}~g`ZJ2xqCf|k0_h9mUnEU`HKZMDTVDe*_`~)UHl}X|L=`)!8945bj$uF7g z094&qF!?o1egl)=!sK@_`8`bj0Fyt$lS0+~3X{LV@q3DJ_k(B$>a<`>~q27+%hS|-UB9k%A^qcJTTdd$r*vz=Y`4nWKxK| zH%#`CNg?)HnC#2skoLv>wY1)aXE${!x?V*$sOWx7?*sbXsG{dr(F>^P{!Di*)mrX+ zbB)N2=RYstKQH7zFXBHh=07L!pO^5Tm-3&N@t+g<&&&DGN&M#({O6VY=T+uU^BY^m zPd^r9Pr9`MPqOUEOeIgE8oY}94u0S4B23O4k|x4{T!P72LUI(5XENQf#`&$J161^q zOwS71UP?tT&Gc->_U!ayKELY0vp6gN*+{+%(JsTix`!T})if{5GC6xlp5ByPj>&Cn zc-+$GXu&6U%R|%(5VayitprgkL)0n|wJJod&eR;G%$oU&{=K2jl-+19Ox2nH@%mgt z-D6GeF=uIvXr%;mvKBdJ)Fn;pWnGz!R$C{Ixe)hyG8sg%K16K*Q3D}rLx|c4 zq6R_K#!Ow)uDHg`zvd9tjIjG{!t`8b_WRM#0`#*G{mf54nJzPX5|Okcc6PJADfgbc z!rq&4?;aKQ9?ZRaR@i%U?mbV1y|>`ry-e>+m(o5a?2TJ8Ija0q3s~^TQjv$X(uh+!v^FwFu5&EZU>Xw!{iPyxg$*O1d}_%6z&`m^_}zr$d`#o7&95$}^swiuXnmBuyFG(@Eo^$3$}63DO)pW zv$m;xGj1di5w3u4ef;XUE0;ubm-ot0|lO&(Sz@BxD+B!tiY?0I{lID%1u8~w5Ni#=M-$l5?6)`Z&J(4tD3A2zEx32Fb%VO1HSWDwWWAV;d^Ax-esp0P?dZLuDKOr0 z|6L+`MSjglHre9#0g?S;_HK;q+xCE7*SEG3`)Yh+TXVMaV|gmFRcs#+6}7dUJ2bLZ zY@aR4OtF3ED3e8b9e?!P{E@w4|0N>1zUWV35m|YksDH7&J{r%;yZD(uHX6NXeY8*K zx&_gUi`t9)*l1>q%ym38h;H$~yM_J!`}?^)H1fv!np-UDT^y}~S z%Jy($WqZ7_vOVBf*&cDMY!5kBw#OVR+k=jk?NP_d_ON4Rd)%?IJ@8oB9(hRS+}T5q zmF=;|%J$%6Wqb6ovOWA**&ctaY!5(Iwnrc<+e46*?J>y8_8??sd#SOqz1UdUUT&;x zFF01VmmDkGiw?;=-}bU&WqaYV{J0vfpM$MDCXg=)om( zSFm$xNpBV|eLfRS#EZL&|hLZicT>Xua-fSI3edo+Q90q;L);Tlw6uKvC-)Y|i zcHQR~63=C^^TE3xxc}}(9?x>eUH0G2NEb$}`yICLA-l~$@+DC#(WZ4GOPxsKu9Hge zAqM`~$TjV{&=1`Pw=-X#>XK`pq5sWd^d;TAMz=WYas@rzCw9rj=_MPr&l@A2-BrjI zUHEFOO?ux&tD_~tekRpdvM1?MpYeH<@`viCraaT-i|g5qts0$nEl9a?ebL&J`l33? z7gQ&WQB7aTo}@#^khp5>NqteB5`a3*O!*C7shMGD5uL&t2uWO!)Gwdx_UZe?Uc#P%IBu= ztdvxno0rzGS#G>?Z8k5azFNc2O2;b~L#1t%`ckf6IbX{4E7w-eW~FWA#;dfgoG&e5 zv)p)ITQ{@bd+>U<`+;pY`$VpV+cUH$nSI8NY1Ud>(se2L=K5!JHdkgp<^7>c=KY?T zZQ}Dd1=?+0@jMFSC)sZ1EX+x&^RKhER$41Bc3rviY{pJn@5W_qSE5U@esVKsYQufa z`qUC_NzZAn6Z`L-(~AC218r!&a$V>dUSq4 zW!?*Zn)P67H;hkgGiPh+A=Y&pY!hRcxl9agsjX8PKhrk32FvB8EzNB?U#91^Y3?QC z_LsKQMjwU6`q>8C#C@v)o0LCPH?`$CT&MOsawc9Ii+N7q>fQRa{acGQeuZ;keMs6b6O)aL#^4;Z z=J?@Q_Oo9Tr+M~a_nt5x=DsS_g|mT1d5c`*5MpX=DM z%jui+?=;$Y&;FY^DEAD>#2D7))T#^X#KbYJ>v9yK-A~HJi*mN!%sx`i-n7D@c|o~p zB`-)E(%zEm!yAvc_eeTZTekm7^xo`2MmGCgTa$Apq|7SC>w)!iYSEiqC%MN@P2X=W z7kjv-tIbg*_NLZc+F0rOTKq1A*)yuu+dUyu*bnU4#n`pB?X}5_Cyi;Z`IZlTG-FsB zX3kyPhIQw}^~c&XdsL<{w%rSitZmowc2BnByZv3CUCz~;yjXw3Gh-#P&5e6rwK|gz z`#zWXo_A2AbA791Ot-%@ZroVm*lu2memZ|YBN3ewchO!U6><3~a!y|_W=HSNryIAY z7h;;lnH%?gF6O?WIeR7+k8xu3^nx#59)$7Z;&S~C=T?$kKbrU}_=VPou~qGL!_Kd} zCnc#fv4{2~UD9z#V@SHB$4%{3SCe)RYKhuzDce)aSv=NHXAiP#m7n=&^^N9IOMl_t zS@UcM(1+_L=k&4bHb-{N9Fp8c)83M{y?i-7$LU+rmzK007f+nNC4Fg0+i~%@dQ;!# zKU)DS-*yDPH)z_WW(B_aoCQP-Fp+)hur<0 z%*Mp~lFPb!du>2<#(&$#yf@>yW0upIe%4n_Kh%D6T<*Wl#eCQpV4d^5Pdg6p@oiXd z)~d~UbDz-}&eR;rwZvyK{IclpM633L-Yfb);am&qBOSD
  • eHS5tJpu|b=|sY^GRI)@rBZU zn>IW7ADqPc{rnauf6wLP^>+h!g(nBlQ{{FgdC~a}*L+d!dQ_ojQTjJ>>`^a-*N9w*5 z$osA%`^fWH3F#Hd)9)E5dhXHlNFeLEXQ1#Wq|Z#AUV7+qw)da9Z!2wa=tFq5=0nTlrYmX6C%TwE15}%5m}NDLf9b-#yrH_ z5X7)Z2&*94BmqGM5m8VS6Ho+kK~%IsF=F(|-whEF<*9%h;POy`C&=>uzEgGjp026t z?&%4OIP?3}J@+hi>YT4m)xCXt8Ta}(l;7#!e*~5HAMf*vzv{pDr}VF$ zS9+GOixhouM!Wnj@`E$n>vGVMyiZNZm-+9*FY~`|04nw=`5XNAn&05Rrw%IiDf#1v zxp*Ew%*6vL_9^+h_jUI%&C=uF;Ov{F)Awt?m3V;4{ZfRkX`o+KPrt((oqtgAAEDwu zB3FCypVGf$zxJCsKB(A(ia*1vT<8KHM~Xf>$N2*ld(f}bzu{Fb^eJCoPx<-+mHAA` zZ}s(ctFJFmu}{e__w{wTuP;!sPsz8K?dod_|Na7~*r(*5^zWB}%DPCs%&bKJIfApj&eMY_{V;g+J;|jt3R~IWYd{T5zKR&4Vd#(2mD*XHX_@Kg{HOIvRD*S~9IUZE_cl*!7feOE?*Mkaw zw%3CSe}{i=nW9@QbpAobex{EHRQSt$yr9DG=kZ99zj43M$vtYyEW*XQlt+?UnwYw^zEaw^w@FL2mz4y1T!>R+@Xg(tfX3dXCpCJipg0-+uy?dA#Y(FOrua69`)-5RN@}UtG%25!cOH% zLw(4n>{PBa>=*JWyLOo;&2#2FXID_?XQqFj6;#$s!K-~rp3jXD)YGQ!WT;3F7u%AUE{AW1$A*<3R z1yt5c!8^Zcc}oBM`Wfl3F9mgRjr7+SP?^V({`&I#%iTO^d_VBtv;Kkqp7js>_o;s{ z-M#MtD)E-O-1l%xUG8~z=}7l_vgF@i02RAszJEyn?mx#C(l-A(KBVLQ>-~^E?ENd9 zJ<@$&c=ky5+zIvQ{KstU;y=d!j^Z)?^C+NV_du8P_du8P_khpy z0iP$R*xlxFyUpWvn~&=@j~l4iZQ*g-!sE7u_qT=j2P$^6d>*rW9#wocK7%^?(uotg(>SzV1N9-$uUfHu811k)QvK{QQH8-5$Q~_V9JLhp)Rm zeBFVH-E3cXvwhvo_H{Sg*Bz+X{m|Fl4}IPJ(2x5=KQ5@)9qsE5RB!kVWR~~234{;q9yu0qC+|dU z_ikS2zh46?_zdLL-rZLeb}CmI>O($dr*frXzmQMawO>m7HP7$PadriDe!lDL6jbiF z3SR9~@{~ShpOO#F&pZ5l7u5NC$B}M4P?^Vf9Qi`Y+hra!zVrP1iD~NA&3S%aKxG{j zyz`fqJN?T2UA_f%c&zmMG^osX!K-~rp3N& z@HKRSe?Kinzw@2ZbGT3SZ?Un^eKvMV2FXROCuavz;7NMX&rKuLl)9sOXj7);~{7(VKj}DSD&#o1)+MxGU}R{sz)D-(X&S z{(1{4`*h#THL~9gUGDM^$Gz3h+d%5#xz%3>K_#AB=eT%=E_d;S<8I*JcPywIZ-ax} z{sSs;Y;aIY?)+;1`F@=i)b*S1pQnI|zxnf0a_3L`pW^4cSvua=@j&YE9q&J90xEHg z-^ax@$a+h~F?vMTY97tU}KlbYr zRO0!uU!OylyLiHJH}mVWpl%*F^Xn5-;@Hfu&w+C1SNrFFeHPUD%l&+Vioe{~!9cn5 zr~S|M>$6$9%3qHP`iNX7R{7sa0hRGrO@E=}Ef)Nck5ac!&i4BWsNDY* ze9BJcO2d93pR!ZA(y(91r|jBg9yHJCew`N7^_xChsq;JC?`NQrcfqIZRIW7a7xF1P zl`9SVg?!4cUGmmEFZK5)DY~D(zf93@`2Hz+h3}uDSNr|6pf2vK{qLlJ%KEt4|4z#D zFL!upd@KC^t#m{G`7@<&^?Id$_WP^SFZkaT1>KU@L(m>ig+IaLk)mJnb=oX#^W!&5 z_w)O2imveSrRX<(e9h9A`}mrr^L%_MdddE-ehTW=#U=iAIH;`Kf>-;LJf%E$I#+=;teh@&{xyn6aI7Nppw@>-o+DiyyaoE%ie0V@38Jq~~O zIDkt0h1|tIQ19Yb`;$EmCwm+~#ZMu3eg^8DAGLpYR{JW(2`ce@eZJ#Cg@4f3Wk{F! z{6h*q^8Fm+Pk8mWqu-Z6WnbFS*Da{TKah8I7Lm*Pg&*0M2I^g&h2NwfSyw}iXXJdh zFM-OwG}5mZP|0f`@8XHbB`^4qeQBWH+z$0J%Y-76>_(Z z2I`$3wIAo#<2b(_LB&rYcYX%yogcNo-|tI?ZprltUa9Oy;FYRe=-2)HgtTq6drp1l zJ?=U75&r)^-skC+{{KI2>;M1b*41owX=zv=aRd;J%^zstrrzuWlzu37qLzrQp~ zf9HSK98~iB-F|MpfyzGeJO4Y;po05A-ql4!F6#|`WFHx*ck@&DP5P1bHuQMhylS3* z^7Q~JdH?B+E^koTXa3}W4;obR9>}|RBXY?beq^5+sCRi6ev^JA@1e)z^42^L_0KB@ zOTX*uf3UR6|G&*k{B^LPk6g<2cgZZJ4wp;({st=hPr;|`RIW7a7xF2)M)H)tS^w=m zUq=`Fby`s8fAM^!&hKKsAA<@W1)s80xzey-$fxWY$y54f{kIDqn*X=`_3+#Ny76s) z-2j#K*I4i3N%wQ(6@DB)!`Jl;f1R1(uQQ-BZezV0H{CBB$MJvh`!1;LKcI5mQT|cC zKY@xKRP@R}dqBJFtDvF}`Lh3i8la*N`EmZb(ky+<*K4!%An(6fI?;b0yIHFLPdY`f z_x@5e^Z)YyVIR^~?(qLVq2zxL{&;Wqu;-N?da(2>D_!h)rBj^W^2#He-D2PW zo#(c5tnxek=ic7w|KCHE_y6yq%Afm+8v8N+|Dt~R(Dg*Fbkjv{oEtaYP~FENG=art{(Z@6D!w!c5 z^zQcch|j2kj;i4gclsZzpI173MuoKKul_cO`B~ueA9c9*6VicxHj4SFafdtpH=fV^ylvF$^7@CTC;0LA^ZGCO^>K}(Z5y_Ib;Stj!txt#!x;QK z)0tb~`M^eA#|e(U<*|_IO^Y%9W~I>0rif zgYTiVsfpM$mZA85DfZ>O)@#po&UWl@Eb2m8J7o2m^_MyieGc;jaURBG7?b~`8d!*Z zWocx;87cMBUgRh5S%!V<0p=)5_bF@G9z%TF9rh589=Q%w7 zOLMI)976qSU!{Yok?>j?@{N3j_R9AJ>n7ysS8ZcdWsS!Fch)cTbDpCA&bbZ8UhGp^ z%OM@csK96#i(xE=Yhds-aHzk|DkX+?pIPXyF-t-1`F|4DijC6$q}*SOxoRE0P_d1` zT3{`ZmRGs=oSKzs4Jm!Db7(fMn4QL`RB>1OT*p4_fAIVHFlNJ;y-+n!K6HlrSpE&g z`|#y8?z~*y$mv$E+=%g&``0?UdX)QWLjMe*6R2Cg(#zI5>iw0=o2ZYiy$?rMk8)o- z>7TJVkN$f1a|h^uKr=kE8xP zt&Vep8%M@mW6o3Z`;1K!=fqlDJL~?DwNhi{38UQ4{i9Z;M*G)}kgwS^(x>8DM{?pI z^`UFI&#&P=w|2{R4fpxA+wZ9B=hs2sTDNZd++`SsRpoVwQf{2FUEPF+WRE8Y5OBF^#+!JMxN_=fr!?kj5(Jl<;p{)T`L^fE6G zxVn||_2S=?D!;?{3skJj26>bmG%o!WcSK%ZLsI(ew*8(1pUk%%O(|YOx%-cP_nM%QypcZTui9^+$D)0-8+WPlFL(S@E}+U*(@sq~cjueiZL^kN@hGJ)GO}Ri5f=`m6kN4UK2j zN_Stb&quCW>7JA5zNNUe>Ob_O_-o$PIQ)DKRllz4OzT>&V^{g>*R|<0_r7atm4KRl2shaeIPs8}S;q?!Q`>y8lfbzCQT<*5M!GGkkq;&(p)}&-1-* zhp!Lrek{aY>vj10P>$R^#!t3Sm{kp$z zn&IzX2Kl;hsQ1~ro`&j2_k*GCqwC6#*4be1rw9AGaIpTv>yP5EdFwu_bg25_{jC0V zU+?2vy-(FT8-D)a_OYQp=Njrhr0Zp#EL%y02>5`dnIR^|`b@ zryhPjEzgOEpN9-T58-;z>x$Ch>qGtfkfB~@!u!7A_b>JR%8>f!aKV19_YGRF?ZNwq zjd;B-D1Dx;58QJH)Aai*@)@i(ZBmo}PUp;Zq{*58wxrqoZ9hFPM?U8$c&saV@cA0eI2FbYAd+fnoD6^Hg#z} z&lmIaf`1R|4i{^=+^+k34>7~{!5r1kjo9yY=rdyfU6PtL8NsBi-}}(d>^$G!x6&N- z`yhI4>G$6Y8ElSzel_o=zgIQa@5#%5-XP# z($AFH?`MTR?r`%_9IH>1yBLv(1C* z8+`V;nZ9b1qSd%wLOG>!4dvC`Kj8P}2i)3GJDo?R(fM5M`v%|B(>_Y0eZT1Y{=J29 z|BYf+JX3Ud9$XzLK3X$M|C4Ly-?27y9%Gc(AiWOh_XBCC=Z*9+pD(mb=SXAM-;2<= zRIdEGq(d27`-a~|()e`!DUGhf;p@5F6IHQ%4(?GnALa0MfACyD=d2m}qI_+V`u?Hb z&%cykpEt_=g?=rQim&YM+rqtDzmGlW=L4y6{A(EX+h{+H)i?X3hkJ`ZdePz;bgB;5}`nyFdyPU7Jjt(Z~9zPGOSN3`zjt(Z59{qiy zm9OzW99tf7K_lQ1!&1*Iez25b$b=SFOuWMjT{C_Dy47r)dd=#a z;jUH9#;Mn-z8UWN)NGv1#?@>bO^jP^+ebgk;6B4}pa0IZeiwTXukq|_a;eMJ?pmVv zqM@EP+P1~H+NmtGZ^UcAdUX18FixYmLOtUv2kW@3xZj}o`!zkmuUVZBrGN0(Y42wP z`s|x=E`I}YGSB_*wrwbK|J#Tg_-EUGPQ9*vpU3?;kGRhWY~;o{ukJWOY~@~m@7MEc z_qyYIK90V%dlHLQVlVgld%>O^oX>lzK4;QrE4h_>{XKNgc<1xMs?USzv#H!8`#9!h z;C}1v%6=`&{ip7+`ufDL-x{62MyBpptM@v=o?PQY$4>0SHMSZ{V(+c7Z4_H#AFlDC zu_gB28e5GmvESC%Hj3>znj_YYwsvz)8Tr`j>EU{5bL(%oUaGZIt(S0bo#|hjPo3Z} zdqVfD8E;^pmiE?}e!rgT_v_oMKKG)}miE?}?S4-Ee*KH8&wc5$sl7GGy_MWriM^HB z{-dsW!Mv1*YqI`5)eCeV_TpSG?ta(Zv-;0ZSLv@t1^RQRd%1ljo4OY z2K%b4$-Y(lI|{#L{HE-+uhm;WR<5?xmwWu)sK0&R z6MR2nYQRsZwP%jc>)x!-j`Z2kza8)P9y=d04|X3ib$2M|$m`_X>r!&H6`$UA_&sIw z9)Mnh^}8c}UoY!3pVdQrPgyb7*Ym6Yjo(L()Z~l0mIm`4{b1gU*ZVp99#L3Fe%@u> z#cZ!(|fV=k&WHyKl__S#SBiveT3FOz$5y&nkQH}7x$^GY?( zOZ2|i>@lf({=v$tpJy0;jlkc3aG%i{zNW;#1K{g$K#e_D_5KpN-+4)Y=C=AgwECGk zSx1NB+R7&NVrpky$!qpp<6o}}N;#h0PoHnTUYzZSjd2c!ru+?7&M~!Fd>Bu;a_)vg zpLEaSX;;2(RGY|l^Zy%KuS?hY?+@)}K8JVRO1GEp=Jr(SZ{{fEpN}zX@XSn-y%GO>VDnszu`aOE_drp58@Sp_&r>5Dsn=%b^ts5rQ7q5LnCk?8 zbI&=Lxv=;)!lEWl-BX62!#sb_8|@q`{x601lFaocR$~)*O^f8duH-M8_pR<|YvX<+ zc{OoPTicq#$X`!oj1=z8*rfWVV>h=P#w##xLd9AFS1lxt3qy|6lNO|C#OF zKYP2aP3oU^_VYvJUnc$h|IJrD>@y7b` zF7e|v5vTiY0zcj*e!OPm9P9t@@g@HIH`9E6cgArkmz`YJ^2NnD^O2l_{;|Bp?)mz^ z+G|{l*l*oy4*Pq9so#YR-=|s!J`|r6Eqg4L5?|W38(RIX+0~=YkNYg9i6c|)LYU~l92cUe<5W}g2$ zTn{y7y)G){{w>$YvcLX#DzeC4pOVvm?01S@@ZSzj{WjAbns2+i7U};BeJTBZcB9;f zf1k_Ey{~g!3%XWXr8Voo*O{!FHLm95{04LWeA=X9F!EOO9`4utb#8QRfkZ}IdL(4)}aipKK^Xrs|+e=-{7Ia(ju322lZ%|$+C((wpks499XHga{G1x`!+26y z+VQL%nNI2jw~Hnd}$G24_K^P^wp$a*3l+Q$5`Ps}dnFJ&9%!|^${j3xAa z8e}o7SgWBe{n}b(OtzLdhl(rx5=-XDacP^Q5nJ-ab0S(l8g0V9_3EWwzj|ZRXT83u zF&p(;1i#FWIOk|wTg;Q^#Ekhi@=-7DaE%NGE1km_#`VTzy!HCl!>V4tX0fX0BUP{5 z^Vx4S8n08Qp|S3nC+CO#SZ~CWwmhGLX6@@?QmlJw_U5v_M^X4zvH3f{N`w*(O4tLqUC7Hvu14U+~2r1&oSvE zN7KHIuC+R@?ZZ9A#%6U|>sHTm);Q}-$5kI3pL+s%?&*5(#`V*zJ?F&QY7ER-uM<{J zIe9CyeR$1D>2v6aFPrUu9QYhfuR~U+zAYvkgK>m@Vz$lNrFwUhWc=x=qJ{n zaWN+1k+QKh9P?rITzkBSkJ-iQq8VGp*o<9hLk#p@(8fbK*CO++r;q6rcVfo=jE&d2 z(0^>cLp${qUIVQ!waNV$^c&MtuIo8vLm#@PQ#PClcTW~LL2gW9f`$g^JNUg#oDpPw7x=}=E-^> zmMJ~`sZEY^V#0BG&iKN9w%(~@{4qNnpT0OganN}gjdOc1XX_zlW3dQrI9J^77)Pk1 zoV6CyX^eJ`!v1PQoWlK*Iy)a4Bl8V)#Es*`bnHjpr=wYaI(7~@ZRmq}ur*`LTw=D0 zR}MY>vgw?tj&+rLT})5Alnwi79jRaDLb=up^*pz}b&b%D_Mx8G5GVHGoZ7ysW4@t| zb=rqU{HZ67wr?04`_s0b4P#^e)`tB;8RO#k)=uY@KDhQc7W?+25tq?u;rh_Jp>4{} z`s0`>JI2Iu=`%;ux#BtTVPB5J8Vh~okge;AW zXu~meeyo4WIcHX;J~ZY~&pz}Y%56XDQhH)e9O~I{Y~mjC!T!XIbr7@BYcBC-oQ#*Y zF<2d`vuNtIKK8D zY#+wLaR=Kk?34SL7+15g4z`cRI@o^oa3!9^l`%JqYcqW`R*P#h{p#V`Y=4VSGkrAH z!So|mc5SonV;FLO;5y?vXP=avuEo$N*Impn?P;sm?UaojpS5{X9e>uA>uxai%#CxM ziX+5}c%*D~E$6Ud3~aWJ*iYw`eyJagruXLBf3SVD4hGw=Ud=WeYwq)4F3t4OSO?Q@ z8GLh&i5c;m)8`my?@UmJ~;;CTEC&3c(eXudY#*tjy~9kp%$g7FIRC^w zw9~OT*BmcpqxS{$$+=*y_oGcj>qDbF%z=FvALntf{j{FxlWj0#<-Sj|{lfT|5A))f zgUPFzeqmnC^id3R#G`mL>c_Rlx#fH^2i8C;A8V`YtXX^dW=r`_)s4nK7<@TKqkbX2 z&Gd=k+o<0%#6sM-7c!fuacuh1xv>6tZ$dfeE9FD+PwAVP zqi{@)N5Ax`b(HeY*lEvvxlXJv&aciDF=H+%8~RbqQZ{x@Q#PDO#-5{b{8&7+A@*$b zZ0M(+jmATN;cJ6%T-xfo3w6YZ_q+7Nyf|lk)|Rr%y^i{noyJC+dUhO-^P+XjJQz#L zZ_J(;rR+5h&M)(8WXD*WwN<;p`mJZr+;cR=jrrD#S?82KxfeBKtDk!aZEcOHKgKZ{ zjn_8)TsPOG%4kQP>ofP~s?#;4F@}2mJZ{P#>(J^#f1#fHBjaH#tS8nL`&b{e(Y=>) zt7AOeFRhGzXs=_F4{a<4p-%fL2BDr~+VRMrtlo|n z_6^4i^`UR;m-`v(N#}|4m!s);S~sjq+BULNf5enN8u@Evr*Y_YN8{lh&9$L%Ex~zc z!@jz9d0(%%=xb?<1M{MueR4GV5A}Lq5z~irVEYmS`sElJKXIZBW43aQk+`U>`et1) z2J+0y+UPpbKE#8*mCx9kJ?dZ<5W3gp)INI2aKa1 zjlP+awWTb)R12JKoq}8!P2;7UdpLbqIme(a z@nkNcj$@?slq*(>7xPiPtS@WJ*qgCapLP!F`Apfxa%2pn(RhubK9;AoVV>lf2XW## z>x*MDPS%}`EoM)BJ$s80ebQEO;(6%b+7HH7eX|eesu|xYTdlW7K6FgYM{Bp)oSL!M zF*Md@`p~wXJ?C2Y8tzvd!^W)nYhBP6??*?Yv9?rCIemqC`s2Ec>1dmyaXqU)))~jL zGTL!nTbbSyXg}Q(a&KpCHAed7T3~+E$80!O%7(EKE88yzPdV3%mFxOo-Z>h_rf=2< z_s?c*Q}*mjo%KOpuLoAnxR?*)V7*wK<{8uJd~0pkemVTGv7h2kU+km%td$e*l#VgQ zbc&zuL&VsQr+ST3?T7hdRd2T*Z+7P2=OdQ^$Fvoz*D@oD0Tf zb?ld;5mz>=<2hx-*2>w3jsB<$^~5T)x3z6`ij$S8U(U;9v`J_^X!J`z)|TrbCTD!~ zP5i<>)Ug)o>BIG4$JAP|GCQA~Ypc^7Z7o>6)`pcaFWR$NInP5G^RaVJ{A?fUIgiYl zwHWGc>|sBxIj-eU$9^$6$7x0v_SN;MIB89CF6`K$9mnEziT2Id65E*VILP-wn}zmf zv^i*;>jOPi8S9;~hhv2}+nB=|usY^Lo>+5kn17DO7}<~KiYIHCcKv9)e(CyGAB>GY zXvcX-*-@`J^E|Y(dd9)ALYvr_#3f~?^OSpkVeHf|Lrdv7$J8+%HsTP&AhhE=rEEE7 zJ-x+&wtBsZjcaZ7IaX|3&MC1YR=Nh54{=khEjHGkb&|5RQee}9#eLlKizYQl|H8(jJ@s&v3X@K)HkwW?bfs5{4my-4P(yHm`5t^ zMtZJ&)~8}y&sPdF=ARlr)`z*&>%;k=jm^EDJ@4UiG}a~OU-z?AOq?5zk)!E)s@KP^ z5#qx>G2eF0=^CLO*9dWF)W@#VX6$tgU0coc;TVnVX%nualyBPFd1_>**AK?Px{G0= zKGjzD#n6^^ynYgQ#z3C)XxAgx7iGkXwpORtBF4gewJz;GN}tqIm(tt(Q#SOWYu(1c zHLT>4?dYH9v`^U*L*kv%(+}fM>BF%?yKt{!EU}n# z$ThE+4fVu^SaIFQY&d7OCSv1QJ#(W?%r3RJr0j_`edlPzL~$W@VIN{b%vGm#M>*F9 zbBpP9eq%cA8`Eh&`mU!Zwj5h)*5X3{v3d=2(6NXu$0H6Yn;bgUHT~ML)CX(H#$;{S zhrXFl*x$}^s8ipxVPB5Hx?zmEX2L$Sp)LD{I`v1J9E~}rY;;Uw%=NDIOgVG0`Ke!< z3u`iEM_=48X;1&5oy{Sp=loL6Jj1>k3o(l6?HuWTk@CU$RzEq;xwkWBo)fpQALHVf z>_eT-QD~^T}^jKxD6&L3Mn8~Ukdqw&xm zaU)MGVm|BXxE{j$06s^G#U9!bhm@@ylQD9wG-Ipx0Wn+pR2-=J#86>?ZbFNNO}kL0V^}-(Wj>58v?rE~o%6z6Y(K4!l-|~Uj=qYI&Yk9>c&J?QVysri7_E%) zlF!j}POP4O7-J}7eOVcwVTC+v*vfd$@rh5UWBfMPP|w&H2W@gR;>AXvy6*aMJ`t@C zjqB2mZTkBreZZ_7z_R&}e+piw3#FMx(=4NqirjN#Iac!nwJzSgZ zZ}DlSkH$KfeynNM9qXOAaqd$XhPK?}Q?~S_dnd8rz7n$yeWvUfW6USle#|fJb+2Q; zl#Lyqxu4XeE!T4+`!HT&oQk8FeM4)2ep!#YXV%*{8uihdvGvUu8}+MK-_7>VF^=79 z8jY#34yNBSjKMi3X7oSFpNII-jqa&jLo;?dZ;fml>0@Ksyi&O|vQfXy*l8|}Y#ZtA-b7pa<^05Q zXr$NsEBdVGhqcJs;@(xyF7KGGWE3!|_)~+><+l*Z^Ho7-*>_+3#AIFZ_QKmT3C$Ehu+gRQyTl%7XJ-zNh zDVtc$(Qh+(#B6f()p{U}*(e4nJ!?w$4Q*7o3BX9qW{Oj;r;XvSpmKv)A3& z*v;5*49z(;p3Q-4AU0O4w)Os#aoGDV))ezi={a7G#(v>*tJv6T&v}XIx$kM6^Vv~o z!+we>G0>U`6vG_xC?1Xaab2>;IH$}(v54gp+Oj@Vxm#P-0sYmpPt}daAB%^5G-v8< zy*26=;>$c5_0h3%*ebq_`YnSkvEX{5|4C@ETxdu6NoYLhd^ECGzl>oDTC;xZ*~jJ~ z<~N0X%$72po0wk5%weavrtD&K5VLLMix_hcV_fvfabtdHXZ6H9N8|mAUK7~Q?%niB zJH2kQ?qj~2v0gYrFd)jC&l!w>lm=BIYxvkxpT{AYk zUg+H9IOn`DMxL|3?o&M1IJtk(jyUi# zlq=?nE$y_A`cabe7S;~&(Y(krHXAQx z%$JmQtXHe&SmArI>YsKg9dinOk>^;}zuK`r7(e5%dY$(ia<$QTtsP@$tjw2`Ym;-q z*IO}r`pwZeuhbJi>yL40ZPAZiLz+M1$3T@?TJgHK8lNuWqmTv za2(2rZ72`N=RGQYz8#IVq4DH6XJ59IAKjlA3-JrbBCebV8!PkR7{uSo8JE^IaU|aC zYq92dIU2_a@2%_gVI1@yvms8DGe_F!c#2<2r?DztVPDRv;t{i5 zvu`*y2eVHF))HRc`%VEP9>66&7HDk*;t7mI*9E@$V zKEoJU)7*Qwt~m!56J1BdoUw#@#Vm)8=iI-;{#^6Kl6^_J=Mp#iw6^MtdD!t%cEpJ> zajrre#?A4V6LV{39QvteS5Hq}N^j##*)V6~6za9Mm>=_CPQ)*?Q|w~3%kg7*aSnK0 z3iaU{;aZ9HXUvR=bDpx{81&Eii21O3)&{S+F+2LuYpAY?W^5T_Gj=f>#=|+W@h}g@ zV(TunA%2WCCg+|=tm^4wI-OtQ&Hh?1Hnvo)gmI`Z=BM{SDVrQNtSOFX$5J1}B1hw% z!bV)`*|U!6tC3wZHuROF>DZ|l>)CJ}F^8}(`Iy}1ZRf&b!@gXjoX60wt@lu8eTVfG z+HxPzI^bBLUVTxnSd*sga_AJtm>scTKJ=UNp|!x8O4-=_^>v`djy0_7gLzq<=EPcM zEGa$fPi=CXGcS(IbH)|+v+I>Qu8WwRj?X;p{O~*$C&y%*Y9F(qPV1|(Zzmo;r;8V#PGInB{@4jHS;>4$l9 z4O=;VFrQGKLqwZ;4u}i=QEzoAIpdA#IJcDBc(~3Nq0uj6Bknt(O+ecbZ9E#k zd(Ik&^&d)K9h*50W&EM^XADE>KbXFpL*mc%GMIdI|7xWV>v1ss!rI^(Znb~2eOY&` zBdw(z=iE1J?a_wV zE$aOS;|TqQYq6efSQp$|V?JqTYa?aHzP3IZ*=dc`v$J)QvJ3HPBGHJY*u>xugz;|Xgttf!P6``UVHWT*33 z&(79U$}TqFDcf)^Q+8pE^4^+QrtHHSZDb$TO3JUDOX6#5CDkWZD=Ay+zg~WqyGq$?_#cao6ti#c!`8FGLUo`&i&SbPnXnHTsd|CI5mvOQ$dEQ&n z-s+hbdDfax(??sblW+WBteCA_h6yQD}V4JPnQYsx?b_Js*ccPmE4RBYrc{h)Isd z`eDBH`ZFflFpgIG=IE!mGI#poJx0AT!y7jv$4v@U(>e6LHN%zeM-Aoq3c zlew=;pR6IR^>u}(*7~~gr?sy8$5881{SnJ%eGw<_=c#>tI&_?ugVDHub3a~JzIk0} z#qTuq<8|XOH2PqCn#W+SMPt#g4UN|!?VrNIUZa}H{|xv%8IAV=IU47fW4#59_Y=Hd zva+S%m!a{R&3gr_>jzJNp`4$wqA%6chxS{7bKa-%UP5KelXGqF#r6l!oJolt&pFSW z7uFNy%$@VDd%R-S$k!b7q0L;hdVYu}Z8$djaBg!n=Elaj!m-0Xw8_!zy=XIi7WsZB zgA)5jet3V!F^G9MpN#dGIy%mW_OtWDIGe?k7^UV%_oZfi&4I7j{Dgi&tYh=js80;n zX8JTUKi1DO^$L3h{MVo18^vN~0H`+8b z`eNf8b8SsSqwWAS+Ome;fHo9AjFtO>#-VtSGTv!uvwdUCjGsL18CxSvZS3sFJlHok zjr`((Kh?`PkBiV~!#O?*Z5bN(P41Pfg`?3ZZ)8Us?%j>-P7Lfg9>?H#J!mJRaa`K* zT>XW1CwQCF0z2k$JX(%MKiZ%1shsD`S;xw8uCf#k)YF&RaUWyc9D{xoC-s{{#_`mi zG~}6s>X{$si8xp}^CM4eId9w}!#)~=$~763ja=k=DpI2L22j#!ggIs0nAB{)}m z%9)4q#EZEzE|rCIrSa&TrtHEwRXdKaKAEe^)vxk==EFInJ>wyEs$<;LE6-dt57K@# z=0QxzQ?Gfkuj+IzVmii?>SxDSU$kW(>T)!Wt2&)`&6{?dLyoUDs^dH{UzO7z^E}DO zI8Qkmb(GVW#g%!}Mlt1FsejceuW{zyUdLq|lxeN0d>mwR(Dp&odn=yPo-xoL$K#q} z-$wnk)((X&V`ATw4;w2nRo{v)b7p_e1)I))j&ofrlo6Lu#`rZ?YfCwOlB!R|j`gcD zje#-dX!OP0I7jryad}QXu_0C(3;kG`+Nll4U_aIY<50QIukxIm9yG2E$~gW+w0<4*I}9&=)h+L!(*oWHmai!>XcXCIb^gYWo&lbn4CUzzG*uStp|oOV~o_ZpZcSW z^G9f!44PtQ0QKW%g_Y=6Zvrl*Yk zi9K;-KfC^zr`0J2R<77{USe|kWIbqX^ucrWtNqoE7|@1uXziGX+Hx%IA6ui$f&SQZ z?J__5)Ag=%PG8nW$JctGp7C&OtuO_e-9Ka;|;iOr5=tri{L|e~xoD`s6qq zBS%x7*pgplWX#Xb*J$uM&-4+~)35rZUgwm3LtW^bIHmfAy09v=0zL!p-!&{#ESA9Ew;~5$1$~b z)Cc`BF4hUpS!Y^<>XTzpmZLFd?x`BH_Mx2Ps+?m{N55KwZ8+Dw8HcsyIrHK8^kwz2 zx}m-H59`M2G%m)k_KbnCGC$IOH0m`zt`YLYKS!ev)iXxQnVZV!SJ!c5FmE4|Aq1&#j(5xrfnC<%$ExpkC$l$8#&A z4Sg!!TrB2eBVMiR<&(61%b8PxoJDm&K_n>LKT3abQ&IfID z&sRI<&3V?EVQ!2^=SuyPvd?I=98K-$leiE&>NpqFjYngAIhxvXY{tQ{*e^$;J^K-_ z94)lvxRkRmZR*()8^*#pi`mf^*ZC4}L#lCy<2TAHw6B*NsgtqsYG&llZaE1T^*`ueEv>&b2>lisR*I^uab*AB|$@gU_MH(8x!l z7>EP+(xKu|&qt#em_xn(&CEq3AB|$L^}z91zeA~qn2$y=FbA!NSpQ~msOO_m47MIx zjiHf`MlsmAY&C|Yj}6;?vtmSB+sKjQd)hW^+ju3 z^~}j++8uMUXg2qZXtok&{qa4E&w$;ll*`GD5pIL=Jx2@Mq3kkYOI6$BVcRX-sPR30 zV8*KID5}OeRgVO{oiHPN&Vpil?Za$#6lQeKStsX5pDm_4JGEmn*KZNC*~OhpGJWp+ zB+4hc4yTIIuAULA*Lp_GUgw$9+2{4bjFj^|!HBI-b>c%87lG&&C*MieN(urjTDD{Q76Ran2QPv^a5+cNg~kw7;O>Cz1cE z@R)cR6M|cu3l1>J#rlmxGQ~;0DUywSR08m~3Zs5!^eiP<$*f#nHFiMbir5h?l(R}> z^8SQ;VnRMCA>TD2pPZ1t*2sB<)w_Mh$s8Cz?Z z<#s$Pw|!V_JJ1 z$I5gpE3@MfNA+v-vvND0m0Lf=G3Lk0tsg5V?%LP-RGE!SW!9I<6nEt<9>mjPK|UOd zxy5i-c{rxZ?Kmp4W2wxJN14iPepYVBvvT64eM6sN{Aw5aqMhQUHkya>nuGFoEMm+# z49Bx_JEoQEI98@(S(zP=F~r8Rayy=t6EE#+eX7jjuQKaPWr~;bnuqe5gYtGP=EXfb zhL_6inATp$u`(UY%ItW|U;WzrtlW-g<-|+-TAwPj{#0gtsZ8-wUh`01b5P!n#k_be zi{YhmJEpbQajZUAOtsmy4_BL)Sw|=agIA~w%Q)Skl%B(MyDGtgj4$3PI%G6eIH=r? zY3;2a=B4&FZY#HbteiM#U+Yt4)}P9(FO?|{$}0}aD-O!rv6$DC1P&^J zjoZqtA1k+hVm?%6`>RZIRbF#d{tU!r?>%3a$W`Tb4CbnG>xZ$c{O!iSm0LenZvDi3 zsLb|PndYjz=BoTM#KM?)zqkmEwXHJBLmA@=WxOVZGVZ&fjC+ff5pT;gCd+GFj5&-e zlrgSQ#<)Tm;|gVr%gPv+0jQ-5-xw|ovA zpGfL>dd~6moc`=N$5LK>DbJYs`ayZ>Ezfw=M&q?S_4Lm^s<*u6WA!=)?HMrZrB>Q%}6D-tyEFL#wwu^~BZcEl)k?i+hERU*$J!8*wflH>|f_dC^E7 z-zmp`$nj`7o+HOA`j-Qd^U*vd;9KR*UtL6B(9Iuq)GjiNOJS>y* zP38O=Ie(>`pDE{`m*eSjyhx7M%kjf@Cr&G5|dOjmZd2yI!8Kak_r;%k8%KPJbY%W-ph-Q9hq3%wx?h@Uxa=b~7>xtbAIi4rSyX3eTBj1}nS4+=l<#>SfxlE3~<&n}2&^AHa z9Bpf~F0@yp?SytRTKOl^w|`bkvkd)~&LXY=e{@v*)1z2Z)8-!I1> z$#FE}-ko+Im7f2U;|%F@u^j(Ljys6;v2y&Z9RJAUeD=Ia`fMq73+4D(IsQ|QyNUHX zUcaVI(MBF6=CJW`Ik%W;|_t zpS)!Bt4ECQc{K_as@+7j@fjzda^kY1m%Z&6i1rlGdVG|=x15gL?x?m6H~X)0x$TAg zJEXfjYU@?yLwd^3v>h_>lZCJjJF>QLp<|7Z^q;0c9);o0TLq;q(WW>BV zZJ=}7de@GbncX%fTQerRbyn^C|l{I6onRa#0#Pg<|^6a=N-yPFt1m$PpZY+g| zjL2!dsB-I=Ygatj<88*Df6f+d6LDB?)DCTJ6F#}^AA82bPg~_S@%gf8WOn-wyB{@o z^bg>9`}uO5&u}MJ`N@Fab2z~EUnEaXv56drKQZS zf(L}O8bmT9kIa6G%zjeM>}m)rKdEMxkDKx{WL5~y97_S*d{W(fs#q%*eKs+4b;%kUj$a9+W$eczpO_4MF=autVTOwoMB!!w$nxQ zD~aevm`X%sTZ-r_@PI(REP>#JJR-Ue5&gOv(M=Fy8GM7wt$bWN!uz#^H;>ExKo`*c z63|y+DFKmfDWIF-0dZ6$4xErjK)*vk4^#uX1wvG>3Fv_V0sUSA`Z_EnAhIn5^b>eM z9Ct_@I3bUK9z;NYs0MT=guM@ssr&(Z+FyFcpTFYVp0@sLS6t9@0DAls%F4sgT+qWE zu5J5kSNyeS!uc!SOT$Nc+NQ~Iw}&L)yI?Ey4vVV@r9%!7 zdUwf-u?yN?j9rXRyBOWDyvR2gZKLhaTk+^76R?#qixID$(zXo)Zo@s6AdOeQZN0De zm@Vhj`*^vg6gBiz&~RFV8ScJ_ne#ddjJZj05wA}RRtMR^R>#}6k^7)GGFILPE!}3O zzy0~ILq;6Yd-66|%vW#Hw%bX}>P<2XPg@ygF>ZA@%wi04YIT^S4;k^6-ZONV(>TmA zG7L`#JIo2lraTFFfb0w+Ge90gPUx7Ky{01@-;wRqk?qjovn=llZSN~OTupDp`FTwT z*6Akmc&Lo;U~%IdbF~xBFXs7*p2`k5{{YX==>cR|*ubd#O7uQ(!uiX`%|r8(*w?{W zCSwpuifl_sO@{|K+D&r733((n1xZcr$R>4U{nd>2h6>rbjK(md$wfvJ5&kA^Zplt^ z2{Efmze|W&`N&@4{Ns4SsN#*c>T;3?T;DkJqIsi%S*OBep zk?m8>Xc1J%)=bBKMMicy_H_x#bnN32GShLOM1B;UN#tZ(ihLP7AmAkuFiyxL^1~7N z+>UH^M|NmOc5pTLlcDY1-cHBdBKXQ|M5)tpsEb~v<6swkd5kH7c3mG`L|!=xA!06gsN_ZHz3=4ibPjGi zIq~-53()gaUDD${M8aZPRJvV(~!q09oe#uY-u%>&p=hXxKAlk zsVp;dvUG5{oG!Us5BHJ_*_Lwo8ayC{FG>nHA&*?%fn3h)$j+!HQh~fSku!@#?3|o2 zxIE65JZ^?}$%AZ5d3+BZ5dInoA1CCI$GOO3MMri{NA|92Dz`&byTVr#sZ`D}bMmgi z<#L|n^8esoav|GNEEI15H=A{b4k zv)khsy%xI4_X>>uTQHgesbEC5C5-ll2Vk^2h+sq>82tno{kS9hVHKbm&Tbz^W`fiL z^kbKs)X-f9pnYN4`_llRy9$784S64e&krN`%%ZQm;`rGx)p_mc73T_UZcyd@8=9 z6wogm$ONeV{kvY-7SQ{Bam4-$y2@_~#C|P^9RaBzMz$ry-U1ImY$1psMjnX$0f_ys z3fD2t=&g<{0jY)Sccz>kGH@LW%iaeAxE?CtvgPD`G>_JCbpB8rt>dAqJXoOhM?vcZ zNChpjEunP=JOHheKm;xFK7>yeJ^uT{X_?(EKV660|OX zRL~;Z5?Y^t2cUI1h@eFtXl>XzGh4qi8`-IkJ6Aco)s9>RQVZDnoyGpOac6NOel;w6 zM|aj<05|R|o|O8IQePwC1W!tvN9>dIzHui|A9!c}Dd;MrJF9o*8+9_#YakWG$hL&o z4e$U*p8*lX$OEx41{S+R6*8c+$w8#Ukoq^Vlo!R!C*>;`TxGHRS zLEF1+r+KKpW08AhdtYOGsJ@*CkPp?z;anf8pIYys`glp|=NLqiBHL0@zl8@Rb+6=t z6Y@xEB9iLs%y#L_vT8=Zg9_Q2$A*1HMs_xLaS3rYE165kJZhUHk^dgfByzGXMgDhq zK)?@4z&Ig~$oE9#yLV>0b!JmKv&q%q{{e07bnIRPU)c>&@|K0uF~vnMPjM%^=;bNy z!0DKX_c%u2U6SfM9eYV?k7FoFjciM)jT$MbJ*BCUM`|;X+KkR@dS^DZn%DYJA!jow zGm57SyI3WdE~Mfxh(3;7FHA46Y|p+hbauHTi$H1tI?d%KHz;QrfR2J? z@0kHWXB7b1GVwlS_dF$n&tm#ID~`|6&{fVX@Oiu7^A<=2AF?gsvkV@9&#@qa4|(8o z9`IS&nJw?k%2kL?cBZE|aws{p;**`4pm z1t7Hmz2D^~HFT)~=smFP{a^slr3FB?hP)5K=fVg+@1?Ixu%^O-zd=f zx}f!QNChpjEuppDC_$?OM9?A+v__U@W+O`3vz^(~o!P%SvnQ&^^}?Wc{Zj9b{Y$1E zemHDIsd$Lb!ROYP>{TKCbcv#8>gv;@>ujeDck_D(vTnsrlCG zP8hYaeo4Pd(Y7t8>sc?^dwQGy#>1!*r+#M`3o2w=Lgn@F07nx*1Qqf?Wpkj?UdlEt zWt)_;jZ4`^rEG(eJ{8*?HoaSxdjI5s=_N4j2AEAtZi^={o8VkO2e@&m3d}~u=?1V! zV?U~}2fvaB*_QHH0S^fO?Gipt$Rm%L$YVw+n_kMMma;ud+3wX;R>Gin zRFFJ*_9vbohnpo-n%esQ zg7GTv8?f~`NwM|4SMc~Nj0F#}E#dJrJOGAAL1gPA4?I2uJU&>;K2XZuU&=15g7FNr zz{)JL4;Dz+`uu?ZmDs(y3gDSao7Q=JJt={b(_$Dt)1~ZFRWLGWft8uq>kB08 z#9rrskcs`Ynb=P`B+SHqUJ`i?97`f(TT0~h@PI@nO8ht>k3?=lB3~|LHue67&NI}o2~Vm^7bSkJv1Roq!)$ja9S%&Lb*T!ir*;$u6*0f+qc%q zyyY0Oa{GXJbCP1-z9(QTg0X->wk0s$1`ojC7!a8^@&Mz<0ONR-=8VGkupMWe~2U z;se)r`)T8cW$!H&pYu2emc73$;a1Ki+Rp;Lw@9?&J94pB?kX~^+=+9%=9OJWA5ku+ zvwKSbXW+*=RzO$zWvTkHj$a5yDGuYvhYd_0hGp+VrP@2GhYd`=qrmiA1JnIxWByG9vdifB;W%WM zLsxmIfb2nm>?4p0WMo@{>{IXn$gTtt$jAe-zXP&IO4(nlU|r+vKJCc0AhlpU;_{UD z2_7?GT?fnFM}wMrtN_a{9`8dgVtzbK8Q_7wyWlvTiy4jiD;>g!QY9V^YKs2(eSa#olW$$`jwe>WztNLWl zLgal2L{FJ=dNKmnt@JyxE4l)|30-BquIdUL(Zwv+Kq_#NZ3(Vl!vh@s3`F1}54d&! zT)kb{tGlvoyRx1xef0JlXMLX|_k+|T*4yRo3%F73Y!G_@mc2W5)!y>%Tp(8Q9c2Z+ z8czHN(kk0_$s;>?j?)8qxM}^Cj(3hj_B-e*I~9=aD3JXgQh|(YOOX8o9st>&Km;=K zfNWPlHnA(~>&kYi;`OLAeaw-^L2B`u=u(wMIK|-gf3WO*ZGhL50xw%(-iK6JpMh(a z2weZ9-zjmpo`A0M+5)c00@ss}3S4Acg6kC<2wWS12wda=*FJ!2@2+fGSGHGIwnr7Q z&7JiYj%*21i`d@Cig%u@uvrGNtzg-^Z&&TT_pAc3iti{DHqF5xdC4D3cPHEc^?AT!3M4aBXI3Rzw_d7?F?OIZUNUEfonXZ0vFkq z;Mxry09PM~z(pQ#EdpE%yRsv@vLm{(1y#ge@2q!sWDk&9#1PkP2jETY~IhcmQNGK?E}L zfb2v-c0yNnTvxWFiq|2|^iW3*1F6O91edB**fN9HY*_Z56yUY2z{^&c_aSf{XW&{A zfol%^E{nr87rM$x1zbx7u6d9OTx45<>nL~tTnj)1F7kluU4ZNCuI#L??Co9I=~cuQ zJL{tzc?(D_VrL^Ot+3?=vA4pq_nfZU_d1prh*f+?sj#yg>;l=_4P>WBAUl?hm&YMH z4!X)Y1!QG`?0858GO{f}_I7vxWG8_LWaI(a4!BQ!Pgiz+S9V?%uQQ$LS&qB|q!zFD z00O+PbAH>3p5BWLUhjlu?}Y(g7ZrHf3iCb$uJgO9?+u*?YkhA>UkH`y_M$ji=RjAv zut4j5g4S|K1ue2Iq4fcH09x+`5wyqyt&gL?uIS1>(v@A-m3^oy`(PEbOI(K!I&vvU zEoN7k8e3&B`w%R9KhahDCgG|Avx@I1HTDrxW0#p4`;a;RV5HtY%t2Pg5xfk#$|nj0 zuM`9?hg1+G+Y*A;zylEcIEWxf9teIG2!5t3yS6L4rYrko6~0e9>uVjk4x|>o&$!HG zQ~QE}?=!IM{d@r57Yg`n$$1}Aa@QKft}*AIjG%Wt$M`}Vz0X2d`Fw%i=LEgaK`Q8x zZ3(?K@Bs8GAc7uwp!YSPcT-pP+-^cXy0zV6a9az@-kZB>AEn(= z;8yV+rR=`!z$b7A>Z1G(9o!NJ<-5>TZZ1Hn2q^yzsenSZB~b2!2Y~Ve5CMfeK=~Fx z`DPW7pE{$v9QheYEh67Em9*9%ayKk{za1d5wm`&IlJ`*q$j{k-Z5)t$psRel0OU3S zEMnyD1U;k^5X)O9|Qc5cwA@d+!Ml`9*<zjbB*+m-#LEBjLwnZ?ldKHTLVVD8EXn13tM ztNgF86n>QFFCHVl(ID?P<52liA;j;LeIxzbUXMz4$6z$cj%-WWodOS-?&BpXoRCL$ zPa(S}yRv_FWsg@=I~6LV?NXb<)SfI-vorTki1mXjj~D0ujfAHq^3&i@6sI_%Cyc4s5HvuCTpp9^j6ysY0{eZo~4+3ogu&dUg#`;S-^^YU!n zd7)j+_mMX0W@zVQOv#aKOF3Q!4{-E;New6Dkz+e@+_XE}q&wTVTc2fJ4i%C&v$JWD zpq-sfTz*WlvT{Z>_R^8ba z)%d>zgW3t|DB`b-F%$HvVuC7Lb;|=aE}bn3as8#!B`My7@gzmEEv5J!ctB>iNM<-8 zj}&)AiraT*+jVE-y0fv}S$8$X@4}!q#qCXs+nE%{6}eQ#7AbZY;z)`Es&FSs^mdFY ziIQz8(YxUR`Ta=p!wGpL+J{7U>CUq5Z0Bl@==hFusmvScI(cjQ~`R}+5O3pKZDc)w40w|{?^W32B5#dvUkq_ zpuGx!><@fq zb!RiXvl&&0o^htnI?}dL2+=I0q&MXU8Hh%}viHF5+D-7F0-}oVC^a;*z@;*yIIq^w zdUSSB9HWuYRSqmLIzTWQ1*u>}wk3=v^a1)&ix9?^5q7bLUNkyjoHd==iO1$oinG98*B{7J;lEQh|(Y zOOWja4}k2oAOabAK(-8!E$ztccHBuE7=vV(=|c>X~2O8m3{2!C8h;35yWwjMh(d*#?{%dy$!W3%?LdQ;CI zpy_?0$Cb%cZbYvfTfA!7a;&Q_zG~SV=ikDO)rxQQRN8T_zhzPP2cpM}Wi01m5J`$` zOG)u3WZ>vMk_%4ABdH!F)ipNj9Gh)Z&FF(rAzPQx3})0-WMn6@(H9*et7N zbR#p`*-l4ak&&H_U0gyk9hpnWOvfaN{7V`+*_I-|4IU71MFPeNc|^V^BHw*%w%gcj z%GhjjHTZ8s+q;>aj@^skE4v{|osKCkdYO*NF8apPv6m#Z7K6xikZmccJKzDid{1)0 z33((n6G_b&n@t~^O|5416R41_SsgQqjO=twcL~XKOmzvF>DX5yzZ1?Ra@|wL_ufTO5xb%S7A*hw zJ()=+_uk~*4f=h4{COUdImwy#obyh}%p`XLs2ibyPr057p@mo%1dfq)Pe zO9)6%Ml9nI%MKOxSU-^Oa6KHz4nZJh5sYnG96L%J-veFZpqQvkeg^{F|4H0Of->Tm zgg7Qv*b^%3o&8Y$z^!oOo*0DUPB6-3=cdK7yTq~*@DdBfM6tBO&rlIUF;4O@q>Nbh zK`eV!*n9Yaw8r&tAbSOYm}Rm@)8g1y;%EbOiGyOIIC=sBadZ^-k)Vt?4n-UXSJ($u z*!%mTa8sLb3qLpr#XZm{ll_|(%V82rZ@^0|6cfc#4FrVHPeMR~GGaLju^drhPxb>z z<9axdBZ5H8GMU`8IF6P$1^`{+pqMC*b%6l)Ys7sdC?k%O5XY1X`}hj`SU;5YJk|BR z6Suetk4vX`r6M0`HB_Kpu|aF0bgbEB79f;Citx$H%& zp}6OsQsFOJoh%&H;i_;%F%d^w0s+);&mL)il)=&I;OMjpdzw#By{9+AJB`FCOwegw zY%_}!Vkqn z{7eD@_}LLB;fFH#xdQxLR$*UKVPE7^#65DLYHW!Ursy(+r00Tj42rmGPI`7lxObZq zP~@tNQim?_covQ>%E6IrtTQJ!N8BjKogHv=rEs(_t_nvK6LF+A!#Nm0!jakx=LT?e zU4?y(PtZ|N06~#E;aum%CUt0@LC~?tm%b^3pm_m7W*t%(!p}81_>qlp=H=!`Hp00n z;O9o+$KMEtVj_Oj1~>jjIFwO`?gl@1R@k>!*thx=8JpmMDeiC+u0wYsBwdH@GblQX z6x~}9?v3vYC~{RssYADWJPSv+=HQ4M-lXr#%@Mb~aqkT{x<@!V7gwbYQB1_q8h z7vdy!h%z{O1RO1>upjgZQk&)&d*Xx%THwVdb?9+}Aa0wJek_Ba#{+`QI;1d!p9gdB za}}{3&&?0F#c>}C_<2`gHCx=)wdBj*uMms{Y3tJCX7b$Z93i@W5c-_D@xoq#U0Iw_38*^-TQ z-pS1tx5aVa4%m82*y4sbQokrBV(S$kpng4zlhiNDVCxgGwXnke&?oFwPfzWX!@Y3A zge^4c*JlP{Z$LBsX+|IZSwNVpGD`jWu&MQnyYQqx%gq?~-Elt+7+WNaal;&8jAA0j zJ_Q08`w%B#j4~Me3XCoB>H5r5`rJD$#wkqK5~F^7YtZ!tG}GT?(DiLVms!6QM&b2q z3BkY3&DNK==YA8g^|i3|6|M?f6ce$v90*|R2b_d0%3y05*!sD`Ug{IJ!qfZJJN<@J zn6RIX`t_?p*zeFxugK`%e+>w8RYs{_OPgB1{vi6VxfxrDd+v&WvE{6kg;r7A)eQ1&nYJIe1zxu z#^NwSpbXDz;JH<452&=OEA5o;{7Bpl7l#!%?+$>M9I~)Dsy*+$MRm`6S;fsRj;v2% z21;n7U`h&wVxrI{009wk&nT&Blo8sx2yLB8d+kcw_T$G6M!ypP)roZX+VJcCyV)yu?B=Q7jh$0U?|tAs|5+v5ZA5V=C=!{6H?o^>83#fri8#6s z2%yH_f{QXZ+7}${U1{&>6Li0)_kefeR$O6%_V!|v`T79{LEKy`y?+Kl2LuF})kI-P z@406VejXy$0lE2EfP3!#0YCc*KM&)o@Ix^XKhFaJ{5+16JS8ZDpQFIf5ta7jO8Zcs zq8B{X7roO_T^FGDkZOl7zw9UD;Os*F;HCVM;!M~CL%i2HY?kIl`| ztGMSL6L562aP%6k3P%(ZakLN!;OHHkgd@t}=oD~tQl&k`Cx}~eLGKgqvljkN(GwX zkxYW(pYwXnX9dyE$<5fWxaXc7Fm{$O_8YDWV-yoH)~vZO_9uXZG0I?U78tw0r>n$M zD)mmyaSGFQfl-|so^_ZnT!ZCZqjb8xZEI zj8ea@Y-;`LMf7WPGu9jT+-m~H<_cqda8($in250fKmcPEI0<8v!Pq=7cB4<%nx2y7 zoz}uBOxKM@{kp}Vs|K3sn=|OTC7{c!Ukan}`o&G&(zoPhi(9<8HwSFZ7q}pQn2+yrTtx{{Y|C)Ri(YeXO3G`rGKtWFHlpa5&Ssphkyb1J5|#- z75qlg$j{xrs^llPvO)9`Tz-zT#ifOA5PdYPx<6NDZV>HV*?cp-LG(|;$}v!uIz%xM zE8KYstW3d4SfLD7R)Uq^EA3w^?d6sBFFqyQkqV4?Q^--|t(IF48#Q+BhIU6iu__5-;Zchjv> z;j%4FWv)2MEWcTbVW13Av_&buX#dVzw3&PGT?eCXt5jyudRKy?ZJA;q*F#wtp_qt~ zyMO>7Za5`HOBsxG1|uC)cKeiFma^NV^di*VxEn6ojsYERdvKuV*kv9cB*ptZnv`rC zTt!VcO16u{aSw1M4vLB5cpM0b!`o;I3Cf7058~*RvU{ZLZhjC?;8r+@UO^CM{p^u5 zhHhCg^pzN%)G<&@6vG={49|({h=DRZW%ksGDmEAMZg~%9LUvKE471 zXyATVQa34skM+REkd!?*We-Z(1AQ{S#$9k_bUQ-=Cd^_T>=7Z|&LEEnshk5nCXC9t zz6A0OfF%%$i2^CX&v_9DH+PaiC?k;J2xOC#?WF8sDSK$j-q4Sw6bk9hQ|T|vg54wt z$93SVF4$pSJW{YjgM!`A3#XuhZ3TPo=2->nT?qcN!jiYlN-YaGAk+LWG)W{}GyQ-2NOJ4R1criAj4S-or>w@`y1?{XmI} zyE#c*6cfe89f%MPH)E3O>+MLCJ_d0em9mdW*^^WDp(*=dKdxP&iAv$sV2SIf+;JUY z#5LK7?tYxct4_}aVy=JF*G_U z2+ExTFLfn8-iwNrnA3`)(B{OEW8Tbx(eW_pHfB{`?@Ca48-$D#pe%(pC53Zh*vd>D{XZYT7tD^J;84s3o0*BqRjB-2UUn#dsVbZ-ItK7URLAjkT zWLySiA%kKfGOhyx%564IQa+SH#-$+R;*>qhXX1KX2SrA?T^!J0mfNhXa=T1iy#WB? zD#b*u-VFq}I$u0Qf-+pa9|h67jNa`a>~Jl=Z%_S_q@iq5+d6x|KNhYMxlgJL2+xLFWrcmyXYI?CYVcJOg) z%DyFK&rjJm`D8qYyWq+g7Tg*zVHV&mK>@n+jgIstj|t-eafbx*Jb)z-iirZ@wn7Nx z74aVl$_V5E1ae=>z9(hhC$SwehsudZ#j+!YqA=sB|@2WU$l@n(0qc;d#@dfF)ODlxp<8N43!OuF;U* z&Oupw0x!xa14HpMB-*l&nR*Ra0~ z#)d;P{bwpXf%_|9%vBkshOO{u7s{3yl>MB8vdswmS8mES$36GYfU=cB*%r7elu=AX z*;pWevaN6u$|!@fmQ~ojsmd;?vWu(qxNv(4yQ0*&8rwCI`+rQ(`~APj(t2d z)2*w*e6^`!*9@hlWo8Xi7(!P`l`J~SN=7lT^)j38<98%(o2s0B{7$&%wyyH~_*PYn za%Wr>x+o^1Yd;_WXg8dMF3O;*2k7cnWp}BvJ5|{oe8#vf7_<-YP6y%?W~>{c(lxBN z!PvpjO!uk^FX{CT7;{xdsbO6_+J&-C24x*`PGBJ6(lSn4`4~j@C0cx*D44b*u1-!{BH=gCmtuII<0nYI1Ni zmtgDV=I9#SbJqtyB#Y7yrKmbQ~;3OPT21nb1qtR9N)>Zb%D!bmN=|NAM zn}Q+J0-VA$jYd?u>5VmLdKjAN?W)4V@UaF>Dx);Ltv#-VvXKU5^*Jbegur8SQ}!tC zx!VPljS>lD@B;niTM5cJ2y8=-SDkYkUs6-XQLz+;qK(d+u%lT@!__w{TVHqL_%T z&w&7zxLcakFv_6oP|$U7m3?59y?>RxZ7|tj4FG& z&s)BI$7UcNUG2^?c$0m{&a4Wr?VT0y=BkWR?WTL=lQ@50BiU^1tlXr?W@Bdtq?{q7 z_?wMUOhifwTm7I)t$~wNDaxo)7l4%Wd`7A~rE2e##wlEr&NFJ#MFt}SpqZYP!N^4c zBW6uf7$HK|Wd4hC6T)55+*tu37YZTV4NYnZ#YBXx4+Idx?a_n~${=J82)VM#zTD?z z15b}zjzPT^r!Xg18ntAu!O2i)rmwCFuO!Y5IB``*sU?@^s3mm-n46oFVYugB9guRB zkg^f33Mmv5k-|;N5GD6c6H+LHlp8_H^*$pbJSA>V2HmZ23Nv!OQA_3vp zxOzjU-8j6QZ!n@VhN{LWW}2Uyh0(a@&I?$$Nm$@+XTk!-L@XQt1VpwwPQn6ZuW>cJQ73luSY-GLR?f8-mV2ZM__HbIqT z*Wr9OQum}p$KA#xI*N&+J01v#jyr-$bd(X@i-_*|D*M?g`)NP46L1S*d!g;k(4G%M zGaL1@UJ&wlcsfX{*BLK~=TiVCo>NTZ`RPD_=ckCnNKl67@4)l7s_Zwa?ANO7SA6GZ z;%>NH-U^&|-+-6w+*vNK1w{~)%PYaf9OaVri=1~Q#O=_2+%B@4}%hM-w)ENbQX!{R{=~sr#YxE#4G}GTyg{$PZLC~(sD1GYU zAX4|UAniYeA0*hfxqFs}aL@fF=vlrNjuzmma6~Z?N6!KQ)I5fhv^~n;=ofJGQ-S820_0- zGu^%#U5?kY?8kn;gF%qWC>5ub2g0;Z%5nm9$W6)$+;iIpq_h)Ke#KQGg<>L7TDKNb zif|HAD1($fAf;Ee-J{y>R&96jscGYBxAjhCIEAU{g{XAh>1R;W9-8Sjs>4r}eg-u< zBcCcg6uI`4yb*8y~xryw8d+r(mk$r{8uDB{hQcOf- zIS^pFCr&~nWe~Y0h)h@8Rn>N-&tiqATIroqIE7hEt4O(!U1P9V4bAjg87$TWEUHdQ z9?cqqBvu6^Ru)d8MQb&=Nn8u}+_eG{Eg`W6SA|51iAWp@1duowCn1qCNUQ~k8&uot zRog?V?ZG~eb)NPx@3aw4VIDU?u(~!5GkDw>n(4X>9)|@yx;i6k<9Y#O?vQ}U!NKJm zwb2;m=(h!%(de+;bZ(A&Ze2jDULFbmBbMtC@c(uKW z&*fN8b$jo$15RNsH&^kpPL4FV91qR(hzu@A23(qTQe&`A4iBi@q^VTyLYpIVQ#k?m z+z|nl^+M&YxGGdqY$}!YHDikHF~tK&p$+;jt-*&cHTJ9;`+^$#yc+e`8021D!@g== z9*X+cUR?wAwV7uynJn_=BA4;%I^#+#xxFsXF0XOVtC=@#8uyi$R#sHrySLOB_wpL# z8alUz1@=`n{sPRhvZBV*@JJa=xbC8qKA`8rQ(Kl4HJ;AvqvVEfXI!a;+~Z2d6tCyb zf`v1bh5kdYt-y zH?Dc!W1KLpjNehz!r$37A&Y)Yvn8hMRw1V57IKd(9aB6MX0ECUhmq3UT_tv|kFZl2 z#a(5B2@aO#}scW zHI+3bNlo2qO!4L{!>vHjt*EKD)Y$WD?3-%r8+1+G+Px)IQ}1CkqnJmkma3_@@#;1R zR&I|0+U+&&4Y_LS?ZWoG5p3tHsj!2ZirlQJ+riA8HST<)y84ypPBC-eDw#oUni&f- zch|T#d2PUB!>>Gdi=F!;?BuIFUO322J3B}f>0g}Lj)E%U*_JBe1?^Q4k7vJ4jWeo< zl*@RjB1|^5ioA!;tnmg^TAZ%IiN!85DCs}2-dx6eQ{?Q-z|Tcl4- z;RWu%hk0&1hXdR-1|ls1c#3qoe6)PZMy0y)fwXWFki=(-iG2RW^Z7^ZGiCTZ3O;W& z&>rFYybRaV_3#jX0JEs^0=Ouy!>w~G+^q(3LwIq~9f36d?l$#C4;Ssa(ch^CavLrb?KhhxsrcS$~%-yG9YUja2@E=c<%{*!7fkfNFgy2TI%9)QU;mkdr zk4wF)^l>pSf9hSnOkbWlZEo4RQ#+RzuaCnhOK|IjJ$RagJ@mOF$sYUM!@=HR4fY`o z_CcD!(e6P3fw_Gy0)flR2G7{+m|;gX5NaFiB!;_f`sWGWBfe7?)a#QQr1;&#fOjE3 z3A!-FXYQD~BdNTdbqY^otp=X9w;Flc!8(WM(@xfDJniCTpD?b( zON>q*)vys>M62wPEr8zM}@cF_(T z6@h;Sz=6A?#}rSnB#4P7S-ERlDag7jh1#~VLTcNvV}!EZtQm}Ek_nKP?c*ft?$+td zx`&x{Op26%O?oShg;_{>k($wES5D@N7fxr<)f_gc{;3t z(ReB}>!wJisYqIvNpc#KmrHUwlUGRcG$yZ<n9UsY9!!)vsNhVra!_Ejz+9FGdp?rs2@PJC zoJN;ycE#=?4d^xbmkShI=%8<{l#k0Vpy6iYimfByQiA7m<3#{~E3pC!rmXr@tPA#1Vus>2u-t3>xIM5S zZa#A*?i&-v&Dw#uSz{z_%82_m#Qnbp`{o9Fo*(yY+;Zo|M58PZ;;L06^T=;3RQVM%?!!?t2^TyBq8~{kX5gE%(lt zxOJD>cs(@3al0z+do$wZ3?Ur1q2b=`$L*O7;^vG&;(j1u-17l|xaZ*{aZ^Uzk0I_y z8terP_Je-hH{(_~nkQ5=k7Pu13pCvaV;J)LO-|>-aT{3f0zYmKEQp(HB@*}J3FGFN z9C6={lf+FKaX*i^pKY+8Zm^&9lH;O&M{2h`8Txu-|R4-}d8v z47b8@FH~{ApAq-t&~)F9iF;EW_Y=en#cg1@@A`3jU_snZBA>+lQNp;N0RZBD8YhXH zGU8s0xIb&K7d6-)`*A;uTj`f3JdEdQQR7pc5ZcEQ8oYTtHG0^WGBj#@4qDbX@TR!& zd1eUBmvr~`Sq4!rKvSW~tTyYx=XaSeLbGm(z`sOG-%9djCcl&9t4M~8ey>U=)97o^ zj5X>Hqh5!mGWrHB{UDa!Wb#KzzMTP8;5_MTkFs|Nv{ZoJMY8TINxsLcKS}ca4EQX1 z+Ut7sL6HAL=Koppf5hZ3l3bV%s;`FnIDq;DNsJvmzZh%!YZnK8WS$2R~!?50j83S3BLpYTv>vXv?a=DOMjp({nlWw zXt0<0ZRsoA3fEHoto$vbX?zV$cUepy;y)|DA!eu#F|gbfe%u~d(1(1Bd=mG{gmM1> z0L1-0P7*g|#NDj1xTxMP!qNV_!T!^aolAz{*h`@Uf4H#_QlX`k#--49|BQ*>Z>2vG zHxz#e&HdYFz=I1I_!&8cffATcR`y(^1P5I06b>kZgSG&yw_D?Ax8$KY4tlk51ysU3 z=y3z}!z}y?U6+~tg}I37jlXum_$9IUorpg;8-JaG@k?XzI}?9M zHvYN=<2R4R??U|bvhmk17{5g@w*YfHXDCv!T7CW@w)>b<2BtJ z*m%-xFI=vZmclAtau*x+erzS96&v48|ak|L~q_Zds^F6Q|f;W9r2iIJ&DMPl?8NeVMViu@6qtQ&2|# zwJ8AW?TvA?H{ziV2i?7k#jhd$_-y?-Gl@F7fxx#^0}C{I0S1>k)tdZ2SWX#_tx3zdrE~%*H>cVEpc}_!|)a z;B5Ru3dZjdi@zc956#9utYG|}vG}#bpPY?nhLnaNT|Mzc&dcVytnWD7^eh)lM0WH`rUD@R6NOtyApki=vgN5(TuwsmCa!DN{u zqXZ_~Ir2bfvb`hEUM4#@@|a|@qa#l=CObLu@L{sEBhLvYyExLNGuhRV-j~U4j&zhv zc6X#tW3q=M-4ByJ9qB2U?Bz(KX0o>3dm$XN9qcb{T(S* z&SO~!mM((LAh>!snPVPnPVI;j%wsoaS#lmb90izc9$U|h#f@9yBr`_Jn8%(5z-3y6*039+>SikZ(ZoMH8-MMB@x2*q6#h2EKPMYM7%}Ga z-U;crX)bF=Y-5pO_}y1vY8|Gj>!^7stA*%j+7>o%^e}0$rg@q#AHiH!eLKEHdb9Gy5BcRnk`XI=cYU zB_ys6n}f6XG67eus~}}`G*{!2*U`{Hv!l64bu=ztJ%r7UN?)F{7s}A8n@xLQWLFxW zn{E7>f5*7jMMW8(NaNRL8^7+~G4AzWQO0+p@$0jV-|+7k_d2&IV#yMPahokz!-AnIj}hWpgAXwjlyq8g37wvkhHAqlwzke$0qJ z+k}(UTgqrdw*e4eUgBuqjDv1I`{Qo-!8spy@y_hw@}kC@SaF#}wVlykJ!gKSp2OGy zKoPfZ$E{>;AIglyjfdbQZc~QacLA{8z5_??F@Kw5-9tMrFXJ~h{B2XmRPDXI28hFP zO7j-4mv+ZtRGsKsTI0x!%xx-b?^BtN!YvM?iiYDSEJby9^K#w&JX%_Xzu1wHmZ4&a z3XC6%o5F2az8T?sDx=PKx|we#^S!3>osp66AIYinooVJf3&OaTzS|5v&G0yhlE9?)I1&ky z%^Yz~Xm`XO`vsy{I`p#%*}@V&aqnD+W`Q(H@I^(9{cB%W{+>sxp-<}G#2v2zv+5WP zxb6++v2@P!nUn4AVK#xr*6ajS;q%vmqif%yI=r}mir>qxoHlJN#rx|(t*A@-9cbk? z_qLeRD6?Ww-i<=BJQQ&qzFY*9an0*q6zHIGUX07yD^`@&RkiO?MQYk5v>X@c2UG?4 zrBqB1=!fEsM!7r|B|1<+ffrXG|F{-)?+d6zfs0qhf_?Yf#o!L#oHTn<&uLZ5wK5=d&JO9<8dsb}BU{>=w7ZW{gYw^V{>58+g3Km47zuX8TQ z0ROeJ_Iuy*!-S3NyM9#mAE9Edn$imUAazOq1ht%1rEaM>qhTJ4hxs`Q#u6Ct@Hha_ zd;K7&5(h3m5s&&yB&r7^d;#W3VmGh*MzDj@c?y@!qC=ftMinX7r)fHlz!g*l_%l?@ zMWFB({gnGvywNDn#iB%a{(=H8o=1Mrw_HFa3S4|47Bsp|2@3MRNYLh%@CNZEiuib2 zYy>UfWn4CCMCbn-RfNV@GHx0z;14PR_Ent1E#Obw$zADIifx_qwG42yfWH*z>jceJ zDqgkzC(^>-VnM^a84nX(0X-OT7a_h47*xRD1v?<;oecj`0gE`IMUHo)3`?zw?7-`a zncvbV@5iD_~1dP#@+!II7pe#*&7z~{_*5XPq* z#{S(IwU{`(i^{jMdUS0WM9-1MRJ{#xc^_k1{B-nK^#hjH9NC6*$}dIfuQ7^-!7qS< zr%*e>S^}OvG{$^;-~1AqZwoQBh-DhZ$EkXG>PsqfHt6}fxCh+R49H|C_isw}33htm zK%=O?9C;|_o*(1El1mpbN*<5@ZYVt80GLxhg7^wNk=BeY(e(ER zX2fps#jhhAMzW&_v?oIsYKK>QsdV(NvvQVNo%ZVf71eR%Y4P3^3Ax{zDGH!d^crVN}1 z!n#a?#RZvm_a%go_XiS%W)n2JBfnNJukBA1IJ=SG+`y-?7(WIo#OnYNnM#mJs;^gWNxHa}fB;epoTLOOqo@ZU+`l{vF7t4_k8W8x!*zDBG#l1n^iJQ|EQ}It@^wcQTVSWvEr@dO)8bI!g?@cQ z0(Ae-d3B4f6^iJ4DWW12(Wml=?XtQBQI;c!uB%%R9diWHZFLKxD}q?&?NBJ&`k}#h zU)^HpiT-hx#89M1XT1=E3|73+*;0-@LLEZW`p@%q|A~FhY#FA_XSTF%*jI+wDn_& zTPT!_8492C7-RC8R*V;{*jq-I1SrQK+MlQNC%{?+2u(Q%8BA7m8>wU=Q5mqcHqPF2 zKSd1Aqr7S-8{BZT;ZIQ9eD1IYR1sWz8Bt$&*&KTe@_nez%H6cOJ~ycA|2KmU?}?__ z^dD+z#DQtB1O`$DklN6jl(i8u$`HTi3sEfl1+B@v7zXu`O87}Pxj>w5-kvp`m*3WvOD z8c?1-DR$gEbae|tjhjPsMUI>6R=4PKjhlz9Zb9T4H*d7M1(9pq?5u7<7Z zW86F(F=URLLmfiX`p+EW<~nrtk>h4<3XfMkZq}C~#zD};av>k3o2_p2t8p_42|qEL z#&Mo!RMxn83-E-Ykvw!k+lVaMaxYwGZW_x0b*u8)jr?c#NLC&5T~K;s-17!#94q)^ zU@5Jw3N&kuaX0a8ZJm|7X`F?}xS=Z6G@v}>`vZjF>C@LA;EqBN7~o1&D2UM%OX?g3 zX$h^kxD76bNeu?B8Khd06M4okPwwHXjx-p)Zb#+N@HGVMa)76o=(BT=W$w_RJQ%)) zaHPz)&*hjme9ea50m?Fb9ZEtH4PSQz1o#+_lMG)eWB6JRzP~5PyLgM|*1?M&h8^m;{wD8+xBl>WA6b9l9f>+n=}@Y=jV9x}w?8paB~PAiuD&6V#HiaWEjj#z8m<8 zS~50{1O(VP0w-aEGT7J;fY{j|M|&?G_P{~2aTHX-Z0LT2`e8PXhOW!Z(QNqp1|LIQ z&bN(zBZTPE70reQ4cIsq`Gt-Bp_Yt|6954=j>k#ZpbRz+17N*<2#)qaJRE?7W@8Fe z!ffb%gZg1MPK2(@%+YN4{l-be&0r&h=+YI69PKGQ9FK!$VZ0LT2`e8QCfUe8T(QNqr z#+k&;s2d?fm#%0wG-$xaS;#MJG(asG8|MN7Y@CCWut6DY%m84$Jsn4TDi4h~Xg1D+ zN_r+PWUN|KQTs}L65#pjuUDVXtY<`KH5R-h04@Lk+?|D!t5qUqS(&TN=fJENK0uvXA0hQU%9#kk!!_n z_UaZyt`)mEt6LB`R_v}?-D1eGVs{N<$Xu}tbqG!CKXa_uorTUma>Y)Y!ox|g*y&3V z&k|^=6}xL!H~Q6z9SI3PF`LG5o@Z3nirw|#2`hH;(8UA$CYJb_eDH@}RC6eh{i1pv zIi@mSRG*8p_t>6Kj8+hhc?Cx({`kvPBap~p1eaWICQ4}eCwM0tLX+j6Tj)xj%8@zH zIM4U^e_6SkM*9Ex2t&QrR^0omezzhHtolh{pzt<|C6<&7#5*8{866A;&}8tIJDbtF zs2%#YnM28-64ajW(|0#j&xRQOw%O1(zHPn-%1te)3up=v+?$p6|M7D2`c#+P;F}8h zfXLFp+|OXt9ac^J=;A^Z=K~}({QbAI6@I~;K5$|o^kpuo``-|^;`f+?`G;_|@wW0Y zc&G;W7QA`EsJdD7%+mfn7~`Kt%@1k`D2nwVz@eT>g@X7n(L*giSojTjDJ}m|X#4I) zJQgxr{zZ!C$FlM^tv-c1TjQ@5YWycM@q^z@`k!Ls&k4iG4YXK|9LCS^=DX9KX_z5+-4G9E6$K~FWGhf4Y?TnP058S_r&((_Jc z4(6SxWom2gM*TDIwt98@MM6ik1(znLb}pB?M$dvrOxOS)C@%xZ)t3vbD06}7k?<;V z1LTb?kfzm`@RK6sP1ArvRj;70uAAX8;eB=e=IRziEBOdhm$v>6^R3k_3~x#udUx|K zV#pj}uR^WJF~YtYRXB2ltxcf;>JhfS6wyMUsYclEt#0(I5jF`4_XGcG%gY*Jf4GV~ zg<5*>kU?kk5s>lRluiobLW=xl)*SX)iQZ~{3J4%A!b!S*%INxU0${y;1CI7}JY0i= z?)pE2O89B5-%e29?~vtL{W)}9W{zHS_1{h`CN7sZjaftp(WNW;d7?qpcm*+hf&9Y8 zJg6mO<10V_=}Vl14a#8Sb^zAfx8i8u!oz$VG#g(-CCr9?J3;+08{a_JW#(u${I?U| z5;ud55TZ+0G#eT;VBC$jipct zv!UNkP(RGZPtbLlIhqas?ZnT-&0r&h=+YI4w{W$p%P|8zn!3dn2q0{>oRjR8~)pg--(;SMhMZRE1C@r8nE#P z@(UY}K`j{@&G3g8z(z4n!UkoqQ8BUJeiNYf>pZ-QgXW^t%h19*we(JHaB`{T2fYri z@E?8!FsGbPB=cvGoer=42+E$tw$My>#UE#%wiLeyJq^Ff;NDP;MTm|6xUEej^dJ1$ z1t!7tlEol~VDg!PxW2SZx~?+d*S$@1h_f98bi866Vkg>u2lvv?;-FmU!rv4#_?gqD z@h7R%%6xoC7Y5!y@_s6?w2Z^l&H!@>M$@$mk)Xvcyn4c}GpFBE;q{02bTrfie)Ooi zkEw0xJl*NmE4bw4=$_%weW_T7Mp=Re+dYZ%E^yM@OnjI>3&T&X!EgF~T!Q75cKG)x zx&U!YjVVU^3lzN=hE|9eVeqo~W!5JQN@`UfGfmoYJ(+C{#JN}53K#{Mwsqs#t`yzC`dv9`l~ z{>!ddO&d+j6%_R|O!1Tl`L+uLo>>uQYZbAJP3&nN6IEG7vWiB8Z~x=8;9Xd;KmVxy zZ%wMjFK4iETmgYd@4 zE}Qm@;XhVut6X$gm6{kmhUMRF#BaMlWec=|cDNQUr+32!n%vl-82cZjKY)hU+q~zc zzPF7Yh=q;2xEA`Oq`EMSzNq#ynv(vcW)-6{it$@J+;&C6&mX-XJO@>O;D2i}s_NVS zt=a#Zsz2zz4I-lIul;XZ4LaedN;3GrHK{5In-QOWe*eh9)~Yn}tmY7obk!<}_BLPt zIOM+#LRAuWMrQxG?kZXh_m3E8_!GbNfQz$Xc4I`?q}v*Z2${ zaGLov_Lkzv(a1DLDz;Lyln5Nfp!1QU?lntIOd;@4l{VFyeMBe>M2BLDX(*3hwFs6K5<&mkY_&!Xllc#; z5}yws+0A(HI}`tH;(p~`Zuq)WA%Tf0C{M@?EQ8tuz*+yHEAsijJ4&E`?Q*JFq73L= z3-Lp;KzTPRN4@P+bxq#(u`}?O%=}8>HE=GY?4B7=L{&Fe8h)kU((mkv+yL1p3#4h! z)45V+YI5&88PhvNZPpYTA2ji8-+rqYL~h$`a79(MzmYO9wf`y_`9Eh$jYiE*vx$SH zkjpI7@BqX!;D01r_q#L-&DR0si`_Z8a=-C{&p#BO2d<`ks*vP?Q@2t=)*&6dnuZjr zBAiI`pKMFx7p~<+Dn*ROaLDQwsd~Sz`d2;Vn2azoCl?_yn${WSm|QGH1&N$oXjACZ z^}A_(NqW$@$;IKTTM4MC0txvKpA-IgK@SLzT1B2h&xX*u>7#*+p`Scb(Ik$|G?aT< z^QY?mj?1kcrY52-YK-IQL5U?}czAFEMb1vX6&p!rCno^{NGIYXqXf#Bo$T3AZx`b) zSJ?jm+5QU$JvTWS3h7eZ%9xu_QO`}NpJQ&)z^tL2ZHZ&dP1-^9+-Rg~b6N>~vm4eQ z0(%@6O{H>p8(f!pwL1*NA6LnnuW88PYA+*N9xt0CsSdt#(+kXf2zt~z%Fv?@uI=b& zJ}oPA)4H6w(pT&8S15+20fp*$%=pXuMTRESUs;=hIIwwiCkAE(;myQl6vxp z>72c~1))|!Ro(ZC>YUXr4mFSsRqpIZqqJM2Ip`H06~6yW0@0 z!_V2;F4U9Z!Ij7ew`b#&ZiTDir9&f|@#}~=RBlaWbD1yQ5?4^KGq(cOEg@(e{!-u7 z0CEX5)tF!w_pj}WOY~~4_R6JeczjE13ckL^l~I;fzK&qpm?-A1kbE$B%Z|g^0##VJ z9(k>9%IXcY8eZNBNnVaVc8Xb|HY083c?!5@Bjo?4Ozud|JuI1CB^IFW)7cKMeV^7=$om$iF7 zWpDf|P9T~$0R+m#8;EZ~^eKCr_ey<{J#m_S>qeNcNw3NV)yt9k&1B;&%y}H)Si~zR zO0yR6N{Z63MSO>%bW9>Hq$s_Sh@(+A9ce5gZc9;`i-Lt}kv7VFdB1gMJzD2WC5hXBK3 z0ZL;5itzOk*lmWBt3xetezGaddPQ35fwas5S%rsr*qf#Sg_=OjOd}YC2Y;Te)#?_6 z8bpN(Z%tGS85T{&`Y8#}Bk$I$TXfzlE3YTef1a()>K26eiZuMHnq67&YTJJo*LHP_ z&D+Z^92>jD9I=(HZn1e=+_`*c;Jaj5TSP$}&Bsx@)h(7BTita;44H$;P&d-FUN^^U zP6y0I4kop!;7v}r&(D4@0!{Urv(xHEzZy)EkZ_bu<2cWgEo(5@1w3I;Cy#2>+U_jz zjo?GLy>b8%YOhkodyr!)qsrF~$Ju+>_asIue8FREQo(_o{{@X}49Rj1KG=SG5nR`R z0tXzM`9Ac{%H1>?=X#GvwWb+zqiH~S%ESLju=?^svFZ2reGmtR;1U=}=}T%uyMV0? zo>A-ZL;VoN@q*WBlUs+7a{yx7MNo^Dnq)J^o%lJu=ckoxg_pvnU>DsDnfRRB|3jLsm z^NFA}*KS2`WahOtRX2ecngO|nzVTLmFqE6xK)0qT__R(|-lnyx|MTXlUOA8(%nap~ zgQbHR!eG>$+EG54>+-U$f7|$%*E6(bJ+iWPjDK@|+zi*!vACDBmV(6%s2%lcSUJ>6 z-u;LA2EWjNtKR)@2qdiiZAV9}z@6GGcOn}N+!h)URwR3yMdl-U6A7zs2Z!_{y+?&Pe7md-O$@GZdy z#8wnbEa_Vyj>qCN0w%}>>XXAHj~RlB3|ecPczu2am9^GcWC}gk3U08bh&i+U|e& zG6A|i%C1D&N1;rlu&)w!%Ma=Ai8aZDS>3Wk*O5@jZ$Xjfn44lz2q^fTB3Y&jM(`((rpjz)Gkwl4fBABWaeJ{z_e! zRnV>PgWOVac9*D|SaJS0tr+FmVN7v*7IgZ{LaQ_U$~}ii4^y9pU->N~r*w zZz-o0Tfy}Qp%LDFgn88BD}KSEzrg>E$`4WbUL0IzLs)*7TPpkW-niNPiXj+5aa8p? zGb~_+`wPqP2QxfOUFHG`sV{Hs(kP@d4g44N4pW<~{N5RDfT0GA8~)?rIrKH$WUc>) z*+L_87k6A5q%Hh!{AUwyQqh);skqepv1*CetA=ch9%X6RmRrLC4FZSTw;|LfZHGMy zU}=G^pkckPyl73~4JEXNPR5IUNm zoe27t0_{T3+st}fFlbj3v>QR+R-ioy8v4_DS)j!cp7u0BdlB><1=@$8_b2kSuL-&a zLElxN{R#S5BG7UZw1S}TDbN%_Z%71MWr9`{^nC?7fS`*Lfv#zSS_J(-fz}Z8k3^sY zO;DSlA1ctb3Cc|mjLtBt{G)2>V8ZIQu#RbC2yJ|%Y^+Bcsm6F4EhFmK`X=lKgk7j$ zYYTxbiGUqy!qyS?V+FerVe9iS64fFcW)5{&p8z&zZ-kbg#AXr9z)n>dAyCP&Bqc}SBv9J8^_bex5~y8+Q|1Lh_Z2_Y2zf* z#>uqtowCtD8~M8DC>xEYjZ;kvVo zjWbOfXPGw6ri~w!jdN)ue)#JxgJ+Ma&tuktyUO#aooq;a0kZm4>p}{;qnri7TB<_1 zm=@y4$5EkN!mI^{aw)Zwg>o6P`k`D-L5Fe$1nVai%4}MQAC*UiGKX0U4&^FpCky3j zWc5RtOF@Tn4Fv0F70PwA5I+})3gvocEjW}LsGTg78T|MG6j1ZVed}}d%FpH2Vs{h*t-b(XhPV#P1t(~yF$UYvoeUPwi6Fz$$GGP}G_BRFl2w{_sHy<@&A0zDV3ib)Y#`l_01I#Cxwctwq6t&|k zb<_jkX=L>)^)nQ7rG6HI^@j@Od0L3?HKRg#!32Ggpeq&V%LI+@zoI~2F+pD?=${Jo zb%MtCBvGJmFl)i2ze(+6q`!r%KIv~$(4@Zu!TL*u@*XX8Nm$$8H(@^@?B5FZBf|Dc z2)odP{g|--DA+}WeIwCi;ZqazGlCXP_m&|S6ZFGGpkJ7vO9)!5K))hrzVSA8fzP={ z__Yc94Pl!p*zXE~#UA!KVZS$Fe;{m$f?Z13)AAHo)EdrDChX6IEmg3~3W1H99V|Ct zR}i+jg8hxK@vS22LH;|l7To;)$ZsgBov%bzzxn-1K{vm@AmC+)7F*H=SEe_@BDJhZ z%Zph@R-|Rs+j*0ZdwlckQV%QD&Ak=0ZtTR5@?%4ADNRxX)r<;Z#? zldT$6TV{N#dBMVNv+TM}H8YVk9ve3a~M@JS3nC#@p)Sk)C zj?BTC?BdA0naQq>%ypUU=E(e%$?lHKDVgly$UKnAo{mh{nC#`qtcuCrj!b@-?BmEB zg~`5-OeL6H!;zslll>eS$}-vCk)a@y<&F%cn5=MQ_`_tSBSRJ@Q;rNXn5=SSXuxE( zBad??(~dlXnH=EABaF#49eMCDX*u$^U~(--x?3h|9O)vN9Oy{5#-!~?XT;8(( zMU9j2O9Q@XIdVJ>x!$zUs9p!?L_tT=8G_YTdC--Zp)R2;#)EFuj_-S-hC$u448^S; z_kgzVa8C$UJLPciES&Z+4)>vUGKc$S8H#gw4QTrg_k&<{P!5-8;dG2~xPscr9InhV z6z6aX+P=e85Ufth;dB;G=NN|vP&=8!Yi1dWbJ&8m@9tS-vofmt}gH;$qAJ@SpC zP3>e3526dYO|4Bqx2eGptggzRA+!)`Q{7?+T$kFJt-5nWt6q;rwFm1{&>n06!RoF& zs3m5|gB~#+45fCa2N;;->{se&RC_Rtg7#n|2v$$!!N$Z4dC)7ygH5QN=|PtW4>qMy z?ZI#g+Jns?SiO}8TM#qkL7x~8wxo8Z2dM}T>Squkv7PVun0eBgTVK z)Xww(Be|TVFq%fS2is849&8K2>Zd%|j+h}2`p0-MmfBM?o-Y{U<@8{C8r2@`KtX#j z4uVy#JlK(#ArC5IJlKianH;o<@L*>e)gJ6ZL3=O(f>o(Jm`Kc!2dNkjb~AA%5vNMw z?2(029fPx{iL)1R(h6svESv!`IQvpNzPE}RgzuMSD6V_mAKE^F2SBjaR1P1Mg=57y zd@!{yQkBTui84V80EjGIT8I7bp^pu#yi3&)PZ zIfmNtp+t>{jx}94jxG#RE}W3%!rCz|OiAv-iKYuD(S^avg;TOzSSQAXhU6|Znl7A5 z7ltSore(RXZj1}lle=)5>B0=Uu%2>ZW|j-<$GC7tau?1tT{w#_Y@l2?C(DHmV_Y~l zxeMo+E}TynYLyEYX1Opl#)VnQUAV|};bOW_r(C!+%Y|VvE?kz}h09GBuAmDWDHmpE zx!}aOFvrBX3IY~A^y7&W)HElfT=bA>D5tYUj!Z(CEOum~$z(G}=88;~I5KHtvec33 z5R=UvnP@QC!jU07lPw(?95dOnC$GxV}r>qj&#jTc6Fq8WwM(iy&RL>9qDbD?BPhO zXR@awt&hoGjKm(~ zy@A3eO1KF^o*un<#1i8?WUYHbEf~xv=%xzvmi(Ymi+2ArL2o7Ka0PlhLF3wd6EyxkL=@-)Ca6o$EfnZO1dV?W5e2%y1bvvG zTPn~;37YTyR}}1HChX&ctyi#55;p$(#wgIIOwgwZIzoXyOVIc)F{41AGeMsx=tu?n zB0=NJKWf1Fk_q}ULAO$%uM#wVloSQ}nhE+kLAO?*ZxS@VQbmEjWrDs<&`}EXU4q7c z^Nz=t6>Sqd-3)XngCB0$pT+eoD}773k*#jc-#?po>k= zF9^8}WU0)Qq;f zX`zQ{p(ia&P!@XALcX`|QO%)`X``=cV-4EaRoUoI8~I+rN7*PhZB&>xDrsY)vQb4F z@$ciK%A(o?O%rrC1-d3dKnD^uALCK5wh23ku)8bR!Gz66aun=3 zChQQx?xA4U;~m{Ot#7JrK(#%US}lY;&;O{m>qD6}v{n?iG*(CL_!bfMEyFNm^+VZ+ zg6^Lj2-aRIluhzmhzey>W(|cBx9m0CbYU~Pu(xty3*y9&`=VUfGRuWHHtVUKjLi|q z>a#hLf@X6o2-ZF-lu@)0q9o3r(I(C|#MxKjj3G{Z`;O{Cwj-#n!edPf+tb2+%ECBW zh;Qss7RH+vb~G*QL<{>X3%k%lh>N&Y>j~73FPo_5yla-BxOzA-zoDqWcgr#qSGtp+ z?bnjsAy@|}X7a2-PR165@| zl)^zum<++MRfkh}O08KPLA8UG+EEa~T}NC)JKDrKhB${Poa3@^DsU(2BbVc;UFa*o z6KGU-vr{PONKS-c9jZJynV6wYFs{9xV&XIq=P-qHY8KAqm`J8l`-1p4Vbe@o(`oB) zWot&3ts`P=olfmMZ{226C%$u!dcvQ9tUk48La>fhZk|oh5Vc3exOon>^SF5~b@I@5 z9(CeFiF$mTkF0(u7eKI%R-w!yX#9Fo)VHM<5meX1i%koc(84jw!ez7&KgNo(aJgyW z3e&=sv~aAlFozbB5p$IZdNo0hQ=r!nG*rgN<4#lqzLwezs@gB-UsuNm1PE*R-BmeW z1z$(2nz`#K=oWkf1nUIl!c7DXxiBThg?ZG@bOCicw+r)WRl9IA1?|Eu5UdlG3%3$9 zp4zCf(QV8c@;&eMgzW!ie1wq__>?`GLLJ;v61)Xr?{Xo$Jn`unu1o52SZbX)%rf;CgQu#li3 z+Rlh^;bUrNx`5|TZWlhGRqete3fhHFAz)0eMGo=O9L{k}F9SIa2#XvU#xYs!$WV>R zW{!-um@IK**u!M0BO@0kn>#YFV6ufH4{s)0I`Z&ivXyfTgJ-g}Baag%+c@$NV6v?v zoiUSTj&zDlwsWL&VzRv>y$F*X9BJ-Mc66j>F(I2E=4%N2)!OT^y;bOm=mozA@R& zk?O!?cSnkaLtrvwX?~VKFo(cZ`X%qPdIQNH#zVfzsFQU$vPVe`GejDqcF!uBWZ zWeT=}u=!TcqhKpd*c4$eSFqKDjUOaNfu>E+0R+85fm#HOA5%qvu4RJO5cEm~Y7;bm zC>RAg$OK)RptBX|Is}bx0#OxfhzYtbLFXvY^$8l^1foDUFhMsY=v4}IC_yjJ^RvS! z0_q5>`;jg4sIYGq?%+Q?VOqFmp^w6UpaV>oThRW>#^)wVFzwxrrMN^Jy$ysaq8 zm64{6txOwR)5f*R#%S8e*8xP?*v7Q6t!ZNnZCs~pjHQjx*f4G~x4nt8197fbIOB;E z-%g`E-I1WW@OLsT>`V(cC<_y4A-;V@S=iOIFwwNI8!g^NH0E*wumyKn*o>lWq0i3E)w-$qrilbAK+eH?)&Q#;f9NCHoRw(ord1?_z! z1nYmw`>6ztAM-|eKaE*K-pAFz>D12jKC%X$25sN_85Felr$exARop*$?I- z3ObmJAz*Dli=6wWInU+VfXr|?Q!a93e#>OBBhyeOn>jLDWU|DOIUbXxj?B!MZ0^W> zipds^%z~I~>BwY-$ySa`FqmxZ$h3gTHjWJDnQZIG5S+;}M~2NzwsT~t%Vc{;hNnz+ zaAZ))WJgDaf=qUDWB|uxXGexzOm=Z(u*76nN5(Wvc5`It!DM$wh8IlsaAXv~WKTyP z)=c(t*Gm;wQvG&SS!YwYLkU+w@ax3Y6rNM7 z4Rfh>r&7BXLgBUaIuqx5;@qWhZp^}o>-2A;c4o&D+3C-tRo&^&r=UZ*8G?1Ua^Zgj z4K=v90l=-)&U687Irr1|Hd@s#+)hEea0dkI9_7Ma1P!?m*Ztm2?MxRUyWe|gRl9I6 z1?|Fp5UhKZ3l9)9vCm>i4D8o+?Dt>hUvE|(6&@BhaXwEv$# zupU$Xe@Yu6{~wR>|1)Z5`XAZdeopPA{x3#m-~TTtX#bZ$u%1xEMXCHb^1a^xAwWU(X9K_;6y@+f1n#F0k|lckPy?Myazq>E*; zg(F=ZlPw+Te3)$INSDE6YeyP7lWiPnGfcL1r1~*g=1560+0GGC`0%IumUezA1oPoP zNPnvHqJH@QMD-^Xqd!x4N(sv#?;bkA7S&Y%tpcXC#-h8+_X_a8?P!G zDcZ=lG8;utm1(2ew2`Kb*OZMl3$YOuhh^GW%d}BL8?P%HHf_W&jYmZ>$OK)Rpl>M9 zb@GEoxjn=LU6-J5D$w-_n)GqF0bzBiZfM%5rH!|gjk-c?M7ci9gx!d+Z!6f137c;} z#i&kt6T)iOH#Kbxr;T@%jm>EzU!{*K$}LPATbefNY2#gGW2C9Jm8rHh)!tKTqaoy3 z8jo^h8`HwJriC%I@V>GzHot|aQrg}G-GQJVDA4f)jbCq%a(hRD>N48Nw6HTRe5fo; z$ZsLa?OjdKi3I&ffleZ5{33po+q)A~yS;~LVNY6Es4VQA-$Inz`Cq@ zi)vpfwTmHyBaU0xyoB1Bo<=SfT}rFk)5|DmPcMgHeXU%$lAxj1HwAa1mh@&*JJSVp zE4kNJ=g_Kl;VKH+g{vW0-zXQZA!x{j<6~U7mfD#vpu5cN!gaK&UAUftcHssH*0;)q zn+O_mA#P!F9<}owD$@J+u+>KW@43UTSChA6b3wqjpmN??-0e{|6{&|6K^y56b_CXd~o* z+;ZUpYG?W%S@#~Mc2fTzL1y3oM=5CkAA?~1sQiC|HbVZ#Ef+pX?M(k8mkXbwc2fVJ zMrPmtXDDd@pM_v8RsKI;h>fW2m0mDyylC2Zi8g*xHeM;jM$~}oRnx|6rj6GjVDO>C z;*&4UryK_#@_gfSvdEFA8y?a$rg@uQcSjV zq}yP!l_M>X$<~fkW+vM>QZJZn>j=e6mN~)%pVjo)(jLD9!F*P4D9`GaZHK+8pVjYD z{bxnvdlY_A!UquYEIUOF3qM3wzh-Z^fs%9)QZG39l_>4A| zD;tXou@O}>zA$YpF>QQF8!MEJuW2J+D~gKa8`H+Orj74t<5y+lheB*b#qpzQW2tH5 zC))T;+4!Xp8&PGx%(SuGw6TIVepfbrqm5*XnZKJB{xB`9q=i3}g}-PaUum?Cc$N6K zY2zQ$M$s7Q3v@+h%Sy8qu`iJJ!**EYNb6y;*pX_^WHU!$hj zOtx@@DJEMw5)vCVja%AuF+FKEuGsR%9*O>7b7L!j0JtSi-d_loM0!5HO|7?Af=c}t zzRNttCEn>DoYMc`cDnd9{N-XQ;+^ce__<$kiT{U~o5>$yzP|Fy@`1Qf9N*kOc6w3HJ)NSBkz1<2&y9E!WJT${WN7fE{E^i@% zVeN31-0gAIY7dE+9U;_}DWMbZbWlQP2;r9S0 z6#||z+6>)F(;fb?aB+n67CHYPd*2-w#nt^ivkQtfs4-DvS=e0^6%{mC5+ewxL=Xe& zY=k@n5ezd+)vXUQ92hyx%i3_w1e7xx@PW{(K+! zuygjFde1%g+;i{DE~aJ*2BOav)P0GWf}tBYw2J@EgZ&@`g7?J5^Z~tx2Oq=NS53>= z9fEUu(@Q#Dg!2YiEPGj(f!1XZE?I*?wVjyO9e;fHk?W4XJ*?%?EA@LY5j;Kr9`sCW zf0({0m}JKP)Av3Zcx#$41eDpM@D3kOf*cKjv!lBDqn*EV*8O`giwhb^j43o|7M#=U)VOdr#UPc~AorTx#36a;bfSeSvJ3AC_ z=A>ksy#Q_)-g-Sp77 zL=TMyl07sAZ{Q&zAs25wJ(LGT_TILK#^Mdsjl-oQ4|N(cA>Z`Sq5o|RS?vAsfoTfC z$rM8??6~c+D*=Ugq(IHuy$137TBg=sVE>1Z;b#2OOr)8I$bG?#-`6tBEYs1`z0p(C zvE!-Brent^I(7n(?AVET1IL=yL&7Ay^>pk$Kx9v_9lI~ybmUQO$b^YRZrZaSF_`vD zO0;JRkZex@-oPG{74{V3t*1Rxi7v=&W)h-ALkZSOF-Wj`PBzmC&HjFq&3Qv$drLsm zCYwQGzCAM&Z_TbzCMLnzVqzBKO;$gM&APf8!+{ChzBL^gj=DlK**tJ5!=&EPohEe& zk@p8~JMmB}qox6c^gAFCIVl@$TJ}(SHSv^B^u0})*(Po~anbuR$MtHSFpLOIuTFQJ+ewPh@~(7Mk}*^CZ(0yqSqN zb5gTSp?F(HZ&N0jJ<2v|<^<7PPLkwJ?{;z(^~-eQc3O{ku{D>}S>SMVVZvmx+qAgC zEiG$5;8c=kgBtGN3nVPi8k$lcG+O3QR@uk*Fb6-yp$v4i>bhP)`y@Z|+*HEvpE8sz5r(6rF8~hNgef+tf*B z^kkc%F((DhwbUHUHlr1955`+g39hQAj!3E4v&x`&u@}@I=|4mZ=)u6F{RiXPL)Y~O z`)jr3b*+bKYjrJ{lA`HadpKRwbp3uHiVmr3sa;XGWO+jZ`d*;Rn(FJ8G}JcNw;j>k zP+Qm1Qg?*5E(kGcB<2u^=@IA=>=e|Wv(-M&YM&VO#FhH_ze*2W=CH2 zB!cpHnB+|r$p=jGu8QOnCizfB@&%K83KGjXvzr>1wKcS~N`6^t`b7_X38Fc0+`>dk z-SS`;P@)4rK`ss2&v1y<*Y8=rB$udl{X3vM$MYK?6dwNz3W8AZx2Yf)_{a2oFrW<( z3ja_m{7t3s7lpzeK{F-}A7G7Kk3i=@%YfR7=C;PBWvx|hO)Yhc8?$CmCvwtA;4H68D9eAtftuFTvb0X-N;h3Q z45+HMmWH~e5?3#CG-2dK)|~I7d7N5&p0D^~7GLNiehP4kj!jl;-p5yS8EY=}(L7x( zzQk9&!Q$umh_3`r(XrWT&9i(p*RtjsAI~(!&%K3z;V=A07QO?7icWp&r}rmsy+8Zw z{gd_n?kD^&Z{dIY3r`y;%BR$U%1#A=QjSy?AUz_pE1G>Gvlr{_=_kCmx9~px!bh_3 zY$u_;QL$>mp};9dF$$Dthjl#+lwy`54Uc2ZxjvdltHtN|il4&b_w^A!2{=W^Ca5*% z`)Z!fnu~ojPgRRA@D)Fs#h3etp9!3zW2Gw1X6ZDK#aH==KfqT;Ez79!kue`Qg^4j= z@eM3~fsgouePt|T8HcIOXjF;N^~FFbVp|V10qHT%o6+nu&yQe}R;cy1`RP5h|;O!Ic2l&)9@q=zd`LbH!6&SI0!Q0qO-Pw&~@de8CKdnxPP078W; zE(FTc6|@*%=B;<5zuv1^?-hQ+w|EP`#$WiYEc_-ADmt~*PwzHwy|?-6y_@xJ_Y;1P zxA1%Yg{KS>i?Ke)5lW7A>mLYFboeioO}f4lsHw{rEox{fYFfSwXB`1?Y?oo4b^OkF z>8vBuJnPT{sW8VK@aCx@mb^Y}bh?kxJ%Ljg-5n^;(9`v zb_Y_`qY(FK5U8XX?HGo=fK!;=A1I~Sdjjcac3;LPmv|sJB-MvwgJ~|J(^++~kLszwDF(U#s06F5leYa>v&*V>D?0aOykwb(&KW?e z#>}3eZP^8kPq0i6TmhuYXIt6m>p-RQ*)_l^EW4UDds}uT z;}a}{&+cIL+kDjD0-VBUHv#2o8C86D0;%fweXRLzAI*2E#l!l?S;iwiG9Cg>Vf_PY z@p|A1AXU~s&zhg{(fpKJJgk3%WxNVHg@rGxMCkg9Kv^X~!pQ1@H-U5;kMrNR&@2U+ z`~3HFHt7=(DopwaD9<6+^$&pZt4iKuyobqO0O?`!muU7e`A0T+2M85*ee0+9CvUw! z`|H&Qiz@qXwcbBjulMBqgYh2z2n_c0M-a_E{>Wy#vOuU9!U#|bS7id_H-sU^dzd^N zNRJ^Lfo30*^V#IFAXM0u%X+$Qv_OWXk+f@WYg)0kzQkXmiC_h(D zX1s^V(}DCbc?Oz&Os-;+XM<2-*DTiS?aDI7d)PGxNDsT_qS?o;dbaCe5Gq{xFQ61A z*8t_`%K41<2_717Dx}1k3+MM$)~c(CxbA-E^AA@-tW|?_l^cQRX!$Yb%-NY z9UTh-r|6gtl%iw*cxmR2^w&RAdZfs4XqJ57-jYpblP0P4PVm#apSRvA{(5J!-WecN48$~`6a!HVlp;9wKpBu8 zt|&*dk1OV}NmXjS2l(kVy!FQX^)6z)^&nKZq7Ep9D{6uATUZZbe8Oze1B-$5aMdAb z_Hk7!o7@aSg7ulHP8!gvq6+JN-1YdM;I>^h$9Y6qdhmB#?3F!|p=`ML5)#(S8& z21pN+Pe8Me$?MtV(?F=O>lD`O?aGrF?_t-OKzi797MgwR>W@@sJ=VQPhJ(ft;eKn6`&AC3B zN2|r>_==yx;`j9tKM6QR$0n#X=lg1&&YFvTG*4BFFYpyVo5h#=h@T0ZqGP2h&DL`_ zEWXM|`~ki)YFS2&kBs@iDNKy{if>@?3w*>M>?>m#%Q(zOMk8X%tI_O}2G_AkC#dxv@2B@9Z@nk`>)pV5F94xp zM9u?Bkz&sQO6iJ=f%I_2C200>#Z_$5X0_f;etNI=*1N@D?>5$ZGYA!~xDhCYD{cTv z>5AKc^l-)PX!dc%eQeU*YQ1;)>Al}u?*smNpJKg_gHYj$M}hKm1s!NS?XCA2f4wiW z-WU9Yzv3VN%2-CJkBsTSDNHQ!6<^8XD}2P4`^uHJkKr zwcaEB^tOBJJ=S0EDXe!L2oO|pXV=pBMZL- zgo;jW@YB1=Tkqxmdaq%{=&a!;omw59qZQDz$rTXB~YHDsOz5t<#%NC zDdVN1nHlEo0X^^oknVsNk1YSmM*j{fDgGTs{|cPKvY%PA_o2~`j8Cu(D{g0;f?MZ5 zDPgtx0B{QR8c=?Y`CF}C52S%v<(NKfS-Ov9J%LkT>PcT~#90a7wp^e<5MW9kS zbRlpGvljrRH2Yv6{mlLs;}gt=w^y)jt)Nrcb~tbf+nRt<+P0K+dq=`yjQ6r_HQV-Y z(5Y-Y5;#R9tOCl@Y$|WsfmDsyiL7~zkLKgl;^Eo#EaNmE8K(fJu>K^qcs+0?kSgmh zV9n?HXg*sl9@byUGA{R#u@N|h^_Qx|>-xn&`9+ZsFXmMFWt&?2Eo$j_)(1#;zwu1-f6y#-)O`c}VK(Uj zwch*u^y0faz4SinulHTn`xXclA@T-Lih+0yD8CSSh4BdkfiFG)(!*8nquIw*U$M!b zgHU1Dr>xgIKt5)?hh1L->0#G5X!fydC)@QK2oH?&PU0u=aV^=@6t1k!@uIvMp!j-*%@-uli#(S9D zA4m_A2cX%<V7!N2 zV}bOrYaE(=?5be9%0Q?X;{AbAm^=e0zagH+cn_0j1Lf7${|B*Z`!TpX(X#(Vr$DJ^Is(W}p5X z&HXtNgbJfq0i`s01(1G5w=v$s=wpENFnTqbeT+Vdja~~v#UQK!%CkRI=br4X_Y{A< zXR+Qh{DhzFE&LpR;g_=T4Ior>>Ow!gmwD^m=&$!`)_aAY@GaiLukjcD5DUNGN$5Bc zyB9b`hwlc;a};&`E}*QylLCvLRxyyr z)>rfUtoa=u&2Op2zu_zX3l{$==oH3(td{iru$E9()Vh;-}&kN z*<0@~{(1v=;Mh7({Re~!SNsK(B0zTnr3g?x5R7`dA_dJpuIRxgbp@e9ZyHcay*<74 z?&hy|AnWZ9LWL{#1WI92U!eRJi9U=^n9F)#5Re{GGZ@W2uF7VUvp}e@E5drcD~L?S zd)PG`NDsS4pxMW+iELLs2o|^pYHn|9d3cCtf zueU3wFy6zi=|FneH3Q8)c3ps{>*?!;FT=-4bv+o|Xk7!F?Ca%p4Fpp*Tklh@Ft7Aw z)#r}DJ*4KiZ&1lKilgtNU&jhNtp|!1XSsi`PuqXQ&P8vzZ z@#gYGUtFvQF9cP|s%GK0*_;}$OMoT@gyl^#89eLqOCygXS_QH*zQg}fR-t33GRfU8PLL)`$9yHRccEu+M z_X5J|ykr@F2&jw&l!C6fVM*iCMtuFYL~4ELZ#qe7YiV4zSVCE!+k+WHMhP*`)wFc1v1+3%NI?}IC>_raC+`&IV)BkcD_+V79D-~W5{ z?j$F8%<4Y$)#Aa`_O;!<9&2BZv#-b7*ERO_1pB(yx~80H$xB&hzdy;oo@`%Fv9G7v z*VC+P@O1nA88-iV`~8{r^(^~(wtYRvzMgAcgXh`r&$sz6u-{*3UoWz+8|>@F_Vp6$ z8oboxqk&nr8vi{j{^j*&VFYx22^yPcHEC;UtmwP(m+ShWo?}J10Vx2#h@Y#>Q6s6F zy`*mPkb0S?RLHuKWnJ$j>sk+4TU4^{WLdX)$-31;*3Bwe53sCzy=2|(A?q%ctS4F4 zV_vcz@sRb9O4ds(>v=C(&w9vuS|#gkmi300tk*nby`qx!i76`>_|%@cpV>3S+zW!)lDfT|}viW@vo8R@cnc^Aox08MF zo0q&_Jmmf4DG#!O?Yc(!jI6^y#lk=9NSJYdd&v7!C9k_AuZy?5&StZF4yRJ9cgEda zlG)2!=5C%cd#Gg&lw|hzmbs^=%)V-w5nE<3FcgrrIt&A3t`EU%Kvsqy4#>*!BN-aS z&=`jD7#hb=K0_01h(<00uvSr(FmyxA_GU-297Js%j@AQF!jvvuO6#C*u7e@--$E3k z-CFaC0a^Vj0c7=S8X&7*(*arin!!*hL;Eu{lc6$(${Cu)Pz6H=FjU3RT!svW4rHjB zp@SHzWvGs!dWISpTFg)*Lx(Z6l%Xbu4ri#9q2&y%WatQnj$-I&8=`UC53t7!+}CV& z4&x+h^Bl&hgz*^0wP?47aUCFQ7*7IZ4dcmxtYJI_kTr~_GISb4r!#a0L+cqjlcBS0 zh`Mz=V2^GcYc@N(wVK*IyLBRAs9WoFL}!`?BhBc%2<=w4E(Tk>d#w=M-_b!H<& zmosz)LstQ!?vuIa1NJcYT(j9}?%CAlY3>HXc$j-5+C{>>o@go?7Q4!sYpFS5Hk-xg zttL19=b3GQy3?L4a2ud*W^H>rAgj8)!-l9kHv!ff$#LQfMZ>172heUhuG52nOviP4 z2$1QxP7ib2Bcd(vC?HGzV*(03&d?JAN_mo@rv#Mxw17H41IUcD&d&le2dDFM3_UNP z)E5Am+EQO+=w*gpVd!;+-VjiyHyL_MKq>Dq^sazX-xE;h_W@Z}eE`U^>O+P;5>VoH?x!zrv8tB1LPs!*`fIX~8F`M1B zM}S&AY|{f>EqYp5t(?>T2<-#SQ-^MZvwLqRB$(I_twU%w2KNGF&d}gMK;{e$4gv%} zVg3#VWX4g-5QaiFL|*R;SZi3cq;9eNkE+7v|4QmZxVrlKhE^FDGI6~K*SOHJy6dkjI? zY<8y63~KWnfZ>E`X;>^B>*#@OYOHEljMSMhGJ)U-!rI4`k57?tW= z!L#K$j+ca*xFpx+)(ez7Pxy&Sa*6ki5ivZ_G4`YE~JGq_72ek!Y?Y+C)1xo6YV-vx!3M zB$+pO%e>B0<~3@WcS9R#l(pnHS*Zda48@XvvgU5 z`Ck+5h2Q*_JApR|V+Bl}SaZ$)V)h;W-MSulBaY7XK)*(4X*!vlAJDmN;B_12lu9_N zrUJpY;*zz*Rhy1+sQ~;6RMrgo9+2tZ;13M_XhN8N!JioVnX$iE5RTY?6>TZMG4wk_ ze=xLDK*2w4i013(fIYnZsoCtFCm&O*=NNo#(YsO-C68|i<4hiU@LOtZYHp>QY|{A* z91}>{K{%gT9z4$WTCgi1bEg;V2FTp$1$qFoBDJT0g1ZSQC7q#O0t)sPP@s>1g1ZYS zr7s|JCzY}XAaf^`vL{3R80yc^0EYHrXdocds+2+8HkhFy424WO?1)n`ObBx?C6lpX zh9XQC6?DNY0i_IOXqbRfvl$xB&B3jx@*V(7qxmu zNs1|^*&|9)31iN+0BT(GPKdc^ZFgU_ooJ7TDZDqRtSMXo$O^nd0R^WDC{V;uv4Dal3{4kMpj1G?{TZ6c zP?>;I${Cs^pwtS6W;0aDP?dmE<_IV-k0HZ`Xt2iu_89D3v)Q?XkES-yp`Jt-Wu-EK zuvPTWo#$bd$5D=zw!?a0B4J9GEo@koxF6C3`w~`4$-0Ke`o~k_)VkINFOGdoO}9CY(Cz5G8a&4$(J-2&toHPvWO})_&jG@#7=_u~G|4 zD^?B$WS#BR0kY2a76396O|Tx2b;`Gpp$3K)*$|CX4PcLvnr}9{lXr|-J;usBcf9p@ zvJKq{+zZIE?LI(OQoWzs9^keIx$PltdzjlE;kHM)?J;h9oZFt@wkNsmDQkPfY(3=ds#n9Ufy~EJE4870L z2Mm44&_@h?%+Mzceag^h41Lbf7Yu#L&{qt7&CoXteap~y4DDd(dxm~s=tqWrV(4dv zeqrcWhJIt{cZU98XeUE|GV~Wie>3zCL)scKf;vM1hJp;GFqFzrCqPylbmq1+hPp7+ zjiDY4?Z!|qhWaqHJ41Ug)Q_P73=L#xFhe1RG8u|6l*Q06hK4gVlA%!yjbSK{p>Yi5 zGc6N`{VL=qQH%&Ct;d9mCLS zhT0iAmZ9SqTEoyWauo0&SvNwhR$W^JciC^ z=mLf=WauJ>HZXKCLzgggDMObrw2`4r3|-F9W`?d{=t_pJV(4mywlH)JL)S8N9YfbM zbOS?M8M+aWFD`x$zWp@#rjRz1vZ zk1+HoLys}^I73e`^dv)1G4wP;&oJ~XL(ehvJVP%q^ddtqG4wJ+uQ2o~L$5LPIzw+T z^d>`ZG4wV=?=bW(L+>&4K0_Zc^dUnZG4wGY%afmQ+oueD#?a>seZkO|41LAW*9?8b z(6uEL)$z@!B((BMe(q7z+Ha@R z8~sK?B%UzcVA3-=o*=Rwlk6PW224e>d0Mr$lhz(PS<_Oq_Fr%d<~Cqb@X2Cgo!Z#e zn(Nri+(pez&Gk(S8|W66y|L8;_Xu){x^v)8v=+85#Z#YncoS->a!fU!?5Sznfzmq% zZpX#40|!q|L+$_yhTM&dX-J+V+S;nfuh@UZs`+Bm_RltKty#Fd z{;=An1&fxq*4MQ)wIsZ+uWN2?Yg*Qjv$U=i&z09KZCz1cvnqdFO=ZK91{`tJ2!c_~ z3m0hpw1L_nt#jXf+CyiD)`ZRoeHZ#MbbaPsnKx%X9lka5qs-efZw^0~`BvtOnXiXm z$$T~Ze&#QkpJ#p>{vz}9$d{R$BVT2H6!|*y>Bu*kFGs%3JSX~H=0A}gnQNloXZ{xc zA@hyMkC}Hwe#*Q)@@wYl;kDs=B4>u*jcg7-5ZMwwJF+#rHu7cow#e7v$0Of|zlp4g zoEF&_`8{$?GVafKAmibTH#0uW*pcyD#?Fj?GS+3DlzDaL zmdxujZ@{qLnz;>wdOL>rxy%ZFx($waKFg>GV`mIp zw?*!V+!J{q@;Jie>BzH@=OZsfUXHvPc>{s-Zsfhl2a%5=pF|L(k*^}(M0P}eiu@e; z6~VPL@@M3q$g$Bi(Y4Wa2%nRqr$$eYu15f!gHXC4dQtRZ1kz>EO$epU2&1c_TcX!S zua9nx-h`0a7QG!|wH*O>4?^pH1l+^XN28A;#GZ;i6MZiFLi8mB-)qq~qHiJO-a)v% zkD&V)f%rKB@Vn@a==agzqQ6IXM*oWb9c|A#HtYDTHCgMjPRd%Jb!OICS!ZXRn{{5+ z#;i?QS7u$6wI%DCtQ)iL&blY-zO4JR-pqO{>z%B3vvy>CH1z%9kB(fEb3)E1IiKcy zp7TY{S2$UvhrS`90^4oSiv;<@}w~KI+&}Ye%gcb@HfF zN1Zn6qtPFa{$zB2ZGg5%`x97VcPprGTG~9Sap8l@Q}loS!Q{{i7B$qhjT$p%eNb<= zTUInJ8MSnwM(N0E8MUybp}q|dLE#583aimE1Ui03)i*AQELv=~5ob`pkVqXrCe7j{ zW?K-iLA}M4DHEAAjmyj?)CQo*+CuW=ACsnGmD!Yv*PuQi-IJ#E2$KeB88pA37IXfX za*!P9r!)S7`mv!r!-czw(Xi%CFz>>g}0XRSz0dcGvoJ@2n9nW53-|L0CVszo~`1 zJ<{#XuIZX-zwL9Py9_kfy66hD^a7L4_B+wNy$A>AGyu{M)7ic!)P^g2Y0*O^B7jV1 z`=79%U9D^P?}i(t(ht+wV?e0A*J#?+cl42{Bzg8Y5V8b=`Sw1$C(yy6ITXN+OBz}x zWfo7WncdQ~xTS7sXc}5tL&H{0$j`1RZ>(==YHeE77Mj=Cy1Z^lsH$!G!p5eWyfL{G zYl@ndE?vH?vF(VOc||pInwplh)|6KP%pEr>Z{n!2V{*rity$2xtY$`2Yg=qWzPX;( z=Z#vpWJzX-?8#|6qPbyV;}R`r5iQlvef#iz2@A7(;TG$#Sg7k->JOTD6?{jarVOjn#5m7cMEMeL+seV*It?Z$X}xQ!)cI<#V*0 z=~ehULd%)f*jBON&}qw;L4XAp*R|CFZu&nK6`}*R^l`C9XOW@kL(_sop?Kl{QL(a` z$!Tb5X=-U{Xl`n0o7CKbkZ99-O&c^|!8rZ=<1kEl2<|?E+8yY+=*N*3eAs*J^Ud)RZo(U$T5*1He&Z zM&;#=8G~!h^7@vxn))WB$d)#^2(eaM-?VH|hl(gT}zKD^)2B|E;{|C5RD zJh!ud@5%lC`yuN%uG95D76#Y8aqr{ToPX^@hn{m`kLP-};@_FoE@{I3J==B7v{_qJ z+tf^-jis79H7$hgcwbcTrx4JN!PHXP*B79IUokk)bCp{F%H?I={HKP%{~6dv*!)L< zKM(&AXT_qGw%R4w8KkBVT|X#1jeuE5sPp!Ge0_nI5@;Q)_Zg!1EOGF();hUPC$4vp z!rDiJHO@I0ob+Fz;@X;BoM#Z{60A7wX<(0YW`i>)WO7=)b1Ga zIOFaizH^E1W1Nt*|AZ9Y*W}Y@WavE)1rtma`r=%<;5v`EZXSh~)B9@L?!=X%9}KQj z9jfH+k+SoNty3;uK1ID1H}YL{?+OQ}Jov4YfJ}Y|14s3JBGL}C$5KE z@G@vTbHOp`S+G;$a+|rC_^R6Q@(cLlGoSdrC%)EY34Ylh`mP|p7?#-fS0>97{~qxD zDf4k2JrG=164$ch@pAHhJeR%)OXr~)YjSX0MI7T%F1B}>qG?epP>>}^PoJS=UxIn_ zpy+C1D?I@(o55yJT2eGz=8>I2o!UZNudKz(zYFA<_aqpn%8c@u5#u$)xOE*~ZYq=+ zKLulr$tb)itDFtaYl-v3lkxKLR5=U20nXJXXMI8ktH5_1@y$IAFW(l+6PEn4-oYo^ zN}SgdXOA=Ra(#)+Nw!|#V$4$3$~|iU)6K+m{}#M_2c}-sv!MPOIJQ@7DB#)}R<+@aN($TPkbN!AP&H7V zgA?|PFtOW*+=`b!3{C4^06ty6q+0L!K()5CX<=n~Wy9gi8(SLiSrnV=d~j_buFb?X zB&KQ0i7VLivTA)}wZ5rZzr0%CT&-VGtzTKKUsbJNU9E4a)~~77udUXvtJbfF@OP@U zh2{o9TZ6M(vgIO3y_lr_bvs`24#dm&0Le}1eNlDVrPXQ4OTVF7-wGYwYqVB8E#A1O zv7rTBpIcgt`YV`5$~HmSC8X@6hw(B5nX#MI@r%LNyM`Rrx_oKF)Faw(|HAI}I`CXd zJOdxW%M|cr&VYFVt>=ImZAnwpVTEl8^p_F+f=BUkKIr$f=?B+n*w#oYj_Yi0U)xWC zijBlF=P|sz43@5@Sz6Bs+f=%&Z35f01q_>r;bUU>9Sk#U9r-dtZa#Bd2ad~$>!iB!oFo@yPmkOCGL-Q!#3`N#emMyP3}PNn%(9er1y-_=kXRdw3QYcjctd} z>@KfsJ&av+83bHM0&)jK!0JX#JA&AQDch^{2dedVsskj1KB10|=jP)^UI`{UK7e3) z%lF*x6Z|!E^&Ljf{Y)`(d0~ZU;vp zTg{eISGN-VGekcc^zAc(W>-_Y*Q9N!Nui#mlBGK7(|giqlue&il}>d?xsjw?UH~a& zO@R7a4%2(r=snF(I?_1NV~b1b>Km3)KSiLE2{#e*%$Z=09Anr)R*e*t!|I zZy_1a)kDS+RLZoQv6Z6roD^p(Pvp9lxYiy5u5XviTnEOv%+K9flldO#*+v|NOTkgU zQqxwGrGWt179dS}&m)MFyktcqY;B}lGTh($A>%fZv7iMq>Q(`|!n75s(EP*<@s=)K zij$=}DSr~%?ZmchCD?uzeZnDqaOnwUoO z&Qz*vJ?Wz=roj~Z3FZ>#oy6G-WbL&5xj19c^f-Tei?SZMPE-J(k@5Ica;v zilfdOsyk!Okaq**s8s54C$ic6#EjnacYs>`Ar1A1S;>Hh_(9ll7s*_DHe^11G@z?R z56%?JVd=8gwwC4fX5OK_JLR1kFrG<_H*5yuaw zIS0-L>k4dDMEi8KpLQULEuB>i-qywi$mH#N2z(Uy`&e>WUTwwfs?zx-5HAV88ARPI z;icu}SUlqLd*a^o+J3dQbZBLszckb~H{s}|0o9Jyz8iXvpKjW*9g(DIq4_0+wZ)}X zvukHn%ql@D5+-WUetX8jH6R_9$$m1rbh7Y^H_%E_%>YPfqzH+^r_V2;9jZF)dFM>P!h!EPd z8e*)eT|~#&n95=Vk70+<#Bj`uW|&dOXv8;MT2(t!a!nN|?srl+M&uUih!hCpr9c=2 z+_l1Sx%o?5B)`$jnqYRaa8|JkcPnrg#AVJXm7{Ak!gW>la!jJJd9_%Ou)2W!j<|`Q zbMzX}{58)UCTsr0y$#HpwzsRs<~c`qE>c#1D@@BNF>vA-2(F*wxeO7(;olXg$Bj8g z#nc1mV4@Bc!%EMo7%}-?gn7R~YY&ToYME~(K+2A>^71jr5Q4c3%+DFt$~OmhM=-u5 z*zEi6)OW}1>;w~zcBVBcsr3c+F3Des)989oOm$I6F)yac;+)ng-mxcE}YW_8kdjB0}!eIAfk`#vTLSXAJ5w<#Q>#Xw085 z=FF%pDWSlt9gCRc*b8VWsW=zo8z)PbHZ6;vl2L(?Vy@{^kWL;8(S+K~iu%HNvAuKi zN{g@-bL{s9x(``sFNTH1v?faNk*cNKg>wX#HtTqRRn|FgNuDqh0I$qR~FG$4f?ge(+^ukFR0_W-2*3T}PIu0xF_?RSY7}tLOB2$R^reVnqzpN)H9*o*SyGiFjB8=U zvleU7jOkVBVKmph>4Q{-1`g3+*uWKV6J3sb!SBXfncLlR#b`n zz+5}Q^}A6rtEi&5bk=l~G+O&2A#n(Bsm`fdBu`bE%6pQrn2HHYY8N0ckN3p04m=0p zwnd#qCWwf`4_?s)72>BqBl5stjy#K|!Znku{?D5!ue+1M^o3lh$+g%*ApbI#Ju_NM9Ge7+otq?^9R0i;aj{hq z7jwoI&#JJOUhnlKpk0!X!iuc3O~IfQV31JzK8JDA&E=^Fl2<`bqhL29lx`ICG79<_ z1-l#V?OILp4rkCN=HiFtl5|l$Pqv-8uyrhhwx4HC^M{Q%NZJd$5w~?N2gvJ{M6O8nU zM*1Wpw2x7+uaQ34NZ-#0O)&}zjPybyeX0>EG75@~P>B(mW)w^(eKU+usS(=WD40p_ z%8c}KBYl<;sxS&>8|eoa>6J#P$|#s)q|Y_d=NTcxD2N&92O8<~jZn2wP-BD+GD80{ z3Tlb_U?Ws#gccYD_4IC`k=|gWFET=ljey5 zxRKssgj$V)HY2p$2(2&*RucCrBXoojI?^aOir)R(NI%+0KgI~HHVWE}^ka?m4ZlmBHqu^cw?;|<)8wC#-1rO5uhvJuRglS5!wBHU(EOt{s;t(Kk|eQ(2!*q{ z(m9^VoobG!sO*{GDto9(Tg1~E8ytDl7X$LQ_*zpXuQh{#`$c3DXZAfDsBuE3WM>xI zpC%(Fx{OE#;)PmDlSSpTV_4Xo)kRqV^|F1qfz5l#tT~kjN@p8Xn5+@%;2P%^Z3VEw z29oWrnUBFD`@UE|+$p#kE69;?q2|uc>6|4H{CV6tMHpjVhD;l%1~RsfK(PZ=nbQNYri**_7l6kWwhTJeA{SWslRKie$Qxo-)KKa`@m@Z&}d(y zePp!XuYYW`AE|$3wC|>WZKQl-qN3M({^N|H``t+U zlVtxzvi~;pe+*rV>3U30jqTnk)~R#s;Ivp>mstO-n+vef06M_6zh0v4Im~ z*^^@P_ldP{(e{nCpP@~TP1!FNEr@k0jHOJCr4+?lieot?u|Csc`ixlnms)A8>;AFe z%vefUtT0V0wB|~2$<(>iQ7K8Yr5J;=#W{SgBdv=-@n?Jon!C4DkkEnHKFlrFUn!Dv zK=6VHes}1U0r{*P&H3Y;Wh%n?YL+e^ia93Vg%H!j>L4A9Nu5gv=Dc_Cw8EeLwJIG0?a6~#VSM`2WPaC`#zpjvGd?fUMFn3ju||yw5$Z< zW*@tzA)lK!6^iH1&XW=xWzf4tz`C|J&+hp3$BVkto0l}oVh2+fNVLesprL*HL#K9SIBAJz}2 zZeo>xnO1r7O1x62#3>n93VQ;#ucd9?Ox$aa7ko4`Gs(|VE^|10cMzo0v2|@(#njp{ z)5aER?XN$aucwC>gTMnAf1Td@KUO*fk7?-YvoNz)FO0^dwR za_HA%%%3;RF`y?wv<#EwS;JbmTy-YR@Bt1(&;vGvhUpSXSK{P90~F8OD_g~EB(zSV z6EiWL&Szde3UJKQlfZqJIG&;uFY))l@l;XqZ+}aa8X&q4raddW7 zi92P#iJi|(jMcf-RvMQk=xQ<07jsuo#5)(7)1mSj5wdho$8m=#(k-A}oiH(Jx6{Fz z5v0n6){G~yX5^=7zs7S{u3S`ghx)Y#(CM1W*_PgLHxcH!U}Rv;tFCv;mNeqK>IRiyJHMuQze`FS@IYpxj5 z;1bgW)+Zkw3b3(C{Iuc!fp<)mPc|t+jYifbM7RM2MJ?b(U7Ix^~klV&c?ARAq3_1Z(1T)7}s_w@UD^=0f@izNOam z-DPp#ab!AIqBCLGMHDWyyx~zBXi76y=3+JFx!DuAi7cGT7%4*NY;RyZgjDwh zNyapmK|4KEk{o6fN`Kluch$@*;q9;E-Y!K3U`JE-yi2S?2`lT~z&5hVgzBpr=qX~8 z<*Fp_0`3TA727F!<{So!5z;Z~wAs=zDQRBL8KyE93k4SvbVRT&E}F_BM~*oX_}Vz0 zr>(r;9RQjMVquV1p?!eZ5szItxDJCK|0T<%69{PtW@AdOFrTfMKzEQZc_1rlDJia+ zQ(7Ez6ad3$nV@pC3^$?>h*q&;K5cAO&nEu|@qsgIG@58UdYy55{-Wwg13p`Lg#4_K zmV&6>gpAit)m4DX93452j;se$2drG>2tqnl`Xa8YNUr?p@v>!{Bk`1%6!m>!!cl{@ zDYX^Wr{SvbJrH$^8w#f6PMPBT)SUHvyZxcLf`W+!6X{D`0>QLUh89lK9*{k2hMMCZ z6Ft?EWBC#%1{5n?IMCjskNX)dq*q2)jmH!%dNahNPRIxk0h=Y;>qz|Bz>cs7iSA%H zyhYD+bdA?{G`jHuFCEW1#XV`Cx4U)$7el}ka*>KdHmTFas8X+zWh5RDUH}QXL}K4X zapvJLu>WQO&InnC$@+rfI9#xwj-ZDu&6%3dtd7JyOiTI3W4+~1Eyf=oiDJopJ49on z#|!*Cc_Xrimhy&270RFB;nlkwqTVq@6|+_JlpHS?^x)mCVn^jVZW@I{fFI-0L352W z4s9D>wQt5un_GtUj~_Cnxl$O{Mo$pPtK3-P6f39od=>{Y&5)i}+~Cj!XYo9@DH^X7 zYduAy9OfaEAeRb}bi0}bmVoUFnT^7fr^gWRb&tDvto-Cr1~|{*UbrG~Es*`?6NG#e zEqsDNb@lz-aS$LBd`JY?YXH&PwZ9pxzV3kn7}NK5C&V78*}Ll4SD5 zAbV2g<~x?45Kt?mRTfU-RdyC|Pg+`WOD;FxaTB8iYLAc}ku&RNe(skB?Mpj1(F36^ zlJ6S`7Z0u?9FlWz(HgXsJ7Z2?sUI7Geb3(LA+tE7&d16&TuMBStVG$cD@T{Z0X;CS zAL(GLwt+2*yVqG1o`$_7{tLQmFKK^jljkIzFTQKe$1@2Jk z#*Xs=$71wj=!m+OrL`^QgH|+(_({`BSe$ulKyoLYr2b<)(@FD`Q!&2SOz*cockyowwyh+IE|aH#1{mVX_&1 z{4rkk%SRJbca$=#T?0!Rsn)zktl{pXiwKZA;(<~rSM7TM_k)C!i#0kl%;e`1DBAhK z1Uhm`;rjuORJs}mHaq>cMlW$HaNeDtmDx>;K%L{mHb${_*vjPJccK(X0!^7neMFaiQb>QMRS|;~Yh7E>IVX6^n{Q zd7;}A3)b0jBdI(R5$xFcoB$zPg%H=Oo(&oONrrS#Ax;;$ETB_|0?R-=@>@>NS~za3 z(;Aj9Rw>s~bTe>&TM5NJf#RG(D`Wq-PYR1VLk-5GLDYTZJ~%i?kTN9c~(zRj7Z@}JJ0>4L~AZ>d<&gs)kAX0tIkx1Dh%oCSZFrK(UpuWp4s;V{bEfb24d(6EJ#qYb)s_2ND1NDHm zDe<&yWfSc(U5Ddi0_I8C>qwU7Nf|vK{LeqwHP)=cN!bIvUp9*Id@z+Moe!8(j%WSH z;L{v2^Bkn4s1n~#BP>eAU@fNF!2G`lkVbU@e$uqfUW4K)vCakEnQ=OEC*a<$9S@qf zM4vHNTBOxw9x8z=WPX?Y^R$#t)ss1X>`RmRV@&35T3a@MS^}X5)t87F=2G1cGc3&t zDSYrm3MraZm24B15a+o;G0>aDg6N+515u2Rv1jBQNhX!k_p(g$G{|{(=q3=v;slrl zayhX-u<4fAxvu-1bYR)Z?uH|kcF|J$;JabmWsd!gA6(~jhUY$o=kU~)r~zH8d^vD0 z$sbq4=Pu*>2uck1j~qx-o)(rC8cg$erWs?| zO{K1hq|5 z>o=vOY+|F8ovI?q(R%^cB#HD$zjYuPLL~N4l*h-)XcuvxJ;`E1%euR0-R$FSGtIvF4t`h8p=T@x z#QiTKoJG?u&%W+6H9TR!XKECYc_e_3QsmQUS|&%wu?gZcw3M&$-94^UVtDI(jUdf*tH{Eh8^lFjvPaU3?Eid_`bj;t?LoJGSsyC0c}fLvB=fu zk6UGL2WW*ehiiyWz1xc{O{l9#-8*9TyHk7&$a&UdV|L+0pJ_8!cdC-Vi>HQ4Olr;v zeUW0uRxe!AwAlO%Lxxyo-?d_|VvaLt55(#9-|>A)?s)0;1f~4BmIY(;oDZ&1HXb0? zG$=m!wg#n#XYDCUcj_F)M=3r^G_T)^y4of9q&dm}`sQK$q~U2+{``vhY4CWL=tC%N z(s=~xCq9oT!-F)}CDbxF*W?ec*-wUbhc4XmdjtM33mNk+e-MSt-+`A5%-kJZNYS+A zLW;_-U&O+4pmSxp1h`=$oaGy+^ej!PwMbwd$j`X712c=G);0SIFm!)-mPmV93$N=w zAw6yVFbP|V59Y_`|LtfVU@?@HU~=;G9|T0Eg{Z15!i@*Vc?cz_H{)Yqr49}&dSK}` z)6aN_v35aYTW!PP*o-wDw!B$>xJgGCz{3=vS8_MaGY0q8{Ctq?V;M7VCU!M!<$mzO z5oT479XBGx`pC_9@fejujq2PdYo&+8-6v8Q*}ddA9V^8t-66PER9Hw9jyR2?!urC# z9pc4t5rV7RUrr5AuM!N|Ye3T%FN1plx%9T-$;rcD$X_%bL;eAl@hpevXew zX`M76)Zb=Vy`u(N0PI#Vzn%B_=K@t9XOy?sQV)nKEKe#&ji05Z97|vGSVv!0fX|oL zE}}0vT^Gc2sIY!7`0tAl1;Ae7P|TT~&%>cur})hg={$~Z+I=1mPe$x;TZAag zO#xSpbS`<4bX&mOrtocn46GJcCamD`a^1awLC7lv$Xs}maAuVAufSE3P zDxuPy2#S|PiR6mtS=hzgj_KQq@uP*daak+An9BU{?75lfJl5C`(0MAseu{TSF5IYK zirVAg+=K0jN1oN6S&yG{&|L}KpM;#zBKXEQ4kjsazb}PtF?}AHqxLRfJ3Aj!D#lij zA0(%NI7EsFtJvU>AiaOsbBX2|tzVtcWwZEQj@{C@YU#^!_%UnvW)7(ElZMYDVz|t& zt}zeTr{{+C7bzVvWm(bbOo4vbrUb76>0FgtxPB_d_Nvko`$~S{BKbxw)E) zEZ`dRN5GdQxw8;OBYTtjGtL?Ytk{nAg>Kihu{G$b+|flq7K;Z3%mL!v=vP2}CM_S5 ze-|KG4G}wBOauva5vr+eA`d(7Mvg`rzD_oTGqI~0xCGfH+|ex=-CFbLqdL->hX+Bm zpZ9HT#@9951qgk9(j4x$;yyQ*E3R8E#E3gk*p{aaMeNe97yGvjRWvO!86lfiDpX~apiyo)Ub$?`afd2A&Q?qcA#*b9~U zeHW4mVc>pjr6ogI-wIVv^IBfW|e7jR!If^P!^nU+*JegV+KAe>iP~D zvS$XfQM!;uiYnrHaisf@mNNZOaddpJ9nrEBRNZ-{a7nx3x zd=qgX`0}NMVLo)o8G}wDGsPTshUX=i!$abC-|`SseD{qe%e_1uTwAG$m=3p#0C1M6 zxd?gP>R)9^nWKLxn6u02bk*9-^)YAbM2mLbOyqUm_w5VHR-&|S=AgQVH5nGAwOw@_ zJ4b-6kv%U@o>^MTVD*`FZT#jORiodT5&52!LFjHECI%-F3akU;y3B)3$GJIuh+&p^ zz|{TyC`DEu92LSeNZgAgS|wV-$q-c|-^ORKT&U36nJPsEPAhl@)4{{raz~_2(Cisb zD($0Lc_T^DRKXpzYeLzfg&@ea`{7)H=#=?-W_4uOOMyCie2kFOmEf^_$7yV9yk>9$=@kens;&pHC*4lV&YL+o9hiRNPLT}QI> zC701MbFbKPn|lE+OB#UMX_qCC=2(DMAjzC8*r+~YF1kq`k`slzQKGeQ-?$SbJLnGc zC5}5vsG<3!=5=6m*nDRdP5aSK(iD^zSUPUFEv_%&2Ex_Y?p&qXobv}3c+=y(K_5g4 z#61$JOSGDFl?;r!Ek(L=Q6ApXTNr@Jt9dVp|0!N9pKvWzEc*lVM2gtc`&88=%zD@^v5~E!wVhXir`Y$n9s^l{#eEzfLef{0@F8S( zB%WKVSK(uBP0h893u~L}8e6a#de6!|-L#vOIQ&ZweCK#I{(m6~3th*Dp#KN`&j2W@J^80w5_ZY`CHju+a?^KYm!KE+ z2>XOT+*d(QbYzdz$y(j(}F ze4)=RSG*VWLcZV=c=uJ%3p&B)rW5aF`mV5_ekp$my!+}!Pke4V@m{8%U`h|@gLjdh z_=G(7RhB>AmY=(e^u*_uE8ffU^KJQKc9EX=ggp0^{Ou>ti{7t)Ui5zB>87W-GSPnfO?C+@FlkFk-9n}LeJ=xz8z3{gfXLtYH z?`3+wxDWH;GCc`Dic3(<>y2)(MSEI*lgp6JPLvM1U4ndn7atLzZ%!XELyqbtpi6#R8W zC-B04@xG&LZ^)+Kj_3rQ>L-geTj`E01pG=)C=xJPu zKG}W{9nlLuAxCu;bb?PsC)&mQB0hIMNk^NY6IU;Kkx#tnhd{7JwqCaH6nCHp*U(l0Zg&fsYmQVdw z(TR4V7xpJ>kDyQ19zmb1J)*zK?91i;k{;17)s^T)d?qVj#80yHLVmLGAmk@YFXSiN zUm-skdXax9@A&04;a{0PnRt-t{qmHMPj)0jC+Mjj>w&*s_)GS@k;awcLaggl3kiAd zE7?Q-OqO2muPmSJ^U@>gHgR?9cfTilLilsHtKJK_!cQtX(N6L+c0oSTXYL|>#V*j3 z-zhHXm-3b9kFeK$b<>mIXW-9GC*I5Sq-R&;6aB8pC;N%sZ(rrMCmDK?AB23reHh6X z^mHZpe)OWg75?hzD&n8?Q2f&`%{S8H75`rJe)C4uw;kCb@S>g+?>oAZ-6DS`Q&-CV zOopEPKs+7UA@CHBrMo~+viHLuozu{je(5UYxvxZDfIp(AEB(^dO()(HeIfpcp04yu zSAln5iGB+Hh@P(WOIJ6Ycu(}n*zHB{SI2wN(>RNE)s^fexxy|LooFXI5kG!@m+1?@ zL%(zt?W!xu7xc;2Z-PGA{*qjwM`ed-m-|b4M7!!r^o97NU%IO3M7vC%Y=4FPWa<;L zL-aRUdqnM9kTXeWA6w~-#vuDW{FZ+>~pi{4L>paz%g0k0SpkOHc7H^awesE6Jxk zk}SQT6LzWOiguYk*?dL)q+jZXkfXX19nlLtDmu|FkFU^^Y&-~hx(a#jt4h8quY1vx zd=)+QQ>=G>biyt#`NW^Bd?8156@C}-ppq;2W%^yQUyO4{^7lgDM&eKC>*y-%CcBD~ z;1l;vJKBc}y(FL3-(=+rI$@WPqq@rUq(?<3+Q~mTNze&;l3#*9`b~EJ7ViSRkSp{E zy{fBBPkK~zqMiCXDhWD4FYF*a$>blR7yV6!UdR=CgkIHErcb87R8x^1yW`LATuJDY z-5C*vO)uMzlD$#b{&1udP&QeH^*e3j}FVV7H;`#trO>`#_n z&=FrU^M&YgcR{|K&xK!!-)*;ePx3|mkgPrO`LmFty2|p&9u=Kv7k&|b678xh(No;) z3cc`WviC2<{T)9)3j4hL@25x5Q$Iu;`Oy=d@P9J*N60TkC-{V&s;jU^_>=hj^ay&Q z6ZZSjlU%XiO!mA>&?j?WMV6n;K8)xoe&{z@dj$Qi%1_3AVTbU4FWBXE?kvWS=*9dc z|0hE)&zFwq$qvd3^qY))5f8$C(I1r_FM86qEA-U=U7@G`tLR1jCj8scwI5`WypHGu zUi3Fvf0CWatkXh1(fi$>5p?28^nUkG1f95&-NN6=tfz8+X&#e4KR%gWjFTTd#hJ)& zetAc>Kbdt-(97|kOuuD%5yu_bPyI~RuOwg4C*vRCPvWEbOTW4JqjB)cD>A)U_vo4o zy*v&o`XP`t9Dl;U9bJWA$o^f8AENJwPnN$c{v=3;7+<34I;O zclSpn-%Tgv3wmKM(NRAH-hEBR9+_XrclTGNhv?;a=#2Nf5)W>F``J%=$gauw6Y=Nf z7xr{SC-lhv@sjWEk4nCqPRJMZ!d{~Di~nTok@4bbiFZxS#d_n%8tJ@!fPF&^w z61^N3Ui?CSM|8=`cjr-+d^g>$$fte?dO!IxolGz1EAl73-* zN9SixvhziyN9OmlN2U|@$noPP-<{`F^4)a1BA@gMdO!IxolH;jNaPP%U;Of$++X6O zaofj-pX^D7&d(mNc`oRau}9|jvqz>A@&&!@AEHYp{)x`ZKQh0N-w~Z`5A9#b91DKA-Fn`+cuGhtxcb?zqF33U%={AdGuf}AC%wWi!cNuI9Y3l%RqzY?j_BOJf-TNpc7Zw9+BTDuc-Kie6q)nPRJMZ|BZj#_IUMM$d~Q$ zqLb|r@#(h?$@C=yL@kG->ix1#6* zI6TS(B}76xL`A|5NR0(K@lV*EO#N2gNI6=i=|UasTp z3E$6V>u*>-oBh7L%)4yz`n)dBfpTBdD2x4Jd8rrIUnv)VN-Y1f=?}|i)35f(bBow7 z^E%F+u)NfZlb3R_Ut(Q1`H|12U*?O<%PJ=5I*N*AeW|>}QF5BE@-h#S=vO;rKatM` zwZ7^L$GU%t-^HG6^^(eIJ7Q1OT)j<9tow_Whhw!z?w|F%i>sGZPTLWCWW7p1W#1Be zWPNFQI97Y~xiVY5q;lGhj;rX^e#XrUwZ|WaxOz$De0y}f)ITx~S{{zo9)BF->Lr!a zcEmqAUa~K4$#})p^T#VrPVLe5wI7-v73+MLeMkHnC8znme4O8Xd6~b`5Al=cN5yKt z_B%>W^HttIhcbQ6>dVXg%};+-K52hNE z=8L@So%zwP@=5jU{e#@cWNSz4@#SUzm3nG#I1bC}c!cHjI+J`h{Zj7VzqQF?Pgq{Y zPuma2VvjE``$T^9i@c0SSg&4(^^1S9$*cb*mVepo3Cm~euP>jZzhU|O+Mi9{_rJ`~ zZ2b+(=cm6(^!xo4`E2^t9;qk(jC-#2=Yz->H$h^ZFX1>WFY_Tk`b9pQe(7H}yVWkS zN9B|5KQjLL(XaAJ^@}|+PBIQ^XH+cqi~jt`Yk%YXsO_nK>2FebIj2QF$^DPsuSz>o zPx>PFt5Nln%BlTP`lIew!uq4+RKLoLy-Dt8qU?#Puljwz#I+NpKkEK6tUpRl` z+@~iQuQ<7E`lH6dw_o%}$z{`@#Q$o4e*Ld@WvZ9S{!DV2?3evS=7qdhko7P3y(*`% z=uaZ2^8Wbx^<-bqw10*5N6BT#>^Cw_N#%9^Xg!_(QT3C`sr@1^evi_pavJ;g=y=IE zN7YyT+3Z&RGH>PnPV|YNviVc|FS?V;tNkjkpEKwq{*Tiy?WkUjg)IWokYJcAGOc< z`u*`rqTiR7`6<`x7mefei@c1V|NhRG_x%$!AAEVgzftqSmk;ZgYqeWrUp}l~u2oKB zU*7kRtd~svmHDR6*AmM=nK$B>OwW5^d6m<8YKO*g@=5fIUXjywRIkQ#1Kfj+0NKU-XKcwxfDA z_WLVx+7Fp;+58`t&ty-O{;2-O$w%pLZ)}x%9Ze8_$-0t%@>_K2kH5}DPUSn8w8+c4 z^6$H)p6?%(SN*cief|Er_w}p1+EdBY%8xzGjJ%A4)JtNI>i6x@eued@zHlt^nc5A@ z>9y*Y_3Hag%fqqnAN9ZZNA-xEz8)P<^_%!z=B3Q%OrOJKk{5r($@}}P-sdHimvbvW z`t?39Kl;T#aq`l>_(x*-r~6Noe|&lIcYfscJ|oH=Xpod3v=S zZ8t2hc4w2*dMYpa;_Oy=mD75f9~JBR5P2DgC^^knd9lBV3EAptxzK~~WH;;V( zi=5U|J*rn@)t609<#l}g{>F`iZ;#Fg@ssLNy&8)>N#s=C_rILO+5D>gm3_R8392V5 zR(bKC^f^jS^VQG3fATwC;vdzcdNo#iRDYD5%KQG;`JnnU*`@NL*O%9JRjxbp^+FvitjZGpSx6i5lDktqoJ=LRnHBKt0@^Shz*`@NjkE%V|uIklT^Homk zX?Zx-a+TNmVL83l^(XQ=KjY@V+An%_eMvplqk1(?DyQ;s`ZL+3^8UJv>qjPgGU-)& zlIm4?U8lbPGp#F?SNp{-U0=;jTJ@-$#!2N=K2CooyHws^mtv2$t9muoeC@B+)ADev zr~`h!}`<(>SS|%E#%?WS7eO>oTq%ne54=SM5ov zSLH>&%y)hMlINdBCTMv$7J2cZJ|~6C!`FIWqV0ss!`HIDM1N9wdGF9BAM&DKo*R?u zS2=AbY;X8lS?*wQ$10! z$ou`3dU1AT8m~C{xbc#D;r7Dz$auu*&oo}yflbHIdU*=n!oNtf#S;s#=_UOEjbrV%z>`5Z$+arF{amtT9QqNy! zaviSkkC(37Ome7+E38lDH1_9@j)Tq%xenL&$16@w z^{YR1yu$iaPGjF59WR|faviR(`gMQK){d`V*Nf_x>$v?nPA-%EQTioc<^Ayu>-XhU z-nU=JOXsOv$L-H?a{19O?WnvzAHw>5IhFVA*YRy`^y#?8?ay&?`Oz=!s=Pmc!uowV zUtanp|0;NTv^*U9{nhy(ev)}6b2cpR&xbfUt*8E%anGbr<|ahdSN+-K zRKNOD#xcM4=zM5l>PFR9{h~Wg&bLSWo^-rKzm9K``%mAWI=)SejwIt7C#UxN`gOcy zpGY!ZadMgTtN&%*CGmfpoaz^UieJPZVvpuW#p-|QUs8FoTkK6Lul9)jQFds)Z%>6dx5CHgbf6aBI;_~V;x{`m6xd=_Vq z$V-2d)Kh!H@=^0z<$e1z%`<=gXR=51XR0UqWgp4U{Pg9M_($ZWze(z;Jz@E%b))jW z{h8*m@1IQei2h9VM8EDMGQVVBlixYS%?DpTiGM_1`kSPl+7p(KvPjOc zlRct8Q$1h5%rBkCsxKU?yl;P8J(Um7|FB-YR{2c&r5%;iSmc|V;Lo3`8RWw9qCZK! zO!{S>slITm@|pB!sweU-Oz_7y)9-M!9hDdTN$RP*uV3bY>I=szpGkkFdLr-dn@Q%6 zFR$w>Y=>T}ez7M>y(sx8yHq|u^D}OLR=YJ8{r{9vstgk5jQR_?Bx$NIj^VsjNFCW#q z=VyII>5n?Uw7+rpF>(EktLNLVa+&6F68)L#iGJPJlFt9|{u5U(lm1Ne%(p*Ef2Mk( zzqtwi_-4ER5qX(!N$O?NpJ^WW_DAW@R8RE#`=;)LanBdNysndM^5Ok3s-D^tmXESa z<-_}Pe(llyIb2Wl`}?i#gJC(}|Gs=wKg06U-z4?ap0IqBT`C{mpR?JYNx#hha6Qql z`;Wg5hUNVJ`tnKqlW9MUs;Bmd{eC-oZiMYpd4K&%Kf-ch`!ng!RL|G1`)8GW>W{0J zNx#VF$9~nHsh;T1v_Hq`kJ>-0X0R)h{!H`C_kWcBO!Y*6a})gW&G!C8(C)kJ6v1p6Hix(fv(6$J6<^^1gnNmutVBu)MEdENr%{=SkA}sq!*E#r|ydL|*o{Y;x*@;Yu&dNp6=)&6Yt!ty#EsxKU8 zl9%xa%jvZ*Fa6c^pylD%mzVL?@e9l8btZY4uUa0CMPAC~pUew67ybK@Z1Q>^8kW;* zU%#}IAN?YqO~2fKwl_iUPv!5y=sZ$Cs2v)syv&2jx$<%AM&(6+SU%G@`}e6*9(A9g z_Gtga|LUJi_em-*{Sv)?J2Gxs9*#4~OFLmXy%xRsxjz*D$n%2MQ~%4ptSwYilbqV4^GfSwTaRjw)>HpP)lVuHXHVStCb7q_A7_s*r}n6R?Vs+u zN#=vB!zj5V`ZJANCOb08h4uUW7Q0kWc)XL!nD|qvq$`|<>5GqJ%0T-dwe-e~q&%lYHFoRz+TZPbvEK_nPweyR`jqoJl_J z_n0Ctei8lZ*D59*b#7AM{83 z6Rsa+PgpL_o=kSDe75nDcKrHr_V{wDU*&bYzDH?KkG~6v#l4=C;La7Uf(~WPy8IG7x@x}mh?7>oWC-d0WeSR$=Wc^&M9JoF+Rt1 zILA0A$2_p*n46RwGvGO95gBDx#=KN?GUfs5cQV_XYx75Yb4rkr7WVgtQ z?Gmf~l1|zOvw7s07aTbnS2Jm;Up+UjksH^{ja5$LS|-1?33YNqT@ynyo0A-KpyimGiJT@TG&RAz(8y_SLW@7)`Vga|r3o6V zZ5sdC?X@y(X=t6BmRRS2lx50qWAYC*p{NPPOgPMh!%firpl$B8u6^^coMT>C{O#n! z<16c{g9(0Y{=jdJxjD}1Y(f_k{P_`=KElXK@MZK`=DVy1jb%@fy+p4y-qQT=`VL>K zevP%Aq;gtMW38{(8fVK7w->%vJsPXNq;gtM<3Fpu>eD#Cdi^=ErRnf~+ttjU!%UDh zD{E2Kt;*=S6d75YzD#((J<^oRdX+su*6i*kgwN@2CQm|l6MC3%lnFgekiPWFjlk$C~&!6OPZlJ|Q>mW8%Ih$lfA-(OB*y#3osva=##L>p7&c%nd(8`B&~M zWc>P>(BA}Ej{{7Qu^ecEtj9qn3^qZ|In^H(56P7qYT{ugoM^&HCY)@-DJGn1!fCnj z=_Vd-!Wp^o2osMqVU!7@O_2I$njrPV?TP*|CW!vCOc438CW!nv6EgKz{59T$HYSAA zK_E3`X9^}rO3FKgV%h(Ym?#o@8fje1eTnRH0|T0g8quY=hlk(ZhD{T=gkZfh(yYFcCQWBf`9k5IOrsz%wDf;l1` z%oWPs6wKp#zA%H_f{@%om6NqAdz##{28$$Db~d?t4HnDQZ|hoidC3XK(pu8pBRE?$ z1m_6lPL`E%E_vs{^M%@iq%{N=P=29MY|51H%V@d8TjFQGj--8kY5Je*k6?+6Ua-{T zAIY(G|A>ZIOJwF{+C%>2Uc}lE*;d|OFT<-BK|j5moQt8KzJ#1h;bri0xB^}QuY@b% zD!3Z1fmgw`a2>oFUIVX%*TL)IdT86V`mG)-pV#InN%|tX{1DuL_6_hxcoU4uw;svc zYHYq}Y-K`gFP6LU;ASa_3UZ$)vnjX*i*EJh*XD}XwOIKsBiR0(6*vty_3?oT5g@FCx9qDe!l9`IGfJk0jV84D3oWt;32LbhL6BU zAriiH;N>Inn8(LSKLMYFHs>kQPeYr2hBVqeIjr!mt*mX~S+BOu@k{;mb4Wf93o88r zt-n~HHf;J+Tem%W=}*=9@}H_LYOG(Ol~)tD^;#aug3XEQ*WWl_JQxna>-g1U5hGPh zcAq!GCAqS1O1`|mlRa18?*(rm{Wg3DzMF^dk@LPV)Jh&%BtL*3LRytnf|fs`hULek zKM|HRLEhWt_RN?16sgVdGoieDlsldFCU6#gPMPiB7m{X&{!&sJg0GPAxRWWBw}avQ zT*lY1av z1kVY0iVuqT&+_WGV@8&3$Ut_;a(ycS-P}wB0 z+NN>X#vG$xcDPVa6_;>gD+~Mn*3dgGHuZnd( zhxLoqniqIyu;yv3^)=S~s95w$*wcgtxoQ78s-EU&t1so@l@z`XO3HWyyx$K>{|n=AU;KFyE{nPjb`np?t|>cf=&HPy$@!z}L(W&(fi;%XOzyk1d`n`rPTt{X z3R5HknfU;<%;s(BRr1=}!j{JV3dpuvlC}|4z#qRK`-*w<bTAfN4g* z4OkP_5{CD?pf+W7gyJ9j8EQ~huO%4V1n#D`Mu*WZt84j z!e4Q>pZkgUd5r0&yvPkAh7NsgWd;rI|!)-tBN zAXcnA0|xbEq~r-P*iBNI^5hvX*j-BH=`YwrQsLS7Pq$ykN8`LB8=ir3Expz=Oww|u z`FV1!_dgojw@S>O`r=7a8P4rY?S=ECt*CXUcBxJJ21VbTNUVAG^HRUWPlsELyOw%? zx1A}x7PZ&nJqg;^xPFDpq)s&xB)@uYTq8HucUXT$JAS*;rhgqyH#OzWOlWRGi!8F? zy5VabLpfpOow)yAJg#heBU>^z$XjmzO}ET;xr>z`@1>SAKV`v01t!* z!GmEF*c3K{&0!082y6*k!Pc-1JQN-V4~K1GJJ=p}fE{5cn71#T$?pP>fL-B{(DtPp z>F&_>r3dMwU{BZ!_J+1EN0UAV9t)3y$3xqf6G-=gePKV?AKJbQAUzOzePL_{kvkX; z5t2KU>tXOjcoIAro&rx5B7K^sxH_HE;qVMC2}W=|5{`nS;hAs@JWGg!>`L(0gIx)h)*d_W?Toi`-JkJxuIHWccCOo5?$32Q%PswxZRfO| z&HkLWv)OVoBQXU|h0|bE{&Y%bz?pCsjLM%)=^Qv0&V%#e0=N(^f{WqV@Emw9JP)1^ zFMt=qC2%QR1}}nE=W@~)!%N_$@G^KgTmi3uSHhKW6&vXa zPEyRi>s@NSOWoj78(iu}m%7QNGHJQlmEPh~x4Kj&Ew{PS+g<7om%7uX?sBQSUFsf} zy4R)dlT>iOP}hI3kvu%>@*W`XLHH1S7(N0Yg^$6<;S=yl_!N8^J_DbH&%x*63-Co~ z=a?OFJFhlLzP@)3UP9_+_zHX#z9v+QB@SLE{|)#id<(uUl(9`F738TKMA$eaS8p;K zvub$N#17iK7*gbFQ8Z7uNQnt z=~wV;_zkrA-;(|geh+_uKYIB;k^UL}0)K^tEg91;^FOM5z*0(>p5pzp)AnSYE`e|#iLHsPgM9THoHj*cPmR}|1jt6pnd9J!setF=njlj2ybrAR?5@KAUdJRG)#?O=P@0d|C)VBWrTCcg_j z0(ON*Lfe;aq`O1gmmZ{#f<0j`*c;lu98LNdcq}{)9uI9_P9WU}_J#dme`xzMfb>A< z^@Ve15V?cl5FxokxgG{jgeSq1;VJM`A=0O5imTHp9S+aXk}bY7or<1ma59_%y?ow7 z+%0YYmdc&A+skYZO2Sfb2e>1&dwXfpWnfuY4(XEY>+#T)#>%%=^1K1GyHv9IxgBRb0jgV{%_kw#v zdoJuldSAF7{3CTIGe_*_{rjWs0C*rg2p$ZZz^1Snv@*>}TbUM~%ps&_(xd6HB{{8N zYuEon?DUJ3zZjTH3wOGPxeVR!4Mpf}LR(nBV*@8%;Yy?2c?{cVtUDns!IF^ygLb zTK){Q`?#gu$1Uw>+I`$|%WBzCuru85^_F(8x3r^q1b(*Xgr(j6EtBi_5_KHpSmQr*c?NZ0M)Unh(4jvCrfPG@qc0QzgQMwoTdsn&_ z*&QtT9`bkIi~g)N{%7ggve}j1x1{$i`MulOvOAD1tM%{LE7G-TpG53vrq2}VGll5=V()Szb`;GMdM*4oke?x2USJQW`$=|_l*KR5|oAy6}_CC#x{H|VpDe7Y;Mgtz@8D6@SVN!t1%B0s+~<#*ove|~47HT`b`?S1V(Hhh5%42<^OHLfX#jrKFcZe_mfi&T@D$yad{LeJN=>11}?e zIrQiC3UaQ1SHhJroqd0wUDb}oD#pdmsMVy`Kz~MEMb28d4qgrIjJk%jol)14z7F~` z>Uwh4!yDiRXlK-or0tBliS*6TpHa7vb1S?J-VXD#hU~X)?KgJqUt+rh9ez5A%$-t; zZ?ylGvb(eOqxA*-;i=WyX#H({X8X-L5B^B$UD$s&jQU%0_fUGTC&S;B3+|H~PKx^} z+Xx?k55kAw!>|zNQepTAIgi4}gnGJgFA{N1i6?lP&r^ZJ`8-@Y$-8GB!W_WXX8 z^lQ-mvgUQtZ$SGynm0+m1??M!w@JSP?Yw)J^m{PMHfzKC$b0}lg!a?d_}}|{gyhHY z6Bz${A8Y5QNN$FoLHk|r{_KRYE9Q4zwU&R5hA-fk(Eh$*AGBG2+RxDTC&&8pD$ z-@qo6Hig#1_WMEhS69~ZZ;|{Ceh=+$4%$-7T5f+a5dRyisImC7@~vlnz``G)^}|o3 ze}>i%zmWbF+FlouzfTbqhPK!IO{Aa*Ikt~QNf(2@%~SD%ecSDyU4Q>M_D`|!?>yW0 zWb_+Ae^&hc*J+gH`OWv|yuTK#2kZ{-@AGzt_xE|b!~6TZ-QoRx-tO@JK5ut;OMfQY zo!su>{!ZSVF|xG#fZfUM9^RW$OS>l=Lyo1thuhuT?%S4je;A0or9b+1f3`cbzdzfZ zIq&{#cV@dM`#ZDUlk@J(c2BmuvA-wV-PqFFV|PV=Z?wCjzc<=l(cc^GuITTLc31TG zM!PFo+F$I=z#B8+EEqLUinF6GM20t^K?!oUf?LCF;I?o(xIHWhO9{Ed+JS4U%iddE zgI;^Lwa#l}MO6}SPfQ(HDFCxOX#fdTd+Q>jZ__I`%{;OB$POvlV z0*`=Q;gQfkV|@MHDD4h=z@uPK*bDZCN5f;_vG6!}JUjvRfqh{=*dGpnQ8o;ubPya2 zhrpq57(5Z41W$&iz*FIA@N_sFo&iU|k#H1@vSBo(XTmY?EI1a9gX3WUC%}nt5}XV@ z{rYx6|K?Hn`gix|={Wy;$9am(4EDaME;Y@irn}S(mzwEPvs`MnOU-eqxh^%&rRKZT z0+(9oQj1(_u}hupQs=l-x?kr6N%!l2;`pBHM*2LLI^U%(aH$JjYKcoNb*W`8b&*Rg zcd3hA>JpbKsCF-P7F_01nev|GF3WyXz*ymsSlw_ZVno_qPrIzi<89zON(aYUuev?->H`ej@m@bwsrNyZaK)rr)(6Rrk;G`=6z! z938!tUh1yDr4eUl`gupd8Xg zpuJNqO1c>IS7JKH{>W$6={}auvA_Cz5$PODGRM}lv)uqUz#Bc@MEYiU3%u3iZKQ99 zcfdR0UGQ#r54;!N2k(a);REna*_rwF?SouD1RsWvc(m3$N{+SWG18W{Cy$e3d-4Qn z%Rkc3zs{;1u+V-YIhQA{IUb*+^r_$IK9}?BJx%#D9_?p{_ESaZ>di(w?Pbc#{d>^Q zqRVmLB#S4jVLrT(1pEqs-BUxTlEX=|ZxTfyc;+3$b0 z;Jw>-pF?=%v3XJY^PB$$K713}^joCghVQ_4;d}6X_yPP7egr>;pTJMyX80Mj`t9i0 zlOn3E&yoKE+P1zV{S~xreNFlsXxsXh^mj0CTfR@eN9G6kBm4>e41a;Xoq6m2icF!R zaxY-(7ABno{knPknAf(vGJl=Vt>!=O;k-Uc?oaFgcpv8VNtEAgeqQ;%&WBNL{c*46 z?c*QubKbh~KF{yG_4V8HE`7tB{0(nj@BN*>L+{TG-}1jY-_EQ5|ECuxu*3I^2SPYIMe>~*3x`F?ViOJ+ILg!+5Hk?BKR5%U#->0yjyq}Nc1@J-`|Lr4d;c_G| zhL^xO==XmQ?SD7KTDStqE8vxIKD8Ej7W&^Du@L6`rkM4_4way$!nF>Qwa@~q5u7tLG)!X90G@W97g&?=%-I7XE;0q zj_~OJr7b_rzQy-t`TItalKo3!`SuDWXNewCW6|h6vjl#68@#zK+zxK2lCZ>vNID!A?k&7h>t@cy(uY?LAZd?z>g#x=PoTU0wcK^3(snb!FdZ z*tZ*lnZHBeP>)ghwyu2}GMQC61&)K`;Z!&cCXw;(X@bA~I&pVhd9D5%pGnSY&L(!Q z3U1E|{f)(dGYgrDPA0TB=lKf=_MWT}W8N6<1^0&jZyodg7X3hE4uS{6Ca@{Y`&;z% zuWH!)_=xX~F>-m%c5?IXKqukjli?{aG#jKIb@S{`tv-B`{L17PBd03#?`xAhSNuO^{QGR*PA^}*9Tx}Hq^F(4BQ7QK zk}GjB6At%c{mVGzO-DQpHIvVAF!Yu^k`VF_k%2xfo^`@sxSVF_lS2$fCj2Q!d`}p~^m_IR9 zSi6Czx4c1&;RuN|L@-an3u?fB{awl4NdHa z#^zeWUb$g!6Z@f&xsD6_nDV%gwx9Yxoqq+l{?hY5J^$15|G#_w?`zIy3H#-S{Y~tL z1I@LBgL1>cCicSt<~lAkG39X~Z9nyYI{yl8{iWxBdj6;9e|r9>=fB;9{d*rtr}sbU z{olX&{x?1U)AK()|Npz^e^YbDNobZEnw!`UhnQ;#EptOF6Z@fsxsD61O?g~M+fV(U z&cA|Nf9d(3p8r+M9-V&w&-$R6@r57$?caZFWBM!M(A;pCiT%*lTuW$|8`_)L4~LuU zxX{6r$Az^0)c@)HE4cNSp8x6jpPv8!-TR-8=6sf5e!4~IY+^qgVXh@~%?(GI*biOI zbzJCX%Hu-Xe(L{p{uSK%OV9uG{7=vS^!!iH|MdPx=74|iC+YP5@85m@o1Xva`JbNu z|K0O{nc3qdT$CG@o7fMRm}?1_=7!5m?1ziZbzHdIl*fg%{nY>I{42Qim!ALW`CrBC z(dp;^)(6#$FZ}Rt|NMW2>92$JD-_QNW3En#(TSYu*8tTfkg;VM%e7t;1q|EKe> z;MQMy{-@`Edj9`+?|;^s^I5{W+;Fvt{cx?hmT+BexZcEmxW-(^h4rR9E~M?J{!iy$ z!L7ga{7=vS^!!iH|MdK~d$51+BkA=1C%ymsH{buJ=YM+sr|18F_xxXG&NvC_=l|9R z%Z)GmkbeIm{r<G}WPJ^$0s-_y_E)6d@v?(_G8UVrKNpPv8e`TyTN z|I^Rk)6d`2&)*B~^Y?;Yf9d(3p8x6jpPv8e=l|*F|1t;C??3$B2mki(f28Msdj6;9 z|9|)V?{4;d2|aSdQ6~07FLN!ScWyY^#D3^$uH(WnraUgB?Wg`v=U>6Czx4c1&;RuN z|L>mv$C~q5!g0CbcoX}fkGYo6H#hV%u^&z_*Kwi0DUSFra`B!l3FFpU$^S_GO zqtn0tV|`G~_`(l0%(aA?xuKSc{ZQRp$A#LaJT8du3)24sO#2cB=7vEg_QMc!En#SG z7-nKW3^vzs;Y3p&7t;1q|EKe>;MQMy{-@`EL7qPaeg6H|+fUEm^!!cF--0`T3wr&f z=YM+sr|18F_x;C7=J{O0$+_Va6Z_#bb1mWY+%Vk4emK=!$AvRYd0a@_PyL_Hzk*wT z>G_|Y|LOVv-#!0FnDbe}$lNf>#C|x_TuT^}8_qJZA4Z$&xG>g~$Az^0)c@)HE4cNS zp8x6jpPv8!-SdB(IiDqr&kccz{V>s7OPG`!CY#s~6U=p7m}1J~LfU@n|8)Kp-1Fv@NfVAUwZzg=Wlxc7Toz;(CaTf|I_n7J^%l^_diq3{f>lb zxna7A{V>y9OPG}#W}Da#Gt6~dm}AQ0LfU@n|8)Kp-1Z?5CQQd1rm()LsTr}MAi)?a%5r{{lq{-@`Edj8uz*uVFY zbb9}j-v9lZ?|;+tKRy4`^Z&nl{->Y6r=P#4pT8H}=kEo*{?hY5J^$15|G#_wr=P#4 zpTDP{zZcx+?*+a7((^w(|I_pTzkB|tpTDP{zo(zS7u@IX1-<^#^FKZR)AK()|I^R^ z)6f594y50I_`MJQ)!+XpQD|9ja|4hg!Tb^L9P@{|b9$O!{xi@V^GCjOMwoD{2`89v zk_p{S2#RkloVS%QC?T8-PlTtzNpK206`l^q!XYq6^fWi2l?i*A(Ab2QCbTx8kqLX5 z(8Pq@O$c_R)eC5Kw{0Y6Pq;Iz4C})NuoBz_)`jI@QS{6~&tuZ>;3;@3yc0eNpN4n9 zyWqp{Cb&39>NeO`xEI_7R)>w@-mn_10r!9v;n`>yY5u@WPA~@chlAmn@GLk84uQjA zAK^|?bGIDfo^WSa8P?mY+7ug;n zF;rytkkn4d-i&M|Wcwn!lgRcGiIYXPfut%RdmFMc0VT=FS5-fRS(%m zk=+y75y;jPS@Y-kbApK?dx)g=K=uh_8zDOy**!$|D3KT@vh^iZ9@$%vt&D6xWXp?e zZ;?1fWE)DVBC@w5TNT-X$W|2DU@1Av;9NKlc0{HVJRG)#6N*c%nXnr?0Zxar;qkB! z><;_F7i2`SqaWA(;dq&Ak{cC*Agjay(%axrEL@Z$>7g>;gU?CVCx0tu`2uG4bEL0l zo{htb&Tuk33f>1FgZrbW2|O47%z&Hm?PsuIF=??8Y)DQcI28@Yz)NZO7PuR13#TJ_ zHT;O2qNG=lz8%(w9pEfVuY;eGQ-bulq}RbJuqix?(#zm$AioUVUDS+JkXy*NvQBeVMKIDD3vajpFm%7T_z zef9w>@g>&peyq3y;Y!Y@E8r@41H70SdlTFh9tNi}!`H$O$jKpn8R=W$?yw!4LFqN{ zV{(d-KAZGaurfRto=NE?@D*~tf#<=iVO7`+jz#iv_&Pb?!%N`JupT@dPD64X{E(a? zRs-qV;2y9&oJr}m@Dp;1lRk&^TDS{r0>@B#DSVZjZ{hjy8dwcBhvSf30pB3!2jR{p zls6&ROx{s4zQHt^i$NuJ?jIS?pJ7*a)&t;1a;}22k*|h)H*$`EMEkxAB-{>e5ASoH`V`MKB)2-O0vo_;un;T(tHMU`9qiwgbWK4WWBI}GAtbMc=W>cC=f%h;=OW~j^K;}AGj6=KEVx;Etyh0`91O+3H^KYhMxnG5 zJm|*#7slu=dY7CJBcGhNA)lNtA)lO!Ye=sa!BX^f2Uu5otlkZ7Vx}eMk<7-#)OMoc zU^@P<%sTi9-M`otu`^*7V|?~wc%)>2Od zwJ9qLb6^p)>;QA%-S8Hn_9U2rCA(lr5$Y9#-H<&9K8OwL;4I{mvnraC^9TBsm{{|x zSf)J+$3YYNkeoe`PtI%bOL9Jpd~yz9JZ^;d!u#R(=ov=(2htCau8~g`rN7Bp2>IkJ zjC^vI5&OfV=wAmnqA@wU;+@3w+sc#<_T}DmAGkL>jP*$WnfN|kH98o)){n zDX=G;fy`|9GQB+=4!{e(U;2A~IT{)3m!H*|-}z;r^UE==XTPXq2V-4V6OJ&Un+a`A z2#R6DT&(TKoEQWL!olzaSXd-$n^4b$T}{}{1bVy!I?hK&DP~9+SQ?gv+rc78&PMV& zyt)D20B?j>!?MiSond)c0qzKorrqP=aqtA#6PC&`mIY;CX;>C+2hU?3olp7;EExlT zg_Gef&X1+BcrMyc& zB((#w*CSgF*<+C1L1f#DL|>7uC8?6gUW;rQWP2l9Qe-=c!~l`4E2$lkU61Te$R3OA zjv^aOBWF5nO@14A2=lZpJRG)zEn$23yqjYkxb6tg68}hRQ6U(cRiYI(3}Nms#LmsI z1fwyZ5oktht>Fu>B{CD~%NO)|FLvy`NFR#K0yM0IJH!3q2xOMQ7s>eoE{1DhC3p}V zjpW7fWpciTGvOTgiu2DsF4aP;i1G|$bQpFfW}L2nLRoN#jCGu)!2yio!EilmZ65x; z0`3I&g~J(-CGdH2K7$M4Dp&y?07oKu5!^)1mvBD35|)Si!84Ft3SS`SbGQhuh85v~ za1@fu;Y;Lv1?SU?nX*QMLCo^wWQGJ^F@qOSI*Zat%;w3kCpnE^5jX
  • cLz^b{ng z!d}QUhDG5>WG+FzFX?mOx#XOHC7+Q#3VXgL{iUwg;9R87Be##+BYV2p{gsm(%Pj5$ zC&3=@Q1mt>-3o3H%lexz)Px}>oM=KH6M~W0JO-W#&w|5+`N5D;PzKrC06l_QRVa&nav@wwUli-uEDf#nh^>gfN%&yRw^r^@!WreMW zwO}ha5t&u+9ddqw%i)c%E<6-YLGmj2J~@R+50O^HD^Vdh4LcGuO3yzfKf&h+`!h-h z!41s%3-Rc6um(H?2Ke|&_!c=o!Da9USR1y6laO2u-zDc)xCCAgYr>Xr0+K7?+vNNV zFM=Cj9oPm=Msf{&kDNlJ7cd7G!eeC31pB}ea4LPgoY^{n^dck|!()-z7j6ZoA+y5H zdeTeaQgZAwz?Y=$Gr)JGe|rX4iu5vD-|fp8o&kdIxpx}C3_TI1^EtGZ6Woy`8J*uw z&1|Fd+o{={5orVcliAJydotS@5O*?XdJ6oljVGAD-@uPKjoYv;OP7>cTvn(%Pw*5{ zU%^k1Jrvn8$d>z^Y(JzPgl{AJA$(SHL}TzN*K1|2a(!+Y$;~M%{HdI9pnOk9TSw+V ze9@3qaw=!T2dYoyg7=vBJ!*)Cxk6WRJ}q>oWFdS%N2GqHwPLhf1pZ3S$5=mtb{;3a zj+OO1>BQ9bqvBvQo=DC?>>Ish|B2MO0i8F(W{gsEIGDPl=+lX$SJS6G@yF$oBRYdi z^xiG1g}D6SQ^sjC`~-dmuZ1h&HA32Y2s<8z_rs0wD&*F}HBNdNd)7s8IlLGi!mMZs zTfx@Cu$@60$_|Bx!NXyD*cNsWVp~U->f}VsE z02jjvjMGGTv*e(08rRd|Bsdw~fTuRV&dla6a9_r=7iZKFuqzyb zQiyl1$8#^SE?faCF9ARKMNnNqSnB_-i0c=%K} z2o8q(;nn@&>5R^BxSG;6@K|z=gN?AdG29343-^M1!^@Fe0Uv}9!AId^@L~7}yaHYc zcSpk>umNlc>%%?arAS@|=fef?0(c?(5&k3;UnL2_&Y~U9mU5}BHI+mIbxUiFU^|y8 zqN&7M%7tqL#Wg3mhrZnlH^K+teeixb1AfPu@ICCyH%R-zd6dqD=ffrNWcJ6ehlmmd%(ls;jk%e2HV1R@JQGV9s*m!=CB1k z9-aVu!QSv#cpN+m_Jl{kuCP7q06W7jup{gQw`DypX7BFB+GxzG-Wx7JW)YkZ7YehD zd2o=9Y?Nd$uSOO&RJ%7~7zq)?#n)D&Am0*zU zYOxZ1!~?Ms0sfi<+vgbRpaVP<9tK-!J3(7Upgnv;?F-&>sUKvm2S35@;g9ehIf27= z1dY(s4IU1g2=mD8MOhEn4mN{LVRKj=)_`^4uJBdbe;vL8UxUqRh^5WpLGWO>caG%m z3vU!ju_kz#^WzoghsU|TpZT>>eH^rtTF6gE*K{}=e#0sCtuWj_y$-rD*N=j`V|@i| ztq9A&vT!F@9$tklYvJec3n6xV$aQVx>cF~iSNJ}qAHdt-?eIEyJzNiOfN#Th;4Sc0 zcn7=_?ttbU;r6g3yo=Ji;V1A@xEX#1&krU#_y+tIeka7%nOs+*PGwjR?gn>(RbW+E4X&it zD!2jO2v@^3us`$bA@~kE+DGv3_{9DT^V>eL7v+h)5cgtvpV+TvuSxu@9w4b}Br5(Z zp4b`PlV!9>o#Il1Txu|5`2&6b5%#Co1K@V70sI(V4OhZ- zLgvT=Jhwgw?}hil)yUbmFsqz&)LWPXc|tx29t@iZwf`CiO(|;zo5L2cE3|K6j+8XE zb#tliF4e=Oj&i9ZTxu>>&x3Q|d^jG@1n?%wLH`u4r^2yt9K0S6tcM-tybU_RcQ`NK zg^$B0;50ZLPJk2Pg>VVH58e;wz`1Y?JPUpezk#p8*WpL-WB4q54qgMVg{$EjxB=b> zFNZ6H^!Ymc@gnnk6MUKcSKtfqML1Qw8cc&@xxW}E9BINRDcP2i?cgx{b0Rzmo(%WF zhx@`)@$G4FC8ew2(c~NhKVTpG5N?K_!H?j_@IqQ#0-u4;!cFic_#Av5UIdrJH_-4V zd=I`4--2($^O3v&enQTt@E!OrT#6T$!Asz!@Cr(=6p9a%gy12S4(@cRn>Ce01EY1X z)(CEMsp~bBSj$GK5!~a~3pS8<9lRH>+y@_m55xQ6Mrhxde8Sk;HzpsG?#Y?l3myxP zgSX?kJK)9eGI$a@TYuOZ9t_*UKJXCO44wgp!c*ZO*d2C&U14Xq4X5QI`n4ykq#>Nc zs+b37!?|#KnYs;uZK6lB+rVY(Qt+^=@=E1+@JES__oZDxE=(fm=j}Q zYvxTG*i!ZfsTs7vXNSSpWhBXc*QLH@_Ix7@w-nT;Ru|YB9w5vk*MPFF@KAUVJP;lX ztHNrqHmn0*r2S3sfEr@)fv_R{Xbkse7VRU%`mb0y_cCwp6OtSEtal!tYQ;b69m$OC z0VknxGJKfUAA$G5`{4udL3lY9t$-uR83pg8Uw5f@gCod&9=-rygqvV{*a5Cb*9~wr zTm!FyYhiOFTfpncxgOpKZ-RGGdN;fs-T`l=^fq`ZIj6zX;cz$=?@xm_xIR2h*)#B2 z_#A8t+rbOr5_kn|TnSggRj?_g&0tx)UJl+u&aH4gyaC<_Z-S%YnQ(u20K61lCS>f6 z;GBGv+{fTc@MZWod;&fRpMn=--z9Jzyc%8#FM}Hy*$3eL@IiPXTmsL;b7SBwl7mgN zxt;@u!!zJ3%;(pHV@w!pLQsmfc7!948VTERkI(_0K_5rLJ1D&i9#2jmxSD>gf%e3? zj6K7iIG2*{4UdM$!xP{EXgdf_p$Aiiq!y!n2xUXzU2bQ279TtZpMlTA$Kez35%?$^ zNB!~eR>`4-`CKo6li?Kj2HtuLKE=Fw1~!I!3&)EGC!nPa9xMj~>Q8{v;SAUbZ+3yB z>DL%|52g3Pe&h^*E3o#9I_%vSr24?&I!!t;I4YNHH|C`^YynqK1 zQ${B){3XxCH*sfoGi<>~9|BKe1`LBAa7up&pN7xCS#UO-0;j@@;BxpNdqeXBwoCEizbboj@V|6ZE49|hR zC_Nh9M$R4ZR(LzylRa_|=zqpBt%mGAli)0ve#YTucrYD*&4P!s54DA@Wo+1~I^y-t z@J)B7yzf%Ku%{McNB^1hufp&e3id%mPuKyr5ayBFkFwsd6Kn|&fvsRoSPRyJyTNy8 z|9$u-d>1xh+?&D;lB2B#t)#c~a|)$1;2fCbbBXSpay{W5*kIpy+UH37#?wAWCZC__ zbCnw(Mka2Ik~~j%V}!o0>^uMFGcWNQ-~dTo4N>u5a^~4}V()(KIY(Z4+dl5TsRL-gp*+M9n6kQCp?{; zU64=Cy=sWf$+-{miK!zH75|?`W+qPrv*23p1lPgN>|$NqIUTo4CV4{fcFABA<2@SA zgtOpj@N_tull4q^H@pXaz-N6Q!uR1vumfxf+Y807LDd?F<%`0aM0`#T|Ro#XCVx}bMzbt#_)cZc=idDSHU0@xEBy6C%}pDYczZdf58uhm_J+b zn}BWLBJ$6M&9JsPoM`@hwt0?#r;@W7Hia$VCs?u>mZHTS;Al$EgrndX*oW5p!k$R> zg0tXk*bcV0IaodyR;HCIurs|r0(L^OGkh1x_u*!G^f~;V(jVbua;93+yJ@fxIfda? zaBHE=mtd;Ss9?IJf_JduJ-83t7w$|8RbWk5`%e0P7rX=B4ciIP-`1rnFyAY}?O{pS z+DWu>smAzmFW3m~4UcycMW|a8eu;%&32AeY>r*F@4+i43L9iRL-C+mV5e~)U!(dIc z)`Fj~Lw^dZQ(6O7#S^vR-f$ndfmUvW_u%V$;X{-@438qGCw#jqUWZ@7ui=OABX~9~ zo&(>IzpfU%33uV|!B&CalJgy0isUl*1R9=%ufsRsbMSe%0Lg{$GjcwMFT+>h0Q^4? zUI(v-tT63v@?8)oTr6oKbx5~6V8CMg;GZO67qWEzoX$IxEKzF!(cbq9ZrMO;i2#_AsT0? z{$P$vEvA(ctcKg*6JhTFjHX}cuc4wiyPOD#7GM!L}*?NaBu)Ebw%+ND;z zR7cuxix1nuuGoJhYzN!J!Hnh*SRLzXz(*PJ$6#Sf?ca~DM&GN$2CyMKmsZY$EAZPD za22Ji;X&ja4Buq0cnf|3zl86?_uwMhT@0V*ta}EQ;+|s%_!c>D!wZpI0v|)eq4d)>_AAU^EC-4RMB3#GFTn*1;o{SOdC}oR-LqrR+B*%Z~=?ZsY1cqjiIG zG?mQ;Ee|TwqpegIny(Zs!D2WbF9z@ycq^O-=ffXZA3wqzMzRQ8i-)d(_c60J!lulK zX0QP{4Pi@cX$7~1+reF675EGz^DKOmGxaSYcE8R^c^Pt-!zT=*lp zeuBTkLgb&v`FB1%iJX(+0=N(sL32^~EdF{9o=xdFa5+|93@?M1!x7B?k+6rZ@?Z(N zmcr%mV%QP8JHdl!<6!tD7Jmi5h2O!6*gXmEQBB6PK75>7Pr!5Gd2l6M1;4|-?_nJ@ z)P>zC?Ew$Ns>9(LcojSr9tX$5aquFnS`Lfgm!fbzIX4Iy!?A9^8sk#uyVP2jy4Iye zxzw31b)HLI^gc-@u{F z?Nj0B?3drd+VpmJcnhU>!Huk!N8w}4h-cu@uj0+LnXv+P&T!yP#*%D{KX z`2hCAs{ZgKcq*Jg=_Gg?yaO(PXTt%sG7t`<)@kr<*3x@$0Bd+K+=Vqz6JEd?TMG9l zrzt#2w6QiiQ>QB|#wy$vPNvQ@_zkP=C)gHtfNSA3@OU@?Ud-5E28+?&R&WD3x52*n zu^(Ij7sA1C2>gM5{tVA2=K^>tJPlq6SHh3+(I@abYW)I-lXC_<4UT{(P^%A|0;j^( zunnBfe4PnPGoN;XZRkZ?*a69o@MR=lhwm_tKY*Jl{Sux@&Nz4@7TyBqP&yZOfk(g< z@CtYXlDEP)u;eYcoE}{Ym%+Eo?$gOLz)46~}^ka3MU4{1f3Eau&hoXys)%%vpRIvuPCU z3VXt8%-lL~M^2{la6Gee3Ven(o`+At7hoIOI~=xxZDC(2#ZSZO<(cpYJW&Wg?TK}J z!+R-x2tGlNpM%fiiC18Ma)!dUY2!WkCVU^(!KQk!7TgWK$d2$5EXOWW9)3j5W;hxR zXTd4tOoMm9d*He7LO2r1vG7B7lTY9<_JosR9sIioT+W_wDQrQ`p|Gb|h^M+!rzb4Q zXq1IBsWS)u%4ig0d^(fv3a^J7;9z(%yaNBOg4@zwNq8qY_rqfNXe(F*ZVm6DZ}-Ey z;6}Kb(zS3UTnBfdv>L1gtHWcZlpc0tgnPpmmR5zK0&SL;EVMCHTV{#AHb8y z84f3rGZ`KNTf*mQ@kQ7MZHL0?^lb*52q(eu)C%Bc`tt=`O3pI)2{~WF?a3(#8=+xu zco8|vVFPmZfsM#%4ByA^AHY{wYp=lytl3KNb8^0h&mj3MoJ{M};8~38SfThG-)}Ec zq@LIO;CxLvsU4iuCM^q=xYP_o8fKn zG&l-g#eBRP?uZ>_;e+Hn4#zNVXTdtKF5H2!Edxu!vhXqd@+5o&J_RdLt1`R+$(!Ky z@Md^Ck|)6Othk-wws1SRE2X=`I&cqooM^yn$1>ad!ME9iK7>2dpDM5hcGQGxk-Q$> z%*whG-bLv~*omBO@Kb!Z8E%3v!OOAZN}<@{hu~cq6F(=M4nByI2&#&9Up`nJmJMp; zky)!U!KK)>5K06q>6#`5OyK-dDFjOC}nuNmR*U_C6~1KvUD z-SA;X?=kok);D=aK=zm+usS1L3tq?`vkV?gPBYjA$s^&`jO2E33X;>|4~**1upR6O*THLHKR6Ix zf>$qx#c5@0cndkVLpv6`d1G-b`F1S6^2Xw4Z!Ai9W3iC@AMwDi@OxNDe9m}}#QUea z>oT-f9v(_-?cgi4_6B?xtslbA82_)}7;?tLn`q}YxB=b{FQ&cA;YDx-EJJB|xFg&d zcBaLy@M&iJbFc(fZ3CB5x*V>d^>y%Sthx@iAg2|akLJa2E<77&`e2kZrF zG4gd`Iad45a1x_B6+TOkUW8A>P4G}!X$M=w_HY!IkAc6?yTbUtF_!EDAE5MM_zb;x z9==5HUWJ3n83x}$^9S%P_#v!|CA-7ga1XeN74tIOiIulA{FI!};F)L`2d9!V9o`M^ zg%`jja1@f`;YX~zPvMEIq*LH-c(p#fn3Z%HY)#H#um_U8U}@`lI19eZ1NbR>70i;cPrM557*1-iEKjci<7U(j9h&J>Uc^pA5HQR&NiRVo3}545iP* zSLns-@I89>Av}$oGvH@v{tA8yzlM#mWM9}2?gw9GHogukGOH`YugLiZPC>&AVIkcc zOG=OBDtJMBLh1rdIjJ3;)Js|xEOn`wXrB%5hY!Hz@DezQwr9e!c)2|MoYnFbJe}D; z0`A3V?F+A9_OF5+$>{=L6$^ql;4#!X9#$f!3S2;~#c;c7B3}wFr}R?T150|rTj1?* z1RM?5GK$y0(zIR94rNQf{)Ydr{SaU8MuMcTi|+lE38LpeOMRn3Hva6 z`os5GMIXV+v|bfnOX+%eJ2UAncpo$D0oawC?r;T~R|$2rH4fer@90&gIQTG1BB&-_ z^Xmj_!m>flJTmK4Cb$f{R>L}sKt1>|z1$3^GXk^VU^onZB3gpa;J)wxSht$w?*^|W zXFdFd*;knK*|c&V9420rJ_KKgpGnn`mPy^}N*@qUlJ~gym(($u$JMT~ACNlQ)&IiP z|50UwVsc-D+vBG&FU2&$}9@JL`{hsp_sDrK@Q_0@sf-TpK?+ z3mQ0m_qoz1U288m3kJBnkDVvabE&${f7}mp zT4%ux&Zog(lc(HQLK^p=xWgC|8ccoc4O zt-np#>+odFWwx|(w!Y-%&BZQnFKT?@{J6}e8amtCxzx_C7hAhtobGz@kXlN+ySg@Z zp^f8QAKwu#2XDX%^s$`Q3~C{}j^3??w`gyIyD7UJcGg_ldK7n=5@#EeM_vi_mhc=5bZe`TH1G|4Uc@CzTC~yFFup zqnVt>d6VNA0u2FKRF8;I(_%M(x+T&FFFeb zy1Y-EC(n1OU7ZCjU1|qsOJQfrP-n~CuH7E4-A&G_lCJbJS9+bZV1u*jFqij+t1;GD zaI8!1?rf>-Y?z?Ba4ibb6;cO9r~s z-p;1l&ZeK-%3kEGJIUGfl^e5No#xwJ=|isFC&i9JV*hcP#}#ioNb#SnbMEtT9V?xgv_JI?M;)yCjEXZIw@3pzQOr(DmA zI}J-*>1wB8ozu|V<-O=?oZ+nR?ou^fKgw29uT6CQ80p&h*;&xY>D%Z^pLVTnauy77 zdG%attz2qH*KUq$cbIGU9@oZEu8o(R1*Kf+<*xL4*V>KFg2P?jo36$%HGmz9zlBI>y)O0AHuges{Dx(vSJ>KeQb-=g;Kz;2}Ufcw!K2g0-Q&=GFH z!^TKiSpEewIKeClN0TxJen<^J^)>#CfA2+W_VumXkADy3+7NF$lz)HCr)Yk!nZGz_U%D5E5SC{odiE2nxDgUL~T9XNU!_`FDE5{&)|KrkJA$V z{UBvb^JP8~DU)lJy=@i#eL7{G3EyU{ybE`vKD)sCxjGrnq}(UqZ0hqQY)(o`I2O-$ z`I5%-?++s_gu{r_Wv~P62y4rjhh;YzN)0@qOg_uxmgYc0Hxlz#AQJg@g9eb2uSq87D%tq$YgBe)iL z+pGBZ_l)2lVSh&CAXtkS90ng`L{5dRNNEc@VA&CtkHiVyjO7?ul9-i(?TA@>_!L|K z`@=zSI&pXmmZp@la5*V2!BVtmSKq$U{Chd=dD*vb75|>ewK?8)F8|(#Yx{fKn*94* z;@%m4Ob>ku%Tekca2i)1g-_833*a;K%_4XrDW|}D@jTg=^dSHK5?||JK>MzN-Cz%R z7_mGO?nC_cg|`r=+u&!k=4;=&b^QAb%IM(BJcoZ@O`WfUyD;*0gH5PKbGU}9@4-)~ z|7Y+U+O-}ICS@qxi09vZNq_L~I@IDgU#oij`+Ba8&bG~PGpdYh1?qj*PSnI~<^Dy= z?%wL7>}$dO*$RuB@m+zKRDwSmagvX%fiWAeF%1-CLQ6ka4{SPFN3p)`y5!F()Wa~k+K@@PW&qRcvj-y zZ_ws7+3^hC;onblZIQQqj(;D*wZpyb5&XM5{d@uZmXZEF+>27H!?|323NEJ4pNB6p z7FNPDNjV!%!}DX=CAr?o{xA5(MJ4-RIsHFaAIl=B;i9GU1T+8NHrRhFnj@TvDEbTNrbh=({Lo0^Gz~3;u#{ z!nfeta1DF|u7;n$weSP@A$$kE3*Uq9!_DwtSc3NvWWp_^WT4lhzlZn1`{88xAe;mr zfEV(9slM<6*bDZCec;7#FzgQpz=3cOyxW!TdM_C7)l}Z=@Gz_nYrtx7FSs|{2ObOS z!h_(!aDP}69sm!7GvVWKHk<=z!6#rp*dIQ}dz==-QYBnncZA!+9pG9lKZWD4yaSGh zcf&j3UGQuyJHRvGnXo-P3wDH^U}tz9JO`c&`@)OhOL$%h=lN*f$G`7~-LdNdyTGon z8$2KOg1uoMcp>ZwFM#ji?S0sal-95fYzt3=r^8d=sjxn502{(a@Oan~His?X5I7X> z3-^PMx%YE1a^`w9+pEX8G7~-uXTV3`boelw1|Nb`;axsj3t zc7+d+b298iN*8!fwufMXS2KMrpY&>uR}bQ23ha)Lp74Cw!?8`)e{Eeo-o|Q;BdRiE zu>vgZn0-b6Kd8d>J>hOSSp}WBb{_l+&tJoD>GAL2j?CYk;8&!44J*P*a0yqJ!b@5A zhQkl|p7n?DdAJO|0AGaratGZX{y@r)@Jsj={2G1(Z^H9vcsm>iZ-ryvy{y3Z!*1j{ zAGU{Q!7VjhWHa`4{2Tobtj!(mF!&1V_N#Cid!-lPAnq4~;b?dZyaEQWI;GcuyTkIZ z8r%yW4Ud71VH0==tOf6Z6X61P>K8l%&+>Qp36ysaJj~sL>BB?3s_oUmUJbzCK-dkQ z5BtK4;5G1CcniE04u_Y)(){&%H@G`{r1J1ccocjIu7u;^-LMsX-Wv9V7r=kuX1EHz z0+&*yAp}xp;|1;xAZ@t9!v6%Q>5!;i0fLdbOE?ui3>1K})6oDIuxwJcoB z)unJBJXeR;!0X@_@Jra5Qrg04@DVr+Z^Plic&i2HQsO*Vj;p)FWn5hjYv6fbI11hf zzk*-G6Dj3nI2}F;@1X}L!lCrqF!-M9o#1`A1TKZk;R?8)>(!tp{GOBz@N@VDTnE2} zH{kh3cpDrGZ-%$P`&daQ!E?xUE<72Y0yo!i<^Bsd!N1_a+#e5teXzU`zRbv61!pnS zo`93#gYaHQ#^A-=vo3)*!&~8%@G7`B_1g#T40nNhzzXnCSQ{P->%x8EesB!D4Nhf^ ze;Bs&_tEi`cQ-uL-zg9Bs+Ly=deskq{oy(AT-Y7xKu#*KqZBeNI|#={V}84p`vX>yf;tKnPlPCSf<%ki)R4#UH6Sb~)8 zU^#M?hil-wZ~`7C!sCc=J@^7qT@DZT5jxDPSw2GZy!zUCAy&V7HIULThWk>h{o!M@ z?s51mDbK-xT3ro~r&g`tC3qML55V#u_yiv2z$K(S53j|;^{@>dPJox<;WBs#mWRS8 z@$eLUfs_~F4S2W-o`i=}9BJj-Ze*k0^{NV^Yc}i2lkf~bk29DF+rd3yHTV=<056AE z!=qiagSzkpcpCf;Zh%j~r{JT^mM7qe)m`4xVQ<(6egeOQf5U&^EM~})@Dl1h9NtID z1CANaV>ztC z)vEAyuC9TH&^NWl0{Mhv+s-lnB2lVeW;x+^R4Y$BLT&)Kuz)7$dz1$DJ3g3b& z=sGC_q?h~#O4#tXW*HB zCD?)f+zIXjYr<#YVt5@K4eQg-jo=yZ9QYIb1ulS#;atYT0(d4hJ{PWo8{m9;_*r;4 z^}7mAA?0D;^Z$BP$F(RU>%X83Z9Bxpk$->W)den|q`l$O>bqEy_ODlW(gzb^YvO(~ zTupzx3qK=e9h^#k%z%C9j{)$0JUj$X!}2Wn0Ukbu-;weYd>ju?!i({6sUx-f#Kjs_ z$+z@F;y;DRJPc>j_Svum=L_4zhFCU-55h;_Kzd{-d-5Fjum`30fnSmGjqjNQsLlQ^3K`DRJ6?5l5g_elpLVosJ!yY>)rJV30{?;;#Oqoj zcoV#XlzU(YB6uFGMjZErr<3<=xE+=|!CUY!4&Fz~6xa<9yKyQEO;tB9d0D;fw5kRyal?iS^6y75F*)621;s!|&k_ za2@>C5ijq1RgIqN?DkB-d9W6rRSt!HNx29vqNkU@A?*D}z+I_l8Mr5`3=e}x!sB2A zxIa7)K2PhG!S;SN>d3Y8U{BZ^j)Vam1#g0b;ZRtUx*h;`rPXENLGUp6JX{WMg?GTF z%!3xN6FeXO4mZK);Y;vYN_-yvNs0f$BWO<@_$xcsKj5=)G3;F3MZ7!w3H}aurayLp z_q$kUIJ?EnuNUC8^uUd9Iw_CA11b9uSO*^KNd6MeAL>}IcBhQNSPq3(!mHt-ZpM(~ z6R&!^*+SZzKCPjfDWqk%d4ih8Y?}$sVODj4UohLgg};!p3C?G>ErKJMZCAm$cvt{? zV%Zn|h=5w&urw_y5BDY4L2zjGtQrTG!=1Q;mVqzPb1NNb&ssM+ zP?df3K4Qe2j?Z?m7wiqE(>ssBtC=M?z!&hm9FAq&jE8gSi}`R69xjHZSjl&REh+It zI0Mdx!x@WL!nN=#_&%Q3!V;vEg7qoA5&Va-xCOolSHkARqzzmHKZG@?;lA(z*SZWB z!FL&dAHj=g^B}mMlpkO{+S3r$hDSJ(|6u%GN9ql5IJ_Jl;QAlC_q;ma^&e@k__SkP zzmxWtSLZTzy24!L1+!=yY0FJ$ZtgoiP9j)oWD;UZWG%e~=)cz6WPA?0Z} z6c3lf`gmvx_oPMD;GX2F1~06hRrg>Z+zhv4B+em@^I!>jyCkdv_k#1`GcfD0HOtR6 z@ECggICu&?9j=Ezz$f8+_&6hFHawL&w1c0+uizZ|avmH;tuBN2lQP*c!`0v)ua0zm zOIm4qxjyY}2uBl#TVN*lo9*BijQ20$C}MsStVe7c!ew}P5xzyrJ8(QPzXx_C=I6oN z@GuTG$Fe1S1rM*ok4RYyAHc&D*aHu};LXJ0cDN6HR1-c*>mGyu!VKzPm%gYE?}HD( zzQnvgTn*obtBC(=@Mub@3s=CGBP80d!Y;)BeE2CTU-;PXPdyH!ZAZZI#CihUM4rFk z_tbR*tWS&@!SCUZa3~&z!|RFBjqn6wbTZtH7?p!9$kht|2LFUt;^AsI1`oHxGw^U0 ztcZsy@EY2DBixf%SA$Pe^M$Y!G2I#N2M>UY;1YNvycsqi){WuW@LaeN{t6etC2&6d z@eJ%hO*+E$@CWz|(O(3wq*hnMhe(;`du5APN4x&XaPy@sJ=K_)G>t@tJ{k+RXIAV0 zzow7Y!3o6kUU(ugJO!@7!+Y>6Qoe!HiS1*sAF&+>AH>5{cqW!-!%y(=8T^5ijc^Vg z=E0$O7!Dtzz0=?mv}g`2No{w4O^JUC_%NIfFCosu;0N$y_%<|s083%HGaQSDJK$te9)dmb&>J3%heKgAV$lMg2v3HsU>n#To()ff z?cmSE`d9c5{1^TKH^CjS+!2<5+rd>_eHDHIzk+YTH{k~OBm4$_2cILVOW|;KLYKqR zcrFVo!Yc4^coeJ$8^W6KAlM0Zffv9&@CtYpyaA4em%w4LG_@)V4~2)rW$;CKJG>J% zV=NvIyTb195BL{+5w3(wC}kP^htahK9?7ojX!sjDtv}%+xCC}%O!t7l!av~ijOOKV z6p_3MK1#|=co3!3f=9!;ju~!^$#kP1RoAQX%!o^{90s!Lop481 zqMhKk%#rWlOm~$M=6dy=8?&VS>D9Teouqa0s*YRJNo(ZQ4Ccyg*qJ%e9j>EB8{i+L zY=#S&D@);(%$4ild^|h@`(Swy`~?rc!|lkm16%=LhNJOtD=bIr_wa4oKr6!uR1v@B_y9$8Z3xxEOv<%8#%$1nkfFyaXP_2s#d4h=+c#8kYOOhw(5SK1Ip`co`l>!p3-L2CLBey?oogC-o;s z*J@gRG~?>H>^5Yl|JVP6AMo>Yl%HeqQ$M$Uf-1D4I_zKF^}!{u1b#}vif(+mngk=g zI?;_m(q?-#!;MkWPI5j_YrT5HjVjWHxN(3w*u@t0p;tX!T}XS~r`2;YC2g};*ZQl+ zy6AItiO>6nPrJkC=#U+$;1-{^iMLzn^Sg{9onpZFRs2%COzTnkMK5CtP)b{hWU*lC5U;C9lt&Xq#A70hq>eUC{OQuh2;p6>|SMT}A z_w$iI(6{=1ue$qIzv|QK`d0t#RY!L<=mtv@+wyQct-lXWBV{J+>v9Hz;Nisl7}(2~ zQrX#MIIAhX4s(6lFkf;5ANh(t@)ap>FW8ru4}$-~l0?3ekK+|yo#bOS$E(MDL{E0P zGhB^6^=h_{<4_;R>wFvP`uZ;QZCLHo?(}Uq$G72DpSP*Ed)epxz^C2s^PZobmzv$? zYqlS)obJccX0ML%?VadVAK%{By;|v8ew6pR+^dzo<>&d9ALncTomZFm+F$Ey-^SN| z*X-H{&3ukuyc+5A-s1C~?(=e@+|o#lIQJHIY8_HBE} ztBZZx-t+2B-^vEQZLfK?+PCro-^vqwP5<%gdSBDKd`-{wHQn3S^bDV4dv78_^1EZEW2E9eHl za|auFkR>A9^p_`LyGG%-;3teILF4K6;&q z+xc)e;ovPxLDLSX}AV$-doly_)Hxa*E5H;keUrK@2x&>JD+#Y?7Xz-249P+v}j-7jvKr>%eUiM zub%QPI@^2r&a1n9T~6>dc-zQ|RqzV>6i>f&p^+^faD9e?|o*wwe=7q1?5wF;hqom?G)^WoR7X2JLHcT)a=&$!wJ zOW+l*e!;cyDc`!@&Mw1U`PsKF)3@nGuWs_KE9+}mlk#f8;jWIsm2g)^;O_7`AB#JD z8{7C;Jnq%yJ{F&Q^^wm}(xK{A>GhGaV?O|28 zH+&i{gjd09;ju0jK|OdXYzM!GKf-zNX*kP8F_;5Sqb6s-FW}d3uDdSVKIh-w4k&=_ujKfz(-z6_2c4mZIQiNh(d3~|^U9#5{;@OQWg26(sz-iC*9 z@Ju|M4J+ZHD!i8V-UKTW&%NLR+WRcrk$CO`_lF0<=ipL!6TAgBB+gA>2iOt*41a^q z!KLtN`eGqGhnjSP-@_l_LL&bh45-yLa4IQ}_#VmdBmNk#%F#aeJ_>r zWB(g^=^kQvA3TZpoeJL}_xtc`QoezxV~6Yb~WW$s=ajD)*6e?d7|308$iz&fx#Yy=O02gA;= zE9?a?gjd3=;f?TSI0Rk_ccWJ2U~PB=d;zY2;`+lKjGhS1$-GUrIZ)o zW=2p3=|}PR#be;_{C#l~d=4&!=T~f5IIZn>)e#{3u+;2!0XXKzv8T8KgW8 z52gl(!eiiZjv20;?VLZD4V%ZP=iiba7Nph8fFTqvtW;~36yHno^ z@IZ3ah9ijZRd6@%4|~8F#PV@CiV=Ggyo;Wl08e0qoD83UbKw>A_*L*rxDI|ouFv2O zr0fJ6GAf$De;ElS&@Z7^!PeC91o#2`816%lRfm&YZ8Kcoen{_s0teED!Egg9KfwmX zqA@%i9_2{>TKF49>P>J2yaLuGa`oT?q&(=@ZC@Lr{7;6;2FydPY?lZ*313^)}&49{hRbc9Xa_zs%EpSZda?(M!~ z9_#~uCgm5$43|31|7!FjUQO}pA%01^EZ)n(U14eXtNT7m@EdHvtZWEdQbt?Y1h#

    )>iid=tJ3UxPK7;RnDPa9=o|nm-3G zgo9vtyj6xJ;m&XcCB6nPgIB@*n7s$XJzy0$8r}{Y!9dhU;YxS} zJPIC86pn_k@+;EpQBM3Y)`k z;d=N1{0N>-)Xsn<;SO*noCWWP55NhG!h7J^#GwN`5uOD1fz{zsX7=-NF8^JxeS^=KM)zjf_unhc}+4u{rK@InXt>6i; zDLfwDO|2%tJK&vgBenV&UQSP41rLWu!^7yQI`A`6zJ^azlSQyE90*^+@>Mtj2JmKj zYAkF5kB6txBkkdKa7WmWn)ip@VGq~_M%vgM9ckkg)GB~S!aDE>N<0(Hm$7^Wj)YgjTdD1Buo-Lt+fmyy;r6f;e2ft?3wFYDXV{$;sxR!wD%KrVr^jo+ z6S;aSY{Avma0=cYhNHMT1|A3xhcn&3vUD98Kj&IPbB43IF6Kwunueh z=fe4L6?`4GU_>1cJJK(m;ACq1Al#MKm4?|Wz6IZfGbw#8>_bXF*o_wTgeQ}7I&4WwTlf&U z9)-7Xbu6q6kAySfY`7e*ghSwP*bi@mV0%)|fhUu4I-EeteXt&E1n0p8@Kw0lF~jXF zTDpj%P9O$Xas4_t9IqoCu{aZp&RpvT+hcK#w`l9Vor3LDtfs@3u&pEBI$*Jg)TM9@ zeBWC~hFIjjK2Ms|R~E$g4itIf6TV+A&^@^lFH=o9xq?Wh+XXO=-Qd z(}FJ9Ik@@=S4aD+wY(baRp0C!!FZom*Q+bN8s_b$__P+;iqht|(ooYW_i^|noC;?+ zX1M6J@;!2*i#KWQy*j~PJ=Le3L%&qwlWAqRC#(qffE8d_SPt$E%fo7LFIWXug}cEr zaA&v++!dCFja=)4X0QpLe4D|&xw;Rm4r{>XTs|kzbPd~>ff03=CEm~>5mO?Cq55uMnA!O zoqt1@BYl8N;om>Nok{%{Jsa!a(YupA&|7bEssI09uu-Q3f9Zc^>)>avp5u_w zg)hM6@OiilwxHduU_00zwt*+Yli_LbLU<7z42QseZ~z<#FNWvAuCN#E1G~ZQum`*V zK1I=(?5~AE2$Z9F4ljNz6U86d+Wbl>i_>2{GwBW zfAqhyb?~cKEs1WVpU*@``uPNOq@PbkNBX%hI?~UVpdn} z&*!5f{oE5B>F33azNK&>Tm-*$H4eUm>*4qCK6fJF)VBT?l;DizP);^#!$V*#_$Q|y zo8a&854bZ|cY(XY(l7&-fIGlaaCcZ9?g=ZxDzGa22hW>fCMny&l5l&t8!Q9&fE8dR zSQ-9>hri*!a0}d#t2@E6upAr!2f~lxC-50^Ep*H%l`*MfR)|YvwJhtOS^tU33ZAH} z<26xP8A@cuAh{*Lpio>#7wk*oEyRK#BcuNryP#H(gmDw3mxSI2u5 z`fKTPWWAJIJh$=c1g}oYQW1Zrcy+2*p}*67j?=w5!>jgQot>p3{?760T(3fZ9erA- zB&*KeUvkuW-d}Q57w<1Qs;l?cElWkl(D`2V@K?jwhw6eHuJ-bId;6;w`n0}2t)Ex@ zy&B-vK(7XQb+K22y}HD!AzlsjYM57-dNtgu%e)%l)#YA|^y&()uJkGhTokg_5gLw$qX521}J*ru1^9S17$w=~YU~?Dg8|f zw7X$vm*sBT+1lN_v$ea0XKS~C&em>woUPpkDqFklQMPv5-)!x+x!Kxnf3mgP=45NP z5zp3co1LxQMl4&qZC18+o9=AwHrLtOZMw3x+gxR9x9QK;ZcCr7-KH;FyDeR|c7H%h zrOq07-hWcHj3xKSuHotE)mQ|SYp&f4L)d33PSgPfM}xj^Y>lwPRx zvq~>g`Z=W+E4{>NssB=?S1bLQ(i@$Y`nVcr>#Pls*V`#w(rNL(z0=ah3QD`5w#ZJO z>a^HzP>vy^^9Y4-yp+4k-yJ+kBGexf8>FH<&eDgCz6Ym|OR z>35ZW&uQtG_m%$E>Bx9?BO{{1wA}81!xh1)h?himz&ZI#WCxs+zeIMxIr&S@4mgZo za(2L>zvS$ILx0KH0Y^tNvJxaGE!gD7aZ)}06?zO(q5oF?Q=ntTRqkj1gr(O8Wi?^gcP$rOSO*?~`{|>B-VD_Q~Ox3iK|y zysE(-O2^tIS5P*4DqT_ON=n-<%vC*H z8JdKtK~trhg+BK8WdzN`)bQ*$I6ll5o*oCS!qlL((rrQ?;SM@z8>WV*$iazWzVIA5 zI5|uWM{7Q4ZRN`NK2i;OsCp^qSMD za?m048lEc$=Z5*iljWdOm>PNw&z6JE;q{d0^OXNo=q}2CDs)%nKNY&0@_)Y5a&PP& z>K=aNg*_Om9QWQm!`#6IPRstTw@U95riUlhLEkVnJgW{a3R4T&X>~tWbJ?Hh)9R5f zU1F_It8Y>1`m}nCO4p~=V^z97tsbY+?^Jrc(i5DPx=nOChh6v#m7Xm9nDRMO>Bp7U z`|w#R{RyRG?ZfqH^=xIYPpjvsbiEIstJ3vp^^+=HpH|OP>H4(#DV45ItLLk9eOmpr zN>BA^^#WB^Qgsgd@Mlz6FDt#uX&L{oDE*q#IhMG7& z>aS0$tEzN;T3t)|cQwu~x3Hg9H&E@;r_~KrdLyM9E8RrtSUd8j%0{17H&f}UIIV83 z{HNlyx}EbM8PDO4JUnX(uiEn(nVGfye6i;>GBcBNS{?4G?RkyN%tW5t=;}vjH$SJ( z_o|1#8t#EZmD6t6p4aeqR=oo*sB`Gz@Vv(P>TcIv=^je=R9f$V?Rkv^PNj3$0o(H$ zk$9%tiSz|({O9#V+Md^l^l9AZHSA1!f4_6EGwG~PMwxad9i-wMTKi1JIkfhfigRe~ z)6S&*XN;6QL2YN!k-L{Z&rbE3wBC{TQaca5Bk!%!^^V-mq$B;cO=s0P?8xm*x^V5t z?Myn-UwM6k+Rmi2_L~Rz{df2rh<%4JGt<69n3)-V|1de<91OiAa{ioCUOSV{%(U+i z`oA*UcL*bQMEee5Bo0}BdiG;uE1km**v_QWa|dkSA&m4(ntg}R-lCD289o7RZ_&ui zw6|zvW`?`noK#M`*hJE72VCrTzT;b26VUwuDtWSE+h*KlVXToHOz-wh1H z{OY@bSBI%Nc@5vO5nK~`ZQ|n|To>k7-whlUrsm|eRha*V(5w1x;7wtE_1(am!_=I- zhEFgDw}f8RcLT?S`PFv=$A+oVUL)&xveWFX8$5rb-rf-_!t%YG+yA?Na(dQTzjY(H zBh0VgyAj+Krib7BD^l;MyE|;5i?QrK9&xD>Tm7BCr&YTC&Y$}coosvkoxf*Qy8h1J zb1Hp_($6dXg40r;Sa05V(b>peDp`7k^7&Gz!x5OYH*c&Ay$2Q5x5i#p>H6u4RVrP7 zu>zMuF~~4{@zgOss6^_YE@QJbq+i0H&t1cRs5?sEu%j- zZ{GM^`O)9_({J85WQTC1)>1mgH~!RUJJeZA?e+KlYO8epeZNMb_s~mD%HF)eU8bPk zN_TSDPeCfa=hxZ!kBnmXHy0Vtwx72BwC$()gqqWunA@~KKV_T>t)DVZfsWNqStYh* zKiw}}Z}PUEE^=?uC>(q0SnttD);?PM$=jYfuW!+)p!RP4)m>HZsRyWZ+fzqQ=n~#v z$JtXS@)nJOs=sVcowa}4#&uvqMU`}4u8Fj+%uM6X< z&ZrZ9e_iOcRTzPU-(MGcRcF)*zrQXz!pS_XPQe*kMA7mi=qdDy$@B0D+tZn|(3Mx9e9vZsDY?Zxz-dZkL&dusa@V5C9AW5qgwJ+l3J%Gl_r%HFu3-ddO8&LX5g*SMNVePTVsk*r@# z(SB0<>nZxJ&Gs9Ek-e^dE+nh_v+smKQgsgJ&HDR+i9Ev*>o*4V-q?OUCG6K!{I=j; zZsmyFbp!kL6!!+Qy~DNC&YSno8Xa<9*~Z^YiM~%pe1&`F#D6cv`Hy%Fcg~6bUP|aS z+&?G&Zo1HGxQkBw_fn!GocInp^p}FYv_2b7g;r<7`kXjfI*d)Uk~w1M&FoCJ@wdBq z^ISN7?YudN@!q*`>?Q5IS^pA>K5w>PLP_9US@u<1ok{1gr%v@-=k%W1&YQzMZ>&9a z@p^{C&YS%%($1SRGwr-NGc&x${LLr^xm! zhMO^R-jc|k+4ja+>(d|~%Zt4l?A0Y+4e@HISHrxz)T`lMrQ{b&3g6yXzpGB~X_KW> z`z(g-jkn$p+p`#vm^>FghZ3Fx1hzM}y|LT(=Jow_Iqr?^{d9r7Ps84)!Fn66v3XZP zBKzdr8X0Q+4j@6pSJyU)+!x7eH$uyZo~G|ncMhWbK!V5 zU99g4+J4%7va$C)NA~4g?V;u^7V{*qB{Lu7tWfX;P=#tyqnI>sMF_++TQmZo-L=_8Fg;n zO*d8TVjG8VeN$`2Bg$gB(nb1x&w1N>gwZmU`){sUtSnaUul6<$ECx0X?2eQ3UwY?pQPS7>%U#H{@XR{ zKlh^^yJh{CZR1`>TsG^!aw;wRn*BeFlf@#%u_%=>nZYf8t@ywVW_dR1JE!HZ?MJx* zF8XK&`~N+k5F8t(26dG_PU(6|*AF$F967^i5S=QuY8agw-UFmYC%NmQPf_|brQ0ce zrqX9A-9hPdotE-Dsq~AK?yvMfr7u?c5~YVKeW}uyDSf%pS127g9k%?xmBiv|mH%3$ zuUGm8rEgODW~Fac`ZlK{r3bewJx=L6l)h8xyObUuYSsUD=ad>=-!>)DnBaVio~ZPF zN>5UHveHwOo~raTrKc-BL+P1H&r*7}(sPxbr}TWK7bv|@=|xH}R(h$@%amTO^a`a{ zD!oeSSCxKU>D5ZVrSux5-&Oj3r9V{qW2M(B{h88VDE*bv>y-Xh>Geu)Q2IxwbDBFc zE;cILUzGmMX;}^aP`Z@6*-Lswr^U~KN*}CrEvIGn)K=+-DSbp}6Mwu*c}J=IM~C@? zW0kI}^l?hpQ@Xy=4U}%EbR(r3E8Rrtrb;(cy1CLVls;bRmQG8%S}EN|=@XPbN$FFR zK27O%N}s9pSxR?M`dpw6GhMpql1lI3wD{jqrJtsBJEhN5`Yfe8D1ENdos>RL>8?&k>KTsj z;Cz=VGpW0>9<1~brH3g!TDQEgL+Lk_e%tA-N_|IJyr=XBN`IvECrW>+^yf-{sr1)M zf1~twN`J5P4@&>!bXa2E*kAvx#Fy>i z)psNU+rvjbC)*zW|IQ!Oy|SS8@XggsKYkl#y6xd3V>{jU@U6nW3|cFltUY`i<+H8Q zwug7mXWJfL{w8jFc(s=;m_7UnZgxsPq;?N~k}F9*n|D&BKBV-+PXGTNvOv$_A5pb? zRO!c*eq8A%l%AvXlS)73w0yF8TBX0F^vg=WqV#J@zoGP-O24gis?OoxQDwZR^ao0R zr1U3Bf2#E7N`L8er1uNiIsDhE72hcRozmYc{e#j!DgCq3zbgH^(tj%bm(u?z{jbs) z?hm#y!!wmGsq_v?@2GUFbNHQ=&8|xCrgT}QcUO83rT0|2lG0U_uBP^8UU#0g~ z`T(U5Qu+|34^{dwrH@ehD5Z~9`dFopQ@Xy=4V7-JbW^39J1r~1@k*bmbPr{JiPA%r zzSL=%LHaEIGG%jlXcL}Qs?Qo%DBD2ktChYs^buUI^eCloQ2IutZ&G@+(l;x8i_*6$ zJx1x%IH~ z%IAYhKjgIde^{meptL@Z|4F6)tn{x+|E~0(O8=#F{PXyKl=ZIeaTXa3yD42(>D`r% zbsoQmve{E0^~XPU-qeH&nW@ z(oL0auJrLrw^F)|(kCc=lG3LreVWqkls;4Gvy|?j^tnoRQu;ilyDELY(mj;EK52ZzVxZC&D}9O5LzTW%>C2S9T1&m~Ug;a04r`plsk}W| zlRbOw$(pROB4gT~tg$C+A}65sWKCvZPuBRmNMKLaMCOG(SrdtaJz3-aGLXP-UwwkN zCu=eTd$Pujr}$6S*r|N>Ue!+J!+pD*%G;@Y+P?3a zZr^vkTlG$?=WO!&eb;-G&wG`=Uupe)*9TPkgGxW7^utOQ=I^^c;@Tm9xlG0PT_06( zdd%tY@1>!V`}^a{_6eo!dHKk$G2Nb*x9_}0`X#--^EyY(9Q}+<+I;6#X8V(>p4)Ub zFMggGzcWKo-nEJ_XqOYvitM@2`pMsY|Nw0Pf&)LA}35`sF({R&() z|3T@zzQN`vl{c@u`JYvt6L^LuH_zWB`kakKIn%v9Q*>e6%a>I3&zHUYR%a-MXeS@m z-Bk8{F#5Y^78i?)jR<>7zP%;iRzklo+QIEH{yQGBgW6H;Ms|*$>%V>4)p$|22yIJ* zH$LSvUNtptdnkQDPGdOcdr*3Z)`9AXE_%6df;kZ!! zpUU@C2S9T1&m~Ug;Z@Uf^bo+*9m* z?tD?=rku)!W`j9vK_y@ILa~yvy)b)pxfkeY?|f-hYytcNyNH zeBPz>-OB$xD*bb%_4`l0ROw$U{f*M!DgC|DKPdf^)BnFqi+UgV&&oQ}{fv*SdL@9O8rsQ2>rF2nTM%jf1>lZou*bMr34-0bCRsxesf_wswHCo}Y3zLH9>qI5N<<+QV3 zI75S!?d4_feVD4l5lSDW^wCNmtMqY7*H^ls(v6jFs&sRuk5{^t(ruJJLFto}K1J!% zly0Z=nM$9fbO)u+Rl1YX=PBJ)>GPHDq4Whx_g4Bsr7v=NtIrYrmBm1%FIM^zrH3kg zsnR3WJiA<_U!ioM^wmmVtMv6s-{5puV;QIVJt$YIQtj>J*`JS7@pkg!xT7DR<6mV` zc`9#jCy(rKc2n;xDXX--ojeks#wsR-ZAWi!Cy(@Dx_xspH#>TJJGpz~gMQZ9-cBAF z&9p{Av(mRJotw8Ac2H-RMfp_zHWioK zmA*siyOg%K8K&FY4DVLGV{a#q>|VZAvvF~5FRC4c(bt?aei+2j&X1GE< z)3`ExCO5~w96YZ2{t2b+?d0jXo41qsNWa+I$=#=mT%Y92iu9zK;oI~bSn>0e@>8h3 z1uOM`TGc;az6UGiKBLM_);kUJ@0+lNb3gyAiurR&FHt%-`}yaUeNo=ezo6RrqS7xZ z{j$=wpHH{_{41(=UQ_xFrS0wHk$uFr?&m*OvHa5M6z=B}eVfhKs;=KSEzbcQtDb_X ztMqY7*HgN_()N^1Wc+k;F_F9bc}jOx`h2Ae<5M=P)aS|5)DsE%Z8m4B^s|)ip!B&) zcT#$*y}ZQpJ2h7I6Z5g2v-w_)^BvJ|gsl57ZJ~!{P`B~LD*Sm9>k9o9L-+fPH zFQ2L24pbQT@xrwPg>_~CqGQB zf%-}7;VONE(zcUNx8E7EC#_Szlh?m9R2ZJL*1LK8ts&dZ>+enGW;b8FersrsdNw1k zd-;6%ts(iWV^3N~X0knL9f`yD>UpOhl>W)-@DoU(KAE@Q9Ljk=pU&?>v6K0{p3K{C z4nz9J&7t(!)92<5<@TFH|Nn;aSm*P}`u$M-E)>0|ucY?+ zRg|vgwCt4ZH-{p#tBs1!2}+-&^eIZ8rgS@{&s6#>r8_8XZz#{h8_L7IeR?YSyn24bxMy?`bMQkD}9U7W1LRUR)@8c_K#Kd9v5A2vA8ojbt@0!m4^wjY{OiIM@jo9 z=6{={L_EO<*o%GXt@mnI6AH=sTJpE`j zEnaJU{PjUb`A2S)i~dCEPveh%$@O`B%XA-o(vmNuTOz4ntEhYvZISNnDvb4$sDG!T z{=L#a3tbITF$o*+@LlxU>IPZiaB)s)^l+P_#=R~Gv!y}!~2MCVM;9+mbSl>c>= zk`GZ4J2d}mk-A=y_8q3$cSKQYU+N-PcsxrVAC(^cDz!N}J!+HeUX<1yo7&b%DaWO@ zlw`*yo%~4z>$?bwZm4u)rJE|}M=5=@(#I-&oYM7`Zm4u)r^6bjyON07 zbC}_rvF9+OMzD;KrujdvrDS^!GwZqU_|L!;>`GItpTlgf*8k&`PV_m-tcc~{a)yQ;N& zH>JxKpWc&5oD#hkl+@GIZn0goMc!j>IpWuYOKmCt-O|E+RU%m5MNo7@r5h{VRO#kQAFp&PrQ0~2?$MDp zpP=e}Qgpq=;*{vruw8QfH07aPEZZ5G)^uk=8rFIM^zrH3kgsnVAzeYw(CC>>2H+&PU-KJw&yS-@9nhbFw<=Hk+I!Ft*{rw zS|P=@x3ax3mTj`tX=e>=x)QqyiGa_V^$9nd1a{SRR9;U>% zO!ufrOY9w(X|VT^zR2%qFQ>XuEM*sscVJFaEt;Ngb5tTdBi-ti?kknmFMmFt$@tvS zodsIVQyBw^^h{d`(s@TJy|k-38`n=>&MH2=Cz04adS#H*Jyd-5jJB{Ag|M7>g? zkrqG2`^n4M`9Fsx?sHwqqUYs*Eo^2ce`Xesn97(vD$(^PInk2Z%rBZVNLsfbwXKs< z7N)k8}`ch@PES7D0wl=Jlv}L(!%Zli>h{ek2)U7-e;-@X8 zg{xEyUX9b**Ol#RrQeE`Z>xB%iEp`8o_AGA@5jn7t@%*deysFbr9V^p3#GqOdY#hW zD!pFm4NCv0^hTwBQTjKf|4@39(tj(xS?MiGm)Jd=t=lQRz0#$W-bv|QlrHV`R?#k_ zEXp}8PhFN*dOxM>DEk&lw^X{d(_u-uRnn(zm8TPY4s`NCar#l^bPj@Aw(4Mf&42tU$mNV4oof&KN$~c*& zY-cMyH&(tx#=n$lPgrjA`-u{Xe%|uh6PEV&!n}=`!uo8UtV;HTCEuATti4z~#%g}F zQs#p_VVSk>msr@_Ez{r=ko1K;VY$t_M~R?4VVMS_IX_l%Dg>pM8 zCDQhUWy&L++aAfuPI}3nu*}{o+Pf{&;O;7;(w?wPs4pan_Jn0ZQOs%8w6x^!%+e{Q zGIQ(+%X~OflvvvnmiZ9tMCO?ElRaUX85GwiEa$1eFwc+m7v}8wtZWx5y(m_`aBPYP zd%`mE7BqXpG8exqDPzW-u(Z8yp?cnHt5wgQu*^Cy3+xF?zZ;a5&7QDK(#j_BT&(sa zOO;-h>;1{{_?F@9E_fyFUZL8$GP(s~u_`(>thro&Re5+lmTj2JRPN78B*Lo`jjH&0 zOZC*6SU$z}U1j^e(jO}QaV#I!$GPugi~&7S1X9*O$5iAGxdtXI9aLFpf({fqTRW$}yBzbXAkbk1}d1Ja63 zsi>j&{#!+2b96aku_Zb+r}&6viSmW?{3@q5Sz7Yff`W>vjL+?CeA?dCzFSvNvoM{? zl@($8=oLXyOSx3hJ4IWhQyZ)SxsbZSm@7t8YT zEpy6kX~l13Tc2B>+u5@1&uxEhD`DYW31!byLG7O^DqT5wdm$;Qs`9>9Uc5{GeN_G$ zO7E8!U;jN?rKFn5`+>>x{@-QW)xtTCtlze!-(;p8oR`@pd1|TISvyvKu{~Vb9vRCv z?>#8q>%{UX*N;)9*NtOaPuVtzWt;b!hB>58jZ`^Jlx`MXrdYR77A=)-9c>+!lAcOh zV^1Px2KFRkn*G&J#-=@q=%2$*&o#tqwJrB~i<(8v&dKbYEWOXk`qO^C>7tQtJ!cybU9+tJ~}m=BXa$0<>8!I zwqY()$)95u(|9qJv1-pEruDl8Z5+oN$H|G1%!ZC?~?$H*> z=>_wmN4rG5XQGi7KfP4%^-;QSw12Vgrz{32JxJ-n(K*wp_oNj=Qc*+kJxoPncyu{p zF(NuOr}&8F$oQ5y<+e0EUo0BQkA{rTD{Xw*Nnd)O^ySCwm)UTYn+>9`De5yr+IgL7 z^Qh=Hi^Yx6sbPP}_0h`1EwOCFT&8lrnoESoBpOxmGgkG~xL7{L_D*FxUg-%+PmJXw zr#=?H6;%F;N>|Q{ubljcX;RXC%KN0ec$fV9sQjsYdU3KUX-Zyd8n)R~?q`+7s<^~T zX7W@uzj%I8(x=6rYhtONV4NN+m)Pnj7-z(?&HES>?|FHGab~R2#aBIdUG%J2wt25< zm_vO3=M#)#Gh5ZAh0=xp8OFJ)HSTy`eb)7I1Wl%<`$+S#kEgtihEhLuou zv8&Q|hblFEHGOMnbKT~8VVLVSPHmjpIJMom?apl_)GMLvuwGB!9hTH^b^6xOMwA{= z77dGr?KEtsVLJ_532i0Zwv|x!Ja4%@kLWc@znhA^kd*U&UVKZQ4^`bhR(fq-eC2kw zNSU9d!gp@#V0JdMw{2#p`^b^m^+jH0m*n|M&HQz-@{8@a%65G$+q}n0yl;r*QLg`} zO5YgA_7`RQTP)kW*EGx_b^1e)`tiKCqe;1X0%O0Vr*lCIH(rWaVi5~r8Q7$?)r`U?+PN}G8PUTse%}cwN z+f#J*6kXm|LRqVKacgzup+oJYWseSKZRaMe{+fdW|d+%XQRnwYzscBAewzO@T zX%@Aj7&TdQ4peK_!SO$}g=0bT>$e^r9BY1x?cr)J*NSBumXKQ|-t+R-!`iV*7hn3V zhlj_q&29a1vXgRh^VY*7UHM{PwBCAHN44yjSW%Xi*HyOlV%g>t>2ykywlq*}X%yWS zv1k&Vnoeyf%5{gFE4qlZ*7*?KG60HwqLN7&{jfQ2~)EY%Fbj!qB|4uGbq}Rqz-ne zqK7CwEZRD!c`mtz$F~e~OP&#`q><72w~Kr`|H|l8$u~yj8>{rVXzQ@NM3j_yXDWOr zQZLJEYi?m!b7lUFk2Qbf`h-~5a~kK8XQIm^`o38C<@zLLJ2{T+lvvmQqb^fp<&pBI zsq&}Cv7Mo8XU4Ie73+FVbq&*`RGp5`vF^7?Zn(x!fjazWv8|@eRpS4!)57PLmPS9 zGV&~H7B$p=WF1&(>p(j1 z8>N?4xn2_es?x7V_nug+Ru*qXTNIwLEp1t&+VXC6Tg2l1=+wf~!oposiT;O)Mqm7V ztonJa(w{~97wa#S#aBwNQ~KNJocSAVspooCpAFIV5sM$AQ^Q)yGlm=8bh7wAFZ=8@_RfbJK{1v%f}y|Vp$=+WwPrS`ja|TbafD2InnxvpQ`cwh~-|f zEamz>v952`jvDbTx5~3${5(>Rnz^<-&{;~ZgX8B4>y(ocKeZC|laud)N|QF#R&hGK zD77!AxJsLkRBf(P)Z3g>9MUsQdgqu#dqn)yRlQsm~O4cblX^CT5L~LwkIons?w*& z@=@@sg0$j{w69_N^sQmR_oCIn_J6kjvwLr0zW3T1W^0(OVFj^<$sX|R^xa`e4bMs6 z8rte*tCy`_1+jYB%(IziGtXvTQTyy8d!CMN&m+3C(p^%q7m{+i<;Az;>8|S5Q|VrL z@s-=PT*~Z|3g5Y{gW1`Ar)b`HWOnt<%j}Xo{nX4K5G%jf4pO#*W7#HqmPy$|RN2E~ zl`XczmFkylz{&lcwUv-$bayM?g~ z8IksEA#bTJns>OuI4-Tuw%@ebXy+V7?VKa0bxrQU_H3cugY)?tt2vFv(tp>KU zw4J5hdkgyBD|eHb>fSf2sIS}7=Gm&vbBlVL3(x&VdS_muJtBVQt6p9Z%cs~bRJMzh zUaa)eSUw6q!qSRmX085s??tPD?F{p>Gn84sBGEY|epbf!BbKY;TPAxfOUbXs zFIg;Kk8hcxI3)!j^_g+WD?(^ZP};&0*`)T}khJm}rlP zpN~~9uZ`tXY(G=BUnu>R((7XRNcXr}{cQJTSHrIY_+k~CO4~%%@ms{HdAb-*yn?ES_x%`wIO|XSW?3u)3=7{ z)Sp%tyUW^L*6y-)m$jA9R>H!%63U)uqucX{{zd8EQn443a{kDRZ^^Ss)$MPkH|NDy zZs)6%xg{08b6W?qv$dtLt}XvPc4c;z*fS6BP?J2{xjdq`kCk7pmr}Mn#j^eHn&$ng zl)Z~8yL7Cw#kP#HEf>o+?==Z?NIB(IITe(y7+t1VS5_8PmEJ4bIxHnUm9(a|x?>z( z)K_(B^O35}b&7hM({uFYR4eJ7V-oEV@l#jza=lnS#kPU6ZKQM)rJKd_kyBeN&Gslo zbB|&p+eWsH?4o+cDfdHrU!lFP(B4XcS$EELnP-gKy>HCRPYFHzEYiRo% z+vnImr>O38Y)7(szd?HLRJwHMF~g-6iZUVRwn5dzZ-V3MXsz zfo`o9eQ;4al_K5g7QuT73SU$z}7-d^m>3T{xh~*<~ zBG)MGYuF@xYgq8TXf?3CXFw(8|`V)+!? zj>@*P(p{A97RyJv$JOd*yN|r=K5V?$c(L(fC#iOlYAd0wgoR-xlwEB1^xdIK4SS|< z4Q;O5TrUiB-NvbnQyZtYJGb4rt%Q0dlpR*D^xa`e4f~{T4Q)i}5oOV^XxL7}b{e+R zu$9nO!fjg#WzW;s?RiA^Q+hxu_Ciw5pjf`Qi+oplaP)P_b&aasbxMzlwocBBkTP#f zh419l(7f2p-?o{bA0tQR&*)h5N3P!z>v~Rglsscx9?@fC<(KQ@lN`^ zJ55TTph}+@%e&a#r)($1v7H?2dai0UMU^yF>1okkrC!sO#SEoqMqB@P$#&J&s`Oo} zY;>mU=#({RR{E|rQp4HlTSFV&={mZtXRK%Ju4t#2c8X~$p{<0mRzlff%}w7Omeg=w z`qt3qm(8zO^UKDDjg8_nHe{`y@78M33yS)>E$v*W+PtW!x4H1FYSKH46YUZ4vsCr+ zvRFRFcDb@$q4Y|nSH<#C@DY|)yc(;9^4H|o-F4AxW7(#zHB!qT^S|WOwaGl&o+1DD z3^J28x|t;Umqcfk`1viqAF=!+mZet3!NvP*` ziTX*T4wg5uKD79yYy4!EZlCDv5g?~{_IK}sUkPP@S6=PoD#Y5yiETw?TUqID1652{=E1|7~>9`WgUUQ%H-A76dYou=tZGE@(-PZSHuJ1DE_lrO0#j<96%Vf_| zDfz(oC5z?3@hy{6M=7sX{PM)Ic6`g^)XcotN@*+Q|F4uX3lDd*Q1p?pW~5xNqil~+ zx~|goV)?LHXtU5};s4Jm8MCXQjI+-7S_6n@cvA(rqr; zn6xozW71CP?3B({LR$&bV|0<%#8>_?F43nR&65vM8;TGJggqI)B8^5a&nquvk9j z`fz1CLg|r8Um44X%|n}qMQI+|cuxQEEbG=)iLOcF=bHF_#PYiMmdPGJQu3(yC5z>a z@hwwS$Io=d3{TwvrGJpaehRPjrJ+2%SXXS&T3$*h^-=a3S*}*wi4P(Xe*(u zgxM>h?C;j8ecZRP_HkmnUfFI?`bVWV#`0n7kF7tp{@D7Hz5dvGVC#Xc2euyAdSEM| zUI}Hd`AholBc+DFrEd*wMClP_(XePFy3>$3|3~~eFP59)TPAy4O38o6FIg-%$G1#Q z9i_Z2@yip-5|xVeyJ?dXb@O8D-nOlKG7GnJvrzQ*v1X)PFQsgEQhFDqOULqIBh^Og zwvAL9IW}@^(CGKucG#7{Z3lPe#~r`T3dwiT7GtaQ~_K5Qi0 zNRA%KHX>|9q;^Eey0urLYm)fcC%zxCtP$Tb*`r@d-Y0@H~$a_mIht0lpn|(GWZA{vj zv@=UPv$U1aR>D-QgtFJHo4)%sI?j*Cg?Cc6>i#c}{%GWRD*yxnum2#j93t&e10cT043iJ$JykLaGUe9HA+%C?WveUF?@rG|sjw}!Uj+KOu{ZZcO~ne&6=&v~&N65le} zvs6kR7QbY%93I~?IdzosM#L{qEJwz-Ois;JJX{D6;b7i9QNBmsn{D{6LmQT5U zow6OJ^o>f7j^)GVq0PghG!Jb&r~i1Cb?cTy*Cg>XCcYoB92?&<+2cn_9v8o4vAi?B zWmreaGd?eQ!rY+}KNAx56M8h2{`1iKD1Z7$X4k|-XP5Z7&-oEODV9&UK3UmLQF^M< z(_;Cs@sU5{!{Tglwmo<AA6d6vh}?o$W4QcLBQ#6y3Xkt#G!&*$QVXoUL%S652{=E1|7~Td#!j>33fIPqtz? zKfYzMR~spLLHv@%a$$VS_ivRyBzRbduUl_CDhAUm^H6Ww)*pV!q+ zZgni5V*8e|U8D57O1~e=hmCF<-SJ1ajS?Fr$r~lIZhe^Onk0Tcj_*e-*T%O@_DGkK zKZ{?oSbh=TGDUU#D*sDPc1z5kty9Tcr;;<8WL~dJbasiKZ=D~}>tp$p>l>8qk4kS; z`j=QflGA$gVly(`W~7Zt8vtc3FE_qX_;Y{l}A z_?F2YA5!wB_$7t7|(Mu#AG7q?m-yMs`4PQOET3|{hO*sH>6%I( z7|VyvC7Vm>HkWKn+L*L4X@BFezj4?~Xe*(ugtijeN@y#gt%T7lp?vy1IQ}PFv8)x} zGTEa{O0FHhWU)LvzGZUiDCHd)zdW(56W=m9H8U?Z)1zm4;T{n(e~w9X{)nHt&X4GN zv3$z)2FkXP(oK|Z7RyKBj=I&}R*|B#iWHCWEbCT_MAszo(=xsvv1}dRGTA*KCAW=V zvRIxN-!iPDL>JA@JiZrx@(i@Gm29Ca*D9Dv%PBb*+sq0ImID8 z)1-IKNwi1APe;|uon!eF+b+tso6_Bt?itHRdPdV~WqUu{``M|votoQ9Xe*(ugvE0u zl>J>VwU6r)Yab`JeU)uLr3WZID3*_cUu&clgVVl-L(;c~1>cKS1G{J0J*#-$vuy6$ z+_$-JbAQ`Exyv4KSo-d;q=v)Ow}!R~+bV3Uu&u(|z6#q4Vk?NPAhv=O%nBkqtP$zE z!;%_~Oy3&X3T`WSVO_yxc3qj5*(G_da(P5w6Dz-5zfReXie;PZc_d}usLCE4t8B5o zMcIytWt&JnrJS*(tp>I>7xlH-#(4UVak-n!R`pwSJN$$x4!}wN{cONs?qG zS!*RpvhthxobPeJbIg72z0bY(Jonz`tJl2G=X}q1X1+6LX3pI6JohQn+nhdgk?zi- zc<%_6vzXoGCE>~>-=)lV8Pm&|UJF?nE!WCB1rwGW-8qyn)R#W zol{iKn#kpl=i11giS8$=d0ph1$#Z>V&m_gTA^4gT-I7pw)SDZ1n@DfUr1phc8dB8G z&8*E^GQG{A)~C9nyR$XkJ3{4bV|RIbxH8Fi2lL&@^e(1%hbtr1`&HtT-G{uFlAl=0 zPb_66l$B6cLRkqjZ6%~#?4H!!p;Cll*E_ z_NDF)iz3{gx)I7+DQl&ym6^X*$~>2OF7sUGd8U2VqaD_P)ZJlGga=bMLU}gGvmsrd z4K%wB#WK4n&taX1^pSA+>H1OTTlg%MFNirqbr;q3kuDalZn~bud`pD$jVE@hrzESV z6w{^6I?1~X^C-)7Inz6yxFl~dV^aD#bNZQPXTkd`H04uw-JyF@A$22^6(Dm~0J)cP zFVl7BFJo86u8duIqZ#WPP1<2qOx+z8MOZ0yBb2pQ)?QhAW$lf1?ajP(gVyS7y;hU1 zn(6B{wX+&)bM;JbbNY;2x;r)Fy(3gkEq0e{hbxnObC_=(rt30YFI*Y<-^0|3`Y9h_ zgVc>M|L>wiAbZnT_NFxJ8^$}QsGLTT%OTIkkv$VVmZ|0@k!vQ;rjb396l1gCYff}a zLgi6!HrH(;-6E6P7iwupQ9E0*Hn+<3HiufD>Wc18>v-=7mD7gZ<+kC{Gx znC=*^j8yMeiBEPPvFtu%yvTTw@gi?h@;L0l$9_Y zRzligbqlw{Dq396Wv55D>p_fjig7@G#t=k1r4Cs$lCfsc{23T-{?PS7;jY`pCFL2c z^N=1AE{gr2{y#JK< zpRy8W;z~$6tf{HH!=ebMrEY{WGcs{z$X%7YDm%Z}c7C*0PuFWT=^2^6Zc{sFvNq4k z^fsr@+DLb2cD#3l%9+FN^4xG`lJ7j`JD=$VOfL*qM*jCOwPI1Y2MGSxsisQj zsZ>j)^Hr*?(giBzsC1!9byT`YrMfCztWrIdE>WqzN|&nCK&8u6YN*oXDm7B+3Y8kG zbfrp7RJux~rYc>nQZtpVQK`8~*Q(S)rR!8`snYc-wNmK@m0GKGqe^X5(tU7~N^MoT zS*3O=-J+7Vx2L1lx2n`ZrQ4XTBh%XFc9lAj?GAP9tkRuy-bEenQmLy-cayCf9d+LB zD)mt59%k#wwD!4IrC!W-AJh7JZsSnv7prgLlSEUD4>c?ykF|B?2tMo9l4PaVd ze?+B$Dm|*wAeH{0lC}?4=`odtsPwo>LsfEA8m5xI{)9@yReDmT5h^{U(nyt_R!LtU zrP4Dhjm|1G-5uQS_Zjx-K}VmE_A`Be>4QukV)`)CN0>g!GzK)4UsMln(#4q0(mK_j z$`p4A7I#UeOQk~_QoWBQzSN%wa*yO5=?998gLLWxdU};+PpmRbmu0#f)8(12ptaof z#PZ{yT#O< zKWVgE%w{{z zgV`7y!t_uXkFxX2`_3=F)-M{>8Ss9RS~85y$>B_oV0t9eqqNSi-jB9kYTIZQ_n27X zru<`L$rEjCAwQ}`-c`!GN_htv@88CcP$~R)YJqBD=-Z9c^@P z^8Ax+%0D61c9^op%Nn1$vra~*j7}My!R3o;>xUdFshbNv)YePkZ?;ObR~h=-y0XKVP1lqPs=;E{uE^#`m`yY4pl> zVPp@PQoj$JK06SaK~vcJKb7fesrD>LpPrRS^KTcLIXg~jNhW_6CeM3M>YHG`3nRNv z*?r3HQ+8Py^o`N{-=WCvQ+^XV|3_h>Baq!^I(%xRyCi=#QoWUS3bW7rMVT(fbXFSO zRrw~i?9^nZ=KH*o=;xf2mw#`#r0+Aa?=xrTn0e!q?oFP*TN6Z&P>k}fQr=bip8Yg3 zNSijp_{e-ArmpCjX>d-c`!G$_!e2VqdK! zM<%}Ykh>~(RleDjZr^OmoSkFltv_^ce7wm%kdBg5U3#C!;(WQ+MT&(J7--MrSJT+hm3oyctUSIr*!RMI8Aq zjO=OUHwNV$vb;l=#phzc_>aHJO>o-TTEpCu#i1ccx zlR=(78PE)p?@r73$);E{{BxSglJtOn=gR*kT z$|Wn8tX#5k*;Yc@11>Xndt_a1T5b8oCabHguClty>MARttc0=>%1W4iD6J{cO2#gb>RHX|S;O>Nrq?mOp6LxtZ)AEC)0>&z!t_?Aw=un)=^ae(WO|p@xv%!r zy4_KG?qTKcjXKvpmTN!L2h0*EnuE;a5Yva5KEm`-rVF1Prp;7#QGK0sF{ZPaF2Qt3 zrb{thn&~o3mu0#f)8(12z;s2XD`_3NUle6F^Qg*nHKwaGU6birOxI>Qhv_;@*JZk% z)}d%@iXyDfay4MOVdN5Qr3P!GHZ)>!H%^DRgYBiA_47VR|Uj!q)(+!<#{d7Yk6MFN+>I#tc3Zo64D-Uj=9?- z>s-?+vs7lO%+marr84tm=E=;HnJ1qVWF<`eN=UoCd3v`;dOp(&lCcYcdR>?Z(CC z*rgUOv09h1F~5xI5WWp(mE7D?22OE z%*x!t^j4;~F}Em->BCGPVfrZ3 zg)7Awb13>uQFIsNw;O$bxjA%ysfUUtW9(4b#dO)EvzRWybV;U5FLr_^7F7@DN!M$#Qfo0?o9P^;>u4RSk4mY_JnAuB-|F3f zc{F6Y5z~#CZo+g^twZ&P6h+dE`8H>|1=B5=ZpCzKrrR*xmg#m(w`aNo(;b=a#B^t- zyD;6A>26H-V7e#My_oLJbRVYsGTo2q{#u86Eq6tII)LRL$n>CC%F4Z_+huNnydp~BM!R!OHJ=ANlE9&Q& ztjt+V&t`fEi(wA4^Y81-Wp@63oq5bYD&Cl5Z>8jjZQn9(9S0hW4b)k6_~EbbS0*G1E<$ZmM;t{*azj_LMH zcVN0B)18>^%ybu~yE5I4=^jk?WV#pAy_xRAbYG_XG2LJ5P_N~#s88p!`~#U@5KCFP z*Oa`g)P}(Pu4|N>tfdKB}^}6dYPFs)W=lv za^|~&>6J|L_p+;)oxhh|&FuWW>>6fI)O*>rtju*xuV^5fS?`5|$JAW^`gV_sf9lFz^q&MVumJ0gsEYW(uGj-Pnig1@1 zAz62uR$0?zO_MdPps#7N3dkxTtAMNmsq@>|v|HJeUb_{FdT(k(P0{Sr(U9KH^Z}+1 zGJS~Y!%QDx`Y6+dD+m55nOaj+*G#$?(^*WH2tK;xJx!^tC0YAQF2m4c!gxjp^-g)#BNdpgX!Z_ySF&2Ot=6ihH36|!(jcvp zPpq-$rFbWrF_3kVX^p*f$r0b!lm3(bV{aKJr|x{D6=RASAz7!IRvFbYs^wjaylatn zEwU2IN+>H~s;q>xTbY(#yA_IhdTK;X(ag}%ke88f;|AtBqQ>nDzV;rkAFFtEq*{SgV#Zy(0Zv7|-aS-dV|dWEIn^&E6sJ zHCF3dt96}eO+c*cb%_+o2BtTfHIc_At97&0y2Z36Al9wAM2ch^)7#CO$YY1qy3=ai zWm@BjRq_V?q>&z%9#8J40$Ndao2vv__n6lF8jTdqUNagma{Y~#{EAHKmA+5z{FD(U zBTPnEs=ODH*(kFyZ?ntJ-r_-K=fAgj zh}rq?Egoie{(Fl@nEj~M!QK;UW#Q~luNPwx6=n7k!AF<8zMys&W9`dgx`furt38O4 zsfA_O-7L#=$@FhwJiSQ0Q;Oa5(oB~zdxyNsTCL@**7Bw`0kKxlB~m06nXbfiEp~^q znLUTut1^3CX0OKV^|d_#F;{10)?~Vt)}ivLRkf|w9ILgCX$_SXgrazxnY~2T=B71> zc%%+Knxr=(^#+a9x_SS@X9X~lGFrrR*xR%=_mR9-vtI$7JBR$G3t+51)cMfxRgpQ&Z!$jFhABkxAj z@3)6(*U%x}T?3WVFDZKrUz*qs)b4%%shrLJ(THTOb=&z1k)p#9>w%% ztwXii6h$(ITMIHt!(E-h38l{>-AL)M9=HIyqcifWl;)yL2aJL+B~1>1!nun zd!g03$ZB0|TI1;ts(pzrk@Qlgmzgz@$8xK6h1I&!v?d_dRk}oqWHr-k%$mq!t<}2D zYF%$yqm7kn+7LN6d2Td4$-2pE-E3N;jY<3>J^iGIq=#bpbV##wi=L09x0-X4tlLa$ zevLDVW_xNxlV80c^~x-dWtPi$k?|tqMcx^v-#fz~Rxa98>`2C*g38_*u57x#E8O+m z+fTW7=PkFbY$|b&E|K(JruQYTCR^>f+bEv>ES>{qJmhiEYCUAN9=2MKXe*U=)by~$ zNS=kOgmM*Sx){@0THDI7*{IwSW*)MZG_AJ$iLp_ArOf)sTH3TGw8k>JY^tX$)8&#; zXF?+{&!VjmOSIJ5ie?_NR$`@Qn;waYK9x$LHdkeBuEunAv;E{<(`v0{wbnMR@wA<4 z&(S54uETU)vnKMWXSLS1S{sMNQLt!3or^>ZKfU>n_oq}wvxj_LMHcVN0B)18>^ z%ybv6gPlFpnyzNeWbI~JgN-bCwNdMOu%7S9bg%SpHMOueYgHen`v%`ail`rpqCe9E zm>w8>bjcfQ@svz`Hi-4jV5Wzd{Y2hFt=3^y>u}SWfLKT95-F0AOph{aB9GBl>lmwb ztZ9uW*4Xn>yyMIm$U5G%#$LMQ2>PifJ)YS;PBU{tYRpWEW}+DlStnVoldaY%R_j!4 zrP8LE9zl$As(HFuGg)Vt)*#{uq7G`^OxE+Wn4X={t)3Hn>!`oyvOb>2^n9il1Rq@x zBQEwjsLvL%zFEZdVzZyfdx_P$)M{O3T4Rqel!Iztu1h4ng6WlJP2{o4YF%x$t}(5l znuAaj?^-hkvaU0&LBu0JBF}<1TElh7^dK=T* znckswuw#f?v(v1Zth-EWu#qLNHfr5&*7JLq-kbidrWWpFt=iA@f#6$65glYv9Af$~ z(?^1jE_q`uo|380j|+U z3_iM48kwP3sLvX)zG=*K6SJSlyQ$UM%xZ0JT0=F*uBi4Fx{fJ);3ma zThkhQgpxycOL^NZrT568xzG6WN>dCm5aWCUOuRkl3*(0+jmf1r)w|;rs-%#%U;d0aU z0cuBR$U_LZA@=BYa)*w zR_jiyb(d+4HbSatx0$$CbyH%Q%9Q{)Xw7(pnt)xe2P2LksZ?aCbS|^#-XyX#U)Za4r<*j*7LJ7v!$uo|M?Xa-S;`{zRzWP zo;e1{d%o4Wz-nD+TH|Ra)xJoVNP02TOU#Pd8&1lHF$!gtf zwQjLmw`wbuw$1bi;=WVO+s&HEy2G>v5l;|xQ0sQGp5K+3Ee)bK)29x)@4MN3-^27? za}1F8KC5-V)q23R#?v!Y`$1hI=|fB(Hfth}BUbBCtF>@7RdPHLhVoMFMRkd!i!q&L z)7YAZr=Z8bmx&N2129^rZA;@H=-}Im((V2U*Kmt>vxO z3ffBfDw-ZajBKj8l36oZvrTId@dQx^wXQ1b`D&Tj(ja;>ed?h5UY*_dnoQR+#{hZP zwpw$n);gv&o}QuF>*^9o*JHZASrd6Quv!~ht&L1;0%C2fOQcAeFx}Lwi9DKFt$aV zSumAt_`!=<04 zpY;x%X8UlN!S3H-p#B(P_6J!c zw*2X6qt;E(ts^}#Gh3RDcPDu<)4iU=?)zk>rvGc?ZA{`PJF0^H&XZ= z^`^AdTE=QEtF4r;oaqt7ETfvsn>CZQf@uvRo*?R=)>ULZUnw(N8bohO9f^7t(74QI zJR zleLv;4I-W(>Y&!OWY&yQW<5V7Gg}%&Z%Q4BTCr(d z4rSwV7}LYeF-qPetk#iM>nPJ2&z+;%N9z(vk70VOSrd7Tvs%YntrJXZJh4jNM2%4C zN$JT{+nv$cGBGvQ3yNlv84Xz{Tdh;9)~QzOG;O8Qrkfr?%uT9!hFLRNXPVX^;t8S- zYTYc>^RqLvr9t$j)RCws2#w1*Y+TM|dY(B($$P%ly1;5(XjoTi#xoM3jR>_;F5h^_?JsEkoNV9!~%wXdi)GN*Ypk7*KwXU{W*Jvx{TWfmQ zW+r*Ai|lF3ZL?8{>&+6$y1}&C@~5MXTDMWRj`XI?Y-u{)oq`)Pjm6DuTy9}{t2su= zdz;m|-D=%oTI1_7Pn+>7&W0C-(b8(G;$(A`9gvYf-DUnAMtPwU*FU zDy^jH5vnbu$g@;r&rqJ+6_r@pERn2bOl$5XrO#DrU0K~a(&aL z6_~DQj!_!9m8{lmtF@|Wji=A4_G-FB($$%+Y1Tv@wXD|KR%?!FjW$-QsZQkF5YQ8lctrWfw_i|wV~D8$ZBn@t(32c=@G=-qMDnUHIucO zX$>MCsYBM20=%9yXRARArdygbk>+PBtF^V&+QziTGta2@wz@>p?U-(F)&D$Fv3!kJKS6X+c~`X~y+st3f}e`Foc`c`nqJ*^z0&6R_!W31M( zR_i!zrF`Q}k05%NYMx-$OxB5}HHdhm4p~VH;z~+0ZW3D!CNn+7oQdQ;)oPt)wN5v! z@ys)-eTFWP^h~B_nKhBeY^!yS)jHR-#uKaLmGz_`t|v0?Q(@fG+BeT!&&WF8YF%Kp zF4R`ax5)Ge;!ab|i_MzJy2P{w5s%c73Zq-@LeO`CX53P?8Z2Xaxj7Tbdxh1y(rR60 zTI0FHRQqaOBIz|uuQh8Tk9Ah-daHGVX^kgV$s6=YmL4z2Jx;TIqs(CA8_}E0{-9pk zY_)E&TDNK|<=bX@*k&AgZjbC~%Wbn!i95^^$-2|D+VYF7Ag>E@_Y-yZX~yl+Gmi9b zruUdLkv#TVt^2Ij{iZdZJ4dx2&?S;S$n+tzCh|CJwH~orkDAtKW2Kr3*HCfgo`*b( znx14WX0>LS*4)dNtC8-2^iVR7FHt=4*`HQHFIruva{lV=0dldKJ`)<&i^+L**I znX^WEH<`Ul^P#bfeD_UZ?4yl(u!-(L(oLCe#&mP0TQJ>{=~hg)X1a~mu}2qA4r)zX zvu3ikGp+H|lS+B1b?sTtcVN0>`nQ@|*on2OGt*syZy`n0l||8w=^jk?3_iM48l9n7 zsLy(_zUj?$AG4pxyRX&S&uZ;&T0=F*uBi3_x_~!)*)8wP}3TFgz@B{ zc!!xWkaf6eji(;T8}#!}dR%%u_}^`%m1Bgta*%bT)jG;*9j&dDZ;a^?#K@+a$C@>h zb)0DpBAy`Xpw^9NJwJizi5cDMNx`>{`g=0#<0(u}WqMlh(FHN$Vy}bxY&z?k8BEVK z`-!|~S*^3J);Xp%_6S2csP?(KMAGw^o^RGf9t*72g;wh#(;BKd2u1NOHe(>`64M$) zJW_}3ck*q&vsA`=oNpkP=^mujV>#0+m|n^BDyCO6y@u(vOs~^A*foM$v)-(ktQ$;g zu#qLNHfr5Q*7KW~-kkoerWS5tt=h`;w%}Vx5p8Et>|lB))4PI?E_q`uo|380cC)_O z!}MOWpU8Wk)wBDAC4mef|tSIYDVVm46CrOlejTE?^n5l;|xQ0vOFo-fCA z`HXILh2UF9{aumuaV4g+nXVdqbU}=`*z2G^tH%1KI@2}Hej@K$R%>mmHOI8Z9$_d4 z)m}%JNV+c5^~{>cqrTPJz-n!1T0=F93TD3`{hXftOmnS~opdy55=Xq`ENOmFaFw_s}}nxkQonWKr~Dx;N8(nC`2!EmA74 zAM@?c^Z=#@GChdt!AuWfdMMMww6@hBvQZ?%S*{UGk7RmOMS`$-as1&MYysm}x1g0k@xAssRu`7yp5{q_nxM<0D3iF-H^fWUcc~55^ zGfa=zqqXIrdS0~_(gj1Ne`ud57Eq6 zo3}YYx!2__ckbhZ%3hz0vU9IF_Nx@@1~XQ&ZnRoAS*@G3mGW&dJ#0~t=T??$8`ImF z-VwR9Pz_Y>PBRZ#cbV2uu0$)UZ?{<=S@)RM#MDh?@6~0K-pBO*WYn3^$Pch+55^KL zwf2yihpdNLsYgtYghqdq)l>Mq&^;*1bTO?HQ)_ycLiZ+%^-T$;OPc*e-leS8(pGC3 z(;822QSD`QiKNRhUEZvTJSteN6|L4vrZw7Fsiy46xyiGt=}FdVR%>HH}Rcc9$& zK@nLK6S-TFJ)n%IM2@G>Q;J4bZT;zjbPm&Xn6AroJ*Mk3-GJ$aT8C=NT~XbQSpLRL zH(|PIEam22Yv?M~-;CAMoaq+Hs54Z1rYP#gmaOMmG2PniMe=TAS~I0D;%Nu z?U-)QbO-6Z;>cUWxOOl!n&hov4DZWrYa{ieyfuuo zA8marwp4u<$(>2mok{ooBE>In4Kwzg65U~WYnZWjSXT2yt>)5`(vz9_UQ0%HGDmj0 z?*e6XBy)7+fA7j3P*(L!{jG@npIs6`X0M)df93v0etyUvFmfNsOv=BRBzr&^pRxx` z#lHq1t787GiqiMe_lbKh$R03peJL}O&rBLw^4o**+k*-CIW~3@yl-yCg7Qz=vhzqMs|#{V@$y4q|qch#yEF6)Q_@bjI$pT zy;@3n1!d2b-glbT5BV!K@)t1T`u=G0W&w>*`Mya4c3sK4OH#5t@8oAS^7|0-`w;24 z5~lkuFdh56V8l!#OWqpFTf+qGUuiVSTf;ctc2PgdTf;c}v0$v>(n|SkXMVOz_x&Qp zFF$8az%w~DR|mSo^42h8?{I34JBdo3mFBZjMud!r%p4Kvz6+F@nb|W__JEnW?#R5& z?0GBqSMIN@T%1aQ~m<&dI1V z(QU~8@~9W(8zga#Q0hnd21%U#nEx|EB1rsNEqxlPPig&-zdIv;cP8OGC7FGZW}ozs z^pJeg^ncQnSs}ARW`)d(bbb$OTf=Ct-6g%=5K+`!&8W%ROy^`rwOs{5o4byA2jy4YQlfIH2ajNWyX;oM!GdNZ5h^&vYKFazivoX`&7|6ON z>zb@y`iS@^3rnfM? zH9sS!IFt3xaT{yrcBa$!o#PJHik(dFVtO~z$$ICwht;u{>3vM^XZirs2bn&^^kJ0(T0F9LRtZkM<)*RDn>lN~>V|tRcuC|h{$8>$B8!+8aYg;Y(Z=+T;V$n8c zx(U-wlhF#QzZt8iIn&{Op521^v}8J{pJ%sXb+%?Y+|RSyFrT(e%g?jrTLUS&GUWf- zBoUSC)SG2Om|_r ztJaBLSLoh%WA*f4I^3Jfp3J8g(?Pwt?9J-z!*sYemwlN}Kc?l)rR**fKBp2rN2R>P zuY1y``PZlP%;~S!;rzM}6vKdcW1w;dvS-R5vrO_BY+CcH-KkkG_0bU4i$kTqlKu0Z z)Eo;ERsOAt()ZH$@^f}sck}+cps}wY^z6rOko2(NpZ!#GqV|Ks*-mDJ*&3=z_Jg_n zmId|ENY;y^%wCLroJkIOw#l`Y~6n#n66?QABqr}mV{Pi@LIHL_=Z^&LexjkRk!(=))F*RTKg?x%UgSQZ66Uj93nJ$VqHR)#>~dt6BfA{g<;Y4{@K!>4 zE-z%yl)TOYfX<(Pmu3A=DR+eZzz|jg127DJ(qhfyLH*E%WgeWRziCAZ%F^= zJ+)*b+r?~3|5gP%&ZrMJvp(D+eJJa_toOmrL#a*n*|N`;bvJ+3UD^d~P1h$s#lMa1 zVz#GiTk`8kKz+D__2EwGLs^mXXGO}dSs?YwK1}vuvg*mImyRnT?O}GYJ-B&`|!|Y>wnEkSciEVA8K0Lts@SyZz zY<(yzNxH8jatGxO%C1;ey>!_X(^LCUW zo1r{Kbso~iV#%L*y(le`oq_BOWM_~rI|Es-3f_7}PwK3K^Q5L0mk8Hlx?Ym)V@ied zEx0p=dZ~1{o}ueySTB|h=UZ@lQCeQ`R$RH~a?j;cfqW{++)oAc>@S!8&wFY~dA5tG zkp8WbCy+dWMJ4b0jsh-U^UqT%FLCSo9Z)H;*&j=?6G8}mX%so!uVD~+5=W+ zd%&8q2b7gXRu)-V;#*my|D^w9k19_Rd6K01N=SRaT5JzkTlRo5b7khH`plL1WRE3# zELo{#rIwX2zLk*nfH`arSV#7Nva-m^A}dRLD~t4>^q=feN8j3lRcK~v1Fx|m0DK9_*O#N z12$!Qz-F=sl$AwR7Fk*1TUn(4r2k}(Do+x5lBD`dNPEEMY!BE%_JA^TW#*>(%$4|L zk0pC7S*c~EmX$ERm5}y;E!iHhmFxj!Ws#LdR+jiy7U@6fKiQ+olO%JWB(!&GE&C-I z<(WImhFb|~FW5%*g0fP|N+~O)td!waN*Nn6He_tbQ!+E2 zlC#A~yOV%}6*XSwV zso*^2sl}ZOPKy)$w4)yEB0VT8sH~ugo?TL&>`i5FDl4n3tg;fyN+>I#tc0=>%1S6J zp{#_m66SFw%qsM1Cp~;rcKlaV@dTB$t(ZzDs+2|N+E!ep5-OdfQc0CgR;iRqr>KNs zsE(yoI#s1I%yyd6W!d@ZN|$5jI`0|2^YXs)Gkxb3eCKER&MW%P&-R^H@|{=qooD;b ztN6~V`p(bsomcanpX)oX?mMsHJFn?GKhJkw%Xf~KZp>DjY2CjU_|9{D=NJ0U>-f$u z@}1Z9oqP8`ug8mh<<;|@M=JLcpMU+VLNhVA>Vu2L)yv(9dzY z>PHIcZcO*Uqb80SL1p%2W%kNjnN(75R#G3P`{u3G&}^sj`>`_nhbxnO2Qc4(5qt-Q zyB>-lzZA7*aB?H0T86Mb8_M)BriUjZ5~_a$t7jzBqnI9@jQaEI?k2ik>c=sxzs52> zj_L8zkMem{c4CR1fl{9A()06E4m|;6&*<%#W7#uKV9&>i;hvAw!?I_@Cl5#VjA{Of zT=tCe%$8?%em=8h{K@!}@t4Y<#_1V3Dcqh=X0Xg)nZc<%gJp)w43!xwGgRJq%SxD+ zm5_FTlVt}eYly5NvWDbk4Ut}xUXwkjJU`_5AuFM*gt8LKN|=?N=@|Hr@ z)}*YhdTEQ}8z+)i`VUKeLdFoilU<@$JJL&;UdHtD{9F+!wiPU%l}xWTgYE+w0bAIe*vj;_aCe3BZD+na!uf{oD&^W4*)x~4N=#=nU6tu-Ojl>RCeyW;uFZ4~({-4x ztF_F%p!#U_GPd&CfsxP}E|MOX9 zxXkc$o#8TeW$en>l@(onmM$xyeI=AVpsWtEI>_o^Umc`hq+ewJC{GA^LdZ%eE1|4} zvJ%Qlm|-hnR-xDB+gAEV?~*dF53&l)_I=wbHD@oqg=!!_eUvAxJYiFFj!IPW2}nKx z$@(nov#f-PUkPak*id$Wvckv;BP&eeR~YG2=~LOi%F{)jF0vBJN+>I#tc0=>%1S6J zp{#_m5@!5Lm{sVFeEls4OfvZmgUtI4gH*VuS%v1L$Zt8&Umt4}dW-F}3Tb)L$de}H zpEPBi^S?M!1CzQ^p#%5xQuZbHx9-*@6`d#6!ALn_u=}Gy!o7PaSkRs1}Oi!}jtF5H(Gd+$g;r?*f zkMn%M^rZ41G_9drAw`}KnVw{QSX)UyVtRy12r2S>G-}U3MD`4oE=ryYnfY9hcZTWl zw38J`R-nvWfn;RM$d-{UPa*GJmaGRsuLrURl-Vb2cZl$+JhEJ^8;9 z${tYWq0GblpNA5G?1^MgBx|v(#j+9xy%NeEP}Ut;cVyiOdfky8mmZfruRMF?*^~b( zq3i)=9?Cq-|9L18$eu{{M6wpkS}ZGJ&?}+r0cG8hbw}2npw}Jgap`f{^UAYFo;~@$ z63QM>=Aq2P{GW#sf$WK7Pb6!xti`et2E7u>9#GaDS$AaJ33}a;9+w`MJ+C}_Q{P5y+lM_C&H4%UUceVbCj~>;Yxnk#$GbouJnp>2c|C+4IV?N1i?T zzY@wGQ0Ae`!~CCz5`pZAWKSe(v8=_i5(d2z${tYG9a(o|-3fZ#ksg;Gmp!jMd*s=Z z|0|*F0c9S_Jk0-jC=tk>NcKds7Ry>JE1|4}vJ%QlC@Z0?gt8LKN+>I#tb`f65@r>8 zvy-0U>K5a_qKYS|R7|B4RmxJSxJpQRxDes;QKt(zz;Ks8V&6>ZnvhrHfRm zsZw2)&Qs}Pm1?O}Po?u!xI;+%Hr8`x+S*0#2wNvRXm2Od~t4i%v zx?3e(es`60xjj_U<=(53F0YqLy1e^T(&hA4NtbiKO1hjrD(P~ZXLRp5qrg9b6TnH} zi{MM(L~s%K7Wf`G4_pks4ZaV~2bX|<1wQ~6fJ?!5z`ubD!DZmP;NL;Fu75zg<*$Ht z%U=oYmiZyHTjnZgx6F^A-7+idC!JFXtO{m>=YUnfYRrBvv)6>K4xR_r0BbS(`OIDy zItRQMyb!Dh)&Va8F9Pd>uK%Ubu73k)*Z(qT*S|4zL-0!Qa52)qis0&EJp{#Qf0 z{>`9W|7)OK|CZ3r!Rx_m!B$`k@CNWYur=uV-w5scw}E#3Z-RFH+e5bnZv}4#JAm!L z+rV4Ej-cy*JGATH3EK6)1KRcP2Hh3x4&Dv+VD_HO-V6F(us`@h5j|RlKo15V2Ok56 zGP}dgkAxD2>ugX#q1w3`#R{g;Ah~c;Cg2NoY^-*ZvejpzW_He`&Z1q4SFm1 zFYsG%JF|bs>^q@%fIooWgS(jh-^{)TdN=rA@IT;QX8)1d4?-URe+7R54>9|1%>Fy{ z5wIL)#L3_pU@5RXcnWwXSQ@MVo(i4?mH{h*r-5gKWx-0|>0o8ht*Z*OTYgn&xBP0* zZkgvoyJc2~cFU{*?UvaXx*2#S(=DKzgV%xAf-RZ-dS>qoeFu0K*adtEoCr<^{{+4a zP6DTZuFosbuFrJnY2g2Xe*tGO`>V|U7W760=@@+1g-+V1UG=2z%RhB zz>VNOa4+~1_#^lW_%nDAJOG}cK3WuUih?JC#lSPba$tF;D?pzKp2hUp&=tW-Om~OA z8|(pg1Mgw>p3L4G`abY}rXPgv1NH+S03QPTg8f0)=V55qX8`kg9QqM(C^!&wz(>Jh z;2`h`@DJc{a4`5J_!u|>90EQCy5*0AcFTVn+AaSXXt&JK&~BMypxts_fPNkv4~_#T zfiHqDffK>W;Ge*kLDy#rwCghi`c-fi_!{^QxBy(p^djhY!S|T{0D3XF6nr228@L2q z2D(0fhjx9IGoKaE{{UBl{{%l|`eW!-;2Q8F@Dp$~xE6GMK81FD)-j*k)yL-|&TU{P zup@W}vv+3p!O)L^L%_$uQQ&jnGvHWoH26IDEI1Av1HJ%G0ABFC0{|1BX<%uvEO;tdj@i#(_DaxaftA6EU^aL*Se4n& zVfOQ&tAn+`8sPb0P4EI{&tdku(DlHJnQj2x5WI}(%b~9T8!_Dkx-obacqQ1B*{^2y zYoMEf&6#cqeI0l`(>Frj0JZ^JgEujITV|gFy%2m8d>1@Xy)rA}lmN59lfdF&Nw6Gv zCU^!|0W1%m1!jY_z$)PRU=#34@G7R8Ltg`4%XAy&bJKC!EzPyNo^6?rtKC{$?fTpT zpQd1Y@M`c@uo>6^bmO`0IPFI3+Fj3%%*WMkD_rgRbcRn0unTw{co*0b>D`Vm*6_4zk%KaehYpDZU_Gb?f_k%ozUNdKY*_PZ_o$8|AD`N#nkI)wTA>x1Wy37 zn7uf&SB9E_RFEK0IvkE0k2e-N}=<{zNlG6zGuWj+S&mia97 zGvF9-G&l}?0h|HO1z!c<0zU*l0#|{n!7stDz)j$0a38oIY_EO{QpD*1-U{9Zb_KhE zcZ1!*$HBqiQ1CI(0f&IYK-cF9XxC>r^BDpCB=|J=6gUbT2|mN@qnUjS^t0et@HucC z_&oRm(|?2>4^CiuBJ_*kpO}6LdJ?!0d=GpVTnsJ(-v?KMAAui&tHD*^$KX0}Gx!%nm*7@#6ZkFo6}S!D4E_uJ8r%-L z<$MS2ma_xeE$4e^x162OZaF_dyXE`>{Udk~+z0*&{sbNZ_k+KIKZA$C1K|Hax11x; zZaKe0yX72(cFQSrl3tPAa`cbni#TpM<)BXn&j3q-<-t?HGr`he1@KhxEU*k%5j+h% z8!QV}0#64kgKk|_pxyGTLc8TxgLcb27uqeeI<#A64QRK_y3qB&iMpNQ}AH2&j!namB7=%%3wJ#8$1K70+t7>f@gx~fEB=Mpj%gUXt(?t&~EwXLAzzvf_BS1 zAKERmHndyj70`{q7T`7DbzpO_C3r1(E7%_F4t525fOmuUfZf1R;1l38;Bas>_$2r& zI0764J_SApjs(YoPlL~cZkZFHU7r`3&l}LMgLA;y;G4`om)SR-uJ7YJ;FsV+a1;10 z_!YPa+zh@4ehn@Lw}9`1-+)WNt>6dXx8PE68~8WyU*IxuJNS3-J8(I;1N;a0J-7ng z3H}rO0bB|00zU-*4Xy%rgCBwa0at^2z>mTIf@{FN;3wdZ;977W_$l}kxDMP8eg^&w zt_Kf*pM$@E8^D9$7vQg;doK<_yZ7QZX!l+mhIa48|DfG_aRl1E7r#Th_u?qDdoK!= z)A!oF7lonSdr<`1y%$BH-FtBYw0kd#LA&?jL}>S3WI?<4qByjBFG@hW_u?dI_g<8Q zcJIZ>(C)n`1?}F8Q=r{@Q5xF47pFqI_o586doNCdcJD=5X!l;64(;BHa?tL*I0M?f z7v-VddvPYTdoMmeL-$qD@|qi8!Cx8Q1U8~8E!FK`XG9sC6R4qOZF06zo22iJo;!Oy`TzzyIo@C)$Y z;6`va_!amca5K0E{2Kf(xCPt`egpmpRytGP*$ctSU>&d;coBFmSQo4gUJTX%>wz`F zOThEM`d}^aQt*7R0azQn47>nr29{3S>2rOMe_waAfr$QfwE(85L z^l8vXq02%S0#64EgXO>zz%#&NV0rLF@JuiZtN@+_o&}Z!D}pD3XM?4{O5iDAWw0i= z96S&F2bcq{051gp3DyBuf){}wf_1@F;KkraU_Ed(cnSD1*brO;UJiZ&HUigzSAd^_ zjlp%`mEdP!6L39v75F*W9NYk23w{B%05^iyfnS0x!A;=x;8);Ca5nff_y#xzoC7`w zz6p*6=Yr3JZ-L{$dEg7++u(R`KKMuQuizwb0r(R54mcTH2)+!y3r+zSfv;sMj9{`^Q z`+}pu2f=5+hr!X{0PtDx5pWDR5PS}N6dVf<0-pzmfaAc&!56@x;CRph{|F8PCxC0f ze}n75-QZ{7f57$N9`JMUzu*RNFZc!cBls1#58Mp?1bz+f2e*JfgWrG$z^&jf;CApJ z_#OBwxC1-{eh>Zz?gS5m_0HD!>n5-P*cQADycui=wgWE*Zvh*D?ZGR+TfwWq4q#L8 zHt=e&BiIbQ9lQqY1U3in09%5c!Rx_0!B$`w@CNWMur=5foCLlDP5~E!uYm7@Q^7^x zpTYOQY2ae;FW~#&tKbrFCinsP8n_gk1^x|u9b5*^2LBGu1($+km%#H-YWJ?qE-_2Y4@d57-NQ5bO{3 z10Mz-0tbMvfuDf0z_sA(;HTh1a2@zA_!+neTo0bDznS4&4ORl1ftA5)z}jGQ@B;8! zFb8Y_4guc)9|z}vL%}z};ow~GN$@Rj1UL_T3Va(J3C;(f2LB2^3oZc1fbW3MfeXR0 z;Je`S;39Aw_#QX`TnxSlz7I|Wmw?1n&gz1-pQ~ zz`MZvz^-6#(5PKXlh~vI;H0mxT1!K=Lc;U!E=! zL;d>K4fQXV>0dh1zZju^K&^jRsee46Ur*{+TPLfe+fzy<^$k5}^)0<3>f3om)VK4B zsBh;5(%!PF9{u`7zgEy6sr3g>{ZU76{q$x`Kj8HPK`(B4QP2Zf$6ZCGs-*R~zFpN+ zI#;FYD%DV_rb_x+kmljAJ71;RdCZ@PHeR6W&QVE!(M^BJO@F~nf4NP6u}y!e z?GlyhtEB6?RHX)_FH^^cDqXHpBeEqT9x229QlQrljaA=XsZtY_u44V%ROzc#YNpaP z%g)H{e?jNWx!ih z^8CDGdu6*-r4B0Hrcy_hZda+3N_VK_`FY3A%66wpT~xYDrLHR7tx`9Yx~t^*`Hwx+ zwR=?RNj~?|u@@cv{{Hj(qV(&n{PdR|^%ou=V0ro~{h&(yRC}1EsC5qbCO8*#zYgnu>DK)^toub+_bayeA}sveufgIAusC;bPH* z#uugiEqC0nOuJu}UJdV${XXH&oi*XE*zC?H+Ul$YKec&8vN`J_d4#*}e5S8B>%q^% zc_qT`Y(O1f_{(xO!v3Y-9?iM4$@6l)@>E`r&Sss{`P$3xY{B_A$IiFn{9Er_j>oT* z&NlSXzrgL_cm95IcEJAqarT|C{{Zd+{|)X2|DzcxIeXyyUvMw@Be)Oz3EU6<3?2Y~ z0S{_I{R$pBcK(~E_|Z8Gum5oy*Uk}K{~bIE7Sf-3)i>iKw8Sam_fX%UjF5-d>}lr& z)K|>Q>zs)5Ebsi7Uvbz=fG2?^!IQyKnu!0DW2!W+oa&t)E2#|Zr-5a`)4_7!8JeE2 z9HlR8W56kov2rF@0X!?e#*O-^lQ;Iy_LMDVn~nacN@cVl8>|9WjZ~6zj^D$n#x2gd z{LEIjwmH@PUQP|a1%5UCR_8pw1%9=()j1!m4PLUzq{?_A6+PCb3*T;kcB`Z&Mz*m(n-Uv})gArKI{Jujyj&ad&#y}F#{uwTpVP7BzsE6zK3=Uy)7HrPA*?I`JXTiIZ#?$v8R>BZdLC7@S9NZJ_O%KNjav_znUe z<2jt6u&HgmS__APPk_V0r!;wK&M42~JOhu>;IrTu@HucS_&hic9It7VH39Y)!HM7` z?&D1M&YYKV)&0{~uRu=){|rvk^*R?trX{dTw4Nu050|WIe$COvg|m^-;c8_ z_gm0!|Ik)v1^7>JCHNt@3j9bjTyJo@vl{*%gKNM~qRs1-f3dYpd_ zZUDakH-cYkqE(x4{?)Pb%{c!W+yZ{%UGwUV_2_IxIp6xraklv_v6k%jcm9Q%wkNt= ze?8HjJKrIm9r48De2+4A##2T#@j5>wyM}0@5TDTc;q1bl|933+#o3KK|A{3}BKq9f zgL?l9?gf7Y_kllY>Uy00p2FGBxOxEm1w80ocYZyl4jog!!RPR?^Z()e$g%U^aenmJ zd7&avuE&Y!1FsCHu&&j?Z&Nu%^BRG30!k?co*1bVCkuYXBl&qT261#sAf}VRk|6$6 zrmov@|0t*X=Q7 zXW_i!vFm3aQ!90$GtjtBn;P5@s7CxU;{3>UlK?o2|Sm%z#3 z%it976>uu}XH9?paOci62H(&OSH9ow%t4+v!MWgD z;5_hca6b4~O@Dsdxw8QN??m!<7Q*jca1r-*-h*v1x7lin*XF#BdY15doDX1I%5Cx1 zlc@a8-w@j}@bBPq@E_m`@SosH@I!EwrjEh+2YT&tGb+86lQ!|~%k;E?dPsV_Z0T}}_2BH}Q&Utw5)dJ7= zKmDBAuwMY?fER*wz>73_Elyq7F9z#@mw@%bOEnGu2C!cSHUuvR8-Z7VjWu~L(b69> z2I3n7&Xs&tIZZIrt^%8aSA)&KYc#zccbda?E!YCQ4r~ctuX)V36>K+vt-%|?HkzJS zK|4A(p%2>H`oOsv*V=)%fbGFs!4BYUU`OzFuoHNPWAP3ox5P` z3f>KNGp=`stp|7y*weUvFKoTQ`@r7d{h9@-k9k|2KInr7z`ndEoCjg+2R;P$H?BVn z+W_zpaG-JhQP>87e*g!Ak7@E4lA)a;sOxcCUCvNkbHHKX6X0<0NpJ-Cl%_vEXC$sY z4UPhz0Y`(+f@8qvG>^+a7T2B!$AK?^-3cQC>i##5&AF3MOGPZ=^w5<5x? zLVr5%`A3|y7$fn0a0&PUxD@=GChr+%8SH-tmxKQRSAhT2H2hb>{vo&u{0LmF$vs8q z-XG4#{vLDIpeH{8*Mgsd>%h-6d9OO_VgDT50Db{(1i#cY{5Qe=6}TDv8r-7EJw@l< zAI>-a9&@&$C%*-^f&T)xgWqZLUUhcB{yn%8`~lnr{#(=V-wpeJz&+r9!M&Q?Q*`eA z;r!_DF=roo@+WXV_%nC_{6&-Zs&f$bU%^A*Z{T6@f0~B>5!inRkAj6xP(Ds!P41aW z+QI*&*(r)hPe|oR6VYobb<^7poL3hqK_@Kmr2cp6w%lefk>9rkkI8DM$vOt6Bc;eQtF6~VK?N?>J8?kPHT z`@_k`J*xs%1>R^p%OLuC*|2(i(w7C))cMxSc=c9eK!3*-zN+$<- zF9hr4rGy~bSrF@RF2X&j3tpU;JLA+t-b=vxc`2bF_ItQCJC~v#8-SPjd(&wM`{iIG z@CvXoc%>#U*=Yj%RbW%_YOoo2ji%w>9QJF$7T|SYOYnNIl_t+6TKYrAfQ$hd12P6= z49FOeF(6|gnPb4Y0sGL_;EiCLX!fMeO`ez27P)Q)+kv-$?KKk}yK^hb?f~8fb_8z+ zJArqAoxwZ7E}A+P=PsOgJ$8OK&bxu#!5-eVM8_Ued0BDRi#m<|2*D! zba|2f#Zre?RxEk);_KBD?J+NPlMB(ul!^kz4~)I z#!|OePAqx+zWy?jeeSQ{f1c?2BbD!6=k;ps*~1+@fA1L1&$D}e-qEv%J9>WJF`S=g z_x!x0-|n4zN6$|mJ)7+q>AEcsw|Vt&o7UdHyxMhsp4WfwUGvuytzWqOvD*Fh`Om|Z z7p-5i^2bxIEp~3xTL05^c>ny`t3RHjS9Wg4c*;*?UN6SHl&SMZlh3QeJ4Ta-`-IEq zxBJh%GQ!!zU617N<+B|l<&AV*m#P0nD%bOo z|IzOk>DR)Ym;5*Wqlgcc|QO<@?JDm(R=ZKl=Us=bpdc z?mzeZ5^?m(_KyBCJ-c`GU-!)z3`dq=zKvU#@F)?Y8UMpWCC+{yO~UZiz1a*Zk+X`SMtFKL2?vW%+%*@~GJ3 z`pxg}`9+GspD)t6SFY!0E8k|*{@y=Ndu3$e(Q9jNM}I%$=Ig(ftUmMVNk;iz+0h=o z7(9RPJep%(^5}BCe_kElx&P>0FGxq-2e$Txv**RvR+i1i%huPE_0OwEm+xtQ3}@#) zv1qRyvE)gFZ!GPI6l0|8@x<$u9qt%U*|xm?dTc)0=KTwIJz6_2N9%C;JU{N^Y47O8 z6|M~LI`_}bH$SfF*z~_-)a{m>JCjkbl$rSZ>D@)IZ~f<{JKFL^W7B0u7)10Z{z2&XkA_` z{+=(-$F=RcXY(I*KK)PI^*`_EY46;hFP?K$6ajfHpU2J1@T$``{f{60n&%6ry)taq zQ31ib?)iI1ZRgta^N!v%@96n^=lZDsMY4O>`BCdw6DkXXXv)%Ac?{mUm)C#J?fjb7 z`k!|_wqgLHz#EU=F zdhLwnXss)&bSK9tl%N0FWIHFE`Ddq173cRtZR(Y}=d`nn7pr>!Z#}tC z={80BRc=%G_BMq(wkxEL?F!ZCU-{Y_+LX~}o!S(>qsAkZn?5~!`pJbZf4H(Tb-ty@ zErn}od0LBG3f{T;JSJM;KXc=oY531HU zmlQ6f3UO+ygRTzes>+MAug$qAJLkgeoC~sZ&d;V+I`x%Xjk4KGo@)AVA*cAMg$gaY zDEsN*Kc3uPW6_1#uMHnnMd=Y$7G0q9^I8wDvgmxJ$7wyRit4f@=p*M0mHUQ^o_?ZQ zdzEfzs!P1QUbYV5QdJ2WrBCzJsH@#ZUG6nXpQ}b)t{Qb&cFv{QIhP!3Q8RT(wbpG> z1>K^{LM^JN!auoCd)=xFX-h_)!9&sC#Zt46iT&S{yQ)8bf*?pBvnYuW8+6>1T`9WC7k;dZoe z8^mtMjflLPDh!e9(>z7~kSak1+zSCKq0d$1x2ec)&Ca zTSLJwxxDg`>_@cQK~zLg zF@XW){Z{qNbob1#?9Pw#JMSN_=R8k$byrtceX6_f%-p*Jdro33&u72_9G=7uqe3z~ zzZ{+q$`%8%ML*y3+t6k1>p{wMX8>G8E_h@2Q?6TM>2w;KlUDLSoCFPUCZ%_u)M|JK zDEd2nFvoH`%yTRx#){>BSU?D~I0RHkMl9DLmaDSG6@DNOpxq4QDiw&Hf-A}w#}JNV z4yW8unUFPP#UWMWe({eJje6ft=SeC;) z$3kMPSe}IigzyB1fC|Zo2nz_| zZ4Lnyk`c?Th-F%~xWx}-Guq8Srl~;moZM2rIA(AhAHh1uL1L^pw!s42|BT&7g=EBW z7vh+eEoNqm+x<|!k*eRy;yV;{6qS5|Yta_tDrGveWLBo6-I8P7n~m$LIXNBL!{l~o zTK8m|r^UUBf;W(ly_pJwb35v|K;u)cKBgjL-;=R>vq5fm^|bo*{|zvAT5Iatfj;M+ zY-q~sw!4|p4`^jZB*tR&2Q0w+Pbm0elw>fP4@M7Wi#a}^JyLJ4EdE4c0(wx!HYM%$ z9BZKl=r3qm4+Q`%RDkql;@aR(v^f!c{w7-sqxt-UKIb9DX94rshgRl8Vk|zDGnh{r z3g$yH_&g3ik7kSI*A=RBbptzbrnqm>zv7>m*WU;%5WHVS4$G8jDvM$cx8RX(5- zrQS)h$VOoTdRE59YiO+oCngF1+3Xr~rTpP@1RRo^|*;*UTCl`Ir8pUTd^T|Ui z^C2-7pVMIhd~6iVhh*@14SZhB7B6Ru7kxzarD_9NG(=${dKDpgYv>IPQ6p$tuVID5zXif^f|99MjM$?AzGOciLn@+1q)!*3)7un)7pHB~|cY!P}L}Bvz0`YhY=xdG7 zMbNai2F~fP6(7eP$P4H*37G(ue*Nx!vh^hEUq=(`g+6DiBDRHz6{D4jkr<2EKv)2= zOHeQ|l0ocy5c|%@HApI5CX35an7F>vmeWoR*I;N`KLl{?RJioz{V83eXYp(|E zCTLoF0%!PM1LOl%BVnHY(&h)sh95SxgCiIEIq z|AN>*KCbCf=~h|HKw;wgM_XTM^t{f!uDlJJ*8Tvlv>gAzpT53a8)aW#x0CU-9M}k7 zXWoH6XTPHLAJdwNR;EQ_ELso30%+ZXf@zTqT2*q|h)Ox4LXP*ibDq?jFN*~zOkkCA z)cI9i1NIO!t!g>u2Vivt%y9?u`ln2nSb(8rD3}<@Aa*2()%0;aA(d9j;z<-Hu9`AZ{y40y;d%<1R;>W8+6tGxzFZq+ zr}Z=$uN_Tm75bc7iq=s~>lw5%EfQnVdLI@*>va@Ni)7Fepml1FuyaH*N96n1K0vQ^ za*p;;{ZtjZW4mjN9;zo@fb>v3A9e4c`VFN$RIkfHeS}FkC=z1@wG9>!)Mp$EDkLMQ zMhL1wjyOF>oaRUL4Z0Am_Smq2ib&7q=`tY7rgNGMNPE=Qm_7d%#@KTbV|o57EWqI% z>@X@M!}AvKym^jjmLrOCM4|8eZ|F7C(Ofz2G=rCP$wKKUlHT)E+(PL+KgA8FqXE9- zNXNG%{x=;hIkY{PibEqYR%lt79NIoFG?EcoTZGmoN3_lnt^BwupbIf;Nok|v(v#9! zhQ&!~CBxE^axQyb5ysea5@UIOl=QqBJB*}|49~m3^G-S9yd2Tq_q-Om%;nTcdG4GC z7m*P@OWP~g!`Fgop=Y^WIhNWm&#{mgE0!EsKnTZi2&j;ZSS~;;-E+kGejo|7n}Kv! zf#@kXzkG3A$Z_PtI>$j`tT^hz0^GOQeN;$B9G4)DJ~^T|NA&bVISpOrYU-mxaf-E^ z^ekU2mvSuiV4he zVV&b3F;*Ps!2;Yro83o+WW;d|;n zTA2}vu^3H)1uz8YTZ7`qPBKS-rTX#kCnT|eZw&F93`P_2H&k1bGq9Csiup!+3c0#y3vy!XuKL9)Ien%F$_ zIr9~Vm zV9!gv7i6&xg$Zn>w!WUxfUSq7wJNaxo>9OYcOb8?73E!DFOv0VqKUnPK4+C8_B0cF z8Ldo=#8|}Mg#{3M9R(938N}9t*lHiwds1nWEZ#?9;##e(uXP%(51?ti5Wuxg;nLTa zYoqMz>q9cWE}GV6^f@mmTF*1BkI>4rNQ^}*KZ|LdfP!g}3|bWuZA4~5q$kAw9Pw|C z_{S$_LBXn&u-jfAM45LFYRa>9Em)(kq<(FyBE7mP(Q3!v_ZjiNCuq*=wv6v zi3xE+LL8S6$M|TvKmqXNJ+@6;vK1G7%bX~&5F6(N$%5E8$7%IrBp9OO{>m_yAg)U|98^d~Tn!LcQ9=|ZMB{{L=m#|zz1Sx*s5%r>QFKs+XdW-0WIBx# zSpVHQriN(#r8;iV{WzL&99O_D$3bGOIL5;Q+#kvAqe3#`Xp1=7Bt+|kXq6Bx5~8^u z$^Mj)3UkUj}foDe+|;=+XJ;m5KR3T7;QR4h(0 z9Q7U%_0)p7Pz$C`{i!y8;au!j^jDl2qNIIcq+*Cxa@ z32~Jl#B1m>gSb`&p)aj#B4fBJ6vHr%VI$0P3?#;i;Uidp>u2@G=}B*qHldsu+~U$XzGkc>d4Bao>H zF(n};CB%e;80W{b0}9rRg!QF zpKMV_->uB!Cnz%y5@YfB7Z!lwcNBc|kqjPpgU9TIxHBQ{NQm2f82_Octh7xwTanP$ z=baJ+AANUdiM>sd(2l-)IFS7?%z=;?E0AL=a3D2Ma3CZjkc9|jK|;(+h`9;zKtkN- z$8sDLtVIdyZ#}UKR5;E&`06Egu8fBh`+!R9eKMRfCH6$j=PU{(R<@|bKFmB$f->_U zF&2+HuztVjoo`^u#WgAULs0wZtx#B(%h? z;6UoaFb6_ntU#K=0s?8k{-Z)N0(lmJtV)Qd5@MwvMKg3+&jl`1R;fUor{JZR(v>n2 zN-5tl&=rUq=>hUdpB5SN+bDHqjVYbyLRpn9Dyt5|XbEM8L1HWz=fMIPv_ZjHB^fZ* z0mkzQvBoFS5$!-E^LZLwdp@r)==ofu^66eIuV+^~!2r8TVk}pSVF9joV-Haw8Ln=G zs~ZyHm4tZ7_qI2>tTzH%af5Q$c}2_HONS(HmtsoijZofXi^|*U45KfU83u{5U|bCg zU@!;;=Z$2*cn>h%Nr<<664#&|h_t-DqcG@sdn=T;P3-Cr7+_aPjOFTRSb(d;*+W!F zhO3{#)sGWmb3%OJdwa7~9V3ep6tt7n53WCU(?&m*{UV`$7&8`{*5?Ua%E>_M(*pfM z1?sp1X|p<;Riw@bsN%Baq!qhId6Hy9a&FPKE3TMs_b+85xPOkUb0wKsFZzBO@8eeh0E&6Joay zYmwAjEQ=*5Ojy6lIQe^my&9~g(6sgh*3@1FOW!=M4gL_@9l>WA+1eY;XF2+uJ&MmC z%;yobG9MCS@o``Qe4aqTd`JeLjNCRNEm!=P5c_;Y&q>wQvRH${M3k0Gk>NM$c*R&Xz;z06732ylSDc(Ha&x^$Z(m96Ewb2(!X#DzVsu?V2bIu>eGN^k zPOf>$D-R;ZKz0U@HOdtYa>eOBuivHWAF|kk!sOLRTVX{Suf5Q;ngn#sb8RrL&Kj`Iu(6R4~45cwL01EE-og z^f}ilTtgXGceFAt5@X@&2MfT}69wZU8Mwv**O*)}I#-O!6(fCO{iXH*SqwyB5*vf4 zycISu#Bm>zgxK5p(E2id(DL$_orRpeI+=Rm9H5~}>z0Q=h@j2G*8n2t7 zY26m!b-UuFuQ1mJc5e>XG*+TM3V-i=TRnY}%l)>!m8w<%gPnASM7GA$Bg(YgZ` zKx;AzrbRMnJ%|N1Cs*8`EAGt|cjt=PKC_u}z@4&~g~DVuM_XeHG-k7*Y0b|yza(6s zm^to1USs!bYwTWajoq!)XGg5JyJ(UH(FE^CpEF+(oW}(3K`Rp^F&4o^umFN{P%uG~ zLGUpUd?Z&a%N0v<#UdZyVyV4E7E4i>_#Tmw^P%>HhHn`(trY=$Pbhr)l5=hFl3S(` zTcXt$MbKMLb374E?-BGlD-^xQnckylWqKsWqPGqfK+i$J^hgH1=Roh-T(QdMwqEMJ zD2ta+nB1O4Jl@f^R^#?EG_5tc=A*Q=ikssOW}ylkcS7 zc3FIn!esK6wn{c>Om;xidN0>}aJNY@aomBtO5TWAB|ngXP0>(xqR)9xL3x*<>_RI; zAu$$|y|4f%zo1|!Bm>IFfU?;q@~2e#OBR2lFo|r|R>@}?k$<3ReHtM0nIfXE64!>Y zO7_wC&!U0+i$3R51>_S3@*i3m2#K+P^sB@`dZJ(;Bm>AF0P~MD`k@U+7s8gI6;f#XRA_qU{zkL+!<9c(-TfkAKYM;X zjIrk=#`1guEWqJW>@X@M!}BV6_^ZP_Q6W!c=85z??@`Z0^qP68l;=O;aw_D>bDr{& ziMsm}E0vdY)fkZ%(lh=ZscIg%HU)EXj3ma2@ordvq1!k#R7ggQM>S0O-wR{xIf=16UkM9vcnLd<3d!(18=jw-Cr-!{ z$K{D*@1*C_Z?f@Cmi4o1!LM3E2Z2dTGH7Q0ZGfSS1}rib(` zH9$W?(`pd_)KUS`cerbV`4mO)`H5_`jOOz*`kWSu&za0;H(HqwiLvDMXGtkk?RK#l>l( z>i!zaAY+}P8D*l+>8Kc;$BeSj%8W>i#pp;_0HbOsm=VcfbO9K3&lBhSfR2)SwPaBn zg}H{h%Xs*1ucrp+XlPm&1pxI_fb=!w+Tb;GegvOm$X3s2KF6ZZxk&N3kog>kR^~%u zEIu|YfKLtz=0h_03<944d7@vQxHL~(>{B{LYM&~LIw(v^0}z$Bj0S6z>O#}HJP#jL z^0TxlUFi%~lpJ>;FQa}6jdQ6ysQJsCi&eY7r0S93!O_T0N1t=KLUtJ=tB+PjMq(^v zXTk!Ioq>Xpkql(RfNW@<7?LNh_Ib6Csx4*F3WdpQs0@i$)d-DOYiL^62Y8K8y!2J& z+Tc|+M8kD;1g3D8OZJcvfJ{+t$AXa&+7`QdZjF` zLSgc{O@_oPY?j9BYG_(_26)Xky?yP8BL(u2ksc_9?T-TzN zagkVFT-VSGq9@?h0x0O^I*f~C;5sh9jW{M>)Xo=2<%=Wo{kspou zcP+K^<@%zF;-gSsPZ!8*bDSek_ugeu>IKc;ac^!CuO1>z_7goMF*>|2^Sz}djo#%9%qMUaM;H7tuVoC2g9Vbigr;HzakoR>9 z4(cHQA^&?tI5!KPtQC~%*r=y+>h|^J52Bf8< z5qtim=Q)Y7Jbw`u;IP9Eqe3z~KNFs(@?~v2@E9UHw3I zq1_Cmn+ilvLD%xdaRJBiBdl{AB*u#4FIa&4zp(qLkc>DkMjXBKMX!8uksr$6=rT8V zZxxEuOUubc<%{JKj^!Vi=U7OL6-#CO87e|ZN5LP4BqNpqh^1e?xYQ4%3fj#;`l&$l zoLpMII0kYYRbiduATd@P$HD^QsLAf5LNemG8gX2iF9zp}%luI2r8edczfy(b4AydT zS@~kQhGRJ%<~bG;W5tpW3kcyP4gnRC5z8>dGBjTd@dL5YZU!<`1)}FSktCgjQxmVk|~y z!vfGWN5T7#WH6cnMw9Zz1RqcvsdtVn+M+N4O_H%qNn4*|P169K3r%Zk0MIlANM9zd z4gN%%5W%M%*_sy3r#eDSab5t(`~LoJ5{{a1g)%l?LrXP4*F)1< z5&*PR0n*oyYlHbLh~UF7!dV*4hhK!VMDbb7d`4n+=0jpEKJE){{1@Sn3_eeR&&qtU zB40e_Bhp@igQY}oxG@o}L`dEmdPYMujS#KMH&5ed6e7nR$ZKeYi#pqsGK*Tdq@ERf+j9vhvwfSPT56FFKj`mI*6VO^28?T`k zH9+**9BX|5(2EL?zJ^>I%x853pSfh~#b`eCS{!G+;7H`nwU7m zEt=Q|=ySeS#I`cA57ElRNQ^~nD=dK6XDFB$$so1^#J2mmzLrYcWbq9O6W4ZaeeKe4 zeG5%%X8_kOg-c&wu8p#Y(-=mdjkr<2CAFu#gKcQe+B!ku; zp!Hk6_{9gdN9ygB#h)llV83bW>rV~XU(mGn2F~|C6)?vg$m{Eu@~*GH$@-ts#Qs5_ zvsV$@!^HNXm5GrUi&#bc;X8<>@t@tJLNbW`2V(ntT$Q9!Wm!}~VdC1St*>-T-M3VQ zrj=%y*9+;E|6o~PU#^X^udixkJl%qg@O?~m^f~zI!~2JB_A{-+(8{z(j76&e762(5 z1+OoXLF+gR57jME+Y(1v;t0!osBWXzs%hyD)m7|HZA*Se@HIS>j~h`L^ga({YM&-YI~Wbjd>L zu%!3$p}O>*pW=qo5&9{N;LzG*DozTCu|n$!3y6r`8O1A&WQ5ibq1CrUJxkQ}Bbt*_$JlTuHH#Yw3v!_tz{h&?ZcG4`CqSf0~sr{H;Cb{G|s;du(4H?>3)OPt|* zPH&Pjms3;axzhwLA|rg3o}pY1Ukip`5Z#<(xf13%77}B{G6EJ5!VnGt6_OFlS%{^j zCC>B%xdH8FAT3oOdJ4`gUmUGDj*+m=agZ1*j)|}U_eZn)sE~{}Iv|dAmS}5Gmy?I z5IrXy%NNJ_9LHU-&T)_!D~^S*0QVnY_fa7kar8nQ7g^#0OLX@`d0470lEq>a=I8H4 zGAsPtu#finy9An6Z_8YneG~=99mrek0)@fpj(YI9;ZiczC;Ic2Ubf}*R-d=U%xF1U znGuPx7_EW@pz&Y9MKTx-1f%|z=<5S|M(RB)3wjlo38=q}jqlel*8tJWwXDkmfG$^n z^kw4O;M22j1fSJp>+)zmYtZLhruYnEK5Nm+d`OJNXCo|t&w3R6DM2#$3w3%FNh1^@#~sLPXo%#@jINGgMDOpiMnp4u z2Yt@636A{mUvfYE46jPe1|E4iTel`OWPFaeF0vGE!j zrvcguO>1lb&^QH1Uqh}9<})gS&(~yYTr{6;=yS#@J|)cO8?-VX5@YfC1r`wZ4=9)q z$>1{$d~UJCWS`HkQtvle&(;;?o1yqP?m%8ZlO<#VRQl(< z_snMxS)UP2Y%ltpTNSbCOzcmzGBFZk5zDB+#P-1u6C)YKW`WpDA6KSS%92F|6eg~j z+H$&E!&MQQ)?EQycPm`_a&m2yomM3>es?sj%II_MQnY3>ttx0`S|rAzRSOodz79jd zv`7Z6d7w4d5)b&mYD>MNWpNA&6WCmBeLbWBqZh4N3j+J^AqC8F2lD!QpuFqrII{jw zG_m8+=PXdf<}k)-ZUtg|`vac_C$(!{^G%bNXXSt%ajA_+HE7Kw|7OiVw0kj67U|J-D)-Ry- zvn77C#7;}>u*7zs9KE8-`pvS|y0=W{(2v7@Rs@_M-IYeSf;(M|^mDfz7X9Rw{=mc8 zj^@|sZgF?i%Vf2?!us9|qK9Et=Qk_(f@s-tRx9rX(Z4d4;ZSBOB*vmL9u`35Mifki zWKh`$Dt}wzPfP5v#P2>5dLtEx$y>6Q^8FBm%aU7o%$0o(meh@FB%M9Xp6@XF_bx{B*x5F`v^qlvvrK5_=Z&r~+l?L1HW($G`%3)Ih;JNCuDdz@vRqoSPKqB*oc240@Fl zSZRrEuSn>LJy(L@#Ga!i_H0Q)OKe9D!;boRsHmoxQATA#SN?MR=HJyk@`g>cu)Z4Vg|=eC>5ZC6$8EQ2dkn(M+n zr%x!&vPGr2H`6%{%1npESah1h0-!WxD5#JOI+ugaprja(6#bIo(xkZ9N5d~+Dt0s7 zg}4k-T=Yy2kXSg={j^M9s?{%+V6?0c=D1pTagi7+E_wqI!l9Qj@$!{#B(knYT*H!L zXi^MGimQ|2NO0aH3- zLyK3osKr~tFh)X|7cYsiU`&7oBzZInPBO`WF&Qu>CdGK4#6+|Mk<4v3TC)=s27S$r zSGjesYNxQPlVE^dB{7z(GhqR)PGt{KAsMdT4p(O+#q^|@>U(=9x~!Rj50)9qVQ0FQ zx2cCDZ+Bx#XJ#mGvPI?X4u)|Llo9C+?5owd=d-M4n$hs z?ot@^yv+*b?Ot~EVHjXnNsQ&{ldu3+m$HYbkPKHJhN}-H#r&jrFe&CF#r?j|PeH+2 z9N2XaDYu>ZTJ|1P*>mQ|^Mh_S??>~2Z#K>Ay=O6>vpAGG*`iXnhNaOy|~j}_qYSW-Na6w8ugi4Ws7^n#UkS@4)5p(pSWl|W~ic91TSB(x8RCpeIe zFwB9F7%LEZtq=lvoBc7;nlkK!Y#`mroNL18|5c?M3>IZ7{cU6aI> zy!+3we+Er!brLsf62Jv?@~lw+9Csj%cAnMAjIBumTKLxwU!u=ho%DbG z@EkMx3a!kD#8`~zO+Y~N4GK;+$zb#{7`>Pj>wG}Fq~4FR_z8sx=tUVDKS|%90on~s z>(v0D4GNIHLR=esIk7H+&#z=_Lo}b?(C56W_`Je=en%_wAu$%8D(;H}P%s~o!RJfx z`8+8;O^T0`VzW=Fs?@F~i|Qy$N}nStZy9aXC>;h(YfI9+Z`!ITIqpDSMxRR5jOk-- zBW;dAR)Y+0jYf7j`kXBa*;kCLCR!O8iLsDn!vdDnF(?=r$w0Of$aW;f_N4gM=anN> z6SBxfVe;A`L*-TVlg29#n%0j2UOy>b`l@nmFs|(yu5Tl7olJIripG_XKIcb;YZv3P z(8{<-jD;%&3&7P71>+(axc&jIzmj5aQv8t=zxl+POYJjd(E^1@>@P&+t+4+zVlAO* z{hKsz;Qmv@9CskEu)PvHBl|-`_FDw9R%H0UXk=%h&-qs&+sDXSqm_}77zt8&R=9WEF^v0`E~-SE+iwEV`jEc~vZ+C~>f_&#|f%sDr&bG_9%yCa-D* zbTmV0cXfS*xi%PARslbBMP{bT}Ag{1m5<4S1QbSfV0@+n$_=IR=SEJ84ULiYW;6q>%!tHTjP8d81b!z9W<)X=)d!<`1)^?&sN*ww zK&sA>#at97qk0;nMjE3Bp=mWNz*ig^qedDdcOWyWt1+q*!Dt>CYZT3BKKh)7icte* zv;eKlh{RZo99RIO6)2by$zaq8jLs_%?F+=Y1>zhZ({oaLwJg@4FfpBnsJyM$Rl~Fv znpT$r^D?}vhRGesTd%!j&B)Hxkew5O?0GWWH5%Cq=ySR#WStq=I;44x1^fl+&V0t4pVk5Nr@CbVU(i|nx^!`JiGe*(7 znd$9EE7Kz}7Cm~;80ZDxJ9Z1`O)d}CsU5Wn0(w$ZSPKUrDYF14sdlpB)W^-iqeTQb6uxAoMmgUL_>P0@4T; zuuAClXbgm80GSIQ4-|;|d?t;h9=&o5>V+swCJ$(#jd zw2|mS*fO+!6x!=5G<{RQCWGLQhgVhI{W{|<_WVW|W6w#9<@sb-faf=}!>Eu9&p(3a z9~OxB3&eW`;vL`lDd;ux@}Y9xc^_WV;ZAvZPo+TRLqmmR#JB}9epw(sFA$&l0nR}eg4eS1r3z5b&gUv4&ZnyGW@jsVJ{QK= za}r~D{xmGW;YZnFR7i&BJK*{D0`YBu*yek_N~%61i)T@oC&+d<>3#C<(oPTun%2$& zb4l(}K|Ah1K2yI{kviK{-TxGRj*RV!K3P_y&)KO?mLHhW8niMa5@Rvi01H5~4h8Q$ zlELVAF#5GX?Dhe@CiOPT;&l`zpkHM?d`Y)g1M~(otvvxidlevkRk${I&+d-k^CsEa z8_nk}^f`MJpFfz-+h}DzB*x+1XK-xyyuKHH9)^X z(>mP7kt0u*fpqTI)Bw2ydEr!%MyT#X`GXA9jE1rYea_(uN)3jx7p)A1#8^RRKfbu^;Io=k>+Tv(i)bi0(mD<&0Q5}Ve=6G%GWNT<@K+`(OHa}IeH8kEp`cygA z}jRt8C8ERZ>{fT@o~ z!5~QnNE;xNw#c_do=-6$RdZ#Lhr*yCE`OvgZ4N$D3D7uFfe>8hG2x7j1 zm{)d)HqBNi8saJFb52zdPhp6sqLm?%7z<((SOCO&C>SEifY<~O&#*-!TQso6=|0CI zsohi-%}|&e&p@!=r(rXVV{>R)O#>X8DUOaekXBPD9>S(z0k@iNjwP3 zk`-zAuSW5anLVnf9o{J;b!?~fPMy*_62VTO=k&sF4tlvC7M-m*y_{!yO~_5u!P%2m zXUf>4(i-6Z(z6QE(&{ZZa&a!Ma{sKGR`gsi4DZ4|P&I}Rmv&0;Lq1#zAJ)T%7kY`c zy~JwIlfKqVy(H}VQ^x;O7sp^f>lM|qBo{6HJEaeFR`;6Ja&cXDx9P@SWO0!FI(c`Q z{RS16!;tl0FVD(gSh41j$R@5RdX1E>wBMxSD$t0Q|3w+&cr0x*=Ez-S~bRY6{ zhm!6>U-vqxJIsEYbcd7f!@lnIq`S!19U*l`+V7C=jikHS*BwQ=OMKm%r0!_@UDCao zbeHv8dYb(U_8PsM5IQ{{y$~KMXwLLZ-wwa01d3_2`e_@aB`1s@cbfA;c!Ojqm2q&3w~B8vEyu@I z^g*vQTe@%?4AX>Zey5F2ID0!fcxMsb7(1(E9t^d6@Z@Bt6s`f6f(s4{Q)VWgf1T~eH#!3uwY5d5B zpCl`wG5^rh_z5)RBu~4Ol!pdJgT^Y1bZI<;s{J#!K1=pML!F!@4mFjR#&a0t(%8+0 zSCbXcc<9j6_ysiNBx~JC%0mOALF0LhbZNYRs{Jdst|NP(p*|Z*)>Bh?X}pL*E{)&V z@JnO`G#)YvT_f6DPUK;OXkW1q) zHv9ou0ga`Hp2pvxAt%}FPEsBk7!4X9VWdmrV^r;bxb+jV2O8QH%cs;-UK*cakV|79 z8~&WEfX4DePvc+Ekdu7rPEsBk7!4Xb{p{J2noMy{OzH=uj4-Je4jqMoe(%6A2E<)wUEnS~j-|~ehu15GGD}`$j zzPwA}W0)!#DSQG^B{PM?mnvB)oI6yhkiwRuO2rgb8&xW$0GcjDX&PHjvJ+M3D_p>g zJxyL2m=}Icx65myT{I${-TetwvX<5oH&|&!UozsKsXv4JccW^}?WGybzy;?oIrSFi zZVz0mWbh3cwd=NiAzPVj>sM5r&-{xVnzm#e+NyC}Rq6jTvkS9W_cyecJ};@KXZTl2 z5wqLU)b9s1Rhkh1{sRW=3hdS%R1Y3PMb_PW(0K!v3K>LZ)eH))a_OPTDgKN-#X&;; zi$bo%Vfa9S(nZ@zOw|JH2gYy;%W7!Oqg3& zem8K^G1#h_9^K^7f6#lVdOdu-P0zEPnlLnvexy9Fx~@$3hx8wmC&B3WsR^juU)TR0 z;Y9f1)G9`Xn$%_jCsD(JX5(j-hhw_-w$#q?hszu7qu53QtxS=`I22EX0l+&21t*qd zP&^(Kk1ZBQ`xNV--8s692sOQEgvV+KHRS^#lo6l65eqoN5tA4v;(9QEh)?4{Q6U)- zpM;42=ZAYb8lC^CaE&lHH;pMb7+xQm>`!(~e>(I0@Ze;4kXtNrq!X4^OuIR){6TRl5;o%Omg(do$lcYY74Fr;Ho{T+iz)k#a4O+Y ztfke(OJ!rEvSG2P@20ZQ&E15=5tPa%dMca2`62{QjeaW8=rl1>nUP!Alv8<&-4CR2GXqCu0@uGncu{Z403B0ga^l%ec>}Cv?D3rk7dIB$j^L-F9HTnreqtn|+ zAok+LoWOp?PLDDsP}4JF=L9PAGJ$>F1ZsmyPhdYz;2?O)HJQL(hz3noaj{eEUy(U| zRTg<#FN<_9=N_ws2B`!I8*w6)7b3{{)uomC)T@VWgcG?J;RvS^Wvo<(MNj`rx6l}_-#ao1P(@Me^i%a zxmOR?2qJPXVtP&>%2)~P?j`VMB=DwUaig2S5;tSm|Fjp!>Is|x=f@#rYV;F`MrW*% zz{h@BIt%*zB$aucWxDm{UdIf2vQDc58I#~>OsStZ3zNio88 zCaDDSjBWy}*C!Up9YVJe7;<+LqI#&h9LBwRoQD6DyUM|H6f<+~P{zvLrN|vFb1&f( zqCzrqH4~YrUt$B46DHaGE|wqj!fUjriYmW ztAtGtH#O=-n7&?_9zmw>XVW*B1FMEjk2Ez3BTV0@OphYd53uQ*%z@Ryrbn9^Eh0?c ztW1v~({tE#i8-)(*z{Oaqiuxgamw^~GCh|~PcR1_7B)T6)aV>xdXh3dnM^;(rl*(# zYlKbTVrpC%VS1`EJ&jDyW7E^kfrp1p-)d@H5@C9VGJPAFp3kOlSFLxTibq;szmLUO56 zvKx1`DWro1dTyKoKo;o1a0(&QLoxEkmcGm+$1=L5+jqj{I8PEDgaMeGgMtq_l5sRH z!O^&=SS&0S3;d&T9=e=`>S$apkH-0EwjW_)3rJ%@;ApIeQ?c+-e3YmTc_Q*h)gn3- zv#B3mJcRKSZF)G zR$paKCy!sA?iph`dFtxZp&!#d6P`|XJgcU2Xu4-v{W)_wc_j06jxn7)iS_BwkLgy2 zr;{CP)O2fUy60H^d2>2>O!IWBjp^j+tWSr2O!q=~I@z&KO}Cz=Tf^!vn$yXno2OfA zOearleLD1Gx|hP!$&Q!Rbg$5K&$Ifg=5+En=jmQBrjw_*J{|fo-G=aVvg0*1-A0;j z9jm`?PA89eo^HJ{ojlp~>Clhq-Uv@8JKj{&y+zZ#$m(ya)^||Fu`drEI{vKXeC$J! zjwvgJV~;9zQ#g>Q(l~{qf-22Z*u+%npThQ{%77FWK2-*$uq3H6D22sB6?yC|u@4M%?2|XP^yOVtsXxs>DAE5Oc}t%KI5%T`7JLB%u=6$L?iMK7bjOgM>0MZFhaLMZtcwl!psH8+Hr-btrtbshU-QgQ8vk_NdXri{B!9O^ zOf#|zzja6bK#m?+EWcQ}1z)TnI{C0zI)wVnx*ZC?<8`wW$~1nzyjyw|A6~NKN1A)1 z|GCL|r4M@k+OtJ=;dXbnpP*;IBNLxq_^#XfGx>1*L4DZ4KI{(rAUl3Jhz~!wv;9W1 z9X#S)JlpT#*<{Bb=;&6dXeSWBF!1j|LlGjf(FAcX^;axHtTr0a@HZMXL`^rzON)Qd zZ2!m_`>6U8SO2Bz&s_bFs=K+mpQ^ubH7x_xU%8r2)!(?9LDk>6nn~3^xSB=PJzT9o z)xBJ;h-%S$T&+Z{e{!`ls`!p&?YK&rX(iL?dp3O;(4AiuHLfbEh*27$_^eHQcEA*^ z04oKrs8Tlt|EbbA1@EcSJO$sW(mw@vsWKo1XQ?tU1y`vuC}$oPZc%S@9!0tb zUtNE(;aX6pIJEsFJB~&NCO!s5sk6$1L05U#+x6aeq1lChRjsh|^=j%}i#6Aw__;5h7Bab3^J$yi9H~9}v1Ul%edOkTyCb6IU!z%Ri2&r;A zd;Bj_4K*9qz%4((?GEVBe}OwE8>66IhqMELB!{%#A>XFJOm>s>aK|kN>Y$$+MvmA( z9fg>~hB^3gS{c2@2xy-k&@TPB&j>rLpU>##WY>pLbM;0hJCi+V0Oi2yl^qSq%E6aR z7F%f)wjw(kla*4BqBEe;t%42b!K09bEE|g*LJuP472PbK?lq=L1l=K~Mg-k!O^pb; zLrskcy4RT+5p;){8WD7_herA7jxg;;(Y*mGF5Qu++SQrvjpjf_w}MaiCQ~JX?r2jZ zg6_?xMg-k4rbYza5>q3B?pRYJg6?=|l%MVd({2>qiBNIrPD0f_jOk7`2P(Q1eY&@p zDiL(2ni>&wrSXV?ZerHduclPSjBhYK58qs3-@D`=0aA4 z3lBiWbzu&wc1?C+E=?yN1o@X24=T-hsNy?ddBH`OoYn_?|BJzNd1a+=%2K6n3KwEj zX`I3}167)*@bN~K{wbUlR2h)MvZl(w6f!`SK`C&cioE~D1u6@C|BGu_7Wn=bSFv>e zOWxShmxbh5W)Yqd*?2mHzC~!z2$XEWtq1*wOTmx$QZNmh=3%}RTuQ3u-B91`!Xw-p zgk|W3y+=@(_X!_H-4q_>j(QC0s04{OuG`(@{P}vsF=4bo1+3c#trCcsD}btg+|6suOzrJ{|f$21w-zgv$O?`LZ%NS@ZVm%k3=`(yQ5sybtaD#XiCPV9D z0~)(kw4nny8_P9mW@(fD&z`*q4gzOL|NjIc%c>+eoW| zA3Dnw`JrSFj$pspq*xLPR4pt&P~w$Yt?9?|sl`XIV4uXsK1Q|ZBR3V+tl|qVyE3&<6PW2 zSt<3|%r^(s_?FGuFpD|9BO$ZsNX&tcn!x8z$;&tkvI}$E$+trnLw3*%##5$GqK@ob zchpX(Q@F-w&@P%b%Z3gN{sci^*`@B1Ci!sl6XSeWfAPk(?7}=m12rc0bHKQ9D3V|F zxImuuy927_JCxJ?L-`jDuIOZV0Z-VAU(r;0-hMkolmE_>+n5|=_XLa@!JD55_-e{> zo!uK471}xKWijR_!k-ve_Jds=G!X}TlKuY+2FJ%nX}RDC|4bg? z_%#5vY71iJoUQKCMM-^Xa$zkM<^%)=GFi8`or(lJSaMH7- z)?qXRZyaRvHAu)TO5iBKDH=Rp=~W8Zg>~FDb2xNi>If9(@%nkx@mkj%brjUiEdm?0 zXxc0rIuMSApi?aUcs(6%eqQ?VdK#jE8Xs)O1dJOe3?uT7*JIhKqIwt&3q1NbG?jiV z9?yep3_>LTD{V6KI7`nitnW^8VqjEg6&>g}JBhs0zf#mGhOCr&oHbzovtiK8l`T6G z0T)Y6QDH+juv~LgSq~ZIsK03rbb;qxSe=ZSa9M(hkp;_~Hhf_fF#$!5UHPTll}T8z z8?mthRExggU1?KmV{SbK)!?o?RcY2i6}wUnBX_JXc~`(l=?-Lo|6a zp4`Ud0MtBS)Ck_(?6|dW<{~>YFe?!uYB@CKNz?L1Y$~BYvh>N&( zY0fj96`o0Uv_Xfyeo8-9&U6u;V~#58v7#LHj};0(c-xp6^Oi4Y=l{an&kg{GQxY7p zd^?&H!>8l{c;S@XDo@Eyuwb`fW1Ueg+QO$~7iw+EtzA(Ko|5M)&2FgTl$68B9cwF} zk}xSxNm!v%lJsn;)t!c9+1N~I??FOlQ6Y{3?=ZXoO=VwDt=t85A&oMhZ1SU3zKL&< zUD(>yy9j!iw-*X~oBW|sdf_+j&tZzuY97E}M;*Xz*!A8}4(vVI(FYyQ*T$)9xN?r` z$|W?L{?Q-(>%4P$woAja$&SA0z;D&sf*=edw0>wPLPR#2Aoi#JibaUkMk5*qqCw*; zx1M{CHBLU`7-XuH^T&+p$>HTRcZH&};hV>QFq%p~=&$(yG`YG%zLF=mF*$<1iiE79 zv*3xhVy-@@C)XSzPloX1HYSHB*OHKF(~75S1G;L*gAsIG7nrS-gA|tz?c7B)EHH|G z_(T86uR-3#Dy-)}rOTq_nsHXEH2S`SUuHQxFq+=_L;uOqZyaRw^?}j9%E4tEJt8og zzV4v^%I5hEfzkA~Ao{Otqeo&ij-B>^50Kh!C@F-X?+VA7w)lYd*AMNJ%HAFs7tky%TfD<6>$x5u7;R*W=E?Hr znGn!4GGk~?3}_lzFf=DY6USa>5I+#2!Y(e6$pNe7ThmhlqsvF>mcVF(l4G7?;dM1N zFxnt@(9zQZqYat|9X%bRLAWajdmwKO7%U&i8G+H|19@9ubooHu9vEFdkaq+|mj*Jt zQD$N^E(-}HmMcCF@1%xI8=K#z69Z>88fT-CR=E47WBic<8t)=a`oj?t0S`(VxJS=hokKo-JZ+v5ZG za(98P!FYXCSr=G#wWfXK0$WSYT){!CLp8L()>HqL-2Y-=vJ%flZ?_!oeNw&@&@5#s zz6{kvu@qk+Kd)jxUk%KDU_UnmG{*)bD)b_HEua~SNG`*SZ8v}Adzy*Ab#31 zG}4yi-X$ZMMT4@Zj@WH@FW2E|=pxxI~@@n_$ z0;-3C&zCg&FrIzO!Dgr5`O4Y19-`U5rrC${?B5)0cKRKxoc-HFH2Zh3gWYp6&rgZA zF5%sSWKotXr;rt@R7n94RjQ`oEA1W{Y0Gij$w;P+^p8o;mfakJfZ`hr}?81?*JAVh{o3t!m z7dIl6a5sRoD7)|`H-=2;>A5K-h6+$E1Jav0hKf)QAe9}J0~3Z~P@gbWpo+CU8Zmh8 zR-@5seKhSW&!_5Ww#V?qH4bK9ozI6uwdhhFRg(;qaP^3T8K~rM;-gH}A-FgWypySx znxZyMF_xz|234zjZ}|t_GwF}b^lRzDajbMKlmY~0$MH1!;G1$hTR9a;zTZk`JMX)&yE{A*z)vuTkNM7#pAJN`$ncE&)P2f~{kG{izb{v|NE zE$*QarPCxs4!J_My3_xe1Hu78X>r{S3@3;GKb!xb{x98q{Kv0~=t*$M9eSC=sVL== z=tW){`_^+%-USy5Qbjn$P$Z-7T{)+~_B#8JaW8xLH<{KVjI@&bL-E#xE&7k2jnnGk zKSA|oq+cQPyYj;-F_3s`r!RcNb#xty!&ZU!JD|(V@BatK2C-u{I|jg)L*%LDg9mSo z4<;=-1Y|>;V_+CeV1nyV@LnSs$3T4$X(Q_4|3zK=pLYTbm)h6M;sz8}BXnC&_i{)L zuV0LK8$QAIPXhd=qX{(SWFzHd4bk9`9bM7=ima%RwC%?9{}w6o`vw}}Zzb?FIm$y=i(X*Jzk+Ft+4*wfYIFAuY-78bixJ!wvr z<4xuDKNWkbO4SN`yOTU^PEy&M#Oq%bdlK(w(S?27sh%;X!tcs?4cK1)v$3c0{t&0| zVs|RXoC=bh%Ikj)Ex1*?fYfc?ROS*XWjo`9xrB!C{#ku+mk+!P+rkW6SpzF}U)S}u z5c~z^@51NNT6B)9@&f7ibA@%fzP}6C>-sN}et%d0C0*a&g)i&+uRy>q^roXAEpnE2 zAvelh$R5jG$j-=J$n(%HBrCROV*>;eacCDF0F?Zb$Be3l1Ka>!BX|5ASd!-D*6ZJh ze&qI2Qnxu(=ESAs7Ef3Q(lE}->j!uFz~6kegBiB+2CUeZxvsydyYA=qEwmP$>#Dp> z`j@-HJG#D~+jn*S_eg)RtG`Lt_jCKcuKxi91L3aVWP30OjZQ3O9g{$eoDXdi@`xAGsYw>Ncm!oVb+S;sNuOG>o(I$-!Md zz;eWo8au!YTlo}L?5kbZKhs_JbNe}3i`u&?Uy%MauJEO<@8|X_U4IMd4{`Ok>iT|e zzt;7)K|pT3=_p8xoTc1yqs%RPEOX1w$lUTglv}c5dp5p>U?L9X_5h&#++OPj@Ey4m zkz22SJNl8^t4Q5esrnwx@O>q$KM-b`}^ww{AG*m@2|SQ{!aak{k2)mmR?KNoNO%E-$^0U z<^>CJ4@4uP$lse4j-)`KzE_{Lvb@^y`u+`?D(&}&_|@l)WYd_tB>ZejJrRf;aNuW& zCEGyI9RtVr>yGCf%eQIl0Q%A^V3W`jP5F#%9_>ClL7>DB(~R9^wMGy2+5GAq3P(`{ zFpvQQ!NbG$IxC>ljIxw9o{>{{6B#uJY(XgWU&Id_aCYzjcu^4(@ye)%3gjB0iMOzo zNISUe8xx+mtfz2E2`uxCMWw1uZYDc+gtbzp$K`IxA)P+LS}D`xQ+xEGnO@qlnE`T8 z)62;bGABo(IKWc#S9;~@5v%SzxaY3AvE(UiALZGug^Iag=%1;i|M1VG;-A@}6^pg( zJ?W?&Qcr_HR-ZC{Q(gQUjBEMdRV-OR8^IkcA5T*|{lx1Sn4kske%IiAS{{pL{5^-~ z;0X};U)XOkWXd^?l3Qe6GQ5yg`m%gf5%>ikPQ^PL zA+To%G(jT1ogqgd=8~9cdpqt_h$i^b53uoM#vD+}0Y(IPPnFC=ExV9MGc6IES9_=V z1lQHN(D6U{<;Sn>^_>XLSkjLiwa#y*xzKTNXY31D_&0Kc^TO@^MtRT)M7Sx%ciAwo! zz{^>0pa5v^`fjM~@or?KzKFQ4FTfr6$l&RjFfUhe>N7(hDvykz!PgAps(; zU*59q9a1-l1QP27g}^%ajQYR?ZjYu@TsB9?j$9nFTxx1A38@>7gi~`VPiynE0MHj= zM5g+YR;KMOY9|)hA*p;Y2zDgEX%VG!$ zt25jPq{2OZ%n#Y?pll}J@RsS@NtB|yf;y$J&%mcwW?W8-@6kAY})#n=E`iqyO0@YngckPl(F zdWaK3`eumkB;HP(7*aPwBsYx^Cu2ZFh*Qvv74NOCsUfqb7lDtlX(4sPivTC@Hiy4M zH|*96;kz~3-5KOAed{Q%2;+RIcMnWpE#8fS*CNUIQtu7`Ya?#M|9js$-ir?FPBbt! z{Bq(hzBIj$nrCUv_i*$5XolGbQ8;A9`<8Dg|2m2P0h5Q(Ogi(RqoradHQQe2f@lMz z@4x$TVNj>U_`4VXCofI!foTr%VT`aBx$`e}=XW1P@%(UW3F$0$b(TW#gFnI#ei=1; z!P8H=Wbn(;Ty(cP^bxYN#1$UZ?Ie6VkLh;EytMPUZf6AqJo)m>QqUF!M2`Wvk(gwp zI4Y`UrPz6@R!;H!^caw=*q)7*WJCWAmyxRLw7;_OQiv0b{?U)6Za7cE08OByv%Suz z$@*+)hOEx3?&pL?%hyU|RyFh@j{OY2I#2gr66c+Ut1yo-v}6m;O8PJ2{vG$-%UtK5 ziS#f0ckmJ4Bl7D=ygv(M*j0`jhrh$KtnYg4_ttzy-tb6}Zs_$rxsoFakE4M8&{Q@k8{e| z-O45iNQW070k#MlrGpzep(!Ru)$|mHPt}YR$3WH06gxusB7?SP?gKJ+7t9?jX_cxO z8WBfHIv*u?)rW_4Gi*C#+uyJcLf~Y7L_RzTiIV*>2~WAgCp5@A8u?>9^lLfZaTJuX zkmh@~KP7WdyXHO%nQMkg=|3C>&+}nGKTCd`KVUx(DNmQWq`byIIphb)7f>#m=T7q_ z&AG}Iz6zNM%}JkYa?ULwWn)fiO*&@o;bTTRv{iTLYjWrr*P(5pIYJI8 z2;YR1<2v-M?$CGS(6g>X-$S4T>Ys5~2s_Y>8#fOsEd`6xN=uy^X-ry*b4%6q6eFi< zMv8-_YG#V3p`}g+ZO_~f5Q^ry9_*wZ#}#%#FxOn%kbl(Y_z41bt~VuZ2a9$9g~L;m zw-r*n4XAopiZ=l{PD5>P;BE-i?>>g{E~b7V^K_vq8{%B3{sR-3?QaykElI|O>KZuN zMm&fA_bycTNyUF<@t-U*Dgqm6c^9I?)P?BFXeQH{(9wKfOU<^|Ss~g0>H8O=6@xk@ zcX@k~J_(HZOICPY-oM9WcE20!&a8u@$-f1x9Gc45CivKWTyDdrFCh#DRs}=sSKL^u z2FFVt96ruO{{3+^=oG!^4yaC}Uv-7UAXq26|1R57Jh8E!M-MIzcdH=XOT`WDkQx|5 z*4=F+;d-5iqtgig27K{)XLX0HjyqyVef-Lp9)s6}n(xpN5bW1n>qkPc8oLfXLJqwk z9l9gr&_;L2Q5X_($m^_y&M1e->V(7*o&If*8voh}>V?DPVdfTbh~UbrM{_GyAiK5! zrZR81jM4tp!xaC|+r55wH+}C0)X)vc-Ayteuk(yxKoNfuR20;?malyckR`r9#DQ+v zysM>DaCC|B*L23+9sY7|2YGFpF6GG~ey$ZUz<69_OpudTKK;Ce)W^CwGZcprGA)^s zbyy7Y=8nC>sFoOIy@Qy{kc^>*hirqdI4f555Vj&C@0PLvuNmh@5iLP95S7m@%0LNJ9QmI#Pg z0Tr?LUa^b4_ujjxKYQ<8{@p1Iw--L<^G_y6L@-I-^eDbGCf%u{yvB06WGX#qg0M>4qBcv^SxB(FbE3`C7TzpbLug@& z0*~{}S0IGFSq_fKm*ia7SCPVgP{KZI1kx7I8i9+bGUYaH%!t>t(8VP5D{!l{aQdp)+J-JeWnTANkFNRC)uegyTV>{Q zR3&D|JgJG*AmYW!Z>Vl0Vfcy^TO5Wv`_th{^yf9IKkcre{=A0!(`sx@ih`8Jl4q>O zu4E%4Y$Q7K5TL_fRjsQ968TOcbtzK+%VyW7C`d6oaa7QdQkmYcqkp{4pgxg9u~n%1 z7ybFYYUFBEP3ccfTmz!`W-XA&4~p$jAkKdKFZ*U)ih>m1B;xllRQ`+h{-_K;992`= ztBFT|DD6EGNaQEQ)(GTpx7RUG{ml?QDn&s`dlMnN9+m&1y+13%H=t@tdo^(*h|=Dp zf#Cc_4+Y9weJEAYtjUEW#)xvhBG8QTKp`*?<+va)7-g5y1WE!UTHGd5^|CVR7^3{5 zkj;ers*q!WIQ{I%2TqcE(k3fH{4H5K0=x4Ez&b4+Px2kv_#J5G^m+o>@td;a#1uPx zy5l6OY|l?4-qk|4kkH?i(5;00p^$Ba{Hc(WNrKL}eD3Kpoc^lWov7Kp9nC%!^7#p* zXM!JQ9EGI)7eTd$%#CnO^zU{EB~^~8fUAIb8i>PptLE(h5-~{uD5nz=P{T&T z6LZ>`DV0+?C2^8@7ApTmbArlqB8i!;>wd7KEZ4UIeB^+2I7XjB=b2*ec4NC$M9b$0-B*wx$4L7R4CUc_ zB`IvG6kbJ0x_ujBJJqO?|K?E>QTgCopHXkre% zJ*Bcw%KbMp`W<#V?*xL$Rhv!IP#>Ck$PZk|#zlGhA<&HSpd&C4J<9Vi$tNihE%IIj1{Xe@+(m@VI5Q(FtYz*lsc-otR1mxhlz*G=;&ED z(p}f-vmaj%q^qMU zxuI#VoP(HP4=*cVB21u4jaU2HpFsksUS6vB7WQ6yD*4Jt|-JgUf!^eD$Xfz6^4P0gbcG%ccu*oca221lj8hD5mo zNy5-5_b7omQSM>_heahKhDRlcMnt(cslv!8cPW9RqTH_p=0@4Q1m;D>ANf&f^7tqZ z`N=wnfHE zy>oo)O`v*_0=`b<>m<#2xVQAlT(gj`Q|RibO0Gcan#zRKpouVnDmA|4Yg-Wspn46d z;&tk>LS~w)4M<(ZUN$g+ZTP^~h7xT<<7dA0rc1rw{OTcf9ZWU*(7>Y9#UqRCNRM*d z6WA;&5!E~@fzu)?@i8bWt{EJa{u&bH4kQUfquiqe=0v%R2^5||rh_Y#;F6@TPMrOD%?JnSb&xM`faxLf{J>gtHpg|%CI&R_rt$NFmy z{539P7OojHaM6#1J6W~6;I@m1n>XB$N#_%E=y-XL{uj2ttOwRbA7&c7IvTM6Rd_en z6%3KZz)07=K&W+U$1_(I??-i(C}e-qK$<15rGuIN@gp!^AL4tKu+ew}J^P=Bns|bX zS3taZ_+bElGHtiqbXb0Srhy-iyFF9HSdWF#8vFBt9%LM;gaN~oayJv$G|GKVV0x50oWN#L&JeUE zB|9Q|Obr7S-WFHYg*Clf^amg>{l#*<^>h#DY-Tq@PSX>ZSftrPOcQqGj@9*Xb|=E}4;RO+s7F zMzYwc!eMG6)sfLymi{w_^d1%ite6Qa*i*BT%}I4m+rMp*5oEi9$xWXFB^Y09EtJm# zI((h#ol+o?qZKm$udV6muqNR=as7XxtKxP8%gDe@%D{zxZD6ne4+d7+4O~P99-|Cg z{MQB!`u||yQoDi6fFOnH9;b2JhlVPpP%fmXF{34}}P5TZ~ZUiGWPAwi!Bmzu28pU{JgzEu4hQyOW z>z!%%G*x{w=zWOpwBfsC8#uEL-$7gv&3hclc9`y9(`u~@&a5!#_!Oocc3n<+J2gq( zTz05?Hks^vbNR&NwvRX!_H%!o1XAR5<%2Ci9Pdi@ISCYN6|MEDw<6C_EL*{n?EHu( zZX>;#ksn%ihTG^L-ZlOv!%1@QZTXSa^iW?2BYV(+1L#+8;lq=mVE8G@lv992&Q!>$ zK>Ey8F9Y998-gvMzk}>_Kqprd$98(v%B4QH&_*K#%&jsOV-}a1KjKN z!%I+=6x;&7J{JRVGN=3+)8G3N^e=?C{IDLs!MMiyB&~T%JkPD4H2hMsEut;F?Vq#^ z6Vhd>WxM`n%l^tJ%cjfOCN2B+e_|6}>b^qRbjRPc$?H{5?I_EpE7>M3`_6x26Mlv2 zDrM7Mf77PF=clXLCN29O$foh3mIN0u(W+t@Z@HB_9Km>BN)vp3;RL^5c8zMn{kjRH ztLfepL=jDUFh!>0xM~;0J{aIp>y6WgmC0&Iv&k^+5ft-~whI2ukbVv#An94$ct{hD zA-xj@jLWzdS3RU(1Ys8y{H?JZ&ba|qN%BkJvw8b^DvoI4D=9)-f=vJT*v_f%?+kzT zbqn#^Yf8ED8!LxRucMg#W)=J!zx@XyAnASF*l&cxZ#ScP<1%iiS<${av8#A|?pgr7QB{!x2l)Ew2&Y zR}1+HLSXT&kdQED_+3Da$Q^VQlG%prj4){z)dxx}O?u?qNfp@v-;hmb&2w5}=-#9s zR_jkc_+g#?I{&VKEaO`8GEQlb(g2lOeD+i0dSk>r(9X)gh4RRKWDC6c9U=ECpcal#s*1m$ zA~{QCn_F0lCjLrN=Ag*x^Sf!$^S|dqSaw6Ebda+1DP`wxZgy(oA7tnMo?&jCOFlEh zIZu;$Vl#)g8M;{v=%7DgvV+h1gpnke{|8M81e>*^uO=hhAlSDD_DL)n z=?J`MR8N?MJgblZA zxXpTNb=(GZ#qVu_Om7n5_QON%fb!{tH5~85aAX7cVTW#r8aJ;fN45t~va=(a*ntH8 z?~WVi1F3qpC8yi4*T}s81J%R2<-AI&BWwVC+KF7CXFU2I0W%5L0BtYOq%Zac5_w&D zwKH*@0L0l70k@ubL-BM0PfAZ{VpqGWeMr@tifvzaRUtQ3Zz-Pr+*E1e{&rQ}NY&el zE$pr;-A&ayil@7qDoyNRSJjhL?N)5PQdK#}wc`+q2CthD?<#4%-Hg!0K6WDxAS2#W zY<>UAh?IBH-Hdo&NsG7{p@|tFIveQx)L)NY&S^WWHD==MP(KmLOqP=P3SWLyAS<~} zqvJJZrx7V$)|&b!OHp6gJM8?grAz%edUmqbMu#hC^jL2WVQ>yesq1KrqwYY|m4Q46 zNaR1N(*^_KhhNTtY`S&y2a0D1cv1$kCJwc$${|%BDz;(ns$6r%M~Y{-n<`BlVOMo9 zsrp#4Mcq}o=8R7i&qy~_nmEd?YBZ_(RI!b5SLK>BK2tnn-Bf8}u3c3gsrp>8<-4o0 zem7nRrkeh~P(0(@RB7UPyQ&GK>Py8|V5dwZ%2$dq2?+0PtN^3=0>L;LrFye7>}yrE z5QQmmqKQ*T&j0Pw`Wt2ER5v>{u?R#NI@5qezEy0+)B@UwTSJFGt4!*J?^M+iHw~IN z-L7E2y7PRa3QdHl>J3uizqLl z32YhV1vG)JqP%=2uyvFd&jhxKzCcYSux*qV&IGoL^7@#-_EBDo5ZEEgYXt&3MtLqL zuv3(C9D#d9IR_EAca(Dkft{l~h6(Hv<-jMfYm}#G0{4mXL`mSjQ67W@?ic0mA#ndF zZ(|AU7UfMW9Sl<^M06L-qaFzj=M8&=cjME8sIvgYyLO?4V9ohax74u*m)oLedm+C?QQ0vW}3Z3OS6BbcGyFNHc{TK}d6j z97#wEg)|b>Zw zofL8cA$uw0L_+pf$Vr5BR>&4Yx+r8TAzc-+jgWm5aw;MFDr7q$`zho!LiSh44nn#q zOFkUk1IkB|ctav>po6>RLDDo%u>j1LS`%EeM06a zDC84DVhZ_`khnrVBcx0rpA)iBAzu(uu8=PYsZhu_gj6czTS68oz*`Hheoh5Sy)N`>qp1RvPvOM30bX>bVAlBqy-^s71ENBLlx4BkaY@aO~_#iX+y~23TaEo z5ejKX$dL+ZPe`LeIuLS{LOK$%ULlo~H<$9pzby zz&TN#qX;aI@(e{_MU>|!0xP3DI}unD<++K#l~JCV2s|Xp^AdrL*W-8~$}$-P9l^iG)5;A%99-jj`BRo zRt+YUXG%tg63TNWqx6z-l$W@S&LNa1Pe$hv%F`#K^9kh%l+hTWJcTm4kWijP87(K2 zr%^^L2<3^CQF_ZT%2O$$%L(Pllu>%^Fv`;@qx8CAlqXb18wlkomC;p%@}$b>YC?Hh zWt3hLjPhK{=#hl-Jj-Y!p**=V+NwEFo?aPkO(;*WjJ6?^r&vb!B9tdtM)xL^r&&fj z6Uq}UqumJQsg}_&p>gT5?u3>J+LzFUf<_1}7qlOt6@s>J0hFg*mfV3*o_HDUNGMOe zjP64yPri)qODIpjjP6G$Pr!`!B9y0KMtc*=lQ5%w2<2&*(F{U)?qxKSP@b0=%_5X1 zV@8Md0Ls%bqaz6A37OF-p*$rsI*L%9lo`z@l&57z3kc{+C^$MZ#WKbWa2^$V^SENO)%h%MKaFzuHe{| z>O1|a=cZJDR9D}$;pWU;)c#FlF3QC7w2RpOd@#VO0^IsMq~4+A6GQC;>)dwOsbDnv z%${#MQ*^B{20!`m7j>NeP5FZ<5^wmkU6xil__6+|)B||3D(nu+Zl*dEO^q(r=bS>; zM_3vfI|+@Y$WzB!+nC5zKrBr0;H%n$^qRD2=LbTLzM$vJPO_tCi5%2Vo{Rjo$fN3B zIoruP*fq_~XiY3h7Uwd2@t5#UQ?jPJS9co!wQe?zYkJUUy=ksx%uJTiI01&zKLq}B zne+%*2MD|B-@MX8jQj=$Q(hle*bQUX|^(3 z1)2sL_K!_nSzlGNqOPRArnYQxrLj3+q=$^2tM)gV1kJU!s)u@2UB^`icC)0KX8&$R zY)tLq$yIgr#^#_A45g#Fjr5a$rkM%annb#h+pg@z7jN#hLwA1=6G8v;;Vhc zFY}eLR%ER5kx>tthl#bm;*S*Zhxv#<)K|u4k#V$-j18c9n0S=0_>)BZ@jl{@^_8(h zWSr`4#>rkHOmizp9(lzKoDO1fWnIJadSjDmn4u7|SiKoI1I4!NW+J;?V5D354aw+2 zG3h*Sz32Gpy~thf#r}GCir#Bb(W6JM0?8xAUICJ)E3OC8#T7T8*vA!jh)K73>%GNK z@15>?@AB9CnCN{N6+K+>AV?mrxE~}>S3C})iz}W$v5zZW6qBCw*87Z~-k0321u^1XcaI6@4D-K&tLB+qW42T;h(w-|IA_qYo;!oCsGJgk>bO;ORKQE4D~_EZZHT_Urkzupd_x2>P>j_$%c`3uh! z;RiY^I@W{{&^#J^07$M4HqG83d5lt|;US`VppWKkZ}C~a;>U>ikv`%N2F;^k!@V`< z_-ZZ?&EtGD=Xr}C>npxk#834RUkI8VUG z;fk|Ba&-kw#uvEjz0hCp6{7c2KjBxp3%|-=_{}2x22}KD)J{LWx47%Q)nD)3qW2Cz z;rF-;zt>-QlkR#l4t95hl4IU7LGx(v9xt0r^AC{5HY{3HS({taumWct0ewQ!9S0hw z`J2#fXB|C2q5xqF0N0NQ=6mmTg2kx?w-iJj~t)Bu}%ufaquT-a=0?8{R%xY#WYxUbf|cmSS6w z`+10nPx5L{(;Or;n`-(a89a#=i0W}Zs`Eheh|aMfrC4R1w2cmdzBp zn`O(yvL&eJ<(NgFd018fl80preKpsM=0kim*LaJs_7&eK;t%%`zs_6yS`qK=*VRII z^XrMC{x~1?n?dvN>n4yq{JK#zyIZzi=qZ+&fs;V=8YQQT(c4kWD;Q1z&BL;7qS@WD zEkaMR45Q={QGcP2`tw2a@Y%T_d02L~Xm+>kOrfV(W(F<=(aUE$#pr8L%gbk1f#zY^ z6{6YQvde^?Vi|n4OVr=uqy8q)JbZQoNUoOAgnv7TUJbubG~ex``A%=~u>Nt8@raL% zhd}eN{sC|CX5a}By{vy;G(Y2``6+Mlu>K8^@ha+hSopG+2-AEKBx?zf(z9mZO%Rif z$NBGDD7FPz^7-$lV$w&b=wZ?aAh~wAX}%AV->T$Yp}Uy;8Hg?>e~w}wlYbDCzePn4 zyT10*`=h(wpZxU(d+1fR(Zf^kpQ6`&aQ-fI7k`8x*To-cDE9Hkfnrx*RP^Y=KHetx z0?DrndkEdd9Lj83)P3H46qu9sfS~0l>6+P_23t+x>Efcy+RMvs$ zVplziee7Bc>{``C28*mMpmdbsf{kW$RG_L^sal@HK8vGSVuDxiQUw~uUCVxo{m^`G%O7?kA?+7@@SX|l6S*8h~~CFnp=B|Z|N&OEaLa`5x);; z9u4c_t$A@&+-dxp1kGcXuLmlQb!#Wo)#Z^=f9Ne6rD9qy-hw7cFh{(1{V??hDe=!gj* zd33}$kUV1F3`_yh#T8Rg?Bj~rV$uw6y(NBn=eX;g>#ui-=&eLW4_B0f{|@u_V%K_9^l)V( zNFF910g|694->kJ$(ulQG5Hu2`y&V-DS+o;q9&YXcQc82iaEfaOlE-sv99;Df&E0%7@8>OkA7AkqBEFxG_`aZd zG^~%e=3c&<2aDzbKAQV`i_i2GKU%~`eZ-Fd&7)z%yfqK?)jUBo=lf{R^%g(ISNt>) zKgCDNxZ+xnJY8`Mh%TJ9kLLc~ z;xm24j}-AEe8dj}&7)yMy)^UEDNn?Y@ex1DS4N@8nCK&80%#s4j`I~?BI1jD#82^+ zQ7SU#c$+cHON4380Lde^&A@yRU1p#KDE1kOi^Zf0Z@mls^e%DNTjj5}LG;$5qDPOc z1j%EVuK>x@6{|pWam8vB`?#V}Ogh|K?>axdN4e`=@2~d+(R(Z^dbr{kkX&6slkth} zdQbA#yIu62>?iy*ci}tyg_M-F&j2XzuExxwE(Uy?n(VDB}D2i0=cMN5gt~YwjVM-Gd=4^pu91 zfrCKw>Wv{{^gz_|3e#-RJY1e7n%ynS5PFJb2-93qKiWtANYFfdb}&dDmJJup?v~{U zJ;gFJkO!id&!&jclTgdcX9b{nSTp=5}gtZ{KnoY}_qd@fPvCX3SXdlfR zyv4(_+eF4mJ~B=K&BOZRyv3V=lR@;d{tVH4nvdpFy~V@&OGU;-J~A!<&BOZhyu_R4 zIUxB(>{&uji3&4t8HipDzg~>K7PY(r=4#Mfqrx<=6wU7Odb!Y3EQ8N(7xlNIo`+v< z_SSx*w{$ab2Z+h-#yib-qS)5ZviAnc+>%G@c@5AnTAMw}wj_7?86+K+>I!GQJ z@hV7uA@Z`&Q#!&7>;}=rRqvwM$5o$;$)BL2hg~0uUiSd`Kj_}6{Ke=6cX zLOl=TKk%0RzPEHU@EM3M!~Js<`waIV#H4S%^?vQA_eXcVKl$qoM)ZmefB(nJ6@Pl0 z^t+!)A&7KwMH-5IT+v!gYJrL#1EU#89s|P+v~kzl)?e>_qPHt5dPGHMkUUJ<3nafu zqNC7L#6p`wRfV@0pKD@P06#jXh;y4Y2KVjsJ1 zpQi`tt@Dhs`uf_!vbtr)M*0Ps0Dj%FJ5L1nqf*ce1|FT)p6`#%Yi9%l!QkWbI`aLA zc^!;^84NzD?oX-v)9U_=x<9M#&#C+K);;jTy#4VrH^IP*d~ao%<~{R_nw8}>6_qwq zO!KaJM%9YC6}dGl>MPgqZ*T_rH#i&D;CHVvo6R%o*RHIj-{w^12cVqRDi6#vDk{sX z>hP<^&->UNO6#l)s z|Dei$RQONo{K;<`G=(=& zcvFR^E4&%w)U|KSGpcJUiVMl3LCd42`I_{%z4R6T{(i}`zu)2hwsrMU+|}>;cJ=#i zUCo`{3cou{KaXvi%}b4jstQ|B^7!b$^kAS9HuxTlB?MhZDu1Y zs$VR&%r0^@dzy>c^OV^Ol-V(5c3hdgSj?WCY<71xd#0z^^Igp@wV92n$nth~%j|`& zW|zB|U9HSssmwk^nO&>QUMprVO*XrM&0gYZc8#mqD{N*bV%{>l-qq{|7qgF4X0KOf zZ%}4$RAwJ9W*?Spc273@P*1auay7frW;T9$&YJ#uT4rx@HTxJBvrmE91}45!ORY7+ z_EKw&aGIJ3cBuR5>VAg0pQ-L=sr%XLevZ1ItM2Ei`}yjA0Z&MjYqypf%klRE=uZ|T zemW1|x1R*})K)I4TH}~$PVn#!C;BVU2wLb|sTy&WYQ)t_={4{@rORs-ex1U1D*Sqd z-=Odt6@HV#Z&vs%3cpq1w<&y=!f#jj9SXlw;dd$gZiU~Y@Ou@0pTh4K=UnRHoQqwZ zbD^Je9#+nI$_mWD(^g=nJ!9c%&jN>Y(w?)Nm-f7J-U}8Ue9^+wUQzT{Ej;wPg@@iy z_*)8pTj9GE{;uMGU+Mdgr7!pa8clQ6hwA>3x_@lln|z|~pQ`(3*1hTH3je}#UXw4? z{VR3b|eK?`Pec z>~HC7(#_Hz2wUZW?$$lnL*09-doOkGO?Rwa`dE1A0Cn%H?h)&r*3XikcA%1fkX0VY zu0k5ob4zE7s;^xYXUj+A4_@7v$|%1syF{mrFZ_i5*cBpy@!dMx5p_ifKg4k zi9s})nvMUk8JIJlC$`|c`Mf<1md>|k=lKd>pzxT&;}#w&0}ks$3oSfQZpA{N!n%hl ztr!h0vSKu}SlySXu~4PzFIDxIsrt)Ry=rw|q3YMD`YYA_5XD!k`07;sdUbD5e5+Lb z)z&?@M%~w{`=Qo7v`*oNsr%uo{0QrwcBC3}jh5WBqtt!9qHo|kje(i-y>@bQ=Nsh> zwY8P_C0~1Ra&J(NSpA~hY87oQt)rd>{2?hSuBokBY%3+>2UB@f#TweRtF43?7{rCNUbL-uxidzB zqPP1aEY{@x{#dR;<02oBHA2P#;xQE(FJ%*?tU$^pO4%eSo2<(MC4jiWf$0Lx&`@xu zK(jQIHX9Jn|7mjsnyaDEJY6qTD$sm^76=s6P%th~nTFC90mYT%c+VrLEBQ(rN@+siDvzx?ZrBA)2%5q^w?`27y*dz132- zMwbQF>axJ0455Dm>!j>3T`zdJKu1^*)&@sf^#C<$D0GwsAxhS3D6oMcvUH;^3mz@d zCV`I8P+&7d;0PRRl|jdGni@P_Q-deyvcQQ9!TR7ys*DEBD8OzRfJR6z(d>u6GEDLm zmn}P}QADRRyd{?jRVG$z*5OQtQ=P&T5woi5mlWsEo}~w*C5mQNWCt@ig&68qR+dvD zvPNfPKgw0Xsji}?uB@Z=gu^bL_efZgr?6?R!lqQNo+<~=IrSWPGBM(?XtV zPex5EnePB(ZH7+=#K|FWhLoKtWoJv-IZ}46l%1!`g6He9;03xYa0wtz7{N;cS!c7C z33R!J0$1pIfh#o>yh>ApR|B%ncdrrZwHAbMyH4uu6zF<^ZV>23fo{@J=w^X#5$INd zZqrb37a+2LLUjvZuTVXWXba2gWZ{Pcc{6YdmDW`)ETDt@u|$>AuExFi==W4rgNR8L zI&+2XmQwKRS(}ggttpE;_Ab=0I`)1*R>wX7$m-Y!0a+dK5Fo1~9v0{kp*|{Qk4f3% zQuc%@BRAX**vk#~60Kt30NqZCQoOZ!4;N<-G1M6)6}K}3cXM%$K5(T{9Jyj1ei{U; zNiP7hn)D(dt4S|Q*(_;j4Ny>iK zWx-!`S@2g4g?`ge+V2AWA<&-!?E%E?O*4*SC=g6D0a?>)K%k&SrENYS9-E;wO${~C zP+C)g(gkWJP;)?*wiXryZ7l(@ytG!D8fp!QETFJ^5*B)e-Lpiit+tI2Gw=+R;fao; z@Hwtnx!6{yM-p$Lcq@ef>)_b2KNDErKNoVS%I*hK>Gv2$q2f? z8$%QbVWD;xsE0s31?nYGZ-M#7xKyP9H7M7(kZO$1+4t&lPH(K=}fV6KK3Z69g&{Xre%q1ez>R zp+HjvnhMBrdXbb(6R23IB~mtBLFDutz#dK?LZnou529jMrw_0g{G2`)RV=5^2V|w% z1%NE4F9u{eeF-4T=~aNN<}H=7Wm2|W%BlrgAyAD#D+M}4pjv_I0I`lxy@JR!vjF3O z!4`}IIJRa`xyvq+){ygvX2o#wt{3C{P*A(^=w1iNYW-n=tchklAgiSt09mcy$YnIT zkCw7c0v)3uvUW9KO#ar9l8lfBDs{D$#sN$^5f!WsIR%hq(y4$flePn5lLDs+v_nI| z(*ap#o*`vtO4(UbcD9tABW34G*?Fpr8gU%p)JANkQrAY9fvrrduBJsm0PExsFIDk~ z^&~~Wd{5;jmt&E%MU~U?fCzeR8`!1@Lk8*nFs%@JQo@FxE&`SJ>VZoDSw6W`pvwfh zT%aoix>BI41iD(FYZOH7KOeAHOD`tcD*V%{9sJc*7}-8%ubpwJB71t^`M(A|JIB0~27;)qDQ4-ofx+Wi7OAkc#XJtWY>0zD$oqXIo9 z(BlF3Bt;R|R^_g0NzE z9gx-XH-!48l)WWoZ%f%bQnp*l-j%ZVr0jhu`;U};AY~s)*+)|Lv6OuxWuHpfXHxdL zlzky(UrO0m0(~viZv^^QsNYH1_fqx)AWqeR9~G72_eQ{8@q0Vb>dICZS1vB7uC@iS z8MxJAqg{vWSg?-YMa3&BD=TK=pM!E6QENP-}tO z2-H@fb^^5*sDnTq1?nWwUIOhcP-lU<2-H=eeFWN9p#22eU!ZORg$3#^P!EB63e-!W z-U9Uz=m3HG3KS8jpFjr+bdW$90%Z!6B~X8XvIQC-&_IC(2{c%sAp#8*C`X`S0u2{v zgg^%i6cuQsK%)d2EzlT&#tM`xP@X{f0*w=Byg(BKDiCO*K$8TTEKs39Qv{kSP?12> z1S%G&M4;&c%@Am&K(hpzEzlf+<_a`Vpi+V63$#F>m_TuX$^=>{P`N-A0#ypMNT9_6 zEfJ_nprryW6KJ_W)dH;$s79cb0v#eytw41G)eF=h&?-w`vOQSjJh77}Kv7%F_p;Z%y&l)%;_td9eIAKwE-k1Q&^M{vy za>1^T&bqd=qM>|QtY+b&hB`bHuBlDI%ga{Q)z_@3%&0D_tFNprt*%>DUb<$;pwi;X z<&`+FE7cV;S5_=EIve{M`x#9;HERr?65bfz65f`1Q|1|&FK1q!`C{hI%-b@5$=s9q zd*;ThH?rQzYJ3uw1lx58ckkJMWqrejmfKpM((?S47qq;n<<6F0xBRB%_bq>D*%&@5 zyaA$)4j&WV96lBzw}!Vt`1bH=;nTxsh0hD0AHE=bVfdo(CE-iMmxr$kUmdv@^N!3rGw;g0JM*E;=Q5v%176O2 zCG*Y94>Ny;8-9Zu_GBKFwLWWO*3ns;vNmTOn{|BF30Ws)ZOPi2wJq!9tW&eLXYI&3 zJ?qS@v$D?4Iw$MAtn;%j$ht7=qO6OvF3Gwy>+-BCvaZUyI_ui3>$0xTx*_YPtedlL z&AKh?_N+Uy?#jA5>)x#UvhL4%AnT#5N3tHvdOYjNtf#V`&Uz;6xvb~2UdVbe>*cIh zvR=)4E$el3##`u)-C6Hubuqdcdo|v_mtnLSjdwv;W>!_)-w-nQ>_JBvqZd_{)o1qa zzcpw!s*+VT%QLGh3<@c$B(tKnvb=s(B?=70Cys!QAkgtIv%G3~uSJWwj5velc~sT$ zkLxU6&SgPdgXWuy92J0YovIaFOu-&B&$f_t>rp+ zsERs+H!@-O8LlZ)|zVYgZLseb&pj^ypJ^f6v2$Mu(P74WfN< zXb?+A>!01>R6_1PD7l5r+gi?2PN#a?Q0K~|dZUfDqq(8V@l-G8bHf-xJz)DM^_268 z)Hod}?kig*fKpF&08y{I*fhS&bt;y6suQT*#U~oZg&#Y8EcH}JP`%6G^>M4522wq^ zID;a%YI$Yt@E&=?ON(l27T1 zimIB@0sXUwmFCt|S2wJvs$W|=Gq-elP0jMU(!vse*@H3%49gtYKYQT7QoJl(I-#bn zes<0fPKxCNGAouZ?-A|@%QEOVs-kMSk+F#K?K59Kcuz`pP0qeLnd)p?R$IQLl!W8| zysA1p*{`g|rx3N7MEAw*?y&wF?BKiugCuj2N)Uo6Hupc zx{)!y1plu!GR9TaPhGflT*C?ou;9G1`ZB;Z|HCOkTOPwaS6}6vB9e`-S-2D$EB=QX zJtv`z%G%l*yyUU6rnY|g%31_Lz0q#meq9$1GNZ?$V+J5vI_%eYe}gdy!A<`<&uoQ^ z*14ZS*Tyt_e}emgd_Bl2OSj4z>-paPx6X*DSvZEQSzQ;NR8?PBn%%#&U`6@zhKfpn znf)^d4Cvn<_tJ*)+WOM+8f3-V`dD>kb@|G*vAWD9Mq4vf+Vg?)F78=$#)y7b%)IEQ zL)xFxL+{jscN^G9l@{3x0cW(AlVQ)S2TbF>* z?^x65J!(`ecXX`(z_Gc7xw+%=b4NE+^dD`kZ(`sf`uUgOWUBE@TCiav>~E_+v?wnx zcS`QK+|iXQDi+ob8KhX!Etb0#%RoEJq`XOalPBaASu6twxUsa4cK-Kc$0wzab!>OAjOacS2i^ zC!h?oW8-_s+o8s-qfNsc(j(A1Cs_#Ank(F8oIo-jB^j+SN|lTeknt^KtXi~Msb7wR zm$VSo?F_{y5|EXSOAeU!est?-BNQ0e!+fEK*_!^4QG%~7=HxtyIPY$TOFPUX3C_2{ z+1bIlGKq5waTd0~aeC*b_T;s#>uTjVNMV8KRwOXMlUwiVoSDk z8!>k1j!W;>hS9}pqhfrB80%J~I_E$*=VW5+oP|pWvr->oOe5!P>t(in(aC7n*%z#* z5Nl?CTy}x=0Ag)Itk-}w9Y5y0s!ppcw|R$@o=Tjb55VO@tR;Inl!hIg3HK1+cH(I=Hhl@MY;c`MTqh64Wo2i>=tx{4GYl^J3k(S(?ad=)JBaP0 zp}0KS#ct%eXkLYb)86^Sc{*|4I}DfKyV^N#2j?2*EZ3e%SegmOGl=nw5xDf{M3uI^*De$38h_YN_h zO^j#Gz-2(hF!o`m1`u$>_zp9!NKrT(eCH5f&MaJ7^fQdER@W;&`qfej)YK3s&U1-# zpV_!v0?vIMoUh?y^HqydMt?5Y&Lg&>g}8i%C{K*x+xwcW>C<~*v$v2K&nL!r%5izH zzn$?RFz&H4+Pi`nFCfMh*yA*wlWk{w7L2dqo8DE6l6!)J_AQ@D^QRnNY4wbC&j#(P;?ow^*aHV zqsKZFeQM{iJA)c^IdR>By+PxGT>Hp74$1-tk~5Std!G^G6~wq@3oa+;*%>bdXmh6YQL1>ue{d^h7E6t|7kPPQxX=z%W`F>ZT-Om-?`v>50@)=oAsu><*?NbK%kEC%+ev(PU5m>sB$q^9A-?ku zLX4^8AT6r|)Ahu3!F9Mi2c~w^vY@#G9Lw=Gl~G??wxVu%S$!p*;#AQom9f4l76Pc9 zySHKdc@O~Oc3j?^i>3Yq@=72w$E*Qsp!F(;fRfts0(wskk7t7rY&4FBfITGO0TQrq zo?#Sg0f9rnYPLSgAt0}=K2<|B*xIt5q#gGqF0*i+(rBh@V;bKu zTAz;RTsCJG7FJf*)UI{-VgvENbs%;@6AuCOLR01sMdr*MI43ZFj%k@vx7jI3L`+13 zHj;?GwGgplBhD5`KrnC=j5kTY+4>v@^SGi!J5;Amg^;63$c?KYWcVh-XscUcw!X;0 zO~06s;8%Va5B^QWA6pInBf-B{g8ym<|J0S0h%I`5$_fXv{}^Ijx(2MzgSGK`gIkbJ zkrROZhU{ZTbGRq{{Saji<@N&Tl?76Jh`$Y={-Dc9#53g!99=F*rma>6C z?(Tpk<|7hg9UWt+1VcvHXxtBs#}Z>}Xm6Z}+}~?7xz}j@HPvodS%K(^t!!8rsRL)*u;aY3Lj21P2;ikdOIxniR;NN;983* zqwf+ZGt;KdHG7qrz01r#W#&U=W^4Qw05LDF#L%!eHVq~jjXNOb1QPSBg)$NiUf`2;&nCK@5cgtFR@TI<&B$ zs3caLKR%W{&}e)eX@qHQKzp8fin9mLvN3%F!j}0Z1!H4l$CTv9ipR{xyrw0#!`|-1 zvR>nhhYX5MnOag5Ls-NZo1SZI#6~dGwz0d>cp#R$fo8j7>7lsUG;XHH&1P}4W!#(; zHz&usH;*F&Z=5%MP7&I_3WH1QACLDirWcmi#n$8uK@WY2PQ$+z#>kYi zbR)z*ESQp)KRZ@DEYINAeA)F~$-~l${&9rU!G^oCwhmrzgAit~um7tm>Bfcgp(3vUfjVXClzeQD zwSMZg8Pm~|_0@F)2lOu=G6<*RjX&!So!~`EHy+cznp!wxT6LApOJ>(}W0KW-IW`w9 zMN^MX45<8)0^5LUN<{4kj0PH`;)g3i+>Zt37H8YzW+n9l``c zttjN5??gv1>Ba-f5=5RPg!fQBJCP6upt~d?bO!Ba74!L%?NMILF{e zO%_EuS|hS1fqtefHz75}%9hvL`u}-kr@1x>ux4PkO~Oh@xJ@LKl+@NH3HTZUB03m~ zhuO!=6!6Zs_1sWf&+P}=Y#o(6g0lzYq?)%CgZN}N&r0lL?TNi3WZYo0Z7woEl69Z9 zY+<}KXFTSwyjVTFd5+bY>Be3vL=n0YX@enesLiH4l~ru+s)0TG*s6?8tx|$21-2@f z5S)qWC{(zK)z7uMUJQ5v2JBr%X^p2R38;Ys7FN|$NO3M5Gd4F*&0(Bb$IQk$iN77h zSB8x(bsUX_ux+e{BFr8&J3;v((JvDU>_aLG;dgrH24pS>hszp}w$hFJ=s8Jj=J+ww zC*&7TD=NX;>WLZdm-gr+=?9ttQ~Kd?L`nNYC1H=9YxVZBr0$y7Io)WLT+Qjdd{o(N z4f#Tv6J(y-7iNCN?M=)$u8yIp?DB-U2f_Yve4`e1LhZT=w{F-GGk#O94%2-1vm61H{|I25eV%^ z4ZmA0i*{=FQL8X&#DOnC;xV@AF$du%`<`YHJBSus*`DjIDlM2+voJ{np9I0#nwX!9 zSyxCiA+}PlFM}k#TcW+#DS@$HdLCaWi0yrWR%oNi?w= zarMBii&jL_v@#fCQ%1YN8Ov5&_g&~R?pM$jzV?K3fmzy)^DK@az*1Ptl1t3!yU#A)M)HG zJ*M*Hc+<`ag_@9a7V!L$ZcItC75ffp3niH&tod-v%-L9n7UbsIX2td(ch1N{sOxK8+ zHrf%{&ib@+6Env{-cJcfSu=_wD`%k>R%t8I$bo334BfN9-Y>zPrzWK2RoFtfduwvw zW)E4Y*Pz)$to?k#&9-Q5VSF}+j;LbQD=Mqet|my{+`(OJ?ZUXSwJHl{jki&0INDo1 zAM}xl$ihUYcKb;^vlIiw+Z7sz9o;Wg~qbG5AchJ(QH>}+YwMu9iptVVKhMqoc8pmT{x3})g;_Phu z*gY8BFKb$EvAvgnL*AL8MgyI9Svh)tN+_*qCT+Vr*2eYN<$<{QVBCBtZay40ABmff z#?8m#=Hs-QTQV1ZM&^~+8G%(&K-daG} z&ybFU*0&(Wk5zQX8h5 zyvn+AV-uaeHSWavi+XPfD$!|L7wuZ?nC$sxBxt83!WKitG3`8okZo-xN8|@-A?3Ip zcBj$SHK{k|!fQ9$j~DWiju$>_-@+KxnLb6O=Je#rWN*7rD=FAIVk$(=(+xpS+Vepp z98qF(x?6U1J(2d#jt6K}j$QR+w7p3p7_B4f)aH*wFlHsHVRECRk)$!V7?o~h_o^L$ zc=&lV=LD63r{^YOhL_}3=u}!X8G_1t0JdYb^4WSVBqo@WZTwC3QMA zZI0t~>Smm9pOnbq)*f9pNo~P@j;$qgoN@gUnsWRi58E>^rU5DF1=W)xnxGQ{ll5Pw1`<2&2pAl=aHXA3I|_ zJvOmMoAY^F&$!tuZuX9wed6W;akFpSjKs};l;{6UEUWVD%PKm{`Yn+G^wS?(-wcFr z&mUboN-u8DOvC|CDH30FD!D@mojPt@2|7?tEDr>2e-!{2^zO&F1@Pch7Zg9t6qqkG40TN@TbO03Ba7PmBX=IgvC2j74W1sACfDn`H~~BJkg> z`KK1*;Z+jzk6`YsE8rANFL#ov6`|Tr8RxXLPpa@SM*1-}IXq%*5p@p)9K&r@+Y?Da zm%_waZ9ZjC3?3Pz^sKRsCXStKqYMJ2I}5~W0pn2QjYf|jKxs0^>Y~0hKcC(KGkB-n zv5xP>%=csF2Ql-*nE7$c{4{2M7Bjz$nP11uZ(?SfxY;gl-VrzNjGK4G&Aa2~J#q8i zxOrdPyq`wYtVB=dVn|3&(xc6c#E7ycA?Go3C3c0qc?D6@un>J+P_bq*UfHR$j7)4V zAn8PLbWt9Xv3+iM2yWhKjR#H&loJvoA`i^lY|OOywDrMbVBTA~%P@Y7Ytz(NFmDZOqnQ#Mbu15r4mytF37f;@9q&0oa>fs=22Yj!l_s-tH2b zH^(Tc#Z;LJ%muIVNX zH3pQBmkOqo#PX-)jm6YzG&aXVh*STYY3W9qwz#lJ7G*X^M`8Elti)O>$hf3k-Co*k zJlnP}k4J#k-nPmrrlp`9+w{eVUMOo$Jz?s_n&V+ny3spf9+DXbfPM2dAIAO6Q&&D| z5Zm@PLND%v4^?YdEU%>BYsb*+9cYpJ#y?zYeQM}c;)R*3YP5;#9Y;S^oL zddQHvhTViMVUaaQ=|%-Y?I~?-P$!tDCPd6qr#DH%;z=kvf!$8|)qXsF6}&fwyr<8d zDB}dImv&-w=u9u|{3m996f-}GnP0@ruVUtRc=IW4wx#)Qi8$Uqh7;>gZE;dJw6ymo z9e_)3_JGfJIyWqNj)mdJcpmzuEM3OVj?ttkGXgC$-d91KO}nwwN4J!Xr>YRdk&*QB z3Y4$4*@d+{9S(?PTR>lu@HAeFLHH#3`F!|!Im@PzXZQ2*;2vv}j(z}HgwIAd6kER3 zE^};6(~VzLV8U5qGVLk%N=z*Jd3o|Ca0+&8=dxAQCL8}<;D2CV;nckR7@i#zOt+q! z@>r(0{#o3NvuzyJi&WFR9ftPz?PNdk1x!hGM#p6t~F`F(8L~#+1d7Bq&?O?2`BKRY4bn{JaCWY0e=1^ zE_fS!pV|`0Ap6Fn4T$F^mZBweFpv~5FJn2{%%$}%k4jvdMLU3flk84XF&(yFXf2|U zt{tx`(xP{+t$*~xpybqgGWsajR*zSfHutOp{bU`N$oY=#%dJpytUX2ahvOwjv;g&U zPWrhew$P&DLALIK<&HPpCW1aNiH=2yBo}&jZLTUsmI31dddA@OUZvF<=TXR6ar5lB zc~0CsH*TI6H_wlo7sSmAq z8Z8Ji3EV~KzONDkT5kYteRu%+aFSC3ZL~x}86-^90ifUMNgmPbA!L=66zEhav3+h1 z?zUD&#h{Qpmxbc74x!eGd9vI?A-5;zGjGScCbB6|u%AtVtnzFvpMgEXA+BMf-@@l- z^-Hl+3j}w^0(c)BFN3EW-E7{nHZS6=!BG2%PVC4_(%=t4_=NKkJ+PBvJc~8%)iIop zj3sH~15j?3h{Rj2_F4Z6r1`gHniyN;T+Ros$ zANHp%A0c?HQ1O0Rk8uT)@i|-K&ETJ`bvJENq^)~F_X+yoI%y^HAXXwVn_FR;J^eO- z^*a_xhpr-#-Xs~RTVuT#BmOH#V~+7(`8tnK63?agrEOvhq~k!F-Lckb&KC`F>Ti91 z;r5E*iPjLnNrht&bcZb`DO-|1_t42G5VAcVX<@XUTbNt4WNjUS+c3Ig=iI{hhz^9T zPhQ~a>#fs{7RHBe#dwx#^JX#a_9R9RfY*Mvz1+v|QVErOdW!ZbWfM$u;?&zfT(9Rc z5TqwAFhbAbtJ9?ScC0T~<-Hwx2kBYf`>&Bh7)(WS_}miGzl#m)M-*$_8Z#m&`mb4}b_8#fQ7i6E0Ff<$yUK1ygt zRws5y(m$DK(Ms+gTHx3h8?+DK#v!4$Y8XedXzBoBe`dp04Z8s8)~O(zn8>2?^xBq0 zA3}yMPjp(rDqE+~Yt1_(hv9_Kadi3&l2{+5)vh!jzOPnkStnwCn`ap%;?V9`5U+~p zT>QT7Kb%-YhNBW9bwj&iTpUB0F06$`-6BFTVZr?Elgd(O_5H4>@BL?b7H+Iv{bYJ|Deb_b5KS8Jlt%^D8=Zge`fXJ^gLj zV;W34aRIhRv8glji;D|z3Q}FR#@4?J$I@{qe*G@K@UO zV=ADJb|gX3OVpb+FFD)Jd<}>jRT8#k7CQ3zm^+moTDd>fqCs$kO|D(+MWF50H0vWG ziL^8f);nlni05T)Yrub+D)8)xE#<|oMBh+Y5OUerrM}tZx*Wa?+1A9#Nck@skklkC&W zf56pEQ}PPzkEUp6ezzKy^wya;<}DB|(c#9=8Em8DEyUR$_Nk7NyhIZ9_~b;6C@zfU z=3!XNoD(!c9b)wN#PL&D_K!{VJGG@~(KdW+idSrG@k%=pQPB^?H`#1{!0FmIO=%y9 z=^jM>-rV||TlmouJ;S&4BYrk{4SbBB@`{z0V~~HK2l;KSR%e|`#w+79nhvd3T?;60i-2EL>(63G`o>u21PpnFYOuVOsPAC#Eac>A{ko}@$Q zh|P~k3yxPZM}d8VZ4qUSwZua{dWR5J{*&ceBliq)i2aq2^PuNarDuBXEF7H5$GIMd zNwkhkG|0A$OEs?ZtI+Q3PM{1F+lkG(I|`&UV!vjAPbT1&@p zp|2!mq@NA>=h|D1#aD7vy^LlbnW%%Q+6o$5Slx;$*Cjn!a;`u=!lR`Vv=taj1MKma@%dw1)5 zY9Z2O@(WA1z8r8rrtXDWmvb#z9ASLQZ1@N$SILUIgx-m?wd;L+dfJP&i`6xCLk6#* zPqh!yr;goR%kiO?wVI+cL)oZN`e>>RAyp7aEaj*_0Td3}~+Kahs* zzED#O{~vYl0VhR~zK>50D+7XxnItUi?f_ydNiq@^R`SB`l9BBuNzNdG;wV8df*@i* zMFkNsp`xRrm`+bU&m2$1oOAY6{?GeXSLm6Z9oW13{yu-SrnkG^e(Qaodh4xRJ&4u+(tIBxJ~f#tXr^KKp=@(z4KOJr!(*gs`za z$;IIEEN2aGJk}ZWMI`5boR5~$LDol}&C;FZhNv!ILMJ)rY@A$_O0Ew~%Hd5tMWB5d zwACWd$s~E9l1`JlB`0u1PcmWsydR$L43=rE`L=r%pQB7ar8Gs^Oy2|=L1z6CXb4z# z)&`A$Nt`fM;IOs}}X7IJWU{Y=80l+yM{GjAr08Pl?Fg44J1Xtaczj?lJ{} z*0x)Met|CNc>yNjwdVcc^1Px09>danRW;yIuNB%oXfII9XE>Gl_f^w}+BWTMwbT6U zOw`NEtk#XGn-8PWsDJp|?ylFW&@%nB*4OJ8q+VHZ^DceRD??IcR$)Tn*M*6C&x<*8 z;F96%wOL(-h*_#^BI5(w0xw6asuguWtPO>M{>LxOQty{CTOLW^Pz#_%552550o4$Y zM>h&aA%4CskL`s?*sD||xoFFkJdAcsTmL8$%zwg5o~*oN^RUP0uUfr`1y&D&rU7qf z#V83ItmhE3UBv_zHa(4)@8nn~IzSrTS`aGF>Im?Hd7R>=ItleN#$h2EClp-LHw(!e z$sEjN606luQ9oI)p~0wqc3tRHcNprU z2@7Zjterynn6zin$VOc_Xt9!RlB?cIa284SR;qD_#OAAgHd$G%!FpEEX`zHY`yykbb4F8TUcUu;-gUMU7g{Wn+U85$$=j@g|f0eZ;LGN zZ@fmN&A51 zs6{n0^{I5a*Fk&BbKtG2n&Fl8%DAZsOznj9e%o_UXPDz8Hlz+LK+M@`G7Dzc>gFe_>RqJ|pbbo)QGcX0_O zgzxnSM`T6?_ad}*MH^R~?25LoXy=OduINAu<7%5im!XVgSe{)7xvJZ)$^xuA+R&o{ zGD};qNY+B!S!7$Z$2`*x^Vd1MF!~tk3n)V`wk(Mc7tpqJ7-Apc_fc5vLD#*Acu-+Y zhoFjlUL#gbU;(X))Tgt~OvRP#~#jvhe6o8E$j<-ADdGc}NO zqV*P8f?YB8#CwmZP5q_#zWC&clW~kE4ic7gDp=W8K`fRj`@=HByB7`~(x;?X`Jj?s zMSUPyRW*d&zA?_CU|=v|2KBX<8ib^KE9SjsVB{Ew=_6$_bNs`+ym3*~IZqpsS%RA3 zR_07@83kLjeim;>33J)$rYT*GdK1LeSNTyo$R0SSW?NUwj?|htOPe!LHU}DaObrz6 zj}OJ`g5{y@#9EkKJpNHOr~*s)Xh{8Km0IzD^nOxJ^pi#zKhOuoRJ(v90N%pdT(!}* zO8gIQ-*e*rHZQeKJ=B(u19dISEO;4~Hl{dY*DHwpT2Lvd z+R|^)qOi3}S>vrOWS;@DJyUW##iyNx3{P0w!itc>x2oSr%SpDVwEcQoC;tp0k5`ds zzu6wI7;%mf&1~Vcgqwg}AMLmygfB^ykM&@UTuK_McF@N@^nOte1)bVE?WKJTvPaQ} z;rW@C0P17|d#vP6ptIU?KD1gy`yLvzNhs}*UnmM%^Ua7m!OCfJ0BC~hyzYVcr*(IP zcfaXb2&xOtw)omB%5Fg1+q!{(d8lesys$25Qrid25A)-IgVx;Uoqml66tjN}OhpGW0j|nh_IGXPXh;3oziJC=7 zn{AkcjQJbOjl{uU3r>rYzOWLf6Hj%nP!DxIAJf*Jif=9#-|m()$VJrnS{yQwA7m;; zgIb5zPo&UlroqdBhVt!*xk|;*$hQ_UiI_``n#%Gl%YPF34KhxMC;q6Nqdid!EIv|3 zf-akFBnP9;8mQvf`)dT|;Dfa=nF)oUoqfx-HJq1H^u(K~%Yx2`Sm^^w3gIOGZ0SmsTi;ON$^ zL$?m}QMqW9YPpRfdDS8@gCy_Wuwd*87{^=r3$5&GcoD=K8;rIK=|V&wVny=;9BmwV zh|RH+mLp~<&a*Ql_>hf&X0|ho#uM__$l{6R%H&^lM}!u8yu$CJLmKMeFc2&1M$QhgSLfilq7hGjC z2T^Bo$`FbAsaoU>h#AT;rDe7%^YQ$3#jG%}isnzqc%ANdV&YXc!NW#&updP(!s9cL zhZ#HZoA!a(oJ(OORSb#RU}qU}Cs6cfVFTmjQz7eg3wFOnrt_Hm{syHBB5lxiBW|BH zKAzUgYKQjyMotrN+8x~o0mB@>RUaIzHHRsrtX$r059SZ%(=ILTe!^hB(7lY{zOW9E zVv){3+lyWa1&%UJ7qxyir2zIv>t%z%R!tzLP(2TPZ?b?241xU}32nC{;X`zpcpi~o zuI?TnmIW7xzK;MZ0%uw3JvGOLYs3RA=lY#CKF8 zp)lB0Y&qhlt2kJFU;He&)j*24^$_XsTe4K^0@@!D<%*r%g;|1#Rwhez(=oNPJO!D0tfdSOY-$J{a5*Qi za&7S7z!cNH=m^YJ>C;q!mh3XT+SynhZw^T@sCh8EZ`mw(m5_dwT>X5_6palXvko~k z)h|`)honkR6I^5{4*vj3fT26h^(g~(S(2j zYP0T!xI!Hln8zgB`;t}g`#h!e&4Tm|na6_eex`%}2(*9RK+HAPND6ItPr>hH%oBCw z*_aH6*WplmWdi8MrM-VJGVe_#e_`Orj(teIM@sIcn$99*-x$A>%^RYr@l{oIuGgb; z-AJX*!|Jl`x4RA_F!XVUUsq%pbFoK6ti#}NOb4Te^_Zc!Qa|wtr5eo?=uG<@F;}y} z`_tYKT6b5d^EuxVI&7)zt#xunmPcqjW4br19PKr9y5`acesg#>cLV^qjF*!YSjCF! zdQ>dBV0D5aulF?%+c6wawWXaAa{Oqlh4f_P!wzjJyjmdDQa;3xTk{lg>_$8dFRbug zR$y^;T|}%gfT&iuor!;k2Z>m`d(plrttf35xL#!hY~1buJ`u^eHDm}@f3$3_2DJc9 zwSRF_ZKxUHpqV&5!a?ceSk+_dDIA@nIah{E#p@6J=%fZ9skb?)Hb!sXeWq3a(_p}7 zV^whRz_OC!{xoGQeNb@!(2=e<$`wbu;uu#P>x$a0sN;&duBhjV`mQ+66%Aa`&=t9^ zXyl590PRKLe` zmIk-ZbVZA&fhiX9ID-`TI27gLJKG1RZPO2R9raN(ud3K71sil+eofmYP;_&Z)-=AR zb?ybtX0T-B7wka@n*SK4-r;TX`lYiFb*0HZ)kw25@C9VxrRr_JIi%me8}B!ePLsz{ zbfww_5uPblR14{1)d+F*O`@0_mHsCM>M|re(;`D3GthXy8S!6p+WNqzQ0&QmFVcP} z;E8e(^^7$d1h=h6g9ajQm+^owl@$5DhW~5Czl7V3fBP=j4hoM_HS`0MY}9l!5G{pBWU?`pR!VXJ9$2R>7~0I(5(^qFhdMRDGh{l!b|$R#8}ij7?|U z<5>Tf@tkhmgrFUA@5t7QWtb?9x}GK^n@E31&2H_Ai}3srl{RgC*C~IDn6dl@jK#M9 za}m*+BZ>y0Ue&Bh@VrQ|;;n<4*HoC-Sv+MhhfjzmKZ<|R$hoQ2Ui-25xEF6C4Yp`P zSLh$2hI7L9R6e9c=?90YCHVkCo@g1Z9?MSg-xE>zm$Bt>qn(?Wy3t-0<6dp|Ymn6c zCS%4?(j%3SJ?u^J?E%;Ilz0zn=gZy#;KG&=MP689D<#l?yHZ7w&#)AJ2)ydF!fGEZ zFqGia>O$t$+f>2erfcA8NNA4A_`rDL8sykK-jZe-AAw`ZC#%;2lbb8Su$2<8S75&+ zjpdgclPwu$nJhK1JuA*06{lJt&&tNsgEB_J?OaVARXS!}+EZ{!KJ?6-XkY@1Dl)*5p{x!!gvZ$)CNBo zaW^ZZ@L86?(&=|$+M}zYUsFV+E<#H-= z`=(B&E3ADBK01bv)XbXZjhjH5BT<0pyJKwfC6@SljaEw0zW^%anx{8&Hd(E|xqB4GB{P4I0^?yS@8PKf z`>ts;eTo$sICS+=q;^BaRvXgo-~&=smIQ3KMr37e^}RR({UGIME;692;f)l?9|z<& zC^^Z2+5NRAp~MEO(GzGP(A?x)!yj8wA$|H#H7KiC#(+cbCDdn&E|E9o^T zec?u;I=rIYGfYvS8+wNWEMG;-lu*s;>Nf}M7leqJI>L1uWL>O)Kx+p!rS0Z=*!DXP zt=r@sd&jBi_UYQ`+6C?+r1&n!=rxnQLp7&`wyl^DBfWNGlRU@5po!Dsblnoa1o6`> zo#cV2sT$n`Pu!Yq`hXm9UouR80fDi$z$pD6zIMEdX+PF|(_)v=0eM4vmg|rOh0Hp* zOnod~KUg>PLZPH(7Z>xZ)KIl^V+Uf6wbE8cyIN*iTqoy(kntkF1z|>}X!FKXvZo(VZ`#DZJ4ysBPN>CQMsGq@S()!ivUFv8eYylIcpz>^A3_cwTJTBJicbIBkm) z5HGBF{>r0{B|t9VSbqezCH%3jSZgA7g^A_vrjDe>P=p048dQpURo67M?sEt)GNVs~ zz}?aMYy7JgX=~-P+NhFRDrTTml#z+Uc*)5s6HhsYFsfY+Ivpu4rz2d>(WdUE21Y2P z-5^pk(_vN(Uc1uvFm821n$&5d_v2AAhFBm|CfI`!H1B!3KRoY$=5)Fmoc|3?)EUNJ zyBFF9OH)(>7-XJ7))-I2^Ig)QdJdt!h90S-VUhfFrBWao4ZWUJddclbR)O0Gb;|A8 z1e!L}vk6yVHsKu06T=#{C%y?a=UVtQI*>Kwz?(u>^mIipR}{J8R9EzNMITr6rBT+1 z5=NcZN{8;H2;CmbtFGYXFmQjUN9hn39QG5Os!iE<^(&@o*I2^R8D(19U3k4Gqsu)5 zjqW%+Z*K&`h;yhvoCTO#>a7NP+C^_ScnjMNHpxsv^TWy`@`eKf{Aql^f_OPN_f%4s z1eVB6#=B=*@9GuJ*6a7+_35@r!9cVRq`{EEDHSs1udb1)V4u#Y&{zmsVH%ee$lZ2S zV;xx6;Us<~%pNiwfP^#JSpcdm>>=4(AzHb@MRvY*W-deA7yOp?9igS3I!`M#cQhlk zdN(7cr&Cy3&L@%52ofz>=OZ|B;L|=EKA=#2a2#LNR%0WdhCRmMJtx6=rxQ2<3ADEI zPWeD9>!u>>7Fi^EmM5hw>;zr8MW=@80w+~o0ivTVBDHtIHnjnu`KO|h8}Tf0Vi=Pv zP=E&x;UhmYx~yyfPQYwYh%hd#sB+0SUGv(Jq2 z6KLZsRZ935jVuYw;;0HBC#O2Ct?7iuodDy5CBAgDhQ_xUp8sTgpX$cg>N==iI#c!H z@0RJU*hh2tGb=M81inzdC3AbjY%Hbr#)rA&gC;5f(f3oUVN$)OWe2SjzWl2HCAbv6GSB=IRv;`6Ao#)TH&U9MPD-DEEaxgU{jR3v}d zOs6{nQ41Jnzx$*)UXB=7y@W`#==5955qGuD_CYvQGtjes32mWPCX+JhG6gl%aTZ)8 zfrVCUe8ya#b&gNh`)8f6i01Ij?_(&PS97E6LeqYcd#7~+h6eu5knWkPD^rEmKtwGg zp=yz)l)&EDUz((<4&AE%M>7mlEPSYMh`LRiQvynS#d)XQq1_Y6um*xgj~t6DP^Z?q z=1Su!#g-+iB4)Xa^HIWP_zk#>>#L?&wi7tsU=0$u&LqIw%=#6Lj1DGK)uMgdH_S$kUP_YNM>~g{^BPu@Wg3NzMxNl$DVWX!FFctr zH?opH&9t{VJRjWJEXbLg_!|E2Ww-bhSG?+q*Ie*FT=A_dzH`O*uK2+f zKf2;4SN!aXUtIC4D}Hmu@2>c_EBiPjJWtlsOgDAJaMQe4)a7UPaN)vBRp}WCyw&O(VjTQ6UTa@wkPU%qOK?Ed7{22 zj`KtVPc-yIt|uCKqOm9PJki7xO+C@f6UTd^xhGEWgyV@5J#msJT6m(RCt7);wI|wm z;$%;>^+Y>QwD&{@PjvJ|Cr@Et-;)$-F=;n#;p6KC;LQnMcL@!SidE!)0^!7v_ zPxSRfKTq`c!~jnW^hB{I26WMN>4DrNJPYmj}>jV?8m>6XQKG!4nfbak?iad1A6Brg&niC#HE~x+i9MVx}i%d1AIF=6GVR zC+2x#z9$xV;tWqL^u(E-SmcSto;b@BXM19aC(iLi!V~9u;yh0*^~5qyEce6;Pn_?G zm7ZATi3>b&p(if##KoSt#1of#VznpMc;Yfoto6h?Ph9Sa^`5xG6B|5nr6;cP#MPd- z#uFPoajhq=^ThR@*yM>DJaMBZZt}!tPi*nT&7RomiCa9e%@f-_vBML$dg3-u-0q1x zJaMNdc6#D2Pu%T^dpxnr6Zd-JK2Ib)ala=X@Wg|j*zJjjJn^t6_ITnEPdw_0$2{>k ztR*teFN*%ce_a@V!Vzs<)W+`#W>ZgZHLun#b0k&;`A$19+*KVdv}cF;$8eN;L zg9|KZt?qhu%H+80Zu~un`Oq2`MTc5fsMQg7f$@p*{I}HR#iQsPT~-@kbmy%Cv*1W- zL>{g1ljNfu$071owo?f8U{X&@a!j_O5!JMp_p!$Ml&t7XkWt}hBs^U~L0 zEEm2LP0Fb0o$Iw`G`|(vV5bgCPfJ!nXAicGM0Ba?&kQT+Q`T!h_tJh=kA?>FemA~f zR$A#ZvaL{awcx%=2Awyu6#hsFS`4}=L1UzKO#*UdMtTAzXw#f*Wu$8V+m+CC)NnUj zt*7APjd!ukaGPI6?dMKnyVl2UFQr;wfEr1v?DX3aIzyj@YHKaM12Zp2Bk}@e&w(M* zTVO%`vHXI*VrY`gAq$#-F?(vke=b)cV|q_FE6LJlT3Jm6&mPR8rsYx#KwdUw+13L9 zZ?Y9H2VO0LO(5uHGD>b3wBpZ34(()xC~3QM_yUq%VX>Agwo=-J4}pCng(Pjh(lF9& z@)pH7u+R4iVyxbQZPNsyer-D6T@wz|NN-wfkIh&G9oqz2V05#Cyp9@UyQL59hn9lB(A;RglcD9qf z2$82*+EIpBE{b*rZL-Qq$||Qf(939J%Opo|(#Djg)y~-wPpcH>p22%~^eTcjs1rWP zrJmj+3NhN~9Z>T(Y*Hnno$RE0jX<5`0z`n}K>fH&U zsF6>3->1U>Ay3(c5>m(SFLpjW7_QBcRvaH?a&Z5TDhy4fE4Vc=y2(XAma8d;TE_(9 z<@{V~#Xb;ppZJ}6tL(raB3Gt%R)V$`GDj)9E{BpKolS;RZEtxj{d`BP9;p!-S~hR` zTnz4vYug4}#d&cGjqKnbW`XRI6|A8aqqN6t5JSPCMXY@+oAmvjc3tIYy;NyWXGct) zMGLO_tA=4D{UHw5AHk@-_YsIY*GfNZ32GAUnPG&1Kb2y)1W=9h_}IvTW8IpqgBgPuHKyX3?u1Ehr;AizGdh*Fi9zK8D=N>5O-66A42&l200(W2mUSu(lej@F6ku16I_ z&NODyy$~6q?c^jxZc-Uy*Vuay(alm87}`ySp@?p%GR4|3WL00okTp?e9XR}}5#FqA zG3MQ^+NNnbbB4v2EBw?7ZwqlYL~3Rum8>JY>xkM5yz*(7riV4ns_IuxqgX0nYhy@T zrw`)@ULdB8g(T{462nwqdhuQcfi6)7Mb-w0wIjX@44zO7XeKq#DEt$zmdRwx?5w8N z>v;8+HEEFISgyhACB{}VA8|2GxP(eVMt)3q6*3ha_BTWI!%uhUSN_i2a1 zr|oDJ=}_4t4Rrc6I}5#jKyR;pJ#YfeL3q27NnEZWw_Y8Al<(slBWUeeQW}8D52TyE zUvV_r2KTGk3)Ml7<{U-MfyezJo+lyxaHcldOSk(V1psS{KSAoCxF zMiuQ8t8W8PCa`AYAnj62bG#SG(Z7@f(CAo;BaF_nGn>M>CHb_}5wecSdeXu5ZVYW!^td5RfCW)D>D z{HM9fKE@x)qn`D`1?rh>lQ`g1R0{{%!*TzJK{Myh8#D(aq*z-^6~^_d`B9UT;&u62 zmFD2}0r$GP+uP)$;B+M~LBSjmnB;MHXsgLGxc?NZ+Y74`?5*hN-B1^F0ut+K>TtUT zr{$3k23NSGjHmv1L^SfCUy@BhK7tCe{4j4cav2S3+8ZnaBe~zOn$#B3+8>Hkf3(Y~ z@Ay*d;1i(R9*JJd)@Vj+2JeEwv#MxtO`{FrJ4Bu4&kOMJoK@8n-Q`$VG|Rxyy%6<~ zZpyR(@;gV^`FFX>zs<^20>0vLq*F^}4390OwcC3`{E5b#u#(EEU8(TYw+H#@G!8w; zPko3&UF}iH*VP_HjWY@B1p!u3z8VRy)HU~@LaX8?*Wg)Y79{}8b&)*-(QmN6ScMa6 zOk^=vo8(i6NMAzIvzYjFgIS001 z(U#Na6k}Rql2%5l){RC+dii=oqO#+hoP)`Zi;toa<7niH1MAR-4R+W)_fVL@dRj zbVI|pYdabk@rPxojIbZt!1;=72{Z@p1#+YHFhF1mATS=^gWsml$7qxAQ0R{5rJU%y z;!HDm%~8s2=Z8M87P(u&Ma>esHT4Emi&3OMfnxW|$OEoptCx|q)JS)6jzQ!`gNYn@ zw~X=?80GDDs&@CA#+b*OGTz6tiZ~hOISMno3wbRd8>%5I9i;3rWfAH+t8Ea{Z+I5% zgPWK=ps*Wgk0ISQ98omL?iG~c`4Xe3|MiIU(@J+i;X{pk*2}t545bL`85YSiu=KP~ zN)xYzf-QLF?hpu)RFVfyA$lFioJQ3NN_fZu&rA#YqLE!V1+=ux09lI)_H4L*thVY- z)3V;UIrGXV&m3DmasG^P`dE;9uGD5|xkM*VW07i2BQ5p_-JbEzh=q>^8d| z?MWLh%Y@Gef$nf zaB1pb=+n-(UAxH8kinhOi~2_}&+#6vH_`e|ov*v+WZCMTio74E^8U{Bhxp>2UwdP&%*r`h&;JGwU@k;0z&mU{ zkWH^>u96;Fp6ZDL(8kpx?#9f+{zw z_>jkR6$3qv5;BRj0ent0ZbHwzrzAHK9n=MZTD@m*Q}b=8)Mu#d^jlCmL)XHRXQOGG zKUaQy5VkU7{`9$#^QuO2a$*S)NerZxOl)s?)i2A%_vPZxav|_(N>>~~2HipNEuoJ< zX|7|S;|ID|6*$_6Mp&-2s!eJD>uQr~xAiGCRH|Ei4pmh1bXaWjuU#WDruG@*CVAXz zl56gJm{vMc)NOPeau^xUE)=7+ljpJG(VUv(>DBkhI#`*dmwsBw%|<@mXoRM(i%cGC z#lHoC%Pbyh0b<&$;YDEdjYci_ojsaBIKs5d_RH@Y3lH@GU7&ioZZV{tZW7iMO`mMp zM>Dxc8o^AOcBu+Y{}ib74m$;OeKX7_(Rkr8hI{4KkA$Y)9h}?SW<;~?Y2B?^C|q%? zETi}YM%X)p%W9LiYUz7Q5q%07yNorJ{SRHw-H6whtB62X@Fv7uWEYdx_AV#t>`vkL zNFdu0uOg1VPqb^SI>_uXvJqs=JkY1^uZuEGgXp46u6wlA7=;*m^x{awofU9BgM+T; zZn&No6<^G2*o=RHk1lErKhN9Q;pitRN8c^vDF*7SYygaQi=+&42ujAZ#I^i1dfdz2HkAy30noQ5XN(;*4{o4sWo12r($@I znwEDoq6QdWMb@UB6|DkzTIqtiXK-4tGz!2!)h;Au_c*j+M0CIDrH>=rQLMNAeg$8Oga(Bi3gVZHOD$jF* z$0yvz(!kgPJF5Nx{+_P4)M@Zx)fG;QNw2YLL{7x4?j$u3daZJnEdqO7TOpBCy?lJ) zctEd#W#(u$ZW)|TEyGMrqCPBiaJA7SWWeXv;s7}ctn-KZigQf)!SGv1>Dh+Tvr7RI zScv-yENj;o>*KWc=MKssEB;lBoD{T=z#>KJ>6EIH87$ii5%nQkbKs1Bn!}x-mP*Ud z`%Fhlyz}fAGzt3nal_Gb>ean8WT5`s#?i>Nfws6c&=hJA7-z(;W{ic;@TOVXq6oE- zO4f+n2N)_Kz%g^CF|nU*s0`aqXx^jD)Qg4aCFy#x28?I3uiE}E$&wZv?0U#fvNh@# zVfn2S14ErPO$FSkZN=_!J&%}9DyQYa?z-x65!ci*L-w;NO&J%HaOcPY8YyosHI*Z9 zVbR0)me(5PiqWn(%@t!@QSJ)Y6`m``x?-Fw#=ByID<-<)bXQDr#bj4Zp-zLsQjam z0_}>QLRl|WAFi4>&BL0XGiTAtlzOrj!P&tE9KFISB@U2=uRG;l4=jcy@xK|Z`N|Fw02ob zEVt^Xqz|s|nFSg9cAJYsbjJCEYmHpH{ z46ID5f+oxPN(Pv80Nx#VwTWf&)UU8dExI87aK+l6nzC13_kl_MVl_Nl+QR{KCT1a( zb7eeS(91EfkfosCW+9$-X2Qn+y$)wOAE2c(y**N!NkbZ4r%hWh9l1#Z8vM(QIaYa*CG;_uAu4wLx6I|iA;zU=RWXQunC^-hu9)eHS+1DviaD;B>xy}TD9w&J~xtV!bP_aK#2!Ts)cYD>k{} z23OqZikn=q*%ez{akDG7y5bgBY;(nSSL|@bt**Gu6}P+M4p-diik+^w%N2LK;vQG* za>c!_xX%?ySKRN42VC)>D|Wl$Ay+)?iaoA)#1)Ua;;{_NRiDY|I`3D7xS!phrupm6 zriAJfAkv1J=Ao!Iwg@wA{TT_m8&oA^Pq96Ml;TQ;zyhFti1}VRExYS;I37P_&t%~9 z1Ofl~GmgAitvFI`iz-ihe%fc&&5~E`gH5T_7NW-Ao~6deu`2e8Vzg*^LZ~X$yHly& z&DmRCrK)oVk} z_4YSCmYc(q8ls;3I+yx3^_dTE>(kW$O-r9<^3Pw>fN^$f!@$y28NDZ^3l!H4! zHpL>7hMPik1Bi|^@~U&0Eok~dqZKSFH5F_#-V9+kPo&e;`u8eriBD5nZ@rCgk-nr7 z=TE;`ku?D3`?`$~IGQ7dM$n-r$-zMRwdFI_sK_5DhCIdurAkGw^-Z629ttgAV;#`+ z2yNC;LwmZ#NzR8_GH(WpqpfxkpJ}8!0@Tmi%L(X>PyIvFsR6>%Q`51Mxem$Hpfc(& zG_YH~)YDw7hwTC#io*cgQ#{W#hj+WYr`8vptjar|b*f$INU++bqNovVcU=C7$kCQB zz=WFi1vGfIy7rv8lNaGjxpL?v8tEMvA2Hq`M(&iSjlgjP!&6!YZn|jFn8L%s`hbqy zu<-Z=6+&lzlfI6mUnE!7lppg)nDz5hA>Ps+u#>rG&Rv9N+&Rj4&PjiW;a-ywvT#@l zcSlBCp%8-Q2fontAdd6p(Ly`T-@W<~I+fju)%ssMTdlz7rYHg)%^Wqg!_SgBv>0GeVyT z{UCIF&;vFVir%ko6|I&q=$-y(>jG=?p$LM1Fyhn+w3VKFW!=Y(qk|COXA-w6hqlPd zFPK_jP4H^yQD__&w9tO53beS%Zo}}2r}osOva3L&2Im$Ue$*J%4C^ATu9hr-4bj?m zXcbaFJCm#oqJ_B0Zseq>uMg$cDO0#R3Gur7^X9fgAN5Oss#l^p zykB`fOp)3v4@iO9_pl1=n|OYw-5l=8C(v2B{TZ6W&&xMkwzh5f8@&2454iNO_k0|L z$2*uF7*p10=kN?-$}Nns##h&E4G~w@s@wPkXH#HbKYO@iFW$b; zye)gsf!&XfVHD}Mit8);gg72K8bd4O!1+oR7)B9TetaKd1{uW3nl$3I5ZBg1oLa%i zEsc49#P>4qLKXcgWpPzf((f_a1*th&8Xw_|Pnsk}Mch#~qVVaLkY|4%f#dbPxzoA1 zwLvwveho}!SeDoV6B)l6zoXiDDej>Ka-h`G3z!5Bj+_kPJ(WXH+TN3~0&%lU9?8k@ z6#iS0OABOuU!Hj_L13#uRcTGM7Eu?50wlG>ROfP5Uf1U|u=JV|63)}|kbfX*yo#bW zKRmxK46CS}M;piIPMth!yf@D)A2*iKJzTc;szt6fX>u9UN#=s@lZr2f>MX8bq8Oc* zYM68YRfa-U!(@_LY;R>_Au5JjR6@Rw&UDekf&$s~0o`Sxq9NSL#Zdjy(a(Fq47 z(76F}@5Or6#$6Zs9BZ9|W)e8MaU9aR)=JCn4$+2$0?yN(C3d~r6VIC%-OY%drF}Ve z8I1E6eae=~eyy9oj*|mgc7^Z|@?{VCd{n?DD~=)mwt#(pjYv29SQ3rQ28B%filQ-< zrR`jb8l0|1(-vPRMQx>EqB_aWuiKC(hw{D`Z^1&j6#5fY%Im6^;LcGY>3r-847=;N zz@bnR5p|M|Y8m+Udl{fOf$Hd%1_*13Va_Xc=o{KIrcIcEkBeiV5U%MWG(o@PCg>`? zw~UVK(woAm*W#G;sPfZdmLTrmT>141oT*zEDqp3?U1YcWI)(PSOc86@K;<~vN=1F8 zT5~SBY*WuK&hY%9j=uH#v+^s{3k~R$3w6{VFZ;SfMb*w6)y1C|<`wLhs25hAj18$% zsf>-CQ$8LaM*)yKRpj!DBA2M)FsV*by>v!~=X-ft zLYTIgF}!=!^ItPO-zk%(j`%=DyS9`E@F;ERz8+OEmt>47^z&#EM#jKvwR)om3v0BP zry?%0Y=>t2@%^01bMWTlieObXf`2R4Qpmrl7k|p|yh)0O@o}A^-n&bWKS=DJQ4u>b zMckpSjE00E{7dSU?HOa1=ol&XE9#XwnIe8%FTBj1Gs;DIs-Q{TCFQ8D=$WAgkM$%+Oz80$y;^o@64t`e{9f1YpFoCy;r%o{gJ%65T_KA2w5 z_aY)1r6Bxk)cX4%>+i((`*2q)?aATxleI*nI3*qn+io<*gN~0YO0 zUnS(8WK#4by?rk^k~E5faG<}{J*8mZ6SgE>{#1nt{PZJYJAAUAn|21FzMSK#h zabl%)-mXKlEQRUzsNH7d=h< zspI&bxk)PKDdQzVR@~40uH?YEY{kj9W!}rUSfqf>nSiIvQD$b}+onY{#E`O`vOf}w z#EC%;ZgS{q1x(K4)tp306^yUoV;2Y`5x^oR@gBMl^tz;&VJL=%Q+y~X5?7!Af?^l~ zM4;3FIHxki@EE9gtO=wt+feikr?^m30EC=U1m>F?Wl5{ZRL(OzN)!*D!q??XNs+i% zO4<)pBxwsH>2SlNNbzVCkaV7*=n+nFgP|ZP8Pgz-AALD4lX4V-isW#O9HR`6j*5o} z$WbmS2#>A^jK{119*Yc*Qxp%M!pGwbL(x`Iyce@`f3u;`x&$fykQ9j(QkQn%L%Jls z#hPoQ&j&u$dP&tD6uwm|8@WJI)J6=&l3s~m{(j-}xG2aYQ5Z<+2cK$9g;ZlCRed|P zAbS7y`7BT26V&TANk!Obd>#oPc$uUq07V-Fc-)+XPjQg6+bZ}*iT{2E9$T}fGEq_x zcL#yd^HcFl$5oO7{yG!IJ6TiNo|R%}R*JQTqBUgU(y?0Ft#6f|NQ%Ve5_!S|F3P;0LOo47lxlsVZ_NR(xzxG5{ek69@?X3ft;Hi~W)V{t=PEWXc5 z(IcxKmu01RKPyGkY?>x!WTWU=F&100YWj0lilVG~tj|jEaaM{GvT2%_la=CeNr7H4 zmlbX^1zQgLvQZp~cQd~~zrxtWYZA-M??%8wK?{$#1#{>8-ECW`jiril4Gl^fH=e;Bk3YijT5VG&h=NNM&|b zio3H?e3OkLQX!sWD~wG%o)ycZvf?m4E5+SeDRQ!DndqC9LiXn>vaM&b@t~f0X4_m+ zVQgY=RxDd&#UYWE;`yu;$7ItoF*+;74OuDP&PH)!#b{Z*-|*7Y8}C!^z(b&ZW#Vwz zO+23!%iOFu%*sl!Co4s*Y+5FUW~I0$ zE5&QsD4JG`)&*J7`Z6m;=d4&2 zn3dv$tQ0M?QnbxV(J3oMx2zPsvQoS%DHZ{XX$VxOBnAiYcrz=-eOW1XXQg;FE5(yp zDW1(r@j`_Zu}BkM4FC}IvJDsrFCRgpoM-%LWdIucyeK4wD@|-C-bA-Fiqm%J_h0<` zHvjJB-}m_U9sYe6D+ZcUB4QW976c?9=$=Bilza93KfV3|zExt8W|S~5l~IdQ(zJ_3 zj%VpGS1sZsO)S!!-@>FobQHp9gwqf($P+C`a1k)ZbppS2AaeRLIs3!?#L99%X@9u4 zs4VxE`@_9eWx2Oz?iFC(=72f>D(&FpY@FLxmUFvooZDBHbBAo4J64u+C+2LIgq&EU zGjqdio@gAyM)K5hb5JaD3R7UFS->SwIqAw&s9>XLP)6};)Iq>v0A3P>4rvqI4ozpDHH_SG++-Lq>Ii}c7W zWh_$29J2V2p3LDubnxZt#oQ|>B}E6!*)JuhGUpn|Em~C95}`gqE<&Ri4i8bXRzp6} ze^@;ykokh1M`Mvb{I+ck)nbvp{1&|dmI7whkEt5Q@a1;JPhAtS$N-K-)f`=na2CSZ z2pE`)o`aA`fHayomw(UW-=+M!jDMH&?+X4spMO{K?<)SifPXLK-;4P7V*b5^e=p_V z)%?4Le=pM-=GnT4EnE0 z3n>S)lt&_GjzOr6a2x`rfTKqv9EH#TA@M$A^#T8W$iE-)@2C9x8UKFFzn=ill7NI{ zpWXrD30C4jgI~f*S)>1=He~^AzWu+|W(aFjQT`lY-V6r>iGxv<;DHd@9oVk3&aAY{ilu?^lWNhFqw!>It9KVId8_`mP zGK3)rLlK4{43FXCA^Rh_q9J6_(wV?qE2wiP9uQaJPV&Ngp3a;@v57?{1-P<(#v+sX z4I7uEW05HV%1Kh{sR7=gniimPCDrsGzgT2OfC`342+Y(}wPTT40ScMd@}_B@jcnuEJ-VHYmI>EgXqZ!Z4ufbv`6TG&=H{%LT7|72&W)) zMd*gmJr-FKDut3v>5npa4yX2Cw}MzCQK1A%l8UaDl;^UP|55J5a3VoiYLqi|_Ah6a z{%2CeBFi#Lfc3{BOgi<c5Ip53>U* zl~yUdAT%W|g)tlg3s|FJTvS=7a*ncmQ7D(EfEGH6Lgh`^^@LdD;_Ru!B9~-LAsZq{ z;nIvLXf$Gx)uAb{)yE=hm_wGf&t;(;!n9V;d~03H+{XgTaR}oPCLl~iI2~aU!sJ+F z-2ro_RQwb!=M=(nk`ahS)`xN@?W@P|y<4!#=A-a~I^&;Kh!xm!7NRVa5Z zi?PVn{B{Mcu4_WyRyh!MC9UD{H!|li%wX}?hH_<#k43IadsCN}7!HdLOS3o9#9*5U zi&M{F$(xvSs$cW-@P<&%gcI`cMt(C*n;1?~RQ&BLX@a*l2hy{&*b@3yxBb)N<}_If zVv(((9AW&_ZoDNR2e&w4k!_)G?2(dh54-{XJ3^^l$^TZS*674=T$GK5`kQkphHsGI z0sF`S&LN-ORsR z`1fZ1-O9hW@b5PM-Oj%|`1e-+y^Viw=ifW{_fG!Z$-j5;@7?@+5C87s-+TG@KK@N& ztni`#7!j}%b_mJOhyV9T#c(c_EyaK1Z>0(H`VpzY{a_nSJixyX^6zf`eTaV_=HEU1 z`w0I&%D<2C@8kUY1poexf1l*vr}+2p{QETjKEuDy^6x+R_c{LkC;vXrzc29bi~Rc% z|Gvz>uki1y{QDaJzRtgIAg>?&uOkH3!VU^CRi1&|WB+^PVv)!H&oqNZPk51N6A#N_ zn&O8RK%B?RYIwAsM(+u4G+7Y*f6-<{eY{V7E-xzJS-vWo(xz@s)F(*ls-Qp`e9Qv| zdQ$j0M0uj5q`thOG<=l=ClO@}NlEQ!MVXVvvn5fsl9V)eq$m$cqiju-Z6sx4H7}8h z(i#U^`#^FBF*up1+xpZSgVgj^kh&dFxA&>H1*u7*Aaw_#?&wqB8>B`Gcw$^~J4ghjm%h(w|Th;6YOq3;(lE%P@lIGNCel18@N|a@iGI5@ifDj{U8kr4J4iyNNU1DSrP^pQ}~t>rR(#R%gfjqK$H`GzUw6xL``LcN>-5ibfTW*Qy(IwAbTb%vZf&QWTKwpQ+JfS zB?V^f)2OEs^)#RQM#-DJ0KL&Tje0s!&+w_Y%Njya=cQ54BQyB`$;KO`EKS@SMx;{(Zxi4mZUC5EO{3yUB{&-3}pqi&d*q;S%xmlE|dpZZHF z1yNEsF^zgTQLpf+pO#oC>XXu_&nN1YKJ{+Nn|ueo(ISm{6;WT{QbEs3a!f2%a=i;4OYpZY~fP5g+O<{E;$FD2^LKD9g?hbc%Bnw1DruOaHo zBz0FmmdZHIT?8rD66HEcS?0%*1mxX=l$R6bdP$j(TN2qqNdlS+2~uA{)Ej*2FJ!Ke zJrnQtY1CH|^;JH#TsEzF)BH-1_tivwjZb}}%tPhHI;K%?BKsW;GE-3PJY&<> z5%u+wdW26!GIvG@O0kJ3Z}9p49OO%LKtbvoiTWm=`cs+P)CwdiPD!KQOw?O^>IWox zL`{;Y{4_G(Ow?O_>Yh>(@-W1^8$wW$TZnp_PhDHuw4&~wM!lV=clgwD%WafAFY)e? zMtv($-{w=_CAC!4g=y5c6ZIWFbv-FJd0yg8{x2x^okYFUr(Pj>E9zcp)OQi}-9B}> zM3DS6@h(cEzK5uH`PAJdHKk4-?NkJ6D=6<9iQY@p_etsqVw9imokA(1Nus>p=Q~{T zRerh;sEL0q?WZ3g>IWq?jj}0!s(h=V+)b1Z`FsZ(zSR2Zhd^oMYQ7H>^&Uw*$LC9J zu>NV3j}Yafl9F^LKGZrHfY6PD&oufNQ9dpyskKA0Qu}BiQxUcQ4-@vwIBU_njS4X3 z)p{^y#LJO;I3`}l`6jM!A^Z#BZG?9a-bL7p@E$@71VAlLM1Z^I6@O^v2sBj%GE2bO z3uLcAg(6T;#ODZKAbg4N6~fmD-ynR8@Ermg!U8Y|fF{sv5@;?7GP+DWeCd=Rv?^@uo7Vv!UYHy zB3y)UF~TJXmm;i2Sc7mG!dirN2$v(QN4NrE1HzRES0P-Da1FvngliG5L%1Gc6T%G$ zHzM4Guo+seM*AQMucmrW1!YG8%2&W;8K`2LX5j=$Y2sIE|A{>s8i_i$62SOo2 zPlR3wMF^)N^hW4|&=;W}LVtt-2m=v{5e6X)Mrei58lers$p~!`+99+@=z!1>p%X%9 zgf0lDAaq6OhR_|M83G2VX8Xl1f?Hcm5}QTEeuGsgnN@P;k8c6`7JO3;$E=Q>gRi&6 zBCV|l_&QSTuu)j{`v3A@al=GT?duc8xrx6b#jOvSctrhbRSIH>TS%ruM;}pTXwArB z#nFG)E*4I)Xi^%%wKNhhsZ-<(s^bi-8E2UJ#AT5r5Q)J2Dh?0$-Z^AE?wHF^~$A7YesVG)@=pKe#x>r zxO5m*Cjy$kYVTgT^v9Z!#B!Ya+Mn1R!$k2ZwRfKvs}f0^PtW^tgifa{ry1TZt5Pi5 zBnKjeRelN$JDgT0lI+jI`Z70eKe|q&86FpllS$&X#3^wrQ0PWN(VZBAAOEc(E6>ZL zXAyoTr5{3s{reS*_K`~Z~&wW8u{6+0qe?8>ZFTB zw=yj5YetrG#HnSGGMtLKZ{Pk~YM)|JNO{-?08N6WPORgMuj7oZeMW|;`*%MdmZ`tv|dWNn>d!6((=vI(|J+0OTXvf!0m7yfIfFSv5 z9Te?cmY`v4*m5NPN}b(wORvAqkz^zpzIn(w&GpzD0JFxEY*SX1cAE z%s+qw7=5E;rhCX-wQiAs_1$pdM?8;D7si+FA?q9Uik#Q#Ij_`H zvd+Wvir5S+%z(4Un_W_+<2N6CywGVOIT6N<&ecqf%i z2TJC2PKN$G&}3Rbn?xJnflG4+-oHnZ-#0FDzHRJ$-PrlEvGaLjl@BL_EdEmC-BhO~ zsuAknHeR{(+nT`o+nUL*8>8|hLs_1i{1SgF1Nt0)uc7DX<^nPp956~8gSY#)@UyJH z^y)v5LW#C2i|DpeO7)OR(NHLx72QLr-=Wm6jh&wxJ3nfT3K0curABo~qhF0ivZXPE zv`YRg6(X&YKT3s2D_`<|v*a`az}Z2!m6CigH~@m)EHM6{dq{pzUXfEJ&k=dfzQ)d< zTKE#g#^15Cqe`C14v}ZFW1p0sTu$;&DSh_rsG3Kzlp+yUif${Vlm`xAG=g=(A9N3; z4uMiN@|@~(@gs1D^|Uz{B={0;lEvg1&ed>oju)Fr z1fI+S;}5!rP$LO(1b*YA$Nc`bX&ukHtOk45g>EaQ%hlij71pr|_=E1D%Sq71$#a@( zMXtf~pdyY@#Lj}|2c}00)?*{MvmSI?DLrlh2Z+Ck#m66X4?WsLkG6SEn>?qLR%IKa zf`z-SQ6<^N%9Br$Q32tMsvFx zMlq6QGFMhcR^`S=pi8lIV=fISBt8LUe0W~aTZ}L$s2ADol^7V3gYdViK)KHkW}gzX z5qUuF+nSM9^xK+7P4G_)wfbJK0`4yKSK;=@mm66rC@$nWwzkxD7E(M_R1|Zu^d>&k*ofd-6@5F0- zI6nVITymVjXDs9M2c9xMbXzHWszq6EI>VLmp?lyn6ZlNebEf7wlQl%uB`F=I2c&A? z5`<_vRHC*z+0YydB76@#5}%zH^lozuL`nZewxOvKXU1r92u8GW0o+4v=upHZXB&)W zF-C{sDPu&pmBNUQyMx9@x7Z{9IF-Gn2lrf^)N?}w84#220E{qY~1EaOTXic7TsRpR0q@!hC zAg6lv}pc*=;;ZKV*K2o6BP#f1^0 zdmy$Ih;7kuoi2&!h&|9w#w7^X7R#KrTX0PQWqex-T-yy?wmJDc_8+aO#C&@=TGJ4h z+-A_ah0&Uhr;HZeRtl|!-~a?>s|}6 zvp^Z&mEyziHGn1k7umkjBHY_E>OT3d;DyDRAvEaM||d^Vom;q9eWId&1FL zgSh0w2Cat}t;_I~(W2W*p>-WN0Ei8^Fj{mEwEhmXp3HNe(12Yp={CvB4Y&jWd(yJ6 zXDz^JRb~8{6#xFL0W9gi$oBQbf!fzi#QoWD#5N-?`HVsAX+~@do-$%|TPeiu00$tp z4Hrg??t$2gK@r*UDl=pJZ&1+>1%b3V&+KFM=F(y+aZ*!YM3 zAR7;=e_?b_e&*X44XS_Q14yH|AK`B`sNTM!LG`a$DLTWJm7?29DfIz3K&iJ_7yLo@ zQ0gZr^+TTXU7que*62e-L0fCs@CT!jotxiDg(x?Z-$;e5VZ)zU@{hobC8yg;N&Y=J zK;X|--+g{q4k3h z1)Z%-shY1R3+znE$*25~L+eretwsi<-9pNUcaCJP#^zv{A&)f+G)1kJ_w9V{m6Z=(bXNoCppOKhEOg54wjQ zxzM9QzEeNnsjF2v2~k07YG71J*0=Jc?t$sjh;?ZJ_N)utR!WyH-~bicvI_Wv?x9N@ zy5#3OjkO}D;CWDye4~h+CyftGk0z`~S8!)N=(bXN3;+j+PiGo)T|)QJ<0RQ;H#qu%;mtg(t$XwwupH}&1+;A``<1O>!0gv6vppf)msW)zm<1T zy{i&p)+!&!rH>nyA}-l7UymEMV2o&WKVw9BRU< z#8bwHZYzb)9B=?W^o>u(hwgz-Z{Smu@AS-fdT5B|O451qG9Q;9L`6_Zb=mt_5Yg7Z zc;EbBN$O`HO8PId4fT{bGe$i^Frv=~$NPn2v=DL0z6PT{jM15R${5jYr7&6n4#4Of zTo@y|2S%m9XmGw$tN}V-(yf%2Rk#EJ8Z32V8yac>M4us!4@m)Nr~$~fA)g21QyhZN zg~V%UI6fC4E;+>DQ^xpQjHiqb-Bt>ptH1&Hti^@#p?ly{4t!3_cSdP^=mV~xyGC9% z;u6H?H0YxYXsm_LwV;f9DP?S|!6)gz$Obe@f=mEaT+b`7bRBUY8;;oZh)a3~F_#hB zgr|%c-Bt>*?ce|;HsivG(LE5G1jHt4xOPaQTjk|8T!L^-w9IL$1=sDMj892{YpQ|E zHYcCQ{-bpVF`pWa)}4q;PBCarX0&$VDWgTVl|qXS%LiJ!aACCQ9%#)2T66N9SsJj1 zB;CXEvImzSU~??{I>Q3&5m3e#q?Eri3}8wBMYgY52WnrB68AI05qk`A$pr?n`Ha}( zc*=;;ZKV)<9vpz!)3`8VbPvSN24agfTrWtX7v<$8T!L^dw(Kim!SymIB z-`Sn-JfM+_gCPE7eteDJWy+<+VUHOEl8^Y7MqR;&eHf`{zB_*_R<`p>&j;|>Upg7G z^3CcMw%XGD#$1|OJsznhpUkIQ%BV3ruY4NPay#9z&i-|7PsCtzN*fO*~m<~a+PXALk< zn?Ikb5F_q0YjnCH>Ex?v=*TAqomUv0?jUA#=(bYm3<3wBQ-lknL-#=EJ)rY$zVmjz z^H#p|M!xf!hGsAb0G{k)HzQo$HMrPC=4}ZJ*YIyiEXZh*Z&-i7CV?Rf@<$EcXT3_0 z2QA(Yn-M>bJpX2@MS&dwo-aL z2@VkdVHO{M&^`2M4Lw>GI42c2j#lC+L!eT}oHQNUunvC*Th@VYE2YD0 z-~iE|W6|*k-9v}2(4k9#)2YDeP~f!FYP^ovpjCAVSEG|rBiX?+s&;9LbYn%{0Ap5! zZY!n8r{Dnj-(mUj2i-%F{!pZEfz!LdDJpP!7C1e$E}wxQKCmEut=*jIYt%{hhOBC2 zyGZK8BilWV>+2!aA$K0qoC#LdUm?BZz%^Wz z0%vl8bGin@K`gMcGIqK_!p_*K5(v)N$yUamE|IV@b`~pgA{etGbXzG!I)MWeY0dKE z54wjU3!%t@0%u-LD8By^?Db17xMv>$^NU5@Pj?{#*lzR+R41G;AqRwXt@dw>Q)T5bXzINHiH8oyA~IQjP3#1-GFRofpdojYm212 zSzfl{5(I0f)RX54?zOSl0n08tJ`b+M?g+tW8}Yg~9G~roOYSoG+{5_n zz*EMDZYzaP5*&cfowzVQbPs$U1wMNUoQDdW2Q@_ZOVS7AftGf{1+zt<>boR~BOLgEIbQL9ogDl|d}&zsM!< zV+lJ$_MrvY`yr5hK#ac%hwMYdCBHO~eZi1@gr^J{-Bt>+AHV^SeSr%@M)!d17eMw? zf%8Lw^PR@)M@jmVy!?zy5U-!4s$2+vxA6J}l=0tE@cP~0Wfwx92gCJ)1=n{WaQ#Yr ze-DT2H^e1>GjRRNaQ%*_3>V#23a-QPU1Pvi4Ht%s?g3XUUgR7UcdEo45qI`!#Ey{E zN6O1lxC9Y9C~hq5;JB#@j|OGDdOXvG3F38xRFy64SPQRapo|}rg4eMIFWbU=9&BN?EVvE@@6=Yr@x=GoaJZTyE_sZB z>u84S1UzN9=(bXDbp!{%)e;wmi|zqeKHzE`cXH!SgSb;)Bi2b$cb1nfxC9YvY*|#VhKue2S9ieGHSTnY zJDuWA2aVWxNj*VcCgKuAtShuqwPa5Vu}Pqe7si8g9X$+Gr<9n&BlcxqkBO1Ip%o!$DO`$r?SAPcW0po|x%;5EqLWm}lfgW>8M*KmH5Fzb&j-8Q&7t0rN2s>5c1}DhU|7@UGhO( zcmJYX0S6Pzq`W10&b1*a<4MZfa+ah3W<<(b@gStUCkK)OETl{pQYHqBeB>&9>>fUm zgU-mrNKcv;VdPWMw5FypGA(2z+LJsV8X=#-ewvw(b&}^y4GEb-Le|S!5(1bJA>WDz zA><1=kPu)YxLQCI_99TO+;X&Il*pi>7slrN6klGvvha4B1O= zHuRG1aB!!YlpiF|xg#Xyez^g_Qe*l<5H@f4WM0+{0cu z=!{H{^pXc7jQk~<)&psbJQy+(?IoTMt(WYB{exyg{+2xFfsl~bH@{$m;z_MSk?B^_dUck)7l55Si+!vUw@B(u|7@qTj*Hf?`;yI5aEHrSv zSrTVncv8Momhf$_g^X^Hl*Z@)Gm37Ec#!5E&Y(m9mgts9bc-zeRm*-Q2<=MAlCa&- ziV)hOFtljPy(*{ujVrH&vbT`%I%_^woU!JB8P$A>c#sN@XN5%omYT1Wn!jz?D=d4N zWiJgXKUH$|c6mFjyt5+GF3Z9u2-{_8c+$`=(9?d8^e$s8kun)0U`8?CD;^}Y+Zmb& zz!KwHiE)i(e_+|~1p(eCSrUAtb=HIdMqB3tHxxd{-wS20bv|Ov?-ysRIbcRLpD!My z!cVipA^=OxH%rYoS@uTDUT@i-S@tJE{TGOW-awne`a2t?qW%iq`mimW&)mTWE}c)p z(}pJEYP$Qj|4W9rP|9P7fEk6jLOe)huQ4(afF;BqB*gD6d#h!CYuR60_Ld;Tw?sh? z@%u=KTO%QU8^+>%9fr6iJZ%Uu)(dwq(3Mgu0|m?|&`-sK#PaeWo_D{)jvnHi)LR%hGQze?-{v4Ed=1*`<{x(;&aJ!c7;!g-^tM?IZKWJGverb@gUTEB?mqwfQ6%fgrj|yy*D6eyQ}wu zd)OfdouGYQ6XRPu*}35h!5>A_%F5LV%FYd52u81P&j)v}2fYs+=ElR>UcCrGwM5gZ zn?_K*kf3NE@_eul9ctjGHhk4H^HWFioVp=Db;wU$IZJ*3GvX&D9)zDpav(pz!cVU7 z(=69+nrk=CwHpR3<-6Ji?x9c)I!nzYDt~U5A7QDvXj-XUc~rU2(smf>>_qV(l(m)vDFYVDjupyU z=GrZC?dAbr?OoLl?%^ak=zO(wLt?LL9pS5^Xj;dm@zpxyE843(AM8~vB6Kx3(A5ck zTbt?XEP2jxAziIVR~I=;x&Skx>m2bQbe$##(giGZbriZz%C+0)+9%}N#|Mm^>uR6p z9?qA8&e%y3mEXfUM;PlZnpUS=87V}1Sm%&2$1`LPYadeMoDiYx`0#wt!}`E+XESAe zCC}*;Qg#X{>nCSP8DK_~4HXYU*#J3^GGL+XOrfktu6mPju(mpXAve<=G$R`Hw<;fW~??&+R7daU=RHFL>lT zpX9my3$w|OL|%#yDJ*W}d?>R2EsMktL~qDLU8YGP3<@x#pzsM9adZ=75dm0&+9E-1 z&a*e=*&Bn1?vgBt){UqmBHA2A6m7^&Za|32+2{ro`Ig03tohyIj5P<$sOB@ogH$;9 zbPcf7e23J0d!D^5&;BmY{wAnAK3QX}h&IReu=36}sii+h`Od99o8ud|_9c@i{>S&a ze`HYj+6{vO%qS@D!!ffNi$n)3LH#a4{hDY0l4t)EL^K}}?T9wVuVF;d=J>@8h|Ten z8&IS`|2xnAE6?7OXYURwzf5wiHPPnyJFL9( zm(I4Cg?Nw(f65Ar04z1H zCN-~;vMZs zA+W^KOk!!8vKt41RFLy}AWg$SqHWUn;Nq|tM@8|@H~=$>qmFoxII6MwA^=Mq%_WY) zl%1cl^MX+DQ5*dVFAPI*@*{1McW|*B#aQZzd&UBoQ7p~GgM`q4A&3Ahu^cP0v`pD8 zfuhb%arA#ZzaLK>XbBKvo2e?_ne&f2Gh zx%f+&Hj?L@mm$v6W;kZDe(e5Y$yPty9wo>J}0d?IxZNKG8ZF_&F86x|#XuCV9@OAwONoPj@*> zegHG#=K}E{{G1~P@&hdV^bvl}Pub_D>|Oyy_(qPXMm~w7Q*^$Bs(;w2p`IE`h^_zB}bRYS#kuJ5l7y~aE6H^a^!ss z=ThP5;*>ogAm|EF5Q6smC7g@h*w}}LL4ofHh%u*HZx=V{LQT)W4Dm8`95QS z88NoVWo)6(7_cyQw=i~RK$rK8oF%RD~xk_)3m7J&mq=L%O2f$@6jG zZ1KZ7_nO(lXK|eAAzSy5EqoA%{R=Q7wmuLK(!bu81N#@Su=SX*^+?KoC?IULtLJ?w z2j9Zc340{czh*`VTPvE@<7xNsnIU10XUP8b(82aEe1*rFX=V)H-Ekfd8Jj`I@WC81 z2AC0JTf~Dfwowjb3|JVOEsV_y==#c4`r18wBL|(XS&{xVH$vC9qG`=Zqib$RSG0e5 zJ`TKpeFx`r&1`LzJZDbG)-z;lo17(EfEls1OFRf$Kgoe?0Sj9%30n(N_6q@Ff4F+P z-NT=9&0hrz2-_o?*2`)4_g6x~9M6#b>xF~uUwh&G6*FUhNuKj^$k;+MwolHI zF~E!%D=R;I7sj&qvwIPMg|Q{V*rI^0a;{Q&_fSC&I$et*{cCB2u8N{*y^%)O(vYrb z|MGksc>k&d=S$6ORhB&GjgYO^$<`rqmTUoL#8#eo5Rw|of&B|u*jg`aeU`F6N!cHz z><%EBFm+E0e(bnAL287mhHo5^t-r|16nz!|94wzBRJG(VM zffbezfTiX;q~_aG_O_J$UCRC@sC*a6)th5`Sb1lg)DlA$G{<*t?cJB^ZteLNH{Kkv ztuQ|_v~E%q8wD_<(0Yppi3s0}Vow8>(0-TDeofiGr0k!9xcW$z#2k5-`)e3iv{8O> z!(yZS94Tn z&K{|vvME}EBhKqZ~0+>-OSBVD+VH86U0a#+m$?s%m=iC1VfsB*$ zdLY^P#@Ffp9$Xxy^HKcO;+=5-W)#O%@gR;Su=*kZOB|IYj*9tq`Fy)QQx~fmP zhgovapTBk8R^fZY2KnK8!>2{ls-Lg-%myI~j%UbAtaeC)bC}5K?+s_eS%Z9GF8_aVFp2<;j14sCNm(|+L(Q3(ajte2|Iw>S5+J`(JOPT{*5&Y4=b@4mw?DMY_|u5xUBXrgcslUFU{$MZ1&dV%WnX!73=L`rL>rciGm$PIHFeAot#e*=` zSPodO_HFF5jM)Z_mlMXXo3q0_O0EDr-T$ zH6h=fGIhr0u;)SsoOxbP!&GpNMKBHB#?Vpe-VHs zkhdj}75VnEe0yoW{dy3{qmpZ_Ol#W}u~<0EUlwWFrD4;){+~^o{tdpFQmC^s*0k=K zuxZ~RBTtAj83D|Qk@@05h`50?E~z_QQ}4XSD?D z&#~Wk`9RyE1AE`4UFFgdY1xk%$BW{ZaR6o%$5QbiaX4~d9KaIC=Mu+;e0yEK{b>-y zo06pmu^|j1+CSGBWB4={!zRYCOx!XCz>H#8D;^|U%s>D$3M5B<&MSfJ@dE*tKuQ&Kva<^8fAZ~p z`S#v?`_CYj(xPCMF0h`8Hf&Zw@D|AVN9yV~>^?UhHtgQ8VgGc)IiQ9uFXcI<3(}t_ z?wPP*a|#ef1yLp+fEn>oTRe!PDso`M0t+992p^RS>N-1$K=ByIK$qKhD&kz`EaS+tcxctQSV))RF4?ZClF?iEUfc4GANL8lhOt z4eo%Nxw%x&X%K5>_e|K#^~ugrqD*!GGh*ii@gSreOHxDt7Isp?PHutStiWzsU^gzX z8wS+yBTPqlEqx|<$qjjlwsbR>7GAq*J&(m~kCzj;m!Pt`?D4nn&cqSX`|cS6?ZF zaRFu&*A?PHnrRrr5dm1@I#J?M1$MgvyG;<$7|F6a6zIcV6$a(BlUn+nxQ!bXIx(gd zS=z^m_dDiI9~h03BApJg&g-5DJ8yfEakVIu48V-Ym?9p8g9&nABLfQ=orR233ha{u zCZ@`Hp~!99p6Iiugfv9^?8#xst8QReZKr>v^)3us&*|shKk(@2Bd7O2 z+0@5-uSj{$pjgwnXTqktlzcd%Og;cJ;sYNG5*n7sflUW2e2fx4Mikh?3+$l<_TYew zcO+N1iVO=zgiJ&maCq2&&d|t>bg;`rXJWHNHS5YAyli;?8qzNPy!R z!rHkq!oU@gsQvezo8au)0wFEF8uNwZIpYh0)tGC@(PlYIjsP>_2wwscYQB*J8yi?S znj#!cDzJ+Kg79r1(fiRo{3HjRph<3Qe3O1dgrHwU)0&n>&#+iT-ZUd*$?*)?jUI5RCQbK6E~M!O%BsNe3^Qd_CC_;* zr0h{rR!z>5GQf-|YbYM1tJIbQDFYVD<_Kl83+!11_LBi$ja=2n?xBesbiQW0p|V#! z8{w;|Xj=2q_0Fz}N|{_KEJHy&QDL9Er;BVM`*6br4N!ae+R8TM{zn zc!um@FT1ppvX>&1Eih1a5*#lvQ+BfCIg3Ne7Ll@!a+Z_|v`SeDxAd>)kZIR)u^;dzj~gbS;n2^`?QY zbKrNCnXYps&v`ebYbEJAPtKAqz>Mg+R6Gb>{p3KpfQ7DgLf5AS_QwVG+5&q`z!*LY zCfbAD!w@;>jD0Fm`8{l7gt1|wX>BObU+HZO8FM^C_OOp#+DX~k2xV&wlwAhL8_krB zkUVEYNZEQ)Hd4-#GQf-|yFok%3D?VklmQE6-wI`47uZ`0?9BmR_)wRq-sm1~l7r6I z*KVlnVcQ~n-7K2c)&hC!?G7D!W9YCg!k1@Aj|`HOXjdwH1jCk}klE==xeb2uthbz#axHbTt>c z3JdN0LOZX}whHYd1Jb^64Zd{`-^oEItxy8<@9#%PNZTr!R*ORY1=`UeX^v;ePL}U7 zPuB7xtXUEHNCSi0P{`3{2EUg)r$xx%QDhL`L?eTM88P^$cn}8h@iH<9EDS1Puw9|u zrqFI(XtxUJ+v95Qbq{~ZL8q^s8#()2`v`seMAJGkjlT9FebGMW`5=33B8;_;$gK?Q z{f#o(o7uyM(VP=Q_D&#s|H@gi2bd9i`}yuzS7EPnp?ylg+kbs`th2=9cf0Np-uT_I zZiV{0z3w4zj%UbjcZy3shzq`J#E*@2HN75PTKQ z=@}AoHVMJk(AY}=Ga{swco0JHc{CCNEQDMjg!C=6dk35x=j!2;W1?Op2c46?kzUe2 z!buy^v@R;t-z4@AIdMEg_LAO)UeXp0`kP5oVV#DmoQI#yT&V5#}NQuBKX?Yj!?I|}XFgUXjkuHG*9gq3&hl3L>Cj&`{tY=W>| zZVyiy+9k60%Kb*seT?yDDU&e*W)$N?;z2^Yo1uvSEHOSNF+NggKU8Qx5Cr(JWJ&Om z)_EihFxol~g)QPd5XxTb%wWwQ5ofG9U`926Njyk}=dr>f087nhOU-8$+D{hRGlQBh zbX8w=53k5Uzk|$@O8QUUxsf}FBbwHnLcL4Q4TE+(L*7%L3?p@BhH~%}eihE)a@Y(|wj$Raw<`>$}2L!$2>aBDS@5(_ZXucZ{ zhjcGT2wEkY*1|M`UJeP0_6pAjui57f{JaNWFPr&!U-F!VAwMsXpAY0L`2oy`pAF(c z_*p9l@&hdVyea&=QD`qIv=;>wZFE&XcMqH7pi}gQgyi?36%mTQ5KU`&p?=}42q|(r zL-wI1AurCNP!9UgW;k16=IBewbC!o3Eh9%;O%5rTdbO>1?b+;ZGI%cZ#QuZa-k8M5Q7G?20j4%V1S z`9t!Y)gdV#kd)nWmZSh?L`sDUBqd7@Bn4PV`CLfZP-w3!v_CDhKMts==xSGT50&Mh zQ?o&$^83!_2sKqi)B2)Nf2wSbP~#iosj|-F7khd?b*D*q-hUjPHau6{Wmb8E(M_7T z28!EkCh}0pbG`_P+(aU4%2^T#m=TeU#Df%FM-C(sScv>yh}>Fee_LpO9kAHgRc+!P zn#w_EajO?;*3w4SjtGm*MAP~qjl~@yi{4F&k7nNoNc=V=@#_O8F@@50m`Ti+Jm-gy z#O)-pK+cjxz>G+2BOZjr7IGkoz(V34A#r!1y{pjvt!%!%i5jn(zad7wzF*iedU?1>RImLY&qy$mbP)*l2!Ai zjjRfG_`b52Xjq=bMS)OY-ePC3ck1{LR;yS*#-dpmV z@^KrR|{^CjHaj6xXPBYO}+7%U-- z6(^nSF_PMsOX7tvq(}BJ2PaD=-`O11Eq(_~$iLialV57yVp@lpZanB2r5YApEvn*h zxHV1$&9HLrq{+`$ZZW9_U-7Xg)rV05cDS^Z=(@GN2F5AR#bugxQnA?$i^jXfjyRxV zZ4_HSEcRL!>$w;SK1LsqA6DNE{Pf7ayk}0zb;d|~WRKCC5}Zh&Y)WvfHRV`M*BUMP z8Uw?H@P#1!?)`Qkv*U3HH>-mXpVjs%gxVwfYIYkJWYF`Ai>3X0WM9ww2W06!6UB2U z`+7<336l7?kcreRo-79knFrX7riiMPP&`HKtjPj2V?$S}jUaP_wrD#Q4pP3GsRvWM zbf;-v@zV~p_$nyAc3AukEZ%o>gSa7AHy)@zhEpZ*CrsQVrqaD!$Ba%+-U5Hx-2zSJ#f4PpUO6yQVCfbAlM*`Fw@GT>g5)M7 zC6f64;{n(1Avsug%6SKBC6nj#UXv}ijHjFM-YECXSDVXiLQ)Lo9u|EE`Z&S+DZ=X7 zu;?i{=homcsG#Ja%l#^6@K3xxh8s~M8n(MfbXeyZl9zfK4y1&~1vsd#JdN<=W}k<3 zrJ~uM%1l8PRG6RjulujAD0fTwI!}mB+q*r3Ck3RQ@xW68v;wk<<&6BRR5Zs^nI$Mv zfLDTBfUonk=mZ7K7Lc0jSwAB{FCfb;qEgX3Pi0P80a+}BJmJQDN+Qnv|=z2%PSV!U77|CQ$DBj z;XSAAER>vL>x;$$IVp!1Bl^eF15AAr)A^Xj#vfrGl`_1Xnu;_W#ilwoKEkuQG zk&}K8M_&wk_?WDA_ev&JUl!HW0@zC+uLx*6-2)DCUi84L@M!L)FL^4jiAtmwY2DP< zSrjc`F$!4dSuaU1Anc|udn&K%1!&#W*Lg#9f(VuhNWJ1&zbQbAKyb1Am+QdsRF(;f zL?8%3xZTv(SuSUT0#*n}z3N%N70r2DfOJNmOEicD&e0jkHu_q1MS3CDP$UB4p^8<8 zSX0qCIwKsWe0LZdNoRZkC8yZ<@lIB)VbN>IXDhD~gJ|&On-(n>%ex?h}Y2-64_` z_yNxLJAbj<<+F;HV}ywNsdt}W+O&JS2L#gjYSBzBfxEW%BNgK{IQ2R};JEl``Bb+% z{_?dxgw`9n)-f@ywa{9sYqg4LeFUvHb*9TFY~$P13J4Ir;9!gheXga}Ur z{gZ=u@Ln)1nPQ=5LZ|Jt&a1=8av-*oCu6PmPDgg0cM}nyHO& z*Y+W#V!RutJ_iUK7q6-8-?@CPKcTfr*IFCX+5@dGbgeI9T6>|jS=ah9ru7%JzSOn8 zi)rnH))rlBTTJV3Xnmz?{S?#s2U=h2TJpZhdw%*%{0psbbgj2yT3KlBZ*{GAVp`eI z`cBvSIHpw!T3dCkPh(m+(AuVJy&Kai4Xy8Wt@mPDWuUcP*ZLr)RTf%5=vwPyTIHa% zL)Y36(<%?GA9bzIV_FrU^^>mkRZOcQw0_pLzKLm7g4Qp(*7lfIWoYfxwRXg`4iPQ6 z)B9b7*CVbu-069>@rJZQ>=b(r;oE@hB7`de*?xqp0NGH4?*p<$2v-C0q9yzgkXI++ zM}X{Bgr5Mi{}6r#$Yvv456Jc*+z7~qAlwAVE1GaKATM3QEr4tf!mj~IJmI&1yn+e0 z0`gKN{2q|}6aD~5q6vQlqC zN_fMN)3E4wx@A7=URxBcN8}_J2xbU%a5m{)|Cm_NzOHDd{(w`ddOd*M0D;Tmj&=Nd z+oPV=;n4b1*Xk70Is#gIbgeEit@_Z~t81Ma(`o>%zjUqcF|CHs+NW!s9@ATxgZnwJwNh++aZOK4TqwZ_D> zj)7J+U2AMi>sV-2*R{sQv|2%{hOTu@OzSvk9ja?x8`EkHt(v;lbuq0XXdR|&<;ig0 zeIMc9bJ{?wmadf_(`pN?+PYR@OsgHV>gZa{V_L^UtFErqBBrIFRZrJy8PhreT8Hae z$Hufygw_$d)^Rbd_Ry-YYZb+`IzX#|uGKcCbrQ51>RQLgv`&UrBVFr+m{vzxj*L+eOgt5Zy?3$&W)T3upVU7=;^TBpXePK8#kuGKxJ z)eTyCy4LA2t?tlD=~`#Rv`&LozOHpvOzU)L73f+$V_H3+Rj6y76Vo~aTDGorUQFvu zXf@ZhddIZRg4R*GR^OP`+0bgCYh4i2>Ito*b*+nHTD_pvQr8*~(>e!Q$LLxY$F$Cc z*0H+Qr7^AZpw&v(8XVI)A6m!hT0>)6y`j}w*BTzv>I1DJU28;4t1qv&yjY)tDSXenK5TuiG!v`)~qu8C<4fYyn+*0nLMfzWEN zYh4%9x)@p=bgkl;)+Nw7N!OYb)4CK|C+k{MVp@Zs)lt`)7SkFGty6TZl9<*IXm!%H zZi;CQg;r->>z0_-FlcqrwQh@P4Tn}&UF&}_t;?Wws;+fsOlt(Ry6IYX$FxR5tGli> zJ*G7ZTBqq+_rw%co<uvm>#3O5IB50KwVsY?T@9^sbggG%TGv49TwQB!Olv%}&eOG? zjcHvAt@CxQ=VMwEpw(N~njh1;4qAP5trufj*F&qXuC*|xRSd0uy4EW(t%=aOK-YRT zrZov#7wTGzVp@}-b&;;MB&LN~XsW-i^+rq!`KbZA)|)Y{Y0w&|Yb}py-2knNb*;Bz zS|!lBMAv#JrgbBp*2|7`XHut3$%vlT5Dojw?b>EuC+F% zbsMyX=~^Ghv~Gvia9!)unAZQGb(yZUE~a${v_|M!8)8~_ik7@_^e0h#D}*;cc;m=- zK74I; z1IU>xVJkpRQ3+cEaxO~P29T3Z!ghe1T@orlP9q6V1mt{?umd0`hJ+^rat26v3LvL? zgq;C7rz7kN$jKXFH$cwP2u}m#bd0bEAm?3#X99A9MR+zKXHtZ{06AqMJQt92Bf|3m zISC@{1IXD9VLw1lYX~m{UIECFJ>ivr9KsV`1<0{F;njc~loO5zP?+!rK#q9{Zv^Dvmhfgkj$#RK1>|s*@OD6sO9}4)56A-QhJjwe28Mb2oKAY|ERoMfP-a~ zaJ^_Gp0->wxkm(jy~xwt&w9~x(U-r-ef23%j^xqjT_y7&QE1wRP)Go$XGfcr6?`zMX=Up+YYPet9&g8M5y_fHG( z>zTIGcdVx}8#TB|LO1O6^>v;>0W&;$=AeM9JnOjt<2*1=fL5A>Q7r#uyW`cK%Cn*p zDNXXi?T)_AbD|TJ_B;x>#EomLvUYp&MD~ILD*yVSrAMtw;sL9K}jQEUj2& zh{q{*FNm!bI~T+v#jXXhjbc}T*jBOGa804`lwb5qDEb(0%S?N0TLho7tl3L`R1)37 z=xv#KS@gxnD{{~~J_;#l*ydW)KAuy!-yD0tInCwwBk-1@PhL}wK<#32e~)n+s_gv` z=0Jas5#J5;syLTxo@GjiuK{BBy?bqCvip9yxDZdvHSO}VEQ1_hnPOh^bw|yGJTBc45p7WoyqhGrcW|` zis>w-Pcxm(^ckjen9gN7kLj~apJVzw(-)Y|XS#sti%ef)x{&G1NQM26%5hj21N$EWR>Y)K9SZ+GtTb!QvaEMe$e3t@y3k z3O__iDC;}36@HkKV71k3g&(RUSZy;~;fE^;R^OYg@I#gatLIbvc_sLc} zj8;t(%K6b~VI^4nWVFaju=v?%(JaB@7o$aCg2hgw#gPdXzZxwH5-ff*TI42J{BE=u znqaZZXfZ6o;t!+6@C1w9MvKc5EdDfFj7YH9W3(8VV6oR|F)G30FQdii1dDw}ivbB1 ze;X|ZCRqGqw759I;$Nf1B?%T;Sb~ntH!n@F$TnIGO0Xzpv>2RVkz=$Nl3-EVXmL$~ zMH!>T_ymixMvH3`EXo-zCL~ytH(FemU{S$naeabCMWaP=aq<(PlG$ovvQ=fX)ud#r zL(Eo_ldY195Z`3qf;gcu{ zR)?9bZcetUWwyE{*{ZhL>eghdI%ccelCA2Rt!_`Ys%N(PU$WKVW~)1rt&T8T-I;7v z-)wbPvQ-1K)!oTf4b4{fBwIByTTM^4YHYT`r*aZ{ZxgfCeaTi$%~tm(TODb(!UA4G z4V#&*9!$2f%vKL2TjiRq9!|E(Gh029Y?U%wJ(_HlZ?<|Y*{Z;7H6z)o&}{X1vXyPN znwf0X+-&tkvei*$t0$AKT9~b#O13)MY&9#{s-@ZL>13;8%vSjBQo@yTtl0`5XiBhZ zWwx4=Y;~O3YHqSsYqJ$T_moh>BD2-A$yRO5R?j6{wKZGeOH&CoY-hH5A=&D9vlTuy zl~9&4Tj5(&305bVt?=op1gjIxRxc%6wKrSgBS;Blbue4u162uDCz-8YNwzxKY~>_d zbu?RHhe$#VPcd7)mTc9@Y_%xasf^WUJH6R?CvDPB&XEPqyk|wpx*Fb%xpMtz@e+%~o$GTb*ULdMDZHY_rwMWUHQL zt9O&FdYP?OC0m_iwt6qw>Rhwc`^i@4nXT{@riA;(`DUxt$yUA1R`?)WLRo#xRv#u? z^)*}JgKY_A^)p-H18xac7nrT^LAL~}3(Z!aBwJl%w!#PB63Xgtw!#PC608Q8t=1)5 z4K!P=Pqw<)Xw^HRc9$3}`XpFfYP9H^U@^#O(J#Sbu+idz1dAa?iwhGhh8is{O0XDa zwCJB;G2CczM1sX-MvF=b79)%nM<-Z}G+I%ai!7Xlmv^hMvG1f7FQW9Iwx3+Gg@>>u(;Z2(KW&18l%Oj2^Qmx7Tppo zt~FY8Pq3I^v^Xun;yRjaAuqeW4I#f?UbHVGCt87lb4iaXaKHd5Ta4zaP~9(IUL z6gRR%Y^u1M9paISTiPKuQ{2}M(Nf&p4l!48hdabP#cl2oQ;K`tA?7P?c!yY^xa%Ea zq2kteh_>SXcZkguH^D@iyDM&7g?O6cj#P-JD{eD|*h6veD8w@qH-thwQ*oCk#IqE) zZbCd;aX%)+o{F0+A@)+-ISKI`#VwH#&sE&(2=P3{O^guFSKOTlvA5#3Lx_D8_Y*?w ztGH1RVn4+lfDkWG+|~#2LdCs$5HC{PfCsU^;;uS~0~EK)K^&;K{|(~BiksRXUZS{D z4dSJWThJg5Qruexaj@d1F^EGHcY{G3s<_Py;xNViTM&mUZp?ysnc|Ksh$9rYQb8Q4 zxJL@&D8&&p5vpsm2M_1ehK!^o$#pQiMtb8l3+Y@3* zTX8|25Np+nEA50>gjQTaC&cQq;@UVNmW>q`y$P`%tQrL&V4+tv4j@)=Rg(Z>X;w82 zAl6*fkpaYFs%jQMtdc4#fR6#@25<&oUI4LRsZs&NN~FpUAeI)FKs0ss!ML}f; z5UYKvc>uADr;Z9B*5_1<0Ak@y9UVZdsHv6##8R0$CV*H2Q(VC#by(a|T$&@qs+HoJ z8zGjX6c^J7vCgEpN=AqUB*o<~LaYoau4@ru$wzU)iV$l#iYrlsSfo*0Vj{%qi{jc5 zA(mAX7ljD1UZUCuAz&dybqF9dXM*jk7u{fOwUx&JG~n5i7poCUtoEE8}kO7FUe7x{B|lnTyx8iZ7c9@g7$3Eixfq zuqwVDCd8Xl#rM91cqOX%LYENlIu+m465=JM;wxA}yq#2hw@QfDj*2f$3GqHrT@+Mu z17QCEZUh_R@R9&-2D~(YUjhya;1XOSQ5ZefHwv( z2k@o0u(1h5j|oq+gNIVN@~e_Hp2 z05InLdAmuNnTXD2Ikv^Jj;0E$L>p3t;(TsKcCuWba3jWCtyBFby-S>q*?3O=h@ht3V z`R{>Rwwoa~G|4F?Wj_xOv7OrPFPgwl^q0YpK{xe+(Zc;jli6av(Zc;jli6Z{(Zc;j zliA`$qeTP0g)m#ZWVCR9(PXw*Xtb!GP{zwf3-=dI<}zL}T7lfjTY`Nnv53mC@+J@%o-R9C?^1qd+$Rc_j{+y%W3)2As;ZJg@>7i=M>)c z(v&ue4=aeJ6rVy6a}*yh5KAjQHz1Z#FTyp%vWjo5LgqokBUS6Pn$&g zjr{RL|Ic03g7Sl+?7+hNj92lt8d+HlwKL!0%;DOpKjNo;h@aXMKlMVrn6KyJr(TYq zdNzLQMVUTcl^}W_^IdPb$cm( zYHs}0`~!>tf6UH$AU%Rzu?V)u>-J~-)WUd0=EYAfIKaA{Aa!%li-heqYvq{bfa?&U z-hzrgL|%#-92?`$>RFG=NqzV~MFs=-C!_Jj7>!SNN8`E@=A8Ja|CM62e0g?)#t^Hc z6Xf{49e=jZnu+4P3KgQ`KyS2P;o!`fIDItC*^f{Obfk{rLa&EbSqI+tQ(;Xpj0)vs zvBsqxP$3r~N-QNcna;oD>=t~A6fEDvBZE?p&dK#ibKj`wBk}CcN4gxSWxJ=uhRxJf zOj4h~gOuD&0P39fZ0P}=PoZNyA}KTuZ7E5&wol?@>N72?Ry1p!mQ^R3wO-3QESj}J z%PPi{GMc?n%dQ#C`drJZAI;jNWz~*meW7J>su0cItY>3R5Y7Hl&&J?Cn!QEO#wb6U z{gs}L;e0gvYdss|_GtDudNu~=(d=*aY>dPs+0x=?plQF;w3gFH0wt#D>s_;la@6!n)S1mH7uI-iE|Y(0BwT6QTtds?~AnwQhFu{sycF0W_f z4Ole0f}V}lyJ&VrJ^Qw_>`HnzR`;UTmGx|__C>P~(X;PJ%dVnl-!fSX7Q?AEReukvW=ute%ZU=V*2-JsXSA zk!-ol&&FkboUZk%u9a%7XJf58;v`k1XJhR;n%zdv##(kXyRDv$we4tjJ3Sj~-O=ph z_3Ss&vX!2_G%foCJ^RhH>=X6uWog;%_3Y(o*&X!k6=~Tg>Dh0kWuL5PznzxdQO|xS zE&CKbdu3X7Cp{Z$^HEYe>)BYVk7jq#v)@b0?y6^FEk9~~s-BIt{b+VKJsWHN(d_Pe zHrD>5*{A8*AEsrWu4k`J%kH6PW3NEe`5AgP_6|g|&(yQAmmr#bmY$8h1<~xY^=#}l zh-UZHv$6Len%zs!#$JR-wp`}DH zaRLglf#PHnVnfA=CB#OGlSqh-6=#YNn<&l2b;+cx$RfuOPj!hw+tvC*a*i&)L39*;r_!8ndiepKL=PHgHA)co=Mud32;&>2Z zZ^f}6#6F7SJcxZ2$8-?;DURPDUZ6NugLt9hxD4V&ieoT{{T0Vs5CYRb#48jB01(G0KI|c0srX=rI9Bl?4)H3*2R6iU ziVtUqS1UeA!gKy40wdQUqK^E{0m-%^Eo5>ePEu`b}q}B zgOu-c`^stE!+!p-LA$5Lh9>>QBy|p+XyW#QnEmmR!5U1PyaaFTpNs6DX;^eF?C9nq zu|$ArFOU1nY5ChP)D!;$V*W9f^8CL9|1(4Xr5YBU7x*8TZdp3uBzUtws9{lWFOZ8x zJ+{tP&$thv4@^?N;iV=+_s2MQ3uTe*JSiGVP=mxop7!U{Pgvu@CQtiY>Kj5IDf$qX z!(bchGsER<+gWIAQMpV&s;?LB2puFZ7&Wb1=@wN1X>Xzc%W8 z0-RsuIlnHdA6(bh%h?0F0-y1(z+!mq?|Gdhz;GSi1f2oUi8XWa?{d~eSlij?Dye~H zt6j-f7n`mANVdAfY=zB%2{pXbXk{l@3^H1{Uy4t=Og$C`8!e0-&9fL{v@l*&p2bk3 zMff#(bIpdCt$vWZVgduh%~m^-tu8ZL{g`Yu!ff?Zveihl)z8URqs&&nBwLL(TkTA? zy4+}G-n;2uOIH{z%zHOoi!nwE^WII@;!2~1dGDrcG1h3oh0}x{bd}M{ynoXzXPnW( zynoZRxY}r8-oNQuTw}E0qHIDe5e&TREvveorwtF6ga z#b&E*$yO81R^KOEO)^@U_iwr_JlSYr-oNQuOfg!R_iwruQ;inp{hO}EG@}Jqs1y3# z4Mr>T9!|HM5~GEA52tH!qtU{=htsvV$!KBT!|7VwY_u@%;dCu-FieJh4?Wu~t%b(p@&^fji7m@a0zgz4){-(b3w>6=WK zFzJ-* zx`F9Nrk^w2#PkcMo0)#ebPLn3n10Rl8>Zhf{f_BYrrVf)&vZM}ADHf7`XkeynEuT4 z7p6Oz{>t<>roS`Y#q5T;d_R%Kd^X?3PGm>$ZsCey>1)?!+lX&t6@nbu=^IMXAT z)@Ry)X+x%sm^NnGglSWzM>1{3)MA>;G>>VDX+F~eriDyxrp=ii#k2*}qnWm3dJNNJ znYLnj9MjfJiB&qxGChT9C#Id5c469;>8VV+ zG40OuG^VFB?ZNa6re`uei|N@+dou0C^c<$=GChy!`AmB=?ZdP$(|$}ZV0t0biHVuCDdPBh&<6tgo)~#RlqnUu>v2gaoOL)I|SmV>QVao2bdY*i=pN z#Us^JUu>qP`J$z6@WotJ;){9eMqf;+n|v`}-Rz46>K0!tRJZz~t#0$h=IVA|JWBn~ z7h9-1eDP>?r!TftclqKm>TX{=R^8)^t<-d1JWk!~i>=jtzF4I0_r*5q0bgvZ9`wa_ z>LFh|UOnuKNC#Xk#@kGVvHu!C?X8312sK%@#naTYzIeKN&KG;A=Y8=E^@1;+spk9Q zS!#hVo~>T=#h&UVU+kq8`rHjw`_LMQW*kw!eDQ7YC?izBo`V_r;6V3SYcLz2%FSs<(Y{kb1`#2dkC7 zI7Geci$m2aUmT|1^TpxneP6sxec+2D)M{TGsn+=7DD|N)j#g`Z@pAQ%FJ7TO_Qf&k z6JNYied>#2)n~qVm0IVEM~b6=LToZpoCXkLQ<36)fDoIA6ek9R*fgX#Lm=D$$f*M1 zMnKLP2tNnpbh_ zLM%@x&T0s;?w~lmA;f}$;yi~CD+P)Z9zrYuD9(Hce+A?ei10T+&V>kn2jrxPa2FtF zM}&U>a+*ZA8<6uQ!ao5yaU$FU$QcyjUO-Nz2>$})oQiNCASYLZe*Jm~d`J$Pbusl19i6m~gg6STOgN(>g$W8R6k$LQ5X1PX>}n)6a?QX-}622j4c+ZQMSJ_Jsrj8q_~knEbfESG2TLY z`|7fm3kxymRWk8VCv5>w^zVm$bm85>sy+1O*M0{52V(xGi@yJPlySKwlkckBLWzXN{hcwr6Cx{I+r-c2eB!?xZLbZ&}Akl3hA4E33uhHD)#0Pu(67=itWsl+687 zF-*xHmDBu`jC&%JPsz*?7vgEQ9JpBoSUx3lg-rT8*`p=3MPj#^fpgaQ&$N>8P5WY^T2ZeS9{=jfNMPP0>F3=%m=vE0}B8q zc;H2V>pbuh!1W$j2vF>SmjNbv;1z&L9&i9Ad*D@oDIRzYV5$ce0ZjA2Vt^Ywutb10 zQ9k0cSbk=kRotPr&;rKLWqKiTz*@L1r32L3j`6HthpQ3~ya8~d2bKcdN`N~(@Gihz9#{o%w+G$>xW@zU15Ee8 z2LShaV6^~#fhZ$3*1*+$o~yM2cqh;q`$$g9#;PklEp$T*Jq@=bn!={MVt0dBL9w$z ztf<)4AXZZBXb|ft@(;1DBKr{QDRK|-a7E@J9-+uP#QKUcLu{bf01z80(hsqbB6koQ zD>4VMi6U~7=;%heoy{|n6j>qNLE&lOzOH-T!^RdSVa+lrLHr@VJCZrr1qnd_;uYTxem_y zHA7v?H!XTnPKlY=Zx;=m^!DgIfebnQgPfK}AoT?PC@>atZ_TqCGYZ#Z{@E+QdxH1{ z{DK0|Z0?CnsMsqmq;7lUz)*mNin&sSPWCgB+D{{SN)n%szeL5sS^o)wU6k4r|D(;9oE=uqp(#7pX5C7yry8;i|+ne`7;-GMykAK7! z2>1Ay=auj;ihIEWSvgW1n$*3eb%_;MIbPhP8jaFQb8ljP0omd+H6I0}7BGF0=}Sx( zGJTopD@Y~gQm6zT$8IIMMJwSxWqcw9%})ql4#I=l>y%Hz##xjJx~SUO%GHBSmuFh0Lwj4U4Zq!pvh1F zukf|*P{(hdlF2)5y{FXhvnEY`tnx9^YT2zM;cX)rmX+tQtYlKtUh+S!RdFAwA$2qK zp+iys6<+;oqW)u9|6q{d*U@c0y>IFbb{Jf}<+-W_R}(XJRU59}_FUBgc*g^E0akjT z9>BXEI2>S=2aXVsc=6@=l>X<%S6^Hih--l2-t&rUh~jYXcdzv`q79EhXK^*ZIJ963 zzwzL5F{ZWEN7bdM?Tm;0Y#HZ>P_B#QgME3O%e!@Y99m$%=ZGt_AT> z#d{XSnu>QUh=(a&Ob}}+UP=&aD_%$t>nL7E5bG-TYKZj|Z*ve2SG>tVl+Rj$NQm_n zy9UGtigyu+4HfSK7SV8#)LtWr z|LAV+YPXPsgUsO3iH>UM{3Icf6qxK*?$+89*rcof?2{KfK8 zAgg#eUMoaA%2&Hk?c(AJ^3kfI&%J7^^m zzVOOB(O6#5e#%SHEX7iV)b?U595Y~nCkxbR)t`hCZB|RUd*XI^is(vD_*ANa2)$oY zu4g!(Aq}#!t4e;i6tf)Y3xrA8CPnL@$d1)1R&*E1VvB}%GtXGRW#QJAK15`V8Wn90 z+;334Uhq_N%AMNi>YAoBmUFvOG^kqt$hSS!YIyg*bOWFb)Y=AhCJl>NJCcJRw7Ka300 zEwjy*rDB#BrCXLVTjsNfhhw+U=&s4wx^Q{9+T- zx)_TN_$M9enOdoZ*QsG=p4zs^M@;hSQe;aHtombka?AqQQ=e)?8%ED*nlp$A>WemY?>7Ig40 z?2KL%!=wn=U$&b~6!JIxpi4ez{w_P{BKF7MeuEpq;8F}uE`yPPrQ7aetYOa@br zU#$DB$Y_?FV#!jG%K>vzye;XFKA9q%aB}4p+IURR^ zP6x!Dj*dCI`T(63H4KiXEm z3l~r8u%&5Mac|6~wc9B6`>?*j=Ra}Jm2cLHKE{F*4zQ##QpaB^>%L2T-~LR!<)rGP z;Pko!bUMzhe((KP{}#W9;BN`&)h|B4k_O9T;x4`V;mTi2xeKG(6X7h%9)k8J7JmkJ z_(=y?WO3vD_af{&!oOIeg7U{y{5fb3A*nOj*_SapGsJ~>dX%Jy04(f$BJ5PSQO4orkd#4^gCrZtzfzk0 zcZ9pg#mK5GSq{$1NK>l4ut`=+q^Rdi$v+0;(qimb!@ppZTG}6+7M~#vjDNjKvYL8) zWR0<^idT-`a;KH0%I}qXP0RXS#+~B#3Gpk3C*8wS?%`=USk(fvlF47@JE(DqtdU5K zo@R|^N0l)3npxRFY*P1@@*mEhiK<}QCMsYfqB2)h9PolyC>$^2?K}R7`sWxg?{^qo z)JV+S4*8PUAYhUc5F@|Gmf^b;R-ETuyBNKD#B>;wVX@M8FlLwV7D=gcn_@KtEe9Z020S1M}iRciTuD}^~w#+5pf zmGTQ&x!*!$^)TZ?Qf?uPU+Db+k%L}grKlOo=e=t+PUC7Uk(YSEwNd=M+v(8jX38!b zdF9}B)SNzvSHiR5r6dlk>saxQJ5%yETC;|4}5~0JOC^bu?8QDgdN3ZDeavAL6e7g9aCiooMNmqi(&(rlV zMfdbJlnM1VA(+*NFD{W`T~_hbTJ9yniMW;ThOoGiR$%ebVuFA2MBHmji2ujhcK}9F zeE;w6T|yubI?{wAcSjL8Lx2!aB)vBYooEb6fM}X26dR`k_5wESqGB(AiXB0)7etUM zf)qs*1-qj1|Ge4VcYB-N_51z)e^G8fJ8xc@H*d<$%3 zgG9~a_8{Fx036b?YYT;X_OFmUXb5}iYux^Ohv-Qh${dHm(Z3gN4XvVg`0c6Tw|&BH zVcHQA;m~GCx>eMFYtLtBGh~bv_jk_RirV7Hb}R0q&fG4Qn~G}1{R6mPrecLPOPUq- zO$;DedYP;?6497d0vTi^^w9~V%SZ^)AythiTEQ_=YSYT^FtqaH=6r@${<)!*|41%q z(aNJlM->NSQ1Jh-mH%Yc_+Pa0VbCOr^8Nh3OR;U`S{><4@R$E96^2%>)wHhS*Z(UO zhE+2yW^@(5{a>jttnq5mr>poKDkek?5|x7%{s(R?`l>%ESF16nQxy(U!`r4Vcl zMxhcc8ih(|(J1JscHcxn6hU*s>kkWrITV^ma(Ln5WZMW$2IR>0#6J_F(GY36jL= zfzUzV&_fcBSr|~TIo^{W%w#fM{OpeaHa{uVfvh40w1+>EOco8l6D9xKqhC~XVghq? zCXSZlXPmx(u?O_NqZ28=Q?@TCTjD6nHb`WK)4L)~ltDepB_?NsL>3Uc{fpiWLhqP= z)4NgV9WC^V%n;q(O0UQQVh<3p0WBPW+g`X0D_4+CeTa&sHQLZ~8GY@Bla0&Ry-9-6 z<>%q?;kci6_`Hc{kYS=`PDM7cGpepiokx#QMz@R8ESdtbeWxi$c;NheSk9IY3&`|5 z4p^W(eMIrboGBa<((Y+d%t4`Inx6u=&@DG%`~AC|P=CjAT5ie4{=1w|r^a$xZqR!F zT~4UyVmU3hYkiP|s1R<07yWeW9wgcoZU>MSt+5$m8I*yP(KSf)8Mqxpx3t8mK8S=4 zD7fU}9(^U3>{6!n=p)Ip%QaoSDka+W9J(ql_qpo5yHs4;$+BG3Ln`&2obWsb8COC^JEfhg z9n7A9TBbSXAWLLElvDS_VAMAz?WSMGu2Xf_? z%}cFou5Aj{vsae4fuI)NV3|wQ4+OO8sS9xTq@q?=)l@ZAHW;#Y5aFPJTHMr7RXfW- ziq)m;>ZMEB-pj^}&p>D)V5}}+M64>HozhAf8CzOdPche6+*H?4HcNyphIMa3tOSck z8?uhE%X)^$`jeJbmXF0srO6Gm@~Rr)9FFw*NNNP%gO*oUURDi7OlmDk{T)adbqzIT zMlRJMM?gY(D$8mNTpjiDoM6qrJ81sZUi{CF;v>Dfzg=GYg2|xS6zrtE=D!^^$FSyT z2hFWPv+-LiknH`|gT;4q5Z?tfn}T(+*WAHTb3fMH$3b&%d+|LT#h=FF2RMlLgJx4O zubt+03K~Tmiy!JBez2pA(JUjuLBc_eJI!M1)Sbn5br9d#QAR(O z(Z@kXZ_sQ^?CB_e0E_oIh>vxY5yvuy+M6-hPJ}EE0?DS1WMvqL79&tRk{w2%GuWg= zd%X!xde5}hJJwlmHtWqmMw=Q*1IZ>_Q$VtHMGlA-uE<5QgDWPmNoU*ZEp*a5(OT~$ zXT9gK-gA)A#ud{+vUCLv#%0!eXE^JvV!bn+gr9FM`~qj;%`ChD8Epzx@1%E*wcfeT zdM{(W7dr`GU@bi8Ec|U2z9BqgSSPz4G@Amy0g`1c%JSk(GBqGzWapi-iyjd7rV-pCXqb{=HwchFkcM(csH z{40w$#Q~NPe`cCN^@VuA6oY7Mzdreh^xLa;gJx6F3P>%iQdim}ker}P=6k1HazA_Tn;bOXU@sol-_0_XA)k$fx7&%3wVE#?*`Vp&R*|Y)@$83Ut_w3KQ@AB;g7eF?BI`Y*{;LLXj6q>fn?*VgCIFo;eMuD znEV}x7A7A>vV+OLv&p|8qm5lZv0iIe9%s6RU4MXRVb`BXcCag|zdlus=x^&v7f3cH z%OE+q@}!f=t-)+zavLN&nB0|3?qqLQhkvmvhUpfr>;|HRU8f+~!7e}B6^o2EQRxB6 z#+7|Qa&l#FrdycYA4Ch22O!zO^GIx3FtCh!%E@K(d2fDQwp` zWVCVRSdeT?J_95tSB_@7g~_QPT9}-MWCxQA*yKE9Y+;xBNSVWWO|HZvWfs#6HmQ%4 zvQh}5g-u0BcChI@w&@&Xv~lBfkXo3lK5I?|$@b}dGKfw-p2&1VdGrU-G7v4wGXu#E z<*DQHR3oE}(dUC?YxHaoos6EzbPJ>FL9{UXLL@sFeK8w74;gJLVGc-^<)JC&CDwW` zb=JF(^TSX5lv=qfMc%bJDxSTJKV4y?3(S+nt2pWi9+}XW?sD_;cYI z!`A0kfo4}>|eZ+bz&0Mf8toaiM%^%x~|IktVJ{G^nLHuseYzns1Uh{U=Z0f7EMWfG{ zZdIe-v1Q*NpP_pQi>0qYv$5tLacrMV6XkCy>wam z1w@N3@>e7qd|-YgJIN;fWv};7C%w`DOT99Z9rU&vpih3=Afru1M1f>e5s@I-G-_Fi z0nx%0?UC$YQg=3~tG(XNPI`M->+R{RcOdKaBcqKgydc@Qq8~_318ZNVw}?qu83dw* zt4>3*gR4fe$??c&V^a^;y! zw=g*aL<^HMk?dgdcs98Z8Ex#!XT8?0%w@WTUBw_;*fjyk4tDJts5j8<1H&?g^`f7F zX5;29Ahjq?vgqPAgJiRBjfJcIta-14<~{b}cRPwd%HoeWh(8RPO~Jmh*L=`X^DnIV zM+eQv?8SfYC|(+**Vx|<;!l8PQ?NhmHUH+QIf^w$46=_E7icyCA%kQe5FJ^3jDz^L zpxG3xjh$vOMLUJXcX1Hk$x()fWt{3DqZep4CiZX?-=D>M9mMx@lyN%C7~&w~G|+5J z9Ox*1B#V!C5Fh6#<1ChOhP@f1?L^4(D3ENzNLI#yXweNOA=#lD%x04^?DeKO>CLg$ zo9nE%g!N8EMw=R$43bTYnh27uE6xGY!WHKt*})aF*rW=3y)&Hj&bHQD<*c`v^)?`* zjVtOwvT;Q%NVcw+1EPg1<|5g_6+t%XQhU7@JL$dLTJIIkdaq}_*C3;fE3N{`(iOCz zaf7wq8=dvu#(I}J3BTQ1_#Mu|m$UHukkO`4_c-Z&&|2?9&U&9GDI*PMi}vlhPIS@^D2jV(R2RO`megr-gNxVF7W{QARtK(Z)eW6lgXkMuKD+RKmp0EWU$-_!vhS zy;(*Ndoxb46Cul8L9&T$SveI%ixH>~k{w2%0c?`bUT>_E-htM72RZ8<$$I0F(WXY? zK(ee6Sq^|?>xu*rEnG1Q$queaVw1+&>pjCsZ?d)C6lcA8tT!7OZCsHFlBFwXFwVEu zTi~pBBI_ORBz%&!@X5}?%UJli$Y@ij5+}Vgto4>V>ph?K&T+2a@jd%6KFQI z`4LDqKKlTq7R$8wpafTWZ3xZFMG@WWX;x= z{m%3jmdT16=GgfxhK-JPFuFBpHa=?wl2fM>!SoiE!Dpwk`koHzyMt!qvu+^SSk?t3 z+amy-Ky)&@1JhfWEh~LMv~%cbT%rNUWfz2g&}_{1f@EuUKM(Q2nEW1_{5CS$*tL=MTD$U1rd!zcK8O}}eSl;K zyLPf&+mO-5m0LlwG5J%FoLu<{(=ANi1)_z?yOHc*@>gu~0c5nX>r2*a?aIAOx3KGL z5H0LFjARG9eqy_hA)}35-?Lt8yS`((ge$Y|4A zP6Nrtn&!zMNYyeSPP%%EWDJ3mms4}p{6GXAD~rTL79(fiDHgvKD3eVvy9pGXxf$RuY>C zH?Zbw9W-BUFMhG3_+>2qHV5&yfM!#$CH9(ca@4$>HQ(o;`5t@mcR7lGg2g|Id^X0f zu$TUjy>wZ55=4vU{uGiOn)?fE(rSCXE1mSNvDW*dv)&D?cO5d?xMD3xHUat?NHzf~ zD;q(yaK&3lc5ubVY|;nzdf#)>yUAMbC(e5Ju-;wBXyb|lwrWrd!zcEr=F&eTQTRyZ&UmenUnZSN;N$jmbZO zS zLcu$x@t$eP(@LoYEktURu85R^pW{{OZYkISqU%7GvBEJISMrZbnGYo1vaMXi=we2f zXo#$B0+y<38*2@|=p@W-Ad0QI^N2d5tg#a27Su_L$y$0Nc5^!yEV%+y)slrkswImU zEoO9;hRBiyz}A*rN)%g5t|Y3hB}+gR?;UsD3e<_-K<>H?sH5akT&~+W?G8Q7eW#x0 zzKhfD;k0`>?S4*sKu=Sa>uJh^oc0Ki>VZdfY+W1zF@SM(LP3BGTP7R z0HcG94l(+Q(btR)Gx~5^qe3L_UIH=_tfk&Id~iel87Q5#0l zjM_44$0&wTdqy1?b!60uQD;V77TCoqtT4U zFgk zo>4KQ35+H(n#5=_qbZE0GMdI{I-?Rs=P){#Q7NPI7?m-a!Kj>31*1wvGa1cdG@DTs zqw^VEz^Iy04Wn8ex$A&L59g}a(_9xaYGBmJsEJWCqd7pTl)0QXkI{UlUIe6$_804E z$|VB16q-NXh~Cb6{&YQ2>gp>S%4#bN)4X^w&AV2x)znm0RFyRueq05wHn^Hdw)3u~ zL~WX1Um1FfdvFXy(hs8O|77^tRhVMt^yLnjO%Jf*D$)4(RGZjXLJLj8yVfi=w?Ps7%gRV z3!_^Z-Nxv4Mt3k;#^_E)cQLw~(LIdrWpp2-`x!mJXgQ+?89l`4VMZ$$J;LZwMvpOi zoY51Eo@DeCqo)}?!{}K?D;cd~w3^X#jGkxo0;4sIUS#wVqn8=I!st~-uQ7U^(OO1t zFj~iGJ)<`nZD6#K(OZn(X7moDcNx9M=zT^XF#3?uM~psZw29Ftj5ag+l+hMOTN!=E zXd9#LjCL^E$!Hg&-HbkGw1?3bjP^3x$LLE&`xzZzbdb>@Mqe@dn$clK-!MAD=vzkL zF*?fVdqzJnI>zWYqaPXl#OP;6zcBih(Qk}?XY>c7KN+21^cSPQ8U4fPBqQo+)t*ac zq%d+Zax;ox6v?O+qbNqL8MR>)&8RJ-c8p>ewP)0UQAb9d7|R zk5L(;8H~yqRWPb#G?URRMza}JF*={o1&pd0)iA1MRL7{E(S?i}7&S6#V${rN4x_n@ z<}sSj=psfJGrEM)rHn3Pw182N(dCS;V00y;g^U(4TFmGwMprYshS9Z*u48mPqZ=6A z$mk|UH#1toXepyxfM^0Q7CX_WTTj+6C5p|Y8&hVQ^4>@j9zE7meCuG)-hVo=uJi&7;R+q7NfTry~F5TM(;6t zpV0@5K4kO}qmLPFV)O}+c&c-422!5`KNU!U$G33WRvkrr2BfZ+Z39w$zn#$zMmrhp zVzisl=Zy9+`hwA3M*A3j$!I^L1B?zbI>hKJMqe{J%;+0NM;Lv}=sQM78GX;_2S&#j z9cT0-qn{Z4%;*BJK52JpJVi|cE`55^b^=CAI(LhFn7@fvwFry)ihB68;I-OA*qhXBV84YJNg3(Au z35-TDN@O&e(HKT&FglabSVm_t8pkM!Q8J?xMyZU_7^O4HV3f%yi%~YC97ef}@)+ea zDqvK|sEE;*&F`5h{`cC&0MpJbZF^$o59l1+@MBnK?htau=N*SF8 zr1rLDjArQ6h;l|1j4Bz;WHgJ>Y(`a#&S!K1qiRMqjA|LxF{)>DA)^LHjf|QYH8YyS zXfC69jOH`Ch|$H2E@5;jqstgAU=(C@Iio8WUCC%6qeYAsGrEe=)r_uTbSCbE=IchPqc0fkWwejcmyGr^I>6{4qeG0o zV)Qkm!;HRRbcE5jjJ{)Zl+pK$eqeNr(Q!sUGWvG2K zMt?K*7CU=+!y6{9Fdtr@jp6wRnDqjrp97`12Afl)_Bofvgy z)P+%3M%@^l!l*l=9*lZ2>cyxxqf;66VbqtAhfzO9v5dToe2n~z`ZF59Xdt6Oj80=T zn9&eMLm34aoz5tZ(J)5wjD|BB!Du9-1V*D6B{CY#Xbht>7@f&zETgj+jboI=D49_T zqf|y|jM5opFv?_<#VDIm4x?N~d5rQI6)-AfRK)0PM&lV3Gn&9?BBM!+CNrACXey&= zjHWXxVRR0oa~YK~I*(BqqZy3K8C5WwM zqS!1J$;$mi#l~x01@>t9fS#<}Md{hK6_xX{8%GX{4;?j(la;#-v|;gyVYK^*Rz-X` z^e5p)J@SX|Io@O7iXWK}#&s{z8q3S7E0b&Lnrn?e`YpDJBd}fUmfa7sh{BmO8!M45 zWU>1pCZ^!XVMukb8*Mndv6-xHIn%Z>{=*ts6a1%c3pWFG5~m{P0IBEx=4#$`x#lsN z&*&mX7c;tq(WQ(oW3+%#kkRFgu3&T}qlJtXFR>2WlaY$B{?{pA@fOuF4!I4X41rR+fQqx*4n93S2pku7+saqC!zk@(w z*V95IPLwLo0I4zdERY&wD}mI_x>bx;GkT8E^Ne0#w1&}(j9y~&GNV@*y~^k{Mz1qk z%jgY8>lm$P^d_SXj5acQi_zPR-eL4EqxTrS&*%e2A2Rxg(Z`H70qODd1h92HJw_C} zczT40PVw{^GN@;Qw*$46WURFA0E(tw!nG49O7s`IfYjCS-8yo8&S(##FLdPItD}g0 z8loWk6xg~PpAf~yR9V@k@}a*C^>|IR2cY$vkqGO<$kUfj5-Z;T>0y0{ILj(38Y&wb zrK_otphOam^c*0-0{PEcao;898`J%7U!{QX6PUKWqcOdm7kq1aEct1w5 zjJ%9|jQouH>&QI-NGvD02Lh>!_k#o#+9C&Yz9CEkJPI*J&@C{aZ?f;*bi#^`D8GxRj~nHr){ZVfDz8pA}Af-Vt2t%zh5a}h*n zth&e;bNvL1izxW=L6fm^=?f9iL?oKIlvY>by9tI6K1o$5<}{&L87O%ECQ37oxN&a! zVnrvCgoe;u-4r%2X|E}V^hnHPfx~$v4Yi{`&4`N-CPmFDR{>F|!#nyQaE^7Wd_4^^Hw+wUt9_${Nvl zOKKYDl$Xp)7*R65vbqv;xDq`>puS>;)LrT=ohr5JdREYLi)W$dCeKr`uf(p3{m}bd z?19)9Vpn-L#qN&%GBiq3>wyR^Rur zxB7pGJ?T3ZyU>3;_IK}(u{(V~#lGnKIrb^vZ?QLe7kgj#E%AQgd&s-q_n7w<-!tCD zz9ZfjeBXKB^&R&f^)2+>;CsOLhwpLUO8+X~Zr^*pb^gu1>;2n&`}})-Px!y|ZSjBW zTju}8_qP8p-^>2X{rCH?@!#&h*8i%1iT?xtz5X}-5BfLyAM$_Zf7rj;|DyjZ|62b+ z|9k%J{?GkK{CoWS{a^SG`;=&Ec4v$x!?1E zXSwG=&qJOSo<}^7d7kt<<$1=l%JaPE1<#9~S3IwK-tesRtoLm2yzP0%^RDN8&j+55 zJRf^L@oe#I^=$L(^nC8w>)Geo?>XQ(tH*l%&aYx`Z_@8*8D^t-Fy!~NFw+tqJ> zzhnJ=?{}i#$$pQ@zeGhIj6H;k`zH2C?6hgC%($F=_J{Wtn= zMu6OkP+8``%YP37<$nKigvvt*lSllI`JeDV<$uP%5+U=ve+|OsWdzjg2%U8ZsEz)& z{qG`#KJb6!-{jxy--6)U?%(O(jgZ=daN38UI*33!i~u|CUpC;tfR_e-JaE&%PY3QE z_{G4z0}l=Sd*GFWjt}~A(7w~w4t`_sy1^RC{h!4D33a>%zs77krB^ytvzLw_9l z=g`H0YXjE@ZVKESSQ1zoxHWKlU>U;n?!di)`vS`Y4+T~P9!1DL5qLWAEW&m*g7}5N z8iemFfmZ{s1zr!V4Xg{S4{Qi*47?S1C-83I{lEu-j{+YDHU&NjYz};iVBZ$l9@r7s z8Q2y0Jg_IQH?S|TKX4#$Fz{92>%if_H-RI8Zv#gI-v@pO919!|{22Ht@N?joz^{QG zQctN{@V0J})IO=auBJXvRqN?~B?q;XId#>6nhJ?JEj1;8 z$xwOIoJu619|xCw8Nsl>KzUWQZ{{qKMw~8r31toY6M1G;i!>KLU2@`gVHt2E@>JD| zWVgr@oM4#;Gduc=z(1G#?89bdLQdm+kp}}N@;rQlxG{W)Jm^B{uND5eMs$PE~$S;hf@l&D68>gAf?eWa9(1< zppyKm@`k#`x|vO$NmY%_W!0YIrsj&Ox{~;~VWUe@>uPG6Ypa^(mrP16nNU|(-B^-e z3^;5=AbxaUc-*kz!%JpV)s|${H8xF2Oc29vd3>Ovx;oa=1(pq^Q~MQF)zZ+JG@@_% ze&ZW0#&7fZt`FDxcwW{}KD&g3<6rWG3G}7bq6RTf50pzoEAVVSbXt`(bh0#D8roP< zolk2}Lknl&Ulaae1~fE13wiPIo5ZzKQFlbuWGvLx z&29ALRy8%242vttt}U-_uBZeI#0BExt0?D0bj2@Ye1ms=)v4xx z6FgT)79!s$8g)kMIc@${M(#N)V&j8zJ5~R8B14kaFF&#ItV`369mzQ~de5d4JvwC! z{+~)+Q(049Kfkn5nCC9>Zn*zpZ_%A+oc8#nhkm=T(~kd5C`ycGrFyZ?9Tgic|M~2N zf1jE8#M6&N|IsP!zmsVYb^pAW8{)?l4u9$G?!_D4%j~U4t%9=TA2+TvHK{Z%J}Wyr zGczkEC8_elB>J|wTXsFL0?#VJJLorhOlfb(KRl}-E4MHuw59L&r6$ix0}iuFfa_yfHj4wIq6BYvuw7rrdfpnXHL7@(p8M*nH>AAT{ zY`rPQ5{oQWgL$dQ?x zU08rWY5=wzIR=iAg=uMdS!p@R)CRa1CQs!V8B(%}l5;Zil0_@fOJQOtFfb(Krst#< zz_Vxswk8!B88Wi+b8^y9d1wf>9ODffiJ67zdAWJ%8ERt)g-C0)I^NK#V}gMvp(rIY zvnVGkO>GZ)K}^n_WZ)QCm|swoo(kupAl!gVC7)ts$VQO?PElHJUO`&2%6ieius&#D9hH@toReOZmy+a* zn>Wsvno(UnPb;R$K`RVgiD?;G$?5q;sY$+Zqs@FK_dH_YOUTYi&dSO!C?q~rTeGIk z6e5osxJKsXWTdATrl*5TSg7-uqGXeSXIM^Nc2Qbd7Q8uJ)1atfdwOSeDF4KmyD%*) zFFg&NG8AN6=ihA1UzD4foRwObNBMKC^M7H;KQcWdH=`&mOUTctY#cY-pvP2-5toN1 zBnjZjOHE78O)@*#@YTa9=ks!^$GBQ0sH={5sUk?I31Wcx- z8(4udX4C3OJ5oU z#OJ1G7UUJ6C69|6H&V-Q8V?T|@{cG=NlDJk&rA{dDRguzO|JOLz%(o~B{R7ouP7}k z&bnS3t_;=B$kd{gf}HG}?4+8yIdjL2(l|_RYcg;oVy2d!o}HPS)KFJFZj^7Bp(v(? zGsnO-B0W7PFD*GEJ*j$DBkM60W1fLwWNr?^ExE8Tsj<4Ei8)M`J!RlX$ji?}U!1|t zYADmgz!Yq+8o1&yb<56Armklsb$QmcveUpZEHynZt1vf@+75TArndQ&A^*tyO!TQa zMbLm+r&?sYOr`nOz?G1XK|4DQ)u?k-GMlM5#|>;F3$s(xG7ED7hVtY@!AphY!7XFjeje1N-n)%&Ri8G2O4P;F>Zuq`!^%(-3xr1!+Y|^`TfW z*tkm?RMqBv`-Z!8>1`SV5PEW^>oRZXNE5D;5|H%C0^vtZh6t!Ja4OQro zW2&KU2Cl@^jO>iu^z3{wXbo$si>G+7Zw@_-yt%pg85t><%uvjMcZ4%9nMOwY>B$xSWH5)Dsnt{0K{)&U-GV2uY~ zQFdx!Zqf`6P*cY{DlB^;@)yEQp?EW8A8pKzQK2ZOC_gRfLObba7_tvf$T?CpP!zYn_ZNh)EqL$lz*Hte`ao8eokguQgg^0Q}$$I_SDqOybLs!=Fk9O z%ARV-9#2nDm~Nybg|eG`lV{AHk0-jKoOBWC1$Luefq^3-GYb!xc=A%KITU4DHJf@r zdJl@;@DoxqatjOTiBOG>@M*7!@qPniUQ#Y*5c#>;En>?MrJ8BbLF!5jjq@8T=T+%zDPd1IoyKQI4h(xoDYWQh@liaN^@h@txS?+DQ1h2p}8J!Mhatio)|`B z12Fh7wCGHS*;KMoGq(ae6s79nB^)V=h$7C5pz{R+%@O!G2a03JQ0V;$BFbl@NL3Z( zvo9#EX04ZjWeu_P$2MQ^1+c`vOJ#E{=`L^Vp&afZ$JFT+1OKwX*LVN>5W=z8P}7HA4tZUkc@ed5!Xv9 zoilT;ran}L?ofOKF-^jDVem^ZokC@BEA>6)j=kiV)G)qAL+Oe0M&djajgMEb0TSZu z4bDknob@Kon~1Zi9X@Wsj$4Rx05}Kt7PhLT3^(;=VtcY5K7MJ-Y|TC8*xqu?Sw=Rq zrAvr$j29mtLun7Sj2ffsROoB0ZRwoBDB@CL95)OfPopR7PmB@doK4W!DV))$b0Ao6 zA=ZiU_?UqWyaB`-Nvz+3HAArKD$5PtA*HtxXXlal$n7RczA&ZdhH-}6LwvUp-**Z4 zSa6CYbrpPa#;J15Y%rmWy1o$CFmT;YTrZEpN0083)P=a*^10x;HcXYVc%koYsEIQ& zy8EFm8X1jML5$0Z@wQp`$UwUawf**B>>f*onrni%9we?0FUH4XqnQhiX&(za4P0h3 zA0oc#m*V4c#A>MJ6W=l7YpiYImmKJOnE1}Sjy{r%4gWRpoiOt8crX=QD~M~(_4w$T z%x&oySR%a=YYO9dggD0GctY@2aQM|gf&WQQCokF8!n{dP^eC~NeIq^sDPf8R8F`G( zph7)HTzhW9N2^q0%X<&Xl8ubUIwQu%iE+&me4LSHWIP1M>4H)BqETfLIG-TSn{L5J zUAnOs+yTzZ1ZR1R0v3bsN#Z-_c6`jwG&WfB%S~Z?Mq7#VDdOz93?HMijGSca9pRi@ z6D8n#n)qVx#K$V|#ZXNs@=abj=Hajc8ar!p%`?RI5wZQEs}myx8TzJ=D$pFxGr;vM zapgUWj{y^mVfnI8j@f45GP;xaRubRAmH3b*8v7OE+v`J&X`KU?tP)JCi0R!`__zp6 z9jRn4c^fz;FOcx9ol-@Zg6O(5^S)V0VUgzP7|o+o%fdh$^(Vsn9N^5_2OyB|I*o%PZ7g$E$ae z)Zx8Ja`zm=ML=KNdnf8=jv`4JOjAKO;6SHf=XCC-zB0Qw~pkz`V&|PXnj8L2S(P;{8 z87s62tiLzZ^4O8yBtm!9QrS7&iiv`ZoZLc8Q**b9g_fh<>o0TFu7ZFk%ITJ@tk%^@eIs z#5Lxkop>cCS5uEl8(%rIvZ1oJyfUmMenzDkT>u--Y6f~m9W^_PI744gvz#5%B92aT z|2Qo|p00#Zk)^_-ULGY`tf_c2?N`qfZr6uyrl2-L4 zZLcV4v#6xa_yxghq_PFdwF{z_E@*w%f_4usX!pc|wyPIJzp|jsn+sZRU(kB*0{QC& z(LXF`^V@=`lM57@Zn$YoR%pOgEnbrLy7o``ZPlj&nBeb9LWg^my?bRa;XO@4*;?On7D-<5XO zJJ5EyLc8Az?PV*pHLcJFvqHPZ3T*`|w7;v+rmaGIux{E+bo3=OIv`wkdUZX-A zhLN=Or_hF;Lfdo-ZN4eAqo&X{nL?Xi3Tt{D0u9U6)8 z_3|qE9$Z0L4Sk!?6(ylw9_fgOH$Q>)3Le}S;ovtt7|G%Xc9hq_s>Hla0>qG<+Ke5N zn&j%LvPN^G@u1F^p9Vn}c7UK~ND$SyTi%X|_@^vE@QRpW6FPzOUW%6II)bxcG0+gT z;dT+tO%c-$HQFP0Pjero(O7wOy4O~mxj^sI2SWd?WcdTVp#Qq7HOmzj6p`;_+A2|EBCdb{9Mvzyo`O1mqGCWw z1pJ8Q4mff6`*#%A_f!si~!T6R-dY z{er6CJLGQ`lsA^nOH6g&X}CmO-l9?Aq;@ZYm+mEr-nxCGJuC|kAz6*tWJ5=!actgRvqZp4(g|dpu zrn0JPD4L@yy2Uzqe$UdXx*5&1tk+pBQIzz7LHa0z^iv@{ZF**9Q+8Tu6BzDQWk*Rl zGs)NE3-c02Gz`Nc;VGJ__qC3arjO=2%E~s{dOD;<_iTnkhsTpR^x!DjOCjBf2GwmO zcWH?TF6^#cfG=j?%d>8T8$1cW;8zC0x?mPrQJj}H0Z+3AE4H*zBc4@8OeFY=~D0j$}Xa* z6*4?ZU$7}n##i~%sv7I@c&R&p>gvr(;hfYwtZEpY(+$okHwJ0p_%uV5MuBye@N04M z_{1=`Mzo2N_G?ndo1`W{YKL;tm|r+)czmPL5fzb9(lwgMJS-F#t=R*17YordQ#2?@DWGvF?OAMP=hJN?KS(Ma)Z29vQt+Ju6 zupVD-z5u-tSttcxLcQ$~;qq}P(uT(w3hRORAlJ+I{8FlxZ}jS>&SPA6`l39=EIMW6 zzJPNhJ|>Kxi16UfrUU3RjP!y$Be|92o~av5@9WXcJO^Dae#jEcF)77G$>UQ+Cs$mA zbtyPb1l~kgGI@Hr7;s=th3=zvx{uxp1zuSA^gvZVs7ID541NXevr_VHM)8F7f=R~k z8RT*wo+cF+H#Jn2)s$xAyKQW48d}Qt7$KshH$q+=HqzkLjVojiDpbRRYS$4h zy)m6O;pyAyNWD<+f$GCNmVS2W#A1U_yF%7j>W65Q5wJOaJ6Ehr7SyAlr%w@fpsYAY9oK!X3-UAyvPl%ASm!kLCy&B6i}c2p zFrqZPz3p^kYRw^m?~>s?192P`9T3EiqKQOHLr#ZoY=W0IUQks}+wpKmXWbnG?TJxR ziEbAZ8~dx3t=*faN%^VNg_mMYTYZC85neQ+H=!K3?J;PNlAhG--84L%Y#l9K69>!6 z8mM#e>IPlfA}vaKJ`~p@3}GFK!d=`m1K*XR5~<ZK@EGcqIQu{@W~Ux zstRL_Q;4H7x!Y(BxofBArxwkg-$?9IKhe|VYu?C94C}m?qac%}snv@o4Vbb@Z(kFw zlHKjGp=Iiy)lE3=pQ$VVL`230b#O~gORU0(%rSln96M4SakKKm$ERyBK9v|7qH%5( zhmt)V5Kb?j4NGrUEsc`q82wR@IU(F3y`Zi#JcqF#Z3FT8;?mx&CB_+fq)8K`<@%Yi0CV^QD8@VWJu2yfDJcKo>`%!VZ?5UL0 z81;=MD;}bzBs^Gc7d^BVCYXgTW?v ziDx`C#4M%Zs-~_nVdOlTvJcU_hZ`)@qokfix}D?GCuA5bog_y|>kNt#42n9zi0%47 z9q!V>t=+%ljEkwA@}Z7;ZmWG!w_DIw-LJK5*4l0|=gmOgt(5nCV<%N5IvIUR{WnVb ztmva|ReS!-V)UHGslZ_jAJ+^=d|^bON}Cc7=k3=+j9$(4rlGvXi99*|VV*A2ivp>8 z3(c6Rbv&#+h+)Kl-$&|xztcK-i=hFgRW?#f*`c?y4{d2t(l4j$?IUlzp?$Q00as5! z%~#H$L1C1xePN5VC@G%

      Pz91JxUHw1liI);|gIe4c9zFJ48(8N#iNx@T8sqP&- zgkhM_7Yy{l`6HC#4y>|8Ne!$Afs6@cc<*%z))1!aYfVjJsZgEko{F*NAu%hv$S43^ zYoT$h=?g<&5r&r6H`dVGoHQ$YXjUHfOEhh(rMHf$^M-|}>dz2GQPRtydN#HnJlaX0 zP%lsN;KmbRz+bfVOv^;~Ci^JoxTP51AvA8~))F=b4s7jS(jBd(UOkvNlipCEn>!cG zI|cJh?q|k_^)p@+r7Fxx#?d7P)D`NiI3+L5*bx3uqNOW&Iwz(P^r(QpXz5bR^eE}I zkjwC1&rqKe1D-kEg`;Uwi~pha`{dB{Kf^fvABo&6M6F>>vUCOxVpidVq!jF{R$7#l z80!CrVdlgGKt7}%*E@03j3^zw_&%zknGKcd%=&q?;-aKZ+`COFM0??GxIm7UT8qc{ zM6%i=te(hjPBZrA)Y%maFKaVg>auxyOApJJa~;swHPP_kMbvZjaVxx|T-8RF=Jk}u zl@_YUEQ`_F%J79{dd?3&j;S7&&`x8jkNkKKnc|A_^pm`(WA2!W)mNc58G0t_)v|O0 zOta*B+PE`@NOQ}v_;&$E-OX^_F8Cu#8oPi-hAG7p3df_sJcU{k>plaAO{*H!kfl?4 z>Ll@UaPAhIlh4-2l;Z3(JR7syZ^80cJWs#ETEgNs?k**mf$AeMt$AqEP<8gAH;ZxT zAD$Ead^*=xa-L!Ir9m`PpK@YR#W(@K8xICoY7=Yo(#Ces+VYbTW)NKD^U!~MtT$kj z#8_|@>Dt0;_~F*>F6v_#Uf#eCUWlj8RfEaFV?@~C=`A}y-|+NC_MguYg}yTrF622j ztrE85sLl)bZ?^3I)}mYDQ=_3p4?imFb5U6vLk&CLIKk;Axp!EM%zT21>pdT$_6Si^ zjIAX6DUcS1PSHUHw@Vnx!{_v_o!QK zY3@HfEoMsE`A7CHJ<@z3ynAV=RZT5UpOS5CSTCbttf9 z>dLcNh=iv~%bMuDk!n}{H~OG2Mak1d$+c&Zg0Q6-tSY}}(E(_69_mVHa{i?#`dgtI zh&Q%Idg@-x4IE3n$tifGVPoG!Bd-ao0n=Qs6Wp>v%uA>=@Bp#mFG?yivK54Fm_&m7 zdB~vTRHH=!5T9p@3MU%d(lN{p+K9QqumqYM&?1I=x#ms%*Q`s$TSxV0k3;b1e&NrF z!XRy;ApFTQ1zPHQMsK6x&+7`hvfV~ojU6#90bz7uXwqzb$~0cK zfoDF{d!5Nv$x)JWIs_FK!NF*8E09^pp=ruJx@o3a!ZEbf_a{!sFUCGlYQl&q>ho?Y zW>Y6o@q(R7mSGGebvcs4Rm+5m6djVG6A=}G;W4SV->bW{tD&C&;f6;8x4 zQ?*BLTFa+bBW>Dd;bL5CMS2w*u)cBl>Kyg}8pZTlUESneb9LOJcTu^6JrPX7ep2ucv}kh5#YUG= zScfm_d$12pyXn4hn72ZOdaTG^$wHxIzYHbVs{0*EXtwvgZoR40DHxqMP7H0qY9k)C zJN!jU7mlW9)v9`$q~z)GS=%x(N?NM7C)3pHtJdxw##y(RYSZi0un~)Ie(C+&nHVWw z5p(W5_J_K7fK?J+Xmi1&USnZWeLW3R6LgEZwn)PyTwk3>Wg22>yW4${-oA?)D@}v- zK{W4Z=}a*aV7p9v;HN!i;f_((geYl!sB0Z&+#05Jx~}1oP2DR;b`?f~RkUuV4Ljv} z=lXcd#3(6Qi%;_=G7{ zN7qLR2SiDeMdj#&PuOEBZTOBdOnT8sdD5E)T3X2Xu*u`H);Mw+>Tvb5tKy}Lde2Mq zs6(RXeU67IEa-^k6EQx}$R;I_A#}DTM_Osdv&N1j8#CJ zS_S%ZiD}#FLG+h5h1y%#^XCDSHd)k?HszvcJ02%#7(S017_FLxb<#AhEv95dHgJaHWuqkL z>LuCVGSMB|av@-*`ei;IcWI(=L>M|-Yn`Su8?T}3@{UqlAWkX=%XNi)tr9bZKj)!m z7W+mN*7(D&w`DqZg}K>h7fedVQifsTKzt?L=a$bd6Tz%*B(4kvzj1<0ryHIh0V~C0 zA*8@UviN3%y!2)0~5&nNG7E zPetE~*LqxpI9i|=?r6(IoW;`zuJFiw24mV}on-3Yo&-$^9sR3mG|ayzMMg_)sSBG| zju*H<`$AoNYl~E@a`J$ZjyVNCg!V?~MCZK29|EnWy_0iijX_|}DR2wT1aTYee>4-Do_DcYzp}3{7`3DbGZx`+HNsX@Sbr(ci zCyzHCXGj)bmldh|-moG@d#{Z~Yq1*= zc8sIDp++T@C<$j6uoDt8e{L<3**&%ae$6C zTWNDty4sEJDMZmYMq8vf1I;$7kMnrO;m3Je{`kls+PG8R7qqn@+Aw28(BaYNLNwz; zN(6#s0v0B->4-gEb)xrR#TIFa({U`htg%K!?=n5-0D4^3&*PPr&k)p(YRF-UNEC-3 zfQ`d4EeFr$(&|HzaSg1U;K9H`Jc;9;4|beWGhlP?hi0v*^Cb8ea>;SVQ}Ez{jS#eQ$tvC!)g z2**W(_>CXw=*TWF54452DDH37Ug&<^JjIS63ty;%($#wIR{CRuD&+}1{X_z46;Jv2 z-KToQ1*Z==Q**So)U#M;xSkeZ^rcq8vr;E5wkJKQ&1;0KZqylmP0%!#&S)sDpri0o zaJ5eS$%*)#J_f30zpOJIvPo~F$47YsEoZ!{=Z~~WU#lutow!`j?H5j&LB|k_^t73& zG(N)&eX{txPI*C0C2`iYvbI7e&ee%Eqsfi*uq}MJPEVg{lkQPfQ#W6r=anal(V29s z&EZX*^4A1A$||iQW@A`|tebU?mBQFiDVlV`pN0UTnGQDMsv5w#QP1$(zh$V3qeD$> z>WwLEjmjNTgrDFeyVRj(^>Y} z5oU<;s3Aj5So8*aIk#4fM|3$oQq-wFJ7&91>1s=PQLDXBJ-w?lwc&+1)hqjS!atML z79KaxL}*1*EA_iH2nBRCW7L41T{RO6S*YTAUBnlmaMDU~mrnX)l2{_7>c#E^nD*>JHkP3dTJGYrE~1HBRtKk5~?q5)I04v>kmE>%k+oPM#MxQK;?Lh31<_)Ex!D!ey93LeoZM{OxxwAfW` z(;i@>rAUf3byJth9xa{FLQ2hdk1n{K+8)d6o7HVze4|_^eHYTH1>sJe)LrFLpRDk^ zH!$@hoz_XO6ncA&6ueY-{YkA>@Qa3J_~lf*Rz;^=q)|{K=($BpxKgJ*r7n<$ob|e{ zr?YCq%#h`qby7dg1ntnB8hY33BKK?MQa!O-XS#ia+DM>Ejqb5JWvMM?iAGUHX~#37 zrPDS2A*&bZ$`@-SdfQ=T6Bb>>XmqVgZbMyID{PnHorRSb;)lrSZ6d(<&COO4y;Ov7 zB{02P1YZmmziWY8dKCwLa}vK}?Oy!i2JY!yC}flP zJq_H`Yf+$0{8|QX=>;iTQHi@i%PoHD0{2DwJ^hdc?#GM!)}p}pnF^%P+f?*2)BPlI zA1Quf0=HANTlxVB+|tWdU_O-`zYl=~dW(tVYJG7-?NGb}_fn+LD@{a7g`Pt1HxVh# zdJ4VlM5J7#r_ftUAQ*4E_v3dJAZCS{#W$2w=nMO>)Hf74nvsLPyN{y#v|IX)x#UvD zfI{D_2OJ1UuK@uZ1V}FfL4JQ_;~1jQm+m2s#nW2{P^p@w_i`)I*{0mMP7RD3ISMP(j zY1gE1x>0uUVJ**P=|V;@X@YuvVuX5KtzN@;4xFyi?5?*~cqo7H)`ydoi}sxN1JEQ?D$uPV=cDJy@stwOaFQwdU6rSJj`w zwrV5R{2P|0`FM4T>f_a#k6T&AX>f_M8>cgI`uMm2BzNg-A?xWss{zAR4%G>Xu zI^gSvTDo@iJgCz7x?iPxwCmkbs=T}3Rny07^2clPD?V3*{@M;MalN2Ky*A&hUZ0;J ziS$p@c1QSs`4^l~rOKJ5wPXD{U%S_@zO4s5R9;_~gW~$ZbnV(py`K5dLed{R^MG2O zQx>WBr@W=!XKVCqjh?B|Gd22IZ>ceOR)i|A94|v4d03!~qw7H}rVnZ{-Qudn^g;cq z#WLS(as03r#}8|9+~TUm@x%I6i(kIiV)q>_cHhxrx5ZVB*Wf$)Rf}1^*Wz_uiW;x$ zw0LcC)#7v=U)6XG-K+ln?QFHr`EB!g!e4(bQ}6%Wq25bv)OeHLSMzV}tKM(jtKR2o z@t&*2yQ0w*jXr5&RHTcG|1ncj~L&zohy0CC#@Vd9Dz?`e>i( z+vQsMmTTo%u9Z)}FVpB{8oh9es=u(idJSmh3uxsFXyw!In>GGsjlWdmFV*-z{!}gB z$7g0+RsuK#<2^&uFs@Ko8^slt5tm)YAR_X1u^q;(!3%;MU@uz#y zmmX@%-L?Mw+1u3nXFm&ye2IQFf8rta{(UX~`+EL6wEWvudaX~*U#pEXW3~Kawfy@v z`TI5b$(sCRP5u@w{}wI(OPc(bH2D<;9>w4vVdIvxmT8rm+)7RE(6d!Lhi+Ew?6pk2 z@3lj{|H4AG>Bnb zQ65wjM@N*fMHXd~MG=GmGJ~Vch^T|_l@LG{QBWkTkwtJJhz`>9)9-PP6A)m7bn`t)g4NSk`rFQ}{A;d?uLKZEaQ z@LdDnHSnEP2;Yvhr6X-A-BS83y;^NMHBI=bn}k11{)fqbBl&M6|L@8Fd-C`1T2Stp z7f63IcZugktyITFYlL4oPWXkJg?FRQZq!+kIxA9VRqCutollVe3G)Ay{C_2X68V$J zKdlfMKS##Tkuez=laa9(GWJ5og_o7^ZTex>h9iM%NuLV-B6xT3w%`%qZr}yb{|Npc z;B};r0Y3%&R^UC|tNC)=^IW~c;qT=8?=je2zRlsJpWiawFMs~1g@r?W|M>=qnGPrY zs`e%P*me~$q5vdDTxGDm>HoD38o69u^ z`gDJzmOfrybD>XP?cvkEV2&oa)p4gZ+H( zR1}}ut#(H|`u~jE{e<$rGsT1bKghoT-7CNU9Y25n>dHT7*Y20S^!rMc^YuMsy83Sj zbC?^SR6pFv9Om+|)qFi%&K#zH{=p8f{Qd#b&;C-<$AqThH=&~NR(A<+RbBX|)+PLM zeOd_C1?C??_0v~fLb)M?0bsO*u!B^hbeDf9NS9Lomy)N^SYuAW=E%TRk?~32L3d;A^ zd&1wM{vduH@}GzNH-g^?J^}eBP(Fyi3jbH32l0CJUxfaf$y_Dl$`XEm<)8iZ;j`T| zPkOeS;exGL!{M4G2`XhI=@Z46yn~Yca zCLM*ZWDc}4QFtcnl+5K3zx+nlDH~a*oSy&X9FOnEr-<*lT?F@y63l;d-KRIc-G|=) z!~I46$v(q(?3*~qe#v*h+3cG*$bQLe;0GT_#t%=GOdsDRxCdRFfQ&EYKZ8C3`GR>P zFCp*A__>qKznNddpUulZG4AQiV4qsTHv?0Fp8{`Mr#@OFzYu9uNBO_%nC*}0KUXW0 z>GAt>XZAfdb@ut^p7p!ZUizKz`J_gok6%}-yib4OWZ{*-&jtSVcS>&ne$gqyPY1se zc-Io?HEx~Yc=n%mpDg_@*rD`V*v9GDdJW)G+S9wa+B1dys=ZID{M&a5UV|;wq}({h z$SWU;e^bWR@#y6p+Pez42m0MttDf`8cQX85gyfh&W53LYnrj){bE4Y6i}qcD z-@0Xq@)>LoZt!u_2mIUO-~Q2A_V7pi=-WqNOIwJQtFYf!;MEmg^N)a+&EIX_{^_fl zpWD2=sCn~KT|V&b@Tr`LulHKdf!MffZ43$M$1u`cVyYg>ta?HbY74HLh0 z?+Opj>4JE0P8Y-#h+!h_4+cdDgxw`grEj&+N1wk(pKqYQ zH_%@q`btD!4bV>m^fQkB9Y_BL@muNNTj}2*e$y)X*C4!dk(Ir)RIOs4V&VWW?g zUJv*f<%96AqzBPbqPmn(dGf5A^X6SVY{DSbUMH(l&77Mn_6x_H(@N42_1LF3Q z^-BLRS8&U5TJvs6R2*^mKD-o^fj9OyZhSVNEjPB<0_Cm!B_Ihlle&(zBuXZJVlkPI=;oFzspKucHTpBarV5seM8CIQz>%`1cg~8H1&nk9MY=L3las48pBX%fAHSSoT{DeuvyaxCps} z@Ok78!llS<@U*O({r%pPPJPMm_lg}V`f$*UOMUn?{{1!L%Ov2_txEXxmpcg7#-8p* z54T^b^rx7wpNc;?6@Tz9&(7av-+2np&Zn^NoQa*c#Lhcm=jZj%_&u+O_^(LFecxNR z^*<>$+k<^h&;7Rt=a3f`2e2+`~rN9e+T?XIpi#doZC33vW;^p^VnaU zw?cCDhF@>wJnZrTJ_Yy%_!|FKEwrc7iuvXO_Tm??cb+ma$Jb-ZHp$nM`EO71H>P}J z@H?R20lthqrLM$FgRhLx_LBs|73Kvly_x#o@Ii6H4Q}Pkz}4)T8|=Y6p$GGa z9>`(v^ZMfRd1=9$ngW?0|DlKQKU^SKX1erIhG(!J4;21!mh|%l_!r=F28cdqk?7f} z!m}3(|Kk|pe_SuTBIPSmzTXVd`|T3_dg#|f{}}qm&=*fr{>8bRQe_1Q~>OsO+FA@Gd@_vuJqo<2Ln)W`FBK)CD<=;J2_-^bw?K$CTABo-_dAnx` zzhZ>wS1>NGohkg<-J)N{yyu=7O23D8y-vGc&sDw+siJQ{kI#cY58jdT9Vy?5@|`GO zZr9@TJ-w8>KzeCG{ubn4i=1nb^IPcOLSHaY^)JYhJn7KWp{GMnhh850T0p)9Rg@w*88BJdH6{}GJ; z?bzLR?Cu8g-$4F!@~4x35Bc|y|2*vBJlTWaSHp?2Z`+tFM|I0sk3~(21`0Tx0)y4=gbK{AH7id9F&}OYgY2p z4W29^+OtS4_A-XXRwvlL`Lt?v64SGE8RiRVu^zma~zbMU3yE-20)jem{gj% zj!W+-*&R+khj)}*hQAVskrwkTX0999%$M8X*C~c;&b*E_y1~m{l)MJZfv;mN>>z9X zbq0fU@F7F8{k>{?o-?GZ+GnuQB+>0TPor~1H+a)@>G3Acd#+{fzLw|n3!c%OVgb+Z z&wpCa-Op#PP+(3Gm}4Xk$iKrs-`)}zX?!G>QvC);PZfPMYuwSyNew=-BjVfD^N&^Y z`8?l5bI@Lsh4;EscxUo$A>S7AJx9Lh$oEP))&G}x!Me!RD>yGR8)}gyTR3incpf)Gx;+lRW6=1S&DCt9 z`DIP|p!=yO`f^-D`Zc8gv4hfs^39X%k$E4ezIh)=#|HP$P`RXT+HXoqkgk4ri}2rZ zX5%1Z*wPO&wv9fM^-U^cYUW1mOBsBpjrgUaC(Hj1^3O*1vy;@`+2tjN!7TbDtF!1? z)kHVgV~hI7#*HP7W%-zxl{JZJkS&)Mqo+^lYW(bw=Sa}CcjC$a9Cgzaar zUU881PX;iV^@@Y^dou8x);a!jhI7_x-!W^v@T@JuhqJHrFU|vu=9%V3+VM_n$+@kS z54|=X%`fuk-Qp9+dU`-|Xia!AS$7Tw_Qbe3(m;U7hO`Wr3N1=+_5?mszvwfMbZu%+zK z;j6{(an3~s_p2PfNqinRm?l0B=j`g=dERXMTLoaI`25|$l72g)xa2A7%)+;SD&d!F z%6@H4&JA?{KR^HaM9*LR0sNAzVSdc(bn0*)ZkQqXd8YiDTVJmbev_@QcL|TKuLt^k zqw8zow!S`Ty6}^BsvTbp6#hk)@Hqp7N7viJqw8(q(e<|Qij?m+LwIz(E&O`uA489> zw?$u^tNKf9l^>0+w?&Vxw}sn!`+XgFbEyCU^j1WIt_s<_Ee7-#&pDCPu0LS+U>U$zkUk~c*L49ZAf2%V7s`75v zrHrFXc^goLhp38KuP{!XU=*;t(PtGdi@27mibDGO8 zC{y3dZ~GPon>18>Z*sigJITNrg5T4>-=m-RQq|w@u@2qJI)Cd1+0}!Oi~is$;r}~D z`2P|Q_p*<$mwki*Pl-NYt@3XjEqv=5;bo|=4E0q4uLOR1MENgYsQg2~hk(y&t#-^} zo>3QiUFfyDie8&J^1sK6-@mtr-yGUMhxTva{Yu-G_&+k6Yx5wvM zTRuCuLNB4h(+x|~o`ll}a)0_V3P5-=?Io+QRy;oY}r`fxUuk`x4Sq0&XH)&sO z@mazP?kB0f=zfxL+fTZU@o^jNugLhQ$b9-++8^C-QhD2NdW`&!k^eQu&ujF5Rrpth z|7*il{x#-T>F|&4SBaiZ{s-Xy0Q{eU|1n zI*zs3IL=nrY%Y4u69v<@Xx^R1{B$w=7sLMm{13o?0Q?8Qe>(i9!~YuiUjzSX@Sg_% zH^->mZ?2bJEkG}}KezEY+3m)UL?4JAqWg6!Z~JwR3=;mx66OC7emlBDlnR%>OZetj``yea6QW_Bf`n?s=Q%D{r&su$w)i zb-)wZxBnLW&+xwp{@0P-hcTJ)?&34E8^_fNyd8q2d?a4;3EW4;60v zp)a*f_2rB1i;7-wUsUM@_eGUna9>pE1@}djZu_EhsXw|uDtf{FQKc8$A60sEe^hvM ze^hvMe^hvMe^hvB{6;e4C%Qi>`W4W3K#%T^ir$0%d!n)Yz!PN!+jiA@xh-+zBKkYJ zf2#7ff4Yb9yod3;9X}S`PgVXKs4t!Twx9aH;QvecJ(Rco)rH9#e^IFQjNz?V=Q+sw z&v46^|6u^%ZVEuwhnC)vaTmw9dz*1L54aupF7P47deo?XY&8$2ex+Ig;5+dU@(kf@`PO^V^%*OYMG&^~Ktq5smK`l<)5^3J!d7 zq0-6!ch(yN|E2tYc|ra!;U&R)*bDm$`4ixO56=VETqJ*yc!^+@6zzGgxx0j4Pa^!Q zWQzaJJ7sqcvIn;lct875_p?uNKj-D{XFirk`xnyw70=c4>&ZjDg~+#pxNjjz3`tw`~UZr z5`O(VZxgJ9U4IMy6n1oSZPE916MU9(*=>cdA$=g}DWsoExoqt6wabdpc#~ZM-7qGK3*zwia@pA0=6~^(^zeN6n@Lv!AFOmOF zjkApkOe*pfkua5ZXvys0$@=swL&L)3%_)lRRR=!yNXAttgjr^6#KM4MB zBY)kebk{*$_Bpf1>-lXq>(%6PJN^BZ%`}Yo9g*|p5WYG0k}wf zo^Vk6rBPgb_LOey^ZBObOut=Uq?PsYI=e3P@u#mU@dNlGb~6!J<{r^&0~7Ai{`#uk zf^pzqu+Q3vbx@<`D%X_tP}7@)-vRv&(Y?B3e~~-c7r!%6`QIS_8}J(dJ^=i4@Xx_V zfsX>8aH{;)gjVAB9Q5a)r=2ExT5Hii1^*O$c2&`5-!6JO^mOQz<3z9AM)dcp3xDq} z;a$*UWzN$+$a&hQI8R$CqIrF#g%Q6W+JmCX z;C}}HGx$pU!DRfwNBFgsjMvGG*N^aPHSq^;;SWaP*J_ggEyn98{91qf!R7dazWBBN ziK%wI!*hR_kAM0Y|TB{U z(NAdq^T|BXN53z6$(O46_CI!v_Crfje(ZYDPsiV!j=y;WfAa?Z=1cVVF8a%PPV#(7 z``)E}Ir!5y=r0fby*5hnwIP2V?RyP>IvxFWM1OreatgZ?I>zZcNoMD+Ip`m2QgE__D%t3>$=H%NcA(O+%!w+a1i zLVr(l$Jf)`@zs>~yqof#_c@G{!HknBjFZTh6$otY23(-kWSaOZeVT1TW~J zwrpuBxQ%_c3pnSzj`#YPo+^HuTKo6jL<}|ne=%F{THk((@}1vR?-AU~xEvXPRq=nN zT8JMowyj0|kKEB!GI#D)&2MAy%)7&LJBx0RI|w@)&K}9-x1{^|f@kC%{=WEJZjhMn z@b@Er`K`qC;F)@d6U(<6B&Iu@m_GI<#dJG^UjP!z$2zE(9>pckB;KQ*v{ZN--lJ}_ zUHEtO-DLXiIPRC2!Jh1M#IAj^d#{a$`-`-u- zrY+|ju6jcDb`Tj~Ni1==vK5vuG7)(nyUOPi`NI{0DOU*t>TZ+anxFq~Gwb~jvN!%WgFUlv z@%S44cB^zh|J$P%{t((8y1`c2oxO5zgIDTU!jFxWIRED$&m1Zl?3jJ8SI+Q}iL&dF z0~LE5JkHmZFT+UvkBm&rj(BAaf2LLmpMDTH4OkJsI0yVJ@J#TV3h||_d3Mkmy}Zh^ zgI8(aTAm%O<=H`L&fk^hEK=!P)VGF@$KShmlJW2MPVz%7BzryJIoM2gYd_sEpn5>Epn;q92%~b{v@0 z(y!;h_LhD<2ewNe2hLSHT)9rt$ARtAhvPd*@*bEp3O=L6XOi@BV0%$~q>lrgq>lrW zq>lsJrH=!Xro?&uaA49a@P9@8&y_w7bdo;8<)po||KX;3r~KiHN`H8T+WT-t$@%aK z>B+&SYWKq{)b58XO5TT?O5TTuOJ2v<_y_pZo}zkdS698YKTy53tE=AHAE;gj?^3(!OZC>CqIw-);~(HNy{!6w`cm@!&_3mCFNUE-tcmi zFGu-uls9}UdjNTq%frv);a~FbD-Kdm-ZJ&8gUFGGf604HekBio5`}7qE9dxVyyP{} zc+7iDej^Wm;b2Jp8MG^7viw5E4*7$Oc-g0e=pkc=8Grl96o$+HBa78nNvFYipTx(pRR}qTKU7wpH93^XC3D74?g$nOJ|N6rK`U5 z4^-cOEkE+@do}45PY-7-SAXr>pXA?daz=UeTRwe}=r#QQDnQ?#T=mh>T=mh z>d@5Z3QwP2XnL1)@#&H+K3%fKr%Sr{6igSNVEV>)G|o2i&g;f^G|n8}DA%`h!>4Q$ zeG2zaPC4ha5}w=+zXP0mEG@nC-5TE)J}>%(7m4qs>xEy+S^P`e{t&NBxhpAmCFSng zrhIoH$6eHG_?;U>zmv02citwvH}_}urd;odq&r;uGe&PZM)ao0*A#gjj=W8|x6;!0 zHd1@{qSw8H#V3lZ9>dF4F0;ndV_BW`jO61V2Jro{ct6_LkM{MWeKU9mc?RzwA1NNZ z!zhTahyQx`2l3#YN5MOdg7}f%X%yriEFZk{D2TuLp7j1E@*gR_m-2flAH)yzRKK5% zy`GJ|R>N+pVMhjA(vL0a$9mXXJ@VC~oWrp*!~aP6KT`fk?{o_058mk%#E0o`QEp1@DGhR9^GiMawmxT2x;1+C@pF{Q2~v zB&~B74Xy0YqZcjLdSg*}&Bt81B&{HsKDubA)^&@P7sW^G zl|@NfuPhp>^~$2l~R(#M8s zqHjo7J2s?iox34h^V$vB(#M8sYKJS=S^C(JEqyq?>5_Lty4JZHvNgZmkS={}$S#VH z^s%9{^symb`q+>yeQZdd;`iHzbggqYWNZGrp_=rup|kW6E+_4!{ok?<{g!p^x2$u& zWu5yi>r)3==YGpN_gmJv-?GmAmUXV|M%O)KS+PQq~;T^->9=NmBA|;e&e1R-h84m&wx9W)O@1@^bXKF zK;K`oOldFwe(0BiUurn{FD3s2CG{@J1JECU{s8oQxI6hC?oJNkqfd}O7(H12cl0}k z%a4w3r13m@u>4-5b3|{nP5!CTHpAs-8r`A%jkd`zT--$K&x@OAU3zi3ll=9-#mfw8 zoqF-I!ePC#;$Lrw)#Qd>)#Qd>l=xW!Fo$g9_goEW5pc@hse*?8*CRpVpd1o3fjtN85ODn9$RiqF2= z#mC@5#?`@X8dnD=DxOE7?Bn1>*+-~6TTLGE**8IaqELMHO%R_@c^KCR8P^9VzT(@N zgXhQ&4xS@BaPmx)ogKVGc6RU%*_r9f;J({s$NRR*Z|s{O{ti|Z|9w@(KTOW3e^R>} z(N6}W{VckZlYG(sGriG2^i%hyuloMW!Qp#v@y1(sgDYfT-2?EO3gY+8yW+QCn93~x z{|4OXDc~v4&$(;AU$287eD2qKj)SWAoDY5o7o4Yh7v!kkemN@F4}1Z*(Qg9333@yH zW;^_5JH}r-{8l^sLp%IKMaEG@#!*G=xFU935j(1g9gS_QaXYrL#_ia$8n0uQ8dQ76 zE-f6EAwHBLK9nIoI7oabLwqQMKPiKsGgyjtmZF`dhz|}DA4(A)O5t}(5g!be!GDz* zBEMdS_~0P%p$zdMR37wP3O$!1J~&8xC`Eh-m52CHhWJp1xZoi1p$zfC$wPc7LwqPh zd@y|(EJgp9qW?<~9~>k;lp;Qa$?5FO>d590MZB=}Djrb6S;`18uAygj5br$0~i}>Im@ga-&;N&4b zWDy^-h!3VOgRc=EUL!udMtpFP`0yI>AxzGwf0AFUNIw~j_Os|tPVzB)Ghid|L3uBy_nRq5BN=(Q?(O@V(3{8Qkc0{;~Fr@;Se_+JhG ztKok&{I7=p)$l)!`TA+h*H2@TKMBy_+tn0$F=asq4J>Tn&`PE{@6kMaZUVj zs66=NTKMBy_+tn0$F=asP9FSmE&OpU{ITiFU`_hJCjDO%f9xRsxF-HMOipKKW?$$x z1?c+O^lSYHbp2;~v;G0Ti$8uBfBY`~_+9+*yZGZUxEH(Li(T)F3Irw9Pdl^@I8CQGp$5ALhx)*;ODi8iR2Y;M{KaN82 z$-y6o%EP$c%edZ)KXwp*ycd7$D{Bi;F%LU9U!(bf#EDnDbhd*-=e-?*7 zi^Klo@Mi{3!JnOiKRX3~<{V#GjplKMR!ye-?*7i^HEeh(C+NpE-H(XL0zmIQ*IE%it;avs3VAr{K>V#Gjpl zKMRx7#bw&v6a5-={cQTRegwMyGrd{=0Pn@0-HSiF7k_py{_I}-Sr}Z4KU<4GTZ=z) z5P!B7f3_C;UyDC8xCDQ;1b?;!f94?mYzh8s3FBl5{>KU;!7i$d{PfHln(;0v1_^ovOLpuJUHRGr?jUBbdj;>_BdnNPTE1BCMb2S6$T{qa z=W74h$umj&(-k?_U9pq)r%hi5zb8I?Pki{E_~0P%;d|mkn4D4nB>&zTzi%+w&!Rgy z>Cb5YiSFv5pYA0-I7nQ$*C27>-T*v-=j|u(Tzv`te+mBo1j-xz3FuEizkvAQAaUUW z2NfSKAU+seLVQ?)zfZ;gr-Cm5H+l>37SQjxWF%51FhVGFd-_!Ro|^>cofY#0Lk757mhe)$u3Qi4O+j zX=gm`j3+)gNPLJVKE&g9;)xFitK+|_6CbJ*9~>k;R3|=!%7dQc(Q`cU!9n6fJncj^p5AmTo@u52L!SrP?p8k)g|Ko`d4iX>Yi4S3NIy*D_LcjL| zT|b+CtsjA||4eVzKfs5G4-XL^9wI(GM0|LN_z(tjuQKCB@=gvlB8 zPx9{<(N6}W{VckZlYG(s6W!HAKeZx0IEY_wWstbgDgZxW{qPC?{zd%%i{PJt8~uLp z`=OU7J~&8RDDR-+LwVwZ!54`SFXHce;s1MqzX)#hE5WaXzMc2Pw+}t7g!i0wJMW7d z+|PUC`_o0=&->#Bt8xc@RqnE1!g~r!cn_f9dptVd7JY9=c=SCT;r3omU(Q4J<$PdE z&I7jOd|ZF%{h_yq-X8kTUH?7huDaUO>pe}rtmZ@T8u4xX^cs_uZut78UH$V=Beo01 zCw24jZ|@ZR68cNf{{X#8XVLE{ulnvt5?{mXR#Sa-J1gDr^LStBJl-cdkN2Mp-^hDq z8+os6Bkz?N{xa{Sz07-QFY{iS;XNqdgYrEnZ}{@Jb>44zNxk=QF8I0NXD-tFBWIQp zebhqbA5}v5-EWJ2H~C90N>k27Rda7ix01!Qp6$Ko^!~dd^m5sp7X}*Id8n4 z^Tz8rZ@ixK#-V%;S8tp*&f~ms9_NkoIB%TCd1KRW9_NkoIB)FwgY(9DoHx$nym21q zjq^Bf9Lk4t#d(}7&f{Eh9_NblI9Hs)M+Z4q{3hp$L(|Qk4Pw`p|7z|+*fm~vRi43J zBxM;_Wf@mxu@A$y@;>BN-dEhp`;~^j$@%FwIY0d;>i-k9 znH*&qS7jMjjxXb?EaR#y*oEaR#y>rq&ILLYZH`!MRO*cC;h`m{U zXLpRNKQXTU#JDnhbdYiNC&pE1y4kZq?Ar3LVI0lZ9Tt(YSL@vU<&3x9+_TZUW3E5{ zad=4j;2{zJ-0k2Yr}^{I!Q4UYAm6VVJVfsu4sNXXoCcSboeVCkbL=j^m0zlJ?SmcE z`S!s}fv#S?x9I9$YJ7G6{mA*I(;mI|ICv@TYOHhfgO@&;?#0t1=d15aMcXg^8lQ%f zq{oJnR9{2BxdTiK9dThx101bH`z~#5{ydTieLFum{?+Zlhl^$LFyhqUR zT}(KWNDN2S?6VdW^PTdNe-OpH@B9x$D0Ax&Y4i&5S;u@0rbK zJ#?ga{YVM_F46jtGSfV}sJ~G2%K8hR_U)v8MDL~7FCjS{Tqygl@1Xjn{z71+vwwcQ zek6H@_-fu-zr+~$>iu@d&-goj#y`k60^d~eEg}8XuV;LL#?N38d^6BP271Uq4;kno z13hHG&q4TRI4F5D&_f1#$UqMn3#Eq)^pFve9vna8@Ayd%j-TTzJ!C|rhYa+PfgUm< z(!-JRtv{f%^t(uM)-RP?&F?>hd@ry5BJ9M{fzuzAJxza9_B5UQ45q&=dz#KY2h&T6 zuY+%^ozoqZ9;d$zd{lBxe>B5rz0Z%NtH z^c#&Y(D)fFf^T!|sX6x49D8bxJvGOkn$zD7((lb3l)TO9_vYABbL^=(_S77EYK}cQ ze#YPNlO7yD$5(o2jy*NUo|QYjUK*64_~8)uaVP1EUbS z{Te-djUK*64_~8)uhE0!XZ#&M>A~@He5Hr4(Zkp1;cN8pHF`Kwz9%wnP8^_daU$dA z#6=nxCk~LGJ&|$b;3CO+qJz@IiHm@Y*AoXM`}TVx_PrObyeWj^F^ zzA0+>)#SgL{8y9T;p8{GD1E&)rJg@OdTmMrzrC-q-~1Zu5(in|xcnjcGU)FN_P;aO z|8@{N$l$(|4ED=2%4=PaQC{l}m*2{BuS$l48qXQafv(=v=REsx^)ENRnkOGQU)f*A z(COm4Tz(=WN$ZV_-lP|=d-|117FQ^gVj7YSj}^T)!du5n)?}7bAQ_EW!m3a%{^+a9QQM> z=KeFsm;2LJH_?9aYVJ{6&Haq4xlb*ekM3z$&Haq4xu0=0_cN~Meznz2^uF$D?pa&S z{fw)*Z!Mg^_DzjGk$u96#J7p;3r%FdYa;ty6WQ;Y$bQ#E_Pbm;_PZvs-{ttS-!+l_ zu8Hh-O=Q1oBKuw8e58+wcj`UUiIa72#YFbOCbADUk$td&8A< zH{yhY#EEX~gLUKHif-In(T#g69AD!f;B)@J^v%5UPu6%oxgC&iS}$T;J@%BwVPE#0 z`?Bv`@HwaML9yqY!RMa)GPT~@mwBo`zt~q=^%=aeqWsm3E2jF-4{vPx><{5^%@=Pp z$USy9u88>YAqrK`jVn~ojg}Ai?OCel+x7$XoHFgv08~BSrUB2AoZoIzJqEAm8?@K& zQa#sSpnL|8oBkL7{>tNa>iN}i({+EP;kyTlzB^0w-2+88yfWo0Q@%3g4c|}s{gmHN zdBa~GApS2e691P6i2uur>Xh-~_sfgostZEDN%809MS5Q1%9lFB@2{6jonA!#zJ7aO zzUgZ5zp1GFCXedhkt%t2aDV3x?(^Ky;Kn#l&K;?3{QdVGskiyh^L8v&J9aEqJ6yR2 zYR8VnYKP<7;8FNI4WDPkr;OUSqm1MY=cD%RXz(n2=E7&5_%u+vcQh!9kJ@eZ^ctgf z_gXJK^co|2uQ4V4dU~~u^Xuug{tUmKUhCEFUhCCvSFWwv-HUH2IKE?~zg}&nzh3L5 zzh0-S-Mvniyy1M*?p|Z0zg}&nzh3L5zg}(C?p|$+;zPS=X9euH0`^-0`!)Q58PdxG zyQG%~W~jX3*HQjD%3nu$!*^4DH|2Lz-teqx;-8f({#nz+KPy-I&B~R29le|Mo5i;p zT=@j)F)Kms56>?>W_6Rkvbq(O-{g^e2e)XRbntA=n+|T#Jj(FT7%!hOUOr>Ie8zbB zjPddrIgz?E9Bt2v|lpSXek{xFck{xF+QGaDGQGaDGk-oAUs=uQh#SR zlpSXeQoFJTsa@H}s~@wESHFbwQMDSIIQ#r(}ESr{pH-r(}Dzt7Q8_^Xc=H~-c(@@`_TpfQ`ss$!>Q4tV!}3c{H`FJ;!I1pV(*9=|x6d+OpJkjzq3U~< zaq1xYe3tS0EaUW9#;1em+m$mugCy^>jMHZspU*Nb9SkYIY^?OTY^=uTvW*&-%Qi~C zQ7HMBZIpf;94q}U8>?}-Y@^2GvNNSW2RDY5m;B4dYCJC6sByTg9pw#%l&}4q)>;exAyPE-@%W<@=Lzj-N|n-B>&rqYy9WRZ)fRT=-Y{Z@z1>(zMp-8 z{p<_uXJ5eZM-or)=b?}AEei*;wBPbbmgeV2oF3rYhUcMecploOSxz<2&$n4A{srik zZ>8jL`HnO_P;VFZAA_(r_t^*GcYI&tJHD^+-8jkp-Db&MfNuFVOKz9%NYexL{;{Xl zi+|)hAP(+UJ%8LSd5$4G21?lOUS zufA}B*RS_wicj7Z^ZoO!_toF%@2}_Wf8jQtURwO~UY-ApkJs1z|M}$`sl5DhetG4u z|JC7^??HJ#{^yr}K>W{a=fR@uzxYBg--pYP|J93k3tv3YFMq`~V|~0yyTRbs2)FiK z?AP-l_txjVYWb~w7dQ6vFQa`?{{B98UX=d~_={f?Yk!gad%|DskMjRJ{7n9N;Qjpk zO-w(B=Kmn^?Lp$xgT%)NiH|Owxajf|4-3-e?;a%X6{O4GTKcY`@~6AlFWEIz^j%4c z2fKzU9_(5!|LpQ{Ue1+IlKjn#_7Nne}RNmiphNXDKeb{Ku*P3eqKSa$*==@>;ptBZ%)jH>*8D^xDm2kF`h0 z9&4{;zF_${KkLdjlRefRA$zP{N%hw*kYDoEZYF!IJwo z5AxNWDS7Memb`Umie7iO2 zX4(9p-!)$OnTgi^UcS6DkF)tfzp9C`(A{47|F_cS2V;GC|6enkAB?@mr#G|q4fW;yf0e9#mfzYp)Nfxt zKYw1I_p0O1{J`?JL;qvNubH*KNdA8N^ZC=ijz9AQ$DjGZ*nX1V^ivf77kvHHWM3_R zKKGSZzUCIQ|M?qzyrbFw{A+}peqLzj0dM z-OS3T`Sji^t^9nSes)KrFYxJSZ!!8tpFX0e(Kq?@5xb54l~2FEyV1Y)>DPZGdW}kY zZdhZbo=?^oG0%T)SfiPqQ`Tsv=Y=&!09pUnU|*mH`v;LK;uGnh=Z}%i&-i>I0`=fg(2Z#WY;;vD7AhkpJM=P3V( zbCiF?9m;R;^>WERpVymc{{H%7n%}+7`H|Plr3UDluSMxQkMrb+me+jE=!4_MfAF2+ zKX|hE59U0^;CS(m(#1bY7yl?-{EdE~+;m^Q1IT{>c^%HVk^{77IrT56{^gvrFnrgU z;_>LRzPe&xU9qpO*jHEV%iuTI*EiVLH`v!V*w;7Mm%#mZF`X^HVd({6P^|z${mefCRgX$m1ccac*CH%Y-CEp0n zzm4F$+p?9SFC!lO75ZPH|C8s?|KvIJKY0#q_{`lZKa>5`lE_mMc{-zy&gf$%`k0A6 zW}*+nJD`sa=%WMrF!&bozJyzB*{Uq@WMj<|XqarHXl>UG4`>xiq@A=h=p)$53>%ZaPYiL1+r ztILV2%ZaPYiL1+rtILV2%ZaNA%%>8VN1fV2^MO;}(>&mBErtJWweZWxe;N7DCI7kP zA58wirKulK&w2o72C|>EGt`ufa9! z1Fd17Wexj4hQBmIe&Z$b<>RHj{(6agUB-*vWxV25KJL@Ij92_=%RX0I_PN@!&($_d z&$HXI-{t6uitBCJ_j2Wr({t;#?0<#lSKMivsCh$M_QS&SBPa4zpq&-aM+Mqhfqk(G zBlJAI0{deXR;nEp*e7%4IImuT{W8aw{jv%p^gO)+`(_m?seKjLKMUuh_ElgXt-^@8 zPka4Qf&H`!&D8D+?5lK_SgEb&()^`^Dy?= z`mj&ehkdp_9i*>5?6>u)qIULS-z}Vv+S!Nww>}-DuRiR<_36O8ko~wYKHp&X-(dIO zFdn|yrS^QYOZ#z--b3yAW|!ufuKWd(`hcI4-FkXf*UWPDUhA>`+ zFkXf*UWPDUTsg+e5XOt+%Xk^Wcp1WY8NzrO!gvYiqxKD9ybNKy3}L(sVZ01syoB>n zyNzB4|5j(b_Mhu?)Oe}0Mf=cow#dHfY>|D{*`j^mIvr(Sb+*X9>fkr)jMu(&osJqW zb+%}Ky3X0MyE7qXjX?r`=0+~Ml~ zxhv573fYk>$9eO)oHuuTo2vik4p;xr9j^YLTao^#sQwSI@IC%(iJU*d@`@x+&S;!8a7C7$>aPkf0dzQhw> z;)yTu#FubBYG*w0C7$>aPkf0dzQhw>!uU)kzDy>*OeVfeCcaE2zBoGZWis)_l_$PT zCccE{m)w(yFO!Kc;rZ1Mj?Q?Q%y^m1c$v(2nap@`bjHhM#>-?Y&v=>4cnQysyo{I0 zjF<5I$cub^i7$PLFMWwGeTgr9i7$PLFMWwGeTgrw9Pyw?;Ng%!? z5ML6AFA2n#1ma5q@g;%y63$2MOd!4_5ML6AFA2n#1ma5=pE1OjF~pZK#FsI|modZ_ zM<>3FA-=fs#FsI|m+<_Odkpbq4DlsAzxu)GTX@fU3-4KP;l1Q7yf1C=^68!Z{nE>) zYajgb8e0EfzEk@*276FG2-~yY5QKkY-ysOs@cwcTmg7AdgJV-l`1_7yQ?zeC7W&vs z$z?EpnBKBjq#rFZA{=^!6{>{V()pum*ao zf!=DMw;Jfp;N!I8aoX`X?RcDa7>uJGakL|jcEr&RgR^MIEZQ-PcFdw31{X9?`xcY| zvOlzdeLx2tU3yrs*r494vhsV@3ExA%?qPpv&(qrXbI{SnXU{rd8=a@K@_pI=>C664 z-)_17zL?=@>`$e!Kb5xORPSs+B<&gPBRc5lswZs&@HX+Y@|Uu|bt(H>m#z}OOCJ|M z2OV8}E?os|E`C;iEboJkW&dj|`(b0pOCJt8y7-LUVo>_D@=LJ0CD`2(>~0BmXRr!( zR|UJPQbTf8!R`#EV0S6lT?%%Wg54P`kKL8W?#g3#<*_@1Q?R=!*xeNDZpue$kHM@4 zk|zth%EIolusa7GUFEZ|yR601iN=^ZWgI-=;t3_+2^Px9QLMd&iga`~7*}ra$NS`}4j{|Kqi;2OLVNrY(=dGS$obMmT`Tk+;;{0{bFwXf8+o*NeFwXlAwGJD`x&LrJYUeP{`wwfU_1rMd{SRxWb=WY@{fF`S zj{g3R{{D{s{%)t*^W9FZD;+&q?fGt}_9tBV8j}0F8q#Zce#!k^vgG?Nxv2c=2je&L z8Lf{;ZqRY491yOw>lLhXPr=iKgi&i9VzJ+kqf z-yP5S-|?K^9nX7Y<2lDWp7+ScbDlSxkJ>e!bG_qvk8C{Wd&l!0*?7+RhVdykL3%E? zRsB$Ig8I+!maX+1rR7?k^KZFU&r|vi)VW&+ZC%N_w=a0J5z6Nv>&<4YH=BXyjZ;1c z*{8^3erCZy5P#eif7}&3ZkpN^m#cQgO;fuJKcnHR&wBHKAr1ajzhu*}Czm8S*&KcBesOQl2 zj@LPZC@#K+&#IyPvyzp6Rt?b&-wb^-^v%!>@4$Nk9cX6<+HLsf#K+HR@8`7N@MfGt zZ}yS&*Nk)MhQHWWav8jzcHIx3`{8^4@ryt9`u+ZfXZq)m?q9OlKNsZkH{2uq_~ZTe z@T27q_~$V0CmuU~#N+#k$Bs{+-W1Mrq|kpU^k2%Ek|(8|k|*U%$rCLv zc~Xd*jvsL|g}CYX1nM2f{?9nZ-?$O-C*zv^uiwsb?5j9B`#j^==NZTNHF^v7Lt3z3 z(qg>$wdg2*E!e+sboNtPu%FU`eHo*FfgOE;U4MaHhoui|p#C4mxE#i~99Bm99o9hl z9ky8db@>}ezr)H%ztQs2?=arucKkR`GmP^!j!&T88F8w2MjO>TW1Z@q(MEF4Xrp>( z#HrpH_>CFsRPT&+ijOn!BQrQRGlO$9Ptt!+(tl6Ve^1hXPtt#mPX9eg|2;|n8T|(O z>jwJk2Kws;`tt_*>jwHOudCXThhNLXuZ5-mo$+aK5aV+Y<75!ya}eWm5aV+YLNPRQlKG?HHf!=+AcacRTvK9sTX- z^mjY@yB*`x=oPxF|0_JFxK;tb9F{(Ycr=E1G=_LIhI>-Ra8HV(b5F_`?n!awxhG`| z_oRg9m;V{VJtt%vTI+(%ZL}`fyiV(a z&2gH~Z;n&D!}+M)o1fOYU~?O-3pTIQx?nTs4mWcSF`SRuZS+z+e<{VhwG{JM!@IFB z(2ae8ZtNErUYqi@DPNoNhHt0*cFJ$3yy4xMuXbm?+MW4o_gv|>d#>Vvqj%GKse7*0 zW3GIH^w>Q?dJNAmJ$CP=^-uS1Mdg>ijNdy;bWi>}`0c$Lh4000z6AXx=xd>`h2DmH zMcbU8>+h?!>8g9i4Zje5T!=m{L?4C^XJ2SI`#Zzg7mDJN*YJ{{!;<0r~!be1=b^zRA=#nfju*>NETR`45o)0QsZ1@*Dm!@_meaA0waP ziLApDS%)XG4o_qqp2#{pk#%??>*qw);fbun6Iq8RvJOvV9iGTKJdt&HBJ1#QKC-t& z*5Qe)!xLGDC$bJtWE~#HXEy8b*{s87vksrlI(#+spE!)LP& zpUpaaHtX=&tixxs4iD#}cFkrTKAUy;Y}VnkS%=SN9UjJ~8td?Cti!9Z4mZ4GJnF16BCWKq#N>#^-sJ-~I}GrU>#~fhv4gAdF8O z_YlT$PGjw}y61Rpj@GaDp+5)t?!$fP>%JgPf8J-1e!Y)=y)S^*q8$z*cP-?u6~xhN zEraN{7W%Cfz%Swc#!I-r@e=NDyoB~T$a$JeI8Sp)0N-<-?uXoyqkBO2@ZGvS=*ht@ zvdcYupKeb8&z-FIeH`RI=v;$$D!$|zv~=KKxxdlD57bYCd7oo2?|1xx_eK7|`y?Y) z=(}Shnx5r9{~OWtnu|QUA5l@~uA}hO@_u?#z4tbv;uU3L@x%|rC-E-vNxVyZ603_( z6pBycUE-5iU3?7hR!;A$bVJ^=GFO+vS%M@Jk7kC+!re7Zp;MdX)2a)?)g><`Kz0ED1Q`Je#0klulfY;MW2wQdBB9B<@`81 zVQ6K+q*8+1t3H8y)m=I6QJ=v5=@W)3eoq)GKQdvc{K$l)o5Y8E)F+ge9|`5N-1x|k zOc*LZG9gLhb^`aNPvGA4P(IuXZ}c?mA&ve`>#TOCWlP?)?3TWqY3Y(TjeF43s%ie? z%5m>`TDInOY3Y(TEnD)YWsic7jpTYhe#QvW#7(&0A?`^K)JEW_YDxR<6JEW@`m-6>BR`Ff&ReWcB z72g$K#rMZuxyG7*tm3=Wj&I|e;G_Gh_}eNFS-4bRT)@BY4BDEK=Z{)YGG zes=q=biwaT>wb3o&UEm*(+&ClVZSR&c(BQd`t!YqK4bK~hd#XDI)6ZC|GusHob&7S zKjQb$TAhY2VB)Rme!7Dv=VtrqCyQRYT?wCm?K5-#?WN~K zzubXRxqi8P=;NhYsNVh5|4(2#?VJO?7+9P3Hbb8ulKx$H$@$%L^?d#X;76U6Zt!) z*YowbG^KOlFjIV%I#|+|JBo|XBjpG9>5nWI-l3ZC4%xyVN3UmAE$`=BRYI`Rd4eB+ zZ#YqS7I=Ia;R`JP`NBU1kHBvucx(EtS*;R&J=f5GgQ@>I=%wlZ0~#kKPAG9(N=d(n zSFHF~tb<>p4S25<{L5)Lc#meH9w|yF~%(3QY{cyC`&G^VMNX>ngTC|AY@AT$ zaP$3Ce2=t#i)|6kRe3rrEX|YGw?)of`TvV3b2NPHoL7+lu}U|+hr!6RjNPY!^y|-+ z9wz6nDc!RJ&o>6)k+i|H2lM3~43-Vje=Hv4|69b1(vgd2$6$`-<`q9;o@RYeJnzeo zMMp5_wtn>b+xo%NrNvc`Zs|Ygyw8)*`+2h2f5WZsW1*APd~_kPIKgY%x>AbUl}ZZ+ z@)^%##V-)=xXT2+V!FJYlp_`83a_Jb0))VKlElyz;To?BH-!Y;~>pKq~EstQiSe}RTzqqe{J^sM!&)EJt z)_5%M*zs!ri^r|@rDDfbaQq#uj$(Np&i~@R`t^+4;=U^GtE2S`ztnQEKI-T6f!^4% zd9gu@S2pfES?zye&`Yzj2E8=DGhCs_s~x zhx5Obigj@20XrPgPC=fPvu z)>xj0^S`*Siv59SC$Zzx>?YPWERWHS1bTb%Kld+ki=N$>9I^O?`SKm==aq@gUl?wD zj|Rr-K33WNKW)FayLf|oG*0gfpZBzIFtAb<5N`I|F5>YD7_f{x2m7t zYP+o8!r*VU-No(7pHuyc{PJ(Lzrx0ymu~Y5@4q+4Fc_A8C|*AoEwoBb^9aG=@pFJ%p9G8dmM&mX5puzt3F zJesv#tj^7beky)eR}fl#VKA8A@JR4|y_LM@8nd>G6q07;W8tyj6(;|YrrUV*jb zOLP7^@IKzL&Ks23)nB|P`NQ`Y0{!rF?}G*V?Z@KQ@5kD{j)bqZ!TggaORTT^xpi)B zDV8H}??ADy_)Yl=8+SGio!tlHuP zJ@#x?(OQ&o8O&W2sNie(dM9 z(f)fd*ydwdZ!GU))klZJC$?Vi|KXH5R(XPTA4`1(`z?r@|BHMT7~j_x9N%8qqI{m8 z=NS1gU%!Xp!w$#qSUV5bcYEzP+`OKgUfv^-{|`m;?qTKzv24C*6@dw$8h35eO7us~J?ZNv0 zaQK>j4IW9^pDM4(V$kX-w&!DifA+D^ZLpsX$L_4&W1ZJzG5Ax}b0mCC7K2u{*q)2+ z**!zCXI6nZgV~Hhvz=o-ZjOYn$zssT7Ta^NJs++;`}Q0A9#bLb<9=|Swh+3<<7j?G z@%^pSO=po2rF1SN=Gk#!X_nt$VR;Hmv;1MOurh_E1I{};zc z;$mQK^Gnf-^{2_>*_+verMW%S|MFgrC)b6=v2LGG&{TQA7n6lQ^AhdX+ z@pPelM95yvPn9=Jrr*+ji?z{o_*-n7wee`7>E@SYi(zf?WQ_fV<@=?in{Iy#cK2Iq zOVB<%oAS>=9pzc6;DJ2=3(fcZpbfTWZ`|0Qd-$}*)k+zEdq4ljlnu&ZG6rEV zpNAKZr^6dhKSozJ1`T?=yq~jQ#&HlY9*aMmgP7h7ntgj?(Dp+v%>RF=pXKv-c;yWm zFT)MSrh94L@7FkHOm>66);3swczy2uV)5AjL7LZYEAva4Us+!i-&2$C3;z$@Q)B&J z6f}GNxnNQ9{Ty`ftoYAS@2{fH6H2sC@gCKcEO~GKuTTCjIsexk_}6^cHUHN$|L6U$ zmH#W3|MT+yCI9E8cgg?#PyVlW{?AM60bW?X+WEAr@_%*me_{C#M-Hz(DiJehu0Tg`8xT(EAxN- z@_&b0&f|Bea$$XCWvs8fIz5@X^W-?1wjHWmSlbR& zCajNw`VQmmwL5mK9&S00Us$| zo7ZIU+HG+mmhPo{xc!2%dvq_(1nFJ!)69p)^7GO>{d#SPO}{%I_jDLcH~G5c)4a0Y zFSeYgk1nJKX@7)f@h!HT@r~8J*AA~eK|Y1$J=}a@yu9+BzP&oVaS|(=C$Fa?uYY6H z4`m0j`Aps}`Q^R;K|bCXDlC7jF1-JqjGhi-^LlAr@_&B{q??@w(@hp@Z;+k{)zf2;W_5e=do)j{W(!`K*mhZ7Psg4-L3+@ZJU)e$|Nq3j z2e>3vwf=oz5E$elf@wHm=7ed|l)%i0BO)+>1Ods22uKfEK*9hL1coR`NZ$x|kbzaUX~=s_bCpyG@lJF?=uY`Cfd%){9^2!@9Z#wT}6C&!l>< zd#a}fppdz!%6J3bX~m0u#rDFQa|6HSkw(3;IIm3?1y$fk&D!aT5)ZWM{4stVjbG~kX!mW z!1|aoeG5m-sjcc>9oNDgdB8`y7JTge0gbrE^RG*f4>7>W=*1VTRld$yU3TI!rfT@_ zfncGx>Kg6r#AxS3-mLZhfHThHK7LK$hkt5^2RLC3e8;tJ16yjN7uV5%YwU0q*QU9# z9^XzrG8`E;{K{_&;%+T|8~k89%_uOV`7mv_Bk zYvPTyjq?>epRWT%(FNv?H`PQGxF-v6pF@mWMHdXpM@zqZQ}uDNdN8mwV-TLb@f z4c4)~UF_7a$`|Z@U2c@dq2VZkI>O7ksqy^=r8b?Vt(bFDXUfTfo;p6g`R9iiCN7|!5tZsR=V4?j4dS2(9u-TXZ+xzE$6 zs!LVePX6%f-&gAuG1-GW`HoT7sM^ze0XsMuvA$JnCgaQVMYnjKLoa?_*KWSu?CqYD z!Am}CYrsVneqvM4x(2mp_E&jaA8@~z6VoiDNQ?_~FTX*(ZsfDd9-MT+vwQDUt&Lc!?Cp9OU%yB48CbP8_G71eWV`j<_U0bfZf!4n zcUs?W?|$}cw}xKh`mN%QXVy-3>W1BWi#S{};AT|C#Mk?qUZEyceyk^FVz%?~&pUkE z`NaLW?yB~xx?cP_pT3RHtjOF8+S%E!u0c-RTjKszd%M4XKS=kZzu^F``HitE2D*3+ zQ3JS3W8v4Sr>gwHLF~E)96RUa)NYT68P2_yRq>;5uYT#i@a%mW_dpM?^jVeNYglFT zwN*A>7q5@FuiNPp_68SxMIYj$=d%hw>I}E3pU0x6?AOl6pL>W2=k)Y!jX4_YXrPb# z6PGpQM-3*s&ij^_jLGa(Z>;HcU78xd)DsMh zPIyud@bx_=!$B|WQVx1qQ^i5Ibw>yTJaAtE%Uq2rEcl^6T!V8s>*nuq$zh&GuW>v1 zlV@FnYpW_=)iv18&-udc*K3t;H@ojiUfz3EapJY!&9|GK8gO4EZ*Z`0)t>l8yMK=G zTA$|{&Wqo zz|Osaoc#Wf^2EA$J*071PoH|N>N+O|xp0nuyV&@_J29%_#vH5c&TC!k`OK>FAx0-V z{YviS%X3dvjL0oqv4&ccJL|xg^5$#2W;_qI^CK2}6U%E6ambeyTEb8mEf-|tR^C6CN*3Ku^w4D!iB=@=o`&Z?I58N|4`4Fd* zkLN=?YK83AR=RH|8yxYRMjUWaGk(iVW4K?vVZ+|e&vV14lOOw07w=nekW0I`RsL|) z&foK(zToTTN3Om4y5D5ucJc>%UBh_;Z>OBS-o)fy)QhkGEl29>|J?xB+*A$z9fP>Y zTz~b(x!e42q@zFgD8H6GH|k4IMZXv~wN=Ha^6`5pabs-q;=UJk^jD0FochF^QX4U2 zJY@PV>f-v;hCe(+e|+GGK|ZNH#!GDxOXRsz{Ai1@Q@!^f&!E1qe>aQ1d>3xUmndg~ae2HD zzRnZpY5eFv8DEdh8fw)`>|T96w&(4=*lX^+`1>B7Q!i`q?c^V?59*6A&m2=V_`G9J zJ|C-W)Pedl&(VNWt~FoFIlWTXhz{oR||jI7s#6!e>RQCoY_)daf&SfN$rN*l{l~)-}*q+1Rt4o%?({ z8+#HD?%11A6`x#EJ!`lhSJ}KKRW{#~xvl|M?P9xc>tL#M+*`?sdkK1Q z#r?4%lXGf|JxBiVk^1=ac-+h5v7Wfx=i{E}>J44gQ(O2z7xh)wZ?qH7F-N^)BW8?I zgLnVk9EYUS`W|EzRE_u+S$GLyr-(xuK~EzIL<|?M`m5BuS-Wyrh4*Cd(pY^diH9Med;k%Eb0E-W6{B7 zT?2piqb7Vui#^iLx1B$0>l)yWaqzFwI~V>8m#&L^wDVyN7}B-u$^9tRBU7(b&wam2 zzd(9orT*x_*v>|6(lz*2>50YlKn_)Qc%VM?F*Ql!I!~Q^*c+be8l1=a&vp|?{ToMC5%U+i!>yK&yl-#^nkts!6H zq_N=A_l%g}jJQ=c$Ko|<7c<7=9PX$CF{6$3?QHmgtKGUzHr7_HLr;%V`>I^3^wbT! z%;2ZS>009Q4Ast#eTv2G4=mh{-ia{i6*% zd=i&lO>JI_Dto+!<2v%g#>{7Ow8b^u?C_eduS-Y1)B~(BHu3yxiwP&xm*6plC?|xvSe|qt! z?%n+B@}bY+kl8W83HKuUl6wKMqCNIyY9n`YCI+0ubv&1$^L>!9M;$r)HQ&h=*Z6e@ z-{ehxzK7=uXYd(qtgCB)pOMFL7ee z#5mZ}o{DzoGwM=4qs{q^I<8B&WkfxD6U#XUQ)-7p`hgxu?JP2@z4sV7 za_;pbx41s_BNo>^{=N9ZMV0Tk^l#VLLgT#}J8HoF){WV9-pA=)a2dIZIa7PMW1gci zTZ3n9?+-BH4`=wnL0yA*tl``_qaX2W7lZtWfgg2i=ZD?7<~;R_cJd(K)W`FVds6Sz z56K9{stX|^y^;G3coGN>YCC$aT zPIL16devUhm(TAi-_$4Fx2|>Ghj9;d)RerVo}S|#ld$r4&NpHsMlbPvf9lkWKl^v`B?o%f`@aegG3dqE8}0n+^23(esck!(_fFdHX$-}eB+ zWcKLhPaf&LqFw&@#y;uh=g%DEz_n4uiN|zb|LjVAsb#E9T{3+XdoJ}^(1Q>C+$|2* zM>ijOCG`QDe;*)s-}2V2ZLa_oKN{gJM9Uc6rPEj8tSM9dh=eZBw5jdT3l z`LaKIx3jY!oVBy3d!>HqvkbXZ~% zuFbd}8Q$R}wK?~`M{0My*O~lMA7t#QK3$vItM>N$Tg>16;IFPh?YK_8#`sqG!wEUm zHCW>{r!Ueq)TplEHos>Oqe_n-v8(*aE!ERca8#w|KJ0Z*?T)=_ExuKH_9AAL&EvJR zFVH$Lr+J`aTPvf?`7o~p0tXfZ8`T#stcF(Po53#*ZIIrrZy7bOX zv~%BpXZERURQbRgK3s!od~E(4662z$-&23b!@iO4xHi4+ye3sXT$5FM5QDwo6gzv( zZk%`X_veCcYuKB8;08R%)SX(fN4k&qU#f?5&$9}n*C$;UxvVP&J(T)*>=@VAdG7E_ z4apD8=*cIp@p{q&sf|6Ub(PIyR@qp`e(h|mt+Jtap3__+Hm?b}rGC^3UcH8JkotHm z_DlbbF>=GYPWE_>Rqew)1U>n*%K^MqcKBm0T>9rpyBPF>$EoWaZmBirtWVd)dp(mbpl@B(@)6R!DUe|U$*y|cx5AA%w3m0__a*X+SPco-A$HRL1 zg3-x`Jv#Y#uEc|HWWU~HPVCXiMh*Dfu4_b%$8*3hU60Lkj{Bk~Uur?USPMtwk@|UVo&4a8eTV~&7z2##Ltxq>u9ICyu5nG|2tMJJoO|W9mo=X2f4W!9yO(`ati7!9Tqm;^y-(lK&+ta=+i{rs z^7+!vmsoxu1q;_`m2VoeogXZ_<-Gud_B?i=0qP5XN?xz>d%-lID0b%cDWF`VHyw{f2GhabAb zH8`hM-TXZ+xzE$6s!LVePX6%1XBGWh*Qkowtyikn5X(7>wXX8zy6)!VIrQRJ)nirr zc8kSxA~>iGIr{yDSmd*|1{mALre1Xo)-xuvzT4jP%73zVr}b4_*Bkq_+Y^4e`FPx3 z{Je(Ue7o7>JsDr(w!_fPzCdfa{}Z!Q9IipGDel>w{MyyHU4HayyPj&dhFm;{xZZKJ z>s{(e{?x3>$FX4}C%((GrphZ1TiQ_Of@U_3ifVXTNr9=r3wl#U0`ZKo&D+>tV@6Mt=ilD z>8C0?98m}QfZs(^ALkHk;PCo+&e)yDc0TOw>)_G*I$|eI#P0s-KAn8vj5uH>w&ycj z=W{f;-qFW>eGUEF&pPLqycm<&tKL}C>$)^Q@PLawCxfe(bt$f1);NcC<>P#GTSwnf z1Ns6C&P6*sDF{pea$0x@sJNbK`RN1i+!#^8h zj_A{8gsK?qfj;(bm0vGD{yD_Hbq(r5j-0dJ?{s`T`(kGu*vZ@TMeq4KSE=3amvB+#gFkgk zx$!;F`~6^!&Sz`zcL#3w_3^&LdFn@=>|fWYS`VLGBc1Hzk=oO|Q#)}NG)C3F?1>M2 zxAXJf!mqADE%2?1*NcziBu=MTbb`KUK?Yv zC)aT5&mQp_Pwmc0TB8`-ed>zkJsIu(IaFoinnX{{z{5a}>#?!F->agH-mPnZAzkOO z{kpI6@!a9Z?=e+=o`c7XId}~6fIo7=pONNNiT_Wbx z2mZSG_-AsbI9`KJKGdh%Ua6gXAlJrh4SGJtCwI6?^{hcp@4lA6D7O1)kwM=D^-{ z4Pr(;7{Hq9+vVKNFSR2Rzuwp*wa0z1wX;V~QXeo-r&J$fW3}n6?skjCtd5g(f`=!AHVkzGsbdXVuCZZr}tsvRILXqIn&Fj5BgM>V!+P+F?Q;c z+GFnIP5;LAVCQe;s%&X&_D|P)PN^Q5TvB}+GqqRcOKtc*5%YFG@@5}ozbT8*Wf(X*4JZm+|eF;u$_;` zz!x8$I~dftDyI8WXY%Rh*NYFa>KeXxC!Fnk;2vAL7Cn8^&Ib2YYq+;p>A6RydglZV zV}He3r1uwkK8@o(Tx+QWY)#K zC%eu$g3HOQg`Wd8={0dr&t&&kz4z z^6Td3`E~R2{JQyhe&ArhdpG_%`FVc5#B=_-#j7hPaCGv+&b8Ie&-3f%hn@Vo`9=P? zXZONiCqK^*teyNkzixh>AO79qIe(q}JilJzIe*>a)s-7K{4=^+|8?^7{CbJ!{nsrX z`GL2SA9m-jlb`3;OFZYVQ#?K!@Z)}4*Wez*9)7Rk^R2D{AG0+4GYua;^H|%9KYn~B zu%=t=m{T`j_O5G?U-X5`G-v0y7hmG0_i?yr7Z-fJ#;wbjTzbv77hlh}7hinHw-;ZJ z3pPHRnf*nix^x{k0x&~`{iA%n{_+&Ujx7ft=`gQa5JbI1m*IzGj$(LNZ`Fg&+_KK}XI%{S&W8Q;40@ciik{~Xv?=h(Vo=w(gB(Tjh? zGFg9ec0BPqq`ug?;pt^f%&!;!1GTUJ?o4jZG56v$pXeL0ck_)kukz(tkoz>b^Sc8B zKXN%>W=euBm<4e#5kwfOh4c3ghDXv}Yn9W-yQ!T&$Qx*Bsed>?AW{ya|-o3+S1 zv*91@To=gj>bcf+4kiY+^)x&-v3AsWyT%q8{{IhA*E#suXIG7F8Y8ar{8_(~#(a$( z8s{Dd9e%_|7h@sgj}7d^iSeuQf`huo-WvSAIbVZ*U~oO5?-XM@+2LrR2K;TN0Vj10 zdH}qg){_%H9Cj^eDV@p8un z_sbcR8ak&h7k=Uq_vMPmwfb_#qvq6^JgE`&e>rOIee`n1^m@OXF~Pp&{|DG#?wDYI zIb+g8-s>+HpWf>)S3K`^zkmFved+Pwve#Jf#QnV8eSKrusLMMwxPNm$ez{`vxzJDC z`C7;4#`YS-AV0@3na`q8tsBtbbI8}X;~{=V^@5*ghP^fF8l3x>s`E88*cV;=J2d3f zp2qNJUypHw*6=xhj7IFs7&l#$?ptL~_w{F8-#3ks+R1032G2otjde7@yq^YZd0vdV z!z4Qvo|U3)wq)X^dj5@)SZ*hVuRBoZJg4$3X zI6U972b`z%B-i~r*rgIEk|%(XRN z1KU;__|ik~()dr}kSq5E&%^m(Cg1rQJ2VD4lRq;4H25B7Vj#zGDD#gB83m--#j@Hsm1 z1INJ{bq(V9dh&BU=V11|>Nb%KYe z2Ol!rQaA3A=^D?$^^VJBX5zB`Kn?aGPxR#EGT6bv9zwC3*MTS1c?|ZzM(*SW$E=Ng3pTK#bB?2q zHN<_P{6A$2E@E0s zd4BW`zR1+Z?bLu+bq#FP$otCka6K5|hkd~8di=?syx0RDw-E!I%O1Nf9lp%u7Wb{v z6T|x#-*Jr@8uTxKRIIJNT{GGdA*Hy(L zC*pfvaUc4rlbt-sA0MwrT<`o=+3`#7CGZZX*c>x>T_3rwx|ZAdfsJ^6ExRB2c}!~S zdU~fy4@SQqb+f0}vd4xC;>Z2SE4`1w4LmT2#eQ%TbMW3FR`hYa-dEVc?=hIE9e%`f zJ@**SQ$6<)^2QdQ-O&--*VlEjKU93(%F;>LL^ISKKsZWd*^H2S%Fs42+R?I*3^H}YCz<{l;L2t+P@Wr*n zbDm=z*ZB+$?mcx4u3_$noO6A`5xs;DYq0q}ioQl)*T9cKe(X`#z{Z~Fi0d(kM_$}t zIOqQ4_b!jgUg+u?#N%__bM`gp+0*sxg^jp=?;6m#<0g;j%Q<-1pIFh}>3+mIkJIk{ zk@~c&Z|X-5#EkWgK8_h~JO}W>1Kcss*1+!Axo;y=gSrMW+zwCPFL2>{a&S(Z&uC{) z|6K9e*V13);WEDLjUPEW=g|%pt|9zf?|D;G?5-ys=TVpT1bl;^81x!;)-2GV*WE^p zDqC9ry8PgYb+P8DKGvB$tJXw4c-fzrRnIcMKJ}v}^ol>rxF0nGBUoJr-@ZQTsZo`l z{P=wLUV=mKC2HurGqcB3jhPyC4fpjLM?1C0K1*YUM!E(p;9_5})iqe-@!<)b@8SOB zfgTy3ZvJ4VPGD*0OHA%Lj)NKQ+WEU5Igmf~r0?n)aSioJIY@DNEaLduD(=#C&PO}` zz+G?bPd(kg9e?fotN2TO9Ya5Sq_OA)>gCt3b5fTMtg|${pPVP~#dWa{>$0UaXtyrb zAoAUAPp%#MiaN8FHQuk-(6JYvp##ed9C7Lr0|Qf*KIG7&KQL9|ktR+(;?RSqPOLL) zhBQZ;<`oC;zYzN|h5N#T_c;>rizY5JYsSnY>c>dF+2koRj@S7;cE02ZI(?v6B{%bW zq`7KelOHS12g~~z6Q|01;gPGYy}C5dnP#cO_F>N#8iM8XQXwof%aW&oWvPW`d9?{k zE6P4(_Bs=%9>30!ht591fK4kka|_K-shL-3MohCDtJYb!P)(TXmCEJ#h4p<4U9F*8 z7<98txAX}!jz10xW}7%=0SMk)oLkOsDb5c^|5iI+>L_!1TSG9f4I6^F&2I=+uuV*u zV&_{I=O<9MciQk_&o1N{E?;W$D=j_OeXg;Fl!^$2d{X$B3_uFsq+no!S<6dyasN&uAanI=Q z`$V1Z6?Jhxc=WgtU)0C_qCUof$Er9{ALB$ly!+Z1({(W~*Tq<_bKYH!e86Yq0y*6a zY*oCwKHbyxaUa*ky<8XfL+AR4FY4odQ4e3fHjSC)?|x}4{G2cMaU3o?2AAVra7+!; z{h~hZ8TGzT)cIaf7xyEFs{Nuq?icm&ta0D#aOO$zFc-3E;|O7<6hw6v#g3Q z*T+4hzwZ-uzE{-6{lM>WBfhAQ`$au``PvxMbupgnVl3A=UoJZimmP!4aW8Q38DGVh z>*Jo$KgI!<`^UVaKE{c9c<{9`rt4xn*Tq<_a~@oF9$a=FT#kEzi)WfD9$X*yjQ%kW zxZFSH9rZCz)Wd_XjWJyprx3>wW$X(Rdz9<4@pFOi=jZI_ z=fsQW?B%k@a+#d@{@^n9D3g!-c)n4_PJGt5J<5(J+Ip3Ua zx<>qG4D9aX{kpbvAJFi;=pRO^qgPVhoC+PilKRmrQAe*tnOIE?lvV~5vhk1}@Z#l6D!Z_3LIe9L}rSaQil3#Kfgfs z(2gIs<8yXAz>cTc@p?N>S&9e;+4-S%Jll>Rvg0@G_)7D6+|EC1$7k)hr0L&p=gZmo zt#*Ee9al2VH|_jrJAT2AkJ|BOJKk=`&)M-QJ6>YP7wx#TML5FFSFrP|?EH0hew>|u z*^VEu<45dxogF`E$M4zki~%s-Z%1{X&Od0!JM8$HCDH6+$4}ewS9V;1wHsr*%vQc= zNBzODG@rENpX_+H=^wPCdQsLzcKop&-(azJv*Sf}{EZz~BKqcdf8JJ3G4E~dc%dEt zYR6N|dY>I`$076H(~g(f z@m`Kwv+@hJW?A#w$&Q!V@o#o~qj?`@$LsC*D91fnc?&C#;p}dUF=i|D6S6cn*>P!G zv4tJaw&R_4Tnf(C#qR=J`M4c7ur+7f@oqbgnfE?+yvmM$d^e z+K!vrnvdD>|LnM$dB4w&U$o<2Iqu5J8*R;N%x^C{e$kFk+i^Yf{-7Oiwc|4!-^a>3 zY~@^XSTxU$ue0Nz9cS2arXAO?<63sy&5nE8aeX_^x8r7Z+{%vI*>Pt({>6?D+3|;V z{IMN>VaL1ec&{Dro3hNn-|d&*rRw#4^t10{E*v7^2@_V{`{*MV?lXJgfrn3>P`A#S zF~Pqb{M&5H9kcMrLyy?^i1+U=)pMp=l3%k2PUqM7DKq!h`OlB=*@ee0-1nFRj~rO$Rqt7}XyE_P|7|;c(Nb@?Y|*we7QHyI?VSJGZ>6DS zr_5Yt(Y55X!tN_g*=6~GS8coGc5m2riQTqcV&@$PH19Z2``)z8vhPgGZkv|fI&JH1 zUyXXN{I+RV&HvntIcLm2@}=>4KbSTU6pLO`xKWhbE>XvOL4NDBYfgP|M#E>;nJ2G2 zFh_?ams)LLVC^f%{yJlp;tb^9v6!!%kFehNS-$s9Q&zV)`?AwOu8gMp0<> zg&yXj))n_nDKh?=Q zU(jU8kcI5GLUwl(*%zhE?`|TSKOThLMu&n_kEY{BhX#vm?=eJQQW(n?v9D~ustC&V zE0&~Akd^KKDck>TX8ScM^Z#vTyY_ex-ZDB=Wb`}B=z6(YMu>f7^bJK&A~#qfIzd)O z_bH>_H#53XN?iuu;&NMb(27d$_m?@&PD1!3%x#gh~WF_>V5_+JS&@ZK|Jv=Rc zK=-sqXUsbD)YE4S%)aK-vu13i6~B@(e^{2YW^jiaSoNAy|2|{wGfzDS$A8Wkm~Y4R z90v^=k!_l9qsdFo>`1{NJ7udR3Hrrzj@CoJRxiliGs5&yxS!#+4o zVa3j(nWsJviI2@#e8-2`k=qIh^u^&5iXaaEp~*Nz7KhJ^!)K>u zPfyF9YI69bO!>0~hc6o7r+n4Fbt2vi4o?yc`@mAZXU)i;E*Z?9D$g6ty`S^mmx{(GtdvUpIZxqvQfQ^J$hDHnM!2>g#zoSN591=o7m6HB;8=Rd&=^OcSO*v~?>7?njg|j8K zUYr$Cmy!@35{ispfd}1zIN9!a|0?zz^lozHIq0xeHfucoyl2}bcCRg5MHlnumLFK} za8T`G+i=>?Hv8yNhi&%JHb*tL*>~F|_NyJ^+Z@d{``b30PIj9^gl5rP@u6u=O;!P9 zZMpW~X4xADvsr`L8iUztgAJ66-Xv@7)q_P(FH3#iIH>D%`JFlBvj%ByovT)B==@`x zpE@I7P3Pxve)0@arVCpfEqa|+Z@u=Jr;P8c(J10NgXFTVHZf3$eSz9o5fo@W!=e*p zftn{!>kejf2ea8tM4QMYv<0GRAX>LXG)L(#KTuqI?ptcgIEeEsB2eY>~5iO8OXhS)+ED^}j+WqyPrDB%MwVVxi=^IeqrPJ`JFgV}b2**lxbFO;>mYAnZ2 zW%BtB%F@fRU6H+&Z4`#a!X1g{K zoh*~khH~s)B8uhMtpH@@*tGx@%JE*y{1gSV%n|#_{3D8>gwL>qb%LzS_gCio4rY4~ zX7y&~AC;-~y56_UJl|U>sumpbdYO9dMD9)}>#<`4_hX~6-gV}*iAQwsB3gn;?NG!pDlf&_T!*Q{q8xF+2a9pbh zO8;_8Unj`IakOw8IhY+Wm>t%H@&%b%FYY5tDESegCWlQ9%Lfe0bqa4-5c|UNO+^rd zuNefLAPdU}h2^-x?3gByT>4fZ$CW^0O^%ryjuQ;WO^R+f5c|S$haxEb+bn&ZAPdLo z!g1C6HK?4^0lohYiPX6y0zj_J!lmilFrGwe)p@EF2dI$Hxb=j}2xY zX+pWbaQ#a$J)ntO(W2k!`Ff*MmYI@&yr{~V182>seQHq8RTt0Lny;FFm1pgfgROUq zPn9hALc8sKtfV3Th|cwZW_P*S+KONg66{lhV(y>I56tE`M|%%!itQoU@=p%Rv-tY| z3FGKtX^kVqzBqbP5fuLKn(Sc|SsYy|jxHX|E^HF?RN?pUVtQIrD?t|**v=gI*o@j0 zfuLvPS-U(T=!%k{*d~n__K9|31wYRc>xycAo|7%VyyWLH>==*Ge9 zh9*J7h2KaqP1n>)(2WH)>!F(iK{Mo8yD1^)=8~Y;LyZ{5&kYs)j1ueSYJSFK%Wo?A z$&H_JX^kJmzW7;35ya2xnv5T0@$&=m^S#0BJA>J6O^Rk0u5*fMuBKLsz9&fDLw5#> z-Xzc39fPfR<2y@=^2S2zq3;wt8%MWQaI`ML?yTnM&9dcplpOugIGQJ|afH|xN1G^u zI9gwmafB?6ej$#2HkkdSNzkT+-`k66Gfk}o{j9)dJ#<$fXmfeiew7e(S4mLpp+*ej z=O-2XY(cEMs`=Scw)|HmKfg47-XX2=gV+~8J1c_td8a1h2U-05PW;?EnBCLlXP3h7 zUB$GkrdEFL6&`P(`vO1jmS^n`$$k31lApY>&>HBTf@BEl{QT~pY`YQtzG}waBU}E5 zlCj?#W4lXhj3M^L*nWy2#`e-=j3JA$2gKO@O}h3koDL|a12whMb$@85hXP&ilV|P0 zgsz85x?(#uV)V||K?HxOnyrIn%O5P+`m3>Zh_uEQVqa_>qX=T_a81S*veja`dSd zjQz_PJ4sq&46!f9&QSz0cDg2G3|WjlC&r#>()HoO>D*%ah^AJ$o(cW+Vxa4z@~pj( z(Dh%U>wjdfwRjxU|L=Vqa`sst981)0&JeWU;l(&}P{y zhO#L`{&VMLh2Q1HbcLo?!d@{{-oKU`Dj&o@C(qi{q1F$;<%Y^%N*fEUzosaNektvp zu`7wb+>lsb{K@?DvgK2Unos7-4gvHkX^k<&z8L$eA}G)oG#O*aVr)e*wnCGxuN6+$ z7t_}@wbHdhfz&<@R}OUDAkW%L30*6fbjAK^#OR%^ZxDRtYPN2aEnlf*>($2Ae@km@ zA@;@AuM|OS{f{PN3t4QfDYjN0%2pl9W)5ZJP1^2~wKg^sepFw*#GbF(=rMj&pV=Ug zAJxZo?mwy@)#*p|SqADi+QdL1_66$CiXc$;8Wx=(3)CEeT4yL*YbeW_i0+q3Xv5Ej z>y(IMHPlPEI6>( zZ@JqUme(r0VL|K*%M3*jglPsrC&{*s4#zHrV@%Nv z2V!41-lzylzh>#{1X(!t6pr18vfYNVU7JwWlBuzUIyo%wH7si@ykSA? z3(MOSK@iq82s%L)mVJa}!BDnW6UYYAw*pyE0*N)*YjQaDH5?l%y5T_V3&%E!p!DBv z>FWepI1UkxgNCvLhqC>fP~KU%Zd**-X=?raJ*cRP{pNF6`25{op0z`VT08Twl7+mn z&@Qn9OB(Y1b)NoixC6lstNy&*QMUZh^7Hon#?emF8b^qIar9nA5H-7Mvd>#&adeD0 zI(jHOvPsZhgS zuWb2oB|pa+Kl@2*{2=zl&k>3se%`0a_(2vwXNaHEhO$$JvPDgb78b5Y7SmChS}8hB zko+tAS%IRXLlMN$Nt%o!WN~z!IQr;Nc5aiP4;6lA7SmapS_%4Sfz5j8fb4CCkA3VzNZ)&Q0LEi|IO!8qF+|c z*k!WimzIoOVvJobtucn!7h~5cf*AX}CSwd)j9n$hu58lv#lq=J#q?!Ot#n-(+UeRr z*H`3OyC$LQ+LEr=PK_A7v-MSiUt7)A*JR7DDcQQ(*t%X?V+*k_w!WnZV(Ugt#ul>J zx?XI3btwCCldxM0zi$`QZJJsM`)cT~Zv?__muKyUy} z*In|geJi2s){?H+UyT^O_t&operq*bcgvQ4t7PjIW9v848e52cu{CokV{1^8v4t$Q zrVMYEEis(EG?cwClsz|;J=0{aCWqQ9hHF1-d}W%!ABQb5T>gmjQlr!OD)>T!M!uOp zH+0P@m+LFyDdYJwQeVNh#mAPf_{+EOt#CGfOwB*7uAyD?R}A}qN-;1-xn62$HraTf z@n1YFHB9N(l(Vsd*cU5rRRjfETa&SZELK($D=Q9XD-37L4`<5_XUh&}OAq_6V(ZJN z_L||^BMo9|5VK++W`*J677sDY>)ihiaJk_oG0T>xOUt7@NA{h$$<9XFI)BY#>=c@k zot2H9`EoXP5c^_hJ4FyXn`tt3kj2h)u`@iJ4Gw41hO^fXXRmEiv%MTdUhy4!b$A&r zd5M?IU_lGqX|~jlEw3-=O&sePj)N4} za3J=D<5WdZ`o~)OIzbkW&4gpq;cVmKY@^|9gW+ubCY00UP}?H8rZ+9o3Wlp=_Rk7%-fMHV01 zi;r!Gvu%d6t%kELn`C@iR&f>Tx^2lsY}RcGBCJ`r3Jtnt!9*zR4hG~i3T!|S`vP)} zA_&MOmcLGr1!PYF*?lgm|X&xofZT0 zUIX(5MK&;qeS!I=A_&7*41-RP1?B*O*>5=8XE<9hobA;_lFKTfp(^_YB>My;3rZw> zlDt%0ZF?<-<3Pi4lj0f<#J+I+P!W{=w=I30APdLg!g1(ucF1scP!q%*GPQy@v;+}b z>ySze2Q7x-2*Yrv!Wss|zA*eo5tRB*Ep?qB3&RP*aQtv~>~Qvh;q0g;jNi)I+EvF_ z!#K8tk$)gG)lrK9InjXJqre6Pu`eJGDuVL=z2&bHWC1x_K+YV_&KS;48_rG{&K5PX zJS2zOhlgwb7awQNEaBv5C|AGromSwnTi+?=t#45Qr>9%rquMY3@M5>VLQ~%Q&M`jz zE@$Hdu`fPePz2HNgeJT7A&ZYsh>!D!v-5_tj}B+&HpzHVR&f9@Ja`nPqRN%3~ezq*^rwcee6?Rzr2L zr3fnQxF+KRS$up+d|Wr2T|1mzJ)C{MNk%5CxC({6u4Ez>_S%97E9}*wu%9oO2!;K! z0ePbW8xX|4fV@=^1Z0louM=bexlurF7|yOA&c512vA#^TZzhi^Hy@RK^s5CD zO3HVI0iHk_NZZttPm3jse~l`ithHtS&Bdx(Xv(Vow~;Yl&PE1eUu0~f2;yKfO;%N8 zk#VcYxMeuIsma7Ur58m-J=fyd^Oll^SkIfvdNv-Gzip{*s{ocNVqdB5t_VtXC(BSL z$V&BxO7;80*>{Jt+nd?$Aye(n|l7RcGi zK11D%HD(v%7|~UpBKnv2Z=9m=0`tC;A_+#07hs(e7I9Z;x z{~gw&Tmf`84SH`0G;b{AV$JU=k>#(i%sIeR1@0MG!S-X|i%6i=)4aqrVJie;&^MIGp{VNz?g-_XWlD2~Dju{Uy-! zaG>dv@~k~H-1;Q-aG89&J4XJBNr?8V{i z`Qhx@CPgdNEKmWu(09z9rAvk|VACG-agu%Uqx!QV}FuoZHoUMtVq<|D1o-dmK6<&A~bVe<>xjj{~`WpAsX>~#d*qMEYT%a(6mQnr~< z_6BK^Yy)}L_DSyg`<9I5jfK`> zdls}CWxEH;cB`OlLjvzxP1#1W<@=PB?QN9Jm)0ml?2EE@DuO86Op{TDEXocQWrvJp z2aRM0Hu>7NaNVw$w%63k*C7Q|>#!pNUpvUNc6h?q5hY)-!x}M+u7d(y2UgIvBXN(Y zrfVnJ^21BI4l}xTme%M(?2E3w6+v|Erpf3+7F{Qat`kPG<43Y%N3stz8QZ7u-nW?c z)6~k?2}0!^c1mFE0D0C<9%=ozj#Em;^2S2zu;UBbjk03{Wgn=Z?0p12rJAyXWXn%3 zDO+Te9W1R;hS(Qn$0~v-J6w}dhAhff({t+CBiWfF*%?i~jw@V`FQyM_YUS%}QJ{a< zIdkCD8MTiDzD|^9?c9W~kCc4H4r|0Py3QPF{@c(Q^7ell@-IS*2>X$0woaBUKeuG- z!^YMr(i&TceX(_(B8aUIX)?Bu#n#1YunR}B&x~ZB8p%E}lAYh=?Bm6P^NZ;MO|6_= z7<%loz}Y9{S-W(k^&bf@D>=&>3$4dK6MF1Zp~pTE&d;ytw@lF|6gT35;D8&abRs?>hGQN;P|5lr8^q$=;WYy)Q{?>>>8W z-ffB?_Hs?e9+wFzlcZ%t|np%0gQF#2;c5~qEd-AN^G}8K0+RY_z zd1Ilq-37Uu$Y*z84s|Tb{M=CX9TqWF&S{BSs4$zhV9NstNh6Z25OfLcU{! z+#{_Kg4h=!e^CSx@_S822(k$Ii3s`8NOotFlLrdFzZTPjnp!#eQRtGN2TmT6XYFSr ztv}rTyyPTrEVM4Uv!Y8LCcw|DNqI!J{AVR8KQ&VRCasZz*cU1PRs@mqm?k3yS)|-8 zQtoOp@^sfwcjR;+*2|VyQC4LrAwY?{XNx$ydYct+mevq z7$Gl8YlI;7MabUE7$Li9GD46=$iGC$V?3RK;gRA8%s24^=3^zi z{2z@@;ZJ!UZE(atG}ym4>ySTED)pYSZ?%87*As?rf9+=I5c@)Rq#~%?2OB7zAPe2| zLig-Q_Vh^hR1?}!G6{A8Z645`EuqEAJuS8W;mT9xdE*}vUa-uMRxryPv9HWeQv@Y^ zyd|s?WM#h0bp2O{)3Yhlvn8fyFEx`tUDnpRykdIu7p{ED^x{5GU6#;!<4>&0y1dk} zF8Ha0)# zjMZ7bzz4{Dx$?YGomX4tpHVQ&9I>y=uU7;me2pcn6J%vRtjq_eXVa!hx^p^lW^3Hab0<-h}uAIkZAtH9(vhAdZ(<^3f9F^io{`aj`C3!+_qYT@5H= zUqJ6x1mXLs;nNASfUYB;YfaCx>Dii1h`%XZe_KrVXlngnSWAFU=ey78Gir0Em%l;( zuRLpWrnlZ+<_2~e3+C|Ub8%JK3v^Pu({LK^o#$~&;QAm&zau*;d!=k^gC&d zBgDQqdPosO&7U;crv$P%T3;NkH$9uzBS9l|a@iVW2pT84p!)kv1AzQvd$5cNN z?LS=~RmErNTY1tspkyg;EVMSNm(=9%EpF8Ik2`ym`esY5P2dBnDO*RjeE*WN{fx5N z(i&xmeNncdB8aj#Yck4^McEOe?6B$C`=@6IH~HGAaGhUF8*6Ii>#zcnb=6UUuTAAy zJ2K(xsFJVPRgDcqU@uh z?A+)Zm8b=b!PU+x{yWJ8%8(FUN@S(W;9!A zG+S}hAL@AlP3@T(MVoBIjp%iw<+qmCj28XHx0aQ3e!Cv5PW{%5d_|r6yDU1sAbQ#; zxtyU*3>0Etpm>Fh0-bGGbb>5UGX!d6G#eVtR%s$SUnZd~5N!&gkrGiXZ94JquI>SY`mE~udJyp)kxmTv3i+& zzN)h1a;F?Ki|nl&<3;voo_cbZ_jS)QP`vHNKq2-8s`28OYYmIgAq&(Tfm&xYTWd7S znux9k(VDRw>y(IMIo2uwSvj%-P$1F&DI;u z=8b0SHk1FZthHCga;#q_pRcDZy&Ut3?5!N@7TI?%$A$*#d)maxf!G(QpDTi}++kRB zf-F#*3Dl;e*~X*UMomP&kV$C6)v;-bD3)X60+5wsqXJMU$L5y#FBQx(N9-%}-z$O= zzS|Pk39>TZR+(=znr$_jZQ0EH4>Gl0*V~kt=UXX7)q+F5WtsZo|FQ8Bi@#LFu-vEc zhGn~cu{@#(f^fe<&?|xhj%M38f&5MSRvw5o zp!6TJ^mT$P9D54K?xWdmquH)aD9_5&dU5YwLdkavHQ9A?Sl(+`o>O?kg4h?9W%Zw- z3c?ba?86XQSoRT?1*6$sO(0XHZw0cT1QKhq*W_^QYdDrubi;wz7mhb5f^e*8>FWep zI1UkxgGRFhN3;E#PlJ=b2_-);)MWq3VR^q{Sw-Ou3u0ebW-5Xpj2Hx+APdVv zVL5y>JG2R;CVeZA!%HBsCWlTA$B~9(RYf-(h<)LhqXKWFc=XwAB@Ow}I!|Bp zGLK*I_}N91@q;XWJ}Z7cJ(_)TG`pZl5%0*6Yj`D2D@C6cB>ygW zaiEB|=F~14ZN0l)TvC)b7FrK|vf$Y`x}bt1d$G>N)g1AnocyAaqYI6reWf*y5c}e& z@iLr)6v#MgybR~_;^=du+2u`w7Ro^cwS5!L=L&4rL)Qd?j@G)`)d@k@lmx{dYQ!*p zF0bInUW9W^H9z(uoU2QIt}=d_FTz3Wi=V~|ZkjK`K~@iaUHp7)H2cbE_N698;Uzd? ziZ|S}_R!Y^$$RL=K+!o+^o`NhyYY=BMR{YP_0U%eo{gg~RdB=$Z)!JIbHrQu32G7Fq-SpdcB7IzPYr-@4fAZ+=qE zn7#hy$0cJwGRCfV#t{2r?3RMD8=Wy^G4?Al_KPN6jd$eSTKMt`oYr>wMQEqH16{l& zr}pcFuDeURVmmcr^v;&OSm*9)wsehTA&ad) zh^^m^X7@G;`&r@FcvBAV!f7S!ccH)j6bSpJJZpbU?%{tb3CkM`t-tP_Y=7|`5#Nh?lZ=CVU96|*cW4eR0J`0uO?#*S&Tg>#vW+W^{2w=&&71VrdGNh2>ta) zpzAO4tUa92^+-uq?5{?Q-uvqTfK?$k=*NT4M{bFSedk1hMsZO~w|o z*m^>2JwBTKvq{)fh2Ou6>1j=^ggqYm>)(N}XXIIXD!IS^yCf`cEVTam=VbfqS)%{D znz83(%bzM4d(s$tURq-eu`kA!)_?de#s=&^yVnV_7<)mCJ=dgbnZjw=Vw$R{m9FPP ze+`V4-&>ZGXYHkgu7R=U56iK?8ZmnBuU8UW?^&w)9<#h``Aa2RFB)6_C9ScA*cV%? zDS}9vuF3ifS!}&wOh2lRWv>~_RvODz9P=O5SC_T+suX+vM+vAFS55^aThPgVt)!V%b;zgt*j`BeL>qz5rl|$Mp>sJ3)&n( zTW2g=Yb?u}xZWd^Fo)lA*C}zuqO4WGvZ7=KtWcD>mig`qW|<@Ql{v4SQsxURVVxi= z^YxYadSltVv25LD=DbO&wVl>0GtcKKMODP^rR$cdFa9jJ_zR-nW>^kZc*BC&7nTnw zf*>4b5OjhpEE@~UMq}9qO(4fe-wI@-5=bn;29v|FiQza_(G3S;UpP)z1f_q1rLPlY z;n+$zwj9egAIsj}gmQ*Vt=+U`2_@e=)a31x!?Lwu`H;dJ7R0`=T%ZVoaIQhn39_(k zFD%=RW!p4?d_wwGAlsHeVokQ09F83f$0rrta3J=D<4Q$P`WIRHIzbkW-GpP;v22&I zY^Nra&lj#&71Pz4T0ehxEvjO_8}1Q4f3J~eZTGR(&fKG9A#W_SOKg{thI}WTr@tFs zORznvKW};2R=)dK^LNAd7)RGhYaAi=#nFw5AZnVg;6fHh`--Ez$Fh2pp#LuXzFADX zimR2Ny$fvief@wy5HHuN?Vk{IKuJ(+lST}?d)6!XxtUl8RP%F-Z2A5rKl>R!-;&n& zLF|j4I~76v+^)$!C6L9>Lh*C>Sa#@Gc1V+=|0!I5R7^kC)JoCeg5+P>j}8?5M4q*y z##*nWqf3hN#zO0%LkpgbqeCh<;{9EPQuYl{+sPA&^LXL+uVUhb zU9J3_DLmdl=LUYBlxOY3$u)Lv$xq%`Xbp5mK{5n&{+##Ue4Zluxz&vQTekeeC1d9p zV^2$Kj3M^L*pja>#-3LoV+>i0oiE1DYtl8Pa9XOEUZJU#uJb}WeKOFsv^;B{Na*@x zNmp#AMvUIsT87}CtY&Lj+44`6Y+Yb%O_kQzLhOsJ*C>Me>%TM^TgYPTQn7XMSaxBP zu-6uTuPdh4YicFz;?Q4L1j2aHTJ7@W`n#eeEN?8d{%U>tR0zV5o*F z?Z9}mv@dooZTb$r&uP)&X!fIO_g1_ZG$AXD_8 z^9l$rcQPQz0y1AfHXP61HlDq8JbTM{_U0y*rQ}fCWW4s5SlA6qIQiR@s~7gI1s*Hx zTgt+|xq#DCVVBi@`6i1Mw$PM?-Prh;Dre&Zu`fPeuL$B}1x>~WviR6qe7s{k+hRQ1 zY&_evNd~WS5?7(H?TTN1Z2eW*9o$K zyhlLZJ)XU5JllCZ+i^VGemvW@3CCW}w8wbuw~gAqlTXNZmx%IrDP6Da&IKf^?T%$_ zw=Yk(Ex`3u<~J(6e2>M-TxiNN?{4g@C1+y?u`hNuPy~@O*GSO`ve-F5?Cdw5?K7S& z7|-?^&-QFmV=rNPPovV?!^?gpFR{}56tq~S7lcah70&l8hzV6c&~WiKC&Pu<7cSmF zBsjc`$=bJgBT?-r;aWJJ9X_5NI-VUeo*mT0^&WYuDT)p@Tnnpl9UgEU8n7G^&JS7) z*U^S+cgKa;7p{c`E?!1txR6z^6NT%8)I z&-DM{x$Ub>f4cOdsHp8u^z3OR4Y6lWDQnw!s{N3qdWHg6s)&81+IS7o*`6x0QvIk> zJ$F1iXFNNrnJup>s-2g7u$)^aoSzfwcGk;Mw@+!y{Jh2LR%pt)eay)Cw499$#JY@$CL4Uo#5V z(PA3Y)XLX`1yt**M+0Bu@~r(W;p@?ouh>2=$atzqt$fHlr8^TN!KGr zS4~=@3$ZV{-lhnmYpy1v3t4nME4rQ@&z>63o*2&_Z!)$);k{uoZKSD{v8RQ~JM4wP z*nD}`o*!@h0{246Sl(D@9rjc~yHWN;pzQGq$~GqO3)PfuB3u4^N!fEo*{0GOWr%%I zw!I>VvMn_kWyqpznF+nUX(F34ku5Rd&xJb_t~(afPMTWzdc_1Nbz{GMMs2x?^2WZi zJZn=YTKQUTf?Knk{<(bYutp4{Ys!TE=xD!WETP!`Gn?PzcOmX_6P5S)cgdDdooL?U zmz@CRuF@J^h<(wupCTyG9-53UWYP6{(e>JiY~_jU)f3sPnvC&UFnJ$POb2ReW$d*= zOk46DkwXIz^hbK_I}y&X(eTEFv<>< z)+j^li?Rz`f*s6iAbL3g8 zP3Twe;?ZF@9vxN7IPBNZHdm|&|`b9An3d9CDVrg8KUX^kVqzBsy25d{2v zO~w(jI9f*>tu>Kl6WN+gjxH)(FD|A_G_`WHR^VuE;OJ6$*5*v;pEv?Xa|1_>g~m}9 zI9juUqss_3x0<8NWy|N39L+Y4u8`I^LhOs9ToJ_4S2Y<&$l~ao;%MuM>>U%?78BWK zO`2{hym={@7Tuz$m8PwQ$}hd`15MwOXKlNQ*2nPe15J&EcImyN;MyqLB2czj1!cDq zc>8L~zAan6T}j!tM%iuB8fA!mQT7u>5c=YUXgWa_W$zJX@1DrsHIePy(7em z=bBpidUpZUF1A@)VrpA|tY@wPPUFl5nni0C?KB0F#*+kYb4cOu)nN!tCzg1;2g1DaY%J4nF1 z$qoyo{Z*c|Lnm5)Ks&4?EpIHeCOfcT-dNi|u(oeF-@Agr2ifGXY6c&YEkCqm@cqUh z??f{O5&L5BX+;o&yu8d9L>7Y|6obc2WXDWoM^9u&HtBn&@P4+Kp3~Gy-*E+U>$#Hx zeb39Yc49)`NhN);=Nd7Ly<-AnM~CwxE7*I1Jx;1-j~AomCzkA;VC=mlt+9vL7kh2q zJ9ehnJ7Xd{t;t)r_l}(*Jl=Na1m5huV`opa{YTg#STQ?hWivB2BTj0MELSU5lt zgzUYVj0I$|@Ex&m+eCKjM0U$Wc2kp%17)q{69uNdz;s){bZetM_=ome8pQC=9s0%f zCHotnn@VNHOHl1+*ZKV0$a>#3bi8fM&>{AP?ifW7I^GCo=#Yi(M?!b!ME1jp?E6h< z$I2ww1+=|^c4rAKUerGU`!8~SV;IlTo`w;z zFN_x{f}mYs&~$<QJwoN^Gg)W zGDqwy^KU4E68@4UtP^Bq{-82{U?RJJBKuP_^BW7-|1PF)YHGcMJfI}~llPHu2g&7G zdw8O?B_An4=Z%GSPrbiHn*XUhZ+;5jM6gGy?<_aVmOotHSspTuZjshFLhOs9A1Z>V zxlNN@d&uJGU*hPoiR>Rug6=5%?kuMN(bP)NWB-r5_W+Zk*xrX{c9*;aK}nKf2OAhf zKwTC}zyK&HC}2PoQ88mcFzc?Mh*>db%sC@ED(0MXj@O*=D(3Ki-_zAK-P2Pw!F%uX z3&ojjODSv#P zMP6oQHa0O+n zA^ICG1#PIRCcBOH9yC*xHPMb!Rb#f%GP6$^4#8n>O@5!K!Ky*7)<050ICs ztTB6M6*YA2LtK>@Q7kJ)-vR+ZpW!4iqKp_-BSy_@(oJiEea7#6y%qlHdz_*HYF@*t z_xBlFhXV8iG*hi=Fy#0n%WfR^TZaOq3rfRj>Vq(Cg0hkTt@8)vC*);XWrNaEg7P!2 zN>C`46_jSpBq#}-Bq)>-lr<5QPBrNcHR&~K((O!Wn)})<{8Kef(a>~)S3%q9779%( zXr{W>L}!(5q0j^cIjeNg@#Tx3Yt+adto*Kf_Hv$i#ed9-Hp54GZAsTHe<0f-FVi&} z$SxAd)p1nMnWg+Qii(tT>uy-XB)`l`MBQ*WH2QA}x1xslyJ z6vY~7ruyYXv41v-dXSQ-Ily2L`(%UItN0*#Wb26Z&cI7tvGBZ##K;(9gdp*88jHR(Ynj&;8FaQ`#{r)V74gR?U{CCkZEIgmV*wbEBH{=$iCM6U!}q)vf%~WSpY0+(`S&HaRX7%c;;zjm?SWxNI!L zZ8E@Mn;e}D<;YS)xg9yjeHp?u!go%8 zy!g^TeMbNE>HX8E_Se(Kz|2|wIaUqfA<@0|lKxO%n`H(uk_rD_zhXgH47$4iFcnNsDU^pwhp$)TAuz;L`~=sxVS{&;;zjMX;xs=c&-!o%f>$#rS* zdQ$f{CK8EJG>Q^_kaP50U5aBZui?XPT=T8RI$=RI-=nC7y%+Y6FdCmO6rV2t2R=3O zPcpf%0SM9wJ#zy#QbK8{CniTpOJz$br=@N>F}V@za8m^6MzqxH`=_t%pT4?( z`pTfCZkD+|(o&bwoAE3oO-r}bn|O6|I4ju`fp&BM%$50C>dg}EJ1o&I)KbBNmWtAB zsgpo+YyZr(q2_8D&#gkU>>tsfG-$CyOtFB?4Y$C-M62m- zE4Qvrw4PX@I$~7ANJmo@%-p7aOnPd4dUCxsbA!y}`b7(F#Aky?w`=HupETmXzPNL% z8MJ7@GP%4{--QdluNky(^p(8_aAIJ{D|^&#R}aXMb=%e_JV}l&jI>YR`3r8T&P=VJ z-*(Vo{Kt&4p)U=aMzoE?5d5KCZOl8pV9ZkA#uffm+W0Xqf9PL6H@G~1!IJ7B^V{}F zu8YHXPjEMp=)ux*qBm}0ax9}a4$+&5=*_54?@*uKJ_z8Zne7V&unGaZtv3Srdrt}A z@LlT(xS6*%ogNoyB1qssD1rnIv?560 zV3-IJIGBgP?coWiu;}b?(OBS`>ZY-8-JVq5&pVQ* z{k@}jI>4*vX^z*x(}CX6Jk9my^EA&1+g!sQ= zn_wtyI02ebZ%zw&bBgiC2g`bMBFc$3XO!v9DFA>sC*vgEP=+_>!<%#K(`VPG&othg zimc3;4sU`XtKoELM!h*V@jZ!Rd)o3j7_Z_dO?yrB$lE`v8q>eCn3 zr!O?#oQCI&TfH#-oB;HVl zH@Cr?Tk6v{)u(ST-dv8X%nc52dIa8F0nMm4w}ia8$#~;~Wxe6ejCgZY& z6!C^Kyty0R+*O}mR-ayKytx)xnWYYIMg`tn2hFHAcZIxJX1wvivff;ea^lTBWqNZH z0N@QbZ^RqQ@a7?S^FV$2zWVgN#+#dwm3n5{a?BEmhDTO|Yxjz4u;#(u6NW!36Sdqe zcu&9@`~e{p&^mH65F66XuyGqS>mHFpw< z`HUp*$$`p$ixOL5KkmDCFM*yFpyf!`JtoQfc=b6+-k$>>bGlVf=MQAdKgjaWOZkVG zd_j^ABk7D^mjLRKEYzb&Vuj+{MPE~o%OU|b`-=pa=`Rw%=Pwe#hDAaHOL~5}$B5_G z$K%AS)PgjDM`hK6DrRZt16}>y@wI0a#kkK0sy8wgOjv-%4qkmqusw+pMJSM{i132&mk-G zqN5j^`QmwKM!k78*8y_s&i(f!F@#c*(y?Ge`@a83)#2d=+=6!hcZhiXg`t+N| zn^%yPdDG#I=}E6bGwRK|A#dI`-uPfyZ(c(=@#cdvy?GM=@a7Gi#2d=+<}-NnNqzdG z`t*m!o41ga`Ox8wnf=~|X4IQcLf(92yz#-Z-n@fy;?3t}dh|B*dh-0R6J3@(Lu>VXZY}j~%%{?%$X&k#*k=PaTY$reV z_rz`<$8J$1cBKRR-^8wtW4A04yUKz61F>7hv0E33-N=E>ZD+4d9DB7Qu^T(ExgqVf zjbpbf61#~5`zK-pzNbIH#?4N;+l}6Cq**Q||58UFAp1?+&P|^dWJu7LjOjamq zUrbgiX%0+QDXBds8z~7klZ}Sm}TKQ2#Xi~!)Ei6>PUwr zO48iR{{|fyk1#l(%a*e)`4bQ@=MS7@9H5L5sS5zdq&wr7?#M%X9D>IJe?cYH4HsM^ z6H5hKJS@!po!rr>dvtXA8@L(bn$f8z1hFas_q<+^@W6&gSe)dg-V|)36RkHpP8gr+ z^NvqZxLiqj|Wy7x|eoY)dJ4zM8_s1z4eiiXkas2E^RS4f7t8Dm< zh~GDkpB=3V;rrv24Zkt**NWq3N325l{+MOMZ$f-8j-MU13gP?XmJPot@%zQ`vm;j_ ze1Gh+;Ws0G|2X~tT=Hk6){-$yK&5FkF=)~_t{PA)8 z2}R>~a^iO;{^oJ~EsDnP?8IM__!Hy!lZwV)(}~}O_*=&Dw<;RHixa;q@h8XerxcCf z)rsGY_*3KfTNjPr&56&~zPxSX_}dnZ-`$DdgZSIU@uwAy-@}RD6Zp7$3vLH^^N`~G z0`K1BPJy>d2_<(3a@V9}G0$X$l65zel}eV#Ojapb%`(|Y$-hUi zTP5=ZlkJoY=}fM!Wb|cn4J895lkJs^X-sxdGW;;vQOQWbWG5w^n#s;e`X7^PD(Nar zc2Ux*ne3{h0W#T5Nn2sEyOL_yo?cUD;mB zx{vM4g2{#yPIAXc8TYX>0f-l#a7^#O!}d4?_pxh1CAAAKxb9F zv4iHy9+P5E8G$Y%eS~91LP-x{GO467Gg+ae-7#6Iq=_(DrKC2QY@{UcOg2^$BPN?D zafc%n$-RJjU0TBNW@ma^)_7CPg2{&Uagv@+8RN}70OCi1aZDe;!+tmfMx#JDps%#OAI(2}|5E561ABwZsG8|XE!yx4hG>7AoKhV&?@IZ5{9%wRr zs1T(cpE@D$D3qgBcL@0qkr5<6B2Iqfe}>#2qHN@f;E(4{`h4h-+<%|aq^@8 zGvxl@W+NX-^7$k;H8BbT`dd&jY%3|Y5%xFHWLruoX(&u4l~fy(6-t6AjZKM5>_Y_f z0=UscXCFFQ@wP)VJJ3po$Ms2Fq` z>Sw#nU_K1v3_YGj_rim$wu2H4f3-zJCk}JbCw{M)Pf9 zD9s?`l$7@vX>X`YfpBx6ApYkN))Vm5YzO_hhJFhaK>3NZVll3!E=3P)+auBNX?t8b z9amuSlIrNYF(I$;xVc21CkZC}*gQW*`luSM7O_{J>0M zX28T;%M16rW?#6ky}*>7%F=WQ&eUFHE^i&W>_3$}3whEawn3J6F*Om7ZE>nQQw!TM z=MpVUgCGuyNxT){zYegE6~BGB+;o;(qRZ_NEvE|x<#r60o56CI>T)~fl>1vs2IXdk z%k2zdN)ux?eNE9l-lm9SvJzI}36m8{jAOD&2_JhNQM|zQT?pCOlK>)b79qcp2ehLa zs@OVp?co#fcB#w2<&XLC2D%%88r5A$ue@wE?G7=(U_gKFReL#Az_kZXdAXVj*_Af3 zx+{bufZ59pbCnIo6ByXBHvpzI^2Bn8`%tW^J6}k$t#vjohaG9wr}k>9pv1m7<#ogz zw7P4AB0$;SiE^#g4MBkw2cSH@E)%;U&Y@W8$w1)Auz`#GI7i0WQ^oXhp79+F2p}DV zlk_Ue7-w$-Al`_?F?|ycH}G&B4#8l1h+pndoKnkhJ$3qYynL_(-z|NCfhfb0ixynY zUn#x3I>XYz2uu)udxM;1y)d$%3_IfC0Ll=E7ltiI!nfxLUZ)AXE@KW4$*Q&V$5FvJ zb|m!bZf7xo9fcEuB`6S&h6taQBA0!~f90VrLuKzy9{sHOZG+EhB+FQnVL@cd_%i_P z31h+_T&}%~5Oo6NNt)l!H7vlzNJ*jYUV9(4k$(&eiNRiQ={Q`2pedsgABW{*(vRYpewc>`aR_?UV!y~4{^=~7GR)>`h3(BUn}$ALt9=IQ zKHb?q$hk3){GYfqSUx*jf~w^|e2w;1I%-X6K#}j)*lD7DX^?bh_AIOozD~2ID)FWB zEq&Pj&s)`;=;6Pb5vjb$o3{)=Fm9c{s(IHGRrHNiQ36%;p)8*-Sk;`U&f~;|tC|yS z@;GtPs^-M%aNjkHl|w@@XYk8)ow%Q^*{)fa?ezSXt!S<2hr) z^|8{W)x(l(TmRoII{XtLS^7 zlHr9C*3EB2-6vR%1PJesf&7yu9I>V}paNr(bKU&Fs^)}VH%G!{T{l0ts(F`h-Tct1 z=0v`A^TVr}6ZzK7kF07=#UW`U5M zeY%(h?h9}N3taIE74ag)%DQ*yq$gp;#g`yNgPL8q<^zY#MpyL^q{NS(i#&oF=a8i#%h%CdZYlL0Af`T8ykCL7+tNtUma zv3&g$fMe1h+pT(%8qjAW{;?*p=Ssm1TO&1 zhW-PT7Y{#!T6rFR#Dd9&f8it^Qig}$0&q3{RE0*AoEFQJm* z1-pml$0ojlZmx$!&3Z`qz{3DE>*3cZFCP93wemdtjs=qq-{K@5Qig|r0dP$E4;<6K z@$d@{frl%glHmorhvs((zK3qEheXYKNch0R05t32zfoR1{2OZJdAO1VlMO%OBpyW4(ldPw-d!vHkv;V&pJ9yWnm zc^>}Gg2{&8a1swG!^2hp9FwlbG2NVprZ@y1{sEN?FW5aa{qRrd=6XoftcQdTJPbgy z9{z>$;$ds3mFHm+zvclC6F7;7l;L4}0FFtoj$^tl4{dM=Jgk69h8OG}ntoUb-CPfe zn)Q(IfrkNT*25~47Y{o?tvnB#00JI1#z{P+3=g{j5Wl^NW4bdB9dQUeYzmbOFW5aa z{jeEyb3G(#)0Uhaz#;Ik z6;x7d;X=-?Dis4;sm}oTwwnFa)-38-i-tC2EdXr*0CU^olnGQUcLBT{UMZ$Q>-*Tw z2U#NqQrbE%x?qf0QyNgQ3&wm;V%x83PUsz_NVp>FsqlV&hgHqH?3zCNB(~$K=0v_7 zrB17w6Zv+OIjA!6d4do8$a{xDD}r+Z{1M}s4zJNPhx{h zmbnC)crlI-XS%Iw;nzD#3`lgwEG@fmoLjtiT$gM7E@|&kQ4IQr#(Mvc903k0ICjv z7=5!nq#t^-Jq_hjW4{imVAH@@+5h8__eaSLV}o_8yt3j2&a6#mbPgL^qF3!;6VgEp zY4~;W)U@fvL@jsk*1QVZlrR1b;-8%fI9uQ)>q~p2hJq6VA^!pttqgt}TKdU4umW#w z4xw3I*0{krmg9}?b*X|H8j@>wz$R~WTe<4i6N&(3T_?)=(9LVHCn&IDJ+a#pyCJSm zvC@+U3vn34VqzJ-&8XG>)y2w|)&e5~Zs^Yo1o*>gDqo20D}?2|5IYhO@Nxs3$lWU1grkcG21f~XArOLq;yS062ctafxPbMCx!uk0?)Fn3$W|7^;4K)A~>gt=otoUI4X8VW>@PP@X`+ zp0TtyaL=-C$ekL-&sEtmBSW=lW-X%bG- z7bs)g*&Kjl(&KSVZ_2}19D;FYE2w06!M>|z_I@WrS2nOhd%r|A<3Wb-!2lJ2V%*Sg zZ%sjY@o)>MmFM9$fPjZv<0KwZhKExDI3_(A$MlvwOvEAZa9gNkc){+W+56oNy15<_ zHR~ba0}lhxtcTN3UOe0yYUO#j10dkxbezOP%J6Up0FFs-k7If}9=5?D@Nh?{WO%{u zq1pSL0o_~=iJJA0@PUT`Xx77>P+mOT5o+amxCsDj8m|duaB4XF)gDL!xFqBz)ju0Gjo1HAi7G@5#gNI0PQ<3zgJND(L>Lpwrk3ipHu6HPkuu|$e2m9=Khy%qbo8E@o1ZXrtIKJE}PEDLyC4jY!` zhf)QGEGmzy?l7SUP)=~7tPfp`Cb;v=vDgz7SaG7*?TOtGPolk%@gaZz4d1vOPJ<+T zC&x6gOVdEJT1>IhlZguA85Fq`-dFlUIk(_v0|H2A;UrCu zGN$0I@B{M=08Jmo!x1R!Q4-<1eR?&H4*S!q2f&*Q&i(Jicx{{kwkD1yg-!6nOB1Wo<;@2XX;F7@L-1|&M- zmKNgzqm@}-2UUE{Ka5j^FES-x3uOG1j0}7j>8_(#<;m;-@p_7tb*IR%DDzqLmNPno z)h?!Ais@npqGBnNHMe5a;e;4Tm%1a3rkV%8iU)3CP^`H1X0jLs%J5bg; zQ?o83P>3+myY?(*iRPU-nYbf3N0++`S<$->4U+R)Jvr-wx^r3H3sCNMqGW%oCkMq7 z6vXTvl*a^lwt!~szL$1KqLY7Q3;!b4dB*GIEUhc5_5ySHzR+d4!yJAR@+408Bg?yx zny~2s2z4iF;X&qHq=kndNV}5?3!aSxzfkpXxZEQwcd;(_XtbOz7?gV~T<&p}yF{0J zBBxyR7qOlUmwO7rl%~dP`kJD9Be0Voj>$f>5>J?{P+}aDRZ95yi&#YQ0@t4=WD`#U zh`eVB8M$38s==V-a|CK!cRs!HveooFE{9uggYGE}-D{WV0K7oX$ZG(XAqRaEH<>w2 zs_s&O4@$n61J0k@(x5L9G@m26Kev_3aD^}gFt4~_vOl+#1LOHHVlIO7Dq!%tV-g&Q zuTgB|Nr!;=I>fr;wc&3<@UGOt+Ys`4;qJe{d?$?g9x<=dnD0}#S_>agxJC>Af*>tF zQei<4Fgs))K`pF-!RT5dgs(O0>0g5-9}_iSO^6Shpk)54zK)olAOqzSphz$N)Csq- z4Gs{Wp(LU%xDY>wXrlfl1n+t>BIhd#H)!D-2pN4#C*7-i?TyS5W4=XZo`~s?nTUNy zHI7x%DT9f51+Ky#K?CdeRI!=W!9MakC#3j|{ zE^VU?6IfpA9~}$5FQJDmQw4uG9dJeWPn1M8i6@A}Ul2{O6R^pA%tUz z_};;+@HNC&t^u_Q>gB|D88N*8r4djhzKsdT5cqSLZjS-C2}%3n2>{_JU4I+9;C^XJAfH5=9Z^kF!f(6p?>WSxIjc@imGv zmWlW-MH#?EoPcmBY49R$K~b8#h+9*X8WNG;mn#`+MdW8YN(M&GlJvq02IXo9#Vl3A zo0xa9YNR$=7Fjy9OLCVf+$vT${~EHm9neURDh()dA7J{Q>3il|%Iy9@_D9NEuWC-{ zcfj;066|g=U|7gzSUFy{idI|IyvtTm_63r*xlZKSq;8k1^N%*E{|9YRZ&K$};~I1$ zJnOLgC;HUhZ8}~1Rn1YoPo$j+Ru~=rp&NZLbn~D8i+#MAo}c|`K0dO=g8v@r3=+D? z2-#Q)nQ=mg_+DybbnWyHEn6aX1&=%a2Q4YjMqJiIiFe&{iA3Pxn*Sg0upzeQ5>Gwf zQ>l5>W!Hb`X=GxFY%q0W6KmwjcnhNL6stU$SRrz^0FQuV>J|*U$lzpmfd>gu|`R0E?81;?gWgg$wUDbTc^I_q7tC|maJ}j(- z54lekBg02&qivoii_f3|Sf4BgRM|&7g=QXT>L-iCR<-c!CyNY7)XUOhTwq3vJz10P`tBOcJoy#{>HeigYj0HmN^EmsH{77Qtd|1dumw9O=6IxW| zU6Bxc6v2ZQP~<}61!KeLSn1Nj_&;A^=$9RIG|ec#A^gB{SsX)9HfCrek6E%`TSh`G zZy#>L!j+!X3<{5B;o0Fo!Nb*NwpwdnG~pXZRj&P_&uv5cq35=nLb=qMdWlr9X|q__ z|Ks(fHl>;=w@r!zXI_GJ^y2@GcBJKgBCH|%w)Mm3_7e(kH&@I+5;XErBf za(n*`v2J`rOw&$Naow9@dDgheIhNyj`CC*$lbVuicQ!WogFr)}TZ)Z5sQ`%EQLL(aMJTf^Wtv>}N%ptza^eF6c8VF01OGnZp*WL@#m)eUeD|c| zy#Q;M7-`h&+7C!7-s~Fl=0oJ=t!)@Ns}v*i-nw&|+Knhrf+jLj+BXsO52OeE2*%+v zDI8@yoiBfCVs}6m)6v4W*#FXz-y>G`|M+<7ubeZCAifxp=ZBd5=8pFQkM^WTI(rCI zl09laqO(%tdm%G2Mg^L9F5NrzG4yP;zc)&vLkbkCaUY6Rp0p*1vxyt&7ug?OjQ5Lu zSr|VnNwYlZVq)BWxEzcSR3(6cI_@3Yc;y~gC4XDVK(Px@|Zmeu+ z?IW_h%qe|f2E(5m0k3+)`EA~gSzsEKaQiv(N;E` z@5Jj88_szADYA*l))SMhSk!ou;QrK`!9R|PKk4}^|D-2f%|<+AKPH)B`y$it3IkCvFnst7 zT$T>9Hm-X6Q3*y5B6eg1+zvSzT1A8Kzv1tZ{sWvA>~YB||I4sSf543x;{T)t0PA+t z=z~eMzZQm2I6waV*_0`47wh14%9g7$8hF4aB9Oi!-z9aq-B_widgkZsnPRnwTQ`O%5f*V*iV|ZH&us=# zLM7tM%^`}V?A7G+0=Cg4uk@ttAa4vr(+JQiTQz4>sBbZRCJd5RG?t|g)n1RIaF`Z0 zgHShF3*#y5q=gAoJ6sD}K#2Zaa-=cQ;Dr3Ck7)B|Pn#G9okY+hH0V}^LGjnk@t14j zpp#iN(i5_)%7|ss%%_A+m`W3l)Fy0G*aUwi95-Rxl1$hxY{E2}aFjM-I&l_`b>U|bLFDnalw=n4L1U*_?x+g(T zC<}Bi7A?BT>`m>+?}Nu`C247!`=F@lQnM)pU20zl-hA!K{$%*9ELRR-(V|_M6E@*M zny^5dFpoH|mu131VbFsKdW;4=l%Nll1$tN*^l*Y6t3i(}3~C#Hjv{C&j}|7qe*5efE;D2}@|g$=Za=3Y%c_>++IJxPsd5TCp{zD^b*RxvMAyBjD8#yi>F* z*OFl*ZY@GTViOx>8(T)%>sYwxcwQei;szRVsy5=LVvMj&z&Dp<#4TYXZlw{YX(MhY zjyu-2I4mv6gge3}ETajhYZLAwPNB+ZVyTQwNk-fqHsT%{u~-|iyci=YEk@i|k`ecZ zjd*}YoS}_)h&b+X+SbD!F3E&PsO_$GTMv5_MNJQTj6%@E9*5wasa<)J4DLbD#_&{_ z;ps5LGh{eRGdxFz*#-KrjpO++#|vSO7s+w9=6IPL?nR%C;gvAMt6_%M$Z(Ekc%v|b zt;*kI(W1wpx2RoSmA{Rmrpn);5LEfQ5WI7>EANxxZ|4+c>%||0K|dtuc^dSi!l1TZ z`EeNZ6M~+vK|dpC<1(Ah=V90{2z!Bs{fe;d%Y^+p4EqgXFVwK#5w=^Iuq(o_-xKyC z4f_LOTa^j>V;FWNVK3IOKNHryP_cEHUkDnkmwyd2{6>aLG{YZcaNoYzy3C&}T6CBB zi`wONnZHrg^peB`SieMDUjd=OYTsskC5jr*DuQ0BK^qg)edl8XZ4w4;O3=$RXmf(j zboOUkO|~FtP?ObRhL&WwTr;#LL!p_!$};J;Vd0|da<#A#ZE3_6+KAPO)5ZM2iu?uP z*jmswaIF!BZBN)MHEhRXU~NNJr!Z`1!d|6eyAal0DYlyK%A!RFtQ)nm;utNyTKkiiy?9edmx`e%6!>&(Q{za{F zU~5@868akeYuoi7M(y43+@nclqG3n<$D?~s#qMRE?b|vin_v&85CnS!1n)*|{szS4 zA9X9o{E=bUQG~ro!){2}sRbIOtqwN|!){F2n>Fkh!tPKe?AS2uIKtkdVK*b}tTJK8 zhhZlW_ErtM1z|TY6Lw-4b`oK4)393+wow1Db@s_D9BFaRU43eoyMCOC!lngoO(AH3 z+d%Mc*Y0dbjzay?=FT)0F4~>#sa@{6bvge@?Cvp@T4{YwtWZ|OS z*_qnqu9tT~VdKuO6asf>oDa0Ge>8HsL_xeCJ#Z*!IHamSn=bun7mzguAo}hY-iT z5pP?J9vTKcjG!3}dPHGRTWF6AgC0fDyESM7LEX1NHcO9Y(W2{XKDEnh7z;`wI;Jp@ zZC*S!MsyFtWLqsPEKFo;XUCza=|77gc=zi1IDw$<`mj~{ujiET+RQ&!bG;_e-VnB`nVW^cfYQWB?NWXhb>H(vS`uG|FWlFHB@>eK(+}Szz2qAy{DC1i^by zSI;eEC{#VRS8i@);iB8fZPa#Gk8NS79Ps z%g&&vsrtJicn|5Szn7qes@_&3%UQVSs=trg?y9%d$o(Y|Jy4j)7N`eHB6_GWk*(?< zMp08Ek3jGq);01NL4Pi5sr@*M7F{1tgiUyoCOo1|c)G9&wkGjRNhUl??edz$b0rZy zUzo^NQ!m7bT%GjA!bG;V_Y#VlCh;-^?@?VJuM*VVBy2tBH5M(pNxU95;SHMbm^R@p z;<%q-*qX%KVbFI7`nU#tuP~_1ulK{C9}x5j4f-#F7J6)9o6J69;iAL!F}2;z*A|pd zN+SBSFp(`#pOr-Pd0`@3Klvg?1W{`V!Fx_etu-0k_pUZq+OTNRF{4cdpG?zf?BpfzF86hU9splcD-{bG%6 zhW1#r=wS5=o6w&oyrNA=6X!PPU}-a9U`Zyd9X4SQO?XwCFqk;*@!Dp>kdjOo8a82F zn(&%7Vg14;*hbmfl1vyDHldCtysk|cK^%8mur)AMk_j77+uiML;T~BM(Wt^iw$X8P zjL5Yt+^{f_t@buTQ8SQj48eOt*T)!wx;uugKE|?W(S36qwacrIO-mx$tT2(SKE}t0 zT=g-bFp;f3Hjfd#iTbcT_}K#5W<4;GLa-i~1i^btSLId&bq_GMs+`QCMOWn%YL{1) zQ%fS+x-gNgDz}LdxvFy8!bG;J+zv%eeN2Pky{+qGIzioYsci(>Aq=`BLEq7!I}y}9 z>)SwQhCz2G=(`$pSArILkdAhv-OL8!?61i_5%%j0AXhqcxq$2p`H_lJ&>>;YS?+jz}hPKpfK#gg#DL>J(RG8 zYNDBC!Fm`A7hMyFQ``MO*%s|1N+LRv+U1QxN0mfWUzo@?3N^%tT%*v@g^6sV(EJ#Y zYeHE7Z8M=9Lm`+@j)j0<+6Y8`C7+s!Ml=E+#~;eZB)_huw0CzGv}e1FMg8zo;&GP#Z?Kr`q|OM6byo5v5wEVP7;im3#`pWFIA;FECl7NUo*i z1$ioXO5S8=vY(Ro$(ii0e%UUa@3yeI>6&GFhwSl|m+mDR~`_$vP#k zvN1Va$!lOtj!^PC7L!WJYf(&YpfZ8;BbB^@#H*u}y#2!DXeDo@Yb)$r6Rh zos=vrn4GC(F~H=`N~UBccTpb%k=#{%7$j#YnXcsbcrXlkJ23-4if{si@K1HD5&Trg zE>Mu4>Nt_=A8GZID15AiQy`d;?ozvc5_K6l2Lx@gspCZS$9zTQHxvynxsK(TtgwKjcXxzUuz4l zC#HMpZgcB~FvE>uhMUOnjb^xo3=tn)uWjEN#<`6+-)fwtF`OG5vAToWxv}bPiPbWa z2C=%6LJ+IFAb8(t3+^VS`;NpGt9!x>_l6mklVOEsxStG>SbgvC@d0Y*`iON?-ro5j zNdq4rq7eA_Fa+=4+JZ-kS>D&QkA)c?4>LSLh95M;Q)F=Oi`jbT(<~YZkEN5s9kxH4DQZjbLFKl=*t9MsX<>QsJoTfKwk@kzE04eH0YZI zb>FMl7Tj;KXwgA`J8Z%`G~s7$!h6JVSBK4n_e(P2gRlu7(u7~M2_MC9enpOLxc!*g zx!r4yrF(rs(x7{NN+D=5pF!|`(-wR|%t$bQcUbUc80RbE{GoBaiQ)X|!1*?e^Br;i z(m3D8aQ=4S{5y>E191|^_$!x{#BsltZ>!v&VkWpc_0M4wexV6TZNhIcoC@UFD);v= z&L707)Hr_;=OO3%#OBK1F%w*_B(?~(k|YGLN}Es#p+Hx$y}DAxqLBvXGNDn}gvKR%^R!HgkThCOChkQ9R#n5wr348EOs_Ao5$^0G~$Y@emhXRJXboRsBxte zg}{~05WJ?^l`do`)J|;McwJezXlJ@n+wF|4L3S^Rs7GNUTlMrrQ4_UZ6oRPrhTt{R zQL7Jil4s%)VBShVPh=pQy=08MD2O&CZV_cFuQb=D4p4kBo^ z1|3XL_kz&|IwTA_l%Op&=z0WoPgpk4^~0dG1Z|~3>j>(eI&7fB!=NJw+FFBdKv1{) zwrU;8qD5EhsIUp6X+j%q!bUNi)sSPGS~sS4?z*Y1W!jD_H})fQ|@ zO!sYxEeM;jXwg9!A2wkEO=zc0*n&9j#lFpiiDA%51YKQ&ZbeXchp`PclUcNAzot;z zJ$Txh=2R3lRkSsQpo+GE;H{xu*^Uemd)gz%)<~vNdw>0d04v*LyB)W!aCP+Uee(Pw z!1iI*>16GoS$B-FzUf%N&LB?E+I9+q&Ln6@4Z2GVw3EY?U8$Yx3YtQGS7wD-cOz?O z&ALa7^&W>SdxmlLBF>r`XP+2O7l-w;shw**xA^i_#J*wH{m9x?vmOv*?dD*elaCco z%kr}x7-pSI*6y11AmZHZTuIqF<-sf(X|Jx8)FELL4y6e_vz^Y^GU3Ru z2}jX{p4x;4;<(?Bv_;|Ql1!LSZMUzs;c7uiM8^~+vJF?qqNwTP3n>J{)o~EKUOHyS zlfnH~rY&YCuxQaO=R|6k7qgQ}B09M+ku7GYps0!2sT6{kod&_{tz)*B3=zlsAjdYu zpF!5!u?K+$aPcm zZeb$Z2=ZQx$aN$5KD13Y`+!2w%|3+S4b@fo5kcLJ*H)DuvuLC>xvKILYL{1)pO!@Q zSz#huRel~La#iIQg^6rc`DKjARh3^s+f?P(6oRV!27K-y|Rk?yii>}J= z!zTQjCakAT_%VjFK5}dW%*rs%PsFL!IKRYjhBYxubK|2NI7w)mDyo3sZJ=?gVmKomIE}(Mjfpc#<1~%ojCSBO3*$5=&W0MNI)<~6 z1E*yerxkHF);Mj5dEfy_$81|^`t{j^y{ZQ1n(w{=$$^Z!7IPJS}J*=k5^kMc@2-r)=FNUW3r8sm)MwGP07n-Otw|> zRu_})l)RY51VOs=Wq zl@TVpD0$_A$*xM?BVe+dlBfSnc31Kgp2;3co}Dwi(wc@&drB@c<1 z9H`{U4U=mtd4j^^ASF*Sm|RE620fF5mFzn+IYi0kCzC^!?7%U(u9AH-Cf8H4+r{Mi zN;YwrtW~m6!{jg}TPIA`DcSH~a=4Oh3MNM=*<4^!DcKTWaswrI^-PXba#zUYC?$6l zOpaEvx@U4jB@1*WH&U|3W^!XC%VZ`uQL@rya*UG2DwAWCtT&k)r)0^<TzT%3X`-j1%ep@rc&6I{RtFXQ*BGFwk?DLqoi#(-YyI}ji6g; z(CLLiZFBn$VbC23I$4A6M9`u~|CwQ&oryC=W!~HIjEtK4^G6lOR%%y0@BcF+u` zkzuiOZEOqV>0yS&VTLovu%l);iwy34cN@dmVbF63Izxk=M^N_@0vqW0VbBW*x|0UI zh@j=YhIKJPgZjKA%&>$EGd06yg&A!1d3l)OiZH{KWY}3VTuladv~3L6gc+_4Gh9c8 zT{OcDWN?Sx#&Bbp;ifRd&1BeBGu%oBcbl{^+!kiIJV!(Cy9 z3>kLQ4EK=1T@N;fd&3ON!wmP4VRy~&02$o%U}JbN%97gU(1g9T3D3oFTwDFmhjCsY&fXg5CE~budu)Ty z%P|vNJD;ym+Z{7oMZ8)P(QAc?Y(4LF6g4B@8x(>S^P3R7eRRy;CWCuh$riJBShVQs zf0x?j#q7P3h~6(uWQ*AcC~9K%A%!4j|AOGn)-n5-4DL0zjp36p!>3_}&&aT^X83{( z?v`w0_%h7!RhZ#xGVG@rz9oZu?Q3KBF3hkZ%m|G6M2DcBk-tiZU7Tr7krgnL~BQdEIq9nE5M7Ee! zps48`l@x;BQ3b&}P{*t>8Qd|mO(;!RwCI>MrMBA@Tjew>iKuyDB3sN_#E4u|TXkU~ z+q}{;M&x>m-3r>KDqB+ss8H-aH+%HOb(PnXUPEVbP*v)|J}snAs|)TS-LS3lrI5)+0vbYW_V7 z6WLlpuNaZ5`S*slsmeYSf~u^6;2or^vM)j14|i-4UW-MGu1b&E?y9so-mfI0{)LHb zRXG4fP0Z31f|w12;2o@EHi!)FnAw{DIxJdr%m!229Wz_y3@M3dXkj8-%+`$&xtjla zg^6sfVEq`8tNGVL+f?N+3PDxYLGTXIRXHLC>iRB8Q9Jj`9@IeoZ)`RQvyLR|p_+9x zaojiRwg$9e7<40o9;QJzA!wv&xjs@FL+xBwK$_o`v0>J6WIbH7ZWd#8eWWx#AFK5v zr3qoy&B=O%W}O&gZI2w=L)}UFSkcV#`?_VAbt|$SsadBG$G!VutG20O(5(r2lm^|F zIl(U8c44(?5b)qPXt$HNeCA^$KKPXfNPG~LQ1bYQ$)u7;L`+sFd9cG|rIN=nOjap* zqQYb&HI@8KHdgXHg2^UI9vd*(RLS-|lg*UuvNPFS$!0i{EtG6ZGg+-<@0iJ!N;Y|! zY^7v3mdVyi_E4E@qh#lk$<>r>Q8L+9$zCFp?UZc#F}b>u-8m-LP_m82WP2t1T}*aR zvN6SEM2MLVN_tmf{8NWCn!rBgkIz2(opH;kyTqAa|mAy>5Rq zDKuzd7YL>??n+@d{Rnav)sEI`yF(~2FWIJxJ;I=S5_G->-J771@yoS6wNDslHgOhc zoc)O7o-}P!%>H4}0|BV<8l9+VAa=#W7ablHrnk ztkxyNk}&I~WIa{0ULIq0Eg7!J$7)?NTp4D)imaz;)@z94?(dB)Kb?Fnix%C^uA>P- zFyq}u_0x5o+)iP!7Vdyx;B zHTuU{wCIpLQJBc~8Nibz5j|Cy$o5+2>)o)Gn~#`IcOPH{VeRyjcOkyI2$dn@|yNE^!e5KSA z821x}z__0wcuTZ#zY@ybaBTPFzp-e?>az`ySrgniEXhN>Q;${%MD>QM7uv&FkttAAk zJc3f3rc<1fx$=<7n3H-!$yCf_Qpt47WQCGRlF3RXlNFOyN~Rbl8z~t%nQW|NbY!xL zl2MAurb@;ZCYvc45twYQq>nP$LP^hJvRX-7XR@V|mc?W%C6&r#Yb9Z3vW*hQxd@?u zUf^9@2;oIY|KPTJ?_d$qj_OzHsI5-nDlN2!U?Sat!d`k2(vfOcYqic0qE+l#FRV#z zch9gbS-ONx=t>i=(I#|fPS7TLgw=Xd?OLtY8$#4lSJ&zj2CWH$rU-hS23;!#>YDpJ zYP;RHt!(;*P3TV(uGc1{V2ZDElCLThlNbh!y!9%HC zU<_WDIt7ed4?4!U^(h3#)k5%Y)W+2jDq@^#x*Hw_9T5gq1ieXvj*Nl2#F5t~* zas{E@kV4?iMi9K4HSs2dig@E1!N*X$K&Z!(DRZ4mblZ}+LS|%GSX-7;pQBrG6HdPX9CYveoo`V`q z@&bdlfDj(k)|Nr7NsHmLgF$T~)o;4b{ZvuljnAq=`>7<2|fmuk?NF;LeSwKKKL8>4oK z5xK1271|~wvnT{1*$skshqiu?7^rKM*^}A@n*LtYDNtW~L&q4m4~4+E*$~h@0+FpT z#g@nJA#ILrH=(4(F_~1-s+g=$QqN3QDybbNtCYCPc1~1`{wu1>U`STP%WDlXh`-VpwHW90zYEDvca zs@6&*23^tXvmOJGkucYjRTZNbEm+h*2_gEr9+}K9 zNoU9gT-h!oDSz?|_f-0K&yEV?)f9D?8->laz*pN{iSi*QQ44Xq3dEn2Xk zdcdLu%X%jU^T^+OJDv*9Oj{1m5)F^6hWHax$L7J_6NbMBQA{`in%-BC(4v5oK*L#4 zov3@6R{(S(v%l8DNf2=DWP-nK2bWgbz4jZHO3j|Oe16+OiH5)0LU?1^@FA#g9S>wDyK%yAp~&+Is@~b#rY4Og;rBi@T@M_E%t8>RTKJ z%%`)6+VUQZ+UdxwdsjQV7{Zh)PrN|h84&YE=uBjI-|0eUL4fkvI29406)aVLg#6wc!bVJrisu65D=jN;X;UcBXkimynpKmT?_$qm*7+=LXErE z{vZ+BtK2r^7w?3h0%H?YY(od>cH69!28H&>hMHP^I@<5+y%G(hP@3(xpR`~0MD{$i z+!v+&zTRtsZ#q0(0#7Bdm(gVj?2qxlUXDx?*ef6)uwp$Bu7sF3uva0&Td4zkHH1PD zO?0pQiRxm{wJad^{2aIEI%FDqu7?17q$upU0b*WzZlqqNDJFvu2O18r{t$zZbx<;# zFnS%8^cyA{=2RpSN*alXr}u&=u5lzLuora9n<1oL1#If-?NJ@*zzsLG!3alJ*pp>P zZ2~&=ifVT1Td4jT@-i&Lt0wDKWMTMyJ)T+jDX!sy>t6c{b3M@!sN2I(j7nlKxaiYT`a}alX5sQ3 zxLhZuKv)K0N+VA|A>K)`s!lxeL}yARF5g9@@On4HP|+_5V}|pQnQY~!L^CK6aiR7% z+AS8}or{+G9eFmSd!UW*zX25k=+{l%7liaa<5BWMetMFZVJQ>-RD+)L}ic_#dQ zy4U_;)RxmwstIswsaHhfK5OZ}yVw3@O5dNq^aH&7CbaS!kgObxI%M@dn7{l(y!=)X zpfC^u%Bkt*8u9KqjLTEeg`nnU=OZ0<0-b>i&ij{#*@@xcDduBDWxs zc3|@_&tyK{6J%gMMxw@be+p5yCLSl%HyGfXRE}z>q9?K1o4PPDH?OF7{8C_@^cQ>2jPh zROTX-y{=&$T;adI^A}vygID~{DEBlRQ@cRfkKGl}Oszgp5BA6MSL|`G*O0)J!GBXB zSfPJQ`@;{7WsHOfl#dO-^%d1Jq+JR8x|XDapI1RZGZA)(H$jYo_rMkY>x=R=gD~%l zJ5_xbF1W4tpoODZOGTAf!Im6}SnSchn}S^xhxIBNs5@P$C8ni9hr?$q>JW(V~ zwj#v6^MT%@wl85Ku2_uBDSbh6YvNF_% zSd0OsMX6V92eOK7PZb#;8^e;I9u_V5Djk??_Lc^5eD(*?g$uq;W5Bzmj~VbPy4S8n zJJ5ih{@+;911)h$^*;${)ZHR_xGipu_M6?ZGvV_MXEPs+|Kq(NZqFiaSdU2~@}yFy zG)6d|>~>G1#8;4P1QTKN)f}A?H{e4Rson{3o@Lbw=!hMK99KN>9cJ zh%d(s%s-dzgfaB{8Z@mdd)IoVUB80Ta@*N(qfeR`#R-M|k8l3X<(i-|mPWm$N6MnH z6AA|t{*TpD=O=#jC;Zm|<(ia-uZe=vncje=*N-;9{x>1ib=JaL%;~R%w@CAiBEqqB~xE8*mFhUDoQ&3v?hQbC~_?E&*Eqq5|lonP{7_EixDQu{P ze^b~<3qMfUSPMT=*hC8}DU8v=PZY*#;b#itwD1dsO||eVh0V0^8-?*&_?^N8E&M@Y zb1nQyVGAw%MPZ^A{-!WV3yCTSTWTRmVJj_EP?)TRN(xi7P(@*?78+65S__RSY@>xH z6t>kuQwrN@p&5l~T4+vTdo8q}FkK7P6n4-;OA0$`p%sN0T4+sSCoQz0FjEVwQP^1v zZ7J-cg?1En)xzo&W@%v!3cG2cJ%!!1(1F4pTIfh&Pc3w!u$LCrgdj6>cXTe(lkvhF zdNTg|2`=*|A)o)^%ly*T7fS?1*6m-Vqr)4PQ780_j%@!BJ4pf=I`y&?!$((m{2wKe zvCWLnT(W$fX6!1k9J!?r@9w+(cPX1<33rB!z{$bzmyF&2yNv#{NhgysZ-TMMKV*!| z+e0uJC)eeS4CJ0b#w;6*_%ds7X5hkE<^*ZK?VDlYEPYYLP84P66tN3M>6{{Vrzm5o zh`lIEZxykIq71Ggu0>J0yomiN$_OpudK9HUi#Uv;48J0dpeP+&#E}$bJQi_7iqhjn z+=QYG&?1hbD8q(`<0;B0FXE{bWlRupF+~}|MLdh53=$%qOHsyj5ig)9qlSnVQK0DkBG}C%0wYzhN28# zBHl|;W*ZS-rzrD)h;LDpXo@`a;6#G}f;a6g_}4VN&G|DJZO8f9+|L+^+32(}-GB|`B+?cPZEE6M@5E@u4y zX5JgfNHjqJ%+}vOoLp`5Uee5aYyWpCn_{Z{CT(ih)cK(QE^WS>-TZe@4WY%(2mP?e za!oH|t=z4f`}w5ow_euv>R!Qoy3T*siJtx)JA2f^(cjestV8}Gt9=$93S`XU`>+Rk z*?zb#E~mEBkA{;SAhd;s-^ttfsc+Juj?b=)TwII1R}r*pWMMZ~hJf1Hq>|gm_5Yz) zp=!)sv-IvqlnFTWEaT;6Lp|bUM?Ggo9Cdd>r`?S)=2l+$8F|oKZl=)}jnrSPzY+ zSmnuZ32|eHsoU_>(tm!kf=?%cF^{dwvVU&dBt0#A6aGD)%w1lc>I6^m`r49e4zEk9 z3k|PP_W1M%kY)ZKJ>BFVhOEHg>sOSRFWrm>e>O#6gK2Hdf7*s<-_Ef?GGjK3V~tjN z9%m)g=%y6;aJ!{k$UfYzOg`GFd!iy)S@Bq>ZaBA0CX)|!O3c`N=7D=B7A6yw*w9KQ z8hYcQTQd0oGB(;{=A0P^&D>|+tXTGa$eys@E;IL;HDmu><{rBLtQj-s%$a#;Vo@bv zni6IYz_hGrS=qQU`Mjom!O%WK^c+yF{EAk7)hNGcSAG-9Npa-0yhm)R1RWW|?Inu5UX8rMwv5o`ucIPfEI zS!pW~5Z~AD4Sooh+R5a1$jV!v-yp*h@jpRO34*_bpt9m`iF{>6qH{p_o1O3%8{tnD z!j_fNCJyNA*IdhrCKYo!&zQLX+&%Z(_rS?>_nR|w_gRTW6$$K=_CByP18`7C^m@nn8OQxMpI;=sCMj*z>@-p&;$wm_ZtVJU{B8EI)qzkTqt%IkRVmOSO^Eu7#}0 zbLY&OIXhHpHK|P)Im|Gx=U^Uchac>O-`K#9cEFEBp2aa`XCCfko?w_abuf>$!*Ak* z-^RdCalmhdJd0zK?95v@nP(X0=?>;;cKB_b@Ov2eSq}JJkY{mhrj5B}1=`!b27Ye` z{GLvXgAK-92gV%aSxnsD34f%4Kg!C2tHI2w5t6YHJuCmHzT9q`9FG0rj= zi|uBdW`js3PeGPtTuD}(jm)iP9XM~FxtuMNGDFWzR-A*&q0x;K#-)j-i3W~uXdFw7 zNf+69FL3c*nxFSFH}6e`_j)K=YUEmES%%oFk!20V&B)9Xid%5m5sHj4X_=jOsf+jS z{Ji(Lc^@~tk3i89iieP83B?1*vWDUbWabIQlep{%#Y@Jd=k2`Dx_DpC&-;p-_dUb= zHWV$PcoSK9L(#G#S@C{;-VfZopBdhdUErVR2miti{(}Ku0Y!^b-@15z%+I^h&HIPp z{nZ8jXMXU%+~7^S1k0yJU93)3BFkD+&5)U=Wj4oUN6TEz@V0V+x6KdU&J8}mfO}Cz zeWT*93Hu_?Qj0an%Ik14*&A7wUW#FOs9|2m!MwH|KJA1bY2ZgV;OmfQaje$Pyq=SJ ztYO~R!Mvdzev}h_l7Zjc0Y4sj7RNTVG0W0vYXd*o0l%daV}`+)?!cIaJd26jI^ky- z_?;c_J2^4-H5hx_&DhfhkxcH6EKA!?R_uq&JpFusTz2&HLybuX*?H%>cn{0Zd$^nT zIKz7k6fHF}A6b@e-heD?C>9|zPbiMZWk)C$8T4etd|w1nb3 zWaSM7C*w=<^Dc4oUTt`YfxJF+&Mx7%*B=4`azynV6PQ4wt0^_0DiUrl~! zucMdjbtEeq!JOO%FS~}A^4b}r+c=DFg*=PV)yT@*^peTu$l847A^9zCicFVBjZJ`}6+H@BF{}KYwhat(j#UkQ>l|V7LzV@t za~v{lb-9%>dLp!J@!A}D7R$yP=KPjzYVu>2p}J-m`soh(X~?t0Y+GbmEZf>J=eKN% z$pl1uruE?`kwllIUmhI$Zo@1Ezb1=`g!|&~cKgz%#?tnkk4u7zL&mY%$ zCO=8wddcO6eu;zrV&qw3b|JDXmYr{y^ILYV$&XoyjJ_UPwwPUu zJd0&l8|M6$U1{=TmLX<$8v3OU`rD9aiP+u>pTn+D@G=vgd$#Ric~zJx4)2@tEc&tviz$joE%m$>XO`3Gb2 z3Mg9a`qst!V}9P1Zr)_KV3qxso%avJo4<4ZX7cmIqoP~hcvRxDBOacyD+NVM74|`v zB~-nT<*LFSCO?nK{g9cb3j5=-!{qgh$wQ!Mv1=W}n?ICmoBTX>t&hw+cGcpt!>%#L zu8p8*3FT;HSxg>@ELSL%$#e7iw7SWwK%Pr(yoh z!Td`;cz(<}d!(&K9IHg0#jzx^EROx1kJ&i3nqh9`V6L{qH%FE| zZruz#p8SS8VZ<@K!e?`=gPnN|!<;i#>y5T{CO=<|_A{3Cg;W}YE(C@zO$kb6s}j7fEN-dY#$2KjkM zx_QSN-f>X0RKyr$St?>$JSHED%MO!IGbW!5MT=c08s7Y& zJl^EzvFmhX=CNxrE<5b%grUxVt-F2Ch+Pfo^xl;+}+IVC;R`;^W$Ugd+)jT-1ENo%$>5E32Z*ZTKmu3D&@>wWaf@3 zX1>theY=$Idx`t*DcoNSn-8&Welx4@-H7`>DcoP0(np^7$W7s65Ntjn4ovC3P}~nq z;r_~$KE{fVQ7L>B!R8a<@RaV$#r;(&+!v?xFi$6)l3ViTHENb#(M^tAuHPo|o8 zi}$?GrJnZeN zO#Au~xh72Pn0QSHn-AgRVe(APV6Zk!K1V5C6Uxk|rUrnLytB~JM~ay+c}hVimAHXp(}VDenWVDM*{Qav*IQS92InXdft zKrrJs7?Ts;`O5O&67-+wrR9G@&<9}iiEN+D?ETQ_cd=KB3}@VGcnYqb|71n|r_X@R zXZiq4sf790fBIlXbqw|srjA5bJ4Ix*VDnkcnlSkUeKbreXfI7pm6_|OnE51s_jOac zZz%5LDcr|k^C1@XpE)cudnZG-*eekaW;BA)Z#B-6pqrzYUz#?B%}4SkGP8GNjm2Im zGNkE+GJV?=)1MEUk7nn>b4 z$U2I>Qe@C9SEj!##qNqPtYP^Gz`7` z1TBEgC+wjx`G$QZjH$vNEcQxaL+$YrTN(QK#dZ~JKCuqS z7yS~Mc~Od)7x=qJ^!JL7l_`8Ihs`JYyZzh;gLlD{Dr4^ud!?)hW~_$MkN5@&`T_Lv zOPF=Ad1gg0xK?KN&e!|IUMVtYX36xM(9cJgNBw7i*xx(8>jPslZ+xfuDKu+DlRrRz zQ9^pof8J+P&5J)w={4`msptJt=KTyEeWdsVCZC1a22-jO`AF=Q76LCmfYC#$uhE=B zs+|(@&*yX5C5FLG_+z*pa$bZ0;O3L5F?h*3e zFnWai51LbiTs_CRI_Mgh|7S{Bd$1_Q^eI=;yM!@ed01@ zUhlXXiQOZv7BG6m)e_Aq;_4}JU4o82OMDSbJ|TC7Db*5p7Q08ty3G;u;|HdP~_)>>hDl0i#D;gVCHKuCWr=D0K9ZvIr)hkcY$Mdu3P%V=A5V#qPnU z7)B31C1_5;XR`3Q8XbLto(Pj~(BolD6?D1SJ%YXtMvtJUpgBd*H%ibm(a~oSX29gh zhpuyHd(S&3^}M&rytkxszQEi0!qm?17Uy@OqYtUuQ_Z`~d*0=#=ejC zPI0*ZAtCMcpZC{P^X~JWcYo@6Gw_9D^*r@3I{HZQ4@^D@dI%<;1Px|n#yq9SLURf! zj**a#Mn|7{tHb0wZ!Pb6k4-)AsWNYUbo7zpB$#|cstZ%9lSCb{S2~u18K=SMku|5I zIfYaWBxC~}ed5ZIdA+Y7B4YQ5t09aYaWz77inz{^xLTp3kCZK8@(H;)OsS-7Dt3>M z+ra1%^0{bE5prh&FJZP)(sA8S@m|bqN%g059b?}lxg|%YV7$_C)gXw>%aBpHC&4;eSL+ItBLNIe< zD&r%5MraUf>}=hqHTJr8#cvRv0)ry2MJB%lbcs0VhJGCjM;DDL!t1xSuIiWmx{#Oh z(xS1$HIw?iJ%o|n#0lfnCO%=D3_~Rc=Q~$11E-LK%#6#XaE50L;*v7B-;_XE`H=E) zWr1n*#wEPbHPAE|>@y|My_*(^iNEp8mqSD0C;&(KQ;z3DreMl(fy|7|%tBSq9A?*t z+w~E4y~wVQwCkg$)S*|1XN{h60*%iaW7o&pWwBkB*yUArS*ps+GP_=Gj~{2($J^xu zyPRm3lkDsx~q$$0_eq1nkxu>RdkkWrxzai_*&!TYqf{3d;EMoBEB|w`Fha9*Lpu+Pl>N5 zynJo)@b##luNT-?X2y&5@%EB^{Jd-*Pp{bZS5+QozGmm=>vs8uUB0QxthelZf7`CV zW0&u8Nx8ShE9PfBVt(2)X3A&e-^ZfCM_&Fu@bLGZr$6}mT6}%sEUa;pRa@BYoC{|-#vWo_45^|2nN(Hoe8A&=`0|%Q&$1v zJvXx|5bwg7)dd|bsHUJ=f@%voUeF0PqTKlhVfLxC86KkG6Sl%XJwp#>1mP>tZOj-t z7X|rT6yiV4a2nbbqY#i{6b4d^B0!2!6i6}35fl?-2#O0jLr?=j4Fxq4WC}V{P%}X- z1f3=5Y(eJ;I#L%!7LEQ!Q6m+SeK7#rQ8X)L08_^1$4D4|} ztH;fWi+Ccnd0Zs~GfpRq$1)B@yIRHqAhnEzKx!F>0jXsi4y2ZGgrFipBL$5TG+NLY zL1S%1wDN#GXkEe0iL@@KHcwjlWFcC!g2+z#lQMNUJIAA4(V7UPXiWlAw5|qHWUdu- zouCRq(}0LRg3-hy@xx9UP54!7zeAPzTUF_5}OyiL#& z2W8$a=ne;E-6`lU2US_>plWvm@v2r^2E;;CTP|pYgQ~0o;(4pw0suq)L2|nMmKuy{uIodPwj4Ok1>#7`6^_Xh-NvFg|(2xIaPUho4HR+Br^9i6De9vhCA*FEl`J`B%66@2B zHDfc7TAybel=ZBjEjA*ZHUI|-hm9UGT>oP~QT}@~50Y(2etuz@ZVRz(J=uy15;pAn zscnR|v$x_Kf?&obc2vqYG`5WFCF4;tLEk$lTR znQz;OsJ#U2kpeGpbK>#w9JP5S!0TiwEgY`hGvn24)YzwRcyF{PXGTWm8)UU*n^qNh zQ&s(ui{J1!%7QkFPtZrP_zXy~_*~Ez4$Az>M#N_;um_(HxjB)~`_$&a=NQ~YeM+|f z5#CSeL*dc1-?M*hRn^VQx7?h3Bz;Y-9up(8f7N{M^7gsI)926rJ`ZR<|M2$to2Sn` z{yqhf z=kcCCYy11m)_k7o?ek<$pY{BG#%-UO877cAe402Y^GpY2G<8sBGeOM-wQx|@S%O+Q zD5JHF=orWW_E@tBHzyu?A!_qjv0%m-Wa(H`R??@WFh6PE2xc@SYw||ZfEs-_nnq+z zbtKb+zsA%l@hoLONoWU)+Ji0xQX+N`)Y(Qv|9oH%`sZ?UBK>oy&69q6vf!`sC2Z^1 z7kZ%G*=sIlkCpbCZrq%FY;>VkkE!6Zzvi=#x6eyGefISCIau>~xwp^DJbe!E_c=`S zneXj$h^Nmyf1hJ*pP3m~0r9eCmI^9kguKWs7c@?+;}ya+#{_Ac=%B1gg06N@<~25= zG#Lf#ktRjloV?a=C;om2=t7=V`EVK4;zt#Fwm@vw`@Mwb~q~ zt=e3tE#oF2mG?J0DDxHvWz7>b-$5C-Iw*62gR&L^@x^P_B57OfpenZsS|aFnL3cQ) z>YWa%eisn?tG*P7FNUk%Eohm8sxAlO=&P;}v`WxD4$8V0h`nU37IdGWHG0v}x01t8bioQxlmFvmm zzdZ*tZ=eo|=^V_QMU5Ue5HqRW_Xa}ULR80%L>2o#x~)JfHp3S&Qtk6^1F3v}$3dCz zIw<2k2W7r5=mS9?Iw|%EwMyl}{X0^;1EgIVj_EL0<^^QXytrY^9G-j$@DjCOIHau5%iF7D^u0cK zldS#;h&-i_6*x_hI8KfJ^6jq}sZwSSka}3L7f3y<_zj3RsLbDi)MJZ31nm>F-$t|~ zyMR5GWCu4VABaCwtH+}7gOongDK)W`GI6ETmN7)yhDuw$v=vBOp|lN? zw&Bt?LfVR?ZKSk~lD5&(Hb&aU0`cLNRScv~5hXxsGrmetnV@lkCO9Z_5|C2+YH7Ph z(6xdl3%X9w6hRe&rV5%SXu6;og02@dQ_u~9W(m4c&}>0-1kDw6lc1Xg-6Ck7p!tGs z6|_LmLP3iJEf#c}pe2HC7j%c9I|bb(XsMvP1uYY_T+j+ZD+R3*bdR8W1+5lzpP)5@ z)(W~`&^kd62zpS^LxMI4+9>E@L5~P}RM2CBHVJxM&=Z0zK~D;LTF_=e&j@-}&=x_@ z33^`83xZx0^pc>L1-&BZRY9)_dR@>Pg5DJLmY}x%yPzF{b_v=o=odl1 z3fd#+H$lG(`a{q@LHh+A5Oh$`UxNM?^sk`64CgEo6qG3_OHdU-RRvWOR9(P0(~fGXz~PXr`bW1kDn3qo6s0<_fw=(9MEw z5j0QGd>|F+t2d@2*wL=nG5Fl5S&%;cHn{0~G^j2Lf4viv9TLrXMU> z!Hmmk=!He)Wz7=q2?tSgaY=r0K_Pu6W2lkwcgb-2BNin*%*8k58tT6H05XW zGzT!vWiSP+W%Ng(;%J^6$N-oSNG=Kvq`Bsr@95NrW%kdi_^ntdl^sxDF5d(kz^!D$ z*UpZ~sFv|G3}{DGJ%wr!D zo5xpy)Xn2-KE6` znLB|Lw_QN$#&|c-=>fW3{Z-obNZW7H_Pez0leYcbMspk#^ru1@nHhgMZB_mj^pAt8 z{wwIPjY#KrfdfU9-T2(n{uXj3f1vv|SvNQuAkM3&^Wp(h&j6b!!@{Sn#A z$CPMK&G>ItXMDyk)zNBy9Lz^+#)o83*=2vn)i%>tRD&6xkQoOB<$yNNR(n+Uv4!~7 zg?v!2=GtZ(dzSEL*tS1q`(O2-n~ zskxGp{KeQ~cr;Qf;{+g;dUb&~^{So-#Hm;HBq098ziK@oPQA>NfsW^NJOxNS?Kl-k zJID zK^+Bk64Y5x7eQSGbrW=vpo;}vBB;Bd9)fxb>Lut>LA?d_5!6>uKSBKk4G=U?&}D)K z3A$WRuAnOf4HlFq=t@CD1Pv9GFQ`CJp`c-ch6@@Ys7TOA2W5@|;v*n)w1cw7*ocnN z8o=Hg-ce+!beIN%)u`Qb!>dJ>FS>X50(8N=IZZM%2kMARJ{mio{6N>OG;W_@>Ry3$DcGK$*gs#L8RIGVqL z9thMJTet4nMHjUh(4u{Zg>QW@cUb81_8Eadpi`UN?JKOG?tCz}U|jyFyyBt5#+Bs{ zDK9RqRL>t$QdV9(w$L0iqzu2rkUOSqe17i4RxNXT7mhB(bL?EFLz9w%p@DjVQv;_3 zs?|NWBD5ehBXmpX*U;~w^^qqd8zXN8|XGS;Y%#VJVvnu*r&YI|goCl*bb9O`@%h?ruHD_;hcg~EQn{t-t{F$>hXG3gb z&SyEV z#WL&*?GGIY9Sr>yIu!al^lxZtct&_;cy@ShcwTrx__pvJ;XA`?!w-ZX3_luvGW=Bd zneemWE#c?FpN78;?+G6a9||81-xpaESs!@-%lSy;Q7q;rEbZ%&HzMyu-oui96xoKQ z{XFt@^Eaa@{ z?C9L+&Cz+$`O#aW3!{soOQLr~mqwRIS4LMw?~SgG-WOdHeIWW^bYt}4=%(lsQ7igf z^o8h)(U+ocM&F9Q9o-uJIQmWWyXX(mpQ78NJEFUyzeM*&4@PI?%tRW@&smUjTh8q{ zcjhe3S%#!om9qwEu|8)*&c>WaavsZhJZE#xb2+afMc&MLJLlb;_i{eW*_!hSlIF{t zuX4W0`7Y;&93*JY&YayjdvgBB*_U$wiFGLF@0`OqQ)4q?Gh?%mIidwWZR6i+JaH<{byrY7|RCkIZf7=xRKW838yk11(VRPg+`tl;6pI6MOF zh7}GeZ_>2syv$&Q-7>y-bdxa!0ossMOOt}q!u;~_g=oM{B+0`{05Tee!SOiuQy3V0)y0)$o62a5_zy@Q)gfKC@-3vqIXxW@k4&r+Mq9&6>8* z8UdR%ZQ80;t5B$QvvbaB&891lCJ}>yf|+jsUDPr__zG^#M z*VU{RAltha(DkPJrwdLkBzNOvIghTb#Ii-Fe)G}i{-l2G0=3)e!c)IJ4FZ94X$7=@ z($5y3OysJOsdWOBe)a;8b?#$`&##}o2-I)hz(C-MZwa~o#GkzoWWoJKpzFDbM5rGm zH7SFOMi-X0iF9m}+pDyAc0VCNsFe#iiwKN=lIg<$>cmpLX)lmca)GU}2ggW$K((@%*^J zE+jYotJnV+>}d5G2Iyx+6+C`I*@%BOR&CW)TSYmS$6s|iGHO84*n;8-Wuc4l@F}-h z)7)-j^GA;>CkO`D?39hYBPo||8cU9q$r${@S)@{7j~D;nNpM4)!?(|6`w z^J%Y(4%H~w*CwaYr#~KFlAhxU?3rCY+w1IeJ6v(}KN)9zaY2(-xpJW;C*e=9F< zbTPi}VXIa`51oeP6_?O2UemLKD%C@HtXLOMBIXdNz&Zx9D&}FI430lNqt?V^2e>>Q z>pgyM2;+ak@J9CdYcRe!{@l{|VH50WN8^&eN*492hY4>Y&;y%J|C3&w*DjEiQFeN; zPIj{D?jhPoq9$H;*RBTJG--a;cs z;)L^P*s6N?F%st%d)UO&gE^sKt#)joR1*KW?rY2%JEpvVvD))ZB!rbb2(|Z8WTEGyM1wS66P3UxMB}2_yBzr;$r& zjSB|s^2Hs8spJ<66J?h&7Go8hFEpebeCk?%WhL*I#kDAB= zo|A{tob;M%h?AUfXJgo%G%Va5KPJTVyxA2A);bC=$dh5ZIyCSu8ff*vk6uO~a0-i> zfrO)h^rmCVo8$@GVBAs~H=q}OG>8WRC#$8m$I(lW-EsPiH1cj5+2&IGcmX3%O&CdU zIT=5!(vjZ*!+>lC?t-1B>t5XtkqZ_rq4$Mm(#$1bMfQbgn?CJ!CLfk44F?~ z3L3bA2HrFnKb}I;xii+r!1@LaOcsVlt)x*emg2{0_$b3Y^lKZ4QyY~W<|-Q3ryM`_ zW1M^B)407fu54^2T`t0W_t3b3)9~Y?^YsINGsgX`kCT1$GK{*HMva}0AG0rzV`(pj zREq~>ri2lzX~fwx@Z+eqfj~?p3U&#ar%s&Ws}x>;OmrU&>vlbUtimw+prwf#>SJ^< zh}0Sy_0dfHxVD{sYjfF)h#C5+Q!rIG7tNXx!)b;m5e%`o2QrzCHsvrY0*BW`!8E zkp^v9gCDSmJA5k7qWT7M;8yprAZO)4|r?raTkYZ-Nyga(rVYNhfUe#28O{X1eJ;P&nzN%}x=kO~OfxnKWL3dFD%aR! z#uSfrcU4+pd=7>P+9KpvLbz0X5_yxlREs5qA#Ll?ua*+&D0){9Tzr0?UhR8#;6>}xD^Rfq&Uw-Lq4UE2`Qz}Ab__-o zII|q%%<{LZMzgcDS&qZN!+rD1@^HTcVk?!jH3GkSv|UYW&|}CL4yfV|XB8H^1iE(9 z8JO^0)DXUrlzC;Nib@LTCJ_s+f~pZH^fy)y>~$kAOe&-AQwPG(szzWzKg?WKUOFzHa%Q7L>{jpQ+7!x|A)}G;oMSKHz`?()+Bokd zEwDOQ$^ug^yc?p`xm_1RKct!>oE;4?0o}kLn0bzLS?-AD`hfZvP<=r64xm#+&)YkU z9)e%j4ODD(So{ONKE~>SvPSKDcjp}GeGWe7cXH%nIGsUD=nRylyw8c}fU9{keI;vx zUBHdC8QjW#Q5UvGRdYT2T59Z~}Cwt%-}bP~}70j~#7~^0ieDG#68(ji zo63H7I$fR`nC%!&E_$vKs5pcW@vlZ;Cndy~gvPA*{KXRbB-O{D9}GOwKR_-D$JmJ* zn3WaC$iN57I5{GHs|WscLu#gPkF{WHq-`ag^{wPA7{>|C-p#N-N(yyH+~XUJ!`YxU z9VLhYlU;Lqplx1HbxYj`A07=EUf8Z}v$ky$Z@tw?(!TR<*Y2El=g>D?GBT@&!hvX3 zg?k1oEgYUV7Ml$2&he&&P@v*=EX*>T!?JdJs3Z4~?&chWK%XNt2;rt|b3L6;3}k)c zk!Nx}C0cift1sA9P1jWm{frUDG~+e3AhW2|18ObkPsd`nzJ1i2wgMIHoy~8auO(Yc zK>pHFpyF~TIgj(TW&MShMJ63-_Wg(Op}p!$@Tn1qHyTnpCJ$O8B`IM13kJsjrp8|pb%8njhcQ6sWm_gEr(Zg;V1Gx#P% z{xjSaYOb%)NwDqd+o4Zhr{2BudS0x~aeUH5N?q;dT?rn+=CS|6(!jK8IL{;ZmO=OF z$i3=;`mX!-9d!RqKwttN6U|!DK|yDq>VbNCcRlw^7=LYmaJu*G*eS0C@`ZK;jwcJI zYM1uy-ls+LrX5lWb+zLQn@R`m3OZ=%4{Rj`VBh!4{4Fv6PdtCi zh7hJ_ufBPGF6+^^{lGxQJJ`oq8~*CdrR8JFpiO?OmJ{vlB4H?&A~%-dxK13a&ii=C zhhI$23erm6hL!xQ5iQNXZX!0*FEi_a;xBaBLu`HLQOxo1R!20D1 zUEd7uuTQW@O;A1Xihhcw>s!gF40voIgnD(*_|Q3XM~g8GuVk}fJEZBRi&Go6J+4jP9I7D7`Te?g;3UW6Qnds%0`olD#`VW< z;0`Gp!;7`V=~+M=o%_eU{Gn_;P953R11)6_p*v#P6Ki7HA86w)C@dd>4^RUY;~jtR zdN)txy|6`dazBp6{kuQCv6a3Mh2dAJqoGFNtXFGkL^Jp{p(rrAxB2ipQchq@yPMqWnI?#}=?ea^?=b zy|TILI|^O%ovyiFjeE~TPrj5z*AY(Fot~}#I+D{%w;ah&amHA7cHlt>TupMC@AGbM z(iZcUO)9$@eeteOb(}Z!YV6hvJtxu!!{|E0>Dt+|bsSy1sS`cz9W?@%+Cr+J<~pOh zdN&uGPeIYi0aGn>I_G(|Uf3FI2Dfx;ir$Nz-fex_J4wJQmSr-)&v3XK5pPYOE&bx; z<93g>z@_NtUNoZnL8trgd(v^{8X{jSnjP+DhTr z0>?PPF)r?g_0KCSE6ig_esI?HerF?5#I`v7SNXJGp+X{AdpLc+u~SL8ILm3?>fL-n zFFpi`flB!2odM_gT7I#Ya|8}b%skH-v4vR;8ISuLI&`)>tah^$u14j~fU~vqqsz9u zk|9N<82O^pq2>STu$oUN68y`~z~w&egXNf4^1R^;7~p5PToRFAlo+V^z!}ot*U~^N zO4E;=A*cBnmQ{YDQ6q4w^tO|0wd1G%`RYi7qF1@jx@F_^C z^0i|)*UwN+8?w6EKnh?({@F<{ybz|ifPPmdP|?+K^KB~Q1a+W{C>n;#6^trzMxEj& zpw0gd$JDB~6D`t)E|0!-EG>L3lQ=tF_D!83ubb+T45%vopupzLw!~iKW7Q&>1p=!>YoJWBx9++2Vj{duOqKa$@eMVo@LVsXM&49G5+v zoT4|j1}Y{yW9Epjq51fw447ItL(a2@;CD8Ll+(50EN9T;b|xa%a8l*XV!C77uAaEK zOSakZ*Gq*r%$4dr$28cU%D$ISX)@PwnQaTHr2otr^ud{GyAb`(cP#JtTHa4m)?S#A z&d9gzk!mXYsdJ6MXgfZa)%8wrFE}cd77i;c&mW;;pRLUJu3O;P%PT5S{QvvcGrJaro*7r2-ZMC;XYjH<0hE0LM%n3| zFX?$4)h_QD%r(ZJ-hS5fRW$=`%1=kr6@4@M1{)AOzDwUgUwlXP@ZtYHO+n9KJ~=MH zG!tc-!k)ol#x>3~lW3aZJPpAkou&kADq05dTU^14Mkr`Hu4BsP*`3X%*=Cb$vvIcB zFxzHXaTdB6b+R|lY+sHqH{v$kYMMQ3`ktEo=!exLd(HG4L%`REtj56e2u}}L4T0wq zo*IH=n^~iZ6EXUdrn9C+`{Dmf+LOmNEwU+uR+xlIQ8g`67b;S198y#VsWu?hI@@fO zZMGCf9bf`m#i%|pYV9&=f$(bv`VlLul_Er}td@!pv9cpSmm}{8XB;_I(~A63cz^_5 zIbZ;)Bl1p&yhFCxKHF@YZJsZ|_lDItU0;q4ZtzxnMCmL?TNOPo$N4Jy|GgZYnN%N4 z!lbC07O5fd04|p?7XYe*RCkcNINR)&ZFUhxLtz42Z88R^T>O%dYd=%NT|%h7`) z&xbRPoT_O>UJ4HgxQGJ=pgJNSh{*eAn|-s*-q~g^3BC+gqk+C0{oUZLzKGIUj@~MI zUXETW`v1KgmoX`PrCpJtYFeZ!-~n7FG8X`wA;`S5JBFx$+R$Zvru@wguD zMs5`%M63lL*!gbg##Gv!riKC)r(!2)fjueMZ{~&LEB4tql9@Zg?Hvb)wFo5g$IPcg2M-(I(SS3 zkMY@NdA3<9ROlC&5)bb2E)}a>Ta(fw<1&f4tb=>zLe;dmJOK}&u#qVMP#s*Z1D9*F z&8vloh4w@u*SbXXHM#o8c;N5TVAdz$oq13-EgrAJ0~~GP@Byd}9yfr;_1Wh1Y;&qm zc@3t-Bm8=oiZxwZlc`6>WfpUJ9qyS6Rny|~5j=px+e`s~>fmw{xXj5mZxkY1(Vj?T zj!Q&elN*nW$IZ-R8@w|Qs;0%`J9t3&pK zs`vueqV1+t%d{4%RhbpIF=X7Hjq9qVp-V1?%b(EGSdyK%Tioud;0)w#?^ag^YaTEz z(0G??j;YAm&*bd(Y$&&XdaCQT+gPI=Xl0G4nwCcU-~sM` zLBabw)uGV}XtXTbTq*+XSN#sC;vkAdftD$5vjX!%#yy%qf1;9v zZK;Pof03_yy!AN*o3+Z-XC>?NH(FUAs-~q6{W=l!ps)?S)#_Yu1?O|6U%O1!%v`*>F8m;xv=ooVLu(w9F zV6!&58f{>WjzueLMAfu3Iu#zEQC$?Q5!Ip5lhEjiY;%(cbeigSx+=0!BntF|;>J0& zSraIPp2pKj0&R8$(sRi6!TN0S&?ij3Hhb$6fz5i_)#oYJCyG|qhpK7m(+nP=)G+79TBLb z>eopXolztT^q%6zIkZ(1s0(@;A0-L2)fGt3A=?M*^Nxo;UCGy0Z+*JKW_{%9^C9bV z5n5Rvs-~q+KX`yXJy5VdREIuaL7y+O&Cf)i{;J;qRSZOtsLvPR<0R0xnm(7Ir}0hF zKK-q$k7Wd#*QSpcDi!u>16x(?`n-A=R3XC8V#GZ z!&PfLt2G9#tQJ+%QfneSK&`7#uv%1yT7N*T-?Gg;BG@F=?`ltM6?yNc~&#ipQ@6{Bieip_xsD0V#xR*dRU z>>nt0NaUKUI^Cp-n^7dnbx6yv06nj>uPbjsPvdZsT!D~0_|x;t_VM5IYaTfdgy5s{ zb>@87ti!Ha|FT-QqLtO6YFcV7g9oU!1O=-_b*ObzsIyruWL60|k2{yEek)Y55=Ek5 z)k5z6RZ|me6?z&qLWw89nyz4$J&^OO3Y_3c>3>)39`at(Td{j#vucFo%KYdM5nYW| zR*b4?DYgL~;OKr7tQggy*zr)Tw#c}TIYtlFY;iQCbbQdFe$30Md~|v0IAQI z3jozY>MW3I5i*;F%rk}2_b`F2_Smq6%Sd0%W{ME4rgf$wq&;eD#gYF2XB;_I(~A5z zctF70IbZ;)Bl32L{DP2qUdU_{GFwaVzr&ii92dC3TjwE4x@4i{XrrR%r?{Nt_qetkPop@t_)TYaPo7*-sG&*`+VC6HtQ<)d|SdA^+hXdMAfu3%7X_; zGY|!zZ>bKAu7*YvL*{r9=t|XZh$@DnNEB$I;>H&!lQn_z(bKp#NubHDKzf?kK6v*W z@1ait`I_vlPa$m9wXQzbus*}k%KA_>EqzMi0s4$Y!TL}g`pkkpGehQ#kU32xDpOs{ zRWS}lqC_)6$+=~pqe(O#J&oC+#3N~rE0JXnBG3)0AHB#9-ETyZDA0VxjdN(RCeUp3 zG!`WZwAd9$&mr3f>vM~TK6A*|VsCxs!e%XU^}*|w5a&&3WqqicmOgjD0~{?t!TL}g z`YeM!OGDRT*a2NVk^+ficvK!#n!XL26Dd6Tdj?-S@*kYt!1?yMk}jD)wI;w z3=dFi6AD&~>QL)ZsP%Bj+#rHIqxwCoiY+J-1$$V_ug5jPoOZ= zMWS3!Y5BE9lj}qDG@eb8Yl|zFo?o_)|DInTk@GFyYHfwhde&9z8CGi>T3IcsrlnR4 zzh(}#PC>zHQ5|Yk33oO#!)7pS9uArRgv>*toPiETwXpG?eajT0FNbA@<*Any46B`t zZUqn9GSZ#-KcO|#RzS*WQR@(zd6U~))8m_O+FfDu)$Lb>=%dw!nANHlrYbE|AVNP6 z+bta~#NT(I);3kcM5Ylsvno_gOOHDPLN!qftGz6V${EW#Y^!s_VZuMyufi#qKvwRK`8bySP1 zPF+@~Jvy^GR832rUhn{QI-_89s19|)P$xTVo)$Jw37hr9=1C&WrRV_h)ID|s(k0u~ zML%RtQ?igY)+tI0(#EQ<;gggwq>lY9!wB>0jY*gnRny{C1P|bKCDQ?*I(W4JuQp+` zb=YhbHd_j*k+9-8QKT9ZsW#rETBCWodXj0i3M2pfF{hSj-dhtl=)&VX<}nI>nFm$V z;z2KUM);FBd;qG0M_2IZ95y?K%?rb3yRdnIP?>=a#zjfTbZ3{1)e)LIk9RIqYs8Ot z+PV39fm#;gs$Z#_X&R42Kk3P`j z(y-YxY<3Tu7mFB6V1-uNx?bukp(krkB?KpHcP&9LR!V3K+n0&l4#!M{s%a5f0}mi_ zH^&b^br87{LY{e{a~bV%ef*yUp7B2ecM(IAb?K#ffQN@RvGnfu|H z$xt;dGEcw*I6TB00H_W!BSB_F*c=u%3&Q45VPe4wqS~sA(3lL5;1|C<1&El{*Mo7F0QzD70ToQU}6?<|RQ;9=4 zb9fDInFCeR;;;=K5c=C3IsnzdVG1}*4x876%}HT%g3$OF*2Juu>`mhumxeV-OR5Q# zh*U6*hJ*b+N9{<1tWcULG zZ+%pU9=Ab{MPYM6*qk3WZxJ#6g%w(92iYQ52|Yg-C?R<3o3AbGElLS(>s!J^4#P1M zp=w%0>Q!MPwNNk-s)NWqAhI%SE)Sb`ht0df<{iSNJ~|ky!^U6w!mf1bSj!Qsv#@t7 zKD@AZxeI%TqVt~?_B70At**4Ns>NN{ds&au(V6w2YFc_Uh6gNc6b0)+b?EUB^mrg_ zt_z!M!{&V=h6yXQ(iZjsR|$P#*C`=*Vb^L4d!JH5Ti6XuqzN1|5vry|NcoM`sp;s%eSQ9Uh=TXB51uREHQ_AjUIc^J!6{2ihT#TF*1- z+VdG#27NuBcGuIsSbmN}?Fk1QDpk`8H5VQbYF~~Jfa(bKHH7*~*nBB$z97+F0h94Y z(xLc@8?g0~wr(%{KUudSn9_Qq(z>Y@cimoRF@~Zui$T@2#25kjQ1eM zJ7M!JQKA^_kVsp%cU&3tb$hGQy1mb#mcRjrO4YPNoeU2MbsR?sKy`%rDMI}?Y;Fyk zA4;^>sjgF0QGtSvB=-x~AKS}DUzYtM?0zw3Dta29hjA&Vh&HDL{lX<`*#qfdwYIuU ztq*~5&&#`v^N4a9Ir}0EaVmciW;$%v=V1h;ZvQ`Hjb@;gHKJ--8r=#Hkmg1dyqr{r zM%$s$Phs;;1U74@E7=Z~>~^%WWK>N{vU}kHlHHAhC8Ihd`va2w7B=^YSgTdP z`&6+8MWR^0DW3db_kbqWTJ$vbC*{-uS1kSDv3>AKY>$UN_mi&!-ukSA&D!tkvyb&z zk5<-)s%hzC!2|T!h=TQ@I`qkibT$JK^WU)fw@CD)>iU!_o<@-?~PMgdf@QbDRj;lQ*sJ$g$}y+4rznja|tav1C7>l_jHUT9W+^ z50Gpp3YLuOknC(oc2>k}5iy&IUVo^r`&6+XMWSA3X&Kf=)9V0w8s{YG)yCCJ&oJ8u z%hf`YtC@#f2gz?6Z@K=2%{s@Gt2N8@7g|{^s-`8^ad@XC<)S*|>H@hsMa&Kn zvwg&DD~cVjde>3K2`Ca3>jYL#hFzp7Ru?^uZjr=m?~7c;EPEhlSO+CLOV(bKtgVM+ zCz9ifyd^scHmjQ}Syz^<9$Hy4s-`7b3?3laX((7Sszb8AkgRva>=iM4h+c;38dt>` zC=&JRt*G)gKS0x~0eTw!lk^(k>ZNCx?Stj&rODO9L#~G8cYwECjbO9-yK?noxf-LD z<)Ug@a&T~b^&@C z!;*IW;jUtqJ&-f(N+ml>HdvD^*F&!Pxu!(S$r1CKh&f3V zD^R@)RWS@jqGD6P%E_=9nqni+)0iGH5fDGqJ7Uffy{=YWuTjOdC=&IW z3kmSK&aA-nkTFlw>pJu_Zb{N>o~xIhVYUyJYj#9F8=8gQ&Syi;jZg)-o#(CARM@Or zT(xdyweXjjm0DCyORf3v0JUyF!D>+*YAr*8EsdCWM$FqI=4}ykk!W_S8n8eW3sEF$ zwp7cpm6~RY(9>8EN&Jv-rK_1`59A!XQ_Hd2wH&)m!;3ufZ81%<(p$mXV6#@Z3NB{_ zm!OsNjjCxWxEday;8GNQOZ<^|rtR z)U!~qdQ^vcPeQ#XBIYL1?K#!&c~!iCB2l*|z{lCzHfy@Qh@QsNk;F%7n_b;3dmyLX zCM7-zcZqXQzC;c-dyDciY}V7RC{M8{ub`Dhp=w&9ybli$m^r^7g>-`(8_{P zH7!AYfCmWjB?=aV>Ja1|2=Z3Md_y$(QT6*t6+fd$)Z{HKOWxNs*^ZvZdy&KkckjEJ zSoT29k~ciEWCuBT-&>TOuvzc9qP)wZ>_RJxLe;cHIRFn3WiJXAh3XLHV~Da<6gj9m z{i%w-P$Vj{Rm+mkG(`@fr}1f$BA>a6=viX>NXU}EY5Zs2g8T!U^{Fe!CoIUnXk|gD znwB8>)mV^0C|D4xLy&zCGp`#h~nCb0b#D|cOjZllM#P``xVM>;x6q0Pda z%#o^Tal8#4;OG{n20(RiJRTftN6lJMv!)PS0u#tg55ofjUc&(cP#uwHBl6Rt<|$FLe$+fEYSxwbA3=x21v<@*-#P_>(utTB zsJ^=v)=5!*phkyIUANg|iTH~|>S=$7DQ?1iOp&T-QG5v=!0ahz20(RCYy^r8qGmj5 z#-e64YKDd4%jl3uv4KW0u2GD+T&$=|G3+*bP^^@NjhX0cn3aiAH7%lB;Q{>KW_|!v z2hkQF+AM0G88uCzxJ`BaSQVe3NIWq#1L5oG-sk#|(F*S>bbcrLQ}i^>iY9I^tu%G) zfqbewQ^~*?Y`R!3u0A7Yt>{zR${+oF4x4pWR31FHWR1Q+D{Dm6v^3fd50K_t6nvJT zIyAZf8l4w4+lW9rRKK07*o7idp!4h{rg!bM*96*)o<_SQf!ezQ=|{NjgY{|Sq0cYm ztG%~AzrtpqFJF^!W!KpwB)OtPjRfs*UFnQ;RkG}XoJRSs zG}aKcQS*m8d2YL;R8w+1(p$1-uvtZ}WFuIz=4fTfsG62!ZQ%iuosEJeqdFujhh(Ku zvm|Pc6}{T2uI*KEA&Nx3N);u}stKB29nsSmpQP6WS1&!QY#*FeC7N7gJ>=?4ekXX# z)dezV#Rj3LF*AxQ1uesFa22!cft+C#t~Azlnq=3y?UG@alj9q_CCi1)n(0b* zJxg{4T3IrxrX|@(cz|R>QLtoGhh+01*)37?rl>hb^ctnQj#kAO6p4D>q9}2OE!6ZH zi=M`UB)t~8dg&Qv```?_Nt0`ihg`+vccHgjC9qiwT)A##xvoMh%SF{Am8+Ou5IqC0 z7C=ES*I~J+4!P>bI-4iO%(^kNPRu+mCU-5c8h_=eG-*d0(Md7)uBC2F<U1(1v($^)TFG24k<1v7F z?1p#dLDjT){0R>Te=mm*Ky~oQ1CJ|W=H)T-GNJMpOo<2g6)qL)a&1j6J2Ea;GM7Ve z&s?aQ7MJSyHB?XtqTrJu)xo6@T=HY)5Fv6D+7pT7yF~Og8FFMihB1$$;hlL{6p z)LHfGqKd945(S#6xXlVY7c%B(0(C=AV|J22b6kP+G_if~8EuA#J{OU%Io|qQ44XCE z)#pam=MuECK2%LhpTY0|efpzdeW(t7?u0(K$IRPe<|2`Z-jRc@+ADDqCAuAyoO{8$ zHHql0ImXgh;_i00E0JXnC74}^3aH1taG=wM)aZ_YpJWzU93?dT3I8irlnD- zB0dTQYeaQuv>F=S6EjzeKxL|5xhlq?NEGNE#f@`lttQZT^fcBa3AEM~NY5eL2kW!a zLmz$-&RTDM_(eEtTz&3ieI{Xc)`zNT>0`g(MqY$Nb?Eab^m#aDZitx=ibUE=aF9y$ zhMPo*9tI^RhaT4?nnMz8iY4yGkGm3C_CU^|4N7O$=s^#S=906=y)~lO-dLMljUHo- zZbmC>MAfu3x*Z+_U{K6jI^=e_lz*Wy^ux%zBjedvWatPfSw(q|n!K%aY1us&3WK5syu z*J9=?qR)EO&-d*&uYr$~KyPdM@Y`?RO4_I2cJ;CBft*0ED3M8^)YtFMcU}1PH*b3@ z#;?D5%T?@6R_tN$V8y7KmSRsUB{s28kdEq5>_aH_zQ|?2Bj*{_mtKLBm`?9&>9kFg zi{6rBY)z7Dn=6-|PPUK#t`@&oXPdWL^jaKitE<*WtQNfxht;BLT57!w4-n}U6r5jF zhgx4ltuJHd=OWlUs-OL)9C{Z{qF`TY`SqP9*!$>de4Dg~f9DEj*#kMhK0ng@`hdKD z=dIX>uvy=_ihaY1eS}t4jH+oV_6+o9M`BGwv4+epc*nw6bDUO-r$=_{Dc97T{mI2cS9>`xlD+Epk;;ovN$iC=`iu{jKF! z&~Wctjz&)-U?g5I1Pytxtml{Qln1MT2xI- ztux>OB4wlC{GvM4s&C+-x?$Ee%sPg7oZ&oFZvd-N+t44XyWFk1hB`;`Lv>(zs1EEr zR8RTMtdk9jr7)7erscTt>q^bD?TlTqeK+D3mY- z0IGva2XJX`m~Dl~M6@RoY3~xzm!R#D@#x4rCc!)NplVt?u7?MNKbgY^pgMS50v;C` zW>>@PEL3K~l$cEyxm2vK+M0AeGA`Yj%MEbPT&S8Bmxb^E3O6wY0IGvaZ*b{lm_3BZ zBD5zG>E#m9*QCdh@#w=m7Q;L9plVt??tuq{e;0=jKy~oA96T;F%mIekPpI6hx~^8m zeJB#ozn7_1;pc{fwe#;9^faz85;JqKtAb?@kn`+Q3;+p?~3 z&$qd((K@uUMpR8pqfPJtY2+1LREI{xpizNg4i$kOSN)z)1-*(ZQJ@0FjqlfsG=b>l zTE>VZfr?y#^fa-3@a{R(L!YO}SCO|qPs3)7aP=9^`fNrk>qFJF^mz>)pwDwC_$)zn z=u-}TN)5BbFvp5SudA+asNzi&i4v89l5@*GL6hh$^fbmBiAT}|S0c+E$T?J^bY_jl zdT2!N?=mKMYxE9m)_7N=ajen1Xl0G4nwCaizymbeih?zwIy9OBjV2rBH6jqbk_-L5 zQpMLO5(S#9xN#0m(**hkJ&mbJ0!?!T(sRi6!TMa|q0hJEYnrz{-@#^0b@i!WeZEI4 z>qFJF^w|p!;JpI{>qB+uGY9(IXqY#MKEJ7czpH{?*p;Zyjo{-X(9N1Y`_R+4Dd`xy z+11Cg2XX@4phPBtQlICYXFmJM`_0~p9e~Zc$yIDFD|QgAtQb|(QY@niEA}@Wv0_w* zVhf?zts+;Z>XfC5Dku`=x>ZZ3+cdeVqNlMqNv_*mx%70hef)Q|s*&^Cyw$1>o3+?g zYZ0q;6k1s=s-~sZ3GjgYItB%+MRlmP9BSQdn0JX_bydF;RdEuEM8WRX@@thQ7`QHPg z6uVF4Izx48po)el66Ly2%dhpCT#eAvSeGQ%dRHzzzic1>J-_HBZ^n9WwM^Kob*@_X zvsz8i%4$(HEwzf_0csVZV6~_Ywe~`-Uk!7&VeT}{?S}c2C`YfTGJZFV&Gs!*7y5G8 zudV{tZadTHR&b{+BYoX%yFp*MrC;!{enRuBbho(2>t(XqU14+Q1<~c0)%x8?enGTq z>2RU*g6Q8^m2v3Is!%m8Ri?uORJj@jt3q|C@;6lZ%P*1J*P&F+gcf$jSEaLb9s1734;+@SZ zaWgY+2IJ;oA+iisli$I&3X@t##gms- zwYW=LJx)aKL1$Kks%a_mFg(D~S`@srREHvUpvZA?^Vqm~Ox&yycOF7L0&C*Z9_Pwo z9SaSdd+cMB9wZ7Su>D@z8fZnPYb$#K^LP|~nFm$V;_)0jfQNd~6adx1<5ciCId0aA znoX8ad?$O2M4NyLql*lBW@aTGbe6F z;$}#ge1Hx{L8K}B7@@Qz_{5zZuX6vz2jytp~Ej{8XPx1 zvDdZ-ogoLgjI4nO*IC>CiW0AFUw3VLyRerc_n(%z3Bt1mS6XJ(;x6+Qtj?L}%<51z zEp;w{2Z+*=MFF5X)G2~G!{cUQ+{}-gL*izhNW(8-%C%SeQqpC(tBbzUg-RA)>3nUa zhiEuY38St0Naoef;YHQ7c+ne(K!;w&#ObTvNMwu$ukyHA8aGSg=GeG7T6kTKo=6In z!OW}Nn^&pEt3=~6R>Pw!@tVNAavfe&O^a8V;x)?QMRly#6!4lHH?N7ClY~(@Ovcot zOQXpyDeD?U=_K(a#fp-cZYu%_FDLfB=1smZnusZ_sg;sfwYbS!!D388XHH(KrX|J< zc)%i0M!}0rb%=2T#JE0gP8TJvM>`}^YulG{_Ig(aJ!hx8YinQC&f-vK!U2a$)wDvr z6&?`kY>p6s>IiinLcKX|&W)S1CE5ir8Mh{#SZ;O$w&rT!1f5w7s-`8zDtLefccI{QqdLS`0x=fH&4r@GJ!pqS+PW=vWzg4cVWoAuokP7B z4meb*rWNWV@PJU)a)ba>N2vEA)KzhFMciB#H8M-fhHb6TR&SZR zde&04f6&e5ooM#I*-X6Ndjj)W_f=Xt)#5JQYSzO-XV!zNY3V^P3xW*Kpx~vWI`r58 zJsymk>*MDAadVA`@hYs)O1mt0&{aZT!1e9|TK8)k=^CYkc7oW*L|%hqCPLM;h|p_= zK;&(XAAss0Vu8rxar3db`G~OCrn-Ktice4^K6!Z@LDD`-FLQl5jw^Zl&#`}op2kyg z+^8u52GGv)v@3vR52Vr7W10ewXsn&*o?no&r{fT<^0yzpgw1*?F5iB5k~R7Yt*jAM z)6$6E1O#cmN5P9tb!hY=GapjTXh z^bE0m@a4o74}E?kU$1!U^E+(T%dS2zu|9vGmGz-&TKXJizeoTD>qB+u^Ck58JZ^p( zH$RS>TScX#RqqEFfV_~ztb|w3YC992AmW--tNtO){NU4)huw+z+WIG|*_PF^|-26fG3aPGP zRYXuE>a|@_<*fQe(<_Re#_lA&esT5Ev�ta{Z*q^@E38Ipp^jZ@FTyS-V}icClOr zT3IftrX|<;@Bq15qF}kG4!I6Nu0P}Efw;LZZvHNcU7&imRYf}#iHiLRR!)Zft0~qV zJ&k|ji8pZnx{6u$K+doON_LiPpC;Mw9+F*1j{o(RtOIP;Kdxkdvt%97%92qvEy*s0 z2T0Zp#sA^%J;0=>vi|?B0R#mVG1ZtDre}s3b&%;W1DHBi=dO0Z!GPj0iNS%vnE}Cw z2@~d=QOs%0I_8{R*L8JwO{?p=t~rNY)9-t$yUslgx9WXg-sk!M{{KJEQ`B^wPoI14 zxu*@dhss)u=*;427Ea~<+Mr(K5*7PnRdr+QWyQWX z$hwW{%l$RBUR2G1z8uFRtfa$o*T{Nn(9s&nsDN&Jn9Z)^+l1b+^~ySaHe|ya)l(h6 zVZF%ZKDcVROMF}}cXdMp6diz*|l^}+tim2>1``LHeC9m6=7Qx-EO&T0(04Th07KS#oMY~wg|G}ZKTU8 zEtmDDoeHvUay>@9i%p09MAM<3`K$Cr%SV%#k0vU7v`Q$eSNrHR$c86NAJthtIvrOn zABm6a<)cfW0U19BC(B3TGkoNOkEYf)PN{F)nS69<5xuN5G<+rZ6Avtnkrlp)9EO(Up)52c(bumXEH&Rm(@><9hjM7#iTC+iwRc|m&DuBtOygI;jTq+S6_YOg8Ih! z^^M*2jh*DQe-yv)LGkoYoXVZnhm6@lb_jFYhal?~*Ow2V9U`4JT>7FFWDAO(x4br= zd99oM-Kp^4zeFO3s6F@*WW$T42m37#evGS@2gS$r^5Boq01tkFljTA286G?m9z49h zad~~?q4kYR$bJ7V(*G%*e!{8TeTNrwZpGXR=Dwdn)*Zc;`&LNz@t7;=u)MdNdF)X3 z_Y#Hoei3P`PjKOB{PJAE7eZf6|&*g z(kWM1PT37tEvJZ&>*W;jk}~8{ygSWuiueqtTnDFILmo*KA@O=Luqm9%J#r0;k{g*v z(je<@sKN25z`&k z(g!i@`hdKscnPXC>{@)!>yuXQ#M{QK+=-9tmAhrofZT~Uf?2r}pOL#4k-O*X8=tLj ze44Vh93o`9n6(a(wdZBl_)Yz6F%#C~;c5AIX*%O2%ksmZ%(7g3TrbN{ga%lClw~mf z5T9ZBpJDlH^^LFAH@;He_%a!P5~Stj@|rY$_*GabDtA#XugD^hCj6cL@SpE?#|FFLCgZjqz$?|)O=)J|$ zeK?iZARod=`^oz$t3ifA)_qc69+IEROb?g7Xw|77$ea$pFaM^e@clyBr|O#J0mz0w zku}T5mX999Rm(@><9hk%8EAlO9>vMJ_rz!T=v(;c>-xqo$wAK+x#xsqoK>Le~#!|GWg*@b}U`-&y|oJ+4~*5g*sf zKW{(-{PRbgEdPkl@J~epejc!)@z?sspUFjU7SXqgr?+t`caf(-#?Yt+IgIuW$hwgY zzxPx2`)s@-Ae`Y{?*#u0F zvYaSB!->=3#FmD}U_+z7p|OelIHO4KT0HHBQ@I~okXid_xEu519w6&>UCWQVNk0zT zUlh?8lpY)QOGh@z%Zg}ZtsHx{AR-doP3_JoWW&2kch0cf8N*e}o#Nwqxw8NbaAy)H z%bnsg+-bm_v4+M-Lt}`1xmOWwEuLoLRPM`IDZe5nQ_PopgRD!g<;#@xC67s4hlt6D zbYdJjZnkls__k(OWDP5VcT)984TCNly{|i^HxXpuqo6MOoqHUaKQ?p`s-PATQ zwT*=bH-YyqoNY9&o?UuaY-(!b>(MekJ76)wMnA%s!@7Zp!BYv-FWTn#;ffz^bTJ;du90L$vcZgMatU5 zX*Y{RYlg3;GMPVl<#FGR8@_%v%GCm``?|s68o0SPif`^{nJfO3=8n*Yc9`hVw2ifm zD@Io=*t9=t5mg%g@K1+r{^M|&ReQPs_Hm-n?yHd*2TvBd!Rv&OxZ;<+^i~2BR4jJ3iIpy75Q_fS$8JCn( z&gv7c>h~q}Z7%9(LFSOLR_Bxpt|_-u$_KinJjYr6ey-{lkoq1M^<9uTWURv}Wh>qm zllp}&>JN6+v7B@)b(WmdassNJsg zj49S{sEn>6ldf=1_cFJ1*QnFI+CAOdDBW8CI+Vyw5IIz_H$dd*irXPnxZ)06c5%f6 zWYT@k>E7d(?t|)dA97FkIZF3wfDW#B5+VmzJPwhgE1ri?;ffb<*~JxqB9mTmPWNTE zbYD}a`?`C&?^3#N19Wi3n-D2ov2le~@t!)}zq_aV5vBW2H{~Czm4D){{5w+qH9&_< zed(6&_v&<-e(wd#YR`WTPs(`7|1!L#9SSIQMinr*y}= zDc?e^d`oxbQ%LzvvxDso%pz z{ceysWNe0W%F|p^PEpE+OUf~4^$}O~t)$*`QJ;g%A!8Y*l&z-IKBRtc7xgn;b+nU? z16_2?fy}|g{an@ekory+_48bHEG8Wboy|DdNrk5MLgWzJTE!s{D(>?ETy}W^9Zn`K zb53`uTe?T6(>>BX-IFQZl>i+|zN@dS24Kjxe|K?O;OT@OVTmO9HKJ<(K=QYN7_P^ z@>*7{C`RWVBxjb{(V2$OsVrxa(R+b%@|OvjgJn5NS#4Q{4rC5K z+YcfK%l4s^)t0r9TxHq8WZ8UhPLAn@%)zowh#V}N=bG{mrF@7>%Kgsj7rLrnLF$im zQGd9z`sJiv?bky|uJY??l>8|!$)5z7gI`xdI+Cwr8GJTO$=~CW{9TYa`0Ngdl$MDH{{0X-W&ANp z`C*roA9Pj^>z^kb&$#G#3Ni=lpKw;MRlES9ll6b3lwWp9`6Xxdu>MWb@fUCo7QXJJ zLeu^PQLzcIPRVK&Z$Y@W@fiPo8<$y-tv&wxF`4usKnIgPfJj;7n)W_KZmp8{NUkvX z69^S1e~Qa4CVxjJe+|&Vt}orv{a&5!5ANxXsJ2_#o@&Q*f2DNQH|NhJSNLNj^eX%@ z3YT5{u@l)<5740q>zqxlfyk{0t4Xdfd1nX}CO6`;i^{>|a zs$F?7$rW}DLa4B72$x;#I+pA@8lZzKkA%p<YK%K$pK@e+vEF}K*)ya*!4 z-uVR(y7~A#lC%8S9nmWxROII>Tz1LN?Zr_{=yc31ufQvMP^hfKZTmhLO+ zbpPm{?q4b0*WHxAp;rE;yYlZz`8VZY*=W{RkU3=d3y74ZsA-=;R17>8SmG|T28@2A zlz(<+bYS(m>mmBv+N_&SY5wI95HBxqLEY4wltI81fX6hsmthk`I5a)^DcA`hX$6(%mbxMCkNX>aFrXS$`kuR7iR+|!*;>2?8h za77114z6g2$nC*8m*nfjq*l=jp~6)QaM{IGOUUE_fDU#orgYW!$|900>{<$;!mdMc z*~P9C$gX1nI=FHLL=Gk&1(BO8k080is(xRv1^-J`@yw!Z5dcri*5;-gPS*pXr1hYttxIah#cmvF>qB)DNl4sd3$H| z+q$Z6B=tMGsIQ02A!BvUDc88B9Hf+eE-6oSRzJm6eTdZW?xKEI$Q&{@-8tnJ*OZf# za@-~5sI&U8tNOi2ecnZV7BYv7rJYi?nrO30{VW&tt*$x_A{_^~=-3}J2NU;oRo_kO zJ6zPayXxpC9epl37C`1;;(S;2OGy2Ii~7Z`I*uY8hdZ0G+)0I|9SV^{y`ohd4WXhM zT!G6j)!@lw(n{xak9SM=6m`0%x~F?7rF#)ThZ4B}B8MvWJct}!aT$aPS6q(EF0Qza zOuE`R-K*Tvyb*gymp)n-DUG3~vsRGBh=9Gl(4SQqd-)lqb5RyuGvfZC%wjlKLH8)Yn7i zkg+=Flxtj54pPcKmz1YEtDoYkeh*T=tBd;SkU3XESCysnE2&A##Xqt>OR(6;Gf8aoOco>>-mnoztD? zmhOCYy1nk{E}?V>06LV&Vu&1W^FByt-Lu`4pRZPafxGf6N%`df9Wr&PTe?@N(_Q19 z?v0f0b#BUUQY*jNUHR9f{EKq1?78(BWDXhr1R`ZAYT8E-xeXb8NOCqbleDG>w2E&a zTsz?HCCk5%(fttN3*cn2n(r6~5{h*w}vsY2$#2|F?S)Po}fO7I#3Ni=F5|pyqvN*}tu?#*t zfRf+OCHZ|IbMRRkL=KkCg2-_RKr4i9RYHN}>zJ)o90;M4Ll;nvdO$fjvyml?L*17A#hH%4M65#+hT|uZCgZXt0SS0Nxi0B29aCDUPAJ9qC%^<4nn7l-%du~3d$*9ZiY-56`FP< zrL2zE>q)+jW$@Ykl>EKm9Q<;(bLw|GYu73sfN<@6V@>mexXd!T_5}J8bNH4apTI{{o@H^w#pDg^ z?bi7Q^^SIpgviaV3X&`A+6Y30U1M?C#jZ-SYb$^buG|752Ukvj$j#*OBv+Wc4TK7l zx5Z@_lk3Q2FF*&oCQ-WTsGLZ0g&RM=II%Pw~L$*!pY9qgJy>8kD8ndAz)0uUt2q!?K%#Ud2o~llFm3zA9P`YQj zDL+@O{5*H%SCH~c0Xk&rVz+cxtJA&GJ>Bam-D}*G-=J20qr37aN%>>tVA+V+Bak^{ z_#udtrKo8SKvWDo7Fc4nk~Poq5~cjSOUlnWtAE;6{a;A^YcA?vh0GyiuQ;dtvTMrk zQOfVQr2Lk%`ZrwFe@yB>1m|G<2hQ5xch;^|d;+23cK;NYU2ga9$fU2G)BVyd-S5@u z{@|YOhz7gG=4o(r#jnmL{p@DaNT^h}ViYdBxMCABX)Hj88)HL=9BvG)VpDaxb0phHyX5ILB%6+~_ii7iOJ&b_Qv>;R#{RTFX9#Z^0!$&&#(*i}pEs#_3Vk}K@m z2||TkJL9s8T{Fn87Jv?}3_|2!vL7NhS2mGcVe+mJDooxDmt9OwkjXKC4t7N-U9~Gi zBv;s#giv8u3YT5%x@xw4gRY+KS<=b$Hg6^#16swJ*`9?1y+R-c0r1-1dmzB5#EsTB zM^xNAdk5>?!J2mcY|qm6z9rTRgNqL*>@vG{wr6Ph;x6&R%n{ZLGgrKfmrQHg)w4bG z+ZT2A@wfgKliXmOXCsUCc*ZW;a?6(9^o-g5aP-`lUR~8)wSTw*@4$}FnDfzzvLd9S6_tpVz%)u%jKXD_-YwNBiQzq5ef(jSJfchq?ylEF4_gF=ttGU`}gSUswBJ z*Bl#|vbb}eNB3;!+1@jH%NZ-G&Z#=S>Wr$JtM9MAz4}G(oz?GG-(7vX_vPw0tN&R2 z7w>D;uY2FE{=WKO)t`Gms{U8a$JJ|UKB<1c=F{pIYd)*~Q_bhq=hl8v{aekK)yLO< zRsEy)>*~MOd{cdI&9~Jz*Zfd@x_71bp_;S2@6@dEK2~$R_newry(?=z_TF9dsrT8M zue_ht9A9%<&FY$e*W6HZTkY*NZ`M3l^JwiWHLGf0uX(rjZ#6g8zE|^V?I$%C)_zy> zbnVYI!?nlMUQv5;?fJE*)ILyqR_zP5m(@OAdsXd|wQFi$tG&ARj@o-`|5^KR?LTUt ztNnBBTeTn8zFqtG+IMRIRl8!W=JAZ!Z1bu~-o-;pjvKdT+?V6N8u#tE6;;Pn9S0Ab zP<3L}NmVDq6K7VP1)rQ(b$-=_RhLvK_nb#2x4RX0`LTy<;J?NxVG z-CcEW)%{fuRXtMmXw_p?PgFf!^-R^XRnJ$wQ1w#P@2mb$^=j3hs$Q@9Yt>s-f2(@8 z>hD$WSA9_RRn;4l{yyo;Nk2~dY0__#ZidJ2gtza3?_Y+uUxUxzh5!Fm{ZaMD)t^*< zTK!q|=ha_Se_8!i_1D$kRDX+d_@Vlz>R+mVt3J+q0(^Ut_Z06c@9Ew%y=QsP^`7Uw zzOw-dnx5d++hS=zZP$7w;S1_q^|WKk$C& z{mA>V_fzlZ-mknrdXKMJiPAW$=A4=fYA&j|q~@}kD^NCTYOY7=++1^8&FwXJ*4$ll zZ_PtBkJUVjl6tY`_ced0d8Ou0HLutF6=nBM&EIO?t9ifXgBrw1%_lXV)qGj=ZOwNz zKcIYns`dlE|Ul-gCbr`Mi|GCUWhd139vwU?qSuc*BerMU(rd2Q|W zwKvw@TzhNnZ79{dYVSeG4x`K;Lg_w=GJmr6>Dp&e$}iNuRQq!6E48np{Qq40*V;Ex z>TjdO-$l9q1F`Tg#K2RNpPu~8FDjN>F%+viEm<5TcBnCET*T=x;6s;kI=qsC4P8;@@Z-BQ#WrYyA^8>=KwB ztYZI~TBc6-O`F;@)z2>C&!(wUo12@(dHOV;B|2y$;X}>Sxw7Zf_qwM2dgr)n{(4jH z=1X3`r@C(D<4^DC@oYYBv`5I!geOo7TmQJf#RcK*o!555M&pZqDEVA)mw~x)EiU94 zAL4!&-0E#Tp2S)?C9dRq!EFNPez=49Oa3FSr;nL|rDd;913rZ!EV6YXEPaLJ}daQK#rgZl8Rab2Rdm6=qud}z$)7UMZSTBG65!Q^In8WS^dEcY}Ty+h`_1;&y^P*D6k);`pZzx)4} z4_7+}a|egohkDB&wxx`eWuSlF0;Jmczf9Hfk>1!fFwj3R(6zXKU}(nT0R+U5XES5_ zZRQ2EL?sHzhtS@9`xTEb@mz{P7ytCOjZwMjJ9@+J3sWzpl;E zwLL3030IC7dl*HWDreM~y;x0TA(1;sZF^qSc-=*6^qp3N@gsl*cl;50|WU{Lu z`*EDr6_Qgjae2Bhi_<}se{UO|jeKWvqy$`}_CiHQ&k3v|S=WBiwO@7ZH(m2oYFedMQK^ln)J9fn zqbjuxDz(v-+L%gh!%A(VN^LCu_MA)Uwl#5seX!|Hk{L~9Wx5xH8?llJ@G!a_!b|C! zZ9blx8IWDZWI>kGT_GFIls0jt*FgAp`l8|U&1BzP0pUwh*u-TAL-w(h`KNN>Nf6dh zlKH)Jb7zHH6Y*JdTjQvQIp8$V*~5ghM2Z^15vTL|2li%{QIdvL|GBkj!W*i;4n-10)QW z)otS;n=fVDFB?E~CW+dbd@Q{wkX6XMH}iU8HDsUC_gbg&yq^Numr_<{=IM~#OERNr zI{)I{5RR7#mOa64h3paeMPCd5;sFTly?AIR%0j#RK{T#X+qhEOq*B|oQX5~XZC0sG zsMI#E)V8S9wye~)s?@fw)bvWNvQpcoQri}lyC+;(vu6qo;NJGW-ov^&Lwh#uxo7FQ zpNsN#M<_HsG+nd~Dn^dPtuzFik0zU=WmVSpko}QlMl+9(#gKK8EX-qk1Vn!zkrCiu zTLjsSQr65pl!UCGWZ^PXHiqmXlC}AGdM%K>MlxeMPj3*iYo)BLevCo(4<;)!^jHXQ zlftI5Z{{I4$uCajO{yCqJB_~A#&7YRAbONUhOaDt2SRub3EP@@ zmDvQ@N-5*FaScQ}NK*p5>U$8f=jm%kQ(09zAHsu480LQ25TY+g)avJFb^HAID&1)N@;M`LDpFTv#cotH!VICS|VNs71@!%c>(f1^3Z7R#< zxe&fcLZhr*wg9r5q^vB0Q;=;b{W_gT@STvoE5GL}Q+gDH|760ls_l3P4<})i$5bUm zx01*x&qWr(BS;wKkLYb6`V)zaX}pRWfb92DR@R#BgKP_#!D&2$cc6&d%8R%;plZU2 zp3T*|c8#uGt83Tk+V#42gRb4EYd7iI&AN7ruHC9@ztgqbbnSLsyF=IR6z!ggGTCN+ zJ3a)HG$|{qZLWaKD`ib(_wi#8o<#X<<4^cHh)$QHvYyn=kew)HJf>?)GA`T6Y_g6C#&&m~%2TEE*>YTH+8J5*{DE48XhZBnIHU8#9Rf9W^U-|FXg^kqo< zJ(3x|vKr)Q2u~(q8?PWIL-YiRQ1kFAs~y5&DfE>IXG3^{6qeOz3CP};GM}FZ-!TyW zOv2W(is@p=M#$1^;aR*AvaO}8sfkDC-4G6v(r{U&wHag^voG@R-2~YtQs(2bn<2Y~ zbQ)#3k3#kala)QlmqECSgl+t;+!1jwvpf!*@1Re0?K55bT-UzPwJ&w;D_#3q*S^uU zZ*}cEUHe|we$cfab?x7}_8(pQN!&r7Q>v|Ht%p^x=t7dU`FLnHL-sbwjHa^Q(cuto zCH>P>_Qbvm!r!rPmU$=#;RPgYYvPr55VB3B*0Pb6TOeCZ-wT&Dy*GiZTgv$3d?Z9a zkqBc_JdiJf@G%k^zOv@^TnIm4!m>WeaS&cDg=LSB2xNClSyS0_VkU&|FkxB!djy2K z%zsl^*xdu+#q`ZKAJ649$c`jgl>2mBh#nx3;VY|}_Jwc>38PJ{3Ai~#%cO|cky}CZ zXA&7rWtGYj2$zyD%B|c2qNhn@lvT-ME@)qV1GKgB8(`h;_W$%Ta+j{%t!ww_+P%7V zpRNt-+WorrfUZ5LYY*w#!@Bl}u05)2kLlXuy7q*)X+D&u`pSa;1mxpa61MtyZFDJQ zFO$qDtKk+x_Lh`2l|AYYgYZWZ;wiub^?V5bNP zwI#Z?RM!sGwPm`tT-OfMwZnDo2wgi;*N)P)qjmg1y>^VQ9jj}{i6Z-!l5H*P3!IH) z_v6X7l|N?J4X@*M?F3z0scR?d+DW>0vaX$?Yp3ekDqTBG*G|{9Gj#1tT{}zH&epYa zbnRSSJ5Sfn*R>0D?Lu9z5kSxq|J_e#iQdHJ#9S7MhBs0naDg)UV z>6WIly6jpACrDv4kC@va`+=0UHkIZ6JP1e0FHYwb))h(zx%UbOyxfc^a-`}-mG_rvV(N7&zwvcDfI z{XJTYEFh5uI1a|qhhrg*ML7C#EXHvNjsYBlIIu-+g7LyqGV;+tU9O7?rbmHh@pS$sQ5BoeH zfA`v-M~fK;eE45w2j4#o$Kg1Rz;Pswqi`IJ!+Ok#^D#yLtvI%HKCW~=zH~mJbY59H zpIADdR63uG^JvjtgR=jX+wlEX95Zpu!m&4wHXO5Y?1N)p9Q)zeAIBUV2jDmm$6Oo- z;b886KK$RC>hq z!|TG8etgz^_%CB>N8pPQ>x##>GO{EyBVOrgh*lOaMwV!sii-`nI2@_OpW>_ItEa_^ z%8sntv$Ae4y(rrGq+>Ss`0?LJYzOpAy*6^gr1DEe%u2=7juKyOU9YbmExtN)y}oJ{ ztN8k?_4~TG^~KlsUcax48bf@&ZT-G3DjM@qbD$&sqt7EKw z%*bLlX3xrzqbov{Y=+TVU^LP*gt~9z5gU)(c+~$3)`ELB+Nc&0US} zHx^gO?u35W|D!8p#d^*1e|)8;=pByG#9Gbre-=}=LRPHPEdOUQWh-O{MwSz$m9}Lo zWJOc7{GX+#Y=x|78<+nRigyY6o2&(|rT_k`6|%vAf12M~BI~|Fc3Kww;?fG)iVS** zrKHz)h3q--_MDs%(Yqu4h$vo;|PJwZyR%vS&YmvYb4cY4do9 zV=H8jpX2eI_pt-VR>*z?+bR=d*3tL>;}x>)ix>AU>iPfX;@Fby|M%9#=KB#Ua$W3+ z2ygN4f4naCOdYGPXZJ4Z>_2p{D$_eOIHzgqoYbO@z9pSq_;bqCDL&uSsW{JB(lIbJ zr=uSm2L^_)ZWt@D=XUfj>hA5CGT$>^d*kIZ4}YVO{%LIIcQa~sdgGrH&R9RihgzB~ zm5&r!c8wme(JvLjxAz$JJ@?-N&C?JZoi>y9_Ht@+`Q2@N&tr4%_H5ch%b;tm&dK5@*qdmaDF zZiyRjxpwToC!Fy=GnA>iV%a9A`DU2@`!EOa#B+)5Dm({v)$Y0H+-PX-)TTrv5zc1| zvC!0z=UA~EwxX)mvtk#q>8rvsS8~ZzGHYhC(NL3uJ4kXy%t&O@$w6U&StRkYF#(aC(c*M7?E@#n+`SEvWTgZi)>{8+2A_>L|1#sa|M@Pv!oa>idI+lrMlBry%Tjia_ z5=>>X>2xBO4|S`&bBF{pk#sy~gw0U5$~yxR%%)O>LOfmwb*sEHD8WK9XC|VlRH$3! zogoRDX5KJjxpb&o<((xG%o&ALI2_J|y6vFl?pZ3qe9nx;BJpgf+m2ce9x6d2o6JV@ zsd%W{4qFZ`lVBV{8_DI2P`4eo99&MIKL$s}A_?T00(Ybc+>48Wdzd7nv2ZjTjw0I> zxtu&)lBsCHh?&SXMJ@-AkYFSdizlKP~iubNyd{2GiO9a z1lh&I$)hD%h-S=GI#&n{OzkU$FDF+J=}RZfd^QqJhuT%)dyE7TYKc@ho(i?A!uMDS zq7u#KW2tPYT@}8^Nidtwh0SO#6KYq5@9`2WL{pJuJe&`;tHSpL37Xk-CT_%Yp?2Fp zJTz8HFc;1y5gCP0yDEH7lwdxc$whJZgxXc%dy)hVRDQ8+I1*}Ch40A{jN_RQ&cwr^ zc2)SELZBbd1T&n@L!&Z$PnBdAcWo?{hDv4lu99RLw{0S8#6a4G!{g#KNv3e$8ktBG zq+L3kJYAAGRDii$-T-MA4=2x%WF9qOA)k(ew9AK+XA37T0mm5ZPWwp10A*GRAsEyN08H0qYxx#k+Lm0&)dH#0Fb!Ir9m@;V9T z!Z{-yMWb%1Dk!g)U_5E$Q)VF^TB-`l8zg9$aWuiQMrf%jC~qXtpU8y6i3D2YOO;W1 zlO&U|NY+TAO}aNO?Cls@(xL6qWQF$ zD=NSSos!IEbJ2W0ivVu2i-?nVNiva&C-SL`2zC4J;pE+tOh$~nnKqHS&%S*) zd5mUAs)!ztWHcF0#?1t7N}sBT9+YGzoGuvA4C2_QDx!xZnN7p< zF%$QOPgO(@OELj6D{9xJepL}YBFQ9DPl+0Psb5t@k4iF;i^tH!L|;Z3o{vc~X&9+Y zGK0>HGCUubWFd;?TQ(5}sml8kk~C4lrZUk8NLAjSlw>T0mQf)FQW>64NfLeVc-BlJ zb!B)yEy+wGjka|Rpej0_kzgd2jN)M#1*wY8XC-N%i4f1k(DzY>=W~*b8&QmoB+;Ex zhUfE=OqgM?*(69+c)lRXWHMr6Bp?A&6`n6jvJg%s!bS`oDrI=SBuO)!#*ju5oit^5 z{$7$Xkfsqv>dNqZS&~tto{z_oBV~C0L6Z4sHXSw4Na>z>h@zkL3L}kdIEBU!y3i`} zGa{REB0Q63BGj%JR{5Mbe;kjDe8xa$rE{Jl?JtN7Bn#C3>=#jJJkh zz9iI-(SSrYoIvNROQrNHA_HhRqpu%9W4ueL^lL)>86zIg!-!COcdx?IZ;13IVt8_8 z(&*ClltA99_?AF_G!`*45z$@h=~k%xj>td`Pwax3N8&w{I?w#~5>4R26*J=K-Sl*; z{PcrFbLo_kkL3kA-_8@)`XiyibUKpB#zj92=)ompHxTZBtmyuK6YEEFJDD)x(;hp0 z{!I7}fdMmv;f5qyEFf*2JpG>}n#UcNF2vCj>lsv;`ZJ+EGoC6W5(c_r^A+y@g+PC% zkk1q{Xo<8_?zy4A5*a}48O>$UY5=J+^fyBNrV&Y*sBVESSCpxz+aBQcXOm$J&ZJ;x zuWcw#UL(?%3Y#(1cW}Nvj==+}f{n19n{H2qFV1456eGXq|(!qm;XT zB%#4f3J;}(h!UW7iSnW!MQk98he9%(L7et=*eF-KfkY$mNG6%ago@kdDT~;X)Jz)kn7!Pk%!~gQ-FeLlqeA5~v+gJX;${Hkv4)y^N=r zVC{Tyb}X?iXbt7eR6%&QXZ|3C%NTL5JUrg2s>Tr=0Bhz`Xkdf36?20(CN!8yf z$u8KHiR(nsPLY5=Ob4JHujGvb+OI+p@zr_O_Wa{~PcSv0cq$Uh~{?c73= z*#buY6A9ddR9A3vOCkfPCQLkjkfUYF`hP1zec7auz_1$JWM_!mxix|QNGhDexLP7K zk8S~;x-LlrPl|LF?X7tOs@t`a$Ur)k3r7r$G=sG30Pgv17@E#tgbC06j-K8Hr5cE% z+e$Q*Mzw0>F>cf|phCAJ)Q^rb9_Se0?;xc-Q`-|6G^5E(*vNzIlLqiG-9fUrQ`7Nu zJTF+XfU^^c4a70Y6+>SbESbRbRV7iBDP}kjDII;Jm7|jg^~VbFLOdCP1w`_ERZB9G zOGU!@d^|L-%MMgddWrNI`DDBxS_%ug6c3;p0{!^{8Z>Clh8FbLBv)BWWB_ds(dGsfmp7% zL9zuil}u#Nn8!;a$zaazNNjUF6^|JOM4@2GVs6Av1p6a#)KyR(nm1on3Of@SKocy5 zhI$Sp6&QC}Bcc9$JYmM71v9i@zU>2E4pWE>M4~2KfRXS8J%ngWfhO+k_q8k zVz~>Z65EVXR19?IqEULt||(<+P}+W=k|(}`_Hf53>w(J(0bx1^XmVFtm$ z0)|+V@w8>bfJ*VMk`?0$m;@|3OvUa-Y;z%R=A(Exl$@(DVt0aD;+SMlC&L&CM~%Cv z&sNP#Vh>42Q~5BSdl+d(ovWtzB)T~g%fxZhSrxy8xi>-tPfME7cp-+zlvVdjd_&Rj zcx1fQ_z6oql8hO6tYJ<-RR3x`LU>C&mP_Pf1)<$3n^8$eGkJ`2q9HCG0#Y}3N{r~{ zWF~8v80r+y0SWVL#t9B$>MCoBIaT3ryT;(rWJord%wp;nZ6@Ju6`LS7P{?JniJS?O zrCMIQBnfRsap#lS2uu)9Sz9l+Hzi?oF|jNlB_5s32o9$S4yIsnKAgn#0=#T1=9$Y# zHW3SlF{maytRk~S21M&Qi&+!lUmN9F%MsdwY2bosH43a~wrO5)c}b`9Ni&j-U`oph zAr);B-JD5;Gl@(DlS?9kY?ynZK=8C2hRsrW(UKBAmN<{*y(EriY&KaCb121VwzYG- zmGBnyQBxS16WY0Qp3Rw(P8X8tcmdJIAdh9c_RlKgr8OLegp?&7~jdD_P4xjv)thQC7U&J2qrvOg^yM29AX1G zGm_6?{6=`#MtSBAAhbD!QGYB$0BS{%qAEX7!s!TF4H(oeg|h;lOK>oiH8JC!wCamR zcDI0M?jT}Y@(DA68jgawq?rd$yQFiGd;&wk!fn=VrJ&~#-E3lfJDCoPs#b)u!sreO z7qZD%9%Ffymz8iQ!ND}9)G>i+xtUm=!!BZ*v1BJ3$3RIjj#WY5Eny51Vv-O86;>dt z;2wg527)4rGPEMuX1NvfiEW8x()d^E{U{qny%LVZ(`igVmZ}UTy@2TESUQ}`n&?*u zHxtb7l7l52HDkF*Dp3k%+h`8=5gddWnH0thtZ24bp23C0wiIHC1Ue(7a3(W&AT5$~ zIwKx{SW9J9&q}(V=w=LtV(uTS!$kE=FgJQJ!P9cNR4i(siDXq866f{pArjAEUN)aZ zXR8>}q@CjfgtrtTiAV%1CM{=6fa@4q_o6|!?H=`$s#a3xlcO2%~ zTtaX#8cC!LF?}Pd5BuKYWwTVWnM5*z6?TXx+_ft9P+|kod;-r-tj&V2ZIstw%Lr}8 zx~u{^f8v&9HgJ2FOBhv0G7`qBE6dNeW)2@lFgmMQj6z~yRfM$7^2{AB*?c4u$!0Nm zDtxSBk03UX$-oA*E`^6}lxOZpLYuMPBNZ1b>8$G6uFJW-M@bl?B`H&k7Zt-SB9?8KXYf=BN7Gmv6UGt@E0|UADuRP?GaZX& za)1%dHp?@38nMkr5)<8Gm8%ubHq5O!UBYm2A{`gYlf+YA1)o815S368>p`pvgII3G znZ&jvqjA#^3#qJVwiRK#c;MYb3b1s=?qptV5ZqB6=nygFDAM< zl|^S1ZCA_BN~154a5|U9Oa@llTj6Zm!QF8w!NEcn%hcmo8!N)uW_b=TBi0|m2mz*l zvY~m($%)H}3=~qiOfrFP!94s>L8&U@RsI!(`tz|wGM&L%M0q#y@xIkW1|o)O^ifC24pa0%pPaR-5c6rKh4FsY65vbd8_3@KqSE{y)6*b;zk~g-C`gp^7R0*&FM5&R>#w& zVR)6p9wazmL^0`YqWv>(k+PC}h){nXiw@!@wh_pN0gr@-i40(_GcWciA!g_i%l-8T zp=heb(%3j=O*j$D{q-oZ%>@IUsxa1=iDDp_N5W$Sw-}}wPMCOV3V48Mem6W$baNVw z%S^IZY!c?GpOA1Ii%>E1o3;vrG;{b#f?KeCCyAwT`QlwkG`Hg^q664lfbBk!7>Yw# zNj^D^fat8PKp7RV(Agh`{pkajVd^UZGg$* zoR+kN>wZbnQM6l=SY{(CRW^(mY2yNiEWOH6;#;vS8{VnF)x!>32relK8F1o zhVAAO&HeT#qMM^hEKNycLk$XLfb8I^Uz2bFE054WFZxXhzfLfg$fU4g5Z%|3lNEOS zndks&!f49CfWo{*)CT0y{1-xl1v7!pk0D6qJ@QvV0|`tHV?RL(B}YveuJsK<(fz`} zJGO?1q9c}<$D72W)r{=~Sbia#CSmThw+L>DCo$`Um6yfBBh|b--X?ll9OE^jms`9? zh~|;`4$&=U0qgZJL0c?6qPgzBNm?{s3w9N!gx@828gA@x9D|Fc;v<|}@*d&AWDIQz zG+$9DRLODg{hiPNmRA(89@G$pqPj`mCls9sBaD^w39C?SmaF{-vFMp+4Aa2sNvlw7 zm>0?i1h-&K3Z9aYT&YlOnmg{FL{H0NRXbW1_H&1<=DzrlaLnCfL2w)^!L56WXs-NU zlFo*)xeDv3idC1A{)p&lkt8Mqq6m=UT}3!I(M&j(NnnU)!J>XeaePZ;z|5thF|qy}#bKkoIKCq^h%rL!_=sE4 zMl3Im?}@gvdAiBtxQtPHCsCSk7n z-xAK|llfGx)X5~x9R3f%Ef@$&WpbtNtMmr9<0qp1kqD;jQ|N`vqr%`3|1*(3tV_*C z3Q4TXvK_%YOTQ54j~aRG48uI@f*zaXDt{$1kTKC0#pI&!uZ{9j`;E|GCKpbo@HDlG z!e)7?d3x+M#LW?`O3y~k;y}WH4Rd#C1P8O&IA}((ZBbM{Hp>-PNHz{vMX@14)Fmo( z1fk7Y3{7HjWUhEm*f6(YB*6i(cM&yOvA3eAOhyqJ%;hk=g)Tr*Z;9pRZa^&7Wr@Aa zVsT#kpz2N=O{fp+|dalQmryJNefXmykl=XQ=GFc8ULe-HLPi?yLc3OhF@ zG>BUZ+l0|55U8z|+qns`O_-KUScN$? z%p$2baBN0o5QCa20|TKzyQ!GCof9N$ z2eJJ>f}I5z+U=Hw%&pi?vZ)-F1Y({5tn>tDwANut>Z)*fT44p?=js)_Zd z(h*F*V63g9N45ROOJo54&*Cl@v*_di9y2u(#f(56OW!ePC3h-tw3g5yCSD8J5GrPi zyJ@72`>KvuKSt%^acuksYqyAb2}~w3kd4KSR2T!$Ank1x+<55+kV+y;Q86o732)X~Q(D_*fpldzeMW@D+Cm^)*&6^Exw7~6DWX0!-PZ*h1A!Dtbo7R2gIq1ldW z?$})kZH}i6Y*7`9DEnCL#`W$-us@9#5o9s&4%mLub4Tn>WOD+q@xn`Wgd~jE?}yWI2ugU}$}-Ggb`((*=CTQWgxa}qsWyrjS~SXN5hh9toOj1uM|*`$~( zrpkr~T8hwSEZdA3c)OKA)p<)39K=4lFc$1udX=?!hFE_zkA1NjR3d$LsPmZ25*SFL z)nVjv7HQX^+}NB%F3 z7@0LN=5N(ZgR18DUWEGNsYnV#Bw~e#Z75H^mB=6()X}WiR?x9{u+uh`NBB%)eW>md zajWTRgS={-MW8>C#&mXAv|}hwJo&we^kErg9y8>~zTNTRD%%M3r|^`+92lNogQ`kq zwj_;0B8u60+_QtKyzfI~Ac7Hij1S|XBtx3}eqTa^m_o-B6nmXJmZ=-a`$@KtHb6#& zTG@={F5REl=4dv7_lAjzV3|V$d5(nB;-z~j@jjkq4h`f32=-wQH8z2W2D0r1?%4wg z^kW79kA;L8>Qr{C<`Nme6Cr{X`w>Cf5y1U*5TX7gRtCkf+B?*#?4`65iLD5zVbS>m zsM0x)NM8!?)JsJ00>w_dvf?@FAQ1Z^F~F3Lfm4M_CxHRH<;*ma7@7pBO1z6u>j*b>PX^z*y(Oyr2?jd?Q-X3bQFPp z=n@l;m~v>hNnS=r6N$ww(VStTYYft^t++o|NEC}7QW&Mdj9)vwo`Ivs5E@M4O=noc zk8yLLwpt!{#}ez0=6RHNa3dAhzz9A+l-`BLhB-1DL3GFLj9PH$YSCgq&-Z_ z^M3+?0nFo|O@ns=fK=&RDbZvKPR$sYfo`W}1yBA&Lj73Y6vKi{kjoTVI*GtQI+4%j z66iO8R3(2hp?Iob>yUUwZ6EE+=XpAXNFSEEr6L#s4fWaMlsrsMCD0#FW5WU#rUSIY zo~v9XNo-@mI#9f5ppTxCoIH(4jJzfbcvgh^*x)BG`O_teH&fybk?4-~u@OSfo*~%? z*5ekixErkc0dyv@0c;Y*z?hh|!C;4?4{{cv=tN^xgLs9Ce2WLq*V#k{@k&x`ix;;P zYpro(&mq=_$9goI!S2w$&QkKc0L~>akV~cTA}Gvz_Q`e%52^DA4Wj9Twc_v%r!xN+5bDSKIdfPohM=OxH_!itLVqCF~N8#2NYvB7+}@&+Q?!dnJ59-1>u2xEkiNhh}})dQ4hr+N3SE)kF|GL zqlOWBImp7@e?5@_JfX9(4AykBF&3`$28rUui!4aTYpEazkv5ci8n}twY74;-bN&rDCO}A$`qb#>S5&D3H4zBB8hbuc&^*| z=TUVBfqwBa+DJ^ixPcmfJoP&zDc)}z6+@nV%JJU2Bw2{35~g?wgItNjb>2;60Gm_t zc#nwy?GokAzlTW73?#9cO)SP!j`rRwNvwUr%ml`z`;>2|x{t^JUL2c=o7k%d(smP1 zepsT|d78||#R44ptm5eX5{)D?7^lHNQD0w=-J0j<1B7DVDV|dq?3fp*UHCjq9wau9 zz}jX!0Z{nz{^M#NB2?TdVowFyO6;!UY9A)Hxsb`@)d=W$Sgc(L{AuwB!2zrnMx}1#w~FJV#r3Is;oUmES4AGk&V}36j_xGj}wf>WhR;xFUjho(B{GQ1d)LP z=9ckRZQR;2wz*s{1~Ki0g_|M}WXy8kJ}pth#Htv)dIGHM zgK_p5$>y*I84VKQTG1V2B}%`9F)b-No7GB#XTf`FLKeLGF_sG0r|OSvG zY^;D?4Av^1#cC(KPHX_Z(ntY~80b|x;m?HnP0W*Ez+afFa>8GT3}UzkZ>$r|=*4O$ z{FPWAR*PrC)|LlbDSv>yL7*QyITF}Rf}*8I2rq*-C7Fugag&LlsvB6UXh6M1WI*hA ziNwU_n}MZv#PaIkZ9=h(N=$cPY*?VSsr;UKhuDCb#`1>b^H4fOnj&|ofucY4G{3j(O^0Pd>~hz;Z;*gh948epT`SN|l`j~BDx?#3JX z`-W_i+xj7qK{TG=R8g)&>Hz!~u>t(7Mg$u};DKc{G|mn9h|nP3S&Bumc)OcGZ4-FD zJ|;GhkH+!3AZ+39TSkN9T1`z{TxGEYlKvil#CDxC<3gI|5jDfXD?t{;W^koYv zEZq=yf!&4Sq4ha|ftdJ(p$vwy`wmlf4ZdI~b^_z~MG#qsQP+%T>Pv}=o$9zNj$WWf`$A4djbR5Od^smV6_!UTPM%e4-ze4aT-?S2&GC( zeRwbgP5{F~SSR=$U`IjsC#*rinaA3}qL2%ax#3?d6urS>Ocv49(m z!+bQfP`x1MXCi&r?}5>T7!0r*89W4kArNo54d?JOOcblK%kiruGld)`bMR`Bh05;1 zZ<0hSD}lFMrb7#tLjg{qm%3IYRS zbr06W82~9zxXuxT;zg_&M$KW&OQ3f8yhuk98^B6*Oypv4cHyA1NJkMG#9SsSY)lXd zRHb$UVgq7dP9E=K1*=>%GMZ4o_?@pP$_l9JfiZ?iELYEA7p$2Qr0RjOA)%sT6?HHI z1*qLS=PuYtvRF5Rw|`;US+J^njU_gK_oiZx8@A7ZwNYLQ;|TR*T}c`l6E3hx9xfY8 z62G2-$q}^57b>ToH<2X9XRvAu;8MGP$W?Aipjb#-$m0$KDQ_yC|M8Mdg)#Al6~|!b z)7`?^&4>+{aqN>d@hb^nZMX9LPaxD^z%v-{q(%`ewMlO5=0pbYo@?yC!9q)r_M?R> z-9n-m^1`4SZi1!CwG3NI68&SmdJ5f)h4O*Tm2M?b(=;Pki-ZVNKd`qZG?yyC2^gge+4CcOdZ>~(AAY*3fJuVTBD+j^owkkS@R}~HE5d*y&7yE{ zTLS%92#0qdVH{U>L%8R+BNCg;jA$4Wo`O`pFnN1IeT9U0zpTiOU79@g9S96yJ#I8w zz(UAHvg^tnKT)Dtyo5Q7pVJViU7>TdN}_p;ieVdQT%dNRk)x9&ibr%7JGzm5*>B}& zwM50pD4HrcfvODfN>mJDCa_^tpeh4u2=!+%+LFdbW}tRBbN|;8>BC+f{P+ZhB&Zk2 zomxjA-T;d|V)%(FfOa`?m6M6|;YB(b_!M^9X>*nJ1U8|5!m@OXwc1l{JUknS^WoO;E-ze|EQR`jdFa|(fh2-;;~QQ7pX!*dsjrV2@{guyC*psMJYDp7QL(e*rRTuu@j^O{Vp`nYspxV~Co+h}7B-?}BZ8!kJg<^xNEWZ0#Lr=3Z`wfb;5@sv!P#Aj zZBF7HR!O{X(PHP@FdyICjlo!bi&a)p3#R5Fhj%B~k9VVD_XwuW2B@gGyY?VbyiWvW zfTl4>+X8+A>`7=4FM0@zcPNGi7OArqk}OtZ6$*Gs*g(G;4NEkij)d_XkB0`9so4mz zO?c;5JSSdiW;bPdjS?l!pT)bg(BQ-7Eo#Z~{KtsI>+dm`l)#!S){y1-j}z+8n)vZl zywyA;+p%1!K_oWuhLI}-0c*x`r3pfP$sBg^ik~~BrYR5CB!PbX?tzJ4kV4j}Wy(`e z5g9jl#2(BM?)T*xV+5gl$mSG0GF^!|$G8Yn#|JXV*MjrAeS4^F>MQtwV-ri3872 zfyh8QiP!#!mpg$}1^!+V#jncYr^qmh2-L2pc-~tjikENVM^Ewk8ud!{nMC^0D-N4s z^tJ}+zT=k8A`+|13Q6qOgPUNfoj$Kp_9hmKb`#+oevD0MRdrz62n}K_1m3%W;aP#& zk2J1!wq&sa46k;=mKwpTOxTCm0QT_WhtAS?qmsI7x-X$YyhsQy04SmM?q3OUC;tmsqK_38l5RDUP5pm zBKtKMnEmm9$rATor?!}9{ySo;5clh3Q?%lt=3VXgjeL{Jj z_w2jQwzFle--=`=Q`_QvcC6)sC-;g(f^MFvoo9Y~qd@cyH7;=aO8BlNP1BDj4BRo+^rE6%? zfCq`qbB5O&u?8?URap;?DB7DG4_K+XfAt1DB$6ZiTR5Ds8qn{1^q~>0BVEQ;-eUK4 zo#xSVg%BrwABgihTF|u^(Tft}8gO3uJukiW7YoQL9Y|}?av{kEf=SkKK(C|_9 zc0MMeoT6~jgooGGT5_ZK*odP3MWiBk#Gt8CA15@&h_1H>Z0okx!t47geZ0t1@B=Gb zvXlAXH|tmaPY^dtd7O4NEAt1#Eaj`|i4nw~fMZ6y;N)KG!Se*>xb3Vk@+nb^FK^?M zL=sCns@fPaGBra#S?DZVi5k9jz4?P-<>i05 z+Ak2A>vuRn>b4C{)%#OL&XW1K!DPzYr@qcl6PQE!%H&(BfZ^SJH9cMAEJ>_cdJ-;k zF#NWE_h&?~j;}NV5ag!|Grk8e6o{J|=L2|9Ea)=O|MW8j=9?|T-7OdE!jkS|eTRRR zP{QbknNwYchV_P@7@jS5mN}e&P>x0x!dJu_`W%6|A@`P5wg(Hkiu8s)H-bGxRZs^Q zS+dE*hv|7D3l>l}EOT+cuxF3_gS?&3cWkrG_{h>d?$IjNvoDBj2k~O=49Fn28uLwh z_Jv}LHG+kZp0$L3&Io@t@gfJ4^%4IZOJ%qxTH)ar3(m9k;dqGlT2*|hZ?B6)7MRCJ zWn1$Z8tTm3`x3DnytJ#0Ci%89HXNRN6J9EKwuwIUXo#M|!bW0+^s)%DIAPhz`gCD` z0(`kZ)19i8kzNA~gUWY~o3*>}4)iJfhbJrc1rvLYrL^UdONIOfqgSwQcUnvMVUw}{N6 zE5(5$+Xu+7c=5ILR-pxwf8pDJ)P|wq?Y*II6N^9#4s5vo8XHhw?AwL%PR$lklDvOv z>boR@DssgLNp1m@~Z7H%AM z&F@qUn=kU+kwiZRy(P|CcCLi?@#K3VNdkf=6d!MVoAS;D?KjK zSP-hqTky$9lG9~C?nu(N9HmggZH|o0$ROi{sHxN0ihPLvw+k&~v6!iYGrK zGB;%VhR%-l!EhPp8}_r2BzNhcL)0l`_;pWyE|N%9B9O{W_0E;>>z@3)$k{gTxI|u= z5_)3h`+~q+g(S;8%YK7`{gm`Yele2W8aoUYeI~A+AipGXmS9hIgEp6kHu4kCmj&`! zCftO64Hzap|KneAB+kXnOhin5-;-aBBz~eDqP`g>>iVAinn+wvXde!vj12GY8}sWz zbG!`U7S=`8@qMA+5SecvuvEtLz{pgg-;C&RfDi77Q%e&mO?0Mj3C#@{_d^o(frcve zzyEEKdD4lMkp-jS*Hx$frM@E+5w#u*S#JMPicB=& z24<-IfBnyYUnnylcUx^#gm-Ev`FHw($UK^zWFum?0U7#{-6;46o$7 z-lY+=lSPh8Y5ed;9{iEO9LiGM*w_Hs2&6aj$B`tZK(o({$xgkw2Y(_k-{)<}eua@6 zo1skqK0g&&;8qt2XB#1i=Y>w<=fCLUCop2flAj4;q#+ zzSv(x7MT-5f>G;+RhRbcFC)t_P^XOUX2zz<{gqf`tPu;UaSyk19M-SCzJ49a8q%Y+ zx`}A&%FdI&i6oaG=2-DAw2NAH~jgP)0%3oQ4gvzVEAl638WNkCSy; zRl~%;)1L)$17H~h5HVd$?eqU4usCGaZQ`g8h}cPJC%YD>DY@^Ak) zk*F**aHyt5LABoXZ~u3(#X%R>4!nP031Cc_@DIUwR1%VD*;>=#w*M4asGGtz{o2r^ z3I7sX1i!6gv2zv#48KN^QI@Co<2i0j>)i$U}x6 z>wo@mp#@VTM{)x#rzK8#rym#JzLyu9=a#X;F44M;PGo(tSBNM#cc>{@ZmjfS(iMdk z=-;frkkegU+Ml%GN@DYM)R~y(&DwKP^?GHYvklf&eM_*t7(VWPC|*UN=^T>x6{YFL zu8Zhq)hR(vb=Ssp_h8EYYNWe9nj#M#){QY@b7gkp#|E$A zbzyA`nzZ41V$lag_|q2W8Jn`<|02w#LbZu(4DcZuC68GK?yE&h-Ppi$pV41x2ZQ68s-My({C7A#0>G+uo(|FtkgVvBeBH}aayRoSUtdo zg8c{L#)3)V!;uSqsu>(Me!k$7#FDd%#APV6P1sbyCr6m}uO(CU~ShteA5V%-Vf0gQ;ak?RECFdCb-nERmi2CDW@77jP}~=Hy4c}KZnDFI8KTV z)!~c2h2T=3?|YYP{;-=bL!lW^5?f*TpG<3vBf9{W6hK3J&$= z3!W8Qv|&mEX6?77?SU^i7vV;wiyBfn>ls_BH4o<_JZ!Z|=f(lMS&{5Ug$NV0&T(fm z>&;uqZd4Rps&e4RbTO&qbT=xAF4nAja@IewBUFbsdQNbOV05z9TE18_TJ_;O#;K9U z6@x1b;%X;!XhTn*CYogmQQ_nWgWgQdMz<4+|167U7Hb(ATHCka?IYVKRuA71Gh#D2 z8{I){k;^PzuWsE4HWcjZ;*Np~NEuX7iLln*)G?Gd;!a}8S6-({ID*UARKfERu5nSp zxz)7bP;1_ba)im^gTHqsxV@R4jVcjFfQYaeJoL?v+hmG=oz`HzG~ELz!dwsnr@+-jJqfbVEA$b!8L(W@PR>Rhu|*s(*rnsFma*aOd;@j`7kcPNF~>~c zP;cIdp4j4uuXPho;H+ScK3{M@!sIq0xPaR>vqH7z;X#B)Vz%nsFu zFZ!;LCftI0w!NrXtqSq<-9#5T;w5Yi@1#tcJhec(yI_323GvGoe#v#}Jwz6IHI!xW zIi=L(67ilwi{{78C*I!9-GTb5xR>BO*$2uv>G83QclLfMcW;L_Dx5dr_Ouu;%RPD@ zp}8Tdg17_Fg;v6h?Ds796`3DZ(V@fh&&bfkzR=Snitk60Eje8+t`0qVKcVcinYsH2 z_8A(A^<(4yV)NBniy4^{C)m($e6eQ;MTrL48uGtpXsXx;M3yj(4p*0%wdyn8goVf= z8iw1sp=-Hi-MGcxs&?YsvF7)i8SX;}YNo@%j{IbyZgeAdbRwF4UHfM0C2w(8B zSX+IQXv&YVblqn8uhycUu7?W{9=+QHU7I25+LvD$~LBosrTG%TV1us;AIs>NmxE%Dwt_m%% z#B6j?CC$)Ov1^g#Af;!D(-|A8%bTzsSpwxMtu}t^n4sC$v-=|3AoEkX$z8g!sd6{O z7F(Pq;kU_rV{9X6&F#{P)nli%c%%=ECT6b2sM7E1odIw3)JVh0+`^%Z;| zvIH1*2$8@7*x-5N*@I$>gtzjgw_!}e1I_6E)y@`NK&-h%=4rEcmxhHe_#ClC#P3kW zA&e?xgT=n!2S%9C6a3oj)9BDC zycrJ>T;j~1TNf@yCvd9hhen#yUQ&N>gFT^x+1`+IBTZNn`QfXK5Hmz$#M2LpG%Al} zM8Oy%8J#No;iBhA7+FVUq;LtK2euCgqANdee5%`Q` za46bW^%F%G@%*LX?SRwh&@R5{^8}arM3hxJ*^FRts^}+0y2Wy#*&=`Sr08I_H{{8Y z=IRlVCfh8SA<52qex%94GDOh9x}VXhvY#S)ZiLf%b7(8A2^|dgJ>&x6r3$%tS|pyE z;-ON!;ZGGkM@&+;&%g^poV7-s^y)S{nB~dd`gGwO($-A6XwsTtS>WftXNYAh zPELA@xw4|QFz{`8VT5bMaga8_CP3g&fgXOQ;8Kqhs9vWw>8){b;A`YrqKl0(5&UTE zPKplI=Zk)};8KrWeucf!6b`lLi+)a|$+Spx{-l${4Vs6a8(}sL$Y&#ZlD%TGOFb{r zRom!HGPKx-e>!}9(a#q=M;ED;`vf;kiqLFQGSCZcUS^xP^i*{Dq?DD(wI8 z&z{U9eEmb6_`+Wl@h(DagY1sNS~A_EUM#%8tx}oGYx|gSl8~6CE)rX0D?xQJk8;)%yb9)79dlI7~FkoIX}h3e1O$jd|*@h;`I6^Db&=2VY*x!@A6 zp!HsM1!6C#+Ve%fBGSzo9$A%E)}^3R?f%M0vt27U`Swi=Np`7MMVf1Jf*_H@%*;;q zsaK1hV*ynqz#^2bI`Pf^8sVinM`>lE%O_=rI`MD$TETOO{r1RcY#+VL93T0zUl(zb z$D>w6K=u?5wc_#D3olsW7gESgEKf~RZxCBVrnEZEZ4?iXd?&d$vb|cl#!dL7ZIW}; z8wHn0Sj2sr?a_I~^c?jj(ZvBOV`M;>jDqAM?ahKqXg4)UZ!&4ec%<#?`Yn-0`2nW~ zocA(Al0E9Jk;aLMd&|o79g{ukZIP}t$OcJ9qDk4w9`$z7bL`j&tg221ncK|xX1qjr zsfA3-pxwwOH9PJ}Oo8tZJ%Kf>iJLPdm_u0rrIDbDl0bhYR|q`ET{Zj|CDRlG#vYr z@2c+;T%Z}bfVM21*c)oj7yN#)#TqM6-0ZS?j=jkj{DBC!NvVNHNY+u~7tg~Vj4_@)nk3|}FyndU_?vxH~=;@D(E}GLbmn7M|mtO3DLU5tR?91_; z84^zfeH(t#v7`hcNxaoZJQDQmr^M#l%@$`GcJ;El5}Mid>-U?ub=q7IHwB*ktk~j+lvf=SbRDFYdPH+J|t8R^Nc?PHY^5?}C5$xnF z3b{rrSaX0c_zMw61$0zLZejw5rt|O@BWxKI5#G1faQgude<{Ls;^L8!v0mY}10Mde zVB5x!fvh{RIo+4PBD%;S0rA1v=F8UW(@D`6{Z+xX`6642xgD4tst?~gzZPjyo6y{r zpEILFg?RewqH|3|yBniy%eXeR!k-U*Lu4LF#yVmh)__t_^d0V-5v{ffY(%KW&=3je z(Qiex(=1oW$YEbWts6c1ZJ`BH!64T?Awy^LJ@Y#e?U4+tnq6;GYN!FvephUfJM(r8 zQJu^Jt&e}gSwz~xa3{q z&xIDa&?T{@ot}dRBYX?~BC>=c5L#u&^02`K&;C+uu`^_u*fwV-V?)8dE`BAr(8m#x z3#hEMlOOh9i{(&fgz5y&zE*Iu8~rB2Y)#P;L%A@6gUQ~C-$uAY6{F}du_D=xeiz{? zd1JV&%6fD9!~T20C4!R5eO%WvGt!gcA4GF@%Mk+#024aZjs7UOR3{-1uEO?#@(V=Y zG5!>3;v6l^)INQOx@-KiXj0=4p+zPo=&(HWli^=Pq65`uvzg8I>O_9p`fEfv#UV^; zXicI%dc`_TQ21w1{WKXWGiu9OT*mh%KV=L&lwKgu(`c zeIK4VGx#bO*pee0W{xlv94f*WyhAJ>-AapS4C@STYvBt%EW%kFeLw4Gz^RdRIl+ZN zl^AK$7F}H17zeLXZ^hwaXPb=*iVJq27Gg5IYwzU+BH=M2w9(cG8%v=(`X;_YLya$cZml-X4!7yP)GG-^L#)%JoAXxsH2dLjWs&)o#ja%CCLZYc zLa!20QcesB$H3J1W%lS*g%;3zU_oUmWt|g{uhpxG&6Ayi!0$Gd6~D{A*dv4z(u`~< z+K?F&ma(A|c=qa%Z6m}=25H8F`zU+%sK|2XOsECv!i-IodkwKg z5;~&Bi^y@t27`UKJz8*~VGD9Dv@c51D);{)%K;iod%FjO4b|XZ?fPPil~y0^ z0NZ338w&RAd!k@G*l{0im@~G0Ri_o<3%-HaVg=c{9?Q82n=1H*5hmpv*(&UtVg(12 zy%jeSj8uB7jN|}~JWk3{-B@UWSo&_cY6qL+csuM3K1pnjthZ&trua;Z!wl^^Wpd_Z=@nsZW7UUt%^^vxk!zr$K`v@O@$UZ^qgVWyzR&FbivztGqL#=8KUsw zr@r=|GMng-H;-tQ+`qVY@LKy%$tTcTM6}VZke=4Q!24%UNualkD0f=DP7C!Q&{V0n ziYRJqCZNmU*`H69dh3XypW3hY?fzzeKJ{9+5nAY(Q;<26?N2xCZH4AX!~vr6Mo-*7 z4*k%#!6`xuJ;Z)0BddU|T`A9l*@%)%nj=ozx$Or|jD=ie?TmmF;PzhWrp=2b%}-~< zU|{fWhw~lZ4GSVkDQWw1JMG<03SJf?iboRHkQSb?y)(5lFA2>N4T?*v&2`%$c+da- zoX9+GB^_L|S&MEjrG~+&5hbT5xljaXDiLmTm&wtt zm3)Yxz^dRpE8o@ow7{h|(Tj+J7#jMZ@314WvqYA4nUpCuOtRk6I}6OAa?&M- zKpQZO7jNlZL?V2QWDvs3^Ghp9+0VNQEsz6~tpL%ZONU4Wf49h1YKQ|cAHt@EPwy^v zmK1gDHCdS~g++mXt9wL{5HT)Yk)Kobd+?qDbKF&9DIN_=$zgIYk$F-LaD2{mv6Sxn z_ZC_}0u6t2Gz<()HPn5?=5egXhmlMB<;7&J-d89Zk${AUgGS*X-~OjZwu2&%sgl5M z>`s|*Ke42c8Q|l`74mXg=IH)HXSo<5mYZ|h<mU`4FrARk7x_j>{FYGt1-U&}sdftwpp(npsw6X6;rAT^CxYql;BW zlnpf9Y4(ZDljIl8P(B*VTkD~VdkZ#%B0o~Ea{}3(Uk;*~evUayATlu|(z5XI<%3CS z)y;@2-oT_qCX{bKNzG=6_=4;r>g?9&5v%D{Me?$qb>#~yW zf@((e=(fEkU<7bt+yW%Q3eY)_k3h%)9~T;r9M+ZK6Cya*36VFme03dbmiO)47Mk&j2!M>?0yNYN6ILBCc{}Q#w)py&f4+ za;6MW_Tjz8ds9{LsEF1O?Zs=bH@~ty4z~JIA1#z5(!<_}yYl%ncc&WmF(SzTN}v-b zL6Fj4@`XM&qC|_dYxt8I8WtoTeOyFY5+L}9%PeRRcJb)rg_6**-Rjhccsz4=DAYH= z6Czo$KzObSAVZm+e4@x%M2H6ber5j5@b-SLI!_>y`FO3@3I0A)FYk+dQY6vVZjz{! zm)E;{^2w3JYndb%c<-O7SNG)kB4;@iXLrtN`D zufW2-J->G;wSj-CNIt;mhT=hKWa^Xlw1^_q%!xRG+k4~8>l^dwLUXu>5V=+!&F@`K z{r)pVGMYN*LgKdunfm<;Bg!Q!@+>Ta_pYp^K2pz&s41XxdrGORN%UDlXVC^k9FNP> zy{SI(Y=H#AHCV6L;lhX4H|KK%vKi+puT2yhWSDn-Jv~=wu7*^6&5q{wt_9K;`aF^N z;v=U}Vb+06es!KNHph0!4xr6|a46(UeL*BiT8{VvQJj0%f|!^mUnmk~9MstmUzp#U zRv&*+L~A%(lFXLMkF&0S{}&4-i74@8cu>x-O61u8{zW3~44~fc^vL_Wkd(@QiO^h) z@Yn$hK+w>nzR;J7WQjuVfi?%)kf~49%OcvLJ9SM?YIQ+Jv;L)CE;Pqz8gR5>FO|Ag zc!kJ(gR{FqAK{kO#hqcC_(ESPw9x1i-oxb`=%UX5{krE>k?rD|$lek(s#JOO)k5=? zA^xc5GY6X*ey?#TiLC~0{3BPRCXP4uwGm}&!~GdoSF6!hkG@W5p-HwHl6sIL8Z@<3 zf4$f|x|l=r*IA8+JHFI6h$IacN1Z6f&#&qrz;}U*MdsU8_6e4O05VkpZxmWU9jn|S zV~U~4A^0Y-`HrQvDih|l8h6;<);9}fBZ%fljV%ypve>tXB}}o#Wha}J)#YS!y;W#| z9C?I}agGg|EcR_;^Hm~j5zr<_Gi&w4q5In-Y9c$m3PGK#yQE_5U+fa0oCkC{pC&GD zb=Mw^1m6$eAvWJ6z^94FGi-9#`p$^O+c-y30MI?39=mAAo?6!Y-=1S8vn zqd)n=4GuGhH{$(5i?|4M>+LC;G~xq-3+O|TIE+9BD>t;SZ-@_yEusP1CffnsX7!v+ zWqa}le@O5wA0##ymJ2>iw0=GEVS%~fa6tYLu6yI>*f+#SB8jG2c~EIHb!dO#$&W@7 zU6IbH%2`Wv^z-D$L>AEM8RATdnd|8Z@#A7qm_&fbyzF2@RrxmfghK};WZ`BHG&yyA zGNL0(D+~*o9AKXkT0n-BEmnZi*Kw?i!GuV*d!M`(}A&J+u$4PGZ7y3D{V4% z(-jR4n>P=CR&a?kKO{7UQ!7-ocXj%l=whecvh6#W)2--mDeH^=yx@|#e3BEML7Bn9 zYG3phBF%1>KsR!&PUv8^r@ttgh%urdDg^Xpbm)}ckS_@?WmimPo65`(U14n{Ob`Xr+9CKK>pMgU2S{(8^TNY7;uKk)y%~7P>J4_Z$_H040?^okxb~YiuCli zBF%+u#ZpmE>9F1L^tU68&lDlpsBKQl4tpL?e@Ao?Sq(14$p@X$!4Ti}-;FSlS|mPW ziJZZ~4iA4X!uY#R(zj=Dm=!$yeZi$V(#&{yPhW8})xCcZY4+xvJK&5nDLU1wekgj* z@-6qvwqCSewVCWymkKX++KAp;u)qWlmPk3`S04It{BTdpY`Ece~y#}Q}1*DJJV zz=P=?|B3LD1p#oeJsl96sb2L{(FC|whdrbUr-f^5`oez}aa8omXrYHXm%oX}e=ht~ z_9t!pR44Dbu3Egxi6_mR`;Mb#W_BDl^9#{)=$!V;C|LwPRHHBam%>ja7-v-Gd~#a4 z2B$CmR}m-u5qDc`KLa1?(eu9+KZjHwD}9sdw%yU9ZmDO7tf z#nXR`H0j~0+`WX}n3^j7B)Vw&*{orwbb$SU{&R#8>*4x`Lx0{fCZ+fAUj&!f$`EsF z>;4Q5W5`?m*GLa4%(LWbp3q)w8blz)jX;q+N$pC76)^jUApzeUgW$cRY{ zdbakU@Z{kCPsB+G-nV$`iQ&nyKeIPD?Vd_>Pi@qgtS7ASQD7YsQ9=d?X4;MbyYWGkVC9&M}WkXGRYc3!0 zIwzG}+=c!n4SbJZA>tfC!b_bY!pa1VPfJe? z|0_otg!%Y^R>(R>p+jA&0^RWx31WRlFbEez67g?@>BHL*nm zt%fA|n3Sx;VL$qhh;YAJz+8MM5Tzgo_ zp)$P5M~N*~O_UIozl_zF))#yY!6mYCkO6)2h1k8R7xXoEbfj@FXtXWgj+wEkH}v#1 zBi*SXm|+Ut6FSu@*Ah(xGwCJ!(~+s90p9FmBFsmb4;u%US<#_n4_{j_5@HBHqmZ1z zf%TPl9kJ|xX+)H$D0k1EkO9b-d#u8)_eAPxVoMlc-j?f&p5w5(&v|J!X0RnW+n*TmQJtt{vL#Fl zPfqtY5PoW%RN%zHMLaZ;pI~n&evSk2A#-@Pi7;zIMfz90k?>QI3_{w+j;*rp5|v7!4%(V zZV~BfkL5>`IEqQV2TMGCOVI_Cmnu!90W&&`X+QpNCAQdYcWwPKv129l7C!;pI>N~2 zHSmF+j5=lP^6+g0bM8@X;9WiGD{(-3n{O)`aWyo@Egg@&q4IY5qE8XbX-&0Hu8T=^ z#Nq6Vo{cmaws6y%j<~pX^K?#hk<3|WMw6E(GbD6CZ%AHnsexn)$u%c4MI6h%=t879 zcyBgZ(`ksM*!1Mt(?!vodT^dzo~%&meaRWIB)rrn00QrqY1?QZ`@-i$b6!&(5i>h& z_Bf7x-##_sjaHW|T@4i;O!xR{!b|uQSJ2#;%!qLmds}W7X&f9(6k{?6#mruwzI~+G z;gQ4G&S0&hXbgM$4w3FOM^zj|r#(eO*wc3uU2IhGytDL4S=nI(`?kMRggZEi4lRRH z28RLc;rR#?_+7zEZTgO3{Cc=7I8VkO@|5FnK*^y4`ZL*z&;rt5+|$|d^}a>TmVT&L zBikIB${<(Y#s+&mTZ=5W#6<6-xMgfG*Ryr8`DSfYCq5+mqJ?6;xecKOg4OZ+!kLO< zwNmrNHpLcM_T%0-S;fSKny<1}gh`IVzJJorah>Mjc7$n*F0N8p7uwX@dAK9EK)?gJ zqWam}X_e+p?nahY8zHHm4U^4Ot@Xs_5s>3>aPsX6sIRrYP)xvGZeVM291O!3+M6&C zn?v%1bRsr=Z3LeIe@ieFS*Q;B!`^^Q$B=U5_oa@+=9}Eokn)rl+en5T+&QAe6md9? z&@5;;I`r>#7l(3bj!!a!Vk3E>a95$ZL7fw07Jt^(%02JBTGarYjt7>SMiq$t`nZUm)JaMM|&01 zmS5dS-jm#0XpW&{nlm()e2x8k-A7~|7yB~D)D*gz_BDJBDrc10+`@T@S*ec@obV$T$s8&U;*^rc|K=<=O=ugE;f z0Qry-(hZrKUREP&`(;yR zAyb8ph32~D3Yp&#$6eDD;4R$}nYTlTPKRoOObyokLJJ&|japS2-_T%yp9HtXG6{0h zW8wd>;p^rb>VVJ!xhhbB#&N^YRIvxe<_Xltd!Bm?*ns+C&lWmsYA|+EA*VEdt$$AB z>RjmzY>Ou+I}bikV2&HE8h3O2cG4f`K_c_L5k4z8E*qJ$^1(uLbv~AC?+p#4Z>Wce z%y+9~gD4Zgv=&F6fAxn7B}5P3#VVddhNiw&=Zc+eAa#UhHw_hfpMU*_3B)03*p>ir8nS|IWaxEI#&hFjYmI=(ORF(UCBBp|JehvVAr&6Kn9V};HV&y2$^euHbF z*ZW_8oWPv@wz-J_rW*e7B4_c#Bwm1>!&+E~`y!tZK`wbF&JoHe>%k`q%;CwwYKFR$ zn~;C;^8}L1x?Zl9S@%JPI`Vz)NkSPN1GGRzBW%5NgyJQ=N7yP8D8BNdcM$H zqti#2VnD?!;MiOG6p{HB?q7JnGdRcUO1{twB1*{EfDA{}{CIb8SoP>rg%*d68h*vZ zH-T>M4Y1!-JWX)HqKLcw7EM2nte+mAE;i3O5eD0PB_m*-A+pf4@2zRMt!*zZh0fucdz5$$m5!$nzEZ0OYd2^R^?k*vFCYJs3(6Y2|nNhFB^;zNyS#aeQS_)?MR z!&K=k9Q;A12JOp)=5PqckD*KbYmw}K{^cU`5IkYS$g6^z+vIWLUOuzV?-OsMAVr#L03}_;cpT; zTj^3)O*|gtFY8r{hR`Y!{qyfV$?BD+_A`7K|j8u=lJ)#H`HQ9bw<~Me0687jNLRtEvHeeI>#_oOl zgSV_V_8nq#xYu#7L(tB~-q8Pj6}&T&-5Sd(i(%f_8?-k(`L0Nkh@#(b;GeRw8eYni z?-q%Y1AhBt7@yzRx3Rb$O!Z&F_Xy5)kh;SmpJv@infhLldD?Y=!yBOPd3;s9PvmT! z)60g*c_?eU?<(&Xn8#bJK`1Qsw3#gP143sjqY7G$_;X2-!I$|#fjLr`kRE_As0}HU z_v!LasKt}$0LixHR~{@m9vQ43FdnC6Jm2iVhosC z2lHo*1LygZiQ?1R#J*iLir-YK*yISXzpgX_0GTym6d{%u2{IuZN7Hcsg zq8sx%-1QCn8G-p~yNdHHU+T@Y@Y-i1%IKqCv#$UR=LEj5eoiRj*DX^Qs(`7g`o2hd3+sCvl_1r#y`?`8N>mi5MYhi}G<*lV zr9TvlI!ha|1vW(5=Xpyn7098cx!t3J8@GABPJbk_z~v)RyVg|*@(FL{fBwf}^KDcx zvw(?lI&$YHLUZ*NTZuJ(Nu{6b`Y#3_6h?>AnNkce-rUq-acVMKd~lnZETCjOPsoF!i;qX@RH zhF0~z|7($XMxUv-(pgq@SnYrRHxb2$u!bx=on>_)3>J_6HlqCoA#^p;EsR%}f&m`= zT|`^tBqbr98L$*)ERX&^q9fdWP=#(A8kRR6{e#eAzt7P=0*#=qW&NkB;7-s!N%Pdd+Ba$qKxs+s&J>Ceq z9G?7VB$0IH^nzv9_^i}v)4xRK(HJ1+o6d5UrZ)dZ{}!1WqORYoa=TU;mFt zP8d*-u+PO=$+M=J)!?a{=Ps^g;klsN4Evwo5m7W?5!d6&V7!^^)`vxu9S#{J3C;yg zb?eJTlnn-o5NupQQ{DRTh;kiU=t$Cr9#u_pV&tzA~L$x(F` zp#?s~COk&5hY-@as@OayEV%Iv=~{7t;p^*a5w#nZa>w2)y>L4sqFsFPs)#9oCN(sU z6q@7cyfN%^C^lAtNncx67s)!iS0^D0J$6gsCrkAaxv(9yd76@K!+cCb8;fUN@aBM_zvqe^y z4WF^8sy!~Uh)g33O43!>jc_#S%RN4_=%7`y+iuv+AVB5W6C#TQ06Tg6&Td7;Fwb5$ zvgC^Ca_D1SA$>W2J+b*=lVCJfe6YJxQ_}wlMOtgXZ8QF+hNc?r`jJKYmgBUni^Y|h zH}}NIwzx=S9c`UF#y@-Z29ZUE0(nkbn{BN~kj}F=6r1C^nLRyzBIB*pm+nR)^X(xH z$ta8&8Tx|n* z(+!eeZQMj~i7X17X(6#ZfkRVxKf0Snnh=aOGAmXMR&*%a(>D`6*BcPljDky`L*d@J z@aDoxOgWrzWb=a+9(s^3{1&3;Y_nGDW>Z8)rwYGi#5s)TYsKW78J>*uxs~V=c_|0k z{w||Ki+f9MEqD&?UNl82p$e0Z-?xc4YVaMrZKsyVS=3j`ZAG7ok1O%IoMKE2kKUr* z(fSneb0kn5;GJuetW}HLMSbzJ!cS$rgN!>aDgh7G=!?%qo~`r{1rM8&CdG#?;Q74x zIow4FBe50ggb!8e%_&6O4#UbwF9tjuNP4^&apDcT!I)r+?**qudW2^HJt5cD|0TQ4&tREUSmg3){A%8b*s3=Un&&xRGTMNR>G zY^dy$?>uRJ!PN-2%GFjIH>?SqGPxFE(o>R^8CRUFT$mj%2HEIbV>Z01eA^ zk9HzT=vMdmxk}g!!+w7_y7Ei=yGF9d0Y{l2=K1kDB)r;D7$(SXyP`utYd1^YU^pSU~{Wm&QXz~ni^{e>2A(y!IY9}F4=lKlIh zA-3464>()la0fQtHv0E}fZ$T6#Tw2+MkjFSE`ADM5S>S?yT#?){MO=9csJi*J0r=W z0LO$Og2-L!m?xeA`n$TFIZY!4s(`g zcSW|{C2ZE@6k&B5;Mv`gt&}-uHJ7`sB@)diZX5PEmR&1>LuT*pqzx;Pk7+i{n43Sd0xl+_&zU(AgH* z32UXM4z@N@*M9p%7R>vpYdUya8=L!5^|~RJn}PahG$4tR zt{eQ%pCynpDNg)N#Dx#cVpz)h*WZjRVcET&$-@|%`WlTR+eG@dJmhE|c4Ict3AQ3z z!vyYp%-DsEe1hFCHix<+eiEz$x1_J)XQOSAdDiqCvmmRwwYe{>M15l&i0Fu1m-uO# z0jgM!9u%5m9G20hvEL6(;D7&Yk+`$sp@fgPk)dLJq31*tcUH7x2v`G6nfkzpn)cUd zfSeR)stZ0yXkpZ>+2x2eL98s_v=0`G_En{d{6}VNcrS14LxgfYMvf!A#OJrd0gLZi z4;7dv=NCGhxb$qrHHI(q+=voB#uuhCzkgj4yqNJbwP7%fgkw->^! z?TdVLByrI*hs`o%_`G=XF(OI2(y5b!uW4jJeN8=9Xn`eh-@@UH48QMR{&5k-0h0rN zqK}LX#d`MfVvF4d$$u&=2QxOr75Q)H69gBUEn<3zuFT-n>ERP2i|R|)5}##kYIZp< zvYa$l`OrwHbyki|Qyp|^~h$QQhA+eM_$na90d}<^KQ((V=2;jEPkUjadNDfDX zAxDfg$nZvNGla6(;)=#}P7O_Ut_veevUwcvC#8m(^40&$ zh_WlGlTqBd%eG`2J^QT4@^!^u5~ItT#}TX5pE!p}zN! z*4z6sv3Ta0`mHsyvEfVRZFsrh0*MgYtvW}(28UMm1;0XU5eFvRH^_~av8jSzDVR(| zcpWyl4mLQnhA;S4Vv#54lo4v>BVlZ+;8zPS^l&9ac9S^=IP@N0@N2{t5tbvXGuzRO zO%?oF!Fe3}8#R(L0q+iX$i6vVCzK?qwQ{A+`JSPv=6Jo>90{Si^&U|G+lrX*v(y_z z<`G#V-zAG(2_lYf14J3xZ8`26^bNGVaFPK>ehsa?z zQ}0b4RDK|`9K#McTDA6A)wuLVd{C?@rE&w!F-^vX#`8veNN|2c(oMYFtnpUE!K&{Q z9~O%DBAzvTvobUk>uvZ*WKo185qa5q`|3HVX8veo*~xMoUC-X_oG^-fxgU!x=gY{z zvgxyOQ;qR)vAFNm(W*yRKL)(`Ip-51$+$_7Qa$VKTd7L;q|idQ#j=!>I11f5Cshfb ziYz&#IWTQmC2S=t;nR^Fu7uczO887Q^FKBkqYk3X{`v(&_iB z5yjC94H|qQK*LM^u29&2 zZ!d4IgcYne_q$??I5HBcU8WZp8{W-NVBd>yt=;T%9ywvdOyk+_N0z`EWDx7tX(%`} zn}>f8VJ;BJE!$=|7#v>D!#@<9W&bAUn$_^;YG^tCdY6hV@<~GgD(kwisn`2agpnsE z8je8ptl-r9{W!u^q9T#S&ngZ<_~}WTH~A+K?)FH`OzlldPQBkxBitG_+Fa01OWsbD z{4>F&dIR72Hm(Jk&6;-niTckYO$OtUt@);OctubDBGNU!Z1p~Y*^{!vJ9_$;kwzSw zeKcCo6FR)4r++0nPpWxjM>wY2ULJ=w^aJ(RLJM7l>|3T1V`ykX-`>B8tZB9OI;5&L zHoTr^e;ZlE9Y<)N*pM2l0X_S>$dcHrg~q6jRJ>>t$Ev@NEaB{?ygDg2G@mc`4`Pe0 zL6vfC!9%%fJ>QG|7-6nN$s;+fv+eM99{y8=k@+IHZc=V&IgkE1qSP+`+9%nJ2yf@% zzX;}xKa<1eBey(G`qckbY!QFXc9z&6V?)#Vg8vp_b^qDnVo}O6?ZoZ{Pr_6H6HU{>NYD7=(5M3aXIQ}K* za2XwjpYNiFi7g_vXn{0Y@7UD%^A&Qr2s0J+3FFAd$)*ONhYyc%7ncB165B+M6{$wN ze1!4K9+4AtYI3R(uMlB!ln?8T>=QxBsYbk_;8LT4mqxXfjTPWjBVH-e=$A1sl4m9} zTBFcc^pzt`(0JR#jHh&XM^9fR(qz6ZbK5qpkYpoXRWt!s4FnwUOx)fTPS5?a>}nzl zmUg(`wnL&_3(3=iBgCR_(za9>kg1E7BL$MjhX4fpu`)DNn(sqb7t2I|_eBGVOe z7KyX#_RBrSse{8wefxoPWU^ z2rY8ZNUjd+7>j$7?{`D7r9SR4119Dvoa#k45{*m!5Xnkh)~x6-u6@tHvDlI&9ULO! zH(_Omuep;%Bc)D2IH&x94u*KI#*>AY?5fH1ekQnT+82Hk(Q`eHb5R(dyripYU-(Uh z7b{g$=CU(N-cn`zR=k;D6uU{Rg{=RC4Q6{oZZ0^7XGgtn=_0mwg@al@)!ss6q1wU8 z47D61Rd>FoZy8yXyqJ}_DuPfTbuQ< zI{8g2N1BBO>g|*Mu^zwj-jIsuIpiGijkV(~D?4^4KXp}wmk{l&`S?{B8Rf;dXDLmI~bLwizB)4~^ zJg!6@mCMU*rWcyXy7MQEUE~FL`yX}tHBA&OLPvRW4y=yNY`ow8TS8$0f zf0+LeO(Oxn-)`)NKJByw}Tb^~Uoq0{@P`GdJy9h50hWM*= z?Y_=%)rl|suA=AcxR9A_@|K7Ae&0=ak?kw1bGuBTaFy-r`|g5E=J!nyv~^U2gWcYe zdx$O)rC8;>+4?CdT2sB`o)NCMP$uJEJ%f{W+)HqNfO-|N7uK(J80o*v_ZC{>aT zCzwk-63w!N2VPf~^Hyw#<;&A(;lgXZ6IN#UsyHjs#OpA>5xkVqvcuDxq6;XTutG9d zH_8q*=j|AaE#VxAA0Woh={O_Aav4>gQ9Z-?qKVdP;XmnBR^-HEwV5~Qr>i>jFb)D z;&a5>K?Rq9c)-G@oTnZrl+8htofX;63{|t!qH>&o0LMJujbRG+!}{S7?cfMQbP`puTiXJUJ|d#*n@JAap*40dhf`ILJ~E<& z@(}rg#@hC7eM3C@D4}HgrZKpx%g}JB>Z|P0VvFd1bWx+W_hSA|eMBA;VWb;51#V3X z4x4A+$d8S1z0UmBtI;d1l+gZTYtY%tif=S3FT;VPP|tUo9>*z4IRiOq5BLV$oZa_BjJ zAU|1Pel$eFzt%JZ*1~)FHa!?L(K`NS zJ-bWXt#|U|Q$-eVqMs?c$QqXQ*ZYA$acG&U=ZkUXzIn@5K;Vrkyj+n%-Gb6T^w1Cxd#0zE5b* z&OUG;Gh4%#+P~HNMHcXsWx7LQ0dhIifbTXR5L@J|hBy~HUotk-fp4!5MwruH9HO&X z6gbswJ`~|5sbUGRwhjp#>cN-%;RvI4!cnkMLBq zuN14y#2V|9k>&D|6C1l^gbh{Z%l%Yj@eAtXr)aI54wU+IWQWA|aad|?u`NMMU+!nb z<_E1#zl<32{B}&iu5W$jnQ=22_my=aCtNd|jkzbcXlO9EV224rZ;*sn#F)SsNum|q6PE+=}}*Toh) z%y)gd`GgGx`+@e22#*l@=Qxh8YXygT@bEVyjGkPN_=>FG#C3~@za_X(BOB4c+zTi; zlM&xbyZiI;^D3fA&QpIXz4}UMhO)jH) zh_+0u2xfTr`w{LU+Gwg=6ZpWiMLhfi!G%GUu&3s<-cl!3KNQOzjJPtgpk@W{OSRsm z5gzq%_`b}(b{a7$rvRXA}?5q<7i+w--iO>Qb2t#!B zSxBxe$Y9^nKaFgqLEvXK>p=U0xgPylL{Y&bu_S_OR&21=vp*M`Gi@Svu4Y0Q9R9=k z3z2zBB~^pnpR6S}6u*op`q*vcIhm=~G%$P>{3@bUL65JM%{!XSJo;;)xfZU-cof*U z2ruPL{f)?c2Qgo?JFIcl&wZi4jp&FlVY@IkG*qice-}~iEoyZf(+mv;c=Y!|bCnKx zl`}7pwbUy14K})&FYfvcAwiMs$F93|n9uWtzx5`X`|rj}c}=pmv6aVto(z zb7bi$WR1$E=s1me_AilbmdPwu%clM~i+T31V)FLii??O>Htn^rLTYIglZM_Bmh^z_eRPX@H*wDD1{byuRN@u^CeS#5RPJAZ*71?fs zEfp%3S-D{X^X2|qY#xCL4mGn*tGpTh)&3*2&@qh(f-J4rK4X)})T;(JMw2=@4?#*c`VW zhNCC1B(hLLhyd+Mo8;Ct9(~hZIkI+Ijq_w?t9rO+uM%0*s{1&mWmO;tYR_IZvVBtR zG$u>2bqxp4UQKL{@I$+nuyVt<#<$lIBJ->p(Mq#j?V385uY@BbN)sT*Z@c9+^(~KH zJ)$gfF?VR|4|Oe%9wjt~G!Lu&>CiY(s$U1SSvjk~EJX3riISzLB-PRd5YW^(Gdw%9zM zS`g%*aKtmDsYua*wzxt`cOH^StpL#7rs z^c&w9{!eI*c>X5$iB=2YM&I|a>x;}I-rhCUJR?KZ`a(~Ps0s2TYh|_`Oif-li0G(k zncU0;V(nmR^15L}TO_F(lK9@xP_N#A8%4B&t6Y`r@rI^muNw<3u=*v2F8eSYOwL{> zMV93(qDI+j`CxMPIythnRs}Cn^De=J@MgZt+$6GO6eDul{OMrBt9kaOVrLOc>eFD1 zhVZfRmjpKxm?M*Ivy2NYVCv-m=8>%8L5Cv)wY46~^nKtKkwmte0Aa;CiZG-Ad#v-Ks_S1gqIF8~Yc!wLp}Y*e|j01x&rrZA9jgizMFCntz`>L48lT zZA1~Gt>6jAq_wfMGW~jc^c0~5oVB|w{P=yRo#I<*R&0*E0Hl929}ekM`HISk%%j@L zKQ;wyNH*OYkdJ5`-Ki!{8HR=)<y_qf2J;(Wnnu|=Hs zS5k|Eb1(ncf(-wk@V)jG-4&Z3aUhS6x!ALJ7K=2=keu$VNx3WG<$S-mON0sHK}6R!a~PqEN)O*P!h~xz ziLavR3=Zw=;k!k+MO-fqgOe)ORi%gTE*Q~aVh+d&NXen){5RnqB4-=8$gt|A*N2hh zKZ*Agm}A#RoQIBR#-{U!Ul(N@2ldB2-m9|OEpaB&)`&dctC^+Ca!V-Z0!adM!he2 zA;O3;R5?9i$}~7shKF|wE^w!5BB6W{#)~>0^p&v~SptJv+#R#Wh7A^bc1bL^%vElZ z?0jr2p%mYC%MPt_+0Zoisl+8asa|B;j>P3^Y6 zw4PjzB!Q8ARK~4hgQ1>WizM5WD#INxnCZcFf%z(nZ|h!0hD!Afuuo_KAG-?8$^waW zYk~C@wIMb~@FX6DwiVZ2(Hn49BuDtma|>>zhVJUgO_6yrCvov;F|tuc!J9f3O7te- znBAUL>82bFy{TJb^IcLi5=D`*p|X6j`-QS9Dw9Lb#8-)tPu0M-*gV-0Ep<_5ZJ3#T zu?K{bCAiF|-HzqPVKL&X;Gjq{#S+~~6sD0n`}gm4c4T{X?rbcnw6UQJdiI>ia=UMi z1Jh-035!P{uA{u(ZvB* zlxR3+m9{CDHDC0@1((>25x$WPUF^{E+ZX)^(M2|8xMtLB{6dFH_C-HZaEYFSBx3gc zGdN}Sqaw}e5Z71P)BvpzPjAShMbEX^oD=&pH6$IB_ZZ=&7P*v0jQfe*$*{b~ik{=b zw86}0L*GnMrT9py#|bYXXiSRwY(_Oa)QY$K@uKI5Hz#z+JYllJRV}{oCkQW?u5_EA zpbQUP)%U3n90CiwqG{a<*h>=&Ig^ zCr6gJDB@}D#*$)F-{bSe7KiwJ4SOb;V{DiTyuD9}Feyh^Gh3vO!J(2pe1YIXhcE-Q zAgu-W>n_k+{M5*jbcwKK>l*vl!c6bcrwJ|Mo7}3^vuOi1W$@D@Jmg@;)F3AXhpO-f zKSOYi@Z35Mp;)0w#!s~uM$*FHsA7thhQ24CDKbxxYp-87_sae93Gy@jvxFi8S+8@g zLuUX@weYhe+rt2M?6ewer~_YN&xvfc+U?=vNu$ArHuLOrBWubVb}4JDcFLZ8o>-Ej z+2Y6=V*f@M6#mtoFSNj==m702IwWZ7)m{);uE8p8qUtg>^=dDSEcbTRF49*Sn|ieu zi7ldG)8Q7M$sQY2zrHKHIKrrpu;n!;VuOPf9=<5TY}2`6=`uYS9L(_WOCrn_Tc0F9 z(~`rzq=#QBxPZ9ukl~i~9(h{&=6IRdB0_zff0EVCtWYKUf?potdcVyrfQ8o@oO-`k zM3_?*2M6$vR4&A2P23r-guDC$@;_X}8^H9dy8i zOj8BFUT}d#o~;U3kMjo(p%L_k$Wjm7thcMiYFF)R;$p{^Ig_pspAD-^5zoF+Y>w!= z4r-TW*su`tv(%eJavp?8LJd7vNWGaa_03|74g3%|Y^HuQDVXVM%-8Q*1eZpf0GRmp z6izKa-YS|vuOY&4_*PrdstI58+XR!*tC=Y}B{cI+!6p2)1_UBc*;L8ziZI!uO|K|>#Y4oN zzgzSiCJ)i`$r{nzyhnIxL?(M~85@}?v9^8vy;t-cSqsZ3#B~FmD*S!IORRkd zJ>(82xa!*%{(jMOtp+hy)$*hUX`NKz9}r&bk)x?PstvQklilQlf=f8lwJacT3WuV- zB_9%9M0|mX5ie6~OPTGv$%h4VDS$#0QI}IVRrE(hvw&;k$cx|wMayVE#y;xU?tm$e zh(}mi;n|NxmiR?H01;<9a0rQZInSXi_;Q0pKvTobrZ3+a+5ZEGO}E(*9cWL zd(&zZpNcGTeztZpG+7OwjwqwB*&)?8Xwrhu2+eUQ%0&?>9tU=XZ1aAu`>e)t zzbLrG*-D*-w^f?Ksh;*F(ZyD`UnSf*d&Bfx_hrE)WG!1g`?6AU9C?0td_^$MsU17# zv02~{IvZaVOlSlNmn~d<0;i1rTBObUX@s7M!Lh2n9bXqb$CxH&Xj0XOn(DqGoPo-g zj0BI9!d2P6@NbHq>r`;r>P;%!L^*=tejfdn@KS}e93(-ragF8br@ruSi=N{?nMk8a zeH)!B{5!&nW3MrRL($%n?};vQuGJ8bAf zg85h=1T-R)cmk)2{(Mtj{UEz29n_aDCPN*ujKUlfc>Pc{R?s9{!17R!eYj zzl?B?5I_9NY}g(`(BxMU#(lQT!CY2vX+@J?JDBjrs%71SGh2FogAGi*D2gZxe`Q#vtj$Zk-s6OQn8@%sqliASnl1da?&*76@5+{LTI zB)$wzzTO`Nms+?8aH3--A4;v{PmyNQV7|)+)S=W${_N;h4==)ONI}aIKM(vxGJ6`iR!anx~7tSlmAmJ0V9MF)F%xSbt!z4|0}}nJ_$rBob_43D%r#Tb}+ukU6vjh zER#L_AHjt-nN_(pwAm~Avw4$e_65&j))M5#YLZRhz#;Wbc0`)FC`-kg!Lr%c^I;M0 z^wB>hKp=xwCwPm;~I|U zHnH48HZ`O5hMqoJbfJq}Flm#SO%D-rf6d4e4$XLJGr$iK9Dgmbd1NCygt z#}XT~@iJLLa$;qDackd3Sn^%X9=YVG?ALCtM+Wogg5n*+xL97_v#^dx@Y2H8?DTNx z2z%yTlV@(BXNL2vY|+Z611%q1UfjRMEA3fX54W60+Cv|lJakJv)Su_m&@bvDN}2GlbxbR`}3SXbF0NRWOd)d(!%Iv+MX6{!f=H_An<#}?A;<|_v zm;I>K>hivI`e#@ZA7#(Ids4Ic_*`WkFO*sjpTqxtZgy(%HSEF9O&%=72V3*Z3FSd& zSe;*^N@&6{{bqAz>+FT`n4X%OK7Jj0d_3vaMgKUbx0O1p(DdW^#N#FZIHFlyWXJ01 z#|w$a=ltVC?t$z;KmB+q@%X9!@upo*;qH@ud@k|$Y4P#)Jo6XC4zy1KBw zyl?+lLnw^zW3BG?PwMV=@%het6+x>edHxRdd}ur0S#BQ-D9@wp&|@i9oyS9Q|LTGb z_r-ntHQs$^xr2X>L(Nvh;)uyDZ6krPo3-}zh5d7PjL-Gv`?w4?dMpt)=_dc*;dp|* z^I4O3zEdosHP3RFx8`h((X>8ZSTvg#RyA8Cs(fCL7m=bKjnGCSSpgI1<`nkd=(1pD z`c|J@k}Xpv$nfbjy0*N&rLpg4`ig&+E(-|@SL9RH&S9C^X9GiRK^M7FSc#&~OK zW#1Vao6K#y&e*qMl{uby?By_f-!Ze}>Bk;+4Bj+;4Sd)I;K&#ulqddKAtH||(|@I3pE!H$`kdtB#Z z=g-d^e%J-a?#LatwJ`DA-?^>F@N ziO1uUZJz8OpV>KiyUYII`S#dF$MWaQtLU){kKIu_e#emy@Q?ksrBAU3XOHJk^{O*7 z$4%aG`rt_?@O$I+|E-u?P%#(SgQc7D=Z4pqnK{`Wyu4M;@A$?1Wgqmvc~c&Jsy*7j z8GpXYqc^cfuV9ZJal(!x_hgTTpImgcV?X*dd-AHc7f#+HW3nJ?j7m{=37Kc?i4?fo(ykx+i(aAG2CuEg+7#+?Yyi@kz`v3gkX*~Bl zd+wei{@m;)Gc(6entu9R_cG7|fXa0PUC$D>%Cr`V+4XOVb`Bff!fjzeG zzWli|9Vd>&6Ryul^pE-9vj<;j5B~df{`}xF51!0}5AYBArmzQJWDlNqfBw9aP8Wai z6dpY7L^JfiTf&}tu|4&nP5xZ3q^GEuQ%=NA_tbxzd67ML*De11ndjojx95(&K{oRL zr(Qbz-b?Jcdp(>#U%rDM_}}5V>-pz2kKUW7UTRORKY~AxzoW*|(Kpy};PBSwnO*#s*g#AuF`J|3Xmmkfa2hIDD_X~b((LdPIGyerSW+Mc`ndHnfx%@0_smy0j+oVV4Ue2qPM#FP2+n!10| zY`x^NPpTzO=egI~bH|_0pOYIiGe=rW9Jb?P9{R{-UeHh0RyD7)$3AS2oylWyHZwyn zy`gom|L)E^dFu7{RPAN_c`idXcFS+xaL18h3y^ zUXTBLk4{@!&YH>Z=utf?)eyqe&(2S-pD})VK8Zt8`027O;T-H5l)4}Pd2duIwbi&p zB%|}v<{<4jIX|}^8@(CzQzoWPXt4>pf+zG{Zu`Dz`)+H!%g?Dp?6gJOkCHy4()~xt z+xb>)#_2H05E~J&!VWU&QT*pJ4AMIxAiXXx+ssV2$!q7yvuDnmwK4fu+TL5Nw*P^j z+QJf$PWK!o-DhG2*51>{&$8@e-;|%7$j!3wBo?(xZU6gi{}BD#+Sx_2Gt(_ouf@5M zxl#2c<+*xO7gwbgzJs4H5(G{aMJ-bm1IkJ&bM;kGaec2oXoCupwk=XEQ`?SflsM{i z$3v?!bEcP%f_xkMuiT_%s$^{AZ%kEyA7qEp4?bwtGPVDN#vjy1xvFeT&9AgqVPO%zOqHj)aX*z zIs)~&azT!M@Fqwb;3gkdY&nZ){udy+1w-8cxv-iA`wOVMtJt+ddMK-8`#aJ1#4qL^ z+{j$6x~i52-xQM{uFU1??BGr=tugie6C1nMqOW10R#RK0lvkG4(C`<4t9#VW;%ZYugl9KxnL2w+BVcf1Q(~=!jb$eo%U3#l zEv`{UA=}GDD0G9uy*e~?VBWE}0P{C@m@0$79a=9z(^$5{D&!BT>)RN4r7sz{7&r1B zo3u`y+_AoX!tA+)4Qal9*32Z&HV63J0^TaY=feN5pR`PU>T8{4KNbkDsRrujPM_1K zch3p^`_9MUzc+$^=>OH!G8HkBp;GIGDvA4dpw*W>?x1$h9Eaf-t64c!i7R7YHv-x@ zh_nL@h9sglAmP7M`B?}Us&fih4DFvtz$(YkPQ3pDS4*`qs9-O)g|tkqQKjdq?IK_o z0N1?~Qy)j5ujKB30`q$)T~W?k8XkeY%qXbDu03(z;i-jpw`*8@=7Ox39G-Gn2Gj%q zrnlNC-n$XAPlMSN>>3!v+rcsHsLFteF)x>)b(NAEV>P0Ii!ty~>XK`E^{tpSm)hH+ z_pSu$j>q>=l>?M!oS$11@tMhr56DDMiL>nJa- zf=hRk_krQgJzwA zX4?ko&Oy3MAlnDhHIQzB>=4L~f$S7W_ds?IWS2m84P>`Kb`NBaK=uq|uRwYPvUec+ z1ky8*UV-!uq)#Ay1L+q?|3C%=GBA*R0~r*^eu3;C$N_;I7|7s2h6IucBnZR=5(W|l z5(iQo$k0Ga0vQ%aX&~7^$^t15q#}^YK!yiW6-X|S>Og7&sSRXAAa#L^3}jRw2L&=Z zkTF4eY>=)G(&K{k_#l07ke(2vCkE+!ke(EzCkN?6g7lOieQ1!L8l`9@0_5trran4uRS#@=r5 zz``OI}UAE=mMI-l`c}lwwQW2xz0>9iaprp@J|nIw8VMgbQPAk z(d0huBF2h-6A&51P7E;&?kW=vcVUFhRof*7Z1I z^K-{fnFb$sc;ouN^MC!hWvZ)MSrUYg@-`3`gXtUG1|nPR?OqOqBHr*81cU{=7!Ah{ z{vd)m4m}&3u2yLm$7LCo_6QjGmL6%=*qkWN1YHxZI6^`4&BZdX;%FdNi45nhS4 zzEsT!%Q=TsPeDxU6{;vOZOz|xo{7#&9FGlwv=h*7(9RBy=mezfpYI0M9d&F2GpzQk zU~oR^2k@ z9)l{zklPvnc{IAMF4lKAqUw^^#f|wnNSdkQ$Z;H4gh4lBgC`-M0y*^{?PhopyB@mj zs34Df!HYT%yFJMHLCvGE^>)ge+Prn@jgiIqxg}w}P19aha1kw2lUXUKEl;$30+mcq zI#Kk^)7S?f^;Q>Hh8~0su<|~QY{LLYOC1_t(Q)yBn;Nqa&L_IwR@RZCj({HfIX&8d z()vQ|hn(1-!!J6!-eozDsM{dE_2in8?YVE}r-9`c)j)84lt>#2hWGZ?DLZ`yP5(H& z(2lC03@_@tK|ejz`C(I0%gK+`0O5Hm6x<Zd)CdXF!DS9qdX90hJouC&lYypnWbs~q+hnzat1w_BE3okB7k}zgt@Nd<2hL-S} zzYnA_Rek-4xHQT!!*=C8ozR>Ond42M$<_ofyQK2AcoEb%MP-c~4~zO=jJ=z-LKEEj z5L!=g9Ot|MwgcL3A?u70FEG`+wMeH%=esv%dF!zg!I5*a`KW9GtJ?twx!8QPUAPW= z|35PG{>;c<8TmUS|77IfjBLnADi8@I9Z0i4iUQdrkmiB32&82on+DP{#AkzYw9>|P9#^%%Y`SiGadVD^8a6UaDpPrac=kw`F z`Sj#``jC8jN;frx)bYN9EH;=hMgJ)5qr1$K}%t^XcRB=@atl6Z7el^68WF=|%bUDf#rN`SfY| z^y&HZ8Ts^?`Se-&^x66JIr;SBeEQsc`n-I4Nj|+apFTgIz965zFrU6CpI(+vUz|^0 zl22cnPhXZ#U!G52kxwtrr&r|DSLV}K<LVPH|Enf<D%+^Rr&NC`ShLn^j-P%-TCxA`SiW{^nLmC{rU6*`SgSN^h5dd z!};_h`Shdt^kez->U{d~eENxe`pJCyseJnBeEOMu`q_N?xqSNheENla`o(jd>2cHwe! z{*JbL3nD45s;tlAc0N|9s;HtIH;M7X4;#-OP6GMwcutp7Dm8Gpt(f^@NY2Zb#=>|^ zJ&va~-qi16@Zq{-*Y@s7G1Ul&`V4Os;@oj_tU}-D>cA-2hguebs>&Y!Tg_Y!GPMPTQ(_!biBq9nrX$f=Qe) zXK38kpu0KIU6o_sb3Dktl2)PyKkx7~03LOKw%f72?ZyjG=m|PH{54zIKN$UShm}H( z$a6DwfXi#VO2vt(IiXZQC_fWk3mFwpsi$I&Kh(EY<2pOu43Yrm0vRjSO_(a?e-Bt= zTKO}4s&FBA`;{kedJKC8rk=-=$GH?u`~xN)q?DD_VvFZEy9-!Yqk^;1hj%DZ3bfa% z=*n_T+1Jp@yV{5p_E6q>%z{*(bb(1Na@gzxMuDxq&P9~fnj9yYo(0i|dlw_eu4XDodqC~1*xN`~ z0?zx8>n*{J4i4OI1lJD}s%+vl^mYmR;unvqsTHKh#O(**O;ZmV_vu9*bT;I25HDKx zE(~$@1}x?)m0KWB9PD1#PdWUb4l7 z!*K@1BnW<}5`auQ(f&B}`lccVm>62Zey9q-e$1Dx$NT<}>@mEqB}e?82W|)1_Hqe4 zlT9dO0-pkbo#_V&wg}a?p?$J*wDvrR8vh0ZGu7hppqRK@2k8c?)>=-K4Ta=Zt2H1c z;Asi# zG}(E23CP_bl4-=X6}WSPUx4dbVx1bPCFbfqwBGKx!gqd{t{6;hrFMYz zI%1&P{Pryjf_4w z?}dq*E54&#H3vV(gQLB5^SIO${DQXC)Z>zc(>g{&V zfI#;k8!5KQ94FChK(%pUPg$Mq>Slfm;~wQ2lS_53tt~o!Kz^#k9>+2E=0IYPxz4!~ zyH$0)Ytg%t@>IrtdnwFnf7S)gO1b?W419)qBD>G^R;A`xHcPpkVfz$Z!fhlCcnn_6 z_eAr2HmPJqW24&~GBL{c#(BZFpzFS>416e>=U)kJZ02I*S{zQZ2VMcv|ECzTr^KYI zaxnh2Gn*0&>*To*!|tVPU8WZ=cD-T81If`Oc`?`ZMYx#(I%j66Z>y`o&PZhkRfKqp z^cv>f#F2!XAjzRD%j;qgeG7Rp4`B8t&j~cRb+T2S-Ti|JhBN_#7g;`l@gGo)c}KdH z(A9#b!!wkA!RY%sjF#1w@U4!Q(EBBVN@XdVbP14>(Rq_ott6?y%)bFB|ET^7D?NLp zY2f~Og;F7W^YSUQ5*b>8$kZi8_J&%|RLS}Yz8x_3Cm!onUZ!abC_9JeF5G%$ z;=5z=m1;*3N|AXxrab`G?bV^yW*Do>AiQoGX+%|7FD$$Z()+>*9vNc7vd#P*sSB^E z=AA|x&^_KUour`Hulx#M*-dFKWED6hxC9e_2X9zO694Abl0wn%&uBULRpXgtVxdWojk9gl~RkRD9f;BvNoiKCy^qDjCA)0-p zQdETV#)X4%bK&W3DL}KxO;w9LC5MvB0GxkR%1AoZ5FO`1M(f#Tyd;5rvhj)X2oY4X zRgQrOrjyOWzq0nf#Mmj7Z?=wOmZKouRyuU9+PfrWFXwbsva%WPc>H4EF0HL$&NK95 z(0VCZO2bPJr`HZ3>qrd`8WISs+V!cTckz~}iTDdogq-Z_A^T?%**~p=8BYK>S|;UBftUhm+5c^aCZQJcp1O-OBHpwu%|<+!0%!j{zy=(^4=6d~m93}=5h z;cry#R;7L%IvGlB!A9*Z*(bne+Y-Me!{9HRXwLu=?`1%E2Qz)pw_b@Z^AD8PgQb&I zsaY>+kpdp3QDY(H?B@Lfg8q_%YrA!4g-!rnfy&Y%qLyvMzOcE^^WS(Q*z(Ju&dIdD~ zg|M{~bzo$w?A+d}+Yxv>g~`uWdZT3uOH!O4pO7`q2q zTyh)C&3rxN_N{W2%|?8;_XIF?jgDNE@v`27F!EIOdsR8Z;`|&co6G`Xb$tSP{6+G} z8Sh}|aEyEtd46PEc<5aK#uX}&3<3@k$953MVzon0OFLUDbg@Wwl)b*~%)|QewK}Y+ z8pf_?9EKf6z5&mnyu8DQ7H z?hl?&)H?Oe$mIFx^cnf-h$foj$qW9qOl|EjRhB5nv3es|9jHT=ma%f~0Md8X#$g-{ zEl1lw&dy3Ic`JV&+D=eBK?M6{i#jxWr{-m!c~ zplPVD8ZYnoK2&4;nQc_>r12JppGeLv_TNVSf#HuLz6uenGofF>*IWX+?^V7>=idob zc10uI&ViP;BP}J#G)I^{+ZoG*6|$P_8Gpw3F?n5+oE|yi9s_o^C2XNC70rG=4C!Fi zG!p5&(Rv?ZX`{4x`PQpI+2+bL(wa1^JwF`h@~hznJ-54YH^50)WgTyPeOmK+JIR zs9>g=L6CE~t7X|u`#n0gQ#BSN{l;6M>oD(d^3Yk&kG=qb97#G#Hv2UAddM@YOQSuZ zVt_pjfE8)8eRbkpSvn5w&79daq$0d^{UT6*A3>d3Sdp=f}&z($j!@WGmQIP7-s?6#P>v9Hk8L-H)t@92t9s=FRFx@B(%as3)(JK{* zHVe##wH9(uv*57odXhT^lH0ss*~w!=KK|OuO4Ti#xg5Tp>%Hu|2y?g5btutk(|GDC z_?5SvW+J|AJp(#_os0w@ZH&CbyGo4zj7qMst@h$z1M!s-=!P=Vp91d>dYH3ev=@mF z0Cm?X2bCd*;rnConKXT-tao36>^k)QRsBQ58G&~ydj@{ef|Q5XPVd71M4p$Ye+{(# z#oB2S#vhJ$qrj={Pv@p30M1XU7MuFwcbC)QDkdqekkhuyXtLrs7x)*3e?z5P?!`D$ z!SvO-93gZDQGP+^pQkGc> zdOC$Zg|XMGLbE*TX;9{u)DzJ&qjdsYPzg0>i|wA!jr;^gZlfckY9uZFSE29Dx_nyy z<>_)c+Ml7ZD?Art(E2uO8g^)5=;p4*+#S`B@VOrwxVYveu;UN38NQoEG7`dEOuE7Y z0P5Qs;vDVV1AZK`=aeVZ|d^MdxA9r zlOM?lP7W$~h&C|%zZESFZw4K6=K_k~y8+5FBf0NM==&PEJ!_u4WL2QOpN^f}{36bt z1Mf45`pA~xa9CM~&LgN5hl9lowO7%8t%oIi`HlMT0NGqg>!qIr?E)k&Ry5Vc_Jq)J zy)#;WQ^s&1%nKA}W9nUWi7$&-C=Wnl{dDBQRR%A>cn&yqr37(5GI_h|=Kcp@JJaI} zhaJpV3ozDPu^QX!O`LzT7k(?X9iNvVsXULyPGsM<%7wSkSW6hfVoy@vPAd<9^~=dd zvxW_&6Kpii-X-EiVe=@_gxnsK>Db+`W$V=7j&r6g$lIrCJ0+XU4ut5c65!pb?q)Di zOp-75?{}_->_@02Q^#*W{vnE)LNbRz^$#GkTD#(4n0k)@AnvEe;@ErRSAphV99okn zr`~Syboj4d+~g&ZzZpCoqyyf6zXL+fDLL+O@xB0Yic*tK$&1A6owzk=SZYmnlip_S53pCw?xV09VlaP&K|WHo+YJwy(Lqq^HEKp>IbP+u0TMqsyp|+| zvz%Z~!PI{!UZN%u@LV)M@pFg#QAi zj%3yfO5p|cJIwyHr`e(2lbZnT_bGMdsEtkZ^#y&W>Vjie4KMfD4DRnORgI}D_BJOu zsAeyZKI>_`MdvZhe~*)HH5)|Ma_2x%*q(TOzXPN$quDv6>xij0RoTG>a(3Zz4E>in zR~rmEp)R&&s%^vh#B@H|&hn&*NRkU=v;;e+HT{7XL>J)~BZz2RKH=5oRq(XVF^!K* z5@pAMr z5#A58E@aP?&GPa7Ul8_>M0TZjoI4HE9;1q~d8kn_!=N3k;3TCwv}=hYx)XZm)pV;6 zc^7jK{1Mty>dyIcR&zM>9u9d8c1=UChO|bxpkY*oG4efp%34}O|6>VV07X7ZOSH3I zrw*G7S;At&Gav7`vkf@EpP*uo=Q&Ak<-Xo&tc;;@8uS%XSHxPVX~LZ!vHndA=w&On&()CKSGEKpTb8mtw6v}8fM~21hTF~;B-{g`)cHbc_>9c9lMZ; z^$kZ}n>QYLy+gbuaOCi!29nuc7rE-Pp*;375WmVLgiW!RI4eeD8#2xqcLRv7(=hTE zY6wU{ad>ewumQq0Z%0nchQ&s5uH+baUXo>KEFB!PKL zkU`(JYF{z$67AbPQAOiwj#uUNXsjKdlb&!Nz=!vE^#6bal9YaQmOlpqxzphUmx}Qi z+e?t!dx95vYgaLgdn-)ePg%o@s|s-LjPo|2bW`nZAJ#N^scm0+e@0S8kqiI%OFb0& zp;}mFDX;Bw(fFO$yGfk|>=V)D5uU3seGOv8{dS(2?gyo>QN7tyDkqjw^t?>l3N=_yYu|}s1}B(9pp`z3dHe8^B=ZcIJ4T&E&QsX$psj}I^)6_y0ag7}E(l*eq1*CLA>T7MN=p%xNWebx*+1LVzD?6~|8p=WatccZEwUt%TM?u^EV)ZWVN z)qXekK!D>-B@6|+%Oe}@yB}0RFi)y%;lw+w{mq;9}l_gq}>beYFH=trdy}B9#yy|l_2-rM&xe(AAbc#RLFjPoL6A{ zeN;qQdzZ_RaVz9MRH2bP?C^Ma9|G>6KWK;yyr0~RpWLBr*2exroxLHbA4q?Q9K3YU zRCIrryW35fcRRp7BU-H-R4@Q+A=vZOXmj?4m*dX9;`!SVk8d23{?3J6ZL2=fu5i@4 z5^{MvCRN`iVXM`W+Xwo`@?P4ZUhEOftGeKB_L!@cmk zD|(MnVc@|9`>D4;_ccmdW$3*z8-%gfk+6^gcCyN&ZGiIu4Lel-fc6FG;XNnL#)B)z z_+gOf@lAXr+tW61k|TBT&2YG4%eDIxZ?1(#H+7AXYTrUCGM^)|;z?Nw1L1v0j!|`kHUmZ?LnE zmtfXm3XjT+y-neIKM4)&#H+NgfP10c4LY+eYwE=yHbrrp;~1a^Wloe4&grUch1vY< z*;u5nY%D3coHgzR1^uA!Q=D@io=Fx>H{Ny-5qyY!BV+G6)%NDZy1f}&PdMaUguR_+ z$hxqLWEedR@m@eQWh*@p?g^rboKLaEr5r`e(DOFegw47ac}CDoXD1x&Wf*6-ftf1T zHF*rhuFAea7^uxQL*cpS7tvm=5KgKVJF>pQ#9uPdN(&bhoz`uo`5~&-jD7O$8XrLK ztDO>Zg(|OZY+I4xTZNNN@wuLdz}u`LbFJkZUMZ9?NS#=c)M?7q%RnO%aE-5^Y$aBP z@{1V1f|xd0KJNMqbl*T~YU(0PgZEL??+-Rud$ai~pN#BJocUKT#4^Mnv4KZF$ zQY!Oa9(DpXvz3>I*pMxw1?2P?&75TDya$l>gl!melsvw7FnkhI?4o`m!){_PxQS;7 zVJQ9SMI{D0{M+fF%)1GCF4WLR$2ELqZeNVMS}h7sYnmiW4**wt61d9k%HcHpD5m{d zSF52VJt5G>Y-taS-G+R0DR#KLu3QBt{goOlO7^jjIu=7$DD1Mf{Hqhyb8sVb9J^Sc z3&~IheM@k?hclbPV;@%6Bf!F?p1P2&^;d}w*09(xkVq!!YTJokZM?^;G{1$&$wtnF|suJ3aDZ6I(s4O;-!l|1nzcKQ!SiO@DvY%gmJn^*$f0D=NHg_hzh5w%DeXe zDTFi2>9sOrJ-xGsO(55+6ql6@h=I`9KH65u;MoH**ZTko2k0iZ^sj{QXQ(>}ytIQ|o_A1pZ6E3IH?r;q<}P8( z@oCgHXk6!{hR4@z>c>H9U8pCvzNBz_-8&$4TEKWQ#hak(9o3h$74BaHxnDt}mw8vY zw*_H)D#vx+p8Z;kd~v~Z77FwcSz7~T`{=AlpM@Nt-UwX=I&Q|R3-XX1S0(A6eeZ+y zela!TeFE!nXEYDdMWhzR*1Q5V4}hWVh%V2vF9cPC6!|thV|V_t6dk%tYR=r*Gp6Nd zq)tr(ZCF>Az@fj?%|3~mt>fmrYNg*|++P$}k*O@^O~Nb;^o+VY6kO*p!PW(sM!1<8wI{pDi8hKE-lS+4(SN-&I;CeEdYEs_D3*qCzWW<3)yZ3*YjOtB`Qb~L-vYWf7e)63w2TJ^XOWnt)8Q`6*5+l z9U2y7G30cM+AuyI=|@Amf!Q||!q(0D-|MQv=u=43`0N#_`ZMr*vab6z)p3mv!)-DC zUF@fmB4rLLJt57sTld%RCEX_d2$LYM_bdD#B~ z@_tqkR_%$@URoWcjrI(vY5(sb*e8fFFAXvnY;8@AO*3rvPEI$KdYON7)IJ&6QH7Gt zFmx}2#D{vMB{v2*;&>nZd(r5%p6|UGt>@_IWqx(XRuKBLPN5BV(;WE6La^Ov)wb{_ zl-`BTli6EV+Yb~ug?<95hE8M2b60i>Z)5PYbq#c7hh6_oq46~u2ziGHc?3b*5zg%= zTfD1X7a|DiN&W!U9hkP8;4b#i$!#(5Vs5_%8eQ)UFz4M~wKpAlQdHo*1h@$@$$9!p zpu~~um(WP=Kj6wb{StHBOj=7S3^~cz4{3EF=IlLc68uGA?nPaSkQ^`1WlVKRMLEh3 z*I{k6|4S>=GW`Bm6=vjrI?E*Pw)Sg2U6kGAb3gvo4g278 zG>rgo0r}nu*pHyToPJ`wX!cXIu5&UQ5&H%Dj)TZfQS}veKOAVJ!TWfPhhnep`($XV zgBu%_z_MN>aWkxDkcTeo$~@X%2DrMa%23OfBzrM*_9r2~ybMZn9^o8x9Za6iFK2x} zTKA`cO_=rGF5iQ(7kZ30Icxt5y#1oFI!>J#*R#<2Imx`RDTLr0c}GEUdlM}D!i~06 z_NBVQG}M1{oqIuYcRPQDf@K`vmZI-C=O~R=F6kJs5o*3C`Xc^D&)=@OCH76_;`P@M>u8Np%_j8Aqdd zxC>^_#b|#LvB~bo+3q}y7Er6bD^3u52%Oxd^5S@Y7@FE^PkS$lI-Y~pv5FsLxw!Rh z(A0vE@4vdg6g15y3g)IzJ?u47Go$J@NjWJ;4NcfOECB&N_e^V;Kkm;%96mm(t%az`KqG5vBEG0cLKN7nN})mUevP(x(`vh zP=$aM{Qz2bQ(Mg1%O!4D`{;d|nh6#@V(1H)$t368DoTbjL4QFQ->Cf;@_8Jw9FN`^ z0$B13-VVG06ny3g!#0}<|9e_G08g}=Q;msTM6jCNlB|rHh)f{wn}JLTN|Qdc3mGsFn_b;8mf$wTF%8! z&SF3$4v+`g5xh;;O&V53e7FNYa5nZO1bCk3s6@!&9MeMZc@Rmc;k(Ul z5UZjKoQiPcpH;LcX4sLJ)(XbQJus!E+||oO*zcp?>yeKwokxEkh@gl5qSU{Yb3OVu zQ(J2i4IK+VaE60k!}C+8p>9z8)!G*?K-gTm!ceavi}0%yb%S>IQwL%Tig99M4ThfM z>CJ8eyeo7qp}5CreC#P>YgkU^wiv<~M|`s9wBZz?<0ojPwc2}9vD`}sFM?VZsqAa8 z^Q7*bQ2^-S9ysisIcskHoT*c0O&mXWJd$2p74Ag0PTl{1H{z16YTV}GXxupn)J`PM zN*Ip+LY?2K&~3_uc%A~G-@Pr_Xp}(k#F(pIE{oXuTq|KEXjf3xR}i+xyJ40wT}vpa@i2$-vw!lX@8_??VV$W zf&FrDg|d`w@(}7d@KmNMZulw(X~TZEzfk+?i(b`-)7cN(^ zbzg!XRH&{iV=q2>4$7XZ#N{e^3$!UH-&e;jTvudOzl5>Z5a-tSdw$(UmowCXnt)BP z85)mQ#!!3`txhGjl>LjO&6+Z=GU>rk=vqfOmLwZcImfX8l%J}`kC&x>F`+JSd0#o# zk18JA`B<3s8p4YGWD%P{DIol_7N_>(=~F@W2x7`693e8t)~jgm;$}`31G|yt)pix+ z@`C=P+F!NCgSxMrT(AZ667a`DESnPT8&w)S2}s{oRhHcJa>ShvvE8l;x52jEWHFp# zfOUuxhefktPe9Ut9SjWC^}4ntr!!INOI<7t+*td(U>>4s#!(&fE_vKgIBWDB`?QNM{3W zy}haJGQlyz)0p{Jie}@&bs5L@VQ62kMqKTkZ_ETDdTlg3>BClFnMmo15--X3A&mGB zwNbmsS@KxvXG154t4p^pwF}4Pj=&#b6Rn&%HWZukH;Px-JMI<{MeNbls?^~+m3NH`b&}V|N8kP(XyarUA$W$>=|6<%N z`2GMq42k?|*x^8xm^}z%7jg$!`i`t1dDZ8rngXhBCWdXYo9EsY9Dhw5H@^6H155&O zziq5iqR%ouUG?=JS90z7+IA|M9A}~~gk;`#KFBgRlwT#z2J;JeHT54{Y=PbrwYQhf z{sX4cP3dZ=_Q|GVzudkzX(f4#!pXTC!2C8uc(qsG|6E)a?z|5|s`0aJLB*XKBdIMm z`Wv?7ZeLLj?%m?@Gwf{x`G5Q60@t_{K4?7$3x29+Cfvk)<-M{r=k01YhvfcI8_5m# zbBFUGx%sMBd!Nxwyg4-bp*m(J*nZS&kP5ZZ`<$>XgzyFV{D$Nci~MN(>^@M=t!Ru)&(aJuwGbpMH@$pOeI5awDB=>7+b$3fMd$ja=U z0`KP0Qp~+ng;IDY!$&N;Lo~N4aj0=!%64j-2dO@?wxWu&vb#WC8#Us>w%E0v2K(8; z0SH?c4oC0CxCiL8_{;>2doLt1TmkHrG=BjI80=J$oIUtn_BBk~fhe|jhaFAlf#PQz zO$|?OoFd0Snq5fR-18z3JlmOcP&bs-)B;4^qy(F|Nu8cufS;QQA!Suw4eni`q}|Dt zW~)$m#ZmPzOk!)rXTzO%*L)-9KEbi%ecZ=Z5r5giKJs5qPlTKz9d_gLo9|%YT}Va# z?s5fmG+$W`ytm}Ga_5O;3md&OpEPmX@0dHp+{voY!3L^TSB5~go}P^OTuL-xl1VmS%4v8>#?+wmq^ zo9V#S_@V<1Y_|a!We0&g7ioLY`gs?0*-N!--=_i6?KB#U42PN5p|K-1qO=l+4!5AW zCz%6IHpv{G1bQyjAT&uja46LQbS-prRu5QqN#woYpTR2Vl z29Q~&CS#8#EqG~yZ=vP&o*p@DnF&3<;^5nG6~hr{W0vont45qg(G{Ef-(%y6Kt>GdE>+CRawv+pT?eDwYdm;8_{S%_O5<$=N&5S_(1OYh$7I1JS-7l3b+>dv_^{!SSw+ zvIGIVX}A7hABx$LB=R0BS=Za00D^0T>;bR9==pf_k|F~Pww%A5LqROkFXJ1o1?SYaZI~t&ThZwFal89gjcL^rH(s$=Tu=yzlMB~IZelJ6zmcLT_~ ztIJAaa&|}eq5U6a&mIP_!#EG@U7^hYi~r&4zG&~@CbwATDB)&low}@JT!K9(Qq8zu ziGMgRqt!dfgcG;+wcJfKU-JImdG;Zg?R>%!_6KBhdjLnPcx+?OJ)EF>VCYTMd*KQs zho$y2Ut19)UfRWe0bz|>3TqKIu*ukhWNlp6hBAzfW_wxr8>hcAd>4`zQu`$J6<$c~ zp(_!ch2_lGP^_j`Z(?|J(EO{nNO~s%hrv<&q23&Yvw0br3&od^q>~5Ij_MD<(~WN4 z(93EL#}0uNuWjGl zT(0OUWFx)on5|?qUJV^?%G1_+u#8uAHA?&xBcTlK>u7>X??5Au!S7OuH(alC>Kq2i zZKaYa_M+|UfrRTBgTN>o&Q2{_r@pig1#x3~-URyu>Gr}Cq}Hh~{_D>OPn)8sXz7gKzV_FD;?_5d8l;SAUA=enzmk_y_?d z@cBW z>r8ww`~cJraikY^XzYn!2Wej`>4h&AJK`px^;;Ec!AM!CCje`!lstU;gBQ$VPX=2ByB$u1Us&=bZqWU*&dt9hZMlh94Y4CRo^;I?_Ic#&=Wy zlSqdY+roM440!baZWj)-ep7 zV*l{%Ewpc?04U>3jXj=vS{LDA#U3aFNO=JDOiBs4dF^3qT2UPp%H_M}W59Gs$(TZk z2`8|(0iQ~bYGlk99?yg9A*%n{KD0d9%2Dl|J>WY|wC35YR;8QQzs<82lm5gje>Tet z|8!`0JeheRO_MkhNB6HVimM4CNQ^PnU4et|bjLWf1Z2BCV^5IXL&;8V<-37x(YjXJ z$ojtmP4iU`Io9CM(8BA^v1PGUrU{R|WV5O1^}F*TgMtgX!PU$TI7F8e=MAo1Ih>HplFEz8tb%tvnaJJSP|r zzz>dhvaU?Ha$Ii%vKHxzj{;Rm*#|eeVCIXw(Q*3k8O&A~{%-OT4T5na^n$8SbUxFP zm*h&kShFKEeyI1G!jD+<8!%6MrKH4rm3a=NcN0s$%C6InhFxGDRoXX;19R_03%&2= z-nLAq>)Z>S+iB;a{<*?gMMXVFA)npb7UD{s+6+S>a=#u0jb27ge#F5f8dT_{ad(Aa z);XrJV)HrQT88$Wx(A)t40 zW3hu>6oSdIyaS4T2)dl`TRD=q^_{`?3Z=KM#=G3pAFZFb*5uJ8@p=SWA9HfZ=KRkk z*Fq8pII{~9?AX=95oYh_{Oi`oT9ftODBHR(Er@JH1L*8@YXhi9wR2K|)s0+(zDv~V za`vps^|T)+`PW4$c608RBUl2TU+1h2yD!$>x9I$ZW4Z86A~)^PX#AT}gN3gGx#n}h z?^udoa3h)XaBrhIMOcoL(+EfQQLy))J+i&Sic{_KNGla0Mqa7xYrw9A5WLyuEY_V6 z*mI7pY&Eylqw8R`qHM;qvHO96)14lw11}L`7q<^dhd$Itq3bGzI=)%L;;>aCzHlxd z-p8g5J^UOEzw#*&2EWhNZx74!8V|(YZTzVi{RPzpY7_9>wodJNDy=wK^_?Dfg=f9m z0o%l0=(aDqiV_uJtIS)mqrvk9BoW+uVpMO5=1Wy189eMK?1g?GgYsilpnwp2%s< z&kxz>A$#fI4fnGc0*_g#=-5FCXYp(WuU%A=*6=*`f zktn^=D$^mxDxDQeKZEW?O#7$`vcwjAanssw1+-SjhpiHKU4(&u<5|7;kh9S`nehZq zZv6~n?r;32oRncdz0Tr(7W4n4q?^Jg`5fM-Lziz*a~7WkU;>AueKY6BGTx!k3bZ{! zica2hxRD0|n`e<5D@Ao_lFN=Zgd|;YyuB}Uali6i<%O5_>xa9j|M73^uYmo3q0-J( z+v~E9B)bS*?2Omu(w&<20ce-A<46J_Z=>H2!2OJL1rV_7tA`@aQ=-voRmEO;S4=ND zN5gd!Pn#Ej{!0Bx)?RKTDs5Tq(dxQTWEN0x?7azn{Oxqrc%6kQI2Zk2r(ZO9NB+s7 z_{nUKOFSU-9Q3zPY))mIeA2+t@DilZN4uBWZyCA9Tha3{xA5SWg!SD{1qb=!m1Q+WmVqp?+c*u zLw^p|?I?_Y8(|qA?eM@Hp}UZ8@yj<}060%ow%H0&plZ4A?y~liAC7E$QZbjz8#|te zb^bltnLI%QQC%DS96{9fqNw**jBJmK=6g?VDQoI}Q;S zNvbGaimts?-nNd6qxcpm`D3Cusmadk&S;q0Lp*O1z0(K-G4TNBPf^u}Z*bW1Q4gvK z6pn`70u7~~q<$h7(pGhyq*k=>h zcvQk_+!QgRi<<2V=;GG05WE-DCB(G}!!jE{NFN0X7s#nB*i3IvNq;eHS z0Zk4Hw+HJt>1Ja@;kuxc=`H|wCq+@iS5Rp9r4~rUyM4k&&BMTZOvd9S3*SZK4{94p zjstu-r*JZabA$3_3ZKz*v~`D0ey6GJa{$KL91Q#WI|in}_|J6O#hYWlf|V^#`J}=bmnpe)-ViA60c|a0;@rgj z(b`X2@f6fsy6wk6w&Dc|rMoSzybO}PvT~>j$h!!;0hs}^}twkkh)%AC3R*{;0pb&boy7#+TF zcasCYpMZ_JCO`1j<8SeUMXH)iP+>n-=rq?Es(DG}=VgT_fVUk9clL@T^L`mX^9r>m zuR7T%?04--)S%0&b2j7XRBP*B-bXgqBr59*)!xg^)U^-Vvbsg@)e~)vetR=O^+&R% zpY|e5 z*E~127Jzw5>BFb%*w79Fd9Ub>#oIDZf=s3pQX{0AoUFfuF8@?v;;u9Y!1K`cFP*gE z!J>DyW$`BI)HXA_kDoSW{G38I$)2aoNuAm}RaDe=;SQ;Vb;v5Uh3rSD>;o@L@hU{q zi~|T;;MpPZBKVNsoQFv+(|O^?nP}hOkX};Rw5;J$2<~OlO>vU2^8CO==>8H<_%?#_ z#J`QjBnc5&HRF_7jwxHB?Es2KV5jabnE_GF+^i+FIV=iJSQlZ|*PYu+E*x<}_fUxH z0N1y0ZHL|BtLVPYxn1lMY{u8a!f_DTTWU!@&vwH&(o>avolDAi4fFrcLsFCUV>z^y z(s%%eUcC1^AKhCy@{(e)j`J%p_md>=8hfDOP%s3H4Rlsu3J-T(-xne7omDJ$A>?h3 zJ;ZsM5;G+^6m!mI%A<;!9Ab{BJcnv;aNsU8W2^eC*08`vWE^rGfacAdlI%-A&Tg*& z-g~JK@urnc>1K$aj!Y@*wf+x%A8>5i59$#%D#6BQY6*oeMmq`BL$Mpw63~~#w*bPe zp>+fCzFRkJh2Q05yJc4JPPF|%QFBGIck9TmI2BHv$)O61{WDBjr*>Ug>0Mj+ACQt) zq{N};_5OsIe%02j_Zgrw5VU?wF0XK@kEcEyfEY@)nPHFeI3)EpnE>xoXMpDWSpg)9 z3dnz=%0G+Ot32$7mR$$JEU&J1S6%EzEu6!!*}eyIMTN|j>unECbueC)dSYJ8^L^*{d(m*#+7h-VqvJ3=dCNTby;ukmj| zqopVN zGF|o=(%GtEghrm7Yzns0&OFOddzbNgA%;#VCJP?JF?AIBzOE$K_y;71g67@G6&2gZ zgRbvYF#K(ltVEpb$j*g0D|Kw-TzF|+3lm-8bcJ`kUW9EoH^UvybXUwtyU#KIDCGFofHfJWbTg2T0I!paN`zLcP5Gttc47HIFJ?KS20GgeMCOCj{G zs!x0(mi2itnEO%*$J=P?IsuJi98PR5%Wm8Fgy<)beK!BX{(ybkPMG~MHnT#>1#gwF z1y-xb-@~Igf8P#@TcfVEF_v>^%|ms2`-=DCo*U4A5Cv8Ekc;QKUk0qEI=NTaO7m{) z6y(}hZP12#{5`Cd;2p7{OX6@2XIQGJ|ESc2ne%4Mt)De>&Xl=R4$luvElL*^*?Ub_ z;9k?3H;!0x#YCACFpKXbffZ!|GM)A5dNS;WsUa&d^kMcF^V>Rz}OB%mnc?n zY{UwG0@}LU4T@@wP2Q~75fg@0_}I{dlJ!wCrxhVn?Q91H77@5uJyU*Mca1X=uyI)BWBH>GGp$f`dRK_LRaif z|JN;*D*9mKHw<$MzjnWk@!Qw%TU`DnCHbeL%fQoJ%9Hk zfTE%6G4v{rIviNB&+Gx>j#Azl?o)C&(iRNf$mHYn+uL633<{p3Mc7tPClVq^Z>Fh-voZwk<>C*qFd`g%3jCujoR6HL^*SgDie9 zk7o82-U=dJQ;>%}Fs?;e>53}*1-K{-BU6Io0NRsW3e{aqgqCG(=|zVu`y&4a1vkq2 zdY^>q4$*I=i&7!M?K+uKEBTR{Zp zFf8nP#;UWVb?%L$i2i+(!-zWj;kZv4vs!}L?_|FG(%bu>b1jcvs7ueN`x>}Bfn2wD z;Mf6;@3_UP@HWe_HWT_k#}m2t5m~Fgv&doKUTQ7J!!6N$gTkj!HpIzg0pvEAdgJMZ z_v-F`a5l_QRyLAZvX|Yus4bS{O4-P54xz2iYqI_#dj=FTM-|qjBGh;Aq8k(_h>J*< z3(#0iVFm8YxUix<6g7M!O?dhE&mrt{J$bUYHiJ07cMM}<&K%fcb9Ky9akb~z{s*QG zQ~PgB$vRawhYPrrz4u0U;p}zrzHV(v?(?#rcort|1<8f|#K92D_lmG26y=caB=Fsi zyfXaAFz$aAM0XT<367ZBLMjuSR0>B3j;r5+gFBRKcs7>VQ1CoLr^SO)M#-y~bSF1( z!(AIUvMqbO!HtZpq!;2X#mGmiOQ`9Mw@9w5z2sS~)7t3XtM&XcCffdL zusUL?T;X*qztj2BzL$*-LIPv09!7e=D6;*$*!|)d4Ewvu%WAz!4zECMr??Y;yBl^V{;eRo z-LzlwNdQN-Ek)l&6;i09$L6{UL^pSiGvn2;y9CF4+m3)agOg%JTuR4Ka#iuEu?rW!5X_1^mnEmMXBe>Zi6R#kdThOJPC9F`u1}(fkb*_2{#N){YGtOFV3jRJM|Fu!hYZR!P?(|aO6@y8GxgC|cWIM#f*~__=u5a>{ zB*)fTOuReOmQ+o#&e8qkVfgXq$%Wbdgcp3r_`yRI66E}gumj;ME_bL&D#_94eL&n5 z>coOfj-A-HfK)NDR=5LB-QU9v^P~1g;m7*J^AqOIoNcRV*Uvq2RvsYlPyl($)PaPH zWRbI9Np<|$RDX)?Dmkj5ADj=_KgZCt$CKV;sR&ZM*-6;{v{nYgKd%x->0cUp96G*3 zjs!Q@i}?WCJ}?^LKv`SHRrJ0A=62PAv2-Aw_l{faM*1L93^oLw;@$vbEflr3q=`Em z+Z>=hOQlj9azL{qRC+tXHMTbvoon6;!|tTRW;lz!JBBr$I+D_~B$Brvuf51k6qY5Y zt;b-8!$~4l-aCuWA(QSje3Gejeec82IfumLn8Zs|ehIX-)fER9n>aW;1Fg#msmyX` zv@O=2HrOG7v-@o*N;aZP|XNy+5JDFJk*V(9xd+mOP<#T-^@Jj#XdNaI2kE zWjD}|sLbq#LO3R>#@x5l@)u|P3PO8fd{K)kJV)_7?FE>i#+NH6;@3f}Z5R$orr*(T z3lz2@!?AHHM|@YnagJX5Pr0BWxRXWTSA?S)ZCNMoZW#y8*3fqwYFdbOM3zMu2N-TUc zoKqNAj;bh+LQ_#*8&%nJa7sDZPfA?IgP|Iijh>v8?IvWBN*UVYOAsGJd(Y@pW&eHb z4)5>I-R)(=TNNu!KD1#V)I+otWRp<;0V$;l;!68g(n2Q)!x%aVQ`;oM#Rh@`k@$n%? z_h@|lJ)49X6K2hsK64^I0AGkPIyJ@^`x95T2n;*wd%)Ad9+doK@cW?bW0fbmdz+EN zA?_2LMDd|Azpz{fP`;;*o_vr53UPd2i_tsk=vXD}l`_ZLEs*Fj+TEUddO^bP=zfKE z&qek#X|8u)(Dty>R(K`F!DkNCy`e50U$IG68b{r5*kE@x?}Gh%tMYv?#C2+=g#gYI z&~f<1v&sVEQ(`}~i;*s{NNKtl$8NVC@grN@qG9hf$d2q*E1V#*`xpz)^f5d9u7%Xue%+ceW54k9u|he?S+G_|r;3*Dl&a6qo;_oxD=KgjlC`fV zM>hwn#>)BPz;Dp@X`~M9BE4i(5!7*~_ANvlPTM8W_CRF`%1U-J-Xdm;e?P4TY^ylA z{-ZJb3ECEycw4{@Xnk2nuTCzQxxN!2kS-d9m&Kgnxd@XkC$b|i%I*iUKhS|aH$Ml% zKA`Br;Wp80A9g+AR*%Re1tT3rBO$A|82fg2LcOO0`s>u;B!!501a!(-l26A5@_XqMoAP)xeP#_Nn@<Kr1oCen8v;og5hH0M&5RTo*~Cb5BQ1=y zG_t9YRz_MI+04l1M%ozJ!bn>qTN-I+WGf@>jcjdX8zUWzbTrb*$hJm08`;iC7bDvn z>1w2#ksXZeXk;fN-Hq&QWEUg58rjXr?nd@7vZs-~jPx+Fw~>8}^fc1TNN*#3jPy0q z&q#kG1B?tbvagXrM)otZzmWrs9B5>)ks(GhMgk+oNN6N75*sNtGSoy6xC^n}*UVl-8ka7Ru(Kv zHlcI~rDG_aLfJNy&Y^4>SE2q3jyUZlUZR${wNY z8OmOv^ay3|Q1%I>XDGcw=^aX+Q2K__FO>eF3ziU}nQB?=`Dr8tzKp_GI&ER@nvvZ0iPQXWc0D3zfM52Y%UTqxC{)PzzS%7{?v zLKzv#s89|HWppTGLKz!MeJJBX86V2Qp-c#6Vkr4gCWSINltV(963U^WObumPDAPlk z5z5R^W`%NCD6>PE6Uy9B=7n;2C`W`cKa?XwSrE!mp&T8`F`*nA%5kAA4CVMxP6*}1 zP)-Wvrc)SA?=Wlog>|8Ol|mTph|appwIcZPCTD0hc)Pbl|>a$hL-hw?xu4~FtkC=ZA7NGOkn@>nRV zLwP)uCqj8Ll&3;@I+SNZc{Y^iLU}%v7eaY4l$SzzIg~Y_yb{W*q5LnD*Ft$cls7_o zGnBVNc{`MMLU}io_dq*El@M$$Qw?IP(C$@Y>bHIk@SqDS0ue7=@UucNcu(6Kav5F42)#oNCri+UnKiSazG>pMlv{(A(3Pv z2_i9(gpov%#E}$7GBlEsNQOmH8c8;ivPjA!sfeU9lHrk5MUso8I+B`5Y9kpDNnIo( zBN-LRL6MA(WK1MuBdL#MTqNToIXIFDkxYyvAIYRhCP#8eBvT?eG?J;2Op9cCBr_tJ z8Of|j4vS=VBy%E}8_B##4v*xBNaja!WF!kBIVzH)BRM9LV`2auWN{?tMsi*xOCnhs$@!675Xps+TolQ& zNG^`#l1MI%m#`#k{ctrDUzEbxh0ZY zBUu^AZIRp_$*M^1h~&;l?uz8@NbZT`-bn6?FGliGBriv@CX!boc{P&%Me`MBp*idQ6wKn@<}A0M)FxCYa{tQk}o3pGLo+%Sr^IIk$e-$ zw~>4o$@h``5Xp~`{1nO0k*ts8mq>n%8cVBKTF0_kEStyDCYCK?X&cLyv9yb2t618{vUM!m#L^*_ zj>JCVSoVu$|5y%)<-k}5$1)_AOe{ex zCYCUkD3&;u;#h{pQWDFsSW08b#!?nbc`OyNRK_wqma15Cu~f%W6H9F@BVwtGWn?U) zVmT<5(Xot)Wo#_gXeE2K_>$YWYF25i$Pa|1q>E6Sjb>ugGCG$HCW7Gaf2lcmNZz(U}=M843;%m z&Y+vY@&+pytZ1;3!O8}!7_4frn!)M@YZ$C)u$IBv2J0BCYp|Zd`UV>qY-q5N!Nvxg z7;I{=nZf1;TNrF<(A{7wgRKp=G1%5%JA>^Fb}-n{poc+EgPja^HrT~rSA*RQdKvUK z=wr~=pr1j*z%VckECbuXG3akFz+j-k?goPl_AnT1FvMU_gS`y)HrU5tsKLGl`x&$u zxCWkqZx9%S29d%31_u}nGZ=0V8zcs)L1vH}6b7Y1Wl$T8FgVcQAcKPq4ly{?;4p*3 z4URB4(%>kAkp`m-jy5>P;8=s>3`QFqZ*YRa7=sfH#u|(>ILY8-gHsGnH8{=Sbb~Vt z&NMj7V7$TE2Im+|FgVxXJcIKMCK_B|aG}9P1{WJ#VsNR!Wd@fUTw!pf!BqxV8%#2o zY;cXiwFcK2TyJoL!Hott8B8&lYH+i`Ee5w5+-7jQ!5s#78r)@Yx4}II(+uu4xX<8z zg9i*AGhA{xbO6;2(odCYZ>i zvq=||t|kkZENHTj$-*X!m@I0tn91TMOPDNavXsfvCd-&CYqFe4H21=-q_0UolZJ_5VwzYc zwuxiX-(-NvK$G1~2AS+(GT3B@$(|;Ane1({kI7JzeNFZ=X)|$6JQLp}FbPc}ll@H& zFd1et+$1(hOj47~BsVEcN|VZ@HW^`Zpvgfd2b&yXa;V8+CWo6GVREF&Q6?izMwuLK za*WBbCdZkKHaXtp1d}l)Cz^~k8E0~m$;l?Cn4D^In#t)VXPBI6a+b+>le10EF_~a; zuE}{O=bKD4xxnN?lZ#9)Ho3&)Qj^O}E;qTtQ!oVlvg_W|Lb?ZZ)~hbm@~z2tCf}Ry>kVR*UE*4!a7O+^*Vj+u# zEf%p@)M7D<#VwYwSkhuCi={1=u~^n(Ig4%<%Ui5qv7*IF7AsqsxGKv7yCA78_e^VzH^kW)_=UY+EVj1T#$sEG?JTyp z*ui2)iyjs|Eq1cl*YZyITyh z*u!G5#Sn`}Szt;aYeWzC~aWT0|E6TO439%wo7jY>`-`7MVqE zQCO4~l|^ka!s0-SgDeiVIK<*mi^D7qw>ZM$NQalOS27B^blWHH5Js>RI~w^-b2 zaht{M7I#?OX>pgu-4^#)OtZMx;y#P}EgrCV(BdJBhbx z%~Cc?+bm?@Y;UuJ&5kxbY}J!;rngNWo4z*vY#KI(jcH@q*fx$$f13d|18sJ<8Dz7E&0w1$HhbFaWwW=< zJ~l&b_O;p1rp?B+@oapXz$UbbZ1%S~z-E}uaGTgBu}N(*o7|?bDQzm7+Gd2!fi?%( z9Bgxl&7n4j*&J?jgw2sQN7;{%`rB|+8k#y+U9th6KuxVoM|%ZO*ni$7X`fxi;t7oNqJH<^r1wZ7#C8*ya+OOKmQ*x!mRo zn=5Uuvbox3lFekBYizEyxz6T#n;UFyw7JPbFa;PHuu{+VDq5OLpBfFJYqB5=24r+Y#z6H!sbbvr)-|KdB$dj&9gSo**tIa zg3XIIFWJ0o^NP)@Hm}*dZu5rCn>KIRylwN2&AT@5*}QM_fz5|DAK83t^NG!;HlNvi zZu5oBmo{J7d~NfM&9^q+*?e#FgUydNGi`pd`Pt?dn^`u$+WcnoyUiaqf7;BpnPc;p z&EGcv*mQEhK@OcAx;S)oSioUHhlLy#c38w=QHRAG7I#>}VM&Lj9F}%i#$j29 zEbp*_!-@_oIjrokio>c7t2wOhu!h5$4r@8A?XZr+x(@3(tnaXa!-ftUIc)5(iNmH2 zn>lRmu!X~x4&5ELa@g8o8;5NjwsY9tVF!mD9eOzQblAyZXNO%Jc6Hdzp_fB%hdvH{ z9r`&m91I83!E&%29Ebi60~`iA?CvngVGoDF4nrLFblA&bZ-;#xhC1x)u%APlgX`cq z_zrtr%;iSS!a`CDy93R*SWItTke-8EdUrYsXqA*1ECQ zi?x2N4PtE=Yok~j$J!*;rm;4QwRx;9Vr?0#d#tTuZ5?ZySlh?&arlhwQH>1V)csEJ64}qePi{D)re)pGGke>>{w2${;>wc8W?N$Sc78i5o>U) zA+h$1wO6dYW9<`bXsmr>?H8*pmK)29<;MzQg|VVo`^P#U*05N^W5uzOSZS;*RvxQ} zRmQ4f)v-pzIxyBju?~)PNUTF+9Tw~GSVzP*!d=#5y+Caj{0nIzHA3 zvBtzYG1k~v<6@l@>*QFc#5y(BX|Ya^bw;c+W1SUie5|u$ofB(9taD?X7wi036JuQv z>%v$U#kx4wC9y7zby=*-V_gyJ%2-#$x;oaRSd(L26YJVo*TuR%)(x?4jCE72DY2%; zx;fS@v2KlZTddn--4W}~Sa-#`JJvn1rp3B9)_t+=kM%&T2V*@H>)}|B#F`%K(O8eg zdOX$>v7U_eRII0CJriq2tY>3A7wh?0FT{E=)=RNoj`d2cS7W^v>-AV~#CkK3M9U@WmT37zDBL|Y`gXvai767@{9Q=**{?UHEMM7t&Gm8f^3K8gA!>X)dI$Vg-+vJ%;e zoJ9Q-4M;RF(e8-`CE6p=;6y_b?U`t=M0+RNC(+PE`zG2iQClK6k(bC%6eJ20MTz!L zbU>nEiH0YN6D5h#L|LLdQIV)jR3)ktjYxE0qJt70oam55hbB5K(cy`XNOWYPqY{lw zG%C^2iH=EhY@*{5jZSoYq7xF0NpxbOv5CedIw{e~iB3s$YNFE;ou257L}w;CE7ABw zXD2!*(S$_jCOR+C`H3bbx**Yoi7rZXaiU8SU7F~!M3*PJBGHwJu1a)uqDhG+C%Pul zwTZ4vbbX>565W{SrbJT`O-*!jqFWN(n&`Gfw^NC(a^kSly61|-0 zl|-*5dM(lGiQY)`W}>$ey`AWtMDHegFVXvnK1lRoqK^`NoamE8pC_OVuk? z?^JzK^-a|;RU?&=%1mXYvQs&!`llL@YGA6}Qw>VBN2}p{e#w zwO^{XRBkFSm7gj|6{d<(?Vsv^RKrpYPZg(1Ql+V~RC%f*RhgcCV7r8+p( zA*l{cby%vyQyr1&$W%wA8kuTTs-sgKlj_)1$E6yb>iASAq#Bdz#8hKbjZ1Y>s*_Wl zlIqk{r=>bQ)fuVIOm$YO@u|*Ebxx`Ysm@JxUaIp`O-yw`stZ$HlgrUJQcX^EO{!~CU6<gH6pq`EcLZK-Zgbw{c@ zQ{9#7?o{`rnwIL`RQIL2Kh*=N9!&L6s)tiOl4^RYM^inP>hV-hqmU#^-QW6 zsh&;sT&m|&y^!j~R4=7^In^tvUQP8{s@GG!k?PG4%W)jO%)P4!-?_fvh4>cdnY zrTRG4C#gP7^;xRVQ+<)@%T!;b`a0D&slHA1U8?U>{gCR%R5Mfklep1i zrTRV9AF2LKH9OUuRDY%VJJmm_I%Oi0GIh?>B~#Z-3uIa_(?XdR&a_CTMKdjyY4J=; zWLh%QQkj;{v`nUDGcA{?Tc+hRt&nNOOej^f z&9q*o^)qddX~Rq#W!gB?CYd(Pv{|OjGi{M+%S_!fZIx;3OxtAIHq&;Qw$HRfrX4f& z$ka2_PMLPjv`eO4GwqhCSEk;X`ef>xsb8i>CL@!X$;xDBax(SLG$7N!OuJ_qlxdGl zgEI}uv}dNhGVPsdpG-qD?VD-8Ol_ImOkO5GQ;;dl6lK~!(*c==Wg4C-&Xi7-02XF4U*shLj8bb6*UGM$;}tW4uGot^2NOcOGlo9Vnv=VzLj z>4HobX1XZT#hEV2bZMr`GF_hOicD8#x+>GvnI>hLoavfO*Jipd)AgBd$aG_-n=(zw zG&R%BnQqB+Yo^;W-Ja==Om}9wE7RSX?#VPQ)4iGQ%XELH2QodF>7h&yXL=;l^h}Rt zdMwl9nV!h>WTvMwJ)P;9Ofxb)o9Ves&u4le(~Fs2%Jg!kS2Det>9tI+XL=*ko0;Cq z^me9qGQFGWy-e?C`XJMXnLf(&ai&i)eVXaBOrK}^BGZ?dzRL7E-MK0y)oU2Q&uDKS- zwP2GFoonG-i{x4~*J8OA&$UFZC37v6Yw29e*ZQM*9N&Z%(YRjjdN|1Ytvkt<=Q;g7P+>})jii% zxwg)=O|EToZI^5NTs!32F;|aVJ#+1pYv)|MYb}kuD-eY zTqARh%5`+EV{#pv>$qH_a~+@Sgj{2CotSHEu5r0e%5`$CQ*xb}>$F^_=Q<yliT=DIA`<+-lNb!D!ra$TKkQm)Cl zuE}+6uIqALpX-KPH|Dx2*OXjSbKRWlmRz^yx-Hl3x$ekyXRf<)-JR>6T+?#ho9n(@ z_vd;b*Mqqp%Jp!rM{-Ti^=Pigay_2wiCjnCqon zFXwtC*Q>c+%k_G$H*&q1>#baG=XxjCySd)W^?t4oa($TVqg)^7`Xtwz7=!a{Zd?w_LyH`Xkq$xn}2@lk2Zs zf9LuqSEoW0QlZX;x)kbKXn{ft7Fwv#!i5$ov}mEl3N2n}i9$;jTB^{}g_bF_Y@y`} zbt|-dp%n_PSZJj}D;HX&(5i)2E3|r{H43d+XstqP7h0##x`oy&w0@xt3T;?uqe2@O z+N98?g*Gd+d7&)|ZCR*$p{)vSU1*y^+ZNic(DsFPD70gt9))@q+Nsdag?1^lYoXl= z^(xf6P@h753-v41C}b2e3t5HiLQbLng$5KFSZMb`g9`0YXmFt+h4w78SE0QN?NexI zp?wSOSE#L!TgWTq7YYi6g`z_H7doKOutLKN#f6eWX`!r8UZ^Nk7OD!>g+>%Qu+Tw; z4lZ;^p+gHDR_O3TM-)1;&{2g(78+IP=t9R7I=0Ypg+>=TzR(GU#uPfS(AYxb3Y}Ew zcNMz3&^?8w6}q?3eTD8X^gy8p3q4fm;X;oTnqKJ9LXQ=CywDSco-FiKp{ENy zQ)ot^XA3=7==nk~6ne4HONCx8^h%*u3%yq8^+InHdb7}5h2AdoPN8=Ty;tb{LLU_R zu+T?^J}&f0p-&5aR_OCWUljVX&{u`NF7!>IZwq}_==(xH6#B8y%tAjE`nk|Ag=Q7{ zwa{;celPS#p+5`FE;OgmUxofI^iQEqr6{FRolA8o)wR?Dr4}r;P^pDWEmCUHQj3*Z zywnnzzrPeOB zPN{WEtygOOQX7=ou+&DSHZHYEsZC35R%-K7Ta?m%K&fG+hL?&X1^0mO8A|;iZl!b!4fdN{uWvs?^b?jwy9)spCqG zE_HmV6H1LKbz-TprN)&ysnp4(PAPS2snbfGUh0feXO=pv)c8_ompZ4^gi`00IE-H0#sY^;-TI#Y=mzTPt)Rm>KDs^?KNu?&2x~9~%rLHS=eW@Et-B{|T zQd3GzEp>CLTT0zp>b6q1m%5|Wou%$7b$6+IN=++uZ>jrA-Cyc~QV*7TsMN!y9w{}w z)T5;yEA@D(CrUk8>ZwvsmwKkuj8e~*dal&-rCuoYVyTx(yYJt<>wK-YE5E zskchKUFw}u@0NP6)cd7ADD`2fk4k-9>XTBRminyJ=cT?V^<}BAN_}1Gn^NDF`mWUX zrG6;&W2u>?ek%2Isb5OXD)nor-%9;n>W@-?mYQ8^PN~02{axyxQk^PMNtHTR>Qbp| zr3ET2*c4AxTDa08l@_hESf#})Em3L7N=sE*y3#V0maVj0rEZm$ue3s?6)UY&Y2`|* zR9dytYL!;6v__>hE3H*&?MmxZTDQ`AmDaDcL8T2VZB%LFN}E*Lw9;mkHm|frr7bIU zue4RAtt)L)Y1>NMRocGN4wZJS)T2_*N;_5Bxza9`cCEBqrCybKSL#!#Z>4^f8kLMn zW+khVUCF7`ztVt811s%bX;7s-Dh;kQq|%<1_NugZrF|+5t+a2Y{VKIpaw~b2{7ONk zuu@cM|4Ii`8dhm|rMOa3DXo-M$}1I>%1TwGy3&YB2Ua?$(!rGusdQ+i!zvwK>4-{4 zRywNE$V#Is9bM^|O2<|@uF~jA$5%R`(wIsoRvKGrT&0sLom}aZN~cyjtz4&DqUOYx=Pnqx}nmIm2RpurP9<&H&?o)(yf(lt8{y%J1X5->8?t5SGuRtv`Y6@ zy06mxl^&?{V5NsDJzVLLO4BPnTIsP$k5_u4(vy{*s`PZFXDZF8^lYW)Dm`E6g-S10 zda2UOm0qdzYNgjIy5EEVR{E;a*Ok7h^lhc@Dt%w+he|(Inpx?mNRxP`hQ>%Zi0ksC!+P&7GT6@$QTx&?JJ!|b%Ywue7 z)EZiA-&*_CYOCee@@o0Df?8p%sMh|q4yZM(*6> zC)GN+)+x14t#w+h(`%hk>&#kb)f!*x>{{p4no#T9TIba|zt+TB7u342)+)Jx)Vi|PRkg0JHL2F*TG!ONw$^pEuCH}Nts86IRBKADskLsdbxW;VYu#4s z_F8w;y0g|@weGHUPpxUS?yYrSt@~>|Q0u{357m0O)+4p1*Lt+pW3?Wy^+c^FYdux# z=~~a!no;Z7TF=#bzSax1Uaa*}t(R-PQtQ=Puhn|J)*H3nto2r{w`;vq>)l%K)q20y z2em$|^--;lYkgAd(^{X^`n=W`wZ5$NRjsdUeN*e(THn?BzSa-5eylaK)=#y5uJuc; zS+#zx^;@mqYyDB{&swu<&8hWQt-oviQ>)VmF+v)l&Lh-igu0H<0wc8G2rV>13y;tu zBeduUEjB`nkI)h$wB!gaH9|{|&@v;m>b^Bvr0H`f zNVMvvFKTKu_i9mq&ND;x#iqV5YEdipnRm9PI9rDt`BH+#)H zK5wq)|+$IkU=E7bAg50HI=>Q@~+x#mo^zj`)~FyM0?m=zRT>U z+O_$!Xs6x&_g^-rytj+Fn_T!-5$dGonIF&*|G=iuzI}_|n;xFf!SU!nblzbve>Jtl z-?w}BU#kB+>i03tVtlycVHjidb#|A_8_*WI&p5G&ykMG~1M(s7QmAdj< z^Xy-5Ih!UdrsZh%Sg6a)mH$s!u${*7A3pC~66~A*N`zl*k)Hl{1X{Zv&HuyD>9`KX z?0*rW^F+E_vy8kJ0dsT0K#MnTHmz<)lAFT|Te3W}ndO-+feh*094OTCaM`S~tmO*K z+_fx8GdkMEe=9*cA1?)>4J@sNwVGqnoxX ze*5&FE9q^$ACENcPqkFQf7!FGAMu)JIK3nEe-Q_*_I;XaAhHTU|=qrTp;>E8hzD1v<&&G|AdnR&mN+11)JW4C1Gwq{PPj+@=P z*E};HA8W=mtV2ZKm^+fTT}GcbYkG&4+xB0De#_#|HLu*LRcW(ynw*=n3m4rR48Tb+{b=c&4wzz#t^C$*&bm2jbL9Jwg8Ouo-+ca(Kwm?z(51d;B?J-SjrsTic& zaI;Odf5dHu{dG&5`WJlAp0eRh>-#Nn4{g?XOW<>L@v~d%bT0q4edY1Zti0M{H2$5n z+HTI8=C1Qb-mLM~z%ObBcjo_S4y~PM;imn|mgxRBzUVPc@5i=oVa^@*ITt?J?#0T@ z{NL5_k$KQaPSZA}Bk}W$&FkIVdv-@#?b})ohc{blw~jLX53H$u#~Ye0@wko}Zz5ot zoc)%Z{@L8MZ;O2{Zl=ZjP}6*R$Hw+N5Q_zyJ9lp>hXK~Wc^ElQH0$B%j+eGE&!}R* z>DXZ{ePJF*=a0=)e$nx^YrYWed8Zle-@GARJN#-6{F~dY+6!rP)7-72%v#emzUlO` zEsc1vJ@=4WYxKHisq}0=2>Ul{`5A@z}IVy?tcT@-P_#U zZ@FVl+SI&XwdRhDAKw0|*xj1vH8!_gw(Gbg&VYZ(746&K+DwhnaV&G;tMj}-r#Ic3 z+TPKdto+uz_h}}sPsiH-9WdIy_FO3JmhJbi_rH|r_A-CGnYFwnYkl@^0{q(_{jBNr z$sHYYNdI1~!yY;}t)I1DpnaMgoOwtzBb!ycRYw)i1%kHr#3!3xd+q7^?y~`Yoy5{&p4xnR>v@W#IU1|=f=zAi{M9_3{f{ad*8D*Kjt}&1 z`qm!Slg-=RsiR8zSo2=qQOzQ`xT8t_XB6)|ZFI|~d&jg?%D?ZiR{wu**2wJFYOuK!WTk@xS{dV3FVHm-^7Ngq78cWZ;6%VK-8{r>gab71Qn ziK;oQr`v$J+~Mf(BZGtI@>0M0KV~7G(cW;tJY5ZGG4M(hTtZ_B9*UzwEU39S><{Z`F>X{THUyT(|xFCN|eypr!Bs zi}-JU`r_t&8QAgX>s%bfYB$($KD`t&Aq z=8s;Zr+1m%tNWZ@+x^vRp}%`|{ihe5dTY_%qpdDgZ|dGOsWd$n9ycFJGapGaA4xMG zNi!cwGapGaA4$`9K9XiWl4d@VWv>H1m-(|1U+-Xg-qW|0tjgQ;-q>WG8_^gf3+xVi5FWdO4jj!AIrj2jg_^yrb+xVf4AKRGO#!qeh z+{Q0$%xdG;Hhyd4_cs1$FTn8%YrToxh(9m zh|8ibi@7ZBvV_Z$E=##A?Xrx^vM$THbaPqWWd)ZNT~=~g*<}@%Rb5tdS>0s~mo;71 za#`DD9hY@o)^l0kWdoNDT{d#r*kx0f&0V%|+0v!E%T_L1yKLjKt;=>U+q>-GvZG56 zm!2*=x$Nw+i_5MqySemo>Fv_TrLRjrmxhbsV!7BZj!S=+0WJewc6S-%vWLrHmmw~D zy6ok$x63{*LtXZD+0UiT#dYyqe3!r_bctN{cNyjqyCg2DOXiZh6fUJpQB zAeVz(4skiuFTt>Sb?{b367?%@W#=4AiImzW@ zms4C$bve!DbeA(+&U87;WxUJTF6X#Ra5>lIJeTubCc0eUa-qvbE*HC8;&Q3WWiFSy zT;X!1%T+E{yG(MK>~f9EwJz7WT<>y&%Z)BKxlD1H>TY* zx63^)(_HR#x!>ghmj_)Qa(US05tr#MkGeeO^0>F5Va{1NeH<#aC{&4xzWwy&4m%m*8cKOGplLsF1 z=;G1UV*!r^Jr?p<*kcioMLibtSlnX?k0m{p@>tqq8INT>mhozl>v^p2v4O{i9vgXV?6HZ*rXHJlY~it`M|Y2{Jht}O z#$#KL?L4;k*ui5*j~*U9J$Clk#bZ~G-8_1E^!DiE(buD&N5jMLFg+{}+r#nb?=iq* zpvUeWgFN=|80;~`V^5F0J@)Y!>anlKejaTeu7~I0djuY#N93`;#{nM0JcfJ39*IZl zk$L1Eg-7X8dDI>UdK~0&u*V@Dhk6|5ak$439!Gi{xW(gEkJ~(M_qfC3 zPLI1h?(vxBaj(aH9`}1Z;PIfxLmm%%JmN9k<57>tJf84)(&H(Qr#+tWnBnoP$8#Rf zd%WQBqQ^@fFMGV=@v6sb9G74vHy+=5eCP4K#}6Jqdd&3r$>V2_Up!`c{Oa+W$L}70c>L)x+hdN$-yZ*X zbn?MRKAnBK_;mGIz-K|9g?twFS;S{CpT&Ka@LAGlDW9c%mhoBEXE~p4KFj;8;IpF7 zN-enev!2iTJ{$OK=(DlUCO(_`Z057M&lWyg`gHf% z%4chzZG5)%+0JKspB;R5^y%T#(`Q$o-F$la^zrHI)6b{jWB8apmXGb@`1JP~;4{!? zcb`E%d-x3T+0$n)pS^wd@fqr~ug`uyZ9cA#=i~bXKB3S4J_q;=^BL|F`y@W8Pv(>R z6h5U-etT;X%2&s9EG`%Lng>~oFJwLaJRT<>#(&y7Ae`AqSd>T|QtEk3vU z+~#w;&mBH@`rPGnx6eI3(|qprxzFc*p9g#%^m)kVVV_5Qru#hV^O(=$K2P{O>GPD& z(>~Am%GA3>X`5QozXprv#iDa9Y6W0cQl98E{s> z_<*wm&Iy75OU%>qV4+K0I z@KC_R0gnVs4|p`-v4F<|o(Om{;HiM81D*+(5%6rla{yb$nWz)Jxy2fP~aTEOc8 zZv?y<@K(Uv0q+F77w~?-2LT@jd=&6;z$XEp27DIqdB7I|Uj}>?@O8j90pA9E7w~<+ z4*@?0%nbNB;Fo||0lxz6|*) z3agv<*0HRQLD-$VWg`7>m8$efVBLjDf(Iuj5!~ziuMl2MuaKs`Ji$*LKv3SH15lcoa6|r>0G7-y0EEmx&V)=*_B36u8 zDPrY_RU%f6SS@1ph&3YCj94pT?TB?E){R&%V*Q8>A~uZJC}QJ?O(Hgp*eqi6h%F+v zjOZS*Rm9d2+eB;|v0cRW5j#Ze7||o5XT(ksJ4fsiv1`O`5xpXMNA!v48__SK5n)7_ z5mtm9;Y9S07!WZqV)uwa5qm@oju;ZLXT)9+dq?aOF*IV|i2WkkBHRcs!jA|d!iXqh z|A+%3hD8jIh$E7SG$M=0BZ`PJqKc>^MnoJKaZtp;5r;$^8gW>};Sonf92s#`#K?$I z5l2TH6LDOYSr$(F>aeBm=5obk=k2pKxoQMe# z=SG|tael;_`?qBCd?MD&p#hNfDDHu8Fud;<||IBW{Se zG2*6(DG^g6ZjQJm;?{`&#n^j?NmV@G!&`u&q9R62h&dxk1Ql?0Hp0yAva>7;hIQ_} zLr@6<=7d=>=bQuPggNId<{U8RoU^}Ecb2Nt%jf$(FAslh&+V>os=B(ny84!)%rDBV zMY*jgw-@D(qTE@OyNYsmQSK?qy+ygNDEAlTfucNEl!uD)a8Vv9%A-YjtSFBc<%yy^ zS(K-W@^n$2Dax}&d9El6it>C>UMR|oMR}7@^Mi;~7fF32qaqm{NiLFnBn^=?M$#0?m`Iu*#M@4dUB*#Q@ zY$S6dIWCgpBRL_G6C*h(l9MAjC6ZGkIW3aYBRM0IGb1@GlCvW@Cz5j`IWLm)Be@`w z3nRHGl8Ym`B$7)bxh#^)Be^1yDVk|4gvT`h|#IkBEtHshgmepffBbGH| zSu2*cW9bviI4f<5)I{Wz$$Ti)HgzwuoiRSo+1XRV@8u z84%0BSOIF_wr84}Aju?&r6SS;JdvRy3O$1*&Y5wVPnWrtWYu~f#AjioA<>R4)G zsg0#Bmikym#WFgUTrBxm8e(aTr74y%u{6h0h@~Z#v9YwqGA@?3SjNXPA(kCu*(sKt zW7#E^_E>g}r5H;TOB_oQODUF#u}q3(ax7C~*)5jcW7#8?sj*CpWqK?#V%am6nX$}@ zWp*rk#je=G;Ya$qb6#d2^ghr}``mP2DXESAG#IU<%LV>v38qhmQH zmSba?8_RLA93RUGv78voNwJ(9%PFy(8p~<1oF2;=v78ypS+SfQ%Q>-}8_RjIoFB^t zv0NC-MX_8Q%O$Z~8p~y|Tpr66v0NF;yjZS^pv! ziDiB)x5jc?EVsvUM=W>7a#t*O$8t|B_r`KxEceIqKr9c&@=z=f$MQ%lkH+#?ERVDEO$MQ@p&&KjxEDK_JK9(0^c`=rkVtF~1S7LcJme*o=J(f3Oc{7%`VtG53 zcVc-rmiJ;=7|Z*yd=Sfrv3wNE$FY18%crq?7R%?cd=bl+v3wQF*RgyP%eS$77t8mt z{1D5JvHTRv&$0Xx%dfHg7R&Fk{1MBavHTUw-?97?%fGSw7fVGVl1P_Cx+c;sktGsY zGLi0yES1R8i7b;yk3^PDWVu9^Po!reDEStXHG6Im^h-ifT9$Qp^P znaEm+ter@oMAk{9ZzAg^vR)$VC$d2z8z!<*A{!^NNg|sjvRNXVC$dE%TPD&kk*yNx zpU8kj1|~8nk->>bi5#8C zF^L?T$lOGZOXT=OPDtd$L{3WN_pB<a!n%FCURXO*C%pAA~z;-QzADf za!Vrf6S*~!+Y-4wkvkH(Gm*OzxjT`261g{#`x3c7kp~iaFp-B6c{q_r5_vR{#}auw zktY&)GLfeec{-725_vX}=Mq_v$n%N3kjRUPyp+hxiM*1?tBJgp$m@x`k;t2gyp_n? ziM*4@yNSG)$ihV4PvnC{K1}4JL_SXBlSDpEmqdO|+E6L_1*`g#{ zmZV=vwkk>gk_;%xz>*9q$>5S~U6LUs*`_2zOERn^+m>Xzl5Ag+;UyVSl946Zp(L4- zRF))LlB$wam!zg7wI!)5NqtF1m1J~DawW-^q@g5@C217gZxV3M$5zoe5#cOT&s_>%Y4xp{Yi!ihX)h8z4lIS!ZxN}XK zFEDO35w2I~xp2yZxMbPId*=cVs6|t;o8QiDZcd98*agc^aOLw}zP?(+RZO;lyhr#2 z^LoAF%>sQH*K1qpc5H2dFWcgzqg~9Of5I}MDr_jVHFpTaUt5io&tR>XScjFVG)N*!TG&@sW=NL1lRtz z0o@HQH`KRiW+*-d$`cz}FQ=z>`|%SS{tuvSg24r41v(c8_zpuHNlMpx3axxOwgNpY zNwC4iX>L9g-w$*aGM(;aU*Dxi#ooP3GiOel-afmc0{=ntK7lm(^7*n5=DjpnAd=|Zb0xWzmwdURYCAg=Q;SnNXJo%A`EVld<7`nmfBNE z>K$_X#q;>ZiFQ4?xxP?Y%O#W6hajIM-o~c3Yc`SvbE~^xQ1+sZhra>0v^OJN2em>T zK-XKj$Eb$K;cp)W26v^>F1hBQX3g99`XLvMs@HgGg;Zv^ObeO(paJB}zC!a7PIRud zmOnlhH2-QB-}6B&jpN`Z({ab0GH@%pbwysCWXE zYtfo>0;f~k%msN?hMCRTq0p3R&bBvK*S6Q7X4>~CmUWa=bnCJ;%zFx{H7K|9FM2-9 z$F8oe3<}0ZhbUw=Y-|is$T%c_ji4a9Wa=N?g@of5+ZWd^^A!7K-p4U zmmn9^(l~sn9u?d4E6$wSKD9KpJu1$eIi)lcH5S%EO@Y*p9>Ri770E(b88~>)JVq;K zbDo!G0gc1R8|l0mh9S4&`+pq=Re{gg4-#LUKd-^(7~SmXbbNiZ%MA95f)u8cwV=zr z1M0OxR{+Bv=%9z`G#``?x)>n-omi_2zB~b}y+NJV1u&Y5e&;x0O^r?27M_Au0cr1> zLTl7arBxb#H*pu5gRt`i$m%4L zWk>90R4s${)mfJ13U>``p*KKYyF1g(ZCVx3sH=d$hLFIZtDtn!&5+7wE|qM$APtrw zSHSmtPPR~=mQxIPJP1E|-j@N0D>~WJDEuH(maYa3t(YdQE@CZYJI?Cwv?F2co~z)xuKAqbWnP>)588l5CQ_7ixJRAh|MV*9xoSNvaBA_Nw2a%IY&) z>@{WD?4i1}>6=c;SCLVsv$-)c9E`l|C_u$ZW^*#se5MVS)zFB9usKw?zmr<2reu8l zg2pOuEH5#w^#QalYqA|zGrGDEtZpv>S+^K=QNfJIt%ZnQaqx|8&M>g1zzyUA;DkFR zPe6cugZ6O6a~|4X?(77avjzHAz2R|M;Zk7EN)F2m)bw4Byz z1Pv`cN)kO4Y(H+Gstzl&?TBx0XQI^k@ixf-khO{Hqm9=smq8nQ`aE4zT|I%(yd(a!orK$l- zWA%J|8ri3fy4PdO{DyBAxMmUhacc|-?`5soLZO8|T?UPR`Sg&@A&}vjXYUHBIJbAj z$o9q=v!_g-Hmfju`pn{_(hegBj2zkCzQ^>qxJUb}*~ygY?X%+Iw2AH0%Rk#;hhaMm zt2m}hMVGEi^%5+IRw|L#-}>0(xS*?h_H>(@e0mxIowSP9~h+&BATIw+TeU9rw zi*C0V!iEAx(`iO+3icDf#C+Q50WabR`t)f?bZ6r$7p!7`1YeV!?p$rSx%)S0K7cGd z-9O+7?N@yNxDTA=whV}RiP~~Cbp>`zd9>e4%1oztlIa)>ek%(s2#&UbxE2!S>DR#m zV>W#K0qztrgTe4jpueK`)g6O10|pTY*MZ2kcXj6**eG6v7a7V~ zI%+TSI$<*?v)*8sA795F;XO2dWn-h-C3QUqFk8;rTJxEpu;`^AY_=;p8!jKT_UrS=|eS{LQVt}2D#L zmYk-=SFnEqV0$~jb@Qw_+|T#{-T##-j4w<`mzwHkLgSu*ao6OD zP@hLIs?LNWu6C*dh>d`TcXfWp=&n6|`ZknwGIg9!3x-=zZ zyS|~&o(bmeO(4<(-NV#WH-IxzS}zR#XfQZOY2z{aL}skMlJ)rkG`@iuRlX2}(|18A zhx$5dTum;=E1|z(&S#LW^XZY6A$SEeKj_x1r=P*r;C2}LO;&boaBSQHeP7Hbq?=4U zk!}s@hLOgzRqQQpMe87w$|yZKB&HNHl`>aqd=H2M!^xwKI^ml54EcQpcuyB0lX;jHM`Mz8(W#uM%bO9<@Q4{3Z~0 zX=lcHMY%Q@U(b8U2WJu&pmCvT6rQKk>@gedCz_wnR!x9?o6gn;@vnJf`CKeqG~lJx zijBz>nuF!gy`cS>GGJ<(o7$V2v42=7G&W}ng?e2`+M`2fL5MfF5VJMq69$9UrjSw( zhb?BvEaUbljI$TpYcu9o`}li&e23{EJ+mAVz>nVWseK|mPkt;@{LiV2ePQ>RUPr0oLk>nP(PHu4T9zQ__UAPVg_d;7C>x(wl1`|PPfLa+q0m|*?}@~yugRJ z-$CNfb%uMeVvB(Gn_Okt^lby- zxA5T2!D}d60{l6GZniE6d7c1rzwod^xBfe!S6}W~(v2RuXuP^U58ZEU9=E(X&vLsL zD0!KvYZ{$Plc$Wo26RwO#@q2$g|$D3_R;RL@ZJ%-toISvj0#!_DGSj!#2_}VCSTCa zV*}DNK-q)-ZTk2W!(}YmuVnx)Ci)$K;j3JD;X6?4LvBygY|z*=HkWCsZ*0gmj&0!C z;7t7R6xVRLO|TKPTR}D$EdLI`_}jU6$ZF<+xrYq8{gB8{cVq&urZ3Qm4V=jp>gzbK zL7#2e$ZRQJ;9Ze>0GlmBwe#-!L(qC3cRuy41rATnLF-|JiF~G!gNT1%FS`fL-1;e6 zzjm4H0wrAJPXgc9``GC=00$78U=q87B&x^0WN!mO+z^uKFcRtZ=z2vr)cX2hhB^WA z8th2cM|8O38v*18Jy>mSWqFQ;JR1$FZERs51BSbi9@7xmK>Q!@u`+R^8w5P+Nzn1V zA;{5epN~Q3O(bhwi*cy&45WRT`z}sc=mU0-qEGYHJg$J-D#KP~dVtKQzi;Aead1@! zTLfo98XI~jkq@#xFNXdGIZ3(;AE@C5C~2DeD?MNd_O`mhD;#go4c1ueqU-lb)Mb+) zaqR_Z-ptYr$gY7fZ*#J7pb@NG^@*2X2$;>mPR|UCeKaew)23e+;IgO3jD?mO7WZ7h z;NalvPOnY=0m>uShc1*@9lt>x!@c)KzQDZjo#_8fwz_nhU_`zYoQ($@ z23u=Kt_J5`J_Vp{Wd;CWooNf!?vFyYzqwX(K`znpQ0dd&SgSAJ*wF20{Fr8LT{v5# zCNbSgeBo6c@&#Lgr&bH4%c-+Lg!C1pdLe1Nyc23tTOAs&c3;xU2P>n|_l6FoeDJX8 z-JrRLf0)IllKJ&s_^^S9Dxbvjocj@|T9;&*F3FAM+abvo`d;U3{#tXudwct$^g{L; z*W)L*+fVSg6uYv~0P3?Olkx^pV4}5<%X2Pug+pzSZcqmvpY$KVhX>7BG=FAb?nu2M ztsV%p9_nb;Jv)YKdW_;8ARFeLt^h+k*rD3W8~&QWS!Z944iBu}1>=_xpWPQ-w(F(*r@$WdDqgYS_aN2 zXz2|4b_^fRuKiL}fT6BCT#o@@9O4Be*$%8=HOXR{^tN6fCQ(3n2Sx=*y zV4-+BNW0x3(!fgyeVB8uM;f6h=O0_U)c7pWHp?9ba+axaDKLMxGhb+_uVO3F z4a)hB;+g`VV%MSLJzb}{rqodx?_a})x-;*o4e_jgJ~*FZej4ld&W!&HzV71~EC!g;j zl{;9XHGv@vghbDGq2&vylQx!CgDsrtb~LJ%k=hFqeUavs#gQ@*pI^;d%~Bk&jGe4@Cc&|%-E|KVJ44Iz7r6nsCLJ1eswGr zg1zQF0fiH3@(a=#md4;$I+8kFZP^Z=W(b5qaC9%sYP3mBW25ri$PVj$NVd|tFR!lH zCA|(H@9Q2JJEC>rWb+fmzq)${Tn8ebr7vNgM|f!t9_L*ZLYYmi**X^MchF1g;?(nG z^A(66;NCVhGB)tXA)P-7as|A2&Id1hf%em>9cM}mot|i3;7)54JC=IL_Hoyl=BN_r zGT?hHikn9VE0CKp%k3Q)3N}u@wfo$(`Q1> zV$TBi>zF6NDIoz$5857djcatFGZ8C&EINOge-Z}elhOPWzpWtIV-f(su!}+bzl2Y zcfM&Br!|g581=JCX+>x`Gpj z2go_^V*%XnH$Hr}7GUPXE=6<3(5S096Uu97I-eNB+qfi?)xg*LZh}|^go$4}g6bv< z$&fS2i`P$pwC4zht*q-hG(O|XstrzQz*~_#s)BsTYaovdIo75^ zW8hj}gKM4X@(6rK_io*mTeG6QBXKsKK6UE!Y3+N@nzql3naI1J*ggx{G~K#scFTsy zZh0roZaI_`hs|Z49sY*mTKy^Cf&C%fMVF0Mg$tcYc&`qUOTK~ZD~Jhf8;}6b01FFw zxl3)c!TvO#tqXjb)wN5vKl}a<_7>wV4=UeHxqIFt;}#C{5|A*!l&>oo2K3`l@TZJP z>@PB+ivZr6<|i&wb_Dk-0w?{_11@ zK`z~w4yMojKthc}tn>Q*Z6NR+VxcX_UK|GrEa^Tcmqsooy+c9yWU`8E;5YP9_UVp{ zbSp1F#+N|GT-IDZ6HGEoz_)aDmsVZK@aERRAnjCxMoU$;8t%{pw=uN7sdEj)bDViU zn9lRao$jbTiLZZkwp%KLJ-0o<*s|W5&+u-{(U8f;&NZwdywZ3nnBKS?sp(ax%mBC< z+rZrtjo&-Rxu%wCo*Z^Z-vb;eFg5VS!Tsa-!9~m$+-V@vH6YUWNMmU_7~A@ISkq^2 zEg(OH`#_K4w-e+di$^vVKz|OR|y}4Oa|BR*00hF;!HTK~Hs$am@*E-eg z@pb^UYxuWmRTZ9z&%meS+`yWe*a)=7!Ii{Lb7im+S{MAh`5KI3xHrPe2?8&nF&}WI z=gw>xA7bon-Q_|uft}w5b^S(+l{aJq-j4@+75JxzvuU+Lb-$D41;t=a0L1sCj&-XpOh)+{oxkd!(OlagJF5w#Jwvq*22$;V1~C7y ziB{{(7)Rrvl84*?(!6O#uzqvvCdr7<{qV^`G&TpepD&s7CC?E3&IZ@VPfdA34`dzuCd zEqWWpM71OocyuQng^T7c==pI+X-jDKJA$39j3_ld7UiSR?^@=!^(a07r(UdopJ$ZD zV4Fhw-mjB?B|r8vr2LM%SKMA#mt&mmiFo5lS0i>5gF69PjQyo!02}xG@gcxKg=r#R z&EDn=kaf3feBJU ztFny^NE|L8e~%Kmj|85FIjufkEyRK<-5+DXl|gYIblkFbh~G|0KxA0pY*VKa&&h|2++lfCO~RZY0xsfCWhHt&0OB)EfDq_TIS+!ionWA3dY|)u*DZ0V7QRc%>Hm9@b`_2z2ho7 z|Kc$8zpINsmkR?x-C}8=<}};gMt=&e&)Sq)-IS?kofjd$JfQ`L7o?ddfr!_g@?3E1 zVh_-LI1SqtpyFQ)yT5t)rqR5n=!w~O6LTTzg@f8A_kpIJ-8^ar@H`$vUt?+1oUXu( z*%vVCc>lC@Am_cc`0Jv3UC_77glszbDhO@aVM5HaczToB-UN; zrCYfFS+s)7(ZNl<(*e`oi(7);+%Pd*4^tTEn&U;+6Cm_86GC;Ng*CoA8fOvAu)obN zn9OJPr$A?y2SFf@!zEtiEK zwbolt#}J<-ZU8-=;eu-GR9A8{eEE?JBfY|E1nq(X zwFjm}7H5_wA*j&ebNGj_-;`3Rm%dFak3x2Dx*;^ME7x3|JzcIk2ea6}Mz|^?Z_eW`P zI5--6B*vcOzDuuPn;onIw>_T+F4vZ3ROy`YIJp8$V=h)`>@lYbcfU0T34Hei&~`VO z3l=27_Vd;-msic~s|$LNV&v@x(wBGgI+9M9I<3XkO4Q|=*cZKs&i5q2;MgsUTE7N! z(`@vP^vYoUuXPtzB0%e16_UV-6+J3eABggb`60g)WSnIhPK5VwoUh};TA)jH;4T)WBY4RMSrE>?k#7F1yoW_0~27Sk*jolqo z=A^#&1h<13n?Vrx6tMZVcb(HJvPSVF=y9Y^!YFRV6U^O!-?q-I);y3Y3bHOSkAA6UwlCj3+CN}p@;fV z!$F4nqiDa(=UokoZRnwp$kPNY>;!PUQw>>O04@3XtgmvU% zlW>p056p7!8$j*_veX=V)djHeF)U}zehIcZpGD92IBk`|3T_A}JB0$`;Nsav@JffU*UF_? zf`;=yA;~*kR$6j^C)Ye=_1>0R?mvzpsI?bW`9G6BK{7mlvN@K0wWb?0KHe^R2M~SB ztsuvt!gR2DvxSjEX&CCnq zvK*=J0U+uF9~cLEV`$`^(0a3bgN{PUHu4s5@1x10tEz+3Nlk;i*ML=32tCahw65x+ zVoz}`q%ocJuC>F6=5EmZr=|zwxKY~ypm>4zTHd1y()VJh;U!l?`A{tQ#Uu=Wp2@4Z zEsSBb-1_G{dQdz1AdG*$Pxx7IP4d+9wqN{PCVVbFe8aH^(`J^Z0(wjMBwJG--n5zn zMZDlv1ZcAU_4@My?^da#NE4-PK05{ixszC~4QzN2 zKAq)*FRDpmUoVBxOYZeE!6NEUU}Sgxm^5914-fQVD|xxAQ|#dc%=C~WbUgo}>)XgR zbxP6gkLG^HvDVe3p&x;+_93Imjt&;HKf+$$r+G4{qqZZY^|DF3oPue>n2b@6a5d*} z!oY#(e^B#(Wa$MIE+=&D4?7=X$WCu61uOh#q}x~jBma4^^yeB(8Xu%l;mO2gxq7qN zehGRx9rX32F17)7?ok4dIU8r(n6eH>dBI zkY)};^Gap=OyBU~fO2)PJk{w+*W~E|5l_HfKwigf9=q zmUYVXYMObFOEC7wuFQ1n84;Pa?}w59CJSPHoPvIjptg>D5jMcp@smS|@Umm&X!36m zKb)kl8T>pMX|=^~N$J5eGx~hr+ZGz98zMye47Bd(Mi#y=@fu8QwudU10>dNu?_g$s zl2AKUztn0o@0&~uO)Rs$U?5kyKAVEbZ8!w}K_HRlV70ju1inAVGAI|yL1jxVJ?Q1uX{Si+!oyzg;0@Ay>RJ4Fk5PlyFsq}N|^f?p`4IY8Sk2HM* zTiI)%>2Dr6p9!9e*ast5k+NzT1P?%2SZRvBgWYF9F`34nob^=79NX^#3c9hEzE|Vm=PUJ;jK|0S`NnDhzN1 zwWrH`vxmNDec2_02?u`JS{u;!9^_n5C7xaSXTZ&}-gTiRDEo0VK+#I9m-lXn^{?=Q z6IkzBl$c4^TJj4zBZqNc59ACr+@(8L!MyMsI(VFoN^=E`y9~%*!(Bz1NN9~`pzEJ$ z?B?JS&2+S`MWGQAG8m9I18?`aV013!32i8Zeut5*TSh@He-54hK!Pi$88WJlLI>+v zu(^R!e0*_pe_cRJ~5@{2X*LHS)apXhr=^rcoDeceR@*FlYYKqA*U+3CA3)@=qP zFLXhNYq{Bw^fdp{*G%kmx}t}65@}j^!`OZcgP&xSEh@}y!*77*Ypgk48Ccs$w9U4* zrW)SHSsHB{xyR63{=k-vdI^L*)r~V%K4!E{g(6p@xhFldFt)UOSU>N4bdVT% zHG00;#D!E^Hntj&y&@^8CR~K+dwm(=8qcZ*C3Uq7_)|WxZhQqtY*irail9Bb{nQuj z8cVe38It(mtM|M@i*u5Q8 zJ>c?4s|yFUIa&bzm0a35bK%{>6G8A!1QNZJjVaS)@;U%~flCZ~y1^btZwPb&HES*> zQ&*4nKE`ss5ajjD$Jp07Wvw+R-o@T|V~Au+?>v32(FnT=%IZtX>a+~fQ?C7e%0z`! z_P#wK(O(THxMIgq!f{}EHctxWH5B1Yt1cbmb3zqQglmH?l)mOn44iQp*^l7UkKC$I z?t_QkS7%YzGG5MTTL%l#B`&)EH*46~YUvew%qL~=LC@(bg*F1)X-x8I-lWea_l z09{81nAa=+!IPj`Z*rK^oF;(sIry#U;%?`-wvx9O8o}_s#!;aqD51C<7~0LmjL?Q> zINcB4*Spob=iIy;I$qbY(~{ToGt#ipn&vx-%aV$}#L&~+@uZ0g*7p~n`)RVW&?8nu2Yb_};XP)3cz0=E zA_PhFJt5`O$!n#Rw@i|o!exEv?3NGDjHaEzZy)Ekx;Z=uo)6Ug!CnP;vu|g^46b3@ zPE!eaV$+?|&7HD5tN%fW^5tOtA7p6hMam_4KG&jvH29$y{B_495?_OrW-~_Ksih@f z7&NedcF5qi^zE=}t=jY7B5*E&5$2P?%Y~MVyM936HQb!xz3vUsns>Ru+XkC)A3|M6$5Y%8WW$-$LS#)akdc6PaDRnk$cKI zaa*THen#*?;B^frsnEifsuzSe@WwVyTe=8s-CR3({($K{2lTFHtYGtohP)2MUga{v zT?|J2`q27Cb7fu+>hO%rO9r_%YOLu9{NSos+iZT;Ww}9#% zBfU3pZq*JTsnH0w`atPEmvyg?p}pX9B`cx?uwL(OE1zCcH?VHfrCaxP7rVPNtK$T6 zhTY!L6UdL#6UYNesc=!&({F(N{iGMojOU)RhNgd;5n? zqdBVS0bQ==63;DO;`I&~@w+CxRxDO%+?kN>b5Sd#UqmjbywGRgJ{a`RAfcvN*erFe!TzrUwxa+*uqe_6 z#NLE1-2GyE`2iAM+NIDM=_laPY>XR0)T0#3g!@P%VZ5vQxar~EVldL; z+V7G`$`9c2nnhoK?BVOFGV8|NQDA*LlM4=Zs+yC8aQ*@?b{K=Onb!{gpmmIYjZBp4 z@QT={_`wp+K6HX5fDNvXBp<~bmhFTWp=(0G4-v)}KRwbK2yc?|;3jy=ZBazI3&dOK z+~wY>pOt|2Ls zg0-IH7S>eRsc6ANkk6l9P^P}2HIu8y3}ZX%x_Mi086hixy`&bWJCM++kufo?FOu(8 z_AqH8#=v3J^9=O7m*W<;g%Tq?uY3>aKIz!f%R%hhvXIwG{(ZexgfwxVh;P?*;Ff2P zz(3!P&kN+A%Wp=T|Nk6fn@^@&jmrXXDKhnYDy``$<<*fZ??T;+}S<{fAs^g|77yJ1~ z@SP;9pD|#6vsaDX;Jky$`7w|@odq&FyyNvHtY_tb<1xV+=Olc8vAedk^03KcO(^+V zcL-svxE&BYok|GEg{NK1LDcs-_{tZHc-m`5=W7vfns8${xEW-f5_V2vSr&bN<9fgg zxzwn42Ish0rk4?|-&OEsyJK4Gp6hfNi1cR=_9!`=nyNrzdRB0!OROP0K^%mSS0S#_ zM~rOvYw+!j+%;CKSdf~)H$(e-?2bB@p%@Rl+RX>g>Frtj`V(+|k6RW;Oik$c7!pdj zlwBKAdCMJ1E+~jH9Ts&M(X9SAxc;Rtos!30=^LfU zIH)SXW`^hES?&7{9nxN!7Ee#6Ow&uob&D#OZ1aCNB4g3bswGp|7(^XYG46@XRXI<_ zWT~e<1s7Q7CoObmtHx)YR-SZnaLcPX#)2J(>-6Mu+|=o_hHSm>zU{>%nOT}Ot9|P9 zqy(-uS(LGUq5-HSERwiBta$@hRH_PuB8IQK(0;!UjgvoxcQ7Yu4WC`vvb54UyZyKE zgO%Or^&8{|+BDh1~^1(2|+3$}b2!o+$C#6H=$OS53q{y19G2khp$<0x;< z8;9$_zWP~fWmeBcNdS*Xw?V5fwj7<R|6>l#+0U?hg6{XL8S;sFyzCR2^DIi>%)rhH0Ym?~B*)(1Eb%6I_`nG{1p5YiZ zGMY?#43FQ?`+2VZR$cV+LTFXAe{c4V+c3d~@{vk8;kWFbdDi$E`tR-*fYlq1em)4C z<*mAqA)#rJ(4S48_0{1mtz+S*YH23ba|ovVVf1|!84g@Co6Y+8{BstKiE`X)e^7U;$y5L!(C+*I7Ie#4-Qs>YbhJ zj_bcHwFe>bja@GKkT;7(7csXuj03!EiBGSyp*tQeHj!vyfL+{_)sllFn4e$)Z+Xuh zw>AvNW6}B6W_xMoRWOY|jqXo&x^V|GP^TU~9O-gHEEimxu8kG~5%4a^- zI0%h*Jx%zG`~#eBpq2<^T}W2e6o^sL`V(y@Y4R%(HVvI$?ag>mmUjv^ zKwp&*S~`9IgU5nCkR$!e*umY4a^9Y3yH~4;2A3GleQTM}ie=W#2;A^PIG7r>eZ`fwnJvCp>(3?_gkHdsjntz}B?cPziaBaF3$X zV-Q%~h4vNQMdW#A)#B90xWPdcsNohoINlY%c-DP{E{q8uMTlfmGD)1zm_6PP;GNv*yQI<6rnz487$ybFA@9XsVY}h4+Nn+>Qrb3(9oq=34poFm0yk=E<|(-i&=W zl*Xv3#tq|abtS4K=Evq*>YG$dwgGoGzWLFlj7xJI?Hvu+ZB393%Z)w_HaDhNQ=g+F zM(>3=z2iOSSbuw>;~(6`mpA!?0O2UOkH>s=DPNpn*R})nyQlx4Q%@|LI-nsB&X8CIu-n`*6_%;L61qFuT~GL^ftHzWb}MVu`((CR*oMXx z952;coWme-1@O|ZlOJUrX`af#+29|e+7{dAQy^>e zP9k9w(-JC&Saea~TYoDHALdGk~VmScO4u5!>!E3*tKL5`j(98>K$0bF#9~c z+ZZfV7eFTGx?|C;zVJSZ7Erp$oI@_SG^Kl&zqq^$x!}xT2IzX(F~kU&j86A+aiB~V zFl{t14~ZPw2|t``rFWk&}ohD)Kf4}m1zHVC5W`GCpsP8rs9;U-Xb^sqc} zrWbgK@?*jHyKWq5Enjv}YSn#wjtX?ChP8ydgWxrg9{BDy#{eFZ;#qMNP_Q`>o#7#` zgfQD(m>m@v%_QG~Dh_sm>H7*M%$2}wqvJ<&P8iuA10^F}nrUu=eftUoSw%*b4K{oq zfGxl3wyeoCOmh=H-rNUPB@kH;V%!=Zck!%m-P*Z_dk?En4MFpPZm!tb(Zofgycgzz zw{7XJH<_t%2Bf(RDTxE46`-UO%+j+}V}sCTJ*f9P+Hv4>$KAluF{D5+%yWEK=%Iy- zRih?dMe?nTFYudc8$5M0yxXK|KGY>z&Hyr&SA{pY!F|w#AoFNbG%h4e!`Rv7PXO2L zE-tMI2-=u5-Q9nTprB{`WHURUd7#@wnqL&yD`;1+9#?-JsT|h_ta<+|#uP$>XqubKHvb{Y{v#5#A40bclW2)D-M}u8f|Kb_>?moWry5wZPc1 zr1Es(M7{Tc${#R`z;g`Lrl;5o$AgS+*w5Y}NOscd`B#?EnUAiJ!p3 z3&sQDX%?N90)E78ChdR~Hv&epk*h_GnRhntfl_+1UW2>Fb3y+mF8RFP6g0Wt2gzJQ zlFRF6thEk7>*M|@EQK0(gv$2vNhTYl#w`Ph>`eW3yzyf_{|KV?^Pb^USsu%y>t+3G zt-oYnUV<-AF{GrY-qyAegnTLK62py0+O$BC1iB9VWzVoG_bBQ ztJyOg9^DT8?dH?GhJ-vneS(kwvyanNtg0};$LSdTVW&+YfO{(p0=_=?n~Mu}^7UAilH2tgV7Cqeq@$^i4e3`!)5 zF)GzFoayL5o(Ji5a}0g9vsN9P1L{WdO+Iq)OindMZ6{5YOM)Ao--4oUp@{-@!5C{> zLeCGIL(}(b*kz6b$7}ewn)${Hq#Gg4yPf9R^a&BuWFv^KW5U={wBXFGj-T|ty3xE9 zzTC&58Qjv>v+wIXD!>t++GsF!WiTxt>13e>We{+!p}n)4Pcx=S70ZIQX>R0dp@Efu z0sL-g{imm598zg5%2V7)W8=NPA=u;9r)zgJnJ=0|f~f63K;;dRUB^WTlTZQe-;op+ zdk5tR$Y5#zLB~NTG;iwB48uw8hstla*#I8`jydO%R}~+CzfFj?OmIi+GF7bGFCHUf z*Si(Sx|mwav9OK0CYrzV&Bq*KMxyu#416|0IoBz>Yb8KqnZl-%5bXfJn-AzO|`yAE2<2w)f9Q&<7q{Y2g=-Oo13>l>|&)T)ofvF~~sfV-1fOP9!` zoIDuoYny1}YH~R~i@6O>Y8fXTjM0>PB(QdjO;a6}fJ~@sW8|A$OxS! zabNKCz6mooA=tdz3#k>YEwiW2!o7@m$l!fDN+|24jP$VUc&Ao_Z#||pVReV7$Gh{w z9pIq(72xy%pG9yBA*k5jg12b84nw8DH0uHh zxJK3X81{DR82sRJGEeJz-1ZyGB&fnX69TC-hV$cDn(u<+l7k~~%zr|8E0CG%i*&(F zgX7TgLDuo2#9*U)MKq5fdkxb}?}E7=K)vhRE+nvD@$o=vPE#^j&DY}x4~6E=OPp4S z^gL!P-IpS%_6Kl>(g2wCX!!Z){UnFAo^YEkm%*3Yd0QqIY{=gZsqN^djMYeUkQnhA z;Mc_oOB3f!WM|>yrCrt4e52+FKqwz{946gAiNf^PZwCiAV}=$YZCT{s<}LO&px6c1 zaTIPOtOdcXMl;H2JSRqCyAB?3d52nB*WDy@EYQ^M9=xd~SiHOilrHUfsHqQ6x;4(& z+UE_d5jsbRPosmMDNac*^cvyE;`=k*c(wX;fYx4M?D(KP6XfuANBbm~ZyF$mdF&rT zb^o|$Nw<>;7yF`lAG2cIzs<6xEek7dAhGL>L0*aI6Uu+sgj+sVG~P7n`+kR<9<>F2 zb{HUep1T)3qs7aw{?OSB*BK5a8R}m_Y0o;}S=|LUjn+b_D+Fjr%d8t=SD@>;KCnJ; z!f06s&7Zo)I+f!&0NE}Ja++j0eMbB2{bp!3V*f?ih$GFhEJm3UV5#sUXC*P`u8 z_t0s8V6<)r_$=q>)GRRK^cb|B;ONw<89aY41E=s^%rwhboTk-8oCO2ecc727TTN7T1qZ&uB`-HS24H)P`W zV6ek}B#^hid!&w1UBUXkC-C(PVFU#h1L@2FOg^D@yfZ~C?uyn&Li7e%Pb1L#Qsnho z8ra<)4(wrAj;dq31t<67$!66zh0r=9QMXsUgw9u?BnQ8{o zDYQmmNvDn3oSw1d_O2&m$9RVcue*A;JU$m3|{hJzxol}_Hg&B z9gj1a(Z2+`dpo$pdSKUsu6{lxr0I3+8n4F3myjy4-^sgiYoU3fbDYC|1G@}ev9C;A zrzhk_*wtYBNOx7iDrpUf@+zlmTun)XfY2 zRtdk)QPOd8Z^Si2i!JUOHCN71@H|woz%deVT#vTxSUpuirKQ`Up0nMi%9(C9=#~KA zUDOJ21|ebt+OKz_a2;JY0*$UspuJ0}nN59dv~Axp1$3&saF23TP8K-B{QTj|Xrww4xf^{5Yyt$99L84pwL zMo37HJ&fr?0ECNuHYo%LUwXmyTc5~+O`s{TntF;GJ7eTM3|m9KvEvLq*ie4Edyk57 zz4tD*?=fYTzCkf#$&O8;?OYA%>&-m7-VQaaLDOeYDWxx@HJOl$;}Z_S|G~F&f;kT9 zkUYidYdL$kD4RyJQxvfD0LOXQb_f`POp{LVixT847Vf!5Rf#h^I>E^H;NY+&F< zd=wC9Q`2f@IF$7!P`bD>&c6bA-CZSm{$y?Xvhi^5KTWQs;a@^?^_Gi@GHLxtE6M~6 zR809F6B_%Bf1$1k-h0P|MfMxtVSw*kbRF)Lg?j{kaU9L6l{~BVg;IZJ(dHTgTbT~= zeNVE@@EPinXq-!kz#Zt|q(~##o5*Qar`1JGbeqGc-sED%4dw9V>&>B;yxS=%*OA<{ zPV5N66V%R3zYLYFXY;k5Lj+NmR%AckyVgY}_1zs3`_&J7Na2`#+AdSC|kGEjL z!m1w+fv|-9JnD0^^H~Uy9vFx;w0?bwd5YCzJp z7T8g69NW0R&IWmQ!vWPshH9G3#4!9AK;4CKgkxBisD@W{Y+_-`ua+er$Xp|vl%ucf z!S&(PdwTPcXB*}GW}C*e9AKC@Q-cA%CnV~bs^M^VKJ~Wa(SsN3CFbnFK|BEn$Wp54#c-- zItTdxPWqnfldjK>SJ&z5ox%V8&Ov=cp<3T<{r|q4G8g>Z%i3&X2f7Wkxsh2bj;EV~ zmEt{M<}&g$IF=_b)d$>6wYfAG=(-Dl`?P7JBWZwmX$P}A`nS0FK#f{{2;0KMzF=5m=fo}JIf zKJay8_3V1c(Ej^kDKvi3;m%e6Nih7oGu%>H z9bTQE1)e7R$hwPf1OL+vM;U2tc-(IXE9Y_0K;oiYg3RSt(VlQe1B~q^tNcVrTZAw{$Vc7D>bb?hz|!5dXPjF+!%Wj z;91${Bu!Lc`D(4Glc@7_mzY4KX{!sIXFb#n0+$#(|KjbrCbq7*Xne+8U-@#UNo!XS zK7z%qcNjSAxC`Q5+q>3Kjyu<_rIR>#z$r~|Jh%)-U(k`Q1FNlyC76kQ*WSrAalN%Y$js+;gtiG;hZA8bPn8 zxMRe#VL`B{+)Z$;)|B6xx39m0PL6XYrB@xWB;(rH3N_f~`3M9bLP- zC5{O>dei#I2azCK!je0`LzJ7jwWU=UNL~+s>;V*vVk_@9Wy=co`imOBmD=g@HM1p@1K(6MYbzzCH?)Uuf#?cy-kJo(+xOLw)D<@c@eu zh9Hq*MrB%IaArx%q$xb{uSdlnnZ^H#QYl76t|?r=j{p@<8Wq)5dEWHh8APmL0_M=| z3P7sDWLM75Hrmes+ciF-$&PXNHe@%C`O_QY#@~97evJn>|D$x@+feUtpAgeCDO}jF z9_~aBr;$^GOVm^pYhNBTp6IaFLpGy-easKP7~43N(HW20=VI(-+!m|bf~tf^LTDS4 zEuzK*&&8KQa+f>cku?_Xgs%gW`Q4{-R3zlDXW{Gp%pjU-8^`iqgfexKW4<~_aM)mp zZhajKEkIew*zikGlt$1s5E2|poD7Vd-&rWZ z4N!e)c0nLNczI6!AS3G z%y&P4qhTDt1`FVR=;D0yu88WxAZ7pr@Dt&%E!>r#2KnvgAjV-O&Xzgc(1X?=ocwh1 zX6+q?;f16Z-swINqPx_WnW%CSY|X3<8|dLaxO|uz=wcEwLaox8V&z#*pWqQ;;aj$7{#W7tmD7@dA zm=eC|t8>CopS5v}!9mG$px}2$Y))SpGV)FU+Otj`FcYwTKYD(ezO79wXVLfV_gU#aV-W>u<&|Fa^?!<>P*%_4BpQ$DudvCGx+Wt36?k6J^*t=0-?N+tM zV$}#HcB)38<%YjZ-PHSzoOBbwq_`I}zo!$C;yqY3ehoTSB`23Y!eXCa3sdZE0gtBX zGUl#F=U+GvK_+?vOZnI5d)-zJf|dOs^Zi4@(i8`i`Y#~t6^gl=M&}AVeKexI!VR@t z5X8Pd0K@lk|CAn#ca8|J1Zu~454p5(fc5Y!dN|y)-qgYlwl~!N715@*Vt7S45drmW zTbGaXb_aIjMcBQ0@js#*jKyrolpxC)1qyB=aFv&aK~Pi;qebbDMVs5@oK^No&p=8a zlTXU=4pBSwx2&6dM=@xVz|p|{Pwu93yh(cufU&j9F5O_=;=H+~B-W$>9 zS5I^g71r}z8df~R?L$$>NLT{vnLmx_MQbx&RGfqkdVB9E(Z>PaX<+JQ$7xs=ZZZhF z!sfDa@`#CRTcGz5^SNn-i7^D8HYk37S3Hg-f-JXRV1C#8xJ^7qR$|yYe3Hx7Vow2C zlcwH*5M`C)qJ}dn-^8$I8=kXmSb}h~mc@9X(Y7g-XjbZa!tk;MXhd@ZRu-7B&0cYvB7 zq3_3PUb2a71js(pQ3QX%q2w9>(LVGoPLWt7KX&a=u~YAT;>pGI5WV~=`M1`a8hvlvr^0F+K$-vqbKE+^3$uWthf^Wn$=#BupuzN6mr5_db z2ZM`_(DhVi9`}q2ESzh$9@@teW$7`tasL9izoX2U1{_Ea!dY}<7VBx0fx%-;C_8GQ zhsJ~>TnHM8bCjSDFEj^CbUrQn3|zE1;87HeG5a!5`7CQYU1+dZEkf7x4J#eyW~iU5VC<|I1&Ws-587$9KL^bh2h)z;ZRAD5nh^O_ zL>!93lD39}v=z-rbO#rb306<@FhYgHp|wyQ@U90uhY)Y!KF*&Qd|MK0`cRIsejAYX zwSg4nI~Wc6O77Uj97I@L=Sy_I(6ow3T%AA=M$U$txSte<^GlZQFlg>%16BF`DO1~q zU=4Sg7EPSFs$kFa2{@3hfnoyxbTGvBf%6vRI_?eDn#p(R`T(9nZ-OWwAV`tkdr=^S7LovxfCwmt-a{`ISUS=KK|rbsg3_cT z(nRUi0w{=zs93RKLlo~h|IIryyV*B$?tLEl=F9$e`pnMO*UZdE)Uk7$HRb8G)2T2G zjR`y!XIH8wcG8UUjnQx0HEUrmA9_&SM|Jwi-p<#RcFv>6bK39CsJNe@oxAIuajBkq zkl6$HXK8aA_euB?ol%c3(-Ll>(aQ8NgL%U-AC;}Ak@+^BLH8LAy7}In&5H~CwdvD3 z^W4Ab=L^l*mLKknGotsL*&m|Vzt>$TAVLd9XDnm1%%6!C+?f+?0qQ@t5vCv=s2H z>4sD064lX;)-dLZ@+!?LPv}ZXaEG-Tx4+Zo=ez^QXo}oaEtQNZ-LvpINF9HGQK8M7 zn+vN5+Iq(5wk?|b&Y0q;)@rK*LfWG|YQ&tN9`?1W6z_WQDXNZNj9HX#tEnBQQi1lk zGbG+wXwxc&euko1vzX)>#z_d@fbO8%6Y~L0SLO|@?FAd0A1-PQ2FP1)eACZ&B(Ob=I(^G1tGz z)WhQR9A78jNmQSI>-u(oZ&CGyk+ik6KEAeYX*R`58qh;^%yc8hJcRu~ zyVCFd>OSVV2zrp3d92w(<6C(ysr*Jg=|R=cxEFA9mVE=!RTo8`nq|TJwP2TSsw{KKQzJb zRIO4IWUP7rsUB^bpo{E%i=_b7hht=@rCHUtGH0q@JpE0WA^bi|?`}iXN1+?jWuxo3 z4YNZ}ZuEekr|A4Ox*htG65Sj$s+Av1E^d^ZzFBXUd^?qVqB*|Zr7$&&8ifU^?%vn^ zoL=}eBk03p)H4LlxqTlEz~^<=V$3?oOF7GCYWp$3>48nVl;iRl$2IGkibDJhkaf z-Jrfce8g5a4wNwo4j=sSzzchsVU9}idgzMJ+dVZ_}s$-MQ+pO<+|H3fYwC*ASr235;ns>b!z zGnK$>s`I`2u)>$)DH5~GKSWVf(0zxm*n2;n@(NX77bA~u`OVJxGv)I~W9{Vm(Wgl? zERLEv;0&0{9X%%-iIlhEM&8V>x}9=Wz}V)Q&eqe$ z-&LE?^lLNSB+7W*w&nA_$P?}G9pOAZ{DiP98NnoQp3o7IoB*YKXv}C zv3t8_X3=}n-hb+FRB!H>7~}ax zs-0A^$Bex3O)t+?uvp68SLQfw&sSwt*&nBIyjGPx^fe1r^$$=6hw0pVFN|KNjpdBK z#FvuPp8Kd#o2nzK`^coZ7Wk0H|JO#w+nJBWb*D_vGV2AG6^+f)=aey_ z;cHQa4}k&nK&$-=vfe8-2(9UWMA+gz9Rl-nD6xd3!#R zinLpAr0e}=uc<{_KlBvXoG9BZ#p#Nt&Y&w1n_+I_G&Y`nis5lx%x>$Lf+B%a3( zwp0Akx}}=)azi!pVrr}YY9oDu#vF|Q(Z(-~gx&K@^Ki`ffby!{6FpDRy+V7JHf9t4 z1gd8WUP(JYrwiVRuLY}&m8IS{S&xXMxRz#p|3^b2hwddEljts`YN;vI3pT3xm%blk zMB9{}5=yE<7s|W!7&5%~z?43rPvjPHPe191rxT^sg?Y%@O^KG$&FFcjbp`c~;kxs* zZs}c8|48eA-uhr=o(bHdBh@9n9`amDN~Ks=>0;7Lp?I=im6U%XD$!HLzSpykQ5A1g z?UUqvVw69%)y$j@=>{Dy8qM5Yq%zOb^SP(*l%Z``^~^&rXi%qD4LF*YHmViqbFSV` zpU$I3N>Q6}ZG_V{JJ%nSzb3|5PvD=QQf1#mTk{%iMekmjjWv@p*HD!_v7=e2cd2LY z)(3a@hZ|MK`IB+$jZ-r-R{jXfC%Ve;TTE)lVHE8=JrHBPH#c%oQ_Rpk1SR&|Pt8n? z{imuCesY_yva8rl*4kydKEwAtn$B)R;w-aQ7pl`);vf_H#hcm*U4(u%!x$Ta`n&?0}0ninwnWBhCN zj6fePHmaL{46%=@E7ilzTO9w;{sr{-rq3Uk7btm%^wK?s*7xnb4>w<--q_re0^Wi! z*E5$Wg#>d9naA3rwDFMc=}kR{4V<6ru1<;b`1CCHDpCD3)cwW%Vy)+n?7LJ4w~R)o zr*e!M8kIR`MC&HQholVak@jBL&vaRb{zun8bbHd1S)8(YU|LSyaD{5Mq?lOq%0W#k z)nKz$Jda~UQ>E@Src8R`jOH9QtMCgu7j=uar{88Uhfp$==d_*<6U{r=yg2{CsA_&d z)!erarTlSCePs+ei-JSWt0yFzfsbXsC&7Pm8*+jcOrjJ31 z^aTQAoZO)4dcLaC_VnRE%DWn3<)}`Vsyd}lO`CnJ8Wrp+UE9i zz9rJSLn3We&tpYWd#^Qy89mx&uAWL#+Ry1S(X{Hh$d{XnJX3FO+R1ZgDhqARt-Gju zMZ?>RU#5B)Xtqn*w}{OS7fC(6xN)#)X->RLsB}G4<*0$~87hBKAre*fnm@~Om7>mR z%zS*K!KnEcY35s|rwIP(WbZ4;1*zd08T-?A&xOnnD1wE$e&~b-kB6$Z$wxKxss4r90rSt+I^dUdhYxou2C}XU}d2S3pO>uv0B+TDNHLJBFZ6BtGqUY#- zou>S?#=iK8IaQ>RwCCGqhl-`|B$;|HiylC)p%Re9i_vMXeCIM1iG z`6pcN(W5c0x%WGR3uuC?WwaTc)|q4ZI7OXkB+XytGjeu}BJW{TocCk(pHjiw8tu&& z5IwW&32K<}dVXu>c_;5K+WV$H+~Iz|D)I#E8-;*-j%8#bfr z?qm*dyoKt$je4EN@NarzPkV6ET#fScB{3@R?$t1J?!G`d{83j;Y)jAMA^oW2ON$GGvZ`sYH$#1bS);#wS z^HZK$>s@I@>>0#|Y2ORFS?Nl!k*5K)@lRb{&CTm6!>BIy=(5u1vSK}7H*QCbaj!AF zT6oUJx6%;kVl)-j$Yx9ZOf6N@s1El-psFWtq6(R&Vo#1S`w;*3L2g}QemSI;G5V%c zp$ZwZF@OHeJVn?@8K0;Nh93nsb5@YHFHv1Mwz>O_P~8cszIUl(R1!X@qBbT_v1b|+ zgXia;vrxXz>3nzO&#svhT3g!rXWfB#QZZK-Q>X)_=o)*t1$`62DE4KFy_+6c^yyR2 zWrRzV?SJ*uKu?^RYs@h;EIX=!9q(P>e@{JOrEbek)D?_A#P9Ncqjse!$G;4Hnx=$3 zX0iE0S>|!34wd^6U2b|_*@&Lsdd#GY<$mf~b(8T_s+RiU0Qy>@dcG+uO?FYL2PGxN zo72=HN^+MTQEj}>d(@y``Id1K=6fA{F4go8 zDqA#KJ%efjmG*Ac_vj@~v!>V4t`qd~D(y2cD&c>qo^$Jw&XY5rjF|HmUn6a-qsMg& z&#*m5N!+cA=6=~rrNAF^cud!J4SJ|cRd+F}lz2Vr=s{s~qPaq2Dpogf=&W3gn~$j6 zSB;`2^YgYU-A8Fe=hJc12OYg1mtRA%|7MIj`k_nnN>?gH{G``n%R<{>jD=^E|lcLV1wk9R>2Pah2%c+xPS2IPT_s5u5P??fdnL6Q%5o*tG zsX$j%w0M-zh<7w4T3VGS^gUV6LYlug7-!BEF`f&&hq7h5o&F`x;iJG(OIAj{G^5YJpyc@N<{As$lei^3=dl zY9!+a%~ie^QQSR@Dx*u?X40S1t{05hy}wH|fVN)KJ2&%O+fAX2eW7|DenroG8G(Oj z^ff(}=)q3Ulbxk$`q-`~sCJ&$1>$Ht6j0*kNOthde~YMY{*A$tRs3*p4I|-bN_dD-EA&v5xhVLa zrl6C0KIaP|o)iBT)Y_el5_`^xuT!47>aIZJ)_b1vA?-X?mk7UDZ7#I((Ec~fah>2< zhw)SJYjlzMT|J{Y`BU9xjIH#7nmMPuL{;*W?rQu!KJ&qs{?yebtKq@V*L&X3;Lkja zQ~fxWJ|k}oE&fsIrFvu9@6D-xSdBKH@-%g;IP-dBOKRutMmMQZ-Ds}9^w3bAs_sh& z^y_c*K;PKV1AYHg3HUQzS=H;1m{y)w{kYG)q^p2mS~lvhC>61ossUUZG#5bIXpZQp zCvAQDt;W-P)I5`o2EcU-bHMR^ubD>r^h}&N&19hrjMft%uFHD*-mjGZL}MP}&!nhY zzDj#9SA8d$UNSH?)}X9iHul6FH)H!y>X_S&j_Lc-Qylfn8EWpO*MdCj+2YiG7mRXq zw>B%5zqVJ(Gb-qYol)^CDDjfM?Pka3tFrZVy|ixWsg&(hDa}>h@Zf{Fq_{+#@0h9< zdbQd-J${s`rMNl8@k3QcwQQ%7J?v|9&$8fsu2+3X<7;%D3zQF2i#OBT>F0dS20uX2 zZ}1EZ`WlgWS)?q17(E%qn6HiOrS?9lC!(Ydp4stnn!IM8Nu9>xqv6RSA` zuAt4o>pUl$+lEki@~GORcSt=ysH+i> zDPCQwdgixAe>J*RQd9SWl*;@d0@sZ$&#wWijeV(-yBcRpb!Zzcr}6dFqI4XXQ)t-m zeoyq$pKRZuXN6ezl|mI)H7dyoJpdA#nai$j)K?1Y>8^SEIM1_GuX8C>V^c>>|N6i* z>WnQF!BsmNxT+qwL*>*xIVst^PBfMFJ*}#+V~jZ?b*H2gbkp&-dR38*QuVCYEtlBQ zJbssrgWU;kAu>|cYNsJ zJ3jp%>2YyA{_vX!sy=R0k1nk?@}({F^3-nHIzm?_-Dxq`q5Rd3yn3Q@*J~=~SLo1G zQr9%TSEOoeIqllO*foJ4Q&hX2rCpb(OnF|OtV&gV#W*B&>fpII)P*t}rCTY%{bZI( zmapF|)!mDp7V=y}tVZdc*A?E$9QysKzE>nseUIspI*fnhc5W!aJ9^Hf zQ>Y*Pq6^?2u~h~KQvUzZW5@e4QCo=e&5 zXbL$|i5~cOfAxXBUP^;vj?qs3>z@3>t(o=q*yPUUoy{dw#U*rRXtD2kIBOYAl*f&! zuw65AxHhAm-}4sL_sdHORMyvx(s-``RG>y0sIx|w&OPVpk(BeAdLDQ0_ZnUQ7!8bW zM)IB~|9Ht%MDOhVI3qtoTTM4VwIMz0rdpVMR$T_frQzB#Yjp0A!?(e>e-K}J$-G|}^mdlAp<)90x+vl(&I%}~!3 zEuJCu+)7WInX9-a)Qd)&i$veAr~FD~zG>7oCRmm65!B2l^`!3pSex3~f@@oEP4HY> zSWmgGVe}AwXx`J|H&V_Pm^n-IEMD)(o~hA2>EDS-e@%`SE+uL6hqro)7PW=@2w|HObdLS);vACMfEsJ zPv)`Sy9_yLYhR;*eZS@R1tpM2A4HOpo12gKK0}R=-+Q6Ob1VH->X}1~q`e;#;$Q80 z&eI6=TTSMgIye1T!J39N+wyGikKPyordXhvzhT^ka;p!gQk~{bmr*{xfQ>$uJX?hfwY^_1{Qrnm``Rbtzu>Q8Zb~r^_H_JKW{JP0 z26-V}m3!K(3f1}Zx_9%)P_b8_`p%*frc)6tl+89>O5c$9@{yLkMzrtMhkh8i*RYr# zJ$enNw=`*KvoUm@v`x4{-u_h^pQMfFjDE^ft*0-xrO}nu zJSrMHFQX&kw?=!XJ4TJ8=1$RNqE)2l{?}zH)FRy%`OAYw?EK}AKXhl{SL#$x8%oWW ztfy#tQHZ}pqc)$V%_mj!B_%X7ub@6oLvxyuspj~-K(%iaZJwu3`jXnkn=PD+viys& za|_SgCj)8UVY(sG?!>6d&Pw(5joSQh3-9^j)3o(|ebn;&*dTvNy}r>3v~cyDYo4Kf z?^G?()bq=VYpF6OnPa-W=b6vjbX0lEsAhbOR@FvB+WEF|V4;s>8TCAty7W+EEB`K_ zv6(*>_lMEB+Itq%L#bzd>*<%~R5p$}<_euHTv#)rzK8NPK#eqPrS%a_qN=hZC~x~z z=c3Ra1&?6EDpm*}ff>}8DDYv6Ml7IxUOtGF{+ZyMlCg057g$~Y3F__ z^AMv(c=hCYik}}TIiP!PoOzH>rgS^1ZS-h{*{i>&j@ia+WqNqdGj$%1j*2LqTDs4$ z)R9BF4Ne)oAHr*;v@IQNA8P{+#er#AU^V~_{f9tk#EOGz7rpLC_eIVeB_b% z$fNO*$KoST#7CZtk31D0c{)DwOnl_o_{ewTBg>>ll}(K*ml{<*HL5~tRK?V&N~uwm zQ=_V+MpaFXs+Jm6JvFLEYE;eCs9LE}wNs<&q(;?EjjER#RX;VVL26XP)TjqiqaI9+ zYLpt)I5nzCYE(>WRMS+d^{;g4o0-?)_*V!YHtL+N8GGKWd!M$S(fiVmpP5}ejq(yp#V)7WHBPdh?g>3e;&h)v+%>N5vPZ#rfq=%G!YHKVfz)tx@4f!*6Y zt%&oy0L(Y)KQ{87_5%`X_;$>cDK3L^Km9=jKKJ_>=YEc7JoESSRcyDY17^}S+1!00 zNNpa^eODKikKSfM8&E;ZyPNr}BF6JNe^uI;UDpD>G-y=A3aW-{dgkPJ0*$Rt($+Wh zvZsBFxp+;afw5W-_10$N7N^EJszwwY2h16$E0y+?In}!tUsQ2h()I~@q|zcpoINH+`_-!|5; zsRaLk#b}*(x`t*{XD-V66(eap2xy)^cA?0dsn+O7KdojaeUWDF2D;?#Gjl56JE+_# zI^`JiS@u6@Td(Bg#H5-vs>Rl+)u|izlQ@3V>%Y*NoKHXJ7#*IzU*TOLW~Vsn>%KsJ z5Nlv_z@DMi2AfK)DF_tD7_d+;*$?mhfmXtbFVRysu}0!rKp0|7|Rzt-lz5~LD9B1*G-;f z(`gzGf9e6uS5`d-r(qQL6!W5ld*6tvPR&>Rx#kl_snS;XDg(`_Mj~~$br*zcZ~nQ~ zzjfD1NXF4q?L3mI{7a*3^nj~5n!8cqni_?}wIQ`Le==p1ku&;^qIqV)Cv?vmahum0 za?rLoqraPrflsNozpAGf{LZUNvlOLyL|3TybNVqw3>K7_M;z6Rv7#&eOU#l!d)!0*Sj%jPodN*nO{H2yn^i%KV$eB$W zJL+E9l$R%}ux(oEM)=X-{OFAZE*ZRdFybs{y* z>pD{Y#E21X1&a20UC!3#X@6d-gKb8eC${(W&?-DQjF$0Cy3bNE@6wA9&lmJwqj+!Y zuASU0*7K78aH7 zIp|nQc)C6W(zoZ@n^RykjjZ~ry!<=oYIN{--8ZSyrhT_bZH=W&eXsii{h}cqK~$D| zQ==ErlV^+S)RlJ9RRr9AELsBuo~4ngnr7}@PkU80-O zdFxYlLI55Fp{Qgr{?T4g;M@Wchp$V6O#R@G79VC8b6z< z>f&|o;d=12^Zt(5c`EQwy(ixrq|;FIfXHtUKC8=vFQ%x-OH+x~8$A`n$2{`zJMu?V zk#V6y?c9Z$Keth0d^cQmbAEs$O1B~XFrB$#UPQg>lFC&__cJ9bW_~VwmL7Q>&8uG} zXrig8hffUuW`Y_%)u}TNG_pj$kmH#RzNSpI(*ps&w-6c#{MoXXb;t5OR8*HLVwW-E z%>`!yHPJLrBe*Zsn9Wd>QeJLM=LuNys@f_AY)u!)uXRd{jT=0iuZcHsuZic3_$uAs=rrC~rNp-Kd@J`jJvVUTk!Jmd zrwkv2i|dQk#dV`{Xsxc=vK3X%YevWSUg#)IJwMKvBwBi&wK_ywr>kC)?73NYFZGdp zx*xPKXVHRGWp5ez!JsfFkq(rpYep&QbkF;SWeWA}J9O`*>qfJc~S# zviz>@MV_Cv>P3C%W4)ib>KQ`2ozm&iQ+DP(=@gptHtRWno`>_?NUum!&-30<+$zp< z=*~+iXVKBqU^I_rOQ}4|bTub>mR!}Tp0BH2>2Xx=^?`|$wOqRIgo4^I z#{C^s)jh^i+KY94(Y-vnd7`#frhMPl-GkRTYRHVGc#o)D^N-n>{hdz{Ya8eDz6VH7 zP_{oe234odl&p%HAB_7?9VQaZalC-)x~uMX9c$7J8#VoOr+!yj)m6ttPtVv*C2gW> z3U3a09;Z7`1xhsbZtr>B;wtSvPjAH&Z$?d(p#lxj3kUD3$lp`Um-OUAkC5<*mARhp zKsnE;mqPRgs(I0QDpls&>Bf^;-49a=@0mT6&qmF)WdcncyDRgJlL7sP^h_C%(yd2# zOd$E(8z^)fQf=wJWT`qq6G}ac+DNbRm^bH^(mC%#~{><}GGNjpZp?m5VItMRVD;9}H6*hw=MyQSi$$MMFso!CWp1)jC7AP6 z*8ig_nQm_7Pt2;V{4JB^suRVwFi(y7P0!7G%4+JlPE?V)b{;)$6X~lsMu}I^O!>Au zm+{v+66xoYVp=v&Y98C6eO&S*F-b{rNy)UpQs3{GL$U4FbwHQrJ@Y^tD*r$|HS&)f zd)Es5lS6yW&P+e+W0bNk)xj9uvc<_7iE-g*e*s)J|e&na)U^+0eRurmvLg6io} zRfp8!d>_E#^Q^AojGqlr1>>)-?b2fv-&8d=*NDtivvWj`)RBWnbQ_X7yx)j^qk2V5jmngX z9{+U~(nG-KOYw8S@kX`NORvVXb%j3dmnU&dy*k}eMvZZQ0rTt7$<KtTHlpj%o*(6?Ph)qBUWK^7wXG_o1r=zrp4j;}Rm>jvA4R=a=eDKiVflxskMvZT zYTBN^Ent-8CUvlDstdJ9XzRJZ!#}i|O|?=YZuqNQEvH;XsjeO8`#J#aSzb>@Y0vkV zv(bLa_18u#c|N<-ow9XB#Z8Mv|K!6L_+K=7H{Dq>nz#s6=T~}6dVX5=aZ2~9p0=>W zHf!_Ih)e@YM~v<NCU)@Zh=T6P_0yq!pQy3d=o(E-GS^}yDCy$nQQmyIVmo!f>}H+0 z-&8RA;0mg;%tl+b@IIC7&~#AUoPg=Fif0DiKvlX=^-}t#gXim@?dhkcm#9}I+~;Xm zhNiFu!5ipyi@A>Qe{JI|b+6m{Wnx;QsFQ(ARE?EXUg$f0apvNY@6{btqmAFeFc*Lw z>6dlq<2dZTHa0z!%NIgFEbQifUFh$#!~FeprIGYfL(Lj|+BTAUZ_bGQ4bl$#BgPKl zmq@0DqA1ph&h!SQ4zE*t%osQJ&7n<&!f$#o?OS^I_1`(69j4bFRHxnmiltlkVcmN6 z8$N^*+8Ww8C8LewLhlZ_S=b%gX>^#sU%|_DJo|R!n~?+N{V zahSiibMxia_)8(Z3-#5Vewe^%7y8>@G5pFC7cZ?6w}-a0#CKkY_Zrb_aL>@j(V>n1 z)#V!QH)Ob5wzoom|0~Sjx4KF5Ba3Z9c777x{^7LUb=%vaEpx(diA`&xzSI>cuDPK- znj*8h6eB_#W*NPSzmnK(NJ_t9wCAA^c*X{9g`##dc_g&s?_vI4*0+F2tJnUa{kEwm zHQl;98QQQR+=k7nm+^anl=%-ryQ~kpWt`gLX8U|-mto;H{D$(lU500G46&g~rxjyO zD4z9cEumWP!_bzsVYkHTEospm3+=S519zx8^{S-}*ejt8bHi=;jxHUy9nx!9%HW<< zC8t7Hl)nxB^KpJ7%AGu@6h1)QyX=tFj4SFrK$Ix&a8rP&M zbrZ)I1?GgRsC>8$H{8VCKEQVXP*cm(N-!#AI2HNHP%M#Yf7VqvKD6msT^qf|@HqV@ zl-XHfx9oj5G-12RZwl?wyEZ1^l%73@@gwzvQhV|ccr~>77k2`~r2S;*j|Dr0BGXgC zhS0`oIuHGN@^t!LXv_GpTh^rYTsLoN-&v*ip}AL8ufvBVE_=?1*=e1}b<08#uXM}M zW5~#EX+!vIXwx{IW?FZ<7}~VX-OGI$*geFZ4sBZSK- znjYGcD{Tw42+io|^OHi`8mV5FmWO?zbY5}u&|ByHz0js@X%Ti$88)n6uVLA^g`u z6ddUW@1Y=_Ir3i%Q*g8!EJDFCZm=i?$GX9LDM-g7w#6v;q#G~XXnQpKu1!uXzY80I92CGwWjvK5&!DroIO$yF+gS99)&kfe5 z;B#)U4h84C!MYS&;0Eha@Od{_pMneBU;_#+a)S*ixY!LoK*1N>;DZ!g;szU0aH$(? zOu=Ptun7g1yTKR=u5g1*DY()N#!~P_H`t7VFS)_y6nxnYwxHlDH`tPbtKDEL3clh7 z<0!bs4YsD>S~nO^!B^d20tH`lgNYPe=LXwQaJ?IBOTi6pupI?Ay1|DixXBH+r{L>u zFo}Yj-C!~Wx46L$6x`|tJ5q3)8+@38+udL%3hr=&k5F)@8|+NMU2d=o1>bOkT`9QR z4L(Z2H{IZ46x`zmyHRkj8+@FC``lm(1^2tb?i4)W276HOEjQScf(PATFABcx276QR z9XHsAf`{B-UkV;}gZ(IY#0~bR;88a?fP%-|;6Mrh+A$Z39~5XVl_8-+M}n%yYG@zdlM9Zg5|tPwP~MMwAMSZHda5XV9@8-+L) zn%F4BvCzCmA&!NnH41SoG^dtzIHxqDMQ7@btkR6eK~9Bc zG!AkyG^25l)1euSgPah}XdL8}Xhw_9G_2Y{3et=g9i74%rU{Kg92L!H6ylg@I-?Lr zM6(%%I3AkJD8$jwTt*?zFim9?;tbPFMj_5HO=J|}4AVRoohbzwrg@BmoC?ij9OPtZ z9^)XVL-QC1IU$?dvTCc zqS-4tdKBl9CNB!{{xo+{hm2 za$+=RagbA^Ig5fdxJWc-agbA^Ig5jw8qHZ89JpgD_!90Sc+9OM{i&f*})a0o%AfHC&YXFIxfr|FV^djH34tvqnZnM&Q4wD5qy6ZQ=hS zVDceUI=$<~##t9-m%UjETpxDP_W1fD<@JIX`$29H$o`NUgX9F1J&RdK1E4nrX~u*u z_ONA|#I~Rk8QRHg3(4#hw)e>FRJMibKYzXY$~BE$5xbktuBhET!|qe z*irfdOIpjME59$sCG5%uxPW?E%C=m9^~JdixqMTQ%jJ-J1abxBUV&T*xlbTpWLe%` zo|h2genE^cLmm*wRgiB5$qDIu(rVTf>^Xe}u^!a1n(J9wuF?N!ysyE(ZwD*2>Rk)< z4lB2pWjNEn3VleZUxPlZa}c&4uY)Yi|61ny^^ivdac+P-<;`ngO>KlcEs&ca&j{q} zkY5SpX2@#-xdrlTf!qrDjX-XL{7xXZLw+xiJ0O1$$eoba1#%bUj{^AyA;{w|RFApaD|{g8hN{v` z?r8U?8$nx~!%)X9>Il>ci#iH*(xQ$*o%O2)YNp22%6U5u`5sGu?FHx)(C-WNN$3xR z`V{mzp*{_LUZ~GNUl8iE&>sr*yU-sA^?T44h5CKyOG5nt^v6Pd4*IfCpNIZLs4qZ& zD%2lBei5%y+Hm1`GY|I4Eei2 z{sQ@npq74x%)zrklUJRcy&e<4c<oQUvuHB{=+h%-`4b2X@D;7m})U6MeR87ewBE|p>ys7w}>6)LkuWrNCMQQ4ug zT2v0GlHq%Ss*RkGIdpvfwpB70WGO+MxgkpnWFE--wG3>FJD_svJi2Ov>ZvM^c_DN8 zr8|Esl@BVnUj@W>CuA8*{_;cR5yW>FZtt+N3}gj?EDKpoka{`DiaO4~ za+ilHuHy?kPgH=s&o6!Bup(3?ORANiO8DcNkiNDnLzeVQU#eB0D*ICnh_5PS6@jb< zSxToIw)Lt*mKMkwkoU9X5dUBIE<&=9hQKt2FjF(~zbI(QJe zQjqrLwGm|HAQ=#EW9XWK{5FBCC6F$Ey0)NX zEg)+M<829DGf4YN)(WzYAO~@fbp^6DWIch5hpaD<36Kp0G7++&K(>K=Kp@*fJ}8h6 zLDteWZyvY!EP~^3+C$a0s3fR57L^QD*P=Q=)w8IMQ1vb9VWQSgB7S)Ya75dL|j{Z2iN9-KyFtidOmNRpXQYFnnp#vU zRIEh}fof(^L!p{m)G(+P7Bw8IrA3W^YGqL)q2erR6jW=A8Vwb1QDdMIENU!NqD4Ic z)ktt;cnY#jaC|s0P~UQ%hH7h3RI)`)g6d#Vlc73V z)D)5Am>58ERfGZJ|~d#Atwst0+z$=N9^)G=fU zR9A~y3iYT(ErWW@qLxE-v#1qNk6YAAs1%EO5vsdIy#&?6qF#pTX;G`7dRf$JsNNR! z3REA9S_9QY&@a|P_SNy}>n9T;`DzQ@eA92Gyb9efNc+wLUxVx~kn11^1j&FLtcQ*f zlxzcJ(;zu9eaSXL4-CphfZhZh8x*&%9$trRCXkyU2MKeq1-iK)-mQ==1acc>OM%=0 zIaud4@SJofRH{Yof*N8`Z$J&TsNGP*Eb2|D;TE+AYJ^4Yg&Jv5`=CZy)PAVZ7Igq> zj77Z#HP)gILOo$oZ$q^T>K7B!kEBDatJ#lThuL+pyCdud*xgZfPukrvcFs(}QT;gN zQh_`Hxn3YoLaq|XQ;_oo@-*Zmfjq-yZ4d9CxiQ$T77%~^^`@O zgL>Mc&O?o}s0&czE$Txk$D%%hnqW~Ep(a|?C8$Xj^)b|Bi@FRo#iBlenrcy>LQS)% z&!DDjrPma`qvI9GxS*NECqIX5Es$3spAn?~1>_8Y{1S4eKz;=oAC%7t>F3I8(6fT# z4bWdhCkW&I20AfF`|9>v$TkA`J>+biU-P)H#_v+1u}wj>U0puNXU)? ziTmiz!vYzNI6DbsX2@myulb~(TW)o&F$>gki^>YM!lJT4t+c4@P%m0k4yczbDks#- z7L^NXl||)-T5VBzpkA@4JD}EBR9>jH7L^a`Rg22c+pDX#)+1TBH?KCGyV!NLySv#9 zw7UZAp0c}w?3`JG6>lNPWdeB*X8?8VFA25IqDn!nx2V!k8!YO6sErm?25OTe8=+oEbgy=hUk zq4ro*9jLt)RTpZXMb(4aZ&CH34p>wJsJAStA=E*OdI0Kei)zH%Yp6LO?2(}{yGQM= z3A;gd7sKvpyKBnMnJt({Vs8>S3tU7S##rj72>Hb=IP~K)vf%^V6R@c7=RTARmQ%UmzcY{6HYPL7o%H z$05%PWD4X3f$R?Xp+NS4{74{sLS7WeUXYgrvNz<%0@(-hvOxBQ>=HC{Oi15L`ayr9 z0No$DYf#)1)5kpk`qQAe1N1=XM}y+_T?rTj`I#`@!O)Kh;!TC@CXhoRujm|@ z*X-2#Y#7w%7Bw8|szr@}`of|{LVambqoBUBsL@c@ENTqY*A_Jv>KluC0_t0fdJ^h8 zi+T#`dy9G+>IaJ&2laSRzX<5Z4(pogXspMR?>v73yT|NqBD=wMH;LUiyPM3;nIl;H zOo3b>kW(Qy3FI`$H3B&ua-l#z136V7XRsV)ucMjldfVMBb{*|*HgcE})PsC;+Z@R2 z{BQ8H!0M{NvyeXucD-&qMucQ467NSkxk@-z;h| z)bAGc0@NQCwFK%!!W;fpMUSa1vE0_V+K&}+XwUDn1MFP1Fa+*M{XF1wlM;qAn zvAd1z9=5wp$YBq`T(KGQU;a0PGt@0mw=HTb)PEMW4Jtx^o!Fe6)C{^ED$=5MKp9^; z4vcFjRJ0|oT~L`U>J6yO7PT8Hi$%Q&mDQs5K+&(DWY|J`p|V@lKB%7DFWkOy7lr(* zAk_v3pmX@+3^<>C3o@rb9)!##kZ(ig7RYxX^9bZ2$U6k`Fl1hVJOY_dAdf=cDUin? z^9$s0$h!pc1mxWUc@naKK%Ro^C75SULl)#XS@Zqkh;01TX6}9N|5p-csabKnN;_tq z!Cr-QPQvz8T$^$3(bAm>0=|QQ>oZPoo#((g;~Y{hEQs$sWD&pgtsO5w_0g$@Ey+ia zMT6txqdCXnT!gyUqAo!dv#5`uid)oWsQWDH6Q~jvh3gJZNsGc&1gDfm;Y{BtZBaPW zckZ_+oasAdEDC4(PFah>nZ8rbqHw0~l-El4i)rbv+Te^|tZ`0X8zW7Bcf7P3W!#f^ z4ddXf{&Bm*dHoQ(!<(vEPG7-Hg!3k+g6^AvGbPTOoQf8O^CqW~Md7^3scca= zZ*rMvMfy5fuX~>du z;9Z?WWGk)aOtm(~TGx3%#~nB}u+DV`2ug)@uJfRdFKnr>&J{_lbDc(lII+$ZNvw07 z#)3Gp&J{_lbDbuFII+$ZNvw077(tv^=Q>RV6027yR?EOP$7v+Sq zJ=UWliS?+{LJ%ibnj(qSrqfc#8CZU-Hl0=$h1I4LXHi&fI;|}Vt4$}~qOjU@5-bX< zO()T!u-bG63dS{7oX#LE1M3VcPN$7O)d}fWfLL`pZT-?W^I_HLwDYTg_^|SH23zun zHGuPwAU>=Eoc4a{%OBPOPLf4o9pEJURX{1Q7I0Gir3jE%4>%nJabiv23=zbMb%E1S z5GU3K&cl8gaF&YofzwILuyX>|2+ku~2KF$l5uDCig^dsE1gDFZf$`z!?{xL6fbZqu z$nOl*^%yo~9Mhdg1##k-?mQ-tIHo(@{L7!NHo`j>1(^nvI1ad}MN`WJgGuonX1aih$6pld7Sc}3D$myp`5ZKpn#Blms6pj|o z6P6Tlv~ZrZC>#Tvrz{Hdzw@+3Vg7f#&3M0yys#6Wy=P;_AnU?r4 zs+?ICg;C|qW+k}Fh0*2AvBZhdG%Rmf?j7;=q1j4OI+wB&H{@<+dI!#a*wumW>^&3-kE7pXme+lMWHpF*%pPC zbmmwTTG4r)Yl82#MP%b6k{c?Gxyf@66>a1^%W+zcUuXemp{0h=0#=3GSryW97Wq@0 zk$#4SaTfcfZ+^md=LL(}%G;e{!L_XJifv<6H*Bpbx1C*_-R)o(V|P1|yF+{jDY(5< z%DW)93FI4)dj)bg$Ug+~Ey$Pn zUrQ|=gros!m2X47EQs?R$W;P)2r{oA^}~>>1#upMd_^FSLKe4-vtz94+3V*xyViDh zf?ZR)JBi#K7PR&$$n64o8gidNo`GD#|5|#`S;+SValQ-rr9i$1d08Oehx|_3y^S@lDg8Q*ovB!r0V~;Pe$HxC-k1w&uri}J@ zF8#{oE9~`pMtk{IG1sui=Ko`lud&CLjP`goea^nYURVubzQtZx9sM7BeTTiU zRSSx0reuu(3F$47n)Iwn?{)Ap6)PF%Q7V4YOF9`MD&`Y!q zJg>b4g%z+{2fDZT#_~UqSOJ^0H8Xvm`WJGkPFcqp&;xHnFB9tjpqFbMSgMH3G?JVZ z78MD#(yu0_FHscai+<^=p=cHjpt1V*YhS#XAz#v|>-zM`ERZ-)Fx$wd zvO(b-!IE-z$d?5v=YYi7geA_LkgEi7=7L-;khvjW5y(7{IG4$whVFpEc}xZ>FVq@A zs`(&swqvQCJ0aKVI0O54ekhz1WstwSpKL*m>wgS=IM+ToAS zm$!;gI6KZDu1Zil{c!~xFDgUg9NLU8;8i>d{+$D(RO?X{>nQ2Q*ZF4TUDst1MZ4Q8D^lYYe1hdf}3uL0Cs z7S#~yphZ0Z^|nPl2=$IdHG(>1QH`N+O~q0hO&||j;){Vg;#UD9rYYo6zx4I+Sg2zb z)eP#mMKy;yVNorhPFhq;s8fCwP|jA6r~T4b&N!$u7S$T+tVP8`y=zekP`E~BwtT?c zkqG&oCB8Opd=}Lf3fJ4rR0Bp|J6BrbdkE^BMYV@IZ&68ZTztM^=FQhq$!=VJ6;N*- zAaQjsgZMhS%96K-p+5Ahfd1AA@*}_WmEsYoix$-x>XJouf%@2@x^v8n~NL*PprLShYL*c4w2C4_t6-(ZFLgBh=266R*!Zp_n zRBx!yb&6rnDf>X;%4`Pl^@GAySyzRPuRr8fLCOOlasAd3=Rn9W1aS_6{8AtXLw+TY zsgTzMatI`@Gh0eD4Dv+KorTHi`{Hoc_31yi*7b8;0d@r2c$po^HdbawA;(9AIUWtY zL#W3{?_c-XEgmI6D{!6GGXdH_K zIhg>RU6}8Q&^Uq#;+_PJqnJQXhQ3pnlPSjr%|XJr5f9e+2qD zXx#S^==spN_ao2?pmG04pr41veIS8e2#xze0=)HVO1=(74+q(CeTh_+Nou4;?Ag8=#|v zdLwkSP;Y|HB-F1%XBO(s&{>3f3v^bY-U^*fsJBC(6s~=Cux=30k^yV!ooo|ib{E@b zGW!N{d{mg@-OxLQ`c3EqLcIsNIRESK*#Y&j7y6tq?tReLgnB>pr$T)InjSC}<@+t@ zpM`NBguW@%Z$sb5{|ajG9q1gwd>?`?A&mPlbV;E;0-ax&lcUh3gmE8(t{~JWpmPN2 zfVK2V=$t}*3ObiipN7sY)Mudc2=!U$JB0dO=)6Mx9&|pTejoZyq5c3mzfhlpzDuaj zL*Fgb7oZCW^@q>}h594tLPC8J`W~Ua1YKCDKZY(M)R&=)3iT(@_X_o=(8YxM3iK)A ztob?XhO#;HD%(Vv{eo?Cnf;Qjb4-}yub_7c^)=|Xg!*gf()_RB81fDDd12h&LVqpP z-$8#S)Zatn$yY(Xe}Mi)825GPzlHio===F!K~8>x&M7?h{R~}3822yGWrg}z=(~hD zxdB~H824|`<%RkW=!!u);3)hjbS0tw3%asU--NCr)PF-)73y2i)r9&V=;}iKFLVu| zz71VdsQ-hmCDajFcxJ0D)REA2ggOeku24rq*AwbY(Dj8nGjs!?&H~*~sIx*pAk^8Q z9~A2B(2ayT2Xteh&IR2>sB=Td2z4Ilrb2xObgWS4g>EL)`JkH%^_|cyggQTTOQF6C zx|LAh4IL-c1)y6CbwTKOp)LfSAk_CjCkl08=r%%K1iGzI7lm#o)b~O^B-F*A+Y5DZ z=p>=O4?0<>OG2L(u6;_een7VJDb2Qx%-+woh0K;=>l_#6xGeM=LR}8}piq~G?i^Ip z0avstKwl8XT@m^lp{@jdMW`!7M+;YiRiJ+r#$6TqmQYuN?jo$g>d?7_`K|%oRTy_o z=tqUR7WCc1oYaPXOc-|^=x#z?7dnNt$9Skgg7^|3 z2Mc5(WU4^6fgGY`U>@5-4YjCtP(NDA`w-Mm7S$f=XNyXL`o*G>p@vy<-vR1ZOI#hH zhU>V(_R@zTZ|L~K%1)5K31nx;5rWjaK#mm1u8_YAQhy9`lpxM-kbel`d>rymflPt? zOCY;L-W13lkbetgPsm#W*&A}SpqBbTjuFVdkYlwB9HsrBp0KF?P)}Oa0H}X-c>_}% z2=%W;4T5^glHy>fr!6WKYMez4fx2zU*HEbcENU3kcuR`Ip(3Kx8YHm3MnKUzBD7Ko zR3o9%zM8!bjFMZ?td8p?tY9Ul^OKmKI%41QBp%z+Fd;w~aMJ<6^ zY*9<0Uhu00>FaD6LsWbUfoKtLZ^2mKOjH(q|PMepIO zzxB{B>$n5g3LBsbSn|0Ms-Q(}f?8!s@pY)x7PT3wkR`<}Q1@8WR;X7jDQ<%*Y>8_- zR1u5X0kuY_s9PzZU3WqkwZyp#>RyX_1FD!s?S?9DQEx)66_#QT^nI2%_d>lYjB_9K zYgz~P;r&o0EGZv=Drr$~L9OEydG+sV{x!?Mln+9$x8(0_s0~`_-ryUv??7%8$U~5u z1oANC>jHTMax+W!%!lWfz;Yjj+#-nc801!gJPx@nl)9znPe7NlwB|{u(iU|J>VAtl z4OPaX&Onv5sIySpb*%)}^1DzwEb2X|ouPVjzZo31hrJJ7j`OG6IIR8vdY2^!=b*}4 z%6uN`4NF`Xpek76`Vgw3MSTRd+mhl%s5dR@64V}x`WR}jUj?j@FGKG0OW%C(3Dkaz z`V{JbMSTYKmPK8GI%rX!L%nTLSD`BDRtnqCzJRPOkY7Sp5y-C~s|w^b$ZA2-NxxG6 z8oGLr_O;$Okni|wX?prNzlE$Ji1RzhngaPfWG#XG0kXD0UWcqBkUv7!7090;>j~t~ zko5)f7sv)dGN46&g+AnOr+{CoxB=NPC|+ON{|5PhK>iN-pg{fs*+?M&glsI3e?c}0 zk^wb!6FMeH`^x_}WK)5>1sN-l|3Eeq$bTW53*>Fc76SPnWJ`gJ$Vx|7r3Q_Htcmg{a)_M zX-@h%H9Pi5&~*^F#>xSeXi+(#PFPBo3+iMjk0Y>p=5q%w8K*EDf4L8Nr4Pr`Z*-^q zPIqqXc}mBx>%!L(c_2><wjW6E?AkSwM|Gf0^7sOr{bo_yJT?pz!i@FEu zql|Lk%X4AuanTZQ5vWTRRTS!Di@F!;vPBhx`oyA&Lw#yd_d$Ke${nj2Ui&Hm-A0e< zuvt?=7k>)DIR_59+!_)ra~~tFS$*0pw3C zxt62pzldyMugEoo{#g+31CYOH8CZW0LjB50UoQ!ijUaF6_`;T`G33L7KGOuUlR(Bm z{w7GhDdg`084LMGkPNt@(G2>}AnhBm%^@EVl&S?}XMt=9`IjK|R**Nf3~bFfsJ|_$ zHB=Wt{^B9K3S$bW+J zJ28EJ+e7~=)Jf1Of?Om+-VTb_m){PM|FI0MdU^KAgc&Fg{j2NSw`WJ}8Np|amgkNi zhU_lLcPGe5L7b03MhRqR$mk#$(9&I?dvIRel4p1f?F!vfs2_#yE7Xrc_Y&%E(3yft z>1(&gAv0?kI5(s~WwEI4P`x>imOjt}vX4OagzP7fy&(GwWN*j;0@(+0pg{J8926u2 z`c*&Zthzq+xSE)LUg!^?J*B> z0+&ReuZ7jmK^NtC1$sX8y*d|xHNF6WpfSPJi8=R8l1sCkwY_e0gS#B~6wo<+R{Ro|lChAO1{ z4%FxIcjI zB-H1i3kY*^9{Les+!vrb3-w3P4T5yQ7tAg~Hx%ki&<_ap$IuT7^=0TrLj4JJW1;>O zx`|MK1|1{RSD>2;_2TA%gg!*gfIHCRqy0uV$ z3mq@i-$5q`_4m+;Lj41D8=?LY`X1qY@)PSuvZKz=Y}?7~FKk=M?61i2S>Zf?1Nu#& z{tfyaq5d7ZZBR`ItYH3t{zw@2pU~e4^ zFLWMZzHdW6B#iq%==MS#k&XJQQ&5cULLCj=g|&O1DDZ4I6I54=$_(|W zMP-3{%%ZYFb+f2!P|sP;O|nDHx2POY3oI%p)Z>8}qIhF&DdYZ1snI$n272fR^G6mqbZVatCn zWU4?GgB-$=`>*>(ScW~hIQAGSi2FXsVFFnKa(IvosE3l!BZRsX^vEFXyTVc$a+E;c z4>?*O%Rr71$g+@Q1+pCE69QQt@=1ZL0Qr9H$Rz?<19GWA)`VOpkhLI}3uJA`34&Ux136J3>q1Tv$a;{IwG3RT z)Q6g4Q4OG`T2w=*X%_VW)O3q_5b7CLdR7c9K_kc+A?dbD=sk{zZ2YxHU+-=FfA7%* zd(8Yl(un!L_h^beX6bt2V+)tvEzy1H%Mpt`X7e7d$#B)w?Eliuq38S`C2sM5@6i%_ zJo|r?xE1!8D=cx`|D{_)&-*`09RGjsk$^p(^OiWUk0wIS7nZaQ^a34k;7Dl;^}JSL zS1;`#7YgJ%?0mS;)&RbCS03j&!8 zxkMm4KrR)?j*!a)@?ps30@(?2g+M+6xl$lIL%t}GT_9f)$gYqt3*@7as|4~f$khVb z4e}L%d>nF(K&C*h)l!d-W$Alfcj#BO4%y9IIt8OA#q`h?bD#*@ogFG#e(;?4jnPCo|fj+Bs z*c{A&d{@g10##``Svd9B07I~VeTK+c2w zP#~X!{74|@LtYff1(25n@_ERQ1#%(eWr17-`H7ag_5;>Ki=jW&I&AH~0Qs3fE`huv zkV_#y7szFhR|Rr8d$ z0{ISPc7Z$unL{8CL*^97BapcS@+f3(fjkD8M<9|>1@e8!LIU{#Rlf}A3*SLj6Ugr&t81BIUVnhDp>^22UWcryrH(hCWIsaJ(mHJ2 z{sdWDAb*CeqovM4K#lzZU03U{IrtT_oh=%l z2eb|w@1KwlYMEiYe?d3WI&6*IglsI3e?vC$%Yahdf{gLYfR_CSvZ+A+3mL1WE`LD0 zx1pP99k%@cK{nSi!+0aI(`wymp>^1JBOzOAnPI$9(5mLwhVf>BPS84RyjdX=wahTyY|w4A4jXTF$hHER1G1f#8Rj4-^g~*Q%|R~6_F85b zZ*J%$t;5Ef2Qpd94CB26x`WnXD@ymcX zD?$$S%YZm5K@Jnh%8Z4ac`4ge%3w0al1wlF> z&uyWf*E;Nxu^r?>fqV#ZkwCVGTr7}DkS_>iGUO70>;Sn`AUi@X6Uc`lmkVSk$Q1(l z2;@qE>_vi4f&lwz5@BZK(2xOK_J&cUKhw$A%7Ie z*C2lq$aRoE3*>spUj%XkId{{-?)$Oyh4ZhIaTGEyM-LPiPXKFDZ+ z+z**aAP+!h7Ra|Cvk2rt$gBeSHe@z|d6f(C!9)rvy zkjEkK5Xcjdc?I$$WIlmB1$n1Ho`%dXkY^z863DZVcMIgZkOc(tJ;;Ir`95SJf&2jS z9)UauSy&*?LlzOp3y?(x@4KZYzJke4A#3gjn{r3CU* z$kJNsD{%qm37xXuh&$5ht3jty$EG<{N7kbE5gyn#G-HzO!Zt zCz|iAS<;E-2Wyu4xf#Ko_tBcAe{M$bEy5>jmif6E!8Sizv+U2!2)6mfn&p0OMzGDV z)-3;XGlFe?vt|V+n%}Ki(TQdx{V)0SujE8CvNbC^(TrlvDo!+AtXb8GrmHopIni{p zW_2f;?$)f~XgZ#8A~^dV)~@Mj|MD3psx@mln!nv{G;7y(w12tX=+>;`X#RG)F|1wJ z(f;LjV_LJG6U|uGtnX<4_6TBIyMd$q%Oi+m&4!NVZ?_xQ+Kn9TUv4*^H5)sczuj(p zYd3MUvE2yXqa?6q)1R9W+%*ZU+3e?L1kVG1ShKkk%|zC0;Y2gBHCsB-Ok&Mej;7;G zMKJ%Q)^6=+|MChXvt}D7n#rx{=|nSyHNBi@rnIKF6U|iCZ0kfbwKaX5Xr{5IuM^F* z*7S3tna-O2PBhb7vz?>)+bf#E+U*_fUtZCS*6iR!Gm|v~oM>jYW}p+zEY|GkL^G>3 zJ2}zJX3Zccn%S+{*@f%xTRKCz`pe8R|qcw>7&s(adAbu1+-bTCqN7tHTyZyEN0FA zPBe>KbAS`g64o5(M6;wd2RYF!WzE5k=5MckX=@L0w10W+%UE-$6V0;L9Ogu`oHd6# z(JXJx5l%EKSaYPK`P=zdwDu@R`?MCp9wwX2OJJD=z%>_R~77y zPBeR1bDtB-~6ZOwyDH2YZdkQ2?m);#=kGlK7B`dRac6V3kCJnCrv z_W5amwU0U39%$|3j`lB~p9Wd;groV}qZn-Mla4mF8^L)PV$D;IrenJiw1-;zw4?pY z?GCf%8AtQC+Z}H0vyS#J&%+37o^v!E+l}BkaHO@*JKDe8?kH}g5(Z(@HaQ95J=AECL5nQ+F*1YRPbA~nV{oIUT z?=!7=|L0}|d!J>^2Tn9+Tl1l#>9`6J9KjrG|LJ6VuC*UI+P}OP=2`PEN7Hc>5zKDB zwf}asf4SWS)_m+}{&u?yt^LH&{^fQTS@R!9^S9ewZ0&y??O$$pi8cRoG=IC@rPltR zqy5Y6F0edbfS6AntwRaJa5fJPBbrAGqDrRi`Goy zMDvn0lRDA7Y|UgpHzT-4SFD-*=Vk=g=&ChSIMKXj&6GbkBiQ?OYo>CddBd8ie{M!_ zoHwnR#);-FYo>LgdE1)loM_&$W_m}{@wyzr{O?*jLqzQeW_Hio8J%q3w{|8+`Z0wyticr5(T^oaDYkNhv`T_Z(xjqDOtQ{#*z3LF|Ncf zi18$TMT{@;8)5>9-w_i^jO1$*`a@!5#6%LKASRaRf|x|2D`HZKZivYwx+5l+=z*9* zVpPPG5~Crek{BH^wZs^RX(Yx(Oe--KVmgVj5z|YIgP1{LT*QnL;~{2}7#}gS!~}?0 zBql`6D)A4*Y!VY8W|x>4F^9w?h&d%DMa(5J8DegU$r1BNOo5nJVoJn(5>p}OmzWx{ zfW$P21tq3MEF>`IEz#4Ly*Wy(Ib} z_Lk_6*hgYJ#J&>SBleTn0kMDoNRi|zI7$FH01PAtf*r|0U?*}g7(@;MJCj4fU~(83 zLJkK*$q`@|awOQ590hhGM}ytTF<=jJEZCDA2lgVzgT2WKU>|ZK*q59H_9G{Q{mCid z0CFlgkemh%BBz6c$r<1fawa&GoCOXeXM@AZIp7F#E;y2$2aY1=gQLj>;23ftIF?)l zjw2U?Uv*FSwH2 z2d*ObgR98{;2QEExRyKwt|JeF>&YYF2J$Glkvs-&B9DWc$rIof@+7#GJOyqePlMaZ zGvE&LEVz?A2ks)zgS*KK;2!cKxR<;H?jtXQ`^hWd0rDz%kh}&SBCmso$s6Di@+Nqc zyagU3Z-d9lJKzcOE_jl>2c9DDgQv*{;2H8Ec$WMVJV!nP&y#xOd=B0sUx2sCm*5@p6?m6?4c;T)fcMF_-~;j< z_>g=L{z-lSACVuyzsOJE-{fcTG5H02LVgARA-{qDlHbAq$Vidx_4j{dWbi2&1$;)j zfX_)+@CE4xz9ikjSEL8{nv4p*A)|qB$>`uaG6wjbj0t`qV}T#Z*x)BJ4)~dj3w|Nv zfnUk^;5RY>_?=7$M)I@IRQ>+|Ba?~1C}d*Lg-imvl1V`~G8yPjCI>yp6kt>`B^ZrN z1x6=RgE7c7U`#SC7>i5?#wOE)amWl{TrwjVkIV$dCo_Wy$Shz&GAsB8nGH-tW(O0K zIlv@jPB1B%3rt4l29uL{z!YR&FeRA}Ohx7gQ*Feh0K%te+5bCVUoJY+>MFIfr9M^*;& zlU2Y1WL2;rSq&^iRtF1{HNYZdO|U3g3oJ&~28)w*z!GF#uq0UzEJfA_OOp-2GGs%r zEZGPwM>Yn_lTE-1WK*yr*$k{iHU}${Ex;;dORy^03am!92CI{8z#60{Sd;VuYmwey zZL%#`hx7sKlD=R)(hsap`hyL~c3?xYJ=los05&EAz$RoM*p%!DHX}QM&B-9J1=$&F zNd|+h$PlnK849)`yMUf#SI~>>26~g-!M0=%(1+{^`jWjsKe9LIPxb-Zk$u7TWIwP2 z*&hrb2Y`X(K(He@2<$`-27|~UU}thD7)%ZWL&)J^C^-V`LXHHxlB2+GXJ%dv$dT=(m0h~i_1m}{QzJ1lN*>z;)zda6Neh z+&~@$Hd@B;Zac#(VzULv1>m&t#?E9Af6Rq{XZ8u>r)I{6g5K|TX- zlFz|glX1Z>WIXUI86W&cCIG*a3BgGI{QL_> zCKG{C$i$!vnFMqtlY(w!GSHn&4tkI&z^G(OFdCT(j83KoV~}aUm}FWo7MTu=O{NFq zkQud94kjjZfJw-lU{W#{n2gK~CMWZNDagEF zN-`gqip&qDCJTUR$bw*6vJjY#EDWY6i+~x(qF_d{7?_DH4rV4xfLX|rU{$ckWIvJ#k&tPJKStAGW_s$fB~8d!*|4i+YBfJMlf zU{SIbSd6R<7ANa~CCIv9NwOYTimVToCL4fd$cA89vJqI0Yz&qsn}8L_reH;~8CZ#I z4pt^xfK|wrU{$geSdDBARwvtlHAqjeCg}y%BE7-dWLvNf=>yg!eZhL9A6TFC2OE&> zz=mXduo2k-Y)l4#O~^p7DcKQhMs@<5lR;n$vNPC{357`s+C3}H>WN*-)>;twV`-1JseqaZ(KNvs`00YT^U`KKg*ohnr29ZO+ z&g4)qm>dR%ki)@Has=3g90_(MM}ghQ(O`FS4A_Gl3-%<(fxXD_U~h5)*oT}5_9Z8Q z{m98+e{u>qfSd{rB&UIc$m!r<;A-*!xQ09kt|bqF>&V04dh!UkfjkOsB#(ic$m8H<@&verJPB?k zPl4OW)8KaU47h_l3+^P(fxF1_;BN8)xQDz5?jJGB(H&o$m`%? z@&ya^s9Z-K|i+u(8X4tRpR3!WtJfv3p(;A!#!c!qoko+bYT&ykP7^WPlJgZIcc z;C=Ef_<(!|J|y3Rf07@-N90HFFY*)kH~ATSOnw2MkYB-n$Zz1kbO&FN9^h*-D)@$s2EHYugYU=~;CnJA_<@WCek5aqpU61i zXEHAMg^UM&CF6tN$OPbbG9ehL9Y6nqk;z106f!aBLM8!S$)ungnGAF%lY<^)3NR{} z5{yQs0;7|u!5Cy3FeaH6j76pcW0UE@IAjJeE}0RGM`i-!lbOK;WEL!C0Lbg1y&<?o{lpFzeAxDB;$x&c8ax~bT z90T?s$AUe{abPcUJlLC@0QMm#f_=$JU_Wv)*q@vN4j`w31IcONAaXi5n4AF)A!mX^ z$ywkqayB@eoCA&^=Yk{2dEh8=J~*0O0FEISf@8@=;5c$IIG$VrP9T?p6Uk-ZByu@8 znOp%*AyJ*=Jvf`(0L~#df^*4D;5>3OIG@}CE+Dsp z3(0NZB62&pnA`y_A$NjH$z9+wayPh~+yky4_kt_Qec&o`Ke(Da0Ineqf@{e`;5za! zxSl)$ZXl0>8_8qfCh|DAnLGh*Ay0x^$y4Aq@-(=eJOl0^&w@M2bKoxWJh+>@0PZ0# zf_uqJ;6Cy)xSzZN9w4uR2gz&TA@VwSn7jcVA#Z|5$y?wt@-}#!yaS#f?}8`Ed*CVZ zK6sjZ0G=Tqf@jG;!E@vz@I3h!c!B&IyhuIYoqP)3 zAfJIZ$>-oL@&$OCd|;Gg6N@DceD{EPeq{!M-c zACq6eC*)V~AMzXcFZmt(kBsDs&%b13@F^+(KGgpHOS*v1NmuX%=?1)Bx$@t(mG6DFVObAA5&(FVL zWHJ#Lg-i^(kV!ySGAZarCIj8ciW0C2=*kpPz z4w(UrOJ)S)k(t2wWM(h{nFUNpW(EHsvw?}o>|kOt2bhG+2__|Tfyv0+U~)1Kn1aj; zrX=%$smT0bYO(;BhAarCB@2P+$iiTHvIv-gEDB~Mi-DQQ;$UX71ek>^31%frf!WB? zV0N+$n1d_}<|NC3xybThZn6THhpY(ZB`bmX$jV@TvIR@5A23Ulw z2^J-5fyKz$U~#ezSc0qzmL%(erO5hVX|e%WhHMCyB^!a|$i`rKvI$s$YzkH+n}L<4xr`-1`G05Fgo2zDd~ft|>~U=TS3 z>`V>?gUMlF2ss=KB}af=$dO=IaunE&91V6S$ACS^v0zVf9N3E-5B4S}fPKh`U|(_) z*pHkH_9v%+1IVf1Kyn&5h@1`%CTD;{$eG|!auzs@oDB{q=YS)~x!_209yp4e4~`}m zfMdvo;8=1IIF4KljwhFZ6Ue3DL~La+zl=# z_kb(Nz2Hi6AGnI#53VK;fNRKu;9Bw!xQ;vwt|yOx8_1*JM)DZAi98N&CQpD{$dlk! z@)Wp@JPmFq&wx9~v*1qh9Jq@-5AG%}fP2V`;9l|)xR1OH?kBH+2gs}7LGl`Sh`bIS zCU1a8$eZ9%@)mfEybT^F?|>)ByWmOk9(anp51u9;fM>{u;92rd@ErLFJWu`wULgMl zFOrYJOXL&qGWid9h5Q%1O8y64BmW0pC!c~h$Yfhbqk?b9Xy98iI{1!^0lp_=f*;6O;72kx_=$`I zekS9BU&wgiS28~MjZ6T3Cli8^I`H!^7@152Mj;b}E@TqWl}rk{k;y=JGCAl$rU0Xo zDZyxDDlj^k8jL}v0b`PB!B}KEFgBSUj6-GsMBdC5v( zKC&{HpR58FAgh7}$!cIBvN~9ptN|7wYl20|T3|73pYynmwTY^=|R$w)A2Y)%G& zEy&JbOEMU2MTUT_$xyHj*#-0@yMkV1H_)5x4z?wGfIehT(3k85`jNdsf3gqQj_eDz zC;NdN$o^meIRFeK2Z9~RL0~6xFc?G*0XvgJ!C-P27(xyQL&*_f7jh)nl^g|jBS(YX z$uVFLaxB=B90&Fy$Ai7e31A;`BG{Ll1ok5*gZ;@V-~e(eIFOtM4kD+6gUK1-5OO9s zl$-?)BWHud$vNN%axOTMoCl5~=Yylk1>hKRAvl&?1dbyYgX761-~@6hIFVciP9m3s zlgSm}6mlgvm0Sf*BUgjd$u-~%axFNMTnEk~*Mqak4d5JdBRH4b1kNKjgY(HP-~w_h zxRBfiE+V&si^(0}5^^WFl-va_BX@(#$vxl-axb`&+y|~A_k*j+1K=9+Ah?!11g;|w zgX_s7;0E$2xRE>tZX%C^o5>U47V;#xl{^J*BTs|d$ur;%@+`QMJO}O~&x5F$(P_A@)dZOd=1_s-+=eYx8MWv9r%!Z5B^Dh03VSb!N15);NRqD z@GY1tXJ* zz$j#5(1lC_x{^sjH!>OMP9_IE$P{2yG9?&|Oa(?KQ-d+cG+<0JEf|YT2gWATgK@|V zU|cdI7>~>Z#wRm_3CJv9LNY7(2bm2_L}mvQlR3a7WKJ+CnF~xt<_43KdB7B8UN9w@ z4@^bo2UC*;z%*n*FfCaKOh*<5)00KO3}jI-BUud0L>31#lO@0`WJxe9SqjWXmIkwv zWxyO{SuiJA4$MWC2Xm7Zz&vC{FfUmN%tuxR^OIG;0%TRNAXyD8L{p80&9`pU~RH3Scmih>yo};J<<=XPx^xm$aY{u zvOU;{>;N_<1HdL^AlQ`b2sR@-fz8Pvum#x}Y)J-#t;i6tH5m%FA-jN{WLMCO>;`(1 z-NCkG5739~3Hp+~KtHlK=uh?m+mU_2_GCY>1KA%8AP0bfTr*14GE+U?@2P>_UzNyON{8ZscgNJ2?jIL5>A`lHr8P9t78thro5@VQ@Wp1l&L#1viq%z)j?Fa5H%V+(MoNx00v8 zZRBZiJ9!4&L7oM7lIOr(&x*UIh1&m%x4GWpF=v1w24r1rL(fz(eG9@GyA; zJVM?CkCL~*W8`h{IC%#=LEZ&VlJ~$<Kvyy;=td?3-O1#j2bltlN~Q#( zk*UDwWNI)5nFfqWrUhe>>A=`zdN2-|0gOv#1mlsJ!1!clFaenbOh{%0{~)u0iOB3= zVloGqgv<#hC3Atv$lPFZG7p%7%nPO@^MR?z{9tOb0GNg>2&N?qf$7M?V0y9$n1L(` zW+aP&naJW`X0imBg)9kXB};+X$kJeTvJ9AmEDPo&%YnJb@?dVV0+@%a2<9a#f%(YF zV1BX+Sb(ew79^{Ig~;k)VX_8Tgsce`C2N7j$l73WvJO~+tP7ST>w%@n`e13Y0a%7? z2$m%qf#t}?V0p3$Sb=N`RwSE&mB{8`WwHfWg=`5{C0l{j$kt$WvJF^+^aN{?USKWK z8>~&X1?!MLU|rG|tVjBR^+|uQ0oe|0NVW$XksZLsWB}NN3T~C$Kpg1hybM zgDuHmuoW2swkAWtHe?sjlk5t5k=;OVvOCz8>;d|aJwacx7wAX!2K~uCU^}ue*q-bM zb|CwM0ptKMkQ@khBnN?=$iZL`IRxxX4h4hBVPFV391JB#fL+LuU{`V!*o_$cbQIauV2&oDB9Sr+@>8j( z8@Pzv4lX8lfJ?}o;8JoIxQyHlE+_YZE6BazN^&2#irf#bCJ%sX$b;Zo@({R=JPfWU zkANG0tKdQM8hD7j4jv|NfJexi;8F4xc#OOa9w+aBC&;_tN%9_eio6e= zCLe%j$cNxr@=x#_`3O8u{smqj{{}CTkHJgi6Yw(m4|s+A7raXT2VNup2VN(if;Y%# z;7#&5c#C`i-X>pycgR=ZUGg<}k9-5(C*Oh($ammF@;&$``2l=Hegyv_KY@RfpTWoE z7w`%B75s<%2L4Na2md1@MaAb|GBWs-i~>F*UBKt0EBJzR17DKv;49Jtd`(6L-;mM3 zw`6qi9T@|BPsRj4kg>pzWNh#g83+7K#s$BS@xZTSeDE8Y0Q^oS1S56i=U*@~nFx$R zCI(%|B%mvq6m%n#f$n5-(1T0?MkP~%(a2O_bTTyX)B-4Vi$aG+AGCdfF%mBtE zGlKEROkjL6GnjzP0wyH0f`5?Nz(izrFfo|}OhV=alajf>WMpnIIhhAcLFNThlKH?? zWPUI;SpZB!76j9hg}`)VVK6;e1k6Ad1v8Sxz)WOuFf&;K%tDp~vy!F2Y-DLLJ6Q(I zL6!w`lI6f$WO*<*Spm#LRs{2smB4&tWiUTk1uQ^T1q+hZz(QnourOHzEJD@K ztU|T~tCFq2YGiA$I@t!SL3)BUNiVP#=?&H<+k$mSAFwXz3)Un3!1|;=*nn&YHYD4F zjmQpQV=@42LI#3O$&O$%vJ=>x3<6t_oxzr5FxZL=0b7%yU>mXv=t*`3y~u8$H`yI* zOZEVL$ey4t*$ea|dxQRDAFv(S7i>@V13QrY!2ogq7)TBTJCcLIPUK)Ph#UfTCWnH- z_v_Tdy^BuKIBBOFF6V9M@|O& zlT*L}(lSjY}*4jFL?>vM_vZ^lUKk4c?~>7UI!18H^3w0 zP4Fmr3p_^N29J|>z!T(M@FaN;JVo9IPm>S8Gvq_?EcqvRj(h~3C;tL3kbi?0$;aR& z@(FmE{0F>3{tI3u{{yd){{yd+Pr)1HGw>$)9K1!o0B@5o!8_zD@GkipyhpwP?~`xA z2jn~OA^9Hsll%ZaB0qwEk)Oc7$PPLz9(aXAIMnXM>00}iHrk&CgXx% z$avsaGCuf?OaOi-6M~UC@$)YjnM?#mArpfxWD?MoObWV@$v}59Ip{&A0HcyA!DwVE zFglqUj6tRWW0GmXSY$ddHklrbLuLTuk{Q8xWF{~^nHfw#W&snDS;0Sq9+95;7?4yfc+F~DD{K^*lwv)xLCAxU}NqS=o{d^_9wXUBP z-ZAUu-Xr_#iXSAqd;0me>mc|jaP{=l&L?z&b@6B95bb}F?BeM!>8q7(Bj2omZG6Y# z9@2>9tD9@5<;W6UJOd;}v4sKN5?v&^c?NjvVY^Cp*Q`5tz)M6w%g#l;#{iigEIv-lES zJhhO(7TS11i*}a&km%;w-L6t1>*`vGwczEgt0l1*tY;yqcD;hV_2eYe?CsaCz2xM` z!J1QO-P;zYl<4jqfKDpHN~vvy0BfZ|w&iIhyLwwpr_swtk08B7m-arAGU&qgei}1M zbPMR@tvQoqcgZ%8S>T}v)}bsMGGtYRgkq&^+EdtC*+s5i{<^yy65YJ~ZPz((XKEdbYC7PlxM+VWSO%n4bh93eIYp%l{}$Ikwg9h?9ay9k*v12 z6?JmDVh4z00V3U>4F%eIIzMAaP>#&l$yN*-3=;AB*=T1vtQ~AC>m+SB1PmJu725T) z!7d`ZetIIi0>SMS-2{65G!%z*vO3UKw5iG9Ac$jwMRxsky&*QF2dpQ4C?toX8fHZf4Hsa4Ha3D} zb)>DRlhYMPK^z+`(*4=c7#q_0X>lwh2c{ZlMGlP@aDF;Afn;@}t*GDUaC)tR=U&QAwtK^&Vcvia%I9D%Esz2451=;jq* zFB9{0G0wnzUEJQ!&c*`C`h;y*D6l7N(;^XGCX9Ry z%O%Tx^~hG}V%e|em6C10id6#aSG8Ki{VLaRFxb{xtFry-*gCCZzsmJO7rTi!NRpQ) zy`MKq)R!mCn+wz=9ULEZk?2+t>8)mOAZtrI|&pyd|REGTmJ1Wxw5zdA2AP0j@hg7;((_yXJ zxiB6P%6{z{9F^=Y*$(2E4)6)*xDLos*b~eNf$kYPDY89-r-ae;Gz7z^IZU2W+M(E{ z&T1RSVm>F9iR(2wFHtA1`GRDdxZ~_5+u!);)i!gEH9U&)fzRTfYtb0#shhn4mwT)vjKM?By z*kyPq&;!sZ{HX(a0E$Nf9DwRC5f4E5w=nDg)Q>qV2cUeS!~rP((KZi2{jXTgyxxib zNz^m1`G1n_%qyM>aOPFdL_G7#=Ny#XiC(C%H_=P2a%aLA_tGygWm6{vMKD z>=R2=TN>;cB1@xb-Al5b%jkkA`gtUVcH8R~VxsFEDmfOq-k~}WTf4f$I1*gF?K5p$ zElbqh#nZBPTVF$bz|W9C;Njgi07D5WjQt^U^|nvKi6pv7)Qu&U?C$M@HIe{WA*sN_ z+lL!VMqw7}v7epojxfOXReT)qAD19*Cg z@^Q|#lYvHQc3uF>HyBb)- zPFhW7J(smm(f!rNV%uFEIuwKU5H9+5_1vEBtECAtLY*O8-ap_fi&G@@RcF%sPa_(VSz zz-b=`;Bt-^xCP)VzX_6E1MJqGhz>5sB!NpnTiNJjYs;M_d5TqdmrcchU7%@_T?6c~ zG94XkW`@8cKyMd4fiuz4smzk-VsCtATi*wF&K&D2v_IGS_)vltwmKgzZgl}#y48gi zef6{~lIUVrWU(#u)8k(v(JcTEuBFI!%*#;GyJR^Q+cVn=W<9qnCA-Tro?WU{=<9w~ zqhqffYnZja7JWQBtwUdzuSdr=vq7?py*Jxv1%KV(CPaNE+l;8IZIS3EZw~c-+ls|H z;cXV}rC_@?0_??S2eYoZ6WLE6J-Z~k2L$-p_1?_^o%J3L*u#CVz(ZP?>ps@>*!Ht# zZ&DAihJ!jNat*M_9Ksqlo5Rd{Bu6C6-qAk_;Ng2L47!u!VbHmrAnXx*G7MTf6$Y)H z7Ptn;^NvTPGq$`V?x(W=9t7tAJP6JU+yXk<-Frc@Yd}Xm#*66SKD%TH!lo_**whsO zo4P7+3kb4JU6bq@5Tu*Bjt(|;L*QbcG;UhMF61r5u2Q}&(JdfYp2s{Q-I46BS+{bR z1Dfwib_viIs{2+6#gRP#aAXe!t^x8iDW4o9x=GXv{0JQ!@LwFzZT^kE#>eR3fS*{W zyS?Q6V*`@4^)CkO`QSecV9);(xCV6B&Qpml0eXWzvvyB=ls!kb$MXwhYroVSh(Eu) zlI*ToH}e_;wyQT7z^>j3Tm$Xc-dP9z_sG`&V0}JSeY61|8~9`cl64QCZ9x7EBl(MD zmq5L>zDjZp#GhCYbt>O2+EYp-e?4NnmPVHB5~yzjqS(?9J1iH;?tzkZFRmD{-Me7` zyLZQcJ=u6jb`1>C3l|lO?ZQPvpMPWtgKjkjTbg4^mX$TeLewLUZLzC;8j$E7*cCI4 z3;5d%;|bgXyIPKq74&Q*z~XkgorK8t7U>VmxJMEp+k_KKb`Rt|l0*lpknGyg zW{^>$i#@Fcl z6vvyJS&tpHmCjLfd0uTd2odL>C76>dSLc ziS82Z38k1KxLt^s9(Qqphr(Y~B20DzmlU}M%YW=d{%j)AO`?`cOLhR4>^ zt|8eaM9)@DEBNavsAUUv0<~?Sy)CLE(JdsvreBv?w^k3?9%uDY*XcHp=&p6`G(^V^ zsu2e8plcikZ8c#_b5jo3K{gY(hS(Wxj*gwt7R-9bv_wT$ZH2|QW@{|gNwu-Xo$Uc7 zf9#cmldOGtrzaEZY^PLS;dKD#v@L+gqmRJFo&@AAkQ|M@iITs($*RGgI$?Q9wyZ}Z zpO3VnQT`gEQBP(EH0;>r#a!F+pM>>@B+rYQ?I}RMS(Dx9%TOmtt|6iN_zto{s2rR} zq|VGbCHW(sR`gbtODNk2ZL5nzu~@(M?t;ZWy0|N{9KO7dM@5gjyF~ep1)mRlV7XR$ zqAt^txAExU-9>K>=r;Qx+na;F$Trn}%=+@%U$X1~ufGEXa>%;wKoQG; zJ@MvUqWt&CZnK=XFVE?#iLV23_SOTe{g(%=-FznprR38Rnjn&q{XnYNwTRh}t-h zsD%p>UA%Os7j2>K@)Dx%@Uo5T?ylIvKs~8fE!uppA!_xyME!e*p0^uVtlPbb#kS#F z%v!&Vif;N27TdP(VzD0aJw!d?`)Jtv{|8vCNBtV!|DBr2$87iJF_tj^V_!2$5 z^_yNjRS86HB3&b)t>KHk|ACskJJ4Dp)NI3vF(NN!I+6q<_MDhhvb(o0cA3m-`W3L& zl3UHs_LIVDe%Mb+)^JHuLELLsytVMBHgW(t?CmN`uJ7|#+e9m^_;s++_kJzMyoZZv!NplvmWgSu)?p_{C#7de+? zJ?2n-y2u>{ZRHW@F^AeQ=M5Xu&F2dnvaRP2m#$VIOm@r#!=+<|M0(7jIOf9PgSyco z;e)o-q7Le+#e{Oq!FryHOO|5}w)0#f4B9FwkYf(Uc`g+;q?<1tHe_2b6E0n?Y?$nr z%Y{qF%8TTfgL$4Sgb(UQD~1o+Rx3HEt5z23G3$A*B3X~w&U4i;Xsen)j~VB=df1R| zzDC%PZM|l=bhTPxvSY3tE*+~Q(qra%t{Xn68?6^UXj`rCpsv~gT|SB$iev`%C~72G zW`IXgW7hESXks1m2=?<1N?mfsiZHEV8*@z7|&tov&zS$>#=3)YGQdYG*_UCR~ zcd&P2T`ULK-^;p6mcK6H2Poabpzj;I3+&Hl_T1hBL%ufAo*cqddxcAnueV5keiR0102-RfkOEem~0qN0D~OEy6M4=VcYhQAFQhn73*|x z3l4+$d_7!bzhBjxZ3KsKyNwK&Ze*0meq4lGZglvd9>JLKK|6r44(h7o!fBHm@1TxO z5ZX`Nc>7Is4C|&RIfiZ9lYg+TK1FO3(A#jTKxWFPg;gZ1m-xXqjQBe0bZSXj$z&Oe8;eDd%+LZ)fbBGkDPi17726$c#d8iE-fw* z=>+&Jy)=AK_p&T}&~~!iL0xr4IBfze9n{fPLY+X^bM%=wz zy#nh6HUWFW-ViP=ZWP%Ba0NDn59(evhY#9Lwm7J(ZVjhRV4H(Fx?N}!;1$^67}ibi zbPU_Jcl}^peYaTuEN5cnoqsPJrZL7x})KyQgi^udyksLK%Nlp>=QgT`#bF=`r&*dmTQg8+{W#Xj^^jpsxB(D3?MX z8Sf>^;oA{^VAje<$uboj?_iPlT1{}^3O5!$v2uU z#(fl>S+^cTviv$0FMKgMpfilc0Xw4DVbE3L5H`cOVbGCy0{KlgU+m(C4e90*gbmsD z5{64x`vb+ccKQX6+|MA6F$A2XrUNIbi!p5e8i)C1J;$DhxW3 zS|G>FtCA*cNH>=@Y{<5kE?l}=dXbxVh_~hpwo(W_BxV%2dWYyG%7jjkes_==*}g)~ zflizFUVTVZ8A9C4Q3dMk3s4mEMzPqA??ROKn`rFFgEn2;Y*8TCE&{G$; z^VCz+%c8fwthIEr)c_J8p>Ot|8hVDp`K;tCeB8SblM=c{sD)Wh0pN`^}N4>*7&}x^%Qem-f2e z7+YwY7>lUYafn(SZ&h75!ICbUsKXuX4}Fs)x=GZtKN;Ch{uHa&pZuoUVmuV4S#B4o zmvg%10LwEZyL8Y4nkmV(L!jOWv#bzkr+zjT>s6Q|(Y-?;?#H=Uu1|vV5cSLH`4Zha z;4fbbknN}zY9+u^&*>svEKx7oVl39(FTrB_BiB-7dj(jAioTdFx5eIG`UJZ|vixYx zJ5*m~Rs#5@cokZ9XRSuITWbxnt*{m=gxVi0*I~eJ(e;w$7ioH&8*Fh~TX&=N+xpmC zHetZ}n=yc!Yl{u|*q*oA0B^x<7_c?ATlTe|YwxgAMEWCrUw<1sA3ms;`9k=hy_>k`psso;ysNj<yBaD(~TdjtKW3gbzip})W^VW2ldf=$3cAv-xXr^_D7&_Y4v`%^ilmFd`0`0 zyAK`IWB5~uDd6ALK5`7}6#jAy+Z6u(!MgfmM_s4z#4&8=>z^O2^?$|D?S%0kwrPI(!MgfaM_niR%`t4}_4^Oj zdZZ3GuW~H76C=w4?%qDuMERj$J9PPRfo{U}hc$GUZa-MhtNRbuGv)Dv_2fhq+rNwP zw?Cvtb5PsS9n^9Rq5bm~-BU~f{(X%qR=9M%*x}OE;)JcHLvh1~f_1fcBL1@+Wqb#< zo4`TcPQvh2b?}dH=~yC>9hxFBhwx*yBqH61NUwNO2lWId6Y43KQG3!!?iki9p29I~ z7a-*i*40xv>NMg6%NFj|+4Y8Gl$qcbVx2 z>lM%ZgY`UR`N4W}vWj^+w4TjDZD)5-%Q=L4TK)BB1UUtI#c>{Ug-eerci4J3i+REa zby9i52W?9E9Mo0whj(>41;PjI1Qv8qyM=^ywRrjpJBD>fMI6Jnr=mYtS1;zM>%NLR zsHdWYgL*1TI;f|jln}GmZs~AowM@9QSyrU~B20HtPO_drd#hJI47yH*Fz6~3xrz={ z;($FsDhqV4!M1@a;nHH&aOozhg{`JT)x)48H3WJ*nrqrX5Z*b}637pa^`*Wxmg7ae zj;#=6A5QBs>uXXyWP5?HFIm>roi#x0EU_UP_Bo}IWcPrekZ$^@YYc?i$Brgw*_(r= zl3fGv!OIroS7*(c^$kZ0WP6X%64?%+6>?X-vaKb%2ZUf=ZEPUaR`9feP<%G=!ho&q zjcf!j9p*=b}l&7y-zwxaFyRMOO($i_S0rPKN=pOcis;(T+$3-^|*tfpjIiTC`A=xER-`@AMr2FqBNq#7;`|NF1ybJDw z#ky8sEVj3i{Uo~w%H;KomtnD8-sO_zC)&8YD+Dg~8EvJt?WS90ZQOIKu~_G~ z28-=Vt;J&9_BvhMv7M*Bo~)Pb-Z4~uqbb;+13{j4o;D)e&vQ3PcCn8|n(;Mb{(eby4V26fOIb{C?a_T3f(bj>{y zJ%Ty~d3V(MUK)=c4bIkf|b6&E0a4?>-E&$luMQhTLL%Pmmbn>>)7SLgT?lUyNiB@Al>slflG)! zitk(d|CoCZ@G6Qf{y#SfMFa~Vkle)FdjpFgqezh|0!ot-ks>0N0HH%52@y~+^!6fB z1VlhUM2d=vqN`#-Uj?zEFQR}Ath^R1SdiEM_ng_C*-ds=*x&DYet(~5o%zn0J#)@y zX3O1sv+zOu8TXc{e9pbClhI-BO$YZ8?#;*c7u*9Mz$ut7A<7lX=Wt(fA3pPZ&3&xj zn|@;nUdZ2aC%%n5ifXyS;ruM{zgC^5;ydobe+KwHH;>|L#}8JW4%Z)LeK4)4V^*DL z{$$l@_56%_g+lvBufN!eqxepIsHYb4-zxqo zt2Dp~S*6E%e{ppjaXpDDelyNs|0kOX;NP;D2_}u=E_~gLaJ_&t!QVh)*8=_%(iE#s z1EtD3-@lYYy?i0=W#}PJd0SAg3J~}?IT5TV+Y5{6s5}D#UOCrFY_Ohhp2-IJe6zBw z^LGhVWSt-2orQX;{FUw5++37POYI!g@x$$0K9ikm8EE9Hvd)XJn(Q=)S7CKq5RCI| zK})iRwF~*JX&LzGWG!3J1uo4JW9ihLZixbVm>abOp93>&L8~DX0>6A8LiO{dVF+I= zvMj+T#h4UB`H~lxVmLqaPC(!n=@eKts&K_|)wb#sRvp=Y4FCGYfZ*2<@MD^~Q2Y`E z`JCngE$K$19wfg9!g^9uUz;i13$>XeZs5?gyU^V!yod(eSznH zbg~3be`g4+k+F0a-^Hrafq9ixrxQh2xr4kL?q&(T{q8P>yl(W6yYN*iM;hea^wqYY z3w}?CltMbjuR$%fkbjBai>v(CXT8}@$4DP;6CgM zM1`VUyt0Gh?@xQk7m+;Me`wOTH-szc8n|{5u<2pFo~*CWN=agZQhkJWJ$JOgN_5!e=$SMu-G{as|sU zOK`X0mf&u9@eoGI<8Nd}vSFCKFUOw`!63g&8I5{M5lu86A0h3rbfb{Zy~h^h(*R?+ z2O${8%>}vqV`O}#gCHPiX7K(H7GoPh;EA~uO(4cYq!#f5$zoK?6&2*u;c$yprvWC& zE>xW;oB2DINmiY@-)hw;?h}7}?UFLLDQ;Mm_3~DUSrJ0#2t2B|bP%T%S%XgKtQ7=z*>NCd{)N3w8 z1+omH!(*Opq6@&kY(eDa+k(zHciMvXSpY%fQ2j2{5eek3=YDf3<*5MJ`q;MLt$5 zMNaNxHE?VmKb=?uRSutesNY)D%Tt}`t+NDw#d1IIgSW)6X}#Phk5YO-cFP+_`)rWi zAZXSfv`rMzM%y%mOq*;I4ZGPk4JFeS+eEQGWSfSO>0v0uI+Sj69+BPfgLR0l5UIs{ z^YEzbGmM%alYNG9G>=;b3TB&S;8>op3>32SuiaFPr@@0 z6%fZL9`RY*L_CN#eDzsK3DVT@cj>W&*S5IpH-)kKd|aF z@P4aK<9=w>X^K8Vy?k-rAfBQFwxGQa+JbgJWDDB=V<`%T)0O%YhziAd5Crj4rO3r+ zN|BGxl_DpHp)j!ggWDsPX%vU?g;M0?OQp!kS4xqSua%;|So{X6BD-Xy-)c#Ij%rDc z{;MT<`VO*OaUQM>_%a7|goeL@h4{f1P)Vr4)s75(-SR zXw{iKMIbpGf`Z3*oKpc)Nl}X2q$)*T$|*%o$}2_TRDj}eB$|p^lAklQBuACBBu{5T zrWOyOi(O?@%cIIibQOql5cJ{YEX%-mD`!JgAOoLq&aq82(z&*Y&p1_W6Ae?%Ht}ht zx~=%YJ`buQd7Q*9YbYc6tf`Fbw3afG*ED5hx9O0SKp`!$CxuNC1G`hA}`sH7+b!hxVCMR1J;2&gKe^}q0BsF zU1gSIUH}ckgNCuSp50j*>qBC`=p=R_su)tft*L<}cpm|QsQF3iMbaSONpUd*TtiUI z4Q&&FzQi^$=SH@P5^rpqm~s{Y|RS=kfk#b>lg#tWMlvp?0$X&bJMmh04 zETdd~IhN5{eOKF3`t1pc#6}LY9ABf%?75dROV_=jDJZ$%`q-VNv9C1J+nx~OwYFkM z{h+YUM$xJ4I@FQ#s8N(jf2$kbjstbQt$3#amcr|9V7tLqY`YPP9MWC>O{kN@0$S@g zLjW#a8}T@X`tZ+=2BMD0t#`WM%QLCi*I+2@KRTB_h2}wkGz5 zvfyXHxEgcE;W88a4$G3fAASYJp-{^B9SrZrhS3ldmwaUfK5k3JwtU%f3@3mmY~&Dv z#~!C7cg6iO`5ePANH^KHqK*XUwGdFZ*^2kS-P(!8WGRXU(Yn6_0@*g9{^do~LBere$PdaF)H;{&pjJlSlp3^c-nR-H!JXw_+i zP1X+lS0kHkL3?bm1?}>XEoh&IA&}fqy2E)y8iw-i)>d24{*T&%_J7P4wEyD}*nc>E zsMv-&;1IJXWS>!a^a0~Zhze-O1psQhQsnt5rO5TuN|A39sv_^lFT;2S67FfiJS(d- z=yRwdfU)FyhgB!X&s%kJ`+`*`r!S%oFLdsE302HOK_2(@{xhwOcqH1I=#-O?Z*3cPL$a=phEeT+H z)rrG6VGHW@mo2Eym*)dGv3|r9Nm25$~pJ@x)zcK`dra7&GDu(7*&$8;Y z^VwFNx}PJv)6sOUY%ZYYs;Fb+0_IfB7PND9ThPeo*@E_|0fFK8n6GIWIPzMyp#9Tq zLHnoMg7%L>V1NF^o*@l|{5&qxGEk7`qmK0GzA8&L^Rw%iRi_c+R-Fb&SatHBZPkfv zZPbz91dgwcEog7U7PNa^ThRU&K&0@G7V4pvTFkF}t1qiG(-+Drk#8WY6s15lrI;Eo z;zoY)+Qq1rE6(T78x6TWb}-$s2!;4b(P7j{OB%bgmNZ@$ zEoqFaAQ5I^KCPav5ao*HrL7wqtSei0Tad#Zwjg&owjgI$+kz&mCqxBu#&;IiC`B%M zDMdbdD@9KFK&2M*SI2!(O(`at*K#A@tM=pGg#!l-q*1Pes#wg5ZjSpymV+eI^{AJp zIvEB?A$Pg~qC#;Y1o662DGKc-r6{zUm7>scl_Hk|q2M2{d4U*Y3)*Wi1ft;QmU*(y zf8H}hcFN-i=lE?0?ViWK*T-wEq@ZE&@rHKKqa$$y>Z!%Nh(^jP4KPYpsWZ-^)Peer zK^6P)L7R^{ypQ6${jstSP4PHcrT7bEcYgR*D7(vNZ$*}Ye2%va>=Z{g4Zw4A3+fn` zzax@;iuhVL(H2Byk}W9cTWvvM-v$9!MKs3kR-JCrCR?5O-{-mm0`pW`B2DtJmq<(>^7c1zAUf>VY*B1Gk!ELjDUcR%s__5^b9@NWIosNeUwjfXU+Jd^Rv;?1nRzcAI zG=r-x1Fw?%Y(e|4u?6kF7NP>}!sDz{iaOq}6!l!M6y0Jx07c>Pr-Ti*i3fX7DRQz= zDRQz2Dy5jNGMiB=Upy&~|JYy)iCe61wjQEAAmo=>4@;B$=HwA+vc5;z$|ma(?4y?8 z6VhXr;4AIp5UIED+nTn?cKLMX35W`4mmkcYgsLbNE#>XDk^Mbo8|71;r)?wqH*Mnt zJ_w$%jPlXbvzF0%^z@u9<)Awt&%mJeqo?PUnTLHrndP`IDl-rKk}}JYcS2J_^2yZ8 zc4xWoE4Gn${kLtDd%g-;9((eruUUdS?vg@2Hr;Ir?)JJRxZ55nUkD)0cITfGSo#not+D6{>GutTl z{2UTfF_K3;YzgjoMDAuiTl~US-0@3WanG;hZlm~3@n745mi0GQKly;}TU)V@qqbrn z|Fx8S@c5mrxaaq_;+{W1A!7OH@kd+GF@8+;vmV#|WGnXZv#r?2FHo3r`-$VPN^;-h zN^ z%Bby>FhnY*CL7j220J5(|IOjLmYgZ&1(qz4vYsVpNm<{Lv!%Syl2fE?V97aB3QJCv z@*+#lmGWXsPLr~sCFei)KA!S=j-YaE0ORki%JtRJH z(j1Q%Kbr1YFik1d2M-xbKP=B1JScw*zWpv7o=+byF=Z*$V48%FjcyBOFQxKeJop_x zW>8T+|7H_2m{KKg%&^=sxF8SCEuvpWVH#7;%A1fkXnYYo;t#s$))teQQhCT&yoxbz zj5QD@H0A7}<8uoJ=i#l9`S|r5J$S*qrkpWs_|RduxhDjGhPf7OV|PN{}r@SA{qN(aA3$}23q1kNz;DV0a%=MK&tLqC3|%rW;V zX;u^6#}r_wqS5(UqWAgIH z7b@^{J;B0DN%JvNQdo&8=ip=T_))nug@f|P^BiJDqPYP7N^W5xri-&gZ>-FeXaTbK zogggMl$zi_2EUXihj@5tFAwaGwTqkCJS-`CER3a_Qe7%*U5(De-$KxAVj0^exo!vN z4H}N8kuY_WXC|DJ&c&9Etv0qg*bHoSv0Z?z9=7_}F2vRVo4|Gvwu`Yf#C8d`M%Wr- zYl5vQwo9=!!`2*I3v4a1wZhgK+hy3=V7nY!TWsyHwa0b^wkxr9z}694Cv2Uub-{KO zwyxN^Ve5{q2euq+S7Ymm?HX*ou=U2)2U}lk*JA63?K*7zv0aaC0Ja;j-H7cbY&T=e z#WoOIRczI;RmXN7wi?)KVylHM4O=?4D7Fl2nb^+9mW3^bEskvvw!zr)unoaB6x%Rt z!?BIPHWJ$?Y@@M_!IqD0EVgmj3b5JZ+vD2f+2h#u|5x!v5Mwg76l|&3%3&*ytpc`+ z*v`OK3EP?2Dr2jH?JR6(V><`i{~z|J*ePy`nc}5bDbBMioPB*s3C{cf@BYilDoL%i zrX(j;^1q~<##M$?&8V1Cr$Wglis-BXRa5#_PC7d$`L0?yk^VW6>v|=j?3H9Js@1Vu z&bg$n&xs5$?yl8t_O$yeC$(H$3r#olPVOD4N7bsGdMEWR`5XV8`Y?lYB7?~BU<|WN z4U?A>8DgxkhgnX;4CP^{db-0bKsF^!B1v#kav=&Djx~n7Cat5mI!*LQ6W!9pRcTh1 zB~8)IXq>iVX1k)Kl8WafC7D;J&7SsS($z&xo1bP```n(_-dTs4t}Y zlo*ihU`8c1uy?nHv!`bF!Pc!Ed2HD$jY7B-gK$zLLnYN-Ce_kTiZqhykEHsgiN0x~ zx60@Wn2@c^D2+1er!#7d@GB?vp{&flG9k*!>@5?btgOhd=g6;wGme~OsK|T50}yoP zfKefh$ny~Spfr)2CT>a-H>lvRfz@c^oQ^>{crzDK+S759jGm|C1{wW7Psb2Wsuu>~ zq)3KJDivD1 zgW!xKCmAa80(d~c!#QA7NF(wIh`cyW6s3uRG%;2MUkIzw#W@|tI(V}PQQFf{AfxB$ z7%QXy=joWpNflubPKsoxq)OlcxlG_(P$7+^N|4m#G;v#+n4~hA0u!=zOvhxMk#jn3 zlL_&3Op*yXreg|6J{8V5a+0AUzY`u1@JtRE71D@&4kDkGCT66GX)5vsFu9NGSvqoa z213MK@PR!|hi{oKnhDZ z1yo2Qmj%dWewvu45?P6McOvt3BF-t8cY1l;#d)lPcg}-ks5~~o1Hxa+;iEztc`QdB zOVh-XG_gpfvKc1#!M#+cVlHva$)eNCu;UGRYLU*zynA&op9L>>>MiTl&UT9wLf znA}JB13DG+e#e}wJ-u8uaxSmKJ?BC)R4)I42c+;8r+^A+^$S^iiGof= zC5Lb?+IDJ%6!Qr=E3=d4#0)bH_f@N6-MYf%SLkUxo#sAUn3{sUBcJvj*BH!4QO6A$ zpXC~1D022SIWyBh?#IeWjp+Z4F?Q0GWcvm-^XWA7l=p2cV)QFK!2S0q z_-2$e7`+5WFQkbb3ea)c?>AZej=~M-1)1CIq`P9qD-J+^pr`S2DL}7iK+a`i`QR(s z4i7$mlCM|1`J8~wd|C6^$$b7oEAt^4iciI4=97ei`H%*mx54MlG_fa5>{f`*kXCGI|>Crn%2#i zDL{ubAm~D>yS5}1Z?I(&F28~$wn*lAsLF#CGY?~^-wS$(%|zo_Oy(JAPq`NO<$?5t@gS8_spc4`@ z0SdlQhOoS*4UYZPo|B~9xL zrZpO^Op9bFS`**_w8o)eTBJd%I%ri*7w0Ho6J@_ivbYt68(38Uv)5Nm2e8}F)2NZ| zzR1ZeZZcJf}+o7iO7%o>{5c}(mMv@$W0p@_|c2N0Wqf{Bp^u}lz) zDqR1Po#xBpP84ojQOEjS$oIgfeMS_qq&rD>hdv=*V2 zX^{*?>ppk@t>q|~7HQC`2U>O0MI8lfjqJBp7VA*Bfz@@auLcfa_oJtAVY>SQ*gyj_ ztsQxN)j8euwVu2;@Fw;EZ03cUSbZk80j*4oWGG^f!UKqHM#02LgIFUFYp8HNCObVY zi)|>}xEeavS5pVBC(zSqQVLg7jmx>dEFY)7zMdrKO}%Mths|uFX*FhAPob4*kqkxa zJ$L}E*HJJn(xBBHw7RB?F6p9Ey6B*=y$`E#WxC^`dRLvh*~MC8^iaK%1&|)9cR<~K zsJ<-dp?VKa>H`eINs$bd)M0o)QU^E}R7fMKK1ixpy6BlMa#Th~U_!Qz$A-OhM$Xyn zDHEdEG;?G^jz?{MIr1;yj3Xx*D)OJ;0Rex*0i!}1k>8BSZ%h{h(nbGt(N6{cGpz3E zxKRgh4nUN2NulZJFQezDxcy}G{1mtBbTr0y91(m=qQ2?K<VMuLAx)_`;2CBTu!GxS0lQKl-<(!nkGA*8zfif+}qzvcC%flH*PBK*F)nw#n za=@4r(ujNm1A15!xi6i^|JTy8-w7r43*1e@PHI9j0dCX52 z^U}o}l}ZoUHAfa#qi|n;=gV2)XFiJ@*WaG#X)H{4ugpc7f@$r@huA!g!JLD7>F0*m zkh4YJ*V|sOnG5yx_AX}B8?DTUWGF^A!2{6rL&4Wu(qOa#jFzX1r3%o^vR|$&2BL5S zS}t?r4_K=lfCizbv9c7PRT_|UnOHvf?77r~&tUSk%9~FfZ01VM=U(PB1g*@6WGFrb z@Bls|P%t0T;Ik2YHl&O7>0+HiR4BU^$znVTH=+$l$^J;S#et|8J&n!j?jvc7Mr2w$ z@)}w%IWwbm9*k}wXIs1(O@PhZtQl=$MibG>j7WxJG!q`c=nfRjh%^{&1Ea^%#a0Dq zmh3lM7IRRz0X-&j<2AJ10cb9I8c&u2v|R&ot|7|@^V#abXCC?5?#<_4u$fP4K2I>8 z`DkT6Bt!980T1A_7zOho4L&b`&yIBQtm1R8?6*=Dt5CT4>_9&D0@~@|vl=~(mr5OD zJ2fBE+L0H~vl21^3ck+U&wTD9?>oJTt%1#aNfUdKiLFH|6C)Xl*cNyIu?J8vG14Hm z3&dVkxE_+79+t%;DBQSSbu6bn4qRK&(|ElUu00x;b2(W)PMy}HEay)?0MPm1zEg^!VPS%V|{(#0QM4k8v9Be ze;;UIrnMuluXj#&eeERgA9xdc88&mDCiWjD_6k~=7|Bq?-hl@YdmRN6BMoAQK0sE9`Gr?Cb)7G6@DjGyZ z{iwJ=foY9C#-&lCN>qN9Gzd&12bhKqFc&$%G|*t`>*@u8jQBINqSF>bo0pcMBU?0` zrc9?DIx`)Tq3B!<51`W#1=Ar7I_*H`@~F5hDq2NFi>PR((DXzHz>{3+5tqv~7v~{! znZ!bi#%v{7(4sM0IO@$L7+OKruMFFBUe{m{&WmKIyoSRA^17MRL4`E(>V>@eM@7G= z=o=NiRZ=5h#c?8&YCuW#_fD!Gny1kxaU|6@iuK=zbLx%eW0ldY@)*E*jD%m#gJh^Y zrojWkpUB~(LK=AtLmoq-VsKOpjEbA1;zpIqbaXIAlscw|=xofvU~WI&87Sw7AMf0( z*XxaPT6~Ua_j;X;@yror)~jsM>vcHun1jyDgJdWk%isYR?nJ@sl{9!1g2%Y1$d8KA zQ87}%SPm;#Ip%eoCgEJH`4R-r>uARU9VtmTCbozZxd)Cp5t5-2*$59vWHrZ+3TY%# zfm!Z3!-AaN@5pG?j#oKB%DiYfoBf$%jB?xbJz{H zoCC>FIeY*Q2>mS%9Tn2Z;XdTBDk|=cihH7BnMz|ntnO8{$~%pFbsFY9jzzVsOd@MI zkq_aR6CoKYk+0za@qf(mqe2>qJcL9xN5#gd*bo)#qhg)PRTt%Ii*wIcNounq|B*Lw&+ve!_4D*bY>nTL-9BX55VvX3O@Cb z29Kw}{dy_aq4@T6ZspCIT4bf z5~)>=6FCb7Cqf#Dyn;k_M#YO!@qAP~7ZuN_T+-0Ncr|LITj}t9>Q0@G`66PqC-!-n z4^QlKdSaiE>73HUW@0?^)iM(+TlB>Kn|Yj%&dh^kC>{;q0TY{zf_abzkGH|&&8XND z6}zM2H3dV!3RaGZeN&TgPV62Df+u#jV`5*EBpeg_4kvOE9CIQhLnYD*9*{_5jvp1$ zNMt_}*%uY>N5x*1MQfOhk4oL9?9+*u?;}ckO83f4XiE7L1KojGnflBpT`iL3w^91e z8bg{Nm6=u9qG$C(hS3h483xHvFuKD77<5Fzvq~B;J_U@AqvD_<(F5&3B1$t5^YFaze!D=4YnVP?#j^_e= zma!jEP9Mn*?bAw!hQ z5GffVl3_m)SuA@mk;UC8+?Xn4$g>h*s+^%QEk#e`%nbLPROJl)B*og1F_nW8JW1gb zb4mt3N#ReC5ww>^wu~HC&hSLG95(aJ427&x24#8=S{WJ1P{f` z&8(sMoX30~LM!tj8H$ey58(3{3g$x^d=lUj%Mj;hhzy138QJw&Sv-frjVR_oRL6m6 z2YMQ{ORc9m-iRz8jOcvFa?0?)^*s5lr2Ly%HlH=ZepF072Oxm5!l^9>~r)qx@EX;dAn<3rnMs< zfgL4wMs}qGS$hv;hskkwZ)8VcGrMVIT^ZRIXk}z1Lm~Sa9)Rp93Pwg6$gTylJ{h7{ zhUlqy{UW>mDvRSN+`Rh8RQVw6@8IR%M;F=CxQ!_+K zhM1foZd1fs$=zF|*WJf0ia@T08OzE0Ne4*<=T@+dPn6 zPL5}JBWnwrIa4E>!N}U7m64GQg{%iW09i*AjEpppEd;U!8Df5hn5TH<$gWq*q9+PB zuLUwyUSUfdyskk{V{s{7OEfR%3bTALuK5mJ^E`0%BEL(#arK7HT&!^|VqAUD%D6~| z!ZipUfU7?W#zh*q)&kdk8Ddq2xHm)GqlgWbz4K%-1cjT}eaOmQVe1{lhM}i%e}?Y?Z{$$nJF@yT=3B2y(pM8`((M%=6D4)x4Z5%<{pw zHfN~shBl(N{oRoLL8ye>KI%OpS{jq$EG zy@y~k-_i8mW_k~!mFbZTMejv;06h~0(<2RfAA#Qf46#pfdr9`&DT|j;xVh~|KK7~Y zkb~PR=xH3xa6d{rq`8^aj=b#lN%#b=n|)CJn;abShVm+G=0OeR07H2Vtqg@^C@6d3 z0Z`sR!B9v8%3(nHOc8lcc6whH|3Tp<@|j~Led!>w4?T@9N)h=|6LGF2%ZCfd2eki} z-az)lW`3c89AO|IqLqP=3&x!~NjyC(XpPcH~uZ)MJ%=OAdbWhH?}(^O%P6BSZNwS{Vw-P*8q@2S7Q7 zf}xNGl-~j6xFYhq?DU5${zTy>a@?^>PB@61Ku_b(QbbN@BFMhqi+4iNq*mqtGHQ3H{v~IJN)16RU?yTX(&eH>_~>nt_U9B zXcQ-f3Tb3_KC;Wm6zQ3wmP&0rOh{X%)|^ty(5X3RE*;JG4_9jGy7fgu7DrwTXB;`n zP?1lE2Lya82aF17L|zY(*Uc1lGDUW#h^ydd!0Mitx;l8Xj$>Z3^%UrNiR(s>d7*x; zzelRiInKtIoFmClIWB_-q_%)lLxnVQY=j&eW{Qh4MFW-Ka+r|3V|E(q1f8>UkxYda zpV>gyt=VbJk>3Mn968BQkv|R(2zVn0j0$N)emNq)EK{_~6fH7EvrN%c#lH<5+!J(} zj^AvBK%YOB95H_<MXf!iQMJqER8H!O=cmSg_Q7|LYU~~%@jn5Q?3Q#rKuevPGL*ZUS<7GblX>XDP zP!04nCYAy;Ndt1OACDxX zOlwD8M$;n2d+Ck zaCIcV%e--Qg3Vm2aox?hI-`|wkqm{aFFXKOcNC0^G;pm4u63DWO{Q3#DOM_C*UH}g zWN{q|H?eid%3fg)I*9d0Ph&$S?i3s=>_JV;w07hbwnn2dS38ic)a`18T~Cf5^hP!S zHgkhU_5dTh0j-RTWGG}K-~q@6qF`jCf$T9L+nOmJ&JU=;K-N28AnbsROD;n0RgL5*N{f!-4S`$ zEYT%PbjlJPRPgl58pCi-M^_!Z*#%MBpHVu==y^Ii$mnNJoAM9u>+Zox(c5k~DUzX* zvR)jsiE}}Aq>)q~B-JZR^vn`DDx=3Kqwdb>=%q7qPDf9f5Kl*rOvo`EeL3=NcH|^O zMZOar5U|Msqe2>y-;Bs_%n}2#ME@+&PX+%nti~nI>9|n`Zw^3|_H^`@(erfllhOb4 zbmVeUuV4_K4w9jgdIuhm%P!6Z71Bs*7?K*2B?f1SfhwbSVM4Z!qhpB9$T=N@WkNh1 z17$*v=@`zD?}amtoMfoTKZXYcypID$g)|}`hsg7@#ON$BQbqm=Ozz`4Uq^0^Mu?aT z`ky&chhFxNjmy3ux`1=}6z(|}lA&@r3J*x(2&aGwY2u;Ki~o3ALH;*A&oprkjLaKaa)#{q*D14CilTTS*K#&=9rU7 zr;x0%*zsUR4VjR8}|`DU#DWubIi${)63;9&Lti0 zITwo^<%30x`0j|x`53QP^r?Do>eYRMu zDVWxdeA-)~F__CyFa4sI=HzT`7RZ%-Xw?EXb4`|dXmuYmYKc~6L^2ek4)6dp^v)hW z{z!w-CNO$1OFWzZ^HSv%#GL3>kdH0*w5Hq3ef8s zkaG=LKA6wT9(?#kIIny2;TPfT)_is`AN3*}lA-umFSt=J!Xb?{^dInfFH5|eCEiwu z952BEDSE?=dkwvZlM;r2rk)fShZ{^1*x#dhl6Iz7Biyq1WP=pKCs!F&}y%4)Y-yiq95!0H5_Jm=9_2 z`7iiu-MW zCdRM7`Cb$Ij)^^P6C)Xl*mIKDcAFS!5c?Ixepa}wcjP=T`_e0L+{@`_$8!4Jfs5Xf zWBgVM*Y6sab2(W)PMsFNSm$?dTJ%~R^EXZFIMbpR;_&(+8H(0h@PPI88VX)tq(LhZ z>nQ%t5+@a~w`D);O*!-~95=AP9qTKV9!6RJlEz;2G*V*ji(G0YDxs$lFNG_iaXHtQ<>S<8ok`9U-n1&iX2vzG7}KhPR;EQV z6s-&30g$p#@cJSRS}j4Vc}!dy6HQ{Gk-}CFR^yVG^P#%V-MrLVWBgFv0>}^5QMVte z2mUgv6(`jIgK$zLLnYN59*~rJmlSCv)gDQ;jfplf(OPBHf--7pWh5V}>x`VU*+wQr zvuU=L2{|4cUcr&Kv?C`OD)LS;@-`eWQXq}UyCd?hG0`O^I>kf>6?|t{-P6%k2XA&k zlyu0`baax@%ZKVRdVY#qb~?)Z6s8BK))hnXq>v1iT7P&zM)b}oUTLI}S|6m=D<*oz zM2^bqdYF*2<5_MmotJY`ddjqTQgUQkj!Egukq>|~j+|tu$mz9Hh0ZZbVOGa?HIl@6Z%XYezoBCTI+1G3uqC8*U1A8y zWPQE8of&OGD>EV)iqUp>02=iQF4AB$3yfyO#54uyDcSF7SK{*>jo)pJ&O}TyH+l!Di0Ud}cGB9cX1fBt!Ap4G-Y+5(+-9 zNrTVb;IlX;7RJN^h3IwJb&o9GK;cHT7%ADeyvrSk-b7DhS~izjjC||`wAI1qSM)R2AlbaCiXBB`yH)JjASTc$>o^XUvR|4NQ2mu zAhu26N|BvXWl;`=8`n0+a(dc1`;R}~aYi!^Ax1X?e|#0~}QJlU^?ENY@~1AD=-zFu(vqZh3iFPA$0 zUeUlzYe!yRJ5G0frIGhnyosg5X1=V6?POw6v@$W0p@`Lm2M~*+U}B^}>~#>^rEpy! zJJpj#eH3n7yBzE5O$V+E(bIUN6s|WlF6a8Pe4P6FqL;iGZ+g?BSG<{TXj*%imU=%M z$xyWN;TN>>P%tghpj9>AQJfPOXT?S3xTq8t7322PGI~XoQ9W*aY<*`FYMnul{mq)8ma#H=ZC z5EJt}$%CL+f8TRHCo%($IT4bf5?KuoNaSu5oCs+oasd)C;-Yq3B;q2b61fjnqkgHm zHOl0|pYm%vrZ%CcHujHGTlyV*_hV4AewnG2EqZF}F_HD?%tT0rBJwyqfC#;Ciiwa0 zktQJ0C@vbt#YJ(^KoQvnt9xo2X&h!lBx`@hzDV+*xs`v9#xvVM;&9AtQ_kZF_~krE zhRWk5ct9TVMN_DdMjn?Tk5+NfA}*S#BzD5&PNJ1g!nr7tV{J0VuOjiQrJ2bm2& zhq^+q&~`E%pOcUKP1YY^JhOY5wJBTl+U&+W_M>2p!Z$z+9VAgeZix5 zTwD_uSI0#U1>+l7!OC&k>8(jPr}Y{Mf=@eFJ5D=2Bnijjyp|LB7LGX)lA#hw!JqRY z5qh~3Cqf#D3_>EgadA^z+z=Pn$HjFjmsE5x^5RAXD;>V7D z6MLOZ=aeS4BE~cG%1o?m(GxqEd7OdH%!6bo9yQ?sJkCPFJV=Ab81NVs7bD_gSX>NI zFz8iIVC9(DQJREvVn;|2Jh8(Z6FWqba7=7ICz1xooCwKKiO>t2kjVKQKPse=$n8kv z*0`7$7q`U4__!#Hi*YI)emT<}apOR&+RQTC7#>ydTtAKb(~D@ zl&1M2glFDSW}0P-p61C+=VEkbIwV8UX#)>{(uAR)LK<}Dg3j!?m>Cz-<6>%DlqfX( z5~ka&neItkW@|3anVu=J@Jvs4%=A=8y+nd>%=$dei{9qMd65j27rlW9>CnrVc=^gV z5*f>o*WGckI4%~(#e%q)ukyMcJ+Ua{3g*1-_ReduBd>*yToyR$^ULJ5obwuB=S4D9 zUWGC*dKnStMH=(926?THit}C;6Ws6?CYZ=BwbmmDW84AX9c)%pzj)Gy328@k>u^}$jD-tu%4n%Tp zd()cTpfNbt?0P-7)?Mu;4s|9RaHu3hg=)QqXs#V9X@vS1Lfsk{568t86)nB0$k&9Gw{k$xtxvhX>5tN)$YAqyfVOjHlw_ zNkw8k+JVS1Z%=6q&Ut&X%)C9rp*{cy94g6Bp>Bf*gu00%M1?d$eHEd;5*It;;>Eal zJ}#b9F+YJ0#;#IF-77k5bEjkWUevQ^J}=K7^kMTkH2Z(pbl>kijq%J~Wu{KH=&5^+ zd6?+TJV=J(K`#pehUZc6)R6{{cfsTBxOg)z_Qb_*1!EViVCA?icw3WjPT-q*0?j>+ z6X|YA!f}Dv%ZcoUV@`x*s6^-c`&Yii*$e)eS%hIL^2d3dJ_=P96`a8O&W~80Heck@tFcd?*>A@?_}{k3OAs` zGBXlD*HAMP(FjN+*$(y^N9*dKpzgPa~3We{M=n z&_dwnQKq#cFQXF@HDmh2aUlKXf$S`DoSg7nQfI?vMiOdCB_(Kv&p|6ABN+-=7CgXF zO%#lbG>}zJbQF~mqGCdnPuP#`VzO&o76}w?UX>D*rTmfG*$!UW=xLl)ir3kimvdEF zJ{VWU1V8QLhalzQ8)slX@7PCRZSs4zH?BIcnP+KSRT!6nR>nm#6t2tQ0l1o=U|ghu zD+9RF6QWi^)JTZxidY-j`*K;dMd2ovj;!nzmgOMU4n2+Y6YdXiS(=z>?Z_*vmc-7; zYB-Qp_dwR39A|kWy8<@ze2pxVkzI*aMn*CevYzk&WL;1&GSWa+56J2!M4g1lR=lo} zU3Vuxfg{62k(7c>0%<{pw>Ns#^d*JFzej9k>x)wI`LXE3F z`k1#mS>h^7hAI3X@k#OSqP=sipp!%?`2HA7bR3Ty2k zHWEFJRtfhbz1EtTY3;}>tf|D#$QnD4UE+akG&yeVjcg2TW-E=XB_qp6DcQ99hgo;pTOvOqEwy7YDC-=xKCL;HkH~b?8sG z4qY6)tR0zAdk3So9*q7)&boLrnh%@VSu^UyjP67$Ga?y^(Y^41#22GrMx?>07Z~+S zh@6Dzt{AP9U02CsH3~PQo(@KR9gOZnPoqx)UvW4X^>r|^c4S654o2NQ7_A{^eZ3j2 zh0W}v8TDpH>(I)KNQPo$!UGsRih>!D2BWcHG$tWNCB%q?7^W~iBYV?J!LZYFDBPIF zAS?UOD|BGmfu2S|!hIWF=)h#{$cNr2$(oUka3CAzf$Vv5TcsihhB+;*SqLx+);{G ziRR@zxm!LM*F*=dTRd>>CBG%!xZZ=!yhG!f%(&i1E8`*=3fEzH03~``8m}@-nSLkUhOt>GQEz;0TYe!yW^CWqu zHpfA2mZLtygW%UR$Rclo-@s-r)CBKhg7i)_CP*?A!QbHl1nK2vOpr7Pt_H!C39%v} zmM6qgh3^m9`%hV%K;g!>QfAI;Zmk2~U+8J9DTQyX#^+pfmJg=4!a;1gqrTLG-bor` ztv5Y-F`BtX)4Px9{f$b*w%vayG~q43Mb9@0>@FckH&F_NL6WaCvoSW=lNcuA4QlG+9+ zk0~OxWv4o_Fi^Nx(qoR5wB13ZE_xbImLjrU6LGF2%ZCfd1+@QmZy@wmH1kOf(okMxD6P@TP)LS?LN6&pmh|p4hC&)pb^*$( zibyBfiC#~JzFknbiM;AqC3_r1u0l`a^#q={%3G%!==O4tgNU`GYiV?)o%VQB=mwkl zx~8z3DbU-_m;%XA6o$bAGP?-{Qy>irM?m58g!nWeK2C^(3de9*jROgp)6JCA=Z>5{ zwU!5c(f+XohQ98=6W71_H$De-qsL27`LU~f&+8YQ9ldRgvm+TQy9w}s?C6bPoE>Ro z_Z_l3nh@V4#8)b{i7+8;nc5&q?Wj)8c~E~Nli@PO2oaB8TKMvjqe{OxK&oJ@!lD#2ASA$iB_{H+so&dy0aBjyQR zw`M0fn+9ABXB;`nP?0|g4{-D_2aF17L|zGzSIidWvqfsQ{g7?D?D~`}o<`w5gH+7c zSKcbw`k|zWo<`+t_mZrVtshESJMuZTJe=T39k0n$T~}A(XUJI<`o~bqKHGj4HnVcJ zdJuUgGkOlK%!p(tMz6sG(7cF(k3G_0bRHO0%NFM& zHu%J|MOL=RREQ49t_Njt2!$I_94Xm%Z-xWW$LML)$#x$&hDKysJMtRJ(p=0;T~}-9 z6LMyFGx`)ZvyNs|n;CtER%S#p6r=Cq0gS#v!Hh_Q(M4d?AY0T|fPRquew4*A6mCEb zWInuxE^z?*89j}L**N9MGs_S;xDlII&^w+k{viT`Lzt>$idt6uK*Q_}2bj1``rQzCogRBOddASDJhCxx43acJUImbyvqi^jaiyXdmt7OG$VTC&*xAZ7=_ULQ+(EGpdK%qI zQS7cMS|=&KG}}H1Vn+?}%2S6}k4Ee64Y59KW;YG7D?_{xtqhT5D2OfK0T3IaV2Gpv zu|FX8%NBjJMel5JjpEo+_HHGM)+pQ@`yp9-HQwOh*akg~0i`(JpgEfMj8MU6j|+m?OMV z_J_?Ju2BwSl-Hw`QIb4elnb+SA|fYJmk)3a zWi|hi2ELf~X-FiKigA={lsw$1Jb9_Lq|aT0#) z5}IAPdf1!BY3+uZ6S)kN2U~cn_hR%t!<&{b+ zCCp0gk`uXt=CBI@{SPbkuWa#Ww)j0;9Jg2MRpwu=m0GSgx_700cxhQH^>50tJCbE{ z4!kARHjjI))TG*21})0h4!2S<4pu7mrj>d%hDok%{^?k*YVjoVFctofhQZ!6Oiv7x zTHE|x9s`nwT0E&dPDP(_{%P^Zbg(y#(~Fl#R;2WCq?d>so0o`8S}qaESshco9ZQ7g zr4KI=s-Er=saG2pga@!_QLIHl)6N=5#@5DHS+&Ke+V;oI4d`Hws*OWC#u4CcR8zB) zjFGi>P+2mcZg9ucMx7Io9VzHow=3EwCAFhYEyvO7DtQo|IA)TeV*Xji{DU1cX~et| zF|VjCmaCY5LA$XG5#k@fOe$H35IJ;&b!XgMQJY=}&mo%2QC~;(W0kwL z1IJ48bYoqRjcf}s<0$e`FkjM$HQ(qcMjK+JVe>6QyE)QOKjXFdjxZ$OCB%2MVe^$8 z5itHJQ}Z2b&`{&yiDM@D4>6ZKiUgC+8c;Q*Z{?)3bCNHk_tF0gO(^D};E+ip?W3H{YK}J1>AuUd6z3M=Yu3zPzM*(zFmJV?dt0 z=ag#bIHlS-sTa^5Q>s<0JA2xectiSRq<4kKyRjRm1y7;UvR3+f_;IfE>yg$cdE!u> zIG{44#f~92Qly{f8Rz%kF+CB-BCm#o59H0BMvvL2R2z#(@2rbSm|NHUgfR5MMiffu zHkAIO2IIrL2D7Klshfn3bLw_$1W)w2WE0Hh=Xp>KaLSYmGuHgeJQ>?&vL3=nPw+@d zb!SfdwK6<8_Go|z7+4RRTyov%(~iX&u1|awYlMMm6uKliBEA`Zj@4;6v)u#P&A+mS zdIVkQu;9Mx8lOzpb840qBvp$J?0*U&6(KBUBymUhB|l;e`VYX4BpS}1_L-H{^l3|| zv%Fg<*@_I_ma6^YR&taQ-iOI`t;xtwswYh!NT-?kv{MqF6SQM#KKN+rss}WD|~0vjY+BLtyB#cs^ZIjN19Q9B$yt;fA_& zw?%gcojBC9;ekUX879iMIu!q zRgxi`C|%u73CM?4$VuNot#uLH7Wb2(I0V5ChcRw`H{Y2%yIKX`oY(9w<_>Vj`aO5d!X@HLHax&ERp*SK~&5oM(AEj|DrgubkIKN1vqX1dV&4_qYv$ z$8D^}Z5ZUdiMR8n!OnXq=Uv?$UH61tVDm}16HK0~ClcuZlh09#({Nuka<71qd-}W2 z33Q*U+}{}BegJGfiS_p%xnJPO!_~+`0!AL}?|xvQ`vT=YKfwKH*nAQj={GXpI!#dS z#|OAC4D>NY`IsEw<2KlQLYx%newK1SJ;43cKp%H0AM^dgnCIsr5}5;&&)SY8FND$K z3bY8#0cYfURY=SI$6XpU?n>`*R|Su|NsYS!9erkGJxo4_`8t?lpRilO zF#649kqUYodin9nhs`Il(Q0Jx z$VMuAnaD6*Q`GR21BSm1HXmk_VDgDWY&QD&ftd-LPh`_!@`-F} z;K)nV$O{8TUf}P3exUm`%KfSU_xJj{zelp2U^gBwPRzW|BUVe*V8*Dz2J*GzXj%=&4mx&BV$-mX`I|GJ)5jG!Y z&%@*s*>h@S@5r7}_A-%0l3#_EHDxao8JK;jhTj)3 z{QI!^Fxv~0XJmB8_YsVKiGQX>{y1RdgZ}Oj{kO`;R{=i0fXyfR!~X6g$wy)Ii~c7y z@(%$cf9LNW(VtL0en&r_2#@=@h(vyYN!|jKnb}D4Uoe&q9?ySIqS>*?N<%TsT@q6Qyz(=z!Y>>5>a-Kkk5qCBjn0x4hZ=?6>?Q{^oi@7pmA$>k6SZ%+-x;& z%zxbT)wtdVXNIzS@Td)=2ah^v4&c#M#nl-deO6URn0!!O2~*G%wpVtKkh{U?5ps7l z2ZY>Dh1>@ned6k+#`Q+oQ`tS@x(-HPSXbym7g_Dn0!B-KLukD<0qBfk&pdB^d%TQ^4W>zfPCIo z`MiOSK0&_@lW)+wUj)bAm@L2J3kTZyhf&dXIL%M zHKnfSbLYb5lknLvdCnq!%mtHNc#efdM;Sjb%2Fd|1dN>StT$_qdaS$DOUloq>)%D5k;WgJKFyK^N9Ll)cQFj3m#2 z(F4_7GzXx%TZOy`9ev`uOO5M&tlX*W9&s&&(Ic*9Xby<$0TtIebo4>F1}2}7SHl#9 za;36+guDSpkB}ckb3n+CtB|*%qfcB9t8u+iZc%oRxVFLQ5!VxF4v4E&mVHHTp5^N3 zI*VQkn-AtDFqKKC9iQSF!Q}J3H6C1Dp+;^SFmfAz_pJln_fYP;2DtA6n@?h${73E( zIC5V#a<71qd-}W233Q*U+}{}BegJGfiS_p%xnJPO!_~+`0!AL}?|xvQ`vT=YKfwKH z*nAQj={K_c-HmcTKEQopppPla$K(JXx54HU;-o=L{9&A1# z&IxqCRJmUq;C^ACkNcF5mHuI@@N*G~EQiVGyb?)X1Ea@ja4nhxPJ^3ONDumt`#{jR zTfE18D0ti*YTReg(Pu`UhRNp?yB#K96wkxxf#L-;2cX!cLi)G=xGx8dyW4x**MrC1 zr^bB`9eq%|3zH9uw_)-{@d1n;DE6Z{0L5o2q>uf_Js33Z=icKU4j%VAHSV|Q=!4>G zm^@L?1C8&!$NeFA+~aE8pM#wL=I#9VVCTs(`%dF;bo5E;WYD-NG0#a%MRUL;o~g#I zh>pI*DtkMx670ODa$X%BeUif8J^PPa%X{3k;BjMW+{_^7ac}2|VCSur^XBf3?t4Pm zd=hQ~lPBm%q!CO$M=9MCs*&3UjNHcGed|E?J(T;d0q(oN=95?_|B*Wcj@(y`+$&(@ zp8oE00^Q%F+z$wF-yb%g#QOP-%(qT?%Kg9q_csUn7^8fQ4Dc}=HlGlO2D&d&?#BhV z&kyu*yYex~Ka2@}E+Ua)n0(fDBzZE79#^0{&>V2`nyo^b;Xm%QpmFDTk2^Pb+@)&V z#pviWBMV{jIm{Qp0swOmGc+S(I+YVeYk&8FME&sO7OUQ)VRBXoWJ4i z{LNtJ)#COY#yN4UQ6RlvwC{M|PTbl*+6?-Jm?6Kp<- zb?_hg3N^C#VrZxA9<$LMM!(s(Rt4P~z5Hh58rXc0U#&*=j;x2Wmx&BhGFT0t8!-G$ zu=y~%0Vbcwu2&;_M|PdEmx(NroCl*HvwRiwDD?7UHUc)E$cCwry(1f<>}4VYv&m}s zTLXrl2%8VHTVV2uY&=Z9KLIF&G3Z=5PT9+Z9Z9|eMn9nQR7SJW%Ma*G*nGmC4wG-# zQ(+7WyF}T`gbmuuRcv>opI>Z?Ve^S?AxyrpEl^{7uY~!^?iJfw729g`^NVdIY(6Vt z1x%h{)75PqjD9n=NsYWAVC41w?m_l(gUUw^dnaIHGfEs>3`uT9#=Rf-U{@(Fh9~evLjo&mMLbD^$(qEu|sX{vJKkjEi z<9_8m?$^QNCME29+LP$$gW?2CJ`?c=OhHTJH)Ss~5qR-I!V^_8ngdW(Q6X1CN1wPV z!W0x&d1d#A>ns>OrtoYu2gH@B;z~zHAC$FV@(H;HOhF-6S9Xt(&xg??R zTo)aE;;N&@^*+|JmE9w*3t{w#s{xt=;%celYKD$JD4W9M6LMpif>2(f>>eSvg3%-7 z)@Tk0xswX{N_6yztGyc68)aK%_lT=Aj2>}yL32P{y;WR2(a|Ta95t?YT-}x3Bd$I$ zdc@Ti%>i+ZQ*n(!N1rJk1(Q$6BVY=e;$h0}5pn^H9w8T^IUwZ8D&$+y@&9A*&Eu=8 zuJ-YBZvuoVDpp0DZju{tf)Ym2DhYv*0D;I1qVW&{L_-pjfT*oaD=N-7E6x+*Jl0mL z)~Swls@6Ksb)Lso9DeILd##(5?cV36@Av)d_j&oa@6K7zn%CNUpL_02^!RmH#;!Y+ zhh}hxU%w^L;a3NdWBgi|@#`dF^rZ3xf;=uCN09f<@K^%l@_cj#cf@llfsS}iBXUeU z7iHo(pBOz(uP4as^f?5^Iek_JcQ}19fexoHA##k<*JPaDNQ|B$Y#_)P5AJiXb=$oz z-tMg#yEnxt|ASlkZSl(Q$tb^z7(GG#InM6AZoBuz+kGTs_rW;jkGhpV7O(tY8Rc(w zW$f}q>~+FC0l!L+vx=qECr;a-jy=Mv;`c{V|DshpX?9WE~-(Bbm_M2>NJdB){> zV)Xb`m$Bby!bbHcIs4}loSVq~*aPi|4#(Mi#y&Eiqa6E(5CwOcwr4P_`_5)0Ic*&{+u5-YigMm41V;kpL6C@+|X9Ko?{btS7#S^^FZH8rthy6|4D$o^zn3y|tlfnS#vk?U5TT zgT;*%gFS8>Ou)|+>@9aO&(-e~Bq=F0e-FyQ_VoQ<>h+wRn)_iX=A@eYMoYDznf{74 zxmMU5HEC{9G{coa&9*B8n_clGk~I|Ym!|eBOVZy$pS0(q_b<8q-Se(rv}9%7!L`kcm#%E93+Ydk|LnRhY-ww6 zZmJ);B5b3ETePBWRo$Z1V@55SS>IS6w$(2ZhG8vB76$`^?SmbHUR#apNS&TqlR71J zZQ&h-Hx>S^=$68_3ja`eQ_<^%-xR)A_({?Gh3}<5D7-BFVc}cpj|%^m{r*$SZcY6m^~cm5sk>5tN!^pWH+6sN!PG;khf|NH9!ou*dLs2y z>Y3EDspnEJq+U+FmU=z)X6mifzf$j}K2NPFIHutEf)fkY6`WphcES3B^9rsixVqq) zg4+x3D7drWu7bM@{!(yH!Mz3d72IF&RKbe{Zx(!3@b7|61wR#REWDNqbW7o_RG!XCl;Mtw65sXqBD!mDLS`kebM9f=4rq4@XkiLk@cv*TQ74q8jjp>`x zx1|4&{$u*C^u6hasi=QTKaqYa{dD@-^mFMKsLZdXUrWD{ek=X2G__Rv!}Q1L&(dF| zzfONkt*|Nmefp>L?~2zHA5*-RihX?XiNz-uucLCGL4`l3czyBtRQ8LCFQLL;Mn&IH zys`M|;%keqFTRl);MU^Xs0nVT_PC20;T~#_2Z|poewZ5KvEs*zpDcd5_!(-Ie-^(` z{1P?DE7TmXQ;WP!ZSx+r%jd;64E}8J=Yzi({N>=U2Om4+xFN?6IdRBILr$jlIeo|( zL(Up<_K#ZR#?()(u&+q=%q0bHd=g{YezBu&d zp|1>mZRqPm-x&Jl&~1Z3!PXr+(^}uGw61wY%dmze_pQuL{Pa^0%;b8!-ucS zNpvt}RdeI86-xpvdqWwvq_w`TeN{aXXm2E`#F6;1%fDfD4UOrg%OV;i>3?eg)-L}d zo@I>@jW!_SIpMV2E*wD+@ia6=RA4!Yy-tNb{V(FFUmcNp&}&ZOwEH!VpCg{O!y+>M zp*G@KvnaYyFA)!ILipEOJNOPRr48MRG{eWa2jAV- zCxRQx@l)r&3?Jto$Z>}zf~GIJ8qV->4ZydC%JFSOSHl@Tt^@dbQ__!k>*suw(4lDH zhQ|8VJqsu9xu~YKd0A_?B2__@w$#q6_ZYLwqUwga*5Fa=V`1tST>G&BZ7m*Pl#@{NH)VCdvoG!6@fRy4HFSbR{$$|h1^ex4Y%hxBvv|Ks5;0o1m&(_4nFhdIZg z{cm1;5E)(a|7g^E$1t?MwY9mmwZ5gfwSCW)R%(a#V2g?!1}z?y*sy_0G=lnO%N;uI zTNx}XrAzuZaBhFv+6L|#;I*R%{l8CW-Yt6F-O%X&Y7=4Y(L7+?KR5E-~Ra0H#$|d#mss3v)iu-h*xF9%p+2jvYi?TFux!}! zVDrR_Pp&)S#hNLb`Y!o;&-89DzBAyI|C!=LBh8V@ztoJ~t9<`HKO{%LvQLi(EqDR}F*Df4%Nk@9p>P+s__+;-GU@4Y+IJ z|GeX?!}jHqR=2l?CW~uFJ$LiDJH5BzsQ1^*J7@7t7bb(#E>8r-g__pk5qjPlaqt6^`oTjVn(GGcOd zWm$PmMdWP7N*2g5HqK@nUn+soOQ1jocq zuCcS8?VNH&XT8VNP`%41mQCeY8XF}VD|73V(5Q;?swovU)1xM-XlxWaR?bdWB4f)Z zOr2aYwPr?CEfZ0vtvuu4-R$5QN^o@bj46|=W=xD4tO`+e+Otw|mJ%CNJ%!?`oG_&n ztq3t0ZJc~7zO$8ZNzGL1%kml1;H-3#wFvIl{1w#0Q>IR?Ds5)v$yDcxNd^yS-U$=S z%FC*!)|4)H^8Quvj;yFIt0;D{9KgY0=!3 z`BBAOGIjFQYRYtZsql8q++&J&?+HF+wn*WqsN0g8J>)nxK~!j!3{tr_KATp93p^89~(gt_i&C)YQXwXK-f ziU*Iw8tA@s^TY>F{;=}0qu%>-!w&EMaLb_fi{@JzydJxv+mOn8?^6!%PZY;l^uPWv#4a01F9-F>h@Cw!F>z2L|3EEfdwMDaM+~Bu^1eZ^ zt%;EZi|G%!u4-%gd17{>#GD4fu{+aCA-zi;48a~q&gW!tR98W5b7vAg9ir8{(91tb zbO=OyLbU&OiTve}sFKOb_JFgxuRh>E$bW)3{Y6 zmsn2bjwd0CQS5a}m5|g~kh*CYy_~#N5c~pCxrq*vy0(ic9UhF)FR%q2Jxl229eTpk z>Ew@;nFqQ^>f%F^e#b57cx?o|45CtYN)95M&qtDVKlgMP37!kVKaHXn`rk(y!5k^Z z`&|XKO^B|CXv-LS=|^1<*^ESCb1VAmFq9m-;l`5Kc@Qh8rk6vDb>H;cA(6j}7Sq{* zApH(r&~f{8dZ`&41lvVPO;W=_aC{`#^fQBdlH3K5n^!|Gy9^0}L8kO9H?@nLwg^f3 zg}|U=&wc6Tev;h2i{zg48|AB({%qx!lh{QNYu=AudQ;b#flCs^r405yD>E#=e>s)Si4Bk#yM|tRj}L-k( zosC*;vW6t-_eFz_V~?kow&l}ILTBB2Mn1gJM_q=tU6HR$*& z#10~{&fN@-zD?g4TGeK^^J0>^0a6n;(98L>WINmPrNTu1zm=3uC**E~+{;(e%gUL0 zUx8erhzfyiQe>hmK>~9=D+0 zFQ6ZexszUQri~%5l=u@t{^?+z)@(Ch0p=gT{5&!DWabOO+|X7XwjB(C-zRhEI_T&@ z+Ub{If{rcjrk9bldu+)9mnwlVqcQ?{Byc4JZh*i7C2%tYqHj!0s}GmZLz{*5^!!zO z*N0>`LN@nadik7Wi`dxxZdtOc({L4J6Zg~01N#TT&Xq_*4pNptDiUxYng3Kq)$G== zq0#5Z)zG!|U+JacfFKwU`H^@g((s~3gXInV0uLP~57Nu)q+tuA;gv|kD0-tG%%uN| z(2_YVvzyBr8&m@703@gN}L&Jle z8b*3Ftc8YkAJfZqE)7q0Y8d6wa2zz8{29FzFLU_tVyA{N9u3Ds!--$g%LSz2V4a7Y zg^B!kG8$&>;n8pcG@S7by==7{YD|@SnOwfKAQ#Wgl6Vr9#M7-Lo>nFEzo%EOkWcT4 z(7W{}dU>4m{wDIQhiFYgYXVvm`F-e(rBvHjtdpSZ!XN2nL4zYvzsRVVRpQIk$xv~A zf*#>NO)A`R8jlcX0&ynt2WJ$|@hUzAig)ZuijO-eHqcQSWwS>50$m4X8+wzntq!*8 z`JV-e{L+kyIbIc~LdEs{NX1FE3be$uP8FkkwL1+eZrhAh^k{UXdu~QWO*wsS!?iw7 zhlX1RkcQuohW4oXxwPy}10a+oU6st9Hp`{w4CooSHR;)AMG$Nr=}EwTBEK=Cz$JLa zZY1~w1RF_k>qsz3y94&DM1FflmLBHO#^};;CQNVGhBVwu8g?}ym~E?JK@uBlBLCM) z&wQVvv!Lj;fuv~brXUz2ijq+-a*U!iO3^f*qO+lB&LC2BFe&QDi?-{W{*g}O9%@eCh14u0HDjZ^4=@c#X}X6LB=HP5iHEyMJhe^YVQdmlS(A8pn#4oV zBp!Aq@f0(Ohm%P>bWGx5ViFGtlX&=-%zuGiO;mWk)Vi_`U!BaHgD5$&W+ZN^)F?l{@FN_py zrfysC6b;GA+_RiP3eH1?o`Hhh>9haMm*f5*fn+A~f|{|_RW-9}XHJ@2TQV}}cyV(& z^eLF+WgnDo`Ut&^#5N;!kyuA| zmbtUZTKkH&kt2rJjTuFecKln6R{5a3U_qzOQ%_ogZ>f7l~l(el9ZG+w9 z^9I&7G%sFB_ZS^p8n^R;1C;i$O8XAQ4as;nwe;IJTAV5O(WW1Bz+x0Q}B89zR{yVN^JY3aDqalu;pur#-&gBtQlx`EBh z|KHgk`UVRZHqe(%YgaVY(^1mVlPW_0@`A84A0vmWbfnPF1Ka4U+sHa)HOS3bXtF-1 z3dP8zeP>Gh34@{QlG0f){+hJ{o(?f3Z?slQCcGB~LnVnvjj8%Gx)NPX0G>!s^H z>Qqx%rK2AjFOK&WhnVU&+Kd44sK{!f-kzz;*r4q90zXyOOgy*QKupi*!*X-+>J%S($@O= zjOkm*J^GbND#YZ@xJIe$^dzq?7+66cJHZv=Mpb()2&&8Z?5Z_eExorjy`D$GTpb0| zwxGJaX8B=lv=IkE0m=0Z-bJ3xQA6r(l2pIrBIlOSgEwojn1^?n#e#M9R0@j)Z+6q; z=?g_8$4+QyuW4>;z*!cpndn`-{r1_c8~W04Zf?gJn80=0*Sd248xRykKFcl@Z#=wiFFcxb*lLEmciRn@c(u zzB;9i|7#-uU#B;g@c-|$_OV%ZP~PS6D{l)SYJzaB>WR_!YKGH!D#_B>fc+ZdtT z2JANIeQY&y$GjH58AO^NCnwLQ4J`N5&hs5l`1pL^fp(+IcEw7pj;z$Rw5_0T9g2x< z*+d`ueG%IJo0{oH(db=6Y5oUQDKD7TnPc5&eMx5>HUsD*M>dfF{p%Z){hXNlIemQS z>7qW^A?{Zp z(HT;SzH!PYuu-VLq;&MV$~XtB>}Ct{-cg2hjYfHsAat zgJe!#svs!JU9oF$XdT@!9GofRI!fw`WFWV{V;yHcmF>J!D<=Mzi9aux*O{Xcdgt0Y z$oXk^<;!af~_3dK;nfaT_5tSm7qv@2RxeKxFR?VJ8-%wqNUA)X> zwr?=Yi=3_2Dvl45+E3Q;ab7H!{uifqgYqYOnf}CKOWPay^_!^ZtvJ>rhXd5_%x=}s z?1i|+q2syDE@0na&bl-B!KzZjy&Dqhz_|P|aZ78;> z=wRG|w~Y@SjldCh_5t?$H^_KiFuya35xNhyA*{I*D=XLFFiQ9%(PAkXgVll?sl1>` zv+MR8O5oR-cT)5=RK1hJi7{zt`K;RN851Yrvy5odijMMJvhx1?%uOA|{Ws~F_gv(> zVE@^(tLcH@@bWRE=0~T~q;fg{exhI_g+1slkv`e7H$Bcy=gEoeyiM8Z8$7ss<_#M* zp4|PrZu@oEX5}XHesbiU9y@C@Yo_fp1zMnZ!OGQL~}cydGcYF7`{!L+p#Z>fdcxBmTsZw zX-9y^9qI9O^G5PBmM(3pZ;y6drv`JY`FlP{p5*I5-op)ZUNF0JHI(Sb3R{vJ6LHUnx3Q$X zPI~%RF5-DOxbfzTc9WGj(yuV=c|l93{<3m?VB$%`yn(C2+D1w^NwoBgg3rZ+#mr}4 z^y`VpO;nOh3I9qNJfEH;H~IJNOu_W%Nx-f;EN@9k42ji?a>r4?U&e7I@6<*gFB5w zI-#<1{Wb^hr3x0-nBNYG44f(1-a)SoGN?N8ru(5m)X}xWqB{$Q*KNX7ZSxQMk4k`Fcq+n`k8{OH|aR=i88U4!(Dm#;@A7}L+0J{Goyf>1DfIMa{0zwyZICDxSb+ zZb14`V$RDfC)2AJi5qA7fHR`7%oea#xYx^ZWwcx^^pidGzwF65&`ag+P@ z=(+!m0&VMu_Te2gO3BG0aNKCReWJhm&{Dg&wRTBETMJeHW&w|h1KSti%m4U85hQX5 z<&pmN4c>@0KRmWsTt|N;f}oM2?E?XgIcxmCJPkW;+K zM9%ke+9pZYI*}-koFz?M)^-6-Qhk7Pj^4^Qw36fl!f<>xhVMnSaq>YC{KiAy*;+>I z(Lo}2Yi1iXxqD22>wLgXnU2AUM$SJYBG-D6-)0cw_CG|V%?ErP#bX)+D>dr8)(kg? zu|f1)%azDf@1KHf^deI_5mxuG2wgA-je|EGCM&NCaHi1)uoh?XRiI}`F-f!1}#R=*m{<~?!tBrkGT<{5_Ri0egU+309* zvz}~h6nNnL&OKBXM1E4gQk8+?ySw|87*Lq1>hTx`6nYgt*# zYvoCSe%on++u{X*t}#;Pe$jl+_PAhINV@S|QTq0lB=t0=(_ili+p#Fu3euku$~A4B zQEwh4*!WC$un%{Moejo^rJbHXEzqs3kRODb1#+UOT*+~nOuQsQyNr}xyAr|25rbq;cR;(8al#J8Ra-dV2kZRH@R2QCT4 zS6b<6`0C=-bcOG>201y!E9qx^p_J4NWe8s_rN5^&G{W#LInqfG{W3N2;tO-oNxvga zSNPsukdwD_2F7>zNY&1a-Dtws-DtuW-e|&C-e|&?-e|(t-e|%X-)O>D--5he0lp(cHk-*NzDY+v zE~g(OQ#rYGqf8f(!JK3x{TLY~`f|`C(>Xbf5QyyO9kR$NblDj4+{D0@q4*DSDqD$Pu3xA*+KCPe;($JWT4!u5J z_+(@71tX*(y5R@nLrxddkU9yDxM4dEhu=ONvJEk~=!XwJ`_S*hMZXV+e)tAHpMJ>3 z;j6RY&<`Ku^vB`Q@55ysfXAg@>gU5Hzi~Kh`*6vx4~KobXVA;YDf-`qx#%JBB9D5n zkRAlxhao=r@58YMd>H)jVbV9y?eYmYa^k~7#$B?o30W5=@%V7WSK0M| z4E%6m=r`aY4XK6H6*8I*zeJa&qZjlw;=>+vm_>K(f3PohT|H&vurKl1SV)+rAs_Gs zG);#cU@m${bjXOD?VF3P?Pz|<75sI{Vcmr^&@0-%L+RRw!FOP?@B3tZxXA0X!>6M= zJc!Gd7aNin8<+TeIQlM5FZB6zx-jtvI?>xcSs$+Dmv=*lk4N<2O!x6fZsK^fp163R z!-Yd0xp!f(@53O69LZj6_pA>SIp~d(_2CjP^doO^^>g7OFFEze`*4w$zHEr`A&y7% z#L35D@Xz)gIo!3LBF?!#-hS;wLcpgMGl}(egeX(F5P&bog+Q$610Hn`8Wl z;}Jcu13q6YK3wGC!yz&9K3vQDY(v(@L=JUu;kpJcT;ydRckzghI3Cd>XA15=Y+prB z91rsAl7)(ZBM2slDwJ=vcEZo!X{LPVCtjd_jGEcpN6OE`K2B zq9X?E2`&t|mirakPhgO>>5@y--p0juIooVm;K-XThq{9XIa>zwkOuBWd>CT$;c=Kt z2K>6mZJTizWU(%68T2mlhJ9XRphKTcL+)L4=#Rr}8RQjpLf&y+xNy`zqyZl7humMd zFzA)Oap58>wX=1Ly!1(&j_&Xvk3Jj7nF|*meYp6DGt<^BvMx;Iq~<2Tp9FTTd*1F_h+$cv9QF17ICA}{x-vL0OdjN=hKaq@8( z{Ih)*omeL}CULniEeD%eBXROR9?^p}5U0b3i#+x`*vEeA^CON&^uUhrx$5J?MIN@X z$NGHm;aWaU*2Y9mYGmVf4Q*WHWsd`H^N5Z(9_X>@bMrv;fv#O>5x2xqyu@;pp#Hir6#G=TS}f$xH# z&mu=%8hnh$;>R^$~qkhQOQpbI^wY0!=Jt!c6* zY&zs^8tkENa_&l>L9dGr-99>EaAAl`)~D!)FXE?-!8URrbru=ncVSXrod^63y6l4* z6J44HUihVH;InDihcpl5LK-+H#aH0^8b9l6=tP{zzox@i!QI1a$)m=E;-bg ztVduN8bePu&_FCU9lSOjexu&#N6imj#Gq-&A9h}-r@ z_p=X&&+r32#PP)8=rx}#bjRUhKO0XR4&P7{oPTjSh~p7Ivgra}HXisIXG?Mt$0Pn^ z(*?db9^kTHyYgfAyo*QcfbT9ITaS+qed5Ek9a*E@u@%RQ9HU+?J=&hEuWWqqy}P{N zi{sU6*JamUzdjzs0lyF@@*BsOjYrm*PY3K|;}L(l!xzV+>jOTQPnt)3%f=`D;?s$| zOAK;fjXLUk52;-o4jr(CoX7D=?c#XEpKQ9o7pDg?$KjI0I3DpOn=bIh@c@^-34C^r zH7v@Xdb>g&QJmp)wLgHLfhaX510la<{1aIqh!13cMq zHbUak$ve#^b|feYI9u>18;|(Y9lkgo=#h2girrpoE*`A|zPosAJw85Jw=Nypj;u)+ zpKU9SSJtpgkG3c4GaDb`>MpNd&n~@sP5W@zlQrq%K^)!X%ccvxgc|v5!A>?F@uxd{ zaXh*{;B)z;dBnGDe9|vIopPQ*pS(wa9oIcY91a=SLeAs(q;_#U(A8bOI6a6t4woFp z@rW< zll=H(#de$y@c3}-qxj6qwhcODT$r5Mx~8({$@yqwk{=%~aiCUlJaIVu^~p*eeYn_< z(;<0u=>R4@k9|tVZ=Y*6j(nmAA!B1&FJiE9TepixpUv7Yty|VuHvK+6`<+Tlc zzWV%t|J~uU&tR=jdQr|h8-oq_>cio4cX;A-ppSg|p*s#2``LJWIQj{_7*`9(#^K^) z9FO#ZOP9Sb+j^u%avs?=LJpuGIri~LjeNM|F-`|~eDa9Phe>{XxY&-<0UjTYb&c;j z=)8bm_87?dF!9ZY>$+(k#3KIK`teKvK52f`5Wgd1(~)m{mJWS3KlJ)A$(c(|YG~_& zjP4T~*F9omVlPg&?F)GEy%d{{TuAP0J5mpqjQHS_1@6M2%SD&-K>Gk4^4%qTC&tEb z#%mh(5BQ9{%Ck58+?xizI|v;7umvAN8a8gzzzZ7kHL4*f2=*p}bbv+amJd?yw?VdL0~pxdS+mo7T=VeQ%c@FS#w z*@Z#QheXUWRMb3r6Pt@Fnp|hqa`BO%fOc8 z)y6`?q_5z!jYAIc+Zg=Du<5wQaADFzwv62|$cIATVgfw^$x%SVTwE=+pG zg-NftF!+MHia&Oa1$W6pue^u0<-m^tdF)RvdD%;#N6Vv+aBb727hH77DQauu=t-Lf zU7#VK+P2U`qNDac4DtBzILsvje!cE&n{gOqC11ViXSs*L+CWZlpKa?yz2!`C;mDz^ zb=cPOuqWq@rXz2%{vqqbAn(FmH0VRVFe4u9Jz6j5HVu4;4a3IZqx3W43Tc3*b>bR6 zqBmWb^ci?Cd_0H;HnQ>faP%hDmhBt#A};7gtf+;}gX@q6eD&eLe7MBs!=WD-){c({ zzCn-6zSPpjz#sBJ{-vK`12Q2EO~?HWdex>QN1{vfqgJ?v|HyAhL*tN_*Tlx46TRruYx9fmi%CY?fV`|r7lv9u)`ejW`7rdD3q#DvIc8g@^k2w4+E4Hc z9r89NwbXR*BTp`V7acUjWb-2q_~ybS9`ua14PDqrY`XAcc44pu`-n&D13#`^bl9@# z$gP~AHim1|-KN6^?EC1*fsNU^w9oJh*O~?!Aq|Pg#vtRu>^{Z)nJtUFx#(Dvkhd|( zk&6y~^#{x{722; zzY7B$ed)qNqDyUDxa8l3NuL0-arB&vj=I^run)T2uj;%Ah8(!$-~()B!(FnlDSm33 z;6>b68$LN%hguH313z4td~nf_laK~-rsDy> z^r#Di9Oy1gL?!$a^=yd54Kd?u-aLK!k={iD(j$LG=mNpJqnf(?!lD0}OS+y@diwu9I$cFZ5rZ4eCTBx16|et?8o8Ki*Y;>gUtiKV9Tb% zH{=Aqp$;}45)E>Q*~TPRtVh`GO#?Xs9lnC!g+X67+$RfPT{@x9hl#y7+=U@G$O-Pr zb$p=PYeB~j-_aYetL1cFe7N`;rvp53IAZbXmpu7!u^*=cJU$$`K`%+a>G&Zhy^fzX zCTq}#YgxpQP2R;L=Y}l{pFo!9{6j^YQJP}wt4K>e0-=0>T1ht8}K0;4`S#J zA9#Fxu;H@7lt_EaL9CrCr*c~d!PL{T`yjb@{K-2tz5X|GmZyx-Q`2><8&dmI2?Ae@rXa&;fv#e9@&3f z`LWlri%08#?=Bu&kB?9GE0+#!NA?pJpKU9S7j;0rTza%U*)y{7A+GN7>b=ONS9%vY z@!_y1Yu(3#IJ(Q1O&5A8n?Koj#Gmf)#qnUTz?yf(t!oDz*?5qj?(j)3`FK$?i4S{~ z%dXTl4u=ldLOtU6q^@y1;!ieR;EU6PnB#ECVH}V6l1&%*;&|+H1Z$}`4cv=ER`xXL zz_kw-pW}FR&22vEL6;pl%dj71!)?8GAGvU;rwap3_m7K5_l^q(tvfuZw@Y5?=fWiK zK3TCHrvp4bTH}yTjwtA#2c%P1gdlak$uzC${E_F8w$3;VvUpx+ z%gB3dn~wf~9eh7PW8yP#*z;kMe;=-UQ}amfY~7%v*JM9-;qp8ZJho23;J*uZ(IA65 zU`D*?6Rj6}D*SL^puraMV9NoMb))r(j9ynZuGfo=iM=@8E?*FXi!L>EVPeZC3*3cC z{j~3>EqV!s?%8a*^pi~o zZ%70GpKPrMbejg>v_I%6d^bVMfd@Sn(m>vPI4~cMTwwTc=m&=L$;Tu8?y?UIeP?6P zhyD(E?oG4)>sM?;)~10E>&vEt*F^_E z^6kPP+@&*QIhTLXXVb-wO&1$BU3$>Y9r{$$U`y`3Z7d`VzT0#yUl*or!4KOP=!C2bgRG0+MH3x5H&S;^ll9S?bYop0cN&Kt>{D2i=wFSY&utpc zf7k&AIn5u^HR^8DkS7-%@wzbRN6fa2#E0JT;ZhTyY#a`qKD|;K7ao!vaN8zwWz%qt z+}U*G8FZaH=@m`GS)i|x6I|oHOK%#k_e`2DId{nbbJ0;}mwp#r^!qTIjyymnq=ClHraj%d40Xfxl>%ukGqfLh%n=Z9S95z3E!da;4_*wi!jWlM*VdL22Z5r%{G%&j`#EpGQ z+tEJAS*>x~4;K&m2g9Wsx?Gst>)0~Lhl?NiL!E4X)D-;MXB`vx<8b6D8xL?75Aq4! zsD-ua_9dIg*6-s(ZjpamUfYm8AdUzAcZW~!DYic8 zH^lA2U<1DTaQNIEo;V%o1)qNCj>E-%HXa|2b%`}-$F6Gu**IK$jN_4BaOpw~Bo6FF zwjQaG4}&c9BgZ}-sgVyC`*AwJEP2zhOTYFe9QzoqQFHW=<^wIHfzNhqx=jNPUdV`E zv2D{~5AmWuH9vBRIBYs-E;{&8N38>X$iAcL;!7N6>k>cFBU%^eHci__Y?|M;ZR2uJ zsAa^qrfD0pr)u1`#3b)&Y#Ydd_6g6T^tG&4O@lu8 zu4#x5_cxlRT1ht8&Z=v9$nu!K3!v* zPwusSHNaZ7Wwf90Asdh6!NrH1x#;LQoITnv@Y*!(3-oAy^c->x8R=yk_hDME#HeL8 zuH(}@unnIz4L)IgV9nSVu5qRy-#!d`qK&~$$aEWnJ<)6X0b4c=yz(8;-t@D+cZOd= zL#|OH@WZ~WCBZ|YAxFT$haS}Ouq(L$t}*xpov0b~+Bj%e#1_&bF-9Ep@bcZ2dkysktq$ZAeYycy#UK_;mekJ~^j!4Ny}In^*fMXN#88 zIDE^-Bl&Uh!M=+wdyBSsV?{)J~bS_bh0chOxm_=Osw z9=0AAUB`hMX&LcLVsYW{*`~|d*SZh~Y+<(fwGYwSFWQ`h9#- zLt9?kkQ&AD=vv0{>3Z6HvY-2EfVE`HXg}dYHXg}?ix0g5+sGZ(pY}ucB29yBT-!8R zyRhNI#8)4#{nR|-hpijF!*3Veror!!`L%BBkz5m0W zkDd*4;h=`beYW4*#)-`7o><7bZR6!eo8AFxW#)eHfk@yD;dC!$QJQLtj7mFxYZo zk}n?yx(kzj@nO<0J{oVjq+5NpeYVg0!1vR}FKg8kMd10S%i zT$rpYALgP%ANE=o2EUL``|OlF*jPxsz-&5bKDxf|>`i=lCW*X+G*EwS8-Btkn=ZO- zI<9S+=s^G281%U4(o;4+=;#-l4m~b9Y~#Iz%`d%U)1k+v$(f_`0zNsPZMvMznl61} z>xLfi*>u^HZ93wIe(19?=t8_MI(p5f%UZDM(1YhJHeGrI_0qASKWrLwz*n2D>tSP% zflZq(`FGJlv+2@1E;@R|ro(^qh>MOIyD;e=mki=?(V@$QAwD0!O@}=6xae~B>)J@) zx%k0n)8PwbY&z_sb}l-4%SG4E9%Y|_9@GbQMh>;F5}OZ`b!E#*pV{<~^rPN3U3_q1 zkOA((V8@4n?!%Bz9|k(=>9Pk5F}pD22zp(Z)X;@NC+g_J5Fcu3=PP7>T`P$RYX`bC z27cIqJ{tpF&L0~CKjO0Kka5w$kG`|{L!v>(ri0%_hi(@gd34bwc3VGqrItD$$R{ww z?UIoiYZ+Z%P1m*6bkqUyNo_R-+dew@@Jzw>3%bw?HeL2gTffv4v0}fpamk~N!47CP zJydiT27MxD<5HhE+=oez2(IHm>|$5bL37c;FMGc2qhK~2^$lsr@7ZfRz+7~!0rXHv z1NXyP1{m@Y(y%emeHi?M4DO?~KA|ICn{Lx2mzq!3nx@G!EtfpIc1KGCE5$kri!WYgg%cYkppb@*AqJZU{iv(tTk?l>1G)=? z4j+c~0y{1_S*I=xIuWA_!*kw{2G)-4C-_}-&|Gxz!w(k*x(~zN;lofj9|n7@JqN8puI{FL4g&_vi&V?Z-J`8cAmM%Hy#ODMq407^b&h7H(R!%?p| zSsxCa@XIAD&jRh-V7vd{P1ikP)1{u8u4}33@W=L1YH0J}p2OyaJkD5~ zj(lKkx#%_xI?zWhI-Ymfbodw2z51bJJt6yS*G_Q6gAs?L4}ClmuS;Gq^rsJpUaUbEZlAF(9^Iqp zUzyqAc@rgdEPd0to__V(6=<@N19*NWCyB(v8NA!r_E*{a- z9UiF-_RzTcNzUW=#2#{xjV~LIG$Zx@f$BMy_Z(Do0qu#dgQC2#LF zE*{)NpueCy4u=mu9+w<=?H+OQffmw``ulh!&!~MIkL23NC;7&`nk%2^d&KI)CEqSw z=Q0kLT)KGdyulyaPn|O#F8PYXC08yU$x|GLIDEL|$%Wf}>EhA3jKd|DE*?9V=m{5} z&SxBt#4CXK;I&}~f4Bo`)oF!n}Q55Z3x)B7l%b80!sCwc?E zY7A>#U&|gVF^GTYdC50qG!87JVbj5ny16hH4Yr^QdTe|#(cr(fA-PAqh|9(ygZCUZ z9XfEffR0(~6bydY81e)kZ94S8zD)-|?AvtkqsMHz*anWC_4#FE;Mcj+wQva)X`qJ@uM4+nQbWY2{gS-fbnt^_(`7HQ>Ch=QwSMFVal=n} zX4sp4#&^2FhZ;y8wVYs(MUFKF+sK(shaT9o>EMTNHXZy}Yc4wc0;cVXpEf-tKEx(* zflp$^n$Z}3M*qT3+@om>a)?W2jY-~J7~<2s5-(=>uQBY4*dv4|q@O_(-|@5bqfLh# z@(3Kmg^S)e+{SPXy;`66Zqq~J!}+NFMQ%Wc9-JvI+=n4IsD%p`ACPnSq4gpckOPmV zLywOh5{6#WzN0_He~m%EzD91qXVcJ2ng)Mh-=?7tY&!ggefW&{v<&R&Yw(0L@Jvwr z7r!-4blJSfA#`HT()_fj##)XMLJ{g;iJZXQBBYh2hh{vX(w`@9e+caDwJ}r;j>T9eE zoGZO)$ls-aAF!?IqRWM$hR87ndREJUCNelvHD>FyarymCEu-~eEubegZtHaMAZFB8 z%W1vP8HdBqY&^hSJcvo#MegJ*z`1N=*gIWx={3!dxX@FYrsJ|PJ6ATYWf8ND+wv|R zsi7^abxVzG9$UYUPwHvQYa3FFI38WsI6hrln@@fR*H;6aceaf76Fy|)kvwGM1Mc%f z?D%kPL-U|t(R&fVLpwS zG(sBC1zH6S#D%>>_8rs(_Y|_9)X>i%4eUwa!Tuc5z`4*!18WkxpnDRH*)*{4VE>7; z4L-vvF;fxQki_yD`0Pon|9u(x(ce>w3XHsl&QAd7wUf73>H@`rdN4#b3d zcE^9@C!`^38Ga)s(2#cwi3K$WAL8te?(X{S(u;hCG?2@YG)ia$G+-OCg)~sp5i~&8 z{Gg3;(8nk`>Rd$wJ|cI>1Foz2x|ZkZG*6@f8xv^Ep&>NrfGjZZ0G~_)vU6#a(Etx* ze0;#mXh0S`xQ0H=+5DSDJn*}W#!UVhvUN02r^Phn8vSh38j0qkYhL6zqyc`>2^wml zX|Rjh2oJ8I-=>LO7hTg}13EAe2jt{^2(D3c_@HUHuBXvN18W_8;_FiS8AD{D7x(4B zg|2PDcj47`gf92R;DIjqgBg1lXqasp;p!#04FQS>lDfO@mz@-R4CuY<)IO^ttGo2HmJ5>Iwglr;rBZaa}|sMWccS)*1Q( zd4vu*rx0UE12Q599?-B4iC(F((4=in}&S4=u&&Z zpih2=4d{g|Vt`K2kSBc&9_X>@QbU{9M;AVvh44eJVG};-Yl%nG#8;aa^bD<6@ah$b zAV?&0|J%`#_p3;*V}O}Oz9Yf(?RoxcuZ;eV&${x8jLaS97~YObo*(4-2A+S*^D;Aw z-2cu0ef|C~XaAS8|LcMO|MWn|uu`)hw^W(=%Q7=38tJ4;=5~Cx!p!py2`1orSecpM zVg5VI4gb;1e^`^@f91d+2mFW6G5D6V%=|9X)6Ir&@d88NBMfrEzi_e9zl!lQ`1*oN zf*!!@=Ci&Q!?&L2-C2G%^Pj!i@NKiu`0@2(wqI%HZ`iNjvz=Es&dtK0C+u85*YKs; z?=KHD^b+O|+0LbWy`HZxV?PJ6UzhNF5aWlpn7AM0>*tt%KKpsva^vsQ?EmH;1ij$T zzYaEXr?A{PEO*wS#?ODW8vJv<{uf`@aa^DB^@3KDx5Zq?8n$x_ZcWHeTT76{{GY`^ z9_GXNdcQVvz1<-OU$NZG-}W|gzaD7j!}^%HXOWrj>Tl)^gP1VYrdHu-_FeEvD~Cx%=PWNntA;=Ge5PnnRjIR5T+0Pb?+#y^=r3?=ApmdHkzNl zuAn#KTeZsM@3DDievRun^bnKJzod-bNgT&c97i7e`zXg*#r}?Df9u%a9k(#@M{%5A zvfRrY=boDxeAf16eu3qV;yAzMc%J8YdNTbOrY~XoRUGGo9B0`zyBv@B>aN-4QOr4w z!=t#Dwgr80eZW#PAK7H+|7kY!^?d!?7IS?sU+=-!pYi+*)2H(Ft$h6eUq8gx6Z!gU zo_ic(^lruToHlbE@O59FYnXoDuY31{zhjTvC92oad_CtfbA8mRAi`gtXXfW?&D?lk zPzJd*bIp8OjhT0tXXew(O#iN*XXaVl&mqel$#N&M+-SZ&w$iMF_9`L>5%)Y}$L*Jj*?G&aT&+=oY82=wBH}i=cM+5WsVf}w&e|Kbm$1?qGrk~IB zZQ0KXp4T*)xEk5+jcZN4w`(+UoWb&2Hks?AIo>N7zn1Y!8GrM@U^B#hB)G2gAsw~_e<&N6yFX1lv_oR8KAo5PQW1qLq- zgDr5~bE%>K=@N6E{qp;913v z2bj5Ss+kX3V&*%hoB5gj%>2Oj<9-4C--X6rb9L|xuIm??dBjvRe_Chew&`YGwV#i%ZFV_!4x#Qf(?GuNx@&HUyJGbfpU4d=i5`+{g+J8zOX&$gLj=1b zxvj>`H|}rd7xp#tKDB1PdzzWgt~YZJ<}YUclVqRab&yXKmBO4z^i*x$SOdROkp?+!Hn?!o)T)7*dkd4K*3$2IEveWSem zVPY^JaU`b%=U_f|zL}5V>n-Zc^`q5hzGb1Aud6Zhwg;H`*Hg{hy2Q-)PdD?+`5cM`SoUQonht^ z7MZz}>-7@XYYNwE6X$;`uGg(xuSHz1bGcskalM8x|K(h-4zAaST(7>&zmfAjllSLK zcz@oJ_v4McKX2gcp}aqT!2S3P@28LR{ydKN%Zqt`J&pI*cX@vec)xsw_veAUKcB|> z*0R2ZEI)wd&tv%ud4F!<{rMkkZwBwr!+3u_i}&Xn*xvixPxE+xF6MP~Fz?S>^Zq=F z_va^he?Efu+duJs`v&jN6}&$`#QXC_yg%nN|1jp?eeYzn{_a{8EI{83n;8tk{93J< zzn*61bC#O#KzK^(S~8 z{fV!4;Ptiol3+XdwI{EyJ9&Ne;q`P1udh@1dRty!&+z)Xlh@a6yuJ!~eI3K=>j++7 zkMsI^hu7DXg=XD9$?L2aud^e0owf5iE9Z6gBd@bHyv~m0b+&-l+1+H5anRriK7Mz5*zu4c*->o+D8qUvrUKbmAT@2=Ra3ima8~A!OuZu6ak6-3K zeva401n$$Txv$UTzW$v1x{usP@VeNE*Ts6)w~qDIvHT#GzntZ-*8r%7aMt9 z3}pU2n1B4C=3J}b_3NwU$IPiR_S5{l=7Lq`{n>&h^Zv^>ujcn*8~Od{-}!x275B+m+$URbU!2E% zayDP5xKCc>&d+h3Kjk_PnQ8o#`C0Cp{@gc5v;HGk|5Vo3 zgY})r`c7eeA@|LLY=0l_o1M6Cj^@6(ko)Ft-cP4<-wfiuIe`17H}_33_sxCWH;vo} zS8*Two%?1i_swnGH|w}>ewbnEv;*^h!ta~c^5;%>9b)dYFXH#nhx2o{)_LZ6(9}N$ zi?F_L=jUko{QkOssga{OdVaPoU(+02C-|D?=z1r&n z<}&^f<6kmf#C8|*`+@>KFTP>9>3qE%pC7;Ae*c=~%6YEkd0(E_G2c@5^D16XYnXlr zKYw1$bLj*VcRoLdPVjT+IyLcX%q`5<#(CVa$~MxM?_Fx-&*A;*9=3BW+u4olHJ{IcQob+0ocm@sejaog_s8EDzmxGlGk!kz%`dpG z2DBOfF5*6Vko#{i^WVVpNxY7at~7o=#LxR>uIKfz^|D|GtmCKlH}l7<%`A8U?}suU zdWhK{4{tT|VYAGA#=Q&7`=e{>%-mW;;cACG*u_yE`+vT1ST zN3Tr>MfR6}xA;}ikK_5M6sFcHZ$|Dw>R_mEVp47b3JG`GjAGa=3=H_v#Ys2is_ebZLVAUnE5x`n)y?{ zUdw(CXFvP0pOtK{2m5&t`}t3f@BXyWvm^UCmi@ek;4=5oamrZ^S*p{KG#V4*ibziT^A$^w(FL`RL_lo;uIW zf930We0>|=C$wJ^Y>&QbSY_<)#PWOd{m~58|M*0MpEcji2eAK-mIalNU$w!k$6lPL z-n_5KyovcwVEicFXLe=2qj-Lm`F_LkY{vdJF#Rje*ZCa(bbjtG^OIb!)7Z{Bw(~ll zUuUtM5~j=CBKmp%{EqF^^FG6KiEQr5c@+bQPvlV9=k^${HB-?`3nSJRiHM z&di(hxwB|Lb3Js4nJ2QJr!6z<>B=fIkK_LQa({EZiPz68?vKqm9+~&zdcDB-3w&M8 zeE0CYiT%BS^Hj)v6W(d|uly==-%>iotl#J6oB3|OuB4m0z!%gtQK^xc?#KKom_!1(((`*-64 z!~Zp3uV;V9u-(*t2A|1x`|fM5TiD-M+22Rl-{Kht--rEukmXv~-?!PXzp`Inv%f2u zK8xvvKeR>r`;X0LKkqry+&5faYvvE9nfZr$Gmoe-^Md`&JY~6=&)L_^KOA7@l`J=x zXFM z7Mb}ymOHJ%T=zWK%{cs%j!;f6o^SK}1zvleT<@`2te!pP3^Er>3bACUUJTm=!&hOz& zzn1+iVSlHvzr)$zeD?QA_IC#RJC6Nb&UVx6?{Vz!cP#fN`&-8TE@XdSW4YtluOHa2 zSJ|(=Oh19?4NTvL`{Df+W`FpW>v|^l!;4(kJGrg}+z*x954&?+k7c=!xE~g?+$5H} ziu>Ua?uP`+-Nbd@iR&J4-Ctq)RHkpo^rQH`?B=RqA=cYMK6kd^b4KQ^<{G?=&!g9w z?=`-j&HRt^Tyc%LKY8L{bIxwg_siS<$|OXb_Abq+m{*nbNG7( z3;6z_n(cnb^GH6o-#OIq59j-ekJz8t2O9coeEuKLalgg)1FzF$3Y zrip7;zVG{<`F>!&fo$jRoVQl~zEBQ-59y8BM*a+rV?2K!Xwy>j{H3|d^l@T>nS(|% zf6D#+8RPer8~Pf?SM&4O*{cn`^*}T4+hXQVmYVr3zMj-(uD@Svp6_4E&zt)3^P}oU zbI#4;=SnX#{amJ>#m|+-@O&fZXCgo6Szlw~Ie_KgXZed+{(P2ug6Grt`Na@^zH|bA ze{vds|8XO~-}?Li$KIR3do_Lk|91#YNT}}QzTfxiaMLCwnlyKl%GIcnbel9#DWyW* zN)tkbLL!m~8IlgtV5-bh`cNcO_!u&i_`lZLYoD{v`<`3f<26c%S#V$9dZBMbf@l#+^Svw|_48v6jpIsMRBN98Z}0SR&UOtM$*8xWAsK_m7Rj z_j2JoSon4kzSZRZNlt6wD*Zd9KVGb#b6hKNtdaXPo#lR6dFk&b{{2hJ&1dNA)#ESL z{%#X_K@06y#(3>-vD_Cs<8FO@b=wa4{X38UW+8E|{0@GE+_zqKskYm6g}xp+sg~CJ z_bIykTm>JY8~&mFxnJ%Bek6RC%lcm- z>wlrFdk!w|=s5VG+$S6-`LkWF+sF0Q{`VNE%b(^}6RtU7k8b zpQpYZtM8*slk>|`xvx?nc3u(rAhA=fo6hSI;?EbwdVFhTY^JH03pewLCzLNM{7&?L5dFA3k6KIaZ{IHY*-?&Dy(Ld?l;iL_B0nX0 z_U!rEZY|jlAC+>c9FGUg)NvFgblHEX-cO6=JU67dK7L&z_tR>M-TXG%t}DOuTqg6L zC&!bMWn8g*f0{d1+s%^a+tVeEQzed6X)iSXOSw?y%M-uvm$IvTzuG2wGD`IRHBuj^ zUJ-ee99KV(c*lON_qQTh&;Ankaf5aI6`s^(L%AM%Qm!}p$n{3CTt~E(>xdsZ>Fb2* za-H#o^nWJ(tK|CTM7iF`k>fyq3(fT|;d+Ajdzx^&K)Br_+_p%6;UGP3m&83z+OwBv zzt5ba%P&^wa_HA7o#{BxM)v2Yq?{;RE|lL{ewN=^cFOtnVfnokCI2okLhQGY>&U<4 z`2M*Z{||dW&(~Xc{Uz6#O=LfLbGq(dDEYQ+j+T#?=M^@|^9n!8^9pUm|H`rsU&#HU zSu*cXxo&%1<{Kk&LazI+6S=qC#~OW)p0CFBx~wC|*`MWn@V(qOYbW+<%60J(a{ulG zxsHBB?ADif$H@KRrsCgkaz86&yw3OYm+0%Zfq(Yr-z$!k?-PY*>gNEq^w8xCBA?Y? z%N5SjGryOV1O>ue=nK$D0!Y?y!g9A{C!LOJxTmM zL;QVR#*G($zY)J)6TfzgzgI~6xzc{6_*-7Sj|~<7hKs+Si<}UDj}w2>#NXyJ@1MfA zSp0oe{C!INJxcsl;_s6(u2}qiSNvKbe(ex{&z1HmoZ z&XRXu%YJui4}HApCHeWQ?5`io`Sv>bzBKb3z26=)UhA*8R3ES3H^29`)7O1m+-cxcuy;9Cshs$+KUGeuXIq&U~^JMF`dfuPq_tS&rIrfE1^zV=704D|~;I`_#|Ned^V6f4aHc zpH6l4{(0@!`nYhNaQtP3=6}*oeVtrSo_Eui$9hWC`*4J_Aa^6MBdMEv$^$r)k!$t2LIc}q5y$*7m{7v%UYPp{5 zy+)5;DD#~u*DZ@=9bb_0X7l|;%1zR~NaTgXbUY7s*5#KH|C91N*KN{&lavcZZ@K7= z5xt`%z8gd@UD~^~)^_`J(dD^vUc0%cmS@WIMVm!$m*{N}y(8p#pL%i}K3v-Ci2gc} z+lYL>%zuMC*L3J5dY+A4b$R?4T~3ta`PCv{f4**iP2}t3cZ>xsb$dDScc{$smwewD zE&gW6xQoS~F(N-8<5r7&lf=7C>>MQirHg+t(R)+uTrP5kaClMV9>Qa``1zptd6S%% zE|uR|hsu4GPCax!-Pc!_b!5HjO%NWUf3fKI5dDWmzf)VS_dz#Zz9aKyiJvXS-cre{ zt#X`tT=tvq#qP6Ww~26gv$gi;r!KmDTAmO2w3n7AU7){5v}~ixsavOGWa)p=U( zI6(XLop3!_cy1Q|o)mts%l_3z;)zK-RU}^<$@koWavc(vJnAj>QYCLj$#uX-VsE6_ zt1I^M#9jxn7nl8Rg_O6-ezZXJFB1K=V($#GS4H~&ka=r~z1HGiRq?N@`1iZSJ5>C8 zPwZVF_6o#ahRoMW?48+M^V=!@eJbnwR4d*7ndJLR;&;jz-CjZRd$GvfW&Pi{MEAFo z`FcwKRGIG&kynWSjn35i9VCy($b6Lwb^9@5?|Je28PQuSdQZyu-qJoz+OuSQ9T{IF z@=%edNt{h(+-~uwhuGUL@qZ)swn+Tt#sBIO|HC5pk@){5_B(ac{`Zsq>m~m5vAX@6 zvvqm6%yV3^w)d^Xd6jTTh`dbZ zZ6@tK#O^E7|F-lG7x{LPmFTw?{qse>T;$_h>izheHoA<1Y3c9Dns60{l3>SYN7Cy5iZ*P=5IbZgp`VzU~UU3GcFIlBDxJn0{$$3HCgj=n^%=fA{moiSQ|T+XwbME-P;zAk)2 zo|pMW^7<1wf4Fk~_*2dwZ^-$hqwJrr3AgmtDa|SV%Oy{46kfk|*6k;C*QM&I%O$P# z@2qcj(dC@(x-96W%MEheJV(|uL%3BCZuMkc?j5TCPN}Elb%XKxxt~GuJV#IY{idB< z*WV)7^+VygV0mpF;+NWk0IbL!U2u%YE~KU9{X!?$6Edspa9~&v(Let>o)#l1EkKcyxjA=r6~w z3+1?VkM#f5Psg=U`j^Xnho8jWmtyZ2(f>xq-yzR|kCbuqr2T!-`&rhfK=!kNl6QAW zzV(qj+bH{cAL+kU`p=R6Tjls$LFV~O{HZ7N93;<|Pm}&9#E;$5-)Df1?^o%6Q118t zDe>(TdyeQgl=)wf>ydFXZn4yzf8tAlke-h%DUEbDRmuL6VjFp%05xvfGKO?`jK5kd; zqRTV7>#{{pU4AIzFOmFeBKh~F*uQYJ_ItG)SAM-j%b&>paEIhU$1`;Mi_+h`o0f~D z{|e#!y~v&9Jn^QSC$5zFJ4qa^g-;V%kLhxp`b+k!mn6Y& zFY@!EzftrDiabl?V`Y3J(O)j(=Zbue^p6(#HR)e2^5??uMmY|&5&Pw2+`Xdzv$Ri_ z_AjKpsGs)#Pl<23=&cn0+KPU$%=e;iriZA;|OVwOZkw*l_vdnh&)O950mlrr2l7;YskD?W!`Dh zK1asoiriSnwUYMN#r~1fK3dubNW9-myvItse~W%?(f>^59VhJ{$~^DN__@*_m;24b zmJ~p!&=(9g|pQ*ZZ)MaqA-n(A>te@p2Ii-a$#0YIMkfkKV~cE^D zU(0FYdp16X^S+j5-S(s(bLmBI+6JReZKajeXMd9Q?7q_K=7^PCl0LO1e@e5nFYV#iq75)h zVq`yWyDyfKb$rWY&Gh!Q>Za|Vmi8Hw*x0gNH$2NSpP!RGV3|I98|}v(rpcK-9^QqO-xAYFLvKf-MxT9Y3y#>^ET(_YR}4n$pOpLJJH_}<<}hQ=fF1hu{SVnQcB#~) z5;t<4x51jN`@dLEjHGiNdA=`MTiO+RV%|DpRmzsmp!Bi(ZC1%vwVtiFl3PoYldY9)bZJ)Y_C3##+)E=9ciH1hdX$_qVK!_FR8O@&rf*-y8Qr~= z#+E6K{(-ZvA@ScTOW)Jzn@cOj0=Bip{-Em-*FOHIwoJ;i9f&&68cxRO2YYSbg7$-YX0%=Y zqp>CO-?m(qy51wgMwHxF%s#)Jvd!B6!y~a<{Ud-GXWQ6gog+2-j!(6u--$=k$gf8z z7QLk!-KFEZdA!DZo;{huu^3xB>7(a0duDP;7U)=O+HH%z$NI`5z;`8SCf4wFJ#YE0 zMB)vuZ|3bb-iGd>G#~BRVaItIMSWpDQD4}Y#5^-9QKKbvY9xKw6Ul%*uHJs3LwP|S zn~$GGC0k1N=~$C(gtz`DMwiWoO`m)$%V-mQX{EMh_L*b?;WHUqd+Fu;3d_jEk}4F% z4vu99Q!cR$9Vh#@@zQv`otfBMqhUNXB^@RFBSrEY+Mdz1OGBwNyE-BoL3>)_d#WXV z<1M{B$2&8Z?y>FtKG*#{*gLzGT$7S5Uo&9|?11Ac`ZF)6c>v&@$LRV8Kn@(pfde^kAO{ZQz=0e%kOK#D;6M%> z$bkbna3BW`Dhh8c5-R!B-f+pCfi7sjm_lteUb4HRw{kU5Ql9lnC&*Zo^0Em)2=7$l_vjRjVW#ZRzm`C|b zag}9E)cE$qZ%=(u=d;Jz@tL_yY3qg6?Xh9~c3WA`Irdny7Ub8ye(doF>fy(Q16(3- zIV9z8dW<(cy>=|+kd)NLR8Omb>Os0%8`Y{@O&>+g^Qn$Yu3~&n#-|QGB==8}2PMg) zlH{==a$U3;d(>agl8dc6&1Ljx9#f||Or6G?dNJzcD}8KVjcj~1vhmf(##dV=Uu~Iu zHFB|4H(Y35GY{3x98@>N^$i_D# z8{dp`9^(Y+sMUMoot(SvTf>Q+tkM<)yej0_}I3MTx|7`ZPQM+ zO`U9;I@z}CWV-=AwrwL9TYY5Pw3BU9C)=h@w(UCEZitU<+sMUMAK5nTWZTrqwyBeC zQzw1;;841N52g4MkF#(!k(P~5TYQG&leih@vb4lAy#0i?fAIDQ(o7uB+h(+-))VmQ zj?WeNBo?vW%e2M+)jsV^d@iPT{xhJ&YVQ45)9 zv94&Z&f61t+lIE~@u`PTAL^aLnh)~!ZQlM@Jx$pDSw8u`{O`n66a3D`=ThRhfZ4sk z+kf*mor!1i7JC|W&Y&&5rtdU-`ccaa*3^Fz{2tZ+muzy}I$|9wM@jK%WIa`?G; zvB&?*e?_^8ay9Ns6vYyMr4-dWbWqjo^651XN!(999oD;QdiTmHhZm*YSfePlS5a!u zE-5Ixq&Tx{6m}>&f~0ecQhPf$*Jv?)@;#MP8qKMJrt`X{bxkdxYSp$~Q@SSp#=m`^ zW#ivooeo{=RZI+PG(BESWqbhWeD4+X3|( zsXjU8o{9P_s$UfYvQ^9|Q4OOz)R{ghzZ*UsT9Cy?T{6gpQ!xn#MPj6&TI!%0nV?8U zP`waTj||m4Lv{5cYK1ODt0T&whj5C_!-lWB3 zciz1OUYg|?rM>6n7^%JA`*Muupf15A92AL>f=a*wVj0J=ph7Z&N+76-8S3&3HNlJM zDs&-QYdI$R5!uUexekbzV}cIIT8^vO^GPtqo|72K^Xp*&4o_u=Q6U+g&w%ICGSrj| zHQDq026P4Y>uJ8{?i9F)wcs6lvhTWc7ag6hilrp7aU`gRV^V6jsV&EJfTFjjU&FE7 z2=g2ZiIHNt9TpJ6O&kI$BqNp^5X;OAb*&f3e6$Axndt{&FTu5Ci{nO);|^HoI7o~X z$NjJX_ZPDJsE~{}<{^$-GSp2OYPJ{31Lz9w+_(6lxHnmAGP`WC+{&>mg?WyJ#7MEM zgaw4~D2IRw$%thEVwsjypMyr(m7qATd%L>tO-zuVMF5 zAsKPphdA!dQ1@i0ge7@i52n9;|a5Bu0wk6Ig)zAF%tVkc>E1Adcl3 z>ah&i#OP;OfcbAx@Wm*}V6+yDR%fVH9-v>e-mkj&4Mh;pY8~73lpABt^A@1r zq3JxA1n7Amkew!CgU@KILiqeaww@2?vkQIhb3UJS%;!(EG9MBn@hP9id{R&_ACkf6 zb?|vLL%p1#Hh73CXw{0ksDvVj=v9P7S0j`|Z&`>cL(_RPBY1Rs%SYtOK+d6;HD_kD zA%xMPWbCbQMu(x#ebZ<31~WPwt;~qTNQ|;!0XcLu3T8wy7`+chn={lV4^WQQJ4P3| zD1v}C>)1GlwpxH<&~&yW0ov*VvU5mmFrQ5!eBxwlYdD`g^toGnJ|8fje6%tj5+m_B z85Y2&00r|Q8GLqt&*vHH(+suULsVC**3-o)D1wMSM@S}zzP1q6hovnt;~qTNQ_#+0vI(x!Hh@-qaVR&XNLOD z1JqjUwb4Z(iXfn!IyTOsUo1dvq3Qgb1n3tZkex$fgZX?H!siUK^-DOPcIb0|_WAt8 ze9lBG^C2-3pKh=KK4+m|J|u(B-{7-5L+$eTbk}<4=%NRTAfMfc$0Sf%rhg*q2~8(8 zGk79P%k=Lw$Ush@T^ce0+Vl0hIkWX5>uH&xXSQ?E=cZRemBMLVh(5QXPpbmcx(KaIi^NE@#=!z;U5tWhkqlZ#fmYQ_RmB4~Uh7TJ#bqdh zz^Ve6$*<}bu*;$8RLcyWh$iIHgC2@9Y#4+YaA8MF#O>$pr+(*t&w)?28HyHNyz9cSfN zZ41~v&~#4744wdM`@mco$oW;XtogNwtk(`Fb}#ze6MSN|nAl>pGBFY(5qks{K4gwdY#sp)=l;He(Y{L z$uYXA-c|t8P4zaYo15x$_jFVJEDq{DOu|8t7%8YvU;#mWz_Fl0GJ@)cpt@wLPMNC6 zi|A8yAzJIUVHZCldo?@hfM_+{A{~%*tF1eG{uzw1=Ojk*{0CTo!(Xz)sE`cL`@-`+ znW}fD>XoT_c+UTb-r#cd@tt>j!%I4)&~o(B-t%4D9@=}pi(7Iz>ftwzRQyWf{nAm) zq5XoXI5ZL?g;p+|L;KT&MlwPhjL-&UssWj*pBL9b=t9iaq73rmvKM854vQD1pAO4f zlp*Z-!7#?2lNibKBemz1*kLRR$?*JQcs?RiU6iSYd7dAIu3$Qi@I7}gf{R!YK9&yi zT`zepm{Q_i?kJAsXqe|%NQ@Lq3>FYV28VzO$%y4r#4;vRjrIbGqdgeN7(Wnu2}YMK zj&U4E9;|a5Bu0wkL|B0P4!e&E$%rF?I3{MQ%QMvkFO-we70jlIekktc)|yNxTP#;` zEOlU>V<9n8ET_W)LO7K}K!s$)G8M60ov9{yfiy*XFp#VLKxm4UpAUF&0TXP};Z->@?on;m|>?SejcmVdszkr{PGD>EW75~K5B0cd)l;PWlX zV00T8&C67`c!2t9y<%PTLlFctPshezusp3*a*p1@j>pe3pRE;!L$DQ{C+$8m(0?(Zv`PK}3rY zlKD!t)Iu~Cn$826!98iIkI0pQoI{H=XJ&MF2%}5M*wS!DMkIsL<6!h?rds9!nx^%p>tY6qAfQKeY@9&*yn_&*x6EzAl{DUFdVy`oz{S zv4v=5VkAZ)wiFgX>|PX1jARg74`MHRxE|C>59#7z6hT}sTIuw%g=-l!osCJjUiNX> z=_EGxoz^2{{N-?3kD|}r=+oN3v>rn%(;_hvtyQo9S}Ra6Es{a&9ng9!Q@!BqDmX9$J|eiIHg4EXTC6P%tf$L91p~p~}xv@hp{_rE;=VR+hON z>p;OdF3Z^|UzuX`a9Dnpe-k>MrH^FvRWKKI^SE11){;pJ@fC4WzMF;SyXo8F&dMQA zzFFT2>n?6_PmF$At%X_L9bFqNP6p%1njCNK_ib0u0qb z!Bj{Fl~X{aZkDQ(rB2LJwX;;MEOopGrU`VMQ?r~yv-EdKhrraez|^t8oM?fm?SrZ1 zSC8K#BmU0p(P@sU-BU}@(Jelm`b?(jU{-Z)N0!bi{iCOCMEHxoZjmuJFy;$ytLNJzzek|_gaMau) znqUPp&I)F1iD0hcU><;F4u-@?!K{P@#ITHGK!s!ka}9!-o~5Q{sjIWpBrg&dy$IA= zmFZR_Q>{p@_9LM)$=`Z!n^Yo>YdMamV3*?{F;W~a!2;Z0&F-T@GUAwnIA&$38?w|) zFNpQ%3I;LD55i8Z8$x54St5p;IED={%Q27`DTeo80j|HsuA@RSVz?7A+>xbj&r-K$ zskvSlo6#H0syo8NxZMxKz12#pxg`R*iv#%=409kPMhavHEWrN{*?&|>Mj#I&kO#8V zk}S12OD)P$cYCpX2?gijEaxx#a^?X)9CrzPHHW^%IvzgsE%Fb2ck6KW>CpEL=5rq| zap==6{-N(7=J73*nFooHcHJz@;3}~AS6Z#q{cxU$YCfr5Rwtd^9W>JmRgggp3PFv zWT~gTSTdmCyqM)=N;rI-y3P;BT?1du!al3x;e~z1U)ZN~IQz7)IhfCVvBbja7Jp%1 zU>?UnnR$>HiAQZ%z{2LEU>+oc$LrwnYLK1=h|HUv`K$&5X7zsv4 zSO9}U6uhb=1I9MM_%KUt@kpG7b|BL0c@kZFe&}Pc*K>=%o^rALF}qp>1MDh^kzDN! z3vjh7dx#3jaP>>L`bC!dEK7ajd3zqZoUfC1#V>q^-OsFb`{X~eZpE0={kp`u=@x(8 zzG4{tpv*8xj09siEP%lUD0tmS28^A6@m-es#v?HT?LcI$+jl+&d)>Y%v2H)Gt0Q56 zT_rJ+t5?7RTphz6qCzrU{R6K4mZg5lQa^d#PSmPb>LP)H_9Xv->)&MA=waF2S^jfs zS3%SHGYgk;I?%e5pu7D*T^UF_tNV)|srwV^xG%s*8FPzr5*gc_1vn)ixSotY_s=Zv zv9w*x=xVewBN8Jqnhgs;GXn)LC&^$`A-hl=lC2KPR_WO)HQU?~nWMFD(#6dvf|w4; z)<-46R5{znbPF_{O4-3Hsmj^@ofH|!m=1yw+)3dBb9y%4N#Spisc26|HkS-n&JIO3 z4}ET>Y!6w*Y>M<&v@$XhBO$vN7GP)r3PwgUkR1hNRkKwU57uI>cb_hnpa{aMs^jF} z394JL?uVvREjyS~)qPm@&LcLMRh1Av50I_u;e3{&&#mV3Ihy%Ah*su9VkAB;EP&6W zD3}k);FAYFv21lrw#xPpJ*8Ej*2Oa@f{0=kqM8<>RnT;fP0FX5;fTZrBRa-Pr|b}1 z&ywAm;kZ_#&pp=1mCv}=pp|iv7zx*humD`|qF`Jk1J{|rbw;)-%vP>MELmaV#Et4J)nnQBwUSP0k}>^!MI2UuB(A-QnpHDtBKj_a*tSJt=&Wyr=tiGn}n!L zhE21GHHD@#HR-57%_ru{K+dp)#?HtlTF5RBLDq~6PYXxZ9DVLoAK4T})&i}JjKoOD z&VmIXD@4J_NCvW5Kz2j6nwhPx^>`I&)w6Zc2}O|C4LVfLu$wGiouTQ>N#b>r&&$p* zvB9`zTDYza!PSNA-V~0jEBf3yKCan}s~cJw7m1N@^@j!E>V<-Fkqlf5f$Pp}bw{?k zJzL%C5gVYj2kK%FiXgE&5tYfXMHaEa&~)y}4*u4$$S3B?K+do`GJ!_ep6<0HG9kzI&ZMn+;JWaD80$Sy{~$VdjVGx7E3!EE(Fwp!xxnxIuL)5YZ| zg1jCC0{pHsJ!NvtdBoy15t`1jBwmmByzC4U8;t9LZ11U*_SOBeQD3}(>ptTwawklgaovqw#^<=hs!ecgD516Bin@|Lq zt+H}#oyF{CXgX`NgFh0k^O?CakaO&5E5}?b$DXw6PlV*#Ei}oxaDsEu=dSe$u3>`n z(8>f!j6`rTEP&u0D3~D0Aov;xzLKprW~=qt>O~LVeOh~oF78JW#P^DhoDXVmTKFD- zrt?M;zBhe*cFKtjPPvU1vGrE{#SnT+X^uC;={<-(_YI%k>rC$vZuPiXgYmh{qh-wp!etho-Y7J9sN?tIy4qft+@mG<*Wr z!R(YTkb$k?P+mlzyTym{0YiBStqg_4NKoE_1weTP1w$bjP(A^ak3Ax9Yo&K|@h*xW zk&mrR`rIP237XDlNkl&PiP)JWHUdE2qw$}I1KEr|_cI^Jrwrs@Xk{QIMgsB~EC9%d zC>RLI0P-Dxe3Pxd_LzLG^}f)>4irHq-&k4lgT>@aXgWKygE#Je@R_(WkhA3LkSzI% z4Ezudr~FsH!$nd4a_5R{5x|;zsZ>hg?}{=FGz zaraQa5$`EmRr^nYHN4QqpbKH^ z&>B!^*?wsD%4MS2Jh)QBugeb!x$OB^7-P>#jO6*%umFcIV~0^88J-uw^W$<<%^a1V zqvD?PQ_ve+m*afr-I~_AHI zj2P=8#yUCb#2i)I3veE~5WKZIb^HMB)j3gzLdoaW_Up1b_1N=UVT?T|F_Pzx!2%p! z!VaTCGCXev&ri=$jdN7P9Cccbs_*&#I23{lbh_`q+Zc}0iI{erhW=W(r{(Z1ZQ6C} z`^_Os#19hbhy9v!h$}E3he%?i5MO`=MD{dCh6>3Du{}a;m!sO|s5UvORgP-mh4>;A zf+4oELTqb=*v5~=ZRLm9!fy@2%8p9$vazbYvi(DvLA*&ft!I z-MhH@fQ)s|LDHA}>1PZ2+-^DE?-*T~(N?rFBN8Jq`Vtm^W;+T#OOOmkeZZ)9j_TzB z`bz74t&4x72mI2uJThsNl5_}ktD3s5y^I^&Z7P4EHPIV3hXhen6+sZO>g zg!8F^K6kv&XB_j%Kr8bhF%q8wSOA|G3g$yH_)G(zDLHC#j=CyGUFlJ(rL|AcMQs#8 zN>dP(Nuz5lN+&|onURB2)hZk%QWA~nO6MA%k}Cr_jVAkO+^h6~ntxus(r@=tsty^x zCLGzx=yPZI$fh&0x@cu&Bt}Bk3>JXwG!%@CWFWf<$Y$rL8*|k49WG4Ikqlgmfa~rYbytpBkfY{%#Lm&$J#^6%MUdFth{|NxeHO7^&~z5(;7Y;D zu={*st_PTT-7#Lweg&%SJpU=y&Ua*=iPSj z(tJm0tG(ytXrsNKKKZJ>ys!H#4vOA(!$FZ4DJXey%>5h-q9YkWbwf~Ha#g2XRpdqV z7)8|4UXCt)MD}uY(gE>u6zPDh<>=0yKW;oHF_P!&U;z%h>@X@M!}GrIyicy`ovV7~ zsve&6&!N{j*@5@olK|PO2csWRn6x18AfLPXZEU1u- zpavtTLAh!`uIlGS^d`Cxt+jUy@*}dBV}K5bm!qE!$Xbpe?D<G?0z&wdLqLUO#BwQO8I!9@Ifpw09#7J@c4hwL9 zC%cad$%rF?I40(*%X8HPFO)yf72LTe`k}a&TWd0*Y_VL$vFw6*j)lZXv6RQ3p(2D- z6nruy8L>=7ELZ2MNnRio&>jrrYCjNrO(vBsj%gf6MOf!JNQ@Lm4Ol=NRoH!0NJbnt zAdZ>2>e^g2!wZF8Y7^YUXZoSI*IH{bqinI<$gyO?JjX&}q*!Xg0zx>3LqLUO#BwuY znUkw#d4V`+4+b*F55!)RS!Ijk7LMaMSm!uMj1)&bSb+N{u=}Wxj5rn`j`_Ljwp=yO z3*{88T3;9Rikskd>3qE^{21WET>qxkY0z};$_*YZ7Wx!i8OVpd+k6b}Jk*n4^wNNg zEzAYEk~ggyqR+i6*Sl$TCo^hA)@!Sa zGf)Hp-KS%lp0YOPJZJ%G2Tf;b5}*ftKz5pl4L+mY8^Y&Ivh`p%pZ4f;m->7jU_Kqt z%6v$S#HSA|fKPW6%!g#~c?Nu*%2g|K)d~+0y(0&z)+=#>h@L`7=DXl(3lY6F$9Xn4 zcywFsBXVUR=g>;cnHjAJVZ<-iSsl)ZUXoZ!#j0U2W8Ic%?k-Q9N7z{BZc^S@2 zVDv(+dd>qh8VUeZ>YH$0(6Mn2ZL|Q5#W-g}5}=JfAUlV|2J?9?gb%+6XJa@Yei6m@iKMQ^wX=Fr;+$>h*x3(>WN z=)K(F(Rj0u$d!SdLvL!%%;@zHM)blPXLC3sdhLz-p3i6#GrAtFoI@l=VstAkAmZ65 zIEP3EqitaHVXoTZ0g{*ISntFM0{T$L#yRwf1&Cgo<7`g?^obA1&LOeEe71z}SwOZv z3Fkwv#c{X$d_HDA^gSXzmp{cIlp$7HNWUBJWjb7sF%EQqWA8&=`ruhDJ@2U(hGB# z7>SXHeGCgQ^Z^PcMly(11hMilbN6n$R{BI2pP~rjDj%b?z>lHWlMc0TeFjaZauTjX zeOz{aiH&{Fug}T&q2aW?K%ZOLr&Wn*?LaHjA~6!JpJ4&CzD2>bNCvHHpmkJCRrP@V zqV;~&#cwErz>WeibNtG%fc*|lr$#Jz0?hD%xiXORtE#5H@5KHf>lxw1cA?L$;S;OQ z#QsDp6C*Jav4io4?;w`Ke|C=w$sm>sVmThJL$p$PT~t63#Fb;^SDuBdA~cOzTjzGA$A#(K;R$04Wy*=NHMK)d;j2#MG%VbxKUt z^{^G7*Eu<6-&FTwcTbfZgY@yV>l98_&g!aACbM9O?5!Dnr;&vkagRz6?@*ucury@&)aIxo3g_Q zfn<2z5uUe?sdh2dHm2Hm&Yywa;BvJ0op;;8OWNgWIofLP^-Xo{J>SJGxf~@Pg*l5u zYmcdTQAmswS}#~YMD)%m&NPw{S~rB&C8j#XRFN0gx#&X7*1g;=eq8pVbkbq*q7><{ ztVQY0p7(|^_MF5>p3`fm;CVlG7!{J?c^`P*JEnTYR1eQ{dXrQzoqGG8yS?BdR)mkG zJ$%`< zgTzR2EP@5NKcC%4g=EBWIpUZQQ{!T4tQX3?T6M85?n4ng|4z`W!uJiYw9davpy^DE z1vB$XpMom`c^4b!V{pf!o_yc%elm7t`1zJzw&hOr&$m}FqortNMkGdJv;r1@#(M=9 z$zU`MjHblYWDn4jT5qK;=v7=nKvQ&Vd;xro1&Cg*<=}6w1E;iWd_Z=Zhz&k^P7dMo zG}*c)oX<1pb7%N`rZb;aXk|VmM&h#p7QkmM3f`|t2A`Y3XHHDbim4ksL>sm0%er_4 zMG(;(gk&yx=UIqeg{Ct%7TlBO`G{N@$T>7ib7n?2gfOD_cRBOI8NH4^cdpOq7H0GY zTA2}vkr-`-1u)u#f*FwvMt6bHf|#1`0isuOLGL47Y(o(Qv_QwkIdqQ&=woO)cP9b5 z#|LERkl0{8^F#P-CtG-fXxKN*PtfPy?ekg4d_F}h^C2-3pPjIPxW7Wdd`JeL2f^oo zm|EiT`9bUbs0(^wSCG#Gh{q(*GK>(!h8(NtdiIIq<9mK@`gdrwIGKf6^Vvl>c(zQ}KT^xiWi0g4HomN`7 z4u+=lWD>5GJ}x_*#KykUI)sd`45w8deeRP!trbkG0$Q0CiIHd>1q;ZpLs2j-l0j=N zXswQ^RUWXTwO%z{R7Vj6w%W?C=Ph9LqBZBar2X%CADAlxIloqwHNP^*`t#w$GSTNg z=M!7U#In%J#7K-p>^N8eu{a7QMly(P1hMrVuH&^*fi7yH2;y3A<=3kgt`nf?ypn|L zRUem~Ut(k5^NU{c=DZqCi(c{OzT(q*nQ3|NXCpBZtr4&bS_4rqEs{a2YP?WYiL1ln zs&ZUajH~i-bGM9MQRN&JcRrM_Ol|4muqtu?CgEXmeI%o=f|XG>kGoZj(<8U^2Oe&D zG_NPB-|y=SqA$U$?osjN7ewn8|Ak*i#wnOFQ05#WF%lJe^ArqCK*3Z<29+F8$%?Ct zxT+pkM|()j^RM2z%U0wVx&M8 zzybof83hMIG6FdsfjDt>Y+U8VRm=Jb!6pdtKV(cktbV zN!?l{mR7g;OIyH17D1VbkQj-`W3T`s^uj47LNbV)0wQ(es!m*;7+1ADB9EgtxU_YB z9Bv&1YrbQjsCm%Z>c2W(Vf68Opq-Bu3(~0~UaR-gm{hNiukJ2am3C)j6)tj;pgg7+<0ntgORMSD%Ev zterIoKJ1)r9d^#rB&_5-hXeTvhB*)tBL$LNW8XV{IwnJS1;DV?b9-!2>0A8ODwZ)@t1ib(>V#s zOozlsbeh5fpq#=`P$3y~t^u9taWyrru8yloah34U@JpDkkd^L4T&DY6?3JFXvG7V? zZLRbqtDewctX0334oxvQ}&Eav)vErI##d3pHpIIWVc^p@76Bmh*;u@{vqL&eITqI+??m}D(;%a_e z-R4Df3A&uSlP--G_(8ez;iXC9+jLZv#PqcyCGc|MQm=WFFO0@vO84#($*WuZ ziFMO0{<=NJFy=v-VUQRJ#yzlrb(@cZ*NtSrZ~^1VxO&1Pu?X!zWUbqiJ_dW;o+z&Vj9170*q`mHW-)(oD zwR&s()pMWK#}E3l`3#y%|FRjp-dlqTrKpzUnWa`?7T)-JnTWCy2K=kPR@*fshy} z5PGc;0(p)7M}=er@;(CD99Ns->K!kN_q6I}UHl70@XpI-I7!D*dYS9ixc_j{2heo3 z#PLN<12~6{JX?JLt_-Bn?k0=CJ66=@zUNjlwlxlDC7(t55Pj~Jxc4m52h8Xrv@#_;TXo5I#SUtsUWfeng-9h0o`6=JOL;nGcDP_*6KA<4!@rd`JeLzrkmBTvUKEu2WDjE|P&O8@Mv_RE<1UEl(Zg5o@Zo zo9UuCiXgE}L}fB8*CN&en$9tK!7p&RJ~3AYa)#B=*cn+h3)xX2$Xb%&+;C*A(B~fG zBgNw!%f1G4M(5b*hkigk&QqrBO@^qvT3jY2v?$DWF!MwA&|AsQ!VpU zbB`Cjs0*qyba4%eAg|UsRL-z=7O!ie>70>=yWaZJp%+~`w6l20KxWj^V$?i@(RF03 zT{xqe=yT8T8MS3b*Q1pgkr;{5?XZBr=b&IlB!f{GFzS@2it)G>t7U1Y3#IHQH=bG!MBx-z4?(aMZSjKs)= z1u%L91v4TUj7Ead@H};4o*J5`278#E(%SS=FbsMIMG(_)L}hlp(H5pv&~!%S1uw%# zTbN`Z?|K(%){JbZg=}yLvS-Qg=x}7K(dUlxkzLHl)}WPrH4nS0?dF_`K|cyVzh{<1Jj5hTwXO z>?Xo-y^TKiN*~um#`O+b85fC>aD4&`phRy=;|wDixNZQhnR)8kJT)UvP0LeLJZPWl z0iWsOa}+^nGZC0cve_22FQDnn$_w5=o9#n$WgsWnwVFIrn_*F#X4R*J5ZpnN%nm2` zCHmZ1KEWHAAiWcf36dCz;BT-1g7oq-CP*>}E&###dFr-2H7`%y;^F&UYyY8(T_}S1 z=Ih8g=N4M{{)DD;R}#L3K0Z6=#0Jy5%_26>s^1bqZ#T`cFq|H}7|p%Qr*|jQ`x~uH zkHkpyN_p?t1E9AgPc8Pi?d`o|OAwDqyN4`p{NAw#^Md#G9`d=lGLX}5v4&6Jy!RUM z%f=oGhr%x#d(elnl%aSp8zV6ilzhDE2Pu_VlQq}1bp@~B7TSgll37Y>SGCOv9p z(h7^nanN+0NFuVrCt_!k*a!eQp2n{T2SRT}bD!{mEN39}HZ;x>5+ebr4+{W7uSa7b zBm>B509lo%p7xlWs`coVV^D8^BFJQwl_l#eCJmwKtj!DFNnGbMab+N9$*ONiF9f}~47p*LL z*&=c#G@XrkxZ|oXozA1n%a<)8GBA)D?P<`<;S@Tc&)w)#*uWI%ZD&k@#7Gnd!vZ2Z z9|cn&85BMRh3$E2Tb}wbPi^sV3_-8+L7tAOFU7RoifNmq2mR3gp@5;EJ8;MKZ+^yS zi{BXX5>&qJs^9ba8AnHN8{_Cmj1=8CSU`02MlgrbJ5?T2RX)L-f#`1J6FUzeXVzGcrRz!-Z@VkFO}!2&#=$PS}IGCcncp8t}ke#%on zfn4;F5lc_TcK5-)Wu2^!6QideE-aQXuf|_(uJl|IX{?^ zhvxe?C1oHVQxAp_+^OT7Ea%s~v+z@7>`?ljp_aV2{WSXA%K6@n$V$xU8MHDZ5+gBs z2^N564GP}(NCu;$!RW|*b%Y0Kz1G{Hi;XCPfR5Dh@FiUh3((8ZbgCx-s^J5&vqEez zpCdx}yh65Wg!6e7eQtH1Pc`QA8d{kTiIMoc4-4S)77FG=GWg_!Pds1c=BpeJ(Fa;} zi!QdJ2qKCjBy;uVScpD^rc*ONxZ^lJB3A}-4(0k>+#J8|<hjZv;3($|ybn4{e zkfV<*gXp+_vIR&6a^lnqf$}pMI5`~3FX(gY_)tz_D8HhWp^z8}N`(pxB?SdTAsJ9k z2b9M7s$sr5Enn65&{Wjgm2^=VMG#G6L}hZPxrOF1XgbaEgJ+fI78)~<&MFOsFa5Rc zY59DYpWo~5H;0^8^v|p~?zG1eSEcEihl4y4eQq-!WK#xt6j~W1iIG6YU;$ItK*1nM z2FNo3@{D{{n6FxU6ysVoPZ#+pf)vk?NK@A0IdF?&O=vnDk|=icDat{LPtC>#K`itk zw%&J$1vFd7aEP_g=XUTRwr7YZpp_w#7ztuSSOCO2C>SEifY=KVd*rL``KoKa>g;iB zq_rFCq6vy1#~ujQWaD`j$EMJ9dM9x_&*$ixfs~EiePV7`A7p30IV2mcs~q!tR7;xl zyl|YY(C7B{ah}UKTcee6k{Ai+*{}edXP{u5Bm?IKz&S8q_0Lzu9?MQzwX-g|pa`-Y zDDhHG4z*ZzgQhbiiRDnArJa+;2IXXbA7yb_QTC)chlZo<%ixXqu-< z5Nc8C=~z6_DoSn2kRB`n$)}|gg1@Zl1puUL;>p08F-mXhqSWS`sgx;EGPPY%YAag9 zb^!DaGWD$j^+thutw6nEGWAUNtw5%JK+&|PF`QbGsqa#2M+D2=MXWSn28|&t{%x>pz+XqiLE>nCATg_cgr_Xc}JfywCG| zSjs$mOCB8#M$$%n&)*rJNrum(;Pc2@YPjd~PiS{8f`|AY zV5THy!9{i*Ze1UDN7kYj!n2F+aMbUn`p(K7TCjGb(d_Hbu)w~OSXN($5#P~RaTFs^ zFkh14Yn$4Is#R^(qPF3C3EJHjwY|r9g>UoPn(s}-w^eP!S1ZC{{86UQx3D%%H3pX0 zXA;Zm^Izu{rS>UGJ&%0t13#uVNR!8<0KhJlM>`jOF23ftK(U;VUr3t?OTsg%( zy7$zUW9s6A6F@)b$liW0ZV}X*e$|mx(&~~0boa+0h3yOwC9ubNuTc%MJ&3GPFTfkL=>~0LKB?5S zRIoO6{FO=ELDp;1TG2j{*t#_Z7b*oj%>pycon&K4zP_$lP8q1(p`C_L@QJ&ifkU<) z$2)dByQGG=(<@fW<%62uQZd=Ch@;)eFDLb+|T8Q8du6E$g1F(hPaj})9?CcOf?M?-9hx)*a znWY;E53Nqh7k8FI0q%5RceD_}opacohhYo<%WQ1LogOX;lvzoo##1SC56iYpJJypO z(?SHt&S%FSW5*ux9qWq|N>S<%mzv;S!>4F6aw?{eL64JMz^yo?ILje&`pfC?La={A z+Ny9{qm?{j1#P{q)M~KZzJR-2(udgKNm8LR+C`3ws&T>eSClD+yVOeqo;CwUIOMKr z7rl{P4{G!bX%u*R7qh>{U%`MX6(% zJ+s)`Su*Spd^xjU4a4{q8Cyw;D;!#mRhTR#QHgSt`XC*qcM@uEv<6K;G?5+9LWIRn zT#d64JMkRs6{@w^iW7+`=)#$p&WyAeeBJE42n9Y>Y3~jt?`RNq7v5!rd14Vpxugtd z8>~mEZP2B)^8(pOicnNJKx2bXvgI0WpwR`sjr+;QOJsx2U3>9kX=xLZ0r+mGH z99kYLRO$!v!}MW_6XI1gkuxieGrA#)GtU}l-hjmXzA}F5hA4i1Z~WW_n|RGQw#Lt$Uu z&gh0H&irbe`4l$s%mlW^nO)?}=V)-L73*e7&bx}VO?1P*O6g|r{nHyk!!Uw%>fv7{ z*J?@AW4Ybi^LJycQ8FbBFIO>*tsIVjoY{#~{3}OoH7e?a{tS~5j=y1o4+Xj*3XXJG z;zPlguvw_Sz}Db61YOS8XmF_&D`HA=CAA`@6yp#i5OH2hl=nu_P&Be0g--t}xuz91 zfQ4-69`u>-jEM@#HtbQvhlUX!`d3N5X(lRSl&44<#Et$jy9UDUD|kihDx+X_x*-a? zBVdBreFvNP|JY+|*i}UrVaiQD^^g+sgbxVmdNscnkB&4R>4qpCRW}~}$R6#qJgOlc zHA_CalM-n0!CgH1Nj%Ch9_fZC9vx#m`jtKU+46|)*%6~yG9yxweJM5FCiR>66*GS6 zhA4g=Yy8^9e*JFwRa5+Go=l3AK#H;teqq}|c>O7UImR#D5XG-r#;?>xlv97hvf6Dq zcLMqg($SaVQXiaXP>v+NXsV5ha}Y$+XLb!m9i;D)EetXW2OEtONrO6F8V?QAaS}SZ zrZ?g#3wSE*Jay1$OzB&YY2*ZYP9}A_J)s+-AgB)$yjzur%|dlBwr00FRZr4T7mZLj zhoYO#Un$2;pL|bcm$WVK8z-x*tz2jNlol=UNoiC8y5w^c6zsEZh~jf|m|&l)z-FO3 z3|r%K3q46|U9>^r9F1=6^Hkj0b4eTdZcZwN$tr6q*O}U;c?*0}8XW;$^0_Sv_E|SX z@wp>Ru+KGMvrtvT*7$suo}`m5I-_uM&}}%ct?ZIEAlAi)j{04aRqg@jN%=ZAGN4O7 zcSXTI>xL*k_ks!bIR=}B>KJT|&*$n%`sm_(6i!Wa8_sJgyQB?>b@3se`zEXW49@0i zI}Tm)xflietQ(^EJP;<>=UT8?sE)^0IoKG-hoRr42HG#F7iDEW$dqV3EUl78dIHqQ zy$g+dx*>{tBaM3}!X_Tm!Pa83mKB}SL?y6MJz ziSF`VH{ES7(Ot#s9vjvj^SUoZx92q6O-<9>PC^{SZ5#?-R^1SV+hmyFWjzHp@!m0P zRUK>$ysOCtYQXd^^`hh}m(+A49%L%zw0HHPMcz#@-sy%Y-d$t7YXqBkH9xlMRBViQ z*P`Dc&-KqBHR!7~DZxoPv$>=z^$tcz*IqV87kPP|@lrQL@p6{&vMFp9swUVP2WO+p zr3M_^c^}R*Qh8I+KOx}I->8|mG{?B48=|;0*SOT0U22J~YL1QZYaaPU4RVDNb4dk4 zdWG7!n9)}>UK=ht(blL9R0!Fv#y{N<#lJg@f9+utuUNxYwZ+Exw}AYk2CN?KuFYLi z(f;ul03J;TOOq5u4s0tk6O*?@nQ71WC(#!fGK$mdO*^%EklJH^`&(u>VUOJP~bN) z)`R#ct2>?1YnjJ$ZH>;M0R`Q7%XL;Fi>XzxY0#Z|IIhP~3AmBlpeJ=UVwD1}W2(o| z#BtQa5~QAr4Mn${S}6v$Tn(0~^$E1%UZ9?x&G4kv*2%N;K^CC%WXDk2KKf!^q{@AljE|Duy}B6Pt25VV&nwy=aCfD}@|sxIQ~$wyeF5aZ>u`CF z$Qcd1coum@&6LE8)sP zIc>EH`n~t8y4_?|>)^=!HmkhzK%4#A;WC~F3is<^%6J}VyI%(rdLB6AAGlm{e{YBV zop-FF)HCq~L+|f=Ho)V)e8qe%?RI7Txt^|=&%#3~bj5rYu9)wJkwSGBwrT-w=3^t* z$wkht9{K^3zpCQ$gSw|reu1uych&6BU@^oLvT}A&YG-E=BUVk<}}%3zjnAhzC667Tv;Ocyn-&qd;SBTOYS$lu;1|d6{Vhw^W=TBlm(ou&R=^- z=LgJ^_jc|@)j7Q9DqP*ABvO-d`Gx!ra@p4>_%)J7VFZ7TERm~ygCXwyl)BWoQyd&w zrUa62D*q=L=v}Dw+pis#3pH6RS;_wYz~zz&H~u6Br4Hf)_dT?@ zQ4ZWg_~~do&V~c`V=z*v9>G>UOq&O>kpnj#V}lS#VP^>P83*r_#A|e?fkxo_Fdb-J z8c4@R9A+QN>wvAF;ui)}oUED@r-=iHu9qE8_95fg4J1%hCO9DjWStIgG^;JcWy`dWAL{u`$^{3o6cAXxLNs(^#*%dp_+G9|BMe_;AD8Hkkq^jB>A zwbPRQvT!E*>F@0Rf!iV3Pk*w9?C0e~&eGrOarVDS>l-Qi>Cg0FiT;|8v!7&S|NAhA zC#kVjn`rY6HYWS&&-a`yXxLNs(_Eew_5&Ja_5&JRVn3L4#7O)!dc;WFTGD^)LKY!=57DILH~1P&+O0=0r<<%% z;n)V>kOnL~Nw( zuk~-X?1%A0SQx+NHP}gd7)F1XQ+gQXIgTGoo4nBvJe#paf10y5TR)X%tAK66BbNgy z;6NZgO#zto+{Yu(&*T;-*E1zXN7Oz9g9{U{jz)f6C^XsP=I`OeZ%O@v9|9mnkjeN+2+OnG8hQ z4`18gotFL3B!;~ozW&dA54j?K0~WC#@|q$a-XxLs!`;ZeX!{}kK_V=@je?VeWbB6( zku`WpDz@ri+LXh_?1%3{#i@*jJ?)1y%It?UIC(!b$Ex?pSm660SvKDX$pLGhf}{U} zzH1Eb<1TP0tmx?IZzqGJ%ap;g3k0SwlYvOPzz6%g)3OW5!kLxb^3U83$^Nadi0tR( zL@Ll#B%YP_Uw?pjc3` zV8>pt_l6yN#fH6H_5Z$SX3n13oihu$zyI@G?)BuG`ObOY?|kPwb!TUt=x5>B=2xK`J}J#fo1>vOLhn5TL%2N1rXO|HpBg^QV|SS_Vb4cnU_IS$lU ziJ_wNR18#(fPy{Z+rvr2dJ5!dHFkPc1MA@4b~V27<&Iqk$B+-(N3c0q-|YrgbR8Un zl_RiF5xx@(5hp5w%U!I1)1JFI`1GM!BDnZ9W_Rg58awR4$3?$K0L>bFe)?ZG+8%tI zfLG_=pZ`1CJw_n$0<)wX(WZ!pUqK*7pspf394QLBeZ{K-mB+&J7{W z&0rEl;*3ClB1`suxZyVfv6M3cv2gqdl#z}RC_{Yh;%^{sB_gin2!!#aFK*Ggf5_+> zU)0Po;|q;e$CrKt$#I|zTqJ;sjxRA#IRXmy1OT$tsnu@w!(5snT$~hFdXKu1-49*# zdj!y|ewh5fZnWJGoxo80VT=FHc8`A85{MX=MVlfX_|5{+5BFswH)|!p*9ZWK?;sFC z!fW)y0RY6e{E+76G3k%Q>4&Mvl067F{Q4nFIsK4@n=`>TdRfp+K>!*fFm39)+>p4_x$n1kkL0(CL5OXuBWS4d*%; z?)=}`?$Hmr01^E_v?=1DD=)bp9LPp)RzKhiBY?CQ{)m3SYxIMW04&Zu2x;ztOokzG z`T^e;kv$qW{Q3b)IsJfzLIOTjovNsW3pO6sV`Gka4xcdQLH?h@0-OYY57ARH~ z`9=zN={*W#yC1md_Xwa_{eUmS_@6e~?gw_mx%xr+e`mW#Kga+g`hjRuL~kZ9*$+ms zk(<>I_)-rbW#NzL2fRiHJo85b9xvB@LcCFeuYLjBU?RAl11B6a;R8H=tzix>EqjJA z>nvQly4qGHKOU47I~iwbCEgn2T3WHVv$SHB-2I7fhuP}byPNx(t9uJj&t2fIJH z==TVqS^ept|8=A7{$w|tYf2gM-`VcbsrYUmJS{HT6v4^&`Cx_-A&AS-yyOfsgKgfd zJ~oyG&Bz%15q*r;=wp=tEY6*aH1{YbMNOS9$ z)F5%{bttlkw;EXWdV%#~PFXL0nuuTW7~SL=rDAGJSma|~Gaw%NCr3=3@#z04on7DI z@<#D4kFnE3LB~x)6@=rOz}Y;bN#u1KML0LEyyJDZf?ntAtc2H3gyqfi z`VlN>M&{s;@H(&I_2mF8&OH@rZiLB6NF1;861jBHAHp2$mJ4U8Q4%q!<+!v&6V0(+AliJv2msMXrX1V)Lis?1h5AyHTlhW z@d`F~mG_AA|G&|iZ^zr=BZ5JFv55Ftm;dPsb-+s`@SaJ#<2j=hUuO3|ZMOYgczZx| zt(cqsJKH^0%zQZ?mdK)Spr%N>s_*;nC)-z>*c&Me2mx>@c7f?Z88pIOcZQ)an1$kR<0f3ueG#&`COA7^%mhb=suSF1md|lePW45JPH-_OIRXV%EN6Mw zpng6cTC%3rm@>$HdMsPq#6tI>uHwmhWp>%*19}EPw=y<3h26~BfoWwzCcA_}5}m?g zEYERJ&m^j=w$UjprVMO2n}#{9yPH$kEwo?sigV&hH)l3*(eDvJv!<|B|LaC;rZ6=a zTvOP&|LYa9rm(m-m&NrXt5)b*+^U@Szg{bQhOs# zHN5^H0E=_)N1D5p$vsFMuU}ymxf*}6AH{t?_pq?DydZ|ly>N^(XJe|0nIs-T?yZEk zXK^!$vq6gZWs^;(JsPy8OIj#fn{UF5TnD7B4%Kc>Ag=(0UbsH4>>iE&Gx6S-7jqq> zapwM4h|e?p6*?rxVc=U~ML&5+Q0`$rc@>4Gn4PDXo!CP?7=#ByH;mcM{cZxkq_Q zfiGClv(aBn5eF9nuC?>>>+>Yuhr5dx5RH3H#uq_}7nFFbCEmxoi)RYFt2m^Bb<%7?<(lcl+XUTnu~1zPN%HU)UE{GTR^a#Rgo6^JV4G+hvGog2O5ther&4Il^g}srm|FK~=6P9PH z&4Im{u#Tf|Q8{iU$KN)`7IJV5^y9F8ty<|Dwxe%XVecU9KQ`=Lgnb!fogb|AgV*t} zceAi7VE+ZIE*kGqjkuRa7#tZ92lo*tQQdHy>={J&#~EP)R%gTm%+1e3np58gaDmUSeTaFKFQtfG?{? zyh0;d+D5!aoQcge;`Kc;0>7Xg^~81>(aJXBE#j0m(}=eT>kMV@s2un)bt5Om=D@F! zCyq&7px`IQW4!GblOOC3m2P|eAb2ry> z-^Wq;dF}_~mi66*i=0%uzCRIXeKY&h&wFIVFU*~&`E;|&uX{xG8*?XetuFq5M`0N$ zfAGSIls|Ei)7JLff5^da95-jE|6AqwN9Fhz7kCSRL&+s_HkZQ(Vu>vl!dy}tVX+Jr ztLv~>>QW4Z#qyM5Qdlf0DJF--GLT}6@ZUfZ8^O#6gz}Pyix2J77m<FlIDR8v zTNS4raXQ#I?TM3Uy{(%-IuO>Gq&lh`oygJA=IBBW*I3gD8r`z8D|0965W1nW8;x)* z+KU&C_qyXEr?YKQ&)wnB)w-7oyEkFG*s%K$Hqnf)gYBcj1_|5MhRvYHsZ^$#EyQfy z>}=V%5N|f|>*YH3eOcJmMt*U*pK3%7jo8aJqAzi}AYz+iL_fkh70p#S`jex(&5=ir z>}GQ0s~iO?MXmTW)gLTy@Qenpsc5fTDn6Qaf5jxm$EbMAn zzXlo4+=*(STcAzYBdUX$J5k%W)T{*$L1Eb-6M5k@$Ru3k^tL@WWp_AqjXqW7I8@~* zA;&&8$8>Te8a{L!hp8N;D#r|R^szZ+kt5MLjV=NXS2<>@9CL7i)sW*lE)uf2AmD09 zECslvFv4OXK+z0~xtwAkET&_MNntT-QcMnu>55{Du$W>fwhW7Dfnuw$82Txugv9_% zv2|FClN8&8#c)P3H7o`difzN9i&1PB7TtnkT3EC*#r9#*927f*h1a+QV*PTQ+8u=p z^*FS)Q^>KO&2btz z5}jb{HhIfcj?-0+739dVIaZRRxy$P_RoJr#yT1*44mFM!SE<>~WwyR{w$-?BPgj16 zx-}}!`NZjG<6KCb$^^lx>jM`N*0J?smE#g}-{!cI z9L*j1*R!x|?)P)%2GxkGXv6`w5gUnW-_D#tc*46-?%BuApXo^DupO67Q3<#>i1gKduI$dPEW(K+*ZmE#4K<3(}| zu{mBQN1}S@I9^dF^)bh`(vXXxoT? zcgF}_k1+b~i4i7p%T^2E0$W?B5xM!x=0=ZOTd~FCR?!HH4IV`^EH-5n17Wd|qL>sG zn;(kFVX;S{*di?U6%<>B#qytGtFTz5Q%nhq#Wcm%VX*+F*d{C%xfD~wVx3B{ZCETP zDYgrXRUgH)uvmLhY#$cu7K$ChVtGNaV_2*LD0T{qnVVwgu$XNrb_t6)k7C!bn3^bd z3yT?q;$C4f&{OOl7K1az9$_&=QtTNP!y3h2VKEd@+&e5r42r$OqL)+LCoFmh#XeyX zI1SSh7wWEjALoOK@6cFcSKf-*i|lYp;l&vHq75!&KS<@p zw=s59D9)?(fUNk z(Ou=}p>p&j$9S7#Z*nyE)SvxNi+xO z{FhBwr;YYiIrbyRAvVYUyThTIXZotJ{RlhJhV4(-L`|=QJ%F%|>3J$gJ~<}Y9EIfQ z(#$DgfXXpYY8Av$}vpk7*38UHbENT_z31s z6xOiq9w78<4~2OMCF)9j%hZ>VdQuq!KtC{Ifqh}V}{Bx zlN{4+j>E}udowv^s~mGwjw8r%n9Wf}jzqrF^_HVl*mA;_+OQRbP2?V3xKxHCt3$EW;F84%i-iV7Gb|Pp6a!(g z9-x>M7SlGxJ}jb@Vu!E@DvBM$qU|Ym3XArl*f}iR$~71rkmFRp78mLo zEYta9$l!?KU}<7qje(23$0IG0}*^!@jrIY)ync+=g93*yc`DO9|`5)-sjj zIC9LkIZhx)b0^#rRgRNXj+4nT$L2VN9EpZ>-7s~k3VRx1kFa4+C#-7<^V^-RVD9El zVQ0_?$C)d6;WXHpxX3xuw&-j%+c|2sRm@gqXFCrU2~E)rMXOcVHH1CNhP{BWiQKG% zy-?MRv6d^j;wS;vXcd5#889CK{6e+fc2Z)o% z1v>K{B&_4+hg6P-$#JyJ@hCYG?VoiVkEtAws~p?Nag5FJ_mE$Ls<7aX-*&M%;BayFk9KWd?zpEU7kYlmU@fSG~?Phg-=07Uz--KOa z!~RRyL`|TZbc}vVxSG6h7G(ikp&s;v`za>qdy)gmq?xeN>J<un(v zmetAPh2#2cT;!Z=S7*Q7;n2A(M}^&=un`-!A7K-1bab$}gmqe?zshj{IZm-T^2yQM zC1!!jQK)hZAjhdT#~^YfYHi&bV6e(DMCBMtj?-+8;p9lPPSg47Ko)jIl;1in%-qe5 zsDn^gHp>WJI1x1x7Z|^tOO6=X9341*i*bSDixC#10!1?{dOpQKSae>BNnz2)C?|pDe$q9`1QZ_jlReHIOxP7R>_oygw^vLetkWwds~l6vafZ!tC^?!t29~HC(^QV> zoWtCSJgXZjkDw8bXOHBC(|TpN$T`cl zsQka-n5%MBs2r8#INRo!M~*~efvz6&RoDfDJ;#PUny`t6F?#|!hOmjO z)xp-Puyuqz*M_a9#%YfRHCrRIoo8oTjEjU(s2iJ?s2odGj%B#OVCIAXhmmX!863>S zV8KDh2#cYDq8S$5n_?g=dLhN6u;?rllfxpWDYgiUV4~PEEZUr6tFUM%iYZ~?TZ*m2 z!XFgdghib>#L>DO$F>u3p$>8RVu&+ShpeWH!~+#4(|lJq@|zzb$c?(MVeyw3 z8{{;RCr9LgL1*AnwV^=Rkd!+7S7(@Ai5xlS+l_W6FD|ez&c;RdJI&nvo`b^Ds8zi9 z#U69dCC7y}$7*skcdS~Y!k$mqi)`2ncL!D%d>0Yc3Gjn8jW_2)HSXSEoSSe&~S z);KR4yUohjC0FFn!Jq8Qq0YV%$yR2>E7J<`?iMpizLrXPjT97yypK0HjaqrygF$21 zWhh7bT)>H{SU2{tD&g*cxWz)c*=a~#qay7OFV5WvmfWkDtViNh=vHJ9ukErP6YR#H zHe=3}r=8XoUwFPdb1RF;S4(YW+2~u-_#&ssy;PU=GLdy!4-3^ar}i+)M%B-s zSl!TQtV}YJl2Z)Rh}5+-z&aVaiM18w3qd4RtvgUP5vt#NEa zDWy6>)h+-dXG`XpKFp-)51n$g=v_{$r#1(lOtPkTN&L-_vYQ^&-=3EeE}IYE%F>xnj!WXsI;zl1xgQByo%dCu6S3P^p>7?yC3g+-n{So z^L{0HKSxH5D?Wuvb@1cu=FPj8Kkq)0 zx0fGyA8+uWKluIqian#0Xj{E z$3f*8J*GJpDoroNFkC8`r};1+s)wKA3tukbkMx0`1D&Q~hwGVV`Z8Bb=6OEMm3sKO zzVP)DzSakR5pc@MRH}Bp4ypKrU2a!?ZiuPY{;W6nbN=9ONbpyYQB$dx{dl)~^SE6>j(aUH~5GC;Mu*LWm9G^ zS17sWt#s%#748F-XDga!Z>UB$&6`(MUsT&vgR_o+b3&3X&N_NYy>ix(A=sf5&M)!wGV{|{LCY3Msws?Oi{c5zI)O*xu5R|$ajg~bU zfn2&8g`v}!Jsc{n*+Zf9GkdVq$C(Xp&yltrj(j@XWmCW9jEtYyO%g&aTtwcVZV^%*idW~fEw(M%DkF(4S+ybSpm)t9jz6-f@!Egt38q2mwW^c=GmHIf#&`X|>^pE+_ zKLVY`XAeQ8vFriK>}}b7QXglT8F&&(ozGsDM!$euI-flUoyM|fB(t|=Pf2~8W$@YC zl771n{p-+aeD*3-o|bXN_YRc0ihm@Tcla>Br-z62UrUTHd@w$PPGkKidU!Li6H1-+ zKT78BeVD)1!^8T&B*yQ^r?K!?9fWEA43)J6h-+Ch@E<5+jmP=#-?*&=S?u|5o4uW- zW2?QjCbfXdv&l^}2`ax;i7E9SCZ|H_VRBpC_A$AuG`SNpYV7LZ$J@=DcQ1e5OvxM6 z^X?;gy*uaLQt#o95R@MN$ii(Oe;gw18jp;cs49j^B9tB`Pr_{< zlV?hk4?{+cUDG75w<`~odJns1LFr-F;kfN%*8*u*6*6jESpk*C0$EGxb0(dlQg*=88vp*NnUSP)=0gFU5laguxkl!``C55wChx4)VMMNmB!?gpz?F& z2~zK2@(L(DOg;m*eM~-IntUEIYV2AidA(hEw$yvrbpezfc3p_uK6YI#?OKnF8dqKc zmB!?CQ2Dv?QmOYac_Wk_CSQZwJ|^EHP2P-*aduf-${Qtbj4QFF+$431P1csu4BQH( zhfTNPwvSDZNShu+MvWWqhbqooYp=N#D(&w49w_~Me3#TK^>H?$k3#8DpT}_9r#>&q z`aF+}8l#_uN^A7fQ2H7Dq||#D{W6puM!$mFK1RPQjeZLmHI1+xD$n|GiTR#4@B99| zpGw}3{J=l+2LIe2{09mCEi!5~jJyf2ph=;kLvI0*DEcP;SVAMx4@9o3f(+l1jSh{<`QzhW{m+<@gz-K|H zsaU2Lvo%Jfdojz36-wqjALjmg_(Tai&?*UggG+m$y-y@y?QK$r{ ztIjAf#1%lL`P>=@S4EO}q!05!diVo<;U`P@Lww*TK&PqLI6d=NU*=NDJk5vsP(Az< zU-)tff20rm9OyI^J6z8^)0eqgGSBm2uGGWN^@XpO@U=ehi=fj~>=+%h_1ukwZ}Nd} z@WnVqVw~iIaRPK26OZ$SKSRPV_klmv7h|==SmlFpHgp;j&-8`ASi)c61HZ->W4*+< zTyMr@ItbHT3zcSEF#{W*^cV)O!fl^n@J4CU^?KfG{djNk=H2Yi`=I2#4;eKraxYYx zA@**lw61svN)J~&jN3l0cv_nDgr4_tKi+4&d7t&?-7a}wLq?4&UV%#EikG0$y5dbJ zJzVh?Zu_|6BWcnOJ@0#dydQh>e&Wyjt>pb088xo>5-Lwu@Id1`Z{F|yd4H9>Kly?G z<_-S4KX@SMtTg^bMop#u_TxN1s^m>UMylkjtV;17pRQ?Z#kX0ddtlJIkV z;E(dfsF4`Q_+V5+r!jH9FMOkfKh_7n))(VMiE*6XjHNmV(_9RdCbrGMNl<#sKquq2 z&)~IEnsmCJ_cTA=Grf7w^5?x+@?L<9nig3Dm8P4Y2bIOrOV1Foeju|K|D?l!tWAdQWv}S*(G(PJGRot<%)mre$L6Uj65A#qx z{9s@Bi4uN-5BxajG!+}GXD*V=-mNi8>OERx5|p~um?4dxj$FFdD1lDn@~M*9+p@`0 zA7>ewq*BtC`_Pv`r}5blP-!fiEt$P7nmSjp~j z=scssG@p~q-tqd3)W=x{pS>&T-$Fi(U$*PnU)Q7KSsy54>y2lc-^XpGqOl*Ke=be> zM9=$?AMY35ykGkB8X3--_HSg=xZ*FUG!5|wRDL1yo7BfO1YUfQ;pwUXZu_{Zoiw=( zGHUEffy&RWmQwFwR~nQaP1qi{eeCKj?dpk)8dr9QN@H?2sQgUsBK007?*pZW$$fC! z$K?H`$@?Os#;z>M>)qEfrQXA?zEFDD)epCQ>>4KR8jOq@R}O?qV{#!>ey+@ydJmI_ zL+N4ifw=8s@;GVo7-ZDgHCpm|yK0$I$xb0)~P15L1$f#+A>!9+i57)Vy zy?Jl;=e<+%Zt(-Z%NzV|fAB{n_=Cu(snq>`ypMYGKIYH+jO2aN5Byng@aO!&Ka=1e zyED2@#6E;hQ{f#@dA6cyz6X^RcuHXLX(jPF$9Ix>rw{X2diXDV;s22Ezxu%c44tN8 zKkAu(@MR8UI;+TkeVG5&!~f+ApDN)~GPTCHgi6yY$xvxp#SFBC(xbb#!)>4L-c6d+ zS&A`40nS7hV1k1Gz4CiT)-?de}7yw|(rIE$y0#j2c&#LZvZzI#hnHERlK-ljlI`Ve%2U?PKx+X>t`ZYV4|z zyxy)XmwFGos-g6->uB8evFqWSK1Pz66nHXcAG~lkDd{QeZ{TVB?=$=xNJ@Uzx=wyh z{B38N<^wtSOtZGBzM^Vc^>N}Q!S;k?y%yv?sa9+~6H|+6-V4>3s)okunsUBp*t7WE z?mP;{X<~Y6m(&hsKZ0Cim)6ynEiPZEyppqBGStat^5YtH3o4(`DRJWRhV7Mity(9& zXa9ZQ{<}kZ;Z>mcc;RKKR%&2*;YFwtdEt3?9tA`7!gl1+c)?71%TM`^P6;23+uxZa z$L#O5cEvXcM?+y%Ua?Gm38+B=)FI!Ps)f~ysvE27m8{kmdTNN$SYKT;Ur|}#+k+X! z{Twrj`f1D<1w|Y{*jdGN$FskP>_D$MjBrM7*Es~LKL)m};H#GS8rLS%?2Ow}8&&&~ z#QSyHCBck70)?gbMmBfIW^y?kbU-T|CC|)EBNK%~C~Uxl{e%fgNjcJ#be5`GR9nAH zsk=pM2C^JTVW;)F*(OFdAkW)q8jfSmfoznPFKkkJA#6gf3zb}Jw7J$Pxz;k*(&#Iw z(8?F{)?~$10(!kt=yK+;42U{ZiaY^?;N)?0Py^zp$XtDbsiGeZsekna*OALnFAbZr@4BSbD zHHw4UZaXt@7jI8nP(2TC5SF*C!D=g2(-+mLiWco!pcNm1#%b#Znak7F+w5FPNl!zv zM)PNEiKadpEvdT93_L+atf?GbpQK`ZwQ5i@N6x2se`2k2A4a}_n~sssGJ|J8zM|xM zF`7$lomPQYp_o)#SvYufb>r09hH6d{#)_6k=ex#u7@J2(f&y-vrM{}uFH3OehvDod& zua$ydL<_3M;yo%>LEMZEGe0N=zl|1D8DZDYO0HeeTq-px1aKccx} zumbpX25SsXf+RXyAQ=)n8zb{ymK^OGbN=S7QOd1$0Y+pClrpCCcC^;5ZFC~Fq#jYz z;3{bb+S%p0iE^hH5hKzO4T^epR7$7G(rPu$Kv%2u3YJbbMCr~}=^jeyZp<~NwrMVZ z$e@M&2ES398hTshS1RmXtn%qf`F)tHcwsGm>|h0pb5?|gfu}Y57%rTmsN6z6Rd26O}OB9-@6q*oUXq;6jCTb5Ag*ZhV2FaQtN+G2hyf*`q zHAT#XWK9vXY>AOL88WQLYvL{28rhQ5d9y;i;}J&7Nnsjq&t=rgyOA5XQVx_*g8^8+ zY@W+rG5?#@TN0&ELx$;JMchUp}n$F>PVr>&_hi*hR zt8&*tvMP7IBPHG7NP!z2Dd{F#qWK#jdzgPEZ%J1VO=i+H)YVtbj|M{% z4KIAB4u@eHfC%dmr=1^WH0N$MN3H+n&4+QRB(`6f_p^GmsqKZOk9f`L z$NLCxd-6U_jVJFb&{({$L2`IsWd3;G=f&+f-e-B+llN6>JbB-R#^U_|lEeEJ^T+dU z7q{bhU*~O4-uI}nc;)DWO$OTc3ur9fosh_z6!^xGlD?JFcT(CVr5_zB@QW=mCO?Jj zVe`l0cAU*0^0ueVUs7Y)d@5rS{~2{+Xr$eLLu=V>UhCK$kW!K@(Vjnv6Ys;{#qBtI ze&uaXd;X!uwuj?7?FkAWrh?6~rJcf?0@;JNrMMl(o6OsuyltuRjG3;`SiC(TS#8(T zk&=2zX>Td@meM|s6zF41^i?Ow9yWInx8rP1<84oyyHR7=yqs+Ze;FNR+wBXjWp`gl zmfiiNlxs`0Cj{BUo(yq2&YmD|d)l)fHMTu$JKB>j+HN2;mMudeIsLAH`Qu|IPuz~< z?a$kuyo0E*c-840@jD6{i+3y}hxZ`nkLNv5+>YZN#@n8}qp7iZSzmGZA?iB`8jE)d zB!~B4=8xwcFK);27W1|z?__E$US6#Boh9QfC=s{gESSpM zo)*larW*5S)Zb=crpPYPtvNNq8QNYGR6$A0XvJJ+jJM(_aXZe6BL!^y1dr-2Qb3RP z23_C{I!_PUq=43YgVuS2*62Y`R6vjO23_h6x>yf-x(%8XSOrP6cHmqot&!6CQo2Y= zYi)_`aVlhw_K1kvaqV#uZ+k|?3Tm81qg;}o$-5J)YUVdCPBH)WlWc8s7D&!qvR*RfW5u zaH9PVW{QvYE#h{ZX}9vWhiQoRhiuTKz$=iPLFImdqb$j-#pzaYI}ZLH-u8fR6?hn$ zqS~6u$>ocxu;*`S)ZwV+rEZ4t2ox!1;8B(oOJ>2E3hBPHWH2PGh-Bq=3Jsil-!Nhw82t)MW%$QtB$DZc^GyO5LT@LrOiR)JsZxOR2Y%_K{K_DFq=} zHmA#b8B)rWQbSg2TCa{rGun2LP{g0G)hXNrBnpT^6nUUZ>*Gxr8G`TR^o{CGqE>En6;d@+Dm;rHdRX za4{sS>?O9uRm7VZ-Hk~la;=H;y}QLB(;HO8&*86${4zU^+N|?1Gw=yD&gr?mxM>ym z2zRH{O{keyTVR}u4`F_2BR&v$8MExiP?@a)@8Zv>hDG=Ywn5}54~rbHAjf-Fjt?Y8 zzOft_A9fWvUPX=%p~9~Yzb|v-iH~|7=__))h8#Pf;s^Sk|HE{C8JyvK^0XGRQBpO3 zviNk$J{IP$8eahg?!(L}^X4^FH3~Cucwk_`@H$AYgdW+};g4FCL#-TdAjjoUnV`EC zf1PF0M#wmxoL8$XW%%i>XROANn@q z_0V@27iN8*@o(sdjOAIoGJeneG2`vfPZ{@we$Ln&`Yq$!%oUjrhSp^62yM)KG_)!6 zg3v9QD?(pq-WB>L^Xbs8%x^=>L#sj?LVtvA2;G*oCG>9Snb0FyuY}IY+8+8a>x0mZ zSs#U7%i0-QoApcR$*li`wq~7@wLa_2tc$bG%DO*mP1bW+S7bewb#>OZtc_W3WL=YW zd)7T!pJzRk^=Z~KS#M^&m-Thl`&l1n?a2BvD>4ynkkqkrFg-J`uCeK~wimSB&~{_n zAKLC}8ws8gJPl4bJ$OcNW$;WmV|8#1+;UOy;^5lgy5RcYhTv7ftAiVZ*9NZ(ZVKKM z+#I|mxFvXJ@UGxJ!TW*_1|JSS5_~lHc<{;KQ^BW$&jz0hz7Tvd_;T>I;OoKd!MB6& z1wROW82mW+N$|7a7r|Y@<>@QZ&q-gMenI*r>6fLiOTQugj`WApA4z{S{hjoW(|<_+ zJ^iorf74ITSebEF#@QL?WUR_KH{-mFOERv{*qm`Qn(2;=JJCpYqsd-EBfWv9dN1R{ zjE~TCpQ53@%J@2CXT~=f-)4N5@qNY*8M`um%=jteXEfq(8GmK`o$+tRX_=>^VOD0I zm3dC)xtXgo*JPfbd12;7nQJpI%e*3UeddPDt1~xdUYmJc=JlDIGH=ejC38#W-I`z7TbUnaevzTpn71CS4P{AaqIS z($Kol6`}QL;Ekb8XyVPG+d^AHcZBW=-4l8+^l0d5H23qN7ege` zNUY7eEbDRv#QLnO5E2^^4%cOE%DORYbJi_cw;?p{%(@%lu@!;yAVTC31kSdsC$pYL zs63bTLe@)JuVlT3AbK?^Z3W#5o}Yxa+Qf9m^q?zY?~a-Yn7D)*V(XLFy= zeIfV7+?R4+&V42K)!f%|U(bCbw};Ww=oZ-rqfGme6}5}%`d3#z)|71i`!5337&))1 zys>{?-s&VXV&7R@yRiSFN`u3Kb*F!2eN{!{;ws$0`4vi;CsB0$>t9j5Ff?zzxW|%7 z<~n9|{S$fSFBJEZkS3YOjC5tdg~(G~BW@=n#U_uxUhn!R^58=o{%e8%lFT!gc;;zX zCh}m+M4si=g}7rS0tbT>|Fyz@NoH$Oy8iLT0Rx8)4l4ih2j>kf7?PKtSE$^Cn4gz7 zXwaZwaA5wRp#?*!I||d;zyF#><%;=de^fQ(pF7%K`}R$fHm}=$cSiQK$I?G(Wpr-a z%AjuNN3F0`v;L|6<{f&wUu*^2bg+D7`<(f%K%N_8@{Ke)j8y&3eBnmJ7{>-s{>gl{ z@2PtEYtvZ1M9BnE=Cl1zZOy&O#`L*t_2@sD&u#;udE77_>q$>X|H*uIJ5ZAYr$6?7 zd_FidmjPV8u&RDo#+YGqrq;p6@K{uM@UWo?6zdw8{xJHse6avLfa;?a>RBX`Pt z{MU&8<`x*aW5*-Ur0GWPxM}!rnUPyu-8g0L(Zx+Q0I=jS<&EW#YyZpH-KjxYLnEH4 zbkFv7MO+oAoqIG`EB{MY?V2LDs=mIqzP_riw!U##T|EM#(dby*yXV{i=FhjFkqQvn zoqIX*&#V-S;<`Mp|H1iobnD+RwU|V%>{0iocy!cSm&1sIIB3UD6Od z1RtKy$P-+$?^9-S8DG^^H&suoq$Eh}pf<|WU`e0=>inNu$vzW)uS z8-F{t)4$CFMUDB;roi0ilFG+V`T5Z0e;+vR#+$E8{iD+{dxoh%tzVk9s$kfZ!h4_W zKJD>m#_io{#+*H>^P=*F3u`NcRn^&-e^_zgm$QHS^z~!T>A7}sr*5;GAMumQ8yAdS z+E`z1d2!`{?YCdr=gaF(`)c`&wR5*z+37PZ?VFE2aqQ^)f+51{8xH>Qk+cnCX1#XZ z-|O!9tmCP6dm!zSSODylYP`#z6GZthP`s~Q{xXy= z>0y*Dp0~uN<)h^-l9{hN2v<>Bu8U~V;8%m zyE&$(nRb*~EY{LBELhMJNl~g{^swq^7tF#hoh@#tiFZt2IOcp79K0Wr3@nqfS+E72 zvkQy^+yzz6{ZJHdRWl-!a*(`A!iaL}Pig!qQAxozAL-I&x!w9)Z zBd(HB_psbWEca$l#nLAsS(2s3 zP21jPT8>&w^$rW-C3Qw*>trNTvkjw{aB2Vn$ATk7!J0V2VJLS6%gvaIBxhg4=xH^* zUG5N9IhBzmuVl$#ha!0#CHHof9EMk}E}j?H^NUbyJ&V=OM$#IA6YYt;`k*JO#Z*2P z+`xkW%t7+8t6(+?9;Fskn}P+eV!>5MBDo(y7iG*x!C`p&+v0h#Ex}S(v(&bFB)tdA zQgBRu5Oyl1V$Iyha?`LNi~Ndm(Vow8o$z7|^!zx#91Ol|SZ?O2NZ!E7U$o=zK)K#( zIXRBbLaA$6s^&B#XB{N_Qm1q?ZNGFwGPz1z#}b2=BWXRtFtV&b!6-qV0fHyayiyQd z&tel!N3s#c>`qIfL)0>=GgzrjEcM0;Bqxkid)`ivRj38kHeZf3cjtC3_E8%7#iB4BPop(kAxR0nIi25){eB2Tc` z(I^%j&1mSS_)6{KhS+ePi&D3;)R^m#T#haq4a;{k%(UN?QmQ*y?lzWt?|LLnCF;1s za%LuC%p${6xAyE_g+g0c=#foGzDJ>stQj7LM+xyH{`l&$!U8;)nS|*W!(&IpemaB| z4~|Xlgb;8VS!TvNw_v5Er5=< zMBz#GhmaIv^yq9C_)94;Xn-t`f&$mGz^yDWODT}b=hMVDJSJ9^S7Ob6cojC_s&#Ep zb`#4cKZ;}*%4XVRdwZ7!uj+;ySk}bhL1fzzhOysxx*>@!GwBMG1_aV_B-Hf!^6G^; zJ8mRaw$?XEFLh@u3^b($d64xRZS%*SDIFtTd)?u_Z5xE z*w>MKfHLjvGEcC~{Hn%coZvOpSJ|JfSfxgR>2@+*xE;yu6*wpph8k(&kyk-Ukbz3FkhzH*kC_6|A6h|=Rq3JbvL4bl!E zPY@*aEhNJ$;V6P6izj|f+JH`}VvSD#_9Vd`A=s8E7#~Tt!T6l0G;GiSU&EdvR@2)^ z_N|hJ@nK;bOFW|KR1zB}U$CbMw*Nawu84x&69o%gD-9bpW=u%})1D#P2Sn>U&&xFN zP^M*C@zew^dzM%izKi6{C>9@;wyW7KYFY8r1a>_~tO@TS`8SHSHHsBfu@brLd4l~z zu%`L4l6lew7dheuQM`(HO$mu>)oyMu($lhgEi( zN7-vp_BEFMg=LqZY*#U|1W=X(pqVBfS+vRXJrFpoyiSDIK1TAi!=7x?YBQ}d%70ja zruZ8ye$FRI4m`#--YI^PQoK-8d^?Me{S?V- z{$rN^IkxVi8Z&xgY`5El!2giNFWZS^NFBDM z)_f|v4xb&A2>AuT7>$lwu^<+SUFahso%0QntAW(Xa)fx^B8`s+Mqvi|!hB4a!@ot+ z?bsL?1E-1-reJ_C%qN7|?>i)C#lo~vVG8{#^(kR~CCopuFkRwcyu9)m0k(aQq`p3; zI(tU}Mvoa)Sy`W75R1TN)8|Au{|6+W1EIe)xMA7Ev60X3*&eYV3i7-lz97WUyO1nw zFpL8QM3Mzz4Uv3CPvXqf+wvuWF8&G0j{utB*ut?kjZfaWF}#iWiWtZLg5*4G+-Eq( zM8|7BR40KZTE^h1;2~Z$`t5NRE#IWAtE$9}6~UfZnq233kRmNOncR#46XajE|wY zEVID8E&G9BQ~yOWf2pjd0JALP^JWrEM5Ui;yNK2Ud)dhQF=&i#GmQ^Qd7*jR_9M|g zCfc-RZrd2=W*VQVl4v4G9orD917bs!?eG&3Z!&@SObj9e-b}mI4>2zIiTE=S8v{Tb zah%&m3vsK8C^~>+qnCZZ5G{)$8OcNnS~osII_dw2oNwy)+;TW81t&D7FHJH zL*WTE_}H(hLcHF=*?-@JmiUdet-^~JBJZ7utu6VJjI?1aYb`vd*G?*8VY%eJ1*Lvx zsmUEts^TO_Nf(j0We&H)ky8xrWczXl8d+;_^EiT=z5w@X{kX{*%iU1{cQswO9qG<} zL}Y`(9Y6|~?#W#Cw&3Em1(%>nTu4T?7+er0aap$y7iY;_VWn}I)RJqR)?Bgd#brlJ z&ip3l?Jk^kP0pFgobi%4khSFil*EA}haJ8rJ8CBTS1P+jG9x*e!DljNlIg<8`W9(d z+$`Op`q4Qe*aDCIL67`#Bc5<9e+W{8DLm40_AHa<5+;MD6SP#!4qu^0?VD)LVkS$NEM>Bc$#G1MXL16Q6PcXE-F3y{x)+ZW9hPBAqRN zq!{NYMM{Q@S4vzB1D=XEd`$7wspS>NR8``uLW|*CzD`D3jR8N!I70EnV8s)?q5C$f z8$UsH(*dyWg?>$Fu)=~eEWWVZL3Rd#Q=t-9eO5zzgR0HXJ5(|LVW`I{>f(ZdsyAjs zeYK)4$seEw@4X1#_n{7rs#%8fKAeY@Evar?P}a~ix4vqAS-m({5szmlC%0liPwv7e z1yhWJqt!!O%0ATwsvBK&1*)-+Kz)@ir4->JGMr;M}KaK!S_DMyq15N9TU&+al4FRjny(kkLc{56My#c63cQd(%$-PXrGP#e*{Y)NU@*opF=x9F7f$+t|tWAZ(dfI((mIN@^&F*c55 zBmICr9!Tfd7;MX;?U{Np~hanDk`Qi%CBwxlH;q zIeT|D@98S1}Q}kgqAVo07p-C#R>le z^!WRn`KTQxdwe)7A6Z+psJ15h(KJ5|NXC$hRGb6@W`n2sFgVN6Py%wRH;$t)&^Gnvg~ z4wEC89Lc1N$x%$onapKU!K9K&6_a^P<}+Eqq?*amOpal)kjWw@HB4%m)G;}hNj;MW zCMgE{v*Q3c;Uf~_+o3&b%>IKKTPMoiRsO#Y{k>^tZzlUN>BA(*B%MhHlT0QdCRt1v zcILiJ_G6O6WPc`onFI`e7UR?zp+Bw!pXhkUKDiy|l;*1eTmWah3oV=>rW8yx_N>y5 zLqPz`B+e@AYz{zizH1^o6zcO8H6}834&MYdtK^g}El{Ix7_@1#Cl!q;n=-Ws@1C63 zSj=@sqz!n*BCaJe92M=Gh3L0(P76Y}6Qh&^T~wsRHLa!>9c5|3Kt($o+ItkOW|kHH zjE|t!SSgI?-hkJna-EQgPMcz!r=XSO=c_Kb7HWpHV@h#B!8FB|2-NIaQk}1Ak3j=* zG7+m-@$pl%iMq3i4i^)D!1#ul#<@be1ND75<+kQ%o^lPcnAbA7j>+{*HZi$@$&E~I zVv=I8XGwbs^HhUY!d%Xqj@s!(o_(zYGH)0;ZR)6!BC*b&HWkwg1})LHhe65kmPiFy ztI6ei7+TIFQk#!qS!#2k<=hh0Vh16$2f%6HLo1wSb@Hg!deAGmc3^WpaWIPAQ+{I$gZ8o3YBqWHEW_H%mf=fjQ|kDcFLp>A*Nw=*n21i# zV6g0r!j7MyhIB3r=W0MVPvcW+F;53s2Ylt+2y|r2cKE*@tdd9eGq9PjSy;vQ#9{V? z`4^yyF9vBomq?D&IM&J!=Hk0b7gUIg5Tzxo8l)Mm7*Ehtc@&Y4hmQq-mD(77L~#?5ia zK0gsp-SUACZZacBro&~Z;{E7;W~-Fhk;7WGo}J!icI5m(>g>pTvn?c}-R#JwK>OJk z%lTQX<5P^~#Z%!^@3EZACCB;215|5^5tLnLTh>g&_Xe7{?aXpEY#p_lUI$=@S6+|L zha#B>Df~+{+Q;2X-jr#~tFMZN^Bsr>{Ne{(#QDfEskBh-rlX+!Fuu|7yhu$$xi~2* zUpRItcA(a#iDTg)d)FE;zGf-WOc+_Lkd7U0CnAeEiOFOpQXYEjcPr^DA%Z5&b}OEn6QgG%~|5w ze%=r5EAb{w;MoaIQn1w@RZ)TC3Z-jDiEBZ2CA8dLIc1B7sAI^%&~k+?wfO_pezy$jSy4w7sDA1J-G7uoF2cknZR&)O zJQ7ig2vr_{G9ufZz?|l%+&K|Pfo1r*R#^oej*5Kdc=;g+<9woRJ~YR`3Av z5Lm+1vQvrD0%)ZvBVfu~v&L1)=cxF$87|}^*E_fqqgCWiQHDZW0CV%{02k-G2H>e^ zZf?{un#3%oyRg}ZiIo~=6n1Fk>t|)wnwKNBFrR(pFvS8GFD>W_-Jgn+N4Yk0TyFiK zYSmzDiF$|F{TJ0X3>vtUr;7cY;l7XO{S~AHQ}}=(_7r~6!Eh1U?Ez;B|F=Wy*^v`WOyWjMOyWBX zOyY}^Fp2kXfk`~Y=v9Dl95g@#0br`7TDSZ|{ zeZa2ymeZfhw7L{ytpZ!(I`+H;q-V%ZJ+VaT)NMf6a|XhV@ zQ!53h$hCXv4KpSRGb-vD7GaOz*wDkV;q~}{m{?mb`cBo98onb-2?`^a+$Lm{;Y*q| zd~=1hTwjjZdjs(wFusBvq0-{meUR(e_>*`(Yh`Vnv|~|OjW6OwIk}_hkYXGXjcIk1 zN=5zVa!O;};M%`n3;v}VBjazT7(7052ASeP>U2|QB=5p^n=}K1?CKmA-U_m+-?FOC zCRnrO`&Jzw)ww(g!M7vc5BSP6*B-U?)+Zz`A4E{6u9G-9l`mdeCYI1&Ig<#_$7Hnz zsMV^0rF?u@EM21Sr`N4p1`SZxEqsAJ*DZX5Jx7Dd(I(&kEeGK==4HSEWunv1)O_~Jx~|0DZvE>Z>eAgRpY2=vDZBY}wrM`ub}8B#05|<8&$> zOggm1L)8{(04-0XrPj3#90Tn_m)6ysr$YU#9JFxwql{XUpc|qV#dBiHEIJwLF0spj zX-#6WYwg`ua6!X0{&V7^sUh?~LLKFbRoDVod(DCRAXT03TI5ZK`ff!nPrtA_iw}(y zq)=`dWw6!^^rGBg&>&U-h)-ei7;JuY_7(-mt$BYQ;NV;Et#G zgXuS%a=`y;e86z9992_^4M1HqMglwx_$WTJHPS`%ad5*RdV#`;&z9AN z!wu-c+n{zn!TkC}37W?zDhqydxi4%s+M(f#0ZDvnToo%+8Jx#1go{z6=@l@G= zqBRZ#VaSE5A$jWOe>XzQPj{T|QL3(|`$9QhQ5F}tg6&ACdnxKt9;C@-WIn3+5wzG! z$1Iss>Ar_qHvpum0O<9yd5hBLDN?!X|+_Piw zGgTg>I$kLmaHwM01F&p6Et9>=+5sNLdOgCh$mb3)@BjMft{*u6FF#`AYSV0DvY5#d zCQF$tV{#l5M(}PwBY|xLvO7M*szi0#0=V?)_?X2f{)giQSl%D_v&nu^$0v1oXpL8m zd2B7@SDvFEyJew6z9%|lX>>*{$Wvz2ZbtH-9{UdGOO#QlNq~A^K)oAZ7tK@_?TZ+F zxR1L}@ly0F2JsQgJt-T-@n}h*I>D@hmJKDfuFr1HgSI?cTOQrX^+P&z4NA%4Lf7XK zXF~m)GU=gH%KbNIwQtlGffr?uWpgp+9g9j;WdJr@8cm9E zt^!z+pQjGh*8s9f*^G$SyBU$$&PHXvR)>cv6xiazJk_yBp&F@*y2v%G(RnY&w>_S} zs;bAi!@R2cDjZjHfjX&aVPkb2eq%f^_LjEi<_X1BlNs-4=uS1Ht`MGLfC zj{(3_vh#^`beZ3YL+cWI#6L;#3PM6{y9-gV@zJnXk1kRG{szHu zViyHA30#CQ6#IAuxY+g4*wMf(RJE?ze1eg@0PnG=u322Zu)4CWt{m@Cs=@(hSq&Z% z!z%}!kBL^Gk{<+F%a>`0_*fUFShGj$2S3Y^#pL?ST*2fFCOrEy&t$@r5A$p$=P+5t zgk8ntrn6zZV zy|RMomZQeOz|<%+gsh#JSYBaZn+ zN(Wkuih~BAEzrWTj}0wSE2*vq_)+bf;E1m8qTRuD+&d<>Xj<8%DPzX+3)6516fzhHt17?a7$g%j$A@VOG zRnWCS7LEyyJ4;;qne|3;D}2>I_MpWM{OAEJ1OHPI_&2Fo`L31kqo~<4{p53$Xiac; zQ1X|m$I{tQ-lZrp@S-K+*Ey}=Z$2643>Q&vx8UG&kUctgQ=m#+k9qY2QF~RZ&NW$3 z9-t_T3)Kl@EVTP8+EPA;B3CpcVHv-E?D$q33Ti*U$K`FE*D-F%`*9(BKoT69!uQL1kD_C+0@VrYnSj5-k+AHs*x0L}OXnlU+t zPpjAiP+3tu-fF-%6y(Wihfl0rDW;v*;v306V&S_dN~-5CXheK9j$VeZk0>(?j)=D^ z#>%a5?8D5SJs!WzXFP|}A$!9f?eR(M@g??hqjY-oNqKvn$WagfQjCig@{$78Q=1Wq zNke!IMdK@ubY?g1Rra8{zNx^pxB69Yh_O{7AxkL6sR5X9QcTjIywt?j5HOsBHCe0o2{e#E7opP5;YNQfw?Qn-urT@R8Rk76^r zFD@@zh;q8{PSSc?X%RXT;x<` zZ*{8X!bMKiJc@ZKeqbMu(R@a2eWf~(W2Rjxd&E>cXe&Dex}C8>u^LYUsvY8PMBB4a zJA=6QE{~^0CO?=n8CNEc1WZ22VDiZ*^G7B;;xm6{!ZQi;S0?-j%4D3H{D8vbgApdD zPCijHm;<{#A8?cqt(2h{TFNg;$(SAj2ktLE$-@|n&yNrcvz_P(dEQSkxZQLju}JO6 zz2K7~MOj?nT29V_np;{~HeWG>otGP2sZ4c^v0vBC}F{K%I)#lJs%xIv^qP_WFx}k zjaN~T=wr=RV8nhok4qhsv$)9t&0NdmQYM!%S;vGMJ(H&vCdXxyD=U)$X za8@{+TjFm948Hcp0m5X>PaZJ3+gs8IJjPwI_0VFf@wQkFEJdt}1C>vl&R(k;Q{bBF zPKPyfx-Y3%P%g&0bl{~JJT-ERFDX!0sh2}LIy&57+>moE$Bh|E!D83acoDRfsy5$s zEOH#w5k-yhLLI{|hPqr)2Wv3xJH30ah;9c2ckz5 zt@A9W=ZwlHnodz(Q6US??CN*i^7WKk(^C`K+D))rsBl)fBDJGfyCoPWgf(2 z1e1|Wxal!RGvOd)j$tyENimagO!$GF$$8j3mN(RdS$;TmCy3e{^suS@PD^P^(mo;ots2o@OcfrbcQ^q{YUHm`^}1< zaNQV`ono~re2xB1P}a{r<2AFd#GjwGYn}g@@SXR~zj>`cvhQ(+Z0O&vJ5NQumfJ|< zv;5P!d3tQ^-yHk>pMJZWzYi|l)rxcX;0Exq(vP>}HMO0xS|*6MTPc3aTubTPL^=hn zx^@0iA3qYEqYvLVxzEPvU#=HYOKrB!KKd7ooy!Xrf78?1T>NLv>|PHsezY$;m7lBr zBgC=Q48JgNjN;%w3lq$A{*BReJ2O5EwNt^?`uwK^roGiIu8cRHeyH`MsA+c^KTn)U zy5%bv(@-`VQA>ETfRY4I%9V~$V$`?X`*FTqa#$A`sL>sNYm1n^)9<>^DWnOV?=O3I{$t}Lzr64|=hofo2k~3Pzh(AUp>Xk^ z>=u!^Aq(k012Fy1@#g8#Z$0I<&jI`BKi1OcU?+U=e>3&hg~6$Q8zJ5Tf0ft0qIjhl zerfDbIX-P``PrZUHwroGZ%6;CaP`Owrq-X~m#G(%rQ7(iXxBH&`E``^T`#EXcWPo_ zhe-UBC|>1fq3L&(bn7TxapfrfgT$W;;`LR`X$NK@or=38^pn1RDvp!JY@gw)`5bGt z{^9eE(>tGc?pM|M^Yl2Y{P?V^bqBldr`Fj|$KUqv`b(0|Z~GUz@kWJm_%DHU-Te16 zhJ9IodLPDjB)-`1FkQr-xlTLV-&Dv~uR}+2XR1?uI0sF{Kma|JLmEpQp|6 z?|}Ri!wIb$&m1qq{5WHpaE5=j`l6&ehII6EhG~7ZxB|Wz-)`EjBd_f}D2uG&U3Jcl;diJPK-M&-YFr1Q3V*Gbo} z5LI}$Zr}OWID2&72}6A+@Y@l#t?#JutMOTK{iSISxvoFB41bYFWc+wy8hX|ED7#qF zgQIlDpAa7}F~6rV4ZK?PJVI%m_#^#Wf-b)DQ>qhul^j>)&)wsaU~T$;LHfV%Hh%oL zThP@Xe8gwYK@wjS#MA#f!T)WF_x5vw?p8DW_hN2P66?f&w3(L6Q0MZ)_Tn#3`<467 zpME^&J>$1STsVF_I_+eCt;ZbecK!5lQZR)S+YH=^s^W}vlC@{fGFtej{55iR%+^32+FgU+5j)!lo;>SgQ8pR62W zD~s_@HU0azLU+K*!hmhA7=b+XZ=5?3bC@S-{616+UJjd*poj3l5l@DPYD-3E<_|T@ig1p(lw_EVPookYSi}b&Fdh9h#yQFcJ z?VMkBV%qLKY{}UzC7Vu{6mt^{I%QiLihn`ts>(zQj%p>iqw_cW_SyXpzt^`t6=hE& z_MF~5#mmVS9lotys2BJz%T2aqU`xs3D|Y=dXy<*ktM%XQ`j?(***{~!Tdf3tUC$@2 zYe$|nVy{+$wO3Y6x}0~OvLU`>mTe{2v&&T1CSG9&Z&vyb<=(Ws4J*ZhWvh&&I>>NUeGxfzut8(br${aW-j=P z=}#M9Nf%gn==2!=unV{33zi(*QgT*l$gbGR&y)0X0=^Y@{YoIY&(q_G(o$V|r`Yi6 zT{-N$=YBhulX#jOIX3#P#yNk$G%uZk8DEhbt- zG>-_`mqc@j<`T^-g7*#4*F}qqz9L#w^aaruMRSVK`I_jnU1S^eqt~lN#x-E}BoYifC;SsjMlYY^1!B=)0ojM3iD_5oxa``o4&C zDffz^?}?TY{ZK?HR}d{JqFhUedWrNOmgNu8RF2tHj@bn7B$cFdy^TIC;}f}MDnqAC z>CAS#NNIGgyEHyGTa@1`naVj$jx5Sg(mLW5?hNwllU!w=K|VOiRmvIUr)VAhYkOyq zU!L&V+8N|mBssCh_^(XzPqn6=+lm;}=vq;X0X%t7SG8Q{r)_SmwQ+B2hCl3?XFcqm zBLeTC?VTaETZ-H|)b?PJ_Z3?Z10T^gzQI|JPLxkca_eH7*j`O?uo3@Ul7orzmyx!R2PQMU8eZ=^hD8_fR*2HfA zy7p&~_tl!37_Z0C408Gzo0jX5G=uy$tz-Op^vocCNbBfdkBS-O+{5gj?d!2KgSNwsU-hMYx1-GrIY+Lt-<4i@hwq|?@_I(AH?{!D9Rtv z8W}ZUEF+5YleLcVEt}*#2hn$Y-%0YRS~J*V#&<>0{ur(CZF%n`r@x8M^6w@2japM5 z%a=>?)3s**Enhy#kJp+rZ}|#Ij(uv24r4`8jQ>TgsgLD)oti=Zq}CCy*S8tuhiM)0 zdgYoy{;}5NXZx!p`I%aS=U!s0DvI$9)0+If|9WMdL4Kmv*tT4+b~DJ&(mKYsT9RK} z){bxWB!5L~2KOREufH?czeQ{I-|{t*{3xx7jeC=^rYPojlh)M7__dP!RISP1^0kxv z7_EsNIro@eU->UJ`c;PO5c7<6MA0>`XtWJiHe+2;l)tPs*BaL=V?9xnb95tq{UqcswC%#MER&B=X#9t zE0UZmBFZ^du|6DuD8DSpIYLo>O_I}RQ9d%rsV&zq{&>7IHW5Yr(OQ$EdwtU+KVNI? zSiV`3f1owPy|#Ih-=j4-SiVJ)bB$92%YU5Y=W0#-?)5E`oNJIhc6>ica?T=h+y7~j z^B9b0^=C=`hSv0m{cn@xleLcVZ=2*3wT|`MF3I0Y_@5^^_VMlbf05)bX-$02fBPgq ztgJ2HA<3W7I_}>ulbrJw_wQFp&i>Qm-xM)^EsFicS6S+B`EQcEuh#6Z^V>1WAJ#hh z-zmv2(3<_@^^>uiDEfa;YxZXm5o32zl=GON|Be4ck{@2ymj7RpPtlsOX!-o3KBN5` zv?hMb|CHqH5Aj*PN0MKsHTARn&q+>yQ$Nf9lH|u}&12B=J(GNt*3@q?5o0e=jQi8)`XY2W^CyX@ZBG%SL(~rYeaVfzNpsGX zvHc1**5+pM@Y_qo=r6*4)cI6vVq8MR7$C|zeZ>P~okJ=*@X%RO#5h!x?Faa#9 z*UIs|CmDS~tvCnNYAF$8kfG3euVelL{V*om6s*VrKq*wX@*eT;sOY``M7-={Q>evc|x?axC68O=fsQlkFV&w zD&CwT$8bVL=Y8>_of9iM_~IFEJ3}ivlf)ypULpo}M~?Yw@yN?MCs%ad5|8(RZ;KfJ z5@kE^*dyzVEIOQp9%YUn_KX29?jL=Qk7Y!RZ2t)Hq8y!wKeEV|)hC1dDaw!18ocGm zqWlG|sk!~rcTvuL5asM)l)qf$wm(;rzmnwiSj2x=zcOKrK1v5r4MU>@jiAOn+P=J^JUn zB1Y~HzN1AsIx)VBi@di!8M!}rCk1ag*n>rmZ2`^UF|zOR;;~=f>y&osMBkSsdG>un zl7o$SzW+u0xi`5VqdfQKRY{(E^O_{jy-97OedaN~8jpSj*=h)<1;&-FgF$c@kSzDROv=J=`i zF``8Z|4w~UFUNn5=Cw10-&IA7b46L_Y4Px5oeL^Dqs7C&pOY6>boz?LY406oz3=)r+ZHGH0>)b9L_5PZOLGPinu83Ti6AL}z5qpbXC!d~0iY&{C)AHQA z>}|y7yMntU;&bl~OZeQo?<9Qg-2sx5pX1BD`&Po!yXf=~ai;hL&nJDpu!tOaC&U+g z2K&$o_o`&Z{Y!K5H4fXcp6?cUPkl1x6-D_WTE~3mOLERitoH&*{(#o8-U}r;_M`k8 zNlyPn`8O+a;&uGJG{*<|Qcv~|Vjc53UTf<4Ly`3?_a}8fuIR0%Pu9nl_3HX$EFtoK z*^d1kAsPGNeYM>~3m<#j8^po6U@R$$`x@gvKr-*^P|d+%o3WIrRUChmtQN`fI#d&_9us_w)Ffjdz|KmJI>z-B8PXEfsCetoA6j=iAI@prx``uncd+^zI8wIv7o ziUIF65m<7M&pr1ZHt8Mqh8&y|>or7--lA4HJtCQ7J56);fPG?oPt*!`n`FjuClELF zVJs(Vh2y?9j`Kt zI@bR@t;xNoh{1b8l%JqA`(gR_lYFq&#B2E~Nq%RN^ZpR+UyGnQ<3s9&y~IF`jd@j`^;hq;<1l%2|pwZc6vnQ=oj2SfcC8;e-e59A&5yGv_u`3{~?_{4v`h;y*Eh_Q(%#(`bi zXHOi*0L_UXIb%~%#Kkx+kj%I#np*~Lvo<*HHsf9_IQoFGxu})Dqa-tKs^;9muGbcA za2)}6s^;WP|1f?mYUOWV$?Wez&F2!WCt_?VYK8l~WX4^kIrX%^pR~dKBH$j@oO-S= zV*FIp%HL*^+226T!O`c8twgPGoLS?p)tr9eIm*~Z)C#wpWX9dAIXIuoZQI~_2HbrG z$GKwg-qXt8e3IGUP|eAYyoq4v=l7d7xc>y)(VBB#8@F>C+#LaTr{?%`UFcon<{Xm;{YxLR2aLapVjk%EKHwSV zJYLrPYa--~zloyV^R$k3_fPWSTF2+l0ZD#o!v7=5M?iYVt! zePjJkt>}yrFXle7=*0fu%t1Xw%Zc0{^f~q4Sj0F>L=5g3=HS>52KdE9;Aa<6Pw$mK z>DOaK;OJ-8oD0^Qh!|&!n*3m|$q%)UeyC~mb8+z#W4lDWSkr%3bl^oDFnMoo7BBYG zRYeE?)X6^Y(|kb@bs*lj=T~c;?H-wQ*rTj-zIbuZCl;Mndrm%%0iRzMttnzm5@Ej; zcDQ85zNvY{KGT3bHeessoZ8s$lm=}7fPFe)rxq-+xYp$GHxaSYoA~k`>{a;e0WpE& z-H7p$2rTcbwgrC|QMBcKr){L)&;F=mE8L9%cS6zQotr_{lz5_VZ#_^n?7Sxe3uc#G{y*2LHqGud= zw!(cV8Sg6e{v)F3kGi(Py)2n=1B#yg@f>J{dn({Q(VW`5&#>1DcW=OP2ZOUe@@|D2 z7jS(vXV2&%2DNU5yIeBoccSL(pZjH@HaOnPjC(?J_Qi32qYdt)fIC8S`p>v;w!s}9 zaL;MZAVArFZ5?nQ zYfgXuRK!?Zl=CxgL&==qg_;wmaZ6QjK7T(5IQAX;n~NBn>Fm$AWhJw}mo+EOEkulO ziCW>cfK1V;S;GExs0mm~9ocC|FHn>{?j^`h^pNSZ&i*lUy$6f0< z2Wk#(D-q*IqE@)`B{Oc4=HTdA#u}nlxKkxFj{7s_w`LpMkpcH)!8yOR+ThqT`};)m zc#hU?gWD(IMrj`7T&IF_zw8=t6Ew%4`(@oWxSt2yt3}Va_1fSz4Y+4CkN(zggJW-9 zm!pcF{cWH%z1l-GyNKMJpZkV$G+e|!&nq&2Y0YhSM3HZ!PsWC#nX!9{^sq}jw)+*$ zZI>QGzO9I{k!WV@@{G!M-xrVPJ^7qdbRqIL^OuXK2oT)9VcG|5pAu|Hhr5`Bz28 zZP5nD-Wm5m!5H`BHn<}L?tab5&p7VK9H;kz^KXCTN1U8B2KPrR+&+>Sce>`_ej#FP zEwX*~e}ag3wihw5KQn#vmh`~wAhJDr#D3o{@?Ywcf&UyYc>0K5HSR*qiPz6>;%bFk zE#SE4z|A9K;MZ}HCq0J0Ux^qyie@Iy*Q5uI_-$`t%^mOSMgD7jGIkQRikCe%?pDp? zefQfoIG+E+N*=_6eV>otl{IzD_Z_hr$M=iqZ|62R&cAU-7d`viwGEE*Z`_-jM}NO> zgJW-uJGbclMxTt`%DR>x=ij*ZHD{k3=O5bOIRD07ns9rz!EyeLyGC>JbHDA?2FLj~ z?zy68+};(O`;7B%+&!AlC8BQ``-ocg88YJzDSGy|uhw4`)#}OKf}@X+I}V=}`tKbP zdG91*>?dkv?`M+L>}_87*yEnS9{tbwtEiQ|H6^Rr`$6Gjk3PWO??jBhiCWcZS;<@{ z@}ht6%{W-p3di|3?hVbsxxW21pH0*%2V$$`FlXVD19!uhMc82sDDze}-<5n`QQo)L z3m=;kMA7D8t=q*pxnQ%+#|s~u6Gi0iIFBlGc(H%()|&Xha8J`$JBt`ci@;~hSn-TG zQFAc6h#1F+YM9H#HwHi0+*QOlP6US96B~IU&wh#V91;Gwv-m{+G?8s{N5OXv$7?>b zwuclf_nK`Vs<~}*SHRyz#Nhp8W^Ip@F8S;(vh6)Jx9ziv+%*}hbXidb{6 zn!ml~wtZFM|DQe?Cy8d(Hg_;K|5!e$_j)4RzO3;7q)*1lqM5aQt#q-yNBP9|cSW{+ zUE%*(pA6pLv7P&3G4YJy4yPv0mFGeYgT66S3dT9mPc;m&8uMPkIJPrdU^xHW4a9Vj z2pfM9F@}k1eqIpY81@Pby}}qSs$rfG-ZUwZi4yL_@IH;Zih zg2HzWBekAc+uRM<<{8K*wyBA2A6xi)>XX5lm|5GLdvfL(YTKM4+di+zU6XUPuGu!$ zpX}RBBGx=l&F`zZZBrlkJRcdvGPAZvOBd|l$|p6UcWrx2;qR|c26@b^ZR$t-2Z$W^ z)|%V)*+qV!J{jySw)6SgNIYXc)*PG8mG1;K%xVGiVZk^D?*AI5cfd^5d`^*L0o&k(2MD4J=|9?e9O{gce+g-%CN>syo zFJ6<}*sC>%&mGQS-3~iRa%0I4EO#`6_uqEd`y@B^dd(X{Us6KG0b0IbK5?)$p4{F#=WAMwLMz8#2amM{%w0qk=r&sJF~W* zmo6jP{+iad{X&u3_WfGVtnIPV<-UlvKPfzF#`!>Q+Ye}tZT7(R{-Wlt=c}5d4|b>s zy@N!I2Ss45i_S<9I@^dC4~epU>gry2SaaKdOmlqCBVr)S_TLl_?5{rx3ZDN^O+ry>H^Ca3Hq_u62D017T zjx%eUJ>}UFZSSqMZF7erx9!I@$2NOZ>zAFyH})0H+0Q;AFpMY4-1VntP8ZQL+lm-Z ziqMZeN$ntfZYHvi=QPL1PehETL|~)+53~kr`xA>!EBh-+Zu`XYd69c^Qo+tlzj4-x zgFDsnEUdY0k1u@gVa8-pyS&NM*b_A;C*PY-7i_D2`B-v#n|dE20^3)FKgKg<-l`@q zOK$uy&B@0#nbLrzhQ>0-x3TPByPWS1Snkb;o!WpM9k4HI&OW+Nu!Y~5*~fFGN8Nb7 zc^~09r}K*ZKz%Y^5Mev+1#v_4@5v%#Pc8foeS%>SYsRzp_I;S<#viUZcKeBpf2qt{ z?Im#|uzw6#&RWF2+JOC4z!GD`zFx3-KhU9O&YgWYzO45N{0%jCPP|W{ zzo&@thKSmiC589Q8au-InsylIF1w&ccgk45ZT4cLVO_UwYCXBcmb@Eh|!MQhGK zb!5CFs>Nmub#rWkH2=J4M-k&)QMP}fc+vj*MQ3LA2{|3uB{TlNgw$o>76 zI~o7vOPsTdkbA#*S2OmC!tbw7FpLk&ycK?o#-}3e94WHSD9y7EYLjC*PrR>)xaS=U z?>Sj-h*y1|V0ivhKL+{ce7tA7Nak3_l=+(aWMHQiZac}0d%5Tt2euV% zlYpCC=El)at#GRc+~A^T9DCCW*E`^@PdIv@6>hPBd%n!=Z_YM2>h8K+QuK_Qs|}8t z8Fy{Mu~)6m4EGf>a^Zep94cb(81!c=?35w{dzXkljaX{a3j0uzfn`6~yNCtX3VTbD zfqhPt{ZfZk*sB7TzUQutep$EL({ls%KFz7?1|kMAw8H&MGU6fLXGP$=r<~bVxFaMp z?tab5%Q*U^74G1G8(nZe)F)$JQ7hbDlG)!&Mb9{%2d!{B2izphiPO0G+u(RNx4*-S zo^cDb!EGFH+=awt+}GRSRtva06K=saxbFtsgGJB#uuze4N9O0*q5;P{1!JJdXX_i9 zlYb3MKe;w{XwEufzggrpEYA^YLcbj*BCd#CSnF1PUz5yOdNuo9qz#t6H})#cIZM$m z^*~;Wne$}qy_(Nm*3^ul%jhX;g*&^* z!0}GQ^TYkntH^3Oo>XMuMu~V17`Jqh)o_Ow893ezIQzzZtH^4&gNh7XN0~dnZ@0ny zCE&&-+%j6z6Zj)<034l({rWIM!(ZRDF5K042c z*yF=Q-sA6RZrfm}>sq2{3wzk&o`8?7sUmF6C1QM6ldO# zY$nS3TZ(7>=QU@q4-_#r7iInR#IyeUnv;v|bFXCmRfGP~niJ11BF0vttp6SHY@fYE ze@_u(Yf;wcnPvTQ_yWg(_o4_MvM-7(LvH)nTs^)GgF7VrAKb9>Tqw8=Q`Y<+oKZ=Q_~y z(SNQ3cckUif$zVp4;T3^+ehnW@Dk(zCBxEiOy)Tnq01h|jg)4v6wxi%XL{ z*MfIpkBHvL&(%rdVFUaW5%2$pid@USW!?(UxiFr+$oP&1{Fs2p z|JOv(f4>I2Ye@X`CN&;hFzi|XGN-n+{D+C}_;1r3J>LNXG^Y-&u*XPdEOm(3LmIH; zW$c-nQ@0I74Cmj<@4nJ8_IAz5+1P=a6LYKm+Ep@RsZD+l7}S8@HsGJo{L3Q8OYDb< z+SP1B$?YFsG4>-Gusr{beWqZ+Glq!p`&Cig=Q+xn{(#RXHTt~B{@{@VJlnzMks@p^ zBm#>q{N>u#d^{^XVzmup@#P$*l=)Hm#1F&suWOD^`1l0RfcKV&yN11scS4MVzMvKx zi|~0{Ss$%W`|`YaCSN0@ z)8y;MV%xrmkD5kbd>6r2tFuavy z7ev@~KNIh1BJ8pswK}{kzVXzI8v1$0yL!8rs5#hNLwe6P>G!XQVhx9D-OlcWg3orx z7CyG=D`NF|BG>ao*hNmReBL7B&hyzp?*b8e;Jx?s4R|p4rH&BtGez(r&Jnt<(J0Nc zEo#k~soCN#ur1<<^}a}JY~|;LDRb=IE8_e_d$(y_vqwMF>|I#+*rU&hKia!p>zY08#+p5_@Ui#2D93lFcr|;R z=V*_dso#LY#~!ir>1P}DyIWMV_c!rt_Bj8J??ugdrbK((-8FkV7hK-oUl%@c@m-tY zXC(7SMKyar5kJPqoP0MeeC*vPqJGidf3&XI`;quHd#e;a_PE!GKiYdt>zci9i(j+X ztMIY+f+)xLgm^W3^B0`!=l%Us;bZS&5uf~w3mc55$~>R9PsPVpw)cMFVdrHL`y1^| z)Ee8IJL=8c=L>)Eri!qO%y%0y)}I%lLv4_aDr?8jU2v)hU5|_zCJ8pcoFU2>d}j>L z3S-WzV2CGU4h@*$6%76}=D>hCr-GrL8M8;goLRx}9L<=W0_Lm=hCRuctpkSpC)W-A zjM*q)&aYs2K4#2n0mEKpKddvRcfg!m!O$xivv|Oas9-o788ctNoL#|i9y5l0cJEx6 zFz(~;icjC6%R4hU^65UFROZ;n7C7QtR0IxU&miPHk8O`k(@LW|+vB$(m;jzB4AC!Ivr+;?Ef3u%Bltn0y9_ zEuKN{*c@9vgJ9wre71t2o;kLi#B*#@D;V}9W8xW{RKcL1G4Tw(T*2fsNIvllK3&03 zlk6v+!51r-d~WUiXM3&>_U;xDZ?wnRtl9HBWVUx-(Z?Qk zkVkv;Y|Y;I!q4{ny$O5ND#z!%V!!Ymhxe>nzULJ__PG1MBs!z;sO8ILp6&VlD#z#V z=GePNguR$AcQtWbD`HQXyMOTqZ$RNA|vVbUj;tiMRmKRfBui&>wu;r%^7 z>2tQSK6`F`ekSC4!bkt1ARk`j!}Lk-GTtilc%GO~5MkFnXg^~MpWb<0L=M=sy?4qy z+v6SfXs@4m+&d$S4BI{C>hbPbv-Q9fp)4aJe8y-IJgyQx zp`Ic_XV|?z*?!D(Rin$`Glp=v)?8&=C)UBC-2YUl99)SL5FpWha(MdRM5%$gD>hB^~*2(8~ie%()NzlPYv@^Nr#Jux<@_NmP@#Ot{wdlln@_r7I4t*Nq z$@|Hp8l4zV-p^YlC)ap)=KbW6gbsCbee!;ODjBuN`#G<8-p}WYPVCe1;$idmqS}5^ zt5{?1YHGpjlVizy#bXtnvw}|EEBt0V`3!SkWjpx{Uo9Q_HpY|poX2anllO{e7CK}ll$P6 zq7&_qL(J>MvW|Ax&!}^Iu@iN2AE1--%6;&*bciv=L%pJ}zFOzJ=!2z1-p^5*XFIou zN6pctM#MrNd|d>Nc~231(Z(X|*y#{hBD+PVSJ=BKzW8Mjh^yti!p9Iu~ipnU8ij zLs91pt%+ld$i7%do!7Kxj1^gj^Br|=)0+B39ehWfL$xN4sKYsrI@BuLA;h zc34Lp&Nq3C6FFw=MxE1(PPD^46m_^0a-HW(I-ECj#*6H0{-kqf(TRJpK+++vykDHz z7!S{)ti!W7>fBz@Sup8vUu8QBC7su`X2kk@BkABP@7Fhz&Ooj6zAv0~o~hVbB8xNcX!t5nRK`dICF7NdnKI@$~x*Sm2}v5`Y!4$t#y2c zvJdS2h9dU*4H317m~RzXkMcP}pVT7u<#)7>cIjpGZ1+9QbH6Vq9zJb%xaQc6zL!rr zhiT0{7IuWXtQj!mn9u8vDi~^PKksUudw7k6A)h4! z<`m8I8Cy%d|0n8EKB*J9*jH;8nRO1Y=xmg9Zqhp63%vhvcVmZoE+t~$7_4($dB3$! z-czu5v&ee^E@MWCXUuJyXAJ9%85S_y4H-j>8FO5~(0>_2O*4jPq+`3Ug5mj{F$V_B zT@}n+70ez1b58}s`ObcJ3Yc3f81yrScOK`%dv2})J)JT1i7`B1GG?9%hBIdj&$f)= z9ArPe1BNr1F`R>p;W=SHJV!EybDc4qWn*|($QbVajEU!sdop6^HO}8Eq76jo@(zp+ zXUe_5iRRHR?Of37HFwkb02PS%>5 zMV((&bg1Dt(QG2dZ$vS#6SdC1c1$|2Yn|(}XVSSwYkD%~wO7*lRBQG;_U+zD=X|ZR zoqdwdAzEW+tjKxomvrcj?CY;dr;pb3cZ~UON$1~1C&s*g(z&VVL^}s0olDC)>hR2n zdqI5|aZmrAbne$W@5Mio&M>X>*&$bI75zO^^kN~o)j3Yb9C7SB_q%ZyYM$e~O}tv1BLnV&3XXfLhNJK8 zkNYggd1njUpn$_4`{|> zzWn*2=G5?35xNXMqt2CDbH7C$^rFt86&=oM)B(@E5$#Z~s582vvq92fFRxiiTFcEtkF~8ONDG@rxa0eSRT=R^1Ry_KLdz8T(pYFf! zYtEj-!zTCU%_3~hE+R%gk&hO^C%$7uoNx9Fn~YUN*%s%&X6wSj$JTM8`9;yz540v0 z{5q~PG`Fp#3LiP|{N~4au?rs`$BXcBr^xZHp?Qv%b5pa`xA3v`f+*+C&%?5fS@NUf|O= z?g#3JK0f-0sPA1O*Y~HIFD$}__i%a5!C+${5%!QTD>8o`&B+D+l7a7@g}-Rw7% z#CyNUKIqdN?*-!7M~wHZ!pGK7QI2;<@$%lDR4~+cDG_@|pByW)5BAo19ufG_H|HOH zd`}VK`vH;j*h_QUzz1`_ui6K-vhRHZA0OBtCeFWoOwydbd{AT``)Hnh{8qf059(@u z^s#N>lLtR%B9G|fZ(8>f5s&lOM049(s_>C>{>_j1asJJZ=VsNwk1?%K_{79}8a={y z9Ou2i<~eW9zkNjCoPYD9j|B@KA5V(7lVaWnXq|m<{%tGzpf2V|ADsWSMEKzRW*_uJ z_VK!SV0`}FBjC-CKBg2tK8A^?Rm|h>T4x`Rh-X_d56-&z(Ff04`1lwh%02Q=@y3bJ zagW?s);SN(f6d3Gg^!O*MA^r4;<5k4&NF~HJx81j=JDS6y4I(OqAy}WZ)oA;i+ax| zdRXNC;xpSiT)djC0fmpPcSP7CM%yB`Y-@kx_#2C` z125P2UGaDqMAlT_SgWI?ALF4;wfe?d9b3WF>KkiybOlqZZ>-fZ3FBH_CqB8Ndt}jx zwPFwA9Ys%FBm#p^*N0l38~Cm%{1JtZkEtSZi9N`E<+F2wc=i!(QDevZyyn=7@uHh; z^(z?SjkXRdeB!!U#Jv`6(XZLop5oQw`oF@*)~zCJJt1<>@qEg*el1?j*3SzcTN6as zdQxOtJg2j*&BUwO+Mw{Ub&CjFPl;^n%bMr?{egJ4758_=z>jtOZsFtOCJ{d3{<23o z-o?bT4{R~$m4!s`v30Kq>_m~{<$PsZ)T3q#8@6?i=GdAfvaN4wo^8D+-WnqJisO2t z@Ui)C5jjp4+1A3EXIoRmtJ$Ld@UeBV2wP8!Y^#^%TZ*U$JlDsu+$|n>WaMrf`t*xs z-aF&yXLNk_)f_bjQ=31?%wQI%Q zO8irc4sm>2l>2uT@xb^jV2eFjzVO+jej@I+=S8l?3YzD-Q*S>wcXu^NL<5 zSnM^`{l*FgT<*8nqt{n3O?AH^VO;lT#Q%|qT3uUoUeu>+wX){zYW0BR;JaI^ON8le ztuC)%nrd}v1=Cck%M!-5qIX>@?pWfFwOUo{{Hz*WF!=NtrpFEmeBYn&`xHL=F;K)g zcuC~_;Mtdb>?0m=WgmM4K0c7+W4FS`M_&;>UKZKM4>fPM=RE&sWzTuWb$8G2uV9+? z{N4(tY0vLV81MNa;(O0|uH`*nUA%U+V$Wx#R=n?Zw^p}SFio|(rGjay)r5p`t*ATo zps#K!I`Mq0C0_2`@#2BWy~}-Nemoyn6+S+07x8Wq&&S$YXCLQ_XIt?Mjtu;GK29%u zeB36&M?4?vXq|l=Bc6Tq)SQ}d)&>WD^uhT@A0O|ExZht9`3$bBdG>LDcr_oKfAgac z&cA(ppgBHX71_snnr9z7iDz3ej~xO(`q-xM$>V(yK3)^q$NHLQADow(4{|m?`r!P) z#|Q7f_;_7p9~)@Sdo=ZiXDq!B@4F)K$h`lSEfr+W*Rn-}?5mnXmgVO&J%TUC$odVD zWBgQesOfBdEFJD+W9cKl(|#aYO@w{!A!_iZ$o4nXJin9U%klC~0v`RG=hH!!>yz{B zEnVlyIU&!tM2>^cj9FYfV}@&rNe?5RQD`5jl>gI!>%$n(Fvu1=Cc=rxM0>+)jMg@$sU=J?8i~)13DN z_7EOt(gPlKb{(lzl*e9JP%_@d!O;76iKrF#fPK|+;5&dZcUCYR1)qKO3OMS;-SvLa zCH{V89&wyc&aC~hpWryNjM1c)tHt!PNFN*6Ngmajh;E-?cia=y0dH zRzKA|pKs!0un%X5T&sNNW6!d7b!14#=IwEteavkYa%i7hE-imdk{=5^nt7Gm*`Xpm= z9l^vp()SsY>j);+ksgj1*OB~O$Du_h)^Tg`+SQS>_X81i&vkq|$huQU_A|yxJ#s(h zI-XF$G}V#5&wiTfNDoJh>v)a$)Pb5GQ*>e-w-b-MlQU<`g_?uGC-vbBB0pPXzMnhr zhZR0PhKRV+W3T;6>-|LNQZHkv1H7X}aj%HOvcrOGAiia(9CyUVOBl5t`toVCQxSGFS;@jV|MJM{h@2vQn(!yV?!86I9 zYp{&??xRUXr>{OecGPTL5pmBZ@;)JlN4#;5Ig^&rx0dC7%+J5YrR&;Ura61*{lXr; zGlm))bA{#^11@7?O)gIu*MxpqRfO)PMJJxEoy5y`6!AIl`!xd(k9v^1Wp`+1SyN4V zOV|0a$DF?okw>j2v5r$K7_hk}v5xd*_QToAm{>>pJz`u(&cEwO|Dn@QO=kLC3*^5@HxwT!vB`YK6rMMZ-0@;E}DH`gf8_0%O?Zg*G1sr<-Ph!kTva9?8V20 z<4kvmJh0!c7bi*{F|Oe&;;$m2Zyzff*Dk*&B?n*2@8KYe`PE{L`LUNVR_E9* zKjMfO=XXVkf&BQsg-*=x_gd#3IafS#q6cD+j0k-1GkeT;8Q1Vg&AH#>-t4AzyBZ!* z@Ugj}W4e0^rH>v3K)2GMon&le)LcCfHw+j4N z!z~J*c-|4^d*u(}WgndXnvc~2Kl)g?@bU4kDEs(7@v;xjf6YhFz>hw@S@`()P?UZA zQM~NqO9jLJ#D1GA@S_j}Sm40W-dW z!B@t_dxrhUe(14`AtqwxbDSt*e9vqyzUw%;==9U4$KIN?tK*L(cddB;jV`HK;+R>$BQc%u(>9&j-x7=raE4fFs>ta!pb6QeL>OTIpVR8X6@?uyyW0({Wv+u zx>Lt1g^PPmEKPOfyL`rgYgfmsDww7^UY#(mfLn9eA<`3_huk z-!G2~{CIZ^DSY5PYi=Jt zOUQp0_}+i`zY6^5d%MCXzw1T#K2+qfzh>=vaU;ozqt=T&|1EPY*d?CaBfSfsI35(` zzG~{lM=BV6Wk2yuKUBdq_2R<`o=F3U2j5#_|XSFYae4Y&pybLp1oPbxn^#>&-$9;VZ*)6UR$;hfH+yUy-bIOJpvZ&xXEnFJ z!bYFAnd6MP(Z3nflpD{7h;eRfi0|C`6rGqG@yu#&p9$L`->k!)uP8$I!=f`tpC0TF``hlU>@7Jq(BmG%HiNqI-PE#tR(1)p&+4r3Zyj-; zokzQVI+xgD1<&MlsmBZ^MUjd*4? zH=b49-M6DFn5Nv0Nf_rA&&uIN$GKVOD)Cnkp^J=o<5}s@n*F_7MDH`7yL?g`c)b5( zqjpx#2(o-uc>Wug&kD~YY&*_*%9>j6oMAAJIXI<7x@*qW6*pDVUzCC^C(J1coUTd+CLwZ(Uy6N^sFlU!#d z&nd;$tmOGr!Olva&lGIVGxiHVN00mIUIWYf61tBSop_%5i^sm__rZt614mDPRm6Fq zruT@<_ql_ATjAq}=ivOJej<+nnq@!yT<|)P?coDo*t;U|qo0clA3uEmLBB)f!QS9! zj0ii-(V-p;c&Cf-i7ej%v(gt2$PRY^_cg<{&vyj=AYvyDKKWh+mgi0@Y^!sAf59G^ zu<@MVS#*vnI`|-lS;_N}Vry3NysuzqB~QLvQ=^<`Jm>cootP)N&PtvS69M1u8`J7V&+xt{=&NI(- z4{B4hH$nWGy|IN)d{>It&uDLm*4W!!Nm47d|kRri?ENqYelsf7AZR3D{?l5 z`<57v6M3K)_m{Zi9pt)@AAW6%e!-S&V1L_+=N`CPb7DMR`K=&Cj;KY zB5c5;XLv4Kc8_M3!KYUk=*DwKk1sBAkMSzMSQhUlWcaZx*DT%{#O->5%Xw}i9(?j0 zB#L;~2gbFo#qy>}hvmh&{s3oN`XY zkZTuvWMINL&TokC9_e3nsI$k3nqeCmHD;cBgthlN_XzryOE82sLG&=%>SrPVAA>#KZRP zBKHV(z%$?-Eb?B*KFD>>{S)Km*&g3x#%j&EI7Z|_FSdIo-Y5D0@=PR#rA6dKJ;sP? zF~nygnD`!ZuhztHoXCS(&B}Ys{la0(HNX!3mK1rb7~pbuEyM&FvLeJdx~6_ zTZ#_v7aqekYpTnR(sAy&F24w}?$l+Ba5=}Oy4+sDG}YzigmGPXp13Zfi%zV|2=SWg z!t=jXUD!{{x>FZ=x4U)WUdWiHx^Rvo#&vl{d}>2)T~~BsUCtD*sV?_R2OH?+ez_ya zx>J{N!o_&Wuc=>ds$iPxGCpBk7tX)yGPdZ%x^QcTT2*Ai^I`-M9^Vq6!_zw5%@q7&fEne36yFf(l$A~e$%Ka1REK~Hl z)AQUjaX)5e-_NaJnsPrUVVwIt;uAML&$ED7V(y%krrdeInU&o6xo>xKzqEpB%Kegr zaqj$V#JOKwbYkw@Els)iDK^mS&c2^o{B@`2Pp@E_a_7A$*4VjkCBAb%rRc=mxm%iY zU$@xkZtj;Cf8ELb$_l0__bU>{xl<44ep%6pxx*tT?nIs$%;zqj_=Ly62D1E4^r3j) zF0!U)e{bnwkMsA4Xg*Pg$OHSI7op?$<1>@@g^U54G3eOOqZQ2T6$~*M!@EHA<5)(E zPp;_RS9Ie0!d2ptgJX8Rz%#H01fQ6ErkKZgUeKC-JW9kcmR@!|&ufkj z=iGz$&RRU|F9W}aiyY6_HLt~kzZegDM;{y`Vju^*zsT`CtT{Td*LYWIif6ZC!!~Co z9^MIS@oZCU5&Hv0C&qJ~c*L`@h+25RVtv*ZpPZ0+e_XrVcd@_mM-RD1V6c%f?iFIB zW*Gx6W6&X9Fb|3{hW^QzxPK2NjB8Ea-oN{cPOR7U;*o=6uGQ;Z$-gDC&6(N1v!%a) z$h9)|nPQ9Bd0wLvbn6Q*Cy7LbB{eJ?(;`lQ?nCA3}d4X_r<)Tp`9Ajbp~inEa-CYpmUPQ zV~l3_YnSW3k~^QA>mEV&S>(!h(575pmk#$t&ULdA3%R~lbYiY!#cRrSwPFLkoa;(K z_F3f0Gq)*M_P&-Y@BiLc?4T2K9jA3uuDt&*UG#FUoPWzci(KEAy{24Wl};_!2TCmL z>nlYk<~m+Ha^;S1bzZ55^C1p$VxZ6S!!r0j%gFQn+eml_h&DI$-XG{g3$B5W~_Il}w9 z2ph<9FYFs+pG7ZBl0EX^`$WtGzs~hd&B@tf8HQH{PDda`ddpY z*X<3>@fZ8*7OknruA)|T`<`U2>c;uBEY^(}oNIUTpkK)2bdmF*2HzLCZYOG<>o&W1 z(cjm#o|(E)3;bcz{=nMS|I_>gQT9hpv$9Y0HU7>JMSqRey4)ciby=}|GSBzn55#j_=y%K6lNExDxymNQ1)l4| zJ6Eg={nd2GtP$`xX-=MfL>_rBa&5*}Fw~~j+p#teN{3j_6nU^08JBDGfONo(oQCT9 zy}gXfwRx!EoEv+NZSq}GL>OVkhrMMbvbd$fKWTJ`|h3jrzUaw%tpiENU7irXmx#K&Saf2)JS<*QUG9($HqguG=%yg+PF%{m|FcgNA`1W1w-xHopIi=q951( zJK|FZ;^$}K=)^sHOlxY?u9n}Byj3lU+p_M|a)fX(UTQ)dImcMbvnrUTTAo?KG}Urs z!nl^4`<^0dIlSn^T0SXWQ!Q_n4mQxseR*S$b*GlxQS3u^`jY!TW14FDQU%jgOYYd{ z$F=M)zH9kH(TTNuO1!38?o({kYWb%i>rO2X6OQi^-Kpgf6--kt53gXFYB@MzT+0>3 zcP+VVi9gnIvewk-H=-V8&V31w0S`O`kNej5DKgH#Wz^ELoa2I$#qUG6Yt7zwh&*aJ z#_x*!d^2Of6IZ+&@YPF1e4Iz_F`hfz5gz?C%eedw&Y1?s-RMDYW*q+TV}Flp4z5GQ z@Lt@d`QjpUIqT%YbHn3l&9L2WFRqsy8|dY|xFX29vlml^c{J?>-!n1>e62RU z#CL5tJH*}Hz4*A`y1N(jI{uuS_u`M@c`tZpAeXooQ?zc{iyexM+FooOWZl^dzSHKq zHtogx70k@+#fier%DFh9;JUjPLklkN1$Tz`;yumtUOXpW(_XwQoyCe?J{Nq)v8+3L zagA{KzG>Qv%PW|f*^66+o0Yw|so=W17k3t1-iwjqQ!DPMQKEcDaaXVx%au>&>>r;D z&iQd7*Lxw&IdhirJhY6xfIRXYjtslR@{(v~&IRY)cMb0j8MB^v+0PpRbF$`n&)2VD zrUVRqoiQEa5qtK5pg`{_Y*lk-jOqItaus6bAC6G zasSdh?>lv=;kFOBlPb6l@n#prIPtf+$o>Xsp7(+LGLHP#3^;UZ{gQF`i|<>9796p8 zjMc1$>m|P99Hx1Wb6g7?@1w@iJ2_7JrRI-2!MG6x=Qz1377jV=SckVE_y&FX*{0XK0@LbNvb?-esKG zjG?aNpMAxYBk&0oCBh7=sJd5mp=i+36Ccsb5-EpYKJ z<9#*9IWu?Jc?B2a^gP#-dbuudYo2=qIV0kz=YAsN-qbwf#)_A5`7RqKjlA#FrG|@l z88ynd4)JCe#W?d_#(O~C2lC4}@{4!b;RP3;DfCOm<-6?2f+IGMu`O`D#CJW<)jY>J zt_3dMWyA+A#!0`_;*59M`32`V=g^uOtSwqZgzoDi_L$f_c!qIi+TCTyuz_B_%f20C z-MP!&5ia*z&XM@zUB z=Qpb0Vw|4mdQvar-qk$sH*!YAQP2HE#__!^Qnw7$^SXdl@yV^-IQ)U%bl(64tv4-fk!{hYPh%;H%kW` z&j}BDriP1qF+n=uoEv*VUr~2zh3*w1@{fDLU5)K_dofgU*E{b8XT!4Y?8Rlmb$2f= ztzbIDtJS8L_}+KUz^v@W*n;csUT}75d$E!D-iu2#&wIgrNG@B7TAhnkBy+vLsyQ`h zpue2RGWhg>W$|2aMth4~pXW8lR)@$V*A&d+B4b|CJY&FSKjdf(-^Vg0pFjM>zUI9r zV#o=dH$~qNp*vNC4(H3`bT#pSygb18=ej8_2-NT0RzJO|@K2y3X;TVyi=+ z9<^G=`r|9+Xk4yktpB4GOs$r&{{N|9sAu*Q>;HJdxc zFZ0Z5Rm)|9tf`i(N!Pu6zveSj%UJ)36-=#`vHnk1Ftu97`ae~{H1+c2gmL|endcgN zbzjkm^?zHuruyG49c-YN?~(~Y)}8wE+*v@xIq|6Va;*QT3I=TMyK>)`siB5XOy9DS>79d_G*9Z zL&W8N-mmC#hPf|m_tu|^4t98lpf9iw<}FbT)14T$3HIJ^VQ=%I;}|v$m=7u#YS^6^ zRu1;Kw`w_kr|39_Zw1Ud6%4)DofzUh&DpKRkoS*0@Ls%^Fpl%D;`5yb-8YKPAbomJ z^QJ!CRXW(H^(o(hEX#fR^C0`I`t(rQUA-hga;e7w!6VaKgAx?+~B+g+4u`=)^w#P`su-y;eHd zsP*Y(L6-ZJ=dy91RiAz$o3%6Cu1`O0f$2_<#6ImWd$k^E*QWz2nE$0u`&8_)KkfRo zZw2$e^l3-M9x=4*Q=a9qcJ9+9#CM;5tT}re`}8BNvEA-F9CqDr;ORLAclj4YmgQc| z@%Anl&dfui`92fK|0t#FW2(QAnQ&oc}{k>mb^D)Oj9l2tYDgI`BuWXmj4jnwS2wk#9DG6HP!Nu z#YU}`y98NxYI$#or9+<{*w6hE`|^Pbrm2?qRWMDpygy-F%VouPE$=Bhv6kG^L)Sh08tGRLj>Yn5J63Qo%IU^3{ZKExDH#5OKy|Dmt;2Q^g~P zcwdas`b(ngi;Q@mFY~B(q>M`}&2FP^3`{cmj?&rwC^-$7?d&36!? zL$6?${qcx*3FmGjk?qk-_`F2q0XAb+6VI4&nrFD$fK`jS#N-N=y8X6;3MnZBp&;6 z!!)g~|G&tr_l)Gk5%qX>Wj*dy&J&*=Cuo-Su*Z3ccjC~B-jt#j?VViFds{s69WC-; z|FYjx#3R0_#~i(RMLk69XHOC5hxKnoJd@ya79jY)6v3x1XZD4 zxu=Lc894{;^id*osTupo`y%)_V!gl&6B%=u<{87jWDMuh80Hy6j2Xk7X$*DB7-G&C z&bl$jR51A&OFnx93}-U?;eN}0b_y8IUB=Lp8MAf3460zz&zOw@=J*PRGn+B-UGne> zhFCMEw|K7Gu@ww;%9zCi=7` zXM_7J`)N8G6Dydev+-yJL;kr2@oY?~V4BXxV--x(*?78wX*wG`KXTog&IbLOF->RV zxrCu_h>d%LXCXbo`y+O55_!-I-8mb?F-qh!d9&u!jn6pZeu0T+gYQZilg|d2_}my> z!Q`_6CY}x6x3iyoHo(N^2JciElg|d2_}sXrg2`tC%uXWL?YaskpA9haxxsr)jxC=J zF!5}RsbKQi027}Zd`HWESm!1@1H!8DzXS1XvNv+-dC({wgouVCn#yr=POykEgIosBmun5MJw zZUxhHHa<=mpAGiNXXBMJ=U(u5Ml;Sv%$s*Ga>XaTL_EkZ5P3YSSq=B1_{L!)CT{58H4TY=TPw+8|N}(n(mB`Dww7_gL@|XX}UAG12d-S z&ftt?4Eg68#OLX!6$~~qW;O9#x3?>praOaknPY3ZGdOP<({yKW2WAXCne$^Gi`2PEfCx(oSir_W|*YdApRjD>_kky zYmgr&GG=H6Lp<3}d=4K~!Qek*4iwLRPN-n=T|;bp1k5oNOulQt>=ZEMmTSO%|&dv-(g4Lyp-`JgawAFw`ew z;#uWAC&$)wR`01`n$GHd6-?7vy}g1Vmz+;Ls}EN&O=p$8%r#)0{qz=(-l3-4^%+Ai zXG}b+yt8CX(^g69?mv&8X%^#0&ijTjBQ?kOy&{ioG{c_ja*pQca7TJ}%LCo0Go+%!8I3x;+p>;!h$-qEUeR$~9P<$s9paC6j!Zhp4l6vKB_6wKwxOt1 zjrg}5_Nu8yqoqT>F}GZ!u@#+Mqwy7;T%#K+I=Mz;DmuAF-S1UC)e+_icYTI z8%c*)|37i(0cS;#h5MNc$_S%kLMAzLXQXwIauEy!1E3Bf;E04p#H=V_MhvXt1tiI$ zVgeO2B7%w$Z54CC92Z%|oO8~)zVAEL)m7cMXD;;adyo6;sygv9IdzvqU zGF}&%&xzP;j$a+>o8njL)HTPCYX(`Y!e%~ke%B}H#QEKjpcChJZGujm-+~04IKPE4 z9rC*-DC0Gi`J9Bk=J;{VqmMjB;4EJZ{)6aE&X035t`p}+{&Af+Kl&Tj ziSy&}7uSjN;~aB!xX*JM^Ea@W50B60_)S55Q~b_w>YC%ndCz`VV>6#PKOW<8oj5-p z<8hrhzb_JW;{14w$L+-V@fde?xc_-j_9k-kIR$%rV&huHIYxgN8$T@Tip}tAj?rh( z<2C48*vu!+h_S_W;*1zuTqn-x(*&J3BgPuH6KBM6b#=(-lc4Nv*ckUa*vu!+;r#@iIEN1tbmAP?N4&2%hxZb6;v7DR=`aq)Puq;ge9pw)nsT@p zx{Qhan@^m>+ytFChf5Q5;v6nY(1~-nBta+6VO~s!94-vXIA-QE5qoRO;R)!{4jG$I zoWqI)oj8Z56LjJn9#7DTb9gdAC(hxim=67aEGYXBx%r%hy*1@98M-{KJ_=jsuMcM@ z=)^fpOVEjPn3SLs=fHDk+@CmysWBaL$OUB|BR3yjI}~Hv5F6J4jxYClFPQ$fz(yar zvECdTwD%uu{CpDR+~+k^lD+9DPqN2&4X2;5&kxTd=EG~FBzwHRNV0cqP)`5mV59%8 zf4oLXvUf1blkD+(v+HV+11Gfva4hKGj=8?=+GzE&YzIueZ}Y5UkN(#c{VB57yI}lXvcHC`Fx1ILYz3C z*uD^_+o8jlT?TPZcP8k>IW0@jiF3LwK_|}Xjs%@Jr@LZ0jPur@%;m&mpb#g~Nj<0-O27Iq}*#t`q0*+-lc&-ZbiI47R(<2rFpJm1H4;+%NCkL$!a@qF*|%$u}Ds9 zdaio~x{RII`{om8@vj7(IE&X3bmA=dy)oWboW-jNI&l^&V>)EMqjED1qW%Sj2xOOo9 z>#*@!hx?41e(}RN+hAiE>sii?@&?!phl{aKKiRMOu+OI2atvsXIy@iJfATRO`q@-l z9-pQy_v3B3CN|afU8gPAk@d0tg3WvwTT^YhewlvX#{PQPe#K@!l$&b%DC$hx>#A_eYR_=E&DS4K8}5kncJ4^nreHA)An5KlhyCo%!hJQZMl}3 zei=Kty8Y6Rcv~{zygCh=X`917`{8-beE5B(skWn0XWH_5E8ezkLR&MRM>uU4V4u3~ z7;V%{+x|}5>w>oKv9NJ7ZFhFsa=h5Ddn|0)Ok3r&<@t_WU7t5=rtKC^Tee|a*XPZf zY0EJ%oH{JbrkrbB>r#HTIfnJ2%iGtDCUVXSeN^kmGF)s~M;>tS-b}{JhYinYO1pZ9l_4 zeRhupubH-EoVL6UjJMr3p{-$cfYX-eCblIr^Z6V0;_;fc0|G6wT8fRV+_u|8j<+?e zc0rwC#WwNdcZX)$G9J^G=P+8ms_o-W+c$%@ZoIoT({`EDmd8Bjq}%Uq&9uG2X}bjbai4oN z({`TI_Fe3AUb#N^Zl>)_r!Ch3o+sS4do|N`g46aJ?6coV*vuI9!+uko$D+=R5!W2{ z>$crDp{+RvM>=iEjq{u5L-QGgy?DQ-?LgF-eivgu-gZbcZ8`R)E!S$cb&ubn&9vou zWZK@C&~|t;ZEKvii-NZ98oPfpZFvo3`sKW$&u-fzAoKX-Ii5M0w8l0Wn;FL=vG3|! z9q3GPbVkK=xUOJw}_!&WGEv#pC-5Wo+lp zmpPERHt^hIxPOiPxZZmx=zWu*cRtEEw`Mqc-zMn2h%&CDGaWtmoMgC>GyQY* zcn=}&-}5Nr@#E_8JRa9$Y@5aOeofG$J&u=a@3#a!uJ7dL>hb&%@0YQ~aCNq%M@C?r)L0P?EaNk-AV?#b|S)(amT$WjzwgaOtH-)6v7J zF|VwbDf$Y<38S(}*`zkIDrk*Oo2}ih+1kCEtv$Ti+B2H1 z&0So`@7%(I8h01eSW!^p--R@qr(4x*lsIOa8JWS&)*jPrZEk8Izc+8T{r1h)4s5n| zRI{~bHCvmTSIF<&jRiICEvWHKL5HYPNRYW@|?`TbrA#J!`t}+~ox|ZYrp;yr9PO1vTC-q=DtP z8HOF2t?kon?E%f!p4@D0ZgwHRb5|DBSXxlyp@JGO71AheHV$01HAAvW?vfYK$nTabiJ@DOO`lvL6>0)VQIbhF?(QL(7zBzXYbm)jim)OzP3!8@S{yZ8(S6B*tMX>(1IGr6x5hl zP~-f98rK%oxU- zu^PuF+jy~{##;q7z9^{io7LdeTtX}*EyC}UO=z?$sIg^1jSH+FM<)AmeL;@)L33n!!Du_g<6WzPnU~bdX9YFB zw;BVIZTwtN<9DmUZ+Z#Q{#8(;g+1naCEIw|+Gs-KX{*7zbP0aEQcz>H)!_ZK1REa~ z)cDG3;1`4>8>Kc{-aU|B_KVDq&8)`IWQ{EfYHVdS8k22wE~wGnYV=FCu}eXX-d1Dx zWE*=H)aYk5c1gC;s-Q+&tHFC_3DnC9YSdZ{-e*s+u}wjZ?X3oWwMw!vOl#zFdQIdy z!ru#!<97t<^XNchdXpLx0*!N<)R-J-IQQ*iy_^$h%x}`hz(C`=CN&NZG!{3hablpM zzfH)u3&)REMNgQYL>FV3&E%FydXuC#OL~i>OC`Nb(#s{CFX2;FcF6p(B-X`falHMxm)%fM-NgakfP=Lb! zN&W}y;CHHUYtgD`ML=r|SdGPoA00CIf|9{apUm;tPQZpQJ(&sE{(%iY>SS<%n!y+L z3~uyiFzJ|1l6119QzSiG(y5Y8lXSYIGbEkK6gQ_bc1e65b4uFq&Oht*Eb#>{KaiuZ2X0ezqqZ34PP@eZLr}MW@deC8(_n2^bBtKWHxG5 z^i1HD=>ZI%T|L|>NPR5oqfj4z`pCOR<|2=_m;NtA<3#bYiK6+{ zDE(->@_)g9GfKY%D+cD)t3e#at&08?^q6T?w9-U(j_{l%=|3f%E$O+Eo+s(~lFpIz z0!c5F^ddeqOkZq!VZ-G{247b){juTFG&2y} zKG<+6lfhS^%ph#F*y^xti48yDWN=d`vlX_jvDIVihz+OMOebs#8!pE(f5X-p+jgyr zUTcDJIL^VWj>~X8Z?=azt%_C!^!`6b_wTihu2s?NYv?(?Ze;LNcV-AST%Km|^)~Z& zZ1^gZ*&o{oY`Cz^jKp>zHhc-n;Afu9A=q$JrulJgRrE#^p2xWx=H?8D`Mf%a;J=(1 zZ#Ln9=@C7>74)<*;@Je-rr7XRFw+hjZnS3FV=KdkA8#`i*ebDAVcP;*HMSaT*;Ykw z$9i&lcqi!LznVv_ir$U&5T|Hlr|0*Ao^xw*{L7JyhX4>yP9Nd=XxB%+UIp}upjQXI zQk;)9`u#QZ%y`&b?s)%!@xJ+WE4|+z{tx|j*5Z!>zYERXE+E|%8@`}scEGkHHhiJU zbi>vi8@~KzdScrd8@?=McEz?EwqDqJV=J&Ke%wTKhOl$AeX@og7wGZR0zKkr`z+|` zF!+Bswj;3NHgjeawxh5ejcs(RqR*SK)ZENr9b-c;Uj)76?nPlHcb}y9OZt$c4@&xg zq{}6J81wkcl)b`0-g%^{vcSWyjE8IL+t>dOeB&Gjy>Hl6M!v0;WaQfpuE1OJJ4g*S zu7@PXt8_dJTg-=F<-1BrM!pwNmm^DEuBpY?TwS@^FUiQ&I(2z{z$^F`*fNf85h~^S zy(A;o-_+%-r>@a=?aI}4Nk*=Ismt>g_2@74TwS?#Ey>8WC3ShkQI~5zzj?U2a)nru zk?T0>@_L2eI%t>QP+VQP3M&P5NPU>4TiD zN-}abp>9s!@(@4BgWvaDeK|jrWMmZ=eSI5WMu++wC0Ae8<&uo7i=zLSWkP<8mm3+< zA6XSkGP0_PzJ7!!_vPJkq%l*n4)V^hEpE5O|OzmA3M48(GYF^i}<E?F`1_PCnliHn`%`QD0oXsE`%`NCy|F)s`;%&bY`HMXwL|Lxoo7t08;Wf} zZ(8gzxQs6Bh)yIZim8I?ql4;Uf})I|Mj)u+WolTN8WKjtCy)@Wj;M?g4Yv_>h5MyN zLm8DnOb5iM{2@9ZMiqE|fOx(KjEUzIQ+YlJ7Jy(caTq(4;rWs9{O~e$Xqh^=OdS|H zzaMJ7UESe0+&b?c3NOuY9IU;U;W$uxUwAl1Nl=5)i3CM4RZxe*0%F-;V!;k&1a&Ne z8e67Dm#L$|hz>&)qIHI2tc}PWj?p?G8IGfLK+bR+C!QY;W8yi*RGyy%3vhU}IE)?2 z@ccA*eoC1-xlEl@rcMZ*ABS46pF13Q920av&Tvc;&nLr} zcup~u=jXx#9G)f)V}~+4p9#;Wm#L{`YD(z&d8mpW*VC=%{#3Y#v5*6Mign$)nyb^K znxb4KR)VfrlZuB<>oa};6vHF^9EpVwVo59%Q^j&QEFgr7Bn0eGMl9zcmf2-$Rv5^9 zlt%-ZZ3A(KVAk5jalXXCNAM&LimBqb5f&m@1AHumJZT68Et~8FAczIIb^K*OjSj!cd+iXS24Qj~iW*T%gjw`$?v zsYhi-(aajpFT-`!6*U9;L-S*3diRt?R}0@#Fb!qdyWL{&Z^b??&}5bCg05)n6B_f& zK<=B;qApCkqVJ+TSobOF{Cmovsju7a7DjyZLl{v^#pp*^fcdYG$;BvTFnSn_9xPMK zLqI=iJw7J_^OZZBIze$Y_n&@-B|FnTJ1(fTy@ax$Y0Q0Kp78NDcsHbki~qL_+N zB`jc4@M#udL>Y`;2cuPGYGnwhO6&2N7N}Pvivn7uW0N`brUR%3n%?Rdpf@cbcMb(M zgwM(ZK3Up&Gno$``|wv=K5q!0I+O|@imCW)2MY+e9+~i=3_hQL&qrnIgEIAAh^UKJ z?W!|ALlQ;w5kfL^=yM0r4$$;ID~qnipIbzJ&`{>k2b!}mdM|;|jx_dpGNYYP=YM7y zeJYH)p;Q=AOvPw-SOBA)kqINpVDvp0eOso!4gu|<_4q6i)EkgR0e!1ulR5O01E?=F zy&q$MezJhvITY9sK3^yB*^9P*O6J2ynEW3tpC5$J-Y6A56jSjT3JVB$A7sLZGWh%j zK7W>}-$Oops0ez0*V%AnQ9gen9y5V5<@Q9jKQz7K^5}^yQ*Q4x1Px^Z{jMPsQ1jRC z=FG-FJn%B*iD$M0Q0EtyhiA5;at1IGr9zBiDq^Ex0fr7iCd4R%SV?(z!K+|g-!_~&(a;H;ZW6f!erSUe&wD@Naerro>J)w0h zN`)51RJ2Zm1rXp zNp5os%nusM{A#PIuQ{k?fhCm>z$H`@ef}7Z7i{lLTn*Qg&4(D#BPNJAXtn{h*1WyE+E!9#C4li zx?N{?AdBMa?98tn99;a%CvW>0t{p5ccYXyn)_i{5MdLdp(^`f)e|t--tI)a|r9z8h zDq63=0%$#rOlVOCt%0D`zg+bzSAEOXo*_2=`H;6qxpPy!zm47R7tArQuHmY15QLYXP<5~w*h}jvGQ8q4jP>#@H$)Fsj!*T{?w0OQQjEUzI zQ+d9L_PmWaj1VZp^Aq9u@#X5+ay2&ed{b0Kr_=G)bN^Vlh!K&sbgXqf|5~sp?_Tan z63b>VFR@Te6-x~)AcQgr0Xvit%c+QEe7PDI29ia2G?4K&5O)a1tz8_aNgTDXE^$yy z700%)0QWs{A3Ky0M-FjJELUfgs|jH!e?wJtHchml_-8m{GGXmvnIy4vhIxsFVyakn zfdz!HqlADR%7|qeVmZ59O%4Ou73I-D&bEQLV={T|;+QUR>;~%+2gOuz41@)^zo)p5 z9mr_oJ~3lFzq;QRmOG=iBpz(GZjhBZ{dQ9SjRVGaQ+mZz+S(WneU~TwM|Z zIz;OosYNiw6;Q0FhUjBXT0r=wIDQB1{X8Z3a(S;&MD zWiYw}jBYDeOG7}@wcZS!%|sRjbeoP%=Fl<+&^gfb?ur3gW&yc#D6k=XmL~9-MO({~ z`TP@g{#};Oox*1}N`()_RD3Rj1@O5Lned?uJ`aM=@^W=w$mepcH(zI0AdB)@j(E%j zdc@&#B{aQVFx=AbDtg~B?MR7ghOs8iYTuY(pJsrdKjK$?nr@+RV)4G+$ zpGl^58|wV0Ev=`7*6k=2S`<^!S`G`KwG5fiq6}KEg4WCB>ctS)16uDvojrss3hZTP ze!b=Zdl;JD%GmMung!+u4P}14xVH1_5n6vOnb@PK^H*A8{}N)4p;U-bOhxQPSOBr7 zkqI%%AoeDRy%FMiNh`gqvsaKsalPTpuXh|=uR_y%JBI5Wi_4u~fsHkvU;m=fyGH7+EXi#+(DqEqdD^yj5s;Dq`V?8K%TUB`9 z249(K_;6TVg}n)#te+{T=h@=n_k32cgp&%0h=?DmweZ0_Zd#6FQVZr#I;AR-tyOP(3SD_X@RBh-MHJ z08ewNCzstU7x$3aMPuQl@q20(oHTxSXMZORhBGL5%CL{bwI4c>xG1KIYcwn%u0tdo z>`+ErgAvz=3N^e!4XaQ?!l1^W7RQMWsuP16ksQ=;6i?wdaRfE20`q^U#54rO-z;G@y znXi<=V;p##SfP%uP{&rNu_26ks0Ax$Tu-zl+{t>p1|j2mtTRE!Y7)-Co-Bb}3d0fz z#Z-YTf&~O}rTC8>$_ONfKqgkGGb+@C3UykAIwg$dMkqvMnP_A2&w!)m7SRMJnA4nK zPRR>qk_59DmL(X9se-u&77)Wyi2*y55zILVW=4gYR-w+WP?N(*eAFUPXH;f5kxX+U zIon3UGs$22Xq%iD$1I8CUf7j5D5i?zNmzjU4~qNPp^P{#L>zM})Oi(Zb{ND8R7HcB zV}o#~)_I9B%+8D9B8lNCn3WhPri$S;Sb*!#i|g2-j2Ny$3|CaB%PZ8S6>4r6#wyfC zXVn$SVO(y*@Go^H)!e*5u9iUl4Z{)$#Z-ZO0t@i}E%6^alo7~H2xM`ET2!GHR;UFP z>e?`tPod!5QsMo_y_{KW!|@lvSF`jj)bYsDx47xuDcZ0`W73z)(bz6m68p8MwYQf4m$nLTv-1&Kj1|dt| zZO*_h)g+vy?;Z){FBq0UD5eUe{W=oJ2FN53$_V5!1oB9QdZ;pO;8QA;nz}~CFS)+liLVx}fc>}9U?7%)QJhp(c@SvEA zM<-aoz}6uX9+bi31@L&TLOoNVo~lq!hA#+Z!Gj8wyPsZ&~bm@PdH*UJbj@xGf<1i=-42r2> z90vngzi@_bYFZ0IjJ8|^{7!X$}rgHU6Sb(eJ z#Y5~+hO589)n6*qPZjEi(A$Yx^(>v`knu>e4_yBe3>zPo{jb5d9eCF*+~5#u#fu!vdWlSl#^-f&kDfFf8crw>ij<{!pG8n7e;5JR2WfA z#pnW90GgS|WH>2<(R!5)s#T?0r&6`3RK=C%j>v^t`y!oPj4X<&Ri$2)h^e&FV!8yH zUYpA3l~ie^y^|6&6in;D2=1iF!rY=#?xe`K$YPYokQTTd)9J|3W6XCF(* zJOT$g#NLCZH=r_l$ve;z^Mi(R1U6{wf@}{5S)T-C@6+(WWMm(p&L3cr^%rCxqEwJk zOoi-wSOBumkqI)&K=yYa8(OIbSE@lFuOGDPk2?DaS(MjM9jY9JBOG2oL(|(o#%qM- zAGB-T@F@2s<3kVT12MpR~oO?Qax3QccX zY}KD`iTOc8nPEANU64(5ke!i$Y&RO7o{X#)>ilUI*;GN+8>NDbVk%_&zygppAQNPi zfou+tomZ)5SE^YduSTu9ug(S`i}E^8hblAdB8S(0(DW{h@w&+Ja%WgzLvYP@aLr1< zHJElUO2#z=b^e7G*9C%WC`ttv#Z>#9n1MWwpDQe7GnJ3?z8 zsk2eYqQtI3RAz=PaEKiZP4BwO=x-ehEHOW5C^PH|ja`sk?jXA~0ofQDUXYAzEb9F0 zEV63_*)b>;WE4{&I~^8)>_lXOj53hzjjum9RjS36YEj5*f>!;9&dxv<<#iJf;CG!F zMN?|LTOD2#q3JD+@w(OWa%WgzLvSsw41XJ11a0%%koh8%quE=NX-z_%ztqyYMQBY% zsnDXBiq;%h0IliBgcfDcdJq$Ad8N9qQu&qY?n-r6$m{~$;6j~Uge=NzxiiNeahP2U zP4D5#=#PYtSZ03EQ0CZu&K&cdId-?Re^imZ-!H0z4Jd_GSim3=L zgar`10+|q`41&*t;IozL=}NVtQauskyFqI&(%Fs3qWGTGk;|g?l7nwCG`$yN_+GO3 z+$k5>kSX`HLu`e!|3m`4CG6v+WO_HD&VSL;dqL>kj8dUTF%`XsU;*@eWI~TJ=)Del zt18vXklVvr?-89niY&@)72+{V+nWxz$Drx0u8iJFd((3BgN8EgR%-YJH^3Z}kJG@L z$xxm^oxj>bc|)K)iBf?=F%^`TVF6H{MJ7-v1Iqh=@@`1v6|MBD&i;igO5|NeS$2?ipjR1Zus~Dt!ZU2j0Nkq{`lz+o(#fCw#_fL+l67IO*S;aTfR2w}p65 z+482}?bWV|qjVH{ljta>itc1sfT3d~DC|&1bXy?0$|_Y}rP_y~jYk#2)}eJ{Xq7fJ zcjU@ZY#v-`Z})>A5~{`XQ(#Oyr=56`!%QXQ&PU6sm)&QC>c zbX>Nw&ifslajCOIV8L@YJK%WvL#Z)oQg$0Cmo`i-S%80QGV(eU{ zwyjc~!T{%?3c)+0)7b{-j?T6^6izl5=DU6Bd6jOPAJ1oHAMdC1aD8uvJ z;Q209s%MqzUZr-bQagnH-vNc_0PSM^_j|%oo``wibhl&S?^GqXw0Y?4V2cxmNFF58 z5Bv3!5SO7p36Wx|5FdvHM0TG41j3}mJ^eHR=&3nk?EI}EJ4g#Z*Rcb^C=rgVNxz4^o z76mji7-GJZ;7|w9m(cVMi2*v)0&7CzsgRQOO# z#ph300G}U`2_MSfa}4;5sZvK*sZk-K|7g{}bXHUnM>GZ@nTzt{9Yn>@^p2~FE`rBf zM1Igv=FriWi$BWlhjS=HW5*{mYJoccILqi*Vbl_(!iZujMjOKd7_~trj3|TAsbDm| zN{tHvZKCxy)!AmqqH}1xjz_-jO>h9UgQjw_%H>jE8;%&NH# zuRWmYT@vFp*Ya{_RbWGA)%gyta}#hi(C*x1TzygJUt)1xEV%YUsoab}gbZGwcS3*a&EP3#)LY;LNZaEHOW5 zC^PJ8i^jjwK{nr(hcoN|8onVJ*+|s+3oWwi1=)cp6=W1sAsYh=Kz0~1K}H$KZUeHV zRqEy{wIt*c$)Zl70s9H6K5#7#+2D-yB z*hb_I#~>Y$3`e65$Qh1d;`trMbBd`ve*_lburCf{hcY}r1fCyMtwvU>5!GsV==`Io z^|o_|;~?w2KN4P=;TWO4m*E($y)Qf*he}Y7p%WPnim8Hn5f%{33W)_flo8a?2x?Td zI-*(~7Dn_Est~Pnbd0hQxx;aU4oHUMFddLH9HYhamtjmirxMWv7zU0qbhn_A8$SPkA;gE3nu

      w5kl8|S|u`Xq_v9hjF`D5i?#b67wK zA4mw;p^R8gMJ(g1)wnQ_FHjy0WV{W;9fEOd7sqK5$Ct1!aZpSZ$FHye_rDeQu|pYg z!Cav$k{d!cT6U)T^!RTj@Ga)aZpSZM|)U69BsvY>`+D==OK>S)oNC? zni+<|m)b;+@YyyLf0i>QGuJMb^CcGkkMt4?#Z<9$fCYrGg@k||%82D+#ByP^niB@% zp*$MMg*Fg(Oy;az9G6HOTfw@-K`~VvU10(4ZzJwwhce>05^>D0R+m+)d0{BqYt|JIt`17zIf6+@f8oQ<%MCK>1Es=1^wQ}HeE{tB$V5 zt1KcvXee{&CCynFy^z3&FTC+qB{Sk{Z~WIRqm{zwT$IWjqL_-&rLcgAFF+=9h%y+x z14eIEtJNW(;H5dvJ8`0b-qNwj9D3gY#MkC{@5KPUZvnY;D6k=XRwwYelD6JY=EK+G z`0rUh?+PEj5J&h>OvPsjEP&4fWWt9s_GX?(i*L#CevaY##o}_OQ($AwX~~Oqeo3aq*W&m;TUtK} zExr&(<`>0Ow4R3r%&#Yr$^4=WTE#UD>aS|`X9(;Ctrxs0hws9P0{hFEUoCkvD)^r? zUWTUEq9%HhYguFOWCaane*L+&^NVlc@mkh^dj6FY-@D_ts0pu}GBpg8FU%2Q6jKp< z7ZzaX4P-)$GKjSXv632d_wGHd^uEqMKo-SSQp0J1A472@t?%Ia5Sm_T4A=S=mpi`# z8*4tlKBDpUlWBd7I=|G?Y9q8hL8;K9n2OequmDzL2B0*716;wA^Kv3bkq$ne(J_xE; zjoP(F?Hoqboe}j2BGNb2ZA9*9?y3XgX!<+rfSlWgyNl;NjOP?ndEQrhzN}+E9cxxJC`CQH^0-2cQZuJNI%2+qm388KlFKL21-sIfF7x zJRb>T;yJ}sp7XU+@cb}w7(0~V`9bh}WQ`h8qlSl`^G#CG=`_-M?vH?r7!g@Zhg;Y4 zuLbj85Ph)3atzE%EEH44aw;q!gcBqL>`+E5M?0^C0nnan22h~rqqF}6mHu2DyYp-e+nbT*B(q4=YnF*$1OVmVG? znGW+33&m8iTm%b@mwX9}YwC>2H&Q!!cw3qTXTf{QX3 zO$Vc?HEK!-=x(idkIwiit|*|XIySigKF0yXmuq?Wo9oCa?HmipohE?|Sv{vD@VSq+ z&PnETKkEFMmd^~~vmB+uhhi!|Pr(BCJd8|^Ys%nrG5B0qqvq78^Fl;VYt?6T_AIg} zq6-m{x#XSaAbJj(-rSn#ku=XD@`HvlhvsO`!sxsNMtpylH!qpd3#jwwT1J-$qZd&s zj3}mJ^d>BT(Mn{(h%y*m4MtbisQDovzLE=iZ|m$GWKlp@>eyrsUFQIL7njF@L61= z7KMDi(|X_Qj4$kp@>z^{%miBM@c9v%-Yv0XY^mkr2MuKcEz*z)sQL4}x##l}tuIX` z_A~1ITP(4gh1f4B6=D=q5zDM2#QuOGAx0U*?gFtpLR>AhQcIn!gDi^c4re;uQ7MT#E3}R1%*oqL>)>^4vXC0A6ajkIX*K-c8ZJ_Br8^iUS z#pTYgz{Z--FTUi>doGz4U-9NYYiT_rw8HnZQA|bac-RH4BasO$%AmDzwn4ScstvNL zG^<)?RY}&|E#oVyyiK#-TftYRzI-^WZPwl-+#su0GJX{-#lCsmt#y`<-0}}R{1Oze zAk}Zy^aar;qgQ{^Z2Se$y2QTlYm+R484qQdLljd{;hU#mXaX{!LK#%5K&2w9%Cc(n ztlBI@!Z%WZnEndcpFAoo4|hhCX&hwYZ?18WiNBfVK`6oB_iQ17Ood?ygkq{du7m{y zaxpRqgfarz8i9COwPjY-W>rlX$W^HII>yG<%Zo+6ZLJ;Jnu0?ce+S=n=+y6+ zH?+FM4sE>V;98HGpo91)lOj$ zkDw|VL{A%pJ3qT8#;{Xf47*AUkD3@Lri$TZ9m5K79WhWw4E+&9zpUz;ReNUD?pf74 zjN}z4cmuQE=kDUu&j#c7g|EDf;^MQXjz;c7?QUmiZyin(i%;}T)~}&Ie_-C+)FpOq z4iFxzpe$obF%^$bU;!BTzAKrVl)+;dcnry^{jzG`tlB4p@hNJ-%2{@XSQ75A?x#V> zva_$V?ChgSIFs}563AyTEP+r=6-W#GIWGd?%bg?;$_V6e1afFr9h_AMX4L^%wSO2( zODK3pX1!KHIC54w)Q0093}4N_9;oAyfjz(u?EX5OH5%9w^yeR$H?X?I4(t)aV?8Jf z4~nUHYz_msSK^Z)b1CL{}YD`ugomHbk7<`ozSUCfGj3wa?>=+F~2KH!YU`J^Z z&cGfoft10p1VS-YAbf!n0@*_R#|~u#awY=#M^>GlRi|dv_^cY2RVRkw$jh0|%6h*A z2kkyQL;k}?5w*QDTdJoyr z^B>Ub2fu9IkK(4kY(}s5?m>V4ioBuIC3fhZ6dpd5g$Kn{JovI8V0ZwT3>{_gcnLgS z$g1bE>Y1#1Dul5DwP5937QA3dxC8i{9YFsXXCZw`lWMEW68(H+u%PKg@b(Al2eKTtxPI?2H-s&vAsA&Ly z=gRY@1>gq_+1g*}5O~#z+T8bilg8f60$TpFNN=IeU!4t~MS4RRy^T^~L@^a3z6l6u zK0qdeO&N?n1f%z}>fI0!-wg!4FLm}6vM8YUb!>7c{Syb!H_-Gxjsg0_0&-_aU_&k^ z-c8{19c_J*%;$U5`5#+89|@lyP%3;VrsA_+D~Y=Zned?uK7WDFpIP;LR{fe)KZlfB zYwb2VD@7Ki^e3V+(;8OTa&8&vCBRZ^?gtu?ppYP4!r zXSK+pyjs^XO8t=Ah7PYfXnGsOcx`BTxw9&;A-GCv#AwV~)TrX?Me9 zTpdv7Z(wn)FStCE3NDJNaP0yMz_mRx!9^LkDuJuKR<*BH?P}GgA+cSx_HH`sg)B;} z98sAWR_ze$4NY&0+UOU!YD>%y8p;f7udxfVb`G*l6Oi?x;p${$yQ9wE!Xm2@WP6}g zkWoy9Y!EB}SwCcgj53hb1KC!!sza@+3wiCQRR`;A2(l=zt#qieZgp~a4TYw+O^jD3 z%gdc%fepdc!NFCRfNL1-c1p(echvdYSX>IuM!Qq6}Q!forE) zwL`7yTC27TiSe~y&^}scqmf04?S!bz4BOcuHWr#*&)VoMy`3#FKWHd3YzK{9kacyC zZI^)TSQ_3r8QF2D^LtukJp|eDC>3NBQz4rU3xIGIGC@We$Qpobk6P8IR`m*b@kL!w zovE{PkVSdzp+l7!*3aQJ3!2_uwYcl8FC9kk(xIQjD`+T;`Z$bwB{2FYjrB`rG#hpP zUY1c`VRSA^g%QP6j4p=-1b!hhVMG~>27}R{TGd#q28N90Yt<`sb|tbXqd^X%VGg6K zpy>^*#ZMd#qhSuCprJ5obQldxV01N&4NGQp4eI=%meCMlbS+AS5ye!Dd{_XZTagJP z%3yQ?7#&xuj;U2+YSqyprhBzEUkZjs_alp9Iu22pLvNgeX*o2#lWL=v;o}@kK|?w8 zj?t_I*%$}e(Fw>Npy6@J$R0$Uf09LZq9A(+rGkuNDrC>W0;1P1M8ghcAUhMt{!yz= zuT`gpyq?#pFX-$=WKmxK(4oqqmveZ%1WoU(7_Xe=oJ}iI|-g*$A zQE0Ofn3-f3IM6j z8VBDW(Dbg3;k(A-bLU)OL+D-R5S!=hUy?xYPxf(5GCjT+&A-~xyGrQ&g;JqMF%`Wg z-aED!^cK~sg(0^>?;Tr&c+9lB+2JPd9lNPEdT;M$%gqlO%CuXk;S*f=UL$$g*v-jM zRp?x&u&d3yEy0l{)CmLl&J$w>dLunL}hN zXnJ?Wh%B>2+?f>EhydA|?UyA3;ak!CyDX491qk1UCbNWMDj+++0)X)KXaa;XfIJ8w z%WKtrA(I`o9$z^I^=`v1vM7-!oLTaWLu7Ag zdQaElj;p?OI*^x_&p1SahLNe!pN*bLrZ50?{?nGiQ$m4nI}-{NQ&Bh?77*FN$b&bEs^9bap+v{GjY)JAQ$=?gEFe0*5lo_^jOe~Zbf4F%Pixi3VQ8nL3SsNe4rgee z+tA#D`coZ*oE|>5`@zo{Uy0`vU`#xxn9B3%umH~|io@8U49|ao=Reh|A8OTiwd$MD z`5CB}KhdH)A^$;F-H@|_(5J1*bY!h~_j`-_}kCB|9kQ(~l;D#rP+fY2_I(6B=p zF&5Y1Z&z#8pS9}uFu*HNh2Wjh`O60Aj?SNUMEu|FelR+jI(B#^jEUzIQ+a+DEWpss z;xKk7!}HegyrfR8Tc=vqnVW3OwCdeDy9Zfx1u3bsXWsSe>`h4@nqFyLbV{yYXKzXd z4P{MT7e;WWPUd7wyC0r~@1?Qz`JbWY-`l5&^&}p zjy=j?v>6y}Ql~Zw0jFkuDt{38EAT&#{jjrfZSOT*bqJ&CGdHc zw%RB2c@A~{=9W)8;qyF7g%8D4d|rnI@Oc@T@SzMob>Ne&Q`L2w`t5vX7mo~{0^4Umcr;=lnNt? zsTh3)3t;pyGGRm+jJ5@%PIand21CaQ$bm8J%Lh$OrTH(lwAO&XPxR^ zr*^7SJA`OjYwb2VD@7JX(-Tpdxzo!*vjH@{-Rh!em0k`S(~xJC?g3x^we3!Ia+hD; z>u!q^&MW$7R;)YyF~l3QyI#p4H$k1hn+3V6fZPG=?#cc9B3&9i<$Zn*cq8Xqzs570C9Mo8dj%<)T#YKjy<$?Po3?I zEXr{>f;F@8K!@Y5(DX*eI38#@`lcag<1kCiA7Vl7XNwbNqjQyGevj(IP7h4RxjX9o zkrw9xf^!d)3QmftaPA8Wz_}MP!ATi7j{?pk>(t?O>d=toAg#Ke&ITikvOF?~mveHA z!*VDzz0on2V=PN|P8u7WlZRWBhpsKk{n_W3WRxRN=a051j~0{%pj1#&Tw9dK);AWb z#^SArPyycq^$qI&dUbETx~E<(s}HWtw)O9?=UUa3Nl|sTC+ea8H@4|al12Kv$b&51 zZb*xIsqPAE57qn2>K9F!!r#KDlor*Lm&=UtAF4;I?oZZpz*=v)e8!X?N{ez+aY`9L zbL~XQJG%Yy$*o!x<)*W|zf^?%3~5=9) zzNj9>jm10A;~iz}Z!Rh->P4q0;f0*NPYzmftz{Yhup4FCdt7TyDII{tw;TL@v_8^f z7}KK?)6@S&OzYI6^^lg0#of`(I}QbrJrY-=%=I`wGHes+#RZ7kje zg9loT#k&fmoAMx8T6#jrmsLFgfOJka4s16;8Ft-R+)HLEXG)rx+OM&AcaC8{0D2WO z_2qi?V!e94UOj7O>fZj#k(v4iqv_8!GPQ!4`Y)CaM6gob2x}|r{b!SA>Pn%#x(V8a zW-9u@Ohs$X)P2#-s(SxLXS#-yXO(pG=6}@tBHOJ zO&%Q%TC<S|t5gC`EGDWz%wo~LUEM~duF=>%q zgN(y2GLSTM#809fRiBRL>*hiz_UBYU_3mc(a@seJxk`~0=>nKFDn2|l0DQ5_fh`~%9pW8oqG1I(h_ z9Jna1!>x0({s|rVLU?h}KMwoXa{t@X0lh`L$2jrzM_3SFDXy)rW65_MMjYAk$b>It z__}AO2DN)9)w`47dos%X-krk7cmuw@I%&Qak?-!E3}3AXhw(?5mTyBRb~PTB#Ak|Y z>+|17HWnY$SbQLTJqUiDFcLp$j#S5t4E#LUKV~GC_iiVTgvKFMJ2WVQ??0B}KS3Ee ztZt}`ZW(l*nD7EpaSmK3pbM4$xrIPdj1k+zSN7`U4zhNByc zkD_x&BZgBE!*~^pavX?8hwya^+NT7WlbTNt#t`Ba(c zs9(4CADt9ZCi#8a!af@N4MH@C|+8xkX++i@me0*JTQG@yrX)ymh zp8`h@Ue~nl1pjf8Lek?ClmpUM(y0~-3{g_I9i`hZq}$JIx7+v>(5=(qm%77F(xDbo zbl6!s{9Zcz7ODCgNf7LIK1(<)gPb$+FGk+WryAmJ(Yj5wENVLCZm~?+$s2br>hS}V zz@&?~sD%_R?jkP!3|kHAN2GywyZRL1gUO}yjFH-Cw%dEx zwJ;JMTAf@MxYJU*Gg#cwLJD{OF7C7vch<4)4EHH;X2o)ir%ib?!&agl+g}{hLJG$Y z7RTC%W9wPR4#5efv3Ru4BDmLm6Lv=$$ZR zogSM}qdwF-QT#Oq%jiR6@kvA0sTaM*;&DS-_7F$w#TQ=Gj`tZNG@bApi%${u!lKYw zGHD4uL)f>6;Re+XX)s66^f(;L(OFTh4d*E9AZ?%z5|;NULlF>76bH1BV(@ck<7^~O zRKgyf*F_pQk(-JtoQZj6!PC03;W!d)#N&&0qs0%oYe(soPF6i`#0EZPztGW_7!@`7@R|i^>o!a zlscn`&b(@z(FJLodEGeE6*e2xc1VpgZ=njEd_tdgM7f-Bd}?qYGiFcD*1NCEZx3;3 z+e4QoJ~Mvmf;4`9WBlw6n|O#Csqyn$I!O1O>BjolbnAg4I`f@zMi-=U=4a!~F0hFo zV2~PTey20Lp}=P;#?9n1?^-j>4aL7UEzHsTN7#bR&_Z;&;$IuzDaq)zQXU@pf1<5X zGC7;KY@HD+8{(hL>|8PawPacQ)_Owkiq44RFPM;}Ko_LJ(E^raDd+>6c-tvbgQFFy zygg9hvlJs@a=KF7no~+}1V|v_yp}5oTd^q$MUSELUmM?)!UnL=hOR-K`OcVIFK)wa zMLujsKK$1v_@`IXdJ6({5-9|7W?Dm4q2GxMnu-h0_ z#8e$W^-u}(L>7b=dNlh59&KVg(gkTe+T3_FKs?&p@u+>^(Qfh8ol2l3i+kYFz`&z2 z*HBb&PI<;JU697Fj>fMM;@5DbY8VpZ+%~AMAIbiF*1?Hx z2U3!YrcT)L4uWXv%%P!JL4BXL(8wsPYc#f{1}lBGhlZ*68!Cph=pkL!OIHZAGYX9< zeGBpcv?7A-sLtCHx*!dL9biHZt3zS4K^=_LM8Bi%q`S^~AoE6{n&+>gt!7NQuGFWt z<9*M#%EP6dXH4zg8(UG2!=Ou_cSa^Y>w+{s_ks!Wc{FS`sH2b?pL^?0_R!g$$h_lF zt$m(`TYEmWG2hKer6I2JP-*9Bd-m#$t*FNs=+fuD$i!z|kjCeMFd;sl2%Gp{=8zhn z_tBjU(%F8|kWxL{uBj50(1V2E;Dd=<^|Ql^?;`Ty0N)E`2@}nfR;=()fHN zOo-1@V6#C@LaNR}VjLffdY=V6E?JAbR2G@M(hV|gG}5!7M)!^}?&*Rw?ww%Vn+}_J zsVq|C*@>v~Sl}~(TV3VMUxqybJSnL<)7n(?j(lG0mSHt-%;!~?gw?#;o>$#AtUe{F zx+bhX71g2BaJM+4xy?Wv6nn}vFhp6j1M+ViV5mEa`L zY(8~^{Q*X3p}o8aRrK+Xz%ekH2z&-{96E<_^+~&s;iM0|E{EeEWqgTaP8$&Mf)dTkRxTSd$X*^^-!UI zR~i3wK^p&V)Rq<@lWP*nxIK3xdcgm5htxQ_SSv0;=G}yHu6Q+F_^q95%S|l48O1*9 zSZYp>x1h$SAq2tzi)y>w21)m}6gyI=FRd4|0@iLthTp_Q58`d2?kz#BV;;}7^|+M{ z>Ti)$_C-mSy|(D9+fvp@T(@H<;zo71+gaH|RO)3PUEP5qiK8oqpm;|ljP6dBG6u2S z4whMZ7fNw2Q1>ooocl21|vu?(e#aW*c zr!(fNy-g8Zpl)Mp@l$wpx0j#`M>~-$AG5f=wy4JoEUOP{w)N`w*T1~==b{(bmfxTF zUBjmzGp5MjRNY+5r)~a5Q@GN%rtrLxa1gs|dn=aMx5sZs#J)W^ypI0xh83i0C6iZ~ zyo@A(v4fCWF5Ty@Zik6;Co1vV0Wq< zh@^YL>91h1L4AQ#ea7SyCLbXQobH|H^fFYsPP2t^nho=u{u+hot&cdZg%nOVG#2C6 zx5nZIIQCE+Xx(KQI4~(lnnEZw$aC%^#({a*lVVq{eJf~a0IC|ShoYq1Lr}vZRp&E<# zgVUwrbZa_Y!em`0Es+FH56*M?9ysQbW((sq8|FE^J__OV5OG=yDV!eOSUilRhr{W1 zu!#TJ3#rCI7y-bRSiT1eqE9)1}~r}^+p4J7IM3;OV@|V$aheVDoX(;Uy&WP>YaxZxN8nK#I(-D3?g)zwYHOs* zW3nZaS|owfN9H+wU(9K?Fix{!p3~c)5WS5Or?rs6=`r$j4t^(v)7!%$-ieGeh&8bgT)55FH*G+lL1WjMiMxE zW}edz#++sg<1`!QIXxJK=uQ80tc4U#=O*E&4qPJVkkNUO5x{U*Z&1UKsv$@Mw{ugV z=5-A&^Lp_zk1FElq)mKkT0eQ^%^#+_I#+r7Lxa8WS81WG3(`0~114Z;Ix=ybG8{hy zJv69;kgAbPMj$cXp97VM_a49NE$272+|tbu44dInRW4WAIv9WfL!si+QZ%|*u;)g1 zC^YEPKT$5x>4G%ToevYRbS^T9jxwSfgB}{x(MZ)OCPy$i42cPG4)kR3mh0=<>u_D` zQ_IXHD%&W6>)5dRWgMq+p5x~67fTo`5MR zY8l6=oaguzD5T@z^C`L@jpKJ}$8R@|Q-fAWZ~(C<>Nd6vwec84;{P4-IN1QuQj6 zmzlhX#6%!ZOdW!P*cjAE1XMQ>uvK0J|3)GE4WFda1!*E!r6X8rBA|>2-a`)!>K&x& zEhej(ypF^~z$dVpy;5UabEU@CK|lj|D>Kv5r&SbX7!H8F* zT*gcnq>1=ln1CfdCnmFwG9vy0Jv6A#kg89Ze8l7fBqrkbpeI~{F}pE1Zsd__pKZ*T zv8mao1shs$HTNY7>BIXlDbeVHG|_wl6R`B51c4pOh~_8s(4c-ms=j0L4U?~sm}owQ zUQ#sr7-Aa}0h^kATF8s$XB5(h@Oe31kR}@b{S_>IVWQE0kL49DWHkRlKk5%AzcKj* ziHYW$CZcIC#}nI_2-wu@(?VV}#psJZd<&B@Ho729G(YKR^xu-fBxQ_EYl)@=salsw zOC}j4CK^7dmozqdbzmD40h^kATF8s04GI~}FD4pYkR}>FwFgVTNf6kfjA%AR4-IN# zq^d2G4VaW7G12@7dQC^eHYNf#HT$%X7tLlUqz~cKf4U$|G<^CGmWq+dDxjYR^eWK< z9?wRq+B0c~#01h3y51Hj@L2^%xj>b+HjfLf!|H0c8Y;QJHbnUN7e1>ePYFhThoMPY z!&apK=EkQ3@&iX$=l=e~Uw>s{(>n`^>!v(E82S27k6>BW*?j#raN1pGtDsFTrO0IV z>w+|d+iFW2AQQrrF<(6N(4e+Ns%n|kATfkDf{M2_3Vc?P2?%c*65g2A^|9*G^$0Fk z^o<7H#%)@nAF~X{pwx`jW@5?xF^s*kLu_Uc=%WlmSeG~m3?MoP?P%Q{gxFmSiAn~L z!JtQZqE1FA-xwckbVq0_G~o#GsYV$gU65vkDz&9@WHLgOF+!cuLxb8Dsp`a}BN8)0 zRZ#J|pulGpfnkK&h9ksh9=)!y>QWg6`?M;be)P6?m0&0TK&ho#o3L&Tz42h(9pvp`n}fU+G8trDkY=MVIuE+g`WhXp z3RDc*F0BAu_;%>x;1o_PlvjbWM|msB;li>GD&nnnn}XvNnxoQGMOZlF-aQG z1O8|qsp`X|7ZNi`3lPTVa6TJ{m_=989wK$3(}0{aBXQAG8s+E7|oIBp+Sv6s)jQehQy5K{!sA_LV?dJ z#t<1zJ~`|i9IK9xCZ8ep4sn%WCx0~gjB#`{X;`q?lQO-O(G2Tcq~X;oLx_&1Jh~hi zO?m|DGMf4N@*J}}w>Jx>yB z3K_^GWD5E$TaB5#dvdpu$2jfjq?JT zk3t4A{r_-x9sp7m%Nm|pP(c9^5y1okq9}M36N00FiUAarU=Aoj44?#aSVa+Y&N-kM zFsC)=oUb`&y=J|}YkF1x>?s!ZuhS0Od*1B&-d(Ex>eKyoo$5Yk&dkorKbS~Sn3sth zU+n2v`3DnGUnVj`Mi|)ha{1ZwQvGqU{_&XS)!uhkz{>yNACM=}xp_tIJ-F6H zZWK``a=QG3i4=u-nTUQaUwS%I{=r1lmx)x#2=X^F1KqoROkX;zT}?UWVj549U0GbJ0QYzYt|$&(Gy& z&rjt?HS`kQz7nTOmFZJwc9t(un%P+%&@I{RYfADm?H0&NSmd*e=iEo z^)hH~y{vLso2xq8?^+zbkbZeru1b%WBbzTQo*drMI$U7kVuzjN7XZH1F1sm?z5$b8 zLwV-x4xcdUvNp!<{+%|LPsms4y!2bRdjD8dI-6otRXS7cuL(X%j^9@3UfsM)mCjed zil3$bve-#iUjD(FP+!i)|0FuF=dbcJsh#c;s8T@~@ZhKu zl25R+OEZz`Vlw2C_ORXeMSgW1;jh8^v+dX}9Q!eff!_x$9mkLjfy%wO%Smfk^SE+_vl z|FMo%*Nzsb?r4o*N4W~GqcydoX4M_7mEKWnM$%h5XkOjH+UXrsR?mn|sgHKFV0A}* zLmlOsxw%uuD3?QW7|}rOsC9Km8-+S5=9uPYW9?{>>W(%Eb<__h zi*~fBcGRZ2qd}pLa>bt5)COxui&l5ES*W8;K2BSb}Y7kbg| zrWfmVkW<>!POf{PnaLH4%X#p26HRmhf@}uVb1zbSXT%dqU zfSSz;*u>RrUch#&=7I%msA?`$z?P_Hivl(^HCq<2Eveb6fQ?1Xg$vjk)NEbAB3E;f z0+y+oZ3FWIpPnjqpEHzCj>cQg^2_Ynw{+GVhjhmwRXUV(Q>FdMzw&-` zv61|~vD~cpSzf&2L}8WsE0oo@zl$Xk?IYa{?Acp>_FPkctgb(L>5oO&C== zo=gt6oJa+Jv$OieS}QrGN&)rT$>p~;#zUDO!7vYA966s zSyl4J91?O6(yN5n<+=%ngv={p(|=S69)Ijg9>n<}bN<2qh~F!c>5*6BW}F{#*%Zm< z91=25@{qJ7{9C5+2d|0x>+CVNyRA4s-8dv!0gv={p&$6n7y*NMQV3M<{guOW=q)OWS-=s>XhWz?|UB2`5~80lBaP<$UMo%lvR?a zbAHHPlChO(C40*)b|oCkAt8H^nJ>5FI3#3V3CGu|5@NsGasuav>?Ju^39%th78~+H4hh+V%zU|B#33Q`O1QXAl@NQmUBdYxdr1yfLTt!OIV5BcGV@Bf zj6*`^m2i2TDk1jsv@1A20b4bV@ zWagD{1BZmnE8)hns)U<3KV&b-RteZQGWadCn>i%pAY@kMdJBhy>_G<0_2{62?WoH9arq%!F+^6Lgq<+G%d-&O5Ql~ea>T?AF`KZ zgY=Rd8}e}u3E6|pyj-8)kdS#LJXxno&_ClH^P?|Mael~NlC2WF7dWvYpXQK|J;-1s z+!%RHJ;Na(^GbNOPL&Y*p~rKaAF`L^U?s$ce4ax>_8>E_gcmp@WL^m`)~OO=e~9QM z&JVe4lKgKD37IGP-d%=zC=;}2d_Vt)wg9nKGVo{J=QlHcW!ka?2dt5cF=UsK-a{E*8g z$sce?$UMm()+x!cuPGmKe#l;ugUc;8hf`?B(_u=ZEYi zIamp?AwTDkkUhxEE8#yJ5;CuZFX~hYv6tJIoFDQ$Ct3g0bRLqhf-gKH}Gd+~pANXUFm{iR2E{8p}BCB)vi{^tCU zgOFY&#D>hxl$7B!t#f>{I%E$rSP8M;%g%F1$h;CN^azjNDgg%BxMC-{3Fn6#g!H~4 zA@&_tQw|B4CwacIO7i@iA9C3wc>xXyISAPzqwkt%#vvi|N@!kIm9QY^ha60DR?BT6 z4hcC3nN=mU;E<4mkoYta*se<#ilIhbUxNMhgTEXyGw^CWk!Q<7tUj=Bryhg>#E?#dw{^CT}#EUX?>a4nlh68atD{I3(mCWLD+68i$0; z%XM`3CFWX`{48b4}7-(m8KB=*L;7UzfTCD|aeDw5tD5^@kSt4yxV zAt47Lv&v*24hfl;YhOJg$e&e`*Wvt-gOFa5W3Q`LB(Lqg_B-tr$M*}JC1=HH6*Lk=c6E6AZ7 z5^@mIyU&T8$zdE4auCwHy2XYZ&LJW5avh;Z1o^!r$KH6i=KPR@kY18wLvF(%A@d|} z`;U_BEw|Vgj_o)<LCCBsVHXYwIS83mC5+^dka;ESTBk~gz47kG`5_0BoK?Aw;*gMokXe=MXbuTE z2$@y6j^U7ydAW|&BZB;1CB!b*-8nzxAY@jRFpfh)4nk&C343rz$h;Ev{704GB{}wO z`CgnKaxlqWxyF7nwl{}_9E8lO62@~#$U(@geoJBkhlI?_bss$<$nTYF?2T(*&JQ^V znN_(?)kdS$~PSGQR{8^Rjew-h25HhQB-Je534nk&C zt_N^P$h;B`tWzb#zRn)R`5_0BoK+6L42$fG$VtqfInV0J+dPI=l+qh!i7M{xa zAqOG7a*Yjn8i#}&gv=_Fr*lZiK}c^+#m?jz91?O6GOIOpCWnN~*VI{hM36tLN;sSI zLk>cEYby55z&RWeau71Bay^$rLJmS^Rj%i8NXWcg&(|Y@{9d`net~cS=Z74G^eQ3t zbK?s+BxIiCi|Ul**c<^#RV7q$NXR_NchxD$u`gkFbAHHWljM6iBxIiCd+U_s*c8?037IGPfjT8Q_8sqooF8&9$yr_99^#OYgOJ{y7JK7;m_tJ5mGDSeRl=j3 zA966sSyjSg91?O6GOJ2>oI^qmLS}WJ^8|;4%**vjJtD~O-RH#KxSrztkb{s}mFv?S z5^@mIE7#aJGtY2H$h;DsEvrg+j`KqfCONB0c%DN-4nk&C2`_L+$U(@gHm(;rBxGK$ zFX<6M{;W2xe{+7wLCCDi^<@qTISA>MYwQ;YuW(4nyb@k5t4er{^Ft0MIjc%|okKzn zLS|J7Z*WM+LCCB&t~WU(WL~as=@CJGZ{v#n0_Sbc4><^#Rk^;yAt47Ly>gBHReSGp zNXS9RtjhI04hfl;>-%~{kl!oU*tfMGaDK=^$gIlsLkgx6rhlCu2^!Bva8}H8?5;CuZU&^Wye&zg-gGtV+ z5`N>5kb{s}Rl@%`B;+7uR`)r-b4bX%T>sD`g8bfnPV9~APtFfH2$@y6{>3372O+(3 zjeRroH;07GDS5poNnV0K)dPI;vtBq@Z&JQ^VnN_(iz#$4p?O(V!h)P1 zaxlqRRl-6X5^@kSt4e6WAt47Lv)Z^?a!AO$TwCc8LH?{Zu7x>2NzSSgI&nzILCCBsVOb6dIS856#?_faLgwY#MUM#bdzY}- z%dIQtha80T$~E?Nb~z3SIS83mC3NGEka;C6U#Cil{YZHQ&JQ`5aY)EP$gJ)d zdvi$0K}fG$W3Q>TIV9vDWL6tj9}Wqbuc^LzM3BGj@M#04RP~bgfu|qYWw`ura4-2W zsM}UE^0|BQCUIq}cDY`hlCu2%qo+ca!AO$5(fRFO7M~#yAlR-e#m8$U3|(AtCdHzm*;ly+f! z{M&JU$Yqn{?KvdmAf&h4VrOy(4hfl8!j5HC2|ICq$iXCMwcK{*kdT9rSyjR=91?O6 zGOGuPBRM2wUaq_95kY?MJ|XtiVK>eXISA>MYi!6-91?O6GOKbO%^@N4N*GgCl`xj` zLk=c6t4i3NLqZNhW>pE}I3(mCWL6v39vl)fFV{Wwh#-Gf8`oZ(A94`VE7#aJGkbGL z$U(@gGC7_@LJmS^mB|Sl5^@mITlleGD(=G}A@eo0uO1QP_bMTFxlZK#kU9UPI`PMT zo-mp7L!Rd($A+B3AtCc5?^mZJ$1alnIX~oiPI7F>12`mPp5z0|D#-_Ne#pTjd)r;? zBp=KnAqOF|+S3lyUd^EGw29uefvD#?|cA94`VE7#ap zha)&7d%N zi9IDP>g&r*eMC!6au@38!&L$UMoXmsOI_;QWxwCdp@VNXS7* zZ@I<3tv!oFLgtllc3D-zIh-GIFv;F>i=E_iIV5DB(!^$iXCMbqT(JLqZNh zdX*6S>UJTAgv=}9qOz)li#b2!V3M<{giAOiHU&^>`dOtAt8H^ng5c06^De(%k?fj!sEw& zrN95~RYL6Lb~opT9E9{LA@c_rLeR+Vr+=ZEYiIrDOTfI~tK zLS|L24{}Jz9%Sa_`VfbN%**v*J;LL+O6cl*J4);qIFE3C$R1=TWlQ@Cm$s3=!sSs8 z37IGPv9e0?(A$v&I#gc%4H+=9Tb9 zohl*ra(k2WLoS;nzr`UT^CZ7rrzFR&ptO-ka;D1TBk~gy{CP~`5}8r z4pu^J$j><>WDhd)O85_lgv=}9i#k<8?B(_)=ZEYiIamp?A;02~kUhv?CB%MN@im8p z%q!uWI#ojK<@PP-hdj?oj=k}I#~~r}B!6F4N&bQJL!Rd($9^*WUk(YGC;7)ZB{}v( zzn?fiWG~712!TF+Z|}TE@Kxle5I=KB$Q~rv(%vJ;MSlGI3x|ZvE8*9&s)XM-KV&b- z!3#(1<@P@g37IGP_p(azADkbum*n7Eia$qQZhvw}$U#W&&Dm2UFSoxqBxGI*f2UP~ zCE4ST{Z}D!*T}oD*q{32uXgn5D}Rb3*Bx>&$vJ1^jSZRSkdQsd%CTdAZKVAt47Lvntp5IV5CW2@BMz5@J82ZpQf`dr1y1x7d))IV5Bc zGI*a5`)%R{IV5CW2@91~CA8rDki8^lUI{HZBxDaVSP8LT1-Igmka;C6TvnCPn)5?0 zn|0%#%_pwGr1_|hwLTUF2Pw{-P&?U$UMo5S(0(1S^PtB`sd%e zb(0_W%HNI4RbD55EKZ{~o!U9a!Oc71&&)YTr|doGy!z;>$mgvcPYL9*Id6+|NXQ7!3w~4$B3pSPvb&YRU;SLYRG?7CZ;^F#I)$5P41f4%P|JU{X_vkZrX%#+-)PDzga zc10)757|p{uo7ZJF3TYydytt|LT3&MnO8!WI#ojK<<^z+L-vv!tc2K*%W+7^9%SZ~ z(2YYv=9RE~ohl*rQ>PU;KV&b-!Agh?*_}f|_8>E_gcUg?WL^m?)u|Fg-s{E*8g$*XWk$UMobrX@M^mDr2(L+1RerSWIJ-L1~~A(u^& ztid56^CYiXrzFRIe!Ujwhg>#E?#&?~^CYjGmgJO&JN5H&ybtGx>?PSCYrp=kAIQEO z5;9NnI%SpQ0_TT3&q;nR@`nl5<&cnhlGiJ%B=_U|kmotcH%3l!e+~(mCwYJ+Is9NO z?>}$RgPZ=tN5i$hc?LsQAH8nml&sHF0y%izYCi+7pB-oe4hh+VOnJ~)guEbfCO71e zka=+pZ0yCg5l;zZ@4VUFWbFsU#q$>Xb=}4s60!$r*Wj#Hz$P3LGB2)8=cTw7s`WU# zl%1<9JvvuUJJ%qd63Fv>-eO;I26ITr9;B^++E;?&3W)updovCRnHSgQR$SywE#t3U z5B0Nxhj4z#NOB3+?geQL|I=%C?LDhLuiablc|#5sm-mfZv5RX<4hfkT*H(2ZuGml6 zhjM<%jk&mn@p(foo8lVIAtCeP8ezp%!luxWE{j|9lt2!ix7zzx{p{G=a7f4=q}|Ya zm&MpO^xJYs$R4C!`?A_zx8snI`3l%xj{tuoT>(4rlt3l>zNmKM zkdT9r-Y?R{Uimw7NXQ;!<|}^}4hfmB{E>P@sVkr%UHf+BDS;e3Z{D>p_6_B391^kz znfWpu#UUYkkeRQ5(Hs&oUjbwEh*DQTL%Ifxy*MOf4>I%pb#D#{nQtcJ^@vi7t0C>L z6L?A>mpbo;w5ays^M+hD^|~*Igv{%8;=I&rL%R4);wgb#YP~k3c~9o^hV0cV9@*%X z$$L{T_IEQ(;gFC$NV^DlPr+h8zu%8TLgtHVe?6ix7uNwiC6F8Qybt8_hV0dA=8Nhe z4hh+V3@)m}B7auoU=9hHFRDZIh{jx8hw_v_Zp`yOjL#dgSFf2bs>3-XWDhd9sP>4w zs46)mWWK15&?6diaUIE10=Y5Idn%tdWUpQ`UsOkNNXQ;!a8XT;yr_=mkdXPJnx;oI z=Hfbrrv$Qh-ZC$)=^PR=KX1o2_VacePYL9*Id8{vNXQ;!a8ro=n(zb;37HqyiH*Iu zPU0zn?47sFH-(cqBxDaVSX{AR8=b--A@kxowXql1X*?y6z4MlNah=W~A$yR);)?wm z;S3H5nHSfYjlHue4Q*@FxgSL}P`b2ubqUR>uk_ToB^rvx(2TO<7p z;`w~ukV~C6e}A-X`mYnFtk9ZozCRrKE1)jm^M*Xn>ooR7;6e@wnXl7}^oUZ=TSI!k z>|&l0$c=g4m+*N*E_L1wX`Nom=M8zD*J17-eGGC{c>k*}%w}!M%uizTzB!5KyJ+QzMIb*vRAKm5%3mO?0eLEI3#2bGV?`s zFNcK87u9`wL}MFwtJlmI)q@-ovIm*@qI!r!LiQjnlUeF zGGFa63C5t-kC=n2YN_JSC7D^Sr;{^M>rzYvzmUOAZOygA6XJ*dIClibF!?i|T7V zqA?fOH#{Yfc}l)*>?!$Mwr$ z&LJTOA#v%Mo1-X$iefLRdM~zAt47LvnsCKwQ`@0 z547~3)_+FlT%W#IiO?Og2buZyn&*&^`3k7eBfww6hjkj#TN6!qN+6dy?}qgLbW=WW z$X>nTO%AOCd<2l}*jGmW_Qd%(BxGK%^Osw_t{6Eb3-FXcE~k2pJ@00G-jK_tUYm1B z$h=+`EVp`HJ#xJ+#8U#foa#09yj$>jLoS>eBO|~dd>XZg2g!`WL~fB8+*NW;33K5xinQ?E;MNXQ;!=2xnvI3#4g zsFv0vN-eI2bP-sFrv!4T^KM8NfsTCMka;O|YV4)3EKdpK##{=W`Me>Q&DPb0Lqg{D z+O@IQ>vB9LkQ;NocH{Gg9IRLGNp|elTg!7u$h=-xXzcacou>qHW3JZ~`Meou$2 zGg*m4LJmS^wWxY`R~*PYL8wOQ9hxfz|lDA(uMuhO`7$=ktb)d8d8Xa#q*VH8><>zE0QFBT7AQ z4e3&~7EcM};Cb_Y(?0h15BBDekb{s*Ip5+H8**(937HpHpT=HXeR)bCH|9mP4xcyV zQs>=}E`9|*Z^)(2yCGft*5&ht?CnqX>2UAO=GY&+UXMdU=KE7WJ)+d}){riK{dr0t zH|BW{;PZxD>bx7${2xxzu?#q|Ia#K5xjS&buLPCY$nkL-y8b=9|eN4hfmB)4_T~spqXB zt<%kTN+6dy?}oHaH|O()Tdm7qI3#4gPPfz}NB0N6Q4KaQs>=}R_o4u-jKc3+9X-6i_z7Zucy_z z3rB^_SL;YUqSUk3kXGxiJSC7zop(c8t-JAgLoRjR4QaKG;`4@F>bz^;662d)ns=Cf zWS2qcj69MLUZ{&l$G%XH=JSTkm;M+%qSTZ$q@_QWrv!4T^KM8>e|J7_$feG^AuauJ zeBO{toj0C^&+)ZAy7d3)A5p9Qg1_d*5&QcH_Tck|jCs$?E>%A-C-&s1kohjPmmX2- z*=tC<)ZRQLkV~C+L)xXr^Laxqb>0nWmzu!m4Y|~LH>6!^A3kr$m^ay_{-0h(?aNUi z^IdA99#QJqYe>7)B%Tt;rOvw{?NXEZydjr5?}oHXP2ux~TTQI`4+Gi5|=64Vf?fgeosVS+?r62n*4xGYM z0=d+A*XPoYJ?~Tbydjr5@A_Q&vFCjnpEu-E=UtymKlZ#&=ktclm;M=gM5!sM&!r#x z!xCrmlt3uSb+xTn%Xxy@00#a;fufNSo+|eBO{top(dpL@(m= zhFt2r8`36vF`qYN%sXup&1!$TghN8+`_rX*M5*VkKKG~C_q~_#lt3~ATxizc?O4s%oo*_dPJ$kRiBG0_8sL_JSC7zop*gMs@U_M z$>$9@Sg%}C{AtCccb*&yzYH>BBMRgrd3FK1e-H;a5EIx0@!FsLz z>oxWBe);tr5^@kStCfEPhlCu2%xdM|$RQ!~m4A~SQR)h)&y^qhUhQU{63C^_yFOQb z?6;$C;q!*fOX1dXD}~s17`O41KrW|Jh`j`E=ktclOW}^jUJ7^elt3=0Qi#0-s`$Ji zW8P^`TC%zyxQjzV4nk&iKX5mPgv=M!J$gi`#Z{k|+Sr$zdwEJAmpbqIywt|tU+?4d zhV0dA=8uE!=a7&+$jl!HJ-{I$^F{Tb9#Lv>)#sv$U0e_Glt3JbhJ*@Mh{Q9a5bA@fD`m>yATan=$`TAeTDt`dn18=lv3&H)LK4|1P&ui2X|7 zWu6kq=lu$wH)LK4uQv8lc#Wq7a$_!q*ZI65W8UTP`0@=72{{Ov)#J-IIV5Dh zsNT{eN-eI2bg6xtrv!4T^KM9&+IRT8AqVRF5;CvXkIJoHW8cz$%u@onoa#09yg%XdhFt2r>+`o6V$b_iK5xi; z34B&=OCa{v^*K)oGm z4Y_RA=^q>tGGC{E>Jg=$xB6VCv0wT9#Zv;g)OpwEI*mQ=zxli&mpbqIT&J<;ox4s7 z8h?GP|Fr%yI_LWIy-I}ckjrMB<~bx}zD_Ijh#-I0T7P}D_=}?7T#?V+i*!`BYM0AZ z^_HAWpL*P~!}Ukin(7_dWw`vWYMmPP>S#5qv$UGkd2kQ;dvL|XcI@4R^Ft0ocFG8{ zDTjpYLE<}1w0dfPYfCYc$6OgVlk;&%$h;EfFRMyefb&E4l58Jm%c>HZaY)D>WUvw@ zMXrSA91=3GgazwV32#Q;6Bgq9ki8^ZC3qWGY{(WI5^@mIE7#bNEjc7)4>DM;u{W+( z91=1w*M;>6k3aKDXwCT{2O+bngheHXIT%uY^VGR0$tP-niOwe#l;u ztz5lIi2coxi*ZQE9%Qf*V($s?KwYWFUgr#LI(~B*@Miy5|-eQ zka;C6Syq*>6z7LrHc4KZLqg_BUZ$*)+>!G`E}JBG;*gL%$jtYIWjQ2dUJ0G+R0&(n zi2EwI3+IPC&qFgc$edlka;C^t5YS!z8PDd^F#KM99(X(Ay?p#kUhxE zE1^4wgv={p#X40&>}QNCael~UljI&85;9M6&$3GL%A6l^*(CX291^kz8Qc?Mzd&1s zLqg`2uxeRVLNCq_Ihf?G89mZpjYC2XLV7RNV{crmb4bV@Wad|gH8><>Uao8E5gxxS zH?IEfH$h=(p>JeqbzYgbz>_Or! zNPRETtAq<8zX~gGNXR_N>y}lL*W>(<=Q+ubL{4%)4hfkjxqn)cgBx$`*FFO{KV&b- znM1D6At47Lz2z4Bj&TDH3E6|peB<4aLqg`|I#7@B_=A-Y`;q=eoF8)8KyJ(-AqOF| zD%VXoBxDaV^K#vkLqg`|I!KT3_=Dvd`(|t~=Z74G^eQ1XJc7)a81R&1Z>6mAqOG7N{9_PltV)HAcK_< z`~Cf491=3GgyD6ngpDKLdynA!ki8^Zxq6il8**z73E6|pyb`wIkdS#LY-^Q(4`&xY zO{Mk~1&YksK1T2bp;# z?8+e_dytk%?}8KiImB)p5;8B>QF=s>zxMW9KYPMx&JWpx%)AoDa7f5J$z#hZ$-8rY z$Yqn{aU2q|2buYD+k-P*#<2Am@kdCE1o+R^@sShlK1wW?l&gb4bV@q-8Rz zjq4B&37MDcp?XA+KdVYOjPpY-8_2^sBxDaV2 z_L6MNEvs^!${`_pkeOG)Q5+Jo2WgqiYU4VZLqg`|I!%uV@_UsK`&HO6oF8)8Ku+h7 zkb{t3CB)9;u^bYz2N_&bKS$nOkK>S#dAT01M|k|U+_Eay6F5KQvVlC2Lqhf-gOw2b zI(rg_gv=}9!}_J*4v)Z^W;E<4cxn8J81o^#6i2X?RBF+!FY#=Y@kdT9rUM0kSfp7_jgzQ1u zFBsvmVO6i$U;Q|^`1mFEFBo0QAt47Lu>)iPc^QX<9E9|~HuAK{FSRb`kdXPpze11j z_-*6z7JlqIY z;QWxiBwM*=RS9=;NXS9Rtp31J6^DfEL1tdAcX3F_yj<_rBRqbqgs#pnlE&V+?&189 zJ;-2^W53~YFNcK8lYC!UCHa2N54miT`~Zi9>_J+&X0<0g$RQ!~N_eQOD&b+y57|p{ zaJk(W`SHsm91=25@}p&yh?5;gv^utOj#xQS=a7(jCA?5pmGC0xhwLRexZGl2 z-Cp95ka?2-T~3jIV5CW39pq^CA`l0AqSJ}J!*)334Vh^ zLiQkodqV7oPH%EZ$h;EXDyvF(oAX2Vl5EQ@t4er>LqZNhX7vK|T@DG^gUq~K-{X*w zdAYu?M|k{J30*UK==1^ShwMSxn>*fH60yI^^g|8_*@Miy5@CJ_8@IddAn=uPx*evAt8H^nV0M591=1w*Z=4d9=|0ytBvam&JWpx43=x` z&!K(EAt8H^nODMB91=3Ggs;o0629U5ki8^lUJ2iFNXQ;nOEy`5}9d!E%j#$Mq+N zgzQ0PUI~A3NXWbr{w}LZ$jy?v#24iDpVogy=Ukt@@*5qw?vTACXI=?;4hh+Vv^AC0 z##O-~A$yRSmunLa37MB`Q$51tw_G-AA@=*@3vfut zyb_w#sS;v;#I8B#hwLTU%GIlc*pLfyNXQ;!=9RDzhlI>4p+#9$LQBpM*-LWfmC%Yq zLiQkom2ha}ucKd>Lqg`2(7LQDVG+&`*-LWfmC%MmLJmS^^@iP|91^kznR&Uk<&cnh zxh|$hc>GogU7a`VV&5mUnV0J_dW6SsmEdh$v2SZTa(>7jWbmOu?C0K{ zI3#2bGV@AUmP113mC(7YDxnMKhwLRe^GfK-At8H^wx+z@HTEYBmgA6+J;=<`5}8r&b$(O za!AM?q^+r}Hm;R9BxDaV^K$(chlI?_brn6r{Tw~vH_2Q6_ zJ;=-}VKoj3nODNMk~6P_H8~_?57O3DRvXt^91^kznR&VP=8%wixvs58 zc>I>+tTwJboFB3W87$Y>cU*lrBxDaV^GaBULqg`2P$;WPSeNrd_L7`=C9KCGA$yRv zrn1_&`f*6e9%Sa_+Mh#0=H)s-kMQ^{$==4*F7nqktk3x&dysAQjRXESsEc2YdTQi1 z>^9(#ka?0ftW%OZMNaZS&JVe4lDrXzgv^t?aakpK6V4CWOLB0z#jb=+IV5BcGV|p& zh(ki=l`yzYmCz#ca@&maLoS;nZ_Xhh^CS-`t0Zs1`5}8r4lcLYm9Qm;gzQ0PzTCFr zkdS#L46Rco#J+_X#`z(8Ne)&*Y{=mp60!%Gc_obCkdS#LZ2gZa!FyLa_Hx^X^F#KM zY?Y7|30ncR*;LiQjtFW2okBxGK$JLnM}f3Ol_?+H6{e#m75xf6$k z9E9}BHFhR<=8%v*$jr-i7Y+%Tm+MG9!sE}pTzBRCkb{s}Rl;r@60!%Gc_obEkdS#L zjIL89#C{byhVw)AlAL+Dj^&V$gOFL3>+T#9vIm)YxsKzIka@Z8p+|W9!Agi-u6uHR z$U(@gDq$}U3E6|pyb|{2kdS#Lj4!K7n85iVdr7u(^(rBDx$eUuA$yRSSHiv=5;CuZ ziT|h)yd=kdfisEoL-vxqRPw$9-Y+A6@9g}@?>kK9kdS$jr_?FQv2V-w_miI6q`B$(et2;Ybb% z*@Lu7@IC|*JCjp6BxDcLGMRIp*2eyY;-feuWL~aE>k%HmB{{2doyPeg2O+bngkv}) zWDn9R0S38aj9m%SIV9vDWLD*REQf^5%k?-t0{r+6o#Ll_){(E!>DEnt+&lfqF1gC< z+7-WHCne`NxOoR@KFCW(O6}u*sru*{k?)U==P7~gq1r^f^ENIrBxGJ(CpGrsI+>>ga;b}|cCD4NsA?BMeJ-j~_`D(0QW(~xPeH$ztJ}Kra~=7R z;d<&}f`xvGnJ@HD%!290aCu^OEL@qG zoeI|^=CXzB60>vR#>DJWxGgce7Vb*S|f}dm;(ySCFc5t6%uoU!b*v`Vc}niIk2#LVs2DeGch+V^i9l73jGsv)53;{ zIjFF4Vh%10O3cj)n*^i8-P0R$}f`ct0`sEqs!g6AND?=A^>ci8;COU1Clt{5LW8 zEBum}`xpL5%mWI!tE=nxz`}fqc~GHwVjf&*m6(SV7D>!Q3+)o~u)-3Fd3a%&#H_5$ z<#L5C<{qK$^5!0??n>rPRd;1`k5adnxkszJhPl(!?Q8Ba>aJ(*bamG^_gHl|GWR%j z2bp`kx?7ohg1RHjJyG3l%{@uo9nC#i-CfN+Mcpyxo~rJi=ANeRzUH2;?j&>1Pxx#y{Sin-^jd%C$7sC%}#7pi-nxfiK>k+~PE zd%3xns5{f#OVz#3+{@Ix$=u7;z0KS!)V<5x8S36=?v?63Z0=R+K4$Jrb)Pi%YIUDB z_ZoGdGxu6`Uo`hRbzd=emb!14d%e1En|p)0@0oj}x*wW*le(Xpd$YP7ntO-3zngofx__HnrEZgJs+Vl#UFt4i?%nDxWbQrcE^O|->b5cW zK6Mu}_kMLdnEQabOPTwix*g4ZNZl^xKCJHY=02kCO6ESQ?#kvqrtYfdKCbR+=02hB zn&v*K?%L))rS3ZBKCSM0=02nD0CS&Jcc8h?sk^DU&#Sw+xi6@@mANmfJHp(T)ZO0P zf2%vv+?UlIW9}>J?r!d@>W(+}HFYPN`?|XOoBM{khnV}Ox<{D%mb%l-eOujQ&3#AR z6U}{B-BZndPu(-keP7*k&HX^#i_HB{-OJ7WNZqT<{aD>=&HY5(8_fMw-CNE5Ox-GT zKUeoYbN{36Bj$dg?i1#IsqQo8ex>e<=67B-pUnMP-QUdpMcqHm{Z-wHYm){0o4WIx`#*ITH1~IPTbcWZ zx^2zsP~EM~T}a&>%x$6WNON1NJI35r>h5Lk!s<>mx3#(ln7fF& zhnd?(-J{K2RNdpuZL99d<}Rl08RoWA_k42~SNBqL+pBw}xgFHK*4!o3y~*4q)xFi+ zrPRH{+@;mM$J}MqebC&F>ON*}Cv~4TcUg5`Ft@Y1|2DUay04nsRo%DDT~6Ki%}yCWpx)c_h0HRZ0;)R zE^6+o>Mm|>FLjqRcQtjFF?V%!JDa$3^GtAvW z-E+*{Qr!#9-Adgn%pI!kwdM{}_hxg4t9!e-BhI*ncRzIpn7hBa_;p^)_W*S_w&;QC4mS57b%&UHu)6qVDI9xlWVm@nm@_yA^V|q4Iy-E|jzl z?0LTY?0K&KI9q?5sXtEFAE(NX!9y02h8K&~?a?ce_k9K|lFL=;VY0x6%l`%!-yOO{ zlqx-F`qY`7d+Cos-7XbZr;+O=&vplOyS&wY7C!XBEd(vI}- zRW56DRp%ahbl+P=8k*~VpSDAP)qm9CA{=>*qSqWi)*<2Z*UJ0i?i)>i^#cQ^LKwh{}sGz)@K@;>6QPILxlX+w6tCEOmG*?dTmaqC#wPoa9#O}0ajo<*FS#$);bnSsNok&a z&XCCDJl9*Ul`zS1l}=WY-KqD(VuW&yHkRv0^a#oIRq}6H&$!$5N|?J!O8>|)F)M=sDLx4|Gw(qr0zBx$Dn zTTe;4I<0Hl&WcO=AJ^LU+uo})sT`!aQuylpRO#kCed?^v(%-Dkg9ml%qiMz8xT(CM zowU`xeEQTEHGbT(Rl2DsS)Sv_sv5gimChjPUpHy(PPX*U|k zvRUII;qGO#(t4dMk^iK>8>GKvo>hu0nOG|FHRrjk@V|Y#kZFE@b%vE?zonMFAHIHJcQ$ zjjGwSfK{&Mdnn>t7NHn3x)P_uOOwR zw+u5dv1(t={(ajG?D?t;(DP;e@sj>{L4Q1_Kc3MaPstD5Jjg*ai=A9u{O6kDKN8PX zX;Zsk*(Ir8=iVP`c&HA2y|&X4rcb@Jh0eF4*HN999VC$(B+~6oiFEr(uBpWv4v}vZ zS>9IuNPFmxew<+{ACSAF&b>djp>CRcsHVwKH``D@*Bt7W;!vMpsM-D8I(I+wC;i-J z{rpn1pWD$-_hLT)mwDW&y=X#pe@qgvip(9C=FYu8)lsG0UGk6SCD&iK);_NTCJEl7 zo#?62y+ZGbDqA*QFEz`9)`h1}1-QUxn#gM4^g*DV2p(<^!snop9nOs#m_kLdwmF^$b9(2$u z{ZT!=X3edl=IE%#{es+L7w=x>kX#GE_5n_J^gOJI^!=#zt@q&7oA=GKdC$(CE-y`m z4<>i3=0T0k%S-5!wxdZ?s##KnMG z_jc;`FpJ0`NiT17R%J7N@#`Xgz=MxPM$Dv7B-f;Avs^w` zxzGGL8Fh1s4W6*u$h~AB3pH=8p}`UwIAP-6BWoVj8lg=kG<5RB(IfY+anvFbYFQzW z+uO+7q>Mbm?|xWn_hYR4-BP+ADKTeaJNqN=m^$)!8+p%^k;nPnk4^3VK z%$e9kf8>2qM?S(vJ}hPAL;UU!O6~qQ>;9OO?vIw3GqI`O$f&ndtosvFx<5X(k8`b$ zvr_svLt+l%X{p^`Y~5dw(*1d`?$mUxYftF z+3O;ozfnTYzLKxFQ-WKKo-}2z$+>CyT)t^j*~KR3E2>1UvAgAEce^y#thm3)X7rFD z-S3ZkZ`!yI^Kl(KulwV^nl|p+ zeB5`^$Ni6u`>8Z^Qt`2boK$=$AvYCYNRXuBOOaDj@uMMq?~nU!+PFXQaeq!9H@8G` zQT|gJI;r?wLNpaEEAkcjCFp!BL{6D+a~pSlY3O#oAn$yk^v)Nv&f7>sXHu=x#%;&P zT|9lm|SJMWa<`HI&0^3u?m)N*O#uEfXfkv{HfHts5Eov+S2Un9Nq&8_o6 zb2gmgo^TV1ITPMULbQ7F`3)uHtWw#AN7%?iQ%2s>?|w*X_am+Qol?5rL1NCtw)02c zCUxX-Hu9L1kw^L6@0!~EMC*P+O80w9%$eAp-pIIhI>5T0lG6R8)IN@|J`PLi;}D5C zhzF&1e~fj1R7&?pruK1)^>Lz)alF?>K7Xu)oZ8M;oGL+b1v*XSlpXneLpsMF_pG#W zFW}=|m_F{+HtvI;pr@LNpb6F@BJb`%wD0PujSTrFH%k@BHcX&R?<4Uy_E-q+UoH_f@ zYvaC^*7(;Uob0*wTLi8-=^Gi!;z?3m#Mo(OS!j$py ztfL}%Lb5ELbu4M|8qYd9<5@?(VtEP9UGSA%Bq*1>H4M6!w5n16b3m^mF$a2O2|3U` zB(&Mc132-D5=@)X3Kl0bT2q4Fj0V_@){|D=j0zHSu=`5L#a>&2Y1nI7ycV`(dk16N zPTF~F+eoYyTN9k;5!U@&S?!X~53^W}q4$*sXt;=uv!TbN3_VI>&WYYtLba%hPug~| zk>{eSELP`E7Oz2;ROcQN^v>mEgWgwKdHI?kF^6n#8<~^sY4KWQa=MPN;SWn0{t$^d zIXg%~4%q=VGAG;5;*9KgBbzSmyu?hCm_v4ygdDOXQ%63-Mm{xV>yFb^u=XpKb;w-PTZ1`(ZhMy@hC$CpZ$jR#!HZmu>%;L4k@)g%h&|4*U8uV?_ z$}5IjB<7IaWFvF38!TRnOjgOGHvB^=!#^M~CujFb$RWGOM&@L9S-cimzTz;JlIb1an-cUU{(+7BZpz4S z``ruu7uLsTDSdn*F^B#mzx#Z}mlE{of3T6iO&R%Xzk8wo-TL@d+Bt+jdtK!7KT4>0 z3sCFK<}3b?;N0-?{P$0hYZTes&wm$OD!FxBU?~@AJ_*rNp3gUtP}*Hd-r@v#Aqf)X z79yu0FJ{PXq@lyrI&Iu`eB8y;$L(U{cJjwv#>VA~b193Hd~}r{$;Wacr{rUhacwLO zovIorAtzNENGRaIR*JNLq1s=I$S5(xIC4|Tbyv6E$NkO5{W-1k|MAX$ zPw%|l(#f6SqD#+lO6Pb!w}`}?2`?-mdKTrwToNi4UX8-iRfY#f9c|>LQbt~abzj_A z+OzI8gzi_g?w3#LemRLb6YIi8F76S_vXO0KtJ%n_q>Q|>-+hnN?)zEyg_Q35O3azq z+WyFE*~oM4)zuH$*04A`ql1lX6KPjtdzhn^Hjh(G#fe((8;;SwZU#xO>~Udq_j)MC>jh z=R}N=kh7@s72_pHQZYf~lvEsGNK^cAC#8*hARqUj^l_)#xJOGvClymA+`%u3IEXxNa3Wg{yDJ3#=^ITPE?A9?yENLzons*iWep1q~duAxv6+ff+Q8Mi=2{*4-DyDf84jz#{H0w`%(J1U)#7} zNJA$TpG%0QLLX>+!^izLecYdI-2bL^{tNH?*YwUSIwf}+e@jDWQh%n6+oTgciA_aL zIf)C|xXq-Yo3R$W^OotIFK(T;m4?ow+N6!!o{!rhecVnq?$T+UFUvdcoZfj~>%8}z z4d=Wkl$bN&)g?p|ozM4@kh4nlp3p|_mooCYe)sF7cE7oGKPaX9O(f<_Y$Jc<4O2%R zVIvPs8F@>;`yr{_?`+-gkkb8j5_2ZDjW;rGokm;tyQXx%OKKnEt&crZ`WPoM2XSm_ z_mi#reN(!hklM$g*2h6U#sOXz`TTwoa%wwYahL?j73gr0Q#P;ZhIF()?$oq#kLBYY zmp<-UHty-t&^aTgO2}E}Crijp#n}=hsW?aElvG@5NEi9zUXV8KWqjPr)5o1<<6a{T zom9+}5KV<%jIZb8-jF`-?KbW$X`SD}JHIo%^M|bS`=y~Xse9ALeVC8?Ncy->+qh4p zb^Z+R{Mq!*7hN{F!)U$i9HlhJb*q)coC&v(5Iu|e{DKlndt}ti;x!)4Y%GsKv;f*l zaPERnKC--wK`$w-YSjN6&>bY^kS%T_^M^)@S-cjRTyeYG@ZC~|@9GcV*}CV$cd~e` z;qw(MO3+Kp8b;PjT6u|CMPkm`TvBYa{nf8F_8L`?XTLA8g%k zlG6P~5_2ZDp+EBaHZngO{Vh(;#%2=q&c@aTJxp48XJadgIVs=5M&@LjTf7#ToRU#C z{K%Bycb1rwvmGVmkZo@xbFytMUW+VWFLp>q9Kc{s6qr{wv{os%MUFygcU6Q-Vzf(s3)9?QG z)b1Cu?wfUS;pdl-b5@#4$T=(diWU+i%e|$@Da*Z`AuZ~UyGYu&i}P{Yr;pp!#$8q# zI_I&Ygq&0?Eg?4*%Sn)=qMOJmsrZ*6_3+1CF>Tyc__(X4kGrmo+gBPosaRV=PAb-t zP})Ue4U5-W%lV4+BuG-#Pvn$T4Kn17rJ=($(8lF=5F1#Wa1E9q;o3~(6t3-!Ya40k zq;iCW9OPjVN=xNd7AMF%NRS}!C~^w&?uI;C8aiCN*|G_ z2jNSCt1n2!uLZfw!Zlcrl}k%Lf2V{t7(Hq7xbY+Pdxq)Zx6j$8Mjumgd1~3DrC>iG ztu{PhpNTu~H*&8UU&-0Bsf3&6n?CG>=hNV$UQnL6yi%Q&w~DiF@^uJF^y`bb^qZN~jtG*gx54PW#_c_B^5}^*nihYdXT0_@dE&V7V{3$pzqcnC1A8PG z>-TUl`b(fz2ZiJ=W?%X2uT*x$i(2E{DMVif7vR(9c_`syoQAtprndNg`~m^r+E$ zPndXMjkyiXx7Cj| zT79pr4w(HFRC1QTRcZ4YsY2Jk);Q=VZBYc6olvy;qeiRWX1B6$xGG}iT{Q`Xr=Pd-N%iQZxA-QxLLK)(6GJtsTr8B<$Q7$ zJ4hr+PdjZzQ@wO`t0qmB6|1)@$c#T$D&2BYUU)xu=YErR-SXgWoJBp=? zO)GO7J#xStd(H@z`qz+JR%k`;r1CJ8XU}?9(UQX389j}gJZX+2^A%&Nk86kHj>uK! zDi@IxD)Zc<#?fQ#=$g}%U#u%0Jxz~pn#0kH7LT4-wC1o>kJ)AVq?D)rOD4=WyCbNI!IhaXkr@FTRgw%U8bsL{!Axtt6qr}}v`65NUx#Y%2}p3&x8jUFqD z#QxsKHMlW_2MM#L<&%dFFC*fAO*gglDc%UsBl{^%DsuqkgCjy;0xSARF~v4b&d>ZI!)Izm;Gz z>Q~y(8}$nfvQa7c zd!sHZ!DQ5Bw4pcZQW|8VE}?KYPE zM(w2yy-`=uARBdM4b&dBhsxfl>q#&fbscT!joL?pY}DQws6FbMDtn`DBEe+Tf!fd; zbps8uQ3q(C_Ne_-_C_5l!DQ4ew4pcZ<{D(94%R^JQ8!iD8+BU=CZmo(!@cDXG9}+% zESvkVw4+DXIC>{-So2k8KEDI&aJ#e)_pH(3?%L2x!Wa#*B#c7$b4_Abh|UFYiUgAs zOw@+nnEPmujX56O&o$;=5S=j(mtZpHA==Oz^B@hfF%LlZbB(zlL}$!nC76skO&fY+ z9;HDx=8@=rt}*d98NKp4y~dcQq>Xu!H|7a!%;O+B^Sn@k$vn@~hTc5S(IA`WS?GSQ zd7c5$8S^R$CSzWq4ZSfh(;yr35_CV;m={5G#=J>_$(Yw`LvPIMG|0xh2Hnp!=1hpr zn0HGs8S_qU=#6>12HBXmqWihVycwc1=A#l!#(YQ{dSgDIK{n=n=zgv-?}6xy`Md;^ zF`vHn16U<{*R6MYucC#)flsx*zP>%*C3l`Qw?k~ z*E}mAI`dpif=O=MXhScztu@HTY=!RU8nXpNXUwG~n2foEHk6y4+Ao6JYh>WK(R+=W z<3^^P+p|1D)!2ZMlkoh#`pHzjqNA!CjGMHN_A~o=)$$@I6kW9mrRc1Y+7z8srdP{+ z#R?j$MbTZ=+7zpboKUQ+O(;bVjnt-CQDui>HI3DxSY6e*DDoA(iv5fljW---r)V9~ z6S%dt4TW1vBemhyD0WJoR^%(z)mSaK^;E3|S19&V3vMIP6Sxhu4TT$^k=k(mik(up zO*B>uZc|lj!ELPS;L+p9PTqaa>e@;I3EdEFMCmruNNu`7Dm&+On8s?+4Og`m-B48- z-HsAS=(f{Flx`c1)TSGuvO~AC#%j^+qG~O=or?X`I(Hfjo6YLB|7%HF7lNiZ4pU~TA)dY}f`sQYW6 z_NY@-_C}p9!DQ5Qt^4YELY2KyZMU*Oje4yH*{D}*p!TR&sqBqk1E7!gUK}!Ymr#465hYtyzdYg>zMXWI5=?O@i9)@~=$ zb~bAlvqoCGT}|7~tWg#nZQ2;K##(fD)5e*#hgo}CyS+@?+pO_sO|W+Rn6|H36U~}r z?IxQx#jO1-y1!`$n025<4>Ijwvko!qP-}OXX@{FtY1R?e?nu+7nst;#k2Y1Lf_(KAgu%dE4_I>*|bYub5coo~?# zOuNvmi_E&%+FfGWrDk1b*5%gj3e#qob)`kGGHs?=SDST>wY%1|>r9(v+Vy7LVAhS+ z?k3Z2HtQC%ZZ+#Rv5KqqcGK=K>rS((%(_dg;t_Y7c8^*2nsuMGyWg}2%zDtQhpgSh zrafZTqZWP4w8zbQ!mKB)-BYGLZPqhpJ!|crGwpe^UNGxLYxk0A|2FGoi@svot7g4s z(br9T!>l(g`j%;LoA!=r@0#_VMc+5=1G7G~=trh~Y}O}ceQNDKGwpM;{$th`*6vHw zzB21;i+*F;w`P53(eF+B!L0w9^`o`>$+Vx%`o*kYt=(^?{m-o5&HBTvKh63}tYV%1 zZCY+-a;?pqRUuZfT@%xqnl+zA=QnKuvznRJ+}bT@+CpZvFsr3mt;8yhyRd1k&055w zZA@F#thQz?X6@RUwzygCE!x4fCCpmVtfkCaTC5_~GNyGjt&?fXn$_8&T}**tzgmarmbk!N*3*5T2Hf9HtS#3ZWYs3HLI6dtC_XBSjAbcVcMFetz}wov(`4N zk6C@iD)zFDX$7;^HETVy`kB>Vtm3f)Ok3Zq4b0lm+6^>qBeOQP=q9FZYSti&4mNEw zvo^Qr5Yx6WYfFo6W!g})hM6_otPx@rXSB6x+nBYjMYl6;d$V>hYe%zo606wX&Zg~R z)=0BFzZdT-V&?W^V_DqW7fN7y=T_@Vik}0z_bs|`pB%0&H6;F z;t`*k_L*6qoAn>Fz7VT;#FwUhW!Bdg{l>I!&HB!w-<$S>S^u@@kEZ=(*3V}BV(or4 z?KiXjXV&j#{UKJ7`A^gSGVA|{I~O>csyFVRVdR=bio~4jJ~LQyCzVU?r!FN#l@ygMsuYxte2&;kiz*|ktoW4^TX|6xM4c->N3q(~Fbs?0FcahktiK;H@V)3gXwo63S6je+7QpDyL6%Z8^ z6@tMBuf#jl;%+KcKSs-yUI5?g0cT|{*izpKU8 zO;mSLJw){s)k{=wD4k^=vGoP=l_M%w)QwQOZ=Trl#a1A;aiYdc z>jbe)6g5d&ZxY*NQ8$a4BI*`Vw?gT$6pC%CsA;06i{A{f%@j3D)NSH7TWq(Bnj>ni zsCiI&1b2vSzNkAzEfBxE#CEr+h0?l6Y>P$RBWj8GEfw3nqVAK{`^C0Q)N)Y|h~Ema zJt%6Ws8ym?L+LCZ65GR~)`)sU)LJOrW1ZO6i`pP+qxd~4w#P(0E^3pg%}_e>6JmQ( z)Kj9K7QZcGdq&i=qHIxHp>*VJVtY>1c2UoZ-wR^fA!?_n7e&1Ur6a#AwpT>GDy^@H z?R8OaNb8$odrNF@i|rjz?@H?~vArkieQEtbY#)mHNYuyTw_9v`M13OaQ}O#uY@dtz zLR!BR+gGB#mey~?wpY}*(z;J<---HO)DPmfUu-{$Iw0zx_#G14VNpMcIwF2Qi|weW zW77JI*nSoDo3tJm+wY=Ii26hP{uJ9^qE1TdDY5-6>K{?3#m~3iz3WR7RYFurD82rY z#a2qxIigC7Um3BL6;)1DdGV_twsS>Q6m_2XRTA6zqAE*k6|r3)s;abJD7K44RTEWR z{4N$-4N;d!YfZ7$5|tvYez65a1x1C#FD$l*C`(jS{8Gi1CaSimI^tJXY)Vu;X}wfz z^+h$1)`nthB(}z4Ya*(tv^Eo4b5WN`YYVYmF6s(ty;5u~MYWRF)?#ZT>MCh%E4Fr` z+KcKSejUZuNmOT1UBs`e*sd1UO;mUB>mjzDqI!wyEq;B()>l+NQT@elfY=6#x<=F> zQP)E0^DSL$*NGY|Dnr!uqJ}`}zC*>9DQcLgEK$RubdM2Y8!5JIv5gXSgQ(G>#)ujV zrQ_v@EmzcyqVmKqUu*@U#)%p)Y66swJW*_uMBOB6vZ$M(bdM=wyG7Kkq6$S#h0;By ziEX;58KP#2ngykM+$Of!qHdSgIbxeDYM!V&#BaXX?i95^)Lr6tx7ZenS|n<*_}wG6 zC8Cy!x>x+}6WjfwmWf&}>H#R7?+UR!C~BpsRiaiy=^hV>?O{=CL_H#YYsI!s)Ot}H z#BZb69u@VNsK>=`lh`(kdP3BbqMm}%BYj$ITSPr0>RC}Xl=b?0u z7sR$h)J{<^ih4=Z%TT)SD`I<9)N7(%7r!^e_NJ(}M7=G3?}+VPQM*LFC+dADJ%SI! z_MxbcM13rNyT!Ig)F+}o6~E8K_PMApM13jhD=0mJuf_I_sJ)`T6}1ma_xMh1-;4S| z)P7MvLg^j{#CA~BAyJ1#{RE|Z91+{kVmm6fW1@bM)?dZ;o2cW``n%Xpi26g+pW^qI z*iMQ%CF*bS`$uf2MfoxS6XakM3og)PW;M?t%9g?MO75P z^Tbw3)cK++i>e~(0w_J^s$#oP)J3AIiC=ZGT`a1Gs7plEgwl~~i7iExUs?lV3yKPf z3X5MvY?i2~s8sPw6I*Rjbwt$_rJ(fq>WS@AQT0VN5Wj|EYb2_%s3xMCLg~oO#MWHY zWujV$-{oSvLe!O_T8e5Vsx_28MjNqRC918ccB0yg>L98kl#bF#Y@J1Q5!F@H)lj-e zH?egW)k9QIQN5sakKSVIBdV{cexmw|8UUsH4iwupq6Ue&R#ZBa?s1*i28+rNb-kz| zP`bxZv1N)HCMrwRa46klgxE%k$`&De zsPUpEh?)qc`%V(uO`;}?x>?i|QMW+pzPF04P}EdW(?m@dHAB=)C>>>%*lrUwTh#5M z=0NElbHz4K)E%Pci@Fm^_gEmdyF}eBYN4n_P`bxrvE3tTiKwNb?iF>PsQaOGlx1RD zF6seMD?~jgY9*BJyGm@UMLi_yVNq+KbdN{GwpP?SQR_u*fYLoSitSNRkBNF*)Fx4z zp>*FT#P+19r=<01v279cjI=&0He1wIQQJg42c?g;U2M;bdO_3Z76=^pQk?E_ICO6x~r`&iU&Y272X zPegqx>N8QFL+PV^A+|3?eI@E^@%u(>dqsUKYM=OhC${fJ{UB<;`28rh1ELO!IwXFF z#rBh^Bcgs5byUskCI|b7F9~rIpSAZY-L216;)3B%8RXnsB=YC6m=ey9zi9soiD1gs4C)j zf!L~wx=_?b;#W;<)kR$_s)qPoBDR{MYDsH~*!-dbqJrWV5?feQM3g0dQL&|pN)uIE z{OX9Ut|%p~^~83msQRKBh+jjoH4@cWR1;B6q4X>?6I*jpmx*d2>T)RE;|j4|DXOKk zwh~)wQEjC4DzUW{)lO7(3x`^rurF&d0wr--ji|Qe&r>I^~x^Hi> z^%2!qR6p_SFSY@q28y~y{052bTCt^z?K)9|MP-QJ^OH%@HhMNJSjQT!%}?Iux^McpiF z3Y3m~i`Z@zRVZqz_)QbrbWt-z%@j2YN=Lp;Y_mn(E^3abxlp>tJh9y&YQCsD#czSw z?hqTvV(or^w?NL#WiF#brCQ+M3JprYoJSn!PL_IBPi}*bwwr54z zqPB|K2BjlEC${aPo|o1a#I{4!PEjw4-%Db9S=1}i`l{Go6ZN{NH^lEvvAregZE1Z+ zZ10NNCF(u#dtYoHi26`kKN8!=qIQegBYvNV?Nd>oiTYgpz7X4&qP`OKwWx2PH1WM+ z`&QIGQQwK*_hS1&)P7MviaG$LBOesoAyJ1#{Um-z#P+kOqoR(9`UOfy{#9(hi8?Oo zckw$Rwm(GuDe5m#C!uuYQ)2sD)IXw5i=XdNx&ISYLR3jn$xu3SDY2a+ss=vZyMeE)Z1}N{{qHv0WspnyBjHcd^)Nh`K~nO;NR= zbmSDV`9%dp1;sBUwy>y(C`(inN=Hr=TbiiaqUwlWU9l-q^+a7Nsy>vC+(2v%MKu!D zSp1rZt*NMHqMD1k3`$3CA-2m!T_Ng9@oOozR-#&qY9s0@C>^=2*xHF|FRdNK)=^X^ zY3(ewE~2`Mx?23YiLJY+9@5%VY`sMF7S%`m`iiZesQ#h`h~Gf5T_b9csB1-~Lum%r ziEXf`3{lsM8Um$z3>90Zs9~bA#BaFRMu-|IDqGYjC>{9*v5girM$}mG%Mn|ys2fG) ziC@0h3Pg>Q*70JSAZnttP7>Qqq9%*FS^TDm?G{nDiYgSpsbZTZYPzTyqGm#A8neW9 zo2c2MZWlENO81y6wt1rN5H(-??iAYsN71kDH^*=772SU#$=z?cDK!?^e}cCPXiN>= zIvYDc&}Pm_Ne#(f)O8Vc}747@F`coTvL zFlzqo|B{=a^k&+dp~}<#6(yg5;?1;^pMfxN zI7e7Vts0H9DrFz_NBB5Jt*gk2KaZ1@S&%iXcs?tr+1*Y?evmLe9l(i3^L(=Ux0VWr(N=C?~`92BgVcYB5@45$T_=(uUh9+@Rj3T`hC9g zW2;temffYrfJSZFE_&y~dBgqJwkd%>I?}#H`hk`9{`((GA2u%YhK!t{!^h=k4k^gV zD^|}OlAB+UGd4?&8Iq4bc9cFQe|%>8#HNkYduNT#!VZDyu0y@tVMBe@e3$rY`bt-A zQRrXjpW(mLzcIKqxH(9 z3Vjt`9oiXQ8(J8CEHo>8F!XfzaOm~$vCvQ98R0v^4~G8?uM2OAYz}`Oej~gi@_u+; zWOw+R$k*ZZk-gy$BZtCEBgez9Moxw8$kfP+$nBAPB6A|!B6mgJiY$-37+Dp0IkGzP zapa-M6Om^kKSZ97d>45mvM2II$hVQNB0ok7(=iDp&#&SSgzD!OjGJCzWrfuh zj#fBU;dq5Y|5X2UK$z*j%|F|JJ76sE-vum-{rC8n`tSFz@IUBZ>0jkv?SI(6#=q9T z!N1Y}n18eXDgV>{XZ&0J+x;*2cldYuU-G}|f6f28|4si}{&)QE`rq?^=>N#S+yANm z3;);tZ~Wi-_xZo~AM?)$%nHm2%nK|CEDWp*tPeaH_$=^k;Ar5Fz{$Yrz|7$6;O)UV z!MVYC!8?NUgLej(1Xl+i4n7iG8{8Ot6qEF1@F`5u*5C`l9l@Q!7lSVcUkSbzd_DMP z@U7sk;QN@ikAfcu_XI!16n+u>Cb$<<`W+_lK=5GjQ1Ec@r{Iy`&%vX?W5Hj7zXpH9 zniHBAnjcyax+}Cev?R1NbYEzB=)usc(CW~`p+`b%Lyv|Y z3vCW<3B4WqF!WJqcj%MQXQ92JeWC9|`$Gpp2SbNLM?yzK$3lOE3d2*w)56m+&9lOD zFxB(JcZC;*mxS*P-ydEcUV*7!9bSvc-xz*0yeYgn{ABp)@H63U;qBq)!#l$-gl zcsu-V_`UG^;g7<*!=GY_d=>sWyf?fr{Cyb9F?=ZeQ}}53xA5`s2`riulO;|inMYdo8 z*;rcJv50nHX}uhIHS#(Z(_4{uBD*5*M?SSJ{tuX9J;`E@tcU7;RStJG@suv(+msE+Nd5=kE_k< z3H6lPqMlLDs;z39dQNRu&#M>I4z*KN_g(C}u&~61KHqt*Gjqn|*2^CD;<)6b)2FeJ zeXZ&4pkDp@3rZ#xI+pP{qw9?s=A+Aow$#I)yvQsVp9KRhQ0SF(3(1&&^)j^7+bL+O$z4zwxg@v-+1cY+k=X{TQp? z-=Kc|rcImr{mmQJZ`_dmuP;XslYGNwjhMSPtNA}qR(SZ+4c#{0zk5s2>ht2D*0>$4 zP})ar;Z}6JsQ;P3$wIj67NtQngQdV z_&M;Yi9)3*!wFLSoC%=T-B0^`wa?_|Oal4cHxMuTNO}Jxo-+~DG6!S3@ABA0$PY*r zt>Em@S$Qpj?OLSw%*z>(H)M>z11$Oe)QQcTrlohw&dkfn&lz6e@1LDNZpdhVpMr72 zvUAcK)^BiGdfS{aW5$imE|`?wzioQooSf15>D~H3HfUV0;brw2)o;+KQTovAvFV+1 z@(TtwZ_00cnGNd=8$CMczW^gs1(R~KhT(os4X5|iT}NJiq1ZcU(RWz)4by!`9g>$h zGQCeO3jK;d*)?u-R=rH08kUpqQ-iX7YJjhiPvs9AjixN0>M;WU7vTS)4SlM8C-`*h z>r);3;QvWJ)gil}$Iww7#*IY)t=kPL7y_O1fBB~GjynTes1;<#-URUQoq^{J9fhL} z`@cNe8E-LER$g9CUS3viPF_Ka+&oNwf$#hdH7_38IBCZKOi4p5mMS$1UmWK+Ezx}3JbWbd}A%Fr2*MvhviJj_jkq4bmosgxzdp+JahZ7q>6tmW9_AH*3)WReX3p5**(2(W^i@jwY}bOxpY`l= zviz{)Ey8s^`=N4fVu2@cWDfa4&t{jmy{_EfC7OKMvee6~CRENjyO3U_ohwhi+;U3$ zqX)Zuf7zG2PFAmcWwpeo?2K!;Qqs_+?N=Qeaq~4}?rX4SYwzUWD(2VnWn_%b$s97; zA(o3jm02)6BPW;sE*|Y)U8;;9e`TpE{>su^5`~yUUvl9BTpg3f*D6tQV$lG&bsZbO z|2#kX???AKPXEd1-!R3OF@E?2=dkp5R!b$5Uo{-?4iepQsp)^w>kC@@l1t>*N~)5Q zRIzEWS%i>cptcn2!{4Oi)^+%Kt9AgSUgbV82q@w{FQ(CZ%R zwYeT%=2!LkE}&k?N!O#-yqH6o>CwTKP`7g$;N=J0Q+b2@3h6x*)6<-M>baD9e%%l+ z7h@{Do`0d|v)nVY_(9)?8(tqHPW=Y-#7kP#=et->z077es080xi(dcB;7mzvF_7r<1qFixXa(P6Hpetin?@;mx@XFl~i zM*Z@~7UR+d$9stS4V;FTkFPXO{O#y>%IqiC(QDA_Vd^z@I$q|qlym7Ax|ELkC^ z;pOJm=9%{2y6Bxqi&3C&~F?G@@a3f;V`84dKMRGPq|%XuhzJx;ya zt-;GOoU-1s+?twHagWi<#7X@&QNJ%9!OOVb=5>YoeUpkcrVoZcLFv4^XQ9((>a=4m zUVcWW^C`2ENqf*^-2flo!e)#Zoih|SCfWE*z&(BNeIM^VJL*8BJc*aTaFf}2Bzh*5 zeX@VjpaDtQ1CnkWkaW|4q?rSf<_$=?Ye3RH1ClCkawF>78VU9xg6*VWUp|GG#`pwO z^LiQv9*+Lis9WcreKLBt@0ih`k+1MG3>ZIvmXSgCn0()qm64l+Tc)hM ze1td;ZunQ;H}!wHl<}2pEJtYA&^SUhbicV)Mt087al;X^iVj)ESH|#fX86~n!}af& zRnWOz23=8>pU-0`<6G)==+xOf!llUXxR+mZBUm|Ka<&U=1VZAEo#c(n@vckNe53SX@QC z^_mga47k1y*Ydt4{plwi8Dqv~jX{WWDm&Sh_Xg9bzA+X*y0ofBPn?NP2;OCUU9arZ zvrX@|JiC2*`U;OCIL~fBI4|m-ISx-*$DqeB_bBJ;qa@$xvf--(KQEqE8mR!wB4Am^ zSWbCp8#FOSaz28e?wgsPfe%d>`6@k6<$XWLvE4)y+I`3v9(3V-?v&o+CE2O7nWge2 z-{p>t@r*@Z+`Z$k#A9stqQ8x?mG@=W#_@3$WaQ&V48!QNC{~zGuDmbn%#CGy$Gof> z8%dpmptscO(D`ay)!emO-gmNpx3)b;PRhq$;PCkZU|!z0upf@BR}(xpyUE`j-&~1? zGG@qVoMODFU%{D*f60~bCRb#k=r?9rD72>D^V2NfYr-fytf@a1b=4MSGe2F;&0@8hQ>0!{5oxVcjL9z`!ZkQAMRS~ z>PsHvO&Kn6ypj<0Gelj=vo(WOfg4v=!z1o+Pk2+(z+4O!ki5@Jr2&pA*RQH*``hT( z)M%^hOa2R=SBmhJ8+80g$~kXSki&;yoV>mGbU1eg;@bhfAMt#=S`QqWHf9n78)8u3 zx+v(UQKyYTnOCF>z`l~fzFk&+CLn#{qAz>KwlcnkLjLOB2KjP0T+`ZZ`(*U!**BwG zk9O^Sg}bo6_zFPR{@=Z!nCQx5Bd@1Gf@pdpN( z08Ntb$^JeHku}Cy^S;^1z7i$yBRaf^V`OD~e|ke|U|z~AqOFc`HS1tr&6=QboFM4k z0GDW4ecdqb@oD4m&efbwFpL5Rn_SD+Dx-(~=-&rFfEqF)t97dety;xCBG7N<&J%*x ztuJeR8U0kQM9DJ#fG?E%Q=G)*W2|@Sk0AFia8%^zt<;9*D!$N{{Arx!CAV~fu^U2t z$)PHEp&FU*M*$pWya56P1w?m%SlFM=(9V7F^Xh_ebYi!0FNq7z*pgzbyUz3@P+#G- z?wUORjBUw(g^QhF&PO20hpu2>A)oTTXq_Q>V>0sSBFY2iNgDs3Cds*dJ;N-O_q|*X zp>Z<$GwD&$jcd*n^Ej-XDcpb$#2G) zM`wWEil7U{UOx?@gg1>1&1t*{ZAbg!ylvmRcSet{`Yn{tTIyBZ>(!>M*{vQ1KY^Ee zgQm3B>HVmTubSy@t~-UspVM#@x-w)m!djsdoez_YrqaFocI(rqVg0sE8xQ15S^KuQ zww!idO8Jt1ICHk%C6u!L4%sGG!6T_6S6ugTn5>A>aQ=bOEW6aWhBm+y$u)Ejvdl|! z&*xm^n0y$I5Q>C$9wO} z9c7-ZfUE-CtK-%z8($l7?uwS-lz5i!ivICdRs-|)wF<_4gzkW-D;8F!dlLN+&)D9* zMHxS2^fiw5US&9|a2$Q7`Lma`IVM_2HOv8Z-ubFS5bek*FUjh*uNkTo_8u`%s*1<+&vUBsDnWLKlnz^a;>~;u!lEH_K zjN$ZC3ch0mq#AHJ;HPU)uz#OE1$kLR=w^Gcds$2=ZcGjrzwi&&Pm^S|(Kyq#-~rmpFB|J$w+Da;Wg1)nB2;oi?-jqHgi#x#hv1rKY(~=AzfB8JR=5^?ZHSmhm-~>jQo0mFryv9QJ#<*bd7ops&mM3dg(g-ivRZ$k(|>4JrIM zo`X~UvvD<~FD;?_jrwdT?|ZclqT)USwvc=2*c!*Siw-j;C%9a^p*R~iF)gu=i#twt|ZI|Mr_~r?Hos=`2FUq-}AyVCVk2NMP zxNsxd)vj?vJmbLT@XWI>UAC5Z5}6?xOUYI9+1O`+7Mb^`Pdty*tG>54(~EMQ;u`)FRh8 zBd+zT=9n{trH_8_zQ^@$bq0HT8L%G93h8jBhSQxX@#ge1rX%ipJP^m`>jgjW9uMw+ zxbDAF?D$PBd7Sz)#B6sg?c61z$GG0LH$Q_tyO{&QIXh>$9o{fbe;sR++w{_zn|^fO znKOz1e78fRhFJCZa%FDD(7cRc^mmheg-^JR_5ZCg&0SA=2)5fPcm{h%ckVLt=p@_b z`nNrU{bU0knTEL1^&ZMlhSKAyo~~_mOIqucgG1^mx8)Z;sq(W5vc?W`8z;Dp_jJbm zXXNK+WiXQO-FaQ_UPyFeJ6!+OXRu$VheTMryS{s!rKCeNam~Bqn_KqeQ;;&y3;sp7 z!)0e|IpR#`NSu^7@&dQV4$f-Gczhh8Q|Ex2)lZDVV^rXFXl5)wx^2tI9g>}go-ex& zjsKU!8h$&G!N2NueDDnR!E(-PJa4%j2ArwkT3Lwv6=`4Lhi;etXKYE67R~fyw@b}4 zHLNK9SfRY{67hBx*BUoY|10&at|Y$4ZRvf+mfxIN^XB1ow^PU7xSa4?kf!pD+i>}r z8VcxwtnW6k1aLwA(Oq6yWAVlC?6LHGq>~%w+kb1Epih*M*~4+Wf?m09uNvM0bn?H? zZED)v9W9m(-5!1Gwlq3p%OqZ%UiS6fE^jLR+=WlYEZ4fKF@HQ0!r!?KE6&sqXyslD z^sN8j_PFFs4F~1zSaYB6o-rStsiB4rrLRm|+ygwIhor5}N6GTOkKKgzaIST|cb&oB z$$9=XehA&%Om@ez(ZQ21Gjyxl)WUCPt?6zUIzJp#7G)N9&@YWaf^`a4t)` z+@>^dAkJy?soQj@r+3c)Ce9UqsoT8o-#rItTnu;^2K7h+jc-dP4T8| zyBn{k9^P;d)%$MKVCPWIX9>Mb=D8tL9FQ9Q=WeGDFV&X|;diCmvg?d39~2?$Ow1^^ z=etf%eJJPAZ+YKnXMA2(Gu^?xTUdzV|KGnJDTT?^ z9xUwPFZ{>XqtUs;D_>HkWTbTAIvP>M^vWgsSMZ(Jqr{E1dL#|%k#tQTAId&HE5BBU zt9zVJwQGAMrCZ}`wV6GAbp>CGf?6_KS;kb@NHcaWD>ZhoBDXMOY zs-5CwS=a<_R+W_Pv)UBkOOE)MZr4wlJ^g5fe)MA3OIbVpc0cq?zg-u40qN;}yEgP) zq^J6UY&$b5yb!&wu0MNPs2~2nx(!8a(I|z6&=d#Zq^O!uQdjAuTDVD39Z9u7Qq5CT z(-hTMGHQz^WUDi(P8l`#GHQh3SMc?ttn8*bACy9aT&YL@zo(-E zC)EcB;iRaVP*Ot>0l8emxj;}INp(X~T~k!&6xC5O8j2=lYfML1FC%k0I_rdZIy&lv zjOpmkBhN%I9ywJL8hIWfV8GctUyxkY0 zbf=@Y9z9P-Pd)noJssC@QutcCPKv4tB~^$B$Ymnu0zq{obv=?AoTAcG)F8=dDw>e3 zF&%@wjLhjs*9q}-4AKc1(=micJ`KTmI;fh^$mb&h28^GjVZabn$H=oW@)0R2D@A3> z$nQi`?0G%H8@Zi@A!080#Lo1FZcU}D(^S8&@Df}J8sVCh)Nj^R7#d%OQp*--n zIVg{nJbVbMBaey5V|0mI+H!-t?c z^0*Co%uG?!Q`A&R8tTxN4FZz4SBLe+$F`4|z9!n>RT1l5tt z9mr*Fin?7A*$sPaB6Gb&%sILJ?DCk;dF(-S&V#B6<*^SDF#OMX_z+Y_9`_)RMJej; z6tzH7`A)ljuZtg0(50yGOWcdLo>sb~y-3f>Y~SsE>)sUHS1tEn-4!AC!_!)t5_`3{ z*Q4NeG;YxND%TK)qF_H#uzOQL?q~&HLwaq5WBb}s+X1xMOH<&f@7tCz zBl=xVW<=G57#&9hgg=6UukTa`qm^K^B1J71K)-9h6T0{VMJ%8dI=9)r1%B%x1JIxF zv{n}Z^pFS0TqaHoen(p#htFRW>!J93PNL0T?eST~d``j2e5jfbANsW-@S$JdWj<5~ zpU1)H(G;~IMXeJ=WwmQLU6e-=i|A3LM0X>!hMq7GRe-0pIVJY$_JoJXb~^GJ+Mqcz zqjhl@olC)R_}LjGj$VTLe%|?N>_| zDJWtAJ*#u$HMHFTTz$Xm_^PxKUybeCErl^-w)Qf_sp>}Pgi^eEo5xt6(+%@!;fv5>Qtv6F*uf}hA zh-{}Luc4PUXJ+(b97atk*jw=#HA9>IrpM?FX4D*3W<=G57_~(NFuDQ-Gom^eeF#SH zr>I>5sGas}uZs>SVgbFcbK^C%+W^!Np4P`j0PXewnQO?2!F+bb;nRs??T*i2LstFMrjtC%j zJqjj9brAaz#C{N5Bec^Vp!G|NIx4^>X}_CvF&RZHuwRVzb;1C4 zGd!)|i(JD`c))C@Bd@QcXS=?pQ1lb=iQR%W`*)AnaVB;vtW1om2@#u%2p~2S1rwt> zi2V&>Ck59$?R1AO=A($kb<$X0K6+l~+*jTSPwR9MTt2@%_%qj+6XUVg5XK%e<$`3MXwN_*u!YE%lqZdyqupBT>~o< zqiRCLHX#B6tw+Jcs19P4L9CMC+N_vSX$oF7KCLZivoG*yRbg7sz{<3!nh>oI5dpN`M8UME4q6Jd>iAWfUq$^YBG^7c zs}=Se57p~ zB-I2-HS((les!s2^c|Xzt?}5fk(ZGqS_Xx%#r)okY{{;~+ z-~&8h2&!Y`tugYJeszUkweYLvGWcK78ao{=y}{d8V3c&rLetSgkDj06HrJ!)r?|zZ zqY-|_k%XU;$WJ=jaB9EfP@Ec76G|<)B&T-DO^xbEtrJq~;8*SZ>MF^r6q=B;F)1Cq zyv#{yr__fzZdisdzRaqbE%5(oC{SG%EgZeNTE8X06}%+G61>s^Q%6R zNC5WOMEZG&m{ZW_?D81Mc?1!i^Pp-%dDKG$4Bz76Lr@)gT#q~k`&GJM4U$wYMN{l* z8tkQFryFxJ=BKG}vjGh&K z=96c<|Mr5Xb)!FaW#)MlY^NiiVmEjg>}=?w&kcK1u)O&1w|&rN-{`&H<}#zcured6 zCd4QM5rAeO3Vy$(IvCvqMic#Nya2jh`wh{>P!zF%ChFYy24#u?C=;I6%|!rB@c^02 z#EHRI&+&2i45L_6;`7Nun|-s#XEO5{4lDDaYC?SS5CMEfpVDyKzxG?Ei{&U{`7B31?gCn6@Oc29*2*I1*eZ{Y?R4Y?biam7fd2h` z-hJk?f}*dAPwYXo*(*I_4>GZpure{KCPZulB7oS#D3}=4L2NCEtr1)swbP@zcnn1> zE^H=CpALCBZ7^^>4o_=+5nLNQT;_6eV*Gbnn<)5(__Q{o&0g=(TF11WfR$-cH6dEt z5dpNepkP{52d$?->j}TwB*326elO@^2Z~r=PZ;a#83Wi(cv@SEoPW=Fz-*@@udhvK zyS`qe=+DF__7d9cEgrF_nb^y)GBK(qMC?680I@ewFfpow*me-xCb-_$P9NyvLlm*N zwi)Ydhk@%Ocv>$M!L`G~Wv(wL#(!U5A5-uh@oDWwoBe`E>v^WN2Uey<)r4q8u+0i+ z)j+|ts191C0v%MzfJzFe(|+~0U!4?k796b70qcF|Ba@%L99A+QPrdA4^xS(*Xt3p*rXUKqn=jY6et|fT|u)7YUkPZ~#3089R-*qLcILTv0B zngy}3s~h?v4Tk7A-!cqxUcGS;&WoxE<&}*H$m@De2ZHLzs}b^Q5m3zos%bzqmZV0Z z73YagsxBqfB7RcMVVJfP9L5yOp@4IE17SG_ zswR}f9z?*<-{ql0P#rnkiX5f{)Z~Dg6i^c+jZe@TyQ-$dPh+x|hCRtxR1=CNQpkyX ziol!*RTE0&M?}E*zvA&jP#uZPLn3nmYIZ=)3aA+YHBE9k00(P+!1~I(otfjMW6#D| z-Amsroey97W_XvrX*!+%bm{vE$Ft`byYy*`cj>!>c^rW=^Pp-%JpM)mVE7FMU;3yH z9!tPuaX>8$sJjB{PJ!_cTEWUV$rgJg%=NiYgWyZwUB<-TsYw`@zNMVVX$0m(sG3kB z)k<+96;W^^R7WBYA(2%9^ORS(IvlJu0qZYwVpnJfpV&PX~S zB(f!-o(iZZB#SH1WNj^So3h1A#C{5+bf@$Qoe51Te`26J5GT_!%qP8Dl+Zto^6sp0 zNPBCsS=APAR&9pS2F?tFstLj9h6rHL0R_)0)d6D%U_2jC&k2d{umh2v&r9jv^LY=0 zIiJsY^Xc3y@8qHOKmZ;pRTCO&IwD}GeR+fsRL4-?z))Wcs8<5&B^m8?XtLfaaw@*& z4cLCgn75bypUm439MXQP*t}_rH*aq;jG=I57*tIN##lrEgApir-lz^3?*qoJfO#e#dL_ueg_l4_EoN1#k%YGT~z8EtVp4Jxu+{)=h8`1*((o58KI?~B%@AfjaKZ3?* zUcSn>k0_^6urC9EQ~ZlC)6r&s5x}7I$N$fn(F|Cb5mggnbT=XZ&Fv_7I;jpu2f%25 zKz$!j`vPjOU|OiX7wKX#idanh4NQj(O!vUkIuwY#lR9i*ayl}m?+r}*j0^MLILMYz z;KT8eEk&Ds$U}CJk=+X`Bcp0U$R0)nAbS7>BcnQy{RU*e1k_Q1wMP3rqKmaCVqyKF z^W+D+Ck$BY;A#C{WKEs$V3{Y66NBHxj>h4$o?@Md&u0VL?B6{;$C=MYSeXx16XIhd z0{Co3!F;F=J|%)3lrO0M38+(oXsdSJrinlV+ppQ{7E~*1p zZQx1`Dl4eMK@|+TkKVr4-rwkAFN#=VsUSx81$3cO2C;A9Y1IwJ-tsDsnC*1rGtko5 z8Cf{UkL>t4P7wB@7p;91Sj9*79op==9LyYRBKYg8AhC}Mf_)~WJket^L%4W3s2BD@B8 zyv!Bm#9&-K4P4#h;Hph=2gJu!2W@tL4_80NRToyqMb(6GwLk>mYJh@qQ60F30oTx= zx<04|2UWTdyIgx;p^Ga~#1b2dtlSkg!XVZXp4RXpSN#zlG27|LE9`oWoskVTkfp~# z)`|j;h>xr_+U(&TvMff{23AH!)r63BM+6}2fP#@x9msA3vYenA6I3?{uO8a9r!IP- zh~<@|Q{@#_VDRbxMYE`cT}0__+F_&Cd65!5rAtD3dTis;F=0tw+7Xepqd<1lZ4nX?VY8I;V5E>-HNQ-6*j{lHWHrJ^q>{< zvyK@aG27|LD{P9!&d4Sk$R@=>Hi`nzh>z?BwAs@=WYZYgXjmB;RTDxs2@!zoMih*U z>OfW-_o?%OYEDqi7G5`L*U7rL8AU9wc|d@l>&*5|_gf1LUbn#0y0Zwc1s*SRg*h=8 z*PNjIY-l#T-JcD)AA|}i?1K2TrlQTh)1x(?X-$KbX;C#HT6ZA=Xx)Z_X;B@tR$zfG z532iv>fWGQ5>$(Y+1k^IneBAsHFm$T#_l!N z*b+l8j-HwM-EpjsPL zYXsjT+Iy`o)}e^Sw^3)#7q!g>zV-05HWk6Q*~4cpIVT1$x%CFIwT503hu#J{#^(6+ zHloemx<6kvOND6gW;e$IokjiI~-D?_1bLQp(EA5p|IdB<2K z9~evyz|(p^82jMv1CNRAbmUd?R-9FGkOF)VAIc%L+3$N$-eV|-VPz;(O$f>fL;#dy zC>RRW0p$}w*)2r=&`y8q;x81jM0OjiHu;aKzPPJFrptc@Xwp^V*lhBu}|5*?CteCXEy>z?`o0lZd z7-wF{FXs1=%7tiXvvEw$k*W#hxC9Xp=uS=zg6hbzGIFdGQWZn0f+V;UO-SCDol0JU z=Im6|sZf%31y4J(Q-w!5Z5ssJb^7_C+Cnphl-oRnHt}iuj8}`f0zPQ`~~%af(z;D8*M0 z0hw*%%pj^a6 zH*i!=l&T3Ox*HLY-@BY21l5sfBP7}&q%I99B`NOFuAk`QQxvgp3=NR*O#19I({DA! zUWM-OM1KZPt4S#K^3v3x<8uE3 zfZBL~%ro4H!F*c8;d6vywTaK?XSCU^JwC0N&rw*J4^<*rmHH5$R z=CgXlXH*hxc6X0aH)fO!D>I^MLX0XS0vMG?!HlR5Mgzd8Ur6;4KvlHg1-ht;B6bb+ z)A{hHy+H<`3*l*9Qv}c;50JTroEW@@`o!UL5ycu5pHDTk+1Ge{1~Q-OureR2Cd4NV z5x~cfg85J#d`5szR!C)r)R2(M5K6VRcO6~SMG;FW3t73#Xp}*z9z3n=5Z>>I>%|G19@a(dr>QmrR@sTw^o1N_;8_CET!pg{~nh>&9hyY~G zP%tv816cu(<%LvkNR1UZo zYit}`9VqUE__#Wv%^vUJ8ppUg!OFO(nh>u3hyYyOP%tj41J?}Tnif)pA$3bg-7Lfg zXzzi#xCTWmv1!Q4U17Hw#0J6BniayGg0aGG^N86_M_yrt9vb@=1KG`e=GT zp$(#EU~2&sw7CxBqB?L@k91HMMO4*@suEG>N90orTCKmrdYQDQ3(-Xp?^8?Fh+bcG zQ(OglC*2@#_uJ<~yL(yu>ju#mM`$dwa1c(4stF}UTgV{L9L@!T>PRYpq*5ZPW<=GH zj25B^+3JkiQAR0VM&?A;)Co~mb`717v28+-N4^Nbc;r+~Xyhvq0Rxt;Yp9Nq*Tu+d zM^tJ=SrHYM!PAyCRw-xjJRP;Y!P}`ArTZDh(xd0;2$R81%; zXXBW4oC~s}I+ALPq#8z4{fMe389hN6)itN1p_h?49rblWJRS9PLdJA7;gLV-j-09q zjr>JKz<_NYFa*^x@>Ur6l@WD$L|qn9&1CQ|q1CEnPREtr;O)yXN_RRg)1&9 zo{ly;A!9l^@yI_wFdjKo6B_wfh=2j_<^e-c9V73Fk#~=%t0St5jQndf#h%yQy^-5j zV~Cgwda=8BLofcz#>F>??!~!$gYcXSRTIkP5F#Lj?>Gersw0>F$fa*Y^_D~q!ycPR zUoR1J3VNSi9s@X!pAen%plU*S{D}w{{xKdt1l5s82J*NrqOOgoYb2Gw&=h-eU+1M_ zUu(?CHD{O0^_JgOlA@~FhahoCz07>hhcN7Sf@8Y!vJrZ%x>_-HQ`dz3LJBhN0E z9M0upgy&qSnouqgL_i9)I0Xo*BbNf?k{40Al86O+Y$ADHBIcaro?RZ}IFBfza~@Pp zD33;nfZ^BS;X_azc}zhblOt+UL`{%X8f(`kx}Ys?V(&{Q>sjHi0TxEQhgQwtY26x$ zy;>A{6l|v>U-l+>80-nqMK^kBPQeNzAXogM)n#b2Z;i-9t6P{+3s{*ERTE;=9ua`1 zB?>fK zj5vI{P^`J}`E*5_J;&p7JM+03R^~(1g!l|b1n}vPg85J#eC`LIdn0N|L@gFXv_}qH zjV*Cv5#5WF+|Pm!7>H=s9BX+b_UiV4hsbt1@)}yAIWwchaTxK&IuFEWL>uMU%RNTR zm{At2%!sN9G0M}4-++P{Q5}rdfYCz{wMqcxYrg_rj6)F%=pmgOuc37Ypz-ju))oP@ z&I4qwAtwg&Srvy5Z-lchJ|Er)XRXKQ5#}=qM`u1%O^A=P!HsN$Lv`?Z3Vfc3s7(>| zm>@DX!NF3Z9d2R~J%NH_q#5< z{mr}aiShO~?|8)CW@1ku4<<&{gor(-No-+IKu2{D`v}B75M0h4InQff+5#tbIelO( zr#%KP+9k)@T?E%250|-|oEZO|7H_PxCq6CO7RTQ0(fXKa(S|roi>e9HdKVD@=`|F* zzNijb-+u0TA0SxW3g+`*iUgidbCxjrDcd z!1X;mtwTj{9rkdU>&uDp-`Cd<6#Q^}TKmyvAM$7&WLiJM%CxAO5Ut~g09r>-FfFQs z)^X7KHKL9Qu-~=c30?ewA{N-M#`^lh0QM(5trJDA?|*o}Y^NiyuVZJszW$==dj_jH(F{I|sk`4q`t3wR;GvgV;YHc1m!S)=p(~Q5Hoku2aVPO0vAq zE#=^8`K;Lcg(OQJESu}giSggpS9uDaWFbcJ&oLFyX5&X6?(bcmW?JXM%CxAO5Uo^1 z0HhQYyuPRoTGcH)RJT-BOI5Md`Ih@oJq@i^CChxM?&WS*we))=KU9a7hw9MoL-l|C zX4b_PjioLQ!bwpzp`@B40s_fiQdCD$0VI`TshXCmAsJmp8C7>O(ht?WjLg}rsS~2C z>>4^DM6E zbjw21Vd>H9hw6It{1mtNbQJq4jN;U~;!r#(R81(gL5P5iXwN8KX;epQjgeYIOVzhj zJ<01@G$Ci>S#CowFLP4r>$G@M>glwMNom3(Pe(8wIaL!HIc+#%g zKu{gIv_&p$EY(U9nFxDqB5k}x%qeJfc6qepJSHJJ=Rwtk@|cMT82%I-y+q78>3(*3^x-`2L3GZ8stM)s5F%js%Xs(@R7W1yB9Chl$4=f+F_)_ZmGb{M>M`@&3COp4N3%?8+SMQLvqke2NY5FxdT|i#|78N5KZif4`;8 zw(RS?_uF)4v;kITMAd{CZ9xQ}kuA8W4o1VlXqcsj3ZQ4S-?O@)t+-+V4b!>t=k;s@ z5N)nyjVuBv+XG}S6DI~=J%`5OvyEb9$LI4L+U$`YpApPwJFLuystNIV0};SyCklR- zpgQ;zfKQ&KaxFDh5WT5g-_pg~C}I)iAtm=C`ve2gJMgr|Td`--1P_tzbmTRZt2r~H zv2hsD{$19D_>6X;%^vSD8pn*@gOwRkH6cb{A_5rgM!}4z4o0_v(G*Kf7C^Km7yQ1~ z#WyHo0Zq}l@fwy@t8ggPVpUH9fd`q#W#pkmRZT3`;Pa*U94p!zv z)r9yQLj>e~5C!w0I{3^5pW7{UoACKX`~9j5+OR8@&+W*^T|n~?2(Bd_E^|3KG5$NP(iD72d|GADX5Zt{TFkV{ z!pgL$nh>oE5CQA!Tog=;>Y()?Xgy%5Wdf|K_PbCQ7oms+_JFazRvW-*qcv+)k@Ii0 z2h4Ul^7>kKw(F}pMPD7C*u`kGS9!!%GO-%4GBK(qL@bI3AQnKu#HbEp>p<)g!Ii3= z(sWT9MJ%pIjP;d9yagr=`$lZ}4cXXIk}OWm;5C zh*l0FfL0a?rbTtoItE%lTk0oE9kSE`OYIkOv_+Nmt7UC>J~DNrFNgi?5wL%9RvLX2 zJmg@cue%+v=qtDM3m*1{?DN3D{fvFC=0Q+s z0XzHBmWLH9-I&=6IFF|gm-C=%LV4^&1mvMNnu4G@^0)+fTpU%^qUu6P;zcyYCULQs zgthsa`U+g|X6Y6kUA6IvZZ0L2rfnbvkFb_{8pHy$8p$>lRy^+TyLvI?Uq}IP;uR zH6b29A_6ebepkFUsSX}Zz@t%AHHfN9qe=;k184;+Cis+Li8MO3wjs^*eQG90XSQR@eD zVq1IZ*ex+ucVe&5`S8TH@FupoPUk;OY#AKSZdYt#wZ)s*w#=g}oS6qz6XJ0ZB7jFl z6wHI_;L!~{x<*y!sOlJ1?F9yHr8U{v*ws=iUxJF0q0I=ng4;HdSfGq>I89deMDkv$N@ zb?3IfPKoEXuQ#{7J=s$y_n)S@9)@QRE;h~D;!X2)Oy^QKGaafXM5iSp07_$q0zq}q z$p)PfQI!={nNc+)sxkx(Z^D%B%yci}GQ#6x&UBW>!ZV#|%=8dLXJ|0StdHWnTDy5s zHKDv{2O^|Hn=$e7)jJYdX@%vk=K-{njBS=B%=Z}SyPML8cp$%vL|Dd?joL~ zv!X>zA1iz@n-ib$p10_Y(L@~5o?2}2YKymc3mL{FIP>DAYCKN(* z40V1~&5NozGTMb`vhFVO#xmake$=4}ZMY2RIJ-n7M=x4Rg|QaCdVswMmyxrqrFz0Piv3a|fhx#xA@KC9m&`_U51PpZ@ zj}U_D80y0q>guRk8C5HyYI#)MFJpcR4%Q<@&brm!us9@-B}bg6c@bMk3Ed z)zeY+q-3#2yMCgJPf^4^d3gqdr0Xbc=K5R|ck<4kWB(kU*0v}W^aqiw;#4Lqpx9QMpR9R5$yy7G~c1%$)-9O zy$nV#M%4}hbXfcSq>CdcVgbFVbK@uJuNi=j!qa-S2%y(IK;{Z@V({(6jyQaNp;)iQ z=kqJt>{mTLuP~qAU}Zj3O^8ofXCna=%!lgW^A-4f5mlc>)hAK4TPT&&-sN>s0YxmO zFOZeHjP@Fo&V{G-O*Hm%(_W8~?R4a2^qEG@m_9L1q}_3lRiwas<0Cr{ZT2@FvacCg zC0H35RTDy%f(Ter7olKeR0py{Kz1Oi_D9wC!ppB+1G)&Jh~;%ar^>79h`}oaPwS^5 zypDLh%vI&YU|jnRT;IpR6{fgH;^T^-&Hl;5b(nEkure;HCWPxsL;$YFC>R&jf$Jo2 z{TWp!qUv~5{VK#-YVTIMXpJJ4*q_MCU19$i#M;2q`a2r?0q!4 zWWUBib`=HwCqA;aXtV$Jkey;=?Ors!C2(B~sl- zWxcg)A6@iC5zFhGRLT+;_MLvKe5!Y0?*~t-Txu+@@~L!bhSSjs<_dFSFs|fOe(1#^&7gZC&H5?HT=sFaPi|W8t4Y)2$ zRTreH%BiZ75Tk9u;5||o*(hR(U5KpQ6;{I_b^|=Ei&JAC>DBOv*-l4ZVHarZjI6SO ztWq3gV<>Qq_{heh&A!+}R-KXMz{<#|nh>(v5CITwMZw6Z4rCD^3#F<+s!9=Fv{4sa zZ`Z{f6tTQQI#pg_sRpmP@U)_-cBx)%2BVZXjOJ0W)cB0R{9mjOwSVda0_eFj}Tvm+RsI6tRrz8;qJ5j8?$Y zYMhE6aTtu67>t~b%&4BhsBRoa4^pru@foc|o88!B)QB0af|VIjH6cbeB7o5*6wHX~ zVAKPQx}~bFsj73T>L{4DYVU2jcn(D@rf$f}J@tAUn6|^y>XjOM8{XT%tfvJO%C@AK43NvwL~SdNQ&dure~LCWP!AL;y0qAsPhLfh--!2BoTjsj9#5 zdRM#d(#3lyVtEbHsq(3pVeon%p4Q+ZyfQpq=EdEK!MFw*xcbMz^#R4rh>z<-wAq6_ zT-PzKk6>k7R80uiK12W|+AWP&7}bGmEO3oZRijeX$W%2vRSgqp-{}tD>*5C#vCu{% zF?W&OXh7Q!Pb)Vy_5s?B9yHtO$ct>0CePGH8q|gxdRQESKhi;Nj8E_Y+U#79U=9;J z2rCn$YC;76Km-u{83hxhItWey!O5v=QmUGes>TVvKehK?x;Tj<7T;u@Ij^}w1K%ll zTDKO#SLoq0*PIiB=}j_-O)&JhIQ0IeV-&`x_Yd0aTRnQWFul{TGCis$M343v1HGdA zj@=G=x239?!tHh-3=%Ugh*IBMRZ}Ih+RnwjFq(5AQFYAwWtV@ z#U2rJB{?x-fTU9Y#qojAu4wim56D6WLc5{yDxqpZK$;)|Rtas7#z3eJAP)e@vQ%}S zFlnm&Xv;CUH%Af6WSOx_RvJt$gQxXiYV4E5l^zq@>By_(zBsF-1qE0cAIjxuvmf-J ztY9ctz{*glnh+G)qzqZo-f0Yl>VWbHpgb%@I%+4{o(#U7QN$8?*jOd&4I*9OX{}4e z6IXrfbRFGZt~ZD{9b=Y8SL(DrK835%X0P)otYr$c+Zj`!YC;r7A_6kYK*1EK4hk=U z!p>CnLaN%HsKOSRjQrzN^7UsBak z0ra}|dqWp*qKF0bi_V8{=}s7c-h!v~dl5hBwv7ACHTD%G0ujzNTQM(tx%2&quyNo1L5{&(2DwQEGc( zWkys@h|v*5K%o67m=V>%=v*)=pQg&Dxz8DY)_zBIaSTN)pz;9ZK4+|C0Qwc4)_G~T z%8%|6eAQjwvYfR&+8H6bWv%Q6%n3Wh>; zK)D1^E>2U`($s}%>Hgc6%nv^?AR-I(QEI$ z_wK#ktM7Nt?wKKu$m)$4!`A zI$^R~L~%@xT9W(a#;?LCj?0&nZ)8uBqF4&%*oj+2agr6qd?#fL&87|>#8NAW?*I2e zoWQM3QU`HgU>he|LEP5};zT?(g2?~(zY5|sXh0CB;+GLb{{IN#Gz76`!sMz6lPe}n zE)#K_o@4Ky`*i?*6~?g!g*8XR1Ee?}2hqoPInt!pZ;lzY1p>8W7Gfei`B9|BrA65l;Vv$=(T* zH4)1hIqJ;ZuR8oHjHN$cUY?T?DVDRq92?#umJutKa!#5$cusn)P-_3%P#(-}M%1Cq z0NWV0LK!kbc?g~wq2&MjKZJ7N78iboXLlYndzfp-6#e_i6d9f(JMah&NA#|p6P&zZ zPJXc1F-1m+1ciFgsKfs@~Id+#JILmut+}Oo)%1>Hx9v9tJ0!ILRa$H`# zoErpTH;GWJBJ3^^MuPCvxUp?q{e@ip9ugP^`0Ti`hjZ|94(=&|{37(zN`2yUB=bj7egLQ7#^xNhj@S}~|24WiMmCm6i3TPhedy7s|2Mw1&SsVIVqTirs%A7fn5@y8fMYJB~m2@pt; zedU7R%b!d%3eNv&6?_os+h??kkR8YlbX(fLPh+aPudS=Ix2~_Nr)fcp>m=$LQsiS$LZ>sb(Q>+N&l+sFptZyFHSKsT;n5HbZ=ysNpX z9fkz79p*ZOOac__>gi~brA8RgzJTibdRm$~B&nSM?Lgt={=#ytgXL;_^_7n5gF?N} zK|KRzQ?P^VE&tuoa#C21IarR^s}DJY)B)M;#Xk9p~D+akiZbLRJB?=~oE75a7&~-v0JJ*Gl3d zMMdbv`Ut%UkEPy?pm$sA8j|bZ&>5{0F0HY*yV}X_dbQmvobBEs?A{2XO^sX+$fk?E z7LaWyHULzF;#NF%2*tg^rMvCz-sxobKDFKZo$Wp)>}~?lCKQhWvI)f_fNVqYG(bft zp21^>P`oT$dePqQW+%I^sO`S$Z1;U(_Z<*zLh%+LWhi!_gnpp5`=PVlFNEDsos@s6 zR{oW<@?V7VA3?M!)b~zye^uN4&Drjs!tNhV%KuU;cNIHk$o9qN^l4iVZ3;CQkZny3 z1*pi(Va|4U5q3v7Dc@DCd^cz1Q-tz~g~Wn6;RIkd1s(@TSztm+0ok-tbi>uca)pEC zGJEy=IjUzu{eceZ4*+IUu<7=eYaJ~|gyo=vWxu_8ucP{zLVe0XeFB(G!D4onjj7XI zp?;Qw`Z`A)O+rV5gN`gP8y7Q<>K6$0^BvUBbJWo-badFeahRP7LfQb?*g z4<0*=Kt~9dmf71~;$-(owcVqf?Vc>`t_0DhMpgi_Y39cPvJJ&402QG)6^|W4ajtOb zEPK0WI@vu>ZTEa0mKtvTbSH3;RoCRG34zgoZi{N=@Ir$4+o@7 zJwk>7N;EA~d%QhBrxFbjxS~Y61GFnqi73%%u%s4UPz|Gi*|@zoAX~Th1nA`U9s=LW zZAAM3;oEfZ?0l;Qwv}&#jC!sX>bHohn~+L@Nv0QL1I-vjBf@mh!L%QkO?G+#ZRJ&N zr%e-9*luvfoas8`2zslZinJzbbT#lieZz-;2W5|B+?R|v~$&yExLR-O@h20*)3a-neg zJh1GN;T&K#o}DEut35kY;9GfyR&u2|pshd-d@CEurIe@N7JM)lLN= zF9XU=0k*1HLf;0srSsVTeFu-FB-?WT_e3HnmS6KKJ0MRCtK0r1uGeAzEJV@XQmm>fbE=Td$!R1-P<(VMb_>~rR)uBuZT;bPj zfC|6n;IV^WEyAyPAliiTP(U^=Hvn=9Wmez{ms-JXVRwsAVo7`01CQoZf)P4o=@I zoW2`Gn@YG7kg_~{ig};f?)}bo9}{*Tc2fShTKOhtIPf9G_%8U)8zl7y~J6Qgg zN`0ikCAZUR@;=p^CU1n{Kpp&;brfZ2Ff3dknpZedyN*%*PV zJgXF*m8q-`HugUEv$sCkUOS;x02N(iH6BYb*m6mBkZ|b$d%M$}>}qPe%-L>2*o}f{ zQxRc6HWd*BWRv@ZCIKo!k-}q#P|OuB&9b*!=VbR_wcU)f-G#z#3y3zMXa-~xiY7o# z18bwex5`OE+W;y;wFr+LLe(!^?g7!puWn&i-BvmUuJCIKK!smR@z}wy6NF#KfoK!T z0YEk`9}UPUlt&6&;qpp=3YSmBV+WVd7A~I&qK#jt3%lx2o+@yKU*`Z+_;oHGJNUI% zsX1`%QCdJO=tXw}W)tRJ0BuzqW^{2o0kS!_#>Q2Nusqtq@+f=tdpoM1EY$Dopng0s zn}UtCx9oAWTqP`*J6N7-uYQW7dQGVRyMy}uf!P#nn!V*3N6TShIpAQ~XRn?)s-Gd$ zCmqzsf!P!+YG>J)qRkQN>mAh3bkuRE(4jl%I0TrDiw8TZZx!mB9n?2D>gW(G3pZu|qd_vT$joz1&EnK?7-tIalyVt1gUh8c4 z4q^9J5N$$n3m}_N+yuxr6n6qtgyJqdb_m5o!lnD|?cVET_hGf&N1W|GE9^c6qD?5C z0Hh2B-_UqYZTER+yRQhl|8P?Ns#^JL&dNU!%HIXirciG?+5J#$_akS!UkbaQIVt~2 zt^8|e<-ZE$KY?gds2`l{{-(D3yR+TDgx!BTDaT)@R;4|`V~4cgYpj?P77`2RgurYH zybB;@Y7(*&Ae&ao=Y+!YXa~!q?A7n>sD83gzpsP(@xW{fHrC#<$I)_?uw3q7d8)no zDURw76zcbPP(KZrO~GpHEE`iNzfjK{)F0%iBO!D|9dv|&*|->VR9`35rybNM9d%@d zj)U#pm}94ckXe9ia+^>cpkf4Sz+;D|xInlx-`?&#C%X&PcH5lo_6xf`AllSOHz1p4 z-U-My6iWaqLa`K&9YQf6Tsq3$?h#IQk5$_}&e`s1!tTi++JxdnK*~_?!T5Bw-7}o+ zo+s>{?WFvCweky`m9G`bF9Xr0P?tK{U8lCY-r4ST!tT{h%CA=|zrk7gk3#u(g~Wn! z>l|(Psjewr0Y{@c^Me0o*d-%`40Q5l;ULEGhpBocr|r(lC)tnb0n9m2U&Wx1+$b^X&*=Hkq&-kkV~Fy*U=3U5%Y2ET7t2%niVlSwYBk!m>JFuMzlGo*`!U2=jM=XA_q@?5*Esubt3)0d84t z+-bfKkEMccd4T@7aOn|yyAL_p-K4hrgtOiEgx$A6vF8>0^ zDU?46T;cM604iMm6OSES-fp}(JKtu!tzSieocy8!SNOF(K!smJ@z}wyJ%wMpgJ=`V zT>;sIa%VtJE{_nn!sWdHDqP+hj~!edD_nMiXyexyVOO1%qXn+;YaBp@U*qxE!LJJ8 z*HjQ~{F)-{s{NWIaD`u$02O{!;jx2XY2jA_M4Kv(0kUy90?4U~LjqU0JOiM@<(YWw z;Ib}U&VXp+*IZ#&9m?4PSNPQcP~lf29y|EeCH!g!(I%9O0NJ>_5RmQ6uoa+FoaYN% zQJ!vqit;SRV~6q_Ey{BQh&E0y2W0E?Qh-iQ_X}L%^f3SxP7mO*gVU!7r%wdYrV>s7 zq%04g=boyzdz!P|bA;VhPRh?!D?iU!`5K}8QV?wlb+MD(%hh(*I@`TQ*uBz8`L$~0 z*EuVHOelZ2kXW!I_8>5u0^bivS&M|+3n-U(QeyGjO2#?IbHeh|4wj#^SHH7ur<+ttCzv-y{OQHTV@NAs_#9sSH_Sy;k3ZSC7e~rfu z&HWeQ(vS9bzjw0xtJ>~w&UOb)FlTJ83AUm5)83_jJGoQ@m5NXd#$$(23>Pj91<|Hq zYzN4uVGz2b+U^KvyQ75Ny+E|dijjb9T-qIw(;%^{z_)74gzf`S5vtL6>=3Gbh0EhW zwDGG{*j3LU+yYnlH4&h~uSt09;Ma8FR}F|Zp{xRA<8lQcr%;v&T;cNm02MADfX5Cl zhlI<15N-VO3cKo1Y64gI6$YsAD}u)ke%&_5Y@i$FxccWydaHNh!vLYT&vAA1v~hrM z0^nyXLt1mUp-C zFU}lfd~xQ$W_)cmA$QDiEo|zX-!6aqZ_e}%gSHvw+TLKhTtho|+pVT8I(<$B^PT(L zOQ*FKAHpcUS3590`^DOgpIvfOc7A{JVU1n$TKjvOoAAZOTm64?Q+ID)S7*!Qj;7we zmY!@!?~>;1vg*q0%$D|+rrwsUNtn_-f1Yck>u;`6u5EXlK2Us4@rvRzi*G2or({FP zv+mnUJ}SARWP^Ki$y+7=D0$ueO3AD4_e*{)`Ml&?_ZKCfd%i4L@A<0aBhS|*&w9Qo zdD-)A$+@N9mHg%TzGOw|4<*05e=K>!^Ha%Po}Wu@@cdSChI^&^e$QF%cRlOf4|}e0 zpX0g7z0&ig`wq|7?k7DzxWDnN@SN_s-1AS*wVqo_H+bIiJmq<)^hM8UrLTJ4FMZE* zUFip&mrB3#Tv+;xXH)6FJsV4pEnQQ3a_RY{rK^qtZVOW!U1ymVj~ak&QVv`g_AcXwa^@x#^+`+nFD z!+st%P<(9h@rb|)#U~b@RD3cbv8wni#N@o<^NTMmzNC0f@#V#9i`NyeFTS$)s^V*k zuP?r#_@?3w#kUvVQG8eNJ;nDIKUn-w@x#TB7H=wkqWH<;r;DE{ey;fW;unfvDt@{6 z)#5jb-!6Wy`2FG!i$5y+&sJ;{BF`!x3% z?p5xy+~>N_b6?=T(0!5nV)v!))$TR!%iZhT>)ltnuXbPKzR`V?dxQH{_nq!%-LJY| zcfaZW!2OZ?6ZdECFWg_czjlA?{=xmbdxd8u>fYiMo2$^StK;&x@XyJ+FG+K<&NjdC&8K=OfQ29%PE=E6+Ec z?>#?ze)0T<8veucZ_i(zV@p?*t}HzXb$CkYX{BeBu0k!Ii~78<^y1P>QJZT@*P=ex zqb{#1y{7cK(i=)|D!m2udVA@esN0RG_4`r3524l{E8SH3BeN+($Uy$dlCJhC9rInhUFM!lncvgW z+_$6!572W!iX6@VS@1KZxvkyPy1;nGB?pmHIkn)&;4El2o(;n1AoBBs0s{WW;Iwrb zkBbb>R%&vbmSqNKu)%rt4M4?|Dya^nfUUkSD@o-4t|KMf9g3I4M!{u@M2;cgZD za3A)ot}ZKRaKR>96NM-9z)`qzjDE;AGFl| zdE2ln-?%<;!zHiYSu(cnk<(UE*Dk}hb#ZL=3Dkui+4zy;%^&b+PuemJ+mFb_As=(j zI~|55tJt3QDYwqdl?P~2Sp54~l-_%}Q*VjM4tt(qTwQO3}*VWO{-`Uo;JUiQ$t?%k; z@69Ia@XxZ!Ddp3qR7@?asL0N1>&%9`di&JSyTY@{eDIs!*6y0z z%EzqD-#+%>RwLAwBbYfLnIl$HPxHcTT{nK^J`+vd-EEx<$_-|ghYjPkAPNLp5IaG)Lmb)eg+xk-T76tn|p&<8fe^Xx* z{@wL|992!n8+-ej`q~OdS;K$R^R9V|U~c~Z(VXodKDni*r>m!@rMs)AZ+dqR5}?nu zQ*hK?^D0TI0hLmYblGLpz$5*xQ<2#GXXNZ1(3y?g*Tp{v24l8^-xH0`Nx5f3a?b|( zjNd!28i{P0)7Ck^YiVzBtgWv%TQ)Tt>1=NApWlLiPMJETynO0Z{Lc0__w;3(yU-!_ z^dT_Ftj6Z9&epaCQx>{LkT*B4I^xZA^pBzQf0^!?_~xfOpZVV@UTSDIR6dxl+25yc z{~ucQ&Vhp;Teo!Q^#4w!rRm|de>`^JQGxHjjD9lhoy~vjx${}>|Ekm-Egj9>%Nu(Q z_lmOaN7r28PG7YDzSquP|J&l7CwTrVr6_R^Zv{Mx`&=;p(PMv}vEn}mgs!{ss-gef z`ON>FqmrsM%Z8s`K0Q@&_ok6`k3JRp8+9$rmL7Caqfcv`S|0Vse6esOp|wucT*qzW zDk6i5OI-sO@b|o^tIZ-tV)1A+lt^l=WeVaVix~4p1BoC@X|3f7;$aps9*LyWfk0Yo ztxyo#En+&HNQHcnh}K%EAa+>9R4N$^`V&#DwMs$kw1|mdI>H!>X|2@?VwXisCQ^RC zHxSoaYZSz8ix`ZDI;^z!zfPL?WoQPE!zj1hK-8K>EEQl)B8Unj&5` z7w4*`*JAqo%*U7y#V#}JMrQU|%!n@?^ruklGP7=EV!uW7di{ZrFNSiLnUy0mmsreT zDjZA)LP(%8vvy?WQi~Y~hf;~4k7tlsJu-8d#SA3^{%9zL6e=_8M`kX!nBibB5(~$W zLuFma<=JSGSR*}p+(qj4}$fL9$%yLx~9c3|n z-asIp3d4H2s)~-bn6Xeam5lpAR8`S27SZbu`;v*Y4@^}R4Oq-z!tW2n{7AWSRTUj; zF#|zgBpeSTi_2A2bezQur5L#JFqo<;I^JT2!`_rPnht@fs-hJZGtD9)7W5;J%T-l$ zg2hZlqe*`tjJ8p(s-l$^(+_4U$Y8xfRYfOSOdqT#0|At%LRCd4Sj4I%aF#Essf#15rdI<${&g#MwO}pooO*cu}CBsV92>jRe@Gn%yfXo!_f%3 zno3oH&a#;Pq?bjbaRk0fRiLviX4)4@$Ni}EDpi5bv53KFI1x<55%(%pfzGvxcQg;VGet5pTMz+xstED#K#o2yn8=t4oP zjQUgYs4;3ZH=8;K^I_wX5ypsqkwuNf(kx~S8_msT#>>=;Eo#i0Os0*2qq*61K&D<| zQR9(BC}E5o&CO=NBvUUH)bfx&8BawbXz$&Mp>VZDjAG18B;#>yfmtMZl5&|vM28el zC(5z}yyMdE2~ftg4$ zah*j>rM+Q)G@a5Gm|d()TyGIE2*yG&e^OguCY(&X!XhS4U32lMd!OFxdEn+m1 zPNi7ftF@`(c$GzrcvHcoH_fy*RUEIjh_P5A67l){TAM14*I2~3Kk1KS#M0VSalF}j zBVlhesExxpf)V?iWtFr~Gt0(q-NO!))8WXPM=+EszP%_1fup>!meOla+@guLA% zCcWW6JP=K4?W&01VG*MVGzFAg>r%z>PKy``h9a?Kz^8So;&_)ujHLp>bSmQ2x>Rwz z+akshnnXImv@TT~H(JDW#G4LASy<~*#ql1CnDVkfC=v*1U8*?VYY~%vzmLTd0j*0F zp8G6fIEukG>h)>8-HHzKenBil=EQwzbUw@TJj%QL{dO_B{09WDA{@YEEEq{@%aj@Z zfnZhzy*`Xgp|I98f4<;u!?ivkp;E z$z+VP^A5``{WHOw7K%oaAx!tQruMc4ouK#R`P*~N_vAExF8FaR9!n?V>44u7XwORw z{LhkOTn#9q+%g&5d99goyzciCCHU&wCc1UgCQs9eUPi= zYeB8>rqWTYh!dQuh{rdASrZEey#XH@VpC5~({iyqljHoY#ZLI*(V*WK$+5+BS!RDH z*wukxB+bIS4!Le~?j$G2_kvuO!ZIlp@CCJbd57hc|3UC7QbEjYvEaxa=&G=hp~HOa{ z2ySJ>4__m26`fHtppA^tWu*I5lrycK1)gtnvDz zEaFSXwPv0M$_)R@VxvcmME#gj8Ej>SyL5B6tvcnyriwoi$+1-#P6W9k8u3Pgd|}kA z%v>s%)iJ*>98X{$qGkSq7U8kna0Ur-O%!Ry{Md%ck9kzLVS-!}4`CA`h_Qn^T`PQ+-Pl2}tCOi{0Q;&Okz$8g(fjOg=m zPLwa9JU;IxBq~#B>?-@veYRSIqud|uE~vF}>@oUSiaU)Vx2w;btIA2YhoDbOCc~jP zQ=g1}fo1j-EeZCYH+^8Y+WvZGVCAhV*a3B#6 zCb4q_Zp&h&>U}JFg2e){0H(e_f=2P(3qRM4wZ!Du|r@^Mr(xUm*D8IEDk0Xq}i6IG^+v$&~v%8NNG_ABSN zEm2kdc#E4%1Ot(900|DR%7+OSH-#giR1iZc=c;_zS8%I?et!%#iJj2-9sTX5V!5ZB zD9BZ*H1-1{m|C^Y@9Sz)^nQ~pZV0_(lwrooxu#yZ$xODmSeAy;zA*9{T$RI9EN(o3 zx@73^ws32|RIisrIV>V)M`lu6`Z zBogy8bWogZ`Ye;nEpj5n{Mb@M`4;x}&okYS$rTdWA7Q?D3^l^ZD$SLGT!pDyFz(}H zOj}=1rjiFP%zaTXWk>iHQEPjD@4}_|>XXUS1-T}LUAc5D49y)aO`W3m zk}G?E!LCa9qp@HjjVO0?Dcjxw7B?Nh20|=_R0dZSxW5bTG_(-x1Yx1VxjmSxm@5Ez z;5yLa2Lo}O7v=rvS*+$CWbu6|42=G0&hMUHHD43_+ORJjLqC)A9sZc^$lWfp=-!|| z8A$MMhP%I5N%vaxc-kL`1QPku_A2Q5C^BKh!py5sOTj9<}J+SSk_52~FM^B|T=*u@($s?*-i^*WRn7 z#|6D6j)U_k5;^aTSyH(%B`h{ZkRcrXg}7$OZ=^W zB%Mg|VHpBu|0{=Rw%{f-e=La2;ykw?M8o)|!^YgE!yHK>j@_>WrtdlR1u>FE<_eLj zBw7jDI`2iSIfd-d!4@|K?SZI27avvqW(2o76$<(iSX61Pe7n&ssXQJWB9U<>8em=w zVVrDgmdRN`t_p{e4ChJkqSKlu$R6v0Tg^}LF!Mz`I9H{(L6ED`p^%>$U0!F)0@Gtz zaihgec$1+N4sM{hWr1p(In?4}s~AUWQFLA4nm)*Sn*`Cn#xPS`GQ&%!HSOI4u?TC)yginSlj@^dMh48 zvy|3~GPhN5t3zmzfnXei5a*hT<%(V)$W@_u5O*o~B#$rq@(#<27Yc55D3FMzaSWT| zsuZ^ga-}!qL)G!I2d^I}0#akuYh#fFwhjs&$u`RT22bdxIQ&|*QY@h7p;58+U?wY#ZVy#v`}v4gR&Hy!4a zP0kj}JlX4B!N$Vfj{}4#%E;NRZRX-a_PS5dYm(t4zaNMQcB6k01C6Y_U$AR^ff%?k zge1o{%PA{gBIq@7Y(rw}6lu!oO3#-Hc5NgYi+O`-RDF)EQoc;kYf|Xya5oL9%IVeS z*`4h9a*OTt#*)!6pOu8sPA-eiJrXyn)` z$Bz{Bnn(y!o@fY(!s*JW93|Mb{*=!fN8XxjmGYwn9ovARU?}B<^2O?<)G-z}5KhFs zjCW7qsuscn7B`Kv!c>fJtAK0zAh-5oEv`4<#f^bLPOq7NGWR&at-<{|U&7CC?e(@d z^(rHMyv6oMLa`){R+=vD}JH3A(-#rR0n+uklz%U$XT78zBZz(EG46d()DGI^y% z4rA4YHpVqelNFhKqD2m3CoP5C19@>zpE-KU#7WlTWtDL0q;B zCHc-JC!4h*lTWe8F%%A`T0C|=P0DDTYLOF(XbAgmTysy8G8(4|a#hHW^)2qka(Z_yPi4GcDv$oM&-Em@0)Bj>0%s)&9=6xc*4Oi%okT32RSB)_Z})#Zdsi zUTjcRE?j6)vHteqgn@^_+WnE$USx5Tm^rf)?=F^EvoD!@vEWvRR=0IJjnA2Wk zQB&b4j?of6PBk~`WUbd))Fh@tK`(Y?+voSI9JtP+`fz0_9>pm(s454p7t{*u{NM%_ z50u$%K4A{D(Jp_9+tJM!~HP2ZHbwTJciLyr!N!Sx$hP1i2=Nd)LVn z?rdUP1N+#f8}dZyX2GuTCB0D`y;h8MKEg;>1Z^@ZyxaN5^KXx*1JKltAi=b zdAt$0%-QDVitO^Of?VT`L?gaHByEtb?J`;QZGv5mqdvTP5Q^v6D%H13WN(Nc5Csjg z*lv>jxI>VuuvQ3!v3FyTO~rC2a;M>@gOQQR*pUFo;!~^tx zGdX4Y-GW|;eT$%vH#p2r%o>#Qc%z_Jgm7~o@6<%J&MwvUnR^7YGKG~^B8k4Nt4G{S zl9k>os8y-BKZx}-F6s4Hx0vKe+$XpdUMvg|34^Ohq5B21Jecxh!irg!=*{JB`n*R3u_hexMQ{|~(}H^KQLRfJ72L{LDw;^}_YHbl`pk04_8+sTfdsY? zahYE0ZCYY#m8p*lYIWKd@G|C&X}vgU6IClG`6fZG3Z^2-SQ-NaC!4t?SM3vmTbYbR zk_k+FIW=FkvI|cNW>qABQ;z@+@OoSN7OJK~PYG^q5GPA`eTiwfZPbUC8O=JA+rra= zUK!+5PTryQwl#Gqym&^UGHg@eez}GvfLS!z;b#T40%s|Bg$c_AP!(DGoM2Y-l0_3S zL>G-w8QtdvxiX2FsUJTES>fzvi<-h(D2Cfy8fNG!XI~K1iU{tgV3LOr^q6-c%26rz#@wl3-TFQn*Tx3~Rl8*61T=%*%pWfx}22 zc19wct5Eui#l&t>1eJvf5KAh#Os@)Nxi=Y%;dBRSXf_$S+jvb7D{!4U$x^uX)7xhb z)3VCfEoQ=(O5&|F)Tvma$;>w_Ccoe6#XE*zn(>sGZwh8r22(;VL!2t~%8mOSL9RfWFw9ufoU91{yMkGXOA!2q z0K8q=WR4rM2k!|gZndQG+6H=}KJ3#p<2x4en&tNTzMxm5-^39QHav3lJXv=513@lJ z2l0ZS7iVi`)ykJdKNP&$I6nu%EJ*7!qO0`bBSFV~0!%>g%2uAP@Zn>N9QC5j25~}$ zSMb%{=O==U^&z&UvEgBm&8m}Y`BTBI#Lh?r>&_fE?}HrU&jhvFhc|L!QCtP;x9em+ z7i3JuuqX=QbrMcqCc0aBzVwA)R|aEAZvwlD23z69mx78d;Y2Em`%xOcen4DllneKj z;8q9t-A5L~3I-?WE#??0SM%2v8K-g#C&pMBak9BIkjdXzWL%*MVHJTj7bmOMJKqX& zc_6`};3l-C=Db+$9KI98DqMxd&311@TPDq^{ z2C-$pm%qvu`lBFMVqSwcFYxw^v{sgL;wM3^3S-aM8^HY_ENO*W+2fxDx59^R&!5I^ zJZq&acT>MuOw_S2jonT@1<7ZF%=}d_E0Mk7U<8*x!8At*+0|_u%xkli$tbpjLb&U_ zs9)rbOdTSqwaFN|GatIXg-t#47xy=rnIrcm+X*`6jJU~(ZFy~p`5viUzuOC9Mbe*+ z8}FtrX){wsF4s`Oti&D~Ug|^h0n^-+lARr9QDbqOg5oVWPOVV1ogDE8>1{I+Z~0)ZStqz{=$+wwP(`Vq^C>jLEGk z0%I&@$eZ#7`P;cTwNvCkiC~uF>>?RVqhiHrk{o`wM2zCPJrWyk<~7Phk3_`rLkMec zP3+;z#8QjsP2&|1yd|nFFv~3y$67>8(2ycb6KzE1jgxpOZ0up&MTZ;HjkJu6)O#hntfoy)wbf>(jnBX)|h zF6|e!CnsZ>#Ej#O)MP5I^^1g%ndO369*+3&z8oJ>O(*3bR#-&b!%E;tFA0^36sxp| zp?D&Vg%;kxQ)#TSh=CZx%YS%Zx!;VVY`R(y%TfvKI4~@4%v6-)Q)BUP?;JO}a7txv z>B&4Mc;(2OG?sU1?VzbzZ_Ab02lK=XdZhUV_ zUu$DmcVAmqXD`0tZ}5;}muq0R5iZxM{2v1@{1gqW(uj+kHT=4End?feG3l1_X_e*d<(SOadQEOXa*7Hi`_NAdAV-;ewZP!Hr3L;4eVB_BMh_k#Jn_AVaWoD}&P^ zx0=h%N#kR}IG1a$T-E30Vg+)tMJ{<6mz+KWACE%vZv~RmNAo7NRm=B5Yz-IdIs_lv zA#tphxc6wZL|II>#|1Cvf`4Z5@nM1BSO^{}3(8f&1=n)H)A0ph1NS27EQ@6joLW?8xt`0__2J`J$XP9)%k4bIX!%>kB?^02aJjk1 z;p3IR%MJfs$c>WaL_c~kq^{&royX(jlmkUu+Ib8aK7Nb~eN4_$fy7l@qGkm?wmZn> zD$OMddI@f)(y+6Yd$VEaYAzNz0UzrjmT$D&P)wGQgTV`R4VQXlB|eVSn@&+!s!^V-OQ!@SK;GQG+8Sx-zp))f0v}> zaB{g@xZK-U4RvpK%#q2-w)u zvY@fEse^wD@ZcdX5HH%v<+^Jk{^7a@A8%*yO?`(N0cp*W;fI)F3tIXb+d6wY8{6i) zj@x!H1W_JH-pwWN<&t~xo@EqS$W0F3CqpVSv^qmJWw(DOONSq7>M?X|Wq%{rl6e>( zk3vhiVV}O2CBNx(c#A2zpr@<9du!kC;j)7s#YYvos2#a|N~dPX;06r7rff%3H!nHP zQ(AhAfN}qqVKlp)OW(w$7eRUiw@k>$20HvOS(JM%#8yJ=7A|)5WB9lZVtaF=gigp1 z_&mH*mW=p(LhvLA-o^zNJdTg|AvjV9?gMWZ%Yyg zMm9F`uYNRU;4O{aT?j}^PcQWCh$0yJ2L30?5Lc3`pFItioznr7Kos#cSeR807yCMT zE6S%fS642B=HE?E!*6qPYN-g4OHre?}fyASvkJmQGvTzo~i<;`Ru zD<#Ref3BqW8K7_G(a=m3CsJ4L8aT(SjN<{%wNjuQm`H(_H9O+0lKL@l( zvKg$K=_{Ary%~h%hHM(5)yN$YJ&Nc}pNr_tZ|Q5om$bSDmY9(%RXrZ!+LX&Q-W)77 zDOh++3Mb;iagk=*0e?~mvShs^I|KQ2$;igGu6g~fu)j+#Cx*DD7#_!G)rIFs?7N`p zb;**C$t4{HRF@)HBSny7L7qgj60_nyUqPB~CPQ2wNm>K`P@tkbo|K9(9^&KWC?`_0 zXU@n-j1Cm!)q_JVeGz{npY^QHMRJJibfYAwl`^RyyTjy(lD>Gx$HO8*_AKn}ZZxU- zU_pwlf#7mUFgUk9HA5170D|9GF$hQGG};efHeXQQ%>>J;rRKg9(CK;9=W9eAH^u|- zdFOn0G76?IGYSKnate;amw&cqJ?2=}i0&QBYJ5Ft(ZB%4rhzf8fpd}NBL;3kbB}6s zV;YHTB%zU{Mp7C{Yh;E-W@@BPBlQ}YrIFbhnWK@p8aY@a8I2sGk*r2^jWlSaQ6qC{MD5S|M*20f zL?cTzvP>h(HFCH{j?l=F8aYZMM{DF5jSOhySdAQ~k>fS8LL(<=WTi$<)W}I1Iawp8 zXyjCloTib}HFAbV&eRAt3eM8V*%~=VBj;-5JdK>Mkqb0(p++v!$i*7DL?f4KWVJ>v z)5sc)T&|I|8d(R2v$QQs7iH;TS=yeZ9a-9$rCnLtou!Mjv?oh@v$QWu`?GXOmM+cG zWm&pBOApV|BeL|!EIleqkIvF#vUDIzkImBKvh?^YU6G|HWa-K*Juyp9%F>gw^pq?; zHA_#+($ll_j4VAfOIKy-Sy_5^mY$QP=Vs}7S$ck!UXZ01X6Z#)dU2LslBJhs>FO-K zEKAp9>E&6vHcQuK>G~|aB1^B#(yOxc>MXq`ORvq+>$3FvEWII1Z_Lu0vh?OGy(LRG zWa+J0dRvy>o~3tW>77}6SC-zLr5m&Ko-DmLOYh6l`?K_cEFI$NlQXiiR?5f;$jIk& z9Y<)3v26~Zu#t?sC1%hBM6dQDpckYjGBY5ztlf~sQLBN#oakk@hhRlv1DF+;8o(~- zF8_|NSHkvFV{P((1lwEjbcpMXyc7A(Uh3F$wS^m6yP`mnNgp@_#(G)%5E6xYS$+!>*H zM@W9n>%oU_MJ?!#`XSRU*B_S?a}z$24l{bOnXI74Jr4@USgvAP)+l?rJ>Zlz;>(r$ zI-tdJAu#8V3vnk*-kaCVhxSNvHj77Oh6{{8c`@q(_2Gy-e4hy2odvql4Mi{Fg~?pn1sc<0DtmTUZBep)9w& z5tB*cXo)*S{Ur@p0VB`y_8iLGQC&z+E>o*z46imhs06sa7=f@%@rSeF`iArU_ zoiiRTk;);6KP;(7>yprIfc}U3%?EmP03ymO0sPAZFawYvK0Aw;^M`_>{sX>z&V{_` zOlRQ)d@+Ou%%+M=5{9;e%tWhrJpX6&8I?KI@&>oW5ab<0S+(5$|H4G$>w}GzTSsS0 z2kLd3TsJhtbvGA@`wLnqgR1YidzdQ~_`M9yHSrQ*dRsV+{SqSYa#aA51u_eOJj)T@ z=_WG;*eqZ}3hJbu_gkV)60o-*UuI+SQI7eU=qmmO^i-q7bu(ERrX?a)yF%|L9Kmby zh4Z#fAme0<+$+C4DQm|c<=CgegD-Ds>TSdqHOf;H7q-s%)I{e~lQDa1BSvXtAB~LG zNU=u7Xrx3VZjE>}QmT=$8X2dN@fw++k$p8XQ6rPUY@o#rbW8&+X`t=~>S>^*4RmY+ z9oIm|H_!14RNZ36K&mWWoXQ2%hOxueP-h+&kH;{s?dJ@>7 zR##YoWuxc`i=p@yNpW4h-1vS0dWnScT9v$gAMiyo?2pvR-P60kOC&tV>wHFBuJi?< zcnTYrJc*Yo~cpuxyw*;(YyBD$~7c8U064Bzdut~PdSE6#c_~<($r*>Anc5YcU zle>>M(P$4E+1qw_3tt?#UAz;HStA@22}>_SQHyLT-ylSVUI*Dd3`_7Kj+Kfed^xcF zWML$O;mj;4#(f~IF%;w$55n|#nEpWOHggLhNpdVC50TYl3L@t!H@{iJ(X~j@yd~pr zco;oSK{kC2;0x}MF;x@p^x*L^a*yHjRY+Y%C5-JN8N=6pB+{}sbGf%hIrAGILi5K! zjx~^60R+Hj9v|d7^Ca)h`=r<|g3$d^bkH-)4Uq!=rvw{&6*CGZbq9hnk_Vu!K3ouh zwJ>`LH;cIn-n;hu5jNqI2U3?yVW`7qh3GeD0UU0qoEe{6&>vrb+3FVuH}~Tza0l{k zeq(;L*ufkvTs#2A5Qvqouy!&O4w9pa#xHj#Vc_*Lo=ya2hOkZ)`FRl-8Kat$shL=6 z%Tuh6P*5gICsXxha-H!Z_;V?Wrhh^^-(%SzX(;F&enm4YLA`af@SYz1`}H`-!_QFH zXvNbZu3dAL;V)ccuZEMFksZ8qi3c)pP{ijc*q>m4k-}B*tpFb902c~n3W}YC#={LE zGg?9)?~Ytjd3f5$@eV+(*K(#{rNeiWwv}Zuw8*k?;AN()pReepg4~0s?3T&RBaB#` zWyWd;#nU0K3#Al{%R@IG*mpCm!1YjlL4R}^uw7*j^E*1CIuCXgO~|--jg@0B+nlN1 z2v?p(FNto!npw$hu?Nr$Yy2szlE$B%P_TNweT6@RgA`b2Zp3s*1qfDDN{y%l+8T|F z-6~-}NA=9)5H=rCu`{*^;#+|0b1+Z@xS-nK0XjODVg*g}8a!VuMP+87u0AzWZbKi! zBWBjz%y>o~Af86~HuIgPB+qlc*L1O2#JQ5vU>fU-ih`}c)zEr`p_OB0@+^xF_7@w_ zT(nv#P22#^Ho7LfhFegIy`k-9$zWZ*SLy|R2Ktp%L*a-#Mc|G2R&Fis$Ck0&LF^B6 z2TMwW=%D3cmM7FJd7Q7S#rjU{qw=h|C8xV?PJ!-eq-fDt7yj5yXM0Ph>m-W5>xkf; zgSE`_#axOS<;O||ZAi4wQvn=i0J(XY0C)ix6{HkODEj5mK%dR!ZYZ$jy1?kPvDsdF#84q6g2$d{Yaxpaay#A` zljZ%)$#U!eFj=0gktrJ4Pa{(`Ql^n|jZ|o)QX^Fwsn$r1Mrt)OO(WAavcEEco=r^E88)Bj{i$vHK_Lj(gR$(G2@^2y} zpAq?2IFYFbc9LWh->m9o@0Ia z@8pk-669xR76K!G*T zx$e#vqHsld1LjN*OvccG%VCYZhqZO{Z~R0bu}f~wG}LvEJvhYmS}xw0Fcil7P}uuc zE-5B>a%-;uelYiEE@tac=uN}8~ zHpF$ZqzTD^Ig>n%e;&3vrN9I$U`I47H_+E4SFx!g3-eu!xGXFW2?XGNxftLp___Nc zdUpf*o8(q*RU495wN0Rm+LBUNK$!+sCNy!p`<; zNL|N0j{9d6PLV5scqM(oTsnyQI1w7VWgHV6IZ$^14_dPW^sr+4fbY&V7l_W7S!87^*ZvBR6Y{3T}Ke6RQgV^%b23stqq zEgn}<*L;`rFW&VTYc+msD&lbxpl>*2931pW$PyqOvSuWRJkR5+srdysvOq2c-!`k4 z>MmF-HPh_?PM4)|)FF=!#{ge03s=d~d~^D0?lm^d3OdcH06yhWpXonXDoYmv{#Ra` zIg%xfeHjrWKO|R3216B+x6=T=!POe84>?Nnp!r*?nS>({6AguXQ^vEY9v$WuN80y5 za0esP__lyN!9Jf9P0hI4=9lNM{p2RW*I>c584E7#Qt=UvU$907t}@pZd&{xp1FFBE z_CEpetmHReZxxJoJHd~y<#a;z%1xsT3a*e8)P-l&`%`n|>k40h zGTtzrUs(w28-PS4;h<437|BJdo&iRe%s|VO+s^I4FO~3_vTq*%yhZ}+jE+vy{tXBh z8g0v8*tYmt;cCO>+;tn_@mO?>U&V0+sj;`WC3o)niJ6x#b4~cNG@q~VR*4Q}EFZ#f zBw62>#teUzxeVevbs@tPPvwkU(=PyeatfQ7Fm77SoQAtZ=m?G5R53uSq@o$JQpsKc zK0jCC#(g1C0AA!i1HhNj#exx}slfgN>>;BN{CLZ}3KT&*e1os>XXY=-iIx7@DD?8|=G*y&!HAV*!!Sex(GJxFnr2wu1FiVOZYFNZ>H(&=!MZ=^D4 zr|rD%AC~;*DIitOHi+a*spxP}6n$q`QFX@E+|}RNhbwx$ZGCM^T54S@X_0YoyauDg z3&wU_oYztQ9-iE8UV-jACDT}P$i49&@NBG69egz|SJcfwj*?5{cJMX81bq_x0uO{Mgx8cGnt}yx1RL$ii_d7f(F5T*_id*Cl!YG9cI(y zldH9oznBLIXJ^CN&+-_b2Z;HQke&oaYpyuCeQ%MM-vQY<*8mDP#4drsw{xkJEXbV} z07n|Sa+`T_aQH^gT*=E|8G3l(=MJ#7cR4z_>Pn-Vn_G@n@S)ky@nuSHPA|Hvg5BJI z1Nv}_0vgBUqJZPTsF!jK1Fy)jU4iYJm(KSr7#gLng(v9WrMTxVJEB}d{c%w7r{n2InzM+6-lYH;I|1r&W$8kcNUH$9T2+K7_Vl|WCs^S zqa3|-b^adU*_61$edrV+w%zgUIyv;MfsUuugAW($b8tso`5JjeX0zTj1p$IWLE}?vu+}+#JH6Motxp41khC3s<#dqB0aIS&c#d*8N zy^Tt_FB$79I@j&uM=hOQc!?pmnplCp>{JbX2?@Id8r>UuBhF=~a+ zOytWN-I(|A8OnKlhB7dPx?J~Y1ACBrHFBRu?$^iz8hKD74{79KjXa`}M>X=8MjqG5 zCXGCykta3slt!M`$TJ#wRwK`8ZF|s!!e`916Bl|Einvr5g#xPRCh?@})Bc+UtWn>&9;~AO2$i9qBWMmQ} zlNp)9$bO7WWu%Oeaz-i`sbr*zk!nV27^!7s8Y9yg*`JXE82LLR2QqRHBN`)&5icV? zM*NHf7zr{GVkFE+gpnvCF-GEyBp69Dl42yy$P7kiGE&D#JtMOina#)?M&>edFe4d8 z4q+tAh|Wj@BaMt4%19F<^B8GnWIiJ;jI=VcfRTlav@x=Xk;52iXQYFXPDZ*I>1Jdx zBR!1tGSbILKO;*RS<1*VMwT;jI3q_eawH>1F>*8`$1pO$$gzwZ$H?)FtYG8>MpiO% zA|od;axx>QFmfs*r!jImBWEyjCL^mDIg63A899fMa~V00k@Fe3fRPIsxrmXA8M%a! zOBq?s$YqSIVdQc~)-tk=k@bvR!N`@2T*b)Mj9kOWwTxWH$n}iez{rh^+{DPujNHP= z21agW?quXHM($>0BO~`PaxWwIF>*g64>0l|BM&k1Fe8sJ@+c#ZG4ePg zn;3b5ktZ2>ijk)od4`c^8F`M8=NZ||$P0|T$jAp-`eBxSl%*eM=_gtGX_kJLrJrZ% z7g_pcmVT9`UuWqzS^903ewU@+XXy`F`eT;0epu(kam?)#)Ie7U^`bPPftNwmKc6)9rM+y-tVfbeK+ez^g?%-BG6_ zbh?vHch>1HI^9*LyXkayo$jI2kviQ|r+eviZ=L>4r=xVbk4{JHv{ApIhsMAS0ovhO-I^9pFQ*~OV({i0w=(JL&RXVNKX^l>6bvjL_ z({;MPP7l!O-*tMRP7l(lrc*rNG@;X^PE$Hf z>vV=rXX><0r}a9WrPJ9uoukvaIz3pY8J!-Y)2vQ)oi^ySQKyIMv`MG)blR-b`8sXU zX{$~b=yah@+jP1}r-$jZU8fy7?bKqSe+iH)8lozLZ>I_bfr#D)agk&Jz1xx==4;bo~F~&b$W(Q z&(!HEot~xBvvqooPS4fpc{)8`rx)n-LY-cu(~EU_iB2!o>1v%`rqeY#yvejCPOsGIRXV*|r`PE8TAf~})9ZD5gHCVM=}kJlS*N$?bc0TB)#+_IyI(=2Auj%x4oxY*dH+A}!PT$t)J34(= zr|;?XeVu-w(+_p}kxoC>=_fkGXS@{-Dzz zb^4P|f7a?+L?tTPUlRZ;bIR%1L}G zQqL-+vHT7wnf zTq*E!DUf&aGrKJ(cCElplyrvV_4fe)7s}4_*Ky>9#f`3_AMiZ}Hmk{kwdCuV*bH%< zFKNSWM!~H7E#SoxZk*=SVJ<37)>^>1+Ndf&ZXfkXH9QrwwR`f@BR&^GBzcJOgLRoy zz+k0Z!tp?_kkFJ2&I0H%rnUIfB9f_-QR@#I@!Vpm6otS@V=5^YSYrOZ7FfW*cpfDS zE+p~8vzT1+!Z+vmn&5at)I7iwT6rURFYmv(c1DAc=g<5e+_92!98Sv@PBsCqH5yF3 zj$eY7WBM?(Uz9U!T(l5oO8`76nKdTW1?x$^SUy7vY((CF;)~7K@-Fe)C}B3!KVufd zs#9Di7yzZmFwJ-WxN2dX?}|LbpWVUgq;!8t^VNs!;a6784oAXXaM zQ7(DqcR%`q-4c8!w`s|;M&qFN3v)j+X?2i%uR?4Z49BIEO}RxuuWNPt_ud8!iJp6 z=xL0e&gdD8p2_GcM$L5rHP!|6d`2%|gDzx6h3f)(8KY|$y`0gtjILvJJ)`EjfL_h$ zHH==%=yi-<&*%+|-pHu2E}*wCx`7ql%IIy3-p=S9jNZxUU5wt%iZ(KO52N=odLP^7 zenuZ)^g%`+V)S7~A7Rv37tq3W0X5eJ^f@-@c}6$0qLM>4HkWqZTA)% z_ckN%u!EOm(6mm^kTWvm%nVtTA!lXC*%@+9hMb!r=Vi$G8FE2}T$mx3WXPo%vN}U9 z%aAo0a(RZV&5(5&vOYtu$dD^DkZUvKx(s6Em40$X=9>;eT zWXKa4@??fQl_5`O$TJ!8Y=%6SAkRoOL%z+B?=s~34EZ5Le$0@cGUVqB`6cuJ5ceJ6QB>Xgd$WPiRKxK;Hv#x?Bbvfa8*NB9q6h?t~$t72fOMJR~_oA z#;$7Os$5s)xhmqSd{-5?s;R3AUDeE0&0Tevt6I3~a96c-Rn%3jTy=!2j&#*gt~%OP ztzG4~s*S6TaaCJawR2T_S9NezM^|-nRcBXqaaC7W9qX#&T-D80$GhqTSDomp?ylf@@ut}1d>KUbaPs{XDz*;S{wYJjT-x@wTC2D@sAtA@I2n5&9iHQZGr zTs6{Fqg*xGRbyN=)>W>nVy-&XRpVSW-c_f$s>D?jTvh6-iLRRDsxnticGVPDO?B1j zuA1hm>8_gLs+q2u<*M1Pn&YZ+S5>%buB$3tHP2P^UA4efXSiyitIl-QB3GT|s>QB4 z+f`MrTH>muu3F}*<*r)cs+F!f$5pFbwc1tZx@wK9&U4jTSDo*wb*@_PstvB%=&DVw z+U%+eTy>$Vwzz7mt1fcY#jd)M~bd?y4(Xb)~DWcGWemy4F?KxoU^2 zu6NZ=SKZ*M8(npit8RAHEv~xNRkyk7c30iusykhEm#gk})jh7d*Hv*>-RG+NUG;#g zcDd?7S3Tsahh6oEt9HBUQCB_Ys>faRgsYx()l;r|+EvfE>RDGk=c?yj^@6Kjbk$3) zdf8R4xaw6`z2>UdUA4zmZ@B7BSH0z`w_Wv)tKN0hd#-xlRUf$OLsxy|s*hduiK{+! z)n~5y+*Mz=>PuIB<*Kh;^^L2(b=7yS`j4x=chwKB`q5QCx$0+E{o<;>UG zrjCrMqhjjlm}(tUPE56lsbgZQZA`U`srE6|A*MRURHvBg98+Cls%uOg8&k){RJWKq zKBi8HsS{(Wdrb9+sh%;_E2etKRG*mY8&gFw)i0(_imCoFb#hFd5>o?WYG6zaimAad zH6*5n#?-KwDvqh)F*PElM#j{rm>L~ZV`6G-Ot~=?i>Xs%YFtc>kEzpQswAc+#8hca zO$05WN{)|)ka{@{v-&zi`>B?@!%@d6Or8X#}TOu>Orj5`8dhKcKcn`f|&8S~zd9 z_%xD_vx^Sb8V4UmVgpXZTXI^cXD3pjzh`AEGZB{Q!vMI_%9&Q(S;=1@IjXPMvmXQc z+S4EOWx-!o2K3HOR_2*H&=WRJV+Xlz+wOgZ&onP?66!vFux!^@j5kIl*zmJ^yYAhC z+d5X*yE69ZacqxcvBW==6|U2)d8h@RbICp)NU)$GP%BP`dyBPu{CcA|y&E(SGqg6h z%!(e{tMsJjCFA=I0F0v2A2n=Dp!7e4;R%$0_jx4F2p$;01 zCT`5Wh13CF4a0Z!G~;1v*y~8#X5~4!gGJ#`B-Z8jF|22B#nnbc`U}~lIu#)AETlYY z`C?YI8h`2lG1x-z77Fdq%NoRH{=tr@JI&X?k|9P7fLasEhsq3(`` z@b($r%m^(}dXX+fA)zBL9%WrT8fleQBt^6~551Ae^*&f1$GKwVg56C~FW83)f!5pv z3gLO!Jl1!J8vBUAf-1Uwydsq`*r;6C+&~GK$PIpLk%yE$+E1ExI(Y=WnKx5T3d!B< zFvM9C1x-mE&rwiC?H8EAqgwGedn2!(O^FOb!cdA(K7>pBn(%EzQQ(J3%f@2QgY>TU4| zUbk!_dJosVYKSLqF`>k>XECHaYY}L^%Pg*MuW!i3S9fBcP)l=0bT~+;`Mf|qI;UT^Y_K2qp4bP z>08C}5iZ-x)e2PD^PA0)(1H`>n-Wu>ZiJ~4zw|r6LsR7eLkz# zL(uvOlsC_RuE#i%)RPAqi9MS3=+U5OkJ`O@G?+KGk(ntm(*M5m7EJew!`?oMO3XRWa~?rdf(PJPD7wqaiP8Tcf19UucO+eP5U6hRge z*I0?PnVCuKfyAf0qD7|?sMtd>^!{=Tt>f)Kym)TO+{y}Y)>EEF>W4n7Aq7ju$smnJ zf_Kt0QL-($WD~dFyBS^-+96UU9U6SsGZC2CRv1Mc?Gaf^q+Ua|vAinSf3;EBks9~) zG4G`4OARb-gq2D=k4|xzK80 z2jj_a5kL81`!{e*Wsm<<=z_Ec?RpDZy%&4+QF~`uw4NTPz0J zbay2DmztA)ql%XzrWsZd3pPiz$D*lEjgi{GVxmYdRW(%5R)x9kv2YE`CM8%}Gl~DO z6Pe$*F^Vy5o1VEZvoaiPf4?{!iCe7v&^9by-$m+S`cgfP32eqkJ4Ib?T`k{2Sq46X zfw5BL{QO{8_yh@;dv}9`M{Zi8_Kvp7{c!(cv~|-HFArr;!DjeVXU@ZpIuplZBQz}2 z!fu}9XJS{+vRT-QmX-^Ls#b!R51J7%J8c&+{I?vW6|Zf%czJ$MXtYQ{f)QrQ_&Q zD$xM7U*NJvUWxS`8Yr<#aMhiZ##3ANqvQ#=s>JfOh@PhGn=yUBu!);5eI;uZSUwWg z>4e}EM-!x6=v@-umN?_NOpT^0b7$kf)REu@b$N z|CkD**N|W>nudfyw(I6gAyY>;0dlSdL2y=VFCz6=_J>LWw`c@zeA|$_+V<|;aWsEa(YN=oP}RSlkF{W7H?e}^p&7_> zt9VYq<=NajV{=VAVJ#AxaRT*9fj;SaB>hQ6D$C3RAKfk|Z|O4mE;OMxy9ZZ(D3yVC zxSDBsGBuQ)gFW{XS3&76*Z-u3y4+8>%Ux|%b=u*@jHXV66NgDP2!0}c0}?K=t{RM@ zG*=Bl;y+$kUF`wiIY`+_Dc-VoQ{iZa_9(mXKr!l_DSfKrQ>_e(=xY~~V^gGlOMdcB zBR2b$AnJb0uCQqt4goNNL!>U+n-(*Ey${PbTGyji+I8wjBp+@i^MiArz}K%+0r{9R zNVv01L&h)Bd5U!S;1Tu|))=Inz=cn*Q|ylQ38cKPdEk*ez8ftnqCushDi1y63ErnG zlV+CAnmBbP4eC$w9-O-DE%CWg`YX2a_-#)71hH8Nc!W1{x|Wh4Iaj)#6rX(GXxn)P0sd%z*3=GzB=cF*8z8fX4xiUc;ZfTxmr@A) z$=2SBn%R6~ct@DW(!M~WoQPb`x5|zB+rajNuOg$#7JxQn$F0whOp^i4$##+K)@3Tp zP9#j{gun(&zv6T;MJy9#+l+jRy~}VLHet|{%X)69_$oa>9ew}#xaG@;LHz??6w&5;Kafdzm(uGzTgISHTl5P5qA4>;KC17usj*x&VB+p z10IxG1Q*e#@TQNY@#g}|Kiae29=Pp7`fe*--illP(^f~1Tfx&)S760$Jy>{$T$3Nc zm}^x>ntZ9JD{!!YHo@wdR<=d**_2`JVRQ;3hxmftcPh#gM&Oc%6?DLTQ8$>j}XEV*`G@RZ=r)5_ry8w!iG=!4qJq+#YX@&U~!hDa? z@ZcM0IAyr#Rg1e`Sh8zTOJ$SKHZfeYoAEVBm~OL!`&Z!U?lw?xQ#VjBdv+-p816A} zUA1#~#IzhJLh0G}=i^}K1^&K&)@<*?w6@+Iqu3vu(q3ie`Qad3)SEt#)+?k-WgTh# zP`BzQ@!ryo!&`=H%6S89T}(^VY11dnY*fcn72Egt8vNk90)%E2P)9xxTqUnM7O$rW9>@v7_J*?w|jdXaBUCX4mEhiOpao z=-`vwHki7ROwn@jKpAyH$|urkV60@%yibSc7h7Qs#{Jv$W`mLVv^C+4QLmZsrX?mL ztqY6V*<)gw9qMbIVdy4oo?&RFuw#&s0rr}JM%cTd$+*M2V^>pN`XIj^W&e(n%$>>` zf_D{YQK700ctemq>f|2t2J{FIq@UZ!8caX85gtlEw~{!Y&u!r25Ux*pI>mIi^z63X zDzU*R6;sr-DCY&MvGEt$R_93rfS>inJOxHKCf*m#bS_H0@?U|;DSTz( z3L$z@InBBjyRQZB1lOQJ-Z+A8hMl{%r9CXhc=v)GNzP)3Q=KwuKYAAI zc!Avd`2DoqOJ^hLK;7Zc=82|8T@0#UAR>ulysj*_(ncYzH(kWb1nh!)4k;&b3IYlg z>B~sjOdit+vv*+GO#ysp9v}l*_6azxcXyDlybr7G>G8-lo2!G& zC7bZp;*uTg4$V=wv&SIqkd&L~&d}idqH(~?_8IL-J9?WtUt1Kw9b@b=yTB{6m!!=4 zC2plU2KLridGb9fP_bVEqB}>TE4@86M$ZlT_A?{xWN)4s>HXs>)78^H^`@t%zI+6g z*T`dG7I&~fIlm9~nsepgnH!tfok*HzIb6gI)l}X4VRsgLEAL9J%JX|DyD4_=nu(2j z%BIeo7+Ri{jc;EJZ7yT9*o5+5hszgR4r9*4;^@&(_T}`O(k1k}c=+YB@nw}WOU+`u2+HTHW@LS{ z)our%otS3ZABn%~M85BEY}6JFBPRf|)VjW(J%s6k#LhZVkH73Ko^s*+gTxDJcEU=A zen?uul;I{o85+iDUDfYY1oGk)Z^cZ~64Z(LV~UICmQO073Ng;B5Ob@a#5R>=o;RGd z%dw-%?o<5(%`*8dU-Jk{b3|V=cl|8(Wsfua7IPj5cvwf6*mnCPkd4;WAVE*E8FFb- z#IYd$^O%8@Bj&q0$vtrzVlMS!zODL6e6(vB^JZB4>lG%e;|DaIW-_*Ia#ITD>gb2v9vG&x5q$8590ENt$cZ& z(#n^%W_pwI<=uYlAwUUIwg{p8n^uOAF;5T=#_A@5BrZgg;@rBwEH|Rx{OB+ zJarQo;2eRpbFGr5pVcy5U3Vnj&&AZYCv$Bx)(1Hb^s5hj2Vm;Yez>sAvRc$0y_GQ= zLF!TLE4UnL^;LHuVIW1PH#xJ@_8_}umdSp0jiiD8ZR{v!CIh@2hs!E#N>LT<;=31D z_V=T(r#b2(X%4#?+)|J#@7H|4Gn4qHwp1XkK3`*=Moijf)Rca~-$a$2t7dpLrsrN# zv)k3U8fm=$a){O=eaC(95nM|WHu%2{Y>W@EAvY3J18FYeJFEQ_p@pFoOge45)dtfw z*q~Gf=&w<*sB#IvN_i?W8e^4KQ9Jti!YRp>h;Y_eh*VAs5pV6CB@n^b8- z*a)QmNWpL?85jXAMA9>wK6-y|H|JvHnQfbu_qoO_4MG-JJ{5Jc8<>OCv#qNGYZz$S zXrYxz6T)_jpc~Lb7RUVLWAR7NUR`v$H-BUgVDjMl`P>BbJ`aXr+J`)9=S*EyabQMt z8jP=!i{+DhbMb+=u@!s!Xq8Pbne0thMx^y%Qi}>tUM~l_xW|xfiOm(QPcfYlEdcIr zJC(5Nd^yr*vq$nw0IG~n|3lipl;-aOYtmLB*Uu~(=}y+wqLEewUZXqZ;C;Cb+Ss*v z4+>f8M$Y2D`uNsfHctzj##3$3fBweERFzf8s2&F(T@p1GgI7@gI5<2iz zD5O3KlYkE(F^Bt?#OLMphI!s~Jk=Eeh`y3rKCFgr85-^fAYEIYA-?aARtJ<_5>R-4=JGiCx&*G9+#jEQs* z(oeF}xk&|j@3nyR^Y6!)eKLaz@~(u#rFFFS0OxC@JjRs<9SWvA0$u4q)Q)k!McVDg zn51#)6}k}yH~6IHc?@?b=>K?Cn%zC$3!D4dfzVFR_ERQJUaqj1>}Stx9*4v)$X#!3 zk3FoKt+M~A{;XxTR`r+O6{1u458vval%mG7lwGxlAeXkbk3yO$j7p>rV>*%G{Y;&y zLhm5;D$UI3;7hI6NOFl9S|gV5X!9wE*~~`q*w)|bXbPx}GM|Yna2`O)cXSE=sEbX- zJfw`bNGxh+FCIAU$M=E3}c7`_;`>Tx% z=>ws?oIaClva>l&M9&)H7p*9gi|>IUjf-yd=AGx*N)L70^c3%&gEzTuBR*M z3CXT{?P0Pmo7CO8Me;^m^tNTyj5$o97Xr~LNC;1AB5YpHwI8e>&epwO&^58#g!|7^ z{2VNIpO3tU;0w5#&>MKW@Th5RvWf?lY_!#RzKP_R)hf{qnO2#PoX&4j9{j<^m{;S1 zeg9`D!ezZsRuyMdEX32-*{8mn1ohuUDkl(R;3>H~VHt-N;3tU-+BW7eOp1dxc|<;9kWgiWs1urVZ4ea}i>^2Q>}) z(R9SM*`xT*Bxmt?tyR4EIXQZ-V(P}v$mKlk7=MCo96JP#eJ0HcRW2~rpy9yD{r=L6mA9F_Vp0?Jw!+BF--d^9{#CAQJ zT2=E<)i%7AZP@6wo^@aEsrK~5Mmy@wp6ach>g}HDot}y}+EF?93AAxpb;o7Z8<$mo zTvmf|S^JI4+Mj+GEstHpK+o>XY0Uacu*~fur-#;6R+0C!7eJj5%I?3HcH=+UQ@iC&94UDZzlrJb#^$|PstshY}8PLdWJ9lz}=(kdA=b}hz>X#|qp=tISHI?s2^eW&d`xOx_ zL@}?3=q94<$WSnLU`0qTx0o;LXb;0$A=R~-u|3wLDXOEHXPNFZ_47_7T&qI~1VRf( z*7FrKsb^PPn$dqzT1dZy5&URewABhAFopacK0)j;?r{40(5lF7sSWs?^h?O@m}^pm+z?QvIKqz~~OZD)6&4Pm;FGu6MPZ8F_~l)nB|9jxf+ z*0qgG#oB$vT-Xvfo6koN?A?DRFIhQGx_5kunB?3uWBN?3D5;piH-fF+jo@!`sF=1o zA8m8D5^?-Y*`nSBNL>VfUeW~ca^K)~<%b~oBCB2wwil`lg12#65#{{^-uTi9?9GAF zePd_RAho>E-)k^A==8UA!>TacRrM>t3%zcCa}DQv*z4@fWm~<=y6!ExPUuoQ5PP*i zaVWb(;?G)`U$wXpL!Z|%g@^&T*_4pqt$g8ezQM9Pz$U0Dls%1i(FpvK=y~WLf8_pg zwRvewKh|ts8aDvxFMG`}VcUtZNNZ}fLs<_VymOZV^A}w&gAn^2+X{qnu^9!*c;+&X zzRfiyY~tdO!SpH*eUbNuO04Yk&abWE{PVnIqCgmT1p>Yrom!6E9`gXJQvv?;Op7y5co+U! z!}(STorUJ_bnm)5%+OOfde%$0v8IGuO>LqFLOB1bcgYPkrYtro;`Zy_CFM0G{KD}_ z)zF_&*ALAxXdTA2o}C-?M64;LH@uYVYE0?xr)YCec^7RPK^2Dm6u>GN~r2N@0Rve^3zY#Bd2r{=qJ!gJjb8bR!o^%h6P$MFx$&;wqMD#lNWnQ zYesk;qAE?tMIU=9t7=RsY$u;=bJsq}!~a*7#2E5E^%8!mDPdkOuR%(Ie(qf{r>2DN z9YCpM&W-VWkD?=MN|-ICqz>HeW$<&7}3hdr9kjjwUUj zr_3+C9L}pT^Jx zq|WqfFXikSQ=XzqC0}z=ko7}rb=?tXw|N#W6K6|jSB}>$_(d;iv2R@0wzs^bopO~- z0?99?JnyAl?Xiz1cKCXh$MFVzes%?RouIB_m6y^$r+|8N++5|Cd1)t_N~e9;<>hmY z_)zA1{<4>Jhc>9U+mmK{o@a8dj!T$$$Ghl=4qk=SeftSs%HcJpw9qMHiXMHK>qm6{ zey6{}%e;x+CSi8@q_RnKOQ(o$=Sp%ty1XnFQdxM9m#xBhfXd2Nb+WUj#6oo-W52jVOd>q49@Vm*j+M63_7T*L+tD@5E6;#?8; zhgd1%0TAbj*bw4;5f6m8K*UB6&k*q-hzmtL7~+{C9s+TZh=)QvOT@+y7mL^g;@KkR zLaY)o58@ILBM_I0m=AH8hy@Uri`W$63K0t-t`xBu#B)S!4sn%;he2E|Vhf1pig-B0 zH6pfzc%Fz+h-*b`1@U|lkAS#N#3LcD7x5^F8$>)B;zki$L);{y197v6Z6IDC;xP~} z6tOMDEh4sqxK+gV5HAw31H_9(>h=U>CE#eS} z_lP(Y;=LjcgBTaF7~*{*4u^QZh$A3AAmT`fyF?rX@j-|=A++0YxU6j`Cxm7TsU0M= zT1f37q0vI>010gtQb$N=vXDAKLW_me84?;Sq%M%qULkdbgystASV(BC;q0<@lnGiZ ziIfXkD~Xg1S}Tc^4_YgUlo47hiIfvsD~Xg9S}Tc^7g{Tclo?tpiIf{!D@5$ll@mg1 zC6RJNYbB9#Lu)0Gazkq+k#a+8C6RJNYbB9#Lu)0Gazkq+k#a+8C6RJNYlVoF$2lRi zRuU;Uv{n)+H?&p~DGRh#63H%FD~V(btra4+70L;rwUS7ep|z4om!Y+iNSC3tl1P`K zwL-*BK{+9`Rubtlv{n-7GPG6_=`yrd66rFuR*2YEGAD%AN+Ml`)*7x=R$5A@(Og-k zIM7~MCJY)Z%fuU6EXsB^BsAD?crsmw_6muvLUV;g*PyjRqASo?A(3BbtB{CiG*w9C zAX+LUVi^rJ9G*({&`u$dJv38DWDl(r64^r|g+%tyMj??sG*L)o1uZn3Jrx6(oDf=Q zI6R#UqJcspgJ_?S$RL_0Br=HB35g7%aY7=4Xq%A8K{QQBWEw3q9G*q?&@ds9J+w#$#_z2rV+4bp`~q$8h!n_W23A!DgAiI){>0 zC#td(nygYP#D7^?bY5{9Nqt#5yc();TBs&KWf?06v#shm=B9WW=T-N5^J6kf%41B!JqBV z(rW&+1Onr&6eyHmR$YVgSqS>nDlOCzK-EiW>&UcFM*&se*h*Hjk4}kbodi+6+#H}9 zB;-^b)g~>}F-cHCCflY&v;$&4{O!GT+XJzGN>m3R4oHdW4@AQRlz5FMgPtTS>tv0P z`jOc3J=7^_p#}hTApY$5{M@Lo8kiC>2nc*L8L+XeS_>Eq#6bzDB?jerJtQsE(6ms) z(n1vjB^>&_wqN5szlNuU8j%)iWLl_EKplcVyJV{SH99TSn6yx1(?a2gH@JQ#*1qax ziC-^B6M1Ud$Z=^S#{(%Py0>yYEiF_@TBr$Wp-O?GJN(|ubz)kmNok?V(n3uJipCUs z_iIX8sHth8PEQLp4Jhgl6YE>`wlFP#SLT)21CA|RR@l+;a(1QW*lXQhQ&4Af!9mW-~dk08$mqD4wn zRTYg8XiRGRU%kAmmJqIGYTQ!7MH6tra}+PDN;>j~2_0h6Q*HW02;YTQP` zbxw`jM7S=gahnO(H8t)6!X29$cOl`9OO4w?I2!XxStRzV-q^BgYnr%=2-htk-|GEb z)y0H6-rywn>b+CdC4@V{;A-l5szx{RCE@y{#$81?>HBGn>GNDwy&YXm*dk-o$0oF;YY5lR;F3LSS6xe(lM*mV^1P04 z^gOwjw!4Ec^h9Z6lGwVQaP&-R;}U$|Nf>&fv@uC+-9R{cuC#Fpwr(U0Jz3hA>f?i| zn+QkGmNqU)-*YqJ=;_kNC22di5N>E{+^vM8C(IP~ZX+B$W2V5}PPpL-xCBn_AdHOA z{AZe~>UHf-!j0U!t-A!J)5aya&)rKndeXFUNy;HkIC|E! zaY^jm=i#J9`F(5>?EM}#@mV4X_JNwPN$TJ(!qU@j3SS@eaB2AZkcUmf*N1DuCh_$V z!qW403SV~k&WBHYB(xTgs> zDK+jH!j+}QJxe%x_D;dybA+R(?-aP_2}jT0DR3_kj-J3%;9evgJ%gvfy+k;A0#AW^ znQ-*{odWj?;ppi*1@2YC(X+RWOXxRW^Dt?&yVpHz8traRP1q#u?hV4y)4%O!lKa$~ zgqxEZ_ZH!31|WsKw+Tmc04Z?q5N>X2+`ELMc>vp90^jcuW?lj&Nv!V^j^+VuTS;&q z5RPU7Y+P0K``(9yqqzVZm*Cq+grS)L85F!`G6F- z&j?2|0yZwm{poYU(VRdE+!utCSpgfFz{;15T0;NYs3g36#mJ>;AiqxA<~M2E{FaeC z*I@gZgzxVd$+Hb9kpE#M&o`t%e$PmraY%vufss7tkOKK5BYD;#1@b3Gro;TtjN}=L z6gGchB+pT#K>o@|o~1~E{Ed-3Pmu!oUqez5y-0!li;+BkkplTQBY6fR1@a$8@*GAA6+em?|&&VsN^lfC4QAh(uUYUqYQbzkRl4m$<+gVIvcAJ(y8E z*I}cQFmnhadA1`3@=!+doQI7}(jpo&l4m_qAe%6f=RHy&a~a7qA1RP|jO4iw8<`~b z2qSs+BLy;_kv#ulBNJFJU=+`Q>;=`7Q9S=)qmq<$AtQMf#6~7*GtC&u^B^`d!N2B= z;#m+Il_clG7|HV>HZs9p3r6uQh>c28BMxUI&x52uwqzvFf}}u38Od`XDUhug$ul4} zG6|1IFp}p$QXr3HB+r1PKpw?Np8v3sNmx3Xk&h(yd`XZFBX=hv6UwJeTBu_f#d9RK ze+jnQriE(9D4s{zi>>x)p*k>%=UQxAOK`uE8jIVhGVg#o?i0Ebqj`SDww(}j=d@5= z7{zlqd$H9uE!44$;&~q1R+5@}T-wNPjN~~X+h#(n$ESrlfl)kfv=>_^riJRxD4tug zZ6%4dN7~4qj7(MkdZmTxO{m(b$18o3;Z{^1RrTdud5+AEH_3geh><)?W+RtWx7m-8 zJWpmLlh{0okvvnD#tc*ceL|n?qtlp?I%S{G0~pOScXotHYRSN~k%Jh?vwSIR4o(|6 zgpoWWn8N1Jw2{LY$+L$kY!;`D9L`9dZA@WvMB2!ajO1C#6gEetjU3HLp1rhfCaKwD z7|C;&DUf3snNDkQ8Og0Bu|_AUd9i&$pPIH8;~2@at#)KdJQ$xg@-#;B%&cuQ;cigE zD4v%Ul(29(_dxd70#y^zMwT*?=WtWloR~Ip5+ixOcQ4VDrG=WD9F>IaDU9S9WINX+ z$f;=~Pfw0aD3@tzp{6s6XRdAkl8hr~Fp}r4ZDf*GHj|M&du=0^RKF+9V&q3OHkJ3g z{`<~^Xl66=;}oOVIccHF33Xt?-8vz^iZn2DIX9j$x8qE(RGAiP9-}@@5#Ri@PzxCK znQx1@l~#FJ^;UVtKA{&fnrG|nn3L4!Gt)*cVkFP(i%qEuNqUg8(nhXiB)7V0iWVXiIs<|e_`-D#ojVHCdu zOi_34O&b|!Bqjnq|7tAb`_e|<&q$8huRBTCxjv9Kau*?M8!v0Tk3E&OJ|Pl5k{t(Ior*sEc!P^`8}F8@-aq+)3Et?+Q=sunY8?p^rKJi6Z$De zXVbsJ!CpsDPwx}@8Ajvg;n}XSmOPs_@;OG<_HEWU5`R8z-Pk*_kco^La0tACBs{jV32VqRxU^;1~d!>9&{C>ced z(EK+XZ!mJdL}WtG@Ft~8NgT?xC~C$e0c&p&u80vnF2UB@gh^w4^E-q~V{P%fgiBlp zxrE0{0pH#uToup0*>|rb$oJDme!$56>0iIqCVe*fFm2>Vj6A@%Sz}H8n2`AOT=~RM3Xwnq+)@#PQ?;zZ5fNKwPiFror(p%Iu%QJDK#hb0XrVteC;FI)rmG= z`&dNUeC-nvY4f#DMWoHwJ`<5PU;A7{+I;N`5ozwHedT%MB04q8xd*q zwQohF&DXvYkv3oZkBGGS+V>*T=4(HQNSm+yC?ajX_LGRT`P$DS(&lTwh)A2S{VF1D zzV@4lwE5b9MWoHweixB8U;CekwE5Z}BGTq-e~L((ul*$=ZNB!mh_w0IKO)lRYyXN! zo3DlN>mR5XwE3D6kv3n;5|K7v3yVmbuVsr!o3GUpkv3neEh25cmLno+I+39 zh_v}yJrQa1wfZ8`=4%Z^q|Mj%6OlGw+h0W5eC+@cY4f#)BGTq-2Z~6WuQd{pHeWkP zMB04qU=eBawL?Ut&DRbUkv3mzEFx{b)Cno3C{ckv3oJC?ajX)=5O#e66#HwE0>W5l2JpD&iQ3$BH->;&CFn5W9&OgLu4% zr$RhI#BmT$6mdMn?joKBv4@By5POO^0b(x^OCk0aaU#S%B2I$XSHv=iMIugy*iXbM z5Kj_uD#ZRGo(}P35vM^sMa1b42Z%TW;y@8+LL4OGEQo_eoDFe^h;twg6|o%RFcB*t z7K=C+;&2fwA&wAn9>kF%&WAWk#03yXi+BdaF(NL6I99|nA-WN%oL*6J!z zr)YJxs8h9iuBfMLb&aUgw0fSX)3v%*)EQbmU(}geT_@@+t*#e!wpKTYI!CJ;MJ?Cr zCQ&Q2x>?k@TD?HjO08Zf>O8G(5p}*+w~D$zs~3rShE^{Yb)i--5%o;1ZWDEpR=10K zmR2tnb+J}26ZLGZUM^~tR<96siB_)^b*Wab5_OqYuNHN=R<99tg;uW>b){CX6ZIUe z?htjAR<9RzwN`hEdahP)5Os}KZxr=Bt==T+TCLtJ>iJr|Mbvd#y;aopTD?uw4O+cj z)QwubL)1-Ly;Ic9TD?ou3$%K-s26JW9#OYw^AyF^W>cgU5uGL3Gy+W(IMZHq1kBWMgRv#1fYOOvl>NQ$@Ley)u z`lP7WY4s^lcWCu#QLoqPGotR)>a(KWpw;I@y-};ri+Yn*Ul8?Xt-dJgEn0m^)LXUs zvZ%Ld^%YTX*XpaH-l5gkM7>k1uZwz@R`-Z{w^rW}^&YLhDeApieM{81R^Jx&KCQkZ z>it@MSJVfz`ktt}wEDiN4{G%TQ6JLkhoU~L)sIAdM5`Z*x?8KCi2A5jKNa;ct$rrz z<68Y()F-t1g{V(z^-EEo(&|^DKCRWSMSVuA--!CGR=*YXIjw#t>hoItkEkzb^?OlY z)annSzNFP3MSWSTKZ*K^R(}@tRjvLa>T6p4Rn*tD`kSbGwEACB-_YvsqQ0rs|B3pR zR{s$7ZLR((>N{HfOVoF@`nRa>Y4smb-`DEDqJE&&kmCFAhg!wd3*C-C(kk}NA@yUe zhDH5EtJ$J{s?}Peex}vhqJFN`98tf}Y8_F()M{N(ztUW^A&Baw_mB4lVWK!!v ztxcxMpZZYPiLP{I0}t7iFWk>0(sldOb!8ykWk)?C`5w=wj3o=%rHu>iDjZ>|MsPk=m} zfVVRzk`iHb>6B>|GnnjrPDC+KCyuoY>UYncYH9pNyY70KS>8b9!@6pDrbN zn6Gns3s0XZ>4*C|r?-S&y9~|{M^R59w_C9?aq2vB^9WBN*pZ$>u%n>lluevbIh~S@ zmZZ6}rb21$DU{-P3SHF3Q>Zc@1Eo&cqy@8u{kBkZ%BG;zQ^xI#M%T3$t)g-QrFAeG zrFDc>yKL&*S(MbtQz+}so?Ko(4%4SR|naRv|gIc?6 z#w_OJcuyhwCqSu3Ddniw)QnFwC+5hB?&d^=oaliQb@e55MNgy8;f|x1(JNT*Z46A5 z&ZLhyF-K1HH76?MM3FHuk-MCJMxVp_Nk*?=y}!{Xa<_D{(dV#!iqR`r9{?TnP}CH` zK%>qfb&yf<)2KP2!BCkzqIn3E`empwT`MXVFtQ0kP;^lJG8U!~MisI|&w&Z67iM7eBMIVDWe3U^Co zP~ai@C`y{_B~gbo#Y^JeXezW?WwU0|9p!X}L8fb_LCG%TY^Fo315tN*GoaShDj{e3 z$z*?)pUgSThK?NA$2kn0T~aDHq;jKje^bF%Qfk>$YW#C`^2CW;5h`^usg&7!vN_V9ob4&p zuT^;pSy|#K6wOj7b;>HHmsD_$%Z$o7EQgwd)ajhK!qYfyrD(eHo+H|v^0`!vRvC@z z(Q2bn_UDRLUcxrlcpBS04_fWAit^HS0It3Xe+mm55dEpC*{ zgp*C4LY!>&6mszbPa#e&6h*r1EuKQKt)4=GT*S%(sq_~^$tfd+k}iQ(t84++(`^Ei zgzch;JC}M2nZC?Z==#f9SvaYD7L+TXQ zWb<0WPM=soBfjgjJO%O&Ez>>YdXXy$vs252xdAe46CXE1tUY~U>CCxMZi147pOwN- z`9QlFS{=H>%$-HZTj(OF5O38fdW?A+Uxu!iZw|M6iPG`k;U#jney68#r+pW++SF%L zr+hb*x={3pJ8_i9^nwiC?qAPZH4SS>-&=z8`XJ^ct)@Ko}^% z?1C8P0(+1Uv+*;16z)S%a#$hI!_aEYo;90B{*TZFyr$F0{JOUm^60^Rnn)S)Wzs}?!;O1$$@7W zIJIO3@a4Jj|OTwX#szQh-l(?IfNIn8!nk<)~J z6=Lm*xl+!r@%gz_NnRI`0^b8M%rw0rC#mARDI(Rsw?w4;-iBBk9T_|I4wPC@DB)em zIV5w+dwc~~#`hUCzk~|#1ITsf;?7oDI+r;5kS-D(+DFi`i0zLV#gr?P~ILuTRdJo=>>*3lR+E18DF~fGacIS?wG?6F~AKvU|W9<#CiOQxI-?i|U zgTK1?tB=3^@OJ?I@O?%$_8QGT1b>b3my18FV#_YTUm^aQ;}7eHvRmK}tH!fi;t%Ur zvRmQr2>cz1KkTEMjXiR+vHxv0_O{K&zO~uM;1B!Fa{gI3k`LMVBR^{6k9?u`uH;WW z{E<%$@JD{_k3aIQA^ym}M))Hiv8Imw#OfIKwF!>oZyx^0=Y0H;-%asHzBj{PJN#k4 z+UySa>xjS3`0IkduJ}6^f7p*TyBq$nawz)*{9(V+?C$vMfxn*k>xIAG`0IqfKKR4> zoa}!1I|+aN@rOMyvroYv_OHwyh(GK-nLQYPL-02gf7t7hmLFtexdAOcU_OWgiko7k z_=tOogM25xiEHASI3|9HTjKSYoKRCP;3_@0Rj8|(o>Xe4RXw-WT&sHa>M*V9S+f>e z)w5TJYgNx)wbZJfy^3m8PolNbs-C?%LaTZb?MSWaNwlN1s^{{K)~cS%Ypqp1r{-u? z&*im&niE2pxFt`b2M2^0&YsN!0)&VA+@#4ki_pSh9yB8=3SiJi4*LZ%A|wE{C(|76E6&S#3TxZ zBfYVtcGjl!q@YK-oAq&JkWXTuJO8GDt)Z zfXds*?zD!bmx#2or8nn_v~ajJ6%3NXwOg08 zo=t^=#Ber?2e{msqfh=n`fqSyRd$ohs|Gi#`X@BF!+vFr^6P|K=2X!OzR>=$M&XeS zLI(`aTHj=_8ar5xDGuRS9ExsiQZ!)jfuy;ERV;czlb)-VUDY6T+@>Ztb?R_z@OmVP zjrt7_4X^qa|D~VJ#KEeR3{ONhTTC{S2CK5@#a=dBDVxch4T<}j%{oL=)e*G=hof{v&Z!*Yw9A-T?=TxUS8b8@bZvZ@nc(GI!0R`#45s;bj46p9bYUA63o1|#U7_@LY! z%T_moyrNlr0Oa)~FKZS*8S(~_mox)qyO^V@Lvi(hwyT!57=gb5J;~y6#ku4{XJo=b zk(yCZy(FmPyr4)&P-79)=v-%Ht~1<3)Eh~NRwBx!h(`Mnb%6T~LL(@u_(%zeqKXff zfG8^MxyzpSfid=+)QmhI3Jaj%Bz71A>F|6KJTJ|4N^+g?xz4G^`C&+no@f_GsqcKe z1YUZ@FdKO(z0rb<9u9Frv=t2kz|=cO>lo|Br9=jE^fho`c`5J-pT3*h;@TxV{sQ=aS0 zHqKWdHQL`Uj(NWG@wxEQD~@vUo{M9)c%QmB&fuWtA`=dZ)Qp0vf(68~fMbC`I)bV~ zP>XY&MY+yG6VVbRAzG_A7W)y|#j!{N;^J5+0a?YdggsvhW9&Jp8F_v_EWqKF>@Wn< z;rVKKeon5lBG*}FJYR>TV7orY_dLD=E}|^BVK4Jtk6uo_(~@SPs(kbW9ndGK5i5ID z4gk=!^m93u^)Sz|keX2}m%su-*vuh7ARV!+Lo91^oi!$qZ8#qcWUU{FT?A|PEspgZ z$97ofI7rPXj_Y9o?q9*~Lm(Y-Y(*Rw<~o~mosA}xok$8c?hE};;+w59*|=}9T*R^5 z0P`FRsTsv`FDxL0+c*RWq$8F~5zDq*=VB8`9Or|9Z1V%L%jDvHi{mnm<33pDI7rPX zj;CM&?mx`#Lm(Y-T!%QW$#t&Eb*?a>JdLDa3%|w>C4QAvCRglREIT-sXJDRVAvL2| zUWWyQ@B)Vbfpo-j6Jog`*SX#VvIpmbf!yE+VwcJF`xeK|9LF25&T){MQ5>JZ0^EOx z-G@Lr;j4-G=?>E8~>JJg5L zzCv33-drGM+;$Ih^fk^hN2F%N(XX%o^Z&tt2cx8eqesBeL%Gf_L(p%6`>z~+$0112 zLlWDn(E4W4$1H;W2W0fo1cDy(39_q+w!wF_T}k-)gKRyPoS#3D7Jt;|XE*cn7tS(2 zq-MlVoh;@jgah+KI{0}J{5+rQJe%u0Z78ZM(0X#Hk3*26=MfT(MyL+GVo}rp$mq+t z!QSl^pQ5<%?&zIom^IYfCT<2p$QG0=QkV8it zf)ss@ki0tdjYUx>AfsRB27BXge2U`wLasxf3eU{Z$4NNqOvb)R&QTYn#lQAB`ieQ~ zinGiSsTpz98y3LP@i;I?q=TcM!O@So&i96(K7#8jhawz;1pO$naUJ^2BB&pb(O(k? z`pqZEu0z@e^YeWYeoi7=za{6VKhomA`uzOD{G5!l%nzv<@iPJzz|SBYm><%?&%fa3 z?_B3k!_P>;jgrG?9D@A(jd;8Yl$Gb-$i@H}Re8Z1SyrAu)1WWp3iPLtOa$$H{O;Y^ z#*+1{yrg$F7in>oXYOpFJPI_1v&;kTaEIZhK8^+1h-HQXW|eftPu$F>Q`fnuth*d56uhSAL=u92s3sz&N5@9X2jSUSO8-yaA3wr2V(_bEMn+7 zPe5zsa6S$}x*}HnYG%>34#;R>0$t5~y6pO;ZKTiEdNSTDIa?c$7BBSKYRYVF#93yG z)Qs4=3>LuFRvefu(!th|V5?Q0)6x)jx!|sl!<9G$32SB5uhte}R{k z*B5gAYPqlV>uR#zIyqz4AT55h&)8AS*tIyzjFFlVW4FQr7~6>hGe$ZXYY)cS8oF*1 z(Cu=#1BW18ZLRv%$)f8{Afp`<=<4LtW!EolBmMey7a8xAoUOZ&7Vqe@)q&Z%2WOcr zQZr)fRagL9&)~ppkq)*7f~`~Xoc?)EzdWa}q3t!KM*HMhlj^7VvB&%CI!2S~{WO6z zsooc|H>tj5Z-946opBxtL|#t&HAErLpcjBZOHXuD64T}`wN?maI|!p}sqwLLjMlaLnQ=JRt2 z^HYYi%nzv<@ly^9;OBH4m><%?&kpc&ZJu*=o^z$4s6wD~EP%NaCBRqbBiJ99Ko%U!)hFY1l=aFaUHtbBIsNoqjx0`bhl5CU5B&{=I53q z{H!5ccPHoPJfy|%^7*-w`B{sz%nzv<@pCaOfS*k`Fh8V&pNGKDt~}>{!_Osx+a`zY zI0X6Gg?PLQwA3YJdPS09&-2!CvnFP9? z_35&!leUpQTep(&XOpva8`9#>_-sARY~7Bt%oeE`v9${pz}DS3Fk7U9t=GWTD|yaK zhOh?(_mCVO#vw@9D^~q_!y@bvAftN{+TR;KVR3yS*RPlMwSMg;>u)4y>`|n}_xOyx z&Wt^Vv&WxGh1)qEVD&wMr^grX0{?YFk7U9t(K7@r$xkR z9&rjIPC>+pM7-J9C;-t`k?4>5k*OIi4r>wdC!w21q$i_C!9vL1a<_uWj-^-N5pijY zcm$`fq^HFn8zfozW<3?QzqaR9&FIzYQOGskDncq1ROm4J_g{Uccdt-L-nd31RP;v! z%&d@_5i8wb0fyS*z^srCRyu-}_7SIT#Ay?8T1T9tBF+(pnB#$oc8)~%i^#KNl!$3> z5!2Qprj12RYoC~-eDR3Aa>UQfhMgYBI^MY&J95TnrxUZ&6JTbC)Qs2}0t;ZL2nS|| zbg~xPfCq$fX5$D*5)5TCT6abJXyc|iqboY6&o6HG93sstUH{pURP5f9(?jpoc z4brO&dvRRDkO{{{YDRHQg$2ZQ8ixacbi`GRxW-1D(Gh24#2IdaIvuHKClXX^3TkZf zphn~LGI|n6P$MI#|06i2;W+(c1DrN-#5j&=u*-3fno%6fU;*x*!R|vK9dS%S9Ayz_ zV#JvcaZZak<4h>a0f?TS(5B1$XyOyWxi`HtLCT1ycTV%`>o_Tv8rpQQzOF)k@zbl- zS2^R?*Qw0MYJiy!QZwRX3oL+!^Ksz%N;>$c03UNA&a8+tBjQXmWNbw$xU$N1j?aW$ zS!W3mT&^>$3OY@gunKlA2XYY%b0DN<6vz%(Kp>a0{}4z=AXNxtal}~^aTZ3L1rcYS ziRF3#g0U?2V~H<M*$K-W45=9fb1y6)hFdrW2&5yJa}ms{ zh_f={ERQ%#O(b!oB2cSTR#}m(v?5vVM?!a!f2Fl8tro``j^jSqbfauMU=s)&wW~U!cdy1r{A9`5?C z_Pf3-C7iUnzVDD<{N`$1pPcc#zMGhj{{YNCU|-@u+Q2XeLTW~Vbb|#1(t-VlKso|>6M^iB zIIl&VS4TvcD0_kw|E4cba#Q7}Zd}6#k6-m)=5}M){zQgg) ztaAJ0|4X@*Aj|kS)yhrI_~rIBlQ98cCWF+B$e0NW;9xQiTyCU;j2}V9_Yvni!^A9{ z2Srx7eecs?m)m#M%Izn1bv6vJtE6V+>RGS=S1Z{=2&BW+Kj7-`5$Csv^NaCzu|Ut3 zLlq9xlKchNzw2V7#j<}#{B>$efQDZBG^SZ$HquzK|Mg{5L<+_%Dz#FTlNw zH$}OWjQt$}In@_jFGE`VuZUTe_9t_+9A}v$QZwRcBP@WL)i`i*k`9jQ<`+3R`A)5T zC!Fu7d~Zf%lb|=t;Q}0jH09(=uS7I8$oFZw5Xfl#{NPBcLB2neqAz5cYQYF*Qn+Id z=krVoKSe5>Po!)M8E%lDl(MZzi`UOLl-0|pNH4-!ri|2#D7yw0VCYgDm@?8q*}w%0OnjfrFjeWB0#-nX8R}GW!vy*H!PR`E_ zNQ)op^K%IEb0f|&Kcr^FPaGD&&uus`Kcs`7!@y6oe5Yx?lW!=xPoVe9;Q<_i6g9Ib zYH3ll3&`l<3H7OEa*DJKrl_e^o$`~=^&r`8nVhbNkQP7Or>h0i^)SvdU8H72*ZZ&l zx?abD=^`C;oea88%6E$Loj&aeg8onrAK?&W>?A}*;{s}d11-ir1~NJzKRDza z=rb1A7jg?M655%vJ{D!Yl2G;u86KFNvQLo~AK+7V3RCtO&N5}BW<=S~umH-w!GS3w z9h8j%Wh3&P;(TYQ;p-QH{wjyxa0v1>LPF(6IM(9pzd%OEB=9xX=gV${+6L2AY|%9| z30=RF-Lc8(`XAEbV|=sRUJX0lV(btgqf_&PWAD>_#^U-yu3@D@J5yF-Q8qpaWrvdC)00!y z7-{jTK4nvwvL-mol#!YdWi4R=HLL&!ri^q@HW!qY=R33WotcKOs6boE;Rqape3eV6 zT*KyDd>sj7bY22q^L@VT8m4V9U9&B^W+tKQD6%_0IbBC1Ek4hutCHzzjk8P_sTt9A z94vsYb~rFyq=T;IplfNqQfU+VSm@?8q z*#=OyF5g+3@2oL=4HoDSISj=i$k#dvm222$i?3loMmHt!wb|#(u3_2+)3w&3YfTcm ziplQgbP!`MVY zPm)6!4nf8)LsVW3yV_!G3XsvO@`LX>uJ##=>kGMtZ5P^^vP&$=E=oe#>16oolQXylY4JyV1|Mby zx8f`_NNPq5UJDCga61mnAn9Q61u*zrzVl4J^Hjd`grV;`LGO^m^*99Sdrl(fPVHrj zzMViuUrM0wWuHE~%4r*1<({z^d&-iZNW$I?l*h}-*}D;G@t1t|US#%e!dYgI)Qs4B z7#6@@90z8Pbg=g}*n2bI*<*NnL~y(1@F)&J-rht!Uf1@X#oJ>*M&Hd3PNlu)^A^_^ za<$tdBSJod1rYK+4onE?Amn=x@?F03jp5{T!F?fzFL4NR@|{&nezG|E3drb>`N4_1 zpL|Z@`a-TH-z2FeUz35Kl9Tcc(&9h*r2N37e2cS83aJ^9@?Tg0DL>-Cq>v6$eg`SP z8Ag5=(EsG{2M$3-ezR)HpB5v30vY`yfssFbM(kRmZ3Jq`Uv&MS$qD%zY4JaNLjK2u z{DZSh2&ownQkuhrjKzToAsvJqQc&a^RNx#~;2cok>{sAT>PIr)*cvdwU&PK&3Ppxp8!)W)$6ASb(AF925l7 z5nWS6mtWxI6*x^yXq8Ap*b-V-3N7Cc%`Uk-oc0#3H1TEqBB78yp9f>?IjI?Wz8n_d z@R{r|1k&O8k?_1#fzz_UX;I)bH_op>YOq{d`Oe2%TIJHhF9N?@n)@e{lndbk-y}Q48*N-LM+Yhm)e>zEs)oS4Y4)kf{%7K!a zQJ{NZ0r9=S@j)ORffggsp#{$10%xEJ@eP5#DTlXk2;LZmBH$JD?6aa-bYy}5PUCGL zqazA}-OEUe9ep9+DhCSdtbSb;Ov5cIX+zLCSXI0Olb=_0002}&%2z5_CPS^_~OK0$U1 z*EX1+u}S#(57{b7&d>Kqi=XE6GoJbR0cV*XQZwS`Z&(07zv96BkPd#PgP+q2oGArP znW5+(f&MFpP@P1IPDe=IpnR4^kpeP0vmn?B&hjaW>kGLKP4Rh&m-(`(Ls?{OR&tK8 zlXfUR)8}XgbCiv<%n_*>anuMFz)^i1m?P4`(R^@JS>RL{f({bg!E!hRhhQD5lz8}Q zZ=prdp+H8@NFZpTPmo=Qv<W8%Wg+5&uFkL6%EYn45Ms$sY1<*AR2d0a3&~-KFy0XBz zyui7%z}aRP8ztz`au|a{kg+Qfl~=>Avltr-Wc1nsj1;UIcAd{yTwlmF>~f!)_@x$Q z+x+vUhPh<;y5y9_kQTqzr|cT0>{Og(%1F(KveRJ!luf{aDI*<}-3H2TDR6EoaBeVs zO%v#JIn2Nz$k#0r64$UhExu*~8NDNcuRDFd>>8$Ra1Fc3qU(kvbj>2WcP6K6HqzpE z_;lUQbj`t8ri;{lrE3Un5WO5*3*bPT>o8rUgRbKWi=3{7PUk|WW1-W&(0iJs4QQf~ zLa8P_s3YoH=s!(%E|mI3gW`^mAE5#Au4eJ}kiESu_PRlIw?gt|B{JclNX;lH+Cm0~ z&gEDjkdB~wA*ddO&WVN2@g|~8NJ6v{Q6Gw^haZt$kS9t&6jl6q3CP+up*MTJ8OGRi zQZw@W3Rr-{X6qW#;rT##eoCR!ztHJd==3$t)0Q>Ss9hYV_|C`s!%OcOrJs1u#nD&1 zU$tyWiv79=aZt3|4F^SPMnUO~W3J~|5FP0VY6OBRE_8+#I)hC_w^Kv|?cyl*BeIKQ zs075tF<1h!ien^ueuw8dsTp~`8y4VjoE?ThIy^rOo{uYZVujAwLT9vb{!yex+u6l2 z&UZc@gO^@$j1}*>I7W;2sf(k8gL({^aB+~DQBW_z0%CcJV}U?Af|`P$$_kx{h0X*M z(aT6ev{vgV^CPm0W13@oB#6)ju|_zCm<3$MPY}b1bB06w5cTfDk_A5Fn6_ zSmq;^%0j2Y1oAD;2Lq|}1F?&sV&CFez;S#B>l_EE8O8BGSb+OKvilH7M;uj%V{xIg zsL)wxLiqzp!N$GV4<)|HDwBo#7RwTjZ?UZBSn^<=V<9!8SX#mYLTJh%Kp-8lT!2_M6*?PCAW@tT2C~Ty z#4eK!`xeKA97iiy=Qv2sD2@)W0QZk(_aXd0*1iKkiXwY|W_Af8pkhK4nY6Q_G!i7M zOwLI`L|njSSzrZrVRtdzsjDa=ih>D5R1iTF!(kp371Lo(cj}oHvuD8Uai0J0Rrgd^ z_jdR0%g(_8)Oeeb=mURPIFcUMyxaom77)(()?43JjyP>zzTj*vIB#Eo`bx>jx# z_88#$0qUgHDAe?=8=&ni)~hTO6h+qUtx;(xtj6E^g#vceXXpW7HeY3ybEP_Zn2rU3!`Ou~lo zLuK&u2>5wufb`%1>3&WTt&xMO!jd>ziXK8p#cRRG1d3?Y9N(h@w7uJ7Dn$iFk>${X zGS7^o`wci^3+p^)%n>b=Q+QP6XdC0G9(x%_R4j`lWigz&0Ad^|i{bno96dcidXf{= zf(jtWbS0dp<=9vbJtq)!8uWb6>IiyHB}mL61%vVPqyax{A)M!o`C$v;Jgf4vgYm-` z!l7bW{3r|D@P%-wj2!wW_<4PR^y&cVWloW>2o9K{6>hXS^g2Q+=FnRLMVAmoZw}D* z#&4+<6%<95L$As_Gmc(1;D{Ey@x5it5iNUDcvI!*4aU)B*voQ=ie+(hEf5g#71*#G zqB1!85FEWfKzf%Gq%4{vtcjx~=zTdhmP0!Qf@s+s-^V(FcB%x4Iiz4Pe%>|U=LW*s zY0M8Ti&OYm<>w>D4=sqp_@QE1{A>XN__-My#t)Uj&%eRXR|BLkI6ob&e)ARLDJIZ& z0zYi^n{Rdf^mi&h1x1l1&=)evM3D9Pz4)vPTmI%dW5(F>H{Ys^eZv^LyT}+7%VO*i znX&tej8Pek{S3x_GY$JPQM9s(JDE7K8S!}%o1mxG>v0?c|Ww2#;Mx{RoNPlp`UY6@AE9KBy zI9kH~6!NQ*CZm)uX}pG-z6z)IBvJ^})O-ob`3MrAP81B`Wd7H981mMiU)H=kgmrK`J>(gHU_aU}H; z==u~jeLZz_^-}2)^Gm_#e13gK;Ju95`W&)CPnE4b8CzdqFJp^}WwG@$5Wv>A*f6%J z47LscTl+bsKAf;$Lyp}E^qe0 zMoU+JA-~)LT|H3K=hD&TR_PM+OTp+oTYD0?+nBAMkQH1iTTaGSFYIM(QL!wx4g&&6 z8h{PUFDiqrv0!VoQyS@%j&e%FIBf$V^$m53lj>^hg^@~*u}O7>KsKq4zl)RVmQQAl zV?hmq5f&5`%L-~V5D*k!ONz<}Du|%`PU%>ubTp4>3`I0niAbJQS0fTz^H@0`YR$sY zazMhgVTgG?w&*z(%kn%Xdwwi)7$Hy@o@d~B$|)tBQp_nuxbtyHwat-Ioi8NdB^~nA z95LB@c~V{Wp3UO6Z;p14!em)!DVSo7LdCK|n*szxL~BN|OrtVFI{~3ha7xEHr5umz zWQY*6Fqb<)jZ18loD*Eppq zPH8gtoK}+3rc;gTd0`4%M2oP#bh7Gt`>|mA1)`_3Smptq#X`lhVmTcM2w?#W0e?^# zvCKp)Gn~>XJdiW6UmM5_H4w20PAM&pdKSl-Kxc7Kv8*^Q1OnVY8yl8QR7M>05yxDo z)Zmn6^H7#Rq|K(eYAA&Up-pC&7E2?G`S8xQ=9IQfB}hyY1%vgTiw*dBn6Q=^^YaK~g^N{wmNI^}VK3u{ie>Th zED*rYc5K*jO=a+NHTb#GDXnx$mvf4qldC>2Z(hJgOVO1GsW{|aEl~6#YWh|=wMWuw zm7;>8$Z}|<%roQYas!TN{Vv~XV~$>itguSu=o-e+E7;38qGDMby$1wv^aeJJBPxTV zb>Qd*r?i$6L`!m^-UssLLu|AJ-5|%ta%h7<&_}50yGcjT29+Q&hZGFP&sqb1J|--z zAZm1lxf8O&O)5X@89$$3FXM-bW%08M2#EVDY#2XO20yohpWB?$X3ozKa=jnr4K3KE z<>xlUQ%s<{1b%)-P2ZimW9%-KpMs*u5@@qbG7)5bo-fY%{6gq=88h}PWQ99b#_nK@ z{f51aF)EhDn4=40?7skFj8Pek-3P|*;dE8Vl`7>;7i_e2-6N#ag92S$QPcN;j;;q) zy2Nx+FgnjxHv)gqn62)R6&_I8x}UMN2lg_ys8|+T`vC#@)e9TO7L~!)cChuBQ`*J} z+h4ACfV?>n8!cgv3HkMuKo~8w=6h0i{5_=-R!|gKer+o?zYZewr;Hiv2U+1sm9Zxn zV+Ug|V~mPrF;)!(Fy_LBF-B!D_8b`7!Rb0ot~5~I9FC2at{p;ty(rLi1Zw(T(9!jx zN|%^l3P$JiixzqFy=cr9E%8=(L1pWC#ui_njf!Ql)dXCyRgVp0i^^cDk1Hze?UH)C zq@FIRhfC`2D$bVC5>>waT)y{}OQsk-9JaShoh0n-l6x|`6zqw=i;uhYaM2^T^nypB zJ9h6NR=@A;0@1CoTG-E}Um#lEqb~ThuZx0Ngvu<3s8|*&wDJ^y&ccSVLS?YhAFLeg zk`8i72fC#FIVH3r6&RB*AydT1!73kOMjRy5L7Ws0l<6Q&3j51^5Gl(0J%_SDE(9w8K<73PTWV@fv%u%m=lt{5~3M*+DWLLd%X|aoh`B76%o}ieozv5Qn_b6#k$x z;y4CzjB`n2T+%2W#1jx{gBYgxJr@JL=q1z*PH`&#UL5^6Ao7<{E+6m>okIT|((6;d-aActep`Dji=m06oou`E8m00L;B^{!ZMQW<XJ@&Nhk4GDpA2#@A7q1!eM8XS~Z-)bog3q*r{?ntYJ@98}=kQoK7`tci1b` zw`*8=kJ_*^86SI~GUJ1aW$|$!5Wq)oY#1L@1|N;!W1dSo)g{ewNwYW^w3HLL5*l`% z%7oakr^-aIhMglc>@1lHp<$a?AO``M1wzHL0-*(*5Xhm-fBZpZ1adY4`HM?B(rxJIlb%QkS&EC0*c>&UZ;|oEo+W z)7eT(A4j|_Re2FxdWlR6Yv~JwmOfwjyGkTaOYb+vI^R|;{h6k@qt_IX(=z+~a3cF8O6QImH)BjZd|W{ph6vdFjq2x#Q9v0-FT8Dwk*8Jk?v&76q~ zu^$x4Z99>2c9Tkjn6o#lZL5rGZ)L770RVHAieQ=aVmrJ_CC2ir} z(o#jfdvqt3yHtk@cL?pa<^M~&t%AwIJ?+{}-lMkL-HeRYsLaTqVp(Kt00P==EjFy( zs0=a+Amag-bRTEpX6y$=Lc2Yn(jd0meeK%qA?E5v05DgnSeC2z00FMv$~?p$REDe1 zz}2T*(i1M}ahLR{OL~O+d@m~acIb|}r&PBKPYA8|xY~M!N9F#5E;b**Zu5&x?Rf7& z*emR4*L3n8wdwxO_$Z(<tq-)wkr$zp&BHyu1Y`sUM}qT;Fr44=25Yn!a~kxKNV`IFWju_f!H3iXv$j z-Vhl0hY)pf-t#>Id(Q>Z+CPi*K4gV=UHn<3cNj+>U@zl{ie+&`D*=I;Pq1N)O=WQO zDLC5cl0M=D(b_<$_l>;y78@-=JLTBeO!^lBLEodM?{ghNU#J9$8KPjY;lxJ<{QN*z zUl{ZABV>ioRenBW{QQKyj2|kN#m^qySll*j7(Y}7KYxOsKU~som-M?!`jxZPL$1B2 zyy=OJmZd)sRWXemZZ(a1p{CF7)?PO`+>{7xKB}N7vNYN)Q_X1lT{w__HK43F0Xy7= zDYX}51-qN4l+8^oyf^kT%BWZtWdnc!paZdClu;R!^>jz29&V|-Tk7gAPTM)v_AKjgNTz?TO#eZ6&j?WOW1W|e}$=<4ofvwdt5q${w|1G9docm#S0cQ0eQ zsvs-$R_W@+=<;DNql=1V(RB&FuJG=x()$d{oGPtw{(D8+K)4KtXzA%yzyhB zWvm~fDrVRKfw2H;`VMt#FW?5Kj1?3`mSKHm+8JdB2$bz-Kv|H02N+Wpf~;_;N?CtK zSr~g6WmGJSvg3dN$`aTx%BT#=27^8KY&vP>?n5gmbZBlu;R!ML}8E zEd||@pYufvb)o9T@@5$}TE4<^s4T-00$-P)rZ4WsthYRLm_kE`gus`g$T$iL9Qh46 zx|F~Y#vCn&tPoc@iZPBZ!(PS_70cr2Iv^nME3si5Q5hUf07u8UrJP&JaE{i>Rj-#f zH(;aX=s1C+NdiYVqNeWzH*RqV98D59QWP0SIf0{$0Y~cyY?3iY>me(gpmH>kadZ>* zGLEQN7DojjfTO=*!#JWcI9dRX8r{-7w{)son!{;&NUlwbfo0Ps?9giy_<9vJedp@arju5%b&|G-{G7ZuB*YbOxE60MfTGK|Wg>vGVw z+$~+=mM(Tn7rCViIccBB3ZKfG&#=*wwj6;Klk5tCw9iq~x6-YhK)XUEt)M8fB)ddr zp0ReZz}iK^-xnG%_yrlc!kED?AuFs@8C<~_q&3kPgH$Yw!QX%Y25Ip!#vql!;0<7K zty@~-mR7r^YdC$s%eDU_Z+2s&rEjeqIm@~A0)78QP2V~led|^F#GF$w7<+33##Re| zUt_@DA7o>_F?+NyT49~a-i?gCKe3mwN5!((Gg)`+Hn6wZEp6hwb+qo-X2erWyE_El z*t%o4yR~zBcc{D-6h)SHn`H8dIKHkCTWstOV^Y{+W4EiMY+=U9zu%Y; zS{1EupGwHRj1XE4jb#ZH%OYe15I_hmkH!e0G6;DLgluz54|7gN%Jpc;F;pLojh2&b zLY6!sa54rpecRpInZzelP6~=5%aVr;vScg)JYh`AILHdyRZ<>jq#TXCj1(%CMG7ra zhA3(6G)4-QLCOx0@(gDrCRd{6$xt_ejh2yTge-YpU?ho}zUSPSag~QoQ)zhlyugT} zs7Z|!DLrq@LK?Edb1DnZG8SmHGsXfH%VJ>;5D?jPY#0kv1`D5ng^%6Rhi>V8xAZQj zqXAOiJ8n6qQz)j7g_u56(t~cazpoHOw>vQ7`X_tF=UsKD!6K+^+ErfX^-~rdtv1G@ zqheXnodEfcK1I6P$V27ocosaTfh_W=PwcQA+X2bJM@4|v|) zBX#vim7d}x+x>FY2jtCz*l2r@?jH5b+smU)N)}Ml*VCg-$zC3HQc_W5eQH;LV5W}c zWTpByKMOxZV7=&LsO{&rABL>Z)59ks_hcMBg1w9*Dwf63-+=&X9><0qdsGHT`-7u> zJ<>j$pdE6(XXVXv*k}pbSB{4b>G}!;J&&5c19b%TRS6QaLcw7C>|?;s3xw6zn4cFR zD;%iua{%M#CG2JVP_Zn2-Ub5rc?}!J50$}>2mH7^(g2UtpHuXXT=iXf^By)@id+b( zIC}F56upm{zABIQ!11XR6%<95LjzP^3jNi;c@BL*U_N7xK7_1LrE=tD9DRhnj3X+R z#nHDw07su=!#JWcI2sI&26?2zIYHma^}d%kyRgv`G)Rtz< zQNKS_AV^VUiF3FCDL)gyP-9Ylfvhk@CFMv)%CFeVNTFg`r0lT=BgKXdBZbN!ulZ@fo)R`Cne6cy>LGDhK--nJd( zVYB>fU3Yc2!Fff#&5C{}g(mJp=KRJ)?h9FAyh`M;jL7}4mk~+DvWRp70jB$6!-%9Z zh)jaWxJQb5q%ddEC0BLJ8xJ;G7UN2!w(WQhTwt*ZHGOFviy4(grITW(<{}1>7*$CO zcb>$7WG!P%;^B}L(kh85M&c3J%SfbRStO1D0!SQ!4I`1tAaM#voa~V%d8COR>3GiL zSh@B%d2=*2S{^4O*kU$L6?i-rHGMTY9;d227K)0LjgwTy3KLZ#k5_jaWTP<3Dc+9? zlF_NgbcP@+)Tnfx%;*ebFQb!+Wzm@j0_com!|0?k=$s8Y>pfDPN2=vq9w%2lUfxW= zM$2Wr5-;WCsREZLpr)@u$K|Oimtsy9F(@bNR4QvrrSc@Qd8#p$Qy?oes8r5jRGy5z zj7ln&O65vV&MxKb)kL8L`n~{tpLwKDJkrM=>BAy}gA1RrkcLx-Wg9U1dop|^=?ozz zZSu9qm$Y~2#EOATJRE3Wc?utbfW>q#d~r{kvtK`!F@>)vhB3Q5)L>V6wk=)!Q%_sl zg*c_83GM(^$v3C(w)4AH*xD|l{V68kb|zL1g!aUWoc*Z6C$Mm_Vqw6TA3eC#V$Lc) zyGQ@vu?@uToP7j&Jd(Bj9X6ZIPfk$@3vvcp6)oy(X&+wf#y;75j5QbcOr!H14S&D! zXe{!WzF{%_^nZw{%Rp#PtjyWRz|40ZZ5W;+ci%BPKbzQbn{nq>x$80z+GOWwEvY&C zF=#xnm9rnqNV>fpNh(`%La>WfxdA}ZGMApP@r+7tI%oH@Or=aICsPwSdx+XF0fPRA zO#QD%`j1EY%_IF%%+zGzznV<#;zjio>9EvNGWAc2F@s>4I0rPFxA2QmrrNwngE3vb zn@ViVXDPgs>4wi_Lm$ zsM%Q=lq~S#R+d+q=Ph1tZbF5^JTDGyC-VTSQJwFx`R01J(Y9?l4R9O1_?rbFS0tyM z=}^#S3s9x83n{zWZUGYWnTlok{G;sicSWD644>D+=QUnwHTU@^?DwsLhxh=dt!*V- zWUj-l%Up#uURn^IxmZ|@zi*ODKErsnhOM;6AQFBrP zO!ka^x(0Py5eX_;+oao)brIB(y*D-T06;E(RrOBZi(4WTO_ zRV`;fi@6Sja$Ik_3DJOp_1G}Bsf;jAMi{TuNH5h$FBBtb+aOn^{P(?H<2!W9whP=Y zB=Wu>`h}XMi)kwTynPqI%gd@k^s?&0D-`+(_>UrQD}ZMDM>~Aa)C^j>_~L3CDqdWj z9tI@3_F%`%>oq71LboUs=;OwdzvLvw4Gx{CH)D~2s)Nj+Aq8xP2rrq)%2&yj~ zydAkv2^X$pl(+=<+rEbl`Uk>3aSvI#_#-8%3l?8RmE{oubD(1_XZ87u*Y)%bpRx@x z+S*p3O*-w>E@yhs`F)(WVfZ0>?u1XBiT$w7#C`~3zqYfnyHR_ z(#O8lFm^V6BTD2y(B$1a6MGnrt?g{=DOA2*i2d$P#XdofeWcRv>pIcy+^fxQZM)wK ziyb9R8us29IOL{2Zx0;vUQLJ9GivqG@1l=`3hQO=?^JL^$`pDO7C?#yH?;86rME52L!A|sE z_7T*f4a82RZ$iqj?!S+F^jiuCkB~2{hx9#f*oAd3c45@f-R2syDR`@E!07iC^=+LB zr3R|s59-K3C5YbaMyuXJBeWG&)C)Wc{IT#Ae?EpkCw3bM%P2ffg|1@}>p(~+cEPUg zw5xI;`c4#{phCq!^w}spNd?D5`@q*wEaS}D_7%<!qD0)U$Oe2Wz@VDli`^QwTgo$xa+pRQq*k>9TJ%O^Dh6#JnIo8)@8iog(*zjOeHH|Q7 zl(aA7YkwdxSE*Qzs|Nu9A@^k-;twjr)j4o=KkjEgxzY%13j2|Ryva{@k3NVwG7>Uh z-)Tj$(%_YJ)Usn0SEb*(Y-0~V>&OaYpukd0mB9R1>}BzwVp;JV3jp98gAJpe%7|w! z;_1iZ8824~V&m&S%{LGy4D?-XcTxlNn@0Syu`wH{9e`w@f2<`wsG(7vosUFO4J}d} zN`-+}=uiAmV1GK*zin)kEmLp^<12!?EKn+z({Kyr7#3i|0;MtnZA74>d7#a5rB-Zw z<8*YKw>|E#<#tVV*zs10gWr4M!E(?r`l$BjvBQJ=a5*3fal$Sn=+`?s zqkyl3gvCJDNq!s@N(^G{3U)|UIv8drEsx2vCZVr_8EXh981yeIkeyMGB5TnH!!Ue- zkKm7e@T+nx=o$z{*jeKm#c7(pQZ!L<6=~5)0YF0YSJzVO1v_B%|8x`GaiJ1I@G34K1xU ztmj{WuY%fbZ40{EU^NR_x~Z;q9t?5O9=O=I+tUz5o0{j>iduU!Q4*pFtE!=GjW z-wK&YV9n;17g$<8k6S*+!t!6u;m@*!U&i4tvVgx3GLyg-n^|W0wt~Yiw}8LI660Eq zag7DWRgjsuc!eeWjU0Zh1^gOIjLjTlqXotW$V^;ZZwY@Vhu>lWf2$?N103UCb2sib zgRtBG29Zg>Vs|_U;qmn?i{`c3me_6f%1ZQNt#(HNyM^A(j^1s(t-IX6p)-1dyY!g3 z-ECHOpES1nl(pSgxZM{~(WFJ5hsdOheHJ29Dqe-qfQr|!+k%RBxJz%D+kL~z?z_fz z-?O&+CAa$-DwB(6<q75Guc;3KTTvm897t*99j zCLl8jI0lhn_So$ah)j-BbiqG8;Ob!QmHKz_(apoX0WFvB3B%WF{`2WeI-~hrhrA z{(MV}6&z!^xf_?5LD=mVLu8WMcE?Hx4bDJUV7En&d>wabwYlAEtn98ewtKy`-CMcc zO{i$nA~!>1a+u!)ktr3oL1;k57VNg5;$H63R&%>|S=qhM*zWz-b|2?T}{gm3deh*RDO?({I!67pZ;^bp8QoE{93iPM81%G91=?D63cT19ji zmm5Sh5<;_xf;^(}sAU$>F_4+KJq{vMx5q$e<@P8pZ|64HuHn8-K|M3yCPUWFw+hzI zlQ_JNRgc|1k;??r3o(JlPNEIm^ehY0Ga)l+=ot{T^Gcp+JB3@;dDSLo=QJ)CJS%4B zsSujAWh-}jA!?cN)dZP|XY;vbW6$Ptc{|V0T<3A~=UABkD`X~|oduDJXJ>HB#-5$V zZLEi7Md4!_(IejSIu-U9wQbNFjHyfLq< zxZH@>JGlAVEX;3)%!JoX5Sj3LGq-H)*-c#D&NI8?P6*A8k_Wld_o0?qGTZ~1iDz56 zWn<6o;_`N$;V5~Un}5Q>{Ns?BaP}xfCZ0XQEgO6G5SO>}%9C|VPXCskeP7y8bpSk(TMMD2+acjh+BT&!t%T3@bLaC zj`6t##;1^(c)!ye-tPDsLNo7w;FiC$u>6fVJiOn{F@8fm6AynegRt9wf=C_$v};+r zGqzpMZ)ceof$Zjj242%MJWG2|@$EreL>)Uvs!$ z^{8kCMNm5p3(;MZvo8u)cO zc3b#$A@}QiR5YQo4I&el&wuqqR9?&F1}<-a(7@%JvD?DsJGslZqhdS1 zxxLk;*cpoxva{3uAH*oqD2o0Qm6}v5* zeuq2#7Al%F!W$47#zRBQca817XKnWrZucWA@K24wKeGn^o`ZjbiY7sQZDn_tvE3i6 z?f%Z~{$d6GA7k*{*5C*9FOCfN?XPK4&HUUxkeLL$7et1wh=;i#k`qrzEIP{AgwX(Q z`49`s{fyw{j-{^=Jc$_m;T*o&0=^0|lfXPimgPReWn`HLHk?}?Vqtl(Is70?ct3|f z#sYpEWF~=)F}FO5Th{f}%0$};E;nk?H1{lldP4W0$)y-%CZ0tgGRdV7w`}ZLfXj_M zo5(#o&d7QfHusq`x1KRaw>wUN(4dQ)gxvxM`b)Cu+@%_GyHl*}o?>jb*4plTZueAF zG--%A5ScW@EQm}FYP+KmLIWzAu-k%)Gq_8O%vTxt7ZfT;2qsfy=jGw}s1hbC>TzMH9d7;C79v+`{Dse%%A1 zfnWDxw}oHh1{BZ8qX%dzYI@O;keSeY6h!U939v417(^!btub*G;+FjumX9@uKiU#L z%i&WN@CnFF0*jejj#yfr#4S&-uzZ|3e9jWSmcvi8fUkkfB(N#wmM2?UZs3+@Sy-NF z4nM;ZzL~=}S-{VS%p|b6W|rmWZaDlR3-}gGjPp3gITjdyh0Mgovn=5+;_w$(z@Kl4 zv4UePx4^grG7}dswuHZi!(V9uztR%pMvk%8+>JG65O(`&h)ntwyJH=M2HoI#?6&9z zZ{sfAVs3Y%mEA4Ic5k<~yN%m@2o+6Qp5-8Z=1*HO`gidP{rq2gtTOsRMiLIWz^!fp#HKH@IDZ*KQpE4v>X+udnx z_Zx2aD^xV0;tPljsh|msZ;kDKXKnWvZudtk@L!F=f3pU6IEy2VKT**ns6VXiRyYkC zu@bv28gWlv7DGS<@=yq7ijfgF54R5S?+D^r-;?Q3lJAZxo$ZnwV`xXT#aZ4Ew- zgOAo$)Q$-uGYR-8hzyCg+lN79a+K1TkX!a!SU%Pq{%A}1EQe27z$YLx2`pxAIbvyf z61P0T!t!zE@HtEP=^Vbs0)7f)CV@>hv&@E0^&EbN1^g+N7>yibt_4N|WF{`owuEox z@Cz;An=CQT<``$0yK#mYgx!7`L?*dycbo&E!5QdW?6&B$yuenA=@zW%njyyBn9i{YrFSzyZ2auKVS_0pf>9Q-j=Xo1kGuUyFG?cBCI&V|s7&`WqkOHs>=&?S(WxP1Xcrf#1P zp_SWhT;9%Yu)Ui5b~Wmm`F15_CcdqN$keyXxozW2SkC1}zOCoJ-GF*#zO9AKBoo#^ zWau`X-EM-=ti`b2oAMUXCJW0qo5O?IyE(>P78rLxX5#%8b9lSs9th36e~4Rtz{2u< z=J4?T?;PVP3ydcqGx7d$GkClGQHZQE_7N^`mlbx$4hYQxe~ml+GHRJ6%!`m2W`*7U zJhyC|ug`LMJI}z`JKX$RsAs~<8|K#kVUCVxeIV4wjc1zQ!)_r^{SEZbxJx_D?S5os z_j6;rUs&6s1>xO_Nw zxf&Hs{Ho%1jgK`CmmBzX1cU~D4Z>~Dhz#SQaqjKLcJHvZ zdoQ=U)e8JRWAOW}!5`<~+fdOYsE4iWZa233gtgsgx!q^1z@IY)f8HAWQx5*IwxVW6 z>_f;*0)8JN!&bE0--Sp{JRz~@X(e`_<6Ca|YYWR?n!|r?3I98X|HT6SC&)|!`@!7u z_m-9&p5iF-PYcU`n8WY3gx{0HclVe&-xVU0R;h%@q*d&Wo)8)w?!BX=9%yX0ueDt-x9dVhlXe^ckqH(3Au^?+3PJ-aeAsP4#gW{lLFRT3x3W9L*zQnk zyT@|7<51CriZKwGP%#Q3tCPeCE^l`%+a2Q}G@#0l-4;}(xXW==H1R9S?HZ3D!d!0P zR~kYCzcScu;n&IBugR!rLggfgOkAD_krkE4bGd=bH4qxOJQcewT%N;Su17@^zv{SM zV=8O8+`z8}2o3x?6}v6``VxLs*ee|0dk)3SR7J%udF%K=+5SjdM@8jNa=G$nw(VuN z+dl*Fgr-H!b@dY(&SHxMD<>p*S&&b-Sn%~?oLcPmk0A=zx3o4i*3vq|hUy<`>j)T& z+3BfQMK8Gh6>3G!SkOHEwAy*XlAOINA+EGneq$o;Lc;INgqU&pQ(>ixS7xQFvhAj9 zyR$8^@L!-TXX$v+Y(x4iI#9(WVb(7W1CakIFr_(mKR^b zcP7{v=rw5D>=j+!tm#R|L6^5`_9V0}|Ej?f)Vp4u?bQuD z{V|mt$Q8C}%+U(_v^~ke3dc0r(TZs-l`AXRmK@qWRqxR6Q;k@#JN}27l<^#YMyACbv8K!yUn0XpQAsqfNEOwbMG5YaMN>HNKrzRF1GB zsWe1NX^6Dk5S1CZA-ZHa17TD2_%z$Rp_Gy||7y2+?2ZKX4Abn1kq2rOIW4;OwDn-w zZL{s!xc~m68j@pA93BW=_2TQ7&T^g{a9}C>$k>`M*B3s&?#`N-i|Xc1Z<;Y{QA=Gd zmV9qluB%e!3$>2u=TYaV(V|~ zw*S~R=atS2oR>RqcR%Fb>VCmZeChte`;~ix_iOh~@4wwI zc)xM~!~3oKs;ckYe|o=nUr@En{hQ|p_rJV9x*zcV6RnJzvS@mw!S5@y-eO&c^)fZJ4Rj;hRxq3_WD(O0@?N}t~KKnXd zo&~Lo7WZ7&b3@PXd+zG_bI&&CdCtY4;6mp`&ZW+aLB$H^N|183^BU)B=XK5-o$H+I zoi{l*I5#>sIX64EIB$2}>D=nP*Lk1w0p~-`ZO+G>k2|+JpL9Os{JV39^Ev19&KI38 zIbU(U?)-=I4d=g{?>awle(3zzxzqWn^K<7e=LN1Mu4S%ET`OEyx>mW?xUO^E>blLf z#Z_=U;BIDy?dAY2ltQepU`~2x_7((aR2FE?70w4vedK8bE)St&kD~< z&()sQo@+g8JZnAId)9ew@@(*I^xWdv?772pr)R6@1L9-cP+qDDT(aZ@k}ofAaq9{S}F@+xuVdpWgGTE~r{k zwG>Ugtm@LL%c@qOv9Ch2udZ5CwHA$jW7T>z`vx@mrmD?Vw^iL>_t^$ybGJ*38mNRUsEG+!WDc2(Ww zyQuo&>SfiJRxhu<3@LME^;Ol^RIjSOwt7wV+Uo18Z>(O2G}=_Xx%yTl(;d}!R`0BS zd*C|*-x~DZpzjC$HfV{oR9YroCasWGN>@r(NmonPNUNl4k#uXN>!pKi{cH!cJ+{Bi zwwJ%IY5s!24KtruRB8Y7Pn)g6=ATtx+d6p2kQEj7Hf7IgP4foNpJ}6mU*0o#W^;XA z>uL4af!+mL_H*b@&A-8Q4fDLSX0v^ySz%vJRW<)uo!Rr)z6$(S*f0M~Qvn55r=gMU zu4HxYTVPnH{tULe3#-%jS;IOlXR_U0S)G4OHLQcKi2ilMe--xc$Suu3^5MvlV}>|| ze?vzN88dA3kfB3{3p?@W&>=%cjvVQ99yM&#nBh!zN)O`DZkxGe_9Y+HkN)31JvaVq zOXl|L-nifGoAAWh7j?Dm+q0XEWHFq^Z~|xlM80VUu{}u7W{xTkve&#~Fuf2Y6Hf4rW;KS_E&Q)zqaNUdRBPiX_H_r)bP z+h;#hi>d#3J*6E;awbTB={#yR^&iy(#S$fO!@TSs30 zvq`h)#Q5^JPd(P|G^jsK7SDRc(_(FN-JF^U3$T%Y6OApcc?@fD${bv0lV&!x*rX{9 zHt9s$aGTUJb6%!tX1z_y&BlMN_;1EAn-qzoPG+J_icP?OXWFD_Lu+ovsnJD^0FeI< z*S6N;@23Cb>AUFs^p;j!glSLbEC$j0rWvQgyhQ^sqr?)s$4XrITLxu=p`dnTf@aYVhK|Yor zH7+!@#~+Rn?;YFashdvklP?WYMcTf8_fyB79r^yNnH!1 zduhMbr}cSaO8FU|scoGTIit0?R%UVOQE%LR?SL;fE&lR?6IajJdV|Au`OS7))%fw# zL;mSQhGs&UKsug_`D^{Q^SjzA@!sA>`hv)j_?nv?C+wACUZ_1h9S-JmnNR?37pqsw{H;;=+aOdQ7Rl#h>3qOnS7(g9QBye=&c;EZ zzpll&_ANr~;rUQ78;V8a{sm3N>N-zu6|2XBxll9`PoUk4&7-TnMW{Y3m7 znu+Ikh_$1UY#^8jr~IcCUC}k>R-yLLTqc%_1=3-EkwINj-78cc7Ego|@nAUSUsQBk z2mOFpJDJX8Qi*)lzo^*sy4nS?b}XIA=aQMEf1U~UHnDaj703m{>4<-kNe(_P)E=IV zM-pLB2)~Qfb$mamsh$pIv)No4j+<0}TBtrWnu&yysaV3_WR&53E=1k(yDI&-g>{Cb zmlpOpYuv^YYw|N@9dSyxu*244qtIbRW7%jpn~VF$d(pQT_F327qShZCOl3m(Y$oe( zu5VSU>*%>osD4x^lZZzX(KJ;rwrm&qxVug{?$(O+Q?XD0xsddqI)B0VQHlYb!VQAL zh)ggY3xxv-KfXIRZ~O>FqpNIUyJF&2L1SbhiHShh$_iI zFp|s1^Gs!?naUlaN+N}BGM9@mm4#+1cL^$^@_}$DlFTKTO1D(*m3`<2~*>pCO_KzRJN!A^q-8QRfG9n#| z6UR6YHaE1+F>aL}g2K>DA{xUvC`oykR_g1zm&ro?;n8R`i=H&a92)OMhRM0BOU9D~ zouTPqIGo7^$woA5Y@TGcC>@o67COo>lmrdk5i&>67?lVG;^=kqh=PvshPpbT4RvjP zs-QR~n99Zi(In`ifZFT!kn{2(B`@a*x>tvJ!S2O73~Fr_NYiIkqt%zK_%uhtYU5!6vt#k(M&dylG}vEtku=U+$!j1 z{n1Dwmdu2++L*Nfx|mNB0Mh;x4zqL;r(?NsDQ2yL9G^%{0>-zW)M5R3lkwM)xqIv0kgCJ0N!oS|iXY=HiJs{L?Av{QFc?O2y*25V|A(jM-XCI;GDA zrIFcKI2=v|5!5`LDV={`idq;dMKY;u5T>lPz817bWP_<(FclzMmJWU+D2>c!f{`eO z6EL+%tEF@BJ3(s{+6v>XY=pwnsp)#BU4q)kR3a3OXJc{y3>@5=Hr5&YQPj#LGSOTr z7ll@frPj}a)+lreu|Ob|@Xx@QU8|;Z@mGynESt$kgLz6QT|4X4eizh6=F{OEMh;Lr z%{sE(qE<4EQCt!Ovl*x9T-5RLKS66$9K-ZbI*)cnFReSkbUxZ{RnPCE62VM5nhvJv z0P8@{A?S?`MYGv>0#}c8jOi71{Y|ByI4Tj&WCHmd(zv~z&e5)-9x^f<%w^DYv)kFz z>2(+MM#thfGv{&nLI+z1j`k20!>ME_7RJRi9d8{d_7oIH1!K`jBo$_doL*1oX>UPq zbTk{ud`I!gBz6vxEFsYJSX-02l{C%Qg@;^=HPkig6ZLZtJmE^Bla_Y)P< z7*S**F}RAOuLH#c1jRAwd={5*5%er{0O~b$zV;P0v&lp@gmIaC40fQ|PtY8Vp>-JD zw0s!q6?IV_A}S_wiEKU{LaO3O>_BmVpcoAJ!+~5rhV!a_mV7+2F&>@2!gR_MPh@+` z=jLt7x!I+~iN)gSY%q_j5Bd1)G>%7$gK3Z;`q(IN7Evgj#;MZcWD+521@ea-hMmT# z7IA|9a44TjB@(zqnz5(@pnYV5UQq}dC;|oin3{+NqtPUQ=9LuK5h6~|AJ1kmK#4Je zIsno+Bx!+iDa<)gT=Pnc>qsq3BpC=HEY|R>`!Q!)=g&|PDBuqzBjH>MgP~b+hii_b z%f#U#PSBqXCnK>8rWVj*r8zW03lz@B1CbD>`;bDV0gV!YLjGVN7tJN}xc)~Db%4}I zPNJujBpM?k1^u~TB9e;)C^q>dVNQ~c>~SJc$d8NCU?h)g9k|pHlFp@LM5KT}pN``? zAVD2SQ%QO47jSa^6fUjffhcigb

      &k0y9D(W6NoP4=kPqbVLu^{CFH zX&z1YXog2KJ(}gwsUDr?(dizY;nA5M&Gu-HM{_+o%cHYBI>)1PJvz^$^F6x2qj?@( z=+Q+UUF^|(k1p}(Qjae4Xn{wUdvt|I3q4xo(Ul%u<=ueOS^5}1m{_*HvkFtCspHe((x+BF?del%pZ4-;Z=c%u)YhkV zKJDYvzCP{e)BZjk;8S~_4)p0DpE~$-h);+5beKPaSgH2-pL+Pz)2CiO9p_VTpZfT8yia|7>gQ8`p9c6e(5D=qa(&A4Dc`38 zp9c9f*r!6DPVi}nPencz`!v+2VLp}kG~B0BpUQkH_i2Pr6+Tt^ROQo1pGNsK+9%H^ z->1N*(5JLd)jo~!X{=AQ>G`83U^=|0Wy zX{JxJd^**q(|kJJr!#yy)2G=!&GBijPiOgbwom8ybgob5`E@6#nd zUFy?iJ}vO+a-Xj7X`xSxe7e%7t9-iJr)zw=)~D-yy56T7e7e!6n|xaA)6G8J;?u1@ z-R9HnKHcHdoj%>=(-NQV_Gzh4_xQBTr+a-`?$dof-S5)_K0WBu3ZEYG>0zH9@##^Y z9`osOpPuk(rBADTTJ6&spPuw-txr$+^t4a^^XVC%*7@|TPtW=Eyie2!e`pc)kefr0ze|^ddhyqFl)F7bjfEot0OF)eRY8=q60W}GzX+X^a z+AW~w0ksHd_ki{YsAWK{0@^d6)&cDm(B1*H38-yA?E=~-pnU_{FQEMcIv}9-0Ua37 zK>>9L=-_}33Fy#(4h!h;fQ|_0$bgOtsAE7!2Xst8#|G3Xpw0nx52!~#Jp<|$&~X9v z4yaE+#|P9mpnd`M4`@I@0|UwlC^w+Ifbs(>2xw41g99oI=!AfV1XL7IaX>=@8WvDV zK*Iwn4X7%hi2+RtXmUWc0Zj>LT0qkSni0^jKL&=&!H8PHb&{TR?s0sS1%F9H1;(3XIH3+VTNwg$8A;W<3aLX#2ZwY>NQZ`WSV)J5bVNu; zhICX&9YZ=gq+>!lHl$7=bq=XZNL@qf7E@q{5I+2x&-2MIjZ3G&H1PA(ezQJfzZ)%0em+X+%gB zAytM{71GF%MujvwBrhaCq#&d)q;yEtA&m)XY)Iom%7j!C(upCR6w>&RP7djmkS2sQ zF{DW$O%ACxq$wdy4XG}qX(3GyX+}shLz)%RsUe*f(&-_c5z?6<%?@c!NOMCvE2OhS zIwz!aLpm>{^Fz8Iq05ZVu^|kZuj>wvcWQ>5h=@4C$_rmV|V7NJ~SyC!}Q| z-5b*KknRiV{*WFB>A{dzg!E8I4~O(fNRNi}SV)hD^h8K2Ls}Km>X6oi^khhDLwYKt zr$hQ*NY8|{E~IBedM>2rLs}ow3n9H2(uR;;3hCvLHiq;{NUw(UT1c;l^hQXVLV7c# zw?cY5q<2DkH>CGMdOxHOLi#YIk3#x5q)$TnG^Ec$+8om7A$<|jmmz%>($^t<6VkUK zeHYUAA^i~2k0JdO($69N64I|BZ3*eOkbVzoYe?Hd+8)v$A^jQBUm^V+(mx^n8&X!9 zC{3v}HAqu-ni{5Qmozm(YN|Btnx-acYMQ2IY1%DK&C}E(O}nRQk2JMRQ>!%XnWolh z+AB?ar>RYv+NP;pn)XT4zG>PoP5Ypfnx<}P>Yk<^Y3iA#UTHcmO}*39Cr!tvsc)M4 zrKx|K2Bc|VnsU;Vo2I-p<)^72O@q=jI8B9VIw4I%(o~eD;xr9S)37v^q-l7XO4C%9 zrt&n6NK-|cD$`VzrjcnHm8Q{Y^3vp|DM(Y8<_Aow(=;YcW6et@nKadK-mWon6lWgy z)Oj;j;H2&jd%jnOOm*sbuOp84&N0XTHi=D6DV|!A6S_BWhIg7dNkuYp9cV;A>@UR- z#kWJ2ugUnu<9*_wm3l|F{J_+T=&+KbGe(#v;BX=-$CxprXp0QYR1HEqDQLMjMknB*fES_z%^rG{5D@ zq!Iejl^h7y%vMv8@8lm}$eOmtrAUqB9G7+kYH^Gzc5>(*3ejd~s0=}(L zrg@spNyE;^;FHA^{1T`Wtz-iAVrB3f*gCt(Jy1t=-`GejCP?czy$A7w4!U%KF1{4l zABAoGdX0F{0BGukSc%Sq?VjY zwV4CCBN0ijLe(#e8jz?=;W%Pzwx}L?_7rX->TV~v^3s7i4D1vjn+w18r8x7_yO0gR z@=7T#Z=ngk8SpPiGP=^vcjY39=Qz#!flMj&2^}6HU~h{)eRg_>o0HH$)p=X+$mHC_UXwbHMm3ar4G#pj&q( zYF%%-6Vse5$D)f8RQi_~7jMAwgRMf6{q|t1MD#^?7f^Rc_dtycEk8TthHHl*?!}JN z$4{Epi-)-OW{A64q%R#-UZi7ee+G|jB0BC<5sN`&nkB-?uSPgepZp2t^NeUYPFi=) zA$PV>hk5iygxwWnnwrW?flATLO4XY)J9n^uHsHnPtQMru}6vmp<r>zb_)g?&- zR0?6q95me1rPsijpjKE zzVn*a&8T#-X$Rcqw7;_VY!{1Q0?JiN55$S}zY`gq_dz?N;Ppl`c#&TBO$VXP?JEM< zMXH+|e|XZ4MiKTi6m1*TTQBwQ%|QJuWy{J3V->5^#8Zw7M2WZpmp@2hd8zWXsTUrt z7^+37Pwd|vM?VRFe_oWH%a0n1V<9v<>%GYS92q=D)i(xe?G^D4k1OC8pq*WZCn3ew zs4!jwbsu<{jncKIwCU}fxy4o#EQ^(@MR*tN%r;#%HaIk*Ax!v%L6q}74<{}7MBwfg zW!eyByvFXln*IkUo*h@Lt+*=+f7&PRL2@~-IOvKEyMm!RcdT3ef@PU)(Vsv}&(^2(d&QD-uckwn0KWP|GJor)avJx%#eCT;ME4S^yl`?w%@U;a+}WAtbC;Mxu|?#Y_G!HBF#AO z)Vwa`3$Q3rhCUda&y{vF+*$9gMWwq+!F>Dbn<~q18WtFdF#jkooiG`1Q6vub64?Gn z282@QIoN(EdA5c_=^Izd8=`uzY6TQqZi?9#hjdAP7Pzg! znVn@-=gq)$O&G-^$a*K}Twvd|%0Uaj>(;7dHQGRXgEM1O^tz@fk28n=Aha(NwjpQs$;^mRJYIbpoN}F5;T6^|8cfc=YgXa#A(bPfF5l3K^0F3+HQO5!H=Jj{m}?) z*FN><4>O?5_l1SR+#J2XbTp9P2>U#RFXuVDxKjU0&(D{nQS~TWll2L-jc85nnwVm{*+1f5?h)QZaoI$h{T;HAO}5pCp(DL+7+$0+%c zzqtvnF^MCOl6J zrR~%#JNu9Sc&)$fRyQ;kaK~s=0hFID$xDX|{I^jW`aR zpRVf1)3L69Z$SMsM4Q9)viA}2K2oaZ_llfX#g@V|uM*CR%L{V`mg~@nFG2b?MVdv+ zbIwGzfc8s1s~uLx!{f>#oV2IC=*?ukNg_8y0aL)?cHt09LO!B$=0E&I(OJgLaI)pR zUfUSNj}!LL?GDz>{vu#21Pk`ewze|dUHHL1hIizsQHnJHw1U+0VM&W&aUV!NJ$@{4EGV!G%-inY`%unf^X=K3`g&w7|!RfW} z$mUGg+oQ-Ft2G?q;;lPnlwF{+=X!H*!XtDpheiphMkv=@S%WvToflq1{NOn2)_J2Q zs#OjyZa=x;w-O6W74TX;M#a}#*NkH$qXOHnGCfxrJHj*KQNb#h1Yt}!J}Z}IM6y%W=F zSo3*nXSx+uBwQi4HffT0xh0vD>lQZcKN0t+Dg^T>oq<7 z9EZyHG-bK_OVbw3Iv;A1>?Dg(&evU>=M@qZWPvs_`%YcsHWK&G=DM;lGhTPoKRIe6Qw2@ zB%%@Zq4#f);h4y%W`q!Tdl(8nD^k95c*7wwXNYjc1tk@FV0j6my(yhaffFgf3!y&N zMbTppDj(r&kv$Co1}Ka29vGWVkF=MghAdM`3=>(2Olat?cpSt(geRy{{3@a5lgGQa1<&oZ zti(A3IRZS*uWx77!F<3DYE{K7nR6^L%{LIYV3?6!(U zK>T13rj^CVKT_#*RGN-jHns?z&hSg%nu@a60=!cyy`2YbO;avW?+9ldN-s7om6ti( zeDsv~P#B#eRddqbD&-LKfcsmTWNGJ~YMkfo**A@|z)6cshB^DQJ}lof8Zhje(|Uq> z1qSoBUGREuk8YeK5KZILxM@5mQdYR}E^WZd=hDWpRRcan0X-n$;AD}49RpdTU=t$i z8Bx1^=TdK!@X^M(;s(X#Zk+cfP_3|?T)8uHeE^mJWCmNCH(1O#6ZGaKLX->{ffvaY ztNb$T36W-CNJne0LTi=Q1rW}o$9C?!+gM-3m{dR6>SADziLgk zsDiHrRnS#0`;GwaV-dr?yzb7rJ3}=cjB2nxc4kk!Z?K1`)CO8tI;%g9>Db+tt#H(O zHHvOa$lCS3)BW+O&#tQN>HUmCF#Velwr34a2u=Z-bj!YRn+M+}H>$YNSm^3Kqeo}2 z4G+4U)FumQ{$^B97(Xtot)7baP^V?4hLa|bpHwqB>+D8IY6&MkA5Q#Hd+y*TnRa2b zdFs*TH_$)E;!Hbq79tM=xy@4NcqKhT^LBMrz&&Xrolod__$cf^2^=65D8yJA+z)3VyMYxS_rrCh=2@&?hf5 zfp{xvrR?CU8^Wd7te1@1&?jiUl%v6%aC~e})34$oTQgx3Zuw2=TqR98PZk|-Tm*S? z>&fG6NG<|*{gv59I6)21!fvfZ&x-BqK>1W#jAyUXMP#A-JHL$$NyRJ7@SKKm_xFJa zgBW?vku72z106gdSTkK#*c7k@mIpT;l-~&6Y*klQKehHL;N!!i`4RQ8W5L9J@r92p zag3tDPB%LoRNfI)<~VWjM?wp)SQj-LOiJELptdH(@^Av^w93K2KO}gLt<{2a%vBd< zodUnok|nz=k74DF4;nn(=7Z-Z|T$~fsQ z9IE^I{eXVR>H|SAdPdDBo*g}QT8@{>`^uc`YR)q34p^4M>ogGknFFRcI9B6 zgDct2LD?e{eb&3hcRKVn&S$Og0hu$s{}!n7K8&)n@UFVg=V?_Vsgl-?^}LwlE*lPD4AagZ znpZefhfh{OR|{0-W`}_<#EB_B$;$rrKTcwHIEX1g=kbXdcGiffIhw~7;PEQUqglKw zo3NMuCZ({6s})p$a`#6rj5iLnrF(+=%4EXDGhmr<@m-}~qAn-eS``026&<#3aPhTL zL2X8rA4@Ng!vRBjON|$)sdz@o!B@`A=|a?7ZACQa>q^A0V28`JqTSmHAA{Q~G`h61 z5Hl~a!e_w0AsTXa`8Znq)X{8VR-Cqd7HD22PHDqHq{c5<=cbrlZr2Z|I0J=$GgC|K zg6Rfy2Iw7Xnh2V0UKibO+>1J27J^k}^`pTLz!0~_6vYz2rtcQTbEJ58!w<(Kmg*h3 zRiOBLQZ1i)JCm_ND7w*l2zUBQ>+Ig|ijXEpyc4ur4IxRa&2z+fTT1j)ipqbBcs6mp zs`@j4tFrdynX=aXN2s|~>?l|~BZg4Vq_2agOcIgI6wTTFc@ml&+$ZU5oJ$EDNOO~Q zU$ocqLT8ig5Y*h-G z#CDLLlr;H)xw_3C1LQip92%PEKKoGw)PcrFY}}c4+a(bB=Du+sDLXK_7yKD)ZIz$k z@|ttkXfVrceb?+5>ptp25I#7uWEXvtf%o{<$NV~R3MIfCEjEe+C!F~r$CQ7g)=hf( zeO(&RN#rW)t`ErXK-rPj zL$P(}9E^RO-85^1xvTVus!*<h1=**NenBJ~KY88s>K(K1vyaBlzp@A>RW6*BXUm-mVyLkH#`6QCL+`y~m=i z0pEwJy3wlwFAA#{}i=uN;?H~$z0u@ixgAdq|3Fpy3-XV3H`>4vWzeD*SO6B$nxzu|sbTC5n z1GmE(p{QJyz7s#lmmfHXP*(wUvY=4bxT|j5EAfkGgt79<{NcL!wuaQ77%ke3i~75I zC!zHDiG8q>IM~@qdgHrHLq@s6vlUqruBosTLPHaUiN2BwsTa znkcu5PfQ#+7vl$`tXX*I*M|87?(k@$f?+%?3RC^qONDR+M&%+NmBnhUQLk5CUR>6- zOQ+l(-KxwgJfH6_{u`^mA=E!7sluIjz5=1!7~NKxk4qKr`#uldn7gs1ONW`8RS zLQJ(NcR-Y32`LQIWqQrZ_aoj?-BuUXk@CW{kH^-=V&Begh2Yar!Vh8@d+4ro&>z({ zirW+Kcjh@)e=ddNuNT*iZz_le+oAHW1YMNpUbEy!%eDy1yrCjpe>ZTPXVu`Iti1>= zjFcKp|G}e`6ZOyMliQPeojgCs0e5x4sz4G1?F{>);!}-D_%e%LS7pHsF0j1VS)H~@ zb12}b$X+IkgtJ5XAS&I>P?IUX9yNIXb##4U>dlFlWo0)yaEH_Nx@a?`R>Ez0Gi0;b z44LDxcqZCci?ItVxvN2OzvtfL=1}Y*iEqX4<%k`*`F0T}DMph(BM>a_Z2iZ zCJ`mg$ zxKScYMOil;*Ttt9Pl^G`E1e7&yQ77FFJ5LNMT8_@=DR{z&T$e`wFS$ajEd~#Vcvih z4}26hzdJ6-;Vyc$&I-9xr{bYwPIH=R}Bxqs9YOWn=QXVDN> zO3h~7q+Gull=Mu3tsgbq8t58f*qM{_CF@hg+{5|FEE#zo2ebckYgIJ&M5QYdY!n5dw6^m0XM#L zA!74or5?_2%vC%kH{a*ER5Wf+PekP}1NpgV4J%A%d!k1wyKCDW2Edx=!ikK3jWGUw zVaC5!1K8EfR%A(Tk1Dh)St#?0vWcK~+^3ui{LftwY>D^`?$xR~qc`Lb4Kvq%3)or_ zVt7~OHN5_tr5X99>z$dyn%|kV=m1rG9qSk?_o3omE z4b5Y-w03*yuV`{a-SvV-&LC&d{tjMoqorzhbg}0nE^{zy{#IOu?}>@Aj)KQL*D+3h zRcp4=?(|qPbAeM;ax`Q<-FT&Q2#jpCPFDC)015Ws(Rx6MAZBB;bjW8M~bw`}wd>J7YUDjUTAb z32uSi2Z-y|+x@s41-}wWbKL8n9BKQ3ai(a8%cPnThv9wYcSH*&8m`Jcf;bZ5%&-Qm zm)+!VRK2@pn9q`WDIHvmYFkRRxLZ}oiRFaqSZH@;i581Q&XvTUz)okW zxgyuZKS;%AqvC}L)@11tt59cMQVRCYcR~iALBT^!K{LHZUNR-> zy(qlE$}+q{>tJsPF~uM-Tw}{aq}vANbTzz_o6LTL|19f;0Dlq}&+bj*Pk{9(>IuOHt+nXp9|=P`F2d z4nz=~MK>?u*U0P4G_J%C4mb9}_KP;$ebCbx+~B}#0rK#m>eRa;QK-M0mH7n@>Uif@yRcG zq5MZuePO-JuAP9bG)Azo5Z&~ojk~q&qgY^@t<~xCcu;R>wE^2Xk!SN^p&N`cIO&z1 zm3DwO)+v9`gFRdPFyq?sNsGv^9K{Y07mYGHJG)u6XpRGIyFh9(9asK5%1%-S082{w zPeT50L_0;!Q@6aE_p4CFK;r}uMx?YZLQ8h0^>0>QN+@!QmJOY+ZQA+QjmClC( z8;xFh&s(+d3Yhwi$kgucO-GQrHEH`Y@em*S6$JklNqBG4*?H#FJTHh6cHDR7sZ=9l zPdk*?&zN;7@EsF*O3MaTK*ut-nE;7yiWs;3l9K8Wlzqzh7)~X%k_MyH5lN-ad-db9 zvYYLMsx8VbEM9l#DA9{_P?4w={Tjjh$jgislV zNoU@Z2ag+O?8NDBo$b*#q0dpG?%dMiVXP0a#yu!`lJyK;^Xc~SBN&=2mN44pz;5T} z!CG*&AyTKw&Y_*84C*{3;tJzBUzCzo^b6QJz!WqyuF@hs<+>BKE;lVRCpR2{8!AJw zOfmCwHs1xJK(qR?c??7#&LjGSB`UkuLUkbA_QhC9K59r@hBv|-BgFu z40la%6dbje6slE)o`Jeg@TOeW_og>u4|S%Ed^-D+ zF-tt_SMJHTWtJIEqMOm;oIH)XJ8^7;5oovm17a5{T{$NeuRvQzTEFH1TPF)8XZzSq zd67Bq)&3cPqob3;xBl{SH9RHj*H-o6=}Q{C$IHra(`qn}O6M@fTc& zo(I_&v#fc5W#AFnB&Hr$wxj|e%lbmYRnB(4xz0TwiwuP^EUKGvBhF> zd;T!2O8LxBFvOQp?_@H1I`LJLAkAxnH8)P34Kwz*xz3WkjnD>;Q+l8JDxW=Xwk}2l{Vs<%M>0oMql!pxVshc<$oluviG(`y!0J zHlR-^$3mE&h2tHP4D*hd-#;E4I9VtQ-rz#7M!XP;CQo z82G!k4nO}eIcY)zbFmbVHgqf$SZZ9tBq6n#1vTY&Q1zSU2kbMt;rggICsJYgh$`Kg zuZNcYiM3S8=Q~jn_g{h-{gh*wV0CL_9RxEDG&@Dp(fZjS9|gI-rc}PY`zfWKfnwi_)sE+4>PO7; z7To@QWPa>q66NvyP0>0hmsXB>7<%=}HZ!Wj3FGVd9#-ux(M0noF=L!8*6HOq{QQbU zv)G*1Q-RMQvnVW(w3qh)W~;$O3FO5gX9IIhVt?1Ez6SEtMBxQHMlrtt zr7x3Tl;;i75r=;Rc~~L{p5Ri3o&`Dn7H`I!%)P)m6zFZHCx|uxm3wh~LsKbglJz2w zf~woY55^_tF6-W1+52`N2U(*O)ysFv=azT)-1>M{#g9YODY6|Q&NS=q?yasrf!HWY zsH);!Fg^9;pxS)3a@A-58{i`ALnc`{uuyOLmH@FVYF&ffpn$HZud}gcG}0?3AA{bu zi_SR%x^p4+1X%Q=SVHz6RkQ|TEK#mt62?oz+>VmJN;ANbhm-U>51JdIH16EM=F1{| zV)^q*c(Yyn?`eqngy;@4#L9dpmW7ioJ|B+=g=LfV@HUL=m9l)h7w0r?PTBd8X_M6= z!sMK!tR8AUP?bhQb9zQj|MXg{Dg?G@R~QN02xB!)HODc`BGCJ&mc#%Y3MeWpg>AkP z6nax<&-XYe_%SPKUS6@A*Q`GzogUE}Q8c1b?|uB0o&8Kz7ABh5VF+hV9X~CTb#^M7 z(EZQ7wN+Nus~xgX_#D+-Y>cep>ka(i2=#-aN(9;Bx{mtEY4}Nz(WAW{s?G2^l#wy+ zXkLNR{myrgI24J|s1S%&m^)ApT=(NAzpI9>RCy+dF6+&00~>?fv&hC^M_}%;B(ZjN z=3!l+##N?y^MWiEM9h;5a`(no<$ZG}ZoeBuIbQfRU9av}ESiG*;jpf#J^Oi1om=junasM!Q2IhQ9#{ookGQ?2t+Yjlk8b zMp8bs(fxT9N*rQ!00Z%RXxc!_AZl}Q^(eesx~dShJ}I(tMqSh_*xi90oQxE?c5NZ( zYoYww#F7JZyQ<|(Cy4omLUivj7b3t3!l%?2-^6jw`(+qHUit(Br_KpnXl$a@f!6A5R?s zMXgE{g(HeC?j<^oz@Ofq{e>r&I5cqI6MPov8ig(`cN*@aK+lsYZwba#Nl@4nd^Z!y zXnn|`uPn$b!)2m0S^B77{0-LM5Y-_M509-1&!=Z6Tkk?Y=_XnG8NT(d$5L^28$DK3 zgYIRv?Ug#mPkW)r5Tj@A@|@>Xd4p-D^?Ym}pg$IW`3FKCEkafdtQh1h3wdsvZ&}Q* zDk;x*wh%Ue;0XyqRV!y~+8miY&Os|AIcwP_QJlRJCa%Qq)wYnk?ix35 zlV`-4p)WvVeOoMz<$@l4j{vXT5;<{?K=(_0&fiN|DlV`08qj%jCI_#@rcz26iAwv3`EARo-`UNFNGbIjv;Yo=a5}^?{AOL$LeTn< z!~tiDicS$mnEpNaydpXw;e8J?7Ho+p1?tzQqqbrZ6}^GmL*E3S>=EhMoISZAA*-R| zPo*>laCgbk6(Ua*6CkYJ35Qw(!{_Va33S1jVIIVyjwBsA6Xpjw&Gb@ zD1LN2@E`o2e~0t+i93YcQupPL?vQ`AVD)mUIWWttuXAI^P%AFm6=I)g3fXPw?%-Wk zzZ|aenBm>-U+d=8AL^WEe8U_;>(QeHM83;tgI7w}Y1ieBfvSEqjhvT3!p97F@g{MX zs7KMm%ArgzF#uj?b)FS_2i4x0v;rsiaVz+F#;}THqxw{O2oT+cXynHT(vUWLJ``|< zI0d9JS*JByoFi?G`UP);ROxv=E2Ec@7uzRVVm|mdN)xvUR26kjgz&8~8!~xIK3GxN z)P~tNBVSWkJ$CA}aQx&kVa@bOW92=%eb7|CZqM_k??o+mZ5k^qy@%6}nK0bhU?lsH zmymc6=#5r$^|FvxK&L|$_31h=4QPa}!VS+5%}Ut7LN z*~q=|^&Yt0X6iMuV3?GOjB~*6L{lm62aQ976}e}SoJcIe-8Yg z(!$MDPh6FEvFfBD57%2`D}Y*Sjls9xoE7OH7-MXr*eFT0)cO#(Z4nPl*q-Ne5GCeS zn3K&MSynb}YNncduORNdrtSDg+`?7uBnpQYLZ8A$4=Fq^fSq>K5S$EEroj5fM5bfB zkV+Oq(3A+nu@F@XTZS6e8k?XYo0B{-7bp1GM--1hE=;)ef@DI2?7Vh61oqU_3+&;b z^lwa)TWGayHq3-bJE(e&5>em%77<>79$H6@1CN9#UEcuVR*Mw}J66m?)dz~;=1!%P zj$tZ9?<&qwQKr444)v}S+07=4^XytPxblHY@%C=1Fgz8-9~7U&kgMl`980-H>c-t& zCsZvTHGd&R&1)FSTs=|to!DH_?v0*a^AX%Zj?CuGK4Gj5GFNJK*E{oF0!^Q0G>rv} zK7-(;+&)sV6PPstb?#zq!1EbrhwKtab92ChGyASG++jGbe7L(^+@FF*GB$1`5A66y zBLAyvUgzA`P~2$U&;8?LK+0H{AqKg>^S>3;7lsIE<-)uNnw5uf9MFS9*O zoLE2vco*({td!-cymQ@RE{gstXq+VO5R%P7aX%Ql@kolX#f@H`j`}|{uE2AE=qYre z&bh))Q&y2xrr700{Nf;EdNYc;7k%yq?NP=u@$6e_{sfF4C5)RTik`Ne0rY+G7S~Wr zqGXF}9MoKE>U8@tp6M(z>gTWx-Ba`Y_5R2|;*GX3%1L{I%icx>7?kxK^(l~g#~9n3 zaNw|2wb3KtJzkrcV^69!n?E+yN>yw{6U`~Yegq|N5@DlwD>u-CbF>~EjW*Gas}z3- z#kWKPNK$ygo{p05iHjFFCqo>nb(66UX7$cd)FEiHrM5X255|tReLPAkeFx~fRL{qA zl6Vy_w&!aEImv!TC$*cw+XFQsF=qnfGy+ocQJAEapwaObRyeQG@gd@9>p1pN4`Gax zR@`V-K-}NzsrSJkd8?JkK0PF5j)49ywyt5e|8%LAsIRAR!tn}bkszGT1O6Mq+gYRz zisz87)iFP#9EN!Be{SD+$-*<}IN^z&MZby$G{uMtf7ZPQKbW*snZOMY{u7nIY@2nx zTihcc?bVUA(N#gw#Qv!B+x{_2yef0kbQ}+}U#nQ=M{@Km?He$AiQ=hrsPopvhhVCg zLYtt6dRe;pX4*$W!ro06ZFd5HpBZI9U3N#yxgl~gw0)*n!)D@aFL?W?66<+l~$w}bdf(Scsrh?<(=C!?c& zD$Xz=@7@UHi%YcUILKfysbFYIGzcz)}#FaoUlhpjbH&O8G}z01$`<1t zOns_!9Z;o4Y#h4{E!G`6?}kja8o}$a1^Jkh3nQE;=x@_Bd8uqKZwvBVi1v1DglN*O z%7!R=XCy=^CIV9KXb5qRMZ~GV1=j?)4-C!@`t{B(#sS^cXv`c~^OH7G^a-$2r4147 zCW$HT#t%;JANS?_?1qysVI}x|L(Ck{Id};xH5`JU93elcaN{>lgVFYhd|843g}Yn9 z`L&TI;gi~^?ZH=J;vzkjhwKUu`7%<+j#JS|sB>S{B#Q>)RHA-*#EF=84Jt=JsY1x{ z=5W^BiE)29@c+PK%rxre98r3#9RXoaG2-Nwju?s;Qj{S$N9-X6$K&Nhg;@s7Ykgu1 zm{1m_-44LEi;U||Rd0cYmd2jOX4SJ%PP%?nM9zIF^TDj_&O3d6Buo;d@B<{@o3(g5 z>z27Dp|aTS7BrqlO3$v{tH5>_!yMlY)h+9BC@D(@GmB1KTaq z2A=^tSs+$IAs-o}x$Y&L*5Int+@?$=ldr?^f3DNb`Wnaj3 zRbYmAB;|D0XZt}RPsKGSc|)XTPE69!nuPn(Ny-IytH0Ku5c%PpKW+u4yAl}vy;Qgg z6&@!|*QQ_BTay>T2i{IZ!HA}(oE)bAl-SRV7rIrqMCDD5pokqU$t`spnN5dfaR59 z540D(%iRpf2O`IEGJW?#%{}T_S=;dfu)NVO9o&%F3eh6sb!!Eal%+v2uTX&SXq+i^FRmiJ@VyqAGg8{ZTsJ9FL958S7 zjf-N%rKeAa135=2)jqPMH2Mle9H4X)Px*xKeoaY&bn+Qv~iMEFKWh1e`r0TkspElJ#s*kl34FUo(ZNtG$naFwXgO_$qaaUSVSt% z!~9me2|w4oNqi{B>6;D(vwzrnD>yzypHiKLYBwb1%sUTCk^7Xj$e!qVa3 zx6G7{E?U4TWGibSO75K?oyV9efg3Hd%bOM`@^l7rLPm^c+GlTCe^yxFJ8Tljw_^;RbJ zb|&>sCiQM6^%Wm4NSsXsEQ zKQpPnGO52asedx5e>179niSQfQZ=atHL2{HRKuFoE;Xq}HL1omsauSvD2N$p;f+M_1bvL@B4Cbefxs&!3jubR}}HK{f=skSw#b~UMeYEt{wr1q;x z?O&5RpeEJ6CUsy<>Y$obhnm#EHK{{TbJo|Rxz$D6b@g5ks73eOL=0!H6xGY7F&f5u zUmAwHV=)#!+E5HzRvzUb7rXMw*8sssIgZc=$q#t#+rv0=gwzwm)u_Fb?Mo2Pp_e4Q z9rUln0tC>)JVthYmA3N#8j6dNjj=B)0)}r1$iE#1+5e=76}x@Z9pLZwGo zpUUB_5-G$}>HUqiqHEy_cLxf+Z^rT>?5}8#;hZ+-8w`gfs3M$NV@BV2sD=Qtx)p6b z2XFgTngFb>G?@q7Aj>8~Lo}bfpZJ)^PTd%?U}q)}@Gc z2hrX}7%Yv|=CkOCFAnuoKZql2mclSZGtHAwN%W@{l%in3bRil$e&R9 z#01H^>3X)sS$n=0j!je7Q=xv~d2j2Ue0-$4R;7Ov zPOP~46@>SQ+)cNQYoMaOqJK1xB0X$f3Zng#EKZ8Y*{E`)or%V22F1rdM(Z9W)uLtb zYF@A8?m^Afh9A&GUIe}J_zFC=6j3qO+MP|YI=^InX=3$K6Q?KGk5GEM;n}!1-$)i5 z_g0NXo>C{Ab}(?QT&m7_|2R-RES`AVSO5`sImFFLIO6bTyw;!yF9cJ!MV95GW!+02 z302$};cQ9O=ne+*m86^0zO*|SZW(g#6`v9cKi9&2rx+sn2Hi-7yXZ{}K(93Lp98iAEj_U~AjYlrv*lunWQ%IvW?iLaa)~8Xy0c=@7srs6AJhGpUb+@*;@c*0xH{fEVKM zS4@60n&kt=FVQ1LH(Tlyz8468Z^}j?3GU*48XDkWt8RXkwU@owtIBT#?H3|LM@Nj# z&BWor?_%)gK8Nsi3FPT$|BmQ8RpAOCo>5A6V|7{sdyXlF247arcM_$_CLr~vs2Jj6 zb4c&;6hRf^69e&nLmA)77Ck-z8yz7P@Ksc_68FUIG^p!5`3dJmMhufw@FuXgD=YG3 zDV__-kA8y)EsTI>BcQ9AWpl4}ULu_%O5(yk*6gRo+w6ZG^B;dk8hKNd zx%li{KjKHWjuc-)s4!;)6aG$z8XK6B#>0zx={;7yDgT|wkLit@U$QS$JT&UgCHzGU zv4<~rOZL>Hq z>%MX)N6De!`KGvqn88r_6d%jvCoGpa&l>UR-A^*GmBJTgz0?UPFPf;h;dh@w2@|Yg zO5Mm5o-Z9>+gj8$iRSoSjE06sP7H!^M=HBRnD;5Spn2 z?gr@j!JRO`>qZ1~m=M1MBO;Ch(L)m(bkR|RHK?^;Vs&FaCz;b_VC#mca$tEOEERV^ z#qUUS#beA)Oc9WMjLM76rC=%bG-~wJECB4tEMQ-ph+W!dYTfwL%uA#8!q}_AA68|^ zbK-1A90UhDMD)!khstMXfQMbAwb`UJWhV4hj97{CZz&mY14dQAsldirrAv1wf_w|T z?_wl$9)q|9@~s-hhC&lWIxam;&V{-s+D3$xnqEh20U!SpR(YkSht@sW#Kwd?K{lsz z`f?wK3$--Wno&2`eSrL0R6Wr;ojG^aSCh9uz`&R{%15Tm%Yh`vBz{wd^KtRUNx;1( z-dfO8p;`j9i&!L@%_aIqqd6xB-EG~eb*G^Zo)h=Mb9VeA5^*Z>-8B8HK%}*j7!QGK zZQcNpORV!DucB`6Z^1e*SnJ^E!?|ia9L{%B8CaV&cJfrt}JEG%?ZQJ3{iLxC zhi)r}DnOOz34_Bc29-E(2EPgE9<}_)B|53JA1eJ`+9|@$m1O)R%oEnZIb_u7RtJL7 z#Zjf^4Mg2@9*Rn*S|paV!<_f$wu9Lg%EJ(H=rq`?;9}>Bekyppbk?n#K)9hWY)>ca zZ^ZK9SOepxW(QLH=|w31nQ4uWKTh7gqx9I6=u>Fgvl6Nc66KMZA6+91! zrWeSSs8@>5HO%g}^MvhceZtZ4KVp5-H0#bNZ0(X7fmFH{o@OI~4QZuZl+_4z$__*Mr%wG!M1PyWX$U&KDrI{0v$R#s%;MlR8 zz@M*O-y6>%ZjBlc@&{BYnfaFB%hH7Sd3EVL4uHqJlyu2mRF}-rOf#*9%_f0!b?hHh zd47NHblB5)N{${&YJCeT%uPmX^uaP%^R0m1hRx`0EHTgM zGg&xGo%f+wj<8=KA#4+Z!}={#sg^A0n}swH61|B2GDK;sQCbD zF@Sa-Kzj_JmIJ8O0NQf^wH`ow4WPXT&^cphRVKAMlUkEWJ()?Z&7_{nq@K>C{+CHT zlS!@1q@K;Bp39`3&!pCKa=pfp)5K3iiq`n~x@@BwyAIXMP|nu!Vd4V(dbJY%Sa`r@ z)stX@PbPjm)jUW_VvQf2@r!cmK=wiF;?dEJo&X=0$}aprhM6Sri-(z?%r;miu@fH_ z=rzV8kpD7arnuZqN%=82IV35(!-9AQN>4aG?)Z2+tZ0YL22SC$Mf{+w91n{tMR78w zcB%$=nMR+2!ncP^03JP1_eV#;|89vf%4ZM9-ygHelrL_1-4E6NjHT@%l%i;tfVe?zTf2Z1%9YNYr2QR8h3M3o33Qzd)y` zog@w0Y)l#(1~h4FEufxXbk+(!%aN=VZv(rr(S|0@YSBSkh zyO>`1Wr7Idjsbo5cqZ;Z@}1X8ReU6i0J%j#zVKc>}WS zD|W7M?qPW#c~5MTK{#y|lVk&PlVJwCTg94}LqKd(>;jyhrCz8HCuAO&@M@OhpeItC?BLis&Q-J(ks^#brMU&lj zv$1yhz`~-OUdrC5z}_W^y*i^wi@o>&@HY_@&!$=@5?%|?`0|soXkSvaA(mWUR2AnI zPO9UTLT|fLXqxr;4u8Wrxb!ymQ5>m%3U308%o|@;1oh{Eoxb5Sd zBf0LB@wMZsr&Whz#~9Ds!>&-!nMBI5lNQk%zYMfk#E3RF%{HG{>L*aWQ2iv{@Q@$8 ziyzQ{c#4NT{Gr1zh6uV8B+k&@fEQMg+eZE3B}l#9cKFGCWMOeG8pnl+x0x$5==r7o zchPIj6=n0%8tZ4lz6xLbK}zE~rg=wE(EWiPr-Uou&|zKs!w~Lt+cf#^oASmK`08pg z(T<9qgFgYOpOvPW>zupn0(oDJt!xu%sd}qGaZjU8&U}U}EKsIAXTnEYjV)13wM_~v zQPgE1xtGs&u(KaQ+z1VwY3Om^thvkvt*mH#f)M$`odN0sNVuCQCt7EU>H?IVSu%ur~N&KfC2i| z3Q@r|u?l+qUuawsv0U?(sk6(n6+Cz9!$hMHZ8bZrg|vr>v`AFvoTx5G$*Uu`<8@k; zVM=thKMdMLw1IX|;JoHF8an>fR4%D;r08kT#G|%nGATEe1^R)ffrhFHVV5G$XJvOC zl{I$q^hwjg+R1g}r;VSH$vQukosBK?xmRK1e3MD3)me#(FjG8MACI zhA-n$wrBsiGqN{j^zr#TnDjAIC(mfjK8JV_-!^+bQjiT3P;v}|cK){F$M3LR}5kjSF0|lfS=Y5?yxf!eiTXD5GiC zn%+?d6FtCieq6=={Juf_e5;8>xIad<**U6j6aZ|Jdt4e9nAaV-Mo-~xY|PYf-1xd$ znBl<~dEWnpoE;yySpgr93(efg-#<1--R#n1##WmtXxF&N4RMz_b}DB*T^axVnw|W; z#PVg2&2Nc+{ixB`7+jE>TN3|m+dw`iWbq;;J``gHnHc)I%(Tp;aWQgcjQqDJYnT(x z8TGD>|GsS}e}B-D=8aQc%^347EHmeTOxunSPsf-`cZ$i4Y;+Qi*-+PlxI~U&Hj!dl zjF_*y$t3r!tsXxWC7+3ZaN+;g5B`j+woE=77yNA}e?P2V-yZ4pZ0B*vX_J@-VG5bM1a zWA551rZB-o)jb~hSg@KR!3Tk75wTbgZOkNkGE*=qc2v?ebLZ8N%c{{}%(Agwu zu)|a){{2>)tx=S>IYw;R8Dd6G+)%ASzlcjr*%_jLSE$qyH;wetSVc$d3{h*VvOe%g zOyJl5$Sm13>&8f~8P#=A#OZO}6#Y3-?3@^NS)!xNEN;DD#T4f66thZR;kHaIkBiiF zH{Ei*x4D8 zCHA$>J$RsE*_&ov61kN9-3@WYi>(Y}Yo~`%!`>L9W+yZwCwwPHEw!a=2#&lhav^0j2<+V!;Lg zCs;5W;6w{H1USipy8xVQ!A1aUE!Y^~6btSOaH<8H0IaiMQ-ISf*bLxw3+@JRh6S4g zoN2)p0B2cncYvo_a1Vf|S+FI*(=FHv;29R&6X2N^Yz=U>1@{6t$AWtUoNK{00MD{u zTYzU;>=^ z3mymXRtxq9c$)?L0KDCT#{;~>f_(wrX~BK~@3LTjfJ-bm0N~vg90+i!1#GtN{3=1uFrrwO|#%rz|)U z;L{cy1@M0s91ZXp3wi+8S*rvm)c zf~Nue%z~!_+-$)!0Df-4GXZ{K!Px-6wBQ_oUs-VO+^j5g!KtsK&$I03H__+W_Ve55 z^Bnv6UG#ab{ro=qJkNgq5PhC+KYxrqFR-6KMW6HR=g-mSh4%B8=<_1``D^rfvHjc< zea^R^zeS&y*w5di&r9v+*68yx`?)RpTwp)9N1vD5&p)EiE9~c=(dR<@`B(J0$bSAE zeO_rl|A{`YvY-D(pI6(@EWFl)5pC`@_LHK|Ywc$$`n=A5Hi$m2x1ZV3=MDC=Vf1;U z{oEz`yvcqxiar&)UypqtEB;XQ$}%dHdNp`dn{6yF{Na z*w3!f=Zp5UTlBfXes+&OU$UP)qR*G@XV2(!qy6j^eZFEpkBdHEwV%E5*(mGebXJ1~ zW2>_oWt{>jd+gLs04G?mGr)-!>;iC-1-k;AY{6~-Yc1Fv;1mn?065ixJptAkaN1OW z(*QQ8VG7d?!~|v-i0hweAg+Fvfw=Zl4aAk7W+1NnbOUkKXBem#pfe409H7~NvTKms zuu;|=3o@0t7GyGKS&-?RZ9yh3o^A!EXdR@wIEZw%z{j9fd!e`z>-S2A zj0LYU5M!@45VLZPftZtP4aAIGXCUU|dIK>VHyDVyxY0nzcb9u@=2o@(@avjv&T zEf!=lw_1?t+-5;0bh`za(j69LQg>RAY29T(CbqMISz#8(-JX|FaAlU`#Wru-zJ>={O@Yc0rBp0Xg5dD?If9ww=Ml^_ zzldNa`eg(&)vqF$$$lNdO!pfL8^wPc!A$qN2xhw9M=;a{ z-CrV@>HZqQOm~ZgjR}5>V5a+f1T)>O5zKVAMKIId9>Glaj|gVEe?~CV{VRf*?%xs2 zbpNq%H#Y0P5zKTk!DIb*W4f5#8JOu}YG+`ki+P=anJy-E24=dL(HWTOVmfDFri;0p zftfBQatwE8x|qconCW5)XJDrL|HwPb@HURF4LdT1sR4(X9cE@`Xc&x%6I0A#hnblf z%iOe0o21Ol%*@Q+Ip;a6RW_1$)IaZ!uh+HJxo7U7h0&~5j%fWRF}F*LH;K7jTDeKg z?b5PMVs4k#Y!Y+3v|y8%+ojc-#M~||)i`d??b13;Vs4ifX%ch0v_g}Z+ok1MXy{zF zX=O$cyR;~yh)r6LQN$iC#VF$5(JG80?i($@DB_;c+KVFY7cILe;$G2;iz4n5Ew)0# z=E|u~3oQ=06Mrc#6ON8{hGt#A zW}v=OOMdDNWY;GfsHI^>)^M_l(}s};s%wOiHIl3nu62zvvaTh|J|cnol}A=d zZ;Sq}t$fNY<=3FMCwh?2<(4VbSU|ajx3Z9o!dqEH2ESL}?BE&McRbu% zzWNudRq%|w^G4a;GI=+MfGF+~a{0ZLYb)wR&{*I|yHpoLjJs|8G3T?LpZ)*mj>i3U*qa(K)<} z?ZRh}rQTV`I~VM>N(Fsp?%|TW)(=#&;CVJeqU!jch4yl8;WKr?K6dy{!M@rN+4G_I zi0!vr-@RqUe*6RM^F4+^-3Nnk4+Y^KW|!|`oY$yxl-}cYgiG*Ujd6*iL6~7~0G;7L!Fe-6J&?W8+y2M>vfU_T2 zD)k?(@$+1kj;c|M-fR4x|5WPU|5WNeYji>FlMDZ;)css4sPpK7pi5lj5{B2}r6AnP z>>A&3Jm}B%y{EbIGs}X9g7hB_(tjjK|Ir}*$JjT%!+PAGUC7>fB1r#9_5B)+V~ujwFH0e=ex#VdG-4DHST*8hvzuIUN>;wU{Wm+W*b-1&+fyKjE$`I?QZo*kDy|GKaelAc* zoALyNp9~b@gmOK$6R^FoE87d`g|j!<(PqKb`;|T__IQT4d-O2Z484l%jdaxKIDab{IF+w-0v`WpL$3;Z z{4~aQoPO3bRoNTu?p0%NjJsEzy|M0I4fe*ldo|g+*4?Yc-gtMfHhUA?y*lhoboc7A zH_6?r$KGUjuReQI+`R_uO?CGgvNz4$YsB7kcds#fGu*u2>7c)Ujc~b3SCW@NV#-r#7jw3lM-9&TIbt3&FjK@lZeXU0DNmeT`k5xCJYRM()5Vl$$}VPxnDQLi z#hfdqJUezVGsTqW#V%%+nDUI+#mp8{o(;R0IbzB)VHY!3OnD;gV&;h{&x2jed@qK)paqKi7C%;UCiZT%5z&6bA_1ltk%U`DW*K1bum|oDbHkG%++Gbb66L1 zjhOQM)x}&ZraX6bG1rNC$zZNqFXm+fbAy=jyw#=kjbh4^Ru^-VnDUI(#oR2WJY97$ zw}>gvRb9-jV#*U$7jv7K@-)@O+%Bd(M|ClGh$&A{UCf49p{9zG`3|6;qx%yX^U6V#>2;7xTE7@&ww&JRzn$hjuYfiYZT{UCdKr$}?#f z^R$@qWZK0%Bc?o`b}`S2DNm_g%yVMCZ*YvR6Y~QD^LjDmxwT8{H;5@uu3gL<#gymQ zF6K>Q%2R9?^JX#SIkt;=iUZXSB67U_U++KisJ9&&7%` za=-BJ2JFX|;$PK|fc{tFU$y@N`d^D5$^S3pJpRVW`c|wcm%6@lS^@j^z0>r2_Wt0s z0@nAVm__CPZr8+5VihxTfA;SN?8h(S7dNW=SO0Fnx_=Y@sxb!ie;2=mQD6QLtE7?p zr++tKKmHQGlu_M(`*#D@{g3!pjWMAAulS{n`VzwLI0a>lT)I>D=LYPD{3{p*SM?*H zA1d{iHR?;4xaEx8aQ|+=enj~1M?gPP{PNtFLgt_-rxmciqGDcSG`3>mRxoml`*#EO zqlEu{1oTUaU(u*9rNpgdq$SYNc5Rg8{h6>+N?xmEqU0sB$Se?J2H)y1!7)R!9K zRyT5M`ga5Nqn7`E1oUf*UxWKn$oX1FteP%XU8fbW)q2iW1Df^4tYx&X8u)hu*4@y* z@AnLDY&=P5t|R``ygH8?f#e@#`4%ySaZiVBIbJ`+ob~(!U$9 z?pEU0HR^Y3|8Bs#+xYkW_PecrH(=fE#II-6@Am%PfOU5ezdqMp$hF;3tOhPtC#My# z)y~dV1DajLZ0OQ*SEm)QzHUy_?-AB zbEoO&Z-d5)*}`c$J`){hWL+y(OP9LFi`B}-nkZIl7i*G{HCe1SE_F>2tF4PQ)ySGA zRy&uvrW;u^#A@$SSFDj0CsqfSy5hy^=wc;^)yc(56sxm~l_XXd7i*?iU0tkMVs&$| zGQ{fcV$Bt+hl`adR!BZU923j`nXuRV)b>g^2F-rV&#j~-^H3I)&Li4 zzE}fYtOZ8aLa_$9)V0XSS}fLJm%5f1Sp{MZaj9#mk+n>$p)PeTH?mfUHO!^1l}6So zv4*?UwOXtZF4h_&Ypqx#UFuqAWUUu#luKP3jI51fjdrPPlaaMqtT8TiZ85U8iZ#}y zu5DtCbFsFIb*R~7ITt;xkt>&2IgKdrx=*~#GL9h z9qXz6Voh_g4v00~#X2a~3>WK=k#$%sx85HSE7qmOqej*-vEp3nI&Ng05G&rLu9IRV zxLBu*tkYs8y3}>X$T}-ll1p9ZjI8U$n#pxp|MH9d+;`R0SL_Yq&ocIJ6hGP6ze)Vr z#{SLX&tc#9erWmCJ-dRW>OJCTa^3jXbprPHUfZ<(HKc&meiSVI%7ivF17Z<>$Tq zQ8DK`O~+AsOsoYi*5gLj6Jjm2>%#Tq=i4(+I!)_(^5Z@gg!{D94cLQc#9UG5+?Vo4Aso|h5@&fYkV)eB-Rb+KMFvR<-Vv_`_$yA}Hx)ysAX z-^Ej-UEob(+?^n}3SA-KBqjiM7MU`rF9* zN35MLb^U8(h45Omz^5)Q<#&%1F*fD5a|(93^e1y+i@DpS)d(Xi(rE>3 zHOkm5DyG{RP|V0GF4i8Gv6e8hN{Z!k90HEDl$d*6S}iTsJ{PN;So_(s)-d+{%f_qk zM#~53UlXKXLHq;8{iztFUnxkxviJv$`x70cUq$>w#`RYf|FE%NEl9t*_(zQEuOa?X zW51^O$Bg}2;vYBmYX{l?I^v%&uD@=Oe!U?5`r@B7?oWdt{f0sMjl@4?+@Hol`b~oL zn~HzhxIfK;^kc+7V_bi8@y{CjEyO=(?6(yEI%B_8ko|8h{`JQ7w-NsaW52EVHyZox z#J|bdZ!iAM#(sw&{fFRL z82i0~^m~hcr*Zv##J|hf?;E7wPyD-$>+c_=KS2ER#`O;j(jO%LJ;wD97XMyje@Kx2 zQ1S0Gu78;L7mWSkLHZ-azu&n2kwN;S#DBoJ{?X!JH1@{?>5movl5zdxg7mKy|FUuY z6~|A=w@)5U+(*q;%kA1nT2#`VVq z>Bk4@Cj{vyivPHA|C7Xj!q}e~q(4jiCynb*4$_|;q(4Xer;PiPBL36HeyaG-82f4B zKWpr#i~pRlpCSJ9#{OLKUoiGF#edP*&l3M7V?SH`myP`#@n13abH#tv*v}LHHDfnb(KQi`LiT|;&zgqlHjQus@e`@Tn75_71f1UWB8~f|U|H9bc z5M=!ugY-9v|D|z%HjDq2vA-oqf2;Uk8`r;0{BMl??c#rH?C%i&J7a&R_}?4*yTt#& z*xxPwkH-EU@qaS*_lp0svA<9JUyS|z;{R&w9}xdHWB;J|zZ?69#Q($CKP>*A#{LoU z|1$QEivPEb>c@D`_~8A{~N@QG_Lhs3t3u0Dx>EDY+)=N$+VEsPVrx>&!7RnNux(`mu?Ge`X;W__3X{x-7yaasXeEfU5nIGNB#QnC)!S?-^cStoANe1F<@|SPjMM=wdYztCNe>Sgg)2Rui$hxL8fa>gr-O6RVqx z6(d%67pu8gJzT67V)b;fT8h=n#cE|_wHB+lOI>Zm>f>Uy6|1j{)y~LjFIGR7x;hwH z9mVSJQdcJL%u31GBrBLk!FwVh%Mhdx|;C!0aXF zaHr|GZ|rSk^$}}?OI>}%8tG#76Kj-hA*y%v9NAyY(YEP#jvQcQ4HRpPOI?GEtifW9 zb*XEJku_ATaa`BcpEdgV8~S15Uu*0S7k|95KSKNoE@K;MWQ}rKsI}hJM|!lF6YW+5 zuBXQsn`4d5asEv7rOwrTy;kf=oR41e-)aQx@A#nX34!c@y_pzviAhpoGHT@Cbqd(` z$;RdsF{c>rlc_=3(*oH6_sR62OU#fGQw{qc85_@GN9NC}^-7IoLV`s_^> za~ksPU-fdlE6irA6m3_}NigYF6#oX`9Ah(u&C(`yrW%`RZ1O1hZ{@ANmZKQ&6ia3N z5!_k%kDPR?1paFO>N3l&E|be;3Z}d4vplh8xLEmO#kyGY#ENsV=8F~YVl5CW!D%h` zjx&VzO$d*0p_qwIbM4jUA~BN;%*A5PbeeuzU*g~N^RF5dh&juk&ZYiMKXooMHkXT; z>}=g}1+5Tkw$t)6?v?&cKYd&!<{W38j+R%8mEvNp5i8ZjS}#_b)AF+_-XLbWfw@u4 z3P>qe((*Xzf=N$d^Idj0INo1Laz zuOIssu{Rpjd#lqdwBFmq-egek?M}1MdhZZ>vq8OgI?Y1sy-VyZ2KC*omH=QQnl{n!`8-fmFu{Z6ycdLIybhe5p;oo1o+UJ`q! zvtB=Y?6T9e>-A$lDE2OAy?*xCLr&AK*N^?M*t-qteZ*-NTJNJ`?=h(NF=O*_G4~qO z`Gm3gq?r4hb^191Pl>tTY5LixPm6iLz@SLW%)op}%;N^;%VM5zntuBEikK&zrk{SkD&{Ez^EEL~8I z)6ab=GS80XJCFK<^==uTQTo9FuxP?0R!`UF)tdJKZtqBY5KY1eiZYv)AV!2{Uqjt z2IkLVKIAn0wEl~j4?9git^X?KBL?PgVm|6L{j~nOn2$M4Kdt{E=HmwDpJG1YH2t*x zmzYl)n174;l!5t=m`^)RKO_2A%x4VDkZ}Ga_E`h7h?vhgO+RDzi21zJ^wZB!F<&q+ z!^C{izzi4jB?B`;%$E(!NHJeAFr&nL)xaz&=4%FKF)?2^FpG=%hJjf^%r~8;pQBk) z%(o28QewVsV3rp19RstBnD07GKj%_eG2b&V%Zd5EfmvS64-Cv}#Qe~}tRUt`24+Pu zKX#gaj!`8sKXICV_EKdrKQ%C;#r({`tRm*;24+<;zc4VXiTS00SzXMpoTi_>R71?K zou;3?R8!1v49r?$ersUX7V|p;vyPbG8<=&){K3GiC+3d^W_>Y#GB6v6`Llu9P|RNp z%tm7VYG5`N^EU&tiI~4TO+RNyQ!)Q=ntslZW@7$nV8)2~mx0+_%)gzcpMJIw^BF-sblJ;W?!VD=QVw1L@6 z%rXXMZ!yann0>@7XJGafv%G=XPt0o!%>H6lFfa#*S<%28C}t%CbC8&o4a~vD<`83Z zsIfUrOp|w+;l}0&V{@dK(ayc(_zuJLfwZ3g-|LfL%zTrAW z{94BTRPk#Y`_sg)W9&~Czpk-AL;QNieysTQjr}?exf*w{}J zzlpIwQ~ajJ{w(pE8T-lN#~Ayw#cyux&k?_cv7aJ-OJhG({8q+(n)t1a{dDo$82cIG zw>9?Xir>!I&lJDCv7aS=2V*~5{Eo(cj`*F7{ao=o8~b_UcQN+!#qVnD&lA6!u|Hq@ z?#BKC@p~Bi3&rng>@O0(m$AQC{NBd?67l;O`vv0nHTIW^-_O`zCVqcof4TSrjQthj z4>a~yia*HMU*+Gozi;4YO|V+Z3^s0Kjeoz;Hr7g+A;xX2^Y0hh#(F6;)VPfe{{2GR z*eGR&8Mm>?zh7t@o2ATf<2JVV_X}-ftCSgG+{QNXM;iOv#UEwt?+|~qvA1np!k!G{X^nUG4>COKh@Yj zBK|aE|ET!Wjs0Wd&oK6niyv$3pAbLJ*gq+Lys>{u`~+kFwD^g}{u%L;jQz9X&ouVW zi9gHOzfSyQWB+>bXB+!Bh(E{Jzft@YWB(@cQ;q$b#ZNQ#ZxKJ;*uPc$3}gQ`@#h-* zw~L=??B5}Nma%`Q_}Rw(UE=2$`*(|GH};v_&eG6eLn2x?)fz_cNv(ki@Dor zZn*ln$s1zsF)-g0bFb6%)6ciW+-G3EE#`iw>8GFX7}xo(mYlESG7qbQt)uqcJo5f-Cx2EyVL#v&|1VI0De6viVgMPUNM(iA2l zEJI-u!mIUxW+1Fe z;ar5(D9l7yox&`HH7LwRSd+pWgtaKlMOd4{JcM;9%tu(4!g&bmQ8*uAeF_&KY(U{c zgbgWNgs>5XixD=aa0$XD6c!+CO5sw3%_v-kFoweA2%A&50$~dZS0Zdl;VOi!C|r%O zHHB*swxMt>!nPEyL)ebO^$6QjxB+1Y3O6F`NZ}@gohaOlurq~Q5O$$(E5fc6ZbR6O z!tDsVQ@8_R4+?i8>`CD+guN)-jj%U`dl2@aa4*8X6z)UVkHY;3`%`!T;Q$H`A{Pa+&i;VFcpC_IgDG=*mnj-l`@ z!m$*dLpYAY>kwW`;q?f|Q+NZy2^8Lla3X~_A)G|v%?Kw`cniWQ6yAz(DuuTpoJQg8 z2&Yqc2f`T?-ia`l!n+X0QFu4PcnZ%WOrY={goza1i!h18`w-5g@B+eF6yA?8nZgGU z&Zh7p!Z{RPLYP9~WrV2|K8P@l!iNy1Q}{5#3<@7XIG4gl5oS{O7{V+HA4ix?;S&gR zD0~uOE`?7a%%kvWg!vRcgK!>&&mx>p;d2NVQ20E;g%rMka1n(sB3w-2O9+=x_%gzR zf{+lJf<3P&E(N}-xD5E3;&R~YiYtI`D6Ry)skjRGmf~vQ+lp&|?6rYVc^e-M}WU59tHlYcntWP;&I^b ziYI`7D4qoVsdx(bm*Q#Q-->5||0tdX{;PNn7!oIM_XXDhizr?X^eEl{3{|`l7^Zj= zFkJCwV1(i=z(~bgfl-RL0gEc$4lJg42e7!}oxl=`cL7T(-VH3Jcpg|<@g86q#e0Ee z74HL76&R!V8nC(I>%bO@Zva~=z6orl_!h9W;@iMBithm1D!vPBr}!SQ zz2f`84vHTDJ1Tw%?4r}!PPzvB160g68W2P*yu9HjUYaIoUfz#)pi0Ea663LK{R8*sSd z@4yj?e*i}+{s|nV_!n@r;@`kAivIw|D*g)`rx;R1-hZ!EECL*_=mAbp3$mEDD^iSPVEru{bbRu>>$qu_Q2Fu@o>tu{1DIu?#Rtu`F<= zVmaU}#qz*p#cP1G6)OPeC{_ffC{_ZdDpm%jDMka+6{`R<6srQ~Dpmt#Dpm((Db@gH zE7k<&DAoezD%J+(Db@kzE7k?hQ>+J^uUH?rK(PUEp<+YeBE?3)#fpuAOB9;`3ly6I zmnt>`E>nyFE>~<0T%p(kxKgntaFt>!;A+Lzz%`0(fNK@o0@o?F1FlzW58R;G0k~1I zBXE;qC*Wqq&cH2-U4UB^y8^c<-+a*aNszu_thsVlUus#ooX@ihY2475f7B zDfR>ISL_cwpf~_{P;nsekm4ZVVa36~BZ@r9VcE#zyI}~RC?^KKh-lZ4^yjw9IcwR99c#mQt@Lt6v;C+fSffp2K0q<8#20oxT z8+cK14)Bs<3h=UGD)2$YG~h#u>A;5-Gk}jM&ILZImSR&hS?ImHFQ=M@(MUr<~Gd{J>R@Fm41z?T&ZfUhVn1-`1d4EUPj za^UNVD}Zk(t^~fRxC;1|;%eaAife%HD6R#*tGEvMp5l7o`-&TYA1H1FeyF$!_>tmf z;KzzvfS)LC1%9fy4fvVjcHrlVJAhv(?gW0RxC{7|;%?yAihF?HDDDM*tGEyNo#KAr z_lgIAKPVmq{-}5e_>cnbKJ;%VUD zif4fTD4qrWt9T9=60i5az#@v*13ij207DgT1coWz1PoWa85p5>3ouggR$!FkZNQ?6 zw*!kQ-T^GGcqg!g;$6U!igyD`DV_(GR=fvTM)6)?S;hN+U12OfRz+411l>&2#i*I2v|k&VPI9oM}XB79|cxdd<nKE*g)}lU_-?hfQ=Mi1U6QD3D`vOWnfdqSAfkFUj@b}z6NZr z_&TtK;v2x0if;m2DZT}4t@t*ujp94NwubO^0y`;w1njK% zF|do`C%~?Xp8~rneg^EW_&KnL;upZ4ieCbIDSid)t@t&tkK#ALzKY)h`zd}0?63Ge zaDd_uz=4WC0tYGn1RSjRGjNFFFTkOSzXFFT{stVb_&acf;vc|~ihlw}DgFf$*aQ~}V1UO#N1Dv233Y@4I2ArfA4xFqQ0i2>337o1J1)Qc>6gXY6 z7;uJSabT=s31FOJNnpHUDPV$PX<(va8DNrPS>Q~?a==-N<$=kH*8pcLRshaXtO!g| ztOQI|tPD(3j0UDFRsm)xRt3>Om?ftPadltO3kctO?9ftOd+ftPRXltOLwftP7l{ zSPwW~u|9BtVgukp#fHE|ij9Da6&nMWC^i8WC^iKyRcr=arWgZUuGk#7La_yKrD99q zD#cd7)rzfwYZTi6*DAIJu2XCWT(8(3xIwW4aHC>J;3maRz|D%Cfm;;20Jkc31#VO9 z2HdXL9k@fW2XLoiPv9=aUclXoy@7ia`vCVU_66=!><8Sh*dKU6aRBh3;y~ab#X-Qs zii3ei6o&whDh>r6Qyd07t~eZcLU9D}q~b{6DaBF1(~6^kXB5W(&nk`uo>LqLyiW02 z;Pr~*fj1~l0N$uL5qOj0B;d`8lYzG=P66JkI2CxC;xypxiqnC2D9!-hsTd2qOEC_3 zw_-f-ykY|I9>ql9y^2Y|`xIvaFDT9e-mjPpd_ZwF@S@@z;3dTr;AO>B;Dd^3z=ssm zfe$NY03T7D3w%^D6Zn{77VvS!Y~T}$Ilw0sbAeAO<^i8p%m+TBI1l)&;(Xw9iVJ|x zD=q}SptuP5qT*uUONvW?FDn)RUr}5Nd{uE7@HNHdz}FR50N+qt34Bv=74R*^)xftE z*8ty9Tnl_xaUJkI#r44V6*mAsP}~UoP;nFRBgM_Yj}^B7KT+HY{8Vup@H55jz|R$T z0KZV&3H(xV7w{{^-N3IE_W-|9+zb3xaUbwI#r?qV6%PP^P&^3yQSlJ)C&k0SpB0Y) ze^ERN{8jN7@HfTdz~2>50RK=t3H(#>6!0&_)4;zK&j9~XJPZ6+@fC(tfL#?o1$I;X4A@=qb6^j} zFMvH2zXbMD{0i7x@oQio#czOp6~6`cQ~VCtU-5h30L34G0~LP+4pRIHI9Ty#;1I=M zfI}631rAgE4LDr!ci;%cKY$|@{{)Uw{0lf*@o(T5#eaZf75@c}Qw#~k{jXvX;CMw3 zaDrkeaH3)uaFSv;aI#_qaEf9iaH?VyaGGLK;B>`ez!{3gfw77ufN_c?f$@r^fC-AF zfr*M`fJusFfio4$0cRY!B`oIN>4S)+38v++8HUchI zYz$nY*aTRh*c7-_u^DigVhnJ(VsqdM#TLMoiYTPH`OYI>l>&*DH<(-k>-Ec%$M(;7y8?fHx~n z2Hv7L1$e9CRN!rj(}1@tP6ythI0Ja6Vl413#W>*Iit)hniV47b6cd5>DkcH%Q=AFB zpg0S7zhW}*0ma$Ci;8oAmlRWgmlaci4=SbsA5u&QKCGAld_-|B@KMD~;A4tez{eG{ zflnyr0H0LM1wN&i2YgyFANY*oJm9m6^MTJPE&x8SxDfb);v(RSii?3SDJ}uNtXKei zMR6(cRmEk%*A$lnUsqfKd_!?1@J+>4z_%1v1K(C$1AIquE%05%b-?!&*8|^I+yMMQ zaU<|U#ZADE6gLAuR@?&oL~$$dQ^jq-&lI-1N=sD zFYsH%eZcP&_XEFIJOKPb@gVR=#Y4cK6b}P`Ry+dyMe!)`SH)w%-xQAne^)#K{6q01 z@K424z`qnv1OHY$1N=wvEbw2&bHI>9z5fLkQM?}LQM>^ds(2$XOz|dQxZ=&g2*q1~ zk&3qhqZDrg7FE0*SWNK_U~$Defh8300+v*~8(2#5Jg~IlJ-{-G_X5i*-UlqFcmY^m z@qXYniVpxQC|(3sRJ;VNq<9%vS@A(&wBkd+DvA#St13PMtfu%Vu)5-7z#58=18XWi z0j#C?B(S#PQ@}ckPXp^JJ_D?$_$;u#;&Z?Tiq8WZD!u@0r1&DRvEoa>CW7bG@jYOB#rJ_76h8oV zRQwRwN%13KXT^_!T@*h7c2)co*iG>>V0XpOfjtzz0QOY;64*=eD`0QMuYr9OzXA4D z{1(_x@jGCD#qWUw6n_8?RQwS*Nbx7&V8x$-Lll1j4psaWI85<3;Bdv?fg=?E0FG4r z6F5roFW_j!zky>E{{fCw{1-S*F(eH4zlueG;}t!?35ub>iHc#sNs8gX$%+xcDTr}u6JUX2Q{Ym?X24~NF~H@D z&4DWvTL4!owgj$HYz17c*c!M-u?=voVq4%k#dg5;itT|L6gvPnDs}{JQtSlWtk@a2 zMX?KTt72E+HpOnh?TX!jI~02WcPjP-?o#Xp+^yIfxJR)MaIa!t;6BBE!2OE-fd>=^ z01qk-1Rhcx1U#%b7<#M21YDFr318iYIEENbw|%lPR7|aRfQZEKRW>i(sk( zUHFk9(-i0uiVT@f5Eh%pP0XM$oI)-gD^6NMGMA3i3~nP{;_U1+iW4aI#8Hq)K`2>~ zAxRQ(4KpcMTU&Lo&c5GjyCluQ&B7ti5r3d1R6X%59yA|;bEQjj5~Q<0G^8EFJm zIGdbwaT3zzQ=B0V#oUXz7I00O1d(x+LsdqGWO<33%qEJGJgGZ}Ff1;C>&vAuoI);> zr!m)-PjLjLOJ(yc;JQfVcIKo13y4DFxWqz=!s5hVgplpU6o$vaT|#k0TxN0_@3#WZ zh)>Pn{kl|RK03=-qVxnl3d+X9-IPW~C;_#&Xg*J1I+(uJb14Sl0D+ zl4adMNs&?)S92o~w}bIH7gu&Ch7Z0_Q%KFoXNHZP}0{_Q@@ z`FAMO`IW^j-)ZxF=DUcgxrF50Jg)w38@cp(Lh2`W)jh~d%+Jo^>*HPW!9|3tc;XcK86ocQc0gA)*kYv zrDs{*!<1G^JWXTq5nIf$#7AurX)HcQiQM@-TJ%MRJWfPAh>0_w@M1deuO|uV@KA1g z7H2Ah+Ro15>}QCJi*EJcSxVti=FO56mY%buJWG1sl90mE3zSqWF*h|ab7tZ! zzMx)&qX{YLl=PC1BMC42I4S8;>=jL#l{hmiHHqGNB12xiGKt@8Uh_?&^PZAkzcPuf zH|!+26e#J#We5&E`zwc8G zy~jm{eBe_?FVzpPNRnzkva8AB-h6CVlSS{Rks+VhWhg-=flseUl4?HlNz%qXzamMj zFDMB^r~N~9e@Tp?^ZufQue@cvbII3NBuO>j*h$v(^6eE#Vtr>NrF)O;_g5zI(fGkP z2}kzFE0fsz$xgD4?9W#wvGofj$?(!~WPc@=;W6{@e)E>`9@*coNRp2K;ZqIor9XYD zk-hYnPZ{0We_xR#)%;^uBS-dMyBZwXkT|*YQt8sQj%<-DlB611WAOzlmNpi8MUq%y zl!T$<$c7VR=z3%$yk)#cHu8!jsV2%!vW{%gE0V-2MoBa)r)Kg#El$8K(*z=yQwd^j zS(t^AJ_7H~Qa*z0&eFCZJF1K=U`Lhp3K(2Dub_h~PYJw_@>0BSl-FF5B;BrHCs~85 zctw&}l_*KZlY+)76U%s*c|6hHGMpe6WR)wDq?)RBlGRwXE0V;jPDwPmr{-bb)gY9% z^?a>KEN#o_N^RHjP2f|$wp{`5+d6gy($~7Sk87)*Zvt0P-&=v~`v%?$u%%FL6yqRuw*`)n6NYL#;NO}VR=IIo*hwyaFLYe6D@8|~rEB6xdU-Rs z_r1NDvOMWyA(jb!3Aw-7x=!e4XY*Tee>*#!+a2J|rVm~sLk4=Y^JJAV$j;`{gY9f7 zJ%pInL0LI*N!|-?s85=8#t*a8yw}QbpES!GL20~msXiX*NJ1Vuyo zFYy7LLKG!=Ih;8a^ZyL;uteJdjPe)d^R5=612y*z=Bo-ziQ=DaT-{UPaPs{|% z%wsc=C_IVQ%M>R`DT=utGX+vKpOU6x>&eA={}YAQku3omnaIvr7|@WP0^BFGPSL2!muRz{4g?vdP2=+ zCUTiv#L1}?=V{D4GGF5iisxy}J7YfLEKXlQaa2-f*4#|`;F0dU35zOn)r&;UO61Wk zrZ^&rO@bu^kpiq0K$G3G6dLx@kWY6<;H)LC<(EdoV*zj zC$I&8TDKB}rO2J_HVVTjF z=W&9tlv%tdPf!?1A;x?XC1g*YLJ922)0)9mouN21g^%W0io#N4T0bXYDqn=xiJK+w z4%bs0k&>Gj#|3XtkSY2`1(}j>k|McTe2U$yF<*1HP#l($%Y|=6ay~1!Npc2pcxiNycIJKXWJ~KH!mM5M_O5qyyeLG4ESgVDi#1Wj$2eO#u z;%&URwOR7}5mRrovaMa; zpAzVZY6ACvz!fPxg$|??I>zeA#|48ZiH@Ko@lF~{Y}G3r9pan7l?tD$_UW0g0~Jbq#qM0g^nxj6WR5X2+^$s>BVFp<_e||qnimRKh-NF%OY`_S0Lsi zGup zo`qPRC(^^@(6CHd(9A}%+{(_OI3hDCRs0lzlmvOCn`!~SchH>=Y4l{0-~7`FA_e#@ zD8oxE&b3HBm8J)RZ002kWm%NQlYBN2RhcJ{Ll8>&bl=FySt)UH#PTfQ+rWH+D9TAq zqVL<#%_CtXque9TCko4wCC~zd{0_U2!tkujSYDSbqBw$M-ffFDgQX>!A@>Ib1Yuav zEk(%6G6`iFx}3tutn4_f&{q(J6Y<;sN{S;m=Id>hW^lZk;;<}P9Ic^{N+)39zg7u# zts|oH3GrNJJpolL>xvDUAr)`b43;(_mK(m!kZ{Mhg@BsTTfVJU7MIzkSvZBa6Hzm= zbl;(x+~@674JYz0D~oH`O+drp&uR9+nuX!)Rl;!g5mD8%c-QQwn1(h>MsPqgxUPeU zgQB;2PRCZG}MjoJ~5I)>Un&-XVzMZvw>0{(YCQD83jV{GQFyvG;wLEB?TTx$X~rn5+ND;+ct3-^X6g z7XHL$*+rlFFxUT?4|DyW`!Lu4h0W5xFMXKHf91nm{%arR^4}0g=Ei4d<@0g;Rw+m5 zJECy?Uc&cME-^nN8{_zaI4YNJw}3wi@+w+J^%G%aZfb14(9agh2!HVs_wQFPaqoWf z68G(Qi)3Vfc!|sX=_M}rmzTKQ-$cdeVItof%VqHoB^0LwdW+MPe^DSgEr%-$Ns#U) zr%88X#L>)|_?&QeDRutKpGiULcTg*#b zw78eJXbFo_*evNKHcNSl&C*0gb5pZ&Qd8yXFXQDbX|t>k^RX}IWy}`kZ5IC;A7;M- zaa1ndrX|XLs%RtkrIL-@naW<2ofB;%%T;V-xvGWfQgbyMS*~s)%Qd_xHP^I}Jk*qO`{!#nV=qVcrL!uRiEN8Je6x8$#^K&km873y)|zHn3KV8 zgpCQJax>=8`N#XJi5KN*N>dB-B)6FtB{xPfXI2hRwasnhs#;i>C%G+czh34r)gnk(-H&x;-FCK2Ydj0pG@Vw1D4|I$6M_L z)f{f6pT_cJP-AX!07_(}$f9+im$=LzqN4mfG&@;Ny}>@r`9pk|>l*4U%`}XNy333G z;S@$t7|Z)%gazE;krr@$qb%U!qY1*P3>O)rF_##tF&7x8u{`k8n9Gi*IEo)8V$Cpt zkoJn6$rG(itQjVGQ6|U9UX(S%6bms6Otq2EuW4SCHN$i-$`mofMwaR30-eIu7H1>p z#uL)M&Pi>ZB@NTZn&7tRW}?l~Pg=`sKAu(0B<3NfqBwmrOqi1~XO>)mbPJ~_2XeNJ zyc_3Om?APQ?I5R!oN6P>^!-6PE_g7T&T(FBGJgh|L2*PLJ&5Bak)4tQXR&XJI7=vnJ3?25v{OLL4d+s= zlCacDpeiI`870ub=!vc1a^&;cAXXAq*a@kUuo4AmxgfYoF&P6}tva2}D8I%|K>4*= zASXr2uOp-$^9QoR>yb^L$O>*Cq#Yxl9-_jHJ}Ibila=CabhA$ioGp|RnNK&w8GLBB z649WUc-_0rMxMjB+sMayhmAaE?j+=z5~Y8;h^T*<5+!9frO<%*QLgYF6sNuk?nO4; zyi?e+JI&tJb4|9}_eL^-IaC*C11O73C8V)ZQ$kVdhjn_NAug_rQ}?WIik!OV>=Zq{uk%e2=Xy$! zdiC_a!7{R}%jQPk6e)9)ouc*L?3*IaEtJCh&3l>L>XRTNy3J0=lRbO8Pl6bCSP9mZ zb*E2)7$!1{7bW*z==QaFpHG4q7wiO__V@cFi17d=Pz%=8 zd(n%Mdr46*=F47`+y@D1FY%fSm*PV{31U2KC!qaDd=kWXloGgoz4{;XqU1hKNXOSZ z89ZUL`KE~Typ`e|=nK9n;=JgSf_h%^ zO%dm1N{P(R)j8)CA{x0h=e%ko&pEHz$aBu?Hu9YF1|ipkOZH8Rq?NanvSem^TMH8L z%=V6r+{(K)ax3rI$gR9jNc+!cF8jbYMOyoiQs@YIXRD8Fmi&*2X_VG%_lXxJ_fy#3 z$?r3pCI53`I>YSA@C%;=F}|dP$o%{i{GGs8L{T6f?bn)#FXw-wnfk2wTg}8h!goXw zR8k%Yf3I1%PxwIzD}o=1sEJg%+vBC%PhOO-?EOqwG(VqjD&$kEUx=w%EQo)FOUqsP zr06$ATCZ|VzZ23Q4)N#he^AJOb;R+X9P3vA|B{%#-$&_xBVAhghvKlfY}Ws!Fd{xP zE0NbYA&CNM=?p~(BI7et)9KF|BSSpM!e2IpGNdNOWwxZ8FbnwW1K}35CWx@04MC&@ zZ3&_*Xh%@gg7yT(Ea*T`9FU*Li|i5v^u>wH?0EhpwWOE$v-eV<1bio=G*MJ)QbJa; ztj^02Qg7*dMP!zRnU$HzJuK%X?qYdRe3F>gpjfOtGp+#0NaiJaMR?h9@)rP=ERrw( zS0>`N<6^V9o6$CMKdS(fHMgpboLh~MMwk#U-|VOkqVHjGziVh-qV%mM5e+F(##f7= zSZY#MMq(1iUmLmfJrF8b2M{Z2T|h=I=hRb8KD4h-Kwr&}A`K)X8;7@{1$=lLS-?B5 zu?4*EnpnVxx2Xkuc$-evgzW)1gdG5M2&qs<3;2k2BA|Zg!R>639NaEM+$%kNU2WuQx&f_&+ucUa z?Lo-n!{O`+(u3Pe^Kfu`6GhO|964fr2#V2HX1oWtFLH6D`VoZTa_vuHsGO?<*vL%J zPT_NPAVH)6PXdFO_%9M=8W?Ql$pkUP$`cw&B$e<~GmIdNreq3-Qy5MmPnRROL`t51 z>^+hwiasz@9K~XGf_#5uG-CPdt1*b>dnRKMr||?cj^YUNrNFfcVvQ%D5B2%rOwjaf z9?V2Q;#`JFfSHmr8IYF9Ia3HCrDCS3N)V?JQ73aaXFA3FDSjsY_-BR}qo&R0kpDmznLCt_x08r#;3O42YwBQrAM+val)jY6os5cN8=SVl*?AJp&A zq8S~jQ`vF~P{%{V=E^60FXBkinE3z}p{z8SC21=~TWQ+L&{meVa%aWUKl{tC{CmIr%0KkWulx(Y{K`M=%dh;KzWmBR=F6}AE57{7Ki|u* z{JXvU%0Jl4ul!5B{CZJeFX`)LeSJ`0AJSL;{ayC?hj;n)QGMl~+GXb7*yUILab14p zU)AMT{yANGqc95 z+IrB|leS*8^`@;4ZGCC$M_Yf|2GBN;wn4NFrfmpqLungE+i==O&^D5`QM8SwZ47N= zX&Xn|wX}_=Z31l*X`4jbWZI_CHkGz%v`wdN25qsl#nBc|TLNu~v?b9tleSs3CDS&W zwmGyF@KwsMoAhPha=z>j8Z|sIQ0g z^{~Dk(buE;dQ4xB>+1=9J*ls!^!2p9p3&E{`g%@ZuhZA-_4WVx_*3cFr_q*9TLx`& zY0IQ7i?(dqa%jt?EswT*+UC(VpSA_GEu?J`ZHsAJLR&$B?o)oZVqT`N{QktuZ%q8k z?@0X0Z$^Z$A9W?>hX-Z#VqP?=$?$Z!q-wzrJRB)OG)bqS=!%)u$HiUUTw4s^jBOCg9KDHsn^N9@!o=c5jJ^9NgL3;8x66#A&{;{E+ z=U*F!dP0(9J;z#@r-%*BJRTeRdO~eTp?4H-nFLR`4d_XPPlEI$5(y2YCs8)k^AxpV zsHd0>VV>ePH1m|Op|7W;4Jn>dHY9jT+kl>w@kx-Lltn^A=}9>o>UqlBFw}F64Pl-N zHZ=28w4tx3k_{=I$~Gi;qHRD=s`w;GPpTrJk@TdR4fQy_OnxxY-L2*tR`!q{%dJe}lK~S8P&N0mmoSwxoO$~IH zo1(YpG&eBOnxAi9X>uS+oC~7afoP`Y(e%KiyB@&dUMO^gxuA z4x+h%^RhrRIna%*^o8$(X?kGfN*QT_Ae7!P(iA}`-C?9jg3vw^HO22bw21mT$JwG(mCVTy|)dpm?UF(|ho%Dp>Hz~y2b_~5KvMw$^?-9|8sMBP z0h$Kr{NNt&-l2JbiK=6wiGYavz(g|v5qE-#rUE7{M{@xYcZ2h2G9co9FwtzldDIam znhJ=xCrmUCa2|DqsdW;sws^(ID?RUOF3`&Th_2F{EA~KllFmCv>yGWyaIE&e#A`@o z>B$8JRQLbxzY#SH!YUsr7*VU>pO6u4N+y-778P1QvVdj@D5Yv?HxSo9GLxdS!Uip}n}q&SRpv3+<^9 z85HAx8dPr#s(*d=dZ

      YO8yzz}I%cZ3^P?%Z zL3iK75pQ??d@S|SIvmr{dpR6a(R=s9ktBl}LygFw82{6tVyOli%S0Iq1)Y#ZeZG*5`1{u}9>4IFd0SIUF-FAfLmLCOwa*%B1Iv|EcGhR0DN5SvpJs zGxa>5dY&5{lN}wC86A`1?R*yHHW=i4ICAaIpUkW?Z?6kC2NI^B43EI${RAk($-Z?`_^j_)fWGq{#dKnAje;Uhvs)2^ELxw;B zGmT|4jb&qW%zE!Y4p91)1KDT~#P<-a4{jV=WE=;nb{Plbe;UVGs)4$HRJup zjbm4I%#P@oZQh}rqpT}0?p^j!&hPL!CfkA=%U&7FbyU5Kh4DX)rX4&`ymy7CG?X%FT6ai3#yG`O*xk+D2M)yr5I|I=7rrW$An&&UucV5YI$ zKx4TsI_9i*Ag@sRl>@oX9*FNTIUC$KZj^DnO0~;482{5aKBO9``)^A3DPX2?+)3lO zJv!#r=$Mp1&POWlhN1S`E%e)4J+lt)WAx%1_B` zaCh{Tv&H|hb{_Cml-b|EH=rWLf(=s4ZMhN5u%Q!BN$(9QvWO)>BB2G6pvWplK%|I@ zARvO$M5Ks_fTJQsS3z{Gi`})?wP3-5uJ7-hXYMo4+{}z{|1X~pJae9N=9KSqrrgQR zpqmsTJMwAoVH1P?5VmoH#%H;12u035Cue#`ko&H!ryKp-9kD&Rr27Io{n3uF6!&dA znbDV+Wkw{%#ONn@fctMS@XaX6V6+#Ec6ZcvNkB)0-Opn91%nmPZc*E8&+WeO(+Z$p zVHtiZ3eeLgAhk^lAACjIWy9w;^7XVmpQF&}Pnmr7F`wTt%X~8#76xWSG8nxDMsIY~4oN^s!tPu# zBxA4wdPCI4J@l>u$Op^tJ5hk%H36wTWcXk{hiv%x$=AE~d;-wv@0fhvW)H4# z6OnH0$UXG2;LMCZv|-eXoPA}_s5f-_mnNexm{A|hG9waWVw3|9U~~ZnW<)X={QyRX zJ8IubK)J#$PYn4Otbh)S+PH^~D1ZuJ8U85>&=C`m+Czp9=JTx$pF;9=#GX$Pbox&w zpC6e|F=m+$i81jR3=iN_j)D1*3_gE?&mSGNqms`MVRwlbhGMYt`2+Pt8YnK_ypa7J zmSJza^+FaGZ$4=-cH{;+Dj*Xe_xtzAm2DV#kBhgxvRw+D?v0mMHcvbiIvlf1jKr9T z)xZNBU5SB-kqlz3;`6l=<0DU3t`bJ0#ZZgEitEI9DiY^xRN6+tH3pX9)={|Hn7Gt- zGJG66t+C|1jXkY#(CMvBS|>BD@t9>=B*sK*3Os<;Bn(W8WY9VjwA#mOr%7Pf3cIOd z_y-0nu=W5J>92DXVAsJie0IF`B6p4nOgDDq{yI%iKXzi*llOD%iA{q}KiedB78APx zvrLS{n261T2N1gn0}~?|#F9WPLE^ea7|j>Mtr)Dh5|sY(DY$NfWjHwsm(Rqd_Lt$~ z*lFEP&VBZ@7C@&bo3zelT6bWUX^|Kct$X1Cw3cFES|o#3C(ufb*HR>~mBMb77*=Dj z0!vl;D@_5m2A1LTzxO$qn)c!Jj9D9FlC+9uw zY3+bc?_tvF&a`%7mT8d~6RlU_0kodOz_dsPtuoLmiPwtawSsspPhxuw+Hh{X@=(3R ztX(fMdW;^b7Z?EPp?V&+BM;S=xII)a=b~Om5H5ftovRR0_ z1P#Ym#}uw30PkD}i80mD1s;%onA67w$*7|Vbxe!bu8Y^E%2NIYm9?9unWgC0DQhzI z_-eV4Ye|QDu7$*yYPk>|P(m**0UIQvmRYD}X1q3C7IG2ht%b}q3sKi(`tj9qGuP1{ z-nkAEW2&PJ9*}+>r;iPiQO9klV}86gFJ7A?ODPwo6=JBwV7>m%7pub0eC|-LzXMX z8AZNU*z>7|PG4^FxtsaaV3zri7!#j*cmSU<7?=;q;Ikfl*2QaUn}Blpl+!I>GYwqbM)IooK@XbN=t29wbP%;;Lo zG9waWVl)dLz~}}H%!p(#+6G2jjW=3|!mkQfu6W$*w#3o$SslEG&;`0R?;9+!OX z7Iw?UumXdX&o0yxX`p=ypL<{#-Wzp{?KAo4#*W-Tj|<2I$o)DWdFFF3dEaMGY$bI1 zUX$1!CbkN*OpL^sh;4)i5W5cp6C)YK_Ji0n64xeSv{?)fVzA!68CZ70LWvD12poFBBOwG}%3Ig{1_ru8spnHGsL(b@$MptS=7(;^wPUIVRH;z_&wU4~NZcpqf==4J-v41nM zr!mXKNQ{ZtOYi_<&tYI96+{T(7}0{GTXX@0+;P z{xW0#oWE~R>kxGMe@t5MF|F4z%d|+0iB?KWrj>w!X^{+CDGB*nFhTPtXvqm$ zQi7I{5P2FKhCw(rA$-{Q$mF9hhXoVNhtU26aVDdWg2~v9eBCW6Vg2+~_=q??s3%~0 zHGNt<+}7rsZ_1~_ZtJqv_~=Kgoe@<}O(2mL$`hb}|1@TDvOOO06W4G8E&cg0W-27c zM5P}*z)?B|rb05P^Z=D^30iuB)+IqpOVBzeXy-{V7r-XmD&`tWFoZQs~H_JW76r#bh2Q~bV!VeP9;2mPCf>vLo(=OflmJf z?ZO1DUxJpAp!Jq$2EYLD1eZ?4rN7BVJ!CEvSg2|Aeu4!xjh>-w_ZDENgN$z(W^-K^ zBM8?;VoY__!UO8MlFPvc$*5}}>Kc}y4NcI7Bxr+VQDdORaUzOJqoRh{7c~^qGw72z ziW-uD{vXUW4Z`%{wwRW64Cgw=!Y|iBVoY_+fCr?1EvJtSl2ONK)KQb5jY`l)BxqMA zXqU@UX2KvmChC~3F{{x>fqCTd&Iqwa{CMX|vtKV4%i?fMTl;l3;^||W^{bdM`?Z#N z%z-iUATcH$OW*+*ZpFa;N-}sffXAc+tu8?upP-GEFqT3KR?50gGD)b-S|>p8x{g;G zbgUquENmkeau*zPAtc6B$a;7{A@^|p*dQ5&G@+1b3EFiD+SCMXN`iK^tmOe1SZkSP z)}mjBL?e%grYgluQHr^`Surb7mJg(z0_~klCjH!-i;Q{II=Jc^aGU`}} zIu;~owim3T*Cpll3tf3EJ8OZMCfB3mAkSObGu^y`9-$mZPsnu8~vUI#Caw`qrAKzSW|f zV>NG z1(Srjum=SQUf2W5!agfVC=2@%7t#fexeyX#Dx@DgppfpIKQ>54A#b3NLkZez3EC^N ziVL6$zZG?xa>y)1e+^kimh=@-2`wpqVxT(^qf&?Uq^m`o_-T}RXN{2hTg_Hg%$TeC zCd0^rF~cA+CKzS#00#LOcvVRTjQ0WKy#(zYNunI{KqS`lZ*=eZo{2$S&v(rAG;WqZ z;8ZK%fKw$grc{T+15zEt8DfKEr1}L?{VYNIBtiQ~W_uY_;jf|&#m~%y^-q*_`{@76 zx>X^h{#CPe6Eo(zeaSFJz?fl>7!!;M@Bju^Vc>Nm888k5#bia1Y~8-+R42j#r%GZ>sa_8cNOdx2hz*jF>TgK(mjvxdg7%}#cA7A~K@3e8=twfZ zaQ%z1Z1iQ>KN8IEsoe<6@b3w@l@o<_qXzxMEL1mkq=QvIVpgjEh;2L<;ImBR5#@Ap z_D2HXH2=c&4CwUV6Xe&@jxwW}m}N#J#>D6jcmSF?7F`bks&Ps%-ZK8>3F)YJv60LVqZ4=EWDaMYB=>#~zlN3HNw@BnC zDf}tYi}`3|OUQBCL|bG_q0`$WN@T4QsnWYJ%g9KK3E6${07v&=U}Pi%*_lArK2bYO z!dfTn?ia&)3|3g}MV~ZaeP7j&5f{beqW*HZWG2wa-9)RoL7#J7Hz*P)f zg^5~zqL!PeWlLiJ5!UaE;R6g-Vuh%R?hEJ$EK`Vm2+MG3qV<-y%p|58JMs~jFR(MR zTm@OS4YH5OahW}`kD=2`O=KmE>=Vo~G7@7#_5(Zs8U6A&BO@8eE&;N^iQ2$KZGhzU zqcHtR3`a0nc?}k&@F(zE6pUAjcVPIS&1J_l+Rh_7fOw_6pwJRjC_QLuMF`S9PN~{`HMLKMZ zLhLM9hHDe8_ugYnV!E*-ci2dQosm^3$gZ$Kb~ZU4V~^|{==53>*=R=A0ke#Z#F&t! zzymrg2?HY|8OR!etUghjn5a#Vyu!jXRSf50u=1)GrE-T|qwwkk%kb4vysj~MsU2qc zU|bUwToY_?btb>p*yB1MI{j)B*JQ?(hFQi%VobRD!UJ%1#lW~o2CkXFH9b*lO4Oz$ zYS&3({e<-eVz>~4mDqGt73r{>6=D~`GCV8ltbemfOgDDq4r>zF8QC-i*>yI^`jg|E z?U7|dr_VBx-NeYUFw4kDj0sseJOEif21Z6QkSzeR+Y+_;iP}8Lt3sGoieUf-E3ex` zsoY_U6kZp@GQ2Q~*CLab+F^zd#x-BTHO~guK=QlD9@ik~^o1s_I~dns%rY(#W5P8O z9)N2Y2F67)aIFHadlR)4iQ3(X+Fg>^C}CYKh8hf3V)vq|NQbReh>eD2cuk`9XB}%z zV!E*-ci0Mnosr$GAiK*3*%)%X)*jhd==3!vvek@i9A+6Ai7_F&79N0X5(Y*_GLRMH zo8b(Z2|)PTxYgthA;e(!fP5V!&{wG5kq<&mVBlp$!)K&+b4#nFj%?0fqEjRws#e7 zPs1|&PNMZu+Pfw<-Pn=a?vQ{_;7TJ06yY^6?flhzNgz`2+c^0z_g~XVkyaEq^ z@;nBHLNcIy1SlU!BCiUg*TnE|3|1l^D4q1FLgWxE!=FSE`P3w$c9P-40_1ht|5JM) zZ$PJiVgmV?fxL-X20~&?Kt6#70C^7s10fkez6Fr46Sc1-lTU@+XJYsqgO$nGN|$`E zF!=(O;lqj62Y26_Omt&M?vk%;y5vi8@Vz~hub|Tpn^3-EDF4MQLm@FHC_lpkpd7}) zP)G)pUjXHZB=U1~Lo-10fke&PvMH&PdWuPts0J(%L0O9_o#PHrzHzJizQp z4=~S2GM~(yo+QpE^c|;Dv2A?EN&LJSS8=_aIf?g_?Q(v%*V#$5N>?EoS4Uz@)iuHc z9F60mut74aI~Ua@CTa0WS_fI$WT;TKD6J2bmS~oyu3S8(BVSzUU~U^fNJ!?)uZAk>4Vz+4xTPm1BneI5{6|0UK&KB*l0U~7#Ejm> zEHff8CPrVt1JHbkfv*xIgVE(+G(1TgCINjZ?7kAie=%4A4L6pUUP@4<0Qwr1;VYv6 zRhfX)Bi!)8e1_TZ`G$N|+4K1pI{iwM&lSw)JIpd45@X`?2Rwk!PZ*dF$>1{%e8wbc zqm#56iRgdA^iMH(T16uogOVaQ<#h@oFD%0olB_4eIuns@?8rSd+T^0wnA@_4;>cN@ zJ);)T=@U#wAy#24+Mu7+nKKlasUt3Fr)AccvK5!eH&8$)XB+k zf%%XOJ~xBUO-b5}B<;o|?FLDyv#>s23~3mwlx{**kv5vEQ0fB9@SG%Es&?Tl;c4ne zcRF)TO1iNlx6up}jeeszQS*;iZ!qU&OQnAX_gqWF<5!sAxh$|TB7jEg=Khg6t5*FFSV--AKX>9 zE4Xg8!Ie*bm)PSffKFd*;<}S@6=Ifgkr)%MA@BfPWf&M2$-uQ1xK<}=E0eT)lCC`a&umG*rnw7 zetTrYq0`ry$nIlgmtmHXkr)%QG4KFnBQP*Bl7Vb1kZnoQHYaHtC9kox@T%cpn4cH~_at}lr0mrS|LLJ%&B#F&brSIEH8T&@KhB%`Qo6qT8* zU6ia{AS+r36{-~#ls`Lv)LCR|rayauvaK@RF7*pn}-~kECSJ#k? z%*&8@NwQXytQ90{c`|u=WlcD&E=P%(yk3MXBcD+UME1NKc_RDSGj9Bg_jQ+ZQS`PO zE{epMiZWgt^8nX^>PSXWgHhDLWNkpQRv{~Tm?|n$mt&w=k-8iML_xe96`~+zIfiiN z+aj5h7*po^-~kEioG>;>M&?%{^UIU9;mO*tWNoNS{wZj~UDf5d+)Q2{jw~a~F-&C7 z%P~}B|JTb=#YH`hAiNwT##Gcx@PJzOb1m2)8AXjoQ8mfhsAO$~tmtK^P_1%w)R+~i z%P~q6#LF>46r?OiEoc4;oN?wP#+3Pc@PLF5al+Uj8JSN)=5@*1_+)LY%=|x4S&!>F zGjn}BQp8%&Kl)fR_2$29-24U6^<2yQaL=`n7*j1@!2?S8m`lJ0$*AQT)G|3)YmkNf z7xUIaCYyz*OVDt9bxh$pzJ_u3${TnC9U)zJYSP{(PUJ~l{39k-#5`N`V6WNnTtg>Hr*Aa*Y+yd6m}NdB#>D4xcmSUv7?=;q;PV9dJeI6I znyl@Ri0BGghVv{K{WDp6N&;$t0RTC^3Fn`pHtwP4 z6hK#Fzwm)5K+lEMQ^yV_Ry;+Dbho4D2V0}qSuqHXX7_aM7psf_t49NGc$V8 zh7rB+Cj5pyBYN$P{<_KN5Hq?Jv)n@@#>D6@ctFK>VBj7i8I0ZsqxX`vcO)R=r8&ww zajbye6SZ*(_2h4|Fh{JqH zjET=icmSWZ7?=;q;PYSb`7&AiT=My=x8Hn;dLj+}w|WaD*6%F%f%05Ze(UMly)~1Y$o(T*flJ1ezDFk_O$4=IQq{fts_i}UWmi}MPf{} z{sj-{uV*oEe~}DYUSGcUXR`K(1oon^Gv1U#@4~SH`%~$!mh>>n_@6Xhfn~Ub&w7z- z=`){X89Q=+{c*hgMQ`B=xAcK}^E)Sc?~dNWC-0o%d{ijCFo%he7!$D%-~o=_#=yi# z2C>#4*2))odiS9)`bZ2PW3b|C<)gO14?}SzwNr3?0?TmQC|vDKTxx$AK90S=J|*Yv z>}h=lo!-`@)rM((j#;KfVobDtf(Ow01_RR~8MMv@tuuXEdkO4_u=`mIzhJNeI}^Yn z=dX?muwP*r?%=at06Ut%bYn;Eul9oau@n1^ymz!Gb`(0jgGuZhCiXjKnHY&N5jzpT z_zq$o{lKiHsm~D zPpd6-y5FSbV_NMn%d|+0iPm}W07%IgxW7mSt-heu$EWr3X+3;eH;JtiwBfEk^`W|1 zyWY#_F@C6S0OW`2*p56@cl~BoKQ1Z_LAWRqV=Af-JfJA~E-8{xR5psr^l2CQvoW?kx{3=n1UqEv{oltmfBnGc6E&YZ-U zGN;#0A@dQOFg8d==9eS$;XZAcPa7&Tr#DGi+iAF&xjqajVnz5|I@CgipIt7BU6%)p7Lj5@}njdH4U$ny18SM%)9Pd)cVgaJ$Rx86bxrDyuZ~8pV==sQ9VEt7$69zm`pY?e zY>GRpIA`Hz?QN^{@<2^I1Fd29ttr?8t}M z6cdAfHMXOl8$LkJZm_@J(#y8=Y3B9zdSBJV2cVI!;364}ZU&>9eA)~N zXs57yR1EYgE-Rp$L~VQnJXZlkFV_m=cdjj$w7DiAwM`5keD<7S!{>4GHP@cc6VT~% zOg^)j&o0a|9};8Ya{wN|XDR8IcS|E5YaPN1FaX336T4BKJv`x2zlRPPwZ#t^ao91 zo0-@zm}O!l#zZXc1Sa-795FGHL2NsSZIifK2&0x_I01td*EXe{9#wFi2+Q!!C|r-4 zxYTwsd>lKilgRm__Ox0-r|&dr?O<9bW0q-=7!$2C;Q{^C4g=F78MO9-)^4A+O9DGf z*qtqgb1+ze?N<8hX$2U)Xf6Cy)baPU2~0P3IYbY{ zt(Y;Fwi6Rs3u7iiVoXFHh6fO#7fvw|l0l>gh;;L7>3*$?UrUojwn1xM+HNKeJsrhH zK4W(gJZNpj@1ya`rU@L%%J$?s9)Vx3gT$EX*b5J+L%e7T8ziHS3sFZuzn0rrW%5gaPSl?v*I^yYN&3aSJn7vub zJl=pYuPKQ!@%S7bfPvn3#l1-~cnkrLL4NIGzgFqj$|a01pam=Cv@^&gp)Tvi0tBCS zDwWetxgeo5=OtXomvGF5kQh@TE%58SD1=__#D$QILPnyHD!+DxU%Sk&UFz5VE^BEC zgK)J!e3DTPUsbBia`Y>ZYh+mWEe9K z5@X_V4m^OzDHxas$>1>oJjVI8F@9~dU#pQY=v7W&r7Y|?lZ3jkV+06Z*wMru!*{MxmC?Ha!}*{?PDwMnuZemT<({_t>DMCN$l6{bO5(MhY_4sCxj9J`cTCIN1?lNGG+SmdV=nVFrt>!#GaV9R zqH_^E07?&rf(?>EXD;Z>_G`2J+DyMT-LExCH2e~#>y4EjKwM^H&s0`= zy0YCQz$mLekL#khIdNSi##9%*fe7W$%b2)*#T$vjOHkLHer=&&Tj1Aj^K0{EU6;ZV zO(8m%>$=mvu7yfn3zS-JQ?}DYPF`IW4!?+g4 zyvQWR1Y;&VV3DuKz%WP#jP-!A&abVNByPey5Q()NL_NFC#Gv-W-G=0;K_8L4hXs$2ZpX1}&kW=pRs3U7-HF@ zdLJBcswBpg>Na>lst<66*dQ6HK7&-B_G|n6+8)35q+feN=KKf@!uz9+x~I*w^?l0f z?J-wRe^Q)3=)>j{n0EfKX}#Zj6!G-^&6ZBgm`nF8^Uz_;JV=a*2fZu^7@owyOGh$z zybK;M`n4DQ+Cjf|K*HD$Em$eH1uvQ;)CGLOTtNMxaw0t-NGKPGSGbS^aLk2}7*iqi zS|JqjFU}tuB%_eGP{R_fkv578m~GS!mSJze`nf4CK#jo9qjY0OZlj|DHDmf! zIgoy~L3Ro`jtkhf)Tz+v-hgZ=Pk>hVG|VzG5@SM^3=eR04hBX>GLW?mR$VhCWc@@gHRD#e%FPE~jXVHrLpir1+oFSV--AB?M2fS>m9Ly!~U8)slX z??jHk5cxgT9#;x<`Y9%^c8n{GS;j?TOt>zD2jJ>~fpL)xT#3LHAJ94kw6g=+nUdH= z!n(g0GBH?*#iOc7hb1e-vS1lLH(>n$muwQ#jUBneItc8H>}&$#JqhvK;92 zb4_GPj4T(kjEuyXkPUzbAS=Sa$VdjVPC%9#&{6_gQ1ZH1m<|-fAPiPssiIUqZ>1@` z2E#IZeiW}Xlb70Ih7ZP-qTmYJ;2J`H)9i6w0-b)oiK{c?8j4xQMPf|2YTyC5F2lgM zNCvJ9;OZUFdIq%a0j;YfMy~~f^=L8FVz3hHjjAFYc7Z}{EG)zQ0@g=*7nsC!V@K|= zo&q}~>#iW{YJ+S%IljOi*#zkHekQWMjI0i`jEuyXklhRqfN%o_Mn*D_6R;WZDI;lco(dW&0!VRY+Ir0_C!WJcKvqf8q{w~(_U zdq(r2(+f>T1X2WPDIU8cnXcct&V3W}xX0#f!%!tI880qi; zMh{_NMkIsLL@=5V(8dL{F#&C~#Ppc3rk8?YrzbF2F-<^KkwdRR!L$pO;rf8}HoQT> zWbDX?-Z;UUk&RK1jkZDdBsp%dN46U}z1~DNiIMHWEF&W^CS)(b1F9D5_R4X#(n zZ<9T)SE18yFmX*|T(4o4agi7ku8-gWl;~|~++idG*KNQxKcLMEXmbME%>nHu3GHLC z!zW_+6oVDod=wUGvO5%LpTRP`AYgrfc83W~H+JMEniQq5r0D|=LGA2ke2;KvN%LCf7fVMQCEtdFx71qCr;V1?x zzU88F?zvS8zTaUPUKxdNm5ER7Il~9jTc!|Os%$T|q4x*HSY=O-UW}%%H0j;T^!~&w z(<3n^dJgX$+W>m&1KK*t?XTWDwjT9F+HSMLjo&-ADPVoJx7p;T8#{8_trPGGoP4hl zzie!?JrsV~*d`OoMus9^Hb!DhP=a{X4_Yb-1Gf~(XsK<0vQ-iZ38NG-gfUnV5PB<`zTE`!2m_(Fp>dax7!#15@Bkq6dNc+? zGJxy`kX-@oaml2Yu%lOw!MqO!E0bMHm+VuRWWX}KH(-5|xX)yw8#{8BJZ{q^eaXQ- zdno;&)AyQC_ArzSFw0O#j0p<8qzqNkyVDp7$$+vSP@a)Q3WO28o(#4{7_3B|QM%-y zLZld$;pYN);wo;PE~DGag9;I2M@wsz&`t;KDU?E|KW9=nz!d0hXH0>_m?(^f2UKr@|R$PGU@%-wY4Pd>SW=4U&=hFUb5zK>IPE zeIL-ilgZD9*19f7%;fbSktLnnXOksGS(pS_UHz*>(uionm+tgY^v3DrjDL+Xc;sk~%EIZG+a9 zY!@^iN*X)zIrT(1!IL`f$(H7}yb3=?&f3v`hT8nu_T$j$ZG-YbWE*Dm1ZJ5Li7_#H z79N0R4+cK=NCu;`!03#icDe+#U)UWG!*dv{fX)#0@GV^j1<*lQhR=xt)WHO#c7@@C z`J8UU=Xvtg!Jf|x(CO!xe9mS*|H3TuAu%RCZ@~ljyn=!GkPJRS@bL$=n}Bll3U$wf~xw`C9ghn$7&8NCmko?Jupl^lUcVakC?o^Q zg@Dp8sAUAT-a)OWMAKSWw-G~I3|2J#P*tRNG8HtZz%txFXuYarDrh1*(p4qH;7h-4 z+dIfl`T4!>=CsXqMf{i*=baKPaeE4vX%F%Y==A<3$cq@{nV4meB*p~N2M-9{0Rw|1 z86b-RvM{LS2en*D(JxE`VhCceQYz!i!qund<*Q7khl8Yd~fG)H_8#C#KC z?y*DcMA6FZA$EpNFEt^SFvRmQ%MeM731S930Ae}@hDb6X4gwaRm0E3m|P!t>K#>*6r7r`<-Jc{FGCPzK8BX#2tlbAlp1bMMJZPSg)T~6fZQP~vq zGJBjk(CNcXoR>1rT+A{~5@W(y2@k+oh=FmE44hX1XLV2;8PuvI%K^glVlfQFU}aft z)Jr`%MqxP^mf_kcmSaqoYEMRdP*09DQC1x<%D+?0G4?2jL8sT6C`U8OOEJqRNjzSZ z3xXA1t-_m12sPmQ9QZyBY99x+4};qK5rSRxPr0P-bi(o^_xX+j|Bd!ZCz2lVS>y|v z?K-GMCsucdw=aYG`v5S5eilBXt;ZK1&mE(GNi}2~4$^`x3htUc#~c*$I0OYEj|sp?{1BbBqYd89xN^QHzr`at`$QKIrL$ z=?ZU8%D5M={brBHlSxUDgcovVH5z--xt8Yei`|$L+2dYwM%z-HeET5ZuY;C|vZk-O zrXT+gHJ#82dk<<^;mtspZ-dq{f)RG#a-5$W;sl)71x$7)bi&>g=K?F#3h#wjJkYA} zUc`_#HG^c*5)Hv0R>cAU(p-Nuu>OovhOY2ta;H+K#L}rn72X_L!y*9sA3F8-p!Qo( z`z5FyiF9hQ{=219PYA)hg!bXqGCK87s<8~kvbqA^JR$vvU8j0NXoHLsL$P%#;-FKp zH+5R0K&8k>A#3$K+urQ(~{$~a)|R+%_GXe-V|pb zw@9)#`ZzLMM8xJ65k-p@5uD{QHAra@UYEh#BD8tDEz&833&MS9S`4c&(6X}(BojmU zQC3JB7m9q`Tn7VvTnLA@k2ApAsHO)!;jy7zG&aqr8{7#YY;ys^kdpS5=45+3S!C3A z5_MP8{qV#&lNeLZKZu;ajpR%+a$b&{mxZ*YGUp#LA6|kC@gHD%nie2MP9168>erWr z=!Ni{qP`T{t7-di+tMty?z@6>{Rtj8R}zmm*V}@qwgD@Sp$-G{B^kNah4Z!XVQp+U z!nYCg`q;4i8n3~3Ojz(;M104GBYcG+62>oOntUgQDb!?m;+#qRi=3MtLV=!BhPQ7q zq^;-Fint5uee_>p3d5HeIAxNN@}Ob(f10YaepQi_zs9_NVb!ec$!WB_)DTUtV2=I- z`(#y-lW(vsu4dr6%jfCazsl1|sJ??LJo?Irha1m;;f-gU*77{surOuwQ(VtGA zkj!1-krtK9gQu9vYY9H^(}EWQ8ziH=OHp27m6l(n<;n_A5T++#2$xia&mFdFX26eT zKLds5R?VJ4kK1oNVI-9gtM#CX3vVe^$RQc(* z6@2R@RXA;OZ~FQSs1npqCPhAiJirt%1{xYU_54*SyA20rt3 zLpb{E(}rA_d0q(@hf~sLW!)F-bFmSn9ZX<(3WjiL6;&gw?03V}^1dK>J`MJiZk)26rgdAi{rs`!j!toXdYs5lW7-*v1N2VlHR zsrbxes<`;LDwYXFSA4c@#eDNeYb-XfysiGC;#{P&{8%e4f$<8Z;&YCv;(?;#Ud9@) zbYEkc(E5ONjXNTkOK+4S%G;gNSGRwwQ^uewH_I~9vd=)A@L9sayMjjm6^j)P97l!(w@>#pt-)Ftr-bau#@;xDHw1CI;mZbfPbm^jr=!eI@mhAm*$F~`gchA}LWB?` zA#RYjQ*n%^{dqVS!_Qm{ycQ(mw0|W|`wvxX4^~I6YV(ENZ5Z^2s_9G)l1)SK28m#w zN2|%j?NC{+X%AO>ItkT6;dEOy?d0L}aNnKKZm-6Vi7}Zy+1ry&&Ydu+ZzJ#W(&-KK z*-#3O4xD*JVH87a1n^(K#{t&1;wanqN^Vak1-S>^i7rU*y>d zSPE$4)qapB)%@p-9F;Rb!!^uhyQE3q`+; z98MpGyF1)hG(CVm)1N1zg9!{>eov#zQTVZHTz1#-Wp`aF-QCe$$iFz%UGTuEk{C;> z#_vV%iKJ@$Ui4_B`l8H}ej^(7#NkWp`iqt&Z|a4nrayr`uW>^3tE=Hxt0QK{!ndU3 zIUSYZgW>EHPv4iZNW%U^*mI|u8bmq?vs@MoV=Ai#4&bL61FrzdSb<3>>%1B*ToXA| zt`c^&Vi+f^&aV-@j|C{{`?nfTC#?owxvilE@%E(2PMFlsufZnGRR;QWsS#nu!vP;` z_W?;Jt=+$?BZl@jhB%Sn`BAur2Hq~sNH?5KfHVC(Xm+I0U5#=3Wb05lo+5Wnb=JLG z;)wgPt$jMAyY>8ZdRqiPOaQovMj_rTItBLaTthS`VG^fOUCEvFn79|5cD<*Ni#$+c< zhP&11eTb(-Bo0hE-Sp{ez`X|!^`132Sl!H%`&?ky-wS(%Q*TDI5|d~Z*r1eEB(&^{ zj5;9*w+j7s9n%)*#7^=z=14TrweT+NknHh#+j-l?ofNmI!xa@18*A$(Gz@I4tFOAM z+A}-O)2gK>cxMOCi7mWK71O(%Oqa3gz>dPJ*IU`qb46DDRi(8JjUK$Nz6Ji%ORtBI z0k5|ly3)FlRpSsys!qmdS+BPgs{Fe8@m1+Jq2SNGRS_gA~PZ-maFuzKgn z6I~2`>C$(=SufCySTpzI)}n$I7Q}uyIs1U@8W)*tB<>+kHs!N7D4Bb z;vKH;@0ISCySQKG>SMk1ai5EiHPAVvxXRW2gVOy*7xxdi`q(LbJmQ?j!%i-|-iM%a zIIno)9)W0bV8a=bT9&gK*IEyuU<8(|bXE!g-ZmT@4#Q6;;qkS@^-Oh1$xy60T zKJL@*abJ>gUx1;*iX4Q>;S_rSDn}GALurHJ6->LJcw46QhI8CQZgJnSkNd8B+%II@ zPhseQ;$x^BP<#lLBZ@Dfv_bI|rd?3{C{sG@9QRwdxIfv)J>nkM6Cb%K{{ce>6i1=5 zMbR$K8|RI;tv3$SF7=))j=kC0-be;-BhoVy4;+}6GH_bh6cNsU`&3O-d=RMt>mrLg*Rzu4@VG(o=1s6bN z+dW=y9#jrTDNe&fWaNP^kq0=tuW)r=CEZ`{;(j=E4uuVKjy%*ga;=P9;}Ut4v-=UQ z?(3!dIv4ljp>rr~tW#vZb($jGPj+$N;OgT>>0_FUkL#dwNO7vG`J9D3Uuw*X3;E6^R7b~z*8EmK+~xLhSGdQ0K*n7MLx&Yv z3zfrRz8We=6dRzlL9r3jE+`(6DQ$I*yTvW;cKf(H+~e+%ad*Mc0mb7`*`lC}@m~A5 z``qImka3@JbN-yY^Mmfr|1F)r0z-$QUUG|j$Ug4t?s4Cfao=`x{vUhi@4Gw4f2Yn* zNW9))f~A!#*DXJE4h1JeWxI-AZxU45lWS_K>vQTRPr$Q|xX2R{KR@e8kb31=M}VJo zc;ix`jBfa*Ae6Y|^^{3>gO$?%mZa06b4a=iR1Qg}K~+{Y#XjTCP`Xugp48h^)C)?d zin3)z{bA))(S^`Cq}>lH$Fwt`bW6Lp)Hh2Tw1>;whQZD$x1rEA%dG{k^APDiifYj7 z9VB&1XnJ1E7tvZ7y2d5+DCis(dIVI>vJy|)u9T6ZvT73DdAZapnMJyD43ti5*(j5q z1S=U)4%M3@! zKV|rRF5&k;=fLbqs2nnTLPoaF>@lftmYFy187Q5Yy(E)<0ai}T4npUU*#Q~ZKC@?~ zzFB5q_NEMf$R+%1&^a)B1uEOj=#K9#D4h!bKt_JgCGtDY?veeM(#K~mK0blYA^VS< z-FxG{g3>Ab?`7m~T_S(&>>k-4l|FufokNC4oLqRlKSCvL0h+C>H|}>Rqm#$;-#;*| zG+FfX-`0tdTgQ_U9aB01D%&OZdRsu{c30w+dYhEnKxvb5TTHv8e3nePJq#W4I?XNa z+4gbIagQ66aedBl&y{iQ56(oXx8V_j(uPM0rd@cH$h-<+=+IU9P&uH=h01LSv!&i9 z#N*B<2nskh1N?@-$0H4M`(d5xBNRm0E$ga)Q*`!jW$s}Z-pj-i!L&|qU<%aSuskcda4U{%1uf?=W$`8tvH^H!3Ug9I=1{pUBB|cKFmpUaU z@sZLSw*^X@oF2loOHO-aPP<^}fbnstnx!i~YwA!remdU?r5oezQm@n#`5?L%N}GE2 zVcMmh7iB%q!_Xn==b&;-dOwtINk1d?Hc7t(rA^W=W7;L@w`J0Az|dh44nbvG58YzE zV;}cj_qZR+xF5JV|HR(;r|!Wj07=Hoz|W3H5<`?yoxWA( zv_Ul&(=Mp)lqufmvQZnm0P9WCa=X%+T^ta(=K`4C-YhjLkE;Ap>jz19;n<< zE|+?nl-EINlk)wTc1ihRnerAGI^?xk#SeYCGr4g_Z6=0tEBtOUEB|c&Y`ej&XI?@My{2SYg{6aa&|w$)qTBmU+3a}Jai6) zjdhAFzIP+tPj+$N;OgT>>0_FUkL#dwNO7vG`b*$T~31=WJ>ot$Gy)j?ne8# zo805>l5rn{p~H$i3YEhtb_Z0BD4vAU2E}enyP()FQ~IZK+^5{)9rmRDcmvZeC_a!Wz2_YF9k;k2+Q%cc7g7xzWbITTjl968T5@(>w$piATd&h9H*-CrTy z4|j1t3_6FxhB`&&Tc>L2euRtrD_wm|kUqw`_^5@>A;qg)-8V}2lU&@_x%#+X`k3mR z#uO(PUhmaVIrO$SZW@#}SD+g(?Q-&(EmOM5IqnR%xO42|&UKHwSjJrlLx&Yv0F}dG zej8MdD3(BJgJLPBT~Mr&Dc$27cez{K)%J1MxX0Zr<8FYV1B&%f*`lC}@q_kpx46gM zA>(dybH3Bw`J?X6_etlwVdzj4UJBt{)Km6xpLUOXP{!Tw=KOhk=P$TBKf@on!#K@v zX(h{b>lEl53T_LP?J9b`t)X&zWYkLPl}9s$cnm@fa3++|4IlZ+^0_kU1XwBkZ%Mi% zbPk!FBO}{CG&)P_n`MS8ZYLQ&>=HiY93Jofas}g)`exz1ah;)b0@G7w)(uupVA7#; zSj{d_IWS9us@Y>@v07kqk&N8WC31$d``)hZOQriF7xx9wITV)X963iuwr_?kskd2; zGANx^;}V(lAXquA#>LP%Ag`2>?K3Nv`evD7Nk+-=RW9MLfX;#0Wl%X}cBzbPpV{A~ zzFB78xN0b!nAORo$HB^p*%;^?G8-);+h9k@G$jIwl zBCmCJ53&zSA6r~}Y=+Ju`;E@-y>Z*1bjtoQ8F{Bm6{T?Ux zUhk7oxpnLlQs1mAym9-XbSnH6ne>aWa%z|tptJ1?ulJygY~Qa3q`p~ZVD`2Q{|4+F zxEykh{+hFQeAfrc=(_Qp=65lz6dL^l^iO3I$2-HDp>*SXlhoVPvj9q)dhWoqOFj3>dX~e`A?amMIVQanO1GpJOTA6f zE1|SWdKIQ!lHMqjUJpZuMOX)wZ9R0KyU9N8X7{*{$hceGoNu>xzQf)59_f4+3>}Jk z+%4{2`?&ku;~tQ4pK){koW1jd?#@4v&OfvoTAql#51m87??Gj|ieB$KP>IG<8jHTI z#6RcwMn?Y1CGr=}?mu&N|EqL=#KrxO&^Z+Ly>sO6TqDN?BX^O1x0Ra!#juqxiTwouv}?(Hz`a=4!@Q#!*r?&)rE&#{l&!98wB#`VL{VI7m9 zazK#;l_QE2C~Z)LG3|olZ!)Dc=eV8S;-=fj?dl%)A{n{EpK;?j{#~3^@q|1RVJogP?gA(3t{MxSH6sEe+Q8(^)`8xLTQs%8KzzGx>V*h6ow8chd||! z@*t?(P+lzcHYpE>(kA80Fzu4^Xqj>~3?1?sDdXCstde@0ylSDe$!iRzUGn+@dA0Di zi2E*hF5Yj`qQzk`#(i&$KhPN0qUDc5Zut|B?Yv&^r*J&5ZgTy|>VdUW`6a=|1xdUX zyT5O>QGCqc%Tv1+?U44Du*#b zXzP?UpuHzAmz7CN<4A-)1Y!fNKiS^7*8_BRy-1g-{HlD!f#ToR3Iq)0@Ytp zIAXO?e5e#WAx8>WSvO@%CnXq63PmoG6JXW+-W9(=I1UO?ypoyxC7>13!7|w8R*$P4 zU)xw+ub7Ho=vhi$8tZE(T&1YQ@9iOtiQz~Z?b)n%=-`>|1)82A=Klyjo2`JL6l{IOJPsHKNQeHKNSF)o__D(`&fQxUM`>ndjAb zs>an;HK?rN&g%`=cqUYhSKl`-y2TrpR^yqXtbsS~{2Bm2PtXHUFM0w1+MUp@1@h^Q zd{9q|3?rYuMn3(Fd@hiA^n?#jo2!dYka zt}X6+N%yRrMK8R1OO5Z+Ec)*u^7;<{VwL{c-46~QHF@ONE9yqnOl}xig}1jilSfuf zY-p^TP_2!xYQV8Le0;;zBZp7v)noX@)#IwG8mfm!47yAlHNw-uljuqEoOD*-Cf`Ee zOy6z3O@YS(TLaGrw*@{5Y!7S=z8^Re_&o4U@Qc9bp)Uh#LSF?w3jH_meCX@IYoTuf zi&DM~{2BT#Ff-+F;FsX{fj2`x1a^jg3~UPh9Jn<&E4VAPAoyNrO>l2$eQ;su!QiaW zm%;6!{|5Jm4hO#u%?!;CtqlDddLZ;r%GS`^p#z~kDKCd^NjVgHKjlB64JjXlUQPKb zv^3?X&@(B&hxC*iQ|?Wfld?EvZpz~+3sMfItVr3HvO4AIlr<^;PFb7saLUeHcp<=c4gZ& zZ69j;UE9NLe{B0x+a}+Qz8TFv$lkY*_R^KDO?Y^D9$9%hdyM23ndwoy&p7A~F+wXhMchL8O?_a)`e6RXm z^BwZN>3hfbAK&}F4}Bl`KJk6#JM5e3pXHzHzr}yMf1!Vgf0_So{{#LF{*8X!|Cs-A z{}cWv{k#2p{CoXR`QP$?=>N|Di~p$qPyhPBCalu7z#~|r9aypV10P_$KE_IY5%@Cj zRp7sYuLIu%z72dAI2`ys@I&B7tm4msqk%sHe+Fg*Z^FvV4$ckU61+8ddvHPU&fwDE zUBP9+<-rxfmBH1)HNpFW_XpPpHv~5a9}I2{J|Fxb_)+ka;Ag=vf?o#z8~i4CIQUC& zW@r}HZ$W5bXi4a<(A}XGp?k5KYeMU>o|{4sg|>#ag|>%whIWPahW2A^pAY>j^it^M z&}*SXp*OMG?}h#o`XKaC=#vmSEA&<9>(FLvv$5uL zQ*KGQHRX1!`Xa3V(v)Q>%dz_RrmVvHuff`{OIe??A!Sp_gDDT84<1R`fnLzjCA-iM zd(b6Mr#zFgAANB!<%N_NQ(jJa6&>?>%9|-~qfg#NkGzjg`54{vIlAU>%9ilWsdG~2 zrrwe|KlN7h&cf71sf$yWq~4XfEOmM6iqv~kSEjB`U4x!lm%2Xn0d&^p)CW^PN`1J~ zTbWv{%#qopvbg^|UwA-b{Nd?VYrD(>i+MJ!dyvf0oB{ zYUaqg@e{k$j@mc5rT5Q2J)Rbx%$n+|#xCjUx3};%88cVcjq5UglqU}70Ws5MRDJcx z#;dF8N(e#er~K*KJ3XUYpY*Qj-IPgec1=(3)vK4!*P~aT?mfDb?#k8#(d!vCt7hH@ z)qVcAt?hkpZYreA zov{dH*Xk~h=N4Rx)j!hCSP0V12lYkCv?S&qvI9_!I=FURb$#DJZr|aR^>tU(SB>}O zW2V7(-jqJQIt?$Y9a&%3P*>CF8&caaxoVtmVB_RbwROY0rFYF3o>Mn|{NxF>jn@tz zk~4fzUER2b;bjA{*|kTPZW&#=r+4k%efWsl3BwEP8XAZ8>BU#Fk=?qC8aFQBI}^!h zjn_`B9#uQega1Vb7s(gDd3txVOJejTGjautTq3LLM~)s|S$9o!ePzz@%F3Lg2@Q>v zxLd{Lv&%@2Hma_{qYbO|XqR}pd$fj8(JRl z|2Ca~{~!kA`TTF1m}@2Gni_d*e|rb?)FrhOM%7)@;47(ZY#81(eR$D?k>e(hs>WuQ z^e)}HrKe*YK6zw)ijj2_YHF|QGTL*R_pKLi|HoUE#YfwW`l)Z| z{I@=Be_L#huVK&Za(89#emR%5{v)pEyBD4C^y+KcS00~B)6?EnN1wjv`n>PHEdC_p z-4~B`Y(KtJOjVDs9zSy8wO2H7dM$?spSpK#u=1{cogWyo=I2T6|BTHkDyGkE?DO0u zqn^6)#{o0{xS(Le=5=j;Z9n$-d@8Q)opQ?jZhb4dKl)6EflnPMNNn#Peq1$=uNpV5 zZX{<_8(#kY$O}Hd^yiOX8+%Lq(yQCQKP>i+FRN-Coj0YizDiJ>-Q&>1cO`$mZpIfg zFIhTb>pgLv|E~3VQu_D5A}8~T^lo{1+2y5K1r?e7d-MkMIih1DX1iWim}^CBC$P2Vr`Y(dQ@g- zXBCtcWblXb3$bCqndxFVx66nSy*0@Q;-KJ zwG;3>uXa@bjEVKQdgGI9B)9gW8J;$pVV1Igx1zl4vi#Eg!pw=|?Q>hASa&V1$SNx> ztUz057}jyZ_uue;>d}F@QnfBC$}d1a7iTI5a+Li;ihYlY%Iw0t%8Hy!>j4wh`&*S= zx)qcaX601o=TiuIutf1Xb(30*`o&z%^ch=l^J_f z8M{QSpQh~6s}lW$zd6P(BOB|DoubZ?e^YkqU0PP2lUG(&Xzn!5*sGQ3#wU$V@2c$8 zqZ~_Ll#O$%s3)>ZRCe8!U3%sf6lLcYmJ~;JiBuHTD?QbHataG73JY>eBl|=OirS~Q zvQMwVBAlmkD`lMeNODmWGL)TqROICs78X?&WsaIKwZ~ zDaPIM3M%p|N-A?QCqx!L>Y&O~ta}ufmE>j>;bM(cBB#$Nt_6yH_rjvGlI-lVTqF}Q zk4mOYG4EEIS5Q`jeKH&Bj5?!|8K78quPiSp$SthMreqBBDCdI}^KQi@rCH^;x+52R z=a(whU2{rHa>|NJax&#zK-3BCGR3-ger`!2F3#DRbSqObvYrm4QTQivR}^W<HolJSh5yhcivF=uwRZ&!2QUq!M;BXIdpRz-DoIA@)%W(UI zpE%gB;r)tv*Rq_lEL@ffG9w3QR5A}J#@$Pc%ZqWa6=a$xo2dTSsF?RCF3+hfDapwu z^T=Tt)!UmD`>usJ{?Q@0qcIYX%4LgU+%31fI6toRoN!;S-$to|Z%q^(Q9C6igu1%BTr%!%md1W?T1|x2oWf8SF z)0Mr!1gFW0B3yK7_v2ignTn^3qU@5ag7P9XiFDK~lc?31rRVuxixm&$nfWMU10WfYfZ=TwvwlqimxWfHYI_bB^Q zpA_U46;qoblL%7hbA8lFcBSGgqq3qbr@S&BCj`aSUuCmK@jzViii#@pk6_<{E z#--x{#Z_r$aXyZq;sW%n>8e>WZG?x%4G$X?50#mf`K6U5czDAOoR`QUo6U-^(#%SH zdMGN($I(pLM4bIqK3fzYXqjwuKOQsCIr2CcX{+KWBd0j00G|R-Sj11WJfaq9o3eXl zW=Tp}fX}jX8G_#;Qt1vI8*eFS?ce7-o7HOyAp)xZst01>58;_c}m}o>58+`%!=~D!om{Vdl8t3ufNLYam5AQvEWHoP6-ai>Pg4BNV^nA8F`htSy_c8 zeD)T8n&lC-NV}EYD>L)+iVF+N@YIL%IL;$!ui~mSGbgtozr3&l2PKtsY>V`i;-NCL zv@9p5v>@Uk0``~}>7RE&-HI#91>sQC;(_;)8B*ONxt2i};jzoU3#| zag>33+dNzaa41ZuKDJdlsO(;uS%7ErMWtDMJ&K?`W-Ko#uCPiaCB^sv%2&pStG|Ns zqT-=4v#78HKPSP%0WKy2_L$RoS#gF{DlRO}Dxq6{A`@};R|&nQ_{hlrf9$;pd|gG^ z2Yhmpwt+%fD`k_i6ezTm?kOVVuE|aAM)#B@+@@(8Xws0Rv?xnhL_|P9P()Br*_2&W za6v%i1!NHrL_k1xUI9@Q#f|U(Kj(SQojW-vH+l7Ye}3QZ%`a!>&OFOJ^UTaM>zPw* zNhg|HFeY3#fO)cXOVSHjmH#P&a9&euHiw4n8Qb!F+*qp8H>l_5ip{x}blmG@ zsTdH4r}?5mwIH9zdPYmi8?9GU=Sv3Ryyk4CIg5eY8kT}2WGV9%10P*)6IKYatx6K~ z$FmjdDf*k=%nQs_0*~WNFDwin4g7m5>^S=%1`MG>^HWx4CHN{9} zzGYA?$Y%3R*nmNycOF+wneP~c^D=3y-?ijWsXfAQb-rs*WE=CDra}r`lcqI%-TZ?= zJ0FWXSfMQjV(JEqrOrPZG}*>97xc5uL3-8H`MyCtzcta4idWEvSIxf|L<@59=0vj4 ziZbZIajD^3`dFt(>18)w_u|yjV%*RF|u-wF{rYQ+2&$8j@3fnBCV^m zoR(!7XHd>>j-^s57$&6*FT2eQl3Zgl6U)X5F||hP?B>3OKgPa8#@OQx;)Z-vA(`ZM zgG#C@wPtZ!8bmo{FO@B3Tgxd9(W#Z@Rt9+k#BFIQHfy)C&M===s@oW37{Vvf;9EHf z_6*_hTHVedo!^{DCF7Zdw{C>$tqZ4CBb;cEuOrv!60tPWHGZ$VZmM{ zjnL|j22rlDCDqj0oGWPm;OV8Z=2%+Y*&uJo=kv)-lJi;7PPwXDTHVzkLsiWe^Jr9R z4~N(4ZU*W6Y&sstHb3gBXGtTpy1PM=Yivz76^q%Nx2VFBs8Uz=G>98o(0Rsk*g}`| zg1*Vh-xPx=hhbTw7%TY8I9`g?>gqlQc|$IrE3{@gOz`svkmfwWD>je&EC*dizGbJc?K2c-{?qN;w|2af@(BsZQfcWX)qWq zD8w@@nS2WhXWf9$Cm0s%E}1pDJ;)%()GmS3Jc+!}YyTA`iM2>_u)zwGhIFo26kDi` zVTdqRhjEC(0aLqHY6(7@Nj8L3LgBd0bP4Qw5lMr7sTBg+miW@wzlod~A5{0B^ zY)4s2NrTaXrer=BPhv9?25n@els3qVjq!Xsm2OE2{U}SR*gesZ0f{YD#G_ zIB+Se5O2Yu13xpW*r8K9t$$Xf$r{XHTnfcvGS1y0YDSq=6DV)+zy!P{*IdXop`<&H z8)YdK4Mq#nI3$qfNJrTW5yNUq3k_T9wm-CV=^0}9jn%?F?e7#HXTo9arD5m znbp>^tajaHaLP7j@~M_=lAS90rHIumOO#^`2I&8jsbaPThtz~aR8i>~$JYML;72ku z=r)*PT7g4cNvtzh@CsC;EUY2vdV>Yz$>&mqbecmpFGta(rR*$;jx*Th8q+X(u_TTS zRC22(Q@_Ck7N<3l&BXHDHE11_y1*oQ8;E71u_C0n}5#!H;B1 z&hJ-r&2VT{j!@1C1~bf8Fn`CMfZy#ZuOaeS#q~*p1?0gwsA4kXcT(jw!x0N~lEE$4 z*c?l?LOb4~5EQLtUrnS_3?}Hro0?jSP25C+Q6FV#ooaB(HYT&VET%}_Y-NOv>vV$w zw1Y8UD>e<4!zdfqrwnEovFBThxn$1U9e^~JA=Co5O6$`G3zk-)1;;YE%IfJx6+GhN z`i#LY*O)6b<2*P|dQ@<$R$QMom=qfm`9dxh$LS>6(@_@JxdtZ`S0dJ&#QvYbX^1FR z?9cFOyw#wao5v0yR@hNRNGCb7D&uVi!Gc6Qlfs}H zh3qAyb|JiaeAl3yS4g!KGAXtfpE6vHw;Lo2S_`=p&PHlt)ztWXgLYmvkxM0#9L#yi zMXK?K22n$zsesj^tUp#CUX6DebaR`r2#8GpG#gm%2sPei5G+V%6R~2NyICZtQXB6v zDCc43+LB5qC8?-JeXl{X07toFu^5*|y~L`i@jiogUMk;|EMWJ$OdDQq4;VxXT4UJ1 z&vV94!=sb0@H+A{gK%CU5l<#kDO6*RFg&S;4GJE5$iq28f>*DGO?DpS~+tLCDc}mPZ-qmakv8O#Z6*fJ>u{*pERfzBoeWB z3`dcDi!i)8e`yfT%V18FPi4H7^zw;k%N+m8pulD%PrAX1Yg)sr^I3y-KDO{FsTeNI zPs6kJYlDVU+9sUzZ4S~KQaLSkzF<(#Z_X7nndTO;%)_YjHwM)LoDyhGq*uvy*7;IKX!A{j z21{)zy!iz>C90;)-x}2Ov)R_xSTlF){1nS3(`pcJ8&nIDg=`XL9ZAx-46n`K8HDrj zsvxH8oZWha;p+UoK>>9pGT4q(Gh0oa?-{i7o11Y?CB>~|U(5(~{>h->%4M#Amq*0b zR&VQnHmK((;)PZmL`MhYrx>ZuzZz7z#tcrY#+tFl)6w0#s`4yjEGbH|hRXji7+{K? z!pJCxSp*q$RdNUh-O9;YQE_f5@BQW*i-kDq5?=8Gr*%=XScj2o4GtK#w*OBg!g zi;!jugBKPI@_4(ZC6^|vC}FH(+R9*ncaqJ3q z^bD-~grBLnY+wWjaxBG6G&mF*(>a`lha(*3MDVb7g(ew18d~xNz6OSZ?(6TA*9&wx z-kJ^VY|!DYgj5q=Y{H6UM_B+V9ceQb-To#W7FXk`0%irIn>8%mbd#=Sa@h+K{p4OspIcJ)5@#bV4ulD(LbB9fDwn>-9NUV^-;S}a?-mr9YO}Zw$ z!IFz(m`S?%!_qaFbQ~HLnsJn=d-bMHnI1&clY|WhB(6OO1L2F8V zut}IrXEJe&rF}x_Ts1|D@DP&_!?-LK5HlcL)sJ^2Jxdos*k}-9eA|TAw-Q)*BxP5> zMQV-4;s$9$Jd2lL@U}K7OBS6~OOpoOf^<5Kv#i+A?q1#BXIE1zlWCI>6W%NiqY0r^ zPc6dc3PLPyCE|ETynA)WYFku`u*D#3NER|UoQb`l?$ssSEK#9VD~nl^E|ZPpehr); z?q1!C+X#lE%Nuk!Sr#vHZV9@9mFw155?X>5O~QOSSIA*w+ap{n-AhFIFEj{oOdyxa zp%t@jtXf$b(8@}StnbfSrgU)yJq~;|H^qv%5PE%s(4t>jL7y!&wQL+6R~_cnaIaO=p(Yfwt^lTLWNioZ{Q9UKO+0bRM2DB81GO7**Db}QT^9d&^Kjb z*bxo#Z_-EPzo&vel}zAFeUN{XJ|h3U74+%WB+jq~`8Vk!^519BFKEUAs@A4d6V$h= zqe{OqU=m_CC5DwLTE?zwgvXnNFjV-K#t8ZpyO7 zpD^h1joFrT9-C3jV}Ebw>LJ~uHB>&)AZ|$Vcy|FWdcq*v>ah|%*`#YuW6XgyUGy7O zWF0igT5vQ!-;!Zx+ z29Jhfp(&F|; zF@6N$_YFeaJ(0w1C`pz^FveFpD~mrg=~}Sdhii^l8o?Mpg6>X}E*ZmxZ*g3<(>;JO zzTfsD=ig%;kV!+G$4er6T=2P^2~xBvied0_sn z>CdV{|4;>ezL;#yXIj}Uiu|*y&_7Z^pKMLzka>`Q6mqrv|Ga{}h_;INt~CFkua^JE zE9jfC_nn9b`3HTq{QshYKAX$&tzgYR=&R-bsS0`=Ucmc2*vIW2kU2%Q{6Aeuj~95o z%N&)wTK1o*AkVbs@G@tC>XYQFW&gPf`cxbvM!XkRrmvR$=PT%2Q@ERe+t_~kBPjkC zE9mix0p@hP%+iy81jYYS1$_YrP!l+2QKqk!|5qyLd1kbj4DvsM;(yJcUy#ohFgs|b zK`qZIBJ9Q+CLzv+WHYU}Ed%)u<`fZx|7{ZD+8(rb?5-olU``Q1_?AJ~P{2Wt7A%~A zFql&)on`yqG3fG**icMjs}FOEfr>eW5?gbMcMal(L@J+-WpP>t9e~a$l+H@@J%bJ> z*|WHRAc;d~(F^BRSN^_1k5{IW>3lwow}wd{HBz!RF+MOjEJ!uAU{wnT3xc&U+bmlB z$=?lX>@_#z#Z~Oak~}JTD+3=I3>KtuOvbxzTHS`3Hx4xAX4@9b<6A32nR#94lhU zmzf$^z0zhTvp8!IJkH>O?4?qe=wx8((e`8-oS3o=EckHykc@*n(A8HiBf_Z ze$2owHsWFuEZX7ZbpHmsYf5UeI(V`As6z}!IE<0a#n40HpbI(KN*=HlvZau2Y6b)QX2~c93o97lq8(h7*-``pxfd@ul@rBavB3a`ND{bH5=T|3 zgGePs}0pMXpJL}F&H%z@upQg#m2C1WtUzyDW=()4t5)Kc-spH&=c5xCt+WwF3^?x z7~x@6o%Izwn(}#``4b+&i36?35thBLf(I7ClWCkMqZ}JYEXP0vk0NgI@vd$1c#Kqz zjRp_gvXI9$PPuezo%y1Z%x<^oH^LN?s{!NkQ?f zd80Rs7aF`^7?T-XBhCTJ#?czaiw#C|uqBE+^D&CwSnASGBv_{{zi8mk&*yR}*pR%3 z-`9V<*gtD9^(BJ@2Q)EBNkdd7(S<|8;db{jgJw>u8GH1&AGL8)`NDTgtgjmQ7((Nf z6^z%4jhl|gdDT_D_9QdhPJgX}2hQpjnlb9~dGwEv$5jRo%o|$@c+)S7vo4!9_4lqD z2wer!Loe18;+jfMIN#WmYz50)`rzCEP<(qx+JUDgttyvo?6HjgHK*(D5 z_*NyimP|4g!&UM=x9aN`7PlJ=Zm>fwIQ)T^6`9G6B|V&9t$)3_f=4l%jpKY<<4S%N z#4q?EV>~^kXEpX)D;c%mra>%Ldz@s)ex#gkGdL9*aS#$$ZS%^0e0ijbNY=RJyA_OZ zgdmq|;pK<;p33ML-C;0-A&V!AIh=#Tt07cVwKt)yQP~eFd0{eFY{hudSJWtZ{m9^j z>rR`p=#Ft*g_^3y$tt}cS8&QSVQhix_&rsPlG8mEoSKU0TU%pLRR=DE^0e+P&BVFh zQDxZnQ-c$mh>|?uc!|_4avub&MrgjgwV^k5q7KYQm=j3VhiOm3@?)9y2&$ z2!ZRCabOW2=kRKK)ffM*6^AD(nH38-GM6@xsb#UAGZ9kZid2Ylc=yy1fbdwuEPKc4#j>3iL=?Z+qm`_ilYp77Q+ zkG;}%z~z^=-uA)0J?}5QYesRxg_E52c6`sYv`#)<+sm&HuWn!8JJ7Yhr{6iNc1-VDD{NXpEDWsuY-Jlp}!RL3wLzdk6*n} zl3nMVSu>`Nc$1Lex%`o@ah#<)+<$(fQ|Dedsb=<$H4{23X!_eLsm>$SukkVQ!5JVe zQyv1!O%;^A7UkzixvmaQJ;=+H8BpeS^5pb$SDE1XB>Va#ILB-rkbQAdO>(E22}he` zwxk!3aMn(665}0bM?a53IAv#~*WWW#G5bR?7m{%PzHs)~#&Py0;TS6C_egP0C83$- zz99WPNpn--{1T-5kaR3bx7@jA!dj11lk70G!$dD4<@jlE?!xZVUKNQBR#2AJL%NGe z_sVoQf5d0ACwg=>Ymwa9AVMBBy)xBIPD+$dsNqQ+sd*{K~0=2+P(<5b?6L)0=*l1U{`5^l;$#&1d**L|lH(TslGhwPp zW@?9omyz&}Je=a*jBJwp;a2y~Z|Zdnn|)O{RhC%@>0uC;>BOp%md zA>~1b!TAX&cd4K}Xg4;gAuT@vvagbC{o!ynL&Yh##GQ9TOEk&M^hkIG3IBNnoR=yH z_Xgq7CZSmrB)pP@=N<*;2dH%A6la3)pve@}E(ub7ja2vc!P#|wKn2CjoD4Y)DqGC2 zlWx%focBRjZuz9!c6YDk57A2t()$MKmY)Xa$&Z^2|9Q~uYSIOEv<*~Ok*eo(IApHcgARSI#X6sUQfy`KL_Xflu1ch z@2I2_&1$|`?RxrCd zuLRXiq)J{5=Q1?ea*%+eyV_^Za?W&X(H+A)ZiBkNJARz`LpZm>Fw{2!zs8yH zT_R`K+sIcD`5#1n8pvY>`EDY2_2)|c$CBVQw-#Y%a16L#O@eLigfkn~V>==EsX;Jr zPC!r(f@?@{6A9W3f+tCkSihlXAlq45h0oWo=quMk6FB!C={Wl~Qw_CLSq)WDLjl|g?**(D_m#TVMal6^^7_b6;dCA4INN%1 z)V%L;_(uc>OPX(yL-9U1FM`81J_qL;lwlcMXCYLvYDw?n^|5tbYkImndj_1d+}e6- zeFrGwdXhi#7@P?!QM*a*Iuq8AauM)Tn+7_2RMgDWt`d4CW5 zxacW3w{|$riIUQ!6%Ib%+}^vsf1uqn5}kdZ8skxY6?yu_ejwQP893Xma-4(KB2RU- zS59@Wo?7!35_Bj0=9@^it3O^yEM6GzEA@1&4f6LaQhk#2uRjat+n^ussnnUUm88ny zIY;$Dk{2P#r$}=Ab8wyl$>79VCR#h`pUZ2;wYgih)o|E8E6&wM}@ot?tFP zahI*Ap~h;z3a92qIAg!VUq7MqARP)>Q-_a;yJP9p!>Jn&r*;cETQhDuIuqu@bvioQ zadxj8A6EZFXONkj(a3*E$-3W#)4v8CmSkozX*}H(^&{+s-cG1uRiOW74Bwt6@!jvi zS-KX^vkohJ-L_k`)pWJhyx6t{<*s4+HAhpFPC8w5y6NyM_bxwP@A9McF26PJ@)Pnd zzYJf?&%3+)YP-vivAYw#3D*~C$*fFww=K>T6wI$E&WeA+IpkQ!If25|j`4+gw$0@? z+FgEi-JNhpnb({MUeA!%BQ-V7-~$o7YRC&_KH#-zZUnDq$tykvycVx>oB>a+I$y32 z+G^OCY9>4uuvrqt<~g$YWIfpY3~Y|^*wp%LYFE@uc&^N0UW6dOCWn*9gG0PKgv0A) z4l|>4{5)BlIsq*10E-htbS!%LW58_D%qV$YAhWt{!7SN>Ul(}wr*<5gg_kWCrRG&3 z7M-xI#nt z4$R!^>D)kP!fh6F@ULM08kxVdKbSuW<_kRLW0kpAr#ypMLzXoY?hLps&Mr!n)~&1H z^*VW7GabA>-tRcG{2ae1HPaK3($!F~nhE!iRsTR=S1&~B>c=V)4Cv~vO<1S#JG&Un z<{RX=D;7TnF964BVsn{gzf8mG#Ru%_md^yuj+~VoQsc?7`QMh;pfr&)-wwRkRs)Oj z1s3QvbSO^Egx4w5`rh`^s#Rtw9EoOf;}kGkcM#al+kn9UMM3}mPMN^eYzum_H!1rY z2ZP{5gWykPf_Ng(9`XO1_??FW|6btlC<*+H_-i@`@Qs>9-^~1?yLX zm;l9K3mq zr_xz}TVDIm<(rRdtKX_^lGjG2uWPG+psn_iw%VuKYMyP|=Eb&c9$eu!m?x;@pj)d6 zy0x01TdQFgR>v-^j#{murs|meT4u&6Y%%C%q&TKk!>CC6IfX>J0#OS2x zG||bysXdIpme4tz&XIIF>8z#GMTeigclkAYcLE0zzG^(JZ0O)hVo+!=Vl;LIHS@79 zXy%nq;MYyQX7-0RUTmAedb&LgP#wn{+j6L|4ZHUm_Sp68rd{^0wd@#c*sYCc&s4|G z#bu{ZOY2%oTR4W6#-*XCEjJ-H?K-x|8dlpnW@tRKQF9`NKbg)TovYw%b`5`BM~5G~ zcliZ-mtUrL`N4UY-;sCub@*C-@!jP&++BW^-Q|bYU4A&-oxoGa+P`=VSOt7-CN}gBtnbD+y3}vC;K`_NS5m3>e+i7{4mwT? zD_h-I&zw_9HB?d!^;1Lr)KEV)6FA(nYjGeQ>+t0qYmd1cOvjyyUsrAL>hK^3uzy=V zcnOTd-~})bgOf1I#4oQt4?aG2UEAQLH4n56o?i0^9drUPXcd*3^`(aOrKS%bBy;(x zcbA`Rclot-m)}fx`LT1C-z#_dv2mB*40rjtZi1|xoP)8 zI{etP%kMS2{MfR~Zzj9^+_B4V7Q6h|u*>fSyZqL#%P;o2*U{nUa$SDs*5!w4U4CTN z<)>m@e&p5VcUoP3U)ALoQeA%C)a5ryU4C8E5QQ>j?QLu#?#r7&Q^4`p|c&G ziFEk&Etg-@a`{axmtVMY`K>CKU!QXM6)ATLoqgy`rL#Ys>2zk$nMr3h9e#4i<>!Lj zgXr*cJ?8zx~Z&J8x=ycIJmQFXF^>mJ-(@$pu9ezT<<<AXqjw{+g7^E*1f zr}G}2KhfdkmhNBa@V-gc!JBw4Z+mpd(&0^u?iO@-&7r$39bPi%PNKsr|J;w#;k|qA zUUYafp37_QT;5sd@&Y=Sx5>G@8qVcCZ!Rxwa~tR!MCV{ShtO%H6Q`4;lcvKPzFgkc z!e(iOUN{T;3Mq^6C$l_jtIM(&4=t z?iF-+vxR##9o{qHUQg#nIycj~l@2diaKB6Eb~@ju^Fum!(z%PyJ#_A+a~~bPS?}`o zc=sVXkI?x!oyY0$y>Is^I#1JihR$b_5h?~J;Cr^DAb-5PAqx_pJw9Ybdv9lmnt@?Al9OFDcv&*j^7F5ilC`7)c!7t`FG z>F`A`moIL)e9_9CLWeIgxqRu!olb}E^tiL=@YNZYZ@jo4qr;a_+!!6c_u)3t;VT#} zU#f8VVuZ_=8{CC-_>zIk_XJ!X^>+`a!=v^tPszI_Iy{^1cG6ixhbOt+ZaO?y?e@{( z$!3>FlU*J!c0Wmn$9!EL)pbv$!vnJ}PrbT4uC#6JeuiVNQdVkT^@3D zd2G?;IYgI-3tgTLbg!aw4ILh;b9oldy@3wTpt-lw;n6Rb$F^J^xpIF%hliY8o=FxlD0U`@&RH`^?$S;4>J) zd$6sX@y?Q5M}PaKhIts9yo13M{>D3p4vDLGHe#&DMZ3hpg$WGB66;F+{h6dQxU(iS z285rQ)ZX6FH{frFcVdALOKqKf{ouV7()4%_R!3R77$V`CnAx)q?3g!a6R7{9l4YVm z_0F9KQM^JC5-!Io_qLM9MyK9sE9ZaKEF=GuAo4{Y>+S7m@5A)e89WO_o{)DP6cYKd z|PsF?;K^wKHrdiSIE9*MN{WMCfUyU=HUdgL?(oW#MQT1K07+k3CIbYC3R2ZzmwsEB?kicZ37#oi9yKEJ86X zZeP@vUmRQBo-d%@<#B-<2EUNet9Z4@^3Si53Y9A^GxGc*K&|C0G#FXl9H4uy^{EzS zm*IrBLH9Uj@4Ky_4vPy@$@Zqjn1XB7oCd-)hU+H8w72T;QBJ)~Tx-{NWBz93}uQNVN`Z zH(lq8vUpj>$iP{3b=$W&_-M7ijN6V?b$>0uFOqGxcbs!D)2Vlofm8?(X$H<$Y@IVbw8HgNLGF{MTeCFA_vBGaHOEPRkL37y`&E>P6LJlZvxhd6N%r04EsCpcdTPtG5 z4G}jX{s&$qg!MvWF{~Hn>&~-fC1*`7{}$Haj-bR73)5&TLAD=2k?&C!CcngxV-=WQ z*|?|}TbS_rghfTHK|;S?(_8`-e_}<4H&aH|SE-`6R7KxcZh;jI@F_IFspS-x{F=Tr;4(dFHIB|HQ|<6 z1AYM%zOY=CX2K{0RcRZjZ3%mV&b~fW%dctgFwn+>YNdhoj6F^}f?pd&x-e@b@%EVU z&e62$T;=fW`lUXnI&L$0xx)@oslT0V0Gp|Gh;#-UkhgceyuDQxuQ_8@_34mr?h5v5 zy}DlnLRta*jdym60@XE6WBcz}*V%(@N5B1l9@%(gGMdBHo^1d)FbzAPC0vcBQtwPF zSB315mavag_uvW#+5+vW4ZQ*R4dDDJIM+Kr2`V9S(6 zHE1aI4U}Do&fvvMU*-V%`0>i*vGWMemou8!x6*w{$sm( zSCs}z0B+|u(ecg?qJecQ*~hS>Vh2;`?O4C6v$$bpkRPrHU+d-P*0Rirtf`QDYR5a5 zd!r@{3p)BZKKp^D{H2KaU1mVsQXeh$o{GEmkhpqhHkQ}eOJj@#1LE7yBJ%8+ruER| z%rZjLVjE!w5E>18ZW_d5T^;hZy05b{$m_RJ+s?(ReZBL|gCxd-f#^YKo98}0#EdqO`3 z*p9Qi*D_zHQ9(1oA~4w9qITuAu;{v(I51`PqyC|*vKd64f9|!gE^Q5FQ#b)*8=hX+ z>(Jc#RkP>Ey9SEu`|;M+`W|nT;~mRbY@LTNhdLKQW)5{GKu%Wt-<4I=oH3^!2O_tP ztfoBQ3!3x&jG^IsMZu{`Vj&C|hvZ)2yCAsT8*{ECeo<@DZA0Sfoo{JzrVcYkbXmx= zqAbrWQ=As#bthGv0W*^)qv!AA7#O#N)=q9Zz>B_qDW7L(sSCogQsUbZhtIQzE z9_8-!THfpmxqM2Cd&6+Rx3ZYOwfFaTws&-Z=v7ta0|&$w=DZ$$;R4K|Q1YH8Tanl? z>|->wps%?`DRX5t%`|%v4wsi6%A92Ki`o}0WEZ?po9ETAWlIf0q#1ON6OrZ=R@v_L z{qyE-qRp75B{(@WzTVldtg`%)Au3x9Q5G4g%`;Nl)~VYG$40G|5FC^34O+u)(8&{M z4Ry~CZ8-h@@wEUq4cuQ4_ixLMQF@oxR<$Gk2l8~2XFZ?Ofy%AX2!sV<)d6~Cm#%4)hHn54%uiz8|(=U&sx5~L2Z zhp7c1EHN}|PQkVZY@aeQOt3x3I{+9z)6D1a?N%f6&yu=qz>&022PQs`dh%_*MYAe% zHip0P&NU%%^JSF+-5^lsD(bZG=(CI#lYZ8TvOpWL<{N7u#3@oE(hU*SVN0j3D;N@>W73T=o$NgfC4JHBBp*=owivTZbBgsV z*tcb6tAI~e8CKyMj23cUHadFyyD{3(JnZP_p>FfN91fa$)(4}&Gf<_UL`$o8vgK-M zT9ffmVFx=8@`Dcl1_G~|#D+%J{T}ZRL|B5LZPN}s?WOphWU{c(96a!7!0u&LFUcFT zsdW(MCU4l|jmiD2d(wO)N4s1)ep9HZ7}%yrrlHMndyo^{_T3 z%*Dp3cX#%zcLpSd zI3@rU)2=g|y6*j)jUCt?J~pU^=R?wGAX>fih#{G|R`on!50+tOn|Q{ldw|VK`&cd% zwfo~fzjN32btndZ-}btU+bb-MIpV$_)o)+T~sb+0b#v z-XNY@Hppdj9vEb-0Bsr4l?HFsloxZRKwZyy>RMK=mb1*!!$+LDzlQX)a(ceK%qj;~ zzxG(Q25Vhd`wUj?wt?6y%Zbc3m#lUN>@+cYOBY2Ly{&=tkWs7Ac!FA;2W)m(Ypm6k zbsEPioa2m|WSIR^LHk&_LR73!{06W;maU6fzI7_1joa*H~dT_tloL1ETt*pe~+o#IdZ`- zu(Dk4!$1pq*r-!pvo(Dhw&Enu4)uAf@hlPi)i@WAsO|g1HGS=FXyZRkM3_&T!YSV_DqL5-&O|~lOlC@tO8Z}Aj`?0d)tFOGC+OsZblAzCttFkzuP}0TsZ;mQ z%CV}qpe&0<9IJj0hG)EU<|N&)fh`^!qdDKZoGeyw?2+2uAbepuhbP{oV^{4gQbCJF zs|;G~c&e-1sPd|=VA$IPc6%W~E_ST!XkUw63dq7-;;-(vA!b9$yKFT$K>y8TYI1qG z%x0OkVF$q0sjl$JOG8&D0(3w{hONbieSomO%r}-W8FSEE494CEa@rYW{UbH?PII6X zEEEI~cGC}gz2MAw>;^gEuXlRPL`?HJ9l#VfS8|19itj^s;~sBHR|igSE)Vt&pt*;% zHNO!SUGH41yEFxiWh(Y%_A6@v#bg(I8bTbo7$ZPz&L!r}S?*0lQe4ye5bF1Y83UAe zjULIgbWUyEIJ|XZkH@4e%M&w}s7!LUGGMT^fq-GypcF+;%zCL-~Y`h(7WlrDB z4b0#;f+Yz{mi{Lfa>*X&L4u_#i-bPRb-8t z+lpb;M)YG>1lrA^2!pBoyC8bbF!g5l@fKE6(`ri#3(fi6(lK>g;9W*b0rCcBkpDTz z|Lb1-R>9 z{=myyTH#`c-#MJ-ZO$E0i_+g69AIiVg`QEiQo#aaV5Me&I}a7^btuMlNT9HqSN}#Q zafX+~F&Od>V%VNT5?sbwwz#~xE!_boH{2&uX2l85&vlh&j6ShLr7C zo5toeUOCt0h=Vb<{Jv-6Z~Pe8!nT6zV&!^mNZg~|Qc`)l_dp-H-dS9>N;5GO3l?^^ zgUm@T;K<~sL+#GNVUb_vRDi42=oB|_=0?lo<@@sykb0-LoN_DyqZcI2{p@9vjxV*Z zL&1Vq?^ur)hUCV`4hA$B*>M3d9T-r&-&8iB?9SJhdj{+sn8TY>0Bw{izbux)@H-ee z6ww-XDOVY;9|yIC>&M*{Obx=50K7q~Fn6nio#$!D*9}Wp4dyi*$d$4-EwSrDW3wwT ziySEOwI&QNsEI37tB-oU3kEfaMLj^0sj@arU2--V(^V(zgjQ^X9tK14Lr+vR#7xd? zh%V@kE3=Fx%tckM@g`T8f?ezjR`2X;T0ZW{29}Q;KNA#S5o4jC{5XiXM{JyT&c(Dn zk7KfPw+S?K{TN{1^L5=E^k`73*IltiHqK|0leWkT=IQF#a@iToJ_-E&y_r3l31-aD z_u*PVQ$pkGoz;N>HW(cbwSHO#4Tr@eW-1e%x+{1;M2W|0aG<1p^#FS(-E0NoA2j+nHuV{OT6EB=@(QLe(~h>KODX*M$9%?u#eTFpf) zB(~n!x2)&#&?!(fhfa@c$GNOUkvFz!+``*aN`= z!m`RO%wItr`~CM` zzpJVJ)2-V(&L6RFT{kmw^4MM;6LR|aHY%3u@Erp^eKX7JeZ2uBcQv_B#@#CK_>JHF zK0h8Mhwe8k-R}%^HP}L;J;XbH##%l`37jCERf8r25(mBKoxrMh5{6|=m@6!cfO(A? z9eiTb94CFx9q%mGg-=`>wMG{{clPxLg$J_&4E=&x0oNv8kh+^#STI@s4ku;ot!Qr| z*$8oKA?}YM?s%uQu^-b-J=DgN9r(k@rd$JpMgO1zaMAw?%}G3Frg}51=bZ{#T$#y7 z0BbJS8}mfOIB;w)gJzlA2p`4Fbf_f>HfYLoy4@iBJCiAWQ=lw#F@dtSM0U55ePq8@ zo}jhz9|!miw<5aUc{xz+@(SI)2Tl)oX2@Rv_>J12yFDAk4arP?X$+Uu8Jm(6>{eAx zda-$^=N@S0NF)2^;=wLR>%2*Q=Fy_@&KYsY+kZko-{(0+Gcgzz`PD_h+|;qYk0Yov z6!o%@SQnQ&u&J11;qa#74~DNpW8`4C)f)_tcYekhhCh5j?Q-f4iJsmV%XjPneuqNC zwv7xi{W3U5Mg2-xG&VEJ6*O2N2r4KS2sW6zmND;bb8ozJgO=64WezxgWlt!^qO_9b zA~DS;Clt2?<}+Eb(Q`Mf=iz0tSr|74W_Ksh?O8V3n5Rjifzjq9|ND(BTDD23_afE8 zcS2(8GQ()NYznF2cfDq@+MbJNc=9ipi*pWjqKq+`qPBoGck0%e6X*N}eR&%VQO+oE z_I#IT4Bs<{Zk!7QL${}q*b#=JOlz<+VApvq2{Se>Uu_}Z`VOrHfH4Uen`4iuo>nJ@m}{8Ru}WOT`G>3or5y}y;r%<4(0(|tqtY@TY%k{ z18e8omal3SE{+0Rssm4-;G0TtUPSzEoWSaGkGI8qvy$u>4LU^nUN4j9DZyvvVlHyO(D(R;05a&xIjdK8x`m@P&=G7d8)Zf<3E@m9)Hmyuft+GepS6kDLxko zNs2CIG5CC?NO*#kB_2?~xkgcPGKW?7u0E*xUPU;&8p7X|wJ+p-O89<6{JvI$5gi_* zbhiaI-q+L56mUZn;Fh2^aCiXWpHPzPBO#{*5MS&km83rk@Fy=nepQftmhnzsfGyd$ zTKQZrB@vX~FBNiaBm^IO@kXKLa=KrME?>e*!qp95D=#YGf+)bl-cCdR+OE}DLOv4-nLN|q1oE11r{e#`Umgf@|B3?s6b0BA*H-11 z$ZJZ`7X@gX4W0OjdoAib?R)l%0vzYF@(c01n!q1JmNLdWUy*zrU+RYH2i7qSl z6a}4M)=}psc7|_g3g<>beiST^`$FBQBx~k+_Rm^0zgEG2@NJN%^iOK!q~&GftLEo= z1)f!wp=%Y_$o^X)gOQMHq(b_#$+QTAevWbd4H)JfBXg-zKHg=@_zFJ{9laacrDZ;< zpi|0eN+tZ2g1+Tb`9ppG6`F??c9j+iZ%uLrPg2!iDDl1h*zKhWI7=a03IrtrqwKYW z(-n4TP!~mpA89&Q`!cL9Oa7RGZWD%b>cel2=P1h!k}qEq&nnT>*;-G&+=*&5FzJRilg3!d?K2-^}*9iDM`w!y==9r1hw&u)0O!m}%$&GBr3XDlA# zOvEz*&t`bW;MpEeJ)Z6GY&*_7;zP7XJoG8rK6oe^S?-I6B2qN6rFb91GZhb6P}F&N zC>nWCOo~7e55aRV9%f@dJj@c4pN)s2Ps1}G&kQ^iZ8Dx1p1tu@|dpjnDW*OaDibN=kO8`{9ZSJ-@M|AzdP}pSAyVo z=W+Obod0_b<9R^{;@1$L*I(gx594_Y7JhH&!EauM#dylWJF%SFZDqrMdigbraSrd@ z09tQ1(0JR3Q|nI0Pu@9#pHv3#PePU?gSYtjUiNtD5ppzLK)n74xt;F8cpDHD1JJs4 zR1ELv0KqyOeP$WoV-iQLh2<;;_FGm3_uc$`oV_v8ZH%BAD+ft}P zO2kW3d^9SZx2Hf@+)a%@&PVHCkKepZg@B$|5U3FSAUndA69?! zydPG7Z;?a&)0JPFkJl;wBm4N_>#$0|y!}YRSBig=_!o=6i|AlrFCYKUqMM9_TLgZs zgli?dOu{Q9{Cx?(E%e)F9a_^t_4kkaVfC@I=fTy_3S9j?&h*N7aPFCBdHI+l`cnS| z$-gUlQGcDptN*2>pD*=q7d@+ghsfU{`glOX0}|GBo=DZxdJg_b`~_2dzS{`i_IUA- z@JB`O{}6rrLgEh<|E~hSOz8h1@l(ZrMc~^C{0)i!g!prXZ->AeB>fL1%#CKs@rK~t zDs-LVPnP(+;7<|y#RA_-;QI>vQvx5{&*%Hc`~7lxbnF-}owbdF>{SOR93nEtiIy)id^Rl`~>lD6aNA6b9edq zxnA(El6ng$D`(>YA{Wt4$cMtKuCh~na&X@NMiQh*2 zOGF;^kCpIoBFACkpCaUit(k*N8>+dA7tKW$G;huu;k4^ag#{~XkfqzlpdkTEJjE|@O(Q223?xPak zTEdUxZd=xuqlC{rxLuav^CkR9t8WLl6Z>~ryB}7+J>`eh|Gl)!m&IQw>D5dAw!}TW zY+c{s}yCwaTaBDI7KcDpdE#kg^ZoBWlCh*@0e0j=`zr1a%N7pXpxbv4!<4AZ= z{e2~@{#*&GKSRRmzbba@Jh5}9i=E@e^W^&l37;+D8mXW4qEGezDRQd+^fEuc*Bb?1 z@0IX-tv>#8;dfD+A3jsypFi9WHwgc43;neMe^$azNcfY|e(<`dS3W86&y@H@X+QqF z!+igA3EwHxIvG5`JI!og(=63H};^w+Q}sBs`(nuYVgQotH(<9|)gA zgwH(!pCI9v1l}d#jgro6;rllUpDN+E1b;yA?-2M3fqz`&x>mxUmGnLkdAh~FR`mL) z@LMeWE*JRI0)I;A_Y(Lffqz@zj@b3H1%8jf{~_=eY4@+o`1f$J%WK8&7klt4k$bi9 z>lXX*qQnnMd~e>@bF$$3o5Wt6E%son*oUVi{EFCtiPBF0E_UD~32zWP@Fi)df0K4y z68OOj{dW9}gfl{atc1G+{)&dh{=F^!x5S?z`8i4QbLNrwEQ(tH+Bw zW+nY}?C?cWzVnxhoss_JikKJnY@H)xg3m1Xd2AG3M<4EoA8+&hTP6NU@$ZtnT_$C% z{zS2zCyQ?E@Me;%HVv-+wWHT;Xw)CFZ{nPWw$`^FBN!F!rzeacH)01@_ZKZ}2v=%i6}vP$Bw@pUrTC_0@i`TUuT!S)b*90u|9mJ$3@ihlTXN$*O5w@dyX z6MhSXpB?^4sR*-_I|0i*9rZ-;{QbSwWH`OCi;qtzBWzu%k$a2eE%2;KP2Jb$QbqQXZ$hf zAEixi5}UA%$dwSAalhD%uL^vcz?Voq)Zb0o^q-mrJ=+A|8$-RkveLgtY~9<3J6!1< zRR6e@gI-wuyH`3~IUZDhJF%_fN`CxA@xLzo`h?%E!e`FWKHgT6|4zyO{vzkQ60iQV zvKI5I_-~2r&j{ZwgzseG`^$Ep|Dz)3d&~WNeqHd}1ixG4JV5lJ{>KGR{TEAq{?)%v z_^ZE{@KOKIqF41F6g|8reAVA1a;X1bBCq;i$U9u|9#kL4YP_)euS*~IJt_ZJMXobN z4__008;ia^u3zT+XG;8e5rXJoPV;@TJ*7Pv7dFA@=sdWe#^G2B(Sr+9ZAS8O!E)_WO)w4Hf<_!f%S?@0%jG z`gaLD${+VdmpdziH>CW0e@FaVWDK`f?7_=%->x9u>;G0sxIy@<|5eGyYUwY(wneQc zulk=A_|?n&_&Ji#=Nf%|JvZpfv6t}ubBmwuQt2Nb61#W1*u5)dY;>={UlaIvnIrEY zW67Tj{-u&1^?xSxI}85#Vjs>Bf9XDc`UeXi^`94h>c1pC%c;M&$gh60z}4SJ;A=!L>VID3QGbrKTlM>-pI2Y`d``+~hK${QCHa0?{LO@q z?Jtmc+y5^qU-d5(Ip<2hrT#x#q<@z7b(HjfKbQVb;ZMk%-}c{=F}v;8N^xn07?N_s1;u*T1jbWRk!6H5nsc4>jcpD*zria#iP z-YfX|y{F0dYXyIXz#kC!MFPi5FW$KBdVy~)UDpG`9EcBCKJO6>pi7N5_@1yB8g;BPPZI|%+~ zwZF^{#@X+@75Dw?@`DQ*R{u|NKdgRS?1K8;!e9LsU9%DYc!8_mD*f$aGG4ew`i;4Q z_iO22Khfg%|F=x>^Yx{@eg8oT-zVYU3H}zM&rb21#h)tvY2yD_=&up_rzPAfd_EL^ z7s1~k{&MjT68}Q+HdZ4`cc zN_$->?fv&MZz~9VqQLhR__w9Ke<<^{>jZD5;BAofF39=$P=9}kzg6ToL+I3>DfH@J zEa|ELmdvAmBzk*G@_Vk}T_^?liRfa;Sfh$nkxVqgV9tyvU>eF(QxpKM=m^ zw@A9ziyS`^e~pay)jv||!z8I^>i0|iQ2#BdN9yk>bn4F$di8gdcB1}l87HgXCUEuf zrjj?_P+#SGJ?FQZ-Gu)qMXsZyKR-(BiSEU#uY2<9>mIiH>9L!6>Ag9|_fLMX-V6Wv zr@sH%Qr{nw_Wg@m{q>Z?^S-~;e!g7e&xw2eXsYPjiHBr-y>+V}{(Ro|4;B2~MgQ@V zpI`VM{U&L5I|yD%{J7wMR_WXQ^zSYB{&s1f&s4D+Y1vEsV6o5l57Ix(5Pj_~piD`>piD@5ns(zr^1DLe{T7FM54a@^!1&rG_Pb`u`>2?@7AzrJh_R^1d(O z+eMx;rT!i#a>Ygen+v}m3ct97AD8fv!hbK}ccSqBt%O$z|9;_LC;Vp!|L25$h2Y;L z^fiKikI-Kr;ZF)ZF01$I$ro1m`uYOy{igoDBH^z{c%tn2>@4H+8u8y1y=5goy&}h% zlKw_XccP^Cn!xW6_(KB!l)xuR{n%6d%LVU1;hz=y0f}EE^zTXixLV-XNc_>l_pee9 z|J>~7w@%>aOF#Fa#BU+--(}BAn^r} zYq7*1F7ba8{2L|yCW&7w_@B~tB>8_{^nZl3$1d>)q#dmg{6CA`|C-2&w`;v}|Cab~ zi(eA_S0sFlgx{C&nbMBVlXmoJX-5Z0JKA3A#Uz>M?JD!T#S;H_ogYj7rbs@vmwY}W zdY>Zrhl`#!iNB@L?JsoONx!(0&>t!Dx8De#lQVw3J|*Y-3o;H*^A0xRNJU)X(}wKHjH=-|Y(rPh6|U_a|PZZ@p}m0!-U@zg7yz*X3GXa>$_LAO)^5^n4ww30E9)Oqh2H}4 z7fCvgh(692`HqzML&e`D`gl|Dz9V*Y2f@Eo`k%vPo$Or+e^l~wo`ioPbgxLbS?I5p z@To#yE9Lr}(9f25Tn+4%!{t&AE2JFmmhj0E-csbgPU2Tf{KFDHTf+a4a=TOXbc4{{ zCh2S^dU`~HQqkX)qOY}r ze~#eK6g&E%*wryI-dG^9WebM)4ivK~AAD$-gwSGK~%kzp3m_ma8;~pFvcB7vE6nW9TK*;j*pCZ@) z$??BipYbx7%Lgx9c@K^OxO{LdzTy9gijt|A+g3 z|gz@+i;)l4y%@%Cl|L(A+ZS$oikFw@Ajg4!=mA8$j@&5^aR9^o# zWE+h&S6ub~r}B~he@d%#{|+9?>;F&wNc#cejRrSLN6N?cqwuT6+cMeVYV@Op+x!pw zH`LA1%J8q?>&nYWS6@allKNNV`9Io!-M0NF>9AMq1bvREvH9!b8mPd2+hHv1^Fm># zrlw|3JSjZQc-rwS!gCCstoRz&iSPiP4S0I-Y=(#QEAgzt^9elb@RacEk7qI-6W)Vx zH5|fAc!r~of-CRgXenP9oU~!_Dzgpi06uv!kF)S#yjC+!!n5JeG{UL_(olbWcu2cB z9_o<4sXyhVd`vpR$dhS>!O3GJIGT1fTwB&^_)MR?tKpe^tKkxkQSz|)9S&~hH44v^ zM|Bv5YvwTu$K)3#e>d_ofTtf1+mPyP7JkpgGY`)+JfwB-gte{dA#kmyl(B>-3`g5m z7)M7iOMI2s5oPm?y-RT-#F= zd_Cxh6P7OHOL$0Y=7(}>d>D*69S*K~kHR56b%bbP3H8*bKb(ud(Np1QSZHJ&_ZBZ$L%*mxzxsSM1Y4Yy?&367}) z%FJ{r4|&ly;S5v9Oqb-;H#Wr_?mVYEGlic z9RNI?bDDB;Y(rj5$HZZN!elXVOc}y>*y+&L+v%7*!r+v{#4*!X8$lhI@yt8Ryo855 zO<0&rCS3DPd%_w#vq3erY?R;5IMS4|Q(yvT@bchvAy~ zxB0M+^oUH%H|GjA4s}AA$%pvNgRL{dNf!nujJ(zE+4OdqF&)Zbra>I)pJf^bW4cU7 zZ4C8L4Uh7U6wl_xddT!B7xlxu9f-$lqc(h|0pAn9V|W(hDd5TB$>2%g;aWF+#uX*J z2>voWF+3Va{MmSB;n8&W#P1lMf0Zv~orlNdOP-XA@-4)Z!o#>F63)Xf;c37#S~`~b z|AdZp!la`t)K3ym3=id_oRoPf9?DH!#_%vqm?d2|6k#yvYR|cs&l2G&7f^y{bb+3Fl|FW9>%f0mgI?|;n-$0G;BvB<*&HJABils z{A}MPc}6OKH5!$P`l*I%>Xf!)q%^A2kQSKgh$gOFV+z=PRp4v)(O@F#i4FXc$D78)pCf!i>hnG@zgpNhGX&@4o~x^PN4bwK&~+vZWTRo4o;b> z;ZRRec+9UUla{@mrs}W+e3pF}oP1bEX)jFO@;6~>2TJ%&yTZqeCtp6~QNlyHZ5-mO zZ3%;G9gU(lb){oLmCJ;&J({wSpUP~*)Fu&b!%Ut!&M^5hzr-OA(z9;cJcvX6j}(Xe z!uYTp$b=L=}kKRW?UFd%OVWM^h`c`BD@$+0?%-3O4N~-7j>e# zE8({ZGux2DqTp;B)o`>8Rl`$#F>fq`(b5s0bR&_8X^j+bI9x3!wma&`)RV%fXWCU8 zP8!y0lSXmvc*;t#~W%IPzy**ZgRGG1IqUOp|cx-iB%0 z3yWu7?Rc#Nj4$C~nVK@1aKgfHC=c6J6kN+C3a<2Fyp=W#X6nI|nYy8F>1&%a;bvR3 z<4L17hqN}_OjG-xFg)@p;i3M*;4C}Z8v5i(-DsWFIzT!*j2UTipdQeTuSj6drY`&biZ<~Iyp5`5B7ep4UBXM3ScYdqcjQXVf zq*q$yO5h)1}MQ$n2PpLNBgxASkqNyqx6WvVjSbQ-Vn zFwa`X#ATRuA`DNsA{dY&Nwsgwk(8EPWqHf z`*;(NJea;2r)itz$KN(i32|C}VQ^EQQE*Lza)#lU`lP=n7)ad~W<3sr>lmJL6PNs$ZdiIMPZ&&PA-xS}ep$a&4>p`MtYfU} zVf1Dm!r-K{d9rUHE@7nSW9prGA*+{w znFjS>(=biKSYPRz{Fo-|GUII+jmW*7yaHdnjqxDklx!Nk?s4i?A z+iu!$m4j)JhYcq^;}x!H*?5#$ZCV%~O(%+;aOOwbw$0znM;J_Hq?|U~lr0R-IF={V z4uhMrg~6FN^JS;YIPwgGG2X`4`lEET#mqPBFm+?ri!j`g;*lrQ7zxjj;;Ec$*CXLe zSx1Vi@{SarG7pDKy|T<$=Cm)=E7K_9VZ634?O)6=@k|`n2ZouS;b5AENvn08=@8C( zX2P|MwNJL;q+wp|c(spqJj;bo7!74m`87{=z6sYhV#>+inx+|V%Flj?WfBFaTwyrM zn{bnsd7vyz*M@0XFi#vCn{X7)RZx?Pq;6(nQG>ZK&U zmamD+K8f|6_&QfmJZ;Zv6HFbOJhYvfaIIV98wFQ6!{Ay6H6P4Bbxpmge2T-g_?vu~ z2mWSz7%49KvdnB6=AY?D#WTIIG)$Q(w~3>+l)9qa#AUgz#8bkf_Eqype9AEzeDWL( z?~&q?ugX!vZ?#SOoAoG4Zp9&u{nZ=|>;U*>hBd`F7Qdcrc(HWnr?WnjBt8w`Up&%?o$o<401acL*2@f#^V z@mPn+kNJp_u^JBfP#@GC?L!owYB(y7-3A$s;;C(rv|6X5@Kw%{;A)#12`+I|j*`eq zd86bY@6q6^+#}`9bVq_qzF~b{l&(jLtMalRVLqeyQO@CTR6gRdt+DS2xO zN4RM}s^Mw6Y#(fYVLX{O^H{>O5)Z>+cv|Mw@JL?`hrC9D!@O!9*uH5y!enEbd`ue? zg{R|`YPghfG`J&8-^>%+dz74vXWgP4Q8=oP;qWvc)%a;T)p(ipk9`uyL}BugpWxp-mwl%0XT>oU%mK!4hD~H>}^4 z(YiStzUp-(xTXwIvYP2e;iz38oH}9J)o|5@RKsO{ST@>LqWH3WSTBcz6K3`k!{Jl! zgfrbJo|KLGV7rgP(efi)%bRpj_zD{duJSJZKh(Vkco$Xn|DOOV9lNBNd=mM%L9UCS zs9+(0Q51|ySwt+M2}%b6%W4D*>biDC7kfjo7j#rCSk~TGUE8|$vaY@Bm;d{H?wq-I zCX)!@nqi%?ucfwJQ~F?>WWc$ai<#F( zQ#Kr@HNrU6Z(5A4v12~;q5DxXzU1|r?DwzVdidczhBi&vwZw+;Yh1ejHRUhud88>@ z>iybn$}af~(Ucw6fosOPXv#*{g8gL0`~BK%^}24(R_l;Hlm7fQ^I7T|>t0Hku{UQ^ zh5nKF492Iqf1kmiaDs0BbIzvvnIFe6WV|wfWKc^j_`fm7K3B8-Knu8=nvTugym5U~P6}-BMdWMn6YCHu`FbozB}5TfIJ6 zSG><>8Ot#o+tT341Z)8b)W zwI-gH+G{*b+55G|eTjPl$LO`2>}MZ!wB_EEwC5UgEp)$CKinIWI@*#meI@%i5B(?g z{`JrCx-aqfS$^EUo$g0zHuOP#JwE>a)SNBjZHawLY&bvT=KAP)+T3cxTxgqSQxCo7 z(3FkNq4TBL`E&7_^11qRB>T9=NgZoi@Bhg@z5mcZney2-Y2())V`sda$B)Uk;e1Wm z>3kf|xyX>Q`Mz{N@O7*uUeo;h2I`f4b2j>%?%U}6ta-*rpZ?D>dab0{F=k#5zCXP- z{Oi&0_qlLR+LJGHBuC#iEyw0;v~HTSp?`8{&W3$yHjI^VGG4uwlYHo3>n52CW%?%P zKKN)XP1)%lq3fn|aqfD2^txJ`AI`Tn8@-0tHkY#TW7gX6*(Ck&8sM0w?qO;6%rmP! z=ko7)Y5vpVVSbD?%|0!jmfCAPP1&n&y`Gepzvg7Ye)U10+OKQCYm$2bKh){G)Ys#~ z@o8h2ukIn_wl;g6L-(qd&f||`9xWZm_;gL0ijVb2MyzE&PhPKS`s7}e-2apl=dH(w zetf@8jn{oq$EWRy+ULhi7QTP>rRn@!()v}Wtv{FQnwlrAUu&u!@o>%5pW5o)p?ccu zUYTZ})<^cV)w!6vKQ_slKK%QJ&YiSlo@sWRCpm}alhjkD4_>3mJ{`ll_T$y-k^Oo< zppP^g#-i6BuP5Jzd2+qAHvK;3%sG6$#>BD7K8?%wsrP%|N17eyBTwHhxo*tE?{8{7 zl6E?u&&&6tIW;xTU!$ZA<7SQW@1cF4)N|d^^z@O`Yu#!sXw7l2=7;{6hvuyPWX&2# z>(jiO>my^vNgHyY%vkEf4`bE2)Sr&g{kb(`bRN#t+Id_5!X>3{xEgh5O(9&@}ht`Z?e7cXd zBqyH(W94UU?C4iHv~*08Lrcf`99lC*Ika?)&w;!-t~DH5I);8}tJg(K$N3yuGe$YA zZ4B?PjE#F`Jw9ps0QGv!r1kTfWq(>9{qj4)rusQI?{CfZ``psz@Y!mq&XY*F%G?d`Qvr}uSdUfVjRAW-k%s7?@juQvfp);j_@6rINlF6ZcHUlI+uY>O-5fe(L$CBF(FbGnbsS4QIq;c*V|kvmsfSMQIZfFlYoIAVoRcim`u#O)s-JqUIrB}k z@z;!N!+YY|>~w9@>=;u$K3t1rKbdeZVNOYAjDvCVXHCDasTxk&aV+PgZ_d*vl=bI9 zUC-uhd>@Qq+qL*ev!M^}9rcN^dhM}pltI!)pGW9}_e9!pj(U6;x8}nBru598%s7uf zM)O}=e{x(hCax3t`o7gh=V0tHeRHi@Q`GtKsg2Ij8avuHoU^%p@=ELH+>DF+QB(c&-CRF?H`U+N8goDQ z8Kl|KZ_REprpX^J< z(Nw=5LsK@4gX_(?c%HP=I#i})&KgYG`7xDg(JxuCmXqWBHPJd`turrD!>V3vsJNop;X}^w7vtbVOOWWjl9oJO9uASO( zP4t=Dk3;*D{(XMFJ@v}Y*Xw-j_va!<-;Vvt*Vi+D?z_5X{?7wR9c9|nx7z9aT6^3F zm~Ya~k6*`D$%y^*#eJE6lQ!z3B{uYz=Eu*0^Cjoey!kzbKfgbY4E@|$ z`z^8MnzY8&_vx>xGSygV$A0F+b}M`e@X>zFr8yhl$J)jx`~9(;!?a-jq>b+**_Vu8 z`?;U$8j{I2`1HajdEOg3@<`hE@$CI`wXZ^d4L(D{&rq}@@L~ON{aIg}pL+-M-UFW+ zeEQ-;f1Fc&jKp~zKEv^$pTYR>-`5Pohx!_PI1hE4V-!AvLYelz*JllUXday7f8ld) z_@Q668vFmk@9*_Vet*J;e)hrVf0geT_~Kga_doR65`VgGWXrl^t6u7st`}Onf*WYd2ZzEt!*ZaC}R~?gl$vKU)9%e=&0ow$$;QtXONi<3l~K zC9ZEW_qF+Aeb9z^HRq=W{Y^3S+52{^jbuE2e{v0{!Cu$Gw@dnA&KfhBa@^do<@g$W zG}e}mZEj3e=#z}dJ?p;J4`a8*C+l8VgRz>IUdO-JXH)xDYy7f?()O6v_!tZyTEklR zzt^W;C(4a})Ap^_#F^$Zxo;)?t?e3ApJ~@~Ykf6!JtzH;No(qv_Wr$XD&(Y3otybE zXRaydAa|bg!}D5v{Oh2(ajmiS=iuJb(m8zF2^cpAA3le3&*wRxp_ps0CeC?1>$pic z*XQGwjH`lu4L+?|3-U@n6Y+VEG5#<2mf!2MslDa*`mI5pel2qSTH}-a()O0t_|R*X zv2agrYH#_yK9hS((jVvEA0K7SxHPuGINt#ut%>HYGurZ_*Jn$|@%r>_YasvLTK4_5 zG-lR-Kd!ZL&^~!@{XPD4J(6|$dwep+tp2#RExEsHe4MK_>o^AX$y!xkRp@K2zvg^3 zR};xPV9wmf=i|e@na{{%F%KW=d9CmnF&V3Jra#*8y5P0PmiM-O!*l*zN*l6jjSoJ< zat!@7=cB1LNZZ4vro^B%%@{dG^PYfn{TW^NhZ^Y8?59CL7ax7jZ|yjapNLOO#&Hhv zW}M7D`SVgsd~hy~U)xx&J8PmIACBRCTnptv7R~LgYS&ynvex+FI5KS8RO5XtXeZ?+8FMC z+#9%7+}C&wQ0Bf#S@%2L4_ULUVLpGVjy`D1K3+5I=l;gAoU;ZW+Hj28RpFemQzkpk zTZfP8bS!1|*Wg26{&?!SpEF+i=cgs(Xva9YM{uv1fDga>(A@R9OtYg-`)hDcKm0HT z-{0EoronzLKDwv2)Slxe;^W)%oH49z@ASvigkv;z`egjcJ<}h<^+zxeBz(Bm zy00l4UB{-@b}+`!M(vwg%cNZm#xQ1$n=wqoC&{uVw4t3pkFVD?)A4MX8*}#U{PE0{ zH8>IK?&dKX686W$(pCt7QJiYpu03H4Kei?I`o^vH_Rc0Ua z=cgVYvgC(;$&lxq)7No~|2w*5-;8GZ86Ua$KI=mr^&HE&$$>FyOODEgW9#vm73w&K z{VMx$YaYp%eSI=s?ek+TSg+vfn+gjG+P0fB=}-vQiqNJWr`K8ign4rytPo)x2-6_l zXsvj9vz)e_#u2xM=NxdmoVS}M_IFyLS4D61+$F-g9XrgJISXQ7#a}Qyp0nr~ zi^}THm-SrPlbz3AW%}W{%IYhr^JQhPV`gJKIjT&bzN|izI$u`y>VrPXQDyq{W%ZfV zCFQvoNA~JR$B}(f*U!@_H=h~Lm3?xoFYCGbV4l7om6;Q5Ro2*&I$u`yI%ak_US;~^ zxytG@sY}Y_M0Uw>WS7*DT~bGOs?!)XXVoh^mHpUgOIiDr9b-~I5#ocpr+O6q)B z<5C~9!}(OEPtLEh`b_GQ^4xGtava$ub!3;+_49O$QTrL6o+~?*H8x+?b7jZ*eRe7{ zPjXRNeI<3itn73QVC>0hXHu7x=VBb=RzEt9a#BZjs$)EQ&RFzZIjQXX(;Cx0 zVp*qF1*^y$m$GpS3;%1Qm`IC4trn4jtxkDfCY zJy%XD&qp8U@MS$$PTQm3=cF=oA_JAxS5oK8%1OsCHs-7{efqNcOzM)da#BA!j+~M@ za#9`R(R0S4=gLWC_2Wy+XO-#Gm(^!dmz0&0 z`q6RZl+=-v>KKonGZsB(9D1(4d|A(x(T=e9Ye{ALVg4$sucXeGm648NT+CNx`t)V> znbaj^Wu$&|92q5bWTZOAqvwo8&l!iFt1n;HbJkovKIB6?j$~(AG_ML*`lybn})sG@;HXa4S6<-X9Yaln`hhOBX*~V?qfNkrqO?r9G{nC zaT{tT%JC*SipPekmHkb+*m9RlH+nYel5oVoOwH1pDQE3kt2Q@gXSzb zz9GjRVm(uifgIa#fN#f}P zIbwBTu~?4J$Z<0nT`$KKa{Nw?yU^c`v|cJBe~@FXj5$w^|B_?1SkIN?Dmkvpk$ZFG zjWVXQ*c~9p>*e^Z9Cs1xC31XGjwKv9fg@MT$W!I`i5zi_L4UFwUyx&ojF}|Io8|bU z9Bb%hXId|lk-x}sPZ@Ke9N&|p5$gqVd`ONRIdVUayj8}mFLwCa51O0g_@f*LiS=LP z_=+6MIr322Jtia1lH-?h+*QW>RgSO8u~NoNljBM`u94#&^ioSNSIfwDVm(5RSIF@{ za_lG84RU-^jvI000UUXcj4TqnDRR6^j)h{kmmJTN=$;d6m8dpCw zkIJ!|*zGUJE9LmP9Q$$Pv9x%O^4XI0J(6h$IUm6DL)dq|*uEv&cBIfS zSk7mO_4U&Gm1w%NSNxwN^1Wj5tytuFz86PdD}B#NAHEBOX11K4Cw6a&rmf5~M$S)^ z-Uo2|n{zY2FYPjZ+PsP_+VrZ}Voh7#6z7SygJ`X0zG%8aV|>GfqV8zb*7B&xax35R zn8*@pYk91wx{N})Z*;a20d+Tvt}E6z7QwBe?r7E4>+PXeSjHl_GxTcp*7h!E8;c-twowH4 zimoeGITpbxQFpXz>-B-qD=cFXJQRAhdTaZzvyDaYsI!eC_`B%3Vy$BlJR$0iR&BjL z6?%nbEP`i3uU2nupL4dc2wrfuQ3NlGju$R|3xZ0(!n`7?^{fi=YvC|4;pEW0F1q&C z#z66=Z^T)ld)qhK3W|3`!L^MhdskHJSrts)5B-QqIN67xAFG4W$G%ZG*{8k{C;N{m zxQx+c{}t7GRt1wULqB2?PWE-^$Le78t#1@g_PuY!$$k_CS1g+BXHl(ZRWSKA^dlzW zWd9fXu{szP+`?_RlN}UJ)<$&gLmiCP35{eyrdihOg+^8fqYk3zY*%PnIA14Gaz96y z)3|P3VrJot-C}0UZv)YEvda`sxsmAFhdLN-68e&L(kV9!eT7Px6~)ZLDNABzoU%+b zo$O+TQzST) z6b85F*`Bq;LFHUgcH^?g;y6O|+yJPzo)?6ksf%FH$&sPwu)|s(?ODg-__Jpn#c`Y{ zyK(VjaU3st?g}oB#i3{FVsV@pdJa2m94C9$u{cigtfM$i6Jpa^E~S)j-{gH&OI%>OW>Jm}$Mm}v0 z_xj5`6V3?L6`l#VqpL*bL$^+IjcC>t4GfltK4=h5bA9MTR4}>0GYO};$ur?Jw}{N= zYn|pc(X1;P7~B#1pg}mz%Fu_XU~;!-5>9iEXToXj6Pb_FI?er}SywbLcrf%qgK(PF zp$}2Pf&rtRcQ~nwH5jmXfjnI$P!OvU1Q8?MZd?QZwZ&An=tdqSbDn3Km z$vz1Eh#XG#QRv6&;O7(HD4gsw--wfaE(+Ogb+Ru+#b+ox*;k<-k;BQp3H?|d{Cwvd zg_Hf@8*#FqMbUY}^jQU&eFk9JnL?vWGK#+f!eK|y1S@5 zOqerw5`MJi5A-GB@HsPPQWFl}JRCk}`po(GSya_I9X^4V4~K6dnsug+ujgMwZE5?b zPaZ#~x9zWXnr*CRE2rsWHO6WBTFoDwW?QS-#%Z>*n!Zlc&uX@Fn(eJ-2h}W`6vo?M zG##f;o-=R45!PrYPlbz>S?!{#iE}4}0|$z#)AY#`=T4m)>IR9f19bJFW{3`)J7-QG z>#NpNh3V~~stJ>I;GXKLetPI?m}+KCMTs%0y>-~U@zZ8n)jm!&1tmnQ{Y2FjL5;7U z#}w_Kqm68==HHf$ZmjMD^_a%$zEF?#)nsLTk87-^?}Hkv>HCnzYWg0p>Z!4~CpK2o z_vFTE`kvBQP2Y$4Y8Usk#%lVW(O6C2vl^@Edyc44Q4=RG7)McXXX4T#fcco|Usjm@rhw1aCE3)fE(@`|x1$KiP$#y|RH>r`` z2&lS6RGp^J3pWDlZqtFX5m0l74zwEqRVzIe$We8-s_aHU)jjG;HUetyQ;lo{)ZDKc zYy{TPgHD6hrp;>6AU(TTQ1ysYakHT6F;M}o-7I>Ca37DWw+Yox#?^g7_0w^6-%$Om zubx(+zMqe))%S~WwfcTJu2$c#sM>B8>if00T7ADBSF7(g<7)N&wy$<^zY|xh?|0*B z_5FTat-e1LHCDxL7F>dlRb@8|sykcjSrtr z+Dg|(wrfJXZyo9DMo;r5k9U{$dXc+@Gr602?m9@<1{jj;=@bo`k?iUcbxoRWZ-`NN z-K484{Kfce5RI5QClT~U(#3>kG)i_8>FbET=<%w%s5Y20a~>ZQ{ZvZq9MYqBLui{z z*T&MNTOPXBv|R^8D{Lp=PvbMGx?IzaomJAgi5=;AwL^Q@UOUw9m9c+tv+@Zua@=-Z zIPU3YjdiwTr*X3`nCknLp?`F<#(QOKAL$i9c-YlRSvuQE&xXupf#;N6J4jdCxf5_c zK+e0(JtC~2wk#LucM<*i(1(MyqbBMImsUH5NXG^kF(ENzcj;Mg+Jd=9&fuIwMQ%R} zSEE%76Gi8F6ZN-cjB;;P>aUWh+((uAyDcjBQ>Fgmhsu$n>;j*@)6tREcQ8h@o#svC z?jKgs0ix^1n7G?Z0nzV)s-HAFraxHqhsN#eRX<}=%zlFC*O&NW9h0Jtgr`HLqbs6} z*&inA4)dmspUU5RA;jsT=?2Z5N%CA9uIWrqFOR^Xeomxc5VN1>>3#bJqVGI!flu~G zRrOq!nIYa#y}l`nqAZ1@-(QKsF@!yT$6qPn>ZSeoVF(6Mx#e&FS&X z>hyPrzU%mjar2dtI%XY+dVTR8`%>{<*D*QPu}V6+(SJ<;K%|e`uMYJSPU=uT{^msmxmRX-kYNCWGBZ%26vseoo=#zJ@}63I?9Bh*}IV{vid+& z-8e}M;zy$I9L_>2nC26wgo9A|nJ5tt5>wshkuI|9c0fZz!T+EC)s;82>wZ~7T}8wH z71Z_ZGI_(&_HBEthd(34e_h9I*miX1f^Kzf&g@=SIJT~E{}BafM-=4G?p`~rZUagO z)D@1)pVz%+$>J+J7xX`;J5&dbY%{X3nx`A?KC)nB!y5e8@@Xd46;7bziJ0bsXqriN zg_H9a=`>3@&7m?4Pg^_98OWw#TRh^T*$NG(6B$$PS5#~EDKdK(nPEj{&!RBPhV5XM z?_0F$q?&mJ4ei%2C>BqpI8wL!}*y!UtAIFiSx5~etZRx ztrA8Jn_~2^-b)r$jlySG4L$ZBQN$4XVG>D-Vy2`9*`)ewQk0R@SR^&3$c!#BBcqH4 zqYK&EjEb1i7?)9Bgx|Sf6tfCO+k}`^Fw!Q(tis3-kjRI?nM6)8Q{?-?0}$*X0po-+ zBAlBt>5><(Olmm*tpc zqhI@S94Sf7!z7Xv#Y{;xzyoqwD7oN-GLmXQQpXmVV~WgCQAWq33)yPX;C7}ppPeVx=X}gg40@;$C;AH#qch9P|TFab?|`jFPHFfLK%51 zMIPrDnRAQG*-bnE{YNfppPfA%q8Nl$wjTp<5J1v9(b2LC}zszad$MH;u&c79;FOAdP=x2Iiz|lh1(zSeGJkhbe76W31sy2c-fa#; za0|}yfF`?KA52AOAJbV-1aerE@AX3w8DsDCPv@E z1Kj@?ja+|}!RR3{dZ5UxiU56Y?S8P$k7(k69t%5oM)PoyyFLT4|gGwO=I z;04F%d12HIT46*n6QfdiKn-nzMi@~Bqu0UcwIcIM1gOl~ZEl-#G;u($+1#Xt-tqud zz%u`40?=CykY7Wg58?Al3ZEQ(y_L?V5`Dp&j?WvyrwUr(LopMdZQucXs?i7^%HZ=c z_J`qMcKr4(WW@0oL9>8cPG{T577<~gqUlo}zB0xi|-EOw2MH2_~ zmCa3R=z9;)?y$^%mjLv=1LW6G=tKB?k-}#W`uaYd&rtLQ-#I?t3ZFfp6+RR*@figV z;IlUx;X@gG)_~7%Mdp`?&uDA+C) z9jy*RYdW+-i()2P3*iB@W}^{WltF7_(Au!rtRDe8(%Kzmo1@Xhfo%w2T3?%az>a}s ze$(RkO>Q#>EC>fmeXVb)x189Y>3y?wV#lH{*whi*M2H;+tq`M_iP&lI0AeSi5n_}< ztPI3TB3ys5MyK26uV~`9O1%22@Nk_0%Y1nPSB1mn*H`GH<+RSE^NMs@XQ3}BceFMa zT4zHmv?ykxbtyc6)>1S=i!x|cgVvVCrbh(qGHZ9aZLUBQ2ezeGU%fnFSHd#CRdM_V z*vkP6!hup>Jz85|SJ8W~bYfSdFWAZv>nX&pfmVo7%tY)KcmT2M(FifhAl3)OdPlf! zwMMtu=5{o3T)n;e+Rnpu2Q2g3CU9-%aQXEW`e=E5-AU)$rPEr8zF=ENtFO?y3tFK? zF%zwq-~qIrL?g5)gVu1++N;Qxcp^u*MEoU~+qyg!N*q&Q_!|T8O^jddKKGVRR(4!iZufMkm1o7#)X3 z7*PhJ+rjA8Vsmo@=wxfR#5Sj(i37UT<|Z|?(gSoVEc16J0IhU@{2B^<2%no%_?$*x zE7SS>1%1Jtj?W#!=X7X=55-J;E`kT}IR}mKp$t9`fX}L8b8p1wZ`N*^Z7xO==d%j= zXaTME_*??Z{6mRrY_;PPgaf63?zNB!sQLT6e&=&3y{}Fub{YDDha9m7h1liL3NebA zh^>GJ5W59&+miZ?WxSn#j{BjC?w4By0 zbpBL2ty|F-Jn3jXA+&CTR%lVoL~9j1fYwShLW?qJy$o6}7MtfIVE0?Q2W;~onmDi* zz50691NIOs^RFbXzgHcwARH+5^?YmVYc;*UnojIt^aZatV*e0gk3cKLC}tw|JUoEd zlW2q(We|G{#NLQ-ygyd3*UPZX|0{v(9f!-Wuh2)!>+2tM{!Tir zSI`&y%h7sUXuS%p(4v@$R*!Z4VoFN%+t@q|@>`bV zzY2e3s^A}oRh76ep>rj6C*zNTnqWuoe0vLq6%_uJ;ULLtKTINdQOuOrRCqvM zhe$d&p^UsnAg{3{W=x40U1CN?Ngak>TqicEUQB9idQxMcUd*4wk<{oC)c+{SX(ZHN zb%r|1W1Qr1IQ&W;6f@UFB{I0eSSgJLEg7r+BB z{1uJVD`oJQ3m&se%*+xqy~G?I!B~o3u=3V*wj<#e>r4wm)^)m9pod!$-onn4L@tD5 zNrYmiM3%z?61ha;#|dR5(tt#cEiuQGn4?O}!V)t-%H=v3#B({;*y?w~_VigzTqcS96OJVjikTAm7#!TVy=jC`2+^}n@aNk=ReL|@6rjDBUat|uCe*Z)_0ZL`mV6)v}o)59PU*iFvTZ++SkuD>3&( zxfH=5|5!=BI7~;LQ&+omf(H?+F6{j_A6eM@+``^t(`nJdmSMi&u|^APHEv-a6&{(OQ(~SfF;A43zeg|(dcn$D*k>FGe_@}pAY@^m@D}#( zmV~#k&r2d(!?7enF;gM~-~oyBmH2T&8Hv1xL|!Q|FPE4XqbznpSN`?HW6CQok>F)S zsZ08z&4f!TKQZtLB+Rsl_2k{6js0zud$Puq!Rw7y)oR?T{!?Joz*t~V%miaNJb*zh z8d+7!fbkAsyj^16j7aPaJrLRT{3D+|-*y=M^?cKi|FjP62NKv2iJ?y7yMch{aM;C z!srBOg%QO}jLwD!pg9GNEGK0!>QGv1)+;sZl$y4srm$4M5jn?NpKF`*(8MvVS88`9 zV(MJ#Fr5#}e5ca*lT_zY_f1MTP%y0nC-^2sHs-da@=c2T6j=y;64?cG+_^Lr*;4cc zok}BQ9ZQ+%h0qEzikXmI4G(a12^v908OSyUvJFek`Vp*atlhP?S&k+SYeSo-{GMPl z57u?C%x_v6uc^%(EdSyOeF&@dQ}|p@Uz?@#S%JP_Q^#i$;d2AD!iQoeJ^?&{&#h>L z4`uMF1fPmhvw5j0jS$^qP4BhMeQ4r{Dm+9zJVdKtncpH&Pd(BRg+2t)=3Y6Krr^4t zetV?jdH{XF77kaH;Cc{R!9_6>uD9UvwGP zZ!~dYdmt-57w`%k?h$(zmib|&@kid_j#v;5lq;~-Vi#mXJY<7XkiAF8!_$$ykG^1- zL$;S7`v6)&MllnzZ{PvQK0_nOC^t{S&;#I$r)o82S)gBRpLDrr`RKe#fTc`U!o({tnj|!Syq=f{S7%TpO$_xZ0x; zT$F+9P~e(WY9^GL`ciXnL~KKAy^(D;MiVDC30Y}{9p(|+1eW=!rSWI)!yK_794Hkw z!D1I=^&YZ=Q;=;+$A_gO+YEidREKPeAnOjTAfuQGSr2$Xg_WTZWR!ty9+1r`HM2_1 zjEGm>nr>;EKcI>8nqyOy3R~dus)l8LeuCEm$IGv<(1+lf<>8usb4C)@0dCQfV-veF7W z*(0_KEb}KNcKwqbu^=2M71m&}3$kN9WXGf++m((_PDeHneZff%*@=Rz23kQzF%z=A z;Q`2M(FiiiKz0_8ol$B|FEyt{yy~p!KDOBxO`O*mHdU#xb3I=B!7_hNg4el@mtSF_ z55aZ1hwHQyTqEfB+;m(c(HETKaGfoT@8MrP7u1ibJ#iizN zrRKtj*hFhR$u^VG#ED&sthBRmgpj6n!7P}z(n}_Ve6l90d z@m1-_4o6>br9*awAe#oQAfuQG*^%%7WV6u-GRi=xXgRF)cSHJvPy^lGl1}S* z^aVFNS~m%;MbHW@ikWDg1rMNgG8&;p8MGcifvqYv_m-NV)ZA5S?u?k7Z3moVn{&~` znXU3_Y_-SiJXq!*Dvke=aJ6F=gaf6L z;8JLXAjM1suYm^;ycmrTqzr=3g5cAo=E+j?c&T|T!gsB;UT&M~(8TdQZ8Mim?FA3t z^{~u8pTPHm!{?V==tD~GNsrj$-uYuG^j2_=7t-n7fWF{)NAEeIcO$eyk76cz55fcJ z1!#mGWzc&a^j<49uSDD)vUaO&^Dvq?x7U!5Zf$RQ+#Z2t{>{?(S7~oKZb3Lu%I*~l zpWue+MfoTlyp;~+G4us*Iw)@ll)pnOP$*`C@*+F{%F}2B3S~ff4^aLc5qZfPy=ZS3Z{{{Av-=7E#;F_5!@qH| zzi-A}Jm}(-cu(1?rr+(gX&G1PP|POTQOuOxJa~YkX_6F9C?mVgkzHw-DK0bJqtuQ- z7t*$=?ZDJZU26Wy6+^9mxYFI7hrdWDm&oVCnM6)8Q{*SW0|Gu;0>%ktL|%=^w=6R~ z%1l+6$wk4Rh~D_RZ0UjzdU)$n<(9y$OU@}%)`fPle~;8ta$JHrB}a;xa=ZW@klGoN z8crx9$3DohcbVC`%=C&9T#7Cv@2yU6m!Q8oTiaAvd_gaF9@(GWklI zm(F%how7voheY;|{RT>kD>0v>NHJ52kHP~oyH_&931y_X7g8KrW_B+#yOo*2Wu_)d z@i7?0Qyl80xVx9)ZZ4N#uuHMVsZ&yHRE5JN(I+sgBuX(;qOZUM@_SbD!wF?1Is%FA zTW0FY%Ey-Bzz)&_BpX4Kf28QPUCf0=0}yqx0lf#op7MsD(fr; zso>%6JbJi#gU&{mq39d`>gP@L1*6KM-(!pvMsGnYj3{Pe^a(rw&AVviEO=nQi`qCJty^xWs%ZLA?j)b6DmNNdT&Mfcz^w^dWr4rttYMebuM)`2u~x zA&$?%!skn9g%8C{e13xm@c9mn@SzMo)4=DjGBc&jOpXx!pEX@$n}YU9M28_IeJG#l zAu5Drenwe*6P)P~1>r!cp(&0_Fxj0)HPnXAW~MW0i@sonV>DeDwS!g|QOv|>LwEqA zPH2P?WiVO*Mn{yHxe=g^tlh@8*#u3zhK{iL$WMDmd4M*BW&X$nprafhzlK5|QbTi7 z_-saBN2T-Wj=tbX$7iANDS}q`P|U=q8Xmx>0*&yY3_d4=&xvJbahW;3%p4a{>S?XF zvP~~EaY`p5D=ni_JxW`{GJi@LZdI$WOB6H=;FHd&j#3Z~lrmcE&;-ZZjaq)adYsco zCDogbPfbU*4f=vp9I_>XtPiw;jAABayTSvIZI4EfQ3kSef$Z!ub7q8znH$T@iip?Y)^wU}rlX1Ty4j{A6?TWmYX&Uyw`n@9^*DUk}w>w<739i}D3NDJR#kCJ#5Pbq(Er5nE*AZNlfvbOct=Xa6 z^eZ>pmYY81`qLy|K$9;iw`DSr8_^Es?x)Fq<+i@~P`oY9AL0Y@s*0cw&h=du&AuRd zKsjSM36n@t6f-5oSIEH8sges$C?lysNNQlY*`?g<6lHV{x{$5SXb3YJ=rZybau=Hr zvkG>y33;zg7%Y*W3uh8J#Y~Z34i5-8dUXwDL_Qpm?^SMwmYdzn&2CZfd}U2O?=Qz* zF8E+5qST*JcDK>Xa_nZKU$Xf4wY;x;Z%K-8yOE?QW=bl2am;m+3$mk(q(&jB5#?sz za#I&&bQ?1o?k~p(myy35``UzLIqGae-g1nV$ZyxkDQ1d%H9R2TKmx`IWkh}mB0s3y zj4L-|%gvZ5_=nM(-^O2#gIw^zI7F$-G1f*e%Q41AzxL&*m!uxSB(fY7GbQyrJRq0H zB^R7fMp9Fd)Z}tAvD}Q0GI{}B$kw|$CcBLM<(Oy_lI0k06Y`d0szm-GoJr&qGe!P3 zJRsm#Bw(CSM&z>*`OI=Nz1$ogMgA{z#jop`F7jYHLd06|5FGA8Z~Tvq8^0iWj^y$V z+)FMLGv)FbJRpVlB?X*NMlK7G%Ms;fZj{J>ppPeVgiFLNlnLM|tin?+F~9iWdVa)L|5Uz0_x%j0Cpqa(aa9uza>(H$O;$NCaJ zPADUfGmyvW<>s_%i#Ra&vVA zsMgx;Zks*O!~tDvb6ZmIP(}U*571Cp=2s*D-QWQEWfJ<3JKEJLeDr!ArNQ^IU|;dkGFm@eMce8hQyS zX$`&RAv%qSUM-LB#;-XD_yplVDWH!nWCCjb`Cb3kMP7gNMLIEg{mp+JvCoCrZAy${ zCSvzlVk?yxWf1!g#J-7eh409@-`esOIPr4&#w({EJzRWCPX31kt{)vPznnrJEvF?f z*7-4=7GH}K{NQMPFSPhV9H}pgnP@!=52&xdqmlZe3|fU1wPsDZ`7HwWoV5$zl*4!7 z#DT5x>Z={Uj0*ox8ZW{!-?k!tlWSMuzR3y)N`3v-+WO*Kc=GKkK)vyk6W_ZNw5^Dq zoZ3_{QNA!oh*8W$?BDPJM{l4JVw6FwBZ#%H&~NYFwMOsR=6y7ATHbyZ0s9G-`R*0*8(@(G7K8((zBaVfTTbj}dM`>R z_6z!g?vB`ILhM&)g&4(5#MZ?>dAXXOPTF)A_w@n8$aa?6yeN}q6 zI>IuaOW>+>xcvGGeYBibCpxc8r_~vKLC(>t5L#WJ6h_{4dpA?m@q>#^g)&5TJaij&uD|z1hFa8X!sa!X%Ou#Y{=< z01rqidY2SsBsB<04XiM`RG6KjjCN#3{lkpxm+CGfe>Hcp32`-pooqth*M@^7^8Ok* z#Y~a!ZX@4C0!9jy5&3XLzE_1AT48ptFuO&;?}6Uh1s{l)J1t6fG*_heV04J z<>fERzBVmclscQ1wND-Fcu+VMPx4><3exzEZF!3(FaQ|)8Jlmp_nO`1@M3rW=RS-p^RK6BA4+M=8!0n zh0w2Q}yFx6X=LtB^249VqWxR+cgX3FJUct9?vOA0ulj9lg-m)R9&W|YWz(8m**?Go|V zWM=E~m?wFh5ATu(#Y}lz1rG>+nS_rM%E;pwGxZ{Y%4g{-EaRaj8;G^ zj3{Pev=SbGCVB-IWiUD!j83dDiz7gHS-ZP!!&h;|0i9@blLz2aJwSZ9Rv!Q6I(ADt z)dBL$B=jM>=i(GT_tMv?>3r@(UvP@!vqbo;f>!uY%*5vjcmSV=(8zU78GOzIpK~hA zSrz7t2+@<)^eNjsjV6xh9HgX=yh}Yq&%iQ&K}GyZTIvu5;XtXOvn*#}bVdpzzP~HK zG@a3N=nF1zjLsKE&qFJWC}v{x7CeB_D`JmT}Uwfn|4d|_9d&-KVh3+QH#&v&rQ-;}t zatoP&n!nHMcRt_K`_1XZen4MvlOuMc5c?5YAx1G1u{P@nv0vdxh*1WyJ3;LB2v=Kc z)Xp~Rpo!zU-7BZNJzVR;GJjVB*WC`6UrwQqmeX2~&hJjA)gFDpU5?gDq16Fep+zwh zt&QOU_0BNfB7d-5UtrlV>&dv=aMgowi@@suZ?m{<_H)|4N=TQg>RmM zqodFW70RGe1}Y^vQBj6 z-qKdOrL9=&(k9=*cO@nbdNx{Gt8q(PEkv$@u@Iq{iO6m603v+hln|i|BHMyUpPcEP zGh63OuZYO)=#4LJABQ98jb!y_?5!;iuC4v|XtJ`sEDmpFx05{XfM3ajVx~MEf(PVb zUo?di%E)79$LJmW7X7`-gEoTPjOih%@OEAa}&*eY!H=m&{nP7Ls%Eu^fKD*g$Qk#^)V>Eb-%$faiW}lqd zJA&~Edcn%uc1Ai9{<7|8LCChVkGJjYZAo~=`6o%_Q#h7HC}v8eE&e$#65-38BoWF; zWC9YY&zXaB=D?geAZPZEa%l&H{G?ody)YfQtJJ%6f`bvOF6@CeA6eJ~+`{f}(`nJd zw#R(Iq(%#CHEv-i3Xcvj79JEc@z@L=z@sY~;XxTZW`M`EoH;CKrsT}z2nJu}1XkX{ zPIDyug+0uIkcFM%E$n1V!duvxl1LF8OCl6ACBhdtA(71`ewwt0IWs#-M_$f!TrU4}c+u|7JLJ(Wqu@w{t82T!rX*{7gj?IW?sT?Iu0_kdHNp#y zYqZQ(PX!3ky1ITdu4i}4yC~O5wUgxFfb&i+USzaz@c;}}#%4@0QHBR%Qm?^KhHZQ)6 zNb;hL^|}msU6M1)a^|8aqj~7cUy*n;y2K?FEJKu9#24ADSj7CXq9FEi;wGPYlMhA< zF=cQ?qvEw1SG<=Cj3Z$zi%c;Sj1%Aii~MIa0)sMOEC-Bha^|Xt#EH-YkzL!7tl4WE z2ES&na%&qt)m|r|o&*OHD#c8phOZ$yRYRqWP;W)3H|NZaIkO^)mai(x-=4U!-0T7l zZuHh|#s6g8F2Iz*?TyyWYTUZrCNP%5SYS}h1mjA0z`89%BkM*PFap51D`)PENL&Ry z5P9o%m&4$%+ntTp?H&pBYB-QkDP{`wc6dOj*GYspp^Q);L#U7B%<7zZFlX-1nfs!c z?|?!6@x)d4hzmPd?XBK}ZuNru?f$_ZHt&PF=^r-Z&wF=czTojjOJ_B1>HaP}0vHPq zikW!uWkJAjKN?v&%HZ(=cs!Rg&*aQgIrBsW<8kzYmG@ZioFm~c;4^LkgQvWW^a)GC zyFt7ti97+vk_g32iSV^TNaR_GA19QN$m>YtwVZh+XI_r7c-5M|W}APaiGTC*8iM3L z%9pvmm2-cb^ad>RZ|3lWng#GD?mTZf06{pAqk~sG0xx@6>-U~-(b-!$Kx_QBNN=Mr zcrzFMEz%pp=wHwZBZ`?A@l8NL^FA6`Y|3Et0T{iPGyjeN@!deM``kAFMH2_~p3P0Z zN&nab^d&6wA0+^N>;U-{68ezGiGQc?`I^2yPUrIt`ht%fpAUu4x6le7ikbLySWogU zKqGu8gU=f9`7LLD$(f&W=7)$sIR5b`{n%XPZhiab6uOnWgp(Pui!yNS2wdA&n(Zo0-%7JhM2xQmgY^{KOhpqXwmq`a3fsveb~r5a z11jTR>Fwl*1>r!cu2$nPI(P5~^ zD;y|{26>DIrZD;ooefQAbUONiJshLmh0$N36-E>@G5Q-kAn|k12qVg1Gy;tFtu%F& zW_ZMCnKixGHkY7@GuqccyDJ=7&D)B20kI`t4Q8-W-)p?ADr!cyV&PJy*x*UDM zD931|FuDR-VMH+#qW~Vj=oU1>h%y+>0;3s~W?H2=tkO)0Fx_LV`BE?px(`hp(+p&# zm)=|t(<)fz=TycY!{>UK!hv$>O|z^8*sf31oNb;*6X$ibO;s+v29MVZu*@Hq;ML%G z`I~#_LvS7G;aZS_>qYu)NXPXO`hw#eu44t)%g_ogikWb|2M?gcx1~viQ3kFvfa~;1 zb6TZ2rP7>SX-AD6V4Dxo#G##z#I(rH_Mm+P%luiD@h{NMcF=-wpcL6@mb_3q z#iMqzcYb0D!H+q~+35s7L0@o|BY36|G}H#jIO1WNR>F^ZX>RN+-WD5)|uQc{#rQnv%j ztr3wetWgi!T5Dt_oxi_Us`qRPcbSMMR7d+&kJSb3hf>xkV%mjrmDMOZgcbY(<3@DES%3~3c z-K`N{PX^neXyQa3^Qz=2kI0^|%s*L)Z(Qx8(}8@ve99vd4vdw?UL5pPI)!2A3!Zco zo)8Lr+nG?Hn2Ev^ctBBLQ)%9=G;c;YrlL3hMy1W^5a#r*m(x38 zdGHtQZ--#`>kfS5x<>xS=S`~+XD&7WqW;7tA-9K*+jHN5PpyPBByDC&L3G zKUM<931vk7BO?F4(tKNKzOFQ1M!_#ZZ+u<8cfkkWB1&%VT$iui61a8w(kWBcrP060 z`AKp-4RcD46f@xdk^wC9ovY#{*`>;TDH#rwJ#}3;!8dhMlkMDjbQivd&bsh_hT8bM?R(J| zbgqiNi0mYc?t@ksQOv~X@9+RL52BH4k1`l-0!ABEnGGU9k6XJZZ1W_VIG~MeKJrM{ z-2?O#Ec2Ts0CjhO{Hh3j2%im7_&iNt-P8FzgT7!h$7fUF^DMN&hhio^ufqfQyog5l zPzIkW@X1w~@+wmnA$r4_zG<7c(8Lktkdi*VxCCYH zJgT98(OEv7(L3l1dN@W~2%~>PD~u>+V)S2l0Hcr42qVg1v^5y@sxmzzKwnt9FKzP` znmC|dHXo^>Z9G8Vz%t*v3R{ldStfJe-^K$J4wS;_nF8fII@l&1%J=9CdOIk86evGH zD^MtAg3_UbKq){YP$&b+&VVwY%IsKWwy!eVMQA!&>rS@mj3$m|0J75B8R((u3d{Vi zRq?yZKo5-$4&*KZ za${%(B*jc1E8qcBcSj>2DFfu50J%q%sjV_YB8oX{T4|dqG;xZ1gqapRgues#DE5G5 zeprIya7QuRq~zADJ_xbaK^)R@h}E2Jcsj(M=nIB9hk+7Syz zI*|K0bxJjQPdWPgs6m|cz;v90(HD$!I1dnW?4GH@OWoRg}| zgep@XvE0|1?q{13XyPmmDS<1+19~*)!eK4 z@=#E|!(-Jj|0BorCdmT(v&aL~ZZooNwRHD|w+E|(mDS4^FXr#U7k4hGC@z+Y2_CG* zs2%@a%?0bY#i}KXzwKPma3XFg!{}~PG0IQrzG~5WZ3`MsrhYH!h~^pDt{S69wyi7N zHn;~foD$AZzT*?s1;O1CY#4Lp4v$wCR6|`?xE&+zCu@IWK|#Sl21N-k@*o;w54@*u@{*Ij1smAD$?dl45#59jq$J3}%c8|(D zPc<=5WmD`b9lLd^F`D!26o*<@xHA?HwCW0X5lA;Qg5+q~f{-6p?E(POsktPuT?J({ zbzR{=sZ>@=e=@`isv<%=B?i~4MuaC zeKF1J)xop&8n85?;(1->dAo^u)>b?=9gOBYBcw#i3zOH8D-k=ll!#5*mWbsXT~i~y z5|MQoB_+bs)|SW`Y-SBtqiE4wj)u!FGLY2v#IHnqnn6AF$IWYC5De;xOS?iMz}u)6 zRTboGdah#Ia5^7whxEj`Bw!60bj7g2g9-|2Xw-lAo}A%Yc#@bYW{UY68}k<$GiAg) z2Qkm;X=X$*e+zwnIwHjX0JEUsEQBbbBdovXf>}NJLU;)=n1S;vc>Y!AVKrjif3C#( z9Xv>^6k8kX;p96PD~@I+8sSSBvF_HZ)(q}tYI-T(dC&(ny`n$k4fzi2W%-^Iis}m?^e4=G?ft!h`Ax4`i$dAx{S2k2`755qzEKVpR!dgT)L?diiYK<;L6AZDm_u||Q7wNFS z;Uqs~T-XcningtyZCFN=Jveg{4Hwh<9$YJ46Af>@Re%STVKU7nI?bi@vAoJY zSKJ|2xP-%tMsDy8m%##CwjC!IcH3$j>vHzA8Ch7p``TGG+ydi*uH!arJGyg0x4Jg( zjIAr|F@j)jy|SCc8~Q4a+iYS&?g)`M`i?$h&RF zPUW(x*&|O2rDPXv*t?+r{V)QPJ`$o8GK9FZg!mAA;opJd7)G~CKmjpmE0ecTsgn(> zwCU(p+vs+c=&X<-x*-zXqY~Z2F1pY^4iOvccqQkQk z%J>P1?(Z(TVR_;pY}PJoM&Nxa7IWtR>%;}pCp_Y;0u3*j$;_k zn1BK+E74j!or;@Twij(+`%7R}$Pn1U64*Z^u$Nq5hv0@%S2#7G3gPYe7AIp+6?PAL zg>toMaZAa+3Q@{Gyd6#h``1F<`l9RqhK%?pk5O0QrtrO2wR8ovhq%M*G~pd>dj3tE zY6#ljF`QyXz+Mh`TL;X{GhEe&cC$vV)Bj(zsE+JrOT6l^h%wX^&KbE*wb<1a&K=pV zzXVz>vGAexh=3`=(o4UtaK5k?7HhjprftE;2>W;8xYoRbV^|b_&T~0dVX}gTPOMS( zLF#HR66*WE2Ne(<0u8?M5rfW`=RhtJSjAAGdVe@q{V3`0{%P<_Zvwq5`KaCEivaUFep zN*}y;ttE~XO-)D#h)pJxvTmc(@@HGz=w(`@&F=$P01Y?eBw*|qW{cn>2qeRMx~zj$ zWLbxma3SmP1$^Rvz>K4=!(Hggb9uZ}*$?Dh?KUL^@g-CY=57tfDzXG~zXtOSeAb$; zaMWN{qYINf$(X)}Ubd-#76_ti8$FXdVvluu;Tc#Sgxj_ILqS3BYX)7Hv*f=${sf=3<_8=#*q0b3bMP)D_A^xPQu-Mx2J^B8V-;C~d0m6~4L)nlFF0y2 zZ=(y7e9V{%t^zr%UtvHCE@T@$le_icb@|gn659WTaek_CT1A#PztlL}B9dBDh@-~& z6$51WUb(S9QEu&^Vm@DMFjkQzm>)El^(2^eykLG|Fdd)>sKvTzD|OeA$A(e(uTxvS zdVh^Za2Q62O<(-iDeyFH>{!u9SN?Apt47*#c)N~m#7j5)Czah$i2vGA*S(`H==PY5 zIM%?0Yz0=41xH(WlC7XKeBxi6;HYb}9=h^fp$MqOifGGF3Oll-1V@MjBJOJq?W0i~ z3Z>XFb^g~WP%V4_3w_ug^y$xx4IPp`{88k?VdTUAI)y)JHgv?O$dDG~#{Y!f4k5cP zh>GkwqY-vik%ip`a3SnAgipL`2S;VMA-agEJbCM(5$Z%Xgtm4yHwq)#NF%a}ED>#{ z5p60FZR|zVJ&b7A;&*mrRFPyvqwrcP zZ0nOM3FE5JxU3>eTw7>do5Lsm|LZvF+Vu$I8ki(SBamYCAub$;g}lnq!J5izTvm}K zuAUm#77|w_j-~15?}SETwu&q< z4}=Sexi5Uynr(2@m}~4LLu|7fn*0vvwlSZCul533qu%wVQkyh+uygN|b{klOPeK1} zVau3zM9f?;KN;iMAGC+ za9&hpYhx$aGUkzJBxb9~67yKNkeCOwaPuoLa%b4rYNX%A|CFV(RAu$h!PrQ~JM>7-$4g7HQ2UPI7WG~vzvdJ{k zc5TziBHbHi3~!o-XBAn(o2B9H3!k;74o8h_HoEdu1Uw)td*?6083E2o>u%FgyZMcL zqtWf6ZhkS}sJngC&2QTqb*~?F&rj>Fh`JY`I|>@%7Phh6_Cp@zwh)aht5sy-wiqsC zS^or|wPqBKW&{oj?*xWG1*Q+!i&mao3froqdQTfvx+RyovP6t2%oj) z036N!IB0aIp+C>a?XN+)^G9nMAxPfY0@{Y>!&GQ%qdW**jPfrUrB!5!@+^(A9zJW$ z!8mGwXQL~i0(-k$!<8zv*Ax3I1Z@5N$A=-Eqaj&EmXI#ckPelQCgEr%;Gl6WWn5H* zPbd`uO(3-G& zO@2P~-0>><@TYd}EjLiT0P28!)avc=CiDb!ghZHNLFEodL$b5oj1y7XN9%d)fVW%F z;CEtT2k}-h&mVza&prOGt^fbW+*yFhQEXp)Hya}f#Bf`Zz`{Tlmmy(rg5{4r+}+)s zg+K`I4|jK$#ogWA-TmSGf9Fjn-ghS6NyUyY-zOTmswbt5m?Jm$lK#szuM>~7Mlnu9S<3A0|k znOFHN&}BCo`zYvEUT&8Z1XoV$HU;Qr%gwW!c9r-W*(G*gXgYiq(ef%O#%^bcbW9=h?Y!@{k;5-LQ8pEd_#m9_|lbR`m>an&oi&Zs+coTrMYleN-Cz~gh+)spjG$}a*cZxJaCuWh zZS7>JUnx-8*X&+)K8JJJ*TPOCDcBfRZd}_;HTm+GTE5HUJuY%%THoO@@o}Se0Z!yP zC)mD&5f!i8$60FF^zNqNeRqZ2*oNakjx+pb>=uzcn^9u}sj*LBZT(0OAMlV2YjbvW zv}~}B`w;d)-3zKwCw&~hZ^T#|t^TrHbFqgm*dpAz3|!|f-9ofAsz$Z}jC+V} zOHae0pdR}8rkw2R;bWnEXvEl&ET#s|>snFUw0xCKWuF9PQf=GvO*U1}E{$rtmhYg_ zEHqACe|Bislo@ll$TbfuHc60nO`yC1rCfuCQ{K>A!O@g-lb}1cyt|Iu5;9m?_Jr51 zH@P)o+=<+n^Pv5oJGE?@^jtB~x$R=isWK}%?;NJlm`r0AzHqX^@!ey^Xf#)5)T`=@ zW~%7Qz+Jc0{E`OEX!pt)^{zdmJ<>C}q~?tFOwDL7t3?gJ!zhyi+nX8Na93{Jw_UE{ zXR(i_sbTKdat$XDCw&Xjw^s;m1yEhu{VV6!xAy!F$V|cJ-_%OMy#p&$*H|W*xj2bN zzH;M1EpJ#EEZ){rqYkynH@0hxZ`h-yf35M1>L-FiLeq9IC!Gwc0kx_qiWold{4dGcvHNdY-e7;Pt~#@5M6 zqwSQgq^c&W>O^}XLt$t?B$Z%R(WWhsneIMj?hX!XRJ$ZwexlO;E7$xs+iUrsY`U&p z_if*$PLGSVYly5ByGA#)D}zVP#UWuf+KgFQB||%@65Fwvs*+14ME=Q%ghuaDR?T|j#F{PN>SCm%or8pxs36I zs@CQlPIqQ1ZC4036|7=`+FHYtw$x&FuS0H~Q*V_`Aych58n!G|g-z zb~d|4!~Z>dnbbH%a;NPtF4|J$nDo)1yKBF83U{AwJ5<`0hAWYMwdtd@-Kb^qK4FROCIMwcn-4&-ejd&Qu&9E4qc15-Pk*#zM&N8KK6O}R5Qd*52mDXOWN~J@u zYD(80hLmoHjHTfxdAnd!!L+0GP9RTrDPt#s>s+vR^TN}0Wm)Xg#eQwt)Ya9#kE(BR zT3Zq}3NuPO##;XTZy0q?U`iV`wcU^_O-G~dRaC{22)(**)P0cQjLi{C9u)WIn%m>H zNbMt=p)8Dcy>ZvS51@R<4XAvJ5^kDl;|(^qz~AbhfwVmYS-Z&e!ot%h1^;kJ@jzsX zf~S;EA(8(OX$Ivp!ycnqwPgQ9X>mTq3Vj(c|I$Vu{Wr{9Yz_h1@yGbJVJ~#eB4}*V zO@5>8{X1mv&fzV3YxBaxL>x^t$A61x&gSAw8d1T<#XO(NIZsK#XA^^WUa??=P(1@x z%enHEx3~>$3r`9Bn+ibaTSf*6ob1KnLGWi4R(^kDLH;9b_r-YiH>hpTY4HBzqAtGi z8xay~LuF-jH{bJ(A9v@-FxZ~{!pY5q^ z*9)jNdKAyr{Rg@iMuQrBoBL3*sF&dVQSFNes0asCHvXi>l5d>3vhim%F6tYT-}&*h z+MQWg%s2L|jQmB7i~Girm5sluaS7kJbYu9QmB%ZOF_sjOTntGN?|rTmV&!Gl}v!K%tDhY_$l?$4E1HH ztF=69O8Ziw)y7y`B*Ltz)zN26>uNl{( zlTY6#eqc@`Cp7m3@&FjyeJ?xd<~eQZWZ-VSuO9@TMrb2gV)wBf&YzQ!&o00hQy7a= z6D=Fl*)AjPnz%0G?xM2rMnEUeKn*e>h41c>4R%o;y&gSGzd>{;Y@+_CI#^)S1Pl?_ zECE9WHc!ChfXesnThQW0BK0diC~upB-lNt?LZ=kZmI;_jV5|6Iy+ejs#ItL{qaCe<-4ZaX!0ri{4N#e3k4`ca=p8c5E}lITo;d{eO29~g zy%S)YRx3Wo+lQ7~K4=4L$e>NDg?$qqZB{Mpmw&`E~*=p8c5FP;Mv zo&^LBN`UsL7TOZ95TG){!JT9%(mQ0(CfC9t36HkA7RDt&`&BDR5AB4sR8G1mfGsBL zCQMqPEn1E`&D%oMBJWwUGSXr1lGU0H`;@HGbU2`7t5JuOm2AoCaA3(6tPW=`*<#XR zOUYK84reXddeh;^lGTw8=PX&V>2R)+m6{HhE?F7qa7@W+MTg6ltWtD1wq&bGhbxtA z$?0(Ak}WtLZeB7Ibhu^7oYLV|CG$y#+n1~kbhu;5ibaPzm8?{B*w)aqp`m0J7;F?Y z6LfKrlm##3V$!v#VCO#CmH=8vI9-kp4s|$P9wsa7Y`7!`)lQci(!)9|MTf%S>Q9QL z1tuh58G$1bp#8&zBNL!~!iA#}u$;ir30Pj>m;|gKaBKor1cWjitCr)E7Ht_W9G?Jf z5-yyOfRzPKOu#AvCnaE2fs+%kn!qUu_?N)H6R* z(-W|^z!?cxN8ro^Xd`jqtORK5aN+C(tS@j*0yYphHvt<0Du;L;EwzTI9mrvb+G|`m zKjGO#;DQ8fmLlzJF>hW@x`lWyOn9~|Z`lgKGT$I+Q)RWNjI_)xK*ia!WJRLG-X*h6 zhkZ&Wkq!rxtk`roS;rDSEH!&yrvzYa&1tn_p^XUPgehjW!o zcpWZXvU1enn35HV4wo&N89E$Wva;6UN+l~c9j;t5Q+2p`$;wuTTb8VtbhuT?Ow-}^ zB`b0r?pU(Y)8S4fvsj02nVUHVZJC=rTIQ0n;Dy{qx;7PT&C<4mbnWmV|0>8F?m_%b zop>AFN26n{-8NQmYp3_7JBm~{rtUr^&yDFWP{6b^Pj;pd=En32a`C(3Jhonua$TjD=C`s{#6Hbn%ml8#DsbbiY(|w{E$Uy?Yhu zyG78A&4v@dtKR>gKIr6o@T464mktNS4LiMOukAn>S-EB>rErj-*4&lyH_tY&wnG%y z*mf{aRv*HwxpoNoqm4Ya-mHfkdGKp)99>%O;DyfCoTB`iQ*ftiZaj?bVw||C#7(_pw`^&@;BF-J4u1;+2G0Q zLzp%9FogW|Q65|G*TcO$_%(MjU0NRHh0fNTqWqduaE&$Rw&|Y|81+v?+~+5A@WrUE zdA;o88>Iv2IQ$y(sfzkF`5tvLeW4S2u?<&aFI$AnQU6q=-H)Y<3+HiIoG@pkqPtc1 z$-=2f-z|b%3+K##`k<4AlNje0&RKE8uCj2>hLMG1c2WxG2x{RxB7bu&obwgf*mfRI zws3@5IL|@IF9h+}`jj4?;K47P3+U4F0xxv7a1`Yij)Kz*r|d&ZR!c)m)4J|Em4cRl z=zX|GQMm*zp?|w)?cx%62^KfSOHPP)?%uuuPn6$%uWhduG$iKUPrl>z%>eFI}lH{1cX@vZ$dbx^>rRwU)96QJoqJW zEnQmP=7r9dfTDa2E4b4oaJ?8SmVoGexJFUA1a72%yJzj<5_lIDH^rM$(Rr$=B7L_A zaxHR$W|z zUuhU7@x!U;Zmpo?gkF)pTLih5;3NO^K_^QvDGa{^AB`J!l_mHXj4VO3lTvtGP)qPr ztJOT8)I9|SOi%J;^&!j>{1L)2t>5$5`mG+m=D{z)r|HtkHpg}a_|>Pliq*#!`Qk6U z=(0T{s-J#Yo^e?x{SM#$lwu`aDYW__*ndo!MSh1SRJ9k*knt%Cf{#_&mPxV4J z)x_1@fvR9sjOQgt+Pz9$T+M%I80OZ?spxJk#$+{Dr0*6%uGRd?KYh^2YEBBnujW_d zhFxVfzXl`Qyv$BY;dQ~LQNLP|*&5-+H+Zq*NBR}D)X8#Nv0z-VyeVp(D1H)ou50x> z3T$k9n+QxpBq@ZzM&G(PV%cVC;wK>E6G zL^>oNHJN4eTwiv9Yfvq&f^jjCuWTX(n+Wh5O~BVj7f+FcH7u*sZ@U=ne&B)MPMEtm zBm{q#3hvhFF*(0hjJ;a~ndevca|7O9wwKxucYM#V`Q6{4nnz*cY<~Es&!&OxvhL?8 zCVpe|<3D}S$<-oR`~GV2Q{1qtTrGZvkv+m@Dy!l@f;|gX=)hkDn@06D%k8|$i@)+> z$BReB0&cH;%3QHvT(JBmYF#{fiagiF<4*-Pw*A4AElOc79@9cNrgdr_Tc^~+f$jYFS=}hi)wmcXBUr7`8wWZHuT_>B*qSRnKLOT6K$lu^3qV= zxx=MF^DnJgQ#EB%O}sR8peh&@6(3LUOtm|MM5(cL~z-B!%J68-3%3UFEzn35=X5%uY(7pJ3CdW-BsVBfQw37dxIPDr%{{ z_VQS>)7;z!LcI>1l>@70YRIF-2X)E9L2*W2uO z9lFCkwdf?Sx}_$+SF~xWb65L5*phn_;)ksfUp~cyXt9Av5ySnZ}Cq8Y?`d z@%+5#k~WK~gT~4|QRCWV(s(A~N6jlbz%T$B8#{1>xaXs-vlD%7dhT#J(d+csv!`E= zvxxE{vrYeg=|;X+t^5~?Wz*${Y3%D(|5A+;Eop8UK6c>+f+Q_|*zFaOQ}eI6^&h{? z;C{WdT~lLp{4TZod4^ft^o@z>7sONXh9n7CV?x8wmIVoR_wW^R+m^36h^$PW`MYYx zg~IqprlPxbdQYwo6?5+vL9XjV>py+a$@L+z&|5xd+_0-$ALfFQHDq>DL~{%3Jmc0_ zp7YE?P{6bxPj;RW<~(y8Uv-UXJ%-2Dqx5hD5B@w;bRi4#)N&H9ck=ri?F#lM8*y|z z+4%i`qakY-8J$O;!m|x#5ne6)8>AtY1WpxbIe|xg^6$0}jygH%v8Z~SR?&ms3F9BV zgdU5j$LSS4c=uA?V{!F3qoRlV#s0vtgnFD=(W7T2$CB!CRz;6ql|7bHkFzU!^sel& zw0fLV(W6ggk7ek=&4Hi16l{@li!dM4ObYcYnPNKZUovTQIG|)2=y1}KO;(4Km26fz z99Xj9>u^xX#;L=>B^!`-wkmnSr(Ra6Pb9TEwY6~?Y?nif!~X@Gw&m#3t}eW&UVJoj zE=ayEujq<1VbYIV?>)-Cu2C_D3lIA{&r^KCv#i)D%f!3x4lD&@VH9JDx21Hv4J*%5 zS{VwMR^rL3SD2-ADTHHMFXplJLOq<%gI`Lk(8Yc`)7@yS$G!%s)3^p7ZM3W7#Py=< z>1yh(Pw~p`OGF%GX;%g$wo6+&es#rH{HvJD>F+Ky6+CvKSyR1h|F(|LWdnBmlPfdA z%QpyWUZc5q1&O52TB#viRci>Nu2f9HN3NsD4mTqegU%e#iUnh26zio%adoXx(0hIL z)-Rk^y3|m^r48tArF5CiIZr8V3k)$m{Ph4!ZEEk@Ys5t9C7z! z_{vb+#LBAh=@y!ldJEB2l*&Y(G=NZYti)RtQ}B^nDYAo46%p;Vhq7Y9xX8bCDt})- zb#|p%!DgkpZC7)a6>FskT3*}1V#eKUBIGe{M<`(0fhRLg7~}4SkUvVzW9#jDxQz#I z+)i|jnFhuH2d1 zuc5l%eYjxoo$hy^Mn6Oc<2jh_g@-|6KSbb>1dJ1SGy#VSJeGjN02L`3_12<83YFn* z&Be!)nDHHBdhnC;{Hxf8Q4gp`!S_47V?X^g{ltC@a)O5PL_&K+s(X#0?Aly>GKo2| zV@!vk_(T$s|)k{Q$b9207NMh{Q%;EU)ay0pB= z3za_^)UJ;H46FVV*DXJ)@{s-2gOe5dd)coJwTnls?j&4%9q0yfin_i8tT?H6=x=v~ z4F6Phep#I_)n&?RqV3YbRH7J?LFu<$?y{c&JR@-bTix|z%?)jf^K&1S-HFo~=WKen z`w7)}pRAX+4nLqFKlzc*H#8Xt&IzN_icChgq|#}~8kC*alkpXN*m(*oKhsrqZ0J6xpU%XOk@Zv1?#DGR`=<}Oh6k6&jl0U{1Xq}=1#^`Jc%@*^ zf|WY(YT&3B?*7I4l}i2rm{ru6zo~B zLI>U@*i^7}3A|fS_e5@i=Xn!z9~3a%%adIgg}EpCgrZ`rFORJs@ZfKU?x(d~FX(=! zliP#xMfw@t9rpvN=sfGJB7L_AGOwG}D)YgA`k<4_lvkWx{pZmS#SObkWj+iewP$ux zF^>qU_CA%rx$egwhXSU@c(U3PruM#ua7^o$Jhpz$gRi|OXl>UE-Kf29>F&6nOhtFA zbdqy?Mfz?Lbffkr-sC*>Pakx0lOwNq0}*aCpN<=MmEwB_MvBk;q-35IRPlWygL4(% z3sAuHJWp19!W7?65RPg6fydVGc<{ydBCYLup&P~b3*8;}OR4B?)y~?y*}8LNy9R~I z++~&jV&Thhql_hEKCcK$nV*$Cmoo1_0n^(&nKHsC^E-rNT7Tuyi}EfF?RtUpj@|~g zO-afodqbG~J+nV-5RGl`(bGodUdVHy`Vb06^??nB17Sw>w~gx0vQd3RL%Uu`jjE6R zndE*w+%NYvB>&LsWBS|J+zWZe_8Alm=~EjL2f~a^zsx$OwHJ9>oAl7ggV*j07xJZh z`pP|h?Vi5jsbvtIC8fKeZW&ww$?>f^4dK;xCD1QN>QDZRXyA?iE%y1t_v-L+@(+oZ z(eHcqr6cdY-QNaj`$6p$KkBRTB_Cw)mHFr?fK~uM(z7rtDEWm-KAGVU1dZyWR~X4p zYMw0tKZ|t|Kudv#k%y>f_$=Z-G>)1)>G_MoW>3JcA#9Fx*l*=wzbkBH681+3YfXp! zSswP6!sblE{tjVtrNbKddOr-Z5m1;r3DciEaC4g{9j3o=5W;#YY~CcSR|uOg9oD-% zj2{ARD9oRP^$lSQq{AjD59_C}1(UG;A#9;^*nsk|NdbJU=l!sHkmveR(YdWPtzSGZ znY*^c^`qt`bIstVg64+7&jd|ngZfqTlBs7(5{siK4j~#;3rqKKdtB{!``P)!K++9 zY{2B23dqwm>YFX~s5q%zc#PCNMik>onua+N<~=R*HmRqR02NY??uOLUD>^0h47`fe zHehl!19=*uzS&YQ5+}6_kCD3Ph+;fRpJ53}`3K|a<>~$kMb+i$#_%-PHSPN<@hy7A zhvwbk(l_TVkLgd5y)wL^ZSmv_dG~ijbY<0*lcH^8@waSd0WN1Si(DJig%Z8@Xl4vJGXcjPk84^@h(A2S9O@ToOeC| z|6Iq*A`@C9zP|0U7w!5{G6!_nSTfOc*rR0g)L~P}hNerI2n(KW0nx=Q!`{usC6h@n zD6aA^OsO%a-ClT_I9yz-55PR&z5sdUM(!IYG5R5X#f>vxj05#k*p{yFrR~i*E34SkAkVc*iEZ8>e{xkCv{U88<2C-4wue-pe8rS|q-% z^Y)^<&YJ`7I&Y%6>%7g=UFU6Ry3UKR;ORCOUCc6^thu;SGU+YE)rIT4@4r=S?t#t4 zm6P0Cr*c=n&inq`s=q%YhU@%xyviBTud5w^2)3j8W}gvP(NOYV=UsS=6+`;#tFA%K zMWbTiJ27xuqdRK`70Yr}2HVwg+*Q#r1Dm?JxLV@VZsO`fjrjh1#O9u+x%jUn_nxWT z)oaA}-&_4tA878wtJH|sct0Rg@2|euHL`kKjkxd_D_o5XX)YQS13!R)Ta6s38C2BB z8r`UoHbut_Y})4Hnu$*bi>nJY;`@(_%{^Unajhixp{d-}YsB{-ul}hTIh1`RJ72`V0qidL}4NX{8h#lBqmZ-1z9 z9PI6bVCOPhTu0hl(&LrX`yJl2oS;`LDt0|0YzJZayG%xZl4vz(XmwrgH*<0QKz_1l z%9mh8Pd@PBx5754L3|3a{PTVzBhRU#GI8{M*neA`)5>Nsx|tD~HmCDyVMEP^0i2-$ zR7j#b!D^D6sh;{i)BRHh|0m$xzlE%=mnL=HjLj&0{P@$LmL0z5810A=Hn5o|)`rzW$#+he2-BM*ebiyFU0E zl~2#itlgidydiGZRW{b#2qS;+(pDj*ag$)Lf-Py_&4T2GPCBIFtW?X`|fTP;^wq3E>6;^p6>*0rx)JBa{@9ji0B^w}9x-r}&0h z4;lCHNV9F?9~6E>LH+5`u1H0(2gLoY;YVp=Z_I#nUIx(G+?N&Wg71!*Me;FT9<)Rd1c7xwx%b3)aV|9xtcTImi9oTy%LtbJ76H zhQ-TI^71Gf3g9UKwPvKirv-bCvKbYu&+1LQ{H&PDy=#|LnwQDg-el-RefOB`)p?GH ziYXMg*SKxO&v#^N*@3oNOfS$I`6s1IAavf0nnjd_5qh-tvUwJ)tzA(;{+ZR$M)0CW zSKb!npSiiXW9ash2C8mGJkWeajhAai|J_{NIYhrwJ^EF>JQ=;J51>(34BO}MTJ`wX z_42?j#J{1AFX*38+3&;*)6ddZ7}YKolG$lUBl5?UrwZL_zX{jseMap=|!MI_4Td8`F+R0K)^x_>Qt2iB}$n9OxuEf6$baN-(ZUn8|IArC+NaAE=u2aMV`0TTocOTZE8c2WY40(7kOihkmR{dApMq4rBoU8X(0oc09Ko|4d>BwGE@RUX=t%V|#$ z?Y|S+Q$>4cIG=QHw5OHRo-W!`6WTLHyE^Zc-DsEBzR!*QTj%yJ%W+nDg0q$2v?Rf~ zN}%7l$Ro#jqV)xGetC`yl;iXy$3@Dae@CAu$HnEemx%U^g!VGg>US0L&|WTDKlCfg zb6lw$XC^tWR*vU_{@t@xH&$WETr1kM5?b3-)ZyZgGSlsvN-vok%4u&D?b!+K%>esL zWO)?1MZp!Po{2x(P%$?9rGQ)2J4^gpGq{c5Abz`mKe5~nD4df_=T7C&&l%;J&Rq)b z@^tQ2@4SZGLvWbRy#jtZ_W=s$CewL9IrMkpI-5={$sSa2m#6cPdS^|??Rrhu*TV#d z={zFfr}HR)Eyf<|+R~!y$Rb=)>9kJxX?7*I`r1&c!8F$1b{!_ryOcT-6_J3GCn-dPuU_trgK|L+qVT=_u2oA)80a7m)($I4N$A}_5z zEpz1)^^Vv6(^S&VO5w9ANpoobc`9jV+JB+mS$9IUwEvRep#4_@Ui+^Bh07A{zg3P3 z?Jw^{`|s2{UiPX#XQLL6DyWydXaV3Rfh8{Gx0Xf?U~&Ait`2ydb}& zl6EG@?^TlK5abVNf*^kictQRG6s}4HY2X)BDh0W^6G0l)J6@0;sid6=(o`jB4ncaR zl6JN_d#QKcGh=UpgZ6y{y!L$og=-S+`zc37F<#q=_Wjj6Ui$&5q@8I$X_cfow4W@M zv@`7os(0Qq;~;{A_Jaky_Co-L>k{oJSB?tpukS?rDbzb&`zcdNJJWuuDoJx_KQ%N# zkZA&TeL2m9ukXgz}Tgpji73nPrX(2^=YbT_$my^y>PC8Pgwt_3pGpaG1cN0)7IE0Sb2~ z6IenyDkc!V<*M>VW=ZwV8d0q`u}f(XUecun{D_tT6z)kzw5)PejOgA@BwbFu(~|yO zqr8?^T0e#r1pFAZd51UB9_qbli{5wYjkLYv)H~OPlD*&5VPnbOGU~8L$=(*~u&HG4 z>~z?(WN%A!*sElB$vW&^vin0F_9@w&kq-No>_V->NlJFz&|$xloiTOTzhvhM9S$hj z3fJMJC0my|oUCL^Lx%%PR-HN=R5G7+IJjg2>rJ<&TJRHH1yKH`dn*5?`$#5lZ@O1i z_xloeRui~C0jmQt%b`|*u0imqBNC=HMf*Sk))sBn$IP{8*AcCEc-`_G>nX>BNsbMa zBkzZ08*YtcTE&~Dom z+FEZCw^MM%qV4RiYy0v+?4UtBnhatm@nn6tTWb(IcWV&4sCSl(wXE8e;9%8m0=|-W z2NWJlrn9GVTpBKb)jzAQm1D2+9DA4N*he`YPjc+199fdp%CWzKyX@Nm>YXK7Eq4wi zI7oJofS0TdPZ!w?CA-M!uvf`0Ogijcvde=G z`;_d|s>8k|I|J%)l9HW0bl9(CYe|RwOIGqa98j{#)ZwHhDbkYj;!lpt@kJomFIZ4JjWx-@oJLeG39tOV?EW9>~RHGT%>xpu&btOlwi_q)kIo>GG@uqUTk>q$=IVuG1?9-ul%1PfXCw)((ZziN4 zh&1n_|FAsAN98#_25?32TIrnGqVuD!2zF-F8MdKh=S3Yhmh9A~!yY9&ed(~NWQ$pc zJxjLcbl9t8^{T_(B{M*WeM+X24*QmDb~+FA99eIp zYvuU0JjZY4Ieu4;_mUicDo56duvU)0%4z==?fVIB;}B@GPDr(Adk`E{ZvqrPNN9VB zHmm4sT^f3e)~nv9JV#&U_%O-QPdTp0xHQxndjIkq1IlwusvI9BIR+|6);wyRuLmi( z;&js4f{}IGN6r%8~Vfbvt{%y#N)>|gv;y4bmI z7P@r39$MUlKT~*NBFSvL9Gos#pMv#aKyw1i$1sbHp-=zO$3tR6n2R2T&qYc1xdpyR zz`TIW^GmHtpO4@$sQCqsOK2BRjxQ6ikaA?5Y-;5wmeVdQ+OHDY(W1?}NEZ>UKiQPZ zb1bSHUne;hSB|WcO|79XQJ!PT@*GPk$2UoiWt1c9{b{WnW6E&IuY%G~yI_yz0jdj>mGAVS}vt%RI5)gO6Gyfl;y!>YKOW<2g(CTkx zCGYYnaTWE>s+U@~u&WXrj9m?Y2H$BQg^9yiy}ZvF)~8^7nA)0x+QILNBi9c8whbYH zYXhEa{=)3$*I&CC)A~K5@xP(FiR(BAU)<4uMV?xIrn%)89@^EBJ^9)q*4Pww=1<&c zZ~sOmyw0}xTYPO@nlmGW-9t;Bx73tCR6L5diY%rzw+Q` zwg&y$)x-=&H(i^Yh}PuQLQjy!w>Dr@j|8lvmR<>17try7rCed3f4lO*Y;P`OxV!8Q^H$}|TZ_40!n}=`JFMaEFmGGVyd8jL>`O(Z)uNKp z&-_|3*)GbGRgbNflG&}p9wqZfhfO6DREIrFrhpE6m2Aj5t0_&vC)r*(bslK68Rc6% zJ3#{Rjy&1o5oYl`V2fuU#I2L+p+66P-R$B*c6Cp?xu@NEYMF*!?Fy>$OWAv3*iD?g-?BGC^gyD@b8hg7O@>CBY=WmflT zh@4FQGOOiA?fp^PoH|gl520(zt~_-39rA-{95tO3C!`I)KM3{=T-NpKIK^k%wwp-u z+vdU}ZF3~G|9Gn^%zemHO=`9FYc3iI^FEY$n}FjbfC;#JTEN3;3<6F7AfRVB0tnI3 ziq95sk2nEcc#MGj&YC01UH2}$K6P)oQTrIwHrtMq>}K1ZY1@vcG1ztj0NXsni9m=> zR(!T?d&Sx2!Xs^SB$0J*B+UC1=4}F=DgjKuz0(4oMq?20bN~W+hBJT=ovrw60r!a$ z(1phc$Zz~PlH7Ig!s}D_mK(LtL2a|`Jjrgh?VGmkd>Vso7XYx$Gh7IS=wiiZ+qPev zZ7w|0Hb)X!_eR3JFJay$;AIlP1l&I@;N>(10j~fcpl7%e2+=i)&ld22I00RFjDRDX zi;g6B-MjGm)V<|K?Q2onY`b2vn{5ZCZM%WSVB3uVZ1W5^0U^3Y@!7T=6la?YkF?E^ zMAp5LFz;KLw+YxT0ZhQQw1BtM7zDfnfPkLiP9Q}0C_Y=jgX08r;V}Zv*<5rax$EAA z*Qf3+H)`LD+GgARlHF`OByHORGzQxq1YnzIcnAp5BZ|+qZCspfE;}XCGJTxuf6Ep?^p9CPFXLt$-(X)!r7Vxk*0bO{EfO9n$9ZBxGcj5J^d&`a5 z&!M*2_JU+L+s3DDdy&Rq+e-j!^9(NoA$nEu*|r@XXPXO;w9S!3*1eH1@7I{O3HXKt zFaal|1$>jnAmCd71oRAV10i}(@!0|%5htJvj}dTebJ3CHu6q|=pSri)sQo@_n{6LT zcC+osv~3^J7;O6(fNh@P6CgyNDL&h_qvC9H;gPmElE}I@66XCm^ELs$lmI5+(P;s{ zqA>{gH2?uU!#6;PzE^yx;GN${X6qE0soW$CgAaD0so>g2>3Su z0X;**(5+FqV6`x)AC&k(3!Xs^SB$0J*B+PpN^ELq|lK>{*$!P%x(ij9B1VBK~Fc=8Y z=ty$cy$i2T-CJ(dZb5CcZ8phnww;l-tw3Y2ZFT^*d4@TF5Va~k+qN^~ zY;)m}wmFi>x;GN$Jty-v0q2$gCg53V0q3DH2skeQ0X@TfK!_Gpe71mR#|h}dV+35b zx#&o8*S!m`Pu*K?)Lsa+&9;RlyV-V5+O|AbGzI~e0wADgSQ=P$7tb;@6wa4mV(l$pDxjKx5d9TL2O~BP9fC+eUTEI1E3<9nRKtRv177(I!6`w8OC2<0}@E8Hv z#p6hF*S!m`Pu*K?)Lsv@&9)6ByV-VW+O`d847P0qz&6jYF%Y6n6`yU}WpTE-@JQPn zNo3s{3G?2Jd7FS+NB|S?^0a_k(ijBX3V?u~VQU~n+bKR~+Z;(`-5Uw>K8$&rfQL%} z6Y%=9fD>p80v-WCK+kX_5TaugpDo}GaRR#V7y;SE<4AJXy$i2T-CJ(dJ{Gmjw&NxH z5JYXcF>TukGzQyF1YnzII0*>RDT>dw?WQ=}TzI5yjwG_~jf8psn|Ygnr%3=4@aD9D zr_&e&JOhA$p5aU&MCT|zTfkf51a#ps0sv>7ha#bx7?_GE^3=?=Sz08?bfty z7tk1NyAXhFp5Y=OM3*Q&+qT={Y;)m}wmFi>x;GN$eJS%c0WX&TCSZG7z$<7B0$vF~ zK+kX$5Ta`ppDp0+aRR#V7y;SE<4AJXy$i2T-CJ(dz7Dm`wi_h7*>*?Twi{^-w%r84 zHqUS~5TaWZpKaTnakjbeNZTAqWZfGH^S+IFn}D}V02A=8w19We7zDf%fPkLiE+9nr zDn47lyW<3O;V}ZTi^q}Vu6q|=pSri)sC^%5n{5wBcC+oCv~3U47;Jk8fNh@PVIV}0 zDn8q`d*f_#;gPmElE}I@66XCF^ELsWkN_s&eQ5!oq%jEi6aWD|!_z>Bo>P3bfcM7< z=)z+JWEYPk$zAs@ygqerxl#Lh)Hd5*lLwZ4buT z=E5Uwb0m>?jXz9|7rz=zTTzC~jY@NEDBdWLs^5WTPXYylsR6VQdn2*@rT zN0PhlU3h)!-g2Y%2dHhfeI(h)uG1_ZQ6D1pG<@n1GL^1^k-EAmBFu1oRBw0wMZA@!0}C9w(p+j}eevJdPxH-MjGm z)V<|K?H^IwZ2MWVn{7{|ZTk<6!M0xj*yb621w!<@;!g8>NW8HNC>?&29rL*aP|MxMz5JWa(@mdrhxi!a2cf_^Z?BD3^M>BYF2#4>cF;_;%sx_k+wOK$kkya z%zGy0Z2}IL04CteX#q#j7zCUdfPkK179d2kDLz}kSK?913*B}uq+Uw6%?N>;5%^wy6_kQ*~Q~Xa@V~JuTR}uZq!~8wavEwlk8^OyJ_22 zqA}REG635=!zw_CR#SYoZSTd|=E5Uwb0m>+lar?lZ8?_HaZL_USvYTyRrfoZz#$eka0BrLNq%qib5&+vg!^uF1{;l|I+rEpl&4owW=13yz z-bk4Dsm$91JY52qfZwMDJcGs{;F$mf^bBVKAv#y_*#iC$C!h`*JVrov@i>y)b??IKQ}>n|wXa8Q zv+YL7ZnpiBw(TYwgKakhu+1~v0)*%`#b?|0Yn*K^JkmBt5?S{~!o1s=w+VQM1TX=A zOAB}>jX}V>00`(A?gm11pW?Fx{5?)U7ak)ZyLcQ)?z(s3^{IQyjoSC4w%PWeWH;OX zNZa-hjls5u0odjl9sxr1nBuc-`!miq7anPwBZ;hgBVpc;Gj9{{NeN&A{*@N+DH?-- zPXiFpGdu%?=y}Cw3;1`OfG#{nKz8vslH7Ig!s}D_mK(KSKy9<_CCP5KHC&han?Wzr z7;Jk5fNh@PRUkyKD?Zz{M#v-nW{?Yyw9S!3*1eH1?>CsY3HX)-Fadj{1$>*vAmBRy z1oRB=0;}%gd5?xdlLRBr`v9Ik;;9QV_l%R-g~!OuE*?jcdv&<*`m7GijoKfhwwe2> zWH)nrrOo|}#$fK}0L=9aUjQNcO7YpNqj#KbEuaeztnsv> z7ha#bx7?^b8nw-~l4LjArb*kjD2>6k#Q@mm85RdZw4~y*ZJRdEHWwagnz-0jl=oyv+LbRgdvjvB;Z8M~8TbagS+bRHT^9-v3A^Ml%vu&F(&NdewX`3U7ta~G2-m5cj6L3ul zU;;L$1zd~9AmG{n1oRB+03ljm@!0~-6epkyj}eevJdPxH-MjGm)V<|K?F~@dY}-h( zn{C6=wrxyfux%3nwt0q4fe>x3_-xyT$Jyq>BW-gek#%n*%zF#wZ31p30ZhOVX#uyU zF$lN~00BM2wm^t>P<*z4Gsg+&!eazv7mp*!UH2}$K6P)oQF}+!HrsZV>}K06Y1?+8 zG1#^%0NXsnZa|3kP<*y+EpfKF@JQPnNo3s{3G?2Qd7FTHO8^sa*0g~8&=>^V7l44C zVLu>52P!^Wz}eyibm1`qvWv%&wDt!dj%qA}QZG635=!zn)uG1_vOsn1iVrLn1J)81-y#JAmG&i1oRBo0ITlext4~){1S{j*8zCCk*6$~ zo0^LY#L4W!V`OF*k0Z&wI$U^tR)^(A?VC{B%)Ldjo4E_7&ApYzVD4=I%=HZIK#1;8 ze8%d)wuRzsbK#M;Ig-fLVI<7^PUdX_-Yo%4z+zg!duR*--U~oL&u||Qq6Zb9E#Sg& z0=n=R0oldlNOIS`3$IVzTW-{T2(`_&M1y1Y9I7;IlLa0iOdPpl5g<2+>Q5&la#0C!hhndsVWVZHuODdyU3m+v@;q^9*kQA$m*k*|sefXPXO;w9S!3 z*1eH1@3)z^3HYuAFaZ}&3-}(5LBRI`2+x9t)!L}~|*yb6&1VZ$+;` zZxir4319*)ofhzW8iRm801(hK{0M~TKZ?&5aG5v(U3iRu?Ba1Gx$EAA*Qf3+H){Wa z+Gg8tlHF_@leX=58iQ?r0IyGzI~C0uazM^a4WESMk{bE*~eL3y%?yT|AB?cip@2`qaJUM(s&Z+v>i*WVgCs zA#K|L8iQ?<0^L*t(LZJP8x%4a{;i;Gt3Qy zXkNu<+xD+G+gy00ZH^?e?u~?b&&Rw?zy&0L3AlP%zy)ax0xkqVK+jMFLNr?O*#fQ+ zC!hAzDiD*|x0} zXPXO;w9S!3*1eH1@1>cy2{=Xqn1E}i1zeWKAmDNU1oRBc10fo#_-p~!i4)L;#|X$S z9!HY9?p=6&>fUmr_Wz-_*|xG|H`~@t+qMdg!M0Ta*yb5l146XA;9%-8+ ziL84gVcu&nZxe7W319-QpB8X!8iRoA01(hKtP6x_1I1?xxIvtNE<8p+cJVlp+;#85 z>r?lZ8?`q?ZL@7-$!@l7n6_;b8iQ?{0x;GN$eJ1lZ0ne5I zCg2Wf0nec^2zV|40X@TcK!`3>e71l)#tG=cV+3Ruk0Z%l_b$9Xb#J**`y$jf+b)sp zX4_6_+b*Rs*mfBJ+dRYNK!~nXe70>n$Jyq>BW-gek#%n*%=;?lZ312+0ZhPM(gI#f zV-WB<00Mf3>wys6r1)$Bca0O!g~tfUE*?jcyY5|hed^wFqxQ|HZMNMi+0C}y(ze}3 zW3a6qfNh@Pb|6G|Dn8q`-Q#R?;gPmElE}I@66Spu^ELtRkpL#(9%%vZr7;M29{>S8 z!~H;r9#VX^fP2OX=)z+JWEYPk$zAs@ygqerxl#LJ)Hd55mF#BQUTNDNqcPa_H~`x` z!xKP=o>F|aZF|Sr=E5Uwb0m>)uG1_dCqn1bj~dn1BbQ1$>{zAm9f81oR9a0wMZD@!0|%7$=|$ zj}eevJdPxH-MjGm)V<|K?N3qLZ2MfYn{5ZBZTo`8VB41fZ1W6X0U`QE@!7Vu#o6Y< zBW-gek#%n*%==sBZ32ET0ZhPy(*piLV-WC100Mf3pMVhkqWEk94~Y}dg~tfUE*?jc zyY5|hed^wFqxP?;ZMOX`+0C|bY1{swG1&Ge0NXsnUqFZ&rtXq$hsN3F!Xs^SB$0J* zB+R>!d7FSu62JsJEG=M98iRnn00`(AdIKSvMDf{mKR!-C7ak)ZyLcQ)?z(s3^{IQy zjoSTC+iV*k+0C}Y)3!}YW3X*90JeFCfk21`D?Zz{330Z$@JQPnNo3s{3G*JpyiLH# zC4dQdL|VWpXbb{Q2|z&4FclD@X%(L>;E{0xy6_kQ*~Q~Xa@V~JuTR}uZq%L*wavB} zB)i#mRNA%~X$-bC1F+3A%mjpJxZ<;IJ37ub7anPwBZ;hgBVpbnn70Wyiv%zMk4X#I zLSqncRsaHehS`7+&7t^g0gsIn(1phc$Sxj7lDqC*czx>La-;T0)Hd7Zl>pw z8I}Y>w6x;0Z96&6HWwagnq-C<@Qk#8>(Lkl zTpxgdo?!zZL>ntUTfj5p1a#ps0sv>7ha#bx7?_`32K{dn@M)F?X0wIo6{I< z+X8@Xo?%NML|ZF9+qSdgY;)m}wmFi>x;GN$y$$m=0k@L?Cg3?~0k@|y2)F|P0X@Tx zK!|oxe71n+#tG=cV+3Ruk0Z%l_b$9Xb#J**dsoyp+jf`iX4`pb+xDO_*tRDC+dRWw zK#2BHe70@p$Jyq>BW-gek#%n*%zIzvZ36Bu0ZhOP(gGepV-WB_00Mf3gMbhnqWEk9 zFN_n=g~tfUE*?jcyY5|hed^wFqxLw|Hro!9>}K0VY1_ur7;HNnfNh>(0uZ7j6`yU} z#c{T|@JQPnNo3s{3G+URd7FU8NB|S?lC*%w(ij9h4uF83;dmfKCn-K#z)RxAmv(1G^+U7_i>)uG1 z_tnhX1iV%Pn1I)$1-y>NAmH@?1oR9y03o_r@!0}i8z-O(j}eevJdPxH-MjGm)V<|K z?ORaWY`aaen{C&nZEL47*mgSr+dRV^K#1;Ae70@Z$Jyq>BW-gek#%n*%=>QUZ35ma z0ZhOf(gNN`V-WCu00Mf32Y?VgtoUpJZ;TVrg~tfUE*?jcyY5|hed^wFqxK`HZMHoo z+0C|_(zZQLW3cTB0JeFCCxH+>t@v!)ZjQ6fg-6=vNFwXrNSOCC%-aNfP6C*Kx1)uG1_jk0ZhRA(*pLQF$mZjfPkK%4-le$iqEe52jT>D z;V}ZTi^q}Vu6q|=pSri)sNEm6&9+G;yV>?&+P2AP47LpfV4G(c1cYda;)nO#eyM=k1fU`*e6Yz<&fCUdglJC1XAAgboPaJo zMnHD)IFj6T@51X-_m&&A=R$3>Z63*Pwmp@$ZC)CKZSw)J%`?moglIvV z(l$pDS@%Z5ycc5LCg8#nzyy3IE#N2`gMgy}2q!6;@RhWH>(dwn+yH=po?$~EM4Ko+TfkT21a#ps0sv>7ha#bx7?_`DQcT- zn@e`H?X|RRThJJ6+Y*3no?$B>MB6An+qT!^Y;)m}wmFi>x;GN$y)E-L0k@X`Cg2-s z0e7G=2)H8v0X@S`K!|o#e71mZ#tG=cV+3Ruk0Z%l_b$9Xb#J**dpFcJ+xC#`X4_k7 z+xDa}*tQn{+dRYGK#2BLe70?G$Jyq>BW-gek#%n*%zHoPZ2}%30ZhPm(gGexV-WBl z00Mf3HXuaf6rU~NyKw@#@E8Hv#p6hF*S!m`Pu*K?)IJoo&9?E9-E4a=ZQJ2A2HPe8 zu+1|Z0fgu%#b?|0ew=MCJkmBt5?S{~!n}`W-X`F&62JufAT8i=GzI~W2OywlH~|RJ z$%@Yw@WVI(U3iRu?Ba1Gx$EAA*Qf3+H)@}P+Gg9SlHF|kC~ezmGzQyF2Vk3LI0FdL zS&GlL?c+GxTzI5yjwG_~jf8oh&Ad&(b0vTY_(@v8^JokLo)17k&u{?{qKg%uE#Rkd z0=n=R0oldlNOIS`3$IVzTW-|81hvh!%Otzm_F3At%V`X@T>-#0&u}FWqN^33ZQJK@ zwz=>~+Z;(`-5Uw>zJ__5fY(U?6Yz_)fY;L)1iS%&fS%z-AVjw)K3l*q;{0bTEP2h3<5p?KtRv%AP}NQ6rU~Nw{Zfx@E8Hv#p6hF*S!m` zPu*K?)P5AT&9=uSyV>?#+O{WX47NQ9z&6kD6cD0k6rXL|_i?tl@JQPnNo3s{3G;rI zd7FUGO8^t_hqQn%&=>@K5rBZ6;UyqMuPQ!Uz#roTbm1`qvWv%& z;D6Eren?{w@FM^MdWMgIRd?}xLPOyf2}Yhz0X%)lQSB5vVEj|>lrEbR1ar!Hqw!->GmRn){mM*MsX$*z+ z9e~0z;bHh5ShcWzprP=4QdmC%==?KJT_~(S{u_nmNIG|?v9>!dyc_P+=IXXPmK(YL zgIwm$uhPxj`7`a#Z!`vXeh1)=XZQnH)tx_SDEyVU^A~`0J*MrFJAeN-+;Jqi-Erad zai=Rouf0@@-5z>vu5K5W<;LkIoVLR1CCja_8m@0_7I0y#JVRe#)xw&DhC(A`s;GVdo(AyLg=ODEQ7w_z6GxJ}uv~b33d?dM*QCg0?hKS} z=1x=Eok27PcLoD+$1@B8R&{464TYYGJCg%QH#JXPaHrRQ!yQMG+Z`AFKXk|4u2j9+ zcV+0cmuj)wL$A$Mec5LX9jB+kX)CPhWVsbq?{r~JPh%*o82}WPjUI*>fmI8unTA52 zq_AcJ(0MpdT_~)+|Bb?OB)JRAh1aLBEH`qEKrVA<7U^d0OpKN`&@XXkb^z(-i>OX)COG zWVsdAfOKKaOJgXk`2ZA_XP6&YwXhbTp)hGuSPKG3SLCS+g*DlKqp%!F?!t26^(idN zja&;Om$@@qx|urz)9x%nV{oSgz#Y%9D6pzKi_uURl(@4vfOJdol;sXT*gDwU>0H>_ z@9mTDZU|eOtJ`JYm7&*uv)28g*XGJMbWB-B5 z1FP1=3N#dkCN;4lfX*xN)PnfST|Os{^an#2Pddrc7#LO#tcE<0-2q_zZBWxSDX`|HGPSlHToA zZ|J)+^x8fqGw=M}YVGjcZ*#jQdF{K1E{(f(cb zt_;0)F(yOrd=1tP|v(`>KB?uM0d(Gjr!Lg;3~{yW!s}DZT^V|9V~X7#dTp+5*K${eUb`5Rq1U07ZQK;s zo)nkW^4_X4tK}KfwY(3Fp_carP|KcSKVa2b-k*j-b5hF(07!QTPhF_xnc`~Mh1aK+ zyE63J^;dM^ofkyy@QjmN?e|;FN#f4m`*l*tT^V=n@Yr!vS>vcIE9ApeVphn*(uF*p z#!$$I11Mx0It&wlRSWqD8VbXcLOv2e=c9PaD&)rI;s`6`zt+C%kRfw7wEZ=Npl$Sx z?L#9P+MXUvKEAQ7?Mf0Jvnin=83RK;njxD)$7<}R(9CItj-xRsbUXlsY!)z_0IaIe zi8K^uNfbH>K<9t+l%)`#IkcEUo!4C_3c2wA;Zk?GtG<_TxjQ$v_F7G5-nqFo!XFwj zcD@M*4{d8}aQ`JTqWY<*ZYG~D`OV~6(@zY{KM&Q-z6&J3*;h#0cOi|zzKa0Z=NT>rLUftpv+bKb&OR4j zANySH-1fQfDEkfx_8A$fUykZ#-<6Wz?3*KP-&HgQ`>qCHpJ%uR2+{S5&$e%5oP935 zKK8lXx$Se|QTB}s_8A$f-+=07-%XO=>}yTicQcK_zFPp;=NWDVLUg<0v+bKR&OR4j zANySH-1fQfDEkf#_8A$f-+}68-(8a5?3*iX-`z9@`|bf?pJ%ui2+;$I&$e&wIQv|9 zee83&bKB>_qwG5@*k@#@{vfKGeGf~1vu~cXeUH!>?0Xb|eV*YlAVg0pKHI)|tmnGo!dSa9%bL*!9F8H^_NlI?0Z%6n|%wU?R$;JVBhNi?DGt70IR+`e3OR4g0hP| zZvl9Em!~e6yilCUF1$V_yWF`=cHuE5^YMd`p!R#HZRUO;+0EQy+T0Im4Ca0Wz+BJp zF%Y896ra5|7ml;dh1bV6mpiv@E}K1dY1{s$G1%5Ho!RCY z8i5e?^0NCak zh5{j)Qt{cgEfr^*3$KrDE_ZI*TzHIaZErWZ_Y2KMBSZD6P~GgCM)I3|OQ-Fdmd0S; zbO7x04ATQ4YF2!P~GesF8R&AF=_io&=~BS z8GwDBVHO}nvnf8?zGdU=bK&)|&*jc-p9_z%Z~Eqy{x8lp7hWIRT<+Yqx$qd<+TIG+I3q*#rBU7N8zcG6zLnDUElXpt zZ#e+=d4}bI5RFxQwtXwd+2_LRW1q{N+ddZ_W#5~@J|jc*|3h`NZ)M4E_N|h(ZxtGY zeX9bn&oitBglG-LXWO@GoP935KK8lXx$Se|QT9#U!@of=GE`p^)y=-OCBNCXTH3yK zXbkqP3&1|lupSVi4Hchl-@oGQbK&)|&*jc-p9_z&Z`xp=k)irVsBZRcBKgg})zkKE zN@K8ZGXVB^hRuNxZKe2Z`__oF&xO~=K9@VUeJ(u8zUhN~MuzHJqq^C*t>icR)=b;C z9gV@h?E%>58Fm0dw6o%~?OQ9(J{Mje`&{na_POvV`(_OG85yeYg6d}9Zj#^ZTRUyv z?lcDb_5fg?XV?=6(LRdLwr`y{`&@W^>~pzu+vmcg?3*UoXJn|pFRGh;`%8YaZ{4(g z2hbSoI}m_~rDuvCrksZJ!H|vTwRzpOK;ZI8-yt5M849Z2LBgv(JUs$3B-kw|y==%Dy4NJ|jc*OHtkIyIk^{eVeE4 zyMo4G-<1ID^9)x3A-Y!a+4gM_XP*nNk9{t8Zu?w#lzo#2`-}|LuS0dS?*_?l_HCKA z??xJfeK!HH&okT%gy=TKXWO?`oP935KK8lXx$Se|QT9z4>@zY{Z%1{r?+(dt_HCWE z?@k(neRlz{&okT&gy=rSXWO?;oP935KK8lXx$Se|QT7cE_8A$f-;e5M--D9h?AtbN z-$OJ8`yK{hpJ#Xk2+`w;&$e&7IQv|9ee83&bKB>_qwE_R>@zY{e*)FbzNaL=*|&Y# zzNcvn_B{i@KF{zh5TX|ppKad`arU|J`q<}k=eEytmnGo!dSa9%bKD!9F8H^|w&n?0ZM@n|(W{ z?R%HTVBdQH?DGuo10niI@!9t65@(+auaA8$cW(P!c$9s=g|BOk4AnnIb+hkN$#3@U znzrvV8iReG1F+9Cd;x^$YsF{Vw_BWjF1$YWx!k$!bKz0;{T}QyGF1Nt)y=-|B){3W zd)mJ5X$RghChK2HB8?n`}T^n&xO~=K9@VUeJ(u8z88aiMuzH*sBZQ(Nq)0$ z@3ehAX$w(o#A`&@W^>~pzu+vmcg?32b?`wmRo*GyxuZzcftd4^#?h-OxNwtWZ1+2_LRW1q{N+ddZ_WnXi!&&W`H7F0L; zW|jPAUt8L~*=P**6#&@h8Dqlq#MOk7fe3P zOzvE%PJVmPg?Fx0jd1@1et)}@8D}#`*7@%s*7!9*{;pyY-i?B*%~kz3a69?Cf;Mzi zAC2l}a!K-=$>Y-|FG^!Dc`*PcdxphtFQ;CSC5%>$A3x$@zY{Um4ZSzEvf^*>_ahzSU?9 z_WcWheV$=;AVg~^KHI*d&_N^=V&AwyO_N_-_ zuy1_;_IZX4fDmo0_-y-*jkC{%*T+7WJGXrleH~Y4i{AS+?Y5R7d zG1#{w0Q)?{PC$ruReZL6C&t<5!s}z7%bnXk7anEb#2=V6GF0CU)y=*=B){2rQrf;f zX$V-^p?Ix$ysI@4DlosJiyfZURV?-jU6wXf*QDga{ToA|Oap z6vYsNgceK!VtF-mEGSJu5djfIs(^r~NEJau6ct6fs5DWqD=Ob}?%g@N$;`c5#`m}X zeE4(coO|vm_dL&?ot-4Jv4KzKjv7Ac?g+lX113cpU4%PP4;S(^V&Lp^y=Se6yOu-=($avJ=b76q2_>4rK4yAhpAgg29e>yBf z!}ecgCUfgSR)6J&zjQsw3U~jfL)^6prv~{=P^DHFu8Cuo`FhYxN4y5wr>{ZbUZe&f zJ{5=yf=wsr1;L)T66_fmnPAUC0l~y75Mc&XTY}AmA$69YV9!CpWhAGUxtEouiy{{xO1F=E8SxQuFM@ZxYFGrxFQI;y$IbF;4Y@N3vlOJ z!Ce9)gS!+8z%?T*gK7)zau`zQ`N3TQ1?gVLAr!cHYj`OPaMh=Czk3AWs$<#jT+Lg9 zEIn#)rMp9L!>K`WZl||~aB5Jv2i_V)5Fow=hzo+PBj^Re=35E&28>Lw^-w@CGs2rt zZ3*@k45=^s3HCM=q}zx?D1zauj~0YMF!kx&?;Zic)UoUdCg^ogaPg% zXW&Zr*nlf@M-8rYcL=Tsf^P3Zw*|PnsqF&XSFPZF2qS~L2MWM7BYXta7Tk|vNL}m) zcP|vA`wWLLz+EE1)ptm}+tQ`GzC#LkKmGA+cNs+gb1lUlqVubCkAPt6SP`E+L~e9@ zAG$5T{es#qz+GwucR!2_?w3#it{LF~R0KLq{-Hn7FLMT)baw(9o;EFmL=BsCj}2@h zH@bZU-4?JNqqYm!mRn)_3Py(QI26EUM)(>k0-YfL(6Fs=2Agzu0vnz-ErUc2n{!gdBmhV45jfX$3>7AgXrBmdB_t#k&Pbaw(9o;EFmL=BsC zj}2@hH@bZu-4?L@L~R$at+K-QGmH$|FHiuR8R1u`2=oW}hlXvnGuWiN6WD^DHZ6li z4WD$64SXUuy8b7+F5vr%+ArXH-3s5|Ffx4qKmmMago{uS$Xz=u_|`asPr5sTFYvT! z87yk}qiK54tYki>LMr_|{tCD+VLOR~!o9Gb5CMia@2vKlJWf=L|mS?gTzO zZCVD28aC-38`wl{bh|XVEnq84Z5Ob;VTJ8d7#X&5Pym}5p*&Osszm;wVO#GEHtFsJ zHau-w28kLr=^h){L~eAuGP*5bt4eJbu)S%8ts0CBTXiUa&5Te3DgxCe|Io0#R@v3g9y%q(McX|B!!Z z_%=F&Pr5sTuQtOcgGCLWbdL>uA~(8T4_z1VHK6tj_%>PLYX~F5*9Z#WGb3CB6@k*p zKQw%soxvyF9l;lP*1HTAHGI-NHt>nu==!zjx`3}4wO_!u#R}hbFfx4CLjindgd3nD zPz&-84c}I0@JV+^@CBarE`vo4pLCB6d?Gix-V$9G@U^D)3;4EK;cEjU!`BuH;4>q% zgNi^mlYeOV-gO3_baw<_;92i7Sk&-I_t?NEa--`V&~*V{Cu+ZdZ@U$~TVQ1PIzs_` zW`r(K5vUvahlcMxXYfgPNALxn^)7=&4WD$64SXUuy51dK7x49@_6zuSSmC=3MuzWp zD1gt5&mCvv0fccJS7zCP4`0pI&p`0jy` z;md#m_{<1>p(0Qg`GrSLq(wb$v-rFdz`^1-5tRfc-FfN7Bzg*JvQ)(-01p9bX~yrAhln> z_mLI8hhSv*9)<$=%n1L5ia-VA9~!=ooxvyF9l;lP*1HTAHGI-NHt>nu==vyhUBEYn z+ArYSYlUwtj11p6D1gt5FdixbJx2ba;rqlHeA3+!e1T`Z%V1H%C*5NMpU91_KaQ>o z_@1Qp3-~^@!Z!&8ovF`;FIo-;0rwKT?UI9KItAC z_(X1WeF3^I;CqGIFW~#q3g03a8NOGc06sIqVyFnTjQm5xcfc8Z(%lh!foHwTU{S*- z-D3lv$c?TqN7n^>uTlF2dsXZghPox-Q_`MeP^xePxC30~i^;-B19Z8R0{y2=p=ehlcOCGx(&t zBlrT(dY8eXhEKZ320oD+UEhnY3-~^z_6zvFw!-%rj11pCD1gt5@Htcj`jY%Z!}pCd z_@uid_yW&*m%*ZjPrAnjK9L(;KY*?a_zqF~1$^IH;X4c?!*>J<;4>o}g^EDO$v-rF zC!E12-5tRfc-FfN7Bzg*JvQ)(-01q(=(>RKTWY_6@1zyJ6EHG-C!qj7Gr}pT2=pEK zhlcNzGx(&tBlrT(dY8eXhEKZ320oD+T|bMi3;2GZ_6ztmCvv0fzoP2`zTc_+0>1C8@cjWJ!}li?z-LCd z02P7$A^*_uoplDEbaw<_;92i7Sk&-I_t?NEa--`P(RBfzahVC<_g47aFfx1|D1gt5 z5C;{3ij#k6_mCvv0fCD3&NUrB1e*nQ`$@Rfp*;VTUV z@Rjb)9yw?UiT*_5&Nkt%?-D|_dG4Ce23O+0kl8kSWuXaz- zJF1uIXA8(x8RQaNu1YKuT>i<*+QwV+^f0uEtt z`4?wgmhQ3PayX@{fk}_JbakwVxg1XEYBKsu*HcpM?tsgpZjj3datSUc5z7RZf3@hRflUuI68Q#HFiaMa<=J zN>`K7UwRCL(<#GcUnad5KfXiltMo?|Jd<_h#fBL!H7z)xg z!yybVUvS1{=^h&{hf}(mf9VmIu8tKkm%}Mt!)56n11^iiAlG#um*DaZ#4^F$Wx|?wb#brEI?jL7dmhS&UE>|X=*gtSIoYK|& z^RHY_2(^2NH){3Ag78|dA+lVyzHYU<t()l<7!J5cdwSOrNPXv-F07&00+nETX)KE7DxA*wZ5}T^%dpof1yznw=7H>FQWfmLBzHk)=D?EXC?b=)mzu!Ev!!MiJS?W+`sn zETduM%`yfGHj5|&5ynEr;R*5&y;({)+bq&OHk&1!($xe{kGOPotcV#GPU&ibM_#%* zR+Objy;#ZN@h8D?v00uXvWv}fiFLC)4I^)s$xyIaL>Y)M1u70R$v^aF zDd}vpNcY%mmT*c}6FfcQ($%pdW?VR>s|g-?>FQWfmLBzHkt=tySxVHA>j%f51INW? znMGt5o28U>v%CN!ZuxV@1rk za7tGbJo3`jv7#(J>dhio?qsuEQb(>I9A5~Ii_Nl#$SyWZ8S7?w6-M4Hi=kk%h%yji z2~-?bk$>pTQr6jKk?yhCEa8-{CU|U&^x7^vz;Q{W3yAjDP7I( z^oUDW$BKBTgj2d^r$k)3I#!gWN4;5O=}tCFnK}|WaC{RuE;h>+BD>fu<*l1#D~!BZ zwn4#W5oI94yHIiXfc!&mmI}@`i*%38W(lWsHNn#(E?pffV#bA2x|-mTm#&T#W$96G z7P)dKo26_WxqfhbH#jaf%N`=T*en&To8==Id9!>B1)D{bfe3q{;;^6mLvNN!&Nhp5 zkIiNYr*t*J)1|xqLPqWG;8#V$sawtNu}*;?mWz>`&hgOIL4*$V*qpvM*i!28QidbIP_wy``kPlP!g>1s6fU@l)Wq z*ivVR>|#q*vu>&HVB{@z77DhM8R2`Vwp;247*ebIx70Z(NcS5KVQi@y&bE|vkIj|} zr*!o;NRPO5bu4>cYPM83rK`6=%Sh;jvpA{cii zF-9;h*~+-9U}VOnK>_2;2vAulx- z{Na?Y=8}Kq5tOcuWzWlyrR#aAIF%7E<;wNERJaFtDTC;1h@+LQFSWvOO&qh#*MnX< z;x*hF6z={S>iF3QvNi!(#ooAu;qOU4Du8tM)-jKQVyi}ahiI>t{zc&=_fxQt<4GMCHTZ6(q zus1{vAZs^}RqTx(#9Fa8uD0%to-p#>xD5*Sh8f{@s0h@D{6oJZ)OE&s=^h)_hf}(m zsp%1yu8tKk>t${|>lLSTVw`l>vtHpIV0}0>C}qQM9>pdW=V0~X=tzi9s ztgO$3ky+ml3RrJO$bxG7j?f>5)Oy5nFQWfmagB{ig%+x>H2N0a1U&2xqf{OihUVw4GQK8(DrheN@(HY1FHYP+rPhat70e_M})f^?&B2xD6}a<;9ddu+CK zIHjw%VtT}-t7ApHH^M1hy%i%bT^%dR()C+Pu`g*$$(1|Y)-s5`2F1P%w+4lKU|WkC zu+K(gpNVZfmNuN&*4J3K^*9)LTaSl=ZEZ%F0M&L|PlO@0v42}X1_kLJ$05|V#`8^@ zh;6O!koq&1-(8QA!aZ>E6*ZvbCs4BJ&?Kr|bST~0p{HQv4m}M89Wo+jH1C`dO0hfp2D({P)L4n_UgBI*7=Jn?CMm>f>&>XVg!R8d04t~u9zXYA1C!z^DH?z`t7K}{i7odR70yjjM4b_&;FT#*|ouAHgpkVULID|px z>z&bAx<|kX#qP)HHR8sGQ@Wah=@FN%j`cq&T}{ErOIOE=u5|Eg0r(~8{0b3G(D?={ zofpB#bbb{I=qwtK2#cZG(s>CCsW?zO~LetOIOE=m=ocYuBKq*rK@8_S33B$5&RN#-b_Rj zbZ%{>^A;GH&Rd~?&SLS1unnp$o!^BawT++7+o53cdpLxmGd^9k6?BgJ(}i?*^6A2? z0VVH1$)ZE=Q|+Qd?W`Tz1tWLp11RW_C<768L&f1k@(=Md0_45P+1jPMleN43HK61@ zC|RuiW2#-Oy}fnqdtv0Ye*y(-7iA#Ar%-L#@fi%MH`7`%YabLG4&V@~L-=IX!C8l- zyOR!;Gi%U)x>KKN{7Z=7gsYAf@z$5?*O#t7(?njnI#zV0gD3|<6v4~G#2CTLj#geC zfsuK66bg7L7LN$WpyKc?`G?q(U|c6>jFaw87>9>s${>2!)GYD4$A)p?l&)q;MWFNKADVHUoiR?jJ7FB2awLO9 z%{b{E8^(oGx|${al}AvzI#$Gt6QzSFKY}QNaX%Ad1mn6`8TSi}%(!2nfN^Go-=HGU zU*sQ}akn~SoOE}>xN3FMWss;DC*31}O?|$M7`AXqSF^;w@(4;-$BM3W5an+WMKJCn zF-9=1tCevsZxG`QC}5meJR-QE;!qriFc{a(8RMk86UO06R|biiand~k*#1Svg;Tnk zCH|F1P`Wx+#EcWAgD53H6v4QX#2CT2?pDT?f|1X0rJ;avW`r_O5vT(Bhd#&kaK68t>C7?$lzWL1>l+y>Ow`J`s5$_ zbkf@yY|`BcY`762gG3FRbdL>eA~(9-0Noa_HKMi)*zU5zb`6XSTVp7I&5Y0lDgren z|Io1A?F=^Q?gTb`nwLSMhE2N11~!o!-EM|%3)rrwwhP$$SYf*XMuzQ1D1gn3&>SiP zwIct}u-)SfHtFsJHhd(OL869Dy2l1KksIA^jcyCr+EUvEY#CPA+QG=M-2?@&nGxDU zMWBx49~!p4&R~=7PGH05N*N?-*ra=GU=z8~?M~>nfUPsNUBH%Ug{=#W4BM?x0Gk=1 zD^vvPLH?m(>*owM>FxwJd^nRqqJ~Yn#|Ac$8{O`SZVT9Mr?v~&vaGQ6f{|gn0}5a> zBisoUf$k>%(6IG)2Agzu0vkTz$RJU}Cf#ELo5+oB_d&M>Y#G#c0o%P+*!sfAuw_C4 zY-WUhP;EaZWWkU+fM7zN{!nljfI}#7aT?1O;Od`Zss2s9hT~i0_b`J*jgGA0e~6A; zfbA3XL~gVz8|@P445GdXbOu_{84M$%GXx6IF(V9xYKu+|45@?s=nR8`bi;87g${l! zIar{hZ>$;}zk39YRmZabbgXG?IHjvUuSH(EI#!gW>wh^#eILPJy8eWxa1Z?IyJ#PX zG6F;qyc|i45xg8?<>dn~GA|#50$!RC9)gNM1>_(4WIxmym zyA#IYOelhYD9?c?f^oBmF@kaVR>r*mBQtI`6fn+=@FG;(GvOQJecHR2*I-|IlZ`k<6ei68Mg)s7-vRU z3l)LhBLC2gd(au+sUHbX_A?Kp(NxQCrFPP#i`9DWicgG9|Z=^g=W|03hU zDP7GH|H>mMT^%c8#);BFl=nas!ML5o7{R#zS{e5~jLf)QP{24d!Us?h=wtE^eU5v? z8RMk86UO20uM843FgS3#W87OZ+R3pmcSth#4nJ2T}HdD1vdH5@Q789k1`=EevW`xh7BG5td56!p&XN;5XP8f&JRx(J`jFavW!1gaPE}YWUEb*^Ag3{Ho zB4(T@9Yi?j)L1f{EEMa(!+I*4)-L=lWTO^gwY8)IeM85o&y-$4Q6%m`

      5i=5x02OqwrRGgAli z6>HYfeBGM$G~c#n1I_oW*+^5~@RNpSqbYAtiP?pwyz3)oSDNy|hnU@H%BTKfcBd(y zs){)~P5Ed|%pNrVwe9w#DIb7H?i@7bNxGPG(v&BrV)mjbPqoDCO;c{_C*m&dvHXY|t~) zYwh}ZP-*SDw!s54nThycb_i}uTl4cH%@1VKpUHeo`ZAdt$%M7%Lcs-amhFbx_f9)v zSf*{VwWnDOa|)kj{|=jx^rti9aQfF@>gV^~i7g&#W&m5O7Tf@c;-p)q>e;d9sZ zvOa>whnLJ{qwUoK=GiIiGj6{#Z65nf53uB^0oyX?)GRy?-nMO73P@&Bm)tlW!E6MM z*#TC;Rp2d4Z|hH+`b*CO%D|>KO&Gyu1L7iV*!BqYEa2HF{TrWMn654Rr3yOj$`x6u zWVhf$P@fFZq|XtW}C%GSjvi=MdKtEEntJpU)mZ1kR@kqflhL z&l)&cc2yjcRFN{K#^@uuHe^;FZ$(;-4j|GZIChXoi!(zr|}2uONBKsK*|VeGJ!yABF1Y42wgeZ`(IhjeL3Rsr zm7LYxg4Yjwg$>{YhxMgnp^Z3rapTtf8MlVp1HjuOKYME!y00K~NsJe_ABOU*CuexJ z|8;el5ro<^cy{m5Y(FgrRg9N6n|QW@csV;L`+5`WzAhQ^Wz3*#SgGwe5R&2pg5s}8 z@mHFBvJR)o?ZYOF2lw4jR8%?(S+l&S5|#F5#k#h=aG1yw+ED32IBd46ciDWW9X}vM6^2K8sJAdPz_2O2SM2!kNs-Bl--DT)bnY>SP1c7%kOP zwh%3su!WpyXMblqiU$hYt$VB;g-y^-PTE0F4nPYc>P6DES=^|KsE5J@JRO3Ah)Nrx zUIT}%`KyuUuVivLlS`2pWv8K>&nzl?J&r+jMugA8qAe>JZ5xVJlVIxZM@!Y~rMh+R z87t-xuy;YRLIttcW1IcD2RfqPCx9KniO`UP?X|s zoG#tSNjETNXV7fO$(X@BlP2%hX0V$Tt-t59VqM$WILJ8D#w2(M4qNjNAkE*$ zF}ah;?M!ZEax)S$F)j#vT^JlL#=&P9?k5=AZM_?KyO_xgpEmWKrjgU8-WtGsz`*|i ze@ytprsii*E#PwrP8b1geC9ZYTMt^@cvmRL*yOqlJ_n&smlAJmG^EIiOSn(_a zIVuiByBB$oSKPq74`z{u!0%_VhMYt<%m?W)J_;{|qwuiiA!l+QMXoXmnF>bXadL=E zzP2_@_a4nJlSdRE+Cw@tB*>A)>`AidkO5rCHGof%l{P<%ti>L$mOtf;r06vR6 z44}Bd$UH~0Atx%pe1SD1B8}Ncyvil5oGuLuA!#23}V})Vd|J**zrz6(n z&a!d%(Nk|8HuC7Pe=T73E)0?~k*6Q}IUBl(7qdN^Wzz z!Ua5a!9m83HpcE(w9uOW8EO7UCf_45Bh?K>vcCh!KDqI|d*w$aS=*a0)KOgF|HPp9{`RnCL!WB)Q4IK+O)AAeg z$#r%(kzNNtCB2>#F5syr4$^Dd==CkwlDFn(qMiIdO#Wi>2NKiuUO~M+IAptGFIn(W z0mH|B!DBAjIMYQa3Pya~K2%|DR_})D5_1NfhiG@A3}yuWk>@SS((?lM*%)fGLO-*U z=?N^LKVQ^gqjA{JILr>lkMLT5{Q=|7eh${oiI1rFLE^plkmfn9_W@Dw_~+{(mXfO zoaCWe7S&{^!xg$ta-|G%b0m`#Ou=jKS}-j_PNw~ES(Kl%W*FNk=rf+piWLTv#3!TM zu2=ZfFMMQ?8PeRBEWvM4mA%PbtfQKrH*9`!wRw{}3b~qiW|Y`RN*}z-t?4(K9%8R_ z8+oui`EhwT9hY{r$X4v!55CrJj)ewza zNU#EMS%4*wE7~%Qg9~^XgM%!4(HDz-yvhb^!pTR^H&- z1+0tFX9U=lcP&QX-A$)`&wG>tbZ~I5x@+nL3K|4pG z(JtKUu$hI>j0}!^5CpB(1M0Ku=#bAo;5e)~i<3aYiL4d<{EoHT7Dl#AbgI}s(HY5; zqRrHqX4VIa%foQ`&53u@sIVE@yfAYNW{5Neu#DvfDv=kk<8lz$P$jZaKqMzbq)~9* zSoO{K#x&o#ptAG@l{ZCYpSofb)w~G(0^E!qbCHidW$zQbb+Hn+HKFA6PX+LB5&APk z?czE?ZQC@kMN$LdSk7t#;JzhY$JQ>JfWj*T@!i=n`uTfGKI`c+ZU+Mt}~$62ONhrFN>2v!u?pQXhJt3 zTjGr>#wYat(Pr#~J^&~tbPN6F#Jg!UoY2cL$6$s?Q?tM_mItat=5`Y~NF{P`KxBC# zBHj@&hp4^>JACJY%F-89J`9z8>dFc2(J#O@dMq`eL&@XwjUievp$i1gnFfwXY9JiT zS#1E^r_yz7LNhoS^t?hB5JLH*P(C`LM~5054O}L408}!ekAn-eFbxL@0@|3+{Bv)u z`IXU5ejJlAOjbZ*CiGb-mt7S=@`Pqx_6`5+gg%?qS4*fKOlYn8Ijp`qt5-asqi$Uj z`dl_M9?iri^!Y%2az}?GV@UG^Sd{SsWC;{*rCN!%tjRQI%3R3mRIa`HT4D8z*j~|6 zz&BN8DWLw5rJ!YP@oOqy9Pw-D4QXB{bbX2H`U98ib;Y%*d?_kRbX-O+Mi9I7T(0`& zo7x&}$aDoN;F(p>NYD$>2w7Jl%V!Im>+6N&uVw?K=6Wb+d@3?}3+8%(f;rQ`HAxMG z!#%4FphN$q>)2dp+;To}t``tO`Rh=6V2BGS_d03wXK_2N_M;nCtwL zimmyL!79HYll7TQL}KRpeJGdR3_xreJV11Fpvfx$J+jC6XIFp+S$&Iy>cI-2Rey-p zw`BE-SAeKn*9!0mn(@i9eX?#1i!wfntms_dlz7WFOmn8pW2{b%+N*CHR)3rwD4Oeh z`(Gvv^^eZ=?ZmIC{6xgBp*N&?`_T21s_WT7Om)43xHgraLS>1Lr&TX?4lfYo8CEc1 zVi$*Jfnu%)jRd_AjZoovWcjSXxxQma{snp|HP=Hq<5Q8*TQJuP6wH|hUP@{p9PU|d z03CXnu48kZ5z5HtTrVJm@~@(NbgoMX0e=m+%=G}MWUjvj7x4534ll*{e~AbD1^F8hXmc2XQ?y2eVqM{yD4f&FU4;>Zn`Stp0+{ z?1N@v3)+`N_bo)f2I{j%?NfL^Sb?hFuu9P+=J$PMrcv0)B*u7r8*SOnk?(+F@4i3% z=ES?tA!u*$0NdjCYK#01k)y>QSi$tlw)kVv;(^klcsDJYz7AYd-Qadhc7)%)*6i#qy;w3!Rq47w{aV=VqcmQRvgehwii zfPd3VspTge7*b>O1kVXLp$e9t0#S0Nfq&U5X|mNr!&YY|wHgNCEVpVJsKZ-V@s)|Q z41JK5semhFXh8Ys%Cu)lv=O+hOaV~I%G3=m&_Wj+WM!g_mFWvvnT|p``Ke3}XL1-4 zvog(ta@lDBl2<0yW#916u1tMd{n&)+!OEmnpO@8-WA%zxrl?!j$}}IFIRVYYR;KQt`1`pIGSL2R#R0pnNYWbRS_$O6`K ziug5^=a2X`^oBH_8oC~=y5^TIRoAD9Yg2g$Dob<>r57WJT}c*Dee=tpns3O|gbLV& z1dRl}5RH(vAhLY6zzKPJNPZzUP-+PV-FlQPVp431%+_TyMI+Ua9 z*e--|3!*aD3kae7q9`Ao>k>l1M*x?(9srfh^^tG^PmAFoqe&Zc{a`#+Z_S?vR{3+7 zoW32ji~Pd~QiFDH>pnOw}|LL`RL zGC{p%aqyWL4*ZY>o3DmNmo3POlD?97&g3qS-0W3=3LiX&&dfj$lL#h}_DC`xXnOP! zjY^*mIkNcYlWk-#_Pc(e=U<4 zOr|3-GOirdYsJB5W+-FV1)Fb%MVG50D=OoS#B(Nhb>wDm0#qnt=*-9%{DBe@;fo^S z`w3`_pNOnMA2Au}(8x%(aT&*ljEs!J2!1927a0Sf5*gQl3wT-!2a%CBWIRb^^uZ*5 z2b0^F+=9f&xNcByA`U(?+hx2L7F|w4R#e8jiRVo22FT6c1E^5O(3z2O9*HaxDVA|V z`iRL$hek%Sjmx-E$jHbjjKFkb;38uHR3hW%Z~;%7;vh28hKy&6jE{gx{vjq0Fu4zj zk#UQl-c~sH%xstO30QQwHL{{IK1Muea<@fp_HjUkGKS8KjPj>_eG(~_aXb2m$w-Gr zMzW2|xP8dT$S91!bO+!fV*pelOrB=)BoZUzEg-oQo10H{R9{on$g_Q649qzxJQhb3C`Z-Ghv4JNNKc?F4)@c@+b36QCL zS%SMC{)gA6zF!F6ig3T_hBrCiMNPJQAS%iAEc%)Vo3*0(Y~Q>lLK;RU(>T^keEl=r zQocjKIph6cdS^tW=^d;OfnU*Gnyct-gTvtho({u7bf*p7Zx-D@MlbRoG5LVWdq|A# zN1$9$msq}CFjh2zvAz+EZrbB26zo%gBr+9#rAq-&Nhloy7w~kH^aLlg(Ix)We{235 zw3Gje$rnsMLt?r#EvR=K4n8y6XXFpC=<;}EMQ7x9#B(P1MC4|_2UIvCLuY12;)}f4 zd60Ykdc2} zuQmTWnB;$D@-vekkr)}z4CWUP~DB#~kn zr_)DFMmjVyl5JeZYeGgwMqvb|Gk}YX0Z@sI*TV%oU5kUrNE4wC}ctcR{CLDZbhB9LB+y@q2-i)lMjJ=8HOzy47&CUg=P{z=ikui9sl|+hVyp29$ zGSZ=uk!<5K-X1bCG72Lwy#u(&7yy;XcsE?YlaGVQNE1^bwPh4vmat8<+8gkdcv5 z7=h`Fz(vLYs6@tB;R2ps#zADH4H+-Mo5!vB#la+>XR;`h91}6;5AKEEVD%*v zs`r&h4td0?zsc%LvHIp42QSk-!k-jj2Seo_9A>G$ZK?8m2a$L0NIx7j(hj!y)U0^K z-?4lPe6SB?`gjjMe3C|6Y_ILK*)n*?dl?{c{B+{YOB2sYu8i#aq!0_b2>)o;`3ou- zp$||V&mP4M%#UWV`u~c`N4lys_c6=I9{(}A&`o*#7a5t5-lr%}70jGig53qr&w$IE z2!KlF#8+?uPha35%F)K0xKifC3TP+4Jd+kC%}C6g_!{N1V*xnl1gp5`#5b%zj`b7g zMCd3M)ZeoDN(t42IiXem-c~ONQMxP&QOZ#KP~b=Uh{af>vQMqz3)@dD9~*SaX9m5v z{Le+@DHqA{lj`E~zoL9JNXDQvhxRw%5+ngoNs#;n7x4544iY4^5hQm=kgS1r@~bgv zWwJ676C{75Ty{+WN|4A;!T79VgQQpC!ub#Duf_U_K@vKO1x;w3DC2WIZP9ATdGG6XmiS15gIJJI9lJyYj?m z-B5UY#hQcFH_@vXTwLSTgNy5&tiEYN^&m#H>b-6Cf*7I8kSh5H*GsBU93y?`BNii( z%08uv$H?3)ABz#HXJVwd{5(bFDHq9cAt^3DFUm(_WFwU3$j%2`Vk7`6iIIVD0Z;vL zkQkwj7X_W^RxaAtY2aw2}U_| z6kAA!*y;tNOqWHY%zhM)@&fb`8|6r4pPh}5audtPMw$ILqg-5mL6nb<+IA>Strr3= zqZR;_j9LyZ;AuDxGHSFjYER0j?S^*pyD-^_$&N_Os4aqW**yU$qb7fzOc@RPXUl?N zrO!}c`EG}u_KVW@Ui4jJM1%X1s1Nfo-3V5noKQXZ?wD46G241UK#)-+AeND3ixL%Y zlNYxX3Ve`O#7D4n=suR9k62Je2>2X}cu=EK)fVb=&8e>^w-_RIGW53W?2}V5h8AK-ZBMidr@yb!RtI*T_ zp{G_F2ZY9|F1Msw-zckLvGdiU&R3_u14Dmn&^RbG#+P#5=yEU>T5J2>>W7L7wf zW9?GTySbdN6Lr2W47|T)#Fv5P;PG$D$gs)E$>&y{jER_hR^j$M(u&DvRi20; zW=j{CGK69-M^ic==JGUUB*gS+igptaFC>>U)F#4U8FRB^f@czYz@JA5fJzp!jo<>! zZGeLWEp04hFUdl7B-F?s!K97Jp-9X^wlT_Oj{)E_3yP6nuO4PG*@W5CkfW?c4e=dJ zSU+}k*_73fO{m@|D~VQpb5@VdQBn`*J?H50Fr~X&pk(eOSQKGP8YhRwRy0ltjjdsz zz&1F@%L3u2NEh-K9w<_HZNqOnP%ZP33;Q3gT7HB8rsxQW6)XpM^C)a%TR5kPW`#JK zc+TW*huoIq!lK*5$ek7%JJ2{iGi7vx&j zyTZVHGo6q@;y`e|2}nO}=W`0lh=_R?O&Jq0`P|8qQ4#ZGJnHa72r=)bDN=~JD`%95 z!5PKobEfg#VF23$hgld7C!CW>@o0GcGZhzEjIU#KO02sOR zLgT<$@dr-_MLiu%Pv?i84xw>DXdLQt%YN2%*T};8VNvI8^mk$C?{FFyg~k!3oY%XY zPmMZ15(eViNFoEwL1cUjC_yRlEu$%>#J6-;Oo?wHDCWrwXpvP+iEoiZOo?yl0OOm@ z=S<^A!(bV6#gN4Wg^nRdUNHiok}JmXZ~;%p;vnHk8&{0C<%)47`kTL;$)!v#Mq;iQ zC!kz*Isl(pVfYTQSBw*xeGPJyD~7#k4L)%U>&LDbC)?@;TSvMK=PU&YwvMD(d_Qt3 zeZ;nok;*>%65l$WR#=`51n(Xd7e1YZqqEbe7NHDbfECv|6Sbn_cs1%!{j-3}I0ir^ z<9Hriz|%Q6$T-r*IDRbScq7`$U(e)PCNq$jaXcU8vbO;6nH6^6FguPHF#A^IDC1ag zQUD^>|R)+_$;&9$ui7v6o3ZYkJS`$mY3nvGECNcL-_&@O*;BXmD<*putvoLZUd z=DoyoCiez59UWX24JKXOH9y3-k%eP}#SWtaD}}cp#kFn@37ExG2*BGdz-6!kppwD5 z11{j{HXLNIXk)N`mBD%p-13hwd5FmaNX%f}iE`N|0VsnNJT_*PaIo5D7CkohS^p{4 zFY#<3c-j*>ip|QqSpDgQ>cQg)t@=H-^@2%FMn#jFG88`>xYtrB@IhK-`naDyVtX!X z9Jw!e7N(5L11On$4i-o2K^o78#zQcGJxo_Ww$A|hRihYlpCf5zKtvTk(q_S}zzbm; zkHC3!20TGLXL289)6p5=M%S4c>+f6#n5=N zsO882DlI?F$}feLpP9wV&$4`p!JQQgwx@FL64!Z^Hy^4L$Bk&xhJfO0=6qKX3iVAhl16!T2(7-hV~ z+>f_F635&k(qqo}dj$r|m{m@K42520v)m#EKqaf(n{WY7uj3%Ii8fZbnX<~gjV|Qh zWb!(bSCN=i?k$wdz6U^A<$~3PRqQHP^j5*!tp7giC$4g#qu46<4y%8VP(8*YR{cHO zdcg`sMnx+WWhh?d-nSGAe2`X|K0c(6*!mD5;8XAR>o4c~M@8i$jVa~-$MUf_=8&27 zq}cx_C?5^9cTt+*@hNZ#v;e3i(7uEVc={X%2{hUWv~KdPywA{1{u3tuWAY&q6KG$d zT=q)<&Ol=occ6XE`d_hri9ib?C3F;vly6x5>xAmT)mW?koo&4!NXRG>B*AO0l%Y7# zzPA(#e2`YeM{vKS`}mPQVu2PR;8X8-p#4--KGK*{{%4kt1saFU1X{8GUr|09XkVZ- z!{ayL5@-QXNud1&7x4544iadz5omKsp#6k)@;@;7j>$JjOrZUZa@k)2I0KDU+=2EF z>;K03iGdb6iUr!gtp0mK^&rr+>KR;2g4PRygp49V5?m)KL-Ea69eoIe0w2U8K7v5g zeKgQVEYKnZeCiz!w8o6K?Fvmr5oHW=lya{^FSwBXZWR6pX@)Jlx!lq?dv8k{E8GyI8y|!Rmt&st4y&zP`s3=q@M)6KN9RU=_8L6L0GGKD0F}&*mEi)O#^E5!(Z<~PLB7SX5ZcKPW3m8~AxO;J zXhk`nXc+$Ud!KE@7oPEHOkglFu_)lt~VW>HNAuy@@#Z%nUUcyx_7+!ir(_ zU7AM|%SjFzn}kYHb(WA^DTCY%keeL^sPM}jk!I@chfxcPWF%TVX*Z;&*c71KaJKsF zOof&yB%_~D*!4KGjvAvSbK!XNFv2DZciUE8R^i-NVahq zcL*678HEv;?g(6D41h{x+yyS+X(t>+M%s|Er^wg}Ci#__jAJqeiIH*Fpx*8{_{?mV zaSd2>xd*bMGOk8EXL9#KZgzD*g))ZDjEngU`%%8P|tJmxmxL zD&s`rIg@)BaF#sx& z@ff&(r=xHX8EHdC{w(LtSjLm+BPJsq8X3tpF5@X7BO{|Q0@G80i;MwKiHv+& z4p02Xl*mXMGV+gxwB~mNll=Bfwq>$45+ftGN~m`Z4n8y6W!wc8v(80URK}f%=S=ST z$j$Bys8GhxnUQf>iAEABmhl4mh{;HYMnLn9;E#$~)KWMpI%MqtWUoJ7U|s6@v5;R2rS#X)4G4H?IYjMKm* ze>9ULnH+({$oN1|?;#v~W`;82i|Qx9qRWSo6_xQg;yIK1C~~vM11gj;bY^4>ZWl?U zSjNZbBPJsq8X3tpF5?p+BO{|Q0@Ejfi;MwKiHy&}1w1{CgUCo5GL9D+PY09ysZ360 zav~BV<8wj17jW>I*&dB&!=lRNqN-5}%BA5QA|7kwM+MnGU%l;RD z@+?QTzY#rPru+G-KUN2 z?;+j42kqqVVsa;w+mV>=|BiCm`vEB35AKs#MeqKftQ+e-9hvU4m3a66LiuR-??VZa z{u{V-KL9G}eg-dZz|+6*B;BWt?(Z+%e+=#9A7SzklLwHP?$@DQ_DKLr_k(YZvP!i3 z^>*~@SvS^wIx^j7EAj3(pnSCZPoM-zHv*UL2S6p=?*29*UqT6z?g?DF9{`nf zzc*aK)0{X+_i3a1$4U3!LOc04n7qd16(pwnbD>=JT>wh=g9`_%=-uzby0Pxlk?B5L ziFbbWz`@;o1&4+_@pEkOGx^(|zw3Gjc$p=i{Lt?r=0Ohiu z0Z6_`ux?a`y6)!dO9Sa7rUN~)EWaPj=HfcckMdC+K1B(#9}HY{2!Kj-Xo3rP8j6GH zKpQ$NB_E%Bi+1u~Gx?Iq=SYkW!%)sA3f82C$MrwJqOS#!73&@I>!fS+5b0XWkF1h2 z6&EV-*>y*6Nukf5#iyybaACzL>F~Yy0uQ;sgK$H47J-MT_}_<=76mTi z2S6p_FAf)IA&-NIPaEQ|AmaapcJhBP`HjghNR0R+Q7)#i&m!SSgq>pfh}39i6lz5~ z@()U|`O(0oBLPrJN0xyLcv=bv=?HCfWL4=%+(||-^LEW6xMRWXmWK^6kA&nJ)i#P#Li8$ln z0xgWeLBydAan=!WdZC^C987vJ>5jyV@=7Qd>xi=A25-`{DpwEun;^ZUn}|YaeHA#1 z_HQnfAgfm3(!T(xq>0ba;(!cfK0-n~vLHb7<{o6+Rw*cD74`DJtlYvM~|0bba ztbaa>gprPyf4SDPe7qwYpjNaa!%%|FZwOpE5&)HSWK+0+r;Txtj?hL&c9D)Of_Cx? zGs!Yp5Q*u?<|voV1IYHmAHC)u{;b0vhs^H8zkvPduuR)?_;o8%4sMxQv%O3B(bPxz zhdyzIFn0i3(B0xF<+CN|A-O&qK(PjTs>2^c4sI8=WZ~$gQkeunkkBJ4wNHXL5#FS3 z4QEkpN1zH7*#@|18vvDPy8~Rn({?zBwzQ$`6w!7Ww3AO0+Z#D7!CG9xupIDKNiiZW+7lF!tdD7S-h8f!)3IWE29LtO#v>w41h{{xj$UM z)4n)JFKMHfM@uiqqn-TfOjc#G3KG-H15hrhm%$ITvud=L;qML5S-h7A!DY0UYoY|X z9SmH0832{^vJEca=};V`m$cE#lckrF&`y3mChIU+3yJCF;X%ErIQYy&KbG4VM{#l_ z(A*}lGT9B0l6qSPmQ41RjhKNpk7B7!h1N8$QJ;1VSPP)U@W z3K#HnG7d7pv=JreNR(`kcJkXY*_z3gNKBNRfpXdZ0N@XLXNDg=_2-___clB(6Jc#; zqs_!$u*W6AW^}U|!L`C>^t2fb@fy8tM({Yo)|kg;bdA^OXEVCRGX~j=Uh#~fHlueu zV?moSB%ZOb%@`Wb7-2J3jAx9r8DruZOWKS!e0QZl$maIU3}lYiT)sV%Kc*>}7}v8g zOg;w>QOxn_J*;^rSRC?mkVVM62ec#coXI_p;~NcB(b~8g!9nN9H#RPu$&7>-*$Xj1 z;*onn*ocW-X#|a52wWmJ04j;xOW^{ZF2+G3mo_5zQi!6d&slU{S;*Q^nqMa*8aM}BgjT0kKq6vPDK&s2kSx0 z88Gp?Kup6d8;g?Vvpih-^pE2L&8M?0{5{TAV^PLln(~F0gD}b{cr?nS;heaXD0{Nd zDX9jbR8SQRo5p9Uqcr}CQe6*84m&w^o z&O~B@=tY#vUIaiH$%0?9VBNxzd>Pe!R!7Eim*6OkzXCLODJ)WY6^4vo*y#&H{52N3 zEHqw+5gQxUn2$l@lWk-K;PDNua6d=kH&M9d;;@;w*yiP-@wVp1)#f`|;r@;`-;K8U z9^1SkZ1a81jf?sRT47h4A4c2!h;3dOw)sEJ&AblkA8Uo%c=dBs_$1oyr)>ACu-(rz zSFUzH*9y1s!s=-Ei)g!FvfZo0cE8eGx!V0&E9?q_Z=!8}%QmNnZGNY@akcrqR@fB; zKSbO7k!@ZRw)vCh#?|J}T47f#{Ss~SR~WddG*gH(KFgWTn@XAEGPymO$vmy|WP$kRqoB7~>2c`|4`?c#}+Jnia97kT5!#&f3W-(fJ{Y{bn<@&_66%lrXQ z$@2LRT%ftXaF7*@HkQvBat*!_z0F_G(keKE3UzCe&#Fe}DAeva!te)&dc%w{b z@zrf6Tt<6&GfI$K2H!H1UIsvWFB|Gk?>8hMdDoAZy~3$=h$eTcp-p z$eN=bBsaA!Z&ae?4czW0m2|&@b-!&1_gf>+(XlPvEpJ}3<=t(|yOd~oC%5|@OS(V6 zy5F~i`zgqCbZoM_~?=(N%zND_s5iQe-!c@9h>TES>o*!>;A+N z?vF3&<6P_GtP(!XK%Rr*X(ioXY~5c_!u@$AeN4ALt}Nl>a^yKEURu)q_167=OSr$L zq>nqSk6Ya|Zg#n-tGf|dj&-H3{!V1BxBcGx>^dcLbX}&du@S2nKIHKMM^?8wtZtWP zx&`YS7NdtOrTg9O-dn2OhxK+JDc$Z1w%un@&@m!UBg?VGK8Y-+6fYuEk>Vx5C8T)U zQhLMP?rWvmeMfKi-O}xTVcY!_1szg+j4X!~A0f*r#h1ubr1%PO2`PTIlzwox`(3Ga zf6?3hwRF3g0p_Co4+=V@_zPL86m!(q)z=MB`&$pVM1Q;6cDtaU)A{VW^B$$0_qERZ zprE5uy-T$_uiox_rQ02B+Z|ZS`4HXt(9+HqvCfC1prca@m1=iUz1gJu?%luTb@{=<#pZe*DmRPYwLcC z67Dxco}*)%xLe++WXn6*mUk%8@^)_b+mv)a*}C7Og!|o)=jhlju9ju%w7+$~PYL&X zm-KPC^>Jtk9|t4PLGi$n?vJtVk1XN-h>|`|u|7_8(>UJcqOR^(WI1BHuKrYHDp#P> z0GC*i&$pD$akqO`sdg{W+r6-KyVuxuuR=k`h+Kgz$27kTSxzZtAXAazzko|fajT_t zle^s;O0|2N-tO(C+kL>cdoKz)q_`Vdsua8!Kd86+Q0aD`wCz4t%K1~e^QTKYf7LpF z2?ZUUdZARiuj%c+Ub@})Y`brla{j*V{DacYvjfexY1qJ6D8;T@3n0(Y;UUOUN3pJM zeq@c?XNMiOpS;o@`|OTq9rfl3$pZ4MW1!8CJnLwZXB~C*!;x7S@NL78iA&y6mh>o; zio}16^ho46NH2yg2k8;WT663Db;gSzvs8~3w)skrmPV$lN8@adRzxXRk38f#XfKB> zC+%gCS&H^DHou5A)ZWZ;+XUrY+%`g95w`{z=MAj;0#%3A)lIT_k*4>;12nma?qr+Z zp+wW$A|l%#ufK^ADA1{sH7U zG`kO34rce*mUU)#+594Ab@h)S)1}!9mh`hI<K`_})UMtK%QqmftJU@;h$#VE?7{@!9_o_a5L;RNou$?j{tah#&$g zWLs7s4AMbVdX?T0qcJ1_0;HHi5lbi{O^P5Of;8!ffQqh)A|fKFh#*!hs3;%^7En?7 z-gEEFnc3Yt^Z&Wu_dFjyX5M?wx#zy;y?5@+PIfmAIlhO_hW)qp>D`{waN4o|g-8C` zVdOLR>B0UI=lBD0HViM=rEt4{gG=55#LTSQ^EaH)_EAg zDHkBnhF3n1tCljC{R&=V;8gG$3$p{Shnd$T1lmYh0+$Wt2jOy(@_zO!C{Kk`LHQAw z9VkD>l;{sxb52u3H0+=0mtzurw5ojajGPrCgKM9wUluxi_B-7Q{Ifg7+&%vT+coWC;5`n?RgeX1*ferJ8;^?oOUA6M#fj* zilHlCYlh*neRcjKoK70Qz_n7mz-|@KLI3@pHo&1Dz@^hU03<7P6 zI_)&>dG)xzIFI`$k9)x>`CsbfmzE*^!U6r0(B7I#>f1^YCWcX|f3#dkxdxTFlG8fjEM{eLS za((;s^&Hc;;qL589ftUp1rMnORrFS+<9WwbU6t8)hBh zvRO;*d1N)Sw(M6i>(9*ks75a(o_+SRAH9ctc6|ICPQ?~E5N3-8(J#r;m{O|!xI>)A zy+=K6y7Ra>Jnl#Y+Dyamr$UN6m>r}T$CQfg$1QXkcf5Ms`<%y} z#^XMWKpQD0!(}7IM7W$TtPin2W=*<1)8SM|H3Mb`sUBy_k0H>8*IXV~eXh)Azk=67 zI2F7W!R)|m4f9%sKpQDnz-2@EDY%@ZT*`h0<+X4sD6fOrf%0~y{44@(cs;}8s-@h- zeg&`R;8gH>9%ct#w!j*9b0~-&^CsReK(}jl;;T z?9<=sn7${c@8*!cD||MEb+#Y5qvOZ}dE|Z$BlodS-^($5I;X$eA$=-*HiZqbA9=9j z$k{ydFo%&d?b8o+Okcq1^BmIWz-Lp~D7%s6`))XWu|xVo#~c$m$Ab#zoYENT{T?)5*F>$NAOzBJealddH z_qcl8Z=J_I!{eSppp6ti!ljgg9%!6ZkNdOpxEFZbU!9U)R44z#Il0Gc+-Y1!piNQ# zIE|a&RZe0e%np-Sj>j#FKwHJitCLr7PF{_ZUxPrKqAEL$TU|YF4d-#aJZ?>=BlmL{xsQGNUXJP0IDM)^`XTVy6gJpyWO3`1#p#DSq`${8M=s|W<&YyA zJ{yX|9n%+a`go8+X-w&1`*9~b zjXPaE?hNN~7xK9C5oj|b^Wd^M&F8>nE5#x>6;dpQ*+GhxOzA26ahE!cyGlLoYUgpE z;c+)2&_;^&a4Dsri}4oqxX(I|yMxDl&MEne>f|puC*RG5qmnOTDMehjD#B+|aCx|tv*>nT3769&qq6L`Jeui(#~`!- zu7NXp!5eQ`uEnIUN0ep#N06=opAEBWJhJ+sQC0TGFvAtM4i6u47(Qq}yr0vnhxf8S zW_Y)!E}VA4G-YOu5M?J!1Ndxavp!rln$?3V=CQJzEojn;N4~{jhMnpscw$1uZ`Wb*Lo z4#TIxXQSC&aM>`slSfuFyMz5P%-o(VIPEmcW74A$WvAIl_-vSs;E~nLhOs|}88my4 zho9gu{CN0mG#d+-4YOjnY~KP<2&dCtc`y58XuCZR!D%PxOs;4eqU;2n3ZD(_DR9}+ zo&={8?GpCK(1zNJncL%tv*R`&J{xZH;Iid5hsRd0gh$!0;;qTorEj0UlYs zUf*GV3^QoB{;%sy|YCrlB`|NnH51i3;<2}vCV73$*{R{LHOzB(ualdgI_XqX3 zKRS==@*DTG{~*vtic4_WOvImXIW3Wk?2nlUeDQ%_DU}Ci2dOGBcS@PP|I9 zU%{&)oQf&D3T6jhHJR6S2(*#1I$SoCuZ7Er@-^&NP_6~1f^rhf4wUOM4`v5mEtywy1lma16fPUejp1^VvLX8wly8AkLHSmg9VmBZ${i4B z!>b*StCq42`xU&pz^UNX6=nxs{h3!E1lsWG#p9}Z^uq?`$t4dv-@+1?pG0;iMC53^rU&pbF4^*jc%Lp{s6o}~!1A-x1HThfc+bRxZw z{R+}6;8c)a39|#~O-y<{0&ON?EnLca=stI|dfaE6$9Wx$$fq4fK53u+2gme(a{3Dn>3@UIrm$b^M?U8`vL|5NMP7Co`5*iAmmJfV ze-K5*J<1a>Tw%7kK2mJy#;|bQrrxejTFt{a=J(~ zWq-`M?Dn*VQz2Cwm>s0*#+17t(1uqh9#?$_(SiL6UftnT@ah4x1Ft)o*I)$NNI4KL z8_NCRa+0zy`xTT^;Z#t*3uXt(Bbag)0&RF@@VIIz)7h`!l?|tY*GQNhc%1~V1b2ex zT%Z=da5o|0ygYh-(T~5<(UXw)n`|fkE{+x4Zubc!?w40wkdf6d`#$j{!TJSBel5s% z?6z>7j!TQ%eH^Y1S%pQ}x#{#h!^-YoN5)ukOcs}?3JDcJ`xK%&j>|7d8zf`yo z8Dq&|RlyasRRJ^W`4LW6sQ#zit0QL*=~_ypl-IArk_X8a+bWt?CM;yPrF&d$j$ z$||sg$`AA`rYuDT*}20lF8R4V(8v!NG;%^VG)BP@li)VvF6KJC_ZKVMQ!|z3lIE;h zDkUly1uj$RtCr|%T#McAsxbF1vhqt1->*|40W^Ff3-zvru*fAFpxa@;ku=kA(lax+ zD}c@+basJ4T|prsA%&>~s8?1_Ucq=v?Q&RrwUd!j@RVOSTTCk(Dd(+ry9{Aw1G@&M zk1n>Hh2Vs!g_fxKwo%J0QA;RlocR@0nB~P}>S>Wmq+V(1^b|!%0;ZrMYKV~N^mMn&b?W{KKjMn&a%K}315;k^V@p0>DzFi<(M3BC-3xxC zch9rfLGmDs2FZ6RK)E0fTcSQNqpY)2#&ZOY9(kFKo43m@>YZ1ZO&19l{!m`Y0{l6! zL{~{g{GrZ|5JTs|r-G%o6pP8D-U>jOR-@Fl@8t5o1Hcx3FI@xGtx`AEoBKDlil&r1A zRKY_lvJ6G`C$m{~IoOPaS5{=oE-H-Z>GoWu_q$f~n~1+0S8_Eb6m?dy^sdCct!27B z)nxCf)H~57dRLLXuebEBPEj55iigr4GAN~ggI`;^G$hIX(=4N3Bl`y|{k;^`X>=a` z*uhllPFJNi)cr=;-8y_#*$eY&*BLbZ$jaxDvT_DXWMJN@q(%2a0G%Cl6o4+mUIo#UwiQv~=ng z+o`MU6t!ymiB5Eh7z89Q5rcusxyW`0ki0|;0g{)9J9R{Bx;HS`<7?t2w<4O!fn>}O z-|-02d{G!c=ApD|*;=xJ?vy?K$%74;ziggvd&Twtigm_0RUSx;@2SA3BBQGqRbq5C zqsok`=!m$N26pA-WoAXuzmn|Olf~JkpMZi8k)oTV>k&YwVuB|L2!Cz_$P0wqC?FqD zDZ0{nf2CEM2!s6mT{ZUNO?rX`MZ!y=#k|zysAV*$7_V6^}l{8Ao>-N+nAFoQC zq1#i7%&`|;5WWc>WACU(Q9~`OTr8cYB7$BaH3O}{ zWONIoTN&NPs1>8ujM^}2%cvcr_KZ3(>d2@Qqt1-FFzU+ac1GP8b!XIrQBOv_81-h< zhf!Zf{TTIUG=R}SMuQj)W^@OmA&l;1l*;HXMt3txV{{LrbVfrNWiZNQl*MQmqv4E3 zFv?~$lF=weqZ#Gsh?aIEU_M{ui(}kQHy~@*OzaK3Z_&jKtFag!dHUQ3B+uyyI--09 z)HAm@N1TFYZ?`+29EC;c1x0XK^19u*z)T>y-?!?=pIi(fb^CkZm8Z?GW2OWZPl39bxnlqoW-6G21?2 z^eKBkW83G9zF>5WB5a&bDva_8p_|*?WR*KQQ`{y(bx+V()22KQTJP z=q!*te}87%IY#Fh{lam-vh6oUzcaePaTnS42cth3{l(}KkYw;T+x}tnFQdyG=UQ*< zFK$L2MhQSNUn1K|F)Gd8GK|Wy_X@UM$+mKg%Colu+bS};ioKQCb~U5Q?5)D+8unIY zbSZZMQLM#i%u- zHbAmRTeh`hTYI*3VAPSlo!HiyQ5QyC8Ql&f$LPkWJEI;P*OP6%*w&j-ANKZTTR%qq z**k!30~rls?_jpw!DtAhI~k<{NzQk%?QTYCjPBvMbhZs;l)>Iiwq-FI#@^v<8^N}0 zwvA-lD7KAeTMpZD*_Ow)d`9;&D&V+6wiPidW;BN5#ltle zv=K<23!B)snb9+hwlI1YNcPyuwrz~Iv-df+JTYi;P}kZe=*!B*i{frJUdKXCcc#m!GGdjrL57>5y z(TD6k%(f$pK4R}twtdX#6ZU?}w$B)S&fYKBc8t-NjK1Qyui5quqvMRe<+$(I_C2E$ zjDFy_AK7-2(J4l!IqoO6ondsA(a(&|0ZEU1*0q3TaInz8C76! zMYdhVs1kdxW?N-ORoHtC+p03Umc7;3R-J7%*mfP;u4mf~Y^%w(T5L;Vo0pM~y?(X@ z7zNpz%(f7t8`)c%ZFLycWt75k_1LB{s?X>qj%&cShKw39YRqv>*w&O$Ge*rht_9m} zX4I0=EgW|%+iqjjicxEhYs0p-jM_13&v6~t){#*sMx8mX3){Lfx}8xsM%{trIn#q} zJsI_4)SFQsAlaiY+xju;&u9Rnfk3jyAhr!=bO)m$jP3-IJyO|r7o)owrE%OnY)fY} zlu-u9WwI@c(J)5CIc@~ovKftJG>Xw^Ajvd`ZMlr{809m%7fALfU|S)hB1XlG#sJA4 zW7#&2(RfDpF`57*d)&{q2N*rb=pjZWK(fa~woPI*nb8zR4+F^_Q`zltlew2|XBv28P>XV|-iZO<~=%HC~k+s^1Y_CC+H z7Z~ke?~81EiBXunFSG3xMz6AWC)-|Q^g4TYvF!~;yV?6D+x9Sei@kf<_BNw^?0tuA z`xzZz@4IY!kJ0;#4szTFY&*p0Lq>-=?g-mHVsw^;f0Q;bft_b0ZUVRV+gKeO!|qx0Anw z`i;H6v+V+-i|qY_ZGSTQi@lfF_BW${*!wTrE;Dj%H1;MpkbeKiwgk2%GAhNWG{==; zTUka|FuIaaIUufc9ZS~o96WbavYRKM3 zY-`M@345Eetr?@{>}|oen;Era?=5V*mC6Wcm7 z>cZZxY`dLNH%8q#t_RzCvaJ`}db6z$+xjx<$EZKY4Pe_qMuQj)=D0i9HiXfg>`i6c zU2MCXZE0+~hi&O>8_Ko}wq>#{i_tJf!#QpQ+p-yrWbY`pjb@a?D3{~%*p|=eUPc8R zSID*^M#YTAaNJn7jbqz*w%y0J32eKcZ4a>RK}HX;w}fpI8BJm|nb8y=xpO_twyBIB zVKj}=bRgMd2HR#bn#Jf*Mzeurk2!3c%V-{>$2e|2+ZHf-oY6u?i-2V2#cX?m(Go^a za@os3>%@9S*a#pn(8?q=JYjP|hi zEw=4t^fr6X zon`bh$DL!_c}Bl5`jz8;W83eHE-<>t=no*t?@zY<#pn{Fzd7z7w*AYt%WQLPGVc1^ zKr*w3Z3&DL*;|Tjr5TlBZ&|io!RSgx-dq>`K?ApY3OUTHnCxc26QlkFJ(?!)f$>H+Koyqu$-)c0Wkg$Tt|d z-S?BRpZSKql4Sk;bTi0N6#2GudNYz2ti`*45*h)?w?8%pDo5|-OK1Wl-u{@_6sR(N zgeb8Yka&+!sWw33Jwm100tr1zwKGuZ_CVs!y;KLbb!1y7wsmG(7sFPntAR@2&fadi zjr6Sv>>8GpUQ}FQefOf#0O=Nx%^^ouU?voI0w zuxv<H=WJdJ^v$eM*l@@GJ)sOWm_VN3=+vq`ujO?Xrh=%+1VB&m}Dr^!4C=LOAIid(m%+ zT|^$*IV>Kp_=FO;ZG=;P$Y=|Y9P?QNC2VE1O-ICI9WZ$G$j&Ip>ye#b7{OzWbgD_N z7ETq(mE=*96z>$q=SM*HO$5nz7`_W6$-ZZxg!dU8Wb^@}Lk9AE$mp;@^tS9HZ2O39 zN7?qVff7D3kmpkaC46Qe&*wTKk#+$qCK}&1MGm`Je3hK4UFBtR$WMsz2H_L$cz%gI zq+Hr)ocQLO(cSJHhQ~7T;tkL4=gEUTD&kXXazolqF2$R;_mI7-{*F+~-trdNqdz|? zuM*-t=kha^;>@74L;R1aJcVw?JE(u86xq4M@+>^*vuyaRD0$KqSGMoSQ7Aq?8YRbZ znM_sM*W^+v^`+slFpx@pL7w7Fi>~x$^0Q>c8)u7(@!osmP4@cEahiN1(sMKE^Bf7{ zgClNNNi$qDQ1(SQjk15Ez`j|-dx}p)@kbGU5$5)^ud?kN*&?q(ee~<_ALJ^?unaXw z4&{EqI9bXA$&;l5ql%2KVpNII)r=}Ls>0|RiSUN}s%*QKQ8gXWNpP9S#oo3Mcenc= za;nz)C33`ELH{Ic%*_nVMj4D4bt~fbTtP;t%cJ9SG2(-jB}=MebWd6G_Y`N8dC@E9 zDGjsi(y6D*C1Ua6F|h~9&nkEkAm3~q0+O=c$f&kJ*ik%n*j86ZBuFh_TS0ChXOti= z7vB1P9XVnIsZLghdNJzFs1KvQIwC3etr< zQG#?MTdW|RMQEfTUC9Dk!q}9W~wpvXlr%J1d7@AX~I3kYg$A#_hopis7r5yvxBANnSe_lT%g5LUKghRN(f-?Os6UuDIbd zZg7x^?)Sv&jx}(~NmvI&lR!eQrY=$A<3>h~zmlA)@t2b$Vtnx(3CqZA9UqzG_-@Zy zy^G~?11Yw`DoJezGDvNq*jQ5XCHZD@sz_}lM=YuJWVRu-P45y(>J?ZeshvOusW8Rb zk$RDwDpD_yBbL;2WVRvos@^4%)LvL6seM2OsXY{HM`|}YRit*2BbL-_WVRvow%#R@ z)FD_Uslz}9se=?7OG>V(_sFRtb$}ePq~0O34XF?HE|H|ZfK`$@24s->jAHFbeL~JC zQuuNXxBDnLVo4n#vyv3n^a(hP)B8ILv>Wv}IaQ;6O^(=6za+EWs6WFgt3D58RDFiJ z*o}XhoKfS8JJFNmh#mh2GAqY-d(P=yBB$anSS6{yfeccAP^=xP3*=Oh`i&g1q<$f@ z4XI0dmq=2jb{M3}02!nbfNe>+$*CfBSxxF62U4Xe7wU*4RS8z9RAnH8R7HxlQ>r{U zRiv&YN32q1$!w$4)q0mmQrE*ON!0{0NY$WNJ5trisUlUC9I>RTklBXR4SJVIQXyC+ zsoFpWsUXGLk@AyMMaoN#SW>mfY(wfsy-OsihOo-}!e&53D#6oSA`e|=Z=zmy^fYp+ z=%tVYJglG3b-U~6R=&zxuCk5D*K63Y!YsTlG#**t3%i?;ykEy5~S-WKC zT3;1oOYRP{LHu?Ku_NAvoGRj-$Pq)lgKkw3??FBV@t$OlA>NCuvBU?%Y!DwvA$G+3 zlT$^!FF9g}_tvc{;&+fwLHtg##}FSv)>z`1FdM{&QivV#d&sFGem6N{h^OjS74aUHVgSu5U7mtw7mlQW9DxVu|Pju`ICb*qZ|dh#i_Zy)gjJsTuLBvk5U)_I9oH~9qqvHd@FF>4xW1rURa{>qpTU){ z(GYGQ9Fo?%K$Tte5b`}Bxgos|Bu}b?j6ML8r_v#|eF!8suEXp-B9XWi*$b>FQ*J(c z$f+uGH#uU;+@)JpWxhkcm@?g-17wd`@cYRcIZ;y^XpOQ0*xmfNW zlOu-tN4izT{7dpFn14<780KG*HIg~z@+7PV?;j|_j`#QERPp|n95KAV(XA@pr^u(^ z{S(<^c%LR~4Da7zHF*C@5wX1G)_9(rD&9YnBZl`G-Kye!fqV+ye~>+f_eHYC@OHmw z^1e(FcD(-~r;7I_a>VfdQ@5&kdoZSocOuzicqfoGhIa)E?{XAj$NLI$s(6d!yBKZ`0S0Z~1@2kif!@CBov`+BNsX+1tPc4bWE>n$q#nvLv)vDxF)l!8VF|}N+ zTUE7OPrj%}wAYbMuWuS{u=Gu76dqLqKbj4YQ&obG z9FQyO_q|DEMrE-zV6$ilryRdAkQB3tMDo=mb&g`f4{0@Ws+gpZBbG@WGAo(5J&p7( zmRE_OcN?sdUTYvjo?9r^j?~TMRFP^svoS9)BqrZR3D19Bh`zXDpEbj5lgBYnQch**SkcLx*JwW z>K-72R4T>Vks3ly6{*4Gh$S_U%r>Ob^e&O4vSF2^MgbY5hEuE^sVs7;NM(>CmQ*^K zZAgvOyF`*If>n|l17wgYpjbOn`Q%iQ$|XlEsnKM%Ayuq*i6r$9tdi73AcNEc6l+In z0y$Nr#*-tK)L1gxkSfu;M3R~Tt0XlG$RIV1V(myxC8vti6mrCpnnY$BQZw}~k)$4n zRgzi+WRRLqv38{9kyAx#4mn~;JxXR9QVaDik)&3@YTQsgMG;X{_=>WWoKaN7D~u)N zFfP}Yw+k&MyA79>Vr&v2yYsqOz!CzGPG&wMO|D zx;6GP=k{zOp981o;Ws#Kr&v2qTge&4N!;phA%{Y#&1APx>IL$(D@f1H7-96Zz9xGO zZiCdT6lzE6Wpb)Wy+jTpwPpHtkllvV>*TX1wGVEC)LsgWB_(gt_mERXYBxC)q;`?r zhSWRcvnTZ-+y`8qAw?XPN3XLTtZ%IEPr;5~3 zawte0A-fH!W8||ZbpmdK)OQqWN9s5^RiwTq2L_Kk`M%Vxs*~>r^4(sXlW&%yzt0-G z!8tgIP=eO$E*NMs1 z=wsA>mD8vd>_#o89`y<`+tq&^oW`itDKJ)bdFEV8PF1bf=;qcMQx_4x zq`QfX^1Z6oOVG_Q8~mD6h#kMCe8@oP!GSSlT0HmJ0t5IZVu$f=^z ziX1UiZq==^RIn&|z-bKHjRNfk?MhD7pq=&fk@M40w<-r62qz7i;28`gf9Y`tkbD+9 z1V}!My^~QYqq`X04MfjkX~XCbte`HpuD;|{QSVKT7`=Mx)>!Ip&meQ0Ons-})g+#F z3`c;xP0j`~Zj-ajZv5FZ+?z^z8RS&aOD9JRy)@k#OV8sOVU8o|;T$N9XEbf_jHYBO z-n3000VzO`G3EJYhgf2{gEnOHLKdVsgaLEYz*BG(DdC$%hvvx@=yOEth0-dmbd0^$)VR zJrC&7_>7a~Wr^GKkZ$je2U6xc0>tuo6fUvy6CMMSGRy~(GAsZh8K~r$z>1RPl9^6U zRmqQ#Bc|ksb*rl6+2k`zu0$nolO@k1S7ga^_2}r5=je7t$;;r9XT)+Kd9tqnk|+C0 zAo&ZGRY3BzU(M)gMr#&9iTB zIjC{l_6y!SJZqTu&bCPA>ew>%kzJ0m^6uqZD# zOUp?w#2*k#%_$s{kvgtflhnRhqqFdimsBI5etzaqS9RA7u9~hgRa=&L=XQ8|F*zE|L6V>{htIr@*fR+?Z4pv(SJ5@(*I-dlz(;bwEx@SPyTm< zXZ%NkXZ;J3fA(Jvp7T#hKJWh{@QeS`;IIA{gTMJV2QT_(2c`yg2ImF746Y8m5nLab zAKVg{8ax$vA^1~ZU+{e3OmIr@(cp^UpTP~mt;yShp9kLw?n*usoRxeu_;vDE!Hvn^ z1P>>l4lYjqJ-9dd?_fB2V)F9j>B$R|XC%LpJTLh`^0MUJ$*Yq0B(F~XDEaB+?a41D zpGbZ!`MczIl0Q!VBKcJEvE<{)Unc*UT=F2~Ot`v=*B5AzUsOD~{EG4`%dakfuKfA( zzm@;Je2I6WcQS-{*!zfgns+(`nd_YgX&(13^e*;3>0Rz!;a%xnY%M`@Z)B?_uu|?@{lk-Y>jg zdB64^_kQdB-ur|1NAG#>6yH?eEZF8dz#PxDXr&+yOm z&+dH*l| zU;V#fqA&U{`Ty}>_D>ExjLDl8m=Ty2m>rlKm=}0Fuqd!Nuq3c7up+Q3usX0Nur9DZ z@JwJ!U|V2&U`ODMz?*?Rfwuzh2Hp$2A2=L15;z+8B=A|_o4~h$?*l&sP6kc|ehQoo zoDcjFm=c^CoPnvI7n~nl6nrB1WN=w$C+u-*>EX&~O;F;jL;BUd-gBP)!E(QM%UJg!7 zo{~H@c^VeXjO1C#vy%Tku7tVmgv zvN~l=%G#9mDH~EYrEE@lCS^;?vng9swxv9m@_fpUl$TP%DKDqIlJaWG&Xm_uUQgMT z@`yt6@@~p|DetEoO!*+?P|AlXhf|KEe3WuDrH1P| z*R>^A;VN-en~c1i{QB9MyNeUumoMXFaJ8Y&fY)!(U~YoDM7NB|8(lvq)8)a|BQ5pu zLHmrNF2MI>}tDliQIyh{&uu;zh_W}xy_$Ok9j~2EB{KTKw+8z;rhKR|| z73M?{^T*54i9}4+I1y7y#LT>p@>&0hn8NYGgilsttp0nge!?OK8zKF}-{3(^4haqFBqdWYee!HJA{CCOjcoZ|2c zJ{P_KBH~{gSEV+hPF;6$zERudY7`|H$LZQr9Hsg-g^>A=<8=MWGwlVJ>o>bNeGVvY z{$Q8u{%;7G|2UsM59G-Mx2sx47D925RHFr)JvytPrN2YV)ZPVo!wb@Lyq#bv^wu8N zqFJ3(@geQPykSM&f!T${>7%{sbr}odw8(o;% zqaR?yCiNTLT)%OHhK(Di4$aO@?UGkmG`K}GaqY}#R6ld{XutOwFw=_0=VxW&L;cz? zx-1_&yXW&IITIYWFf4ocUlwH(o=*UjRxkw;!hxDR!;Jp8r zcMS&Xv_gF7H#_n!g2?N<^M;PZV443f2eZ9J(Xt8(@(K#F^79IcTILsE?u%SkcdB{a z&?fFz2Vp*F6<4WQvb)%|6Kk6ORUcRZ`&jk5F8Wzg3b)5Nrih>Qq^+#9l@y6%<$G&k zAq~pT&CDBH=5&wAf}sa)poErThaov552U*fSMvq<@R@8-9(zw63>JWY?a zDz#_T*vfhTEv1?1jg^=7w0fZ9xl^})fAg_}mughLt$O@ZX0w1RxxYT~{PXu!?N#mV zp*6nk{~s>D~fB$O)a#VhNo_#19B36x+4 zU5O=g+u&vTm|C8S=@CfFfFpzZ0dCkSGba!(ADf&3q1!%^vsXyIfr_V z#`UD6EV`RL>!7FR6+C5ikps@9ZmX-~$4FdE^lsy7xr1JJ#WvP%(M;!2$41xTM|*q~ zO$}M2-m#Pq;}zz{3X=k19;1%UaXyv!aYYJI$5JHDA&huUWJl|mwb6Axb?s3HKR!m+ z8>wq)>UsuUyNIsFkQo+rXwU`Jvs^v=*j2^l3PuciPee~s9_sfv_4`i4kKeFCR~7x- zU3~6}Bhd*p8snM08lu-i>b0#te$2*g(KXa7(R~kk&59VxS{@Cyh`N<-h#x1ewUYc2 znRob20V&su6x%hp9Bn`wKl^5gMZ#A7hiP>*goFyW$o2GuzzFst$Er zN*%-WB?7%eF4y%!R1X#$bxaZ+b7KZpD60dcTy2e%2AG=Tp?P zWgq-_6FqN;=vgC~PN|qPzdgDwr*3(7;>Q(OIOdu7SI}Ltp0%5GJnFcDI{urAAIBp) zmP&S4Y;EmmoeJu>k~%(mH-5Z=MQ4s!2_0+Tk8+P07CjTxYZdj{Q-B{en{zJ+Qz-Y^{rhbDb;m1d}Sx@|(==Zm^AMc}gpw}Ae zl{*Z?!;imkhuLieI=ag|H_$zHkbBY~_alScvj@574{|RaILl#V zd5*GNhu1|Vt?{C#%sn(b9v1)AxJTFC{nGk&?3~uHv8&`W5XFbh5$RkY10^)a=%5|PVE zAB}TBth%>wD&b#ZC0u=?rd(bzdCF;ZeBh<|dcrD=^(1Qmf~V?W0D1ufGII?v6U`ot ztQ~3~TVYDuzCFa;_r2Lw@`o|^-H>YvO$~mLkWJ6pd5YEV0?EUWB5`M|YWkIxV>==Ch>&e>eH7ZP zi70h&Bak|7)JnhQx@;k3J+rTYuMtbsy{|k~HnOhIYh8(-Di#jk?6BxPkm?vxB`!AhhJw7}{IpzbR(NHP zPa1e#B~RdNcothjSyy>;xW?A)-v{3qi?o;%mbND(n?I0Fz^?uK$uFOCm9#Z>vbi>% z#J_?ur-}YTfVtCl@g=yIbKRJdUXYVkfG;7C17n`tt}*}9gy=VMHZxMrwWmH(3qV!vaVmv6=*%b%Yw`!)s4$P?UtovkHr0o>CneECzj6SZ@iS>V=CRqs&qB@&h>BK zFRf$WzG=O>$qSFTl2NZ3X0NvGt=;N_*I2Q>8#bc_?h{2+w}xAnkA_@7*TE<~dUfcS z))>=CXSWz85w0?Q`uFJ9xKV@l&6*4rdrimo*fcI1A*Ec2C+w>=_c*HdJ5-xk1+Aw*m*^|2Wv(#2HB)Afugy7gow0sb&u zbY0_nkqYqrX8NoP^a@wvBz>;LK18Pg-wiH+?wc@KiIwc{>dh0GHey`5pxLLm_T#op zE|T-cKGmaR56eb{*GlvCfyGT|%(Z5VIO%@BwJ;wydHT%J4Lkmob^T&iW4#?O1J@Pi zx@u&-zp3R)#APCOTZq|ylQ76x)PWt&lFGWj-{4BDWxrXanL9a6_|HgH&Nat+huJnG z17CM8&aP*SrG3_{$U1fOQnQqWhV@?lI#*&H2O8$g5RG%9qDs+wcGrH^J-Z^9-fC<@ z^b0a9&x7*Dy{v0l#Ey$a#3$b;AX(Z%(mEyA!*`{{XT5n$g71>0ZfkLs;5%pftQ$lr zu$(ubM|-hW@zhXCSk5(9VJjZkA-gcWFh_{J*oe%e8jY7!X&FO>_iA|_mUT7ZeS}^l z^3GWv!*(!EQM@RFHXDsow}p-Ud)nqRvx?~3!(Am~jPXBEo5zVAws9k(Q;c<9&egb) zxcSV>Pa9g0mYH2hgKjqlZQ$hGn}U&X(}E5Gqr=Mz+ogtL1bJh#(uh1r1atBVn>8Ib z4jJkh_Wd^YxB4MIYYdIn+=zWcVGD^{v@v)OLS6yAoK4dgSv8~6#kzD4myuscFC7eT z4a0j}c_h8YB^US8RWe< zO>8+=A6-t#a+Z;OQHkx%wc^yaPx0A4d4E zlw0j;C2Ekn+cbkqc5}U8{REt9INq^rZ<7C3!}X@U>qq?_C4;76w$Y)Ev07xJuwnPx z*gG3)XB5zR^NJDQ-o`#u6fu+@fAuzESGS@yOH-*=_PpWwMVuV?0=2B%Ov5?Wa4zf$ z{nH8yv(iKf-y6DaGETo}X5HFn78a+hRF3iUK>-{`X}vo|%&N7d$5 zy~SBZ#mRNL+vsq!t>>&hGb3=CVdS|+k6ohR^f7oHM=SoMQScd|k||%2(P6E)Zt>82 z4f_fk``vsF%Hj?f9R}Gsmd8H4DCZh@o4otwfj>6#^tJW;rq^s%vCrt#nYUoc>TAPs zi=E>~V=l6C@qK#Px%6nIi_z=2le2)fHt`q@_bhZFk_&J|_AtD#M3#Ib%k}2$>5F!W z;cC`bTt#Tg3$o}2>bT))Z0i{>rq(RJfzf5ZCLiI5C7xwiS2YnY3|Zjs499Xihp)A9 zj>%o#PZ=uB7ai@paS&Wg#J9#E zOXb!jj1!FDUm`blDPNA^{mIe0n;DpkVYAV-kx4u|leXJahNrHrr;mQh$%6EkqPT{O zf~4^qqnZ}_qL${RM)Epla(%6TYPe4KHZNeb;N@&CHr(GjyTgJ6ZD>Nk9}FJ7jLD`y zujMLvz_8Ec_@Np2fB{^MjgfBEyWsN&=|yx?GtKDqqP|412yhh-DWjm+PuKOG{wyD@uBKOa68BYFuGh z#b$@=;Am6E{A;?k-8efrb-p4B05Dlhz5_A!S0jLe;9l^YP zlGZj!Yn`Os#^n3L8>(fUj`k+`a9gl6rlYlFFQ(%*$^QSIj!vSeei%d)Ma{U1N=F9N za)+n|fZ8ak2a4*Jq;*ZwI&(!s;X<{R>F8!wWSx$#vLG=Xon=9m>F6n#XCRqiPR+QO z7a#)&XA8mr)CTjxU_LNO>z}0cP11TZ`9gR@b*$4d&?F!350=Js^p)(zbo7?&|L^Iz zLllMgXv?Cg8COvy$beeLiCO@tjiT;BQFkY4sY%)pu4p1$sMazacbgSirz2GsB&K7C zEXXn)>4NzrBoos?&A6D)Mg|bZZ_Yp%fZAZ54d%m>w5%j8gPG5PEAqS^ZZZ#NfgvYA>|K<3@uKI+%29kRWLe=ZSOHthVWcq z+@OhFt`UZ!WIs}}Cz7Dtx$>??^s_O>c6A`%N%+ExlMpHI+ZG9pPQfZPqGntg{f-Ps ze-;O^CsG?4t%OF)leA?l&;=QHQ6B!lAyS~_vbJfix!%yz7J>dmWN3AiKu?8+bWS|dy4przwZRqnX^m!&p+mxhj zV2Q4fp;yX7IUFJ-dIlxY-3YCr?G}m3BQmrtDROt)Zb}r^JBl^5N$M;#+Mv*=0wvq7 z)~F(U;cccyTZKkf!74POW?UNGfDF*6Dh@&;YD1%!q0vi8+71?|ri`m44@o#g3iOh! zO{}4v7Jl)H?2z_=a^zl)yooapj@P%JB^?60;6M$9dL(RDKX^0Ha zrw$H6A8JFNeb8rblC~#F+szU+lA(>|p$QI=675Av#u_?ck*FymL;I5=cjE)5L}9(7 zSVMcH&O)Qz3XPgkvIA<3n!^{~Z))_8(5MBhLL+L%rBQoifJV3CAT**jG&&584kc*^ zS)dLwuA@A3!XZ+iL$WrphK^bU>Ws+HM^OSDH3hP+Aw7rC=b%ELE|lx2TA!})g+DU& zIU@AA9afBpRnFhETGS&$Rv>S{kw5x8$#KSs};KwzVJ7uVqXizQehQ}Q8O;Zh9LtK zy9WoM7`36;k5KFc%QajEjgW_I93tg9VOdV6Epm-SWaw0sT&GRBtjkHy@xQAzijtpJ zt2G+F@F`QRlR~W=ScO{Dj7zO?$N;tO#X+b=ZK(Ad)cPe!JI8{JmvQ&W!vq{61^dOa zzAjn>yC0FE3sHOcMN_b_-chWtbN_XHJwVwnsug<>zVHQ8vEPMa55X!Fqh?%+%|r$$ z_Am}YF=|7xf1ubUmTQ&_dQ=`};}9v=CCmD9(epa}zH$yCLzkoEa(Vf|pLKodIsW(c zHJ6gRyvPxIpE(b{@MTl2e}!6)!79|EW?X75M+T_17zd#iwV~D(-cDK>uU5)yJnmc} z<5tSUDjXsOE8{iyuksebRwFW0&Kr3FEN==H);o&zRSHS)r1XDR>}kqgUai;~_`>D9 zd}n^8mkM1At5A%ZaVfSH8IWir4ni?%L$S(GtP;z$O$Ke3hv#sJl&g}gR9p_LTI6~j zk)dm%}QWnEu-j{jY)7btmEwOTvi3twZZRYj=vBCJ9!YR0A3VPt?>`*9FzQ5$M$ zP%Fi&)$wXKdbMPh?FhV~px5$HJ;kg&Tt{DH^icgqT|j!Mo(ya}R3GQ`P`$n=>SGKd zilSy*MSY75DC%=j3jnoIR8thy*sC@4YBzC3-@%1yEsqTwn-y7Sv!N`AW;1+~EXeYx zt(jo{J(3CL)QpSyFUSDGCk0^uYJ+(jFmL76ZuM#{y;=(<|0}$a)6vQ#AHEeV>6V42 zqorgop5nHU?8Q^u*y(7D-*LF{TN3_FM_Wxhqh?&CB_@c{{x(XZHcIP)(mHvy z4qmMt*HsEG)NGlQPG()!N$DWV5|h$SmSvfgu7Y`KBooZ385i>^l6g5n7?VP6Fz*BA zy}Vivuhxy3UjtXKHESXpQWm4r<0#M-OBG{f>e@0JTv^9_q;PYNNbbHkZ;< zhW3(&-Z(^Fe{utW!s6VViBWlK_Q5rHpn!z}T>n*jR(S6WpoL3ve0^K9y(&b?&4v_+lleLK( zlm{#VWgs$if0RHEm;zasiJn93o?{gHWKymN)cRz>7rx)rXM)gY7_34cYR08c0Wv_J zkvIr_s11FlL7%B!ZHiZ$#1a+C&?0###vxLosVK>K$v)E}(HKOAW_Tmdq?x8fVZEbR zLsO*ALZe9vjmA>4nQD#3!55xkYBXJFG#*x=5jEq|Xeu&5qla)18c`b>&4)(wyxJTV z=n)w=O&+G>5Gl|+S({ix3oQc8KxF9gD1jE50$JCPo{>rPfYlfLc3n5Nc5yYCR9NwtKa$EZA!@?sa+Cg+ruZ z+b!$sMT=l>ATqQg>im1r6fCTF6zgm2e_da@Df^3R#omN3yu(!N1)e9g;yG%EMtCBISC;vc7g%uYeKD$VHIjoGcL7~@x>fa>v|l7TGWPGrF@;V1fS;iX_vj)KVIz; zD;GjQsEjXkNPo%Xr8kEq`1q+;*zJ=$8NC#|tjkER%>VJOpR^KEP6~uC!7Mhp^W_!q ze6zeNY_zuRYA^k2wJt^tm+?`PCd%cfpOga+xI{CB?KCPWk zYva>eaVb*}5V}3;obF^+6Yc=bjmJCfr0|2#A%t#b7 z!lw=MX_-E4C|44O7lm48WrU@YVU|iV%}VG>a#@~jLu2X~CF*z?c|{%6jH`~fkpc8y z7xV$BjXDZZ$Gtu+&!^>Z5&PhZEaG0X2KypgNw0d*M@%re5`EsJVwOd%zrkWZ0V6hh6o3i%Nk z!2e6ZAAs5@WEKjU;nSx1w5dLAicg!wwVXsiXtpo(rS*1ZhFMN{8n_x;-&9$T*!rfJ zTi+yE&i}OaoxynF*)dz6w3u7pqe73f2o`!!GcG;;K?cb18xCUYqc-$d1U(-2Y4d&B zJfAj)#rPLqXk|Ic9ygV+uFv^W2(k6evrOz9sf1jKrc4YQ|Ma^-`jcia3Zu zsEtCNMj@+w+6tfcluujg)0S{8H4qS5>kIv5o!C`oIpG!HYE0}?vK}$9OU;R0BFp)o zCblNV3$KltSZOgQc8$=Z7J`Ky)Qn4yddPr@4d5X3pf>b)7J5A6(>D3E4L)rhi=n{_ ztt=D!jH!fmVmC=4#Kdl}Ozb+Tgk@s4ibComu_%O^aTRh4GN6#gfcqaf#6b8K6NY9K@_r8)EE&7_a%XS6PXkutOp_pEuFH=WC`6*7D1wC;)Qn4vTx5U-!*LMvMs0|32x1)cY45QTd9Xtw z%e);lWw6fMdolC&p`e0}KbH7gAt0mf@yvC9~b zC?`>}V?Kxz`$m|_@P)tdfs}mt|GCg;3ammSYR09}W5@t$rsE){liJYeBsBWLr+x3! zzV&I}uuSu1^a6Q!9EV7mez3^&lSQV5hzyA zPin~)!xuhnN_I*}_5`d#GHS*p*&1YkWKZEBB%?MY`wf!);?vHtSZih6I(b-+L!?;0 z$U4P?-HR5nHXt%|A!JbDgs5j&^QXCvjhsMco_eBleGKEDfnHp43Pp=MnA zgpmRIY{Nn5Lv85e@psZ(e(hhM_BTuPvJ8Di9$v*EQX-e1DwEH?OZm;yZYLr`iT=p- zRLaj!=ByIwIfO+2T9(t_3b|gRyrulgGw^lz!ij!90~7pIts(36n+*M39xmVzsaI3W3TtW6>mnjUH%IB!($vek!t@+MuErL* z8Y<-agYvdi%k?LG;hRmlS_rxRf>p>x&A8;c8sB6Ixys@oI}I$`nC3ct*u{c z&5Bi)(N*N(8XO`O>xin16?VHtv8sp+b@fNyd*5y<7S=n871mzLE+lJfk*u{svTG^v z?P|%Y!58joO4db4RvlI$88zdQEEyRfSxp>-WYmUa{UKRjzt-EY^<=$5GW14ysEtFU zUVUY$Vw)di(W?$3Lj$Aq8f5BaU153-Ay;pUTs;+X)up_H)N-Z37anNJH9*K!4^|-; zHRF=2B{D#+hByehs13O?A=gm9c8_1X+pndvVzahmb4B zBG)K|T>U6-ky@_)@P!LaxeA0_17H<$Q8O;NGLQjs4Z%UkMQzA65pq4`*BGv(5r_;;_J<;V*D=LZEUb4FE9?O&yO3;xMY8b<$wpG* zDQd|^!55xvN;XMIHX2qT88zdQY&b47YdIF!GQakuUwgu@E%IxRvu2OU4)f(< z0S=LxEwik#RTj-2M`UQFKk}D^t4z(pdPlLwp0up7CoF4hkp(}lSZ@nykX3307r_@^ zX)3rvD7Y9_p&&KmQgAIYK*41=2nDGP1-C%K&3YZdBkqA|9q)!PhTc&n-2vqHURU=`|7 zGcNUZAp_J4;~>b>OGcCc=5$hh6|@FotCy1j&YjIC{_MYlbO487`)e3Z7+ z)Ge%c6w7Xh6rY6aZk&{FQG%UnQTD@(Fz5w@g9y z2thuDRR}`OxCHqg86e1)I0!+g4M7ew>6mI7SoIQ8TXUijV=*Jz5k6Ky6g_ zFRJ_7ul?oM{@~Jz;X>K6v=&s_-)3pnnfnW7{}$hBtCv$^`fcSGZI_?(;M+3BdYWtju|Fn?}XF zP+Y|4k**97wP_er)JV;^YFva2NHj;320(4pSQ#}|3TPDrT6r#TFty2C8nUnIsxs*fR-H40s+m(CGJH)WQlbwCEjQ$G1;so9574tnPx?aF{`kiDD)kS zDhj1$T!kJ*2GsYys1JbJD6}yOZ5YsQ3TPUa_^}NAL>@lHA@ah|5CuO>uYDf&hMM8K z3XRW1e}>3V(?I0*(#)cc-cejCZ;~>I6|9+~P4WX+>^w;Wnl|t%W}4U={jMGcJApK?dmaI}So0YD1sy z(C7Am)+L~IVu}8hp_ku2g5Q{+9A~JMGlt4pFfvjst&mq=OKZQQkDAy3RKGoq1-(l)ASm;v& zR-q3yQn9_vP(#3R*`HH0smZAvymNY)5e zAsIE}lB_i{K(gjI2+61o$%-IZK|sq7Xt}Ic8yVVG9@^m$saJt4Nvx{>hqd>BlcGr9 z$7g0i5fCvW9O!6JTI+P67h5yRORySY3A44It-vt{HQ}91#O5dS)HN8P6Qf zoU@*1&f(7Vf8Ofps+!sA{+{#u^Z776)$dbpcgt}_)e>JpAl<8q_*yOalCvtW zgJo5(L|3FR|ncc!50 z3`W<%ILqjw;vc1}hc<{l8e0qCK%46@x~L4gc5;Qa9bMY?E^S+vwzZ4jwLt3ruTxJG zFLgvay2M?}_AWiYXi~f_zTZz1%| z1z)I)pr#0U9hDJO4T75G(q_1{={%yFD57a{bIcME$;~lC z4~R9#bUh%cIck~bHyfT)u_VtQfCf06V-DjBmErk3c)piQ+ry>JacTA3`3E6&kC&Tc zFX4P{4|r)b#~j^z)*SV^_y2cucv(;n!3fJSDwY(~KcNA!Jj!Ch7b+vD2!aZ^w17+V z@ra&<2+>McM@U2@H%CAZh&6{#4@hc`DD(U|C}W;eu_Vvmf(AJJ5_1?|s0`1u@I39( zk}fUIJ%1ab!s|LMJkKTJBHDsJa&h7M@E;ow-ynJ)7Rx(O&tjosNwIti4G7@_76QId z8L=!vEDK%Qd>+VWIA0jZLJ^4E1oQt`9E({TpF=x~gNh}^@gHb_`(HEn@rBBWqZx5D zxwHnCwjU4WzYrB(+)W~sT!Yjm`~9(44q&nT4D~D)DwY(>DEtf+A=q(XgCUg>OFLp| zb!ja;kS%b&FpyReh}Id55 zrf^<*sNO2vfNkEo6LGW`t<0px;j2|kN#LxcF z0DczX!1$pu__+Z5oafTcacO69ifE4c#e$+- zz9P$^b99~=M`tNGVjJsRtmcR|%E?_MIJ%H=)Q+=^BPy1}QJ)_8K{zmus0@y-1V@*< zw97a_{W@+yKMdkfNYLeaY%GVamIzt}qF5bG4cuwh_)o z!OvBUpEa<~_@QD+{Ny*d;Tz#l8T{M=er|GUH@LLxIYrVYI7lVh;iizHn-G$bL$^y5 zok$ej<|^!sZxB}aYV(EI64m+ z5b+r}upFW?IJy@c-Q&{k;soV4&5`!RDJ19~JvNp@4@d;jwmI(miwJr^5G3bNUI*jn zE(JdqldcEU{Lr>Ix%&k__c4BGLmb8r6-(mhT4(@2m*c?rp)&Y+0{lGY(jMXbY|?S2 zyWc#9c#H&kTH=T8e)CjOKmD}eCzr3t66g_~WFp9V{%*YM!nVJ8TFn^S{^lvc*prO0 zn-B+MjEW^OcDK&NZHy>TM`bYf0vLOa)0N*N=kGd}w!kS&r{|<}dRd~2cFA$SR7BUy zf-X6o@;d%^w%EoxFRR(2ZEn)e| z1}E$p9hcuJhxWoLB|JO8W3S`D7^5;6`xuOU#OZoZ2feQ!KER=nu8*Yr`b?thLm=Is z7SZ*Ypi9oLypI1pzy3waKU1^y5oEbf1zVpmw*HN?j4djb#MbxF0Jgrsfw4tpu=PFI z`qrg=%?bNK$Ni`ue!`)Uuy3XO`bi?}KR~*FEb8BX5`^XQ6>gjJ490!~W4~~^HrGL;^urc76w>vJlwWqY zxNjK^q}%2$oG;kjd|_G6ue^@`J-^0~a=RNkhTq4Gg)E0hAI9%4e`joMiL;C?Dwf1n z6*PdP$vCk5qB7Xp$&E#Ix3;}o+t#gZ?KT$Gr$Xu;@0J(UMeMol-TD~G7S-{cFRJ6a zv8ZnOX4XVE`7#YgSWr|fDX7`d07ZN+DJmnVDF|w^Tbtz8cIFYyp@??MN2D*Ri-_db zoTLXtQRQ~l1Co{vE12hV4bQ1qlIIcK^SznF2!YD*d>TC8)vZ;zHMd)Ha_6Iv7BX z0U`9V5b%Y{h$Vnnd~R(X59AP>FAT&d0+E|w-XDu2$l_Q7?JN!|mK4V^&;a)jWA5V% zl@Ui0am3wP)UAbiD91unm`!mJN-iq3N%)V&l47wO2lXr#DwY(>I%q%$C$kXnh02I! zK4QtbwKNapESxV4Br5`u+a&$R;#k1qI2+no98@eRj?19|?qA5<#}_Iijt0cBpIck( z*7oJ0T%kj+)DKtTP&oeXr?(1QH{4$ue>Vc@ZgLl9=Kg|(T)rZ^#1;!0a{JQwV{H)OdLf}iD#pL=kY@k7Ou z_<0N(z|Z|Suu+1_;Aa5*^trWOx7N)mdR&J-p&y>ap^&0Jgk;>Zua+o!3P|@Vcj1+^ zT2PeBS7bTVtMkk_>Q-<>`**olt2ufGvfL`c(IDgKpE%1nqGCxLy$KEA=p`H&M^pw! zhl8WT+}fd>Ali}(xVQDgJ2(^)beJ9+%b_DBg5CwveMAvKM+$=E9Lnop{2Z#_=RMMO zq?(`iAh_!(mSe1NlzA1ao_&)3j^xIe*x@k3?sb0YXT-mM+S`T0i2eXAd6!>&Sp zjz>I30-Yl9^F5I6lZ&pgQv^S`d_|T($LS;!LDu8EvF7swX+K5H*pHCqP8N)v#2EVt zXBlHuEQvA4NXFPNP{bIcG8kJ2#?Ih$mFb`n`e7svg>;=ErPDbQU7G>vKD&sna|B&- zI^}iz?`&;O%Fj`=H43ua*@CUJ7+YK5EMtp`C9$;~G$6mW#DTFzWw3QA*t*!QUC0UB zUdQdAA9lo{kg$uT{MsN9MjNfUFDttKHVDFU`HC#RF8rhUwG(OIpk{0$WVy=(W9u1X zJL4>4jEW^O=79zNzIl9S?*fF)-{Z+={U>SqGCyG^*{sIYR7@GMP;z{HQ4&nt$ps+ zK6Ps!yS0xvbF@X3`&+mBp8PFSgkBE&QZSJFJfCTFEBI-iMta@tV>i8WOF!_)eT37G z(%s@$s?B7jyTVz<2GIksn)}vWyg{^nCg3+Vi2jDLG6*nZg^DGyauhUxl|SRaSfMgl z`30=}*RB2J)_!nn-*HN4M=CI;-$EvckN*lj7Oq z%RCeY+7L}^_wc6u{r_y*;yw5_z-Vp@PjS=gXGGJE@=zd`1I!qqVo8kL1PxGhH4dz4 zsSHN81tVK~w5>eamL6@4$5@2A8PdY0-CEF*+X@^Q_t;zNd=M#=!1;Y?$KWh7U256w zSRA)NFN=eUCB<<+G$0OrqbYo$GUE6X;+W{sCU~?Rcn}XjR2alW5rmwd6O=LRFf4{i zEQSY-7^qlM4A1E?Jjz^03{*x8yCQ}vkLLDhPLEdM(aL!w&ja9|=5aqRcRp1jn4BBF z(lm-XAEzD-%g_puq2+owCY?{=PS!8OUT)g3+|ckehX;P6X?AcGrnu-HxU+Ath%W3*-|h zW`R(#q(I8>b6x~On>(>UsEk1T2*m5r_V#FddbGJ7Z8nc(1OV=!$New4VZ9=p+}`lj zXxKgVcv!>E6%9LE59fbs*io>T3l3{o{fubX0OMl|fEgcDEQyaDp#gl1!-4TZW$=*# z9|?~Z^Jo!|7UE>kR!-nbYS@HeLT=cYP6TV%h}5tloe8O7(=3pkpqK?h#gYP{4V)0j zF3f*?p)vw#L?BB&+7gep$fGUvX!AWcRa_%{(3M<@O)e%=#J8%uS4)-2rCoP_ZO-_J#(KQo~5W7b=6DPO!7w zqqTdqR*%-=(V96mY!jx&d`s^`yet>I$SvKj)52Q1Rch%L>3g$IjMVA}vbelPTvRM6 zF4}WP#LbC z23Jqqe`&XKU@~{cuy)hWh;}=jk#R1-j0`H4 zM8*ba00$T1z}k(0N}o==&IWw+|I3+TJI9kdbx}A{)28d zFTiQ@o6W-c-W{-)yJ}d|>1RaKUCH>!0nGTIVo7|^WMlgqcZro0eoEV(KdOs zYdqRUPR65hubN&P5o=6bgWGx_|VV}Bh;_gx;`sObbO zrk>|+K|n5Fk!t5|l^D2LirQHBe3O*j?Ez`S-+p)tvfN!B{`SM2jH9=4mT^SIk~pHB zfI!U$IIza1GB|n&96jLC?&Ab~rsF=>4`1L=NYDd%Y-}a{5s9F$fOJ1xM9?FGAUQ+w zI@omLJ_SGDkgiA6{Co>p?qR{tKNvsX;Vk2aiY4*0MSddz92h@T20w3spEo?(YaZ}^Kbc${UFQL!Y-CPM>KYDXLxWmE=bpMtWFJ=#Ye?L*F2xelG8 zA1ZJtHfTkuP+2&a#rPaFuFdH==xAWmy`5pj=I`;d^-D9dm$G$I+ z?$K3+e2uB1t{I@O#>yF%*TLu-QNI}65g`HC#Vw$o{6lx-tXHeNy5N>aSDnzC-lauWq*J2A?7aF$U< z#gZsH4jMqh;W#kLs0_+npscb=n^L7s=6umcU4S01A5OrbkgrNTRF+{?5??0*>Go7% z)mxuBETySKmBd%RBI9U^#L;90M<_-LrV5WZB#vq&j`9^5N7E&a zrYShOl$6z~Ia&`{u10WF%{aOYXBkISEQzBWG=QTUa9|u!860K6QL0KyRB5p)Ey8KK zQ%B#WAMVDXkfs!(GA_OO5>592>E5TRa2h^eqA6dIU3v+fYerd2qAa4I?C+#_zM8Uo zA?vpfW%`C__(Ek+)(Fa$R%uJBv_+h+r*-Hv`r)5A6!NuH z50zbd%@SYF0_onrh_7bBm)yDMbuhY?NOUby(DfYYZC2CuJY>231zk;yt`~5Y(M83Q z=z1R-z!L42#xjh`psO2nbyaBxR%t7$w2msRjg$6)Ug1Oi@Gl$+N$WyjMv@&Yk@gXg z?%t}x1+;?&X}NqwmShL&%rn+jNUU{8-`f-n{+o;(tY+|I$a1}c!5+roCpgO(q+&@7 z{sawR@Jk#RgH#5Chk?OEtF$#$+UhE8kkj`c9sOVZ@G}mD^c|{4&T?)@qVE?V-G>*^ zHzeqjb1tugvA0HIY_;@#P{H1>WMfFp-fxiQ4j1hGm9h6b&NB9>SQ2}*&luP%-goSH zuyNne9pusvZX60T=`<;m&XO4M0O?*= z#K>8K5jm6cItmD>qWWj4387ula_a;kXEH))H#C+dR4j>*T4+F)(DrDI5GsR^i$TbR zRoeNSlR6zoTaE!f8;3$pE|july~N2JAl;W%6|N+%7o6ns683959BnuR1}xvK>W8yO3<+ZkhliY2kI0vZrmGY*Ue zDuaaw!NUDj+PziUJyqIWoQ_UN-FH^$F&#iL-7m#-Z$3TfLHj*4WmkQl*N0eiwA&bqj*2BkcL+2fI@%G8MMq^s_avfwyh?ktN_&`xwgw`Et%uf1 zp*=1_lP~H=^&r^r@UZxvf1L3Y^Zd_H#yqEDNuD1E4eOpcqx<9Qd zOv%qg(7Aj?)~9|bBF()ozVlJ|PEz)nx@WlyvfQVlXZeJ2bT`g2j;L4?M~^@QsJRaZ zcI{Ca9DN6lzNyl_;siaa;~vuwkK<5C&^LNKY)bc|M9>pJx_>Al=tn`2oE3Q;?3(>b z!OxSV>qj*|PeGRZLGbfEbS4; z!`C)zoC+d6Q#IFAt&+1iMTb`Che{j@S@h&1 zrG@Ni5{oV%-MbaBI8Csa@1)q!Z0H~oU4q2Q|DD9CWNn(7#9blF?IuXvm65m`&N33I zSQ3eIpaCS#z=4rSWso=rB-T&WYNu+|Q?;3#$GJLs5B;zw4uw3{BUocJ+*9IlZy?=! z6!EyH;4x=Zq-?AejOD5Yku$|Ynn8fA2K)RzvT*d^Ka!wjL zC@1}bO79<~azC;eQ&YJVvRqV98DUg5;4Gt(ivI_dLpRv)Z(QRxWsAnzw#qp6nvk(? znX!*02Db!zS1b-|*DcNu7UMGZ@$MTI=WbrK_UM0j@ON5{8fzQ+$F^V(wzRtO2F>94=h-f<|!CrI)MkU!>e zuO{v1lJ=b>;m{F!7&gz5M_oFW+;z-4a+`9XCQ7I%R6I!!4?zL6TuNI0B+2P5>c>6q z51ABn%ikv)i|{Z|T_FF}O=}rgxyT zr@Mc_Ku=%G@^;%=hi%jdTji=?1~?7aOoU&ckV`ceA5+TW=es_iyNoF5@m; zVs7^$E4v%ib}zTKdjq$79e^e+axFwAUF_8mnNo2hgbFHd!f6XC?&2=pVQ%*}E4z2A z?cQT;_c3nwVE|32cnBgBDjtByl#0h8R8a8*PFqm%0(a?IbGy%2*?m!M_a$q)?{K?s z0%$_T>kuia*wSHlysNhRp0(YNx!r$RDgQ*R{8MY?-*e^P0B91_S5|g^P}}{{+U{@M z?$1`re^)EFm0M=W=yGHFv^jt#L5+mSw57&CsL0H*)^@k$cE?*O-%hQ3du!#>x$@l# zfdzBIsgRij?14xbu-)#0$mA+TH(bXpS6f(~X|8^EOZ7gkes2r)dqQRs*j#hVvn?&h zxaF{g<)FEGzoq*5Tz$queF`#@z!GMb+0kx6db9S1|GxX$}<+F}Gcl)H3@x!qM(cK@QbdziJ| zP05qZE z0*I7U&|th?ZTB*3yH|6&S6V5*My>o>Yvs3cbIPx9pIa1pK?1Pj>sS5cvl?I@u?w=BvY`UVYmOx z<JbMD6it2(2O-#pQ~K zc7V_s=7 zj;k+XwbE{{;WEke!B{|JgJ_JK4qKQGLS~Ykeu##7rLVMkx#c3ShV<;*o69B7jO>g< zXx5esxzqaqWyV(qG84~I+_KuU1eXu<49(TT&F^nvz7aAL&Xz)C;@J{zS?$>(E?0SW z5cg~aaAw4GKxX1u8$>3aEwi*dz%3taVY$a#{Yp#qLtOn~7U~Z*SHFg%T>Id z%*~%*VSX)SCcGXCkqNIybIWSaj^y%Tp4lCzKxlTAoXed)3n;T>I1@4x&rau-)t;To z<-2(OCdAi>|%&aJiCxvR(p0nmk;yI?zj>{GtO?{PG1L<8E4l*X5!h^ z+_KuUtGIlaXW%Ty&EIBW{uangIJ*fVrDrtY-wB~v;P-ROf48uFx4C+F|2Wt2h=q=S zKxX3ogXZe(jwc{A^Zq$*`56n#PnoNS_pfsuuK;J_;Y(&J?DiKR(x(8!TGsA(1HxkG zvHtrePD@Evy#D(Mcj+SlO0{e^A@~(b{fVg)z&vRhZiSjoVdUoWF3nf{zi3cuz+sPJnpPFwgD<$i?#G@&v8 zk%`Mbh^(lb$K?u_V-PA_j^nh2%lmSd=L2ZsSC-pVQ<>&+gqzd`;Q*RYc^E_{E*}b!6_snaT;cLj5Gq_g8mBE>K83q{5`e?}(r+nG;C73s#4Y7o zE|YxHZz=7LQz2CNbQ(@u_;e}v=^_A4XuJTTVeabpn&&}edUt*fgjO7%#pO~w#*OHD z2o>>MhSL`D{Ef%62|yF4uYt(a>5ULtIejIUE1bRoLWR>e;3^rS3k)@{mzh?1h$j8 z6&s-3hP+rL`t38{-y6U1S|jOB@v6lFj2T?P+dzu9aP{+OE&qZi?HD18C9^QHV?$A`Fp9 z?%N${2o+RhaN2^3CETTb&FwC*vb&$!?ow;JE4bZu08OZ9g~)`87Kp3{)@CjrmXmfz zCxi;B4#a5-ss_2seE^#H)ywUwua#~tSNOFGLWN(eaoWPKW4K>O0%$_z5JV;}{}m!D zD*wXe3YU+CP~q}%IBntb8QkSl0W|UJWNueY<%wLb@as$n6@IP5X$!w5x{QHqM^^!` zpcma9G83A&g=knfKGwx;4Ux%nYb;zDgkeLKF$J}zgrR6BM9I~(+Fjw!hRKE{bpSDn+gv=zc zxS3@(MO)0(FSJlU-%`f`Tt}0Ijt0m~T-?u6eFs(M5a{S2BCtA+i}{0iu<@r_n6zg%gXNkYP%0u+kKMTeGEVoDjtDINd+xv zJf*h#w6)zAx!vcil)t1_{<5|5ce(Pn05l2e4J*6vsqMaRZTAyy_aiIipQ@FAX07}O zuKZg7O@jK`%I=S9yFXdm{hizW#Y#E;p0q0M?Ko|b_7mNFPFM&moD)K367aSVDO1yK z-x?y5tCZ%1-11}#%ahF2?`)}F7 zsj%Dkg~%kg?T#i06(i98IBjt$F6S<_ncH1vWp{IPIRh&%XmM2fMl;1m-liT){1?lcAi;hXrnTOoPy@HR`z2 z)j*l0=}gE>DBqo1R(qy#`7qCrrU7o=YhiwG$V@of6CxAO=5otw&t`M^Fwg9cAcSU| zrMc4ypv*XnL1yAvgj-g77UJ?@o`JI_ZhonS`6ZB*luAnb5`MD&K~!>&(9HYuxaG4gEUzCJpflL{=&C5|7(f%hKH_%O3GyMAEByK#LWN&n;IxHbzi_|)1E2|&KSE^U z^7jx~QTZ*GD_s5+LWRq};k1RzTT~gd^UbPE{Tcz0m0u1nSNJs=LWN&raN5GJow#2+ z0BAzxb`Y6RxeY{CE|2GOh07BmRJgn|PFuL_<}OzPXyVrtZdaX^let{smj^%lkm6 zaCtsXTe#fBU0w>HiC;^&T{V@9xLo1a{tznsYQ|{`zk0Y|T>zR;c_2h4F0X*dbY|EA zp%u?7?e@DM(i2ZgEP7jsJ?D6eTYlWa@}uVJ zAGTEg3RnN4h5F|qGYRZjbIZ?IT7H*Xe#^r08|La?vsC{HSN{=kCeD9ouKj&;?RLkf z5GpSB&v4q}a{r#Y^o_aQudM9;ptk#?wcWC*#*EE2)s%|g%w77$%B2xdsi0ycPFqkh zj=MAlK$8n&3y4fE47+11wcYX7b|-PW69F{IiU|;zxU>UAR)fTLTt4htwmWu#P(jsX zoVK89SMIV0Koh@Q+^%{CQOV^BzjlLA;ny^rw(x5%_p2U26Dn&VGI6;YA}cCqa=F6g zJs?!LyeCduxE$dw2LUwk%g^nqsq}KW!mlWV3cq4FZQ}8Hy7VpA#0Jht& zTWlL_ll0eZO~ZlRal>L;XLm;rNoX|y`}h959VBH~ptuW4X!~HhJ-67ls-t4*XKUE;QGe4!PbMCdzN(!_P4fR$Kqk-)|TG> zfu8PmZDmXUKzm=~%KlZYjfd3LG|q4DYH#UpZ!`eYd)t=TCfNRDn`GO3``JU~XO+6c2D!-|C)%k73?auEiHaUN+IHmH~%6purSH9)kPno3Seo}d>^RvoFonKde?mXIgvhz~sf1Fo4Z*bk{eBJq&^FG(J&XZg(Ip1-;?YzeI zuJd`5Ij&NP#I^K1*>jc+buG3vlxGr)%;JVE9kZXhMMc3u7n_RcM z{^k0+>jT$gu9sbJxIS^c>3Yxgmh0cH&!&Dgb;to4x8AmVN@efB;89~Q9lK%dS7W~( zJ5+u|`B4b`nDXPw*Ong-0!}MG9aNlEes=k}9<^2!97;|GVPjiccy&t@y0s z^NKGjzO4AF;_HfUD!#4w4h`^Q#m^PLR{UOZROK-sb#3Jdl_yo6Qh8eC>6Pm$&#FA9 z^4!YvD$lRHu=1kHODiv{+)#N%Z=Q%HMUgW$4O|ikb5sk6Qd4uyt=grProwqyhao+EI6b=esUM(_P|PkH*`8hP%?W(RGb$lk0ld4QRw$T(_Yi zb7bzM%~odf zcC@z)OrJ61v@-ip{>-YLuIVe=Yz|y}`kCo%eeJCStJ-k_-2rOZ|4LsA{!MS~>~eN2 zXXmJ9nSCum3;r?8@-B9+44-9o%yf(XF-&JSJ4;!4Abl`Q z{~C4%yC*@C6G6i9@@s?bwbJ-)*1$+s$LIc=g)UrVC!Wt-`(Fftf$sZQG9B z+(xpW|6{kI17`nZzUc(9J*}9A(c^U<@|+Xy3}CJ)!g+1uy)4c=?}Xd(B%5u|qDVO| z&pqL=f2b{XDt#0GI4;jWNpAfBe_Y^i0z=<8F5d=p?!6Y9ZS=ZA2RSa^4usnZq<{AP za2yELD1ke>+WY2K1m`wp`+Ao5wX7@;<4k{f)giO%rZ%QJTl;$YdpZWn7j^azwse&* z7#M8p>}i}eW9FR3K+npRgWa72YZ?~?8W;BTboDo;7U1j5n(4FVOs}3Xv%0!*S!Z`+ zw5NYy$?Q5ddbG}(-qzJsQI6}!rqTG;*4bs#I%r^e=8K2!9X1RV4^zgdV+>0zeXT1R zQ+2Zw>?79QKalO~?8bmKz160*_4M1crJXiyv8~#s^|y7UdfM7;T4p)^58(f@SvD;c z1tzu7rbQOu{~DVX?i|Q0J1{)h4F&r5V9P)YzW4k;4xWbV&HV!{1D%C~DMcVV-?QvM zSZw=$v}ih9Ywdk~J$-%cy*+&cb9?)c1p~IN!;>a1tFgb&hrX7L z|2(Gc`?=2DUi;TJrHhUUKeYE@ zp|3uPe>msOXMWyko0U^bih5=H%GTaB&Hc>15sj4(UUGS5_PjlIy?W7x9}nK<_tKOi zVq6M3i@TiD_TUlU?Q`_6dq%Fg?#eO$+2)`>rc+XN$syxTo;5d9eaFKS7CiV^Fylpe`z%l}!qXUBi7>ftfp+F+&ZJVh8h6FGX z@caD!h|k+LO92cEU^3}T27Cd(x2;+Mj0j*h6iOr`nTWToMgfcpU?v^*$D)a-x6R;4 z4kjjmsYo=H4n;!VwmOBzxB#ZJk!U6y2z%S=6~Kf5#v_?@((j9VTU0zI1u&M)Mq<8D z%-f>kF(rVBP&%0o#**F^6_05FOr}%5Odyr;wy1c_2w*l4^G8Fzw6{gYV^#n&$#^0Z z4yC*;DjxR{K;&A~ABknXEh--83t&2)NCl#)jJHL_;{pz>4kbhWbR?ejcJvxVj-Z4* zUr)$|0*O{hWTNQ|kOq@7a$kXr#-mYE3#37%j9es;5nm(~3x`uc8eGcA#R3_~2Gagu zJPD*hri@%7kikeW5(uOdKpJey$o&M;pZ0@Je;i1IP8qpWAVWT1$QOVz-p!_^)1wze8b+4lYtGMr2%e37WP zzr!#tBbx;>5{rgY*${dHCGr4)%qG);bT%3A4)*uv{gidK2xKaf45yRvxOdeum7mKv zvL+Y|L8U+BZEfKpjij8rU_9$BTP3J36%S;i2|!y6tunNYL#rd1Xg1+X1-vVjp0*2Q z#_vxDqw%n}Q;F>0$XWh$Jd)1%!rlRcP`Q6w&Vekq@ z8S#I=&VLujR%a7_UospEdk6be&A(D0)7fY;lL*I=&njd$N7nd*zE~&}r+!4){5=Ai z4P-LW3?aFrGF81CSsP78ePLgapq)HZUEwk8zCH5CY`jMlQ+eh#hn2a#53 z^d&8A22xJ{0gkNkC$d3bHtZ*4Oa4lcl@1DMIuJ;p)5Fl!*4C+jt`bm$gk<&k2zsyr zx>`VE{%kN22{EmQD4>UMXth6+jb~#%3^(1XsMc^~O)?#iM#4c*)va{(&m3Bv3Zyfk zKp^UE>F>&$m#I2bApIC_qUkI~WZtSW@-G5O6QFD=;$60)U!n3a0nDU=sc<3`^)Bn` zQ6T>+kjZo;8xCV^TDHRAUN(NXKqk;dNBs$?R2d%uy)XbCf^^qlr{F2M+;=wAB+Wq8AQHH<>oO0 z=}%@csZ6GTRQY+VKq8gX;UGq_Wxc9KKTaSqG@*;if~1uy-q#AGKM{+B(*amtu8RG5 zfeeLxiMT(Fh`I(8ES(@Bx`B8$@jKSEdL`zah)6VIkX{vf)WWvwfg=OdCkky8aUk&VW}X@3CFF4f3*ngoqx z67fhZ1pDnq^s?5|1vC(hN2300*1K$=Uj;pbLu?LE8@*Fw$>x8lLXcho`dyHk`?35~*lX2M^{Mlfh?maBU)u z+az2p0C#j4y@c${&C*&+eHeSr3)j`~}g?(Af(^edmN6Jbs;mDe#FOW?n0+`OO zI7p@RQVy+7Br}*-VN4e}BP(4mknxy57LMcAt#zep@^KkQ)MgmSVG4dB*@sSIkwJ^d*VbGBXDc) zVE+ok3HbuMMu4+{1Qg>Ije!j>Wbm~DobX5CF*O-!Hr$ZGn>e^SlE`K=K_4c<%Zw{Q z&V=g((jV|8v2YRtvO|%G*K=e|FoGc|6~{f0mo;hdYgcT<5_fE{uH2mP9Q^X7to+D z>cjk+$l{X%8G46+#{J8QCI3@06f{STYvHWdp4$ z=v@LDPy3>@Rzg~hiGi&3ZUN0?(?OpvNUg0S!e1*>E-pt(|R2k} z#~NbN+umbLIpoXm0gkN6#C*PJGMpf!s`Gr1L#r{Lb0L$-4Wp|(8 z(ArEe7>&}s8{FksS?!Yo8}w(fD4oD6V4E8Il)z?j1CKi>VywTjJI}7H_i2HR1hS!E z%1@yUw5YJpaBN)w_oU$vZp#^VMP9KyBK(tstCKNbAe;r3&$dNrSu%U1;91I3@tkEIJ*cSvABLW7HbeQz=E=k6|D6pY; z#FtKCmP%Na-j@V69>PsPECR;huj<-;nPY1*K3^b!i^_0vo{H zd?*&6$nb}G75Vt4z(ymfP$WsqM8K-_zQwUMnGjMp6(S#$gYMfLTAlJ`BLSo&poRl- z&-4yQ)?kIym&nqEwyfWnpvc_5%b~T=K-z~f7mLogZ!_-gWp3Z&*qUSvix45)S9GWc zviAiPi_Tb4O);p!fb78s0*c`-6HH=s>QIlQ9|~wDnu_`{wI!%Z>%RmvmD{sG(M-;NKiu=Z{3wVGI$#b}#2X$lb@s99$bng_4=9kGKU` zku#qNY}TJn(ZV`mxn9|cPX#s+@X>vUjx|z2#(pNS*>o(9{*EZ?<|`dC_H%(vWWqjl z<~mlT_X~jy`vQ0%8N)M`W&J#HWxZc=Y)v8?QJ zWa!rd8uBN?QQYYQ%EvPq`VEKHrXzSPn2n;Z0o3U8WoN(T*qRJRsbHMCXEC{#)qcmJ zwSM%@c&vpns!jCzvfA%Cwl1E{q>>RDC)=cMUrwAK1UQunhU4Kt9&Dtf4E|Ao`p$h{px~44y#{)}TSgZZ5EqDDJ57$bzt(Ul}_}V1sydAnQ-+Se4!_ z1U3`Lla;U^oh5uQa#+?onq%w2=}?$WkqK((m3bJ$vGox=ch7|M3tAcqNl?>sAn80E{kipwC(e@zhJk?#QwA*+@Ez1wAx0VOJVYN#(SdAkdf{M6kjSikG(!v>#%u zX36NCBy`#r%3$e*p;z)d9T`25qiZ6*coGc)ukn7Lg1DVIv@R3QhR|CehXC#Sa~>== z-k$_G8AxV*KD=+z(bcnj<_raR5(n32v)NFD`Zi#Vg;<%nT?7=%U;c0?27iGy?g(V; zWR9&5CliTqB#7HB!tysoWG2cvx+W3I#$!>ead)ijF&;(ADKv#cYtxAsp3UG*1VC3A zJ%H>)1;^Hf(&0ch9!KN#OJJF`N&ya|FT@0oZq-e|P7bb51|oPmMfaVA<@LU{S zmknc#j?mCVXk%$u_QTD=HPJK%y<`gcxsor$$Xs|hv=%Q@VFFDPtbT!&xu_D@M8=;= z1z2C9#!ltfnmF!bu+WJsy1U(2jFDZ~l|yUe{$w(oqW6Z-rx;k-h1~=;6vS#wl=8Ao zjh)7^HSt&m&nMF4LXUCL$u4LD3XSkKh-;&db1OrqbLecm43+RFbtrxd(r4t)7W7={ z-tp|UlifMIHWQ9v^@OI6{VmE|o58VlL0`%riD24>U!N#PrkNaDAIF2m1eS6EUfv}- zH#vJ|33Mot4uxoGj?kj*WOOx0*Wl%gbTCNk9AZ^QW}}8f>k(NZkf5nNpkj(HE3W0} zTD;)rk4LE|1X?vkuM^meKNQW-dS*xe!F@*8CTB%G$JRw7@euNY9G1ZH#W7oe@%S*`cRL4)OVwd^5cdc&c5i|8hu{G2-WgVqe@Dg4y z5~d4Oy*T9M*czF7IYB(;@&{U1_d^NH}--Fy6XT|#X(45qp>(%D8;h~VEF`0)*BXBOp-8c;H4PC zs`N%UwkDN{;EoEDBr%_o`HFI6bsCT8@vbPfm~lDCsTku(ycLH#OT3x_B+pt|X`DlA z@yq~|6CZW|B5mcc5*%9-_GL17FNd&vqA06P3Mkf#Q_&zp8u81>lt6|tUgB82-i&qI!SnZ)fLfi_-*o6X{#nLur4m#FI1R1-p zz$SdYcqYMk5H|ucc9FnlgK4}W86nQZeSnNzEU@WBGMq_b64x)XR)#L&(3%jYA(?E9 zu3etCa#QRlpm@L#3PdvG!Jz6<%Tf-l4dVsHSSUlSCa|&x4FVejvv@}l4bi5?HgarD zG#-zKv8d|p5YHH7Z<{!@HtP#wa!MU2psKNKe~ztBB%)!=-O$wyw0DcU3we}m=IA=i z-ePe-jeG-rExpFluAF8EaBzJjj5$LlglnC^{JvgR-NMncgLr!f%RPCt7<}Z(%Q6AS zu!{Lpki(73PKLJ%crcO*`f(qp`yz%Q8Qvz~k+2^fJI&9?b@7NohPMlNG8V%mjpi^6 z&M#~k-ofGZG*e8*!dMbuaAUDbCT6)nC$Z?A3gQVmL-X-SMz7%L*-<2Q1g~i3(VTVJ zl}-T<2k}A;z3on(h*3#KA1I+C8LT1V>1-aZBK;r%$6Ho-UzAddl=D7RR^BDhVY~?w zOX2Z<9iz7 z{#ZvF%H^hC&Ea#f0_n$;kNP$!mjeV9pcbbbjyR=!4nvHXUf zC}|`LAE0IUp9MUIH|+6_J%<~~BEt_A@HAHIlR@KJ7DJf~|BHaf@K$sjzp^lVS7|>? zz@vCI%omMg8c4*55lz(xV+11s)yv3Lg$sQlY z(bXAnfxgY}Jy7}n+tC7<@?-Lz$i}?~D&IvtMj+$(c~vlpCo|Y1A)iL_%=K7~tjR>9 z{%8j85p{KT8*l%~VI9Yzb;$e_)xh2geI! zCX@{)=vQN1%BW7@$eJh~>89}_k5^jik$pXpLu=z{JPFC5`y!}8fjnI~Nnqh+8n=hK zTI20%8GEw8260Ca^21qqO-RO`BCsiXr9O=X1Hu|~$=Fi`HXX%7d%XR{u&U?9rwMEZ z;{$Hg6AY_*<>YjZtxH5>*<=bo@*^K+8b6eh+w2Sut_k7&$}Haa@M68f&@1zMrhxkK z#w4ck&^y?rdP!-WfTqG(yzUWCdArrW*f@(rt0Nf8!XdCAR+{9bIh!ME=-FHbZyOWR zSUQ$nJ%>Z9@q-0g^n+5Kv$E221roozi~I1Nd3TS|$;iO-IB-@NZ=)yij)Rxqamzm~ zI-dipF=wY=V@3cp-lURMUciwxv8*qh#FC@8x208e9bU+x)v+jkgA@!0yuCcLWu+H! zWF5MzNCv-Z^Y(Uh;YCfwn)1aQT%Qi&w>5Ni>0slck$bI6IC{1p(*sQ1BL>=7S(dx- zOF6tgOurh#iw=3XftHo8=jgg%60d9F{d{k4S5HfuF_DzB_A&v+0y|zEzz-f6c(o$P z4IEq>z@lS1i1$r;yLy#BHM(42!^v12zYGB(z#4kx>-P$Q&H6CO!_)0vy3X=0$j~b} zv>rVOy=)uQu^q?)V9;n|Rdo#43MhWZUZz2~6R= zeaH<08pjA3%^-aNHMGjm8#%N(M8BlMvkq_HfYG$F{hI_b9Li?>QT*($Z@}PRM&2xt z@l+s!5e?A~7|$VO@*#l?2l0Y^6xrF& zUm2H?{}4#@IKfC73()<1nOH_XERcyb=5LsAgHP3{{fLD0XA_|e-eM7psj|*T1u~n7 zV!aP{g<{=PMn1-oHFyk*r}-dWOo-)v;cKOsW zy?Hu~SF64Kt6PjIuB`Q+99oT8i$9*i!uNpkw@c4*WDV}ggV_uoF45g#zI%|BKF6W8 zc-bg`A5aAtRQ0~W^8%alqxmD~AV{r|EAk-yg1};aiAyRNWLTq%lCdvxY@I)ackA&w z7pdi)lsxLbB(T_-BZa|4*US4U8T_&UXQRWSsef@~4SrvS?Qr13 zV0V}5mgOS}irxg<%>db}LjKN?Gchqvq{DbEexC7;kK@uSY@_mf_t5@zO~(6xHTab^ zc38m9EAyOza6f$*Gp><(9kwS0>Nt3v+GHXbOr`P5@Og8F)!Iz2#dcCatu1*i{CFma zM=DunDd?P$?~_L8c(&UL@Z&gsRuGTqv3MTTJu_xFI-Knm1o&1QJ~Nq3Mngf`E+`Kz zig~<%rZ9{ov0&phMusBj)*Lzu?-OEui{8~XI?=L14<>MIZ6JWhqIm00=cJk)^1c+Y zqVY!Fm)*WFwvg8e8NO;IcA`m+K2*a90evHTcrwWwx2uQ@YLMzJn~n(9`Z z&9O7EEen1ShMTWE(ysgS(zbY+1^&$8$fVbgT||7bC?g@lmZ!xNE$w zV-K#QJ|4o1A`L7p+_)b&}a-9}gYP+sjmTy1qA z7E5A*Fq`)=A5{^T3pjozZkm$ld>9k4Ji4e;S;Wz^@ggX_OoP=H9=9HHzUCIXU+lFk zB-0XJvktEdV*ZCKD}N>H;pM9pT~_c%R7 zUdtIs7+=E351#r(-ZpUsGqVZ2(I3bpNr7>p6tS|5qi031ET6=WTnUZV!X7tOGv{j+g|(8`nu%3?Jf~!rN;sWI7kSmg(X&$+g2L!=3vA>wG+()h zfP;DEdVdzXorE)DaFrO$S1#%}26^SWXgGmYHoO{|kFMYXD{AXCyjnf|Km)%iA=0Bs zYOuC>Y$!sLMU8NajBenyXJ=!$sPR6ix2<(v&FXoz1xAYky_{FWRgJaGSPXmDNfoI> zIjFm5b+^=+6kW+1xr$j>&4`3>E9RY7W4uOD)biH|a5#W>R4@_(Y;>nZ;7tOI8!>7@ zv;yx)i@-MsFn-{JD1zjMG2<-)-z0&9Sz6M=byZ``I*P!z2yi+aOX4?I$krO;hOh{H zI|t9iU=_u@AcMwNr|2CVJ12nEP(0CM*J-}n!}Z2mT@>?LM(bS*dv1!ZNwvn`J=>hhlD_!_+Kk?}|H6z9M}{>-i529rapvFQl*{J@qneSG^Bc{=<&N7h8* zu?X((ecnz1m6g80p-4Hr(}ZCU(>VOfyt{Qpb6ofGNHkPZJv44vk++w5meaEv>rSOH$E?N--6sT}n`LiOG9_0LEB`8(N~ zS9Pq;o9)7$^CL$PZUPLROkdJ=n{CmKkDlhWjc}YX!Ct+SeO!A%o&M&+TBlI0H*wc6 zv^%PbntP+>Aq6#ii)x-qHM>UOV-%{3nlaQ&O=N!R(G?mzjjC;!fR6)5^J?czum>mF z#~mP7EB5qssyJ&RJ_2KGww?4C^A%k?!(M;)aAI}?F=tT4`YL=>Y;Ci-sp3c?=WAH3 zDXb{ltU}c@scLE}K3+yu4^`cas&2WnecTFG)iBvAu|r1JQOz;a@NpmJtj+?XLj^Sj zJyh>3s`r70kMFj#*|ul(>?>gI1XMzdhCNYhCTg8cwQih_k5jg{*|wuvBkV({wW+|A z93B}vhpKHh6CeNDL3Z*tF!NABO}X)@=DAe!?OFJkh^7?bO@z%?Sk2bqo=!)_^Qht- zHTX#Hl&@H3G{(n;6=j=L^?a(@TZfOa$O2}QRVAC-Poe}^U7T?BsCEHWo07uEYL}ch zV<*|iO_i(3>`=uEsbVgTkF48f+nJH-K*CYQd8}ghFoSbZ?;@(VIE#;|9-D2V-t_r; ziGq5vMXGr*)ttKzJ|0BPKNZxRJDD!2VOM?t)h?lGJq`HS0*NE8#GNPON|dX~_Nd~e zRPnb)e7sjs(T$1+$Q9+Lpo;6M;>r8t<1Qqfus9PH=a!SB#VtX#E~8ox_2FYuJ+B2~ zW|qTGsaCO@8>rrb0et*`dg98bdfQB4SN8E-(P`x*_DbZWZmgd((T++tQlL#t5pDyn%5)wH1(S`{T@BR-ts_`T6#YjQZ69OE`` zvh}qu@1(y_1xuHz84=0(Wy;kn#$Zu5rks`s!nOrITOBI zLmFcD;o~Ig78}b*#|W2uscT-tXmIgK?BkjoJ2cs~Cdckgj+sr4>Ly2RlcT<= zY<5%GoF>N}O^&^q9P^qS!KSiElOx*Xh&MTsO^$t_PF?V~ z_7z0+vWgj8TFk{zKoq_l9afngJVMiF_zBG*W^$hk7ck*vk zZ}bQFxDNHUA~qb3SC-nJX|j*9W$IJ0?1JX`p-A)0YTM9jxHj;YnnpObvW>AVOttnm z$~VM%k7K|7XpT{GR|{&#Q&Tm36c62cmkR?wW1#&YWy=e(nyq>eClYXzuJ;HrN5^wtASOY)z6k^^!M};LTx6BkcpRU^5NW7wNi3**+H) zqA}V3-BIJIX@g+0dKOg~gzuwlaRHw#sUHndO+C9LBJ;D&vH78em|f#~WlcE}(q*+w z>Pt2I{0lP4eHVtBgT95n<^|Erd|)?%8ipMYY`Ko5l!&Dl`I51qZD_p#ATOG@GW^)S zIT%}zl{Ab2;4|T7G&WOmbh>SX8xtq~=P_2U?CBQMHtM2Bj6k46^FZh$<+wL|9UXrW zTJO&}v>DJx0UcvoTbpm|=4E}&ZP?!%if%I6{1_|YnM>Ifx3ar^CF*RZ*BNCyK!i~} zLyDptAzrR?5YFz~ydbtT)Eru}FoZYYK-IGbRb%1Pyb1lCe{QD+tYi&XD_Y4v-q zSu<-TvbIKzg>(hsZ?!#(rve;wgn3Y`r2Do z(%){uUzD4HUYjz~HZ&gLUxh{-WBa>?Xt1Wy+<#DKZyWtl9rOS?p<`@!nhQtS7V$>K z#T9GDuDJ7?vzY}8ah(OEOK1d)?7TaSwDeIvRvNmuQk=``d5zHtNV-b#Z;WlS;_N8f zg}V8Gk+c5&7J|=b49e}GJS>Q-ks5I`h?=?cbk*w_>Gv%_M^e}UYzg}pO~8U5rlv;E zIK~#-5AlHa!B*=3ZZ!JVfa>&!nYi02y6W{iCVtgZ2l3Bx>Wsb+9!F#H2sXnu;+3Vg z&bC?kfmCnmjcCSaSToL}mZB9d_;Z?(IE_3=Y!wr0&dv|%kxH#Yo$Y?Y=q%ahPKf=} zB!iPMa4cwWENpP>+u&H#;8@(?SkmCwufegj!O_s*Xl!saH8}Qfa5OhK4rp++G&q(u zI9eMVZ4Hk021iGOV|jyPMT6u2BknxFt0=m-e=`Xr0`^976O)_B)gXfu=@vR7B_c)S zZbYhdkkCYhNJm7ZD2Rxnh$!}gu8IX4h!qvF_x}3YyS{$^|C!yLy~zdTe&6$aJbGr% z%UWhPxr3f?AyVWlV`?<^9G&`g1t7w}Oi8eu~H9tXut$!1^ z{-GajyvF;4TnVot4ny5FhIueWoLP1TZfU_3q2O(EZv|);Rn2@)k4sgY6PX`GefKj$ zQC|y&^3KE%44c9!u7z*qh!kZPG{ihO5F2h_?*>k{1HCvp(m$xXG#D}g`+W?>jeu_( zja25E+N@efM|kTQ$9I>SDPRs@ye6EwSrXy+;1cG{AizUYHD-g3ox(G94Y)Cw^9aw3 zll}qI_*Xm9wt8XKcX)iehY?R2@7?HI?a1LhIE@UNGHsyT1itXEik`O5jl&DZ18~fg zy5cGCh4>F%RE8D?opE;$76#2w`H^w4YtP;TJGAQ!TQPsd*Z{U#2voe$YvABP6DN)w zHWBU>8m2jsXM<5aqcPTZ!DQA0X3q%7nfrCHwq%E{t`c9SNf2Lje21)hTha-DKtZhm zGKa|fXW_zOC}i>PXQe34h^(#~Ib~p(`Np9)B4!YNH+4#5yx1%0n+fww!24pNZQE9D zTVXK}QJFbKu}DeQ*!q#FL$GEV9mLG#7}z(9=)usyJ^X5~Q^&6Dcn=MHJ#`u9FO)4z1oq5dvA~vx!;aVumTSTCxRQsdAwm@%_{d(e77PW`urQm19<+=8^@Kr zaa2ylZKQo7V`4&8B-EsYnw(Hm5^8EfO-rcr6KZ-wU64>0Ce%dEbX3AHStmM7GTgt{W3 zu1u(v3AHMru1cuY33YWstx2eB5^8NiU7JwXCDgivx;~+9NT~G*bz?$pNT{0g$C1Z$f>OP~RrhcM0`q z3H5VA{gP0>Ce&{U^?O47kx+jo)L#kpzl8cbp(2jTaFlXXrlYbPRl`v=9hL2<97pZv zs9KJy?Wj7A+TT$JIO;%09ptEk9d(GK4t3OFjyl{?M>y(8N7Z#yuA}lC6?Ig;qY4~# zl%onARph9cqlz6>;;5q?RnJjzM;+s+V;xoMsQQjN&QT2}KdJL(iiwRKcGN40lU2S;^uR3}Guc2pNf zo$9Erjylaz-5k~3Q9T^h(@|xPI^9vd9Ce1HdONC*qxw3kpQFxnRDVaE<){IUN;t}K zRJo(hcGN&eo#UuMjvDN!A&wgAs9}y8?x=GeHNsIN9W}~Pqa8KIQDYr7&QaqXHNjEm zIclP#DjYS*QIj1t#ZgloHO*1yJ8HV4E^yR^j=IQEGaNP3QI(Fm*io|_HQP~h95vTb z^BgtbQ41Wk&{3B-YLTNZb<|=Pkngbkr(GUFE3N zj=I`WYaDfrqt-g=T1Q>ysCACI-cdI=YQ3Xwbkqh%-Q=i^j=I@Vw>WB(qi%K7ZH~I# zQFl1%PDkD4sJk6?kE8B&)P0WH?5O)4^?;*XM?L7MhaB~=qqaEe5l21hsK*@jxTCf@ z>Ip|Z>8Ph1^|Yg&anv?PZFkhOj@sd<=N$FCqh4^-i;jB9Q7=1cr=wnR)T@qq%~87? z^}3^WJL(Nbz3Hg89QC%N-f`5sj(X2g?>p)PM}6q1j~w-}qdsxer;hpzvATbX6;1G+ zqy21O4^!#eGL`nTx3VVTwc8Pqtlv{Ccf9Ww23k`+VCo$)HOQK38h+pq!;HNnbhE-; zF1T6sL|s$+`8WBYNhT)pJI&&4`~-hl_liG*Z`xzck^x-hckR;~FGrosM_}#zV=moe z&5XbrZnrq(HUE%_sVj0KrRD~~M>Op~E_gb#UnDEK$LA}-B7+~Eu%3j67s^fEe0U@m z{L6@3@vrWn-d7rXxP{h^>bGcsSPq4{`ADEwpUlvV5Gi z(XK<-NJCVPG)Br!=bAoJNiy>3kxyx!lLb@b=3Ftw1oGIhsqmGhVXC9<(0d?$y3=W3 zQ(O&Pv5F-=bm)9mj}B!MhT$hAL&4`cv*fHD>6EHCC*t(!)1x<@)^=!qLVx+F(W%23 zc!#cUutp>+8(%9`UGaJp?MEC^{8)x(dxPL{CtN{S2L$Na$trx$4;^yQx_{7G8q3p_ zD$gcr!pW2T4=Tg3{n=1_%K=wU^&_pt-YTCv)BC_U5c}lwD-wU%f2KREpfIQ?fryI&vsu-&^#Id=G0JCfOwpJ_%;-~`s)XA?f{hQ4!>+$C24LPE*y+sBeMuMlrG&#YV zY}XJJHqo1f7HmoR6L zFU9J8{s&1|9pYQPD^=kea`{bz*K(Wt$PbX=X3VS1XZ$#ef3+jM_Ewz}S!>V)Pm8*j z^~B97_%zR;a_UYUGGfp~dv9uQqa}Q2;;@fTB8?sTaXSg_blEW0xhbv+SysT|5q>Az zrYOyc^swjQBZ}a%-#?PolOtx{8b1*Cx^ssO88K|g=;8R{!_#N z?`lnjXDB}3?2`P=qvutyj_X#eO(4vEP#L)D{hk3pIM`y#w3_91Jo1>=xIgufO zmE>;?%{VhkWa)4)zSXPx#fe~S3yhg~;QlB&l@r-$tl4jT5I3Q3e7Kas-+^KoH^jSS z`LqiEaw1*q0EE9_;%%dV%|Eqo}1y5M*BCZf8`EL<}{Q&Rl6*GwE`-Avr zLlbmK#W|5d0h{0+kmAb%evQ6Ou0693{=lCAolw8S3*mema9Q1n;cpFVM`pK27b?!L zm=2yZ{eI1?UYHY!nO@1D zlP+YPyyvA(=mQ$3s&54D25(JZC|>HH{hHLpi^AUwv>P&nYc1Y^Z}ahWu=v6kcP4^m zfURm0{thb-Ubt-uk|73TEBsE}o1#=jUMxS_d~M->2kJdvJH0X%sa%P><3Y6=wW!g! zMMjer8BJScoX{epS&NL9%hk?u^-8&VwOnO&-3udoiIdT{!suEv+v25o{s&G@rTAAn zvU*QdxFc3whIj3at2|hSa}jb=)hjQ!kq6(m@-q8Ad{gFPEVwD}Mr|U*HGCCDQ8zGD z7k-jnh`O_a3njdWPx)OoFX+>)sm9^q<1Z6B*}CvLgHPex<1E9mEY3k^3ne~ci@o0QhTrue`Omia1prPis4GXe8nEh+lE)x!C|ZX z!&>gW`heiUzuc-nGkwfzC(oplzP7#;k@FoQCnvHnSTOPH|6swyUm)CKBF9W9=Bp77 zxLl+5A!si1518Rkg{G^nUp{pYL;cFBe&ydSNQ5g^!SR@1{_7sf?>49A zRMyjPyS%qd@I1F!-fs14F56>G2ao9p%8$l)l3($MUtv!1v|s+y9?FlY z67U|CQT}oF1oN-)e1~6g>z*oplrtqgx2hf4~H5N|BAiUubgjBGIA)Vi!c3}nR~3+;67YF_>Zq#ZZc26vHXbr5Hgml42CaXo@iuV=2Z_;Llxh@Jk&!4qr2Kyocm)A6{o> z4sC=STt}`ka_}FyCddH-a!ru~3FJ;d4mgl&h8&n6*Bm*3L9PXIpp%(7i1vU8Iobm! z(@q zRG1yX7)qYbVJI_e3^nB#QOUC$1DjcM?AXcDR}3(^GLaTB%;>9RG1!?khEI^LV9c49 z))@NCn!_iIlzyG(NBl%aMFqtqipdmHD5g?Oqd1>pI>iMP7gAhAF@s_zMJ2_>6tgI1 zQ_P{5OEHgPKE(oxg%p=iETXuSVll;K6iX;Br&vm{jAA*(3W_TzuB2E=v5Mj>x5hGH$nwG`J;tfRP|;s%QK6gN_Apty-*BgM@Ww@_@NxRv5IirXpfptzIbE{eM; z?xDDs;y#Ma6!%j+K;cq6NbwNG!xUR69-(-Y;xUTHDYjBPLGdKTQxs2AJVUXKVmrmN z6gw!Mqj;X;1&S9bUZQxJVkgBb6t7aeMzM?Hb&A~-Z&18R@fO9~6z@>HOYt7X`xGBg zd`R&T#m5w%P<%@98O7%mUr>BW@fF2?D88onFU2<$-%@->@jb;46hBh@MDa7lFBHF0 z{6_IR#UB)ZQv5~nKZ?I8A`V0bg`&u$$fBr0QIjH@B8Or>idq!4De6${PjLXnffNT( z987Tt#i103Q5;Tj1jUgQbt!Tw@+hJd`4j~dM^O|~6j8(|iYZDcj;5$b5vMqY;#i7O ziux4CQ8b{?6b&hkr)Wgcn4$?qQ;HKPno%^TXhG4Eq7_AJiZ&D{Qk+C_GQ}wrZ7JGO zw5RAm(UGDPMQ4gG6sJ;jr8teE8%1}D9uz$($|z2!=tXe`MQ;lHfe~(l6#Xd9r07p^ z7R3OH1cgIUPH{HHK#FrH22l*A7(y|WVi?76igPJOP>iG)MKPLU48>TAaTMbzCQzJ5 zF_EHzViLtoMHvV6%nPSy zTu*TW#d?YxDK=2tM6r?LW{O)VHc{M4aT~?$6n9YENpTm&-4ypw+)HsE#b%28DITD3 zDITPFh~i<2EfkMXJWBBx#p4uPDW0HslHw_frzxJH*haCP;#rCv6wgsSPw@i9ixe+W zyiBo^;uVTlDPE)4Me#btZi+W3-lTYo;%$m|DBh)bkK%ob4=6sQ_=w_Ticcs$rT7dY zJ2H_s+(FpX6!+u`t3G9oaFHki|`& zrOe`1&r&wP4IkNwWP#g0va&qE%|Elo;2|TbH$S!EP+qN|Kz&a@gz zjlrWQ@T^y}0=rp^84G0%lq@_gLiQTALAD9aOAoOUL3S(` zZdi}tz_AlZ1IrT06DU?ElIMA_NRd3PV6B1fQ*A+MaV^svcGFl~|i zNQu%%kgth1>dCe8s8_)Nz)DLhCX)+RT$x$J#xu;Y?#irzEFH%33&qnIiCBa&%hO^h zh8EK%4MrX-GOViy4W=ttm|IHaSETtl#7i zQLv8VA^1yM9D?;66}*}V3f6U**`kbqh6Nrz#mG=$nFqt>lHDms@U_)w^NOz!)T^E% zG+*--*6i||k;v;%U`&wgHu=ds`x~Ya-rNS|O;3@tyyYvj^|q(TS>Ev#*1QV^h9yAW zLmr)HAF;4xaRp-z>r1%H_ZmaNI+GQ03M@AzPdiw3GA}2<;#2Z0#~M`H&X$Y?Z zgMuX~xZ$<9qG4^yDrl&}8dVgj!CKWQ>=xFnrWq|@?P?U(U=2$J`zJ%eT9zl3`3Or| zXk zA>)|k9b*QvhF2x0s_84VmhCBWq8wjg&3=9}j#4csL}Lc9Hnbde!Kih-N;9DQ`gP>MlWSp4}}6RM@~Vr!=!?5EQWHpX=RinMB#gcQFA1e z9Pg#VQ0t0{zxu{ogQ4d7Dqaf=H4kbHzRVZ-DDv6n#lFz;MUyx8LMwn)Q{K%BzCv4_JVnmZ*;iQ81quwyHF_%Y z=sdmZYKp~?(@cBgNjFm=r|9nGX{U$D%L#gVd6t)XZRo`5$b*8p7JESfMeoWy!&I3I zv$v+ z@D+ckI2%fi_YOa(1EFTid!RVP=a@>_I~wXBsQXE!8R)?wogE%xb>TELq_cjQ)n$Sn z4jt!)c^UU}16788M9|ud{z$9K=!^>Kv_9JEa`rJHo%Lg(o3lwUjDu=CCEoEtrG&(U z;8+tC=LOYr>WNmR<%&R+6Hl@#YbOV)I6VcbfoS4nD)d?c!3&jXK?4&l=UZI@W_n0x z*DtWTOy(Dcbk<)K=q7k(KsOvDer7_g!FPF~X{D)>mvuqCm{oim7xJ@M<-KkT>TIZ4 zc%K%sb0jODTIMo~H)5f59v@6FANkgv%+ z4PELh{N%ORS2#;v<}2*Q5?|qR>2hD;QgbPkY+A!Fi19%QS`AE&tXb~mxe{K%JYS%M z{1wP&nHl;@DaI?1P`px#WwKsnvIKJ#vY8UUt66B)%vU2@gD)CFgEcJ1n}m?P2H9-$ z_8(|#q2+k*0)l!i)crh_^YwMMn(8_^R$kWw?fO8Q3hf4HHRXjnP}chjYi<<9Arwg%slg8co+XG+*U zAURH0E}P$Rl9f+s51R(GwZ)V&`-o}FPr;8$R%VFDBrEr~$0aMD+qRl4 z4|_tg@~Q1f$;yYerz9(v;?t6q>*pC$%81!!O6l-+WNY9q&j@~2ieFV7f%!OJr;Uz9vv5P|$l$YP^IWaH;w$XVtG+^juR+OX zGhw*P*97D1z9uAh`}xW4egZAaOm?3lTZ236<5ZuS`~>FzMqV9{Or#tQ>Q&TZ zuqotgYERi8N><6yjZl67vYGYR+XInPYsmll8pSP<$w1l)Y3+IyN7tL?H)(^C9O@H>(Ar5* zYeH?v3;Psb;T72tN>)id4ty764=gz`w9EI&C_NRWHA-+S@~0txkg?hTASxQx6YJek ze26)Hy^3%}FH~fiLwh5uj)jeW$m};^2%6z&=>4H*!)X*iI|~{xnJR}(>s8bzb9zw@ zT`@BlnapDo$cF+)X7k@QEhs5J}WP%H?(!Vp%;n^(mHb7(|F?f-g_T)#ud6I8 zs{CK1tm*#456RETte0JRGdpyEb4X^tI*|j*)a7-{G6s}ooYgymw09)FtZwJ-Wd~DB zlw~;aE9$meF#Co&k=D!WqNu!&>XT8*>>*wHMEX?zjer0CG(*cWhS2a(oMvTknqg%b z!{e*{)2!lY&Xv`)Yc>4B(LFtP!R&AA^rdin=5Cz5un76NMQ(TGFK2#sk$W2QOPRm82*|bw zqsk+2boWLJW|j2C|J~csV(Z?y>_T&#M4Y0UmQ(GGQ>}fcsKcoNaH@ZKBl$+lF^Kc9or+VWg;uO`i zoEiiR@Z~J=1sUpaYAl=@ovTOY>T?5+2BQkzhK6Ib^(Z_XBaK5c9OoK`Lc=jmdOifk zq~}!A>iI-iK!-<4hmoOMsmqhhf|esYDTWUFjr3xJh~WF@HR9YGptA9 z;keK^B*QV?I20O=i>2qYU`%>WHLads1`Fsp{;tLJoH}~G5IvuttLNtG*+I{jpep&g zo^N~Z&P5k77IIh9CFl>brCGoq;PK zo2H+b^FxsAi(f%~H zGc}_FQ0KmE8NDQo4n(OiqM8qNgm3t)625@AFgjD7&4?{f7w0icei zT_=-tMv@HZJL8+g(9a=2UC=WAQx!lzTR`C$@@xp7Z&L6%m9~CP&8I8s+@CC;ABE3p zC>1_b)8f+?7Qm+`65&G~eEtTXzjE~-0iS-R-I*rok0hDTU+~8dAeCotWM`peJR>jp zMyB%YlLqfV37|g=WCGgz`rW^?4WMfBnE)_y{3EJ`K5sHR108Z3a;c}Rp7b0WudEb!=KRKeTOW5eFoqwr|G>xxCOxN`R?okO1$6ie=`b?X z(ercA^Rx4`lcxvd>Hb0Ie?V>WaGY&B?>guuZz&v(0jBrz6t}Nu0rROzaOnOc=t)3rhdR|*Pj6tD}o}Y)FkI&O%^YrMT=ZB#xIh@AZp1Whw zMU05drK4@vtFHwk)t==}6kiU9dGUp6TD}y)0$j)y7m%S2U#7yB$$7dWa3qHEWJe}j zN5Vr;v2T7%6F-V!UHqV$mLCma0o{*F_mQCvKPutJj68i|o}M1Kay+V%qiKe9#l0{z zCe!!Lmy5-hMldhFP)*C1lVAZZG#3|;p$=c>!IwFCdRE}b$tX{DWR7(tJSMaD&5!xw z$0@Kbeo#%zj~=jq?st;zBSRg2EP)@3^Yo%Ty)ba4r)gSdlGBkS-+vdIQITgp%R=|x zUT7I#nwK1z%Pa-gJ5VmMMHYj*5c#Ul4bPylWvTDCy;0{bwfEc0g;5`r3L~m%F&YR9 zK+_+I+;6Fa(P}VSm8Y)^0G(sn4Km4KB*}nQ8Qrp0F>EP&4_B*KR}_-q894S9Nfp1wXnRAHJ< zGRb5l$%r<3z!M$=H|-eMWu zER4=asW76N7NdEv07f&B2qWrXbPpKam8b6r0L?e;u*n~rFGP|I=q}@%#L(stpi9s) zeqR+pn=PPl40$$$&mAfFETXN=srg)rI`=-y=U(Bn7^T98YFd0&!vY*$jzsuS2cJj5 zXG@-bDByFoX}88C*C0vevjzV60kk#5XDwRBAFpzaZMA${??4HlhYVx_+WURpf97*7 zt#3_D>^juBk6U7o39)r36=GD=BDM(@K+Ag&2Myb%Enij1sumD<{kq9m7 zp!F(f?ab3J1;8FL?H)DBV@Q&L?F_}&>mgu|qh)+omFw?y3(WNnl=ymSU*l^lt-qd{ z*b}I8cUfYu39%72tZ=G}>vBSCAy*dMgxP?}u=` zik9*Bs^EIx;tI!?XXD?;*K0KXerj5~Q0Km9X}v47UPr0WqM8=1dU#VDXho3-E$X0E zFWOm`M0G5x3!}Oqs-sc=X>1$~;>See-+3RIiumKOlBj(M9gCWoj2{IHk@tV@RuJ7d zYaKo!&MI-ED88Pb7Qd^L;+JosPlZi3w7a2*U#-^1S>0ozR5?(QV#>e0k`C=75%Y~} zJW6MdLt~*rH7zP_U;&02ArUInLFEKcX%f|qqPk&JH;C%`QGILx=0voKH;=~mkDAYt zae`?Q0@El2reO$70}H0U%^tf~M)H|CpwkwocAHnDV@fQYWvppDBr?> zVFY=~xUsTibYa}eduXDs5WT?Zh-tcQcRQHeSeo@^gaB384ah({a8qlc$ zsh#SN;@SKp4yXD>5&wO~r#>kDt`3R=KOFI6H0+8WRMYZfHY}j~=S%mIp$nck zJv6EZNA)>TeRkl=95jfJs&Y*ax8Arz!Q6kmGuVugJl;9S#_QQ;SoUyDC&%jooX;Iq zEnZEDjn|RFV<8#~52|VLSP2Wja2XPbSL)zV0UqZ?_4ueB8`Yx&7^_eVR-th{&yolS z>v#h~#&v8cKt~%Ap@E$wj$8%9;t18W9N7p9aAd9Y9~tU!q!NzIi0TWYdU{k(i|Q$X zFE^t>vM)2NFYbltsQ-v)ddQh+A!nvkbLL`k<`!5MXQ-y-%mc6hAMOwzkf9D|E`c)( zqIzCb&xz_;fhR6%;b>@77KA*R7xH9|^@Mklzs=P)tC}B+#E%DISNx!wmLJc+0=oaG zbRQY&@MAgrSQ^z!qIz-Q#5PnVJF(O{5e}^-DScR6&4(4@!*-YzAE>6~!|SksuD>8% zM}|6lxE4NK6V+Eo^;J>5GH_!zYLlbtn$&JwZQXFM3I)~5YK~kdj=TZG;t18W9Qhm; z(EoR(|Hx2>Be%klTcUbnRBwpt^-+C&;L8_i5WhVd|6h1HbBlGy-H5*WQ{M*Tk4$~* z?bLU@apzx6eP82z?(Nm4K2u_+zT1Syf6-WYP)&=+U$6iSKO&K-k2-kV4<7eL^*vF2 zS5)5-!1y0(!76l--DgRJuc>K#$NJ*uAxU})5W zRcK(JwZ}afE7Gj4`t5*3Pm}|Z8PDUn_I%f32#@F6c09es z@(0q@G8mAqQcbI?4lJOneWZuTP)Aq4KvzGD>QAEjqoB9tsEU7832cG&$SG;SaL zKN+_{IHmhlwQ(~gcHF)c7=zJRU{Fm9#yD62gL9F{xKRg;?*QYQsQx-2F&^bW6dJd0 zEQav7eO+zbzL%~}fC1?$)wH^L5iFpqlck5qP)ApPM^}H1>YtnI z_n(L?H?3Eg-9nVQcg)VW7k zK8FjRTTv=}sHVlog$3}r3yJWd4nD=;Q&w2XJpPhRr&u*6*NK)C`t z8|;FtV+dLM6v#fJ;U1}xeT+J{yG7PbkbQzuK}Iz#WIwieQNRo*S zgI9ipjS3Mv94+G`^OM)!qbxDkJ5VBQh`}z%28ECfOo8kO8XlDz*^#JoM_Obf1X*2_ z3Nor`A*%-qKvsZ6kWmM+NkBF+Ur)%_;{slB)ASgV9E&8G*F@v0MA+02uTr#(PpQId zs^t}qFwchInh?S@E(Naov^zC5uH#VWPO-Qq3$6wz6l00K5|U(Mv*48=8PDac4yehN)d`ryr4wMM1G}r~%j1aO5 zQy@EqhUce7))sZ{Jd13uAZv$GK}Iz#WIbU4$T}ktWYmFdDUdD6*NgM@qJUSKX?nUz zdLc>XwZyn85w;@4>kPDvFR#LDh2<5FFwchIS{%Z)CAg;Gzy(>wxRpe0@#6zB*rD6%ZS0S`RbHa3smZu7y{Agsl$|8-bSb z8}gIC>sW7zx!!>iVb>V!g6!%Lva3=c8%4wGQzILVI`;;P?0P{q2Bm_GYFfz7hXo)z z4~Zb74rHg{TMLMxFbK1@f@~c>|>aglbwqK7j=Qc^8QQp$;J50La(*`m2D+r>5O! zCixsmGLx@EQSyC=$rorD|1LlI!QJeYq zpioT<$}g}0DBmFwDAWPvS3vnWAo8ne^qWb3N0LnB=TMaV5hC&jTE>5`LgWuiBpfB4 zjie~~lgIy&8pvO$bAPu$eiI=7L#Y6vnih~D*#cw$5&=RTKn^eHtPd^F2N&oA3-ta4 z{zJW?sEyYtFb^=B@d4(c1@_6@!3AbM;cuJ{MBe+2lli_GcX4-rTZnziw(NOtuOkXL zO6THi;vLnryqg3IFf>M-LWVlLI||Va2?Yvtr zG%h7}2<*7TY+;IVVY{TiN2)JAF2Fg(N2+Q0xDpoN+7fXM8S3z{34Cl+pc@wG27!aC zPzC2hqtnPb7#^L5#uWyi+rZ|%(P=6@zY4~r=Ty_``Q5O94sVnWBSRfMKLtHMsX(_W z(5(t|ivry&=>I)vkUT&q+5Wq2&{5uqdEvCOW8taItHF?oyyT73dBHx?SMn(`bzE@49M|@ zn41y|3IX~WE#v1@0W`=03SZ%#4dF8&1)u-Y)}YjUzCoRPj^#5@_=F79xf4`N8s*!a|pu#s!T9cLMh6-HSo6-HFkVsr>BfKhEE!iYK;O$DRL1-c>t zbf{@}m`M&tk{m;mjX&~fZ+ZyO5oj4dzY3t~7Em~bJR1^26)E@}Nn6uX^QntE_k7D| zn()a*sqmqi7N1gB0G}cx!iPHe%m<&j1$uUYzPLco3@Ft%t&cNF10>0m=E5sKj4laL zYKWHcg$1}(ZNV%NscgfQ&Lx(T>m4XzG~1$aFE$gke7!o;mIoo#h=wmojjS>1+=Uj| z0zuXUrGkuVTF6d;1t4pIM37MjvK2tKtUzC0pf3w}wKYxKnWR0EWM0dROA=KpL%ceo zW&Fx2yjEIX;i&R#NK{=O!gW~+T%BomWoleqQ0HE0aa|#}PDQEUqM8=2ey{*sJ&*`4 z>cF)gxUMhI*A?is1$s?D>`c?Tze&zQl1%J+c;!dfO(9|f&@#TE04s%1gxzF`x!!>i zVb@tS?%EKtHMTs6umla?lp2|XI(LIbcB3FGN2wsAnijHAumEI(kq9#CKz0|9-BF-# zE6|$)UZYLZF(w&{B$?M8#wCfcdqcd&p=JD@D!lHsyuuOY*^mgkEre@R3S8r9_ukaF zCZNu}$KtwMaGi%z!9{gnah=W$qUT_10VLd9M{rRGuGWQ}b<0BCyilJ|sGAh}pC-8h zO*~p?!lW%HqLzjB(`55P6JJ~upMd=1Tp({La+@IU?`5&q4Wio=vM=*+5^;)ZT265b z85p`md_jgfoN5oJ+7{}Q3-yVCN6S$KZ;eMC=}}wjQFtIvHV)A%_eA4RXxoGi((@HC zCOxN`R?pYL0y-RQT|*r`?}46oE7V;Jb(ccjDd;@6tcl0N!_m!l-tCHB`kzs{nBL29 zbTYkPF#FJwLlpJB4~cq3$1a{t48^ z8;6JEY}h9&dZ@jzt$S78LGi+x6;yY+QYV=!xRX`!FxQP)*C1uV4W# zd@L>?Lmj?Mg)fr}bw%LFe^8$6$YkqCcnB)?&5vo~$Jekfeo#%zkKbSc-TzLyj|_GA zQ3*e06zU5L_4L4%-%*u(anG=>xEF@TWct4OacIkBI7(bVhB|z?0=_IS)Jp?L z;wVpcWVv-DJSI!`&5tX^k7Hn6{GghaA5CEa-9Jvcj|_GAu@-);Db%YA^{T*?6HL=) zCgB!0$?MWJW>n;7fa?nFL#q~O8NaSDdA3+*DY)K&GVQIl7~ECJSKa8PC5^2s1i9)D zty-bZy{<5LXmzbHYK>B1L^Ul&onQfIxMz=Cf7HR~W-z*`P~R8;>TKF|G0CY&k^$Xh zd|MECyeNKa2vAqFjBly}=vE6T944L(xue~fg3oERb!%!q-B9OlvV3k4KHX6&e5j_y z=WJL2pMFS$4|VW)7g3rk%Ok8Epd_&JqVZl&w`JJ5OLR>_#=hMv)iK< zk?S2OG4z1pEQ~g%U?dysJeryjH_CAzv5d9|qhTl&MpV;c zej)%=fd&Ay$DMGVGQLR+JsScv1;@p=R{`{_1r&}U&xY`MA_X7W2?Uv6r z;S+3xLp3cv-Uc_pMmW?FL$86)D~0;yLj7WZD6|O8^Y)96nxgw)<>!N za9bSrL(As_;lmAagb&rU_-uj&@L7*U_)rI*|A5bzh5GY=&p+*c^CkT81L&I&AKCrp zzg6bxZ!90zJ5U1Xa|4-x_P&1if9oRK-+Ysrm~4OZUrX$3A$GSw74OT#23}HXuSXnh_7dmNPJNTt&F11`tL&hR{-oq)6Ux|hkM~91N%D^Us-$@ z<-JK`CtAici;{10Sw;3qmUp1U*I)Y@U)+T!o>c_u)mKj3cgM{v3RX_4h>mi@93e(E zEn*+Q0t~%{M2Jxbv05OOQ{+Fr`_MG{$Rr;lNye2^#IV4Zp}3Ov58?U*E#q~n;M(8f z3dfgcBQYFeM6&aGo<)fQTxqf}^7O^en~umD>BMIyAQgVqtCby$%;Bmnla zY4?jsenpZD>@WcH=daulu;0)!UbiUu2AFGsx!!>iUxyg#|DM?Iw4R%q*dM5K>sn$* z3b8*?D#WO!MXV5Gx39Wt&DhCfN^3GOmJ9d=-aq)k4d7tO~AT ziz^&oo{fJ`t2T`nr>0d0b#BbkDiT`zqf}^7O^epCumDJfNF=_fgH~(MYFVV47wHp< zbdvyEDQe@5i^31pt?zDgFUI7dx(84msw3||RNw0_v)YJL4R8{1ifUR;wS)yY73?KN z9Zt1}Q*Dd%$wm6az@t|5sI}*jd8lqZ3XkT=#vzWTd!lhD^w_Y2^t`p-bE;|eyo>4i z$y?Ll^dM{6Ls}D!D zpThJM*Sg_UGALBja%})Cz$5M%C6PuQuJwg$y^D0OB3%~vl|U7I4n525ZT$)lN-yJ< z3`&`CD>Nwmq~{KdNzbXK)pKq;g`N+V4kJSyJwF>gcZ&3YBHcgeId_su4kyR<+#P@} zVnk#v?QgqYeJxmhgXn?c%NUp!U#O<#%T!o^3lqczWT?ZJq3~sJkv=DIWE#qo9T{vL z2@kDacoSZg?||%}jm28 zv*+v-d>*2$OH%WB77_+_Nr32C z({zVPoD`}NQL7L>h}{$5$~29#Oi}|$ zGOl|<;q*WVS535x-(LmS0~S{}oID%n%EKaiSM4(i_!CvGzb7p)*E>++Ysf9$Rv8_TZic%p)H7#PtzygTHkO(pAAoeVXZ3}Q6YZ{fBq&|{lT-!qN z^?V4|acCKTt_rT_Ev|5Uc{cuid~uVv`17f0af>(iIZJDY&Y#N>bQbY?OdOAJv>iwbw1f}!b1 zgbH;~DFBsdOy|b*kuiOEfP_0zftdLS*^NA+mPa@uat#hLagQ`O$izL|@E{cL?|Y6C zN9Mw?I6^foN7lju9JvCCI6@tc91BO{F@1DQ7sqr_;K;S8jn}U-w()Ad$fx|HLql6^ zhqmY+hqme-d^g~vZvARQYf9|UmI{&eXe>mirbXm#SO5`jI3+}=gUAUW(j=xE#dO1% zZV(W;2ervV+r;8<8^KxsGj>D6gJWy{9!*BJfx!_P*=FL$y|62OP)*B^$6*0}n2n~8 zp$ZcK2%Ol8s$?hHSSP~q*(#+EEvor&viR_X?*rAeeAsDx*d|?v57gm9 zH~7#srn|&+r#)9nIJUO|I+k68Sx@Z{6gI^%XhU%8Cpo}j=qgrg55*wS{g~x6*mNBK87LU(i0T{U7mBc1>@aP8~ePa5Im_9wGdj>GR zKrL8>rky^PM0i-wFd$^wIXyJ(^fV+w!Fi@Q@+Az5BUICJBolwm3rD!QlQ=>hjtqe# zgJODMOqa)WBBsv@e91zC_^?D#p6g=0FMKZ2oLJuF%CS&#Pq0`9ud>S0~p-O39Lc`JI0a- z59}xdLI!q3XkdpM5}|<|FOKBGusA|BEl0S46C628`i~5CIC2pjxge&`kLjr~JvpW; zV*0$m9od{|W-R`@chUCb9r6O}k$XP6>yPbJiC^5!N&KRkmS5a~2<~t*CJA4&BT;-M{JJ8hm&f$d zm|haoivzzBXo;XO5iEXPk=n22A-|S}d|498FRtd-D)Gzl{i2$dUlqnLZbl@2QO9^) z2fxjcL6Xe@(FH7yu(U;%@C5fXtx9WXWm#)g<)ACQ=fav(Be+lMi`!D0xFPWfkgifqtE=8NM3?worH-!Ng|6Na)3?R+rl7answjR>l^e?)w!`jip>f;v z|76@&;*{<^)yB<~*m1jCV5~x8fk8Db7&pKI#%&D}88_;H;R43}F@0Y^Vm-=%C^T;O zTMXfGyRX`~Jt$qh5eB5IRMYC}J+OeT-Yh*thB~_XG`jj^OmB_p$71@Cn0`3u^Sx*g z-&W-5MIb$L#32kC^#`A2uIG@t!|yCa?D%!1>&5)rQWL*r9tyc(`aRJgBC{ zgPR2b!y`y!=%|Co%i!^1Og|sfJ7Ri!0Am|!!78*Yc+rvw58(550Nov-iFCUm5xPO_ z6i2qhusA|BEl0Sm5FB|y`i~5CIPxYO*&WlnV*1sizFG)N5(gKlKy!J z(6?wA|Evn2&n=*Egm^Y&Iq^XXKHt;U=c)PpfI9ax%jZ+!^CL=y57o5z?3XQmN00~~ z>frM?`1}>qf5h}}G5t$Gsg`M7+az_6BvbkeUio39iftI}kCyR_;^faws+fTw&!b%L zKnbHi3~IsjTj)aiB?YnrXjm1e45zc*>W4j{LG-i@wB+0yL71K-eBew%Xyh_kAen1so2U=d?sPb$GuAE|d z+9wY|YQi>VV3~LPEAVLAJuo${dZ=>`u(jWf%i#l-S16N+L zu3M~+DAtDs#7;J?PccbbB+10`;FTX?g&|_?&@z5haqb&PRU=B)-HUVYIreq0q^4J@y4gn2duSG^Ffk`%c5(Qbp(xXwhKdz{5pUvTwD zsofq0Vh%k+l|N<54QesHTN%J}dyj zOeBJgI*@e+vW~^NeX(vE@Zv^YXu8lOmmo>z)zP>r5!N-tYY|$;Pc6n%Z?kk5z@Hm(p0*)QlFR&OOyK>LQFTL#Z&Lniiw0VF8XWMQ$`E zigk~G(HhhA8k4L=lFX=Ah*7@~qifMJ-nSTEafBH43o-Hz6h>tsMmfD(Y*9^h+DoO*c|YQNj^oA3~ezS^MhfEK4;N?P)d!h+Js%a7Y6&65{o0kbe>L9ol1lJVn z)x~;MvA#0E_nT?`yGi~)l8kSS@mykVT?pTwXc@n*3chs~UpVGG8$xe&h}f!7{>l{e z{^B{-rKZP?(cJ4Sy=#Tu-zXJ&RMVojhkeIx0lkgIdPBhNpY|Qw2!H&ryDh{`_8q&m zIQiM$ZI+ws9VlV9!N4cDU|%EIZ0xqwP-L^QTP>7L0wvgNjA~j?O0d-rLaG3XgcNmz z)IET5S3u-w)2N8?;DZ4MDR1})?FRUxw35(!6=XCn#7u{?frY9QPd&Arb8 zxmSR2H#CV7s%Zgf1`7bf?a>4XbpUx3K(-X?hXN+eO*?KmhUP7iBs19(iju7%Causi z{&;cnlf zVaTWVz3|`{?eBVE_;m-Kxc)7_@p;=8rq~2k9=n=-UOy4Q?)rojTdU({b1C*=0B+%eS^L z#kf@ai=5xY$3-}&_((M^AJ@PFTw5WoAwwNLW|ZJ>SBv#u#rluH!D~3Ow{iK=J07JJ)hmoO| z06sgB2p{U;QvyD*5?xrL3j#!MnWk@>i zLxq-$TVV4+482EV@zjjoN1a>GGCEoqeSlJ7L^Ul&|AhrG`V5IMq7Ft4!Kgurt{(vU z#lDACOVG__3Y+9s)kBpFQ`c;&}V z+Yp)q&@z5XN%CE#Z3vBjAnz)zJih#E+ZHAAlwbCBx5X*$E9Prf%sbsM#E0;7ZBv6h z6m{+?7UanS@-UPNNUCXpEP@4`x-Jp{NgW_h1ISZLbmtP?F`yVTO^Z!Zf+U&Zsh+2i z$MHMx5XE|E8Sh?&Vh>Bvo22B{?Asv3&K6?Fe-E*gXX}v~Vtv%P-7Um!0`WMM3Ph@D zL2LyJfY=C$K%@?c0|2pqiSAdT`;_Q20*oz7i5lJ$~{&3ch#_|xylhHEnRN+`| zIlBIVjK+SJnA^vKJi`{Jh{n(=$NxU6Jx^Mm8fOR8xsJt|5S$%RDmba8h4XY+0M1j9 z2u|w2c`k4cE73zr^q_!cFVpl4lk`TC%yO9LFJp34h-F{2jE}6sa+GBmj!EAJV{(W^ zIcQ%|p2c&HN{w;=>fDhQAcvW#PhPy^p1rJeP|rTW2A{XnVS zTbSau2&tn>qWW;mqy$Nq_bY1i(76hjg+FeETb8F++4=~wn!w>mYt%8 z4LRFQ@{ZzM%QF07H_A-!vDTbjr#mL!mgw&jrAcQDe0oBBdiMXqry8X=x=&VFMk}1= zsnTRON_=)t$$56{;XK8AVpnY0)hNZ$JkN>AP|Gq-!r*~cS;ol%>DFqHEG-id@?q5s z03clws|xHCK^dI7ETgSNDkCMGNbOpd(Sc*w6@Xqvr0y)$FO}*SO7(Moq@L#POp4UE z=uI~sBcbI*>T4|R0cWMU4Ayp)y3eJG)LlaR?LE-`r%1(l5UDttk$O5#v%A!NDHN_j z@a&e;yz_r`8XV2j^ulT0EOlQn*MOlB1kamto_F_fo_`7+;|`AId3sBT6lPStj%*LZck{)0;s#ztGc)R*rm{u<40=Hv*#~?Tp*}Z+moB>F zkiVY!@9K1KC#_poNMC<~1?el*eeLUL@~yy#BN>lG_)Pwc4*-9H4V{W{86Um+qnTxH5rzq&s6`R&y{z=!N>v5A({Q^L=G%d zCt*MO?*0sbZhq->)}K3GAA7{xCEU-QdF|HKYrrYL!GenqjWmVG$vQR?X~fO|-j#rPiq^ER(*)%%QOC|twdH#S-eCOzI9R0Q5l{4Z$IWm?_=Cz-UJ5BHS&q;cpvW$M{ z{x5zZJ`1$|-HDX`>iC5j2f~GJr6_cNflHHUEvLBUZ;lMpneI0ZEVD4f)bCfjZOdKf+eCi(CE)y{bX6tzZ_Fj10%?ZALS8tSqBkthS#FU0gi7PtDe_ zTZ-mo8RxiPJACFs`Z5F=G6b^@o**M5Xo_0?k4*IG<^ys-0G)b=p!n&+tAqN-=n48Rz!NYK;&m#VB)5 z9w8C>V|o!fx-4T9$89v?EW5n3u2HTt%e^aQOj*X*c&&1`Mmg4M^+}?^G4p2M5^J=f z{mn5iYQ|rU;@ah*5p042Q`iVO&aah~Aj^NnO}Vy<_YAM`c-?o5?^kXQ!Br?D-vn{c z5y;PTYn5XNTh%F-2%8v>58xWHZDrP>m>Bmj$83Ygb{JNK#R26eEHcsMWn9!RE8!BZ zqIC{OY7%b#uu_&WCH{kB)|pcgBJl&gqvSjiXn&)(wfo|%=$UU{LaZ!fYVxrMRXsMR z)<0R8mTckRsum9VM+?)F8Q4DVg~0_9CghODL^h)=<06L141~!M2$RFg^&x(k%uMb~ zy9E8ua1RTjCJRyXTm42G+WlHzu4|QI$~9MI^uW{a3v=>b3(-XkM-T$DgZ7)>(=$;z(urC zD%neE1xES)%sp_?Djb9{#9GG=a<{FF6CK|ld~?frOT1U zWN4ft$9TN_L_{ANN)Voeelk<@B!FWk`y_aer9mZ+EH%fipuG|?eI-j9lqWm27mws5 znV97##kCiHNj`XHSJG_5eKWhCF?;-8%&wx@MroOCyce@q(QK2n%r@PN+0`_ALRw~< z?ZxcXG~0a7W^<}cARIEombnAlLWBl5|Cl+m=N{W=eQeILd=$`~Lz}wVu272OEy^3r z;yozd(#!CsW^PEW_R{q=?0V~}U61l+$G$1Gmov-KBHm^%)~})U6RTPeU!4nPua7k{ zPopF2isC2j#n@UJJ9!_Bow65W*V0&9x!|rt)-AwHiS-CV){CTOV)N zBw$!&5d{>Ote6Ba1VUI05<&tI0)Yesvka4&0U~4}3*d4!?2DqHD1xE_itLDpf{L=q zqTs%vprWDzZnz^V?|-^`s;hds``+(<-+PaHotgBh-#MpF?bS6sa}ztwo1IQYmmW93 zG6xw&O1!3UEfoHTPDFI*nW;Ll&d~|%r6eY;ojpGh_U9+sIFJPgG-Vsi%HjrExg1Xf z+(xHITRVD}v>6|NsQO+Nh*e zEuM_xr96ph{#3R7P_KHXaF@Ckt6OM{a#T?o8?74cbY<)ib^fsPx&l7K-}ygjN7vir zX`7L!XDCmD)jVzg|0_?n;Sf4GAsqjobZ|p#Liel@y5}f#Icn&3(8rqT$zL%k5=qnVhiyUs_--}R)sY5OrN6^MD*&{&}IfLci2-WeI zLR>LARe{0Ku`V*s(tNz8=w;P~c({P(v&XD8F3-mEeX^T2fy>tex8JN+i246{1B@GG z`w1bWvkh39FVcr=i?w&WO!8sU`39+Rc;kQzvPozd$c^0p!KNO2W1iMquC=QVO-% zsv$J(&?`{%?-E_wp{EadL_&3G_L12Eo1sK#>&{)x$54o_#t$2?quMwwyDq5GyP9!o zEKY>DVpL3laq4O`MW3iH#KQ%|?K9c9Rii=68?U>1Qcf+H)m@#SD*YVEMDf_~UCi_uVnPh|75jL4yvx zCjHww*0e*HER~y$NzaxCKXwQWezm2 zzLRrc?vwO-RH^3RdxspDLC4N)vZX_sksoD;tV*?EhhEkHwp7t`RH0On5ao2v?0KAZ zse(Z2pJf+X8}k-D95re(_2!Sb#Ud1_z^FZdR35dK+1Hf*7UHR8KMpT{M@qd9{{tW6 zr>IVyH}f_2Ui+4S?EJpT9Wo5JS|!KP%o{!_Mv_nHVY`tC25$=(}##OOi1ZNgEWjl^r2xI zMkV^tC=JVV`p`HH%NhF6Bn=Z;`p`5D;~9OpG!3H}eQ1`3)i!--o`#h&eQ1$}RW5yK znTEj8wi9J3K3dJ_KlmsVW(Q-0?>S9PKzq!V!Ky3-e*br$Uj=R~iMrgK_ z;N7+;nEo&JhwCnZ0_3kg-qZn({>CQhu`&4Z&Z5q@6?MLa?~pctC~kVu&fBrlfmcWO~I$eO*Hm&MewF9l{IowA4%Lh#Q>=NU$)05;UR&vv9+K&X(Zn$tb$on6Az# zqF5`z^GQv$lsj*MD*B2IwioDkEa@Lq9*@GUzGt+{)E&@2T>g?SpN!&)FNKnwv!LN* zRL@8C5wRI5o~s&bCOBF*2-j6LGiE;4IB7-;w^}q&U%ll%6QN$1 zfQ@V%E78JE1vgr)1GuW4$f>*BQaAb-O}F}C=iDOvN%xv@YjH-jD_qrY)T=soFst)s z-h(X{*&@}2MRZlScm)y*4pIAitg&Vy86{11u+4ws)PjHG)b&B9W?48Dh22TjRo$t! zvQyVPF-c`lzR4wN$Q1tNO%UrlzLV7q@C9jhbHei}L=}u`)tmjHqUlh{GeWd|W zQ7%z$U#j<*d(u5-QbyNTH%>y`z~)hO+-kjhybU#w-#YBQ3d6f*BF1bY?r|$39t1KN zi`2dA)Q@rah>RmkxPCQhNmOrODs|0U;*ZG%mVvOiS;B8b;aMDqA2RF690WA7#E$1Zerjr#E#lRjaKbrI=%L)W)d)0af# zlh_}YvbNSLK)oMO4Rj@9otaqgKqM2f!Axv)Ai5E;sYuaHcE_JshiUdHgKQ{#pU zTHKISixP4|A0pD=Abn_@2D=nDQW38y=!=hf+^!?VVfr6bgX8X36{9w4icv%914~1t zqz|q%M49vv8Lw5^bmF9H*RKHmwnZDsL`uuHMyfk?==rSP>0}`tYz!pDk@_9dCA9zS z+^4`O?!NK?Y(}CmuDW>#M~4dJ)+;;zoK?BN8=74Fdv6$ZY-$hp|E@RLo3c>V$q?R*838*R};GlO3n?>tBu*3WX)jYAUEox}g7JEc$n zcP6M_-~;^)ch10_BSoEG<-U~RI!%0zXyLXyfcd%_)(Rw6y`n$=n;_i=1#pIzHfoUQ zZ+P_sy!xQ1^LyN@+i^Ya!y9*LcO2JYa<=mWa&RP_ccV2#Jz8MIy+J3!)^x;OV!YBp z+g)y@_c7Jg8PK4*N`D%zhOzrvcTgB>!kV})aV=@>8CF?ST2Wq|S5r~t9UoBUxs-@- zCHnr>O8qeQppbN#UDD-h(!4gBR>pGMD4z7H@k2_hYZUz0c35}>R`hk1^%Ynh3fYhf zpLY@raZ!V2BpL!yRz+2rSEQP$qU#~btEmcj%LJ-9L`__9vVdD2?O=J7z50Ad_2amD zpM!cYWHuS|*jp}gv|P?DPjs+cYOj90qxze<`Y8_TYap}9Se3oyN=M7nx#im(EZ=6Y z{uW2|3%L5Z4(ew^W|Og*c9zxpwuq}==%D^iM;*(!jt3lcEP>3%#d{sqKg!iV?4W+R zqmH#)#}f`ZRzqgv;z~#Lo4NW84(iuA>UfUpc*fq1r|ncQ_7p@m{R(sKfN(^hx^_~H zGKVQFJRH4P4Rh_pWubRt=-pN-5nBI-&S)=p>1BJnyPWLqv$nh6+3uU%?olMPDUsJ8 zvgu+ELu4C@w;;3##oM^-5Q>kvOCQ?Xec#FMacjFLob8_GcE3VGn^1fSkxeK*hsZV* zXCSl)#aUc-2*oelrE~Une{izcSJ&) zOvO6cO|-V#$=Pl=4}{3F_Ar(SkxeT_H#~}4 z&U3Il++O`KNA+H=zSu#1A!IfgyV2hAXh+MX-10aF%YJ+HC64N=xcUkQ^<|LRWNf0H zWp(N_jjOM9P+#q+V>;JyyMvC~AhU7t7Dx4Sx%ycS>Ss9WSj2TKw0Gl9I~9!0hsdUG zGuL7WEk>YwaoM3qeu%sDpuOD(oa{bqZFhyU-F4jV8YHwSk;fsjY38dSvJJ(02rWXf z0hb*@@eFrqtG(SVPIk9j+kMvA?rv^(7ZTcp;suB-LqUV_9&5XMo$Vgxb`Llyf7M#~ zYtG8w16kPYr7vf+x>*w{n$zQr`F0pb5xfeKI+&{?gysrg7Y!kXycF(q zGExckUvfGLG8?D6KxE@|Cx~*q)2uyCfY2#NS97^Vj(R|7m!tkXN7o^hU5?TqvvIo* zM7D1Cg3!tBR4xy38__Q0zTJp)cD{{++2mE7Ry&KiT<|PdJ8y!}t}JV~)02_PE?yOo*?3mQEn9mw zk;_9oLvc;#=5Kc}e;Z^rF}npK8_%Y3%hsMv;c_d_?&O}$Lpr;_%z@0tvsnV)hb5 zHlDr6En9o`JeP-f##{#=w2RrB-07o8Wf!y8AhYr8Ft=>&*+DK3@eDCL#?8O)VE$dm zY-08{M3$b>jPD}|?J|CnTmHns@^O3h@cs`IO z-8iq}a*KGxKxh$Z=L{6c+jms@u zo&%wU%X4wr!R33o%l9Cmjb977UF%TZ$>kP)-3OtCUrTV=!LL=^uSb#4CX_26vT^w# zh@3*XjLR)tUJapz%a7x-gUg$_%Nvm}#4l}0xt`lKg%V53wOl6nq%A3#YYT)HK0SrY z4nFPXKJ7w6n=rlrQHZ@G zr(cE0*6BkKIyrrS%PpLK6G988-@;`Fr$6RSe~5%Oh44N^mieJ6=5cGgC!Fnm$?cwW zQhv%>`B%=$f8@%)LqeNOoprK%&f4xz&UVjpyT3Up|I=Fe1!v`#w+qe;Teg#mRN9|w z4w+4cFNMgm6mggfBCX;H6^mM#x?$9TTfWM{a$76)TF27bNkM+fz>klAD` z+RC!lM?_j#<{9h8Ehjlx?qaXLlcV~6Tz#5@`aY1^WUQCHF^&ETc%rz21i!O2$ zE(&DM5rake{;+ntSsHldgakxeM3L*z8D-ofP|b&|Q}Lue7I1-R@Gs{6Ui z_adQ$Y+?ms|Mt0E8BPEyZOAznx!l6#H4s|3 z{3I?rxcoGCc?%NS__c}KwGQP5F1PS&8-x~qJ%h^*e)Z`P9Fco=kP=G0Xb;G2!rUFA zknE(ZU0gCmHutTuah1U>_j9n^*Ixa#j_QYU^@APMXG3O_v4QrMGaW6D;+FFqEDyI= zKg?0Rm#Z&!P+tg{O~!7tw>;X>aw)ew&cU+ZUVVw9`YNuz!a;o*WHuR_XlGeFcf-}! zI;gL9)G?jwxZOd=ZIIcxc#EU@xm^7$2lX=?bu8jK7CPv-6EYhY=R2x@fUCdHLH%M! z9glJy58J!3+)f2!4?<+quQ1nR5L$GDD{WR2*n}p(ku3M_c_@;Y;E^dXS?rnyYC>OO(@=i$R-qT zKx7+=4xBrBCeb9(S_)xwYLdob7(c?VdqGn^1fMk!2`oL*sjEyFWPF z{f*oG*-82D*2@2IR_<~KXBrog&?ZxVJJ}6$TNYwCE;|%rBW^bW32h_R*jjlLXXRIL z<(DC$O{Q8n*==oYw~e!1H@Dl)NqMBT@+fEJeYo zC*+pvjk&MxZ-z*`f2A$6cCjZ+E7X-TBsb7dYE}fZM$f32jPbF+?`a{2qvGL$MS> zi%>j>%MPJf$z6KH-tNOrc2`;3UF~dl6Sun_32j2L79z_~&|tjT+U^!-yU%jF+nkg? zXRUmPv+})M`O8RXlPP?U+CEeJtnKc1w)+~ld&o)o5o_f~ot3wY49+l`MM_mk8n>E4 zW|QH@5LuQYV+|p4+A@mZa$##`5Vk?60$c{6xxxpJEVt)QUx`#g{g<3>1DTCyS8&VL zn?|j;Jj64MxbfV4oP+rod-G9Ty|sBamxq{Vt^^3}0+Yf$OGYZYz$8ItQ<_~MvWZzI zh(flNwbDXN`f|&C94z;;SD)&reh62e?Vx@jWHuSgw6~nWEnAmHI+t6NMh=8_rEvpy zIv=U*N@E0MHX+aDmaRP-%H<)Rp-BAPyw}0J2Qr(O6+vXp@=88VxgO@+wDvs#F3j{sCd=+swE z=JF7?nd=S+?E-oy&(S=jvJ2=O$ZXu61(B`WGaz(wyN=64+(xt?JUhRmiWEQiR_Z5rKHL1$v4L4wfIcSC7a( z&2?;X(6I?J8}B#Rt7ool5ZZbFJh%LugXQh^>f!xCu4BK0j=hlCc)#0DJ!3CH16k7YrEe#+f|~1bK1X=&?XcYAhIcl^AI^z zk>9yIq#*F%gDA^Txp3JbR86?c4Uy2suLy{o{Ho987JfB_(4q)0#bpP-+Ht?yBB4zv zTSH{y^5qaYxqKOyTe#dFLJOBW;If0u3Ebt5NND3%EVpaj)}p!G!mmUKE&S?)%MO0^ z=6(3+~omCXyaFZZr3`L{kYu1uR#!6 z_?3;z4u0ixzlI~BjbFpKU2DH`xZJ|8kq}z=H42v<{F==DDn~+_BAx`1jmtMd*}>@z-08JQXj2GlAhOI4&2u+e+uh`B_Zey= z?jCEqd!6kb=5`M_DSy>k`D@O~PjTg+%L%0&vCkm0$?zu-S(YMW$05=xo=~yqw32$C z<9lxTtb^s#_UgZORDYhU|II=DFOb<}>?eE6KRQ}=MF(e*7ac7BZLj`8bfH&+?(LCLvz2JyVTO&ZgVHQS6JI^?QA!O+l@p*n{w;`kxeMt zL1Y_>SO_gb5r@kTp}2;-)XCm%f|K1OYr9>Y?e^t%`yioBD0)F;6N*%boCb*$E)QwT z%yk`v7NP2g%MPI$%v~OYgf@O1@&?c0lAhK~e zA0nqvj^J_&mkS}ZaJdMV9bBHkT@E0jjbA=)*E*D5F1PTj6haHXZo*{;zg~{-poFn7 z*Ma!g|QtF4G2`%l$LwxIm4FtvvL|i$4qs2Y7*82Ztq5_%xRTXo+;i*!Xr7G zghL$8!uQ#T>yhvkJ0W&l-qWM--@1k%- zP9x|Lqwqdb*+hYbedr|o$WDkD3`__Pk^>T~=C1e#VSfm;%nP3JF9B6^1(irQATX)4 zth6RjB_!3p&{IxYYN|@h#|t9udwXyrt5eX8j7~Ogq(cy*AT2nHIg7Ku^lWR!zA03y z0^_NkgsG2ity|ebpXvO9Gzx0}ABBynwuhZBY^1h^KMV1oY8F=Sf_A;$U%2jKVc~xl zs;#BoKl(c>qQA+;xk9C~Dlo2envfTAg|QzB6~DK}tIVONJJFM4YZ?2lP$^L#{3N8N zr()Cm`Zsu6Tke?@C?8)lfhg^Hv$f3iYoRi(vX7BBu@sFaFL01co?y(aY$!H6OX zK$xpBcd}lQQc)?Gtii8GAO#)@E?m5~x#ma1BJQ{Dfy>pPDCqZ$`tYl+j(!?Iedg_O zJeHg_34_@yU=|+{lglj4wXiY=E=uLXT+u}>)SfA(sJRk`GKtmx4vW+O?pV}PEsLx5 z_jvt1L4Qvyx=iIdX@7@x(chEw_hkLOyZ+uofA6ioU#q|O)!+N+@9An7!@~RP?-}}g zrv9F#y@zG%=?ClYIr{rh{e768E?4J9=zr(y?<4i=H|T%gsJ|EJ@5QN`J4`Q*^siwYa;c zsn@CeJ6M)~yCS8uTzVe-47D0wS)^3@q*l_#s-{p6Z~h-@PaSFxTBvJ@UVHA>Ys&+A z?OCe-{h0+I!e${qHUM`&RvZoBqCCdv`sn=?~wjzEc!$FH&;RNumeME+1DRG}JJ37>wN( z8YISUDN=H>g`}PJHa!b%I#A;+okTL)+sD)Ry^t~2bSf21y?*_|WpsTGt_$4@bImML z0@Kvz^6TlEp!8@=URb1zud1l6toHcSr`ZWl$_|@bL_Kh|2hZ*ITZk9v;;B^_C_>~k zRqll%WrDZdPrpf^J&aFL zqMNwXe(f;t*A5~kehGU;t<&W~#Jf{e**>TXUR0F29%?bbm)D_78#j)G=z7)C1wh9* z^g#&po;B21X{Zi5iqfdORjbs}>wDkOEj?q&(Rc0|=PpRcuRxb)Ybqpi8B{ zL}{&DrLfM;{qn5<}5Op!;$EaDc=c4|I{weBM%+FEJ#rzVrG3NKEyQAks z?}}L*{YlK~=shuOqwkB^96cxIO!W4cZ=(;zoQwW0W>(C?n8#wy$E=HaDt2qk$1#Uv zcE`RIb64#9F`vbL8nZt3WXwCUXJa0W{Wa!5>|ZfEW2eVH8aqGsf!GDHFT^g6eJyrH z?B3W_vHN3J$G#W)c(ev4>+nh&>*ACiX<^=dqu}eiQq6#|<67jsG!T z{ZX2*<}KZk(dm^nwKE$()_8T}9~+-*{A=Sn_jLD61Yov%u6v$)J_51Gy%-_6-~E95 zLH9%M74ApfkGWU6SGiZapKz~nuXS&5Z**^VZ*@Q8-tKyQioQE~QS{>Id!v^`-yi*8^s?yX(GN$jh<+@3RrKoUC!(K> zUK_nBdUN#F=p)f5qrZqg75#Pe>F6`j-$s8QeJ=Ws=vgsyP=t$P?u%I(vn=MJm=!UP zqCi*2tVNM-jCm?%Ys|Ko?J>{A?26eFa|p$IBnB*jcf2V&|dQ7sTEbdw1+26#NoYfd^xk z$3Bb-@M!ExRDsnf{xz{{W7o%SjNKgj6sp2AvCpD9>_kP`g(|Td6=i?yf!IT+8n4A3 zjeR5bt=M-^X+DTO7W*-($_Z4H&rn&uLa`| zcf!Sly2KfYGZSYe&Q6?@I5%-#;{3z~iFYL~OuResp2S6oixcllT#|Ty;sc3G6Wb_l zmCNh4qBp;^pRb~Q|;zOzKkRS6t{Ev@2cw zRRLeklmN~3sLQ~S8u}>x>*6b&6fhE7Fo`sudo9zTtD=9G;J+|-DVdc1 z(S?TBbWKW0b{qe?rY7}D?wQmzNxTSg*QBH#J$ks^$vsk2d!$nOu?;DRO!3bdcjw7K z&wsWxe&X1MoQ)5?|7=uT-rf&dg)1!^U!ss~^xi z7XnFdIIJkAvShtT2Yvs)U{V(Mnzd!ZFya05b?KJWwOhBslG5_RK^4_CqkHyHhc{nx7yqP5QEoIKrE|^Al>tAd zPo2ln$oaIv^R-B!)D*l(ld(d}Jbq%&` z9b;7uf`bZ%X>0ko((zp;D9zYMZ!Eg?qulE+H1hx2J0|g?uUeG-cZ#Q~npKrA=ce|_ zC~Ek(E9FGrdiz&RZ87P8rqa-~XXSQ^y9}jJ>{n*Oki}jU4&@kdAxLAM$o? zTG?LlcqY*=o#{2Dl9qGhJQdontzmsoFT#!0K`U$*-ANznPa-7IaG)(fX}tzmE>eHe;CW7HLg7WGrYU6t)w zvkt6je~GE~$kg3Loxng}cMVX3yb|O{iL5k{_(qIUHwk@vT?BB0j02f~?=`?rEqAiP zMTD(xjhCA+r0Q60dlu+1lrdp{S%Zy}A#{;sYx`KLusI6V_ayQoSmk|}t zia^bmOo`beWBA^ZQdhq#UcS0qbn;_lZ>2jH2Yfjhe61-}}ofnmYII3R)h26Ct4&D-vd+XdJo6TK9E;QW_B6SvC8eFF+v06nzFF|&ibtL~n+#3Z$PZE|r z8!xMY>5Y~Qbrcyf7?i2CM7=i$FSqp*Ti!u{*NLE5W(2MyaPvI8Je4kjUjQ7Vg25-{pxOQI0mCgR#I!b@D1qBNzFaIu9QS<_Wg2F1>rLWA!!Ds`_Ab`vn8HzP-P zUrhyQuFfT(wh%R74PG8blQpX4b62yb?+TO{PU4;-?)Z~963W&|q!_v#$V~`Pj#ovvU#1 zHbUMcWIB+RnrqvD91;*AJH$LgOvM4bylgPffjKHLLUxGRPE6B-c=_94UI6p9zzEri z!1U%>Vm1-e$HRSl8O(H)t9N3+gE={s4({?&?RyHX=Q%=#9Ky@ZKrW@a$CReCg!Ggb z0oXynZv;Ff0H+F+@qrr8)Y6&>FyaqP^LYK(Qmd}^l+oIL#wA#|0;vxtcanm~uuW38 z3kvEA7=^H&>rg@1(E?Y~dWEW@fL8^ve&FooV4o+p-rIQT>BY+kl?|`AuYesY2nYUl z0XqdHd4)ueg}{6&=Bii7iVIoO zsRC(G-9WuWRNhIv3=Swt3!=iOmmdI*Qo%5QdgPA= z*|IWjkNkXvu(TiWGP6_)#z#RwutU)}KtP+H@G|%&MTyrO)Qx;$FdicuL>(lm$Ip1# z3TlW%eJ@agG0M~-!Y=(4FPRhZ8|p#KMbSSW#41ZYm8CpWgdHaA;%|64223ci2s-AV z)_0Uxb!EU;inTi(AqlqC9-v<(`t%=oDVwAygUDz-HU6!FbX8yycFm>)JSA1$a^D0_ zw+HK#Z~88#rjHAcTd+K!O6 z#ed;tAGGxfYE#`w3~DR!`M3*|{i6i6{0A?i%N3=A7PUMF?&0PF zmIhn7obvd^Rz*I(MO=$8aN(7TGEvQ0*dboYi-IWH)wt4t+OJh}cS*t9q~LDaF+2nX zb@wT%itvrpmj;{4i45y z?_Gk%Hw2VZg*Ash($vWWMyDArWC}^2#~}C~F^@L_vrb@e7hbEnWffBbWvH}LzTPM1 zWMeS(suiU`%N5VkRD^Yz%;VTru+CFlJ|NzGDfpG()mj@S1orVDjGj*7J|ymJGjJ(2 ziqc25>%tg84Rj-iCQS;A$9cY>!Ok#vjKFCv0B!|%DS^Gy(%R9Zff zBUBon5HhnJknK|yB}a{_iku4~zRKF_2_9c*`4kRPR6iwfatD9|r{U9sT4uuv#)RFc z-G~3!g4bhnx2mDE=Njv6qi2jZlBwN?ii% zeMwliL|{JwQ)?Y#Povhw7jsOktU7jzuy+Z&;#Q7r1lE~jU2)e?D+-)wzo+Zvn3GIQQ6b)hkMuxa+qW0OrByJNvR8T1?ZQ-;bzd} z=??^6ByheAjub&Jt!l*#{z%xeWMG>O>3pNX8^9b~(IaT5IlkpY=BdHM^HX(=H48zg#PB1=VbvdP(B z3H+77@c{M8wi{HLOqo3Wjj(%q0J}@ZCd-(~&EE-&PX)GB#%e`u8XBO<%|8g-N8tMa zg(i4&2x#&YJC91;xSk*{$mG95NRzXF64{^^NcZiMO{~%NJ`n5CX&!ZRLac2U2;4|u zrU6pJpB)04oc)W)VZA}#B$M+)NRzXF6ZsR7_sAr+jf2jXTXZ)65O;qcaL<4fI-A92 z&gAMv01?JG=Su?@eFyiHI-3<{&gAI~0{dk+vOxECryHB5-y0uYzF41GsL9;sSUGNSo0;B2n5V~51=Mj8mf534D z45ta+X~5N0o@!H@o=@ZnA_s%itKN1L=q?jx3ey7Ore=Vvl({`7&J?6OiEBOp-2F25 zio}__p1TO!K-lvJwgPS*Hen_=vE_~qAQRlDGI!L(ncTdaxKD`-pU%TV_TG}X;7Z=D zmEk=^-JAs~-k?4L^`1cCKDwz477^BRAh4kZMrCl!gqbq8n7B>ERmah7ToJfP zk((sP@-dYg0j}XJGZ!y#_~L+^zm+PONBIi@yUJj#OWflsHws*r+4{x@b0MM>nZW{wt#yfeg1DKZ!L0=+M>J31YVd^^ z(a$w1HwN4}aC&tiV>f6J7OvP-G_}De32JvEpv&jrPC0Lbw4qlZai%u7mcY*m>;tg1 z3hHf;SdZZ-Y?|8OI%2UgrqqoE8>z8c8zgqTVV7<@$n|DDv9A__T?bZZ6cc4iE{hFB z`HMik4oaSxR0yEC_uWX`RmI?b1}BH7TH;LM*+k$;0$b0u2+vfFr51(hfhjzjiQV7< zn+Dbh4|bI(Ja-s&Q3Xul*+T5$v0&$b6~Z%9rsVKEMU>AAY6B=aJaf6LIE^+*-=lMD zUE5aTt}FrfCOE@WeaUx^fSQNjrwQ%l1KMVuSj%&f!=(~uitIKO^aCsj0Uwn>Q&^u- z!2o441bk8ilg(@B?J7AALvbZeFGMZ!Ls2#ijQ7}z;D z{jr8ogfXnjTQ|FidutN7H^J!vrn$HS)kzDu)QZzXtFYz`F1H!nUQ^ zG<-MVhY8QA1^%vNTi0-C=GUDcROFTw~S%?@bzxk_OMslz%G?siOCEP)3{&y-w`EZlRpt&D-92 z)X_dNWeV6Egk5nfu>LZ3os5}0eUq@QgpHT6fn&9^BECvmjZ{We?U>XtEy-@sUKVTS-`8k_&%IiL5~sJW)0Zet=PXrHh7m?H~SHx zk30$V6QCKY+3=wI>P@wJUf!=&(hYgkJ^3!u$E2cS9aQvPswhd^bJQNXDc3ZVH`T!7 zq~O$gC|C&v>ah@YC4Hzsy~EZvRDr4Pogf9to1kFGgFyv)CQ$vzi8xIMjsA33Qi|Ru zMBlLm^zWeM;lGQ$s=K(5;o;2VEvYvCgyZRAXy+yG5?Inep^8XKuWs~gFyB$ z$kHkD^!g-`>}ik-Knhd3-XbHfRzD}^A!4@3Oka(`faNcpqTl&;YnAZ}Vp6t&c^8a+ z1cAx*BA1&CRG4Q*UlRY_v*15k&i$kfhkOY#)q_(+&3z8kMVT5cQKrKGim1pPpkf}9 zY!!->c`*N)s27OJ1|?4g#>$|{%WsIR-U+hYAoW4eFOw!uPZOE=JjnYDQXj%5$fU&% z^BJPQAbJOAd53vY2yNP7K1=WuF91Gaz;K#&m@5r<+IWv&A5z>}P573;@h<{&JTXciXgwr4_B`#x;Zg%M72D4QrtJs#sulP!2k{UDDU`nuIQANl|Gb*b!{EMkMf{W zTX@lgncTcUT*0g0I?LQ{6K8VsFXGMSo-&m_)N2D6AdP1G$0MP=|Mr_>p&yv~?S)Z8~g zJ!(+jgZf6MOj(;lSnONC_RH9}GG@xzT*CGdc3Q@Ml(3K$`#j>jZ-Z;Pl9vE=Ex(vJ zlfC)GT_moX%>5y89*d!G0ii420XiCJy4rsR=k*sg8h0YJH9=L#t=T(?9`+vSy`Z(h zNSIkSED7GI2`Vsk!gmp0{sH*hRc7nWWf;Dj;DrRcj{$x@1a2+El@ z1UhCl9+zW`qa9=vcFpKLgg$T_=-o0Jr=fbl^i#QRZJ=62(2bt}`U6niA$2*V&&Ad8 zd!S^u%v0$%4Mu(YDI%+2$PP&g!?kYX$q6o`w3m~70@3Il=4~-ikhrGKxm(@fwo#Bg~=nK zbo|k5bt$382<;72-$YihtLFSSrg^$2mU?U{#^jK*6bc7HsS}cE!Qea ze{FuKEyCYJZF%r z$BDe=cd`vqSQzgY8F^v+1Tja6*&#EBGzK$W*pU~;YlxZn2bdFJ>K17oq`WXb#!Z&v zAgokLo+SM8zkq+dfxAibf)fT47;oBsTuab11SuOO=%fUhn!q}uM*IybR;Er#l&SWw zC+bI{u9vCPB4ys#-aypd|A4BHsqbXU|M8?j^n90XYguP1GP8s{vz=B^- zb88K3Ga(c3<1$%=1%$qVCoV^~5Y(6f3fm;b{ci~}W$G!S))RHLOfg?@ zo>5*=V_rUOC2EihRE|v5;}kYoLXJ5LXI77Cu}!iCk>3YgIbv|lbg>HS6mNV{mr}th-+iwOm03$++V~c z%3M2vGw%rPAZU4gK)HbA9id2xGkLj_z)_a~tTjM=Lnu}PO>RCia?Q z5@<0eeu3cE34R%{ydBip44WpUFA}??0oX4MR^JWks z+!bg7Xg46C&1V}B+LU?Lv4^nF2s>riqIGbN2{YA#y~N$#6kNlnxR1mQH*uy)u#dQ_ zE(Ldu%#D;d^E!AxVb2qmZ(y_+F~)?M+Q)S57pn@5OSPuy)Xce9Bzxp|bhL9M{8l(~ONoT&_6C+aJr z4j2@b!E}L|7TOTrAa2&>;LaKx6~b&YXUg821V&u}u-Vg6Da<#6ru@A{;BEp_WN@Jj zn#mxG?-2MGfp-`n72y45(Bvtem4QyX4Zz1`aG4C6isC)OdbS02 z*ubbLR)|<=dw8F?_lf)7;HW58nmJPjKOnH?N`Ni5Nk#F588l_^Ljqe|1+b?Ku9HD? zQ5+-gDdLI@jv~6r%$Yp>h`^!k0M3xXt!B{V>Bj_qOW>0-xLpQKMRA<41?_2|Y|$2e7O@$J6PiJTt`vKvU@t3@Yd%rqhRg0Q4GV55QQQ!dOyXf|-tAWgSVza;8g zqW%R+zf-=2-zopf0BcOkfKx;!Uk!4nWRJ@3jDgjbgwC|TBJ_JgKLIK%Fuyl*ri%SF zfp^6N40~1re=>univ10N2?+qNmcid7Fl4fQnz%#6&uwQ+INKY>kRCqj5QQ7^X&e6 zqCO$2{&T#l>8DGZ%AhGMKM=XR3&=!+)Tj4&=!pKsFk~>~)Y6Ycj=Bb9u0iVa`^!br z{Ds1E1hz;5SPM|EZ1jb~wlZb%^e4ieB5b*gwU;qdKz}A|Xjfn_%UG0%S$v`J7XrT} z@JoO~tB(r-O`iTro?>~BQ&?gp}pOm>mUkS`SePT)xb^9+zWn&c4B zg4Y3OGDBBn(un8rJUUzt(Iuq=(iXk>ZV=WpWPAg(Jo?VvV& z7oi(G9BM{Qf&7Qq^F6`d0@k=kjK)OxC^K$~=0(Dr_6ELB!qK7#FP1W^KXbsX1+^|7 zXmlUS?eo%Fu*86H0$$$#nNH9_g1Q0{R-NMvM*&%!6rDk2;98KQKpLk6s7!EVkGc$s zuL_5p5}iqKX&T^1L*OYAZ0_S`5n0w3$AUM|rgXJO|PdSwP>_eHbY zt27jQ%v3z48n}SK4g&z*0#K+CYb1jqUsJi0xLw3O8e(v>gsO2eS-p$sJ(-l#5c*jY z9eVI}Af`S$P}B!) z(6f4i&rD0W4A0pmY|Ic~PXeo(6MV$qq5_4U_3p*ws=Q(xdP4l*i~8Ig6?Wr9Kr1|H zm*D$G0RC*ZqD<2tS2m|We|kwpr4LV7^VE3pbaicCnJhHJb9RaAFcRE#d+_N6^&W!K zAgc|#v%s}TJ$Spmpx&2W_KlZ)>t!GL!|?#2+nw%-=UxJ($SGXA0V`>0O%f| zQTn;zqJV<$=BotuAFHNnoVr7fl?=!1mL^8nosRC|UPD+<(WI+vpqa1YKnk2k_s0CE|T|CE4yWIrBVO8LZtg9EJT z5>5s!l4-TrM9a&G@9PKO@0H-=fY{tXSko1pub|tm7EV7z=#Bu;$ARXO>9DY(K-i=J zTLK5x2K1r_tpD7Q@S{Tdm<#CB$FB_0ri zU%M&y2Jd!(DFM8K;74u(d@taCQF(>q(V;piJW-QB?=b-C5u!GggUUFFPYblO&h_UM zFg$1owFJ*S#23TR+?w_+Q0M{sc$QsFHhwKjuXcCIlAq(N_Tc9fp!R!M!oNmJ-;iq&%B?-PlB~S!p@Rf9`(fh>!$$sy^jtwY z7T*1k!r_eEk$HneCwju*?A9I+JzigZbb7#3S)rChHGH}h8Bu+z`}avk<|8XLW!2r1 zlYBk8PXql&Fh_&zL=noPV#Y@H7d-z4`RcEEPI1l2L$>Jm1l8C@K{(n7dUCQ5^w!AI zvJ^N|Mh{-avKSkX;M9C9w7edn{A7e^K>vKfi#|}+do+~kKj(#=jbN@~tuNo)-cwqE zA033*mRk5Cl+TS^=4Pe~>Jw2sMM6GOg?zMw>G#GAM7rtcbNYS&6@2%pnb9JSsntnYLw**n|@GnC7&agKqTMXPaFnF|6ElR&zGFhxulkYM@ zlRjX;Xu({4C>zl^BhQmFY(S<*tz${ul5lb&SpAzJ!S#l0GC%u2(upuM!Gd%;+^V2zVKtuP}j1F}bnQ5m9y<8Gi? zm-f73uE+yLhg3!H8wJ}xj{?YhrVgkG^UU=KPCOlKMzfuSXUC||JS{5^l!2+QF)n3& zLCko18fvhM)n^Oy>MO4BIxLJa55igiW!Nl2xz-4HUKVONZ}(Rr0Ar0_7&uY)wxh(vaNKC;V05esRNz)}m! zLDk}=xCRM&8F;Q3$2O3q7!9cZi1eWugD`##Nzcz7h5YiibO{oEX5_d3;9Rky#6xmwZDiO*l@N!ad`O3zI*4SH z1MlP_kU%kFkT*oEbJ+;MaHGC6w6^T*_7dQg=yB?(qu7o0h56jw%0ZnmHxS;1oxm7ENk=y)*c8m3O$F=3}J2FGCF z!R#oilNkkSZ;si5M>W!;XJ!VL@i-0?>|?{={OdG04fU3(mAP(t(EqbWeg|cP;SIDi zH2-WkH=uu(;M=tjzH12kXABxBNZUbL&xi{;KIEDQW+hIfdkuu0jruZjXzpM^It67s*2rj9_E51s ztpoeEp%~3pK(B)f5YCH2T#IP=1{lXua4n2 zWDu$F=Fg@yYm>^_rm`zj*;T2mT`KF4$|6%)R4R*3WihENHkHMtvW}_j>Qsg&wk4#( zU{4_<=-R|t>vTBV+HjUS>rp~pyyz%j>WsF5-|q2LPb{ScmKV`)sWsZ5iRo9hR4m-Upo^ADF}8L$;PwonhvT%tJx(4wgE%kBuA*%@iwS46@hI z5Ter%yw5{@yz&}&@2#RCFgob;r54w6wV@QtD5NCY_}573U~x4Pf zXbbokp>&i>QW`NU5vflEud?L1Mn@?8ntDNPVgRjMwT`5b@|D%)@Fw_a5c70N{YeHs z#i6;A6#=-|oMaod`-E|3A1;!V%&c&>2 zF-s|Cy^2{{F-tFInZ+!-nB^3+;l*rZF&k6Nii(-Hm<5ViX)!A+W|NCqZ85vKnEk7m zO)qA%i`o2Qwy>BjE@t-^vt`9>MKN1h%$_J_>x$W?Vz#xIZ7*g!i`lMXwx^iAQp^q) zv!liAtz!0GF*{bwP873~#q3luJ6+7aD`w}4*{{Xyd@*AlR?ov4cvuq;YwlrfJS@_~ z;ytXZhxPKXbPpTsVR;^QgNGG(n8(A$d)Pz|tMIUD51Z;?cX-%L51Z>@_juS+4|~+Z zp7bz0NM(zMZS$}fJZztbz2;%>c-Y4t_Nj+`;bC8U*jW$z!NY#`u-`rGf`?u7uuI0W zOUJU7W7(BsS@c-eaV)!LEK42B`iy1Qjb($!vXNt%Z!CLYEITun{XCZaHI~)$;t7|m zt(V1lSr;!$_Oc#c*4xYadReZQ<$Kv^FDvx2v0mo)vI$-`$;&Fetj5c3^|BdWHpj~r zc-g&Pw$#fW_Oi#k>~SyK=w(lN*)v|Y!^>XuvfW;`-^&hp*%2>$)63rVvJbuNxR-tA zWqjA^M=$%u%l`1Pi(b~Sgf%Z=txH&k5*Am&29~hFC2Uv;%PV0wl(2#l<|$#m5;nes zO)Oy*C2VR5yQ757En#<;um?-nsuH%bggslrc9*dICG1cMJ66I@l(3T}>{JOmUBbRA zVdqNNuO;k!3H!T*F(0evV-0+)iH|k+u~t6T#>d+ESfr1|`dGY=b@s8YK88oWr2AN= zk7fHa|$%g-x`WDup|_BR8k<$(!?~XVAhUFIUiKwARS}mCt1u6 zP0C~Co>bZ}Dn~317-LRW{td(ARr947HO~&gc9I9bbcyceV8!11qr&5%_oETTBSL_S9I7N8;HTlSkKWYKg5VQ9t&;E zNNLG2Qjj6*e74#OvUla6iJ5PQSjW%+RaQ~mBLz?4$MJ4HdRtzPP<)2EtRce&V(*2= zawDw0Y6QB!v}|k%VN;`G_xCBSZ1f{u$z$AsW&VLJoTfIc$N@KcP)D##Pn^ z_lamBtd`1ScB1g#@k4;7A(;QtUL_xfJD?K1KbR7dT>C{To;C|<-$mL8+@h$rP-j<|}*LXdmtJG$CtWJ)l=iB^{*l#_;|x#=0= z;vfNz&gBi2Ru#OVQis;|22{tu6q<6T25np(at-^3h5@Vt#JY4nvU1pvUN1HG7O*}@ z%O`bg1LThFYB+Ff7fg6PQ}83!6;(804>t5GG;bo5JkvtDI~pTjNV{RY+Ay9qA~Q#* z<}X735LLggvYLL+C#bxQraZhs8--TVGvSP4O&3tr3MC#0h!`TqaK_uq2WgTAtEi$Y8&epdJ%Qp zXzH{s8YKEl<6%H>3f;)iTyfWDGo0FC)W&qVJHSl|EM7xeqyA%%yg5?S{ZNfu1H)G4 zXmJ5F0(O2g>6eByV~|*lX&<1%(3>T%tad=!PeZAiWu#}Ip7Zh3jYzi2 zp&`yY1;=!#uAdGL1w)N;?25jX_vB5X@ngf8{#jV9iQ5M;khha#E@fsMy80=t)w)I7 zcKAPlHwA?Q#l;_u;x8FOY$^z~n6}gEggvY*3@LmMi)IdA7-U9z9&*9^`A*1rs@eeX zgTS5=Z&g((e)Iu%SA&h~q7l+Osm=^SohdeiSpzfkGe?VK*^@B*D(_cD;8zfgjwJ`O z5t>t|M~QNwO6k54AXwvHxC_-cYL7VbzQH!PW}mC?Z^7`UjXjcuUEfb*vV1w z%XjWb1!qP#)20VKoyl&~Q`jFV?0gFQGlgA9VSlBtzf;&h zDePhjQ+hDg1CbuA1&iu#-UvjQSKUMeYn2hKENpKI#d}r>FH2CS`mljHk@sMW&<;Ox zQY+ZL)W)%LaJ?;h-* z9_(Tdrlc~K%ED4vy;N2|m0g0}uvFF{l{HLdjZ#_TRMsSwHKi@G4~)#vbO*P zyt&~KHuTa3>5Y*7VPtlIyxo(I%>E@xrIkb`q+Y`^?J|zIQP8~}^8E(gU+PYpK=_FP z4;>~}#*Xmngg`>IxE~&;grBh(fA~*B8#laSQT30jRezMxtYGQglDx;CRby}n{Vn5MZ;W$ z0}R+@8$(OH?EJhMZ%r-T-A@l{`_e{&+o(cFFx8;N6K{(fp!0U_2L>gmd@rc7%32Vi z#2aBuhc@0jHc-NUj|nMF{TG#aQPS4lCu&hf8AVBxBx#{A5d-#Z>QJd|t5U@Ak15sv z(U_tCTCUBY5ux-Df`UFq2+17?NtaxEqX3=3&;?)N6tTFy2NIp-dIr$D9`TQiL4rhCgMR$zi#u=$-+?MyhKB zQmh`msHcQaXsrZ)&I#X~til~2EX{FxOdYv{ca!M&*Qai(cyn3@kCtGludAm;q>=JT zXId?&yAyF%nPY6tLjDbAxBD^i-!oF1K%F-(8{D84|Ytu=73 z+4}P80`Y_cpY!Gg=e*18ro%W5lb@fHhr?4DJ-Uxpw>L6rkhzE&t2aCJokkw0&y$uN zRmjFgBLG;~i^K9DMBs8GvRTrtR}X}}jUto^uq|Xw46}KX%~32IKl~Ol0_)Ar*a@O$ z_odnu9PY$V7oj#lcT2&kbnM*;b-fVcqehP8ZI#O*Ja4cg^2MI9KNYEwp?vY=118P{8LkU*5yQq79-7qsGPh9_B0W+hyDpiwutI>4JjBc;h6GAB6mK%zpDlNDV z6e!0r+R}2m6F4Z?kEc2bkKCZ|KFYszjIU8?czCl8A;mM!yx6}4rSp~ADV`HI*Jvur zH`hKuOE^enr!Lnj)uPJ^IV6xo`#JoG0Oh-XXd0SB@HEuoUlYn$nsL+K+lNN*(H)3W z$w)-MnIX-RJIXO&S8Iy-)^Knrqa9AQO;PD)Xo;xrQtx!~2}v}Bos41|Idq7)hfxdb zEe$E==EKFR3u$_2)|14nQ@47Rp@AB-ls`IG`iGIf5wxP?bFXw3emW|oXsf5nH$uCk zWWQERwxMAtPuiZ$gOyheE7w!w=T=%m7$%U?{gol8xuf!p1E2bYhdM0$Yovtrr2Vea zN}6d73D#yM^djzu81}Q|*~luy=ng@eCob3yL6~TGm!Btgcs1~DQy+LxSxL7+@`DaM z8FCFngJA)?gF^muk&V~Y`ze@$>l3UbO;dz&nL%aIQ6+&Zf@gWgNYzz5)k%B#w+U$8 za5|63L;ea(X3*^eIztD?eZc{zkJZKHw0%fNBydE&mTsv$5!?&Io->_lrc=i_!6sVB zh65FbbLklv@%VCu4yOz>S_JlZQDu3P=m=?JLva?4Rtm04x@< z^mIg55+AjCRfjUv6F^%SpmHXpy{RbQ=XI4{GE=4R-(?W}G?(Kg^=VJU{3 z@uk=h$TCA4ES)dpeH9%m^$5AgHd>BU>}yF0pGoxSF3cpTr@79^`KbP4#ydcG#85mW zd#Kpcv_d1i*^tulZz1S=QC~KWq?U#+TG36YF~OR?*7EA}V{$91YjUg9Bi=M4t9vY1 z!(LbCX;``7s&+JSfKg4vNjEk)9#mFHM4~r^kqSxj$I_4+!R^y<9qxf0a1QQ4#ZDj)tT6L{vJt zMQf0GyaLgAN?w2HUO`u*e6w=JWrWfSed zX+QIBwPo83=hU7{aqUlGucWX8DePbhJCwo>r?6L3*lQ{5ND4ce!d_2dZ=|p{Q`lQ6 zEd2KN7)HJH^#`2V_l&~{LB9KXC9-(hO|#S|gt*Z_Ee=E9Lw>nYK>6unpXfmW{XfLL z37k*m`~Ux*p^!nSNHX)DY0i7za?6seqp@U(8bZ>HB1;M(l9Y@kv`5+(v`C9KEsj#8 zMf;+?PrHg%LMh7sbzS#;?&ZuGaem*&v>=2KIeVjXO6ec&b^(} zYke$elLz(dH|hKlL+R$p83DS9qn9~8&Cox#Y=3RSbDk#YQ;O}2<_<`Dq&(2^ z7gu{ENQhE=M-$8PCao%>4L2SXWd$2appThfITWm zu_&S!-=obq^c##Gi0-&PYqG|bu6?md=cS%zPy1qnj@s_-AK%E|pvMM*blQs+zo(l) zJ9l$0unH2DYgGJ)3+B5Y-Ld2d8dEWWkwzQY1E||bS zO-%UF(e_gW5dEdrz5hbr%B+=;=Ivx@CvREwbgo0_Hp*@jK|l8w)DsZG$0mf%-P{M2 z=_1CnRs$>+&h_>-`qF-s3{XWY^F6y4Dw|)v=TV zI@@=c@c#Y8OIB`fHPwW6v7x(aQN?TDpx0`8^1~! zU!C2F%E3r~7+|LqpJpGQ#{>5_W?%e*ZPhRR{y9`Cad_%W^@u0zY9ZkDeCCli(Z3E( zJEazH`!0Gz>~Kx}^W8tJ*MP{D!)!o>;2B4a@1jDhTe5sBYYvH8YE4&$%?tg|lz% z2lYA)8%C#g`hu}Mn7#IfQWv`N)ZhH*FBiI)skKji^p){+qiTUKRr<6@_a^VL0O3!$ z+~*;Gfx#>}C{`79^vg%*<&sE$6Uldi=m44-Z7HAj(w3RX)GwmKpv4jCEexnV5z&k1 zL`;BGh1LWfjv^eR$HY%9!J~_Mb)u*?NDKZV^EWMp4 zKo7wgc#*v7!oL|5{MtwtMfk6J;?{~(_+DdNp5oj)DMWT7!nd@0QU>~#HeK*{~I{}hhSEq#ou=62Q7bItFW z7>EnLiRuuKKolpKU0Yhm3q6JQ9e%fD zhWgDQ&ZT?N-KtMEa-m-o?6j~V#q|tJo_*&9*3Y$5WYw+EIf0@P-J1-4iQqrDe>70l zuUJ*6t}hwfHNg&-2Ip59svq=USV8|+e4RiK1D-W(DA#q%V3*s286S2&-5Gl(=)bvw z{--&=v*_;u`UJK+JJAIIm6J;Pi9pkxFU9d!lq1d?9w;vilzUne5xQH#IMxLHJ1gja zTn-+Il1C1?jt-KIuuBlMdMKK+P>jLmQcHF`~OI!ITf7%yGP zsd_3HU|Zx}!8=r5lkxtxMA^lG?+n##z)lZT*BVCn*T}HbreK7tD%3oyfB%$0Jsj+^ zRUWoX_2Qtj-f3oy3Xa%^0_9vY$T`Dlx%e^AOs`P0R8^cDTzx~Xp14|-i0r;S@N=p0 zqblc((y&o7wkxFiAe`gz2x=k&e}s)s20oeiRKlk+J_q1)AU;*9;6j0na`36p2s(07 z4WEPXsg4i+<%7yK@TrMUEqo5fr#3!y@TrT>A^04M&tdq~!>2wzhvU-#pCj;Th|iJu zG{Psl3T{#-GBPR$pBmV%iBBzj4#uZ8K6UV^i_anW9E#6j_|(IvK0b%z)1V3-O(qBJ z@#%n1AwC`PIUb)Pd^+LN8J{lrbj9Zce7fP&9iJZf^u*`HDtKU(oRoFLU$Ii#U9~+_ z+f%hCss%lh)O0_1~>m9lGp6a;B%gXE&QWpj4TC6@Hq%L#S zJwximyVCj2O1$?;A$5_f?i*56!XyI2{V!c!5Jv5{) za@8Y3>M~b-PN3eZocD2@j}57d0<{cnLP%ZasxMG#JRnyrgMDg~5O(?Ti*lTnE~d#!2m&BNmWo+_lML)u6lV$UFNEN zrPfpbl?)H#t`4b+jB0I2Rc2H#g;Y64^=e2p#Hij3sTLd6yGpf2rN2h1g4y{Xv}fXL zoxmp{RgqDB9#WMV)z=|aj!}IVQVlVx%^}rdqxwaubOKTpB(PPf_0l{9n6;kansti2UNb62;tQ2L)z12E&K%iDUi>ewmpBhY2RtrqGN)y~{uvfGifm(Sg ztJu@wA=5QKN>5X8eZzyw4CzQnhE0F2&@>%3{Yjc$9C$5bnY=a+n{KYqv~Ae*mkLcg zg-w5xraCPXK(DaruOU-IpkLT@Qz!sqT3ea!R8!ES2bbBqXV@XZ%w!w{#Bt>&K##qb!bC%)DuJFCyeUCkP81MD6gc*b$T$i zD%6AuO`RTQ1?m8W3T+q8%%PH>8!}y^PQw?gWmAPrC3S7sR8<|FHppumlkiPp(=2Hc zVY(=6TC+ma`;=)gjk~2+Ik?=7;(Rb{rc@lGF?%E!I5^ll$$=Ha6(M!PRX-D`gV|5W zy#sE0s<2G)tP7hev=OGShfVRiE($xsbb~U@3Fdga8ZayKvyhiWXX!;Ph+l@(MXvhW zkh;uO{}8By(tA`oSJ-|Esfz-&yfFJMq%L#S+d}F!uKLfg`Y|=ObiON42S|ddlNY3W zlsYJ%cB*`EJXIMYPa%P-y;0Rtsx``Kk?XW>XwRu;&m%&ri;XHTdTXcyH2&vW>)v%Dm9!7OzXfJgM zKoR~JQWb5LQ#&1t3)I^}>V#77%w+ZMkh(~Y8C)_RFjP&i+UpV%Qq7QRs!=rvsV+7u zPpN`~FUK5wEtG1f3SoU84XtUQQl+%MuT~wWQ~~NWGi3VesA?Bh%kylRQg>A9vY_yL zo4slI*f~oLR5`Ox$W!7mX{y$S{vmadt3EBHE_2nRlsY(!I><9b_?$B)WOj)%!#tM; z0|c1_=NNei4+*J@T=npfy3AFNSL)yZQD1DRzVOO9zJ?4`J=Q8>S(z7yRP&7Lia@2J zUDH$VH8Z3tGZ!jzLaH@Jl@6|QmBZa9YKIHdUcoxF=43f>bZS5XH-*$?uKM;sy;bhD zMxD*n-it#a^^tp%<9kA?swUcp0+n)F^(!6iqajrfqk1BwnrBoiL#hI!dN!mQWmIcI zs%1v?qEcyS-^ldUH{JE2J*$4L6L=$}>S0vxgjDm4>iv+az^FbBsYV&q|3a!|M)j3a z=>)!Y64yL;~p)WNaQ z)d>w3v+_$@pzbWyY8|S5R!H5=*&F}5y}Ngjvv;;q2j3Egm~yTkQjIbyPpSS@Ax$-^ z?xDRFn}eWNNcELb4OFUN^3)norcPQVA+=fu0(EgnU8WZGi{%-yUr4>iRiCZY!Gcyb zg9*_QJvyY~Tg13S1J#)!)jYG;u#jrKQH@ioAkRciH5-VOtI=EwUl=kis@QaT$h53t z)49qtxGG4D*U4U^R6!}^{2^5w*R?XfL>Uf;%9%HZOcTl!T)iDYZWSap2NTIE$cg2uGctf{8Qde`6ntq-+vM|mE{>+8R1{(c0H-1 zR2_z2htx%``n!<2%vEm=sT1x|ihoAi8N0|;Zw;x-T=fp64z4vOn4|Tt(4Gmkc&McC z4_&+Cy6TK!uDZ-s9}uY3)KKwQOK!E0y2w@62&v0lb?uNkF+)06=c_|Q>LOQtct~C5 zs?$oXh;=~J;VU!Ynp{FADE}h^$FjzGF9kE{s)`7OQsuiUO4Z)8xl#u!luCxiYa3Ga zkcp70Q^;wNs%Lc}bAnO_RWaUFMbD7a`d@K4NKP38&chDR0Be)Hbyllq?%$> zgF~v7Mm1Eaf^~Gw_s;B(2<=(_Yn{M3A=PO{H8!NW*{CLjRBepvf{<#8QC$>Ltu(4> zN~II{!AW37XwQR9>X(I7eT?ezkm@?4x;mt4W>oV-s_{m3LrC?gQQe|cI)RN&0(XS= zJlLeZB&6zNRQHBd*BRCQAyqS@S{_o3H>$@%sz;6LNu|;WeCH(KD|K*qOfrYZ+K_6Z zQN5&8TlPq2>K-8-Iq!z{y3p+PK}dChQGKFR!J)5~Idb@UNL6(Pk4dVpl}g=fC|lD< zUMAz8GJ zQJor6?J}w}0+ot#vKi|vr3#`Db(c~Fsh3GrFhNU|ItXQ++4JF$(^W?GR7mxVQ9Tz@ zJ!@1ihsHY1Oc4HIL0%eyV?bTbQH8x9Qq9w=WCmV{sxIuft(sM(R!Lb|;{VV8inGfq z*I!&#oKyC1qPS&^k#!nYt(0G-?0$-=W@(*Dr)DK;6=$B;s5s;F;*3H45@`D+yz!0j z=H%KWl@w=`dJ`LUnm6n2tVFvBjnFl?e`f!TG;P+wD-ZgY?ZJQhKFsjqjA7(>IEJ}E z4>O`TW284F7-ljJb2bk{oBKP=SY%UnYzF=jyo|D=(a>-#W5{E&y9tpkj?Nb8Y>~=V zS(f3&k_qqN?A3ERO-htiJve~}<+JC_+LASZ{^uW^y=>OyIoQ4|$4_JXI@+F<FC9g4}&v~oWxj>(^Gp0_#6%x8zdw00f@X`w&zFUql&9 zN3o2ar{g3U{eMr#shrd#48lo~7%M4yWCXcP;aspmGLjmMq)M{IplmTvXEXyUWNS@F ziOI;GjzKaZo{oVsA!|C$;K*mf8AncHtjMo{2LwEa1I7l)hAD%7F$`(U(1T5;*TFsKLSn33 zZi5G;u#i*02Fb`}401U)Ta40)+>U-Xk#kKV_7sfTzdXir9(TYy=RsnuJnn}FgujHt z#|FvB;{xO{F1iN7i;#>wW+RW8 z*`h34T&h!f6)N`#pJ`I@%d9!MbpLX>jB|Mn?l~6{W99MzJRq01I0bBwj9jijF7vX* z9G%FA=ywyDXA-gJWX}HOaV6*R5xjFAB*x0)TX;bDpKbz{?}lu5wYbqx2zKOU z?^=VwzZ%=PK;u=e1%@JLo5NHZ0|J+d^jaBYK$; ziLn^%fCsq$6%E%d$zXIR7~P&NZqK1^!yN@RR)kG(-q3)$O1l$e(+!Oa z=q;HW*U$zFPF zkO|Pm{v zcmS;lXqXnsptTjWe#;iWXkZsfyQ#9F-&b8=zghLQ-2!$AEWK@^HGI1P=BpjKzJA%? z`kF@Gw?`AZ6gq#KA@(~Hn~q*4Mq(^tSHc5`U518ndqAn-YhrCzI0rm1%=J!J9SIyB^=2dbi(WU5RVkE{Q_9#5S(F16h7|9@33&d(@ zT#rek$7Qnujf<;>%#=@ubu3&@z|yN7!d1uMvg=Fv*mqh_lJh#zw4Q>_uWe`@%(R|H zFViA17Of5N09vo1VOk`ER%6gA$Pr$SI4VcvYHaUA>m_rno9YE7ci&SrMmN=uQUK|u zdM>tuo9Y+r?WX$CoYY4cgp(pMR#M->1CsiTbHN75NU8;rYL+9K=7=Ubqm57@TkE!A zGn0`$n@wdxG@E`CnUHm>ttChP9h`CGB*u#TcX&X+n>k=?kc`L+5qbL@(Kbi4&JnG2 z@Y|qur=z_I-fxR2>5_$}qqU5l@8Y(S(eqv0^3%~0zj0*XR}%e8M@LTW4-Cbrkr*qr z%J>Bz8SM^IBN?fkfYiF=h)y};c%9b)P$6e)Qo5MD>`Cb))8a`vUZ!PDN;i)DKse*b zNsJYFT^V_G4j3trjL1($3h?o&xOM95m%U=s7%H7K? z=3EYid(MT#Sh?iD15!AgQ@{qv$fZAWIVDH*(TOC{?8v zW988l9uU6A;bVhjY10`4Agr zF!&>}9lmdP3OO4WeZK7noqwJ=-;QNQ{n5*eNQ}kkOn3mA)6nqwmSixx5R5L!5fe3_ zA<}NBY|cXC0=huv#uq44EkMIy>0J~8G}QpI%S8F$)pKG5pW)A0EKxTr|vwWbnBRd}if{898FQMl?~HPLj<9Xk0|IkW%oKeV&DAGAzBh zIqs1(&mi*Ej$A`CBxhzcJ%Z7N-uOu zS3&15Fns1SpR3W!d`OJN=T>+CpX<>uACkf6cJR41N8GIW+$QaAm(3k$Tt2rVpP+yi zS$yt8lA{+)){9ZYNqdYKrBv4}kg z4u#%@mRYzSfu(m}2-h-$%PuG7W8Y~#O3s%> z(|Qa#|2{)&Dbso!y-bV5ShQBd186;khG~%uT91L&BROKZ2KJn^dtNqc(73=JvFhsy z3)os%dMiT5-xCIyuXg16TE4&a^#XZ+BAVDb==>Fi*yBv>Mf5T;5@Qj22OdD|H8f0& zWDr{gVkpc+NXTDYD@jreFr7{?W;!IsqSFT+K&KlTrb9C5GyL@oG)jd@%SW9C6(EFL$(129~JhU=AN z@aO{`CnrVkq&P7tdT1CoLkm{cyq;`G*u~mgg5Y93(JIg$l7uy}eL0a^;FuF3F;*hW z-~ox;$?;=@WF#^eiIgP8prja>6a$i?pU&le7`VBVm|Xlp2sF4wG|)<;* z$vgnhoD7Mvl3584$l(#r0UIPEnX{41h@=>n6ho8ZOr41jEfTe6WrUTe%1Igl7DhmYU^p})nUV}oSma0zmlniNx#VscVU(rJ7Qty@)7qtlpT z((or+MK!5hBGWjLPvDpnAu(1Wo8STQf5Gu%gJdLfITD$h6qhB%tfZKc6w`Gsn_=Kx zne;xhFK6bObo|Q@Yq0dqlKJq`H^VG_(`7pQwDkRg@%$^xEq$`bEPYonk6&TTJV=bi z;~#hchV5v0=_46D7J|ouq_{3Au1SikG>m_t1uN?yTVP1o^?98H!AsvY*2G>VNmxtY z4V=gxIOar1jFm|J12~bIXgCp)k;oDxvM4F;NQ&E%;+CYiN#}An47|IO-kavyWGUe9y76bF^@(tW*#KQ;?V>iFtK@PmaXuqJjnC(;y-IS~?LCDI-q zkVs389~&eiktdPJillffDIU>Tbb!ixI&_(`!X)B9hA4w6eMDwLQ_9~M=n6z-TETqM z*&%kK7@c6uFi4CA<0N;|n zIiJVSwdXSigFTUcQdP)Upx>NI#js26aA*dQ69euPjzNQw|S^PvOCc*GLnI8E0Fz`6u)R#OQqd?vRQ`4 zh4q`vlYb}JZo#@Amfp5dO>H-@?1M-7;FH)d5qusXU)!VkJP4h?&G7l1`87$ z8G^^fE3IW8wM&9^mK$G>nU6;7a9o z6ZyF!FIOaUMRsm*>+MTv{grIKM&lC8&z08&v`{s+hM`W@3;`J)`pi|Vaf+rSThS((+FHU$#3gu zTz^65A7^m2VqAZtmvNC83s>y}8CO*_jEiL8>Iz()b45|E=$I=yXkvAwbzRvUg2pA* z8ClVlCskN?i`b#C^t$D`*WTR?F<p%GqR2rvJMf*4kO3iqmk8v&hKWBoxsTI zqnDA97z@k+ze>lfnH z-|(_4O!;73Ct0|9Mc`^oe)~t`IvP5^pTTts<7$Fl#zkT*TnX7AUhAp#^j1~bHymlt5}-$kxgGT zF0U~%Rj#lJ7Ozua>5UKZnqYX@6{dVJu5&G1qatwiBfk@(arKAJA8&AtV_XB!%eY94 zg=-i*0N3eg7#GRFbt!ONk}Ia>iYd8bvL-fMT91&;NHi|7OORDiVKXdZqhRTk<+{Ih z%rL}!wIf&9REeFDO|g(ojzD%UIi3-XY&3L!nL#$4k&QtwBO@^uvWwsW$R?m+WF!Mw z3fEzm=Zd+x;xf%^sx-Y=HkY7rd0h?!_+4jSVpfiKwZ-dFSbA55cwKFH*%hXIFs`|| z`nRFWU>*E66nqgXBez#a)0zRDf0dziCDWRTUZzE2EL!v70kr0#VOk`E*6k>;TXV(D zx#GrLu`pLG(99Od9j=$nLNqS3Tdf*fWHGw|mfoGY?vI3v3^QNt$TfDeRbw|=HMY>& zUJy}lH_{-Bq6yvvoqwkxcn1@_8NE!9#8?EE!UG82frbf^41y1W;QhJczFcu{uDDy{ zyH8p#lg<5TTzvP-%z06J*uwV!EWPC+d=DFZcF8FpTypnW#O}4W?~b7NAdT^GG`)wQ z^OqZX4>7&v=w*5&#-c~>s{=hB4bvkT^qvO2Cv(LL&26o;dqFnq(74>5L_WdNw#wr6 zA}l>W*S(dt%5d}5j$C#tBzywbJ2)s`A_uFYp}Y*8?;9v98Okf@Whf-Zg7O|b0LmL^ z7z)XNvIbC|(?m8%qxWU=0UDRcb5El zFhJHakWbLdKuC-Q9zVPuX7H?X``wI~${Mb|l8iZW26Ty2o%**dQ6%?Lu~c<%&OZ z#SWd?1yCVvnOYl4?Jtv>J#&AeJ9uzqhuKy?B<$wMC&L*>PGYRcXTt*mzL*2X2FZy0 zz&!lbVV=m$6NxM}n{(ywN= z)$AP1k>3Jm965=xB7Ynn5b!b%7#k!b@`i}KL7u3eCl1RKhvbPmI{pnb^;HKzVDIR5|m}_$Jb4-ejOm{?z<*G2viN1$@rQJ`m`5BE1sI8h}de=@z3(zmH^a?|OIvPOs5w3hNpVkq4ekETW zqxt*>onL79bYMPP(93*CjK$|4cmSUrXqXSl;L{U)y61@#@W-9xi}KzUq6}Diz4F{eu(v_vs~x$9PB2{jE@oTTP$oI+9nGi`bbc?x=tO2z8NJMi z#8`~#zymU_j)obL3`YII=#)IsM+2%W?GBO6p=jJ1Iz{Hg-}VMtfDVJDcWMaGKm*9G zA?1T>s80l+dgNX??V8nxJthorSD|GCJF$)D)K9$UK~?3L#Wp13$qT%?H&l-8%oW)K>e*mPtSRM>2b*y*tJ zX64~Z!K$#?hM2E*PwY%qEm8HurwoeK{@ zb`}~&Mlz6H17ug_i7WENJk4vgG#w+Gv1nXgSILyP!sc7N&V!|QU5M9w!^^HP<%28i z3Jce~2wdaH@BC<7g0=q^F_`4;G&*hK;!*+lq{1XT8IwGH{V+7`C%&046)X-#PPh=?ddqiWMof=kO}d094!;FrlSQ%z9NX6#8{EP01pV*=YX+6G9vGQ$lK+M zHu>VXd~vJ}ejT)44SPD;nc)34h%%Ut<7D(a9mmS(|9d(LIjI*h2-g^iv66ZR9+1m= z&IKDJBdM-Ps&l?5$`>7VM(;v}Y^|fCv&qPwjv|>5Pe(_YkTo4AaOCg78AncHtjNEB z2L${f2aFAp5&21oyjQ;HnJ>EQ$iIZjJ+6D1$o-xO5pzNR^ShhS%m1-)`4>c=%(;98 z_nZrfv2ytd9+1LDP5~PvBbR>2rEk6{)`|R#em9Z6CJ}oIiuW&%{+!1z@XmRV7%Pvz z-~r)pP=Bad_P#o75{gieKCYU3W^=a^Ldv#mK9v46RY;anQPJ?BDVtX%Tp0Vy=%6tF=u za+!c!#^sB#IuQ^3ZX)AMBKDk&-M>7}=R8vI&Uug+E031&fbfsz@UcNM@|cP|rsRvs z`C^hzp6A~6=D6W{@8=$$=${E-Ysmx0l&d@(}<>L%^F z%cch!7tk!3+q}fu9B-Zls3$DFxgkLF3?REqln*|m&4}Q0BKevZ&8HW1{#?Un4)f`a zUgkq$EIwzz1NfYZhWU^TJ~xBUjrn3>zF43U(K~WrYP}N2MRX%l3cd^8W+9@t=6JW} zyQ|x629d9J$T^H~(ZhhK!VG@1{; z27_G_|D>WeX(j4oZI4+=7GB>WF=Pf{Yz@PVA2+;EekX=K{2lH7O z!RJo$^?WoRdM%FsoZ+*Y`Oph-m=B4u_&f*?;ByZe=0h_0tOuW$^Tmsr&wsuB=4Ip) z6wvDyAAbAIYoT@eb;HM3J8}WNC?OM|yK{Xua2?iSg@iUNgjAWnzzG4<<%p zEMm{X1BgAvps+zQh`kG9Z);riP8{f-lMTHB$1SI~t#W$b!bNY%@iv5Ty>D>Y<)nP< zJ1u^(&im1{=(RZh21DyTrbRErVOk`{qV*O$0K_Y3xV}gRtdeSNaO^|gV#e-%yaedzoz4Y4nn7`-ruiIEtK z*w^p?VxOU5VkCpu_aL@WsK^Pi)7IH9kjOOi(fUcKcwBCve}8o1-8Yi zuN@Y!zhLQY53TPz3@~5q$o2K>{?^yuhB;QoWw!W#3?ck>RUZ2dW=TR(8FbF3_VyvXvzyloVcS(_qq#7ZqhMs8PiTXOD zwv^FfDkFJQ-DG6XW&@cJW#!kG30b!dvpMp1LF6RHioCmwydwvU6i7zoX+)m#M7}5T zJdxDF_kh-&j+6=B&qtJW$wJeSC!?1))n)X27q|R$lzSAWF{joGL-C}L7%R2Y;Q<-Z zJEOSLNJeVSk=iky5S}<%=T!m~a<=Z}9%J&dCq>A#cv6m*X<3uff+H`5Gmf0ZSdr6f zrx5vB956OWM&#`fc^gk0=ZRx=7r7%P{B@PHJq z<`l3&GIA+KE+=`Smrmpc^t*|iWD>FGq}TrC(TDT65#Biu5@Y3Y4?H0J+c|t}kc>P| zLmsDkqQ56j(W%@kO_$2%J~Zz6_f$D6eBZFdGxrUb!O}b3b1SpNQ1I1`e2Dco82nSP z9lmdPKRGM$K(73KLwebkf4Zmd8xCSd52BYDkr<27Q}6&Z`W0LxgV8WB8tRENHK3=Z z-AdWetGHZ1LuGFKeSM?_h+eMcjR*l6X#m+}qI~e`d1eHkXUNycXg<$E=Z`RahBKel z=w&`6#^UoTJb=$yG<=pI8GI&y&p1zv^~7k6=rw8jx@_J+<02Y|l!CA9lPpAU!qS`Q zxku6@gUDAqat)1@oSD(+2uAe&E^ksaqqm{+CmKfQGoyFV%Zx~j#prW*0HY7lFe8$| z=n^oR>WL{D5WSKMc3;ZoD>N>ksWLaNq3IT&uVLw38Ui%k0J3XH`CvX%BKUkmzNSa> z`4&3=Qp0B&^Vx`A=0jpEK3m}ddH;xp`H&1g^T210CuVCtze~GqvY{7txqRjzpP+!Q zwD|0RrFTW>7`xK&@zsu8K(i%e0<`z@d~na_5AuFxG_gOS^RF<(E@xsp(aXe0j72Q- z04BB@j+hw9AT}SwuGP3INu$cLIRK4|>sqUv7FxItgr#?V2-iY`%PuG7W8Z02A?FLD zX;p>JzuwSVz_hBNmuZn0i`F6VfcmO|hG~%uT6cifZJxMA13OgO9VVN4Xk1{oS@pHp z0#+ZE-lEX)x7Yyl)s9?Wx9o3y9ZudCM-yuRoxjKsyOW6>fnFv?Vk}}QcmS~^8YV_E zh%E)Ndo->BX_S^tV>B+Vd#w7p-@)D^quRIP7Ob z!2eNI8hsVqq%hLsZr^+K$SuDhdLz2m)3?Pf`}%_DNf_1N;)P!jEql6j4qg!b8&kOe z##}=r#-c)Ro&uGrXqXDgpz;@}{OO4up4jGzts2Q}XhBSVh3rK<{xm%7ir67>@Cj_2 z#6e8_t&#^pQGeg_Hz#r#9CIQh#!BQ)ct9dIaQxUH8HrR*brYE>kw}SuJ+WISvItu5 zz?3_;nJInOMdiZZ@)Ida19OO}{nt$G?*E+H@H_bK#-RRzsqoaw9y7HEq$rVlV9Z2F zj78*ecz`2%;S^6T$slqth}2Aptduw?C90-^n@}sDb*Hwb!Qp3tLGT^>AjyNE$iGM9 znXQUmRJt{@wK*ho(ebox}@Jxk=PBN!ayy zXk-p`%jM93b66MTKw_*M-jg}3=g^S@$;csv9P(2lFC~&Gk)0Ap>P$Akz)PpRSM0?n z-z4MbAy&GKqQxgEv*8NOPU*$xNSRIri;w#z>yI#=pDtIMvd7eB0rU76#yqDa#^SLF z9)N+~cg3|yGI+EAk7g;+G$op(L}LwOGqhl3Ej!H&342o+i4>+p`;=<K9BmCmIy47^S$?^}Cf3r#wH zd&C+{Y+IQRPi$*5v8`k}`!umtF`nP4+{DTrGqFX?qZ*8v2Z^zG)Po1`sELMokPIFt zf=7>(=#~;)Q=+qmQ6E~cvL?2NAz@E!Hwl6#wyQOKU*a;{aIt6lEQy6@dWbdCXIR^%5{xzLXLDXfL0%-r%IkEQ z7rl&$%a>&2H4%ADNQrSNF*YSer^GoruM!xbC}ah5UK6788fWD-*2-nHwS7*xye4s8 zr5J?gi^N!YO@s$b(`Zfy8zdvIOOV&pl$eqdlXXUupzO{Wl+SEWmZ(g z^tB@4yqvhgYu@mM(G(2nUs|qsWsfP|X$<2c7&8nKW5JjW4`4724No%3fH4~|W~M}$ zCUF`1fk@76f2!G;27_I*WoB;GRqbUQ>Kr)WP)Upxs(KC46+x&ZBh;%A>Xj*Rc}mRH z(Oyr{UK={GTxkOKFSq7x?*GZW-Gm|iYs<}>>@o9p4a2w@#tehRSTOE}2h7{;Xn5X8 z28I!&3sP}V(*dQ69-i1&X zr^KBpaeGSKni4nbn4f@wcTec3TWrGi@3dy`b~Ahat#bXK7Y^Kv?ux%`y4QOvF`j=< zxv7&qX6o){9zKkj2Z^zG(942=;W;!sbtHqwa`1RCCGJm&`%>aw4P!mDU}aqvJZMPR z6L`OwK>t2#A-z|Uuuc#Ub0V+8F(*P|tVHOwLP+E-jvpH&Bax?&$P+2?cuG8~v-n7w zek_|$(71PAoXn3+o2BWoL^n6OJ)_~~UK(PBo zHou~A0X;8s<2&guT7b5|(pwh-^r8V|SBUb#mlLZa`20@3UX13m4LX0F;qwCX*^XZ3 zLt-pG)zpgw&@dm8!RIsZ`6MMiN{J6rVuPl1khHEYn=CXgrB9GmP)1)^lxo1z`#j}- zZ~DSe^3{%9MjuJkjOhdGK-v(2tR^}BA{tpO=={$Ovi~u%gVD>#NQ{Ln8y-+9_0TXf zl7Va!kbR#L8&l#N%_~QmCS{Y0#^v?BOqHwZCyQ4eEWIB?ynZsg?5a{e7}rJ%*EbQk zjv~K5MdQkc&i~Qi+RV5-^fE3IW8o@<2jDsu4dWsixOM{9A1SdtC4NtdEt*(IX??tG ziqN>k{y`^fUGAPMn*D_9Z=9sR4Nb|1!9lpb&53YC!79gTwaw5C`&BtYjeD+ z1!iF%086h*fy=9E0WHli+LC2gnDW86G79*X4&TYx6M^eg@>{haa*ZDdonNIuuki;K zP?o2mmvNC83)e_^fTO`^7#GRFbtrJvEfBQ}M6Ci*qae7sNUsHh^(fh#gT^IR7sP@J zt8Wn-4NI?HfqP4@z9HtT9l644OYDrSmW8Ya`hz=@!D(?UIj$d#>^$iFdIs5HjBFfw z85xPOkj;e$K$wn(k&z5!xj>dvAQ}~jhMLzrX?nSAu0Z4R%CRae-{N&8EWM)&aMxR2 zI-E|I4*3=@wIefXWHD+O!RRV-mLJXNYUuo<45K_|bPal$5s9%F-3AX}bUhkoL^2p1 z14g1i99pMEJi*&fYGC9m=Vcf)EkUWED${kM7ILbRbyHut)G$2vuIpQ zCnBrh&?~kut%jv{a)EmpUTk4fJMy8|L$YRM-7I8XBal5uj*Fv_JrA9KvO#tdBU^)B zMn+;RWN*R)kjWRKVS{8K8w6wn3&el|(NFVwOPandn|IK-yavitd2uhbc)bftuO!5) z)bO$wcjbd|4X|+ai@^0B`7MpcwE;T6#NaxealMaT#zkT*T;IY2DAC)}xWY&VuF=4C zPJuYPK#V95!wSSu4Q->`;XB!UkH&>|4iXEB>^uwF53uyc7PvRi&NI+_wIdhV*^)d{ z8(~o!W^E6RAh?MJIWL;vX6XE}hTs?`_#=9mAc?UE?t}*r{0$8gBpC#!g5Z<_F}XlY zDiG&ue1A#nzh$!vjf-!J%$#d(nuTvSEWJxY_@)_rcFidtOmDJ9Y?8HoegwULXpCvm z^ytNC{w0Rq#Y}GxdYK-HvFKIs-my8LH@iU0)ZG5-y<@YHPf&K3Tip1)WAh5!dwZ7~ zZob-)%WkHGPvG=>jq1^hdM=NK!Y><}XQ0ewDEeh%B*uc0hcQu7N21}9A{ixhEudVj zi5w-3@@3C~)s2-f5Wl zYDcb;nD9XYr&8cKWU{5uSk+Zjp+^fD9@V?m*plmQC8JB^``3@G;i%3YdBcWFeg zCxdNIG%k_5tSY(BB61=uy`=@X<0>zm2Gix`eHIb5qf;8aXs7$4DfEWUUur1a%M|Es zXH0>_SQJLV12Q`k4O1W)6xM*ka|Pnr0<#;z%};2lsQd24n)GYQ(W^NE=e|0A=lX6Flz z{7yLI$VrS9`IGQ~fR}T?*dQ5^e~-vF7Km>O#8*1+dElJ?b(yrzC*GWEYQ+xjfLikxkZURj=j&fjEKmLHhWv*=|;B*tR&3OoSK z8Z>>HlQ& zIT{zyKS(L4q0F?ojrIjBy^OSb;AE!tZ8Tr)$ThUfaPj{#+q#CnBxjjvU@iaq$XC$$ z8EJj*ERm+vzD6%IA~6=DU*Q3cen7*FNCu;W(%nSWv^X#w+%@}6+HH}|Rx~c4s%e_~ z0bD~hEI`{}>1Cy{7(aTUs zj0L4yHHMNv!%#>Dl*0j~URoTQ7Io92wnlT1w5~3jEHo~fddMoMorV^gny~baNV{j1 zh8CJ&M>?wnwX?lum z`k`@Ic2fCLO?IXRmHZ4}A#mcmJDj?X@f0k2fNefmYyUoiq@G-PcGa{Lg z-$kCM-sb%)rCHq)-qxi3rvP9U{d2;zvJyEB8gRwzv3LK<#Tjie%u8uEjl6)}OFYi&6^xTx5xZQ&?tnD*rg1vBP>VAP zF?pa>oY9dXJyZ^op(P7~zpTm$0HiCDVPMBINE|Khv@Nr~HM2^iRB9oRSB01}0s=rktJTC*dL}+t=OJolgv$A_pv}l%~ zp=oCsNV+xdCb~8jof`*N!b@S`cW#VBJBK64rt=yeqi?*L+On(Z0=H{pY;ywAkb=(X z&5yE?QM>MqX@vXWiDM=)R?ORE%)bROlZ=?pN6h0Ji}Q5M+tKfhMTGbVFcW3-5h90< zu&zn^;~Ucp;WX_JaDWe?r*H4iSIE3HrU0O8o96^Je{uQ}B$s z2|Ri7d%D@OSzFV7&k{QO$x~n^DKjb;BofW;s&ij%i+gf^$f1k#yU4@I``{s?A`f@N zgMU&9Ic!3wA)4T-)%=r9PgbWnoi9kV>s>-Q-2-!GLt-2@RJ`y*M+37V8EpE2P2Unx ztl2C>zc--7FOFo>cQ0&~cD_GJZ0;uyr|yG?a%=(*50Hm}``{rnOgHfGAbB`#A3Rj5 z$OD}d{Q)K9kfx@7HUCsC99%8SAE>3OkWOPs%~*e)F}m{L86z>yj8TOH=Obu%#z@AD z4aSU>l!!rk#vVhzcV>w{D00S1_A+Bs=QLxFlZPSu;Gx`%1s+zAhoSr6q1=oG9-bf% zXYGTBax)fqc#=E}+XoMo!*d>Zc#1p>-vup&4p*sFn&Kou#E5NW-*LAJT9wQN@qY5>@<2ma;nW`SA>{_*EE~ zE1twS6~7t|P>#={;fg026+apke@=-wTUY#Z==a8!_~&p8{@J?l55_WnPqG=!XC4_Xn*9>6jsm*_E^ z{#qz-sR=ve@B##!cvjOAUbf>93?khPAa`m&oCSYP<32pC^3ugRa*^3TBTZr)f-l1X zMt=zn6C@b~CxYOF5;0B_df1mA@#-&ooNrx}7(LGV&V@ICB7S0+r5De_@> z34_}JB`CrcdAv_y4la?`Vt-N{N|%zN98^)XTzo(-h$4B6Ls8&Tt{-t*0d9{;XgH3o z!{IRvEXN$3GAgN(QSp(s2jNtgh4Ms+3=D0oz?ueuJ&nMgj0)_@iUX4>yXaP`aL~pI z=a?XzXAq9B!kK7u@+%HUs_bx{RpFqG6;87toaYhFY8B4KcJ-{TI2@_6i)oDt2W_ly zS_I*&LpWJ`E>Ah`*_m&C|ZLIKG1>wDi@ZM43y)p z%JAOj)ly!PY*68$jTK&ZgopLB8%K!^lChr6K(HUkVA0tFo&E!~8d5QQ;M|}zm zydO%u^{QkOha!v5f|}Tc1D+0Qc-jksCjAd+_iITa9qcu_qP?p5Uj}7S zrFy1zF@{~F;R2O0mW0Y_1O4)Q!>?zudIV; z6749?r-2V>w-t#5j_6KYq@#?zIimY?{SQdP5i*$Uy2wq|K_?Z}PG_Oi|6O z!#4}2(5`y2s&T-Ts<-)FWqFb7xe{_L+v4H2i|W9CWn%o;T-`u2LGy z7WyxD{mX(fq-6QAf96kv7;X7VyTWz1KQ(a`?W${{jL&m4CVoQvL&3P3Oyps_Q*~YA z4j6S9U+bEfb-jjO*RO*Krrh&a4YWFAn1+gzAe=_#J zRqQuZG=y1#Zgfpd>{&YYn`o@c?RH_T!12xQUjG^UEv~&8rHUTqRvsmdQIOv4u6@JQ z>{;{eBcJE4$;{g06D?*ZYtxDI4%)p^8bBZ{qTTgO2M2PS-3rTM*ZaO5{Y&Hk@PPsD zB7weoQo+Z$$XE&o@N+L3{sK=jE;0@%#UEpqii}dRr$qdtuQ2Y1*59Kq9Gc-2Ih#-Q zm4I(4pXwhZlZ;Yz;c$HQ_Ek&S@k8iOS1(PZv+${bPfdJk;d3xPwehJ_N`XA=j$kGz zLr>5nu1P{)Ok|jG?Q_DTuDuDGT*{yygGsw89KZ@}rt2b}L-08ipTqE}hfjTc4#%ef zn?30|HF44zQC>nl<(il{t3}88v}+#~=SrBUI9FjaeFWlZh|iJuG{PqvpB#LW_~de& z&$>=coHS!H&eg8Tf5!Qo31STek%z&K!Y3ae51$l11^A@#Y0N>q;ErH|sH}rn=bHRy z5HFe_UZx<9#$ZkG5%@I4=NNpN;nN(S797NScLWo}0Xm3RU6cO|;x!Y*8x%xK40bF& zt?)SxpVs)a!KW=g?Kp_H+!0I=2kIc+c1`RhO&?ZvdB5Y@%O%Ra^!>;B4$uValwPdf z#lEVZHefT|9)Whirx2fx_#BT<5k8&p>C6dy05g0Ak2MG~WNr zcwf+XU3t8(TxVvy+IqaNT@y8)^R>gyEg0_`Gu}oT?*tz2d)Jv6ueu)Z2iIi3W^|Jo z^hX-B8xQ(3Hp|UgMyy%;#SHKp4bYtj*n-W-S*xS7+UlB^<&9QMxeRY36D}jZ1j}yI zgPm`8_f-7X*WsN$Ju*AvAn9qn-ZXJ)rKk^TP>>EHPlUEV)^<(K|@!M}9$ zr{lkJcAMVpe`losz1L5>li*eE{&(c=@2ML<)#yvU9UcdjrrjwpB#+YH4HxP-{}-F- zleu?~=}lzvWt=<((ka}lTG|1JG7R|uFT|Of=cEv)Z`#N##5tTcDiz{HP8*dAaW8WiF*MjJ;I;#@`>4GVEXqm3gAaaN;^Muj-F(MEP5 z&Tq7lQ;72qZ6phE5~7XVLY#?cBd-vrBicBs5a%S?$S=f+i8j1KoSkSRRftm*Z4?yZ z6ha&6LYzlvqj4clCbV&MAr02n85ewZ&S8{z9uWh;;fc4>*Qp#!vFZoY7^|pzYp<~ zD}LY7Ii0R-+yvT0@P+$8jKb;kkC{$2I6yj8ISXu%jC9UGI;ExJ^ipwJsW??9b&#~q zLgSSTlBe2UwUOv)2yGIdS5MU`*T>oKs>aRc&03y|)9mtGdLXl`Cha<;)Hi1I8rN$Y zx0pBU>c(VnFbw=5aB?-@0W8}j=@2*E**KlXaR}57*?$$-&zW^Ce*vIt={NZcK%J23 zMq_$iW51MK!}e{qJ;d1Jd914&C)%CKE7PIqXW%5psh|3AfHdo&;rbyNz|RHnQKe#J zsTf`=&eFgSm(~qra|9aiyi&{#o+v|1Wp!zZ9aV~opr>D{<}>***pYHN@IdTYJRRUq zH(3M5N0Og0rT%#uGo85>GH|Z9HuR(v%xCbFG$Qk{(dHRc+^%^J%>CgAs#%+Hr83DR zb&bJj;oG|AyHl=fVy3WJ#BPUq{%xiTccx^ zT@yHfpQF)m*^!L0yAWk}L8+KnDkkWf6HuWZW$+Cs_zSqgP-Xtaps=XcB{BV<~T zh<}k4zdk~aBR{iB{mY<~3(;PWkk({AJK8+r2x&{^PI;&ZQ64g!i1L_am4_WOF>eot z{>6OA%~6M32kM&5`;aqJ_vVl*bWKd%XGBIpQ(pd%>j)<}n5$c z%ch5HdZO`e2v^@#<*V-sU48SSs;?LMSy1ZVuy57Zo6N6|Hjk*jlgNBwv^hVE<}T;O zF!vYiwUGL_CT2D>e3_qH&QwVDs(lLWe*IoY=;xa3%LwI5bpScJhR{<4iKE)wsE(CW zNnv2S*BoS9DY)JmNR|tAs8L@PPjgL7^_wr8gIp8&wNXYEd__MUCb(IP2vL(IBv5V7 zk6GJizybUWM#HsDGHUw{)b?$q;+9fzlP>HtrRfma3`OHD30L%O9J^drb)(3KY*EDRw|a3ihD}MU3#*|N$c^lnSjQ7 zI6T=)%TM+_db00|n(T?>=b=*n;eDIzNo2k}+B{;iC&S!-NKZo4A$Xx{V(P&hf>T@* zbqFq_#DYU`D#hiTr4*B$NK2gj;_z6|pfVaGIHmPG7pY({cXE4|D6cFWCWFP1-V?Q z12dzV_2o*}#6IpN$@1gc$Ng23&O5?dw@ocGBrAy;F zX*ypv3($BkhD+nQpbkuFJR5ZRtD;I{A^CZs)PHf`O5+AHUl(m2Q5rYF+Z}xkyyux$VI}2NsGkoaLARgHfAL( zf&=)u6Af1a$*6=kQ3(4+ycAUv z_mZEtOa1ruttOU|`8(0(5jAlinZFxt9&sIeKg|8NbqSgJFu$@r;F_3&xSB8XD_m5_M@eB|@8vr7F|vGDhZ=P} zJ?@$qUgmgO;hLzEC`T47oln37*RhBYHTfh7bRGLv%-UWF2k`SW8m?`UQQM!Qwm&Wv zAC`*ubz%EZdH)O7@W*xy%ReLkP}lJL;8E_%brtz>4shiI2e{n9Eebxs{|8SMU*^gK z-yV$){AVx_!}%;Goaf*GepaJlI3xqkw}A6?sra%~e6HaP6u7xf@v3WLAFfeD+E)|iaD5FD#h-2aWf8cw&DJX3?D6e+;_(O;Hp39{Jf)>i@oP6T5-Tw?>;sOza0_ z?o6zT5ECoIiI~_e*2LN|)5LzbpAPM5iyV;*D)9r7ZK`MS0lsxF!+(U~dA@&(Ip3ec z0n+#c4bL~pnD4(Z-+z{h9i?KMp6}13>HlQ&IU4Vu@O=LnOs<*l9YL4BEo#2MBtN@K z{eSjtzP}>#-O=U|^ZgCX{ap;uJ?_jiH{ZG@_Hiczb}NDsvroj|(eAtVI>Ps^$-azG z{zUu(obXKl9do9Cgagd)> zHrK=~#pYULyKADZH8Lr&;9BDkGO4ZyGG6F$fB8h&pRS3VcK<+lS(2}>uXe(Sr?uMP zc)#)Of&)zJ-)MMRNyfAuifOGoSkxXYY7G`O1_!?s@0Qm8pz-R5C$n}ib5!H6#d>bv4&Yt_l54w>`_R%d>;P zX;rT5niR+%bUDA^?&^Us!7u6Zm!~7~%Tti_m5rTT$sOJ_RNl4<%09xjDr|W|4~sdW z)!_hR9)yM`lw?e35)+y|SR6T695GlNt|v50TGv419TlF?BZJusa+~BI5p?;7M@?ug z@{>2%KWg75v^LEByod>zb&;Et@A)J+*cy#Z|#<*@@6>9R^#T zf!vrga5x;mPkl5z10-Vxj>Zh62aD8Tk+1PLfC|T&tfFlC{W7fqr-ChSd5NFTw9B7L zs`9D6R`u`=p-xL0^RMf2KU`Ge4mTxt1P0{fn#4@55gfqJk(?7YNJerkkzDh^;+Vlg z=;X4YLfu)(H4jqqj|sNCM@xJWGda1RNiGKia&pJUOfC-&kW((_gbk9BTp^NcKUlOK zELsm1t#p1zN$Y&scxb#%;X|lxkS85N@|#KPpv!N?dCU0q&$$KU=lH>XCnziaUZziQ zX)-U0Hjg;L9Sw8;c(|_k>4qk*iMia!Pyv^(Li>WIDeYdQM~GUak8w@RF>My`fviFh9({9?ZN_4q(}%{5fBtX5CIi2 zAp~OYg4hk9f?~mny^D&yyY}9D@4fx)4ZHHa=gi&NdSlqn=fRzsJ@ec5oHH|bckgB| z7Wrm$IlQRHpayWCXacDJN#oEYvHopDpWpvX|DuZ!RmugML` z$ovwWtwd*sa(73LQHL2fLCj|)nRk`48vCMZ0WUg4|ZT=2OXHjxewN4*@KsUT#MhuMSakW5TN zP{-c%lw)rP1kjnzMkkik8GGf7y*cG2v&&0%vSV+CF`a2Pv&?2kv)PGFW`1O3$#~K? zH%h^r-p;lIYbU&lo!;&&G7BOjIb@j|$-9W*ymEIwDs>ovbHuzV**swcmSgTN@J5FD zJIm7Dh;U&|g(%G}_xE~9)+MxT_woYA7*-}5b}v>#2Se1VLI>(mT)Kxg&zHWHfrB(M zy~_4P-k4MylgxETlerx4h)<0G$wO{CI?}nld%Ff(mX!82myE(veC&XbtdD1 zOve4oOZF`<+1pOWL)eu$I5Oef{k`es&$xZPCU@_o8MoLR@-UHGSneKNxA}Ag=I+8; z$H9?dli)ZoAmJnmaB!tOitZZAgHpz_1_5Gu3>%H5)QRO{V!6mhaS4r?!^+)7GS|I7 zJYFh|hnEXcORw!%(|eJ&7PgmFsO%^v;}PY&p()Vl&}h_3kIc=kYn0Gxn0Y>qmNruxOuK^1#SEVDhG2=mG^ztoS0KMT*yUs?6JLi7L*;T6KJK_%U3Z{ zO*0TrL4bpt%tnJJb%Iwz@Q${@JC(-F(sK9cVDMH+<1&p1f7@zKJ5D#fj}FAC?09@R zmf!^&9U6^V>2bN>onej<3f`H)B~gt)N=Qv$J68f$n=Q|6(u@A2qdUmu*NzB<%P*fKFwZdTxq^CJG94xmB?dt*>bT2(! z(|&Ct^WyURWM0+umOBl;)5artR9zU%3r-xPa~(Q5d`?L@d~QSl_8Zvf@R2&h=Uj%* z>hhAa%1h3$!{;Vrdb8Qw!X|TJboi|H#)?0D&hnbvGm?hSZK892xqD&VhR^L{enGN% z!tl8hbN7N;htFMMlceDj0?!Sfy9FdPd~&`se2jg<@Hsy)e1f7feC|O|Q+Zy>RNjvO zI`^^BR7#yxUO_4^D=)dEyyPOA$_I?;gKRQaMRF*ai=0PaVpDigQVJgynb6LlYjlCieDHI%1dsubZ;2DH_hfPvw7QW-Z7hZ*<>DwjB@vmpc8r@LgGD0V|`n|8++sL zJ)`!asNG#2er1~NzzgRzZThk-?~LRl>2eN#$;-s5aU{og%c;ODc{81ByK)D3)DpTCDqlKlK5Y?AZyL777y8!vC=k05LGT}+K7Ir`o)|Jjv4!xA~y z9|}sa-s$_Xq<50UUr6Yx!sJMGvivUsOt630=&CGrR+T4MRURuZdBmy2GOk(w8> z$vhKXKpqP&AbO@O*qi7A@(A&c-EOKcGS5bCH-#*7rxpz`bf5Lcc5l z_&V&HNHz+`j|-;Hn~(lPXpNkX;wMv%;&uq&Tw69eilxpdevMK5N_ojkM!7RxqwbyRW>nij zn=#c-Dn(^v(;;Dc`=Y-z$sLNX_w!?LhF)cBh zP1t0KPHi}wRf;ceO2y$!_GRaTbqgb*U9Dy>()@r-LLEb@~=7k zbDd#flVGw9aQJFbhC%QK<>u1;>x3itS2ZKTCjLU^UmKN%O>)EGQwgXy8b)HG+5TV3 zY>!5OY>#52*_Jxl{*i2dUtaR9O?B4TZDBTJ*ksm4QY}GYqH4xsl_SzWee*hyPYpPO=SO4+3hL1>+A%GfALc2efuyy zKR~@Y0qo!d%%I30bsHxoL7Csm<)u3`XnwP#KnjIfVk(7tS)w3?`dPT;ohu^Y7=c+L z@N;><4H?9FUpKL%nE#S&o-mJh#@zk6)>$??Y?3s~b_tv0W|=<{{PP#_(wy?wH?LX3 z*rnL(J=!l( zzDO@0O7L@K|8V!Dx3C4{8+xza0rb^TQdp60lpKrzqvRkqI!dI@C~3+lXf{VjgrH}ym_*D!YDZc zbGKQo2|hAxl9b@1!Y0848=vB1Etue=!`+h-91Kk;!8Ovixpg2o%<~;OKFpUOqNAiZ z-H1HuziKwv2Md@rI>d}HcuE%Cu8n*s^C~M#B+BAHm)#1IYoB1kEAMS zop6b2wc?kkrwUr=LOd5aPHBwi;ZdjOIvw=z=0ZFe9yxzng&=1Eohx{?Y!3OfG{-P5 zCLiN;iGhI-Ix}3;$KVV_c0h*zOsU94P`i|)cr^m(oXti@vD6vGy%@zkDoVOllytEJ z`5bofiX!usfW9=TN5xWJ%f&ypTW|oImnL-yj9CfwxpY_5-YHQZK>(eHm5_qeK|OHwAiIM4zlz9X{X-bXCAj zQUbn=09-FA7X_&UxEX+(TEJIm3S40Eb$@ zH)-UhN+!jdF$QH}v=@vrJ9K-zyLWsY5mivaK!Ik2LZszFM=nb%g9E`Y749 zDaqC$0MIWAL_zA1Z3o$8OZF>`F|tTDCr8MBqmPnJO-c4A0s#G?Koq17*>uRJS+c)q zjFCmMIW0o=H+__Bhm>UN5di341)?Bz$Ywz{!;%#=fb5e>B z6(ImneKvZkB6Y}SL$;G8Yd~X+%*M=+?GzzvNFOEJB_&xC1R!gyKoq17Svh2LELl?; zc}bPOTu74d#>efNn@Bh z^m6XG3EXxh81A5naJNEHxvNrgw?P1%){09(>Tp-XJ>PP-r7_GMdg=H41a3P{40q5( zxZ9zq+`FaZ?uY<79Tb;>)ZyL}?%geSCmMOFkr^lQ5wbq?QL=+llJ!FXpo{`hkUC_GAUoKS^{258=YkD2tp`UC9Xc!GAt@0D zApqGxC8Hp95Dx=!u|+JQF+ZZ6%LZ|A1aT8OE8^iP5jR5svcXD5LFynL1>zAFaR`n1 z5$&`!h(|;ahtgRQk4}lWIRcOkS27Ax2XP6A$5_M>G}hsa+8`biK`f=SA}&pdI0^yC z%9M!QYBZ*!XLCn%w5sy!axFrIRjZrcRQU~z_5SLrTu{7pKj3jz_ z1aTal74gKBh!YTiY%3+BAaxK=263fDoJeEr9NT_U%b$KObXP{mwx*AgosyDlTLb`_ zq(Bs;4%umtoodM@(-7IkezSIcA+sw7Rl!M5wbb-QL>9tl2sr8P`Lt8kUC_SLUyqwn@eMiERxNOBV?8I zQL@WYlFdf|pehBTAa%&DgzR!lwt&X)IbY};`|<#k%u{n_wba~>X{<9hXd-7;)hH_W znv~poAb`&9ic3N2a9;!WRhD~C8pGV7bL^`Uxa~+V+(8rJ-U~(LUYnA8Uj)$EM{y}g z9q#MlzSeT@M`M^fbdG&(0=FF}hC65?-20=b+&84;J_rGH4pdwUQiuCyxNo%F2h+$a zh|D?mh}=1LX9mEfea)C)aD*?{$}XbydDJihzEzEtsdNw(t{%rK<5YrryzAaaPi%mbp@?PIO z*EvmfHr^Rv7P6!1qhxodBwK<2IyDMJLF$m*2iZNAY$=T~GJBn4$nJ@dEu)W;-Jg=| zcmx1CPJt*$9kPcYd%%({r!humuX7C90}-+n^ii^hQ}2{V+2bk6Rv`e;sR~3v>X1DJ*%OxRG#X=McJ(x5PejO0r;n07 zos#S<1OPfyfhb5FvgaUs#*&>)V~otMkB01-2-#}-DB1HV$<9LnpmP<7g47{<39=U~ z+4(f`%F%E(BQbj+LUsXtl=GJdGeEydk%ha7t{SgI z$S$RilD(di>N+bPMeK>(nu6^Me= zA$t$9cP!aj8e?R3)i7l5M98kCkCMHglI#Wq0J>g*C`cW$k0ATNlHEvSYzEk~Z$tJ$ zgzP5zDA~s;$!OHZl{lueV&r+E(8F&Q-LT* z9kTyH_Jt*LX^fHCRl|^d5h1&qK1%jgO0xS90O(!?q9Aq1zJ=^-OLjkv`Bx1?_H~5p z0s1J}cPYspMgX9P6o`V`x#7^5cq3LF%xtgZ*dA{v?fI_G1I=;d8v71JMwvC9Zg97p zPCbRRI`C^s2cAU$ooAGrg4A)~4;=W-I`ABg&Oh>Wjr*GobbtHDG7{e|#UuX}gYd)7 z#yS`8vOg>M3jhZ*-jMQFh51f>B(l!m!1H&f93>p4(4|OF%gd^{%OBh$L3sfo4GITL z^^oby2%z&48~vV2>bO=ocVfwU8Wrm>cY76+hW5jEUF z6XE^@MdfahlKXQ6(D_VpDM%gejo@x+xxb*%X*ZW0ZcAm96*4?=yA_XYF9zX>YplJA z+j_1{T+EobZRX}CF0xKr;0tTM0rb2EsaiB4Nr$W;bC3t77vfH_QJEVh6gjk)7c9TvQ8Hb&vzV! z7m@iNU9w(U|9h(cAwjsmr;qxNb}IjWMgX0k*r@+f$N!%A-`)EE3yn@+^}l<5|1)v_ zjkV{0FZCZY{O|4gkF3*2{a?pX^84RQ{SOJk{VRRcf3#Ei{|5r-{LV)GmpcAC_}|a^ z|0j)3iTd9!zyF)W{WsR0{{z&2%x@?a8*!BU{`Xb?LxONOrjPoMb}Iji5kRLY8}(o6_&*l^$5{WH(U=)O*BxV> zkNnPYbEDFdjkC4J$u|vujId5_6OWUz_Tn^7Hr0)srqP+N6Q$gSJ~mMn#3zce_9jZDP87_TDD%9Df~->o zJWt1PlyJO4SGhqg36Y#D+8cc)IzbbO&JYweIvhFGG#ZWoI>XrLG?F^e*`4TA+vsdg zWB!Y??m7ai1NjxQ5%f{AJyMdDA%MTW_VLP2LFzbhFisq3otQvl*opkp|G-El>_TRzzwsn!C+V2TG1QZVDLt8l06N>K z0~Dl=CyVi9k@aL-8l59_`Y*Dfk4^t0y}l|~0MqH~%T9b}!;H9GS+3cpVfzBOY{ zs|Kq7AwjsS=%fCloyz}e1khQ)M*WvM{;$UWv#kHS(deA7{-2fK{|n;&8*9)1bJTy# z@c&%Te`KBW)c@T%O3Z(|8XNyZf^hFaAN3#YRQ~Uc06KfIQU9fm{}i@nRCFZ|fZ;k&ULAdv$kNS^xD*q2e0G$Ka zsQ*&O|Euu-O6&hYH1bYLGcx6`VC6(mGvi*V@yL0I(7~80(A6n{4nY8&Man@z>Hu8} z&@~olF^w@G4V8OM1n5vq73jK@Kt~_|$KlFBLFxeA2+;Kw=tvr4Po&!KcT05cULPSl ziattqQ%bTL1OPflfhb5FvRfg$*^(`x(YaH{?#=nf?p^V*YplJodz+43%ow}3dt(<_ z=MLZtYnF19nE&<@+4vt4q|Y+?sQ+lE8oS3MfX;DjbnHqU|L?(n*ZRMlM&|+b-_7s; zgK__jwdeo6>OW@qf1l?+vd;bL{|b)6`xV18MAvRNqyz2=n5x@IrgHlv1khQ@M%|V= zZa;$C4_UWQrqOvq-F_&)+fT;bHrAfokE+|4;r3&m+sHbPtJ|k=l$hIQVF>Afdn%^t zHj=5_J{=9@A5(Q3$y9D%gaA4hvQf9Cj@$3x z_FLBNi)oBKA!5&`H&wE?G#)t*QM`mcO7?C_vda-b=Q0JNAa%$-fb2a>b_I$+aI%JZHWlFMJ5CG_A1)?Bz$i9Z`f0pc48e?QO zn}+Ov5whFpqh#NtB)by2>44=Ks+MF60C z6o`V@Udvuw+lrSj+YC9|0(dpPYr;`7uNz8Z?pX z<0ny6?!QxVKZ5`|Pb)43sl&YOzQCXHe4(BCRG*NB-Ic-(dsF=IYxBHVAG zsNAhma=(iJI`1eh1*yZ`2JVe4_j@!t9VBV)M)|YaQ4GRk-dKBCZL3+ujI6fvvWl$J z9(bN8<0!R6C#aPtIzbbO&Ic%JbU1RVtbU9DIv=sotV$gpI}@EwHaefs=yccUbjlx{ z9`WcHYcD!oG&-0OovvPVkafCgbUx)MwL~YVl_xqu6N%1eC~9;#a;oTji2yoZu+iv9 zo#^x?Iz4T4{zqe&JM^_%&xA2=KcCE)51I(~S12lXpOoC+B7n{}ic3N2aQB0|ujT%Z zMrWWT&Fz~%tAoTKJm!tHm(~87Rm{k$<7E|DX8`a#ZpKk+iB3?<%W5P#K@*A24=8GM zIC842{)_-RKe5rQN*y0JB|0TGI=|594AtnASZ23}jhLRzzcr%-#_;WZ4K=1NvypwoFOZ7y-x{DG&vzL$)K8m>6MtdlQa$SGdsQ)+CdD$>!Gps zX8e>&Iq$`c89&XN@yI&c<4R#odyW#&54>Sr4%b-!@*%L_|AJnw4>m1snR{((M`SWn zE5omywm0(4wFDicFjr?|5YqlUR3}l{uF{=~zxkhWv%d@9S z@dUtr=WK2$Zl~jnm@OGFMHYvyB0VFwpmfcBDIvF9R}RQUBNtz6yCvDmdm<8SyJM>Z ziL|6z4tpWMF?+Jnfh2VXz$^yR3_Fl|8>2pElVRh`(SbB0|3I1>A4ta98%R6qK*EfH zG}{|U$U3{|KRMzb%m~oU{y`v!OlL}lkncc;1y*TG^Q8m^%ev*00Qgvwkow|#ex49+1UlxJ`TRb(I! zO|s1m&ZzA$Y;|yw>QsYs1Ogm$b2d6SrOx1-&)}SA2WP1<8fi9VW;4ocvTU4vbP&zU zKUDXP4&@Ga)P*Wt+)e1ZC8Ia+As2N!C0PYH}J%KC|6T{cVe?vc^IorvWb z{lU;kRHi1`=0<|f zQt2MxjgF>~U#Hti3>F6rnyW#f{0yJ|I^AqBI5c4p*~QF8wB{yn5bdYa%S;%%pv@7b zg_Z81bsI#xius~s^MpZEfw{X_POC;9E;E=|%@u{iD&2*eV>{d`a~zAp>}{J1pE> zMKco}O%xZ1P4KPjxn-1>t{azS{Q4tRU%GA%LoAjI$Qk7p67+UM&pkw-Rj9c12tCa1 z(rl>16Jiiq;b#=fj%2klrh9}G>J^tBr3!oIQz*$P9F2l8-7BO}SX_FHD(sz4VH2a^ zVCIMlEO@dH<~qI)rkdslN%ltoo&DHo@}$oAK9=#lw6dhej_(7E-GOFv5Sz@3N_VL@ zzN5qUU@9G3Bx~O4ZY19{xuAt*iTt3 z7Nz4W-IeUD!|CUtV!k}tJYo1BiMhK%hySYF@IOivPO5Z|4-e?0a~#XV&Bx@9cT%{y zhGvF8nj~kb*hGgvfnfL>mlKA+IgAA{YdorXO; z2@2g4y=)idRx|&1*p}0)>|_-%|~^VQZ{&YjfG^O1ZGbjKP1Ycan#!bD8Gya*mQYzfz;aZ*mQm(R`(}T@X2+ z3#xj<<0>({u+qK28^$dnpSf3y!9@Xs=%@BIVsLT5piyojc&pl4F}NgPFvc!;H?T{% z#{}Zze`M*eWEQAeLHE)djOR54e>1EUSN9v74!U1+b|acZ;3l)VSq{FYZfoYP-kKQ- zly}~Ft0-Mj>8>G@byzcR6Z0#R%@fwlJ1}>z(DhDM7=J?gKiPL@*u+b@1w|YBq>xL5;c1i^Rd^cc+}OE znvh4>>)fb@k4o_-Ej~t(Ge&buBg=gUBcKa-F#a-{AICO#+^0n0W>t7vinnO-84)|S zZeq{+V$V@z(YZ=B#EHz+EIQ*B(IBI;C=0a|8f0OXLc=VFmO`T}2bR@GBpf5~5=B1> z=9k(yg}GJLUl#RCDy8pV9r)j5$F#pLoi5RjowX)hZ;0Y;mEoTXlzzEWT0Y=Rd}N#i zuD@6W zcSPl`B$dZDK;>Ogag$VT*Z`IHMCI-zl{Fin^1i6tlb})&m=eh;&*kR>QMfljp}ejN zABw_#2@1Q`RpBF1xIaOm&R%>h3J)YG)I7Wa(fmYI9!ygCdIMBG6_tmQRIc0rmCr=w z;Utxog>s{#ZnN)mQF$au<=YKl`9f44O;Wjj15~~gmB*4)uH68Y|B1@uNh;TEfXY{* z@)M!kR*9yTFIY9^2G$n+5efjB*I@r z?xh5|n%mP7t`o_ZlO!KZEBUKPzLF$)Z(SsFA6&nQ%Bx8#4{U(S@1pWrlFCCHpz?>P zyq=`;WnEN~Qu(JyzL6k#OsbLbm&m=DAXn3313pgv7L~X3?C>9oxlH^^krQHb)+nc@ znYDTqj-i}^7Gyaul|o^bvq>q`%W^^}h5A{}>7-DU<+Mx+4YQnCNuhC;lOriK$#Q-p zg{E0fQ>4%=%h`q$nrAs_kV1^7$2UMN?axqy5?K+dn^rctSsE|NX&#q$5|(xCC^EPZNAqWvNGE@F9Z;!OqB z^lv0|#WHt6-;E+8ilf2TLli7uVfWGxa}YgchvJR8&Riz z52mrZ#(aAeItTafKW-~+`Ok+TNC7%{( z0D3u~K?3xt0+sw1kfg={ZIT4U*J^2jHuZrv6QIu&Xh;O;Lw^#R`7S_az7LI<2C{p< z&UeY~OFG|&VHykO|0BD@<%x^~;!B}0%W#rHQI>%&g$7wNAcclm=AwMgik5S&a&INF^~*l0 zEO5MqWdcos7zA&G>T=_+SrfIhLuW*{k#6VJWvQDa-Q+uo)pShrox~IbIO1eBx*kiN z?+d=-JBcstcM{tfqp571?`6$&zXUGN7Y;v&LHG*?W9@z6@O358cQ9jN{?>%EU?j56 zck2B193}HjZTHmeGetG`F|p-=ha8VNg8dqPx+q1z#51d(&mUQizp>{N{^zp)F=>|R zkUIo#2acmjz_V0In1uj3Gudboq)rTfCJ8^B0Jc!`q?d%?5o{86Ln%NSxUcV@#)lu{3d+cW=Ra$;hfpOa)Q?3Z zq5sw)p}`|cLigl2noy#YDxv!zfX?1*G@()_9}VX5=IeRh-+k?CjP_&WG}VOGpO<%O zD~>1BSbGU=NGgjQ%t&bCdHP9FFcMj(i6-;_j*@9KFC6Khg7>}YL1I|3>wWTFU_nir zb_GVtdz{fekx}!Vm-e8FL~juauJ1}>#@$Bq_;e3v_YnGN)Nv(M)DJ^|;~&aKqb_x# z-h!w%vr#|X7#(3YN1DyiY@GI*gJ$`2&>@}!W9{XjrRD%La?sYx0kTdz%|Q)E$+U{( zAgJKwV2K!RR0qRlV%TP0JYV*4F@Kuce1(qaeF=O#O0MsFa?)DGleR(#TF-Oa5Vkse zd3>TArZu+FzX!E`Dc z9ZXVZFm23W>SzbkX~yVuvpK_T&SK;A(!ta*|6uAJA56yD8%&*bFk!}E>fsG0WSyQm zm{xO?Oqa+Q2`YGl=^QcaIxiD?QaQ=+JTdIHfrBX|GH5iZZLHX4yG$G(ZNJcQVpi75MVH^VWWdd>I|j~ zgQ<@lOjpzB4A61YC(pRyB^?9f}UeZyjXR;w3 zaMxn0ZX=n>?duUh=Q=j(w$yQZ6WktT-M)dwOg8t{knVim)bb}FgETJ2Q+?Vv_OUcs zJqg;$N79WPLp|9vr6;!_fX>b800pVz$q+mlY(2S^#>_T3PvobxYw=`ot)95S-QvJ) zNUH-wQ#x=b0_fbK+!Uma1DoT(FzdiwG{)W*VgH(1|K7$O762DAmp)21A|=_q2%vM1 z0#T4UWMz<*TC)3S%uhB|lU^DjyPrNvHYz3ALkIx$paM~lI%HcwHrkRsY>XZ;n@7#& zF|&ExY@TG}Owx%xS{Y>(jJ>RL+xWyb*51S(qZ1o5Cid3e#75TH2LE^k14qeh8Tmj6 zDtI3V&xqmJd2;f_9cA+b?sK%cTY4*UO##*7(#fj(yl>9kJggF_w&K^x^$PDsp3q0iWt)=W_(m`HYRC zN}YMTJ@a;|owr}m7<)&oeOt=*x}r?g*_xYwD1J#FC7Yg->}v$j`AUH(NFB17knLc} zzM(NjW>;ZDwnK#MTly&3tdwLwAOO(!3PeHbknIfFj+X348e?SkZ|e=&juEn-=%Zw_ zQ9eTS-MFO`S35GjpBHVwYsNC~Xa<4}KoqrXVg4E$&0C$z; zE@%?v4qaYUC2-quVz`4Q!d-}>a#yG1E#L$(mI zgDhEFW7N)U+Ox?V`kyB_a#mxY4+=or`=1>}<&b&qq3o=~8BHfKUz}{7a7NP^bN3LW zqxVz%vxqKX6aQ1ViEDu6^us^t5qFy8&Q<&m=x!pixYpxz51Z8GIKe+K?Ll|V@S>C% z?u`J6?ZrmtztqX_5oGu%*kq2`fD9j&l;QrOa@0Kcn7U=y5%Z&y%@Z;_ z5OepaS|dLwY~n}0&^5qy$?zs3a&)c7*)(k8AE!y);{-E2nC_b4BU5I0C<0`72pi3? z)XDHtGF)RbJdDQ7fq{!~8PN82=nP$5Y65AL)nzz+lx$f_vQh-l8KFQFqz>8fkR5Bu zM$#A~vlmN-?AQod8GV#&c}lV@0sxIxAPQ24>_o^`Sh6i>bWYI=)D;Slc!7Fq`~uZj zdl#rH^#T<$PUTPXE>MwmP6nRe72zoP{hz6s2?^3?OZuq)Xs5as7>@utyV_3>r96Mx9_%2aZlc&GUyT~m@U%6L zLvYaipCaZeHF}(_IgZBgjFd6l76EuCvC$YxofxhrhG*FrPNp$)Zrx(o#*5)uNim!v zN_k=!>>x4RPHdB7XiO7gcy1kH7(LEZj-xR=CuIz$BLMIAY&3>aCx#ag!}Dwmcc3x< zn@4NfdSN>+5H^Xz4EibEg(>NFL;#&x3PnNc&|L!EMV4+S8Z%!et*qg16)y_V>7))e z2=2}ZDek2yapxd_&MrzxLF(XM0q$iMcUKynt94PkOos$qVVNE$li3LR$_3#%iK~W7#ut9=Sfsh7;1EyN(<{^MiB^w=KQYR?a5tOwy zC{;9OZqN6YwVICJ2wNM-q0r5zpVD2Ql5RHy(5Y4^3Q~veCg^Ukbi30SqqCpgKHUuw zx;^NpbT_A@+ZzF(_EIPcQitv~=x(ue`_LGpv!CBS-7OKied(ukx2L2#00E%(S11Zn zhwd)u?yz(R(ipp{viCTAx;r9t2hmUI+>~^S5CCeSLQ#-9boWAcx1~FT#u%Nwli}0d z9idxHKc%}bCEei&0Cku`QII-x4?=gpr8|Pg7@fUe;nUq8p*xa(O7~Dox?>Ok>S%?c zAa&>-h3;WXS3_g$jqC}rdpJV3gnml*SW3EM5ddnLLQ#-9bWcL}xTQOe#@MXzPnSA) zE6U>$y5s4mbWf$EI{^WpRwxt&sYCZHbWdBl6KRam`74U0dpbh5l733}TuQoA5CH0A zg`yyJ=w5{Gc}sUHjWIfZMX_|xN9b13Pw8GtNp}VUK%K5o6r>K_tI)k{>CU7vHY@xU z#nQbTp*xFyO7~hyx^oZ!YPCX9kUDg4Lif6*JD0{7oj)rq-Rlv$^XR8^Z>6NW5CNbr zP$&vghwfeI-nMiX(HNuiR}@S4c7*O?`YGLeDd{dl0H{k9ih|Uk`w+VKE#2ib*0Q2l zy7wb=SI|%CK1xY<6#_u5Q78&hhwfA8KDKmM)0p`#?>R~*Z$Xbk`vO z)U^slLF&+b3Ek(G?s^(ybpDEB={}Fp-9SI3`(H}Bn-Ku&CWWFPb?Cl4 ze?_r$Uq$F{rJvG$o09Gh1c16-p(sclx*wqX&eGjUW9<6IpR*f#nf)$8cNhJX?#GmL z_aFe&-3moP>d^fH-A|V8UK(R`{+zXRKSk*7qo2~POG)=20zf^WP!yyN-S5!-YUv&_ zMh~0KBWyB%CtPjYk!TAwHtD|x!0jE2$3*GRdG6or%ztMA^CkL{!pFt@uVnLtyO&Rj zdGz|6vjhIJ!_XvLpZ^Jo_los6v~WB=HUy=aVHGMksp=2bRM!z!%Ze>5HOtI}@8BO8f9`0;IH z?Ol}?RLRr6m~mBFRF!+$7g?u4m4Lm@Q8M+bYI!a+VR!_OV28(>qEuMr)~~A5@OVqi z>m{2f43Bp(cMFlu|MkVYVUwhEzApz&9%O!u{ckvQ^wraYnj2<8$7PUxfSwKyqMYhd z{9^>r`G}1U52=&Srd1P58drIbe}7_(J~f-q*koF4V8$BbMC=uKUx-q(Dz`=5GWMmI zH%~TC$k`eGammhWNafc*3xF|Cu8)p+5EyL({2MZ)-ow$zlu_uDz{zTGWMI8w@o%r$k-oZ zo*ZjKlMw4RfmjETCDwnT=eAXYd`s}(VUwg0@DC=MvDPUwR?t*4wjLeLnAFKwM>5vl zW~|T{)iay=Y%*OEGG=e{C#;I?lQPyols2w%yVNaX4aK~3vUx(r8e{HmTx*1zgiZVi zce8V>SWG(Cs?scM;;S@qjoaa&A>X70ztC$=cg@)uVnLt9CpOq?OAK|JB3Yx(Ko=gN58Xl z?^Wv&x`a*qBlx4FD<+!59w~F!0|9c_osH&D>f|s(4*S>~_B2Ml%%->5^f8;hX49XI zv#FjK_0e>R_u+?RIWZa%KQS`a-ic8^Ju$+J6QdIE#0Xhu6Z|Wz8Ng98{j0)XSOgWk z2Vw_`p;IM8ULK_|=Zz)OIG}EWud{bC6H=FxC|N`|6{Uey?tr=tzQJNXDA_z=@D0J- z?O(;msqojVZ^^@(qc*G3{0wEEGqlQcu8VQ5Y_NuBnCu*8cXkc!94Fl< z?A+Y$>>lblLUxX@J9~t7mdegjyR&C#=SbN(((ddP+F2$$%k0kHp`D{-=P0|gPiW_8 z**V(o>>Jvdm7Q6;GZWgmh3wqI?(7%ZIYxGlu{-;Rc5W#>Ouz4h-!a&rbgI+vHCYpV_QRUiC7mP|;YewOe^p(slzq|hLX z+frzl#YHJJ%Hoa`^pWr^+1E-T&je=4wpQv%g#>D)zEnt*!5zo3TUFMXQG{|e;+ zbbqh+ShoMD)7Bz4C@SYv$s%AP&oQ^bh^TMH!s1~}O2mlt+cr_$pQ;%QOVgnaV~3D|MFgty#(^*rj}X8Z##+eG9C)?BXqZ6Lb;JEz77*r=QYo zlag*G0_e<8C<;=CZZdR}EZr;`V|4!gFH1KmLboIRlx|8&y4eT-wX;G|kUDhJpxe&U z?LuSb-2aZE_ZHqf3b0^ax!g{giHIO1k+7 z09B<>6r>K_PSDM=bPH&VW!67mx0#(4p{u5!((Rm*ZVv>2+FhY2NFBO4(9O1Vd(s%A zONia<2;E-vQ@UMK((Q`?Q2Qtp1*t023{wT#BPGz02*7cKa!`;uKzjqUrv*BS#u$)^(4G;XqcK&WeNqA~K>&^#<)9#S zfc6JyUkkL9M(1EXKi^jY63@>U#?Q}R$hh0a+H?C* zbsIC>KFo6)S?6$d`$UcsbK6YNkPf&jF;%ybOy%||2%vK^8+BXixP1(6A7$M>l}2Zo zx_wlBw~vjxZLB@FYt(JbaC?d8HnPrAb$b;@iMeeCc}NG`(=b)Hkxb?GnFyeB1{-x- z>bSiew~w=KpJj~BHk)(UWLDPga<7|r-g8`FcG|n>=ZVq@Rqjf5*5ON*^TqtcWb=f} zy$dmSPe9t-Mfd*{PflvhpWzl_%dt)i97~MkEo`Wo zW~1si(`hZ8oHKQH`efmICA=x%toZB<(o8NpRc9w=%+Axj*@>)khR)9G1nsrl+3HyN zbN17!2CX0*1-SD|Gn@|8av{o1d>F5%x2B4tq?)idA%M<}Y&2C;CspT=s=#SP+Pve1?o?Ar!{D8inhg`Fto{hXtx6#SDNYmrf#L{zdJUu~z z$z|tidN3nB7kKGG*11sAbBCaX(sO<=Aw(sZo{%(Qy_4RW9*&YKJ$EC3j>|^VBX!bq z8R@yirsp0SGgkz{7k()A63ta0;yGIrQ`hXyJL@?5y`q0*Kwr{h@{nux(_p6f`@TAQB7Xw2LY2%o$5KW2|HPMSTYXCRjx{c+L1F`zH$kq;#n zH`DB=$IhN7>Ezs^>G5e|>A5wYo*=>Gvg7$+!Y94c=p^Dn?1%hH+#(P+Gfv- zqVERu1GC38`{^-R1Nmh-IrnOM{3FEDb6-3?LEOn@cWQbtBRzL}=|R@HN7M7FpoP-o z1`|S5g6RoK!}uD#H9Z_9ReIh;0G&73XnLehdLAS__uKTmMPvSVlGOC{&Is=h+lI~*!fci+GC`cW; zC!u@X(tTo#J~f-q%;s~m`NC|zV&lA`1MP9UDuo9czcKb|e4rWY+?hz(Q##NvW1zj{ z4K!q(mvx|h!%;F%N4^jWDtKQAeJh5~cwY#ax2AkgoBOo=p2fU1z|K=5WR1eei8BKs@!LZR~;@h)`|J^$>s@{ z8NZ2n^g#l!d1%8=P#?~L*EJhVqwaVP67N~AAhOJZKSb|^DnEe!%TfN6T`vZ9`KQe$ z@_%FCKCj}k!ub~*{@*?S6E^X$iu|{y{2MmOeRJ@Fgq{y6^PS)Nu#K#UyglW`kWFE6 zcpT`SZ(ogB$PD$4s0d$%v6a}e6_a1cb zSh^N8)dF_kpErLt~82f8f>9eGs8*OFyOi zI3-;N1b}L#Kj^-& zbX{qT(fQ-9ub0^`B6Qv8r*vPXr0aW;4P%AEAk_NNS4rB8GlX5I2ZwRHdQnVQit&m z7=N>jo6#7Hpg;Qhd86;QNCbz_PwD#4|IQ7y3J{f(fOm#()|^o z8$my%`!^+B83I6!R458khpuq`#FF)vZWN6%I)C(8y7dvd(ezWgdh^qLo{d2Os4WzV zg4CgF0A2n0-gCEG(il52_A}ex%WVDm{=>C0?#9wj=^Cb_+X?}6#w!#BsYBNUx<;06 z0*x^`KeLvuQG{+H{gke0O1eo10JV)mQII-x&7mu{blcJxqw_Os>53zClj)~)EmG1= zMF6Pn6pDh>q1y<$mX>ZBjj`90C1kc`gl>EKDP8N7bTbeDY6pd)Aa&^4LD$C8&7?6# zmyp>u5xQCQQ@Zvk>2^i{sGSswg4Chw1YHM9H=D*7T|#C%MCf**pVDodlCB&9pmtR# z3Q~uzD|DSLT?LKd*QAAB@76g0C09psx#Z{F@n&?;OlI_4RF%D3O7J& zPuRO#_W3l1*+Z{*>z=^wj|$5kG!ym(s49D}lvf6Q3+pqa4miK?<^QnK%Z06KdsG6ku_?!ey9vhPb{>_us{zUr-Cf;%qL+`E(@K%YSnMCL?R5d~zJ=InA zkqDr31RK4|mO6fpBtj!>gpQ)o$!df~8Et#QqnC)0G;C%ih|Ukn*iN-OSgi?_%+Qah2olKyv=FiHO&e1R>p}b8Ban0w3UiR zLFzD0f^lohcruN#*A4iuYRGyK+&U7$Q|PC3+oq&D4FRB5DHH{%L$@7tlP%rpG{)%s z2mCDE2^s;cO?QqU7=7Eqz+v2^y=cN+pg-KtO&qz>Jl(Cu#NZl^Iu=dUQ1Zubb?9rRPWy;9P- z2mp1LLQ#-9bo)ZLx23zA#u%NyqFB1UBXsxBPwDncNq0X2K;5TM6r>K_fza)5=^mgl zHY@xU#nSB`p?i>iN_S97xS2YVAa&>#L3gmFdz8i)oj)rq-N6yM$LObYhoq!? z5&@u|P$&vghwd=w7F)WfXpGVMD~hFC9HD!feoA+EO1kF|0P0zVq9AqXj)Lw8OZPmD zwX7(X?uZE83-nXEqf^qoi~vwCDHH{%L$?IFV=Ub(G{$CyzoLxsR+M8Rbg$A+>6WIX zdjkQWURNjzQitw1=$2W!H))K~`74U0TNa^vi+)OXd`h}^5di8Pg`yyJ=uUucxutuL z#u%NyqFB1+5xV#3r*tQ#r27Z~pgvS63Q~veWaw5}x{qnB3*E{H-6!-@x>HipeU1Q7 zpD7dtsY7=fbf;RnFKCR-S${>bu{$+F_a*(5?(~#&Un2n2R|-Wz>d>79-5Hkd8yaJD z{)%Gh&WO-`OFyMMJ0;x@2mtlHLQ#-9bmv01+S2_F8cfO_jmB!e(^H-EDycOmA2;Fb=Q@V>%(*215P=6>C1*t=KDRdWGy1!_Q z(fKQirMoyn_c#5N?y{70>k$CzUxlI|b?B~y?s7|4&@6$@Ur{XG}`YGMolyprHfUdDZQII-x*F$%$rE5xK zjLu(CEZwycx?=h%-3=+}S|9*abA_THb?9z}?nX=3lExUFzoJ;W8zXeB=%;kIq@-(u z08p(Jih|UkyB)e)EnQn0Ygth&-K`P2cJx!aJ5thhL;$D`3PnNc(7DjvY3VxA7<)l= zeQubo9N^v=A=(&Q=RUo!XLiN!eDYd@`{VcZLPBMC>wP`UxUYAQcV7=#=UyD;NeUtA znR`@Ue?u>H=QF6~-`C51QBt#|w*m&um(~nsQkL&>77}-IY2+^d*Mq3wDTZL1Vr_`9fq+juG3~ zlpF6&Ib)u8%56z+_2=c3{)|Tef5x#PU$E}9nAN@e8*x=qp_B6limqH`JXyVbKkdF_Mn-3>THjyvcI2_eFg&P?4ZaL zqz?N>uzz6LXVRGYWPbb&iT27s3z-||xF4t=G9)64ivCJc%i=-oDUjVoMg0p32J_(X z0C6|h&wMjy*Tz|L+~`Bp9Ewk`q~qw0PXNfjj&cBgn$mR6eGQ1yJ8~S2;>RhYI2!?U zc4ngkRq90XbE5dEjp8mehCWNe-?)C7I0C%$j-9>H8#I#4PC z!~PZQUt0FLG{&A~^5@oUkM7HW6GB%>Kc)LRCEa`k(5X@=3Q~veJLtZ#bPH&V(fL;o zmhPJfT{Zob?)#Kd^fJ-4B*-Pa0!%{?&t}`yoQN7yXp(=ah8&A^_Ar z3PnNc(ESSCFP3gU8e`8gC1m!O2;KhlQ@Y<$(j9~VPzNd$1*t>#Cv?ACx`Szq(IsT| z_XyoW`YGLCDd`p?0MsE0MM3J&{R`dSmhMm*V{{3b{X0T;82yxPeM-6`5di84g`yyJ z=;|$)SW>XSdv^0E8e^|$_G7n;H)jhLgrD6!ntn=Ge?hv_swD^jRijW8qz+v}=!z`e zQW|4)e(Wq=QG{+8{gkdzO1k3_0O~k}q9AqXnnKsu(k-Vk{47`K8M?*+DDTtSpEGm3 z$Og@1HC%zJvKOahUx@%ZCn_=psl(m^_GXs-BpSo)q3hdb3GDu;u14S#u%M{@6^(DiO^k2Kc(xQlI{uwfVy0v zC`cW;UeNWhbXU??mrIOtFU36~m}?MF%-$(6uR#F1tCfy|)WOVv*~en8r7=IIKgTU* zp9to)2qu#wW@tXlHi@lR3KeUw|yy@g$ zoIj7O!jDf0{}KW)zo^U?Tk$4?TjT98A?uWjG06K57(c2hO$KR<$YKo22+cY{mXr!j(kJOBKq>Qx}sc9N1 z%!t(XUZjw9rfa0$;V7XRMwwY;&UCo^tvj|Amigfu7|FjY`KKmeWh*=SItPEd9v zC^KzPKBUpvMT0Uke^BPcgJP_`pzNeU!Hl5n>;(l`XSN3ABaRXdO6cr3sO1Gk&!ODl z9tq0F2x(9_V5*>eh5$OBveBSOouE_@lwEC5KBqB$_jsO8bZ+78Y6F${nD-a-R>rw0 z8NWgR#{VfA1*yYW1!JXU{F=sEmehsbs#K}4{;d3leo8k#CEfQ30QH?hQII-xyFs_W z()~cAvzHF51vXl-RcY_|urk)(u-aXR6=n>pJ-lIsth1*Ms~1LgODifztc}+fPShN{DlBIf3ndSNSzoQLJSt#82nA6bGXJ}Vg48#5s!hf_F}MD zV}KbkIMj;)vd&=|gMT|S{~1kvGy{wOf!TT z89LU>5VFp3nxV!Vr7kfDiGtjOei{SxQ)Q?b0_YU8(F{qQ7@SB9R@fLcr_nh@W3VEB z3{H*5z*u`RSgA3Jo#HDD0i-r!hc3RSdczfKFF78Uv{lgUg7)B{l}#X^heNm$`Pexi8UyrGWynDQo&IbzLsBOOHxPsCYzzj_=-i?)xGsMTZjHylSbH(JQDcA^ zF}TT#0kY1`8iRoxr7kfDiNZdJei{SxQ^jCY1kl-pjmALg#NZBMaGQ<6U>cpfH3qlk zkHJ0h7#M3W26t)crrF zVsNjG!R9nN4{HqW%^!nD;xRDRUJM@47+^*W9`s^>tn-k@U<600OAJDyu$R(LV}O3D z7>q&yoia8W1E~{($BDtCHU^`OQI<{SsRi-pJnStB`@l!dBJaxRQ4N|2gMD&ij3_<1 zzNa{rBRU-7VjnH;9I&W%( zUd|t(x8e~p)?S2O(+FWkgkJX|gsk(1MrbNW3EgcDM<}ROON4@E5}|3RYJ@m?stBFc zLL+o08;y|EiO|Y96HDG(Q1Xrq(%H1T?=9dtC%wPdz4T-CYBkN$P&k(V6_kB|yJp9^ zV*ie3Kc;xpM+;Q{JldU4F#D8$pYiW=)j409zo7ah|Nh6nueA9BQL#tW->}kOf-2}? zk4F$Ll+It%=^Ori%fIim^F`A9J=Guh_apy)(&mdJn)0$o^(mxziFE#%PQUPP9shpS z&X-E_Z&ZKh-yi(@Q=2b~Xx2;Ayj(i}MW?^{_YeR6)y`K)^LnZU)dfx=|LRrCpuIAp z$s|eOTqB+9)2WDm4fxkkJ6|Quji@%}UlaZ{)#j_in*6XLii75_HkUu$i?Hl(>_0^@bku?-#C@~<8L+H1$_rMUyuj{NJyzm2u|hLB#51ic%j zV`nwKDP-I#!T4q|?xM!Ggp3;}7~d+!UDf!uka4{PLozEh05tMOeS z#xnPo&T<%Vd#4|16V03Qm@pAcX;0rh^m)W|}cmHqA0Yq%b(k;FrQ?S!RF~hGdxrQW%uWR}fq@@0BqoPpY$K zr~2f05CM+!02^J|rOqeEDn2=SRhRUr_MZ8Ai1tk1YPU!Aie)GE9*gyQ z_Ssyodcj^phX#8+9_#hP54m1N!Co!pcRKB{o{04-SfA_FIM|EEK(D8y7a{1E=$GFb z_Uq|bub^LkudrXw#Ciq&@_U8-dN$T8=$GFs?AP=3GESM~)Hh?XkFJO>uv5pPR9kO7 zvtVY;dj6Z%y{4$+B{kD})cjj8ZD{k|T6bw&zi-V=#H*miuC43u*sP%Cw0hZ&48m6s zVDmB?9g9+DEFM2+qBja(H5RX#&Fg0K2Aj+#)jBu4A@a7gt(_yM?mA3c$wT2<y;}Eo{JL;y>H$YuS(p7IsZ{9}xd8kqz5gq%0mZ;DwweB^ zb`6t_fJR$Oc{&nb5TN-ybh<4=LoZ5X{{ zwQJ)3;y|lEMS6_fnvh6WUo((%Uw@nS|5wRdCPe1 zUqmAdEP_}x%vt0vKaE8rv5=%lHBC~QB7k@kHcBdWk}|ED--4|!nOt2m$>yclm^L>S z({sz_QXYOOn~BRiFq>(lUf5C^9U9%~)f5NG40k8nVz1H}xoOq{Eq4;xxwKip)TXkY z{*ltLy?Ppj?W*O64hB&#(1z}%J8ER)Gh1Spi_G@Gm>sRy!6=5z;fOklTjy+Z=ZDzh zeH*cpC`vU=6x$c9vCu zYpNTI?Hp_umR9Nh&Z^6ix=+WP{PR&7FO3Q!xxYA&fAuo{( z8f@zs9J}nievHRUn@uTQpa<*f!I)}yfe9!FI-b}sxFdE*O;$LmUIZkUL-?Oe=^l{- zgmiRV4ToJUdt%8o<9q^T;?kQ24SXL8b&AV2p4;*mS5jPhcm{#ERBK%Natuw9srI89 zbl-O55+D?p*dhNbE-Or2`bQ2B(h0@I!IJfYxDccPQjtN;cuF;>OAtV35F3rH)EU(K zFsS#cF4?2HWH&pgH({5%2cs@{1DU@ryt=RYIBNfDRoE0W=K!S}EX4!0xEV#JiaD8^ zEn|5v8S-*xFraDfILluw_BDfiHyz~u3OWRtvi($Xn1~;w#oBwq_{|nqmm9|o-Onv^q=00_7Ag#Xdj~5W2CrPi(5+ZP%Vy?;$d1GC&k0H zI9`fJXmKkk9;w9%QannF6Dfw`u1irQ9`ez*Y(Onx-?}a;^08a1$~LIvk~dihk586q;oTrxcoJ38oZUWQm^?T4sr<+PEoaspS6#BKx@1Xp$uV}~?O?2D8lw}uOBsH&uIwaM#}oNXHjRZX z0iNv8=$;_6OZXf2DqWfTAfAPQyUcz<%icm`*rd4h(CwG=gQ5lpDAo}?{Tbd+(D^kX9R|Jrr!$#vLb>ep>@jJb` zWL0&^DK>cJ?8=;7?XI#5*Pz%5bcNU~&n-^7%Hnjo_4#ajO{mxZ-s_p=OFBG1CF1$q zx+pc)D;x8JwVqy+WWCC|=(S4F+bCIY9(o%2vrddCzs^8lH{m3A2a;ndQ@#6Uu{28yF%6W7qv4tTL?wa}-d zWizuh(R-bUxhWW>URZavP=eh5X@X%k{ebLLWAr)f~!Ea{X&{VbuELc=Uk zlR~2`4$EpP5{?mAENZeETtqC=tfq$}faGCpbWBQ}F?ls(a*Z90M;N1{*tlzSz{o{s z_(^{`MI3p9X5?t>%C2F}GS!;@>ZXxX=ew8Qm|IGh(21F0&Us|S>3$~W!T^E1s^&~{ zmrQ_4`w6gyqN)xV8ETBfkd6C(QL6?pi)! za*gH_hDLX-OwE8J@la|^dX-+M0bP-Vs*gGZGz_Ydw$~E*LQ)2ngZRuMl7E5*$N4|v zz5_gpstbE&6CfHu1PeB@yD5-`MF>@t-j!Ze0wHCAC?PS0VvT@^fJhUu&=o0yf(kB* zqF@13L_-xBd_%0tj{}gpiK{tRh2>M(VtXPIVa3ExMB=75B|i_S7O!*4CmH*j{NYoP zeMKgWonCi%IufB_f5v8?&)DDM>!Btpafg3Z2~ zv2Wq*Yt(%mQ~5>KZzBi4gojwz#MEFjGvy6jPTG}#ichnan1_5uw8WHQ4`NzkblHR0 zmKX^3ph8P%#vW8`iSpP5hLNTU%C(H2Ee9-Ic`h(v5PP+ z!A7*FY!8LEmRSoLM63j_Gt>?zs?67wy#WBiZ4%}!nDBPKn6L{(96#q-sdQq!%?KwA z64#lBs~HA=P@x9DGF#!^0~D%!=zM;%3rqA)Ts=gie13w)@Q3W`!TQJg zn}5P*!TXVs*bUb?0fCFW6tFy^zHqGtqNIX|Kfl<O7g+&6@Dr(G7R1#r?KaT(47J*L7i;V{yX^o&DK;X`AkRYPaT}$?N|PWf~D*6d{rn z*LW+94_O+x|_Bxa!x>THDUq6 z?}acQ>M@~Wtb{&^tV3S9Y@mhvl;J*N7o)bUe~WEA+HMw_oqg=EJZIlt5FqP4F#POe z$CziW@RGv8Q1F{j@IWZIKNS2T6xUm5lRsJ-c$R=U46n41FvVJ__`DKbw8k*z1|KftpYmuQ#4gHGn;z%5**mZ1@W% zAv?!B{^qCTTsXuW2f(mcex6j`4?T=_e)hE;U%i3R;xL!&2pTb3=nKlDtfwQ>YIdey z`H{mbJS94vk=hZ~e9+(g7a9AQjGBuZj-hz*N>AxM z)@|3QkJtWC25F@h{XyIx%OE3fB;)intdH#e6p3UD%eR5>KBTjp4f1k6$R{H~aR4o? zEJiX7Bgw}0=ST>f1b}?Q2HS%C!XWlMVb84ACE_XXdGX=~U+?0ZpXQ>R23Af?_6}U! zw-N2X{yPW0J@Qx1amMDrhK6y7_Ot)aQ7yjt8P4&W%~3&ci1u^;&f$%3ewK6mZgW%= z9HRY?f9Gfu-~2bu@n;l=X#b0~hvl=VY__<4CvFO`Z>XciioeDyrYt7mYQLOrVr6Bc z_cxiU&zH zr^roQA~(|0H*}?MPxNhE=v%?3DeNYF0$U`XdAeYFu>FEc$(hn#492fd5_%wwL)kWs>EsyB$aG@XJ$}yTaid;DEf=`oT zzAOE`L_f}jevB)}L&P!Og`*TcO^Wxs(oZG&$u9JhTsh_t$4q@1kLf5(^HI1o>x$`l z9L_$WqLPut#w61)V`H(36`P*9Xm+e_CRVq_Mx0pRuox|*l%CPYeabEFB6Zxw?r~RB z+?4=oMr1i$nk9A_Tv{pCz^RbpMKrre@fxM{sy^<^ZgIovxEtN$zDIGl0H~4TZMZa2 zyakt5iud7ENbv!hU8LAWDSfPu`=MLhPt|dEyT?61alZsmBgN-%DW$05F+E?a<9_2F z_bA0Z>_&b}P5!+*`Dr5m89+@@Ke@&IRUP+?d))IB_jfn)ztrS^yOUS)THB{sueK-; zT-uR}gHtgxFG91+%&bOntGJP0swS`QPF|PD>qG)0_Jk?$X+|*#E@i={>4!^mmSP!h zM3Eb~M6R!=ujfkNis)~2p}zq>O<~RSk(;yF_lQr*G{_-;?OOxzOJXpQf-b zy2yO%)Su}4xX|}<|(q?9e1I7++`GZsT=w8YVzgoK@;*xX~_%un! z!=;>hrg;%u-809kGp+=uTSXPfuc)X7oVtnrau@ne`>VDzg!kSqM0tFxl{FGRuTZlUasqgr5(eMzg2k(q#4|MOJ6_1o@*fGd)Y; z)M>Vwl3odvPP66kX);?zk=2)dl4>WW^Bi|0Zv`vZ&Kvf zT_T6|^vM2w;@IlK@eX{N>^JM_P0t5#>ayQSkw0{ayj@R^>^~=tJ-}%)+^wT9&0TPb zEkM-Bnw~GG22o6?&L{r5+wMyXaAe@=69! zGlYq7X;SvV<(6^+`4uUr!l@X-0GeG=ZbB)i0jSBV0mW6XbM?uu$g3%wioBYk*(I-z zlvg_dHBz>LOOtXdxZI??iTsL`JHe?)xigwwQtm@3_XJRrS9gl5mhu+zEAr|Kry{R@ zXm-gfi}K0ay0oBDVM^jNcllDyQDmoQho%$sJz5e%7-a# z87c9U@*(m$auQD|P0utq6*)bMW|y4iQ%+9-sF86VTv6$Y=bCfj(mp$%1E-tDv&iqL z$9f{V08T|c3(@RS&kIz~3IH`pKM$8S>F3~dOL{5!6-lp#Q<3xOFI$KB{2_ic*%rW^S?YVs}aE`_$y0 zyOaM)*T#YEq1D~ca11?Qr|EMBUVbv&d6_?2Idismt((85|(O>OCUlTq}VOQuQ zUq+G3tkv>HTXpiQMl_W&O99TYJVZ#I1fM1|KU^Bgy%brUSuOIbGHXbg)mKHY!0&z5 z(?<{J*-cLxoQfr~5tC~g*j8YzatrIBI?Ty7WEbn-{dNz*e7 zPK8v%(d;5sA*GxTpeC<8imN_X?j*k=uOc`Vc@?ACC9m<6*8>1*q`VIWan!4*|bTfW3qg-i3gHEvubP~>Y}B44eiujxu3Ao|)a^vUpP3QN>S_PIt*qsZ60 zL=Nid>$=jnB>EOE^v&VZ6xLK9xv^{Hjug3_OXN0s`c|&=J&67m7y7R7X$tGCi_EuZ z{fNG|3w=*lj={uny9>vy@M%&U;7XrO^g~_fhq!W#B#vAcj^XfWQVhA$7ZQEG3w@p| z$34U`R-eXb9ffHY!=+hQOwYY=Dwe_f(Co4dPNI}1=;J=<7WZLw+{x~7pQN~R0o07h z9Jn+~>@2vnQalBxLW-x+>>|apl+t2-+=Xs&pHs(O<{oz)#eES#jTEcl(nzriF0B+V z!>N$s6*Rj@v58XJsE_-aTiiF*ao=)}yN%+$2cSlZt#B!&U^g_jtK;r)kNYXb-RVZY zTTT9%JNef{z8^qMQD3;l{YD-4TlcufDDDwA^6%B;$KA<)CGt}MYKl7P7Wa%g?pgP^ ze^J~&+{ph{lmFvReq{>n2~#4@kH|eCe42u*!KIv1(>u z2Z+A53w<(tn!*zGk$tX_(3;j*5 z95)k3XBUo+@M%(P?@Hf`=)1en-{Q(~8*vQKr_oPGVVZs5(#&nsb32@hE6^Y`yIg^C zD5Xq&+zhw4A$8ng?r{q#Za#pT5y^u~bDG}?msW}*I2BS9quE7@`zWQm^>N3##l2r0 z_W}2~k5Jr60BWR|2$xa{b}^o!jyu&o?ktM?m>c%hlv7+{u3?@*g9C5!bB~@M#ME9xml5n&wfs+-?~iA;06+Oc(z0fay5} zXW0pFy=D1NO8Oj7j`<&v^jY{cnf*$U)i;fPA%9e6xZ+m8=gQd!;Z4(1TOZzlPZRzh zqF0Cii~LdHO;1Je>V&zJGOOy6S!MV%qj|AD={UHeZYzt?f+kl}+`pvdacxQ_ga(MW|;HyVv7=>|aQrfGfnH1nh$MOJ4PAb(V57?L&= zzNJg}8{yMvb^~0R%$iYTb!JV-AC;NuX$z-Lvs)ja-Bvknwlomo5bM`Z@h zZl~}AUBdT=Por61xHOsdhD-YvfSz!=t(D!$ACj=!>7qD4=!zPcT#NiOvoj_D!2P6x4VJUR%}f{# zmoja(y}2Jw-H1Izk;l74F4faR+3CbF)rI2`_%zu+tfx0UkHM+SelA6x?GkyWo*vmR zC5}Zd91GynWdDqg-ZY-5oI(zBbM*WfH$H{R16Mzf>PvM->&Ln*zbkGsh&?iO|2t?qHZ zqPSlGsF7kHT$+K{1DD$r*-ieafiOJ>;8aNUHJV+dI!-Ac1yGaM5sIsxAcx4W$m;~0 zioAY6vrAroP+q?QsFCsvT$+?m!{sLBDe@~){u53`%IDGSl5)j5*6uu}jy5k7F1Nfc zxaCy|ofUb-q1h#`D=4oT0BWSX6fTXFm%!zgauxC`q`VSNManhN?2>XKrR)VzlUFT@ ztDcqDl3$Tm5}b;>lF{svR|Co`2%sjfx)fKPS1S1xc{PMnkyjd;UGnNqdEE@4W{A7M zrAfIHTy8_$f&7Y;d%&qkxhI-kQofy19tfZ&ul^KQEoEQwEAkoyry{R(G`r+AlJd$0 zP$T7VxHKt;;L`34v*C2pIg|W~dh*~@)H4drF7@0)^^65jlk{k~v`H7k>6UaM`4vgu z3#TIK`_Sx?^uv_&L;y8|Fdi;tJ#3#lSsnKg_qa1C?xSwxGu7m?+{vFI@+Se*6!nB# z-1+Lb3*6&AM{$?9kuOt|KkrWdHj%#>35>WS_6B^Kf;YmY97WT74K6Y9921MZTZzBU zv7I8n?-Kc4J^dC}`aMMdsSEul@M#MBSReUA*T`Q}wo1KOiper~VC~MvC)rX(s3&aA_u} z=`mB4Qh3npB1Jr<6bGOtZbi7XaVx9iR&kGeHO0LWK#dfa!=*{723&3ziA%{JbuOEp zYv5GOnrqSQB2{flISD{bUVe(J-a&ZDugI$ooQk|s(d?2}Gs>$mfEp>&;L@br04_Hv z>yuxRa&tHpDc^u*my|nD%54GEBiYtmgx1w=wI9iQO)aV|Q@NULbh`#C`Ki3bR9fbMNL~5-cxB;%h-RlG~B%Bm9l9 zuff$JR8*WhDwBQBu(JF5NQ{GH0>3;}iK&9LHv`piY(Zhh=**FhujH%}3wNv;yG7%! zz?|>uoVeq%N2;=4R2}n`v1;BL(jm*uj0iqBo;{xp`-?BlDbWsR0dB9YO%Y2NQ$4>o-CeJ+16ob zZN`+1z-FQ~Evhwy)}~Rd*=TJX)jAZd4Wn9f(AuO-D~cV7Vm(;QMh#+%8C#@sMbV+6 zB8HAwpoVMf&a;(rR8u7e5sGDm(G=k>eS~~%gc5y(du4?CDZ)5?gfZF(_vs_NLQ`U` zraKCKjX-kOEbF%$+Y5$P+PifB!>-mdYcJ>{HB1IVm z*~WNw?%^A=jRvN9aF9{NHVha=R;OWau`5unKP}z3uA}ZiN@t0Y? ztFZrK_$sC+Ae$IZrS$527ZsO&sS)FeiHT3I!4{&J%FXSH7HPXl+g;io>6c-Cuu~%@J>o3jQ{7D0 zo&^__XTjf^vw&Z!`tiBRV)afph8O0S6tEq#SXxTs`B~JH1&rAEh_x0oI|IGNB{bd2 z)aqPpnzyGL+5D?2i4l#rrsGV_&dCYiM#xlXIq~9)ag|YX5Vfd7VQ6^7(vzjlC6BRSpFz3sWyUi~m7?hx$=W8# z7pb#atj=noDl6o)igH>Wt?4pFn$IfJT%t{LwK~l;>NH=_q`98bd|Bq?TpiXbb9zym z(`)LS!s?thXmWa+a(Yvd(;Ld1HfnR)qRwfnI;VFuIepA?it+5GQ)Nf=ux?Wf>-)-d z-_@qOi{YbBl~2@Fe5$Tur>Y9R{_Q7iKUXBXSDEZ*+GM{{g~#MSLQxJXqI{!_azGp9 zsJixJs^F&QJ5}w->1WF6N5!l69j?KPjhkik!|WbNW@A(_iYG z{#NI7UX#;BgW0B;UC%2HHrOSa7KGBp)!F7gcCg$VIkpj=!BN)@V=yLi)PCb1ZT9gD zAAOClJXo;}F+CSEblGb>M)?ZLzQ$l9C%33zWM+0KFNCk{rZTV>x>QlZCCYrOpfJ@Q z%=FY$Cw3*HDRZSmUVh3eflC$2$;~W|+=^YNNa`A8Qden{N>V44s7|ULC6($TR&7OI z$(jsMX=5U7sH^mP1!GXp*oqi$bV>6D1!*&-d`&c=OivqzkDh~V)vC5;XvG}tO8Itj z$+v?d-*%eJAZu?T?V;${OCe$oPw`R15MD!! zXV_r=yv#FP+7Z&`N_z*lYzZ1P*cg#nl#!E>S?E}Za0cI|EO?-{;7o?k2xXQzGx0QM zurVe#r+5T=CSvlNAYRjx0raq8MWNz|)-1*mJv*}1>g1?p;8)>78q9pfVCE@nyHi_R zF~dg{R-{S`gD@7c*-J_H46e*xI*Pe>a6CW0Z!qp6^L4*uurbf@5y+^ z;o9J6U@z!^`$5S)QF1>dxhE0#{n6YL%5slaa!;3&XBJJ4sS52LQEKNxDGxabJR#WViirC9FQPA;a>iCkP;~IU(FgjvZd)}ehv0gC}uV@HN&t|^Y$!Net zqF)YtTQoL|Xnd2E9KCdIV$IQu!$vGG`Gq--mx)SD&s%CS-(VDFXP4=DougIj=?7e` z7|%y?-Tat}e^*ib7H#p{)w%Cbr@2j?=7-ue_lh)QzL2ZJmvU9u&sT+**l$GovENF2 zkXe2kZuej#4|lBa>Ja_(Y%%{;+Ff#Xlx^Rst?_esBF1r_sygw)^w$V$WBF$v&DgJ4 z*=44>8G8VUl!3C_(wNG}X(}I848{@k!|s%Il`kil<{@qJKd1-jM^y=?=Y(p2kkM&* zj{G)Q+zvlCSlkZ(eXzJ4{)e=GN_(DLb{YPeF=oh1qBG^6v?-rar+ikO@~^6t`K8hv zVm%%CMmY5arVe4?~wd^&nY1MUNX2{j8_r5Z#l5D(dJ})zK?!qF>IV z$9S$DBKAwyaLWdyx+0ru+H9^=XH!$1%@wL_OwUyu9kmR}`>Kf~lvk$aybD~5QARx% zyjGJibWb6=Bt0lVpxSy+eFD|hgVG3ey&lw*K#laE76fXh2el&5je1Z!0=3qIIuWS7 z9&|H-I_p6_2y}}c)Q3Pl^`HR+>Z=FcPN0E$&=3L*(u1-Hl%WR=BT%*;bO(Wk>p`Ok zbf+FvNT7T@Xf%O}^q{*5G)51)pFsEMLE{PZfF3l7Koj(!DFk|051LM(sd~^X0zIY& z%_Y!mJ?JR{J)s9JAkfo#&=LYI)Pt50XsI5wl0eVvL2C%KN)K8`pcnO^^#poZ586ne z4SLX<1bST$dWS%7=|S%iXp0`Soj~vFK_3%nhaU7Pfp+RadkM5#5Bico`}Cl%3AA4i zIz*sv^q`{zI;;nsAkZ;A=p=!D(1T7B=x06XHv;{t2mJ{Ud){?^NG1MOi@%1j{dtV% z?;#cV-GzT>%W_UbB5xgdGOT^x1q~3}f{Fx+$xv^-0J@k!mGq#h1d7*#ssqG|tC1m! zyDUQ#cX@^=?urbyFJt?$OEe_1xT_`6HInFBNpzhgszpRsx)b>&QKBSDl0?apD20d; z+=&8`sIDZcCy9cRs6G+Zb|*@cM2#d-V@cFR5;Y~F>)nZ3NTM4h(M^)5r6g)aM9tiZ z+DW30lBkm;>MV)65K(Ilk?Colp?sRqA;TyR<>6W26}U;z+<4F^HA+|FMG-m7-DKqM zGI9?Yxu=ZWiz0W`M3zMTKqOv+>8$}`p5IEK{(4Y4fo{`-hRVD%W!_mb?`)ZO4&^;q zLn8AYLD51QAo3nbpjKv zl0;8SqGyQcad)Ccl4!9cS|W*-N}^|pXudnqauA7A;5iKtYQI3B6?)K11X`^Jy#f%M zC9lf7*UP*&$h=>pyw_?-@WDFHE*BmM~DW0KXlM*vj zY*J!}TAP%=H6(K8#z~@!B+&{}9y{{`rU;x6hkE7fs z!`?2#4iaHK>9T#WY#$=i$>8b4#0;gh`fAe}s7~uvU0O1=9I411GKD*33L|9-c@#QR z8+rr}jn}TMPc7kvr(E9V_;eE5hO=CvU$_dXGashQ9FwdFS+nPUcME|$_eguMwD(DS zzqAi<%bq?J@L=}6W$}^-K3*_NTizHp`|uL9OZBi$s;O#Grf>y0yFH(nAk(4+ z;V;`f0ZHKYES58PiJZYp<;nFtq+%!Eaw*jcDcwqO9J5Ls$GjkqSIarG29|wv<3%au zOVX~DcAc=Em!C|MrTt9WJ<{%#cAvDLOZ&x8 z_R)tJ&zDlS{nCCVtmgnM8?UeB@i(w+e7}{)2ZfD2B=}+vOM67x@1#8{?J*vYodR>T zGyQ3ti6sRE`Gv(r8AbT~>Bvw9E+F(iod%|7A!arvymJwlkD2Ot@fP2e_RLUY6#FED zJ#kIXQ*8c6FM10Qu`oM=ZxKVX7oj6s=c!MVCmC3ExnZZubIO=8%al|x&uXafF$Ve% zpLoLR^Mkxt{3K7clk!yiSzato@u6W-f3KDLM^zH?Vsu9G|0em*N&ep@{~yHvi{ zQYPD8hzpeSk}4&-M25IbhPYgYxI%`wl0sD0hPc!bBJv7dgL@oTBlbxg(^JjS!I_ik zsh+8shL|na$W*;DRi8}NFH=pVRBLKez0MIiGSyn@RIhb(h)gxXCDqz8)jBfORGDf( zrdpR$P12+)hv#|_i6!tGV#h&R+a2Hru##)Yq4y-BJbnrbjI{Rz}Z54w#&1N5N51iD=h$|TSbJt#z= zEIlZfK*RK)JObUJ2i--WQF>4bfeJMs(=$dr;A7RJI$AZV7?FD^(l~9T`_+*iP)E8? z6KMiPD%C_nIu8?Qq8>CAAa=q{lPBDx@`Rf%Pq@eU3C1pylQkrAHJMG(W@vz>XO5~$ zWIB)fKCbQiq^9qD>id+YF9Iwk&;mW^Ie?fH%cK;~ODUF1DOQjaOEe@>iq#Ztr3Q$U z))Huq9`q`K*6BfE007XqEsgU%A@v>x;afqv6~ zOwW1sGWM71BsD#MYL+o0OPq1BSz-@bAxrFWD`ts3Zlx@1kNdYa6Hk`%S{;+6yz^x; zwCbq{&d7LVBlbgaS-Kr>6?L?#>S&c!(GaORMY=>A=`wYs%hi!;Xd+!jk*?52x<(!8 zT6LtWHIcj&={jvBzdBN)I+9NlsWu|9bvh_#O?^3Qt{1b$(;!RSZ)%t&-pHHAXHiT{ zqbza1sj;+8q-`o~GijSkdxNwsq`gtvo1|?iZ7XS8OWQ`;w$io}*3(|(;psrLI!UWk zJ+)G)S=MI{za>O`AwU-z&5oKJF^#(ssH+~- zi$LA=pne4Etq0vop#FMLI)QG}gN71lupX2{piDhz1c5?&&`1L1>Olnnu~~hWoYjSL zRu{>&u$X2|o`yv3KE_I-agyk6Npz1Sx|fJb+=)sh(Swp`yd;_+i6#=!eeOh)ss4vF zK>WUzdcsdt&+JE3GaEDVF`4o#neuFz@*J7+{#O_%TV}CD1#1&^B4gE?LQ^vXb4hlFxW0F`hlr?xo7!(~z2; zo&4%i<_5?oqA~IY$j9olaR;MT-vIegeWHG(I#Kb{wr-aoNc1I1v`C2vkE4x|%>&>Or*#bd4V5Cs2YOltQ3HJt#n+ z+ImoZ0@c-n(g0#xhep}rX;kBE@ieMQws;!VG~0R_b-ji}UcOpLq8laAO_HdkBx*%O z&D@FFQQECFKunZQ1ZuAb-Atg)dQcAn-J%EeAy7{}XaIrw>Or>?XrLZ6gg}GzpezDq z=t08>l&uHdL7?G!&?o}ksRtDjC|?g6O`sw@=xzdy(Szz4cmh432TdZ-1U+a9 zfgaX_rW0tY9yE(UkLf{k2{c;|dWt|#=s^nz^t2wdgg^`Rpk)MFst2tk(DQoG8Un4- zgVqt~MLlRefnL^wHUh-fx!2|L^oCrXHp%7bO`4@rs!KVq^9SCY}|fwyksf9u5?G`>Luly<{NKlDDv3gKEf#UR_O9)h152`_+YI@L>1iDNQ zx`seC^`Ha-U8@Hr63D9u)h1Aq9#oe=b@ZU?2~~FQ6EXvmx#K# z6AhF^w@RYhB+>1XXb=(gb0^B6`qMQ)oKM*V8mb2kmnn^qDdozP?vN?nNh#%MNTf*l zlBhru-6e?%B~cL(jdUj(BZ zT1Z6m+=-TgNZjUGqya+6=Vi3zGTI6mZKaI1ilRNMA(2A9D2ZN@L~A9{I!W|05xw9} zv_TTRCW*q5Xrm;0orqp>CwfZ~ZI(oDOQLrq(H0_l!=31T5D6i-YJjF^TaIFPgsoIg z^i~S0eIM4hIz9%*Bwjg_{7v=ybTByF6u z7fE}uwDHnbmbQwtRi(W|+G^5XDs6RXYe;*Uw3kbJg|t^nTT|Mrq`g|&Yoxta+UumP zC2az?>>V@*a*VvpqC43;zUZy|``I)W-vL9dRXlv#pA=%3Yu3>pGO`Ma3mu;lnZkZ* z#q@@Z%;hw0k@;6`G?R?|rUtgJ}1(2(jHmOvM|8t#lJC{FPcV>xrq zzntKBGSrp7f3rSZT#yX5EzTGj8Z{hWLkP*_%ao?4o`r~Lts7$BWJNHX#q2-!I|vo4 zRH_n(g4?5D_Gax)B0*1QX7T3kF5EJm+lKhpl4WF%2xU8lN&K*l*%}elUwYb+#hy%G z;S2lX?71;ulvfc!WZ8;drL@u zqdngJEqb+T-fXXj)lndPuWWm;_Oess2wAsSO1(=fQ>QpkBN`hWj7c7Xvk%9N3W?Y3^F!h_`vQ6L+$C+Hv_;YuOIsrC zXlchtJ676p(%voYJ<{GQ?S0bTAF_Vq;0{%BBiNL4oPPXyyE#l-8!DSDDvOyS2Y0F* z+-Y)fA0;^-QbnAA^EJ1)hz%Ew?1Nn5jH2SqLdO^P%I_b3K$DE=d4vtS{b2xcRv^R2 zd4_C2XQ?unp{#kjHq2a^v3(9A#sWFMi{$t&mgBob>b_LkXQh3PTb9$)s+^uw=JbRn zCqBbgAOkE*v8%*5#J(WLA$GM~w$_O0?Rin!muOs;X=qK)$|yy}7kzFNu{^KKYTuC6 zZj#l#DeYU*ZkG0KY2T4{3(dw2IKvA{GK$9);B2D{glWDSGVlvE&X$*1w&G(>@)x6m zm$GZbT1^#PoNXfEn4NNxej+F7E-B7uB*uF@;AEBp`&ljgj@niYF<#xXQ;|QC!Bg>k zh<3+BG(8`M==Vfub>9(EZ1?19aTw{crRtO%t6!u&E$y$;o{{#fw7*GvPTJq4{exRJ z+YXA9`8CHn&kdtAhCM+xzrn>6KfxC9dt4CUfXp5Xzx5kk9KK(0IWN~@D869Jbxw#~ z)9fGi0?|IvZpFoqmet`ywX-a&0m z{PI!97U{wZ?TurOR8CdS`nldLQ$?;NR$9>;EwEW&dIStNyi# z-}-;^fA2q;c-;Se(h2|4q#yi;lYaDnnDmqXv!s*$Imti!FC?AvPfY&B|9j$T{})NW z`Zpw<@xPFC&ObeIQsSnhnTcN~ElqqoX?f!8q&10?l1?PPn)GAh2T8vq{**K^>CvP` zNq;1*NO~!GZPNavZAqJxcO^|r-kbDo@;6B(b_mclg3MW69yfFEZ zU-DPUCz1~&A4>i@ z`TOJ_Q%|LC3A`WpB(OVBdN<^ZxwMAYm)M}7xMV`*nUxn+UR-%;F9Wy@$Mq zz2A9{c_;cN`5yL7@lEs1@Xhu;>s#Sl>3hky*7v3Fknfc5ci(y61>f`j<^C7^t1&Py z`(MGZtj8d2_wVq3<^R@y5Ce4tLv-AK!vBN+NB>X$lm4Imr~JS8Py2uMpTY2*^Pl(s z?Z4okkoXXWWOCw^#A%7s6K5pOOnf}?iNtw{PbJPzT$H#ZacSaniO(l4Ph6e2CUI@z zy2K9?4<;T?{4ViW;_<{2i9aTuO#CJB_r!@wlQ3*ElV&G9k@RHJ(@FD_7Ge;WCN0M> zzL4}%(%Ph#lU_~QkhCf3?W7Mdq#q`Iob*Z3uB6YB_9lISLH;`Fo1}wDhm*cb!h}lt zA?c^2Q%Pr%&L*A1L^z-HSJH)~2a_izPfDJQp`MaFEqQwK3=H-h4Ewy~r;?w+pf5~b zjA37jAzzlfJb7jE3(0GeU&8RelDr;MAdJbe3DaORCdby~_mV%rbl8#nQS#2@UCFyK zQT8Q&k-Q(%;{c|{x0oPDFloNWWI2^QrS?;`Kd61U_R2b|>TFDXJ@v=blbATaq@GSa zlX^Dwx72f~f297IdOr29)W1_Nq?QIA42%y<2uuu23OpQ`9C#!!H83skXkdEavA~SL ztibHRoWR_`6M-iKPX(R{%nvLGEDS6TED0b`yIfe&Ij%cZmB{;iybO;T&0-=|AKYJMQ zuYPv!$fRMzc^m5)W6ojFh<_Y2d?as+!C&0-S{4Do0mtNy;?1!f(<@nt!H=@Be--e5 zjQQCZ7Ss8U^AwHaO}ID!GjN;J&mMCO7C`n7H)eqev5*n}Si{BFH*C7Fjnbsau68q(_0PWr6cT-{g3$MKrqiN z0B?e|TYLp0^WPioA8kHgB4m-aR+FFuy2&Sh06N zZc$0*NN?ZblAPT9^t1*IZ%A*SpO;rMDz|uC`hfQ7{qpli7NvLZi-!#x*H62lexn8r z8#PML${m&71<#UiZQhh$G_%v{=ZqZb_u>RHf^0*WlRMG~4rABjohP@x6?OG3dv&%h zw${}+voL!^dfPtT+5g@1b4o^r>Sr6loctmqczdo99B4E$f<-wa;R+eSp2P8fG5*g= zGlCtv0Mosn5$xO-|Bo|*opOtNX5G=LWE2R*;|}bb)q|b#|1UQSR?h4>PjPPK=D|)o zKkE*}%K5*HrQMhWLxqL;g@qyZk?R%(g&6o^fGSwUY6cAUx3mH_bg*^#-+H1gPPCO4b6fqcT9`!x@mr4hV~V`D;CWwq!v^VH zM`e#J$qC_M{RZ{Z(i${?O)tqVEKbkP$4XdO3{^0rGP3hW4a*%~e}qxZ{Bq}vd%o;- z^ZEFkvn`V9etEQdLHUTsaAr>VRij* zJayvc?`}A-^ZZrSTh=W9kSS+xHS_rNE+3WL_Xu8Wk-}T?jLab!=7# zfBd)@rLc|_m^ix-@v_K{&X{%3bvEnTJr#fUp=)i{wIb{K6S{WcU9FJW4s}@2Ijm=V zJ^a~R!!VK}f)0)7Y0Ja9}2Z8S52m4n?nN5uu#rv0zWIZWSBi&(SNKNq&v;o{i|~9DLSu9_#r{8vb03p|s2U z6Fpz!J+q@Tt&fgRvW~Ac#-AQn$&NABU~G%*=#0s_KE=8gG{v9Fm<2p0@5*AH^|J{u zrtE}khHg)@ZocmLGX}dZd*1x$H>+Nh=;-EDhjo00bqx2wpI#}3aSa#Mg9*nvCh(4< zq5`%+zxk}+z+U*1TH7$L7DF%l)s5)qjL3Q}U_D#(#-Al<8Z`lbrnI7S=@)dVRNJ6P5j~c% z9?d4=&qb{bBUwxotP(6vjoK`~sPqOP(DSTY*N5FBqb z^}Bio{-ks=jH+xTJm!qrX4U5+3Un^kOqw;U+qedLDmD`Z(7W*6-Uom}4RsyPqbm?jdwq%Q|gd zjz2%6)1|C3{B}Be92#g~^O`YyWPTR5CAoMW!220M?!uL4K?)uuyo^784m6A*Bhb&R zyl#Mbi? zWfbIN0~IPP0@o#g;a|Kl;ol%}MoeRhke23%P!rwnt(B3RpH(splr;opoDt{1H*?^x z1HN=X=TLFi4jF8HnSUwIA{Js~P#*LUkWzb?`5HthO4>(j#flx8VAD^hn%`wJT!p6*t znTdiP$8g0Pa|du=-l$L>3awaO78-9S+^B&gUoX0}uE~C;o(Yo(bewTZ%f7wZ_G!-t zwr?+^^b``{1KS_q*#ojmaDz4vJ#sQ+lqyz~zih=CHgQC`6df=0%Pz{mvm#`*M93d+ z{H$mj$Hu8gW*$$d^eJnk=Gp~x>FTT?2=3efxG{q>itfxU;6KoXNgu zQpw94iL-*w!*_9(;a_YuT&2oP0&!)fNxPdbHgo^}n8&WTh6U{7<9_6$q9 zSi47>v%^*B@GeS1Iry%-P+|L#nMLdj-D_2`QSXd1it4iUh@Jd>ZZJxJx8}$#Af3R5 z&|;;beBR3EoUM67=SWsYb%vd5L(tNiayfi|JNh+s_^KPRf8rTM83Abv&3+k5oOB6D zayLYb-4w02ymk||6R@9g!QZQoLYp?`rQVu`qz+lNnn>z`BPr)9aT#>@$e~|{5I*!^ zlzwh$`<~VpXQYv|-TFABWeZQ!K>NNKJ$v=b=-#tKN27EnCJ;Y0W8nMEPQ@u*JTj@m zCmy>iW0amp`uG=b{J=UB^n)$+;3WfwP2E>eCQQ zFwMa3C~b6V2`)Iz*-3^(k(`%GIiHx5>#<4#s>-?`;WE0*gun^&SCjH zh>B&a;MXWN-l$zSvoJ3MlLzE1Vf-_V(f`vR%RQ`Sl;e%9^+ApEU68Yr9slBtU+t;v zTzuk;*sem|0^E1a;N+n~n#&7O_^Zh*<40;*n<2IXsUT=$w<`u&CTLF=wiX@qvLrnA z7^gYM_)7Rr^~2K8u}`0jp0|igEMFK{udD1{ZQDD$)kj`q_^HycDLYr#H7(Al>4ZBc zWf0DvQxSzNJ{gTLSJ+y@!^FZ>sdvBbeH*1UXy3H)t$elY*dEK*1q)Kah+Si!^HJx| zbawt6)yrWo<4letkR!GRZd{dF^{ty`G-WCQe3WbV%=M0SydlPr*71Fip)l22FbW_- zY>GVBv1N3;A8Wh^KWpnXN}s@}PQ$qq`y=j0l*vHeouC97BY|T)fyUO_-S@U0{o3B@ zSiMaoVD>J~D}s92O&gDubB{@fe{se?_S|de+}GAXzmsea#rAxdRoT{Qc2w2a(b@=& z&Kz07t_05sc${&ybHttN^z{gEYt7M_8T|Wdaa*RM%&6G0W?+iYn$Zo}o}wwz6niR~ zB5~jf4d{ilq!+uL8Y<*lphZ^7!geJ17yBT)#hb~V;^0|G#xV9W2EQ6W z)@uMc?q%n^Z$RI^#f70vwiO>@Eu6KY8)K8AuN%X}O(&X1Y$BfkYiyH&M!yjyd0835 z^^!GNvDk{SD!K=9`?QOm_#EEn;{*_(K=6RViU^tpMo2M@Y!W}iVf~KKyV&7#Zh8~oJMR$0S#>q|PT4-^@=*a<&gkF0J)e-cM=P|AHy%^8 z6%Xi;Ta;Op$46nFH44Ab;@7WB|L*M^>t8i+=P(7VC#f0PS-kJ1Vr7Uk8q*rYo_5ok zS{WU`V+(pts5ld^-x{T(t-L-_H;?6OX`?hoU&5si55RkG3)wra(EToPp2QpP)deed zJ7`O^mZy!1ww)|YUVc&2CS%6}ThGF7*R;Re7x>U<#@o!ozO86W;k&rec!vgl*cq?> ziuWuUrB_;=&IQ;uFT0?KJx#H^S6SXe+{>PRWMvi>=3?80dtjFH5z&=B>AKEpn}cEO zSpXeI<)HaPOU2ph<}v+b$rWZg2a@k<0UcpMe^9pmV@W=2Wae;7 z@@uRIIhMUf4d_G*+DX}3!nSH+ zqkt!wI5~PtAw^QttlnMJ%{eVuQtYyUP;)GBhO)I?bBq~i*>hZ==UV92n)Z&Au*hX0 zbe-XEKwmTsl}&MC8bRb&bo| zT+^Q0Oo|}a^GQ~RZI07laJ^)?w&-2o%WHNv(|@|vp-~!UJ>D5wkdalG!GF)&C|zec z8@M@Bt@$KU2wR=}n)c4t*ku>8lk9a1-(J&xz9G*{h{!%e!NtnrqGYifZN03vrLEXp zXEjKrUa>r<`AJn2!uOu%Sk5t)b8c6Re@0PJD1%G#oi(m2t%XDsw%Nij)wB;5DKS}l zSlEMdDhY}vR`XtUbE{tb6l4{M3IC4O;Rdbeq#Vu>I4Kc%hSg&;uPSpip3JaQ=eSkX zPh1LHqhhN=GspB}8@h~wO#CVdUP-h7jsFd>j9*SD`S+}ji!|*+=$sew?65iv)Hw#x zL}a(jk=$;p%K)t>l{`YzJyw_NbdH75H#g#qYY8nU*D{M|KufU+ro#7Go<3U7898e9 zIDBAr>f8s*3BLphRlcMpkUdQiEK&dVk%^^4E7;&PE z$Q_353VIb-y{@q*psfEX%hj}xl`W53O zzN9gK3P=hcu^bC^4qt0)EfAxA)ar4q&T)b+$3pk%)*17e&T);P5-ZbsE5HJgl4zAr zSL2O6R>2~jK^A(aroD^23pP5FZEo(da(O|@Q$!>5faPjoi_Lx`#3=pViqTB#8BSX) zk?tC+%S4{mSP0Gs;;Xgn`e1{boIVN3EFez z1*>bCT~}@nyOx}=JOQnzw>%|9z494ryivsK6^#e2VvE>$CGO0zrg)>dJP8Eu87tb& zLKOC)AGs{;v|OonBJ#BP!gBr4%ic3U6S?Bgv)qT>-C>?ETi&_Y$E=+Di(JGjitH0e zM(IZuWlw8PvAg|7>3vq8sl=6)jZb~R)yV2{lk9>Ig=FHxgGT9OtJ4NK6Zwyc&0?G`n9w?JGGuq z%P1=c<_@dp$FipgC2v5-8zW_Yc2y5q$!)PzDhv$^6=#nSxla*py#3C&WKd}-Tgm>v z{p*=f8e4NwX-{wIKSs|+Rfbi+HZCT)Qt1koP}TJ6F#{?am-O`9Rja3Ydr$MWz6NYx zBc-TTr*1tjWk-X0n&~N{Yqgy`VQFQfMR6@O4esaZXQr};)jRhy`r+-e7cTtoVRCw! z*^D>`Va8IJP)~DM$~{(?aV*Sm9)>;quVD&MO=)A(07+?G7#5BnBV<}ar(lDGVEu$( zy@X&OK~`DX1hAAE37aOhEynvT@iaZ$AYt-^Q{4IVHL%W zQB(^Q)jT2CG$GiSDryfGsudMo#VTrUSJVjUS2p^ys=`f0L9D89V^I*RN@ji|&%6W3 zc;@V|T$%R<12XTz6UGB}jLbVC^Y#hBwh6)33Bi_>d>?pIYB`6ay`6lxEwZ$RqqWGM z4@XOp{l5=KCtg%v1mQ)o!*Ugs2?o@18?OZq*fEOgj-qZ!2zE^fcBYE5;6k;I;kd=F z$T=KcML~QxI*WoF!_k9ho((ddIXf&@=7nHD!nr(QJYdJj{8nT>AR*WC8Md97`q9}G)uA)l8fLg}#TJV4!qo|=M zYDhvbJt25IRrDZSsMawYL+py2!;vlu;=^&fD9AA!`0)kA84of(9PF@MnNJ4;i13OY z62=2|jLdV9`S65bC?S|lnLh?s9tr18evT` z`%h|D(hWd5)9>K5%m6*Fg&mfwmZ!mh66Wv{@PHkomVDHbmk_*@3V8hg*b=c z&i__N0k2~|*m)i7uv~Sl00Yur%+tpMc8og4qK?rC!QzBqA(g^DKNWd$kG4w*7dytJ z@W0hEj@PmZ^t={!Sgu-L0|QD}%S*rmc8pr?M=kdz1n;Io!f1~y57*N8;yaYU8$Ef8|)G{?8_y`rU7wwUSOtlMfj>#kct&Zuuj(uR~ zb+E&7)o~aMNPj<19}n0u>X?f<<|G7XB?M_C z*?7d8@?-+`Rr9^wZUN;nAXDZgM6MQ3+A3Hb`LZ|5mLWU?kFi1Ht6UmFF|zL&*^>!S z?o?$Xjs0ze*hUBDI}TrXUILI}-}VI8=mc81M(nU$8l43L=ug7%^_?9|U2fw1tSLpL6<9b%D&w2R5 zOKp9YaDDzlE7yk|mP;S@2`A{oK0nO$VaL$tMd-6SA-F0bxPm0QNI)+ZCLShIqSYvg z?MB!fTIZ0cGLR{26Czi)b+$xd*^$qoRYGU3(F%n|RT$YiwMJFp3$L{`dWmav30k>E z?66!KT?+?tGAURxmN9FiPdpPdSQx-hQ2YJIxG7v5v*^BLFYX0&pB*kQT!=?@0z z(*uU{#*U%b_fYI8$u(Sn zMhKG&6DikG$8`F^A=e#1rkp4v*AKQ_&gmpM{&%(RWaK}n)fx$3_=K(2ajsS#TDe;6 zuv}`51q0N&3x=!3j-l2WsC7Cac!~rYCvbNQa}P|UV5c4P>zqTddx1>(t;`yJ&K4{z zJM#H;>c7sf`xyH?~L80km?(*kQR8n+gUf_7DtLj2%O=0}z zkSX!r$O~X)Td=U~$mdrDkl;?~|E}1xjJ>j2vFG3m$9rjKezBJox(uycF?Luk#a;pf zh*rXI#n>?vs}9Agkz8v9Xq_-G!$iteO;pM+hnG9#dIiXo%gV@gxhW0*25RR%vP%gS8D@WxmxV7Tx#tG1Jv3M!_{KPP%8+v>Ux8z-e7HSFqvfg4BnI^ zuj8hAUAy*hs+?o&rh08DAiJrajK|hZ^|5X@)$8-3_8|x_iXE1#sKa1DQTur_vMX|qWgXNTp={4^Ml z@Nu3n9jVN(WIEACz{YEXSa9<(XFm8PA*@mMilbBJ+5jFb0JkBlF(Kyr(zV-5b1xGQSM2 z$m!J6&OF>5DPlzUT6&9}dh}kYs zurC$jLwjT){p~`WL(uoX)p0AY!w+^|2RkfR9reM0^iz2Hc)*TP$57NU#2ZZa25+ZQ z*mqn-&ZZ%DDdBX-nB4x~YRTlaGypxXg&mfwmX=^Z2~Bwkc)*TP%P`cE;|*p}A+69J zSxAmuh;vM`{#zZxc^$36&g)=@<*K7Q7?6HPo<1J1W7Lt4I`X{1JH5eNDy4^j_7tWU zOyu=9PmBt`=Tqpo{`Lkkuq27!gtx% z+XAjpKeTd<*kQRe$^ZkTxfOV7NZ) z82U_xK9jt`iQeFNlBh^Pi-jqHiIiv(O0u4^PjyH%8pxC>-pDg)sx47icI0ztqR^RZ zG+v?67)CZ#t)Mq~Gu_n+Ghdv8{Oj%s! z99v@R6P6wM1bSMC%mi}3&Rh3<7BcoFYQ+}87hY^DwumdX7_D3}c33XOR)GPEJqN=T zW5-ZzITTw)a=joxtA$wu6Db$I1D8EJA%jecNqHywPIV~3$M2odzCA;6|Gz`c33XOJ^=$1 z+YZAOW5-Zz6BK)$+e00|ZY5-Bgm3-`w4V2+$e=o?E_U#Nqyy9BX$A-Qxz+4q}ST0p=1Otc~z;IRA zF;uw>s#Ny{tNDUeeZk7U;KjaRoX@%|b`vluSNKwXlES1gVX8ZXspb%-Djr+!1FY;L zVJ@~G#sQ(%h(Bj0b=n|w_=+fXM2oG?LmDr z*ZG3i_<~pYf>)9>y#auD;yHFI(%k7orN7g13+u^WcS6j&bd6 zE8(21J%tc_vUYb&&|8EOj)CpR3waX6ybyL+u0ocB0fj8!`QrgQMj=B{$PiyJ-50#w z7rfOM96+_K03foKA$Bd{bR=rsBD&pC%&m@M21FH;$%|PDW?l?CELSnFfdMtV$ZNm@ zc8p@~KrthH!C}5&jxU%+m4x9%p^i}*;izPoqmmrE5_ToIAkMa|s5Ei)AMjb_{<1Sw?-xtiIB0hjCvWUCvBAinzUs*$5R1L+vhHaqbHL$~S z)vyl?Nd04;Iv%iN)bIdmxX%~7#}^#u3yz^OK8H7QR^6vA;~u+=@Hoe$8WUAWDKF#; z5c5LVVYv$V9t_C;Yo0$IuwxW54TVhc1t~g}B zk*l@zO%nC+rEj9W^o z*kQQ}sab&+QWb_5!j4hMvnXVVFSy7TT;K~n;|o4TwOj>2$}(TdpU#0@VwV$Mgj}tG zT_Eb=1N)3Uuuq9{{-=Sx4)Mavq6Sv9*aQ0<*P|A|Tn~0wE`BvDC9L1vfdYb#TQ&hRonzu%EmI=l=XHY;a8BQHKglAC2UCfGX}N;k(Fx3 zlU*%5;?*d7XN{2IjZvd2TI^8`b1~Wi%*9}bln8!|4+s(6CuMpqQ*_M*yFaHi;)E|7lR#^ON>!qfCj^1 z__(oSh_MS|?DPdcA|>+C4v8G&w$qluIc^_CjoYU@)dCRkRM}y|_n^wJQyOhR1l$%U2oe7Ug(GcEAU5qTdKJ0lx58K6+cney-6(v~rEuVYxJ# z1qMj-2n-)ib_|Vg#X2qOV967fG~HKwlT;4VXxY z3_q((-21NJw@>H5fp&2ZqbVjv-e7a@Fw%Q~bdsf6(u@ZoPdY(BBGk5GGQwI#7)5 z3)n&xbSQQR$dr2i$SrTsRxB(#@-r|+$j&88^7C7E{63B!?PV9O!;Cnnmh1?8;d-`Y zb-85Up_NO<4$CFkuV8>=KfrLw*fAt)2FaTEgN^*bhNRaS0X-|sZ!nR1HF3&(CA=mGWw}o1+Ki~`BV9V8<%k?K(xm@h9TykBC@5F>$ zaWGsib_}^XL#~egV0(YCtv}eB6ss=KHH5hgCQ`AEsLGmQH#-!&9LSWe{>Z)e&9-7; z*^$q%_Cj_pSzCu>tre18!H92GOLirE;jXr1UASa5(aI%bhvkwi84Qr@Iv6e)JBDQa zAXy)Ou$MpBgY-%f(AvV(fr-?sk0_Nd^8+1vr2?5Upp0GvZM~c`Omc9!dO76kp^z)U zcn7NGstaFufGt;lE>}IYa=F-Hx#VgA2FTSAhRel{Ay*FM%JK(?`h!FK!E{pWMuEOb zn3gb+ie;fHYlaPXDAo$dlwoC7{o%G^VcC(-u%SYBF4+)=Wa$dYS~KF|YRTHb7anFy z7UGh%MJtz#9hOV79$==^W^?z7<5BNBW^L<<=sU& zw|5XBQkD%*NoE3CYwIaG&p#gLqi9*mt zbag$iRcf%KkQ>n(fNu~0HrEd5Yq z*a;@>g0lGvW%D$Y9Ycy2>M1)Gvf`-XOltmwc%iR?;EpIOgx5;WilrZl9J^e}vCEVk zyF@u&s>!#D$;h>O1}}lExJ)v5jbQLnoD~dGwIT*@fCeylB?`eH)xqGcU~pxvadWM) zqSm;9>ATTHuP}?7P?XcR(u`bmYPT!&-3+Anwn6mWF6mQKuB1bx+|3GOE0p6KH0<3% zHg4Cmw-U1AZIZqJ6YTvNX9asyt%$t`paJX^Q3&>^4)*Q=dw;DpRxxjDOx%NJ@eqn~ z-u{Ystgdaf!rQ|@dhe?(pGsRTc`KHFDAI0~Nj?#mu`bF-NWp47DUU){yibyHuOQ_y zoE4-{wIWhpfCiBAGzviq)j`TbAY~0R@}dcP$t+$*QO?L3C6gXi7+DLX_mM%2JSrJc zGpVGbjF4C8_mAocc@?taBa)DZ1tG8DtRRG{6%q0QG=Pw|Q3yh)4nm#-AzDH5c$XX>!-cT6%0Z8xbgBW>3 zGNNWlNk>_h{7AolLr=(0kQHB-guEsQ`59*gAylo1kk*X_AxEMRgisxXd;>zhsx`i- zH9o5~K4E6sAoZ@VH779rG=ce*46pb_DN|^T(`O})=tYBg-;DnhKanS~PnpBsUf+u7 zX26<=j;a+!*9Q$~?oJUD4ycakenxaZ)*9c}8sBkf{SYB+Gqed5+K)0cwdKCYX=~xi zck;OOBHSu-NrDt;c{D3J*Poh-Yy%v zd4{Vv+->&r)GottTv}o!+r=eMYTAWxW#1!h<|fw`!={Llsujg}2{b^_c_K6%P#rOD zgBVA+jji0q798NE5FvP_bwR3V&+mW+IJ`nQ zj038}^F84CZf;{&x3RO^*wJll&;H*DKzRf0CjBq&3PVQKZZV-om(KR` zw5Ex~LLzgqUyTTH73_%+sajEpk3a(=yH`Yp1F9p$y%1u9+wi#!kK1s&jgcJUqX3kL z*r0^yQ$qB}Sc+~L;z)T~6XK9893=vM0#-$!RIMn`wa|e0o)z)ofa(ae5rK|%8+*GA zgF}49guZGPuc0WvF^omPr_r;|X*J$v>{V!e6a6}nUcbA%dudkKDg98~D)%;N5E*R9 zV;)?+LCTuxt?kfPKW{=-^t*ZDxk+&J7S0Nes9F(6A3+1Cc@KrSOHdsg?GKLjbsLkI zppQ-5IaRw&;WkEK_U2|I{3+epOo83xQ!T7^s@>5#VqjGI|fmdLP*x2Jg-oM zzfoG{&AH1v!MvoXSo)#Jp@ih67?a1GL-@0HRo=XwqhXL0bCRR1;AkV96&z8uB969! z25_`F3c(T8!O>)Jbg0`nm_?ZEI+TBL0+h}nc zQ<GmPP~V?Qr8(W!_8op^?rplBHtlha!zyB{jtsv!fO- zcc#kooKj;*@iBVJ#zI!?kd)07l#Rn#K^avmqU-=@0A=G*2+F7q%KAWAkK5>W8?%|O zfC&wnMF>SXUp;0>BCF;qd_{ot4h-UJuH;M2s*(0RW;NI}W4(#3?a~tQljkB1qV@+tMS5E*ukLf2Uuy1Gd35{J;v4^erkc#`+c36CIRY*cJ#=nmhC-ee$k+KTO6;U0rKja z;?_8}_Ofu?AbJ-M`LYN`L{L<%C@9)O28zxUvEYE}2x=sP+QVb)<}r5Vh%SN%(V7uO zD55=NL~29sW(Gu26?ZiQQnpQ~6`n7FGT}K@EAo69G{9lrx`yiTd=xz2(__?o46nzi zW9Mnh8t?Fu^P)NSl+G9H;idJA;x)Y&%~5B1zxdRX|I2>eh6rl86%Cx}2SqeWZH{p=BDFcjm;s6A7;OfmG>2b!ey8O*RV(uRL1=)( zMd2_Gs1DB$fam*pjD0-DM2|6^oqq^Y?+CRy_LI&R_kovIb4)b77tJx=^!~p$M?eJi zFpP*CqiRJ#{T&(*%i|&z98euW#Sv80V}w0MkRy5?B1EfP9Z?yP+8kjsAkiE_Ga#io z62kKrpiFp9)rvfS8yev7TH!Dbs1DBy@I2=+G9Dwvp8o@)^6NS$Juhb9BHDufQ%p(M zhkk54bc5&vMJ(??y@-XX6~(d+8W6%iMF=>cI$}8tu^i$t4&p%8<9vA_hsZ$GCOGKV z#W7jL@d>nxIH+1t9RGm^xc`N49|u%N98(d;Q6A&>9^(iO<$H+AFYcpcD8=6^ZF0n~ zi{%d@mLH&A#6s1IV%Y?rp&|qq3UM=}I$~)@EUg}+g#+0X=gR|Wm4T>j((>!#m@eYj z4BAB;RIMnEouC16j1cbQfa-{2Hsa{?7{_>wnH&mjYEyoNcgj$T$0%(w^Vh}FC1TkH z>P0M6ttb``G$4fCMF=>cI%4TVEIl5hn*;IUe0d-}G7z;*x_@09{UQz@w2L^XT2UO0 z&;a-M67J)G>WJe6#4+Dv%<~v?Ig}<7>NgA8;--9DI^S#+u?%p5M^0Le2hw|zr@XgV zAXzAueki)Vd6I_WTpSPH=w$*aTi^k6Lno~!LRLJtl)^M6>$`W22is< z3UU2W9ULtNM~ghhLMA9?;^JnJKv7Q6A~UwdRcmUzXDI|Ff%Kj^h@i71L280L31pqnH?Y7Uij2!5{B@FO4zeRZZmln9Nntn z=xkDUx1J-~_NKT>a&(vA=vaRO&;Wj}Lm~K~I{0}C{5;_?9%Fu1nmF6tZ=OIrRsub%@FRA=d1g>Q{jB7tSo)zz zpvO#-i6H0kyS3IuY=85to-wig%`=j*rv+noAP&J8RV!lbK9h-6f+$c&buji47<+-~ zD(#W;Hxo-+;FPD+3rae@qR>UV}dQi>ei|^(-`iq{mQ*{GvM8dIxO1?J?eD!k#m6rJZtUFPw71-d6JKeTA?Wfb_mM zs1JW%5>_nzP~_K}zc#;KB<=6(8G8w`;(L;@cLifF0LL7uJw{GHNQ$a{`dU)7b#z_XX``Ait8j> z9}BkrjkAI+s#e6-H_!mKK1CteqB_|625f!hF}`5JzBO?h%;Gx~<%E5umL_zuRZ#Ao+7 zpgI`)8I1kNbZu;cHZhA$QIym5qmo}PuY7LV3`lR4w|uDy!x>I(9JJ`tu1j@utn91*s6yHkhBL1kzZ5?TRVF(sqQtl_Zr)Jjjg@b zq;6BgLdTj(JiY$JV5})|C0S*SU@ruXKgy6L@`#U0ulLzcoA zBD6G2iAJGnMWG!D4Ty;Lj1rkfb%fT0(8hUHp&V z&9Ib4@e9wVK$-BIsug)o+fKprX~JO~P#vD{2haEM8WX+7c=nujk}6N9eWd5biEt4u zBKp$t()FQZ!J!*O?=NEMgnAJRRV#{RE;Jy7ZV>_wsE$~|h$ZMX4&XqJ!};<+f-(@b z2@d#maYRHM^PpYCLDh=lI1L)${t3c;98eu`WDrNnYb3lzj6+!jQF%6{WGKai(k8KA z7fV*eayrzDSg2Z2EK8sPA)F&ZzyZ|}%Rz{x;5Bj_$Wojy52PRiQQIW<>*6?A#BnjS zi#VuSQ5@Gn1KhttxQ_#>BaYuAjw8IrWUp~3hjP6My}>MQL{WbKJ;H1iF>iRZa{pZc zr1vOqd1f9hStyo%C@!(dl7`};I37H2coQi*T7SQ#&9;h1$@}dT!O<-^D>$NRMI5by z22jIWa8Vr`O$SG9USk>)bhnB7t69)iT;&9{nX!rI^$vv~+FZ*!a}Yrtk{~rrN;*XE zIZeaQy`-x{&(D336=zC*W(a;(5B&6ajc%_on<;wI zgg#{!PopTOs0SfgkL+_5ik<<|JK!z9lIBW^ilrZl9O^cC797pia76oedFSdmdJeMU zfaIuOaP)Va6&z8uB97jI25__%h2V(l;OHc9bb{BI&jityT)_RqEZ#v;PS6QvY$AtF zQ3!e$Nbkvm2s%X)q~=gbhu~+vhM)IH*C~2_-iNGsvgBuh;OCz>EBK*mMf`jL4T$?= z6oMbBgP*g&&lz6hbmr$v6Ze%_(1u;*{G5S!tOPn&;pZD5z2^+N#?F=e6iYu833R$i zG7;o_pSR|Gz9sGF>KWSrS@9gn*x7=y?{HQyM%9WKs~#>G`w@x+V^jxYOTgHLOxG|I zw2@g1M^R4Kg-SYIqR{mlAiWn4qU#b#mzqu`9sfI986UNrZ_9u zqH0BKZ3hj=uPspswx|xat^r$Dd5tTWu*b_xLT{kNEwNjyLFCe|Q45DkLq)W}Ol8*m9zi5*;?@B#e24uxsBwIHNwnpQu zV2i31vDF0)V5=R4V2kQt>kF{;nb-KlYpnAcA9;-rnK{~`%KMeqySntq6sN^upGgLa zpOi9<9tGExXr$$CA9-oXEq&lo{1B%fr>Diwb(_g5Ple;G4Wj#CwfL2H@CMQ5nQ+M3 zAo@$eNML*C;l9B$PU0zln2*9h8=`4lK5p7y{%g|?-h*#Bj21Wb4Q^WV zjBMIXd=$ua01HN_S`j06Km!!rghDhe)xpTNU}S5b@mrsd@H^*6Iy3(@Si8%fOy&?{(Rusn?Xh0n1MpHPTI^y^p;@HJ! z?Bp|c;2<7^s62>WWDsh8?xc-jhaoZSCSrKVih-&X#qfd|!{fqr#6We#uqR@u_ZeQF zQRg#ieMSvO@*)7SUV#v>Ybl5E%sW;p*-!)^k5#mJC`HP6U~ z4GTUt1z7Mw)r$Do5gNe9Rwx7?R0khf@R9ZzNuLq-8Br#KwsHbjO2eil6KcaIO(I0Y z#+8PRnoKASn-hWT486;mMuEc- zn=>8l^S)MU+Z^2?kCYJ=4~M%}+a6|yB--{6*|rDC!-5&y|J2N*;a>6RA2D~gMDAVN5_8Iwp~b4McY0OIQN89hFu+h@%7 z8J!&0?}0>8m>DeM>eI*7qr}y%#4=ks?i>==ToKn4D=w;56j!eq*RfVyR7ZQAgt$)d z8S{O{JdUUjBJatAhDImIpo;V1rIp0<%%~`d>9L}!Y;$7UG4J4k(QzLMr*u2QukS1*JHxO%4W5C>F;tLMYjbA86yKI2UG_9BS97Y@3yoGTqJo~^Xo zng74E+a)kryl_annP+6XT_DJ~6ktIHRVyN6IW&NSD^Q4bqdLgA6l7fNGnOzD*Wo-U zQrhieNrT#MONO-DWy00#p+LAw)rwrb6B^*^O~OMQP#vyb4_BA_jAcIKYM*hX&$yg@ z{tE!!8wXu=%ca}JWlHN^EnBa6rP+Vb!{+5UZU3-YKHmE)>=kbu(sbq-*>pDuK8gSf zKB!s|AGBEzX!sin(R5S?AGd*zTYbh#pK-I#SixjG4k@@&h6T4uCe#L8DI2hOv(k~S zFqu$p5Vwm!o`7Nz2vsWzgtiqzAkPZ_aX@thQbZtk`;5DM#+@9+D<_f`OM4R zaFY5_+RXJnA4c+}Kga$CkluTJcu+G5m`pv-eUgA;>4)^|;#~>@cPdd^^PX>!vip1> zZRqNUw;?Ou>*LiA_Xv*ufwO`ms#e4i?F0mB{)s{~Hr2t=!{F#apYZ?_wBE#hViupG zC@1JaGd3}k{+L40=RkTN9YoM$k{~rhN;<@F;sFgmUy`oJ^!$7US@BWH&m)4LuW?rJ zL)D7-*|fBg01Ckm)xpo(;O9-B@w(4=)n}|_mNqldo14WJD9TxS6H!@d^sd6vmOy&n z@s&R}y(?KNmVPMG=yj87LDQ?sg|t>f*;b_ZT|H&Lg{=6Fr0gGpvJp5dD5Gjclcjk<$Qf)hAOh^Q-v=#kls%Q@%5?XOUVpX%xIKvw)j(zRaD<;7V+7gZ~wYd>fJT}>ziT~r5MKY*_P_>2uc z;~Ssx6*IQKi9WzA0w~HE`wybBGVEuCu^^D%pM2#Ha6e1NilrZl4BKGRE-3p(q3kOS zWg$}hv!1drWW}E(Wj_kaA~-83qiRKz9S9AeEQvx;Ms-lONqx-tO}(*Ey-{6nO_d#F zLJu~JLr|3S^_zN%5*_=R8t>-yvSU9KNbhF#<$P^kPhB%WpKqaNSV@PVYomHG=_qD0 zs-fGOX0!VE!$|Mu_1ZpuGGxWg>bZ~Kw4S0o9A^bxRIP}v>Cga0N1+gOQ5|&c1iE&p zH@2%cwy8HpFk`eW7|=7#q60-aV>=)!E5mkG7&{h7?=JP_Q+m5f#)_pMiVWM%q+L+9 zjY8Q74P~=P@veHxWM`qW4jqo9p+mjGSLug>qmc?nduTX1o0Qe- zIXVZjqEB+<6&#(5vw|b4R>aZe(15@%LLoS!Iyf2!j>gm*qw9@P%+VDl^h&e13Pm|b zV-$}33P)E1>20dVD-MMtzrs=Jhk~Qg3P+o5&nFOc4;db(bOta!Af>nK6jOE@d&qH0BSy$=mwiFQj98Af%`H5+tw)*Hvv8#C*T z>Geh%llD*Z2OpTlzfhEu)``HZB%7m<_92ko?)vfxv^kQrV(Et>$&N9Z7p%=xSevdK zw`mysHyN3uXYeD)irtdIF2Uf(I4c;WYDElw2Mu8GGZcbBs)NB3z~KCPV_v;6x8CSy z`u=00zc-5?P?Xa*-;7-3+yaHZAA$6qG>EAyMz~10}$IbwIr`H>&F>n8E-?7sXkCk?3E4+z)$IhxR zpW8cI@>VSUP^8^yCiz4h?`tGB8#`N1ir8%IEJ@0lf)w6tjH(rp;x_#@Lh9-FOZ9}%u4u(2l8}o8 zA+#Hs$P%hnM2H_6kR`M|njnPgAml0#az(xIC+4Kt#L<>xfKNbC&dC)@mMl{^nFyr! zn)>pY#AT9`V(Et>Oa7$El1ZdsnVyt=AS+%YNx52(vMzR?b38L-EfK8$(XXJV%OKw&eNdf7-sU9<~=FsUV8eZP4FjD$qS!$%|M>p$P z$Us)SNwTm)ut2+=2^OeY5eqY+0g+8bAy}X~Sa=95tf@EduQyiL8}~9D9guqOsW)T# z1I4sPiRu1QdeDpZ)g@x+b%$8`K+~@G%9EN+P{p*XxzFpvB0Ab_OhiZ3ilRFX8W0`r z2qvPVI-+|T(LGsjJYH`+%Aw7J2w|I{wNhwL%Fxt{`f)P|aeH`F9+zHcJR>|m9?FF0 zRISMK)1d*LpC}y00oCF8EAaf~dgH}<`|TitHb{chtSIRa*X-vSex4>>8}$4<16lD~$R@|t8=gx*TP-ySstl)^M6>;<_G(gdZ zC>FN$&=$0JzlZn&?)eq%tn3{5{SJDyjNk zs9bPc75;5CWt(A#ZBg~xeD!`i9*cnNxE)3lY4wN9qcQ9OfdS(Irw8$fNfto(YW~JZ8yOyzsG#uz~pg@7cM0WJ1D{t z5I*iJSs6!u0kES2pheA3`nMG;Og zg%7iES4EhB@M)hnNy2ML?QV*2!3yFX{{VW%=Y5+%es(x zDtbA+PSR$@z)UpQ*IOt*DD{WqP4yERst$+xiDqrmA;Zjr zJ-y#e-j~|paM8l9{on+(%dq`GO(yS})F7POS8c0r$*{Hl(O$Ku^3%apl#pN0eS*EMCr4xo&v?+#$F4riCVqHD6TGU^S z5TZRHI=HW=y=9j2tF0m0vKmhA!VuHk1a^SE<^3Ej=h$-E z!E(}GecVy~5v=|&2la0ax!&$|&USBOyMG4IrbTXn$fk?E2_jo6Zii4q#T_{9 zK*hc6(qHZEu5z+_pWg0jXS+|Z-A4hmq2ghPY^Zn;B3mk+giu4pQ#kEF#Y^nc^Y(V1 zbF%xg-tJmwyYH~ww*a)E;thzjRBT!8s(x2*_dRF3AFZ(X4#0a$wn*umLigfPD~Y19rJQ5ZPR%=!Towa-)OgvG(fsc2pl^_4_-h z-xo5Qz$V#Sp5SOX$(CadmLvA+LyqbXV)c0k^;yVl0!!Oj7DK1QS^c37>JN6*(ZV{8 zcF-{eG8-3!ClRkzF4#4^S79892zn`n|v#~e&YAhXHN5JW?~GH2QXY5j)_Zms%XOX|%bv{y&W@PrklA?F29b?t(;O}LvE?}qmb>iL&vI11fYqPipnkr+ z`gyEg&+A;4>v%nf&7bLDelcV=ye@*shS!B`S?}2?EFa>TtNL6B?XHqb+3BS~*(Jk8 zklA>40bAC4b{@-zc!sOwdNzNpgZXP9v*GM2h-^H&f-UPk`xDEDc;>3U0YW>@Zeyqa z43r&bw?Jm&*-dO&@7awkAL1D}E3)}j4(9&?nGI)mK&17IZus{=Xczbzw){5-%lFx< zhxbpij>jByJOY`G_Yc{tcU32ICDqOCYAToyl zLt55V{U(HioyYv|TR5#G+2Hx#kJ+UU0km=H1BkRu?sB~kk<+N;U6yNHUI(GZ<@Gr2 z;PN-@@|OVG`1QGy-EZ}FH#plJR%?y2t7>iS{>*mu7w3;G*YL3s^lJDRj?)f&?8Sc7 z18CEPUVE48AaZKLT9#{E9tEMsWdo-jT%N!#`vJ6R!bY~Mr*bUIHGWNmP~+DmoObXl z!G1*nw4pK#k&Vkih@7ZAfaMyOlMrfLPT{nJ%ZIYd2LWi~SAp&7sm!rl?S=T%Li`4lehw%UuB4_%(~|>Zv@IDwUGIDI=#J2-tWJN;Jx zZ5m+}MA~?0hjQxc1=GBIKF3tRrt!SeSy^=8NN zolZT8g!;|g);MlscUi8M1vVTqo4|%aWD}SRBKyF$Wy>QREN^A6ehWwSHLQL&2lcx` zW)s-X_Lg^K%Y*vr(nQ<#EZ4Q@DE6!YIHh|iqud9Xjb|Q+Y$$iLWxZ!3S+4V}i9H*u zvp!tReeP{<-LTj0s`f*u=^~qPTH#>uBiRA$(!Ta~Cpp;-=*gHS_79;Y3sIGkNN)ZXsFPIiyb+db0R?o77Z4xkMctq|Ez(E^dvjdd!^ zhvcNIx&uNDRmb4816BR(au0wues!~5{k1ZiRAk_FZ7pEQkI*t801wb1r7eHj= z@`(^RQTa!fYg}Fgp~mIYaoWM<3)$uK0JQPz9JZ^c@+_8X{JIE2jbBS}+QF|~Jl2hC zM^72BtQXxLG8>w=g=k1PLD9u+4Ux@zYfN0#vgJJ-EbnHoepg5J2CLuGL47@BHi3EV zE!R0(_Os=24wlE*s~_#CKEUetb5OqzWHy0Kw6{Fo(Q<+}a}Me= zkl6&5va>9PXp>p}Ar9&fa@6q$)^U`Bj^9IOZh~%RtNPhjyk$nN2i01V<59} zai*jCepcV(puXEt$BC?CzP%gs>{Pg1b0MLMOXt z>g}H8Z1)Pbdl`T>EpiD&HeKveh-|625<(3XSK+h+6*sa=*V)^>*2(S)z1^Ff?cT+9 z?*Pz-irXNvq2gAEY^hiUp@xdPaoT~32iT?6_IB@evb#oa_d#d7PqW=80JNdvF^IHO z(1gY_db`g$+kKhszTl*MtzP*n&dT3qJ3)Er-S->$ZP`h+FP!3wCrcg;~XrHu~$FZQT_g` zejf+*6Ctw+Y`mRiF?5Qs`k;gQ0~~c^Sx3r2M*=b%7h{g<4`%fR2lY8e9aC7x5%z9O zwo~D99SV_6Zo8_Ff>3h@IvS@PF2xz_Qk%WqX-;-$>g{$o+wEt&JpkIYNH;__m-%dn zY^fN4P(#IBoOYmM0lRd9z1{gvc2CyZJ;mAX*=+X=0Bxu^9U?6ibTd9jZ}(hhyGz;b zg-*&Z)+@inS@|+neieW=L0#cw_gcN(<<53*X1g~!DZfRpe5JGUFIo9#<-oH0)+dnJ z1iTI+Z7aH5A3@|aW%MD-m8qG8cs<~%{tCju32!Y~{)wIb9w;UM%bflWG8@mnWy|_W zqpw*$#53G+H}P5b`r$r%^TQysG4F!NiI`vP&AX~M#gFZX*^WKi+QGBmLT1yNTS8>x z^yUzmPU|??jV*|LA2J)x_JzpCvq@}O@7V;F5An=Z9f8n} zvm85}2Fi}JBxE+8#o4mnvnb1lcm~dnV)I8jm_Hmc8_o`c$i}lnAhKNoa1ew}T|$B7 zL)>;%9}S@$p~rAUGk~%qv>h@Vw_72yb-M*ZC%31ve2Cj%doKId2b`U6J&@V>)(w%Z zZ?oC9J`*}wuJdgH`*s3wcD~Jr%qA1&L8Nt?hBqfeXxCzk+45-)mQS@;4`wf59p^ge zI2$q>@6WVX@2b8KLObs-W6KviSYBeU9^T);I+i==SO%Gm_gCAgce$>F$SGqlXZet< za8=(3pm%Hq(-)XPiRedjn zgX6}U=KFA333Tua^hemG2kq@X;AHnvz1_#0?f!%9z6qcW6|X~N(-5yhY{ zw4ri4h-|3b1|lbyN3dMu@-7f+T;3I@9bERZ%WeQ|{2Ix2^;x+G%Qb%aAk_F(kJAo* zHL_o00JQOIG~3ntHHzgLznUP__~plG2fqsJR~A5Cx)c7?Orycz2V!t{8w4w4Ch-_S*36br{a5{ue zJh!o26HhmUnt0~mv_m{6ay;_^v~hYKM7B=Ph0w|AewJ&TJ_$mN(+hCg!Ra&E>C*wU zX@t`t(#AvM+_Us{&vv$Z5!*fAN%<1J@}}0B94`pPcMoqqn=v+3pIqd%ctL zoAkI%ESnL#A2OSOS3{(2MVISdh|I)O5{p(ViT51Ou;nKmEI)3q{!vHu zud@1=9n`-FnN48N+gpCl(ek@&`E3WwZ`!MW-BJC=to}pbY@GkVUiv7uQa{q>1`qJL+=T3IN)!W_RYdzXH6a%m%|)KD=TryZ!+ie1_q zK${C=Q;2LX3|IAU^>#-%+ue=r?gF4qR_p|kjY~T~Olp+O_U?YQL@hckQR{k81y2_i^p=x^=bh*R8L8y6%(Om+C&P zUE=wy_LsWPYZrRHsQu3UW$kNqU)A1S_jT>cx(&7Gx)-@u*InR#yKcFAP2CFjMRm8j z7u9|2zN>D%`|-Lj+@I7ftUIUfn!5kg-Bfp*=k~fc>Yk{3!1H|F*`Bp^?|A-EceCf+ zx)(j`>Mr$sQ}?Ln$GW2DWY5)}Gdvf2&h*^txxn+3=St6mo@+f1dzO1%_FU(=!*jRi zU!K2t{^@zb^NQz9&&Qs(Jnwnl_WawkU0Vd9`xd5Cjt+}}7(wfU_uCBSJW?9X(HOp(RueqUSMa?ZWD{F48 zxxMBuHFwqAU2{*(>YDp&9;jJU^H9yBHILOiUh`zlQ#H@jJX`bknip$cs##m}TFsj^ z|EPJV=DnKtYd)y?qUQCH?~VL?b}H%srxebpWIituXJDSzQ%p6d%631_l@oq?v?I8yKi;h?!Lpl%Kfx^t@~B?>+W~m z@4G*6f9U?m{jqz!`&0K9?(f_S>lUF!E~vYx?vlF8>MpOlvhHfM&+@tzXrYyLx7FQV zcW2#Qb$8dTu3J<0I9luJx@YVDUiW<6OLc4OUPJr6UH6Z=ckAA-`=AcFQn#+|le*9A zzOMVGZUfr*hq@o@eyKazv(U51vly*-rsr(Wxt{aUj!V#@mwNu>xdQEZwPzVxbU9k{ z2G0u5&7PH>TRpd-W&h$?h1M;i-B+W9A3(c5?0MAlI9mEC&oiFqJkNVxL=L>-dCl_% zTK+Ax`a5X*edEbk^mm1bJ>|C`=)eZ|r z;(GmUptWmO_vntc2m3d2{qhSkrYbPKy`^vTm@(%Mb1f*H8R+U9J*%y%8rP?JW^`Lm zdu!i7J5Hdd!LM8=(qY-Z(XAbwb<<~vbM(t$uG0uw_D^7Dbc%Ds@ZVvs`FoZDP!X7p z+2Zs@0y9L7iD^GhV1^6K@ViAt`H#@kJ5QX!{!Fm-!r_Wo910A23;MS){y)rhA-Prd zk9^pBEdJHVe`CjwnK*93n6YEV$#ZlxcFdUO=H{B3M*sNnmOdV?G_tXk!<6>;Z^9t#XpsAIzeoY8cf4xBTODj zoD=SJU~V3S3sj8=sJs*Irs369V+TdbxDxk-J9T1p)$5y3Ys!C&EAdZ~1&`p8bK{4|1qxA4kXzOs($JkiUXkrC2&V)d(WiW$fPNSo~{`^EwgH3 zIMZ8Gf82!ThAG*O)}F53uIYU>hjsM!w{+GV+}GdM(KThYv@wH*d;e z;VFl7b#?Ym$sUZuu}!1LO&r}gW^7~QlxZEarzE<1`wpMbEN(EZ<3_i2cGlM5?_E?G zbQ5gr=&UlP)4l7tPanR2$en8Noy@v1S$D3Mp4ORDf(K>k|Jj!A?vB|rMz>ZOZC$-p z#*rOW2L6OVmC@VQneA$8uQKv8@c%yif7-YzBbopvdq|ZLKN$a?S7pRH`ts9`iS^Hh z0`oZ1($|9HuK&k7tL606-oBQ;j`BOL;&<1yV_>Z9|IwK3ZQN+@>FMg}Y47gp>6_Hu zgQoAR+B&w|F4LM^lV+kh#vzHf-EF~x{Z-c^rRm>Jhi!>&Y^Ob|=)VhwV_bxCFY(_| z=DAJGa|`-Jxy|`IA&(|^%x>$N+gp?F=6_Bpg|4ut540esrnYv?p58HI^vtReuGgPCfBx%*)DN4teKV9M?-M?1v!AN{Z|y();cMq^Q}}f%rKUB@et3BQ6QZAgocdtmThINl^EMZ_D~ftn z`>fXPc~g6ZdmBx0KXmnV?!smJ?0M5+%Qwu~rlGDPrHHtPt^s0k_eG$(Rr47-F`h^y3ei+nK&Q?=zIC94-;D70nD{?3 zzA2l?=Htm!KG3RHeF8)MiBK{bi^fxd>D}$ewU*TWhSaVx)t<=M=3FG7OlRUrU^`~_ z_LaaJ6ZioWd=i8G(L^j5iKH_C_qO(E6faHi?89XkQO{9Z`TrSXQ`8P;aIC}ROCexnGT2JsZ1P{kF^>{MJ|!ZOeT^`r^9H)u~zG-$fXil zh$ga;Y#yYKwVFpoUM!LMTs#rXrO}RKt@cromq=tb9!$Y>}RMyjJN$69TqA}^Q7R5%uoCNe;d)3wnR z5}C|IbBTBX*2n4E=t_x92jjtTERqCL*G5-KWG0o!grbQQkh(UyS|SVaNIDtL(C3%NuP2|dR$tpabA zz;q}dkA`rK%(0SG1^%A|=JV-9E`cGn2n+BqqsiiSP7~E@07r3I22AL6QRHyD?e4>UnCI8kxHi`!N43VJyqac z3~VeQ=2$)o)7ox+l|<(A*=)QJL^RrN{%(oP#`2*ECGs3?H~&|O%w-GdAYB}DwB3AB zB2$q}CY6bz8MWQ~JrbErr-S$(GDF+V-^<8xNn~(3i<=Bz6)H*hNni?Nx>OGLtsY%g zu9mR{l)_)40$I1>9YGbXj@71m?5(P&|bjOph)rACSO8tdNc+anI_} zW#t+P%;j<6WN;ho(Pia>5{SWfHj>7jwMUng4@qD&7>kDE;bfpkmz57oU?>|dq_Uwv z?=;QW;}MBV6>txXMhk)7P7Ux;35-W_nS3%ygMJP0F$I{!z^sso20C=W$0aaH{dzo< z2=wZDswX5cg`f)wjK+I)Iq{?fqVr9qqp4V+SCT=@m5-1*n zvLQ5~E+?Lsz!)yVL@t&O^y+%57Z}(W%jNQ^cosZrd#V>DG8)as(upL9)b>;_No2f` zPhxnF*4Fk^FH0l_PmydaNX>1vjyfn?E0K{@2ID8na&1rbibRHk=@c#-kg4sdUX{p9 zG8zd*(cs$g=xY*)+e0B345G!gIq&%;LJuCGj|?9gn^# zk+DK58BXHyzE?XQeM=&v@nj^F!qaK5c0BsFM8=5zFci$C zGWl2rNb4F>k^hv)R3aKmhf~O7?Qrx1iA?5WxZCHbkFl;IRp-AXG6p0bE?`|d9Q{xt zqp*$#7DS{Sj(*I@aWV9np#-L0dMxAWeRLfI8}qSv7#!h-tG$HROJpINNM(b0y5m~i zs~XTJ5{cnUG!+TsmaDylx1MgzQ#HnL_sM5Mxj;*sHPfN$+(sfpk$66l%cX&|resv) zwh~z=#IwmDsq87;fK=di3~b8AV>EP&23p#CEuHEl+4d5eDnmN+hO6!Z}P|1*UcAbpDQ!P2p5JolM3H zfoaEf_mz~YT-Ob3Rd^(wqrGjZfT0N*rQ5{45g=j1i&Sc|(*3O=GDy9u(yW5_W^iLB6vRyhvo_Oa zXqX!#fr(rs6AGaZZkuHhp{CeaiHw8bR3U}grCuF!oJ1zG*%0PkGlBLlU5DAo$fk4_ zd|_M~Xzyv)UD-_%ibt+oJQ&Fb24-~)lwwjd+|SVQ;dBC{4)hn(JKJWp@nx$vS+hjv zXqF{|IXgmkv{+Y!iXPACrW_{Y($QEFZuD45sk$+Nq2r0KNF)~tOz-Wpabu!HN0Xr# z{v`xj@5UrXH{}ZHOfDWN1ZH;3))BW4LmM#;NF+j;RA6SOg;ZO3Ux~yElUOc-2d$X{ zx*mByiA<&PDGVL(mO`5g`zy$7A`%Nl!-3AW7ELA|z{sX-AsLIMvq?f)38pd|V5lDx zI4R7XMhL3y!h(!#4khClIH3C$SWB^b*@PrGnvbNwLB<4IH$@d3mf(CCiJs0SOt9|i zjWD<=5{suZnDHgB1y!SqGSr_+Cv(AEl!#~@XWhos4m!rzrbIlG&P58OwpG{f$0alt z#?3K;2Y5g&t*QqJhBjg_9*ab>L4s-;Ey+kfx@cSxktmR}xPet)QxcoRRBkXSUICY3k>x~Vu@HToTK*A-+T{bY%`iQlBKyg zfwg>4lkp%4j;9i-I8BlWu;qmcK3IaYv1~S+NXAUCm5wU-5C%7eGni>B;4Tc!7F3Py zP=@+bp-?iI$4nnVb^IQtU~`2?0XKNUawnp;#bm}dM-y;18WDPXx#3iQ4`;AHjwjv_ z=9YwF%VAaV5sYn)rt#z#Lf=nLu*a(6BN^P3#S{jbBu-!}IF*RsGqkag!weYBpa7~# z-zgFq4aN)c5aw`a@oQ(bcRq@dP1y{F;Fx(Nr0!BbT0$e46lVC*&sgtG8PWw86XN@JFT0f8r3w34Cg|a4vQgv zzN@RqRz^03gLtlq;^GBTM}M1yW+F)p0g{BY#z|`U?Tp03YB-s}l{>3P*U?R9U=yB^ zlLfdyNQ)*_=L`wOC6L8s9s!iKs?eDX^@j?na3+a03Iw&(s_b_#wlNyT6Bypk1FPfo z7>SH!vHBt$1*g4M>#Lj|E0M`;GL{U5(fa+?EkQ+gN@ONmh{f=x8ZUx$Sx6+q z@n9hvz&a#N?$2hVKNdsor!XPeee6uWs@3Sb6l^G#4My;24Q!v)7pmB9#x|w$u|hbD zOzG}y)3yH`hBg*rxnwAdQ~^}uY>z}ngNZoCsxcsS54OFGY>HswJ(a~BX^xy(P}{$c zq0K40`cEb?{X$Tl_EYuIQLmbl80p7zMKqs@VA8C8fSpyjT_CY|^A^Tcny9> zWFA9AsO`|HJ&mC>&lE}}a-g=?LaKZ%lE_3pokouUpsqVUoq^35$E8wP%$3_+H;WnT zPiAu2EKOb!SeFH7Ft#a!$GdPMj>&EPb#o>|8`EK|EW*SbUUcc4J&Tc8JBPI^c)bYZ zblt^xwuI*Jq6E*xf!?+bE49=M;T%RbhJ*1~5EHF|-gaHreJ&%L>2WoY!^~}OdtW=x z^r@Z9c?|X^!+1zY(-im2ma$e`Y6_e$vGGtYpO0V;jj+0my+C3^xM)KOn&t-98q%wJ zFO=9kUcw|YNzB{>Yt0d<*ozoDKAnk1DXlvG4 zMK6_TjACMi2v(T^JAJc~@=}S9VdR-lWRUVDyyd)#zl`zYGl@(P^Xmey+*?%V|HSC#P$VBo#xZvZ z?eZc~bL4Uc`(w#q7)yNwnC~uX`&=QhnOr6q4dT^y?@W0cP_b7sc6>5~OpWDnq0Ur0 zch%*q7~PzYFjHdHE>GqyRA#f?6T$u?5lW_22> z;_Ddf$3m`Xtbmyl0$ZJds`z@wj?YKqg;*5JHUyUAQ#rmtq6^6a9)Uxq8=X8xQ_(jv zx*1bKn4(J{FUSuoLe=RN3?3f~W(zsY)|bFmh^p$FB)X8zMw4i66U_ra6@9ZrV^%dA z!Mnc_+G-aSeG8+TbHPwJf=OF}X4R_ODn-N^lkf04yCeL!7JA{C^C_tVf}c4(9}zUp1*sej8((lks4x5J}>dDW1l(xpcb( zV+m{ykA&#O0M@qQ9Sj~%kIx}2PAq|SZFnc6u?iaRV`J2V%>o^o@#|k0+Z-)K5?E3} znt`>RBUGC2Vz57)&!p2a>Zbv=o{dy8Rx!3Y7EIw1#5{?>>J;D2V1FTqm!lX&5||&5 zRKfNe`73KFNv2t z^g16{?G<&u1jizHSAkV@CRpdi0}>p~Vda&Xas8dzD{74d$7sDvBt>}vuuk)X4EEC< zB7+r-1lC?r4>7hmpDCm;-zQksUr`S;*pG2yI$FSOs;5^wRDVQ5v8p{@NJNnJz*^mf znih{L*g_;i%g_PU4%Hu1ps5^|M`9&9VRdRBXKWMJMMaW9y8e4xEXLFk=o1WW&gDae zJl-S^Q&{|TejzXT7$OuhKWHO+u&(f(PUtnZY0+V8x@BjgQomShb=3iu}AIqb$ zd;}|>0oA@Xd5N*jiEt(oOyUVsU@gUJBfKoZ;b=aEc>&>V`*Bu(rh?Z>FuvfyivSuY zlNZ*YS_Qwt;3llL$>6&c|6nNI++gGyqdvM%|0d!c#x|$%s*#rLn^?;S zwaMO<-~#45@XihQHd3rhhW8{mmcTnSte!W)Rtu||-)C@BDwU2DFtbZw3#ul=KN;$e zU=lKgcL0R6x-qpQ{eYoOi9!y`HVTxF+G+iNF%*kNvcUp!}6+V>6bQpsSfCK22 zG{}ETWG0ouj0>$r)xLE7NFuSKEQr}^T)uOyhhnu)_?VGRSg@a?7lVYf%&SDLVah9~M*A`C0A`V209&o4D*lwAO?U}_ zt_fcm0IT!&Gln+Du@)#8&I+~C1vOzlXK+(4QAkDv56AUcE~q?w!O%vmMZ&^0tY7JC zpQCB8FB#dC3a29AArt89X|dWtRr(b}8^ehpS^_Ho@GYN4>DP>Gj%UL7e4>yFU^u9s z2>yn_e#}{8HULXX2|S^sSf%z`#x_OLm{JVmd9PnTp|wGQhVj&y#ap9({WR5g3~j`H zKa#^3DA3z~!4eW-UyES449&=76S{L4M2K)2)*fvA+$55?p zk>5xxUV6mhS&*!}Nl?>$V}_2${B0JCXvhb<2HAws&FOGH98bn`CR*q5rVREcg7^{+ zp9u&0F^_CvRW~+cY%>PNDJ;r|8^E?$U^O{6XK+&@5{@Kd6rX;`y#+&?F_VoiqA-m` zP`*M`y<0LEYlKqxBo7Py06wmCm8u=pRt#-M{$MIMN&YHntm^$OgR#UEU({s6xxH-7*zsw6cN_}gBLRWs=+tc6hSB~U`YJ5ZKpxxNU$$jzQ#y?2 z;y8t;zrSq9(B^a^9l_V@0?96@L~PI4CXDuIO$*XTe|y=1q5g237Dq-?fq|B3+N*g- z#x@l)alDVihX91twA)S$_2c7$92UQX3EE~oD5yEPGh>^Q_}~R=dg21BQM-!*MZcQC z7rz9x=2O(n*_EMwtTMm@2o^yNw6xA>FR4{M_?^Utl2NRoKnFos>xQUecVjH>8~C0k zh;MlYa4*n!yE{Xhqj)!scb%lRt!<|Dc3N$-Js9kdWihRaDN4fX2&<7$+>h~*1s?1O zYrRKS-5tqTJf{S6SuA`9mfx_bjMYjg7N5rRX^db7Xy)SI*ZvKER_Y+y3eZ6 zItj(sLa}(B)+Op+UwR}IU+olfK@6h@rtzm&s#dRrhA?X$jN&8zfmR+CsZgJUV!c>C zNMDK$$UIP?^%5G#v|1Q9A%a?Iph6oYG=c@EdE8+E?Xh3+Y#^tn_l7YY$nm$Z9H zXgnJYXR&^gpgIReNhlT);M-E-RW5;69WW#`mB%OL`52JAuvtZpW~4ux%tzv}1i3n^ z+X_p~ti2iA6sIrMu(%mm?Mlxv4E2YzSXWMSAp@-geOAw*svRq_c$1XGw1t3LLv9s1 zj-gFh^@Pdv1bPFg)m(~=4E5uw8Xt_~xtgHX)3U0zNn+EPAld=X>x8wgS{3V;SoFw= zLPjLlK%X_}RKl)uPSsO361CSn69PXbNVc+aaHKP z5*mty@NEr7(tzqNh5Z=nkB7riyeLE~OrOnaRkrq**ibqb%m(q~Ls(0%iakJL@yT&0 z7s4#S01f6f_l1DOM&k)At;!?8XcVo%1{vFw!95I5%ka08HwjT$2uUcG;DzF0yr2hE zH-{INP)u~CV-d^&0NSWY@rZ5fULz}~Rk%G-NgadM#Nxd<}Bp9ok zVtLHmKrL3GmlUhmIAfdQ*?2OHk75aIO+=_9BpBM94JE?`d?|_b>Mh63wk}CkZ<4`H zSlEJ%A@CVJfix!di)|YRxm$j}=4s2pykT6I7?RAhAjM zk{9ot=#vB;^gs#4?mrRS_sN4UUO}f`I|nfq3r#b42Z#6T19AbM>g~Z28p4!kCQD;Q zJk4pCJ%phcf+mAl){VrqdGI@wv6zqvVs{-Zh8mE|{ZtPQlTf@Pi^o$T^kB2wt#3_K z=wycaqj=AXI|=xjEgM(m;BbkJV4^&Vtv>|TYBCjjgv90(iF7VWgRj|=1r>WFW1Ese zEYiTM=fFT$k1iE|FQM^xA}+rC0aSODO<`y=p47vMNE97zH=g&bhET7vqZBY+KW0K{ zxBxH@LRIk548}BV6pKo*B1nKsEv&{iRbq2kk%Xs1K;`ADLjNG4A#BNjjVo|7>6VwI zifxfteCmwPV<~m#$j1Q{J59l2XQptJ#%s#rM-|)3*zuV8#N%`t&qQ?_D`}x&@ik>dfDQsqe?i4K|&{q4Y=ou1?D--+t z;1m9VIk=Yltt?W}GZ~GJG84r5J7Pq+^3~SvV6Y#{EAi1FJA`k*a~wM>D59$er2 zK&oo)V>Ffk{$^4VP5#aS|NHS2V#W)<_Y!*%}3@;CT{^h2wE76(!BeP*4RQuYjR9 zPTTGbV249~hEc)uB^WJ;&#fs-39K92{856V*%UU*!)8tbY+baf<`X11h2c9k;w!mf z4fj>>i4vSn=kaKQwR1wVb*E6lCrNND7>s6VFEIhO23ab2fdt3H5qxt&PX`pB^#!g9 zKAFLOJf))lkCPkv%jy)y;)5FK#YDHjYOj=28SF<-imoPuAsJoWnp@C9#*UBT8@>W9 zXa{yqk9PaQ(jBbu#;}~?)(2T{jJkg=@e1-&v@SYhf4!|A2JmsZ=&y-+1+C=egrv&cP z^j~L5a0s8-N3f;U_ajDquanX99S%_U5|4PW1BK5yu+rwnh0C+K^>!= z%TRx!fICou`f{b;S4lpPu}yJ&XrH1jY6z=Qd%lEbu~?-Lj1j~9`Go4h1q}7)!>Ldn z`vL-r4AP|Ag^XPfX;)=!SZGtPeO;=n@G{W6duXY9ir# z`>a*ADs-uYCh=HyHzJHm(WNg62-y? zBCOwfepjJaFti!(c|k9hzz~$LOEt%@WUwE*@#JZfC;_$-S53yNBo+^i$z&Sun@O>5 zw)SeqHbs-sXefqNas%>Jy6W#W5*o%wSD_F-H6G~WEhSXwG6}_MEbN_z&bp63IaiU_ zGSZLv@(>m?;A+6smv!Z+aV=+T6Og%J4Ak~O3cX%Ju^%ly zp~lOTf&SyIyPFEVK|;e3Oz&g5G%#>HZ>yz3Z*pj!TQ{4dM&y2%I%Nem&C?FqC)CC&1N+i~zW3NW68}HP{|9=u0 z3Kj6oo(|z_I%~|L>by-NG4L(ml^?zz((bx&yF_Ao1yl9-XuGG!8i1%e?_gvTrh~vK z8eh4l)F!=?p^ez$H&3sY1AV;gR8{&HiKHD9v63bQq_rqRMc&28CXD=3Q3}3w+H7m| zqncmE&_=8a$zTUkY`iheLaIvdmPmXH6-;0^qd<3;mHI03uZ(QMM%Fouq4CLIKYx&= znlCaG<_qx{ZKyh1tMnd5`tfaGJekcD0`ofBd408-c=s~4F_Fa^_#jpR&Yf<(B~V?x zPa?5|25!d8$eb2q=aJkE^Lg51~{f)`%2|03B@P3!6aTa2U=Tr zG^A>MnxTy;JQ!s$R1V0kGgMZeVdO+i$j0&J79W!KbPV7xCh%xa{pRLb#^cG8=FRZR zE*_ZH(=xkt=G2~cd?nB^V71-|`W9&Q2=Oh@bNstz3|13Z&>zFrF7vwkx=Ou_dQ<#6 zgR_Br3{NJs_P-5(xnNpLPftg?br0Es^cVj>_TDqPs-lYBwv1S}|)JCjhw zMhcKX5<(hy&$&i{bB-uY0*D-`R7Bux1`c^+mt*Rb2pO~gSMilis*?0GG+4(i;yBwDI+8`s+csw4}VW21V90oSBh3Go|#p z{&d_3l+TqR^;A8gv1H`L#`@Co#yT833j6P>2z@jl^bHNPKS~HtH9Kz1h{npMnzE9L zhPv>3Q($lAzAs0)QCSsIP>uCX4UL&`2sMJM?al8u>+c8FRn_7K9x!s=plB{IRp%|^ z%Q0n8bKpB~a9dx#t-nNW8k_xN)%Mz8yjhaN)Lj7uAQkPjN03H53&HpWRu}By8gOQSQ@foaezkeTbRdS%X4M%}+nppAM`Y zi(3!JAZCL8hF_Xe`b2*@1c!5QC=B=5OrJdMh}O1NT%YQX_eYYuvUVhHf|@aNPV9SA zSw7R>4_1dh%WH5m@SG#(PLIN3(dR4=`ZxhgK>%TXk6bn7LLr(;xkeCQhz%Hw>y@P#k>pq#}-HwAebG0 zmHW6FM-0c}(5^E7nQbPdzSbWPM1>J5{7_?w8?4%p%QyN<9F?oaJ$|@qY8Ip&erlro zt^Rc2=u$*d74XsXhO{N@@AQ{-BXE8a1%_(LJazUQJajYlc=%@Rhq@`3@`!RNJr3&m z|NniKwjZnMPS5Q2dG|wK=sDp1Q&#OVy6-Mubv?gls-b?unnHI%=>BdQwF% z>Uy{dmc;Zt1z6GxKjocLsT~6vL%=aPIXDdzl$ z5eLNq%`x`^=n4f|GXOtt0(4IW+FpTn*@?Oy>4Qc?PByrs23@HjJMD{~P1~eWyT=Ay z5QEIIN5QR9aG&mnpI^33rMC0o=tvB=6hNRc8ZQS`45-x#YC{@7%eG6UwpCDtv;a^y z#fCD;Q-fWgz}gq%=kx7NB>xA_JQjmAg|8sjD98^=@Y4&T%#qg%V{Y~#C+B0D2H=GX z@SZ{VsogOIEQo~hWgO5PQ-NNjKxYlXPiJU>Kc)|=#@w#AQh;NV3O5vB7b~!SHTXGp z4^wYC_ol7`OfZu>3h)vIcyBF!>iVZrJNZmyD4YU3#0Q*_H{fu+F)Zu5qo~cx? zK=dKp*chBSqJq3kK@J~}pGN_?a}08LA7xT`mR}CA%N5v63qM;yadMWpQy*BO31*I` z0IyJh|FiM)aSX6O01r0-O;ISoD;3~5hvDZwC|z#EVgL^Bs}M~}LP1@npdOozpWZ_? z6c|(77kC;_Ni?rka1C?t^BdrDmapJ?^z$u0k1t~|-Zctt;zInqevoPS?*p#438($& zp@6zpLCrV~KT8kRw$!5^b=|993O*(nDF$(!f*868KU*D=O6?IS3cQ3GXOKTm9(v6f z=z0ZKbvk~o23TmcYM`+ujL8f|)LI4g`eOW?IKs5NuQAwU6VQ~I0=z*1-m(Ng>q||* z4jAzylN&AOkad8(Q9+)u6hEJqnO^V@40(kQIXREO2EeUTa82jn=er8iU=?3B#NbR^ z7356{vdg*nxoM;csc^kF4yh$!1MX%8*K0X``j1Mbx++O9Z2-^{F#=6ztypu50()G6 z9R;wQH&cjyx~o#Kq&iOm)U67t;yV0X0+Y?D0-H~or& zqurom!CTf~HCVNJEi;aouAZoESCqnM7jB(O zE$ff}q&DK`-3%U)JKSf-e22Oo8V4$gL7lCj-c(S%;8Q}VF93CT0OdJzTJXHdjFzcW zQVTn@!(iY5Mq8!eZn+OX6O}J2q$3rQ?H-#*eKIsC!$ULlm(#JU6ZGQukcaVV)yHKI zqb zfFnNN1U|1(z}G&3pJf1Eu)ojeb~G*n!H*k?`w|;k>PL=lDISG z88YZ!zB{|1C{^mH@8(oj)HhTbU2N=FlsaCjrmEV8mgezjt#7IY_aa=fz~$R1K5R)7 z4hs!4fZdLrQjIl}TU+n|CaC@njKIH6se|+WR+QR7Jv-Ub&{$sGQdd9H=wvwtcz$v) zK((q$Y-y^iFxp3LRg}6eWJYCu>%3u8i-#D^eZYghSq0u)KDu%4yg~8i3%MxumOpee zkav$UAnVa|L&X0olmEK{rStt36ctRE-D&`JqE4yPd$zQww;26Zhto1^CKenHzDh0V z2HE-?Snz-Pq$nkPnwuLY)R{=FEhM=_>TsWTZG36NL}ScHpa`P^MNnE=n-uj! z7<5dFPfc~jpee%=dh{rsEB`xZRJi+jQj0rvzB9!bVjh%g1X#>f*z~jS^ zMPOf9%p4AdJ)ajf)-+X5Fe&JW#{Xs%hbpUT&4$_F`WqVYJl2f^(o^Gl5*zem(A_KW zFQpar201G*V6RYQ>ZIXZSg+|oRzPGeA-44mWidnHSm09&P=(D0N@hVMAqgs}ftx zPzHgHg22JmH^f}Yi7?tn1A$gHG?ld`ArFKwCuu6-ohwZ$M}m^hkzAC6AK!*PoQ^Ki z0r$&mYL7SAe?8bgK-+Ip*RFyMe;+cxsce*KYDWU_@Z78bJu+Bd4wANLlp7jrjJ9Wh z@b!^;`_9@Fci#@3QWy7ZnL2aQTo)|gCh(R;sqH5DR;%W^VQmn&3`Wr>AP{BP27POQ zX4X)Gp@tIl1}4Xc(@JSY`Ru6%+|QuADO5{%5;bYW#Q6fmxogOonsLpov!}JV(~j_r z9xjG*j?g_+D^C!!<9pFVvGzsPwa3Kl<;KEJsn-u3?aZmFXi-b3O9S02O5GC9RAunR z2^HHDv(-l5cFRVYJQ%1{B$RO@iWy524(D{x`ko;zz-lAf1lT8XZ8ezRjn*5`TBm6Q zmx_nPjQ45KSQ56won&gwS$iEC{}Zy`k2%aqbQZYxQ~=pfUz*o(Ddc@$TB(GJnZ~P0 z@b@TaIv7YjkaNPyp~P4_1g>ajtxm`IUcQaUX%&W86?Riqn-?{7MK4E1y$r0bg(EhE z{|SJ<&8b~wmFav05WHF=Ur{p1K)yfP)B6QP^HOF;6Z3h8rFld4m!) zy_m+e9&TW)A31>ElV=(DK9=Itd}sG)Inpv6j}NDo;OXJQ1wXWh`t?gK_z>Y<_XY1G zb~!OU^Q1JLoTgLKv>;8VrfFfCPD|6GG@YKN#c4VtO-s^rW}23!>8v!Jou+frv@A{M zrfGSa&P&tzXAWdu1bYYqbDr0KRa-JYg9(sXB9I6Do~9?#^kkZzO4HM6dL~WJ zrs=sfJ)fo*()41QUP{x;X?i71ucqm>G`*gtH`4TGnl`8Dtu(!zrgzfxZkpap)B9=q zAWa{p>7z7#oTg9G^l6$tOVj6R+LER(()4ATzDm>AX*%BF6C6I#;gcLb+2KCe7eJn9X`Y1B@UnI@KT4*a`hNU_U+(Y~4qxf;RSsY6@HGx!>+p3BU+?f*hi`EBMu*oq ze3QdBJA8}7w>rGu;SCPo=J4$f-{J6`4&UYQ-45U5@VyRibof4p?|1kChaYtKA%{0P z{IJ81IQ*!?k2(Cf!%sN;q{B}+{ItW*IQ*=`&pG_O!!J1eqQfsa{IbKZIQ*)^uQ~j> z!*4kJro)>Ze#_yv9e&5*cO8Du;rAW>z~K)a{>b5v9sb1OPaXcu;m;l3;=uns9J$Aa zq}dNg>ks~fHM+h|Eijs48Xre%m}For1ZkqzS>8VRnl!J8h?D-^#prbs0wfC!nZ&WSuzeKB}h74Wig zTvJuXB=-^U@exxqOs{wV*ysgaBK(><(2&oE=yP~D%h!#qjLGhH%uuIk7B)kl)C{0W zal!raaM4+vNlw-GW6U8zxQO@4ORMwd@>}8O#|B7MH`K>MlgEJ61HN<`5{vC27_(b2 zIbeAcD5F8m5-8%B+@u5^=y~BoW6VY$`aPBM}InhMt6g0gMY8S3b$&2(x z1Ks^{jEJvqt^*(L(wxWZX9foa7~fT^SW``PsTpJ|Yn-fYNkvfRDtQ!I`$s~nuP-+x zbNN=CQZGrB9P`t8p32T)l2^_U{}7z$F_Bz?J!qv~3nuzis4&;b8tHS#=Jaz-@+%YgNj}H0gaH;thd_M~`f*u8qg; zdjpHo9Es)4jb=7$chI=Kfdj~BBRV`6C^){%8%K_xJ=+l4`+)D_w;+>MQr$AHt`XPa z86PMnwwQABwMp~1418Rk!%pe2A%Ru^*94@)aa6cQzfXX9BJwyRkDoWljjdSLLJL3l z`&IK_Z1Ou7L!KL2L{+otIE%olZ#1s(3?nBR$h-)+84;^g3>+J93s`haC?$VkpUAs? z1$_I2$^^YnIQli{d*`S%FXOigtzSeV=O=QGfKh!N4(%_gi{oprDbSBwatf5Mh;*RCb^ORBOLB1tRFJ1%w$rmYqtW_3X%=q2wwhp+Vchpnne=n`%mxIqSA#&~~an zWKDBztEo|cfY`$W|Iw7Gi?0*k0;MlSlp^ntFoY`5k&0rE@nD5%CC6dJl@SvMLU;)g zbV1)g>Dd@Dkut|*KI~{ndARQ~$JMFD7!vx(l>0eq0^a`(*D6ibrpKHO(cj_Is!}@U zEWRJuHz+_jk$}1x*nS>~q;!HAMzsLw&YU>wv097!gEZLCs3*oa2cO5Rc&X3bIVI(F z4aMfNXnRaOzkH?t_o#Q34Kj0w7WtIWg55{F3n8+?g9SH4)BRj1Ye`qH4*Jd48sKeQhuisYhsx&Ub-aTEfY#xv{3U z!ED?N-kz^*F&+oa#n2B&vc?>R^_kJ_a2WqyQEPF`z^}xJ4{MWZEHl?B*C+*w*c;D_ zegLaEA&^+Y!T$oFzeCP7HN>Wrc~saRg&Sdc+T@wjr_Y>`D;rT;%7ul9%oZGi9M_Y5 zRfzU|XtjRW*J@C7B*vfNkKfqP7+3o(K%iZSb#hU0GQfsM!9(NmNtL)A96rRy-Otn+ zM5V7<3bhjL$+8x?I&3IUxCin!{K11 z9Cz?@(LOJ8>B{V~w{f@TzAg+wed z8mxLM=wQ6sA4$6LQVj58sGCg{RY6X_#r*MtAf)HL%wDQcT&J z=#QZx2Z#ED4IeXzxEoD(hS(s(k_c_nP>0^>=Ia zhy`f-Thm@YYqF`B^FaJ%q3YFF0NKi9(q{+gUOFepQst&~-&;eB*XnT_DogPaP(u@9 z5B+PJs**{uAm9-IE(p7=tVTSP*z5Z*U>D}R zL|glhf5MJiL(=`VZX&Vq4HW-rP56XSRR&czf$n#63ZRTp?`5@s;#nH5c|7*2V>uud zbNvux!pg_hHZ+>k-c-OoAH*9zFU{Ft6yO$wCez&LmdrJs(tlwWuSWD@PBe6*8V>Uv ze>|MGz#9ifQzM2uGJ----FAfc5g2uG6gefG^|sK-pF=L94Xd2^vV9r^@uBuE4fRNj zXoqhzdBLh?KNcEy!c;^$;jqsc%8ejpG{PY3hxz*ZPo#FrTcueHKKFiQwX^=|=%p z6E@W+k}yx8Z9>!~-pDDPV4(UE`W&tMtg1KXwM_sV8BIWqEp_7>8iVD%#^^yXXQrW> z(0fCx>(P2})OSNwy{VaZqwjli0zoxdBAhFRK(-D(fE!5$qe~&`FZ_Z1sbW+eT&A8Y zR2p(a;Ov;d&@<_t3+rT9v%4{h7e~ zZasKjkR&m{Q0?LT-H&q9pZCHHaY)bBsmD8N&wn?6YUmxX0Siu(gR8-UBZHU+h7!wt zegq?$8Y1a$ohRxJJ_e4i*`8SaeSr4wLL;khXu%~T@GFMWco@1zs2JrXzG4`yXF==* zT5|ch@Dl;OoA$%WcK7V- zU#M|JvQXn9SV5!qg{8GkCZnH+$leW{XyAIa`Zu9tCs1&e8;WVt`%v&#BG(%)h#U*B zv$VIbfJf2JzAFg1C7^L+19tNCP79>Y8G)+^xWLcp%Dfk1D?Ax*gCTh00!0k+9&5;#;mUF>n)Fm*fVn z$9lso5jq+pPd8OGKJe$z(A~mjK*r|zOVD<Vazuo&BIHP`5U$4AhpQ> z!Q)HI8j`N#UC{eppeHE2Q@d+s_s#GP&xLx1Jb7iSA-|C@$(yxWC*4_p^m|24BT5kQ zXqDIv0(?Bz>&S`bBz`cueahFsIVIH<noCGUXPwH_BC!iE(10VW?RT^7cE*pJ08=>-673~1}L{5IHa!*_JA>i@qoZO2|x$g+MzZ9r=gNk(HWmQ#hlh=oG z#bO9Nj2lQ_7(sF9(W=!>P<;REMp(j%&^F70z2{hET4%Jc(})EV0KAG;N|gc}7U&HU z39%i^4WMaAWVs5lLwjCIHZ^+P~dNaZC65xG% zq(2R&zV8d&=@MlhCN`S(xfsmYH|M8f;nlV1a81~usxFJ;vo$*XF6Z#owj0LO{{Ce! zYF(~bRgFUFbn`MaziTqWP`W1YVXmI+>SA-gF1M z8%Xo28I7YOf00Ryya`&-piLV4FNt{aIbim8h*?vj9)BK?I!n*SF*jd`ZifX1fLfKd zrsECD?M4GP;oYL7+y0_`r_}bDAfe)O|GbF%UEBC8vR;9iqSV*m+ZjOdizvX0S@sdo z_zsaytIBEvY5}xjwc$<@Zmt{r$;2Qat2PTdl;OUnl?kznp-Y8mdp+zDE@|>(CWT zTLY{lhjLj%wSmoc!1uz)TCgn`)4U$w$$A4H>|&XYV+A_S2E1%2Gd1N6!0j93Wt%lF z*MgV-=(w$%lj!Sb|R%1^~okrAZ{S;Ks$qgNgD&EJ)l|Hf9I&3SC^e}*X zMY1T4@6WD)4Aw>bXhg|beA3$;JXsa#fQn=j@k3XPy;x%%)EsD}RetoO&}EfQR9WAc zoA?dWPrE?zabU-cB~ONsj*O5RX^QV72);U^HLfs^BPe)59q6c4(E`#t3oeSxYhgsZ z+Mdo!;{OR2?4NTB<<(|Xwlh%Kq75Xz>O36CtTdUEu)8i`PUl?Y8qbBD4$jIzU&htf z=bdJ{0j}gZKUGmSag3p6>NL{VIgedgg*igI?ETRAjdo$R;~H@{SZM?1868ilvMvt! zXU>}^;P2n%v^P&y9<2itzeQu}-!LDvXLyMFJ z_{Od_`eM~iA5!7CObWNxwK(%}JRE1?3;lEScOzPU0ZC?vC&$K6x>|ZCqj~SpFx1?g zV8+!jj2#0f3GbX&>Uut8|46QL+(&0dmDi&0Un1!b%J+QJu}C{KWLf>V`dD$=D`3dr zfFWUWGBF$80`=c1P+5PQQQO5z@OfrP5z6G^l|)~FoLGUx76#cYKV%boR&R2x0r;-8*k~)K=cYIgjmtH~L_0WxA z^!wV1{oG_5wmt!>T^0HoOvUvhTjGJ-Bfzg&$1Q%TU2IBx5%?AADKQy6o&+2QgwR;p z)Wr%&t^#OLZn9A&vl{tR!MEGA#U+-X`+(?2b4*n#1gp_3y$&chg?gX@>KMK+0QNTR zdd3ela#(`_*D-RtZB=QXh7ayB#;q<@r$6+#7o+*P2xpZlHiOTR827-)a|NgH<}2UZ zM#bBm5XtYMOq;4>2TYCuKRfyk0af_8);oFY!D%p$0nsR^U28+&SD|-`xQ^2zCX&a4 z>#s!MZB+k`g=5<%=hrcTGTz z{}+(w209dO)W$NgMVJ!S25OG_z}PCYANri8<%N9^wGpDlH4go57r8Oa?{Rr8gVnFn zu;Hm14LcvOH%6ikj%3EPY&S^zy3lb~l%W7x^Pvx%)V`qu!%3=^*rEw-XNOQ_svbZ? zwL{A*(M*ALhbgqN5ZX5(F0p)~10*H{rm0Gib!RU@Op7!_{lsSs`M+V8r$mFnw#=FR zcOY_Lxox%gq`}-j&<6?&nCV-Y#bK(e&%WHAm z1#yfD%tD>>sy8uy2qy7(U`?^O{9th5xj_6XS(>*oI}*zCO3pDO`zCN(0W6pw=o{?ijfc0wEF6!DeVJF@62&H&jF;t;h!S;sQJ^7 z&e7n++>pDfAkyU0cd+agS|{=rO`Rdw142I@ZZ5>Sz5|r@3wVKD>DGAt;YE;LmtfrR z2wDtwF^1-72FWAn1c=EA+!eOaW*g+Z4^j^Z-8JfaWA$)%fK9Iko~YVCpQ4q&8ZB=G z>JaA0b<;Qub%f?SVl^c0HRCG)cb5;Rjwi$%lmJ|7L|;tzz5!|526_n+L)5c6515ejuIPE6NSRH; zyawIAVj!F!5|0Ja&*vuPx^ajQ6~XF5cU%m-PSednj$b#b8pV6Gm-4S*(Sj|8ets58&p)IPo6Qe{*gJ*V ztLiorY+3|19j%o+uG^oYty|zng3XZFeNjtbq;Kd%Ls>nZAE?B3BSN^UW-Lv0x}gJ5 z|4q|{YnBXVzJ<2)L)2C2L_A{X1k_stHTREQn^OD+YJNi0rVbyP6ZkJ^yfq*S&tk;v zbuXyRpqy-x3pdc&0VMqvav4WK5>?JK!RKY6IphA5*h;Ab4Elo{k&V@+iKvKwdN{8k z!pmE7d=5J2Mzr7zxk=}DAZ1hls}2F>?Lt2U*rWBpDk3xJsl~uM1TIY_Y-X9xemSVw zpfw8XdUMph(b!!pOKIkk=wHJi!Re9pXl+hi{PlwI^B`EPU zav7S3g{-JnYmk_K+W=0SmE(k}u`vZO1HAY#a8kHhAQnm=1;}6h33XIWLu2ev)eK}Y zcM@1VWoE4c_GH{aNDCaH`O8TDs>!8OJV>xnhrG}o*=&-+I)M+ zk}4EX8qC}m?3fcc?8JHJZ_(Yw(Rw7jq`?5(7TCBxEBxGvxgPldTsl6qkLaGLM4tF( z$oHm5zL+qLj`x7KK23`^e=rFQm5qqqymcN1o)UyYD2z?uVnLRgtUFTMy79u^5f?dKSzx?ht_$$0O+F04s^C%U?3a%xfKU>WjpUIk=GX|6Q5$f9c8`I>Dh69XiROlN~z6 zp#=_|>d-=mPIG9HL#I2m*r78VTH?@|4lQ-)EQii^=p2WZIdrZ=%N;t;q4OPD;m}Hl zRynlVp$i;Zarl>Cjyc-R;ml4&Cd}Mu+Zm=zfPDaOgpY z9&%`tLk~Ojh(nJ$^przSJM@f0&pPy+L(e<(fU zwArDz9D3WKcN}`xq4ykm-=Pm2`p}_|9QxRyPaOKxq0b!p+@UQFedX}i4u9kDx9ZBA z9YTw1D#H|>DDGGeyOWU%Dr+NUcmrI}oqCojjpgRnpsjxhoPTNOEZTqf2~stY_2y)I3_86uFzAuv>dl48_K3Xh4cB{d zL`u-zApw6>wSFw+au0a3B^TT#&Pg4vriC1$@!;}YbbG6wko*&ViAuM<;Lv9J98j0@ z#5~Uz0Pb(h8i}Cca)@+bw7Q6&9J>kbZgMao)T1;!ZwdM?Tz+5eWqq^^KYAfhx-}A5 zu-&2q{k;&CHAX#GB6FOWOrA&2KZm?RQF%@CD3zYm;M2gYSG0?6z%orwVyY9Y##+dGPP>KjmI3SJrfxf+BPXu+thu;jY@L-oPtNZ9DOZ(E>xx3*raLJf2zcyMEY4#HA1@Y@X}qyj%v-%yd2l#8pFUfzR~m$ zK6o;arCQ4-SJxvT&~3so)n(A}qK~sN?s}8jyzTx0pmwj|i(2r?)RimYY5GKrC_ZM$ zptiSV)_@~>ggqd~8M`FvGIa5Iq}L-xkYw^yU3U1Zb6 zZ5Irj4B`BxZ8W|;F&87R^n1n;yxFaW^>%^8I|dBJf^L>M`<@1VX0-NU(vGbq4oVdk zhwfe_|4jn7!%^JQdCxU#}Dr%5oU?X=b;`LGPVey@A= zFQ+mIeFYt_3u&o{9nst!l$3@BfZd!%Q>GgM^`s6(>am>Hp~x6Ctq)^^%Eoc#`g8#N z#fv#qRE?`a;%xvtG31S^G)v4ezhbuhU!W=KM(^0-^;lS2Sr9b9GECmw2i_dzYl*5c ztv#ZAnqh9AKpNlW;*`p&fkvbvfzHo4AvaXUE7hifJHLcv`cDhAv9UZI^j@3O1+_nI zrWI8Jwq3~JAeXE|JylThOsL#yOF5BPEr)Ku>36JV&+__1>l()y6X*g!_X$imS!bnI z8)xTGQgf@BQkse8YxXN|Xem`EPf8)4?~%OH_f!qcK_VSy$WGl%G&*v`>Pq=|B6t)0 z@Dm|9cwE5rYlnc8tkwxgFIJ#50+h_n4LV*`^%%pdDSeZc5q3}W4tMPjFT=KFLgk{FyE|2!Ox3+!OuII!zu?_S8uX-5mJ1IsEq>kz8avGM`eny zhDHiQGu=Wp^l*=`sRoHRLklkhit9q=lvTvS&fUSBA2fZ+2o1QYfIBjpq)XbYZ1@NY zc$a3b@3v!mKk5>L^`XgCs{>y#s~P~$u_;FmjP1PA8$$qXNgHBD7hi>-hxy>6f!Ya{{>t-F>FD zt9htlyXsid%Q+fj7vqfqi67^{1~+2wLvPcZ1wcDTfVz;+Am9*;I6abO#2Zb<=jiy} zs1*+cB!kHkkTN4`SJ0+Jw*Yu>*r?`yQ|)g-TXE*LRZHTn{L9+uOeyu`t7mQu<(&-F7i+Jc zNS^$ILEqANtFlX9LE6B)9++RIg=#v}9WcNa9dI_3z-8))^C-04sM{(A78`A9VScbC zScT)JTki*wx6iHQOs{q>Q2A23f&9xiCP7KQ3s*ya!LD|u9y*;Aby_m%-)MaY1B{Ns zYv17}>P$BQ^_z8Ekf){nu~PoJ8V^Rbw6;1elP5#PK8u2o3;ccq8EL$_1Fz|kkp{Q4 zB@E+phqH_Krwy`|Xj{Aou1-yZqE=%xCw<&`)U@ z)|(efDtGl@!0GrqMngf+MlIX;e0M3@z70K@e?P~_iDt~@f|j2{=^=GI(Qro70C|If zXrjh#S0MVh9yDxp_b0D2Deiw+q{S6HNl3J}h>Y%{-NWe;W zO#BC6W_VE#qVle7P5_k{V?;QM)mJ7%jC+A;hY*9ra$7BDW|@95k>&Xk!W^na(p(-Z zpYMf!e+@l$@^;V}kV^N+BL3y3{xc!(Z$suHRH!%P=A!E%Vb?hR6I+wtiWzZMG*JL9 zmM!@bjW37FIj%W>KWPjI+RD_HSWaXiwBgG@8&Jh!uB9fyC2Urwr|QEe?(`|D>m$!F zQ9J3<*!i=Up+iqcD}jcj>6Zba`vS<|P+fd^HwcpLt*3^n+U8O`qHfF%DG0E0IB;h$)uFD!em57l*P}m!-9F72iKV?%Q0%+)x%j#o~h5mxs+T%7L>C3HC(W zcA-ilg_?IVV;Lk|7e*f_Z!;jDhUydsEhSCKv$H3maZxyA{2i~q5kFk5olD+E;?7XE zl~HqEsZbZRHsD zLnwE32?{2UczM*Wkl#MR2kLB`xj?%H!*vV!9^Qc&o3odo{RGWIy!;VMNgoCto~dnkIlA7A`-0V_`pIi;Qk zON3f~AeOl<*RNl5XLNifI{r(meDr9fHvbPG!k(d0w{g?dd4PT`Sdqu7$!h?%G(;Cp zTZ^p#xDE>pFg(7Oa3~ufSJD=W2_w;dJlg*WRjMhv?L>D!ANI63a!28jG2QqN#$Fp( zg}P%w`J$L&^n)*36Sb?t@Wl4Z)@W~uCJnU#obWrFVXxmrij`kM??4W3hTT_GOvvlL z4&4`pxF@c2I~AC}5pX$qS-(2qv|AMBwtY>*CHUl^2rnGxiL2>dDuy*AqVO_9;d{aG zdc(d^qoM7)2YS9=s}?e4hF+;MpB;5u6i{fr`U{{vw49SWBWGdI*}=3BT%@6e_%$T_ zMW|Q^7jPuR(5@rEr;kGx*H)N*&*H+NnbhQ&b7#!Kqr9zC=S-dF3`;HMLjQX8%aI^| z$xo2~nd>^fIWk8nPc$#%Fj#Dhw;#~GDB`eRXPS4Ke;Y{upTNPYS_K2?`C!ynVK|OB z#dLDYx6akJsgmrblbZ+@eig7#8A9H2dNTC!HZ6f>JRxF;XBE1BDzX$@TbIa$mx9eV zMH5qgS zhCE9=WUG#y&-I&XVpUt;r3!oPl((PUdhD#(c%s>DnWguX`(RJ`)xN1z;rsd9&!|^d zU+Zs2;oH~nE#jv@TX9_35bbN=;_H#!#%5Jj2ER)HV!Fo*0MO{GU^DLXNd_3tV@iC$ z?=D&EuL@|N)~egaf$TD<@6u3xt7_wEQ1t@+AAYx$)uuJIqSNWZ+72h6!()OD zaTi?tVcV~u>j#EZAo*!(^qnB#yh!xw@TtMAj%ce0V{5#eme@Cc0Pb;fWG3;&r@HF% zkDNA`3{}r2J)mvCmyUKpSD@`OouH{GHZwHpZqXj03J2@M#5{BsbofJU^6?7dLqY$v z&@d4aC#zgO1HXR_jVIb?Z6k9y12)hc^rB*cxiMb7h(6Z)GD8(XtcXCB(0>+r1-~RH z!N|ja`B~uyYV$GgO8!E8uu};Nn1&4U@9LYV9z*#UnyxoZU&uL*WYS|aG*_aq1UucmIO4+0L}oVpW_zYyqVf ze1ezW3cD`Oba^;Kk7nqx3_YHqmol_;GMzt}c5$emL%TY(w?q3nw4VcZJ{eM`;+=S4 zFaqM-J+c6GeNWp<-AfT)?5Cyf-x{N3-W{ylBV=s2MVH7JUxqK%YG~+;diGtzs|`Xc zkat}T4r`fl%WJTZXQK(bAsNe6p!M(wd6m&N*!LDNzC_1?c@gM#SV9e{L0qpA)iY-y ztREbO_4~B-XY3UC4oKBCU`<|CVQz6Q1O@NwpfIWO6X5es)tLylWPYm|)BJ(fJ2Ztz zBjruB`+>?~q4xPlJrWV`2I${Lpa1?-N#?R|AY}hfD0?`mSfD%~l3yIQRpO!gL>&AN zdfg#1m!!2U2f+_%q+@$#!+`CTQMWiJo9MO|Mtx6nvatlk5A~(xjdi8vV~ssyb=3w3 z6RXN%Rg{`KaRLnI!e|5p_z4fw10y_cxR1OK4hCiQ(d<ZD3?gZ3@> zmy5!_gNoDq+|D-W{tP`KsY_z?hEPWoXY`r?rE}(~^H)P7joUu&Z>SO1^BoSjV)E7I zvK3@{tL}e1l9Iar60mKdFSBIY_fNDu6Y@;$OebQwa*%zQ52#{L!-~|w#s5XT%IC+i znCv%eTpEfI2xw$14EbuPBYrYDu@I|2=ii@vc^CAY z8~RoiWwjb46~QU*9xC>~%s`i7l*csxYyNZYUA-OKB2;Cux62F0Fox<^)0oT@@9j(>hSC1TA+FE?O-tA)7<1z z8Cwiy!GXgxdCiI1rBaA|w*Y^2LBPNg(_38v%$9}3`C&(5I_Ut~#)iJGrfy`$j2a(< zr`s_=xjrbPNod6R0RB91qYzqN=+FZA6LM&)hlmWbI1Ff~gK!n6HB6kZhm!6RwjlkM zm)yPp?H}c4r?4_j+uLK{bhk+5)MkvKOH07!9is^-+^A_I2s|Hi(KTA06(!~+x_hGg zUqfy1Gi31%!5LuqKLJC7>Oyn)`RModAbzY(T&uq?y1hSu3wWK#Ck+N@X($Xo{hCn0 zjgZ9v&6KjSby!nqmZ;5-A48nO^B{0TIi1OK>`c3gDFiw*HaqJU9Jt zyTX;brPTeNGiIii6ksyKEV2kO{pL?L;pyYVa0tie|kBj*e~P<%77ACfQ!(>jDRWX;j+Bf)V36Is+$|cxzSzBt>ID3 z?mL0NeyIhYBI517U{XOUwX;~TfqDztMNl6>eFgOsw5y=q1nn+p4?+C}?I~z4K?4Ns zEodJ>`wH4mP+E`>Bn1@%sB1q~52RM0R%`wJQ_=m0?n3OY#8!GaDEG(u3R zpfW+_f+_@!6f{cEXhD^NssxP@G*(cxpc+B7g2oA|6Et2>y`Tm`je?p4H4B;`XriD) z1!V+Tf^0!qL5B%y5p=kqBLqznG+EFTL5?6-kSFL!K~n`CCFp2D(*#WyG(*r#L9+xM zBWSjuRzY(F%@s6H(6NH%3p!5F@q$hebfTb>1f4AC6hR9FohoRdpwk2`5_Gzt#e&Wd zv_#OEf|d$8OVHVZ&Jnas(7A$^3p!8G`GQsmS}ACipw)sd5VS_ng@P^;bg`gI1YIiV zGC`LMxM zM$of@o)h%Epce$aDCi|YFAI7_(5r%86ZE>EHw3*YXtSWV1idZj9YOC3dQZ^%f<6%R zp`echeJtn`L7xixOwi|owg~z{(3gU~67;p8Zv=fS=sQ8*3;IFOkAi*@^s}H}1pO-L zH$ndq^t+({3i?CPpMw4p^tYh@3HnD+N)kz8Nd=M$CAE{(UQ!1XZA#ioQb$RhBz2b5 zMN(Hu-6VCFw6&xjlD3hwt)%TFZ7*pDNj)X)D5;mEoh0onskfwEB=wQhS5iMoyGq(k z((aP>kknt&o|5*GG(ghclJ=3bucZAXr6mbTQc|&`5=jFk4U#li(hx~QB@L6bzog-k z4v=)9q=O_KEa?zQBP5kdDw9+$sY237Nuwl4U%q?bi1TGB;6_LE=hMwx<}Hzk~T`ZPtyI89+32)q=zJJlJu~oM+*IkZ}0LBF86eKN0)oKypzj2 zyWHF5U0m+ta$lGGxxA~(ySco(%X_%o-{n1B-pl0yF7NH~J}&R;@_sI-T^24&my2C4 zae1K2gIpf$@(`DYx;)I~{aqgJ@&PU%=<-1>AMElWE{|}z)a5dl%U!N;d8EsuTpsOm zrOQ<=k8ydd%hfK|xLoVV)v&$1)p6K$SE@xb}T((`#x_p?+ zEiNDK@)0gia(S}LQ(Sgjc3t*dKGNl>E+6Ic(JoJOdAiFpT%PIjESHaQdA7@~F3)j! zuFLaWKGx;=E+6Oe@h+d>@`)~=E|>3i`5u?=b$O%9_qlw(%MZBxpvw=ryvgNy^~!Q~fSe#zyRU4F&oS6zP1<=0()!{s+!-t6*QF2C*aJ1)QL@_R17 z@A3yOf9Uc@E`RLuCoX^L@@Fo8?(!Cwzi|0Wm%noPYnQ)q`CFI2bNPFhe{lInmw$5k zXP19*`B#^JbNN3m|L*dCUH-%6KVAOI<-cA2pUeNaobs4FW{(RzF7&va$L&4t;Bk@1 zTY22k<4zuT_PC43T|MsRad(fm_PB?~+jzXK$J=?ly~jIv+|%P7J?`c4P9E>WwF7~*@e4NL}dwhb&CwhF6$0vJyipL8)KGoxe9-rp%B9Bk^c(KQ4c)Y~pGd*7F@mU_9 z?eRGtFZ1|ZkC%IVp2z2Vyu#y^9FzQW@x zJ-*80t3AHP<7+*>&g1JnUhDA<9^dHkI*)Ji_-2o9@%UDc*L%FdKj86$9zW#qCa6lv)seQ^VN@qnbf8^@ko2`MPDg4YZx6W! zf%?*LajjBgi8#IhtG=Tj=97=7{l(Od(MmRFF@C8aw})td8KY_)a+0f_dTXZR`q7d z+VO)h_U0g0qqeSNXClU9>`QWshhj5bqwYXFE9|*!lv(Inh#n6JF;?%?mf%5lV~KSK zFupC604@qL(+K;3`|H9rT~Ilc$cOHZL*J8Bb&OgLV*T(Z7D)KlDK#Shk65p1HED>a zrH=#d86WrNrUVMFB4hA|Cb>Zs2I{oep#ZDT@!Ef@+2FN$6XByAXzaPLDFB_A14S;} z06c&Sf9&GfV-MtK{h4_d$T)PHMm_zc~gcYAya&0PWkpfC#w z&_ptEF|6l+XvrAeAKOM{&K+1brlN(Re?z!w4##12TNx@yO`WL#4+HyE{&KUfx+=cE zudcN{B?R&xMm3G(cfcJQ3N*2)^$G-<4b4_v8foUx-+-o`n3IZ1J2e?{X~B@aLT>oi zhsAPzE5M7&D0%enHTMsLrKOr>{$9Fa3>(3yFAbeB*XPrqGglebkSFV%kmERA>-hKz zKfkL@|44v$jT{HANlGLJ&H&5a4w}P9^I}%o0K|R`)C|WilWuYbfUgR@EDlQLr9*ZC zZ@$!S2W(I7GE4&JuZ{FD|H{o>z_h2L{u`27Sc=}a(_-_BjG$hc@ZUlB!XWjNc=hN{ z2y{@OCXHp)gA6&`3@y1QvMSuR7vD)M2DxYCTz~9PPzqZXvm;ek`|ODv$=6W!6&f~p zVn?UbIsj;npw^2^sNbh6j*Y% z?mIZHY0jrA#q&snzS`$Bn05fLza}Qcn1S>L+G`@vcoJ@FKpvp6Rtl8B`VL^dcMj|L z$scuPL1nISREfUYb-nR#-?IK~Q9X0jfLK`XHlR;N? zKsF{RUwLD6KaNRiyBf9mc*MND>!5{|;ci=Nb;k=~>4n&Q-7j-Lx`O)c_oW9xMd`zgTBkOHh-u&`q)bz*wKrKtt!rqj|} zFG_E44-dMDYDC#4+^%VvEV#&dx{(|=uyq72%Ab4+4u#afB zuPEG4a9Xqzf~DYM!6kwRilRZH<6zNYh~S}uhY8+a@NmHg2tH8oL4pq!e26F-p^}3; zm#O3+SBR}fs^lP#76p}ps|1e`JXUbE;2OcTg2xH26FgpUy(nrBMUA4UNfb4U!U>}N zMA6|;QJ4`0mgs7W_F2J)32qU5xZop1r%9qw!ULyER!Ak|7B?`_K1?Px@WrEKYh08_Zd4kUuMJq(%O2MlH zuNHiPC|V=t!_$k3p3w}oM zvx1)!{Jh{71ivWwCBZKXenk|%Dhgi{{JP*b1ivYGv*5P`zb%U15k>EcqW476`+`3Z z{Gs5F1b-~}6TzPf{!A2pF4}Jq9lj8SUy6dSM3=8c`)>q)EBHIX-wXahbo@~i{3Hr~ z7F~Z4oqrV^B?tMxg8vZwrzrSK@ZX}~f1<-bq97%UNHR+e`?ku^Baxcj{N#0pp z$?XTr?T5&sp|brjS+u`wKU@|bAPWzae2^?USQZ{4_Z=aNN@Y=*EGn0U6_Q8F&Z8uc zmK`c(VU;W#BYCXkYT3C)cCM9`J7#73!(>5=YAk%hBmQL8MRBMaur_VZ->V`b5N+5I@#{&-n%g6w;uEILWHKUo%>BD*h; z1*giwg_2K`yhs+FF554bozIYkOJw1hvT&&^JWKM~vhW;PxJ-6GR~9Un-OrPS=SyB8 zyRVc5t0b?Me1YUOk}s57T_k&6EDJ7?-7l3zmr1@{cE3UvT`7lLCHJ^mZhwv3{#wb` z$-?U;ua%u|kOeo&_UmN(nX3vZEyx5~oxvi%0x{x;d}cG=EP4z`OY2Mh0$?e3Qa z56FUlOAfvy7ku6ERax|!4QRwd8N)w%^Jr-^o$m%LNnY2PuA( z-G7qX{wzEHA`kgh(r>cE;tYK5Wf{6WLsw+z$_!nXq3biWHbXaL=%x(aoS|DXbZdsz zXJ|u)Zp+Z^8M-4w8#8oYhVIYM0~vZSLl0$WQ-)B}^oUW`^lXNn%g_rMdeJX&dO1U{ zWa!lly_TWZGxSD=-ptVE484`1w=?ukhThH42O0V>Lmy@6;|zV0p-(gPS%yB((3T8+ zk)ba$^i_tw&d@g*`Zhz~W$611{g9y_GxSr2e$LP@8TvItzh&q@8Tvg#|IN@J8TvCr ze`Sa*DzK=~qIMRwx2S_fMHX#kQAdk9S=8C0E*5pQsGCLIE!x_m9u{q5(Y6+CXVLZ+ z?O;()i*~fAmqj~Sw6jIME$U-YUyJ%#w3|h{TeOEo{Vm$lqP;8{VA0+d?PJlt7VT$I z+9F|*w5Zsk5{m{}G{~aC77ejzxJ3t8bf85CS#+>PhgdYiqEd^>EGoBXq(!4F8f{Uf zMO7A!v1qJC)fUxQ)M!zYMa>pXuxO%18HM5r&+YfqSGxp*P`VXooCVc7Ok*o zrA4bOT5Zt<7Ok=9LW?f4=wgd5vFK8ZF0<%zi>|QfN{gz7Ts^r0~S4K(L)w(vgl!p9SfbTHtlRv zZ<}_psgF&4ZR%&!t~Tvv)9yCyVN-vb_Oxj)n+Djlw@v%nw4Y6Bn}ki$red2)Y#MCS z5SxbDG|Z;`Z5nRV0X7|I(?K>JY||k&jj*ZIrV5)z+BC|h(Kc1uRAti`n`&%ou&L3e zCYzdVnqbpJn+~-pW0Pf*ZBy2!!)$7?X^KsbO|DIzO;c?;%BG`jnr72DwBZ93Ve1vZ^((?Xk0vuTk{r`xpHrZa3> zV$+#6Ew$+^o6ffB9GjNebgoUyZ931U^KDvT(@L9G*|gfG3v60r(}gx&WYfhqU1HOv zHeF`Z*ZPPtA-D}fEo9?seew!Y!=|P(wvT2h|58L#JO^@32m`#t{^n^`M z+Vqr7Puuj2P0!l&oK4T$^ny(<+Vql5FWdBrO|RPYnoY0U^oC7u+O*lGw`_Xbrgv<5 z*QWPudf%oGZ2Hiqk8JwbrcZ48)TYmD`rM{1Hhp2!mo|N6)7LhAW7D@beP`46HvM4J zk2d{e)6X{jV$-iS{btjDZ2H}%|JwA2O@G?-mrZ}$^go;au_=`$$`WU(AWMZ=YL}(< zS?Z9bqAYEdrH)zZl%>vD>XN0dS?ZRh?pfM8OFgo*O_sLJ(so(eK1(}fsb`jU%u=r` z?UbdRv(!6FyJV?PmilI?UzT>w(r#JWJxhCJsehLC%+g+28jz*Ev$Ri^_RZ3MSxRR~ zWJzYJI7=m28knU)SsI+BAz2!lrD0jxKTE^2bU>C4%+f(wIyg&*WNAc}O0!g!rSdFQ zWNBoUMrCPqmMXJUm8CIR8k?o+EY)PGHcR8ORF|dkS*p)c!~e(FcgI&zd~fFo5ew?q z-ax5}4Gp1)ib5I?O+v^`Leagudv`AZ>4auSu?vC)Q9!|pDE8j4R}>T!8!9T;5$p~1 zeP(xdc4lw*eO^BNmANx}`Z;sv%oz)H7V0fDSQuJG zA!EU_;9JOA7;d4_!Uzi^Eu3ayl!eh2##k6@VVs5W7A9DjXral%Bny)*OtCQ4!ZZt~ zTR6kQnHJ8naJGeWESzg$x`p#BoNr-vL&%*l_KCtkig^w((v+%KnPb_?DVZDXVEPQU^3kw@8Y_#yJh2Jdv zZs89Le_Hs(KU^tG`gkHJ&hh|^i1QJGNiG zzG)PvQI(^!$l$~0D`u{w=4X{=3SeHx#q zu`!LW()c!w@6-4rjla{_n#O-=PrciXtf#=SP~vvI$T2W&iO;~^Ul+jzvr zqc$G1@wkmAY&>b>DH~7QSZ?DP8_(K!&c^dLUa;|^jhAe^Y~vLhuiALc#_Kj#*m%Rn zn>JS2c-zKm8*6O5W8+;LYi+z|<9!<+*!alCIvXF`_{7GiHrCtt+{PC+HrUu`<4YS~ z+4$PVH#WYt@tuwDZEUjfgN@BLw%GX5#!ohWw(*ONUv2zm<98c>*!a`NUpD@>vDL;u zHvYBopN%{RaFFkyg@XbI+c{|IV0#BUIM~s_P7Yc**xA7@4t90$KL@)x*xkV%4)%1g zmxH|>?Bifx2m3kL-@yS6T03at;6MilIcV#korCrcIymU)pp%1x9US7Ivx7q&9OmF~ z2S+$K(m@voM>#m!L7{`L4vHLfbI{#E4+lLR9OIyugJT^W=iqn;y&at3;6w*~9Q1Wi z?4ZO!se>{HtoZ{eA2bP1h1KWY)z;%#u;5qOeWE~85(CA=mAH@u)x7W2RAsl z(ZM1IiyhqL;ARK6IJnipZ4PdCu*AU~4wgE&)4^R1mN~fF!95P{b#R}9`yD*s;6Vou zIe6H?BMu&Q@R)ZQo_FwqgBKmVlQRt$piy{}@Ty%HQ!$nUQ$GGU_;#e2Q zxj5cMZx<)HIMGEP7kyn6yC`u{>Y~g=xr=@-`nwq5qQb>VE>3n)>7vR-wTpo+YFrF* zQR^b*qRvIViv|~iT?}zC)Wt9tr?@!Ph2G1=*SMJL;#wE; zTwLekdKdFuEO4>V#SJcQbg{_AViz~LxY@-mE^c*kn~U3BEOBv%i={5^ba9u9WiIY^ zagU38UEJs5eisk8c+kZ|E*^IAh>J&EJm%tY7f-l&(#2CQo_4X^#WOCRb@7~w=Uu$u z;zbuPxp>*dD=uDj@tTX*U952NhKn~{taP!;#ak}kcCp&U8W-=lc-O^R7w@@v-^B+m zK6LSsi*+tOcCpFD4=y&l*y7?x7eBf9*~Kp|es%Gii{D-R;o?shf4TVE#a0*pxcJw_ ze=hPeD9B*D3|eNeQwFUv*g1n;GT1eP|7EaS2D@jlM+SRluvZ3qXRuEO`)06T2K#4l zKnATdXp_N#861>B+YH)e&_06>8Fb9xkPJF!aCinsWN=gly)rmHgWehR$)H~b{WBPl zK}7~9WpHu^l^IlJP@TcR3~DkMltFC7ustPIi_WHRtF@G}^Z z!N?3w%V10fV>6hL!Nd$EXK-!?=Vve@gNrhlmBE}0uFT+?4CZEVT?RL2aBBujGFY0y zvJCFY;E4>L&R}^4&t>p@1}|l>DudM-tjS<)1|MgzK7-FP*pR`-48G3brwo3{;P(vv z%wTH<|B`whT6x&n!>%6w=V3PwyL;Hf!=4`Y^02pueLU>zVLuQ1dpN*DYY%Na9LO7l z9@=_n=b^oa4jwvs=;YyG4~KZ@?BP%khj}>M!x0{i^w7n_Q67%=Q0SqnhawN%J@oW& zjE7zxj`Psl!wDWv^w7scUk}9|N<5T$DDzP6p`VBT9tL=*@NklclRZ>=sPa(lVW5W^ z4}(0^dPsSw^HA@h!NXt=Lp%)iFwDa#9!~XOc}RP(Jvbg*4;c@h2j4^1!*CCc9!7dN z&BG`UqdkoAFxJC3592*d@G#LslZQzjCVQCTVXB8|9?tM^riZgUO!sh}hx0wm@Nj{L z3q4%q;bIS$c(~LP7cMXNFw?^<4_A1Y?cvJc3g*=wuJJI}!?hmfdAQEQ^&aMXSm0ry zhZ{WH=wXqE#U5_*aI=S7JlyKxHV?OZSmNOh4@*7V>ESL9%RJoe;T{k7dbrQS{T?3h z@UVwRJUr^*F%OS>c*4Vz9-i{>w1?#$p7HRkhvz&z@8JaxFM4>%!^<9C@$jmL*F3!L zVTFe`JiO^)rH8jXyzODNhczDF@$jyPwI1I0@PUU9J$&S0orjM-eB$9#59>XA=HYV> zUwGKyVWWqyJbdlp8xP-l_|C)k9yWQ{>|u+CA3gl!;b#xOc=*-B?;if}@TZ5rJpAop ztA~F)|m%i(&PTnE z1|Nfc4Dm74$1oq3kF*clhvUQbk@4aA@O@-`4ENFKV}y^9K2Gy7%ExFQV|Dea!Q5osa8%%=fXt$3h=B z__)!>A|H!=+~nhCAGi3p)yHi*vBJ29`*5vH;o~VEPy1Nz;~5{%`gqRA^FChi@uH8He7x-A6(6tqc-_Ye zA8+`0)5l65t9-oeW3`VpKHl;1zK;)leCXpNAM1R4?Bf$3pZZwu<1-(h``F;)OCMkP z_}a%eKECzwosaK*Z1VAgkIg=|`1sMsPdeTo%V?(L0M1vgn&daTX<6lx9($MZYX6vN$P=le4JIqB@I#S=3}PD2v)GQd!hz zF*u7MSq#l$SQe*bacUM;7U?YPESxOdEHYVmS@>CGvlyO5V-_Q_7@5UsS&YhJbQWW> zn3zRV7L&4=oW&Gz#r$Gb9}-?6Rh2fP3+mC~UEb2Fnh_%>YQ-UUu*73eRiwcp9iv;) zZ=893ScEW0yKQUKQS8BDglEF4NO8|oU%VHm?;`6Pn!8*kE*VcyQ1dpU-kGb8gB@bX zf_B6TrR{hJbjp6gH7t8lULODR*Z-(GDYoWmz9?i0>!r4fuQlssGUt#Ir^;d%7XFz} z(!R@*iIJ*|quP9_;&Ya9Y!}tCl;_+8J%_^!Re_D!A$xCrbVO97(#*Bs&q&+{!=;0V za*eC`M-rKVib4&QWh~@S6cR6Qjfe+>u5fDbWDaIRGO!860KM+yBSLhjgqEFOj5pVB zVmVkvI8Af{)TceqX*=sxIn9(CUdW1^9|B1c4^bJC(n$7Q8RE$3~JiL94x8{M27E0<G1|Hd|j&BySH%#?mTQ6RTz0l3*uEN#@Ml`k)s$ z^*l*3{$Qe6!uc1A?5+$8^Y|XLq3b(Qly?qS4hm0=)*lyg)jwlC@lB&(vSQRa(yC*m zCUwc;y@gylPsuC0_Gm2rf-?&vnQW-m@PHU`a}jAjuBkv@Ni6kf*!z@E8VKB zHXdWzlMuJpn35>8pU-9cNsTY7HD57!hAMAGDqpnC&fRONJ+}mOtSxUaq^S+9&@GCP z6AX0Q5U$sQS)#!WwN^2%l(W8+dJ(?WWmbXO)VLX%aO>*2m7+aZiDL5kQZ91>lNy#k{=HaVf z20cd-yaNIeN!67mOL?y**)EF=QB|U|bqlhxO2HnyU#_WNAwln~RFlmx^s5UyiFGAV zvJFz=B6|yh^{%W&4DNa)WUQKYqpx0iozwK~aSFpH3cOUE-gV$P0yj7Yj-I=kFUBdd zA4l*ehXPz5yl$`L=m+9_gmk^EwyiDGWb9Ugyl12pEXqzmJd;|nkNT!)k3u7$KKUmh z`dNdvRvTN(v3`ovX1|Y0AKoAnp*( zPM_P3%Z?3g{J;hyAo+?TGi7WbE+Cn@z8zsbUyahiCN9AIP5Id+V$T0jqkIubd78pG z>{hAdNO*)3BMyq!tDs4{ZI2%3xufMz5^g1` z4M9n}CgoKmcpJ$Q>Z(#X(Jb*wRhKLpVHx&oCmMp!6*Z{l!OQiE9xss|>CpPJ2cy}2 z^F3NnKN2jyc%*&wWAf_vILhl*r1$R_&%psvfI#WcCq73#sEndr^WoH&NZ;3#ccQ&f zD3%b#n}U&AJ_o7|h;H+zgt&{oMmhTW4)t|y$nEf=$F{B+45Z8qRaBx6t6;kzMWo&& z(l^T3CJk4H6t0vaC7Q$NQR7RLry=^f+N#HM)ky*AWtZV(i-}F7|8pTh*!Q?ekI;k# zZWB5Pc2`dFd@do{JDA9xaJkps#G6O$l_G63#+Xl<43cbQl%bLRbu#gU@asXN+?-xi zj}U-crT>bYz9E$dQkM^nWxcqxKO2uJdbc8WUkA3OtVE9`#HQB%e+YL;kM_NRom zo;O8wC7DRsT4M;pwpzkf66;5$WLH)sZBQXad!JBUc;hJNp}5&Q6wK?CH`QyJG;WmY zWHN_aqYvp@XyB!k^bfqBL6FNSDEmdaCLVonW~+B4KfYWMt+sZEMzWhovJ*nE!`p+2 zEz=_;_?yaqr1T(JT%$o~SlIoQazAk8d?A*PISj{Cz(_t8JKei?n%nr0TC?hNu-;Bs|id|$Q9mg>ZW0E7ggxW zU}REJ(B4nswiDNTRO&SM-A$u>(AG{EM6$+_g2fnPWKr^^l+9g|3|0rG)9HfT|7R z5?O*BqsZ>=%5YVR7l0F?#@#es_sg#bkKZcD59gQPh*_y`%?6T{%cb6lSUcyA?=j>| z8=Z>HXLRNg_|XCINhi3G+`B$zEkB~ijc0N6eg)c~B5lJYUicgpvOU$HUzy!Nu6K(i zX;`)HN|q7cwJ{G8Z%qs&B|1rgsS5fJDxLbQj;!N6##ku@B7Pl-#)*t!qnl9MBY7(9WKP>>&J4SPr@ zm;1hrcz|Pp6dYk@bUU*bKbwu96`oZC_7jf%5UOoSs?yg+#O3?fBJPQOY(k|=$h~s8 zDy^5k=yEPPP?0X!2~r-F;}ZQ1i`B4bT&E3o;^2Xy-W2m`3>}YasW}VPJmC(hS8COB zIdPSAWFiS_2HOKjy{;iPWMxiMx;rVyjzpGQ)8u8h4>RG}y| zK-e8cAJIzgH%Xu1ITUT)I8tY8Bz)`-sSQo0M|n3C5Qetwl%G)IYKqC}>XYWv7pL-* zi{&T9<;jEu?a#0N85@u@*a|_hU)x_2w!Vb$ zBqZc261S&p+>F zDm6O@R+83e3u!b%{h+>bKyvfCl|L9Av7o9f=Xv^#WWvs|3d_f66`eN|^0hIKgqJa_ z!$2x8e^@-s4I*VteRgM#J|ZQRRyfC!9!*KT zNYT22L2R*jyjQu59r^JWm2VU&X#?sLs9zUE=0`l4Vdh2t;p(4BqKag>2;>Y!8AhA< zr(_v-4oOX!NUq(f+(6Dv@{auaFlmZJ<8Wi?H6-X-CAxG!i7e_s3h$-Cc=W1?lHdIN z{JdXf=k?5J-pfFhZ^?{^{=bFZABf^&4BdvF}c_`SKlCVBzwDDf}P;z;aB140C zOTAw2d^4DI*eMEIc&?{6Hl0C}IW1T>GzdA}M}H)=Go=WIE>G#7JJEE6pt%XHF`327MC9-=Lg;-;lws@^3w`8(coA- z`l?V{Ow|60jXnn!o3i2GaxP4@;x=s)+aFQGH`NZvh>0m31lkW9! zLe@GKT;`z+Q~NI=`&da&%IIO{aO|?kQRrb#3wn_EluOSElxz6O14C;_pPYPm<62Ih z5XO2UpjX!QTYhbQIE%@LGQe1u;DFF z;lh_kB1Oq4(en}oWc#17<|cQ@6RDV$ntmn6Um_tcRBM}WQvXYktK?YX>4BFy_p zyq>KLZF^E_rX+nuwNVGM9ltgvGC_%`{!1#(aLJN}I;M^^`g}@;92p9JX-V}kZR9qh zf4>UNbbUCSV7#Sb3?9TK^r3=l7D|yWsU!l5RZA(*^ChdqbE*=qTCPSP$dB-LLH znG)_569g#c_ywVP5ei^9wSV~erf{sRpC&!u^Y5zzYbFYPPO2ADpvrv2wsu{lZlVlI zn^;d#?k;^SgAn5c?rxHDb~KNO8VRW#IPrDe@R(cLQtE1bNJXZjjIHZR!nz`Koe}Ys z7L;+UZA?D{_v=WP+aqx5nmg%lOPJ~ub9jKKXA+Jf6`W|g3{%v1KOnes)Xds`nCmt&@-}72aVLMxw#@yzJzirnl@2jDFmdoa5Ymz%@auWlF z;wWI)u#FK$9|3h6m};G%@pA+X%-!;XQJ&DS>xYo3yM-2rIgZ@MbC=Q%wU*=Ds^{p} zHNx>KO0ld+PsbLJP)kF@$WXy3VCcZ1Jt8YCdOPMkrE@uL@l7F8#o|eV#Ln^nVs>k& zHY{^9c2oyaGHy0z8Ys8s%-ITLGFP0`DdtWjU{eBw<%S{Iif=P9end&Sp*=@aY&Jwu zNcY?*(c;uq0X<5FBs;W<+LMBiQ`D_oLZ401xk*7SQq-w>It&H(1)N_UeLH-{wwbPT zuWVn?x@}IA(BX;q4*PH$z-JM;;uRr<`Jj~^ZEa5ipQ>QtzFcQ|A5QD52Fq*9^>jl= z4n7lm0vcN72ue7#Kz^>ihIN3t9Ph<1ey2hy+VEbQkozP}s|a;b&a#c?xG$j7d@=sG z{>Vyye*DGI2n7#nD|J4B7HF?HE{rU&BKz;0_?N<#@9GxovHHgx9T~<9G~Gtl=5yMK z&PoBA*?=#m{P$5mF!LslacsT9BqjEkijE$?`E+ER_=KK8s-FC6T7gT>l@HN{znF6y z^fj%4fA@n~(TRyXidINC#zfmsY~ z=68I~+zRE-1-2boQCb=`;W_8n;z`Th-%J85+5Du~X04!LBCvMkz7|6eLm_AjDB z@b%45CB)O4{6})D-L+ZJJewSV-u$vYjO4FTuEA1O^8I1QJnn;*Udy0FgPkxlJ^lQb-sit+zuoJ=Wi0^yFlth|9QuNfxq9FBez6Fes!UdQoUBvc}zO0c61!8$w`7LUg#_4yX+TpMKwa*k}~ za`GNZa1EbxIpwxilg`p2Jq{PQTpp92T~rSxiPe=1xk%a()xDI9Ph+S~@o zn<$E;8z|fNLO-j_ z>V*1EmfvZRSj&`vqR1)=%S5%NdGhcb*KCkhg0HOA zHK?mbC=qW=jbtbAC7KLuA-*>&*=g>@#?};}m*kh37}wSOM1HhGNJ{Rfa?flRaPf0u zV)7}5TH~aUjc@Y)ix3VXznpky8u7kdQ9P)>P^vqYi1i5F%79ApL9zcHg8aBf41GT) zO5W#12-oIjSa##weu0v5J0>rPm{gK;=kte*)D}7mmbd7g9LZMALKX(JMLo-C*{l zA~M3Lanh52OcU^HNUyMBRFj>t92+LBzF<(faays4 zCjVQh!2=tTO6XC6A5g*?yt^O{W)z3#l8qmP4j?HvwIn7a3;UbjJR`s0yJn7yb54u< z(Z_ri1VP6t7=mJ*QvITQ8^SO+-av>4ZPX4z97x=)Bv4$B)$NG5*w-#pxA1*gB_!8V zXP%dKPn6Q-oCP0GvRxY>&H_^7nEijmd%pT)Syz2yaUehVkwS&H6sb#!mdiQ#V=N%z z`6V;QeHw-2b;+vARPw~8l&l({#H5*g&vTT6CzY;N3KyroeItQ>SbduTtD?kF{ODpy ziST|%B23($l*m_n&dFDtNnPAq#qCCPeFcepgn~HdwCGmCdt_t-a$knIjSKgbDpN9q zY*irNONBXFA=CSw2k;^@t!!aU)?ErF#g_`@za$ zXIECtgOB3c+KO`0S=r0;xWX06((;Hy4^g%!Jw^r?$&g6r!{E zS}t~OM#B0$@~CYnIlO!ooarX&3$CMA`a%f+@9B#(G)2)Xpbn8 zid+o2p+xI?j{YP~1h3s{tB&Hx50V&R#i{yWBS~?NG^N~u8{56#iOdXXz|FgTTe;xa z*b)?%>Zaf*l73ATIFbhDZmN>xtB#DMDELj-_E-4P>q6F3P%Ep=N6B}msLoPhP>v3? zq-xHJKAi}IS_;0(4|6wOW!$Nl&#zW0ab(^_x4q(We}$ArUS`uN`#eSQt9Xk83L{20~i^6%L zp@5-O`*Gr>63K?T$wh|m;$6(V7uBjPj4?`imvGtg(DKmVPSlWG&b||G1eb}Km*Zxp zJ$KyHOC@h)pt;}Lp1yl%XavP>waLhetR{Eogz{)^nsy|y4hSS)>~E6CJXiCRkB69r zd$9zmi-_F4QX>aYGBo%Pr8?$IE|gQ<45FM#E_k7#7*>%ehg?Tt8=wdlgqTWCMV045 z`8{zBqe=VV-u&QCk){f04FZg!vc4oSp>4`Joj;M7?4ayJy_nCaOMUn|e)y1(xXdIp z8FI6Tw4JEfUsGK_NQ3G-(zj3!iYwlUOxscp|EvS8hkBz4bG01I+0nm3bVo+|N=w@O z&8yET6n}?s*AgY(FiZe2iJTa%fUg#LKBa~m3EYy{qG}`UXvCT%WFp`a1x#w%_k^sg z9As&{F4T8&=v&2G))MF{_9kikOH7NDzUCN`qGimU;CMtPV^=2JB4dfTntf~!9{&VvMPgQA9Gqq8Ld?g(NSN>Pd%la z7t?>a7ioKtI+v)0X-9mGs-S?5(ftOuS1N?;LJAxj>Jy<&I{lldQ9nw<5mY?sdU_fq zWKQ@|I*qP9^>6OTZ@v<yQXG3ORj{#HZRgP7@P2sv-ssR0-3H#)#~*-KNFd+V_Ze@ zSJVF$9DQ5GO%>G*#g!El7Zo!J+g#SAl&zQsmX+JWJBar*gAPXG{C}rdbO)GC6E<b&{Li~r3K_@Dl%ThYV zqIm4NhzlYd%i+Rt6syM+V)8D55{?Dbl6h+FREZwno*__*d;<&h%~a8aG)bq{u@0kK zQDJG%?n8p6Q01kydDH)kXu2I2I9Aex*G`OFzym}ZQSczL%G>A|bq0~YR<6M^FT-y9 zk0SVU5S#R)TjcE=O%cUglJ5o_ONmk?!!(F9xuX=)IyraetlH2p1eds!wOqkZEew{E zuTH9wy}8(vYAeNDa3Y%SPQUY-GG4i+y@aAZQ))s(-L!-~*^cOcqa>P{#_pOpUzJy| zefyjWi6*)E9j}VL#pZWIu=zbC5)~fhFo%{9v_(|dCGmcAgme;@cM=Y845`#v$|56}8r=yjrX((i z_LbWx1>TFlxm`o;7!9?<2>c6*gSll+y~)8{bv@9{;Kf{cRwSRI8b*`BmK2(=LzK94 z%sEqZnect>NcN$j&N6i5e*)4arXqcvo}Ac?M0`h~kkXkmm=llJSetvX{2{V-M$Cb2 z#35VBgF^MIa2q{MFsqsJoTdEjxzRUi|4r-g2fuf(l=>20)k(1PP_lDlysHpN7^P5Y zBGXD)QeCGnpv@Q*#m>b;^pl>~$)i1_YppXbXJ1bH_omXn+=BUj1f`QQ2CNFJ(rw`O z1STzk5s&HWvBG-m3Vjsn}vDdczHHs6yCuNTd2Dr@=epY?&L5|!T z*_fcd$E@o*l@4@Kn!wZ9yo3)v$SlcQt9H^kV~ z-@&gQ7O6^YD&vkFmDMA|n|ExLcS03k4;OEQ?cW(?HGp?y;k7?6v*Y_u8o7Cgvhek(M6Cz1r`;g|X$G5Z|okDtwof?x&+DC36 zfBH(aD2n4fJpz23oWCko4Be3LombFp{~UifT;6_C?r?j$!!HAOc&a3<$YrODIR0Hy z)(<(t{g3|rkI9gIqsX<+*e}l^8+VORPaY^4?9>*&2gYNa_YW{L83QcF)6Jy<}c1ZT)KSjrW5}27CORz zl)ACll{{2a*K_K_3aCN4a}|x2r%R4ds*JM4Ke=XY%-h82#R`rd6B06LCXf^K+(!-V z8EL3EbTKw1_Y&I=r7p1!E3tTrqpKqGAX3i8+yVUbJjp{5OPC_L8yPrU(XpZ0%xzXs zp63UWo_IT66o32}Q;;gEd-Zonr+=mT%3jyXrc9;k{u0lu*LPULqSVWI!3lsK`mLn6 zk5?ia_>Sc9x{`0^UC?f14Gi8B|F!WHYde| z>&Khf8iTuVv{bQQ&?pfO`JF=UX}-2+N#|-_`S3UL0D+m`z%TK zd`LQxXUI9QIiB*mi(0zAs@SNR*+PgOibRrqJM@sV3+3m3A=$(0E*b$ZA>CirjCRgl zmp-KY;Q{3dGH)?yb8q1{=SSOJ(djD3X75Qub*`c#Po*_#WH|daWjf1>blZ6-$5zLb z;*Q5Wbv~K2x=uo^df+F#`tAh$Aw{pm7I+?6@sSGaYio5;tRv6^r3_cq7`MS*r8wQK z@DaheQF$S`U28%TiDVjI|OPrxrIRJ%)vn=4DYj9+dmMTfOVIr?=S#b?)8v~m*e z7jyi@z|622if(02AgNx|r9I)qP9R_}D2kMp@am~@y0;Uku~9r$FWM+3SpQW^?k$1> zxTX;!hqIEEJC*U#mcmu$smgpZ;6pOEUNM(9=d@1>XMReEXMF{$VKgmxhbRtHYnGJh zMtu#Jyem+i;I@D^s}pf}N=g49BbpJHiME&c1;^%w$)8TPKBY9BH9N+scn?a%DIr6n zX75T`-r+Z&*1k#Gq*4KW`OTFfqeKFh4q8nU*M#m@tPowcHNsrOHUEh0hv>qPh>a%@ z+UF#nWo)enxyO;scS=PstI~~D#~llHJ}_qs)-*NffU9<3-MPQ`D%gQt5Rf_OFQLoX zKZ2GD_~4vRP*cg$w;V5()D%r4b>N<&m07AN-ApIc4kY#sQmMHoNs8e<)au`K+9YIr z9BFfcf=%4k(S49Ob2~t(UT(yGHRbN6$Oejfpk%mx0GIC=FVD&ky>6r>mw#CaL#@91 ztsqTKh)jMe$M`d~M?40@i42p1WmwUvM{`n=-uDbk035 zV!gPIk&yepNc@iiIy6x1ldP$uT^Jji=55_7`-<98FQdhQ`d)h_L7Od!$)o>dl(_@x z^kZ3-pVLHl$ZNQ?iQ7`6|Ph?yHt941BGm<63?=3g_^Art@l1rW2vsx zS!KsujvXY0f#Ip10Gmfy7!?zJTie(Tq)vgf=lz41V+`t?P1aS%QbGD^P~mYt&iW7Mw+@MjJR$G`*H1tU_QH{Gq<5U!z#`ziU3bIqPqz6gqTi)*k3HA z+n+j)-w@dY5j^HxcHW0lTo$ij)&O+o^z)=3hIg70F~DD(y?caoGl%b&5%%Na)yl1}0VVcDV^d6&GI8%X5iX`(ezYy$OqvctP znaK4YNX36%njMjeN+5kaIXyJ`d{9>FYwTK0<-GfND(Cp|;$A>qq?=1}{>Flim^4Ap zbfuVkku-V%HbZ&rJoguOR~TAuUxc8{6(`{o4CvJp^Oo@ z2Vpx3_Tp3m6Z{jF8U;e%K(mc3GHhTVJgACon(G0GIK#A(9YdTu&mJ`KWS|J$X^NbO;4wnBRra@nW#eD{7Mk!EOsdWEw5v0%Hcl>a8FgrD6QUfZZshc#5IZ^#P$oCBFVG zQHlFt3_MT8G~h+f;4&pl;adVqmc~$)_Kys(?7-g4VdquU&_h&ImrTwrB4BOR=Xr~- zSQpoPe*bt$q}+qGho}eHNbJHawT{^*6rQ@sh-;L8lW_kUd{QK38+x)7MP+1f$cACxc(hCkxE zvz4NY%!=~*dvMVsBI1iP4;}Mcxumb)2@)@Q6ezYgpM_c@%(+qhJd6|{7b{J%sEt=z zBWhirR@N?=N$p8vwPXPO$U%n1RmyB{ zqzcT{CYD#057MSi=7t%%!-fxO)j~>}1?i!A7DZ}B5 zBqrhEu`YQ3Q3R%j{%(MIBYO)W`BI5;%E*0?g9jeG;UR!9zu@Y&12`U+xfapmw zvQZJdVW5#>KZ!KBC1PX{>6kgbHgpL`$Z^*0k;`x#F_tvR1VvE>lyWFwCXo18zdsGWJ}Y1DTD`0w-BTVsS!$H zZshdyB^k*~w88S#L<;s|vhQYP$8%WUn!-3G0!%(cmpp;lOuO^03?@V+ zL{1y|YJ&HDU|z&~SQ9nC#kJHYrIM7G2kzY|=zB)KU>m!onS`!~#4VB3zK3`%iB@i= zEoM6|KS^;bEc;Nr8ceVr3IGZrlFh^|3rMkx z1F}TNr%H(ONRgWZ!8aRsw;5aOUkPhvet z@whqSP&ac=)tbydL{o3w123Zb{2kyGJYAp|Hi`HQl5@fs%-o>7&Ur`1_zKgm$)mVS zI7dN~Tl={qA?l-q*(`<-4bavpX{;_E$TL?Zh{D4ztEW_q>DjAr8f9T1=sWSY1KV=4T%eSAQB`AwyS(+FX$%>No4S}G9H(B+(t;Ml#gR!7qTnUlr zxOIWzz@RcpiAJqPF-wIMDII3x-LbE=Cw5tBYKpO`n- zzTAO)dPIGBke=5T$M#1ns~}JC;yf_4qiuTE@wH3 zoc=BlE#cmEizh(3UMjFzUa<%D*HIgpDsu<)f$+_e!j#8k9&;1tekg}Uyphbxr%3+s zv4#|vcGGl3+{->bCNcAcbfSue2NBlIlS4fN!%yp;yt#2N*B&0jopX}& zDFHuUA(A(Zh?S9Gj$AR%6_Y+eDU4)F28{ z^cqa{gsE-3Zj~P5UB`9rQBorMBhXhVLFq~oz8FxUK|K4YE5Zr<=#zmxDe1?gqcTR_ zIi)m0Qs{jm-|$q+g0{o*MDCN_sK)wv7vvY@i&%6fW6{+?EP8sxn4ApJPb6Rm4H2C{ z3z+EbbBs6%lSgR6;Rb&C3yDB=nGXM{gnzk0e2~$lp_n*qFNrNqrOeFmbb)yY1&=8c zgWaihC85xXM5s>cCnM;6nshsqqURJ!D}3SM;a!xw6mF5RW28lhy zN($T45z|viqV%LpJrj>6B%&8bUyS2hHV8_bTAo0fwu{)oRF8)1^=!@haF1~FJ&Mxg zMbdPC?jIS+D#kRFR_bx^{zR}Y`a%&I-u$JVHz`!DrQV2FKoYe;*AS7tLPS_%o*bP; zi905;P$F24)|r@l23jeChc9a(C=ohoUdq< zdx&x-sdQCH2U<3>HB2iC*|FhVdBGqN5k0`kcgH;DTUVM=&moV?6s;=EOI1%3sR>f6 z#qo>oA-*L#9RulQ8M0x%7jnr140$m8{MF>?T`@QeomuOz6!8j9zC>E6it6gBYWLG)~ZT zE1wqjV@Z=b@p?^ibJ#$2I620T#psNH6n;k$zf>SYqV_WBkl&#Et%^)aH`Bxppo5zo z5L_N5E8nsMDf&rhyhKQA)Ub$`#l|X$4qm2FunZ!aZPl2W^ARN2qQ-bWqHnj>aBzU+ zeOTjUc0G8GAFY%03vP30^m~(J@2`wXrrAQ~XGy|yLR1rXLx1PW<3sA#lHsftHeuIYs9L`_sge5NS;C`87qmQ%ohH>t91k0vX}%yHLqajCA7Ea-c$+fxV)V@veSE^P zoWONomR3x>D3Ux2>O)+YM8Yp#B}tqWwW9*u7>_p>r|-+3JSBA`aW$j|S^I*TooJ!j zoAWA^DJx@`m4N+u8i0P?=-7g`l@XXl8QuN8L?COFur^ed@q5Z3bfdU- zP+;=XyB-aQwjEWG4j5NQUgoqH!mWB`&Z{83IqmHDgQB4+w{+^04(D!C=9JqPjoQNr z>p_tgRgP|d|L0@WR z3RV-~og(j6o+F_%sF<6AZ;CXi@wCD4y!^afMsx~N6XRG=dw$Ej{DSFs_of)P&zt_$ zUU_-jx45~>^tpTA+GYAhyWG}g`u`|xC&g@Rc0cn1Y1Bd*#PSAq0MeO#7OmlGWes`Z zBN0NLOknGki77Ts%t{Vc#r{z|$gUjZE~MO;z=nj41dSdmUlQzJr90v?YqW=ocwuYCTe8(m+O9@zABqFsIQ8SEAPak?2Mz=VL!^z<+16{tphlQbo@v1NA`(G@MjA7 z^Quzk!Tod#A*zJWk+WIAmkif`CsLCl28uvM!)g;he34qVp;pjZvl1h@^5Y8dV)Hgu z5$9IKf~wa-?ns0WlG?$HXE7r&C5!W@9LL9Jv^tF+qViuYKgR=nZPL#C*7%5LRk=OM zzA0#x*T0SqN~^dZH=Y_kCUR88|HmjDYs@>ok3@s7ID1}RLDy}*dt}F5eZ|*K)ghBmb_gqI&=IRo8)b6`=-+J>=j$*p52?tdCh9kD(@&(dya_C zH1CXIV)&+SL`1!7TG^s9om21861^S?4kJ~wJs(bBNmNnqVaTpH5hg|R3tr| zgD)wmYVQ5D6UpwKrEL&)#Z0zb$oc2U-ACMh!Ej-}Q(gWHu?n+ux;30g&-HRR7+w-h zY~1>A{JaQnSxKbC_b-B0BL~CkRW&`$A) z8x7rjv>=OIHP{e(Of^-!bk{4OCg0{6!mvWYb3YB;-V&a$Cqp7VbOm8LS;53Eq#6fB zSJkhjQDOC0!W_AzZ=;eL)==sZ^m@uo2PL6q8-xX0$saYU(Jkfkv0$V9IAxY6DypPDpq=aX?30#jR=N3syh`V^^CT~AdqFcmQ zc{JaAY`Bb=TbjfUY|xEEUjkVuwVOK;U38Wb@rMog47EOr@b#AQ24`|_tQh<-7hR(S zOVq(7lJ1ohjb1TKrJ@bLBDg5C>a4gCoP4RVorESRiA))N*hE#+g_6bMSWrKI|Cj35 zSu&CAC08_X7nA*+qyqKl2|+?LZy=&K$#uhW59c=_P#Eg8difSnRiBGOp@oEBz5EuW++Dd-*g&fMrlvPk z)YjFr9p$j%@Tg0jjx6FbW0Z`Cxz}XL<(KrXso+UEZ+z46(QadO0i|^qZ1CQo)FIXv zn<`X8y3bMgm+39!MTug$wBrNo2k4G?IVEXQ7&6rxueEL>InPmMczBUf((pSOHCPP> zuTd#&d5dFbM2rf~V|54lGv(_v$p^k~m$TXWf~;sA$zQ@bi@VG-l_s&=MJTZ1!Z;#X zs)9c=>-iLsxn1dg?jcHB!n`P^o$+*G2d-NXu`PNPshJAQvuT+2m6(MtG2wpZ5VesC z{2*1OfEQ)l4@N`_3Lz9dk0k6*gy=|X77)A{^1Gso3e*ngI!=X6Q?iEFP?R1VUdnuQraLR%3z zgFaz;khPZF`!zCaA}^iTc#q}ya>XViOK=Q7drxdX7)ojQUP+-|7R)Oy)2;ZyoOHY* zQedd{r20V|o~1NUG!xZ<2XJf`je+Q22 zsIcHoeQ{|<@$`Gbb5`W7${0Fmg#DE^W-m=MlHklDI4z{pHlD6Mi;I4$3~OC&eX4HQ zz-sPKl}){bzc^N!3-jRc0fKv}0yk(>swb&NbNH?hrl7<&!Ocz-@5khD5Vsjb>dMiH za#S3m=mzyWB6E0XhDvyT6-N=bP`o~q6bft1%=;9>Xc@i8&WI;lw7KiZ&rc%34R4(( z`!Ja6z7q*%P^F*1rHT-}E%m+3*oB=$WqLq@B$C`}%_9g)|4_@A$1oC5&r-uGr7vM_ z&Y;UnWOQrENVCPwHRRJing|H>F)*A>AeSj|H(PVg=H#m)?5paH4M8hnf0abRq<1Ug zaK4%)E^Sa=6^4IvbhOD@5u186n7Nb2R>qP?9oNQGPu+AkQydxJCglvOpYS=G#N@V|yf73Arik^(a&Ic`PqA3n8Bblkn^*8}ZjD5f>|$v*@mQchyzDr= zE#3AH?S$XnB1P7W)kabY&Qwk@r!&l;Pf!|LY z3meYsP=d5~BwOO}r1@as3R2so+hr5Nwli9)%BaOZErNnYqWt7A! zIr-O%iD}DF5k#IeaX4@;rQ=nFO^Q*x(H-h8BC{kSQ#UiW(2gX!QJNX{ek#(l*!$92 zd={A!^U2R)1o4ZO+gqR$y8Jqy?o3tPJ#jaA{!*;`oI{7<^ zX?Y~=&2+w5PJvx4gAV#?eQUWtsc>>UHRpigMNU0Rj*E)Z>N3r$F5%!u;UHVxF+-kX zYwBn$8UwXw+^2tcJ#UxndUSXW$eZMp`qQKQ>ei#0`7<|}$_@;zC>Ldu$_xnf9}7NG zn=(V@t{mAS84|oPni9_jD6cS*9C=Qe9;2?cjCA=x4W*2RP^WV287UoMouipm>_vVp zQDTsICA1yCxtk%@IYhgZVqG9S9#eisXTU9C=}l?3`8 z$*ZvP(y;2C$*AF>Dza3-eDwKKiuF{9Pw@~|bPUpHxP`#Z3gHnQuC$Ss^ai&nG8m5H zAQItS-9j|m60(|F@u=i0Tis36)-EKfy&_8#B#?xONp7$2=K^EG&+t}?*&{Xh~XOMyCM)u>}+&}U#D5Ppod!<|6ok_=afoTjLG}2|Po;12m zem>feDbsNfb^JX!ulfwrrq+-=H>L>LG;iEQ(H-N02($&w{FO0z2wRZ$HJfG}LFn#_ zXcKhXHv+-KNT7Mqa5K*p??xGaU34W5FQu`5o+xz=G)i1*6!{k0tovEaACySb6Wqy3 zloD~@^ z>Qy4Y*^(-Ag_88(G)x0&0`YlYjf%5Yp_IyVJjvn1WdO#{^qTU7MCTCBK|qni73>Q2hK_e_-G&LDwXMuttKpPCP`&ZS^%9|BGzW!To~ z1iX!6QGMtm6vqD%xT%uVtY6c)w1t3e4n(@#>^L}rbG`}@3Yvu{WWwRRX?pNtY_5JJ zZ{G++j>qp^Q}wi&N{Px*aN@T6x@!@!C>-7#M8t>1+|pscnMi*Zn~GGT`;|{yal34* z6h<2}BbB_Nxj$1JBOWN{(o7EU0dnC<_0?ki5TQHKel8%UI3raUi*{9G6muFxvm#A$ zYN#he<532J+Mqahx+WsCcuY%Mb{Bf+cS5d)5w~Gss|e;VAq!*>tl$~LMIQ?%iX^7U zDH>j@E2nl-a$Z`cL%R=gc{W^@ZT@u2DYm{}s9C8xUXRj?4`1fQKa^_aoLEetJiQf? z&d8`#(5!wjw10L|ZMKn3Ke7{xJx@GRATIFU9eM9L5rv4U=wPQX-H{|p$-(5+$v4QX z(%9EgM3t)(Raz4QSQF1reoGu*QM?yLc19V0UoQED3pei z@(@O8{u08qs~i#c;gVN-F6Q{+i2A%Sm!!!4WI#heNtz@xnp;I$u2gc*N8&50^&4}d zJhP>wNO;-GkkNBVl<|sSHRc`EZ#ejuCToc}sfoi&)t7}o8=#B0NTxg+3v!jIk+%@z zY4PMiiF>}MaPlHE#!7gR{b=kvhC&jyipbdtEM#{tS-cwLcCLmcMGw$5bqV@{X%?Dhz|?#Q6bh9;^RVmQix9r zvAz(W72@+kd{KxEh1gh#FAMQiA-*oeH--4N5Z@Kz`$B9g#1DnoT!<}&_^}W_72@YY z{8ETt3-MbaUT@4_(U|{6WB!|s`70aqS2gCp)tLWwWB%&K{56gF?=TYIe^X=r4~^u3r(~LCN}45G$FaAiT!|Ph=dR94B1qGP#xzas zDKYD0Ko!=%Ym3*DcZWp!ANHC}BpVjx6;%8mPCKq+5>9(d;It18#gN)%WIb-A7>)|Q z#pHnQKQ>UvRw?6IR$Hq9IDn?JbL5=mnRGL*c`+T=T7yW5sAV9D^q>4jP$-vkxHOGl z+CiC}oYrXPkqryw0xX3S9WxWgWp6IfJECQ(q)tciVWQYVEiTe7h7O*^#ruTDQoPTg z&wPv;luf?RS0TD;sQ39qd$A4S;tU58%?T`0=4`czRc|S(jjY%s3{|36T(5hQ)dcGU z#h7GOM=kOFUdkP>T$CABI!mc*DF^wmxDhX$OJ{kq97{gK_aevc4#5$x0_cix2r*fx z>*ms(FZcT;dchw$V=k z#KSPlm1U|eY0^k^3F&j*}eqWG5c?2y>%{i@? zP~6HTH%6}BJQYmSa=)((OqiQ*CJ-1zdA>Z-!OEO>5(~)8RRLh)s!woN#4v&bXl-mo zr3PjWH0VkQ{CCQXrMh+1a&cn`xvh!dv08ZDmSeX_W`^}pJZD!VX+w4{k)!gJdNtOL zV~aF{Pm^MRyB~SuM#4>mbffYi=RT#8x>7JtQF;+~Hf@gPjhLw8s~F)wUOAEL@zGLU zSMK6+mrGD8s*UY`0in1}bki#?wFlQ$)RpH=-^_47xN;(bw|>&JR}M?&G@c>3AJkzC zFQO?ZMF*rQp~)1+Nk?xpnK3yYG7SF@96L&ipU64!7(9`5TEbssBjYHJ!kf=|d_rle ziMcA;@u*GHZiMYCWw)B?<>SzBXP`f#pf*`h-H{MBM5++JeV5EN zuc9!Q$Ix}tfZLAj-8iJGv|?<~s`9vSui7eaLoK z=iFD^fhK*A=oi~cEniORwFx9!>~g4ViM_~Ns&pzwvDv`>4dVDpqyag%q5G1A`^8_# zsZY9+U+AO0(A>%NV_bi$l=$e1xl+H$wC_i%<&)sw#>LB|>kJZ?W)ksfvVTRmOB$l7 zyEx_9Q7S}#UIj`-VdqmLmPu=n?1^+RRj?q!Cb&q}i~&5G2t5;-1m;AOH}QHArxnV= zrOJ)s)_W*)QGqBc~rP*()pEFHW(S1A1RKbqlw~PzBX?o=WQPXQzWyu3Y_T# z=kwUiiN@-1k$c?<^lH{!D z)8nIKC;*-c9F3P)*O90-k@OTXVs1u}U*q)l;dCRPJD+nqN$18p^odii8z@%?L>}Bc z|Gt{q&^>a+Ii~b(3iS1nth3ih;>=?Y4lh@BSl^%>Ly2rDDKCm;j1=Lyr2BSC34)pu z<=nrfkLs(xGNL5mx=0dw{a?epk|G5{^iD`N_SuPFzFcC)#A?@| zJCZwPTG(IWtH`HbsHU)ZT$BZx!DGbX6E{WE~(p8WSQbY(T5C{;` zC?bU3JJONfZCKD%v3IPfVDG*6UcRTC+1Z_)&E6YPU%x-^`-^+ubFOpdJkL3EW_D&0 ztR~Llf9}EhCz<6PnVYPl%HfOJnpeQ-*-1>{605?zru1iANAvnVJZETHW^OhW-fR`l zE~;><^*CJv^jVcAgxUU?6ZZ~bE0sWRbx@W43a<1oSl-HL%>58 zFh3Gd$FX9Yh(}os+~R-yqah!*3a$%RaFc(g@XH_6ndhx4`@@z@^_OT$UbL#@gew^D zFEBmcWmVa4a^=tOF{@;E*pf@^64TscR;7*oc*yzh8*2jIvI>@kEBKhcv-QYM&q*1Z zM$tcMeUpOH4mty4D z%f>7=Q%bpwR>PY$hSco*q2|bZ#wwa>@6$}em#w0GT1#K#(trBsDXVOUH7N9qokFRb?E>X)5DM7OG4jIbG#RBxk5BLvp6dvLt7zEJt#-%9BaXQF#iCzAK5>`d}rm0d{Qr}AQw z_p7{w`n5p%048Y zRN0s0Q!4wBd|G9HlFz8ToaD1A2atSD1k$rn`)A$e5gl_Za; z97^&fmBUEBtTKh|RwW{`YSd8vT+| zd<-pOEO{@qh_U3|&?3f?_d|;qOWqMJVk~)2w1~0fUC|=OlJ`Z67)#z6En+NrZ?uS! zq~A}DkD*13CGU+EF_yeHTEtlL-e?hH$$O(kj3w`l7BQB*H(JD4^4@3>W668lp_2DT zix_RCKQSL4LyH(o-rH`H2|AFxM_R~Y=j1>2o7BW)YWm?BbagS*kBgGx2Rg4t(mlm)CGUn7F_yd^TEtlLj%X2M$$O$jEH+jmp*4&Y*QX_n6j!Gej1d2h5@vE;qcYQ>WGMynM|-rIXBd2h5@@mAg&tyUyu&eCed zlK1w}iEA%fzG>CstIZSFUYds!*It?j=-TTOW%=6cQ*g_8U>cTtp3JpUP=E?LPd57$t6nCzj6{^qC|-p`6*el z5^XO*Ke1ANreB>+*1hI}puF;W(FUl+^ImK6{&>aVnr(raR!_Bdtkl%r zUO=^r7iUMRc`E&A9yK%8DmOnQzD`7*7KXMn&+&AjAH3a*qoOY%`gHoy-tySk{kC!x zlfdf*|BpxWQu--RKY_D_R)rGlf+A$HEB%}Sk==;meFwJ5W4k1z&C7_Y;6et^AKrU+ z`q34V|EnveH5zt)nd||RJz=sJO!g*{&ygB?QT^-#lYL>bA50D)lF!c0F$&J*K!_Ry zQG-2mMqOe2b~Qk;7ao&)I+l>t#BAZjF0wdhCtWv^hohHMUrHHINs4j@l{!1R+dRyf#>xsBKWGTXle{ZjU}oM{m=?c?eWTKuN$Fz z9!KST?N;=jvx%r1ks1$CIYiZSw8dkwC?vzVM4jtG@-eRG9qW5U9#QpO$k6f4C(7$W zhR*z}h&s=O4Bh(_qRxlNtBGm=kyD9k2$9o>Y6Ovmg}fFv#@Ol1Ho@2#%<>g%;4IQ} ze&8%GoC$KXKyEh3&0&tOog?&bF38OTx%nWsfH}Tu59}Ww6Txdq;X;sG1agZ(ZV7Yz zeIY{smV(?ekXsINE0}8;xqmA`ZWVLSAh(;ji(K~Y zXm1a5?ILq~nQI@J+s9mo$lQMBI!5NMV~)S~Mwm0#gWL_^es2W1TbSz{xqr7Z*CjG{ z8^|35_j^0Y-N78+2Z)eoA9H*MAOd$M$lV3*_im88hdI9A5TSqfg4}(~b&cHK{UG-M z$UO*h4}sjnAomE!J;fZ~g9*$t-_z0Slfb*hg-yU#M) z!-aKe_c>;JI#_O#zh7*S^*Hd(K;iSu^BtMMelWk-oqvUSzAxkC9qa9D%=K~MxZU7y zFNJS`ZNAMM-@kG0+ojF-z&76pxeq|@Ly-G~IljXb7)zLW^(nLcU09d#|BTto9jwl& zpzk7|GspL>0{5@&1#w?6H_*YkwD)B=F7!KS;aA~U#~k{aIldnj*hiOre-n;#+4r~M zSjWD zbIJ8d%nrraGRzKhVfl{WELn$w*21z;^5vLMacSQ%mre$`Q<&p>lg>PFe;sS)sZp?} zG0S%{o$WgMc{+1^A2R}1o;kjg8G$>4xs1r%nauIs%n0pOV23p36&>e)9yZr#&QE0j6573>2mOK9d-C5|_V86QvEl&Y} zwl5Z1o&^B(B|^&+0f4?#Xn8IWNV{CqcNJ2e3`8Ki2`SG8B9NB}DNhF?kllrp=K~SQ z9zx0!f(T?!A>|oCAZdN)n!b!XId$7>*WCEav2))6r-(hCJl~O~VXt=fSGG~TL4SBW!))*!=-E!p8cAC)g1O#Y1U1)g@;zqkj&E@zgx(ph z?=J0+lp6AM1ZY1~Xn95g(4&NwCnW$qT4;G*0?=7P%Tp789wW3oJ8{x3$JAJ%w0q0Osca*B}h1SvwBSHt8~A?0aPgf^$aWTBAqWGX_N z(}k30QxV7+Ldw&r2;@v5<@rx(U$hgnk(8_j;k_Nhi?u2B9AX+ukVjV{WwL z9Iy!{uNCrfpv}!Nxkbn)fHt?n18r`H$(=$z3ADKjCU*-dPq3Zi?--*!Fu4~d z_rc_Tn7jcdZxm9V$U9?qxwg6~JnhKT0hqj5NO{ih?17`rTZELS{1M1og_LLf5y;zw zJOa$8gF?!C01?`}UC0-JHt&E*AH4TFVe*iWF9Q9%2PW?o@+i>eeK2`HOg;dU55nXl zF!`jA$AH+Mg2|_0@)?+XR>+sQpJnBaEus(QidXza#WJcE9yExm~Wk--XHdgnZX-v&dY$9~J#URP={Y(H{vd z?^ZcS+%bM13;DhsVc4vFBBZ=u6`{>fg_Jj}oTSSWtIve~2WFtNitcLU~^-0vRi9${S-5$WlVeJ7W>Z z(n9_Tj6j@_F`P4Jn=aXk7rF#UCkR~G~S4JJ>A$?`(R1F@e0lV`$Y1(>V|la*kyGE64IWD-nzV6qBK zR)xv4giHX&y&6nbhshc+SraB}!Q|OOo&>~R8zz%svJOn11Cw=OvK~yH3zPL>(hHO4 z!Q}Zc*#IUR!ek>M%Q)xKGCFr`lJf_hgzWQ22gkL3X{!XvN=q)fXS9H z*$O6G!(mpeqI5SLxe03w0R{=4u#2KFqs0A!(lR2$TNW0 z(_k`P$TNX9GhlLrkQIP7N5W*LkQIS8N5SN1n9PF7F)%q6Cda{KHcXC($sCx>g~>da z%!kPWn4AEU6Jc_akd=V>ITuUOfH1UMKHM-CYQkEQXwk?$L2DaTn>{fU~(l)u7b&HU~)A~u7Sz5Fu4vU z*TdunnA`}Hn_%)bFatpAAnta{OF)(xu%a;b}*^&kI?@nddP5eIY9PMR%HyNk=b^!sIa_ zYdZTI<~V;z=vq!X%q)62D*BbE=vSknUvsC!jLPfbX-A&l2v54qqBq0Sj&|P?@@z2A zZ%0MH6BYe#RP=l9beKH9AD(vP2u`<0OBD)Y6_$<9#;6Wupa(cik$E^Fv_F!{ZZA z2w4{x_lhuCNyvIYo0VZQ5hjyh(gTxKV6rMqo+aeD&Md8Vn9PI8e3&eN$q6ty5hf?W-m|O*u*TCdzm|O#sYhiL7 zOs-n89xeF$D!{i>A+zXTYU~)f9 zUI&xc!{iMxc_U2T1d|6~@@AO41txEW$=hJ^AWZsT@=lmM1e5o`F$!B2l z2u!{Vldr(!t1$T*Oui12Z@}c6F!>ftz73P_z~s9y`5sKZ50f9jXMVPDvlQm%SY?!PKljp!>U6`y7lg(hVB}}%0$+j@r5hlC9$$2oD50evNauQ5Vfyp^AITt49!Q_0HTmX{` zVe%T7Tnm%yU~(f&Zi2}zFu4yVuZPJSVDbP=-T{+$!Q|aAc`r=f2a^xNX(-@)YfF!=*a{s@yl!Q{^{`3p?` z3X{LV{6p z^{D6?QPDNS(~c{KS}=JwOxA|UWSFc2ljp!>U6`x~ljp)@eIYM!t`dQ8^B~km}~@-jbXA0Og4qdW-!@YNY_zySut9;)3e>zmzGh{t)ik^M@6>@ zPdnC^wlH}COkN0+7r|sZm~0P|9bmE}Om>3F&P<+7KY{-)i?zBqeh2O1aI9lAFO|Jt z1gt<^VX_-cUIvrhVX_BI_7t)m5PL6}>d;S|tSJ2NKI-3Qa=E{l5d}LU3U*`^ zY-SYfs3_RcQLtIzSeH8&W0);$Z?7(zXFB5LFONBn^086TUIajgSq4RS&Os;^*l`y#qCa;0X)k1c5#vbNd$eQr9D$){lQX_$NlCZC1L=Y;GDWa$V@J`a;Gz~qZC zc@!p(!Q@Lq_5!l>GEBY#ldr<$YcTmbOuivxZy@$JVe&1Qd>ba;fysAa@;#V*A0|J5 z$q!-jBbfXcCO?76Phs*inEV_jzYwwyFh9S9$**AYYnc2-$i6^7zlF)~VDfvI{6WZm zKtF$k$)8~IXPEp2CVz#=-(d20nEXS?{y;wegvl6wl2C}WSpp{IDNy0%KtE%pO@u53 zlcj|m0PH;uCgWi;0VYp^$uclmR>*-s?B!tcWSBe!CQpUQ(_r#+AqN4mmxswSVDe0u ztN@c0VX_iTR))z$AqNBbOoB-dOjd!(sxWyLOjd)*>M&UYCTqfEEtotTCTqiFGECNi z$#Y<`u8>y%^RpgIo(q%pVbTke=fULpLJk39Zvc}GVX~2sR|0!)43kY@vMEe9gURMF z*#ah8!elEUhXVO*4U=tPvMo$r0FxKOda{nJ_sDCP%|$7EF$T z$+0jw4koi{fU~(l)t`c&TbKJxHJ&0@E=`eo}Vs%vX8h6^|w<^{OIU4NqI(Iru zpVvo4Z*Zqw`n*xdEU?d;-03iVzBVd)vpen5=Pg2x0sFkwoetCIZBfzN-D#IT?+|h< z*yo+$Y3DnmLXHF5-R(|?$;F1C)gUR<{@&lOsP{;|u{QL+eKZeOqgq+BGkCneNVE?TFz6x~tJ@HSAuHm>o z|4isfQMCVg(KQ_HemquK!s=syPT>cuw zcW#_Zd*4ehr*K?>f3e1e`~fC^gvp;^@@JU*1tx!m$=_h|cbNP`$g6?O{|S>Z@idNw zNSh^KvLsB#!el9!EDe)!Fc}Y%2{3sQOqPMkvM^Z=CQpXRQ(*E`m^=+8Plw6!FnI<{ zo(Yo`V6vi+Q-R~X5=>Tx$wVQi0eeq^Ne@g`fyt^cc@|7ogURYJSpz0(!elL&JR2r! z!(=i{)`7`$V6v`|HJ$S_%-^i27oK)pSDhQ4bh)OjAD(u!>lL!l*CSNqGp|~NrycFK6mo{MU6=811(U5|vJFhO zg~JNSMro$x$#l8YZ(~atut4g~@R+nGKWU zVKN6Mb73+MCi7vk0468Eam%-$6m|OvqD`9dKOkM+%t6_2tOs<8=buhUeCO5$3Mj>Yd*EXAB zatlmuhshl=Az~rqkc^gdL0h9N_!UC4kllO$)hlN3?^TN$=6`=b(nk`Cf|X{cZHk-oDn{N z$q!-j6PWxICcl8mpJ4J=nEVYU|Afi71b)_wjL}IjSq3IghRIW4@^qN=z+_dJtPYbk zVX`(%)`7{!Le2$_&1Nv!941@AWNVnb046Vn$*wTj4JLcQWPg|(2$O?gatKUb36m)> zIT|L%z+^T|=D=h=OiqBwnL^HU9-A)jXU!6FK0wZf$+_^}=fQ2xhsgy(E&w802$PG1 zTjn3e3+v zFu7OAWk8$zU~)f9UJsKu3b`EU=S?tq048sN$=ifP-xWC+o_4HFw+p#~d7g^VW8_Z3~k z(fc)LS6&RftO(N zWte;gCSQfg*MwXRMD#jLz5$bO!sJ^p`3{pU<*Zmy{+mp{6}B?;xBlM+x%ZfB6}i3l zLGAz&kWT<@ehHIb33(W3 z^J|#=mPtOo?B7;Y#s7Bi+R%CVU6lOyQSv`CU(zwUF8%n0xxzKhmBEGl6>RZ0ko%oE z&5?ZsyX^N5=J+S@_W@nFKS3_$B&@v>%oVN$GE)*JW0^eN5eq$GF*Ah!C1d^{&&8Net?_@0TqRDAf-N5f zdj_+W{CzF54`)WfR)~VF$ZTbQAN1b<=X~+JaQs`Hm7-uPN5LjCo9NO9{wqcsr61PZ zl=+jyd=k!knD^j(73Qnpd{ySF;`~|6pM~?)n6Ku-JFb|kGgr9IZLQ=?I!3dG(Cb0E zrqCNex)#&b9X(!6eV88FkF%Mrfw8rjt?6K0j_zcTs{?Z9Fjp_~e(N$<--X*88h1Tr zy$&`^j?QJaaHE}l_Av=zu4>NX((_zec9{j|GkZS9Hej{^#x`WOA;vahwh_iQX0|cL zHet32#x`ZPse|Qnm(H%Bb4;@+*yd5NEuvssGTRL6Z>uQS)={u+qF~!H+uYG#mm~KA zkh>7%E&{oB%(aNzzxE*40pvP@Tqow7-;7=I*BRuxFz5Vc?9$#PAa^NqZ6oKeD{~h_ z=DLC0WgyobPSeNm-mifyayvsG;X66RCaN1_jccCrJ4s>B%t_!xhvHXp9 zRp@-#7LIlKCcWK_<+xn>u!Gq_SbulAv0?hVD;(?6-`&g(cIks-e(z=OipbnPklPP( z*D+VP8Cc`4hshgY@ZZH0y6+b|}W)%Iq))%Wd-A z>sj;@lMr-w^R_7YgHiIgGoRwpAII#w1LS-lcPGf*#oTb0{<+-kzdH){P!#MvQLy(i zo9fcvxiYpv^X5Kg(=hgaX45hD0cJBW_CaPxVC+N8j>Oo9na#x5N0=Rjv5zu48e<=0 zHVb1PXLgJW>o^XcU~X(=?l5!XB6CkNmmQgVin$yY&gHE3bQJ6}%;sY4J{tx59J7U6 zfV0LCn0#Kyt=y(wHR)5pWID2RRgMdM_IH%&e3!@^BYF(vUIMw7nVaCUUzZi&6=o-5 z?5oU9!r0fColHM=o{GHAd_7A3jVSpynZL@V?~bu}i@7NdZiat+gI3SCnZ4S<@;q?K z^E=EI&gbWa&L{US^t(bY0O|LHUI^0f3%v-WKM;B`NPj5w5|I8#=%r5D`gSo-&R0R# zA|FeQWzHH_&h>j

      oNd#_}j?d@40ogsb8Bj{2F92)e3)0^Ry$+YaJ0+le=jvQMp5Gjsj(@F8b3;nYon;~ zlhoK8u7+cV{Venrkp4yJtswoY(Az-zH=(zOqh0dHj&^DPPpPph zTn$J2G5kJM;ck#FA@m-QmUpcR_kwh+w7n0cO9{Onq)Q8Z9Z1IseZ3p)Sdrp|yupoh zS&!5E%)nKwZOxA$OnnK`J^){mo^&-`4m7lhRLQd*$gI|!(n-Fq;Erh@xXr#W z*-ywENM9xNFCaZd=wIDv#~5BM`gf3?CiEX5T`2UQAU$1Z z`US<{CsAR}vonOIrct$P=>|_Q?b7aC zCYiIJQtBCizh|!rJ%i6@zNDkwFzkXT*o9HBi=to`N5L+Mf?XN~yDSQJC9^sf6(!5b zGzMYvyNX%iyYzU>62--HknPBgUzaPY#T+;kC?|Aw9w1LS}fVvB)E`P_+Ht5ii|4CdMBelW# z;QIFd`M0F`=qudJbx)-qjZ-7w-zMZb_PQ(Vc4qB-+pHCz9=Aa`-^q0fcRE)DuA!>} z-wo#fNhG_3-UZUTnbwiy|Jqm8+;^8XWDoO|=tpCX$nTAk-xnpnpZUuE{uFs+T*qup zjJ=-OdM@m>GNwWI-)~^{To=~mUgrU3Tf49>xxR&2=Wlm~8JAn5U~gmA`5QoC+C3Nr z>tnVv7TcZ7I)AGqOdsxIwky`|-BGajM8V!01^WQAp}#2+Cb|csq8}1E;QjX^XZ*ua z(T_51{{}$BWBajSzQ~?D9tHaZvxBkmKFqB1t?n?Hev(<|yU=0Sr&8w)M!T5}% z%39f7j@W0V)}AP9J;$}2??hVtS|sZYpAYzaBP;w7=AG|G7QsKyyz?E&BKQ|1ija2? zts0K|LN79%Pd~s}{wTA-@6{DKYmPBL)unCDiry^@%FIjB^N=STVS4_u&>>GG!qBfo zMZYR^$bIZEZNC;3{kqU0_ld)_{YF&un^Dnk2`%?`fzf|ED*BzM=y#){-xK;JKAQ9j z%(~vxzXD-pvQ+4?_rBB&xw~rBa5-8(kQyQPO^c}UsnmFfd*{rmeKjd7!Dm9c-ix%_ zcO0#sOO25GZ%jMd{zAx*@3&UFE|GpIHA23*hN%%Bb7}?!QHpmgE^KOOZTNWoeQXRK}64s4|{pC6x&zE2}(-WTMJ4B$HH@CFxOFj${>; zCzGtI@)VM1sXUcrHI=84tgiBOk~LJ8Cs|YF86<0|Jd@?Rv}qmWmS@1m1mJWPh~Zd=c}wvvVqDPBpa%%NwSg3S|l5* zJey<_m9O0jvY*P% zB>SuELh^Ez7n2;I@)D8*RbEPRkjkzk2dnHx@(PugksPA3JIO0m_8>V_WlxgBRQ4j7 zqOv#1;VS!(OjX&JWSYu;B-2&)Cz+x0a*`ud4j?&FY!Ba+=C)l7%YAlbo(HhvW>Exg=+*%p*BV zWj@K-Dho)?Q8|I+T$K|^&Qm#wCJPTymMQ)736Fc81y&#?Dl`(%4yQR~b87?KQ^EQM=mMxoX!KJ5TLeW9O?~XY2yC z>y2Hgc7w5t)NV9(vD!_>E>U}}u}jr%Hg=iXEygZayVckgYPT7?QtftQSE=1$>@{k4 z8oOHUE@RiI-EHhzwR?(%Zvc7xje#%@%5ow1wLUT^HRYHu)hv)UVt-J@Kwjjoq#Gc4POby~EhOYJJA;Q+ube`_~(7IHuie8hm5^J?LEfcsP{UYTq*UIkj&adqnL!#y+q1U1MKR`<}5cs(s(sqiR1e z_L$lajeSY&N5;Oa_G4pTQTvIpud4mj*w@s4X6)-~KR5ObwO<(frrIx!eM{|E#=fog zYh&M0`;D>hs{Pj3_tbu8?E7lJH}(UyKN$O=+8>SmNbOI?eysLqV?R;*i?N@o{ngmd z)c$7d=W2g9_6xOt82hE#KaKrLZOjPyB2f6X+7iZoqqd~6->Qu@_B*wujQw71X=8s- z8)xi~YU7RlNo|6$KdU{-*k9C^G4@xrWsUt!Z8>9qS9`Ltf2cjh*gw^tYHUmiIscw! zEZyVb)A8xX($_M!<&BM1dxo*4)ShW?vx`GWJxp)r>t&ZFOT$S6jo_@@i`udxqLt#-6G6Y-1~^t!->Y zwaLa-Qd`H^%4*LsHc@R|W0Ta@GuET_Tw|-Kt#52qwO(V-QhT1U)zqGEY<0B_jIE)z zp|Lg9HZr!B+Q!D7t+t7=wbeE?Hd$>mW9z7GZtOW~TNqncZA)Y8scmKKxoTS*TVHJ( zW4&tI8hf7F3yeKq?S;lRPl!Pq8hI~vG zn`!JIwWEw3tah}qSE$W0c8JPBnI%+G)mS zt1UEkyxQr;=BS-vY_8gw#^$M=Wo*9M*~S*Aon!0-wR4S~sCJ&Qlhn>PcCy+9#$Kg% zp|MlcE;9CNwTq3Ns&|(W>j9sGkT4R^0-E8bKwOfo`u6C=j zE7Wc?cBR_w#;#Jk!`N%o?lg9_+Fi!3QM=pNwQBbmyH4$1W7n(QXY2;G`;FbG_BvxX zslDFVYt`Oh>}It$8oNd9O~!6jd%)OjYHv1nyV_ff-J$kYV|S{(&DdRP4;s5$?d`_y zQG186d)4}k-KX|WWB04Q%h>DG-fislY7ZHEgW7wHy;1GG#@?j%KC58P|X?x}vu3L#*962$S$&^YN%QX^N4$ojD zNo6KUkH}2kT7_ik;iI$jNLM8tJ3NcjSpsBDBw0;1vZ^i{CypXngJj9!Bx>@u)U<4p zwMdpG*@*Pnq~lVva?-h8ZDFz|lS~#lW-Q4%D!Jx4BC~Tz)+HIAnv>eN5w~8CT!Oe% zw&&V*B-#45oj}&>ugZnz`5l*?Pp(uNo%7;j8i*Xj?KKpc%d!#6^l_Z<#w1Ip=cIE+ zny@YyGp>MiQ_=|;S!rX^hI3TSESs6awz-ly97GE#%FQ!mOUo+Ripi0gW4Zm-q)Uy= zV%bJy0gp*rmYLG83s`2QrO?(3NtPzb-Mxr(9BIjKJ2LTNxTw9~@%VS}J5EYRa@+*# zPNb=c)J8nsowXp9$F7Ufy!~R*w0rKPVLD3xSsnohi*G^2TbrVEn8dCri{IWiO@RLk~}q~pfqXhEj(-1;byx!jl0BJ+9R zvP2f}fi{NaxEuz?l8nn9JyOy!&X_#TbvBvO*;#4anekkKG|3#5yk_JwF+L@YH|LR# zXWg(FxqNbQ>{^g1P%M{^i3w7WrgbK&$<628O%f_sj-1J=W&2g6Qa&AC=RXAt@CKjmhN^o-QUMT_)@d%kbW38k5NbHOn$wGMh}P9GN?F zRPvC_B^jSt2_x%M*4a2U%i!^hVO%kZ+fl1u{E$<1#-c9m@#lD)>*MopV>Gpos- zL@-;P!)wTwQLok425#U6)|m#(D6c0QPZc!o4dl4L68J_nI-Hxdnl*;kYBe*6o5_{Z zlhhU|7?YJUoD;v*?|6K-k&DZvGM;SPt)eu}<_@cfbGVaC0&`i?$S&J*E4!_VGL`rE z3#FaCek=2TpKZD7eyge!UgvjQcD>~$aK~@(J1)DC9CuvK);F1=T-o6P%Smr;CdWO` z&62`fv>ru5johjv89rujvx@j&KWG)n@qW80k|X{OQ_5e9bLcS#7K~tnjcu0zJa^;wO*fN~Q zM~snU@=?oh$zx`@T&|gPPl?IXGu_ithYZzu z#%K=qS<DgOksAuLJ`nKOO z_>SLkZ{8)x&9Q!uH1$l+q3@dl&iDtUsbf5+J`^eI^hYA)V&!9z6L>-Tgk@nX5H-^j(0lZEehHM;Qqq1CK~?@z5}=3vYSt~Mqmg=bX>HMDGzDXAu34!Kw| z3HkmrYbmnvVtLo4g&eQDj#Hz%j@N3|t`oGH+4V_6(g};(C?iE=QrMLxS2|x0t#YPB z53Q3;$wZ<~(GqiLok}h)-?V+27&FSJlS#;DBY7)tmGStUL8dg7@zgkzbUbUpDwqs!Z29s-;us7|ncL z)mhxxdPZ{;=NipSeWUrSlUMZ^p7!UFjw?tVlg*XS*8=%I(Lf6d@;GS?EyGD~q?BBF zHns|QxoKhH8PC z&X$u?OBciOf_AZ#j7ga|mJ@M_l#nBRsg`7pm6EPnlF1qBrdm$amywPu;L8sx=xz!) zlpdx)CPPm(;|iGSWf^X(w^osJc^}nsD(|b1E(!g#KrZF`iyoWK-(xQqXsli`46qFE zeV{SY)*z`eE{FFw*l3RZ3excf*|ZRFw}x0wj)N=7#c>&r#85Swmtn?8DpJIZPZ`cT zrSH~M$9z9XC6iDvKFy>i&2J?k)O{_@my=?KZMiEW)Y6xveD3o|vhfAu$+F8NM|;r> zj3RSV!T6lCG1|~*MRRgTaywb%s1M{M_Av$~EA5UYPc11sPHU3Mr<&Q8lZxZXQ9D+> z98*swX0DXwSc^%XRLn_FmE$ts?>IjN#_1Q836^Wj^LV1=n(^$Nq|O`&lhx7f0zQ(i z@;jcfQ~Zu|bG6^`aXHoRc(kYa9nbDUzvG2vI=Q$4leHOIWRf=1D&jU~kx3wKd`=!O zJF{)e@y#)44tH~|Da#)&i|jnI@ddf*S+XF`x121A3;d2(jfIvg;5HYLiz}c};qhEd zrZgMUOH6?b&{9*teO#tGi@&fgSBSbxW`!0=?^YVk&??n=@{P%89+K5YHzvKtXdaxk zq$w1>wL@;5I!~ajM)S~Z zlM1N?azVCT3nU9WRLiB%PSN?3c^>Q%Jvo#0Zq_ted1re_mr9YPXD`XPwAAcePQpIR za2EDkhSP8znOOPyeLbmC^wotn-k_30zLBLaG&ix#k-KRJMCNecZzfrq0_WY|!khEt zTidNF`TTzy6RE?;^0Yk2n^T9gyq#tCI1b?sCbIM83%-vxkCn}Ll8l>_nJ(Y0?&9qe zGI)~St&&Ij5X)S-XK)Y6(j+;6dr8w;r!C&c1qHgN$3}#{`}~C7!R2?K53A%Co}X07 zZ#h4ulHYQET4iCOzD)3pvD4K)Ypi*D?>S@5+j~chou%;e#+tYHUNF|Yz4xNA=Iy6^|d+!Zn&D(o#8f)I( zd&^k!_TJmZnz#4fG1k1j_pY(#?Y;MmHE-{|Z>)KH?*n7a+j}1xYu?`b$XN6C-p9t8 zxA#6V*1Wyta*Fy3$pPsG$Ue5kII*;GMW-JdsAe!qB%jgaOIke z=0t3n?3~Pk%&c@-@@Qtno;ExuWo+ump*iVUDS4R%JXdLk@U8Dj*?Hs0(FBPtmzF{o z(NN29lFv+nkKPj`d-}cvi6NS_UTC*Xrj=D-u?RY9n_&GLBBpm{-Co0Fm`L5h1vvw_Mp z$ODjzRT9I=2#P%-9_%W$jDY<+apz)6_Gj?2_e*?{c*toor`EnDV z#y_^Kn1FhB!O|-jiDo-1maF%fD)4Wm#)+ zl(xdkojm(O(++FP^N3p7+HU!9qs`?SxmAN+Lo@9hkL`gGs1&X{wX*0blCop*a%Xm9PkDbFKg^*OkQf6a00_8u&!TeyGWx9EPY z@?iJhs;?u-8Mfx69nJAB`#Z)kQk!-RtZdqfHn?2JF8cXq9~Gf3*z>{OyR`?qo~{19 z7DD&@*N(5yc*E_1w-;w^cdJJ)R#R)?ORQd5R7?VIao_4(znHQ|%2wQ#=E`2X>{3-$ zj{^6^F$bQ%iYl}EtNXH?Giw@sxPIC_aVoptR?9I7)-hs7qWcb=y}{czp~BBU2s1_v-EeDhwc&C^3V0kUM;v^ zp?%Yy@JtIXk7i5sZG@{~jcRB=kN=j?)kXKgeF*GF@wW!HVz21`3tKrR>&NbywWatG zN7F(yd5EUn;;{e3>gyh_)!Vc07i=KtIKb}DO)w6k?$OW@o=vSE#dox>Ab0&{r0vw_X|;3MGg zawo?8c(4AP(Gywatn!bp*F~$)t z^@;siWBTu8!d}M%zn^PgLd*1gp=(j3Z=Uvd0p+c43n$!(Ojy@oCo*w7GoeQoUyE65 zO6Zn~6HxeDGJb2&1F1osr=t$*% z=e|$0t=YGZ*HHIYM#nne*iZj-t+4j?Z`3Epk?{Qr?3{`R5YA#^72eO7y$ zt=vj^UfAD1Y{jhdT%Z4cV#`1GOyxx8dDihy@T{}8=oM)6&d#e<_kV3maU(0L-oG1T zQ9UcF?BDG*viG8TU)(ZezkijnR&(v6)2~?vG}*Xysnh&Yl&Q=J|igSv~)EWmjlH7ny%L zkN=nV_g|bJ|74&4FVBtR6MIpkWql{qJ^laZqPZq7Do_7zJNUR*{X9N1=fBd*|L(|H z_`YI#PM?zJpzK zbtBP{%Ky%NAK$hkMe=W#2S*$1BK7SAtr;r*u^%ae+`jI^IuF}h0#`zN>k00EDK9#9 z*60L&hW=GZtJMDc?A8|kJi%Mp_%G#$=c4n9$lhiv9pT_N&+Tot3Ou^)-?p(c!!4d* ztTpq$oDCjDJv-=#2D;-h-kh7@c8b4+YieIv+0L4Yb{smBBR%g5ZUuLL$NoaI&s*$> zitB=NZ}nXB!x0~^Ek$L|+J_yDJwB1@ab3IKzvsBe_TH_`Y0v(yvfwP)j+O1WFSaXg z8OLU~VmaMnMH^afk4$J;QFZP2Sfi^~6s>=UnEPtK&l$=G_c&Z1bvvIYwN>`kd)%xo z9}}Rh?SW;%e;e7JE%v#ZX}9e~6WVUzf5VTM?jdjt|LT^&{f5(4f3SQ<*Gh1k;hf!r zz}Ver&PVV#*ju=+<&+8BqODow!7h{z-4a|Q*oD%eTY_r@yHGlGi(P}WrOwJ$?{zxqZw-@aGTdmu@ja~)E9qM$8 zHM5E;=d$9gv~Kn6Z*a~Q?cdPmde)Eqd&brl{?x79_oDNntouB(%UE%5ta)Ymz%xlv zWz1VYNPI>2SxdRS@G7u3_IE+MU9D}!9d5hb=kT*2_=wYXQQBUu!behcoY9xMXU09! z&}jbMEy1~t?9l93ISFntG}hqqU>AuFEl0LQw~t6Pvd81k=yj5nV{Tvf!CQ{c*1%Tm z_3(dTs}=3>jyRfjqsc=w?G}f%*J7*o@!#Se@87q-;FgQ}R$!lJtaJNciQe8XpT{i6 zpW15pExJxv<-zX1UcY#2phnFzCwTVoncO{3x*w}NIEQX!+^*YMUbkB#h&%1ERWF>g zqCv7!R1SiBkM|NM?cCsXY?76o1H>sE-IW^BuAON+qN0`EZ&jghi?|V1Uqa(RwrDRy z&&+>iJt}^Wf@`v~{?D;!Jk}Qe4BcvP2^>+a`Oj?$?x~JC_xE_L_Ey~X{L;Ny-(iBC zy>F)qUa^8*@IJWAuFdW1J_7R@+#9>xt{b`sZ8LPc9YJuJ&QiB+f#+JS9enI)xmyWu zv-cP3w2#5tBlUx`XXop$D7$CDBZ9l&Yz5aVsw_ALyB}5^{tR9tbOu=E_I$82XlKH1 zFStj+F0?JXUT~S)h%l>BSm(y$?LvDS9HI7>d&)mrracX=8SL!2YDXKPR{W`h3kzfZ z&HweNR#>X?mcky@3;&4e(fH(y@>LRIYsVMv|3HP%ko|N#`G=xlm3VA zCap(_RBkwpcC*I6oAe$fGLqL@yIIS-86mr28SQSCQZ$84O2kkjh3C=-?@m1JvUg%< zZ_h+;_e5{EMDL}ECd$I5ge5mlJT#|WUQA)aX)!Uro{95jepRj?|Hs!oanH>8)k)8; z?(0T+8S9zVeV3A6&U$)vO4%XFQDH@@-L1jA8MXS+Pq%j5Vyixh+=XVe6A6lKv4U!^ zLAA1iVoyO0qM!yOdiy7O`}!m5Kt&X-MwG}A4X`6>Ox-UR(~qO__1AznDqmj>h@&z+ zA1poZNR3I)*%qtky{H9B!Nt;H66~qx>D2SoL~lx>cW9z_h`;l_sWkb5z~M->JMT-O zURuL3RC_POF+_VGc{nm8s6Mn435sp8f=ZzlD3*Z|3kmiV)EEkCbfPyi(L2H)(QqoF zXak00v>j34aAaygG8`i`pn%~RD?Lx8#-!(Li`DZSYJobODIF%ko_ao!dR~y|%}ey= zBzm*`ozJDxJnyXU^y)I}N#Ik0EiT~FS^tJC!AF@;rV zC1^}*Qi*_5AM}= zD85wzW3nQ;Sk_4_`>A<}g>A87xr17u5DrKPB-m3d*HSDS6TR#Gf%s^9a3CA)Kmx~P zeROebmN@RD)+G+M#fsxGYJs|cpLCxDdx~Q>#j!KdyFJmn)gQ{^R1|!K@3celZ4Vfe zt45(nF2#qln+K;3^;x=(^V#c`10xHZvxbE5Yqe<<%M`o4aAKp(sm6~0c_q8H7G zkM-TEqcSgMe)VKuB3)N)s@|qW6$LK|d(>qkjBEAHfN_S7VzOv#fgZLjei;naJb^9SM5KPEg=9F>S~h z?T|};e&Mzra?j7NROWlo&d&pqpWkS!?f@)JWJk{|YzpJymPPbGQ}Cwd?E zr|2X_%jid0`Upqh!HBz*(el($v;1qp8Az5?i(|{B;B{KPw z#NgHVQ#(aIQ&Hy7dzxp-(K{|VYQ~Ly>Yk(KROb7{&e6w`qZYJPa>TY+IqE$Nr zhvbMo<>*_=(btLIFZ~JXs9Y!g=u98M3Hn-NlR5N5K!Umunf$#YK|k0D3Ym`$1 z&uoLK%vU1Ge`bqG;y|yUt&%ae#mZO)wLlFGqYud#d&*csQfF^ml67}wghC_rBa=RY z(-oJ*LDHH{k(Lce*C-;B%Q(_i)=pR8bTVz=*&5A_mvzrp7M1zR*x5QsvNeXbO19V* zD_aw(1nI zvJ>Vr6=i;%rdh``b~U$N$vtCJsmxc=&R7M>*fiQI8Dm?lj4h-VC}XqfLo&vmGFFu` z=JBU%kwT00V+nl(r^^#Czp4kMYblY*)g0-nZl^17ewjA#Y%Sx)tGj1wIhFaU+1WZv zvbBP?O19V*D_fhX1p3k7ARx;=tDBb zo-)>mGS+3o~?sa z=4)bStFdJ3cG@c0Vq2_iJx?uAww|C5$rgLc)@78fu1VfYlDu7#yq)}Mdx1)mJ0=C( zRPSoX?z_ayF}|tZ#Uzk#s&^u7-Be#w)J^s764Wu;i3G*ASV6r@El^OeN-QMUQ&9aV zs6I*FUP;~_{)pbAB8oQPwqYMTqQKGYr2+A1`g&+U0k_)vOV8h@#-!(Li`DaQs0Hfq z$I@XE?5XF&sOMKEd9O(F4odP4@OS=ODh(cvEA7tvuApA>DTRk)koI2g;ttT>%U#^i z;b=_HI7-k{691Eq6bbDI+LeUHwpgK+ij~lQvqED}p^c=_GLpP$N#5c9xJpwI#T+mw z8FpNOgOa9U$)F6^umT1pQ+ggpjY-eh7OUrHXwS<^hiOpQQ_sg!&&MTs$0T`2`+I&S z6$MYHadyvrW2lQXBC?i_w!0pBEf^DWFE>YGsX)z3ENqJvOLc02LP(SlNU*0^CQvN- zN#0z4AT?-va3J}1Ab~@W8(ka|C61cZy2Qb@SaF<3El~H9rTZkqE0(s@0)@~_LLkAOVwpp+%u4dk@CR}M zZ4VA)mK{jon9PVSj=2)Yh19yl!M0d&Tt+QW_d7}VNwB9lmQoyxle`O)yz~8`bXT;8 ze)Ob|;PdZd9TmCfvm)U9+l$ELTx{OqCp>`LN+jwaDo$r0OPXl%rcH zM+cI;H~JGaSGjrmF`qty6LdghlR0!SAVCX=Ouo&Lpo4aT0_TuvL-KQ@OMVt|TL<0q zvxv%kx7qo*Rr0f#wn~237ArsNsRhcNRDu=C?H6=ee5rAg)l6@8w!?)hxy)*o=s*cK}D-EU{?KFQct z+A0}iTda)jrxqw>UIvkL$8;MMQ!jZ1S zcDe$mlW7Cb)=k{_VfSnupfcYRcD5duY~4&-C0lHZm90b60%hwUeMq+0Q?_29Y#mAR zKI>1|J<8pyANSEmaKerR%&%hs3A>-j)B}M*8|-8G53r;NM*jG zcE(lkg7Y_Tm?wrZD>Yx57rd+HJ4Sk5=o^UVU{uYoG+R2f zkBQMIuE`!A`f~}EtgtOsR$5aF)KCNZkgTw$tTdslH1c>Gc)aI%y!AcadLHjN{=~E) zCb^j>`DBlNmrUlwGzv&egMh@G7m%3xc4F$;@|+@bB;T3+*|~^z?Q0g29o=GQr>SJ8 z9l??vw#CX$Pild()0sXbJM1Yt?I=4Jdc18t-qs#(OOLm?KQ+AwpyX*@>T+H#wDS^p z$h6h8@TBpz)?DzU@wE)l%{4JRgUnlo?Io_>v=fPoZL#9Yq!uWyVG<4r_7qniiffR^ zJHX@Z@A3Ba2Q`XH={V7#>T^(o+=CiGn`iPjaSE!xhvt7jiK#Db{<<7(_Q!FB#4(!M zl{nZID~_4e0(F0qbe{x!ien_jk>T;CdA!3t-eDf^mHtp>5s*B}aZG2}(fHCR=hp3= z;W|cgduNzEU$4|*33E&b&)0dhKi{a3`Knv&`I;&Dm`||egKe?$v4&cpG%TSHnXl|A zAGwr|@gDCuk9Um6JKCR&wNy&E3K-Y%b|wNR>o`q>jO&S1_7uzl3TB?iJICXl*d$-4Xr$3fN0+Ju`Bqy10ZLWLM>G;1Qu)TfS0EDjVQ2fyD zu$S)B<%iUwTM_J$3aL>grD(?++gD zcmCc^Rdkwu6w(JDN%jlZKbc|Umt}wV*zc)LCo=gr4_(S>ppAHf{%!~AGZpz@_5EN+ z>ido~-4~Em#=1p0gB$zZL&*t!;d&;O`F`{GUrYN{ax{y!N{-kTD@QA+1xn3)`jFvd zPdPfNN@s6;6>sS(-q>1_A}f_%r61SOM{t_rtLUo4X)0I6PSa{4lgm~KzLF|e z#lDkbDoUD4QzLXIMHc4RDsm@9zD1Ux?aq{~;fBjqaZTA;D)W`C;!jzbDjexL+A1ky zTdb7rq!y^5Yw1H$#-37kCZ()=74K>OWbIOJw|?xQkKkmL*Er=lL8X9X?Ikj~VwK=I zRmo0P;K5_skX)VSlAnFtRweiR?58qcMLRzgBtO^DR>=?BV&%t2El_?A(1+xQJ>{n+ z<)?ZT?^#v6Rs1QsQ_;KrA8Y3U7)6=)|J@J}5iDRqP0Y4zj51t+glgH|8-nN|9tKEA z5C|rrSy7OpXF)8esDO$n*z2fR(DSTkJ@ss7ucv|{qFDal-!rq%JTsXYW#2#V>plBC zzy5iid8X_#D9yuY^oU#nqG|!rCTRM7hV@i!j!5;v5FH{crwS8XkC5MLb6k%?Ci^s8 zUWV&2j51u*EeY3q@Bm!@M#FGXAGlJ$m8g(n6;h-^3UOlpRkYt%nh((Ei6u}KT^G<1 zm=%b92u**cLVwAd)riTeAv*$N3U-DpA|MNyAp3|MXU&m)44ItKkfj;2PcX`mQMV*y z-@^lteT9Z0qdt%w2V}=qNMkCb(VW*dMfC@z*^Wlf>sX~!b`Xvic>M@X|6dKf#%sL9 zgHZLsaE%dgjW)rxgZz#+$Mq9r@?SMv$1_|%W0c{dZb`WI>A`UIM8j}VAGoFhS5t*F zxk75JkS20seHHC~O0zE-J+UTKRa{}y1Y-L^)8AU5zxJM{5tCIzw!$VW*cq}$0og7G^;|I$$9w|)f%Na z6pfx&yHYA!VRHpuwb1m>G4PtJ@e)^<>Vx5$CE%KAg6lByJJ%f7;gHF5G+eV8t^pWj zxTsqau95HnT!YXsT+|1yMZk4Vg|whTI(30V#vfGmcF zA)`K!EeEoTDx?c4r1LqiyrNoAn$c+Vye?8oWh?Abf!8t6^sg}Rx>VyOt}xXH!*zjx z>wFVjW61BN=D5Z}Ca=(NUBYl3i&2J)x+US73=hCH9u31qec)OHT-Q}d*HlPXS4dZK zVpA0DCZ%acqbGJ9sw%Fq8w6r4(DYwlq5rPq2921k8nP93je?yayIMeYr3tcWgJxys&N2BMp z5eV?T&Qixhm;Vld*O}1t-)`V_hsH}>VX6;?>y`@s-Ozey7rz@S-Uuxqw|AJ+IvX2Ods)LLE;-c)TXN3|#GV#DKV?F11I2jRoZd#r8E+}hq1xIGC?|2q}>M``bB++@{| zExXqh_yjIfJShJ`4&F6~@)Tt9I~tU?8I*rwltH0xNl;#a2S9lq4TC~`K=}wzKHx-N zRg_*+nt!9w6Zt?`NuLTtUWcat69bV?H6r3lQhn%vyg~M#nge+gGWin?$j1!Ge=y2` zP`4x?pTGlvyoZJXp+10o3m{)tNMCU#pDKEvDb43-^h~}MR>^k)lP{p@-&&!6aQB_Y zL{<&iD*4J}m3&DKzB7mN6=d>O4ayb<<$oAuP^eoHlpo;%P`09BP^b?mI{;-nC$d9P z`blYiMx!UPU05YM1tL44>Hpb4WT!?%TqUXx-75Ko?01?2`4uwxXAQ_t49IU7Wk9G~ z5|GKeF(Bj7Fd)J8rS@cQpGsvv zq2D;|h0p45oRsgIaTb^RXoGl9*(U3Ed+lFIvosaaSasAbsk%;hfTQWGD14wksyhVL zRa8m`RZ9JNX|o|h*-B}{sk92MG;!t*!f^42EB&?4>K6%BEb}>V#xkdFNtrK#2PAwN zOBf%hkIZY4c}=BMT`74hB{xt0TuAlvQllj=R}1sv)uuq37q>QOGB2d3`};_Tu^N{m zCaaOUCDnKZJfO6TSZVk`ebhJ@HP%&111qHgyug(Zp?G0->a+sI*%_#mLW@rxpnXJk`UyHx%U>Ra zMCn9K2hIp>F63dA?2$GdIt|*e$rQ045-C6S3$POJLp)X@bxSJoAMk+69%7Z@1NBj2 z8YLzxrFf+jt(3x*QjnMU6cqF&CWR8?LWxnW7CEey7}SPMO6;-BOGEShQ8nRPmUctata8~=wFRtDuXX7fd=(~RP^A2S4v6cLLjIoT-yBKARs9O@F zFW>=aK19RL64VEyzk$(&N@+X?^rfQrmD2nVjULbhb&Bbw1dRfquc7Hb$pENP10){d zst?9zya}Ig$XBB|pKl?PPty2IWPG+@l<}c%Nql~V2k`j;4dX+7@R<%i(<-HwN~xJ6 z`b|;&U1=OWjfke9q~b++n}Em(P5;bF{U+F^A(B-?wuV|XE^@Q>nXjQTa@Jlj1hH9V$>HNz-SLNj1l$0Xf7Ddu9P}Bpni(pzDlzn8vPoYt<=Nr_D&T5 z?GH`=d;_3UH9+DTQhl&B)M3Ks0P=OJIiLQJ$@4Wn^BA84G0ON*wi}R z!Dk8hoLea^td!2Kl+NOm4pX!bSDFE6^pws;RmEj=o(3E9!`0A$0^ zFl5vRvP*&Nl1k~~O6fw*E1;+bl_rEn&+8JUB(|!q5O_tP>A&2->k5sRxT;hiY*k$> z;JVNRSB(5#VU8;fnS8m1>oSHbfl-Ewx+UQn2M@rNMZ<7WAGmG+uCPqR_N@*1* zcATPpywdy?jh@(AR8?GIHwnbXL({*m5?2bs3cE=oCaZ>Qg{{`m$kz(UR%zpWg`Gf- zZ!$+V0Wx`=hU`X$>_m(*WYjGQ*)(_nvPozdGU@}_oj`VbrF3hhw1M+FSy7#?G&9iX zdEKs*#8%in0CvGWl)|*If+PDHvtA zsJpAU3iN{LMR>IU8hW`7!$p1I8d(*ShF3{LtEBoWX>e8XZjxR=<3G4cStbG6h=x~b zcauY_l=Vdy#r637I9(uba>;}7x%e&%+ZRNSs-j#LBM2*sx+N7wuaJSG^H?qTKz$Sy zLQ#P#>8L8{2wu?&h)}IkQG_ZAXcdVQd6ZHRRV5#x6ePShAR1#trb-%JCFOZVcTq)IaXQ9m6^YX^S}BN4M_wsN zn2vEQ^Sg_gQ@5ndH^T!GmRZ91Kz(F>5;Ff=l{BGB8eb(H&y#-wQvV=vI{v05FHb<0 z#pxKYWY4DKcqRKko{mOV)RPFprh~dA74;H4pq8guE%-ov6xD*FnyaKKRnjD0(aR8_ zTH)wu)+!RGV~SD`n~q6JLBe#jvdmwBGnP4ZOUnE`ctFChvxM=1`pEngWZqUK&8U)2 z=9&K&BK>jQre!YAK#G_P`XBjZE%mN{*|_TqqT5+5@54Q-g}Nox@)bOwgpXMX_&|Ns zG8eVXu97-tHt>{=c3SRG%(JFA1bCDrj0JRtq8EPZ^SKI&M2I?k+; zPOp+q<)!=#k^bO5Q!7P2U6_+ocdeGQSuH!^p4CF#l4|LRzlMquoM_m|kou@)F=|;< zC7r_y*&XBhLKbO-h;wqzuGO)G)zJ&ySsm0ZsgC~efI9YO>Ei?SQO8B7Y~ zFNI!eqd&qg&`Ocd7v^NyuGMletK}fLXSGnbq*|)s0VN#5O27x|qn681%Ze&#IWNSI zaeW~xv_ix=S-xv^T+ZsKfp=C1bxW#a2s|MD!&&mTDE2<4j zL$A2eUze^@W`+F>a7~r=&}tYo{j00=yTuxff~*>{ZSN`#gS---jW2o`PR`a;fn3*z zRwE#jS6A_eR@X5`BQeStQMV*UQFs6vdS?$i{-_T|H-phlRnmZPBkGpKNPQX3$#BFNsV~F%Cm8*s zN_v6=>VN_OS-uJ9A4+X(4LvIWngcukGX_ASGQ48+=}^l3uQoUgU^`m*9XDz2Qc`hF(QU#WnP%farWe z^hT9_H-1w?B&&vO4ZW;zW{h4mVMH&y@xN)#h+camzo9XDoiVx)qihXPwa;_mtY$8u~~8M6b>9e`o;okp@UyL#hwP=N%J1 z*OIS~%=yr3apVs*J|8eX^g%sTaAyb8nOlSxdNF0*N|2CQFQ4QIQr%Ey|A2i2)O7iIsP9FxOQl`#O0*=`17>b zi*c6D%3N-!QT>6t-xl4PJr5dvJ_3N&#FM11)zuX1tU9X(zy*qL@ z7r$~Ub5Wu6!W>47x+M|&03P7zZ8VG+^+Bu`i1l<8pWc0_D1D?fAEVLZ>gl3ofiFXG zB=r$+eF9B?Zv(DA8ZL2tsXqSv`udcd_c5pS8Dw&Ajn*EF*5?>yw5VGWtsme4w7x;Z zXi*=u_6MzfT~c2TY`dcOqtfg^qX)JxfED+z0|j6|LDS#gr9S~4r~#8zL$<#9D%Afx zv7gENf#$?^LMHduh#kO){en?OjJhQe>w&-c4q^`W*Y5Fw`XE*XVwD`%Zi-S*rP&>g z9#^HXzB~f1UeNTr4Y)iSE^&RSKK?wdJ;=GooK|nhWVc4k#c1`xD5FK)l4uiArIsBZhqtWm6} z0SLm1qHak=4TlF5#or}GeH0Z!Q3029luJ5-S2Thu8mU&KJXF^z5@+)$r68J3`3R*T z;jv+uWj?Z)Idx0QJg#JZ6iXN-P#>9Rk$KuBC0$b7B}IAi2}t$Rk=BxzlgN?|d76&6 zlD+a!UCEw3#qByBU49CaW2L1LicJc2ODb(VJfI?aXB1m$)JJK@qO>tCX|zkq^SVxe z2sI1Oa>ra7p7` z((ycVdXtoXIZeW0UxN3 zTBe|uNiOLmUdTL*>kFBr6(UZ-NxN1@6RTrByt6u}TT&h8!UNJj0}WeE)JGjNP{+wG zsnsP-<)ti!NWYp+)=H6Eg*lnJYqiW|wJd>qRtt4Ys^wC6KrI)r67YfgsHFq7oZ^z& zcp;ZzTwlm3S|Q?`wC!3Qove<_;hoh%-ID6K0UnV4DwaMzP#<-ijyg_tN%LIN9A3(e zit0M0xe1N_{Clc0E9|-9S;F~uJv9Aiy7VjaERBM!8nQ!do`yl5gU`n2hBuS5v&_%8 z^s+7aOznJo24l1Vql^)COJZ~%JOB-U1sCyj37K=&(p4=4@2ic1gZT%|U4 z0eqeSh+eMc$KScuozl+J0Ex>)^}%+}g(iF+B46j3^LZFDd6~v%DdV#Vql^!AOXBkk zJb=&RXxMR0eek&qd{(%m+1yp*Wu9gKX1VGf`&_6U#gEkzrN@t zZ~hm|Y0)d*sk6MvMBO)z=-9_I68qx~1N3sh3;o=`KDk zqgPb<_jUWAMqMz?~!@wxbOw_a}g$u0c_54k6XpC+nX{_G2) zI}ugh*KK@3v@)W-@T;GjikS^%wuY!%5*2#$6daw3hEbtDs8oW=!EWh5w{(D8+K(fl zH&TI^atoOz9tUeY#1(O%f`gdI2Pim*iM*e}gP^E?zvmEE$hmOL3ZZUEgkV8?3-!1vvlE*E%cp=w8>OagdxBf1*u)BPpFtr|SYF&RgwZ?bwU5}vhVO^$H z8PTS;mJzuD%8UqgOCoX?Jb(zjaEcM3K8VzV$Y8fr=avS#r2(AC-H__1cCdy+u0yfK zd+dP<51L!$@1wDq9iZS4X10OVaS!~mI;dMx9go8U>QG)Zg%8w69Y>;$QEq93TN=iT z*bI@rh*4S*;`$t6TEnm|H5|oic%oPXbxW$@6{Uu!S?Z{P`lum|8j@})?v|o%DeRVl zypmU;;Lp1KUx}MfQY%J|BUieNqRl6&RKuP_g|!tLRLZf~eDrU!egpC3Y?rmEjA&~! z!+5+2Wj3eOEs4kH@Bj?-zALsisSh6Gz+s#(+)|Fi_ySU}61JVO8VPY)k5NFd zZKoh?J2{1fusDxng?tIetPtv!R7f}cbzT%gFLz>vP#=X%Mj?%EX`)*?(Jh_emj23X zDTji;$?e}wEr*>|8ntrdiO97$u_r3^u!%iEo7lf9<@~9M?TL7DQ8NyG>ixJ!DA+POm|Du+)|5MYUVKLRZd_fOzd=xggCL&6cB7;TZD;i zR!9gF+r|nx5RO?P)GetHdVv!PIfUhp57b8?XP}VN+|qovG}kT7c1s;@=@ecLdpXlt zZvW5fL7Ss9 zY^E0pGkuQmd4U2(nDz5nUGz35Ru^?ks*B!0gmUO*OlblIlt`$OE%Y|Al5(&$>PD0vmKEH2`!l&WYE(`|)A_i|#(YhL4p(L98d*LGRF z%80gj*Dx6Kq0AxHQan0VK z&8>P>doxRQF&wZ|sasO2>T8J3E2c_)qXtU}Z0S`+{<{q)mfN+2%9jMPky?~)F~s{)cuq3kfF?Y zP`4x=^s*pecmxfbI_iVR%i!^%TYAAQJ?EC5;V_Adg2kN7cw@}ENZs~Qm^ct_?4Mp`$rTGsU{ganB zktFS-^fK3X-P(_n-iD_C9XD>&6adH3&hxGYKvoUOT7F$1@S0F{@ww-_)qBj8n&BtiiWK$oEJ^`bT+|mae5WO1+dS5HeH)!;L zK2mC9PtrdZ0BwP$|1$%i&ow~e3Q>Kq%ZU$6_tjCLxh8K$3v1L;Q-WP6h1GLPw!+6yw->ETPt;h`Dc8>0*vbxT54 z1rKm^02+pj`ass(6O(#*q@EtBho|`1&ZVfjmBxcc&#RY*s#JdDwwJ)m3r+u?23~t< zyu?+d`e3+vdf3xG_7J28d}9Y@`%du)^pW4a%yCsiChw`?>cepPG0JdJw!0br{2SJVqHV>XwA786JS^L^KQ+^?_>ya1HZF4IXKTM;gS5(QCn=-J&$DX!OK} zp{n8vJ3=6KGBo|8Jo-m^M`*-k)sU^Q1_e7qHbg)+$OPF8a(sk2vYC*{qcmhA8L~Ev zGGx>(3E2{O0EDy9Fl5vRvKWv>JW|Lb1voEyQ5RH~Db0Ck^t>WUsceNM1zzVv)1UC* zskd_JFrF?Qk^(Q)kTD7gi~=T%{!Y%4=8P_YOipNw;*8OS7-fv8TN0zI;Q@uOK*JbO zAB@I;(P)p9_efdJXqBRRjnZ6;M$c%pz-XMn=sIZnkM-ay4uR1)fsty+807^GPzwt zb_zrG7)BW~>XwA;1$aR9$_vr(f%-sp29TZRk>-1(xt!O(6xA1%<|QEz81;ecBH+5fBc1P&mU*Nl9_d^T?PJB@6Q%hSjUL(sD6F{1E)k%822KBRkNyGL zB^oqYHDrtIe1$xtwoIV5MEHEJ3Bk`P$R*|kzkp0$t`WSL5u|sbF@n@BiQo=+06}_r z86!x25WE%yS9zqXJkm;!bUDZOlcN2z((FW|$G1wUoUOSv0={3M>0fQYw?@M!t~u2Q zqj!}+Y^Ct|aua&LQj9g`^ytNC@@kFVb&THc7-jURTM|8s_m15Hdh0#XI?nBn-aED) z^%R%gtpYdp-m#4y{jX(f|(tLa#?-K&THOj{?XhkMs~{GE~u{SB^n_ zI2t{ZO~NYKEHD`XP5B1 zLgqcaQV*|G?kzrKyH8QQUuhmdqu)V#dbKleAFuXMQii6#w^zR;`*^j7lByxwQ+vP( zp4725S+0HNXW<9QSs(hxP`f_ceh4zTx0gSN+=DTC7^934bxUIOPj~>D$I!52kNRM= z9~kxXO8am?Pb+%QD9y8I^nm&)^{`92{sN%qpy@xr0I0tPNL&@F55{L76F$$Aum0wI zUVuzKK;yGNrGeXHngQJSr2^neB^^{_QGNC5ObH2rm6Y&pu#(oFmQ zAOVnS$QI6FCQyDL2ZPL^Y==y))1dr?LHQA*3<`Big0lPW42lB{gF<~kITBDtd8H9v zX_!}P;Ana&+IuKXZ!~%|qfk|G?F0lgdqUHHv{!#t2?%J4hICdLq4K4_Z9B}%p7OKz zx@*HG=N08^R_r@zOmSZd7cd9e4>I{^4dhV_vWOf#Xro^iMEwJW=B)7Y%7Oj?;+AV>OV+Xu~F}QMk$}ejgR0peLH+3_~VQ z&~To>a7Hl7a8kDV7 z9t%x>tAXV-jitCIi#}*gPS#L1?kdW^Qp{=QD91x4w`wR`7|Ihc%1}~wS5Yqa=ABaB zSwjdV;QJi-KJ`i;d!-M(()&e%1LaRyNkeGEa#Ri9LV^E6Hg!bOq1=mnL8F7lcB^IL zA@KI4SAHJ=7Sea&3wt|U2OY##jQl0lFk-8hChSu0rlkwF^>!>c7pIgAx!a#9`CIyL zI%l_Tjs;6-Jk10=&e-x=SdZH@Le+@xy|~q4$*MVfhJWXE)M7aAY@m#X zvbn$2;cx^fDeB>coWV}jiuPI>!(Z&in36rNH5c~IVDlZ0e82YUBJ!HPW;Jd5Kh)H{ z7S?0S^Ue_n^Q~83hPTM>TNdXBi#Q%Db{>sg_gYv}oFnv5^UfnNd7zbd9>pMS>;g%n zr7Q?`v#Lx0Af4wn0y~_1D@k&2?r5#>rdvT?v zm4!K|!AG!=deB8Q^VH=Xf3dlYN`0U2p+i;Lh~nGb=z*q@-P$aLC~ZlG4aiXmu^P z37%Na)GaCJ@0FatE#^#pLyOAH5Ks zr6{k&=e6{CYwt{uX^*^y<@y6Wuw1FTtGQm}MYSE6aWrjc7+>lm*EWAln&FpD_80kf zVq8Ai&ws|N@}1^a_+CnUXZVYJ6-6YBzm%!*o#m%cv*C&5Ox-`odBGhh(6Q%)zTL+4 zcI=feJCfc^;eYjW0Uj)FRL8m@{h){cCxa%L#8Y1CzPd#c7w?Oc~jBy zkIRB7ve*M=tSsu5GFu110sI_@hRqiBQPxQ)tE^daG)uqn$_|Fe-@VyiHGb0~j~fSV zKUDf#)6#|XwZYl_W`X>LHCR;V)yQSdnAT(QAI<854Y;?YKQ!R~rD?#@h0AIjP+V5S z@8T=rTkhVB?VlZEuHkz$EBPEk0!Q=Gh4-)^j+(^_f9MS-it+%&Wz(K3&VO0WqJ>*s zbvJlEa}7o~x`%U-3oXx+;9_fa-QwVl-r>E~C?2Rl(~HL6qnWBvw9L(L*1yq9o~xlx z`7Y3%yUXZehK7|7Akd$7HJhZ%k@O0N&MnlsV2gsy0k9u?>Xt72Kt-@<;iaUkTqP~= zQ+XO83oBR6ISW_!_ScW!1S*aNS77e`OhQ{-nE~hYbvXv(f2iU^|7697{z1hRsQAi1 zTd@bqR|yr@{;7&nyHqhx$XM~=rWLb`Sej$y1E#m98YY2 zCp;M}qdHnfbqHaz{4((Uc5U6-zHilz*t6MAGplJ1@6+t4g*My92LGuV2=hlZe|+#L zVC!%U3_ytvzUw&Iu0yM!czg``Q*jl4L*UQZpdMKDFdW;x7Bv9RQ0kP|Vs}Dk7dMBHdZ+A5$H*iirN{0RLXiiXq2jb8?0$JpKwZRuy$iscIlzj|e{!8deqc zQPnh5wRNiWEw8E$Xwpf0S=IAo@Iy+)JLjqNOi|lX**AKw4ygg5$~Kz)8JtDn|iXJClP7Ab-iW~mxR0YjgIFxr#(RS)p!+%%xkA*(l z=z?^dkNlZYp!b(!wL%9K97mnlgnBNm5p-M z@ZFgq)7l(8j#{K)Y=&#@QYB9Th+lPwYmFu_D;alF9aI*Sb!}o7dk~xEd_GwXMd|mFw zHcq;D!w&pzZIG@_93%TN9%sS=`yCvhs0HZoy++eHn{e{lfp& z4qm$Oy;?f&vG=Nb|Ad{ZW-XA=8K-z=VQ*3Q{Rz`l7t@Q7J57t-Wvc9LK`?$NR#r~u z>p!l~QFDWGF^Z>A2Li?#`l~7Gh3UnACakZdupWeESA+;#X$ZSQnM#kk381R<$U|`u z`fD>62{$D(*`n%4BrjDQ0ccqK(sCQw}o z#Do`9M#Y#qA3(Q)gYiF9CB0?e?-dwh>?(|n?NN(B=v@7WMV0L_y#7xY#TE}MiZ22x z3JzFNt0S`p|2}2+|;_ccD7V{COkp4vg;}qVAF-##Mq1tu&y7t8~EBYb2>h?d( zx-P-Ot}b|Bb=|aUbqU^eOLM(RT{kOrArk7kh2m&?z=1g4?w}30ZuoHQ6Ms07P_jD` z#fh|7weY|SrhkfI7gud@0>p`=f4RYLShlw+1tSs)z73t)5$xmb_^7VnJ4mIw+M!*` zKcM9ZOe_@Ho^vF2C;HIsNG$UV+>k-7vik2N+wzgvXlt=!vJ1hxF(e<1eQ$MdWnU?t z&h8;Wl_Fq3ih_H|37y*ANKHGncXO`jU*&K*`#AfQ?N)Ya|B3loovm#%JH~XjwKq;} zax5)#^elIHFYE8<(apJ1P`%Ph^(v-1=0L@((^)vsF)`RaHPhPB>A-2eTX|21)3IO{ z{<5gknS(6THo0*+0&&sqc&O@hW*~~Swa;i2t@dW36hvb>+nX9^2v++*)Tazdp1>m? zZxeZ(wfnKQ?wh&$$u{mAA+soKqIKjGZ6nX*kx#aX+-mK9s;&F^-2EII_nnYg6xMDX zd6sSDvw7q*Z6cp;?fz6-_vdl3#}rv^>#6Le}Rqr^KE@x$$eaI;5+GeuItsn{9pE&wbouoyJ{OE}YIg zAhOt3oMjI{cuZ5r?CG73#ZHH_yd1k&r?X7Pu&}#1vAeBt^i=jYY(|@TN{?E{-DDT{ z3G=v5+Q)r~$9(~c7Bli3L>61@GZ0y#co{+y6t7^|2F2Svr8lkPzHS%y9rL*F+QI0C*@zEXn|rU zM5ZYElsU_s2btDehGCm}cjs|?K+)29FLUR6*gM~kJMRlci=y_ni@U#h+ym_69>U`u zZ0Een+_}r%`C;674HPYkssxOH~U>&=}v*gMa0=V`s7?wT+OnMJ{I zh)h?H(;0=x;wZ&7JdQ^mV-tC_wfnrS`$q2mZ#M2HKxR?cc4ci(2?egYDGE9n zKW-j(vwhrWc-*J#oIh*s{5gB)|K`qLfucoGFWJR?-8}9a_Hp0iao@Ic{$F$F@7p`~ zA6&d_@*b>PO1krw8#0T6s~|F+MW?e8qR{N-=BD;=+w7Tm)=^e`LgHr6Iu7P?;aP`= zJ?n6m)j()m@C&>U;*{6GlO7B$Vg2ipu7k`X>46YgBs~D4Y~wuhj1Pm*uA)P^+@zwR z5L#6f;uReYEvt%-gv=uCQ4m?CJpw|zw1;tdm$X590?%zc^sI6_9FHsN1`%!1h~5SeC1SA1_lXjS+JJo0-sk>9a)kL&?M#F7`91yKb~@5 zC|cyTw_V)*&EpKCvk@A@k*`Yk0%S}>V453NNOE7Gc@+Cawi=b$c*9APTIm+|7+$66R5Srw5 zDTZzGTFdjg4vH2iuYt%S<*OmGLwO~ao1}a_geEE9fMJ`IZ{sO%gkqPxlv~PMcw7TY z+)}RRG9f4BmeN^vJA@`V-GO17oF3yjZGxf&#)ly4lCE;EDMMs=cYZ&Fc8u@ka-p8$ zjp*YLn$)uy!#4H2$m@9?iWW&f3z22gPeW*z^iy1JlJrXunk4-)hHa95nN575Sh**e#`}tvhak3MMoKXU{u8;SJ*^8$jrU6 zvGg}{Pa@|2Fz&v_#(gzp7KM4uA}f1@+bl9KYzU8BXA^m#wfh0K?gQNYkv8r}L1t0d z2E9Pz<5hGk*74lI_`M8xF?y%ZM2U&gU6i)MT?1OfyiPa znjx|{sGVgqAv8hJhG82N^LR?Lt>bps#hq^+_f-41OL^RLp=g0(Aw(7^&W6bD#CjH& zcUhCpvSkpOpgIr3HmEM+DPICbi@Yx8am|mF3%T4Rugf7c$?FOX+vIg4&uc9dEl{q8 z$Rg!yA+kfcipxz>UI(E`$~R%yCgr<$%C|$&BClI{TyvBgxZEVKyCF2m>mCf-HZRBx0@)(=QqpjWNZQVC=_kXi-KLIj}!p2)iKHfHRE05f46M2fY`$@L$+qwHT z8}~CHvncFjtH{dlZn*o|HtsuYeVomGoN43ZbjU1HJk{3y67GJHjr((KeO%0aTwvql ze8?B^SB?`$Niee{St~6 zC_abC6a_ud_{Kc$xAt+j^SIyJIsehz`3`&MWv=3t#_v$HDC$?cxZPZ)lUR;nn@QY* z$L$G4OJcpvo%gYKegJpAFBC0`>T4Ibzj@pP?c=(5+)6v=Zgb}zd*`FL^Wl0${WT$E z76sQsWD45p91M}gQA*c@JaWJ$@=@0AkFa&07nnMG#q{xB@~G6e}@ogJKO&>00Z!tL);gHII9}ecW4l+*_b%fnq&GrYPuS ze4BaP+wJ4t$K&2@=lp(i=MUIB-^`sq3Pp>e@S-B?qMk61`=ou`=Xl(w?VLYv?)(LN z=l$HpD~!F}x}~H$Z|w=0MZvuxGMz=Ivlm2mkBoY9x$tNvfyW@U0QQB@xZsOFSw4g( zeK53y^{-3%K*%gIJAg+ve`vHHmv_kwXWUvI-ft7$XB{4I?63vn;_@!xon?nXXa%N$ zXEqpGR$%HNvzX0+5LqxA08y96%F1kk$x%G=D4WP5tlbZ@b)VtxlQ!<-kXaNKwT>L- zkJg2*!Mb0D-!djXes zNgK3R^4uguuAhXDAIYgGZUBqLXuY?P@+$^^>JhyA1XO-J3$ShXERS=n`O=q{Y z5L(UH%{=lto5(jZyJEV6&h%DvP12t;-(_F*pXvMQWqPeW)`_$xf=7olafU|xXCbX7Q=&+*9S>-8Bf z?~)mqz0JeF2|WuguUkid&DuMD>jR;&Zv3YCT?`9_8oxmQl&AEOb=(i^;(lfx_jCKW z4o~r#_E#ucpx6nK#YFrBk=+vck;}VG1YUgLF-28|VH;F^c*?z?XpvV>i0ty}!R01- z?FpgD6z+v#o4hJ{UI#(Z0%d=QEK=SdBD<9L<#Lmh4}s7mqmCo21+hp-IXe7`93IOrG*-P_)QvK96gTaxRyfhD#u{<9sfco7A%$LX&zf!LUs|*YSE*LD3@Vt01yW zdL@K*Nng(8CP}Y`&?MX&cfJXV7DYW|7x!`VxSQ?cKEvZaW#{}^bLY?5JO6|`|4^@}dm{EeWEKU#2a)M4 zI-T!8q%1sPVbQOZ*!LXY@W@};ME=6s{b#oBf8y@9+qmBbnMGmWSx4St8@bF|yo&tY zCi1V=?swX{--EmF>9tJ02SgULQVx;DtT@YhLuhii_rb8u;l4jlsh@S+eeB{MU>>)> zeOw=p>xQDmJXS$ufua&3OBB@*nxODw*apR4cuE7T;~r)gx6VB7Ap5vS@wlU)Xn|q` zL>4H9L1cH5XyEcL$Fj5RXb4SE1u$%bD$P?)K+z(v7>{dy1rgzLle{tzn&g$muuWbk z@Vt(Pq6Nxv5Lu)=79u;8$8fnx$`c?oN%=$!+oasWQ*MHyMP8G6TyvC-TyBzAD}*L_ zO~bHFUSA-uZq9CHTfB$hg}dFlZB^Q`@6`5tYRkHnZ&Ui^Kd`os)9L&aj>ojkZlByV zru9_zl3?|Oq`Vg7V=fkQU4~PO)A=Dpk*1E$)|rj;o?%n-_w_o0kA>{?)Tdh?r2Qqd zqVs08Pn^>@U3evDpK^%Ho#kI!h`W>UTPq=+xcshC>F!gg^ibQ~)V3#UiNY`NVng9) zE*2_KDC~gfk0@-{>j*wX3J#wo1U!;pzd<-10;PB%Gya!= zuHg=@f?lL)dh3kV&Zc%jRrw1&E6Gb|d+W@pf=Ky$dq`uJznI1hzeO4+L(s*+k;SW+ z@0zL{W#F)_iRO~#Y)g})y=kgrF}-GqUg0|1>HMb2(b70`3cZ6`dHE9lNgj3$^pk46 zlUx7T)%pi3>vH@u*n!x4G%M?khvEn5y9U=hPyeC#D)x zd3-8&qo?ydj1{I^yBK|IW%RQWvD+_Gd(+m^?boS$z)81mzfHwk!JXa8f9IL(=;Cxc zoED3BI2II(-w8!S@vOM=7FJxh9xY0!-CC4TJzH3)Zo9V>i!N(17L7n=p}Ip+7YYpf zDPhX?=kE6D;%+a&9o~Ij%zR%HcW$`Ds_Euev#wFIK2*uN{P32(v}czOXxYcnt*l%3 z!7cr0g?Ar<@YL3;ZG$>KRP7H_+u>+o-+e^OzObj&SJgsCM90Lr?KnawPFCJR#$U$n zV()3M6m^PofJ)p0*BXIOtdVE$YJdwK&AI&MCt}#>_T-Z%woPiD z-7&clug~w&pWHaBqqA*hlQg5T1DoN5869&bPnb8fe!?+L)0-MQnkEz#2F{u?$B^gQpq+w+m+2Q@p^B>>$p8I{zFVq4@V#37m2YMB55A|WfAPuHXIEcWy{!83>hr1}s$O3GT=g~8o2%DWKUsZ! z^}nlcsJ^TE{_0PwAF2Mh`kCrCs^6*pvijZX53Ap+{=9lg&GMQXYBtn7Qu9Uaf(&r( z)6eDh*3Igiy|DM{-fMba-}{cB4~v-=76Tka3tTiiR`JKev#*LyZ%p6>SC zgIT%{bN0UH1I*aRn5!>5UwXds{Lk~X=Nr$ro-LlOp6@*0d$wU7fAsA1{ObALv(S4k z=4Pq)Jn!GV7kV%DF85yMUFp5jdzE*U_ZshN?^^Hm-W$C)dDnYy@ox0q>b=c-r}ug9 z2i}jopLjp>e&PMn`#F4oEWSS=r81$~Z{^S|nEtG8C)?q5=~tmeF$zt>z)b0OByikeGnF0Z+w=E|C@ zYF5=;Q*&L->YBAR*JEw1t65)jGgjDLHFwwCU-JM~+DA1%)NHT0{m^B#=hfa-`)2K1 zwQtwHTl-$^e{0{b{jm0<+K+2Lsr|I}v)V6ezpOpbagbyG1(nzp_6kgHn=xx(>y*v2 z%bmaf?r?N-1e%)~I|tU)UEB@-4z4mXr)~Pc8B-i(*cX(Mfm7O>CU?$hqLVM}7Wgd! zeboIKIJtGYuX!pPBg<~iC8VnR!*r%jXJh!6JfL%PchVLAFrC(!Y^WUn+s(OfgsD!` zJf_o~=`8pc>j?kD{B+D`BiP{K$2Cz9vyV&%yA=J|4gYm>_M(uwKQz$mFM|dR8Sc{l z3>sE9V({>~L3M+*G5R#9u5Reip)Obb@IeiAgJ|TWUIfwUn6kL}{12Lj|8{rp8~?K* zyYcGR@ALS_Y~FPIZjOGvcXNPNMBp?)xCa<<_S)OQ3Q(bw-bK*4#h@2( z>>XfwDtOZCc+KG$K{Fuy;d&~35@qqv`fhwfP{K#9r%nJ#&%LnR@zZzuz+6wA1k&@o zj9Sj7>CpagJ#`{T@)@YFK8B`5`$KvFD$xpVo!-6t)25Hj0;Z~+txO{ zV?uTeJ`SoMIC#XsA$5a>44E*gb>@UbTSw>d!-ujn+vLFmr%a#japBzTkUHnjYMRnI z-61v8N%O^To_w^+DbjcfEuImJr_9Fo$t@Ft$7JchsNOb}WHT z$3C&jgC^BGdp(M28H~l;uX4fW*^V|WZTi!HTp#Rb{SR}{|1Ri`Yb&&ev;Q5SjP+E; z7Id<<@5TMGo{npsIi+oGhb!IM*)d^I-Gt=K$~X~M^Wbpr60u9y{E*NJvw@w|{;@I2y){7UP_EsUabB`%MjPxD;)~9_hD$Vg+=9#&Cv@mQ` z_{3hnmNmS4RQD&>&h1;+HJ6&F$Jgw9@~AVSTfR(vGUDAAcOKYxMr}z|&uE%4dDi@i z9W1@_3En5JyTMzya@1irkGuZIQ~Lg1np0FvH_^=JAy-U!;_Pjs7yWuf{FYnS?eSCJ zlXuOh;Oe@0dtNYjWPZp4PxT-3#53`VzH?95rJ83nPM_X3nPt`LU-kavBR)Uj$B$n- z`R@mvbw{p^**Ooaxy58xiKKkg1 z;lRYYL8*K&n@QvgfulzR9Ov|Kl;f{P-bnvQ%U^I_cj9FIv7lWS&J}W@U?Ln)b)Aat z>#FY8g6@z|JXJ{K3dulYN4u(CuBcx{PrKmyTTwj{%tTY^LOL+LW4gKeR#814EyU8X za181e-oF>sqoH6SS4iaoINZ&>{~)TT3!!{45s3!c+vl09?{k9&ad0FP%O|txXrQ%G z)$XQLdWBkPKT#V1Be_C65on!cuDzeA9f>64p+X@Mm}24k08u-XOlP85BtFH|ci)Ep z!@?5JFTp9ecI)WCVMS*WWu^7ne~a_WU!VE+BTrp*Mq*z7L1m7rn*>OSWHKI4q(XtF zQ_RbDi`ubtA{Q%QerGnBYkNiQXgHos#iPMMONY63wWytrgyQi?HWZlNX0BZ$Y8Rr( zd^(>924=LHYuAd}sa!A-Plw`xS;bXsSPF-W+OcRZ7)nOcfjJg=OQLot9|{N4@l0UO zWb;h^B5D`H(O5j2$^=?0@*X5=LpK!3r?NPn%zY0LwPUe#HXco<15+(#r$N+CBkN== z6PVs?PM??Nk?L#K%>RnLF@@PSMaI6psV_ysgS}iIZ zBWg$E;Z!1-4+UDMn4|uipglAn$;JxVd?XM$Hje*SEp}73uE*4^>m(L6HAWdle1!jZapMU(DI z@>i?LPZdpKnKbeVWmJ>mF=Q}l6-l!Y=gl}!Js~rDTG3yY)q}8c+NJ|FiSKE=W+ZcqpHPl zwG4wryI?V-kk5rui3IjutExK%^@eaLn+O#Wc~ZBkdX8w2$R-N;R6I-uR#ndx4C*t9 zXf&43rqmi5%xjo0nxylwLcEYnswVa3CZ`D|L!$9`t`H0b18r7ipCPC>ea{i3XWOI1))`6J%gj_5#76J{Jim5hJJ8Fvz@yb3~JD8X?lj;$cx|ZgQgEt3{K1D3mXxqPS>e2j38LlN&^nR5qRp=5TZ?CPU3l)`=#`7=UH5xhp2a z%uQ|)P2#Ck1c8bRrMSTw7W+ogBpS}-Q#hZgQHqyM29rBPlU$(?jNn>Q$*Z_88!X-z zEOLQFJRi^IbMXLOIMF3j4$r#Pg8C>M#KY z-~u!#8Wt%U48PME7DDk{E-g$nA{L<-47ceFqxo1Y7zstih{a1WgW-0;un@?`qgYsx zlx8@1V(Xw{vU@4(WV5MJ^UU1sH9; zDx6KF!vU^s@cx^iJp^}~iD*1VxlC_YHz~tqkMn*l_l9UVn98S;I33hC53T0~7_MWw zi6)6qEFF&pnaPmBRwmsAlTbL2h^6A0P!t>QFnn9sK5^!$ljjhC=2;z+i+T1{7QvJ1 zBIqf27#1qTa##XX*R088$gAtASUsXz^%ATGMZ%d>A&IMGZ1*9RhJjvhLBAoFqI=f@ zvaIj0E^SZIBoU3JLpj_|!DP@-D;j$XCiU4^D4R;9a9LO1F`Qc%&Ov=iRFXo6fUPIighW62qyJ~bS4?j$7zkWT9)DxEQZ8!ky=Qw z13@z|9627rU_?HfNFpg*uGKdqE8XE^II;P3c7;SJmrdaKXC}K(xc*5DsPv*ss()g@s{= zH&C=o;`EygMkyX0d(7B^OPy#}$Of|oT%y8`jtx7z!J=I@6b)f>2p01c4|qeK^`c!g z9}LBDTUN9a4@iUEP{FPqw@rAg6Q-j}Sj2{-ez<56i=+zCXo428z}{dnQnZK%v)ODC zmz+n}3)Br3M+g=Tcm@;1A&ec8Wp%U<3sZTPY&ZoRC0gNDITp#$21bcl8wCWTdTdCk z9IiNFg(FNbGUOK$jD{!hOe7tn?P3@^RR|}|-Ib01QFY^wh-R@!Je&(hLd>jb9y?>G zbs5ZJg4u{nC>~2jL!g0Z`0Y-o5Y8~S3BfKCz%w$sFv6lx4F?OBdnk!Mq$ZjYEQd$q znRF(G>wQ*V>lDGvkZ49QtIs9UsYpCQyZbC{yE1^x2^P5J4Wh%_6A;?$X1WoprbgqFp8%jnSb=@nB*X z?{A`AA{B|n;%v{LlenGTNupgejpreFmVkJQopqj*M7wMuR=_h{Z7&t3-GFn7&Mp}V zMM7aZL$hfRuQ&{L&7xgCf@e1A1fO;ryB5(d9*cxxAw0G!#C;#;tG}qjOPlL^@(IElFs11jP%))4Rxgfa5{I zW++Z!p(q|Uut0Pjuf{Qy^{{ADh~z@aP#Rk?lIyUvc~Y<$1Pm!W3c`8JhX>ZC-)%l6 z=-1~n>2wCS!%QDGIRTu3!83y0FkFa6gONN=WQJQ2!%f9=qER*)%*OGpm1=~ui<+Uq z=mo)OcqA6dCn9uT#v;+VMYS?)^DhckBMOB=I2nmyy>hF;s+nOuyeyav%SUpVNF+X#`W1~E}0L~r4%hEy`5o6?IqX^4rQ~MP>{}KI1+JZq%2;;4gL_pVn{v`$z>z# zDZef|LuJDSoBDVtnM|c~%EF){zQ|pdTHkx{XrT08BZ$vK;!QJy9W#!j-%_^^Y{k!t z_I4gUvE|j_ZAbpHaKI|h3kycgEpu!TQXEnUhw=R$@P#AzFE(2xVW{eU(IlG1QvzId z1SZdzSyXpbI~K4X9h5m95Oq_@P%=gVCeN5W7`=F>BP6Y9c zD;EiL@*`B#eMr!)k0+u@JQ_~~8mCMyKJV*Jj@fruWsZk+%3<7I7m{HpPcc*8Br4}J z=~RKfW}IoN`-rHUNyNk1LLAB+?PiW26_s=0WH_6_V}VJnrYS!rD#wyxe36>O*Zys$ zo*&mKr=qwDPUq-HAZBT77L}ve*n$}xCHM)5ner2&G9F1J@e71RV8--DGvz0B$^~4% zgmGIwqm6$tFV4w7MCB;%0SokNf*G?-bAC!xjs+9JB<>CZGv>@ROXHuSGVWQz(QG0f zXlplBep*z{1oL_PtRW0#QyR~R%E@#-mrdgy1wV%|OXFElIUEb7vO%E3k73M|pA(gn z*iKvyOSk_Wm_t+TmjvzlR1|x90$0=>vrTJ!Sx_E|Eev0$ zVwat5mB}ljI-cuB3)w;z>K3WIDyTQaa>-aYf(H<@u_F|p-1nd|+4s$5j?-lAd^7~V z$co44OO%;ye7{rfD~mtLIzv!z!2S_WW;2Dr{MII`FD%az42C4K$w(@gi3jF37r)#x zY}IFr>bYP9-?-v*Jh!>{y9tB(LQx&}kxA@*=|D%*oZ@b+&wjC>ULOj_Bk5Q&M(V}i zd+5$=WsYTn{@_?R6iJ68bl);pb#FN1t`*d=Zzpm|`hn7{+5GEbgZrBV{lVEtI-0>x zns8+c44MG&sU=uis&v_4K3hTPBHviOu42QQ8$mSD~iAI zGu(po5DW)pLXk)|AHu~quI0>U;|M{2SU8i*#WQqUs$RTw=wlhKQ;!sE8*-6&Fj=4{ zGeukR>c>#tIKgrRR!lC7$4Kn57$;HXR&J1xv*DWmBGEd5Url82{ROk;vGsWy>@ODV zhsERhXr>S`*o(Ovs{UQDZooZWJd#U+*bse4L&1)Rv{f(!S7i}=pNu=uAz~cEKH?Kh zhNbbF0{mW6x!<5F_0bF|Rtu*1sY@<{D-H#35m51})R1OcFw6#0c{~R%&_gZUuizp} zy~oxqzuwAjCacf*GJ=BW z_@**eh(&Nx<3Fh|>>IBL`a=_Od_|BgL<8(Q#Hs3`Y&i5^6D+a;`c-W_6OSk+^tIzD zMLPqv*9E&_(NHps9Uy|A1=H7+MH9mUds8sU1#pj%jbw0&R%~>!bl+2#Io=WshlQ|r z;_Q_TG}*;^M=-&UQVO{^uH+-Cja{tw1jC`pC?+(PPX*?QWf=&*FIZ#)$y6wv$>K*w z%tRN-K=32ME)&QW3h8_hUm&rnn4LOdh6m!G2xi$pJdMZUA)LzvimII<+-G{b0&WNK zdw7wEx!o6nT_%9%$M{_XF21$$%+vgzU{;^W;RmUiLY@_;>Kj(>H-dgcJ{F4MK0mBf zr5YG^oh_n4Dx6CcBI%S;j=8~ifVco?-2AGLctUcZhZCMDi|0l{#h^>63-_J>0mY-n9*Tzh5L)Bp2hcm z*p-8USyt-53F^aQLHxKI4;2Hm+FSAWluuR(84hU2!`k_27{1DgBr~BxU=n@|0yA@y zGQlJpC=?=i)Q4{tRGW!28jDvbhSggx*o{cyFBagJn9)FU~2<$DVTL-7mdG=3WvRSb$D47*W3!JDQ%#5_iIo-NK}sD#u`7R#I|Vexk6Mf;NfKszYz)) zpA{QCR|?AY*#uo4tGZ4@%NF&js3tPn>P_Ouk;UNG0%u5!h;SwO7OBYgs_Ca-miD9h`6;1GnGLAhU3zI?CCc{LN6#kY(f_^*DK4`GD$#B7B zXb2l+IE-zqW0qiHSVAL23tVGI;<%RxOmDZg7%5tWas7thVC4yLbL%PUd>dkn5-sxh z)&pBXh5%by93fZ?OK0-w814WVV9mq;_(;(tj@$JlZtECeOOvBSlYAVrj^DE~z?LRQ z3noM3A^f}vzab&OnuVeGfM}7)MI(7U?IggK7D3UXfF~Q7d^SiHt?d?oL!w0(zep}b z^0W_FTZBc6Oe~nrh49y_5Cbo$FrUPTXc1503-D|R&x&SQTSP^RSSSK~{&QMOv^J7D?u#=@fn;--IA7^NXi^!-CHU zCb)Pl6ryQ-&5S}c3qx8t!J;97-;Wf6_}%`P!kA-UOpLolt+CsVjDq~H0#l*JPa4c8(6kG<~zv#PqkSfO?HcVBK z(BK9SWpw#utm@1_b`m8%-cMNY-#oP8wbhfVtIN@b+Uh6K)p*yBJOv##^r$Mz>}Wj^ zx$eQJKYS=QT-0DQmdt}_I%1O`iKXm%4|&Y=>gmP7g%mfmK2ze`lp9Bc1HP(%1KkPLP>RC5lE(^ zR3!<1n?1zg&<3h?9NsuoBPTLDcqq#35mRu`v9bpJs^RvuMq(l-^kbvMPQ`R_RoRG9 zN;?sIFE93?(<-J+si;e64q4aQ5aJ-t)^m9)nu%HV`bkJVK=#(u%-zf z>L?t_nvPBHSSv7_0$_sP3~QnYpXDKr#Cay3DP=xKy9qS4G5gr@i+w+vMfdnkAbnEP z&sy5;8+Tp#=uHFe-RZb9`y8J6df%X_2{#cmFVRaUFiKt4IlpQ73SL6lfeXO8l?=q4 za=Tz!@@#%&1N^147nI?)v2XSbGZ!Zb;EJzh`SH&g2>dsIeu&~<2K>5yLDTB_$17Xj zSJ^Giczwa}Tz*VX1wq4ZPh3zIq{FZGO^xiA%CyCBI-25G=Mn2SxZWo_6sQsAmw>q@ zhPfhvc|I|h;F_3h3D6_V8emTAZ{(EJ#Ti~ev}^j}wFnpUDB8t+QjS5WLRYB?xvVRyvgh)~zvCe)7odVxn~)j@RqE z`a*7oW*&=S`k7Bm{IX<_{oM$>`Xei&^Oeu`LRGvm!T zqR*44ml1Wv7`(QF6&Ridl{|MDKm#~FX>enKb~(}Zo`%=)`}=mY-GEf)ARo=w4iWLo zmqGS>)A6bu6a>2)rG_v#B91qR%W@cw1KyRyJE9h^gANFS{*v{IHzkJWb0p?f#2hyh zuO9+)j~M1S{EqYL`8g%O0%+eN+VZ3D>H))vO5*N&p(OffK0hK}O~lP}@p?6eI0%Tx z`iOp35OF;b&pigO`(bnu$KgO6ho6*OJwKTf#QHX|9$SgmfUyn>iWxo-a(Y-vF|Q$B zeJ5W30A5t`iMJzuZ3iVkM=z7X?^@y=c`{zlf6*`azXjd^AJ5gJjljB&Sj)bK*I8e3 zWogH~Q<($z4jiW##`VM)dkS7X#s|UvVkoF3$Y+${lOtXO7~Md$np5$*254Gn$!Lm? z<12%Sx{+AVpN7|$%lwk}XE1B=5&b+P;!Q-n{S3VBnBXH8gX33xZ8Z5TYk_$)F;71W zuh+``TJR&VyxL&4Swn&zF^$w-R&v^YOa1%EzRv--~0q zoR|x|+lbfy0=x!Q2SJ885vJ}0(uP<9{mPoExt(Y~BHALLMYS0PeGT{YukJ{i^E_aE zhgg-@<8=j!Y-E-%?UTxU;9>ddB;Fmwd-(>uR@M3S3h`3=!p4MIhf7%-knSYXBRAsp z7Laye%8F7S0HYX}@dT6Fn?{bn)xSk(j!`}C0NdXiAE!Nl*IlR>O3DyF6=b$!^C&I~L5!^wx8>nATgdHBjYb0uqofKhr4`IwGhfo59 z8;I~7A~bpkhY-QsQ$7`!t>T89Ic>N%&X=wyaBn1T`UiNu1KfR;*%$KTg0HWJn~0nG zAzqIi9RvqXq8f^*vJ_R3q5xs0#*vz}vblXpAvta)tzCbFSNkzRu%nS9HPuk4FF+w7 z%`K!*y8*9PKw$@=&|oOsMhbPfHMe#4idoAiENNe`Y-!uFPTVD3R6?!q21VRT^q>A5 zugpAHH_^i&^Lt|AF1V%%)0!5vb@G()j1?`o%o^QM!MzVXiOco}+PW9;x~oNTQz5Un z3VCZ)n0X^krG8=i{LTcK^&oRO$qfD_UcUkvNkMl~Nby3ekk?d&ynHI;l~N%uiV8D( z;MS#JQ64$;JG@o^vDVmJNE-{O37A`ggyZ@WlyVihe*O1& z^<5AI2Z_NFFGaA>SZZ*4evqBHNr3zDaw+{+@lmH zOdFBMmcK>Q_{u-_fcHUJ^<6yoVE)>>9?O^$}ioA-s9*UQuN#*}tlrHt{f-96weGr{h`(+%y71p0T20DewEVZ3yd- z_n3c^{*BkjWkJwGHIlkcYMuz!n6Ea$#QQt(eoeeNz_WEvG4V8&t!*v5-^6iuwf!?t z>h%TQ44X)}HT32r2TcY1(8zvIxaH3a&Y%AU8?g}j6= z0GgIRvk+pdV-fYsh zJqRAT(wcgaA;^2hLS7dZW*RN6Y2{7R+Lo5jSkak7>_I5&783h&2E^_Fu?k8T?!r67 z!eja3ZC@cT@d|l2SIFD8Lf)Sh@>Z;nH(iCiy(;8=R3WdJ3VCr<$jhKYUhow1%BGN) zFonEYDdcrYVU{mmY7}NJ!rN%EroOz16Iu0Zm$l>-ma4p!!d|f>guSK1Z^A974z;)l9U&AZm^OaxE65(Q z2T)G|YW6KH8%H;$$TO9Bi1_5%%0eBStf)r=^>%Xo>pnpJ7^rn7pMp#q*al`0L*1=h z)xrrqhqnvxE@f$6yFc(Mj>p%Z_A>Hj(Txv|ZVX>(%nnTLGiUz;<`kFC={s~zxC8{V z-wZkc!V~!VDqg8G_&Oi2qAU4zJznYC@CqNK^D(}DOy@7~>h=;|BVNU;u&PVa;{v=*S&)_xSmw2Uri`R~S#4G#@Ua5Ea`iRaH zG9&EC*A9I3#j9j5yi$YkDjtki_c45p$17dUuW5YE!Yg$&U#)yC=Btyh6ZtxsuQU0& zfUk@33a`Se=sJGUeumNr(huTDR`@VqKj4cO$#m!aFxk@sUi%XAHkXiBw1m8LCFC_K zA#Xwnd9lfkysaeU{Uaf76bX4rNXTnHLSEz%@@|f>KVN(B#Tzj~UUCug;);;BP=vfv zBINxLAuoFfd2>U^YZyY_sSxslgpju#guJ>SKQccS9b=4SBjYr(V-M#TtH}uLt zIfgv981fuq_z_-x{)JZ&PyA(ge6NTn^1AbgU6?ruZ`Km%z_;`FET%Uv#ZTyP=rRyJ z7gSc?VTt{5-!RB7JP}+M?GNlJrw75nV_CDO2cZn64&jUPrzk@za}nMFt`lC?fxd8? z>0Yt=@jDZDk=VC)2eIow%yuT$6VX&Z&;n4TFK(-???Q*XJE2fYT#EIQ<=V^ zkQKOsy~&8xwi15Fg{CkLh<_2Dj0>$oroDs}dl4(HUaYf1)>++5 z8^M~Om^$mml5TXC;t8OT=Xye()d_h5C*--Bkf&ur9)U^oU`r8Cs}%77N)b<$6!EM` z$nzf|4|Rk*su5<`0Ep&itZ0Ktw7S-0f3zkavH`0-2@1IV8~7>?jqbPm=aDI+gH&&m z^!CQodyT2hjYShcELF`H6QzwDYg6H1#(`5?S59r7*R~`dyL+kcp67$zjo-xA4k^Q~ z1YE$v*iZ;{^2|ucBOoDCiW}3t8^iX- zB5R+_A|rknS!#w&qsIcKpO3}&$l@a0$DN&iF}?y}QC!>@_HInKH%2BP>S1X@VRWQ1 zoT^>fHe;m>Cu)|pwynWf-nU*3N zSx6%*;z&vo#O9`msWP==%J4TTr^qFhVYeblds2+{1EhWHJ)nI#Y45BCutnNDEfZ$g zTZz*ikuQrLB!iw0fx-C8bl##U4ReNlu_UCJ8>tL?JxO9_(k36the-0|he7flkj!2! zGH+kpSR}b_G9?wyl$6U9$pvOWiWz{xb;Ntx$Sv5zd8im4ChM6`f%WZ|s74uw4Z6K2@siz{GcGU??12>IXh0{Hj462Cjb(wg?Q z$+V<0>^UZh71ZVrNOJs(AbBT9W=|Gv_A=T;l0r|L@g$`@9kQD$9Ba`u)U>Wafju;t z02Zi6$!+PY;C9nh_>#eEQL(LXyqQOjI{Uvd>IG_?ACmY*uY>rMZ{h1UDJW7Mz~E3; zQk>aLnW3DiFf;5`$4FD~j#2qUe~i?>_-9c6Evet3)VC};JM8hS7@efeeEkt=zx)>r(#iD3`Yua?qibNnJF8{ea%0? z{q^nz5bA?h8uRkVaFi3LJVt8leDt3n{hNzGf5eHB9p>zDFb$1q-p%Mqh?lo_ z&gUWBnq{lGv{9hRd6M)mC;|P4N&gk0?^;YYmu4o?OsMkAT*%XJVTJ=V;iHoU{y37E z@DvGOoB`ppuML73Mlon*SW&`mIon`*FR2U%GD688&L_$JnB<=919GYBf?#h$4h^r8 zOpPpH|U#Z(M1Vv_xgw5s+3t!qKcrnx8V6jKQ(5lfgUrs0)7moX@I{8Bu%7iKuB z6&4d~>uQ_ZvGNk{>#akfe}+sx+#gI%zY$;W7{#Vxs?4Ov8q>&j)3h7n84kRKWPMv_ z+p^XqMcUBMN%8nnP~7Jxd_62#<*dleuBCWRFwAfWFXSp}>ub>Mh^7Bo5-P?|_hcUi zp+gha!)dfshU5Q;0;lI$Q)3}df`vTY74pbd$a7dB4_AdeFctC`RLH|k zxM2h@9zY6tnkeMyppfT%LZ0CXc{V5Hd7F?&XhNQgDdKsTBA#O@;`x*!o;$%VFlRO8 z&C3?IwH9dRo~JG*PlGN_z8zn!GDbMS7VaLS=9I97>(0X|AzAmpC^klXk}?#vIl**@g{`H)-UL+)}9 zxp6(@Ui6UL%R_D$54i_CivkASO0|4p?hDe&4b! zpB22ol>coGQoiv!K`J5wam3!B>YPfe*I_=KKG6w7@M$n zLpZ~6qR^~IQ-KoGj^-k#V6zy$NNQI!fm-@b?WGl^rC6g(GwV|s&W{PT>B}cIcPvD6 zgM@R*&>w&Nij;;lgVJ(P%C46Jjeahxh@v^E3}@I>arr6y+N7)v6g~!pC4R~=s^WkWdKrfb{mq}^h5>R>*l-Bw= zh$^4k!$WTL4l|s*6mk;^j9)KC75W>JyLLGR`%iqmE>);&jWNbdalRwP!E1^e!9#BC z4l|q;73yY)Tt5nO<}JVNH{)mYX3gSpio4E3?j{d2oZa>4*#Tu;UB0ya zo}?F@1kzu>2VWb+wtAXACpt@RWNEsWrr&28qNt;pIV?XrC}DJck|T5LRdW3IDd0Hg zUVJ?%xy8v1*VRO;3dNefd11bszs{3P!*_U+F$?4$$oP`8z<9=enCCNEOi}t&hST7M zXpP86>ow9k;%v}bpQOdv^g^`q4k`XfTDzVDTJI)laZ)}Ht@_%0GQCbZ&y!Bo_Y&#j zyuQ-Gl6*eoH;BCMTp(Wzza}>t0%|_Bc z^Xs5L{`>gaH8Hkfcj~3a?zZzE<$7dj>_(^9jZX0#L=n$36lJ(fVH4)bkTdF}2yaq^ z(=LMukKB*1->Bg^t9yyFQF#X+an`8}*G2Mi%^fn5@1Mx`=BvT?-3RdX7vY=n4c=qD z^`xgVT$0Jde^?WK@N`(N5H$WjQ;5bJAjGJL@TK|7zO1cBT#?IL%DDiPhvlJ#$6$XU z$75~<$G6Gxr(#j4w%BSx(U`k5RS7F(Y+x=xAE_xgY4KNbn0OaBT>tRaIdI`BnS%P| z1$tMTNP5_PAU*dHeC;LkA={a0OUREY9wZ@cI_CM*#S=3jPr!s3E_VrAvk;%J?48TS z!{0m%X5)Vl1Si<$kfUMn;W~cEgE3)-t7bwg+7*zG;9Hcw{D&ZT9|&eoiK!kfEO!~C zcx)!*5tuN;g*c&$@>{!PRmY5Fd3#=OlWvd4L3iz=L9omS>NR9s$`dl!Dg#RSM0g-790jgB3zJdU-%?~?jGzXJ6`ew3#Rzy(VW znfoDiQJH1$JtDvGGLYBjL*_!KAUEJwoR_aOQ_wL27t%of@jDRMZ39-Nt%0y0Avbvz zC*-M`FvI0ipA?6*$jcb9zf+pyUZpf3mVHoi029eNskNOqOEp5@*l$_otr*qy0rw>07 zC$1#tq-NpDwz#f7AeZci;PT=V`1-RL6;?00oAjW)GIcK8dfBWf%tzC5A)ED~;V)%cLC#v$A9+7*d&8c{m`uCoEYqwRu?^ z_EUI_J|d&P?g~cTpTgIcvz_x7DW10qGhAa&rUKcX!-JXfPx9D#5AZmNJhqzsTqu^L zkXI_hrTiRT%#<8%RNcSGtz>_2JLbpu+H&TQRp^qH%5cL#k`*&2FQ<>m>G|Q{^cFd7 zIg`k#$m7(RhZ7ViHl4$cYTQhAtIEOdoTu^CWi@gOL^5r&sKx?3smyKM! zbxoPvZjoe2Wp06Ab`ZFXITHN-MSfjVDR*`x`FRP9+5K0^=!Jz~bm>pGnlRQ!ei7#G zktCxiVKF`@lg~A)z~|tfZ8bsU;}_(8WI4RKwN;t`{yz9D{E#^~bTd`Og)ob+kwe94 z;P5y&^ffyTg3JMVQ0v=Ih)}t$=@gV;K>VW+zfM^V zb@69+w3$Uphjbs7?N1}pJ7)pu8X)aPBy8vy<&f&vcKCcYAW5ea<)gEK@2lZZF$q{ zCrzzH7j8!-(j7m_Tz^~2?CGeVRWY@xwyp~28zGJ1aY3pim}_twsw!s9sH>bXYeG{! zx&ztWA_~2NQ~NeG@#n?OdC#_{70b;}#CJfd-jLQvmEC%jhFM5V=TiI(!LXJwqt*cX z1DmFrLO~_L=vzg4{0`SFPx6&W*k1=T)%A__)ZGMLvoL*5MZ?UA*nn#jScC*NMhYG= z!c%ZxkhuSPq27v1S(^~}f znc<0Toi&wBouGH6B%vhO6w#YhhLy%jkK0oQ$NYG%k4n*986vsL~PTntE#W6YpAMhIur|z7QY0M zE*)G^-!!9k7P5KztO-XpO`n0xo<3n3toS;l##nI?;uSd=W>2WB1QjR69}#*~GH>b; z!ntlf ztn9GhH2i>jI{Vlmun_D9ycFtBgZWM-Wm>xGYny87W_tO45SSn3nB$i~n`YPgiMs?8 zzV8<#mz)Ux6WvYocNp~hA~Y#K&qqRijcvm|&yjHafh$H;xtHy$g7hF9H`PP+Ez6hUij?TE zD-Xh@&B3xSXasUNU7#g-2?y{J^yFNfBi00BPk>mj;33o(?aMlrH7#A% zhSLGr?#LJXl>|>YeI8L=s~>|kvkZO)E0BKv~EvB_BRC@f6Pkv2!77&&DQL|De4 zt2x%;Ua#sJ-yZja90%L{no&Qg9*u>|sUoCoeBTaq6j-NWdaDdIYP02l_2N%l zzBSa&W)+3ZlYty~GK{wm!DNji{epUXR+MX)03f)HV%T=}ejcMiKEAbx#obNlxj&P{XxV9IPCl zq=Qx>PG@h#s=iyQr-u4j({Pb@qVMswl9FJd%SLRmXqx6pdmSpT&5GZN>a8ND>OLGX z-f{S3k>oI>C$_2t^*AWj*1WU{m!M+#eweejKCsps(8`nq%aW-UT(pvT{X|8m1XNjlhzMiiEY4;#+6uR>c3qrHLD7ZwoBjd5w^~S)zzaF za$&1c()SpOv^TG0M`T}{VoB}k6(1qkB#>m20;;DFfq^- z#cxx4T~YQ@zvgt9x59V?*k3c)QETNjR^5U$bTeNjTBY;wpD0x4qAp7Fz=RQcW!r+L zWvDE8P6GvRAbQ}?={cr@(c71u6?k0u{lWeoXFS*?=IQSegw1o(=bG@h5dII}0*;JV zW!oYA-!4lhqTz8_%E8;jsJ248<$7w}k!x4>t*)6`MKjg9xtJ!T>mxju&xw)KLg~kr zAggYM{qzb#sT)w^+mo0bph2ei>lOUX$&x3yBske6RWr)urK_SIMrvlnD!_OXh>l8ve|eQFdzZ1Q=`ge=fA=GlCtKkWi1C}K$YUZA6V|rKa{&4C zoMvX$@TLy0rQu-XBWF+zsCS%k7bEC}h&X=sz^hMKCEVpItop=|eH}vQM0y(GtEnG! zF=+_uGWJifm$9jnGoI4%HRe=VIItwx(Km^yb&0X~fv||LIpfZ2|Brxu7B-BcXHJ%x z@ebI(V9j>bmID7W6?2eH9UW~=EiFL$qs_-BjaaPu>JIa&y(!Sc{jORvg~?UxS3=ee zE-W!5xe@672=r-OY<}NY!S(Ey`CP3G%d24 z;eOYTHSLQL3tYMAQD?C%Gbu#VRU2=+CLq7BF-5P%S{jQb{z`%dj~TMf)!n-wY++LS zs936FL-`#+d4JY%OP6TIe@QURP{s7L8|+}%*?bqb8gYMtxFtBf%07qANK{XlJ$2T!3H4LFn!0Za2UWbLuU(b|!ZccbY)*vM zzGHe$54i-^&G4J>tC7HCk{MDTD+`<=-D3pg7&D4vnWiI0AV*(?h^KK0fpuX|UqeY7 zpNN`tFFzS(m>Hkx8x1K=$yeN9sIIh8AG5tY^yg4Hl{UpyPr2RgGY~$=Rrr{1z^FK$ zkuB(uH#-V-(jZ80&9(4X!7j&6gI%(!TD}4b9&OFCG{5&5UX@qb*1?+XMOz(ywO|-* z)k%Um*LXML0wm=OqfcfA2T5+?f+N@6kAQq_tJ$9&YlYh_$FC%~AfLK9i{SLlis47j zY-(eph8s|Eec7}otIZY*4jODFz&UUHVa&bd2qnR;zFDBjiO)Th!YEpkrWqfnWda=5 zvx9Q<`s@Z7I~V#B==x&xgnI?kj4b%cfu$I=TS+-KHj>tCAvE1{zko9b%a*$-)>B~o z&kv+Mwn+ouq~{S(iRaGpv3|Mv4joKlItf3Dml#aGfj;@v$g=$klTFN!nBgXCpv66U z1ud+GnKI=1KOvk+)P!8mlHkmI*^bE)m+Kf$yn}l|3sh*Xieh#4qEW%Su8+fUm+RwD zJ7?u%hN{;w>XxIw7Rb`Zq6g&KS=-k5Hm}IAD(rYedEp;P@2KwSG|eNYD^=ziOtc_*P$l) zyhCJO^U9Uj#Shup0vp{7DjbNa+Z1y*ZG|qBo3>(iIOS@gS)BiN9lbvw>^4^wPHU*H zLwn(B!=VWMu?xj?z85wPVGXWhmQ%-m1GdxGplZ{L$|*jrJ_Hru6J`EHh0E+sVY*i0fg7K`OYcZ!o?| z4hD48W6H95L7N$X#V=2mYYs8XgYj91*w`5%?%^mIxOcEGRA}JAEtt(-?5f8LP&fP<8Yu}Lb{SV!hY4MmaqE$$#fE5nd>QYA?}AG&@)@-JIiHp4P<|LhlC06I~K#)S=mQ(i{y*k8=$!yLj;y_jZJ@N=l0lOrGJ@g`6TfAxVJ4=~%CKKg3#VD?_ZnyUMTz0qJP{rM(#i-ye$3OOl=)>%Xxb zKfxt^T7%!eor|#3^3~FQM}S4}E0JQ84bbW-JDtHg1@SiSgC!zegW{#cX(SAdfG@g}crb>+j{@4VAGdDJ&VtSYu(L#89 z5oIs%4gNs2AT7Na%#mu-yEAfX}JU>l-;8_mHp=TjCT{X=q(*Gi zO_-&TL+|+!yt!_FKSfW(EA|*AcT`k@(TY48itm@|kG$>XRS5IE3W0@nUX)!U(dxNg z!rllQV|5l&7`HQwc7+o^xb78BZYkQ&U^)B5H2$PU#Bu2#hjjf^EY#mNF}w-v-7Ex4 z+S7)Rna*Jc#x>T{5!MmaF*$|&4lw8*S6sZ3u7KwD@TIImn;jQ&1lsKHOGVXGGpimq ziLUB^WlXS^ac{w}l3=5sxoC*%n$U{7Z<%M*1nMa@2148 zMDI~D%p~Y5xt?fYO$PXF`j}DiIph7&U-{-X^;cw0gv(O-J1pDznO%2SqSv$!^1A;B z%!OjoLL}#m1^!Bc_8cLT%YQo|)~kMon<)#-;JOTFn^Y5(GJiUWEkeqdt$ad#Rc&2O z)3gcxn)Ys~^g{eRMfKj8->xQN-8JfClXzIs9Q-2?t`uEUO zYFMghSgQB1RG(p~dxoX%AC`JxSn9!HsfUK89v+su7czwR@%25vzR%bFd_BO|gM2;2 z*TZ~0!q*S@dX%pp^7R;BKjLcxUyt+k1Yb|`^%P$}=Id#`e!|yJ`T7}O&+x_HxeuS^ zi@!-9mINzv@_fvwcsF2=AiX(0k%n_I!O7l4+P!ADbXs4#MHSutY&UCEr{~KYw8t)U z*a!Tok%E;UYY?yY}|$ecLjISCKJ)rXrkr z=Vs(+W6^y`Nczut+HEazQM1j7$ln{|`+{~QxSPdwCD^k(GAacl{I-Uz#_cY>9Gm&$ zFRthe_Nw!``kY?(B2?%Pxbef(*uvvgXblF$^^mCRN22_H&C3)2QV--Cvju-x1&X?L z{;-U#XiuL32Y?j8sd*qoc+0ONOqZa^Z|u7v%JN7(6DoZDaFfvp!vXz5Y+Q{s$DH+P zG=W}SS`%B;r^!5N2B5>oa0I%yNzR|$rh~-3#si_v{)q%ln}MN#OVBV#JJbq<4wctK z#XNMt`}_7Aj}2tlkkGM(?PDjKs^)I&vS(Fu74*!ya+$9NzX!>UC->OSdwreXcYhZ_ zRb2Hmds&!xPHma71otq%d8AwL1+S-VbGb2}cS-O~yT_Mlj_vB*(>KH9*ybpx?Go2E z)|aE8xk1YbkniYOv!-e!{{PQp~lP<+( z@^Ml`gQYjtVSWG^w4u~(@rHc@;g5cCF*O&a5}f^EjC*u^F4t_ZvWxgXLYb4ep_Vl$aQp9$7jzT%u*^h&wAFp8#MvQ&^7=}u` zG#!>oALmko)nlERj&^uHj`Un%rl!ASmk!#NA;p-igE>#KEx@5$3jE0txavkH0Wk%soa@Fl zQ{$6TmxA=q3~3DOYo<3$n93b{Z2e8*SZ0c&VP300%p>Q?-VU|;oc&{`V~5&>UJK~D zj64D4x+P5hJAU$|88e4mJS7yPIW37qnJ}$>)jUq}z*IREg+FYr*-H3NOlQWdUz@36 zYSAG6Ab&tfFh801SSF577xW3z+u=8!5;m^COyx{`6iob$fv6>?x*}P#tetmLNvDX1 zt2EjGL|mn-e=o!ahRq3!Np{H)Ep{Vs$JzUjv@gIm91&O!)Y{k!!Y2;;AniRwTe`(XG!p@Xc)b6Cf3j>Rkgnu*4vtrm^(`n}#vZxnV7q#yF}43m>D10t7mrIY(t zF_vD%I*A=TL+Kj@Lte~LC-A6FgSTM|p_rkI5;UO#{Zco<#-nXV^j+QDw1ijRVSitD zL$4(G*e_wzVyD}7LIHfrWemOj_5E1R~%X6-8P%G+L%L!asN`IE!sEb@hu6yCxx%c zoDqcuxHF>M-*_(OC3yjCEid=R3=u8sYHQ&?He*1{a={lmg=AHcb^5l+JlidiR7gF+T2l5`0EuMV)hlFI+c})qpWG{pVz+xSJiP77?bZ> za8DR2=ykt(F%39U>_%4TBwfv4!fodHYMlFRn!jpUi(5S19b&yXkcRVtYXNHg8nzom zey&juBEa;HvGP8X>xqeSSK**aN;G%-_e@vj?k$-wKkMmwYaEdL$q00%S`*gOYb#>M zL4FOH?inrRYcXVMu`=D2>xo?eIoXY>&XrY8Cj8p8aBGk!W&-XH)-ESl^Qt$)P0z&2 zp|F>u4hIfKdmDt&mE;}rI%Z$eG!Hk@w=8sBh`Z1yx&ZynUcubH$G0qOHbq({a4MqG zg;L#LWq)Zf2|mg>1s_b*?SHHp1dJ3_LRc5xYY>Slz?gY@u% z>rPG4OcYn1{)#dl2K=!YdwzU`nO8K^R-CV0DZdNk?}v&XAnz3nMgI=l{-xpjqDxfe z@}=mroBNEt9SB_Hoa7l-@`&202>+oZ8zX&l)WwbTv4f$vKRCqNG}i~tNXa?209Nym zv6|IZEvRCgTB~2HD)|cGs`UIVRz(w+&65uwQ-LT{(1$|w-8zq91(F&RQKyr>6elx*vy!_ z4D~}1H1;qw)+?A&)`8Wp7HuWDqYQu873I%2B`8lq&-MvFr`S4r$7#5)u-w)Y(!=wr z?h1r1F`?eH68H1OCfIjHtO2ghL+?3f&T9_J?)!ee@pw~g1z>w<{(aY~PV+a8Fw@(k z98K2A*CTjFq}k-a@f;AI6jcrWX;&8BNFmlJjkd7{cId< zkM*WQERE$h+is70v|O|o@@~^W=IQ>%WIEP%$l5ErBKYeSydqOQ3ICE{2g6(Y;+Sxa zpFukSsl7&Zg}#8lNbm}X_SWNiQUk8FX8Z9FX^vvvup3v~Hr7-zovyyU8EpQUtgd6j zhC{K}_DR!KkaYdt_7jfw^y)7L?*Z}7>$@_3Ex@xm-4Wg|G2HKevTOSX-?YpW^O0Vs zjw6gy%8^1S`2>`wlWelHxt{3S`Lv9g=3HZw!4%)O>OpW#%kq^RM4w_QUXjN)4EO_I z@p-BI6}L=Gz1IsAu^@CAEP*}a$2nIlqZU*INNtBTSv0lIWLZ*o_e}$5E93L*!;xp_ z6$IrXVh<^eZCF*ED3&VG^w*; zZpnaMobBUD8J4I__l3CglgpMhoDOu$mbAhDFjP3`bPE%%%Rv4oL~U2jS(`?EfP8%=N6vZ{|3$_#d7OIj!^kh_E1; zEtv6*A2r(nv5xgv_-8M;qqieTfp-qXri}-nvKTOwBLJPoWP5_YlHhthvU)^a%`Eim z-I-Mm*cQ3AJ^xXo8<0ygBe{5Shbu@tRahN``ExKFtN#%z;M6?I&NwO0y@J>B_+5c& zpt8NAxnrp*`71&$(KA13^>EJR{W(w)9_eIOfP%x5}i+Mb`hDdHr$P%hjP1ru&UNI+no% ze=Wk1yu^|`Y|FvFjz;}vgdscqxDtUsOqFaoxVJl0VrClNuv$OOmA7jAatI`LrHyk@ zD_m;O|M6OcI!rW}{r9n3HO@gT@ynhJKd*rQ!{am`_3+GT7GW<=`rGwvbGYsf8`Q6G(3f=ZV3c{DML2Ub z=3N)lTIQ{6YHjaWfwFLy4Log2f$yPE@TP>OrOiaT#pdce1^iF4y)8-p_bih&1^j<+ zdXGF)G_R%El+lqE*`I9k>sUpK59eGFBnp(*@m-8tfwxp z80UIc!vP`oMYgX*gvV@zv$huDz(nEI6fd#_?smNhN%D_vz-@&B?sWFTZajo}&Z68} zFytf`A}V>_qI47rSm^>(;_EHSt*R@h-(T908w-X^jzW~&6Bg;p+00rlONatqu>ltr z3OFvxMkRKc#W`oTrG(t#4VJIkkTVO03>|aZSdcu4lwoPiPp34kx_+f>xNrx z;2Dt&?X9el{$xY41w(F7yA#=TE~i)UBaZfDpCZ$aF|nGI#Jj>0zFN}IvSL+}mbIVR zppzn=YJ|VCLAMB&46^0Qi=WuA>ujd*=g@=fSFGy4uKp`Ja14Nj`V1Sgy@nu1aEFH3 zsq!@&Hs0By%J87&bG^tgKa%|CHt238sD~n@)SY8VuF`agCSI~g2aU9Ls+H;&ZOHxw zL-x}UA;n&_(eXx@eIJz6VG;dy5nJ- zUGQY^^uW^%&(3&C@a%+V$6|A+meI=a5K^=Q@K7|8JP;2>q-Z2d@eapx5FV1CsAKR@ zG}54$6oDds3C|bsFc}BqVUoyxBp!-hif1gIp?E0TKs*!h48lW^nKUMU9G)HVjK(t_ z50mmmJX9N#JOa-lc!uDiD)z_2WFLlS6dop*>K=|~FrNMJ;6_KI%3*-};-R|s!Lv7> zpg7=faRx=eT6|6Uk$BYxX)_}*K-v9Mnp>?_|3JMg`~d@os! z?*rs}X*<3TlJ6B1?-2Q3&G>`$y9M7v<$EFH50~#Hj5AWc7m(Lz_3y;@SoP=kVd~E~ zhs$>}dGUAdpttwpCq45;7p0!PQ-fsZpHU8=DWCj_C)-{eXN9ati|^{{U+m9 z`CdYtHuK$W-(hR$THstvT)T0l+p)A!94t1D?r@;HSR5>MPD5syLp%(DE1c_4xK|D%(Tb+wmc87B@OI|Uq?I-9DKAWv1#lfq_x2N@` zV6Vl!D9`J0FAB9W?nPDnDegsG{Uz>2`8OFaCkM6`km=hwzU2G29AENzFUOa*{SV{Y z+onV(jf;a1jDN=WXZC-Twn3J;2h+jtgc*X?TXBZxUw$dFx!%j@&VlKr{HcTnU1JRU!L za*fcruP$UIo_$2&b#-Am-QQ8zeK(2c-~s9$EAWnfMju&)zD(IG=1ZL4A1`pd%I2WT zwq9h**4KA8X&bNbWQ7l%9h6Zf>mG52ar?aNclJLN=iSp?oa~&-v6T+^bCk|^P8E97 zZVJ9e|BLVJ$p$fdBPQ$#|1?G5yORfg>OM?h(`BO9qAA;L zAitt183Sie2@L-|&z5+5s=Mc9eT>{kt9y`!4^sCN! zgde^p_#xvJf|sn8@ItWZRFS8tO7!(xb^lh~kDg(|jm{pOByrx+IPYkjsguPPruM{- z)Ib&sdvzDLgR6y?b88vurT#sOC4SEvB%X!eR$ZQ~x*Vdqd`@+EwU)u8E9D-&mc@;p*;j#QihDzk+*EA10C-iaFTW~FW6<*I|rHQd6}dq|obl=72xZY@`* zTbL+cSN0X%T6nM4Nf!Qxmh&s`?8y#u_WB+vQ|_-(_v!mb`S)g=wyzJPlQcGWgNFJ3 z`67qs{LsxcVf`dOa{O(0dUwf(^dT`C*_*Bp*m2LEvbWH=t-Hv2mde`eEWztFS)rE2 z2Wox^6biQ7Tze^`u;O;k-~FL zg}@%_?xF5db(gC9O||(uT1A%K+5|qgSm4hze1^hm^`EQmvlQ=bg(s`7-d6aFN}=;z zEgMhNN&Wal-L59@-ca`&>i(I!f2QtD>fWU8Z>zm2G&COFy<1W@*}ZlZz77sj_ZWe9 zX}E(LewT*dtLYh_`gl>(eSzXRsCXAB-rXk({r46LJW|`SOughsd2MLQ#nf79`{${9 ziNch^-D{<<(4g+o3b$AP1JwO3m9s?U+@NwErf{u>|6bvBr%8MAAbu8wwmVGi=b_c& zUZnExxlrVNOyhk~b_UP4b6Sk?+(S8ukIJry|dO~XDE%$8lF}6smk+s zsUNa$D7;(YEvnOtw2pdAZSgow^V6z}D$RqF4>V~rvK^{%AJ(v?>i&(o`!5hZoG-Kt z&ZFAqeqG^<3U5~U6NOhP{DZ=K6b{mK|48#-ipqJRy8of@P;GkwP1_1++Ezf*wqB@h zFQ5qrG~s|IyiD8PLhv4KdkeuECP~^qt`c~K%6X#d=m6Et(+bbhGTnBn#BbB~_mArS zqq;YoA>kXey?$TA-`DUuZL8{frc58n!akUKpp81XTH1T(7P**5CZGDK9rf0>u=foT z-@@B9J!fiqMr%5Lt?)Xv%T*@`-YS*nI?OCl4uyu-^(yoA8ppyX(0gKB2iFQM=N6lF zGCv_UZQVZ1&fHb>=HMW8j}iENEz50M4!Uc)?$q*g6y|&>%L$sUDh*$(_IAId+vjQG zchm@;gGwJ04mNIfQV)q^;jNR!?Vy&YTh;a-Ql9&^Nxa`^UVKl>{H|J7K2*FLG=6W5 z|Fp&*ukfoHzENS3juZBiddsBa46odON8|0P^qy5ZRSM74@V69(8t>Pt!$UM3PiuIs z;$5Qde<{3Ib>E_RS=Iey)%{A1_lVkDk2QTwd(dM|e}#J}+*9E|h5H!Tuu8%kRta9i zD#6Qj+jtgF=rybodJU_RZi!d5u&=S-s)hX(?xAo`g##7tW8hQsGpEtUA}H~nnlE&o znlE&6-8P=3BlMq|FZ7?9pL9#S7i+dN{9ddPzPWIZa?0~!O<#rm3%DiT7ZwN|3tJb7 z+rmxrh2QTN?q|~b`-OuP9%x{l>Z?xmRku*mRku*&uUjbTsaq)WZ&H0_7K?r|i$y<~ z#e$bvEO?p4f|pqw$FumG<{xbMZ<;T1ZJIA~MQ)KV^0#im>!$W+;nixNSI-~B$?fdb z^AA**bW8bdR=c+FbS)niuG8{p;j(toYXn7(W$hyOvUZU#*RAnt4t|t!Ez^8oRx>E! zK2Y7(-?{~_T=O}CqVMtrk`LtzBp-6!HlE}|`2xwG@&%GVxo(X&aStO;`9w)~`NX~n zcYk$Tf9n>!MQVo;6gd_x5_uOb5_xmoHlE0_XpzXfXpzX9>(+RamG5McchO{#Ymsw{ ze38F(3*JOc??g@SL``qxmiUpsbqoHhHG7mZe_z#d`)ZAp+g!KAJ4fX`N98+5<&E4z zKk~P3;rHg0gAKnorwmefU;($pYtVY9exlR|^_tH5)3@WoPqzN_jDZbmpABbbBwItA`kR1FLlysZ6*T(^xU_1MeWZ+Kbz5xH)OH(Tk?R{FD* zey&^S&z^7b_B3+MR{FD*U*wi}n_9}hPWd-=ls{`=QH8*kO7*W)|0?w_RsT};AFTf6 z-%vWwDII|=mFi!q{#EK&Yz)C-*{>Q-1ZP2CoX{cP%x{MytZ_Jj0j zyo7&Ih0?83IGC`|lZAfP897?YziD7c`ST)Ig}|2bi`4%G^%vMt{tI;rY^hW_l}e{l z=~OA5N~Ke&bgGn2rP8TVI@L<2nsj`*k%!evbE49$Ce36Vr9V;WS1bLAO21U;my$kc zmMYD`O0$$S>92GKE1goMGg#@AUo7#;e`#P*g}|0d^{-U_D)p~c|7!K0sQ#tuU#k9t z4eZ}4_SV0%+}KV3bcMjy@=M4M{x2Gst`OKNcG$mD?67}Y?67}prN*z+_*EKT?6ZHT z*k}K=*k}LNQjK4#@dpd+H1=wBo$Y^$*l+(%W4E5a*m3_(W51ri*fZp&ALJLi1%GuH z@K1|9BRvu?ZR{ENU6m(EKjBXDX)V80_53TY*V)7k&P=B!#=wJQC9*{2*-fGIH)u+{&v02!Lz*bZC5^Y;2N?&2A!t%@2Uty`h&hp)rufkG+V&jn>))|}2jyol8^W)Zu z&5t`JZu8^TiOr8wn;)k(KTd7FpugJUIJNn4YV+f|Do+kyv3Vy)4j+@gD7{j~nD5q) zka`!GPNY}LJoDYup~!cIQl}R5@6`C68oyKHr=2{^`?w5|OjaHnPJ4{L6ZH^en5#CR zuvB6B73#0BRA6WM9%>s3OAVZP?W8jJJ3ce7t)V+R^V-P?|0(J}HQ_I|IXoJ^U zsjyUG`IYLguvB1Y`2geJS*fs8pvVLMF*)Fl@rT>-Jx1v(ELB*3mHI0z71&w6r}9-; zDp1NqfG|GUnRlCf%FdKB;rWZr%#@9O z;VWgt$&uu9?IbI^r1x4)@3oT?{+ixvrzZS0y;7fNXG)z7DE$%G!#7p`3e~?;{X3<9 z1^q~PBoFgG!OO`+J4l2%xo8vdu-5V>l|f;t!t!sazrs?1o#lHO|ISKBSCpYQ*WUkxB({YQ=TW->M%S}0MiFcun^A0ZQ zXXd33F4-_e?Yh+&f;59P;eDE5Xk3M*f%s*eK@!4pNwKuR2)#R}E5lU;($pdsoM)>oq;=H9hM~Bt7d(Bt7djJ?k|+>oq;=H9hM! zJ?k|+@9MZW2lkNkyz8LI|85US&$~Sm?zL7_8*-Fdp9;;Bx@Ds z`+-S)&G`C(NizO^V3Lf#ADFbK`VUkn+{@^_xD51gmv>O3uH=jr;uy;_cQq42v``QE!mbR0pMN56NC%%k7CCgENv^XT{L z`o+BqHC~Qe;*F^heMV69Kc+_XKc*(`UZL}%D|B8o7mB^Dm}sHc;fjeCiXE<)DDZ5p zU(VM0;ICRf|ElHbPR)-yRbM-4{cYhb>b|92N9_rksk`xkKA zc>8Gho(cyRa7(-?TF$0u`J1BUFV`*UpE60x-xMvEQzl8d%ymn=S9M+K)%lXIuj+cx ztGZ4!MBA$&+Aa;zc4~;OI}OqHXNa~(Lv-C~qw05~+V4iS=Z$K|8`XX{sy%O1JAPK@ z^PkoE{AYDOKi4hk-Kg_%8|Tk4wFV*n#kC%Gj{NqKg9Jj7Bov-Um=O^4J zXgzX*)*~mVo=;G{52=|`PWv39`W&MAJY4+`SO3GE|6CLQ@EWPt53dpXS)}D_k(Rqf zS{`%Vk}nr)x-Qmq<+wE+7i+pMPPpf(oy=P(`8rS26}d%Uk-v3IzRpv7nzvB$ah}>) z6okZ<|@6&ZQ}{v zT;*f&-drT)@2foTt32;3-T=*q0h$j3G#`%Adg3Up zCyvs3B63T*BY*1_Jszd?#8FyL9HsR^cl-wd7G;3 zUj)U!NY{ZZe6CXFA1&NmA>+Tz72=Sg*;*bVx5yFsTerm%`e(P#HSOWq?NUA?x5yFs zTesjfs$Dm#T}Nz4lda;3jq?RUBIkKAGxk-v3|oh)~9h@C7~IhU(FFIRaZf3Xvbx4qi$_G-V|tNmW6 z_Ish)?}ci=kz3@5{Hx0#n$!T zJYMSCH;LFiC62slpC}>+@R&*1}zVf zTkJpbw{9s9H)wgdLCeDpYWI;_>_76iZYd9&G<};ieVa6Wkz3Le`CGT7@57EsrW}5F z&7^^}{|`GRt9!D#r>c9Zx&{A3T{r$v*Ns2ab>kd=T{r%)NY>dtEE>#wD)eMOY$@N{ z$k9^1kH}NbL(16?iz;|{nc+O-3^~gOsXq^G)6E0hjK>4oh*zm}DwR&9(y3B9l}e{l z=~OA5N~Ke!bgGq3HR7+Rr>Ot5g#R@0*Lm^LIv+n;=i^5g^4EFt(K;VLTIb`tEKd%7v12Dk zl22>-V3WSiavrWnIxB`6*jlOnmFi!m{-x?)s{Vu3U-AX%Gx`J_(PyjV3;3(QE-tR$VK3 zU3IOg8$5r>>#A!_9pU*)URSBkt2D2xG_MQ#YaUc-URP;ecUhhszLM8YjvPL5+pbdE zu1eT;Ri~ym9k=bOPED__Pgd#rWL2xIH&zw$*Y!!rW!5vHAAwO>%c?AqZX=lxX5{h0 zoLmSqGDTs!J_*_8(vBgULRp`L{}t*lP}e6R+aAWhQ`RRNI^()(I7Muup)+0&G@K&3 zYUp$_QI>4ODWa!zpl$cPO}~d{RoWY$*L?ak3E?X7PpOtNG^oMZ38ki znY?MOR4D6m@c)+jE0lFPvC&!U2cuHE>|Ed`?${ITG*`n@t@Ux z^0V4cepdV8qqW~VTKnCjwO>41`?I69A3Iw6yUjXpTB7rzC5xs1S)%izB|0BkqVuCA zIxlMRA}IavX5Ek9tn;stTl(vfzjX^vI8)OT&A z!SB0PQ)-z1j{d0+n`zj>d z-9xdPx(^U|N544y&Z(=*Xe)*9ppf|MBU!R~XGGTG+WR5)x>oLqxbgDtM*ir22%+)r zB!vqF9-*>2*e?FjJrJv_DBGvK2jbmth&)5r2^_C5JT2fwN!eW#x_cp1M^_yr@?3P5 z=%`W8x%E3O7*4!XJ_?EfUEXZ<-UdCllf1X#{p00cg+j1fr-T=Rh3;#x{)O&qu>QIC zG?;XoJbZN0>X2!js%QJ`{R$4^fH1>*=^3P6)#|P`ddc=$EpB%ogT0qQ&metU?bzMN zpgOYmF)UZU_Fe`D7YN;}HU8BT)jd)8UVXf{k5qhnM}vbZ_W+f9fXY2U@t&hSS%YG&uXZvah7c!h6+D zEwuMH?5E|>-rsOgTJA}n;a^6Zvv)Um(A?>8+d>o1$QIq-ATo_r zo$cIDXgPS0xZQmY8t+!E1Cn<&>^vnHK^Xu?8n`$ZMfg#*_yZdMk4_6l8~^zd{>O%9jbYui-_?xJm1Az0|X1M7d!r@i+;+nMCO2f6ngh#hXw_O4FrZQM&>+CPOx zSADeY=%Z~%A8jjecY%rPpz^+5_gJ~R3)J7xR=N24n4ahqP~52UW&fwJmUPkSpWi{#4qG1FllJ68EZEKG{dl zFnETC>yK*MT|ZIEk;Ae5KiiLs`eP9-=O^XK;a>TK=nK&3>t59#pv$XCn#S~xziP&` zID%m0yG?P&J}LgUdN@a28XN}wn0R+wY`(LF?qvG5>SV7CUo~f#FVMWQcNW=uTU=eG z`f&A$)+?^AuyuyQnQCKzCXLRmbnHDQRn?NN`zJcRSv{F_B<~urcZN(>yhjwT*!=37 zkNSCiXM-{kImqS}+49{|yb{eO8`r{oIFX<5wQ&he*7beF$q~ifvTQz$ZTZd)3>^=~ z&jxAZHp@-=%^@+fI-g&XM;15A89H5rIdry?7pA(IB)s@d{Cs{%x=D8}@cf72*3Ivf zJ{He+HzF+Cj9;iSu*|@Ad>8W1dh+J`CY@v&C`FTcxFKI5>LC0Y+z zomp5&4(p$kN75iPZ5#`uxN+U&^N;-E=@9zXFQS9^ef)f~_$L01kvv)bPC`GP4U748 zQLieev2n^qTTjAmiSt?DBx!7eyQ{Y4m*p6t{`9m3HT|XmhNdvdOlmueLpX%cM=&ioDy}UXY(jTY)yw zwwWss&u<%(a$0v1!VXoBSp#i&HYtBlb}YjXKLL9xejHjl78a_jw-g@9W@U8H)H5oN z@^@j|>UQNt={WZm_->81tz%?a&*`?HY{x3^1dQu48>qWLy=m*p|8m&HzHfG5cj;?b z*j4;4#xH}t`VV!T@5zzN%9n&)l^evP8+g51h zv@pqkD{j-5cp@-mF8NKjeRA?|D|B=6ql@vAvSd9OtxP74O}B+z;AO(WnQ_oH0fu*ZNJw->;JzIRv=yelP?W^IKOl3xxl!<>L(X&r|s0X!kqTWwqsp` z`(~tm_`F~s=_!Ja{HLqsH`6>@i({(F7Rwm6HIwLeqTRsYY*K0h^IYnK+r?Gyd@Y!USC z(hE29p{xG1U;8*)vu%}yh57)V4CG7xzC2dGu7p{9!fmpv?FKlW#K~^Am$YA9^#7!M zll%&~yG%cQ#JX<2K6l2C)G>Ws_5ZBw`BU??c5GpeJ@?_#vegr8rjOa43fL8YYs-Y6 zz@8m1%iovB%F&fDi%+;M_MDv8Bwo@l+gEMDL2W||jY;j8)xtvY{;T}092S1wd~N-8 z<3K4x1)=Kk#%+X_ZVo)pv_;u{6&B=Y<=IAlRxZo$^P+3%JNWsgr%cN|%2ljy;+LI5 z-xh~ul4})q{7jnm+lCdQk9@C#4D7(9J#i}|FaIysiTs0-M~bhoCyEa_G|6j!nnN`(%ZK9f97TT zv)29p(bKv&p6CDVW#a#{d|_EC(}&-#?zDAXqD_g~ZOyk&8~!=#dt2&?Eyc0AA++(V zpYQ%ZyUkyYsUu%sIre4y&Hr8SbFx3%7d6L&uB&>n<=DdPwywJuh{q$l ze5~CUoOk`NviSmXZgV>K(>aaOZ(K_qWw++usQHou?fg;_Cgz)T9n0p&|1U86a>F{- z7dE}w*LE#7`tGWKj^1s4B=v6H`Sssrd2;w#`WD9d*mV9+f!Wd{*2Rw7kFs{(MgJT< zd_w(qRh}HaR__+Z^`E^lIJLyLw?p^W@m|;bKh?ahCqq{GTYK>3>q?l#C)}2KU96w3 z>*4F+y+NXfuKMTb{}bl>r{-((+rpfD-=(LY-a{uyJ#%BwCI3&E?~Yei`P+O$zJH=H zi@&Y;o}9ZUUeYgTKHrXuKC3?6C#7fcEc~?cB*$@OTK7#-SSye^${y)`AFJW`Wo;9- z!V6myeKRcIWBW?^!sutiyFTueIY>L_xHXvM|H=7knNR9d-Q<&HuF4g>@!z*>>c{kudCQmpVoHkZvEw*E5KP@M8Q2hN35hB6k7(o}s!->RtUU z-L8%eYm~cvc7UohawZ z)5eLQt#8Uy4hx-snbO|kSwqH2J`oQ~^V7mani6#t`Ln-jVJ?5cw{qr&yEG?sQAlnV zKks?MT>6FRh(F~5PS^G_fBx}z?zL@lZKKYd4s1HRglF^4!fie8_gU5dh3MG!$JWmg zEbFtK(cd%VMYZ8Q2N+KeEpZHPUO7?-0^+p$GnmUp7P*%FS; zCkqRg30IbmHS|8=`8`+1+PcBjdx^Tk`8#_|+Tmw*b}vtvPV(ATw=FZD%eg(5M|Lc9 zV^m*8`Sys|m4;;>(KbnO9E~T$-{j>p(YFo%q%bFcZ9Xe3MA!D)j65%@%&#ci7cF!QPcxq3c<5e*XBeI#ct+wGfu{$aWPJLM#xn*_SMYp3 z{Qe|-x{Aj%Qr@lcBHfm4j7OSVqvz{rTjG=d(ruv2cq63@GgDu5xM!Yq6wk3X2{;knZ#wU+0$)AjG^;<}OUq95- zaa*D9$7h+LdrR{8@u`32*_Prb<)>b|690rP#HS6k;$a;z0*@{G%meZ*0(-v zICPT-^`7LxFw!dIpA1XZNzK5eF35W%p8v<)dqCMy9C5$9+Eo@gX%oA57hPDPmK8uq zB1r-yKmxH!fJ9m)5Gbt{k;5X9F(yZob2MP$03sU`O)v&bG8iymjBPMrFvh(9zq)It z?q~$keBU|myr*;SbXRp%b=9wX=EfZ{ji)~)+ZyK0 zx;CtAy?K1K-aNiq@5=ge&GmYdzMf^(NRBJIo@Lo{-8DYz(tW_|!HVo#F_v{b%d$`B z|5NeP_R4xi`K0ZY?~3d#pY-)CD}QT$2p#4xh^t^6GU+q@LhS#DWi@{jwaWZH99HW0L9y-4rW1e3FDb);M+6#>VH|D;ne6c8s>bOm?cvs+sfs*f@Qxjpj1P_-SsmC1=VSlX=?bCObwJR;EAW(?|WuaRDBBKB%5K z(U-AR$9M#=g)iDx^7 zs^fZFJ(+R8vgKT@c+iJ3b12}^4-fozeerupwVwlBD;_Ir&-l!1W$hV%RqV6!UzOZf zWSf=uifprTwzk}lbMatIz7OR4a`w4Cx`$P-dzX9C>d2qxF2@Js!E=XkG%jPQj^_dG zvvg@a*W8|SjA`@Ln2g1onXl^fI?k9`I;&6DtM;~DtJAtzYZfonTYszL+{$YR`kRF~ zwl=F%4yvQf^NVa+@!+21dN3CA;kDq$#;yO4`KHI{$7>K<&XFFc?x)7ve#D<~e=PQj z#;E7Kt$1)P`AGBlsd47j8hq3KjK88W*1V!I`l&D1DxK4c#<&mc9$Aqe^K8XqC>~sQ z#!K_pv8=VRW2~S4x~@7#U6!79Kc;WRIPM*TSdihQ#4<6yrN z9;5Nt0gp*R-X+NUhIUu9+v7o|qwtuFhw2!Ez8s?s$H(A7-zj*E#Dg~UQM;9ycOvYW z&qzEbgg)osUTDQ*dT6Peiw7CC;$dZ8^Q@kHxbM<>?k#;S%IAkxJajINO`r6bjc3QG zXH2$fJ>&4fxUG2TJbd2I(r4+IEA_2-s6TZY!|F8;wpOn>s!r>qJRJ|lrOjb@kXb7p zs^=ce($n7NOMCT6k8!@NamG%MaeixS*Nf|`b8v5H9n2#=#vJVWs~`2s$@Tt{oK zakBK9KN&I}bFsdBy~yWg)#*IUL3Ns|)iDSSM}LW9r9sOpkFs`mJb;@yU_3wBkV~Dr;PoY0GPX%49_y_lWAW zK9#vAIComMI`-+OHkz}Qb-kIV&cXaz@nFtYPqtQ1U&_o?ZFT*rr%v^>Wj^WWOAA;S@kqx?KaXmhv~9X3Wlwv?wz9Ql-;QamyiRLPI?lROM?c*cR;TAM$J2UpwR(-) z3cc<->yzHEI;MWiXGMNlV_F;cg?f0Q zabNKq;JLwhSSNMNQRk&E*MxpnpVldxR@iZ`(VuhcHLVqW)pI?v^vsX*s~!DyEmTLA zdJeE=y&k2CqC$cXt_TlTe9wYBxDPUmWcJ>$?v z$22$Eq{q}x=g;!X8Y5?}JJ+9UrRS>3S_k8&b&RJv#^Ia?;=wqY5BKDtAnRV>TBh}6 z!8K|P5Bk$y&l$#V#lz~ED|K97wsy?!4eISUIdZPFUUNw6nM0O6^}1K>+>Fmy)A3L} zTjt5SRj2D|b+%sGt1b1m-t<^2#;LP<#^*kzOsSB7K&v)urPzH+vrH zIDNA8x*lw4tM1vK_ zm5t8DxoNAhbPYHMYvlTIUL9w?D;lG3D;~N((!M`7#y!V8c%Iw&(mL*8>a303Ys?`% zrZq92^!SgBvDPdfa!tn}$Fwe;7rFgZZdo?0SJyH<&N1%ObX@CW$FlUAdn@8_9k|xy z%ym?mbMUipu8-B}dZ>;qb5)ssjKjRGj%@Y4m+mdva1Lw7_`J4|CGD82l^KUM@xlGw ziU-$$w$#yI$vpm)6<2nLA_IILuS`3S)50$~Hgir#7ltJ6HKj`^xgM(mTF#$jBpEA3Rr zmXB6EXiFYsmex_$np@E)Q?+OQ`k8^%r+t`n*0}ClJ4RbQPpqCXbw60WwWp08BWJQ; zt2vWFD<0&}*Z5YS*4fy+7OSnz#piY}(l|&Yv}|>ukq37i-cvHD+4R9PIv8yY$?= zo~OrjUOUG4+zi_BW_ppVAWG1jx9G4)gCXvu?8yRa1-Mdyt8_uaVjKhb@jL*H% ziU<3u*FBS^=blOH>6_N+I@!2fbIxzCnK~!OlmlM_>iL(pm$9y8Z}DgS6`i`{7yfTc zx1wJI`rmmqyZ@7JW%s#@Ae7%r^Dg~o57~?^6)FxMM6t7oYjl|@y5UH}i2#q52=s$bl5G{NoRSnsUYGzhc)!;#@ z+C)`!^t1L=6&<~*pQ`BSQ|%vAAfi?Sf(nJJYLIaZ>^3v1fM|%QI`{Wk4h@o@dU%lh ztXqlHg_cL6plyN(Q;H*k?NE_MiPXKjtgmdD?PJZX!?4Kk7%iF}u$eQz{a{h;D5{=8 zHAr+j$BylDW{PH_DEN03sZ0NMpXF{rTwB6S@NmW186dGgI-HUphWzn;&JHA7wk= zV8}KGNe4pK|$fVUf|(U+u}l&Pz@l(|tvm58XeT zn=xBYI)?hRz+SnquXgOyM(0wQI?gpAHLkLbvu5^HZcE9m(T=lD$~r$~GS~T4)_7`f z>*biOIV+y}&kXTZW;b5V?I`HfvhapSHB5H z&%WvzPy21ApWbt7!}+w&+U>cc`-6JgXdWuFF5Q2&zARhnlpp)*+k(FOvd=M{M`h~h ztFroPttz(#f0ea1l{If$BV*e-X{+^VRXRz2>Xq>OV6TkNKtJr(-E!t53(L zO$#2XXFokBZQ6`Jy&u$GbD}-3PYdzTw+tNPTOze(eRiK)F3d&qp&k2!@z8p*#u?Y{ z5w&j#{>ngQ#z^lAE2}@b(^loSl-!<@HD6mB{cU~BRp+NYWsR?Ldfe7$?U|pInU9q< zA7x|bNzakCX+f+sH)W*x&_-iU2y@ehebqBZ?YEi!BGYd-edcV>E9R+rXgxZ=%6uMQ z)%~IMGQRq=9?E=Zt?cW3I?j6RxcakJ+N<1_l3Ax6*Zgh0oXgfrS?8xc`x;+m#?*SU z>@{DtSO1x*c+4*yKb?!tqcIpWJ-^!6dDXtf*t4&-v9I>*t37knew*npGJWQ)Hq6JK zZv!Fop*gXy^JwmT4z~LzJF&CR3Wt$)S zHb2T5PyLmr%4vJ@(EO}F^RqJZvohnQbJI9>4x5k7#oE{$)V>Ar)t-H|XJ75vS9|8G z{WjBIWcsW@ZJ7VS@X)*|>zq2SbE(Ydcf0=SamKgt)Sme zA7zcF{^@a>kF{q$R%Sj{W;~mV&BM-N=eK%0uiCUA=8vr->!yv`Pe5Peu&;XNuKhOC zUu62MM{Tqg)~9S)o93e9I+x0PZeG>3w(-@U`Eov$nVXe4A9J($v2XLEZ1bb6@zme) z&$1^E&CmKXKP&5ANXJ)So0rYW+S^>Ljm<&rTQI-cv#<8-t3CT_&wRDtX8MavpEalr z`3%HkFdkY1Wt~&UbuN|pTx-`qJALX=vdfet? z?U|32nU9s3kIlvAVdt>(TfLoEZCViX$JUYDXruNM(APNZtDd=Qzs>YngX(Ed-mHmn zC*rXi9$Y)x@oP2q7vjOMtk~E0srq$aT2DW|hvodVXa8V4sAt<6TKele{OZoeRzJ?G zHrm(u8IN->3O0v=gIMCIbI^i8FHK>$E9+dD#s(_c&69mCSjdA z8t~s5cIvoBjze&Z(@q^v%CV(_{g>o84!88|)bX4g$Iy3U%8!WuH1YgUj&0)ky&R7g z&u`^;n0S84<3xIXES@Kc&uU_QsT})=^|f-W6Q3*O*qd`6NzY#5bEh0nktjv!-z3Kq zMbjkx>*Y91;yx|MNfP%JIgXdOFUWCcM&FdtpAdhn0{WlGaj|%oi_gzxv|04G%5f_h zeNK+Mi_L3toFH*umgDZix=oG;%kfY-o*~itNu1l|xUIx_L5@=;&Kq)^EOGuI$6e_A zGv@b{_+vMr|Ct;Q7thY(bDSK%m*Y|5`3;Y|)B11Xd7AjFB|cZmv01Edlw(1Bu90Ic z=RB64Yl_bqa$HY*Zjj>u@wroun~Kk`mUwVcg_eq5F#HL1U?vUdUv3yXD1I7McIrgL1 znv8q4c#aUyr{y?VJl~UJn|OXE$GPJ9F^^;D`J8wjDL&<5eU==n#QGvRt|dO_%CQ&c zTtLr%is!Xr?ZobOIc_3$H_Ne!)}p;atnmy3&xho=gLwWyj;&(zo*efQ&$oEog4S<| zCw}sW{#SB5PJC7q>r>>|S$vL{V;Se%m)5xc;&`iA^pUX}x$6A1r>yZ+PLJFAtUdFyGV`&r=A&%vJn1>oHZ6#i=BA7^AKGZl z31M#9u&;XNsQot6Uu632rq7)1dBr?653NV%SDDZAtGYk5UdC5{)7O;O`RTaYGe7Ik ze5|bb=-hT*jX@i$w{xjYONh%j?5jQdYR|sfPcVA+RnL62-)8!YOrJHVjplFn_&|)a zMy-jm=Aia`9k8nV#l};A=F9jhGdC-9KIUTcqipkI-{wbI@ zepY6@bZ#2Q&SCShxmX*UgW9(szS^^|_Ux-Y`)bd8wclp?i%g$2s15TU7#^B8Wt~&U zbuN|p{BGAjJ!WZkq;`w8f49QIYu+_m3k`io4T^{9>3!upggYtvkGT<21m z&&{j4);7NSGhfc9GIO&s=VNX*KlW{Ylx=>LHJ zS$ms{wXr#9Yp4A)kSG48}uipsaK1xXz_ApKI;< zr^gxJ##4Ld$M`DidaKO%fw6<&Tjw0ngANbU8|PW18ct!yQ} z!}PW@Lafh2dvu7^J;XRAw4FnY<3o%8XPdd;o5D(bi{oRR6Jk__7&nG?V2E)?Xq!Wf zTSB{$kA?3JD?8Q=F&+->=^=LiAoCAYX?JSSZyMw~L%Tzm^ADljFU( zKR3SDt;BbwKKA}0)>olDF2q_b#5gn94GiN^Xm<>DuZMOOzcLL%Vs1ad&84h;e&pH}SDLmWDXJL!4iR zwh-dn722&roQFfZMTm2MXb1Ut_!hack#Yt&`u7qJ`8PJi1m4B=Z08+^X;~b z^>K)GWQfr@_?{Koy5M_JXx9rd&JFFFKCk^5t5=9o8`_&fJ0!$aF(AlKhIVYwzZBZhA@*~j9qH%5x6+jzzY23q3bEe{ z?Yt1{+tBXoeL5P$_*Ox`dzfQFh`md&doaYkGT3h%?3aahRPcK$v|9)N$3r{R$HBMP zl^y4YSUZMTe+X@Bi1k@$j}EcE4eene)|bA;_oI~^uY_19g&3;^-%CT=C-`0)+PVto;I_YsvHAB0$kh8X3+_w>+K1>f^RyH<#CW@vl)yk;;~w-6%=wgZFBU7_vg zZRI+BWtex1;Pczi?i%KOC$w`ytWQEaGsOD9xA+#n62I~A*U0t|gh41w%@rAmNbxmj=2{E1xzE64|e3xF?F)rB53O2_Do1?tVc-ov6Y_1G8 zHwK$)yv?Dsxj&5kCX7Ae$M6k%WycP|fA3&(c(6Ix+u(N=l^sii%|*fH%3yPew^`7& z>}I|+sis2*IxhD?eyfVTG5VAW9sF-Vp?Er0@R9??Gpbk&;aL?9f$*FPM?iR9g^qJQpWnrb zTfO3iSn--yycjD!_llQd#TQ=ja;*5!D}FDEu4S@T6_qpQ&Br3jT2WXCLDs3F^59u* z5M+%Y$e-KG8dY>|ojIc&L$XMeW>S(>f;3+wSt3a7i#R50RMC0*9PyJys^~mxfsDxt zRdk-)K9`oVJd|Wi)~BNLyt%C$lLdmb;1Ei(LXZ}VpDYoiL*{c#)~BNLf<+?90#TBf zvN{!=7x~#`X&@~+jDE5(Pc4E4#mVr@}*uy<@^O)jiW{Aa`>ECb9py|WBu5nvu8m# zPK7xTmU^Lm)*%p16rnSOxsXl~siOa(=wIbW7A|f-0Mhk-L~g)wqx3r+4fU zL?U!KB)BXSvGXB*@DXo0cji2}J?n>NEt}7O`uS8*o^k!ytDN zxzpb0ZYAArO?}$K*w)?^3c1Ei5fQg}z%IcJ73gw?suHI&eH7esA-MhEqYMv0%N`J{ z!zJWKBH(TlO<}Z;D7w&_m$k7X_UhMwEgaj76D9HxrP#Hooun3GO;9^girtZ->crcg zoG;yq>0H6Pq~Ce|g87tQ7OAV;>}G$+uZY|$zWGfXm9L7j+nm_yby2M56}(4|n7!f6 zX2oW2c{8tw&E64h*TZ;!9Y%jwNVXOagDKlFxXRwzI6N;3zPpLp*iBy@ih zU1vsw^mmcENGyo|^rA$8_=UHnKcp|cG{;L{duf)JzVVK8g7_a1E9bTIJo>K}7K-pc z5xOm0G-qCG`#~5j<2#>kGD?e#cFgs?&UG@_~QAz?(P_mdwHjLeBJ^+gYF!UdwHzL z-DV--0}ki@8y6dRc~_CUOx$ha1TJ!mh?Ty$iC*xPO!k6Ldv`DR9QX8sPiUGK{Oo&s z!OwJ{2wk><-8Pu%0zbA;E=yN=VTK5|iO}^(Ud8w~hl_inCtO8^GS%hw!aPD00 z|Mx}Fr3oUh*WdZ^ehqkHZ)k$zf1>C#6y36im`BCHA?SDV{Xv_dUoZXcxZvwme}rhd zP9p(6%ZwDc^RzyTDV-`(CGG@N)^&|(9UXW<_5a?#@%0^*y|3sP-_Y^Dvhjmgo4s~z zw~9VpJ8on~tM9dT#gtxUYmD!7X7BOkQ^%L@Ik61w#IoYqy+@B5zZRuw zaPpF-$#{$#$%w-zRxyPkm_&-An5(E!zNq0^6lD}O6-Dh)<)&1*NpVHnVF=awimF)A z9!W)mk$$hT$*d}x;tOI`(Ij6Gs|uM( zRc_xZw|AWU1dJB9vCAtmbx7K`s`&n_V(HT^m5FWq9$SzDT-pQqFNCFMeQlI zphFo&%|lTKRk=A;ZvVKV=@>$_W;qT@DzeKl#}_2avA-|KEXRDwoS&0R<`i>fz6cSJ z@El1P9m>f3Fl2s6l{>h~Evj-0Dy> zgE5H|MKM=V9f*Kh4wG8Yp^TzBP}DJ1?x-qvL|oBv7(%sXIgUvxvdeLlFG!Z-2w#v{ zj^iZrB?u;&Q_Pk5FAxC)>G8p=9qaU~dxYf|~-6Gtr`2gCSGKUHcu6XB&6in(g}B_g1NbEO1yD5I7$ zP|N96?zFg&OQ0_;b&IIxa*V=U2IN ztK8XfDg5lb^yEH2DJ44BtjXD{R?9_F%gqQcwNT7e3qQ<3Eq6!>=uk#2m!XzRs@%nK zA$((ATF50yA$CnJUbQ+dmpb@9Tk4>gtB$7-0qH*?>7zp#bzF}+uB~!cSGgneA9T*?RD^h4kL1r0An z9dF~c=!hji(@Oi$wa~4KVXE5TIaEP9{hgQc} z^ism;MPalCw8DsDE=IM807mPf5k{23=nXJ>y~@2B1LBw8u-ni#^=L`~z3yw1J@mE# z)BwxkTPZ+qCxGl83NeJws~LO>jP-UlpGJ&DZzX)*6h2MR3LlEO_zXk@)ZL6m_)rF) zkHP0JRqlf-_vaYVAa6R@H=Cg;Mf4YxqeX#JM3_d@A&-YdCyO_@uZ@0T|_CQn0=X=zn8>mxt@uAz`tjHA`ph1lkXc z5TguY-Ks~sF4g+!%KqNy0N>0(Q;MrgHH*YG8jR3 zduG#`i?OIjLaV#bng^}WqL_=;VTb@)ZD@oRWzbp|wAQY6YsSD1_jX74=14T9z}5yZ z-Cr9RU`N5SxPEo%liUUguqZgn{#w&hUwL9jGx`SE#E!vOw0=TtJt1~1v_gzxE@G!4 z0*IY}Mu<@cu{sc|iE;hh8}a8Ou>A#^Qd~7=e>E6fXTY*ppTgCU;IjKG#8`P+XEJz0 zHm$QT7S$)THWXTCLo2i>=Av~uB7ne!XoMDJ&}s&)jjLUs7}yowj=v9q`Bi92fo*K| zS3d*nYFHLGtuB26?3VzGf}`xOKC8OFu3_|k*~G5JShQ(EtgjHe4q72bF&DAh5djEp zLL5LYuA?+Y>?wM~)CKSVIeoMNubzd!_J{)r@v4rOG% zA2Q#k+U-^CrdGQ>;^hB@(bDDECrLiq3t93hh08J3XD^@P?%}hSPjQ!Dj=}hjqa5Fo z#NTwZN@-tXDk+U(uF@*;b23!)UoDL?N;?3h&8~JctKIatuFe=j&1O+%Cw19Hnd!@t zMVao)GK(@tGVg+5k~zg(nXltB?fcJr#;L2>5mVyJXGEl4tt<{?F_ zh+In#N>X3`wP4wDpXDx+TKE%0sfA*$S{e`mCGhu{a%xaUEr+6(#nrAoE~Ef`X(5Y~ zLhKT>uUZ|4Nga)dE_G1MRY!kBKpjO%A05i5qXTsuQ|*qbc1Oge{0u{-yXlyul;|k4 zCP%DVEyqbM0}x(np_r?dtq}nw43QGhp^REiL@mcxyCrcU+dyAh$ni-bc1@P7S{)}z z9or(h)Il*<9lIa`(%(VSM~5=%I0JQ@UhPh+cBjOp?CMR&`(`&ZrO&^o`&E(8e9kt{ zzx?fb@vQ37oq2XbAqtLiik+5Vh)zL2{kh=;20J_Z`F0}4qO+3c+cSmHBxr>Z#axW` zMFgPP1C5-2l)>m?FuJhXogV|@AC|zb)i=}8lmfcY*CubUE;WGoM_uU6SzmrSRdOiwGZzx%ezX1k`;X8sS43d~N`r>#E%~)$Xbo zQM)%i*f)#Olp?wgCFxtLn+>8vU|GDWy7WxCIYAT!N7+Nyc+SG;stiVlGT6=8j1I$C zbW_6UMq$LCUJE0Nxfq>@2w-$98ev2kjP3-ZJF4AnF`$#Y-O0Y;pIVgyy2IBdd*~hm z=u}u1?@j@_Cjn&lP>3OXZp+|v8e`p)&FAMBi|$VN+$DTYhgSGd%*E$oL;#<2&~;zlM&?x!S!L1AEBZJ?xuD(3Apu+3c^^46sLGS$s8h{=Jp}i-M!=`sdj53J54PtM`xcIkXFnZZHzeiJw>rJ!2 z-Zi*hfo1VeDO~R+xa|H4F;;$m{ei*X&8GD##-cwZwB8X~{IfctMKKqxKKO$hfT%$u zv?zmCpPJFGsm2v*Tz!qJt8q0o`e|$t2E~nQil2wKObz^TSW`{%A#|a}U&;7ZupWK= zxm#V$4NI=XTf`+zQ4Q2r@!jI*y)u6JX5JMJx^Cpv4g6}gFJ_H4uA#_wmv|6a04FoO)30R~Ke1EyaBrf<^ST((WP*i&X}kA<5i+S0S& zriq4`{uUk#cTo71;V7w#f08M6QOs4>97I4}`$;+IP)1!7QP}UgP$war?xj91nxyfvIzPc2Z3=6U_DFo#}p!;Jlesdt;Q{=ar0{2K{1RA zF$z{@UE2~8cC#+eB2oewmaJU1T=Z1vvF zSPG$-s}SCZ0EMiMMhc;fLY_b&kJY$GYTQFL?!g*&e_Try42nW# z@OZw)JzL|Ru5rJOVK|I}m08&56B2e|pY^zLl(Jc(MGRq&gk}Bvp#JQsv!vkm@AK5FN@$^%JD}QH}es#=ReB zyElf4pQcX5kCKF=56!y0|9@rOS}|qx>2mAlHOadDRbWhqvB0313&wmz0E7L}$huJm zjL!k%A2sf?n8X6;fyk`eKN1Xf-9B4x-M)}i7b1Y9N-9KS=eP z8uxXL`!de<7;k#4Z+Po3o=M3MuD=P(#vjXmUz7Y!?KoH#|67BXa=y?(+@Rklg+{@V zCu{U|Qfc%h`uJQxt}^-&-=UP`$>&k2O6A|9q4A$rR<~%f|n7Y>bs}eEws!cGR56fcD+R|52 zy=s$BQi7vk>Wm=xBt!3GA_jj$}PUt7ATHb`LE zlPAOwR%>SP;Z5#}8)Wmj8Dr7<37_?Z&n?gjABws7M2G-Bcc2kIl)U%qhPAFX zMs&Y7eZV&lqA5kxU=Z~&h?c>!xKV09^~pvQVhExQ&33BI!1WO0_Q}TeFvg;d5?oD! z>k()L7sXt--a!Q5`U4ulMH#qu2Cf}z-RN4keXSc66Z@05e%Ckep(!P{BdX%-0-k}p z7-D~hWpP|>=}X>S5@JzslrwO&$1cdWH^@e1AbX#IcgaTf0mh_cb;8O2=4 z{)GrY_9+@cMj6O<2eQevZep!#iFtkLO~3NZ*Jw(4P4=bANjTN;`Zp|#d!~3zO?cUp zFvJjC6AiAG3|!wZ?$m5t-(oDebu(&R zYpvTiCbqV>UdK1VPLJM3J;YXU5b=cIU@oA9zbEW{98ryE?SW#F2~ zxaVf$nuM|FoCMd|f@?Cgf{S7xTc~JT$F+9O5nP@)?Hfbep%}-iiyqi*0X#w z8%-&(%Tbl?uxkvl17KOay0-MYj%yNPQE-$UcB#iM$bM;%U6g_BKnA`h8`(h^i>^+P zT_wooLMzB9=0bKjA^=$%8bL-G$acotpId6(O||ZZnAZ{B^hni| z2q1VV8X-s-1b+vD&(*qTYTZ+{?#US6_1^jh-`t3%6yI~ca=ECzWboYt%i@bEd@m*V z?3N2LWXnBch&^TcPiD}&nRC39P45LM!wr=A!oqB7k0mM(9xny*EJb z^;-98%w?86CfW5kUv5zKq%${@*yGs$UA5R2xS2I z2Y`H5>pqQ{{KeaSV2 zw@#f~tIn-a=T@uJ5A|kZwAic8e}K6;Kfqk4F8O3`tvY`_;cuMQKtKG($$#IBXYpvY zM2Y*9EnD%uz1FYeD(#Qiq&kYZsyi4F5NNIxg$`v@w;`<#j3Nu6JD8Vho{dU)oTX zR-2S&SFRdr{ozXQq#wRWsF%zSK`_ajVy?`OM+78%q$G?EWn|ur%r~xced=6Ooh!u2 zpMcTQb=f#cKI&uEr72m0WL*l0GGkq6SMv8reWk{eF{ji>F;|TjAOcD|LrO!3GHM)z z8VA(5{&lWjT;PQmLh)vG1|$XA)#>j`;pU6_CH=5EgC+Be5KJK@vuX zGBV#5nQvX^wybl*>f9D}Zu2<*J7G||KwBsIM_VFMJ`wZ88J4U?v_+kKq|H-j^F*Do zMDjx-|6{)qQsOf8=>Zo4`+GA{8+7?hT{ zlPPhGDRGCSmT0@A#F2?Qqr~NQ;W#PuY0N5xQp{E8tB8R5ekb*zLm7omM4>HpZhW2F zB`)zbZ~D4#{)ndZiJ=7rpTPG%Co~kN)Ft0(yaCJNM_08YVlmgl-EHQ6N&}smE2Fv1pDL}0WAbW;~7{X_22A{t(R%o3d_cL0UhYm=%M6;8AyoWk5*n(_E6&Q==CyeF^qe^In5yf1L)WM}e zQ3j(!!Dw-vYmWh~fEt0rM}*JQ{VJM zQ%dOsRHfVKR70shEQ_bq;i+mFt`cP(Tk@68sR^YhILbC!nxKh}^A~FQdiB^uA8)Av z418)fvVj0IB;LsQD@HeZtLu)7Se`LHbBnc{U;G(#yxOU?WqL0U|1<>&3I)aNba1E~??S|I7 zA@y#vdN-(E-%aucG{u^FzfDH)LNv5Kc{e$v-tRBIDBcYHNBIJISwl1keZ7~(kKQ19 z%X;Q=A|{cdDCR1Pw~#@gQ>7MkD5I!RC~8E#+os-a6<2f)hET1qXnR&PBB{tOdCQt&(Jsf> zB>8A3WU22_#`x@IId<^bpS<+ApSWN5u2K~5b|Xbm%vDslam3=xoUBnhKK8JX{g%=f8x zd)2$C^=^+i`NuI@9B7wgpCtKcFJ!69G1X@;%dv;g{->9tRf>87lgM&V%vIEjh=5w2 zl3LKAjG_)eQM2pa%z8IHuIMEUp;~ix%uXt@%Q4dzB+D_~7i5-Wj%5Baf=T8Sb7ju| znG6ZPDhZ=Q8JV{s^9A*8UcEag&iqdpDm||kB$-F^kRsNChv=Xr_2vKAc=;PdFOpi` zMR=)&Vy;>~MFf=afs}v_Wz=#gYFS+G+T%k027PHEi<3g^611;c9fwIBpCP)`K`~by z-y#Ci|6I~XhcfEuKpn@_yQAve5pgO1!BFYReN0kHbd*_>BUY`Jx2P3@M|Q6H&|Y^=?UANO$N<3pqY1#IDJbRjcD9siOy?OC1z*)zKRfP{*2* zK01_9#~G;O^m=z%y*ni?g*UY+J;P5=N{LQ0YjVn})pDlPQjPFZ3&mWu^g#rau%VQI z4rSDG9%?zK-klW}QiQ&=kaLnk?3$dlYIU41b!?32QU}Fcbqq!Xq`#@8j}B$jaT)5k zq~2Xz?=Fl>+02`6?i=3Xru22`C4N=pXMk7MCm&jE0n6eQ^`%#fD-#M)aFom5#R-P! zLiE!&dKt=KSJs2v@*i3a!&r1hef*)-<-%wpWZW2D@pcOt8bMe^+5x{2(8sS43d>#a!`|I6(_3oY+5$}-$Q*%q4QbhNoBz-UV zutCJT<`f^QFTJ`woFIyVqwJykJZE8aPX;5ovChNUjCiA*=%IwsGGR0eT46*n7o%`9 zoP!WZ7=@eR{1%LUQ|}&+0ky*bfL3@XoZtA`WDh-K038Cq;?pTW&m@5C9ttsp&*K?< z>8j|a}65dLm7Pj20nkScOS=m ze(LTwe?>jIf&O9m$lY)Lp1Mx|BjFPTN7+Chd&mUz|ZgiaF3jaye)5mQ@Wl0Wwz5d1{d#=Q~Y-d*Eb0+ zyPZOem8T^)*7+uz7H^9a{X3!cwb0@Xab$l{%th;WhyYr@MI-x*GH8`IjCMcNyYFLQ zFL=9frySl3rxe%^W`9-k!>I5-X}k=}VnsvglU!v(@<~>3l>PPns_rk|g{N5A0P4%X za^ih=qKbz2l~bn%7Rnpu2r-Jeh`omh2=pczAx0U*dVpBB2L1Hz&)(>L-+X|k6j!$f zZVP-FiZf|7gX=?B7JH>|t(M@j`zyp)`Tg}5245|k)<+nNdL^`a3ayW!6lgcfDcS|7C5ZE$PHz`pi&|Mtx{Xi9;t3t)QvsxrX7g=MjKL+KM>RRSyujjx*#5NFO|AkhFQOrfG3;ysO#LDE)?$MzPV)Yor=Z_K9E3u93sq17O?_i#hS%VuCV{67}abSb}P(7(V8WQ%He5f7(%7^Oc>xb$;`pc{> zrKokk+4~RGefIJx?()mA+)rV4mD0vyDp?eYxk{Ug2&jnnjFO#38Kq4|X%ibaMFfyT{;O8Ye5vImgqK<<=BnjfL_jU4O9|*uMlJ2ArLDm& zhzmIn`qDz$l0xj7ELgQV4wgF3M|7!!Vy-%_K?J0KiKLGXWz=yL>Nujo9oFCuiA%ZG zn_lOe>(P`x{~qC2MLst?);#~-0L$Vr4W&Et*n~n99OV={EWr>Rf`0mQ!y6gw*zD(9 z-fSy6CV9R+S{U67tuUgPi_txZ05tI}xG00sNnmtBgIgK{y4Ty?=NsONs}#@)zBYLQ ze5wJ&n`;&EH`gUkX{RQD>^2E8kT4x(A_FyF^m zbXCIVO5yVXw8DpCEv=(lAP`!~j-UnRtD6=L5&E5s<~BG#$1 z5c@9z2{Fnbb~lLK8RM$(MwPzljHVRVon|}TXK;0aW%1q=uKN;Pb~}X_D^IH{gWs1; zs~g6mdlOps2(9kW3N4DcXswF~*k7xm5n7Z%>rv2pxWO%pfvxB5*7wZ@Xi9-SZ1&d^ z1{iO&R(w2l{ymWZi-M!gcHh&?96YM>Qj6mt>V7!g3MfJTT> z2C-*A?5P;nCf=yoH+|8R;(E&LujdV}O<`GlE`{s)1ee`kA;!w@FW%&>_{U_)d7s zG=@J8TeFaSNVs~zU&;7ZuowFJbGIG^{^XW_;1P9$`YBTV=gQt7`e4i&ty@UnAlhq^ z8-A@*U@?nfEPIGzE-Jk96apQAMyOB*l{!$VDY&YF+o0gqi;?h-R3PTxLXIVmnuLel z5mg=snM50S9Apx$=XnrH`1_s>rH~U4SPG$-tB}hO0fn50Mhc;fLN-Am#e&Izno`Wg<6}es z2Hx*V_9kWUm;xS?3T{Hd?N)HR#xOp?C|H@x&ZLBdUDgR6gj{xZGnbuRJqfcpcb7u` zioj9`#ax9{;Lmwc2ygBrg-}KzGf+rt!R=dcdl%fag4;8$r4k0kS%qTPP>wvSv?k?5 z`yy9e*u8x{var*Vh27Javr-G&4f92_mRne_Nfvgd@aPU>;XyGMj|~t3JXS{|JSc<5 zeDIiCa0eFL0R=ZZhQV7oft6XXB$KSl+6SRI+Q`@RM0uO z;7%;K;|p#{!F9xFL*xy|b}$>zOMU>pu(S!9a2U>uJKSmdM82n@=A zaRXpnS8&(FBu;=Hi2T}4;-0-O!C?37HObnBSG6}vswX0Vq)IVYs^K<7r)sK{k?I{t z^|pe$wcu`!v*oRdig%`-SZ+%aj&3#UcJu$0b-MslMt3f^ZeEkD+ph)2g)kNv6m!A2 z8WFH=m!Oe#qYM}kVBA}9cgG~IfgXs=y4{;#ulan5(ap!ihkta~C!J9^Bl-XqECMGyJw2j6Ty2=$8J zY?i*>yASh4Pc64}UXv`{Z-qw$W8pzD7Z2Vn2pAqhBTGjaJYE8i7YgqAf_t{$o{nKW zg;B6FFAH8sNZ18@K3Tx%S#u$M+LJI(5HCw1Pb07tLNQk%ysZ!l`JLpC4rLVb1`2t- z;9f1bSK=yO^QN!+=8tGfKY4i_N%A_%o4LMSNPe93CM=6@74SyQ1K6Ecp0^VKQE;Sp z^r|87im6&Z_k5ed-Yx*z^1nrT2V>D&h4{BfZwjM7K`V?X=3>M<0RhbiXk@V|gVBdz z^nSs;7X#wGfnfKUZ~l&^6wv#=Hu)s|V*}`)uq=L*0`zeL$nKC3Ltak2m%--?#`-v$ z&%ZDheU$L|i}3jpTH!-67oYB3rS38`!iO^W`~W`R7uvQCDr-01o=x~7=d1aCUgHX-1cJ1oQy zTzw3#rVLzD7`IMr8{gZL+l_}7Po9H{YY=Cgjf_DWruCg``TOyx_5oeZzwD2zrKMk6v9{hYye%4T#r#-be)Mq`B0 zFQ64h6mv29B_g2kbI=GQ%3w4Rj9MDq_(r!&%;*wtdZ}+NLsQDA#W0#;7+ns_;^anr z#bFptF^qzvFdA~!&FD&uMUxXolZ4S#&dp161=)cH z*#Q~I9%A73Y-A5(ELxNxYZGLTKr6^7=0f&7BA|MILo{?K1KH6)c4VVFywM#R^ZK1P zeZe;`qABHdq%T!Yy$-|cC0G`ZP4VhTc-f14h#|NRH@FVX!1XfYc4XuFJ;tJA6I{m# zu2-NHToiNRdLI!$iFZqr9Yz_r&H%2{8{KJ*?vzG%QlmQ|hW3GX_|P|hK~oCtbQGqW z>}&(=BUl#CYApQ#?d$|v6dYxfo#x34wNnhWlT81F41ynXlC!f3euA;+tc2j1LXh`F z6M__T5&Q-bK#(^t6M~dM@G=m*q|sg6=q_w@=g0WI_16FK&39-@@m=C8mpyl-!S`QS z7OzO*yE4IN_gsh}^e#5UE;Rk~Gw6NKIj+p6#~Y(XS0wZ<7kWQHEA%MlqPK$kj@<-$ zH#EBIVs1Zm-?1A|k8ZnL4L7;(*e#8vpY7e6aEpSYY`g0`e1ePbYa}-tyEPk%+-&TY z1j@|Wr6^-d-3cgn#6&joMtyu!L{qwx?l3#)9z$efSQhV2 z5xFNJVs}!AQ37NW`rnfcgm*=Y?oNQ*B|vyLG}$E-a{<{L5deg@M-w2F0pwu-S=Q(t zh?xxWcD&^n%!i^WWwOldlE(~_VX!Pd+F1HY;$sPuC^*V4c_3q#3}=AHvY~8=vFOnR z$|C}0D`*7@#avK$lQLAvd#4E$%7F3|pgb898RLz3dotMWgr=0plV+DZYl!R&%i=SQ z_{7z}blRIQFP}9;f@8_n7)z&Tvnh4%38r@qljyV`DzS-z&+K)B;+0^uI*dF|%{ha`YUw7aW*B|6JK5r$;jGLg! z$FBZ9uOCWvyxW*mM=@7*ham#0;~l}II?AZ-GgS9!qx+=MeH52=IEGNRFKq@(`!p%d zp46ZCBIN1eqog0c&iK1zeguL^<`i>fei9-e^J64obSNY9Z;<)djqb}v_eG=oXPo@W z7%g3wuao4XFOelL?p&8Ik|jvi<)4W%V_lZ}i=1zz#?vsT)JQQ`jh7$-N;_9dLx(bI zEN{Z!t~R>w8{KztftO+k#hcanAt}(V&iBcRMBgR-usWTZIN@aoCYe*rmHFL>fIzoO z!st*&<~@*kwSRw=CjIzX_Phs>Rw8DsDE=Ipa1fY2Y zjhuUw!Du}&TBpga6$5(8+db`@XV8=aTF2KTFX?(4K+nRmxIqd~?*x$D6(NT3Su2Cj zbBxtHo6qwYi#AC3tS@|i2d(g-n2XOFhyXq>qY*xo!KVp)3QexQ$<@V(-t?w#`Q~jj zrHBeBNngDc4Wf5oS?tqPdg2rlL{V^*Jyf4?iRzMmyodh8V8v`k?_wd{^9NZ>6_2dlmhDK>ybS)&;a@uEQW*+qimeM8Bo4rfPvXizQ$NIAc68Tf%0!?1q#JnP`Y;)C}n5_3S~gq8c?=u za>JV37ENyR7)=jv-P1R{(3GOt5>@Hm8DY?@4$I=UO{LE&BMcgKrojX{W`6NuZd zJj7JrEn6 zmcH2vO)1AcP^|98y$#20U|HNN#c}V1W2BDUjZ+e0(WC_AghZXO8_la6{XS|GC*3<6 z=XMy2_DXP06P(*aD>y0U!nqqF0OyWq1Se(S+#fh+HMtp0t~F-a;!P*`W+IwWma{^= z+>-|ymXl#woReaCV8YVwNsYlhIU_;Yx~eGme8bYE{4RWHud;^fYS}T-BhBy{_Suny#RGaTThg_ntm7o=$I3uF&!oy`cu%SrU%pv%KV~>3%uqk<>E^QNK1nv@ z+&J{9=CWp}$Cq!;jEBhD-&$5yHiAh}!VNh`9vr-Qt)&is*bSY}91(Eh2Nig~b8;mw`88>V@^IeO7-*Ld^1F4MgIe>4reIZX?ud80Y{oj(UWjd=6C zA@jVmf_Z*w^Z0V$&3Puu7O5{!pGV0S@pH=-@kRSB;yK6X)FiV-WL+l97GZZ)x5y8; zm~~u>O^fDAG+cI(fn;=Fd?nh~jq0m!H?M<1G^#I7?FPvJccWU;R8}0>cNyD`)A<5- z`@ZN)0p5^FH;mhER9V?b8Vw)Qmor?CNRl(fTsi;C=ll=NnKE)-gq#=lb@St#zl6Rx z4;kV=z%1)H3n@zKNb47cXklO85MEM@=A(ZV`=9q3H&U#Jw@a>HA%f&eaaD6Yh>kj=!yY2e9k^PkK!O%w|`^7)w4SYxR^L)=G-|hM-UvG$n@kf~n-_iXz z)nY`FoGGqq&WBDLU%t=y^1YesKFIUTX`|gQrn#R_3wiDv{d^iP??ca>28;b@)*4jE z{i|MO(J!W*IBM}AJn#fCz4-HK$tXS|7<}?^>#W&n5F=oC1}-TQXJ#-0dpz$AKZ~(v zNe%4gso{X}<@+SsNp;LAIA-8@-!T!8(AB|2X=EIO2t;U&oMV$HDQLT_{tn&@Ir`%2E;ak0An5}o43)50jg zE7}T0+i?j^E;A-rn*qtnbX>~lmvOClPISEeb{Sr%TqV<7rqf)`7&kQe*A;hh2l{k) z(#R8h#}%-^CENSSiCxj`bG?BhohFqxU;5LmI&Oz?+3I_(T`{Fs*&5?J4VgN=yw5~} z>3Vf}*=W}p$FTp35e2RuvTo?n5BcLs3Wwp{pa-OlWl}Hv#1dsq+gGOTCDZmurrk86 zfN9NytN980$%J0WG2sB2a2=U&Egan%ID}#cM$~XyhL$_>2Ub2Jq8aM0=+U!YE^7YB zZnNh&9^v!7-$>M?`@;E7f{D zJ*$6Y**5Ws?J0?QAxC2SN@ANzV$Dfn`{4;?eEFP+Dx^1TFehVD4gMO`k8-nU@sv_@ z5M}#^r^C5m-#_Tq6y5NF;_)*c4BMI0#)$LC1T9DdtBU zrNd_Gu%O6vRUhmYPU<{-b6PaVc5RZc2CQNZf9`L%s9hYf zL|B^g$Cn=>?1jZoJxgX?f{zmRLlJni8-iol6h{}i9Lq3SSw~OqQI0`c-Jc}X4<7~< z5FH~4cp=B)cN~vrBS~T_#2f8~;~0|YH~~X=Cgw9E7eih*7q^9hJXQJZR%3Q_!s#NX zOkmz|4ZI>6BiW%N(fSyCXi&s{%}$IUC6 zkO7dJOeovBlTOR`ws@kKX;C&m58wvqxDB0%xx>wGf~_Ht44>0w9lRpXI^2U0vJN{S zCSEV&sOxYqhKgJsQ!2-Se06`Bk_|B$DkgKECgT-(l6gpz*$FX6yD>OwGLK;hlRU$m z#z8NasfZRxV)ahilV`*}UHaiQu)GkitlXrmY`}G+ZY+3mJHvr-p3`K#B2Tg}YqH}J zbF|w9M@{zk%#t;jQ;FkD)tpMZLB(WV(PX?LPcm<4G7}LKzaqs^lX(Y2nB-&TGzEHj z!ii|Xh3up~dA8oJ3*SAYp-qA^p7?3j#yJuCF={cr3+H+YE6 zVEpSD8BHheEBg4%{~o?-q%GYmdvua0Yv7;k?2dB$tE8@X55J-J!DPho14789z$^0L zs6ZsS6ii3V(QZE+6-QSL6=y;bQHvGPmZ_BY;Fb~`0SQDruXS{bz32+1*s*l}>lvvQ zF@S|J{0PSMJ!41rbPVf7K6E1={_7duX?FC0S8PZNa^pW?H#D%Dfvm``7aC#b6?xdL zg%HB-0K~+9FomPCTN^{fRG)t8p%M0pTo5Y!YR(B6t)m%vMV^c{(2V9vMhBXVdWVd* zO<&z<1X^-&4;jr18C7XUUXdrG4K<^MlF@vV5kIpdqlPpi8ijMIyuy-d3wbqYUS5$W zuZ=XXgC(y;Ca*pruMufdGy*B^KIDbtxWH?1$g8M%c}1SQ`f6TBNM48G=nla_H`b;Y zZ$66iMI1vCLyx8;FPi$HQ#=Nuj_Il4I6(V|vEZZzUDTpKEjSp_9~L_BGYm|s7%o#b z%Tzdd20*Ey{6~;S!i%TXK$`R839rb5U~`0!)9N_H9PN(9QL7)~CmH6O;b@8{Vwlfg zWgDNo^y*#_txfh@rcEC0HQ?kEMvlazZ1@t`GUu((NX}l7C+86eAvvFdn4{fEIBL!# z{UqD_W(PFIUtrkhd?G&Di)fAgu1_kX(4|QJwW=GMi zy%yPI<4zKGV<&0ILP(I!CJjk|MG^=S+}+)MNgxDw|8RGg0|a;baCditJN)lk(>>dB z=Jd=t6Yjl#@;sSS)m>e0RdsbwPme5q#O9zNi_NP+h1h&Dbhb2}h@-W6^#Eke;AbuT zX4E%`AK|vOqH-rkY`E2NHX*?50 zYx70{$fm*1X86gSk7^s|`|I+QMi9s1KW*N;P~<1X*{-(Ffh=v_0zYDNP>{vuZJu8DK z76PXJ<~xl^r&^POf-EMTX-%3dCf$u=V;%=<*IBfS1!jfPkf#Wk>e|s*%mgc%undb% zlr`TA5r*t+YhO^1#lG{beGfxtOXGt$Hr|heweNh|#{%>ohwG#~MFRWe0y$FFX)?>2 zAAtz%yTIBP6lAgQszB3~_>naUd2G);0fd&u$8fZUUL6QtgP+{fDCdmVFqT*CoLjDC z@iQpSvyP?q^msjL@>B#z=wQXrrsu&0Xg7e6!eD9rBrBlpM*QHOn8<;>NyKwcq1I84 z=h~W|V*~Z99EBDknfAH^tLeY25x;H*5iz5_=>=9ci--~$P`98+{1}HWs9YKcdUq>J z>4RwQ3(YLO4W-x%4A4c5Yz5tc;ygov#!_uBC7{Xyo+D9Noc#H@Wu# z(bD)Xj;4!7<;l#R{PM^!vn%RzAEIpZOx_vGeH4;v$@I>^wm@7G;#Xgc% zS_~ptt;GV8HCiA^w$p+!4G$eDqj4z-cHnDx`&>?2E4pC~f=tUTpQ%21s31gr>Ll`lJS7l^y zZz|UrHn%j^;%LG+El+0l$+5y!QZ zQ4`#~3XIJV$MvUI;s)0A%JmV)L9hp3_Q0{RKMp3C8|KL%^YX00Zzo$oiyCZcHM#oE zwRJ&44Tdb#ZX~@NFd3}de0nABV#zZaxuMY5(%67w$c33p>?dmZ>=o|tTUy? zx=zNrVUUH|t;D*3$za{yxSvGp_D1YRK_fm9jAP?)9E^4QM>7zZiFj;YB7kpgwfm|;K?W1-{jA`Q7tZaxzXfxa5_872nbSHO z6?qmIlVnr3bC9r08+(qj_5=l4>^Tl9V8*dx1_<)7XS~?6jAPI7sK~Rx*waz=uB&PS zi<*r^CqPO%DJaNd(dkeDLrxPzK#+$;S}dC2Sj2~VP%n?|uv`qoNv8rQ9rG|m)AF>7 zDQr$E%aT`8il*|+&T=R!ygy^q$sVI!UtS2f+$0F+*}_EO@6NXR5>|6o3hr2}(hK3D zGz6(8@2Zq@qig005Tq}>VHwN?rm2|=f*=RRTUkEvW3^J@a-Ex2q#9;;tK6QP4A$eB zSa3fB74h+EIxz*!@@yOPQSM_F_(=xh>un_xb3OLFEqV5Z0ZdU zq;7$f+&ki2{kGbyZl;dltyyS#3O~{jf-FvTg$iiuf*)~;Je=AIR<$(lfTMM)J1TN42s#ZO ziRX@;tZeHv!-bvJ1MTysFs;*eh9+9o6F=f#P>{tx-bsh1zW5RU$iu(gfY8#o3y#)5 z-dE4F04@}!qbZgiFjqLc8xzA@>p?*l6M458CXTQsl81?ViHUnSCXNgQ6@Kz857Wz8 zK<{tt;{9hUG+EB_d$UH_dbyLlFN&-X`y{w#33|sZ@7T$5+#j?nXx>rI?MD^VBgR-2 zR%8i^>_ZXCLB#$NqkC01%7}ZzPAc#&H?!l~hwjn@Du5wc5?P zCh*v5X>zp~42u;sud8o5&_MFeGz(iRs)22ckEpehyfaNnvp^F}*c{%A4hpj5#q!V$ zO;hkAsY@PtaR^MrH{o!!sk;Iya)+Uy@Bs`8A(E1}HqzMHWSNPeOPB(Pp+dp zS=GU=Ujsuez_cP>z&YL}m$^iwGo9dg-y52Ek6b#0JUZkEc-GQ56Gz)2>jZ-9;U{+# z%4IAEA3Au8*O`=U>zClB!TJ!+QyBh9Cp0w80Y|_MoT^|fAITbJ>o*3In~fsLjTD?s zsEopGI7b^C-g389E{?6|jdn53sf2mqt#z>~Q)IV>W@y?9KN4B;i0pANtflc79BpK` z2?V#pPoCvr<~dW~i72PG?eRl%%~rzkELOIXH|ujJpr~+(WVA-c4DZfUQ$wCDfEl?2 z7RA8Z1yYh>K|z)w&wKdL6ut}>+|$pU0@RkqlW??g*n{SuhJrjxVUZo)a=V?U4kryL zXVXpkuc7I56cLHH--8&*OBAQFSlP<`EJ(q)mws_h{I34CxgcCwo9b{Sus_u1O`%}d zH=SY3IiQ$1w(?+_!@-v9+L_cvy_La*Uf`3I!r{ZHgy4mNYh^|8z?o%gh1q;DAw0|2 ze7MypV*gb9Q_&B>p4xmi>y?$7nWCQUg1sH1{v4xzRzy9d{t@*`>Xm@Nts^Ow9-DKi zG!`2vg_1d@vcd@*ijPLIoWBSA1{EW;3)(U^mERf!E zMm@`H{Q5KFp#?=1c~cRXdE^ujS!t z9>}G4+WYY#E(RQJfd(r5Ly~<#nHO`Fe>saFvhh0 z)2*Vy?9<$VV%qZve#D-jAd5YZ2bvzkkJv*V_S^-8mc~1AwDvrKiaZO9J$14PSs7dx zGg`r382hK9`EFz2lV~Ic1_fCRdeFHu2=XxSUNP_<$G~S%k!OK1u!|U2aBJy4 zW7vNoEQSRISqystDqzp^Vh;%NFzg{Q>;cEH7g3RCflVuO4f?RL{S3cz6T{+n=97B=-yo@+>W5SbdI$c{X&16E5C}FtcZajIg>q zL5;t)b{IX4GMf1Xe#GIRAdACa2b#XZkEAVmIQ%>i@b`Xjv~GTbiaZO9F~K!5&X9O0 z^m_71bNu=ve@&YW6uw$$g{xM6WrJH45L?!fj^>=7#I{} zG4L0tfL%X}T_DKAz}LmVR~-X?MMa(kw)af7zF}{uz&Q)SdC;Uj~k%ujB zi!E4gqe062hM$gBAPTDO~kpNAd7Q3sDP#s_>sOR59huGLQCV}#1?*8`1_<)7=LfOpJI9_yQITgsDFgRMW8i2s5(9&REC#L& z6|ie1u?qxw82FnQ_zRAWKjC1bwhC(VEU;GA<|zZtEMgeR6x^uVg?BEu&0CA(+N+Y}nYZv}}z9rJ7p(`st1aoZLe7krHX{%jW**H?@a6I{@a_AXDq(6}8+ zF>c3ljN7TuxCR@!ode_gi*aItYg|_`4x8KqLgRL|#<2q`UExZ+#fgycGHAC#D$16-hi1%lM>gGY>N1L|?O0f!xgYX1>8>F9%5a>OK zdO12_VDM^3M`QcJRKN$zgMutm&=F7pj9K`R0Zkq~FboLzL<){}_L&_B9v%D~i=UiA zb)GVCldcA6k4P}sK#7&S)t=8v}l14-WE1GPGj{bRNEKCg4razOLcm@ zK2N*QT)tIAyXtGr*F0L!C?ZV*McQ2X*93#SK@yM$xo{=1aH!|ZGW7&I5cW>ifKbm_ zCFrRZd-{cK&Mwl1@pFCX6-u8|DDA$bI2_H``{zPP@+c@MGmjdf1z*d=bMDL_d^I!I z?h0m4HI62Gmd=xzJ^5YpRCPyi6kbNvf|AjOr^!)W(cGQ|c*b3IvNe3{)2SJ+I@=mN zXztcDt2$eQr`g?_395^&X&0@TsJhx3JUi*O(W;xR=@6}1R&}>E?V~lzsUEhbHd-@D z^|Un|qcxLNFI$5Zk88mc)!WwKBFn8=UiGmxU7|HBsJ^y__cNWit*H9hny%5B7R*f@ zSclJ@=GZk8k?f&xg>LI39d=5UZtDddhP_6&#aV}eZLixRsl(89)NQfSVQ@O>wrJ?k z{W{&|uNDXK9D9p0Mz18f8zfGq++9_^5h||*fbR-4NX?K~&FX5X)C`N&OjpCDW<;!J4V9Cck+GUJ)hMY^v6{8i zB2u$xtY&RBT51|&H8a#=QnPrhW*s#~YLDFEWB(?S;6Zj}O7P8{mm!uzC|VjdjwZpk$dkc2e8Lp`GPSo<%Y&-Ot$?Em z>LeE6wFkAL)U?EEwpJ@i&C0QwZPY4K<8+bHwk^77GVAaa%^ble!U_>)AS$(3L9$8< zEXf)zI0(vv#azS2aUwoFJGsyCDdx2hDfN5rRPw;lOjjB3Z3PIXvG@nFhOy z=YgV3p6`WEoY5t`jFQ^`*!b)Zj*aW!VBFt3PloPqj9<#`qc#Cmk=qnU6qq zGpX4;R>z0JSaK=C;EzT63V8DFqbhqHZdCXNM`@huw+hmBZ|m!on_ISvO&IF5lzEp3C5A!Y<4 zL+mA4qs1|j?X*OIWP2^aB-uer)Jb;K(lsP&we%m!PFm7{WM?h8Lb6UvLXqsECF@9b z)snmBz{-bfp_uQ=a4-sw!FvWG)zWwxj%M7p z@-w!17I5sIjb9PJfbl;E9NS(<=3FvvXPjwjFJkR~q?TQ3y2{pG%-Zv$_WXG5C9J(b zYA=k}^1T{$k<>crX*FNQ+KZ)@NnU`!OOlmKW*YX`5b%oSA1J&a4 zB^`C8)N-g7;PPD@b(Pd!9k1o9IO-ayy*6IUcWl&kQtM1r7ME|;sOzPclU)Js^{l-? zYHy6!^8178CaHBMU90&<)M7ZD#d>r%Ga|=K;E<9WV769h$pDg-TDqHLm6pCGS*@ib zN!DoTHInVLbP>t+TKa=z2Q9%T*-=ZRN!Dr!E6Gk;Vo0*HmVlA0(-Iw$U9^OPWLGVI zlkBF&Ne(GGrL0Rg(L?Tl1TJSAQvA*$6yJs)86&}W7jw5FQZ0=)<7kHzUqH&UfJ5pI z{E9f=MpAczt5A74-X+Jod4yWNlcesEqPcRsSC03Y>bp@*56$CDx0&L5*y?`6@O>uA zm?w9v3_r<;?!Dbe(YhS1V)sf@wwa>EG?L3}v5({mT8t#Qq83X@wrH`FPxBpDqi~~YrmG-Z{oFl$3%TAwe#Y&eDOqmC$-sHGoB)@lhl$xd1#OtQ0M|S1nN?*-c9b zNOsraF9#j{Q`Wnm=`82IAiK*Pbh`ZfCnQn`5^-VWGkbQXsnzNX5AfC;*j>XDWa@|;hZl@_UhRZS0 zRqkVU62D`C3r)x1M`B1GF}xMV;mmWpQG|c^DBipg zV;D3RZ$5JNtnWsQnLYV3d~Y8f)9vbpraRD*Xvd>L^KE35EjkfJrD)!H40>OJ5@yaAW)8zvhp-*3Bv@l-PyTT@la4Q?&j+UDAnk`w|Fgz-hw;aV z@wl}y`B(Y468}2J0%3gbBF3M!pcvmD#{U@nVJ}2pzVLMRf@1ri&~|2x*v<>X-0c{| zGLz$P8Z=b29@o1tkruZ@*p4aA+__CQ2p$x8n4g)m6BYj2$pgdWSUarHvDie*QhQ>SX1KzWHAjah~XF9LLl z04V`Nh%Y6}6@Z)#GM&MA!3<5js+LKgJkDVE!WH~!KO7tH!oi-wcmbVfLFs3(ru!it z=;j4>v~^kWD42{RW|XC3d82W#Pj!1Qr~&PqY#y${RAY`tKc}`pCt2|VV(xle79kq zA@hh~o~799hItN5?!l|E@|VA~nS<3)L+EQexdw28e%(;9?|C-9HKlRzc4)lu3$9Hs z(xx|zO)r;XQ+tn1uasg_ji>Reu1&AerZopIp_`|BWe2hcAR~FR!l-?`Ft11uF2WT9Qgb&Hs zk?;{1^^WP`Pl%D0%sz}yUA3Q4?Yldq4%w;b{^Hf zZ`6KYidx_3`N38DBh`Lj)c#zGT3@RC;;Q|XYCkk;e=kL?FWLWa)&5Df9~rfOm!j4; z|NP^st>_Q69~-q*U~;df%$7cDtJyd*3nUHA8c2s(-i}6mVvOiOJr`s&qNA&}mTEsW zYCBWyFDV1m=UW}s+EY~*7o#gNJ~J5IiE$ZLB3Y)k9xg^t7o!(3J~tSBh@n!#<4e@O zuG)T7`-M?EfNIl5tM3G`kgIke)qZKz4yM|)lecfQE?kODzWJ`+wW)zNePwJKO0{WO z?u+0sHZD2Khf_LjYV~nq;~Xhh?1f>?}-6GrYt?2vHvTCooHMdOQFUvG_d!N$2@OA_oG z1GY55PRuytE#qP|xftV#@vXs_K#a3Ohl(%GeSS=IF|>=ZEHUO8j7h{un?pK!mR6J5 zIBj0@ohhfVab&P3Eo_&kbXo%WVzELDD(URGVkuC*DXgU|sFg~A@=akYmj$&-DNw$7 zWmPl|N8nU4b_7lXqrNlAv^p`;^1*kNG~HFZ2GxFV)UH*E+FDPJuI;LwLA5^^wdLH_Xj#FM?5bs< zNwS-k^&rXaTGntRduUmAk?g5uxkIv-meUW(-dau$B>QNY!%6nlGS!mor)8j!?5`!c zNe*w@vwANBlc z^c=t%do6LGD|QgY{xV{RfQh>QcLLm@lpeidaNV&fw#c}w=(G+FMJ9&B2x={8C1V43 zI2iShv0xT;rk&4x8vK7jK-nK zr+`s4#^lqeHezzS1d~svbYZe#2~afI&L}2~1y@nwGa(#i=2>KHW}Xd3wKwLTOPy&K zAim7}4;x2(P0GykTqDk>5gm*X7sm8-Oo-VnL5A>R4+PPxb35oi){Oh#8jD z$u~kejM`0LR2SpmEipY^6CAvi(uEE(*NaX+w^2H)gSW>FOLFiINQVyI2}X4@4&D{h z(>=k#yD44hAg+mvJ9rPJvpP68W>}Jg_d+^!@IElAhjH+Mn4X>q4n9cfLI*iai}v6{ zl+Nnl!!g5>9DD@Qp@WZtQN4_VkH_@%PH^xEN*6lFsimlcPf|LogHOc_OLFjONQVwS z14i{R4*oZ$r*DFT&r!P2L0owickp>iXLay}m|;l{z6j~i!I!|Oe#XI9VtV=~IQS~1 z3mwE3SaAnmqjXjWUym7<&~xxa=?P;JcL0>fn1Z z!;&0)AJU^bAUH@MB6BI>_}?(J}Z5rL#KtY0R)B2S0;!=-}sI)L`S_ zmoYsHCph>Or3)RzdaSsEUsF1(gWtpqOLFjANQVy21EcDVgWt#WG$c6q1Eoh6Ty9~* zr08nyM;G)bf(|jDzr;X?CV>7*>B6XX_eJ$LN@tDg?=i!YqWVWEP`>5(pJ*H|U;iRw zm#=?=QNv8ADh9xv$nte~LZ~V!T^On!zED+BI%}w^V}>P#s-_euU#QxlaTu!hWNfH9 zfKek%sA`E32~{p3RGlbY7^Pd`9s757(su!gTL)FU{s@{~&8mc}q!;(VPw-hK}sQRIC7^?ncY^Vl+QObmBATc7L zS|lMB&Flq@C9UU`bY(jLFrF3C*`un1@9Hp~HXHv|tr07g81b zjEMOy3FaS2=|c0lWnRqugD9NU{DaXrH2)AX*8D@ksFjTQt;C3!zjA{4hf})H{KY)x z&!lix^Jk%PX#NpotocWRQL7m9k0M6I{8baopF`)xr^3^KM?&IF@YGre*)F(SRPdP1+9L+Qd^VNw;{zde`IS$pL_F~gF2$JLEs)Y_(3ZYD-# zT+K-6m0KuX*ee5ly>ct1v-ZkuF~gF2<@Qpbe7$lC8!o-V$86lUU{h$C||F`|Myju#CuUFnf<1jk!gHfB9 z=zJJ6V$+1^d_?KO=x{@#=&JH#N@tDECo#j4qVs7fP`>DVRu`|Md|wKbuUCF33+hKoXYG}r z&^YXspUK!>`2~#H!t}~-#EA6DmI=M`JEaSIWvH)L{-AW$UimX-SW>V2RSJ}^SN=xh zFgpK$QCpelR4!B)ovjn1Q$^{*=nV5kr<&4Pqf-+zEGateN`dl4r+rya9VneOXFH;C zn6tHHY|eH9qqZ@0SzyuUC4M1=W+% zS$m}y8i&2on~d$1K48>#rdRqABho9|C-h2xN*DIZ2w$%Zpmf$=Stw>$Qm+gw1kGlY6}GJ1x^^z59VXE>z`w_&-VRBRJ`1ckE(Ifuq! zl8hu{lVlVawTm%-5n@D=WY+}q7o~Km=8vXuR`VOtI5dATGS>XX!KmGg`AZNZV*c(4 z=8vUxq4~adPsSA!_Pu+uB!#p3x)d6RzAjD1`nn7lwTJO_JTcPV*!6t^pqY&$fl7LV zdjh4ix-&5bl{CCHq(gs~1*7&f{!XHvG=F_>K~Ihuk>u|bN@w+V`507^zblji<=bss z5skxOwSd7(yf#;M;KQeUos=)}%8R6YA+LpYI$XjWUZFh(MWdE@=_Sd&RSl$B3Y;9H7Sx^w7gJ6 zva6O?Z%B62@{$V4?pj{wAlXC9iw`7wYI#L~WG^ib)06D2<*{>;eY8BFO|q|+N0~|X z)AE2Z$^Kd%pd~p#%LAe$7t-=({c-)iCa+8>((sIL< zrBiX3sP7cY%wA}L`xww|Q10=_2*^(x?gqD3!l4G@O`jH%` zWv7Ycl3KPmNG_%2TAt+6S}q_-E~DkDg=CYKB|6FRTGoXmo3$)PNKVjl<|R2%%gK|Z z)^Z{uxvZ8+o#b*_<~)*0mOC_BGJB`3du8@S0S+k5RjJDQbNqdxooa9je{es9moVwZ8Sw`mWjysCGZ2 zb|b1y`}j|V=NknZvvK5Xk~HOQ;u^6jjo9B9u{rgmy}#-U*%oCPv1KVxzO%_zWkGFS z3Y70ey-itA+fq91#O3=|&vs}Wt~<6TWAl0kFzNu)Njnka@{~{8_!4kuSM4rTd!SLf z8`YMaL%X|r_Mo1FjGn!y=k65qe2Kg_)!Hur?BinWON@gJ#{R_U6y72{ogZ}0V-CO< zm-!9Q+lQ6@&7uRSs${nhr1S?VpDyyn{vb3CojaI}?cYPds6&i%hY{nY5F_PVOuo_B z>Vh5ag3Tn@p$6;-f~7g+!#I+SOOD-a*NCHN#9_vWqp2tEab@wZPx-7lCT302i{!`B z8k=dyk+Gd|JQ&q#OgoWE)23x#ho8j8CCBGvN~g^oKIcy<3+mKTpnPNWw6dU1r*zsW z#W&BNQ5Mvhr9k=S`LoJ`I-AmIedU|y&q3ob_0A<@Q|~`u)Zr%e&L_ro87I;U*tq1> zyU;b_A{sH%7;y>poEgrv<$Xu((z1-WjM8Z_^$oSl(Kw9h6=ZBouLPrJ8F#KG#t$hm z^ut(#tgIcw^G5)U)@$V$y46ne@7A z(i=4C1Y^=$)U({bV$$1Xne>ip(z`V2L}SwX)U$PHQhDR(gR+eHkkW64tLEZRzM1_a zG!7@ykHM&uj0c}m?Liqm_>7H9o*_S{bXE_(K;zJZFTtpjjR#*-?a>)M_=b&3_TXDe zXZ2tn8iyWy2S%M@JotfXcgpC&k8E7B2R~6ds|P=$ap=J>VAQF`gWsrjW=0QwXXBDR z_=D0}J@^xiLl6D}qfRp({6n=TW%Qt8U^yOCQaY;#RcIV~Pz^?%Zaip5wQ0*s-_=2T zS8WHXJ;SK2rP{Qmg72!W6C0P@wVf%Q78u`ETOAsQ3&$>G?831t7^Ft@eOQTvhzbIoz?lFWkC(2blN!fb?I<44kI^$jE!6l zj5^0eZWJ-nR=vJapxC(N$Sp$Yw8;4e^`dATx-*)Lb*B-GI@h?fI5E=P@r7&*8<*_P z5|mDJ$2SVb#-Nf$!8k~V&M!&EI=>Vc^&jK>GE|!8yl)gVv2n@HkEe82=bOudnn3BS zqhKN$hmq4{Y~+>&qs}vtn?#JXQ=2bsCbMzLk()y4tdUzj29=aHD?mDQenm3Y`4%wh zeB=DeRGQ|zFKt#~R?J|9WRHVaTv!#$=Em^21Z?G;&?bQvi`xenJ&gG7vl(GTy8LC6C>*%OgqZO znB!s`O^hoH#<9eh@4vZpoC|im3w8p*t~6jL5p0+6##hQi1-?OlvI};K3wA2Ot}7?-;kR}kYmgK-rxvX08DU5sm7jBAN;y}`Ji7*C}1x$nGn zgNt#ai*XYeJXC8Zf~nkwrO0k~LZ$ zb|cwN%Oh1J+iQ6Yiev{ZPco70sO5nplC@eM&mq}K%fmAyJ8OA_g=C$UM@C3?(Q*r) zWLGUW(n)sHaub?lcP;mdN%qik%a&wMEw^P!_R?~5lw@x$Hzi5-(Z?{@B>QT)K}WKm zmfK_``)j#9MRI_a+d?E4(sDb7_P4HTD^S`&_a6DR#3Fdk{?Otl(QAJ>;r= zm}+k^Y9FQAuTmxgpW4T$)|&pfi}3_8ZZ#NB5hJqxxeYbGM=YMEblTM9TWUSy8u2WR zxZN1>9MyiD;;3&i`#jZJM_+I;UL?jH2IFO7Je6{G@L{~-V!Y~Nyhe;W4aOV9NP9xd z*I{q6aik}b9s+sGHR5d=kvB%X8`EmxT!dgFnAY=Xf5sbRe*zhy8rY%Q&ONC!twZBsB{YLHY zRGUi)pHJ-{RBKKD)5Z9U7!MeXe~6LwQmSH*6Ol?V>OrHn8ceEMpXoKO+ICd?kWt%# zY9pQfFlu~*sw1Uu4db_w`D1OtQ@HUzLtpE{b|UN}2DUB+`)C4e7fPpPgD>m5mIc+V z6ewSqyQ6WK&pp7X$Be(dVn!tG7WAebn`wPqrG2UNaig?Qgp9RdC>Zs$v0ylLMl5(H z!GaN#F0{b+LCYLLtpy{=SPMphQO_C+7NO3F1^-R3U{OjJTHyO8ft@O@TtEJ3XWLOOt4@XN*7wNxF-*q z2x=`DPsUo%3`V_VESN~05er^Uus~C~(1I}@3zj9QwO~0i)`Cf3)GNkYfm zQp-gX$to=uMkK4XT+EQH(Q?f}vYnQdKgsr57U(29Xjw;-?5JfmOR`qWvXW#cE$cgy zowY2(NY-gt4Uz1kWd%dBtCocZ$!=N}2PC^|IiZv6q2(k?vZt2w56NCy&Ke|pYni@D z_R%trlI*KxLL=Ev%gjQuzm_3Ra)6exMsgu7Nl$X1mh2-rNK4Q0dY3U)Hp1(Haj$oW z+4nx5wb#4rQ~V9n?HiDJ(=Z!>NzF6gnSWz6ZhppG{%%6GZyB|lQEl(=y6mj*Z`seD zvQPZIFrWU-soxIEEnKiI3HG)D+nQkWQZCSZdAyB_v8{`-9WmZ97&{On>v-JJRl5__ zzH8L(LbWAN3cI>`cB7v6jGjHHC+lU)o>XhYyqAlyH!cjMx!iQg9XJ~T4Td|HW@p)odZUFZcO_RmBw!xm1){})Kao( z=hGT%+682+X%~V~Ul`LarqUBr#*eQvE@9)6ExMFOSc@(rV=cNIjQY}8bS0I>gXPIZ zU*ccof?e%`T|=<14A^x9OLO0calMOigNtz^F}^k!HxuLXFvKZ$@qA#nxL~)sV7C$M z8v}Mnaj-H|?M`YbxnuLR#&+yoWNgRY4Mu%yOq)xkXj~df_5vD*!G95q`oVbcGS!y% z*#e(GuTWLV{=7=*tmnzs&^YX#*U8w-dIOC5(Kz=OF(MWv?JU1d>C$(W-yy6`k$1^h z8{Pw>elj+EK&=rQl1{lFx=KHCm3~a6KO3c=Qt5LkdFPt}K6BN6PPM-nwO^K^7F&3@ zXo+vWe&wqDnreSFYQLr0v>j?+>dtf3en+*x8MQx9ZCVhp(NxshAK5t4Ex$vpZy)+6 zO2_x1gR^!#6hA{e%!XgUs6UL&zr|qxOo08})$<4S{AKj~MLlW0<4bf!eg8XVM3V3S zP`Y&AD+WV6ZJzQ?A(d<#>6N6r167ocTjskvP)+fyF{_DLmK3vg#VzyYOM8l^#mqNA zI>anXido0vmib~x9PPFz5_M{cX~>3)M#YIq7yxS4yXa$G1S}7K2I}aor&u zn%o17`p1~ui+a)`fzNan9dW&5MkHlVA4MR;%PDSjkv)v%aUTYaB<6gF{`I|)|fTKEK7>nkm8p4Vm6fG zX)*H+!(lPYl43TzxMjYWji7kenB`)YRov-c35+amnJ;FeD4w?T@m)VDHvT-kv@U*i z(ZMt2EP}@2@^n!$c6mA)jH-l>71%jnj2Q8KrNEy%u$Mh&)+zjc*(t-u;l8PF7FpZ{ z8{>j4L9i+VHjZFv{p8D_CD}M~&PeK~r6^tc9J(~c)B4HxSnV=s9EQ4yj1Bd8Fsj;k zKY8rgmK3vAcv`+O6gmu_BGDMU1 z2G=bG%9lUup>gQJ`e0Oh`IcszpmEqCo072|vKbiF z!ML*pG0J;S(C6HiR8_KbTTwczb6cZv=-f7BtaICfQ5}tQ+Y=-0?Q)+xJFs!d?(9hE ztnTcD#-Teqld_x`9vo{#k$+)vG zG15koFTM9;>kmF(PMl+Nm0 zD;kH+9ZtqNHxrDiGtM1BjI@#DbLU7lF4>*gl+NnTQD_{xGlz_I=V&mhi*e^zVx)~E zpF78~amnr+PwA}goPfrmJ13H{?wkZhbv5psLX3z--B9D(!abGJi*Fcw(lXxzj|j#0 zZBHYX-O@juj0HXejOuQH&!Vc0Q+D5dGt${E#yKv=xy0yUFwP@J$uCFxz|MEUE^xsv zBv?-ac5!jAU?mv42=ryhCDan>kEA;tm(m&=>&wX4SYHlC^)jYiNu_D;RQlY%%Eh?a z#khtTy$!~7#7KKL)Q54si*bXCaU(JM7>t{Vad5_*xy8k})y24t7<~=K9mGicI|ufp zFkp`oY-ox@zLVr*F2>_7#uLO?$Y4B0j7cdNK0lszF`jWTo+ZXWgYg_O#$?2J-o<#q z#dwhzgAB&Y#8@dK#w#wyt1iZC#29Qa-XO;688O~;G2U`9-X_Mv2IE~~tdkMrJs0DB z7vlpkc+%I-W9#w88J{`jlfG~8HUghotL@?a#% zc3PfoB-vieBZwqBXn9hQWJfIz^pUL9A6c|cS{}4xX=g3Z!;!4h^0XSsE?S;2BiU8U z6I~>`X?cQ*WOpr(E|Kh^<-sD7J+(alL$a5ar*la5*77tA$v#>h?;zP%%Oe>i`)PS{ zf@FU!k06j7pyh@=$%VAsHzzqz%iV60gS6bCCOKHkU1gFBYq=9lvR=y#R+0@`?vaul zqUC-Q$)Q^Aq*`av3e>0+LNyrfibqwaly}o3+e)BqwN@o=8sAGK-MZS_V7GWwne+ zlFMlsI(*ccNv>>)e+tHZ)LPkBi=VTPT7O3IdNb}mC(~eE<(eo|!q&;}$J0s02%ZTqvf%2UzzAp>vhf<(?Pk8)T7SvCaPFt({cBg(u<8T@G z3mMxo|YsLc5GNJkf=*2U;VjGV!!BSzW_H@@(6aWT5O7~P05(qQx;Mp`!b zV%5`C+ly*P8MS>%QR~a+zEo?k75cdt{fVIr#zMr1T!18PG7qG5={GY5xv+x?yNH3U zkHIEg_cTzC^<{{wbSRZBYLpI-DNVY`FoM#h`;v2EM-q0lfmKwL*89Gd>LP3$iGR}V zheatJx7m05VKl|lZa?^*_G(1qaM&&eMl~9T$53tBy#rsmFG01oFUPtV z#$mUtM#gr_>R{B8#+@~Ykv7JCd9x-PM`DpQ#@C{B>0^9tif0|;Gh&t{&6w*Hx6F5o zab1e1#mswKEoNC#%+@b%nQva)fZ|zWwqeY&q?m0~+%jLxHl}!5%zRVKCNayBVzy~< z%X~50jN(~iwt395q*cZi#Vzy2Y)gt~ojkT;o}k!5*No#O>G_l@MznU~-dS}vSPR%*HS zC0V8A3X5d5ma8a|HCnEGNVd~*fkLvqmg@+T9keX>Np{q-L?>CRWhG6rla|#j$- zoMc}u{lZNLMo8KC91O zyxEYLMT`js<49tp&3itK*{<57sCJ@JdoIMOdkoduZ+0$@m?glcWSKI&pTMvPSq#uLOy%VghZdD6vr%Efq^7^@nLXI-)Xx?;~!Y^o7^ z0Zi)2z?bwdx@upd+G$4ZD^#0xo%pJ&_BEu?-3*I-0H)4-&Oko)lN5RKPpA7@0$H%Hja#pq)U}gC|&v`@uw6|yHxRA zczzbMEa_6^^Wv8IE>*sucv=eja^*`j4!ip+GPb+F2BX$6{qij_BB4!kU>>F8q4hcN z9mUfe@D0uH**GoPeVZshpmFH^k7TU(KY>we8t;E81;f|(zq%N|xfs6_V=aU6Cov)s zPTB$Zi_)b>_-~4*jaFZZ{1dY*X;@X%7q!f{15iovv|;7jO|D|&NX(M5vbwlszO1aF zc-E|JhsI%IwI^c}s{zm;hb1@co zF~$&M1A{S^7->)F`7p-07)!bsOA%v3gRu-T_6c_v?N^M-yhv@LmPqF&U8IhuHFhp+ zCSyZ90gT$nn5L;TZdx#WVoyW*;;^g>wwwz#iC`NWuqgyfdrZ}bvAm11f{U>tF*Y$6 zD-k2>Bcv<47^}D#tAfEUs*NFc33J>L!?dIUH+9)z%68XuFz%-AlCr7Wt@DJJ?56G-6yMb3(3)g6GtAmx!htk{ z%!_7Ub{&dsZp79D6CIsNI~eP`dN!b*EsUOxs3&a)!*`C^xGW6P}{UDsLd#y zc2@H(RW?WCum`pvV|!prFltK^xvfjV@I`JLHjYfLN!_Rk z^J8BZV?P&Te`0KFFb*U})<^ITaxo5eF%BWdb_U}xVni||X>HZ&>N%Wxwl{ia#q=aC zypN!C=?m{8UD(-#-NC@lp`xtowWF!lE+&p~F^(n1jt1j+VjPo_PQGDrf{SsYi*XVd zoO|sk;bflU#LaWBOxc|JE3{15BrCN{$|S3_%&R1;wM-NwYqSh9lI^sN1(NNxq%6q} zS~81dM=c3JvQ|qUlI)}TFjZ4^)I9$)BgN8`}@JIGk??*yav zG~VAuj5P0k7C(NQOYt=CeII+d7mY*j?;~TqzaNa+%Xt4FG19#EEvFu0 zvAv&@+V~MNd6Rz+SiP-&xw(>U%p`D$S6y? zi20JzS>5>xjYD_7CS%?C28`OzxHFF!Y3}&;1iy1JzIQQxAjbX%<0oRIJ+a|iFaGRe z{NiH#3I^9D)-5jhb6ni>xdZrzH}+M4`>fTKpFn_Y!5IT%uHV zZaRR0Tbp0-`-e`IoG=v)5|IPhT(v2wLUEW1)gq%r1^^wwx;AKQ!$F}9ogk8$hQ67o zGaIKZ#eMfv>d-heybBm~_rc;^n|0kvvCg;R>Fxsb5CA0rh)hqiRWmA8a4pbtr5P17 zTK~bn>GiEO{V!~t-q8AY#q@Dqw(U8nWA%vE8!Pay>&88+*R8AQHofXrBqEdyfD-)l z$B*b3=Ra}4t{>aPi`ivb4TEiry#yPD<5gB9*vBW9qOu@ zQ56+qE*<)5!)QE|ToIO6)>KWNGiz=`MRP0K5&kcz6IX(QY_3!e5nUDd5sS&gm7{>s z(s(3})|GaF;3L7$`}oNngX-LIIOHi9ccn&LxqQl1LyCAY2Tkb3$Iv8R1O;V!q5DI{ z?G>WwHvEVW^_`mn_rzWFk(_62*t10-7Gej|77}qId=rwltoGqYdF>sK~Rx^ms*m z(^-OA+4?xD7}bW!sHVf$rYQ%bJkjeUIp#qwo!H-x^9@bw33tAd4 zz_IZ>9?s?AY#gjJ|AkzhRkJ6*Hd00$?XRdGe>uvE)Kt|sT_!cu2`9%3r$id~&p}=D z#S~CdfuiS86rJqbHo<95__fw)%&wPW(w|;ZSus~ee(S~fBV?hmcxU0Yk<)@V9pZXk zreAb)&aCSsm0KICQG|cU)_Ehw*bLu%$W z3g*!`MfHO0y zmGm;$x9D3e^V>BvT^**u+YpJS?jJY-`cm#4O24@QKi4&>wFZCpSLTknoC#Vx^Xpw^ z$nfjO)7F_?u}|(AAo;YtOY_Q1;A=z6-z%}Tlfc)pG2-%mtZ7+!_dnI=;VCri?T$#` zpX!o=JQk6j+I&47Q`Wr?|NnH)m(nFVsl-Y2-bZk6Mvan80Q)i7Y9%QR_7k!^P0AFV z=|uB6R6x^b_>rlSJWe#5;^f@Ycnd<^coPpd;9$=&UqU1@jPk6tGjOm37{ld-ndYzH zV4*5>UocoW{pYDSdb0Q$ip8DVP?hbh-!n-19{3S=$itofSUbG|rH!xg@Cpwv;b1-L z1*tp>a8Wjzj>wGaoJ+zpX>~)>*N|h#dgG`0Ei%d$^`jo*glDP6?8(BOSjNv|i`+#D z!I@WA(R#W0L!3k8ojsbza+yV@jhi!TR$WCy(>DSl4aKScgrO5DC!am!bS9}d7Uwjc zj|ZSB7INQ;M$sF!xA<9==a!p?;jH?{kT4S6J2!ntEn?9iTI4z&OOa`B zn5D^dFw8P!IvS>lOs!#>$#gQz1TvisGm%W4VKkX8hFO+OSHmnvrki0Vlj&}lDP(#W zW_dC_4YLB7UWREQ)7vmBk?CWYmC5uq%qnF18D>>58IyD>nufVC4a|(1kY%Rjm{Jpw zTarx7@785%D=M_aRoEu7l2F1T_NlWWF-fM zok~{vM%Za&B`Jkni>!2(uxpc*EERS`veJ9PZbVknR@g1cN_Pso6tQlZxW{_FP zFzb*RXqa`$3^L66WCj~%12PL6WLfJL}s*Mb|%wkm|e&$W|&>cEN+#DlCno&>7%7Dgguh1B$Tjo z$V%r3do)?eFkz1)E4?M`@nj|CgguF@bf2&%la(A4_FS^kpTeF`RzfK3Wn`s;g}t1t zq^z*lla(G9_6D+&!@_dcN=pg|%Z(~6Ni8gQj2u-qfklI6nQPgXil*ayf;_X&Fx zLZ~H$gq=fH28FQ4l9iki_BgUKN`yU;tR$JRCy|w5BkZYUCF_JejjW6#VJ{^sX(;R! zWF?P;y^*ZsrLZ@Vm0>3=lS)gX3VRn>8Hd8&M^>^>*!#&!9&-L-0x6q5M}WZvKrnyF zDh?71NGYkhd$_$3uHvxSrD>Z?a7TlHIz|v{<`0piG^ZlC?D~{*o%)zZQ#ECu%B7IR zQkCftOpu`1@=1Sx5-DB=;OsA1nmUt zDKjkMX>0MFp`bGu;7YqVKUs9-K0-X4z<ty%yMDIaKOy3cDh%p83W=5?NIIw4s z?bs}lP$Dy<1B%aN6Uj6%XHllTvb}OP*>=s6wMt}W)IjPS7FR3De6Z(%EyatSnTiUR zLFWy32hgN29Osv%h>mx|KHYi4>G=hLO`;6!B~<0PqWTKGE1k<3Nlhj^T3m*o<}cat zU@m9P6jQ^QsucgCdp+D#l;@toS3v8Q*OyeB$mCGH;R5q2pTP^9yGaTC}+k)p&*#wfUl}vkDw?GBd-i#j^ zCggEK>xNCBl`te4SL9)N9PIwjtq{nqih?}rx$DARpkcU&g(LIjHVRBbU2c;Nf*s(8 zxv51R-0H#EJUFRLZ%z9*4MeDPGWb}gP0v+t@hVs72Bg3XmSlgm;MWGI)&d5$(?jRJ&xi8Nk zINNWz>ENYrIP8K`{#tAgYq=g#2a|~^I|M~3$~e%X${wJyL*vR0OIOB`6;<{il}W&( zmK~n1jAJRP>>(z_wsJH%zsjKUU6ebXG{&kNKY>5rpPQ*@{(+vX*<*-~ydRkTj! z?7}X>6vD1A62Mm=9|rJsFzOhhOFp~_0#?3-pWHeqEo~0LZ1;%Fc5k!Yx<%U+3rN`R z9kyGqXuIIytY{#^cJH#?`bFCX4_tZLz0YI9?e>!PZ-%Jr!F z##Qw#Rh?*5%`2+vLcgl-Tvgvw)k#Lx4@Fg7z+TI-x41x&ev)yo zrDI4|X$dUJYAt~wS);`SC^e(QG6^aH5hDb4$R!9;ii$4>{d%BkhV&KbmvpFc+6PB*5bNcM-56Q|oEr!t-p zf=T}mK&44jiF416i045dF~t>@=XwhfyYU6!KMM=^?BC;hdc7$01ABxQiT8u@!c zajETcC%gdsXZ~zAS3xs-HdHQ!14k^^WLPdqx`M3&8y$mfk4Z&FkDNQIDV;P1c{cuc z#$Y=@l{*Gc3CCdjSnINePIQMMYDQU#GL69w3ySf@#$Yr9>=^90pt#gF2E#3f+WE7+ z$QbMdjTnQHt{8)LU`ro^T_~M22D!5RcgA4XnCHcxyKv8gr-oy&TdZ|iL+Af?40c~o zj4w6@qZwewV2=gGr6Oan=lt1TWDNF#MvOs8SB$|vV8hGQzO3U0e18z?v@oL=0*lgt z_{nX8(lW1C2eI9zMcXA_uMTFr&5E{5yk4zmyN%f{@w$_m&3sYxy0d|5BFpr`>rP^% zUUv?Gn!J&muq9f^VtFV^)#>0E*kNFrw=m3b)|_FO5n#%??##KWMpD(8M%AdIsuHd{ zm8)tIsyfT4TC}LDgzL`HuBt|=I@_pPtf;Dl>(0epRb!~?9HVN9qN*-Jh&@-sV_j9_ zz~H*m_5yn?$KK*~r}PuAB`dXb49O}jfhAe3B`_pwv^YkxofgA*-AUcbYF?6>)2=&% zH=*n`P}{cLQf!=d-C1l?hD+dO*f^5VN!OiClukO|awhn9&bQ+M6kHfsKyAr0dSf zlujChJgfdYV{l5$^Yk(JpKuH=A8Wk;jlmTb6yuAH!Dt59F}UJ_;!@if46i#|=Fj#b zV{j#C#2A!x#TZOnYW~~Yi&ESJCXB2^3pamd`)WIZjS$YUQtqV5H*!5V) zOSla|s0-MMU^XIip zW(1F{K`(|X=*AmI@qO3LDec~LrP@|L)8tvwZ@~s>>*HbMDZKx3DXo*xZWn7^);Q&xv3SBT0$-Mb2G1+7 z@`(Y-o3V3(rwF&7KT89kaWkFW{T=2{qj|bAyYH)}`);0~+;RRa4S*uP?*xsQ4kQtf z#k+vbJ&|%>(|2ofS2PailHI7dM#)%*;@w%dh8YZdf>D@Ak zFg`66yRd~4?A~xx{8`^5N?_{VFi6J4KD4al>1JO_mowe$#|CNBjW5>w$85U-G4M@= z2T(fUQXn3!VtZ>r$mi!C@qw@-I!UBoCtS(CmHs#wtUa zp`0wS*Aj=r-`qCn!rZlZ!f!67-HO)Z@DxHc3l?vClQ#Gc0+TH1am>gW+;g%+y5i9U z`wZ;N1tsvoMNOVDL$s{m;oF!x^Vgw!qHaan0l`#3t zfpmCUIGUPjl$~pjVVylK91lia&EXD=6Uba+m=nRIoFj@Y>VgT&tU9lyt`b(AA_oIb z0;Wtmrw}}H8n`aO+fykWI}PwD{YcKjH1n|JX>5>o8Yp%K)t~SCMBGuQzc! zBWAjP)oI(D8EccY>O7kUM3z3$yySJ3&Ea!mvgxz`4fI61;oMm3vaz2Y+my`firp5VI|5fqf&T%UWO;I~@cWGd~OLn_x$DI!>QrZ)4|3 zf7~2vUDg!)f4j22WkE5%q?NTlJ?zT*)&<4iwq5%0PT6hqXM2$q>K*f^@qcl3aOeD4 zT4Z&QpFfTNi>rgX=Fie1tAo3t5$^=c9EMZNJz%3}l%y+@xsVQ*1NTx>J0+(oXu6MV zjgs>=*!wAJR|gM)QMYs2M9srw?l8LC4rhs?``wRG zI(B~K`8$&TPoZ(xO;3YCzetc^#xtz5{qh_b zb(iUi=gHh{m>0mzZ@=6V_REXZ7U`F{3H|aCrDOfVS7AN<@-iD_?Uz?#wk7q;tCY^# zFR!6-*e|bxLBB|l&@XSW&i2b&VAQ=~_}&Ja+W{;So>zzR^|E(Zx+6+6_mjQF^)58Q zg!k}+H-mRFK-IxJoV(HtwKI>V3SV64hV7=QN~-dd=k8O&{i&f%yRf~inck<_?khFX zWxZ8bq^pC~UY;%kufFL%>V(}NP@@e`g@i}hx(`t|qkXfOuf&KM?a<_7Hi;zU{ZQtc zC_bTdVM0zQVj;)*XB19L#$vn0Z2Wo5uB2rAg3{4Nw2h7!7rDikw#tR`=EbBhp*Bsr z@W$8!VgG&=YrO!iiN9V@j1ShtwzusP_nQU9{I(@-wcYIccK&QHvc#PSjaZ;aYGQ1C zM*vO}{G#!LVZMGJ!;O5VGBV}<0NLoY(e?*rBZEyI1o<(*7bxKW6lEAvzAGlFY+~sUq`;VXDbI8pfvvY;HHOxhMGTg;$4G zv`)f9FcKG;WmZKU-*U$U@;q)IP=q$LW4ql^7ujy*$0h0`C1RrYCZ+6!d6LN;$aX?mPU z0O&>qdl&_e6QJ~uV7U5~RoH_Hm19wEu6eYi1r)#>O-pX)Ix~F)yLj!59Gedp|r}x zCA&u-^dydt40HWx7Mql4p3xq<`%`!6Ux9FSq4fZ?4oB=lU@&n>s-bQm>+I5S5bHRa zxlg5@pkuPE8Ui-AFWAzuBitn&igwU8oXrzr$Zo-(Q+Seixxd#B#>(G4k*>sSdnndO zM0PkG3G?s(p7RMb{fnOgfnoRzh^U1>BjAt3B}d01E4`;+FuJqoCE-X)7q0Y%70CzA zaHA-kb)~1!IPCC6z@Wpe@r$y~cKB%4vBMilREOo#6KmqgcP2!beYB_Ej};^j(=wxz zY&{FX(O27=)~m?MnLujqCwpU9%MWSm(?a%Bvd4t%*-)?L^dN2dr7kT`z6s0uUCU`j z*ayg77PkGg2CQ6SO6`|qV5SslU3#(=O#k(EsYVfj%JEguFFmiO(n-0l>X507bi z=1$nv$jaal_Byirhi2SFRxYpjz6j&0Y_yjEQ^qI`m&w5_!K@g|ZsKRiS0P@ePc|(D z70|RKek6y6@@>_?lH4w@{3pWI6*kIn*l$|FrAk=e|ArwOO1 za3W}8(?8siO+C)Yeg|w|&v=Ty3^sB?&PV0#*|nL%1s5r7Yt5lQ;is4K*0{t+6d2|S zP@5)Qc#-m6=)uGiTRVS3;Qg?%jy0a2E1ZbOWhn}lya|5=gBJ+b9>hy(#e#RvipjxvgQSzHAJ1~6lesHi9)63k&mMa((poO2v=&N;tl&N=(c;Xmhg zS9Mo+Rn7Da&-V}CN6%K*z2}~)y7yL?o*CmC3qN2>(1k14S363f*I={r%OWFNKV&Nk zsx8Cnr7gW=Ow6_vq%9bc;b;Xu7Wck1EpoWka2vHF>ZOggul!iEUdV?#>&V&U>lfDs z{rsyKm*itvM)(?!axgGu^=o`fo|4Cefp5t(60$evscrH)_0o^wV_EDobcCWmGDY9$ zGvl$WbyKocq(=jBJs@J8CGmxTTA#({f=ml2Zopzw>pK#CGTWIeU2}eG`G|5dKW_-d z{A+X$&rqxRaAOL;L}6o*90QlnN6S|Y2VecUB{hc2cM@@jdNZE}q%}2zDwp#5Ps_)e z?pDAZDt> zs~{Ex5e9Z65=XoglIo5=;2LIkRv4cwq7*76Ef@BCpjl?{SO;aP)(VRrbu@jS}$#imRHC);WtkoRxjkkWz!T zYol*D{GS0tO!YF>h?FB(Y%YlNqd1errh-i21)1=1^GM$0&izI4@@jr(^B6z?>1e!& zPqB=hdrv&dKce^>V2i)-@)Is<=YA|i@_*t+V#`iJHN#WhvSmLmuy%a#asq*jldc?o zSs^&-qG`R!mbv64O8-T(#xjIN;?F|HmLVro<8RcLsD>oPMAgtwu8x!Y)1VTUZpU2G z-lwIJzxaS|I$d!P4Dp46sylTS$bHk9@p0Y@STQ>5e-`UY! z$ug034H}t%%4XdtL*XHUFhgBbFXV$$6S^e7d>=;*80CxWg?w-F>aB0184;LC??ojkEs~7sw8}jQ2gU z1O$+7z>7=|EMvZ%A}8ftkvNN;dFh0Uns0A{NWMF6B<5QRs`-}kmihK(s`hZIisJ^4 z|2Y6|AwW+rK%*DnRsf*Aw-d)aQ#X&|*}mxLUS=}(hF$`c6hX%vgjGZMFi;7m%1I|@ ztX?n`jK`fR?MxF*V#YE^X9CJFV=?svzvgmRy^s&q)IJYT`RML?X_6%$-CHl*gYQH! z*VPRAXkE>KnXL=29UFPgahVi+XUcuGwbGJx?*}5Xt^_4=$3rOQ=L8-9_cfY?+-eIS3r1#i%&aUKOuNr~#?$PRs4 z=4Q?Tt;ZnHItL2{b?b?g?dX@z(-xkjv@f@E0+=yVN?!(w$3KHd91X>$*|5c6YI^VDa6 zK#M=ci_B9jW1c!q=BdR1Tg>w^02eh+eGZZQ61b6=rzoiADau>ssV}HH$f+8eryKxZ z5}@b>2=}lKfUgL!Bmumi%BP7ax{L+rE3yFnhB(Fo^x@mpc{jUFPmHnv{g%?V$XDvj z*3{6xm41XB=gTFNDINTKiu-0`_I_eEHjHY_va|6IFjY=EIUBDC>w&lYn9|NPi6+*8 zsw0GSCZMvjad50^Zc@!oMD7d@EdPTxAs0v^F%~~_ER2;S{Wt3TAuYN$exc}K6un>7 z;C8JbyZy>OB?@AxWrzmhK^?&+If3HO4nR>E-WP}(RcOAXDn zT55AyDu^YtCI=f?<6vd7l&sm9($3_*|6Ck|D~W1zUvNs$R4=U!zf(2zOSODxt{3`? z;hQFJ=&D0UA2@^`RdT%T*#XVNd(YyWaO{pOHWwt3pg0?fX81?%7$%|+(w!)sp0^q{ zvCmtxL%elyMg?>`({NKk(j$spQ-*zcr&~(8TteZAO}YVd5XU!@n#o+wstuHKIUzc$ z?haGsq?0r0DmsJoNNN8+%^<;he7+e`&!j!;rA^fZ+MH+}99+f_4&DpJUlTVHI}!@29SP+vJCcQ{x|UNlwj*%>EKC5S zJEM&N*_s=HK9o*(XHF8TX@MJoz7+SRFE%<_i%R-3jFuE;*^R&=FjY=EnZDMBb&gfP zlx{7_%b=VIsH$y%*@Z#!DyWwA=KvU^8_ilqN6Tt?K)KDNImXX_LN^V;pu*G$G8HtO^ZAFOWH^PlXZlj>eZIrj< zwk4^$u~Rjc+Z+H(5y0rqD7TTVncD_aI^CT?ZZj<~w=GR^Uv6Wg6TxB_Eh)^hxosJk zDkq)HZKGkGW3_BbHE9=LaNKl=eAA4;aV}Jo2i%E|FPk+(+oRZpq8$xTx86 zHHhT5!;Qr3N?gk zYeK(uTf(8R77FNQK}T^NV)N~qDzQfrj{P3sSJUt70Rl|c#f$Vi%joxWrQgSbc5z2u z#^9p*eSL`Jcg2lFzf(~4JLN6?z5!LoIaOn;8VA6J1lWxL-eXXj2uCyVo3S{-=BR8; z9OInc2z-=*jXJ8Ycl!$^JVl#0Vzb8$A%ceA79L9%o*28!< z-hCL)5!0SIYGmtV+9)VXThweRI*dp=d4ulV{?pHR??^o{1-73^-$n<6Fs_X-p2443u)A ziAghyk#c4K!RrmMGZ%Y4jGLxkweBKQqsvK4qY_9b>R{x zjWd%tJ`XYZ*5V;Y!clpkwQWd$5uSju-K~4m0O*;Erd5WFSyHp2g;ZxFd=uplHTw^zK#q^btvlcFL3giK4;&C_PbKQl;xg# zg5!}hfKuZ8jK&T*hL%di#MB#>Y(9B3 zMnwjtAnid*E@ktY3gVL}UXEhrx$Fu`SDwqRq%CeTf_zrZCgWN_facYBkqBZLn~ck3 zlW`WtsCWi1r}1(ME^3o;9pv)o;znYVK|!_2puA<1aXnRyH!O$~t=fj1hho6y28t%$ zupl43Y%jU(ah|ym`mN^>4uzXgz{m(XinkD(o2lRpi{trpI2(+tEl)vZv2!b-IS_%Z zY6jvCK!DZlc#(l%83S>x48+CYRlJaw^KnsQP=ZMQGTcav0R`0_Br;Go&}63$r3vt5x-v|NK?&@uN>)L6+U*XE>^T${58wb#fR z|9;~5*5)PyS(_UuCDk>KX)4;iJpfbXq?41{wYtF%rnGCBu?*6gfXeRQqW2M^q2|a(15Y<59O>2f7NyI zh5t%G3KsrGCc~Sn*V9HpS$eK!OKmPo1+j$gdY%n6vQhabgKi*8nI2zAX=lo1?dE}n zK_e4ThNKw1x%y(gkPqKn4c$y7z?bTUesxLY<=UEONg}TR5s5;)7oPtri(D-RiKLp< z;=cd^q}TBx;lMIhi}%QC@m54h@n&9b#6_(Z{|%A+9k`KLEmBae7AbF8Extk35><^4 z$P+BFxKq!My$OvHHNq^`{&xd@m?q3;ci}$SzeQLhpQSXI*$kWpsCLPJh);D6nttfF zT^sTr=s)FWu4XoT+coxqPIg6X+1GkEO&1h_cm7)hqU@I-P!IxW`@8HQ)!mK-WO7M( z56R1Lzn9X^l(gE->}Sx(1XNY_d%s@DhuJUXlqwH?P+LPRiQ+>bB2mad!%043k%{7V ziI{2<#ixJ((kFNk&tVyf;$cY?4+6G$KQH&y$m8fl^Yu9U&X-`M!p! za?;5Fe+<@xVfrSeohdHc%>Xw@X9CI);L)D%+j=2y+w++ophEq-dTEkn&-Z<8+%0M9 z2OuI%iMt}Ieq@np>S6kCRbT(|Ga!KU6J8`uv5YkJl%%Pr0b6{Mm&b8YY3dh<h}#q^V!2`aD&Q>_V_8yU3PPjsNe^C{Y8OPiC=bJ<~XQxT<*xwE_7*2yd)w z9GY0&;Fld@s2Nu`>=-k_{Rz|fdheIXr4TXt>%Yq=TJEG7{Vj|N!U!Xr>wu0_!{SJy z$+Y;2?%76Y=U+rI-D}1jz1nP?-F3fH@bj9%FH%jPj3RY z_-|fb=jBygRF3Kz=yk(O{$1Qpq$SXtD=G&-cLKamfFFDhRMA8{ z_pLfjelmCzMk)A|K~Lfs@7l0I(OPN9$0!E9Gbcq8@7l0`bgC-38_sua=7N6f+k``* z7YZ0mK}T^OVjBy@=z%W7hMe)wOKIPF&uoLN_Y9Ph>QzUoiq?Dc!BjcvWMcb7ciH?Y z?M!(ik$?=+nSe4Rpy)>p7N{5UOh88!%=ej04}iM|-@dhAy|gKKAc}dQL6cvoUdTs} zHF5VKpWIluUbqKO0;rA`?tSWoyJeTq7u=C&B_$!x_CqoM4)Rm}8_%Oq?pY&vGowE{ zg!3aGh5C%yu0%}Cd0~kY6K9y%`#UY4Qm!DybsJJQ<#}%h<|RX2_LmF#!|9G>(??IszHP6vq8ZVU4cVOvkKBIjL_0(5Z-f? zfkbf`7MltZ7AP)@qPYU<=<*{-FQ4k1@*eb!_MjC~+L?UCvNm5aXpEQuy%rX^HV>A2 z)tqn+1q6^<@giQ&GS=pA$lClzG^O}GFW=&#mgOr!B>yvRB-Y~;RO@ldTh`-kRQ<)N z%HhlfKVIShSQ!AIJB&Dvbu3BiwX&>Zhf_NJTv+gxCZ-`SpjV~1Z`sSXM@x5E_8LY@ z3bX98cQu$QC!JjO{toNxgVj^InY=5Ji44k_fXXg-;fRFHDi!5 zul+@og2Gy-0<4C+99RXx0;7?nYz#*EjFST@TQe%9n`t2bIgbeECZn%|B(9pWE}DX@ zEklWxt;fDK;yudRiBW;{`jk$`d+RSwH`2E`(&=#}kPvRBTWYLWQ0mB>NMI4W1 zWYPB}i+05D6q|Wz#6@M%(GbbcjvI+ANGbFZzOI@T`TEun7hmrr{aB5!ZwCkrz_xf1UuPM<{+alCcfc0A z@zMnsUENuK{X1J?2GUND#=8T(XsQqy9Ge1(J{y+?*_qP5@G_ex ziwgtAY+HJAz*vVL+usGI%1I}~Yi`|-yQZ`=#YJK=F$N?PP}u;pJvTe9UdY?tLp41> z=0(KYZuQb6%jwAOwQ;v>gvJ9An>=w>bj}18@%v=-UKA&?$Qiw-+^8nY?Fk4VO~Q+0 zIhK*-zLhLDKVXZ!d6@?nmE|TwB)<@DB(fX@RhFZ?CCg2r>cUhtR=fmDta#^8OWvte z=}VQh`6c}@(9qtcCnBCOp*g<)AV+J{D7*+NnEv|amvCz|m59l;veMm$x_`xg+&Gkw z+{CUh)8u}TFVPl2XbwkB{ZL|W?oTLVxgE;!t=#+oNCgY+1ZZo2>K7EsfnJnFT_^=X z0gHo4Pz{7*k&?`dc`^`3XisTpN@t0@Xwb+6lp!xhZ+0G1FXY2FJ3~)Xt~k9m`j$L$ zXl;o9+tEC%UdV@|83wx=&BJS>ZyC)QK*Tg4!HPgXf<;aP3o?4Edh7ZqKmh4Tyh!x3 zjA`I!nFf{sY_Y)0KwQ)`a5O~nOX7x+%M)_~wbYzI0Dy#pd>ftxGwyyO?HSm85|GlmC%X*OyJT$33~g4ly;^RITdZZuVAvp zx$*e}_+H=n1Gw8g5fknA0GVAA%b`kD-?G7%F=`=5!(&9&=jcF_&|dKyx8nIC$h{4&E6+k=|%QRdu~_ zHXzU&XW>P9gJtx_UlKp70Jhl1%TQcYZ=3^>{HnO&>kVqD-k`F#H_j#E>X0fCHgw#+ z@;trW$<_YwJSwh{Q0&u1#pU^^E)f?o(Xu99gEn43tr66sYG^L_%vE1?D|mb=c$@D+ z!caaG#e!*Vf}!6oB9yUU3gzTvawMdJ1rvKRHg>J+P`{v1F7cv_a-kFi1uQNlLDkEi zoDvV>b;&@6{IZmGrXWsCu?CGyK#2vDBrnUa%tqfu%s178?;^guzM2sJU{dHR%3H5M zBd}$Xfx)0&$zoIMTH-0k)UdHg>%F9WFRAOe@eTS05oW10?Ir$ zL;?6feKjErz|d7x06vIDAmU_TFsKi)$XF9+tSZ(X1q6^D!HbME%ZRnE5^H1O0L2}7 z8H0<8wZ|Zm-xW7}u|_QwYgG2e+7m!55iyFj-B2R2CzUa-1Nuro6ja^Q2{i=W?xET< zR5OAugikEU*ur?wji-J=p*-hBi56rDl!Bmu{PQHJT3=z%O&|jqiWgGanPMd|>lrjM z0c8%lXhHU3eKjEry3kcr(7l94An0UZFsLuH$e`Ore65;8>(>DRq}T8wBh4~`?gn=x6T zR~`WIfb08;LH-)~g=Kzw+%f!CAp>!#=)JrPx()_S9$w_P*&;aqewaI3B@dbp^p_v+ z*0&s_Ac?okRHHut5e$nkL#sYU5q&rfL`&>F*y8}^_rl-#@ovKuT76{eer#Z2A6^Ax zS=`Qb$7N(es!9Y#u|zz)_HEghvNC+1utQaSXuEIAfr4d>O7w>S%dx0 zq}x;wWzhVUMb24MiB{D@@lQYi>36(H(qkF>2!Mwwq*w7IeHm}@AgW(LYfbIme*OP6VWPO2JD_z)+0!l&gF6ayl2 zQPf!EpN2Zj82Dxu^3s!xL~}1lmy}V*Y?GWnPS>{PPHEQ?O$LojKpEzbRpDem$~(C8 z)C+k=)BOc`+X>`<7V`7fM&1%4y@80MbQxTD+}eH3aVuyS!_G z6wC6t`V8$|3#PO)IYlB@|HIz3P`!|kyo*QEfp;xj8+nU&^#LNhO9mI-)tAMlf_N8- zi?GOid=dx0s(d^E5J2jW7scLc70K1` zqE$>UGF7<@4}FQ|0-YR?xicBl3n&NcuNr{^^i=inNx1cVV1k!d^qBL7Z zZaq{yw26s=fTH=Upjc7^RH0+vstFBCX=ifmUE$ad7F2UFjAx5u4-Y7c8Bko6MLPCX zv|E*9uK@@kt&SHNPL|==*NS7`3E1KtyxfM1a_kWh$=`z;3CE_Oa%{?59D7Zw-b+=( zu?d!NY>rHGXEiiyQSbgr^}6e)n%0IMTDK0>AEJ8V;X*~zGrY-%3zxy;gk1lQ0%nPr zC+Q`e58)+(QWD^>BC2i!@%8hg=Yh+Uz zc`a?^^~#NOENf&l8u?e+$iFK$GJ9Dgo72b}X(Mk|ZlrTrBU{kOTWKS2S8k+RStDE0 z$UA8x?^bSPj9-F9TkuopdkJ>I;a z%#1b$HI{7h9-C-n6UlS9*`-D5Bya3QWtB~ygo@l9i@SyQ31DWE4{)o(Y|;p2e>T~f zMm|g%`KWRuvz0Zn3ypl7Hu6d3M!J+WvMY^znl|!Ta#p7b^X78KlWL~kyLW1wyVirOunh81y(iPZQ! zB(MhyU$9{M$d|ZPp^xy(GW|X>iAKIk8~M6&Bh6)v>`5cvq>X%Axsgs~jZCJI@6txT zuiQx2vPP!R$PZ~FKUQv}M_D6NY2-g?BR^Gcq-R+p(`e-9w2@ybH!^2gBYV-vuW2K{ zRc>UivPSl%k>Ars{;1qYud+t=p^-n+M*gbY$lPU(>`Nnmr;Rk+U2(+EQ`X3SG?D{i zBCRx5Ze-rFM)s$XrnHgf%8m3cYvceL>5w+kv2r8xl{Io8jNrZdr#LEM-p(^$b5@W{ z9n1=nr-NBRvS~0YNX`pp1<6eOvqPKY5B}M)O`@EC&ekTe$Ui%^NyPBa+1tdg`Dc$d z@jm|9vrT-2f6mz^BgsGKYLouvpS{|oS2zceenF8xh;3;q$Tkdh(@`vO(}|`GnT`Ee z;#LwRf^_OLq*L-j)a@mNqg+_q357l^ZF)!#fg2;Iq%5FWGzS;5<8) zJ}X_y@ojFC4wa#9lVB&aQ zP##BN<0Nb@S8D-%JV8QtXz8UvPDp{w?EyJ41|lu&(lU>RIw=LUx_)CMv55ztlPRs5 z+DV@3!`)MG7f<*ID2k^g>@|03nOEC8J!P-Ahx!?Dd(Fz;nSnh4g}t*A_8Pmi%%|<0 zld?Cz$KJVddyUH8d4W9vg}nQenn+xJEC|<^5Q|p}MScp9Fa>5#(xR8hG6_D1RxUg>Sl_?OPCtei; z2|clohPpZh<@3aAD6KrPokv${w5~-ByitJB`s))m;f;N@%^OlSecpIu+~zQ4@20?> zfWqD_348FyMYO$JQ}%q`cw5|FUuEz1z@C7@UMXP@-q=suyEA3a=Z$y8?e$Rh?hfn; zDD2%sp)B5bFZG)X;xo{{kHw~fcq5AUv&hrw;MlL4hrk~K1dtxYi=^PGjS$~9xgCJERY`AO)K62YZ zpHM$ap<+TP`grYQtX>k;JZWwiIP=iQ3;AVH41T%_4^`aLcciZG6x1*0s_zlhFYl`F z9n`Pjs_z@rujr~@EU0gB)ejEphq&rng8JyExf1Og7Sy-8^w$dNhq~%F2@wCs6^#k5ye7G=D*YbU@ zuy%oTEk6Ym)-IT?<>v*$+J(}!e7qy9T{vCKZ?O++`=o36HSu9>-*hd%i!-QAwx+MH zXQQYWUAtCPyLh^GR8+e}x^{!8c2K%@bW~eR*KQuwE}5>~I;veNUAw)mP4>i2&KkbI zZugY&&YDTOrhRal1;3yr^vtExwfjW1%cN@$h-#PBwFuYO8Lop7uCg>Jae0B|hyHv{ zCw@L>FxL*j1PhHfp;6*m1#&Ix;x$+|y+t5nL$Ds|g41;_qhjyp0^}WngvN$0gKAlO zy^Fhr^$7`)_gL6~1rv5d+_J(N>q>4A+LwcJu+1@7U?W=#p^^7#WTUi^jVm{@d|4wO z(8%btkxeQ$vO-xSAJWLCX(O9eZe+!>Mn0mE&C^DQ-^9lSH#53C``-U<1&%WWs$~5O>w=(|!O1kiN%@1iLv+?ss&+0wP4=5{r_{uv2!{_wU z-SQ_HG#3OIE&Yp@GxpMiu$TT$=~mH8nzsJ&m>eH{WTz=R4YNtONvDBwjz#+XPQs%a zpYH$&AT{GfI+tbm{9WSnlL1?t#LGlnl+SmBNPZe__A(<1> zC52ewkhIel8aP)Fv0KfE^accw=EaMQ2+J6e z=Ve3=2W;_BUJk)UjmUfu$Op@JYr3zju=GN}Vjsp;-X( zC52ky&>Rhvpot4ss6Adr0bdOpgl-;?&V-T{e}2?s2>$Y=-u-K%A9L#EL#G}fgIth7hJP%| zB0g@(F-I}aBJ6=EtZkDUX#3a5@3rb@Nyh3DsL?gk^HH+;mcdp zQi+Gk-n=!4h{ks~5nj|ArsYq^-@)WUK4u0hLbIgsE6iYL03~Sbk}2(4V#T152`CtN zPs)g5Ww?%&rRs%z7%SnBs#qCZ8+}WxEDb~ihYT-VdKnfO9H(%+tNK{U@_+!+a(I#8 zU>U*jwgktyfGwWQ%bB>S;8+17`3rEv7aY`5!9itjaI_H72oA!l;J65X2f;x;W^fFF zW=Y{!7#tS^C1`AGN;{KJCngeuMkb&P!7)q+$IyBq9|lJ_q$)U8s*S!SINE@S;E>^k zORvl#gX4UTcU8eL91uVnh8GDAmJu8uNpM^N*y3fpT!M=Vj#VL&zZy4u!9gt*98~rO z$7(<<5fK_ZD8Ls3UW*cmtxjV`+=OzQ%)q2_J*0xTA=Oyiv|dO3f*|d+=Pn?#0?;qzY8}KPn1wl z#UACO*wf#bu@P18rmFGbM}oya{D_0Q5(xlpcGaV!p<1FU0+qqqjyHPS`?TDPI|2Po zh;1A!+>g2-OxciFn4;C25>BzKFti@fwl+&?XNrhKXc;sz0aX=Ro7W5ZAhbBxJpYwV z(iXLGx5U+!K*T|=j4k|PD;Aqt@8eJxBInwgc4OYx(68k|ia=uEY1S_AXOm=}}18Ej=QZ6v_@>l&kM>pcDiJ4c-y@ z=rN&>;!fmixN!Ne6M2k;q_tyH+L;32e;Y|V*9-Y@k_sJD1=B9I(YFNCu0Vuq$ne57 z#}ItBDZFKZhH} zoRgTlsHNsEDo1k{B1)Z(`ut{iIcs6h`^BHg*)%fA_L=Dj(1gyx%~hEq4g(@WNQM`Ve>jT_q1QRyRfW(@Kmh3oyhsSKj1VeF2)zf`;yb*&g^LQI zqac$15I1}wL@njhRQ86@(M0^XGDOBzu1TH@DT{jyaX$raiQr*q=JdD39Lws@Xg2Zl zqikGAUVrDx@eoEwoq!kg&*zXJ6a2y`zDNBFlu86bfj97->0hJNQ23J9P#E8t-UD?b z3sO}g0*WQ-;&njFSCo}8IFY=*L9rAPQNo?2@m)%65_BZT1V73pWaP)~)bDZ~cvMC|raBvWB3ecnPr$CwN%@Vz^;LzLxV+N~eFE zJ+}#3k!UXsUq$gE|fC?m7Nwjvm8}09z#iZ4Q88P78zMkExVEf@F$vS>d<{7Pg84`tJn<`Mg+7p z+@rkjYGN235`7J`F<9au*HGFVa)nvT@Lo%9M$eYtV&~Wdc;R&^-AtqM&kZj>^>9={ zbyql)sukCx6^L6I7c}Yy_Omf69rZCwdQ@(tbUJPu9C3RSZ80eaNu!!=>TQ4k&0Fvy zNttCNM@n!NdTIG5Nz3Tj@|k%qvWFKwmD0^LDv8W&kjMm7c6j-j zGCZ#o_JnNd3aSxLqY(&O8471sEJWzb(!==T9^aUot7z(vu29U>O`!6Kb15q;_^ z`h+m){|i7ue-TtwNB>Pgfb|=~8h@}1`s)e(JYb6hc>$; z2$TNX022C(p{hFi?*Rg=-xb#QgJsa)MCca*TU>&d0xpXF`w(%`r%FVhx{5v_O!^-H zNa!zxs_N)}4hXRROjzR&mO+1Op}!npi_7pb7#BtV3y9=b#Eryygo27IMD|KUewjfV%gdITfmmeNGE6Sm0$|} ziVprRrJX4+Clb6tBNI^B1Rp&i$lqiPo~Hf2UdV?Bj^Sv_?1aAmprB61X}zjUL+=2M$#KA zNpCg47Kih)3NLNAsLa>U2~8P+8;Q(EL6uY}Z^?W)s;=o&jb%OuKqCOaxhZ(*KsaMV zMp{t{95NEcpm7~3n%I!Bc~Rzb)8`6hHt4smK{ymTp#Yx|bQC)i+gRB}8#2R&EY-SD zI=!+BHe_bAX}BxJ&Gc<%eY43j`5Q({3bSlVp97}KNheeKsIW`Ar*t#r;Y30=C}#pH zo6v1XWo8$K8#2|ho*aO+&`dLY>BaHDk3ESqCpFeaeTix~|EFI!^pk6F8ZVA6Z};JR zl%w2>-4~M%AK_XT`gFLt6$ilxwi&8!9;(tBkMP%{f<*JY3B;fKwQLZg^(LC}1ZQYD zcr0flhy{oJh9BV@+BYOXLBY)LhuPQ#QxF)mY5@S?fui*VRhXBUcF>L?oA6$|LmCFO zj21bmkrpnPXkkPDmQ5)ll?x>*@u<+|tc2NxUA*N{p#k`cHGAu~5c>+HuNP%e7fL}; zz+w^T<86=41T^B^FToqbwq?k>zsq8|VcSY?@B~q*8nHMUVa^HBZa)!L=&mIwot_hd-M&hO z(d0h};xhRM6H+z1{lS2M;U)1R@xn4D{|Per?}(8oj^SlHUbewSP5w(mF26HwBqo0f zs>z@7mdSq^s_x=cm7Eyty&V9{0sx$s3tm)x_x~4tm;~^CH z&ARM@XrUpqu3@yKFw4%mtuR$iIyvj^4(sfSp()*3LdBq*38<=B*X+V@)>SQQ;{fbR zXE7GdbRWm8yD~M#p}s`5ie}wm?7op&lKM8I1bi<_g!+VHvZ2gFmtX04mj&E&6%Il>^338<{& zhjT9T6(h|z$6;f?Sj zZpJd^h-orM><8H5KD_M3%T!#{9I*-H@(1EZVveAonjOoG`*c{;i*bD&R zym|1lCE<(>B56f=d&qPYgT`$|(ZmLk&C}CJ$xWX##@5hpJ%Dg1Y=Z*)UC>e7j@ZUP zM;k=LhD=r4Q#w7+!Bk~7n})|w+&5L3O_r(3Fj`WWWv8kgV5*#Sa;iEs?2;W*x|sqk z5wQm4Oh9EL*0w=3yD*%pRLjP401ieo&8doB?3k){rbavJOH`|9s@k317n2UBs>7g9 zha0ar#HK1$H-W0O#;NLXDo8X>q>3?Fh49JA%5WC(&^@4vjoS=j6$G)wbinCqChx_G zV!Ap)gMTQFT6NfESTPZz1gbd})LdX$(@C{w&B(R7tSDF_N!OqKQ(0^ZU} z+?+<%hToN+u8t0ywO2|vlh6Kh&L2)!;ot<*m1@L3>{TO+MblNHC(&K|QaYW*g6T?i zV>Dgu2XUFMf)rZKbafygVE6#Mh?}vD>FNNPu1>&66p!QO7+lm$br3}IC*ww9rlO#l zsVHxmsSc*S?|9%tYOv*dm_kssu9Pc5m?H}IH66)vHy%wijrWu_l~D@I$VP!s2UU{ z!4qhUZ|a;RJy=Z=JOvP-c@kd4t5`-7JXDh4d4MgR!^>H?s3dqQMDiEnMj{DPP&o$W zElKb+s$N7@!^a60`M7*tlXNPGolXs-{~|9ZJu}^%0qGL)!!=U4>bV4Wg65r>f{Q-c zoQ6A#aH=VejF!w%muXvPr?hKvXM;v2pt4yide1ug(tva7g?#Xyb+n9y&zxHu_n^Ow zH+|0oB0h{MV+#Z4v)I&nDTlfcIoAcao&Rx*;GN((_;7vbiukU?sim}gU6|roeua3s zcCU+4+L^o}kuCpW_qw=V$cK+agafIv(j~Rgw|Lm4K!k_M@WR6`W3j0q9){xOEHcqw zz~Qgz-TSKn0i-MOB8i@5B>JNy(O(1D;#Is{fs0D?*FYqHJ#HitJq1;wr@ST6UrW^+ zsA?p7f;kfXjnr@?deSo!{Y{WA5#LPoH{njuyqi;SQKC=7-9k9klnN95E!x(tDeYP! z(V&qDsH#MNTfLCCB>LNH<8BGVJAjBVl(9v$lvr$Py_rK@h@9(A+%^+^=!%l))9!Uw zif8#mf2(${yHnbkydsh4|6%vKr(Vd1i9Q@imFVxSjlRXh?gJt`OokU8c0Y?v1@SNx zA7GJ*{yGkSRf+x)Kmh3>yhx&F8HxTxN%VIDws;3Gx8b4^{i6`c--8>8L{CAL=qYbW z^p8>XUZ-m8Si=GEI05eS0yGBi@;U&X007$i6mg9CBRUshtIhf2X-cOzTEV%9X^7_{ z&rsZVF2c@BoQoJnOA6C5xnNHhe*W-Tm?|fo+;cn#>+FN)Qo6Nd3WIVcpt2JYgDv^_ zL$eDJfc*TSYT1h%0AqBcZJ^Q7a@g@wx#6P2&YIzRIo0LmQ~N{VaJ`b!&D6_@#Qt9# zuHf^8=3|6r7ly;7TJ{df4 z9iru)zNPfIzd>o^Es78k?*>fEKkCtZlje;cEI*8oX_jxLwEv$DB!7nMV*Opu-wt4I zd%Ir9^H;+D(^WZ%a-4TSAM>dU23qqji%kXbAQaz6(e$6__$}=}A5c0yD+I@H$~&Ut zw-0HHll9&7gsLX%PXGa$ALB**on=hcU&>_tG+>KQ^71$?YO?+mBKhZVBQaT1P)*j9 zw@lVwQ#BqR`Tm#kQS~*3HMF?@{d471dA`gz<*d|kUdN1s4B>Q0R)hK#)||Q%LuX`B*R0~wKAN;^}OCRRcQjZ8op!aX`FZ>$&c;TAV^4|%gs z?Q@%IYl9_>n}LWhmNABZbYPKT{BI6=Rbku-5I~v@FXA*TBaDBOF#Zg%#ZP$o2p1K` zvqL2RC2sh_m|7}~sq78o&O|ic4<$U*V>?}PiA5SXcY#((VOJO(Ujrp*XxEf>CZ|qB zhe0C~P*u^A@ny;|q>@RpBugAb>O{UL-tN zMtJ1p*Uf(bZ1Fo@zQIL>M=yxvf5Hu4cu-4)2bI0yF*guPL<}RMp-;bA z{5!4LaBn%y1*w^XSi)vwS4u-MT9--x>Nn@_Cu&kmXHdLFIi_0&M z0uqZ-m-ezvOe}Jfs_pNh=h~!kQv88MF~Y1uh=KxGktXK=Kz>2}(e|~u)8G&(FW^Xr zf8*;dgYTGcq2k)Xr`o4Bw7*Fm;-ES_N;qULuY2@q=>_p%Fj@gt;$ZT*6}MErA3Mc8-mZL&d(b0#9^scwk*g>pbYo2aJOY4F{@Bk^P;%hA}C<7 zdeD{y1T^Bkh8NaJ4uB&Bun+)B7vbibxT&MH!uf4s-HB_Zv@=ahiTO$0w?Ajt!D8=z>0 zyUtt<(@HvX;Z1@*00>r!iJ%3_hCs>ce0{a^ZIsf^xzrBQNj1+^Zw&|_ZG{(^ zzgfmoySFU07e!Ji_UC00T+~u~n?PkdyyO?deXap|7;ERmT9XKB^+lj)4UP<^&Y$JG z#Ce3gJ#mebD;iPyq!e4|Kz;|vmlSM;Q|;nF3EI13O1qY9XVAz5RMk|wQ@xN6<0BkM z6(3`3qi>0ioq>q>kl}@E?7|}BV<5-7s;%g5fB@1syhwbojQHpy@v#(Oi$z|Rz(vK! z?t#h#yyTa`ea1&$UwjZj`8R?5@iCFOMtsnS(kCS|J|;oFq+lzIkL7?8w0F;xb|$w@ z%pV4gOh8q|$K-k;AI3*GkSac=)JESDA5(#d_>kd+S5IS+@v$_=yQ=uu2M|Eo8!r+c zEF(Vh5+6eVTU?Qs<#AE*u`fjOE8&JOCa9%+n#$IgP^T#S0kK3xXarm9mX%Q=vHfYx z*g%JJ@~F))NCm5CQjNt;>nhYQD3k-eD8pSS1wjFegGf*{qrwiWli7mf?Cu zalJJGTU>*e)o@X+cQ{1M6Zie~7g|vx<^e#SL21v^l!;{yttpqKQNv|%m?o!ehLw^M zbGQUtGkn_e2v8{}O_2DnJ&Xj0pl6PRHrjJE+p`Yt=C45?;fFZ-Hnbmu_w-HRrJ911 z%7N1ly`U?9W1PIrV@O3C{BR5@?NYbAEm7Zgd0eVBnfx%}(1z(uKnaKToo__nl6ri- zkPjvm-yv{0k5#dIV!bpu_-54-eH@Of-0kGr=v(H|(^7~=)EJ-1I|H&vd=iZa!ZT4c zQ_z(qH3=EXL7oski^@!sYcrUuN|WaS0(Q^Ai=;`GktSD=G`SIAiyQE=9xtPCQMvMh zK<^^FC_5o>bjsXp|}$X%Y z%RjHbr4Fy#Q`(uL;(r@nchn2{FucOiR^fGLz0kLZ*WIXAEGA+wrmuFI(ZF z);v!HdQagcKNk0WYaS}A>_80Hn&)YP?MyKHnum524ymQrJkJne7aKzGOQ7Wuo+rXi zL`bZ86!A*eJW4*c=25pQTJyX_B91i=hs0d-yiDmtQf5!8?lLq=6%pZ@=M}(~lTNOA zc7@r%mtIY2*OHVC(wTs&TJyYCFXY3d9FDe1%Kxet`e9OL$i>z?Z`4NLl9b;BB9gLr zCp`Nt6wUC8);vbA$eQPEN+-gLX{N^TdMDM&@@t-PI=tRZX=jRx#G2g?t!Z z;b^Py`k-Fu+r#Ul+UQ%t>ti4yyu>>ZUZ0?7hF7%aNr%_xDLU>o&zCgBHP4O=gsRp& z-v9y}zs8HKd057pXN0VICIYrNo|oNlQOlk00+k=|lHU{eldA*Da#>U9>OjfIRtM@< zMXQ5fNyM=_U<=IE!Ecl{)0c0(#@4IMrdWZfe%4hEpbRS|CFUj16~*tMQcgO#qL>Um z!ASj)(yk@t8Kg4-Rkfn{vtGytDX$g}QEBq;dTDZ)CK=kXRYz98xm}jdO^0fzZ;3q1iXRnur+e5lbZS*ZGpRPbeNQ+-1q`RS5c}UMe=~)}n;dd)l z8PeTT{Zl@qr|OXIk44>F9jI2s2rDk518XpHFN`Lp-0@pCMG$`NS50 z0LRVoBIgq<<9uSYoKGAM*y5qQ9D<8FpV%r;*#G zN%`=4p&uq?hFmNuA5j~9OH!T*L?mVLPI&f_D4OB*=SLTJxL@2yi?LFS6!g8Ec-MWX*FPV2kJQauzOX zxpQuyaz0-27vg?$bwJrHTSFxuTOFud6|D{~B@xH!fGsdr2bWRWOkckB8e6Y2n_?AT zugP<`hLw^M^OEO^;&MrphrI9i1m0Vb=E8z?>N!Z`NUwPCAVcp?>q z&*9#f>YwuKmy2~U-;~nM6oZNN%Rd~-yGuX}CS4Z?BEMC8X~FB0^gH z8X;XmvGS0U*k(rE^6m%JQRgcp;@Hfv z1?FbvRZ3T$GTC~ynNh4#n;FAONr`#Mb2IZAsFagVZf33ppJ1e3PifbZEDh3`fU4Te z{HtEbmrs`EJVb3~-l&%*hiQ_b9ox*jRU3UvntU6GNR#5xh=zAiG{ZRB%oqVCY4Tl4 z&$=*vS-`pVH10gNe<|KOD>-)C>9AgW257d{i$Dw}UA^kZRfKkp8YV`j(LX9*78O@oR+i4=7e1(mzsq)`oQW9B!2%{hw6-ln?0}bV&b{ z(ypVB{<&Vr&zg{qp2PjMUK(x>>ECOkZwcu?fQXP5zeY&^iJ}?O(fNcCX0q^Z=#t#D zy3Z#XAuHz-S2KjFI-lqW2ykr1i=0oejPr@9az1f8V2ii%ax*VC;-U^IIt6;2@shs_ z_kC|zQd#ZsiQ#&{tP8>JCYb#JGulx&q?UfbtSb@ju^|Ls^jIFDI}z?ALgE24MO;oD zj3KcC!IV& zxff;wUz$6mT}wJQNM`~HLNw!(!t>M%`5>LE(N?D+z3YX3n3NfEvD1+GYol*T$_oGy zNm;xTp1mN7W_U%XAx5xBQeKGCiSS~YsWH43PPMZ9YUw^5UVT#9nW7?brtuGlSKoRe zABI;r+A6&I)eC)lcnzqHz9qaC1tP*ryc6M-N6`$gXw8!juR@BBF~J%Sm@Pp=d{3st zK&WcXvlJk}v4|I0^RSFH&;GLJc^I(82YI<47q#43I#5{_FZsuCKe;-fY?k+AlzeP; zpl(&PIv7GCj@1EMV6F~YDQ%`N-+GO$SD8(*O1&pzSScwnFL|yghJs2t>Ew#yaqtO7 zYNeEREh*0+oe8L_6-8UUkT1VMEaxFAO|DWeO%Br}Lp!z#8D1NGOPX92h)9#-(TIlC zP&C6hT7?(^CaaLuDLw1Lm}l+b0j^=ITzE$B$*hs;pYrRMCv-56NNHz^!NmII9}ea< z>xF#n!5sLB3hA}$rQ!CF9$6cGOGu9bB0^gH8X>(dij{}-dX%2EA>AB&mafW>UO&}8 zO9nu@5wCgCOH>?-(vnHgQ^%p5@TrUl`hx8`3(YJ*3ra(kUi(ez8H$%}3>1Z=! zgqh6JTc+r^H#1w)5H~ZAGK8wy%xn(`aNHIzvYBBSo0;jdnRyPd#bhb zdM1jMhxCz@p0y#}F*u*7GNg}6^-uYbepQF`(JAdZ3h86&h5W1u>5lq*;<$QgxILs# zsExiQq)!AQLR$P9A$<~xW=Kcp6GoWH!u!+|9ryXf=`_Uii5D0`Rh>_q1qg6F6EAW; z!7|P#j+FC>Hvn7w7cZ~jqRuDI2~^I*Oa5)#Po7UuHp}^hl8>EFs9WAGzB-?{ghU+Y z6KsKbK5;3fD^Hnhy*i&ztWxI_hLw^M^OEQJ#ATpTPC9u$@ecR|BXxO7yOv~Wkj?}Y z1VF~ex2~uc^5v6dIS*0i6IazslfyL0(2ku?TvHo;OPahEh)9#-(TIlYP&C6h`XLG< zz$8sxPw80~#>Dy|fZwcw!fryY6zeY&kfnwz$U83}?4e9WFqRNoIGu1!kL;5`((s!k_>nNn} zt{3vNCZwbDiF@m%;r5Wezc%`okbVG&2x;+ag!F?bnjsy1YrPR>GD|;_qT}AoJVry@ z%)G@As%kUyBp|@?3B1T=hGlGKPLR#a$AB$<$jkeHZw+mNt%3z(z7m%W1AVnR=MzuHZ$+0`ltNL=L;Ro@1?Xe#b9DH^A88} z`}IP;_Fy(QGauGV!|fscac%T1A^iyu5z^w<22NbsWk`RX>Ywr< z{iP1+FH+id6w+VT3;9_S($Qw->w0OpJ*2;_jlLzMzXKvdTKpOz{XL46hx8AWp0yzz zzS&x3NdK7XpYkF7l@96uq_pcOq<^Xx^0OwSqc>ZBsh5V^L;APc=vzYicOW99#jg?4 zf1qfFbaXypgqbY7|4z|ypHJkv!Vu3VK4l11bw1Gy2ykq|i=0oejPr?pTaGAx3((@% zxTu4P4yY^fhCY2LAKX8XnILyeX=e)V?FY^{^uT9Pv&9aI zomga-d{4twbx9XM0I4%xggDFSl7Z-wp8#6?5f{}ZT~Sx!jSOA#E13y$x0H6KF4-Dg z@?+N$N#TQeY9BlYK+z#$1Pozkp+o*AGePc^($3T&iEWxeBNI>%)EVDEp1WSi2NOVvV;A$Ad1|9?$%FF(5uPZ+ z3;*fOB0cdhj(1g_xBwu4G(TR%Us#4GE(K3)xG!?T1#!E?8yTFi3E~0hLMiP`zO(tj z>4)CXl^fX{PEZFkM=cCQbcC2du@8&vh(_A1sw4UV0!WMCMLL3Ibi{J#h>id)Hshi~ zvOnrdypf?dW+yX29+1+`)EkMAG-zZ3$`F#PAr<~8lf$C*LOu*hj@^vm4;NG}&)3G^ z5|aag2v?Nxg##_dB3-c)2R!DAO}UeM_i4!Gy5+hx&enKJ@9ox~GWQju zjUc&|w!FE=@}_S1(O&qSHT;eq_%Wz+G;BM!^@|-`>@~c^V;q+5Oj>lQ>b#J*e6is?1~pqY3Yg=aof`sZ)i%dyY0T}v-_sq?puDl zpJ}@vL(tI`AEL_974M_U*%hCo($W=Q;I^kLe$v~Ur&RNGzE<{;o7Kk zG&C`B6HR9oKIV|hb2{Q6$_F&chb5B%1sb2MyAx8=>fmd9z!J9{ke z55x4r5oLLulL!#)o%ATzuo(_-FqPD=!&~gW$g-1 z#t+!-KIpgmgtq&r5By0x_)~uHS2XyG5Og%^d7s@^?RH=D+kIQxeZvR-jvf46KX`rt zwQTCYfZA|RTkX{m14$^~AweFaG?2H#jrLRSc>3U0x zRzRhzMXTx-tpX`mi`r17%`(u20cMZ*Q%+Z3#ISx6M(P;?^YNys3sy z^lJZHZnUn8ncfozXflb8)24U!nBEC>j)C3*RVh}%N!#|?a)MQR;GNs*`WQ3iox7pZ zHI`E~={+Ik>aRUe=U_HLTedUXUDv0WVYm*_<`43iKLB-(KHCpf4rcpk%XVga>3SQp zqcyXckaKm+4AeQ89fm3gv*}*Tr)bM3dMqFBhCkK|e}RTS*8_jH8~#iUZ|~RBb-k@$ zuhr(S@|eE@b&h_$3{{SPy+m8KGrLIFrIlD?;7J5$T=AP^|M*OWJbpo7=O+OEATH`MhOUR$8j!fQ+1_VC(O^BN05M_2BM zDhK5;sPc8?cDmj|c^oP&ly}2z59Mi^@?;1)cumrF?Oi!h*IRh)g-Q#ry>Z*a>u}9$ zIs_eE*^Vj)<%3Y=>&gRky@m1&R9Yw>f!iL+Cuz#ZL(swNSZ&wdl}GD(3$K$=Y2kGW zZhLrLq^}v)0D4)V2W3;rMybpO>`x; zlvn7w7^h%MnQOcrl@?An;I@a;{hHG~5Oj3oU8qXY4fdKPR5^F&x1-Y6$G7VGSbNk) z^Z`^_+Vdc8d)o7yZqL&YbdY`$RZh~6qtZwEQC)8#{X8lyq+h^o59v2F>DM9X7=%|* zWo-|am~YzczU8<3p|<;;5BwuL_{V~_ER+x=DB{mBRZn;raj zKlnTgsg>be3mHRdoX_<{ouk3sQDq%PJj{iv!0}>^#VC^lqdwa5f*#BB+u(!5(%S~l zDuG{I!w>YpFN!)x!}{AS2RUL9n`PawWwqtO9?MI*;Rku)hiUjW5ByNnIT|*^ZFxm) zIgzWwgSO>$y=_ECX=ZCfE|wk)Us@A&4rXhh%Hd0^Y0GwI!*#ul*=WsdL!0#ua`w5t z+xoh0^jza6sI;WWO>sNc2gxnjcAC=GZo6Ch>~3$jJH~H!g0{OG1RVphE2txt2gUuo@JDF)!#wcQy%;BGjAK0*N2AU` z@klTHX&U}y5B!N)xBIHL z`w|2lUGV~{99{7os+?W%8Y(Sa@j7mMy5c=e>20^&H+^>Bx7+=|Z}%&0_j3q3y5dt* zS-XM<8eiM(e&e_MleYVV5Bz64_%D9&#=dH$@izn=jr!APx2dmn5Sww^Gl*TZ-A)j6 z_E=XtcsD=zyc)b01Raf<(`UE0-R^vTyM49Yg?!+P*unex!G~(_7E{n%6Qa)1;N?(d z?dV)?8B{ruY%5M0TyzuL3_>ms?wNdA2*qUz3Yj`bhsx5EqvAm%hetj?e zb{c+b5B!#>b2Myomt|Qxjn(iwc;L79VocN+yL&Lkq0T{Z7ccx&4Zo)ceh)9kff{2! zH;sK<5V_o5sB-vruJIsLT4tbwaodx;W@<`@yX_w8vwNi7?oocbr)j$xZnXSaL3 z-|lVN?#({%+wI_Y_`x64;P*k$(WrZTb|13aeb{gJDQ)+0ANbRD@Mrwsb1kA)7(Es- zT*;WX=0KgJ!Cg^h9mQO(Gpc+?MxAth>}X~!9D~pSdZ9Au@amD}g*E8~AQkg}gY&8_QG%rN5?wE4Wp`~bK4ej46xzOSxNna?#Yj!IX@EU%d@11VR>3`U(} zG?zq`qt6DRDs`+Jj28N2Wo>z=$MO(2{EA-qQ5t@25B!>_b2MxXx8>EeW&3Ch*Y%ds zSQnM9(b!Cr9t|niXl#T!N0)D)E!&x`r|VP9FeE!^^J6^bw?mzy&$dC8gV|QvvYpu$ zx<17$*EklHu0GpClO7K#SD)>MItQ~|wPicAoppVR8T#xXZGL}``F&C6=(D|1CY>`HC< zGLPj;-05Dt9*k>I=U{)e8$Q=~Gb&x|@6?uW_gKEw4G;E@X^e+G7!RV(!Tx?1 zd@gq{s(c=Mx2{ilMXvF2RJt1eq9*+uq+Aa34C<_2k;^@$E!+L|30S0Vz>LL-)=)cwWj?Of{w2E z9aWBj_!U(?7x`J&rv?IFe9+I@RgJjq>8fs;a%TuScy&URk5@-sZ{aluDlJ3U9k)Ha z7Sg=thoGY?d!x!hc^*{xDEHF!7Rn2w(n7fpZhI&%t|M9*Rl}<&|*TLwQY2d36Xnc&)1K+PiX? zuD9@73zZgLYvZ-2X*TJZ?@M_0x53dt6uVW$T z=*pu}<)C~ds+=psBT(t<=ficqr9CI2($b!jaNETq z3+W3`X(4?fZhJ^ytw~=2LB}9mhAL}&xX!)CZueTh-CMNX8-3un+QD!0gWs>g?}4DB zQFr<5K47=|px^Ej+U}!1@F(ryPx-+=(%|o#g2sv1yQp(C_-#~KM=_Us6IFrZ#T<)I zE6MvDUu(->cr1VBhX2G1|Eq@o$pil*>KqOG-fj6?ujR)6Y8Cmn$MTh&wCD+&$m6mYthTEQSpGQ-g%Wb!(&+fc-yS@E(2WY#CK+rLceNg4- ziiJ?+?21KEY3YhQZhN|7DNSjR+wS5%yMyg^m-gFTS=${7K}S~%L6xH`Rz#I=l2~5X zr(!wRxC$yQT{R51JzX_YQ(g;#4qhX)UHb}RbzN`aH42p$UhCqvhu2n`*X9s(bmgX~ za!?+PDqmM_r0Xq|w??If@;12bp}ec6JQjiuUOQ^L_O2YG>n*&-q0+)@H{AB{y06fu zp()qY_-J8aeBo|W(__JF-Ez6y-37d-xyQ80JC5CW+COA)UBx-Xx|U1HTIb_ zdAq&FjE{XKXSZflH|Lrka#VL<wZyM+otDcTgWDTSjq_`g@7L+p1R7@u3bjv# znCY_pxg0)If$pR#d1jVt=nv&{q1*rp7Yc=@ri(O{v#2$8!XA_NjkP^6n`=BzK?={{ z>t?6XvjN%Z;#`C3m=5^6Vbd|=r^TWWoFLULCe_&~)hi~|lT!OcUqOXY?#^55#kxwM zd&iXKrbIv>>QIqdFeWu$B&EOMDxldnCbdu`mB1PhlUgK_N?`)RfKeQR8a37{P|DiXZJ|_C({TJ1Wb;+Szeu$; z(u{Xmu5o2nB&jmHuEL77#>ELWGjk5({ZV_w?t|nA+*Bl2qkz>R*NI838A-)QXST+X zs91N8ot9m3)p1id*kj5#P7)0>IySVQ($LV*+|WKpPnd@c<6wgr;JS7|NR5t3Z5T<# z`(d`mO;7=|E39bP?184hW_Q@!6auulWejaII~t_6jY(}4NyVF*Yut_%dzn4CV@z@T zNHI<}*SJ%lh?`NG85dLBIZ}*U1g{A(sof%}I6S2Gj7d$5q!L)uVp5YMsRY*kp;S}j z0r*RTt?@wo#bBdn?nBL0jhwR=Zw-&#>efh)JczeP^LEtg>A0sH?_fb1H+71knQNR8 z>dhm1hcvV|wD-h-qMb*@w2#o*@n+^4j|;SCP`kN7wC4)6Pl{$oHD0~G-1a30)O?A zzrMs@b4kO#)_;Ag|N374^<(%KoA?p_HqE{+W@WwfD=LGX#c%j4F#J3I3Jm{=zXHR5 z;jh5(-}`eOtG&`abbsIA*Pt8%-Rzs z#K3d80lc~K|FQSofmKw?|GRr{3hgQ=h$xzJ6Nn0?&@H6*MiRh+UPBTf8j_d-D3KQx z5D^ftAfTcmh=?fmhM=Hg#e!H+5xb(;yXfyT=j_hb%X{DV{r>smJ(iDi&dixJXU?3u zd#BhOLAD5b{U8hX36zntamNw8B*l_tuy>YWmMm$M#jb-8Gs==@c$hq=i#+6(SwN!q zXxWT%4CKqz5jDsuz^?LCEuF{}O>MgUxl@fMdevEGm%_|h^<|p5Q!PoVFGFUx5@EGM zP^DWH14%tgbVNGk5f@h1HdCrv5s_UwLEac798cX$tFTBZrR?KuGLUzi$SX(4O3xf; zS#pf`%yF*BLFI*jNPp7$Y|87=ay25i%yS;)ap^Q!PF&mx*FbcB(g))9iSNz`gSii z6t~HeXQRkdJ442N4vnh1ff6dqEaL!0RaITD3r!J0g9HCMB9}GSSn|u^Sk>;Mr25v% z_KC`6H2$OMlw_#!FzAM=4^W)NPhK0nngMpd5?bWdBnOi3QLcpY@Z7CR|VMoF57Ep}V7y%9d! zyOwNkh0peZCEFg#=5PXG{*Nu0KBP=&N6!fYTJ$SR-p?tohjBg?bWh{#rz8*Kd}k5+ z4duxw8R}u2pDfwF51;K1OSWGrn|->Xsy`F4tT}6{mLR(`t z=Re`IMeEso{=AU={&Z$^C>9mS|GqoW!1V{{CoV+|D1 zUq=*gB7l{ghBoX(U`@$CPuGr(L2M6EqDQq=tsA9~HO-YOPVR`9c~M(kX}g%X@p#mQ z5-eusgszkTqmHnQRbmA|s{pJ6dPIo1b`aT&E)%P>I7X#`M9wWA+bFhDEDPE9DU@j^ zP%^fV&9D@sYDq+_q?I2BD^O1)YDsltTYYP5wIu~@9eD@oK_f>Lkeq}^1IbBv7a%$H z?#ieeqwb7)FbXg_jM3qYdNS(8=m;qP^vMk|xuQ|;>28pst z#{$VJ^#_twIu1xyDTYxTqadS1Mgtk0!004KgBc|=N@X;J(J)3M7>#0dDv(jRzQAEC zmySePxeOp#xlABgxhx=Axg17$j0%8^LQVr#ra6{6!ZS;dB1u z3`Q3->R>dB(WN>f?;8)SUhlZ>`7+6rX2+uu|VxTZeruo(!n!Izg_r(bf`eieK1XzCiieVV=$Ov^mq^{G>ZAOhk@iE{|KW;bwm}o4_Ik!t8Qy=wRM_%iC$7*DRq!2 zl@|UFQCf9PO5I{-Hg`v>i-)o@p;I?M0@&#I%>0_6pN>GVN8Sy~ecHnf38U4cOS0HJt-B)_;~B*=if5F-XaJ)mMkg{F#OP#3DU8w>4P`W( z(MU$8FglIVXhs=~vKZws%41Z(sEAPsqcTQg7*#SF%V<2KGZ~%D=p05NM%9dJ7}YVF z%&4Bx1&pRLYGQODqZUT3K+-4MnAXl{8l&lqW-z*l(Z!5rGU{M-38Ptz{>7-1(WQ(o zV{|#A*^K5gx`NR>MprVL&*&;f3m7eAw20Bwj21Im!e}X@YZzV2=sHH%Gg`*z21d&n ztzfj0(T$95Vsta3Rg7+7bStCV7_DY>JEJv>)-t+-(K<$VGFs2*E=C&|-OXqtqkDj) zH{Hv$O^ohibU&j97(K-3VMdQIdX&-Qj5afRlF=4MTNypY=xIjV7(K)2IYv7ey};-t zMz1h>mC@^rb}`z`=xs*tFnSkA+G-Ee-edGWqYoJEW%MDVeT+V0^f9AP7=6m%s(Tut<>dL4aqwb7)FbXg_oKa6ky%-(A=txGr8TDaw6r;Y3 zj%L)4(J_pUWz?V1ag2@!lAajDv{*)QjN%yu86_}EWHf-$Kt@T7PGEE*qmvj7Vl)^`-sPGNK^qth6j&S*5FbVeDBG8ttt%4U?qD3?(l zqkKjMj0zbQF)C(M!l;x{8KZJWV;EI1s$^8fXe^^~jK(uMgVC9c&SG>nqX~@8VRSB# zw0MYV=P{~gG?7saqgqCFj3zOf%xDUudPe6nx&TOO(7?2*j2am=F=}RXA)^*Xt&G|j zwKJN=XgZ@A2GTA9lFQVK8O>zWp(9$bK8jhtQc_`EnLdP-sj5Cq31yZA>rz2}P~^8} zmkZe_?FpomH5W8a!tFa;h}(XmxSY29NJZI<6u+uHO{}zAonqU2-foaB)F^E$s2QzO zad#GrVu<^xn-I4G;+{g18l^pne`I+$HmT)SH9xUZ?u2EG z?dnT_X}_gZ+$QA1!6@x=B!CX>^plg>C_P;h`mKb1vyrYvX_w+3YYjFiv}2={2glNrANNx;$10npf>9)+C`QqYx-ja>s2ij1jCwE%FglFU;f#7R z>c!{?Mn^L0&8QEfqZsuCk`_OjY5f=-!{}H>{TUs{=y*mkjA9wZF^XptWR$=tkAOGu!RR8`-mg!;zT#!z+ZR7+~J zIN057q*_vj2)T&qnKsd&MKl13h!rsvNF1m~Gy;i; z71?T}Mz$HLk?lsRZ#t0N44%R0A_Ms^X4JuG7Nbr^mob{nXbzBQSN|12vgPI(G~aw9 zU&K{LYQzGjEo8Ka(bbF=8_2%|NS3jb(KQD0U2EivxDH5Y5OF=zmNB}4(Q-yB4CG%4 zB+Iyw(M^nQHjr->khJ72jBXXF@M!;PBcK0v1Nqi)zO|fh9jC76)VmmM;Cvg6eExe3 zhGkSzmA7k3%jGo}sCks z@@+Hn`L;89hS9SI@;?V8Bf<^?`JU(07X%G&KB4#L0V`szY|g0Y-6~bhp%nKdB#X!% zlMq!a77Wcb`b8MNp;1EgHrq=(s#Yk($mza*#wDivS{WrYw@<{p$SJ6ll5DTq$on05 z-DWH$Ww*9bFw(_6L&3;@hA5{j&6O}tCSVER;HaX6Cc1KDUO)Gbm$@;2x8=s=68S%< za1LehQsLZiB~9=uDfDkj!h4x06Mxl+I?C!kuM_F2e^OXMkzf}uDP2HWtOiy6=MyQj zy0s2dN1FxeDPepI-cFoYU2}nXsU;cOL<%dw22G;OiY$wn#*1cX7A3V-wl%fXS$I|d zg_K|~i>lT_!;u z)32HK4Wk1o@og+Ab-?*$f!y-=q{r>ymq-g?Ceu+j+tC7NyubAhq^8f&oYJbUbbL zP2K(UPJx#H3;E>YQhUs3WgjCyqbMDbb^ajP?pXJmAUErG(fIc2FGTh<&p(vnypyPE ze+xO2CW$4W#c&6OpfYC+5|brb%?6;NJnlb|)$YxxkEH_LfjuhFRghg3h$gaU1$t2m zy&oa2=E@fC6pK==r(kkNQtdFA;H-tJ9WE1GL6fT1A8E3c;(^F>sU40X4tF~oEy%8F z97SZ$Y8)q0T!vM(<7I-UN+%#qT6;K<3=bm=)@6`L@v!?~N@#7L*w#{A(^iMOC5C5-SDSDPQ8K#Qv%1lg|7 z8AS8cCnQo_`iNpDBTW|D3?xkByO2=}qgDfHZ8{=z)d72`S0l)-{#Z?9PYutfltZ}c z6v64LfvVNZ1h++1Ujro}qSD@{bv(c-6E1NHQf0lb0Fo{-&p^H_4dkD1Anhtf3k1?| zH*%pt^DQ!vw!}cbrHro85!q}eu#(X*z51foa(u9%4Jszvu3%k68Qg6?U6Ac<-cB@6 zi(XDC?%J!`rIgT0HC*2qd#)f;&+BOD4FjFC&7!>v$t_NmJhpWO()p;ysiZ zZlDZqGh8pob~9W{G*2_!BvM?CBV1q&(xhG+fTZi+Z6IwUqk9|NDkuIa*<3Q5&pJ23EM^wiLfj#PY zzaYEnxQWP~b$mpmh_=+B`{QPi>wN zDISJey9WS5#di0rB6PLbj^+N(qtMl;6q zHaQ_weXmoJxNoV?y`lIAph++P3`i>eIioKaeJKzHwXY1CZ$G224dnlZ(E$T#-|C2} z{~qum`}Mn&!QG5+3$n{TyNT>+pS_gg)p0(eghO`$_3q0q5NmI}oINrmDWCF+P2>IdwhP+viIDb$C^o(jcM%Jll$wkhUN zjMegSL`EkzcbByOLWWayRf{2dL+eBfzZlsDfiCNk0z`Eoy-%dv?v9rv$S%DH5ZP1j z!IYxESD|m>iBd;^PNh;=!-P;;@yjj#PI-zrM37x&r4re*tdW#rFAHsz0jjKD9*}IS zd;|Fk7!@)qF_2bjAYU1yaz>RpqB@KQ_ORD!g6yipDMa?HLnft&?-j}K1?VFqj;MNP0DDw#oFKcZ zS4Cvc>YYs~9)tK~&}Ac?4VQ3Tsu5(DPSr&A)M*N(c<9syy3olt z14w?4GiJIzBDY4-U*((G61h!mbnBE0U=%%%i)c(_cET{YMyX<#6kv%K0fl>-`8>%N;7t^YCmlWiv0^U&~ zy5p-m6s^cbpFo;8r}aMvBwhpa?*I~e@BZhR_JTq4y(nmO$K)lZz09;%44SqRNLa)7 zsz5jwjCc)5?v=m6=uJj%F?xs59!Bpo+G`-+KA__ilKhcDi}-}mXNedTv)XlOCm#aTb^cMSZn6{0GxpjEIuBA@C z_)d`>eO8I5!Teb%%Xx(9+fMY#Gb?RNV*TtwhAKVO%VR|u_60`2N`jq4zw)I3iB~>- zsX+2ft34Te%!a^bLOnqbf$@7@fiBEJhP_M6EIa*rQbv1liRp@kI7)l@ll> zv%2vD+OD!Ot)43G_32v(^l?&EJBd;%ESWWJupr?+B=X~f1LAlPc1Lcd^99^8 zjMlW1^(+Ooh-M-~C(1fkU^G=n zWT}b39+o;!kX@EKm&l%$s-qP7#=RU)I>j6J2(aR&UmKF8lGA}mNh-XBnA}5rvmm<) zZzQs3;q8>-DjXg-3kkB=e*wuz+^Hi{po19Q3S2D6E(K-~*+T&_h+Kh0S=3cPvZw`& z7V3x!odfJq=;ea!D)dq!dlaf_^C-nJ0jCZ~H!H72n$+e7Aj95EiNjsp#e(cAc@dF4 zOTLa$>fQTft3a2ft_Ctny@_(WOI<0*u2Pp1*|XGJD8-}H^`OgA?*)yA<0&WKYF*Qi_MI-v(Wl`W}!`>Tb&IHpebOc9r@%kv&V@Ln-!B zRqY)jdaU9;23@G)`x;2jjlThsbK?U*Vs7mJ4oEnK|9c%#!|nt2PH zMJf2qt!0EzwNFHL=gi>?qGmNU)?y}*Y|Fo&QtZpVFNuVeh3&h0s`eR?bL(4L+iD=l zB7}TH^?ysrRhBISbdNtkle+?c1Ih034PV=ccBJ2D{a@-C2iy+%iU49~(r)mBa zDXwilRXa!tm~lD3-t(7aaPLrxP~R2$$$A`a=&bc*)XPA=BXmUdhz3?FUEMd5$nNU- z1=(IbjcA_L>p>~-OUKEgss$*)>BZfI91ml3mkD7i-4ChcDWft2 z`N|oMF_2cpXskpy*%@cheB%w|KZDVkjLu?owt=(>IwF6}0zTv!PX=XhJM3sdcA57y zB72&*fKuG|rSgRw_u!c;1bG-fPbRnxkKkzxt98gD2e=D>WCJuXn#!n=Q4^zPiD2Rj z4VtgTKw7Jg$aFQphcsO^WpJA=B*-q)okL_#)74Xo+jLWe9JlEv2|*sFn=BLDri0IR zAWi!0WkAwomou8pXbz*fjILlbPa+uaN`vN`Zy@a|9g*=a20o5yV@umr~%Xn=> z_B386rMQjvFCoWmyi0^2597^}32x(&-@$-OkuH618IUyK4F>Wp*AZ2HF|bF?774Pe zW($byS+naX#W_S>BeHwwf2~Y#>kr*;L7LS4b|9(y8Uy*(GP*-YREwK|J!)~IAiHX@ zg2#dYhImLNS zwM8&^+!op_6Wq6jo|Fl0XA%wb3Q}bi-vFX2QYBs@9(RX+L6BXQ*g<5^O6(LVLXd4) z1&??aNwVM%fuwEsG5SPDq|DpE9?I+%WS26#i0rA%2b40-@ny^RiD-N!Q{Vf#6$_bm zRof$y8fml8_&lif+;u;aWd#lZ8J7E!nB128T##MLeoACdWxu8rk44zepv&0*8<2e2 z>USWy+4u*LFs1J=AhFr#I|w9Sfcb}!`lL?Nd_acoKO)^j_wNPSrTe!;_SF3sN^$Bg zmlP;XUs3=`?Rx?V?R~v~q^3t0NIMcp)~Gk5J_hn1#i%c%qb0()*3Y2%jxmt`SVsK~ z}ic2lp?-@ZP{7vCZ)JGwF7$QYTM0WTuW)YE~42Wg`jW$K99c_grh zCc_2UrO8ktdunnjrFdvk0J_wq2*{{^9_4n|KSz*VrDhS?qf|Q6D5Nyk;WQ#_6%u5@ zX97tRoTVeGcm*+f9Z8o{f?KyzL3Zg@EX25%zN$8kQk<)_@jB7IAv2b!u1cud8G7y% z`_2nZ;%bm2t2YHmRT^DkJzPoEE~FHfk|K(by=Nj>Ds%~u zRA?5Xe=+LR5vg_&u!m~X1=*!qJCQwA>!6e{s)-0Xm*rPr-3bLy{D~RlA>su+sr6had zT}YM+-3=ra+Q{f0M)&H7RJ#+{L$x~u*`?YVB73T~fl|V#CcN-bWRS`|2_%)v zp3w_BqKa+@_NdR(g6yi#Rw8>^{5eW-Dap?88j__#ZvaV!b}@RB(QX})YCC~FRC`&F zU8=oEWKY#zr<5?N31@g88KiQ1fuwRDGTNsjQfUvchf41VvP-46i0rA-2b2;unpV8NhzR?k>_8G8;YM%(QOSO-P?5Wz9loCcYVXYsKK`Qqn5GhB+e@AT7 z#5;8ID6sRWUf7&h4-nm>AR+2E7WKPD)Gx%+N*byvEIV^l@y*4VrE z@cP10^oK-{$n-^TqD{4Q>G!uN5%#s3iZPVmRLhl4-GZ3zAvwl5|`-$>XWydmM|;Ij#T1s_egG+|Z3l?m4;%ujecVM)S^2{$D?op4*i z_Jq|5ZzkNHa9_g137;iAnea)%^9gSyyqEA*!utsyC47+ZMZ)a^?iwK8=JNGCA|^II zIX$Dft^M-uw{&0K{od|dyFb zjz19pef)3nvx9Tt2up(31eXPu2UiAf3a)}%tPZY&V{8cC8{8DUKlotq;o#=rQ^6f@ zl9z(71YZrl7Tguw9ef9F^FeTLa9{A_;HN>jXmEe2wPw>)& z*$HzK=D~U9CoD)jS2U{p&m$h z2u}4V+-)-)Yb)Gsd&08`JK$h1CcK=mGvT#_H{g12CA^cc2M+f>ob5xn+$V6uFW`P( zCw!CeZNhg6-zWT;a4_NTgwDiE6E9Dkoj5P?%EX0P8^-%Z?;_layyglIE z0ec3#H{ksNdk5?r@ZEs#2mCVNo`Lrbd|=?_f$tBzGHHI&RY?ny7A0Msv?OV1(zQv~ zB`r(3A!&KiilmiEHzwVbbaT?Gq+642OIn?@CTVTbx}-ak)+gPSv>|C@(mhG{CT&W( zFX{fI2a_I3dL-%5q{osTPuiUHWYU(Ttw~QMJ)N{Y>Di>`l6E9LpY%e~i%Bmhy^{25 z(rZbtC+$kwo%D9nJ4r_?{gghPN8;oEho#pvO>G`rU;A{sU;XDFMe!-=lW+}iaB}iu ze6~-gOlxWwJhfKAr}z{}8H~>s)U-{jlef^orOqN~`!l$vz9BeivY-*CPraI=rtOc& zGr2*~=!+OWwRM**1O7wgsc#fye4P(@N{(>~5_#|&1@s5s=R=-3izu)4kI2({ks#rV zFvt`4nl+uU$b%3}f1>c$r+)4fgI@+#l&&YIqzoGwWBy4Qo;)&jL~=@Us!1c1lAJtj z*f9K?HY{z($TU#S>qV~I$%WqMYQ>Xk6R zd`f!a_$Xx;{VJ#B59iYxfRb`Lx+;seMO$(y3g^=sff83l-KJH?_8%F=Ch)wrf%c*ETf7#gIOO+AeCYtF3QP22G+F!OjEQx46cC=lsAJ z?v43CbxX~Z2^ke7^f$Y{wYs&nZYq9LxMgsSGN=|;b_ShQuM8Tmq$z`1Ya8(EQ+3Lq zvdQ?{hQAY2l|ecA$Wv0K49cs--;0z%x%F*j6VK0WZ-fAev#Z;xft&u9lNLksP%D0m zquxG=aVp<5@qCn6`@bwP>@;amT}w+-OG{mIQ%l>Z<`y_Xo6+fFM?e|_+|IZY)h*~uxurPI0S=uAd z_O0CZeBQCWrVjoesW-K{p`ocp)U-bF#t&;w{o?FjKiPG`f_^tl>vhtg|K8(Es@taI z%)l2=q!s54*?r&gmIfX^#Md=N#4c?hQH#3*zl;;-ZX5}Jt7|CCnnR7BT%1g@& zOViQCy(RBAGZ&R-mSyB;=cKo^%<#?}HQg{#W^KVxYko{uM__lE@T}`GUVr_ z(1B>skUrJ5&v)uq2cLiQ$!Awwl0Tzwil&rZ!p6xjD9FppFU(A@yU@GBW6Zp{Mfs(< zCKF^GXVf)2D>dx7y5$oSE5Wg(c`O-g0Zqyt%nWC3!hTMd_2nv_+knw+Px6 z&>jWh2@0>#W@fgMuQ8?yagF$*+tp8nd#MGTB42f zrWBMGWM<)i>63JA9YJoInYAdhFuSy@EZs1zBj*e=XGvB`20~|Ey3th~Suf?Rsk!CZ zS%`5N>Gfgib-9^0Coiiozo0BLy}s7lw2L_Ju(Iru-13sL?DWjBdHBDcKT3w8t$HY0 z%=uG`3d(b`v(Rj<7kSHGYUa%>%`M6)fv2~IX}4?5yg3H( z4y7gOqk~!5$ukUw2&wc+UFl^eLvC>qG|4R18I1nnU|7x!X?fWhc}3+VCF%98Q}k*& zMxT|Od1!V?Nmf>QNgie9nnp@xp3;@M$;_UYnO{^|SXxBcxw4MzH*@wOnZ@OqnVBWI zy6(mp>(KoclOd}NJ*yx`&p$#}-;w_|&YxCZR+?FupO5$%uCBLp=Al`cCHa}<`DK(j zTwT|i+4D>C%gYM$vM77Fy57OrhZN`M6zaMU_167PlcA_Aw>+=Bpg?CB;>~au zGo_bYk zvkD-;RM$PlTlf1+hLR$PFDfwHKG~b$6_cU7AS1T~K~66r)tli}lc6j#v#h)@2U9uG zvC_O5c9{%?C3%GzrRcSiVVF0=Zj+%P7e*>Uc$N&qy&2v$8S)AXvr&lQ5=NkOxbu4^ zLrzw4Ss}(Dy#!-o<6!vEWGF2!&&b9MPikaDS4aNCXBl&o()9eivb>VA(!6w<*3g8e z6kF?DBHvG8(+AWO+`R~W-;2(!P3`cDJsgy%A(QLsE*N#94!4zmg4Np!pyw#VrDUVs)OZNlclgA z8+|*wfLRP*aj+c6ET!oMC7DH8Wrf+yQ%Y@D-QmW)_rSlroyRDmBz<%xoQeCt3J1 z(FXaY)<#GTH5((SgKseNA;Ojw6c-kj=2{FxinbaiJzT1~SywfgSxeIkOEU8dO0!H= zEtavFv{(F$|9*{YU7*mHndxiYVkKR1VV~#Kg)?VF-dMV7^bHR_*ei3L`oB12E6&MG zNgW|1-&y#>*1#>1cT~#&q?OF%dW8>{`Rqb_p z{g$t~KYVXqzik_yTyuD@)B6736lyIIdxVFp|2%nc+JfHgzr4|PNBR6$UYs3R+E)pM zutibbpzlUC)3+NZg_@e%@N@9=yY>;$F^baJ8*XqFfldW~{GE%_@s+mg`f7n?P60UD zZ1m<|5Ci_t!G5C7zXJRfM=POelcwv%HsH`V!cY17qQHd&N>yAcK5EC}bj7bN?W?98 ztp@6BJgp%+*COJ2A14W&Cxg}GJRO`fY@E#w&Z~*D0sHoy(O@?@3&2^@Pv|LYXD@Iu zv90cl$NAW^*V&f!RkQo4f%B|vPED5(V`@JMr@HOczo8!s^s6W%yt{6wegAb2IAbCibp>*rCGgxDD!Q> zS>x7pFc_B;<0C`xC_P$d^cjuurJd1QCb6y{*5+Y&bcYv+G6gG@*}FeEz;vg>4F}sw zVv8-oV|s$sZ@Twa14&jkt96L+Mq+%l6p!*mML9+oRfEG3<7mOy=qhj&_--P;@#T0V z4N#PRvgvicA{(EzMB==eI7f}aV;eY+wQ-I*p1PE)=VyU!6|ps)jYk(aj@c8BIUYUH z%4RK(7;hoQzbD}Fk&Q7CjOSSytxZ9Uw-V#RbMbf_PG^>w0>)7>q^Pqci0d}u+TMak z|KZF9!=%JOPYah*&DF$L*@nk2;4^zZ@%4%oJ>O-QLX>wq@ttuQ9&esz?f4&nufLU# zlom*X-2bnZ*NV%5OFSOqagmSp2tOB};zWxD| zcMw~_96VNoP4Bc+P?43#Y7DB>I^ueBE*>4})}FT?h1FOYt!+k(cM{{qd3fBLVP%X$ ziI-Td5waFp4$k$&dBuD@KFPF3!9P&sErPSgRl!Q|-9>z37vgas+uC8tE}Lw8R$Ym6 z19A4a8jlS*R!-9OQ9CEM#02o&O?>?pf53o!QyJnlnS zh)zdtRS9U*l;S35)-{y%N6NYjStIqVJ*MH!#}a(PfU;kv`Bah|0m*AA`!}2MNI={; zLeJilvkx1>*`tyD4$6MXlX&D=vd2!thY;Eu+luR|Yq5=fRviwKt$K9@=Q`qCu@#S< z;EdM`O7-GInbykRNt`85<1z0XMH!e+mG>RQD^%0e*lAi|v@W8mrMkW$TgzqfqS)#QNAyJkG6#2NSEN1n!@vR3bMHvFaLYsjcx-N5pXg<_Mq11B70~<126+ zrgQX~uCz3@wOITjAM=neDDOLO;nAm7!9l;2-dE&paOC}x^47hLM}Z}8+H_@dU0Y=t zUZ}#$Yj}|e?*_5;solOJw%R>-q}C})xv;)AdYaa2x)!Ju%vDp`r%sgo;)9qr_Wi{E z?mj#kC!sciT^&754NS1{rVK;rZtky%yZ&Q59Na}&&amVjSmzt! zUic{+Iw`K)f}d<1rh&gJiX1r>Ru!iyabdg?>wnJHDU?82d}c z`sr%xbTx39gVDp>-x2#CU*Zun1!JmduWPNmRnwcwt6SQ{mqTpk{+`&+{|1j|z<#1& z_xGBvLV=5?tCvBCwbK<`K?r4(gwXC8C8^?9KlD&D5bpN_Nof5RkHmVtpZb-+UOU%N zD^~)zek875zu=K`0b-}_h(8LQOR<-LjVO3XS##D@x|d<}Zt}06h;#05c=T*glrDNB z{p#Qp&7*5cTt5?6;CDQRfGbMp%EMAvsjZ`TD#yx&E%(K2Fx?-E{Cf|>t%db1iju4= z`NV@@DyXW2=eM_pn%i5ag!CUfl2P&tc+xLaT&O2F&u+ztsdGMM(`)O)s$D3U<*=5x$>svlrv$tG9^XNW|bHAYz9_#Pc>0XwZTx`hu5X zC^XFP#P>Y$eG9(hr9YA4YG9|0xw>{*bz@DPGz5OGDawa{gwY2w{tz;bgp46=xYeZ_ z`z;%LE0s+)G+B=Y>z~A$(;KX3gY^t5-iPR+lF@yEFG)n!lsb#KPCz?hE`e@$6qwFx zSCl@wwa>Z}naOogP5U?aB1E+P4u<}ViaXF3oNt5kg!51w44q7$$_Cd&+*{&yq0#IC zDri$bWXB+)^w29djI!5|R@uUpTFP5+bqRNt=|`+&qvnD6L1M1NCA-dQFn7MGQROt1 z3L6#>zw0omzOJD*7k6$7$Tiw)Xj37Ss?5f(mXc}rL*av@@J(qD^41JA4{6|20`#jC zx*u0Hm1Ge+_>9o@Bl!L%zH5ho?_Au~>wJC*6&`uvxp%0_EV63n1-{?$&vXqxLOi+~ z9@>$39NnK#A|B&M;L$e&kIuPDA^wT1q{jq2&YzA)O(!1xuEe9uQarSkc=&Ip$K80S z57C2u=h(M{&}(=^y^BZ0$Mm0H)8l7){7sK2{8YVqI6aQW!xx8#b|N0#hY;;FdX&-Q z40=@4<9vF|p~oV6EThLQ^th8A_tE2VJR-K!<7Im6#>2lC5A_Rre2+);AB24PiAl9P z9ud9q@Y9dNs{`mkKeeuoq(>$_is(^A5BgPam41L*rQga{>1VA~`ZZ-${E#vIVzGK7 zJ?PhiRr<+a^=Vw!>ZBvzEt`} zEtP)XOr@V9Q|VX3)IaG#zlNpuphq8ikgIlPMg%6)Eq@t2?fz=`T_5!4f5`7fUGG;q zzq=FYVpaHEDU3#!kIA zY%~?)-T*#*%2WcrONsB|Rp6TszRq2X{(o=y|GfdO{$KP4a#iXL^S68U2Gj2zfZtt4 zemDMyD5dk*4}e+^(HlsvMxLw&D84FkXyK8ithufQzj4l9eKMq9PSUUV1JY04hl`rz z(|%tSdYVRIUY$pez(`|MtjFzKjM@=m)P5K2vx$A?UtoV3>;tEOU5yxkKB{g<-PC93 z@hm;Aeg==gay+f0Uachvuv))i=$S)u*Bpf0pCR`+QVSm_7s_lT86ka)_TrC42$@U# zGyVbp?H>X45#wfL_lqGRnoQ%1rRWhyk9c~}kEE$5(BnjUoJ5a7^q?k+CbiYTyHqfa zj>J+Vr4nB<;0erGQ27cfvLS$5e>I-~U7?WDTGW{+QoEEMq`tNc4|N|sKB31m>p=^A zX_d^)#RfSV6`DuVgS{YqFs(JBgcoStNV>lU4^c!U72z|B5YlNL=A&t#N)tJiCS+>h zh-XokvCXxZZ;0xQ%Plv{HKt|9q1-E}-1K8mZhu;*%#pR~GMtJWjfZFy?OG~V)QXF= zmUa@A77_)~#422)&8M;sKOSZIXlb+GM;44cdK8sKE!SOGkjm0TrD$@f(nKWM(U1w$ za*6a9K#zg+NTP>V3)7I~qn_iZw(df$tWkqRla18Cc=CNu)i2W`kfd}jLqE8RRR3Zm zR1fUO+@1PCluFfB1Nlbhan#((zCg6@DPaH7WG6>g12n_ZJ91um1zwD;r}x&f8gMh6 z9fUgaLK1P_sSvUKYrV(#HR{Of0-**?(o8vx_!Z3XvKEo7>raEMbFs=xpl0xEWN4MN zQ3EvBGi6P$Z<~@)UU>-Jt`^og9rAvKyc2{x5oAQ`=|XAls0(d7WK9>7wDxpJTY3O9 zcOgxeak41`BFd}lTf$dz35mHh17dn%Av#!AQW)$JVKAD;8v4{6QlX_J>4Ypu+5<^L zq(VYcfTqE^kd{NrxQ1lx%7KjMzSH-gY$m6vv@WRfP;PK7$w|+Hob$i8yTNCoRx}&e zLCB%$yeTI%BD|fiCrKL$An9gE(wmFaPy@6aun0jAN)0b( z8OeF15OR+D(IJOc6uO)-hpN;KBw~9JsR9uLEKT0)Int-jl#_jE=UGmYl1m^d^C!D` zju(;|9g-@Wt840N!&hzv$(vLPdG9&oohandN=dI_R#sVio7Ygjl4RUi1{u?S#`cKm zhFXBuPC9#K8MF}FB<{(;jU?fLa!B|a5~d3YelZU)J3mEAUx3zOR)LV|rP56#aB~#| z7X7Ly?GAw&#UxD%q*b6U5VDF9M7-s>+AApt*gt!Y(lJEX#3o&=C_i>PwOCY{$KdDY^k5wG-Bo#pk=czFRQ7!q|Ul0 zU>huMBWcA`AnmGyK=EQW;g8xoT_urzF^v$F7gnSRlS(B-253#Lmtb6?NiC?I;WeVu zptPFGNxTTYjm;*hs=9gykaww4>mtM_RZ_tRc|{7eMqcQ4rlC=92y>5#YH75mbXH zszD?x-!(Agc`l|RHz!;HYpHkrV5iY^!SEopCPt8Z?oB5_$$U16()X>Y$Dz6Mz)SXn+;zv=`PTC=TMek8m zR1_8Er;0=cXa`6aR+V}PaqES+Ef6=5wk;p=6c-VoO(qssQZ}w?d^r8?B7yy$fxrc{ zhbd?O{s>_Twu0Cd(>;*3u5{5EEmIFEdjrXSVh3bb_lE2%rLvKB**+0W+4uYb+7{Cb zs4OYY2&eenB>c9QAbeaO2*20jD-k5pZ}*jm0PU|CitD#OF`T4ekKa9@Y$V}3UxV|O^k4{vTv!$&`TeZWG<_pj^uT@%VIB5@&v{U_% z_AR8D zniil+8`3JP!ijp6L`~`jQ58vOrCA+;jT$ztinWvnDGCNXH=6f=- zMA^eu1i6JzEC+;JP{)l7(2l%WNa`U9d7KKlDh-7UrGttuWFgU1h@26U?}8X zvLxE}H%m%8L`hFjNe`WZlJbY4q&<2RHeH=c5_1?)9kHbl5ug(VQ~r=c$lpxzkI01l ztA|5=k{nDU?efJ8L&(<$JUXn<<(o&K;acQLD&omP6p=R)MeNe6U~dt>n4r>uaT2_w>7~;!M@-oN)>|8!WqI1rL=%-FMqL#()xCoWDXylPg zfX<(+(laZ(hMQ+e@~~=1et0yF0)<0p#<&>RW08^SE#Ns4aO^|~I1$&O<>rAYfX=_H zN@PuK_7<~)#Qa5KRzZwDz)K&Z<1?!aWB9DVPlM^FKeUp0o+Lb10|`fDs7k(!#low} zDEfMiPT{;{6;#?}y+E>hPJ*oWAWOz|%Q9P7nWB>xpc6eWf#o=Vw8oxhI={6QQDv*aYb5^W1rYyC5yY>Q@j*tzaw6qlC+SBog>>?3MmP5ppGNW_)O?My-gb}p>9e8_5 zOb+3DLCFrWZ<5$ODMx(`~W#Y(JS=sNv+_ekKH@p zA_1wZAYl0zqg#na6|;8Pqeun4l5_yiLW^rF+iX|;t0uH zviqElP7cYkEluKZ_IId+%^Og{KUJzyD5~sO44Xcp1?cvHA=MbG%3(*=nue)&N#;HG zKxWi9RXIt9V2V+4i-)cl;8L=eB|-#{exrS4*rC zQ!}%~g(UqxlTGSAlA8AgszwXp(~_Eh$f7XV+h@OF$9o{Lc^-+7M$sM&3is3ac}Q{xX;ev;gsh+baTcg zsyMu)Pe{^}&qLB#=epaGYN<=YzFlT@OG|xSOPP4F%vQZmNy_~%LdrQI{HTIx3B57t z?vgHork<4-HP(ce^BKw6^b+Lkamu0VPlhU$6|{|Q)8KRByysRhcS;h&^1{YmB(^`q2B<2A z47+T9fG&yYvWv4T5UZ_$kNWa{5_{l%h#gi3vFr74MFX5=UzPUdgtJEm=*F2%qSJ(5 zlf?T!A`?!6#LeCkY3p4`j0({8HCReunm~ZYzh#7s40A0*8WMWUs zA@e(udH$b}`RWCbsUM@5OD7>yG?ColAph(Upu2yD%;M}+hs^Iu<{SR5*yElGnN6O0 zI<^4<0lGVA$gHe#%KU+3ZaEAx_clRhfu~GI-2(x-o@mG{&Q5da`6J1keKcggcOhiX z^_1C#cXuLX-RXLxA+xf|Df1_iS(yNtzqUeVp{Gp87E6x+-JmpN7H1D}==n3rJm+M{ z{HYx>U-FdMjrEKsJp%!{foaIBta8fyg=7vr4Khn+K&HH)=y$ZctBvSFry&#j{kSk; zbI@N&==yvJopmvU-f!uXa{o#kMDhlIM1bywTI5w!m~#?}8o!aeS4$vo&CLHu9^K{C zXm5~!u`3W{k# zB+UqX;$kYbLR5h6l(JmJokPj}Q|NdWy1m*#|3T9We(5Y&O?n{MgTiYjwl0)^4A>1SgjSxSJ zL|+c{A4TO2LU~v>C=&$VnD**g3s;I{#-}72L%8l@vL+Dgs9wYxt$ccyDqdv3xpQ^~ zraF)))Hx2yrrjsg#$iaSO&L}-ePXCZzgT9;*$@@2RBqIBVnD4OHY7~W1$ft>zjqZK z$||$TrpJ+@$wpxt$b-VT!FRW;!t*-EITcfJ;YM`2vt+A zbGYwN>>$|Px65T6zS$kVo5^2S(c@M;wAJ(wF1;4WPcE%RE4!tQhljF9TFRLQd(P<_ z3eksE#Ro0wLd{M1mPK7lD@=YE9A22b^WSCBlv;20EU+orar zr6$)58-h1kI)5`-xh;I6rhMcmEG2EIEG~xJa41?QI_k0x?e-4MZV^9OMAI$uq_9Y( z&FjuZ57mU*(`7NcD|mJ7!>GJ$y?@TXhkMqL+7S*v*yfK`PP2B>v{dxbN%b@8YAxO} z4IT71q1Tv{l+YM#!I(Yb2Kd^k*3O$U%tJyu-XVQkw)IGKsT7NV8K_(vZYNt~V(JL| zq>9_C=KUM5@{tWuQb2fb#fVUa)vGo_(>|s#(p<(UgE4M{gp#bXf>3c&(*^C#!5!+!9cprinnDrgEQ~qS$J;V6 zMwy-Sny%5x>^YV&p9+I>nD2{fER~IsY%yah$d^hBr&wzp3tdlfnl}~Onq=OAq})hy z%xE~~Qm11^2*>0hNb9CdS}Qt7ZCx8)Pe#X>W^{}(-U-o4mJ#GCDs54Q>R)X2n_)x7 zcsR}+H0Ki0oKtYEHH5bcLT&mbS$EtEAa1Pe8>(-b*p3%$JCBfoB3c=1_3#lMr7Vil zlm*nFWAF#Xm?NjzoaXR%Bw1|~tVY9MqKuTOsiEvtgiBb~>>JO*_CuYvPjLlI*xq+d zhw6$8kz{_ur?0d*#Bhs4^oJJHr54n;lBs{;ueFmN1!G?zv!o0~+Axcf-PCT%6L^s# z5BKG>Lv66zO|nrjh6t95VWA3?$7A5#sMQuntDg;v>jq#f&VEF~su6Z*2?}d}vF;bUS^PyZ`-qfX4a{lO#*(IDES(#~Np3NEt!?cMAMZ>mQnVtTm*hcBp9`>W~g~Xooti zLml3sj_6QFcBrE|)KfatQ#;htI@HrU)X^PkdWV|Pp=NfdSsiM2hnmx&=60xg9cq4u zTF`-EzS?0+y?M=%Obnc2MCZ_J}`!B z_Gs#7k^1<1hS^#vwIjSj(h^KUH#y2p8-f)9Mby4jZaS44VISmuB9@9tyr$gYuxyQN7Vb^c8X0t3#d5`rwQ;0ECaFL@$>=FnnP;Hi@oe^9^poC>7D>VMT(pSI z6CyA%{Xhl)jpn9~nV9f|2z?f@4e5AYIXk4ku!Id>%&MS@@Y$YF{$sqy6SR*@vWIG< zbq=y>T4<)aaV9Laz~~*^12B5?a)4?_#fqs%S$R%HMrk&!@Cqucaw>2NVU!AkDXB7$ z4+&)t3uVKe9GG86;!QG9pC=k~7u)KfA2h$$;XEVsnW`;RVivC*B7Dn0sVVgOn$3r% zji4Jsh7)!6^J7ebJ@Tm);Yhd+G=En2t7e_JVAh0%vtky_ih(O>N_Q_$NDbo&XXtB} z;_NKP%4rE|7jo22pY52zE5Zx~G#c5$*m;%!aG~d9b~%Ff3)0T!idj0Yr@`~kE>)I6 ztae10pFKQtQaF2#JZPoA@3#FwgdW6>lRS!qM{*g8GH`cvD%=u!UQwjwJN<1=>v^EPNSi7 zxl)aeexIXpM+}$sHe;t;fQE5h5ko~6NBv(C^`|MHXTuf13a2{loT_&fdwIA2hf9<9 zoPHy0nxb#9go&bOLXRUHdZdidy;{r$3SoU3>Ck0WJ-&IZy`yLl5|!8d^in0o8+rFR zM4!CCIrwE!=&k6lJt1%bwzV|nPDjCMX?nqS1I!N>D}=#~_5Lo?yVGhhNwV)s^oT}u zGjkYQM$YBv1#thnonD}izoz%oipDnAh1_Bo zKm>Yn>TAtq;}FCI%h2;OM&cO`3#GcFDJgSBhdR&M8*TI8_jT8AqZbNNnk}XD!8CZ4 zT=UVEA4mMr&@FNn=2is-A>)n&zBNmqepNd6;VOfu!C}a?LULP&i&1FYGn}dq)uTu{ z^=a$;>4X1h{-h~~IV7fx(DygP~5mL|)&iRdA9SmJ3tLo*LwI#a!7rh4s6^}3nr^)uCFGu0brs>^4pwH<0*hdQZ4 zo!p^L=}_xC)bl&k3uw{4Pmh_7h4RplrPiL&^jyWCh|f0iPbE#AiVw)}M{qzA;~jg|p4J+o`1jy5eGY5MukW#`LNL`1m`YPF zb<{U?q~{jTzl}j}n~v$;AnS?YcaEzdmthg?!bCc`RMaOQQ;eOVD)&s`R!j(69U

      zv@%0HO>i*a*<*)gf}<&G95RNx22D&BBChE0dwYQxFU33;aVTI80%=&MJI1a&3PC8b&W zx%6*G4u^M}!h*nN}*Oa<#p`I)i<^_hNd>wO@%=sF?8ThwDO6ii()e3@WcL?L(MU2 zWcgx(y9Q+1^EiZ-6l7XL=yIf;W{tkhHT9O{X^6g8nrfs@#A44JdY{Iy^|aNKy|!Hc zgcpAyhOg{YY)PhCyTUw_euTBRS;xI%bhMB&2o2LG8RoPFK?sX|b*Xa?MJ(|}U`Ll; zXVG#ZY1!gFo!p1*o>h+W(u`PS&Vl7N6XKqn)X=oj5twY-x!a`cP}kwv!y%TC>F}m) zP9=;=n|n@<{UWjF1Up~KEm>ZiZ5>4)>!K+SImHgq7gY8*i>=(SaW-1nE2?ANJwHTc zCZKuWG3#&HZ8s0I{*%b!+2zMU_|>yYva&;EP_2tmvy|^I52hrVI=EJ2mZ?Lu(rAedv~8a< zY=$++-GP4fgmhx-yiXsPjO!MjE;>ydG!a*#~aTQh&4;hn} zEc~RVWlPl$-gs%!6r5zG;v_58dQ!X%>01rn+@^+F`r(a?R&nLlocIJ#&1gq8Q-b3>8G8>Dl?tVnma_%j!#E-g?V%wO+ebUw;N9O04Jil>wq^M^cuJPD!ic_NZ`K@MP!4vd zFgu#r%;k0GTssaj$7SMR3%*yK##k6*m`cr>8kxHD!gP&cpPcV5)*R zgDN{5%c2KX5S1Oz$~K9QH&9Bqsf`&=^YtVrTZ1~1dluyBSmjZ z9pwhasl;*yDyJPEnt9ye9V+f^^%7UNjuf}I`iKi$eZ?KFe&QO}vEnAzapE#pjJVGg zC$4k_#jUPHaj|QlxZ8DtxZZV=xZ$NKK1VyH7$c4uCgff+4Hd4Y62U-^Vc$Ur7 ztd=@_@DBT_DfrbL%ri0M22i0z*iemDRvLqA<(Za|^>C!rap1&_EsKF~hMoSA%NW=F zAKM~G8c^&sok<2fEHpE)bEf+0O!c*y>gzMrH)g84W~y(_RCmu*-(VrAC1PnmxZDW zhmSN}VW!jdZZ5Q>al)eM2hcRx;!@UA#s6$K#_VN%$q~=ed)Z5i@Wq_+jEXFA@e*&f zc7BJ=7qP!O7G+-HaHX_l*R@XcGyl8}#}r-kGa1&pDLb*`t7&g-YnqB-z1CRx^)MEG zL0NA(E~4I;j_~AfJM7XXThDsA<4CABS(xL{i}VnU3etN5RO_?Jd!j=#qgp%Ewhpzu zL!H*4PVZ1>bf_26Cg3hv6c%pQbz2*h*eO$J?6#=agp?Rdvxx|8N#6=RPj@w&JJ zwEb*1Tz_=B@6a$O2JVh-bKfY(c02uEnqqDTQa65Bn4r?yfyRUUwEGeSO`Z4_L;!hC zu&jD*!%7WSy`Skj8K#FuQd^xXJQO?cWIx({GTTy2w?ovHT|zUX!|nA(E5|wpv~ag< z#$s@*aTrpcx0*A1Ij5&H7TluQ%R>ilxu)WpE7l8^$krDl)Q1j%DQWr;Wt*+LZ>L$B zMN?iU+t6l>X&l>L7JY5iwlIQ`#*N@rQLKJOeID78&ZytT8TAoY%^J2~R{p|S!9}xz z;*9!Ki;MEIU3jV2J+Wh`b*e?{L@O<(iN!4-&x@9K!M?XTBZ;wgGDmF8U43$`Nb^E* zkwHE5hJ&X3P6i6I$pvz2v+Vu$n+sj2uU|69vb3dpsl2r936E`X)XVe4d<_;$*Na{; z1|H8rYZ!X{WscTQ)34}?;43fEU>$_160H=){;`Ob&})c{Cv*t{!B zwIS|aV96B@pAh15T<2PG=drG(1;hAl#@)CE9;+)d^<^-A^3mejYoOvWddL&^@t~yj z?Cx<~7W*7^s>ikFYP{hG;TIYg76(zN$jS=k;ZFEoV=7J8WiD`73ulpzOD>1p&$iuk zy3MkICpVj&2d#Usk=N5YT#H!8^S(lK-iZ!{^d*rq8qj19(V(laM@4d|!n&?okBTjI z$QkOoI!(8~bT<$^-|wFbp_p{h3qW*yjbHJgpW`r2unW;rbK(&Cl(`}>I&XFkx9%RB zQKL6?+QArdX=*)>w?`|yb~>Iyma|MNrof682e<~-+iwkj&fpiseCPiW_Z@(76xZK7 zC)tuM1EvH_wGDP41QP4yN_WKuSIP8%kYyPQTx7|WJ&Z6IOf!VuL+`!!-a8?bB=k^1 zI)wDX_xsK4?3CR-on+aro0sOB9RS>bqbxRat*EwQY-ekNa!YO*+jUEq`ri-52calG^1A_!^;j^kX#q}|QCpU? zL5^M>z%9#OcGqkL@(LINZdF7sp#}3452-q-@1yctBus0apnxfux=TEgFgzj&&gP6x zl36q7s7w#i3vDKLu+wKwnl{y1s%L>#H`}z@Vp6@xYAmOuq{(GIOfGeLYLP9omAiwO zN}h(P{f}orhKL>;kl{5N{L7wNHJ$D*xU~+N}ThRoM11p5dhIFDSCOk7-KIm1l%&B<$_iZhw=&0(sR>QLS-bpJ_!aR zJwT^4tWZJtM$Je;|1&u*+v?%Tf~hz^3ttut%#~00a>m`XCaq8R0PxM`$8Z5jnVl=~ zqm8Vc!|a4-)xOw1oan(~XaW}4q0(i_)qGiEc4ct1>5A^Rh3a=fe7(sdxHUDAh++t? z(y`^v^mSj7(n{$L^=y|ZYImsdDBUBzGWb>c6dJ@zox;O0h4W&XIHj((-jV!36#t>H zxH^w;DSJ84u)2|^6;#+Y+qTVpK`Z_i*ISq37%>FD$i=^aIxeAM-xaNYrCJ|aKf_)| zbdCL)hXmEouuFbusH(DLN~)T{2AC?f&3-xt|Eao4G6b|1=)v$)-^ zs1JMgE{Ljv=u;5u6~y`lu>r#>e(!^SXtX-aUbh4#S}s`T)uW{vqi&VEa1q5D+~Y$q z*(}#S%s!cGKNo!EwOKtZ5**FSW+gD{xs^Bq)E|tvT(ih`@7*5$MV~~FZfh|lU2aMn z$K zJF1yyt~6j%xiPi|_*WGS$bO0FHy=ZWB;1@yww2bwonOmT0L1j_$!j-d7s1o~&>Tkd zcZ;TAgKbfaYV10v#87p$FotX^h{vLAx@q;Hn3q<9!q;SNa^>THeX z3_PBu371lBIT74zu-e!6fKfdnQf~OfwyYx?r1IH@FRUU@Hb)r-EE{GqOUs?Y;gm`3 zspHPC0Ol%xVS9n$1y&cBTwrg3u?3bEs8+l+Gb%xjxnxfAmyEM<+*?6hx&A;`Y@6!7 zz=&@5Kvy#~;!_SDCDk_ui4^Ut4BnC;^J8U}VEVonX<7EKv$QM}$N%jOuzGlcNgDGp z>_SC1Aj*7C+&0Z?tIurqa1 zDd^N-rQN6s>WaK;UjYKw&`N)}?KE9moOqTCF7$dgJnG$Eh_%wI8S?dy zr7`a8f;guj&Mk=Z3gY~NxS${|EQpH=;^Kn1q#!N@{uabf3gU7gRzUzQu2Nx^1#xXb zTvrg+7sL$(abrQ;R1h~8#4QDJYeC#r5Vse^9R+b`LEKdkcNfGx1#xdd+*c6y7sLYv z@nAtbR1gmr#3KdqXhA$y5RVtc69w^PK|ECuPZz{91@UY_JXa9U7sLw%@nS)|Bz-Yn zDTr4K;@_<2G6q9A@*5bqVl`;2%I9~Q(% z1@Un~d{Pj>Us?Q(#ot*_;V=Hlg4zY~Zx&P` ziT|>oIavh2J|S2zyM!oXQO=?Vi=HePNgx=cDSEN!&7z70!}Y{^EY@d1zK7A&@8u@wvEb`jgK=+A-?Xks9XZCP+jCHZr%xAHH#X=S>EEch7WzoiBF^eTEmaGLpRt6`<5?`u8;Bir2wtXH;cqvXznDdcihc@&v!NvTF?Pt~<-4K_)vA2iM=|D@hK@>g(kJpDcte+b1N zL-D6jd=-kXL-FTOd=rY~Zb|wv%!%hSskrzFkZNSS4S^}e-i0iJmL-h9XiMW;0uI}2 zn+1~ZEgd??v56cGlf@6Ubq^KB);*?4xL<*&BTc$A@TbCxdjT>SFDN|&;r=T7KVuYB zRJL??9x8d$lX$A(WFy5pBSu1iqT84ed0d2((!Q1HOuxS)9!tV91>Qu z=P4I*Y}dB`%sqHH*ieBQ*PeJ7D8Q-SylAgsBZ+$cMLGmv zTfO_p&m3dh84rPWZZEwEYU{@Niv1O$oF}4cGi&3#riRwo#CktO_O+mGRl%kGCQO<< z9>&xXk1Ft1%fNkxlsOAbSh zO&11$9@g6=e)!OIo5cl)&!!M!Q*6mboJloA$%+d@o{TtlW9;0f#-k=QH_e-EMQ@Y= z**=#l-05>yv=OI*fpV%g!b9v0VZ&U~xEOPIhu%(ZnEs+NI5dU_;twr(;XJ_N*od^- ztFu3zk2m%Y#_guqVphTyvzyH|90mUp*m3{i&#Wd)2`&!Rf=g5-7gu>V%Bu$?qC@Aj zH8w1m6Gw+KkoNTfwBN2#!+|G}VfZ^>^-+Lz(?vQuAv-qBa;AfzAnU7hJP@0Lavs)f zEqeH5aDuc$#>Uvgo+&+GKa0AY|$faS=Lrm&87VUQTRiQyI`3=8bEbW7!etIr7^$ zmVaEGO>YNb5Ziczs2&wj1&fL+eS*;<v-gD2f3zsZdJhK%6Q_TyGIJl{GVOxDoey_bo z?Irb=2+cePYpq?tn;EN%;Tl`G?j2x~F@qig{Nmoo#V<(*JkJ2+f|A)fr8naoOhB%@ zJ}iUR_r}uS8)-ysoT!`VdLhk&BsSC{OYpx)S(fublejx7PLt9YO{zqhDo*Bt{)w55 z%scMP9$%2zv*bbsxp-F*UL)R0Ak`EXj`joepEMtWd#1`8%n*9WkXJ_3O?128!zLI6eqtp|C7&kspxO`|XmXrr>kMrl}75!bok za*t9DkJRT5p-cvZDJp5Z@LjV~stp_G0(;L?i~$j*u}B0nY@5XZCPN=fEs*plO+yKo znMyP;RR%*W$RSOEy@zN9=3Z|wH=k^~uN)8@%GJm}+>Kd*;kYYJ@siuE7+) zVN1%$A@4NcZ>6iQ){D@YZ|nq_zq076RyM3$(95q;CuJ}jGxRaqn6bvROl{5qB*D1XV|jk3wH!NglS7ryT-qElo!f zPFuYVtlbbOXD&jd7MNg$2rkSjMV0}2?wou$2iaSDaXDIFp#oeK}ClvRF z;=WMaABqP;@n9$(3dO^rcq9~$hT^eMJRXWCLh)oMo(jd&p?D?~&xYc;P&^-s7eeu3 zC|(N1%b|EB6t9whJ)i_uN6&E(`ul!NdsKKrg0XE1UT}st{aSZ8fCNORbxyJ&X^NDr z4BO0`m&0mBFXbj?uwBv81oE>?S+Ec@qZ#!0<%?Sz8W-0snbiux**Kdq#p_6W>!Ey1 z@gr$7vUt}bxK8!)@S=J|+HM&k{UXs>ZGeq~8S>pD1wPVTHPtsZqT}!12U+l$l~V#%5Qs9 zU#&ee9odd-B@v2iv8T%5&t#HF&4fHSP0O*TY2p!d?ej2Q(jA^$dgm1kOy+S3Ob7mV zY>MTpeevp}NU)+}$o4>J$GZz80Fnwmsjgkw05GeCVBuU zI^D3$j0CwSgJu54pI_~VU|1$IK)~quWim+6awwV5z8S<_G%tWeD>k1DJ%KlAwJz$OL;IZ1E#o4W7RX$QbL zKhAke1=emh($(ZM@~18V;?aVc*yKy4yq5#Y@e|+KA2McK%FTwyXSv@PkE0xXto?dM zB}6h#8!*^KU&o*Jd(pHpEfOpQPHLnVFh4ZDCWdI#1!i44L!_Gn1u$EwCmmMjOL4L? zcvWvJS`mz9wiV@Qksc0%q}#sYiPCPlfIP8heb~d^3(H)`GqL`Vfv35x0o-9e)D5lm zDhUsLd?fM3mqCLMEA6CX(2Q=q$l#Q<36R*Pf~OIt7_X^XI~m};K(axaAj9}!zdIBZ z`A$WVu`!5Ep|wD`CK8g_eO3wkif}D}grxe0Q>qV7`}d6YOB;dE{|e znr4U;D#0kE^q@7tuX@!~BfM2EduMY?Wd`bTp8*%zWUVRfrobnHn z_8z#A^4IZiC*Zd~lLnu|G{v(Q-1#7PJ=82nn?LOS{%Jnf00nwkbDR<@HwH?%Nj~YW ziCloqx-psuSh0#O9i@3dx=C+(bYzOu73fsNPzzD$IYY^R-saK?Z+^p2O{SW*u(3B{ zPOecCV~qD|eWhaNwgAd%MX0DiiuuG~JRe|FDu*^7gdobrsufCK$gd82zxDMdK#yUj zkBl1y{clZf=@)&(}+KW*o=v zrgOU%D`%8H-`d;P*{wmEPv)CDxOzIqT?)yh zDeg}#8e^6}*S+B~^yvvHyu%cV_((4c8*`3dZrY+U!&-qqhX&wCAE!nn%taLcGUL!K zwp$ghO>NYX zysMQj-xPU^ENpU_I4YM>fad}6l;F?{*MH+oynb4KRp+G4n~moWsppQj-yy))w>)}V ztrxW+;C5WNz-n)j_($Da%sHuh8yI1;uOFd0>}a(( zmBs*KmG8K<1$gIG7D8oGviHC{XUEGXgTq~lN%~0Y=a(Xr_QF;M&S@R}W@^5$TI3cO zYCpB_=}U0Mk!AJ{*bXX z^U|Ts4tcGI>FHAmbtKS)0>NI3Cjf)!kFMBl%%^;tufv-TGK4%*`K5>{XO)$oW3eE3 z{OMzgbqc&!K>f~_uF!Y+%Uv7P`Vp)$>krfHXpiWjTFqbf`3)PEk)kuf|tF8TCI=hNhdKW6wMNz za8_4hAxD;Qi)9(%LPAm}uWL0+z}A1<1YFq8n~J>YWV-qpc?-~`1U1(G*Qj%GA+SJzKHc|zHe&?dQ{6t#Cgz*NJ6soYJF0w^; zp!z^kJb|4*mQH$L0tb2nuGZ1PhMrJ0fEM8ec6A3XBgzr1{HrZ8H6^j`gL;y8K@E^X znw>=QwDB`6zZt#=&1%%iOHx+k-B^)*6$#@}s-Q#`ir$V9Zs&Uz@wB^fOIn~~P`*Xy zVbk%_VBYt$95Z_U{O$Yj7YF7y_Lh4&-H86K38U$L6|ASMmB|B zNests_;qips;d*GPqkJh56;|-S*sP!U_>!#@ljMv+OpydVV!llL1rckDWqXPMGAZ! zIPnUwNv2Jb?kw<)26Gxc4+pu|HZ8IoGZ-qhn_6hfvk|M!X8P}8w(j!4GBTlO1XQp^ zr9n7dCn!Y|m8Cfs9OG426ZvsTksua3G579FIb!GAs>_~Q0EezEsFxPTR8CxnvF;L$ zl}RRiPtIT9{dfc3>e=cv>=Xd61b~lGHA&f?KJ?HpI)3z9LvS4(`DZjNU0yHa<-gRr zhwG%!y0Aq{vy1f>XR>k&A3mZZpYY*BZJ+SIBzGcc-vA9z=vf%`&hOO**t8vO%MRSx z#!5D3zr9gW0~-nU!Q(f4h?nS)HWdi;sW;=*HPN~<%bkl89@*}cTbuh_z##27U?6QR zEeOTJP_%?%Q7BpwY#55gp;!`%rJ-0BishkL5sITj5r(1=ies45h|%LFO3%=FH-!)! zjlGODmBEx)T1?xsoQN?qNH(beH5h6(36=sh7d-0IF`a|c1r?mUihznC>M3kZYG2*h zS4*7E1&4TT=kD6!=Ys1!nyB4F&Fm=&DAS!=O=28i0c}&2 zwl~T%C>%A{xZYL4C6eXLZ<=2}tD&{E8UC5d-Yxeor)0kbGf`5UEn3pFaGRR}7ip5? z47l7yUh9uAVb;eUBs%ub)h2ruMN6@f3%2)gC7%pFBLz|WsUkFz87N$JMWi2zwx5tB z^qNpe?wY;gz^KjS5g1#_!!JM!61_`sx{`X=KhZmf-KrkBLHD+{IL;HbO+gGOh;0jE zP(ggRAa*E-9SdS7t~urfQO6{z$||{8idE0Hhb>~|jq@h=7qR!|6d=K+W<}&PU3%Zf z%DYM}Eu-U66eN}43_!(qtKX-^)EK&&`gJwFeo>-qo#VE3B%VJXJ-0pM=i>Q~tzl#` zlov6KgN?S*xBr|CuogU|*J<=6c-0Xs%A1q1^1z+?y)Fq~b0 zkdU(ewAatw9-u}>ZXm|d03%_3CASXgT~HyF&p7nH_$tXfgCT3FAe`Jn1J_#m7`(im z-)RY4Jw{TTfszAQ!_1D3L&GCKK>aV`+S zMg4+3>s8ot8&euL9ML2rf9vb9KW~^99XBlF$eBnIfx&HRueSyypsaGhz+gKZzv%%% z@+~K+r6TOoue=Rfu-y9f;d-e+NCwj4fFy&pLz7thGx*iq?Tm4PHAXu8?`QBVsrX$B z;4+m^u?>>yy-SB;*GA~;Eo{l;I~QRgJd({v%y}WHd}NoP{QN<|vPPT*bX08cI1?() zUtsmaf74zksbOnB#(Ej8mjt}=Y(KE0u@vrCcxM}B4@AWeNvZ;m4ulG~G%%E69HviV z57)_UX5{Ws?7zm+c+o@IYA|fiy^b8Bn9DlU$G&nEy4+Z?n%_n#Ru`jBGH7#B#VIS> z-waM&*mPw_K`m$*Lfm4~-$fSOwPxJs*nF zuVU}qNlvPQ9r5l*X2N0l&2YOv7nA?E*S%`ZM+|Sq0tvo>14Fy28{lPW}W`D;F z*dK^HLj8sTvvj<)>E=7Y&`s^ZdT|-kFyH5R{nR2vLeGHBYnJxc(la1=jt!xjeA>|u zD?kcb#3CtkBi~Y5V`|%H9X~Wmc)YtZE-3(t}A|Jcin|1@P9ON;?ZQQ0HY$N~9LJu9a5O6fN);sOP(y zFHf`hGEXvDq%&#B<3&6#hZ~Vf>jnvdTH7=_3E%xwhcYxbK*eZ6wsXO4-u&zI#QnGj zks9DAU~AL&xMQ~`jFKMX|oI?5foWDUGdQh2ZcA3!s3h|GVXA9bKGhy*e*dj zyI*^wsMbOFW*8JWA_5bPK;KStrz<)YJ5RHuXFO<7`W-J%GxIPS1+Zu6YQLHnVaUD6iHWSl7* z9;sxrqG?>)p5EAeQc9qU0!(NH3L_LXlw(7z0 zD{5jq>7xUE1=T38s>M=c>)00Hd6}$m#)$eEBkL1M0_%9Zg-2Io?Uu3m;`${o;@F^C7K z8(+Ks_;K~1fpG{CiBIS?3CiqAX(z|3qZJ1pYcBk(!NAkZ?4VLKBin+xf*!sWxv19W&R(5G`dvTOMQodU$b-5~6HTdOSeQjJ*k*@7!+2OrjNvS{Yoe8nju* zIP_zHy$YR7Ne6+~->K!v{To`F8)i2*T6x@pCya97YM|Xpe3M-t8ZAvXr2zGcW+=pHA6| zIzg8m9O7W$EjgKT|1AG!O61srDA3G|aSF!xKE{{}mLwpV$n8(*G9lqQ(&fWmB{iwy zOVY(x$u36bt_;@GYCqbRW?Be8foeYmaVHbuAVB*Wo5R#rGj+su8(z66Mw+lRKtG$XwvO<{^3m{`Gg-esHtt5`l^6D5F32LSeP;BMw zl1Z_x3bD)3Ok!%?L>{{v^M?w|^7o%3x{?0YwKOy~%~r=Tw9b_2;gFB7ynMHI5wtG> z2a^Y}zgF@&;_u571xr7It|~Zu1+(M8B?TrzsCb@L9w}A9!Ku$->+-ckFjr%emHXXa zdMho_Qu1D&<+~_%%F0pD5j}w9qDMnRv?_pxXceLwAjfa2q$VcfMU1Ak`M4KIG*e@q zI@GV(!lKiGd%M{5%G)Effnqfn9+Q4<+eJ{)-J?2?@Rl~5FjczBV+NT>JyK(uh3~jk z^z`vu$5JCY*Z6b+7cfuCrBqQ>|8*xNYlp8^&_1-@>Sf z<|L56$VSCdUgUy1{M8h(1Jh;hLr%|%C3QAERn|-+_R8^T9tZJo-G(IHp}AfpMV+JDtef;1yOtL{weyIi&Qz z6rPZ0X!PvatxPk7RDOU#oH2%hP`69y)!Eyq>FDYVAG7t@YZKW`nTH%?9dXTEK3Rge zOn0ZUaY2x?Y~tW-u}z%*ZqE`h=qiYYj5(C6w7uV!iX<+_MEAq5c>V|-+7wDkyJwt? zt+T#tD?@Q?DB44DTqstB;`mUU5Q^2II589_gp*S@Zr-kBlCSz-Jw0a}m z*rl7H)mvtCFNsb6?Wmy9(weH!FJEbT2~^TO<)S2mGpJ#Sp~#;XuUhki!JL#`BHS75 zPn}M}V~~d&Svs<3sxu@S$!#07VGqR)+hZo}U5_(>Cyhp`8@ln+#)3oWgZ5monb&N! zRx-+ol9BMh*(gDxi?h;3EvYsd>+Mo4*F}0P7*xFtM<;^p0w|q7k3UClycC0Nf278{ z)9Y%DPV*$mTuC0aNCW3r0@>N)E+o|;{OK;f7M+8amCa9MYFxzO<9k@T59__fl!Z&1 zCe5F3Z7rCj^E6qf{U2aVExrkni-#LHCl@^FJ-=iY1RWm_3(&aWs!*v zllFb#QNHS-sfs@+ceALD1z2oPybk7(G0jsbL_2S+2Nx@?op&za@k22qQqfv!cFZE| z%SE_CGNr2EXPUK;^x}+nEDkhKwFUW%n>Z59y)AHD~DvxrD^KXUE*BUWaSPwEKWwaATl}Z=7qbH*QT%@Zh4Y8;1UQ+bBu)ptJe0_o23X z8GU0U?jrlGi=vKoW?wU6dg5o8Jx_r2eyp|4gto?#V(te4{*OgLk;E0-i&$AR974{i zrkVV#tXvFF!};eRxeWr?fx+bV68ArrZj;VK7~PZ%!u%j{u=PAB&dx2#?IY3&Wcq!4 z&);^*oXT}rxEQ+HeC-j%J{`@~+w{JFmZMJshW^%{%yGRdGJ7Ihx+Ho*U zY;SmTSPefSNoNexRk>w!PNvLY7;8IF8C+p_U6fhVml=LhRuzoLmKR%5j4`S9t`oMjy&+Iv(xcOWVRAeT*%01G!?6n>y=fqp7ylc5~2E9y-Td z?xvT55X?9)n?56Q^<{%#cY>u%H z%*Lqe!DQ=^->wyh-GQDiwWA|Yd8?{CarVkaSQxi?;HydUb2TC2%nn$(N?K7qw_kv$ zrKJt?nrGL;*{5MXvJL0B~*aez1HvM zkjM{Na`pW{7b@wxhAE~V);JDg8Xk%nRczJ3#xD*Sa>r@j$nrXCfmz^+G7*2F2+0zwEV@(` zoY+r!-XXaFpxr~!8~A5wjGWojI=^{A16=hiJnV@PU+nd!M(=D5mxS=pbB$79rb&yE zYf4-|GUfY{um@#{Vb61S#!8MOll^Y3L|Qmt7^KL%4Db_dA*u{}ta0Ct1AF`+noEc* z&}f+XT#0!;G1iuAcTP7e)noWggUYn&CN%2~&#+*izecH#98v zri?u(;UnguL|z{vY)G~uuvmSbu1FGCxp4%d-|y8^qZ7-!3a7+z@e*iCX9(|n2{bn< zc=w?Ew<*Smge`)J>^_!6=Xje1GPP061L*)YPqtBqP?~ts`vm3NL-O}Tf8>X5UhM4# zG=+N;dxDFQmIRK=nWSBN19pY3?}3`DZ7gA01a~ujBy@=9dzhLG){o{cfvXmC#L370 z+-dR2-~bRlBN|yD01mXbuon5!-KBdq5cXEDv)X=Q5CpV`p7`k-7Y9+!ju6F~#2QeW zyJCXGlxB4+7Br55-!f<L4atdmGD7x=Kdmkd5<1zukRlKtiM;N!Q=uKcASnkuNX1b<19U~4?Nsk1bJ~d19z>H?%_5p*cW7o3S1VjNC#qpB48Di}MpFO|>n% zJAfXZ?4g)en@c%PY8GYM3Tbo(MY`694{Q_?K4$N)j3i0BwRSq<>BNyeP0f}YzYs?N zd>iVM)C!`kAj%7(M?v%~hzjI7=2Y=4=iU)Ugqhde=pDAk6w6ChCA2pqCos4ST8YJ%P0>>ZSxM?Ua}xZz zX2L0YGU%=h!XVq*!~<6K$SAsXB8i)AQ2Ida1Jh)G$Dnj$Y?Yv=gtkWHnECxpGA3%i z70SAd6zu3I$&qdh#Z95OITW{q0vX_|f=$#A6!!q*cv#G2Jg=tGSI3DbmAdYWR{l-#!ZI>KUmRN)*^BKX z^plx2Jbm(Wc)v!zXEKS@Cg>Hoz(bz=hzNPiA|*M1jF~RES^I?Yih&7@ZspOgI2j^9p%T8lXZqS(MWSM-A#7o$dzIz&$-8E+9*NVi zy1J@hxjmQc67J3qn~Be-n;QRuN#DWA#^_lz8*){_vpXSr6NUt^M*JUx{nn$E)!L)N z^slqJgv#I>B`(op*IFs(pt)!K=7uCxZ{Ut_sPz=|G={plH#C=%p4MZ(W4u^9*sy?lZc0q(6Y2B7AC^PVNVm!QAk;x|HeeMSie&n z8+kNC%CB!ID_?{0V!$$^vP@^$$gFGn4C|*r(k_{=Z;_-4){V!yj`cNqs zQ?CG|7RSPqH5}s%r8eNjrB}15am@Xv8u8Am+5}=M4(A4AD48!8jP&L&uhWD$w5hB} zicCw2$_1x;$UiKy%sR5FINm37j*)7R_M$*E^wRtsa_-o=bSQQ#M_c4}jP>p=0C|De ze$tdn9RU`fOBt;tR~0my%-TTsg|l&DFv!3}ZR>6<{`&9Nh#)$$q`m=$T_haPNey?< zy2Wo5IfGg+I)%(4YCi$`<`gRNa55F6V7mPmr0 zYJF!a>zIKl{o1mJDrze8=1M}%?Si4fj*Yb0LwxA#JtYPZ0p56w>mkU~n4dxgMA!Ls z>6~E(t4PH_likU4@M&B`BbY{ynU`$4(x({bDi2-qI)teo(IpNTjjUP8fYIKP>Dcga zyb~Yrs;|+Uz)%8?AwB1s*0gV^#t^Y_iwNF<1#!ED3aO_tehGSX|FhWTVb%)pTAxocvSg#<~m#IjRRLUQTPCsJ+#od1tiB}c}sAIod?w`h&uWwrz zn61xxn1=~+kr7X!$~4F&191+Z_<^A=h~|=ju(yiqqm8Q~ZU|;M({(s}4__V-uc+kv zGqIjt&=TInhBhQeTs*0+Y2L(zNX=kO!!$=!s}5j$29uU;(Ru?TSn8o`Qh!I(S0Qc1 zQNJ?yL^d=7{~%^lXIw9(z7ZWB_+5`)wyPbrlb&S&p6?U`L7r*oxT`dQ&TXGY=VZIx z6(7oN8BAMMvS+jb|XKI(n)9e!&ZztyZ(a#rIc zV)lUyATZJ5A2aztJBDL-wDd%5Wr|%6m{TIQd#?w@_J4J6Mo+=X%=G?-pv$ZR_*WJD zz3AI&X)|wQaJbBR*P?~n-$s3sZcr9(39r~;C1$!SPwdGioGw`4omzb5Bao%gTsv|m%1EPN~4+^oufL385)^7 zzZ(YSeYQ?Wk8R6j&Y@U%917v_ivbiKPm6d{k}nM)UkU)w+=lgG-&h%G&%J#Zho_{> z1%FMKVPtr|*UvJ1$CeIiW{_097=9CyqC>*o4JSjhR%D7}s8t zOag>+%)H*@MWMwEKggdLV(}+QmS=G5Y!PLi z5=FsFDeyi>n`@HoOBw01-?9E++}mG0ji zv?GcyRjkD3FpR0)%=AO%g6EbmR&-29`*Xd;p-)*c&0`tTtFXwPLMhY`7?Y?gay~UH zfMe+(CrVYY3Py#+^V?ulXdFHi3Am-}E-ea@W&99!1s>wi+(M)JWUVsUDeW;_%?$wP zVwJAk{1m+UHO+}yTbEl0_|kIll77|D)@r@tJYN>kYg>m{BwT`7+s~ArfC;y?q>^|F z>?5r;)hX|TT+qWqsOk}sdTb(jylvo$lo=fwxDGKOjM7;7URdVA}9YDqCco&vxfM8Hw7S4786HDIsuuR`&4DE=G@Bsl&{ zDE=CXzlGxOq4-BA{uzpYkqmrl)BL<={Ms6cd4GPg#KaaERxwi};+rW?kyOdEPC-nH zX*Dy1e(kRvebkBJQY3zI?RdmbGAb#uLPImo!kkoU+<_C8;ntfGUv`dmhgZwl1zb~6 zmO+g3O+ca@k9aNML^n{|^f7Zq3xz-uO#FibpFj2l+2A%lp-`1XUzyf(LI3A4@iIa) zDeCM&QD+cEodNY>|Ez=)7lq>DP+SsxvZ06aXZ8{9+{g8Dz0iWLE|MyhsGgM-FF5`eHTJ zL)79xPCmYgA3SU{h<$|5O?&pU@a+*sVVDf-}h$|#m!~wJJ361Cmi4gu( z1%LGjlzCSf9Aw;OsxvjBXTe|QooIS^u9qY<#`(dWC+s)ii|1`BaL7sG^aq_r!EuEsxi0^?|L8s|MI0M@bpf*)NP% zt4oH4QKJTOA1~~WfyWPf14$Ykpht%)m-&U#B`>)FQb)5O>8rhHMvsO5E?zZ1#9Dt! zl9xJ%yfmU08tAjo`&Gizj^#< z>cR!^3yEcBI?L3k6-RRcd;u*A`zBuYk}qqk^Yu=I!wq=#h$4qhxXYn)+dy`CnAh~SrX{msmWhMm==VO$0>q*WznhD}Rmb>K zr!C$F|7dFOC@Z89Yk&@cBn&EnQKs*UA*ph1RZuz3&eU*%JGTQWhWnRU>x?VWN%yiF zc=+SqXlis8VKW*!Z^3E@#^*W?WE(W$7;3EoIw#fSvz(J|!|=aKpU~I>tH`38#2m7v zve#7xkLr1aDGO1K*1YnJ=>sKf4Wsgd>8#|2utpgqsDW%{sb{uCr2MYYj(6hzW34xf z0q57P@1WT5?AX2F$G@cq=xUu6$gFs7DIsKBSww0Cs`&Njv!9HrR(X0LWo~9R1WR8F z4<4V4NRB%^J_SxeKS$0n9wKlqS04({lgi*99#Mdx6H^2v9Sq*RO6i7%j~ucbZ15nx zC;wUM^IWjpBkY<983-YvF;({5tjWCK^5~Bo&yRp_!4-&=qD6ChD|`$P{Yln)xt8m{ z^y;qGM~$1EAmzw}pOTdbt}1v*h6Ny^8dYxxo{rc)6BU?}UEwiA2DYrWc2Kq`NE6V( z-el(WIc1J|sDmR_rT?>JY-ny_%%8|s!FaiIvykudz z6QEVv){K^`!^84J(EOsry0_ZC5mk&;Ttc1Y4N=@S`TPnHc{w5lI(obP%nI&Z3_3o?hkf!C7)t%1;~lw7X#-_XIkxBkQN;P=8OUid!fVmF z3DNkagNA2>{2b%|V-ZqFTVa~y+glzgqkI@}IGjiCT(Q?ZKYC*>>Xlg3)SljG}ad;(oi$z=0YxCYw4b=mM&6xseTy>p0*>% zu+Z@!h#?WkrHRpYig_I`Cqf$qoeb7A)=B+=jERk%uqYM$&_*V8RGBXy&4qmQd&z`Z z#dNTSSQ4jd=NAf96Dj_W#=CDK3L2;0CjAQ9=V3;mKre>|F&Av@;c2zDn3>f|9TxD^ z)?tlOgI2A22JN4t<#S}OW`H2YJK>>t{BbNVNXb2M*7O!It^LI(A38OO*&k&oN3AVV zE~t$W)m5q+H&(Owt&l!=-$#qzwk2pr&(ucRoh2DmV&DnKqrs+{1N@f4Sg?R`=D&Ro^?aZI{w(yuG!z?VA^b zIs&dgb+_;Ocm`(SZA!ThPs9*ANcOy6iB{GbaS8Hml$VI|ZI0=;rBi?>-&!uEx!?%D z+Q>L6$0jwHSd&^*QPzN}VE^bG+c-JsAzC7up7EwK_#(n}-=Xg$U`CsIXR}ad_4rsl zuBNZBt-?MI?-nQc^KvYa*amqEIP{W~pQPl+xD|5y{T>u_jJ^@rC{v|tL8Y!hlz$3n z8(koiSJgMSAvhYRH8sq`dCS47TseLbwC6w*&lyaa>jlFPQd!Xi;OXJs`jjlgIo8Rn zHfsZr3;vMKf929cfrmm3UTUq(#NMlmp z(Ac`TzIh>1k}O%!7@wH5C6?fq1Gol%;J1}LoCq|m9Lk!6cZ=gs^_;|$I_J3MBT)ZR z4|c8qG15T5B5cq~$J`wOvKC66g&Lc@8f}_UoUNxR#Iiz-D}yZ!>PBa+ry%Z3;P?)t zsj$OLw+#a{E?*&GGQ;uz8jTU`pE?2q3I~T8ydO*CGb+xsG1K3;) zH87pQ9pQf?vGAMpg(8QU zt%Sj8(H_mH)`w~s)g(x#INd$wB1{8m=MuOpu)8ra3e>rvEv*-+Q1pDw7aP(^zSHrGmHXXp~I64fTUZ&T4c# zpWz}D$(%%EQUM@!*CtT1GPqVT26igdwvfs#w!`Y)FdmHcoh124EL$J>D7hvx+Xyqe zAestd4ps6eSWuhfhMGJAt#)I)J9mlXB@lPM@4+FjGbkEOTnS`77kut7u$oj|ei7}E zB|yRJR=eA@ErA0o(^bly35}FL>bIjXk6t>Oj^~ZEleJAs?b>)WeUe2ca1LtLQ8eFym2t5g2P7!7 zJUy*_>M)q%`5bR$)TFz`fkLDkXD!Q5E*Rtof=(SjZR+HO2*yBOvL?)rO8)rGrXa%* z-HxSlgqin`=z)09j~NeoHR3_1AR2TZMuYAnWGHCQ7&gerkgyBw3Gh_P@kdG_X7|FM zExBJ02>&ZWCI8*Uc=tuzf=prTS)K-fw@*@-B99vM^Zio?S!68k0rf?Md4(;KFvltn{7M;rQ08U;xsh!E^>)|2aZ*h!Cw@lc$$-? z!8jMqA7;sbS#gW!WAAca0;!_irRhm@e4Z<=OA8zp?oa)Z=)lvxVu>FnQ*11IxKw{e5y;)tx)?6}t#HRQcC2jxfE6~8WM-R~O466{Vz1lD zSpC@5Av0XvvK~|h{UdCE!L+)?B5u^YO^!)Is-NL%aJ_;z4SB7)aFj`KH-n2unybDx zIbUX|>`+IzdIwtRVQOX2E(ukbtu}fKy_^`W8^(oT&+Med`!(MGK)q+y4yX_NHkBS0AjNA1g4FH~WxjGw`jJ>^YV^^ioQAq4|~ zDBb3*)zeE93!a9)Ky% zEPK)a?@tgja|7$c0sre1{WwM-0lp}tcp?|7biwVjs(?_eo{@!99*~o%29nkmiFG}z zf;RX@!;{Q%k6zdU(mG$0*7-%>Bh_abGaA>hxFP04zaOdiP`l|SE^pOA``e!-v z5?sJ@f`^oW6AdYooM?~8t8Bu;*7^QHj?6lGrKFs-wqj@u9-qE)%Gh!B)25HDA3L|H z@hCIz?erFsB42q>UY(g3+e(wd)Y!k5d&JAV#a*K{ct)fJ=()I67=hHk$#dD`Gw=+# zlw4dpw;xPdl8%^W3%&`ba~FaM!}&a-N(f0xr0e3*yL%XNOB+%825K27?o6AV3?G^z zLY)qM!o`Xm*}Q01aNKiNHnz>xro#Er#Ee@wA9+UnsbL25-r8xGr$c#}_r`+3_lQLR zDP&BWK6BDE9JvthBliF?nQSp<$RUmxwmK-^#aZO_NCmHbj|HnEjb zSYlJV33xoqf`)q()y059|A-bc2`Wg8lL+-O(1aKKm56jvQlV=s8OrXcvZ2{qyKSPX zp$3&14Q(m^QB+;+VOk#UB+05_B*|SJnKb30X_dinRWay(;-s^;G2pu-9O`U1)Zy_( z@~aGC)`_=D6>1q^+h#zSR~{1SNO&^>yC0@Gnc;d#z6Plam z%?`}M<$~DXu;PSxdIlE6Vb+3Jl#1u)V>P^{pyg>o9KCAlfG48|;ly)|nx+++@Rs?OxKHeBv&He;Nh<}yA6l-ze5Qg-Hej?V_2WpMTVEEMOJ_OT! zbUcbQ+oPqQw+_V01$FUPYOuSIT^Fo&wWiBK!;aMaa|~3OhAm!2y?0Dn;BT79S$r@U=aCZICf8bZ z(t++OgRVT-!m9Q?py=1JbU$gP_3Hbm?>5yL)(LUYMURFj7rN?l>GAAWYDe7aYAJIG*45zVyUK+9Y zDD&o?z#iJZxKg({%+6wAIMsK!_I?0nL1O=`LKKH8c^0EoFpov6+xqCBlm9#DKp&>F zeeX>pSX+i|sC#3Kb{A0TDi4`-ShRt7s#AiaGr3OEnp#`^w>SEHirp^LQ^XB3%xkP%12#R8SYj4q(g(vK zIBAOnu>~6y#3uB%*u$U0WKx%ivJ|l#I4kCK?U+2xb4<%aS9hTg3r%GmrBvh~nIcnZrPO|gdGPS1 zbiTh9#HGLWLu>}J+|LihPbX-^uB}U)Idm-6#brvcrFuSAMC}0xUh3hkK9kLOtT3k$ zw&Jv{8KDq0eqp2+o-c0kxdHHr{vak8{z2WFfn@9lGc^zc0<}@C^RG-T<_4G0f#C6 z+-gVQ#N1x#`(aBtR_6x!HXe7R*mJhpBVq6Qq2Chb#1qRI&3}A$UQi{V%bhCno|2`) zZ2?MOfN0X}<&z;aw-M>f%iFib2{&Xat0>Unf46#V*CdUASk1W(PuH>c;5RC&tSC_G zENu@Wc51vEozOfF)};Mqgr(Vx(p0zHpu61rGTOr5WZeN=e@D%s+?-qJybJ?;(nIHJ zoeNwF@xuUyN~rJM+(Oc7OlTqj>^D(VY^zLX@UgOb=YlT@WXtF)S4ZrtmZhw$4E8Z= zL?5%}59oN9KPF2umSpu#)+r+=IDUXvtDViHdfPin9%CTa5NG{;A1Kgedl-j}V59{} zp<6n9`#!IpWT*oDx{Bv$Iay*0x9X{=(i3Q~#^HC^hsXSGD=hc5{aV|akCtZ%DPQ}X z7cV;#tdC?ac4(lt?MJfNgdo;&(rShrZDQ{dynI7bdQ}CtohjA5Z7bT2#&SDWQ=psD zAHR5o{Ppri*cI{f6ZFrYOMRXT&hpnR6eQm4QA}OqJCIpaqAGZf2^Lj^0=LAuV4n<> zb0Cs|a!WO@nOTb%tXR)@8^ncc{LX4rGcq-^087=b3`5C0+RoDJLOZQ!3~j`zXwx5v z@eGHk&Sv1U1vyb~q^^gLuaZ5hwG~|y+n2?2V(qFte*^7y;_hnVt#>Zy%SxaDm$|9U1Xhv_T#UKr z-r`Y;xt{MZ1nJm$xOY&#M|S$t`Zlm`U07T!n*Bs7Ybo>ftW6}NeWVwux*8>szSVyPnb@W2|3s^wSyvOVXbl%r7 z-HDm+k)$cuuo{xWaKq6as^^oaPRSU_IkPOi62*;71?%(EJ`{&U)@Ngs!t$|^P#5uU^ZV2Rzz+R z@TQ{1BxgHzqCIZ9!^V7Q3-szG)mtZB;8A$~U-?`+{nXE}cXOBF{aZ#PsB!c->qBb( zsag+4kzTq>Y${!xh8g~Bt>RA9Kw?_Y(d*=+)aPK8F}NA);lq1#XwB|Vk`F*9rXGxk z{>-iegR6g^H}3HvLu!ov%QK0vwP2ydAA z;n6T%$_PIOn=<~|1)z)c12GA6jG`koqL1mrUy`yR()Po6+t4z)Z8Q)6wlq|m2j!EB z(D@dJ&i@H?9$`y9hC0fGjBu+1@Zk}L`c^ATQVQ+89MgG$2d^3sgrvNajDdH|36HC8 zCe$JcZkoDmb_Zem{8{kPy0o+#uBXCnp}0L1cZA~3P}~)YyF+nLDDDl#eWAEN6c2>r z!B9LDiibn-NGKi+#bcp(JQPoa;>l1v6^f@r@k}V54aIYzcs>*_gyO|eycCL;L-9%| zUS&LO!OV2sn3=7X#B~qg`eXPKc!#@8!s%+}aF_M*qm>FAc}Oxc2Q*BvP9ErOfTyda z;2>=bmiXZ$+*PU+X;53h9c9n@u!omI02@-yALI)jD$y3Kk^9j0**UonJrQ4xY{$kV zxC5x!e%NMr;y?S|#p{!09De)hf>zB9??tiYeJFmwV?uxU0E*2YM6upOCa(quY3*_C5+lZXSwqCeqq~#}kw-WYL16auJGLD+z9YTDxj!321P&8z+T6qD8soFLD_LA#427f8BZ^sHeR-x&rU>9#T=*`GhIgc z$$Z9SSUpeWv(r#i^5h1w7R7dFpxEL}6n%N>c@FD-RCin>d+52M@8-Idgk6)qa^C^lRpYiH*6y;yA_%({$mn?pRVx!-psQev@ zKEFp%@dp$={)l3|KcU#{D-@f2jiTbuD9XNJ@fQ?*{>rPrp(y`5ipqbW=Ipwqn6x*~)Er z)gMLA0W1cxprxdII~Idb32O7i5EK>k zH4!`qqKq}ao1QvUv*nkI^Z!n3)J}9d8MbTq2ib`rTdrxICjRlX2>M?^wEs9DS zUn^&#C}VtDkNsI3fTH|B76+l|$qWQN4?)rAN4z=|MGqz~?@`a&!&x+-sGNnOcOwch z8%3^(SB#*~QR)$MQS@nMaU_b$qfq4Lv6#?(wT4$G z^VumZPDPPBjm7D_UCXO8Se(h*AEPKc3&qH@`Rp7%I~PUec_@0GkD}}X6crbu5Er4y zUCiPV7MHTP3`LKh@al3D~xAFFNUfsdsPTtR7*o}H(nlT3zQj&d9EreKOa1taSV_~=+`!N$^0mFGqe~vrN!VmSC2!Ph}dGw zJ}vELR8$%zisMSO$~MR+vR*s{*ST$ubCL*fV;d(Cco!o$$=P7q7Dc9@y){x2L6sR> zY^I`*b3kDSMPs0wi&h7k?S$O!h$|_)T!TWU*Ar4@p9_Y{`Ad}Hb2Sxo zl!nK%NeI#nK{MV1-P)Vl%qW#h07Mb`q6@nLb4N(PL*6^gehEdSTqH`R`5vxMal z*ffo_HhXa5;vt8=K7JAWZB|)$neYmE2y=6DG&i>Ona*s(;?{Y<#6&mJYXMXhq$Kv_ z)#$i$V`hrXsZdpdR||k*QCqUow?YmYO&hP%g8(r_&M}uN-Rlp}lpj z1kw?wf;v6Sz+lUc>L@r4gMy=Udp|7VpD-eFVv5KcZ+BwXFM&v$c^a?7q1_KUNt+}9CqO;N8NLzIAkipm^ z1!>JKJuW$%GsuzAHrT9lDpYZvo?PRRLUn;r%|}`R_q@>SFz9Q{9ME?u-TeFk=Ad9h zhZ^u0I(>obTPup7wBsNNwxa71y#GzKhdB&U7vbCU%sS1d z9_jNMR_P+Udv;ct9?*LA#iS^z51rR8N|jj^Y>@i&cIZH*EqcCGd|sdxpMxUDmZ?Y_ zALoe$^9*VY1hdR~r$Up#?UX%*+Aq?eDOVFzqwZ>Qa+IEJLn2i@^)l2`n|jDnt&wF2 zY3)wfb@RwCnq8s;b2Cp>(Vq0&IN5#IXNVc(Pqp<~d9iW8yx zYfxM%+%oG(>Ou3V%9@FokTL4_d3l5`bsQExeS(#|t6Y|f>$wcdWR+2(i?ox(k=nMO z2&jIX9dhQx{dlrSoFJ0NeSRFt4s9)}CO0!066sb3V(1 zM#x8f<1C4l8!EkRWw183q^s<$mPa>J72K{sVRQH*z@zKK7z;R-P?u1Z84hkq21sV^ z;a*-Ji)EMwaF5z|V0xA*#B$}#1-;lIn6MNaFuCowsR+U#jjBDok1;gbS{$!MXLgsXv#1qdZQ;P47VW}@RXd?EJ*@C*jO4fG>kP;luj@PrGIDF0JZ0it9d+}4=zEE-pIEmNe>YB8}kZ4PHmw}T7xVJaG)%qCp11S=u95q+Q2s^^!Ki zRHwRv!mBtJ9a@qpWT?>7@}mX?%NpAj%xhW@tjVcRv(w<(`IR&@{UJ`B$JD@a>O7`y zof9LIVppXbNez-YnRzyn6`BkLp44u>8c5hJh_{Zyv~e^P4p>`HT*SI8lGJ z&$Y5|`ebA2dvUvdIj-2t=CwKwMy8Zmt3SFM-IzaopP0S zzR`GDso_1KKfEgQO&@FN&5~aGL3@qIpPZ4$ z^_xMNZ$8kiaEMd&?;itxN!K(sqgdyY`rU&?-YtwLcP`wpP~(~UtNR@+V+>S%3;ek7 zlc)7h?&JodRqbe`b-`$7ruv}$*n9X^B*eCkk-9_H*d#p?`qIg}C{$e}eXN0y9x_zo&4ak0V zrL`6m^gq{MU7G#ssN*CsR5v7stksHv{jy(OqAOIZ^j_Uif89OxoVpQ7BwmQdxwN4T zpb2#gJ4cV(;)61e)vq41q1LpVtLN9cmHUgl`}H+|-NLrv!$~jUG|wiT`;C5gQ;~N+jd4@~D++{dh#T^oH)o95aG9^ve&UN@q2+wl*XBL1N=+ zy4uU*@hPbMQhzoRXsXdSS}wcmchif!n-;%Q719hLk@fdcKg?XO)}0vFuG?y9ZJN`x zxN)xP>xYFO4+$x@%KIau>y8;5T7s!vV=I?PS zKfX4)ksn_deJ~6k+z?$4#q~|NE?+1=zJ zc(#G=brf_`5$u4c>)TH`g*$o=+lci$c@LpFs0e<5hkc#T+t~gPJdXP=!&|T}upJLT z+1kJTR^*`K%L$S>{Fr7d_XTNSM^B=U>r4EYjhU8{4Mf!)o?abRaQcf5YRznCR;ks2 zVkCYl`|7kD^?r8Zrx_hce(XFc`72Pds7ZW65OZERr!@L=2A#)F8@S;QkBEL4eTy2@ z)I0YT@cE2lzy-8y9Ma;N`yog8mo|p!IpwPK6)kR&wEl4EGV(xy6SZRT1Bw1 z#K!y?^6$F@#FqbmjRSbz8eJ51#*75Nv6x1Yg-{W+cJMLgNHHhW=}ma@Nk!0>0T|Oa zchZaYZE;lDKt+$@MQPu&bM`&x=#mmX!_SsRKhp@&(URBiJA?vy|)9e%1bcqN$^!ru-k;_r-*aqLUs*l^2^9$zDAGnO=4R z!wP95sR)iqdyLVkHi~wCW%Q}(j-2Y!K0Y@37#l$|`4vHXMt5v@yD}o)SOg$m!`LQy zRcTo1s`S0-e)36X<*U5PHSU_qGCw^&`m_WHpWytIV@r1NfAgg1#IOFp?p8%`Vg|hR zWV-M#+WV6_sH!7?7OkA|D#XvMC9Nyh@AbXG8}~`k#!l|~JXFZT<%{)HLsa)v-d6;t zcF<=g?2q-bTAce1ih;?NaQ z^`>v`K<(-@u=KQ+@=exnijMip|JzPg$h?fj$gK?pjUpNf{(YB5OegsNQ3oo5Yof~i zo_6+LjjYJb0YN-<#I-3+Q*`=2X!^RSX&-Ald*9)xD*{HL+bl$*hTW8rUWrTuftl|j zAcdi>#LDf)O01eO^QH7#SDj57N&wPLB{rr}LpSE%cWHgy95t>h>v)EA^CgUoxduuB zqv^Rj{X_`aTt#qeMpfq1lKX`=yv2B1hm~jc>-LOKHD+jdb_lIxukMJdhUEkT2>L< z^MBi^ih$v0T!{V@bU2$8!F@$PO@gcF!0(SLOHQqxe0P3|R`x(qS*RGiB)@p0m!qS6m9OwsJVe2^RVwJY}xmmIOo1Xo|0C|d}_$* z`9)0*&r)M3+T*9aNz1Crue#VhM`*v-y0H$sgO9vr_DqTM=R?B3@383#dA1sXZueZ? zSU~mf{onid-3W>2x@n?1ghX-@m^I2DnGXs7-v2%CyU_FtDNUQINXbyIqehkpToEw8 z6@QqH2sR1q_!k}ayCQgL9h)nt~H#*rE*GIRF^rtC}+jA-xBhZQe=eYcP z&M`Zq-}9c|cL@@2cCs_N@h&y?vy{e4L9lKa>06y_T+ey8H2!wfxKB6z`}D?$1MV!x zPbz|UGOE^9Y4q`%>e39po6%UeRQ~g*az|?bXY=UsKm~<(J=phL557g*zgGi}A%`!# zCl$djOKi$+noG~W_bN_n>bJKw|?Zeu? zFQL~TmDuYNs`@yp3d_?W*8Y77Ree(8fJ>-~c|y~`?!(HzFQMvBOB`?)0PtCf0O$gq zex3mkHQ=bPl8f4vbN!V7k}op)ovhr3cZroVvuoN^me8*+qffgq70e==)~XF1m}GyO z(SrB0-(~#F=~zX;T(xY}d5n9fw$i5L4;lUUt1bbGf6S=Lo=f(+gsT3OQC0c?qrO_Q zT~XfkRaCj(FaJJ?l_m82>x|0NdtS7kf6f2`Kzw_AYr&x{$;jiLY6 zI*dkRJt>Ou|LUM}d@QT78*|lvoow*m-P#~xn>)KO{}Xip;mppb_6QBl?BwYF+d<{s z4$g18wZSfcGeCwXg3Cwsj=^bvVFZp&0$g;^eCGh}ce-1;nDe@b5n8L$9<1ANc_lOAMDl5`_Z(ggjLrYm->Tu1i(It`<$gQ?aX zNOsXi^)4^%J{>fl0X0BWZ-9!?+HUFMdL>S@Jtg+UXG5@rmAL-@6h0+%V1soWeZ~Zq zl{SGTbg*wm2mKY4MBpyar42J0^XJ~b@3=Ge7g-D3{tXs=2I(jPW*e>JFxG8S?P2`S zhq`ez)I*Ap;dETIzvwc3+oXf$Gay+aee0Gke&_!~7cp!yMN4FkpCBbq2OV-hwCR63 zJmRWjo)JH(2sVovvyqbc(AoQrS9l5QvR^lM2IEZI=v!d7p_e{{7*=V}+q|1QoISPn zd~}9r*x!L>X7HU7=4Oj-9_qTyjXkXYFW}fR0!Nm{MGvn8$Zi!?72#s4q?}HoOQ?M7 zu1p(JdPScN^w>tx`--4{#!&pBIrm5wRzhq3EE6KgF6itn6g;BJtyNxh4G-*M<49S! z?u~C7HE!dxPk#SrBj2vXk^7V0Enpwi#gTUl*avrU2}FQrStVLTJvP>*VOa@Pe=iM^$jcW!_B-p}+dW_pOK9=?C06aw7*y@wm(bKs z8BKMes-2^%{7-#=l+ddmWK`8r)m>=nhb1&c#PORhVH886st0=Ltv-z^ER}{=XH@2+ zmvdhc<_s7U<==P9$cAN%%%9qBX>53jBkLA0jwo?t-O|{| z5*p)T^TAreVjGnKwDhVvx%hS|q2GqKvvLfg)Rnz!M$dgjHe{m{mG4$U&$A)kNigkR z!bsRy_Q=p+sbJfq#KzE`BU~6TcA~L8OKhx5mG2c*9zi=6gY0{PtxJ`Ujw&DMfx*5n zjsR%6)HxYbBABufpc9RajT*xza)RCIjDRP5p52`LP0>vhkE-Ju*UkCDDyvGLCH;kN ztXsM>-s_I8Jc%R&y_rw`LOm%u`UzfhT_1h7bZ2j`JK3X82X@i1PV_1-eXLz*Y*LpS z^Nkx_XnY^9@oX^Kb~eN5ih^-pukzBt*oDR>ceyctb#|fgDPH5*VDxoqC9J%uUgf2O zu?vk&>vCg0Hg=)$>0aa6VDwSlzwZ)>o8dKII-q?N^1I{Tcd2`|UiY%0la9goJ=tWb zth~-^uItd~mhQ~#a(8^hOz#ecmjxZ1HsUqzg3$)7KhquEcL@{r_qx;dsp+VD{`)R< z_W-ZE+0e6%dxpu_@KqfsI#~yL&2=3*-O`T z+#%i8x%7!DiX}ht8qc1VE>wPK$(8$H>+F4(7UW@G_x|s&!XI9jx?k^gKYQx@<~n;{ z0umqYb>{y!EQ=z2L)6*Mz`@toxUPsro0}Ci=kNH6-TSJDPBhn;F*;uo^+#XAEYHrU z+LtA|P<2yA)pk_`N;iyRPKix*!>Epkn(~D&=N=~smGUzTz6*2$UwJufnoDfV>0{h@ z5ll}ubz~=-$|hkQB4@JkqcR%rmVo+sC05>PAmUu0PFB4RK*LEvQDZ(({QGXfyoDK! zVeZylHQka?xj&Ll&qxxp7Im_zb(o=KHS>El3CS^GCs<*g!|5|mMyU3t1P*Q+Y6 z^2H@qZa3ED?aq>n#!Bet(u_~j`&EPhRs_qUs@56la3WC$RjmV3RRk+a9I^v~is0zz zGv`P}V`4;rH>fxey?Rc~OJJ@hQ#X_U>Xqv-ff${3%X30-+d z_a%&VO$kkrq54gkap9$fUq#1ta*2&~sq#}wtUP@rMf-hf2UTaIM+q}Eg@k+uO+5eBVvjCH$Xu|MjbA;f*9g^VgZV3tQ?jGFTVF&>N z!QI{6U4py22MF#iKl1lC*EQF*^X**kcHKPv?CebU+h0{z%goO1H9>Xh%8R=H*VJvs zXagLv;o|UQ4;Sx9*Kj$>61~DVW%MZ?-DQyI487I00IYz!{~X@L35}@6_YnbfS|qw# zRM`cmcY_v(lwH(DWoL9#nKUhTQ4yKWif$_(vv#JhOyVTL68CT4o4`bA68!8)x3tj) z?w{00!c8nWH?p#3mbBQ!=S5a0wl#~d@O4*`*2~aZzVwl{&9&qq4S} z@;YCcGgK`~$7^`scs|08>zmloh;HWpN+;dW1m0bXv=KKq`l=drhwrujbsSaNaZ@C` z4gcTV#6?~Hc7sC@@0B`l@vv^&-3e`|V9eUBEfiLUj#;~{(uhjQw^tTLr_Akl|2?Ql z#x`Q*&L*fXm$Wbt+*JvyuwAu5Ug4OvyPLqoNUaOr(MKw(8?$y#B%D`PiN3c9y33=^ zTKwb9`oy8jI13wB#a5oAH($C}jI zvTqpt@f=<+zOU-)?cDF}a(857)Oy!?yP>qVTk*I-!=>K6dh~SfaKsHGy`6|~c^{M= zquX+5M(?_yT-H$=w^V0+GyDQ(Z&hv2wBlGjC)6IShXe858{NxQ>y-!PIvSl--@I%v z8r-X{EV@OxsPkNItTQ+$>ResxS*m%6{6#q)0Y%glAmue<9kK>B_z7PoS z-pv@be0&AvTs)I%w=S#3`i~T+s!8$jUE#9oxZZ>(xyo@_4iM5K@O9!gi{ksb*qrLn zUz27lmiyv1Wq;ux4p_(;|JgR z4rR;~0R}1x%&E;WJC-q1x}q3jU=Dh0fhp8XT2ix988ekD>W3S58-ietC>ynN88fvj ziZK>y0^f9qZ-NP_zDv3IG(qveCml8Kld$-%<>J%2;?gpKFKF$%m5Wd3ii;~@gm)z^ zzI(Yi9^RDN1KaC0=UGg~k#W&Czyv<1*CuKyF8T$=1io-;1QQh({T+tJg{0g3 z3=RVo4Fgq2ZR}1pVZ-iOEUOul$SRJvJ3T4uabAKAN%nb~1r1TapC zj}Pz8S|7L6aeqOl-=~b2B^@!VLtu+lv2R($Z0U&E9YTUV!vH9~rPXksBLt15K&=J* zoDL+tHyc}lBvyMwh5TF&Bq5)TLqTytKesonA!>WEpeGZ=JS`O8uiVJ0WukV(KV>Odv|znB9_$aM{n znY#p(L9#r~lIxbm15AD&BM-ekos(#-bC~TWdY7m|xX)qpzhJ07q}5a-Ap`5Lxu_a;*bh zQ5j3}i>%JEWOR>?@>r6Ui!bYnV=%y25*9y#6hER|e2^DoskA4;j~2=NCo1m8a*n2|C$GJlYOUfE$VcEKo@3b$tC$dFTZ>#(v>tGJ>v zT`A01%`r!nF{^eeDXS?kr2(*XX}cP%a0xROZVeQHBC|uSS1C}AE=yV6W8fIvCJ>Bs zQ`4&vvgTbQz~FX4fvH%W5jAVNqSA$N+n~S{YRXHqW6DOY<%&u(;r2lZLl$Pk%b2xM z)TKn#l#ifB;TtRH)ipo$Iiy=1zH+GQF7cpv%Er%PvTn-F+be9?#SV|*8 z{kSq>({#jU>4?qK5nH4qwoFHCeYU9(2HRYsIsWow6F(V8_M?(1Z|yNwNI zh{Iq2K$vAIS18+tAbo{WG3t{ml#kagt{}mv)b{cS^D^L1nm@pzK8{#PzLSnK$t|(_+4X+TZ+l5Y{-a`o)gQMUA&%# zj?snbC}U14V|KMsvzx<6Yi0k_-jU(6>}JwlyW8m5!(qb7%{O|h-r3Ve&0Y?}W~UYh zvArDzu5D=Yt_##!c`PJ@*ghQ7r)%aeFT@FEUyiA@IHd09Fh%4Xn48ym&FNM#<%I~D z`uBIm(T~I{ei<|)DPCH^9}rZYGdimtLdw?3=Sv6j;xk5mJatf7@q=A)8QLIT2DVHV zwfHm^e=cb9)Vo*xn6Z2NTLER?oKp5p=B{m|8rl=ZPxkoqVb+?vRmZ8OX{gJ0AdC z7Q3yUtrs}CRxGlX?O9r6olZu{3+zxAD%AQZsxDHfBm*x73iCfmauSt2PtM2@<1&E+!_L~F93JJnO~rW{hk4C zL!lyS`qHM3jGEg8l}AlKii(VyJAf*pCK|<}=Fav|tf}vcKt)E)-Qp`mO_t>Ldjys4 z_Io1?BrV9?eqVbi=Jxv|P?2tb04SMHurJ+3E>^?t!d7w*DlHq*7>``ZJ!FR(sZblG zsCrnTk_>zVsA46@RgvWvn?)XtP(@H|CHELm#Y%3?&{tI}Ir3;i_P9c=n1XsjeB~hZ zYdvt@5hb4}uS^trr6ba@qeHLY8y()5t|5_l0TagU?4W#e+Q8CuF$k9 zMRyX@zRwFgSfjJ6Kz9+)4_1nP6h-b;HGh?&yNRNo+5z1|KtHzwx|e`{0Z0Nen?m(| zc{VWX45V;Dz}CdSHbwQ4ueyea`-qy~fRH(~ot4$^Apl<$lcB6?u3(eSA0a5~qx>Sb zTO&v6KSRIZ%VMIbR)FG$*S`QNhSv$GCNjLon1@)txzdX zmuCMc15>{8nf(itjMzzE`po_VN`eyK(ev%s;l8&~S{ah>z`Fr70A$kz&hE$vg58V2 zSXgMt!n^;`2sfUlB6=!B-*yafzla#9XbUlhAY8lDv+Y6^?l-DREyCQ{OCh#z2Qg+k zBJXxG_ToE|vKS}^2J+3I2S{(uJDq^=P04mad6&bg3$DfYB?XkZix787(mU%@es=Uh zqA35CwLHs8LF6IShX^RYD6~+NuSP8t`+S7$p{^tgg zd=hroo+F97^IHi`Q1ak;Br3l=vO(pSur{dtQq~4Fsf+;bwcgKw+erKx* zO4b{ZEtszco1j`Wa7sI0O_j&D8=K(vgzr;kQ(J+iu>wtN1I3}i88u$yhO3jivx@B0(|B`J0ZkWb38Lc^S21=x*D%yXhvx%Pu8 zRRHo^R@qzth=Ra`R)5|nn>z%dWxSGlaWkYxd96XdOPI|QniTjXxD{Id4mtUyvus{~ z|5g-KS1#7hs8KDQK5MLZ40yCRWhFS(FB$+V^P|PnMb>1*_odAIRw|TPxxnZ5qU`6H)%qHr*S?{WptFuRluLc5w z&ApZ({5V6s#@0$m47>CEaxw` z)wBG*hga3Lt|h7-BfiSN9Rs(QP+dzcf_j{wHV^~TQTaoog{sb*C=v`3SCOjnhemBs z8`~MUi5+TFplC4A=hmJeEw`Ddaj*5XzL$T4$fg@_QK70L2-t|Qr5$Q3g~}JH?T!dr z+o84*RNnWJI?NC|)V6|huk|eHdC2@DxFW7Jsv;QJqm}tbaW<$ODhzB<)s8?Fb8`5Q zMCJU)E-ZGcKvk$>sGSumzetRUcD6v<#SXQrLUrC6m+7Hmt-uW2%?`CYP`HH7``|#l zD`w@2$6THy1M(gU)%j^er-Ae_m!}9~Pdmf*vP11%fod@{_pw9mt5Esfr*@-!KReX^ zK!ulS@{F!L#}}@HpC%!2002m(wRv%ap}aQVl7J4h0v%)pI@k(yh!yBiE6`z9pu?>| z89>E^nSV-9bdO@VE&smkGbECZ0IHbfG^*(TWz@3-HB_OJZW149hZ<&wItnO!)X+-z zWk0WUv=!)>Zb1Xe0}4|#yjxJ;IMA`(g2*GvOwn;xpb_1IB7Jmxx1dNLod6KJZz+zX z#}OaV-ypIAozyLe_=qVwxmytN5d)plEhy4Qr&@td>lPI0qtm+uMf&IrfarMCQ$AuS z{~{9m2K1R$ptAsy*~CS+thc*}fbZ#?H@k5;i z#7sL6Ad6NzKLlm@I@hlPdenM)<05}u>w?g@EMMoAP?5i`b)lWAi|kZgY^UlHJ5`t3 zsk+Qg)#XZ6erYckI`Xtfc%j1vlq-Oc53jTQlD=4=${hDd`S*}sApP!2JJeMQmERpG zRLO`*RJ}-4U9C{sz!p*0097pJxvERczIutMx;8=;K`{fb0}3NK)+kwihpyzSlgp~k zB&x1gs`5K29@SAB)HzXw@$@o5+>nmA5eQjyWjo+q$)K!k5c`R)n?z0SoBXy%7s?O3 zN0xsKi~U5`%|OY+8CibYql9|2jCzIm=#~i7WpSumfs$!F%Ws5=s#a&a+w4%cH%GNP zncvYI)vAGa0#(En?-?P_GeH z_g0`}TDYtnq6~GPLUlW+yiU~I4}>hlvbN^A2b!vI|J>QH!O4um-29*&>LG>7?>kHP zty0CNfsqOoy1CLohI$yNVxHrw$mGQ4xkn;Y5foGPC{V>bmw%{L@)eoq*!RmGYpN=G zo_jnU@dOaXc$9zgR5FOnbM#k-fRaZ^@K3QkXcu|@Bb>I$|9j1z0zl>w?0Z1;6Vy+K z0DO*91z?{hJp+IQ9ZabLut%_;1waN;m{JAUos2Tig$l6m0WCj*{d@=te9`rU33>RE zJz4rfXj0&l02KFl@rwY-;spa~muY_Ni+sHJC4eN*g8$CfN3J*6&k?X^mR<%(0*>B) zAm2cIgS6T!R-jh_k^t;{Xx)3M>r-U+1=jq}eKeH!DEBqJH;Ja#Do`?eMxtJ?K*T!2(n$Di2<4wjKqL%#-=Q5^OY$3|_;DX&(WEu|~&7>A$g- z{=rQ4aab}Kt+tfN%F3fvnevGVWi%)jE&XW-N@?lO0J3Q5&jGS%=`Tc)d#!hVw@RX~ zYodz#7R;A+sITl$UjtQ4R+Hgf$w1Oi**84CL185HiXgUI{TEQ#w}8l$o()!-q{~Ns zRpdK`nn$6E`6aIXzPCgDV2AqA4)v2A>SsIDFF+wc^C!Bd#JeIuB^bzK$n2rRUs0Go zrQ5X*CMfpE_HRv5(GUFo4us94YJVuyRCwoo6#b~$pD0xHxj6zv*E8tkJ5}rOX~A0Pl*9B10XCZgvS>LvJf4g#}|#tj{@6fSOaGitbx}*oZy1 z8HJ4H)sK{vVutSYuhw24X(Sq|T1I6u;S9@btpbB5bUC#Ed zK((l9Eaj`DYtXUnP~+I4##O#LnYJML!s0vRa%DU_)cAI&3G7gP>`)Whp(awOQ({~2 zUDARRD^zqayhl)z*r6s>s3Zd?vqMd;P)WX;LZOljoKm5ZR83`vnp&Zf44lReHLXG= z`D!|#ie+v7xn{8_lG{*Z6n&p`oayaQeeF>F>`?vfP&3$}W>l#BjV>Sw>SLm6VTC$91+|Dmoe_&-1}tPL-X z3~Wjrs8IPs&P8{wSU`S4`rxv5s6lq9!3uS-@>PX_Y=yj>9cpnPNrDy}L988+jrt5AoT{xMD?8NI3Z+}H z@KyN-IN2bx4N%3$XSxODGcPg^vit2r6iTbAK(S8&wpFMkRof|4lB(?$D&rwqc02Rc z4hnTdEQ+AptPk#_Q2N580>$ELXNAhY@mws`T14%lQ0FLLRiK!GyV{|4 zQ>Y{Zceg|Bp-@S_+7qbarqj8~?J~$j-jms@Jruio5zcpy+s#w&>{GUKrBe2_xv@u~vF#;b!BN_XcLQHLm$?t>L5X5gWAsKXR0 z$-u+yP?(hfCDp^^+d$_{n3LM8d?7@%xsoZ;=E*m!lU9qPFD zP;6`;(H@E!czk;(rs@Pc)QRn(n1Lq&Wi#WPtWZfa&M69&)SXXNsH8r4njPwNg-SB; z3_H}B3YFxmvlJ@Hz_S%9N!2-asB;x6$-wjMQ0FUDlCLfR%4Wv7usswTuP(AfUECgu zjqR7Thhhd^+8&Cjy37uBd3z{k;1%tmn1NTehhnO(vO`_n9*P-wO?xP2;I-|cn5ygS zP}jGIVg}xzQ2e%GOqA{GVmcg)JTO& z^3}tF!k5akyVU*m;^VWphddvtKoxf&<4}(()ZI!|7pnBg4SQbnF`(p!a2gEkLY1CX z`+|Iy`nWvK^`2`T!~TQh^Q~i;nipEfFf}iBgCUQ4e@%SzQtOy+2uVRMjr7P!5&?)rA?7}i1FX&uA5>$|OEn40&x!H{rd9pwGiF|31p&^m^x z`LJ~iQ!}a?Oyn^CQR^7iQXjXDVR7?G>lmhHbTf<_G~{0gE)-f!OzHS}E)O^zoCNhS;Z5_i}>bur4EOx$c9mCZ808Fu5 z_#k!)WXpvg6)KnltLJ!z`l&q>o0xxAsHBz0FA9~k^7vJu@}D&sqwr0P$FN>cR~P{jw`TvgVm^bGY6#O?o6D6Wd2ek7>B z6)H*9KMIwk>R+IWk%6N~T>V50{7<2{fds`uw3h#5u~U|>v!hk95Y2D36b2@#s@tjR z36xEUb|@70Rb+^cp-|jc1jRZ|FNI1{HKszXnn#)ZUP3X7#(lZ7w?eHPi(=oL8w;o+ zu702cayEWxkolQ(oUz+O{X$UVw1;A<#%&M9RE^gjim4jEJrq+l0Z>IB%zrqvJUdTV zYC#t5eH1GH;m{b=ucQShRH!6X6Dd@Zs)-dUN!26@m85D?h0@=TY4Ix&lPQ$`eoO_5 zJwrV?P{ntNj^`u8#HG0UjReCKcBm=sP*W+?39$zLP7Ivd4mFJ(YFazgbPDwX^%ePL z0`_I8=@sh5SkxcH?R^#MEs7#vK47Z)Db(AsDE1Yu{tA`ks~Hq3$yYNfRFbb|Qm73YBEw0(Phc6)MSB3n^5RfeR~ClBz}Q zP>U*5l7Wlap%z!DBwsC|P{ULolxt@)(X(akk_vTHEQS**`9&_kYHG= zJp=zGsI}WO@IQiD$IifY?F?Mc&cOBU4BWuZzzyvT+(=Mv;Ze_~)z@QI|8#M@$L#WZVGA- zpo-P?c(Ew9y51A0Vs#yjVyo-Dl!0T%s$#y{TNyY`EQ%Spk1{YC#SGk6sp_4gYCoka z8pTxY50p)a9-vT3A$p+lRdigj7CcD#DjLOnb+9rpDMSxZ21dsfGw@JlU^I#uc$iWZ z9al`%;Yw9BimA$gvI)^66e=l1hsL1FQ)(|Vr5*`XF(5ZlRYr|TP{V*K2IOc|Z-P2X zsfzA6EEtYfs-jUW7>)s|2!^CSI6MYbb~|gqW0kL(s4Ama3m&I@6^&voI6|q49vN5* z9wz9sX7U$BCe8_Y9}jHlRg-CBlHyItLToye08ewRWyqE z>NI6wlMszF@N{KhbX+k5&rk+NqnLqbDpk>O#Z;Z8R7Inhs0&z$ z>w{M)1N+6ISRcGn85oUXeefzf1FyC-@ESV!m18=r7 z@D@7*Z?!Y3V19P@OUcViB!Ooseq>dNcouZ=~Tcoseoqzuo=vs z6D_R`P~(tc^LeEzy3>tIP%i*wGeEtlR3!~iFWLF(Wu+>~SFhOl>Q$gp2B_Ck0k5Y5 z-be+!2|&v5@K!3|Z2*d!PUFX}WY`7oJK_xosb_s+QS5^ET`{XQ6uaPk&(6U2?F{_D z&cF}t3>;-=;74`_er#vpCw2yowlnZkI|DznGw^de1HZ5{@Jl-bzp^v%Yh~aBu|pqw zxaFG|RQW2EeQNow^3{Y~RT;%Twfs)`DjLN;wfsItRr!LKefaW2jH)t?_uS zf5!N#jAAYLSB$U9DAt1ii&0f}J8QweV^ozMmvS7V5(bYJzd^VOK5D&1H3#+*@HjU@)gJXg=wFJq?y#z_T?n+g~&6)=7(U;+SQ z?~U{!!$Y4`z=WxQi2$$}pe6>&X4ss>PSvD#swT5jHMyOtDS*Pf(C$z$Wh!8*RKV1! zfN4?z)20HZ10ZE6m_8NIHxvkR3Y3knX0!9v>~_AI z!_HT8+WBfOpkjv+_N~>qQvvg&0_IHx%$Ew7KNYY50O*o2Q!4w`>Vm0&g;D_v17I^i zEh1W48_Xvr!{(wuwLU;iLQsnVWivo6Zs)5d?0mJPov)U%^VQNor3_HZqyh${0tTi6 zmIWYXco>ul7%YJNR>?%MD;ahRZaJWe+e#C2RC#^HZow@tsvM-AO&W`0x8PO)s<@V% zgrmw!HFgVbMNyURtCj40wX_th$PzFJjOrTc0%J729Xs?vS6hMlk06a!-x3G5c! zTB(4wQvvIw0@h6htd|N{AAs2Th~0wQAQiA-Dqtf3FrB1#x{ZNyzdwYng%NmCvcB2` zD4P*@Q}Ix~fQ+7ECL^jgvommWplsZ}g`KJ`fwFP?RzRU^q`Q4{M+F zl#ScB1Iotj+uIqq15hbL5E`9c<^TL+pHYs2JGprN?2ZfWuP(St{U& zRKUxr?4Ccd90Y{|*jt0PHfI0>!n_+XfovLH)R2^rhYJ{DtHnpvfXh+=m!|@*NCjM(3b+aY3|}#;Yxe2?)v17MQUTWjU^AFs zCt6w?%-N^^*8|o1V9q}MzX2$l!Td%$U)^NqtDEh7b&H*^ZUri3fVwReaC<7?j#R*% z0Hh2LcclXE2B5fVn=E!E!*0Rd15|MfZgP$)udmpr|M!Yn4pPsij770qaQ6XKTuV;D zQRSr?y9IZ@ov$9S^VNfPzIw>cS0n9w^{}0<9hQS)Or7-H1)1oIOx#pV9J zUB1a`wHE)g{m%+@Uo7fF(tUqXsC!aSzbe%Iv8WG-s^9ETzbjOdfq&Sc{#2+WU;U*} zNe2E;p^{YnZHM|tp^^;z*ADfcLM8dChEXAX)XWE$3QXjvS?@*-!LU)YXE&J0QL_UW zBsZMYv!qdT424P>HG3&kQb>-eP)Tvr+YU9BLM0hEwjF95g-Y_(xC)hI;CKp^q-uOS z)C3BZWMCgV)PxF^NScYEy()d^a}NQEb3jNsxMGQcjl^UWLh-mFs2Pc>85Qac>UM%+2F|2VZ^oi#BC2Kvsu*NAio_KQhFKJfyPcp| zh|a1|-0hL5*%XSqouHV3vny1RujWvwBm?JEsHE9>E})9;%v+FzD4U(`)6TRFZ)UDO8ey3)`U)OU{4Ie{&8!5mG7yDlzSe5w zu0o%ZnxBYgRQZ%F$yaj`RU0W^{T8CSRFzS46V%2)Avs7r%MGj==;k4a zO_X6@YBl}=f~@?U_q+tPX?v*SiMuzmLv3z{+M+!a^VODisIA&VF}H8s9*P;bjU8%8 zdnjh$wm=o1jsB^keQcT5k1s8F4kaPFogHd>JJb$#s2%N4JK3RjwnOb=huT$8`NLs< zg>jXQ(^_2Z)*Mx9F+_K_L+xRQ+S3lT7f?v~{P%q5_F^g}4;ZjVjrJB*IqK0al&oGR zDoyV5kvVW5rRcFPO!d=U?~?&$U!aQ1YmJiC3%OFCpQzfeJ=6jOwSRjkrs{z9P)yZ< zKq2L=_jroi4^k-Y_KN58SPLF(hdM-|k_##WH?Hpo{dE< zL{LX7l#ccmRUM;H+U*sng^8-+3iVuyfyXM8Zovvwix5@E0fprB)H98$h;|mDBNR%z zy#mET^mv8RZf_BFfNf>RTnB$lB$aoDoNGFKox6- zq-Q!VQK+O(xi3|yBvqFwRFbO8fkJY@S05% z*zA0@LTObM6FpOPjY1vHRh92*e@5oPYwb|iwTJqgsJh+`b%R3b7OZePYrz{8>OAUp zGUF^tmbEu2)cLU}_F3-DcBoqvD#^fG?NGNVRFbc5SEwWd?@*{DRd?EPdy--8mBVlpX46JJd4@mE@~u73%&J zw?AixdfpE8f*tBbJJd^dsFxKgDHvW+sH9+c)eiNV9qM&E)EjoFH|px6T&e=3yzV7&sxo@e+AD5QMNpnX-bW?&Qj{}f95szub_3Z;Ejfnqnw z|4}IIs}@oJ0#%F*+Q168vxo8iYY)X9#;ZXQaILiwfqL4ZI_ywm*r9sap~kdB^|nKeWrrHu4mFNKC0!4Wt58W7apT#c##g8$ z11GRU^--uKUrh)U5*hl6K_>2T%83+84}BFVHqlS4PPNz^ws;0L?^;M`O1N$jdl7amdDoNE0cBmN@D#^f^6e`KUnH4HY z)hu?XSrsbDz}Xb)Dn7`RzfrXqc@SuJJJcL@s5$LWbJ?NhwnNQhhnm+8HJ=@7euX-g zhG;fnX-Zw3gy;h8p_U-11?^A^wTEH`F5Di98MsJ$D5h#rJJe$Bp_qY-w})Z|F3}!} zsanzwwN!g3X5iB8p_qZow1;A<2H2qnwufQ{E~`+-(ebJlcL^{^q4>~8Q0x+5upMeS zg-SATd4)Nx8tR8q9BYlm7-p^^+-U!jr=+(4m{RBdR7+DM_24BS|uk}fSb zu|sWYhuX{zwYeQ?3p>=7cBrlFP+Qxfwo$0F=~9h6Il%7L4pFFcVo_|Vwyhm%JB3Oz zaC?PHGH?flN>a6>9cm|qN-}U~g-SAT7llevwW}R!H-$a6_9cnLy zN-}V7g}Pb|G8G?GeL}vMx{n=dUpv%(Ko!q^T&4^xKD8`A`@tUn-ro*&fI?j!tBO6} zexM!dAfSqmWgk|mDuRK{I0q}#Be5tp4<4cnJW-)qY{5en>ZDi{bNgWmm89x$J5;7n zNd_KahZ?F-NxnML4mHdUb(BISx&3H6)G>Cb;XoB5!%)?6Dnyg-TL&vK{Iag-SB;R6EpZ3YFxm(}BX~x=h{u*sT9I z3(bFH>MOEHJEIapzEZ~^XSNF2mnb=_5<-5P{Tl)~yHyA?=bTDNq)*Om6~cUSUL_>b zC+BmB`xV;Wt;Na(9ONO9ez~w!2=mKD98zr(i((~e2ZH`lfUV!pYq zRkPU8d3~!8=9?SZF^T!+Mu3V{YSOcHH!0MmYLzP8BJy+co9$4yC{&Vxw<=VUfww7C zlB(P7PP0)$OYNbUfiD9kmqOWPeAO5CVbLpg zs8BFMe>`<=*RV=n2R=%pZCCu*QzM)W$#G=^UKSBX5c67 zp_qZA+e0x`pW2~5YY)W?{2Zua6xGjP$bAO#ycm1_;tM;}mv*SHfRcZ^*mZYNZXyq_ z<$rFtt|7U95Irp!Kfi7jGChHO(<+21`LbcEXYrSIe|O&a>=D%60^e{LL!`lSjbF&wArSD=cX-sIPO%U?SDm0ZC7 zW{3LS4)uo}>Q6h=Uv{Yf*`fZnL;Yii`nNq4`(ny}?V;GWNox32zScVqL*+m4*E)(B zShrKvvpp13)nSJkqdgRJdoP7*@(+mOzP~u8Lh(^F@^hKqcBruwD#^gH6)MTVaTF>^ z)wp)3@f0e_!0{C-$-oH|DoIrzJJf^{P99r)q;x6)u))ovW)3x$eq8ws(z!kM8Tl*&C(;HcAC-oC??^6|iY4U^4)a(2u%n zg`T7pHctg?kqX!n04#~ChJsq@^Zn(BF&eut+RwMWSj)ppaTatwc~eDFYXXRmFU@ zvodhOSQImG7iC~HiW#`8QZ-+Ss@;^TXcSYmJ5V+ux`#p~h3KBjS4kndm-1CKiur19 zWnfZ>?xPHhjw=?T`ziyYQOv;ol&a{sVygC6s-jU$)d4`+gy?|^l@y`}#h}Vl>dIv3 zI~b_q-q)ghWGJInA*e%uLdpl^Xw<3%b*NGm-Emkj9Hvx7qgXH;4pb2gNqsPjL6zOk zTJQ+vtA$cpaH#TCG>Wz0kxEtc$iP}~m{JvuVl8--QWZTiFjYq@RnaJ>>KLGkxJp{8 z4Ogh7LFQQHtLToye07}iRWyqEYJ@T{sSh5n42+H|X5b0Rz-SaR@I<95II8MFGB6so20@)>XW;2}2A*MO;F)#?o@Hm? z*>(n=V`t#Gb_SkjXW;pQ%CG1L$99}GNwi-e23DcU%MW&Y=R%;0+dIo~Rb>>ry>k&z zW4V+sAe*4dgUnjQz>DpCb%~v?F17R3Wp=*0+|E~5*!k*8J6~O8=c}tj16}87`3Czn zseo%!0oSDhu1^KrkP5gF03-}w-L(R{!G2RJ;O11oEg>LF8q9A6s<>C*1XUh^*CxZ} zZ9ug?n6E=nw*zG}nBQUNt2^y{b(fv5?zZ#QJ)wc!bq)3j;JvAU`%(e-rve@T0IA*K z;lWhELjV+)ON;SEQF$f9E|*3ERotLkJQl?+mmU_g^7U0Tid`-}VrSr^b_PCXXW-*@ z20meD;FER+K4oX%({=_vV`t#Ab_PCYXW;X82EJft;EQ$!zGP?M%gVqdVuwEVvFs}` zsPY<#-EV(Y`D#h7s*GZvn7pQZ6^&Y#EVo`)s+Qua$}-Hw7a_?rBOT9%^9==Dr_vEiVp>vpvnerObi@bROP+9iGgJl^VK+Zz8Y6l zrTc0;J70}2s?vQmft|1Vh^lm7O=#zLO^K@M?F{TIsC2jY z6I8m}`vYa;_8EY(ar=yR2F@g?bhpnesC2i_0+fy0X9dc}?X%e#ID4q7o!M%RRKT36 zfVolubEg94Nd?RcK+0@2Un*e!RKNlNpr_>hcSXL)FE6JzBZK*Zp_Z%(s(ih`?h-Eq z6jDAEti)B7QS2`9!oZBv4XSM5=ET57fU@z`qCiRHr1@$wppepiwKy;~zFGn(8(%F6 zl#Q>J0tzYJS4#t9DXQ3m4QNPt<$l)#H#>f)9F?P%Eni#0cGQ>)qz4v_thG}*!XJA z(7^7x1{Y zkkWm%1u!pg|tCEgV%o1U^8P^}LI>@M-{b_VVN6jHj|_q0>B7f?2C z-y0|!x9?+T;J!d1rMrDUJ5~DwW#je(fUfp!KS6sqcOoMf}r!Kr{lQUQmi0uDvHPd^KFDYUZmFiuvkTJ5|RC zDsRDmT}X8On7{aHj1eVOYAqj?y6lz2Y>SBe8 z4pC;{C3dJw6)MTV%M>cfz{?dXN!1m0s4EpJ$-t|C!gAVe_3RcESMp!RYJEz}kFCg> z;p+BKTNBhZ%D`)sDp`JHlay4k5WQBRu2ZP7{bHM-wjrvnQ>YtaQB2kKRVeu%>*f3W zLx`#y6zZlFRX0|lT2plsP>3t1r=DG_R8_R#dt~UlS)s01sEQWcmiX!xg}N~o#Z=u| zg=+4r?TD(|6zb*_Rkv56T2plgP`C->^whIYv?`Ax|LKqY|G_&IYIGA+X??~1|KMFf z761F}Q-vzxs(fMcEs3kU73#BC6#L(2_b617s(TfxnW~bnn5z4LvT4El6)LF(A5f^I zxOz~bl2knelucZXRH$YxSh~H#TJT|oN{XvT6sno3sJMC*D4V!?Orerm@NuAumCUWG zJGZ!!dBP6$q#f!hg}N=)K(@Ym+79)M9qL)2into844g=2obrEUW0y&n0+U%jDFNxpg$D4S9AEj!fP3U#}3d&St!hQ4>~Q19BI-czWg$?JVP)CUTceijkZ(ushz6N>{NYjr|JtkRbSev`bw$VFARp-IR2JZ zWL$l%RP9euk#Y5novLr`RDEZs>U%p?KiH}I(N5J*Kw)!XpntiiJlfT_CpW5o20(7= z1+i4G4VC5jxTWE42Lk#f1VK?p=YLqO*G_E?+L3^M1xTLOTRa3+DB6jDegjAb;J~yF zF)f%0>N^v_?;#*CsY6T(0lN^uAE8gO?=a7JuTTxU62zY&A~2#}bI*&piK=&&mD^`G z0{Sa7CIHoH#d^66+MR&@7b*(8Qm+*kbY;*U1oSsRw4o~$?MXoY03;U!$~0L>5+ChF zK>voOp;HtwT%m|{hW|nkOe{bZK4P7rhA-fVkCq5Q6^dAA$iK-W{e1pN5Hqa~MFN^H z62wgF2~ba$T(_v>Aw%z@QB?tX7`f@&0g&|bY&I1D6<*q#1i%=faoOy#sC@{kSBOf9 zr7=U0ilqwUn8SMmWD!ea0VIoLv|O!os2|;C-}HTiGcY*5>m zIC-296vWWTDiDjIaREZ7MKA{AbS)dF`Rp}}m^PjjXncUMwW8=qqG$quWOVF1no~0O#~2nJ``m?gzZ+P=>US7IMkH=7>i=& zO`=dg#iE#jlPUv$jzuv8Cj$xtnuDkauk~);dRvm#n;ak(m{p*y31|v{WE2QZs{(CK zKvN3HnHQMW+^hph08C{8nc4y}jRj;{3&?a9km&`|7j=`!eF36@SFy}vBVs=* zP=71X3|2mx(F!yZK(fqBS-#91g4FV*#ij5p09h;9ucGT5?@3YQ0}xPzrXDy%@Uj|x|?Q?;T}wG9>%{?@^+GMj`qz?qtr z6e7v6l@)5^Kuy~vW#CFw z)rd0cOrmP_2o&)ZL#+XnEV{A=RsIu*6U(aDeUUWB2o&)Zo1nG>s)(irRjo}>+Y1WOl&uW|Tb-hI z0HTPeb*PUbr>Gs3kCNhPCsCCiPdi7TBI9WnWne?gwKh8K8i9(8r`>?EiKpEK)qXtf z0fbFF?WugUNf?@~j!%1usyv=H3Q?_&PkTq8BI9WvW#G!8s*&=r3>lw}Aq(hzBTyus z7-~PDig@Cx$O3wAqH2Gj@PU~#t)8s{17&;~S?e6?!X@-jvYIqSfrbH8bc)4-P^^5q?iix! zC_B{A3iZ45mfXK_J*;zn4LitiqUIPNq=(HK06GYOJy10~6>w|_$Yz9Vdv|`K)xk6z zON=-!-47$u5yyvy%n`VVTF87HJ`I8ii6&yndv7674!5k$jDq9F!wJOP|6 z3S2|hXY2ApWj|qobqYW-tpZe-;y>pMO*w%mITZkGP?F7zz$y@AGCh$XP6I-E2Q>JB zsNPZU+4O;^lL+W^fI?$rM5_X^2UyPls8}J)qKqPbVJn0)fhhbkQ;6t@^vhX5h+pP) z`{EZFcGyS9ClkM%EuffiWAS(n+td0$phZx(Xl}f3k%!gcZhBJalv_G4ARR)y@Lwnh>yHmy(v} zh-*X8LIJ31P(6*9bR9s&V)f4;s@-==nm;pnIze3@qJWGU=-HPFZU{jbN@76l8TT6j z0sy09%J(I13KgZ8c5?_)rd5O@Gwl{D({2qF1wN{r)6O8xf14HPc7QOo^Kz9O!A*87ya+BjMqUf$}6-AnMcekKO)9wKXlVdBUjUbcb zy;eTDuUpe1eRO}fphzD*VCAC+t$g&5fH1ISbE-M5V$^1H+Q#NY=W+<$L8ymn~3V2|+2h(_aNhu1#VUv1R;gAt;y*=r_yH zCM%QILz9B<*;Bwd1n@=(2o$vJ+&4oIZao#N|B4ZaEs@^>NLK&ZUqPp+)Wp6o{Weh2 zPTAand6oT(O_J}}q29Gay$6(ZjljH?fB5135TsgfX!EN{)_NZRB&`<&WThh3b{~d{ zGW~_{iikRw#P}$niZB=)_^I-0iG{&O3N@=jRjAsPth_%~sQF@1Ow}iLsL^()Pwh~j z*`YqSLwx~MtCKgo2>TKs>BiYoDikV~g6yNmuk27?E7Sm`sv_2zs&DL2-vWhO=WeTK zgOsWYU!6zBh3`ZaLA7Y$_jafs>`*`2p?S-P4S3A^i6{r^D>UTTT z9}2a!>NqW``qK{em!Q)7;Q#DUe+w#)tE6W^{;5E<==OgrP!&TT8<792K((l-Q`VG~q^Du${nRZGN1J45xfLv<+BB1%<@z8b?0)e9&rKk`1ftWs6+ z`38%tG3`|KwnL3ofod_X#Q^ug8M?1H*-!Sm)?_Gfu^tm zO=$(1$_g~K6=)hO(6m;d>8wE0TY>sof%;j2`dfi!uma6!1)9kUG&4Z*#Df}-{QKbr)oZh+KaAr$zvVtd$sceB@vbFu29nN zo-2Rr|6&qT3q+us@U%}EFmZd zQ47?n;rDW4-jV=WjN?l+Q`GA4yR?;}WkOJvG!hI5jY}H|1}fB^ItctHpphfNvI^DK zNH9ozls*y+jzC3@1j~tG=_A4Nq6!@)+grI?MuJFHD~PHb#ar&V@)&*v>2)hcphyrf z)Jh7~RuHT#KFZy_i}F#$bZ`t=6RZ+}BJO6WRmHGe)lO6unGTL5?p_Tja;IsBswddl z$ET}{c?f|(5q$_|XQE_{5P;jD{@E1@*o6Sr6t6%*d;cS1tq>6y;U0Qv?SDk99U2pW zDxY=Oofx%Fs3`DC7>xGK4`D2Y^kG-#7fszr3EZ!Mv zg9=oIfef`FP%`glGsGImo($Wl0##ukLv37vsxXkDHUUa5zQ*tBX`_0K-~2hFD@iD9 z3XlvQ*!SQ29NlBw@@ji1851|NQnGofk}X0d*?(?emGP(MR*_A=gL)S+YD`?pLp$@P^9cYI-C`5&m zeARcgS^FIfkPODLAQtI|grNAZqn%Ht_(MbE8c-Fh%?k+XFojC`82fNLRAz@d0w`&} zw5yn*6{rfgvrCU7D^L}yP=*?&e3f(+bCezGXgky~;;VeN$!|IM|IiWs|HO{`Uv9d! zPW~%4y?fQKBGEn^C|t*2>4?r;{C*Ajsh6t>;89@6N|LMtga9! znRN|OHKIM#wFGs1g@F|@ejP!bpirTKm5-2IPf#Z+14Fl0hQJL3by9n(ZX~Fa6)IF! zY2Zx+bqY|jPVX)-HzUz>DgfAA;cg>)8v-~D0QvrC7TsDm6Jt&Xs#qR&sL1Ym!m$+D ztizrWqVV0ncDu-#Aqd|_i~%u4X8{!63h|&(RrgU3BMv`1RFr8iRrG(R=^UWK=<%A| zPn@@Qm3MAv+_(xzP z@BCgE0&p`;?t!_9C%>?}c5O5o5iOZS*Mhbxa_!a9xmxrL>_U32-g-RIUiroIP zFGg1No7;&=S6YFt0!Z%IX8AwDl)hYbck&LR>FNqpMZg_Rn*17t%Ky`6jH)|{s%sT0 z$-wJ?!X{ImXsT+xt%-Tp17tH_-2jwy4$R}Csp^>o_9@$q07)MYK~=`F8+SJ~ddUx4 zTM8)bB-<13+}s4v@_)6v1)w6fw+fa8J&J$TK|Tb!i$u|_Koy_dY#pG+V8a-Da_csQ z$p6uUv{mub*TPcM-|NFy`)u6so~6zbYk$-A5v5 zr1DXCX+nSZ{C|`QJS8ez@%n59By&F?S%6AcpAQkx(*Q~5 z>{63e-s@otsAm9@*jXS@RI9ii9!V5E8=8inwDjXn_>@S=w1)}kxlmEV)n|n!cJ=u@ zP{p|8CW%5-t=3UEJik2`_OVBZsuu)>C0#ZoK=qLSpT{l^9wn$36>8f6MgJ8aL%gIA z2Ly;7RS$GB)XP9gB;nV&WWJE)3NwqX>R+(}y=nz|4Iqi_l)>Y5fG~Ktt*-7swH)1V zgqpH2Br8!Yy59r}O^=Xlc_HqG3ins9b&iGZsjPbTmYC_F_0De}_+aQ!lP93bGWanP z<8KQp?=JZ>>_uG3LyKf}#MZFyDAe{rtam*QPf%>;e^;TnDzeaGs@_v5u8N?Ts`nKt zf55ZkE3&jDc$7&`0hZvEi6qrhkgU7UTM7R-n%tP4l;K4-wPCIhfrP z`yv(aB>?CY7?pCfI)9q@5O&AmZE_Xz6$<4erUI1iZ}#Zf+vP%X>&$#?{kpNFZ`a~x z2Wi(b<(pizHy|4`?BDgSwNXB@ht6cv^|wHYFYx@8j5)17fAyVcLhz?7AilQ%jaln= zulon8-nJ>-D>@T49K#0(NU(cS|0?GOyZ0ERaBhl*b8GtdIOqG6+v{X*?_Y6lvixXQ zeUtceD1-X(Yb$t#Cafp$FtohKD~{pc$zWf~{O$IqbqVL@bP4rfllsEE@SyNQzOZoY zd6)bEQ`GT^J0^9!;Ll4vsH+`2`nqzVwr7Gm`ni4KL(8N7oal_P;~rNATUf^}o&!7Y z&Chn#gZi%V=dlmpiv}>TK*TGKHMXO)lju9kCBlppMp_y-)E54DE=M43f{{J;DBesPhP z#nmu)QZM?9@V|Ha*d#xAQ@aEm*cV;MgJWUcc#rW!ScpGpMf+hx`3YT;x{)7#l>9fk zedLk+DAP*af4ThAxCGx^;Zn%L{!cF9JnTl@-}(2*f2T`fe(3(ppU3g;?0(nh1?y&) z8ts17pO?B3=c4sKw;$Gx{U`l->^JtcD}8>ZYqQ`Sv>*>Q*ef>RnD_zb5QmGoggiKh zF*qzYxjzT(*iQEEVPhC4#|6hFw!j?bk0Wp9(p3IE^ljpje}puz6a5!uq%QPdyl<>) z_uzO~*N*-;t7}ttPU@P#?Qib$!d8r@at`%P?9YLX_v`pq=n((l_-es%yoXJAUBSQN z{YEaK47LF-iT%P}(j7w?uqSc}8{RMMU&VI3;yC)RrHneimKwiuyNn3Hijv@Z84!95hJ$h=#uI7}!$oGPjSi zNPS#F8KetblH+0r%3qrQ_|f~}cP7%!n2;{o!I;}SOPqdh`Bhr9QU zeB?vi;<&`!bZ#Hzz(s$-hIN%})4M&KM_JK{b2t``sbFsH5?;Z2*(GckH?g5S{E746 zAg%A;Gc72Oyy)}Tu)nf@MOnOG-oFYHbwJkue;hhqaS2OOV~s|j>GSG6^^{h zG3Ws2Uzf0f^MT(N4)Xlwk6~ZxM}Cy;>tAsk@54R@9_BtAmp&$KILaM^4xB^2PyKt? zB&@gGKDK6MK6B^5z#NPX`kwXs!oa+P4f&u&Y<@UD+MNBlFC*g@%Aw8iiqzI zf^#x2pW1H>ZXAP7Y^Xbo;r;w^X$KisQRkK}$vlI)clLQ<54P?7Ya??jf1EKfj|mf;#_?lq zUl#Sh;rG!t*l?^d|MJ1Pcl^HONBxcY7Z38k*^nPGG`~LvZLn)@{~mQ?-Goi}@X5^n zn6$CHTe0LqJPU%P!UL{m6#obHZe10Ne~`_LuiM|qTi|HAT_doKycWnW(5OK951 zB^g7J?`fBWTXXx5`}d-2lzSigc0Kn#?CbaV{LqDThkuVU;vaBt3XY3!aQqs7T=7E;0R6`{T$XYro0ezUaref^woCniyxS;JDO_ys#7b!9Ua`(T{V8nHc@Z z^P|t(=r{C#oCp6_mvBDR|A~7qdhm+=kJm=d+re?k4~?(-Gn}B>^uAT^AdY|`1j&J;p`L~2M_tt zc0>Ge)QP&J-CFHCYkN*(y{iWNv)w+`=91`# zZQ(i#afY@Ne}sJ>y#6i;KlJ}J{y2^y&KmVM#xLf7#tG+#P(SR(d+@Jz2^wJoUU3dd zH1~CTQWkUA1};tEl4wF1oX0pU$Hi_O$2cs<(a%s0WtIz$3m>l-hmjxJzIO?E@gCba zE@50mJ{*^NL@WA8$ig@*tUKL4>PG*=hVnDIg!AH$zWzPxzRo4&k^Hz0ime;>oxp7j!7Sra|`)AI4AKX=Ne-;W(?le^F;UUzE0S=olBw%uQ&K}k~i!N z$lo{)~JBVr(o;e*|Ksej6by7%$tL~D$Vn2Q^2+}d+s zBVrGm*ob|M<9LtM7<j!8#gsz!#yWKm2>xnYjeJ zz=N$@xCEWpQ0KQUp{&&PrGF1*Sl1`P@vtu3N5Xqn*Jkdx)CC^eL+nES7hFQwP(L(1 z6&x3zqTD0FapAxZ_xt0pZwHs48yjqb&yg2g(T#IB2DWgZ;aZoF2b>RG!iMn~8_Hkm z63&B*{1^K7$PYhaLp)%^u~zCH;qpt}Kj(xl7V19IpO?B15Aq}4!@A+yR_fj*V2$#u z(C#7rywtsAkpDZMU+hNT-O!(p@%d^2>z4)=$}i{7OWgy5{OGr#-N=uACG9M)$b)w7 z>tDgb`w9Fj+7j(0W4+8V64RsHIpjeZ9!y8N?G96S{;AS`oV_BYN;2 zbu{XcIBmwp+!|^@|HnGKS^hQMInjZ-zVZ2?snKTx+%aepjVKptM7^0y@MSo!NEz59 zW#K!l5l|2MC|=L(!ayTyKMEkk^oYWm^7du1Sa13n)R;Ycr=ivOG{(Pt*^XE|xF^gBx zfcVFIB={2c$vKH{(YKpB16xqf_Ia+(yeKO%CwaGV$0YB~LEg?1U42LLZxH0i{3AN> z+Q?ot$a}ln4>$0RbqRihuEur6p20cTAsh0~7Mw$!n47Wv=MrLJZkJ#a>VR*g-$NtH z<2d41-h;n_OENDumXYI)Wd^%4{aliI5I5q>72Q6@4s5Uw46&7IMjp|O^P%Qu^)KP_ zN&P7EgG=xu>{-$!sUI5PBe5N?pSpy+GL|4taU5mOatRyGV}qaGb_wrcEAqYW-{V}U z??rzc9KucOxsFSyA3U(|iVeqLvz$X-*>G%P ze-8TLt1DbWdDJKU9a=96jw2uP zXg8_%SGN!QXZ5+U-5}*ZWyK#S z`{T%So=ea-sY}?v9qtm!iC>5L_l{$UnDBlK)Y+7v_J+ zzeoO?Tta@a3uRVuNwhb%X=B@O`s1hr`(Yi}ztEq@zLZ1VsJ9j09q&2J zcZhrNL*K!_p)U^c@1gT{mykd7-9G-jv=!!mlt+HV5b}%f;Da4p!g(C;&Ud)S!+f`a zKaM(Xaj7xx*6`<1M~d&3@*L(n#5?$*@8k>BT zf7&IS!+xV5`nqG#hI5T^8EPBbokv_t9Uu8J^SM{4=O%w%v|i`mOB{`I@1a|KG1|YM z-@OVW?Bm_(L0pKQ_uM{g2=$Ec=S9yk{(Un&YrFHJ1$sjJp?QB_9zOn`OQqUd32FC=V85 ztC_yWb;6}SFUo~=p6}no2cukqF7zSs!Rc-<%zv_f-^e-69|z}mmqHF$7yDy4j@Uza zZ1AOw^ElTyw=|9od$>H%gL<%z0%u{Du%Y}8E`@rB`1i>Fs7uJdh)a?m{RtXk>R!v` zle$OxGGW~-`SXYg^daO08+A_O5{@J8F~-Yr>1#MHu>`H~C$>dhlH>EaeX0L(w-3!? z3-Y$&N33y$g*a^VBjO$BrS6G>{15y5i@8^9DBDWi|GE6I7j{1A66^^5i1-QpfxapE zAMyDYcdyu>ua&w-x%|Sq%I!DW{gyv3cE1+nzs~1h!o6aH{y{FGEm{1a&2bJajGHO( zaH1=ZEsO{Bf3XGY`9?op;m?aLDfJ)kSdI0c;Q8>wr7od<@eRhoR@&ttmtSmw?#6b( z*p2gI%WgsbYkYo*N6g*Z`SYw@8po7P0v5)@MnA6O&r3T_?%qrP4f{3bNI8x?;NU&l zUXJ4x`~u}jF0^O%PQ`u8{&>Oor| zAC8B5FuqHD+qnIuT*7vgOU>$-)twVoSV#ZhcvuJWNF7_deW~MUx8JM|v@fe8Tt9?$ zz%Hp{U$?)sOYjMfedZG8K=|}xm*7tsGf-|$m%zpGNnMf+Wq0-Oqz&+j4d>SLuQ-Nw z49~R^?+?1NqHm?;E+x`s0j? zwr=EtDSA=Q{4O=>#d*XrjziyYm#{7CU$Kv|1o^-aJ8>MxruDBl*XXaw+%d5W=VR6^ zU%PzR2Dt=(pd4OB->YsP+hG5S^MAX9F--FP;orl5h&>#~xbTxp$cN*i6*he1kHdbf zW3a(4Y{)y>C6r?}z8{=x^vxUo9O{p?|38-(b)tSL_n6y9{m_^Bw}Jyg5y#j@*nGu zv-&XJVO!3>V*gN=nzhY-!8x%NWl;a_{+#$YCN>c#*ao>IaL|WPPPEVM_8aTNdCb#d6WRmY zvi=qOeO;GvGj zc0k`0ABcA7L4M4Cq6cLqF2Kh;jrPHK+1n-Lhn~#8;yuQpH(f&h6@eMv&*d?hKW1ZM4^-BIn+&SdOdO`Bz`UU5q3u7@}v7xNA zCv3rc^nYPJbbs`^Zg>Gy(HiLh~ zxkg`thdiPId2kFdhU1w_XeTgFaS7W%|BAdAKXC0N<$v_=S$Xuo#`3Lbd#8eZ8ezZS z^NTjr53Nkwa}DL8vlVT(Rj|)&V8d@$`TU~ovWoK0H$iKWx!nxP&!zPv= z*GuK$7s}nKHE&k>ps8efEM)sP{(lpUi<-jr*~;+a6D`a^na8` zzVlte*5AKkAM=v<8#eCY67qvD@dbbE6dcDKBe66jIF33{4!q6%aU8?^hU2(y!-oC! zT@t(Sy0(9hb0{O*s{S~R-S3a$m~4am9yCf@;~X^X=wES8Y>{)VtV8B-<)IN8u679; z!?nN+?!DN8deI(|A8~~ItGR>?TG0P-9{Y{!kZIg8X%CD6=x=xr2F{7!QC^OR?Sb<+ z4y`A-gl&LJa{LdsKbA{4f00Yj5ZdyCdyn&yKc)T?9H+5<^a-i|GPjTVL*KmQ&*L~W z$_ASd`*_8<#x>MD!8yzo$b${}aczZHvFR?i4-N3C#0B!>`X9$-EXmxyte?Jc`^Z1g zC2Yulg-fBYF7fXhxflbRaldruLN3^753y79i7he?!4_y3<`URoh}|fAm_H65!spl~ z_OB?npGzo*eJLk(?C#G=9Wk*6JFuaTOF3NsqYh~J)Fo`Q_*dw~{Ezd5 z9G@U~56%KEt?rVP8SM6@js@NR8ZKdjU0824^CSE!bs#V1e{fKD7+Z4&$Hh-5H?uzu zO>et|E%Yzq20XAs9?CYxBg#qLVIAZ7<18M(a_69Rpi8o$E~!&EIEOm_a!KX|m<)KGe~u0pqBg>n^TeaCuQrV|zU1kE8xiT*4OmeWZJj za)=Mqg*l^q=?>;$Xd}EC{_F8kz^31Z< z-tUQpea;QCIcH#@zVN{`NyNxK>^N+P?|^Ct`{>)wbDA@9Pkp4db8K74fMM-;VyEW1 z&9@Qw@d1|6B4W+o6HjQ(KK}8`yU6mKDdaa0F~Gw6-DZ|Mp$a;LF;>H#+Ep+qf3j%zHJLe4Ay=Cuofi`VD@6k-stC z*BrZRi;U?I&5(BtLt@>e|BCjiej99iPQ&&G4Ys!rd1KpV8v3sled23_jq~4C-aah0 zsnHrCZ)~egL;v-nPY&B)L$)hyoI&j6n$lajrkwq*^xr7@#M1^FxuI8@`h{%6@b>n8nIi#{<-2zhGI-C5xGZdceo)?USSTgV&RP1DeSvq7KxhBF5?&M;2~yn45s zCmz_48z90bJ;*?Bw1|D?JUy`WEs_1y9OQQdGRKI}Csr`vhx`995q$jbCxZV|5d)ut zMeM_$RfLS~tcqi5=em$TZ0h4mof!kY87X?DXI`IP}*`c2)?xO*n>xoN<6<@sKwTe*dHEd=M|Z z`4d0ag7c3&a=gbFi^UTgy#LuJW@Pekj`2+&kYC$+QFHV+5;2&+C&C7{IIlbzJh=zG zm;08z7t-E>n&Xc_?Vk}@&warjb9&i4=I$M^fSvc_Q=)}L+>6L!3!BLNKx9AJ7INf; zXSGGH!Dm|&Lk3&s^Zkz>h&v7&*k>T~c+82NTp-85X3jb55hB|6nuFOGh|9g=80Qg>ywtqWL*`?TT%IYqM}$r5vq%3kHWQh@vgXD?pHm;_ z4t~wu(n)?|k>~7v7P$E~thkMtCubep&L3yH;>HFsBmayj%OhLm`R29!P|eA^^TOX5 zdb>x4%O)fD$emgn!*QDDzUIEGn8zjgVVZ;4IpKWuHs%qsSuxY=#?1GA?rVDWv*?cx zKSl9>`+A>*;}y+wU-P%6n!7!d{FEZkJ^xwY{z!Hi`8;l-we$C?=DANf+ZFdZN&eX) zKUahNs!9Gd&2wMltG9cEvr~IyUU3{F-+;NVx#wz(^t$EguiV#P(z>@Xb9O4`=ff}e z$FZW^*Sw=Xi~is@3M2Q&Em{*lICyvGzW$2VHFsBvXZcA*o;rLMxcR+Yai1uTad5Zh zzUJGf;yyIVPcHKFHOLQ0^21~9``TKIh4R$9D}++oDHU zqxTaL{lq|rJ1NWZ&BB_T`MaC<8f)8FO>=D6e%@On?NN(SB1X2y`-%IR0j3{{_|9eU zZTO9t8y~t1{9~VIQ`|lW>~UA{Wbhmqb1*}^D{7qJa!lYlNQCcSCH|h8GuS^$A*XJM7}8Q+x+VmK^3htPpmBgV!cj`n&q!{KLZ!{q24HVEfmiu42u3 z$mbmSp49vv>EWL<=RE8cJn)T=IhdS>-GkRA5A=8Kt*ycie&}!S+Yk35*xL9Rl=9_mEJh1pY<$QlB_S@uPVCdv~3m^8wS!eD%Fn?dv_RiQZ z*>S#~4LiicdnEhe9hZA}zSyT0J?&xcX!njW+#L46z#Z*<{D9{gQQKI#Gi=9x&IvpC z;m+_re)@<;itvNa-iUSou$AjdE%5;c?$(@d<^x4-V;z+2I9A^O_QN^Keu$O#e^;@B z*L&DQ*EP@IVeHK!LY7?mJ8aHa+y76s-cp1-w4um*%>P@&z|T4&`^H!HJ#XyU&aAPn zzS+0^yTitB^fZ6Dw0~FZ|5i_9SSuEoHcY@RMej?9Z zPh7tfQLmZ$%(PhgzcWTOr)G-Q3kQ$1d0?Jaz$EgxM3=!{ZUbIXl#?+@gnNIIqsw)W zeP;NCdV}bDB79veLcXtvf!>uO_VJJWWwA#7d=c{7h!~Sa_~(<}DMIHg5jNN}9`;8D zA6qwz@X=4im?CN$%MsFXELUibuN({4OO9p#B!5ZBJCXZeLszvx{<^8^^veZUCoFAA2rU~gO4qKR?aQzC+ca6DES!JK9~SbC#WlO7=zy~+maCJkw>6(l z8DreDNOUPR}(vDfS)baY_EXkawJuwIC%QL~p7BcjUW9g&$&LV0{PQNO`7h{sBZJf7C zhdA(cwg_ywX5+NZab6W`8DHB^MHej-LsYIdyj9Lt58*H{jX zefV>U4vaPa`IAD9#Wm|6GS=BU)-{&D1|M4^M94c9?(p8M*>7aeaXuEla?Li2ePiAv z$=@IH-PPauCZ`#Z0i)wb1dwwE1F5fIh#42#0hVqc(T`Y2J3tK70K~!M1OG3@U@dD=WVi9 z$Qbw2u}0@6QP#olqp{y9hPy%@d*m8>^kv3yqgENixLBjZJnJy0x16JEJ@{%f+uZ${f1t2sDpk5*fQyRg+i+2UI&<8r_46*8{dpSrNM zYqE8z<{1~?Qp<{(a@kej*NM|SXWzX1s_`$920`bFlRlF{X&X#`({<=ZiJ?ZWiVGfQ5TL%ado;*mA#4 ziZwRu|31y}zm14Nzx+z%Sgp&R_1k=3ydb@mMfiMPlw$?=L=pS&iQ%bOBad#zHd$-p zsXa{&u~BP!NAR)rmMGWMdA>emz*6g4@3zZA7JKiDYAn3}b1Y{kdA^l$EZo&2V!z3E z+nzci`FcZh?)BPJ2ZW4sJuvCqu6gaLe-!z>Vojdi7n3w+y+`bkn>R)HcTW-DQX=P< zyn=y2pMj&d`fX#`q6Xl&P=rtC0UYaza*cizYvjj@kT>qhniE@_eqUbl_J5P+#Mw{8 za2~S%#l*M#2+iry--{SiL~Z?ZHf)c6t?{$Y{_$h^%R}Dr`wpeozbyhk`aBubte%lq z#6y;R-YTl`6BGOJIqwr=jr=GP@$VvH;Adx1Z}rA4vSn-sY0kZ#d*j;JH?}L2{2?Ll z+)UP*+K_MXS?4^>@xh*R#r~PWC(b)X$ZsoRkdwA`K1Mo@g|lB{0dLOpkR*Rp$U7F- zdEcVL`EQElFUi(;&2ucoGf>o9HT&=6i@zz5(_FJ(#J=;tagwK=$U9Egtj&2|E!jI# z^SMR+L=5_q{6O}=P9JT?9|V&DE>N%F^Op5v#-`Tf{iy>Wl?b+qPS%)P<;AMD1)`FAYG zYL2{fGgK*XDcq@vC=Pl7}q8$J0TC;EeFUJ~r?qK5IMZ|#D zoA31dWY5?x(wx}06ETSGc2UN5bF9H}u?YF?MU2TJYD2!rgX6heb8N8ZT(Qsjx9>wW zM}9{UV~VJ4ollpJ?OmaHjpg{*H!jY<<*y2P$KpC4RCET%y2jE!**Ze=91AfI6cIBy z^|wE9P7<|^6O6|Fj^_Ed3ih{(eaE?Fl7BDcx6zZ~nzebSuPZ(KKTLDZ&kiC6{(mT9 z-~PWJ>;Ka8JQ4joJ@@vK$=-*W*Z3ETefyt3$@8}f23JXgqopL+3RP_ufTiNoI z^R~TtO|r*%#9lv<{a>nC_RpPT|8HtOz3=qXl0AB@#(!Mw!>8s)#oD#W@w+z;EINZ? zUGIQ>lda*J=h*3?-n;|0OTHcsU%Ae|jeW=Y>m>hZ$WKq5f1K>`?M6@UC~}>Dpjoc- z_hL<+4-ir3T}6y3qPBgugmm0DBQ)m@%JDB4`;LFUBtI(T9lz^5XUK5&ySoFhYyW(| z)%dxWmKWLod$A^d`ib~=6EV1tekJ0r!T0pOAD)yAeB+Bd0Bk#n7}$SMl(F3#Yvj2D zkl$Ivm@J|;bBMs_cy81j8|*n(>~sF@o9`OpbYHm6mxN3wc?OT|U9WkKWq9lx7w6yd zV9c?2KCL{@A)OrOL1C}PxqtF=hvvlDSCn(s=AF8SG>w}(5vs z6-}#VZSp*?Y#G}Jn&()FZI0MCHn3Qp_d4?1hiTC;EeFT@)8 zPejPqIzJsUoz&)`kj36{B7TdwZ_&S7l>OfxYvfN5A@BH^uPbtGd=HQtcnhVye5Xwo zpC0@|>^s);wRUd!y9v4PCt|n{M{Az(4UaYWs87}*o|9sqc_$bS3wi9lD!iZX^l zT4f9aVvP>pdg$yXV$3f3y9jwO)Evzz9=UQ3&_kB|81Lj*(pNN6&--+zU zy6joM=6kb{#~$B7*xOaaaK1Ox9Gk|sUaZmKw=p`76}=TieMI2FA9@U892igbGQLS# z6K|VyyoBVP3%;qzYhMuq`@H`%Zr=Zv=YB>vxN4{Hw&i{jZedhiRUBgPiqdZ_Jx~(WCX;%n|#>1{T+bZ(HP@o1XN>JJSD# zh};|@np@OQbm$M-gL+sO`P+kaX<-dd+M6)GPbHJ;~n~@{ZrV zab3uKF7|mcn(htmD*Gp%8vl8*@A%J3@|@coKe7K+gdcoP?>mLFVr;w*$$7pv4v2kY zqc1JbyAb(pM2yLzwzb(^I<|Mb=HzBu5rg=46tQpr>{*_^`J!lgdSjDh?*z?j{OiZQ z{jZbc`OeDmyEj%VI^T^oxuN%ni~6l7axB=&vEy%`sJH6;mE>!P=5vU)6FJY^e>udhQ8S3e}5)U=2-wv0AEb+W4noX4BKR5R6e@v{A=ME=$crj1?ijy@)YcM4z|$uG~%X_J4@x|JvAh{M5sEKMHxr@7}m5WIE}MGm<^@>CGJf>9KGB zCnx#yHP7+)(YiOk9r`C<-~>a?&EI0**#4a4$Ar9d)05u7mvhbEK=IR0WNuJukcl^|rdy{u=#=LZ_+2d@}Gc$?4E^_R{ zG{=@>=iSqrcL09vi}z@a^JDRr3I1Gq{yWy>`H|o|&YskHO0vf{B0asM$aQ{7v+Vz| zSmS@Nh&umC#K0E0{F;b7l278}$$(ei-8YMeee98I?x4OR270`ovwz-6mLI7(^4o|Q zuJeVOBZGc-{zr!_{!bFs`04%Z9~t`}qB-$%_87B>dh-t0SN81d49&r|lZZiVdx_Ym zXXp*;VEHkcBfqnV(Uaczo%C$)HO+}N_r?~nZ~vPm`TawFdU|8cWbZo7Yy7LmzWuM9 zwE{0+eL#ePiRBlw4*%?9-pl z@tvCEr?04|HRJAGS_E#+0a$a*UeKC-gM? zSe^~}+e4<4vw3aEV((&6jpee~cPwL*{JSCVSirKaXj(OEb8nrHeEnPV94oOM5&Oo* zw>LQ>mJdb9ZzJkyo&P3H+j~oM?CtoewW)W*9bQEb8faQ z@|(vRTRxw*y>aYegFBHY_8D`E))V2YO{|k7kFPI?$cb^UthsUTuQ{m>15e<}8eagYfAj+K3E;|sga6M3*ceu;;DV#6ncXPdM2 zy5yG>f#U!XJ++;Pf$ir->|>XEYI3ZRr#F$`Uc`Xc#`k@aUo!O0*OPlI`@TK)?fd3f z_U-$OB>zyzZ=)w;vWS}PByvrv z|8Jx{Y70hVqu0S=U-SZYunBIhM0``=gL}R!J$xXa^^VsXy}g1@P4^Hv7bj}Y zKHm%sY!KJ9@PV`X;SR*k-$h;FYl`dS(EFch=rzT~Z!P@&Bk8TCx#Qx!#s1zR#uO2_ z`-;GhO>zxZ2G2IVyoluOi+ix1BhGNnA?M%nM~3|NdNTe?)W$dXZR;}4>p9~4U^~~e$m4|emMV@=bl9V ze?=bEK7DNYPc-MfZTs}y(Xns)^o->PXrAqZr%i11xNVKpoEYu9DK^f(HV^q(T)TQt_h#XGC|K(0;w=oRc^Z$D9Yy-B>59~AP_svqZn zaS`@E7S-N-DfS)TbFoIA+~wYc*Csa3zkLtW9DVmrQ*YjujPpwW*82dT|1IJPafhJG zpssCdj=p_;sChoi?7c5qOk`|t$C_9^5+U!rAm66u6D5yrZ1IhO51%z`)&AtW+48T4 zynX*igFJVs<{9EVA(Aif{20eX{h<*Fuj9Pwz=G6!JX;VMWzwOZ%-PLc0B>!&6=ls_A=yBU0 zqj|00FJj;EZJgxEKk~Lev*vB;$N9JKhc)l6ek&w-zFBK-|3kbQANK9ziO|XQTOjrw z-@HlwsgUolC;h~rr`psH9s7S%^X}^Rj%2o+m>9Un1S z{;ZI<{aLl<{ImZ#5%u(7UC+}U;@Q??n%8=8KCTZL`@bgX{Hs9+f0v5z2i1GGP3}iX z-}tW8{EMP#-F?R=`71)+xdB(r{lQ88rjWONVjmd$j-9?Uo^c^>`^4Jjo$`ld3#_^B z*xD}k?YnQ19~<)aO>C=*W)h*B>khBh{b%Aij{7vHZw83aW$>&zYl&x_{Wa&EmUYmp zI@H=a2Q=uA}%T`$V^ ziSG>&`;PCGSR;RX3JyIVV+q z=Olk!$me@#o7i`JTP67$Lf-Z{gKc_f!({6c&1(<+DE94pjU@likhgDo;JdL;Ug#;0 znKY~S!#BipUhmPolO9?)>FlR@Cq2Y_&3*g;muYS;ZS~Qc0So3?1 zb({WrUh<2G$UXgqZ`U7NwO^hT&+@!$k#`Nqca`USTK+W6bN>>@ZL#mzZ%Xo~hkUj_ zr+CC|dF~SIW6L#Xe{ArH>s=AQm8lsqG2pk!6IdJvz1Llyj!yEtW4p@}?+Yic20KQ*1YD4bJHeIn@H6~O!B8_ zUh}j{>^n~@CHYfB-g)B8FI(i7jCIWuwQ+sk(Y)pffAfmyFDRc$`ms$8v1MNuX-=rC?7eBqEgH=d5M=}f+qJ>pzkUF;JZ`C;F&jfpilt`+6jxXaqac3iT>zhiV4+d)bGf{>q9Z0tEUzJaoR zV*6|CJGMV2`D;Sn_S>H8-z8h8g)R3C{a)|=&651kkhkxqy7BkFg+p#gJZ+!Y){K3} zwtB3|0eQ@I<4&M%*aMs23;5+MR;#9jed6TY5JyvNOQ*eh2i3S=knBPtY~B`6JXF zk-V`Up*jAXrzWgJlKg1R!C-lG`^Ubq?j397$Z_qbKgT}((OnPh9J1ItQiMOp-Gp_k zB!8yn=vf|J-v7jIteeIfx%)-AmpPZng0l&0o8N@UVhcai9xMYz*k$k}9?p%iEvLD4 zxUbRKUt}Hhst)qj;d`a};XHpiWbB6;Sm)x<$$pS)6YGbP=MEy)3q%z|Q>?Ehor^*z zV`z$XV$!*^!4I)M8ZwUc!KA}?a?NS|Hl0T@w}uY(d{w{06Z;N;i5V=0wPi^u> zjh#2{&`$C;Ea~w5QR8XK8|UAC_#UZ#i1Xl(ao!F{I+uk`t`B|qHBndhKDo%f{U@!B zfu19G`-m9iZx<2!_P=ASk)zf;^SS2zk371r5w`GIeg9HC`~F1p>buHskmUPoj(z*a zN0t9Uk{=NAj*Z-YC-xoNib;OIkhlFlS}!XiE~ws@D~s1@&gYe^<9TX=vu5rwo zkG-TSu_OE2?G0nS+?fxYHM95Do zwp)_?p_m|vu1xZWhrI1K-7%bZ^y?inCfOmsAoBLz z6x(`9{zT1l?x@=uvG3ScOY$d#yzQg=?bxT5-Q8JBhb(pD9Pyl1Y}CMYcsJzjyD7Fg zlRV#-**>vx4`I)-!L$AMHAmj|xknZf<$KBf3Xi(xo_S5{1w`1O-{%$$7Fmbqvm#{d z|Cv~$!`Z1i_-KP+e6n{|gFP_Z95TjmebTw0L5KUZ4F=x-&coRa_P{VIWQ<{0(&7DI z^FW`q!NA>S4Cgl31H=9yV+{S1&e#SW?tr~Q2L0OW`5TG%8!`-fWbt^yBeuLp&*nbb zT5GV=n|!w+3;kN;n2yvO{|AU{i{~aHWE|5^V@-b@E<$IBDC_)4>#VaztkF4IgwBDY zth0*N=)jwvSjh`^YOK^6J{XP?f#D!g#_(mWGj4EL=LpTwIari+IR9A(zt%ZMb9A`x zv(CS@ouuH+yCM zr1MhI0R#8YOd>E$?>lHE*>KMLYfkQK zuPhTX#XI*6B%|xa*vw zn~ObTI5lL9;l!l#P|*Q<+xve|vUg*#XAFCXj4}Kz={!($=%YPiztc0lU9xvWv1bgw z2^nM9BI(>;bf`~n_R0^Euc5`4@vR&(#A!7`8CY|9$XJ)N; z5X~e4!}Q+&eE%EY!J6|ogL?PU56Bqb$XJutBSl%KC-=$`$=;A+&pG0JWDEn74&MzK z1HJN(*zdGXyC-}2%Jz(byk`vklFp$;r;paXS*P`ruj4hR7CVU;#>e-6#-3~fOC@{96nn~$5P7(Ml|KFM;&wIn)p#J{cEcVFvA)@S`eE&4|ZHx2Ym94d64_n;f*%tR$Z}#_+ z$rpW`efj(?7&69A?9SW6MW-kIja}Qjuh=t&55(u)XbkVhnjAeS%DBn*tFhl{e?JrQ z*t=hp?HR*kA!7^=B^~BjhdJMEUG;bEtsBBtQ*Uwpi5+bGR>*#u`t*X3Z?ZKe_ONwJ zu|?j7#lBWm~gry{f1y%)AS|=kt$$-vPXP*mv$W)*M{;I!(mcHE#FRy5bo- z_x9ScMyJ0h=M-PxkA3@CCDu)`E+2c?`ll%SpF`_T>jSQ@iNKltI0pERlU@Z|Uy%pB zkYglIUD=|aZHwQ(*%oK!eGxUboPCh@dZu0p*^Jq>dN%gR&A&xp%$WI`F@Buq$79`O z>w(zA7IzVSWLx08Q)JA2G>69k^Fbnd5FX!F>@)r@B7W2k^R)v}oyT5T;7GM(hx_XYN@ z4tw-L#>PFG^UXP94c#OHL)H0MJYwkt!l7J4%!>yr4DqoS!K%N9P7n)$u*> zS)cP814pfs?_cmyC+@X+&MygF$8=$=t1ZqyGT6FD)MRUT$aIo#|7OPCO=0gaJ#)TU z)|7(}k_&lP!9k{8U>@hD;~ zedNcn=Dh6{d~ggBf$wM$xn}U(O_cNY`&h%vwzdmCwk{T7>ljhC^&73xgXcWqhuYU~ zpr4C}EcW&jVeeQ`w#WI;*w%?PIv0x2;rCtESxxIsG0?Nd&|h=xac5_HONESkVX;_) z;d~J~Cy1=WcXDr?6W;&egPc$NK<4KfeIPyqY}bkSy-@4@hIkCe^Gd9%kLQAqE#9%% zs`cUbN4CX%$Eda*3_i9vr`XDQCe9ggPR7cQ@#Vao8+`CxE^5l#$dGZ~hQ^v$v#pbY zk1g)GCR^M$4C?5*vTiyjgFls=TGLB4Z>j_5pJ8m|k^zRhMNK+;d@9iyhV4TZdz^jj z<@yoFZ$%lyuVanQouaDq1@UG?&A%HsYMoXLKKMAloZ}Nk#KPdYbj+RC#baGOOoexCSA9wS5Ap-{FjD=X{j6GvnIM(zN{p$1J z{y=|{2rQ?IY>Q{LmHRo{!iMw6U7KxTr`Cse1Ms3>DuQ|qj=daThI zB&s@K|8~f9f?=MJ#UAI1XT?x)BLgO$^l8>{Y;%W9&411%dSJ9IKe=OTE-mYO^Jk%l zzH8#W`^2Mv*y9_Fr}t`YohxwS)8m_(8PC(PSNmk~kikB2Wj{4%x$nk=e6?4xw>kZeu>Y?8j3p%!WMcBl4#qzFre3Kaq7+KSI*NecC_5MTawpgfjwh69bqKf5# zkTaHhlHTo_S3S;rTP(bPjpdQBnd5VfE(|$iIXCG|Xwb79edGDi&;h6W$M#Q*J@QO! zHP7(d#fGvrXr9o!E11YbL!r8ual0-QY9-s>pE@?;l0@gjer} z1H?myJ^ywl26%jLd#@=zY_V^g{N`{CI4|5)+lUyBjeW>E*s#tN&9e@e+G2PsY!L6H zV$T>}48Acun{-|(I$&>$;r?XrnPSfvI4{I%3^yko<8$sluf1zxpPY13i;I%Ir(M6$};MfRHi1eUi>`nscVD1HQI(;`~zsdS#-h2}9qI zF^1p98lC4t2Rj~ZF>D}BW8i*f?wDLB&Odx(;QQM;oEiAWK(DME`{bmPURgTiiRp}( zR}2dW-xzrR8^a{cGX`?eo4vw&U{(?MI8WRc72iAJA!B^p!Pa?E^Q=Q&+SZBt%=S1N z*`Djf-(NC@dy~%VMTZ=<#c*}9NAERZxHx2-hYOOlR9yZZSU4%&lo0zjB~`h$~un}9k93U75v)XEybQOTpKdR z!1t(i_}gF31LtXM?04ELXC!+!6??{TTF4l~NlAx$FJquSz1b`KCSU%|QG12&e{y1c ze@r^VG|%{Y(kojhd#4wB&e7%}V+@-n9dev8^rTmQnCwxHY|j|J6EeoIV$vC1bm*03 zV!zW~Suok-UC@N#OCe(n{5{0|IymEXs8npjEEZKCz}wCy266PwIp}W8n8hw&xu2{hu-XHtEp+SqJRD zjQvjQv_Z0WY_VqyYlaNI<`VJ!Z`>zqo-x4h%{ncbeBGh>+#>gc@$vVDoTD!#9nKo~ ztkaV^eIkAOkGhW+HDTcU9~tN9jaZ}eYVeJLI=vA4;OXRh>Zy>&-rb@m47>+3hI^9^ z-@Q2xvuM4csJFg*FHOEUTVE78Ue}4=ml+@D-+3KabjS<$Hu#*=Q#D7P_l9#uo{{DJ z*w$g1XaD3IUiJ;fu55wDwhq-i+v0t*tf;HJWz6*99-^-NaQ^LQnC3H!;CYZg_K6=` zTgAF5{$Ir&{V__EZOyLrs-mtiFO>G2S1>rYoUL33&cAWO49qWwQ zwqA)nFkc%w)R#feOc7xVpI;VvkoVkEV18VLZ1&??JrH~N`9MU!+7CAG6lKh}#=6PY zb+L!7heY&|ZGn^A8#8%=#{lz%BJ|+RFJhnZchT7*>-pZc9{cXouV|iaZkqPUQQpfn zr-$=i&EI70Q!`@bTpCyMB$Q6k&oNgj}K&F_nOwMCw7YnbLuwr&U+>{iUP zh?mdYKSLI5oH^``7G-SbYn`!?XJa@+^Cq3)A=3$l=^J#$Q3hKys{Jl56LCc&ph*NKR=+FCDUI>|TptaHbmfxR)J zjE#F18Dm>M=3ux*)TFay$aI2%zq1+xzX7m!mMCN3TO?!Pp0Li%npYj)1E2Lde^I`v zQLWSD;JHrV9VN;!JrOd_>m#wQwmARruyvcL$rgNMI>|RVwms^Hy?V|s2^nMKuC>ni zE_CR_PBHMEWqZ^Q4E3BJ6EendMAEstK?i#?;+*dmIPjP6cFwORL|z`LdG%u zCf3y!=ijz?XEfQ`C}cXR`P#|elVPu(^Y4X>v3)1$(9d9~I^PJHPB1K*?9uz!tLL2G zS;TD&~*2DUgS*vff^KO@e`Ncl0ooHyR<#`m#i z)RgZCa?Rj*Y|I_&k+G&W+1A0qC#G{n#Cnb>+uBcS+jY)aQ~O!sX+L{?DmgWG`)iIp z>}Gqrg^YE6A8Rm-6`^yUDC=yab*C8koyEZ3KoR!N7iD`t)0$xnoB``xq!~IFh^#ZS z=Dl@JmX|F?JtxZ~ey-7C!6%+8M6-!%z2^@Z$HUod@-b)du{BPFty&*qW!To#)&Cdo zhms*b*y7s?M%0w8QaiUqr+X+q{H_={yV{NNXTLDG7USl9quDARGkGvrV|XDf8?;ocPtoA7G(^af7ZreZ0OJ*V8}YW z17<|cC&Q5dSZ;0U49(h4L*OhFDm=im4 z#>sDU>y6aB>Y?8jOMWk16*hUdR4iAEm$6(PYjSp@2rOBTIND+%CdY?Oz9E|O!gor> za$M58vq6tD-xkY&WRvdzu;ln$qrF1zKlPkT^ru*pmx-dPXSs}jhtL71`^WZw7kk(v zwwh=7ZDZRo*(6SEUM#9LUn}H{`3JGaC*O?dT_Um`=ZGBS*j9*jQ*6t`9`@+3*+dyf zAFbQQ_9f}yADdvSHl5dcCXu(^T}2NZGxeEi@hd(z6C#8=uZVCN-xKXD@*Yp`k∾ z-j_9Zx{&)y?2%&j_7<^Ey0}K*a~=IvWInc;qrXSYflp|(+oiz+8*)3w(>}J1b@j1T z;%6WE6?2wk*t;xb@v)+4<5=Ub##mo>>x69e|HI%D3s)zx{4;otgU|Xc5wTnmJja3_uM}aEv6|>`5jyaABEtY4hlZl4iwe+@iic19REJCuJzw5@w1OTgO3mV)%fwTQ^?rIcCoHLwhlhF&J|%R zpBH|PY%c1JT&@##Duy2>K7P1%>Ah8h54J-^O}Sh?WE|&mv93OrNc`->KO^yRn5Ze2 zwI}jVpWGAN*X|Xb*dz{~UZ1BqK73x|6|+Qo#n>cA1vT7JQixXeU~iy^CwpHN@pfZ8 zCn5z~h`f(m4|sfW@O0`beE3}98U9mR6Vf#zd|LN<&ABR(eOi=d@QG|s{BiwcTlP0v zeEWN}$T-GRL&iFt#K#w3lRu7`{XJP^@b|okeD@b2=iKmQkmtXP*lUC5LCMb{x>jVH z;M+lDJP&D}WgP!jA%otG=#6pmL;uy@;0iI;8;T5A!Pk@C;1i+AA7764$1%$?&JFue zn_BQ1%eJgb-R+M$Wf}ZEFGA*h5m$-p$df^D@Y%zjZFbVD^dV=OyxS(d@h=g!IE$Ru zEQ3E}!NU`(cM6}PU}A4Z^v&Dy({$!|9XXD7i;UywN#DF!Y&qvgCVwv%nW>eU`oA2} zwob1VTlV*tqOMiy1&-kIXy%3EaMnA37HvH|A*x- zpBZEQR>I01pJk?}{&y8y_Q!kHxfx$%oEzTFZR>wuv1Na6i_h8PoIX%wa{cL7;H(>_DOGK8OL~e=%9zJ2X_Lsn%3QLcG~CO@jz#(w8xrw7_*D0t$Cb- zd16g&4iwR+ygR_eU|n^P#RktIqO9ZGoglvB=bfHqu#5ek;^do)_i!7W&lVly+)aGr ze7?v`%|Op_zTRN3yL@to<=Bk##|bBQSe5}N?-}0z#6oUeWA?hM`$v+g_PWE#J2vYW z=K|t8pC1<)u#jW0(tE~=uKNw#^c#D&*~vNN?1K455w@)Rj^_Nuie7z1lx1AsmqP}< zruXn?an^VTawoLu;UkKUW4u~?$9PncAx7fr=~<&6xnJ7ge6{Ep=h5ODCugJD1#3@n z(vQ_%cRl=G(J{`Q#W&7>7a1_pzkNf7+_pJugCyU!?gNUBajqE{=+8D|6e!fX$o1EvbiJUk7T$W{=w=F^kJu# z80UrJ8|OnsW@-ke{#g$hFt^DkImo%`B%gfiWF6x?Kz!qTqR3#^{k>1fS+A2GzEV2$ z>@6ZS?zB14SC)zdzGwZUF@ zeagE#$7Y=HjFb0JmT@ik#+X|K<~DuGZ-Q#CJDjf<9pmIa00ZZq?~Q8LeR_Y$S+A2m zJyklhh;9`Tqjkq=Zl6On&obo3a_B(yt{o^I`C_lBhqp-k#Kk+0fzEvKw2w~WI7~X6 zrQ1X~4)~7a$Rgt!_r%}eV#`?nnEV}BWSqC1L&iFt#K&)(rucr9{2f|k@b|ok+-@Wy z59Ee?^JI|kbw%v8!E>+V=MeFCvYhX4YmF^@+$YL1Q$0@oZ+IHZjOdL!g@bQ}+8dlB zV;x^)jI}4dabvONymAjwLvnLVk-;Bw6Gg~ar<2~`>^8+mO!jw2k-?vP+ArD!XJ@m2Xy?WQo=)ZH05*A{q{q(2c zgZ+#mLmc4mNk5%jY`IR{q0TAyc*cZ3#>T<7PAB~|G<0fws|TO>h8G!pxt~^wy*55i zkq+<2>qO+qx(jRW7*E$c%S?@M>fiB@L9e^}gue5juX<9CXQbD3-rf`+eB@_xk-=wA z>(5zh^7pX#_V;*^ag29|jPuz^{hunftb1khH=)Sj&-K4BECU|S!XhFDcxvwO4ZmW2PCV}88$`}+Jy+jMd&q!^(e!)S zXAqo+h{zAN@ylQh*$!tt=LJ1v*=O$O!J21V&dV&pN0x7@49x{KLe##>)BKM zp9BWi()j-#eDLqz;LmrmnY=>Otd>^fK)^Ysri;q8KdG}-)>=IW`adKvexed-YijHxP7vDHJ z*VQgqdy134>r{K)<&$2?I>tFleB=D6$bj+lBEAoiA-Apnt5UXH`x zDWAoCa+rM4M{Uk2eU){bo5|wOCL-p;i;U~o({uW=?A7;ccl|%5=oly8|Hk=Bk(t_6 zJ-<)*yJlOQuNEESJTl>Yx5$8#`(#MS&@*lBlR=WtHN;+b`Q$yCV>8Yj#dkgjH`w(# z+$!X(*U6nRRyy1fw}^<*x*KY4pPbb!;~K6VGBff#9VegM0d3CH;YG(W&K>wUPsbM- zVkEAfo+rLnXBM@=$yv!d#`&!H)DoQZf0l7AdWw^Ox2X2I>r>83)-lej#WzmAiL(qi zIZqdd47qJ{o(`3K+q(BJI>yQOnsFXhWWee3bYRF?uaon{cit?bTSdfZ-M?yXpC@RZ zW!!7Kh75Z3-Lk7AO6Zb&QjDh;iOk zWWeb@J}2a?*Gb>pFCE^S*NTYIx+iLGpATrBWu{hY>i_e+bCb{2bCRcTwh&QA?Dkgu zi4|LI>JOf*;~4vj?-*YwGOj-{I7as*d)@Wvlm>g<_37lIW1Qa&4D{)Qf6Xp8PAGYxMgec26H=Ir9rrr&!Xs@fJas8X(=UjQe=5DF9hYWZb-JQ9cC6jB3PIvXcspvR2 zTZ&Koc9Qe)p>w^SIp^H{V893W2y@GThwmc# zn1SB^-`}|>2_v;3F7PtCtJR4iV;$#}-;>VG$wkKb_*2N>t4&WG(_pVVocygL$7Yfy>{%`W+y%MZ1}oSPut`heEF~io)<*mv5b8#88YZK zo#QRUC!g$71D*_cJ^daVE?sQ7&e-cN=fjGQ^Yga&oCRVWQDm?S-j_r^FKv3`lm>g< z;iNxvY{q#wKs`ulioN(gy3-~WtrXpsS@dxO9KA?G@} zPW1Gs*t5+}?iB8!d|z0Xb7VYx$7dOQVtbefzhH5Xum|s_@no;wH;bmd+*6K`_dmXk zrIR==lRUk8i^#cQ-B;u|h&9VNcUy!EdQEsXiTyTs=;2vJw~8{JAA~J1@lMJz;6ax2 z&pz|ExmzN1+hDy@Iyo=aKk`O>x|v_OXR5qr1OXp~uEc8uGF zephw;ZQ5@WBj-5d?WB&}MOnu&t{xbO@wOs^U3zv}b^M0*U8kmAT|Di#iSb_PWxSol zcu&!BjOa2aMt%cVyX;LX#y7N29=fU{zk$5pCdNCYSFv>0tDN1e;~1$O7>JQOG|Lb_ z{Ba`Vtar}kX|Jh{+;P@z6XOHYt5~{=@&2OY7>@`H#PVQ~Ax7@Mp5D2Cm#*V$ihs|v z-zI+Y#y1wV?)1*Rpy)XMpNsDrUsPm>zq>nkto`Wf{~gQuMF##HBH||o2t9}a=B4A= z6#s&sN_8E-^JOew3|pKJ=Y#&lKWm?9;{hx0{%K+5 z@0!!XdUWi!!OGtYG7js4&sedWWx&dMT3Gi8{jT!5Q|#McC;d7g{MNi~9=7O#{fi7( zXBBNEa_)Rq*ki1l_L};YzyG1z2J11B&pEU1a$yUs+}l|OES%A=i;NXH<_ym5!SRGg zkL5kS=a7L%FXg>y)yh7QZ;GFO#;#-Nq*m`sp4jdZVb{7ZXpSv>ekjT^#E9(EBF9l{ z^;p_#!pd)!wph8ZG7e+q--?a(ts-Nrmxc_uD^}hCj-v_d8L@AFo#gdx=`>-b-;DLW zB4ezdMeqDI{1SgtjJw5tn-~w0&MczZJHH8A^bWCP8OQjGkZG#NPt#r#)^%dP4c5U0 zhjmvBTVOq)$QbLi&g7z@-&J1ci+%g+q<4lC9M%P+d*{F+(}%r2GcB3^XT4_=3snYc zTvn58UiSM{+Gi2@+ zVV8l8nyWR%v(A~CqeFjLhx$~VZ;NN0+cd8_#ItP3V8`)+ftY5Cr*pBe*4V=rvdDn- zbP=}i7a0%Fc|^#gKd*?-e%6q4#?yU=ty4rzwmuP`VJsiS8l9^|=sX~@fB3tIun&*i z;McL$Ts<3m=0i&o;1U47`FF=sY2+I_yWoV|ocF2&o~ko8 z>G0`Zb--M8xC@Mp*Ll@x>ai1(&czKn^a^&Lw z9?~<{ZugKe271F7uG9<+SqI#0Fl_OuwW+=EXoEelY#cJiuwl}nUKIo9q78=cCVP)J z*aHK1Bf}V$jWzvniKt>A*KIJM@4Wsi>^-b!t_Al>#z36bxmGi5WSv>HZiC@1$>Wch z_{oO7M?@LJi?MbdIRDl;RP(As5AGQ<$brd&J{=%(zY>pq!P__MQB zPm64e_fVVn%GQ#{F7|kzU~i(x_IPeCG6wcHjWs&d0^Tzs>&&kCDx$2zyN0#n0q4ge zu+kI8z&i|kKM-M$+_KM@LsWCi_qcUm)*RglB4eS4s}8uWGfDHTgD=+fm1RZ*4_Vs< zOFkdyWS?Led!1t7i68zFkGq+ z@dbrSHg~qxRR6iy3vn~#e_abb=KU9SO%|r}*FClV%9FJqi2Ybe~h31YCKKuBAz`BXZzV6ceOCl~4`&wT! z$4M^Ni8a`65mD|JM9vL*tBddjue;i;AQ|IxEa)wp__;QV2Os|zh{(;0BKzmbi_w^= z&AhR$wILVw&D^!27UtL5V1qsQhlz4+*lSap*CY>C^qOkJF=8KIcZ+ImCd59tsSO`e zmcLDNYV(rFxk2u6k!$08yLa-XjJ;b$ws)oG#QL(x_IPp)Aj2H{5Q8VR#}{+#T`WSD zcscWyIWPFcd6fu1uZZjiezi4Bye3;G2OphlMAa5oQjU}UppK67>d<*rPx}XJzEhAL zAZqgekHmNEVE;?-!F7fRT-4t_z*K$gBwmw`eu~%Ufd)U)&qS^oA(=s`j`iy0Uk1>|yUoQMCuo z+@Ij%tYmx0kgH*d?|9&I{*lMWLn89yc*p_#>Vxy&rIh!Og%DQdaa+xw%B)0IREBnAHNDdKF$|ayiIox=ij!nk9871 z`}kq-@j;!dkEXk4#bhh{ST6Cik0pYSkMl&;2X{}+73Zue4!)Yr&p!BShL4X6Mb!s) zQuV=)CVI7=)%OxV`*b)yJ>ui(y_`>c94X?7zVBje9Gv+1yK_+R@qexe-`vsm!E9YAISYN@#oSUd3^mL@$ti%=`Uh`dl9zbA1=cGW+DbQmk@!Ux#Mx{wKl(yjBVYd zIeC6Tgs$yz{&Otr#@f9BZm>b{IRCaeUh^-BHWhiasSW2JTRCsUMvUg?+VHE{zPT63 zP5n(k{gEM;)Q0nKTh15pbNCGbK-eNWDLYvb*>iAJ|55<+*zmTj<_J{a9`l( zU6K88NAUi~E;z~mh**Q+ei44&6Iq9TyDir6s5^OK&_nb!PuoMEH8S`|2bxV}KC<-1 zYa;gW%^uHZMCiRQV$XKzFY9N!*fBr9^RmrJl0oO+qONR$56sxgHt`P`pP!$I2c{21 z+2$r%yKen8Cm$b%3^_xV^M#$J*xKSaKz8s^aePZW;}{Y$83$O77lFh0!Q;9vlJ<xIM!gv{?-US*vTz*pf9k=;8|@sch%N6Bx{UdtG2LLZ8>+<7J0R; z0S&g0ueNgTa*Vl#_ezi4IY!t2DDmbMA$y?+ncQpmbFQ3kbQ$2BR2zn%>1{#=-9B?n>}>DY;vyY8HW4ebRF zz{c((WURAGtnq((%#9ab8~?vfwocQ$$^RxHWB)%*I@f5PK)Dv zIVO%9McF>_SNpGtXL;&_FWbjPm7kR4`MsU(H`T`H8C%0d**>+oM}&XZ=FV6nKTcHb z6BF{}79E~Vwc-1i-}8>`5Y4f*rHFyvg(BMmS68;?)86Qi1y}!=|3**Sa&J41lR^gh zQ)0f=r_xj3heI_t{y88`9xT(!< zq8ZUYM}+^{KMw>SjC^~OhasXoYX97#UB~sN=C$XjXVtkP={%u1^~t%we{Y_bqr+c~ z_k`f%?_Lpg%kj>v_2DAob8j3RYjhqGRqW*IPa@Zm-lDb)cx%QJ9{%#)pS8vpJnoOY z#~qN*pz}k1{hh(S&kp$bPNg0PiafAcZRPW9TgYJpn>_Cmf!DU2kM+d^GdS{Huy*j# zrT4*ckjMl3-xE1r`(+=W6(fKDvmbC+Zt39T=NJ+7phh0}Ay?=c^8&F3bGF4CIc#x8 zsx9Qnl`&IW4=@uCPv?#&1Dk@>U5K5KN%r)TXm z*A?5?K#utQJW6x$@a|$bNB3%uU1X0GA#PaYvHd!$f&p ztQ9iY!!J(;_W1jj_o!dq8y$Pbp5x9vnd9DHI@FQ#&9Ls#nj7aJ&5@xO@>of$9CyYt zP6Ft^c%dN$COnigZTH3}G-gmSHCp_v#%#8CzeMEl}fq{L#jk4|! z(jIzw56rBg*~{LK(;hwRfgj(c&IxwmlM{Fl_f)RI=~~k>M~WEM%`#_-kIV!Sn2@1Q zz8-7ro=}b7YxZjV_=ax`_J;DeQ(1uK2ScuRy| zdeS4R#;c+xKRb)xgn8S< zXCGfYw~8lzhKhJ+a6fx|qFIxlO~h~V^OMBSe%1-T^I!cOu6^SEe#j9g`rK`dTIc43E_f)hN$MYcms)Rp`)I4Aar z&Jv>aL`^ZSmH6zFr~V?o!<<9>@jZyYV?-YRs~NdQ4?jzaz8P!c%IAEk;A4xkg{@;n z9{XxWe`AYytjj*US>lNwY@rVyd(VmJ1J0QTHnI-y2V|}DyyoQ07?9_z%`9S2OU@$l z_yk+NZ;g-reBZM6naKV|iVsHK2@Gs5Ey~{(*=F{I9r6jr>I*xL$tn;^6qeJ}Y3>SHzbFB!x%xewzNqe=1^o{jg zGwi~nXL%Y&&J||^zWW_`5@d zt=a>>4H@LE>$tv|_FQxCRSfPIFyxr=>3IIBIWdnEdEgh@Ie*}_&h46GW0Z*DJT0%e zW$xA-nQC{*kg?9!lg^!?lk))<$6=jLYROq8uF;~5F~@P2cED&EeEGLDI^^?K5$~5a zzAu+NzRwV4-}FDWz%X8fZ_7-T{J;ML2K6koxzBhX;EUS(Y*3qHf)9q9M4ZR&?z00z zr}pxI;A3l?sNM(2b9TT%Zfh@3tFG>C^sw)~;;z8YP*Kk9)>=8YH)@W|uumnX%3)`7 z5i+jjrm@EUb)t$Noee_9IzNszIyZ>W87}f5=JQ41MZeatH}11#Ww(LmBWCvtHoLmdIAd+^vqz;v4n~O>u64f8o)jOMk)KLT zm7~5(im0`9z8-7(<8cu>IUnda4s<%L<;9Zi?ml}$GWhd-W=zM6N506L?>FjuWbncI zlnC8?AECdisHmr!z%))Lz_HySC*!g}iPRd~Dq!s^^*b ze;G2!TNhu%nCrqkpRum)qnjm%pP?d#bH1A9U%6IX#g7iXly!*JI&XzeJ;SW&N8->iYOMd@$ z_pX{G8T`4=@#VfIF8bqn5x@D`_`X{5`1ToatPh1PYClDUZ_D71I^8A0A6V*H=3lLnq@$XIl5EgbfB~WaoIY*GI(Dd&uTpH@A_lq( zi`X;Hhc!p$9FYh9KNL~7CM>)|*=vJku;j^a#WFE$foWjKR4i?3#@{QzMopYU@^@?E z=bBv~eEfeRYO2}gAww?O)Qni2r{y&7q-KwXkD8|w!WKBW1Dk4gc*r!>Y)I_62Rgwr zNIFe5`%BmY%YGq~YepZnso6GRuhxw3RM#@sZ1dpTe^bpi3YoSwTO;(^^!6jtX*y@$ zNH`x1nVcuEEfz9OHTzoZwZXE#bed|$_Y=7!X9GeeVEnHCW2zlIk#ZI zfDyAivtq=AI)*18=A01Y!z`lD?DLuU&bf7~ySk=(c6MZa|BwFNsdVG1Th(Ev7sg7m zvdkCCFRvxX{B_1PY<+7+{S8o>Z(RTErw`o!=);{Ldr&uhAP?*T3uY*bH6gIl3mL=pqhn@%i`+J4ZTpK2EVioDWbQi}OC( z_HiDn{lxhrkRLzg+v4*!s?WExnfBApXCUU7pBr5NF3!CFPn)yVwV%2^1^K$z-xi;l zhiP^iw4eI8?tDAMd12+TI4_`WKYm{C&<1t=2=aCDnyD>5{{VjK^zD4D{j~EH$hSkE zKT#g*^9*hKy10gEgSuvcd|iyEEj~X5{xqMtR;-=JQD+X`1+oWyeh@?+`poOG`?T%* z%$%~io)-afHr~*F z+V}+I+hDxDji*({k7Kga@7mz`-^TGd>WtmRine_l+%v4dE>`26e%HqJ+D~0SgM1s* z<=ePKW&AkKcluo$XK6oeaBh4X+(Sdkm^eS& zLx*YG*TwsP@=+J#VxCU`*@I)eCZbLf^^tfm|J$-x^#MQi`97?t{q%vD`?%5Ws>(y# z&7fY|_H`|%{nRxUl%}gKK2tu;=LH=*&!FzF3;IkSC~JLYUz)Dpl$ZQmJH9Sr-4>s@ zhN#QO=0ol07E>} zkgtpR)E1wIs6OA$VC|=!Z$Z8t`nSgVp-HB6wE=QI~Hg z(0-0x0pi}}=f<+iL!YUOdqL|7-21uB$-4E?!H1qCC{gd0=Vx?uAgJKi1CMTKDa|uKl$050Gz%I-gS>tLrIk z`?@A+KXqLV@^ux^$LoLUpoeEC^|=}KJ3t(#9UC9VZ+80KbM&>^Px}{x{M@8X z-v;^8Y>aXGT^n5gF8-?y>3%J??=I{mJV^|hb6nD@R7uA|kIhcR)^SJJj`gX_~`=-TL} z{j~9KkZ*%}J_GUK{BxXocrcfGYMGXgytX0_`B~?^5Zl!0`as+4XL$?Aoi8iPa|Pwd zbDHwpgVG+f&%K#ER^}^hQ|5FK_4+bLppUj&^S>E9)%Z`}Tny<8WuFCE|7W6}=8KD0 zwe}cSnmw*5Ywybxd&I34dtAS1_AYen{g`5pzKm8Li%B(jQYOvbQL2k``xD5=lkxG| zc}~vlNa#!RWe4DbSL&NN?W+s4j& zN8cC5&T}n!+7kQO;7_y1eUJxZXWh3)8*@7LbD%TLmp9OFefb47-xtRIyz;aq_H!YV zX73@@#n`zY`u5mAr(+MHGtHMv&~Ibs_q4t*jGb}tXiMy;fI~Fr?_TXAKe6iqA}?inYTN4Sr2Vu< zvi;;Gv5z`<(BBy#V&`7>agXr*WnOU}e1Eymu%Ehq0QvqBSKr^6=(D<9e?NBmU4P%# ze%j#q)13pxK^=R5vgX>&H)8)R$ol*>>Wu$BkUcnGu1qu9kAkcWugxgq&x1kBPhW=X-}=Tm@O>jbzRYMxhSzGo%mU~;MR_JB0wd6v*R+uXlc(#};N>e&&* zgZ;i9Vv(kYb7}QFjQS!VtB1On@2)@OwftA3?%Jh~KL1ZDPd^_4x%wGnqmEOjjn87? z&IjZDNO`Gi6o@gM2C@frybW^weN)?%A?~if>}!ktDUPmdP*1a8QXV^h6CIfcPhNEVy6Z2`Ti5Bh)j!VRe-L$7KjRy& z(P#M?w`-d=eE!27e){d|Ps^PV4nOx;S3l$T^>h7Oe=bGc)z6rG{%sw8&XcP@ZEpHH z{8ymv>gU|7tK)WV)^zwELfzNjOUH>VWmu-o4RgO6$i_AXb?Vv$#Dj805XV`kUzK!q zR$gLqDu{W!E6D0{aiVSdW^Hrc$iF*?G2=fBT;BO_?sy8KS{@W}mv9%fR{_yA@=O7- zkI>tLW4_F?=(93YQTJsi>&w`!gmx}Tkzu;61+tJ)-X3Xwli&Jq9_sXg%h?`je*cV7 z3)@Gi`!baE{hsN_a5++j%i13FV+M$NIV~K2Puq-@W4;Xed^;~YGS8?C`xplgroS&U z1${Q2b5N%prnNno4!+Dp^jVn?QTJt-YIi6PZPRY0{JBnf$uky2ecXENK^?viAo6gG%fOED z%6}!09kW{*<=AI;dh*lW>mbT7B^L)-doMcuObILhw9`)=mVdJLGvv3m&MP*1kdMoq zwyf>@wN07PpoKv^Q`>{5gWExrp?qtxT&ui(ELS@HZY*P+em53w(X>gwxV^Fd7|0&< z<#dqs%VN!O*4@-0#$4J~-)X2b&VPdJL4AjT$YZhL(q`L@g}V3Ae)@JO=y8xenCeX+ z>yMuozFz~uYyIMuOur_9>_Pmu0=a%|rfu3k8$_AOAbW7>YzU$Zx5W8)g9^(kV-*rH7?UpFqsVP%+$^z8|dJ%|PIv~gAPp%?i6 z0MRevbP*M{>fu~dsf@NE@EVL-GO>qoZMQiF0O|Mv`t;yb9m6NyFuh* zzm1LhZgcvHr{%xV>9=vS{D=0FcRGkVo&wo}*c}35NoudX^+f2l@wj{I(M~_-*v7;4 zZ25`1^>2UeXFP9$7|+undysD^$i;YfZByn;t^0c`*FR+_Z}Y?Y;-4qBP+mJ{*0+tF zem9m4oPIZ!wX~mpy#Zn@&w%Vfy<7{{FU}|XtY7T6bIn}p24WxeeWrDPZ*9uV70O#<12YwSmm&2#$2^>1aqLY*>`LH6L@%Jokk zVq$USIQ_pwOOA0aT--Kw#;i@s5&tG<%+CY*;Ns1^vp(K{I^&oEvIlJve`|x+B3%Dg z=2q0{n=3;d_b3nLEBV0OxLJ9L?e!qaPX*b7I>v#l4=ba7g|;a(9z-8}nG2MM@>Z5Q z+ltZ2DoQ|1;>8b%$vVqfYu_TUM|CXP2EdMG_zs)z6D{4P^r-7*BS&)11yhBVZ zE>>?n`ql(d567$@l%*a&w>v8j<UnbU*GTOBR}<>4x+y2 zLH3}IA3)@>cz&a8i>I|SQ~Rllx$*+Y9^BvB5+`xAew~SWTAV!plgHX;$s;Y!Dd@NQ zMxmY-XGwW%oD;R}$2q~#bqMNioQ-HRuPyG(PuH*IoiTr|7t%3npL->JrhWF=IM3I9 z;yfF~Jb40S59YubAj(pX`_V{k`?`4kx43+dI(0n>vIlJ*0U{6Ut@*sK^7?j$X+M3w z2}B=#pLbCn>+>LO`?~sTKXu&*qAu6xCbav3tj`uZ#>9EqR7=L=&ktqo-1)J(YiA|! z1t5#vHL7b0N_)_+WkKYj58S_+wN2l74M_V_LH3|eJhxciTl1ll@>1UoAnKa}vIl)2 zey$J98S+u)dae6D{H*=-hkFkF=Rs_`XvseAud_hZM>~syC`0-bWcw{ncZTmJ(b^2W!Cul!yd<*hzP|xAY!?|I8 zl9xwY&tF3zLyRfUydg%Ao5sz zdTZOohq~9%e)@J0$lcf5dj4v0bj?IPEl%z=)yBDqqwiDI=f_DKZk&vRZ9h(~e~yt3 z0J(9_$@3Teqz&39_I5tG{;hq^J;$B^*@HPS4MZM}@%+X0pQekxTV0b-C;yWmd(b9z zlZSPGKV1lYoO{YKpZNSQ&Cb2r&#_BEyngU~zEydw&o^n?kN+C&r>=8B)b%9D9?T2c z;5dEe9Flk}2jYH4pE*Wb_Fy05v+=Bg`e`8QA?*)(31kn-^Zak^w6@P5ro4>D-5;4l z)WLpho8{ix&oQn6e_x^fWkKX+-OAEG)(3&CZ`K~i$h)nMF@DY)bDuKwp%aMxoLlP? z^&AXhep{IhP-j2sQ;_c;``!I}RkV2yXTOiZ3QoU`gC*l5Kj|xwZ-evd+F&epfAwuJ zPpoa%2G@(VF$;Cy2KRd3#-HdT4!(_FoPO8F_u5Z8UxIuaY3I{V9bI<*ICotC*0yWo zZSALx&p^Hn&aoc{*T2=}+IY(8cWq44e%j#q!neWpgUUm_oDZJ=(`@kkZ~I*vw`f0Y zd;#)pERVis5V0Wn>(1YkE(VXa!;&(zH%9wu=PeNJybQ7j`Fvd=`qFeAul>|@8HhRM z>Y`3x7tfJty7tk2>UtBz($&SB^K}hIUz)Cg+D{$RK)x=@__{Vz8QS5v#jB6Dse}39 z>tfs2wYths7cu90Wyy0AbyMaUEnh)t5AwOXxOXfKN{f-tF|DqfP+tJ_GRPhU)O=kF zqAyJs*P+#QE9$;3j=Q>;-@kzvpO4p1+Q%5*0CE3u{bIiPx|r{2x<1l=>bea?|6c{! zgZbv`V(z5rq7Uq+uGc{H%hkpG-`6z-eQCNL)qd)l1oC4fe!i{=Dnot5+U6JWwtn$C z!q>%^eO*_pjIZlbN7niPl1($z&7 zU)P%GOVh>kKl`cUM=f1loC{x9H}s|H;&qBt?fsD zfR6{|+&un|_S62IAb$_>_oH6m`BG(kU7u(_b@3dkNE5-P1ohxPhC?$)aB+^ z+J1D7%J_bruKm>YFv!=%nEm`ZR%Lu$higA|anJN)q#mw+9?T`~M|(@F9IrjKpSn0d zzOJ6=qi@V_>RJu71Bi$9i*=4~Exl$QY5#R?b36c5yRY>EFYo_d8+Ko(eIE3e*A2`w zo)7Ke?`zc6qNCPdtBd|vU6-Q9Jact%%$<|f(Owk9!`H=J;6cBrgQdH+$nWbSW@);9 zMK67%4r0iX=U;np9$a0F@oNxee7`=|e(IPEV(G@nwy*0Q^jTf>(Ozd!&ieH<>XhXg zvxk43MZCyobY51hW27FgfBL~( zVvH+k+t;^foEZsaNzpv{(^wCdW7uPuZspC5>-F#tOt}f#B zEGSLa6WUK*Q$Q@;7}@r9J%B!|i>2Lul|(u5UpsUA)rvqmxv|*L95cQwOhYm=o?irtL@jtBkK}FYTu;t}p6x_mH&x zXeX8Nb#1TxHa35KrR_(XWa!$^(KQ)$>T>Z)+mBYs(6yqYtCXUPG5h(oWQMM;j;=>k zmx~wm__~Op%~h@ou5-4DlP#Y>-NlQ!g`f7WSmCF=*Qz+xG5uNcph{lCv1A`pi)MK+ zH7pz)TLLsMhzGYCPO0nus%ZbI{r+_SqWuhG7Kl?a9b^yQzEI}hTG9vV`%>G!zE8BD z`o06vFIOL7d>2HyEZ;emjGMN&6}}82zi*3M5&LM1{?PX!ARgB5NvK;n>Uvb$wvRs0 z7Plg+i?PygtBX8$={W2DTr7@0>af_{puE&)=f?VTwKGP3YyVR1XDp*YoMRuiG0J0c zIZNAVc1Aj5uALLLpLRkJ?YMFFMVqmt#o4H1HqQOfrft{$@7f;bjM==V-rbyj*RLJ5 z-{y^L8l*h)ug`>;jZ0$1+>ziwTeW%~Gzoz!nKDTx^m-1-01($BBD-D-MXUz4B zIb{8H{pzg!^y_O-8ZO*sC~I-CdeZC@A08ZY?f>lbyY`6%58D3<TYgEQvZUrhUH{{~Q6oZJg}*f^P2S@X#? zX2)DR?xTon!QsY9{cVZ!bMQ0w)8d@rjJfvhqX@=%6(}vvS5?-=`J$uC?)P?mJmrkJ zcDVlO8|_>Ua^vKs>;WKRM4r~x=bg%z7U#{*m}{TdTKl}bryuV6?1DDeD1D$D_ri-o zS$Ll7jJbBs(0=NF1?1bI4c89y{5VjSox`0m*Uo|3PyL)9mYhp_a9)OksF!lI!|T{A zJ3BjLuALpUpZdA~`*t{wZJ9gXie&k)mNVx1u!{E6HglY1Yjd}(%B1B;lQZVpA!hWA z`ajjuwUah?+>5f}p=~?n+TmJZp3%-{TKaSMqw-LWbI0>PWzyoA>5RE{KGuHP`2@t$ zwX-1FZJ9gHf0hr=IAg94Q?#G9d2PVb#WZc*@%*1<=PqZ=wKHD(ssC$`ZzpZ;xZh>j z8S9L>cFxm&>i;*0rHd(Z=yVYEQjT+XsdnkyuEGD~a+s9-lr{A@`z0>d7-b(vv`)QDCoAtJ0vKD00FtMjs`s@0&qQmd{ z)m{7P*A$TJm&K$}c`PPfwe4fV>hjXAphh7Q^^#KYigro*5w9@A}JS&wlzl8N}mcEh%>&h~tda z>LU;PidtF>nFH2_@9!jM%=$~-hn;@culu#1e)RyI2BHr6JeFwy#5<^~<&G zo?czsmnc7Nw}4#Rw7-Uq(+{i9VzQWyQ6Kl8k=jo4>jY=awSScM)Bf@xJ0HB1J6Ol8 zey)ETn;-XZXUx^l^-me?K9#khhq=IUQo`>FpKkRK!0ub)H2&$sgl`WP4I*^Y4?5El~X#P+-PS!X}(PX+PV z4^#l*^cpy)S9cqr$SGt2QGKN)N0>NHQ)$r8)_&_gdDjE|*Xeg%=5|9~y8OJBC!yp) zUtG9o+ipc^wr60R{l0B(H@4rk{f73__6s1EHYI4^x6LWFdi=DX?2K{RY}}7H{jTka z+E1G=f>_$PX@ht3EGfgdZ`C&YeB0MMW3FvpZdiX^+q~RhKW)CGrHz}Iw_@9drHS<%aEd{W?_p=@;kH#Uw2k_Hy+2wz=I{8?No0oPO6fFE_|fn;&XvF-gmX zO_iTAzU>X2G1vCmPQPn=Rqdzkk3eqR)X(jPC1sckE!s}A&8vC#lU&>NPQPn=QSGPA zk3lTmxZ9Eo+&`>s9}}*B9==~(|F+-ti+8I$=+75g+Vzo^3!F2n$G6S(Z^v9rxc+Uw zYny9=2W`*P(#6Ez7p4feiOsjo_0PkPo9o~9yS90|!GpHH)Y8UH9k+mZP=>j1gS66Z zbN%!1ZFBwGe%JN|+E3fFKrC(C)X|n)aDDbM;rh4s-T64w>399wU;F9LbP!9cKP?yb zP=5OC+uq3;b8U0|Tc2FpyxrhIn{R7rF=4--3%$|DBh5C~za4XJbN$!Yn$ue_Pe%u{)-n8`n8w#(}znyE+*vn=VNE(PqWSSZ*91?x&CdxYkO1e zr)}ctVv?2%>o|J+`QZAuHeB0W|F++?&GSF|Y5R7N8#iNH62x)JFc%uMofbFOzqR4o zrcT@M+Ae56ZQlWM-iw7hvMgjtvL8uUW-+Z_Ed1%?A-(_c=*9x_J-^~_PhICE4G z%^Vf{GDiiitkF}5=etCfyN9V|@rG;LJpv~kS#y3V^K@tymyGtJE$;hPmc4cjv%a8? zv);$4hwo9+_JohK)z=-L-|Y$i$=1g1_%#XnNoC{jyFKA!Y;95|Z!H@8iSbUZMEEFM zo0iF2kBonb@ef>y@DaB9mC0L+#=pe)0=KEss=A7pFGGI?v!_?H-8$dw2mU<)^Dl53KAGXK`1@h>s{ zp(_ziWNYg(d27-5ml*HtN`&{bwN074wP^fHjDO@xg!i$9i%!pfYti_Z7+=_x2=8U9 zf0?|sX#7izf9y(x_pr5HnY^`V{7Z~?vFl#Y{wmR0l-juJWo)rTt4pG_c%rpLqSZCg zs!z1;v@LfJqs91qF1F8>&sWI33P+_@elCf*xHl!Q3uH{rF&SfWhRGO{^Gn8&)t@tggQ@CYbTH%(pDBLnrt#HfA6Kk3b*D4!?LTY zXe7F#ih9blaU>dzG$nc?8QUB2uS!qLdLw>b$JtRqa$A>QdJ??M3M(U{kw1yvji@F4 zY?nOuaPN+M6{+-dZ1Rl9-76`Ter8XeXL)U!luEyzNS@snDw9gTib-BmbS{%hzjjJq z$>5QV=VAI4Tk`q|zb*5m(ytSfS8aGq>`A3xohGjp@$k-*O1~yfUZLXAlqb~}J+e#6 zoj|(f#ml7nSgFMIfAVS^k61lhoO9CdWh3?q$XqX_^Vq8_b4`}clYU)gw3b`l27XBF za@I=fPjJgMFD=SSlWU}?mAWeJ>MUQGiIHf};hH7y+}6gqBKZNK3gK_c2Ejt zwR0sp+Go(eXqT7k)#yxNuKg<5=Wd+T&b8`juW-+8o}z^n>~sH3YUgg`Xs_@@LGO|( z*yoO$)V_UEdxhsEp;$Jb(U~OiM1!j|seOl}_6kpXLP0#NV4rI;seOQI-&M`ha)g%qXt}SJ;U3I~4oWI{ za@Sfu&OM9!Qg{x>%EyTV_q$MbaJgmSOJ{fB4U@Vul5TO$_luEcxo4EDxG*Ul zU00Pjx6!qk+#f`mWvy>S+ZQFJ)AKv|{LQT8-ju#LDIHz=JVx8mRZQaPp;@aNQhIDs zn$a*9lTSmF&pyp6+<;t{MAGA;+PrQ)i>^;OCbeTZMjP>2H$0MkJeP&6eyeNzVo4eX~7Zp|a=E zby_u7dkN3mHe2%4E$R7E#C)G@&sVJMd3046Yvo>2evK&SO*hZmHe2$vDYn5{Gd&-X z?Rn42o>#aAt?r69F%NBM}qgk5K?42D=P&t|k*Sxh}b0^|!+dRwtU^2dC7~fvm z@%5@4UxlmgTCe&O@%{B|c#*LsWA4V7hiAvUQstN{+zXiB0GKP|=!z$CEtP&Rl8CuI zaz?KBk|-=o6ozG^uySP-D%`Wwde4+Vp*=F|`SM)oP85b_qp(V46x!k5E`dUOd9^_bXGK@(hg)Qw`HnSj`7}cO|0nyax|_cv(tkjT{!^`f`)nu=y}d!^mkP(SCeJCvs$4hn zd@px6w^)5_ElJMN?4ghBk-I7Bp$GQaRHR>YiGG<2(J$9+%wf@gbGEiV;4#;gd|J~Q zw;P*&FYLv{ec$M_(JjRu@t(Gl5xVi1XK`ju;~1=0F)EZP_c}Rlo~s!@VvjmO^0>$w z>M_Idp!yX#pT6Md4e zwMYtPl{9u1PeaGkR7hPwt|t zVA-8G|AI;48?*Tnn$mPe`=88YHC{72Voh-^_A}b$WX`Mcnwb@AifggXXdjiGts1Wv zY*lCUWb@J4;H}1MK1GVXi)*o;(S9tMTaDM9Th$rux{}k?c+GpE*t@tE`^i-!`SSQ| z)T;4%kydqb<%rHn)LD(!{Dvp?F0RFXa`(2x?>1tdxE6EUwG@9_P1)AvqUZPWG{1U# z=_@(5-n!-VbsK+^-nxcr_7>w&>$m=B?xVTqHRGjE!W8t2P?^FyqA zgUmY$a(0&8P4Y;dfpJd~+3}R!NLx!$CgW_m8^y=W)lBd;P2irIdeIZWCT6cav{ z$CoBoggu^-BNX3^P?W1X@l}xJ^@X4)*QD!ftCGJvgU8s6P!vrzW3uKWDd&2q_Yj_E z0qrDwT$VkOi`jmLGKWc9f?~qQ^7zu^!U;sJ5yUHz2+L^^miMtHSPH((TftI(MYf){ zDtWyVc#LIYX?{KM_t_I%#Pet^Wn@9pPuD~9y9x7q(-?`Kj3$9eclOBKW#eKpCuytP z$8tQ=PxH$bb4?~QC|Xx!bO~fy*dsHTjgGmq_AK5*ME_2U<=B+ZW2&dJp80%( z8ls$;9_5TgA{a>?aaWL>k$qwvZB@c)5O|Db$r;)4{yuwxi+CRGR2kXs`6;>W`e}aI zWY$=W#|n%tflLqfNX}%V6H4BC7RzR$y)BkwQ$CNWo=#+TECt#K6y?m@QO?ME6O1H} zxEo2%NdMZ}s)W-(@EFUIGY|Z|_5>I4JlY{MvfcAja@)nl{GQF6<6=CPXLJc`Xh(8J_Mf%1RS75l zmeW|4oO$T)wI{fU=g|(Ck?o$JlG`pW=2wh99uj#18Ob8anQU~77SCeYOtiPfa%{@y zG1b!&=WuBd@57>;c{j=#SrHvL?~+FwDHrpm5;{9jLRPe7iac*^Z!3aQ zCwc687s~HcO{T}O%PNdeAOdn`lKfZ`t#nMx&g5AvL%qE%mSa;sd#Ro-!c2&sUdnot z8I`Bq%V2B+P?R_F?S$+#a`qMMB$sHPT*Qc(DIqcn3g)-g{`X;WwJaI3k@7_=M!utBmN{CZZ`kIfRzad_ALyUCgYkS5T$0b` z1qt~cgm;o$6=LgsBFLIxCRe<|Dc^2X#kmJHbWjTAH{#~^!shvqXiM_QuffCPC}*C; zrSQn_zQbdMN6uC$Jn{?g@EGBdJu-zye#;#mEj+TTrSQnFw!@=@M^;t}kNjrD{Knn9 zwHWgxcON2QehCsDAsS`Jh`FP0J_PG%jwE*@O;-#5;UX`27RyK9TF8}V^eu?oIYhdz z5&pwOUglid@?_t<0}$)uvsCd}u0o>kG32T;vUR=iA1eAJGh+G8t-Q>@7PcjG7U{l8 z_zw|z`Hm}=?`I_h`OR!g<|@)XUic3d`N{l@<#~NB{tM2$!;_ZmT#@eEh5sOtpOTdC zYb69HUb%_9pdRVIOXLp}`6nXzKcm`gsTFch>K`$q3T`wMV|`%|zXo*s=0e*aw|(gvOX_$@oPYSY2=Sl4}Zq7xHCq6_VX*_r9s^8e7S0Qtlet#xxCgV-v_oWW(%TD zy&XaHa~V)K5H}<1v*owgxL8ypZ*5sS)JM52d*pX*)hd^U1>)QX|o52 zm(aY-$_o&Z`&5@DrEd9mDsOYkC$JzC|?Ae5stvW^y(t$1hqA z$>h9TIp$GJ@931_V>rKZET-ibnVe@S$1+-OlgXJgs55KB(T2-pZ(_Y3?r_bM$@QMY zwR|Smw((jCC(SRhmRrR4=d#O%A7^odlgwO*=f`JqZD-IGu5p=M&p2GGXL9v6Xo{|# zGPz0)*Vpr9#1}5>VAUm4*F_H3dS)*u$12P@h#rv1b+E&=T^84#7Wb2~IKmkY?w@AH zcSejT@hbQFB(;=28g^(+K0K*4j^kk=9BR12olW$(MeZ1mt>diZ=Qn%qpC+F0Xyq&z z%u_h+4tkMtu4~E^&L5TIE-imFHc~i`GT9P7r<`AAa(R#2|Hvbe(WW+V)h z^TtfhwH29_mGjC>&ij>fHRbGY;!lZYMMY*!B+`-_G!WkOBWFOf* z^O~Zg@lm*T&EyKJ;`-I$+9gxhu_gksn9cQXhij)yT|*2CqAQ#0IfrXdrmpo3lAt=^*K$b4tuA1{oCP#R;GdtU7=?T|&5bdAIHOkR7(OgZ*PPj_Wy>4H?(RD{A*C>bU zVP|(v>iWasx+|0G1ZNJ<$h7#K!*ygP*KlVJm&oLL(c$Wt$<^DL!!0wpZgsd;&*H*^ z2s6{ynXAJT-0yd0=bTKgjT}VZ&E$H>;d&yIYb6KK6*IYRb+{JIkFdYN3)9j4ElWQ>t(b<_?Cp%o9XK@{2ao;P8Bh;%9*+;j|TWODX3 z2#2>Q=a5X!JCt*xaz1F*L5iPC8l=M~l=Fv7&e6*Gs&a0e#fgVw9YcE$eo7Wsc$rxf z;n%9~d6R!BJ}#~tziC;>)Hzl;=2c7wWa=y^#}ZnepUHW;a&*`7U6V&Ce*Uf;x0rbe zmoPf<;1^FlHjzB)X7cD@ou31h^F*UlIA2@c<(#gZYb*NK7*0Hx>log%v2gYM7FYO!&X47M%iOc2Sl(Jux17Iba_Td`$ohquoa-r;R_FbhoD)6H ztui^AJuDB-(Fmy7MzSiwobubN1tz{M_7`mg@_D zQ_l6wRa-b%J+b#0W>3zqWAf-2oy{J~y{op5Vu4;`d zyixHyzg5oFbtXo&%6YeP9@8pk51oMnlyhezSsqPzopSD}oC8gn!Z}N=A1G*;E2no% zAHPQ0&ER;T>RY2C*T0nO&w{K4InS5t8mM#qbVaU5l0$RA`P zxJ)^FIh@C8>^bo}f1+^W%axAdTn^VZ%4Mz$_%~9G#(!uoyf;rAZHw|=FV^^%5Dagi z{S&L;9k0CSRl&QIBEC-*yjLjiMpf|Ib+}09C^nhRNt?==$(yJO>ghseuE-%=-!CIv za~rPzDAyttxn`+%T`F=tty$5vBG(N%*Tsrlcj){rS&{2t^?s)AsJj^5y_qG;2$K0m z6X!?DxrM9s#CAbmnEmUp2@FaIQ3az_=V~`)aWed+?cW>RiD{GJC<{W z`b;(aQ1$Jfr7zTTRCt2woX^CaqVolvpLbN}UYR;KGb7=Vs#Bj-rs#Z3IbTbotAE1a(D z=bx%?fYD#BFWkxa6yhs?xqiJ@CG;6dIAt-}%fm@}CVNr&e^wL@YlXkJ@_ni0^{w#V zs(c@4xoIo>MfLl&D)~=W{->0Gnz?(m&xHJV@w2Xu;ltJO;%sj)yi56qRn{FYsu{1( zYQom|FI0Y;fnSYpVMh?YI2vsqQTP&2_G-<+r~ju>3!nJJ&Ev|5}QDwfy&Z{1aNy z->BGI{jKra9JBoUwW9wQPk(FtBXpju{?3*4@8r&HkIKB^7v9`{Y3|)Kv0q<(KT7#- z(>-c2o%2<7&m5<@bF=afSN=m<;qR)kZeJz;NagRX{Q1iIWuFhKDd)i&9zpu{it;#=H_Z`c> zi0*01kDt4C499uAU#jkrx~EN4-BY#yLggQ(x-I`}s@w8!qH}eo$3H{$tfKlKQT>m4 z{6*ED#lM7K7H0wovF><51>(Jk;j8N21QwhBqPvP8F@wiqwb#0|^ zuAoTRjM1k7<(%@HMg7h#{K$Ax&J}jI7PWjklhc0V&{?C>?|)KscG75O>kjp_k&r9I zWpQjxkt$ehyg87jiGC)sE1*SnF0_RIB*WhM>+_Bl4U% zqR-jm3~&ZH3!FvH1ZR@7u{&swLhdCe*49wBh$H5g|7y&I+$)adD&l?hFIb$fkbBLs zMuf9s)j54#t+kRVZ#Y^jWeTmGSjfFuO$>$HG)HTepX{fv_`2n-)_g7GraKxdVXc0? zT|pzTe8~dyb|`k*<$OH!9@bPt#P$eNe5ILhfIx0kF+bsk%b$ zL+$NU$bIDK>RiZutRwLC6KAB7uN;G~pQg=+*ghcbY`yaTE_6D?AO)$Q^@_h z9Xfb@PGq{$o4ZU9gb*$=bE?7IHtg zqs2*u+<&Y^8)+f;OFLS`miJ$4k$C>vj<#@-^PAc_1grW`&|#p%K}Ud&1RVuB8gvZk zSkQ4GybO{*0dykhB+$vAQ$S%TtN&E_94VipXbrm_FwS^_dHL^%|T6js>KGFbTDf273aQ? z%l}1dhwKZ9*V{I+g=4EYd z*5+ev9oFV&ZC%znv9=y-3$TWZpM1C=Ya6h(5NrG+Yhh>Bdb74LYa6k)2y1-`xp`WN z@psKxJcFreUa@ehlKWQe6biXQdtg?`)m0H`dq+t$80kWV+`LYd%n4=#^MDz^x#z5N zzB$vJW6mz;l{3n@J}aNk$>;O(`GS1Dh--<(TZs;ge<=gG?k)8$ zGJuue7+-}@5<+U^7+1eejuO! zlFu3P`JsG%B%dG4=O^-M{;De43b}^= zL6pdaqK&RSS4|<;*v`>Ob{BF@HX5_~&AK-$-mG=A%FX&VE8DDTvzpC1HY?byU9)P< zdgV%8vYq3&4f$tjg+gvA8;_YCvzwWH%_}!WGP}?V zh^M)o;~9i_EOja5mQKbqr}yYWZkcwDhk1tkg>E*EIlY4xa?7@J1Zle+u0p%pi01S@ zP{_5kb3~jI>|{M`1ao3e3c2Ol+3U1_Wo4SwNFxSI8=x@;@t zR&Qs&a28l2=~HWYR>-Z{&OR~2aF$)m`qkP_Sjes2&K~)@9L_ZBSnpb!$wF@3cJ>at z*m~BRG^`4__1oD4A0M0nHn1M0?GJ_AhVAUpZG~KK>w%e}WL_6?8@00sg9^Dm)`KJl zgQc zQol&*U8R1p)a#`_R_YB>zeMUqsb4DfMyX#W^(LubF7+j)eudPRlKPcWZ}HD=nJ`>{}0BE zRkTYo?(-yH&B`%r#;g{zPRt51Ys0JxvmVS!Fl)eMzsY-M{NOnpH?JnJAMI-WHtXK3 zc(c~cDmUxftZcKU&1yF5*sNf)cFn3a>$MpRVYfNxv7c?Vw4F7&yN!BI?|FsX9&<42 z8Jwdzur86Gd(QcY3%Mcx2V+Iz4Xq{CLT=a`js_>IHl0KKoIbXY8=j1$x?QD^+iMO- zvQ#0rxAmkg`$Qo(Vh(!Z<5Npp&rvf>Snpd~n}yt=bI^O&i(2bk zkJzyfvk_$HaUpm39Q1w0U)-A+Z`VTZ2-Z_wnFac zIp{Gl#@rrbEhaH4=ln$rs$6kE+&}LhiJ7@&Z>ar?>7!A$LYQ*+-6?S;>AO zH@ZD67jkE%TP@_yZU=k#P3bwly+ZEXcCfT^AvY$rRLGsz4mLU$a_3WRUf#d1%gg)E zb$ns_etAhf-;AA!ZxC{q!K;=a{g;<_o$K=QuChpcVP1Cc46gY=e4?0?koT19^75Xs zNIYb0Sc!a@guG*1mzQ^hMZ)}vM0uBy?@QxH;GPY6FSsr*@AitshsFkO_QfmXksF7+ z*ISpD_j5&Jq`c5BQ8NzykA}%OS67&|5r*YA-R~BcVz4GpYSCkk$6A0!5EmoNeOv3wk|L4ri#SdMuOQ+ zyqGQM2ia_w_f+fh@}8+k{M-D!0_HAtvrJ0JyQg(|dAC#~zRu^kipa&h<^Nonl#q8$ z>++&7f-~D20BIMOWT(tjo)rjUqA3*x-DV zo9`zlCFCu|y1cxZC=y+h5?#wASibyt^{x8^9(TRF(ZcdC=z@>X13KF1AM^nW9NHbnB3oQ-7?9fUQX zk0e%+Ki46CGiRI1B<3;_9V3bU@@G4uEN3i9ujV!q^F$JhnJmQD81la>v!n!G{xbja z1tU>sCHTH1IhFx&MJ2iCHQe)A?r@5kIdX9iS-MPOek0K-l6carBt}ddq@;}njKqSG z#F;Tp)ZeX4Vj&|TZ^Fo2bc$Ci+VX!&CvC{vFm-u(*F_}WF*dkbX`_3Y4S5%(E-&w% zh{RTAU2yGDif_^h?=N|1wIP=fFCC-uwk`|I-Z`+IVaP;PRqP{u94pRdcyuiVKU_BY;e=IH;5 zWfJlW^}2j>G;?2??649&%OsXIGq+46Vg6jA?BVo^|C?|!hHge;*+}Arc-=ATUS$&9 zjYLZ%VgCHFtW@e=sZ64WkytL07-P;CJm1mA%4HJE8;KPniG|~w<=(MMnZ$}lqGu#w z{z#|n2HY|EZfG*{z)19pB)Y^|PENidm6TY?NXV~6Wd_$WGl;ry^6kQ;g#6;OE-%01 z6bbWRgGq*ybB!_y`7LH$UVdRI5|70ziE*r1CLzC+tjo*qA4TFRlOWRB+P%?B0DF&;yaW{8}i$~y1e|xPb7XdHn_fN zW8E?d`E6cZUVeio5{DUdDM1_Sl}X5N>FV+uMKfsrn=!ctp~U)S5`D}J_KhTNkI%-G z;Jcs6I5svCn?w?Gn?F0n^EV~ z?m8Qlac^O`x3t{&dmM5t#Vb47=u;-Km66ywk}&_-tz2(XqHmeRHb!FGNaBZhZE*HB zE|chQB;>a)GJ6Xrb83?^3HgmmU0!~RA`3N3f zrxN%9hn|h)R}yu3`4s~t27-ggE(_YMj9Y$HP?wkQ{zd;aCTi}tl-RsXLcWi$%geXs zA~8AMp?USVMVW+r6JD2>Z>>dQCzDT{J;tzQnS^|cT$h(`d__Y4LkLRHEB@^);uJ?M z-@?}AheWftt=VsRw?K)l%Or-H*&7x~^pE#jULR~zCNbPd>=j9v{~kg1TjuY!WfFTE zi4l=R9}_uZ60iD~N$g`J_KhS4nEBw&#yGYsli1Hl>>o*7AMc)wgMXJRiPZr{;=oA4 z{24>pp&7>xWfBJ&iGw4FgW^o5jR9p6hZqU@Rzzm-7!x_~t{4ZiGU=6kQ&E?f?;=Fv zCSzl6aMA{TjP6OucLa5L`7S^tO2$SgttNURxOfid!($|U3&dtF|h zsEdU8gZ**`N3V7+laMFfb$NNNEfNRE`z`Mpb}5sPXV!Ijc}^`7znD1k;G~VgWfJoI zxGpbGd`04Mvj&;%yqDP(w2?^JT|u7S*5yMxgE@>sQtsY%E8{-Z%-%@L9iD6UTV^5e z_jWIn7-b|*izMzg>yPtIi9O0BPB#)~L=rC>3C=eq_AHY)(@2btB;GP>gY(UuXGodE zSw`aQNa826Hs(@^p=A>17>RQuiAg34ITy4stW08zkvK1sXfX5LK_!O!5_nqplnJ#j zhBgLm0@@VB&752G<{)mP+!!nTnZSosP1S#+>N6GKw!@8tTLTw6moFD2mlzifmjM%- zsmkPIIx$H&?VLzX4Z$XS1cV{(1=<@l0<;fkU(kM_{XqwS4g?(p!XH`uUftks&hre< zPJ9}|)xlLroS6a4WL|IZT7!4zykp>*nCEYv|9EA=yU}LQ(x7EP-9XENx`SFkJwVHW zcqhaA6W(#~9wNYBDR|nf{p?m4LSyNEa*7U@t_kxCxT7_oeVk! z6oxr|o+_Us<#UvLo+h8C%jX&Ld8T}hme15bd9={3(DuLl*MF(7W7liL{>|Z^x&Esy zFk+F$y1BX+!dvOng1ap;*N&ZX3-!-m(6xVu!TmezG9ZU?K(6JYuKl*|zc5?7_V2J; z%Ozd=j2?AEr`)<1cSYCk1F?{nXLXUy2IdBav+=KbGkf*#Fr13_f|<)AGkf>%Frwv3 zYvyvA*+4Z6O6*e zA-(m=qepfd1lqa}HLg3Lo-V8jBN7ywH3ikz1jYYYU4mj8K@CPwJJ$z0)&~Qlh&IL$ zqBRlKGoqd2h*pF9opOU1RcS{P5Thy$GyyRx^?XCk~^+HatHTo*!Kw99bV6ULPD9Ie!F3TefhgADmbp93Mq=DuxiPGaV<# z5xLWGq6tW*<9HL0GaaXj=Odv^JZG~e&-uSh!1FW2VN}?L=V!t5GwXxX>w{5|=jUT6 zxvtNQJujUO7cm#Iut&wNw_MBJ>D1<2*od8AHS9?p2A$FOsI9>mt@N`cmJ6U>VqvqU zSgwKwgfLb@K!t6@az0`iQy-iY1#&g|lYxwh197L|oVLYrfy6Nm+9eJ)Yl`DmXn_0I ziTkLqjW{kx9GBJyW9x&9qEK$bP;zl!8i!IE>&(eTZHwg!iRE^vmsr@WDVB$z0U_KY zA)vxGV)+MRxw<~MG76-G{$wCm$AP$Wa%J1%xJKf57}_NcHfxIG8EAm}{LhGFg|m$~ zZb2M3)dx4!2iHZRJd2^^3co21rF4TcC)c$tmhlqHb5Jj_uvt?qZ$blNc}YS*g>A%g zCt|t1KDadsWE%RDf!rPk;?BvfZHwbBiQ_G3mpIt0DUOe!0q(ym?xVss;&=dY++QEu zTOZsVh4P7E{nQknq2N{&zK?6sjYbycD&22pWpwVW=9W@DuB*m1Z@m>%eh$u-hw78N zMJYzX3d**3Zwy1}Zq#vsCcE6KFhylwP+6%S$bH)>w<Ph0djLlbqGGwQt(-ty53L6XBmu@ z-iz^hSMceEUcraWn($c#8i3F8C69 zh|QWX;{TC?h}TCU7_kkEegH<_)d$~10P%mx0pF&k=!YT+(03*_$)TSefcSqcwfy7( z^m7c5n?tHY@cAYMpUtW3=X89wz*y<07@r>npDocV_^??MK7*hEac_%4@L?PH%mzMx z)Ca#s`0Qx-b~44zD3bX6fp}~JCliok>wlWCk-kn3G|x*nE+M3ez#|~ z!PK5_NIkRdim_6MhUmev@W3X=5(|!#8_#m7_B7* zt&7krXt7xnTKr-gXkCs%&|({CEf2JMGz8rvz^*lX*O}sa6iL8(IQiAn0qh2FwyfBY zJOTEM0V}DXdF-B|!LF{Jq3Sw;5gxKBC0K{%XA&9XJ#8w4j zD@SnMW0>wW#eFD}aINg**BTC7_k*)#bq}sJVz}J=QXSRj*F-8`BOR>=FjiVUMr$=e z>p}DiT5Q&Y*6Yv!w4OsDXt52nwgFmOH3VBU1e-Mkn?|s`fzg&t8k~pfTg9=Lw$L2o zL-oxRKt5F86m|Ph{jy3A)wh+P`2DB^#b!-GeGCl<>RpKi6}A!7AOtm_A=thl=pRM& z35F1@^Vo1e9FaSl+nazmo2C9HAm>rrj^g>JP$r(US(E4ALjxS1DGsB;Has5!&-Z8u zc54U*Hv~IJ&i{bXQZuxYqhVM8!;9HXDn~tFp z+Rrd0p|M$0X#8IX5z+59G`11iz6fnZL$FsvFf58|ZVVx2XHrJQak-PSmkCQIWta)e znUwv+^Le05JZG~e&lfeG&o2%m1h(P%VetHrhTx!v;DE^U#W0jir$b`TO9#P4%!urz z2gI(IUkm2Sp5-1cv2=lYiG|IYVrhm3gitRbpu#p{IR>#D)esyJ1+p~ylYtx+2jWh_ z5p9d(Sczj9XqPzHtSOFO&;a*a#C=rQMjRpHIJqG>u^~7<3S}h>C9~<|IF!TATp-2LBxrt3~u*Nw64F_k-)gD0OVu0K< zQ5~{-UYdf>Ueq-%9iP21R=PUI=PJR6|2Mhd!)8tR91ab@hrbCIeAos)q>8Bt$nOBzsGBy93eD;B2|AA-R%nk0C0lpybev24}(O`V@?gp|ac4 zF*+7wrQ2eRZWWACbqfK!ZiX=ey znAjwT9&i9U8=Nf@J%ApF0djLlbqGEaQt&y4x*kZ!=Uj}HCdT;OFZhf>ui(RGP54|1 z4T$?<6oL=iz~^z`^H@XhNQBQ-hVN=qj6;#c=P|@%6KINq&p*J~GTB>WQ(}BdDkur` zhyj@ZRX)$#XFk_Z`;>IVuEkhsa*Ws{LF_v83Sw;5gxKxS0K{%WA&9XJ#GV0SPepLu zVVLeT#a$?pa6RRu)AJ5o6TsQ>oCnwQFjFp~?(RxlI&X#|9aLtI}a`Q`dRG(jOQu&N@w5DOK^sgAL4+O2Z&?{)M zSrb~_@#9^fRYW0Zu?@7k7yAX>iow#wV5wrzR1Atm`!u!%3@ts1E#K)aQ!{@Y)~y&n zgkHL6b~4@yE`_@Nxm#0l{K)HYi#W1dsfh0DdAImor<7m5Id_Gt-rVPgW`4E00<4yL z6xrlN<(A>+Z0*^&Z!TxPacwCwm=(b+sIXZRD(gW56s?RxP+=RWtPWIGEe0zWgI>j; zXE9iz7%Ue7vp#rQ)-1LxP&D_FEd*v&2bh%|V0t;g^o)U7A+9c05hJ;0j?mc%rb}y< zp<{Ytbk-1b`hZ!`VY4Q5wu1(s(+`E9!#2?A19W;9gAIzodc|O!Vz5>O&Gujbcm|i{ ziA(Po7k9~QU|?a=l-4s?FlkEbIQ6v*Fw7wRm0@3rYX=ySxY(>IuKl0^aSf4hP+=Q! z4M1Fji^0ytV8>!GFbZmajAEUbpn5W>!RbNmjP6mq6Gu=x7LoshB&LDr{;m_cqd0bx zI1YebiG$6W;ur-DaQ`@Q9~HI{$G(VTL^0T_7z`^0LyEy3Q7ET@p=Ez>O^=A9DeVQ! z?c<$cW{%|X&X71?_b}6vv8I#x%J&3I`521oKf&WHFbf`R)`Z7p&;S_DLm~Of zHt;wCcpO#?4k-o)6@vpJFfPX^uyW@0uoww9Sr0Kl$h;opBD6XB?RM0C6p%&|@| zN0$Y2sswWzG)pjS))dS`(0~{wNDQd3jbP43Fr$mX8O7kVVlXm_q=Zof>deY$Cz3Oq zNKT6*;hAK%S#2ZB;y6d*co=#m4mN9w<7sGs`;UwJsIZMVE=C*|7K8JP!I&tBXE2lu z;=(uxH?_`BjbTh#3}YpRXQ5VNV6&ze-hu|W{*t(k3fqX`8pJTJ7+h5ht|$hVMPW?G zXfmtDrH64<97gF1C#fzg3*=e}~>8`S^&-BDw z-<^WTzriecuvrrxe?S9Z_z{I{eQX1d2Z6`LVsKwExThFQh`{(0qrl2pWD{c~-2A-H z03lo7JqZ0%040Ohq75iov8}@XuoKXfb#= zilrV5El(9&8Z;caPMs2mQ~VQ$oQZu!0_g?C5(t|$1+pGAAduC>e^l5;Akz`Zv|{i^F?cPCVtov?yyIP_Op604 zy#X)nl)h#n;grf91Ft|d(v11!*&=Vgjf$_VVY2j2*{qtLcvjyQF#3R5z+kf`Ft&jP zV9*bR%qrUeV+O$ZpcuRtA+as`0g;){m3Zy>K@5XCpYO%_>j;TM&<}{5dHW`Y!JW6S%jWHSarICr z5Lel($<>pf0j?e;9-_iFT>TZU{!$EnE(SkF-kxk&PccP^f-5Qh!SydXZTzw9AI120 zYNvv;<@X{k@xNd~qX=-ye{ektW2N7V z(a+L;6O2wnuVBPxO&DDS4S=zUogSi`nxf+8GjrNJi#fE#VDK0^g zgsISIb|u2psWFD>QgF7+-eLuNNl`(8X>KUNlN8yQ=W3KEDRLLt0sTH?mr-%2 z##G2I$5?6p#t5?c8X4&o=oQG=tO>H4paF{hfkGf-8;~sq$QEe~I!9pLZ1`?5#ds7+ zuof|K%J&3IIAGlh&X&a+lR33S43@iiREJ>IIR&5FsB4LIeE6qdN{h$%bP;^+K(FA# zW=;5%paJ;YgF^6O8~7{(e3~1BB^!gr2%?7#>m#Ok6h#uEW(T6~4n&WEvt?N?pSq_* zq&ftmC7pC?Oo8j4)Z0BBuE#M}S~iBOo4_>*y#g1THNo`(GypFCDMW#bZNRl9;M%+~ z=+_u*(irrO5c`+mo?(g)Q6v%D98vMQfGcnt2eFU9*|K$G@{)I(7_pKH$_ngfU>C?X zaUkoP0@=q@yiGb}pJ1%Cbqv{70@ixOsKL52RnHE2b?Xtcz6wt@p2cT>JYdFIB;#B0@p9pJ2)M#|6;7P zOAOb}0@ttT6}Z@}39g0l_dozw9SVVqZNRk;;M%(}7~U8RZ4CB|5L?7>FKUX#P$UuC z8&TN|+uuQ~3piW$YfN5y?;j&pQbEbE;RberY^Vd-o+*$mPR0ADL$(CQO8do-?JJP+ z&p!%eY}N!>cW3})O(+C1wgK6Zfb8(b;Lyh4;0Ui4!`j0X%b`f(b+`#tGVB-!ujRqn zare--gHzyIfqIWghigTQm5z?#I!fT`iC%$=&6?m^7a9Q9Dkual zwgJ~^fNNx95H;l=z4rC{$K-Qaz&rFAGBaD^Kh#@;&AmbnT70B4E39@aW0g&DR2#--m&R$ z4a8XK;ux-r1g=5o6}Z@}39jML0JsLD5V+U|T-O1vYZ`-bjloro!4(l=dl~M%O)&yR z60vI#mCdjl9mMtpXUh$Z$?rODj1eoTpk&xM1G_+Wl>^xoDUj_?#W$uyb^yjoH^h)# zFOVIGUV)6wnjqt!d0Pp#f;|Zzc;`Yy+*wkzkKC29GobrN-dF#$aNE*+oX+VpEJok;LpVCZ zm|X(SmdTCDFA1l_n3Ysea_kW&$4X9)J?PXYrsUhDG%_U}!OJjKnj9lINf5joy@DW{ zH6eI2GyuVICX4Ls&Oz)Mr~Xt5dbiWYtLf<7fw9snF?ufxdUv8%&||YE^d>_ z1a51)D4(Q)_tQan3S*`BVo=@{P@YDwfWl@?pu7eR2=)aO0t(vzPP_c7Ue%n2V^?NN}tAnd?J9nja~tS&6)uD z6dC}?2Pgy(wgJdD0Oae&U{-|5XNK={Q+$CUiOJVamVEDEG83FF-!+J)0ib+`LO@{~p!@<*evT0N#W4NX z6u+WKBJ#77CBHd{{07dJUp+*AixF|NM0F&x87gJUs8w6m)M2x-|t$N6w#)(d4}Jh@CHWcjl#AJO%N*EFE{I%nSJv?<1`sF^+~! ziIL5kV!R9*5Zd_?8Y*lf##IsH%1uG9rl4mO;N=)X@XqY490%ymPA?M*ldse>uIucq zCZ1mbW#T!THF5i~`<&j~vSU;HoyI%h zY#G#)++KEc&{07-RrWV9NCs~c*Q1N8cd2a0CM13NS3mDztTd=8`W|DTVDvtE1tT_V z!e}Nm0Gf|b$XSAIV6+D?+N~)V90ByD;hSZOuTUfb+D)gJf0SUT1JKvtY#HJKG&Bat zUE!)j@EM$f&%dc_XgWUMV5~GG#%E8#=Uem&K5W*6&mYhLe11Y9_^=Ip4g@~?HwF7P z1tTJe{xqz!O_9T2W&eNdT?d>LMf%-9PGSZXcV`v{M`=V%%i<`Yf(W>xfH`MHQITB? zzzTwhIeX@u!B>C*@NE5|yK5=J0;uL2#-sk?mZ_7&^$;#Xi7KdoffY#-{2TRpOj|xUbP+ z)TjecY9!fM8m#~e(5O2O)JXEss1X`X?`KW(1X|IQTge<&#vv@wbmI@7_Kpn*v&$-E>7HK0P0jGb|U{pCa7*%Hm zQY&e_-bl3h#5b_YtyBpXYzLtp`t?Slg)lRPB51Crg|&$_jrb+f0}p{D2* zb2to#uwJ(tml$Dp2lP4|B{O$5)9Y?uuV92ZHW*>I2IRU~k!z~hy<3;-2%NL;^5wdd zavceja!IyWxwexHqEE!u0yxO#I+RQDkgKk0lvP`0ZCqt-SY-{Va-Sw;1Dee0RVGY^ z%Rp3HWYKd{jcGBpb^q*+K?}7Sb0a zBoC)X!l~g^)@D`Krk+RV;1s+y9&ITe4fj0?Hsof;A@R!I)HoE_Hem}gKNrTxT(Ys4 zUkM8!>}_2mc`zRj=3}d@F;&*+Dr+l`ylh#M$po8YtWVw^1D5VH%4ox$&9RkXzhLeO z5&Ly-OQ&SF8#*P~SWY<`$J|I?;GN{*)Fe2yLzOk5%BuG~x>GzFA8d{te2;?7F~K;* z=BPIg1)5_rncw9ymuxKNkHZ28+a!#HX4Vfj#~wa; zdpEFjn`0Nlp3Sk7VISQbd(){WQ3;zvvay`{3oO8wr|An4l7~|V!KnkPto^F2eLRm| z#3^_i=p6_69tE3YKjRRaV;|#Cpg9gE^S{CvnM*bn^VeYkg#SsxNJt*cj|B6nRn}ou z)}bErH*hN4uc!LV?ZZG3Z6SZ`Lw)Kke{9@xgXp8^%bPGyUnCpLmrq~;F1$+@kdQol zX@oD+tE_3BBcB2fJ2KsOB-jMgit}Rz{g8jDlzvDymLEUD0_cB5`bbC~el)?4Syk5Y zRo1bdEC0o*aOa-oyJ8<7Xp>`$^W_Bk@)OL{7seMf?AGN(8{PNE;(V4Z$QHkKcKU;%#gCVeC%4?oU;AE#AWr&L)dd#=c) zHsKzAn(vBzN}x?nF3y)T>C0*`PhTV(%a^ra0WPdb7m$!Vd^r!koKt0;73=hKe?uueZD8_SOkU;*^kC4D3$4?ix0AD2{F7gbpodai6}if&{Mvc*k! zUV4dX6@CVIWtG2ZwFydQuBZx+7FYTz*v^F<_Ac^eurEZq`9?3bV(iK)DA#h)YADXx zS5$e6R+m$wI-t}@vavMU3Kk%Z?AgQqCwXXeBQ(0c%DUDQXp|{8+8nmVAuQ1K#B{MfS6X+ISpkSCdHh4$7R?%l0v2}~C&sdzZZ}#=MiTaEKN_`|7OP@Vp z0s2hFf%-@u`aA@E9;mYJud?p-B$7RHP&BY5PFSJ`;F9|+_((t^*)=Ega8-D8d&HN> zb}nQL-EVZJM)xWjabulFbd6-A9Q$Ekqeawcf1uPzvavLBHp4j-hNzLV8O~GC=nqxa z6P`fRPyhnu-3jLp#y7^$vjKq`a9!q^W&%Cy3lxkY#|HIzLeYmC;XJGB!;NsB@%4F{ z`gj}RNH&%}&IUK$MmUm34E+Q8{H@A*vC4YElPItW4wRA|Zo)D2H@M`+&`SY{P7#Uz zRTUnMU-BigoeLR5FB+Yx(F=-3vf)kUC0!%g_Qw8~uhBoL(dj@LLz0c9(eGdZ9-oZ^ zV@UGQ=uK$!dX@F6Cy=vgPGC=*ut2XH-xx#h1O$?8b24u?6X+dZpkNF+HmJ|5iawW# zt#@>NWLq5jZC{_asE=%jLwzJ0OP`xz0s35n1ND(S^!XI}d|YLH=;;%+`_0Gj#|@w_ z0{U?Go6nn#(_i@d*v^Fvpbw46BG8iO@9wuQ-2UbZT`_Kd^SQ6sXH@J?S24-PQtTn4 z*uAb|l80j7Lb0zsxtu+69yVoV3!HE`eH{p=9|Cg8E;*U+o5}TqFIO;}92|v7d0x?&B-ADi!-5P%0+bSc-MR58t6!8Gm+S7LEaR|%R zFA!hpfLz^BGLvd1SK5~=7+;Q!!qw_7#?!i5J#fxW`D#^Dt)4)smSkh8wKgn3q$(U3 zUy_Gfbx^Ce+S<6<+OXOh;>ni9+06RY!9{i7cY9+e#<-~N2*^csq}@gJC4QMTj7|+i zC3H%%v7D-f1vusHB_(+{H4;t@ueLU;wl?)V8Y&*uIUbosb>E|4Yi?#7lGe00H4X)q z4YwfkI+wX*V=*6Xm~TeHa6$55J|4`+R$F7Lto>V}0`W7_gKsFU>L9 zus4h9hCNqtTQ*0FPhqyDYhzIr8%46QT-yZ};F0VZ#YmGpT$=>fcBr-{R9p3)U%TQI zd=9MT?%?|sY?KMcEjCKMaVyX$lgWHH7$bAZ#$qnpPJ#J8B#eaQ!F&%e->ur(rP|ub zV=g;Mg~Mq#pSisYD56C;mhR+JZ#frixk2=v^koXn(-+Cc@}&_L;KC7f0SU>&m;K<& zKGoJbqhe9B7jRi}U4h`f?J?(-+Cc^5tAufG?-f1tcU7U#7vABde{co+IZ0 z4?A+C??|vsrWWVN(e&edSf?M7jpfHRumJj(kUkQUhabnok7KK?8P!&U=gPIF=ym3B zJr3df@3E#;xNbN*aR0plB{Q?C!;v}LSHX5JWEY#^%V0Mk-F)5fMlm*9zu(GcTlOsf zemj#I-3*i(Nj8>7_re0C@wVWSJTy898qKS==6V9%XUg4g4zd+jSfF{vH%@>T1_YAL zwKDk4b?BD1&=)8eCXNk`o^us_9u!*(b$uSfIs0T^p9R!s5m4$Q*;x8K0}IgSF&x;h zB@cbhgFfd}TW3{UXLu4lYl=Q+4u8TSEYUe|$({0E7?9|Bl+0XE9qvgN`V!gBg^Z!I zjLy{P3`HZ^zbkX0uF(rPXJ6oJbUrou3s7n#*;pFA1`E*WpEyt>$wQ+npwVU3)+L@m zvLzSFyhms8>Lb}$`g{co@cUyNsE_2K&n?jBrfTa3PoMvoa$lQ+Y}ggn=O*~$2GH#R zeZED>%x%s3*zLYPwsRo^=msOQ2(;w;yu0S}omjtJSL}P7vv2biyOoOl0F;VJHkM)) z9jVy=V2FxI9*W%q#qRRtsx*ZVk9jeZE@vQmw8)sg`78skIU;AijFyK(!k8?9xYXx9Ip^aZn>3mIRFijA+nV*N>7vDI+Se!^GmaVoYtP%0+bSc(mR z1t^xnfr?2UiaiU(p7!Kg+Z4*0!#X&G<$5|0U(W~RS{EfVe`+Sz^S)fc_;PF%9$&J_ zTjqIPE!pDD{*$lPb5zUQpG~r{)S3#rP-}l2sFviR)(WXnR_~P6D`oXaS=~}rmz29& zCRb@Sqi0EtN5KZh=jU1why|U3mL~(xKvnCyx2g7tkvauYw3>M(Xc{tD! z$-|Mg;YcQB^-o#plvV9Hayias)@jzZnHIkADZhW9Y14kwR!25%^F8>kMy2*TEt=LK ze$!^D$TcWTMI;+bkvm}lipYjjR7CPnWJ4%2BxMawS%Xs6Ku?joa5mhuLwq^x!En}n z#vWw!khV3yM`OzlG;#!5b|d<6H|)|6$;R^IF<5{fW}_)2Bo9Aw@MBoY8k({;@tk-Z zr@~GQ^PLFB=TOy$OC4N4Y%D!ig$3x*3kT{UdFXLC^q7*e4oO)DrK|%yF=Q(zXccJKDZUcHhCRdx!G=93 z(69#>B?1jQm5%g99*7TG$EoB|)xx>ww zW~Va$bvo^~a)&(5_sBj5bltXXG%m4ir~7R?%}*X_oGYlA2Z5eFyG1h_#Bb(VRA)UD zraF?1rOsxs08uuiC`d>i>MVph3sTnnlyzdtnv=4cJZZQI(@dwOCx|W!d|iSqJ>ST} zmOe4i(sKgoCL>Is)lZ>cvYQkAl58x$WCtR+BbzZXe9ewTnG4|8c`56hlyz3hIwNJB z=J~ZNN+Kvs1kmtviqj4&8RkNwlWxiAPC1B|W@kPcf31WGyC<|>)oOjOKd}1^MRoYjz2wsEu z!FwgeI0l8;$dZjE#)+_iMxKcS#gIJ2xB+5Zm$I($l$Zw`5}CH0C^37TFGDb9ukqW~ znbqD%s`FuhR3#gWsq!4W)Q#K?xYwOqAsX)*25|5A&>LjD3E!& zS+9H2r)@tTXuU`M*0UcrNACK>CbPB5;HF zD;;?ThUti8V>u$*3c-;-lRpxYha)e;k(W}|KU3DU zxxSY2KTdiDB{Q$4@StV{*ilBF*L(qN=R&#K{%1gezX!Z_*F9eoW3QzkTFY;dUdK86 z)s*)w(ks;H4WQIWvavLhoq!gGTS9thYRYWN#pp`^+3Z$001xJH|Jz zq<VpZ|!h4|RRM#yR@~U!V7>&o@A+k7Q%%)3r1G zF2jNPNFMquhCV;1te;ZWk16YWPo-|Aba!*;fkRlOpW&4oMips4jC!JEraT>fZmLL2 zAaFg(b}nQX{bZ!3Og{!X()WsFy~J=uS`De?aLz7Idm&YpmKN>}l#)p{mSk1107I+d zK*=Nz$$F$mS>4iBm$cO>?JnC@o1!UmNaGOJt6N&UG#|Mw7tpH)B{RL6>9w4%S1_s^ z8b6JP<7jlqGENgk4AA=!YmwN~1y z@$}l>6y3obCgKp*Yk+Z;~(#))}dTG0i|4$jV0FsumHJs$ANN59&!zZT$`k=jndWzX={B?G1(Rjr4KTPgK-Ee zwh6p)BW%-vVuzw+W>`ABq_?TBnC)E12;0cWPRTY1NVdKr*O#?z&0!%9VZF9At}?>L1oS!u zB{N&6vFdH64!g+IVN5_T=R#^UGN93LMWa*2*ce@-({Rq-+Sh0_H98$AHIi&BjV^`- zIDQTe)JXEsXa{ICA#K&Ct?`~lmzbiLn!{x{gf*HF&}ec%qsvh;GbxQ%9083c2Q+dn zq(=1tjm9e)T_MIM>l$5&bM_=(qlwh$DxlOzvavL>VF4Qb9tUb9d1!P5G&($OO-Wma zq^*NInI15uWm7O*^bihVnGT0nZr7U@kZBQ0W{ygSr{U8AGC3Er>rF9QQ?f$>k{zT- z_OKY9rc3q+&e=!#k{wCO9tBFtBpXYz=V1Zfn+?&BkUS)t3CWI2TgRlWMo+Ilo1!n6 z!(VU+>vf!Qm0hnXpx28inVH>8uO?rw;Nb4qpj^iUiO9 zva7Fm0Xh$@ilv{a0o}Oo*e&Vs+TN|cZnkqF!|pmGz6j^-YsAgQZq-HM zW@ESbqTEbTyv@cW8%vZLZ1sbX>W2eEO7aM)yCBLPo+ABCp|#8*gF`ry?g&KEy#YlA zpk(HrW{TYFD-w(($3{qywdMMIbwOlTH2WT3kh>{}?1siDk!&nMHi88RBHN=;5XnQ3 zMF`S8LeiSfa=#W$;q=PNOK2hbT`&ls|fkj5dX2doq+AgF{%6KL(=Y zxqu?upk(IRG*(>A)MN^+9D5R4%)keO}+Ace2|Uy_0M#?`FUPyptWl=$+)@-DmLbleG0w+WNqA?HHVb z+s3th#kEg-*Mgn;BjW^b4fJ3QsHGVM&^=@ z#rz&vfT3GS7zxRPc{eccQe$_uIz9)HTv@$eWvBp~76XLID`cnX#8Oe ztsfBRYn03kuECIFMwSC)++RN+kaHmeXB|b9Z^gj+x+ve_oIThVWj%`WJy41w*;t}< z?MhL~aG)rXhbTFSGOWfLT4QZeV{PO~)6JCbZVo+g2um{zUb(R|JRnUkl+0{i6TYhq z4@l!)D0h{ij=u71+f8b?%Flh>eOS4#nAfZrcgCWLSCHz4>q4%GbN1%GkegA+m4H%6 z$;J}08WvD>9~>y8sy9adK3?(zWHPdl-Uq{=$P@-|N zub4g27jkaFjg(4v*X7&-=j`2lId`R;TLPt=l8q(jcCY|Bx5j~TN*;0^ z2s!t!vG%R8_V%=#V2W;U4m;ow)^dNxUx~>>0$NT&$;`pcv^>PuG8mJt4T;HpeJS@Y zR?3~F&O>x5cfmRPU|-6EDCMp|DWznKmGZ2b`f{tje1J%3LB0Cy%=V3k$Xekm2NC)W%XCCkjS$VY;%Kd~~)(;L9r$2Inw5MZvn3!mGgta`Q8 z7%}$8;=|CdYNWx=ty#2S?l(Qkn&#n_GEU5`!a|vY`Yf8$xw5S3B*Dk>gjdhR4q041 zv9i8=L;GFSaI#ZF)zGhN@Tf(y4(D|3e`?CIfa}XQ62=>|?QbnBD;qAPB!>+-M;z^3 zC1b5%_+d9N!ya?Zxjn{V@T~>k&uT(7dOm$dpT7A8K6T9E>WLld%ZH+xFKWVW)VSJx z!Fs;UQ%^ddc4=R`j#*qS^=ujzwZ1%u#)De*<(pBYTUv*wisDfHbM&39VyY(bUiGQvt(m&{@QT< z!sRS^aJ~ebFY0ey=yCoAc;*5y#6N&p)^rvqk~(Oep0Y3MFB`&>qJ1IKS4sM-9^*!^ zbls)o`YkMwt7MDidPWVrorV_2VJZ&PSMuOGH8aXOEMpy-arHeKxP55G`;6Do_mGUy z_gvBUu#Bs(DG0*&QKql&5gDm!IxLa1WQ*l|*r59IJ?hJM7p{AN=lns~cXyCAXOP2l zPkYWF8QyCb4nm2&q}bjLG;qP(Z+n#4Ck~oFa{3Vbj~l=~nK^^}vsfb7V8ID1_O2Kr z7I1oB3@Nm;pHm3hdl zE^}%?l%V=zIn&5|RhQv%&C8mtoU|rqJ(j zu+KDVUm$fiUF2SNF%p?G2RUaUyen;`D{a#yQsmq~5wy)7TrM^$2bg)q-4cO@j&vH{;G3>M2@KihI(F>Jtl@ftoT->to;@d8tES(h za9OY2R;ZlZqinhQih-D7t+j&)^Yipk)=$%&*vr^IO_z29-|B7y!5p_I{HgoD=@4fC zE0bhI!)TSQ!^$ceMp?BpIWc!K|h$s_EQdb#!Z5-|j3m znZFWqi^ap?cE<*ISJ|z56$dTzSCZun$vGhAK{%5E!lb(!B5UO5(@XelPCk;1!DmbISsr|rbNOs#FGqd&SM({bFi3ZH(5fZySwZ-W zA|FY{;Dfmk!f<8qS<&S)F4MDNk;vcFX?b*s6-6w{RB6&ZCIJ{Xf(^8a5ExGal8iwB z^Aiy03j(XU1h&sC?-1xJ1XdMws7s|uXRws zbh}3Edd}3BH&8wJ6-T|}soo%{H_%mYW+v6J2vw9db(csQDAn~c;VWp}dctZJE0tu7 zCTltoBReY|f{F*b6*tWTj60g#VMJQaKQkLOV8AzgdJ3Px64?x9N6DsZP~P5%YHwoH zZjy;QGk;dEF~-lq)xG$W%BQ_GgL*QYTz~&&3^9Vc+7+yasJVvsgmD@SSR)sn8PO?^~ftU?)O4y;p+GS;f zuN!$|$^`px()*K3PqK07{ne$n73gi@(fgb5+B_KeTaa8J@JErr-(3QdjYHsNm%tbh z80`^w9WeCyP0+g`rHTt(FDp+Dm)Q^YUWp<4y7Uk?8#q6?@ zjpKGDAOCRw*$Hk>_T26aII~NGJz3N?f2H#BZW0`H+i@LP+%cNEIOTVd@+>1x%75K$ zgW+npFIO8JXWVC<$Np; z*)t_d-2r@5`1GSa2G8GW_z3)8R@X$9qfvk?B^!t3co-ndlfZJG$8uZ1U^&4Yw#OlJ zs;A{+J?wc6kZK72m$7z-@ae0e<(wMR;tR-fA_|bDWaF^h1qR6S46r=SW4S9})W3&0 z?1@9>Tu;kKd)TKnK&m15Us&!HKK(7UbRQkgB+I=~fGi~&hvoh-K$gD)%L^K;^E{%5 z;*5PB`_TpRw};$D%0o!6ita|Ti%4dQOGdJB$QeX-CmchJ5_ zi9km+KULAqJtb?hp{qK0r({_+bgGMYO4eCJr+Ry*8k(P~_D(h8ltWKMsxYctMpb6u z9Ggh8aa5TL18kzJp~{sF*5#fsCrY)Kvx%;hzr53zSK7>UG=~m`%QfUO&*dW7I9wLG zTy6xH>l>_VJuauU@YZ$nl|Y!=3o|pG0fK8MiS?^BqSS$#04&iyFlWO2J3c@$A!YsJNZsA!^E;Q1WaIF;)aCO4_}t%M-RtqWO!(X@Eh1fMxP8CF zhmUOmq}vEV>K-JY%UwQ_jl<_g7(jo$fwYj2JSNPKfZZaG+D)d=%{XKp$DlZ;rh14x zKT1!(MZhN-?8h4fac?%a0ks!3fVMbOmacuunH}7Y6NJnZ@=<#6dw_U5fif_72Qpyr zm~Rr_7S;U`6M-l3KaM!X!KODX*Z#q=duO=9s@kU;%Ia`3izAHQh0|cU0h+jcWBd{3 zcMG=2*jfd)1iJ?q)`g@dT+HQ!`^54S(ilO?_e(*Uc!&o@3cs#=)KFiZk+m3n+>rSf z#QujX_S*J8Alp9%cyU-(mHBtWz&Y~PA@j16Fx>?2qsr=D692NKBFPw32G*CaD^v!8 z%4?wVic7_^Ujdbu43%MTHb|jC*|*RFFE`-jk<|XW)V^N!ZD8+&u)*1PfxQ>P*3Z5V z?1KN$-k3!f6*^hyJ62dmbWbh5C%*wpkuqj##G#CXr)GdjM94eGVWe&ASqC*a* zCDAbld*kpqMwS*fqFBN_hFG=r<(r5O^0me15bIM{tfBU&0kOWKSasR2g~7<_O^flL z37;>-iDB7q47G{?xM}uV13GV7STdLW&Vc2ClAC3}H=r}sXUWZ>(3fI-Xyz*_#JcfV zn{(^RIrb}aj?E4^*nu#cXL;dp3M0m12!r0UjR=D^{7iWxzWsKE8D}qsFfTh%)S*!d zjn8&$3`9{yBd~3=oq%<2bRvsbeYOj*t|4r@Y&T%tL)e6D4`4k**!Iw)QVfsFbZC@_ zL6s5>)@m-7>Go=k z-hgATA&i7drK?1h)NYpLB^jgkW9rLiNbSd<_B3j*cB?+tuJ)>P7FlYfw&UolBxBSz ztG;}u)HVyXWl&pxx3<}Kf48>I-7(U?Gyr{G{?-kUN}HP8l`qN0sMuZcH}3;rP~HH5 z#JV7nbxAbM2WV$qB2BW~*4>2MK(aW=Wg*!(EKY?1RDKE$B14np!D2nIusjy00kkcb zMHj9jR&+2t29w9>D8XisY#biv!2qg1m(?R7dGOc(Jl6Mk$Y%mL#}5J4H*_#?mto*` zUd7f9HKT+xJa5=omIZ=K`1XIJ#_%dPO>k| zX3UBZWMe5Lm)pJ}-bsRl>R7$JrZGL17dbuF2q+{?DfvXe*b+0Fcds4RXc~ntW;W5- zv%W_~fRG`~*pz;sWWgTF-|1bVx{eZe zp#)cj5yDp zv0#i56a!cs$KNh85<7;#{V5osxUd^bTzTmPJI~=jaU~CNM?u^zJ#qgGFtcT2$osHd zTe?z=6V}c2;7PBiy#Ql2A@K)a;cQKv{sNeQ`I2BXbTTLS`f6!aF0Z(Pl^Y8DD}Mst znt%Xw`3K5VU&+Q9_~exs?ED)C>T6z+WyV6^F`mA!;Or8_9n(@=xl@?<;7RAEF^-&H z#W`}8Y#h#S!2meFi32%H9x+i5&f`7K?*PnFWOTzaW zUQf@A11O7f@#9 z?BQRaIra=R2h(12ERXAKLQ&1J54~9d<>`%N<9H)){ouqZIIuY+4{!E|H~V_t$U8uL zUm+b1D?(J*nX4Z_Qr=5I$;KfiZ_7YxEtiz!LF!(?m@|AEHl@+M8t>XU_cqG=XqRp#Evr55Oi|v8We#h!r`72g?ckSVp*icyUYWq+rR8>2bY~@9mgVQN?#d5j0Lh6@9m#)U5GY1fV%(b=t zwX|t0n@f6B)gHkLdybfK}KTi33AT z@@Um*Xw@UVR+X1%ndyz;*StrHLX0z4zO7Kqp6-g@r>3@n9OdO&fcVjn#+(==;WcbkW*+D4k)ruo%UM;}u^Up$-QWGJU*clWt<;a3)&-5HxuGDgR> z;0kf%-5vWg%Eb~{-pj#`yuYK!l84C0LgX2q$dgQ=9dXFaY(&2@KiGX$o_J;iv^I;e zJE5386DtB-L|$B7JBy<1?7^mA9S6_Mncc+h@r`KNCEDFx3>+V@JDYap)t`ZVyXK6% z?hCXoDuk!rD?Z7_3CsOp6?XQ;fr?2Uip_yyO`c-=n?eWTU^khtYxZO@k8BP?0iozT zoX&+N=7hX1%$(Tl@s5^4aXrPkzS=%fY6(4j!5DZRh7ybr$;R$7=QeJBPpVh)^Ah>h^E~T`d8~{%S$oPXgvEuJk7=RslAfNfQMe4-)+>W*FUEPQ3?{Kume-iDW8QNjA$h2L2~@tw zQ~3&jnTr~seV_+k%RH_R<80=JM*A|{FhZ~87@^IcScYKS5$2EJBKrz)$iATwnD;iXN7o+q zRsJHk*ysu98YwCn%+!pp*VETWVTZm-Hjb}PzySC>jsty_Jbb+czTV`y_#{C4CYM6f z;^n-B;9JS!4>(U2l8wXSX&3;Dr&u`>k_U_5gT-wgi)R4Zx4A5OaKWkEJbj5WW_3i` zpsel=(s~vbkd|cQ(0U#Qz~)b6gM{Qk>u%7x)1&ogfcBj(t)8USY|;K6(s=;|Nk_7A z==>E1z~V)+Ktl4MV}s6p9-Y4dwC{82^md+q9w39i;~W`CHV%UiU;q`r$BL1VJQzF% z29GpaiyEy5Jsuz8ROX3B`@v$m#Yecvej?N%@KCV`Ks9?v5Bm|X7XN_(u=t9V zBO!UPcn&O{@mPEf(0;~cVcv-3=?H%!t#5DvX-PH?t?yv~Y`!BKBqR@7FM!tb9<3h$ z+RwYRx;l~f7c%$}=g2^^aTs*3AcJl=uz4g827d#C7d-|&0NO9Q4A==@=9@G8t@}HP z^h6O7k!&0yyp0Z@HM{&8du(=EB#TJu1GeHD;XGo z2W#QLR+T(lc@M6<X{Gxa{BFQNU=JMZ#jeM_ zs%pE=03n>%%UolZ%|NB@MSDx>pBiO{05R6ZeT?1*I6jK$Hlr+y>wSAYILYc#RomUM zx}R9BnBkY`#1iH1Z!nwo4^}%6-vjb-t&3eDG&*#3i5w6nVt)S#)(09QJwOCi`qgxC z*V=nJL=KK3a!6rB4h<8jb`_aoi1Y#xROu7xMIuxL-4z+10g5a!h0!R4N zbw>G)GYp6?9+wj^3(!W!(xW>Uwf4p{zjSu(XPV2;voXjuSiO zGeE<9r2K#E>c`6^@)@RN<8<{CVF1?W;=m3id8pZU27UrQ!}(mRX}&3RvN@cBL#Aqm zy{ZJeXxZ6O3=eq~iTsE|D)3hS z&uf0xu9|@hxo?6Ltm^9g%DL(M7A31qNm!GT9ZXlNrg{0p$16#!>DjoT2pi@(*nLyb z*Rye9gpEq_Sk){4yB6hBA>J!`B`*q>4E~;FHAc+ED8Sf|Y>}~1GXpzv;fqm;3GB?3 z*=Xh{YlE3iJZx-lFmwKhH=HjTYx#-SCfT7gDJ;Iz#Hq5njc4N0+H9Rc*vRfDw_jtD`s zsYlNBA_wC5B6L)iltwe2q-kTs(>B~2jGxJ7wn02??Z(qsd+R_vjb}WK%WgXpA3e-; zzJ?tuf{f2@2W&zJ+cvvBupL5JeRd+SNg-^z>||g&hOi0Qoq+8e!nV)u0&Le1wnKI| zV7rH~iP=4X?HR%*W%mNMcLu!BR`F4;qX z9U8)R%}xR4eUnbDc0&}66Vb+I#xsgggkxO}x^leBK}<2TN)jD& z5J(c8a!^GQopX>v5?yleUlLt&a9R@Ga`03V-E(kH5pFX=eJq`wO=qWMn?U#k*NK_J^RVn3U~@y*;n@>|j9nS&wtGd0U%N6;U+G=@LZun~#)gHNF|C&QnUW?J)HmyWjQ(WO)A z()8?UpnAGXf1xmJ$esc0%n;U?Jqy^`A#6tWoS9|zNi*FA=*+n@ogb2%=OpBY?F=!r zd`$LySh*l%<=E_nz}#I?BWo1eD;!XZI`;WU6!Y|nc2%><%*D%S=lRrT@}J+ zXRii!O$g&R(%EanHD2e|czvE4n@+&=HG2cB-59nuNAR0~-yFv03VsXlTf?|~S)IKt zT>I^A?Z3}gyL^V7y#ve z=$L~?lIWC!Ad={ugJP2Cl7pO*=$eDplIWI0GfAR*4s9rj9yv6yBzor1`jY6CL*Pha zxg4TO61{T>IRrmH8qbnwllOhNgief3z-`fBQof(&rUjY7>FfQL#XI}*F zg^RIst>AwJeto#S?2nWE8}Pq}@#_Wu2k?J}arr7c`!C>LCouNqqwMTUz%L7zmv67L z{|5eY7?%&Pv#$VuHH^zQ)!Em8dtKVtm#?U^uLD0XT>dt}-vIt*7?(YDvTp(R1|4JP z_rMXjPg8VhsmwDBUbK!xO<4|YBZ=}H8bcBlIjAp*${ggDM28&ol|;uJ1eHXm92As9 z=Nu%HM3)>il0?@WM3F?d98{1*_Z-}oM2{T<j-Q9Fs(^96XW4ayd|!;1#-AL-r0~ zE>Di)NSxr6{eWQd9vm3FW`Cf}y9nO5z2KG4#_hKmydRk0mG8&1AI>bxeuV!&#{ZvC zJNbe<`zf-Y;s4L^{}+TG1S}pn9|pWf@F6MtC6n^SxtuREZ_3Si*(eB&@;*xlgUknP z6kH-@N9ItyB(}(bgCw@hfruow%7Kj}M&-ao5~Fhca%>rL1jLUXI*>!;r4CC_Qan=GpD2&U8#@Y3N4-Vts0!JM7WMfFBjFP^$GKO{P}ZFtFU9N2Q?~deYtFS343hQ`kCiQ+ioHrMS#d2e z>lClC#b0lIZ);rf>mL$k6O#lY_>3* zv-}Z5=5sZ1L**j*2&jA`Q{~1|zjJ$7Bs}p0Wol+JF*F-iUtT8>I}DmV28($2kH3yw zIa@L<<)RAx`M238G3L(nxS_TgshLa+Y9s5*M+mi%p!Nq+d%~x-g)JGKTDc*mQv0K! zwk4^VOblwl)tzTZ?J1wy*vxath&sKT_3v?%*6eKhzI^^FrG-1T`+a-BxY|D<3rDx* zh2BYbSs0<@mJdfQgQ3#f>aUzz{UMM{Pjigc+rkFnW8U>XYpU9g{+mn;|0iPSQ)!xs zXqp#b5nm4AuM;(sZOMe2hC%G?#jqpm{tJo3sC##;s7T$rqwasP?tkE~^*8zRBK|lm z_RRbn8CziVFK=)xcfZ%$EAui=g@0NjhEO>8K5y^LD?u}J@Og-5%Uj6b2YYIR&1+Ip ztU_(Jjd@{I_a-1rz~wK?Pz>{$hNo<~(7C2ERr`h%6b}!`yoIFguwu1tQRgLuEk5E( zo>QaV`9|$PTTEeTp!OZHj;&oeLYk2LNJ3KFgm;tRzb!KQ;W@VMUAZRfTzN>ID?M4t zdum3qG$Px4cc`NjS^6ovZcNEzQ8R-j9){0LbR$Oi993U_q=<_ZnaoEpg3ki**Ln|s zoXDAG3o?JiwdR&O>{I0AileiiA%%q5MZ^qs9~-DK`?*QXu*K4Xx!0vVEBJ>nu9bWI zF^q}OWyfZ}Fqa*d|FYxdGH1%~)HXBwrMYZY%X70a3H!vHot6>mG6`dGmd&w3GRcv$ zBr9|D4AY_6S?5~b^{KR}GltSlM^i2C(=Yll57l?MQB+?QUt~Ihb6@?;Y5?TL<6`$U zseF0up?Imf_!0cScvUl-X_|?%wit0b&T#j2@*47~Cu*D3{PM+%e|9d7bEn z*GNCd2tSo}nKc;(t`WD)yk?msx{<@8r z!UOpK>-4H+6B9>cX@1h)E<7!r~P!;Q&sL;SUd;Ezi)gR`~( zh?`+UaimuRfM)BE6H9ALW|))7B13P@Sjm0C#i-+D6P_8$$~xd1+SSY^z!+o8>NasM zUPml#>SWd}*pl76g5jv6`x;6G1EqqTQ-Kw~g0c#!AXsk~wZ1`8-)2sI>&36HOFoAN zO9h)d6|7%K1;Sj@eu!8a?pWHO5KC;upaxA~S!SeBwBJxF7~xc~QTz%Jbb8}%EESA& zD%d1`1@KF+pjIl_!l__r{0e&KtDsIQ*wU$BSnLYK0o{X5rGl-T3UaY4C~L}B!Ddpy zD5rwW<5y6IR#tn|aH(LlQ^AN|T0uB^#Vh=$);m(_-P);li&*szR}F6|hQ~ODw~A%B zsZ7R)e9T8l1=~0kjE-4>4B7cA*jg$W>r^l%vI6P95Lp=^wh=?)97AIx4Z(^GX2CY> ztx7yj?2dQrj*qnK5DeOFl6aK=RQubC{cRol_3`YNl~w1pzn$2xckEAyv~Qw86L@O(+G0D2{T&?pJIA$; z=*we&7qLIlvA=7SeW8i})Z6lIVri0NY4<2gVg@}m)F+w*%zIbfL+np>?C%-del@C4 zmEKG2@95ayJGOljDd7Mbjymxl{;3xwLidq+cXI08H*UR73l~xEep2twPQCj_*UNE5 zX)kHT&;+vyuI3N81EktroN5n@u2v5d)m_mTCv=$)l6rS_>OFXA)+_$Xe`-`6BGvBZ zRD0;std@16QPgUuNVU5=)gBh7+Tp6*!^Q3%j@_wo>^6b-5?fE}BS%QJdpgw~xm2qi zP8}s^!hJ{Jyuoyo@Y&1ZGi|BzLABD;RP~RRYWH@koxYT-<-AF)wn3`h$Emh4ZngQ{ znj!Z0b?hG#&;D>|hW}Ll$BO;^9Q((`v%iF(WgiR&PZP=LY>pQ;`#WrAE@d`mkk-1; zEUESYr`p*|xmwdzLOn=dW@r)?2RbZHh+<);^4cV!$eYd_srDeJ+PP8HO5?HXhZ|Mk zBI`X->OI)0cV2Y8d^&1zj~y;G>vy&JQo$ik1t&#UP)$?HEM$QgI@B?Aa-oKr3pAYO z)oIQ`sbGpz!70%d$UI7Y_BvGz9p)H1Ey@sYHM*hG#n9o7p);ZknP-5OvA6`6&y)(L zIu)E1Re{U22u;tH3XX6pI47zC5mdsuSp^(2^r7lpn8X@)ty6=nux4asRX!NznyPv8 zz!g>V=7CG1lB~#a@lukNIj$>8vO|t5fRgN(;}V`EJLS08Cdtk@E{jRBOO6XzlI)t} zQj;XR<+vy$$?iEW-$=4Yjtec4?3v@*ha`LDxLP5}<#JqCkYw*1R{$ire2&lXl3XFj z$8JfknBx<&Bv;DuVOEkW=lD1($yIWEpp@jQIX?SIvQLhWX_D-l;}ex6SIhB{NRq4P z`1B&lHFA8=kYv9c=l+shGso$;B&%|qB1^J5$62c+Q#sBgC7I4~b|=Z294BOw?4RQ# zNs?>jI6skOCdWC0BnRYpAD86XIo@(5na%O;D9LqlyfsO3-5hThk{p=hm@P>w$8l7W zgK`|&B)MLWgODT#=QxZ=a{U}Tyd;O@*kvWTL5`hHk{jmOJtVnNj)5#+?nu~W-Jm;9 zVo<)_F-!09-Xv_ak-Ry;yMsnVFaCuf{I#aZpCj>yFA!|O_uc+ovEu$~qZ;t&`->Joz(M{+u9xX5)`hL9+7xVHX#0f_dU!yR^8}CgZ zRDP!uC!CLXx$u=>U#T$SO-T^HNGDF%mcAg79}54A<%)bhwTgawiS85ONaCgJx0mX~ z36r=)OPLt}qXy2F-Prr$rmSmUjDTbFNzvJj%Z@GL(lgP~F(IGC1cu=klL*nvbX5rF z^TCV5QVt52>%33uy5t{My6EG|%SntY*XY6$j*N&>jw{#d#0lpk-YUkG>vZCT^>O8TxgwuW z#f~c#Nkq{Nx=(~7i5EDoBtrZ~oj73<|7~1>LNOj2Z_*LC;az#F$ym6(J-SalxC&H1$TTcGfRg*-T!oErRk#DA|7Cmcz< zl>PP&ojBoq#9Kwby;CPnSns!Y$rbs0^7?HlpEK^(eIgu5yubk`k=4$7bmD{~i5EEF zBtraNojBo0;sp*ki4ea}Cr&t$cqs>*`*q@k^?qy16_GxbvfnB_MwG5C)`88#-X7P>OQp`0Wlh87 zUA~x+H}=?qquCq#v3l*#EU9)cOiS6np4Am492usiyn{Ta6DO=U#-G?2&BF8yJAp8L zUgt(w=k{lf+y5nTlXyYrMp)GNJl zcW_=D{nD}HZ=P#Q`YNfwTU;Vfjepmhi*V%FQQ$2u5#s;Qi4%?_Udlo5pE_~EdI$Me ztB<0Wbe{;bF@BYv-P%4i`M0hL;Z_}@FYCk!>mmBe(hSi=ro^x6J`w))LbMHj`0$!8 zEa6ri<*)0+3F}e*MnO?t%141Wb)N`FHb#N-kVLxYTRL&Vk;Ds}ha^J$ZJjvbNa8K0 zpugS=%6D|)gd>TUasu_PPMombZ{L$EB7G`lzkOf#iEt$GQilHrI&s30#7jBge5eyA z97(*C;s23NoUk7LAIlYyJ{1^6i9F1GqWeTRl6Zkpv~IzRneGx{0n7ED>ck005-(*G zeWnv9tVhx31w~PTgJ>dA^o8yd;mF1)WfXm>6DJ%=yp&P&l}?BI@^;s3o{5$RKbgJ>epGe77)5hn5Ir9AJI zT+7Fs7Ax#>uPttE+%pmJ!!wV?DlJ|NdM5Jx@NDIRUyKwnRrpaCmT+W5lrqZys}m=z zNBK{3MS;QMy+Lg`0(s4}6k6JSqtoowVUHwQ`hU7$gdf60iI*}&|4%1Q zSP#*~MTDp~lKeKF&4z5wegvnp5ong;)ElKmoof&=)?)@;onoPi1ewz$GJqpznAV4 z;Yi}84FBbH;)ElKmokca>%Z6~d9tS<1e(nogW>KH{ySZ>_EqC#?6aHROtXJ}n_8 zf4ymLKiwz7x=(8sf60iI=iVr*z_k^(aag6h$pZYtu6d z|3yQqmaRsYjj%3T|AJ&Iu=6FdF1eQO6Ja*SuX3|)gI_3TbYTg%>L?$e6DORHc&oVI zudNd&tas0>T#?Tw?|xrk_e|v8xQ^}<;orLFFW4A+U0qnhkr7eKd-p({IN^N6TSfP@ zbmD~d?m0-V$mf&SJqujtPvq{op6(OjNaFcsOU=F(NQC%cojBo0;svhrCqjIEojBo0 z;suW6i4Y&66DJ%=yp#jZ20C%V`G~iQ0cS&f60iI;M~sndxQ*8A-+xgyf1QZ~k> zx=(~7i5ED-NhFGLI&s30#7jBgY^D<@97(*C1J33;al(f60iI+0QN9e=} zM-ngPNI6m`PB8Jw)rk`(@n2=l-y4Wl z&Hq!GJU^iLFo|E)j?+~k9NCB`ENS_J}(L|=5^}0`lBZ-%CP}oi< zPB@Zyfr=+GC`{0a6DILrWl-=2_Lehn@53K=P{?yrD`Z@8|Ba?L@?v^>z3m9=Bft)F zMf2%YPyEiNuz!KHi0RZsof~1D+az+!)4E=Ol(Lgg)_o$pv^ser!|IMYal%WBcp{_I zPC9YIzl~0L{~b)Px0G^zva{ZHg!K_%7r7!b9!og_?5g`jIFfjQxA{ayfZcTBg!2)n z(7gS(n5nm^@4I%_wIQ5O8*jEz${$hep%W*p_pm+XihMqKqedxv*j~C%gh@PlKDvas z^(K=Mzw-A!Ok2W!4n2zAw>eVyQV!R9>%tS(gJ~ZIQ?t(&zAgBdHAPG&_tm)(*17FR zZc&rTQjW;`>pl_A7br`J>^3zbAE0YPSa0tGm(<>TsB8x}vV(Nl2S%;r8AK57o6HtOwH+FPN6J$xQREgiaVcddnx^|in1K>~ zD_O!krqEkSA$Oym&I~<|nqKrS;Z2k~$!``ceUo?-b+j%l;e0*NlcAK44%2nwg!L$I z@S^;;V8QBpjDM=VQP-TXuK5gV-Yk$uCh@t#F*-NGI=5prZiAEHcAUS-y5jl}>%xCI85&msN{sq4lnxzX%xK)qHvvuNx^(b$WEA&$*$f-zo3;gKwze(IV z=jiSd)_t10G<~Wpc%YI|ME*g@0(N^pQTK_k?$f-2d@69DO5`oXeBCF)1rAi+fZH$j)EN+2;bCIAOh`oa}X!=-KCQ@m7{e zB;FS4%|=*nwo|-jTMFw-iA=;!)qNry*@s#VCF;kxi4Z?cCr&t$c*~La*CT$qPMmNg z@luXjXXwNU>*0T%<915-(-=pQ95eoR4@%nSIKQ zkMkhgeGQ9g>9{ua67gJJ8^U@IJ5R32C!04BC}p6Yulqzel6WZt^#YwZ;Yi{wKMMZ! zZZH?>#0f_dFXav9cRF#xdiY-?S48?$%J9Ef_la;M@luBWB|34!k;F?G{+H^+2}cqy za4wR_Qp06Bal(`|TBSMWj!qY>X>)p9n`1FL1y~B#N%mi4%?_Uf_U} z2=S|R;)ElKmoogX(TNk*!~a^jBGRV-o-u_B{JOItP>|3NxYOj>=vCk;e5o~OAotM*M_j( z!)}u+n*Y3UY{75m+@+8L-p<{wb0e&C`@P0(XcFA+(76%Tx!p-_QSZ7+c?-Qu_la=6 ze&Q{3<(ok+#h(F}atyg!*M=~)iGIuFeG1p9#ZB9LtLpyyrFp`{Q@iD|qG!VW)y+~A zzLay-dvxIm>mBXhR^QR?(|sbGucJjy0hVHWm$IYXuWLg%Qkzl+s;v_ztOx1?tv*m6 z)O{ix*%+maqK9)!T+}zV7ZdMkzbWV>)rddPjMDX?B!E z)(M`_eIgv$7zIB6Btra2ojBnFd$>2i7cfE3)5ARzE$9;Z{xj8J#%cNa8JTm+H3(i3|$Q>ck0? zc=T=G>(OmzPYnZmU2+|lTMtlJ}5jdS48^MaAq*M_j(iQkqhB4sOOCw@owiEt$Ge7oNieyfhGB3~z7idE$6ZcDL>O=TFJ%kBI#@BBlykIU?@1u8AUM4~~vbjrn`*>fEQ^I=R`=HhL zy$^Mt2cI`V|=1F zKH+?g-(EV#r@A(T^J(*2$CxMkrQu#ZslXd{DQ|V3=`BoH@6n$Z)T0X=&bt@9yi~+; z#}~R!gd?N2l#h5{>ck1>BmQd+MZewZmUOH8s?~Rl|LE~WIA45u!+9w?#@9M=!ug2* z)-eja4|ziU@`Z_fZQ%t`DQ|V(=s`qSztw%aq#nJ5w>xcWE%iHHHp04W-+Qt}za#S^ zqveF5#S5-HuUNcah7`YL|A-`}A3x}V5oQO8R>gB^3E#Z9{|Z4KRXkx^-n3f?+w2)T z5mkQFRUurUDxOO%SGZcZlt&d$*p_3RXTlZs*HGoZx+;YA&h^tW)46s_qI3OE7mRR$ zVdTX?Njg^|s{E|0LbyOxO53>-QRV-1RS4^yYjOMTTxAd8B`EJsBjh&%Wp$@wC8I1$ zxWF(fZRbkl&Q-3fLbyOxO53>-QKdpxg|ObaD&>k|1uMz4Fp<%ygDx210#zw(=SoDC zj=Cy@3sj{IcCJpkDungU)p?oeT#1ZEU39?+x8E@8s;fe{KvhaRt5>z%9n zGSj&d8KZmXf)Oq-j7mF3C!$JET@}Iws#4m{m53_6bX5rJool&ergJ4S8uiu%Biw$& zXn9=~!Ud|*28Wy#bX5rJoomHqrgJ4S8m*)YM!488YCBJ&E9M-y-nkMPh*!~7 zAzYv;r5$n-QDs$K6~g+E(?_l-Rt_tA-RcV7m&g!}HMX}O|U!AdgZBr?mX(FG&iepTtOt3tRyRZ2VLBoZrY>8cQ>D$2i=>3x&h z@>4H$pPFrw_|_<+6DM43bJC&EkAA)H&D{Mve!(Ye?k*yQ{~k{t)dq;i1-j;bNO}*%;LZipK@I)&@s4 zOK)((?N^mSx+;VVRHd||S|W3`^>kGTQkUr0*amMqKjhg&SA}q^ z?!UDgv$S;;V66~e8$|8A-iCtPfEE*t$fx6Jh4 zL?U%Fy}=0=*x+sOsbX_o6~YCo(gvR@hU=;j&Nr%g!BOBFoE?&QgEK-WPBcWI&s4Jh%SH5KOxvPq5iv9`|iJc>uo}~z({R_{dXT-6~YCo(gyqQ zzPc)e^YveT7$f^D=li!*e(CS`_FHE9ZzAg*`|E8&xWGs)ZU0R~l>>BD2p6bIY5Q*? zsvM}RLO5Ul^@5{&LigW;+IRmwSZ@=;1xBjZL?xL&ClaZL=&BGdP?a{=e-G7FA)K%O zdh_R`o`0vb@BVw3-X??#jMO&Re-GDHAzYv;ZLt4N)m0&!um5`U=cJy0k7(ch_ei}> z2p1TsZLt3yrK>`?Kvmjc|DC3*LO5Ul^<+ru`S<8$rvE1L{%E@1CWM!XNKHhQ23-}x z`fH5FWhRUgdEl6#3r2XE2%|()IYw87upUOoE;C`2NWVKy7mV;S5k`rqa=fkz;bK*3 zJD@z2s#A*>HMv*n6n1uIDyB{D`g>4Fh1R+W;3Q6j3GpsPZ- zSXJ6itjy6>AzZ8~Z6{Xd>Z%adhny4Tied#TNf;$^KcA-yMz~m2+D;hF*Hs~`htWw4 zqh|l+`knWcmo4HyMcg!a`LZ(mWc+)?3+66NO_D$MNs^mWGYS8DJL}FLIo+PeQn#j2 z>elqQNpgK=HZbI`OOG46K<7qS=XNr=$^N|j$C1s?!1HX^>#cFLoe*EB3r4uu5N|uG zoT95jxL8$6((w}+4o}rpA*^?<)0UaemB{4mbX_pQ#fDKyI#(j9oS~~ixL8$6(zy~* zUDaX5N^MbdcCd+;e3&r_}%}8WhPP+S;)Cj zZxh1pH&SoXRUsT1slD^eQ=6@QJy`JCmn=-3m`>4b#EZ$Bb>f8ewXa*+cl_U~3r4v8 z#{X@)DunaJzxUR+yeg`;Py6bioK08~-JFcb>?s@LpXN!o{jml6U8csB)jK3gLXCg7^GV z;HZ$utnhxFIAMKMu;q$kTe|JU{{y;Ugxjww59+EAE>@McGb%i!t3o*6sL(3r%8PX3 zg!NJ3VY#B%mTo(v!Xvt1gxjwwkLs!rE>@McGb%i$t3o*6sL(2&ARgC=6V^wCC*+D^ zTe|Ix3Qy{S5iVAhwiEw<&{ZLvFa9Iv%D;4P!#}p~NPS9g6T-ztYTN0*PwT1>E>@Mc z(|@1QRUurm{`+kE?!V9JZ9=&HM(Uq*RS4&c)X3+rUwWr`zI{jPpY=8&Tx_Jaojc77 zx+;W=Ri*9RY5t7C~9?K@Kcp|=U) zVk5Qf+-d%)t3tR~Roc#-=3lxhgiF?cUuxg|_uqP(5MCxCHId(BysWE2IA5ejuAcoG z-ygoB6DO>%9>3bY zk@KHl`lS6q`;OEP^)?~gek1iGT@}LlA~kZR@=GK28>Sv79W;2r;3;t!q+`@ku_qpyqVSQ%ug~si^`xDqs^h=!^VV&Do+!v= z3gKc^X*+K{e$Z7R+^R=~A9dn{^-z=xsu{SXD|AsfnmksjEUbU!+E^S~pu8N#yt89dzP^^_f=3_8tG7bioL> z-}vvWt3o(m{70^ZH;ey7-r9H3i4)f2zia!B|8BZqgxhcYch^-RoG<<(SJ<1ye+#>SeaC+X3MVq3cHj0$~p z!3eisRr>0x5H41gwlgZMrmI3Y->A?ko*-7&i4)dGg*D`gVq3cHj0*j9!3YcFGZ%zB|zy0+# zA>4i=buC>L!ucXK^7-qR-f1%JJ5mSeZ9=%%NNqcJnzeOR2p6kL+qu(ZbyWzLtpBdl zzWeXGdYce#zmYmnSA}rCNR51^|D|^tt9?i6AiYfp7aOT<=T5Vpt_tB|RcSkSn!&m% zgiF?c*JuB2_HDqUN&Gf#i0(dNePwS0a$6RDo0iB|fE((95pKV|Xd_(}!ufhptN3l& z#yWArdi-zFzT>}E7mRSR@!xjttwVKH2p6kL+qt*a>8cQJ)uX~Noj75ARM=FmD7K~B zPWSm-{M}uLu6^;ZkB`mg&l28>cqYmm6U`o26WKd#OTA49 z7Z|B+P?fE8RR~A6Y|CM62qU6dbN+Zwp?l*Lu{X#lojBoq#J%=gxkXeP;)UNL^Ht$R z{Tg|yXr@i$y$NVDTGxiKJ`3Giu88!hl5Aru z!d~;Yok49IT@}Lln$we^jrW4Fx;BLMUNFw<1?@7J#_NI+Zoge@TU`~x`MQ{Q7bxY3 zS+5f(Tx@f4$<=nZ)x)SduEiWKYS3*t+IS|)ooQejx&3aZ3r|=dcqYgdtvZ;t*L@;f zY%sN*+wTs#Dujzw<+m!tP4+AA9!|=D_V6h?W+4kxWHiYo+;bT*sz@M4P>zIHcfx-QC3@>>F>- z!`l0Txwob#$)9nPWPi@gY+%S=mmW9tK%E<5o!dbgw;4%%*Ltwdjj+z`5RKc!B)A=_ zb0e&Co1$?$Aqj4W>D&nG+z!{c?Vbd;sX8~pI=3S(Hge{lHfL7=SEoP)}V3QDTy|1)VUGXxy{hHos)!a$LQP$>)ejjxJ^xh+i^NK z!aBF(HEw$+(WWzXZiIDivovn=lHfL5=SEoP)}(PeJqd0n=-deF+~#Q9E=YpgT%8+X zo!f~Tw=0t1Hc#h9Sm!pM-15AJ^L9gN`H`La&CW_me3x>P?i1mBlWC7Q6QO0wUyt|# zoj75=F-|V1F}f7?kx(Lyu~7GkaK6SMU#_v_Azt_!TwS(PC|k2y7cdf*Pacz4OWcCbQgcdKX~~i&iIQMrmob96V@B! zDmF&5A@mtPP?p})$kjSG!aBEWG;T-xx-C6!*XrB|>)fs*w>-}^-o3WKSV-jI_j=tY z!VKc*hZ%1#rj`Rt(T{jtTRcvCCOYbmc<=gAxb%9+4Z13X^_ITTYw2jgyb-x&!+YKq z`b^w%0Q5}s(giy?i3P2jbioMgg5B&1rcAB9NB))}WoACVba~|#*4}JDo1es>ajUKj zVO^QqmZXd~wQ3nVOGla8z1mw%ATReT2J-Lq<|3>&*B$@Q-gUq^Rjl7Eiy%z|LF~YS zt5H@FL}B%+Sg^2)3fOyZ@9Fc|o^=%qw&%0=zg@BS5*2&zz4zXGumAZ@G9Mv1H**7- z+`Aj}M|QrGJNKSBUzxcji3&ynxkRd0#$7j*I=Y^rqCqYh&ukjqSnB9HzZKUgdivt! z>dsBvpMb*_Y2_04GBMxGi31KJ?u@pAg6Cx_xP=o3%rofLN=A_vXWYie1US*o$Z+C- zxifAr<&1Iz?7?X>YULJZcknR*4s(W9!icrV%cs%rxvf^2`z z$4dDwJ|@6?On2*;+zX7Zc8FLIPB($+GS_})GUO~vmy(c+@1k#Rf#KRkkMOgTxl8Xt z2Qp{)F1nT8g$`uC@LlxdE2T4hq~Sf>^MJYM?=8dgC4yT$AN3rmhCTn356|DnJr9_B z{(gAApdP&(nVY?v9pQ=E2RJvtoZEvMm1O;{^G0#rR&Nda5FZm@OnB}>ipqt}!iz`L zbebc47uCGv@Gw^eF!%H$iTCuQd`y7DmNtk??phk6UKah2apHivGagU8GoIjM0vzUy zMAVBXIdQ^@iS>&h`-2*1CCheN?g&1dY++D6t59=7qjydvyCG!fy=nP`w~|L zFb~m}BZX+h%M4yT{R$rw;6#V$tDHDsC-LHdqAR+^BR_UuMijlqi38?Q^m^i>=nXz5 zz)okxS?J#6!~r{r$2qmU#fbxU5|15y#}^A&W2hm;gJS5oh>+#fbxU z5|1_e$ngvzmSszh88y6NZ50*}mf+f!Bu`?eNU}xq=EID3oEY8k}19lQG4r^K~ zy%6uhi31KJuBW|yicWhe@m3$<-<1;w%)`H%^avZ17Kk{*zdIijU?=f7!@mb74j9DU zXI|=n;%w0JT6;x)4lXR?B?s*0ff7 zxuVmX69*hdJP}be7bgywM^T?jMv<2pw=W+P;4o)s_(zN)FU05O!~us9Pec^;?FmrU~na~z{}a!!rUi-oxv0_3%n3-5`4k*rs8eXFf;lctAi-<&|XA>t5 zn5X9w(j#n48XXbS^IIREb6S#*39yqmMljt?$?Ubk=-;d6JVfzL%j#Wz9Llu;>?9ts zba}aMx)di4*h##&R+Z~io(sbwOG9ps2L@bY@l&?_9DEG2rS&@$kaF{bRJtIy+UWl*6i36UMo->i2qq(qv!y+OP z>A5l|4w$FsD$*ltOd918*N9%Cd{sUsz)s>3)6>fd{aLy$&A};4o+C&j7V^e~;tZ0FF2{RQVQjNM+GgPv7uMb@rn* z1x3B1`CQgid_=3Ya^LH}E*BOsPo(t{pGfQTF#!%sB(3;yR<-e*IN)SPdGyswnD7;> zU_4$YBtBjza<>BxlTG6_;+ck*S$G3Z9B{;VE#ZE>bz$paNJ*`7VK1o47e`*smT^&c zLoO^}9_1S)KFT-dV*;G$DBpw=2kays=XA0uCk}X4dd|e-Kz0v?~4x#tmdeN(KGt_!;7zH}w}B9sqpdmY-0{20y59(@Nrx?5OPr8pl{701VZ z^#ru|-mmVWBmd&`?mm9YY)2l6fSm=iI5_BYT3!~vJ8|NGd7SNBhNsm{aQSpkyA`=9 zWL;dPV6m(7g6XBNk6_t_YYsTk!LlnS4wwhaZe;`us=>_FTRn-wkLK}s>srOK@DDB+ z;6!`+pPV>g?&;mt)1{`L;)-9rQnv>m6JR*QJ#$sEo)uSpEr}JF{Hj^c{>6m_%!6gm z#0Sg2`IrEQWp0TAMx)%zN@Ooi958pr-f%|2#CM~Qd$0R&Zh$$reHpiGG@itX|8N{m^`f6gnxFSOhvMp0X%WG&}Kmy;tNw zF5}AP0bE$XJXj7yuoNWO?~%Ecaq;3H&J8f#V41{)1%%5*MJd#Ao*A_qmDp_y2L(0Efw@i-h7c*y{QFJWd?2lX#qgdOjx(IE=XWK)oRG zfqEgA4RDxji3rq-IB~#E;&BG*#hf@`KD}L%_$a!Rj|p(1opBi_4%kUN&N@AX69>$r z=<>uz(G`45fZ+`H0|Q!`iZi^DcOC4Fi-JpdURGdNa#a9xPhV9@PkXtfay1_l;7X;P z7vk4&;((pRi(`_m>%0)ZmJ&=Q1q!NdiJ!hkJG-lIdQ-s?!GBs zVwx=brhM@QAl-%ibXQ0i=rhrC7pbYcu%9t2i1L$s2>T8f7BG+UcQwl0nrrM77a1L` zeTu;)7*2+#J9*b#gnZ}EXdi;T#{~oIOrheqp(*4g_uuEl0XvDuS+qXj!~r{r$62&K zDk}aE|i1SiZm;1FT zn%VLnvWqA)i2ZiCf*Is&9|iGKE-YXk<)0-!%0K600-We5|AG?-oXjY%Mu>jNRRPRH z^eYWfcUg#%(~hzbC8zB=sX(xiK63hNE*Rj5VN}WGcJYL##WL!0yIgn!V#uDdD7Jl=EJ2|H?&NYpFC*H`>^RZTv)(~E-c@2;(&PyeOKWWvhhC?(_%Hx z6Taty0iKmYGw}u1KX73ICpv|G6fFq_*JDi(;;i>?RsERH( za7M#VWE|yIg)K2R+iZC`xo-R=pY)ZT8e~GG4&6AK0Trj}3t4cjr1#m=FqSQ+3 z=#W^^!ct-dWy7stt>ERxR!6Q1;E1Z|kV>qe?2tlKQDIB0pscXfP-Ql*3Sg*G>ML{N zyx-A@69>#|WoPM8uBY2it(=_;1~{TB8oVXWt8DOw#J{FcLaIU+t_t9Ys_2l~PgUs3 zRRNsns?d!S2h6KNcj*z)(^2BzQU5hqO2ofCH7lt9UhahS;DP~mdb+qcR_}3-IXH2^ zPU3M+Ts=8)z&u3fM2Hqd!zDhR3GBtW0p{F#gPW_^#~CPd@i75*21;?3RxiT)aN>X? z7A&nc?PqH0%T)pFbZ4A-KQ|{1nCDhM>ERqxoVhg*9~0n+A=(b-)OooofSvA)Geqa( z!~ydVoj+2D##u!d;9~;pbVi)S7v#hNJBh~`MGJA_fFl-#NER5PIMcI{j|p(1i7ȇlRRGd&mO!~rKWJqxBjFAw3TxhjBpZY?G~oSrUT z98~Z8esMk~z)s?EhUgGZ958oAlRBd&A2(lu3kEo1PFLVcj_#s(LeUkmy?Yb=D>M=v zsY`O<0rN;5THBGj6c-F|1tZno;Rv~Itk;A}+$6X6Sqf$!FE>esaa8~(I{t@q;(&Sl zFJ0U5KY|MeIMJS7h7$+OJ-uvgdwL`n3~;%Xu6Pxx6Kd2-SK<;=H7ngHt_t9CRVi`L zDXJVG>~sWfxp0rUJ_uEP0i!^|}&mxxrmdMucey*$phJQoabG9$G>6)!85fU5#H z(eu{|oH$?}|0~vZ{IA3X16;xQcT|NMJf|GZg$K+db>-TQ)K$1(fU6g&QO+r=Ie)Fn zRRNsnO1&B<4w%RPm#)YW5&m5MEE)tHl4=Yj#Q-S}UFs{%OD@xLY~4w%RPS{06e z8@z2~r9PGm1~}24ZsEiMb5E~b+n!#B3kJB{N>}2VN*jy+aa=0ZUa+w33ow#@-SKieD_EMS`r!9uniU`yLvD%i$0hXvc&=I~%g z+gv)>*)~T6yV>S4!5+4`Y_O+ojtus(%~8RAw%Hu)Z=1^n2ioTHL91;B!J)RfLNLiT zR}7A@&6R?qZF6*RtZl9w{LeO52~M@mRfDr^bG6`n+Z+>IVwHa84jx6O@$H*Is{;62;iB>2EKHw`|v&CP<(Y;*JAE8E;6_|`VJ41ToD zt%9FzbL-%D+uSDj+cvii>hH|u#dbkw+uT0rW}7<%J#BNxU@qI-DVWDLcMcY`&0T^9 z+uSu+#5Q*ehS=smf~9QppTP**+&vg&n|lO-ZT>4***5nKR=3T62Q9X_SFo;a?j209 z&3%H6Y;)gWGuzxR*vdBl6KrRj`v*JO<^jQOws~N%hix7d>}8t=2m9LQA;JE(+1i>) zrGi7$JXFlX)jUkhqtu)v=Fw^%F6QxS9wFw5Y91-(DQX@i=4on97V}Isj~4SBHIEVV zJT;FM^FlR`6Y~-^j~8=_n*SB^Dm70K^Ex&EC+1CRo+xHU&6C8uOU;wTykE^z#C%B2 zQ^kBt&C|quQq9xFd{)gf#C$=`GsS#G&9lUOL(Q|rd`Hc5#QZ?bbH)5v&HoegGd0f> z^Gh|)7xQa1FA(!vH7^wNM>Q`J^EWjw7V}RvFA=kDYA)MaFBNk(H7^shi<(o!?4jo6 zV)j<^3Nibsd8L>OsCku`{nfl$%t2~iBW9zT*NVBAn%9Zhq~`TvE~VxTVh&gHMlqLF z^CmHuSMz2uS5)&BF;`LZRx#I5^ENSC)Xa#vo|?CdIZ@3!#N0&9JH^~W&8cE;qvl;= z?x5z~V(z5oJ!0;n=DlL>rsjQO{!`8S#oR;92gKY{%?HKYOU;MG+(*ra#oSNLN5tG; z%}2#NP|e50JXp=g#cWmc2{8{-^GPueSMw<`k5uz%F^^XB88MGl^I0*ESMxbBPgL`H zF;7wR1u;)k^F=YwRP!Y<&r$PbG0#);6)`VV^Hnh~R`WG6FIDq(F)vs14Kc4&^Gz|Y zQu8e_uTk@DF|Sqg9Wk$0^Ib7-Q1d-8Z&dSrF>h7#12Jz`^FuMGs`-(acdPlanD?sr ziJ14R`Kg!>s`;6ikEr>%n2)RZg_uvP`K6f8tNE3fFRS^rn6In(jhOGK`K_4mtNERn zAF27hn4hTmgP32a`JI`_+c6zlm9|=I>&5Qu7Zn zyQ%r7m~*Q6mzaIj{9DX<)J&Oj8Z4k@otOjE>>%b~HS5JptJzV^CDfcv%wcMF5_5!_ zoyBZcb9OOTP_v7etEkyk%rR7 zh`G0#3yQg~nhS~fA2s`nd7zpD#5`Edfnpx2W`mfAt2s!_qtqNM=Fw^{EatIlHi~(? znu~~ef|`qpd7_$WF;7u*F)>e9b8#`xQgeuy=c?Hx<^^glA?77&E-B{aY7Q0iDm9l9 z^Ex$$iFvb{!^ON^&85Y>SIrS(KBVR{Vm_+ovSL1|=14K0QFD}-_^DC3%Fx;@=F9r- za$@4g|M2eeV!o;G24doe$?)z9Vt%CWt|%scbO!IPBqn~~1LkNk@nZ!rR~8drybf~} zG4b8PFjp0`&R$GuT}{l+YK{@JyPB(ui7zKY-!;VSt?#ZWCceT1@2({#zAgghSTXVO zbeJt-;^VL|*A^3>;Dfo2nD`7C%yDAkgE}zR6%(IZfVrNSc(@(r`eNc)S(xL+#G`{S zCy0sXvtUjX6OXIF+(1m+y@$D>n7G9Yb0aZv#|Y-eV&WP%%uU3^waS(>t~5>PFrhAu zFLWK(d-Vya39Wyd|Hk!i?Ksc*t>Xr?{*@XxyvGi`7nr?%;Z|8OrsmkJcl`$4Q$5FZ z7+|irjH_#1c0?*Q-u&OVqtSRw)Ar`IXOT3)u4m(As6Q}fa?u9w+xXVYrjY`f zKTN)tcI^06^MM9QrT51x+T&9h*^zV~dSUO&8t?@Cat9k|d@4Ozw!{8%Uu?S*Ivy>r zhUY)cU(gsn`OvxQdg?y12j9KqyK>NJ-LlLJzOynTdobg`517cYY+E#wdx_>>%Mb%* zN85amfm0JYrH_%nhTdN0Z{zAytc6k-K2Cbfq(k;L`S*8i0r zM(cl>zlk1k<9@<$8B>I&9@cwks&x$${~0MQrg}^?|1vTHqe!--m`%oJq=#vYI>G#P zse)~6kKu=Pu1~ExRz>=s?7)b$r}^tiq<@#%wbry;UPq0!BQF!R%vf5-idsTHr%*;} z^t4}48ryiR2#c@#Zv8#ZqiCz>}!&wb3_GWCpF()KO2>q0%F?({!qr*_2IDkmeb>DO(#x8}$Q1$}RR%sc(@ zDlc`btei>>Lzv25O=ILq=5ILNv&;_1G@W5yn@*FLQ_Kt25E;QtXbmwzXr`{i1`X&x@_YlO8qYDW!_7Nb z$6%&zzChkcPycqE-9r}{PhEXR_HVj%L6>-)?rJuA_~WYCc=`i@~Bb zgM%Gq2YZd#-I%7U%xlvX@-jtUE|r&y<>f;2k{!F4hQM++n7?KfbF2B2O5Y~0jn|pi zMp135Fl-G>mdp6`L67X?YqC@Gezr22#@NP!M>7h430Fu--e;3v*xBTl1Lk&>5yI0- zNcKnAgth5)X+z7XjA>36sMiXR2J9rB{c?bKh~LhM19lS6K3WqG@jEziz)s@Xukvsb zFZ|u{iiFCYoH*bx;(G7D4;Iu;;;jY0;8+pjQ#ob%Litn>N0`p$3 z1>i9H8hvq=g8Mjez+uD_Q3~$o!~yeC@PPCP8mp7vfKF;($SXRw0RaI`|}460kD_;w&UjapHi( zh$o_uJk5y%=7r=L=@B+2EhKT~dS z!~r{r$CZ&h$kX%U*yCA^SpgYdW4Nh^ES>iiI@4906U3CEI3}SV!pzO19lRR zSa7@$f0Yvl>?9ts;CLba8Yd3eNj%Pi^ExLEnCI;q(!)8XIP>;RJ|@6U;&JBfTbwvx zC-FG*_H9lau#69*hdJP`|p_c(FDyx_bqJqoWIJrenhKkq`6 z>+atNoEu=y?L%;LT@i~|485%3KjLEo92O|L`ifW#y%7JH69?=h9V>ccHV$!Tzv0{fb8g=$rs8^&Y zidaOwL{V=(CcsW-#2H0%apHiT#N&*jKAbpU9z}f{O9Gw0rT*mPkK1V6tReUIiH!Ij|nh{yRX>k{kG!MoBV6&GR>BE^&5vS z{XsE3cJ{Y{@@_h|NbisjiuH|ro1=`i!2(=Kz|IheGprZn!~yfLUP!~*9UXc}6azSMz)s?E2IfFc954^ehB5+EOGj;&twCI5z|QE1 z7}j29uECr*U?=f7!+K#(954^-Mh)vy6KF(dcsUnagpUbuqMflQCk~i9BOS>ZaR%68 zd`y7(m==#Trs5f#UcUAcU_qX*0}dmuOUgLENoQ$J954_65z-@U zOnUwnG5i;d{CHy-=hn;cF#&cGj~M=5h%d{D19lRRGyF$#;()`5CnEeuapHh^_%}j$`R&Q~;5+4&_KBm!;#uRaq^im~O=3@e!XlJa#i34^Lk29rL<-`H=C|WI2 z6oq9*^p7DVTDCDl?0sVuwIK32OLH` z5fl7aP8=}L#}?@kHYT0mBj%%*$#88xCcv}uF;m95_c~ljz|Iheb9Nrbi31KJo``&0 zmlFrf^Km`t5jG~x$B5VOz08m6^DzN-5)WGs72NjsLVP?Y4%kUN;`Mtk#3yj#fStr6 zmToV^CvxI|oy6lTI2&-{fWwFZXCvtmHl}h5j+X_%#(YeGox~#+952K- z;lu$uiAO9rUWjkXi34^Lk63WL5Z{aw2kaysXTjN=69>%mb_?m@98;Xm*piP4u#?9s%!P%M<2kaysXTjNq69?=h9%qbi%ZUSa5|1;+x8uYCJBi0xDYxgu z0f!M!#L{dBP8={V@jFV7!f&QqB=Qr{d5_S$J`J}M=LVQ_+nI4&$OpGwI5)tY+pgeN z{-+eGchhP&J|@6nL9A=>IP2X%IB~#E;t}hem(P3tlM@FF;=ZryYYpmG^j&sx=#bAp zeB$G?ue)#o!M~)3b4(Ef)5~IWPd+BVPU3Nvf`4=3fStr6D(?9s>BKMN=hj8M6!-zv@Oz=g^@a*YdJDE3Ixi)~qw9%DCoF95P zloJQcGwd+w5jLhoOsbRkm;i&gd&OBIZqd2)mn-NaW&Fz(x|jXs$WFQAEYgQ_xdHPK zIsze7@DRd}kw5=Z#+9}sIXA$Z+fm@=S~JF3hbQwf0S*h467k%w>hRHA8^GM($CUCn z&KPT8`Z|`&2AIosoXX}draCDUXHA4+s?#JdrXg4IynK_%@mwarwVrwZ<=Oz|A#{R< zP^m9xh;ym_KRzbFweIf|xi)~qw9!d6Syg5}CBK9(z|aBhG(w^PB* zwOolaiB98V0*pX$Paq{$FA*jX$Mn;q^jcnHmfuLSYx#ocnAgXRq|>>QfWuNw2OsAd z!Wo=6U>??IYFN*Tj)=c*eij!QFcxBuhZ0CR5V zfm?-Yu9qjl&*x(TJgerG^C6xKxRQVqU2`ww!~yfLzDRoTw=R~qoWqUyEaq=M=Eh6- zZ~^l%U0TU8)km&OQZ^!1^vn2|0P`_Ti8Q7-SA&=HF#(QPnRH209B&a;gAu=x!&Tk+ zr3^1?$-5(;X_OILS8zW7b|!k9Yso7)alkw&uF|A%uO(;2R$XfHq+%0|3>NI98<(;+e;MP#K#2KNj%Q*znK#U>?9s%_}{{b0}dlTn>=J8 zlN=T~nY{a?E$!+q->qC5z&yillOAER>7*ZLpl0}(06U4t8K}2&;((pRiyz6Y-UM?8 zCl1(2JkAN`PEH&!5C5ss!#Son!~ZTmCcsYOafbihoH$@7@i@c(9!?yvlX%3nh?nOO z@8!e+JBi1cxA$@4fO+2DFFl-Niqjbn@G${)5|3DLyhPE1oH$@7@rVV-3-O0IallUE zafbiHoH$?}{*Oox=a?dfznAl(NBNilJBde(A}_=r?9s%hCR)R0}dlzD;f3-*9I`puxF)5;l~WeM!xHo zcPYg6BfGE^TNT^*;9l;IPzI;p0q- z4>)naJSje`WKwv!67Ufp6JVz^BA(%RA^tHZ4me^qYcVgq4iCv@?Oi+-i(VfZH(8!+eg7vna!k8jxgn{xxqxux!nGOz(_RntrrR35^e6Cc8}^AHB?jIUWCJbBX94J~7xLbZtyc8(&>>7xseQ@}j;x+XsN zy74gq4s(W%IJvYyj$eUOJ!W{=*`Cj z*cr8Pp5o2Li31KJUd>W8YpN?X)%8hyV)W(l1vo6ew4BG87;|&tfWwH-N{oo}kP0>P z7be1dp+OYqRM(FO5nw*m%~L9)OWf0GSJzVK<+1_hvdyQmx$lf=WE3wL^6zbhJk+Hh z>?rGd@kjeubj;6X0*th9YoVjzPqo-@`47=Tl`Nj6^OY<(pZ21~0$dBg5w+0K6kpBC zA5DlBs$_9VlipUzYG|<_*8(t4pM?^hKAZVSpZ;7Xz!5`6onFQC@uI~5t_9$TTEvk) zUbGmwE!GZi#XE9ixx|9EdcZM8J6($@ls`mbD03w zTF5NTwE!GZi*{2=MsO_v^YmFJ;pyY0$}G!e0$gs$RPiFd7cE9|EdWQET8)!&MjTMPsaET9=K`)ZE!N{&0FJ0d z9M#Ip+G>5S1z>2A)M_=J69-(b6O&x6CdfD=4k(Ul+q|=;qwH zfXj7m6*JV!dSVN%1>i(y=$4!~;BuXqmr1rGXIfe#dwp_dB-Z!~us9SFaU+0=(RBXW%y{wii+nLr7I@>o+HM;GO_n zYg+8cwE!GZ3k}jLE`+?Cw(Z2V034Q~niO%CmYq3qz+uGIYraa$Ep zR_+PF5u;K|XInoVJCthyIHDHqCPNS7S^y5q&<^%T)w+1f&`GtJp@(x%0FD@y?IuHy z;93BVs71TU&?C7PfWtBrkB7)oA?)`fX7*EJM*I95E`@F;!gUdWp*8xfXyUYSC^o^uJsS zz+oAxt6X2_p(oU0hW?Lx0&v8rY&RKtBG&?NL@nA)hMvT=034Q~y2|x+9(r;uX6Py0 z6M!Q|WxL7HQ@Iv^BWlrZGW0aA1>mp@)xrBZ4?R8M8S3S3%Ng7gfD;^*UbHxqYXO*F z{y!_>A>-v_;A}1v-~@+^7cI`=S^(xDb8f;z#!F`XAD0Pmf$xfX!S)uOG( z#U)$|z~ySu*5l$*t_5ITN-mQg<;qmWknu7TPvJ5FE?0}T9x|76EdcY7xdI_m@C(d0 z+*+5KdgSO!8d9x8d!X{-UV9~ch#scF5g(ALBGYAzGta>Kc;YjF+N0&uxnR57)^ zl(}oU7JzyBT$k|l@v@k@p34Nd+>oha`gqae2CfC*a^5o<29#V*1?7 zWdfYwknvJ+Z{b=1<{@({LZ)Cb^|p`2)NPy_V9qTAZZ)=;x}D1exYok?4z2}YXhFUU zSZ~|T<>{HUJ8Lm2r*cmKuC=JVi)#TmEGqRmtlplY^6pxU%6qsc0M}Yn-pjQB92S-O z>`^aIQF&j&qteT|{eJEVz_k{Y4{$92hef6L8T`RojLL_&Cji%4R6fkL02~&T-e>Sf zYB4Gw<(>dsYf~ zds)xD%C!Jot`=3itL#OK*SHpd!}4CwG9u=^m-XE1oH$^f_isp#a{b%ZWBpAo6X06Y z;w`QP;BvKS>v{h+*8*@@-X~&h`wk}#nCJbw(xY7ew)MP!kIMwO*0gw^YXP`iE!ukC zf55c>9G3TqSm%Gpi38?&|B>`4*S~E&??2`;0WMdIwjS%Ba4i6b#kzBCJG0+1_h~Ig z}i+z~x3|Tc0<+<5~bNSBthjZ+y?S032I}{!oh<`Xl!Q;985ypSTu)!=lo8 zZauT}#?Q4FmA`OL04_Hw+xoomE7t;WxmvXKdE+;(1>o2+^!HlK&_B2*04F#qy?jF8 zPp$>vu&8uir>e#?b$@Zw*(f9(8(fCS|=4;Jki>Wl=T8s5Mt_9$* zSa+UV7sR@kXX-j|;(&Rq*GrFb{oB@88y&e!fXmgQimMGTb$vFj1>mq)cb*Rv#JZPf z>N;`afO)KUPI#<)@$c+hCcp`fbuZ76b>Uh74vTf?8fIqCeY@6TRCeQ@09dR#UTx;1pH`fAiST=W(Pb`-4$(ffT=V2M2 zi0sFS1Lm$#;lalkz9 zM@Wxy{oB@KeHktj;9ApSS*``(a-L zOn_@mi{-f%fXmgQt>=BfwE!HJ_la2NufT}|=6S!O^eETAZ9VT-;xYj)SBthD>!Z0A zfWuQKaJgEv^$cB&YXLa63>{O88M-?61mIeW z$~CwafWxBFd2Teb^TwLB7?o>rPXI1AD%<+JF_voqxLhsT`n=J?wE!GjhOS+U8M+Sl z1mIeW%5hu^z+qA8Jhz_Nd1KvLjLP-6Cjgflm2G|ASf6VFxLhsT`n)loYXLa644r@s zEx1>HkB`qnP2|G|%&(zs0B*_sER>gfq8oCV0M}Z^Y{azy9F{SO_$<`MoH$?}>zmYK ztZ&L?0$gsaxAmEFGp+^TahNu^_e|y+ol$ya$D{Rz~x3|ThGw#xE6rR)uOFu==NL-z_DfM4rOF$o&9=% z&P6|%EMFSXvCF*X>jTDy4W-1*1$+r%u6MyHq?gY~@5ns?IAT<`8!dL?S^##svba1A zLkJW&@zL=CQxK#(oWj&>mbSz_pf6|KeHz4ofGk^KsV1Jvni}vD^_b~3I0o68NDmzKSxN1{V$Z$2i#<%UpOpH}zbS^zFri&^QkcV>!NflZ!t zb;Cq?X_+YBGT(Ti!Hj)rL(8arx!izxI_;Y<&C~~SxdHRia**^$bO;^H#{@WH2HZQ$4uSIN9+*cYJTSdH z40a@!39!?@abDm!iW3LyBpzpAPUge`^T0eBfmv{OV3)|>u$_0|#&zCx4Ce-zb32xC z+t0_-oyT!*fH}A08Mg^Oxc!%N1I)Rdz_=aigWLZ&H^7|RiHzIkKDeF4xdGbom)5phCAy@D* z0S;SCD{(ZYyXaUw;#YFwfVnfSisX#hqdlVI#Ti%gF#!&92KeH7N(k}j_gT4Y*Fd&{ zbC82F`h?QgbEQ(5t8iE6n1SXl&M^ZsSBQ1kpo!+6jgBFQHw;WoG%v0bk!!gIfH}eI z)UWQ#N*cPwIfu@rA6Il-Dy`>_D|&g-?RqW~V1!ByX>kMB0&rN`=%X4DYnT@&-pGjq z=COWLEynuITqeMY_U|p6IAHGITh+hhQN={W>}`BZfccm*rN*QMInH_ac0MM+VFBix zcME3BzayWWmGQju9h^8|?u0XUcgEd` zcg8(@On}3jp_viU89(`O#=V?4VD60jA~_?@GIc*66JVz^BBu20(-!ta%@gt^7WQS7 zsRuZ5z}y)R!Wji6^wDX7QsI-1hd4pNoZ!QZ;9k?jt1!VwI6=Ui;G-az_~4_;u$UvU@p(IrR337 zRdLuBUk<*Hcn7?8QDQr!AE^`b(vb zjRPp95BzI*D4uB zUYzkd9~0n2JL3&b958pro28slZh$>FZ8ELgYV0jOCct6N&`KDw7J2!M_uHH}VD5}} zN;#vO6mm?>MGItFU!U`_G=7(l2{0eidpaifvZAXUBG!V_O<>a5epoT&JW3akP^zeR z-`ujo)w@TLymIWhOZQghbJE`3O7~Xg^U>b@_=4yRAKCUkcQ9b?;19}haETa3bVQV? zMjZT<4+nq99SoQ|_#-&DU@h@-WNu|V_xdsC2AFgEM1zm4#&s4bPD)xay{t$-C0UfQIW72Ef1-PSu+RiUCk>7pK&b!bN_yxc>jLE#{@WRd4hQ44yA$VW#RrMCk~i9 z~=27%l;-lzqJ|@6UXT(|FQumv$ra%=MEnlINYQEMybDc^9b`p!pWtOmRk0M?NONPU3MoV>V74Fn30$#5Zv_aRr5+s%q) zcCH0r?%yu(Z^6pripZ;}GAg;1z=tZ=9eB$|HfGg7T{w7>?9s%DOivb2V9lF z)Ki1vx*|EzCE{K9vSzq-eavtRaU}usu()hv!DdKtNck2^|(`IrDZ%R!uX92Vxp0dr?GCf*r~@G$|7SmLxu75fGg zcj+Rfz0oLog3^8lD%0e+lUkHYP0#afbhr zd`y6y#N!PAp`18i5O<$ZsRN3$p_Z!pQd~*EVIh!+d>qD!1LpZSTzZ6!Ny8yxK6+U> zF3raT*h#!Nj%ji9a%pA+Ck{A_cp{=`8BQE9kD_HO8AV>E*pYlpfWw@j;U6)IybvG7 zi31KJo`@)F=EMQ>C|WM@QM5cC6W}msBqE9eP8=|ZyVnN#D=9PdduEPvw#xnJP$FV~ z1ui#W9{VdMKK57QV*(s8gi54BEiErcb0q?@1BtEQH@FQaXi-su#iBA-)MG4tQ2rXUYicO}UbQ!$Lr_GR|iPHsizr^L*S~dW4Os+?9)$u-<}? z3Gl42E+?$F??6S2C=f;bNmu{LaFW70 z`XVJv?g|zv9;N#xK1%oF&ITMNn?`BGGYBt}?SD9Nz!9Ugg!|>Tf-Qg{<+CcKyP)`9 z9C?{q#`V|zxsrf+SRau1us)EF32>sr`XEjmu#Klx3prwUS> z1?XJ*`w#RaviL@<^zNAJT~Hmm`}m=)V|dg7b{5CtXrNC-d0EOH%ZUT#(RExI{#6gb z(bGLwmhYjERj$|Quq*6>=;-SsI*#We15R{w{Ff64%%kIkGNJ=Xk36RrfgC@Sq~}2R zF}I@F>RQF@{~wnLaH9QtA}0=*`}ZXEZ>hPZxSUt7qMgjg1Q^ah#AW$}6rKu|t>U_l zL(kNtR?V_?3Re;^kB(ClA04OhF#!%s)e?1zhP9U!#_60mVD5}F;EaO#?M5FrLeJ#f z0CR3XuyIBz?fa|6t|oda$mr9syu5g%jsvS>S(j|p(Z5~t%RJ~NjhWj{$CqJqx7 zd|l_5x%Jq*Kz8CYcdy8iE2Pbj?_yCg#k40+y1HSaytGV|-}`91&|t>Cw4r6x|8XS& z^XNDa(NU09zena)#ubP2IXA$Z+Xdhj;xkn}&d9xxj|p(Z$SqNgBTTQV0*^iWwV(z5 z-8Hg*%ZR;;xE6r9e=knFe=p%<0$dgU>e8(XJ*RMd;37fMaVb|4FprMQ5+5B?_?Q4k zj1I3C;Ck?x=K>$ue>v9zF!%2j@NYq7nlCc9GG?ADIXA$Z+f|I)ARpYW=G*{tZr3nw zBYbeXmU9Elxn0M&4e`P4dd>|n=XL|*wt^3CH*#)(Ik%g@twJjuFZWh%=3@dJvDWEq zRNHIxTey;dd34;G_~^Kej|p(Z=$N^6aJyM2Ww?@nd34;K_~^KUj|p(Z=x8_Vq&vA5 zfVqFCM)Gf*m#FXJV*(8Smb$iHJQ>i7kX|l4-OY&u4kKRTT2Yqx%-(RmC-MHim&*n? zOg5eTi!W4E&)@fP;((pR;|$dMIdQ;Y#JvaV1BnmR2f1v3!(>ZDpgzQj19lRRGf*Gq z!~yf^?UBSs(W87!fD`SE$2f7oPU3Oa>Bl*7z&whcNPHAM$;Sj3&T!wy*V0s+;WK}$ zz~1C4xFF|c-SrgL0x?9sBio7WP5+@GWNj%Pb&o6W0fO+`8B0Um4rdRox z06U4tc?sk-P8_h4c$|6rIwua;Nj%QHeS;GR%)|dp>ERqxoGJYl9}{3F@i@c(ZB87p zlX#rr{|+Y(*hxIj@PC&R2kaysXNWXXMD)V1lUPD zPG@|?i34^Lk27yS=EMOziN{$fKjFjy^YH&vdW4NhzezZvGy3@Wxc+B+On{xlF@otn zr$bMDy%7JL69*hdT)(2B_@}xmbK~lZ#QXb8E*s!5*)&k&^!HbsIAAC7FnGKk( zUvuJsdDZwP@lo_G9}{4wGvbV*?>KS5PU2xvG_$w6zmMeah-(cmG5iCU4X{(TIEnwr zi31KJ4!*dXQ1rlgWoC(=BKbScRl(0(Ho#%B=`0Z^@n1M`z)s?E7N%c0alm|*_$~2K z^gACD;6yv)4^AAglX#rr|0gF7m`BlHh@ygZ&^eL6GNFu*ApFg_0p{FN50p52(mTNs z&j`KTf2$LQm?}og=MYoP*P0I^rqY1J0!4{05Hh_KIAdQQr+pnbaljz%z7=0$nk?s5 zeDSp(>1{u?7xH-keb#yIA`PXt{Y+Sak|+64vYsmmn1^*o4Qsc^8Z5}M$2X>M@3bruJpI3Xay`T0St`Cu;0&C zFj1WCqXKs4N&@C#-6Qc~JqI5X;6#UYPfi?glES(gfjKAF0x%EEUK*J0?04j^Bl~p) z!xwrXPi&6#k-xpUOn@VXOof)r#S@vhA?lL3UpY(WhR9#wQ^wb1%*B-ioan02hZ6_P zGo^3kGR4OFjLme_T}XuG3BPh= zm8^yq3vw+0C%OhM#EApuHL$<*DA&LIyf~_V<6l<~;4%S@s71TU`+-~wz!9}*H+kQ{ zwE&#xydT7g1Lk=@SbCJ}U!M22GP~+J&--egB`nNk0$giaG;%EfN7TYm1FdI6;zFwi zU;EgoDwyxR+$mawYXLZ-7CIWf_OYW0(L$BvYagp*HMCfiYXKNql=@nkIBy%IIdQi7Jw6-_e*f% zfO+08DLo?k*AeTEx~|c|W8I!H71VVv=l4UoOn{yKEiQW1dm3UXP8_h4c$^c`FispW z56s~R%z|jR#K)6yOLK03Ikyqu=Bnv&2FfygOn{w%QkMrttW?kRc0@)7R0QV%cJXYnE*%3-ZeFIJ$ zFpu>OYcbY0;xYkFw0}3|!~t{vZc>Z>-IU7&xZGM+yb^3%tBuXL7J$pug5U9}OkHm$ ztBuXM+<juV4-A)X^~tZ&O@0$iC`cjSF-o$qbO;I@+tUG2{tz|sct69tb z$z=kZX#eici38^T-J=%$`!6mN;BspjzqZkKVtr4p1>kbEn00Mq@5~hQ{hpI2UEMHI zURox~mwq;0XfR`6+R!rU-&}6MJVW=YT!yxt)yCdjCcqJ+Qs)!?u_s4{I?ng3lGV7j zu@Bb*a6~P1G(I!58d~hjwE)c1XTMrZpZ{=~0M}Z`?9a6T%tPjYS`3*3xlDj76Ecp9 ztMxkmYZ(V|EdbMynNZ(+y?n2C;|=C@dGlqaw~8e2W+!Gc+56C z2G7{$Y{5&m*(rF#HaiFJ+ve=Shql=z_|!JL2A|tzx8Mug>>hk=n>~VWZF7#`d)w?8 z{AinV20z(mui!V^>>d1Nn{x#n?#YdU2=G;Lq+w2$gwas~g`D}CEU?JO_ zFKDpM`GZE=Tp&o>=7PcEwz*I+)HeGEBW!a(&}^FngB5MFAsB6&gM!s;b8xV_Z7v+N z*k)s}o^37?Y-F2@23y!>I@r-R7YlZ_&BcRVZF5NQFWYPi_OZ<+g8giB$>1Q{92y*E zn@a^p*yga{DBBz!9AleH2gljwh~Naf=6s~ z_23EHTqAhaHrEWEx6QSJ7j1KF@TzUL1aI2r+QGZFxlZt*ZH@~*v(0sbZ)|hD;0N1W zKlsTu#|OXI=7iu^+ngBuZkrnff7s@R!C$tyQINVf7xo(mv)Se*L1)|CH0WxZn*}{= zbMv5=ZEg|tvCS=md2Dm5U_RU2I#|dyw+R|-bK9WNHn$5Fv(4>;C2VttV3=+07%XF( zI|a+x=FY)Nwz*5Nnr-eHtYw?K1>7V z&4YupZ1a%dT-$7IO{G%7g=!uu=4EOgCgv4tP7?DfH4hi_IyH|F^CmTq6!TU!j}kMZ z=43JNRP$&t?^g2|G4E6JSTP?|^EfddQS*2)A6N6gVm__r31U94=KsWeS9 zMb*4a%pqz{5p$@Tmy0<<%`3!gR`W_RS5)&VF;`aeYB9&Cd5xHBs(G!LYpZ#knCq%} zy_gf!yg|$j)Vxv5P1L+e%q`WtS#k@?-r^LKm&8Nk@O3i1) zyhhDu#k@|<=fu28&F96uRm~T~%&7UIn0KoAl9+d^`LdYzsribS532d9m=CM@nwXEO z`MQ`-sQHGNPpSE)m`|(umYC0~`L>wPsrinWFR1yhm@lgNo|rGG`M#L1sriAJZ>ssB znD40hk(lqP`LUQEsQHPQAF27Nn4hTmnV6re`MH>1sriMN->Lbfm_Mocm6*S&`L&pT zsrikV_4b#JTE7*ulbYX&*+tFo#q6f$4`TLI^G7lJs`-A|I@%W}TR;sM$fx)zz#QvqjC0 zVy>s=Y+_DSvy+$`so7b~&DES;%&pbzBIXWib`^7HHM@zqtD4=#{D+!7#N0#8ImFyc z&7NZJtLB_y9-w9~FE#hk2WKQWJ1a~?5|Q*&N1 zPf&9{F;7x+elbr~a{)2WP;)^s&r)+CG0#!6znJH#IY7({)Ep@0#cDQ)d6}An#Joby z!D3#e=E7oLqh_O+*QvRPm^Y}osF*jYnHKX_H5U`}b~P6lbE=v{#Joq%CNUpSa|tmY zQFBQ#pHOqCm`|&@l$g(}IZVt~)EqA6n`$mCCVuc-E)BGf5c5-gcNsCiP;*%^@k6iJ zc%+#49Z;B~#Kg};!fX~3zxM}oIWh6WZ7`P?Gi5Jov<6~!RC5I}yQsOMm_5{7Nz7hq zjux}8nk$PrubQif*fY!fKPQ_d2KpUUJjR+!{nt^UJf=dE#rEb4UaRe z#!W7-OHG}8*q~JFw{xXZ8R=$1S$;60Wtf4-HXd(~jC7hjX-dN|c^TXIUt`KJavx6n zU(T!_CU?iij!!k8XOL9-T)d(^K9!LjN%x@__P(rPi1c3W0t1atrLUCju)opS-_$!6 z9j}sC!}CP*7c_=XK6I|Sp1P0hC*w{k`K}yvTDL6of^SgF$R5mi@go^>EZY{%a_trz ztNDC`q$YGqUoC$Pv(wGr#?_}-1y}23t{BSR%)P-MyBAP4*p!BrA!dg;)gWx{*h9?7 zvOGItd}A9=mR&3R5e0(|dl#~blDThG$OuDo$c%W*{2egz8q>(`I3qhTSkbZ5*hU9? zt@M~lH=JSiF~hPqo*=ywEweBbnPr@i`8v~Z$&77O=If=0k@*z!H_?M_JX;tpW2(;7 z!+H-*wXR{JJ|nfnl#7YxUq(h?M99_`klke76g|&0e?94WR;gXj zsGjGTo!Sv+guEGTHw(;>kz)!nzm&pMf4s^|-6|`mQo|6EvIo-`d9(SOY7~*M!7x#2 zY#OLW-7T`s_~IFALZ=C{WjAV+nQVD;1f9z20!&}B(+&aV3u)E|sHW2F7+f#AmF8># z;#!)W0=Pt)odX=VC7qphIyPsg)BlrR6Y8;Ez&u&*dLfv{tQO8OJ28LG!oYI2i39oN z*)dI1%^{lZke7_S+-hF1VldmCYdT~EHS!9{p8ZGOW31`4xm$oVVAJC~V>C{d_%~fr ztq({{%N}zvfA63c*-z_5T~n$4Bkz^2`TL(EhnXFnPY;70=G_bAFa@8N%JH0NCfEE! zn#Xv?njRMxAL>3i{CE-OBH7)9>9SU6W*@i6qo3Q?#b$GJ&+vZfpT=IyJ}%+=$o}Sd z!9LRHYC2tNI?0jhbD0V;4Q{BU;PWg{<{A+`zsl^w?CDDL2V)f5_z(Wy(waJ;@d5TuE@EVpR~uw6 z+hH#!m;;-=yxbsfyo@)Xa`uS1POWkpip?L&?)n96{z5}Wcu$^mi#o7bjO<>h4aViQA7^9sXU-k%oc%bjCP2#+ZF zKVxOhho$Se#>~iGb0c1$s|e7u8y231%Ohr^jBJ#9-z467vIq0lqvj9P%7x5Xf~W1f zj}>&BW5CGsa~&Vgb*!7NqkZ=Y=_rGhl9<1RIpmY(y$Kyn<0;cfUy$41(ER+>C%Qg=C``HHvEdkLG?l{%xZ$tgq6fF^lH?=^#mHK{eJJ5uXy9KP{-Ljya_ zo)z7O@!cY?xwlr{yKaQ>>)15j%Eq=hIU-kI77~^7CCa#4-n~ZGso{G6TrLGIr3tQ95(5j+>sCKwTB$}J#%EU zbbw@ONP%Q}U*P&Qyll4mQ20p%n$m`l=xD}p!=Rx@j{be1p6JQ&Tf4y<14cd~s+yi3 znLmx!86zX1Ea#3QLA|`xi6GNX!O^kHbenYu*=+VM-KX2GE@Zno3%1Lh*G@aESq8{q z=jqZt8$XW<>$K(mc{J|2lj%5xaWCW)#=UTiMchp$WhKjUPlLNr{99ptgBb`ezvR~M zH_KWl#DUpNHHjtD-m?uEDM2PRZ~`TsGx;L(oo0sF>gtBZf#$5sOqNqH`dauk1+i$1oW;dDtuCiLjjj`l;?(H@th89G18 z22xNbPr3l1-*MRC4Fkuf?fXCF?;tm~piG*+Kb!YV7J#@he>Z01{<;#&h^DrDLKIY{ zKV&Qa`Y#ry|DX8-%Gdu1)&DQqq*xO(#J}@97pRfy05z~1vuOuoy49$ct^BL8c$gX; z&G9v=^3`}!)tF5-p=xx>?_8ipXY-zk4eZ9K(Z!flPy4!ab$){PM`=aJOqdN#2-4_#5PTd!mt^DiW6sG%-`~l_b{(|b>B%4s(m&os2 zpvIEsJ);J8W7Js6m~J(O$yWZ=7!sz&@caSgtMQ_$v9xSL)fkcAxj>C&%zH)+?8c}u z(wJ^FMim|^g$0r6-)!C~3Q~hFCx^jJK}7S6T<}@h?85A6wE2TmEwRlx?`vjxMU|=PP>+&_l!o`^Q!^o{Oiv}hEAFE$0Ft?Ve6uD znzO3x@y!|CV+V8Il)GDKwOY;W(Cl~h>^R;sdxmn^(};JCnM%JcuZ`Ka%xP#(oQC49 zjDWJF7Di?@ikN5^`HpmeJZqTU+Kn1dmldbkI(Nl#`r-E<`JVJ@M&C5rhSr)g+z+r) zmHQ&~ea!AePm#m!SB0Bhgfmlk>!K|q-^HkFgD)FOvZI%3hG7Y{sqQ4Q$s{j=RM zg0=ES0A&V`{6O~I_-<)dvTa>G<%a&vP&JLV8R%FU=%KnKpWO_!abqzjPkPYYNPbF| z=n`J$`nvLjr|RYUJ60%pddjCNrK6PyS1P7|UxKN{9JKj$8I3X4HpYb6(h$y=>xkJg z#}ZDNP;cP%3|w`d>kAjj+bq`^$=i+1E)4yR%pbT_Y?HU2n!%50`q;cSeP~{6-fm*v zZT#E-;>Fx8c+-2+>`pez{@FbHXN&BgZOos-1eg6zOYr5sH6{+et=TsHqp^h2c4GXL zGqxAw=bW*F7{BC<9mV)HXY3@#Z#iRUF@Db(yNK~e&e&CqKXb-zV*Hgeb~i@jy*Hcq zG69up{YXw(MF4wQWP-UYa`d7mhTdDGW#r$vPJ2ivt4dw=Jh?gbkQqkWZnCG@1e)av z{AbcNjcv?O|83rF{wBA#y^N8rliuc?y~XH|GxiaqK4L4q(nLCL9T~pO|nm%z4B_0KnYT-02CR7|hMZgk~^L7ZXaul-oi9q7UXJVj{|5 zUMeOc5ayL)BJ5y3EG8lf=F4ItrsVpv3_EQHeYi0izczzzd{jJuvfoY0cUYL&tMW&f zjv47_y2wGyRr$_2k&m?d6nqYJNZa?0lJ}xU^z6AEPL@tjBSPdxa*tB{#-?qrW2Dy? zGBh@;PoMNU0hFB8kCi=sIiq_dv-9K6D=nFFq|2Rt|00cXZF zIH1w{JQ;R~YtA?CVQrN4)r_o-rkGurqg-bGAjQNs#bYir+%ZkP%xhCm^J3RVmuI)W zBKzmc?4PT$f37iq8vB}!3yZ$&fUPZT(Z5zY7F6%BJ|h<}I}^g!NvDG99oA`V+V;9Z zdi4{Ita{6Er!CpE7L}~tH_9I8p3yy$>V31>p>e=GW|w)@dwyf4((}q|?k%m}cq=2@ zOZ65i)2jD;(gA+GMR*oeUl9V;H`iH5oL_wx)Lq;vyI4_AQ+i9a6@Qz8ZZK1gVTvfkH1FLdX2)juGYu!9h~6!*oaC?FXNv5`m!es z?b+Nh%DZPjV}~^}cIxD*g>`rGw-ltbq#b*KIX?*}C}>0dMlH8<&@Q5pi^CjCnS*QeoD6F9F3 zH3>&MV>oZpj~6XX&sR;)#wCoAk+`-u>BH_g&)#La&Dag>?zl|WJVExKwnurL9))$6 z=qNY}Ba=N!8b>jscvJSjq&Z~cj^=Tx+)b)}Qffm)k%gq*z%nF7qIg+a^xnayF z!?5`W9y%yv-D1BDOpb1B^KD?VB7ZlZP<}Nr@4aW-08uuWh?(4TqMkc-{cQy+7;OW zBR5oMek+?$XZ|SU3vLGF1*v_0cX4x(r~k-}WQS3`p55B0_>(yVRzmq=r?D^d?$1J? z!a?yzIfL3*Rr*W1EoIEcW~?2}CHdAm6HtX~FHE#pN9HM|>&R)J0WzceTXs1t+Ai^p zN(BLH3eSUs@;+8%c9}BI6E?oA7m5~?DkeuT>)s*e0kqUa^OBKKOb3MJrqr}Lv&RV? z(-6X#^~MZKkdCrxeHxKvHZ@nOrdx8E$0Ro~N0#}oi+Kw|P3Lv{Za3+e&&fHjZkpR~ zchj?RX=6+`VU~FKEr0qAdw@(H49njxYyy=B&GNS^nnCrswcNvRn+fZ*<=(3-?gg`T z823~Gry}mtIF;s}d-%Iya7S_%x*iW`X6_igX=B8LYA{XN3QY!`Vubju3 zf72&KV`EqqoW~qrqc*<^ZZ0ms;&xuyB)Z*@e?di^*30 zofP^|+f2N%RIG2{s9Y|u%vm<%wagR*>tFw z^=U|I%wcjgr=Y`SEB}IqK3BQ4IX)G1YZY{aY(fQHCckrmILn&%j2hUDQDc-bXDC9q zQ69~*3#XvV$yWXa4SiH?d2@U!=(akLKsKR*t{~(qTt-&RCsg31mCSo4fbr@dqDC!3>ooHzH*8uCu1fEDq->H;s31}{HSd{70W}jEn~7PUhNF$Sg|KnDc}v-98RF)x z>>EXH-rByCk$xrIyp7$k$j#fzJC$;Cjs8U1h6fi4S(OZ&)9EZ)@#8p=mF9*;8Kjke7eT%Wm?ri+Qm(w+=Af8vkPe+!4#2G&jgv zSi0Nm=CT*LxNR;5UC=!vd$RAy4&~N@d1p#PMh=v_VSIH%Mvh~)GoL5B1)nD~7qs>B zWCxq$X5_d9m(`(G!51owmdEm%_cI&Ihz~J6p^zHcGBG{Bzu{ro$SfJBRia?og8SI zc5<9B?T#|X&B$>hYj?ESSVlbA^n`XBf>>o@U<4PnJ^!Puq9TFz+^=W}wF7%!}QH z-l6Y+kDXrJ@bLhSO#clF8R>6JjgV8lab5nb90B{)2q0jHoo#TamIY=+we!p_ z%%09Qf1sM!Mzs#+b5~=U{?9OJI!9j4l9w~gi&gD>vt8o_1`uJUJ$rkhfitqPRk8ob z3ymd*xG29z?zz;oee)7|vtWrJp3B9qeD*6NY~+()CZo;Azl4^J*W3Xy(+SCG>X|EP z=2vTkr|FfuPj#7a6iD97)xYzNDI}+u_n>GNm=Q&V&l^jQ^hSQim2Jm24ch!{Zj-lU`xkP?+xgqCVz+-MfBSc3`xkTDzn8!L zs&@PL^SA#%wtp$N{fGJ6uV%OZD1ZBpW&4+N+kcY3{aCyGr}^7|CfmP~+y3+X?bor} zf04iam$Lnu58*&%>9(yR|K zZfSN2FeGVq55QKQ*q6hk?LoekgA_!o_}oUT1jO{w`km>4ogV#1 zeQ2!dFmuV~1HsaG#~l2({C(MyfKAMszssABsZ4lItIk5$R_7cQQ~{wsP1o#HCL@?O zmHi>?1s7P$25Iuj??tHynHGzADb7e zb&qVnIn1AoyqVLs|KO3|8cWFaG;fLAc1HVJ@U(rmmwC7G8v`|dWM1qpO4QTd(xD(i zrN50(AvaA)si$-02-x*42pGJN!J%3fm=V7A%vsD4F=E1WCPYC*#heqEv%;8j&N=6ta}MA8zFj@rJ3D)O zu6}=?$60>eUDegq)zv+-d%L)J6>WHJ5elTdMtScw8dvVMA!dO0nhbzpi=kXza|QKy zZ7HaLrX}zquaV)kwdA!<55rd-dFjB*UogyjZE3WNS!(XWv1vvSbuELc&|RHb9{Jh= zYBee0v56g(7AAZ23)8yL!esv?$5@V&cJ$f|z4C=CsK*z}K?O7|ix>HV3}0+0U-W`e z`5wG<@lcu>T5Q zNIQC633}xVS5S{H)`1FW8ip77f(&15C13PM=lOoT^yOt1T)Z#Vb#lY;60X}wHWa(Te&CQI9@3@UMxDf?X zYmoBLC--tlCHJz6jm<2-24xn?H$l04?F#Dg^$t)0P21r`z9z%hJIU8MSdt&a%RpWR z;NpF~qm$bSFEK04*YgZ2ECiy;olzC~azU0yzIIpC<{}j3nsD(d+VI+L6i9iE^4@DS zuH0+8n*rWyG605+M7g}?3hMFN7^r}zgYY7+k>RyH<+a6ONqz_~i}12AF5YX0IJrad z60_30Hus>y(jcll3{|1mmSlP4YmY!}ZYdPy2IJyYwBfZ@3Z%S7dG9qESMIeV%>eH; z834nMLb<%=3hMFNSg3%eWAGxck>Rygd94Ub@Ru+Z(Yk2V*87%j=9NlzFv)0Jp_ zJzJ-~)0o1H8T=7aTplx==^JS=!zQ@-Qi!1LCe$erxPp2T!8E9Vrd#l$5F#THyrx93 z4Z6*5&C8a&Y>tah1k=$jw>=8vZTJM=u?;=3Q+GRScSLRN3_#5sJ^oKJz#SCdDO)_1 z0kXvJr1;L+;>qVG^eLJ+OZ*;+r!oNFHV9Af^h_xO&_zB2aMU)Qm<~&40Q$@_z;5^_ zoqsPnRLEJL-;U*xuf6YInL{_U)12MSoclA)@wE@qoE^}V7MBvzLnw|pW$0|^u6R{6 zJ&e+5r0IPmTk=s9x9nnV9;3h>29JjVrG)fEDDWf&Mw!4LxDX_;Mq{1 zl#rea1)c{WA$bcq&>RQIgrq`ET~VXtKO2g&U+yW&GXAr%s6LsHs4(*CUZlEILZEk< zpOg{GV~A_)Wr)NKqaY(FWKj1C>XZ>&K|LAa4XA*o*YKh_BqJjnuZ*xiy3Oy$%Rap9 zg^SM!Z#ucR@RB7hv}9LsTjz|t`&P5-S5d$nbS zzg6+ah7Zv^W^+d1;dqtxAE7il3dAve3}`vb;1kvyZSX1K7=zCU#~OT27;Eqa;W&dY z3F8dDA{=kqr4Dp{KfnYocg%Z%@w;ZW9 zNAPM@$)BdHDrS4@qxZlUYL-y`W3Cx8$$X$TrP~#hQJl#Hw5cj z_t~jAy1nsj zZkH@rR@4b!$97?lAxF(TAUO#&l)f^ow|$)%!mP=41IzxbbOjB?pD~pWWmqJ`An_L@ z@Mq`pCh%`!rxwjsq>0d&MPv>PaFQ?$*v+_)6mpcaq98u}x485JYKCC?t zwHfEM;3D_?LX(+5a)Z~5X<{F6~J7di|h_H33%zIJZZB2>;r zp&GfId6C*&z^hdyIa5_J+rul~DHLsJ99X!J5_11M|7MtqI{BI3=h&XXUdE0w*rv?E z`q}}gMSjt^BH60^G7!ZvJr}G_c?k;VqX<{0E2w96E&vtKG(TSC8Zumdj#lT@=r(^P zFPHN&1sA_M7eu?K0<{4XCZXI;q+Gm>dcQQ~btkaXtUgl*;v4;)_5$ zra1H}Zkn2>fy&By53({^$zZYee#PEOfkuZOi7Asuiie#%+coD@hJr}HSc?k-a zqX<{HE2w9MuLKp)v;tn_8ZumdsaE(s=r(^BFL&^A8!mo@uYq>C`%%!=8g>seDU0b~ zSR`wBO^QEIL)`7KS>kI!99FMQEe}Hrr?`}6)ZBl?mjVeXGpsS*P(i@qHw{$dUB9?D}`;yY6Or5fVybeSc-6UAT7 z7Ehfnv&46%_$%4s$=G{WHGUV0znU$sZ*8Eb`&AX+jpE~``dfSbMjj`u^xR_T>p)HN z?r0mm3*yv|B)n&^2jP8#QG^c+_9T30uovMYgS`nK8|*{)#9&{-rw02GJ~J3i_}pNB z!WRYy5WX}xknokkL4>aj4kmnKFoy80!6Ah23=SoHZ*Uml2ZO^2KN=iC_{pG^@Uy{@ zgkKDfBK&G_G~qXcV+g++9837aU@YNJgX0K)8H^+RZE!rH1An0nQ*r_zW*lREaMrsu zHFwmHw*_V0n+gpqi&O)l@epET|F+I^)Eub|YA2w!j`{zqgW7*Cu+`x6Nrij;fX}Wif|%Pu_ruBdv z2v;B~mV_%36`R79h>Ahs%0$Jda229rS2z!!WGQxpO+>|rZ~#&9Bb=A0*b)vTDprN_ z5fzidK}5x?aDJj6_50RC)&5 zMl+b&GYOpy&LYfca5kZf!8wGk2ImsG8JtJxZg4)KhrtDeo(2~ZdKp|qn91N`LT`gh z2z?ALCCqGa8DSQKDTG-KrV{!ZTuzwH;0i)NgDVNM8(c-`Z*VnX4ufk5a~fPrn9JZg z!rTVe6Xr3vfzV`dBVmBSO@w(3ZYB&gxP>sE!L5Wr2Gam;Pk;MB_s~1XzkK5^kC<8b zsG0H0qqxM}cu~NhXi#ME9u4vH;sVLhcsf<3PI0EEN?gZ~Xn6ygnbdEiS@WA&w-a&( zcMujZxRbD;!Ci#N;BLY~2KNvK8{A7+*x)`w-r#=1A_fl-7BzT~FvQ>?!eRyw6Bajk zgs_Ccql6_59s|g;q3`TB<1ySP*mfyv`!w7BBiB6xiNtl!05FSI6yM)IQwK9ZbiCRy>aYQ*CkF|&!6`T3y1WxJfC?36~)%l!XPNGM%uQsQf4#O4K3{E=yF76l$MUz7c9; zRqzV6u`1^XwXrHw3AK|d?1kD%m92!caf4Hq70yo7A`|u}D$@$*ASyo#=OSu(3g;#& zM+>z_E8hvVDQj5?wJ9s-3AHIJQwp^UYe5RN3oBc47iQ2$KIESV)Yy{V!Gh41^a2H! zww3oHVHty$2nBx81g8-(Qy-Xtt<@D^bOgSQDQ8oWbT z$>3eW$_DQdRxx;=u&Tiafb{7g_3K`7_0s`wM%#HhSj{^85FK(t%1;Nr_9N7`ybY~P z>L1h4)lKe`u;x<$a+YtX3FH(pXGuU)egZR#{4UfDwKEYwL_ z^C?u`(Oe6acN7OgWe3fJP$y~mTc~8AxezK@Xr6>h7MgdVPSToRp>l`jUZ~umxL{1v zDUo-{=YW`pv*5{wZd%ar3wn!X17m!4gH=hS`gUVd;dKeFw{XxrA~4tLAXek=}?6U9#y-=v1Pd)$#F z{xiilts(B7)n$qQLh;SA#nmYtP+k02if^7Ro;>bwk9x9t|Bd2XWQ!+{JNoN!N0#{S z6yLIjxcjP_Eb%`mzEutJzEykwlj2)LTrTnt6gzZAY3ja#krh0G*$${^Y(U#+XAonw zBViYVM#8QJod~-b%s|-Ppfh2l!Hk4G47w0T8FU4tlV|#)1Y8WITPv;#e{03i_Q^9C z2|o_PMXP0Ew^n;vhuzSjykc)0tjF@m*LFv3%eL0E2MyiJpl4Xq3xMS58_KbC9h0X7 z*hA}OJn?9t!YM>KK{%BtKMF4=%9Fx7iE^LtE}~p3#24#zC~9_u_YgHdOky-H@}~6$ z)bC%e{dW3yZ}U?hbV#H8=H&eAYiFf7ZHM3vP^1v-%W>>uYG)(tYtWCdpTX>e(FXkq z`y0$bIKW^|!hr^J5e_n#8&JQC{y_*HY#q*n4l7;cYnxEpvb{AOKtsnE%p2AW1Rw-` zLpheNV+cw>k#R2fZ@EBt9#QTQo==n?g%=RzN#R{YIZ1doQ4SQ|L)7dD?;}{7?LQi1}%LbV#GhL(tbQKyx-gQ#RonnlI`DQ0p%W zHR7Wb)EN27!K~Z}Eo1Hmm>gNw6f?OSH8joX3U!rPdIuICXX5j!g`vR<7Y<{eG4=7o zP9ikPvlE~1F(!Oou;p;JjC_kl0wv8ylqnHG$)ceWe2^7NBGpAwg%*oZiSN5rN-X?o z^h{07M}}pwWsjzUnntRGmc`kRKfu^K%8{C&a!GcvdIFdJ2y*pp zf@cuu({@>7n>dDD!j7fUp{Ap3oA9;E(3}m?lub&X`7N-xGKNy0&<65{$gaWHl;CK^Q4N&1hcy@J^YuN+!@d0*u zh%<$(3khr%N23uw{L8CiZa5Wflqed8_kA_AjD#_MZkj_;biYCbo!y5#n;_P9p zpD_$-uRe?oG>k~YfIS;gK`JSvZ@jA~1>PF?87TKy#o2K@J%$c9Mu&1xSyJ$|o1!*m zUJLFQb^3wiX0)95i>{!a`^BxG0-CnKizbhZ`^CF;zjz9|%}?TGA}OJ5&60h%5M$Ou7q-V~z>F8hSonHEFw|G`ax9 zsoX7Fa(5KBoM&xDQs6>^Jwky}mLC-g>`8%(Okl52pp@nJ4h8n1z{Mu8Zzxd8^81AX zqX9@J-a-yE#{n{dt58d%s8RBt4Mo{6_Y`Fr|JhhnpG@FX7mmu=_Bri}U>{ zvlgUj%@FF2L7mdHE2t+;kAn(m8jBaLcrw!TBTCcPqTBq{yj;o4<+%7XeLULbZa@KD zSW465S$rdk+e*wXIZ>sBMv|B(Q2eGE;_d-pmiUPjzqy9E%j;R<6DfX6ws?|RXH!IF ziJwIATeHQJP04*+DocD4#iwP9C%wDdx=_5AVp!iz(WR?D7oJRA)3bFYrnrZRp)N0e z3dQ4W@x&DOI4?{5REpnLL)<+~%o3kW@!KIDGm!i$b$56O)zevh2dinJuWpLjp;3pX z9$NgVZ$dq@L<9wu1+YcLB8?&PLnlVGvizIfO?H&Luo*a30|?gYyZG8(ctm z!r($c*{He~o@7oCN5O)=T-& zLq-ZOBg!)26r!vaUI(*^8o2O!qDCvcfhbRKM`ZVr@BA`A4e#Cq)8ySL6nxr7G?nm- z!R3T!4Xyx`&u`&5R+UG9D}y;#qIrc!C4kDSsf*#m2NKUq3lok-4ju};5SIDLN*6Oc zA=2bDM3RB>YqEM)C#bxZJu|&Pu<)XKVXjJgc4cUIU6vLJpz?ZZvFd!fs+dV%c^l>YOuj*hxO^tx49k2EO$9ZLREgo-p4Ek#pz;oOVN=%pmeiF`naa@c z&MYmy@-9>+PPrQpy=~*WhwzTUy@YoS?gRLq3-77tvcb7BEu#C`v^*l-H!TmKs=|N1 z@ zmdstM*wi!?q&1Qrbof}7HEM#&$3tsAR?j|$9F@CSWe|HJOQ)}Vk~+PXPo&edlq~@?jml)co&iLkQ73AiC46r19N`Ot=K${K~@eWar8>ksq;X`9%I^T0TZq#YFnbPf(dy|0w_y zsh%*hQTr0~1CFYBTC50!cMx)v3#RB@!H(D`|mF=~R!FMA)^s5OfzY6vLU1q$a^4RF`Xy9@0+@^w>MyiC)ud_N-6I6bK%EY_h0-^@$M9p_$ z&G!JDJjrQS5ne@9st{gFRDKX%M^x?* z-b7S53U4JU28GjzicjHmqC#AFJ5g~hyo0Ei7wSN%vz|}~%4d@y=s>B%pK5XY*`cVT zgD@uQydcC+&~+&4EWy(!T^4zV{Rl`>aYuSsYvLysUyj~*#@DZ2FM=;V<$w4a`s;PK zkbJen&unXZU!l<^=@%60?o0-Bz)ytg7jRlSu|D#xek*T3mcixS*G)9Uk)b#+? z?@&vg?Qv*Nb4*WkNE^!?>T7$^oVFwD0XR;PH51xKy-aOy!b}Ez2)zwvCiF3wg)pl@06 zbQ9xC0tyOcTRB3gY^%`=ryz+GGXPe6jn;cRm*&$y~G1T20nG zD6TQF5BZ60qP~7M&;f+m4dx~EHyB8m!(cwboCbpka~aG}nA;#nn8#oNLX*LQgaHN- zVP1oU2m=iU6Xr8mm@vp752!zY{y}P*-#T0b9db6xSCX$?6tyi6TIdX+p*fRVEUZ}^ zfYjt0YMM9^3>^t*z7;x}5urjy(;!snXo`f|s5LLbYZzGam{9w+=0>P}Tk|H=zO7jh z-a=V9Sg37WGa=MAu2~Xl8`ne&wT)|bh1$k7^9)%IJMx2Gf<9=B6s)LQ3iv;n$OUXd zmPUuPv3w$ZZ2`5(nRP*mXhAj8%4+W-mv3%-{@%josVDZ+FwdCg_*VBy6FT7+o$WA+ z-+aQ8{7Owjp$W+*q9swuo@LoVjrV)1@66U`dp44V%xgt-Sm`xiyIl40RvFjw8ds!o z!C@~ZYuU!STG0!K#`zJb!z|>V~Ip5}X1@*jtvL;kO z)9QFpbdmA?$&#>bwfy3^=7;dI2rmoc;@>}63+-}CqkuC}djDi?7B7S1wjR#8H$bQo zK}b&}@1Lwg@j|wE^3Jq-4syEk|lQ+5yMtg&IDV9gRc6-#ulnNGz zT0n9K)MHnYJK;sqM8*O+2?y`h@~ffS{3^Vx#LEh}_yw{n+U3?nft-)e zDY!2v-JQj2p}4ID;@)7SO7m2*Kt@u0SPgOa4q=w~9u!}@hPYdvS>mH8zD^Bs_qJS? z_+Ai?DUMOmD|kY;E{N{ko0?~wR{jk(^lmAL=w=^8f%ceAF9oQD$QsledF}gBdn#hn zA7`xI8E4B!YRj zQ#;LB-^@8M(;Q!WP=-0_{kQsLS$HYE)R?Rd%$$QW&GEHkP#bfKgY=^5#55m*I;9s^ zP)~X}0xF>CFuW+ekda>A*XI{DN4NP+dD)nk4RP`5r4{XRTcMyly&T2jtx?=odT|S! zDsAGD^l~)CN7N8^3p`8w7>aL`Ev`dGdD z%1)xPolM!JD#`{_S9Wr!>=Y{7*_54HMcKU7l}!$noknH5n6lHWC>vN^*%_g-GpTG> zQ+8GrW%E^6c6O-j94gz*l$~2e*`Vsm&I^^DPi4ECvJ0vxo4>lU3qxfWQQ1gSc5xMD z2US;gNvP~nD%-=9T~{cq< z*OX1GqU?z3%BF|PVk+Cul-&jh&lX!+`Rypj10A2XlrNbPd7B_v3bmfX2P;aALVXLf zlACZcYn7ga`ch^k7~$!xRf-VmJDRn~g=eu=%T%bZY}P^(o{OOtwN!-X5f$vh^N9*q z;RQqmobW=TLPmHIQIjsbn5bzJUP6@Pd8dLs$2X9lV*vxq*(;Q#>Y=$}fKL7TG2oIF)oUAcs&U2aO z_}UjxTP>PjM4gWGF1+hG(!UB72$+}gqMSj-k)C(AtL2Y`h4~|RIgFP>aPdd_*U&C^ z3<@%qZ1V7HX3Yv^%_Yg%{dI~Tn=PKCxIR_I-=O%|Y;pa<6obEWRq;0|eq6SA@<$;q z-((s8HpRz5oV}DDC%%tjxbg$mR{o)1GAj4|rJ-J})B(*WKx3Pd?pEj@NG4zW=r)VA zWbXlmp-F~fo)^XIpiHF z;=ZB3DsOqV(CjhfO3zF9K<`^NFW)u1QQ8kGCBDm$VC*m^`Q|~T#P=Bz443K>KR^PH zJx@fV4v`zFd8#mxWq#bvB8~e;c2YU+&8v+2rwp5{iz=h|IYXlDasL8|*aljdM7xtP z_n(zkDW>69G{t~V(tzC%&6?(u!vPmW8t`wlr*goXRT=Q_8RoY=34hRh8)4zpO!HL= z^Z#__pCa>1CjR};OzhC5G8Wr5v4Ijkb(l|KPDd2uyx`1nK2<28suQYWN(84FtxMF+ zKrz0h;tJ}?|6QR1nr6g{CW(yv-&^_rY;>DHlb6$ZnT(6i|J~3ocOD8dQeBe&yJ~7F z%aw!wlluR2gNVQ7EkiOOSDl{hACH6O3axdLH}~zm?JAC=E{(uORG!F4GE--%g_ja@y4t7R$+?B#@;N_*ymv< z8DsBPee6vccC|hB0T~i)k9}T9#5UN%<+MEs2cIWZiYXq5rWo{84cZOUtZBX?9CSgX zLC;5fG6p?c^+6BH7(&~VF+Yc3qbyvNIRuqr2st-|D>a0YnG3Sdi&2=70g{7@dSG3s(2b!W2m@1naX(Smz;uOzZ~h zW=#Q${uiaiT=qdGmW8MrLNR7yS5QwTUJ@#xX>q(L49LjDU+CfbP3Sg%125O{at$s% z6EB5!xm!_Co{g4a@iY`?Oiyx8?J_J?a@pelBtaJ_KHan?KLOL?OEZ+F<~&rYIqj-X zXJUjy+fb4uZ}+ZZT1n|EI+txjNisZlU`{LPkyuh}LrJm=&7mZlR?to6BY+uC7%#wG}se?+wf0z zxFR|Xm)0#Tk5n6ZqgMJ~8FjlEwQ{CWzIIiblUlrtNWa6BkDNJWbx6b1-RAG%{8I>&X4Si{bO)^C>q!ke=RcW#!HflpjGBCF` z(@IKfa}z2_Eh{=TwXEL2gWRUVqp0B2Y)YZjvP!>q&WS25E6$i-R-6mJtb(qRWyLA9 zW%U^T$qqL|hvBk%faQ^DBX86e|0|;&H>0-9G|Ja*O>b_Wh{6MjEN!87JEZe0gW?i8N!x(#V_a7Q-2h4#PC!%<;AR z|0{DCJnb~+Ei>nUOmlqgf&a=J24g$TdE3l6DAOEYd+@(9hr!)WbKWs?#$=k~YY)vZ zC!H*-$Bsq2HrN`m^RAh5Sf)9?_6XF*jJP0KD!LGLt*BG7bOrS!%VVGdnvTMYk|i0* zvcDc5eS&WDAMx@5FYn>vljX5!m-`$A<;n6m7Jq@_jAWS{$X&jnN}IUkrez$(zswd- zonErUkEi%o+2Tp6c3*UrB|e_wsjQKHmya$fr6~HwrzrO81CgF8r6`v*=q$?`-{PP2 z`UG?sW{uBS9{JjdsEz4MXl?$ERdP-8Q(}EkJ}goNbe+W3bR9~iv#IbsWfBddk_H^R zTJ?e9NEOg9iNjBwD@>v8waW*^bH!x#$#Dg-sWG7LG}I|JT|qsuc@|Va(;0YCY?2Y1 z0~MRUq1*f~y!^z=54iZ)JR9wDf1;o~HqT}8UntIq%_KV96HltNxlCg7Jc|FFEuMt7 z+ljNp&!>2Y$1;0Q-Fat;Ur6y9u}PPdVw1k{vB^=}cw%}g9h-EP#bzT+q}MM(hhc2~ zfhPFVO{={GwK1Imt%Xijcqwfx51?Gx51(-O5J-Obg!g57+(Vw&~z1E6vkwP@nD5<4-7Hijh8OG zbjHPp@wI4I@k>N(Uz%eI`Z=b&pJS>i&9NPkdZCbpTnD`xk}IfZNH;+RG~J+);2&fR zX-N&KFZ#*P!b=}sX2Qh}>1MRc&5nZdm3aq?`=dBxWhP6@J;tF*8)dRG@1*z~HN;)o z&l10j;&avz@2(v^OZ;w%&jsz0veEix)<5#$+cuk-M#;N;ru#m&E%s6whai>x;rllO2k)v}5w6XU{=NOdD(p zaBsE<$c^uL_E7nxzNi4=0L#7qLK_Ap>(_mSS=yk6euaZ|_9+SDzJf6{HAp~GJH^+kTl|kU#8XQm?7e&le^SY?8aB9P87lEZ z=z#al((eOs4sC_-PifW#YTg^rHrgE2A=*OMEp^?BSHwq0R&TAM5mwa5qHR>Ptrc}* z(RM1@-il^m(GDuw(TX~=XeSlztm`gTF(WH>Rncx%)P+U6t7xPZb!E{WDjH=)-B6TH zAUmbr5@alw5(tCZClJP|PauJNlJ_nc<(5G9#6Rhd?&wg<-*W%zERTF`57f4-V@-R~ z+`SBX5%xBiiLj4BZ^FI?eF*y*%uE<%#Lt};5SIx5wn8RzjIC$l zE18N~E5fsgS{uT%iCQGWbBJ0}!gGmQHNx|VT0X+_iCTHW3y4}z!V8I7Si*~lTA;#< ziCSsGONd%>!dHn3L*Z*gg`4noq5@9%22o)ue3PgM6uw1N3<}>SDvX8i5EYcdcZmv1 z;d?}_ec}5=t$5)FL@j;cheV|a;YUQ}0^!F*B?aLpL}e1;r$l85;b%mp3;wkTr#bSI z+{6$}y;~Zj0cOed5CY1Q11NZih0?r)Lk$KJ4l|gKaJa!B!Vw1Z6Iu;&gd+_WARJ}D z&*el%8$^U-3>G3BYcQBF)?i^kdd>gir9@{nbmVn_`wV#CiL8WpoOPZ@=all_aN-i8 zuU!PSEyJzpqBMG(!4Sgn28$6+Fj$;0-e3vB1cN0BCmQfqNu!AdOA}5q;185WlMMLt zq|wO+{BhFg6oVGRsRsO=(*MMV9shw3CtK(IRn$r!`da=-YIK@4627m1h(ILgg7P5TWvn7J^WDMk_|BJfoE%RG!gF6DrSWMG2K> z6gEQT8HI;Xc}8(0RGv}12$g3Pe?sLM#ToMqCnNGxu`{4Xp4kW!r986>1#htV-IZ{o z!ES_`40b2nY%r2=i@_d*TMb45{*$O~{0C7z%{t!`ozpetnZeiYh1!-4t?Ax0db+_r zgxFwT!fgio5pFjaO}N8gf5M#x2LS$)QFs0aqrS^JKMRtB za|i%y*}F#p#1P?HmViP|>q6ln)Vfd@2(>O0FG8&g#f4DoLUAV4x==g`wJtOTLahtA zTBvoQIT31I$oE363(cia>q2wJb-{r}eprVCYOIS*FleodBPe)}`Kpz0ufdUo`wWgE z+;4C+;Q@nV2oD+@OL)j&Ea72;;|Px!j3Yd1a6I8LgA)jk8;mDBVK9O4q``@Vrwk?% zo;Em%@QlGE!m|b^6P`0Th48$=se~5{CKFyXIF0a4Xz=4WpFLwYlG_u-xyp^_}1VCK-EXh z%cD{02{+$>yAjP>Ha6LtsOUR`n+e|=+(P)l;8wzq2Ga;X8B8bqY!DNEF}RKJtHJGr z-wf^`{BCe3;SYnm2!9&f4M=Cr^ke>2(Kh=j-I}ODa?(3AjJ=8{q*&o~RWsoIuo?7oJE|8Wc_>D#Hm+CMqWgPa!HR2qzPjnS`eim79d86P1UBXAqTQ zg?iSegelasHswO09kZF|*^?*#PS*Rys$__$35mOcr>JgYynNW|wl#7IV=B3;w)H5$7C!rp4DJKf` zkV{ET_%&Up>?iz&sPrZLk*IVi{E4W1Cj6bKG%Eaqs5~gtpU%a7IW;ghX(BI%|!W;(Q1Ip%SKw(Z+g=I5Y zSvnruzcX3@v}b2j@0idZVOV86`r4mRn}ov89MD`gpkD}c8~jR`$KW?YlfmzV0S12% z<~8_}Fwo#H!h8mQ69yS{=oVPe0Kg9HV^gbz>w!D4R)Uthc3_2zP+P7dPN+RrK`YcA zt2hyAk5zODwW%sVh1x|G<3jDC3M-*@Q3az=+os}KsC`mPLa2RGQ7F_tsdyJ^W7Lun zYA4jH6KW?^pbNDVDr|+?2^En-?SzVBp>{%rs8Bnh0$Zq^P%$giPN>x()J~|t7iuTe z+zPezX?BI$>l6k;ZElJep>{Jxj8NN`LQAOqO5q^X2Bm-yYDZG!Fr70dA|DZrfSBjM z;3E>NTPEwo;Nf2vyMlT?BGCmZ&}C=5D6x|95sBgYh{Rw-Y(C;;0bb_E#eYPitCQ=7 zm)xQ#Z|k!V?$gUuVLMCmk+bd;ACfJe`XE7;cn^rj>>YaP$IeZK#Xucms-CY^$ z{SK99qex9L_MRy%Gd2|#&(NZ>N-ZjemR>0>-I@wZq_s3!S)~>=g_hoQ$Rd!-@MrSj zkiN=>Sq|w#BPfo+>tinArq9_d-F|Rd{f7hsRWT>IbPu*Ly_P#Pb$qB>)5ELnr_i#bvQT0m&+DU>~$YV z%Mzc5_Of@gw@XuDC7KsgWoZm53j@`SLB$wDQ%XzMroze@T2xl4Ma9rEFNd-`?&w^O*Uh4JLq;AJ&lR>8%Gd*tL6!b@&A$}@bPgpUh%s(@>mZjzKe7~(O-OQEtJ zs4U#qW!7Hu4qd!vb+`ySq_}m6guZ@uhbl&gL)hWE*&U{$DyzfA*dfKy zVMSEYzon?6qkU8bs$#mmR#erkDTpdL8Y5l;CM&93K|N8m3{*hVQg~5Rkr7q9E2=ib zc=DU@vJo#E;NqjI;N+U|lG_U9ZB4R^Dyo2M%c80U;xWZbQMEOwEULC(L8M|Bx-2`~ z5=9vurY1S7!y-GRc-ACyxTQ(vxcwvts$zPf)+E=hDVSu98zWvGCTo&iK|PbaGE_j* zig?i^lQGHM-&f1;i1FmN=Ve=7M&RNnc@?zF?ScZP^3oq1tm@RQ#@dmn&6tX0KXV_5 zrRMb9uil1uGL!BDv7tCkDSaSz4Jz5Sh7Ilmv7r+GY0@<*zFXbmYqcSs`XYxU>Cw9gIx(H8|+3n#b9^BsRknn zlMVJDoMteJaJs>sgfk5GBAjWkH{mRUeF$e8>`OSuU_ZjS2BQh*8SGCu-{1hk1qKHa zE;KlZaFM~mgo_Qv5H2w|gm9_Bp@ho}4kJu4IGixm;0VIy2CalE42}fE40=oa_NVv&hBH?C(lL)sMOd{NBa5A9Q<1%LI(*DGh?e`~UK+CUj zxf9$QNzCE)M$$C=lgs}UbXe(TUwbNQ6TeNSq0>$7w6NxM03Ks`2P+pb+wd`#1lU9C zuJ{_wqE?J>H=-7UkUtAl)VdY&XMT!WlEP6$WhvpFL?s~MK13});l4zzEa7OPl7Mi3 zqSm*NKOIw4$`c+)R5laxM@@=a%fiEnTBbt&)<{tqMabU{DJoeAk0mO93i;C@MWsd| zf8e92WFq8Gd=!-@g#5*hqEedhM53~lkiW-KR00?B7deW`&BBw3%Cy2$h)SZu$wZ}I z;b}x=RpA*#L=0znxA-_kwsAMYSw|p0sG===G z?4t6a@Fk-1o{-;1T~vY;^82NWN`%69iAt=(_lQcMLVjgxQHe#^lc>}p>_b!z63$Ij zdJzsJD!~XBASx3HHzz8|2)8CG%?P(6Djx|)5tV9$`x2FGg#6N$qOua7JaQRFei5Gq zNN1w-8%fnO(Qa7%?aV~6Wt6kgA&v5nh+M+=wdc{Cw$C?vL6Ock=W`slnc52g;TD58 zl5V%E3#qf(+eqd4b6CqA6pFm)MJcU#tK&{KQ2!TGZ;e0ttL{464)v6;+=z-KewPj8 z5_DMUI$wJ!YVnSj?29xE%=Kj`Y}wP~rvRe64W<(AF}R#?ufY|B`wXrm+;4Cd;Q@oI z2@e`vLwLyGTEfEy*AX5uxSsH+!3~7R3~nSmZg3Of34@ynPa51pc*@{b!qW!R2+tTy zCp>Eq6P`1;jqtp|?SvN$?jXEqa3|p@JbDiRJEC{6qL=Z>9Z`{~<){S8Tc;BD`wwFyS?WM+mPQJW6=O z;4#9R29FcoGI)aUw!xExcMP5)yle0@;XQ+A2=5y_OZdRxIl_kq&l5f}c!BV-!Ha}X z3|=C9YVb1QGlN$MpBubN_`={dKswQ-|2VOFq8kY4P6oddW-#~zkY4lucq!3YWq+JF0=AYOFISxW zI$P&|qI1fYCq!TS7iwGfwNd{~qh~a^4&4D=3>pYs4LTCK88i~Q8+0P{FqnbR)1Wh< zm%)sLnGCuRdK+{l^fBm0nAxB^;6L$U*&ip?@Zl`hc@K16=|f-J6SavCd(r4wO>U;J zrZ)f?%sX4b&G2OglYo{(XWnlqbcMP{REP?@u~xAx)Gec8R@jTRS_4AeK`PdTbFx+w zD%1_7CQdkjwVGj}?k_cy!ueUN$PnswQxPEKS1uQ|K!m#c)Itz$!CI{tp>9UCGK3>o ztCc3yy{T4|kl$ikRM-f0tE%u2@_Sy3iX)-!Too_E{aLH{6Y54*amGBu$%y<^%mS#9 zXZFWLDbLJG!M--XeF?J}%tq*E(2p>?!R&7oF45<$1=}4n%FsXv;J6(ddCDH;6Ew!Tf|l206m~1`7~! z1`84vFo*~X8Z1PJ3*kBPt-e6I{f8xWkzf`P|XBM%}hoJLHANtzG zP@DL0aT>j-$t@AqED1oK@y=FoGklq6B%tM>JfqMRD$giHg~~IEWufwnVpga;qctE@ zo>8m|m1i`eLgg7voKSg2Gb~h|(M$@JXA~Ji3eLm1h($Lgg97pHO*5amGBu$%y<^ECZ;KXAbmv zra-|VHowh;#SB^qiyI6jEMc%LVM&7`VJU;<0RKr;m;I$;ji_GQI$s{0(>3Lp!Pl;U z+Li+>GptCXmod4O2nBVW@b)MbCESYy;h>wFD#UO8%C zyC!OrQLja#movFxVa?hAtYz;W1rS4oYgqycIjswYhfwQ6VIb7HP`n7WE)*9+tqaAO zQ0qeRB-Fal6bQ90Hh^Rgl@%j4od)UXlS<<>v}?Js?( zVPmIm6V|SS+S(s#pk_>1*#}xSZ9_cup@vYLrj$O^uo;!CS;GeVmahyOHmCSnHN@>3 zwlc)Gp!l$C@ni_@Lk-~&{O1w2r1;v|;>l+s+$Vyv#J7fcOmTRYUcs+G z-H=x(*?|=ssc2&>+L1+@sAy9w+KEM*sc3U6+8IUZG?spb#xO3u0VzOov9r-_D?Qc4#njv@ zH#(%nelK60<&m%52etT$Q`v{c`~9!1+s3RLooSt~-Jj-^e~YD078~=o3d>gqKNKHomXyy{c$h4v=yqJVA!FV1NF6s(`;^B!G5ZVg5(jX z(|+m->e)|^h6-pp5-$ouGWOGn+D~^uxA~oT*@2hsaPj-;F=&_D9R&=a(tdiZQ#Y2i zd!e@WeoD<2x5>wjk849b*^JzW1VeF}Qrb_)QOU>}Hn{yXRN{BE<0-yJ4RN=hW{ICb z@lo00$q?Lrnk7D-;(J1zV`|9oVro+jbtGTUJi*&QB^_g`gQq+Bjc_8XQyU?tIM@jH z0V*s`LfdFx5WdY(*U`Kpa3-;0e-#~IMJKc9KouQiMW?XnU=@wAqEk_nUS{cyknvZ_ zb__(n5i+)XwhL@dHbO?GEwe-LPg*(|9nuj#+wI2k$k(2R+Lpbo>FG50P}Lu%>)}>$ z1}lzGQL7c5$)Y1wbd(jH#iFBCbc_|9jiU5u)9)1hC!;;qIy?s*R*u%!o{QRKwCB;> zu_kwZhN0hBeh#?xQf|KrRpDhs1*mWe zQIRT~O4LjXFDGh#g;x+Y(ZVZ<3V-2MM8&!AYN7&Ocnwj}BfOTVFcDryRJ;hUCu&Iv zZy;*92yY~6-3V_YDk6n96BTX3TZjrfo<8WZ$UE#3K+Kc|f3YogyKy!Pm!c}Qow5bi z5cbmY1vV`5LQ^PIHOzWDEn|xe^kg zLvSQGfn9}VaFWWD2Cw>8BR1FTY*6k~cQy!;)_5E7)tMvqwb!5)M>N@o;atbzP)Tr9 zkc&`vJ)82@+ZEJvRJa)`py@`u$QfiD70%F6;S_Y6pTx^VUMAq;j|#V-UG6j#aOz4& zghB4t*&-%6Dok%fJlSX6Q6UtkDW#)AOeLq+u)!S_LM8sFa2v(X zs3Go-3R&W}Q~b9-;| zd$ygPjejx>?m~y*TAa-C$k*QeUziiqDKIPiYOxyDonzMBlWCo=z4yPcj)U*$O)PtZ zpoWd-nvM5m+URTVM{UfYf&DPSwU5!9@>@j(t~Q18x#E4|6KEbf9-kn+(E53jnyP(*G^MHK zA__%b^r@6qOy|XHpy_;?dQ*$H{nKedqHU$z2)C^Si}w;6$TR4$a`F1wXHkpklzowg z0k=HQ0Z>)2xoFL!?ga{Pb8!XrY%Z@r1vI^c7rBIt&E-OEE?1)4{N=n%;pI|X{O0m1 z+U2f60f$rCTwZhPUT5u1sI9%ZP_r$HWOI3=4e=y1yUisOrzxe)m=&G@YFKxhS@(UWb-wn8|H3*BzN0s>>&zUy*+Fwu`Ge6k^#Kv|f1+_GO%@{y>W2+vKOq%VC$h*we-!g6WwZEel>qYh< zeEgLQ+`hInN3HP@{rs;Wnol%|$@DHM6p z#*|jf=zVOU8SO;9sT|Y(8MQdkQKj4ncT@>-%>6cy8PH*6j`6jfQHvRseUXL%w{+nE zs46(BDEXtVD+PE|aRv1pReC}NGwUG=^3N8)4zy+GT7%thny$>@capuN4|D0)Z*0if(lDk&YfXp`aJTVSoxA!IZvjQ zzP3qLMzRt^nwQq4(k)}3p5f!da?dc`&PR#V8zw<3e(AzaMF?*jEDA`E z=l>;2-?0vdpu@`X_}ax#n~Z018v3ruEfLl%2|zIWfosw^t$de30_>r6L`OVk*Tf08 zA!<^E+Y;pl;dVs1NO;8zK!t>r_i*w1+_Gqw`y2(dzqHR4ox0^% z`xRFHy#sLeYzO!n|6~}fiVisf zzXN>6^2pb&mSIjhbyYWqQ_)UyzA;;mUz)n$Qa6# z8cJ6VWkz0R;H424Ka>$@mobz9Fp+xymwt-wYl^^{QI;ap4c#>HjYrd+=hLr zWIzoY+zuEj@iy$&hInFw+W|xIavMfd$-LP%Bud<^QK-b*Z~(aeCeeEHr#q$!`hanwC>r!_#fj4+ZGYEP$lEcw9TF`nqf)E+BQcG$k(jVojJ`-FC z?VO2)tivPGVdYHt+M`h0GM_a)nuZQGI3~l;_J_z_c zd8Z+hImXs2`KOQayYPCVJkR?9s))RTasO&~%m(e8hrA8%_{`z?+VQB3xsHOvl-3OF zo`5=S5U!w}4Pp{hK+{CLC_c&9ARe90ueV$h-R2kPWe6{e;NmxklhH1>3<~JZ((TEq zEH0opci?UK{fuJ<&fB5&i&<=Y^AE4wBO|Ir{l@q|*%>BNyg6H3Qi@k)GbayTrEoY6+1GKaloX?u&4K4s=JhgUTCmI-F-}852sOTa9R+HDO zA<#&!CYh(@!*A&;syiXS@vbPl^l3TT;uTy%TgvYtVoop}&F4dv=3EMin7$4IUVeoG zE~9n4A9n@y1pF0H0Zmi!BFB>v@XsmWS3|e?Rd`v6mlbgF0e>ahr3R9_=>U9L{OAs? zgJ*SN;5De`B!*TF|zuQLa(Cf_g@IJybx`wRq7e z$r$D98s%{GlV69IVZ5w~iy!3;Xjf~LeYO55YO7^!jgM-|$9E%?h2vWvEojwEDA)L0 zK|SM}1{KhB3tlunGRF6T#MP|r~Af(mH511}m18AJI}L)i}fc8%rTWRFbC%|FwHiDVh*)52ktn@ z(OL%H1^=Ym9z=(9fIm*|!1Bn~KJ>55p&Qz1&aP(8!CNFpPWeo`dug>Lhscp1sdZn*eJdK&F=`=X#clAdMpekiUTNmQAR zq~|C;I$K;fHR?^dBuo4Sir0uFj;Rz$9Gs6Nn(e2KLrq5#M{AL^KmJL#y@(FONZNK0l4_dehck#N1z~P70l5Ud56`hak8}^Csmc4$#K392~DM)feuFt zTJ{0THAYuZ&lo>}3TXNWFB&5mW9$<1a5@(KsGM<;?aq(mR z4()QMpg?vd+rbYkJ{83oi#T}?*F7GfN)8$SCkOH$DL%P|xE{2}S>iuY{IqQGzP z`K{z+mPfw!Z)!Q$ns(@kv-jx+4FDXOJ<4dB#Urx>sI+w%o{?pea8;tr6|PN`jXXh9 zW90QU0@8^v{aF#lMJW+7Kzt&!p(@P=u1o&JixFdq@I3sJ&g+B@EB)YWXUH%om%7KQ zZVp4qVl1v<&iQ6e=S*{a?Tj=hwRRbB?1Xu_yc6cDu8@d1>>w{|s!`Vsby~l!pq};H z3o4+g2VNAHWUSvgw02nQ8N#rg1%I6ZG{5LBaYjlpdS>(bPBvh?MMZ;fZVjrPVK4G<4242!qjs; z8f%LCqiu96MPb$)6dXGhZaQkl#tyB+`nbi^Ivl@es8twfu^aF?A<}Z4$F%QZCA^EM z5p(mQHIcVvaX@Z4GuP&UrGPQh zTWKlY#VReYrD;RkOYufDR@-IJHoDui762Te-_X6ko7w0dYt%yR8S9lliC$%fheD*~ z29sZw%I-BNR#8R|S5dYcgoQD852}8c6sZgYSv#`>wL$GVVF&B7gGa4{;ecA_tm=_( z!J9G3?$HHzb~|T1W*x4VX{fJVAGJ7DddF&dI02k}nXLI`losV8p%%6#MyQ3Y+2HI` zW90R1$kAQ_eHjOe=b3m{>U;z8F%@G&{ikQ*-KgNr3I**y6OW_<`ZVUeV7?hIr4MuOkyJBith#Hm z7Du5v4r*|s{s8SwXx9V*+O%04z_2UJm(9D*yA9T+M*h{`@OWd~PLmYnq~m5m9N z9YSTFnzBQyC`-=zmC6nal^srHpP8~FswhiN)RoFwLuE%&+2^M0s4B{m6LqDsqeErK zP}vuz>{vjUi(jzvu_(vU$wz=fkHN*wQ?e9lU6-4u0z&h=T)2Qq_Q+9e-a|Qt6 z<9n66=n#gF1T@Kt7Y$mdc#&;F#f$vL5TM4$>pPR`8zapJ>dpq%n2q<*xn|=W>iOPm zJ{QpPp22yn`N80PK+JuB$KxNZ@B$Q8OkU(`FASAkL}fpj+{J;i!Y?e0xkpj;&!k9Y z7|11=9jFazFAY1mj2--H9ZUhFk8tTHoYhx|1$oAdyOTFhJ$CZ`%{rW#X{fKg9JM%k zd&g>eI02k}nXLI`;1=Z~p%Q>5MyLd!+2HI`W90Q+nK9atsRL{E(Q5@2 zGDqucuSRW59|Z?izpSr8oer$7pq>Nk4Nw6OT!$A0Fc}Bdg>_)<_!N$*9eDW*2IT+1 z#UEI2M7!J!sG>Vd2iBWe+!@8S53E#ao=Og^w@`e>8shH2nk9ZK#k*vSONz$2+><3f zjpAJ?o;ose;B_7ur&DJ)=!~hjjw54C1>GwYwExI>yLU>=d4b32gr3Qn@J>{RHQ0z| zMmrY`cTqOA5qW3WnXo4sD{}5e+h`VwBA)J{U|VOxK#QFT?}bQ950k%-%4RjVzlyTt z~SjVXUd+aqAWSB zRw{ckRQ42=&2Gw`uA(eC6ILpFCRFw;mGw7e&s9;DoCzzHJs&E2fy(AEWiJA>4()){ z$;w|sIW~140SY|^7t^|ADb%_S)4JR*+={3;5$;HoKZSb`HSxmHL`A4@8d3fd-cHnr zxh2q=$lLNVpyEu(5g3+B4Sc&2WnLvhs28{hfCp($dT1 z-=(s74Bo4vj2^C{?EO&L2UON%%03KhJ^~;{e6R8eN6i?KfM!xbp^*s{6tYdIppbJo z&(s)seIHYOVg~Ey% zihS+Yp|WqNY(A6wHc(cWpM^1Z8mb;did2Sye3#jQ+MxFPu!A4iLC!k(5m4*kSA7{+ zBxlUHJNWVRUIGe&z+>fl#>v^;jej`oapK^yIFnWOc!zoRy$kAj1rU%P*xP6t0%P|v}yLoa2A zzo1D0Ovb@)DINS4MYs7pFN1lBaPbGf2DHm9jsm)~bnt6r@e(Mmeek17^Hg&1>qPM- zYlyppUzYd`6kjS^JoTtCOT4oek2wO^#<7(in{`2TScAM=Ks)ERu9QvXW%`TfMLQxb z1C)=up>5PmQN&(%3TC9-VfGDl3|@epQquhqp>)vxmz1Q`vH+Yz_b? z+HZ`DS^1nO$0pVD8HnE%3yE5rd303cv3)Sbk@?KqL zXL_*AzC8ZPXdi$MIrcJVN4|F640F==+||wD!f&TJE0{S0GtKd}^Px88AcEBE9XSYf zO1-Y2p47V_RKO)UyeKV@k$U+y{%ZNv(QSTJURLI1MO=L9jnFQ)77FOdQtBPd;$bLm zEA_hENtNcQB=s&#@wKzXllNKrX7N^Z~1)d?Dm!Qj|A@+zyHwkB|wyD2tdO*+JyhFVEf@ zBTWeERs`0Vjtyapreh`Q*}{gfGN5GxgH>3wrNOFznDN7t^j2258VYHePhfIO&&; zNB?lHWU}1PC@jiRLdH>1-r;OeMdTH%1BjVDAm6+VO^~ODvzS={9+TIa3fr<0;_IPG z2}7!}C|mJi=+VPkwqt$dTW#Q5c`aSkDpD(G*%0-J0`&;oh|NcKaC?g65%tx=U4W8y*$l6vge$&}GDih_|BAK^{ehI&S#F6^iEZ_Gq@`50Yom$IT& zAK7f)lL{ruj{ok%d5csCne8jhi`k1sK&MVwHbQO($YCaBEN~|vwfjH1+ns%)d}lV} zoVbE|=45xMfTmsXqB$XBPS(?$?2mr(`|+|5FMHwQ=VT<>`FemKZ?Z%qqwbo z*L^&KDlws4#>u|BC&kBPi%W{Vx#uNW;(Jp(b%IOh6^^NtS2#GIS7^2w6mzJhuyJ{X zqqV$p2>wa8?Sl?wlASCMWO?Lk_suYe!5)6hr@A?GLp#km)Xdp0(;Q#BKWbwRB3Rur z7y~%~b&4ccP){U{feL6k2rr5xG9qbnMbgpeHh&~9NAPkOESlKOh?k;6d#u@p1S+Z5^tq=Dv~;;{$hY*Dn$|p=Oc+``>Eql(~-o{S|lBh zf6{G7qQfwfj%9h|YmcTmsZ`Fvu@nBqKzS!j<;OxIW?{ zRoW&`V}0aXO-w1UM18s`IVn_P`C4_6)S#P5|Hs=^z)4lT?U`9h!T?0USQK3ybrpL7 zR|!RtFhEpH5Ktr~77P%(yRgOXu2C_tySux)`+J@f&)m6l?wxh@`~Sb+ckg@Ne9n8$ zdG9-yosk-`Y!fq}nrw4I#U*97PlkorzOD|O>|&h)zR9#@G$qq#zy%_lhMUPW$H+84 z3HGl&7jbIO=H*OY&cMZIdLHy@E&#*eQh`2;?D=4)9V=U)=`wz-&ZhZ=Ve?pl4w;`v z^VsJEf_B;DHxw?$&`k7v=;klOh||A-gUj7uJ_lF0!G#=L=>`{ZaFrWe%)!-ea0vzl z&fD!de0;gai7thRN%CFn`Q+!l^fE|$UgT6Sr^{>I;EJf^N(|6LdPOr)PK7aD2fqe`3R%7s&`g%E zrQvmMM%Qt0y&GK5!3}P30|z&{!Hpc;ga0>^wy1}g&n2lq=vvul> z%<$~o21(CLoZ9WQxy=mC4)Z;nwee>dgwUWBc^o0q$IxdRtpE+2+o z&HZ37k;V5&k63q)Qu-jIX;ss{PNHX*FtxRh(fpwb=JrpPL*|du{Nb>9td|LyKapat zmsz&tN6ndt;$P7|>75if4@{8a;y(vGMeze+h>FqC?4oE4{|gS!z&z?0)%h_vvrG6a zea9XeT)N0Z<53LFaz6*%{NpsmCU~BMC*0r#dI`K-(myRkT)LM_FT$kfBhLOMI(yO$ zUgqE_H+Ut%v;Li--1DnZ&#%$h)6UuJ96aL&ZzOouKRT3qelzO%EjoMFIeVLf=iJ~O z3<})PZY7cM=bh+Xh(d|di?dkJo-fca@6F#&FxS6r#LV-?9IN#K43+H2Ajp~;3BPUX<-Ycrh2 zq1p3%6cKvf1OEbpvVS>Y6)Zk`SPuQOCvr3krD=41tO1J*`Z69DK!yFNb)8AxW>k3$2>47cRapl5xg z$GrEqBnFi#6c@HwF1fcWH|RU@|xl0FGQ^U0~ep+)uC6@ z93q2DuXk$6j-6_n6;Czw=N^kAQC-&x<~Hh@G;4ujV7+2Lz(yqT^;#>%T;0F@VdALy z8h~Q)>o2d@rl$%m1G7>*kW7z1kemTm5&vI^%vuMM`Em!cHAp6Y9RxI+(RDb@$j^J} zx`dOo5lbWRG_Lo*Lf^)rUq6W6OE-WN#d8reC9~L#*cvCAt5` zTl?dB(Y5uT?0V3=@fqy-&(wQSy~*2!vufmaX~%qEg*QUL^6lcK^^l@FGRe!Ew8LZ* zFbmvykrHio8Dza_z<BRi(?d!!%YF{h_JQod0Cv7MRD;3WHad1 zECohjU3F&dm+5KikG#%ouB~6<{`9nT*i)={L_K-)EodGq$He8!F+rEs`vCz9#!t2w z2n$mv-6`(`ZDwr{_$L3B(Ukme4Hxh<1UHj^j*G zieMOAD&X6a-3{!trqKQiC|$bktEO-$%~uMW$5u6Dz8%eD=PCZrUYt|0{Bm->{1Uc5 zPn>FT)$AuW&eoORl|eFX!x1ogo>m|~@1@%lPHby%a(f1m$%n*yD~h!g0vNZSG(x#5zFs4z^RgY_XQ`_bXf<`GTb&dUAhFph!w3%E(N zj4eDJL2Mdf=C-)IxbTx<1FWd66H79lDTW4Sp-9S4y{yZw};Ra`75PJK+5?(T!-O6+pcPmTpSup9jtFu3w&PKbzISJ0X zB|AGe>g+r^8{?dvpWtk@WM>ydoz2Gp@AN%TCai{u;;ST+BIai955M$UtllKU41eU% zOvem=;?MvZgo)E*-ut_V{&t4H!20QPl1*V~{Vt~YZ+N6c|5=thxmZ8ArG5QiAm9$H zi0g3u;$8y3_()i3o}PjR9q(|9XHr%ERs^hy7U#yGKW zKjTi?%gL1~PRtJkGp2oJ#GMrXL#TJk8f4AZO5<}MRnc27+DMp=zD4f-}dhpL%#2(`LwWk?BD!D=Jya9 zqXSy68MvFg+zW1ge~g%|`xqhCV>2LU$(PMcRB54K2#cQ6o%#Lrb$}Z@knGExz(oqq zbK3;h4@O--MAx&O>xa`_FD=&$)M}BW0FOiiJjwubT!6>^Nr1)iVaH9y#q-0Yz>h}* zKY;qBQ((-K@FLat7S1x7 zQh{ED3wU}NH*?ZBMg@A%RG`BUr}hwD4&voNTzmz34SKOTm3>&Yf0{#6%#`?}|Aihp zD?O#J!)0`qM?izv-T>ds(lVMd%Xi=cp5DUE%#vfw@+mXR;}NI!SYD3i z%}HPsC~~uizyA1?N+-vZ;;%nGqtYocrTFWQQOmFN!P3XF|=@%6_SR5^_*bQVHG_8epORpvigaygLHUdqeGyj+NjpM4g31#*kCzX~JHJ_k{B_E(ah_tIvN z#%J&RnAtN(>Fk?3e}4AHAL6tC-^|`Jnlk&=Z~;%Pa5J;#7_)C{W`84))LzfawY*%7 zi=TZP=+)c;hS`&P#nYDTTfvThv6Z%*R1`#yO#xo25Yg2b8xEA-K z4161g1wwU8;=gua-@YzEKU9IVR{?i3;r8I>7huFRbl~7_H|WU0J#Mfh2lu)`Cl2m& zgQYlF=mtx3aK9UL=HLN0=)%E+Zm%VE&-b~jj_l1JR2nuAB(peqND zxxoq;lqQJT!HnAUc-*OUgGzKq-b{YpOILzaL06{hC!AeP$PS5G1$?wQ9w<{=!<4ek zF}5aHy~!)dY`w`U$y~k3DaopOlTnh*>rFmMwx~DRB-ygwD=w5fY&*|>k{BC zQ(gBSW8_UFfEWf4+!k5)LE%j!H9C-P2PwAMyM|euz;HW(?PC*Iv}@f5@d+#*;I$9% zItF;10=#7dyyYDafOiN^$Do3AM>CzgnGS|KVHn@#ei^yTxsgiykDZ-+-+!2F!P72u z%pGnSP1)fi;R2p^!_Dk)j?{%r+w^QylPGT#g41x9x#1OJrp9Y)O0IC}Qe z_0`@B$5R-4Gr3mmRUlJYe9_FD`WMa2mditd87?lpeHF;4?#<-)Aco^asM${>IBMy!?cVKToruSMxU*rRQls zvNO*#<~-45{5L} zz=@ZeWH>INje*n3!8tMr$4ie2z=@ZeWH{WdjodYhI5kQTU-k#b}974mu< zWTxC$MpMeoNpJyAC*Wqv4aX=q-A%b!90+R{<)tkzt#R??=49yAbO58Y+?-Xs%uZ-iP@Up0&j zTjX4ViB;41G3ACSR#WaAUrk*ob4cLqO)kfAVWje%?#Z|5tEa zRvH6m83*TrARI59AAr+2_O}Ab+2LmORii?7mUVD048rl!ivn=sMJyQ(w_GFPEa%`{ z9E9VgmqJ?L5=V-dSxzkTWssR7W*JQ>VpqWhJY9jCDPkO>i1jc#NtkhMeHUzSv5QnA+bd)>ckhZn`xe}U~W6mkom1JFK`jDJe(Yw zt~D_dufP?8th%n2?7R_bPxu;WWY}T1(Hp_YTiseTD>E=$7!-)ULeb;~Ef!7gR9`e5 zHdCdzZ{tOiTh|rM?jU&v?m)n3(X1gq@1=MCD>yEVje)bagL799j+ZV7z_};(xi>jG zJRI)O6)I$B9S7&`ARI5fCjcj2G?U?Qi#HO^x(?30K{#Hz5YhsdI8rpta$=e9hs+dB z%VAg^=|S8~(c~CKv#%+dJrTCHj+YI1Sq~RqG#`OpO+6T;Me|YX?lDR?fwXeb zq-U2f70t(K-n)XiEt(?4fLJ{MJDHbvA z9ACs73{y3@kK#p)Tger%O+j)`zJP$yBDN9vc`tqOU%_!RZw#Ex9GsVeaJ=;80GxQ| zmz*7LR$nzLWT(G_^GXnom%bW+6E9-PaJc0f31@Q$=d~alFMR{j0+%>a#LRMHncsxW z6fw(aN)dY(F5u~H+)NSU7)5NLDPltqwssINTk^66F20Dp2fdnYz$h(Z?^|~tP&yRS z%0-NxUBXnvKBW1u3g)(mh0H&q`F3IRSP=`Ef1F~j(qW5O)V#EaeUjoNR>a~?ibd>G zI@vZn5h1ZfEb7D;vCm;%;3^=$M2FUGdyK>@FvXBn*9|8-Z-iP@U&M?ITjWcEsZhkY zVTwhJJI5C>2g6hi?xT1S<5qG-YzL6slV2fVw1{m@e%?#J{#S6^%o_t|M+fJdARI6K zHUKByi6v);o7Gp13fURq;CvT^zY z>DU=_nrikc86wzUR2m0v(73URs5y6MhzQK#!)>6wh=y>u};PC%>`G2a;}$%jY0cm-U6 zOwMq)mY}IWGCAWg?`7>FQzANGkZ*8S9V-MZhgvt&nJx*_vaON#(oS@okO-yO{uOs< z>6Q-TQVPox(Q7hrnGM_-w)t5OWfwZ~X|a{0=OiavhKl>T!Lm`sW+s19T#kzSImP8M zD4REqN;UZSb2RVV%z&8q=V->(7}XnKB&+I8X#Ob}P4nKcD+XGu73j1|L!Q_go>V$D zXVf}1Cy`{f-fVG_xq7q6^iMB&e-OISN34tJ6MJL9ie2m?Sh{@|!HS32=CRE}9`7Pp z%Uu_-KS2L61V)_3Sx;YNrYC&{fx;o*+{+^pVpDEzq)RZpQKull_Sj2LFAVZnl z*T#hHy4KB=a81UFZKB36j9c!;Y@&nR)Yn45@=fHW-66%HGXc zya!~a@3V}i^nHACB2B$;Gn=PW@^?fIn3=yn1l}-XT@C4UqGW+R}aa{#a-`9ucCs#1HneQ$h=>Q zxt@!*?~9riZeP7hOpWk4Z_dL}_8iGOo zY&Y17jw|+kQJ;0^IMc0RT9%Q#mu^GH35c~Kwwa20_lUQxfGd#6a~-asH1$Wu^?hD8 z3^FBRI}GyYIji9n0+vIqJKvdZ57Y8Qc5{d|F)Jce<19LdE%RuxnJ&^?hD(H!5D}6nDp}05EEN8 zV{44+4KR{b^(Hj?GMeVS;V2BWSbNZEm4-aAH9VsqjeFdW^y-{0bXQ+$d||wF3Z&TVms2@!P-1rb5MxrK z6-!3mn8Ii(JyqpR8ZewrAF+AH8?EFG$mek*H{g|So-+`ze4bv~Ksd1_W>rgG;#sgL zaHB^WE&tTq7c$dmSw>SDt=VvaH0_U@*)$xZ(b~l{S~nnU?RC6d!^>5;_(p3E^lEMf zgL5r5S_hJSt7E%H>$cM2?QV#-(Du7)b7@lmH}C|F^<9MF)QK{UUkg1POxLgok4 z{LTvIw(km=ACh9O=aTKaqUOw6vF|#RPHqWf&?CzBT~Q}KfrrDqKy##~*8<$lN*)1j z{%(x8zDHsZ-IX^v{!vuA#|@6gpoXgzScq7A6oPRK%~P5n`;3iR*4^tOA4^leZCtbA zWye9*^Dd`&JO=su+~5RSCE!)sY{wCe>eF^2&HowRg)Z_*H1&Ax!#(e1Cs%N5-vLGe z)!pyho{Q5uQOC*)Uq+xA@1>G=Gf zSpir1elSqF);;9Voka&e%lNNFqFm&??Cc88%a^_GVdwT7n#Qv1W#>YsET4w~zmezc zc+6^eyx1(6gJtm6o8v<=TW@wI$y~iz9X3n!lJ`C?ppOcVBUasFKg9Cu`yrMoSN;kt z#_@iL_1N`8kAURCpO1hBrt62y!Owf?h5rSd0&@vi=EzmT^{B&jQ4p7xUJPl0H63n= z9zEq_G&F_nk^tyRR|L^{>6L^N zYdCnMm;&~crQ3)-PgxpvVBVO*=mvVK%9}J`coTiZ<{9rPlQ-Z$ zIK)uQDTaN8| z-M34J@3^6Q-TP?sF1UflBi8E@hAUL+br;h7y$a^G*A1E9PxJRHnA=`AWd1;kx%vUy z>qgC)wPLUPAf3D!#-OIn_PS9gzNvT^<^`G~HN8H>-K^vz;O0NVi0k_(2GP^T7iX#^|~P#Ptd$#?-;eL`@}_llBRy!xF*lbo`S6B2Tt*64Dz44!85c< zz^k;`rY9QJr|nsq|1-RwxyaAa)Z=x%u9rPu!L99eqk!r@cWz&xsXres4PN#lWJ<$J z805cjRxkhafL}V(S72JUE%ILaDjg@}S9{y`y3y(Q{JvHJm+f_O=DU1vbP{pmfywzy{_MTJZ3dKUhH+v!7_O3&G8|btv5T9 zWUk(<4trgC$$KB~Vo+eQf(z=QiTj4I%!z%E0b6ZZ)$V!8jGp-k>SjS11j{UG6IjMe0Yam#I*xKdQMiHj`EPj2d;BVhT$cdsQ&rxi0mETuxZmLd%l9j8W;1h)CT^^0;{Hb1+CO>uotIy6@lD(x(5uNk8*k$NB)geoyC$xA z>9Bcl@So58$5bEKwM8{ExGHU~G~79*~23k;&CCF}StsnpI5 zT44}a15Lv|b)yLC7ImhJg#72dv^5=b8w9+^y2GeLE;#h2_ zSS5Ws#cJZJRDm@!-cGS>x^`+wH`(P7uzV4`bou`RPJy`uEc-O8fUA?kRUO3TrCt9E zTxK0SxMqz)x0FM-LJ*yoc7wFQ2LmR}AZVDErlF~hD+Qp(8|LH{=F_T?E8N*(T{(!= zOKTuSH)Zf)Gp_Q#Lf6HiTQ!KzOY?*i>st7bXA0Obmu@CD%&Wm7miuKG%H)3am=F!~ zvJ$SrSh1tm_=R!HZ5rlMRJLJ@9KGe;)N2v2{OEb^Yqg7{tGz%6gTP+cXhbd590FD z4gL#UO(-!dICL8Z(Rpbd(Zvo1AC}1nqbDp1+=Y>L-Zx{tAT#Z}Wi+Lo-vlnOx$1E< zM~!2&^GBO@epQ66t>I-QURK1#xAVQBSF<`8OjYrnY#*{~9ox0@YnBezaznNAeQDDj z+(2U%Yv&2Wl~J|x{b;^+1#{cZhs-yn`8pNMZ95+_-z>#kO^a>kqvp(7v7PTvCu@W; zs3WuOeAJ2WnYMs=f#yg}uk~;@D>(q%{Q4MieYeCQdX`sn{DD;3zzqgr5Lg3E!}f$x z1a%ua)4?JCc`qG8$J_=1@3D41>fO(8E136O*G1YIgM6JEY(vKt+xe)^x*pDSTbPz* zB=4m|={NzgR>bzAQSTn{unM?rJ0G>I>*;W9M^k@BTs!Y&!y!{5w#Ojf%USIZ4k)OB zrQ67v?g-QJM0n{4I!;K0Him8Iqto$;*eQ%lmgOm|t9Q6|rfDn@UbYKlO2n=hpq=*{ zgr}i~r-1Fe+5cvC^=6lo%+{OjLo!!y63BL*Uh>|@?idtUQ{aMn=ma+=EOW3%GC=G> z9B(*SIg7nMOQ`SlS?F8|E3lx(dwtea*XwTrl81K`0-8CvSEuIi=Dl*Sc7l7tB9{9;3}te^S4@abu&;#U7^}$(#<-9?O*-aqEq)xCj?7+M+h0#QMs>+)*U^tmR zV)Kl5g2@|@&$>o#z|Gt|ryyYYJiT+@vi$dVxTXeidFizO0vD&9 z^WfZv%?ju?cj%@E(Rt|%qKh32*4gBPF%uRA?!rhX=%3@WATynyWi+J|JOD1Rx%R`& z95s&72~IYh;1GnZ9mLC)yljDs?*wNjVkI?P7I;b7{VP1#{a8hRhG5`3@D#Z6_EqKRCr)&pX=*M$MVEVkdYAoopM% zpoh8b1fx#;m_ zJ%Oekult8zFFTR41iV@e+rmVBd%P!AKxMnYsAb(Khw5aS`t#wsKrcH5GNs{E4Dx$8 ztJA^(1+{$HdhHBTvq?^;qtVXM8Fb{6Vh?Z6ot$hQ700;2nHYq2(^*s+>y*xpdTSO~ zrxbwpKO3pw=fD-7sUC}&FsHy?&xA8z>dibzR@ED%Z18BB_lD;YQo_n=m)o{Bx;}no z&!>6Heks}yPY%W1S1JiY`rr6}Y z^wR$VPJy`uEVG9y;Tq>~T^7XUrI-H~xXe0uaISHvkhQ%Xx+{X{y!6Wd3SHGdLpR=` zyDEszORs^nz-KU)gekx$rwKGPHRjp?^!O*IZ=iWP>& zFN|Am^U0|cmF?Ukg<-0j`fUhUUKqUec1Tg>_n~s$pv3G7#F+HSsWj}syfKB*9rRR{ zH)+7|F8YYgGycgbc?14~0yxdha{&UD&(llq{x9J8Q{1QmINjm8Cy2{S@BJ@uHK72` zaOmy}qVv*){}sA_SO6Owy8DCZyz~L0iyd1w8p+4@Ay^c6Mk1f^*IneQ6 zrqXe4@CpWjHPAHd2ZShsy5pVct2FiN?mpLf*=v+>69jz6KG#Kk``Nt?^PWe#IB#H( zKfw*&q~nx6JAn5@XZjXRJzn>@&dc7WECH`p!}jnYyzf*%Wk1(NE$dElsNSWiKOgRM zotM1_nbPn+2Kken)d%5#f?A%2UdO=HY?2S@=oIJZBRcX)ai8mscCwGDc&ZzGfwCmfpQz2TRH zl(4ee<@R%36pi1BU(q~ezm@Nay3<`UzNTqxWxebh$h5NGVt~(ee!uf**YHSls^&1; zshT58GFxv>1Ib*y*%6#Iz2v=*?=dK_K*9y}&~%?cSY`wKzyPtHC*IrfF;M)_$LE3n z(8sC`uco)-(;@z$j}Hj

      G~YR-zvf(9FSo=rffl@1;LMijK_SgYwV+D|BZ%biV}A zdFii&6MK5|yf6i9x=T~Qru#Qo#BzTYLz&$F9uuPJK3l>+7^}$(un8GO2!7Q;!1BN*a!#cAg}IQQ0}0=f$vx|Tt7 zUfSxvLRau(=+pw&@9(ccS@qVRM1EzqK7QUn(WK%x(7{HD>~|`bFK& za8h6bks3yqH|BgAGM6?9O(FD_2RnbeU3>T#M!lE126V88Yuq z^ZUc*u__rdUz_F+gw0jvY?Ta|uagp8=C(>k&CTgnm0S-_3QS#w!39zgQ)?3w)Jy@XV3po`_dTMs-#4VUXNk zbqE-(lJ}6G_tGB!3XaQ6W8ggE;Pec_@zP!aIPqsla(3LJGzQM24$ekFI9^)+U%-hx zLnS*LIpUFJ2<_AaJ;lHqy_G~NR>2u412F1WTr}5 zMpLTf=5PT|o8e}vB*&+>+)mS1`AQCS*Pc<^@JqIjMUEBRjLf9vTrZ>R-wXA=l5t6%*uRE3ok* z!B}Is4ILAgbDXKJdzFqM+7_bd`G0}@yq6B6``Bj(2he=vXG)7jh9CL23s|_w2^PZ% zj#G&25Q75Vwuj8@5X)%F4%rDV;AuzP%nsogJLDa+L*7By+P8RlgO}HE@jGN^=+(Rr zM(GaOmFy3|PTL{&(*|9}cgSuu|FD92D^sFE=DXAUqYCEsF&r`fW8e^$YK>BQ(`X#P3O3!H&F2-)faJ?dDrH3_IT zS6;IH`erig9NfOU`Qux9VD<`}gtKY2NP+9&MvE-cwlhd-kArrB@nBu|1@0NISm5@7 zR&|drOW52NWLxdL5yH{l3|ra~7-;rY3U{b|qz}xSD6kmM&@M4#RBTFkq05zk=iP(HJ=2 zI5^XSaJ+QJzk=g7Ph;SG>)=v-RX6AOs7yJv!i^c7YJ=hpH-#Iw@ z2H|+={*V^9Nh8(WEGKs20g##MZW&Ff?sMS+p61|YsyoN1?w^|K{wu=P{>;mdynK&~ zukHsyujUUhxXp^6k`5vJPp~Ujce-?$()0gNn*UY7+*bFH`C&BwyMno`?jiHTX`Xp5 z2tHQbL*_@&JR3HTRriqjku=X$Ft^n`WPTLQt16h=>K-ybn&!=5Uf>L{E~Z3Q7wFNA zGS#Wo{aAWn_6nSYvq5#|dbm-fx*rei0^_l|H^)8W6${)xFsSa)qJ+(DLAKS-8zFY? z2@IQ9-MK@3bvIF9adNpuSvBU)FIHn70bh;Xbj$(gfrwY*V#FRTi5~$^LBMD={vBqS zyqBK#ui&_3H3m*A2j}!4950>sui&^vY7Cr39Go+QaJ=;F0GxO=PF^f-N9>u#z-jH^ zoD+oOrRPCf;1Wlwu~|+m^ZAgOYHS%zsm2$<1w75i%~WHKQH{Sd)p!XYtX+(kcD%H~ z#aH8tt=%QK)hr2qp!&ut5M8*;sQO+?^G+4aZ3POMUk396qr-23ZgB5fw-kty-QR(X zykTRiS1@KrumX@{H8&LV$`o_`aftmi5jE#&Y^66-SEV>n+Pauc6nD}_POkP&dJ*hT_r>f;Bfapr@FgnY(&No1u0l1e4)c#(d)ALKmwHTjT5CjP9#kduLJ#{`KIS z9cUR%*?~911w7q|o7sUJV+S_7gYN^D2a?)ldFjH-(zy5?cnkDuRsh4`vj21eKevNj zpfYAeN!RMS6)|FnLev6(F4Bkp*x`kDP*|ES@5bbWp-Xde7b6isYu$4?*%5gxC7ilSe<_J-un~uz6MyOd-5sb;aUJsfmy-5y2rXS^}_;l zO?KTnWao_#c%P1X^skpM6v1mSq;i~kCaTc*aq*}%bhDG0|)Uk<>DzvWF{EVr8* z17|}A=anEFFMSQt0+%>az07iAnO}#@R4>bDO7(ghF5u}++)VZ27}e`GQ@u7u*xHSF z>B&nSF1~ub1HGC)V3eMqcdfhkDD4kv<)TKckiNk7>SX*j&#E z`vEv){t3-D3!A4*!AJib<^_VsG7)E8n;x5ElqnFA1r5v+ zyPDjajJ#oExxXaB!!JX{Ke%O8X6`_|O`-DKU7Ba?`f&Rd>pHuguV`{b>>Z_ko(^57tC zriPT_v<08X&K3MEi30(DK)`Z1Ui#y|g2U6(NH_x>oS%Yly!2SCm1*Qk zXU^sR6?O$qK2i$J9)j#Q$V@4;jHZ;rzu*F%{=m&_VUAG>?=_`xTZFCMnwKHG48p~i z!oQ(cvmF?mMDc}J2E9AnWpS$+0cqt@NY5_Ou~L{zaiY^}OJUqeu>e)k$?ytD>`{w5 zDVD-!DNcmMmcqD`B9i8GvV9mytQ1C__+r$8<~xMVW2G=;-je1!hRsu^;G?&Od4b?v zWkV_438PGbh#U{4(D2MYYC{9Yb3&BDooNs~ufxd58#eY#TOtgU!rgr-q}uIFNIQPt`r(TfU+q3q7<6hV7NHv5}7Bv39vpWhVmNInDvLce64Av2}WGMZ8fmxBvLSq3+=g*iqkY-c{}k44zp(Y%b}Wp`YB zDO?_UHRHf2Err$AT~|uSLz-3!Z3jfpF41}kwF1p2R4})nltbn#(tKhCb6fsG=G{`v zRWAdm^!#7qv78p=*!H2$?A`^+;-gImErX zZW7sfBgAU2LhpX@{6|=$0%4xQ*fEZOgyqI4mK*L6Uv6AP)6sCh6l<3~#*FHY@f48U zd#fQ}^ce3&e%?#@Vyx+KTp}6+XCDV=jUXH^tqs6gJ=T{dXXhWlnd;!I8HD4dYX#tZ z(r7q5BfiL0SgdIdPWK=jFI_tTC;o{#IXgTqjf6AZ!C5B=$4l3Pw7?w~shwtbVb`q> znW>$Y(UjWR11{icL)=X59sG(V_DUO0fl z(#N_7Vm{k&-HSDl5A-bq7F;&2C%*w!ZZVJ+6)G~fTd^W@-}#E{=4DD?sc&16IWt$0 z4+qI?4MM>3Y-w=r;zaBzkM;dtp*gcDla9Y`bi`T+7_4OYgSTloaxFLF1-P&m38mscP0Llg-SX(jtSXLm(S8d5@73 z5J;j$7N=+sMExgEoj5XTwYU*&3DMB$Q^$;)7_nLcqINle+)0slNQpc=+5NCo_haRL zj}-SKAxoIpZpo2%NsT;7k;kV*9+&KX&s6vO%6&tM`{|G+Ol)d$7OK%AfI{#v=eD#iU3sXlI#kDHTW+?eDdo4p>Qgu0T=-45ZlW2ViR zFgUQr)tsZu2v(Y<)v9S|~{OB*$Hl7We*e+y~O*KBKr#LNQ@Q z9)~EQ#6Aj9Vk(}6Fp!Gpz)nfU>w@%3a@?2F;=U1%`(}FFPZjqgC?=%h1Ben*@g78p zsrU@SKq@{5J0%rA2-3I7alcNB`(rrnPw8bw5?^C#Sfd2wB3! z#wSHKtyCQN?{I&G}2cpu+}G2bza4h|PP+4&WqjMzZJCm-RPx+f0kVV% zS3?wB#cXyti0~84W5-PGH+jY+yz9vMHzX^VcOA<}9(mWXqIuVm&8-4qe8bP}1|c4K z>kITc(2DH;642ctO8~tlLlW|Acdck68-?l5^}a5LWCy24 zK2?!VN{M_zvisvw-CrR0=cc$nJK6o2av#p?8Ip(cdX2(gnG*hT$P)5;DMSf*y;zaM z$S#z;3|TgJErdy@ruklmojVPw}yUWN>(k5hbn2w4L9_mkacbDu+)g#J54{yHV{m&xvd z{&)HK1$qexe@b$Z&Hez9Z2`(wHk)m|NRr}$R>-w|82djZyj4Mn+T~nM8PG` zW~(4d>q@ec2OzhBFaWtN*eQ^g6y)|$Ou)5xTHH?IxJ#wS?WVY0ljAP0xZ%UOtmJ`w ztOQ{oA1i~Ml8=GHwFMLtc2$3f5>mA(L}^RdSMmVlK@bKY4+c90@(zN$9TXFA4OQH5 zDz}k5fNMtx1Gq+joq}sG;Ti+QgjDVUQ3B+V5T&JZH^~E#$3Yl?yf@e>kY@<;R469k znxeSjR8EpSfU5z*0Ir!}r{FqFxDJM5LMrD%lmK}SL}{r!K=J_O!yybnJ_76%$R`W( z2~bSHb)4dcQ+bT!0bHj*7{GNZ*eSR!6t453n2^eIAxeOJHbiNuJX7)jK^3_l*!(~5GUa7dTRN^D$<&s4(*^iXj+;tEJFkKIJ3Z{F7X#o@y(s(CCWpM3h z%>qP;pU!WCFfGToNFJGw{~&rFgn{`i1UqFuPisC;KrsRIV-O{Regwia&<{x-0R0Sv z0npEaodWuGfqn&w35)O&M8Wy6#e5?i_s#UUA1Lm-Y0f_kJO3!%`8RU@B@`1T^?6#{ zZ^LoFOON}j;{KH8{I{_4-_xCUTF!Td9hNIu(vtUcOF)(|;l&^dt|I=J3nIJmA{&dR z%)BtFR^(+JcMkRkZlu+-rT(V+$uTx;AHRF+;$KKO5|{`BRPnFB->4pc215vA}#Lj;kYBy z<4#oEy`h+}5PLzCun=P*N;uTn+$0DCshA9QN-Aav(v0M|)6(MZ8;-kQdfX!w_b@0X zq~Z{W5>jyxL}?G!10^rpliA!+5C&3pG}tMrI!%yIhGGJ)6BRdnR*siEfa`P!1Gvrr zI|bJz!gV1O6H<8rL#a z2m`oo20H~;uWJ89uB$FlEUBU!K$ei^^&l#nP9Ia^)`2MD->vcDs-GhFPKms6viprv z-4Bubfhq0>K$bAE&66W1#%-0uuo!o)@-N8TYd@;F5v zn-Y0+vinh~?x)KA_kC6LA zQ`{e%>f=QDI4;G2iNciu;pNeVi{J=On{8E6GJRI}f6Sx{}RZ0AZjE z&IdcC3|=WnmnFx&BrWb$;kZ|)$6cVfcR(>=MQ(>Ep~T(_QDQ3YhA@zdd%#Xf#Uq0B zU~=61)8alFj{8`8+?N#hc_=2N;#r6iQt>oIiK%!Q!ayos0XroX?+Vge$#LIEi~C+U z?)&L+zf|1MpqP+~Paq1Wf-f|_3dj9AJ?>A6`+b`8pTo|7Nq3&>>N}0Up_nkKKhxq? zbqy|JGq6(@v5n%kf?{IE+J>FCOLxAMoOgs`!lc@##a%iaw{v>ju8O-{n)4OH&R0x# z-b>EwN)=0cLdX&(ydFfsL}#<>K$LJw*%K;q@07?JC%fM$)%_5;ADH5P0AvXh+dMh) zW~q^fEAr5k$lD~l-zwGpZgRhKiu)0eB}{CGq{yaq8YB0kQrz#J>SL08j8E|~4zdJ@ zd#1X_FHxE=bY`>rq`04)>SMNi?3WBM<3CH{dh!RtA284lB%mX_m74rq@yyUp&q{Y239QUI1 zxYsD|l~7Db#pMtMQ^AMvwc)terN_Nhac@dqq z$;-lLbE`p^l$iB}Y#nGNC8j%M39Gp#L)9I}LoZI&FlpCX4>qmSf))ffz6(rRok(8HjWv>Mw&mXPwT6*-J-h~#C+uq2}u zeq>7c-5^WI*)9+zAlpfi!^n1&ybM`3HwMC_oJ|(!3D8Q)+1`*PAlplk!^p-;UWN=g zo1^gir-a`ZvV@$?geU>o42Tl{1YjD3X|-}6$;)78a|c40l+a@|qa&e}l+eQ=OMrbS zM2WBuhA<8GT*=E|Bir+Y?KJ2mVLJt~1Z*ckl!)yF#SZU;<0KDZn=fqVK`#m0Iglmn zgtH(D!sgTMLI{&q>mVo}MWcS(JO%NubzeAC4ONo3- zvU{L^SUw&|@v#uH1oZbNxzA?rhA3^v-X(e2uE^#dfiP*}&k6L?&`R1cPeK;l71`|L ziX7grk4j#K3^{vU;a`DXLS9}q3;4%C#jAK<))$0P;p)r$F9Z zkT->50e) zngqp!C7u9L0_43RN?YQ+Bo9EI3Sj{9G_X@3&k^MPp_qVcU&Rfla;D?~Tn9oJz%>`_ z6kI0?*KtrxNaZmQB|tt3qQuVd2nf^ie3;~c`J4n{U_K{5>OPUjShM^n9>WKwl-$mqRgO5iW%&I3M=8SBK+XlOFeG#l0cT`7L4Rx28M4 zSI!qeF=0}7rp3K49Cu-Q+(#Anp)}`@g`Gd1?)*bJf3H-r8q5O5{J2 z-T$8IzKz_s>Xrz;1w;v}(hQ=6RmtYsLKryi?Z8es?wtgwLvq|D(&8=^j=OYv+?5n} z1t=!0V>LtxsaOu8#8j*dVIUPXV5g*FEkRl%Iqqs{al41(uALrtW5w+S#e`J!fG8mq z8$y)!kXT>xva_7cZ31B+RlUJZN!36>-U5mVxcVz@xP#bK@&K+u5C(7!20I1UPQtYV z6cbW89HIos!yrma<+hRsAny!e0P-$ir$F9IkjFqV0oNXi8&2g&$pg5?K^VZbH`pn- zJ_W9-Y*p@?Zp-5zjH{}?wfEe2?*2XRxvFMA*m1KT&AnYVoBarmhfba`b&oMa$L(i+ zB-lNW?9YOHAaMliQFyduv+qH)>6mHL$4wf^-x&^?zf-Cc@o|WGJhiK82iTuMYqMEX zrta1-azf-MIomaZxLLN@mkHwL6n>o~#2c5tT~?Z}WV6!3-CMeQD|2TS{(zU1Ec_;M zWCk`1zd%$e3qO_WM0`ZEkXb1)3s~7SVY4J5a0_owRP7gf=F!XaspBT?84=mgLYHtqyt2=DIaxY(+*Ow+`9dN)4HzdyN~5-vSoX zmYr1_GQ%cLiL#rwYmOCJOTgC%g@MMpMx&}~Lkp~`PQbc*i)b>kx%J9{u`aIPklA8f z6hJdpybT&MgC<9~2)L0T^#}!kMsI1DbMsGn=KDGvHy|^l2qF+1vrfqLazRL7BOkxl3SiFq^ruo9*nPlgZ`|rQPAQYnCx~ z9jx7vvOBCHv+3j+qxhc+XzqR^uMdmwvGIruZbJgy|BYsTXuE}(+$^8wPJw0O6nqq)D=(7}NJz}-J` z_fOpYGjr!bdOa3`|1n%19_);-U65~FkZ)a(?_H1|oU+-Svk?F?GXv@>Ys?ycRut+^BV-whd*)G?9t@ITe-uy=ra+hZ&~Gt+0HdC;j_ zT689xiuiu%ER#;E!t3aQ744{Umee2|8Q}b=8Nv_h<*e zr1FhazQlend0=O=pA%8PiKYQ4o%0Ve`_?3-^to*I+b>f2F-hewqf*tZ`7HA}yjhD` z=5u(nmb2{V@I_|Xhi7YdZ{zN5-MyW=FY4}#x%=YozJ$BCxA*29%$+6U_nDc^CQP@V zP4piXn}OFk+3c@DwD{|uStdWl&v4mXZdRu6zSGAHnPHj|Rr9|~(k3<H zzv%8SyZbBd{;Ipb?(T28`&;h*w!6P;?wrm83CKSLayC;RIpiNZ?98@fO51(2ncCuK8raUZo73JPSagmp0E^AB1z-tx@8IrB zy8BY@-r3!karfoiz1rPZaQANRzOuWo;_i8OU)|kn-F+={XU-OxlNmXB^i=yu(nt1p zi)CSp%d;6)(5l=ZP%Tjwt8#-uv9wp^hJb30N?DcL29$r_zZvKZ-nqmc1pUaK5@D~3 zcRy?`2T(A1>bO03GgA9XZ!V?T+?JH-eY<K@q_oim2V6toE2wtI9nA%42#s!62J^oDvpl zy^ukyXN;4K`4^QZ6HKA@ic_nqdJB|&AOAKe`$qm9P^K4X_C6@n4K(|}QJm|Gpz$=D zHohcP&y(AK+|+5)_n16sbcyI$iUL{0Uo=yKSI3cAWOJ{Q*$+<8Ds(TAyhaJ0{3RdA zv$@xeK|j-36d$^Lz-ODiOWCmEGnb9~XW-dG_cT>6g5fIWKmNb#jUv>Xl+6J*9Q2v%5})a$MKR@+U(0&kl2UCY*2Rl&v6v}&7kF^ z857N}j=lYM!VwMV%$;Y*5zr9P!Q-b)Km6 zMO`3jJ}7H@p?DXGx>(dDqAnG687OOexp-HIx>D3tqOKNo4Jd1St$5dox?a=`qHYv* z6DVtYvv{|Nx>eL|qHY&e0A+3O5bsV=cZpgc>TXf@h`JY)^>Uwh3&p!%yaz-*DC!~U zJuKcM;yo(rF-ad6^@OBPiuaUwPmA}Ac+ZOWoOsWRdO^|`MZF~IW$C>l-m9Ws6ZN|E z-VpCiQE!QQTYB$^_pYe-M7=NS15qD>vKjwKypKhFBI;97pMkO#pNsc}s4qo*CB3i3 z`$p8aqP~;f_u~B^>PJyOiTW9oMevJwzl!=z)bG;!L%csl{Uz#e>1FQpH6kl2C#njR zjoVDT=Av3i+ETn$;w>UxYf)`PwH4J4l#Q{dc#DZzT+|Yx+Jmwd9mMM>YDrO@L@fo% zS}ZMIXHi{5EhB1KP}X8O@s<~_TD-2JRuHwK^ty?+l6WhNS0ic_QLBo|gR%%#6K{1< zYlx~9wI(QQv6gtwMvN5(2Z);K8h}u@vP*B!l zn0VWXH(b2!MeQJJM^Pg{SuZ<@x3j2SMC~eSH&E7MckxDw8YSr-;*Az>jCf;3?J4PA z;*Aq;Z}G;9njq;!@g|9yENY7M_7QKYc+0-qGS6Bi^y%9VhB|Q74Ex5tLo&lf*k& z)G4A)6?GaYYjL`GXNa07>P%5*fwC57i+7Hwb48se>U>cbfU>sp#k)|{MWQYibqOeI zajAHhiMm|W71Fy>ysJcAE$SLk*MhR1uM_Wj@oo_BM)7VE?`BcAh`LpJw~2SVsDh|F zq<5!ycZpgc>Tc=XBi_BD?i008diRU>fT#yWJtXR3PIqR#g0i+x ziTAXqXGA?Kz30SxUc48?dr`cXM7=EOE8@K>>NQDU7w--6-W2aG@!l5oj;MDGlXyRi z_ltPHiuz5|@6!82ygx<#CF*bKW$se{Cn_hZ3Y5)cGx3^>Y9Xqn^je9xh^W@0+DNah zc?qS}keW|3Mgx_s(5)(tBG1&)Ec0yMXh*iidsulcTsDDvKH%zx2~x5 zM6EBq4aD0}RGp|E((5T+FHswbs+Zoz;%y?Tx2Qg%`hv1Z`-!)ysLe$67qvMkYq5oR z14L~pYM`h=psdAU@rH=nO4QcU+eW-?MGX}-OnTdiH(b>AqIQtpj^d3FwUelwrMHWC zyNcRP)b7$7Dc&eidx#n>y)ojA6}6|Ry`(ozyuC$@7d1h86UCb(YO<&)(%VP8siLNd znl8N=;x&kxDd{Zn_7%0Cr2C6^fT-D`=7>5FlwJL~;vFRFU{QyNIuw+(I8405MI9mO zk>VXC-qGS6BkEXD$4T#a@lFtRqNtOkcd~e=h&ol$)5JSnyfeg`C+bW|&l2x!QRhf{ zu6XB(I$zQY#G5bbLP;+Y?_yDxNP4Mwmx;Pu(ksNfQq)zVu9n_4;$181I#Jh4?*{R1 z6m^rRo27S)c(;nWP1Nn83ZU$cxI?@-5cQ;_Pl@-msAohyE4}B$dtTHFlD;V3OQK#D^@{Xf74J1s zuZwy^dT)yNmZ-Nyy(7JM#d}ZG`=UOO-iP9SBHKN0U!QJ+crxp-fQ`cl%b#QR#j zZ^Zjnyzj*OUephwew5x%;{7b@7g4{8`VExbCBKXJhp0a#{Y$*RMP(MK{{v;c9r8ArKnb-7Li_S@!E)LE2^FJ78P$XQHzUOLR5QD7HJ3ZI*M9SR3}kOfwC4$ zi`Q9H7g5WIS{9VGSWdjm#bK zsD9GhRJ_eZ^%u3ds4YO*xC6x7Qq(|EgQPcDydk2t61BCcZ9rMi+ln_-)G$%oNpHA# z+l$&k)Q+M?fU=%<5^rZwyNKFVdb^3YyQq<(MoDiE@kWapBWkSl_7ra~@y3a_w|L{l zn;_mq@g|8kS-dIY?IYe)@urD4UA!6MHHbG;yjkMyE8c$M?JwQ|;>{Lsj(7)(H&?ua z#5-8LL&Q5&yu-vhT)ZR1J5tn9k{&JIG2$I7-f`j`FWw2FP84;L^iCG<6j7&2dYX8r zi+6^2^F*B~=~?2PE$SRe&lT@HQRho~fq3&pT`1{A;$1A>CE{Hw-euxlF6s(NuN3bp z@vatijilF#cb%x~CA~qs8%5nD>SpQPBI;IAw@L4I@d~2ukn~RR?h>^?(!0gGN4$H* zyHC7@;@vOa1L8d>-b3O&Eb0+S9~JL0QIAXdgm_PidP>yO(tAd{XGJ|H>UrtCAl{3j zUJ~`P^j;C~RZ*{rdR=;Ni1((bw?w@y>K#zFcD^g#d!pW#^aJre6!np$AB*>ic%O>* znW)c2eIdOs#rsOs*P^}=^{uGyKv~S+i}!=5A4UBn>Ss~EfU>r~iuaqS-$nf)y+6hK zOT53u%iQh#WkK1$7RiaKlC+t4%|*44w552hL@gq!wWv0rEc&+MwG*|dsKrDr4$4|A zAzph?9Yl4M-jd>V619}5rKQ(dye^`a5w)!JmJ@GzQPrZlN^b@6Rut7u)JoD@S-cui ztB6`vR34O_`D)^=E@}-?wW8JpWi8ecue+$VMXe*fb;Vmx)cTTcAl`O}Pr)f1GB z+e^HSMAeJhSbCd?*IQH{QGG@A17$sLD&A(I`b)aGcw2}!K)fx*8z|l&QG+ENBHmV_ zwidOG^tKgmsHkC*ZYSPwQQM2!L3%riH$v1-qIMRw3n-g|T}ACC>F(l<6mOJxdx$q$ zyfLE2irQ0pdx;t+>E7av7d1iBiQ-KXHCfUr;_V}9s-)Azn=WdGqz&TD6mOPz`--=p zc>9YwK+@Ub%@OZF@#cy;NYaDFJ4Do>k{%}B;i8U^^hoiJ67Oj7juG!z@s1Pkc=1jU z??mxV67OX3P7!sgq^F5@x~MZGohROzqRx`^Z1K(!b*`l6iFdxJ3q;MA-i6{_BrQ@pptdt1~yqTZF> zd*Zz>>H|?9iuwqY&ELo3eIn{pQJ+cgbMd|q^`)qHRF;FQR@G^_!^QMg0NF&h1a}{u1@KsLVaS>&t?&7CG^%L^TuDTvQ8DEkRk^R^lxp zsmjPAs9w_BNW6Mc8;jaRdcDQ#BdV{Y{lwc;)MldkOK)@W zwh%Qy)Rxj4DBd7ZgC!jz-d3Wv7PXD^wiR!vs9~bEliqOgwimU7q&tc?!cqJ(!BP0j z+{~t9_Q1EPqrV|{wE4-yBPi^HZ?=t@7X7s(e7%u^!2=@SLaR03>p6t{*!K*w*@MU} z{i;JYdmx!Z{WpW=T)Tn(5i>9uy4THk!q4OcqB{5K8-Q6qKcR z7vm@D#xBNAwJHaCTAen)Te(DCDXuhMk`R37K=(|FvQxN>F(5aM|O;-GF5l`hgQfFwh^=mv>CJow3SHq-3DztXa{H~XcuTVk?gw%+8?03pnahIpaVp*??GsXK!-s` zKu1Bxh-Ba6&`yB<1f2w(0-Xk(A(C4;3+)`V^UyAUE`lzh-DPN3pj`!BgL@rx1MW>| zx1imIb_d#BX!oG~1-cLS0qAegL$rGY?J?*d&=a(K3eC1!Rk0nU5y`AMpgBP~KsiCV zKp{l3?=#SHgYtm#g7Oi`9{Hg?3n~CAh<1gb6$U*ADuQ;;Lwf;K6jTgUoJfwK1hkT% zQlQdk7YfY<3In;(E*zQ%6agxOc9GD$pt5kwK`Rff0<Qe)u2@e)d0N=s!1e!yaMf2P%ThxP#q%Kqb{_1&|ZU9AJhQU5bYX4dmUP1XiY$G zfZhZ(C6Xg(2CX@$1*j#c6_M=G8d@7rTTnYtdr${ZMICWxdI!{nNcN3^ z))f>B>IRAf#e)(+-9bHw_xs{Kg4FF|>27*2&l061N8w?r(cPO-B(1t@B0U8PS6KJEL zeF|+f=rg!upp6BM1C2+!3D7==HWAt+&}7gTXg3AgRA|$nO^5a+v>DK5LYoDe4Vr^? zUxB`cI~UqF(B?t=7TSE!cc2Am_dT?Q(0+in2(%dVBWMYcoavvS{R~4&{ly~gVuo7g4PkqzU!fF0BrFW=mk(wv?~U!IJ6SbN`gv(N~2vUG#4lgw1n0Q)Ed+V)Rsv0 zXa}u5r~{}Y+PwwsZBQprXS90BhBgE=6f_L&hC>?x8VULY?M6ZS6f_$28QP73HWoAvG#>3HK>Hjt5i|+yCPVuI zGzIQdXwyK`;eH8i252T|7HBq+oc%e_z5;y>nhW}dNcNZq?OV`%xZgor0PTBd3qe1C z7NOl@Xg`9MfPO-|pP?-UEra_DwB^uNK>HQ+8{C!9eh00ByBgXW&|0|bpsfdOfV&ae zCeUWMTcB+PZG*cV+78f8&@Qyw4Q&tT571t;+Xrnw=m6*-+8u&+7<2@56m*P8R>W~= zCqRFKPJ&Jm$sVVnodKN%odcaGl07a!y9l}j_cF9ApsS#3Xm=gj4bV-vx1iky-2vT2 zyL-_70^NuE0NUT6hoDDj_ZZqgpeLZGXlGliuKMgC4dft_8FE6)0m=!=g?1s(o&n{C zn+IB6P(HZ%p*;&K0Jk8tLeL6Bdk$I=XwQRQ02M{MV$h0%N`Oj&N)gE%l!g`xa={IQ z<_3j>JZKjItqdp<`@n5JqBb*Y6xnCcCSNg3~B=R4QOwInu404U2|wH zKrP|6g4P<;2Gkbq+Cgg%tpl`G0?_B8wYJX zvw5iahL7NWkOK3Bo&4e}!+H7cZpnV1HYiM(!eFJSCv~Qu! zhxQ$40o?DQErj+1v_;SsL;Df51oRWy{S0j>Xc^pJpe={C0@|;j-{7u<_B&`5+||(5 zfY!oY2W>rQ1Kf?!HbL7AZ40!m(6)iL!`%UGC$wFl-Ej9n`vbHW?mlSyK?gtw(e4oF zFz5){9ffubbR6ypXn%rE!aW7;G_*6&&O$o}?L4##&@Mu|1nn~D3f!yEu7R$@y#ehe z=oaWU+TDS67jzHw7uwy2_5k!Z=pouYg7z5n59kTnJ%wglhwDF(267O|wbKbL2Ph}p zT+l*5&%n(MEf2K3(DH%ugPujZ0?-PA3V{lPo&yyjl4E`z+6$nfpkkonpb|u~Z%JsS zK&3&UXy<|!2F(pE9GVAO1gH$$NN8SAS-9n(l?PP-MS&_3$m6SNcN}- z?Iln(P<6Dc0qtc_P0%Z7_bRknpxU51Xjd0nJAH(CcW|7+Mq18=yBq zO^IaW&7d_0wE(pQwIY%|T0?6CY71(IcI}~c0Cj}>7PPlPoj{#I?-0rTc7YZH>I#ZQ zyKd0pK=GgiPq z5A;5$KiYi&?L*KvX(B^`^ zfjbY{x1jlOzk{{_+V{{FLi+*QB4~@D{RnLdw4b2;3~ecB8Qfo>EeEZD`zy5HKr7+? z4s8`^HQY7O)`Hf7)}!49Xd6MBK%3ES3$(4EZJ_OFw*%Tv&@Q;Uq3r?v0osdp`=IRy z9RM8!9U_v)+hJ%&Ku1BxK*xz>j}y@T1f2w(0-Xk(0i7k1TR8{qJm>=GBIpv4>~R^| z70^|<*PvYo-2mN0yIat1gYLk+3+*20FSz%iJpla;dWd$9pgjit1A2mXPode?t0?V6 z`s=?S2gr$bIiTePDgofnEnSCXzjxKzjr9Ca5W>8IkPK99j!dOSr9|wFb3;+ZI|oPh0kjWw%4fIR7ts5jgMLKLItdKANc5NJs z=FbX^W!d~$q0uY{|E$m#YzKT+$bVO#vupgU(5Iq{#b<@4v0?hG&=gh!J}czEhl%W3 ze^zLM*pKnELZ7i3{If!%*fxDuXbh|7&kBua+4{3WliBk7tdMWaK|U+AiaN*->8vIa zC9JIx#NX?;7TP+UxFA;&8xMJ#En9v(@K-hswP&-1+wIHQ(2D}!9lVUiCMg;IU;4!# zRMWqntl1Ln|&KX1^M(0dL zj#)%}U~^=Xi0S(VGqRGzw?@lh%1>z7KWC4IDn9In0LHUwTF7|#`RHrZrnAf6$>w(? z&~SesStQ-Llt`>Y&SgY-#Om`4kywYcjYM)vHi0&Swt%)Oa%@wiZ3pcD?NsF0rAXVY z$gxL}_J<Q8K(Z9C8Qd^Xx7zMtUtanLaFrM2_e;g6QaB+&;4={sui z?N@V^eTIE8eetHT~nFKe9s~QPpQM;Inp%*i)+@KI6AosD2Zr zA2ISvZ}F3+?h5HVF$ zleVuVrN+_M0&*(sHu{!qyZr!LrhxO&C+?21(;}@&O7~O_TmRG}RWO~+j5`Gc( z4BMv)_z*H?+;@>+{XF0ZwTWR$Il zqaZ%=-%^_PHmDP*Gw2;q7f_5MM^{B!EU23zN1P%pUXdd~k=9+2qlY4`Cn!-Tp0{$u zmJ7F+4a>?ZQL3*VYs znI+%%xcZN=qG(MKRjwAWDpyncsGr_1Ei=`$mrCphoF44*^bl}ja?)@7Klxw&ss7Jj zXWEyx!3R7~d2cxmdEVfYE?u)Z#3?zGomh)M>5$GwhSga-O>QhhUQf$Yc((i#11W4- z)=83bOm)(W9j*sl4)D3IAFK3v^vtXb{+kefCvggG1eq$dVcalLKP3i)HiR9k&<3$# z8QMU(F{{u9uw@zAhsrU9)}I|yXd_t-7TV`z$}iTQM8r!J&)<0NBJVlyS2=LmJ(f+Y z%kIzEps&zwp2`Ofu3JB4nM%%l;ceF@>Rl2uGU@Ms_)3|QK9ekQ0?}p@sgZrj9SkG0 zs~du8Y#K%;E)l1&VIJ9JmV=CJ7JE45;Yg=}eMgQ=+4n?hVBd24U<3PxO{;-@&4zhk zb65^Cum$Xy2PU36EG174Z5fdo+E3gg*wB7t(`smo*f0-mA<}{h|Ks!q$C+(ahF;yqIbFlI`!KPu9;*dMWhIy1nSPnAEGwfli{13Ss z**!MQBfGTtsSQPGaN8uzqT68b&52)5eB*WKV*Qj51Sz z`pC=_BvSj&&s#EN2K&#;rq%v)vtizU2+Nk4q5YR2Q|`YM5%1rjm6jyRx)^shj0Dy5 z0-J`Bi0UcAhIu4~S+*RBT`Q?~v6v$-S#pf!h*XZsaED+c^RQ_(GB+FMk-1n7GP1II z7mJZqB}{vp*cbzjl16MAVh~4Z12&8?yvCws40f#rdzt;x=<~7`|H5EqB#O~s8r+$5Xs4zW$<(r3Ca^=IJ9z-&k zJ&9y86N%(R_fq6|mq?~H36u;<(TS58LmV`j@33i=%uZ|=llc~lL6Vuko++8}tQvCE zU1%8r`R&G!+5iDJKqD1tpAd=pa*k4z<5SRRLG%aretCZ z0e=XtA2+j_*uHES9x924XMA5xhr|@}#nd`x5XotrNhGIn7Lk0kG@D2s9CIXT4(%(Y zIltD44}{6YLDM;rO{;WHV8fWsaV!Q&=a=lIC-ev`@Tsg?V>^tawvGv|h~ zvXC5^l_f+nD?bs*to%$Qv$B*(W@VWmdT_4&qBQ4noj5BCh=XQjKAToqna74PD|1;4 zl9eCXGiBumR;{wKSZqHqD~njO%*tAFnH{suh+Jpw%j{R4UedJ3{_R#~$XiQ;o;lIYbc2a$Y1#0fVCk<4>W zP%cmi=owIMP##cTP(Dz8(6gWdpn{-6pu(W%Kt({$gI)j?1r-Ao2bBPo1eF4n28DuL zpfHdd6b|x$B0yz8ksvRqET|l)Jg5RF3RDsFBB&CmGAJ5U1ymLE5|O;Js0OV%s0Qd| zP)*P)pjSb)K(#@2Ky^X&K(B%7gBpMuf*KLYihZ3(J(t-{wQXE3arwQIO~Z02F2A?4 zK`Ue6tM*%U)#~ZzA@*A1PuhyB?}Mxvuf7kk7?+xso*L)3^4Yb+thWo0_OfKP((Yp; zjsMoJ|Hb}(R_nL+7sWGvz9?@=DUpk6S0cHn#uCXzwHvfJr8(l2=173nok$++JwQD{ ziJ)GfcR@*@WKar`oU&9RxwND~dk^i>K^dS-P!^~+s1K+ws2`Es+xtXvZ~c{~eE|AU z5MR`O1Z@DcY|udI($&bvXg5faW3VFU5F(K^=TOiv&~VTQB6+BdBoePdYo7>`Px6}+ z2QB5MY+9A_8*G?Lxv{QVm2zkHIs}wfdzM-U{$1uatckZv;WZY%2efM)*)W!UJF$hp z<0FQ(z&G64wbpX8ey`l@7hCNhHV}A++LpCG>S{mWTD=onEdzphn%wYma$qLjVKFhjZ%lIFjfFh=_?0y}0w+)-c?3=;l1Jc|MDq4-29Z3nW`bsc zW-HR>5Xs8;N)SH@`x-PC^o>q@#W;>QXx)rq)2ePpvthhq9K~XgE5<48nQoe=vT7`b z$t)Tc%W13yu76*MW`R>ak+n8G`SFFJ>^>KclJUsdu1#ViL*91d*@&2vMdZjiSxF@4 zYu+d$hvJBZ}kwUbD$ z61(8;2JHd;K_uVDvKO>Z5?#vehju^^)sf>Mv_nL4q=!LAKu1M8?r}^Izlq_v)M(2m zp#4cCw{jA63UpevbDj~z+dHc?$2rh>K@QsT1xeKIBHT-Y_#L^IiR9j{fUbhBiFPzn z=XF86w;Q0F%5~flL~jXn+?FnF`3{lX@?Fq9&|jeYpa-D8iNq{89}43AJ`%+Hcq}#A z$3Lo_;|a8E{0p$keAriIb%u6Kq zmQQJp{HmSfSx^B`K~N!3VbF6#vWklk$t^#xH0KMdowF#Y7^pa?1gIpa6sR;P6yySh zf!v^QkOve&By&)PNRBj8X_^;QR*|EeBCWhmy!I}nISjh?E@0DY?VZnt>6|@JSFO(3 z%h?M&XaCHSX+8dtRl}KlDQm_xdWmQlc*0)BTHqS}lV}#WM*qf|^=WwpTY;zLU&R(O z1K+o^m_@78@-J){PRrsv>!kB6-oqk@&$=(sT*xQ;FB8cXz9x}8>%KxHkL*`LwLrBM zX?2LW8hA#diG$8)B{r>Qv?3d(8LgnJRx?_IJ;McsU8~Nj;mlc$HFK`S8LlyT@(kCU zNK~}e0@M=J3e;LBjKEUYH1nIpAp&Dbzh zghvEKqMrbZ^o}X3mc}HjbW88<&)?|MZe2=e%zjqAGi-9UzYs{B3bq$1@Xh< zPoRyG8eK$x3T-sB&y?mEqevSIcbw83<8|UB4kR`v5idm#VAGI9@p$$_HcUzEud7x` z9LAn$c^JZKGrx@3wV^B}c29~mJj5T)Ix{o*Le)(%?bD@2sG{-ze+P84$E6wp8Xn{_g&MCw}(>a+72omMLK7(ZcgWP(cC(ncE@b#(juqsWilzpKa(nRyqrkpcm?QJoj5y7h>h97 z!>z?^8nR>O4_W-chABJW>#9|Deqqmefv}WCMC^CJwTz8`$50g1dJ<(&TZm*(TS41E z+jZjb))EH|Z#A1%;r-5rDZJlw)hfKr>>0z`z@k-no7ga|NE=x-2ECs|8T2tC8T4_` z3DBRQlb};NaU%8-2TjBtHmwq|iw#pEcIc{AA`Y=Av|T&E znpM7zvSG^CL9q${RfdY>GKunP?G};D*KN=pLGoP{7m0&r_@tMYH7AZ|u z3AxUmAtBdTGgiwL7OkSc%0_IwA<)O9%0L}kRiI8#4xM=FA98=g%Y8V+AFyc^=wECY z1HH>)kU(v;OH)u!xPu}3r>q6u0{p|0Id+=Q{IpemEt3Pu%XYERI`2Vb~T9rvr_UO~7=69UiH5Yrvhn!(7 zQVsE^6|nT%wNhdqfpSS!XFW!&%ZE6&mzfz3(?EpT(CS))Byt`yKcRLTBZ zplp^SU9MmiiR2OaqE0-kUhZeeFv_zGn}!UFGmwW3)5_%5RjUj~v1dH!%Cl%LJiAtb z4a1TnZii}+A&8R(b6QnPL7HPw>go#rD*}JCA3!1T0?6Ctu3^6(Aq=m0Ij3a9B&cH z8|k+}oj{#I?|{01VnAI%v7m0CI8Zz&0n{DT1Jo0g2*`f#K|O9Q~#{fOkv-22e_qumFf4?!P+27t0b13@2y27v~HhJc2Gh7rk8 z4Tm-YG!pa)XcXvE&}h(SpfRAapmCt_pb12B1fLVhyi9~U2{ak>1!xLrDrg#LI_OK# z4A4x_EYNHsIhHxlz5;y>nhW{{G!OJGXg=sW&;ro+poO3xh~x+s5y@;UhWjIE3Fs%# z&!DBCWkhm&zd&0KS^@eM^c!d;=yxKyl~qJ?RIA~x0j&kC1FZ*b0Br|xk2s#8h3_1cj3OWWl4mtt)6Lb=E3UnHD26Ps5 z4s;%L0dx^`33M5B1#}g34RjrJ19TH~3v?TF2Xq&75A+x4KIj4HZ_q=~BhX{eKcFW> zvi_bDiTcxQ+mvP}k~OJ8a}ddMloON#loON-6asn%lpB->loyl_lppjgr~s%Ss1T?y z=s8dk(DR@dKt(~tK*d2Nh)Ub|Wu}tQN`Xp)LP0K27|0C@2YGbj>!gO1{h-%L_1Uz# zPO8U-=>o8hu3B9HzQLa1UgS-o1>S}>X3cz+WY?Oo(I@cDiA}`@{O`@wqb~W90$p20 zQLOUXsxpy$={*`$MJLWgdE%g%D9ff*CL-A|WgURPb>gUM5(kZ{2Aft z8LQ@4TCi-6mIbXhv_496^d*uDem~Irp#Go_Kp%oW0u2CV zg9d^=1`PrY1`PoX1q}lY2aN!Y1bqS;1^N^;8uS@x3}`H99B4df0_bzlM9?JAWY8C& zDWIvKX`tz#FF`XvGeNUJvq5t}UxB^`%>{h}ng{w8G@nRb7JLV70qA?sLeLMOMWDr? zA3;k%KY@M*Ed?zjk|X$qNM4vMhqgj#j$fhu23o1e`MV;=Dk53Mt3hi(YeDNk>p>ep z8$p{un?YMZTS41E+d(@(J3+fZyFq(Ee}MLa_JQ_;4uB4V4uKAXj)0DWj)9JYPJsRd zodlf%od%r&odul(od;b2T?AbMT?SnNT?JhulC^Oi+6~Z6&@Iqy&>hfS&^^#!p!-B} z9}kG+MeyIy9-`eN&|}a)peLZGAlr6TiFS|%a)6wm9H5*;a#XpXg@B#`v>Kq7K{Y|I zfL;aFB9dFFO~j+(%bR$rz@V2m-Pp9cyy?n@>GGzFu3BB*B(i6?#porpz*~$StXbV+ z^klX46qpMak z)r396OuZqrz?piJHS@)FW0tKZuqhjcOIdnzk=U|v3TfgJ$&eG5MkFWhJt8r2j&ve9 zT^XQEP!^~+s1K+ws2}KkP=6vhT^~UE5cCmf04N(Y5cDx<5NI%H2$9^!P$F3p!<42C z2aN!Y6vS@^{zTXK;O#*iv?LPPv?_@>HcTZEtE*Ne@h*FYl1LI-U`ZsiW-f_dEL)XC z3LB=9NEKVQD2WMV$dZ^sBoe4i1x*7@SLFCokv0P~6Eq7nTajaqPMqFx#6iNK=vUBhpp}Xozbn#KfmVaofYvH8jNf zEM(6x1wRNaa0-58&0OK%vurgpi`g*F%pw*|Wxs^gfH%45Co_KIEx$c%J2jB=wueZr zh<^~tQ`uf3IhXqsIrf7NfDRJLmGcnjFz5*AD3M&FjzK#PIsy6I++oA`+WajRDL`{5v`=k^Z=W{ep!<9hY@d&<_WAHX?K6+xKA-td z`^?3rRh&84FvjU%F<6|>k*RW9h#LmWZ2>l|_L-jz<397U7;K-V$dvUOPE^Ro&z(I) za;1nMk~LgLks}i1C6enySx`B+<%#6=N(H59Q9ALFP=eSPA>Oi5j7>v?;w>vLuwgn9 zis-7jeC%2%dxrJeCA7fxx-@H6M@JYNsq{fNzqk3g#RmM34SnUUMuyC1O(MDSzCtAP z`6`iI_i7Qz?9?WbS*)WIXQwK0(CkFBX_cKyY>4a(=D!w61Ga_P?G<&^DmyjUiw}7B zwq1LfMdJclokeqg?xt*f3UZT^55?ZYwg?K3j0ZVEb&w zrqw>*WW%`6CM*Wq=i6keeRkxA!S>mnO{;yjWy847)+`3wXB?TbqIwX?qp_z>Tq&{K z*)R?qM=@*~#vzWQci1qFqZ5mk=_QD?m`PZjN(}{mkBN7?~x;4G|3|3KzR76 z+&L- zHjJb0&0>&I4`45F)Rf5Kq^f}o)N z`<%VNwA!`tEEm`$0uk%rH{^*dIes7#tG{Crk<8L!Xg?}VTcR}WCulzt ziF`Si5{bMzmw|o(EeEXt{R;XGw30|>{dXd{L? z6SU2e=tHtwh~!qbDp%X46VLY7#6f3!4x3i9J&O&R*ub|1&(Kw?bKHFP44<`Jz*_eN zdaH1Hg6W%Ez7rh+-}bqXwVtsV?W^X7tuB%oxb&x$nO&w(|SWO*f)41jw5L*c>wBxK<7TPi0 zF%;S%mIFTuu%9KX+B?Dq)t=wQY(UvLcdD|>OC-xKACWA({Lr3NnpQw*T0v-qh-7gT zCX!|M9HqM%}+;zY9SN)X8{mxNmiR2mdYB+JC5G)EZ7O(csg9GVAOgd{4q zGDLDKk;>J)I&raS#6gSA#->%VJ>fYp729K7wJNq;yeUJmJ;PeCVhdr@SZq1PRsxGH z4{MgimRolW#g>C*b7ch-QDtf)*REvtgQ$vbt(DAywHkOvp>D8FOAmGz`pnG;7u=q=ml; zxiWbziDdFx5y|AWR+`oZT3aHS&~`*Jq3uB(KpjDE5y`rKTWO9?pw2|{=y(V1x+qPH zQRL_fiq(my;C14lQ_zr2t0}0@hG`1w>8jNfyvd$n3YxPP?3ifArkEeUPx`cA(X#%V zvJ<$fzQL09#OZhcy{H9WnLD&3B3YlwiX16AahiG(8`Fdvi0*6}(j;ym;@L1>>2_n0 za%av`K6=;byX*#rO;y&1R8eJGe9{(V2A8h;s*|Zw}05*){|B%HX;~&nR zas0zrG>m^JYnJ05M~*C+2}E)xJ_k+IiDMc=Y>WvdGn!39Orm5)v0;p9B#S{}8qc1o zU}lgi3uX?HSeCS}h~%>LHMF@(b9_T279+%_CNnmFjJ{LZG;to+6XO@KHN<6CrA z=&E_)v}+sKGn`&F3N7$tzMi!tsz|UnLA4yG;^ofw94E`HjMRrg2f>9e2G0{Jzr$e zP|p`wGv`P=M|nt|dcyU9+ZmQ}EPH>kX&ARy_U^JFX59Zt_-$Ran(;^M1rD5M#JNk& zNC=T!C7w~_$PLP)NXx6pkxwVizD8_}0;`FQO+yr7HF;tg#pC}FMGoGSRaWheoNTp@ z_kWtj7YMn8?5|ST&y%Po;5lv(Yyt|gX&AbgfC6loCLq7AT1~(U>?H>NjSjn3lvU%O zO`#EnkuJ~s5kx#OoaRt&Z5S)kT#8M@SVfvkuwhyris`D=Si{*fyu9jW&769>=3yf? z;HH}bs7R_xaRqK+7&dCW9Giw=ixhj=Fdmy_SPXJ(R%Orl8Tgl2q`EhJ2EK~ePT+^u zqlM=G(RBI_Kh`K}zZb_Uv1IrRd}X2eZ;nz>n?yN>b%^A_RacV6v-v7_3YM0dY+9wI z1{=n-RAbRHEi{fMWXff?8Ic@Eb5IMNcto!g8%KotYRINxM54axvtg>Qdb(;=UvIK! zSTLIk&Hq59Kdr@@x#lRQj^xM-f-Xezf*^)SUJ!I8l5xgL(j3liMB=pJj3bg43Gtu= zMOt?v*|&#IoSF8-K{L~qO{>hbX2X=3mbz+{nYY>NmYx}#-Xp>PZ%)~@x7ab~!mf2< z!}Mne?2gW?2d?;b$2%<2cT@OPbUyx5R%xV*>vTsZk<4cnk<4d5BAJu-6*>D8$t->V z`VjPyPMo_GVq@-b_$RSx$elR+d$D1x^PVhP*127KkG;6ebpLO5=QBVC>&85!v)HX) zrvEo|@bhWAqpwx--YjONq^AbViK7q8fg$sFz$Uei^2B(6Pa>3{Dnv!zRQW^;rlC*JbZssp<&48$cUDn?RdETR>Yu+la*YoZE@SBJJ1#Z6|1#q8z(Hdj!$@dUE_B zNps}bD_wfTy-#n)mGC2R(79N|rqx_5WWzWY3s|(A3%m9+dswIG>?!}^-BOktS-v92 ztIjfgH%(Lf1T4+@oOb65_L>ELK}xlMxt}DGvwTXC<22}uApQf#XC;ZF z<0x^^oE&D;DklfoFy>@Gi$QX7g1y#$f!Vb`S!&ZSqnV$o-|Sx_ONMltNQQI=bQg3_ zC!X9Z#Ku5y<#LHlLm=YH=_GHmvgC;KqhL*fpEjg#YVzl$$~%%G?wslJ!tb5@n<~v=X3_pi(+4O4D%>#9|5o@dWcBQLOKxCqgTh=zd)E6kcz!k%NpkT6P48IomkqKIU2 zDoUc{ya=rls4^%TR7EFFlZQBHn%rz!rOCyHDNUty)hbQp*)yc60&B)Jl@kpE(^OVy zfp-g$tXZYb%Z531uaYcN_ZpE*U42QEx(3i1f*OHd*NGEWlQ?L?YOraQuxf0W5>{1L ztrAw3Jww9kv1UwI9nml_VYOJZN=|Jy%*km; zpvh^W$sO=QpTjG&j$0+0G0 zteHQElEAXnl=fsJF(p2suiur2UF*)W=|ckVvTFP&g!mYWxN9Cowyc8*M6wP(Cz5qA zQE84z&?XbfI{1P}*1;4aSqD?0O@lTa^d;OGN^{OsnsXLtHj%7@IjWuGD@EGZpt*`1 z-+<;Ra(=5wo39hk{z&4Wvp<|otJxpQhH3T(>#Ei4k7ds=`{RTbIQyTmW}f{|S+<(} zF>IJ;e>BUc*&okp@Y!ENww(Rnh~(_AB$BiLJCU5}RYY>8R};yZUIT3{v~{5Ma5q5P z2->7b+YH(Q+N#L0O_8=8v_p|&Cuo-<=Wa#X9?%~;@$4@q4m$fkuxT~>-?L$w{qJRpB7r+!XB&d`kXK6)RD98m0(}_#tDJLe_UFSb+T9w8l zHcX}Qx2{^1MlRZ?u{1)27FZfi*36}$v20ZuIoL3lMouXQmWG2xQ)xWIYOvBMN2XjC zsu0Q2s7fSD<0T?l8r6toX;deYrBMUg%g}0qUV-~6v|5U^+KL=?6lrxq^%OZ?1JzgL zY@kSM2xJ=FLBVxFT;TUYEB%qteUcERaS4XVJfS}x@uKc?b$PwRR^I3mQ@?p%w^SzWvjAk%Z9nE+DSRE ztXi{ZDyxpH8q3Oe^D%&ISy;n~WMPdUl7%%=X^u~zjUtlM|0$6ytkFcWus(w}2HIHA zIORIWgC>AJCz4y9NF)nuk|M`sMcNmjDT*9ZLDLjDrz_IF1kC`=1kKWk3+6-Opas*P zO{;?G$A+n3`sk`v!3<%~P%uM<7FaMJvt}-sY?iGGW)K_Zf*CC3z=9dbqN!kpu^PN! z=94W8W)YE`q{V{x>xzDawgmJO=x5MUojB$5h=ZnlE}K><|B4M$%4h4URmvBzXLz`? zP-uZE|6aE9e__zBeaE6z!hc}H{BUO#$udnFh-8{J3gR?vg0>m71+*2kO(#y%O5&ht z`jt(qG%aVtl%{36YL%un>>1LuPH2H?S}WTHrfD^cR%u$#hB;09NR}^n9wL%yI;;~1 z{Rek5Tod9||J`gFf)=m(?_|Ri^mbjf3i=>>$$_tq*|q(wA{x93cYtL>EaGLf(`3j= zze*(k0Pi(H^sS%TbxHKb_Zy&_pj)8ZI&u6biH-5&m6#K38sZnPNF8It6#o%jwTk~D zdx77{c$OtY9h?_h;A78AtOb4u;0jCDU#fVSt-vo;JSR44_)^6)EF$%OFMVBLBR25e zq4WyIBa&t6bNr!FpHmR0K9?j)eF*3oP;Q+#;eYey4F!jU-)GY*;rG}uCH#)AS|!|0 z`!po{A8u|)_*0<;CS2pLfeClAWSwvaTY(9GB6k#chsR&AQ>tGR-WYa2w;%pdS%r43zg=G~$7<)*!zO>Mw%9AeZxH6Gk z5Tij=BvD0Ih4vDt8mPKXJSAm`jRB#eBiS?rB$ki}HcV3zuB%oNMX_fn-xq}zSiTiy zyTCcBz#`J&ceqz#!?4y;n(C4))ATx#{F{S~1=;B!ZvuJ)^rlXnlG?;UQ}QaCRw=2; zhAAaAbk!;)_1QDNbo3gF?E}xH^;okCzmaI{|5CPHYrtBZ;e*k3ts%<+e}YAvliHFj zGu4SmW~#Fw&eS`gE}$5lI8&{OgJ!BFn^u`>&W0&dO?A~OQythdW~x1lhD^0%%_>uG zi^hSO>d2ZoQ*W_s&Qwp5Wu{Vyk5eMpW>(qJN)q#>Z8pkX?3 z8u}9lO+!C6tg(bZ`TINmVryqM=Y9Swrc~~hzqC} zyEcHu`T_55&zaYjoBp7X(`K{fNhwmKdg2>3J5;Gxf5MKvqq@5~)uZ;dhBZ51nzj7G z)PDoeB^_X_u7_xA85?lbP6-HXF_xsSU4a32ca z?>-QI(*2kFqWgOICHFRrhw!HTOQxb@zmb8}6r`o9@98x7-iHZ@UkB z?zoqE?z$Iv?z=~a4-H@G85@4WGbenFXI}Vt&%*Gbp3C7sd#;9W_S_1;<{9ky)HBob zx93~WqKL(wqn<6E)e(Csb`Vot>Vh_51kj93H;q zBcDbNE<3zz_8m&AqhMiISa_wh%&b9qXXc%icTV0#d2i;umG^GmdwH{616_kCB|}`p zT*F->C^chTV<}0WyC%9OyQaEkxMsR$xn{fOxW0DHb zrE8UIwQG%Qool0OlWVhUt81HUhij*6w`;F!pX-3@uaaCoYs1!s9SJ)fb~Efj*rTwgVME-* z-6Py1-JiHexj%J}c7Nucn|q~u zm3y^&y?cXulY6s!t9zS!hkK`cmwOLQ^FH@}_d)j|_hFj!WA2mgQ&a?J-REf1FS#$f zueh(eueqK+t6geG}-_{i{4;iJRHgpUpXJbY64 z@*455F0HEBrxtHkHay&oIwODwwgJ@t#SZ zFFaE{(>*h&eCBw*^30##lS>pNGv&^%?^Q&j2XN_l_XT4`L71nmoPS0-7 z9?w3{0ncG7wG*B{J*PZpJm)-A)}AY#Yo6<#o1VL#d!GALkdHi%Jx@IYBL+tdjTlZP zH!@;W#OR1IRCE)l{3b_CiI_&kHzQ&emERmHy}1$dBIZXdh*%i0h|2J%h^17D%c)3L zQaP@sB3&P`F=8{7<+g|&5xXMxMC_%4Js5E~;wY8raVpW1RH$dEcrQ}X-i&w@kzHnB znc-zdl=-2|<}zE#94T|O%x95PBlkxhh&&W|B=TtFvB*CoPeq=NJQH~?@_gjQ$V-t| zBCkeXkGv6iGxApCoyfb9e?>ls{5$et9`qja9`+vb9`zpgp78$ZJ?TB=J?%Z?J?lN^J@38Xz39E< zz3jc}z2?2{z2Uv-z2&{_z2m*>z32VQd*A!O`?vR@_mTIp_aE;Q?^ADf*@0z0E<32~ z;Ic#M054`MZhJm^av_`T*}8G5$!Qf65(Kf2mN%| zznE!kB-$jVh&Fs0aM*tf%_V;G{Sa;FZ6o|I2mRk+Z}>rO@tg05Xp_-T2suTYslzPy zMN2>b<9#^nF}%5ee>{fVFIJAORN3YGSGjtnm!oS`s$41Br!iHoRH<6EYA#oe=t?hD z5>{6l*VCtVTl~=OpPWjl@nlKfuMdCMY{Aq6OWkGKtnF5pp8n>|Wn-^G9e!dg|M@4J z6;5{r; zr%wR8D}J`w+6HT8T58Klxf}K$`wwbR42Ey$qrBPhLiAf3RHQfzr zc5a!T+9N$S+0}@Y441cWjcR2(H%p95Pt8c}p6P0zn2{BmenWpgN&h=B1 zle1D1Gy8RJU%zwP)YPPm&du5oR<2qx`sIpMDpjshrE|B$l+KM)Gcr5Ys3tBK;-V|Y zCndRE&(X-D_&bZ@6O(LF-T6vn*Y)+QOxGR8>k@UDp{_$>)8l$}u2+wK(zS^G-)5=t zSxE^M<7`p!sTsDYw-aqq9c)!>Q5o?`WF^?5TJ)g*XVU+>McbkpHl{Ys+S;OCZ$tm@ zXNzi-nAxIRuSQw)2bXnj5StlGoce#fTvB6?$)K;hO$@wz3LJWBw_dcr`2XYnf?l3Q zC8VdPrl%*QrKV@rOiQOC$g~w~RH}Hls`f)2XkwzNWD1wcUYlimj*6TA6>Xo7Rx~Pg z{+XSF?$_zR<;BkmQVWq_Fszm?ooE4Xz**PwiR>ky8$_!OkOk8S8_rx9*d)f-vkL()L|47R>9_5L@SJPAe z$oWEP|8B#5#FoV-SGBDEO8s|o|D(NhympTDv-=cE{qHvE+tQj@kJi`zu;Ij~i~3)n z?&bCV{i%O+s4b><_dfb==>ux^98PXmly>+jLvvbm+P|=QOkJB(%P4Ix9BR+sFrZIH zOkl6k-0L`<@v>i}uD+h7sb|N4o@s`jpK;G5I=^IxPwZ6^rL6S!xd z3iM-jVVlhpu+y#qJ$>onexGx{vve-XzDw(M5z)`yILw~E7j>c-)&6|FDpRkC+-q?~ z`Z2nQ&GsDka@xC6uTcTJ@(+)9Hi^6CtV}=7Kkq-t6BOQ80X_XEpLErA{V_sLzSaM!eI^dm1-f!L?$%KN1RqkSBfma% zo59^uJJFA4sBnBo;zN%;e+B<;{`=#OGr8lF&h+DSK*t;r_WX7HJNi!rcbvr?KkY(4 zex;)G?XduLELMgGYMcq~HJf{_Pp2QHs-qVrra&1Qr(ZAQFz0Z;HktI}FY4zz^10tF z?w65b%F7$HzpuDo$B*g9{#yPA{z~fi*uNjv(YL7A*W4>*5d9cg8^_Wu>XIwchCK!J zn9Dt?52hc_)UnwjWTDV1!TTv3$>TE(uRZPP8}8O*2>qBt-SmT&cT~>5kAE^asCnFL z|4{nzL0$hNZ!2|t&A+4noN>o*x#Pm&^kY#y|BmOWV`tG(Wzm0^Eve^x?m28E{W$xY z|0;NxdJYgh<4ggzp?=?SzjmL}kLwNm4_MC2n1Fu%W96O;xM#l4=*NPF{yllDlLLEV zCOT8U@3~*`G4!KMBf3=Qnb7QGBJKIV4hYbHvF6k)%2UH#&YgP zy?)?c4d&91X>`c?%5sI*p8udguVj?7^{NIlkdu;~}FF+Gw}yV0ddBHbT|zBX#Tht58S!wEu{(2s|7soA0@ z^|j|-(%$}d2YX@%ds+v3zYg{R9qdCp*gxrDAJf6Us)IfMR^Mjj)eW||m$rC>x2Vxw zQ+8FlB`VaFM`H`IJ*?8KNy|1dtsA}`Q@M&Q`v{GDsGY7vp0(w%4J{fI!*e3frG;ZR*hZiZnd%pN;_-!mVS(E(xRrWJ0+MGFP zDaB=Wa&l^lZz1PN7LSXw>(G!lx#((f1(lAWwX6s{fB+*}apoz~&iAjvN zeVmJ~%3M^I6x3##sXVqx?S+?|l8{Wn<}9QKo5wfkDwX`k?6Nrr_%@xM&?6=#HaUSV zZ=E5$-7jdnn`pbvG+!gJ0EnmZYVQ-M)qOYby-rbnhY{zQI#I6PtktGvz1Hj-38?&%-+&8J$ER)MGGgd1ivpZ2XETrO zhK2S%PkVEUM@;+_*)+s9(U*(HP5hG)McYm+N86_3ASUD8#I$(6HKiJpgUVw|2yTYh zZuv%B)o;K#X`>&NZq%eHEpMt?op1ZnDUM;0N%D`-7;l78z7u^7Xudhy=~;1n>p_1} z*=gsgnM6%jP}4lNN9~){Z`re7M(czgHXA7F_fxh(B~Z^39VW8`2$Y))T~X#Wny zs6$AHX7wqYM1D1-eo|}(FCGU}6#r1XLCg?aM)`WJn~8dB{jx3lfvUGRX`_R=98^b? z#W!j^_kHtM*}p3CQgk-oSS! zNp!9>=Ucy?K-)&tcArT2#)=eZwW=c2j?pxz(<)Xw4eF`ip!^rG=O_;a{F2)sAtR1* zdr0N>nV?>XEgGq9+S)I*ye3vFSHDe6iF0e5&}%Hx&QW<)M+} z6NSf5jcnPEX!!ImkL?NdA??mAKWAR&O8y6qGL2TN`sEw zmDjhaD*mU#FxpLTzkE@mk+0^Iukr2qNNv)#4Lz^R;sd;%T4u)tbwd5hvq?(#RO;19 zm2SbHp7Wu{bR6pUSBQsKvJ(_f9$RGj*!1KW$~JAB2TcF$w%-4%xzw+XgG^=~+xm*M zX*y=*#`%Dye<8LzzH;dA$vHtT1=6?Z{K9|QgO<~+t++E6zxAl zFW8))`07hsH<-@;Td2H3Y&YA|@!ha>>zEdA%5$zby4fk_+jhPB{u{4IqwgaQiOSXZ znBWsrh^?r9bN|ANBJ)OB+6%8BG4!X`#DXAp<0LCrtG3PBREe%szgpFfV##Y*pVpwK z6ryO7!{$66JSV=TmUD8Ja^fsZ54;R3vwGNulE_7k&x-_3d(m&LtxR)-we}!InO;^M z_h}TP^C~@{Fl<_XT!AfDr7d5eE$6Y>TV*C^P+W1o674gJU@x-YE<-C>HP+i*ej!nwq_4sSqJj7Pqf6Dw<%NJ<} z9gFskjY*>OH1$Z!DFz;5%k(?yX^wH!H>HWZi8-!DS4q6+iwWdf@7}&8y_V6EAG9W< ziwlvNYRLUWA<>aT`=Ow@R(w(WkBMugg#Up3uPpddq)U7M9el2W+~j{Y&utr;~ zf`D4q_lt*5VVA2UC#GfSQ^(f@^v^kvAO6PjJrLcd#B}EuJH!<=C8-28x#Z%hceiiT zCNn)Dmao&hsHHE|EIK{r#l5?H9EF17QoSs;`cBb4aXn*2`s5LJ&6gEgQq`WIrm z?c16EwSF$Lp7Bj)wEu-nX`7RlYx99-S_VUDC)ZuPmt20E@?U35+MK0>F9$Kc6_vAm zgEp1N_L={sWIb_G76tpgtS4tb-?5uUH60^Hm5`1T_Y7+Hr8s)8`$G4h0={s{;Wu9Y zJBs2qXW9QSUf(3}cyEf(3mBKrCT;we&-@h9t7-w@*A1y8`5KP?<*`Lu8zHvo0jnZa z367aVH2R!=qxYZG66EFf^Zc&~L&n7ZS@}LZ{RmI`Y_pn&b^3rb4@md<6kQqxa zwA!+JtL^Q!mivljtV%R*K1(F`ar;DC?D$P#)crkqJmj%$EKggdO9j%x)ylBKLfgf= zNlwkE_EO)z)V6|ZyETZup$)Z9=*`=$uG+4#(8`EQpx*RWiqv$z2aeHe;sw>|emTBI zic8Dj>vZK7Q|@Wu^7VJO*!1*7s(X4UrOXksYaD5%l=eAIREspq1HCiRmc3nNae}qn zr>!1xOe}pefUbwt-GWzbZ(&u=3$4qvwWdn^&Pwc9gIcE1AGfq+w^a>WTWB3x^A@Ys zsKj}GOSNocsdkN)ZQrG)ajI!&EAiHg)KXj$Qq!KQ=@m=$iAs6*q}U!R~<$86{ zqYK(pKP7)-Emy2V`_1T=@jkU3pxTzR5}UN7mVNmJWNJECHEm?6X7P29JV*1|k;m3b zPox~wDAl{MwH#lI2gRoc+SLTrIL1#`#LG5kya{t|vi1 zI)|zbTl@}xxvfRYS{K~9sGpnTIRB$nhbqxj_4MY|w3u$`G4Y8RTwXsav(kSu%c^>k zLs+glxr6AhtGSCy=Y#B5)xLfZ{ZVBxGMU6#s&zM!ly3Z_sio59)aF{}81zj2q@3I0 zpvp+dOh}1WW*=ovY(n!NlaY}SBT{ls&Fg%%kjTJRtM+q(=Q%y5fO`B>lvS;@8ZDI#Uml%SPL-feKT(~&=qsr%TchNo6LBaeD0OyKarcD`pH;?; zU`ALSwHC-(Kd*X}3}#%$=~(7{v^rw;1v5&>P05vMsoKGpa!69u?-cXc_N##9a5|~h zyMpMA^+!m(WBKByzZ%N|Jv|wip#jRO=}UG(UtS6>s(n-s>h!=RmK^Rv)n%|4R$ofE zn20lKCk3O$Vr;k|o2R->lPj?3(_e|V1J92#yUEJE`XAl37@)6K7O1Y#zPJ+O`CM{Y zIpu;nt@J}u#;f0%=CNgnc%^ts1)IUgm3*qjQXX3k{UDI-rm4NXA(Il9mKCEfOS_a+ z);AFSusN)(D=mH343ran#pgFgi+!E>&-QXLU|!xuvM;DHx07R$FVD$4yd7$jEmTeM zvt?WMhpNvf*jBeV`d|uKRaBQ(^)B?em00?V=(gOF6vmzEtf|Ru_F&`n`lKlTm7up?V@^>W`{Udta2x1@c!*IlF>7e;6{WPfRb> zbEn=@?n-}po5z-};Oa|8M_Vgl0R7 z&dhG%%6?*NQ6*pZLM1~S5xKIzBR}7suXoQP+h--NT;xWvF zT+7Q5k7XX{qLi%^Im&*XdN-{!{NwO;^#7*yc#Acwgz^xo(N08A{Oi98>NOcuO%)XX zPC?bAplXChRSS)(iiqlyMbXNLig83Wd=XWl;perrDeXTU^?ie1UXMnp zrlXD=y_k+#a`gZ6bTkq{wV|Dep!nB+6;v#3fns?}#6rNoQ&7z)s5e8SnuJEZj)=OE zMbY|A$D6*0{HLRd3`k7J>oOp}>1ZxS9!DD!Bj;cL)yUIn3pC(FF<=7zokre~M&3R& zs%>ag>(Ho{7<>k~Wy<y- zTcB9_idYEvcM7U21=S@qs&i=6+lXi&Sro0`bae4WMvKpMrP)yExKB9Mfs*A`brbU&Zk)ZGnbAOAMcYf2TP5QXIWQ zqcTII(h&-O&?)fX?(GX@d8Xf-r2luZ^b@gsN1GS1@UQdAv9`S zXw(>la#l7yC;xMv{=-XA_Hnuvt^08<$MOksR)*U~xXOGHO4n7>T}|JlO4a>(6(*>GX<)Ud^t7>+u z`>XT&^SYy^>iNu5&+~q&t9yEemiEDDIT+p8jVu#@wsYMM-u#TF9MFwCw*^&~xs96@ zK)*m~tZV`3W(i1LCM6&2jJ8a}=U3|MW<8(ZU^7=rJ}VfXofu_&XtyFh^q(Dp5B-O} zj1TRD&%eRvj&9`kZe+DUv?rJD#hdnM$`Rdxl<3t6T|?^>L>-_s?(SB;yRDOm%+ed# z8oHfxW{g&A80}4+t=V|XkUynMzmWIqrbre7l2TeJmr;w7hhMrdt^@Y-S zu3PzT{JcbDmfpzL&=Z_9WAvDYQ9tVJc|D_}U^AbSjGkqT`eT$aqTPxZMc@I92BKk% zXdjGT1*4a{k<9{7ln#9nk$}`SRPw?2Y}W8eQeRv2 zd{VHPuS-6!F+ORGGCs6h5ucOb0etdk7$4dPpAW$2y>8?k!Dlen4dKnnXv+D#hkUFB z^s&O{6ex|4TI|ywOFm}ljcftE!y!{Z&e!kOnQbWb{;{6eKVUOIlEgk_#D-y%5u@FT zh>d{<5IY?WBS!lm_Bn|CPv9EMMdNrg9!)u}|0&C9tAgtcD2*>$;Myv2smrP4-%oxTLEkq*Zq?>v(c0T z`(9aJI}~95g3{RDVh`UTftjT@vi0@tUtM2wsP`RuVrRi-ZkNPI@f%_V5cas8&OuPS=Ku5?{_DU`;p7PzY1;>Mr4zDhp+ z{QA0#IR zo49T{Z&siw2e!Lg?q3}gU@M_C+Plk7fE^?-v-C!`zS_YF?v(y{VmDLo9rVO*fz531 z7FXtbxoM)eVw4f1-HM3a1rKnv1`Q)d`yjSIh;iR1A`17>xqs}|)X|0FNJV4Uw#Aw}*QAUe)E28x(Jb>17Xc#Tp2Q30x zN4QCMHwn0jUtoI;R-?wP+*Ch8=5BT`tucC2Jx~HjZ>sz8+PbMe)9I#qPnOghn1m%o zyA>t%2|OUFcUUfXLHkImFOsTvliqG}q{!&MFd zMgA$AvB+t+qR7982L${D3m7kGACU(U`LS*?&`k!oNq-Ui53rV(<5(HIIS^6OOBPy= z0X%wk7q>r;p54W5U557znxp448aDG^lFw|$XADLeAKI;mPa`~l&lzYK zAKC|>1>iH^P3F1DxdKrWmp1ce8k%xM^O2JEk$sVZXgZX}LU;L*v`8W{OK)UrXddUx z7@ezOG=n-@q-Qh}Hgln5bRlCj3!{t??N-ESK0JWY*=QIe+6SX6!RT@~xl{nUfa@0U z=0Y^(fG+2`u{Cs+0%#$W#*!9*u9AS%HB|D!_*|;tvxxe-O3#NriO*aj`7CC9F2*S1 zL%S96xfUM4=Snn;5AB1`jo`D)O|BDsuH(Avd9w^nIiF?7$67!u6h1dVX)JGXjIEG- z%+ed#0=kYvrhuH!^VU6|8>#mddSW-hW-gb+ZeqliW0Vo2-HM3a4i6x93mQg@_CahF zh}|l1t>vOScylM3a$I;kFa31LmecJDu75*mtZ9Mkc8N<}P9-0Ip4MH|`R#gIcf)3` zk+fDbTI(>%Xwhy(v^K&6Xst)XXwg1s-3wal+~h6+>|w5Zgg1|(DF?PrSzq@nz&1f? ztZ#Ar-7kTer8lzmb=O~AUyo7m_v?v04x71N61$HPdjg}380}U>>_6}TV$Y#r#AqMH zHiFm&f$L>1dWAQyqAAC{5c(&^0Tgdk>gXtyFdMR)+6I2uNW_Cd!3I^8^^tA`xwAqRWNK?2S3 z5C9(kjNP4b=_a|ThfG(Fg|aaZ%k=FnZ>F*)^Jfx3E>I_(MobaT2(4+?Flj@J*^Z1=iv!4g+|0I@E9}Iuj z0Uyvs9s^k(XTmSbgLW&*<2-mk__J8}ctQKfBZ)lX9uoDCu!jUaQcxMAYkdr-Ru*hXK1m(G$CUY@|AyDfU(NHCs zla*u!w@PLNOJ)r`vt($uqGTR`2juW?mIGeUK9V^D$&B-mF&@(3AtOa5Cag$QsmeGd zlQBvr4KfpYCfUW0wvny!IFse^ApEjCXt$y~o`wg6{|E~oFK8cmG$D_v9x~ZOCW<7U zfvG%+sWJ(5X-(GVFtJq*%`As!;g;n z(s&cr@>MlQpT=yNhB-@FR5My7GM6Rt796ugXt$z7K8FXy|2~T!FK8c$T!cgxddLC~ zneQR(2B|^IuCDNrGOJpB3ED_pAA~z$E6&`Yvhuq*H*L%pd zBA0_9FmCl2zp8~@A=5E$LabI{Z{Yc`!d@>6do54rPZhQ+<}+_?RaibE3wsOWaTvsm z2klnGqX#^ous$@52knE$zro`U54qh#R(r^80tSH!4{V(>t!P5y@=8( z={lYXEh+oNK(9bbncCEoo-L~Rw^8!S8dI7NwyG*0kySMrj1a^O2JKb^BL@#)5J$tR zO8bEEC}2G7ArA=>d5i-Quji5U+Vf$FL9ORQvYw@j^0v2XI>d5avAC%y&Hqihuln zhcTLmQO1aND`Ip7JOIswXjnOEAB?^Lqt86#QxEyXLp~CiuH@>)yjg;#9MfkCrfmwQ ztDrQtddjb)wkeoOZ)BK0RWN;`Y|I~NkS(Q-x9O2x4V$@DBKwjdy9T2S8SPet>=t+c zvK!DaWV8=tKLXkJ9`db#bt~81#+y}W%3*!a^JF)6cPOw{LuqVpv8HxNSn9!3^1)7G z-)i`*p}uzL`P>ehxn1)4iSb#BQO1XME8=6q1NhvHhVh|&@TvC3NtKuU;UPN(q6fKj z18*KeQ;w+0OEcs5zT0`_VYd-Vqpi1mJ+b<15;PoSy{=}Q@Xv%r@RaV#l zh1U)!jiX!e8X$S8E3D*$;i^|~_156}nfe`|$Mp+r=Ft*Ye}?N&0IryqM7$*ACC3S3`*U?C-W-6YoLCH5St~595bF%3k@A*bd#5Eav-C!` z!Xg|yLl#ny9j8HdAa$J9BRdE-GbNEF8L}=IWyol^B4mDe0J5%V7&6)ivJ-)9ke3v_ zBrkXwTpHj_Et+y(gLtZJn;)X^>JFtbxCO5vl9#%|NT)ojST(l2d4ZtpjCLzR zmWKx*i=$!4XdlR?0@-9Qndl{F3SI>+E%N4gH08V|^HkXiYgTv-g3@Se!K+#FQdd~X z2g5Z{!F8qv*9p{bvmV!pu$fH~S0lr95=I#=+N}uJD0l#_p=cN`+6S(4fa`28nd2q1 zy=0ak*1*-Hc{2u0IkB^mm9@g=Da6J>X`JUZ%D(HECyAM*H?kErhht~RW-G{MX^@>k z9naGvI}s*X7TC`gct;^v7v@SryXwg1s-G~LY%uBBGl54zVsh2Df%&y>XxRN)E z(Udb=rmV3Q3bQ3p8q2-qUlOj6%*@go*&4e}S!35IYiz0VdWmMeT}3BZp(nT$HgmZo zcoQRdHAWdh+O3G-t?&SX%g``_v=4%Jg5X*&S>q+EyyRAa?>4Sp#hcY=%JHq`nX^sp zZUx^OD2=;X;JaJmQnh`N$WKFWZ+LErzB9>|-pnNLa}PcR^FVUz)( z-HL#G3J(DCJ{ksu_5oxwfV}7>&kH9126d&_U!y&{>I zr8lxw^1No1d`TU=qKC2-HuGf(4Gay6JFd(!KAU^@f4_@+}mwe+TUkNe|uo~OE{03%UdIR$ZnV$JwX{FHLIDJ!M zM89ZY-#6ng^D8-s=ae}-+iN?^ZY*YF+0kxA*)_uh$~}Q4g%`As?EXM@JH6yrFZo%d zHVr1E%~R`7Q`;$1Q!Do?hOHm2{48IWzDU@`BA*UtEOOedDDrvmfPiPSfboL%5&51z z{HsGBY3Czte8lCmZuOiGYk6IE_lY}PW;-9>=V@Kq;C1OIRTJ`Eb?pMj73hn6-B-d9uV*<7BF7WJ|gdi$h-Q;p+0i3j~wJ9okjfjKu}(wt}=e} zPy|X(#I!&M%UYNR`PdCLdgyeP!L zJOU|p_mO~)_gf5o9MTp zH2V6=x0ikjozffGsq#pUfvsR7UyF;Ycc`;|^jq83U;Vrbo7vYVZanv4jNZd2V??_Z zG5P`?faYT~>?}e1V00`P4fK%#0??OSx0N^B(3ArjSSm4n)=o$P^c9pwumzxy1f(9} zB_E8>01cn7sjrZp&o{7{LCNPh#^+m%GCs6h5ue}T0epT!!}!oX_+-H+?ITGai3>!3 zaOp1I;J?q&0#O<%Sr_F61(6F%BkwEU1Pc<8S$ZQ|LrKZSjLX+z4dK7*R%I0QjM~6v z<|U&XW7HO-j1lct#Attb0HgM37$e#Tqak2)l8>Aq0CnQJ19;OJP5Bx+iRZ&U?G04` z9SEgyN((?kB_MSTm3*)@bb^M@LDbh!J)bVHnWsoTCo?_=W0dis-HP~hhX?R+qhWk# zAAH7w&uAYR%xiegjizU^IIzB^>tT$}tc!_KrLso}ThKzPALUtTH0NGJ!7&6)i zvSuJ_^pPn(GD+|Xa%qS+VKn8u8hJ`=Rn1U%MWHmNx8OBH@={k-$p>3iQxsg2G`Ql_ z?+iVz1Z?JXiEA3emBc8+MY|Q@8VnD>l|#dD(LQj^1Fmy@WUh~#MUKh0>Vs!Fxbrb z6506-*{K+1$Y{4BWM{wwkc~vckkLMnT@GZI`pCsTvPkeclS?P?W+Iw$UYGKe*a};$ z@R|grab*i$izP30g_V4;6?UrM0md86Ch53j9fSvWo*`Vc>jWj-chNzraaNzq5hz|lgM3trGZlJX#_Zhq3$PYx9s zT?rGiR@k<)HPkuQe_1S}q1L;Hxl2O>Y* zPipSRW0IePJgSUGy~gp_jhWs%=wMNYdF zMgAB(AYhXPj2Em-wMM?b!9+1m3EEl|>eI%7YQZYY?_(@1)^fFAyRyjIiG9$Gd5uOk$ zM~Ek+lq1O^e+AB1=qH0jBHJ)tp2&$Z z5w!$^{#qVGSRP-&JIjN1E6U>+ctH5yvGDPN_L0YM{KHR95vlwNQ~AMts!YZF zhfSImJ97xl#3r8kiuas1-zhr8vSI7NW{Q+c_NK65w#{${#qW>SRMg* zXL-~FJ&gNBNKLecWmp84B zg3>tKU%p$+l@!d<8`-uuOJXo*;C0Ifz4WKf=K4Xd^-ZgzVKdM6i7s`}K_IV{gp$lF@yP(IpsVjA*waM%TatGQI*0TSK%DMvs8eMnBmg0F@q^qdXI* z9MDFd8(TwbBs+b06iuFscWd@gYns*;d2A^^_ZRyeJqZ-N%DD=@u3gIVSH$} zB0jgn1NhvGhVh|&@Od75p7oQb1)sHCXZ!SDgu&3X=*kYf4N%ApEZ)6MT zX%3kJa=w1Ie(S;>fAf-_7<>H9i;~z2jMzHl!HCgrMZ_NBB-S%fKu7x^_8N%2B5;+S zk@GOu(nsKwFQ-?O<@APvi#{dC*wO;m8xohgoJv0aJT3NMoj3Hf=worrEt1yjj23+$ z4x>f8714SL9sucSG;Dp*K4^UiTJQVGy8_r|t}8t$hdv9Z9N7EH`uaox_6n57$1V2o zPb4t2^hUP6-us9Lg6FsrlU^73K#6DugUdJdSM!OXe`v@LD>>V_W80~}D7a;bT z!1XZ~eZrgnqAADqnXF`r}Y_Z=2l7TOGfK+ zj51oZTM@0F-~qJ0M#E^)K4|>}T0i*7cLLaUuG_(zpV5>9`$1V>KP$j~fzsH~Vt@Zx z0y9f*Wb5m@zq-DDrQUzm6Z;J|bB83hoe|rKQAUh*D?_ zCcgTx{@vv+Mr&`3GFr4-5v^Ky0Hkhc*!rS<&^p+_O?88GHb^If>}Oav)w{!LbTrhP z>N0n;v%$}i?4~+ii<|0rZQWFN{AJc5292c$CSgg@ZbeD;hX*(k&yu2jB;`R;-3-#z zAcu;Kj;0wMT*`>wRF@g4)$Ga>qFI@T@`RMzhF%u=04s9Zttj#YkNj8`FjAm>MBW3D zA8wFZgBS*>5y2;6EicF6GI+BVQPN8mS`LFp&u^;p=-FM|*5zpRQy9Wh%U~*26xyvQ zwW08UjOa6?*h-^)q}B(i)fuFhL3)b3{s9wmR_^82$-LB}^x|o;qV(ixDMjhaA|D24 zEOOedD02GPDMUV!1&kN8kI4Uy$d56|(FQq6L{6V1Rlb~#k&&B6BSch$?WIS_&|6;% zwthhLu`HJfaL;m~-HLLV0S`!F3QGYmXdk&mkW0uQ$B9H{V!S+&kW54^!Et{rk0{Gy z7QC}OXt$y~&W8ttKZk{n7qpK&vdANCkfcH4B9-|tm9M6>OvOwpHHrVVTyiXz3*esR zLc0~^vKSta!o@5Fyr6yLG6=a84U!j$EWvnrB1M^qT9f==%i{!=$5rso@}S*{^0*lu z5dQTne7vB2qOSMm&Ox_Q7Zj z7&RDVqyTh3*FC@+`Y5h)Kn*-M_IZ800*F3b%NW-J(0B<*T_zFxrBKF`|7iIvb4U7-Y5pL?6io-3Pq+5KTFtIXpMEhR#(0eFUX(P76TiNr}yzEV%@5ZKHW zlGt)a>`;s{VzgTku>d@PmOuLk+qAlnV{qd-ERNCjg2BV>m1_*L>ySH#a82Rngn=Qt=6^GD8uLMi?Gp5Iv_ z=fg2egmx=R5OctQI}WcNUvvOqO`7nDDAHQv$QRr!M75VntKLXmX?pm((VzUiQEh^BSO0s5m^ThaI_i?D=qDV zNGA~4FF^JUki7$>eZaa2bq}oNrQJ{BF!u!m>ofM=oCk$M7jWshwCyp9m9A9w0G7wS z@XPX`-HP(q1P{oAKWGXsXdij}4S5_AAYB6FK#{~_FqJ29h)hCVpIx*$9M~#{t}KVg ztsH2#q8wh~IXuHcM-H@)91cegwE&dc@+YqN5FVa-F#|gGNyr8>17n% zd}??$Y=wH|3U%{zY&M_rCt1IN`OF@z)+Qg3Yx4-k<4uTJO=-6x9-qSlFwo~+v9(G2 z;L#U6>I0;AfE*bhM8Nn0R5Ilg#K4=&Z+6Rvucw_=36(ETK zi3u3=QBGi`6gDGCsD({&5Uj8XrLZwhLMd#XC2}wvvqWgOqD1HeoRG+2EPlM8eIzmr zi3|;plLKUMfSed0g94-|(qRv0IxS$lRjO^Co*{?IjLee}u2tK?JSA4!6J>1&$(Kc* z+@C6QPlRWl)~d{WM3(tfM(0R~86DcKh|aO_04RMJ6uh8)&>0UpV*_M#fQ$-|5dkt> zpkWVT8dj?G@s!J0$wjU7XpV(ddX!S>5z6b~9E?)+Ggw|hD=*ruC@=a1BBVnf#>AE{ zeBowyvWFAf zUh}rRFq(-e&2w5UUOplh?_36B7Q}4v(r!gC=D`DsJO>RcGVKG#1%PpWfSe~toR4uJ z;`}s$IZBoeu{rRNAd5)GOctp)O<*;sxy^)XNa+B>{3#fGiZz zUI~+NMT-;5B{E?1BBgE%|9`35QcP)H(W-8IMAq$c2IFdo84TL32*yfy0E6q%u)5Jc zU|bCtR|UvoLE>hN1CdgrQM1`y$2o;>S`7tUeG>5y#=AJ z43Omka$|rj3y|wX%=bcI+}7f#TPedfmn+q~QC81f#`h2UVe>i++ke~x@C;e#!(6>+;PqhH_v;?HCkdhB}Iq|55&-c{V(|SHXz-B%r z`8>(^{D@J;hjuICvuEi+0%#Z?+6SNa!ROroc{@Pf43I5?(q3HMo;MxPlv8>aSy{{I zBZbo5P#PZw%0D-KBq^DtH?n2)Hb>1cy{Q~XTQtb_p^iV&Bik1?^FxX31BR?4Mj0~N ztq55+c)*f62n|C<`#`o8$i4`W&jRFA!OP919^QD-l=J$6r^;5<*9tEml*U&rczrE- zsjI5wgW>v2!S$&IR}J<1wH}urHuEcqYa7F5V3gsa-HLGi9Ug$I4;qGx_JQj+;QA#% zb_B>z0rG<&b}UyP$D1IUa$>(AD{F=Qp%4o}Y5X22{{Z)gBxaW0$X3`6j-4Ufwkm- zTC#sF=_rWN$AUpUjyL1cloLA;Sy?OWP=(l;P#TBSmfzAlR1z~wZ)7X%0FIp@+h0M} zQG;wEb$qBE*(BJ^LnN|;8M4V3Wyol^B4ii910bA@h9RSUAoBy6uaBYOlk^LUA@$dEmXQHG3mD?;`nJOCMgAR1oKK9CIqvZ1x)gy5>qg7`<5vu^GziX&QRJ(>dnq>HPtldA6i?7NfTdql_NyRz#0J zXAJaOK6mUw(7T|PoG-ZjU(X%80Qp$U?jnU7d+ykx+VXpQ7fEhr>5XjJozLM@aN@Z} z>|tXU>7lTPjV+Q;7BVQ}VPmvg5fmSX(iII`QnZgHbp@bYCWzE^7@145sM##RaKRs^IkJYbd3$D=VI zv=1OR0Lb;V5cM_LNCT8i4Y?WNAStSFg zgXMZC$G~RZB%$2MpbW$)gF?F%L7@*RLzeW}X$%VO1IlfHa*H66;3E2XGH6q1%8A^f ztdcbfku;RX>RQ}!<(E#U(#y*=3X#$q%a%rlzG;n~LKZf2wWP3$QJ_ydV-#q&A`0W+ z0htX)!zj=`C_D}dn`+4;wPa&0*&uL?ht+tnmgjUj&1sX8(<7zjLBD9-6Tw(^w2$mwKz7g7l4okkQzErl zFd=Q8+9;aZb22scpnirY!A=iP$=9W?GhSqo{}aww&&}N*+EPw zjjgriOLCh`+AO`1?Wv#2OwCW^YjGBSkUHC@-&r=mW^R=`%a@GNLl|X@XtyFpPs0Py zJc@=Ld$bQmKZ4Qswd7j?=ozkimN(C#DF^gD&xc*o?N9(c52dla1)v=gkh&^LKG-q) zt%lDF)YlF@pBG^>w@W@hF+MM0l<}e6iuk+@58(3(8penA!Kb=A{_}v{$se_3r$F=$ zm%huJ_t2Chs_HJ+P`mE(Hro488g09mA2{v0i`!^s>5Xg+{UN!SJLPM!hCZOq+I0uk z*58kO2%FiqySR7OraMjTBaAXev|ACQui*iXK10J8(LNaM4My#|lRdjz_Zh$8x^H>& z9h!1L?E%QT&)87`^aGT}zTL6q@SSB0-S;~xfJ$#<3ujO6guWI~exeRK>Y;3h&D>W) z*@r>dfl&s9b}NFi=bj8o6&ePG_5tN@fO1H8(xp2&usbq`o`pEjSL~>SK5_5KTG9qmZn1HXNvMJQhmhm=+udN{*)W zM!FjNN@8Zc1ld~-YgVIjm1BKd5T=t3)Z>i6W*#GP4q!N=7-cwVw<4THcmU2M8iteh zfin)A(e5PNodgBT#;!uFh;lODlop(~-iKXje`Dy7 zjpy#(rfTj}u$wOpq2oBcuJ>hO?PNYr2k@V?Ij7Se_%841fH7rA-GX^b=vxm^j2&To zCQy2N9i0$@&WgaT6C9`rx6UrpT~q!{UMou3OBXH(;~)YwHa(%;KIA28-q z<1%VISTXkE?_4C_d5B`{&yAM}VyyY{Z$y?WYV!wXZI$4{QrbVBpw#t~yjS1qWn+M{iiZ~9?X zyR~u6Ql$U1lg?(+`fl8-%hjt})$mZ`*zEYG<|;gKtPTFV1+J>OQ}8njm#Zgi*~z0u zOu$6Kv?s1-T&^B4#V0pT9HG9eBQqTi(+SOuqeo0s-nAc0dsidKW5mq;9cJ!l@4k}USF?uR)?JgY&MCFvYVN$w<*H?Lec!&lc|g z<>3CGjy@I$ALl#xI1e_P5YKURe~ECv$ie-Ejy{$OAB*k7xWdkb%XJw{Hv5XJ`f3;l zjc%GYp}A_ltIE~3Eq1YHSM@a*R(3ZRcDLnKd+_}Yo6!mp(v9}>E_0f9rGDOWeOUK1g`Y(MX2r+Hu3&%4EW-VepR??GsT;vJZ@DE6*)Rez+P z_haXIzYz2O&&m0hdgoi6o&O}9e-EKeQr|kwyInu;4(ECQ5cB@#dIqbUInMKgq%U364HS2p^|8_!tJ8O^8Ds-H#RS8ywt^bo4Pr_?T!P z#+i05T(0pj*{p3>^;8%&$9W@$9nL_rMMyL4=bi2}@4xi(&T*diLNV`r2yH4d4mGiteiFubnXoKQ9n6xP9$#}Vb-WAUC zt`_s&>g0Tl-udm$&hHb>*Fk8L)Ll;VuGi0dzw^8gi+MLVIe$d&{84A;yLqgWaT`zB zQYt%dxnQ$Nc$ZyFF4ylcg{O@fGrBP{dD!`Nwka%!I!{z!-*p+)7UYO_t*d0^0 zT<~*!FyfTgSp>bmL(m=VgWd-w?b36(I>3}0F;gG$UNAakw1=>3GCB}OyNtXdqi#?s zM|4>ky254?_MtG@hJ7%MPGKJ;?5)BE?SUe;0npjS)*rT3v9)1!?kC*0pz3qE`Usmc z^;FzIV<*v+m^$t-brd$6)ftAVRaE>=TTsm0BC5H3bsj71N@UjROv7kb%M(S=$3tbu zs{or#WH~XjKC+Ckw~7qq8X=}X&0+dsu-Pyh3X@G_CySZ&kqs7hU1Vp9$i_iu2WAXx zHjy>JWE0s)$C;bO%u^j^o^0=aqNDq{!u=cv_p|NY&l2wSTxSToj_bu@`h^bDFM!R4 z>wK7OxXu$Z>mxf?*jq*Bs=fq9yQAc45%dzM>=wh7u-Qa*xtLiW*`>nXDl!};w}|Oi zI81*NY&OhpfXODZ>&49a$gUOkR*|`?Z-vp0*-b~|h~k*yXp>m$2O*jq&g zW~P{ay~FhP!e+y49ZcHD=n4Np80`|@BxZitVdjVI-6Q(vgpa2kd^`!8P4ti3yLVMT z52Ic5uZWp9JIwr|y?aFej_~m&bT$!gv2)>ay#^D%1ZY)RSM|FvwhSKkf8WEfvdCKA z|NT;g^cjRUA$oo6n{k%Jz z=WXM)uClAVw)6fW=G7mZJB3}tqb>Yuc(lW?1CJv_T(uC|l+dsbxdtYu5_*MQ6LJq2 zH6arWJA~X{gxnWGn-bQGdG#oJ3%e$+qhZvN zgmRd$YeF6aqbB6B7 zY(kz5lM~8W!mbJVJQy`0&%>}o$d`zaFM_aDT>K;DLNRX(l=w)wK-iR+_(w`t^`$Us zV!8~&4l&&%Vp;~F4aVzWY85X3ta%Mgwx7Gw;1%@5+`M1bt zErd2fuYt)n=v6Q}1%0cqYl6NDMorLnW7r|+4I=0VAhapMdYH8N&`ZpR^z&|Xp7#kc z?$u&0Woxx8 zv39W8B-REdo5Wl&*(cUX%-qpo=6&qlcW`v?7Vf(`xIYv&o5T*bpZOp$bBn#Ybfc}a zu~$?&dIaS9|w|I=Uyq{oxMoYhklV%&?!i#&PDpV&*!BnS0s0 z@9F41DBS&YTo8#~fyk*t-uox<6jH&pWu!!e*0L+HPici8e&I zKheScAV(jk3m>OC`1l8GHX)wk=zffFKgz-V2uB~2g^vjiKF)y6Cd6@$?xzX&jSlXo zIQlqC_?T@U#w=Kx4Q7nT|gW?7ZJD|8tgmkn0yepjMU8SFQwe!69iFwySXoKP|m~2qo z36m{~^)PBs+>c=g6pxCKHrmg-!D-%2`gtF7p7#YY@3Rovpm-W4Eed)=<3;_vFFDWq zx|sJBC+A!A&fjo${*iG0K7=+&z3VjZ$NG6cah~@}G4E$i&bR8FZ*z9OT{!;%LYt(% zbDDRDe%_y*=iMdd-Ra~U{{?E@vUg$FVc8#Ih-<=fVfi&7Y&HpZf=RnHU9SCLvN=lW zHKCZfo5Rdq?cE>h=$;7ohda2hh0P{0!+z!($C>+znd=;8?q%=3r=$C0h5KV1+#d~_ zO=3sc&CD*HqQZU1!ToWLK61iG+QCN>Hk%ORj_ywo?u!oY^Nv1-2_L7}hcU#?h0Apk zOg3xVRedUqnlsR87*9r{-)87 z!rm$}oN@OESm*k70sHCOz-BYO3nnKpyX>cTRqu&6+krViM7EzpWc$KqQ_a0$vI)99 zOgv~EldfXsLmX!AV(ypFxf;lK+LR~)0x|RX4l|!;?;d0?7d|d= z@Np4rHqkG%ckimc0!F*&uMsm}tw)_J9NfFXx_VYgKH1AXTd7pNk_X9ESyAax-cpE00Lc9r+(-PSt z?5zsns{Rm04XTeY?0{;U2>A;LZQ}Y&%&T7@p9;GsuCHL!#Pv0X9pc(4;`#+b8 zvI+Son4D1lAnclue}_>M@*fy>2zk$1>*{>BTHCnV!sHZJwXkdA+6zWaT%`JYrt`s_Z80nz#ZmYT~NJ zutQw+BCcK#+QijU%&U*9hp=nn>I0)DuD%#{h^r{#%0XyT;tWhSA*Wz+Dse*CH6b4l zqbB4*7tq(fymk{p$|yUxm#kv6t;<-t0K@M`Gsp9cF&l-u>H-?!Of7KZDLD_)qPr6?dSd0Y2NMnd3QL^+orp9#a7kb7R4X-A?zXtRqv~xx1;mCUB$eIKxnfny1--;(t$8Jog@wr_EyKTtNJh) zHK@8_*a6kyBIE#sHgWmIy!tB$pRjA8~8hcwkL#oD&nA9*qed;fta_=^~b*S2lsjI5mPwL$H zsPX9mL+V43#V@{k(HQqXLM}X^IW}O}7t77huDf$s!?aOn4xc=7%(SLaBk;iDR{c>U zrZhEAo-~?F9MRM~x^dXVrs<=G&Ft4_*r3r9MvrJ3J?n~Wky$^ct_P*e|$NP!*KJVSW&E9vsuXx||z3$!O`_Q}H`?>dP-xuD`YrgcZ ztl8@Qq-LAzr^-k*Knd*7=0!FzwrkKVO4JG__p=KD6* zT<&|nW~Faa%_`rOHFx^v*L>-_uV$O?nVRo>U)9X3xwz)0nqO*G*WBg5yXKvmXKNny zzg%;Xe@o4W{ts%__&=(7)xWjoYX46)Px*J&nErG8H~KI1U*%uu-{8O8|Ga;h|1tjx z{}cX|{@49C``7vJ_y5oTu>ZgQXZ>&Z-}Qg#f6xE1|9$`G{<(VtXPf;xxjnuq&C|~7 zu(HFq9lq-@*L{xrJmi1A`vUg@_l4kanfr1OS>nFReYN{K_l@qG+{@i7+$-I;xNmi@ za^LP=>%P-{xBFiAeeV0+54tzHA8|kG-sFDV{gnG@_cQM2+|RpTbid^OkNZ{kYwj)X zx7_c#KX8BO{@DGA`&0LK?zcT3d%pGj?D@^J%d-}|?*Z%eAio)`UkC9ILH~2_7v3+u zTfN)7UwOawe&hYt`wU|7H~Mb!t?;e%-Qv5=x5~HHcZcsz-`&1-zV*Hrd|P~P`rh_^ru@c{mW6$m8j*d{#E`p z{Zsj`Fa0~{>}cE{jXvLyy1V#{|@T@9%}v} zD*s=shR?AIo(wz{cslS*;Mu@)f#(A+1YQhm4!j(AHE?j%Ayo&?eHTaizQIwGCr;@( zzTvTHZC$%|VXagJ$BZ7)+_P7&%i6f+mPV#ep3rk*Lsd17Og_@Hp>g!6=INs`fIS26 za-BtAmi_5DYW#$nF=N>neJAd1Q)$^BrWredjkUqwZCqUrFB71{G~*|+;kHcE$_>|y zp2;-rnC8LzSV#Gb`DvQPM(|`M%yq@dikZD+8tfDF&+hnt8`niNtg=5eh9i5|)%SMG zKfRCYb#z_-UcGzO$uat>cduUk`t@_W`}D5sb2NLy>3dOzuBwLlV-|fhy8j>dbhzcM z+jDEL+p^wkobcEYncb>7b=bX%+I~vyR)q?&KPqoJKxy}AiD9pfoI{B@)m;hAnijfX zRmY&po$5wSude!gi%f;C#GdNTSz29n(=1v|`A6tV{Hdkw>s3{r{b(iRAE7JNfLb0H zURCA)pN+0m2de7==3>xYdTKWSKUa#Qok{rj;~%c#1Z4HG7K-3K5TLQj7U<0n*+ zG4!mp`RgYhX?2cjc@DEqN!B@QMB}J&!$Kkajq_Hi&5f8cW&EVEJx5iMhRID;Wa#)R zGNh`$iZnG$$W3k-T}29G@&9K0e`H-1i6x=QomfQ@C*c3Hsz`i%b7ABe@oAIbfWMB8 zXdZ#rlm8#jtyb{Eo0>;7k1s#hwupW5$TKiu!~f%iwkLBky0LL`W8>&4lN*}{Olib2 zXs+5X-t~}?eOx)Z?bKmGcj`L#v1wJqvApS@E`#^RmWC~c{yn!Hu6EEK!T#>S$M)c3 zbDLSa|7BgUriP54)G&EQlRGoMxoKGMUc*w8MopO3Fd8p=_Uc(z*Q*!WVbex6HV+#$ z8QWrGGtgjt4Iedm(wOmMdycE>=z4qeWwYNdrhjYS@Y8^rBi{bs{+Cwfcn0&#Ts~4f z>X^u>d;MPB_q}7=J+WfO{>8uMQhM67{I@5LofG@^%k-y5zqk3fgZIDOS5ejzM^79z zW!CT}7GB$7zQ=F8*;l;gn8Q~OUb$oH{@rUTa*B)_>2W|Q9=5dM@pFDWe%|i`6Kn3c zwf!&qU;5VqRb1UTbDxXr1{CTac&f_@k3XCETXog9qx{DmH#`y?-m5;Ij%UNMd@MM# z?&x6Exw}=hb+vW-tL9!y|DjiP)pt^vf-)D+WP&s6duf#43uT{3DwB?6qQ&5(e~y}7 zlD4Bxuj5XC5YoD2I+{qO!;xUql#;Lw6)xq%ABC_!9?oaO$!Iz_Lnzfaf0D{XE}DxK zqOstNe>Q63+%A>TSiBf7BqG6?TICL*tV_o-*-$Ya3XZf=SHt{S3RC%PC|U@IgCl!u z^7%yyGl_IQkF5Kvad$?yA=Rp2fmtk1@i*-Qd!ZDen&H0rvjmdZ>n5lSbM1t_iBsLD1{ znM%g;xmY$2rBxhN*;Xpkg?OSEFXo`Ms-r5~No779P9~z!ER8CbU2^H>ga9NNL99%%4{;452q4P*6C{0K`JwaNFtJsVD>s)jrNwxR6LYTW(rvC zb-EhuBbDh~I26lfu-xl(HQHAy^HJvT2hD3!TPEK|rua8TCiYP6qJ7Q%^S zwphT?C3C4l23tp+u11}tGFdFd(vbvKa-FV52S{ZiQAFt@I6AbuduOT4 zLYa)jF}rqmKTs+&m^~H^BcpmkoG3<6N$sxLT`J?LTpBAK;I+Hv;Zhk3=Ob9^sHJw-JVGkdk$578lN;8$ zu0}niGL?;CA1-2c?XF3rG80OKBJpSnO6vep>)ul;v*{$R3zKOmts_WP9x0W@L^P9% zWD8JQhmfl5C6$F@B%F;Fi%?p}kgDu0mAP0bR|rLOP+A9(s;raBd_J6{|AW#xid1F2 zRK_!@VlJP>O4jb0eWWrLO~;D4B90F2uGv>A(@;k8Da@|jHTy|r3bTiEIb@{WHIEX? zx^y~<11^;ajo2nFcpd6 z77vcIYOV^8k-}m=9*PxHk>EJ16yj8oO%`&|;5e(|s_^epm@6g{k$fl=9A_0= z6&@>vIL`CoTr3GbDudd0axq z67ej6TcuIgT39M`(R@Cc3}>LUYNIM6Qdvk9Ly=fM4W(5aRT-7aVz_{d_H+tLt2(MO zCY87v&!nPpB&6Ln<5HQyL5`w>k#^TiNF_G7Tme@{P+A32XHQCHI-W}AL+KopR)th$ zN-D#Va50yQV{vGA&9qczvD)(ZlsHbiX=bD_pGx5}Hw2}2)67a`E}YKh(lJb~-86Gj zS-=HCI+McE)NY!2sVqh_`Ajy4wW-}S3sRZQ;h@NeaFA;^&7xFh;>Bbr7sFAm-87Gv z%2Xi_af%-1x)KeN%5*XpP84!D&b6E72~rsj#nZ`12n$)eX`U#R*a&0M7>*6?o_UfK zVuQgYew1!9x}#{YROT>wCYnS-+C6iKP}Zd~xokLsv(;3~rMfAcEQPqx3`L?i0Zz4! zOI3J^6lPP!d@_V{>Qw8nRE0yOFcU5$Vqu)7r&>p)D*T5O77CdpHidj}s&3C5CWXZ$ zR!0ISzp1)C^HeF!=hES99Ou)iR=w4!Pm{u294C|*PSI1XBT^L(m%>;i97(5=;owx= zo_V?y#~QF<<& zs@*diq!KqeG9h|?o~qq5M@wZon$6;l1Inn~Gsj3}Dw7G}e^?pXJ#(y7X2Pj_F`c7} z%_@+(6ONP0Y$~0|rBYbG+C6i;R7Q)TLOvEtKxvgo^?8O=MiSvT&VWfMts1GyGo`W^ zPlpSkFqGO&bAnVBaAlGY$1%Hh)0`-kIeb(~MbdF7tpiA%eUen>3)vh#5X7Lgjv!Sz zSt`@vVjdq+qflChkgA*_m8n!A5st+pP+G^3s+=m7nP@JH%UrB@?WWl%mDx-_luYEY z-bS;zeFmNF?!=0m-tQEP4iNzjAo0mLLMI*nzWndWl|Z56pHyAK8iGH zH_gkXGM$Uy(`*Jp>kv}Iyg~}Yp?o@9z$d0A?Vfq1RHl=$a3+$*I@a!)i={GEh~vs5 zPxlyIiIzwuPJbEPYr*W=J@YE5jA3@%zd=UYJ#(p0)};!u1TLMk!5O+e^J*zfC*yfs zjc0;0bbIDCQixCRAza|&n=Py6>ZWk56lUTHoF_x6;0)cKd7Ts%GPuE%#Ru9Mx;^uH zDJ({@Ff;gwJVUoj3v^zkBl1w zGpr+0^>~vM(oZz`IBqq}u&S*JmkVKiK9bFa!f6P#d*%wM%w;plXef`lwR`4DsVsz2 z_;LyNx@Tzj%$udMm`;arFE^QI)q!Wu}h|pJjo0_fV6w&T~e9Bhl^O29zohY^KPlc6=5ihr3|I6MC+t7UCd@9 zX?hH4H_dybGMvI^**HCjw43I=iZY7(fAk>I?wR*VVLlv9Vc){!+C6iQQ59~KLVOjU z%@(8K;7sc{Q-u#pA--$Im$St}aHe&bslrF3FdoaN(vfU2I8(P1J}QLu_>5Kz;~pu1 zTcuGCiA_?8Tg|aZCFyVLzQIrlHhsh0jZ68b^7$kjL!Wt?&h@%w}-L z$m4U!Ozq|4i&B}1X7SMvA4Fzqx5AgC5=T!wfgg83X&pl9TG}j?_$dvp^ztbvtz$@4 z{zoeFxc3=Kg|kpv2a&3LSt@hMd@7ob<2Ogzt?(78jD=$OW(%J@XKJ^?SB0`Jg$oMY zPR<3VTL*`FyuBucXla502CuhX^L)~8aL ziR9Bbe6iZJ+t&Z265k?5aQ4Fj)^1y$No67xOXO1-y3}qpG4y@LB*DwCK!6~&G{UHhqb@6p!J@#@2o1g;WrjWS|nQ|X6$D)@b* zGL9b&;(N+`a74o>jdEY1>|01-dD0I9BN`gUO)6=3qrd*#)RF!6w4>1WD}*Ds9|lfL zYaPhDQ}Lr*yq^&F!Ed9mn(z%V#8XOs)t{g4FQoP1XrhqJ=QC8QiMEqa_6g%#xD@@e z9m?q%rw0gWeX)pp`5{W6QRB0-5ca_jio!+QwWLa2pa)86E)l2S%*28tMmJfJsyQ7b zrTHRmA*FEd5Yo|_NV^CruoiHuIGdu<@e{3jsaOvd;=UPt!xoO?8!?E5R;|||LR%j$ z6tT4M5eEM*PQ&0(MTwJaGLJLeh$bDazX@e;Y$o|a3_q6|S@Kv-%YS4iwpO|dU41^9 z&S&v4COC4;M9tiXNo5SziTPv(zhoP4<*u&kZc-V|M&pra0dtQZqw(pM${6m3#-maE z)^U8ZM(GjCx>O{CpBv)i=*S5rp?XI43LzG0JQSrrI~X}ZhsYu6UrtlOqG!#lzj@}BJL33_lu)OPWorbsk%f1 zLRycn)3f;5P!3W{sXDC{%09_>CJ&^k;HXg(tvy0@+FeR<-xNQ9#W-$vg|sjI zG6i>w62Vau8b{A8#i}mlBZRg-8!09exTyuLZtLqImH2sY93LU6S6x;_DEq_{(QG1% zJHn$Tj-IMP)l*9G1C4M3-)2ENR(CWXDW#EA4m&?SkV9&%J(X22DaH4qsYD11Wz@uR z<23>FmeNEnk8j~|C_`!iP`%bkX)+m$;S&}0Izbm}y_7~`>3jzFT&YwSYab!)8^?(+ zm&flZM@?*Qvb1Wk`U-75e#jHS0RRM(ETy`z`blLZAIA4j_(lK3$<}tRDvuJ%e)$M~ z29Szof}vorB%7Q;GqZBw zz}g^bCGD=(TFH_{kZsM{7TA(dFgDTT3?}EC4=_3BXmZZ+2qwonjsxz1-=}AHx~peL z-~W4m?mfMGo=fSCNT_Ii7Lt{NxHASQA8k6<4S)?qzuDj-!B*D>BHM%iX zhr<>r2}wxTfg$MKH5ybmVwaOFp?xjqeg93Ns}l81F;rB?ifEq@KFK{a7~4ElP$rs+ zV4n^S-cy6?Ads3w6WoHN+9!j9rzx-#M;0}KL)Pl9fr9UDxUy9%Xf#>VfYWs(V!8&p zdwloJ)gs2Qi0m7r1_A0zn?vIo3I_shLonJk&{LRKVll@iG&YCjyDledIlKDQ$tcGr zH8z_}CXyM%gc56o^jo8`8RXSsSwxx=YlmQK71mB=lkgB=ue;D!Hm=8Y3h5xV)`)x* zY8CtY!VEd3pf;lHWJ9h21*HRFoz`n)Je9*?Ob#p<@_jBJzCk1FWSMmqj;zq@J93U} z)X4fwCXVv$G?4x>#*t}-bQ&`-3FNw}3;hM(-nqJDG_<}ROGy&9V+xB0{a!gVtDtr! znUeuzy@ZyS&&O|4NT&&#)kd6GR?nS1$B%P(r#S{i9TTq8BqTJ9`_mOPT7v`791fHL z?NUCUt5vhc;`T>lwzjs2^{M69yuvz7xKxr&VSSpbqg_sIi-Ja*Vs)toXn_ay1zb$a0w-jNXEnZO9b}?Z3-O4eS|vH{DHY_mE;|_Yb?q_ zV6@150UOG)nHpOk$4&<2?;bXcWgQxuZHnQj5&ItWtCloQ!(JL&pUuYNO&%lkn#Qqv zE38w8^nNZ`my-SZ?B$}^M?s^gjj2U$snLV_EaTnotFh@AA~n?40jvEd$95`gRW^bY*W9}RH*JU~IC^6m*d3p8V)_L*Ei`xVxysfSZZp|liOKg{9X4k&09PFCe* zL{I=|kH1UhY#UVIN!j|GJQ#!YJh1OBINOFaTHYYb;-sjA_UFgZixfJVLJl|H0P&$~ zzhgeV12q)+2RLNh$dp*WTaI0Xl87XeaV$!JhO*)y z1)hYuE`57*GfB#IHU$VUL`D?Df0QVq>!VhDcI@ZNg= z!l6efXcPz3h!Ie)I(Ol~kRQ%*Vvkfq(R_0%}{I0cTP zuqu5l?CQlI|DIJi9_T|UXXDM{F2@2XI zPxa@@u0z)7vlZ5dipu9N^7qFadA>&CK(?t?9+GvdfQBP4(8z`c*fG}H>h1yGm2l*R z8kvwuaLLyN>QXO9UZjvt6AE5%`Kv)9`$HywF@vU&HA9LCP%8|2iGteMrrKIuQhtPcR2xufWj; zT&l>)TS*?cL@}S--xb!8N1Juogw#W|taB^8K|yU?7HPyCcqt0scX6TJsE|?IMr%MW z0k{D_{l$mBNgD#DP^T;KMIhP#b-sd=mBMfQD$-%?jxxaG|p?hkzbPpH;lm zTNE^kdcR~Yh3FB`fiRu9Rb%T=BpuJyc(e}q{qlL;rm>BUHFdZwn)CV%*W>w^+62}n z5A65M!FOvgPKL60t0Yqd`_tp#dlcAdfZ8BoSL`{&eC}1yDDH|i*5ZEc0(U5s5%(#m z)6j&ocAO}9*pOcDSI}qb^BW}oGgC|W$xe>0xk0@vqC!{C?LIFFVp-g*JW3el4 zz(&P``s8v&drUzcq_<#ec$7qT8^Yhm71U0~P!QUP*lI!O8Q2pV*;JFOZIn+sEC@Z# zd{QADm;`bkc9#AQ7(j`ZzyC{7KvS4_{&xIVe$*C z5}5nJHx)RV!)1@gI=FccT*7kedrM&*RG7tUXsUT9hws= z;LjC!QcVo+>)^$e64)n$3-}9#u1d#X7d0q99GE?4cBol=sld?`PQEg=SUo&&2+dz9 ztb?2BC{|43@*6rXLAmC9t)Nx)sWh|~xiCQ8P#V5b;AkpV7sC}e+|!fb5E{N!Sf{25 zCX~dxUJ@HZ!*>c=mCM%QBDTCrIoqARz>k@^?7r9FjJ*1R!bu5sL%~02FtQ}L?F4yv zU|-pI&p&D~p3p#nnB)XH_C?3BKPhaqwl~r8)VK?cI-z#+~$5(Si2E5p{ORq#k4tLJM(`lq=S3=$ey8?Y(Q5tafSFr zL8G|Kg|kq3aT2+Bze6*5|%z`I*@+wg&lSS)?dB97b8!<>k$t*}lm(SY&}Jjf`qA;hkupj9bcux@B< zl-(`}Uuf4=;3ytQz=N)++wj1pjyc2DQ`jn8-Oj{nQQ!dVKP6m*FS?uIv0=*dV|HsIjL2m1>?_rjYi^rR*{+?Z&< zWnZsvwSnh-Pf+N|xVnaWMA&PV&|#fVRPaeiA>c*IdR)T?;aV=d^DQ(QH$_2AJ$#CX z4x8qd3OyN*G&QAhGu%gqk+PM7N7E?iY`{Sy;CfHVWwW)yPR5JNjd;2N+J8Vlr<=2I z8wIawl&>`7Bpzt(xw(VeR$(V$tDM2BmRQ#%SnWhPN48Vw$=Fvn;i(HLOC$W}glx~? zDcCqFcT4ag-+OTQ4hlY{CXRC0CLHM&dmmD}3%*3|sPI(@Tn+2Bi6+2cu;T+sWfhXanWgV6iX*hiO;~d|T?N2&h ziB=rp=-m{0GF~If$u|pqbeK+6DtI)7!#})_iU{U_@CDOSSnLIGK>$aVz%CwCoaS@1 z6*wBl(uN}NA~u9~j)G2VLYl0m4*NsduNEPnU{s;2aL2n27Az+y(WS0A6;&FH(-hRi z)xZq;Sxm&ilN1a6gd|sM_*h4`b zylE&e2SOTpYCPK8Q$tZA3}1k9CP4j}ap*J+&7w*QITP52o*0K#D`-^`NjB7R%86mk z^!1m^ET+Iwym>7j*^~Y11(tIxuCP@JRF`?zkt8;BvzJg{bX*%x=OAH;4dGZ)LG2_S zHNis$;O?Lwq4RjFMkDbcVFMm+0&fTXd2wW|MmFMweIz6Y2JO<=99O4tIIhIQmhxGX zK|iy@ktv0Q3N+y5Ci$Ap;DXR3d%ecO5^%7GlU<1o3q=|f*1-P$Jc*}hUiMtC2Ln$2akWmaVlTLhIBhqL8A}=t`OqB zzw9=Q+75+v;&r&iSc?k$fkCB;oMC$@XcU=z+})J{&tUlR)ZQA4eNPhGe8~i@h}<9T zqp&!kh~p(j9E3`2$jtUtP}Bt^GQ~UDV+ zLa8*sB@(!X%~r@NyfB5mfn@Fw3-`H=%~4=G-OvDSknhfg7N&G5Bns?PGUZ%7utWv! zTnw&4+Q{b1I%!zgl7SFX3mPe3_LOhNR1c~>7oXHzg+w+s*$~66E+9j1w9QjcyP*zT z#T{Kh{rxxZbiPL7+`JaITpEG&&%HRZTOplP3;7~o--{UVGeD?ckD0Z?q0>;@7 zp#Ivyq5CUn6>=I)_%()1_0Vv+>jerNZH(pcsynu*9=OC;u2~Be7KIiWyt$7bDv{U_ zh3!$$Dm(~)xA}439MJHLZLb1H@c>gp6W#+afwXQ!+jV$>A8Ql9;koMp4bI`!2)t05D}w#Z4Y!3s4Ms{Tmc_gMMX)bB z4jxkAC?0iApaLpZ1c$IUA^hjhGHVIBM! z4GJEz)kEPK=_Lvo#WpaF)Gg*VOh)=3g>`TOglA5qDN%cmny7-pOcB<<*j1BAsT#yf<|lc7(s1ay`(q1V);mo#Usv0HpM+?7zIZu zC~ANatsu(wupty2t)Nx$bWH{&wGi5H>A7PRIErFK)Iwul>w!ab>{x}x#dN%C6+;FK z*zok+aSDt}Bq=;2fD$JU9MbXe3hU(XQwi}#T+$f|PtTp8phywMlSs(}iPg{F;B&(~ zQDLKapBn{fxaTp%vOrwICn;ekp=O=5~t4#*uHU ztwT8!UxGOirz&g}Hs7*X0|XD3(>YCnCp9#s@ZJ_uXdYPQFZdRGnL;ClmaM@dC&?H# zr*pc3M{(V=F5QSH_J)SZqnx3zRk;`r1@Uf#hgEcNnVhM>lTuCf4JZJG4h@?}IZL6V zsB(bqBgqA{3U)a2&Q@3~9jJA}^)z6INp+l~z)}1%M>d8h@r&RP37)I4RgHMpI)Ps& zsU8}x?)*FrMrI4Ao;V9fG^;bLoEhgUaI_9Li%=8*E)SEFxIkmmxWt{y$@OcPoWz9+ zJ1K)FOHuWWg>l$g>x&c`W|BqK5%PCHhh{J?R@kaUEv{CgOr?5gxD3W63LJ%J!5hv= z@Irz^n0%?iI=LoUMvIJ@#Fn5uR=P|>QHY3V&v1tt(6AW%as{oDB|^y>96}HAd^eZI z6$*^|F*)4nmkOlWz)84LL95_2Ya8l3HVl*RxJrSec-IkkNbtzh5OY~viLX}JDm>L7 zWrrmJ*wFak8U>D`01Yn&;8(0Xa0q{|Rag`*W@KFgCU;O@SlD`Hw<};Mxw4Ng_l(m^8J}G z=&c%xo8!1HhU#cMYZ3;%O+#z3Yl6SV25U|z^mYwxsENs62*Z|mDD(pJ9U6*kqEr{u z_UV%d&VV}=v?_zQk+H#(;SR9AIdZePOM@G0rcVU6QYv5LMufp2+i8kyBQTcP=T>oAP@AW>7#16MEo5Sxy95^>D zUwpqtHsEDWNESQ&(5k8j6w*OCQxdlqaWqg^u{++R>Jno^NTh(oewFX zgB$EP(UW|d7pejeYbZ)qv$%zW-}Nla3sbB|6g1kHk?*o%eAKOU`}NHejdvy zvJBW!gkm34SSKy-={DdNBKq|=+MENAYiKfoYdslUltH&)&?gksPN#4JiON|#85Aa~ zClxZ9%u3%Pf9Z1W;%;9Ad|po}tc{o1;kl6+(offL8LZGqywzM=i=Ts&g`*)J>uHU| z(_#q(=txPZr%-sG&nTpW<2@8y;f^A%f)9o)bI)oho(rwVVBOnpv4aq5K| zziBK4ve&S(o#z$S!7l-1>rweHyY=@RyxSKv6sspLAD|q(E8JtesG)ec1)(Skrw0}f z`bjC?>q{D%g~LqZWnu~S6Mh`}vW8+Ohr6P(@NV&-pU~&fR}|E4kPiqn;1pM1-RB~B zRUw^5#4rhOgBDKeYZ{7EVH`c;G;t`L)Ymn%0T*U7c$Ppy!$^HYK`r>TCj6piwR+x) zKL_=u#^JdQ`7%xl{fjI?UG?CCIle)0Zhobq zDD1~iWTMb-zoF2V5Wdz>HAB zN203d_Ra2Js2=0wyR)AZ+QB`;L@a~Na*uw8g){M=3Toqxuq+;lg;DnVdZFjJ&K~3b z|Nqwc|NSHIV`=%j&UQas^ypK$9T5y(And}m~(?240O%z32%S$1hoGG&37!d zzX0ua9kU@Hb2~IWQ#Q?Pk3Vmr>9(@zDzfRC8`GHiUQ>U_F2)@>=vlJm=$-KA zk#!@Ht&BmJ8Z9+@WV^FvyU%vUpP$!@MArA((R>VdA{t?i{&>1oC0d;$Tiv<~{+zmg zB(k1tHIkO1)s4nbe0p-Qb7iwtD)Hy@4LFg1f-_GTExGVz%kyN*k1YHd4^isrjmMa8 zdo8=lDcuDP&zBAFaquU*QK{hwUl?DR4f&X|=>@WBUlsnW0WI*x^qR^s*WXksz=1)9 zn}lW;%4QQY_;cXaTyNIcl*Vk&n{n>Qh8M|(_h#`Yw@oCnvBy*ag_8}Zc@2BY2Aqm^ z7t3~SIsDmv+el=5QS_yDjYc~@qHKAIY&ms0{ydJBn;0#pZZ1u#%<>axcByREyBGef z2F1~qxbfz&MBa>#CmUWS8~(XB{(NFI+y)J2@rGO!vf<^j;VJv#&;3w3Jz^yqPMshL z4N5|`x0VQp5>SEr2*qzCEK+h zi9c`b!43aIwA+-oQ+{+NT3sz$^&EviC+?|iX`P8QX1j?I_?Y5IMvH4?i%Cc0&uY^m zk*$l00xu!QalCQL$eV$Iu9eN|kHMcS(X3>&a-c@uhBHG>>N?r#jbriWkZNvu-(avV z-jK^oHoRUoTz)+M+!EsrSH*~ja&C0;A#-T?ciHl|6Y=M>IQN3TW5~E3zGJ2^}jAHlSu!K%-k_qerg8pC8a@Z8@_M^ebAlbVOpY z{;v5|4x+kwojtP`7Q8ql0_gc`M#Q%xhhd=LkL?Y|X@>ueH7me9VH=I`(?8KW3 zJ)PZdWOyRtb^7Kk^%4m2- z_H)a__;UmLndH$RMi=O&xnfK~H=ftuJJeS`gJ)&y^B%>Yt>LQHk~9dhTL*nH7mKiN zy>ND)Hwlkzat5no;k`??O+1D_9ca6wY)d1y?STXtdE)ng@uKl!F=~Yh48*^m3=+(B>rr;kM8Smv#;8m8h;kXzhAc5 zZUz3#K%3^$_(z*<>K86ljix~ZE|rZ=doup2S2Bb=ww0=Jyv0i>!gpTvNV<0oNH(5&3hr56rhTr&4|W1qPV6YDHwVISeqpzqgHj z@5lE8I@R}BJekI9CwF>NX1I4pRz!|q168&h*t^Inqvz{YDk5JyMZVN$^PR03oEWFE z&OmuQ#$7?9BQ2S(fzHK~Wfb;37>fT!NA@iHw~ENijD>iTFq7=(T$}K`m_{|cRbz1aB``Uk*=wV*m4AC~@qK`J8m zsiE*|cx`B|)pAP=(%J&<4lW$9t=+n+oW6T1jQq9LAD0LD#*NMU8CAb;6-7J;t}~fKtrj!f5f7#}LLdpyh)OU&)}R?fr|Z9475r z0RF963eTHtPj%0m&(&sMF*-7}9Y*3724{CKfPpOX4P@)Ef3Co$*&nhw--?`V(U0IS zcM?xS)JHNYOy?`Ye9-lzW+HlN^PEhXpWOw{XgAhNyb{w>8nXeqc~N)Mk*oB0#27FM z?O);2ZVp*Brb66zGmz)ZEjOqY69B8xQ?Hp}TkV{Y%Q53>)lE?`7g=+SmF#*j`@(UZ z-Mw>$=7Q7f7X4gB5tg&hC9|H)t$IUf)n;1fT3VXhx$i#?pU>91 z)SR%bxUqQr2}Z6|jKmUL8IWccd_0B`;jw7){2+_I2dxL|f$#&&+S1fyVOPbi98p+Vsb_0AxCQzf*fW~r=PO^=1p&b9RljoYE= z7Up=HK+#)jMtE~lIz>~a)mUZToLN^GtWS2z9reXU^Qnl;X8u2!X-%h!?!UXoEi5j$ zOvKM(K|NiYspt8;370Juzr*=G#mQ~P+tclg-orre9n4_zmE6T%fUk|3Yt!L=f{eWb zjJ=(UAlX(V8-EQ|-UPrp#Tjq42*e4uV6=O5SE&4I@8@bc5k2HggXsWs4G(rNocXRM zCYIz@cOC$<_>v=6VsJ#orq94^$LSsrfEn$NK>H8WG^BuAf;7~E>3`{Y-~_(NHSCRo zlAMnz-OcR8?nXo$2vR4&8o$#9kgDg)%dX(r=#qeCBt1jM;>zLu6cLf{ySDOorJdNI zVTZ6vWaP-D)o>+CCnCFs&~mJoKil(neIqMSw3 zEo!zXZ&8aytrpF&sLi5wi)LEXVbNX|?QPLM7VT?Mr$w_Ynr+b>i@GdwEh<qLVB-*`iY{I@O}nELvvK=@y+~ z(U}&VWzpFdonz6t7M*9&`4(MZ(S;UWWYNVIU1HIt7F}l109VbPNoJ!R1fi=MXV8H=8^=sAm?x9A0nUbN^Xi(aO<89j5rcG?x)TST1#7|w~pIzc#UE=31@$WA2 zOPBahm-w|y{MIFY?-Kv*694NGe{_jIyTo5zBH{{ig>c0PSB!MUC|9iFidC^)b;W9~ zSltz)U9pBM)^x=fSFGiVv94I#73;WSU01BL;kY8|iYix3a>Zm7P;a;S1fkL5?37Lii2Hoh${|t#bK^E+!ae*afB<5bj4AwINBA*xZ+q> z9OsJTU2%ddPISddt~l8hr?}!&SDfaGWv)2g6=%5OOjn%cinCpDjw{Y}#d)qc-xU|Q z;zCzk4m2bv+xn@*HMA^DTo&^|BVln(! zg%Dn-Xkn3K3vL5Kt~d)pl05R?4(r?dYBk38OD0Y%9t_oB{O#0gn{R2)@dVB3SUk5? z?Q3QDgBa5c$d+M(2QdOt7T+|?0tKI`h%k@*MlP7($RHkb6eQPN+nV7Vx)?FzHLU+U z@BUn7^saWFs8@i zTxZsT&IqPb`Sz9+Q>pv#`9l^fBbX1;QiqMj225w2+TNjlh>dT84u|3#$717}re-$C zG|V@v=9_PwF0(p;fc0)jWtx(Ea}72EDvZ1iLO)8$!%Kt8w3e|S{}y9Bs%)dUDUqPg zVC=jDOym$nOiOdNEakaU28m3^+KoKRYZ&M_&hVCWJ2E*cT{I0GJ&qCEl5Yvl^+$B^ z5$nRE7Llmx<6QKyT+xWV7*e5f3m~^*hP`hHJ$XO_v3se_x95#We``SUEG(|{#5Z|P zFf@JuVxFuSSWK>P8DEZ$K4dzHIu?(dJ|?L;XyY2nGHS8$YWLJBL~(}zZP1}O>`Uc& zRtJAp)uebqe^@5C4-|c-XAgHW!(-DTMo|Wsefjj8dJ2o2`3$iF6Mv2&JVpoh4GvUd zHBM1}*lkEZ2K-GYhO$Tu@f6h@%xwp5O)@LOs5ujs6l1!9Z6Z^Q-_ZI_Mynl?LE8+p zj@5GV%%u`I!(5g?!^W`*wIU@gEwU^NbOfgJv9im2x*om|Ru#-#H^6Q0&-{qobC*~Y z)Y;boeT$h_n^noSSr1}{EA@EZ5)n9($fAR7O%_&`WsH`AkLM~)#JL6dTn35&v@T@!g779~X|R7l9IrBwrJMPhx;wtU%lIb!Zy*Vk zfPSu`I06cb5-48^df_JLYFbLmpEP%-UoT<654C!hJK{P_dM*=Bim$L~d=yM=6`qMv@+MU9DK=0WALvF5^fr@BYjeIi#zeCWjZafd$-_eqlg0cM zOj*cANmX)f%VU@)nQ)40Te)-G1zg*i^%6IFSr@%L$B8XEPe$%hAa^`ZEm%A?6v5Xz z)_XF_3}R<=zL#b>@!{=Z)r6%k;^cL=e0=W;Zi`Eqfq93m|@{$ zrLT8jkjd;R7|g|bam&}F+qg(q!9>o{pJlQ$VP-r3!fYmLeTO!ujBMzMuiw`J0gnWlkmy z#5bA>1lz$qeG9~0$(ZlJ?#s3h7eE4=Dz+x#9qo*YV=>cL8KK^RJdb*Jho(Hjh={dk zGkJsO+k=Qfrn8CS;=#|W&$>7Tn0vS}dN~`;x`|-?x~vyj zBqWzB!{Hu+ZobuVqLYwJ6Jb+qnjyes@@qc>TDPlKasinOx>*NHm z>lGgV$}MAM)glI&iWzUi6sfh@SaVK;COx1PL>=Unng7<9?)@P^Hq=&t9LxxAMokpg z+Rs4kKecdW9%z_QWG_tpWG2Mvl|1#=k16e@`;n^F8Z`6s!T%eT1fO~gIey=jg_w6 zg$sLobS1g0G95V*AL5hLG2`D=P521y;z&!=?FX;;w+X1#dx?gzTd5Rh%j5k1N!tOZC`dc*)9y8D6%yq6616{31 z&C3mtx5HtyjDZY3W(p$Hhi!aek(T@s(}6Z?3JVjT1g)*?YqFAm-5p<_(=(BEJpmPP zAeK+KSdg*^>=YUyna4Q96E5JUq%rbh0ok*6{wa{)MdHk;0L zV>&WbU%}nUbh9e%066pW)%RAph?{~J=>8}s_+)dA3tqA-qjgYL#B~^p)?HA&scHa7 zDsSckuLJ>GvktsNmB7CIR8%f~JJTyh#~uBJ@NTQ1A{qZxM1Iv=E*47$Y-lzZe5)E> zW|D`=lZ?kaV~h@2+7~Rw_&esZp2kRn^AZu|`?f=Yyq5_jZ`n)(F9qQ>+D}5qGr{E0 za;R{lqFZhpq&YDoxC4A!jcHD4S65yK+z(fjPfQ`ijFvVk5R)nS2@%Hbg3PX%ZlKHi)M2}Kz#aYNBJ1}*}yS- zySB2b=wBe1gIOmji|3kVqm$2BC*BF+WS%T<0ynQT-4kDZ)_`kTrd6_NuK|_(4VZ-L zqPb=UqOX99xlx+Eg5VG^V=mek;QR4R_;3qtrd|I8I=|E^CU-S~>Za-7#KX+6y~7IT z(hmeLHqleT-c6qJ4fY!6FUMdmYbu8M=N+NBqD2^Q45QgL_v8nH;M;?`6yV$@(4}R1 zQm~s2#Diwh)^9MJCzycc!k{t)f5)7@R)cuu{sFVfV~AOLqaf8??Gq-T^(T6G@7U7J zhBso4PpQ?dro9F6g>e|QE2uk*EnPB6$#|Z|=hqcGy$qAX_d0ukN!`j;)B*2-z09Cr zg+2YK+M3A^#QQ;S*2ZHqt(aU@`irl*KbkYQTA7yOZ zETME?(8k8#(={=0fS#EgC zN?;!Z75g(~P4Q@MItI8zvr0yj!Smr&;lhq(?Wgl&m<4G60N*X6;=CBw29`M)0N=~F z6>B&3bqi2=ss1iqSF5~WkOz(@bSr=xqa-7U$qEJs&s>aM)RtEVF6QQ;!=b)IH|rvyQDBuu~Gz~ss@74L!TZ)+B%Lc+rs zSahw1NX3Ww8WH4JK$fbRd4(VWrTz+2`=>(4Ivp>c&cwPGX0)7JI8N1=eb0p`+S%tg z`!*Kejx;7(ymAw?h;K02_Zbl(HB&X9;vpvS;wh$4R|M#dOu*=~_bV`G2{l@+JlBAa z<}2s^kmjvyLGx&5D%*`QIt*H}twA~-2WD+Gdt6U!3+#6e0(&krI_bdX&)74M1RdXK zeW=OT7-Y6U9e!u-uie9dOD{uI7O2%NeM2>(#vY1I))t zuWPZjhM3I=p#fthm^yh@XKL+@P|15Z&!snGJnusnmsRI;vF3z#y*H15>PKW7y(_G( znCrKU%z&!4ju;*JYG&8az+mq}L~w3rDSNP{pFQ}V(N>C+jf28A==z(C({0Ax;s-GL zCR*i6Nw1KSyJMhv^~^sN&kM_Ic5cIPIW}C(<%dj1{s##RzZq&vL8 zfZ6Uv=wdqa$1!Ac7_V2u=e5)b#ogR6OW9%!b&67RZH8f4y?wz=p69yS1N!G7MBpb)c7wqO|C*cxLl15V}N-(&}fC4A=Sz z1eno`E#6Kwyy9J$Pep)r(m#g;I0t}rn`$V2Ru?}BU^=2>0V#0id2ya`=(H*9;#a0C z?M8;_Ly&X0!CslBE;I8l!J8))Z(75mgk3Q8mzc`bdQmt}0Un33Zr0ukMH&GK$aDG4 zH8D~Xia~TR);b>KWHqp*XeUOo;@yC(p&{~UfJd}L_{}rDEKG z<9Kk@(UC1W?HJoI0$sw}=7u}Hp}5LtSte+zG2O^TO4F_h{M z5V95ns1y70z;Q94H)yClU<`{@*Mm6>F>@#ua2R^}A>8d07V#iZG1ZDA z%1|kk)o~4s=4~|%e5syRIc=JM9ap~Bp&s0*uAWjoC338HIc(V~;0Q&Q-V7FwoQR8I z5nQ&Z_{)N;svx^U*cBt}ijj83D7#`6yJA(lqQb6N&8}G8t{81stYKHIX;+M~E7r0r z#@ZEY+ZF5B73)93S+Z7ww6&uzUBsHEj1_2ae0`buiB@^g#JueB82Aq5YD%Y7#*(q=h>_cOM5Lx$crC_1 zJiH0>eICh7B=-* zO};+EXTJveI8|GFi}kF=;?bkX{1|?gS9pYY=yRLRf*llX1g1BaUx^tbVL@)vimUA3v>tGc0cf- z#0a$Chbg!h)0J1|Jp~=TL-&-dpAp=4Y>JM))@-jq%+Gf=vd(v%Qc*%(bFQHo5swi^{7 zA7iHVjEHQ`C~mq9R2<5vD89#0c8vHrBz38tu9Q?Dgsgz1e&$pdrcy#g&s5JnC&`R*GmV%Y!N&dfTtMEGD90k1nmlne`B)-SJ z6B)qI%q=MNM2;8mC2(73BFppQ1Q~=Lt0v=J=0dn&6nDz?>2wXr%`{Jzf5+zyl;CA( z6AXBhmw67=(~a&59!GLSAwfU)Z+ z08)QuX7^xFc`WNKUH(Y#0}V1Htya(7NxK5$6Jrbj^V3 zzQ^pV7_S>!w@$m|RbbSbTGDL&kT5(t?phT zS(9=?o`=moMxOT9$0vUl;;QT zg!dh3XpkBHEri~Dt``I^lnv-c6S_D@bpbt=_XQcXf1!(ojC0<0&g9&in9$l>%Z(-P zKbX*Qssp*t@&f;|3zt8lm-`u8YoW+Yz60pybUhWXpi54r?4I-Q5cTuQE65#@$$jX_ zy6STrv8dX@9D*S}(~2zXJOa1;GhoJYts}+4r@*FvLj(Zl@p+)sk+u z2%ON#YtU;M4CQX)-{`?oGmzQdK;G>_0A6PLmo~PoQ^4oxh8-aR#R!yj99t?zBdRv* z_D%+Sch@W^9Yo8Bugp-cf}zYeRN1?28=f6~1$x-T`jw$oKvnNSe{X9@v51QrtlL2k2S^u|x#XEohSN@{_oaM;_EQ$Xo><~TzRQIEo8 z_fRGb-)wH}uK~NJX}OeCBGh+Y2NB-Hd|%%1eP@E?cU4C+#tLY50s@}NXw3zx-yQ>@ zwQ9~Nv9qmUiQUc6--}rn&20-9S69K;cNE8qPp<`hKpgh*FRo-*Zp|=lZwU5IjVSKg z4JWi25Y>zgaihF)8?fO+g9vDbIYb?ZIDwf~u|C*Lc>fcEJ%C|~SJOSQ1QqRFKyTtc zOP)r7IZYp2X_>wo;MS(9#6R{%7WRTI03#{2t7WnA1bbWJ*a(<6vl8 zi1#WsBY6sdBDYXYTN4D0;69WmdcVSaZZwASf;Xe)ZhZ{4SV^ID<2DdX%T48SZG`fk zs%eB90`QGy3l`wAZ3DQnx6*kea;2eq3tMp8_9T$oF#hGSv>Eqz<>AjCnmx_+p6-{q z<+3_A9W4c68*v;Xk5OUo#c4|qWt37CncfyvRX6$UkjZ?LUSdO9gP(wA#Cv^hJk!vu-IhvtZ_DT;@ z1jYXsrj=q0&E|~F->p#B0H5v(Th3n9oTkd6*`0cN{~E>&q~>|5csZCc ziVa_^U^BK8JsAEDJx7?XsU(|%fGZezGWnV10ci&SDNUhQFk_5xD`?z{(TF{d`KZ7X zpweZ0^t`H3b^Zbbafh~OxhLU**c6{PAm9Zm)C?fm~pQXF&6gSKmD|m?0tj zO5jhxwDLLR19Nx?b2y1nSX_wAQjedpx)3MRW)|`VsGOip4A)PP0)!TZW~Qpy19lc`e`8RU(ETm8@D)Q z9qzM?X!+zZ1YEZDvO#{Yl7aWG*JSf8fwv)ok%|hGrv`5G$j21sF%cw;z1!ya+RPQb z{CevBP~{cMno1Q3a;FeUumJOV|gNhZhK9e`%<=g}ch@&^~Rj zJ`2_xHT-vi^)G3EDC4luZS7=8@gz+#S!VAx70mg zbu|>>WVEi-3>mHn=>pJkyN0#MdtSk?a1(TOC!dbI)oM;>Gj#KZwn8M~${#A23&!nd z7&9K(GEa?OgAIMkri`)(Gbl-8()$>Flw}*9LLUv>4h{Vl`1&rJZ{SJO1g81~Yusw4 ztL4KKo2Y5ZH{t_)I0jacV9J3A7h0;)KQ}@#&R|Ypy76|!VmUeXHEEnXNDoyXbpGbP z^)|Tu&l&Yt_LzxW0^&boQ_lr17iTc{!&J23ZJiNz7-u&!?5ouWp>Tid7<3hUO0lu! zbE!PjFJBE?jeXDL`I7S}TCdQPlM6x7{{ns3UU}P|pnYNgI{ms-)e0@M z*MWp%8mo@YW|GIwna$)IaBeF-dhu-AShh}qZN8%sxVB~Ny5b=46ef200%#zd`URoz z#pCe%#P~fp{Yw<{m2>xs;FOZT0)qdiXY4KNMtMsCbH1Njxw@tmNF8s5xkWYQa#57$ z_GQuKC79t+T1ar(!#pMREk<6XNRvN(Wb98rf_e6FR(sbmEyitG7xKL7K<3-p&0S9v zBOIm}gH^9QX#N8H*`F~rIwt*r==Re6Crj)OqR^UQ^|8Fe$aq51c!x#ywe&WdlH z+fa}5rL5M&`SwtktjD>vxaAui`6BF}aUFuqTRvCE^C7aPY>`%Agf?YI5+6Z#=NLLC zH{(o9;~~cTH0z`X$|D5k9%##ok(Kxf&%mQE#h(FHRig5VnU}o-`bnxc*d_}87Bhc$ z8TkK(`d-Wk2iCYfp$&5k-IG}&BPf3kG+%E(I$C*LzYa{`G$y9$#&1^)Nv>(dEEZn{ zi1-LZ?5pUMN5c{jd^~#vX0wYzVYcuzo(I8S!$+PAV2u`(xBi6fxtBv)HOjobm{(R$ z7=10rT>jTq4Fg%kThe_k z2UBw#Bk;FXYBz#2c^QK}syTC_3$nw>4d(7pkofG-an7nWn z!D@&p8Pv~iSS`s`a*cm!<2xC?AbR%F`iAmNeHk8~!;Lz_D zba6G4qpZJH3))E_e|Jrz_udY7$5(;IOPJZ@jq3(8Acecs@Fgi2bs(FAzzcbM=>mB` zlc$lpbws*dtMt3EP+FMvbtsm4$t#vRM-hibTW-gUJlkLJ3e)6)&+PuL`DnMycL!JT z31d7p;S(|8Z<#c`{WH_etML6-MsU2gy`Haz(%~J+X+m8}XyE=0IJc+v7Vzk$7Zig# zifiF47HB&~$R{7*FsAti^t3ymrx;d-qUDK^SD~*PX|Q+0-1GmzfsX{xRa0q+XFCv` zsVMpd(Eq#crnm^oei)_;q;IA%UajBc!CqrEIu4_puRLq<1vkX3tQWZ@-kiy+Ok%^`zh=73Lo z9UY9& z%gOlq44bBxKxFegLi$N=M)H9zvl!|dkT;+w>gQd{AIp6obA6lj<-MfM#1(_&2RKj5 zN?G3rwf|FyQjN2D`MdyvXK`wZFM_dQo&g!Vt4_R^83IwfTs;0_Oi3UO$#`-%hPa$@ zbh=S-E=#@lQTFBUD9kHxPr(NN#W*2fWGK7vwKv#tkoL;cRB^*M&kSHqh2(`M(rU1@I4Ujt$zJy_{%A!M{8G1|3^KY3n!Bfa1ZHY*&M z;mzt{u4+Au`Ms@&lqo0fDq>*cW$bfc6TcchPh@no8wK9do$tfcKt6M0ra_+qLTFOG zoSNxs_s1^(n>2n&yK`Wm(Am|6&}F3`x_qjbS-Qh+IO#OSxrufV zWiMwQ17%!QcjTSG2jS}WK7=1Vg8NwuW4eC%9S;+_JxJ!*zve5LI*`Z$4egx+&E%dTuZnBCG*z-Cb#`%$geYC09XL8`acH z*M1D%-hsiEsSaeRPn(ywD*Iin-_VuAWR2HQ>y6u37emy~>7GhO+GRnFBi**rD|z@E zSYTrq=t)I$jrqH0yFgkSvema41e=@9moTCCRCDhabPbJ6qKC(sG>aLT^4NbT2y+`X z9q9)GG2CgO^CrD+f{>Dz4lcwSK!2LFIU?2J-GVX1a1W?@PIEg!^>R@=3LBFpjaEmHURRq^7(8mJcAT) z9Is#uOHHeIU{Fln1k~+9xS%%`F~wgOn!}dPX;6~Sm>ITnGn6+(w$xHA{=lS}+Bq3) zn`bCluB;yEWlZN#MQrJ}Ar15T9QnDeA$3o&3_f%|rhkIR?!jY@LG) z>cA55q(;c_H;|Ot1&F&DB4$OaQkLm4Cjj$rMY+snl&9zS1qVoBkiJcshqe1b0wc69 zlTm&^mXv|(AN8ChUji%ROpLWVlXu)G@0tjKf50@e z)w_enG*iAgvlauOw1jfYN47HL`n@-{|n00kAh&@{~6A$7VanYX;%0(;)kk1S< z!x{y#uc2CJW@M4TfqoD0OxF;)Xl9NJ?Umz_hacA}wesE!EH70W3wcj6tgpD$WprEy zh8(HrDEY0>JnuK4W`SC|@C&{&w;IOv|ayrNZ36cHv%(a*e^*;={VZz3Wv_|?*Tu9RDUuE!L1Hn$A3LY>0ydfys+jGQ+_z|7F6gJrs-|Q zOJ1^Ef2EQejx+ESM$opiu%-(Xrg&=3qq7nC9$|u&&nZY^j5;>?H0W(gRlPS!Jd-Nh zS#6BjU&(s&AA$~)`>z3YtzlfoBOZ*)@=C{8EiAcb1WDL=26v20Ags@nIJ_NsU~$c0 zN4^Q0eQAfpH~z;!v#06NN(W!%*9We{VE@oOz?xS4IYOp9^_cz9d|EBurDRpr^Ea?@ zC6i`5uhn@Dv%X51kIEfY@}r|QLF>l61LLP(2t7QbCyVgZSSTz=dI|HZ_;F3SC>w(Q z1YN9C(%#}z4%p2r&nlm_9M6VF7!pg@;|y6Lq#3SjwCBm3-|+P(&YzkY{H*eNuxC6w zqRQ4Z!T8j<)RAc2!d59*om!>V!?%yL-XXZj1)Wa{IyaJ&hE-0{{WaRBnbnqU#YX~g zmL32B1%8~tGuoh1{()H>!PzYHtpPU6;SS-lE*;u2U0MlpA7B*Knw7PK=;05owKCcZ z+*z6nr~eA`GhPJ36@Mxex<^@$pRMA)>@Dc?*G%5+yqx1@P;dknW{bsacnY{s&&W4_ zww|z|tI8nGmMP`lK7`p(Kg`}S?4J=`XuVE)Y!5tneiF&7QiEfo#iusC z*BR&a_YO(kNDIJ!sJ>z9E3e5b^%eNI!kAzAyO+CRmd7%Qc*dn%)1K(zMXlf7PR1$<&4G%)xWv4`f1r2Q>S@T8(5uG_I-Rj#*v$-A+9Dg9 z+i}25R1vuMj{E|T&MfM=C%6>sQ; zx_S8yYcDeg`F0Z%?zZS>J2sU#Uv0+V<0(oK-d@Pd3Y5L_@(XT{AG`}(Lg%7F*I;kI zygcq_z&0%E9bSLZ%Yb)QDOa1aQ0Z_?`z1zCn^8e}CkPtDoXZR;dgWby#@9cT|CLu) z14Z0(p*s69z86DUkB;(?_BE*VU3&7VSY^Jo(l{{M9EcW$@a(TxvlP_&2Qlt$3Mk*w z8p zM#D|Y8+t}s?hg2ce`pOY-@Qsp_@C|rfq|J#Ex=PRW!8wFjFq)lMxgf<`uIl66hB>T zyyMma-o3@9f&=LkGv;c{;$gXnh^$A*^&A1~gaJYBRp#2IZX2dZ(w%83CHdcKsUb--r!X*%Xw*tsRoZw>l z>d292Z5fd-Aouh}j`z0ck)=l?(eZ|t=y;dUzWjjaMFso8mbGs&$vroZ@y~ zYH2Vvy*V_jT5D<84B%w({atSrRK>lply3@4byac09tPiIJrbAbuUYG(I8{ zsk4_}PAQw}ZECQo(WbOb8Jn^;HQAK2X}V3#Hsx(uXT%ci|; z+Q+7SZR)gXmQAy5nqyO!O|DG^o95ay&!+h{b=$O`P5axlz@~*Z_1M&FQ=d%-*wk;+ zfK7uo4cWBFrUPwSY||2(4zlTBn+~z*P@4|3>2RBt+H{0XN7{6hO-I{wj7`Vdbev7c z+jN3WC)#w9O()xQicP25bec`eY&zYhGi*B3rn781+op4DI@hN2Y&zej3v9a3ri*O4 z*rrQty40r2Y`Wa0D{Q*brmJka+NNu4y4I%aY`Wg2zuRy=2qNHoaogt2Vu6)9W_9Vbhy7y=BweHoarhyEeUN z)B84kVAF>-ePq)=Z2H)yPi*?srq66zY18L6ePPp=HhpE&*EW4))3-K#XVdpK{b19N zHvMGNKW+M#O+VZ8Z<~Ix=|498YSV8v{ch8LZTg>0f7tY=O@G-Gafloe4vlbVq(h?| zTE(GN9jb6>HHTJrXtYCXIJBliV;ow`p|K9F?a(?7t?STw4z2Id1`ciL&^U)Sa%j9m z8#}a#Lz_CZnM0d9G{K>X4sGGkmJV&@(AExZd*{_+8kUF5kp#vQ1cWA(& zL5GGMTIA4y4lQ@6ZJfUFgt74qfcf zB@SKc&}9x??$8wuUFpzO4qffgH4a_t&~*-7@6g{Jy1}6v9lFV(d_>(G4;-S5x?4n645Lk>Oc&?62#>d<2jJ?_vG4n676Qx2_g z=xK+Zap+lxo^$AVhhA{#MTcH;=w*jqap+ZtUUTSmhu(1LO^4oc=xvAIap+x#-gD@E zhdyxVLx(4y|lDPg1+iX1 ztX~it6vT!FF|HssDv0p~v2j6cQV^RK#AXGtc|lAlh=~QUML}#?5L*?*)&;RmL2O$P z+ZDw21+hax>{t*x6~xX3u}eYhS`fPxL}fu(1z{J2QxMUDs49p_1u?lGrWC}~g4n$v z{#Fos6vUndF|8n~3nEq!@q$PcM6w`i3Zk|k>Ix!N5cLJoP!Np;kuHc#L1YV}sUUI% zF})y~3nE_-Ed|k95Hkv*tsvS9VrD^f6vSQyv3Ei2QxN+WL}x+FDu~$yF{dE93c@Xj zLP5+ehm|ii!avVTYi?N5X-J5{^3#j-5Qi z4ndNDhzT&GBA}okf*AvdVgf}41XK{g0E!X82hGu5-l_j!2v@{gO|?#f+V zRb4$LBc^7=w2ZhSBd*Mdt1{y1jJPHvuFZ(+GGcm0T%Qp)WWIb4hAPxw`fq^(E5Df!ya3Br|#G!#`6o|%wXcCCS0?{-O z%>r?FAesl_h(H_}h@%40A`nLh;+Q}j8;F*HI4%&!2jYZ4oEV5!fjB7;CkNt`K%5$g z(*kjNAX*2aO(5C^qFo?TfzSfcJ`f!O(J>I60&zwl&J4s^f#@8FE`j)8AkGd%*Fba& zME5}S2t-LBdIq9bAkGOyX&`zB;@m)-7l=NA=o^TBf#@HIvOo+7M0p@80x>WUm4O%( zh{1uV3dE2=qywP`!U%*J2rCeFAe=zBf$#$12V!U-GJyyJF)R?n12G~HBLi`MAVvjZ zbRfnAVr(GB1>%B0j1RHR-IS>~I;*vmI8i>mRad{x71Y&9+rUl}P zKwKG!s{(O#Ag&3-wSl-U5Yq#3eIRZK#EpTN5r~@tF*6Xe0x>%fHwWUDK+Flm+(6tK zh}!}&FA(zsaeE*Z1mccBEDXe=K-?LKy8>}{Anpmoy@9wd5cdaSaUdQD#Djr&C=d?^ zVo4yD2I3K7ciz3qi7cCxOceFhr(qjoFOv>#^hjfE*U{UOo4Jg6^D6XZi=f$Z7UbrLUn*XsM4&pJX&*|gx z7%)OHopY_c839&5_Qnafq&q&5-0__e{<7{O5f?j$@Sn=gTk=3pQ7z>_zlT84B5G5N zCh;=KB03Jf#Lf-jX*&@_KV2SsB0yxWFwySiUm9R3_~sOmyg~=deGwelQWc5LBz82l ziQzBDW3rN=7Gt-jAuHn{bo*89#(Fe;AIU*2QH##D5v1=&BnwL?l`~im)X(!|Ntrxe z(lO;PI$Y7e`gvV*|42PZV*X`c=}}(a{EPTk6`kj54*j*{D_V$YDDRYTppIHR-7cqe;;GfeLuRqcFId)JF zFQu|$`UDjGc=&$P`B8#iCiCA7&#iM}(8EY&t%23QY1KI~V6y$EJig`}PX8uyO<)Qi zUe)7?_EShBIz1xOOWRuZxeB6*W#xd})wqygW?^pup}Ph4~mQT`uB)hdOmpVB<< zv9E)beCQhbS{8v3*3wJ!plm45(wJLgvW5yP^)MNP|5xg3EcLS7JCypIWX9hll1mv0 zWnGN2%{QU}C&w#>;id$6=FnnAF(bpxR2o3Gxr~+8m|p>|9>HnhO&X#Hx6o9bPEk! z&xtG{OZXb65}6ytf-ci%p)M#gcsZ%I!3NQFgB<_rB^q;|N(!p|kU6mArr3aJu|WY# zVccm1QRkQ;CEb(<1s2oS)1x1U4G*irvDb9V$_FaPg<(TWl%>7(#YE4#UV+?!Pq>88B z+7{8{pM7Q7jXPcTDR z1z=ZH4djm4vm`%ns4!Lb;~V@Lgx&gB&B+%H&v#0;>r|4V4! z09D1D&0*M!q{jW?qiI{(>Y}Q*1L?KeKZl0NmkD`ShdGzBmqeIzd4X~+{ieNKFE6iI zyZ%SE>vL=>pOPMC|5RaFEt!{kgHxg^C5EI#I#o|k z2_q#;CG#S@l<-qxXsRHSDhOoerFeL%cton<$W+7gQw>L@ibto4$E1qKri#at)gs&H1SaCWNj z=9IW4CFZ2+%}v$2HC6AnRN=f-;rvv=?WuwVDRD=t?!r{vMX91YQ{t|axI0z%o>bj? zQ+4l4)xAF@7N^7msk#rQ>OPbbVdmw?rKuwyNfjr!HUN^D3KzLY9_IVE066>dxw zZb}utnkw9!Dts+fxFuD%HC6a}s_>0e;hU*KmU$@-GcTp@rW(GNYWRMt$p@*1AEugo zlxngw)vzY>B0fopn#_y%B31Zh>YzQT{Jp8duTrhPP8EKWs`qWG-gl{@n#_y%DJ8

      b;8Vx_#-94%!{bWyomo&B2N?0gwX2cYxN4WdWD)O(nK9i6wAzusHchgTD=BZ z(E(cVftol-D`=?IJ6IEkXyQ;!G|~zh%gjsuVOoAut)Q9Ayc9Io3Xjl=j?~0anrNZr zAFbsdqvao~<+s%GkJIvx*NRTi@=w(ATWLinX+JQP1(^`S96&qTCsWq^)Vp}V4wEC{r zz|-pcTG3D~Kcf`|TK+Jt{&20y2(4(OmVdrhG)l`Kt<@i+<&V{h#%cK%Xhq|-q6u2@ zM6LKjt$31Fe36zvSw8^CE843TJ2s-J})H)LPEc3TrYiBFwzh2{SLECi5Z|X!&<&`3tosi?sSI^HO}T zChpUU@7Kg)to2hqU~MwW1|j{!%Uf5v^#MR`jS=^q5w-T+4r4%YQ=4e^SeT zN)u0Ohpf;FR%%7hXhmV>rRX`W@OiE11+8ecR=7qhTB{Yls1>f$3fF6e8?=I&%uC@$ zt#Ff8|5dI2X07NoEq{yFWUE&6x|aWjR{u>c|1GU(n}x?`Xw4H1V!h{GOKo zzLx)iR{Wt>{E=3Fr&j#2mcL8O->v0;qUC?8)%i@T^SPG)g_i%NR%ee^r(yePi|ZWH z{(wg9(YQUDw9h}ReS@a$8#Ze{Z6VbbPuo`1ynXR)X)=V%(s(qD$I@7y#^Y%`k;ap0 zJe9`NX{<pqFQ&0BjrD14NaLk6UQXkcG&ZI2 zY8so<*pkN9G+s~RjWpg&#=B{}m&ONae3-^ZY3xkn<1}`qu{(`V z()cuu&(iojjXi1XP2;OHzE0ztG`>yayEJ}C? zs-u~X!*w**afFT|bsVLmg^r_j9HZk{9W8Ynr{j1XC+Ij)M=KpC={Q-(DLPKoahi_P zb+p#eMn_v6?R2DcXgb>K=%Aycj!rtx&~c`YvvhRU(M8AqbeyfDtB!6uy6fnnqeMqf z9ldm%qoY(uZyo3AI8R3(9es85)6ri?nT`QE%5_xe7^tIC#~>YpbyVpXq9d(C*J0=| zbyzxV9gYrHho{5WF;quJN1$Vvj^R2+=oqQvd>x~7jMgzm$56onJVjY+0xKzhwIxg2SMaNVf({x;+<4PS@>9|_QH9D@6oqKW*xWan4@E^j$3uyremIt`8sabu|UTiIu`0!q~lHrW$2~gk z)p4JW`*keV@qms8bv&fwVI50!EYDZ=Y zyNj(2sur{jGcAL#f{$45GL>iAg4E*-mde4^u19iQp=T*ntWzSOZt$6g&@ z>G)d5H#)x6@tuzEb^M^?M;$-u_*usfM|LFKv$A3EV z48VXekZ+*CK%s#m19c1(8>nlbo`L!X8W=dhz<~x1GSJY#!3GX7aHxSs1{xb^V&E_X zO${_NaJYfy297Xrq=BOhv@meAfny9DYoMip;|v^c-~r104)>G|PxoNr*1fzbxW7#M3{oPi4rj5jdBz(fNV z8kl6@A_J2RTx{SH1D6`O%)sRarWlxNV48s|3|wj8Dg##=xW>S>2Cg$O-N5w*ZZL48 zff)vFGBDG?ECaI*+-%?$19J?_HE^qe+YHPzFyFxK1{N5&!@xoViwxXp;4TAq8@R{7 zy$0?xaKC}Y1|Bf*pn-=BJZxZzfu#l>F|f?QqXr%`u-w4o2A(kRq=BalJZ)fwft3cH zG4QN`RR*3j@VtQ+46HV=#=u$wFB({9V7-A223|7ovVm6&Y&5XRz^eu}8+gsY76V%i zyl&tP18*95%fL1R+YP*J;2i@y47_XLJp=C>_`tx220k*d)4<0Db{W`h;1dI%8u-k> z=LWto@TGx02KE~G%D~qKzA^Bvf$t1_Z{P<5KN|SSz|RJLG4QK_eFlCr@VkLO4E$-} zF9UxY_{YG%2L3aUX96aKiF^|UCJIdynW$r;*hF0u^-R<^(ZIw3CJr=lkcoyS4mNR! zi9<~^GSS#X6BCD-XlkOFiNj4aH*tiCBTXD-qJ@d0O&nw5SQ9Nx9B1Nq6DOEB(L^f~ zCz&|e#3?3DHF27W(@nHC(Z)nu6YWf-OlT(Bo9JMoqlr!?&M}Hqphz|4f{1 zqN|B+Cc2yGVWPxDPZPaNoMWQYL~j%4nmEry9}|5|^fS@lM45>JCdy4zm>6iH(!?MW zgH2SK7-AxALN{TUFilt{Y!i+N*Mw)nH!;*i#zbIZn2F&gMwl3B;(QaMOpG=$#>7|? z<4jy&V!Vk7CMKG=(8MGY7nzuB;$jn*n7Gu$WhO2+F~!7G6VpswVd6>?SDCol#5E?a zHF2GZ=_al>af68)P0TQHlZlxoW|^36;${=Kn3!W?u8CVs+-72)iTNgOH?hFP9VQl< zSY+Z(6L*=o+r&L4?lp0riTh0~Ht~Ro2TeR=;$ag@Oe{6=h>2w;9yRfpiRC69H}Qmt zCrvzM;%O5rOsq8VjEQGWtTOSOiRVqcU}Ck2H73@Yc+tc<6YEWEF!7R!mrcB4Vxx&o zCSEnM*~DumwwTyz;&l^mn0V8~TPC)d*lyx&6YrSVVd7mA@0obt#0MrmH1Uy%ohCju zvCG766Q7v))Wl~dJ~#1&i7!p;F|pUgS0=tT@r{XZO?+qKdlNsH_|e2qCVn>Yi-})N z>@)G3iQi59Vd75{f0_8(#6KqfHSwQ`JPWWOEaY1#uuy2B$U+^;1z4zSp`L~M78+PM zz`}tR4zkeD!od~}v2dt`Miv@dXky_o3r#IFvv9bD<`#~yaHNH!EVQt2w1s0V9BZMa zh2tz7Z{Y+BCt7G_;Uo(uTR6qSsTNMNaJq%o7TQ>7YoVQmlm*Q~dkY;bbhOaP!WkCM zv~ZS%&K9~@_@9NdEp)Ze%|dqzJuH-1=xL#sg>x*FTIg-zTnpz}=wqR;g?<+LTPU+I zz(To&3JU`*R9YBhVX%cN3qvfVE$9{u3#J9jf^EUE;9Br3_!fp*$XEz046`uY!Uzi^ zEu3#*l!eh2##k6@VVs2vER44>!NNof7h0HP;UWu@EnIBj5(}4FxXi-k7N%I3YGIm% zD=b`T;VKJPTe!x;wHB_kFx|rS7H+U`qlFn3Zn7}b!Ym83E!=G377KGM%(ZZX*k)n7g|{udV_}DdcP+eU;e87q zSoqMwM;3Nk_}IcO3%f0RV&PK@pIP|a!WS04w6Mp*UJGAY_}aoZ7QVIcorUi${9xe^ z3x8Vp%fjCl{;}|{h5sz%*?;|Lo^+BnL_(Ke2;(bC3oHjcM(f{hbxw6bxMjgxJh zV&haBr`b5&Mr#{wY_zq}&PK|HW~0504mLX4=w#yz8)w=$%SLA#U2Oc%#@RNy+30Sg zhm8^&J#F-|agL2r8@+9uYvVi{eQfl#(a%PI8)Y^I*eJJAVPl|;N*jZ047O2aV~CBk z4c&%e!?a=9ux&UtTpOMZ-^NfI85@C(VK#=_7-3_ijq`1cvN77m7#m}4jI(ipjqx@n z*qCVJLK~B8Tx4Uijf-tuV&hU9m)W@7#uOV!6*3lmpE{dj}mHbac?k!5I$Dba0k~&JMab z_@9Hb9dvcj%|UkuJsgxc=;@%BgL52|I_T}-TnFbl=;NTTgMJSBJ1BE7z(Ki#3I_un zR5}>sV6cNK2SXgB9q0}W2c`qdf$hL?;5zUe_zs3T$T$cb40ABt!3YN<9h~oAl!MU@ z#yA-3V4Q;s9E^7`!NEia7dn{a;35Z;9bD|-5(k$$xXi)j4yHJm>R_6KD;!+u;3@}K zJGjQdwGOUxFx|oR4sLL8qk|a^ZgMcw!7K-}9o+2T76)@2%yn?9gWDX;b1>h*?G6?= zxWmCh2a6os>EJF0cRRSp!MzUdb8x?d#SR{D@SuZ-96an`iG!sM9&xbD!J`fybFkdO z;|`v1@T7yM96aq{g@ct2o^kN3gH;ZmbMU-_7aXj1u*Sh!2QNBU=U}~q4Gvy%@Unwf z9Bg#3$-%1*HamFD!4?Nw9lY+~4F_*Jc+0^y2iqOI?cf~;I~=_0;5`TLJNUrChYmh+ zu+zcE4t6=%?cfs!pE~%=!RHRXaPXyrJr4Fd_{zc84!&{lt%L6zeDB}~2R}Oa$-&PK zesS=tgMAKubMU)^KOFq&;4cS%JNU=JzYhL$kmmv}go}I^1uhC*6uGEFUB6t^by3en zeHRT}9N^+W7YDg$=;B}(hqyS@MI#rDT{LlVn2V+^nz=aKMRONNxH!_qQ7&4zINHTA zE{=84(#3Huj(2f_ixXY6a&eN2lUxj5ZLYZq-?v~|(WMaqTdqP>d_E;_pC zQ_)*)F=e=;orkiykgYT=aC&%f&e^N?r7JajuK=T=a3#*F`@U z{auu~7~rDZMTLujE-GCNaxvINm5U)R(k^rth6~e$<-&I1xNu!~E_@e5U1VGYE{3@n z?qY>0*|P*)DE&af^#NF6O$p z)x~Wt=DC>f;&vAcT-@Pep^HT>?sRdNi@ROi*dD=s#=*yQ3>7n@zY=3~`^qi%(sA=Hhb~U%2?v#U2-XU3}%@YZu?R_}0aD zF1~m1gNq+s{N&U(J5;Q$W@dN{~KLk|agIK;!D9vXRQ?4gN=!#p(g(9FZ(9-4bN z!o!gsj`GmL!_gj&@o=n%mL87taJ+{TJe=sEm4}l&ob2Hg52t!K&BN&)T6<{Yp{<8@ z9#S4O4;?&o^w7z}nI6va(Ah&54`+Mm>Y*Ia6Nb)d=EoCWIO~O zhItt7VT6Z~9?thL%EM?6V?2!YFww(>9wvFX$irk07kjwG!=)ZB^KiL`DITVJnC9UM z4_A7)%EQ$juJLfKhwD5{_i(+38$8_TVTOmBJk0bk%foCBH+#6n!yFHDJ>2TyHV^YW z%=d7+hXo$)@UYOsA`f?ZxXZ)c9`5mQuZR0Q-0xwrhX*`7=;0v`4|`bRVX22lJS_9@ zsE5ZqEcfuZhbKHd>ES64PkUJ5VWo#>JUr`Rm51j%Jn!KJ534<_@vzpziyqc_Snpwj zhnGCO?BNv;8$E3D@T!N+9$xdX#luz)uX}jI!`)WADWN$ zK05g5=%bU5Gkl!s<18PYeRT2hKOblN=<1`JkM2Ht_$cww(?>5K=lCe~(c8zlKF;&e z$46fu{e1NIQRZWSk8&RsJ_h=z^fAcCU>{XJhWJSP(0v#_OdpmH+lS-B_2K#OeGK)H z@e%kK=3}^z5k5xxIN!%8AESMY@iErNI3E}I81G|(kBL4m^fAfDMLs6`xY)-fJ}&if znUBkTOz|<*$21>T__)%?RX(ovagC2_eO%{bx{vF9+~DIzA2WR1*H1*xA~aoW4@2ueJt>ChmVCm7Wuf-$6Y?|_HmDodwtyJ<9;8DeLUdfK_3tK zc-Y4hA4`2a;$xYQM}0izW4VvVeLUggNgq%7c-qGbA1i%4dw)=S7 z$2&fD_;}aHdp_Rx@qv#IeSG9&r;m?)?DDbO$0t5M_3@dH&wYI1<4YfVeC+k{m5;A| zd_&@zcQG$fQ)&!tDr~rfmBxhixmB!^sT~bC%wH9m`0Tk=esrE zD{6{ka=WW;r<#^YO~cEwHoZVb|Iy5=jhbKf3hPPe*(thvFpgENoJiFf-C5m}?DN6v zO8=x;USR8IOFna#KY^-W>==)lcj0m?B{vd6ZOjNP*^slF(gyW*f@nM^sM3a^ir_iG ztNFQnEPmYh48vyrhR+NqlzYTTZv&qeo*rs<(TC{hF?lD+N4f5VfXtttjhOE?-MJ$L>{@ zH|+;1XAgVIw#m zfFBY8U){GoSsAvDz;7KJ1ggpICVNOI1!nUJiO&=yvX9Y5)LclgycOwRW!P6TQJ#Dj zY4{~fyTTT0iOw6cGW%7A@L*mHznngf2(z0@vUCG@#XgfOvufA5aoPD;2vT_dVg0iJV}qzg@TFGIS5+C4VSEI&Gd6L z&^y}$_{Ef)2!_egXS&MKHrzcJ3wP6q<*_t%mtFN0O>IUi)QhxCUZO}`0hmAoRxki% z5AA+^xn&$fBc5RFqiv42@MumLZi!YPwV)2N>YbJjq=xTBXk=fSNo=IuNkpztj83}3 z?mcE=@-@=0XsTyaSVBQ!BsqrQS*Ay@%3IGmljE^$3){edJ@ywf2STL>RAT7|BNU45dkg($s{UR8}dD;U1z%ml#Z< zZnnR2&J~9T2%o`<iFWMb_OkPXcY-1qOW$nUSGz^HdsM39IB#}Mn8V(2XA0q1WTn}WOx8fHbPeQU% z5fZtXD6a6)M9t@8{@2z?`gjt8JxrRZ2`%5PW!LMonc42HG|D=jfc%cpF}!ihB;x`4 zo{3SU9z+S}XDbc(Ha3+#EBf|Oj!=W>d$&kLWn=NODn`O3M1ntK{K!h?w6ygJzZJ3M z(fuLC6t^G^X~q_)@z9ey_m#BLTZ|p#Xe<8ZS@it`MJ~I^_WjCQvxt^gGHTF;A!%Tg zYWlAw#TZ5DA_+J9N7Cn_nCFCWf}mpwT`+w1Z)isn#HX;SDzoRLoNKCcX~xwtjcfB7 zPoyCqbK*!@&9&L3v|xzF!Vo49;RciYXw*7VooTWD)^;CfFIkb(VhVNK7^X#B_5Wz zyRcy1ad{W{6DE#5KWddVo6czO)22q^9cxFwoZtF#0F#zJC6#pLol)co8t`8va@lwI z64yY66FuIDhmZ%YH1m^va0_BO&@Qnb%RQQ?F(_hQ$Xg&#vP-Qbf%uV&dE(j3G@&v!nu6NRh41o$^mus>t9Jf1Q($>$N@ir|%AT=Gm$R9O)XkS3y(pJ!Uo=W*;a zHR4tuUww}dw)lYV3D^1+8n7)Qdp53+U~y+M4rjADx|Q>7{2`j)59VZ4DZNcTCIs6@ zRLZtNP@KylWcceyaL{>k<;5Rm>t~ z-36M5E!C37w1_n??0ZR%G%K#abmDvicHxk;lPm8AQmkK@>Q&II*o@`N=<{VvBIF}` z{JnRLC^m{wySzksE#qw>_l^8Bb*oVZ{6YgdM#QRaJdto_?j}MlU@-Ke_qVw9C?^=& zGAo)+?t2Spz_gf5)fa{L7lGJI1REP`UHITl!Ysc_GKLsxNq4!`*<&U!=8Pn;Pl+_M zEW8>kd&{yRb4ei#23UB3IeDOciQsvj(NONYT&s?!NxHB}NNGc7kFE0nO)-E?QKrtY zikPr8lEg4H8j>)_L2E>K{}(Ss?-z&1)}*l+PFv+6@vt!Nwx9Ffr3Bf946^csMc7H8 zJs3|VBfFJ6`p}S;dXdXUc&C~P@WsUYer$myeGy-zMZL@*z1wvmooEH9cbjVf1GGPo7vI>|UbY!kWgRe_FJ@JnME(w3pgTNK9kIFHP|YY{cJav(w%kb!Y6fzg)@ zkUfLg=R*2?y+W~4q8NX@=O?1r@QB`FIxk_4-z2IvXM#a~Y+@_An&jeNw*U7ZM6qec zw_)^MXXdDT?_LbXLur1G!`MBM=Gsgk-oV%v9t9KUyq}3%hel>1>uW0qk;_Ol2eL`n zbF{gV{7GS2jeWO58H*%s>X!9-*;LHcTZ1fdt8)dxIN^!uL_MNu0t=>%aqp1+*> zo(#;1|E#A)Zis{=`)WeC11CL$pGjEuM7vgaNJ&s+039$sViX~S5)|o0*11VMqB_l1 zYj}4m5$^%60g2=4K?KeRG2DH6^ZllTetb9+6WSuBL5-4*ZxQ8wjo~22EqmB!#J334 zZ{zu^JGrSH_Xg22*Ro|Q=w&Llij3Z8*eY4mDxHB^o;lb`bNw4Jt4~QvK48w^8Ag(S zMAph^uk)Hj?CsY-+xwBvK=AET@T=tb$zJ?l#q1#QNLr8zV#7bm1mSBB zkqkafGwf!BraBF!@Z?+~@K+HD$d>g^I&T#O;wQ=q6p3a$kcXLBO#Z?>BB8Utli00~ zR*@wJrHlxt(hA!d8R?X+TKySB#;wuMYqB+LhK@AD%M1qc%4?0PwI+3I7}-kN4CN>` zk95u($J7e@rq${IPN9iDXL?lK_%7+$^&wQWWZ912V6xU%wr&gjLt31%A;W`V~nNOlJMY}{o7Cee zXYpZ}vltY&dy>ztMD3oMkQ}aM=v9^Rqrgc81%KA^TI!hU$5rEn`qDxlg$ot1$*O6k zl)sH8GHr@*>sgg_3)>O%OCsinfvz$ow785Ups-r8!sjG;)r!p3^;3VHR(`#be*I*$ zd`V@tt>3V5eEU3tK$y;K)&O#zB8w%fJkE^uMeeLwo0Z(3?jr-xPEmyt1(G{xm8DD# ztrSDf>=zlE>CD3lPl$uxIE1~<-}voM-jx=u!W?bM%!Gp6?dV98gYUu%`Iic zYEdlKVX`T7;*vZ5Sc2kbX7HqLDv7V9G}G3|itKMI>`3}{PdrN2HOYrwxsz6phD_!N zNi}B(wIPJAigmjtjG0Kad?WXim_IUhk*LS1B3Wt0#5t@BVQP9aiSjjEPEt%x&L?a) zv5$kfm_9}yyD37npVoUzNQmY}@+`efIu}jToZx+ko1KzA@@;lCb#pL5IxUu8Dx*(U z!t5o%y+9#N_`;g9kG(I+$7jiH;kl2dX~b9{-{WH(dX2Ez#W+aSD2i#DPu~YK4K7oh zg|$S=_n6%*Q4>qu>BpC{wJX%8Hd6%sjSBR+@1y=g;OE7bC`^NqXFrK)@CY(P53*@$ z_RO3Dw1(t_ZDv)dB#2QJYCi(?kVxcf$tzz;x{x0~E)qxDPh@X%#mc-#EE^ZovgXQ<5>R=M$hadx#$2n{mB@HDV=Nt} zlKgmx-tpZtq+5AkyZ69~iSEP;Cs1)qx0>RX&-e4CIIjbzJiT4WW$rsdpmn4vGC!J# z4$LQ&yooV}Hs&fdnzE1RIFK(vlW-TX0kQU3_MHwTl$c<0e}UwEOhj5?KL%tnQSulD zOE!R(yN%sI5Pi$kEWFLa7F2*f(U~>78Q+>P7-}DMKZ!`>A9DWJy?Q3Eg5pv@|}}A zok2us74b7$Fs49!GjVEqgcTkBvMF7L(~pGHBWx-8wt;fDqA}@x1+z!l1XiuC?(?*( zO=L)wwx#f5bf%TnTn}=wAQ3I&5-jgswq^<-6D70-M@Psn>H9Acwqf|b9Y3a+M2%Bo zx`$7HC^_D_G{L6~zA9pF1l}gP>vdUp*K2%c7}-0A5~J; zvN5KKphq!yvSO(0Y1h$^Un81Rohb=>0&)4u$tcEmc^qS0J&s5`N1BQujtk$s#NDf@6JJZA-iwIacy^ zj8d@Cf!3MNv_|e_{jxr4Qg}e-Vhy8mWx1k%tw{e4kBv?k@vBt`ucCR%B3Y#~x&qL% zG|ip}r(U5~p$g~#!s`AQE4erCr~2jqLas$LQto5jl_z|rlT8Vtwd4!L(w9)|-|NKn z`7u`2Zw2vcI@GD3*Rr}!H>;6SRq0=SY7Cz(>{b3u^Tj?KX=>Iz&++s@uG|7<0|qE1 zhtmkGSrKMouq?~8q(}HWp?G~lYNZe)U4x&9s7sjShEsCMr4Au^JsCVDJiK!Xfm0fv zu_;0r9kGk))9XyYLir*p=OEmP#9|bKK;Fltx@!)@aRkFb5x-<&NJaqJCNY^7yPBzR zSRNB8UuXLINF;a_Wc_-DYL^2_V=|NXai-@U#TyV^TSuVu=#y52Se~?dMeHFXkOcHG z`uP~PLR6Z>kl8^5`5+P%$_fy$$~I9#BJz5)O17*uL6AT*ge~GFi#C~|MXHQdX0PF?k;)?4~&`yLXV3;QKBU>X}h?HSn5JJHuO_}B1> zcRu3Byn^9P^QgLDk~?a|P@1B zG9RI^&n2qQj72_-X4aYo_>C0o(ReP}`jo24!)TsCk#5P01GT53*O2~9jHjXXk`R4F z0(D}n$u&oOrpL2MkM~CVW;S{6sdY%@G|9FYob1V7agaNcu74ZRm?8wVxLkus54Z6# zwUse;ra^rbJ?mE?&yoz_6~u=>W0VG#CtiN^iMA(k*$cBVOk8%8KomxR$jg{&KxYgI z!_7?C!oVy0eQ)}Gc1tnyQ-~|QV%H zQ0^{XLsZzru#`I|H@odft|}vy3ZIyxeU;(9nkHx#!$`sHo)t>!=t^Sr3^qXC(BUim zO5YEQ1tE0lLcvSAhSLa?gV{v#sWBONQnnds(0+?`x3=)FLyUbk;uhKFcI`V>V zWKQIb({djFT}Jx-Q3Q+h8l)4>aP38wq&epmC6swS@oHkzs%U~rSzTQ#&s)+wmoxFK zuANNOoqj?3_evzBw5!lnGi5oMp6tjdD>r0bxb!{Ic29(EXg#U0WAubk45a}?k|~V1 z*#yjRHsVVX&`;G_=s2ZZyy!!dtmna^oXzJ{0>x(PTB4|{j3%8QF)&OPsOq?#78n%4 z(5Iv<(OqZ_ajvPtn4W4f>Ix!NV@4`U|5WnOsO*UI6_a9$A~K_TFMUnLe62}XD$(JE zB&CnB6|!a9Y?5IF!s!t^<<&zKN9pyP!W2<0A)8Aw{ukqu+*l~y7L~IMrSAu`<-^-A z+$Y*Z)BnIYP}P>Zknhmfe(dKJa$Dd(FCyrFh*{iE7SVEhH-siQgNd{}d?sAbdr6+3 zh`B7iN5widr|%wvu$0P6B1fr|=6^2Q5-6-0CJJ++WyeVsR`^IaBqC#TD@}4t%tx{m zS=S}0=Qj{9r?XjlmiOc?U00gs#+Z{b*_(82exV_!$Lym0CmfM;T$)G9^-nCgq@z_O zr6Yz7=er?2X8(09wKF-TGreeY-5q+P?=vdP6O<}wJ&4YO;}fTBX%rnf4x=+(iJ9;HxgpUF^#2?2lXc1O~k3KjN60TlDI|eev05|k;AE4D}JXF zvz~}aNbaht`ppT}yE#gUir~5g$QCC0p-0Pv<{Fax6862Klt{|H|4pF26VpQ0DbVLg zG0!H&ynubKIj-hZ0>4ibb0ht)E*K>8v$OTT7!(>z5jN!I)E75T$ zQ~y3CS~+9*Z3N$%2tL|$$leoKNlV6J0ro_)ibEW_`vS+jkI&ffdoQx)?MJdnQ9ZuSk|Na#FNW*?Z3? zELO$z3Xi1f9g>zrs;?uM!dn*!mJK9m9LDtS<>xUvH6@u-n;OJM zNUh%!@9om{i9~S#eOuX<^3ar~=wD{{?n_>i6o9bFprDU$@~KtJcs+fd!%SaTTAbTD zv&jpudGGf=hL{`xwt2sKtWQnHQJV|`(i0_(ve7!iX={!04b%=3u%G{k^KzI zrj$M~`J_$@x#?_2hl6O#x{|PMz=f0=l;j-b~C|dv7O5W$Rjo3qgyu<(*oMM6~%VYP&f=E6k)uSDRKOnSa|k(N%$BNvWiIIs-q~%f%$m?<;_^Nv-QG}Z8?+HnUsTVJD%_Tm|*R~ zmZ;9NGi+oVs)u6chEz?|ZX8UyRK=jE?h3>vd6C5KD+WoTRIP#(|DV`ER+Os|QF-_G zI>wCwTq;J>$0ji`s?NTOiph(6U}>I9V+6RWyKFos?<&-E=K z6h`x%kxqBfvEwu%QUeB`Og}LAHqhs>5pvnuEH!)euB37_BHX(pHJkZ3{n9ETi?l zVe(p*Y|dLriqkS4AOq)#TD2J@&@VDuq_$Q&nJiHi`v>p|9-~J^%ZFzL~i;lLT$5B9^ zCNRj!`B!fHeMo?x7|8(zS(M!3Z1QKns_NUL|G3O}cg#=HHbYoj|_DsVg;!DT`%#0};20hem<2M53 z>u5xnn4q9JCx&drYz(BrnN+(rJvwMrVcY7SJ<9W@{a3@_LYic6ZGrG9}fl)N{ zIH5YqHZCe9lu@?N!YJFA2;G6*(>#x`gGA@nXtxZ{5xEtF|I&8(O-zkii!dvR9LGiA z$}1L1+0acykGEp^AEql!0n1(~Z^9I-Gu znB$%PPD^f&W+JH}E+}f#g_g3T0Tj6Cp6E@okrrCdtzJLcPnp%blnnW%Q>j5P9TUmL zr~il)gJMecJ*TJSypls(Lqm>_6*}CY_Y>WkNpzo`gC|dl{6Q$*8H=LaffGJs9Wp^z z#1cZy^%Ao96-mi;j4@P;CA+++tr318N@e0%y7x;ffhwBf_vowi9Fvg~mlWbszK6-M zd2Th_XS9(CW-N$jjM}S+a)UW>b8h*|EZ$tUO!g8nC)hu({5_w8P6Ih}RMDVY6tc=254BXG{6(aFmNPjdO-@+$SQ5om942Yn7*OMB zy=DSt&>!$?JMO@~qZG5r?Lq=&T#AYHd_u=l5oP|wclmNrh zg8F$~`uY>>$(=gbnKAy@p(Dn~a_iEX>nk1i|B*JUNKmS8MJ1aiyiHbbBGbqUiYM{S z;Z#C$IRn1>i5-T(a6+Ik=1b_;gn{Q=zh(@{<&TW`;a0_MaGId0&-SwFYj?R9RVI=l z>8|ic%8ODxw3Is9zBYLD*a;olPo8YMLx+yfOrV7Q*r6GsUaOjFjk_ZPg*oPIIap3h zy1E4T;SsB4C@XnW9S?{t8@*(Z*v4hUx!)L}!}g<$%#YFcZ(?A{ za7yuKDpW}@&S1nK$S;cz|A+;E0)^^v*&_jI&WJ{u zE)U~T@@O0V{zqjSA^RAePIl1O`yv698T+t>U@dnL8W6nCM5L1ijwB|dTqX5+46$en z6BVtNBEAl!iVx(jsJO5P(OS(J^{TzxoNfPV8rPk%Jgk#bH-M$Y@tKhs%(ncJ<~=DH zztL_xkS(b;ih6+-8W{oIyI;j5S|x$}He$pP(U?$|6XkH%(1_lVs?m8ix#d40X%h{o z?kSiI;~zx&Sjre$!uct)SM!-PR18!v20dPVx=;iDbnLYMsSn1ba>XR!?Fb|$vK z1F{e+S>mk(%)nSWW!xiaFJB;`c!9xN(T*px?<0T@icqFRafO=ZolGRTfc?5usfZa& zzrI@K?x4`S=3&EciM8c1W3uVhq}%cw@n)8S2;F{3+}it{FliO30L8784fSS%Wf6mP zfP&{$^mSJ}Kb->9s7r5Je^)fOycR+i7uCE&Z(4qJ%&RbgT5ILniNv=_(Oh99RyFCe zq4QHQV=F>GHDS4rB!8!j>2l3eK5S=rmezS8rhfIq1d9K40;%7^cu3Z%R8v8PG~|A! zdF9DK>H);Rdew$MoBrnUl^+O~f|x4uc$L6pG%auyUw|&wsTTbkQtw5Pgk*DyImV`l z1|1($Ri5+5Gh)mnI1XfR$co+lxGNVCK&zRgR48{2@282bQ_emmA^R^)&?iUClpaD)lbAJPw<5wiujdY}4mQi4V*O$|NDD;u-inX3k`(7e zj)aV_FeIcpbdF(=$)Au8ImOnC36f)DdXWey9VTw1d9I0topd;CrlAH4zLU}%u~*iP zS0xpF0&(pf25(r&z~G%p_{`;=kj(0_?|lf4$GChcCr4Rdw=5P^X+|ou=qAI_O$glu zFFpPO@IgGag$Bpyy({5Ze93G50vK3&%z4gmnzj(RbuRA^_OHe>l6FuP zgrs&3ol-RN?U*Ta(^aYa{vT1`jCjTUg%$3lSv1D@g#BGaoZp-Tr&ejzXrit$spwwr z_{oft4-=)fF-a}$!;595<@zczY}u@kTA*1$Hs>D3aVmXeQa*&f4r6Lw%9HDTY4R^( zN(`jBaP?|He}ZiQ1HC$DphUw~(U{>3e!7v!)<2q-C}UJC8=!9R&k`9QiexQ1<|y0D z!89fvJ4OEo=hu_umMA0p@U!1C`t0)0@_M9tDtVQLtYq}6P-2dY2%Dc6t^1wBb4K$1 z`UXbM>YfBV<#`$rYb=|-RM`M3Y5K`Ad|{i@@`XYctc zXM@v7=MLa#C>3un5flddT9M7F^36lummA5^Ad?rJT+8V9pD;40FBqIh6qv|x?AfD? zifqZsGnM#=Fxal@7Ij9hRk^y5a_wNq%9Bt+Q@awj`+Q-bXmDgsG-<*`;VXbq zFiE3e(wAW{X^$eoN&XKY{@)OBtR@(wSe>6q$ksC=)e=%Vm5`efBS$-3n*2{CV)!MI z=`%KqthP>U;C*S9^Ef5<6Z3tF#{C3T?xTDd!M&6WL5Mh?$V1j|ieKB8ko3aZ(Lpf0F5a@g!NBl%SDKa6BB% zA{$OBhnYiYijA?#OHn1wsU@e>mQJ>aX-$RO;jpCpHS3Q=c~k2){rR;s4qanfr&kgSZu40MU|+D0#$re!ou(mJHRKe^ zlMEU-ar6W#hw(dTlkIG?3t0;jM$g)?U()>E|;S7DqcZGOZwdayWgvrCrTJ{HkBa&U4J98HO3gJa>(=Ba84_pT-BUlEfv z8zNF+YC&}UD8gP=&V+iDo1W=Kz^`U3lsWK0%z{iJ7H*4>lTV1#iCD42ooPhZXhgNl zw(X$gr5`2|6tO~^%Bq3fOs%FVK8ckmEai{}hDQp|BlX$Js7P;&Dtl%}BHmC%y~>iY zhAp&AJqATL?q;u}kCT{52y32t@EujgZ(B2s>aKWhjp^%5248Nm+i#>#A29azQ{AEx za*M8si9ly*8R@9SMt(;FPgXFMRZq&UHiwY8CYF%!JXz~O={uroQ3Q1u@lb5QSc17T z6OZUxG!v0usFq~eS)@th#>q?318WrN!JNNQw{13;tiol}+(j_&Wekv2E$s6>MBn?^ zuPL|5zUuVj`J8w;H;O=*UK#IVHLZw4moir^z9!2yEGA$WUQalcZ_tEyvL*Nb5LX=< zxjoX5P=^w+K-u_t4+BnmA&Ko{04e-7ijMnlaaklv$ zv$ZGDBn{$8{;y)S3u&@lk=W2>h3sWgHd${{#|072p)#qLRr4v^v9*s(aK{&;+SFud zE8;q5d2J&qb3T+nyn@MyEYs$R^)u-EiHvQu9Vh8HySRQ{k1CSZ5o0EdA#wF<3Rus| z{UhZj6g{KdQo{H>M~th8grK@3UV?MalfM2O(>43ZOJW~1h`VzmdrhKGdx-KB)IUVe zzZk{oS(e;428Pm}w%|0vjry6{)OzJYnf6{>gJ6s5+h$?wf=msmzm1p_cIZ*Ge-L3e zB*tzKzofX1u=*>OCwhKY-GPP@D|#}lvwbpTIY}*Ni$_VGu8p?XFjAT8JAY4G)zApq zu!vm7la!6-|50`pU{+OK7@oNd9ny_7O4ke^BHax`qarncbcc#CB4VK;A}WG~VpA#z zN?3^4Vh3WQQlj{a%Kxps_C05xa}V54p9i0{=Dc^Wz1QwI`@9LO8yu^s2kzv%tW=^v zmYO3jfkYQWlXt$~Oh-&BZbK-O{Sw-y9cHdx5v`9HG;?ApN37751!5^}**d2!lRF39 zC7a9O_dK3E%vD06GBp*x$nWP&zrK9}FJjF=<}C06F#bHlsPrcU)XgI?r^Od&L$)>p z8Rk?vIrZsHGv%F~54?!PKX2+bJQtz$>*89#1=hi$vJnQFCc4aNP40u0o4hb|r#P~2 z{2f7!c0lPwVJu-w`7Lmhyy|2&jhm#0HjO_*L3qp$OV&x@8kFDgY^0c!UZ>DGU-F75 z>qkI8=2UeIncel|Vu;xc=W%#h^$RovCA?V4gf8gJ`S^V|C%3|@zd6ub4=g=v_^=7% zrpt{oQ*znC^38s`X}4iRZPXvg$Q6FY&@G3+MTe(RF*-TrIx}?C?=-Tps8jvqsun41 zfyyB_em&!MbPe5CN$x=q+r6^Vp;zb_es%o#BIn0#0~@_n@#AvdkK2U~gD%3;tG%L( z*SZpBD?g%IWjc9-kCF!0GPfghs=5x4itR3&eFhtA+@fNp_U1f&;bL|(tJ3_%t5@<1ze zAZ1q}4|+N7Yaf_*WQZld>e}N1fdH1F;^y%YlPWVCKxPNPsQ^28?+wW;&wFnOA*6J5 zD!(2%2+Y7X!Fks@wL>n+4IUUdjAByPD@|tA0bkq+E^w?stJ}yoguNMeVdoy$c-S2afda=ad@&+~-*78ycbJMKP`IBveOnj_bcc-gNc~x-OrG z3g8BWk;ij5mQsQ*SxrRMyD|>C`bUdxpHb_ceijp4u_t0awYhR-*fnJN3YbF z6)04pz@S1-((d)5h<+@5n@(fYkX?SW)6ZVxoN!3I7KQ)=11`g%y5Nx(d2#G@ACWOo z`0P(3IHR=VQMseVDPr>BoxiDpVcdN?jh82zt95-~=xO*a&Px`SmOX%U*ZAnD4lT(s(4kshFgeytc%P7N-vVEN= zp~N);_Op+fl|Ct&?n+-jFn5Gv7Jl2|U&MZ5AZF6TnnE64V*U`pjdT5Ac8?uz%gNaK zPFS+W85%mQL>SYY5{7SEgsQv@?5=i7sC|Llnpb{t3b?f zZ+qzY<2nSl&1aCUx~&!H39F$r&GaFZxIx%!3%*$MC6c&paBuWpy{F+MEN+aIIm&(U z#(TdXWywWsibb|-Ezzzm_e&Y3KyuT0;w#}Fq)n1Dh?;Eeg*)yl`)f8t4(j5_O z5)4kyH9E{1gma(cHM^G>xfq-mZtEY&AUQA`IIbrv^&9;j6g4F@Ni2sX?r~gdz5(hu zbpZnS%?|+A;03#Qc^$jGzqW!d(OX$b!=v6#(70kRGtg(|LD=s(J~Mk2fg*Szh#Bq_ zuVHwz_Y2g+V!pr3SUIx6yApZ-ixZokz1-IIAsFiARCjwqH=#S(0+&DSn?s>CuZl(V z)ulm>3uI33giipx2dkGjjZokmkZe$t_oD<$_H&8hY2~%BwB0XOayrVawS>9q*kkJJ z)sMct`UWr4--gQds&CKssDbaO)Q7Xbax%<(64fcZosph%9UsGnQh< zo!20b76g1Y#Efsky~$6oQ_L$Ca)oPf@%2hvv)`&Q8eY9p-wY_1#+OxVMnAx-iGDF| z(+)FUuOK%-!_djz+HY5(rC~PB!v{`tGBD7b$V;S~o$+`7zJYUy72xhK9e4K(zUtfw zN!T>lZB*}wH>z*@)e-Zl@N4`slP&K=YEWPwIfkdh9IIy6EAfl0dr+jR_(e(&kp+kD zH=?1+43wt8N#*TG-V$#Wqc>Kfy+w@th(iTG4yIt6DjP1aixG?Uo{9MT^8qtuP-1d< zB@z>m;3b`M(bqkWGx{`g57Wu1f|gDywRw-MJC7i>k9v06_wAkO6#Jqmj(>T@(Y%!` z-JC;=#Lovg6~k-+J5{4FLYU+<1nqiscMl=gKtxmQV{>XB&8#=K_#O`%cu~VyzJP=7 z!qd+j4-5==U>BZN@rK#BwIqD|_Kg?={Om?t?pkw~z8^%)%lVmUUWt{iJDit`ke8eM zyu^(=J%UG*%OfWbdez08Ymu$=z_q*GP^i}U#`>936Z$?<9<)(I+!)JQxZt9m*|Qz`~pp*ESJ+29g{@QPav^`jzAj?3nApFkjHGb+%#J&#a^_&F!949M^* zFcEqQ;mq~Qmc6?wP__;t!Ta4D4y?a!!|!K1Pdf)rM_z)bD?O*nHdbgMA{8Eg&;lg5?9YkpU+EPzENI{~fV&Qqis{^dpu56*TZ;ghPssmMa;Kd;Bt<%%VOiMqPFWO7i=p3Ha1;8U_so>>nt%n{Ut)sm z?os>#GyDC9PS5oO3Q{A6nm+JLF9q>yPy%6hLgV+i zQ)}bzcqR<4ilZbS_6i%CfS!TdKL(<-jdQ|@zh9Z~I?sE^nxZ}^nP^r{6B?x}08V$? zioWiAqBgvC(k~2pjxIE#xC|k*@k#;K$Qm{YT)^}g;yf&nLkX``?ZFhPRu8+eK5_I! zM-XB^WNvyaRL(-f-3ukH7H?t2qD@Y>v94sQ%y; zRkPI>o(%Rzi?zk8fbw=bUf6bBT^Yr>u>;5XHp1U^ytY_B z@)uroy915!A}2}SHf`j#%&&<12`78xOskVUPap@HI|lLf#vXy0@`JE;pYwb9tV0is z^1LOOK?q@;lL7Ig;%+xq1i7%@FGhOOFLH2UpOnr(2T=u<=DUf=#9-A4y$J%C?j^z7Rlz7TG=}^f zWucl^Rpc8WG6ZlM#+zZOt7EB6d-tspnPffg{oH;#EazvYMt6^v- z=qMso$+y<7N3idfn~^Vd0?{HG>P%ll7;_x2>M1nGEe#OLO@1?q&3eJvitp(b*+u;1U;iR~SQyap} z$4*Hf7i1Rw9 zuJ;`jI4@NM^)J)4WNw*taxs5uTKlpIZ?|NH-foerQVy9msi9wHkofkUr#WTnZp1l< zvoxPMsGpmYa-^_~=NOFPL!0Q?D3V`$Ns)=h(qMn5X?k3$=89(8kMyl!qt{3Bk=a~gr* zreSeJ^ddJyrOoN zx?=~Bg|de{pPCNM9rYAMjz8!*t)29`foVhmcrN^9H@FuxV;VOnuF7XSuY`X`Bps%7}mvwU6e1pwxiLOCLE%6;~uA~i> zhGU4wXHIV8YZUHsoxEspkz>Mq)HyWYlFOm;IE+mDWcM^Ma+nI}v=5UN;sA zTH_Whw5@@DN2YE$ygWv)6rPbxKn_3XH71gnP-{{Et;s$w@8r^qKz+|Zm(;|Mrr3vx zz&L3QO6SF;XOA2^+-zRz?fHv*o6-upXB&P+kmdYFP*RQnXG{(Zniio-q&a;CuD5XN z({?!TJ;yKF2zoP(8{n0l&SSa%$ocggJbuZKAG!hEMNGJ2qYiwt-z)tx7BYQp;@cA~ z;pMje?gyGvZ|_6KvYq|ZYTIF47;*k;15(|@FQ46qgfeRl0$b%j@7u0%BYfe_sUbPx zn09^*>5I;xcVNNn36!V}f&9dQ@W>VWvLJW*1;Y$!Ld#+`k&{39h>WsBWuq^MI$rrS zpBM`tB)9{V$ivSiFnB%WB}tY65^s6RM2!0Q_RPXfsOfzko>}UaQFN8=k(iFi>ZM-U zla=Mp7#CsOubefYdmir6QYyUK!!eH`xLd*GQtjKE zo~2LVrmNX_I>>PrHVDicr;+OlyWorVp1;frU#L_+i4u^{DU*8jPw15NbVT@Fw_TPg zn>#YT9>7{BMdq`TE+A|5n_U1!$!QfP;BmWPp1A{?Cy-w&0{IdA?B!|XMz#~b%zllX zz?&m-4IGc@ksEhLd>7nQzzN^>e}Tc(OxT#=IBGz@%)mhV3$(-?z1>+1t;WWOR;?rc zilc>IrNO8hcb&PVYc{G(SwF@$hZB#KT!VPu;#J>vJri#F{S$u83Pc+F_@PesZMf$K zFEa9WNVp;S4biFVn=v<|2YR6uFw?^9m*S&CJv!i{Lo<+g^9g_)c(mI8EtYWuU0iM$ zU+@Au|xa0gE_vqXuJUx65L~VcMB8%nHKqXAcmZRZV;g-M9CS^~Alj0XZ z^E#T@pbNK{<4_c9I7LOil;?J^x1gA;a1zufaL4?WFjK+(wRyWgaSMAfLMh`E=-?L( zWtQ-QA6dOoCSo31BX2CF(wJ&y170JlFZ2~r!3fkU6=wn9;mxuO@)W* zE_l4y+PVu)pds$zccpR))ay$N!sw%pQFuDC>ne&cS~z)Tz5x?zPu3!=iavw&mcWpE z2_ERV9q|M3g0bWFjCS{CwYu^(L-2br>yP%@4H>=W#@hlCe%pGS9G z#4lwgu*k&ELow^=lY{$F7N7MpOYi$kxbw0i!YJe??ac0;jRcl) zI?j&0@wKu6XpFtSQ|4=*dwrI?XcAeYJD>yQQ=CZ4 z{SOhNetDDP78zI(RFB!dP24|)E8Zifbq8Q{wU@(Y&pB|T zKyKv9YA2k~per|;?Dk%!*;C4)*B76Jf4T<>tGg5-FE`9|o^}rG%n!xWg1%3rH8s^M zFwK(J`F8{-o}tm>`3UBDm%!b(X5eSq7N=fR1=z)JnVLEclbk>w?M4)RzgOkD;o-He z8>K!ae%|3Qa&NQa&BnpjrUK40b?S#z6X*5^b1rLQypL~lmZ!LM(h1sRc;a;ozaYP_ zato`>jGRGC27I~MZ}2c=Jj10X70{kFb==W5aAu+c{ISz{ni*KNcoJkCcHa!8QQJK zLxm%{V=kU6e@Z>PUp_W|n7M-gGqY~dxY3NsfqCR&bO|SX-=m>U{B+nQs2+biX=s-j z_*nF2q~UX?ehduUQMwxrIO#kc6xjFp0#6?a=99jp6}o?+FiPVEUK!FG6HPH17M@%` zfWnj!=$X+yg|_=v!=W`C&z$kqgj?X9#lCmsWl?K2G&??mGTy|?N3))aad&VFa1GM1 z*H0_jfZ#30jq$vo6LW7y6^{NaM1QMW?7XTO>d~seyPJH_9KQ`rLdpZU!S8|15X3AQ zg-`SSh9dBx*EgEm;{(O070N&hCzsm>%7Db9X*l=HV9<2eLG$b-Ns=@=Le19{w*Dq!F+41D61 zEzAwhl*+cqfT2!2+Xs%1%9)q)u8}}j7(*0Vdq%pq$9q-o4E<3Q+ce*SC~SJZ-O2um z=;m_!)d+pXpg=L3f+|wdwcp5{`u>gBeeZeEd;&Q%cIpKmw)5&UI3g!TqGlfRE5uo{b_l}!!K+*H#!7gnt9NQF<;kpS!zYXzuGg;&n>2jl=wTCwVtu8mWBHclPTICV(l)CTFPtI|_{N>4qMp89io>M!Z3 zzow@iPES3Oo_aJr^;ml9@$}T+(o;{Qr~aOv`bT=|$@J7e(^LPKp88jM>Z$b9ztdCy zNl*PZJ@s^YYDz|GYDQ`-BQ-}xYFb8W&WzMt8L7E3pvy?jn~|C?BQ<|UYJrT@f*Gk# zWyPM(imlIzZODpk%!+Nwifzt{J(CrCHY@gAR%}aFY-?8R`K;Kstl0Lf*b7;)7qenJ zvSK^4V!N_pyR%|1WyN03ioKE*do?TeT2^dNR_yhx*xszz8(Fb^S+O^>VsB-|-p-1> zlNEb6EB0Pi?ES3R2U)TGS+NhZVjpG2KF)$uOZo1{vVVu*HoCk|v&<`U^7-L2bRnlu z`11LUky%bL)1kzsXgW&aU4A)j+p$OR`rH_vpXWr%9Dob;sJ9|s_xNGRa(Vczi!=oD zlG7FpbjLoAqOvUx*wCY>p#!f+VCID13ik|M^ebzeS34#;H*yz!N8{;wzs2b1^@vWB zQ3msj%zAk5W7xanUn&f#!1=3Tsy{Cc48KO35aqB-?A?WEmg#{RiJw{~7K0#a@ZVUB<>6 zG9huYDqewl;P7x+Jo0e;|H%l^K#eT^bxTN(jM6}Az-F=_+qS8@#S9F(jbOw(?1CQl+(fN7kb(4H3itU|9%E#ut^%*&N@SEcv zb5<}gtiKrU$?aIt4gJu9@)YF5H%@WJwco*d-W}QSmg7eA>Y3w>rs69%pTlReu7ZW9 z{MxH~l#y*;Db$_bj@#O_cLz-v*rw$3V`>JDp(TXr2w<|4V*7EuKNv8wrxR~oOAmPXIe7RbuOxKnm2hBGKG9at?GXYSl5#cje%E!9CZ~?vj9;Jh zqiSkEXl{2IVvyHE^a?V(cs_lClS9*xkP(hsi*SpQ`031!sL%g;;yuG^wgFY*~Pbv2iH1V54YD}vhVq_}^dP~pf1aFx?IbPn9*G!l_L>^HAbMQ0%L zd&I%9xF;;8MYuw6uQ{55rEk9}XObUCq?AG&!SR5d(|EX0h}+FLw6pbipxlCB$u? zlTUIziH}ZK7l6xX+$}P&&a3%3!T%PPGJIw*PWa+r94zz z8X-R)bFxf!M9e@jVWF=W`u-MOPN?J|@AhJKYdu)x?eO90c)( z<1sCa`6>RRkBFmk7tg)+l;hm0wx;KQ9} zw0&U1s}o}Is^hIt0jm#B{p~zPZywlyAC2e3yyqR|JaoA6*n=Xz&550SzAZ2ytcD1F z?pGxp-vk?=4hW-)k6_S%^Bck1b|cC~Gq0hu`$=YM5-wu*!`@Ya!0?HZ;9-#O5!i|# z(m%Z6dK%1a{;jxLUj-S5&!~c~m#kpI|!;rU6dM=U6Hv$KYN}{UG3M3MjLxpy@zCt3KJ2l08y*|{^ zJ_s`{of0aewb1IrBQUkhFX!fp3DZS{cco6Dv|sED>(J$U!#Wvqb#&`e51H^emGWQs zXldzb)5pyl?O*=1)cr+Z<-Q}*mhMN&49de1zZdao;$^b*dqEekLEf%&(k^|PduFo; zs%Epm?*|25$+{oE|H{uIvyvEb_@*=b_l;MC;&;L(3@y5&Hg0sD zTeBc-HV4Clf;q7FhL`QQKEHintdx#Zp4YTR>py+&^m!O`ULEfeu1@?TKG*E0&(!VE z0AvJgHFw&F^uTMH4B*vJPJf^=ecx-&f^{M-bcRoWCzE5A}AuiS|i)*x@p3&E8!*U6-e5hUfD3qW+B(4 z;J${v@_Ayt%?vvGq_xH+!CdDl7hnx8qQ5=rA zWwdSE;H}<+klhzLZjnAE_!9m@D4$tQWra6Pg>=V?=b}RAbK)D{ZE|0ToSq}CWtqfN zNQpCRdDHZWnOT>0a=m9D+pj?n^sxN~i;k9WiZ@61M*SIcGsoF&-J7lCr15IEEk}8F z8$MYQKi~I|oa&6Odbhz*DPCchO%SvPSPb#j{Kmo8yZn%%UKOb&?OC8|wMn=ta|N8e z-YcHi2#?Qe9aCjcKz2JR9@xMsUF(pds=jOGbHdY{-`)h@eml6+=ox)SkHJ0qqo=hQ zIdb%LoJK^W|73hLw96?G{iT0%+V8oD;B!uC=-;=GyDnJ?WwNmE2HQC%zHTrV{%q$D zQLqu>jZktR1w;Hta+JY)CQGxc0xld9zQr~t>h4hA0r53{#|JMXkojI-+WYbYW zUM-K;h|Ljy#e$MkJO<%}tJnCvg|t`k(w^C`KMJy&e>WoKzj)b;zPnpsmeC*Co9VZG zrj&;ktG1&puI+_j-YiZ$y0;ufc)VB4?Pxx@wDtk=ak5hoGi52&DTwF6Ym@v8urmh? zBf`V5j}Yfu-8KNtpgW%H441s%kN@SP!)CIRaD=V~zzUAp@vMbv*bvLOSMI zvv0}=_kQL6jR{Vi%^Hr0b;PRpe#Cx&u@;>S2)O~3lZ*k%%yB1C)Wg?&7Pp@gd%oHnJsAeFo%iM6< z$q^SPq^=0*at8=~PQ6M>Eaiu+YGbBNo;fA)G?A=9<22Dra+;`Q;f(x6GE$3Xq!!Ca zEuN8DA|thAMrx^y)Y2KLWinFBW~7$ONc|}*b|@?Mb5`t^tk|zvvBO!hBU!PdS+QeT zvEyJT-s0=E&r@8SQx-VXbOhLLYM?lwbSllbsBu_-dGXqOwvi7>gH*W5Bzz5abF-c{(YL<`4$%jxre}(up@r$6mr53sHu?8vadOb)Mi$;6_he0$TpWhm`bEkBHY!7q2-jsPY(iR~Ql zR6qRoLbt`$~QDziUkH&c;VJ0CGj-d3>5D2PDC)~bi12t5tDnJ{MUiI+u`Jb zH{SFbOSEO-RnaDJ>qCCVnz>%YXA}w|gZKOSV_my-sB`3Wg%gv{X5c~!-=$=#wDI>n1E6Y0U-ndKLbF2jq4tM%~e8<^o0?Hte34U3QA6X1s1G^u| zI^{GZ{WAMGA#6g5jytX$B;T6!hWH;N{Jc)BHm~6ahjr5sz&}p#?Qr3x6aF)J+{-B{ z2}hu|Ac0$)2xJBhi>*ckhB^~C_jrU{v;V&H%YlKYZ^hF)op|BXAAw_Hy%4eSPSWH! zQ)tuS10WAOzL)C*I{3qfQ>iD^tQ^ za#4UI+%grhN%jU}biY$TQFo;(I4wm!l+1_y78prNShqU|RkEn#I&(*dlkB}PQq)Tm z7BE6zfV%<_y~9b7{W5C!w8FnAn74(o#5UwFV3#||HgDSpYUTTg&oHNuU@6m^91&(0I+rPUVuh@_9xZ6mz;omY|7WV3k*VNs|*|4zIiKX0r;^dy(SGHC@aMq^X zuz`KM^utW!2vz{hfF%ZR<#K+C@tK>t7xDO@Q{x69T(7OzgNI*ur9y8l4i)u|@ZZkF zw7HFNO{8tEmo^+_Yl9VRvt$__e;q_JhXyJz?pX}&=D&=zR`(4?tcEN_>H6ADlDhyV zefKra!#-|$&HJQ&Oie|KTw5)Q>NL$O6W9$7f4l56G=UfUMIye;6c|Rlf~XvDa;85f zC~i-%5-IKN*8w@K>(zn6_-zOOS!3r>PCTmYWtyzv1jgex;N<`JgL<^MXH zSR^nMyc1>WxStIOCEVf-h5ujh+>3*x!8bW-z;mU%$LL?fL)!(2=c7(3$aH(iTkx=e z(QZ)^IQ%med!EJOv@b@O>{yeuJf}*W(p=62}g#GB47UYs~#?24lJ*X zhFg|6V=?Cj)QIJvW5~j>eo-;~aJa6&D@k|aeug*N&qo6KIJwzAaB5f%Tz7N)C*K`& z7x?6L$52B99XZOA+c_PGuYX}f&>Oq$ zKxEr`ku~!UZ1V-jwvXdAk*)GA@#*8oO&K+O#_(YyN0{cVh%T9Y;TVlb z-srer-lTQc%T6E;d3?{CB|_7MB+lTcq6VySTZhn?D-T+a3Qobqn@3J!_rn+Yyr^Qt z)+e~*G#w6)`8m^9zM>nki#{F&popI@X2n4cS%v3x^N{YNpj#AjBc!elfzzUR z@7v7U64Sm3X@B4AN3eD`z!;q6^b{?Sz#lyKVA!H>fH_2OIH-{0pq{ouS;ukE zpuQ+8-jcx`aL>zb1awo~A?o7y5BQ#uDikUU`7!Q3?Z*&TG=v66V-dmGP6Tm{ckn{t z`Y0_A`j}R)9O|=#O4ae{}_daBm6DAp61*A5_-`5y@L4JPbXSjLi z5p^oDc(=!i&O0xhGG!z-sE6stDptg|S%=;$IBMIAT>I9uZ|Y(w(|RBRot?%TE7G!x z66lpSz{)buin(bBZ{j&6=oA{~*8Kuk-&pUhjC-%y*&gGwYEILP8{k4GsINm#|Kmi! zoU{!0!CC0i3OSujho0@b^mH#4eHEcx?1f^^V+JnYdA3=f)8KKmnyG1xhop?0 zJaf{FVR(0J+>CLvMyD)}rI}X?R$xzOzxiOz_g)D0o%2Ay+zUst3Yo8-44*Ye?+X4Q zK0bfnsTk(ChRKP9(Oe7Ei;MkYk37fDrY^FD7Cc^&!sR!9dRbB~_^Rt1mV@{YD?zAm>8(G47$zH@c#mSp?!7E?4AZIfCh+<5c&?K)0Qp9sD zu9^-{4d$Vc)^nQ+bWQ`^w&(klwDHxj05N^igwc~ymc$Tq?8n`N4T584=ckra4codW zgJjNjz4xuROpHOjZ@m@3qc?;8lLpAC8cpE8553;3f8+)BXe65Z8H#v&Th+mV)`N)h zU%s1Aoip97gOSM0#a{VFHIT%vB@v!cS-$1T59*h6|<}>{L zP4l%=Bo4=5W+Jomr@YwQw(a(<`Ni=d&K-oI<;2O;n`F$HqoJ>lKPr9ZM;F=mmd%~t zOXELSl7SE6j+Y)}#I#|f#!a7sVzx2<@Y=IIoF6|Ts!`Y)|IzF-{QZDA^eipOh>^q1 zvOwebPgccytC7>>)4bc_e_wfqzxUR7smJe+(-p_qt057@E;(W;PAnhw$LEY^N8l=^ z1-;|H{13`jm_B;O=t-mE4`;_8o^C36As^y0H>mB5|NYN1{C%UE zmh&?`!)Hy{J~95xijCro-%yg zH2m`AIBTCMXg^ikN<8{>-b?J_1zos2Tz>o!FsPe%F%E{ z{{8q*9zWxg`Q8(a_Wt-!rk&}*36mZzT+(=&ax~SWZ89E?hx5422`~3Pia&Yej8D4w zPi$~|;y+r|Uka3bq*}dlApYRiGdSFYGFBht~+;FKxxUrg~!kF|1l{Lzj5<0eoR zCg4X0<4=~H@ySX3;GCDvZ{t5Xai#~e+Q#dY`u_X)FQ%U9!4!R<&VM$J{}%D7yZkA) z_%R(lM=HUOasH+=KG{An-fpUir{X`!$}sKV@KK|t$yvmSlSfJUS{HwOOj`%jc3u(x zW2r&$!2J65MEv1(ejLV)l2+|d{K?g4eDbg@78*BuwFF)lk(1+?0w9et{K}tlv&~rL zR>cEeqiGm9W#%wjKi-Z%n(y1RMd6e9qsR1D`m%-I&+=ycSxYZx?XO;lKUu54%JOZ! z8-Fyz+S1s4rhm>S)#&iZl++kLZF@edXAKs>2pUWk9Hm=EIrRLl?YFBJ~DL58`_~OpPSgMM}AjVWI4l##{B_O7$SQ27R6-zD|tJoA`4HcU~JWs_7AfB&cbBHxnybxk76Q%x>!{cgVqFzmL9C}@Yl!t#Yy+`@ifth_RIwdIjAW&hw1?PO#SReDRqO~cL&Z)I zo2b|sVpA2nKy0RBSBMv=*bQQH6}v;cP{ke)Td3F*;zcU375hSL zqhcn+wkr06*iOa%5ZkLb0AdFf2SV(q;vk5fR2&Skvx-9?c2RLC#I7n{46&Pvmq6^U z;-wIKs5lH_PZckN*h|IX5PPdQ0%9K(M?&nY;wXq%85LKLhS*QVEQtM890PHHien)T zRB;@{K`LGjaj=TxAr4V-0>q&zPK0=|ijyE-qT*zTm#R1g;xHAbLcC1HX%L62I33~$ z6=y&ksp3qCqg0#)akPrFA!eyK2jUnN=RzE-;yj4sRJ;P>TRknu<9~Z7h3gp zRkN+ST-9r=dWWiuthz$gYpr^xs*A0bRncST-Cd+`h=?YSoKL&S6THbRqwUx)2gnv>UvezSapM{_gQtL zs`p!Uld2C`b+f7uTJ;%KAF}GRs;;%_bE-aU)h((%V%4pxuCwa%sy=GfZK^(I)$OW2 zZq*l5eZs0Qs`{i=cc}W5Rd=fTv{iShy56e0Ro!6KmsH(o)t6P>WYt$x-E7rYRei>) zuc`X1Rrjd+oK;^}b&FN^s=C#xZ>ajbRrjg7&8lyzy4|X8srrId-&XZStG=V^4y(Sa z>Q1Y^r|K@NzOU+TtA3#BOIF>l>dRLBP}Ntg`jM)yTJ>X9U$g2bs_wDsr>eeg)z4Jj zYt_$HeZ#6>sJhRpU#j}1Rlid8Evp_-^=+$ut?D~gJ*eutR{ciR_pJJ@s_$F%J5@ih z>i4Sdx9Sh7erVMnRsG1SKdJh$RS&89iB*4A^;4_{Z-Y^t$JA1FRXe*)i14j zRMoGndQ8;=Rz0rj*H-;a)q_?&q3SnQ{aw{>t@?+m-&ysfs^44nPgQ@g>i<;z(W-x` z`jb^psd~t&f2;blRsT`-7pwlO>aSKkt?FT`rlgww_lQ+fRXu9en5xIDnnTs&P;;kX zu9PEf4({R1or1X%MBMS4I|Xy4962Y=8#xOyCQCVTU=c5O3g${V(q_+Lc&Z5QX@#1C_!or3G*aK>5wo@f|LOXvm{7OAYqaOsVOAP zksvjLlrl;riDfFJv=I%(NK8esl0!u?lcu8B$*H0k%B7-M%B`Z9%A=y#%B!Ln%cr7P z%Wp({p(b}q0TsnsK^4VXAr-~iIVy^^!YYcjA}WftqAH5DVk(NY;wp-@5=JyRP*O#) zRtjQ{Q4)pHMv}jkF_J`}tdYciIU|Yr@|(x{6{g!-&SKO;i+XO(EtOD_(78B>CF~Mv@3LHFYkZUZT8tnq4F6~#(B6~#<@6~#^m6~$0T6~$5~ z6~$C%6~$H;6~$Or6~$UNBO0%ES5d6>P*JS)R8g$;QcW?MiTQE8%eBRVk9wssgcC?Fe8cS z%ZwzJheJx6YP>o^MX@qcMKLo=1qSzXzq8PheMX@&Ch{mfE zR1|9yRTOKJR1|BIRTOJeR1|AdRTOK}R1|B|RTOJ8R1|A7jcB|&OGU9Z8)A;>;?+4u zlE2M0l0;yhk;MKLMiTQ^8cD2QWh5~^-$-KnY9op11x6Cf3n8UVH(t$FQLJ2}qL^8v zqS(1sMKQEkMX_|9iehSsiel?}6~)*MDvGrmjcB}jlZs;PW);QSQWeG8Eh>t&TU8Wm zx2Y)BmZ>P#ZdXyPEmu*j-C;!I)fFm=wL2l^m@QsiX(ajET}F}!+-)SWe~*#G{3;`f z^?QvZ##b9jY_Bnrn7+?QV)=eZX|s)2A5c-OJgB0Wc}PXEvsOhh^stIz=@Avh)H)T# z)}tzlvBy*tYmXbzc=ZVt#oCi9inXUy6l+hbDAv}iDAqQpDAqQrDAqQqDAqQsDAt}a zqVejp5Od5CS3YMXF}uY`Vs)#L#OU)z5}VtMBqp~TNi4o#Br*7+k;L8(BZ;}4kkaND zSME|#tn5}%%)F$c*m+q+G4zUxV(C>C#nfvmimg2=im}&K6l;5pXk7V*iehb_iel|e z6~)?HDvGtYRTOLQs3_LnRZ*O72UQeH->4|2zEx3d zeW#)r`(8z{_Ja|P(|%M@to@{-SUaSmSo>K;vG$9KV(nKI#oA#N#o7@S#oAF7#o93= zn(}vCMX~nRC~O17ynlI0ik7EFDh9!Ma;IWsZ2rY!^7mBp%qOx9mCK<@QB-M)Dnn6a zDXJVrm8Yl*6m>4B82;tJzmz=1J*irPXDiZVr35l6rz%ra6)#3-%g?Hy((o_EDHn;k zjx^bHo-M5ER9Gl^gvIkHi|2#NiGOF0eNBq0MNzdWst!ffrKoxoRiC07fXan`>Mt$1 ziRHBsMKz|Vbc$+1QB5hT8AV+HDmVU}z2r2fs0%5o1w~y%Q7u9F`54tkv`$L2NlLU$ zO0-W(bVy2cOiFZ$AQIcC&J@*!qPkL4H;U>`Q9UTCCq?xEh3&dP*$(#geepE!S&2+M z%@-mTB#Z|7fykef>JOqoQfdH*f=Q`?APRZZnOd;H6g7mRE~cnU0#sCu9F~;0EGaP} zDKRpFNUSTPC~7pQbMVh?BZK8AD=9GsMBz{v7-goS?Zx;rCq|a?UkZq^_*W!E2Ca=t zN{k0l)C=QGrDGyRO%6~|IXX2dF)e~f%#G<3HG`sNQq(MpnoUu2Ko!G3x0EENaV|y8 z10^HrvxjvBMO_K1gcnxKNHW%mE`3+wxsGk+|7WA|``CQ^lbMhkPYE|AkIa?yzgX;Q z5Hb^TsbGm-us}+_%!6De(R&LPl3ccMQs1=ft1oMuG1UvM5ng6kuKj2aEm-s)*lUHA zIT;b|;{U*2C#=lk{PdlvmM>WHAK2^v1AD`NU~d#w=95HxZ~71H&HsU2`XAU^gq4}C zn{S~qd#f-qr#%aE8^J7#Vj{}^?IgFHe#YFh+9+F!{ za`%$lYLZ(+a`y>WIpnv9^xjW$50Ko0B=-=>ttGjKN$wGnTSsz_lH6k?_c+NtL2^%$ z+*2g?G|8A-Sz2_dLmMBf0G)_X5eiNOC(! zZl`cnlb63;B)6O7ULv`dN$wSrdzIu~Be^{!_d3b#CAl|9ZXe0LNpf$I+}kAgj&PVc z1;%?3{qMUZ_a4c;PjVlS+_lKbx`k~>6lKa<=qB=;-H9VWRW zBzIIe*=bBte~*#eagzIu?=q~C%qb7qFHXYcknm*3 zI0=^~T*KrX7W-o{*;`H$9+psJG1*=A*UX|;-xuKU3dQ9SESp6KMPY-7}+B~3sX!O*&#m* zQ(PF?A9tCEaa0MCD@k&tNUk)=l_9yZBv+2)%9C6Lk~^2=Dw13!lB-N|RfUt25^i}3 z)r0B;Q$v_mXAkFmf~iR`wF#z96cbSo>XKYN;aZro;Ai0qwH;Uv&lUx?b zjUl0xcRm)(a%qi+><2t6v;gu#YOmeJ;`k#xs4>ZiR3m5C+`C# z@$)kz_bkahM{--DxClRQCAsHGZX3yMC%G4d8=BnDFOu92lG{mgyP~)VKkp{Fmq_kq zl6!^ZUKLK>Tyx8FL^@t0xjn+kJ8ntBd!6L=3U_HJyoHJF+8ZRdkL2DYxwoRY2>-oJ za_^AbyCnA>$-OU}ym{#6+rmUYe?W5kN$x|E`zVTw@bkwc_X){;N^+l(+~>j(9mf0Nul zB=@gyBa^p7r%5g)#)XHLjo=8YFif z$(>JfHH9P6TT3{(&m>8DYe$8bo#>Z3Bv+T@>Irvw^7z#!xdtTHkmMSXTw~#ga+)rj z+#Zu8KQf}i%TCOXCM4IC$+aW7_QFj`9={GG*OBBpkz8kz>mnRcPP+;x z_a`OEk8V-nWhdracarNtay^BU+nbWauNTSnCb>Q&*O%lnNvN&GjE z$xS7>X(TtDL zakLw`3+s$DJg%QaHI!(+w}8UfxA=cSmvA ziRI-Ul3PV`_X?-CekMuDYMNXVO=c&i=02LdpC%tL!v8e`gWRpfhJ$1 z$sIJg(~#y4;v^~BMU%T}@+F#lnI>N`q`4{CO;JS8`YKJn7ENX+mbyJO`8rMRHKe)E zIZ2A%pvisFWOibT-lWO5X!31Cnp>yc6oqcGc*juYzUi}2?;6V7G<_E8Jwus0rd=vK zF}?58XM39LK$9J5vJ*{qrpYce*_9@{ z(PVd;>_L+~X|fkh_NK``G})IXGikCPP4=hB0W>*~CI`{vU_+WO^ChX9Luhg+ONH8i=1CauK@^n!J%FZ=%VY4QamAo1`o)rO8`p@>ZI> zjV71TW$$@^*Y0h)Y} zCLf~7wT3ib+;;1G=p@C%hBDvVJ`44Tq0ASz&qA%Es7DQDzRZ1=upXnR#|>q^-hGy^ zo-ma8cK2DRCkI7b$87MeU@hT@GAoYClDNXs8F1 zP*fU4<)o-w6qTEz@=#P> zipob(`6;RZMHQr|LKJllMHQx~A{15BP>&?3kHrkNE(ulKP>&{|N>EfuLp_!xtWp$J z+E9-t39F2uo=8HKrKoa-dNN5^z5~>14oolG4lY~`~3ab)DRW{W6Bo?bsR8>Q5 zND@{ximGm?jY-0)VW?!jKaZl$r>L5S+LR<-wJ55#p*AN8tB#?bNkY{%)U!#bdKA^b zP|qa^t06@-GSrqNVKt_xbVF@T5>^I9H8Irl;jpq3-$83ilg()I0-9`2lNZut3!1!$ zCR@^EE1GO=$ZbR(wV}zjG}(?O+tXwRn(RoEooKQ%O?IKlu7=!B`s$CXtF0w z_M*w&G}(tH`_g14P4+Y73*kHpt+Mu~r~!t0F-cehDQb|Rb|eXFFhz|p)Xs2Nxf0v+ zk%rtwkfXw+%o|hkR702%;f^-+?r^vvFK1EI7(=}j4lAN}8cUPoX!3HJ98Z%IXmTP= zPNK=lG&zMPryBBQB9Ergl{9%3P0pvu zs}1=o;m-v$nQh3|!eNHmqeT>TZ8R0p9xbNH>kPRkN&K#-s2eEiCW^W_nuSs*`{*$5r^9@JCLg4&KV-;v!YK;n z+**oyIGT#^<0CY=&XDhh2?YD%75si~7VKS7G$0_QGXeuHlPtxR5 zhI~Is{GN`cA}p_`$qh8QktR18@`G?{BI3E3CZD0nXKC^|n%qK@TMfBCoc2&jd!C}U z8S29%VQr_V7Yy}LIIM^~dC`y`6XXt>+(}#CMU%T}>n|Dd6Cy<~8}d_ve1#74RXWVq zXmSs2{dGfrMxTmPFT|Dmn_YseoZMY=Cg+>@%AnO$yo zW_S8O(J49Q>{%%6lsq*O!%d~hm?3`(=Rj!0pM#>(40R|RR>W<}IcYK%P3ES_JT#e? zCiBr`ewr*0O-9Um3esdDnmmUl3)5r~nk-6_#b~lPO_rd^l7{>_T;@adrxZn%rl>L$ zRn}0ygyXd!adoMjA%7*v@`gN2kQEGhgdoo~&c39_;wezxO`cDaHEFVzAx{!%uWiUb39=4N)}^i2qsjWT^#+Fg zACaPlG}(wI8`ESuO=i$!6Pj#Flg$kI7vawf40(zmo73clwDlG=c@b^Br6K<&Qq+nj zThnA4nrusx?P#*SA^#!L-hn1N(qt!^>`aqgXtFC!cB9GehWt0|&(K(=hoMe~sfb>y zCr$RE$=)>ChbH^dWTqjpF&F&WS47(T(PV#`96*x;X>yPuF(*x$qQNvdgeHg5M4n$plf!9p1Wk^l$x$>p+K_2P+OueK3{8%u$#FD!xgm2B zDH>0c6KHZGO-`c8$uv2|kT_b9w60GzB$ld@lGA8%I!(@?$(e>^QZ$PuXVc^ynw)D$ z#-H;HnTPQF6^6`9kXO>=RWv!DCa*RmlcEJQxsWEaY4RFFGX7j-$b5w7ucgVwG8x(!7vrkU*2TMLIim;O)jO$TWIoDLozA4jV71Tnev?=a*!gy&b#$-8Ot9-3T5llRi(YMNX_llK|2Fp-=0)8qp*`5;X` zM3ZZ2@?n~MgeKR~x}lixd9bNt3&1ayL!BWXKXkJYS~C zS7`E8ntY8W_t50)G`W{1-=N8TH2Ee?zD1L78?q#k@9)s$yEOS8O})wDNTN6$kIeSKc~qrX!1*%{E8+I(B#)Nd5|W*p~-J)@;jRR-jHR8 z-28zif27HuXz~zE{!Ej<(B!W)d6*`T(Bx5?JVukp4Oy1R_upvp1Wo=lYZZDv|c)GYsWO}3$}w>4ySBJJ&HvOP_9pvjIj*@-4Q z(_|N#>`If}XtFy^_Aq1(A~$;)@;rjSKWEY8Y?_=y zlXGcu9!*|BlULH@Rfeob_;Wr@UQLq=XmTM!`*?=Igqsb+- z_3LT!2HN_KhHOZr=q8%HnI@OguD)Zl}o?X!1px+(DB&X>u1$?xx9?X!2#6e1#@orODT5at}?uPLq3S@(r5Y zN0V>Tk~X!28<{EQ|)r^zp9@=Kch ziY5=xPtfG=H2DWjo;2hI#CZNsn*1M4{za3gX!38G{D&t0rODGYnUY)1D>9x>rO6mg z=Ag+mn#@U)xo9#sP3ED=yfm4QCiBx|0h%mm$mT@dEJTy%&}3nnEJBk-X|fni7N^M) zG+B}+OVMO$nk++;Wofb;O_rz03N(2xO;)7IN;FxSCach7RYP7#)Xi!%S)C?p(ByeE zc|J|nq{&(|S(_&7&}3bjtVfgeX|e%LHl)c$G})LY(`hn;CY#V?Q<`i>lNT7WMYwK; z?zL%dsEd+N7aFQ%5~>A7U1X?MNy2JLQLPNsI!Rcq4b>(I)y7b5lTd9bs-2Pb<(D5^I_^`WS~6qQL){V1wGMGc^+ zfrjdkq~r{usKFF9grbI0)WwGCm?ZX>P}HRqHH@Mzqp0B&HG-l>Qq(Al8ck7IhU%2W z_hTq(EJcl@sLLs8yrGhnoCy>)k)kG1)MSd9LQzvGY8pjNr>GeeHIt%dQPgaTnnO`@ zDQX@?T|rS-Qq)xxHJ_rcrl$Hwb)QylTg=D)DlB= zOA^-ghU%V#x`Co@G*piyVckT9bu&dRrKnpd>Q;)n%}_m)q;VNV-EOE}Ny1ugsNPAa zI}Ft)3AKWv?le^2a99!dkFGRiCPCgshj}+0<~=mIine~QA^Z6$(r=JOe0gjQP2NY7 z_tWHqH2DxsuBFL`!(`+))YehdqZIWRMLj`LPg2xV6!mm86;W5#)8q!4+(?s~XmT@6 zK0}kw(&Tf7?C;kuRi`y^cRM{Bph}`UVTZEU(w_Nn*5q357Oi}H2JL|FD1P6 z9Zh~ulRwbpk2LucO&+4jpA9*T@X{}ayo?}!rOCsz^&>QSl(v4%ki&@-9jD3PXz~P2 z{!WvB(Bw%&jv&(hry)lY)L2SZH@QxT=3BTaUq$<8#{g(kbwWH&=jC(_=X zCVS9iPnzsSlf4Z&gGf;yn(RxHnKaptCi~Om07K3s(ms$T2hrqUnjAutLuvA2L(U@7 zehE!pN|VEA@-mtnZphh0ibl}nNSYi)lcQ-eizdeyat@L9v4)&WkmG3ba+(}ZlM@Wd zq-Y{dPNK=lG&#kPj6bIuavtINX@75#zaRLoOi5YiM#2OtQiZluXgG`X23pP|WTY4SOm+(MIE zY4UlR+(whzY4Qb{e32%1(Bw`-E+*>cE}Gm;lP?+aI>P$PbeONuU|u zKWXxRH2D`zo}$UWY4RVM{Ff$A8}c^7pDB6eZ09n9Or^<~AsOpAXflnqp3{)G6Di6? zleuX!4^8H!$$T`KpC${?WI;nNC;VB6CeNYC!ZcZgCX3Q!F`6t+lO+s!2jS0>G+Bx! zOVeZ-nk-9`>0=+z^YYm zD?zNIVr7VRRjdNBo{Ci=)>p9_#0Dx>huBcX8W0<)cpk*YDxME9UB#LZGgPbvv5AVc zAvRU94#Z|E)`fV1iuE8iSFt|C3sr0Yv4x5aAzq|nBZw_kYz(oLis=wrtC#_?jfzbm zwpFny#C9q+gV1ik%>4s@NG~KNY(`?5|>1hyzsY263Q@-60NA zu?NJ#D)xjpM8#eZhpN~c;>9ZVfq03EeIZ_|VkX34D)xhTnTq`(4p(si#1SeEgg8>g zK@dl&I2ht+6^B5~QgJB6F)CgRajc4$Kpdyyr4TPyaTvt$DqaS0f{Mc-PE>IO#7QcS zgg9BnQ4pu7I2z(q6|*2tQ*jK$=_-zeI77v85NE1*ImB5ij)yo~#R(ASs5lYgToorl zoTuVsh*zjM1>%(|PK9`tiqjy@S8+PTt5uub0ugX4S>2F0<-&s@`tZC8{pB>h-GLVbvQ{U18N5RlU=yH>tYPsyC~8 zmsOXldbd??QS~0H-m2;T0XruId`AE?4zFtKOmN{Z?I}>H}82Q`HBp zx>D7Lta_KKYpr^>st;TB9#tQ)>MB*&S@m93AGPXgRUfnJ8dV>+>V2v{Vb%LpebTBA zsQQ#uA5`^et3IUadaJHgb%RwOR&}FQA5nFaRoAJy*{YAK`ixZ{Q}tP^KCbF>R((R% zEmnO})vZ>2O4aAB`n0Osth!#+?N;5O>I+ugsOpPW-K6Rct8P|xr&XU(b(dA2Rdu&j zpHuZEt8P*CWvgyg^%bi=uj;E--KOemR^6`Z9;?2f>g!g0QPsUx-J$9mR^6%UKCA9h z^-ZhpR`o5bzNG5gR()C3cdYt~s_$C$RaM`!>T9aLZ`D1jeqhztRo!pZy{dj_)i+fA z$g2BP{n)B+s``ml-%|BctG=!3XI6bj)z7W^uBu;H^*vR;wCek+er44UR6StT{i=R# z)eluYXw{EY{l=;vtNN`~KT-8NtA48L_g4K()gP?-xvD=}^$S&hvg((r9RQ=7WKdO4dsz0gvyHyXV z`iE72R`sM+e^K>MtNyC$|Ezjg)xWHIMAcJPJ*w*8Rz0TbKUO`i>c3X~P1Vy@J)vq! zmYGB>_+8ahtNx*C%&I3<&0*C)RZX+%|5VLs)xT8DWz|!v=Cc6Vy zv+8M8^IJ6~)%3pwteUE7L95~lGwGcRSv7~M=U6pO)xuWIscI3c=2Eq&RdcIa%&K`* zEpFAks+O>7K2=LvHNUE*tXe?T(pD{~Y8k5*QnjpA&r!9URSTaTlE4}J6N^3svWI*p{kv%+CtUNR=r5o zE>>-+YFDeaQni~^TdUgLs%=#5Vb!*(_Oxm{ReM>ry{f&f+CkMmR_&;2U#oUfHPfn{ zRqbchE~@soYFAYUShbs~1FhO!)j?M6q3U3(_EdFcy&#wdy6R zjSd};9i{3NtBzK6s#UX8oo3ZBs!q4+ zSXF0Ob)2d*t$Mktv#dH^)!9~^pz0i}PE>WSRVS%B&#IGEy~3(fRK3!wQ&qjns?$`R zZ`JAlXYV}Vq$sjKKC`<71q>KqcXr*GS!hHl4+%&O`4EXO4ffV&we)-mC8F>e=pQr$I$sKOe1n^iIq~EVTqHaIMWi(mEtT*oFc{9mN-?4b1ZS16z5vvU!*wC63>(3 zd`moEiVG}px)d+8#0#Xj&=RYp_*YAuA;m?OI8%xjS>h}yF1EzkQoPs_=SXphCC-)N zQcIjC#buT_Uy92uae)*svBV3dc&Q~Wl;R3Y{HqjKTH+!pUS^3GN%3+^Tr9;aEb(F~ zuCl}>QoPaKvB2q814|j`3 zpt~=+bqkA%MvjB9AB1`=w1Kogq&ko$px;;?QH1UR*6?KX50t~@=pH18%gOp+?iW{( zc@wK&jDAz}>lGGPl#QjSvmw=m#6k{)tio}0M2x!?eu>W&>xOL8>2^+uGBXxoOkb%0c# zr4b}{bi|PmJ2~RH5IZ{}rPT$Z^hCDDD2YsuRT5bq2dU18ieduU75%y+D$2&u0(G+m zimba7#ub-BIG%)}5fdtogm8i_w1IG7LTX3>Mgsp-hI%mQ(Rt5oceNq$|M>;g-xc=a6cL@DI8AKcdFH=Y5JpIx1?|c zuiI(1Kt~LaRz-BgK&g-?${-d-j2KG+4Tey!galg1KTDOYh#{81u1~iGay`@%c=6A$ z1=0+IP^Uz?KGRaL=d+|B7vO9Nm~`@_LQ3HrB~?Nygai+h$=h&w(Bw(9Y9nm3F|-6l zwltPp6f22bl-SZZ(jj~~**MaTgjAQ@(-M>^6}cQ`OT2!gl|+XjQ|V+19XA$IeR48o z9342$R!*b&#w&>qMDj?dsEn#>BKmbp#$vyMP|k|6g;bmsdM zA~~51k(^8+-MO|vnkf+Kl#DH-2&bZ7kNWI!8YFlmiH`bME?S-PbpT(KA+4p|s8u%8N&E1uak#g>a#g$o)bom5rN3q5f4#v}r9;62ZMlNrY*!k|_6!l|(+5 zD2cYprI6~ElvhkF$MV#REOSJPW;w*VC8UIK34}T&GM`JSKN4|adjJ zT4~XaEUrPn?wF#&a$2!(?UHgxFC)-d_JMcS7$i(74hG`HCTdAeN+li1ZAwm@cg zLO{Tiq=&ndM7q0`L_Y3;got^+HPHu|O7?fJR8&%I_t^?M{(cDXT`7HURubtRP!jom z5E6Vd!iUg@Z%OcBTcBgMSXMOABj{(1;miG_vP+|XBMa+%d5nhTDfzhUQUN}}7UL&V z!Ed$tbo=n6)u&>A%IZ@&{~i6TvE_8=)7<5InSZc_tlVdKn9sv!d3f?Ta{e3*%k%ho z?vAH={wHy~g7oeyuw zBWRO*le^<7;J47NS6(r)oVWG2`2dojdPk}%hx1+NyO8Ra1Jp>ie2% zmT=q$5bBVC{)d)X5u1HvnH3R(|Fg{K%J8u?D=HjAr_LvqRK(J!N}|v|QxYZkIV8+m z#16l(Rp*lGOIt-%`4xn$is7{Re2s3M3VGAIoo#SYqkGkFSRpT4-?Cz4;gNL2ceX&4 z`@JpDYW-jf6!nh~>Q~^HiptgycQ_(#Y5#+`7qo5KA2pJ~`^i$13^7s?$=qA2<>66% zfE;9Cpe`)QsyzLs09WpM^fUb)}75*m}~2*R{S>$eQ1a4;VvrzBjt{ zD(IY}!yB-bb9aIG9&fw-3?(n94cHAfOxY8ht2R?7&Ij!4c5Y-=l|W{~SvOq82RbEzyZ z!k$3U8<6Yaf-0A<1tf&UrzVt#TE_O7+R~9L>0~_&^4`+Cl26dXF#vCHM)zc`AYo$Z zTG%Qsha(_iBHQtwl*oQtLj(?JrQ0JRlOw+OX#)XsOqs+pwv{SKn6MoLc%3py9@gHr zWT!{5RBjdX(U7t#%Bci9pj)@XBGAzm%Ax6G3FWk_bcRr`0?BZtbYT@qP#puI4yn*T z*6P#o$H_h)-W7cujsl_u?gptYOAxx-D&9kmw^g)vCDB2r*oJgeKM3%^_Zz38 zkC!oNg=Vh@n!! zp`RfYGV)=zKvrj3Rusuutgx;oXG5rm6_6K`b0B5Ok}8yniE^JC&I-P19D#0~im7}O z7V+>@x|A1FcM@*}C1f#4J}fAe!?Z<>lwG<7C}WHAakPe`tbQBxN26b_(!Q9DfmD|z zsK$~R3Fwcr%;d#vyk*9_dxweW5aSDVwmGTNUl@-<%Y#J-%73?ppu+Fgaq#y~O520SAz0FT&m9@=ZU<(vn z6@)slBZf1iLhkJ|ZGo(2Nh{vlXQL0#*4{oxn#o;tuBDQj<~&Qqi#Z;c8gfBO6DTAvv<+Okm^^eUG!pzds!kOUm}l`+r?6Oq;>bR zOde@(i_0xb-uEt%me#&^sZ_~*Zw0ID4{$4`WG%yGY-sInm)ioJ8&^Q6kGpH@qt+@* z$Gg>)5b9Oho848cvNpS`A=DuiT&%YG>mb#wv}j*ztGMFU z+bXKK>mbyroHl{Zn+;Z<@Lf-Ri^4|qvm}E}G(4@0&2O;!WPW1_{iv3HNqdug6iPp6 zy;*kYH?z0MF8y@%R@tqxzVpA$60NUmZnwlW@=59)mbg}mcUs~#QoPF&*GchiOT1Q! z_gLb3DVmmeofPl2#0^rs&l0bf;{BGmQHq-_@o!Rmz!D#o;)9mBNs13y;tf)K*b;A) z;ucH1Ns5nH;>}Wg)Dmxz;@>RsRw+JaiML7daZ9{iiceVL9a7wCiFZozNlUy-iceYM z-BSF!CEg>&r!CQx;y*0$UMW6fiT6qISxdZMiqBc%W+^^zi4REepO*Nb6ko8!hotx~ zOMF<0+bnU56koK&N2K@?#Cj3b8$C21L01eE9QxymsE>-{hw0Qu$z|3VUdA@4H(YFn zb05WqekDJmN2TFYsl0tdnbB?sflfbE87^qHgd)R7#_@DrMuBD4omy5rhAs^#ugt7- zOXzV5N{hO5*MqXc<*%5wQ%Xqf+>3GJW_&nV>HpCZk5^$#U@|`apyVVFjgv@<3m*LTwi?vFy@M`9G1}sw(-5nNKZoh7>=u zMC&K2pIf5!6V)#u;=?foHmZ`-#LOU6$oH+78lS_9Csp!2IcCq?dqR2HTFQU#K!5YF2mf0|KN>@PRrG5yYUyWU)Y9+6sHKYpwe*WHYU!t7)Y5Oj zsHGo&QA@x2qLzN{MJ@f#i(2}D7q#@uE^6r~UDVQVxu~TdaZyXZ-lCR%wnZ)dUW;1# zp%%6D3oUBtr&-j}Z?dSRA7fEVzrv!HettzQ{qBm|2(~I}qgIM?Yn=-`yKpd$i6AX|0^3e4s>J9J6CY>x!{k_M!2zef}24X+6Q!bv@i&^|ZU|^S9#9t|zoEuC?RA*UDNx zwS4r?dA0RWTMxDM;M|AV*T35H;`e=C)b#$Vwhne)2l{6^{ruUJ$L)2s@5|GbsebI| zsHw-=47_U0wngi@Z>_c6d7TlXRBnDef9Y|(9_;m}7=G?^;MZW{Rja#u?3Z3Yea(Ii zrn@WOny$m{ny;pQ$d3MH&f0mryT*Sn>sM2rwfVZQpS9e6+t*KfAJF%&J!woo-_p6J z>-pF|YRC5c-yGDgQSBPp*A$$$JN>LyTQ9ZsQd=*-%st5NKG*DZL+d)vch~stj(1o5 zrJK{P%;k0L?wCJaAG^!mE1z8%+g)+_`Pr4&cK5Mep#%toIrq6k7zT`9A&zQS%?5@P; zHLus0JqOjM&ax)sI%C~_ca8tt@$4@D>H6`rPnVmYAHQ)w|6cZFi#2t9&f48$VQS7R z)*wHAIeU%o?)<#`QLJ8b|J>tVvDA*$J`1z!?&m(&e=oIW^Fr&|8-MQcUxMGyokOaB zTgH6}v)q|%-@n*)Xsg}->eq)o&7RiK{w*5CM*r&TYL9v4S8FSI?a>^xdnS7=YuC57 z&gpmiwe{fa)qC_goN|9&yKc4XMtit^uTfjSwfk9ZJ-DA^)b5kD`{bUuPts>8d%xDt zS$o{;^WvUlZ^vRkpRvy~ihob!T^sN3|JrDuJE`?&kMGInl>I#w#crQdyE>*H4+iSF zpx?NC?(XjSb?!8`J^!yUPWyn@ynf@vBpv%&KXQHjICzco7&zC}S1fj(e&?Fs_^#HyS1f)txw9C5j#zd!=g-N-W`kDUuZ4}rFV5O=`FAG2RSx$3 zb87s4<91C!@2V*}KJ1w7^XIJ7nw;DAzL6SFO~!TqzeRg}{eO$`r^8>bRXf+3j)kd> zblG~@d&T!_#gfjv#5Xl|uQA(a>K;Pl`r6w2QqZ{0Pq+6Q_w&Eo>?MPg9n;Pjt!pRc z%xZLmUAw8CeywqvwZ7iJ<*`(*b}qH!@}B3n&OxtJI%m{*J$W zwWBkzV+=E9*8=i)?Pg(o?MfVfgkx>iXkDyp$J5)F)cG#2wyxj55X)4awf3^!YB{($ z=zE;a=Jz=EOYW_y=bk-x?Ra{7T)N!s`sMvE+`HlIPT$j>d4$&r z(HK_6wFCZM#(vG}^J4u=$5WGCM~_pt_dEO39Z%Q)uVwEyuitpO9Q^Fl_5VxS*JQWe zGk3Z@Gb(-UbhiG{hS8)y%dd3=&HG2Z_ULK z)K%@e{4v+%x3X{iUgNAi?}E=e+8=4{^?Lz(EOqa+$7^kCnbEsdYwJOtTeTc&Iq07i z(ya&G9)13-Nn`dnweatuNuBlAJ)-tH;;dOsuaWkO?O7|CepIze99ryF^H=eG4KYKs_e&c?A(jE8n?>C;Ve?NOa|9<0serm_%HL@lg^y{+D zxhCVff8D-zygL7%gOA^O?P>gfD{zVp^Ajs{9-80Q5q{D7jazH_#$Pz@pmzMHgT`Mr!; zcNgkz+0L(aJiX8JHTm?R?`3Te|%BRC~Sd?HGSA zW2v=n=eMVi`_)|SxcgotbscN@>>3~ayti5Y5@WUNxQo}Mdi$PHRTcR)|LK=smDO~0 zRlj)E|04a`HY#bHTR*dTy{hXerhSGr&K%q@vTwhPi<|a~4(%5`eLw{5fQYfQX^%er z_9y9#e$ipZB~81{pLI>cNT+2@F?8m@jDgXX)NR~zU}Rv`Pxz+oVWU{rw^l^VID5vp#D$i2h@qlD%Qpf;jqf;$|Q8FQ)#ixOp=AOQ=61 z4rH5|QPsgXx=-u*GYbac-#*>QW2XVx6v9!Mgp(pMR8rk#Ql0FiNJdgak<^fEF*sWc zR2dx)6|$8XWm85&oQ&Ec{DzT1l$AMHCPZ1817$*#l@<9J9Qg@w#*vd4D)RpD00bv- z!03>S$cqvAh-^`qEzZssXR6>&gVs1!Uycz@@Ma;Rw3p*-89gt@nKJsFFGmR{H2{-v zQY3~-st_KK%juj8IwT{hu}ErkwkXRMr7EN0P$64wIYv7f>B~_j6XNA4l?iFfF^(f2 z0cRXJiJ>AdhX({)#sQ;4G9sUX$R}ruN!g-2TTD>FS3qm@(wAeh6TCSIQQFH{Fy`EpFJ3auP#Dei1w%;JF+yIwT|V1&DlJwwRMGW~s;*L*+iN=Q)v^ za}Xldf=}#OPUyyJ+MQ;^BUQQB3EE;$iVm9Fy|NDs)tP=F=W;RJb1o!?%H;}pKnlw_ z1$0P8E{l=NqHM8HC9(?R?nD+jiReqPFugo3<~**1cg};vPPHCdWoE|+mGo8X>vAu&`g_rL>ExRp~thh*e(6>?dX zEiPAym>72_vdT$BUz5wz%j0U!<6d~@JV*?c#}n{?@E_vv(IFXmT!%ca%@)^Wi!~~h ztx&no@N1n^%xknYS(9Ea8#tFI;hu9LF;p)9f(NAV4^9Ccl99`e$YoQuxLzf)4dd=a zHaUstYjS;hdECT#ya?}{2Z^Ebcncm7{>vObIwT{HyO75n+2Xcraf?djZE5@U?0fa-fa#B^A_}R zgT}jD8%#yc-X~{fHpqR}Fw%zp+ZJ<2P9WU}(3$sS!&2V2-OY?X#3(Z&F%+Y(;Q{VH zLBltrB!khzVDw{t+=!k=N_00uHT1lOs39zk=d#_q+w%@0(>joA=qbsW8Ey4o)QFrt@6Bi*=*;IF zM$a;%eKE?6NDRd&7amYU2ccm`B!kg^!04rHu}uNWlXi#5CLfI(&`UBmuAx^oKyg?a zucQEa)d8f}kmZBZZ1JfAbb_=yQ8qo$xB-1G zbK@G?t^w)^OXKSlK-(QadJS1Vn9rvkd`==?+r9bpg3kQf;qw*qIT@qOhs02P2EhaP zoPvh=kPJRQfzOU?@q^+sSlazrHbc<3`RqVGb^&GNI2W?hVQEBj+!wNp9Op@cbs!he z4-zr~3ci20uWUofdq$4umF*1Z%xI3fvPE(z(P0>6VkCwlRss)jbPgIOMly)i&*>rR z=GaeHN~O_A*_5Gi^I&Nl zoa4U8HF1EM)`47K`$_6GCw4x0Z{kgCI&|j24zYun*aaA6VkCwlwh$gbYz`VGMly)y zfmlr8`l~crB%6!SxN*g_`ig6~7Q@oWPr(&;aOw4B`KURqi^+N1o7NKO%zTH|Axvv2 zMwu3gp=ezV51_RY4bvhSv|55ziyYBh0b4EY*2rcp8aJ>OT79+BfL#MiV`f8qTeXS$!t-Og{3!QnmL+mgnwjQHQjKomHZh;37+lYpVkqlyOK&-XGb*nVG zO*XfqapP*O)mM8B*B!7l+NI!X@8Htw%kok4`nr>xxA&%X7j$MjhgMsrbvH(t7Kx!~ z{SzKQ>q#_Bi)7I13tGK%M6VptGe?}Lu)P4SaYByvP`$U4yV=XCF?y)p(*j5j)lWp< zeyF}8=%M;4oYae$gp(pMR8nuj1Cn}~b3un>BsB<04agDwb3{Lt(c4fVTkWyo04F1T zHT%niXf@4#G9m3z+hC6T9XR92NemVF7w~|9Kj47TAsLaMgUHXy5yNuC&>S&D1^*?q z?&Ubk3EmurDCv?y%P~|&&rflO$msbgZuRA8i|;t1_?AR{(^1H&ZO2rc8i}D&%gW@` zeza2~8L5p#Y9%?MC`SxedDVdmIctkj;^d_-N|8*97iG9iOIwsOj=V0MapWY1iu?c> zc>@j@i$XFYpNPoE=ZLX6Vzi3a#z!ICl&KNZB3@7m&**!r8V4hE+mG^2>(P5A03jB$71BM zC`T;J5erl*r%2O&vN;uv`}(^`t_nZ%S*l%s`@_;$lH;z-r49wtI*?DXg$@RD0s5)W z4NoIyOTDkR1E4dPIM>^YnbAOuG9wa0F*+L_fMy69zTT1yMwf%p${ca20(6eFE0oP} zG;TmEWp4Zd>q-sK2v{1cQUG1)0Mg6E^1-|3r5=2W$k&zLe2SqnS2=vHU_K=nWj-W^ z;!_R};4=yh^C200Hh|Ci9I-A(tW}6Ar0FEtRHAVsT91_Mk5rp9M3Z4@Y|L?=Nt+x* zrgb3K&^pPP8LjnTbS^pDM%mni#*OPSt(>0HaNP_`CoEBv~I&F(;_hxt#%wD~5(?kqlbRV?9JcOeA6=KPK{GA{Mis#u_j%TEvXct&dD``f*r6 z%y|f%h{>IdJ__ceZ~xpaFScRk8hk{YSzyL6yp}#Ke%{dImv7pq!Zz!>T@$CTRu99h zW{Vh!v`~>G{r4wpVFXDG!Vm|H^i{YV;JW#8h$ws z5<}%N3my>uR1O~{#T_-vu^kN+^LGZec)e3a9B%v+rBu?ZqIOar143)?Rct9doas23z zj6|xC$n=;vFD9nN#FUtrta7;?2JT#@JGq$WAyE4f(KIcYDOxgOo*(IFW*T#X#AjEO5^;T6a}l>7B+EP8#NAT2Za2 zmdI*Oz~5+^k^y4_dI&PO>{45_)~!En7CKvk_`jnv6zu#rNj5BTby*vhY+j1 zun)+5cwz5%7WQ75PK_2e5A&IiRa;m&;wSB(V&Zv~MHi@y|D@ceY;zJZUqF=hl0Gjpp(W){40H!#W$Lq@bhXHk z-$pri)|k@#PqkH*BhIS+n_+Z=F~cA+6pX&`00uqK@T!sw7_S4yYccVPB5?}Ffk>|B zpXlE6H3x&fp07CTY27Tp!J+np0}hqMP@xWk2ZTD1BSeQ}g!%zOeJ>{7iHWyVv}ZzP ze3Wu3zUKsNzN4+%Tf1f53NfYmQMGlGBhI>g$S{V(m|>6@3dT5i0E1FAylx}|#^-?X zX-s^qNQ}og5NYf7se?gZw~wo>+ZP<_1UTSONemV0`S5^HD>*`RNJgmNBh+tWVtY({ zrJ|iKO)rp56&gB|oF80&Yb_i7SawIu`JLJfSQ`+*tF#war)F%+Yv@BlOm(C~7S3`Tq9 z_7L@QMV(xcnJc2X_7jn1(t5dUE`}yA~ec=qfaf zjAS4?5Xc(miv1L<_0sM-*=#`LhSgZ+$=?$+(O_KPSZ=i7#I|*6QeF2?;eKlfl!qVuI>%Qgf z>ku=o1NjW>A+a;E6EtMqJ&?Ucj{ABedmB2lkAti?BYOvamL(O>cUN}7Hxo9$@ayavfs`6L{w@%jdq#_1`%hC00TlhE?PxCUsr`g`E| zmi!L&#`PU^=IIWuA&l#Lj500~L*d%LF5{|?hH;S$T&2KOoGV7;io#rRwj$P8S|1>r z1JSsN6(cLV!bWMt4uYjomg~Ov9_0`-tpmBjMo8?8tWZOCwg<9<$?+&}WKEzm%N%4Q z8Cg?|GBOfFA!`l~sIWXVjErO;n*?O#xne@D7^ip{(zJza4n^bURW4KI3OiTh)e@G* zvwSeF2^y|(9=Hx8zvp`6IvhH4vV*IVakauI<03H>u1@d(Tt}i|TqFb6 zY~Y%iE2?tE^jvYCBGy@2cahC8XxzkRA}hPX=4r%^g{3h!W!InQ5Hqac1AW` zLw24Avg63{Ja1%Op)=XL7WFT7tWQ%jfqFk|1@#-f{ zPnAu7G;UstWvX0Z%Qar7!O~ck!fUz1ORq4?2jg0#;acc{YXJFO?u~08bmlS#*HXqc z2&0UP#89|Kzyoj%MZ>sA2Cg;0b#<<|GFM!YD=t&SillY1Y)a6$iCvAX>@)x&a9Az0Ul|thjND#%nq(jhj<=-Qw`l zE6no2xHjgh?}j$O+Wv0H{vcFEZg26XH3K^HW{1{IOlu}anHGtmXf1&U(3*#aX^{+C z52C;}=ZgDsg_$ev&J}kmW=rJ(%Ve`0jhoqKt;V)!%r1eY@o=vDOTsMJf`qnC#^Tg=6W=4e1Dgj^QQKkhHoP*jb~HvJ?G%lOV0AaCHJI8>5ddsXB1C@hUva@~*8UUj&c)`47h+a!Df*T+67|3(g8^@j2obml7#l$ROG;}~Tq zB!+_WJUjr(-_bA>k^$u{KzTzE`KL5`K{o$F<0kTkR!Q$_M7F`wcqfI(yABb(k}MxC zATQGK?|K7y2|Du~2gutDx1D zZYCdVRq}<#U<#RL)g=9ea7Erb;BHv1*?_~2m8aI*cT9y2u5%~d@#`h^iesGBBRbu&YRmqQZ z{14thc0gx-?*RFZf&34n41~l`Kt|MKAVbkG5Rw7ppu8U9fIP8(p4c}}G|ICd>J>q2 zG|ZC^Fx%4u%mebACv*Gf$^C?W;vdhgAIeDU~O05zqq%BkHK&jdgbIERwC;6j;RJ6s*Vd)LSpsKW z63(EQq_&t-Lx*JK*akVa&J#!EiB>AXl~5shZFO2Z z3F@nJgiM8s&ur!Nt<`DEkzWR9965=hBEJnD5by>L7#)%k`EiK+m^{%rPjt)^N9T$5 zD*oGH;9j6(ocPVo2$U|wbmDY$*1|kGj~{8%sngyW_E;kRA(8yCUsq1?F3iU%k{Bw* zzrh1CyN@$Nhh(JK8!7h66Fu|9iFxAqJkd?1_!tb_DfZG*?5U-AqLYhxypv)#XV@df zYE{^W6WxkgIZ+ZrCAtkBkl#NzKXgb&q63g<|2)wzPxMtOz9>y!lFh%-xGxO-k?@z2B49;`D)A$c8jX`(0O@DA<%9VQ_2Baf`6~40^C@)ZIS!w*na^h!Wj-W^;VZX$~O0hAbakLlqu;nvkz)-h7%uXHIqaOkqCR7-c>rhT_u_ z9>6D#hWU^TKJ&n5PM(;RCuZb{3lycpr1jylX@$m3X%4co%jiOl(h;yU7UbblwHdoa zq^dLB>0IbgGOYu-jAl7#%o%c{=C4;TaK=?hwI;_GdLug$I&*=8Y(67vgHc9CVkl(C z!2^&TjfRnt3}nlJY-ygjI8R)pcy*Pg-DJ}pjhoj}nG#pk3XRtZurw}B;kClyrB{{Z zgRAOd4cA2;xO$M^72dddLT6s;;JSoyorF=wMPevigW&tv;98p}R_BSU z^291d?9bAAh-^+r<0iHiS=kkKoknaZERFSfxKq$7>^g^-X&uNFw%S2sUZo*h<&3Ke zJA)iw=Z$O_bmn>o*|m)9OpG!z5jHUV4RDKDfee)NpO`z%`!y-r4zAl6*F=mm zE)vtlbt=6edNy7yfQDYK!?;KWu1@(qM2CEFRK94JFWThWpC;)AG)636mPuFIh&tpu zpC*sWm-R(A#qH34m~N0a$IUkA+wZand_i>Qe2Qf*CgG$=43!kULI#d5$W~@_0%g?I$w*(wV`V~=mDxomq`fxbc#eEIoN?qNhKhU*JRo58 z>Kc*}d0#}{J74t57d`XEi7I${WsPCz%hB5j-t2`a?awGZW%RrpC(7vO&ziB5_jRAb zNzvPGI4KfCC1t%h=6cQr*^!K-1|g{d`J#Wm=%+HejWX)1FUJ5UBYipg%Y=A2`pJZ} zl zI2q~7Q6v-M~>f_H)kwO#=Ukph`E_0E~?0hj(C9)UB-HFV0 z64BRWW_o$d<2?3;cg};vP~n!^K9ID}I`hh*e(336GMFP5l842-)IS>`07ugQ}1^0<`q zXaVn>2Z^EbXbTSr|8Nc;9g>m9RmfvizPLPJtW>GAlcw!uL$A1T-Wf}Fkh3-UAXojNRY&N|)%oh7)z!?X6GoX4 ziJ=&s2oFF*@9g38k7O{q9*nNb7uPC4J)~Vv*_?#N4d^I4 zy&2Jqa?A%DMw^*YF-DmYiJ=%-FT)uPN6g528P4Ni^tXKRhyqjr0|4@U6VBgcZd^l8 zYJeu=IAd!HpeG$bdJS1Vn9m~~eE3B;PkQs=7vXGm_&mXU)QfOP48_NK!Hs$m4#}vY ze}T_G^Tl)d;u(cVdkGFm(Hm~uHS|xUWY^G38lr`S=*4{ZZv2vi$g~dR8hTE0W=79= zFrpXU7%zDn(3S^jaMAO^44L%!gix!+b~# z#b*;dfX_NK%!g#~`9JXaFkif{`0VWMHyPaI+&GqKxjVkCwlcE2Qcmraah5c?X$zErrZcjP=EZRr&_ z?sEE4E2nQYT=bS4>2 z1M2H>G+bXKgH|-&L;RF4b|_%aNIUCIIrJ_ZH?W_y`pTk*QP%%S<9S#bnQ`|;E-UUl z$+8aQ`r46hebHNZjI21QSHE+j_wJaPadqdE5vN4yg*i-AZEfCo5w84VL78N~Jm zvHEfQ>D`;s=q=g2jmC|uew@kzUxwmLYNX+M2bM;|6kLrQTzY+3K5AZH?~?OI-n8C> z&TQz=YQVJK$0*YxF%+$@;Q_QhLBq622CaiZ>%h2ZtblEocHhY6TQqK92LhPAe`RaH zzJsOFH156tW;?)4>p-rr#*%u?iG5Grv%QJ^0G-*?A=ZS6{fJQ}Mq(&pb@7MqAQs_2 zyGMs)5X%R#JcX;CG^#I~z0kOE&x;{b6O3^dD5F!L+H$e zLo3d-8ex=akr;~Bq3{4m`DnPlNCvG=pw%HRj*5$RanVL$YYDA!WL$r!?&NMBWz`rz zRJQ=~Lv{4+hw6d9%<9ZZwZbHv6p5jd>HrT&O1(>pWF*xcNp+2jW8{PxELB2LsaDSCMkD04RazlhayC*2=ApsoY1S^3s!$Y^x2%t7`W$L zNDP(Bx$uA#CU6Sqkc?c4kjwD6I7cNi1>^2ShC7MqOK?tlc@%RVQ{kQSATd-PbKn8t zpO1#CiDcw47I}=0i?X;VRjJH{%3V#Pom9*+ZB0tk%ViwrG7s)K7ZO9|vK$_e%OXwz z9g>kt1#+1f7vohTmtfqT$V4X*eND!vm&YW|<5GC%JV*?c$2xdG_^UX4bVx=X=OK@2 zaWN$>CaYAgm8R=ua~&G@^>>y=%+q6 zyq=t0;C;QNmu;ETo$KxS%xDuvnGuPh7~KUAK%-v4MKT!81EV={F-rluTiV?t8+sL& z8_*n?8{Yt5r~#svYZ>^PYu6?1LI;puCYBH0J!g6FxsQBZ=*{PT=*$HUpZUyZGe(&Y ziJ|yxg$M9?7!9A-B!kZ-;Ik|)mc+$kh3H9X`jl+`j>e5>8B(%uc~@$Po`$8dBJMtu zRyv4G>p-rdC6Y5UTI|7y-rr@c^k(!7bmj_&(WT7jS&T9x5<@Y16&}E78yaRrG8nA} zqpRX#l>$Vs9+3BkXqXSl;By1`Y>bNyiq99)?n~Lw3%lHWHX_<3aVkCpuogj9*!j&nFvSd>SjT_hPS~=aL;i?Nug!Pr7`VHe ziZ}D`4y~t{mU=%MiJ@qXhhNYtM#Hp72Cc@49%8?Q*e4+xCdA$eQ9ofnEu&Xd83!he z*Q}3BJ?Y0``z4%*g!?4qPDURE8=`Oj+->g!{p6PZz{9MM;U|ddXEl96^d!t`9+*gd zL9`rkUifuDf|99(G1m}@p{UTCr{HKB8m2-rsN{i4EFrQJqDev=q>#`XsX$DAgzQZ` zVh#_zBC;h8Vq!LtIEaaPkmNy7tiSI$gcF$q$D9a>p%S?Y9+1c-XgCp)k;tJ)#7Kx{ z36V^QxJu+|XpO^C*4C(&3xCRQrY&vKS=#tcmp1hseAi%7^RQ}5D@UBAZOKH|!I+7V z7>dYk@Bkw8!YL*~GKjPTkv0j@Iw6ioh*pZo?a;cHwvB_sY>i~?&)7#u9<;Xd@6mW= zTS*++%C_e`?tov;gTzpIJPZ%WL%wJV9g>m9G03BHLUc@sqg4`HpmHbC*-1jL&yJos z99=DkV>yRM>>Nl8mBaHghbK66IpWl2ALj8AjCoB-48`Mp zcmM`^-xb#;$>1>=C6b9h=S3p)awkrNWF#^Ii4-Qp*$HuGLY$Ehr>k7DU|XVroL1n-G-=QIQZ6RXY4~rVA3r_tr^!3SA-p;$&n_MY#6b zo-0%0wXJm4w!-O7l*!d-nU6qt<^|Q3S&lf%Je}$M3C2u^#87mOg$F=s$57BA8FVfL zo%sndHz8&x#LR@KQfT-kOy^rG-JiJ3cev;)Jy&Akm7cAw^h~W^CBbN`zL4{xw>fcM zB!9stk-JfbyY&FN{GuU`lgswc?c{PVuf`7*k=)i%eoD7_;F4i+nyBhCwo5 zYygb)39(L*n1gX3l50DVYIePYL9f|$&e~dcwbyf~bK!tPB{5W})@z6^v_mBsq27v6 zZ%&9C6JnE!mR?n4+@5k_x!DQWyir@XO}k~?R$xl=_G;@UN1S!LjbW^WF~cA+6pU-& z0qeF34X+!?fMEj0-3f80BC!tRK%}kP-3|tQ-R`WmZufGi*TMmZN@A!`Z-)njdOb&o z4#^1hF@*YPLTpKhhZ5p}gt%YDda{TAtEX7pc-G9wa0F`_pC0nOWJc(F+aqj$jQ zt%P_(0it&U!R}+(e1gUe=q;HWKS_UI1N0dzjrURjz3%|hE5!1_w-ax8@cDv#z3Ir2BJIMv@AFpGTS2fm}vENYsq!JMBdJ#sk?tZeDvQDNFey zw|zBU1+X;sN#V7x!%MF!%Ln7CpX8@~{1Burd}9aZeaAinn~~pry>T^%&fLer)rfH! z7-d`}hQf6WJOEcaG>nU6;K~KAoTO-)6bC28fr{9%()u{rbVcJPmV>P93d`4sb%UjG zNYecQF5e+$S_g84HI>*I*})pJ13i#+C&&5T$c~53Jj6kk$H-2=C?g{=6te#C0A#(; zFfx*XtR;}ONQ&l3QJ{F8CQS#(W*{0juNE>@-nUw5yavJ2I6Q?{D~Fd}VU`cZ)m+0> z;DKu}`EBKm>(9`chda0qV_ZWp%D6}jg{uS}fa^>&jEiL8>Ihs%Cq?_DXqyyADq{3n zFj$Y2O&J2-04nbv_^VeKV$M%GqCcBBWgvE;amH?nci znVlVEofz48j50D3Lm`_74}fq18b(Gkko5qv6Oy8PQgl_k=tW&HT_Bqa(YSe?AXDWE z>!tBp2utInB%XT9TZf@^>(EQ%WgW!GcF-b8h zDMl(x_eyJeDHsmAAB`K+IAmp?dKDU`&9F4elkVH_3JsHWAfI|;Bx^=CN<%i%1K9)Q zxWXIRgV34f4zh`i>>-RYG7>`}dm0{)y?h}WIwS+x`9SuUq?no%=PF+RkfzVb=2L}>5S_Ij500~ zL*aT09zcoSmc|uEGH@*hu0=_)Few%!#k{1LqoBPl4|qp5@1k)-TZF{yB3r6Kdk>bz zlBD|q+ENFaX&uN#wosC1Y6~=K^R)gP4}$O0Bul*segK`h#36Vw6Qp;dF+mbT5&RY& zK#*Qu#sohQco!yTO67iJ_>Mjgc4% zN&#N=gObWa!zD#BO6qn%xm6KqCXJfQ#z5n)q+7L0x=SO{0+z;|DMapai0GAM`EUU_ zl#aj48wkA>&AihAat8yUx1n*BkQfR`dw2j4dOaEgAsIj(1dz>1ai3yxl(eH)j={VG z8aI>8T9s_km~@1t@o>`pByo$w#Iz3ND!I?2N;;8)E#6Q%LuWqhKzWFvbipV?Au$vb zdPy0wq<5z=6p{hu2|#&F5$P$7==Ef zh;^W=G})hlfn-p48x-D5ir16kwWN4O z;V6UFcsVI^I)`$4Q_Jaft32q7_SY;h^mPZGxcKX#Sxd3}eoqqmK5 zb|i+%ZVEggJ9;A+XGb!!`xx1MloTH%#d|8XsZb$pnc4_S?IR~O{iOatCc&47_nf}< zb;c(g`7}7=$Vm(p`8;?){B>t2`bPVnYeh>|vU zT9+@JC2-c|GiT6aU8?;>&Uc*SLd?lIk{Bw-Rq%k+mUC+8kc=Fo1^C<5q}Y)ZKd1z+ zgbK-PtMikSpuRdgoE0&DaQfEjWE9YZSHT%aPGYFY?}P_9x{(7$hh#*)HzKcJAnF!~ ztOENX+g;N1ZrR*}#=V2oFL18BjS8HHk|r#Th6V1DY*gSpl(Y`yJ+&^J;7J|VWR}xc zSK)ifStI(Np;mvkeIImY!vggnvH>%?AEV5O#88YLhX3f8YUpo=3xcNCuw*@JSSi`~s1u5WOr-Uy;qLXxxYrNXfo?Gc-i6!P016 z;68B-2a#zV$TgJja53|ozN(@Bk~71b(d*Ee%^gO~n9&;;Wkw{1V)O|-fYEzsm=Vcf zbOac+DiDV$K%Yvx&t&sC8aJR;G9Rv?BQ-!@!qRA6fGtPvEG4w>AE^Pd4&=f)%md2T z8hcz52UL~M~g50we8Ub{FI;H>+TGDTvz1Rtk`#Y zV~HEnbX~nc9sr$roCES$26-Sx86=6JK*r$#Q#VD!AV~(ulL7Li0@0&DoS-Nsq-jz% z1!&w9PqH$NJdEFgYZRNq(&&>yv9CkX+NAi>Z2KUHJsgN9)Er_Q0lM>5cPv=*(db&NCS22^eLZ zB!wbdP4EcwT~4VjZCH`~4xiD)f1+br6Um7DEb;-39yu_xC9B)Q+lK|_>i{r| zz6+n#FcQzn;fgUoq#QbaUO)@BykPVESzk4bRL#L9r4P9~n2n5)O*hZ1ml>&=N8`O& zq2?Kw)e=V!%^8|diuPI>!yk5IOh%7;%~=imVDs&Oct0+1&8Twvm~;AS7jml85=Rfr>KE;Z zX+AA*r%_E z0RZX3L@Kc37^RxJU$iS%Dpg9DO6}DzdOWRRF97-c@6(;w4hH8a1J=YXW4iYJTbsqZt-&WcB-gQIDl0bC;a(bV(EDG@n0 zmxxSSmWbr6&Z&V~iSW7%;u4{5x+T)G87>IdqG-{qK|{;VGLTGYhOe@ki80OWkDKdZ zV2){qQ#;NP;B8bh3nIqoW}B(4T0}Rvw*2}nZEX2GUiY1m`O&=s}S?$&BRI-^H&%*Rv<$B4=^KDOAsQ5j<7CDn3p%B7s7Lh=1TO} zQvdUYeY&xArz<(uui=4XB{AJt7Z)Jg3amJq@o1PY$%u8l(L;0M;ldVXq!=6q;a|o;xBm1G4H(}SwVFR`L5m0s7qn0xdyj^1GqV``B^PD9!(PQQ zo(`n=A11kjCyBI}JL~I)a3YOcVP58QiVZ5G#q3$1$6K#Uz87zU>F7gGCvxG$c@A8B z-n{kPZr2uc*xQ<=3rt{n3>qV=n6i;p-iP5bd2IoCJ`VO2Z%g<$rq zs6?t(VC`xW(C6_!t!6fkN7~>&lyUbOW_;*QGR{TDm(?`mB#bZDGCsaW8K0b1#wwuH zj8F8;nD6>%jb#VRTYo1RpMY>y)imSYFuqdDxJQjL9w0M5%39;q!E3An+K_aw@kuqB zY#1iHrJ?cYkj*n2w~ka@gUN_TCY|I~Iif~47T|p14UzElK^e8CGCCPk;N}LWAB5f{ zWVXZ^51|hU83Us&Ga!c9uUp{Na_~cM-{uXCWNc{XU_*PkMEtwN-mhCqyTj3#FP9)_ zK9L{8^aUN>E+H4KpmOcjua-nwO4SkSC}*=@gG1?`WQTY7@IS%EXizMjtBopPM<@64 z&^9;}F~3$qF-3SE>+~kHub0Td?v>H@w7Ip!p!pgFufjMy+2M^6nR#0Z;KmZ$AoY?$ zTj|C`>-F8QPskYaJG{$*w+lY5`lW~hmxs2;p#!rzAbUTirXGsaI3CInVMe{u|bqLU7i}yc5S>@ zg3Ho+zAUY8LAO18d1f9%;6YwvLxwsG4iM@Y93eU+Bh--y^;;F^Sr{~aC^1^%?8Ty2 z-9(XoTS9^0Jd)qBMJc?1y3x=WcdR&J57#hxtWaL$eyy}#S%u;)wdIIBSX6gJ{^z)7x2UNu&(?7T= z_^df@3gpd~ep6GwRC?T+a^!x_k+0D0guJ8jxnDR3{=ZA=6Q_0fS$rvKJ+pDV6;(6w zi)N}#u!DWKmW4g&NyDsD3Oy?9ha_DbogOMD06$NoVa_Cj z^E7a7P%8FPoaxoQ=3eP=-pAtnY|4>ofwDMj6Q^}}4LR2b=cf#_fyH?TbEel5gEP_q zpXW&+&W%EH{udm;&kJanGs)n50XXkpD)v>Jw_)7eHyzFgTAW`@IWjF!7H4hZv<^?< zT)mQ;g7DYPsm`-d$aDDP!ApB`z;T@54>vUTFP(d0*EaL#bfYux-@6j9MAUX><9M_^ z{zLx$1AnM6EFc7W6*O1a0U;~wH8_BuSJ7~Vk&FtPjS6d0Dh^T=_Fs&f2c=VCF{{E} zPdPHJ60s^wn>ek*)2OfvRbg-J$pKS^Eo*2tDaB=ruL5n*p|YUYe(MVqf|IMv-hw}r z8CDU_=`G@1X4xUjjNX+EKlE~KE;Eu*W(!be%}Pa5l^MVFx<#q`aYzznSN(BFvr@X@ z#J@Ft9KvtSZb7>>-+9D4w6rSpM+9TUOHJ0PU8tdRJ)Jr0))w97;-h|~lfgW8;0VBh z10?km1a&j+*w9BJmSjzULT#1aYQ|Ho1%Z{Zyh%DuH-x7mnd!8O_ z@c-e2pF4Qb>bma*lN~x)#e4v*L6=g^ls;SHuG4X&N}O*QvGCvWt;>Np((Hm6zU7-@ zdGW;~y*UNE(R4npluzA*VAk?PuKa`DN3?dwM7c#9bm)PcP8lj6Xxu}eznm%JxV~?v zr-pAP_z4HE?;vFFtkar?eLBJe&)kHjlPhSI0zpyPWY7ug?Y$K}TWy2?P=Pmv8x*)} zx68)Zz`89l6AW^8npQ@G4n1q07S|7_rRspvf(K43M$<`+DN8L>TDg?g(eAYJWLlUB zX&nNg)3My8chhf8=GpozB0O-mNt$oh7qI|tQWvoq#;}N(3E4Jx z=he(9HTB^s67O)be_q-VLB$CVoR^VaUYd7TaklWti~h#~$O|(eua-2Avk%naCx+OB zTX*PBN;su#Tgikm6A~5>TK3`Y5$IYK{3kN0 zV+pi#8ON1&LBYb1_nl*~Ls2L57?gP*xS<1D%Ia@T$7XfHX4?|GCO=SXgCX+>?0u^n z%B{t|q_rhQ8>wI*wxS(5q0e^h5Snv&&x|f>njeWq8$}ys)XP}j^z42UCY6mJS21AH z`0~Qi;>i4r2rkS8mo$yk&5W+pOfT~@y_`)4WJ|Bn=&9L}v%8g-_9?5F6q%nH$;_%B ziAJg>;DrUz=qb?k89$lz3|0eG};HM9^=c$7V1as$EuT|8ZfE6xNxj?)c#O4 z%0Q53sF{ZZ%sklN{lGx?CCdGX0QZH^`6PC>|IB9w&OA=dJUU?JGJp4_f$pa&_mczM zPlC=Tv2y>JCj`zsL(M!rVCM7u-A@a2f1z?eFTnjA=zJ2Jxs_AubJcf3xCT0(5Z45{ze%~@6yW~)Kp%H2A9whN zahsouX!I7SeD;-S#ywD;R$NgzW>REsG!o6q!Y(!`nqgvC+ufqr-PT0v%l!?T(H0fb zgZ}ew4x0B7?|B~$p7&Wb@6#~!S&^rp^4VgyLgkC%IVe3)Jdfc36fdigUh;;`q!abq#te$A}M5uhuQf$M6)yx9|X72CrzF(mGLgoIf0QbY7^GR%||I9-I zXD(ASmjujQHrj7yzIB?S+*by;uL$%pL;08<;Nv{#d_tTS z=zgAZKRdwv%s?L(D<6ye!&vC&A{t!)l}~L)GnPQJq&$TWF1sKr}3c46S>^<+6;CZ*Ic^?aM{-n3_r-GgTOF4fYhCWF>8#M1W?|EMgp7%91 z@5@2X|Lg7i^mE-WNBg1|| zlHg|@F{Rg@btL&&M>L}al&J+@RRAR}dF@ruZD6I2TXq+bUw_cLFE(K z6g9JVWRsQNE3$o9hat_u_h^nto%z^c$e_;kq6wAFk`v%-)f$Rr+d?MKf-K((f#}M+JQ+to(}M zcIbQ}yH(BX9ofxFUoA46C4W=XZwZ+GA?SRVJph$YWcRC?y(7C<>8nK+&3Ft-KW5LW zpr3}7AG4>R^NDP$n%O(D$CbWXWMKAhHT|}L>0f}(huQN`c}7NeeE)&cFY!0j%&!H^ z{EEMOME{}k@m_$BccAl${w;s^(TtCv^o#xrHS?zdGk@&w9?}1xe0&Q#p9r`6xrj!; zf=b>3R9o3-#*a{@29M{zJ20#jS?crOy>snb$9lQGA=QD(bIGI8OsInHN}@{d5pn}4 zJwk4X;ee12QXw~np-)`<1h^oeVLn%5g;f2H?`>vSkR z;u?zKfVf7gxQb!ugK`8^J|P!E6@>C^rS}NA3`&oXM`1W1r@SrAJ)nVmKhKIV!H1F!VuL1(i?8)1eANd7jdHggh5YkC5kKI3VPuD&)m5^oeVc zn%5iULZ$bJYZ;UtaV^JiKwN88Tvx-;2j!Je`GkB0R6!^&Q+kh(uYuAdB)z z@(nPo7MJ`;xlzrVf)XDoHz=JJll({-&A1s#kC<-3a6n8CshBpy&GAQWBl-?ugXQA{6 z`Z){-1pTrK`Xw0pEW$RZJoBMj%vZeUeKmOAx7ECF1UY}l+xfe}&OcMmKZc=CQXd7) z`?>eLUj)zlotk%hkn``oo&ON*{NOzM&hUUd*OI!P&+QMLPr~~`<++OZF&9*_@U+6B zvy2}Y<*S)<17^P7Oo02&(D@|R(SPQn)yye-we_H_z0!NFXde|>FW70@gR7Q$Lgy3NiBS2} z((!6$@5s6-y;o!dRb>6WX0OA~KKuF4-q+uIG-D8y9$VyK3~LNhKa!oTLK@~j@6e!m z&+(qOFnHdvYTi*W^jV0JQ28uG2~<8Obu?oflpZL?V>kfC6ctjX|GX7J^G@}icUthg z^VPg_VCaKl7F0ecWryB^;#z^>fVi$zajk`+56ab0`GkBGR6!_LDZNL?>!I`r`8o^-gnXL{`DPgU#C4;Z z*Bj*~rT2*Ib|^jKx&y-jadpnOugD$pU52h*^eE_jFt>xMS~}f$i)#aw&-d1NaCN+z zxog18$NIbP66pRE<-T`-`(DubB-Yb^<`V;F9;{{_5HNFpfA{?Y-4`nNX9c()2Axl0 zL;YtS5;$|2nzeFMC$Z6fGt1xIDEE~C?kfU)%uqh22lzM- zI-d}y1-hT7+|LehKQqwB#mdK`03QpX^9gZ5p!-Xe`(**{mjwE_TKQPzAI9Z=E~3$u zQ2FdD(TvqldTfJhFdVQAZd4&%=RfbYLGy0%p7(~}c{i(h?}eeyirfR0&lY5;X5t?|GjLo_Cv?_n$EILGc_^J}91n$`{3pP z-cTXE=0EQ%LG!-pJ?~q=^M0)6{SbyeDBg$469qlc_{4kOPlM;(uIBwR$oV(k&c6+I zo)Ne2G=74iPf|OA=FNS+~41Qzd-kAEBC_!+z*A$C$S-ZGxM!ev2s5= z!2LOaKE^2@qXT@DLFW@6*TYvv-Tx`Q5V<$-~H|aks~6afc4lU8`7#EIS61|+55gsAf%Eu zhGYrRTxK@`Y_;)1yutfc!~+x$yl(}qTJKtG)q3Druc~<8{y*<~?aX(-vqpdaw9YO& z^FHs*n>TOnnG>w}o>-jk*#_S;kWf$}YY`===BFV_sETtCX`za9@pBPXtTRNqSj_jr zVtg;N=DWT)-)jxNS0kZ76&ny`sS0Y0ue0WReR00G8hmdm27a40`0d5Pw;JI0A)z2s zxCl_3sRyk2K3JUZV+P+xih)0F4gN%N@SV%_9>&Bn&Xl-zs}ym9439^YWhvThV-Zzs z%BaMMXQpPtmMtlK#o4hw7MT(hiNLGVXBE`%?oS-ykB1)jMeGyeKt*n+7baH^f z`L{(l&lAJXDGDDq;3GxgLx>Y(EFk9WGdNotgU5)sD2)UnMWwOG5PAVpiAtjZaRQa6 z4bIk*C5`w3$xtL62K%-m>{}5h(AggmC6H{f!P#1}KN#@^lG)@8B1JmuGlcF&Dv{0( zL7YIcWd>(!$(9=N1(HE$M;h$^T!j5f#0hk^98m(v1`#FP0+2;yF<*I@5nmv-P5vt) zMG8I1$kA$~5-D^Q;sjzJizuPkMA))}&0jC3N|E<~Kb63$1IrP$QEU4}?eiET7EUs;6nye7t?l*iMtp%}(Aj?s_Rk}oKrhdUxj!pL$6g;q zn)8i4%`f9;CZpyB^tTO>-VpPBtr*|`TJwFUIA5t;@6&#dgaTE3izq=se2u7LCi0~b zUr-RZ_@LZURWg1qqN)jo$YYUEAXf>Zipe$Fh_{fd6pX^8x1BoxTC(%@^Y%H>A9gH&YYe$gK|+Bl zPePPH=_=9$YOdv&WN|j&ss!UlmUs53yel(&4rQ$%8pj2$~ctl!M_X+s9NOj-U5NT&I-<^u_onp;*YH_|UgKrrU z3d(UWLo{vZiRk`tV5mm(uk;6zRkSl2LweCUqjd%;W;)t}6D}kSj$hFvz zs~HIes%%1(K;#98DyGT?Bi=&f7DQTz{73v;MC4_L$QdLQ$klG}wN_=D5pN+^7a}d> zIs`u#k?UQ^Ww+Vok1O`Xg}Zk9cJ)*KMEm@dK4rV(Gxgt&&y~*!Hk<8j05|px4zy<) zyAD?_3Dz1U^;(cOjc7*J6VSBSY_B8ApULLBdfVupVN3FDd>RJh7^QidV4nc7-$Sav zivEGtp|)=3O3n!mL_2Jb{|TZ;QRGLWNX)qWsA*-COV!F~?Q@LwS)zQB7QO>Y5iNXU zL^C;1weS_9eo6~p@M#zfRtu6#s0Ea4u}Fs~5;{1{r8knjNLAQ(#RODMU4uHH^2N}__~A2lFID!4rw6MDXpSwmgoxCL7VN<4ry6iZwK8$tzN!_*Z-70ket~ICTo{> z$f%YuR{10pDI;}ta3DW)NL{_zUM3fHJCVJA2XN-cdi+QoXgdH{qg71Skud}rjT>f% zZ>J}|)=8_S;msg}K3>LVV_3d@+tTq=G3~D{9j8>>*O%f>Z3z12QbkbtE%np!w(>~= z|7WRL;1`w}%$Qu;{~4=oBXZ9*0@*~)IWln%1-Xo%kKN7(g34$y0Bd8>}l(lR*ja1*Wf-RhctXWUTm;+ zlE`B^)zT|5=tp%*StPb;MW2JpI;BK}DV`Zh@l3FTe1b+^YLJgBAm2euzOzO?*&yGk zQ(6k{qcrYrn{7ui`819ER|ff%PN}O07oL;!bc6cNHrp;@`stu2<^9H>cY&Ta+44?H z)2u>5&NQKnI#nF|yiV2d_U}{;@3)+>xhIV$8nwg&181+oKA_A_h_m`FlotY zlk16_5Y0?FO5|UNs`9(?y}3AuIT=YYCXO) zpZMp=OPz~7^xR=!|CV>x-SOWGu50NSY(KQMZ^_cZYpac5sr=6J&E=0* z+*JNX`7Py}E4Gz?QT|T(hZXOZzvFtZe7)=a@;6)`lt1qJU-`4H56jQ2{HXj#*T?0@ zR&Fo45TRovrRTk(o(eZ>~nhKe&>*Hx@?y;pII>w}6% zT-z)D=Q`GPitAF>*RGAO8!9)u{^R<)>;B4rxK6Ho&b6)bRoB&(uettN`M&Gi%FkU7 zRetBXqw=WAODa#OJiGG5%DXDpRz6mFQRUXk%PJqNTwnRG%F8Qnth}xA?aF&A->m$5 z<-aRms(i2V<;vG9U#Wbj^7yK?RhL&?Q+03Ema5?eQ0GoNJIg9&xjp^4!DGgsG5*r= z>&CAif5Z4K<3Aq1ef;O+hn+_`kAXIha~|(p?K}ZmS>s#_{hZ}I+j*|@0_P>pOP%YS zmpRuvuW(-J+~B;%xygB*bF=ei=Pl0LoOe3!ao*>=-?_#4fb${e!_G&Xk2)W7KH+@Q z`Ly$&&S#y^IbU$TWnU;bnHF%`$5 zj8<2iSaEX2sTFG~)>fQVac;$V73Wu6SaDIsr4^S|tgpDD;;M=b6<1ems<^h|x{A#e zk5{}}@mj?j6>nAix8mK3_bNW9_^@Jo#a9)_x>lhy*SgMdo#Q&sb%E<5*Ci<1^{x#l z-A%3=T$^1txo&aY=DNqV#q|hE`f=BjuBTo9a6RjK&h-My{uS4&uGd^|xZZNX&Rp-i z{^$DG^_lB)*O#!5Z(ZNHesmpGd2HpX%GI!d6Dv=yJhgHSY~V~-!?~5`S6&EPxTJC& ztYJMY;mXPll~-48s=Ti923W<-mAAq&?tsnQ1M9dSHuGTRLzR!fN*=3xqVlQAe^mYx z_Ve$`7b^b)t9cm~vki9hCT!^)*w6=+A60%_xxMo9$}cKUoPOE#>!&|D{jupUPv18E zyXnVQoltdR)yY+-RGkV7JEQ8%shu>e8yqs@B8uuB_TnwGsAr zZPj&E*H>+>y0Pk}s++5Bsk*J|_NqIo?y9=G>K@qUeX!20RS#56lXjDK9sW0b#E$Ov zzMlS>T^(Bo9kw5Tlq9?4UYcpk&73uBjU7*aslN>MbRP=-1j zboH!R_4V~mXZ^gnb@TA)bRImGlxUMWRxLg0wanZfZW@2Z z3)dtzUGUtk<9hi%s69^_BY8c1F&XK! zLZEbKpqLJRdlJhBf76oaY9Hv!_ASjho4T@tZQahs++asnUrWub>Uk}`zMh`J-mcurmL^}z zg1)})Y)hgMU#sh8*36q(JFB|3wq;3IZ%eo@n`@q1ue5XRH8VT9yUU%EAdh{qrF6NL$u@```gb1U`N*`qsRcpZa#%qz9XRUaqMsC^BvP_Z7z+ z*n4`-oE^(w?>(#e$4Pa~KMzUMUr(l|y?Wje&K%~Jjvg&JZ1zj9pm$%+p;<1ptdHl@24mr5FzpMv zdo$K)pUkHX_(G9rDBy7~%UY*>I-fS?_l83LgxB5OXPx$$eA;v%l8U9m9(PZdb=qh1 zX`@L`I27}S-2L6wX`jod4F-}PZ^R#S4+-RbKA+Z`^7=fnP~1J#ZjJk5K5g0;2!;~T zxO8Hzk7b&+$CCShibp)YxcV`pW5s3dV&E@5~=H!S*QMUK6N}9i>Lgs_W5-+ zdU=?zk6=>ALaAgl6+`Ok4r}bc8ma5Ts2ivq0ZLu33qDE}`~pqzqm1OW-l!)QONOFI zK35?4G5OTcUkGIrM(R3&;KwnkBfdx|948gl2n0XgNL>>O#vr!Oht#^*CVz24K5;Z1 zh{h7J2omd3n-ZUtPwWqc)1k1RkaeL=iBDk?`_l*HrdxG-yqGC=0+9@Tu#qry60{@Z?AW*Jm%eF7oEFg^To3C&PJPL)E&Pk zj^atj;BE9uX)^Ek*yO1|Iv5M0I&^0TtnK>)Hn|rj7*3`m?lw{K5831auP2>MN0V;! zm#oo0W|K!Eo=7?wO}l$UvVX!PuZ#JDVYEkK_uz`0Znmb{_8FT#7>P#`DL4wG*DcqS z{tGsJG??-wJW)TTU#^L7O8*s`-s=m;l8In~(yy>i{|%eom-L2{eqY#~70Uk|n?4y% zNBr?vlF|$0|A9^Kjm3Qapx;mF1@hBiO*fsoXwo0^MbimNZz=zzCjtM<4cV#&dO9$) z&t}m-q5+0#;bR}WwNAR?{ZV`FdCiPHMsGP$mi)Ko#hjN)CIVh>7>>~83ufofQ9owQ zpRIh+^gdSgx_4?`w~+xzxML}AlA0rHg!zEdP{yk$cW5Y049e_S0@ji6`rO$iOS=x& z2u7;}TQq`2EI~LHkNeV|w0lrY(996j!~&sYJei2Q8HqT5C`$)1>FeT2er$I{V|8yPU`osn^Zs)V~WCA2XZwefJ;8;*Fx z1fl87f<4gFBtWt+#L|_@S!%1WQJjjsDNk-zKU>N12kO-Cb2tzYB;t7V5=%T4Kj0#MJ^C&|!C!Gv}4&7meQI{c{ zNo`LvG;nd$*+D|m(_iihI?Uowrpv__{!j0^vl+AQEtTktIq*BEe8NmDGu91e{)CiQ*VmM*Zk1YI&*=aC(Iy znion2$VH?zqME$=Og?=ZOXc<1)8YdWU0K~ zbSx50>$(7yfY&<=)!alh5cVXKx`dfpfd=1WiQ)mjCmltPNYh}g&dFpIpD;veH~eeJ zpY(X#x$Y%!)I-!W%~Ts6%;YLRV`vlZWH1~^$I}LF8$)Pn4!>XsQ*QJmLqT6Gr7>;G zc6BhMrK)RsV4^zx@D)Rvbf-OGPbB0E=<>F)OiiuHHymXkkxE5_=j?^TsbX&gvk#q;5XJ6kk0XQc$vt)y{2Bk?&r3_`l9mW{L?+?dy#%&CtNlgBcmU&lgYY)}(RPS`3q#oD5~k9SKA+1r_8d!B!(RnecRmGzp2*z6d&( zx}sDMVa@c{4COq~g)qR>^)!TW7&@4^H=GV6!stF~p3CqBS{_X%?q;at?oblLj1;=7j3= z4rB_WP}9iMG((VMi0Y#;Z!!>1dT8M3r{OAnc6aN8FH^^QBSTsnji*9kZ#?8~CpvwQ zU>ZBU#8RYvKFs7AtOO)4GbD4+#v}qEn%aY0vsMtNymY26?*|Ow>{vXI^hV>D=F_!d zjG;|K;wiW1o6`Dd!skz;8CJ+JVPz1RG~r^1s(tYo1{g8$(ue7?>R|-urHMiB>kAgcA?!i$bT9n5^{= z3`un=jHz?#>CSgyO~X zm8A(M!H?FPPZ>i~pAMyykq~B6DLom{toe1bG-EL7dp<)qI~s|^Fr7rast*(M@~|}NbRZe@ z1WDi3Mf5$u(9BH+Lw@*g)NS1u6d^SUP2=*D|zoF_#{L>rxC{^+H5E*V^#T zU@0TsWF&zFB`&wMdWY0xvS+cBfnX%$jryp9BpRc8OKnr zsnFkI=+o|KGUUOa4ddBDdRDoDLjNxVhC=uG{n#J@G@O6>xrP271BFUKLqe>86v|~( zilDWAwlg?scfx}Si8wYuL86~oU|%pm$Xhz#$Ba`T;$G6#{&Vy8EdvFaqG5kJ8N(VG zR;!c>FRmFTW0vm8dk)O_#XX@^D1oh2I+CIsFDhwBZ;}|tt3?)`v^dH;6VdX%u}Edw8B(f{s=I~Gnli}fuP?P z$68B!_drG;=9_xjJ2C_*cMvNXzNA0wZqH`4nyi^1>M{M1hnhNEZV+J00<&(~r$~9qs*DeR|DQcvUO`Carz` z1U7ULf!>WV5$w$pB(UGYll0M|Y=2gtq%slAU_$squ;X`U`n1Mfw+ zKn(|!@cX=IG<*OW5GYFoG=~EU`aS-H2ZK=T@eu*(O^->U-!VY7*ja=r7k|Xv+t;tz zw`uHq0F!)nJQfW_P+Q$AyE5JSZZVVU+zdf&I1%wjJ(xgSzEt1YXu|ih$&*-;MkhXo zGFXql>^!<${^dOVG&Wi=4STGW#=T=b?dxjnfKBIFX8v6qU__!Bm)qg)A?>JCaDGV@cYm zj1Hf<7&=Ctg=Q8OeQnIkd9m$wq_Aur46edFEM}P@58k9VNllDZ9+r$e4}W4|<8D7K zQu-1jMP;*KFcoH@jp0>`jvN-#1K4Jh)%X3GDq9DW9BZGLxkEFI-f?$Fb-vVm^XsXy z(1as0?Ll2qXWnS|T3@I6pvkI54`>$M$pfdN(Lj_WF#)?gaUrxZ*fc>O!b2wl;ZQmN zPhS9?5JHQj?%|;!vKI{{_IUH^aCwxOM@xl>r0(aT(*bO93k0#B)C`>xN-cuU^3dUE zJb?v`WFd4~2rW{`5Dy)XVL~+JPZvOYJwj-a)GK*tKNh6Xp$iv6D-E}$u0>M+g@+FM zQ<(mZMa|G+t2SmUOs4l&7TE7jCa}c?D>`Q2VpgqBXPBCsqgmvDJB?ZHh$kE3#h zNa*8OXulhMuLM?ZErb>uwLs|AJaQlq_eBy|W%wC3EkHhrMGm;J=KwP`=wuWii%nXj zj#F7^zdMHIxH$F|6hId-X@SsdS>%8lOUNNCVVXtuitSk>@|ip^I%wD~?p1upz{uRR z-YYlR^Eo_l1RKRYF-+YboV?- zr36h8dN=p30mx?^#P4Z>h(OdFPXw95fdbZ3K841K^ z9f?E=p^MnGz(O|i(CAQvQ(^2tE0DT~Sql`hiHAn@_QgF3#X?4A)O7;;xSj{bj*3JO zOG_j(3tY^oYXq9Uk%z_>A9Oyj^P&J+Y}6vDZ{eZ6*szDSBMX-&HfoX7xAV|3jJ~nU z*`jeNV$=eK+{HsDLs%d2t96mrbrGW$6yv=-G>$X)0+=5w&~*``7Aa&44;_t!5;5!$ zD})yNYEdyh$V2-B9v@mS#ig;;1*RwNQH$D_M|tRIAcZ5b z*b`O&Ew*Zr)KBoxI9(9M$w`X}BerUh)KBx!Q98mCwCJ09#8xeW{wELZi(lBvzrKX^U|{5vvwS{Q?gi!YX%=PP3Yev52b{N&ONF9d^@}sT5|F3ZZ@a zu-LE8uvqrn^#);zI%dpjW5!o`CNXb3iArC{!&rSP#zXg4CLXWzJc98c_S3{HYJOlO z8PPqLiOE|$6JH>m4EV8;sGuN%BVnSq%qAx9uuKB(Xfz(if(v-ma6J{VqtQ#j)K7Vz z#SOY~gf;4oVZWvsxLEUPSm-Wl3FovD{*cE`!8*MO9C9ke7JC{I_I4IK;Kq7kBJ7Kk zr{NV+Z1Ap^r%5HB@zB8pc0gn2i3POS)#&zUg8q_+4#ks@8|(FjQj1-UKgaoO;Q&^|NKU72Ob)Gl7p#;GQ>7XEw((P!kA2NJP)0~ z-X@<1TT=@ZBDOq{LU!b#{b4^&&0`|f3|++XL{d-Up(Duvmh-VbRsb#Tx{0LTg@q1d zDLj-+B$dffUf13cHFCOro80zP6O$y4rumg2w~5J!S~)sKyaz;^1RlWJ3=FRtHxrDK^AE#=47PjdfQ8TBz8dFxvSSFYlODBEl0H&(DJ8B2m zyolR5eZA0R{w@|c=*HbH@c_=U762D(=Zx`%shz9hv3-$%Ct4_SF;^o(-kV2`V1IYS zlc4s3S4Xi{u3A^MN$MFaHd;_Grh?*1TV%!-I~#p#nMv8RSm>ZT6~$x_E$bDEEp|2{ zv1?iE0E``1DR{BGU4UK0+X!r=o`+7SVSCXSId+pqinMbAjm+br6WG_Cj4R!&+L4*H zXaM><9ypYW`aOXtxpfY>nDL3A=kw4wQkzVrl-V&8w78u!?Al}?ULHCYN{1u95VaU4 zXtC*upaVQ~(jUZ%IBuUPfEJscNFiY!Iu*g8h6pasFhduyJdxBf9y*HCw>Shs3uwGT zidddV>Ld#dzwL{7eF>%EH$ji6ozv~x|^PjU6WTIV1a|~5SFbx*e_H7T&#~}=)=@o8RW6CMLy*T z;d&6W(8cUpguQ~tj)l|cW8r*5A-34Cjb5`!?mx5G=+NT4rx&}UEwIIwt#|uP>OPW% z4&oGjED?@lV|t<3V#^kZeH4owaL2>AW({YZ3bBirw!lh`<)Lx8l`oW1Js)R&t|D!n zKqJSq&|!BZn8GPaY-xu^Sf}b5*^o|WV)EQ4vP{s_#r<9%&H)!P8Cg@OH>jpY=oFqy zA`lN?QM{1Jh*~Gbk8>FW%Zi4R@@=P+t`_ z974r4azeyBkZDi!jSLXhGt-Hv4+j&eP}t3?MMX1d@D>IU=L$l!n=VAI-x@G4nd#ic z-3$&kL??0f6_=nWd0h4jwRRr^iJjze3>m{XAq&y05%aQ{wDu?iguSN`Z#0IZ(2CZw zBQ8>tl{~>}dErdEhM#4CAY3YhULQ`uQZ}>J`P6sBGWKQ??%xb1 zHd%*a0o(;ZeGn0(P`XzbBuIzLFUjV}pAB#otfF2YoHyYpCKY#qf#&{Us+^;70)!Ybpj&~pfelgeBO zuzsc;?9E`M;T!0-4V(b$8N|&OSTZ$r5a<`d;lKSDAl#P}@cW})>@mfL?nBK;+CFB} zEj#rL0JI%S#-hFmX487aXJ-sqObYrf3l+w0d~XP6@&PrZo={OXdTR$2v}+2GGv!x0 zM23@P`OA_`J*op(=papjrlGQ^CA507)`Vo0Rx0(a9rStLxt!hSsgg|nI^G_h4#5o8@=eB z1PvisYg3QV>m^X+#Nt6bC{E$WaGe4bftqs`bi^kX|Hy+TV}UrGD6hVEcvEC57 z&)#x`V44%?Vxc|mV9FbgMNx%+5<1_un*3Ndi|BO+aL150j@@EF94szv9?~>c=wl#j zy|IKZjg?pTKqhB>z-@p@4zC_c#r#oRGuYc%a6nkEcP6jCoB_aRDpGR zlUw@>L!ZV`RLt_>s1xq`Hj(EGNXv++{vXNUBw$YwFDhwVx#!x9WZgUsa{xHHlScD| z({i}@dSn2rH~@5#LSA~}f^Nbd8Ndk)00xdRteE5a)3iH_#`-5)Ym*tA%wqX)#@-hW zN8%}9p|$-mCX)GA(6xv#BG4{B#Ic^uQc->euTY5SV912C?{n0xy0gq@-(^Of{ z;-Ld^+z1yyWi5af?@{Xo?iFj)(T+zR^(1?=65XGM_1u`f?sR9>GBn8Z?-tE;64f zlKLthI+;j&vEYTP@p*-at=gF1H5KC3EHIA6_(Ew<3=iX&fQwnRK0Rt0m0!yu2i&;Y zH4yS(YN-HOY}6v5Z(yNuZZ?Sx^O(vhgceWJ3xvLjNA}0C=P!vBfC8b#HZ4HDl|>G? zae4*k6RgM82=@ULI=x?T3glfL8qF52-L&X36)|d&LO$T3Q@FXG-b^Ua zbrGW$72`)NG^Q)?fCFw|EL6zIR#Wv|h^D!$Pk1KDKr}`BRSM-F(Q2w-3G#EE33gQb z!ni25kjaQvQ}ssEl#{P`Cg`R`f&sh;ed;^aUwgi-Onr;;B+@GSHaB_&+W3r~X+yoJak+C?a+r#tgJaKO)lL2)6E5%~f^HQklv5y5K#!4&R6EiBjn z+h+M`EEmlFW0n(Mhn#__h)1-uLf|`hXPKa4c|%E@38QWpx3g313`E_Ty?9{U!4ts_ z9nuj8T+A7Wpv!saD4tIBq?8e@30mw7ME$!;9vWvB6CpefStzyG8Hk{N%|i$Ao)cdF zA@69CTI>u&3fYH;4&gPNL~Rb)Y4M&u9#n~HzWGQnoUun&%hcyQaf#Qs1u4dv!>F{}=UgHakv za=^v>fe6~iLo1gFN0oku30mwAL@id3hsL>U+zYR?;3jCXKM+AjcxW%qL1DFxdfg^y zu|E(gB+f%8z418q(NZJGLl^M}BB@h6bTAQ5#QlEi(3_ye{y-#k0}CC-CM(==kDacC z&?E8(f~I>R%LM)a+cWUCV}X6Uyd(1my4Nw))MlPb6jSo?6xN#xv@{}rV3dW4%VL%b zZ4XHJ!clU~rlJ^;I}miI{>1X|;X>R<8m^7>^^3P&cCnCNET-ed@kEGv2ETOcWsXJk zxiJSpiy)+K!QLHC}YS=&NBb0&S?%OEA)c()nbQ9ZahxJRqp`U1DIKfzBsv$S<; zlXY%kaB!I_mc!C`uC@@z*gIufaDRZIPrH5TC>H#2Sh7G4{$_f?<>`N8z!Jz5q`?Ms zH`bWV_lxVx|EBE&4>JImAdSU6cp(v$)(S!2tHSPUGHs~%I}hhWS;bNI?(Ev*peIC5~g?FzgmrM;o{tRJEh4valkK5Pj z3jb(2U`21GB$F_2aA3G8J)XdYP^2T1Fa;_y0e#E>p;I6CCDPb8fq9FSCS@x&jm=Qr zu(pd!H*(_#kA7dXX_)dU!vfnEsl%Y$H1V_dhkVWeB`~)KcZa){m3Q3DxwhUP@+Aj= zErGa&Arw>|b{`qQ_Z$Fj-;Kv(xCNPBdLJ2pw1t`L^J0$+W^>Ww82km>L+mV+A5Ti) z_*)c@((1eAjNOQO$Lh6{L&XU4b(&nG>IC$s+lK0qJJ^m?*Aiw3%KnSq(O zC|{ardw#(Mu@iP#KDFZT$o7Y4{-$x#@2CF%CTt!@J;A&q?%U zSi+xUc#Yd8*`#T5sXWaDkZo`4wWdGW3Htwnd>@T|6zJ~({m|0o8ryDZm2H%R(oF@! zQ|L?5CP__G9$Dj-9P;;5Z5L0ol|IeUWLtTvQ;F(j8Nq%a%~Ng!>W=Yo)Va;v`eB&f(nwm$A zaLup4FWXzFn0=s_(}{4-uMw2*BuUeWa1<%0IV zM7jc`|5QkImhFsoi0PR`Ic{GB_v88!7svE{jxw(vqC1P|-kgEpv&oXQi$Z7nC)j-s zBIHr$m#3-*)!9U~c_xBWcafyYMCGu(52`7na|#Fp!6w}?K;!Eq%%Qy9ueMNhafpkBed&@mlnf?_UoLQaOtEarNmYs?||0(AMBPjp9=QNi~X z=p_n%mlIv{(Fp$ad$!_7%50^pSvtdy{sB~wUmET`2EmC37!Y<(N#niIS#>kkZF~c7~RU!u*#rJZ6Kp}$d(xqZY09%RwKBWu$8tm zRIECQ?gpZJ=_&++4Xj@wy6y_tn93|`+9}Yo*6KR4gt|kMDzm@9o7uh-hYD|U7AuyGjZ352K)O>L^l)B^EV^7m?4^`5Ru3v ztJ0s!w05-R+R&fMEbUrh^rH?3-&+V`^6dx~{ek#GSnzcLqJ0^%*45Fz>`349kdWIBTbeLcD0@bz_Ml5IU1NNF!2qG~ko?-9`L%Wp51-&rh|zOOKe^bTbP zav3mEnV}d|>FU7fePZ;&qX_=gDoHzN(%roQowsmTYi*5@mGQ{RlcdpF;>Rg*S2od>J(LKJmhJerG&~CER}#U^|3L6(5bUfG zJk1c)*BJyQAh?PM8lFM0jv?4a1irq(-dsG>*3s45c~EAcFUv|trLuu&uX+~2yd{!U zp)uQTO$)wyiIN&N67A*BAsF8-Nxu$LiP}kJHd2L+1dvOAK&XnbV4$t5TO`NTgmuUB z2sQ(2k|KxAwviA@5LzLaq`8I=K79efuRBnaRfKU0!XAVW@9V5F=l%mK_3X z8CB+2$i#=l|EUiUJkW)9R^cy|?kFH{Qr#uv5I!P$|Az?X9U@6%H2R$j={*>&E>kp7 z2=Xz3+)E&TWI(1Af~ZO?$i#J25_3O7a1`iw(S(>@NUsPX0NGAL{P;0~T@IC`391>9 z47SpJ2?2J0;rD|%QD%YjriJ18%&U}DBP&g(-Z9OYs*QiMydX99*pTzLP~#$prZ%Y ztLfoSCVEvQPsdPWB;il=bpVPqT0P5Rf`%zl(^-5gAEju;cjH3aoeLc$P4a{$+vKKE ztD0;lHQ9Qa74Z~#gfa8ux=z)wM#f(Qkr&ly@z zp=*Y>QDI4{DOSQ1zb2)xIRQ!^{4>6l$%-A1yK}CUg_cVv!ENC*nC*fq2|s@$CjRr(+bED5tR3%k>JS=DG9=0~A%k*I4Nz|&RH6Ph0!l93Yyf&XIvNL;m`meFLObaOpt*piU7Ca zsqNu)1gJVk`wn+f39EJ^!w~bBF9A}1nSxT1Tyrqg7r{V;1wNX9=VMlT_@txp?K({b z09LK>rY0NpYHZZ0u#+b2A1J8b7&0sEdZq(r(3Lf#A4BLjJOuQ^kHNP)4I@y^U4{`T zHHXoz<91zKrorY!K9)e&KL*fG3A9f!c>DMp7s`s%cEuT@;ABN`>WA8EegS|tagN?>%8o8(nZq!#M&%G4;?A|z}x1*HcYxW*8OEz9ExcJLj*maUeg zxr)g_ zSfiC{YKFVW5-wjmNw$*+@7^zgcm0WmUn4m%M`w_yG2+hT+LxvJ4Oz&oolLaHeFfTI zorG^=RO3U@<*flO!_i`^ZPhY(s{yI>+^oFXDFph!j{ucV#<#mv6Wd`E`61g@9U68` z-9Z)hZlKDgTL~Mzv1DdNt|`-=>l-ktp+3$FL+Dcp{|<*N4PQ<8S4&!l^-DuEl{k(X zY~(fp!qbRw^EeQ;oQiK-l-!Ql$#CM!nrwYda;~XlWz!g?+SyG$y%|2xMpD{jtc1xs zQZR{v(!CI>Zizae9ToyCf&gnsfc_~EV96SMTcc=ZwBw~#nPj)s5mZFMTWH{^P?6q_ z%nBnjRCH?zYs+51lFyK&gA}u-mKSyIq$c_DCfgqf=pY4ciGijJ95Ws9wk4Tv4(@b< zn_mvNcEAnas1_P$m1pTj-j|2#80as=I)kw0RRL?4Gx1IHG1gdrF|fRt$Lh)qq?AQA zPPQ`%FS0N29wxkns+FqEgUu-6!{DrUMdhrv~l z9#`g6aSp-mJRh*JbMS2rTVb^>94hQ6qr%Ficju8YNK%JKR<-tALS7jH@^8<@H?5J+ z>j4#lhF@xZ-3m~-l!gnc(bMQZ z{_ad_Wn~(MHBhyjNF7x>^#q;Nn;TEPF9-FQY}CQAQK!U4t-MWX)2OkuQM)#l8X=jy z|7h~HqsU|0$j8~JM(;`0a5B}Qa;icOGJG3Ztc|S8Mz&z1lCzPLZBHPOpQ7L&6ueKt zM+ltT5lq|(-5tkd1omC&+f@3t8wI;luqXXiM&ITmkUjKmfWGA@7@}YW1&34c7YdG~ zV3>mADL8?GlPFkA!5I{sMZq}~oJYY06l_6YFQsk@d0M?jaFaQsQE=x|!F~583Qk_H zO?1kR*9qWF3f`vR9STanL8uymZ!nwd>rn=MW&>Le$O{Pa{kH+xb~(N!71JFxUg<1R z;n}F%Y*cPGQ@JTcMvc8qDIO}B@l-Ol(%tR?b8U)>S=PtAOcy4aGkEew9}mgugk~=U zxsU`|@(Bd_;tFk4FUx8#xs-;%YHpN#D0Xek08aw(MMV6sPeFVrEeSk#vtrT1evn!Vs*&BP)-6*kJ5sbQ>zTHXR?nU5ulD<8IV9YiI@*4>3Z&C1H3f`mNw$ryS zDEO8F2@mYZb_zyQumc6-DcBK#eJ2X0P%w>xy(n-YkgF)zn}QkiTMY&D3ca0PkeBIQ zc$waMm+1v}nciiW>9uv4o=}(R!E>1&B9|K|p!d9GdVO1_SFvS!!&;`trDb|DTBhfn zWqOENrYDnSdfZs1XNYBbFj%IiePw!tSEdJZWqR9IrdMcXdN5X|w_Rm=g;k~pQ)PPG zRHlbWWqLAHrpG;HdWKV`2Qy`Q+ES)RC}nysQl_UJ_w)> zSY&!DMW(k*WO{c*rUyb~ddowmM>k}89z&*gEM$6dLZ-JNWO~OzrWY4vdK*EeR}5r& zZ$PG(0c5(vU#2_uWx4`irW@*Ix$7FL=US!kvyQArHT$ygOmFfOj zneL7)q3d2t=&n|oZdaA*W>h;}WooBuNbPiQsGY9-l1IrsF157Nb(D4q z=S^ih0y|yaDAT=*C3I(^Ocx&7>83(^8U2&)2DH6#|{Fa>m7l1x_~$#hqdOm_^)bRUpRH}}YN$Bs<5;mCAvjl7Nmx(i08TU%thVMV6P zP-MEcM5Y@?WV#GQrfWN7x?w}6yD((Bw?d{HCSsl-k^Yvtjlz`T&82-G9B2K=|Hti2cBg*kSx=IVVMs1%5)4@rUSF`7z*eR zs!Yd4Wjfg@)6q+LR|@FpqD)5%WjY2Z(}6vij@HR^2u`NsYBC)xlj#VUOh>e2Izc7V z0VkObAjx!ENTzc=a*zT#Dg3+MaD)F_*RneF$p&jg#Jsn13sgl9&h6*RJAz zNH*BT2=*dmzjLvtzRu@sjU!WM>*^T?xZ|g`wlWLt{e8+-!7MoLh-3=Kqkk$%iL^me za$|5oYrHWo4gXbF9O?L+YxCj-QprUFSw^}F+c?Q~Ao7&!$=24)YOk+b0p?%n+5Idn zh$@jnGu4u9@-(*A__1QE^DF_+j24+nw+7P~_UmyD#2wA6tC=syQb&n&)_y89Syb~} zY$eiF_7un;;Y_BctG32$EeoJ=N1b7lH8qS)P6fi;oAU~3{6pi49HWm1$Dp(}<>Nhm zfAhc!%qixLF$jnkU}}1iW4RKR-HgQ(J(ndY*|!%!a~+u+7Ji}7Azh*Wu==?~dKJSR z9q+(uWcei>>u_+pj?Z#~MGe^>c|Ma%rWkfjhgmsJ`#5RzwAQY^C4);L*v_h%p%Qbo zVnIVQYs1GwD@(Wp3i{k-X7mq7mq^dBd6~^*r3YErfhm_cOu6g#U2tNSBh9(A)zY?i}6AK5KSh=saJ1%e12ge{YeBJ~MBGxHBZ>P<9 z`${(i7baNxi=f0HV>^*#<4{+1eP{mwlk;a}m_WW(qiQnMn%qq7EVa^tx;2n$KtloU zild*8*xeZc8Un0u-vI9Cu@$}=>M&~jKS4W-(`a?DZ*X8}?h>AJAaxdQqYlL~pQ-vCIGHgE^Y3~#>_B;riT5Po8dzVt1PM;(*wk9E*%NGzVe-4E zrkcs`J-~2qgQOp&4OgjXm?hMuUjqy-fy-nO!DFxT1?Z=H)K_&nX8 zl4%XFvcS(7s^5gj%ed^+2~Q~ipsTPoooFhRTwR~;>6eQ^43y0cKqj1I`zJ}AkX8HwQ_gnl zjRO8H)p?)i_c1PS3%bRxb7j{M=COOnIM!l6w07#Fy|1UIuQ$INoA!n{sN*_3A9eL% zrD^NoWo-;MbN$S(?T#R}h?)S^ou39;E6^TM(3bI*SBEk*ERUM8?-_2Xh6cXZcmit4 z`CKg#bfc$3gUfk?3Dj`*qVyJdS*qDuKwkHCwoxZ{Y4nbcKL zZ9WJU)S#vMbtIEZbln&6Wi%Gqe2Xu|1Nq+SVX&botdTABHu8Nd|B8Gc!m+AO^=2%_QD30jkl~fw7+%CHaXW=z|Jx5?F481by=*ONq2Xo6A-bP40H*w}M&$Us1F1!8Zuk!;;?}bxqvi!Dey%^b zA1ZN{#YSh=u&rxBe*{DCYm6j)&8)NB0Yj_#Q?p%%XQ&^CZWt(T)`~ohL7GwI3(XN~Xw~YuGZ|27u={8EPAb>I$0EB~&?n-@VFMvP!T*1Jp#(LX<~ zwOv_%K+$&SwR(bHtB+>bFRFpb876Z#*iYx=R~z)g?%j=O&~M|185o5aGbiLT|I1dG z8Z_jFUppGHmoq{%*VHmXyn@&kUI=9dq(BSrUTQ=Lv3qTPzBhkzN6lcJWtmq;Ho zMzk=IY8pcSm$Bo&V1TtNXUBCG)_57zKc4BU1k(-G^;kXfb+=`+WK-X;j_PpDTGTEU zuCt3bR@a#NB;+LeIKJrhnJnj9aQ!|%e5i)q7`|dB&_Br8O%3U+uydLQ$gx~PeM+mK zYd#Uc2$uO*UX_cuZpb*eqUSiI20!oa zm!OVb$m9}(MZS0OYdFqBX)b_<{mN{>`MP#4=a9AWNP+3jB4@?b0Mrko8omY{P3N+Z zOmiK>8&Qe}ag5Ztl!8gZx1o$nSw1x3VDNbne9p0Gl`jlPM|tdX~T zj1!@7z_bXte2FtQc(X#AT!z)iQ7tr!qAv8esvqi9inJPIBzdZ|P8!C}Fjzu~Br|oG z269|ObLtq!n8gwn;Cs6>z1aDT!iEW*0m3JpMEtmxC7QWgM7=FT8`P)lWPDZ}k%r5n zZcRH^Bn^#TzI*!-3gs`1t`}9aW7S&$@F=IRv}s^C@F3l%-3s7PX}Cpy-AZ}DU( zbUBltv0#!4=fS0Gn3mSl2t^vLERDYEIYp*Tovp3VV}F6qG&xMn-k;PYH8$o3GHpGr z?R~xNZMj*-w9-Uq?J7lUZVia$fN5gEXsW3Td59K?Ibh7PGP6Z~ME;o*vY;Iw121*R z-cTdX!MA1)?dqqqT(GpA)mC<#v{W34rc>`&N0_bIFaV@}S)@p-IBsCfHZgiVcLRemZ-R9$aFScNE@tgHqn38PkOA4$bXC zSKVlyPKWW<@XQ)b%8M@j7E2vj841PP8&^)L=0x1sST zeiBw8b-3+AXy^=LCdzB<9rncu#riSP#iSJV>Woq zVf;z552AXym0qhfyh^WNR8#kC!h>MTR%R(LQkh~SD;Qt42&c&MzU)R2oK7PHbRn?M z5vtj&I!IWY)z6MK`Ng05I&T}+#q>q*Js`v;MPGxwGH5EAn}$P0zYzB&m}U>vI~R=E zLz;_x+DR5ZnXMa`^I9~pg3om z^TbnOMz_yUN2=J)jRT|Dyr2%3q3Utcb;3BfKE9r@)r_j4pOZiv%vm(&Pop_s&Xy=U z5ZDZ$3%JZKY~ThQRoGx|gEM!{$HBtdIo_^Zx-Z*BJ6x634do=W`3Nz)#BnCFNlP51 zuoLP5p3jatFn~1bEDaCmagvz3$$!Hvva;lgy}__n^Mb2xSkJ=}?uI2ewwh|IvQuAL zJqo1{qT(KrxSS9q94NyEofQ|odIKLu_LC{PUTEVZ)yr=mUcr0`YPWaqITOb_wmr;r5ubpKUG-E z_XUdGlylQ+>}ePPU#;~oyV}+MCH2|yS0X*hdI)wotP7DFn1ZBUi>YT+2bF%tsZ^EH zqEQ=0nQ!8fLi>fA4CW%)U)k!V_)&8QVUATZ#GU@=V z1jm((-CQ)qW~iLH5o=f%0rz86$43G9G;O!)>C4v7UP1fX_SHvpk6Hd+BE7RfgFqL-YqQW{BRM*UPz+M`1HlxfB+& z8hXe_`_%ohrr|wHkS7J8L>x7j^pThJM~gUeRBfvuzBwq)k?IH8cGe=cfN?vHT&1)>wu!Sd;tc%v&LKX>ewZF+&d$NKAFZEQ?`f zlM(09h-u2Nx}Kf$qf&p7vl`l@%TG2fh2fmd=A7*(KMjEA*%GA&-zd>6s`KmG?pxI# z&em)5zpZ}8AjM>0g*!zrMZ;0cG|K)=mRi;4^|p6kVH}(=lMR~8HdIV{xSVsF)fTH< zvtZn{MsrL6MsqwCIen-Rjw>@n(@=BtY;G<14NK5kaTq&{YPo(*Dcp`-8RthDy{-69 zILg13Uv9)2yRqCz>#o;p^I3rdnfWX-rq!$fm|Nn8+0+AknJZB^Eu%zNAU4356YW7U zW{^ii303=GP}e%79M4tyJzBdkMb!vqk(n}BM0?MTLbwIkFEZs%a|F%&9Kllf(?{4O zsiqh=EL-4kOg3gl;o=ku{bQH7 z2b%*j$fCB1ew=iP))DB?Is&xpjz8qkGy|w?us7Bs2zEO&Xi`^XxxLIsU`2Kvqr~PK zb|&IK0Ju@#R*+%}p8U+CTAs*-aDyTTO75$@spQ)Gvptwg)|>Nbda>Qi)ehR`S1^y~ zhSr)mtu~mZuwJ)223-;@pZ4|{%PhyjL;uT3syU5SId%A99mdu>ClZ{6o%HKQ$^(fU-B*VgTHao2Q(Vyf5a9N&U^EljKgCbE#d~%XdRQ8rE#!M6yQ8R{CO2ukzZ(o$iCCn%i+ZOn>+kG&MywU_yuwqvOl;3cQ z$Epb5N4f=_l2*;*FHtWlQ2RS4>x0=imm_W7qi`S7^Vq?&MVVD-8(Pt-ENQ)~LdX)` z4ya5w*3bE=xkkK?#B8UYh+ZzuHSP!`nxR?4=a}}zSPUh1N4D2#g@m272Q_(^&0}N> z-{hSs?f*BroTZXu8MVRs$ey-*)2cwC4L6M72uR}~4ul}mSRx3ZZM*^fZwH;@=T3vE zw_60dGjy3@Bld1J_Gj9=mf{`=W4`>4Al|HW-osWZE*$$l3l*=Js4mYgcLV&>P1soIGb<)bbAj6RA5pOAnnWSXrnV(#*Vhx5cv$o zQ#7L*8~vy!5ZT4qD;i4k67uJ;*f*3GpKhqrY!+s+m)_tHG4P96FLeXpU7YONmbk(d z^BXXWH)M2}8)$4`^q3QXd6}$+QE6r$&5sUfM}aXqn24_2v-_z_UpVuM>W6Cgd$rnO_Dc}sI7?eGTo~!i znU)N9gA2To{O4h~ytyl@HvV+szPbW?6h!)uBGQwLt>Y+^X=eW*=sn1pn0XuEGf+)G zr$fvrTU3Pauq1K@hh$oc-wWNp1eXBw4tz)X1@QVUp9JTRxbwpgBgqwvn`-9z`>!H9 z2lK+x{zwaPKY+Lqo|T`Q`uZ0bE#nhl=)ooV%(TJi42^{_3UP$vu$i$r0I_aj^2FqTB~B`YsS|XPTFVG<9z}HsvpIY~m*#)zwyZ z>hWg98vY-9-vM7$k^TQtBtar15JK`m4J{Ojk|MG$B2__=7C=xG9sx86NC-`V^-)Bz zt%Y4(E4aFL7Zpoviv=s|l2x(dBKER~%BqWn|M{Ld=iZt7?hBBu|Icsp`P_Hr%qeru znKN_e&Mi6GZ7uk!-HX)NT75vteq8`7u|g}8MvMqeB5b=~?nZ^zeF+aaA4Cn^V(G&j zKzG-_j8y%}nIMB(#V6BQrq94p_Y@hhiR>--lW;~Vk_K32GCnP_NuIag8jZF zK4gHL)f311thDq6Av+x2zX0;z$?Hg=f16K&ss2tmcFw%ZmOSd3Gh~j$&7P41j~O_s zKV6x6w|fRg(x-&nanS!K;Wu^yHMWHtn``Cei8Lj8i}c@9Yt!8Q4GNO?ycq7{Uo6J( zJ~6gw?d`CGh+(7?q+~CqyhHI`kv!D2>J`1dkcy2bEgNwo-bTL@wwIE!j1F9i>h+Ea$7zD z4+RV!h0g%at)cZ}UtK>gNkXCb*xb7Xlx^PK0?dHZoUY?5MrX104Vm|oW1g9^6Ze5H zAOnBEsmgvHiEPB|M}M@_oSaB&bnBZ0^t`h5g6?x9+RwVXgM9^3d$QRdX%Z<f2EShhP62>VvR*=gx3lD;JDt;z9N-a9-)oFF;I4?xju<2_4* zMcEi9(fO5@#Osi4G$JC7>C!U^k3w8T9;|dYv4!Y7kJOST-(Omj)>s-e-lX+B^+0F7 z!803AMe=B(9;IRH&zpRE5_dSgX%pjmM<8yA<9ZRkz_(Y|mF5mF?XU5_+e^H#e93Jq zbP%0Hk@$0vFL4GrmDtV+E=--JYZF?SUh9N3@EwKD6wn`>ZltYn=g$23w9oM;x$HA> zMZoE=No0fUDLU2kDH~^{O+Dn@pTidccKZ8rv@PUK;y9%|A}h#aM_G4ywHr$o;<*BCqbT<}6yZ(eUu*EDVnqoE{8&O?C`*;98d}>|&r- zTKaA7GM&FeWj!D8Ah||wh3D%(Dxz(h_*W<;^pW4%#1ccb!L)mYb~Xqz`t{{4bJf^(wtv7L3a9rvSk-BB?z>2=3Y zrw{ZNM8XxBWPYQ4FnLY@ zXASym5}BBcL|^K%l7VhQ^$cBfVfu*rUDLO}-8c9W$p%YH-vM;O@*XZ6LDWkBj5hd$ z6RfitGHI3*o+SH-KTsU!xgiJ)9=wW~ZOsCBrNh}&x|SF=*`t@P0KCC_1_kL#-bAK% z@@YD1OJSpPx6@+qRMVOij(3wT$@hUirmU;Bv(A1};|^+QlY31~pV-G&b*=vZW$hX7 z-c28Fkbu&yq`}TdSuhX|vif4cfB~T$+JgA*6eapn6vnvsS`>CdzIOIw62FFX4m~`v z)S5E!Tqz}n*Y!2yH;pYcOaC2_BBTYlkS%tq%gJ#ue?`0c0;cV0ab46G+-B##IO${49YQnIgk@(HT z%q=14e|CG2A4~H#MG(yIEK`P!9O~XWT~4W#Ibzfa74!+h{yoaa@*~Ov`_nkuO;aN` zg3F2vq{qCASo{3anivYK9>a4N!LL}{Oc7mYeY0n<{mq{BDe1G5&({7EgP5(~FU0tm z?Ph=2qsc!}>Q8sscxFy`;N?4F{F#-xc(l}di-_*nMpor}UxhO_8pk^MV_s5E*n@k& z5&gF#eZP~RV#52K-u=?2s28u{hnRln532rS`qDds-q$@E(G#Kg0=N5gY5fnshCfyM zYc~|wHB7u|(vFh)Mr*nl>wF>YZ3_I=Hr09V>lLCdwbNt_J_+HxdxWvy&y8I8$?_$d zbVs=c^8}Z;wBJhi;6BlZ5U0$f0ORX~k@z6Jl725ak)9-UjG+a+yES|gCGE$K8L~-{ zc(pu-M)ZPF^1L&?fI6E#+@X*8bk^16r&gNbE@e;JoU^8_d6D$%@lVCwM`!h4gnMiB z3>pR>@-R5r8rpb~i{7Sm=9!PEKTiwr3<~Uje@#5sIlXG%g?^2?EbfFL`Kwr2r0I4i zqG2By=|MsL&e51`(|9@QD{-uM-wc0@=*L=`9i~)4og@ayiB?-=v+zr`OLN zD}yhY#23(V_^qPWIsBd1s>O0NtdYW<=WBvFFNKDlEOl->m{Yp<*1|xJ~HV&-0Xd5 z5_57Nr)j?1nmA52(#Y=Y1kQcfZ5=uLnX^{1uXI*WGsn5jB>P6-W@_kOYq;_I820{j zZ_@Rl-4Z@nxs8(KDaRDLsB)8J7_k()z6PG8tR-*nb1#m^S{KJy zNc_QV!?|5|JT-8?^w}6%LwVn|!W+Up9YOO5L&7QQ=|<`E>A#o?%z%DX*j0uW%d>yv5L*hR;$rrAlhjUzc0tLnN_o}7du4H zAa^EK(r~cc!<{Dgdkk^%?=M#J;e!Y6weA^Y&P8DnNE|ZxlqBVD+%f(`_LSE*Ndjbk$?|5HV<|0G!LNEeals0zUb?zz|)1F+xFpJhBrRXquv_VlX`2`EbP~e($1;~ zsXLpW#PcssyX)zAx4*@P8{OVDe+yFn#VAtFTVwRkl5}zYQDS8}{$Y*tv>QF*rCVSV zDbkOaofD_8@$s{SEB48>gg8b&u0oe#^pC#HQlE0SNu+mD%8T-nHNU)w=Tn%!Hl#K) z(%QZ#qH7k<<-;i2ll|dw!a)0C8J8I!JG~irNq7$R=JA$?d?xNu9yk-fM(3yVtZ{=| zhR&xQTF|R^&YS`Kq~5DNFK^hg^08(Hg{)y`)NaOd|? zPS~mLT}^)B$h)tJ6H{x;+9cQdc=PZBi;bp1x9h4Yv7eS5BI+^z=XK_Z+Y8K)%Zyy_ z%ZuZ5P>l+$J#oTt z3h{9IE;@F>k+`dM!uSpE?9gozs->_}JT_TYnuoXSP99GjJN#M69-)Z&G;2OQ5wCuD z^C2$MyE$ITe z8n;HviOyGp9;WMB{G%!Fea^jmVUpkLjDJnj0$!M$PVHcW<1#1XM~`$q(S9J!Dc@p^ zY#egWV8Zw5Wd^yg&C#qGAS z_)4mGlMWk{y_}YL3744q&(UJ5+?(5m)4qx~wc&-B_be-D{JExO<;7=ZSPIG_5@$;KqvzM07Lq>Gl1nWe;7ptM+i8o2; zk5)e6)pyAPr$+umu=y4rOZ+YwDZL4{S7P|TFZ6FXCOB`_w5AUJq!2y)YsXx8;FQG5%*e}* zMZue06UY$yzsBB`X8($z1CMpaOcs3}^;{lp3+QTs*W2&uY=4nukXpJc?F_Ioy6pFE;Nq3!dE*ROlSMvweBHYHhN?4&U`${9Q68K%S> z-b$ykzxl@77u9$tdQxI*i90^qaT>R>Yy{q)^m6wc3c=Uz|Hd+1HbYb3uk}!A*EZ3Q z#4VT4$&EZW6O(+G7E7#CU9Zfo*n~6Or{vZqr}2@&r^Cl*q+gr#p|c78eK0(B_E#EE zsS*4mTK#`4rTp>^KjJXh|4+U48-&4s$nuI~IBiNK-VvHe=jAu)jb-|Fm$`m9-=632 z^>c47ev(4*TZ=l@IaO^TYIA4!b$v72i;3%wc{JMY7G1a<&9~pYd(l|?ZgBd{eHeBGoicuJ?caJEZcQF zhVeS_HX2^L^%DY9r^imyCpuc2;guPg;B+DuM}bA*XB5(@;xg^D_IDq==tHh{u!dH$ zr)}{8i>*%RgE!HqXQZzPekz%F-uh6cq*12)fik5@Lvq!Ufv z@(DR74fZ2==+Y z_9uVR?47vqA(MNpfkNBGw955H3C7v}{tg3Pr}sqhi2Nn4`_3cu2S?JYLS7!2pYW{L z!PNEJ3(@yqIiU)9FZ~x3rU$LvZ#?#3?SDT-*G><}I&2JGaC`S%;N}=dxf!O3^XfJl zrkA*!$)>0%8Ix{}Xk0|#zo=P@P| zQoS{-n!Y;kxDfKd=~y!UWp|&SznkuD^CP>ja*V>8LCytN2l8&P)ev9&mz4%~mtUp( zymNSQZtnWLt1I)D?XfqMzRG5AxJ{tuGp)?CAGK{mv&W_Rv)%tA)54vm1GjZGE!2(l16fBWn*knl6QE&Z;?^X25f_>kbL4JPwPb z1(j#g;{x>Tm9iciQcEM#=^naxN!*0`HT`e6I$n#&_u1-Mi*)cw@ehM${*Ed@DWOVr42CxXE*oL@)*eBN@9{^8B>&Xh5l9L%&B z=yEG;b-Rkj*dS{#%FN$ePFGbbv2Nd8dP>&CqH!0aj_h#s^fS*qW9}>-cKY@r{d?TWQ}D=H-^ueT2A?p1 zK5R$y&jV$OPF}CqM&cJlEQm& zF>yIHomj7TSoy*@@iL=pT6!z{QNW>dXUI3rXtI${tUpCvu%0h&Zn2jh_;=jio%j1_ z<#D||ZgAh)TfDzc4t8@KOjwLQL>6aQ1K3`q;W^H8EafLU%4=zwzJ)h<@Tn30#{}o6 zM^b5UQ2OAL9`ty>C5#W9c!uFF%?hXQ^liU{=r^Zce9fMku;1rRO|wbS7mgzO2PV!V zZwpC&w!@L+cJ5D}JsE>J3+m z`_+jlq~qF2S|B_97% zd&*?*Lt;piI#)cfoI52W{qEpHIOda6eP_=O|J2kIJkQ=_UCO%G+&C4^voAXN`09a(?3jg0);OhI;)me6sfbUL3^U}-SzvZ!I}1u=dW{` z|1V9$0}p4=AH8z37d)R2x1N&o?7vFwf4@F5EzPa$qO)Vzd+1XsnO}8RvHbs3y+te{ z{E*C?L#V&KMHBXkm)N1#k6K&%WzC7_Q)j5qr0k8Ab14W9^OYdJzQ(s{KGGSXzm;bA z*DhX~!Jf06?g{)uC;VfD-cBBx-SUL-@&Y~f&mRc3wRn%A9?5h!?RXNPbVjRBKvXNFPEr5c_}??a|VXeq}dZDSJlj-jJ{WiCG`=z z>gBC*r&fj9C#k>4%Zy2tF+Q=BsmLH5ww3e`E+X+qw0=O6`X5TzXcONx%3aCvnnXM1 z@!?u`Q*T_A!#xS&I;DKgo2~TUzv!Q*C~>|L?a<_Nhx1QAJKRIaOS;KCAPD%z87ok>{;9YZ?*uAKPvB?PIy)46y4;lZmikz5~($%Aw*uJVF z2PGq{PJHpcN#sC}Tip1a>N)W!vwQ6Y<~5~MB&GaKde85t=TvCWNF)>3T(b0i6FfG2yG0(jMoR0{RY#3sm1D)&!Ru~Ev5f#L_U11{5_LWPWN5_GRp2&k>;g5Q3PHK zx>d>7nc0D7#D!YKe+jW_e|DNd42 zB0rOkHGJ2q;^U1Em9yqfkn!;+C3W@NlvH>_Nn?zZ*+Vt|TjGyO`_w#N<-7NoQbri5 zseW5^N-C7LjCF6BYT8STL|!;Kl9o25I+79Dh!VX7lo5FerPFJuvs+d&(wiuq4!*ZhnhxqaD4hn)Te)rym9}vmO7C+Ws2`#fgXWJ> znmLb3^T$Wh(hu!9iHc`&vHWx@F63e?L&g0Lr5jRIUc%Kq!Mu!%q98mVOl3TU>a0*rUNFzG^mAnKc}M$9Z&&Nd(Z*XpaW*Y1en;Hj$U-Y zjjnXSB{W|~2Tboq#}RZKMh8qQq@yn#MRdSqxCZx+q@y_K%=L}9p4jeUv`JNE2s@K_&r?LSnH_fKCa0`&AixLs(64aGA36xK6_q_@LIz_I5A)vd&Fa?szHbS!DFa2 z3{Q9rmCW$8&44DJhc%uz zgZgGl33tv;uFo>{F{%89E1PmGdK}kjb^peeY^YD5$JE%Mw6~Wn9~oYrPgtWwyl%-KI8= zYfa>;X2oh$aX!~)bDLbRJ|1ML5drFeLasG2Rd%W_vY4e`sJ1iL?k|y^QbJW-xyo2< z`h+UGab**~N2u;lr;d!Gy6%>+=?$tZw-~uEsICXsc@39RRnGt$^c`u{aW7C^FRnB3 zU{AOYh|tGk<{qHBeq86ZQ$|$-EH;il)eYjhbdn-uFeCfPbU25xjP@PdPoIuC>^8$% z*%5>NZG*IDWD6si?Yl4NXjnhzibha`IkeS7$jOXug>;4j-huH{6bBnp$I1nBI$|0c z%lLkUM)9MJHEQ4S(4JF?m`b;fBWbA%so0E*`*p10nY+0mEG9xZ7aJYgaW3l{%xL)GZqKeKf`*Orr(DKrfiJxQe_@x48yL5-QDBqm> ziaPT-JzkWb*$3ygqWr9h24=?%%w26@{(1x3Yz6Gynb$%d{Is3H6&{?ISqQ#pNiNn6 z@q_cS`xrdGpMjA{roPQYz=!f8aRW0~8<`e^Y^EsUR{hj8O>rxwQFPA!a|omv<_ zJGC%=c51Dgu*;3or&T@Q9DH-%|BZ(m{xheU`o3Lx z4IEckD!9U)MaKVR@O_~tgSlOeJ>z9OdQisccp0DL^Ub&%pKr$H_@aInyxZXf**Fd_X%yPK14EiFIkAU3%A{j3P`!HR`&7u~j z{Y5f<2#Oxl{-PG9{Y5gK2(CBs+OC1?@=f~$x&3uA&k^MI*X0}k33B`E@{RulCqm!4 zeB(dCxWP^P>!iQd<>w2ZX@8yco5EGOru|hNOg^p3HSMj+HSMg*HTqZO8ojG>jlNa6 z#{My4{}{1*jMzIy>>MNZjmbCiW5k{@V#hLx`!b35GKuptiSIIr>oSSwGKu3d8E?-> z+@6tmJtJ{?M&k2~#N`=@$1{?@&q(`Q#QrT}{}!=-i`c(K?B62xZxQ>qi2O!rf1}_F zWnL#(i2fkhMEXAMK})$vi&_;WeRT2w>?^A37*A%_GpzYcsA?n z(JEK)+(PK@(JEi?e4)1yoX^W#*W1ipb~*l}nHRWD%Hee~pFG*h| zyi;6gwA+oeO=O^(_>;39`QXByJXD zJ%k%5alB9Bc%P56zWXGu1X&q@6)0V5%~RS zk(tZav^V$~nd^dhkpBo7;|dRyyxVIid3m7Z<$;oyUx=Q)hN9;S(es7qd0+G-gHN|K zbHdXtbK{6ZW=_^>19Lf^r-}StL$TvDvEwwcW4GwpYbbhli=N#&UPaHGy@jG@j_8>q zdNR70{@!a?V9xCs1?HTdQDD{%v-2`1B3`revN>);OLF-dW@t(Nji_HPcJ4J4dzXv7 z%f;SiV((rJyi{Z{P#R_x6bdo#t}OtF_B>&p~-)s9m|Uy;~RBz6=@ zyStW{Yhe$TWb(YRt0b!(@@iKCp4-pV8yGv^$a}D-k&pE>^05S5#a()rS zJ)XFQ*I!@IS?LBAWE%N`EP=TUpOCe*!WX4~6t%>omD@CsdMej<{yHc-7 zW&T~HP}VPtWFA{2^H)2$wpSQ!XZq2D&CPi$+T5JCqRq{D>-G+Y&x5&!@Ah27cYChk z%aHSf2lM1Sm?!7KJi|9l_&g|l(}ZuD@O6{Xl~d>$0O6NK*s;k#Sn?m>zB-4ge^CGM9=ygev!zf9tOnZ$jwocBB^=bg=RzS=D3 znY$z(JlNdi@mUK(9pg11^3$T8)#qXUi*e#eWmfI`j$b=U;Uuq z&zknDUlaTz!M_ze;{?Os%J@^=X@tR#5d2u7pD6fggAIMY;O7~BKmMbb?#F+u!9D+l z?)g8?&^`YJ_xvAi=)+BWEhh@y^Izzf8h=`@mi}HV`1(G9_J!`X-#5^{;9mRE-(LGd z_u3cwrKcD@t78VP6@2{^XA(5(CIrUAeCfaWrG{#kaK$=_wtKg-TD{97bmTh^F-+9L7V@`TB!EfTLS?_Os7k$7!MnaX(2 zcB@j*FI_qqxU!QAe=g^Fg)@bJg7BwxHv9@xg?~@*aam_Pz9JpZB*i_Lr2ZvY*S@sU z@GIO`J<0fwUb<=k>>!Bex#CBQpFw!ld4`W5^IawJN`&T~(%$lSUvBggWWC)bzCpOR z`mXANsPtsOB9-G-S0~j z=1($oh33BQB)Kmq>lKdfYH)#wX?;ihqR#w$YW%HMsT}{eIvMz+ zT(cMEwfRsp*OZP_aS{~?)Tgv{`=7Qe?zYE--pKUSLFWV zD{>9@id?(BBG+!O$or)S5l5ok>^dO0$mHh^HXdP~N7#6Tc^+Zo5$1V>jdH(hb9O$*^Wv6Q;o0B#=IpER>~8$x zmib!&Uzd2l-qP6d<>8I+tZn?u!+*`^+#qb$!_*%n&({>l^EC&_^ECw}=J}d}67zh` zL3!r+nup~Y)`JqKhvh!$Eu9M^)Gm(rM{Ui1fd_NU`t73}W8;uQLm!fD>W5@!vyVfv z%{}cQ*@kbk$ZgIs`v{wJ4BzIQ+|_7jbB^KPEP6Z2`CH+$GAAhPAwG>3-$#qjJtPJ_ z#P`wSbDr>J3q4QxvxP5P^yLZvr0)4kVb@dTSvMM(%X7=5?pghSPwH;=`=2V$-v)fU z%t_m2PTDSW&~}-7wwIW>Vta|1Bd(QPXwou^{cqCJ+;_P)+uWDAHamAB^fr;)h|04N zQMvCGZDGbALF9@nzHPxZ)LYH;zVhwjg63o#JN~@w1Egd8hb!r})`L{JcLW zenZy-3O|rJ%!6`n`9RLq#9OYG?-dDKht=rQTP`O<&$rT-qw&f1Fh9?Q;+ z0M2ij&;Iq1IQNmctdE>K`pEukpOz+X`^dSXkDM#|$ehVUm@d#U>xxxxLV+Pfm;E0 z6_|7GF1gRKtH9{pCF5Y1v8S2XGeztn7)QGV zR|{M(ko9+yb7METkI^m9*wan!V|2?ies+^{=OURm-;{aNhi1Ncv)sT%GLQPu%%_WF zUVT&M)$c^#+QZGfA3i9!9w^;_(U82wS#$Q6cA#ayfsL%lV^1&L5YGo*xfOVj@TsYh%qIRClSZ9WdAV% z%5ybm$@4*DddNagkE9j*FCtm7V)^Z7iPkLSre{HV;skIK9|PtMoV#NTP+?=_agE4$6T`)akE^9-6q#zx5@hRX1NZ#S+2uw zll5qs+$SrO`^;r)&APNq?lYHd5?t;xm+cTdV(yca$$hi3Lc!&}S()5tE|dFaWfO%i z_sz=WKC|C`p9sd4-~IrDd+iI|Yv0@#@!J>NYv0^g@!J==*S^p%6@ONn`&@qe=02P6 zztFw*&3!GueZjr<&3!JveW82p3*Bqq+&A*u7k@X2eRAK@kH6TTonqo7_bto3_9foK zg)a9k%e?l5-pA}AmR-6A@50B+h6}!S4c>!~mrWFW(;B?*9xt0E_>MJrUp>D1GGpKB zHOBtcb%MVu_?LpG7<*UCeYn+a1(*A9tNR*zR?B_3)iI&VeYn+2gx=S*zxpy`-|7*9 z-(&1s9TU864c^_4udWvSOXFXi*jp#}IqSsUI=RnTC-&CKeaxS@3zZKJhzFx z+wL*(+$Q#Jt6PKbBE+|ez1zMt{V`DP8}yL-29L`93x%i1e5!Dneo@ z%6*AF!4lysIWN5f?DF8hxV}Q}lM&?mR2AZX5Pm546A3ckhZ2_rxR-nb zm8@%XWIdZB>)uwft}Qj!8$4%AIUa!Z(c*WT^)T~DS?d(mM~l;EgW?z;o~*2&@0RuR z-LihZTh`Ba%li3lSwF|*-PG7JGtQF2vdn&HCsvj<$-wNT2AciOSXn-=!((M;UDr&W zpL<-^X;*jV@2A8+&W+%^CiTEJy9_-X9xKnODr|IQ1m9GNCx>mmH}r6Lgy<89SaZBj zHt&9NIht)^9L+Y@Y|(79haAl|*J#n~+&*X{nr*JhqH?cgP>zuslw;%u$(n6Yj*%NA zYqvqN#v3H}T&Brh+Y7RX^MdT%Oq0EpX|k8{g6z%hlzSdK<(|h*x#zJ{?s@E#dmcOG zp2tnH25l~D?&h-QzDd@gH^~~bxvaSh<(j5Yu4xM8nx;^$X$s|>Uz}BklxO z3tTU7E8sfuv%C1&UHn`pey$TgyNjQXNk2R*Ywc%ct^Jtv+hfvS&&pc+Gs$g*8)dJr z9?177h@K3lz-~+4<&!<7jk2e-QTl`MLY9-grH#@rJ>;H7GT2}GwZG`;Fa6qI zB^ZZa1Xl}OFK{bhBx=T2M4m;DM9sL0$TR4Xs2PtDd5=0z?8p;4^2Clju_I6H$P+uJ ziyZ{n4uWh4LAHY++fgce^QE#kUn+a^rLs3)Dtq&#vNyk6#`n82zI|x+Qs0&FzFfw; z56xccavA^c%J`3zn0urT%ATwbjlKtEZ#Gh5?wR_~=!?i+#)Gmqze4;bSco_i>?3d@ z;NN7gvYo&WWt?3jSCjF+{rZS1x&1E_qie z{Z%RbRVn>ZDg99?@voHlS4zAqCEhp58ulicziyKG>n7Q=x=H4-n`9olN#?PeWFC7^ z?0-<~&yYQ=4B5lVkUgvn*~7|^J**7b!^)67tPI)1dRoT&Vj1s?Wqdy^U| z&l3Mq;!vc?@JYus^VW{o?p%&c+8$r^W@tZ{QCj=2)YT!~|@#4%Umm@9G2l{n@~99Kyk z(yx#zKDkTQCwIyEWUZ`Eie%kdB%)_DC4S7 z>?;)e3dO!cv9D0bqWqcBbC6{ZWmpFrQAcw_ok=eCZ41b3EB#AMm5T zBi_K=RXJ@p48ji7?<;I8a)5g~cc7hk%3v9f0vpR`a~e0{dhlp067#~0hcG|(B(pd4 zV0+q*o=>17$fGokbuy^!<8#V5f_nUV<0J5YmyEW(C#dmA27|sQ?5Au)Xb#HdZp+8$b4B!=C7gHdcv^D;b_eHva2)ZWDi>XNZ``QzT#i ze}j7%XNaMm6BP#668`>|uH|%%CVQAU)h6G)eNd&#o~B1P`$_+7eegjK}^8Yhpta;*(hkve(+D{6D<5BAs27TI_dgZZUT>2dP zv>b$CG^cJK`$NaRLVPX(hiz9_xv#~8vf}&NH!7P9da>U}zk+?jF=~L0ef8&`(XM~) z(sP`Sbv*~_7*@KDeWfRx1C;+C(`WDZYgzj#g>u1RO*OWE38hgdnZ;iG3uXK%r zp+lFg+ux^Be$}t~RKLMTwW;;VWdD;kY1?}n-+kq8NT2^t#=oBZ zzY+^w<0_1&G?zUzfq{LD;QnF!zh=MiU$ZZWxcK{qiPzUI{S&$VrVCb*+nYT>SH6qv zwGCz%vL7h)l?<^L=gL>@fu3mpzi)qSAMg5k-mQlc?b2$>CD4_%R zTspeb(U^`19X3xX;fK@FL+XRP)2V(k9nhunbErIj7VVbhJ|+9r8H92V27Itd9;_Ok`nen0$S7m4|G7^2z9s$AS2x z?XdRiql0G08F2{HgSZ?H{!&bDI$eL82`_2_qd&bDc= zAMpv+p&t5>Q}Y9K)YnG`Ek=jtTbO)(bmTZ>%jnSl4*Foz&>noS>t++K=LwuA%jr;E zs^6|t9d@0qqlDz4M|FTdMhD^psP%{q@L)aq)t=XtA9~P^!Wfm623^T$;7=wKR*&|f ztBMZf6XF%4L)$`rfDTwjM=2ffp*}izZ65Rye6;H{)-kGw{xDjw9`?gN$OdVu5A+~S z<&xEh$*4Y!wQZm33!|xAjO@S|4YsNDFq-NGPkr<-8e$B2+fMXpuuj{DUCC$~k7RW9 zJ4i<^p$>H04%A`352JxM8BNDVm>g)xSL9U~9d&w63fcoa84Yra?HjdW{?U=``WdJ^&5%==b_)7`xDI%OR$ygFM!@HeF+$jIQl!+d+Ay!>%ALCT$@` zcAJpVxdm}W8S{zFqjqWR!+4O77$?xD{(>L2BDbN_ra@;i8u-vpumSP4^})t48g!w( zFdFJLA2COutU4hFe*nwqD5b-u+p?e?P6yTxHcyxi)Y&}H1KW{f=pXox{0QTLJ$vFy zrUQDD(ezvrBObJ2x2?2bJ?uu`fgYr(jGljNeJU4}(fTkM)dwGv$%WBWE=F>CuC;AZ zdKgXZ0Z)DOFq-OxtvbSlMd*!>oLBe>kK*?(}BG#o7b*KyD>T-0|&wmf*y zZWs-^lhNQO+6>bLosbRERbMhX>XXqRn~a9~7#(O2Xpn<{phGT9wm!PH zn@l#DUgQk&5%QRmZF^CNJ_AIq+BEo*jHYt-*a?$OMu&Vd8rn@pgIqFO!|H?lK^tuu zn}&Kjmthm=Hc!~zmW~t1qc6kcP?wB`yn(FUPS6(6!g!!FjHc~{(V*w75Ph06dhWOF z0nN5weMUXzq%c}ARw{$`k#{jVO6Y*BO+!4iJ*|g7VfAPOc@yMUyozYBPi<6vN{n^r}4OBHK>8U5&Ns);w05;Vbmp^cdkfrh{~~P1{yE#0@qC>$Ux0J;uMDlkD~} zAK-jp*Fm>E?%{(?M;rCgRbG9EPsw!D#{;{9a)<}&)IaovZ5!zDQ}foQsa@#fpq%;? zMpHRJ^#%N4x`X~Cwd@Ko1C#)WIm{VvaxCe%t)0 zN385RoqNLS!LM=B{LwhUPP84=Wy^%o(SOJp@L>+DPd-S84UiAYXdU_oW#ppGgR-u- z)&5`};NGDvqjo}!TxA>Z7B7 zZF-Dw9aHc@?bd#`>tHK*tLU)n;agZe+6k)%e@tkgqknCEkc-g)S{NO6AWpCY@xTGx z)}cHxs>j?{ACKy>W==Z<_|)$!N$M$mslN z%P9>$L4OzxW4=B*+76?K`GkJZSOxn>>tP4_IYx)gk9NZ9VIN{`^MmL2EcDv-Dj%#@TWwox zIeR?W^@oyv=tTSI59AMGgfi^H5u*ci9EEgXjAHJ#+tPa244vQ^LdRe_j-g{99is$4 zLGTFzhY}n>2W0xuF`5pogAT}o1|HClr312K=;%uacp#&Ed(&HJaNpn$fMWefLAVQ_DvSxulwP^;OigG@H@J z#;*3@pTjl#L7uRAjAgQ&T(LkaNS-UsmI~O)6^pcjtmTSdNCoWWinvyg#awY7SL`pX zu-PlMire9;3#F=@6?4^PT&3psB!jPz8U(g|St-^0N^01^k{(oZrPg>nzmXa?k$JA+ zn#@Cc!bT{5f-BNaX-nm8C{ynv3y+`!8HjREtNb&oj4R*nbUD2)o{@Qf-Yvb_O#?^k?U(nTFrK`Qb%jmHE1;5IxKPs=d$^*CM;jfLu zUmJ(NHV%Jnye5FdUz-kpZM;5zG?&3&LWkl(U&DL>ullC4z*QE0Y8gIi8UAUx+A6~@ zt%pxqhCf<{FB)f*)h?7_1NhVj;5c*~s@w>wQ#q8uqjHL)4stpc6^9=vE3RWv@#+8_ zKH2>6%f{iGjjJDOtKw=eaLr})6F79JpD3&R2%)Jwa9dt+$f&=zKKN_nIu@0`IzWfN zHb4BearkTF>W|v1xY`RGxvBl5xVAq+^r^h!Di7S2SGsVC0IzWfN zw!GRGX0P^_O;f!iM32%G2VKXRO;b6|Pxu1cwO;cQ_0?8A>{TAkMev|sv>rZa{7^={ zwyiko)E|`5r_eKk4wXe2G?i5xb?Ot!DyzOIuKp;lJ}F);`W08-6j%QgS05EuU({aU zpsBrztG$Y={0M1Z<$>GsimSZhDi42AR(x^**RiJb>Hr=7+VVQqlpp@ubl9)Cs(oks zs&=ZM+Ml)zd{7ybRR(2kSN(##`h>FjgL1XSuYRCjeLz|5M;SJuEp1zIZC`QNpuT|y z+aW)K4qIMv)CF_V##LT(Q*rnOS;aLs6|WA^YXZ3Drt)iUDh_|(i|sFPwO8r3zbLEx zh=9D}DzCW8E3Wd|hl;~rTfg?D(yIgXngFi-s{Gowio+ky*sJ^~D?iG% zPs$H}vAx8)UAdBs&;ah2Dc zR2=?7R&mWq#j68!_-pfPPAb3Vq~fr@gbv$REvt>-QGVE~{3zRgDL?9!AO2_=zGxYK zXt~-d!+x!Y?OKN2T2`C2ZN;^H#lf$>z~;m0uya!7VK3+^uei!9uJW3bio-9+E3P@I zcy)jdA8mfkN#)m^R2=@mR<&1gwO4VqS8srY2kr?}>%;?)5<{6+gp*PK*b zb5e2GZ~LltqF!x8S@~hF@}sQ$C@Vk8$`60E3}3ViKeSwJm0`cu!*(shZY{%}5<0YP z#kGCK!Efi}5ro@0sq(NF`cz(Vl~-KlH76B^UyxT^b5il@03ANs{PP32=A_EQAM~l( ztGL>$xZ10@%ENwJUU8LIT;&y4dCf`1CyPGCH76CX4$$E*+E@Dg0IoTybl7kEs&=AY zZA4l5VXyL|to$e|Kg!Avf3yr=v6PjSsj#j68!%}J%hU)ZDgf&dQtZC}++)T@mst32#gew39T zW#va%`QeY2;ft2xhnB0YGVIrS*skRTRvGq`(4lQBuI(!hSvx1OCt~NM%EMmhQ+dTz zUU8MzoKzfsL0)mqNyV!Jbj?Yn!%tftzS=naK_9BUimSbftG$Y={t*Fr#Z_K$l~-Kl zH76CHEcz7JoK(CzK-Zj9I{bw{io;(UhyAv%YA5Q|MwC?^_9{Qh%8#=0qpbY!N6YX< z%kV?X)m9nyYdvh&GVIne>cKaQ4&)ec+}WNjICyP*rr@}vJr6t?k@xwQUTSLmo<=G3 zdpmsxDK);G%kS~;HvavPe?R5ljm&d1eZ49*ejNS(+tm0M{JV<&=VxmCXY`fO)c8C6 zyNv#mL2A4+OZ^eQQQ$wa{Oc@#4oh}m$>;fZCQG(p$%pv&6iAMNB>7Fhxh(St|4w9? z{aEI9{vF0LJNfrF-16nz-dvXb6PIu0@(HZrEB?Kb_4Hy5@AB^o)^G@G*o5DM&^85) ze&6QbWh~j5CI863vstngOFqiKF-V>SnWI=HpJo2Qzmr*}G0WV|zZER=9sgd(E&rPB zJ&R@k%;h_{Je)QBjeoCZJx8;K_xX1vYdDlOyo}#=uwXxy+{(Y_v1B)vtmEH#EZLeR z*YocbNS+GGzAV#*WuD^S(^=*KmbsUIPh^=N_;(Grd^OvW^G=ik+=XCQ0%lz)H8ddgYD8~E*t zwhv&*kNNkPELqNyZ}9IgSh77!KF7Z^AUPG1^yCQrc3_zo`F9q}v}Bow`F8@#q;s3M z@$Zdn@3}1d7MIs?c^qr_iGP2~dIqtEzw+U@HT!AMcX+n`8oey!IC{$atr@1 zWyww~xsiXXAvq0_^n?rjc4nDB@$Vd#DPWn$`L~i~GP%vW`1f~g?>qeaAZr-UvMDV4 zJN`YMWq0uJuUNy8Ec+MymZH^`EV+Y!uVndNEcq_~u3*VSSaK8p&V}SmNYac=zuj2o zW&T~jG6%BEll*%c%Vcqzmofhl%(;bsmok4R=G@4?)y$vA{Ey(5OCPb1Pq6%HESbfU z_wer+mi(T7SF`*;NcDzwZCU0A{{1aW4q}R-43^1e8}G+2bHB^K53~FPmc)OaPL1Ejze8E_YyQ28<&T174{#K)%ufEj zh9%m@5?0m~f5GOzIOS&*C!$EFwgeBMV?`TL4g=7iKWUFOE4k&R+};$HeT>Uja``CM(3gKd)Jzt^*5f0p@}e=p{i zS8#h(Ec*nPuSv;>d?-&`VYNm*$#;6N(gTjwEAIR#UKYS@8f0-OFJx^TvNj$pgWr}7 z;!1-YbSVx#8@J2g#ZH6GYvXnqyto3id2QS-gBL4vo7cweGI);&@Y=Xt25-**uZ`Pf z@X~74vBAc$N5gqiO1yg&`aV#Ap={SXs)9I+813BA_4y=>u ztN5wqbR10w#>8kkCem>R9ms#oY3=AJrlThv{prALHI9zSbeu^?CLOKl_)o{>|GNMG z>G=P<+y77Z_y5}e&(1ghr{kXyx$jXtv4242jG2WUQo9v)*qw%Lq6fIPiC3FObq{e} zGrz9G?(|fuf0*mDW0NP>6n01<6;K0#$3p~A|B_KYT>Z5^1@XmaJO zni6WalaJy>g|0qYMrbjk&8D15320|esn*YS>yI$?v(L2ZkrTbRK7Hnyvk2+UNTai= zrc9qqXdgqHKXnQr{S>JpWPm|xrpzPc7)JIZWIADk8EZjl+PDKc@N^1xV{#wKHiT)d z6KK2Bm@ge~$qWm~*I4o+1M*6PJe65~bU=QxB|kPGuQbS0ndMIo$WOB5PYuW`4f0fG z`55!0SJg}+XC^a}JAHBq1tWETdiAG63cd2vzDGF`PjiS(JR-lBGR+}oc|?|+;Sdk- zh%7nFAvSf1H4d?vM`X409AdUdWVL5G#2k;vl8YRo?eZ z1>6lRcJbvc?kXe z7l+=$p(Fg;9D1%pM-P19&|5lmB-_VKr#Y}RFmBNJXH0CV#6Y08yHr2Y?DdzfVn5Wd zYNt!|Lk*X{b%}ncA-T&X`k{usKe|Le)KD9F9BUVN>W&=lhBSxhyTZgq4$=37{cP+I zeNUK}s7RVYbemXFbvc?eotl?4L$))X*d-7x zb4C4V!{Qz;(T_It{>&q~dBf9GFNf$m!^EQr;Us-gCE9yH7iGa7y3Dx&%JLV$I61bl!2atfO0{^34 z3#V%}uCze>NNigbCubHL=DxTx*R)Fw>D)&n&5=elNo z9bFA$musM@KXZ0qn_`IQ(9JC97^=J`sNROyD6Vhi?HUBFJ(20n&zwzifi0tx0win8 z=#(JI-!hsQAX!^Rl}u{s+2TfKDpPZ3&7MlzLAz7(u+HXfJ!EAS6SG|+2-BI6Lxj1O z7$|2lC4KgkIfTq+Bx~krx|N2Q&F9J{RB5^$b&I&JS*#`y$6pu)H4EmLq2B==6!$7k z0&?XFuhJwRSFYsBoEpl#K=NJ0l;$-^v;gUsOveZ1=l))zMBxd&!PEVg7$!;)OV7V);fZ|lMsB=5%hgz!9O@e-$!2fJ?RjAA9>BT z!6EuivgC6P(RY$1Uv!ARmrQ)gA^L8z+B%2myUCKTI7Hu1mVC`2`hId2yy*~qKRH5M z9HQ?hOKx?DzMm}lo za$&*rH;3-7xR6ZWIdpfyg^hvlnND*9Ut(WiJcvyA4^tyh(q*a$&!aUL_d}+S;9n$Ws*zCa;8(P zl3hX`;V`(t`PQeVjgzV!G{b2HGpua=(gURFV7>DQwlZk^Jq906F zJH#RS!DPu{4$%)LOO9kB1vANI)o7+uFq2(Yjdd8@U~=;(J1w}uMCzZ)^yW2l5-+Q& zn3Pj9C*iVcjtcqfZY(shCYsNrrZs_!gtJwbw<1@8#Y{PX1oRpSYLWJC`B|>awkn1Dc|)j~J1KA@_m3g!q3JJN-^9E2K;65B z*RK=h@0og1?q1dG;QCfIXGxp8Q(I9d?M}llZeD(ElUK?Bro7jmA%HZNaU}Ru)qE z+``%iseCEQ%L;4nr}AYeFDayuJ;pJL=aKY~?&mLUKbnpqeWCHl$Kg=C2Q|V@0d0^| z{ftvbs#CzpsSV`RQw7CO6cqo#^Qb?O$Xnx40X%xj_o$4_&x(wOSG7+Vhu~H1AB;or zN-TedEgwM2*m9r^vU~(-pb!jVgQ)cg5u{q<3|#;=r+4MUh<8v z-AGnycf4S%=k9pUSik4)sAH!ps1bGwXoH-Jkp}W*9Q#5A;N;ZnPv#W=*>@n_?Z)g5oJ<&~t2EeF~l%V(1YGPsHjrUG!X{5`V#-Gbu3 z6cleMD1OT`zJ{np>+J4$*EhcQFJz^5#};EfcgI`C`aO5Y`|Q*lYJ{Bv+90Rmq=9@{ zz`jrcI63thIrT|F@ka&4A9x-uArg6Ob;l>ZM|O97WE|q|_`o=1b;svy`BGBGmIG~& z<(H5KGI#|WOaF3U zTB>&)`ObI5?t*Xj&5!TdkLyS~`vJ5;e%wYH$ow^IJ{5qIA8FBJic_M+y9^{leH$Mv4kJm^$`vJ5;e!NE-$o#k1d@2AZKiZNX2S#FMtha68TKO)Ye_EC4X=-@{|1$o*#&<{gx zYbw(Mjc2)1Y6{9ehO!P(irkK@NGX2HsO`uA&^{qrZTl#3nsr+{j?t%7%P|7lpcws) zG?4o31UPSjQ;fP%jJigPJ9`28#_)Y>z;^`P0ChFKogblLcbFBRzY}NCp@9G$<_E}5 z6VbtEw9X;%*#%vPg~#W6qSYSi$ETR%^8?j#e1JA6KAEW;p9let4{(alkrbbv(c&J_ z;&LxUjScJm1~ehyhNvgGgw+Ug=qM{hS;Se?E9%Z}NBJSD6+zCS9wyElqw$@&jb&km%s}^bLtmTj&}T9-nqZt3B3_&oLaI_EgL90otJW zl#m9BPZt6lAK(<93X0E&Xz{RU@d;jtN)2n70p$eT5RD+0G>67mAv&Bmi$+J?*?5c} zqFNE;92#cg%rQD4Bt|`;Y)p8Jjv!j?Xg@}yI7U6GmSY68K{4u28Yo7+2yl#mQ;bff z7>$n>pX3E-fZ-cxz%c~e0F5`kaSp|-03A!5MH2%7iunPub4YY>d`=39&micEg~w+w z(P}69@tMH!IgV;MK0q53pV6d&;xm*0#|JpYXBx%l^l0%^FFs=o--!l{CE&*Abn-_N zXoeM^al~0PJupwt@Z(b}f}B88O^^|w`qx-`W;+SmXM{)WWTMqh_ak-&M{GRRa>Rf( zC}LAd14V2i0gf1OidYRrtlA6LX@==^1F8tP;i|UMX`U6XX~bDHHxRCQez@#(5*>RV ztuvr}UU;;o6RmcxAFVkYtr=9y(E{3_Xe}TO6s>9k94+7!t#c?^i=)L0y?~u%_|7(9 zAptjFi>>@xY6WZ&aTYBJ%;8J@fYpj1=hwo0&9BAKzBD{yzaU!e5a8Yp7t65xmdr-+?T5nJJf>mtK+u>qG5aKp92%C8HpaQ%`vi!KO+>q0+Vc7BPD zz0a>pq5Q(|XkA9M+6(+>t>kE3PPH5@pbd)F4Wxmhbrk`Q7I2EzDvH+S(c(+JfUP!s zYYe!NfE%#Ot^B&u3fOOnv*_1>`Ta^iV6`I1`E}{O=GRToer0&XZYEmoul%hNR=Cy?XVDFTaIN;k zW#^aZ*!%ptAIevUN9zHi)!yJo>w1pXgH+4W0@|Qxy-XS?S}zdbXaT2aJw(xZAX>aG zT6}M`c&!(3_4{($d$?K;UZY^vWY0mP>IS}NY%p~S zaI*Yuvi!|x@$1pz&7S4CL~_&VP2cj`*U3cc5uQso`=%$Z1tST2xm(zmmZYA20oov6 z3P}UGP{1xw0XX@xjeOY}Eq=#yq%GCEj%@WEvAf`%ee>fz_M;tXXFq^8$d5xw1DRjM z=2HPU`SBU~@kzA!qiFF5o-2nD$<3xud{=5evijtMee>mW_N6FfIGVJxA3z)A#|fl?%pb_+Qvo>n zv5WlpE?WFew0NiI%22~P%z)tp-1F~urdN2+=SS=OJAycieu%o6`J*3&S`p+S_KhEg z+MQGm?i-GTvLD0Gw-rRI{lP!qe$O!)MYS9wpbd)A1kymE8B2iAx4pJ@1E223L01}LpHCOz5|qf5!m*8aw7C2J*~YX0-P9RU5U2TT`i);{&uo@tI8;NYOL`93S8mpB5CKoYuw7S{EPS zg{a1`&M{yv0XIZBIIA{D^$+_pfj}I6kVK&A_`EYj!kkXV*xZ3noc?opiBsm zokPA2!KY^oK4;NZCLW)&A@kB9KGlNHIp7LDBopEDFIWIR7oiY*NCTg>fX|v0$_enf zLhD_ri>pvX@mUk`m;_Q5K37B2>6bUhREUq~HGyf_%;y?fSMi8l3z^q1 zM69nMb{)8a7|BG4-2n?g>?Ra~7-=9j5QwcCz;&lqx=R;#qlm(_u9Z%MEx7K1rZXrH zuE8N(b~^bsmLIKqX?$=zTK7Tb4GPg(Ptdv_TtSOuBD7|}0?>L0g`h>D1@Vzl}q{Jinpj*U*;c*ORoqaXeyALFUzmh;1Z@ zJq@lPMlum%ufqZmdl7{oMjD812E-ZyxZco8Z|dSL6j8Vuto#~j!SyyYoh|a<8X3Z6 z=a+9|`Sa@?8Xp;t*1M2-TZCwBE@-_6uAoIS5n8=V1+5Acf);6@bw1EKw?ds=p{7=- zDHUpRfSdyb=fVnST!r2;rTKE$xgi4H*?y*RD>&7MkvsD#6}L{j4y%ZXHQr>fujg)Y zZh6d`Z`Q7Gz|HkHr1{nATIkigu!1B9swm6PB|c~P#zjT?8`ld2mA+6GR7fU5WhgA5 z*ZwF371BWE8lZAjg}S0bU0$K4Rj5lU)I|X>8$idouEIIi2gV^VS6RSZVF7cw1Y4bUo&tLkcj9=O zGqVEuzrDotIM{Q`!4BehPU1Kab|nsyiQ)NDFgK5PUeRMDk9S@Q^YsNiEX~a6XueKCf8IL<`Kmc#zP>GZ zoC#&YgJdE+rojSWI2VQFD{0^{3wV57p+2lo?^mdI128Uw6j)i~`f-Saova^fAY@$M zw-WSSjf6F@pGqK?!>|NGGEpG6!U6)hTKq?aGy?e^fy}8;-&CltD%2Mh>hmC$+n^AQ zWlk82_YE91kBGjqg89M<=JSGJevn{phh+(dWTIfE!vbQsM`A#QG=iCrV1BDmb1T%( z73#+z5)V=YYK_WoRwQ$+NPZ3@;hkiOo^3xC#IZo)cm#GO4w8xDcn%ie{^R04Dx?v| z--u&zg<4dh76w5)4^cFT#bFS3YAuS5VPQcGOC*LDU{+!vnJ9+$U;(bbDz2kK8ZmUJ zY*6hgRhvpxTB(XF&GUlyA&q8LyUN&2f16594t?b-t(4opT>6T^$Nk@$Ass8({|7KE zfsjlT$hWWnL$kzxR7fL`?g(VnO4Y4Wtz4mhjj1ZBa4WFkENf(5`Z4~1O% zNCS^7@JLsxUX`k{QuPeL_#0ASWlgelh=iS=y)+PV>8rE`wx>qI8rT{MWC;vQAS4q7 z(xXfQ>5M`GA&o%RK_IG9^{rHHrRr0udIzzr4h3i3O6PQYU{x57*B8E;fpv8}GO&HZ zf$gosS+0StLVw=61p})&;lTD6JbFP{@F1B8kAAR#fvrIyc#sAjb-<&xQVp(D>s6`& z0T>EWU}X(#ZHR;mOw}*3S=lOAdrFLKPsdV$Z!Nw zU#W&ws$3Ao1`s)$Rz|lT^t4RJgK6m)@oY zqpCUKsBR)))I(XoAejh^Enxu|G@y`CB@Hk}0*uWo)rbIzt-uFFdOX+R+H>;|275e5 zgyZQimPd)JjW8gtl1$|4I9PzIqs2p1NW<09aCO^CwRNT1D)4p}h@2hrrsB4t!`{}` zxNY@+GH&D1rME-DxM@x}ZrckOdq7#hAejh^Ltp_I?2AIijWoa*2QYT7RAT}p4h0_& zS>v{I2!lOtV+zJ?7jgA47!X%UCUW&8Sb(bwg_!_~dv>YkNqe5Kkg@b+Y_dWtTZ zP;e%NFI?~G4;x>W-LEqIUf@({I{Q{)DW?M+zy#ed4Ak=*a z0MkWU`(j;Of+7mj5f)6xSTJ1*P3P#!=t}As3nsszz;u`e(;?P{`JfocrqS>*@sM2x znRj#u*#v>?a&QGQl8GR@2^Ij^)hGlq(tzv~Kz354Iw1h-X03ONE^b8;1?waor+iN^ z(E{r>Xga6n<cD{wsluE0ey5nQui0dT#8Lf|3|xc&{e9;j6JRjPX`)m;H% zpK9&Tbn!WgC}IyFDy|E7p_**aj}oXn@x|tvX*93s6My zdP0XPlkgb}uiv5RJe`NvGa+8~B=l_vT#s3BJsJboLfU;M9mLHS7Y}%NArW#z3|j4Zjl)S$D|1w?oL@63BXhE0B>)1X*ubK!#PJ z5XeXavQGioCza}>O7%g2m!nnt=weM2QM^9Up-P6$w(xSH>3p7t*X$54JHvb%0@p_t zTpz^1wHEEpj)$u+WZvf?T%QSC{lFEtNG5`-4i*5{x+nxL(tzt{!1ZIL`o2=lsZ`$t zhz-@+8|Wg3B8u3Lh{|NxuNGn(LerU>ch&zjM9lLWN``%}VHe2eSde`a1KBVd{xu%5 zjUe;phLHUtkkx}LkdaIT*;cRs$Qn=xWTXMvVnDX2QZ1}h3j(|vwd&To*ak%uuSGgk z$*?6BUfV*``8yAd{ zXk7pcKyTOQQN?R?{;W9L-XLkLGLbb1wE39(0c+FfS!j!&?61>HU)aat5kh} z+f1$Zq%NL95yfpd;xRYR%`DuWhNd&3D*7mGvk*7WZzyS3ufZp9qs*jyh6Xl^2jyAF zyb&QN4Fbw@;0h=t6M^z3EC7_3Q3xoc0m@bYWmJI3TUzODUA%)LipVG{leV!Cc^8__ z)_I6*6Cz?~l5Zmd$a`$RO*|m)L*{KA0@5ged;qQhLNXB`U%>(ZnT0|CAq_xw1|Vaq z)D8hAUu(T@bnz{UC?;d9EZN1vWDYc)aaGX=ce{j`cz#34k{x2Q=PnlXNhkkk|m4TexG(FW$+8JSJ_Q;(M zws~=7QdsxDNSG>~9}Q#TImtwxp9TwX_ylnn71HqhVt9UGl{&vlom-{O4xB$7(&)Hc z7&`BrZ;i{j;Shx5a(2j!85inBevfpC#5e_gN{l2E#W)QX5ZZYX8Y-j_<5h_9iYj$^ zm6{d=co{?p-Wr`N!T{~jxm<@L_wi|A-5;H+#q-NyOgtx<$n*PQ0S@0P4x>UEp5G47 zZ>>@{SE(DT)b&;B+Q9z@pb#CPTSNc7o8c&L#GE)chGXGfuNNP{-@7(s#|)9YNTgr( zyF)^J2>nTjBol@B3@jkB|43x0kVc3PA;br()csZJ-YRu>mAW$s@mVNDLwwK*@qR1B zd&5|~yTcIg4B0Uu7G&YW66g!)RRSfMDA0Fd0r9;m@u5N*fj)*nAFWc4RH^Afi0^6D z_jU0Bis+5uQ3QNC_dchmotf5+;X`OTPgF%OFEcH4{DyL?d_=<_89Y6#2aBtZXl!Qu zUE*WNyeGoD#N&d|C*TT3BokpY2NnR$Y!q^rAPtOO07lPMsb>O!zSDZ&>*5C#QGlNF zhnT;adD#N!M`$`Ptt$0K0MXxCb%`#D+T}y^4ni`E@((SDQqXihsES?$KMW!A z{DzW4Z-uycZ-n(Ahl*+J!+4BJAoD&5F?wGxDg{?CBAE!IuCM@%I-(GaNCTtU!059o zH7fw9o7P)J7ptO(=Fn$49@*`EWdXDrG@UQ=0QxEf$j%|(hUCz!7<{_Z)>rZP^nlF! zGQ{T#!Dn@F1s{@$@Nr=Q_@q$?KBR%qufXS*D)m#9`k_jF7ofD3*6yo|ekh_S{eq}W z8qK#*S{s_qyeizPX2>FLC|5f3LzFzfp`_7IAvE3()<*cdkRPN}e;S@2581kqdGkWZ zeiO(BfGd!ZOa$35SO8?}qY%hQ1F|K6?5`^IXO;RRz-uF|TCa?PVT}?x?lL=wc@nQN%j+3Nx&$h1kx} zbXM+#m4cOFT|>k?zoBGUM;I{=M%(uaAB?sQ`9X$_rQxpekd1@PTRDVmC4p=ga0N1w zi6A=w7692ECWEc;iaVA&mG}(w3q8qA%iRE2at@DeE;%iW!$p!L^w09Ni z<}8b)9uR$VHGP?kP9!LjiGt!0GB7k%VnKy8g1QSq-BGP>t5&xJ5nTikqSX;?!ieq& zBeDnbHXRV7@@~-qS;r>aEuLQtW8yiUL z0zo}itsbpbj|36j&xoem!|_-ckv$xb>VRZ89?=0=!!c7lf53Q7GLh#`!U7!j#9>rO z!}FKm`3u$RxoY)HwR$RW{wYYEEA8QUA#~n*4qlq!ct(3K!|{~%e%ZtEvIO-sI+5WZ znJB2&VF9r`FR`FP8bQ5-ziuf^`55cUK#qov2 z@guBD93&IP@dqrx{kh^kDx?v|_lRRowfd%7eHDbV2%_lZo)d=RePfNuS1pU>2Z`lR zn3q^cCW@sUeujz=QYhqRNE)%sMJzv8s~>|v+Jher)oMYtniqt^Lv5lnd|?=hx4;^cc`b|OPl=@`%u6gJ6UEXS z77#)&2>}(-h@~jqp#H8_i-SNM@S}nJ9R^~L$>Ns9kxH}sKCmuvkW3WEKv;mGzT!SA zq!CAZ#L+gb%F?PNZB|+9Y1Kix;1M^`b!pqQzLW4Zz;dp!`~#xbho;jp9lctVr^5xB z-%u`lWiWyTnq09-RU40)qyJ*kxYcqrmz5LcxI2x zKhnTx6=2jgtyT&EYS4Nkbg>zVC_r6xY*UJ6rk(BM6N8Z)tg}`;Mm#9Tb3=^Q6pZ!; zS1=-(2qXV6oC9G832s>r`6g4Ku1CW05y9OPJbPn z-~cI}a1+g;4H1&bq2U%pXAz=})6uK(@DL);ZzwsmfyP-ds*Ayh2i`ct<1yl~H{Qk} zM)iWxx!_6;kxYcq<*d^41V)>u)rbHf|Ii%kOq?h{o9oylhqkf+;;}i- zmU#ee6#``EkZ(iq84-ie)wH!$JU%=Y$J;W*XO!T>191c&l8NxS0~UbKjVJ^k(!gg& z;In;NZ5QCPtkZ9{M?5BhcDC@5({FalyH4*M;^X-ZC4sinAQPaauiwqPE^_?M&hd!J z@i#k#h>a1%?l*{$OoZ5@8nK5AVx)oC?m%qU051QGoX4~-kHCqh)2>!J?P4kBvv`8_2w4LbQ$+w7vyb&?1=#t@*G3w0=S%Xpsh5rvj~0 z((0rDumxK0cU>$*5e4iNE5A;&0Q&=)4&J7XJUKZn1kCdrN`9Tx()?OP>!-yd_9tZC zq!6)*g4kkk1u>F|5Nm@Uz5}r$`Pn@xq=DE}AT}j{tF2aQr;GL|qHs;I^6MN6t`5+2 z&d!7DoDeQMzkD0ZpI;qm{G52S$|3X44$(SG(CP%PphYqfT5G}rK&nO|`9&IN-2}95 zNUQ78>YB8|o=yL4$tD+4=gPGGP(6&@yUx!sd8qCKC=b<9HxJd9`exS65>!8QB0-T% z6jUuNAgJIhDbfh)E(CQ)THTgbw*(OlVMI6i5$T8OVMO+5-lhZMXnMEkfUL)ccZ=tB z#&eR1JRhMw-%uPz2&Ccpba?(yT0NLn_ovmpf%BU|8Xb;@Lg&2);U$+W9FF_7_xho_ z_FkUi77jl(~@~93=2IUbQmNh6d#q)76CZ3Z_g6DgP!>Evk=P$tX=hEt#w0bJ=oF_>| z)9Ja;bMG0rh!K%%=~JQWg=@jW1EOD)SPp`DiG^gMSdM`Ogm9RIfC_2E@)}}!C9Pfx z0y!4^XdthIf!IUvQp@6aUE(+n)+G*-iQ+gN7U2F#;yx;*5y$(82pc9N!?0uhQy^wE8><S2o?ZMa0C}=VDu|6`X#M?3IKXo>rK}MkK&2~^ox#7_UrR4fOxo;GcOOI z`5{1dn)o*4>iJU)KL4Su`SJKX3Yj-A#OF7`X9l=}56MLMyZ{TpXC?}{OOOUWMHxIp zPpidgwJ3n-MXmahE?!0vh3IdDWVY-jnef^3E6{X`Gtrq;k_n$Z`wbcvbUNh$)Hwvm&LQ81;L{fN^5@uW+UgvS&liw+ zokD!d1)nd$6?{l0!e=flAnxx_2tK5NPj}$6YDRSn@cC8i{iX{Z*cHWRRm5WwsHcU` zd}unWXQCIOo*_P--%t{$n+BNxE&V=kp7|`G^`7yF{SKM8dWcvLL2Mzof*8p}h!vL! zVvAu&5F-u5(mV!hjA`P_q0j;$%YRv$!Rkhw~y6BD~3fNj!eyw8x z#)Hv&6eiZ>a@O2JYqc|^VSX#Q-W9pxPlnTM2Pi)1t69|A&8L% zVuOI#zyPi_wUVogwNOOi8ffKLtp!(KXgcfX!Brc=W#^Y~WBK!ohrBtp@o4dgH*ftA zt-*p;a6TK!L}(ofyFhDi6oM9Mpmh?^Iw7Nu%cx^AYC=XG86d|as+?0Y&gL1tWg5Yk z!%heh@Q(8{ja$KEd>FYipOBHaBKaGTBf);23yEKr_kif5(5rV!CjVST%^AM2IUxFE zL1hAzC5K2RLWL(!0hQxX2r8t3$`qh7IipU?sEHZX6hOigseqWqVT%{1ac7qxgev?%cyfQ>Z~A; zYan$l$s5}X3SyC6{(08Wo)Zr3S<4*S{4@A&K&Rd%1w*Sj;m}?zh};NeL4;%?MDB+L z0Ko&NWN1kPk!yg+RT*_fMqQp!(*i^ufHXR^SA}qRS0Grk$G%+S!Lil9N0X7Ars1$g z_F9SKLD-czNG6J7CM+Nheb5vtq!Guhh~wsrx-p}!4}y3SqG%8|he6o+d1Gu0*B8Wa zo5b*xiGgII7~a$|JTI;z2GWS(A;j=tM%|xL_h!`H8Fgn6$y-oxre~ZT?2FHXVKCnP z@RiFbUVQG=(a3YCyTc5VF57k zyer8~(!gUT@OV6V zAiczYR7fL`ZxP7X8TDmG&CaOLGHO;veH?@%hckVbarX8j+KP9`ufvGEFX65k+u1rK z8Qagov7HrGKi0u5*D$XQ_q^{4hFNpMVV)!CtOI31hh!pjHiQL$vYvo~3TdD-AL#s+ zQFAlu=ZyL>qrMNIkwcii^>NvTxcnC4VvqD(4U3HQ&(=u)Xw|>hz*wWcK;q(QP7)W% zL~-#1B80=km?VAmi9}9uwm}tT)!!MlIHMM2)WRUHvCu?P=nR&)in1IqS@PL&{cXjy z*otM5RbN;TS4o!cj5BeOOcd9VIxZeYByo|(cy&Zv?X#+FR+VMV^Nph*ayn(B%ii{3 zP+r??n8anM`@izwwxTFXXvok!y32M{!hkj8oKm)6^xtagyU8vU|a@e z0fS^BFm8YajN6qcWZXytj5Pp8HmlMB5;uYmh^%qThA`OUmM$2#-s0*_Fd(jyOyueV zumD$Y6Aw`#4OiENtLtQy%BsFuH;9}B@&XJ?AS4q7!efOH$gAQ%Dx?v}rU+zs zR@G(Wl@FMkEtq#FKyk&6g--ut@`>t%1>2 zSv4vEh-U*q??+wygdz&iRysC$lD?e<&@a$*w#@@*yAU8dLwp;uoEQ~@&#$z#T|7R& zLFR26;+VV zb$p1IomIXKf$K;MuES&CT7!0vkB6%_WZrQhT*nGr4!8mr$wYAFU;%KgheF^Y4Y;&q`8RWfXvh1d4bbS}-qYg&kxongKWf$Mw=u5)AH+JSbb#ly8DWZtDA zT$c!3W55--NG5`7A6NifyPy!bNCU1L0oV0eb!}E%omE!`i1Ao3Xz!_BKbH)o@d^lk|e^ZbUAVb^Nd1+uFx$gYfm>|h$cB_6UvAoFexA-hQ+I}}`j zjASCn&VU7ga0&{6j5Hv-50KrHRd;389RXfEs0*rR>S8L2C|>vIP$k12wD39$n$81R zJoVN~hn=}}c+kSjZzveuWnpwj3`S?u*n{yHodcQoK#0-(g3-C)3PvOoVRQv7An=P& z2u7rV(PO~q(X4tTtELASU8z;C(#6#%q8L4DVKmdi=o)A`Ph{~GhlSBh3nRawVDyNE z(exOMuBEY=@fckPnfFA9(c^;A_23FdBokre!2&S47lmL%8W?>9j6TS!_p<7pta>Ye z=@G5XL&4DKQ4~>_K0s7v>dmrXngLDclWcSuKFfm1ZzxmmJ&m zA$uG$?~@R+j|H+Pz!k_yCW7o0SU~jpKr~cH1F~-c+1FY1Wme4&@Oo9NzNU-UQAF|j zT8AoA?|TccH=yZ!mxtH)Azt>y-M1ldeQCipI|i;dY4`hhxZZ-y`!0lQj==RcxB?f+ zL~wlp3qXmdrAda723(5(*TSq?kX7@t>esCLB>?S9-QX)-e2pRs+Cl_olI$-Fv~Qs4 zEY3zBp#2qs=J^dJ$rfnj1+{q=YQI|bUt$pamYw_+kKi20yu~4ce+q&;6HO2#nFzs! zumA*kc$pwb8VI(p!H<1wR9THGsZpsK^T_QFt-VMWf1-%O*S3a1>sN}(Yr>u4VrV)Y zYohR#*Tg=5^lb=wWi|55K(@*yRy~D&@Bl%!&1M7n7yBsZUmPpkK=NQTuVYQHf$UJj zpqGFv=#fl>UNh&8tqSzI)u@#N+?I9jSU1FD(yoVvo18n=y(ao>uSbZR=QotJTUmoo z;DU3FEr9SeG|3W@i2xY{3jl=2 zqX{6S0mxbaWX&4o1egrgdOUIr>a{4Mn5=1KiLx*m0!^o1P4r2k3Ni8ghLR;tOqSHq zfQkoYC}dv05R|?G$_C&HC?pes!b8dsCC^S1P)GxmfdFOQ0Fe<|iN}*ccXJd`MAo&k zWUz(E7SMDC)!>P%UOMf<<>g=t5x-$1HAb@0;CK{9LFNq#QCLq<;Av-q0?9-u><0^o zY&R5w0%@So2o$!gQ6p>A<~3?W0LT82It?{CrrjCSmR3w7{q*1$?VJ0+;4L5h>I2{L z84)sL4neifdEHu~<7s0O9mzz|9SaMHjwgaibfgj87(};2jT&8}whcl%4kCoDL)(*~ z?GT1$PwLS+2)R9M8`k}=Gj3Tb%0Cp;ftqjsxNyVR($ zf%8)!jgHIs(0Ok+c*%=9$7Ppr2*Pn08!}_YrQjDidr6FEp-+jCWTF_agaw3lv4n;S zX~cLCVmzQm?N_7r2?D$dA_Q-Z&H-V7_UP;vj)=EUSocTgVDbEF7!%J)Ci48>umFee z5{FSC4bLaQ^CN52;Wg^e!1IT+>chI2jv{&mITB8qJMXd96~u$4b4*P%C65h*_WXu& zO+7q})H^h+2Y2B|XzbYdE6aZ%^NtCxEJq7QkAf>0kxYcqbFcttoKD$j%DihRoR$WAJ&IwkE~n^9p3% z#1NlT1)o>J6?{l0!skO+06uS`5PV1jpL2oF*)?ivjhYfb^pRHmSQnq5h(dHWLNYmY zfd$blXgcTDL?_M#Aw-_vP;zK$h>JHRtOq&tDUDqakI`q4dFO{1ohKN54z6HCG7&~U z!2&S)28Ccm8W>#;jHcD7O9Fs?)_T9_VlIj(K+|+Ql0#Qo0R09{=ZYF!a`csDA71yb zv;guOO5$7+1Im0FxH2A;1(11HgrNLOK=~b90fl5DP};W_P>N6pD5L?(tpMfb8g*lh zy1qtT8$i=RYj@N|If^JWHzO*OJ9k*nbcUvLdrkDNa)$+tX~?_EjXu77r}uijO_Fon zLw3x4MSsnTEzw8}aaVSCM?8?-AoFeyfxJzCTm@VKl4K$v)3AW9d!P^?Ndw4#1IPzz z)O|JTo&d#+R?X_721OLb2mDBjW~QC#7K**0={%f=;`9(j{~{%~W@CdO-WP&+&+>!l zvbX8+Ag%?O_izZ}Ljq!7a0Nt?i9j3z3jnb{3IUNcKzs%uK2@V;)~Ls8)QkYfI;}la z7aO36;`kJTHQD&Qh2w_Mbe_w@@%a!(&opE<&I}Rr9uI+>5wc^l(OTu04gJRK^!a!= zhePH)7sC0hz_|&y0w>8taBd9?fO9hx0w-y}`6l3ey+*xSqh1cM+(xTztBdVWM6rC` zkC!?5j)mp+&~)C;!}6UFOFJix4d&#lA(St-6w000=R5IG?hKjtb_nHL0_9k61xk`F zh4Seg8dEzrrnV=9I|IH&JK}lVj%vY z%oWDWmC+WTm1vKPMC&RD5sz+ib*O3UTtl7W(J7Zr5=C}BEWoAfP)KB?5n1V&230)9 zJPEu3Os{y18N%^3wQUet$T&Vj2F%=O%-j@hk@h1i6Rn#eL}a?jEup54OzYfA9Y#hn zQDk?(0$jQsg+xXgk+nx;ZG*_}1k-C9L{?v85j$rpEo!_iIzCfbp}p-O5#0qd;w{NU z-rfrf@b(^Y5*5<$wiCSV79ys(Sm`=qQultx= zC;gc2$JIyC0N!}H5_=0muL6=Y@#F@Vxjwf}`YGLi%A~WX_)EH|UOwx3io zsxj4vS)q^-rz0aKjZvqLQKyViCz+&J+nY3o-*64&M^Sa{IgD`~w&`!VGnw3V;jD-U z!rB>Qypxbgllbe@N##Z9o;_vd?42fG0O(fo);&lZa08z99uGz*m5;)uuNMAJ9TVv>h-s?CbioS5ROX`f z=+eg25Oj0)m}nR^2D`JRp9`DmC)*r$*$}%j7p>XP22oHOQ#lMC&}vL=C?Ij25d|qk zOD6=;^5FnTQ#1L14Pyg;Nh|5Gkz^{XNiucw#?)|*;pPD73S{c#W7M=U>XI?)B9p0G zc$Y^q^?F7#l5Hfld{?d{cS{5-;zn4zYK(VLT&7+nXy4Eb+RMsR^n*-AYi8=!=;oR+ z-ZU#+gXFnJy18+MxJorfq|@n9@=8CI>N@Yl9=I70pGhY2 z`8VxzaC;^VpNGKb^>LA$O_eC6F;d?ndZUk4E1BQfGA4n-mOl7_G4WAXRp$EtQ?4ZcT#@3kAt-{jf& zwjHbSy_ooR7;Es=ig0*_jc=#1>}momiO(dL;j?T(iaL+$TCziVQJ2Qzr?Ah@G^WyY zH3K)#gqvp=AG6*WV<&GsVd&XoDXwwP87p`;aT`|;K~ddQI*S*LW+#MCHEWeEnlSNVeJQNeod)xLncDyzjH_ZnZoU6v&n>|W~&xYM!(>$}(a0&c77qb?%M6;PI$nsC$zycp@s;z`fZQ%!~?h?k&FH$*5pM_f}ujQNhOUomx<4!7<#uOEcS8%uPm@)Sbl%l6B4=y8-44 z2u}4>&hN80=l4;X^KG`x`F5I~L$5hA;hra9CfN%l%*1+;gqch)kuVeJWfEr6yh6fE zlvhcZ$?+NqGa+6lVI~1LzB!Zl-0PNvO|Am?Zj~gh`y)Buuh!Tbx6J zjA~46;>w7P&{sZdFgKGcEU$M7uCROJ`6n--d*TZF6t1u{%@uYpZ|2y^^_OPk+2_z_ z1-j47Na^C^(-3aes_dW35kMIt0KLGE;2=7q$Bk(?s@D6i70dH1> zcewj0c%MahN4TGZH#@>R()|LwFC)C8+^@jMXaegodO5#G_5jn5Fsy_{z;8|#lE z%3OWtfUBOC0F#yC91vusBnQ}7Da`>ZR?2b!h?O=upu$Sq9H3yOT@LZH(mscvS?Q2N zq^xwzAv{*fbBKwRPB{d^O6MHBXQfLHE+YYtcE!nKB;7dh3DWKO#?*04x8sp+-y_}T zm~=bQo8zY&Zri&{%PQ!9_9BZe=_)IMEUEIKLz|Vqx=En zPX+(1D1RXNXM=xEl)oPN=Z=eB9W+FPAVP*8DR>cI=csYaa%!U}$^ljx@f>hur8o!R zSSiT?DOO5zfQFT_9I#-eO%B1c(l&=^S!tI;c&xO~As$vb$YnBOvqoxOY$NI+bH>l$c# zZ;64`Br)vQnA(@l?S~jfA%-nX0Q);zjrX<~k2OB`R`g|J4O}_E+lo9bSwj=D`3g5y zThglo#Vb~mc-1rwU}Ll{MIn=qG(6k}9yS^eoA~7zl=#({*Qn9nfql#OV$$pih@8gp zzLZb6eP~Mzv`tr1Wjjj+W79tznI?WI=55EZVjeYpg1dWl?T*q7zao=vuAz-?Yv@N_ z4{~#)-Qku~o;@{P3k^I?(CuW;S>kG6gRh;oT{c$v8>H`dYfSatj=(&6YpSS0J%Ud^ z{~V75M-N`7JM@G9{t|fx_yDPo43H+4F+_3Qt|i^hlx`mnyY1_dK(|(hPwEc)Nr#$9 z&|!b+@OkO*S$wLe@!_U4LuU@!IaW@v7tI@wTuhZ1s(gE}M%Bwuz5@je<(A@(CK9-V2XS!ceb~Z@-}v;0a$AS^X?NPw9m;^0 zU{+!%9C|ac#&_ofD8QZV#2rl}aA!wx=VREyANa(l@6H&H1T!nIlng8B*mEhv_K9|E zCvi*@2^`x^9Q#Zhn-w~?J8meAsr@~&;NFmL*%_Tm>s`y|q+Q|Smg39?De3Ru4i5tM zU--P0gje^qwD^*rfhe^aY>#wBjaM>LemN#%W1)0 zuvpezGVT(5qG10c3^%Cn@#!bUNe+i&20ANh>c||W3{+=5NyxAJ2`oT#vN)iL1cTpn zn%n>}SaV?ye;O2@z7tKSLxejq?~HPbybcv-9u(wOrM>G!@7M^_MW&38xxCcjQ5nwG zE zu|lOBkayOXDM^SweP{TzPMpziL<3}2QMJu(;&wONe*MMrV{0J z)tX9WU@<5@Y7%EOBZ)KmEeTAgcH&GM%NagKLMQUZLPzlBhT~C#16gcpa~7Grt>Wy256I zS_z-V8NPVntOABdF2>E2a(nE+&!+A1uVaasy^DhuY=#!1GZ6nedKRZxw-tUc^Z!Cy zqhv}pFYQn)R=VJyWOh>u|4Pa0(LpD4H*`igmcWGMkY*%-qXd>Dp}WH-PNc`Dfuk)% z&gx)zXv*Z?fFp(T)+J!4b*d>eKv z;=^XdhyObIJI$sJXcZ_@gShdZU{~v7*8^S=yK)qQon|D#Ze^Gd?5be1K~><>VAmBQ z!c?7q>!A|zL@o$;<&ZbmUcN`&j7OT0#G~%Uql|b|ZF$tg_h?xD)tyQ}OD^udM_J#a z)s07*k;J23#-rZiQH|vhzfLAb>3oc+;`lA)66`u|Y1e%cq0zPsR2nNGugIW)tCVD=CLnlLYQHR1A3bA>q?uK%Y+Lrf2 z^HpY+_n&fleLemc)vXU*n%e+{_^cU8eBKBq#ODoRvq5cuPvdjF?qm~PY>L7e4zc!m zG9K-D)JDFWn@U5z$`g3yY}1YE@xQ2U7OPCO!8(_0RZGunZ^H#c( zZFI3M3TGt52IraO9<>4D0Q~1wf4h8@8-Vk~8l4*>pi7@eqY$4pBZ<#D!-V*}6>K)B zQTQ}IkJX**s*BxFINL#NaDJlPqc%VsfdBM)_k5N4z}c*}8=*^|$Dy;D;*|pN(Q)E*AU+1- zz-hRfD%QB|f;foVu_$C%H6sablVC!Ibr0BVP`l$(?TQZr-f47!40P{Nic(fCcn;;0 zWu{W9z1tI7^zL-yon|EQZmRKaKiF(g``}aUg%9K1S&%#QT)&~ygIjAV!AaiPJnH)O zQHChdUhWSOy*%4^sToPUyuf&Q5NzUi-uN^QUI>v#2KFX0hqH!iXDa$D1iX}9cd+l$ zMaCt~NaE5or z690Tl+;YpBgfzCOC!=goC*spMdb{rO4iwI*;PZ-?9>85YuPt|yJrQh=GIGuB@oq>w z8UnHmuqazQ8Im)56H0BiT6z;|Mz2l75qcbXuz%;Tr0b*Hm|J4rsJE=shR zS_vPur%@tt-H%Gdjq2JnD6A6|SL*2M0k9;Fff$0+V0F1AZf^<80w@y$X|fha2y8GoW=bNS}k#pgzT?KS%>S5|iuy zmDMkGdOFp zBtI2MYTchj@=Jkah&xv#zZOX9+}}hpuRt=?oiCCF1(FTi-$k;pK$3I+5Xqtf$%gKq zB3WD@8Rq^alD`Wi8@WqFQiORC#jPI8?=L9B7fudGfM11c{81^&3Eq-OIRTi};+!DL zYDrEYWVJLWn6X-x6OdSKlM_@}ZJQGqSZ$Y+xLIwVlR#PRkdw$*?U<8LSS`$+KT`3uOm)vb6V`^I> zxE(<60_Pf3Cw%&#kM>CTpbx_jY54GBC9u#yzsIeKL_P1)n3C6K@PdTXO?qBA?0Hv@ zgx_;pzvoqS&$~&?nn={M{XScF>3P+#=e<1==y_;Ql!Rs+VFu#uNg4ef zTC$&8Wh8io(w6M+_A-*TQON;rwUM-oN)B|>M$$eiImpcz3D+6SX5WK@-K>%D2Tzvd z5Vyui%A=A)k(sMghF3%!M$62USQ%nbE{Haj3&JbT1@V;Rf&fZ$fyZUJz{NJXz^Ar3 zaRRA(sOxumm<*$KKhZEAiSN`nK1U*f9C+WL*1)Hqx<@%2S^Sm_NHkS)txKVwP$mBL z!+%IGX!U^@#wLhYnn>i;v5l!?=+&|Csvm6PZ!+Rjt%(ocwc|VzT&&@Ls-s7_?^vp& zeIUdTq&k%A1-OC=Y#uMpX(EwxO-*=y+?YCr4oV$P4uI_j)gPZ~ZG8AnHcf=4vmO{8 zx&G3!T%O;iI+~T)Bq|NcQ^M65>cavheh26bwv{4c|9ikG)T)IRbFW%fkNO*eUK~6+ z;$zgNy+>o9I#YF6M|`)BU)A9Wy&Ix6_2_B{(;wL zQ*S8s{N9?;JC}MJKu_=A*}@nrZZAB%Nu+nr=Rp;KuTN#TR3t9d4Fg%^=J@H0ux#uC z8zWs2dDN$$bQ)#0c0=l70M9pFOQPv*U504+5iz|zx`zJc;iWiICtbN>L{^&@!Hl~R zZJLH2vjL6Mwe@66wp?sFGZu|kEG=NaPmEHm@ zY7|Tl%OIu)J%ai8>2W)qq9NFk-mk~acdOJA1I8>1$E zw+&nTMqF~9H1cL!_|>4c#-~Xc{s0AvGj#Dd3TF(&9(DYf+sZu#m&%D<({!dSHiN)-TIWiTKk! zXv1HI~0(D?&|^CWh&_<`fK_<`e(U2!R(8fJ{#s;E6>(nCD; z`l0M7ynlNwUu_=bu^|bMhM^n;n3C5%Y_w!iQ(e0Viil2r49;!e&%KN47Lw=slG^1k zYPZ9$sRbo5($cF7Q5uF{T{9DgAq$qk6CBcmPxU80e1JCcNKBb@7tY^4wOdoV1S5lg zeeg+GA)Ahmz%JWKfpR#=SXcworgeRfY9?|&Az%&BZXOsA?UhW2Qzm_!1y1}k41kYspzt5y`;zR>g}pn- zKe8)eU{~O;;}Q^qOsr)lvg7`u;1MXe>tDFHi1rx4Xdu*5gLG)4qI#_?v>wQy`Mr4+ z;adB2ej&7Ft9CdIhZl&$xI@;@=2PaaTD8M#6gu44svTYv4$m`d5ZQihjkSKMTuOo~ z$F?gFf}U^o9N7*}^`(Qx)M&XR%Y`e+C3(lj)DFC|;niu!+W~*x6K<=v{3yeRe^uVe zDF+d~fKklrw7!7(8%rEFHx^H{@LL~`E&Nqr)6;GFYmoK8!QUO>g;QQs|AW^}b~R&T|A7{IT9@JpYF`I0i2A2OIa5q@zq{7k!e{WSTtgQPF9 zMqu`GRszFWg(oIGgF_Qu#nqeBABU%4@g8*;ck5?(McCU}IkpWBVQIF_K2F!zHpNS6 zv#--FwvD_!)QoTYJFB2g1Si2S!V%;uB+R@Yg7|ma1DsWtZAEZinw5i`+qT!a@HcaT z01!ds!k@iI)vgb+$a!S@8T_uUDb+2i@l1_ARI1w7i&!Eo`Ib1C2Ro}lqQAevV9nsI z^w4M*R#S8_bam*nMBow{KZ zyS~y1LGK&sRwwFK{EEnK<%-yqw)k18>HTE4UN@7armk@p&44PT<3QsKX)H068E7z~x2ToFLC?mz==BYIRP0;;$EJ!S&nAEA}3T zo#S0QoGx-enpTS&unVqZd9uN5I0Cf;Y=+VMgyLKwQTz%3N6%faDh+_+6STJwfuzi>0nn8|Ye8 z!&*Rc6)PID;JB5>D$pRh{?y-URFThZ1>lsoqWBes(+k|_^3+-*V|gmiUrY=68D6@e zh2>9v3w~b_S@-K5&7z(y{Kq?pQX8wT<~5BVyr6$NvdB=8JB55kJ~o z$NX9e9d9ii>kjOWWzSl>O@7CSSa{O$V@vB;zOQ03=0p92bnJ>5S9hmEil0B96}a8}{Fz;#+iK?z4nL@uuZo+#Xzfm?@p8aLV(lU%?`__OgUS2j74U_T=AER_4lT8nQVgOI_JWgZu&H()PqrS#lRrPm4fURs?;#O77e6O-(#bSxMRiyAxrFG07{-L61BDS(| zil09`>?rDX^Yf>yK)02J7`H2F)7qVmn?KF$N_hNKbg)`905S8YJuJ44`O{&=V*BSW z&hhi7V}aYv&!0{Ox-A;Me?G);{)D@d&aK^Pe^=7{LN>aVjILp2Es5Ws>8(tc6^k`y zeyt3Ptz&+5U9s5y`Q(eAU)>7aZhn5PTA=$sFuzu7?N00Y6`e%U4H=ixDV$WOCsFqm z3n*q1@ti*F`DOEjJyTDR!SjF$%1T|?xH~mI>zF?STl+Z0&!6=Q+-`pU3@*_9ADBPuw|1xF z=1(&__u3VUC1(D}Nw2Nq{=)-hTlIA=e*W-?+o;>k&z}tobX)EG33u+pTD#M6JB#Q_ z*6b;GmT+{eT7-Yh^w}5|TgUBZ_=?5$|7~NQw|wK_&Cwxge){nE=BRFqhVP#bF*c>(#VhG^luen%xw>I9?kJPae9d|Te}-7df&POyIU8ejq3jL z6W;JkfAdcHj#TbMWwx*^mKa7GqdJDFovG?~t~dBb%;U+EJdxq}#QpMdIe$3Gw1{oK zI|R+WhOi5LwV$$hgaFYu^Du=6t1th<6ghuAVx6cpZ(R;!U)r+}XS|7}xi_cxfP>L% z*s`B=>;a=XWA;J?vvY4oIRM=M`jd`*3c_h+_Yr@kNwBOZ9s3rz-TbX`{{r1s7Gij- z44-ry(Au4j+o?sb5V%~)`6o>Wu2?KFH^PHqv31O!Lsl%de|{YnKYtD_aJ%{Wb9jO7 z|G@k?qP066H-Dlx=wSXFxni-z%%2Ic*gEFV(JL0)e{236Q{Z;<^XIq%-Bvq)!mZlz zt=(z8RWqwe^Hk%66>~dgs+v-^tB${hCs@`Vn1ALeIttBSSg$D1ZDk?G z?SZds?M}z7;hWh5^ABo82dhN`5OcNVU(sqE^XJ+Xi|zm0!X$70Tvy-2Az*wL2X*f123?-?U<}#LS;tV6k<~AO01)6}UG1^T`!||GBNe?dIpt9R<3r zcK(EWVE%Q$Ry{8M!ros^nuYycE9Q30RJjKhTgO!4pIB_wLlQq#?kjM+`KiLc<=Co2 z3~x2zRNA#O;`=!d(vbxw6~ACTBXxU=Qq3R^rNc?vVWlq|=2P zpxN*PC*l5rKTy$)M?mpZaQ@LtY$zv{M}LeRfD9Q9*u$yHzwi%MG(8Gq9*vPvyAR!v zFZ5@ylcnwUf=04?ZEnZ+7|q|Z+mzED%iUp@-Ah_htWX=*1KC zVh*E}#;fH8`B2SLgJgU&#jq=eK|V>6f0MK$drEQ=d($&)m}+_&g&;*5r?T_Fbo`BA zm{t4X!~D&Z7a(;G1|#n@!57It6#T+>7W9$jG~yrJuE$G`EN^;=?GB4=r;jafrrpbI zcX(_&{h~!P?OtKKBVya>cPpA{_Zr(B$#(V&8XhC|-vy9&Fz`nj%^y2^oh>F5v|y~w zw0MIpjwxutD4S{VCR-d=(1P(b)8Z|*I016LN)h<_Hn}H8xXwvY^5iIaN`yrIybBW^ z!^L6LwB5G4_Eu0jr{1HGkwG~0RFslw?}O{!P9?Pe07YGsPkcf8m5yp#VvrO*J-#0hBz>@!LX2>1qC{|&Xz!NtQo=@D+u1{t{d z1qkFCg3p z=@BGzQP{x2*?-44D?D-bS2WPhK2+%JZxja3@^We1nn#Jr>R^25g9~THI-FSmGH~;E z5bndin+rkMZXyk*$G9mxaq|x}&~AE#ZZ4uQ*3CaDF>VIqyBJ)!Dc0fUUm)|Gc_iPN z;_6!Ai8FuGstoXd3Y}R(VXQMn#g;R{0H?r(Gh!Xi6oU*fD*@p?N?#x;1!231p`DTM zCh|~t;$|5dXg41(bh8bGv2M1d#9&rx2D}}(m=lk&M_2c2%?XU(6ZyUXGU16Y?E_zC z7W&emSzkKZzLXhX%EcE~th?e7;OPWr09u?}Ze0U5ZtDhT%(-_6xP*nf|7&qG*H+zDM@qLaxy1L)!_`ZeaQ_>^`oh` zLQ`+Iz?8l$2Bs8Ey%U;xw*{v3MJ+J3HcX9f6Oe@3A;kRi%mS{gn{tAtyp5U@G*~Up zNi?jMdQxakTRo?ei2D0&FpIDEQ4@l@S z{SejV9aDXQ3``B8sgFWaAGg4izP<&f2Gi6hp{ZFdFr^bOFtt8SeHxnjtOch0Ofy*3 z($wdnso5r9g|Vzo3U z7_(ZI6O34Glam-(ZJQGxnSboYHJuCv5#-+nlzhclpq2v>A!6onA#YofT?kkK{*VDm`WG~rzj_W zvzp3Dzr=}6UDI$lhybTeXtXRKdFgg|$)-`cSZkwlb!N3RCzG1hHaWqU_G!g6m-9_& zzlkA3(m?yA0m;3R!#xu1%kD^fD%&A#UslenmgQvkp}UfWDy!{sa+_hbLr#`rtai-F z;)2!Axo6ln-D2mi@ni%&DXF`SLibjF+B>>-)wSP~Cz-K1RD&JeSzrry3tIbuN-#YV zMBP-M7)8mCKCvYm`?u<$=a|M@QROFJrIC%#_KB@2`PnD7VPkXmJI^%UmMXvaD%-K~ zxjr$PlDQ;wrv8d*e5O7H9ewvRyIcQ4VoYsMQ@@3#=C#0-e<3lZcA%;Gp{WHeFy&uJ zjHw-I>i5vp!WNkFZw1EG7@GPcG_|M&ruzi08=u5SE~H&tL(PX$`=*LpU`nr4 z15wRrqH%)Ebjv%$dr94Y0m(lwjYQf zQ!YZ^k}3OBrGu|>02^QEXUc(;bPS^}Z$b3s`krb`9Yj-|LQ|bvV5(Ep)WI~>B{a2C z3ruy6nmPogFeb)H;^Pn(j)@>boQrY-0jsH;grEmPTp;?i;u;%=f(Xz*jP}a{lD8R$ zw-?&~i6CqHawlQ6G$)gq)iya9HQJ{Y*W7vzr+sr1JA#sx2?f-S1QFcCE`fC!-J__| z)mNFo#uu|==pRiH!I;&OoM6OiSx#bPwQWv(Wb(2b*K~3fh#>#2res~l0<~*E1o?NJ$-ir#@()ZH{yADY^@1*WQ_rtYDs;i0KbT3{+2HFYmcVN8sZ#K$2n91}r=I2Yvv0#;Kw z2|*8pxIpx2#WgnW0}-HqKkb(VByTegZ!fejHx_MQ?j)?1=44W{+9oHXM*Fnlnp@8U zv~O-=57K^VK=Lt(!^b1EFAqkveOW}ZT9T88BDyPCtFYQOC-*^iMT4%f{%=|@apf_L zE01ZQ@i3U)!RSN&7~G~D23d+uXW#ZKFWw1If**3|!+z4>uB?84hOd@*)VF_b5g3(M zV!Q*S#fAJk=@-_>TP}~VXJbfCyokd^Dj#N->=_1@U-xf z^8yUF^pdkh5a3H_4Rl_ncQ-T6-}x@yelh$r4u<9U$Lh_vZ4V-w;j9f=AARlE-hU;Tsnf)lcl&zo_mYBo(LQ z`!vFrST&>Th|xu(o0i~TV|7z$k87J6(@lRDH4f~wPuI$JCB2*Y2b+sJkLy~pLwQk` z#^PKLnD_`LP<)6&);^^166?G25^E#ozuJ-?Bk^J0Wc?T_&bDAguWud|%_52VF)yvo zV$++qpTQ`a{^oUqcKkOk`Pa9{fYgqBO4aQ^MlPv&`sS+n8I|o7ShFWmc{CYbHE|-f z$0)fn!-d#io_!8;o(Z9u6%g6GJ42LU$xH2dhjyYtO)s2%e3Mb9?U_<%?3THHA z1*?2ZsMJh9eD{dX#WYQ&fb%f_g)F|0xq|y7+(bWD)f*@&DFk1%EC?uOQqW zN-?+mKcSDuPkXRKH|%zCzKc!q4{EG?`JRE#e=TR@y{u)#-a+fXTNuF-M$o2iABi9| zQv`&Z^L-$CMSwW9TMQ5>=;IH)iWy`=G0C#Jy~L`724)FuE-$#Qv_-2@nksb#Vvub> zMh7zYTZ-5SdLbhD3t%2DuXxy%#aVxuat%;17S8h^P)>*g~9L0x??TKPp-TpEl zVMraphO``ovm<2x^;=-4){e1%3nW<9EwFQe+s)qsnKaQ1Ze?i{-U9Iwoxed}xwSi; z)_>93zg(MpMb{N`JLV494Hj_+l!=6yvkJ*lSFSK1S0!2E%AL)X`yiOBk;(n`Hk^Hl zel)r|Ou!QFTXMrBjs5mvFxa3D!KXTi9|z#W?6-SD#W@0uy!|#6&3>EuG5hTbHjO+@ zjNF!KH2k?E{#120=P0nSmc_Q1&P2Dxm9XZSo|;()=WmNAz>1Ev7g{6oYPxhJxCK|J zh~>zvi(jN0eQS|!Sj{*WU8M7N6AdTH^o?}cA_L32NGDj<6)IEUb_A=)BE6<50YOD9te}X!_uhN2SH<3Y z@4a`icm3Y?%uF`f%;Y9F><53Ihh$FX%zMtvyys*xH}`HccF~rh1}*4Ls|*!g;YLHr zWUayZx?;&%1t20XNmwD8mZZpxG>LImQASz@5J2*9l8i(d8R;+p*4G|_W9>8^rt)wA z4kj%PfnK2j7n-CcDw?!JeM?$emQ5qufW!%H10DfUc|&d&4u=@s28`;PZNQ;WE>T%O zLEx*@M+QjC6Djf|dhC~YiXZ1^N2A$p1%jClI1)8+lKV-#{ zCLZK##JW-bA#`>SH-Arf5 zRkXU<6c9ifg_EpqC}VYVG63sqPsFkIcpi@B;bSi|0>)zFUpCs^Ym%`CdMrgFK@Uh&gH zSY#1Wo7Nebt_MRZuf}ZyxRUY9v9f8p?79FbYI?UrYYfl-=+pVQ8e4WnkRw^fzU(sk zp=Fo3fZPwXp@bv zt8q!K66s7dC+!WilCk6n`=&YR8lb42?u*vw`2@Oj6|Tl|QUo~?XZDU$vhtJpRX&HjC24Hk&z^<5KRYCWJbDzaaK`Ang$3U9fXr)B+AH0Hv_P~_C_3Q zujk=f985+!7%GKZaiK{@qN2%2)VE}$L)bL(Av$pyms7>NASy==rRr@Eqaz*C$A{<= z>Hl?6AAhT_aHBKR+4Occ?Q#uo99+9~=!R?IeSf?2{K&n9`U%Kr7mz&6pUISGX|wP< zoVFqxYV=u#0c$-DU^I))gnr3DI}%mXELsAJ8k8f^8XcTPqj$1{P2WI{AV)HTJ&PLs zP!=_p9L`0v=uxrmRFYyMCNlw~&7vHv8I3Eu*)g{xV-?Aw$Ha6qd8o5!Gj_2ti#C41 zdF+Djw929-9V{ke9+%H;OU67NheT&$tT3PojmHtyTJkoBG^6j)6nQQhm5eWrEYvhbJ_ZyuFz2H+2I>M@eiT<@ zDKdf_3442rH2R?wX)ZaOi>Am6W8JAFe?&}X0!W)8Iar|-c~Q*m$XG>E@v?kwTT&Nl4M00 z$?91E*4I9bW9^eXJdT4&R@XqK@H{RgB`dZv$%>6#$?DnwES{{^l&nKbO_SC2XjL+> z654haR|PL<4u26a(!(3j)_WBa`+XzLN8UCJ%;9ZA_CK2NZi0T@3%c>mM0!mNw@`Rp z3%62uLkqW2cvA~^KqzS&bi8U{@hw(`ueIy1uED=Mp&r>6FnT&GS4}CrgXTzM__(Nv zyLE39*b{g_m0VEr9?iQh6i-ml{%*7nx_%D?yl`tqg7Z<}2=m*|GPbgFOS4@GkMtjU9{a^9$nC#*0&d(Hq7niv3zb@ZZD4m5w{l!AwpI1xCq?pCgB<)YJII!Ef1DnatPd!50u^NU$yV-vEAm_&P6_9q!>@p`pOM z0e$Z~qN4Ge6u#HOTVVtIbXpmB8<*?8)H?65!CWo88*YGK&(sax3paS54SvuKJ_t9! zZ)EBQABG!z#0Ed=1|NqT;FmCUgHOT@K4pWSbc4^r4fxcr`tW(U!50wl?uhA<3?PSR zHBe0kMh4iIVPUa_FCAvFr7vA!vDz0WS*-EJJa4GP_6+h@5Tf&4NqUYDCKEuDJCO9H zI{xz)9kFb?zEC2yI9|b^ef@vK{jRd=ObSP{CHV~}zS@(J!d!hzkqKAwNks{FE+ByP zJx&r_l#y`%#8B4P{*GhquRQ#WgGsnQK&9*l;`rM>Bc?MEsSnua?!}-#|pNlDI>-{R6S-CTt|KOFAV;mRBFt7)m2t z@JljWEc{DQro6ux&K0G+7Bv$7RX9n?ql}bSgFi)AU)vJL+A1FYg#nZDT0*7J8dsCn zm~3S-8XHG4ntZ|(T4Podu`Lk`O%|FoV-}j2opWT3R73T4RPPb_+^ZDTR)3|X9h6JN zX6sf5I)++t3gGbRbfP@<{5Bx+NiX z1QHm~iM^w17$jM{^c~id-j`@3xK`}JYo4l!jYZqO!@5hoXob;Q^&PfQQ?yoni`_(9 z)x^;78osI*Ot{zuF3K==rLUYe?N?R5;=)9d%5JEP-bWWfox0_bhS6JIcWOsIjnufZ zRFCWTplLIlj=NCPrFyTxx1O=qm89#4`Ah&!?nucCKdB8CeGC2Ha9u6>3^~jKZ(%r( zZzsz{fJlo_Y~=}OAohk>*NT$_VNurAc)~o0eJECY637r2hnVKzcOFa7BVQL+XmYvw?v^L_-41k~`(P?GrQk2-Hr-P-{a`eu`T1vUtm z>pE$j!ECUY77F18e5g_lmJByoiVYUm4ZLszJ{YP7ONSdQ!v;&}21CLP_+Y3S)P@@@ z%LaXQgXO{v_+Y3S3=KC}o(=lx1}lUc;140_1}laeti%TWb%T||4e$p8bc0pG4OV4? z0lGmk+yH+TKsOi`ZcqmSkDg|fIe!Jt7#}@lt~kG~e3>a0Tl+ExEVl7wbXjcc%eb-F z&X*BkvAr*SWwC=Vyn&VlA4Ej6?Zd^TB~{YsXqIkkg>H z2*{_#eW7*!Z@6y1Q>+W;k^W^Oz@K`G)t+z$;(8RhOjdV`N?uFY5D-Ax04E_KWh|42 zVCL&n5?kr@ZHbK|%jD3)abtp&d+%Ph8A>#%A@zIr z^e?)8+5~Wcy_D;rp+Hfc-xRGe7@N_j<#08&Wng+D$dSij`<8*xM-ZD|U^15+&OtM@ zWw3dyJC%f8#AGIbCJQv@mH`KAM&p*j7BROYV-?vl7!%XY=7m9jV9vE%W(pdHmlBh{#A1LkOL1Aj&g#=pC#`l$yjKIa)pbo4Et^_2d7x1Z7^U zWoTCP_`f|M;LrbXlDtM4d2KiV>uZPMSi33@EAy}-56k0VGTaVOF8H{Rv=P8oCd09D zB*Qh`2-uN`YotRA4NY0xoryaFxFxy^cNQ(NUo*N*40Z&j_FasKRZV__6F(n4lxy={ zfKVa=f5EXHXEk2C5;&5Vzrd$eYB9n=i>BS(2x6RdWHw&j5z8d=Q#sSxnHaE5ziYJueB6RFUWGds=~I7YB)*_|zP zcN+fhbfb$4d|-|0@{KF$&0?i|VPjM3eh^?#>3jk`=og}XBw0%F>P z5(BTmSYu2}l&P4O=u$B)%v3Qgv&!OBUq*!CO+e4U9ZmFBo`g5*j-goN$vqI_u@tL4 zxnDy(9%6~>Gc2KoZOIW1)^%_wQZ$7;GR{r ze_<W0)AhJlgu1t%-r4ptgqb@$J+5c?1qDxxr?Dv*cTU)W{$1Q%&~EqnY)CT?wKom zy)C|@kEw20ne#~Fp?M6=COwYM=4C)G84ps<<|Lq~;kZ23x`O#k^xiSYn3F4D8(}KW zK)jM7!*m~dS5cT=0|+2pjgw3^WlZ)o0M^$|#j*AP9;WcH9}Z^5uZ3RW5L_rx2{#Yf zZA+SdLYV0%Qq$?LG4BLlPw2?^8E8koK7sEu(4FXX-U$7YK}YK*<+Ak#m_rjblf9FytUvuLJ& z9Qq~Wu_Jl#a(LtR6rdI2BGrT`bc_yp3cpd!{$~p-gWsIVLNb>7QHB$5>~24%UpuO#gh$?Z{X~ zGX0A&-ApXdnLaYAnE=Yt$d>6}TF{-=nLfgOqyawvy`0Z?OS*prh}fx-Xo7)PDb{$B zW+1*svD%aL2=R4_%>KtR_$tc&Zvg^GZ{j4`pE9!l`2ei1Jr~E?vw1j^htqK|+5c_m z$vqvsD+yCaP5Nr_>~EK`HiFT37VIv%MT&1!&yztr$h}uu$E|ojnE!nZDuEf z!Iu}uKO>NF+L0og-p_6b?0p_R28TeJn& zyvN9^pp96@BelN8<>>2k0YUMzPjO;>7xT0H4(*Kr zvF4&ReEES!uf^5a!XUz#$j#2aFfjUv1M>)IE;(2a&Cny@kFoA#B5Lz9T`vqcSThY82N3h06KzYO{JTzv`>?221H59oC8&xQ5E?)~;cg?DXI)1e~ z{Bw9=Rk=y)ukDN+LNvZpvH}Xc*|u(lrr|H5m*^NO@$K>vg?mv}cUKNV^zPagElZ|{ zjy%)!?m7o3YJ}UPHOzOQ`Fn6RmINcnk-)YmL8Bi^g65LLxo8sX80$_Y86sjb6F}M9 zy-tE0tWXl{6mvT=R*@vwC8nFnL!IZFv5SpKkYA@z`(Rxcbf=jFAM9wt#>7>(d~REk zV0R!Q>q!V9a(Yl?*1MB2RZ-Sk1Q0-47$?bkl#%rw0$_dZ131>+hl5FYy-@2tLSqHi zt%xMoVig>UkMf!T^oB}_ZE$(`<2cLJMcMEPD#6%d6rQ9|pduH5d&q~Tb&qL{#i{XB zL}SmW#uC(cI-;>xRHH97o{4De9o6VZjb|eo`$RSRQ{%aa#=cRF0n~UtqA?+=F_0QB zL^LKwH3m`R#fZkFsK#JwycE&cFRD?X#>)|n$x)3ZsqsogV@gzGDQdhL(bzw#;ZftY zh{gd?jissadPL*EsKzqXcq5`QHL5X$8gE844vK2jQsb?N#xQP z6VW&%sxg!r??yBZjcP1UjrSrNheb73pvL*J`_%$U}y)cPczp1$N17WeWcd9b** zFIj@ceSAp=Ebi+|+_N~rmjGvRqA!um;v`=}mc{*iiA@$K`x1mKPVpt$Slr*2uwwB5 zU*dxE`7n{=kK#uRgIA{FhBYHg0?z!16Qn)u;6d_9qlL zT=>44`da^nyc*u~Dzq$_6*--XuE;l`_Cff$r|v_m8hk!6&^v9tFl8+E;$9z6)vzXN zXr-$-#a?1JU?ALik-sSgm65|*!AcgWg`7~uYC?Geh%w(Z+)Zr!pqq6yq9J_i*U5Ity&&en;ZPRqmEXY52jCseVWxF~>d zacsB~SZ<>ep3+cVky(M>*3|n8Bq>Z7tA2caZOxx*F%_a%Das{c7CX==V74I)bxXuT zjT*L&;*(L@)@iGK8e5&Tt?jI~JgN4?A{^S0O6h||IS}oj3YKDLnw3Pd6EXkcSjB>^ zn`K_GA@I8V)WCCX98vV@ zqDqGTUtBa*SkQOD%&45krvNqI8|e8~Ki3hmK9X~|&PJXfl?V^H#3Y9EfZ~6ImT}pQ z{flfeFs;s>IkzKr8Rm8@JkQ_hR=<7MMjJy{vGp1@rhe|O3%tg7V81_}|8|EN#4A%KA0gK?6(3uWBi`od~`?czAr_Tiy74~y`y5Dz_Y zFe~>%6~bXS6$aqCzAI`5Oy}i+q04G~569&aL2+{{u7I<$K7-ot?0}c0r>xoVd{^ku zy7|tne5q46LV5qfN~n~vSrLD9q2CxB3jNikxgF(0>zOnYh8R8=_0rKJQ01)*sj6-e zj~Ij_d1)0b%wkh*Z1|F<)lpPgRazCa;%r_jYT;-I!6+~rsW>LGkJwr9 zg*|NPiw~;bg3ivesb?BqPEga?D_FCZ_TowiL1$}mQ964SRo13T-4LyKH7~8Bg=-)L zo#j{Nl<(K#a?s#9Hdt3TxIWx~UrJLAZU{HH5du1E4AQd#Jz{6Y7xu7)FFvS#3pzW? zrk-hd6G2U9Z)Q!s_Tm-@L1&l4Md|FVR9TNIb<1kS+jwbxE!++v=xn>d_d9SoXmBS4 z_-@+MP=N;MyFe@71(FU^-!s~G5y?1QB2rBtGD8)Zl=#&=Nk>E)=Sv!5aTi~vlEv}9 z#4C%FeCacblYJpJtrFWahVG`J>be!#ORq7--a~_lDYmcynk1&xdw~&6tIMN_4E7wl zupw>M4doGD-N#ECY2kjFH}?Z3NOeDW0GERX53<2X-Qb~c113n-;NftCN7!Iv-Qdx1 z17;=F;IVLn$Jt;L-QbCE17;=F;K^`57^vagtL-K+nKEP4sF{rV4e>5}g}p>TS49`1r~pqi1-M`)5Fj_gTgmq`wA~c$?O{ zPIss~;1E6zat`NqEb*=#Y;Bcz`vzy_0h)L5#w|2H>pn+ExS;5Vs>&7=F9HHcFW@AE zpo|5@7y#DSZh>R%W;~3-!K@%&f=YDJvo&hfqK7R4@8zEUGPN%Y{|>JB*sc1R-HXwlX7EZ!G%3$9( z0M^&;h-2;cJZy)9Vc$DYDeQs^O?pB_LmlcjQYU!#)cZaAP`H-r+ zLW~SvDWnfJk{>lSC1Xuk)C)h@%YXP_{L+p?vBYh;0uBt;j|h3X4un2T62wO(7s4fW zHX1k|LqCdL{zbd-K?goXYZ(2EMt5UBn*M#oh}V(b1pCg5(MKSfofmV-5kAli?Yw** z>rN)d>urgM$xHxELdN+EUL33$jXN)2#N3XIRb=PotC(&k51YS>jXN*AGplz@zFyFs z?x((MrGv%1X!lJ%w=GZn-vSXY+DQl@a=wFDw=?4j!uPDJ_9Q<*oJ*0JPt{lQIowZx z0Md^*N#>)B%r^lB>udMHv34&W_Q1hpzMr8|n1l;WG9ML9=A*tP^Zm-Ek<3S&Q0AKg zQ91GlRriA!&3qw!o%tH7@W9W1H6>%!o&ou^-%vI8Kl#@o$cKN@P$VDHs>z2Of@nVc z8~Ra8<@4eGLAU-zYmE1QG&-5RYnl%ueTc-kJs%qVP(C!5Qsu*{)=j%pNwSET%mk1& zA9Aol`LIRI?Z{X~@?mvMH5j2k9>FwSGzzNr>^SM z9j6kT!Wft14R5uq!k@u95?83zgUB<89Q|6*;kX1x@UB6OF=`8}hfh%ckwi`d~$2ut+2@q0#`h-g;sO&~Ksj>N~y;qT2J z9oXxG*6?OAnw^QOv8)_Hj$|5pRyO*ftZXhhoP%a)mAZJWJC&rYh{;RQ6NK?nXboRH8a-k`2;-$=-C4jm zuD{U0!3u@(GBLN^VO$&2UBJ577{-kco69cfPV2>$4i>YxS}vd4mM9(yL`1QK5F%%J ziq)P(F~k)pay@k@L#(2mwUq$@q?K@zJ3D2pr%nc7eeH=j)*jEpu{fCZ)GAOZoQexc z>nXM}>nS!)Tu-g4oES#n`W@8v_@>zTDx8j%;Z1K^HH)8rxng;|zib{4XUp(<#I(ep z3WXNlgko2sE0WdFres`m-1M8SNX`U`8mHBj%WKf^8Mqo-kwlOq;b~uy82!+S#9VSX z7hRF88S73ZaUL<52_Wr?go71IWg}v4N5(3$B3V18o5@4HB5B4hHm0%>!HQ&^1>I@& z#!^X#7W`H(C#{>$Z%Zz#2O^S}#1K->dK8(wPGL}0l)N?s1duksNs&h*)o#6 zbju)lu`AK!wHex!jBAek&@_2n1{5_;TPT-D)9|IZ8cSXgI?#ymV*< z$!nW@ep`~)wm?Mkk{CkD*^VNU*M$tKijvn3fB@3=I7#xNjO2AK0PAb7#7bR#YyV6po|<0gl-itIk2E4!k3 ziMre@x)o>DvE7Io&Tl1}XxuDfU!&P=cLEvT9SNjqcDp^Ww+C9on>}gvW?YSBw+M11 zV(r<@=!deKx#Vyzn%(w_b*GZhkC@B^kT$zv5I83ePgXQva3(ArKFOC(*pJfU#6>_i(U6fjBMZwmT3HiRmt2U2F`*#_gU% z7j&ofc8}({+3qU2X$=&)%D9e^SkWqDCLn+`11DK!P{u0bUI5nD z-i>4JT|C@@gIQ%90hPjixRA8UU@NoAVB^>-1N^PRpUje9t2>g24-j#C{vHoLyRT{( z!#A5~1v+E!AHQv<-hY}!<;WM|*it_4uNqi*2xZ(|v7&S#MRicA%YxM=6=!cdK=90s?=(6G1Sa&K3<%r2l0BM&E94t(r zne5|YZb!x{vTQgZrklw_y=-X4F50ryi3_^ZI$PfS1dT?u=rXEBXGUWeuN-7Eg1mzEB_bhj z@nime?MieGQb%KKH1)!dMTHmHh%MO&{~P}6qTZb9z!-P2mwfx@d=*pX_VYGE9N!rAz1=%K$> z8F7St#oyw?SDZtGuK!5o&SBVH2>Y3a-HouX@e9r~+EiCH6nJY$4ZC|7c06G}*RXpM zww$->8{2Vj_X@-AP1r9q?7oB@2cZ&gClJ;Q^u(}@Nwo2$wlSGDCRRAmQ^Gd(58F6^ zHonp}rqafa!S@lejru`s9AWR*fOS!G8nw#}nQJBvM&n?}4xwPUc_;+$8{M7hw88g) zDw&psu#LmRHfGSqx7x-Lv{8 zNfy*^lBAB0qX{0FsqX>pnyF)`{a+A@+rkyvY=I@(P)kf7OZ7?zh?;lkT{C_v!BY?YY1B?X^rut3+|a9E!-!|MGh&|o zkTCRT+C6g({aH{CM*D0C-j8~;&m~Z~(cZ-nT@7n$qMt|b)T4bqwbPIG1ynCL+Abbk z81pQN=oi^NbB*@JP!EWH2?ay+OCfka>7l=zsCkFp)xj$Wo_gr7q;~qDzl!SRhTcW= zt7D!e5&aswXRe{Y7V5!hUkAbaS&#M&1WG;H%K6kpzmednNBbsfryuQ`sa|fhT|BrY z=2;TaZ?${o8tvPl9uWO@3Wn%+K=6LiLw^@h^A5eMgC&Be9{Rhfoqp)=p?bNYcM<*G zm}f~upJVsTHT3sEJs9o#A$Y&)(SDFXY;y@+UbY>IjWZ%dKb~3 zk9n3v^cU=&xrY8ls0X9{5(MveJ=(7jsN86eH$<J=pWlXa}E6`P!C4?QwZLldbB?$P`S|#GI~a$e?jonqx~hd(~tI7R4+H$ zE*^Xx^DK$z-`G8KjrO-t4~YI91w-`jA$Wi3q5pxXd57NB!5;~pdgycMFL4#E3dkM^GgDmU7}u1ni&8T~JUrylLUshxhb|Dk%h z(RT6R-Y;Bp z-bM7bG0&2S-p=lsYv|iUJs9l{5WIi&Xm=t|Iid$kmyAU3Oz_mB-G$oeN4qQ4%Z;{+ z2i;sv7FE>@L zd0vT)Q%}{()J{KDt5Ch%RJlmBDjEl)S%lzK>(Q(uY~Imy4ajhUmm5u&&#SR<>e2M6 zoqjY|r+T^3bP<1zm}g1EU(@cHi})j;9!%9*5WE^aRqGI_+*Ac0C}kx6x&$vbRjzri zXXDgUwH~$8Pu2QVFE>>#5^aFS!Dwy>!E2>Qb0lH&j;3osHYRwv(RBH|2^*&#%~8}& zKbo6Tz1(QJh`(9Pvn1kgZuiVZ{4Jm!Ox0)zUTZy7V+mAls)C2tjKtrP;N_;uHP2hI zaq6ksn%e27Y8$GTn<^KHwngJ$G`EA`wb7%wJz?{XrfWcUAb7dabosm^8>b%4ov59D zG{;fB+-SOpzjMs9B;xO4_sm87U7;RK)ou{HwtA|@6NumNOj?F3zQ>nmd$4h2G#mf2 zMdU$1zE!>_waX2U>v3T(G!7mR_oncwekR-pg4a%WX98{TJ71M_XCfP??#?7?SK6KZ z&^YMMWD2G`Qy_Tlb$1S+jms;1r|iHm>{P;b(6G}8TP{9>9SlddbCKd;f|rX=*EAo( z#*ryVdb{dSYNwCS!>C?v#$0J9O?lbW>7G6mO6Tn;HcmZnv#Fha-j1evrSo=7%(J9$owrliIQ6`pO6~OXb{f?yoww6to+ZuO8FtTH^L8fGgLylP zf|<9oA$Xnjyq!zba`RShRp^?x^9Ww)yq(X+spstiYNwyK3#ne|yj>LYENR{@wtME9 zw@aWN%-f|D%)DI&0pGDS;x_V;4%Pvy;hlYXMV~MG<8MiF(ID^r`=6R(OJ81`=hbTe zb91%EmlxD|wUsaLk+ay^m)E^nY~#zT(k!<1<&9<*+xhYqGK=kfc`KI14!*py$zn%e zULj<$lP~YLvDn%F#Tf45%gaE#+SQkrQ&{Zg%bOD{cK79zd=`87f0|}JefijvR~Pc- zGdUI)_T@7o78mj50}K{>`Tv<_y?xp3<<&)f*{Wo*k1tzcEH38DJ`RhE`?62K;u5|* z~^}5$NuyFY%n(eO5-V!sLv`)S?jB^`tdT5+GVmLh$+`p6Barav} z+`lVqwnVcFX|wml%r2Z@_FlVLd=6$EwK-w4_tESk+Ux@{v%M0`K4>?K2SKaZhr(tb zrrF-w?4vQWizb+T%x<=|!|dZ>vro`$A8q!jnAyb=%sy>5i-${VZ=VU9eU@ey*JhuO znO!2m>kDwj&?_&twK;6GjV>m}U`}Y}jT!4_79CMsg3<-H`Xtkv8shb##&G?nWZHJZz*l827;w$_+}c? zYU-Y~3L9%3Hr9s5JZ-F<-I%&Rr#99;Y^+1rSVtOLS{v(ZH>P-&+E|ycv94ib-DqqX zZLEjgm`b{-jr9y0TPSR7VHz8vjrFn{QyDO|vEE^0i-wK$p|M(RY;n7>q1gzsMA%s0 zu(5tLwyZWbz;3KpHe&w6P^=EOJv#dR$zJ+VKZj*W;o`vnJM;reMNv z83^7`?L#e58v0-6jbu_l3Hny7Gm?PF*#{96c)x*Ztps|&-u@QD-j+E&#wpQ5K+F@hs z(Adh_SiRktS`DO*_4UHW)(;!ofW}tQ#x}AW>zFP4Muv@T95%KIjjgJUZE82B9$!-T zY_qVj&BMmFps}JhHYSrX*PM+F8{0B$Y%3ZYrj2c5H|7{dm$7Zb#^Y7jia&Q+So33V-7aDjO`jWwp-ZP?liWVHnxY|m}4E}GPY;f*j`~{ zd()V&jqOWgk()u%r#};@9lsg4zFR*rY<3dOuCC2aj+tEpHLgdyDb$W{tF)8&jPDBV zPxVTFHRAv@4(?e8Lh#nqJ|9Hb$WV<)@Oc`w<36`>_>)I}mNt7>%xu!9)YGXQ zpCQ-nx*=@#a0uAYH8*VT`W3jt#|>TC+v6T#l`lJcEVl4vw~fV?zHFGWSnbOu7K=5$ zY%HB~}+#f5xX2(q}aFUvF* z7x85g#bPgC)-o*i_GP8P;-bE+16b_i%Uznq#eBJkvbeY}cQ_W8@a6u)VqahG4lMTb zC3myf-s;{ltIGe&cS~vzm#esG#8rQw4_im3P?7ABE1j3g4Fa&EH z>zeSyFziW$t=F)p5Vl-eaP9b<8iqZMuuVe5 z(nh%vak+k881{U^ZlGZ=By73g=yAbb#Kv=j-&wK$_>OB!;9~k@`h5un!-PvAcpGX5 zFQ<)4e|6`Iu#GFjHm;(LjkJwxXycADFMPP>@7l19>%um!r;U-?#*MU5ZvI?jbyL{J z&0!n2(8k8v#%;7wj@~XCw})ZxAnYa@_AbKm#}#=#BsFATr`Vi{{YRAXM^&!@aRIhYwUW$2k zq;qUu&gR!EP!GoDRSIToUW4Fmp~vP8qNd&e!B&O!X7^^;*jr&^Z`0UlZR}mUF~#x4&&o3XFITsO@QY#d3=Ngoh(Ok>J* zAL^9JRA*{ex>D+r$yC=grd*TM4UGdvbf;h#(F20Fy`H3nXe0IOY{(=?^RYcZ*CZ}X z@YIvI2(>G{VfI4fpohI7csuAG_91NE9=f=*7{OEbaB*sv>!E7}yaXBtJ?sksJ0WID z`HWoP^DuWp_*j}0ug^JR6MVs~Her7ZUF@qRg1?T)}zN zjjt?0I_oPmOG7;f?PVyu4S)EC*$@ccIPJl*VYTJLYD1~EvsPOHLe$ZNosO#>5;YP;?#1pf>c%~AEyC+))OawQg7IKA2;Q#RgVl)| z@!%lm7_33vxCiQn9pCF+lSYjPBPbXT)`H;eraf4Ps1XllIz3pIx^WL&@0ZonsPSMu z3dV!=A$YrM4>lxf#Dl|~9&AM2xCgiwS$Qy$MvVs>Q!pNE0>K-vJ=m0}5f2V@daxOF z;~uDWb$k{!r%~g<78HyJqak>EXb;8`HR3_is$QyIB`^b_<)`oo4sZ zX7`Ah?UrD6PrF%Hj@>J4c5j;9SDW28X0~U7*$H;Du8cV`Y<3dOPS9p2$ISLhFgwL= z)|I6851T!JW+!U1Q)6bANHBYl-K;Arr-jWPOtX`;*+XMy_e(H)nBA;vZl_bdf_Fk2 z&@M~WCjFpviAK5!bg(Glmy?8r1qTPtLx1DDUE zU|c>Qf_JcX`9h*bTs|bh<%_5tciDA|xR~ncUA_eBfyE+3ZQ z@|Dz%yX?BXTt)TtE?*7xz~yTw7?-bw;7!*qUr*GC%MA%G-$3oS%dV_>Bh}Npd=u0I zmv5$ET)qW@cer->HljvccE9O;J9Xo43cK>{9buz)(&!9rv=lSye*OAxyHQv8+!Ho> zFOAOBM(>Lmb-%NJzul;dO%H^PK1icSXrm9ujJjXMe#CCn#fL}3MjxZmBel^dVn&m` zD)A(>E4VE_Mf>KK^fU!SuxB86v$QkM5k5k&qfp~ooIX$Ocucr%NiR^n0^eUmyTJFC zC>Y;ghTzTCzQ0QNi0?-y`2HHT-GN_dqulEkxMf&BH~ckh+XHmtASFn(A?v`#D^$ zfqLL_D+WLG8H9u4PSMs>fY+g@MQ;`#g@M8lCxOt%XT%3HNNZ{v)Ia) z4O|vm`?8bDVjEw!G+Aux%ibc3?R?oDWU;+3TXrmV@MRl~#g4vgZL!$Nm+dANJNvQ) z#9|j;wq;oC>dRIMi`{(Ld0?@-FBJJg~C3kS`B{EH3QJ0~U*m`10Vw zVlQ7F2w3dx%QBtCMSWR3v)IR%B`u4K`LfVtadBUkc`PpB%c_aRzP>C%SnTJ^J)On= zzT8?_9N^3Cj>Un#+&EYqJu!!AeIavub` zV26fbmnZCn8g|7rut>z#Tkc9>*p&%;k%nEBus4_aAm8O}k+5c!H7snSjy5jVHddpJ zKP$B1hi$ALwy_3nT%v7^pp7AAUZiyOW38}_wZk^np^Zzmje6R6u)=<<7q+o}*v1C5 zahbNU5p6tMp^cGY8ykmhY(g8CYa5%=Mx`sn&BCyo6ZQ%XJDRYSerb3NVGWhWhHY#~ z8&_%@Tc@#s8>KZ0wh7zVHf&=%+PF&F*q%1d52$3mcdYJZvG*ffoZ5jXk^5)To8YRH|~M! zVf-o@H6C0|!FX^D1n)NO!F5E9c;J46?0V|PJwQ}hU&y(EMvVtIQZOFe1i`yqdvFU; zBObV44ZD@PaSvQORkzWo@!)m}#)CT`cz0+I?jmZ$1NVzrCF;gKaBV!@O{2zxdngzW z?uFppsXe%ls1Xm`FD2bi-M9y?9gYWR)Ohe91>?a(5WKsz2agc7CRl6Q-=lWj4jv8L zcr0w=aoQ+p8&A?kq?buIsHeg>PZQ^Ejq_{_ryFWq8?w()J3d}6);>@5ayKj2K)is) z!C=2g!3_3G5WIVI2VS9#$Ur2$@A4|O;~j8K_-j zh;+dHk?K3tjem~oikNr9M&F~+Iojw4F{AE}R6n#EbtTJ>!bU%)(fhQ~Ph&=to}NCV zcKTJ}=QL|#^9u@Qw7-Pl-LHN4ny8V{PWqJQ8)~Qb;oGp;?`ZY`ZFX+V?1QLrh1n0; z%>GETrt3dZFkSx{g7=X2;a8$Yy6%2q;5X{ViRKFQ-@``#pwWl5(Z6CwlRk|5o7(a5 zc6}K457jFT&wpc{C9&~8yJxOv`KsQbDQQ8$Oi4=!SOpuAi^BpJf?Ng55|B&DDqj|W zEVl4vk;h_7UshWzR{OH-VX?-S^#_Zsd|3#v*xHvnGK+0|xizxb)|Yz}i|u^5m9W^} zm%9Or9el~FEOzuIL$TP&m%PDZXJ4Y3#V)=C6^mVcAv%lQeBm35-F;yJ7sTwfXZqX* zLU=)3YZk;GnFVoMsz0JB)Q-ZVTIc|w?3BBne>$RZ5Gb7}e5hB`ooVASZKEq~>{#Lb zyIa^s_ppr~wDGvMu@G%kO5KISHWmrn=tUb(Xd8>tM!CH^*I4xl+gL1YV{zJeQrqa8 z#)j(_-!E*Vf7r$V+IULa7(^S>g849eca9w|m$AV_iKM@zcrQ>po{3!Xz9iHGW-Ud* zFw2ABJ*|7P3{m4faqJVhdNPD4se4jO?esla7V1GymZM;LG8BUMjPA(_M2+`EEec}$ zM6RB!NR-q)S&7=|d$KargPyEH!SrNR2;Q^0C&P#u?}>w5u5hUf;}0kPa~j{b<2&Zu zg}-_je+}Y4uklCN@f|ba!e1+lzc%q-(D>^Te|QjmyX#-<#Q3bWKYye1K>mIA_*V>F zQ(jNF)Kk75wbM`e`cMz1d;Mm_Z?etyxAJl^`ZBM~;X$J`2E4oWN5jEZ=`Ic@4u{4fwsk^i@wbOTL7pMna z+LeOo(rysES9O=h6E&er8E0t^!lmxgp43j?rM;jYbZKu2rc3)k@Ltnhnn2Weml_)I zBjgpv(?mk1?$#t~r|;H&P!GB_nS$xo6bRnyx?2YjwM@4%&enm1Ox>-i)K1^6gP@@@&Uv#42B&>{x8!%L5pT zEq!@TVzJtn#~BuDe0l0%v6U|m2Q0SsWp&MB8()^EEVlJ!eaB)uUzTDlw)bV##9{|u z7C0<+^kredVkcj2s4RB&f2D$>!OBH{TlwQ8nt4l-MTNTBPFH?{BJFmhBksl7yL zKfb6m`a+#L^ikiTSEpKaS`McY+hb`u{2QF5{ZL%>zJ)}a%TxGH3oAen5^!x0cl?27z73pzi0<`4Z!97mlCTT~ALFXeA1 zwX9jHs%q$E13vFJgy_Nb7BwwLuzgkC2WZD`u1ohg-ReSR(>)R(z}gTenGnjD?muCp zzV>$p(8=rHmaB3Ip`Y>p*zlNaW*Aa5B) z-ipXAH1gI&Zt@9I7UXTh$lDURrAFS4$W2~%%YyvBF!J_9uGYvq5V^@qZds6b3?uJE zt`3zRZHWa~OFSBDd1WyArv{&je;c-Yty0JCR#!!nnS6r3lqU}@ zr7V^wge^~`<#yWgq%@X;zpaQ*>kz3~EbkY#Jeii;Ys*tISynH-WU;(|*zy6i+(BDD zFpcHl?|^2vJT+|jAX@IIEl*2hIrz)5YR4!`pAQaOK7^J#Y0HPEu^jX{yXC{emZ#Hl zXKlG5jpcybvbmLsVTXq;&!FWl+VadamV?pGZuy9?^3kr&d)rwelQ#q})6XM~Z@gn(tPS)_4MSKwl9HDq&H#;Ikl ztlL;@;mblxt$1Z+#A3BCOBohxd|7+2*vgm10*kGExx2I2#+TbMi*0?mf3n!lmm407 z?R~ievDm?vTLOz6eaX=*cJd`@ve?;|EXHCNU(yPTU44mj7Q6Wpcr14JB@$Td;R`ic z?CA?vSX{`L$zyS0Uq+j&d5(~0#^)>!7nj|CVT`IqRkrLt4a7skP?v(HCuiB~Zr!xzU{+FXFE-V%_AbP-uQ7E`uMVYvAAIEL7JmrmwR{1@?p_lRgN5FFoLpQ{OY%SFkaMT)|d0$~>3Vg#0jI*U&?>Rf?3pt=4&fS%kEnMHvAD1-OkoFJA5hh>CZOmdUWr5pI2C#&{GxQ= z^#LQ5Z4B4#7%my=J2`GkLbY%!hGxhN4s@`oa2G1;hU!r-K^R@*$p`}BZiv>|xd#>A zZF+X@g#hJ;a7r;dx6g~&Q6Lr1j%wbFv!hmt*4atpx>{IUiIv%PH) zk60624=3N$&2?t3>RXilgKZCkZ9?uxNjo9;9dU9$hRT54k3#^t4Z;%;0rU*pmrp8p z&I{Tqkcw%mn$I8Frg7a(wPI%1-B_7vE4DGy&tj&9GS73$g)(==Df0p<1IoMz0hBQa zFF^#*n`~d6G9{r*@@%Umw>4Z;^9-}?#>zZoXTv5J{pcVjh+>uz#ocioLuq3adr zS2gN6^Q(Y><8OiE5-jhK>=G<@$AjfvR0hHF9s~r7L3kgcb@A{4D!h9b9I*2t1e`v{ zDMd)#D58g(hS_#wWgfCLuDf$$cGullcGnZ~YZ}+xgE~Z(v4+j2>zInYhOrQ$8fd7aLMd+;J8UDv+N6XL}f5L zogiR#3_@p!*4gQT3hyC3J6$2b+`>4en4O2`#q21Mif2bPZ^qf_;GUf{uDjDkF|+G# zEIYBvx?XYWQLg7nJ=hl#5U_0#uuaI_o3wK+?G{C4K<+*eKyHJu7(@W|WBc;==||=T zZ52qxv{lXL4{g)9?xtEXv+HiG%(NBTnCbqQX`#$OPPtIVvM)3Ul>uc2LjYwALIEOx zYT3R#WgZpEB+s^cIaXB7Gt9OdEAx=0aov5#%I>-wt65xklPkOHZmbGjuQB zRv^i7=_X`RHO~;2ZY(=P5|(ypTz3;PyX$T&yXy(hE#f+6x(+if#9ED0F2u4tVEd>H zh_yNd5X&H}0ntjVHBsR`p@}sD0?e(4Qwm}|IWLH%Kq@AdYTk^*>cUC0f0mrabvGG` znO%2d*@=~~Dpj^C&YG%uo~+rcuj)V8wm#S<a3bvKsX^@MDoT(3B!RP#I`g%{BT1ROsb9G8$fmt=Q^ z)On~3Lh5`72q}Yb0Ym^@&i3WkX0PT87S+5NgC&7+XLAVy8_5O1mD!kY9 z{pWfJFn1eHDMIS?d?BTpH)BX8Y(AxN-5mzS%&xn!?7U3a;8nJhdFc)V?RqjV9nBjb zHPZNyur^c8lYMYBZ{h>UdOOG}v2iC^>w4U|3zb1^lpr8B#0?l2~>D*>N~=d5Mb^FoKnQbTlr!`HE+h)NZ8X) zH-?n-9~^%X9G8%KnPhh@ zvR*-D5K^x~Ku8&c*C1L$>UC6jZ|jhH0|Lywk5h_}dM95+Uef?z$Vx?s`HtP_9=TQmT2LkiyF!0s@YI0FFyYeMGXmLh55w1|jtc z1ca19_!J_5zG3_FYqNLr1&eCljKPw?xHPW230}EE*4DxMwHeE!T%8rR+F zLJwaC*WFl|iKSexIQ6LJc~TF)IwT-qTPv_l$lZpt6LNnXCwE&^2IOuB0pvCa?I8lF zGuxNHPk%BmXsbXfrmbq8VeaQ)Qc2^wn`*_(uDh`^(^hO_rn_LKg)-eZIkp(jKD^Jc_>lLRS)jVhF5fHF#C9qA%y$WgPTH39O%7ENO2q3pX7zPnQKHHbS zPk%cvXsbXfrmbq8VeaQ)Qc2^wn`*_(uDh`^(^hO_rdP*I3uV^il)IL8BTyMoW-SPy zj6ql%B7inz`|_0ePAHQ++wSF9Q8mvn+itAPLzc#MH@ULA?#5~s*WKjG?z$VRLf0$K zuWHhA=2rm$$2S7UC0I5l*&3(75MXX=oKl3; z+AE`%vb*las?ha{LrRT$&X5uiaC{qZTtaF) zl3haT2k^PcR_p&z8HCjK5D-!ZVF!rTklGOy-j6z@c7gzN<8ew6Qa|MjDb>6gLn`4x zCyndwFeqkr-Hm1EWlq=KVUXQ*H&%tNR~%Am)N_WEfPmwBfa4NUdy(v}klGuSK}hWb z0U>1&_JwE-sR^j?e%2v15dzE|h*OG?`XygTspicXQVFR(jqC0(C}wuujb-O$PS@RG zkll4RR)wxt98zl3bB2_Ffa6oaaS5quB)f#vui$f&yVSv`3_|J<2nZ>Ia41A;NF9a> z?>8M%(;>jzESyq=)bII1N;PlBkV;7PXAE`%vb*las?ha{LrRT$&X5uiaQqB#TtezBl3haT zFYvj^UFvL91|fA01ca19I2WQdq|QTy_qPtI^C7_8WjLh>sekf?lxp6LA(fEo)41*q zgJNda-B@;B=5*a12H9PAV^!#S#UZ6eJ!eP>2snN@I4&V|CCTmzsjE;Kgw)j#5K;!= z8i>}Ax)v4QzdEF@g8*|k;#4lA@L}$M`9exHZ^n>n&pEgM(w?%NJh^Tz>7FM~uA_P5 zmjJ{EjP^|!ZJFF#IP5aHRdZtb@>Wy^lY1KkOs+w=9inw|??8pu0$`lgJ0ak7H%=)g zwpoe-gk8iOOJdpMrqNH3&~bv`+3bsPNk8$$b_A%)Nk9ipg!8Z*o=h`7^o7cEyvcn&+Hc z0l{d$h|!kGeVM~9liMynxv!uynA}$(U~&z@YY?rI`#LJT_Ih&PfB~mA0>al2ar%Mn z%fI2#H6IOB^Z7%AG_Jd8P|WPQ8_WLCl)&ILuDi*nT~7`Gck_z>=yP9fcwX>bMgTPZ z5i}LP|4hCL-@C>6{tGGtzW)jVd^ZTcL9`~v-%;UpC%<9m4+uE@gHwvA=#eifRP$zx ziiE8MWjmQ0ZYDFY;nm?ZAZ~(1K;{Km#2w7uznDECOVtvFESBWh0+j(-T0#I>3_>+T z0JUTL^2xDhJ{qXz^M?j$TzAu;nAvqVmOVKpFgT6tZt`i@lLNrrJV$a=e$NZO3leDB z9yArccO+k3$*~hE1HN~L0KOZ9E)cEBu`4RPg>-W41_9<4!YM^mESxVYRP$zxiiG>F zvYpHgH)TLZWP00DeA2unh=CdZ{v;Vnvj!;S|5r&^p+L`9!`QK6bQV^k#E zca`mAZn&AO7kz0!+ysk&%nP!JJD9y?F?&Lmp`1ona$Fvj0a;dn0J0c_6(Is>7~7Xm zj*I1^foeW~XpqKrHw}uJU3X*IlVbvd)41*?pLRVt0Nl-UBuC}8Kb50p`Zwlp-qn=Zgx}ycwe+A>pQR-Oc1;X4l45)imN9xlrW?MdHdgqDnt&|atvMrdyc7$JkO4@Bz- z?TZR;DLq0HAi&&2oKlRCmv4kr^PD3jAaHpST$T}#wP zPq_DF9(6ZXg{~*3WykOO@@IjS>&YSIXx{inpn!nm4dA$h)C`hcLaH_%QZrE*gwzob z5K;!=NQl;unuQ8)SshYGL4dgva7qzU%jF9x)jR_)9q*xFwC$6duqI05x;qStnO%2d zHH+)+Fv#w@8>>RsD-J0&>N!J7K)~@6!Ep(xlSy`0NS%VpAf!%(fRHi>r$Mxa)aj`3 zhU$L+UbAcq{6Vx*P(`U58VO zkXk8UNU7${7*Yv$sWh&;!=RYibvKrsmpNT`he3AN-B=a6UU5jNQO_At0s@X-4~|Pn z-AJ;#Lh2?|1|fAb1ca19xCNp$q;5rpx3UhY+aSPP38xexwMxE_Qq7w&q!Lnn8rR)n zP|WPQ8_UkioUXgWK)XI4_VHxQK(4z%F5&XMWSMYzRS>Dk?O_fo11{eO0bDi+_d~RD z`2kdTMa|_0A;8>YIHln7uzXxr&6|u&xPGrR7_vU547>j_*|uFnT9i(!!K zaga;6{3KcC;__3d47mI>1aR3PJOk0na2H7!tUHZOeyzd{PGU)q95YTsn@G(RHeZuzT`#vIH-&ONGeaH8n1q3dC z3YVqtpVN2g`&#k7e}T%N?_WYd-wnc75CQZx+n4YA+WGpfn&;^|_SFRhE`I};rSIR- zcj@~&@xFhL%AoIaA)xOD;RlES`jPF+_kG=beOJx%^u1NzqJY5VpWw3e{TKQ!eXo!A z{Z~{5eg6#t`fd<@hiJVU{DBH@J@yrL{)B+jKRA^eA+U0N8KH_l@leg1ab=V6o!&IA zCoB&#yY9xauWS-l>0%p`^e-k!I8oKtaAJcvCt9E~;6zIZ;DkY_hG^wP4Jy11H78m@ zfVs9fmE#1Wb)$ToP|fELC(^j?o=4sD46eJe?3_rTv$&2)YKKV@PITaGNuC%P=R`+T z2At>w0h}-hogrE|(FGOW#+nmdA;4S@oXT+md18}%oKVd(46I`b>HHWcVPMm^?w&{8 z^9-)LvFw~k$P?l^CaEVTNjR}EXG=ISD$a>TP#JKd7X)y^AoPZ4<;0?>@HW+)=mP=f zmcXeTCy*yL%f|`TJj1}wLr$b|-93-G=NVjgW7#>8Kxc6slhhZJB%J8a*%D4{9_PdW zR0fQz^NQ3kSDgu#|hOu!@$l%PNZ?&J&(HQ8C-W`**TH0 zo)FhDNo!(~gcECVwuBSg#yPPzDg#ce0|A^c2p_6I4RI>R3FL|Y z<>Q2Eo?&3;At%zf?w&{8^9-)LvFw~k$P?l^CTSx~l5k>U&X#au`#2{yL1n;+Q4qih zgRm(?DQHv@Haf+X1I?BZN%4vy4#1J2%aC)UoW42ZQ0 z1Q5$0>?%OFgGXeHKusPM*XVoinsa|hy-f>?Xx zBbI7De~6XFbvGG`nO%2d*@=~qv6Stc#1at9^i<5W5NjHzT!^)2oLC2=G9cC=5I`)0 za41A8u?|Cpx0fc?bOl!+B+YyRP*^mtTe8>$xzJfx*N+*tb~lEZ097FfMBMN zz)TCVW^u}eSo_3@brdQCV$FsCVi|;^AzF!b3@W^RHL;F`0COkel!90j@)1ilpFhM( zVoi(_>r_+*#5xTEh-DB?hiE0%8L03k zX=0rT0p`xdDFw0i%SSBLeEtwCjq7eQ6f?W-#`_KBbI7De~6XFbvGG`nO%2d z*@=~KD^#{~5=%fZ(^p}pg;>{c%7s`5#EEq+Dg$C&2LZ$~2-icj66*$3cn4}?-3S5Z zZpA4Dv8LuDmTEqKh?T~5HyMhVU3X*IiItGCl?# zfLM1y0I>{038Ix)cca3aripbA1em)Yrxe6GI3KZ8^Z7%pG_JeJP|WPQ8_Q0tgxz0d zJ14OO1T*~rW?G2#5T{&-bx53852G?5)*}!=EQ9bUL@Ti#Lxp#!Cf4H+VD4$0QV{E~ ze8f`C=MS;cxb7xHF|+G#EIY9h{#K5%os(Dsf|-5>GcCk=j#DngnjRuxd>GrR7_vJ)#IV=3D?i6tPI z={GRbLaetqA3{fY|jXico&Ai&&TIHe%gG5Lt4n$I6%rE%R&hGJ&d z-B@;FCEN;??VQ9C5X|)7m}w!_znpR**0FJ7{fEkcSXKRmSO%d5L@TjcqQW~)6RR2m z%(cNO1+k9LM=aHR{tzpT>uxd>GrR7_vJ)%eR;X;}B$j|+rrTnsg;?!57BJ z%79oMAs}NJgia8x#OjO+??g?kE)Za@2Tm!7by7ZJspj*CSZQ2$lcAW|bvKrsSP2DG_m?XfVsXnr6AU+ z`G}>O&mUr?aotUZVrJLfSec2XZ097FfMBNkVWx#x132YEtkdGe8i>k(Sc4#dSO#G* zL@TihsPInL#99&p%q@dc3Sym+k65bt{2^8v*WF|&W_I0;WhYj`tx(y{Nh|@uOb@|K z3$d2vlnb%Wj1y})R0hNv3IW722+KpX5^DuicxP#1tq1|;R>dg=vChs%EY*De5G#%A zZZZ@zyY9xa6D#3XsBGsXmVjWUie!Si?~n5NkCEAeKS!AzF#GIx4(# zHL=!!0CQ{Ol!932yKo zW@0JZIf*48nCVS1(?YDxIpspEi{ixE0+j)=MneFx48jWk9SQ zA%Iv0VJC=IVvR$EcbO*E&JbX3cbrlX>+*cWQqAWNvC_EiCPOi^>uxMNu@Y{D%63j- z2?%C-JZ4&mwI`=sh;>DrSbL!|AlBXxKrDl>4@4`m_CPSI3EUASwf5O@#nr8H9r% zT8T9c72Y+PSO-IZx#>8iAl9|{h^3m(A7Z6(-A#sKX4lz%t?VQ9C5X|&(m}w!_37m2v){SvuorubSSSLXMu?)h=5Us>I z1r^>+npmeofVneqND_MP)#&^B{m&2H|{&R$^U%3h!1;tP3H)+@(0BAl7a9h^3m(A7Z6(-A#sK zX4l=G&eHmt2h;;?0T!?jhoLK*lxbu#;tEk#=LT}PSQA83F+NL*Q z3xqBpL_m;^RHZisL3$(zp(`LDAYFQs-g^^}-a&c?=}qeQ%$nJAzu(=n=FFVQ{hfc9 zysW#{diPn++WXv+n{x|QiMrg%A^IX%go3HtZUj}T~5%0bp-;jnhIAUgJ4}npt{z9bv1%^ z*K;I*bzK=)HoZ4srC8TtsI#r>wZdRU9)-4dAy`s`N#DSv1+1IQ$OWwH+hE;H(1Udg z0|QiMt0 z!=weQd(FrNtee_k-AB-abw2{InhO6$2ElrOKy|YN>p=wV9_2^?>y|RGYkqcP2w!wOmpa<(I1Yk84o<;`2dWJxCn*-}v z1npknNC4~hGO%oVZ@@~iuES7gTi0ua!J6Lu@9@{LZ0|y_qzIFKkx2_!FPo7ISa-C+ zdWE0|>s16`H5Fb%2ElrrKy{}B>kS0$-r-09>#j1eYq|3o0qfp2SYHwJV111Mtfs;@$RJqX z5~%KTV10+6-T1R6fpvcwST?;kV5L~sVW_jM>$SpQMebO(cOh6(gh@}pqy?;r%*X|- zf49M!n4kx15(Hp16(&Un!J3Rf^?(Cwas=(B;z+n-Jy-^oP45j@Db{ru>TK(Jt!%Jt z??SMo2$PLePUX9RjeL3ezKlV9h|Fdf0(ABZ786sJm2zs#QMF3V)VLoIKtoaF4Pdcy`K+tXxjs&otDg(==_XeyK>pBc|wspN$7_7)0 z%l0k=ONub*MVYjKwU`;Xfc116ti=g>uxbQgH5Gn>41%=;f$A9t){+R?EyK|XEdF(b zXUo8{>Ae9f#kvlIyYdX{daW>6kstK4*5hD}Z>nB9?E1lj#*VpY_&Vl4qxdiXR+;-f z?^1+GFUzC_tmVzf1+3@VV68yVgS8?8u$l@#MFzoIi9q!q2iD36+O5Ws0M_$mVA=GH z>5RkQ^PXZ|hoR24uGh*2%l0k=ONub*QA}FETHTCXz|QiMsb&!h#c4b8{}te4wh zZA8$6wJ`#)nhL){2Ep2dK=q0PYf}X6w&X|v>(w%_YMgUe*;g855SO*ZO-gRJ&LD24Cjs&p&TLzX*?+sWf z)^!-_Z0mZhFj$d0mhD{#mK0&qW0|yob*LG+fc0J*tiuR;untE6R#V{!WDu+)2~_Vp zu#Q5|?ih{)us$dQ%cl1RtQ6}y40X13y;c~k$Q{e}E(A-8FzI8Nw19P-8M%PRD z33{+jKmb-#;cv(wSSJ#wK5}54grME290_23Tn3g+?+sWf)^!-_Z0mZhY_M$aLa?L= zlRk|}3s`5EkqcO#w81))pa<(L1Yk84{(%gFbvA+OQwP>L2-;o1kpR|bWnkI#-hh>2 zU5BC0wyxI-gB5uc+TMj=Nf9P}A(IxcE;b_)1mw{!|djnRAbsdH}+qzyW3|8chWqTKb zB}JI@9ZXuly334Q!1|^Q*4+d>Soa_RtEuoWWDu--2~^)Yu|QiMrA#H0nRN6g3ttU)&o9yIR(V?LN-(86QK+&FACKI&0| z9<0X@fYnrZ92o@b2?Et%iW#DwL~uOIkpR|sCTota|FLnK-W#w|tm`n;+1B-1*~DkpR|&WnkI# z-hh>2U5BC0wyxI-gB5v?WqTKbB}JI@n@n23dfSX#z?!HH);k0}SnnbLtEuo`WDu

      |QiMr=!lVVP&&njB9zT-#$Yw|L%Yw2v)SdmAe?Oh0#6k*a+Flo7CO=(6hcdV(}U`<8PgEch*u$l_fAcJ5{ zOQ4$Cfi(m{yBRqWz?!BEESugNuu`n+Fx1)B^;%)DB6lp?yAUiX!lb{?qy?;*%*X|- zY1?4^ke~-^W&~h06@G*af;9_)YKQ}CD1vq)I68sFk0wu729{0l4Ol7Gbr{^0XIR&3 zWrJm{$HD6OqsdZ)NzcZl1*|#D$OWwF+hEN}(1SG>0Z|Yhg2T0qgs1uofZc!CDjn zSWSf=BZFWqMxgqE18Z>v?Uv+70Bfc)uxxs7z)G>M!%$~i*K1{iWqTKbB}JI@QcPOF zTH1_U!1`eutYrv#u$DytR#Ra)WDu<72~;yXuvS3OZe@-HuzpkqmQC*sSSi+Z80u{6 zdaZ1*Z0|y_qzIEmBLJ(ZumLg%)`kSC;SQ{g5VYHrBLS=tWnkI#jOmQS_gE>`br|Yw>w2v)Sdri8 zXL}cdB}JI@W=vYZ+QN)nz?!WM)|Lc4SieR9R#V|O$RJo-5vXQ&U~P?{-S!*_V9ikm zmQC*sSSi+Z80u{6daW>6kvo>{T?m#GVbVJ=X#r~|GjaiI&Nf&(6ZBy1f&i?h!f%m5 zuzp9Nn#+N;D}r`=a3p|Lm4Ri`djnRAbsdH}+qzyW3|8chWqTKbB}JI@ADFa&wU-&W zfHij;ti1_(u=YU!R#RbLWDuuQ zP45j@Db{ru>TK(JtuR=TN1^Rq2$mFK(tl>s0@l%H&A$boe{f_5iyB!IPW8CW*GH(;e$*I}r$t?RYIU_~B|QiMsL%%laZQ_RQ( ztVP;jol4Mybs7S&nhK{QgJ7LOpjy;{btZy#=Wrx|_2V+IYM!%$~i*K1{iWqTKbB}JI@ElgU#y3LGSz*?#e z*6jp6Sa%=*tEq4&G6>dP1gen^th*7kyN@FQtfkAqvgy46E5*7FL!E71uN4L>@*d0f zE(A-8FzNf5w1D-18M%P9OdG5R33{*|LI74%;bCMDtVak`%Q~ z_XeyK>pBc|wspN$HdwZIAy`s`Nk7G;1*~Vx$OWwB+h9FQ(1Z0H03P>VEwcW z)*A#pSZ^W#tEuo7G6>e&1ge!BSnnWc_dZ7gSSy!-Wz%~DR*H2UhC182UMmb%pBc|wspN$7_7)0%l0k=ONub*ubH%f^{pAXfVEm1tnUbVum+6~u$l^kkwLJ= zBT$WUV2zKU-NYQ7z~V=fe_jTbP45j@Db{ru+?8io*K1{iWv$1->iDC{QiMrQ!lVVP z$;`+Ftkv6KO-|5*H3fn@R#V}7$RJo#5~$X2U`>Uf-4Kohu+}UC%cf^cXB__6Op0|K zhC182UMm|c+q)1fDZ-?uW6}cF3})m4)-T#%%}CIL^?d|jH5Gn<41zTifod%W)(;W1 z8_JOY*4kxY+4SCkm113oq0Y9h*UARV_AUfViZJP6Oj^JiZbmL({jv?#2!bB0*${x$ zRG1wZ1Zxfg)jAHWIT5s*ha&;3b<4oA>Ae9f#kvkdoo!vOl?|5dT?m#GVbb$5X#s0~ zGjaiIy*5}25cFUzhybjn!a~R(SPK)V)^}hnf}q{v9G$@8N0T=w1IwoO2CNk8It=d0 zGpy^i!e9+E|2zCItXk`FusZ%|vJ_#`HIo*wmM|k1ur_RiwIo3g)=~(-YATFG2EkgI zK(&zrYZ(OXR^UhgYvVGoYcg0(7vY7+<6Y6#k`!I1#gre$E+^xlA#VqJ%!&bF@C3WGJB ze#f%C3&D~iOnOZwEnux>MlN7&)&^^Bf*!12A^@wYunsZ^*180$%^g_lA!xS|M*>(| zl!0Z_djnRAbsdH}+qzyW8!X$q5G*Oeq&H^L0@fyG z@+h>u3&D~iOnNsaEnw|#MlN7&+Xib7f*!0tAONeWuqQGI)?Ngv?HpKpBWSljM*>*e zmw{!|djnRAbsdH}+qzyW3|8chWqTKbB}JI@XeKRS9biT-VC~QbYYagT)`1AXYAXB* z83gMf0@aQVtb-A>JB%X%tewihvgy46E5*7FL!E71uaym!?Oh0#6k*bbGid?qNHcN) zYv(ptM-lX3{TTsRO@+T8gJ2y^pxVWObqs=b$8#ir_1iMAYl6ajt`4kI5wts#BLS@4 z%D}Sey#Xu5x(-8~ZC$Sw1}pL?w7m<#k|Ip{EG8{rooz-gVEw)g);R<{Smz=DtEq4v zG6>fB1ghN~SQj8@cL_%VSbLO#Wz%~DR*H2UhC182UMmb%tg8rAdpfYLM$qnhjs&pwDg(==_XeyK>pBc|wspN$ zHdwZIAy`s`N#DSv1+1IQ$OWvu+hE;H(1Udg0|QiMt0!=weQd(FrNto_p=wV9_2^?Yjhb{HoZ4srC8TtsI#r>wZdRU9)-4dAy`s`Nk7J<1*|8` z$OWuFw!wOmpa<(I1Yk84o<;`2dWJxCfCKAU1npknNC0b08CW*GH(;e$*I}r$t?RYI zU`6g&ws#>|QiMsr$fO0Vm(9optOMI%y+Y7~^(q3enhLKWgJ8W*p!$;o>kS0$-r?v3 z7C)MNP#IV@y*FT`Sl3~2SDs;Auaym!wH^nnK0y!G z2MEAwDtw3xg7p!BYODk6V+8F!=STqSkTS4rdd74HnIT*|?E1lj#*VpY_&Vl4qxkPv zvyTc-XA1fF`Q_uU8o@_CEFb^m@KJS&bsYwmo?%_D6}BF^V_EBkU`Y`s{RNX2u)Z`S z7qAX(gY^|b57yTRz-lUdgA9W8ErIGV2iA88+KoS35?F_qfo0P(rZWz~O0llPP-k1$ zYh{CFdl!NwMVRyiOj^L2$c$XTI-(8M!~{K9lOO=AsW2%r2-ai-sv{j(lOt$16-UAy z>!>oYYsW3e< z2-XY)s=qj}W<=0#7LEk4jxGbsrVk)klj)Db6ze(+b+&cARv4^8>-vu-=Udlng{?>4 zfY_Jqymf9oVA=%-jsA98D4TBG8^?~hbHt$04@?7~2Q9ao{`SyWziyoy$Nq81pwWYe zWTf9YV$>ogYp5*(<3nLwR%%uQyR6hP?Ufo%(67`81S=(1L510n!IhewKy|EJsW}jQ z@O&HzEA`j1m9psrxKh*TE0tnhUxPZ^x?U^HWubL_4f3t)wZhgTD`j7{u2;&Y7p{~P zf${laTvlp91G~0T3la1ywJ?H}YAP&(46f9o1ghiQO8po?yQMf1R_ge&m9psrxKj3p z7yN`R#k#%*b+&cAR+!5|>-rkxTi0uatw&bMzHD8ulua*ODJcTuBVk-tY8eB&wo=Oy z^eeR-f|Y72ERPJX)CvTu6WmIzh@jnS90@D+x3ZP8=>xb@6PTHY|6*5)b$t!$Z0mZh zFqeha^)<-1uGb1%kF1n^*}7gSn_jq5QUu0F!MLo{>IQagrPd(mS87cJE7er^1v0o& zYZ0hUbSt$sf_58nB&^g)Wh-UV2XLh(*H# zgMnRE>J)gM_kb}UOfhKTv14u=wi+L`BSF7XJ0V!9rozt1;7aX6pgPs9)Nc_K`U6M8 zN}X1=QZ{`6S1R&3eu{N{4eD&`daW>*h1T^o$hWT73R{n?lzrK{UMZVixKdIC#`lDA zS*g7Z?Al80L(s3(z6e&Tsjwe1xKjHQs7`k)H5x&?gEWs3Lvgrf3QjvF0Dc1Eh zsI#r>wZdE$TG!Vg-@0BaY(274_GRmOrEGfPN=XqI9}DBMQimGYWu?x9=YCJA!wCA7 zIvl}DH5HCP23P7x0@Yb=rH(?-?l_KwmHJ27O4;-QT&c*H%~GuEYfxuf*K38jEVQn# zLB4gpR@i!ErR>Yr^-9_F!j+ODFn&CY%S!#tz^*-|P9*48>Ldg!)l@hc8CIMYu?&RpSQWFlXFDP3nn?8Um6}i=?Sl8FUU3rFe zy;e4tDc1Eh$hWT73R{od4XpL9SIVXru2hN#3r^^Vz}?Fi_n@Tr{ZN#6V9)Mi&t$Fd zF$*VaeIYy5@AJ8T5%g<)FM_phD%^(*uJ!!{s*BuO{~JNOM>smIHNOJ&;*5h0%>3v*^2S9lgP=w3J4Kc#yC2cOB zAn3V#5&@S@g{P1~E}te)UFx`e20^=5I6863$eG1m%Fuo2f+t_z|m=~dE8u4 zw$?U1V>ia(TBlgoSJ7R0hIPGGcsC-C8*4qj8~Q3b>v1lX^gb@d1E72eD8l8(h8W@U z$~Kpu5cFJrih#?e!e_`Jm!A`;u5w&{fuP;s**kN|-A<13}4_pMZl2jzK@>Oo2G=Yc&N zk3EyMp1>@e_PCjlpkM2W5UjOa1r;Vn2G@EL0@XEcttUnB!BcW1JZ`QnTWg!1u^Z!X zty8S)t5|1S*K37$Bl5Vhz2m!~ucEUa-wh?bk4y0YC{qE7a5;@3Mtj^$OVD#U1Ob;# zh3Sw%E~h6@UFW!*0YST=9G$r2adUkcmo|L>xwLB^{Ol&hy3Ufj@(k;Gt!yq+tSexd z`(^g4uGb1%k34Q{@Ayh7&x=0m@s(22`&KH&gYvvc^`NBp^T3`BW6xx*hnt0ywZ4I! z>i5O85d{5O&xT;F-s9XE6=d5*9z}O}ENFeyx{Bu-0-FR9FEST}bpP~GL$dP@W!ybVXEwdQeiciCFo^o-pYhijc;U0+3a^jz+UfXk-BPRJmaI}@nxaa`_# zpxvGvow($2^RF^4ZF-gsnfqn-tFG4yTaP?$ zZ14C=DbI^O>+zLR()(5_#e?#^NcEtk_w&G>?ZuwSTJK{PPS*NfcBb5vmW0KCB2VJ@c<|X1B!5Yh#^L}{CAtnLkW5=4@1CZQ{ixAkjopDyB$}_C%wX(TPv95q+?w8rGx?U@6z2mDM zUn%8z(PurrQc8N?O4;j=dr+PisUDQ{ejeDf6WB9Z>l4kwX^)$e2>P`?8Npi1RZ!vY z$lzL^LZEuct@Wu0KKLw-PHWBM=Harnw&@wWF%H){#k#(V?#eT)>$SqW5qaEL>v1mi zRdm+lyP>4_aVZ`EconwdQg2MA=%~^o-pYhijc;U0+3a-gsnfqn-tFG4yTkrU)$5%>uUi4Xy zuauJBw^H`{;~tdfMXCoSy`Km6>@oIC*7^yvaN6VMNrHZ@pF*(Kaurl~8W~*cX9!f! zxV3&3!3V#{(P^!D+&o*h);2w3H^$*wr&!ll(Or3lb-h-2HzJQ4Ydy}TzKYIzd^eQz zJ}$)rpu7Yq!sRQ580~TMDnZZXYY4b(D!h&ia`^^<>N&^dn+V!{$kB;Q9yk9f@w=^48*4%a%xy1t6;$}_C%wZgj*dE8j*@!il@(OHl0hLYaLrFa08 z?*K)(96U$E`u$>ZjgGA?a;#&C1F zw6~t%7t>O#>nyn|&#3T^ zD9?*j4@!DJ5A500?3t|fv}WPtaTEBh0z(M;wVn>aTFX^XVR~e6t!E%mz3SF_Mg$)` zGe@Vj=5g~{*;?E5jNKTAYn@_UUqyH28P@e$;oXQlZmjkAZs@D%tjBjlN$=xQJOIj% z07bYQYKRdo1HV;Z7(vhFtO&SlDhx*kxg0^Ddfjn38-jN8adhI6$ITmMT-x-E;pTE_ z*FN~TNwKc8HR#gXY;dXvepZlh0`843la2dy)c5cmaCw`BFNxcFG`?#)2;Q75q$6x9G%vh z$IV-1Yi-jrc4Hi_b&7R;72TC*Sl4TXcO&w+vDV|ep|7H|9^VZmy^l-r04PfWif}p7 z5TiYAmL}-ATm}J`O@(EVK`xggP`&NATpmHY)i^qF$>ZjoGA?a;#&C1FjNJHAtm`bf zE6=d5*UIKH#kvBPxnE|#>UyoP^^UK4e5I7B8qQUp+T1r*`(_l6kZ^5Zs_yA$+W?ty^I zrotbPK`!?sP<`UK+zUaw{W%i2{IrZqo8B8PQ>^PO)!EkdTG?FM-d%HP(+jzjB7ia) zP=w0^3^BsxXKgOW5cFIgh=9wc!k>^qE)OD5eeSqC7(u(kITE=1qKr$MK7d?CK7mQG zuCr8UTi0u4b7^~b&81B*w2whE^Y6wxwPqpTuKo@IT28V%aaW;!sS;$ z(eM4`-wApyPeH(CQ{hx(kjv8uR9`zTPe;)1Y>osjzbWI=rVk*Ok^5zeb)BU;+qzyW zn@iifYc6eiA(v7FP|g7q;qp8~jK<~p1U;7*AmFm8a3M0t0jHaZTbLm8F`MUSl3y~x31U9=F(d4noFBr$fXnklv@EsxV+sEBV3N(=JF1L zp36HCaM@J23mN3{ZUWT=j>~%xwEH(l0+$n(acR>Bkjuz(JjJ@sQk`vGua(WE?cFt( zHocHbDFP@D0E%$=kRe9n@?nCW%SRA!*;IHG8RYUY0@Xy0%f}J4dxj%{%ZbalwCMxL zW#oRDVqIsc&bF@C%I4Dc?wU)RUdW{s0hDI}MY#NrAx5~I1StA_-t#;`&*cjUxNIuC zhzxT15`k(`$K}fi+P%S%z~y9RT-x*jO z0w`|+ig5Y1Ax5~Iyv^l11U;AUBH*&A@Lyz*%l8OWQ#dZ)N6_vQjsz~hSH`7HA3!c6 z|8`S~b)BU;+qzyWn@iifYc6eiA(v7FP(B3|;qr4sjK<{`1U;AkL%?NI;Y(zY%dZGj zQ#vlcM$m5XoJm|xRmP=FA3!c6&+!!NI!kr7b-h+Lm$rA;T-x+PE~N;dj0Y&frmEeyfuc#3tM zr8?WXUMrhR+q-KnZF(V>QUp+@0uxs3eU_!R3pOLew&y;e4tws+TD+Vny$r3j$R3@F0oEQT13%b^54 zm%|Wn*;JSn8RT*}fogik

      1r=Hf`;a)vT4ZTbLm8F`MUSl3yqv#sm3vbnUqyXMlS z7jh{@0Hp#H;c^~BjBq(4Q1p9_&r8sAIUfQpn+o$IgIq2^p!&Y!azO;`e$0`;TK(Jt!yrB@24jWM5kOfCP=w3c5TkMV6M~-0B@l4gR9F%j zwj)l81dkqFu?&ym3856if;=>y1RgCw=G8kmm|u!wCMxLrTwdg!LJjgSl3yqv#sm3 zvbnUqyXMlS7jh{@0A)Ks5iWNy#0Zyx@AvFT&~v#H0xp{hJ0pW!?n0oN&2jl#1nqX` zNZ@kzGA?cU0CE|5f0<%kXQ|G%uGh-u()R9}OPgNEr4#{_Jpe_x+|v-Fak&>k&*k0- zxNIuygA8)HFM(nyn|&#(=Jy(8zv_CeF0Eg-&W#5x|NB9sCmjN1tsmG`ey;=8 z&5!d=?iwXMSUV>n_VuK2oB7?*ICxL1~ zH{8n*eDIYV3Bz5eY`8Xk0EZj7;o06@57(xb40pkywG`pizKT~{hI@^9*|p(bOVAJZ zIt0UQDqN4G&`lqZk8P2%vDx(AjLr7$ zdTchmWNh3@r3kO~J-pg7wtLOXu8r+Jf_`lGBN$s#;or#Mt@Hr`)uQfJ`XGXKk8^Yy zE}u{RxNNvKeE^3Wc}}KS*Wd5CE6=d5*9yM@E3~e^-^;hI*Xq)G$$LjWpOVo5=@URI zJMomERd!-Afb947;%S0@C!RsD6HSF@k-?pKjzG1z+ll`mX!i<7!cNp>J7Lo^z#502 zPo-GbIj*y<>$SpQMcx^uSl2nux31Uf(t62G@cEQnKajo(q_PvQ8(OuUc!Qwdi8m4K zL{s4{WN;_mCQ$vv?Zi6>+P%loX(z@TS}#$y6E=MScOvrhtSQ!Yj@^}KSl4TX!Rln4 zA-&I#gozK$w1kNz8A!kT$Sp6bh6HnzGO(k#Mfq8!o<>TCcYu)nfMj~6XKo<-ywrc z44MljmT^oBM)1KCb97>Y_mj((F=5jOkcr5fGTS?T7uV1lk1d$qaS^_i}BxCnxCPo&o{fO@;3vDKw4A z@9;S;*e+j&txeAuTkfqaGB(@05ZjdN*HLpXU&i(8wX(4l>r8rDCN0QJXGSi_tk6bg zdV(IA84w`TRG1M-p;=6RXJl3^L&m0Oykz4LnH1~#ovzNduGh+*c8YZ!u6*lytuC#1 zeSfuAUU+|%A}~G_#${P%HL%OF{ItC+!wLFj8G&F~nhLWagKr*YCs3_qmV-WXAUNjb zNLZJI*=|sw2y1 zX{T7%;mWtJ*Xq)G*Y{U@<%RcGDFWjw!niEUN(OfA&BMwB{j#irU|E_9KSKuJJgiEf zTGhRISPenDUvMO>)M{lbWzz?6r6Qlg+1@30VZNu5a{W4xE{ zgje71G%VMv*a9N}XjBg6#vMie$*kxH(Z!gOh1pTsX ziC|fp3cp4Mp9H@lP_1E>gFag!ICkJjSgAG3R?4Oi;7Uc_kK5iQPXa!TOu2p?NSB^* z{d%o1+#RpKYq;%|7s4$?plwHJ6S#La*lACKT?l%(e~SR_ro!)#6x!3|cYYH5q6}M` zo-wxECqZOvDc1G7cb#orua!+)igg|EeCv9xF0FUHEcVI^mqm)e_+BtB%d(GwU3(Jj zOVBUNeh8MOsjxpX_#_xjpjyj43I2$n-9a3kR*IiEUAt_hZ2ADMRODO#Dc1Eha95sT zU9T19ve3G|2F`l?8K|ev5l_@F)6oK42LqR|e2Ae;SpFp-_4^dyP=cQ2!w|46L!-js z$RNu{5UAF1EFX#Bga5*j!1B6fEZg)9AaWlMksn#Gz2i43eWJBZkKd@2^uF&bOA%h} zqj|MuxW}58U52|}d$@lk=!bh8g5fq5jzyR#@6B*+ z@2-by(+h_yMR>LU&Z{lMJ=MJIGTaT@!#$0lAMWW0hTBv)0~s9dnFOkh+;GoA(C!?L zgyC*nHe8!NfWwX4%5CqihilUdhbu*Rwa?|%mf@anUUnJouiC@CfS@1lg$Rb*RJaHk z9PY&gs!iN*FG0}mGLD4dZdx{6o8Ft@+TL9c*QOT^SBmgzU(Ty7!@bhH>@wWV+QYqy zpdaql2!`8KxCR*u-kYZ0mZh@cYL? z>&o-q{B3h2#bKNV?M zw(0SEtdidM);Gn2{WAam`)ivQ4Ijl{-c0qNr1$dxtPcXK?8d`}TG@@Q+Pm=xLBAW1 zBG?VN3MxE?4DQC`1gfpwZajhDgP-Q;v>SY#V4Jetu<56ShHKM% zGhExd>*3n;!r@90UhUU-wPm<(n3r9KyF+`pZxZyweG9>Gn+k6ugTsA?K((VA?z@Oi zQyo0C-btn!f6D7$!Z1Ir&);g2B3#>l=_%LtzG*JkwsZU1J|O6??L!3D)>QZi8N9ZS z2~@kdYx@L2yDvC8T_Sg--^wL+{cla$^bBzImn;0(i+pR?_Kr_Se}mxuE=9`qEB7Yz z+{(Uwy;gVE&!qpyqy?<6%*X|--?hQ|nxF^k8w6m9dn$a341)C?fofL=)}Ttjnt&q# ztli4Mvgrc|R^hu zEV+0pOoj}CH93Lm_YSNn5Pa~|90_3UUIvy;&v;?S;T_BNE&+?5!AiM)9R`=4as7I& zFj$d0wpeG<(=cfPYls=SfVBrx?f1=(=?HqTrbhr)Q(*>V5Ud#qRDW<_eIG%)nK=@` z+OrHSo1XE)=7JU3SlhbAj&o z#kx*voo!vOl})|v-8J<#Jx*Ll>Qg)@*c$3nJSgdo`l*K6BEY&LunP4n8ES?4(QWEi zCg`bO1p)P9g9<-G2H%6MN}&3qp`4Fe4Z*P{N5XC#P_`R3eE@eO^5!nZy3TW*ZC$Sw z-i?mdj5wR#8{$%|>y*^l*7aK1#M$0);*{H|A$S3}x4pZj z-li8)pW;Em)=;0~K}qj>4UT8MYVSdIBIv2#83FZ8g=*$J$h?`!il7`Xr-JqSo;C&n6DWhV}4@5CVl z{Z1T;U?-XiharPIaX5kMP`49DAZT|CN5W1VR<;v1y*E3NVqNFB&bF@C$_6XNy3TRF zb-h-X)(dw+t{+H`1yb3G;|#5`6Nk5V;&_67Cr&`H6HSG`A%i<{B7y1%w-YBJXm=_{ zr=8#@agHq837bBEI}!QW*%a$K$L`8Atn0PHU=1_>``X|?d}^)7!O}T)H(M#fq)%hg z0@fL3s|uY-yB%?A!zp?M*>(UmVsr{ zdjnRAbsdH}+qzyW8!X$q5G*Oeq#t6^0@fpDo*+=2 z?7(^wLAz%;62SU<8CW*GH(;e$*I}r$t?RYIU_~B|QiMrA$D{?U=gr6ktW(-x zy+F`|^&$eWnhGx=gJ8W(pgPro^$LP^Z*U}lby^u%HoZ4srC8TtsI#r>wZdRU9)-4d zAy`s`Nx#XY1+2Ht$OWv^+hDyz(1Z0Z0lnpP7*hSZB4t`kbH#>k9;6H5LAc41)C~ zf$AR)tgjHX`;H?4th39&vgy46E5*7FL!E71uN4L>@=H`~??SMo2$LQ(w*zZD{$Rm6 zrw!Kl1U*<2AONeWFd;Gs)*qm4Ri`djnRAbsdH}+qzyW3|8b9 zW!T<@U`Y`sJq44NJJytDCrvqyq1nm~!NC4}yGO%oVZ@@~iuES7gTi0u4 zgJpXcf+aCa8byXXzWe9q(mPG(oQ(-w| z5Uk}1R98E&RzT2hWsU@}t|xMR1>k;%|t&ae#rosluAXpm`sBUy%ZG@oRrW^@i z-BbpaP45j@Db{ru>TK(JtuR2U5BC0wyxI-gEd44%l0k=ONub* z9hkI$wUZgSfOT6NtepvZuy#QJR#V}($RJq1BT(J$z}gi-yFEA(z`COhESugNuu`n+ zFx1)B^;%)DB6lp?yAUiX!leJeqy?;yQ4S~z`C~#ESugNuu`n+Fx1)B^;+3r+1`allI_tYZ;?)l~Q^G6>dj1giTTSjQu1cM?YeSpO~q%cl1RtQ6}y z40X13y;c~k$fMBqE(A-8FzJ(-w19Pr8M%PpBc|wspN$7_7*n(Dp6_ONub*bD6Y&b-o$7fc0=2tP2Qw zur5RZR#V|3WDu;22~>|bur5K+?sAR$`$;aX%6tm_C=k2|ogN6_wOjs&otCpBc|wspN$7_8~d{|tlJ5Cu>k*4y+dtw0ngk0jw9w zz_RJR0V~D24nv)7U9S}eD{{xOy$ivTB24;KCM{sSZbmL(z1Rlp4T2u5HxYoAe9f#kvkdoo!vOl?|5dT?m#GVbUKkX#wjaGjajz zl{Q!(6ZBwxf&i?h!l%d}Sf3H7UUgu7j-cIF90_2(RtA<$?+sWf)^!-_Z0mZhFj$dC zq3vA=mK0&qUo&X|>svE&0qgZPSl% zuxxs7z)G>M!%$~i*K38riaZK!??SMo2$PTK(JtuR=TJC^NT2$mFK($g_%0c!>` zaslhzHdr$f^k97-0a#6iA0UHZ%|xL3uLJ9c2-*$h=mZx3ipqOsVA=HEfR$ohhrwNW zhIPGG7_7(-`dRC7usZ%SLMg(ehcRgZYq%M?fc1VGtPun~ShFDjtEn(MG6>cj1gZ}l zSaTw1HxEYwSRa;wWz#dJGY)@0R*H2UhC182UMm|c+q)1fDZ-@ZWzquH{AT0=)<7R367*m#g#fIk!boHgtfdK5pEpBc|wspN$HdwZIAy`s`Nw3JH1+10K$OWt~+F-3r(1W!K0Z|(FrVm2kDn(VA=HEfR$ohhrwNWhIPGG7_7*fcWXTkR>$8#Dn*#|noL^2TFZ=F z!1}5U*4hL;SieL7R#RaeWDu-%2~=M@u+~G+ZX=Eau)Zk+%cf^cXB@uAO0llPP-k1$ zYh{CFdl!NwMVR!)Oj^L&#Ee|P`nC<$rUX4$n;`(JsjxXR2-X$^s_z_FTOw$;HAezi zgKpt>^3T!rzh7?CdjnRAbsdH}+qzyW3|8dpShjZ|SW<*ZZ^NVotnJLm1+2kLwckJ6 zusuN!)(!~3YAWoA41%>2foeR12z_=&aO}#F0M__rVA=HEfR$ohhoR24uGh*2%l0k= zONub*-I%n1wYwR)fHgrItUU;Nu>ODmtfs=A$RJpI5vV3~VC{{d-ToX2U`6k@r}(cOh6(gh`KP(gM~2X5<3a#BH#~5cFUjhybjn!k>^qunr){$o90@h@0 zu#O_=!TK`-u$l^gK?cD(nm{$V1M3(B?T+V20Bedeuxxs7z)G>M!%$~i*K38rirlem z??SMo2$Md6Nefsfnvn}w-)n<)57XBNwoyZi96WK@Zls2*7G8 zoQDj8bv}V=8VA+|2-;o3kpR}TWnkI#jOmQSFE^xE*I}r$t?RY2!Lq#z!IC0O`cft> zU|nWLE?^C5gLOGU57re3z-lU7i41~u6@h9x2iDaH+Fj3)0M_(nVA=HEfR$ohhoR24 zuGh*2%l0k=ONub*8<@0!b(0ynfHgxKteXjXux>#BR#V|tWDu;|2vjpVux>}t?rx3* zu)bdgmQC*sSSi+Z80u{6daZ1*Z0|y_qzIF~he-=q_nMIlSU+fkbss?w*8K>;YAXC2 z83gMA0@X|otOpUadz7OSSbR(8hh<>d^xlA#VqJ&9U3rFey;c~k$loip*5hDx{FaUs zVbYH=X#wjAGjaiI<~CSQ67*m_g#fIk!qdngSkDlse&oP<7D2lgI1<2`r3@^ao-v(q z_#P|8x(-8~ZC$UG4VLX)2$mFK(l0V;0qbQmasg{-8?09ddazza09I4sHDnO1*9la^ z99VB4X!j0B0$8(_fo0Qs16GQ49fmsFx?U>`R^+eP+uns>Nf9RfE|V6p-ZLW?u!gt6 zdY_;N>jMN}H5EQY2EqD>KsCaF^)Z5WpK~ODHCq{2HoZ4srC8TtsI#r>wX(soy$ivT zB24-VCM{rnX+|z!&E5vT) z4y?%$w3~_};f^(T8CW*GH(;e$*I}r$t?RYIU_~B|QiMrQ&7=jaY0bz5ta;jC z4I${knhpV2O@--^L9k{ZP|fSWnh`;}A95ssHD4K6HoZ4srC8TtsI#r>wZdRU?pU^W zAy`s`Nzcrr1*}=j$OWwV+h7eP=)oF>0Ia6MtjHi(!wFOiIIu<_Xg4QEC$RXI&VprN z+4SCkm113o!CiTVb-h+LSk`(Rtd8H(ks?fbE+#Et&22_5U@g=JYaW6gta%ZD)l`@d z83b#70@cC}tOXFXTZAJ4tVPPevgsMq8HZnPNU^TNP-k1$Yh{CFdl!NwMVR!WOj^KN z%#2*XTC@$;;siZdH3G1j3O_*x!CHbq^a2kpR|D z%D}Sey#Xu5x(-8~ZC$UG4VLX)2$mFK(xaHPfVH|Axq!7q8>}@5da%|+09I4s7sw!3 zYZ0iHbYQKGpxt^LoxtK-I!l#-Wz%~DR*H2U26yEd*7aIpu!foc9sZ4e)_NSQj^EOe zB20RHCM{rXXhtqzjckLp5kU{u#t6V_D*Or=1Zxul)zS{EO%b%)k|P1EWy-*^=^4`* zhwrgctm`n;+1B-1*9<1FEfYns^Ju(Q^?gXk89awuHXty^<0$4vS1IwoO2CNk8It+ETb-h+LShjZ| zSW<*Z@57`8to_W$1+10YVC_%PgEblfSWSgLB73s|Gt zU>#4;gLMJ|u$l^gLk7V*kwEox2i8dl+MUXg0M_bdVA=HEfR$ohhoR24uGb2K6}e;C z-i2UE5hi^alNPYfFe4YR)@XxuCP5F@SqQ*tD*OW(1nX=9)tU~ha}cz2U5CM4d4_epRyJ7HdK|2d-_nsHO!`75Enr=2MlN8j)duSlf*!0(5rEZH z_$M+5)@1~$wH;WOBWQOuM*>*CECb7?XG~`tez_sVx(-8~ZC$UG4VLX)2$mFK($_F) z0qZ(5asg|dHdxma^kCh90Ia6MjmRKaHxa1Tbzt3$pxx~p31F>P29{0l4Ol7Gbr|Yw z>w2whux#%_u%rl+zJo~%Sa+F`3s~#7!MdBE2kRaLU^Nx~g$#mqFM(?OVA=HEfR$ohhoR24uGh*2%l0k=ONub*hnTd0^@tg{fVEK@tVaoYupUDIR#V|| zWDu+;2vi$8u%1NF?s<*`uzpnrmQ5c(uqHD@3x8iE#kvkdoo!vO6$Y!&y8bPleCv9x zu=OcAz3S(!bK?QiE;wlPx6?w|bnD(YcFdh42917T8UQ_Lx!v@)htB$S>)bf@k3$BH z9y}x?{mv1i7BN{vZ4nrM0mfyeUNW%DN^R0!sh0`*m3jriO3Co4@G3I6Qm+xHHgzlY zI)V@WFGs>kZC18YHhlnBD)LL0Q>^Q2P-k1$YlXQiw63o~zIDA;*m`88?90~mO4;MQwkTUEn?8Um zWp8-%Uq5)z*fCd)SZC~*hlh{izfTSyRi{|j*TAJ`Sl4TXxh%ArA~609jLS-WXJFS>YS4WDZ>0t!SgEGMc*x*NjZdK3(yi142-;1~k+4#~ zE?X&^p221A*FYvPGY`MbEoU0bQC2>Peg)Cg9psW1&PxKh&+sD9&CY6yaMGjSxW)K+CHWzz?6r6$)` zD#g0K26eV|y;hjZLhJe(*h1T^o$hWT73R{n?lzrK{ zUMZVixKdIC#(x6ivQkSL*tL~filASqkqB0*sjxIMxKhgysCIBGwJd^mD{~~Q)Q)8< zWzz?6r6Ql>r&!n5pw70g*9vo4XkA}}eCv9xu=U7F*_W;Bm9puDDd=(g%m0H!n zuC3H+1pP{lLaTK(J ztuU8`*7Y^Wx31R;TaT=iec8HRDVtunQc?uQ*Mo6csSOP5+DdIm(67`+2v(}8urV^Y zQokZl?c!Ey69nyk!;!F3zb#uSn?8Um75N-L#k#%*b+&cAR+!5|>-rkxTi0uatw&bM zzHD8ulua*ODJcTuTfw-j)HVioZKbv)=vQhx1S{24*d7^NsT~MZzjG_KBZ79jb97p% z35V9ZmaUXcAHbE0-0D-T>ucbyJj1$PE1Sy{>-rkxTi0uatw-(#)_T_~Wz!2+D#e2Z zXPA6L^P=H=EAt}xhUQnZk8&?x+=G(d_Y)lAfj!%UJ(IQG(=42<^=|A`zb}#OMbNMH z-U!yZsjv?+xYqj;sDAI(dOrm1#&C36YyO`5?qzFj(=&Es9DZ*s#k#(V?#eT)>$SqW z5qaEL>+#*tSJ7FIbE%~FaVZ`E6YE)O!q2$y@bxjdMl=W;9pE}II6AcI^UN}&3K zB?T+Q>#3hfLJUyoP z^~mGK_KvTV{R&I)R&UeeE2X6OtyGE!<$2Nf^2I$U>HR#gXMbhSWUY@k3ny#6S9`5b zAn4cnZwS^}u7V0DB7B) zxdf{H9GB-IXm=S$CoXy1>|e&EP0tu^E|-z-V5V5tS#npNVO_74&1H&p1uS#F%zoAN zT4C#v$BpeBUn%8z(PurrQc8N?N~L&Eo)@Vel=OZc*t5&oGg<2^&BAGqo2v-=wZ0m` zTFX^X;TmLct*<3ejdp8&9fA+OnWNKM^SJqA*;?E5jNKTAYn@_UUqyH28P@e$;oXQl zZmjkAZs@D%tjBjlN$=xQJOIiqfFfMpW{A-qH@6e?T;73z%cjDe$RL+@5vUGuT;7eK z-9sFmxa4s&ri@FQo-y29F74U}Kf6h>uCwH>Jj1$PE1Sy{>k3%rewqEM>$SqxBaa)~ zJHArN^P9Jt*n@Jg{dEvuCo_kD7&(wLXxY>i5O8#|ZkhejLGC z%T-X}31o1spCnNI$*uKM2tN2f9G%vh$IU@yYi-jrc4Hi_b&7R;72TC*Sl4TXcO&w+ zvDV|ep|7H|9^VZmy^l-r04UD`ig5X&Ax5}7xXtBD1U;88BjB>B@Cq`><*Nj$v5w2v z5VU)bqZ5}rZVoBq(xzt&H6R^Ro82Utw$a= zws(A`l;=gC_4rCD>3u7e;z4;{q^Q&=&n4&x?U^18}bpu2aIF_2P#x{odSL_~ zyf{avwdQeiOxar7^o-pYhijc;U0+3a9?<7N+np36TV z;IgT(Co;(8UIeO>9hZ9}Xg8W8fy=*_acR>thMUW!UHjl?H!0S2mg;QldaZ0OZSStR zwCROhN)bT$BcKSEV+=9E$S4Ew7t9L(xw-3DMbL~TtE>n&o{(qTwXxXb9o^GE}IG$A%k3AOrSc)ad`=X zc2{sDaCvSSmo|L>xs1HOOtG%BRA*b)Yh`n3dw0#HO)un9iU7)$fFfL8ZHN&r&jX5n z?=P<*=()TW0hdjM>ySY%uP0EQ@3_1HLAzTy61cpej7yt7fLz+olY*c3q*&Kks)lc4AFE(BaQ74Aj`xx9x!b&=!pUkKVg zz>&b^#bsRD^a12D@)wg+tm`b*+1B-1*<9M*U2|#E3%Qgcfbt-q2$v5VVl*xvA?Ue$ z6akk_g~yOVE*~dQUE;WW0ztcHITEw2whE^Y6wxwPqp zTuKo@c@9v7%jXR-!sS1KqTh4;1%jT-7ZGsTRCoy)y26g(3JHPqD7ERA*b)Yh`n3dw0#HO)un9iU7)6fFfMJV~El2m+unvT>cjUmraHD zkU=irCs1ACxcmS?yH7b1xV*BAOPfA`Tt@y*M2dBtr8?WXUMrhR+q-KnZF(V>QUp*w z0~F!%3qy>?<^KqJF26*;WmDlRWRT0R2~<}(F26z0ZoCDOxV*ZIOPfA`T-t9n2k)0D z)^(QZZ0mZhY%Xo@uDP`7g5%gS6jDX9g!X(Hbmy;5xu5nyW zhM?V490~W!Ysy1RwDAas~p`b&ks!5wx3`BZ157%eb`Z1IT6M>*^`ib(ZRE>w2whE^Y6w zxwPqpTuKo@`4ON9mqQIP8kfTedM;;0z-3cmI5NoP2m;j&j?38)w3~yY6PFVVt#1@A zO5q?t=9?@GNJk3;eRMouAi4{PF^mVPGw#D)3drelkAJsq1qfYXUQ5>u=z zKR9K69x&UwUMmb%N9*xhkMi@7eb(c*9woi+N51CL-AhVnqxgc|U8=2(^dSq5WfJ{?iMI?n*HTj*9xkHeNPg{Qu z)iyojCDUtVzht&|{1K`@vD_mx<@)t8=U=~GtIO-}`c7xByzovZMWAgpXcKIIZm<(< z?`&hcIzf-^8VIm$Dy)g5&@WAXXKe2(!`7zv23y;^5ZjdN*HNppuV1f~jji-%((5p3 zL1sNOazW#B*&g6zw?`i z`^N>gwn*35+Vla$HuANX6ze)_b+&cARyMZMn@R7*qy?FM%*X|qf4A?4`x5lX?1uoE zro#S63LRwfJ0tUeAQPXqey6K#dd9T%TG=mIigo>-m~UOL6}BF^zouB%;mWtJ*9u#Y z++VHruJ5llz3~1jMPU437?))^#K5k-c{r4yUzWoVEK5`2aAfe!!x03k2hDQO=ST#{ zpE(j%>Y?Jh@WexFTO_`hI*=|sV=whuVL~E*w^gk3a{YyuOQv&-dEI0>fv9h*LY(}{fZEycQiyQs6R>$SpQ zb+q2~t;bp~x%CVhYOf#KPK7ps`*eey_SWtUf*$TO5x^}rsBjjN<6M*9`8oaQxWLvH z=^9&`-WzOFtm~-N+1B-1+1N^NCVd{07Gy3kBNt=>Uje_6phxB+1jsZME=E%53X|U% zna2c~__X!6W3^4sn6_Rk`z5ozSi>(|GefBkx`F0a4qJDt7q!aJQ5 zfwn85O|ZS%U?pEQd*7aIlTJQS)YOlQT{whUa{C*ghWqH8BF3S@53iyKr{jxlSU|E_9 z4UMoyUpGD6*7aIp>yfX}h;=6Y6q6RPo-rdAumWF7e3qaG>p28qH5LAY41)DMf$C`o)(Z&Q zy~dFM)-&S*EL)^&ux$DOf;E*HTKHQlDb{ru>TK(JtuR=T&%bT&uJ4*Qz2vU>{h{{y zq3v~O6S&_r*a_T$Z>_vV(8K*U0=UHn72ZK|yl?V5zr}cVTwrU9bd9Y|A3$s)_rnzH zI%;*cb-h+Lw$htPf54;#nUBoKwfo`61U)jJAV8+6@F|i)Uz_~S$UG;=#HX!4LTj6z zF>Sq8_DhyxU4Pi-Ti0uatw-*!Db{tk@~!K&!qy}AS8KiN`>RbayuV5j82<*wWm zuxsy12QB#jmSr%4WoasmhYY@X7@t7(ANS^A0tD?Q<49Pk=gU^grVrpsMc$R!-tjlo z`Wm<&DM`709mqQS`t@32xI12d*Kk|wC2;e_dnp2KlS7-p{XK)7!2JSb_4~USQxfz~ zf~gR|-Bg$wNulXXe&;8_i)Gl_^xj}=dlzDxa{W4Lb@uh^wX(65-b{LWCN0R!Xhtr` zywpbK`vg5QKR|#?Q(-0~g=RJRosoID3>ll=8)Qvy_3+qzyWd)g`1b-41a>$SSH z-u3;}UU}jDRf@p)a2S_mna#j1%koNlS!O5bmt_tF%hFVs6B&H-Fc*R9RkIxQsSq3s zawM$OYh^2C(+6;+B0n#bVqIT@I@`KlE6io&XYx|4>uZp2U9T0k9(l`Rt#`drHoat} z_)$_R0^ct)Mg(+6-_BE+Rw*8#7y zt?RYI#6|Wz#kvl7zIDA;*m`7Hto5#!#ikc7ixh$JrD0r_WmyBewk*pL^vkk5f@Ntc ztbhzYe^w+=z2TleKSj`PHI9Updb4b$Z2ADMROBlYws*;A0sK5h%Ju6&y7Y|e*K390 z?s)xO!)>p;1a3Zgl_JnK3fctj)eUw6ci@xPH3)jR*F*q!Q{fj#3aw-EJ3k5DD#O;M zXN+weei_sDF2pwF`gPRm?CaNSWn(M7ne@6$T98@aj9icjeDb;hL66La2#{$iY=orH z7AC(lGH;h5W7B(sOp0~=fnR4^*K1`@JH@&VSH5+5g6YR#${Q4 zV_?_bJZweKFU!^lmZhn%4Kn!VVOs*#JMPWHb_m-2mLp-M-Yr`xn?8Um75R=#igkSr z>TK(JtuU97?|PSz?+@d$EPphxYs+!~LBA|x5G+em;Xq{Y`ST|N)qC#wa}c7_F7eO4 zzAw8Je-CZHEb#w+bJIn`N3An<48L~D{UD$e;o1(Sr(D}1rny|(2h{KPjkiMy`fEE3 z!L>CN4o3#B?Fa(Zhwj>rM9}USj!u`zZL&*cdSxD*>y_#2YrG?U-?0rg24 zaW*|;Y`LFPN5+<7U8khZwyxL8CeHSb6Q@5^ob@!jA% z*7aK1)Z5-&Q*YDb#C4=T#e;&ap+3cflJ2OVYN#y&tQP~TP=BeRR;d5HP5nO!dg?Dj zK)u+Y!sW=|dyp##R9_g%`KT)q9M^Fq?8g7fcEhF*;BG|TJf~RKd9Jgq>$SqW(b0N* zHx#f8m)3fGHfP=w1H4Kdn#kedj4E^kJ_rP!dtEl7^LO@8OQ@t0-9 z+4SBJmttL~q|Uak*UBc&_Kp*$+)fQ~Ha$+9lHT_oB*lY*ZK?+)z3)AUcmURWfK{l! z*HEjy2f2@+r~ZBf)HfCWjik_HCciWFUzJgB(|bdGiglgTI@`KlE1P=TyKCxgdLi{G z9u#a1^(h{d^uG5XQUq8Z2Uel}Nkgsn9^@&4p8BT|P~TK|21%ipOnztTzb>QRruT;W z6ze*vb+&cARyOsvch}V0^g`-WJSf;2>Qg)@>5h87$|6O8^<`ic>R&a~3iaOrX1}lg zy++Ve|2hKdn+k6rgYUfGBv5^8D5uX`2#)tT5_aRevfZ%hz1fWv>pIVMwspN$csC+n zMoO`+ypb_nW?R>5b!k2R6>()JuTzh)izG(W|w2v)6Omh7igo>Ymv3FK)ur{q zXQy00kWL4rvJ*2HT4g6DZSTa41pQ8YAHhyE6@GvW?!-*yv@c~A4lrAOZ1 z{BhZl4>f;WZseoQAD18bMDxcLM?T&Baix*ZHh)}i82M52$L&Xc()@A9k)Jnz+*ZudPVeR9M$Y8r6h{8Y%kLRE%*!c_ z9PZ^*M$Yc#)JD$bRWBbi^5aJc=@i8dwKbuk^6f2fsv!V{K&{LUVdWa zL0*1lpO>>4`GA*m82PZ5a~b)VmvbBWq?hv=`HYwI8~GnE7c}xkFBdlQ z6)zVx@^vp4Gx9AjYa`$FatR~f_i`yCKk{;EBR}1zMo#AC>PCLg%QcOh+RL?!9OC6Kjhw;Db&dRim+KojvzHqh zIn>LIjU4XfCPvQgeMe&g12;jhx@ht&CjA%WaHY)XVLRT-?hYj9kLYos1mm z*eo^T*1rTj9kgf-HrU2mwzyFl$U!MxrUef7`c|0`x&{8m!pkb-^&Ax+{nuV zjoie`gN)qV%dtlO+RHXXNQ#-e}}mUfyEl*%4r%$Q!+U-pE_Le8I@uynNNjJG^|&$h*9J%gB4YeA~$T zynN5d2fTdW$cMcAKlZ*mK8oslduMkOI#Lx-V6&TDSSiv$bTuI%lmLl<6p3O;0tC}c zLF}Q3NEbv@K$;*(5fo{PbQD1mkzS-D9i)iT-gEBUc{0h)%=>=7zt8*M4?pfa&vVW_ z=iEDYW@qlsZmu!?4fHzG-JrLa?gRaY=>gDtOb>zHXZi=I(@FF=Xb97jpe31}1}(+( zPtbBq&w-X_dI7Wo(@UTgnO+60#Pm97Wu||FKFIVR(1)1b0j%YxQqS{~HJv?6F2)5@T3rd2>aOsj#0Gp!ElWm*%|$J7m4 zi)lD$ZKgiZCQNICHf34|v@6qkpwBXG0Gh(I320xY%|YL0`Z#Dl(c%5)9rZ%o&L{?2qG=pLq9K=(1-3VML)cF;picYq#Y`Wxs`rn^CpGu;PzlIcOv z(@c+m{>k(h=sBh*K`$^p1A2++InXOiFM|HX^a|*8rq@7kGQA0Ui|Ie0|1!M;dWY$K z(0fen{4tcc__P%x8Uku(S{&5Lv=nG4)3Tt&nU)7F$+Qw^X{HZ>mStKEv>emwpcR<9 zKr1ozfIi672U>-xAG8|Nx}c9ReGIe)(?*~!rcFWJOk044GkpTo$Mh-C+Ds!sA7vU1 zT9;`X(E3cT6s zZJG81jb%Cjv=h@b&}W!tfOch?1^OJ*Y|vgz^FVtu9R&I!)7L?hnZ5;@!ZaT=mFW=B z0ZiWk&0snLG?VE_&>W_tL35do1s%k6Jm{-TCxE`m^aIehn0^R4gy~11Lz#X8I*jR5 z(07wufpDV#NdibQxVfIY^%5x^9Do8 zXSMi(9mV=|O^R8_R+knT#L3=O^YK#r8H%yBM9mf@+3FWQB9u!XibuuPh;nhC!njXd zfUYc(-6XdZr4aED=^Ek}L5YSlb+!~e@(Z7?4wAhbX;im0Ly9?U`Q!)AXR+=3L++~WR5e+jBX*1*Y%~`JZ z|Ioe#JN~;`+k=C6qSqHQXgN>q<(|S5eHF)~)cl#(Dy~n%!8`kLirlqW%SvKQMTe=} zmYi-6CXA2M6*`j4`YRF^N#Yl=De4oPDzs$Pj-7Nj*uv zU{YU_1xy~3WFeCVk}P7_$J%m zLXvNoJT3{}Z~I$HvVzGIlJKp!|4B(!F$qY*cj5l0B>9%f(~|HFxj#aZHB2HU;d^s` zD@oQeiIRkG)BVwstY^|%624>i$4Ih~NgGM{=H1^`lFdxoNy7K>{`Qjmz$8`@zNPnf zkYp>9j*{@*y}y$r+nB^j!Z-T@KUJ3Ab zlVlf@?vn7LfWL<%yP5Qqgx3fB&q=bENiRuwslcBg$$lo!OTw!L{ud-U$fUOn50U=>kj?_ zlAK}kk|ewY;ZKv~ER%Fecs0VGA<20rnUe6rgg;A?i%edYgx4ti*^*plk|PN(SNL-! zxymF@5?;CR50vB@lUF3+MGXHSNp3KCRT5s$@V_R>-%MVYgqJq_Z%FbFlQ$*dRSy4K zlH6wUwj{jZ;m?=kE|bBM@Y;ueh$Q!!43&hJLHxrcQJB0V39pFwhfCsM@~$LKCL<&X zVe+0NyiVdDDM>LVqa-QLWV9qDn2eExS5N$7B`L*ZoFu%E;vX+b87A*bQkKaCNgiM_ zQ4(HW@qZvmc_x!2;guHuhmureGFcK{bn$;ANo6Jy`NqB+AKSPr0OlC^LYc>8^lGJ1}TM}Nj@qZ>s7?U}Y@CuH9t|T5N zpGy+XWS%5mCi5lXbshf~lGI|dK$6-_7E0o0vPcqM?eQ;`qz;oWCEB#?`B#$#$BS}jp-%IiYleLmO$z+`*0VeAud5XyfNuFl1QIZHInGr1~B z29v)e$z*a(k}M|IC3%_24N0<@+?0fu|NMVT!i#_YTax54`A3q0O#YSR6(+YO;T1yv z9Z7h7(0^Bw*O=UsIf=Ovf-eXcml95cxN-~Pc1CoqpQcjXFOv+0# zmPrLk#xbcV$#^2Gs?dOp7`jZoVY#B-uka1aNjKfF924^MwT28`Qd+EKG@`W(z5#ik zn&R$a0ufp?3X?<2Hzz(f5q>n%%c5AT6VICYK*h6WwLrzQX0<`Zvu1u!@vPaSpyFAx zI-ufNv$~+-S+jbe;#sr$pyFAx$3VriW(`2avt|uJ#j|FOK*h6WjX}k;W=%lFvt~^} z#j|G3K*h6W%|UJaaeWI=JJZKOolIMThBAEuv^dizK}#|XfR<+Z6lhtdPlJ|Y8Ub2? zX(VVRrma99WEurpg=sWsHKwgWA7L5;T7zjDP`(uov;}oDZ3i08v^}VgX)I`MrX4^Z zW!e$6F4In+^_j+jHeebL+KA~hpiP)|25rW)3up_bT|rwieHQddrrkiFV%i-vf@u%X zR!n<>Ml*d5G=^y}(6&qyK-)8Y9<&3~7eG5P?F|~w^hMClOcO!7GVKG}jcF2S52neW z&oNB_O<>v=^aZB#SeF?Nb(=^ZlOw&Qrm}Y=xFwF$bVwwe- z&Gco^T&CHe1DWQ44q}=M`Wn+b&^MS41bvI?E1>yI2Z0V@`YPx!rmukxXZkwm2&Qj< zj%4~K=xC;IfsSSRHt2Y!`JfY+4hH>z=@8HlnGOa0i0LrUPnf;~I+f{g&`+7Z3p#`8 z2+&zf-vj-O=}6FTn2rKn&U7^BN~U8#S1}z6`YqFOpx-ea5BfdR_d(Y(odCL?=|s>C zOg{kK#B>tqW~Lv4ZecnZ^arLNfo@~^G3a)tpMdUUItBDMrc*)pFr5avm+7aV2boR> zJ;Zbd=rN`F z3oHlaMZUlaP+r*!tOVudyud0@Uc(El2IYmjz_*~hS{L{Zl$YoNYe0EjF7Q1lFUAGd zg7OMnU>ztgy9L&R@>*M911K-B1vY~6s#;(ZC@-Z2HiPo|Szrq&FPa5@0Oggkz>lE3 zJQmmr%4=eQpFnvbEU*ofSHA+=L3zn5@G~f{a|M0@<;AVQ4p3gv3j7Mn%UFS(puBb! z_zjd7tOC10d6g>gJ18$r1$Kk-dQ@N!C@(?<_JZ=tQ(zw`FE<7DgYp_v-~gzNE?@%( zLG4TrfjXHU1`TC;1hhEQKR`<|JqlWy=`qlV|oI#0@IVAywnpo1Cvmq8z8dIhvD)2pEM znf?XZfax{RMoh1R^3qA*1}LwW1a5-zB1zzHP+nFD+yZUS^dHa;O#cPt^@PA}P+mj` z+yRYedKa`a(|e%2dJwn|%1Z_Tao;FzYIxBgAnqImbJu6qN781LBTSP`=3yhtaSXmK^oQ}t5t&GYJ_rn#^aG~+VP6d)6nxm{Q0`T!X;YLkN*Q}G`~51t!u5OUswm%9we^n7?$;qTC)Y+- zVh(37%%sFLN(560dTc~dR*)$sGdn#|->RH2eM6=$x!Ea+>AF_s z$yCNpMQ%anjTV{Ln}=U(8Ga|i|6&n-JK0P+_LF($A1yQQN9H{inSVDA|C?p_lL&vz zBK#j@GwIl2^UMb=GhaaFvlf}pn1?@Q8U6;s|78*W3fW9LcF8QWm~Xcc{+31fo0c)0 z)zkw^QIu-tN6UTl67O1uFNyHQEW(G7&G3j5-K>Zh9C7a18mbMIE72zMW2w%xE zh8r=ndHx53-I`}FCUtZX; z&^6&QvYB-FD>4~QO+{HkCX=I-PQ&Yw`Fo4Z-4jBy(=Zkd;H(=3FdTql#s+*a&&$Y}5mbeCj{cc9RRwF^$i!=}fSLMGF^ z#mH!ow>Zfbc`G4rd2%$_BM*?tmYA!ax@tVADIk?g5Qkm8t1KNowo_{Hna-f)HrxE>);Ux9w0}PPCa3jH_|w7E9<=N zkT=FEczfgEvDU%gNAR(Q9Sgm0jV7B(hewjha4#y#2r{+G>)SUaJ1R3TgVs9i+6qaS zSnC)LyKb$+E!H{|`vfu;o$&b{GSXY#3=}<$yma%wP|;J!W>WOWWHKpwGMPFi4l=HI z5*e*}G!b@#9?c}9S&tT>M_-VaS&!zC&7|zPWHK%LGcsD0Jqz}rvT3w`Ky91J&#bnM zWDBazA@=ingfB9x9z|ITn=bXsw16hwM1M!>offHgkj-RA|4gQ!s??RXZOB}ts(f{J zZiQV}nKnCjlhJHn{(+(ok(b$c9Uz-YW&4oXxUxO42USM9>jKiBwMc)4Y$juNicBVz zoj_*e%8tQqRM|~bc8&bZ2IeZ+Oe(ufCX>o8T4uhF%y%p@|7#xpmSy--k7!pM#UC;6 zSSZ;{s&|sf>HxLFZZxh{kiN1-`if*T8Q1b;GO6qVWH#R8Wnd4gOtDubquEj7LD4Sq zGMfxF$YxU6BgkxASvA;$Dx;&M0n*pANMDC+CS&F&lSyT@klDC0FYG~;DfWhBG#j%g zP;?9OG8?mIWHYI(2{Id3)(G~X%4p1@kv`HQ{nKPK8M6SH3@hU+zSd+k>v#ubZfB9X zjd^&g{#nH6Y!M@#Y$nxrG7qoVyOGhX`sb1PIg89a%)?XleGwyx{7foLGz+09y~(7W zVS@IoV(&-BqQ%qtZ-0_?ldS0aZyrj@CP$N!vdCn(%M~SqOjakoG}sMF9!N%ml3yX& zqU3y({3bb?)b+Ym-oeIshgjzwi@c-E^S+0?#s}xSup5lWI5HZH$9R%0#$!3^`kEX~ zcHvSonGDsJWU|_Yi(oe>c?B5_N?u8_Madgc@;Y)fsq1^>H6F_EU^l316B!Na+Dx)V zUAs`%ujFVll)sS4q~z^nvKq>tU^giFcQP83yqjc;l8>U~!{lgE*Foep9?Jc&8`O1- zj0SZbC)uK|E2!%tIhqXRc`})le3ndBLwN>vgOab3(V*nNNVX{XE=vBF98K!Fg}lZ? zc@uVny6%zDpsxEQThvvix^`t+vbyO|7AKQQ$)RMj8cHYZ1|^pzqe00JkZe(MRh0Y? zIR@3G-cnXZ-XcRux0DrO)77NjQY!XpWHhMhVUjIss)L$plcULu^pPp3T=iZvoJ^*7 z=Wa4ujj;=MU4OJ2(YjUUo_(cxbj7}oj0UI3^(5=Ypy(~xPbldJ^Sqm_@@_NEyWKkPKIGj^ zjwU-|7nw|U#7;7q9Mp<^KN$^%;sD7OLvaEn9W~E;#47Jej@89ugo(qvCO<4nZLKl{GECD)t2G6Bm7p2@IR2vq+^@SGjFua{5vx5 zw8*@}Jp9j=;SVGH0gLea$Y#>9J!YBJ=WY=Gs73fAmN70M##xIPXUJw!;wj7Uez3gamv+9mXA%C6WsH)DQOsppMhKZq&MOWwnVeS?dnqy+ zoCZsiY;hW_jFKvt=PhTI_d(;l4_W7}jl5oRG}$8_GMNlT7@16m!cRtnp?H*Ji=k+Y zk{X!jt#6gLiE-Yh)_Eh5_bGBT8Hy*#WHJ;j$z(bdt;lFF6j3Bw3`GZ&)XqF_8>_q> zjq`T0&f5cdpCw0=q3A*;!=c~>jh@DNpR>-Jh`cXY1@B`VJjptEI)V=%N0UzVx5}Gg zoHx@t??B|uu?qf*aqvOb!G|FD+vI4{sW+|i4mHj@%sTHV0~mTnu;=wOeRMuUlStp0*lP^&BK3g8GaSQFSiK4jBF+y`^r4?63fi% zk@|usO;UL*!C`zNG669!-w-}jB^OiBrTh=;n738f< zjwVAna_Mr5NeG(bX z24)5-n?_z{12cteCVTT^GMS9oWHJRUE312p#$-M+&$Y<>nR)nGmf=?*{4$I1Uy;qE zV@u34FGgnLy|EB>gT1kmjAnad1BzZtUS@k^4cSbF{99x;u51?kxV9)Z9!(^$~M6sRGDJ`m5gR%b^t~1B`>ov+f6o;%61{Mab-JU52}pD>@3os zwn%@HY$juNoJ=N_9VL_LBLGLpXmzeU1ba}~iv1iJ%?9))dUTDv%m(x-*-Xm5OeWK^ zFOt!!?DMb(l})4VaBEjgHn(|g_sna%V^!O~$Zb3mZozI;TWQo*!lJffWHXrwA!ITf zQog(?Lq@YbRtcHQTV#H~JUoqTb;PJ<5u*y(Osap-JiKDBK}NIcy~ymg$m}u?Pt`X< zjK?fu)FYco^>xg`D~g{?Rx`F1>_M|au{S28S;qq?x+Qs;9cV4cW;iPpr5Q3C&(|if z2USL67K8Lr=T-Hjhrv`jD|`zv-Fgwj}F1TJ!_-XHZfn^Sm9b@^&`P+r>KX zOUT=w98HFzFPThsL^7GIrbr*ygLVY{@BtYOhAN$8i=i5XlJm&Xq^=y~HJ%_Z!){R5 zt7J5&>ot-s>KcK%-XTYmp&UvkladFM$!aLyhTWj#_sD2a@<@^`N}hz0Cy=8_UE`70 zcqqrhZcx{UWHhL2GRYQo%|TtW$kAjdXOPLHOwPP}kRFG^lGC$rg33MP1*Kqe)$>k=MAcm9QJswT_Gib*(4aqOL=z zYd<-f?Bcy-GAVgCnXGp4F4zr9K1@b~l8=yVQSw=oe3~3h>N<(M#zT1=c7wXkkbBBxu{kcoBMSn_qv`gJ$9@C;j z$YffygN#;1E3g|BU5bnbMVBVoqUZ-vbVYJB*$L&zWVjRfI`<*tyj868)%Ije}#+&hx;IsEe`j=DCsTpyl+_L9b%k!sCC|P$UB-G zO@?A5nM@|=2r`*WP{lr;j0QvTKFJnC@d-+rY@Te@}RMP0YM*RYte1dthQ( zUP_SpI+@j7(K{|t{1N&}Z1?8)md^oz;-v&hr|FU94Z=A!{o`|3t~U0n4?lwD*p+@CebU^3$M zDFLnF+8+}M9QFoc~^L>>& zCx|WY>7f+3OJ-hnQc9Q9*TnBt%WEU`7itE>tQ(y7XebrsZ8Alt#${<)H|o*9BE<>VdH2sBkk*{a#Uuiy>`r&+t1{7 z4o2Z)iefPelVR5NKplliWct62!oFwAA!eItX>H>UYbUa+KWc)Qo;Qllm1>Dx*v(-#PK`2S9zPm?r@Buzgtenvtz8>j+5K*a{IpAPLSJ) za{GbYPLkUX<#w{%ek8Xa%k3v}J4J4%%I!3{{ZwwJ%k2!gohi4ozvZhHk^L}jelJ^Pre0gk|Vd7Moys-+#*Nr z$6l4h2yT^;w#n_!a=SxrcgpQ9x!oZqJAqlm)k+LK%1^R0)M6*_4_lQpCI-shn) z>P(GoR6;jVg2T}rrNnWol=RGO{q=^LR z38B4si7eW_KF?l;L;aWZayV`h5=A@ymWWHeT+mWKWQzS78;X|7mj>6_&^A?Hkdxo` zZ?N7WQ>Rmrw@K8Byu}WN6Y{>!>rR1}e(w~s+vY2_j+x1go3~2MjnB+U_c5A3hF3Xse~Q6E+^35<0KY0x$hI6tkBk1Ep=&yim?^6q9m3Ksig1 z1Lu4|7p=5$H1evb^D0;1rSGa@uf&Fdg-5cAu3_bZhWcXZVMMhdi3O*b8oGuL7c|so zq`KTXubKs3`taoC(|LIcyo$tnROeNzz^h2C2GWbJ!wHFl&EAL*A8b4`>v79gh0Zy3 zSc=q1d>U39jalx>azU?~lcvppCL&U5F5RVQzeOre&QHj84~lk!ZTYtR^0Y&#pHJ&r zKZ(}*ZYuUDwe@gr?X-#371h>lbgiS=D>^f;5C1`!5cx}}k^I&WtF|AZ%U(%sAE#^I zfxTkVGU<=T4Cm&284q;U2D%G$Um_lhKM32p zbS)T+{Ax6R<%N~=3#}s|gw&3N5>h)-jF8%q;)K+WlmIFTR0^oHM4VV5Y-^XEUT8ju z%eiu7(M}p=jJ#+9RMPpBH}R<=eE8m|Dj~J{YJ}A4A10(${|F(q`szS6fNBD{fWm;> zKpu&>Z3kk#pB!F*&>u;)Sxuq87*pi1Xe?Vg905Y=Veu3p z^~&jKLh4}=p;_&b(#lmgAZ*J{=_js{_37%fVPIlfp>&G91xN(0@7OzLskkq|E$I_#YU;>*i8iFjzD2^$VgD>eiVO$U~PMxi~c zMF%XF#loF#$5P>;Y0FZPUQiFZkgQFocy=jzKq>a_EXTw@n;|aLbZ?VxI?m}^jBKXW z726O#>Cuj~xfFX37Q68Kie7z=)sBf7xv4ohi8>3_(VI+K9SQ8lbx>P}8j=45+>0cq zWoEvVM;Fndwg|dx^H2ear1E9kt#3F0?|^>^X*Yv62-{LKl2hnpt$QQ6CgkKo+Ev#2 z>sDBriPM;3|A!5~=!pZNlyVa!SOz|1QVK$xY17%PHtp z14X&bddGIUto7u{Q*kKN-jl6O+9OA$2Y` z6^Q3zGl6(nr@4w0M@S1o;sh4*I3aNY3u!5=)FR{wpeKO>@Oui{(?AhGk??CJG}{wg)WhFXV20iN>-9s&(U3lJivN-MvC~ugmM;(zjSCX%a-n`$+`V?f%tN~ zG8@|EG;2aPY6S;t1I1B6&Cy7AKy2n(9pzO+!yrRB)zBcwP*F8B4l-0?L%SS4g`_0w zvhyA4gKUe;N$*JA$;?Pi(lr)~nsi@XCR7Qn#%{sK4+U_sMLoF|44t!vRO#%mQ>(L@ zqu$f&lS#A{+xoR1n?Xzx767CK4NS-zkwM_pFqvVwO_ z9n}!L2kOZ<^xld%Jje}Mr#&AuGpOE1Y%}PK;%sbeQQs}o$jIk-ha;bmIBPiu6B1`F z=MYVE4%M`fVVV~54z%IW-i0;-+IyPj7^!KFQJUr)t!d6Nnieuv(?Z5U8xQS$XcM4K z)HLS@n&zCOX(1nKTF7KgbAF_0&W|-M zY)!MzBc#49&DW6g3qsAxe*hf=I-#MEQyL0AO-PM*2HIH-+0PSF?>aANe$I=UHRO_} zge^oXib5d13eD(goZ)_8VY@i zkQ(J_Xpuls8nU-0B<7GK2B?jOob4szYmx!9hYhYg`m=0!<&h&AWHqEEqC&S{udp7K zUR2H#az;`4RW(YZqWa5f6y3YJxVo^v!Fpy^Z+gS0YkAz@Wy>%@{+X&F=xW6NIvY|m zax!|Sidz7LdQ)adE}S8YgP&(^$4WKjd^@n1AOUB{FK3%16OF1{KkN&=s z*L-lLpj|O&+t4!npX#Avy0+o#8}YxiDbCM0wBbAQ9Ja_$FSVOjdJCUx*nsY7o}r1M zexB7sn=JO88ge|RA!je31Pz5e5A*_1Zw=XB)Q}?)sE>x6NkGXO3P}O#t06}}4LSP* zrAow;IgYTwWbP>BtWM%{4J;_evT8WRJFEV>UCaBNFN?ddrO1Ht{^NZ?1KX9&!Fz%l zKFb!m>f}XF^$NTq?Rc%Jm;y>jcf;niUtT7Ix?l1L@qx{~&0zQ7n}#$Y7wzo;Rtb5#aueW2eY;b@5kwLM>NO#;_i| ze?|$pXqVn&)u2n1>k~4mqx~r%ZSPMOVYs96$s+ZZagvaWMxV&4L3G7FMfEQ-V2XVz z>qUl(=J7O^g9eL=oJ$6^$S(+KMb2jT;31ePI|As4W0Smf8jB04MYv9+_tGPV?Xr*nM6V$kQs zbn~@>4MttsKnAr-TL@`Gyq4XAhj@*UgUbJwWyA6}vW1J(ouO!eH?wS1%`aq7tNE3X zxS_M}B&4p7?BkEQ%9MQA=^Qv>uepPxk6&fcWT+ zc2FtNFgvNC{sPufl2v{rQ>V%c7;00Rtto@ZhzT`ROep!GW<9d2ld1tBZBjkTt%4_2 zZ6OEs-^a4Sq*Cnl*%JI_^%%=WGwn$-h-yMw5fU>kB#MxjX(7?jT5Fm;hLAe@+Gxnp z7O1_3oUuS1G!)vAkb2YBiIA98p>aU*K+nLhGqf&1U4fp}ki8orwW{taqGO_`)Odb9 zPFP#swHJJp-kjww*-12FvGnZ z>ts?BzfDN&bw@tXV2OCI4tCv8`k&+TLu=n zP@r8zmo9Iy$>@L^MFzF__X(-RPtcHaBG3mCaW_T~HmG+v%d&U6IXz5x2X$iz%ZA+; zEi7U@id?RZVM~z?$~&}iY%=QLr)1y`a^X|hDR}%pW;uBLCkr{K@JTEi6wa60WKsun zAt5oC_C*?UEC%{gBCcsRVT0r|g&dT8I?D#h>04WD>6DmG4?>fOdUkN#=BTHB| z?8r)CDZ2X=`zqFB;`u(59`#aZMkHUhe9H!-IyaI*Tprpt5mKLl+e}D(Y+?%`^-|^s zLgEd^`6D6qGGi+t^)llpplv|gfqn-11!xD*uRuG2egoPC^gGaQpgll)f%XCI2RZ1FKF-byIp{b$D-!ARsE;xz_J7$zH_@~!s6O3-=s#>Ie9flV z@35#}A64wPS&B)`&dDw8%*W(iVTM`miq#mO_O>@?QRvVfh+N03wK&uO_9<=(<9@8{O15I-@)HHh|Lh77rtRZJpLhAXV z86k1L2x+cqAuXUit|4bj4TU@bzbByuG~|3rLm^MYF9KSmhMcW56cPo$XlSi9@RV>j2adsFOrI>#GwsoWc*Yp+jOuO3)>2RkqNSW22aJSn_>{Ey0tz zvXFx&bw!p9-aPE~Ft*48XGkc$OSo+Ou9p9TIJoR?HV;&fM|t%qjz_yk7~~-=Eqn;8 za}}QhsAs8eY)L;oT- z4o>xgkb_bsuxyY@u_vnybjPQ*FqXm=u`13d27VOS!poXwWtigQ>ts`yPZs5|i;Lh6A%9Ozx35gKy52Q*S5 z?%8XE4SF_6$VC@Y2eN9|vA5V#bU9!Mi-y;9`D*x}2Z{#EFa{TOigPF%gT{iVxZ)gU zXrpV|31m>mX)+;gvX5i;;Qcv9$VGcSidDm2Ph?BsUfb=HSQNb$M{s^VeFH^3il3>- z7xMJ>@*%qf^@OUOP6oBw&j@MNPG$GtYCjQj(P}?p)v($bY$;mpEEcV+oy{&r)h;B1 zTJ6__)H%3JLym7G;#oGIut5(#7jn@a%wg5A2aDKJxCe@T35$la>`UoxIGdKTF{oF( zcfK;T(B4@?2DQH%32A$0HM?X0?{mUR2rxZP+6b{2&sFf9JC5R z6@e-PJp@!0=wYDhKsA9}KyDxpP&kkm$Olvls5X!v=ux0LKy`uY0o4b345$H6L!d@L zje(i~H3e!0)EuY<(BnWYft~<*5-0%l6i@_EE1)Ps>OP8w)*2`Vs0~nCpmsp*fntF= z0CfcF1QZ7p5A+OBXP_=XU4fnj>IT#us0UC_pyz;k0VM!E5A*_1Z=e?msUwsKtq)KV zP%=;oP+y>aK>dMIfd&A*1e6Ap4wM0u36ur&GEfds9?&a5uL8Xe^d`{TK!bsX01X8i z2J{ZlaG()DBY{Q(jR6`9G!AGy&;+0lfIbBJ2c5@<_-z5@ChXc^EqK+Azv0IdXC1+*II zTcGcN)&PAEv=(R`&<3E5K${4u{n!j`3(yZhKLTw9`Uz+o&~~7ofqntn0rV@-PN3g_ zb^-kkv>Rv-&|aW@K>IahKR`&mAU!A%Uxsd__hQ3){vX&7d=0l*_y?~(6|-+AOI()t z$_0PRJi#lz@!g*;@P8(YQ?dWXP3cMZ9C}g^_n?aXcTLu*#q7V5N{{@}Y9oCqhr-P( zDZ-^vxSeEDirIgmjhe5K_*%Oz;SMrU!d1$R4sB@>uM4dZB8)`{Taee#dq~r>>VKfdg4lxcdk?Wu2LtlqIOPfNzx?Aa& z#bc7^*h3r4!k;A+v!5uEsZ%EBP0JOx4@EMbhRtpqz>oJG$f=Zo&TNo5y2OP)USvy zASAvE>s+W=or{E(pZ-~_SshCVsRb`3q|TzR2-UFBt)XKXv~QrT09pm~E&RTNwgzY| z&^q|7hqeLQMrfOWHUn*e-w)7!gtishPe9v%w!`mdXgh#@g>@&iUC@4qwi{>Mr-A;2-&ttqp5$F=oW%ylz_7}8k(5^$f z0qt*Sx1jw4?O$kjpxuRb588cb${KC{*$Juh&j~FAS}|zFp_PPI3R)RxWucV=ssL+6 zXqA8}!}=h!DnQj>eHhv!K-FQb0nG(144NC72bvd}4_a+#erR=|)rD3c+GEffKx+uC zF|;PonnG&^tp&8lp|yne1hfFq(?F3xQ9!MM+7MFDG;N`^hZYO1BeYJ?;-NhQtqZiS z(7HkE4y`A&=b$A(dmdVEXfHzR11$+!3bek^`a?^F_7b!-Xc^Elp}h<(8(J>3JZP^# z8wBk&Xs<(i6WUwQ@}UieHWb=0Xv3ks3++87Nw9U}AK>HEeR%qLxZHM*?v>niPLi-Kc@6dKb+Y4jfC`xV+wXum<*1#LI9J<#?++Yjvkw1dzNK|2iX z4`@fB9fx)T+DT}qpq++x2HKy{&O$o}?L4##&@Mu|1nn}ktI+;}b{*OcXn#Yy1??Yb z|3bS1?Jl%?(C$N1*5ZAYkbGZ-76L64S}|xPpp}GH8d@1>WuZL)tvs{}&?-W!1g$c( z2ccDgRux(`Xb(fH4y^{Xn$TR(+|WGG!l8Mg`JmN;RvVfhS{-P0q1A&{A6f%w4WTsx zY7Eo_eodh@ht>kxpJqxWHv>woULhA)B0on`DdP7Tu)(2WLv=nIlp!J6~0NP8?(xGJtjlY4G1?^?{ z*P*=$^fu67_zi(J6lfUGJ3#LeQdbB@KpP2d6tpqW#zGqp z?R{typ?v`DLuiwseGKgrXj7q0gEk%73}~~U&4xAy+FWS!pv{N20NO%mi=ll9Z7H;` zpe=*;4YU=|Rzh11?OSMTpnVT*9klh(HbUD3Z40y?plyZr6SVEneulOK+ON=lgSHFW zZfJX;?Sr--+CgZCpdEqs2ef0*jzc>M?G&^#(EfyW4%&HW7olB(b_Lp1XxE@!hjtU% z-_ZVn_Aj(M(C$LJ56!ktdq=brQjZx2v=C^a(27GV0j(6Y($LC6djMK_XceGUf>s&Y zL(r-~s|M|1Xw{+BfaZc02F(L49GVYWEogpdk3y>ptsb<;pf!Nj2wG!kO`$b|)&kn& z(4K(yB($fXJq;}qS}SPL&{{)l1FbEz_RwOXb%fRlT0FF8pml-P6fery3hTjorM}dw5orK>h zXs3bB!1^b&vq0y7&cp8lw2MHOV7)9fz8by??JxLU2f7J#3x5AV`xodo&>f(Agw#>H z4^3IGX?8;L9u`^%v|`YTYnrp9K>WFVDHYLI`$}tCNEx8AKo0+CO|j)F_S$UEr9V7U@PLi_yRY>{ zNcD?>^4rhii-Go9Y*3%0k$-YZn$<7))@3t2;G{lOggk!Pihqxu|2G2S8?xePQ-8rOv`n!wq4a264LV)b6u;FQ zMo2smngKKuXco|HpwEEj0L=yZ9B3ZUe4sCY z762^-S_HHh=u4m_KudwX0{R+g8PGRC%Yjw^tpr*Hv>NDJpznaz0DTX%7HA#NdY}zJ z8-X?fZ3fx`^aIe3KwE)+0@?<&9q4DEUx0Q1{R*@b=r^EUK)(a+2HFF(7ib^QexL(D z2Z0U&9R@lA^as#UpkqMCfldIO1UdzD8t4qrpFn4U&HsUX^Z-yfpz=T!fGSE-@tiic*aY;%BTA)!(4zNAqpA zeD%j$s<5?hT4HW*cF{F%A{sx)=KhHp$^7^1_=)}Ebh}7@O^?5@>|$GH(Z3-=Kbuq9 zR#H6MPk$^iqjKfusqI^KZyXu*!Oy!!_jUD(q(-*ZEfdbpTy4`b?x0w>sa|R|Q3~JUSp>s-FN@7k*g62>^E4h!YitQ0w zbz8B@PvyHNx`w&Nxh}h|xu%BA4x1h}FKlzz*06={)$XP4?VhjQC*0q-mwI-%54wMI z@AK?-@9`XU-*o@!zT`RU{xkfXdv^GF_lfWe?(N|h-M@!la)02x?7km<#XZb>)qTtJ zmwSKsHTR0}>+Xf&f4j$ehI`h8zwbE`KHIZCe4b}w_+roS@N=GT!Y_D!48Q8R7(Og~ zO!$oOf5PX7FYzu7KN!9>e4Te^_-OB*@T1;8!oTny3*Y5EAO4Z|M)(%*o$yuO!QScK z_q-o^M|!{YzVF@Uo#x%(o#ox+o$cN2{mlE7cZK(~_j~V2?^f?#?;-Cw?_uw8?-B2x z-uy!}ypHk}U16RE5s_KBc|%K2EIp(2?9xk0uPeR2^p()VXMMchkYCNUD%qi@59!HtqWTpwjpd|*e2S&KhO^T zC2U97uVKH1?F%~)c0BA#*sZYJVfVw{agT71bdPe6c8_t7b&qpTc7NiY;-2cB=Kj<@ z!#&eI%RSq@(7lMJ#@Fs;G%=RbG+FCj=l;pP&Ar3DlcvaS_gip za@Kv$ecpY+ebIf%ec64*ebxP!`&8XGd#0AvpsV>pL^zc7I_wXmU@}Nz;nQiV z%?_VOlWk%6lJKSBUx$Aaz9M{0`1z4p-i6-9-X%0imwA`dL|sKwcnwX~bu@)HdAE3fq)EHY`?Gh4 zcc*t3P3OJd{oaE#i4W5RK1$R0Bu(ueZ?|u+Z=dgg@1XCn?}+cH@0jm| z@1*av?~LzH-&x-|-+A8!-zDE=-xc3g-(S9KzU#glzQ299eE<6H`0n}gYYnM2tk&>a zRc+O559V*AlkEc$Ntx+c^;45K6{3{PmVuZ zCmwRznkhU|1^?hD_W@fT+H13IJ-7 zAu2OHJuf3Q_tk`MQ3+i$Gt+VsI(8x0uu1(!kJoS9pkd?234KyC653|w5EJ_2mnU9hWw(4Z55tdby!pJ!qE~iP=g06Cxw&l`b*l zHaayYF()S_o&Kh8cKswUuFkk*6VIrL`(Qwv`k8Fe7D z&j8Ar{6EZUdIeT5B|AGaJ3A#SGds6sRyIwDTwD2=>ec!*Q3kK4oz#e?cE#%X8}e*5 zXrlAKD&5M^$*szxHh#?yQN*^6c&)2y#Z@goS8OYcuR^n{JN+7Q<|{d_So%VCLc<0L z?J||7cjnrXe0GBf(7_N(9DR!%vvWBls} z;@jUYm3*URc%1{MD~$W^0>2_6i;!#Mn?Dite961^riY&j*);2w3i1D0$bv}gXWriQ z)SIoZoNIsT@xwcASFNz2`+wGJJ{UwzNB7Pd`b@@zM$I2^AJ3T7<9>xkJ^!;va{SU$ z(vz}Y?VTfnIukq_r+?;&|M-bV=Xaa^_sbPF{dYlW?C5L3>i(!PIeFvY>(30k`(&Fh z7R@d7PlX2mSxjB1>4VCSY1A^V@yab#x@_Fq<`KK?#{}=wPxp?B=-r@E+ji~Rv}xPE zRYc0m5&YeCr{b6~hkuiAGJoBi-dcYu@QsOW+bJeKDkdT$#n^Xyfp6=mHtpKCX&o8S zKgZbjmjd6|=vHmoM0aczk(O!f`)h%3eCu{`v2kr9BhpiieSa(PZQm)fZJXFuZ6dPL zjD3GE@QrERDY8|&=-7yXCiU(q@NE^>Dk?IzO^1kqNyc&a75K(SwT@}iv3-Y#{wDPv zDDWlER?%_oJ4U3L)NrW4Hzp>wW1H5ou@U`D_QjC`-&m@)T}+3Fv|QtIj~2MLX&ckJ zZ3l{K;(ENmHKu)h`*s~#Q&^JU^8 z<>o!F&ECdw(Qz@YW8$JCo^H~jkMwq`^Y;@ue_tu^ZWY-oGNyH8C-QF6-`M-r0`Cr; zVmrh|(`0 z%_tr}t>!|`71nqE@88pnE_+(h>I(lHia6hIFXsFwXKGBXBNeWFzhQ8X$ravB{Eyy5 z(i79tGLuB8RNvI2Nl*US>+h4lzcjkqM*}Owy!hW2-Z3$^KmC1x>_qi#X+)DfUwvHj z&$&a-4(t9=pQWGLZFlI;&g0mLj_g3YCq9`)KxmMV4R0 zzqH=JRaD#9P90-9vi~4s|FU}js7|fgc8ZQ_8uH>r?&C!qC3QPVtA?{ht#OCpkDRR^&=~ET&VmH7E?R4ZbiR`Eso0h?f+U=c1Cp1U32eF`TA7(u@yS} zk0Kj&s7*?S{#L4MBHd8s)K8^5qH;=$o2_2>;O&RH%y^{L?iX4<6<#4w<-b2E7$w(d zrkl8OO3Tb9Z@s)=TgK;K?<@OZt-XWGPN-t*-J4EQiD~jyA&Y;orf=`etX%qw_WVFn zNO2dfn^&ect5FQ{ZS>EXKR$vUqncF3UUqWP0JNl?VcdSSi`t)|=5=KIPpEz8sWP|K_$Eyr=oG`iK#FHX%1TDGH>9jl2t)!r3OIG&r$u0k&ZN}}21DoS)U zrR(Qqx-8G?bf`c~~jiUo_QHCh10plYYQ0OVy>9b@W3~;f0ds z7iw8BJlt*)w>w#nUar%EMP<=W=}+lKQX}f4mam{yLu&OQw^~}CUdC3o*(z}>r;<;t z78XjS?;agP@A>PlI^zL|b>xZzZ8xT+Jq#QSWvhsB`UX~J>Cr$xhzpoA@{-8633J)U0t zwQRO(>aLgVVhgp?XXKWja?6&_(91?@`ADIbEo<^26?EiBQM2jXEVCEAl%R=Ia3nrl zla54vGkrd8ID;GBOQ4tIg&O*(;fwl)`dz^dXL7?aFVM@kH0cU5Hl&6vU0i6F_d0LK80hcLYPvvc9@OMF>0nlE#`8I=ELZv#M3sLSDh$y zmf$>1M4q7Xx>2Ifxmmk+=w&uFlLsv)iq*H#4+eK?9=F;(oL=6D&>wl{DOr-fp?;rn z!};8B@d$cZ5~*)kj55BdAC2Dnl=0N^3vT)DNP0QhN`Dsomr~9UEt7&e*oE3H;C9cB zp_fb1`U957Woe;y`dYc=LT*`R9K9@Tt#8S-t}5ITdm@3_E#h|7#?y;0#%3$ad%~_P zrAAu{bx?n@=Al{4%{Fth0o1JEY{rG2bn^r&I-UDat1r1#^jvzGN{4L0v^?lm%HGno z(hn!MTf*%QeNHcVo%QDxZl`!?j;YD`53s23?kUu0DK}a-k6tcQqw?G{hjNQE^`Q5K zL|(lV7bYpa`=#XePU5A#-ig`SiLdq^n3$Hwf4fVKl}E9@;#f7mrk8)a({Z?tW7*2y z6@hY+Qd4{9W~ODnBL1GE+GqeZ`kEWv<3=y{prKv2B!U*g%G!H!cG)N|E2~JOW!z}r zGJ5$`*XSY9h)d>LW!cHJ*4;ZRJ4OBTG3s^HYn1mJ4pC_(y>#!%d8t^+>!uJ%{i$oI z$w~cR(!KY-MNO7-lg-@ZOKRd4W98V~UAfi6{!mY)>_c<|XKS0n0pKO zyo&7q|G8(VR47H;rfEr`mZWWhhDu5UHJTc*KyY_i+}+*X-QC?6Ti9jM z|L1+5nfsiX+?4jWeE%PUooK- zKprwRM!pc_b3pDoMqhGs$ZLY!+%j}b%Wg#2zpR6P7g`q(^^1sb!?OZ=DZ)}N!n!6x z?_ODi3Pre>2(`}%oNFR%MuY);9C%36nDOfPZ`Y*N63gAfihBuhFMdH_ld*-usxGl1 z`Eix56~m>(z2GH*MaC5hYgHqL4u~v46bTHJb>223HFElx=1J}GaT&C3eMR6}(ONR) zBiSLPFs>a65jU4Z;a{%`tTkS0U!*W0rEn({Y9)&Cqo$3V+JBNh130;9$_(v6=}>{x z|0+RTLG;}}6d1jWl!xeLh0d=Mb6hOMObRP1;*~@^^b>&{CYB_)u7-OBw_?)Re<+~N5)|*l&{KavwCCJL*AT2P@oZiH>wi)0373(@;b^Tf3a>ZJ} zWwDl6<5Mn26~~TQq$)+ao=E2t>3K!k&?U9AOKPlE^fJz<1UG=b>aPL^PSsHkm&OFp z$B~VqIHqU!b!L&bQsf(n{2-ApQsgy?f*`5#&NHDfp}A?&_(58K8azeo0yD=khRc*- za}l@+0(Z*Xw5~O+P*{=FWhW0KZZU@=rw$!JWLei@(GOLun~8N1+d`d0*eWhcL8)0=(vu+;yneD%>e@e!vOVwodL~&>43ce2Lg@)oD4V{a0%dA zz-@s00Z#y46exd7pzLFT1;6I)zXA)CNhW2T1Qu9YpnOGv1=j#<06^_pZ|{K6ThA-+ ze9pC*00YT88Qvfn-hvEQ*;3c+-h95^T9QNvd>dFri(Z^`CpC~}IV}~C{B|Aa@wvx`x^;rdvNbO&yg-6Bvhe+K9soS;@ zsWsFjuQL%s2@E8iDdIv=F9#LBCDyb{GyBp8Owtl@rYReU%I#387%D2srG>&uuv1?4 z!l>llln_c15K>F2i;LT#bqBOIA0}F-h}K_HS_!-)ol&$Bq29gPCvqo5s)vinGM8C~ zxJ54MjHZ_8^z6|-ox7m(_YtCVML>t!-tE)58#>q2h|Yk^EkE2Er?G87 zr%(H2?t#n)wIcIcK!(fWlFrmP$IezGYUd`Nd!f^1r0DE^g=MFsuD?k-Q)w-omTB#C zbRU$4j1r}aD>Y)sO1?;mdS9Y6H$mSIotsCC&ZVML(x8=7j-H9=%#EW5p!9jYDD}I_ za#W<$PxKr|qqUW2>h$)r_8^2tZ!1FYicpEAjZ>DeW{yxzP5VUDUDxnyI}w?4wIx!O z62Tf~MCL-}VW`}-y{Ig9jitg>Z%Jp&X^F~Q$UFj>Z+8%xivlt`q+~G2j!acm`#E|P zB5UjE8-rtu@DYLc@~{f#DdIOsGxLyZZ00!sId5v4K>4V>9|YgE#iHmO}Abn*<5 zCn0j~SP^LvktK_^3nH{>j>w1s+RZy;%-E($-8Ts$KSktS$0_m$ioAR&GHs!YJhW-D z|3b7$_Gw}sHC{1iYlKqN)a0#EWu0k2eazarx;sCf9*`YJ{ojH=K#Oa5zYgM9Ij_wkz=b^RWuA+7BP3mt$tAk{cbbhC81U) zTSUfbQ;`h4mY7V>9x)#;LtwqhBCxi`kgimV1nBYP63F4>707%AnbSlj;DbI>Os0G9 zn2%Q>aPt%q=yYqu2mP&F0y%uV2AMskip<|dCg6h}TTG@;%*N})?>|lP{~5DEXD^CB zq;0vr0f7#?i@;8|W%)p#Gz*tQplyM?34sS8@N`UoPG-zOTS>kJfkUQ?K)>4~4(Oo9 z1low;ZQ>7ZQT%J;_;j&d{E-uyRDc)r!<9PN0WYLLMJhyhnLVj zOLLUaGqNc&4sj{h{cgJNlkP8vDBX?k)!TmQP@ue+ZduyFool*fS&kR%%+SZBJ8+Kn z0=6{IYMNV?KOpJH&s5UKKCHKYyRz~Hm1V0V_O-k-gDOXU#F*ykbEEtrl+U?Xl;3_- zZ*|2?EmYKk)NYfhGK5*Q;G~siCAH-XbY|@4(vrs2%^W*$E;{!SsTFQkYCk-ww_e56 zq#R!7$|1iXl3IX1W2$}Sof#UsG)fZ=?J3~Lq;bqWN@MoZdb_?TtBN#@vhCnLZHY3O zm61@Yi3@aQ_~{bTI`&+&{1Xzn_dz9c;xl?X(iO;CqdHWKE=$!QEeU$7NoU5h0o9Ss zP2<~R|5GSG`Isnw`>bXL(l)e%bUUM0)|sJkCi3a+5&8^56Q2~J3!W+OzWRu>dY$T6)_Mb$=*PAM3&JHn%;Xcz1FW~Ma8 zOsbqdX3DsUK_mGEbM;i@T{WhyKL@i|<538AW2M5vo4AZKKR(ky2cd4bN` zl?Lg}+6`XVzvBWLnQM3_JM|SbCciEkUx~(A6V-!B7TBUb*@(ejZ@|WYqX89#AA1fR zJfg0#cHmZx-Fu3_;suFGqwvMF*>j6K^bw%`=|1nqs_q-h^^x18v8u<0n!i_4DdsYw zvXd?zDPi_9p}j?iFQoX;njXCxYkF)X*V|y7AsW36R#o>6l~Q-P9&+LhS( z_pqt$tkinzlTbdjx{r>)ykVKT!mJHK7gNH!`6w>4P=D z4IbChsEzs(@|U8if1L`Sw(+YdTzX@PjUiQHV`j7A;x$dt9%0g{?y<2+XPmfbw&Lg^ zq4$(XdUiKh{gbl7IF;gRH8ttnB-?b$*K6&jf)`_|6opDcHKy;`qh(s*K!W=b{I!D1 zx^Xv6SFXHCo&h`ycn0UME(a~ z?Ef0kPEbW*TQTpIuxb-iXx&w`BW<8n-@hsFKoeLURJ0uwdW+GD8dZ*(?mgu!jbkOV zzZfi6l?)4Ciq3}yqo$^DcJqvhjk~wZ9NS$-TpNqicE#DYbkc5cmDYrm>$JZARngxJ zmAfIVVx4sY_QVbP*ADI7D>W<)eYC#ri|%PfzsaVqs$Qe2uG| zsf#EqV~VYRRaL`u9kwt9H%KV|)QrC`0xeaHY8crdBkglhAr1O)q{?r6(+n-(s90zD zVtpphyQ07sq&z(*b}?B)Uh)si1Ve2`d(JxvnH|zwm>%w3bawDlp8~Yo&iG1kZgdZ_(?M1 z+gzgqn>w<#!P>GzWKmBtyw+HmOjhi%Cf8LxWYK%{l(R~^sU%lnid)7oEAACVVHrz7 zwy?Wxfc_~2KFs9>Tcadul!TfZBeT<##B7VzM(2jBwzrPnO7rJcjWZTQb8=K?aIX>Ctf;I))`+tsm>FhFTQVhB(y)(RxlrbaPj&sus>S#A*U! zdnpv_>hn==Q@U1xrv&V0l|RzLY0Bs+C0SMvwsmI%Y0jLrXUbIe>_H}HiaB)xOsWmt zZ5#8PLiY(O`>+vJw(zf3L$;jZtEzi16_3?`Z$;v8gHfY~tR`s4#){*e0}X2!QEzJV zaZ<2JH-m>3ZnW{O*p5=*Db|Q$A2TcZyjpiYXY{|-_F|u4Idc1pa$DA!KEa|# zis|Giz|nwX0LKE30~`-H0dOMVB*4jle*jQXm1dQC(O!++^67x-drX@#RfpA-P}+`^ zDTCjadY>|tS(RT{L8pn5C!rP&C70_hXM0N1mDqU}vsCx#W}2$Hr!c$QR%4i24cpj{ zRiX?73L&wq#1*WRDvT~Zv!5T~QkgOHoo%C{awy3d&K8R74 z{gsnJZFP8;@Fu3dRij*6S@vg|Y}JCCH< znGmXGuR5ce3o5m-Msk`NFrwR3p$(?J9$s4;j;jt+d(BFw43^u#k{)#68_(tCt*z>l zv?ls5J5^pBrcRRFlF5K6fT@6KfZYMp0WE+TfSG_<0Q!5$9KarcJpp?G{tnn1un%Bg zKr3KB!2W;(00#mN0vrrD1aK(eFaW)pXPx=I6?(X} zdf4{N>^-Q^4NTmI?P^V2OvGlG2!?FEOEzLr?0lKz$1K2T5Yo{`%e1LeChbvd3d%s~ zKvR(3Qk!rWt@6V*6Ahq9Aa031Acg zm@zIDK}kj{Ab^gkj4BG7nD~{J_!3HgQW-F$8L?HJGLnU_(!;qdoe}TZKPX)RN->#{*6PoCsi`nVbyx z2Y^%)3O_jwa5~@&z?p!v0A~Zv0h|k9fSxc2OD+IVFO!P^7XvN-#z?Fcj z09OMl3R8nBYijIe64-@-ywllEWG-hVv$x3HT0e9^Rpamx0~+ge<;NhVB3c)gTBKcM z%xtGp>)2Dpnl+AH6*k@SpjwkzjVl#Mhb$}eo|<5Z`Z(unxZAf&OY@#h384$THuh{+ zarb>t<3`oi*QypG%g9i&(k%_EO(w^S%x!-1bf95#QL(wVWph+zJb!kT80Aao zSqhrj69cW<0msNsyq|ki)HyR^{f7o=N0P zD0e6n)0UM=unx1oLeDpG8+u5ivbb+4bbk}KI_ULnCys}&KW6%5&HB#LpeJTCr5h3PW7yN-H3_Rc3_bn$!Sl0d)YDppsF5(SUkD17KUgc7W{xnD=By zz)pZhz|Md%0EU3cIKX&76JP>h7r;b7GhkQ1Zh%RE$$%+c;u^&rn9qP5V`QUEr!7YE?;Hu(AT_p*NuB-#*E z$n{jN*a=@8;cC#vlGs|Nx>ux6;6a4DKQ*ls8u=MJsK;&)4 z6CKMt6`I#kzeo3(G`8&4JdHEC>N+e{>~wc3G_@b7r93~sHP{Tcq(y}mYd>u3bd>^I z1D1x32u6C>N(q)S-GX$hLyPIDRf)oq%9}6Ebc)@m!e{DIbGU0YTY{X-O=nu~KTDZY z!?LvUmvp?ozIDXvH`KQt+~LOh);$-wslN5y@|){hckg&hed{k3x7AC2)j^G@tqXcN zd#Fn69ppycN;`1AO1U{9K#;Wz7ib<3N{!8rTQx9QT3dR#wHqb$?xhVB#TK%Xj4VS7 zxe6_0w~`S}XEryG-=A;3qO8Cfnsk6_3#k2x@c((-c`6lwwbkTwz!`uu0cQcu2Al&p z7jPcne82?&X0?)w02c!o$|RQpSW-*ei1w(kfa{_HzDouCtK1!bC#*44UBBFR{m8H-Q3i|%E1Go zS?|fh_*c8R3g>`xW*ovEUv9Qn7w`Af7nOv)s52Q~uU_Q6Q{j$wLNw`axuR>`7;Miu zM8k@Q)|JK6xLpKS^@i@YHhyJ=+N{#)4r8r`73E0^lsS5&z_*X-b~ z;VMm?S<<32afh?u!$unm&Q93b*6xj}3|F%*(UQlvQBPxH^8|Y`zPKu>QD~>a`}2rd zQDCaW>v7s2&Kh_b?@LxKOwefy?ffl{Zm(B2`lxht`_G^Pj?&IkJ9oH}x+Mn%7$c&g z=uN7jU)rRDzQse5#*IOI^{3;>hmS;pDO=BdLojXlhDdC01v*kpS{{#7L&BKTM-O)Z zZ=~pS4}56;#*h=#S{-6&R0op~jiS*M>O!AtqYTXCE*Y>GZF?FZ7WWFoptepFvMH1+ zI+PU-C=UGWri}SC1*P?(U_0Il0c#_oMY^FHa!hqew>PRR5#EUUyE+{J<@uY^jFE;p z*@O|}FIt66FH*0H}~!C-x~ zly`}Mz>u(qQQ5Kl$5DO?Xq-NNGCivxx5!o=tqRhqaAp@>6(^my0T^nxYep|}Eo+ZFW2yN94$t)nj+?1{Lq*qW3;`#-%+QTyO`$l&4LCbc# zIRAO{&;cVR?$M$aqEOH_e?^#WTCIBaM`W$mb&7EOD4F)+-44p{wZ6GHF3-E7z_d?R zaKT=S9@^)q`>CR>1I0V8vaJK`gm@+$$xpRqq$T3|U_tX76*EgVKB28`cqiM=`-TG5# zJ)kIFZQTzoi#04vC$J$QBVOFYZHSLh^0REA+W9DUf&M#C#%N2+n%Y^x{W7cd)j^`3 z8%qo$rnaP~VEXm#-nVahaZY?=O}~Dd^wW{zbVP8Xl#0CO*6T@roV{G;Z_-0 zI}eV7w8~fxLfr-os4aGA;*AmOs#b`L8-mQ%)&xVJ50%#zn@+kfVvcDKE>I`ov$fNX z);L|L(|T-CS;`92+F0sPlZ#CK-)!8oL*s5n%2hqEVRljJzY^qu2E!fWF(tKwWb~Mw z!DBfqGe$J1)h521_Q^Tb(p7YpwwRh9vOWASMCn*#sA}xY$3zA09~9KE5y4*d>s3(8 z*n%1v%?A&XaboTu)5+2rjmhjeVv;#?k5y&2Q*0n6UNR)y0UWm8kezyfH}AHeCYWB{NFFc5&LO11)20|o<_3`w>Duo9FE1+bAL84ef$ zr~xp3OX>h40qlxO*c+DA0~!F^0=5He57+^)BVZ>$BVcF17{FKn2hfu7fF{5Mz%Bq* zJ(6a?u7KSDlK||IO4zQP&`C|Of64BE>3|l%48TmlEWm8Q901#4lRW`@0saoy8?X;x zUqCBhKfwL~`ryfdfP(-B0}cTk3ZSEruty-__&~yr`h-I?YT!>EtV4c{`le0eI9=V= z`k`0*eZw6RAt*V>a6WNcd2)!In9 zOQ2T9@CPN6ZV=i=b^LFZ2*)Oi-A`k!%0=MTz$!9k3mUM`WEXoGOHygOz)Y00<=eCB zj%%qkm#NAIrN?Mqj*?u!PIfg#wsLkq%c4@#~DG^*uZ8n zRA~Y$gAEkRDfB55S{DqwFH-283?R&xmKuxu#h3<4)qw%Q;%1^s)5T%eyT1?)GD%bi zlGst9*PGBfTf9doko99PreL%8Itnb5nlJ_~St%@|Ft&a9hz-HW;#q|rV;eZ7nYBTW zsU|(mK7`3rTY7Iahr^eDQ)7|Vu*Y)!wK2*hRUK@%8?U5Tw)TvK+c!5+=q5pP8K2qR zRqf?Yw)k_8L-$rSz=FE%j>YaZ0)wr6F&q=Z=)2y}1Us^gcR@}m#rcmqb=;3J5I5jkUm6d_rdrZ?bv`TX`TK|_l@Y|HbBwg&15i;2b&-BhxKG>t0 z$s*{R?^7sWP8WwqgY)d7^l8}uePuNp&v(_p?ya_C`IhWj=i;%3LBf4OxMcDj!kQT+Lp`|rl!)U!1zvp6?P(koikA3l2UtRAuI57Q`{9!I)x(_UMauQq?o0*+m9 znQ1FYx|nOK$52%dHraa3X$YF^7gW4-KZ|z+Xeq7K{w|BfT2IE7X~8m+L_;tu#Ri#U zjWiqV?uf?~IM^g!8Eoq6rqGA%@FO_)K(beuWYgWtVbwoSdE3mOxC54Ik7HZ1lx#9R z*ww14s`3r;5Yb770)_#G14aN?j7(|)b%2q8QGn5adO!nUTflaJ?EyOgb_CF3B=ka( zodIJ2V*%p;;{i>834mPy69LVDT>N`VMWOpx_SEKvr=~}%ul}yPe?#l`>LP69y9h7kd23U$Nv%5AvOH4#jU~*Ox2may zUi~Y+@4s-nVHJfbhN|xBFgYBgJUnTH!~Ueq;IKalW$~rs&Xq`sRfbvLx|bAyflXv^ z!n6DTM+WCoac5R|%L-d&nwVdgu8|~?YXR2*=usv&0B!`(SSL3FZUNj1xDCLD{NxV6 zoq)RlcLVML+zYr5z`oez0l@%a)(N}Uq|QCE(G+Eo zjiwe>@jqCn?q<_07DG4odUS6azly>@TV}-_p$yyPY`Lwd#F(-0rJGI#6<1Glr-E2$ zxs6VKdLkq`4boA8{S7fUOQ$5`>lBt%vRAsb%z-s#Et3HPM`1iaI#6x2Y>q+)wmtPa zNITSr&Qi91^W%(i32KdXH36=T-du*74uZLHUsC&PQEC+hwtxC`!rLDDsoCKM+v2IU zdFxb6qvUo6Ob4_8W&maaW&vgc<^c8p>BBRL9iG=N=R68N5`ir3T3W_A2V$(1G~lSbQfu%AL-)t@j-7roV&eWa}?|;@LV=n5k0Itei<#TH;mM# z_Uy(NmR`;=Wz>L(vod;Jp=g#TUTp^%TPyGyf0SmpsZT7~J!<+e!JId>n}ZM&>CyS&75WwSg?+qnPhW8f%#N+LDd|GFtO%p?u-h3hd#ZGBp$R zf$G=4sD8Z$yEd|}5i%zm4Ur|Jm>&j==!|=HpnQK}OMww=dgvh&>^(~A-=(gJof+sv zCXLMN>|DuVG7?N5s>v($uybdVO2MHjmikHS(ogCmsne@$G5JnUlbYOaqt3*l?D3t;6ZKH7R-P>B{WYk0;q58a9m~JbC%@Vmx&;HbSJFcJ zJSd7$;h=g26~rfD9jG0y1}>`tsOy+;ak7_PokTo`1tlq~pOxeT3f&;cOl>%r-dSek z5)-|FwlItSzM>y!LhI=UW}$a0^!*@n(zD7y&z4s9h8T6J44T^23gr*hOO(@!pMIIZ zSH%78JF``cucq=l*~AYP8mB1zz9z6TxWk4!uULri)*jL!oxY zLQE(p>}W{V2W$Y?5YQda1JD!D3$PKOH(+Bx9{`pm*%ZL=EZH2e1z<}+UqC+qotdN( zFaW@8ctXD_83fo0z?xw)7_c>98-Ua(5U@5dg`<%hb$n?jx6f~^?niFcjZEpt;7H$* zzbBpCA2VxCW4i6_)1rS_fe)*sOXs~e{=Iec-o5O)`QnMJMWUgE9bnZY8cnok zJ%bBJ9<)pq?{SpPv(3(#vZ1rOq^%C;l=NS`>~5n)Yy5*Hhk>D8sS6kBXUVW^WO7q! zbHj1gE4|oRfEZ{l7^MDrsF9KcyybNHM{r~Sb zBCc!BjB;hk*RpQu^glb}jyD#zL7n@|z&@$K2ZDOT1tC$*`CikZ+z#rOZlzo47+9M_ zSg>7FO0Jf46SbsW)F{4}c5d{|`$kvG6uh$U+srhKZ~!4=oW+S^=y1?1cZm4p6>)J=F@=u(_r%g&ZMvXCSNRx2)=?Gs^iZ`b!wUR_TD@Zoo%E1j zo6SDEFw4PgGi}qn4GaJLZPltlX@?`4kt*!3!w#FyC~1#I)?=fKe6kf>>8MV${5nO2 z@SVjBnvBr4|8DKd)vPtd3lle98S1RnKSq7))4CM;HV!X-3b;efvEEE$koO+i;nb z@Y7I2?F}7r^S`_pU~>i27QK6wI9Lb{Hgg;>`IQOC4h0UC^affBLcgw0GZQe`lG?2D z@*dk2W{=aM|J}0A>#;KLuce(=c9eM9pa<3gb(!-m zisoF)u7MGazQ^sCb#>xtOy(KNy^s{Nx zf9Eo&KmS}kTUTh_+EXuI|4QLu`IK}k*qyzsk+k;2Gh#PZ_!}wM+Gb?Ye^`}Hso1t< zJ7FARXtceNrcp+O4!+kie`8y?1#e+t(Gl`k^|m{9r4l(esD`!C0fXmM55EjBqW%9X zt1VsAa?xg9^*1HL^s(ol&JJ;oRp7}1eJ%nFc6~l97G?)1{ezQgmni%K(}77l16dD- z&cFph?AoeeRry6lzduCKoJoN4oluT2c`Pn(o8lZNA+w#$XVG2Ym1~*U=)zKz$IZVw zeFIvEfGZu)4o29kOYoZ;vFgkBh9ee|4h!Os2&3PoJRKY&1bv&E6@IQEA716Thsd+C zmSrMu%(R~Jz%D$G6jZW&E7)Eo%a!EHVuB?JPrpv{RoSH6aS9w^0;{Z8zn;xoOa#K>VEalz(EpVjn3W^IpWv+;**m>$jDz?Lg_#=B+KcvV$Jrv{kB zUMJ{Fsa6M7YJ2sjSgi8tnX6T_bHwn!pZH%oAQc_E9VklQ24YlA2`4>QRaH67T8Q9Y zfEUH=XJN-q_mA7z=mpg5u`Tg`8wC}|vGL^)M@k6))8#~`Lf~>hMPb=MQ1M~0ttF{d zY_Ep>5>c30@Hg$IU@xgek-wlg2~H*hrU0e_rU95$_*2~ec&->Jsa;mL zRd;L)y@$m4wJ{M5cE0-&sZ4Dk>)P;|iUTBSb|z=(*#1Rm`f{t-a?&{VAJcv9Q|e(X zK<{-+*L&U1(l6R5Q*X8v|DOZ}sVli`2V+^4G{+@8i^H}XFxtfLP$*wCXQR@T+3w@% zrAt*;SJ&{3w9lKAb`>(So=uQ3$@xRTOL*1V+G2%CM$d}AS)%2U^jHH6riQC7N%@aC z`=Q)-?i))?4HZ*wrcAwK2uqsXWg*i~leV>iOG@Z$<}S`Wm82eQuldP{tRZM}pI0vX znb68$y_P#)XBZnqlaqB)XmTcobN#YE+2z6}<<-l}onu&TlRbzL=USj;_fPPnzKz@dQRWi%yiToD`4 zH?;v}1(@z1QaEXz=A2vu)9$3xe}ddc7t61u zyuT6T-5QD;#A$sqlbXr3$>u3Y?gsW0>C^xM_hLKkIU7s0}*1t+?UeeLb>T3W{;A9ggF-uC6phN?l65Z;?EnAH=doUJJJkBVk zyNS}4xDllS<`!%gHRgvSYlG<&-Pl)YG+s!R5$_A5nE#>7CyJ((k%B(Sy zn#VUz8#7%u_34_!#wq$Tm8^`vso`K1{@Y#A@FA8VcXG!xL93|=;@A|LP|A{-5h^Qi zJc{5_6BTv@e{Z6xs9^Esrhklr={gOQKlkYlYO%@Ui4yv1221z$=oYt?7Lc>VQAFm6h)1U%LTT&1eW>l(vqWtL`FnQqjxKnaRH~{ z;Oa!NdAe2WV7vQEqQ91H)--1rUT(6jFj#u`ZH%ipZO%QdB8g2mc=6W{wpMs&6P{j? zU^L;QLiy)8z3?_81I{J9o7SFZ47GG$WqaS!VvB8AsjJD6r_AWEv11P-o_f09S=)3& zp?r&aT_>R)S9%7P-a_MGeQ+`K%BuGB>PDQF?qlm56p6OmsqdXl^Y>Mm9A~)qAB)gU z&_*K7lGuhuGb-&A2Hp2fgEVU6J=wb{m5T!1Vc&Mp-+EaaB__EhNK^i9d)h(8&X5kH z86FulN(^mBI2f{JOVaH>z>0T$1>R_=lrEby89hpNj??&_?9I)e;G+s(HeMAyS%_B44c^sryZ1G*Ffbg?u(FnW$ECH|B1} zcIb;&LxZ`lGc;$yvE5=%zW7~-QX3I8nmZdE3co+qM|_-MLTl`>csB*^W&*>#g#%=k zXQwO0`VNAYii?+#yl(L8gDt4ni`r*Fmg8R1^2+iwTNCZ>u*((wgK$1=aIu|DzvAw` zZC_e8{q47k!n?M}s;Y98cPY_b*W#roI*o32P$gU_sAofhowJ*&l09q)xFr=0Chdsj zY*FDfNoGX($VIq@zLronHR7ub*3dXl*Tq&cI~B5?0}TghT0Gb@My9rEA3gCaL`SZtjz^ z8ezrPs#Qx&U#;y&NR~UW%5TUjpEzph0KZGR(E5ZQo}Q5BtyPX$yEbrK@?S5F-3n-mrq!;i( z+6y?=q??vPo9`}7RJvUamYWGQO8tZQXN#BTzuwxx%Vn;)YoRzLGPf`2q}#_j6=tlR zeO+nTSUXCV z1}p>k3*fJSE&$e-ljQ)*16Ba62v`ZQG5|p)-2kfqXciMX@X6``_M<1P+$L)Q)&?-@ zO0cm>c|~{zU>tj_4=yWCOx-UPKRxX_an8b*M0KD+V7(i6`D|&SwYoT>(k8#T1(F9>A^)DoK zjDkux* z%e30IOxq}MoXM9PmqZgNo2l%tG9>h|5mO`wi^lnehWl=^`mgCns|@B|qI0RG6HL?W zCpvR%;c-do95d#WaKYR%~O?T4twP8Z&#=OA7gMS8DbIlZ-o` zrP8s3{4JFfXJdT<*V$R9BMap(aGRww-HijLH|fq|spy885$B^OXQj>NN~RO1i!(LV z6z(k?t}6U)Ah_sCjwOY#r(xKAbl0drt(ZM3z>uEk>owsAJDP;`V~|id`?0PrSx;(a zOm0z!a$N6TI)ahT`_r3DtMOI6IBL~AjSG&4_*Urhww@Xrz` zI6$GFhuvoF(9mJ1Z0oJIycf8A%Xj=rje=PR({`Ld)rO4-bgfFd_EngQHu&097FH@; zy``m-{DIJ)y;r9zrmc{JuN)jAtK85>#W`&nv$P|9Y1X#!D=TmXSU8m(_S{P1H#6Y+ zCQf>ir!;xBVKEJzbue7j1(T|0sOWz!twGQTW%GeciQ_N1S%@!Kisf;BWoPwl2N zX*Aeb>nB8Jp#N5Y)&pj8nDD|PEq&b0)}dg|E6nomc2;v+t2LFqEevCoL3^`|ZhvWO zQ}pHfl1=F=J}*dZ3g_rE%M^6Q&r>4H*$D{^aWf%u0b)OEj#w?}5guXNUDjqmP<5g! zHD{=`zusMIK7Dv<4frmi{%I=6@RfevEE@#eq0sjN<1;e6TY4#_JKIFBwms_MDz^GA zv&J+|(#)MoY}$e@!L3b<%0LjSC_yd&@nX_9@YMN=_vUUWoA{lvR{D-~ILcmK2#moZ zGRF9Rt%QyUa;DvvVGryMwR|(o&IdL0+0KU{ie4S$!nQPB6?(DlF>|6T>oLEl(66)E z3v!TtU#0n?i%G|d<{v3Pv&a9@EBFv++clPRg~RhG?0)Zv0w ze;NGV*g99#bu-7R8V?>n$IcdiA-!X8IZ7H|CWhZLj}wqlQTVqBj= zl<%sk!CKcSTybB1i|HHhAnATpYLKicMX8xr^2Jim4Fj3AW8#hDv_8~aaHxK!=wz6G zRem_n=rQZ<*27Ch<{m@Fed#mW5p{}4Fw5gfxXUU{BELv1pKTx=@P|kwl%u^+UdRtn zpVP2a9So*x#nDT^;OJtXF8? zpsaM2M%cDYQ#buRn}GH)<(kl?(eR!OPTZ&kbxdpc8n(Zq?-m5Rr|P9_FZzyZ@nF^V z-aI~?>#w^#Oj%(v>Vu;^Wa=uzan3mGVAaP*T zT_Znh3`5PmyrH_n-R$4OH(b(-{rB}%ce0@u?nxY2C_hJ=e;UV(n?9qldFt54;Qoo_ zr6r$srRVxh8&L&{vWn`#P?Jbyu#C962yoL?mZe~8vsCSt4XxAQDpP~Emd^c4 zlJHu^6^@x@e_TqnzOfMg%O+aCHdqVFN}Oy|FTLV7Q@v+Z*LLnv>>BQ-k{jnsZilv> zTJEr^6~Ek`GoV^bDGq3RRoQ@AHHg2dx~A)rtbBfMa#kPQQ*po8Ixsc9b2NRBUh@6E zujogZ%+v?%??a+_t(zMhI@rt&maBqs1$wZo5cX+HQyAt#qE3Y!y38IoaZK8WEN-K? z#PA%RAZb-1T!c=~xt-mif6R`T(^LxoS6_&G(Uh?EdgeB?+;#WQQkPggpseFZ4``?% zk#pfWqv;c^5Uom2QvAN5;h4Tqvl zZ5g8QCKK*D((19>xri-RmJ@erIKdXP*&87iUfB7 z`NA-B=*YoPSxHnHOtDqjN%jqusju61<{Rnq7gswk@srR0oEJ3hs5DHO?~keTWYcXC zQ+pYvs)H?2b;{g#rHtEINUo~8*hJJEgURc@3gsrHOe)$KZ$^Fw^Dk;Mza1gVYi8Ti zi;yP!QvG5sp%sN!O)Ba6<6NDgpw|uhh;0s??x0@c&Dp({>DRADOm7|BNZ$AmUmC3;#W|0myZ zo3~3*{_Gt&?Z*k!B|P0#qsyB3#7El3l~(A(rZj&9@kh6P+D2eh%4}g*MYq;xhSchY zOue-mar&5XGvd#?(Hp5SUm0|j@vG9hscvw3OzIlMKr=a-MoXxXdOE9%CS=M)(OM75Vykx`Z59PJgd zCkvVs8Uh3PmZDEFHI>P(tQs@f#aUu6=o(Jz8Y3`JHuG11Yv+VXV|MY|qL(k)Otn@v zcCdUC>gfO5@(rKTxGgAV&SFIq7N4s@zt>odx?sNKRFU9@KA*+(mH>ALoyln@71PHC zOm3OV$M_fc&hjhRCyJc6=QdO#;(mo%JCBRFF{trFITRwNfN%{RNVd)T*Ytp zK9v>T2S=0qJ$uYsTX2oE_ws>;=wqhg+}seVx}6IvPMI3Jx3Tn-&54=1>rk&Y zc^Xask1#GU81CzJs`$O-Y_I$8DyIH+u$(SkYE>in^vQG$na?)WPsMFgo2}FqF{#C$ z2>L+bp9ZR+uM*n1>E)yge8DPG`+3-?sBhO9w(5f02hLHl-yQU74iKXW9HS{91mu+?5IJKi~0TJo=;^tt9HFh#4$(w%7u z=~Re2h%L)$ZR|`Do1yaZa;dg+F6=(IG3y`?YM!Kt_0j3Jn9|@6p4p4;3AjtFj8=c8 z0bffxV>dnBGWM>Yu3O)>55x4$GrPLlD7yO^y6)Rw%uz zLAky&*(Y6GMPI7G;>nq!=CvdI_TWr~?j7{_?Z};t(uW$Uw!P76XKBEiwq&$7GP*LZ zK}GYrA(9r&Tt4NosH{IR?2@y^8E88yd{^H7RtmEpEF)eu)CV2#uq5 zc50xU?d;^!wny7fO7>5$=}k9rTh7M+hGAVf7){cSQkF&qiA0xL9jr8Ncm2EmLrnj! zv)DT)&=TEr84g~aRrl$v5GA~`?rDv1XI`clMg)ZJ!IOYh6|((OOAaeR96tN-{} zb%Tdi>67l-s4`OD+3CKaxqQA~Yf@-kReHw-DRlTkg}P^JSZ+xqk_ln5IQ z$(TWeFTwCjvs);1@%Sj^U^;HuQA%`bY@m(d=J^w(jAM*G=U-{IiFA5oKqcA*dyvQ+ zWXQBV?y;jtEEZ}@*j4E#PVWy$=p2Bq?+__t3r-iAGj08*r<_%Aj{F=FRF5{p|65dp zwl&GPy|wCc+hn>cnFWnmwS(K`mB>DZg>-LG#sYhbo-mtG*&FY#*I!5*ymm|Y*3&NZqNZsH%L__J($bzHIqiD9Z?eAIfbeTb5hniGo^g-#~j z^g}Ee)%V5KX(q|=1lx3lZXM`OZM4mJFDcK$M%WTZ)`oF^Dg$Vr<8T+^mI}SunbNK7 z-J=UDpvKs7ok9+^ZGYMEqf9Yzbz)Xbk0^GlNwhlXzc(m!Y`9F>qt2{TGVVCilD3@* zJ}bol)aR$(P8DCKz{>*lZF337>r&qbP5ioG!Rbs9c;1v#YDinA<&OEdFqF@|7p?7F zZ+!U4^gV0`gRRfoo8-&~GmX;qltzACq9A3>N|*hn+XlK3?W#On6T!#ojQZdy>Hhgm zi=C-Xg=2F3W{gf}Cnl%eu2YJbWd%MZFLf{VZ^Fsm{B@s6%G4iuL8vZE3v$_Jzv4_) zfosB&kLNAlRmt}Xsf3qAH;KmaMm2&}h+QRVHbQy5s|;o-`NqQ@CbZgGq#6a@l8v>C z&9YfzT|k}R@f=NQ*{yk6`r*EDW78s7qS#BTC=9nMqLU14axnU_ru5_GFz=Cps8D5H z+0 z)*BK%MB*WXWo|w;SZ4`~6Yai8+O94q!uVT|CoO~rCzE$nu9z~+Xaw^yTZvnC-TBZ; z+fZ~;xmEVjK`ITc+~xcy`+jxbT>rAdUTxcsusW66jt!Uz_(`>pHt(aLc=_O4(5e2b z%5ILanCVq7nKkCBmlfjDk52y#)vVzpYm?K@NDdjZ$JCkZq-PI_{^=`D^MLdDh+ubv zlg%k!Ht)|ZSbe#0q&T!rJ^XB-NQe3+*Io@#n~_cJvO#0#Ko_#xWsS!4kv>c@Sm`ER z6Fx}cm@Z%5={Jr|c$LDhH2M%;DszzJb89*q#&@jJ{c9f=t*E{^8Wdn{U9jr5KzaFs z=~pJEOlq1^IF!4FB=aLB^KZH`&2q72NmuW?=@Ru@Y`xo8%=OAPqO(mZJ8QIvI2)Kv z=@h2|&i3WeH$Ol#G*+W9cbP`9Q*X;u#f$TPhk9C7egk1Kjmx}$pLYD4H+J>M-E?)Z zkMJm``}|b~=?b1nkGE4cYf_Zm<36Ciy@2gAEn{X{%s=m=jBYn% z?JT4y+ZTP57269qyX~#5oeC>t*e)9vc{-!FC~gqQ1oN^FsckppJ6C$8a(cu^+Nu_X z;;>m!D)0D!&Dsl?UDVHPTmLj4WBHQyIHphYLA`5z64Hf9lH_|nq-VP!kGTT`saa_9 z_~-R<+V6Dt10Qg9djZ}0`kGcOk&k?g71|3}z8Fxf#W#8Mvx*56ed){VU#G&RCH|Y{ zP&GdB_#3wyvP*W|OOe=BKFSh3Qu7gA0&|HEKBH(eQi1H{J@3nil}h&tAK0VBL-Tkn z*k?XuopwWNoEjB*b30J9V#G2+@s>K8$4-SluDFYMXL!O}7xOS~+RR2*Yo7K&YnRe= z3i7HC8dZ!{TmdS60sBcG_G$5?P$_$N`j8RDSQAQVJ?n#3c4-y4d%ftrFlF}04uuXK znszUAEIh{BlqS7B!P~?Zy*Nv@>{9j486UR`tkN&>PP4Yyp4hKN4!m$rMHZsZy+9# zzJa%c`f`P&th}one-pXo&THMlJ6-8>wlBmSZ)J3SnDd+Uru}Q zQkKaY+22%dNx6;W`pS`&E#wdzS?(dXuH5=^h+=g)vb~91FFCS{xVy`(C#U<1%lpV7 z$_?dKl|x*s$aRxbiTzB8bts>t-8CHxzxp53^`oFkafOU&;YV5V$MmWEC@=nCM^4AW zg6WS1X3m*`dQ@b;P?3eRU$gaVk?hwT{pwu&)l!VNc=n5UOJ=`_w{-T4c+AyPez?}( zR4Mse&`bK;{Vm9&7+(Ba_|5%xe--UF7eDg~##6nRplK-KIxgR29?oNCO%2mj`)3%gd=z?>>yb$lmia)r1jekPG`g zn*B^Xa8>P6n$S@7P9M@&70%M?@B9fR&H-}Z@E+^OswT|S^Lev6@R0D3C+T{+HvBsI zA~zonjtzfKzioW*&>b(Id-ZPP!|S~A_N;I%ZQ|Or?}=!~ygeVqhqt%n&Xj}4`{XQd z#JBn#>x51FFyYGF272+ZetX*cN8zMReIlHE#Iy;gEa8hX2Zx8h*UAwO9AB2;Qiptc zJ@sy%L-ngY-S{JH$BCjJ+m1uz=lP**Y(0fHD_dW`@rO?<+bi@twjI;t=V=p8xega|`|UJe?nf z!^cK0oH)Nn+w<(xSi{AQb)~EGCqI|U5zjy1A_wG2nz1dhvi15$oKA8+AGhlr8R74F zu`=@Ue3+FH`tRxPX2MAGWf%5)az9&mvD_bV zaiQb$iahUg{^a8vIV*Q$K;GJu`(7ptJ@B#x-^$kVLYS59N%~DV{$BQ!nU}%6dbf3g zyw5A`F#}4m!||?arzuEKb+z_`||O z?xe{BEgOElej{HW4vr0fQNL|`@LrHRT@D@}khAfjKd-z&$I^~@yFa2G^Y&5{AKuV? z&)b7J@ohbb%h~4pNX3o&Fee+@2S(wfeY6WFA2Dshy$yqNYzhW1?%ZPK4t+E)oTwsR{P+JsxXgKXxN_GLM=q2*;lxTTFeu@%UObiBNg z<$vW)lcQ|!kh8L+e7}(+JdXFd^C#XVayGqKPO+}q@}(cm126tB_15!rq46giKAv#l z#F-my`l>#!o;K|ww22$ng_~R$Y1q18`K8>T$wS_;2mUvH$l(GxpGM5zk_w|7NZ;CA z;*u_5(A`1K%LM;p80_&kKIC`Vd8Yy-XFk3)YKk@I1`Zuzp=N+Di8lnHw5(;6;J+H-=h@N*ga3SlpJz*l82q~(K6=2DXG{CZ-}C>Z z-pQ}W&$Fey4F01Lex5B|%i!N1;pf>>^5psXkHbeVdAiBP<% zsYT>?2#e)*mi&A=hv}X65Z*lP82@;Mc>II(Zt;l|;~#AB4~X!=jq&$1__T@0!t=9G z4*nE_|9*r|-edY>4gR|kKKdBrk2d(&8Ou+e9p2jD|4Z-mkBGyQXNR|xznAA%dbjv_ zcDRSZM{g~D7yXX;U&G*&j>XTjtJqG@&j}HJo?S&RJwAPAOFz%9A_tFuRD_>rSN|=X zljV@%f81Zv;K{SApUL0jBY)y~{5-q*mcjof!q2m-&l!B=Z|UdR)rSoJlX{02>I_de zxwyP;lb`4RQN3IIRdVpJGWZWi_-p0hpJ(tdj_}vc!G{;m&-oGlIyv}<8~k%4eC*`@ zF5KI{eGLAY5kB_I<00p3<&d4Xb;z(z4m{k#a&xnF;}q`mLK}o^kv|Xd`gyhy8F>2egZ$x}C(kxg-|1^Y_j@^upJy9CH~7?Li@%h9$N7b4 zPoKCJKhKsvZ}5+Z@bhfx!v_D<2tUu3-fr;W%kq{lKJ>vXex5BwCLaI$2!Cb$j^)3v!KdxB^z&?Ki^0EN@5rZ<98Wj7nEo#E^ZY!m zcZPad5&oj-IgbMZVKc#7#f>+oZK z&>7FqB@rETGp2KQJ9KU}bnejmqH>-e>}5>nN{1iwbFuR$UyLU#9b_KUK_~O%LmB&g z-4xO3ltbsRcIX^n=v)`kp}mOtncWVZ-3^^nTs-o|Lpu`FX_8-Fz8alB@*$jfo(}Cx zOsCG_#d03%{GoHai|6Ukj>L5OJN%f=X3ifvZ^%Kz)1iHd>1-gsynJCxe0ja%Xm~ob zJ24&VW*(it8agjUbe7MdgD&LJ@$%*Ga}gcdshA(yniJ$=`TWcIL+1%O@oJ{Xhab}!=lr4biJYZFdm7WJcla@#8s`t4kK`bS`r7e7-8& zZ(A3zw|R81d!7#YqKrJ9h4dct^O(br`FX(kldrqvESyIr5!rx2=t-zf}Ew3*QR63^7#2x{>RBd=N>ue zP~JRwZTh$J2R|+^+67PNDZN`dE9rMEpLZO7Ob3~GI@D!LC$CK>tvr4nF?6W=mQGjw zj`_Kx9XdA|IzKo%=rK<>xtPvn^2_4~+wSvqpo{0}tdc|Lly>M)hMrDqL}%3;ItRBy zhq#{3k9tQwo*#5K&esfwAD7n@=a2qSrj|}#-(YMzbapUwzKrOsqu((HKhD=Z&Y$@3X6Y=f-!VToIQ*E- zRnDLI@5xy@dHsR&+M#oXp+oy(=`60_F+a#APd=12{>1-IZb3P8muCsNn9e@(%cC>L z`9tSxIZKE3A*M6Q;m7is;QXQUrJSYHMZaS@+d2H0&PeAEom1p2oxFCux*a-|hR%r* zo#pg9=BIZ%bT%|}u*sI6ymoxGcIePH`tmwDqO*d2$NV7syz-(Bcsf7m9XSz~C$AmH z&g9XdEjUJw_~?(N1FtbZU&;^sxV)&Fp3b*=w{-H_@i*F`^OB)MT9!^%{f_y0tQ|TJ z7&=eso$^{tjwi1jzeWCe`MS>e!v|?uI;-e+%+Ey*KbFrq&L29D$XPmT>32*AUCra? zXy*@|OXMt_y!LnhcIf=w(77O@vyOhp{7h?y&aQ^ec@Z7j-?1*dTz}EQo!swOJ`K*F ze4Qm{^F{mR;}d?D9PJ4-{4+me^DPuBPqxhe<4+o`a-^}i98X>wO8)ZbtnU1wbEKT5 z1FcxL*t0x3^v^s$hemYBdrXIP^60?3r?Y=Vry_^W_wqx};xhWm`I9f|FMqv!^4j9} z9ezybP3KSi&*Utfh4nkm*Ru{krt`S-C;mrrmQG$wgJ zL%z^q+F+i%w)k}U=gIjb=TCm@IR6U&qSXeC4(2w9k2RX8zyPLC(;lym|84baXtA4)Hu4+ILGQuTB52aE_9T%j;jx zpZMsZrIXjDf9&vMI`0}fUq^Jh>UU>3+6HgqU(|aZKTkV<_;^4LIitrs-Q;3A_scJj z&YjL5I?u>iI;-e+Oy^pMALr|G=MSAHw!@F0cIb>VbS{eMtgGMKyKrCb%>U=*tH${wpL67_ ze2}G&Pxy^;w1fEb;79$3F7Nd7Y&daGmrI^p>wW_2d;mhY3mU($fNU%{IS1;)82YM|Kt3j zPg@V4f05$>H>Ur&{5&0--w%zyrT@0`hdweV-`G4J%3(b@_=g|j`3JvPM%1^ww5dP% zlg2l40<$b-Ci z;xxL;FE0&jnD@77tnU0tgSLY-&@G+=-QW4qlO+_#r(<=rlk+DXY(MFAmE%EQ(Ffvr zUH?t*lu@iFwEy0J5xsj|N5AohJ~{^dZgM;axxb(3FF3?O2L8#bvu`WZr(^T+s`DqE z>*Yvi6*(U0J}XB&pN}Wq?>HY18-JURd!0Y@Z<9|>8a=k-;4LKh2 z6w@CfzdZVbjK8Jd&-o(<+BxXcUh`0f^HU$e%}X14J`Y#woiymb@gQr;g>bJk*xWoi zwCUd8>M`xVr+>BHp})2q5BZv(Jp3&D!{uUqp`VXG^so!0v5uV2!sJXR6DPy1a*%cf1g&ZbR&+v9)i@O|3z zs|%E$r}eg@Wz+sie(0OeH+GTV;Jhzq^9?P=1cc9vE_~o{q4m04Eb}*9xKH~Pga4+( z_xWzsZ=SfVdR%_+18*zK!58-7K{=m~m-SBCf0N_c&;5;QQUCL3UFZDC$N6&TC3co) zfA=?Tn=X`p9<8&D|H69r{8Iltzw~wBcYQgY1Ki&@jU(lsm&U=y-=={KeHz#w^09#& z&w=jm{InmF6elnJ3CLoX-dPWb;8gpGRjE<8Sl97zupnpDPFbo^m{tAY zzP+O?kr5Am^J9aMyHD$Gy(2Ty<00(7a`Yd4nSAel!yEl^@H@$Q{P{`yJ;j1Hv~HJ+ z(|*l``?OzjzrnxP;rp~ne}2-w-_W|%(X#o5ADeH+oSxS^9llQ++0*AD9GU%ITX=!P zB_B7+#rZzNh5LM;V({U^%KQ-h<~c^rr~kj`!`_Y#ykUEg34HL7x0!NQF1x$m;2$Li zeubRJpPw?J{zDsDC&|TWk9Of+F17AA_@_I3pEl{wPuhJAtrHwAo9~TXxKEq<=z0Bz z!}n>U59_+{dC`Zih8E=*=evsw_i1DAecH!4e4jSyVM_?lOWV^xX6P|#dD{WL4Zk4@ zN2b*OL*$5$F539$B{l>)xE0-B;$fH2Cm*(`-hH}+ttrP}!k2M>eZ06menH{zK>U>* zE^(id^Sm)uAq{Lb4|E@rBi!flKKDDOL;v5?Ia2SWzmc4$v!>qWmDfv!3#~Yf^PN9( zJWq}^ddvAV&}YjlI+jO=^2Z-K^i!aNuKEW(ZI4&(~6i02>t)-++iS63DiZXRFA z0e{l}R*tgUT#kpj@{=4g_ht7V_dAx~H_jhA*c|e)g`B7JsotQISFdCJd&}X*X}n_m zZ9nNb=TF+-$&rUG<$T(Y>CNWhA@@6`e~m3 z44a)lX_HUVu9Wj>kI|dW!;bEEOuydvTlzK5ANn`RL4Sapr$1P4K5r{If5HlKUbl(+ zj2v-E*T=Qt=#mWwr-z)E>yuGK+b_*ITH2Fdv} zNSAn?*B9LHnAfMAKXfjTqYSo^^UwUW7q=@`9_(3qdR9VmQg#cA(j{B7EEoIh#*AV=C;%lW)9 z{|`N1K9k(pOqwprgVeEOEJmz_Up{U}HJBjkMku&2Z;mxGVT-S1d_4?2J7oFj)^XhS@mJM{*gc_}08 zY96oDfA4S0=pyG&+CR&YhgvzGHo8x|ayjxq`|s&kS)6G6E&ZdNKlIO&BX4zbJf!tk zIr4?0jF1fvY4vx1^YV=@fUY z@OMc$kH4)8pO>`Jcc1n>dM9n_g{L)0Z#L~p_nS0tkOO}yIgj68Z$95~eVreftR*_0 zFaE|d>FUDEU3x1R{KFl-l?k>2I`blvg$%7b94#voXh6%SP5nPW4w>91XJvw1{wSHe zFIqmG{ard%PhNN7o-gXZ$3NKNTbWS*37;34JYZ1T81l{p`{a(G@*Wp5oesnC8*)H6t z-D2>OkCh2_XEzs4dHi45np&3zJbxqy5A>yZNOx;F^6z;bUA@_~*L1&0`)E1v7nk$+e^k99|DLb+^d8HE^etb=$>V?G@U2Yf z|L-pc-tXzqmkyUS(A8KbAGvT}9`FZk@XwI5GAYyVKT0N#h?Y<19lgggxyOZjzNr5m z{{x3_WkOp)_`JyEQbUV&JC@10F5IVmrolhO;d?#lpx-CCaMJ!?Yz<}Z^Z16|W0~yb z!aZNqe~cZzmCgTmQWAz@(WCs`S({3>M*gUHzq&LEa=cVmwpksHtxX6(Q zd>fA4gSHO`hxtaI?^~nr3jMxZ&X>cAdiQY)dS6WrxsnbxkoW(OSN8zhbh_I9pCs`7GJdgtP{{W8#u)q41s?i`2mA3twjUQ`>^ZCK z(20!y9wETml$Jzo-mEz`oY;vpZ{9+ zaKrV8K%a9L@Zg(1$-a62+x|<*)O>S+2adXTYe0G_ZA_aPvk+u z6vEd8=Zz0^b#HEy&M{4pOb)IG>u-#C@AYDg{Y3)3=6e9S*67F5vA*`& z4?_>neFAlHf50(Fm?HFbk7}owm0<{BrNdTcH5uof`yUZdW& ze^)ZSxsAZX+BJnK1bo*#av#Er4G;D`@r%yAYiUDTgQ60WNN*gVBcp;%D&HtF}~*)ek<@$+geY)l~`MQc0}mmI7*=39Y1x?=Z<`M zpYaS3YW#ai=lJnQEjAT+dW7AD9RIE{#`mKFeYb_cGqX^0pcbth*iZYVhWYN8MdO@9 z?bn*ax`~UJ*n{5*Jmj;wkaJiy#^i9Hz**T|;K5hTVHxRKIV=`>cs>wv4&T<8`t`Ms zzAIbTW1M96(R)e`)FkJ?zB(pkV!#*gNAr9tnYG@}StZxpI4|@-?Xgcn4=-nycY)*K zZt7-#CdwWkaNQ}eKRXECAI?AX`TX1dWa+W@Ihjpz&4KgZ%Hj6V;};+KJAyMlNa*YS zTp?S>^qOR1ay_W=1u>88{UAU1Yrmczw#4zt}XZ;C6uE)q2V^2=()fNH|`%vp~ zkaVqj3=2IxZwt8|^j|l7IwWyDESY-zUf>}I&R@=fcaiJ&lw@)qEbz=J)EqXJu9d?t zLQf9Q3-EX!z9+exJzZJ$j_Fa!^~^0B^L^RVMH1I(k~uFvcdVZ$=H251VoV;`v!^=> zJaY-P9-RMHJ+N~Qk4UB-I|)4as66OfJe=`81>*Tspf|P`czOihG4!(Ie@8O*#NA&Y zN5I)I&(9=#Z|0Vq`-?L&x%bi&iRXUFaJ!zw^FYiyo_k_U{9^=uZ9hkH?`pWyQUXQuC+KU=3R?}lKokdb1mlA zxaI(ND~CTN9`>6YT#E%HS02uPi)Y)=69;z?XT!aUsMX}pv` zk5ZrB`fC;0-~%r1!dg>u&HcW##jQiL2 zlO$*Rg*C1NN zT&9^;EEj~He9jlh)A1}Rx$=yX&OGi_>Uv`6;W=E$b)>&54>sn>_wa$Chvxx-czpjX zBf0Xx(c(H^zd9McxzpQ^jU>=$C#@=+|dQ3CsIzcjdd!JZe>w8z&!-*|15dW=$d5DSqcK_kK=5Teg z=lcw<%>^FnSM53f=D$$#OoHPihB*Y{AZEwaDQEID*WqFBSXs~C|IE7=c>mk}S;^B1 zTL?USW7SxPN@x4aB@?T2;~nsqnD0xhJBKYfQYW~!7I;`+eQzb5eP1k@KHE{?p)TZ^ zbK5A!@YB!OY$Nc%|1$x5mv5pjG z6wE`sm1i#LT0FCb9-fzk%!AL$!~3$u!(KWsdXmTS&^wjqbLsvn)Vw|nJ@MQka)&xFvk=3yb{MW0q4zMEP+4~8BdY}iBRMb38$tn>L8ALE+WO`(V9IU(~PFCIE% z`V>AM&T);E^WTc~?9k)mOo4mnw*n8mmFGn1T0DH4poiyBfpg}Z;hICp_Y3vp86ea% zI8-`wab}5QQ-P;P_=~{2>$h8s@%;~hecM9dp{6y5?WJRVt@qZUhllU3y#K9!{AJiz zp7j&YJCbJ*@W}&rjc0Y~TJfwLde*!lBxK!fd3}8cj7Y#i;`v~l@>q$S>c&KqJ z9`+DDJfnmh4|`a7$h*aZfAicSnX!8gx$=A|9eZBu{Bh`s=TRY_d(K1Uc|Gjm$@Q5S zdUy_uIeLMIJG=5cDP1cb?hN$sye#B+rq#Ie+%8>GVfY^C7Hd({_^;BEn0WidtqODkNeX+$4lm(aV=VR*Yh2Co=QBQNzVP% zy1VY{z{9=gckyyC=3>O;H~FvP3c-ZtA-w)vjlQ*o#3iG zoPYDMH=Ido!1;HLj+2~ohP(0%414VQ3&adK|K{QR^Ee)SRUYzg#Y3-{=OW3(>OE_n z<$r4aPeP67)6kQ{=R&Se>kPgb_Lb+A#PgEmoL8%_>Dg91k0ze6g=adAYkjC;i|3Za zLw#~yynn8XdGwtBt72U9qQBv%KAhdmLylJp>>GPauOsuoIY<05=N|A}J%h)|#(r*- zOpKg69@ZZrFzq&F`O_Jy8zHF^| z;-j83hb{J-3y%8)$vnHnFY|+ioag#6cKxyEyMzb(wS;WHdW^9@P2l;j_{DxDA=@t> zW9&x?Jb#Q|?3WO-{h~3({w#q#cimZA>(C<|>!|~^rauM<^agr(co(yOy9qqlt|53I zYVRzS=HP^bhj?pWp|cPYC?-Z}PV9k(BM{j4^gw3*I~Sxtm_*9KZ|D9Rj_) zr(nO-E&JvDzng&lnZk5}eY5wqm*1BTdw6m$zZrUXI8XWhLmnh_>YLijPs!FXaWB+& z9`$FQeeWmWlL!9Fb-Q%tdPQ>XXV%{o^X`l5lKst+IY)a5Jk)kAp;I2;PjkctKM(eE z$1l1Wg*;ble4^%wnHu9CTfjZ-T=thtJbMc~%pWQ+?_3UyG4`t@F4;GW%#Qcza?VxwjtvcGwcvRRT3} zPqLQS@*Z;D?3;5*jfV;N;$i*VLZ@7q&wKKb#(xy37yhU_`Mx8dC$29A=7tOQ!!KtJ z8}HSG7_;UQ0h=KL59=p)*VSHmK=$^}IVbM@gzO)E_J2!^@jsv7_dI8^_Q};@OWyqj zc)?|Y{T?DY_Z#~RuWL(Ayvun82(?d6lg?a6Nrs=jubVnSE+dwz((^Btj^J$*~| z|0R&)c!52o@9@FH??eF`@97IMX3a?gYrLnkNv?T3Djn-<9`}bHo+pI--7&kye8=^5 zPp_A)^LR-zF}Wt>a7D}`_qL~F!j`zmm7euJvA*`xDbm^Zos!AZ_SlY$dFsdd5iy3J z^WlEs{;aj*e6?z~Pw3%zO~|!l|GVjdoe~#&LhTL|h}Au?jU?i54{RA@{IkE*$n~C6 za?N8y=~{XGEcEa^Eo2_fRyRGcLgFHidajp>dGhM52Np>p>$`_$?I>P>#+ak@Yc z*q$DkMR5J>-}Zx(?Oc*;?cl_=o}Yh8x2wQB`BFQd!vT^j&->D0UwODs&GU|AddWOJ zlBW|mhu-@aB)53jKl7|9+5IrLWO^G8=RUdjDrd+%<6@0#Nj&J7cRV-5m^z#<@N4^l zl4~6TS90ay{omp_A@s!YcY*zPJ?E3$O)WV8j_GvC#N^z1By-O& z?^^sd#`r#4$hDYX8H zw~X_q_iCLu|F%6(a;_6OQw!$J&7Ea??)hA!#Wb$>&MjeI^X2@Thu(Cq>`krNWgR#! zNF0Yqo<=Yau~(i^VP9i8G4#~yLV;Y(v!vw8bGUTG4o^Q}N`cxQC^)AhB{T2ZFD1G1 z{4MNjJiCXUcpedm$9EBDrt<6{o#W{*nVtpPgdUy;1s>=1eaV$)W9iJ3^ZG^T;WgtR-U<~YsJI+A3Z$J z3b{TjX;gWrNsEVin1_Ea$a$@-F%R?TIm2HG#9Q!=;;9oyrQ@rmzC1)hTi^YMG1fDJNdjjG!bu`*ZtoA>`8gxcS{|Ix#P4SpOa z{ZReBDV^GY3m+N^;jH_SX z|Jac)F;FY#%f4JGFpta}d_44Z&5b_979afu)_}7F`*=k%xp{AxuYJT>;~5~-yhli9 zF76`MJKi42oO9-#_kJ-Zzmo-iZBLxt_}*3a_Wiu%>U)Qnx9{zeJ$1~!v8najH0*2r zHcUM4O3w9zb3q~BGp--?sP$V_I_EH6GQM1o#U<0fa5;x%B-{RO$@r$mH+&XKuV_b;T|IqdrDm)yWd0($Zo zD$FPh5qPN6cZI&zeS&Pw#XBy?MBO=i%)9Q7#~9z7EA)p5#Kpr|oL(ImTsKD=GLgwQ9XReK6Y%XkxYrW9J@vy+};X>wGQ{&9_qZniRq`>bH zLSFL&jah?^*vZN9b8d1isXMmt&@b%S5P^sF)qbFKwm(F2K1-~r_Om8?{tnOf)T7!H zulX;K%;R{-quTRsXYYvrMj^+KuG+sZo$c?Goa5n~ReRoZwtqk}HE}%Lf7PDzZ~G^T zJ+{^U{$#(OWP0EHQ#b5yN%j{>&hdY%VSiP!pIGdvb&cozWPfb2=YFpCrzLyp(@${x z(>3gmPWCSp`{^6@2PFG1CC?z3A9?SX_qp98#_avO0yg;@<-cOSbvE#y&&Kbupwa$&cuRK4NuEq1i(8DuUV2_+LJ}b|X(zSRN z2|YZ=3G|=ip}v)8fOIXM*+UP{c%h$Q9(0w5af^pM(6i<-A@eX-d3gWtDAYQC6nc2h z70AW$aAqpcYtprNUJ5-t_X_!L;w)7j&VP&Nq0qy_{gvaHR^!TZTiDmU*lYOVc~!{q zOs7%h;a%T~=c3TVbF+|n;HW%jNY~;yIrQ*cCgi+0Bge!%`YD7XV_fq(IP~yvzhoYI za+tt9$$4S_{GANv+5*4K%_+dmgRbU5547^wA@unFK)~lO>QH-QJ+Q3CU>9p}Fl54~@mOC?vHwWZ^H_T|hD3$D69dxoBz&k?2(+%K&&yGz(t z9^!PYM@i=U$~>*wZP9^;HRc&3nRtc>uHE{Qn0M{gjd6`<&Crt<_b2g~hqY@9eXSkm zAD`97pwQ#vGlBitT;OTdZf@yYJl_pHJoEy+WFENcnPtAk!x=>n&ldvmIA>z#Vcxa- zN-}qL&FhoU!*i;DKl7klTj*=;Cd#(uv-VFeaC$@ztGp(asF%0tUWUH%W=d)~#bItI(MCjqzM?m*yf#;h-H)rE}vTw!t zozUZBv_O9T{=r|p59rkv5B-K7p7R9u*F3~qdAP&27i!KQgdQH=5yX>g_eRXScCW^` z^1K*&crFlfzj0S}Q@i_vtNOSz^!OMnd`p;I&)pFAm4|ahEzHv|@w94peg~e>iRWg? z#FJ}xO3b@JTIB=%v`@+ zVjd1+pgx_rw$qHcCP|)J;EeOI{?`KY_RXB_Zg*nSLj*$A<~j(7t;lza=nl->=0O`)34dXy4OF zUR&_~%_*69c+l0m=yB=buIJ#v(BtDy0Uxk6J!YO(?Y7Z;i-+@X9_mOu&YAjb6!Y${U&Of9Zk^B*&t(Gfme)=4sWA^WWm(PC*aPJpw$=nfmbk#=L8XuEq1E z^uHD0c}&PW^usuz)0tf?%@HSSd9eRx{M!EnjqQhX!XD-Napy7*M?ZmhI&nRq8FSqz znObc9-`4+Hdq>RM_pLF8^DTip@<_q)^1FcGJn=udd+`#@+dqG=k&FHJNUph`mFzE& z%=>yrfoE|64)`1||Hfo~;v^n^9WU#;sr_)-o9|x9`Fz0nx0px9*W_x?``=t+B~yFf z@vPRmi@*jFCzH^=*r!b6`_ z9{gZmc|MnJJArtv7qA;5@L>DCz`X19c8n{}q|n3jtdM!A9%Pwuy0#=L8{L5yqd)(t)Ja8C2xhP=1Xso&;EbM)qv0?z=U-Xlv%=Xj5i zOt0m?Cl-!*$2)(re@ODQ0y*=rwj1BG$lku`mFgRA=IxuqV|znFK8hQ_$&wMXdT;r=Hc^U#0Y)b4k(Z^gP*=<#v4z&*FUz|*STM$)%<)(bs6 z^dIkJ^R#OBjso7&ALdwf9pjcAWnjD|i2`p~uIK0`CQ%wN~G89?j!Big&_gp@-)jfqwBjpw)M0hkeeOct(XD zp0NV)_^e@jynz322-x$!X~lDR=;6T^@%V0@RdP4AiHEy5_uY3i?xuE} z|5mK?g&rR#2;2+56*}E_vumcs!~KgMp78?vY@Sx%@&0e|U~8TeCFgsJ`g|s^Pu~!z z-A6I5wRW;}Pwu<(W8SsnerWNW9(s8AJ|Z6Tu>Ye4YEO^WzmEo`IiFE-z@9zl z*ZvQX?7Ux*%w9Whxc82EWMUwmPF#P~jJYOAX1^Kpuzp8@v3>LYw>|ywbzuv^_H#&b zj`*H3<_74u<}p}0bL}S?d&WFH!ny)u`{w-H{yE8C7wnrg-PDlxzquw!riR`t@`j7~ zzSMAF*iz?-0yXrvDeI{TT+W00+rICR{B^*}%)545#<XC6t9e?r8yNPLhrC=n&P1&pXNGy#j_(x4 zm1mmJ6VFf~_ucn2K1ARgkmLX6z4ETs|3<(M?^C{Aoj2T*1m=;60XrUi*Sq~$>CAPq zWOASfcv%0Kz`S$EpY2bTObzHg+t+^O-Ge=L#KIjpKo~2S=S9icFI9rMV&)#JplrDo(uT)PQ8tUpS?m+NtOjIkdjkf-gD_ZPDLzA>)# z_*>}Vc}d8A=hAp>!S$%UQ)|AxZ1IT?*N)h?4m~~|6zKDv1m{+H`2KJ4tRH%K_`8#H zXCAmJ&+5{(cvcQQJiJ?o$KSBTzO2AH*LtZK*Sr=DJv<)@#ABWTlDnxL-+!%G`Tj?b zj}HXiP1Lzl?Ko#G9_-EYx@7v%JgwUC{lBG9bABiE#KX4&@i=E}UlmyA+R;-j9?m~{ zc-|I>$2>if*Ak`>z9!VZn=a<;<8F;xKE{V0AM8cGt7@-Y+kxYX#KCt!z3Xc%=XT&Z zBk`;&d5FM6%}x@C-}xLD<68R>p(md!1!6JJ+>*ByI@PS^yO(TTGivYqkv%|*)H_(Tq9&2^5$F8vD!cS0YZIOY#^Oux>qt>zUz79{4)h0Ab**iG*$`*#1NPnd zaVNkvx!z`di|0$}w-AVtzRf)BMU98|KlU}A*Fz5v_Xa%fOKc|ytaFW?i*e<7GW76V zAY`6-G@f7RYwd26Z7bHXp~uH%!Zbp@2d|EK$IAI{@mv&oc>XTH;$zDG+Y7uyr(bTLm%j+vOqpPEubbD=la%aU1RF5>!3__bhr&M{+r zat5+*&S5uaaf0mOs(tWG=;3}%AZFiV#QUg_V|p;gmFMoz!}FE^kMExaBzJQbIsdI# zxhq_cuO#>O9d>pHo>7VCL&@x0zJKbOKBfcD;fZHo$@%`FKKsYK_Y<2|UVQ&MuTLct zkI(dilDnxLd9-|N9eVcXeu3I~pXtMzGvEI$p7lcy5BCPKnumU=JgZCB;#oQL@X%Al z<9?xbeE+k~wd4E0#j|MW;ki>F9`h_DneRo;VC#J5d!v2_)U!LYIPj03H-gW18F{n! zIo_#ajQv|eJ?ou(!&QBMAl>EyT-OQI$M*&@@i6aNy&7ZeZxyor;u!IsIkr>+m;XP?Bhns+yUIbex{VfykkY* z;`u`QUkT)VvjC6pfAZ^QpC`#4uDU)=(~pP7oNW(Gwm*=(jlk2Y^PbW>FUNp?&cFSAE}1*aKH-{Aa9&>5DR%su>${Tu z?&y(R??QUQwqqo-7q%zY^<&<-t{Y?OzoIZqAWt6Ft}eibuEtq?Q!D%aQZn=QO{`1C zynVC3w&&Y0$GVut^9rufoH0*a=%$NbbIqYKTyW(35!pVtH+*K`q1Tx+2X|GAgL!ih z^ALe&aiN>D{hsVM6Kaf{L-g#y5dvpmu)ssziIbci=kt=SV-I#lxdf+41VqlEPHS>^c!E&yIQ5^^6$Tx}F?*c-V`~v%JRL#L7L@igj4%@$t04 zlVjaO<6KwX|1F+fLJ!YGA@i)D(JVqfyW47P9-m$E-y-RAO?kgz5C1qJ^RJ{)H?>$p z_V%59tP*;BaL4C*6Wekz?|tLWXz>gRJv{VS=Hc&)`C^_s$+`b4qyKr&%n`P=H;CKy zI7TwQ^1ksM!MtOgI>wcUv3X7nd-HI{Mhi0w#L9R|frq_ZJAP{(t^0D4Y}v!=e?sVq z|9yct2Mav#)_eDH=~_ITfAsK-6#5C~fvfV2m#)Rb_rG~QluSIX2eDrj^RDaVF|K)C z7<%G4P9PrhkXJXgJ5lznSlM^SI$ARO!?;uJ4vhI4>%O5U)@uY}HBYN{yT^RxAwS1+ zj%4C-&e;Ag=3TpOVqAIn_bT&TCz*K6Lp+_%daLiKGhFz9hyEQPtS;Ec6_R~E;OF5^ zVcxMWALGiycZqqpGvL`x;K8<=eI_orYCUETJ^RBxPZMK&w9W{<-s1UY=;1k1m@&rx ziuQk=5#Bi)3pJjPLJ!Zm0`Yi%uzgEloon}6j4RJep@-*afq2Zr+HPvc`ESK~cj)o) zslfhhE_A9L=fA~sP3Yk{NuZa^16RFYIR7mk&INjSJ{Ri!a$3y0cKB-XaL1YF6v@Qn z+QHpT?e-0>x<7vlJ$%m#(+c!er`qAa73&V6H&1VU$N6vZpmWYIN+urXOzi8$ylb~k zjB8%J|1(eSJMM>W?ibE~jg@<7(d6Sw$ukMA9rc?x<{fKKjB~8;%n^EOceMbIbDm1_ zS^{?519J+j=RsF{lJj3;b--?qxMGya30yP>e@KB4I z?-=P?JZFX;9&FfO^T1Vkj+3s%Ga~fxoGlQK`-IvYB(TnP+b_noZhMCwp7Vv=Z|p@k zwc9bcs*mkLj}PwK-o9J-K5gZ^Vd3egvHP}FyPtI6SuOF5lU%=Beh~An-S<22EM9ns z$9n+hXra?t9hBz!OQwf-u%~D9`TMrU)PwpxE6gA`Z}%Sa$i#qMCocBJT(3%IkEu5g z>pvGZ5}fq>otKI?k4cC{yZV)!TGdr;-H3m2|Vn_ zsRHx%J-Hh4-DIvqB@?TC_eee@=DmLh#F$vAFEzC9X(V@ZzW*qDeAn~6bLjDLyMT|{ zpShp63j50QtI)%9pU~TP!+ITfewujhl1x0_YkaO2^RCekV_f4|F7(9nppd^C;OwS$ z^9EP-F<0pELEmtX`#Y0Q+M}^G8KEgv!ps(M6J!!6g*pLJE^*-K5I>&pb zWcDc6k8ddE9WUpfG4b{jh!5VK1@l}lnY(psfrl8oc}Hv}dvj3-Vlo%GZ4mR0>E|&f zmh**g2|EgY21#o0pl-|DYk&JKeAM2Kmd1U9`iEF{IB`&^ssEO}g){+ap zoCo`8-<&DlDSp?vKbW`g$-N_}fw@kROdj@)-`WRXNyoPpv0f;!em8+}&u-54bFzoqIg%fEGW7VkB6PVo>wR`_*jFCjN6w9J2)NBdewF9Cu&+E< zhMst?72p{n@L)^ba*f8sxbmDCdU&1@G7oiJOK`u|v(3H9ocG~K$*tNQ9D01rE&NvC z!B@?9Z|Pbbe+fMtrwa6=dElzC>?B=_hc)Qo87TPgGU~FWz?}2p{omr?J!Ov5Bom8y zcqez$Z$Any{P!2A30O(6kHaLBpZla$wA% z(+XP%Jgn`;_kFUr?~`JE_I+E-+xN}M{t3y{(!TNEjqi&S*GS34?z@w`&xv{aJ~PJT z{jfmZzMJU*;wKk)xDO_G&(jyqn|r?cJ}~C(dw8_7?=V+JUs(t(W(39U; z0{OZBiLdrQbti|)!y4yyg=Ati4|`O3)(!j0vu5at=RARU@;O>L=3S!|VqAHa2|YaA z|HNaSStNH;ySZiG%K5vY$H!d)_uTdZPpfwHM~mlMp@-)Ufp@ZbTD9Z-{|lk!{7LBH zxkt$NF1GK)ylaQA7SGF}hvzMUczl0z2X|Auhh^XLac}7H@wUJ|yI)$h8yEI9=j%cb z&nrT2eaHE4#WN=HyeFA>+%Nb%J?33I&Tot7xX=^NYeMe3Z)-fi(CPlJXJoi+s}I(4 z2cX9X-|sUCt{wfdyTH6--8II!cJS;NdU$RU;Bn5gO73Q#@sH2!gMFmm(c^=Eo0>*& ztgU_K{I_^k4Lv;ExxMW(=fB0XSmOCiGVwTPVrPF?=h_X7am|ZwJ?C|*55=r6Ujg zOcdB_=gqp!1?C+ubBu|Xm{k0UG9mwh3&{MzHh2G8sd*0%CF7do5nONNy>_gp8dbGvE`yV~=@V7`k z594FrwHp`XniuEaJnRAS3=w$PpKfY*uI%BeKF$a|u|6iS&w~XXYFl$YR=O6?k)el& zyPCc;4_uXJxO6QZdILQ?+_}UvMBpKI-v7+IcDu&7=EeKpJiH6@IpF=)P3`CbxT+7% zzkU2eGO@Z}TD9Z+w|G`fJYPx9_fe~M%XHvbEb%-mxz=v}n0M_4cHp5t&TAjZ{e&R` z&-a8~1m8#4QWqX{J@HHaKBJzi_b}`1=K;wx3AuisYy5M;@pAqdvyPbP5qxs~(K9|# zm`2!C;A!o{MCmh+?_tird7hV?dEn|Mw|f#7_XN4QhQxGh%saQSF|N5?8+vj(MIff# z1RiWJ6NuS77sc2-&W-c$+$KoQJacKhwm>b3t?p?(yCY@e`gxC8cSPukmHnjub`p4) zuROz~Yw_$EdU)OwW)RE+SLLA}TRguHJv`t+h@E+QB(EiO>bvP;&OSK*KND)KoPYG>3}3!OYOlN;ww2@g(8F=5 zFoR$o>Q-ZUM7mZi_k|vwb%Y@T5B_c!SmS(diE)kPhS0-tg+MIkVZXK&I@OGCD$h}C z&Ogrpq29k|N=H2S882`~eQ&ZiCkZ)TzW;51k!04{zIDD2348K$EX1*2=vjZIko^*C zH#zK@xb6t4m$`rhwWmF?@I)JZBLxP7P3A0F|Ijm7<$%UCy;}A21@ScPFPj; z_R&AM;9DW|_~0Hy=bl8KUSO}?Pm4)z@hlj6c+L_s4|S?M-2W|}Swj!chXOqAOX@?P zvd-~L6JzFbUaZHC-}8jbGmpl6r?`iEdlylcb%pBVjnLzReI}NC555%hj`jH%SDvRr z4-aP%9^YT{O73Q#IsdI#$AumrR|%Zcodh0gQ}^de=~_G&haMg{Gf!)u&+Nc+O5&ln z;c?E?XJpK~b|Ye3Yj;TKiD$f!dFIo2Z=usZcXJ2u{-+-J87)vV-%CA`*>~n0@3t|< z{%V0=+q1SC-@lN(eZMHV`u=Im+xHsD{xr$iH+$5L@1+vg`I7Oyo4`Zf3kx}K&Xr@m zRx-YA&))GJ$UHp0ui+XXuy^d0^O!}lxh6`kzNd|O+q2&Gr%TShiL0A4|Do)8x7L1p zJM?hBD&W)iC3(Ceu+A|}h;ik4CiL)dkHF)5ZUM>NocX(C--`9t(BtC^;ah_5Cu&*G zJbl{Yxh(YXyf3hC<{{_GbGCFXo>8HPXCGl2A)oozSoGyJPS(h zrgnSCz7;Dyiyj~M3DnN}+^QY*Xz^?vdU$RVh}Ar;+Wj)@YtHM39-apT;u#|FV7r!p zf7fpH7+0Q^Ll4g#0`ZtF61JKPhB;Vy*UXNoV_q!rrm6 z_T`v&EnZCaPZ#^eH71`{Zup)$=FD}!#`gWFWcuI`fxLL|PoH7qH8;nY{O%Rl*Suy4 zjjs_{15d7RD~5~07C!E~Rt%%V#xb0p*6{B}HHL*_zEuZw(+m8X@362Z-~Iw|g98Ne zAhzcPV)J=pzVdMXv9CPrr+FTiOuXiyCY6Wt-{RRi^u+U`Ks-YP9(-;lu+DjL{#!hp zf5$_Q5|4Qnk=)I@?T5itb6zg=#Cp9jjX++07MGM`#cwOt`9crRSOFg2&x^(!d&z#} zUPD*wI&;|9Sf>j;K5iHA;r(gtGrCr+pG*H!0iM@{%tPKa9^U`h*LWs{9-g}ec)UN@ zz96v9`}|CdD-XTqc;1qnc?M~GkkF}iv!^-wgL{x?fH0N7I{Uvtvi*EVvhT+p$$yVI z+w%Um?I)6n+4j_R4#6>1zxD3qd(>Q?N@m_%_&zS??fd8$Q`eCKdfSs5z1GQh&3PZ$ z+BY$C#(D5t<7CdZd^?e|?YS>^ih0M$IkEi;k`EE64G(L7BQTGyw;F8}w&aX&VzX~z z{h0uleIwiV38A499bTWa4q{*q3fGQSjP#(BBL$$OxX^XBh=`{p|k-?nG(W{r7j&`-$kuzE*N8@AMNl2CnDd-mDBIpf*) z;u`aA`-$K>eGp^#$ArwtbTaQ<_wXU4e3dP?Y>Gdw<*%Sc{Z z=xbdM4zB8Bc4^8Q->N?_P{~ zYS2%Z+?~evzqvk3q9QA&g1^a z_BPyr(Njo?qx|UAK}gT(us*3Ozo?3p}~5oc|o_dNHm%y#F2R?UH$1*Oer9 zbC>e{-->mK&=V^?N6$FcRxiyP_BGbILJ!ZaLgpdvy3hRm--?Ix@0{-q9_Nft_?dTa z6Jv{q9$7=c{tf|q^YER--QU{hR!_bvTe$GwPvD%>lP?PPah+ry_at%6A=ro4VZ+*Q z#+>uu{F`f-Wa2hgkL259-uAb|7(3>&Jw9r^uL}E`!=<5TJ@+e*&jYq&1mYr}-f}oK zY~k8Z;MZK_P;)*?I_G?6v0q$c-v7)y=lx?0?_HrkM8Cwwv$C+K;CSbhOb$G)eWeGm z#iqXi57<#akDr_4*JlE*Z3N~W*OoD^JnWx&Zj}t*5P@eJVVr;tpWhOu6nNm7UvTf_ zJeaS0yNY!9ss4WudVHKM;M4xGT~c73^B5H4%CkV|;Ta+DeQh3Mo<$&5^L$sbi1r_`T&C+G0G#x0(S zp@-)$f;n3I@>B>7#D?^LW`;AJm-lj~*Z7IIUnG#L4+*-gRK#T0HxN9v<$|+@I`g zH?i&%T(#D}4Lv??6No>@x<$-8*3DvEc?O3bo`;3ZLocr)(1+-~AM_Tw+Uu)H=X&Hl zT`~0d;GWFq3Erh+9yzaT_3(mWOCJ3MIEiJTfN#b(2=vEZ0uQ#l`VXw?{ zl4N2v51ifX-B+^zv49WPjvV>kMo+BVFX-~#y`wSnj`fWgSDu$c56{y=<{^)6VrB1J zvGUF1SPz#>|K?c7$Gl@57vmc1b)hHL1BKiJe0y~h>$$;IeVh?`e4H)R^Lt{)LXQvjyT>9zbAPW0XuT?I_@8I^{)I_x*rL3 zAKnc;IXo!jdc!*@=8<#E_^Cdg4O@JW6P(2Ign)0x+;P-x~^}oHgb+BgU13Uce5H%Y?jd zb8AfhIZo;{rNA>lm_zVf&EcCdXaD zRuf#S4`PhnC?VS~r19kXv!3}Ef(t)6PQDND3HR$l&F|ru?@NAnge_d$QTWQW9UJq` z@A?>H|CEsJ2Wh;DK+W)7_ndp%b2%UCK2^-w&lws!$Jr$3n7HSdv+Z%o_A|-sq3wGl z9})9?smJiJCBILFoFDSvV&1<09AoT{70}!FVv^}aa<=`Bl8GIzT!ZbBzQ1H*1zUz5 ze)`AfbP37b+yy@i9{gthpM)O%n+4*u4{TQva;;a4apn1b=;66e$UIAG+)bN%sCCM?t^XnK_ zo{d9Kj3b5o?>)w?@Cws@%8Pb&++36d-!h?cpU#qk~{4sc6l$^(=P?;fxqm7 z{zQ)tzOU&c`@ojEG4KB3o!#P@7bYCO(Co%;D@-c`ibDVGHTqDl^DgwFk9^md9A$SeHKNqk;CVxNhRK6ceXFl#& z?2i&MALkMq$FOXSiGedr9qJm+e_vx57`E^oClJHYLXKf}jdKi~f5**xnHcICc={Rx zH8LN4#oA+p90PvnTi4;k7!x;l0x{GzZ-fmzwI>dfZVG|9+7oN1x!!u>Vc8NFaU3qN z$K;S>ze{6m(2<)T{MVkiNjmeLAsPE)h0IsiT$a`hZ>+&zT{AkZ;ZETkvj6tO`8-)5 z7T5gv7?bP80yWQTSbK!f*IbF!xt=DOT=C%;_^omONjk3?D!Hy{<;wftYp#$?t|tig zL$1FOuyL-N$CzBl2;`dAuy#X%HORf~>snz8-zj0wnRg8Q)?8PV&T;=!GBM;ety~vN zYv>Dd9$b8)UIR?(Z z*X%Eu7)}@R8uX5#_QXn>b1&7N7?|dIyO(zgAJl@F*yDOHZxc4&!!2XX8S(xQ%ch}+ z>uP}>ul=xo*qCeG7+0<}Ll4)L0$isGxjxhenCk~Iu3Srp9xi$TuDU-9hYkGBiF<>* zW{6+=8K5zK@k4$2#cp;1J$~*JTIXxVu)$Bg0|rV54|8?DYYg0T^nhbl5mFwTc)yj4E&=bRc0{vEV<^1Qkw~sMv_7zxDbKNp*oa?V*%$lJBYjUpa z%?3jD^Ya+f5AJnpvsUQg`b=QH_ToOF$DUsG!+27Rknzhe&lCdt$`}x1p1WUTY|uF# zuRAQw)xPWI8+a!1xF_C~Ouy%|fp7W(8)WVwKg7lyzpndNl2;U{6*YpN^Xt6Km)GFe zYd(-XV_Ad0>gT1j<_*czE`MvYM^A^1V|zTt#CC$f8qP$HjXRQ9`jYD{VGAEMBUj$3 znXktEcg;Ij@+Q~3rj_fMv}TfI;?CdN+{wB{Ab#C@XRxXE=}fw-OPZ(>Yr@Uy0V18*EQ@YJ((sC4ur zbF;)Rv7!5E{4zJQz^~^xE4hzX*4TUdUy?@(w&$0-wXgMFBy7ov?>_3C`y0Mm@42M2 zf6gKG&TCrrhSzKEmdxFChTyoVH-4~jy@|#tAu!Z+5ftYfC zw{m?ct@&IsG2}I^Tsi;5gr7SEay?VXxpMxoajtj8m^If3_^Ib;T-fv_SI)m17%%rRCz-lOIlCz+h6 ztJmsA4-Q9{m<`--^GIj8?4nY?C*U;8;+W9Lt8@rT`kp~ugA!Z(Ex zLiV$_#`aV9lQBH@!(L=Rj%Vkjr_bPL-S0w=f9~X#f6hOg_OV%v$suzM4n17_yGuXe z7{R$nZ*yigq|422(5E9DQq0~#2B;Y z>{wHC{YP2zL|QXC*5q8-oBPWezK0yM_nDZ-haUgO3B;BAhdx_?s(sxda`9FNy+lICjPEs^G2d#_`U;dE{3H}41kCek`*`-Kg0aG&^r zr}F((I`dH@?5V%=;&>8^^FyjH&NO0(Gcswh5cQ#6WEv!wHg!fxgKxtQR(pVVxKg z!{-7q)HOc}o4&-bT-d_LcPcUPU7urEOygXKg=5T`&jezqYvv9ccxq1^CY}4G_Qcw0 zuD70GPhGzwB{Lo=rLl4$9Pp37P zO6DAn5$uQa$@?E(@B4i*CN{pA@RQfDcD%rvzT|ps*urXYGJw`0%yIL|eyh!jGey0(z@!6Ov#?){> z0Uz~ja5nj7V0~{fydSpkT`v&B#X^qZHI3nO3@^u+H3td!s6G2k*z_d^&OiL{T_+I3 zB|?tjPK|R6<73R40|jEZP{?b@$91SZv6AN8OSLBkrn%nk*W{6+=*+^sZ#1Hl57rXTY=l`JO*7;g9Z17X>fPvC^PwRfy7?ueh z$KY5O3q85sEwo~oFKnF8+-VJaPyg0$gxSg(;%n7_I9&tI9X|3ML%dUljcb4n53#bg zQw?%`YR}jDyeXdV3$72oz$>ArKKwfb{a$0H)cTzjo5_|Rp9(WxavD?qll36oG$gyFIOi4B=G7Ybg(FTF@C z$o=CN|Mc#m@ylF2OFvC>^(=8#a_{e^vGYY9DdZS-ig|RsoujS7mYhx(sCVvfIBLBI zOK1O|NT%L-O{?BNNo&SS=I&zO95=ni`G?o_ULnTB#yyOmF@o3dyQIJx-O%`DuD`&q=l)ZFOO6zybN)y&=W~Q$U;G{_IDY!UbHrGC zY-re05Ar6biv+LX_s>GE;U8nnntuw^aEy@G{9fa}#;|4B!Z%hR2F_gO`=!P?h7DrO znqdMxR(tlRVFOQZb>RHN58q7!G30M4ICy8~7?zANYxWh0q4v^(VZ-{`6Dvx`o-j8{ z{JLM}PIJB8$^B&O*msvqkHE>pFFlgu<}5JgE^u9lgTMcm63FKkfqkvL@S$|r_&mKE zfZ1j$y)MtPUKHsGsLg`+^Vtt%q$sy z*zx{Hk00`Eovkaw20!$O>&*Ir0>9|`$8VCS}`0GHqPhBwB~Zj z^h5pzA)W)m#%qSfnA~#>_6$A#Ckfb(5S%CWe-wxv9W}s)hgg>tI@Mrcnwv$kIkB&M zw3&3dKG=f6p(nnB1pLrZ0Ln!^Ov)L!KLfB@b1Tkwf6|*6!Vxdp?b=^iwc5K`?#P)Z=eEgm)VBq&gI275_oKjh&W@cu`SpHl^DaFqZj4>kCM zfQ@73{omr+HuP|vDa<5fF8KZ=v|>hAV_sjn?8miPJM{RWSIOsU!7=k&xqc{Ji)*>i z!}XfbPsm)vJWz1Vz4gF6vc(U4oGa{W56mGQHm>KaF{akJ2RN(d`b0A4Dfa;O^cXhe z+*@p4%4P|H*xnMzwZ`^=bl5nycVb*)qgLj^hFEKC>q+Oj<^F8#^<%+@ALoJH1EDA8 zO9krlzu6zYgB>^V!dGi>dDyrH7st5PU`*(VZ6Bd^c1DGbxj6s$cb@bYdv|Q;;rdLV zp84#sekFmLwDy|%dM?)*+j>v!A)RY*tK@oz65Fm}^>S{&)WDHFLZRs1*+}a;C6x{)1x7T;^IJ z^u%_1%<*0_*OZdC7Fv6QuHI98JLQ<+!EXA{|3meuDH@`gOReSRh>CDHSM{Kpv?hYI84Rv>Hxu3>` zo;*hi^i$sFsWe_s=#D&rc<>)-kUUW5#T)B=8JzVz*HD3mgpFg~ zF~*f^yU@e+u25s<{naVvRzLqD`0NK8&d@rc#}9Sl{PG>=bB6togxt^k{h#~HT+4?Z zu1ke}Lgt!5W6ln1;m>zNE9QB_Hph%SSLpG>yBA&d!}!}mj(MgSS1$S$JGhP)*q6*j zojI4RBWCQe;o&amvX*N{@!Jt2m2QV)|%_t7+0<* zLJt>r30yY`=HjX>7uCt6(RhaRp+1-Np|aQ$2$ zKH|@P(~9{x*|hwO2t9t-3wnL5kZV)(AFlZp*IuEA>s5hX&s@Y@xptAR#r6Bp!}Xy+ zTseRCcq@Um)P|gY9pk$H8;2gQHw5CUT;1&dkAtuJ`C;hsbFskvRP$dZY#j3vF|J$- zhaRrW1-Np|tnU;vdspi`t8}e8&lr0A+$^-t8M<6&e7Cs1l73MEF5Z>(oT2X&Gy7L# zeoZ>~YHeN$J$z3I#B-zIo~6&87Ff$1+>gh&ay=M&xSkQP&vl+snASuy`D3AxSN<)>fmSDjxhnMdIaHv}ZV|j^ zty-R^`4-n%p@(Ztf{r+{5$_6B@FH7*{UNzq$68Ok9}@ z?rzS~4#8LbY!iC&=kK^$OY-OZ=a_#PZJ#o=X z@ZTyh&x5}DX5L)cH{T%EXW#t&Vtw{~S?KZcv`~F>kBo^<4IjBCr-m)H&;E~3 z`t1Lx(BuCr0srF#=MK+70w)jZ%RKR+hlk&@1^PR4 zP`_+*O2Y;p+0SZ)gY|iS=`zo^YxZ%T#x)MU$vFS6)9DQx@)<95s@3diZdS>z6ZZ51 zzvRomKQPDmePJPi_%;`~6TOb#*9Ff%CYf)XJB4gBjmDYVeenIXt-5a^t>b%Aa*dBZ-zaQa zK63ut8#VtmV=b{fDpY>dk94j*xnj?QF4v9o$$Io~Ij4Oke@nPaV4jDV z;l&2Nyq5m<+KVOg+%0%5znpvgu+}j#=H1)kWS`9WJIVJ5=7XQ_y%ygm(l02~82Q^3 zJvALA5YJtLIms`dQ|=Ex*yO$#rt!Cgdj+q@AH87Td9QT!7kfy572WD3Fe{Ze-m6E@~bxR>q5Wc;>q88=KE&PE`s^RP+@t2_H|IXQVN>h#gluZ=yBZhczUF?oYkU3}47&z}5C;ArWXVP=$!g;Ph z{W33mJ)K})eu?jS;Q)a}izM@KA30y!W8*qmXAXM697jp69Nf3x7sw0VIR&_Q zh-pCqJ@C8AbGeUrZ+ugDFl_(D@UQ>>2_Dwt!w=#?+(E0o@K1*;u10?(0 z!ut)O#)STP0slPY%l!cdI&=SP_WxafiRQ_v`d}}K1%Ety3y$e4$?)bi#I$?Zc+IXc zX6~OtUBj4t!4Gn-PtEf{&GXbeH<7L{d0r;FzT~-j@DcMcfv4uVqICFlp3B9UHTwv4 z4dXQg=b85dUB2&J1NLxk!8N}^GWSW21>W34c`bLL*KS+Z5jXb%zMaEVlCh^3GY|V> zp5c;tat!4Bi7=mFt`A~dxp@C$$C{x+<-&fVfDL~8S|`rGd5@J$O>&I*xj$@bOm~K! zn64A(`@9zWv4UfwZp6mZY46ZqE;uIkj^2Ag@LGP)6R^oKvG%Oc6BG4lt$kj4IKa0B z*Piv934WQQ7JksxUc(0c0fOV@tdZx70`ollc3S&q&3P^F^67=Vmi6-rj*0#)z2{N(k#ooaq#TKjs3n24F4p=Oio^O2fw`5rAj z9KF^2P1#VBiDAoLQA2oH|NjYZ3D~?Wz-OC7C1F!*zJKUh`-V_!j{Uz=^C5}%bjhu} zJJtL*X)Srwn8=A-`cm^_WY_Zjli=vB=C8^Q|MX_A=W?;0y3xHrf z=WR)!Imd<`&I1Iv*yqeSTx0yB`;OoTU9Kr-j~YHAb4mTv@;ewWkh%y0X{H3C{5v z$<+sIUJ&2~|B3H4-v9P_h~(BcQ|^u2=fv){FH5f9Gvr(Mgt&Rwr@Zg`Y25PtzVrhH z)=lo)fwPJK31N#5>cyD#_~NW#^OE2=u;Dun8|0iHXUl8318aV8{5$V4-v8!3RWj%J zMdAN)_Z@Ij6wCk1de1u*6DIEV&O1~V(U_a}37O6y|TBpX1L{UBi4Z+7{!Rs^eqM?~bUm7|6x^OqFxK z_!%HBzj83|<@lY9dR*R(VZOIx`(q<9CB^)TM#kPk$0&vQ&pQ5maOxW7YoTVCFF>8R z@tkyZ8dS%}yhi23oY!6-bLy9ad4=P566(#toH(xrVobd5`!O-^q?mI($BoVJSUE;1 z%=!6)66zHavs#( z7Q{A**Ks>+?u`G69%Aj^v+;UB9oqXC@VvG@#!HNOP)1#H%6KhiENo{%tAQAE8_?$< z`sP6$cdm!1{0nf?;rwwd`fz>Ip4Vu~>Em_~*M;k!K6p7TjsyfMFbqrM!-&58CesSa&y9%%cF${AB1kZVWX zS=vurlE!n7+R!Jj7o2C;FXLGX#GL$iZh*{kc@TA;W3DadfOAM&)_Gh7qK)tCQk64~ zK_DLdzJR&#pnN!pw&siLDb80vmD8p_h==QoW1j`0Z3~cLOg+ZRHaYtkKe_eMC;P}b ze_R(|flPb65I$Y1Is1E1DjgNb=+2&AZ+mG)Y$T$vZWst22=2y=B z1Fu7jnYoVyF`l^~`sYFJ;z@ic<9PEyX3Krozjvp7TM%_=W44r2#xac#Mm=t9t^&_14NwiC%N zt2#dBdpWkuH7>t$FyGSgJ0-?%Q<$&g*m50Ig53FP4(4MU8M~E^Q3`XeVU9l^L|q=l zkcVN;`#|b&4|a8aLAxI0W6t|(%DK*Y9{Krkk6~X*IsNlo_!wmV+3)HMN1Jo!>TvIK zb+|urELVp%+*di4ALmn$S^T^<&>!_?shqyq|2fFw;4MAe!}z3xDXu?XS46 zcu)Ot%u%4YYdiC@oZa)}1;=(F>i%_?c=>b6xOvbY$22|!^|-Nl|8My=b&cz%_VdAQ z3}Sq}+Hk$6&oF%txZ1o9Fe#Dkps7V&mo~Jm{CW5f9omb-mB2?oX;4dI+E0=h(F8 zx$63M*E#2%J_%??^W;T;hUk>EjY!G9!w_`IG zb&kCNWaDgvdS?**T5LOMn{jiU_%^gXAH;)of1Nz5a`y3hYhyA0JDfi5RrJk+eOyQ6 z)MsuS-}-zkYSCj@+>JW@`~tGE$bB2miP=1ax^Kg=d>hKlW*F+s^;eLMLm$4)kB~7w z#(x8dxwtmO*|+%wGPB`0er)vR+q~`AjES+~`txm`cWmaO&RAUB;?~`xj?H|var5Ch z<&SfhWAhB^em>OqZHSd&@M??=arAAthnvl$7#r?cz76*cvzZ=a!+pWG$vHM3#n@Cs zcBbmsd335{GXQlTYpx-8&*0i`YR&Wfx3~wPPE2_ZYHKlW9(ewn%|NyJ-LZ+obSKA# zar@&CpRHBLa^2jq>902KI6RNKf|8!!YdHQsM4jXO0kT}l{W)3%GRu`Q5KGsFK71RV z&t`LDj17JGHuTAR5B5z`?v4|8-hJcPTp44-^X_BSVVuN#p0+s-_f0<^j`No45D(5J zb$AeGKW<+CE$;h8s~Dd+OlLYaPoVC{z_I*sxF6d%SEJ5c{sh_FvF+Osd$SpbI(2yM zF`Kx#qi?gh8FfE4w*7HZ_coiGVr;k;{c+xNY#xrW;WdEkfPNVR zF?mVbjBPlG+{J)8Pl8;V$Fxn|At34u0J(>I?J9M@dmAh**MX>W-zB#rF4sxuHJgd3 zbANMfHbC3Q=W@qp4(g115XcVR@ACTZ<~mH<%$56;Z^QQPARb)H{{8M`m9vlM3ONs+ zD;I*;CM^x3FYDtzXXjX{y}KuL4GZ2|(a&Iz9rW*G(G4=QnSr`*LtCyF#!#XCoxsgz zDC*4hKoAew`}$i#X8PBo&OA(?KK+>1bM)!okBM{O+q7|PM#tDNCf{a7$L8r68|wQu zT!WU&D={|A&A0g#GT!?!?uj5jpXDL*ZN7xeY^KH7w2ra)z_FPhV?%$htB%bjbFgvx zqfWWMX54d_>wtOiVBL?K`;GbIwV4O^20P;Bf%h$D!*h!V=iQDtOsAmNZ2F;2Ox2v0TS$oAKvBv~kDbc>9Bx7ta;{d}HkFGk*h7w;1NAyazZB+WY!vL1y}lnQ@pt zZG0?`bM)Uqo$-zW(Kipq;g4}BWH!bPsJmmZ?(6gXH~op8{^BwEJ3IQs)Ae78_IBED z7;WX~-|p$t|3=!+oJ!%nrs{IcJcx(k7l$|R*)6xnQFmh{mOd67-}Je5sM8z7BMxiI zOn*A+u7B2j{|g{%t$O?p+|?&`-)O&K_l35p$LoNr&wM}Be$)Rz+l-sKB(B%DKsGLQ zs6Py32Yof?e)0+Eo4=RU3$I~z&>ycQ)Unt&UuMHShlgv!_K6_IOM6};Y0HB$AIm9_ znLqB8)I9*igZ94um5`bK)u_ArwDI+M{Wtw5QRiX)J<@C*aT5{|2WBd(0tAIGx1Q27m7-R=+zXMUn;^XHd zv*8{PXVaV*c>bHeA*eGJKZci7$6|QSu^AR)!}yyM1J{(rFdlV|GZJJ6ao~KpI84_z z*ieV#leo4RCl9Wb?#kK6HEjp` zxW37m2iF*N*ggSdV-kDjH5bHw9^{SL^7?PKyk}SjHAUmkP0m!#yjO(bJwmirEeCWR%jET49!)rbF zxVa$u<3S#W1!LlVYqrmz&b`aErF|Pvb20t~He5fR9ls+`Z_YZt*|8-q{=Aoq@fD6=?z{9m24n}Zxfm3O zG0%U)>3h^^dkM%6+Fk(iZHe*OD(C!s3-a@!Z8;bp?)V*#dUMwCK8`KdPu#qhvyQiQ z{LWLqKE|7<4)f-@*g|Q2l@q5AL5#`AIIB9YEirCTIc?{H{Cv1CvyZyuAAmRyAA>kP z56WGg7tp33SBK}ntMdcez8~8B4q|T9oe%Q;a6GPU&Kbw&{e~SDqwyEfL;Fh$8lmQ` zXwyIKd3|AQJZQ)BjhuP2pXWd0G2F=6&-35nX|l?hKe49la*!Qt^Io4mZ493Oabs|=q@2EZ z&qiD7+QBx@f7jPQZTookRXKhA3ZgCVJ?vonbdc-oWNrJtj#W8*{Q;uwl_2-<=lKxy z(l>o^uDHI|1nm!^oW6()=h=MHAN4l{*?gG~_Ho=Lw9l~I5pDA~8FgMSxqj@RKi_6E z$joK}>a<}jb}%;IW^KsKW+Lje=?}7l=S3S3bu2dCo0`oe)M;}7hzE6i%(!l;&zOx9 z2ilpRaj5&}2G2L1`?ijW)1M%Iw@67uO08&XFGz@BPh>8`DQBryt(C z_%X5V$MmM!_%Xera{8JGa${od%~=nRIKG}hy(OsBdbrcEnWZ+R*2DFV&0}iQAKVVE z2hJ6-v-QAphHd8gIEb;?dSKnhi}x#W*bh-T{agzoUT1-LEDdt~a7~;G^8GNr(^XDC zGeKN877u-F4x&BfwuU%H1IRx=4ui~cdjNH=Bd!ZOdZOmrbcf7r?n9k6#LSNIsBvuH zZfD5ME{{6xh=Uy;phmlGK-4q*x6n58y&puo!$CY)_i+m#qdnKFt$pIwPUZA-2gt>Z zIJth>fFDm)y8mdjkb#yac{5sE?&fOZIu(RNgx;ZRnczF zUP*jy4zEO=cyTW6=!u$tj&VG*xg2%caP8Sad&ckE{SF!T0LIOGN!tAZqArgQwEi79 z^$a(z39}oEI_-LZc(eg=k4b?{e=h3OcX8u7dq?FQe;1HpzZ&Y?b6p=Vp=~~vL!I{{ z7T?p_M?bSbjNjr}9d&me>GL6w`QmxOxEK$wGnUu4sMC+dv_>4i4ug#Ij_-l&^R9(CH-yi7oy@%ZEH2btMCkGen32Wsb! z)!DK8RCR2uIoj@^Iu;+#e;bR}7&pFk(QeLsujTl<7xlRLZcrT?zt*uKrv7~M9-}!i z5EIL1miqJeO|6novrfsf~$3cvtKgf>tQ0oHXymG!ut&@+TL;v*0`(S_mdO_yT z-CK~E%?)Z}b2kBPj_a?J=NubeSNw5oo$$P7?3VAtjve<}8)pvc9LJCCPDlS|)ZI1m zt=ddg9UFsrTR!Wcekh2?hM>(rNwK^Xy5{F1)cqWLLFUIh#IYHnHkRXfwBxWm$FcbW zbsp}yZCIY9dY0#L+U8t;3F2X6ZH#(z)-Ly1%a!LM*WqN49UNmX5Or+)-L=iW7eTa{ z0iAug|7Mf z8g-7*A7lsDHRE!}e@)vQ_ZtvxxJGzv0cy_pGof$e&lV4hj-OW@%l~f2=5@8P@wY^q zb7=X~H!c-986{=@(T;kaMs&+OH+oIiA92_rhE-rBV@m|qiLvz&b zbk(ysPIl}Vqq`oqL;Gm$=a{9|!y&3mAEQC!{XuqcJ@{+5D`bY>7}RNF^TE1*eb~v- ze?;}&F?e0z^`Aa1N1p#S#-pgaV=$)n+Rq$Yf@sHs>wr0vo3FO0(--Yl2JxU>J;>zT zUrb)Da*oM4UmC>gh#j=u9>g(NH=ky|toGUX^b2!9A0zX!}s+adMRTr zjG5yzjxRvwi}z|A`$mu*)Sm~Uj>Yx9w%JF_%-5Ta+#TZ;l{4NKK=gAH$US`QpFpq0 zYdCS7M;y6}{rxKE7(aqIw=VXKbsLajZ}Bk(%Icgx8;^Y)(_fd@L1viUj5@DbQ$g-= zIa)4eT<>Oc3+l9)2C{?W3oHFxeG4HN&`kD=jTYo#Kj>WZ|w&}}V ze_J?mn_uR$k;*v+uLJ)2<34gBC=M6OIy-$f9&=^i`c5Ce=V4yf=dWpAzYT*GRG0dk zLzBBWGhWKcuL5yCx!&xc?eCyvK!(i%Z5z(ir5?|J>e1IVAo}7uw1YaIf?Qwowe9xQahxUHvc+WZNkjh|~<)iIkk+NRAy z5N+ICnX^AXoImEynC(2^{82`tuU|kM<4%wr)Mp=cY<%Kpz6?kD;^%+f1NdY7sB-%G z6+}OGf$U)XYk}y4zTNf9wx7!!$l}I%Tjd<*B@q4I4RVi{(W0&8^1QbFn4eTRebI)# z?g81s_0^o1nQvUox2T-sJO<)8_k!GG3R-T=6SVEe%zcJ>^u_xY`f}%zea(q^2=wD( z?x%8&^D!tc=Cf4Ca6V1je#|GRoW4E<`7v{ytq+P@8R2wsm+`o{u+Gm+mdg*?@8&|CS5?n)p-&#nrMq(W zS&Y`lIi?PMSYB*@4&r%b_z|zUAo}1z-k9w>=rddTVP38+?c0Dj4*f7U_lWaLJ)TGA z_e<32m-hyCFozi+>bUvPmglkAeuX-1dHuG7`nQ05TgJ%GK4$v`>a?8;qF)~5tozob$pEZ`QL2cQ(GTn z;zS+SmN9lwIoBK4kDm|MGyAAZ{xyj6@G;2dfpS-e_oVdW>Ja0tL9`+9d{`XBgE4WP za|}Btxkvl)(r$H?bG(tDHQ@VVtmezk zTgGMgI*jW%kRKN@^L>2-8ONYci>m?k&s0udSAw`-T?4X%ZQmEyjPHv%@-r6Y^u;>k za&zQ;s_*M*$jq0U<6|nPFJ4pq99MzN_r>!+&e!cKr!UT*?`u`ad|#8*#>eYgmD3m3 z9>*IGvSV%3d|#s>v$za<;x%05^z|r+V{vXd$2`^p`M&x>7UzrCf6D3WR*>&&L&)kt zT=(>Eac~^QvINLICwil8{w_n^_tze>169Y)qx~EkUb`qC1+siLMZGyO>;Qd>VLIxJ z*~N!3Y^gdH1II9%XHe(i#;^t2KBheXX~P`dHMqLUiRlL*9{rWG&ifDF7tjAVUyR-2 zdI)vj*S3&wAES=t!g$OV?YWmQXJWv;hjHBo@^R)|9snZlBSTW$P#JVfR6^&W`*qd+!~tD^4v>I#{U7qQ<><@Ck- z0j_}wAUoDZjdSVlOFU0}U&MZMmDATu5aa3r;t_!SnAU~N{J3i?t8)7J2*jA&HP1cS zkEt3m^JQy`F>$^rr!UT-8x!~A42ZcAJF{cFwBXv`i|f?&)gJ8yAfETOcknX= z+Z_7_l^+VuV^dIb#-0Ox^K~=ojMcE^*l%jTjm@=h`p=@y!^Y*MznWYlL)?p(}L zIdfnPJh-p%*b3zPxfilHKewx#ejWz7ez=})0@2RmpQ3HXWAnm1uTwew&?ogRFV4+j zAkHO;?WXoz?x%6F4puqG7y;tB+8<;G{rYS9Y{<-)#oGq5Q&mo1Z-BVxjsh`09&vka zAIQy@I~P4wPG8S}{J1z5eq7zu#>KG#vOQEzU)+zl$6gDvBW};_fL@Es&5_rC%IS;O z9>(S77`NwgKQLczj_p)VUz}e*$5kNnbL8F`=W9ik)7My#?<;Pf6^}6=EzKD(QYmVB`my6fiDyOecK#Z$D$d2_; z^L;%JSzKICs+_(q0rA{&Zq0VvWZ!U<3>#sf9(?HZQ z8}5^4^PtMzwX_Ljem+;JjgQTxjxWZ-qrY<2xd%5VpB(fpHqI>%Hy_UJnIJbGp8sa^ z0P4iTwc%du=fm@#Hhw-mRZbtDfq3*+&N}yF-xtsSIA1*fEv{Lp`@Xm*@2EO9HyyOi zxNPn@hdlqy*Au8y-<>nA$$LOtGbDds=Dy{wn=IOKF*m53`Ckm;`E1uBj^X=R5wbWx z)U$YbZFK!C9pi`C#QFIha_$$5=Oqwxvv@d$AI~?CQQyUnIdLw{5BDkVy@!K%a6WxM z??GmM+`WL;7xVKb>TW#D(f7mLZ@|jJLiIHuLp=n z8<6kk6v*OmK2GKIa~p_rZ8)!ny6>kaWah_>hhtk_ccRXDw|G`Z-S@Mn>ianFqH@MV z%-!{qMcenYwd&K48xQwYi)Rk%ZalnB`hF<$^J)Xx8Y*WzT-zMS@>&n|3@8Pne;c23 zz&Yai%0An>xb`fj1=?@EI2Ny6>^FUmY5JF{-1Ij@yE$Wj2Ys#``kV*iVZPd<&hwxB zHugu_rv40-+dVF?e?ES1slGp-ud1AW?gsI&^~E`AP7aSk-*Wg-JViMWzr6Na4jj+) zc^zjAmh%><`#IdC`hE_RR8ITPL2eGb-uZs6fQ;k%enzXDejWq4ezrwx7>ITj{~&GC zkF71v)dec2pMQg>Z*#+Y`{5w2N79lY`s7g!+6-jtbtTlP!-KNbl~cy+mfPoF(+@$v z<;eY*x}^P8&e%qR7|+chJE+qI~n@7eyU2XhadCt2woPQgK{yC1DYa6uxs$4&TFUH0( z-Fcm>a`y2&Bi^@x?BE=|31Yvk-`BKF+5I5e+zzsXHqU}wn3i;{9H$SHX|IHp=#si+7`0ED%VqVEI-%doERQK zoomaV*TYrEa^+q_Y)FrSXyfO)ulAeG-rAU>C2}Bz=S6+LT1-bVI+^4C}m~CICZ~CO1 zG!4Z4<35lb+oARwh>7b|FiYG>Vy8cmRo_Y z2iZZnZ}TE#meY9DX~Xl)4(j_hvmi5@FHt9+?l_Fwx4Fl$As)1G$6?#IxyiAak2=qL z*M{@r+g#(=Jcc?kNXRUoQK)mA=^#6JUGZ)DLuNKy2aMmf;hOSoPIqj0 zed5}2apT%KPIc&;^L~`JId`MA?%MEPhd8)v_dwO-dSfp1#aOy)opR#BHAK5EAj{=j zt@AU39XvNWsodh)Ufb@PrZ3+AQ^y~h_m(Di$8N83=J%b}?*g}jHq4s`<87^VwmBZ{ zjDLW7C5ZQy?!oh)erQk3t3YxHDgWJ&tHQ(3c zs^|Nno%wo1>#ncWVtn1vh%cT)=8N~ujF~>|SRFM#uInJ94av>%N|iCkn?Rfw*Vh_o z`@SxMEY8P=`rU)= zUzdPGY|+P<$fA&c|1 zn#$?xS&*OO(UAGRc%KyKi+Vih>ot(?>m zR=FSBttw}p?}6y=agZI>KLrx{Wj}pP(6;aIYL(O9M#m%A zoDVzLw-kt+V{$!FhwZ*vr|*kF%zduPXivSyY){mF+WrVy2ISh(z72@u(9hB!_lWaL zJ?`=3^vlm&^!o(J4(6~Ih&paQZ11Xa+AaXmmYCT={f;2tmND}Dr<}Gwf&6^fR}RK) zVP}4?N4*L(S7nTgeQ{VYCeE?h_CwvbrF|Pvb1^o3<~l(A`WO>?>iHP+vlivF9SCAf zKE|Iw=G(H(yv?>h>V7_4&-80Lzo5=};JHs6c(DIPkm(FUoqk-MO0*dhb!hijoGbin zX=7f9dUMW|$&T$D)cv)^yvmu!iygo7)bEqvc5v>9599Xd@dA|-&ksS2iF>CV)IS5{ z+p^7Ti(xSrbw3|sUe3AF!|^)~b$@-(Z)4}mZjS9ssB;Z4Hrm)x4#u0n+H!pbb^7%& zURQN|jI)mIt7_|G%Zand3`nM;~TuzE)MaSXFSuo}k<# ztc7KpgtFXQ^kH%468oZsKW6UNB43YMHk9Vt7%pseP|A&`l&y0?^tml4_dcbo#nh;= z9VnTmjQcjr}4;Wcoj2wX)$uuRhcUUIZ-wxV7G8~l=H`d1y*iTv% zYg*Am=#{l7Gq&1jeS6%;k#PY+*x@vkfPE;jE)B ziDwXXIw&oQ26GqB-s&@Ju1D5O=}BA#G?HlBS-vW~(|S<^*~9VUduT%+^&lBtkY%eE zC|tAF*VA+!qo!!Dv5;Diuw<{hi->(}PdMMD>^m0x`JQvX(N^rY;>c3lx==f$P&>a+ z8&{}(_-CVj8;`j0o^TKB0G|z@7W6&-KO3uwyk(DU{#cEBY$C6sv2t^mlapD6v}0$t zai3+y@e5~{*cvha+@l;{Y7-=qhl|@O>d4yc$(qF3__eJCbdu=hBo-Of8(+qo!5E~r zBWu3LxKSF{ZWH4{v|}-so+jp`9OQc;g7`B##GwKGMjfatGa)rWCwE<8PNbcpP7^UU zK3+LJxi>jpgF{hdQSHAGW8>I2f@8F{8pknqZMQ(SJ&AIO_1-2%&sp0OV&*M&yf{Be zW#RlpGZEEN%-}y7FAfJMKM!9S@7=<=D=W08hhm(^xJ<*l*l@QLzkd|`E|gkjYE%6P zfKN(ke2PfplYv||sE$v%vVrhs#O>ovNh{Fupyfc+Ev3VYdTS6q-K6oUJlz)54pffq z;;>r@v?6E)5Pjhjm-t%~d@T_D;@dDJQye=!MW$;&wV({B8nia3Ir=T3&s&%^K&yiY zJ$>NQU^)P;584p)pZdf%XKCIpHGt|tyz%2W>ws*m^-$+{?LixWIPONEjY0T?w^=y7 z6_}n1gyT{=RRwS=a$o%`#h%=f@>#F~lUsqws>m(hj`DO(sP$tat<>V;i$09ZkB;_T z=!fwXM%t^TJJPqI277ZSrwjgas-=DwL|W!6cT(s_HGbEK9UqdHYH40$QiTzY(3o=H zW+fi=(@8?k>lLa7mrb0SO|(O4o{AB|{?EveD2B%b$_)Yz#cp0AeFIJ^{|IMtiN^Xrm$ zPA`e)HYL$|wxq^^CDHn@}_2WuaA!=9ix4OO0xtAI^gL+&O;amLbk1w60F1wRSioC4A)*Y3&lu zObK7FB+WvGYRTu?+@r1B zz3T+^rCPb0LM!>KTdetqr#Zh-&5LxF)aQZmBWD!T*r?{nV$DwRBd@A6rT!Yxx;c^7);d#7`+6pkRu7%2rhUy% zqO}^&qo)1LE1soBP#9l4OO0r4kO=oj5@~fwg!_Amw2n`N`|pXgh9|*&-_p3Rk_gdP z6KNfh2+&0-$gT`nSF_!%<3TEgt$Pp>L^ZRgx$7r6Th?r0P92ujzgrZVfb8KSGc8X4EpZ6rz+)1%4 z?eoQ?noAPl(*B;(eWbMJAa8yeM}4Kl^D{ZI=0=I ziRb6O#PicRG3sw5);uyX>OUpc9F!RK6_cW#o0L@Zgk9m^ZDpbRyiZNu;$-BHZs!q}4eQ?r$X0Ix-3Fc;K-j*ECjobuOWGTO!;$ zCPMVZL|TU?LiDRdTIVN1v}F=Rb5|$P>Qfr`c8L(x=b>`DC}z$Mk{d5)OnU8b7uj3= z+26Ze&6A`rT^nl7Q_b2KpQFO3ME@0PejI8xFq?E($0N;n4kGloPN;Qe=ts2lxy2Z* z#lx8@p>okWOU8O{zK)vw68>pgsiB;6+5XZ8(!<$8w57HNL7jNErE8EPJ@nk|*!mern_2r13O1W3E zL#^*s>p@RTKQAsHYW=KQ>nZFu) z*0isgiL|=v+%@g%og`ZL*>6RzX+Ll1JT|R$X)*SVAlfz&?sp~9+946{FDKIKl?eB5 z5@}tK1ovG_Igb z?ayEH^H=??K>TGre__vG+OG`aFZXdO%P;2n3wnGIl3&sDSLt{hTz;XBFMZ_K@OZpZ zei^?8cv}!2TS~X9Ol=W{(E`_=7I^*%^ezo5q{n(z}E90O7Vi-37E4 zh<{kXgV5=2pnX8yLAZ%a?*~HqX}n1?jR$tpc$hqW5a?hK{#>3u6x0*c3v?Lha8Pg1 z5g>e>nLe^IwUrYgqil-247Sz`ayP;#jh`E^oGRrsDW^+$vy`_;d8?GSNqM`JcSw1s zly^yax0Lrtd9RfBNtu`OekmW2@!ol#fa|Q_5LV%4?Hyk4yatmWzY_ zRhimGG3Z$$f0#6hPh7u?*#(uUZ4I-b96vWq$_u3&F6Bj1j*#+VDMv~b zDKC}sGAS>Y@(L-(N_nM}S4nxbl-Ec(PReVgyiUsTQcjR^qLh=QoGj%ODX*9E2E1iq zyJoB!7&VESi_pT#R0l)opS!9mQymqb4kdCgg-u+)ix*bZ_WyXia0c$6cs2a}c5lVTOOHvUtYx3)SdR*O}pcGgj=DpR|t6!X?ur45y-T~(U^I01a zC4KJ=zS>T23fc^`IcN(I9$`su1=tD%pi_Z35|7h%RrgT;8aHCvU)qf>s<|_uf zz5lt`Ri?TrZn*XQZ{xPl{~z2cQ{6RZo72CGyK4oPtbH|Ktk(TBg5@ex`x^=$B8+ry zzLXzH`LUFrNcpLhpGo<-lwU~srIcSu`L&eaNcpXl-%0tsls`!Mqm(~M`LmP@r2Iun zdC6z^I@R3oBKbqgKc!qKWs29R9N%=E#seEH7i&?OI^e&ADMBb(r{65Pm-SFY@j9UN z(V$~M$AXRn9S_38dg&8ECxK1|odP-)bQ5gJL1%%^2H{Imd8IUd=AJ$ugs&IU z7l3j(!K0s){iPfr0QDy27jU=~*tc12w zW~FQ=<(g8iCFR;ut|R5TQU+44C*}H5wwH1PDL0gIBPlnQauX>xm2xvFH~|3?syLHIC3ct?qLCn-BgxwDkJNZDD+U8USj%H5^hL&`m+ z>>}k}Qg)ScZz;P;xsR0HrQBD_{iNJq$^)eAA?1Nm9wg<#QXV4Zp;GpgvX_*HNqIOB zKK%a(!lllKm>KB(-*UpjuFl6v?S@vLj8*tR$i%@0i=zkhE zm8oM4lYz2343cuNltZK(D&;UKFO+h)lov@kLduJ!94X}}DMw2=M#@X1yj04|q`X|p zE2JDN<&{!iCFRvpUL)l=DX*3CIw{9XIYG*aQcl9EJoX=gd>K35asQ1Os!SdKKZYQ7 z#1sC0!!fs{EZ`$^ef z$^lrw4@V4lH|PERNO5hQ{|`sXxtr|K)&K87%&sVvsR93RtZ;uf@bAQkd)ACMAE|krRBNtsI7zPHjHb zPE9_|R!~pNGul;YdBU06d@8IBi2n;5HSq%?{uVI&mzJlKtJ3mxFSR*3ee;QUY@eRC zJgHlimSUT9uY3J*l0WCqIlRSTNh-Xyi%FsTC_-|8k(R?39V-}Ek{^j|`sI zNQ)hyK_vNW0RF;&7Wh-JA}LSvRi))=I%@NG2gJsHi%_gBPtsMT<#{w}^H&Jerf>dg zp;%j<9ji*q6Ij&FeI6l63yxK6Ax}(IrRCWpTJSdmM3UNEH^tiWoKRI-p4y?d{WhW& zn*7~Fv9>&AQCJyrR7NrYV)}gYA_1sQLHUbQ&gqpX#{Eq(4gRgGYfu!4JPA;h zmcOJ^dtLNWyDi9OEYg<0YFDM@ufo*cNVPcz&nH^qQ2<>p@)y{uwETsX+I^%qd;%1Y z*m>IWSIMgMk=#D0otqr~5Rci>|0;`E$Y1HI((<=7u?SyXCb;k^Q)XHmk^Bv-DlLBl zqQ!=)!Dmf*hPMYr@yp*+s?zfJ4r(7Ez2X1N$Q`O!TmFVnm6q@LC7MZ5{PfRX+7w&J zcji@T`A%Cb_LCp~$b8a*YqQuwz9X(m%Qv}V5x#^%GUi-x?H60fH>6c*`5sd&!vCI3 zEI0;#^HXdg-wRfysPIaX{T-;GtJ<+~+XYyb`7ZoC8P5vuaNO;uXH zSD|)q=?(w?OP(#o+Vb5+Ra(AVkZ2}GsM7yxi&)5K_o}pfwib)$kR6v}@ColCi^|la;XO^oQJCzbL3os|0*}&F90xicbOPu^ z&`F?^L3os|;#3eGrK>m{gh%PPSAj?AD$WJrQM!urL3os|;sOvJrAwvA z!^x<~_1E?QC zU&Y2CoJqVkS8N8_9JB=pcO?~gR=r|t&^91Et6s4k2O>9&U@ay;tO>sQh~6{55!G>T88z7ogG^v@2*g z(C(l;Kzo9^fc64)1?>&$2HFSI9kefKKhXZ513*1M2Z9a)9Sk}IbSS7Ns2Auk(BUBL zM%?Flt*SV(GWDB=!KJk4eY71&UD15km@uL9dy1vaP(Y&jL!L@KZ?RJ5y1RX!wV zas_^e5-#y4mD|fypVsy>%AZwk|81iFXSO;058ZP5pNr(|zb1QG^dMQ+pf?aJ>^ey8%gl;5q~{(qNywSAv*eMeL7er-RX+}>V3L)#B2 z*Y`x_9?|xr%4aH{rTj7Fk1N+Vuq}@N{#haTKfZzPXfw5=F4motcT&Ey@?Dg7R=%rp z`+qBT*Y+OD_f)R`hjVT(ZFf~}ZxrmN?R}JYS8ng)3U99}a{3$V+yUBeZ;U=r+XpE> zSotB!4^`e%c`xOMDd!t1DpPwI3p1_+Q4geTwq%2CE`>nzm0@ zeunZhm7k^jY~|-DKUevA%FkEcSNR3XbISEyh`IjS9srIf2@Qr1^|YR^{3GQbEB{3K zr^-K5{<-omlz*xGE9GA+|3-QE`jU#=ciOhsrv9MqAC>>4TwgetTcB-yv0Uy~ZHJ$! zD)38=aJ&6O`Jc)cDo<(J_##4X!ti$v;fo0jrx^@usJN|i{of#R?XnabF>$^sB>ubBc@(q-4sC*;k8!HcQjVp4SYI`%~n=9W!`IgGD_=(WvdWiJzP$2Q%2!an zqVkoLudI9(<*k)hE3Z+WQC_ROPWh_J>y`MRy*&L+9$UV|B?^WyGx71>9{wB zxuP)45nWpJ$zEl{jO8##$}p@pcbJjLCdbte#*>M|NgG4%UEL|zt2)@TI@rBB*tJ@- z%<&w_Zd5&EaL3b9xvJ$-sr+8mLkE1*vOA0Xp4B%F7}kLLpoaYJsE=ZOKtq04)JL=4 zuK|$F5R7sw!+Q7jL;J7Z9khE#dfc*GHACPDC`qwdR#H60;D~3cB*iw8>Vc&8uMYOD z4)!Tz#Iq3Dh8a~eqy3|dHbVF<2P+=QM9gn1rtqzW^4vs8jbQrpjtur0RMj5%&adeoFOvjO7 zLe6xYAdw#qXA(J^Wkt?A2L#L;5m`uVBl5El`5D#0Y1P3g)xk-H;CX+M?d(p+8By^0 z(-5Ui$0=d-G94#{(U+c%vn46syhu`PmX#E5PmmPvawI9XkyH*z^{o!hs}9a7WYiB` z$kv&TzEMW*betC^B-3$Dn2<9a{Uq}Ka3+znSytq{-$mrSZI;N{M&!c~`H<>hP<1e% z5IJv&i_hyJQRMkS2oZB3C-#6S^z3-8ExmxT58(~js(S7jtr|%BM!kK=dxv*JQF89F$ zQn+1GK!t7OaxHSXraHK)kVqc#;zX{A5^?9`s^;Z!o#b&pyh|QzmX*ho@PP0ik?>Jr z8+qJ-Jf>6!ld6LWg;btGSMeD>B}yef$(fT0&CBIR$>nLdmt5E^E0@>c0VzB$DWJkO za=96~OsfuVDkL%+^5R6MMTxj`a#Qp2xJB}K9o{7mHp|Lm9y}oYw*+*d9itx6VRH{S&%Ej_`g|jj=HLM|=Qc6R|C0kTBbH+xe>-r?a01Q(U-rk8k*sK z+r5I(XOId;Y?g)5kMIEZUxCT~&NeW56c{~R9n2^I^i!z!bI2Be6$A8enA_0QsD|ug z4nV&^Gds%z=&=YOcbTXUxuVU8!RJ@{dMqBF-_Vzz72z{e@cA85!H3PV@Tp1*J}EH4 zhi%~V0`PgRI(Vi!c&Y%=5~1pnAzKQp7^3Hp67NR1hF*3cY6;EkOV!1@+shF|c{P+Z z^h}7eVDwZBM*Pog;5~K?ErY)NOA$sd3P#I9Dj2a@7DoK9L9mAS|9=TaYy+dWfYBS( z!R!J+b)nv>A*%-~2I!42H(5jPIsi35Gy9GQ(7O>p?ix}bg3s(2eE5>(?7Q*!tcJe) zI}tu_3qGquD)_Kj7C!thtAP*yNGJHP4SYTUJ|9&FA65r*3lQ;t-+}5zA=?aP=vn<5=zylod|Njug*al)%HJyURYwX(<{;3^G zM}_QYuwu9tuVIqdvytgi4qV4TGrOb**HRH&?s8He$p1k~myFO_LeS!W zDJp2OSr%Gn!2^Ie8BEY(8)&Tvv|7~!%M}1SJJjR<#R>Iu!HNNE1;A{5t>OT79yGHn z*A!pmR*3-1tD&r~-00$dk`N+UvcF<3EN8E1VpIB<=GX13mgt098RU0>=WIa;IWydfT~(df(9M`*1o zXpMnX&|JX4k1H zz5uQp0hU)oSzm3NyT14zmS)$DM~qJd<=2T2TU!vj9#TP!&9V^VfA#>xrh*A#Yy+_k zfmr(jT(^fxcZBRtuwuB{JL_u`2QI#|J-e|7*Cr8M?)p+6$=BE2biPSETKAwYzj1`t zMuOJ8kP2FCmW9?U@Bp-)1{1W{23mUnt=(#Z&Nac#HNj2=*!bUVWp}J`zEs~W%01s% z*BHN4-&q0Vm+CvAZeOZj(bSjfdrDHTV-QJ-&9ai32M!GDk5;^{af3O;`jqU0ro)6pZ0UcSZMKa5_!#a(ndHp1UHTHvoF zg}-$4lGJ{}P?8#(Wu;cJn56c*rN%Z=I|`}wsR?@51cw#!`WL#8vok4uqP*Nm=^dse zlX6&?mNO|wOXU175hZdq%Zhx3F!H4&U`z_zi2P(keqv2qkg}&&$U}}-?a!-+5_+NEME^L;SO9MP0g=$Fw6}FMfnaJhzn&8wzB5fcq zPUQ3`5qAnsZC)N{Ngk`gyX3)US$V7n4+uXi;iJMf^2i~NzBR#lHNiQBRQSIx7O$qh zQ7ZZKoH;qCdAanHT-w9Ei+kJd(+vN`0H&q^yNoK*V|Eo(LRt0 zMr@Xa5&y$oK(jxXTyNP1Mppr&u{FWv1%P^ndc8t+7+5htW5e9!1J*bPApTdE*=sz2 z#zg?R%S3(1?s<6(KE3H{Ts%HUpf7(-gwNH2PajAHA2!Rv=M;DVKF5FwK5PS@8-dUD zHNoVXU}6Cx{vT6NJuPIXgB3$`JyNodRMQ-Y&VXiiYEAK(G%bQCuZFUQCWkl+MiXN& z;(rs9ofePLS?J48jWD`NFghDj!HCVWFd7UGNc;jY!H8{ObSE&ny(YM|0ML+7Z)nJd zffWOEdzhQ7p?e&FE`(2d zvn+hBf(PJp37Fu+Ht=~E_{^vY9w^{*b*Ohu$i{&c<1+*K*aDjA;BzfBvyXb`*vtr@ zyc)^^dLRUu05yG`x9@zeqxYHdh>b^I{?Q1rM+C76kP2dKmW9|fcmQHkzyvY2f!LEk z?1=(g(?g}3Lv{;TFhu3Mp*ecFTTnFua-IjN82Xx&EV&%~p3JNoiZM`%4I zXx#y+pv7icXw85Jpmh(Jpv5-OdKGBBTob%l0F3{UGxQz~*&|@ZfW7Rjuh$*G9))Ih zws-!$9s!nDLs?%hHg|o^r1#h35u1g+{Oky^*95W0AQi;eEDNz0;Q>fI4JL@O4aD9B zVs97VdMQ+TIb^SZ6~pzmv%WrX;CdCB+4nuTK8WCQ*O&T8zP?_g^AFe?7J-!8)@Cn~iX%Y`c0Vf$1n{EKTg!>L~f%7O};WudYaJirnEUsFMaZJ@F-P}wjO zw9f?VWrB4x!P=Q%%>po6LnpgwCcAVd{4ALzFdI6+w0D46&jDuL2$;2_>Y7brB%hfJ z=ybr)`Aru=CzM3!Y$E7%gtDN+W?AU$1rI={6PTdGHqhw^bhgU`+hl^RGQk#^V6y@= zU7-N*LR{7&F55-8xTnlEAuL=p`K>}MxM=cQIQ7j!V7P+xDZ}k0ue~vdTe>hzoffBzYVQzmf-=W#usd9uWT75%-CUuS{ga0i`VN=jF&%Vk@Xr%qV;;T;4uu!f(M&r z;c*2#0EUafWWBNtJWd53Cuf2aGr{qh;Mf8fW6=w&oOwMtLc(3FCx$@CydLi?&|^a+ zoQXY665;}%EGv;u-~sW!C-I}g zHWHbRM5bnf8#BT6nP74zm{`c=Qz&F_$z=a@Z)c`P>Ev%jthV)CALb)l-{ffPn;52( zXzTkDL-ic-#v-?#={vW`f%@!L0=_ z{zNaZa!#_lBP87Qd1nZOY<;&o6MJijgtPVCCy6YCV@ZU~vJz?iFG*w>FiC`MB=Q&% znVAV5$pjB&f(J9f{e@hrp^$wdldaKorrfV_kT_#I6n|c(4sTUH~4?WrAli!Bd&w-vuxN^a3kq zVxNnUa3}Ve5D1yrr<{rXcZh^Du`fy@>%p-k!e&{CYy}TUWFv_m6}FMc8%Sh!CU`Xy zyj;j)YjkDb@@`XRM~UQLMU*zBFNc|MO63y+??5!uM&^@Oi*)$csOZibL+0OFWL85- zG^=k47#*Q3V6a&h7<<42Fz5s(v&uHW_yAzMmkHh}Ah9RpfGC{L^?C34UIc?XpYKHT zsW;1WB-Ac&Afd8ZR;UNT147+LB1DC4g!(B${WufM&jj-d(H@Mh?C0L8_;D0)e!eqr z^Zt@~>xCinpD!|Rp(L8O&jgIape$gpSr!;4zymNi5=`ceZGiDD!1y{7d|5!^M92Y= zGjCrP z#=fHLPiKE*0M4QhTn|8B{`XAbv9#X=qk)hLMr@Xa(HM9@#>2p5I@tzBOVoA>Dr0$A6FdN+jZMzCVAT7`Ma-w9T6z`6;V*_CUH*VHNzSnkQAJ_M`fV(^(t zU#rC9GYx(Dl_Pvs5`3mZD)_Kj7Cw1+06w>a2|jECpVfd*Lv65XZBSc)=>Aakfsj22 zRt!;t15sNCq8ZT4uHmhxw($_D4}oY^XF1iz!1WOQwvC7DVf5wKh~QdX;Ccj7fs4(u z;Cc@p0M~0^0vFqWYgfRvOKs4pHrTN?*uH?+`=Ry+A)5nMjMy&7iuVOP1NU$cn+whC z?zP3Yyn955<<(Hmz)m6T0@;oZWZTC;Hjj??h==S$^yPPtAlpqKn-8f##%5WNeGd~k=IjBP-+A0X>q8+5A;x)$*IAyoY_WIurwA@Lzd|Z-u~`;e%P%f)Re=dyYy++%0oM_=!Qr(* zuiD_y0%EN~?G-|{B3LnEM<6R(VaGU#tpv^N(Y3|*-p53U<<(GD*x@1U0$DEyvO{Aa zTbYiJiHB?z^yQC^AUjGRYYnMD#%5WNwS@<)usSe-jBP-68X!BRHaMv^IH7=7HdJjF zvNgeq@j4|;RaV%U4qj_PGkb=I*O?Js?g~>M0@q0nTqnf9wKn~p84uSw=*yoG!F9U8 zwJxLr7n^0lwIw_Nt_{EhF17*JK)}_%HptZmeQSgB3W#kLYHuB~ZNQ2V>yNB#g$;2K z+ZLMH!QQSvBtk5&hO)wPA?yNKUk9@DVj$a&j)%lU)&YI_!4YJG1hS5h3S?}S1=*hP z0LVIl31n;oveAHSWNk2_HW*&Ot4pZ5SID}872`EBOjTCcr4C+uLo<7chu5VMUhWE0 z9|G412d?2UaCM{KOXK0%2YvZVBDlr~T-_lRxY#TUuEXI0aP9xVs+Tg|lUgw0W z=Z5S&uwuNX0|NYAXJ~3bL-sZYufEXC-s<6XTZEUp!qkVrHMO?zx1k%MZGRiG4?;P* zy)7QCe(1~J8liQIpw%BzL5t0@&>9U7Kx+t?pv5-OdKe3AMs4swZIG`G?yU{(E?_n$ zG`J*Wmx2{zHp5wCGabw>gJ$;8+TuSF&Wte2tD&s12b?vQch=awPW|qf^>#T2nHi7Z z73j-98X@?IAUGCML6FU|5WF59fZ#YVL6B`A_&gANwl;XWHh8i&c%lH`4WagpA-f5z z7`|u2%wY@lAKTjAb#QwOn%Q@1 zi@!>HH^MEihO+Ethu{;q-R-1&oDSZN2jvO$<==@wd0RmFH>3gzn`MFWGCTm3XTby% zwgJjKfHJ3m$Sa}Jt08+0tQe6w&Pw{oL1Z>Gv-3SfK8g@=SCaZD0_1hte-sbM8|cf= zj{x~l0C^Kq0ff!60GSUD0OUO|0fcP;@-+bYvNrg4YF$bwMmmyrDmR*c9`&MNuMLF6}RW`Fe%`7J`kT_x(HXqEg<``_XL`2&6V zUn4+%5kUTgQ~+VKEI1uN7A%hv_V)&)z~*_V2~(VJ~q7k+`c z3BSNxp)UGnZuz=!KjAY@%c8E&IE8<2##KDObR@)k%4RhFZm*T=I7@heZkQdLWo367 zJiyU$k`yXzBfC|RU2R=ZQx~)@q;@*Gkan2b=1i?NO3j_Q8i?(|mDW*R|Bz5Gk)Hu) zGB0eF75PATK)~lpz^Jf|$k#&T?dpQIb;0U&L7PJGgV0+%FYTh>^KG4ZSv{J9XkOYx z!kBrXUeWK7)|MQHVob@A&9ZX50v?dsNJ$M9wvpq8$gzE0uwGrTZXv<3=tA<&?6i*( zbZ2M1FcmJo{JK$HXJ;dc{7N{J$k{9_@;l%G0pBPAqrx^K-wu&)Qx|Mi7i>`%Y*rU+ zQi%UfC=^f7Hc|Zftq>?L#5{4fh~^@{S)F{P%~NNSNE|ao@*q+8uwMsB@g9sPDY98s zijTtsGJ8NWLxpXmxEoUJTo>$I7wl9Q>`)hUETs4Z6pB;q?4-D}lj2TMF8Ljz6gx)Z zm=qUTg}Y0lPhnI^l+CgdoedAj?|I1&6}FLRHzeA%F6dGh>`_SZ^-%SVki7|3d|~K{ zga`4n&!C3vzID;xG~R+{wtHRi_Oh>ojvC6PvP%eqtl&MOdg12kZ93bx4vT)#KmELe zzI^w(!rw9W5sco2R4`(*EQ~&d2S76yOs*1a1EWKL(Lr@Vj{-oSg?gWd>^N~+`=QseZ49)D>9zf?r0J&>OeaIR*H3pwm=Iw(19if@M+{5dN2rqY4sSjCIqa3&{j)AKa{az6d*Usq6Umn4AnZUIRqyiV4 zWx=&CJOHjezyvO~0oP=}HL)%jUl&|k7hF?7Y`;)@|BxL3R*cw0WMwPt1_!Yo(9B+6 zhdTvlh20P#mRCbrVdEoc^4B_$T@%R*E9^izz9Am6gV2}1K7wqDKz1;s0vVfSL3Rv0 z0J6it1TwY(+3kSr*1F*4x?oxXuVX{i<3e^kSTSC=hAGJkyUW4r1ZZaO^zgbX!pmJ@ z>O)r8%?@1CV&FQFe(#Eh>m>B$?~LHOL*P0YQh|%j=EAiXUl2VIuNDB~%XI`UwgK0c z^__yv>w`_}gN^Hh4eRaGBws+2&D4j>qysmi&FiC2lbhCu>x(zV8>9XxZ;)p+J2ImV zQAX}WZW|`Vtnyoj2|2G#*g+z{6wV}aHp_~90z4q#!mDf8M&x@S^4;o#&h^30^}$Ys z;Q7j$Y}TEQ-J;<0oe`ydM%g)xUZ!KGF#4eb`jvQJ_nwjz-*zKOu~}A9`r??IBo}1I zHj?U&q`K7yUF(A`g^ccCMtiu^(JjizosOVqEj!TyEdXQ4N{fjb?CM8W3|LX=>Y?hVBFYtiyzm@P&VHuspN+{b26-Xxr~xr zYT#aSVY94U+QI`;SXEL$g>B?=8FIO#J{Vm{Bnx?QB9}yoxN|bPd3jted9;If$%D~HTA(&^}*OeDjSEYn}m$7xGBCby(XL$c?@tuee|W(X3)%z zuP@#$CPXOY)ljy*t0EZkV^Q~C^s+gfO{fQQi+*Xf1^V*i>kD66T_+fA38`SjW?2~R z1P_3Q@9dHDk8NOd6EM1=KA2Jfs8gu7bI5i9D+cI>Ft?$pM;o%!9e_GRGds-#XnF*Y zyG+!FT+yb);Ik`zO^?TCH}vJFMfgk=e0GOa@L{tod=7yJ;Il87;KMfXc@X&AUmx68 zAKX)bi0{aOs`E;mVuasVFx0ocu!(Ml%GXBOn!w*enYpeHqTNa3mP%%W(b;j2^EKW)%QB6$${T(Kq2d9_A)% z=xGO_Ghml}$^+=>2q1S2sSm+tRt!G!BAln=@sStdJQd;dq~KF{5e}PW;iE6ODZB`W zZLFc!fX^%S!AteQ3k8Urm*4;?zTu{L4ZVVtYz@8PKs1~XyRWZ#I#h_AiLzaC*UTQIs9QdvW6mW9!k@PLfRfXNzS8yI~6jNYpc-YEd2 zFU@h@iBk;Fdtq*}hUPf{@wGYGxgJ3CB7odAq&@_ncVh6lmcHi2 zavlnG`3juk<@CL?oEA86@hv&opFOx1L~yywNqrx<2@(0U#ou)h8cChLoBpw*(GQ?Rf;_@e;W3!$FADTnXEDF$qzv%V_$Wt9F;8ZSdL zyI4ca%YOrtb=7vi1LiQn8FArI$t^-t&h={ZyBMrl%Vwqq=FWkWuf&WJOHh)zyvL}f!4}EYsH43RROS{LcO0u zwg9XcuoVHA?O)XnV81{!+q$9n0$3dZmRCbrU#&valOy&ky;sL0_8a>0ts}%%5yXCn zR1jmcEW{Sa58r`UN`7{a3fn-e9*ETy;HnIjszSB|STS66&iY!-fon-5EXkt?1}|@i;DfV_uhN=wfFY=o%1BQli5AtW{0`||i|SPN7uA>gWY!=!)te3ir`RmYsR7gjIi=nu#Wp#$2{|>i(i&1} z4OSivWRI#nkK9G|yhp)k4sjjgXgY&khXTunn}T_@&z#Mom=AZE4*_9vfo)>GH8CGi zX>D0)4X?B|SLC;#+QM**$dh-rB$hnnIUK`X_U@v(%O0z^4a3pkQJ8Ju+6X!ng2HA| zu8pG}$RmDd6f%u%a%~K`HmcIvuF|Sie(g+E3*#XSQ zQ)gh#W>L)fwNu1=cMzrm+r)eqVm`jo8dquUq?q%Yqzcn%e4e>8jwn(@FqiI>r{3^d zu;B}$cZDwpQupwM&7yocih3Xy4uK0)V4Hl|lYH5|(%MZqax~$Ej_jUyBp8C-8t2De z@Z%Wj9e%J`lpiyw2ckcPHpnKn$&Z7`j{_>L{VJ_}lq)l-sxX@l$h+d~7l_F|jq~MT z_%e&Shc9dv<;z*r1Nkx!E>MAO^5t;y<qzCwm2T6k+|AXrDLnrk>qZ6ZhEoIQ-$m3i zdqQPlW=_qk;CMS?h#j4m!8wx3_16ur;m)SY=UaZ+mUBY>d^-giT}LQ1VzVfX?w}q> z8ubb;wn?K|q|uB@Yq}EXPPg4%?uK8*RVdI5*Ed`M&j|>`FW1V_Z>|eYX>;-d1=Gaq z1GDFJL7#iLuQ{?l_fnm6a$cX=&}Rvu(1*>U^m&4MAblRB4aPOwq|e!;&zY6h{7UOI zCDD^^)2H0c)3hm+=uC3SzvMkHAkj0_GJ9@i;Yd0!FOlQzh#Z>l>I{ue6Ex!YcV*9$ zHF}QfoOAOUodb=YClng7S(HZaP!FWhtF(beY?DTpkVXqDtp!RTekB*Rd(YjxPn$x4 z7P`J6hb|8Y^Z~WZURF<_%ku&SbI9uh`YaIi`H=gfH;77im>*G{b6H-WOQFxlghC%S zi_+(N>Vf?Jk~YwXZPMp@(&ySrYmw6D2e;ji?uK93RjALkEYd{YrJt4SB^DL$Tiog<@_x{^SflVT2Y;I zXI`y4pjK-_p%$A(skI{YK>5|4Hc*RgQtLrd>;6h>i4trjx82I_rYmg<1-n0xUylR? z;}@-EAFen49?1*lcsnA$mNYiMx^wT3$cn8(b zzv9h#IvV! z_ZD&l>#=HHk6=c0cjaJBoUX1MtckOds|SnX{k~@nI5LAeh9hhi<;X(nfgCxTHgJS( za%3%XB%8L@Ok0_>RjC}gm};|Y*NbhofiJkrUo#NeOg^-g+R)a22jAs%P-pE1p>>gb zXme2H3Tg~R*eptsTc`(8gkLxXMc5`q)+a^!rL8_`Yu&WfTPboY)fR@fUtSKU4>{}K zW3TJ#!LfCJkA}$hcI5~}b_4iv8}$o6*euGA2dM}0!+p^d71$;}Z1Q7J+8UU)Hd0PJ zL{)`O49YtZ%+G0SewQ1TK zraXCx8f3RlXTJ(gK3nFUafTCDzKr6@XLHvZtV3;@&(LA6J0X)#;hU^qqvJVSH^@yF z$>-)s=B61^t|t9O0Kc!4bB}kv+(fiD_%sv^61Z z?VPs8DqosWgX~`EY)j7_oK+^~-Enp$u6|%Axc(rpJLdyC)^#URU|Z4goV^+Z)5sK7RRiE$G3KtY~D8;HR+iLr>pxGHU3p_G_GI7#Hjb~NYg zRe2eLIeSGuw%%3kHK00^IsjERi=yhihG>pYm2IMWGf}-UZ7oh)*D1FAs-oA^1xA{p+Z4MN8@>G1;T@m$(^CT%^Hww_R8JWjQwRp7GVxx5m=06vos zpz~B{PYc|f4=sAcxEdIEi(7but^ULUxe_(0I-2kz^0S)U)N&iO2_ z&!^DmCqkhQn?>o$R=N^RWMZQV^f+7znvH+ki! zQF$hxM(wF(wk%V4-&CIAM8JBKNQ6Gh#}0q&lZ8qf#oB z;RvrlC?sRED9L(I57bdt+CVb4NwRjC8mmplYL&5CWc+2jO1Ej+-DGG}s8^c|d+9#p z)-j-06}8NEsHa!Qyk5bq^7?>Wtuk2c!y-rv>YHX@%sc)FT$B6lD9hE8>YNUFx!Oan zETNE#&7$P8sRxp4ecC`Swn?tlNUl{fR=13`a>iOwDK^Ayy|KF)N}EE(Rw1wa4C@h4 zY#6o7u8}Fcf$Nc1%<*nbvA%Ya^UsbzMH46S;*mk#6j(qYShUfzz-Xp?|OLj{da z;m)>{HJV3t&K7x%hC`!M357;%7NyaJ)B`zwCT*Y*+oaJb(rCMkRhzN4RvImEn_lE@ z7Sg6rqwNA3?GVuDVrrQklcBFT0vhcQ(8${n8r23g+FH=)67FmVS))s-&KZ-}Xf!ms zj8JIAW>FeB)B|aB6K$Xo+oaJUq|w0{>%fe)f5zHZ$#l2dnqLY=JKam0LYWRGul%8R zctEBl)G~WmrtmWS@PJI-ju?6ex>`fB{R5KiD@b-9cYL@k+5J@K9F~{tP)POwp^%Kt zq9l8UdLZxJ7ot&tZIWyXNp@VuIwoTsrSy8%ZTg(Md7d_fdL8GwilJ8*(CYit6~)MK+K^+Mh|b}gy5C}Ulvbkn_eY!Uh6 zr`_U!Zg}t5^_jx8y~TOm9B)UY-BqsmES!3;5neX7SQZ5@8@oO)%5@M$y=;ulqC}~p zSN%{*txg-H6x)2M@`j45B*c!MrFBK$O9R zLKHTO5`|w-JsGv#k~W2kJQ~Q7rvi#>MJ=;WW@yFL zy>yzumzPfk6!CT}NR1J^(^IkvBdN}LGOxlDP=Vie1{K&WN`-x?2l8xJ+CT-iNrjI| zg%2~<`x)!qjPStnU>0 z*;HE?mtXSaou7y$PwpI-AMzo{$K|^`D8!|~FLHi|k8|mm@R7};d|W_1kZWhbH7c-8 zK9*I{Z&x$c-x=#q<={nBMa~DJ^H1KvV08Y@N5uIvU-qI?Ud0DoNS%Q>n?*6doqC{- z7K1Pq*e2#}h+WhDcQa% zzbNVLh&i%`1CD7w;yC>Yule8%msEg|lF6p`j1bT{EX1mrCs9Rp3U{-j2 zK%Y*6K2LLB-DG{9p*p8)UZ0hr&$EO=A2y59=S}K?^m&ms(1&f(r;7ARS6Mx(tkso7 zZ@Eq1b~o?Prck0Zx#VBHWdjnuOD(fKs|p8BHZPIm?T8%ek=MmpJzrKi^d5JXl{I>w z>YSc=jn;%l9}o(S*ept;Z>R^-=rh_tBeqGSbxEV%Ro2={pl{uF-?^LbX;UarZ`U8> zP~U(+KT^wVpDLPi+?i!>p7;9(1oC!7;;b!*@-uhPR~F?Ls&o3}MOhD`{7NW9VY4Vv zTDOKMDcV33wn-G5L>W|N4Xm;@su_iC#X3<5=@zJ)HMO>TeoRN7EM?l1N2!)7j7A4|9>VZV; zLmP<5HirbgXt;4{|qyX;Y}9akaIIaAt#$f$+<1{Kyq$D z8_3Bv$+-{7xmT67N0l{EX}O)-bbEI*iZ+E>?&bN*Ik|s8%Q4h4yI(ym_s?q?%t^lw z&dELUQci5Flw}qdI55yp;Pw%AE;?lx#Lu%7=EWEgM%`Hijh}NAmr)6J0j% zWc{?0^}|lyh1qV-PdoWP9r&kez#luM0zlnAsZ=V>U~Sn%?qql8hn*Hp|Gd&`(|h)b zT~ht&qrBN#sZ^gUGM`oUrim=&{DMB)x_2?Z^X_|$uE?REy*N6lK+WE8j~f-^Ufuab zkuv2x+8|TdCRhI^SO4^#th<0f=TGJ6u&M$7kfV8ET$%yu=0d-l1%-ROU*R(TA6i{R zmE@1R%ffuiV4I7%P5J1u9Pd(;XO~eAMCnr6z%#bVv+}VuR%)z&U41!$PHLKD9M?DawYiR?| z*e1_fl4s48XV(+xG*_Mts|pz7(yIlmiNUI4)2prOvTX&A7E?E1%Vtq*Z=xQE?TsKw z1-6N8TVmT0?E z-9aD?1NVyV0KTGY4|-!bSG*g+6+q}tY6(JY7Dec8>VbGT;6VkpiBK0J)JYM#hd|2S z0HIC|2(1W0_fks`VzVehFHjG}<9YC)0^3BWD-l{r5qgopZ1=IwN@EvI|GKg_Uwx$d z@rjqO#9pFGr#sc0Oe;4u&GlL|{hP`@v!~DHhTm1DhT*fi8wkHljX{{rq6oi7J;|T zzgWcY`6j*I5x?Xk^0dMPiqh~W>VY);mNw9kZPIWZ(l9sH>NVEtsWkkVs+^pwp#_J3 z@%Q?b3Z%QM;Z$-1CoJMi56|_=E9mshm%Y){8y)>d`;&5RuYd4y+?L!8onhCd={XO0 zXIKJ>_@6$7znDUylrC3MO0T=nld((MI~lti|8_aLhvk#J=4h>Y&7A&IyFTOrdr`LL zfb~E)Rpu#OMuqGoFYl&t=smu;qW4szJ$=!rSfE)s?N6Gyy*48waFO6LZq6+@JJ@V& zcJv!tTV~ak_2R6sC?lp*Mw~d-nmX2+GS)iIPl|P&6UXvBTYvsY^%yXheO!IEUNocZ!^X^$5AFt=Vt<^w@X#7vI?%8of%`v&4H(k!d&*W<~F_ENSgWv5Z~Ej3y!FK znhl>$TLzz+=VXx--n{o`dB!SMS zOg(q3b@o{6%(2#dKU24I&MnB)OW2zcybn^#ySl!B(XGi@RM%2(7mju2OPP8h)V?%C zZC$3)aVS%1Z_dUQJ!2z)aD&TJON`A3(tIz6*ZoHruQ8;rC1E6#k{&h{gQ^oPJx zb@PcLs1vPI)6NFt_z&ZNqSK$smvQ;~b|dL>j9OO@09QV{gDabj<=Th!J)9y=n@O~R zzHAfMHsk4=jqz5C@xH!C5bm@XuYS(t>Dzp~tM6H?Z>#aXzHUPzOfRR%>)UobA8Io7 z1kP+~IO7&1)nR<+iXGaeI@XpyNcZ{a+OkTfnkJgFh~^BRW5$^=e&!~V2hADJ)m6E< z0Sk&nF1BL+^Sy$Zeo3v{(^ z?i{b;*20SQa_4##w-r|O$(`p_@SRtntG>DOy$Zhj3RLvVUEo#l%~qhIf9^uB;;zDq z^>Yin3cjlf?6E=aBCmq)vH}$w<`#Mte5Vzt*eG|gSHU+{fr)<|70m;3Y?`~y1zQBb%|=&LpUeX!lbthuFpU>7cs?q# zyFezNdw zu}ujwvbJoq93nQ{o%sU6+yXN!&v!-4uzS$@Cr_b!&4%)La|%LUj$xmO5#wE#Of_ZnfZ7hsceZxHro0d`34 zEyCU|zz)s5L)g0o*kQT%2z$Q(J3RLRVILM?N8~;t?BfD#a_$qtJ}tnGq|x{=3%O_Z z5gLudj$oDfM#d&x-C;>$a-rNN1-VdRlWbgQW|LN2Xl|20TxemFDqLu3lN4NNWt0D0 zXl;|zTxesHr(9@jlY3lfXOmA{Xm67vT0*SgNqW+T zDZnNglP1(y2Tky=eR@%?bI^pD!_N0I|F8*YycXfPBPOJ>lP7p-e#ivwB**xXgdbIi zug&<;gdbCgufzDUgdbOk_h$Tf!lxAC7UL%nKD7{Em+?BnPb|dOV|*In(+lxFjGsjK zj6%FG<1-1LRfzXvd^X`H7vlXHpF{ZELVSJ3Pnl3SJGc^UKvk6Che9vbH+$Fw&T?)| zo0LtmBH}jb$c1v7gyTYmO-ga0nN8Agp}9?3aG`}w&U2xqP2O^$l}+w(p|wr^aG{M& z4sfBZO^hjn>zGQ;C9)y2;EBAN@~j6T4>@1ZwFi9$r>lp}ZgW zK-K&$6Z+ZH>w*%HX5i{ex$nK;0~d?&Vc*)aeVE+7}0=v+CGuJQTa zin&ayA}aek*D&VRtmzuK`O07TFJe{)fE5>uVO4i7iA~Wuhc*~|Y!k!liQ%y zs(Xjd?mY(Fg2V7vWH`*l+{dCScggEEzBzK~@ckUtp6V{47POk+?uUEMik!<;eeJYZ zuT}jUq?+Ao%X*GtVY*&ZmZI+f=+n!;tiuLJk62f>=}r8-OXO~ZlSsV~AlJ}@NILA= zIP7XT>?--guH&#lhYcKXb@zb1aX{B7;(&c{z$zRtO`lc|`tY3X>oCG;>1{b9|6$LE zI^2w$uV~Y@2LmbhlZ$0Y*=e2oq^j4XMx;qUP;`wVDB7Udi~6dudeW!IZivGMaqzb| zc)4%2b!n{@&TcK2-Ns<&8bz?%4D8kcyIh{#<_;UIowsG}%F2DKEe3awrLgPmva10* z*C>J=E%Q+tuLpKkp54eS%ejPuRM(;t4J@wn#$s88Z?zjk(8ys3Wglulq1+mDT%!m& zv=B#h`cq#uR$uz`Lb-jG^>gX8W;$F)dO@=a-=g1@Ppk6itWOPy&M44vjUwpm2s#^4 zU$m%1pB|l^95y(!>TQu>6>V2pO4tUt#KwY{YZO6jR}dQnVgvKUcB2zYZP|VfLqu=j zrhG6aRq5Wf3}!nAlujvGn@ps?cRD)POD*&q=hCMdsPgPa6GW9(ohbo8LlR020 zH{n_NpzJ18^eOoDZM;Jq>~Jmbu$jNZq%70*aj)GWqnlT6&Mk7P-J#&?ci5dd)RrAK zx_J)mYRe8E-K-i!bKt`3t&<&gky-}ar^{(*4=r?ONofi`9@=j~9oJYj^ywwVlq`p1 z2^}m|*OqgX>&WWh4id(zwqC z6nQBXvbEFzrz)3SduGQw(Qv_#@ifOn9S%1pvIDlGt=k8$`ewJ`KI(bsHHCwIA2`W2 ztKOdX&gJ{y%ed^e+y|e#G(30#P&^=aK-_RZq;$zX|ip$~Czfnwsot8z$&G1Mph!3+BI7hCXjJ~V#v5p zNzicGgZiZRCeo)*hL@4(Ab4V7Z^CiHakvEsvfMA>Y`tj!)_XVy-{@=8(-^kzc?#i9xDU66>im1gy4Lmk2=2xD z@NTRR|7+{rY1Xx&y;MVP!MgE3Xg9#q?r>to+O?w%v~z)CwChA&K)a)<&l>AU`t-Hy zOjRsXkNT$`ZbW&434tCtcWy*#VRH8v zP4O6Y_ZhiBF^tym8P$Q&2?0j@buw#ISzjY=a(jpSqMiH(E&LX|I+*23hxexzeg!WN(pnr2 znZu!I@bKE8-AA`t-f$B{(|BKzCD3o9sDM z?LSm^c{_(&2iOm)-{iq|eP+)XHjMsHRi8m^xx2x%0cRH|hVxMB0-VpMKIvH%`t&&u za}TnayV;yJ*@aZ?a-K;`dk(jzeD_Z(HT9c3K#!blK6DuUpQ^rq+A`tKPz>k2s0(numHMQY4$!A{BYpV951@L70UnoJOWSssWE!9y z%G8EH`6N>%fNAPuTlP}N6D)s?FHD5_SZiEdfBtJ_`V2kUk;Z4g!$C`PyG z)CI!2g!-(p?x9c1p$}iYlb8Ynba;nrX^SftT8Hw?=6<1>%kDmE#q4JI>|CH2c5{4o z4^y8t)`RqE-A^ArySY@KW#;Y^I^Fozni~;GKC?O8)+>+njS83LBUHsKPw`p0Krt-m z`z#-$KI!kw)2C1H461S%pnDUH;f!y!@(b=)2=q{T_2V9;Gkr=fPzJVzR%AEis5&W&+ldGv&MRn zKCS2J!{@h<`7uDz!&QvKOG1}takwK=mK{uG27Evk z9fWqfkqQ9aOY1keg5aBIL*I#^9ho|l%;@ce(psQ*z@ecfrr0ZuR!?pQt^aM9O)y?kor4ap0hoHZzPM=;jaEvNZHUEX=FoS zE|%L+l#3NMB;;Z<8=7&kxebxH*usV?Tx@AW1}?U;;Wrms+i;YNZESeP#kMwF;bJ=* z-09o$VL6ZKCdf)RCyL0*n%c6>Inin;E4z{+^i3swdRaN#VS~m3AG-xsR$8_lvHnVXIl6;$-*JCXt zcYQ5F@=>*A+p~V7Nb)M8Mz5WqPfzmE4jZ228`Do{c-dl2f@lZ#32xUY;l#HIH~19WIyi1Ff84zsHt4v6)}<}WvUhGh zDp6sdTpuoQ?$I-oh*v?BEUei-*Wa&cRakRCZhgO|bz#kc zxefdpzPjK%_81(L+t9D!pE(6;4$f`l*R(6FnM65haUDGvl4Wl>C*do*n6j0(Wwvs! z+*bZn*vf%swqo4eRuo&gs5{xVCI6 z(?gjk)=O zzwB1QMg`U0_kOdv)ktc^S=R$si|#i9YjEJ0h^J7C)(&?@RtIjnaa;N>pMFJ0EAs9& z)Ew?;YppU($$up`+AY|q zAg}rBWQPw&Lh$aDJqAo9E9G#%9+s+fF`~;)bs;O+zq)Qfz^~*lsk7rf0%d*=YEbc)*4YVE?H}FY zww{w^6>3oNk6IjVM^%MQdJNcuVCKQUZ)w28ue{l-EDNYa`|uB0kTsC4v5!XZZBQM5 zk4+o?_8a-mHf7D;#Hz;HlRo`~;UAk&!zJ$Ke%fRYq-uxTcpkUJxrL_5X`S&C`Ukkt zLG>Cn^G-m1qX)Us!Sx!^cUxW`k8||_RP8Tk{)`{9x|0a;;onizt9O_e?T#nwkU6cr zXHVQO)C+ram>^oy)WofuxzCwZA{hLE$KSZHhU$lZqf!5;OY6sdmX4QgxS#H-AO2!q z*G~obbXEKCuR!YW!}7hkqZMvS?kKy-j&4RbQos% z9vv9Ix`HGvVI#8C zXv+;Ci~Hl>c_H82LB4?p^T5ju^o)DuHaseG)m|HZuEb#mv!`E`QAeihgexX;^yvqR2Q^>0{NtXQH}>3656`$j zBPnc6z0{U7mz9>UaT`%Hjt(qM}2z2u< zr&i1Epb(mOsm9{o=>=2aI=-j6xJEhdt%~DlkLi zaxmvLuX5O5BId?ml-tRgNCDSqr2ZqR2a5h7J&^>HXoDnRn_{sW)z(<2YDS#S$YR$QU@n+2M2o{OkH{h&7=-|Iss1lNX2Tr9KU zFBi*gFy~^04Gugxafdm-yA!#0o}668ii`UreL2n)>B+>a#yXrntwZ@^5`7@t4r4?Z zqnC4%E~$?rh<->#pS-+Y_YeJZZ>x^yid$ zTfdR_^w5#qFPufGvDcd3F#M12?8($!jWvrttr`3=oj*?GkE#4Ig+5&0*(5rH=FxT( zz2Ss5soZJ&iSw>2_zT2Gnh`$^>d*`WS{te5%css*(bnR9dUS|Cw?DYK}Q>4jUax$OdPNr zj0<=Vtxpky@wW+|E|h%&tR)_2Fc!$f0n5R-sFcB&Zz32AWuE{iIv5wr!~x5}xTKW9 z_{l^tE|q-(oakU&CKCrN2jlWm2IDIe!MH;932>r=aivTgupEr5N*Rm~O$6g=*(bn> z4#pyxIAA##*OW3CQ%wZpTG=PSi4MkfGI79iFs?6UFy1f`jK#7~fD;{z8)V{uJhW1Xvr4h}YysZjf%4i38RWk5lnmWa5Ce#8-%ROM1JBaeJ#w9I%}JxA7iY zpW+P0?XpjRwZtQ)zmZ$gJ7nU3wZ!98{7#uTU@h@D)Bi4+IAA&b9o|FhQ=GxLTlNXC zmUzVUH?jzDk4zk}mUx_s-zyUbtR)_2`Y(}*1D4bOKHfv?Q=GxLU-k*GmUzVUH?r*V zfJ_{)mUx_sKPVFitR)_2`adKS2P~)m!@P&qr#OT0i0l(!E%AuyZ)BnCKQeK^THHnBa9I%}JkMkZ{pW+P06S7Z$wZtQ)zmcWICuQP*wZ!98{3)3@U@h@D z)BkCiIAA&bpW!{UKE)Y~XJwxNYl%lpez&&k9AYl+9H`13Mxz*^#QrvD2valmr= zzsP%NeTp*}FUdXu))J4H{zjJ1UzUjj))J3X@mFNxfVITqO#fG9;(+D!e~tIh`V=vX zj7*}h%RT`HaXbL!KJPS_+6vD};e}S*tWASOY3%I&WFbri`s-!xQ&ww;dsldSzdOc# zxAahc0+5OD^HcNyvs3t---xioAmN!#oSFZIEH+>{f!^djv_3^lAR`x{Z^=FZZb~42 zepL6=s-Ml2(e<*q!BeYm%VGnT6X=~%CXkUC=v~<-z!4Lu+@C|*igQS6nP#B!f71-~ zo-8(CIf33UWda$Qfj*FZ0^F29C7yvkl*I-tC(uWwOdumO(8sb*fFmZ5x{ASz_zNDn zUiNFCvVYSI^ocAsU^#(4O?(1Xn$MEXd79l`%d-=aK!1N zX@v#LJrQn@zn8@ZEGN(prA#0r-*W#b`vkZtfl7S7`AHTVu$(|YmokBj%s{`$J^_xH zKus$wQD>lEWw8Ov3G`bj6UfL6^t{f&MII0vVZs{*rwH95I2^ z{c_U^OW{{u4ZbA!TNWFzoIw9ed;K=ZkjGie7>oW#Re=VP_x7*P;=QQz+suMPB8!K1=$v|GJxf1w=89} zjeLL8O7;nGShO2E&lw@!S|$!S;yl;1G!*s5tc@%-U^(;KmNN5=d==47_6cyQGT#XC z_A+t6O_^WfGkgbGY`}8ncPwS*8<{#+kbMGNs?0Y+ypv2EaKy}ST8xW2=XaLH1}tZO zmr`cFk*RY<*(boI%6uclSCWYXZp!=;&-p9MVgr^lziTNo-^kS2P4)?JsWRUP@$NEl zz!5WF-JLcqe`=OLSCPdAENA|ziO>AiWS;;hI`dbTi31KJu2TJ9y%4j8tPEf|O?#9w zO^ux4D`lSmhef-w3o%BBr)A=Rns4OUzPaGUsLu8aH2E6r%W7h81dy} zg3ijy0G89VS1Hrf$oKGT$vy!Ni*{otXd}dPGI78WC+Mb?@~EpOYs+E-mNS2yQf9u9 zuatYsJ^?OO<{Key$;1ISWqye-P1cpg1}ta(dZo;KBU5J|*(boI%6ucl`^v-tN6h@D zmGY=_em_}kz;fpIFJ z$UXrsRpuKZK2RnOIAZ3jyVItXa?MJ4wJbJZIr9f4KJy35J^@a2=G!uHz+uEys{gB3 z%7@6x0G88q<5H%nku&^I*(bnZ(QfQQj1l6)Wa5CECg>7hnrtGA4Oq_nO%tE_o5?-_ zPITsPE)xeFMtu30plf7h0Ly7QJW`rs!Yg=}j`(+1jr{r2Eo7enhef-w6SR?MO}3PY z1CBUBH?5RMT{YQC78|fOOX7T$=?IxPV0p-nhh zZW^*BzNV^`#Rja+k~oL#wlZrIHPeTs9) zPL_QFtR)_C$QrqqJyIqPxM|3i_$+&rEH+?mmc%(^kCur8mWS*yyoc7OIEU=9vQL1u z#3K$_BWKy;Wa5Csh^y1;zxpZa<7H(4hbe;;jd6I>rr>4Od`hDG?_SHd3;UhJ+wZ>IlfMkeFCf{9&vmb zS&N+^69)|9c+>w<{~Ws-ZcTTIn!CiAve$Mbz1#b-zAugyWz+uWHVtkz=69+7huXA}1txs`|uk&P|0Beay9A8FOInS4g15PyY z3uNMeL0o@(+w|kq6#X6SF%kY2_Jy+8fVEi?=e6mgkylcn_^lan3c@%02IoI4I`vh1^JmOqqWWDBQnKSeqqr&Na8m!~x55&F#F0)~7hMzdOFZIS zV`RPNVVOAKL=%5RCJq?Ho93F*%{Bj##Rja+k~rs@M`hxG<+AxXl>r>4 zOd=+RcV*&$<%!`v-b3qCoD;+QvQL1u#3N1&M!wDSa4mi=of0Bs< z4kNyNObkEE$^Z^iCJ__EFEVk!^2G2f@1gZ6;`o|>ZCPr`%o4xA?Kjycz*^!FXEY<< zo%}8n2dpI?@w(H9;(y4*0n1tRXDPGDNHG4AeFCfvM#L;K5{$oP;()cp0c%j2OLIR{SL1S-W_ye{@orU z-PZ}fJ7&qWmKCYGq5M)1|J5I}Pwe6pJ_a>Hj&?ay3Olwso5p$OsgOkjtR)_2w42Gq z0f!M+Z^`OxB-+grAMF;hXn?~+Q)wD!v|Gx=0f!N9#zE$Ztdo&ww@Q4pTg##W4il}h z(Kd1lY9kW|tR)`j^*~#hIAHk<(Jt{>)L!-pur?SG=L{oR)IlZ=SPn+V#0O&q*(boI z3dUn5?r=NF!~x5}=$!aqbdh}mtPMt-7kw+r!~tuGM;y{dF7a2Ai38RWkMqQ^vP>MX zoc>*T53NrTv&cv=y2(BP))J31i@M9i0c(lJnMJF}!~x4$v}!4{$jDiGHQ6V?+F(S? zA|p?St}YV?tR)_27Of!@2P|h%kHlwDrR)=6Z7?Eck&#I>EfWVU2P0F;U>Ld9tCD>J zoakVzDH8`AM%?h4QqROkJ1dI@I7~E*I9{5GbLjPwi31KJZg@>;tx`tY$mu#Kiv~DM zG!^ZLSF1*duPqY?tR)^XO^sY z!^o|}hB9%$VZ;r8-@Q>Oqitk586b-WI7~Ek{St8=H1cfrK$$pTE%7)n1FB`>faN)3 zP~x*_u%RT{4H1QglIAAUDi0N-6 zi-ya@0c(lJnf_bI!~x6cza{UX^(kWd8wti%vQL1u#3N>rkskw%kck7<5|1;BM#{ti z%UQH_;j`z^|6fujgH?gX}v+NUKE%7+BXuM1uupEpDr3{9VA-#+26W~M#V^^6t zU@h@DhxBeTalm23)x$Gwjr>GsVky(q$o0$avS@(AM8i}O_ro)L$ix9_iAPLRBZ}`S z69+6$c6%j0i}sd%0;~;2#50ePVC*9k2OLIRy`E!5BXh>SiI4VvvS@(AL`%e+vA;|l za2RpJUsxZI_-G#}iv~DMv_wSvAelJeFyiWZz|0S{4^DivC&{7#4ihaA(LO{b4mgas z;fHAtO?;R2TQzKV)Gi7A}%V|0* z@o73+_6e{y7;&cQ$ue=kVZ=+eo)LC{M5O5)SsB1`n$Aspnw}#21Xvr4IMZ~VOdN0+ z@scgXgdHFeX?m)x3}87;PfL87o-X?YxKzO~@~h_gGI79K;&I;LoFNkjEN9V~iO-_5 zWS;E;&yk4(mb2*GQf85no2v6qx z9$KFwW|5KCvs@+n1XxQvVip-0w^z%=0n5QyRLWo&xvIQI_6cyJgK@1)9B>%%l70Ik zNBg=`M%zdRUoVRWI7~Ek=7~7;jJ#Q3u}mDWmUx^K_zf~~z;YJdnD{KZN%je_HW(4l zJVw(0W|=r(E%7+h{}!1zU@h@D)BjePIAA&bZ{t0*KE;_ux63{O))J4HMMmB%aEDAB zu$Fk7S#+mN9I%{4cO^cH9N8zp+F-<){&&m70c(lJnf~|4!~tuG$C>{3%EST7>A!^c z(E1cHi;Vo5_deMtz*^!Fv&hIb#QidHz;ZAiC}l8=`1GLc6W~M#;~|+iU@h@DhxEfT zalm23)w-#fU-Ldv$~3*e#KYhJkwpU>CK{%SxPQ(2s7xHNJZC&s%3v6oGai?H0;~;2 z#50c(;!nuL0f!MU*}_rS0TPj>Ps+*w4kNCV>0spN!cQfB96T+H1~^PK74103!80;( zz+uEo_O*Q20hBT*#PsyYv$8UP!-y+o+8Y@M&n12wJTHp|I7~DZ?KsE53o>!QVZ=-J zz(UvolrnLSgBN9G0EZD*%Cs{w4qi(9ICxnW4RDxfD%x?5gI8qYfWwHZTasn{8{lCF zP|CzP4qla&0USnLDP!hl?X^;l10y$UugjtV4il}h(KhmGvo~bofaRODHxZ0_KU|%6 z9sQ1V=CCU>sk%P&Lsn-N{jPQP^f~D<{Nc=CYg*M9`agJ)<4i}Z#Tja~I5Tn#@1LDQ z7}-~4Mh<*S<_1{i_BOc9r7p6Q>0`;vO(v)6Y$BxYiMbGQ-Z7&0JF-uJ6P+mU%ESSO z5m%?jh>K5c5wj>+#382O;;gI5qW5ItfaNTDKk-@gf$S6DuwW!&y7^Eh4mgasI=Mv5 zqTeIWMUBX!k7VM2=WRyU?d`oK9z|B))J4HMW30-qR(XFfaNUu99dNF zY%%#%9raCN4IAkck79v*^df zXVFixPk_UMk%;vFStbrxOFYi>|3xMaIE;8Au9AP1i366?|2N(v%%?2ISebR)pKZ&rE-Af^e^K*v_8doC0Z`~1XxQv&Mc~si38RWkC;WPo0vqK z$;1K6S=2o7S=2)I39vR85wpn1Q&=r!;()`5H}-y}+(Z_&l8FPBv#50`v&cv=+Q>cu z4hx1l6-Ue>BWo*dW#WLth&MKijNBEslZgYCv#5P3v&cv=I>RFHkq)E0`5z;(+BW>Qu@sG7^l=vQL1+g3;J4GLrsXWa5Csh&MKijNDwV zC=&-PXVFTf%pxPfSXuT7a9A)Jn?**_zpG3fu$FkltLt}7%thT~;(+BW>R!q$G7^kc zWS;=WQb6JJv%4p>V(&h+mo69*hdJP}u- zS(!LsIsJR_9$`KuBK_BreFB_l;yIZ(U@h@D(|>K5IAAUDI4^$Ik%~G`}+LC<&tR)^Xi;NIoS0)ZPjCft0}dnJ*eo*gUGY$vIAA%8h9y3WHj#Y-92Sg3r2nQeall&Qai;%fGI79R z#1nBPy17gou$=xiyhoT%iO8bivQL1u#N*7OEo9<=!-zLFi;R59y`@YXu$)C(B|eKr z$UXrM3q~T+f22$tu$Fk7>A$s19I%#noHt_I$ixB5>0irxXnl(FN_1P5 zyhoT%iAeulWS;;hn)t3Vall&Qai;%nGI79K;t?-?j6C2vQ6>&pPXFC`53NseUPJ65 z`vf@A#P^hm1J)9cGyV6Hi31KJ-q?#DBdgGR%ftc8>Aw%}5$01OX8(Og;pCVrT82MesVX{wv6HWYZnK)oA@rdbfMDZhJ;()`5 zH+J@)ZQ?HvO_qrR264Qcq#wP1cSM*U>JOzfd?7gRT;96-()Lz=USh=tuhqw)y}jQZ zvt(M!id5ZDe&e+NL*m&dcB%KK%MtRBJ(9f)yKVBvdSW7(4^q(RV2OLH`5flFj zGI78l{;!z$r?Qt}aY#hw*U51JoM_@F%ESR{iN`r)r^&8#E_jM z#{saGc*M*%a;q{|CJs1^cw;C26;1r`@f4XjV0q%7m-s9?RrU#RSTGWi{-?>r0c(lJ znf|BC!~us9Pel69mx%+G)Bg#LPEB{5+XB;4tEe$o%tV;(-4>nSVjzGyg(4 z4uHcFsIi%EWX@k869*hdJQ10HkxU%$zbEq-mNN5=B+$ij8~}$Ukjnfxze&GDCJtCj zJmSg9h~k&Z!~tuGNBmmO$XWI>nKqOFZI`HKO=cGI79K;&Beyt7YPVL429-tdcNf7qOSxIK(+*uaV;bIMKwf zm5Bq^5|21!jhtn#lZgY?5|4ApUM~{|4C4QaA-kBp)W#v=kTsG(H^^}StR)_2=HDn2 z2dpI?XXf7|69@e7$^4s3nfXSpc5ad509czq5i{Qi@mpo$fVITq%>3JA;(-4>nSXoY zGye`b4uG`@6fyISoUHDYi38RWk2CY{l8FQU_hi14_{_gsjsswA0!6$`GcxDjBNGR# zB_46e8XBO=qD^$BhkKJ77ehLc${hafJ_{)mUx_L`k+i4a2RpJY5EY-v|hSh9QhYC zCsLl$uXB*a)2Tdr`r^zO{unui|3Y}Au;IKieh)0|jjSzoYCJtCjJZxHwdJ@zgpiRh`F6sf~bb2Q7>GZ4|6~J22;!LOK zWa5Ce#KY35-igM@ICx$r4p>XvOq#xs_%wY{77eggw1_ubMxyB~vc%_u%;C2&d|5xRx0M?2YF`bMMe@!M1IE=XVdHrQgCv^Zb>GXQy z)9DR4DuBbHf-F*(!%pB9Yoxe1U?iR1l!*h@5)Yf5>Ye?K5PwT14mgas;WT|a@oD;w zEE?c2(Nvm7Jo_7o_Pa81z*^#QPS@|r!~us9S7{nHz7jrNzmIWHZxXoK#Ja=>vbuof z8_5sBEy?Q=AIUxe4$GJ>eAC^CQ%O2AQO z0%uGew@+nmfMsr`qBKcDG32>rE*H;otUTM>0EgvOV`r!SCT6EUWa5D3LH=i?V1%8f>dm-D z)@%NfeF7}|^f&JzSN$)NyJ5Ft_1rb`<L&3j60nwd*kt^F zp?H~09I%{4<-CX1r#Q2yLiP!;mUx_5)J!H0SW7(4ENU(j2OLJcWS0tZnzl%Mnzoch z0~{t=A||_5GI79K;&G;FYneD;E%C6gWdAQ_={7QPz;gPxk zfMss&!7XG-SY>#eXOIrEPk^G*^&`0|s#{(M9`984Xv) zuye#0lXPsbuEu-&??|XOqSlT)q8hQx(n;0=usotV^B&sx#yO(8$UXtq5|494ttb-* ztR)_CL>aktTuCMlczGL9E6Z8{mPb@q-a{MTh$G5Ke7ng$0oD?ab3}EQi38RWk2s=? z+~lt!69>G!ji^;+Eda|SYBkW*6-Za0UF+XmEzao*~F()FF7iJ!=i%p=ex_WIk;p|`TsQRYefosm~-{+ z)r}0soE&z*+OWqt{jDt%2P{wN>y$DWMlL6M%RT`vRWOVYw`AggwZy|Fk9z5Eg!sBL zalmpGt(W*L>LdFESR0IpL)u6%`pU!sYl+91Mg3&rfWwFzzToIz$}}}{=2>4B4RDxf z>VhL;ni?U#flM5*mUx_Lx}i)QusqpqRLU$eGG`2seFCfvM#L;KLVTc19I%#noLN*Y z69=p%9`Q?PBZ?1_i366?e=zT%^(o@zyAhvk*(bnS;t|u|$Rs*MCJtCjJYxDAA-=Ip z9I%#noasMQCJtCm|6#m`)~ASBWF-AJk$nQJB_1)0j1b>cCJs1^xVmBtn{Z0D+G1u6 zY_r6t)8=wi0Ea~d>EE;lMsENN`Ncp@q_CUH=|ud1cDS5ZfaR%oi)9k+|6=82OW7yD z+OZPnIb$oCIAA##BbF%`%Q`Eo2_~XwMxM(XDT@YJ8|{cES|gWhTg$`&gE$_oTRxu4 z+eX#`u$=j|O_{%~EE?caWxkP1%7@*(bnZ ziJ6G2p)oRXz;ZBlNPIAMlzjpm7L3N8*o~YYcan(%))J4noY67zBR!3H$b76!9I%{4 z<4T!DMuM@k>=R&ZFd|+a8kvj6%fta|iN~2m6J+9m=R&ZFyhRj-DKi` zcR z;)AiT>=R(wr~M-N6tMz7(ZM)a zCJtB*#-vgP<8l*stB1%w0Zw!<4wZ=mmVd=|}?eFCfvMx0r6vP>MX9E>@Uf)S@rb7h|ZYl9K- zGQh}?K1C)DSPsU##0TS4*(boVPp3ulDdKIGkvN?$`vf>F!3-~T%#S2moTKs#Sv0_5 zqJeKCmO6|?`%IZQ;4tFq;yf%(m-PWobpSJ0|7S%?r!eR0EkGHG%Gq*M0Eb0IrBj^a z;2fDaU@h@D&ravc!~us9H=L&Dl`>6@tcss6iv~DMw8o~Xk?&S6kck79&)XN4G8jhY zj0Lh!fD;{zi)7+}ABBuZKCLZ0mM)nD?mUzVUH}a#kYh~hqwZtQ)zmbLR>ty19L3}y-(c1O0 z7J%guwV3zN#y8Fpb%X2^U@h@DN7Rinall&Q5l57fAH&@w69>G!ji{StEda|S>K5KZ z8{dc{YO0BI)UC2lfVITq98tH)!~tuGM;uW`&QZ6^!~rjFBkB%W3&8S-x|8?N#y8Fp zb(icDU@h@DN0cKI2dpI?aYPw8N8K$G2fVzEsC#5B0LvrlUfx3+--sj1$i3kb*(bnZ z#1rv@?fYcnfaPG^U&>$@xnOue_6cxUFfgm()+^)@_%%3P0MNjg0MQN*Qedy%Amt^9A=R&ZFe2Xk7$N?qOdPP5c*OKKLi{b6 zIAA%8-Y#Vp85tSx$UXtq1|wn?86p0zOdPP5c*HC+Li|0MIAA%8-Y;bq8M(v#K=ui+ zHW(4J$O!QdW#WLf#3N>r5#k@o!~x4$^l>S($jJQqiR=^LQU$}vkp5IA4p=WQp1;YsO|H{Mx%fa}%l)*4E^?oD!1Xvr4 zI8S!p%ESR{iAOxy8OfsWWa5Ce#N)j0{9YywSWf>Rcn_^l5wpn1_vk;$J^@ZN@t2HMiFEVk!a{B+uduV-%nEpn5`c3u;u$FklEHW~Q{w@;- ztR)^Xi;NKeLnaPb&Z0j{nMFn>(Z6J$0BeI0F^i0(|KBokz*^!Fv&abX|H;Gw%USeK z;VAO~0*jEGreB>l@|;()`5xA4Dej+jNSnE1076%}6ks$vy#2H1Xy#all&Qai)I@nKP9_c*#4(je`)h`68$3e8 zJD0WYP7h0t2vb2lO1YA_cgov)*&e8D&t8TxXzY+Ra>nW)#{qDniFcHV1J)9cIAo0| zzJg2~u$Fk7L$;Gl9B>$MHOd-}(Na9Z+LsqqCJs1^xOy5h;`o|v;+MZG%ftbL_%fdo%a?viRL`3?{B;2iU6NB`SN1Y24vihM zMkeTPavT6Bns|4aIAAUDh(p%MB)N)A9I%#n#35_sDt1+wIA9Q8<{_JetJu}pOKlt? zev@Ei$gVEO0kD>M#LPEBd<~g6;4tEiUA|b6Rx+1hQM0a3r&P+BMfU9JbJAn@! zw5l=mztf06TH8Y=4p?5ks4Qg`8F}0#E&BvGEEwvH6)}s95YNcO0f!M+KR1dvf39aD zi>hSefaNS&vy@q6=WRyU^F(1j1bSt!~us9Z|sG0)P$mvoOFZHk?K2Zuw2@34u$)B$5}!o_WuE|R zgAwtJW+eTqW#WLf#3N>rku|PCGI78l{;yc$8eGcEH!=;`avT6_6DVTl8zDYKCJtCj zJkHGDSSAiQjJV-1JcpJtO^wWR!(`C_hl$qM)4Y+Z+)ZTSfWwG4_F~b<_lBFw!~ui& zGEdM+_}*}{Qf9u9d2Vw#4uHcFsIi%EWXRUY!~tuG$2ma{mx%)|P39-z>$fdRnfXSh z&MoCQ0M;f@#7h$+#J7@(0}dmeh&g|ROdN1&GCv7({>V~hzLBYOYdH>p!xAVFbN)6m zall&Q5$Aj(iyE~ualrDT#=WRyV5lsLIHZl7B=?kw0}dmuhIGWg2HVZVHR4_}almpG z?On<&G7^k^WS;7m3?p;VB$+s1IT(kOG8jg#Uk{ai0-Wez93~S797a45^XuU< zalmpG9Z||GGBPqI%RT`P3r1t-S0m|vq)Z%e81Y18(NQvSz;YHHo%k#|M)nDCSTGWi zMaRm-0n5QSu9U$rGBS>reF9vnU>KQ;rpUwr%fUDS!Kk;2|8(R#w7{QybEebJ6=qLg zoS~m>F3yY`!$0WEP9co!t1=@8PL;U{tRWk>CMQ9nk5qltR)_CL>W0}%$A7*UfxF3$+8xJ>U-{bFnTD!}~h* ziW>}PN67yH|r`o;C_;eK%gd!%37(B953Ze;J^ z7YEoo`^ACwZho=a-pelzviJ9kgY8Lv(YBB9i$m;V{Nl#;34U>?J>4%3vuFFoP3(Do zaZ~#Yzqpxwu3y~TzQ`}u*q8go;r2CtaSQuKzqqA+yIKBi+kMN5}*+==sqwQn; z;xYDAzj&-Y-7g+z&+?1M+jITm6#F#4c!GVVUz}>6>lf?lQmK@Efih2I^CD$VWAhSa zPG|E3N zZ1H0=EZDwQsyOWuB6OM z+3c>&%h+69nU}MfQRWqF_EP4RZ1z^>Rc!WA=GAPjugpbk4p8PbY}(4amd#u{nRl`|Rhf6Od6F_6HcwXO-E7WN<~?klq0D>PJV%*J*t|fQ_p!N9nfJ4KxiTMM zbCEJ1WOK1HA7b-nWj@U2?aF+FO-GskVe>v^KFa1p%6yE?N0j+En~y5<2{s>B=96qb zsm!O?d`6j1v-yHDpJDSAWj@R1>&kqN&9{~LJe%(;^943PROX9pexl5m*!)bHFSGfD zGGAfyzsh`-&99aD8k^rJ^K~}ARpuLPey_|o+5AzNZ?XA{GT&zNH)X!V=AX)Zm(9PG z`5v49Q|9|@mivEAsO|$cTPX8GHrp!mBR1PB^J6wUEAtaJyDIZjHdj;TXKbdG`8k_a z%KU=OtTMl3b1h|l#pXK7{4bm9Df4SK`z!MsHaAk{w`>kp=67rkQ|9+raquWat1%-`4?r_A5k+(nsxusKngf3mr!GXG+8A7%c{ z=6=fjADag%^B*=RDKkZrynUE5%h)_ZndNLArOXO8k5gtdHm54HIh)g!*@Dek%52Hz z9A&m*bDlC=vw4~_+psxbnQhrTOPTH1JWrYJ*}PDh9oSr`%#LhcuFMtKT%^oSY%W%2 zXEtw9W*0W^ROX6o-mA=&*t}nvE3^5CGP|<*m@>Pu`J^(tv-ylNS7GycWva zRkc0Y#2=eOZI(^^)i9X7*sSpH%$5pnHQs>Dp~~El&CQg#5t~~m za{!wol{t{jZIxNgCVrBI0}WymzbAn?m`yxi57TB7Pk6%|!X_Tog}E`Cc;*u3P&V<@ zAIxEF9-@xB37dF;2(_ECi6=o|ZpJ2_MS!_EoA@>yW(}M80vhIUHu3El%q`f&(m%{C z*~Gf#$Q+hhMwgE+%i#~S)pi~}IyJiPANp6@qpn%EOX_MX>;9Lj?caXy&a1Vm=vl{? zOsNjzJ6G(`F4eKNd?c+B)Rxsf+BcONMgL_lA#ZA|h4g7H;ExOV<2?R2hd<7ukCC;V zsNrQ)$_}Bum(YunQ+1nkq8BOiZZs-h0rU1dU4N9^`iD&-+7l zmtx0<_>*{EO-_2!S@6iBvWXX z%F0UCc3;)ZFhhjQaKvzK((X|J=Qu+rkQKyEnTglSgms27*m9j7iB3c1vk&M;;Pg zyA&0<2}uu_knPstTvQs|zY^~Ll`^U3+%vQpRCs?HTyt;@XH?4j*nWth8(AW4H!ns_ zrtNM)Se&-Cl&~ai*E?a2w9RV5nrRyn!dhvI+b8AjIVBz3&GZf?Gq~7x3wD>>*xf?9 zA@&M<48@60vV#c7F%Pa<%bmj&IF?<;!zDai#KQ$VoX5ktIN0_9&G`6=6CYb~;^Qh# zd@jwf5hiMD{8!Sf-3l-lh>xWix}867Nj-M6Xzx>-HSLXNd_pyWpQBf^4di@O9bB9; z7odDL%`g#OG`z7_Ze9!#{UtiX z3erRys#2!P(4KkVzuL{(Eu$fvv47Rfh-Dj%y8O|s%J(S^+Li2zqHrIw%jxrewu1bJ z>tSZ^4whTW0uL@h=pPUoLt^CwJksNC~&ipo8|j|I77%DR%d+*6i2#)>aON*ALe_LSgn zG*s!Bh8__jcBg(f$8Rn8RqQ&kmn|H76%>7}9wJ>H4_+rVb z=>*lOCSTpa6JPgOHOWy;emlNL*^`J<_BaoZ^6)SYK>_)W2krQ7CqpG>F~_^{&h4H7 zql)i&vZuh)l&1nM-}98NgQ)Z&90C`5a4NCIYFU>Xo7zeNcYG66`ih^Aw&`Q*;NoFw zs z))ICZN`0|5+qvCqVD!ZoOxeYHmGV@eLQ+6~@=X zydx^#R9P*YpgOhSyC8Vt`y;CbIcmWVQT8Z%55ddc;o&VF-oPQK1z#GW9p4URsH~bl zAA(WEH$~Yc`GE3NpyivQ()AFPzK%oSB4+;ZT~hA+Ve4T2Ftw^OacjYsP1*Cu!b8rt zPF6D~s7}p>!Ua4H#>r|%j+*hy5k1PjL?&gQ^YAGTAL9_zY?x~|9H$JGRW!V@I4Me&8E3_({ajBSyi(?!RT@ZPT4j4o$^$m zodr_*2Slac;Sjipso88c$f+4y2Q_1Axive+hYxCI;gQy{kXy~1pgJ`>11{j{RGh44 zOpwL25143$+is|kC$T!>S4%}OXw1=_PgN^3w= z`WIRUE@EnS4jbgujID#3F}2*9o$JE~HM8(YYZ2sDGbgA{&8~q9c)AiNs~I_J#t&5X zDBBcSmDS^66CP^g5Y%k3Yqu1q43$+i+Y*c}uf-|5W}8!<3bfaQlx_i0X)PQA7cn(k z#s)bxW9y)1Of9!&H~8>D%`809S`N9@%n7PfvsG{bPbiVA898dkZ+P@5+YXtOZOg;f zJT$-|sM*b~-7Pp}sI014BQUz;qj`4CcAz{JXm1B8-4P;JGw&j%W_O@Lh7EkAT8-Q7 zl-m2SJ1l#YTj~t#=_V+(WsTn41G$yj393`-r{Dsf9>>Y1 zCpk*ZPtf-$D@7({JM++thbA}#rGDDAdj_Wrl~twQ4U8_I#VNbgyHcJCw9kW-rXVV9 zj6>ierqnO6K~BxsI+&hJEw^Sb`tU)`EIiVB3398M6I7>WufqjAy@Hd~j2tz4!D_Y_ zGAY}WhcX^^$04ZM8?N13IAy4;s#zN_x_ld_?3%TvJQZl)1u5MJB3Co-BBo~Vp+SZX ze59I<+wDt_i1dEoi{Wax=^5zOQ2LuFN|yMoc>uQ+9wx-;deK>IsL zX%~n}+u{(oh$;0SY>-nkwhpEzQ_HQ{pFVsrJuN)a`U`TanG;l}W}D#67(CU+$!bQ9 zn!Rb$vo|s+>%~J)9=hWY)U2*+S0ASgl~pzC4@Q@pLX};!zLci|?dH&y_JgRj8xDbs zn3`?D201lj>!4;#Ew^S{`tU)`EIiU`0J+u7393`G7H|Pi&2h4tk)viGTFr(cld?m2 z7{tTDI0Q8-b?tV=DMMvd%?<;j%M?`EH9M5@RG{4*+S1_=l@7oma1m3pmTZtyGqw(D z#?*3aR_4P8HM8(YYY)h+W=>F@nstT?c-kK)s~I_J_LbFa3^FMz=V25NBXJ07*2T5! zic^Nls+vszqswkkW!G#R<*7j11KQH@5S5O=A#f2>vz}~_Q!};>YR1%ZYj&UyAJojk zBduPLTg{xHIyD;x7w|L$C#xAbYWB0$tOA*oP2ph@4-;_+YIdk=cNk6?DywQX1B@<5 zK$TsyqbW}X+QXqOoeojykvIe{Vrn*u4RUJ6)yPQRz$^0v9ngJDv@4YR1+<&6rwl%}(&)gPK`*q;(?XRx>B4PR-7R3wSyUC#xAb zYF2Y4@0({Jld{uzn8(8@I0Q9Yp zE#l!E9?rrcsM$5JE2WfWX|f%1=j)!ul)mR*FLv^;?>l8^2aDoE@DC^%ddcnH611Y5 zpnDg>f=Mlf+`8uk)#=_1Z~;%(;bh$-NB8)>ky}GDG!TzxEhC`BdcLo zdIJO*s*wBM7y}N~ZBS&W0O!9%RTdSM;NLEait4so4k?4(9<=rP-}%w6|F)xpRA6%_ zZL&u^@M&YsOma)K2KLz{TIOTj1-X^T393_~d*K3EXK=C-k)uTX9rqq(s}ZMc6%Q+U zxDkh-MEAiiw+l2ushDSC6Fb(m?yyyEch<(XjcRp2T4fjER`_M=4?u23aDwU-;Ssoi zr-yK|B9Nm9t*r=mBTm^G9`4}bHXMQ?JPNzqBG3dyu#VF*x8qO3KD!I|z=DCFg50{` z1l8%nb8rDq>u|CzkfRIxSr;BcoU#XaSj)q`I0RjI9(K81ph?gLTIP1)Mc8L|;SpFc z@JoVeQ}!eekMr;-4nY^*f?ese5afL(jcMln zN)X$!Z}`uB2oUk!X7lGZ(A<4%JFNLTZ2o+BbNvkk_uc8R=I^0-hRu;uyBBbFeSe=` z^M5CrHK_V$7ZxM}Y4KMYOZ^aE5ObzX+qER8_(sZd{D` zgg@H2-p42Wu_c_cgfZNo(RcRR%W0CZ3%0OwU%)tfwm-vO!^xNQ$|U*h1#|fwa_f~7RHs*e!v#G3iIeq;9KCwgmZHxQr|eT6KIY*=9D=U> z13Mc+|F5MF1iLwVA4YR@&oEn6b;tkX=$8;O?!RzjJ#d2R^q?3Yq=Kg+oU8}r=)rr| zgC7v5>^mO5;o&PBf*zE>F1iOaM-N!_Cho7wux&vk2-JxPx!c{ z>jydd!N1(pqwG(_Df^v=UwQZ$hoB#uz%HyGO|1Gf4@QEm3VQH2gp6AkZmb7RP@Nv| zBW>_h-x3EPM-RTY9uz--yc0b9hlpkW;1Kj+3)n^XfaZQAHg_YzwgvsD0oRPaC7fA5 zoS-`W*aj}(X)8+~fE@kcpO^1ZR*zlSgooNZ)Wjj^$F{Hw>xa81(mWUmwkqhsrVui2 zL%6XXI6-xK&Y zpdZ^p$mosX%=+O3)#*obxPYgomOcPE`cc>Vu@mBy?a0ISJT$~1=*P~m3+o3yDv8CH z=D|p?RY4D$K*+c);Kq931l8$53NGMj7fT#~96i{|daw)Pl(pcYIS);72zsy^?CjnW zy1vpp=mA?5^dJQx5w=>SU{fE+#OZfk09#3}2=Lr)&M z;}Gbex5q4`GIUc2+cE0!AGlECqs{5?jyDsii2oZd&pYIiYg!F$1^zq zelk4NyidnNKy7Q)8wRmAk4qWZ|VAad0!e0^`sxkFi-lE9O}sclHr~V1j){_ zxN*C~ylN0s1z}Qw_7Hj*;Z28-jPztE$>E+1BN^q%p(LX{8BS8}$zdc%crt=y42kvq zaL}N1%%_HX^V7K9SZ_ZH28D?R+R@P3CkV1XUC4P~^_a^GAb8B>jK_G`)W{kQ{Ms;I z&XsSRGtU2LXGd(DGhPkR&c?u5hrux63>gbzpS&LjkQ(Qu<4MMQGJ#}*Cr6ST>B&(b zc~fGdS51Pdu+o8c3cVcVO{bDf@}z=fvM19>rg(BR$y86KlT>&zgJhZ~Gf9s2WEM!l zyN2qH=MHU*}A}C**k3)JmJ1+8)(8# zXy>as+Qx}+RN5|S!Xwf)l!TMgb_EkoN!!Q~R;2ABCpNUy_DyMDajPg^(X}i#k?oMihY;-Q(bf;}iFnTJf%?G0kNNxErdKRfo9i!LO z0<~q$=(VIarHw8pwH46lO{6ya``~h6aZ^EQPv974zr4wCCFg~Q_v_gUv|kcVggt!* z|40(7#wT&a`2NNTs&ng}3l~W5WSndzB*(40pWV8TMOJ0Ad6>z=bR2?P_dM8@o&dpy zZ{2L`7Zu&QPi6BH!<*YJm)&)@?y%;kvH3~i&2{hH+7{Tb=4S-W8Kq=vB*%q!0i`*& zN_IHwR(Ue073oY^rYgZ$x`iP06Wl6~_wuu7bc!culg#zx9FlpSoC}g+SCB<({MV#z zyHmYt5mW`9Q-St8XbWyS9I>jK4u>wd>2R$4C}gtwNHO-Bstxa zi%8D!? zts6#%k=o!GJ(SdX%xjh5Q$g^{*~^$&VeOep7%-5b;U|+0lO= z_et#1O1B!acK*D_@Cyjf`FC&bmtu2A4&Re`ta<)urpz^*UQMSts|+tV&H=76xt=)x zuPLzi(=x(-G3?pNq_T(;-YdpD|WU(h1k|mzp15&V}akQ&eG!A>Pq6Ixb zFEWKaxEIdUgZmg}sSmT33VPuWrnzvtzDfn3X=vGbA^8@+@QK z|6P;n#(XY2=JO1*%7=M@oLw$*+!NKP6T- z=4;t8UkAbcGPquCA>m@d`=u=tc9Y_8r0vQz%HpIgQKQT*ZF9otTcmdV8hxMCDrxi+ zQk%3!za+I~!030RcC{J(nbfX+qkoXv;q_%_^okwcR z26qn}j8rfbZ-Us@IR3XW=e@_@ltPxYx9Kcr5$DY&dJ%sY_DnFiK?iq+_aL_$v=db4 z2K^CSpsyd`WOpQT+@MF>4f-x*Rdy#2xASl-4#5rjW7m%J2hBfqr_XRIT??xX-?iz` z7f5&Q&)NL`4K#Om?Xc!wu=xYw&FkO zPktqN(v#mvp7P{(lBYf4rI}ji$)6<8c=8v?v!47-@|-9CkUa0nza%es!Ye!Vq9^=- zS?VQE5+pBsk|cS>lVXxrJt-l1%@ZyRsnXE$XNqv&{J=v7x15Y+1S?|f_Bp-UhWhwQMCtH$y>`4QXPdwR*h zZAd=%WLuIiJZVVsr6=2weC5gZBwu^71Iag@>`3yhCyhwH^JFKI?>%Wu@`EQ$NPhIB zDalWsGy^GE!gz^S?aFwq2fH#}h`|z;HHH1YvN@b-zU~Zy+g31r?GoTL=WWX-xUH_- zxuk6x8Rgz3ZL`-Xw-ss2+bA~{Y3ra--saO*aihFZr)_AA@*bMDX=s!SciLvZQLeUW ztD@0&NUhvP*OS`#8~u>fCW=umY-zhfjBRm;QoEpxvMOo2 zj*arNPTMRt$_qPfSA|htrfHkWMtPy8?aDC9%Pwtm$tW+pv`spryo}Oz=^5pPl(sA0 zC@+h&T^2@pVWjOcGdh%aK)ddZ4kNYY#^?xAn@&bYlG?m8T25*gg3%*L?TRrvp48S2 zqZ3GNxiUJ5)F!vl$)t7_7@bCHm!;98N$vVII*ZgUCZn@S?W!|+JgKcpMo%EM#n9-< zq_%t*tt7SOh#LS->r^nQOF?4S^+zz_ZC&4m&3*>sEn`;@x(*)dGG3md(J!9tPTx8E z0p3J;@$mt_@ZxI;`wkEL#%1*Mt0#Mq{N~A?B)@yoisTPZ_9FSylf6m)@}xD%-=6G4 z@{cENNdEO?Uy}bkX-iV{pzClul7uJiNs^v)ASw2wBT0!T`;pY}Bu!G&ll@6*d2#?r zZBIIp)bXS<$tIq3A*t(0SCV?3bR((nNq3S>J?TNRnI}C-HuvN}k}W*xMY5$Q2az=J zq&LY{p7bHv+LOK@1rNi~%Wg3882ylu?+0fZ`Th*EjSn+`WLr-TCTZx&K$7h|8AP(Z zCw$wL+QAdP&Pwg*317OU8hOH3ZmFF-;S0A^V^8?HE!D)6;UrBxIgF&4CnHFjdoq$_ zXHO0%Y2nEzl2T7blkDP2Imxb`96^%uWDH2b^L%xyI~LAV-Ej=Fn-4RdWOq*{khJvV zNRl#7CX(#o$x$SGdNK*5;2l79^PCK4%5w_CwDMu5lI-P41!3H_w@HraWgc%)UO%Y?8K~97EF1lVeHRdvY8}2TzVC>FCJ`AO-Ils+;GD zaHc#@VwnAWm^mbAPfjM;-;+v`13Wo}q?0FeNjiHn52WDzM0N8#70#6BX$;fFhdG_3 zt0!lWbn|3BNq0{cko556Op>0SECeZdr%~NJ&w?}Mc{T_(hr#X2?xVa{a&u^RNxSpf z=FpZ|qqaG;)!nFV4lQq^wmGy88nw-#&1R#vIkahS)Ha8T35+Z@_`&Zun; zZ6!2nn?qY!joRkWRzstOJ>_7Fz-fRwgdj!`}$rGMkz!zdq;(smsfO}JgQMr{*r*SAsIgxg|n)HdO^>KnC9xb0tz+9uq#O-5}K zZVQ)D+l1Q+XVf;~b~`g_n{d1D8MRHgEzU-56K<=xQQL&u?#QTZ!fjJ#)HdOEt2b(! zaN9Z4n{Rp4^;4Qj%0Uh5P?pXhh@BYPX;~ZZ| z$M=OhR>s@g2Lv|G@g;DaVJY}ay$5mvWte{zV^Fa6PUqi-um+8rczeH9&v;#9Cq^|c zg>PCW{D` zUmkk%&viaZ*G6hTU(Z=>aA_i(;Hx%p)pF(aTv~4=H-y44h3WJZv?S& z`N2Qf%U957xF;(~4)f$Dk`bP)A{pt)%_N6=vYKR+C%1qUJXLapt6t`DsDqbzERP?x zOjghQ%e>p@d9?R@J4v}GcaR+6$(ODWmFq1ubh-8W<4{uz|_~JfF&r`kU$4DwX zd7NaLCr^+Z?a7lM1y8lnqZ{Apr{GMTewtyX`!MTBW_a=pW9I+;>FAj8oqmpr;#O1aj`kGu1X9(~iPQh*0;&W0o zZhr!=l^i*TG)&G}6DH@FH*R-4{iK{Xe<5Z3HQ<%V;bWLGcCe|l`+CZnLi?%L2AjIz zuKyY2wyAT1>TK%1h6_aa0w>#TkYiIf-8OY|k$PDr4|8}p5r<$?_YLeyPlI5?n>x1j zgP?zn|CY^9-#~M>sS9iV9h;xAf#z;g7uNiHHlH8fyjJj!`J35}G`BharT~id1Dh`h zZ?4A%_n?#AoZ}n+pz|XgpGn6#yG7Q$aJTpqjTb^?euHPF-yqGfYY0X~r@HMHfpLs~ zX9KG20|xe2y7*%)FzTHOZ2n?%W`F_fcs9;9DgK5ub)I+g4@ifzJo%TJ^F8^Ghpm*u#XF-76vw{uPTrENpGMb^TIY=NBbI5a zoKb$rGHvBDdM~MspV9kBZJdnq1CeQ~hEaYbGHoR=%FjWjZ5)mAlZvAt+= zw>R0FB;!eIl6ySahvZ&Q+JF>1&{Vfb`)-`G_#(B1GZm>FbH2~#+@55uCml%c_oO4q z1D@faEz(4kmftlYt~Jcru9OMNbBkyyVFtBrkh11f<~KQ>$B!p&REcz8u5gOyxKf z1UJ=Sf#Et|%JrQ$Ra@EZ&aj&IE1N?``JIWhU13IVCAE?oy^YkC7Nh)HMB3J7qx@n- z+NPFKyItEHG-|hNn_fomqOo0;M(yrx*RN5#d)uXHlwXoa+k$S?ZsvA(F={t+yNej* zR~^zeq(<%DZewrM?(H_LM)`$@v@MB7?N)EAuu;3!+tO>4Ut37q9mlBM`R(>+)b9Lt zn={&#w_Lj(jdmlo)yimhQk$Medyv{PZL}w;-RF!RNNSg4~4qqYIDo0L)8fY_bM=wKS# z4cVyeM{IXs)b=B`3*df)Gc^^=)5ADV`9}b*EMecnwk1wnLzBUQ>KLTaiO8jBeWB|Hh8`cwrfX1ZqL_FP@U)NDR6-ZN8x1K zL~=Y|pJ30|?;`cGw|RJzhu3ikp0B66b`?04egt{QV|L!}KhTBWI_WWc8k>I%MTS10 zWhrab4gSGlI@B4ey{2U6cAtSU;TcfTIM~6yPkAcP&Z6HBAPPw<@1JzS(wfcY>o?Hc zJ^hC@KZeae+(2{pZ!%%ck7M(k2W%F;>H)jsr=T`i$HOx9IT$N)0!TqcAU}~tUwEUF zNWS!B4v78vgX{~FV_x<6$H5OC|5#5yfSIg}{Nvxr8|RGGjdoT^XZf$=qcdZzqn(`s zXB|F)39B?0B=wai^GLq-M zkIw%0(#BWgd^-C-RgDYaOx3s$B=v(Yz(piKdU7#i{_h=#pBtBKoU{09TuNvE`#8m4 zDVM>Ss&P3;>L*`-D@cC!cX zU5QU3c0b~csCC-bS;DqyyQ~P?rLAy;ozr$(BJ7^FRfw=h+9n-gu;9YhplAu|2ELvZFs_(-^Auc4~0h8KR7hDf3FB@z6#CJ>D4%8=mpueOXBQGa0{L1 zY=_wKs_hU*VtC_rC2RmMx6(X+31H=_HZ?3^u&H6qf~`ZAUv6qT)S$~$;P`er&c8IP z5PiGOMnfEIkVWar~n-`9z`(ewR(X8Vu{UBNt zj%J{J2wMD6Xd6v*^%1(ySuy1k-`UE$j$r?&cOI;mHdP>hjBdGNIze?-%%|Z3o}R$T zR!nlNm}lFHxj8ylwkZ$wc-RDoV8vVqyV3>_gj_CpkBDsRuRE=n&#?Jc;mu2etId7i zI;{D#Y`%4P^Wvbndqm7`&H<`XCwM%5F2;$v;8yKyC&8aOd4bJyE=ATScVVqO2>)`| zxLrdiSmhVlB>#ssSmdh3mDLUwSC%(eu(EvH;<_DOrUJ(=({U&KXma-RQnehX%rSC( zl`eDUDC=#j80KhRILy+9QaVny3oFFyp@|dh+yO+X#euTD4_+xr) z?!A6Ova=_jlC<#TGm=tIJ_m^mp0MDRo1-|)qOvwX*Dgi)1L~ng{{p_0%$FdzWdy~v z0b$X(tF&^P$G(`6X{(pfex%j|qy0&31dI+KwR#%mR|C`5L!*O8ZG?>Si(zT2x6$dO zRso|kNNog-&Lp+*Fv>4@rL96n`4z9UjWBnc>{u%3*4H4k3D&|beObR@@3|H_L3P%` zAK?PwzQf5TDmm7|i)}3|L!7eRc}VfF3l70r_!I0(TS2hlwUBN7C9SpaXExs}ym{VQ z7}oq3Hs3qEdEQ!>-JCV7S_^-Tagw(dW;+Si!avwNfBj*_sunhuE?C%DD_?~S3+We4 z|0?Xy|C7%Crn8)7jHP05UQva?|0%HN$iSZU%2^r;+x~~P*;8{*wB&>;s_Cbu6I5qv zmcRu(C2_K;Nsg&`jZMw=h*Q>&h%b8j}L7Q5I_FKR{dwO() zM<%`{;ht514fI~1nwuN2kfe>tXda!N& z^k~TDy*AL?O^>kV+p+mU;mtP93TwVSoA(ZHuE%CKufm$|z~+56(A+(Bhc$1+ z=6%sT!yceA9NK#JlhMWc7nq%B)GyDd^1sdSN7jN}XcL%Z=*PP#YSOMhSdJ{=Wf%+UWOPA9s>-y+02)rm2INpVh^Dn$=IZl~l3bXDK+t-sxaV zx~g!yL7Z2(!8B3fjG_JROeX(%xLW<|aERp)I4+~({3rNoIZl~ld*b zwpKX!-kZL2)aD`^L~ zfTy-N*`-5{mGo9yNk^bBWy5(G#={UCf|ax*>`F&L5VDfmR}Afc z06)Clhs`H#pt-vxg*ETX=99ylYcKBpwnkXIG~6 z!L-X6E;eG9c(t%9xx+QEz@Di_+YhGwUZe3N!fTrpRldld6rO?x_{HE`>ScmZXkJ=8 z60)nC+Mga6f<_sd;YDUk-f1j(o4$M!_1{dK2m^L?D6DO!I6-x0%3*K;Plw`UGld*8 z3$&5sLjuI+=n|7SO6 zA*!C64yTjj!<}dg-44P*c9qwA=zsjN}wkgJ{ zaRQ{Q>ewJbw`x3Sn_{dQh@T2<#?xjN{?d&510iYu?s@}7z1!KNXPlxhH5!ZnPU`W5?$t8bDRTAhu2(QIatu2JKhq$$3&jblbD_+D3wWB2lU*p}xKM@O>6~#$(zlHb~i8Q zINR5ovF+=ounW%F`bL%4p#o;!)|tOz=C3r%FzfmA)?ilPV2jV`$la<`X=SUbQgPyf zhK-97iTa89$y&(^8;M3D_!BGC`JJ{4oiCnJzlb?^k5Nc4fK zN5%9h<=L$^H`PH<4VpQ9T=|r&R$D+-KZzs{Q{-VWk%vUP9~|p`yxfn8abFHyM8`%& zM;;j)d8#5$iitci+WmxB_s7Zo>=^emp^NC)^ytXbVk4iT$a7*MpBU}__*nO6%KaHJ z?oWd*qGR)-BHMghB=={>xL+9S<1+cUIL60?&_$$peysaz3oxL=XK+qZ!PCr!Z4y!o5#i7COq!8@o{%j+#TYaHx75+B;NUMa=r@;BRbV0F7EE( zaa+d6ZLPSi;+*dj?z~OB^L}#PJJ&F0PuL5(hz|FJDs=WF65XMSxJt1M4^iYnF_90B zcHckNeYxBp9^-xlbP*jJ9vyjDY~+cGJU%A!*l71h#JZm@_Z2bjr$86cu}M*pZR>Qb z+|P<}KO@%1De^HV#>a`!MWlFqtot+M{?r)vb7Orhl8>{a(^wegB9T}CRm9v*B+r8~ z!6Cb%$GtHS&9`|ZhF^>SyS<@BN@CQX=?8}c91^nT}Lx}*O5r>0%iV$uWSw_Zh38#^xm+_ zn*TXTw}LJr={=x|NV+9deanvx&v-W|<9f8K^dUXk7s{v}by1HFfK^nF($Gbu-4UwD zwA(`&mv&p}3(`ilM<}=9u#3uV7<2`>727xuk^8)=Hcuo5OP3Y;XuQ$0o9IM^9v>5W zEOZeAeFRhmS-CfDqZK(Xt4cRJ50^eGvtV`}1!dG&&Q#Jz!z!v?70^XwHbs%cGn*uR zL1q}PQxtwqO!yO_i>TT0P(@^RtRjbJHe33z%oZxM`LK&B%<0fYWOgc45t+@6jeMaZ zpBEGP+-Ub_$GTrE_gBTZzarZGWpW>0*Gr@itLrL-Ul9|2IdlX!oL<1{uSsVYW5OT zp_y^V_ZE~<9bd1=@5MxZC)z!-|583ai}CRZbP?Hq6zx8d{0hpb?0;0`?_wf<6YU<^ z|0N&4!!9DjU!z21#cdKDcPGUSzc_c4 zKBOKyLm5(!77)kOqqp)p5QY)6ss~gNrRoM%+z@t=J|yKnP==)37vh+dhbiSlU>K3t zAjJ(Y<-yX2NA$bjlI3}+nmDe~JMwD_4R1qncLlsxbQPPK`JQ2!}l#hZqCgoX5 zc{&Uu@|vc&;ia4^eMnxjp$y6E7>Hx?I!$@ag<(V~E1`-=c@9)@r94skkd#k{G9=|Q zAdX4-e5HIY3?uS7TXDlnxlsC$ye@z;B(Do0j>&7O^123w5v9Bes)&@YfGVz(mq{Oz z^0iQgq|n|V{&>>Ijx0Z zL>cdesvuqWteJr-^6C68DC25;r}SC<2_8frf-R1BMZU@ETO1{oxk#o$$Et#>f3wao5K=|0LY`r}56e zm-BC67}2S(;^O`g9{0!ixPK__uW`=*40rxlyz^}u1v|qAjdF%G=l$Fk&_#53GpIsG z5g+D)%1ykiiN&kTUKll2yiqG?!U zb*!}_w~C3pN3{EvvFCNTSd-WtNn|%HqwWUXdh+P3wBw{L(W|4 z30*{H-Jyz@OI;N?JhRTyhh;WcnH?M!y@tK}>>nMyZ?yMB@(?IPmdGIxXVoD8k!+Mw z8WA0LcwF4k;c?63<4#fBqhJ^@5Jy54F%aXSinyo~$*E9=l%fLSm{J_8lx9W8oe>xJ zxbV2g$H$$oxTnD|q7?I>iYUb?P{rL?PnN!5P9~BIpbRP1nGna6>LR6lJ`5xBTBNw) z*UCB4hvaoJlp%Rt0&z@U*DJ53FpMbWVyGfgz8b2yQeG*2NXpBg3`zM0h+|T|O)0O2 zVMJc56gRw-E2R&~>vkwZ^11`!n7leR4(`b98s`}1tfKou7g6SYpepE2XItX-hAQIU zt?}Zjt0H%biM)Tb`~70w_mlhHG46Xo7tyhv(UH5yMjoQbgJL2d9PPe;tow4gKRm|$ z2Gs$o;Gs_cLOBoFX4{ zVtkwkT||n<$GSg5?oW+zKR4FLBKbHw#>YbFB2rus>;7W7zaYl_d9gmOk&i2*)3`j! zMIv!2R1xb+BDomKkY#WQ#4*d@3Z-;IblmIX;;syjdsBSewTgQW3?oM5Zm1%b*fmf^ zmg0UWLrU=g#4)9KQYk$a9ruyAxKD-0eL6nwYl{0a3?oYMB2*Ejcpj?AQoIgjNGaZc zIHnZqmC}3Bao>rH`(b$8kK*HgqqtwfFrpNnLls&IzR>tKJnnb#aer0ZpW>YV7ViA_ zc<0F`!A|2p7)EsJpSZZiO+p8;1mc)MtgE=SVHjDldg0FN$2;Fv&bNYLM5nfli`y_f z?soBUn<#FhIOk2noi~ej-ciom)z_lzT!&?i3Sw|7iF7 z#k%h&_q}7>_ku2>V?CoIcaM!cM3D!@L_Rp$eg9bZqvU=>jQioxMRaUfRAk#ajg$K$ zV%(38^)XdGCdK%e2wg;q6Jp)Zl>4J&+*icM#uY^WmUb|N_k%8)zI z$q>gZUh|dGY0+`##l>9^9{0@nxECw#1u%>lk@KL6xXjOmDzX%pKp9esOCgRa#S*1- zb#&Y-L2UG2wTP4&O}f!^1a`z94)exf_&Gg=wSA_J&ndVOl{KF`9co6;ZR6P!+sZcB6%w z?61fjVB8QJgXX!&mqc4(`164$3v!IIn2*3;|?mmfI5Lb~Wsxa=Q|`h?#IXRH13}?zR-ls1dtSk(b3pzAoB5DtnuJtd8-q3c85w zS4O)}ByWc@D*JmB`L3AAcSgHM_D{&iqcJ`nhAtxe2cz6468A$DH)HRUzF<})l21Yz z)$x~<^z*QanlR5o7dk5viFJw`K3|`bz92Ky>}`dA19lO0c`Z8nE79KZSsy6#`;E^u zzYB3zNAv#y{Zpm%QFPq(adAHjkNbIi+@fZ|p7tLYMwH?&s3Hd952)g%$ZygY3r$^ z-b(tAly`zMB<02s$E3WQQr-oI5qY&x-0*9yx%44LC%`Zwuj3Rqyp+dCAClL}P=@4H32{tbid2 zKji+`823Lz7tygFqa%MG8#&oL*hT&q6ZxNL_kYE@uPgVpn@1*J6RL<&DS;|tR1(R0 zP=;LY^&yVA+_zCm4Wi?25f^vc@VE`*t6lrRoH6OsRS+ zK3t7{v`QWx4brc};{eB(I|&j>+qfVU3HDiQ?p+!*;^Cej<_hbr^Rl zGbZsTE{p9aF74lD@YQH2x*l0Rebnso$+N~4sDFgo4aKNwV`d&VZQQ8x>C?-P%gXdf zyRpI!a97_%jax6MD(zrH^`BTP;M2%1*1g|HPI#DK@ z%cOpk$yPGiBFdzpOtyxJE6#w5iBo5en?56}E>rx!i){y^!6@9=LQB4X!7nEBXOYo? z=J3lw+ZhFMeQhHDS$^G*DDMPS=y>i3MMTA0B0w<$lv#k{6|<&~88>L+@%DSwesAP{ zq2^?%vx>6-rA#DFf~woN88atNE$2^Ohc-VU*CxxyJU^l9qgJQEs{66i?CQw+b=dkP z=v_&oWPXIY29;+HHW;rqwr@hNhbM(q(1Y1D+Gz(Lxk2^`Fa1721OMr>)< z@0laEC@M}C7cU&qfV}uDe?Hrv&++GT{dti;pXbl#`|}08fdA&b>3YI?C>8!+r&YTkSXql&TF z_fBU9qiG}E+&Frq>*4f~Zf?vR>E_04e?HcqkN4*j{dtZ*SNii@e?HZpPxt5f{(PoC zpEZ&dWDll{Eb3E!T*WN=ach6)zpSbkOUgO>i<8%t2REIo%Xt+{pM(pkYQPeSD0I=WB%<1E*sHrMvevM~zmYaS>9u)lw)fzD=pDV5@Oc zDyC=eH(XeJ;3#ludAgtNp2cMuE*svMCe#BE^1~9h2LILwn$mo+pxN zD%@@uq5aq;lKWFU=*WrVF$Lu90vu$?%OseCjaa%Vs3_*<6*#sNXJj>;R@E>&*+g=tYY1W0GILy3!`W30vm+v}ld`Oiud>Q^535tMtmaf%<@q`- z%W7_wRi3Yf-l{lx7LZ+R$+LlYv2kY3XUi@*YtHEub zvszz6t8Nvuj^H1Jso{SKwKH!G%Ut{US<$z0?N?;AzkyagCRgB(#+=UP+(vX_^P64s z?C@K==67T@zm-rWuJ!TbxzZN&Z& z`cEjaBG48K)ex#BR7a?;P<^4zgticB;1O%_6XF#O8eCP3%Iz_K{SLVy3|&XI19BbN z9>{fM2O!sx9f4d&8VT(r)L5vAM-03*a8a)*Q*!2mZRd7|CRj9@hFM_(?3!iMBEqJn z+3?w@49I1_2awBtPav0lD@8t7?XEd^z<#U%>Z(j#Xumpa~cHXE{nl|HhGBGGV5-@MbpPk zusw2ixGq%8E}xteE|Kg*@#Jy1{p%7)BoCr+;*=>_*UKzyV<;V1bqPV#pQ1rIq5~r^| z8cUP>3o4PEL~)M+hfKANTGnl{8Lsn0athUWyHYfliyj8Ds7WF@nZiN5uVhQ7QrfqC z>dc8VW|U`XkjD(Df;^_tjCr7KvGd430XGxk$rTloW?>Uuv#1lcZOxIuEJ(R+YjaaD z6#D|XYqc$qyH?u)xofpOkh@kp2zB&`1GP7BQ7@a4{%NxXyP0T3d4D{HR{c4+(yDdt z0BD2s_oL`BXX``SWGYrE|NzAxx!Bba)mz%$Q6DPkSqLTp(#RBJ>n3I1unwVLH0f`kvM|V zUSo0B)sDd5WM)Id9E+1D0NLF-d7?-3H-jyw&YEH_t6C=#M^iClX8H7)P-Xc|Br2$x zICTc*K~}Ux@)*j;PaHRStb2K_`#cJ9CUkBwI19)X;%p#Sh;x8kA>8oP(k_u~snE63UMJc0Ld&GR zL9*pSH%hxgvXw$NNxMq2n}t?Ody8bZ3f(4jyU-m#uHtt}wnpeKp}U1LK(56-lHDtG zpU_&N`+;1G2PAt?=pmtpg&qNNEgqHZF`>tWo)CHx$hCM%vZsaC2|Xk9ERbvQoMg`n zy&&|W&`UtB#mkbtBJ`@zYeKIBxfX9o_NLHV(!MR(J3{YD`<`U)3w~oI-cu zw3+NSmuw56ErlA$ZY#;Q7TQK=TiG>~Y&)Utg?5nLj*>MJ+DWLf?3zf{RH&IybJ^`I zSqq_3pI~q1Lk7N3u3T`wF#{T|3Fz3w03c zD7*b6OAGBUbb#zSN!D4Yi%?hDb(5^SP!FM=vO7?+UP1>6^%m*_;zK(58fl2r&J|iDbe_=pK(56Fl3gftkUM+lB5Bx)aE? zT_f3DLU#*ggzgc#7s$1}PqMW__X|BB^q|l~K(6h>l072ysL*3Vj|)8kyS=tZHIgkA=6ZC{b>RiW2}UKe^p=uIHk_ASZY7J5hMU7`1c z-Uo7RKagy_(1$`F34JW|36N|1sbrrCeJ=Ec(3e7A0lBtcOZJV>w?f|ueJ}I_kZb#+ zWIqZ0EcA=euR^~8xwgMc_J`1)LVwBbZ^`}<`d8>b*%jTa{hv@0$VDrbtVF1Wv^6EG zB~)A5I+AT7R9C2;?CMLlsnBN9ZZ6ptLR(7PK(eibwien(Xj>rHqlS`gC$zoL4zk-( zvPMEX2{o2o6UmwiHIufvWIGGBkhWB^U4(X(HYM3^Lc0sK6e5|P5 znknrp$z}^3Bki%09Vc|Wv?oY*qR>e~bA(O?auu(X>=dE7Li1#Is${1Loi22S?B+|h zKt=w6}wgw_H%&-Y9AfY5`|J|x-0LXQYND!a!ddtB%VX`htr zDWRu@*2(S}$(|K@PUv~ry&&0(LN5uuEW1}EdsXN)q1R>ihGcIFy(R72lD#9@yOO;p z^uEvsvRg0Nhe96-eJs0AB>Pn8GojCA_l0C%O7@jxUkiOB^sUf$KyJ*xm+S|jABBFB z-OrN!BJ``!Z$iHVInRGc_NUNaLVwHdAIbg|`cJ56wf28N&T~?-VxbbD8nUY?SuLU3 zLUm-fiDY$!>Iv1C-KLUlCbYTG7P8w?vIat132iOAZ6w=PsG-nyvfEy=9fWoiY9zaz zBx@|xM5w7yGay&V=929!)Iz9KXcr*YVpqvhLc0m=F4PjpwJ4Kp51~DUTFGuN$@Ug% zEwqp9+DNvqP+OsPvTH9{2ceEa`w69iT&DX=c7RYPq0X}FB3W0VZbIFKdH^}kJtaF( zsF%<|vg<8bAECZN{e=1hInM(mJ6LF-&>-0jmh2FrAwolih5@Jb)QlZO)E|=XE zl3giumC)6)yGF9bLQ8~}3SA52GQCc+>xGsH-5|6a$hEjpvK2xrg>DjB1>{=XEZJ(I zTZC?v-EETHE_8>`ow8da*-6ynG=zbuV=>w8IDD;rf!?JrsvPUI* zOtQx%dqT1&C3{M;rzKk_*)u}VO8cB-&kMaE^rGxulI&%nSA<@b-D{G)F7$@9Z%X!- z(Az@q$nIUq-V=IX=mXiUm+V8yK9cNXp--g!RI<+``&_awB>PgbuY|sq_8XyZg}xK| z9>{%u;|Ixpl|de(q%FE7$S)z31akAV zSh5nK8bUQ?S4*L|1ykgG;ovi*e)5b7k<8OXKh zB3W0VZqjy_tcPShB|A{EUXmRo)LYs`s;J zG@;Xl&XC=F$rcEmDeXeZ&JsFX+H)j3SF%NtohRA(l3gHlp|lrCcCpYULYKLY_ZT1p`}9C0=aAYI?1jVS|)UZ&~hNx;zr3<2(1*lNoW<2YjLw= ztA%b6x>e{lAlKq{$?g!kQ)rFQT|lnI-I8U5?h(3I=sqCVVy$HN3q2t1gOWWY^svw) zLXQGDe~(G_xX=^QJ}KE#LQhM(PO@i&o|X1F$(|Q_LE0B3dr9bJp;u)0s${PTy)N{I z?B0~@EupuC-jUtAlD#MNzR(AoR+W!e9 zg^Gb(+!D!Z2-Os-B~%;8wWuT6CPHIu~caxFHMY%`(Fg|-md63De^AlX(zTMKO? zv@MWp(NMDOgtiyjL1;%H*P@YRI|(%wY9hO)k~I@*F0`}kT1ZwZw2RQLvP(&}o6zn; zEoE0G*&afB3bm5mUXtxC)LLjC*|m{uU!k@_?PS+pvJOHWh4zzOTC)9x4iM@jyUvnz z5$Y<`O?KTS>mk%r=s?-^lI$R%-a>t3*H^NBLj8pX$nIdt1_})l8Z2}OkefL}BpWI; zOz2Rd;Xtm%VUmpy8Yy(R&?q3+VzgxCLPtnDMzXO&af5LoCXu|3;;yr%_ux00+}FZ~VQtcuFK!Qrmypm>iGSS`+s>D>>gh zyN!w-}BPQLVdO7UI9absqV3+c~Ns)H|< z>C11+D77i>yxRoFPrgvxZ`PE-6@w;C%>LaDd}p7k(3lq>_Xuho{^0OY<_y8_64e{H4EO+u@LZuW>1_X^;=`MJjC=Verc&Cg4yuz}0CrHLM4}P>A6!vfr+_pHh4UaptTUd9}c_ zc^XRhn|jXxabj@5pJbD~dqGiArMnkAP9+CDh*MOAANhHdQv8HfKl@o1{hq?Z6!)4s zBl}CO>>yY7b-u~O8T?7Is#O7Ly$Y2}>ouStt(Vy#FD?8ypiApTDzno<_Y;ZdDJ@Lv zS&Bo`LhuiubiqFa3WC4KCV9bClXs}h4sJDhi_*g2Z%`Z>Jds@Qn}pQlYp7gW-vR|` zeaQwjc*c?*6&ccwEhGN()yJRqSE@A%7V0hq_i-t?kr=~B(0MBgS2V_1!*OLBhxCPvLLO0!_)dZCaoHDgr0G~|QPrwP zWkFh-P+C~6+7w4rYYX2bB&{8wa%nXJVp_$?ojl@#upOI5CAck>1qp6VX<>p5D2_;Q zN8cnQ!Cj$p3GN0I)UA{aqSD%#%7V0-QCgT*6N)3!O8F)sX|;yRrPT(=)oovoShu~{ zG%CS8sVqpajMBmccc(Za!F_y_kOVtJOg5>TJ0!~NUMu) z5|UP5s9ak8fr7Mpvq4l^y{Ifmt0$#}X?3SKBCUSDNl03ULgmsr3@AuzC>unjbqJLO zX$_*ZFs*|rj!0{`ZxWK$IH+7&6M%xW#;`$DTIEz0q&14t!n8(G9Ff*|-y|fhqoHzX z%>WA0s$hetw5Cv5kk%wh3)7lNaYS0veUp&1PJ+s%buv(p)(LD7mDX`o7Nm6yrG;tD zqBtV0Ilf6qS_`0ZX)Oc_(mI0;qS88z%7V1!QCgVRDHKPfb*66;lGcS#1$*1`X%>~t zA}R}#Ifv5RA9P71&N5-xrVqQTtDp=5UO~gCfR|BO5bzT7o%54SiNr-Fj0m_4O846x z%YlNzU&kgpa!=>5!7HcjiM4+MI{r- zdhcRe%az_Wx6RsY-)O?HToCgfD1(@H(=aOL8Y;tL-eKIUj9iM{Q3-t1=#t{5^d_npSGW;{0QA;|yy)07e{&I|an2_pj5c%Uj^F>qwS z1eFB={|gKFPh7xFvjWzO3%E&Wz}l4NFOD@$7}3LRp$tm8H4URm+JMS}9&Ta2^Gdpz z2_phFfieiV6AhyR?nq@p!0pX>uqXOz^<`5r9e zoS&plBnOzW{m7?Y2M>~Q);$@&5oxA*_i6q%;PFtnX)*`MO_P&>+%%~Ka?|7#AU93s z3e6Kb703<9X_B2TbVh)Z^8>r&0*8_;`LV!}C7(@YLCI%QT2S)oltz^NL~G%$AXV!m z3T+&6s&xXz19Pi|TAdHEdlI@B$kpl+AXlqPfn2RF19G*xT<8j+D}}BSx?1QOp~XT= zgq8|jD|DUE^+L;pZV*~7bfeG;p_M{639S;kS!lJ;Ego?M7Xe3(;5k$ljNn<67L4GT zltzr;1=J19{a3mRO_sY^y@;}k@#ANV%eJ+D5XnI0X8VIcZUi3!vJp%^EZHNHJqqMz z_G3V9d>;pL!sB>Pq9H=*B!{t)_8=r5tah5ixxSLi>Xq6dRHln_b^6$_OJ)ex#F zR7&~8Gz3$+v~6WT*)PoY*qdkOu2q`e1xTSeA3 zuDMAdkPt#>fn7k6WXeLau@e%TD(R|ASGw52380IRWG68=wy_-(*j?824q@rN1X%jQ z(t9sUSvo8%OYb%GrGL-Ny)*YnzWVpnX)v8i$Dz$@3?Wj^asnpIYwTnvas#0NTfl24ihKBX z&P3t5xtMmRolU~5iO0Cz{x;WNrm-fDyJI(0-=0_&B4tl3i;%LH274f74>EfqWltS@ zsZ>#=ES1_@rAjKbk4lwQs-jX=mFiNdZk1ZBQcF~7sY>;z)V?aUpGx(r)H0RoQ>lKH z8c?bIRccVBhE!@;rIxGIh)NxxQY%#IK$+4GLdw2N{0|~!zX+*-bVGwP_>W@@F3Z0i zV{mEyZ3BaA=fBk%TqpkyaX#V|QJVW=gAReMwYJ^GcL-%5xCM5eE#ynFPB|Rk+vapU zQnoprfRw#XIZ=IglKO5XQk!$1;kc8LvW@L8NZH1Aib|cTQm3iZ=_+-GN}Z`vXQ|ZL zDs_%ZovTvksnq!@b%9DZ!5zbH~n>;(@+x?xuy&$MIsm+2wzdFFNeXb%kUB4rN@?;&Lm4DTal4+0+`Wp|Gck+KJY zk5uYomHI@bK2@pDRO)k;TCGxFsMMD#^_5C}?WFiJ;6F$=Y|4N0AICK1%lz9hP5Bc4 zwn0s~S3-AA|ZOnXaUYyBnf@bAWY0NxN#N*Cku&-mI_zjmLaYHgfM zjT^606I5yqm0DA!CaTn0PKvARM_y!|S5P^gzUM!VQP+3;+cE0;hJV{YT?_^CcW00Z zhiSiZLY)qM92hGPm+Rh(!L(llx>hwpInzMdLL6Idgp_TY8zW`g=5(ZlZEBmy)VNKN zvaR$tNZD5UTb0^Or8ZZoEmX>{QZrO4pi)7V3aM0+N^R++xZ0;8-B9gQ_>W`MKAC?z zM(u0!ZyTt6L&2z1`v&~W>azN^!}|Q|vCgO8<7=*6F7r$dX=Ezf@*l^@ybb?$jLci{ zZyU(mA{cctH}fyY$~>EYT_ZExWjo?a+a7j7inl$Ny^TW~$v&U|I7asE`L|iows6^!t2$5e1v{%wN_rulDmUDn{=i8qyW57x)NXT@(dy*|gk^6cSx{tJ%8>NCkW z-`8Z5;$PNi)!7p5jUVjh-v=q#{6!A0Ykqagx+njUYDa_&EaKme(M~7-wt;p^f>G1_ zu*V*JD|^rqj%XxCH~(>r7*&yJy_dhtzil8!FaNDNSUcGE@h=B>SaWwtye*|hoBQ!! z`v+=Q1k3oBXpEk&e0iC>ujS7#U=gveO=%|ipt1+xTU+~oK*}C?|EN-ba#Gx0mm^)T z3N`Nx@gJ!w#DT~D{M#`t($Bwbpo)X|Z(Tf^T9a|=Ok2UftXqa1$iJ)Dubgq*^r+1! zzU6O{P%*XrunV?wQNVJj%PcY-prfTrqEMvAw&u zyFAoglz>?ST@~MS-*0`J`PSTU=TZMD{=@wz`9Jr6r|xO~Rdf!hPu2c8Jt z5O_OqQ{ejGQ-Oa6o(=pf_(I^t;2VK&10MuF3w{{*AoNjSRp{fu+o4YaPlP@VJRkZj zaB9=%fnP(b1BW+#5%_QL%fQQ_uL8G(z7AX+`Yv!{@W|j@p_7BJg;oXc3tb*OC3J1@ z$k0c@n?j!i9}RsG{4{iU=!DRPq3=UigsyA4KJ@R<>BZ0+O|OTpY8%J>2wD=(eUqnl5NMrs?#iW1H@1I=Sibrt_NaZ@ReY!KPJBFEm}!^!KJ) zn%--=yXl>#e>A<+^lH;bP5)_ntLe3-51K~*0@aRNZ+-ua;Ov3n<%dnaX!5Gb*G*nM z`HRV4PyS}|sQ(cEVNl8u{-gXy`;YM-2lcG*cr#qSUKaA8K=)UW5!uC&Yp43jB{t4j|N+XCc9$B4Ktpd@yd+1W~`p^ z-x)v7_;tn+fujS*1da_H7dSp}Lg2)}Nr5v0X9vy+oEJDhaA9Co;L^ZlfxiYW4_q0z zDsXk+n!w)z*P+pG2;7J!zZnK_XW*{DJ%M`z_XX|`JQ#Q=@JQg%z+-{O15XD28F(u2 z3=HD=zzczw0x!cjUJbkvcoW9*4ou_2z(;|P1D^yw4SW{(Jg_?OMc~W8SAnl#Hs1xl z5BwPTIq+-Xu;39ehNFYW29FP(7+e`VIe1#|jNqBUvxDaaFAQEBTot@D_}Ad&!E1uo z2ConPJ$PgArr^!NTZ6X+?+D%*ygPVL@V?*!!3Tp61s@4M8hj%7WbmKCr-Dxhp9ww} zd_MSM@L$1Kg0BW&555_EJNRz!{oseekAj~BKMQ^yTpj!(_}}0U!5@P^1%D3y8XOHB z5;`<=7)IyrPo=+w|@p)*2fh0Y0`7rFq3xhix?=+e+-q03>Q zSBI_%T^qVCbbaWC&`qIRLbrx)3*8>NBXn2j?$AA<`$G4J9tb@cdMNa8=uw#Q6QO^G zo(??|dOq|*=*7^>FzweuuZP|Yy&ZZtgl-i2IP_`gv(W0$*P(Ah-=PEi82TynYiJY( zet6T7O-IAXk8L`>>BOd$F!NJk@Mkui-E=O@{eq^8VDPJ8?3XoN-gITt)lJtnT?fOz zvFTj648t`f zA71wc%tiIt`1luV|Gs(7oH>5?uX+CLwwBh}&9htF?|7pF7rac_3F{&K_QOJBaqxcZzIZw_qPaev3Fns5EdYx?+aoBdnEM#cW43g_Q& zb#GU%&b6o76>yZ!ai;;p-_J+?!oI0tQBggg}G%x-Qg>ix@> zE${0YKCsxS7Z>#R_YM_}4kVlB&T46!HD@*&x>)JyE2jE~h8MNY6BBN=WmZ>jZ@|9+ zB%3*W;6Qg59+aH9n9t=;efHozV`lF9nO#oQawabiR+knd5qx4ccm9oHMo;%G?w?il z&FtzQ^3B|{$2W7KZ;o%~P**Qrjos~=Sy+PqhVfse#Wypa0>)V2o0;sue+T+zCVGYo zm35xmo5R5Q-}KIPFse=eosWNxPQa=X|86Tj zx3j;SXn!|4EdHIg|K_l&g*|;;{Ra&Bvv|#6v3Yhe-B;~h-qnrdtl6_#T4vA2zs2R% z!Qo=HA0y-7FmwY8D^>gZ7WXWfwbVD2z4Fw`KfGdQew@_x%?_b$UwLoZ!2d4e14Pau z%X`fEJL=ZjKWp3nXO{^NUVOl`{{LB)Zcg`I^y7oO{3*Wrqs+T)|9R@iO{V?W`9G^Q z?*u}oH(t8*u-*Fp(lUSDz*~K%E&6rZevAHRIXU`U*1fDcaA0XjWIDbWeBgphg63H} z{_cv-Rp0GD?dShprqJDBPoLc$o1fA3z#(7ncKFXbC9k~ZvPs`h>-nGMNwT_N#gr3T zb|}ob_2KCq5BwwfTkI!_O}p+|(!-_MEva-mnM`G(;qLvzzC+jWjc4O7ycFA{(KGmM z0GLz9x!6QDl~0&@BHY*Qjh*0P<9afkNya1Lr9HC=2r7ELB&Ml{^p?~Pr{#hUSS zAzMgA!pnNRv6EbECLc*9v(aRDpw}C_j*Csi^O0yemJN?Ikat}d8!bfjNH&=Zk5s+$ zUC+gudOVRdGP&^52J)`&Vu6gt3K=8Z+dzg5U2GzeHIngcHoT-kTWsuNvye8O$c1}{ zy~W+cg(g#pcq)fn8$f^KLK7J?lg`DFZ3785bFt}2A(o9LqTzCbme|6@#&Q`wTF9ls zeIwrDUaPQk3b8^Wo+!k^yUuN`IOy@V{hsaE?{zLZ8i_^{@kk!%xl6s#e|OQjd^T5z z!PlGcQ|KG$9dVAHCk3Bi3x19x_^k>)Cz^?5 zv-xBO@YV)`-|nKJza-iw1@znog5OEdX+51x<+uu48VG*3LboInS%|IcKufXf#*2Gh zaK?;hvPL!yu#~zEe7_5hB~xZH72`Qeq3gg85^&5kU{PFuQsx@)v>!VE_jCIHb-Bam z$|u$w|NYRpiLG9n_SN0@AF}8S&39W#4ybcd1ymy*4G)z2q#5{|e51k~HQ((nP|xVu zY!Ve-UY5h&c!In`A&qd_%%xJyDa@o{ zQ-&K+?jn@Dnbq||G9Mo9#u{NxOM_DGCX`q@5shX|BfPAuTE*dA1Ij&$(w0wVV@AQu zgE3ScB>1&?MQ*n%a<9VY!ns^56Dwqs;jYROR341kPSq!I#vL}}KEg0CMHQkL8vBR3 zt2Jd%#{G(s563dOcsiNO^D;)9s<$|$tiwyW(=O!!#WBK$Zbpq*BEmV9k-^!dDzr@= zB$P}xAB~s^htb@C@epC8%~&R>W9YUEY1AYS6G}XuOyr_w!J*7)P|72OlE@?@>1bT2 z7*(0ufbuAzWb~Mk&@u4Zf^FY`@()6Z#DWe&E=njVdT=0OeCQi zpSC{bJViM1d^BFrP1*X*wD~FLX~Ib-~;DRBN=Cy+A0r9C{2i z=TNB9DCI>$Nkw2}gs$3`~gP#X1_e-jEu@Jy~+G)=Hgft8g@?uhZ+Foyg@k0 zNYsoalXi~=hgtyTyh%7I=pd5J+rtJp)C4H!EyBqqv?WsgqaP#d6}w-v_->+x*T zh$n^K4rn~lyhA7j)67OwhEN+QRBP1I-X#<)M+?bBQfLhnsx(S@k5ICDOwT0^p)^pa z&M4)5Ldlu26jqx;XP{7(QOXB|l8PsDi9}wg3>2y{O8JmbOx-l~R7#9Zpfu_=9}!9{ zlZ~12ychyOY1C^zCKMxWCgRD6ETvJe`Ginn*-QotXl~6Yq*15&R59{lBbvxXG6^we zfYPwjd`39gNGgvW?Ud56&wNfOX(JQE7EyF(UJPx1YL}}CC!R9QRL&Hm2ItWBr<^Yc z2bU^W$xi#8R!YK@4L zH&O9&VLfZ;SahYs)uEy88V21yuB8}lW-b;fq+-$V$UsjQSAyI+QYEad@YvF33-P=W ziHApUGE~E$B}`I`wp0o}nq0;V4^@Y2B%&ouR`^^vozJ1)7=$2Yq9v@O7;On7lE7x( zP$ft_En$j_k0+v7{6_N%KgZcFQ~bIv9$v*5{59Ed`TtUbsV+WcCJKC{RCq6W)^qX6 zWIT~b8)=32l4qKWPvxN^tahpc0P$V$6p#E1F2h z;^Czte~F&RjrH!S!dG+wqN1Yk-1aJrz?DG1{+8?`3zK5xLc&?H2Y0lcsh?}O2Mh>z-8_f zzNrh(q!XE#iM_^BoKTRyLgBx0;qhD{i$!yIsohLovi#OXN6owr7fV5E#!HsX6ud2? zV{4U*B*VkQm73iswSvtRJ{OLs;X+QDE?&w*Rk?*CwB?}qR2o|mS%AdT0{kvM8-Y(h zgEff6%L-8Z3>Tlk_-m#y{Bk^9u~2+K;d9}vZYCpH7=t26iD(UiiqVFFCyEA$D1yY( z5<&_OvrnXTGXsfgx)n9#CWUTI$0He|kVWn`T4qj-VM_&{k3l4n!bI)BC7Ncwm5at| z9>Z)j>Y$}6DSB&#ZqxOgo=w3oIl@+k!L8-;I8#Bm6f$AB|p%PxhXqW@08G3J|b z0}jJ*7YteSLP?;C-&PS?^XTNfUxkMThPXJ=-%In~PQlx7SP?52MqI&V_Eh|t3g2qx zp_?qc{!aE1PP3oo!V7WJEbz6y1DDFA@ZT%={8$Fvq=4zCcK)QQpRLfX80d8vaY3TJ zWNB9L`B7arV)=;Sz$Kby-r}NjF{}pRbhIUra#Qde1)i5NBGDXH!l))xF8$1F@^SUv zsbb8Y>w@9>&ZhG^238K1?L)!ayWnggmdY34$rNBIGX>96;O&igI)#(10@rr8JTO~> zOL3nq#e9XG3(esiA!dgA4ywxYvI!h2j*&E9s|(HQyaT1N9xC@NcBX3zZBx*;Xk3rx z;)Q6qx*XvPeZxu$YEC;Sd}}J3FJLp6;t~&*dIsfLGPRE#U3k6_%i-J^s|OA*SL9(M zh419T<8aPqVN*7Id7nJ;q41qucudEbl9OF$agUcUyD0eFXe^SB$1{cS;(_X*hgx=Z zp{8Caq|h#lA+`rHtdMO{xFC~QwT8Q#9wUv3Dlnq(^9x2Uk}$E@wU^NnP3<(Q&{*FU zQbs-(jfHy_4>cZ6bj4`HVk8pF!v4x2P=7U*C#LY2>S9JDS%~1oRuZJq(g7>37;SL` z2cRS86hY!?2?-aUfWIw~MqiT!$i7MONf)2RbW}bJ^nQRv8cPQUROTj6+pwLDbOKTkUC-N}- z?iJOV>5J~#OhuWWPbM;vbioKOF4NhI7O8JwEtlF{(e0UIxKr$(^5!p~0{>3l4L4eda~ zigqe=YbqHtV+LHN1IxsUNA`1C(S-_bhK)=-mrlep9FI}B&))e;*1CM0zkjNjm=+P1 znT$oF*v3khz3=s6?V(uta4MQIb4eV63@qy(8LH*b?f;&NlMBc4Fr=8C2FKYe%Tj0` z+e+;OLsFr`-f)MfV5~<)SRA1WU0BVFVS$b2)fT z1goy7DO__8*qYm$ka*-tB!zA5z_R5--I)1kNt9GlB*>SAw-G1jAmIpHHj-QrQ2F*D zEF1$MbOkH1t)7fy59PqUIzX4gw-&OAOfH&CNW6s8?7LmK8H?-bh#r@4*&Qi-v4Xdm**wnK zW07!KisRvDSfcQ`u#ro|Z~$ny1St@;$fb(WmXG4FL^orKAn~-r_qcc?U5IC5IbGpp z4JdwJg>Ow@2bD@;RvD?(j1aWK`zd%Ej^Xqa_gqW3mpHu&-wN-Wp~o>TI(P}E*)Mb9 z$w)4RrGO#fQg{mQQ}Fo(4C0AA#-G7u)O6@b+wY8yj6qEPgJi_Yg_1%&bB z9JG{#qW4#56G!fdYB17CJQ09Swqn?JoO$)KLB+y)s*r&zG={_dTAGw?Djx_O=i!jz znPD@PF|uYH4kB8bWYOL^tXOSE-o$|bntIrA>&cOgn#OV$Z<E*`Nt zn6%N>GJmNvia$W%jc_cXXEG*taBzVJ`x^|lD-@+IA1@$+0Bagqgj6ss;y{JxzRaj@ zCQLL--|*tW{YeS5za69)2xf|4z{sVtoH2qc0YH)UrZd1F2*t!w!b~E35S0DkKmqpCQZlJr!j zkU>ZkCyh8Id6AA#BohmjjGm9c)Vg2!i7SnkcYpKvy=j*Sx{Y^ph#voQ800Q zlNP#gNnX`DQL$ivxqM8=%x@Rf*Z@yb95hu@&*ribVN24KX3K)8cq<7>$ATP7l894K z|t&=skr0qHbCf6k1mc-Ady-GTrkdo1SBAYS!(%h~S zKb!O-ok2)hz7azO%9Q*G!FqvMwMjXg!|Cg570NtDvk42@6IW#Uh#S za-FiMSy0wRgoXZ*kELP>mqqP@vMwepm~AGG1%=C^hCx}Y2n#&~L9cK*D+#G(P}U`c zh1ji_jy~+NsA*8vrG%BvV_3%)%w#3SlFeF2s2BCHK25?&+=ZywKV4?}~(# zD*ONiIG}_wgyW@AQ8y440weVpLcLv9BO|<#u*@7b9^CuN6)(zaWP~>nRxFZ7OdZ^w ziq*&nZze2+m71X0iWg-yGQ(R43jwULR5oTevS2kb!&?app{1z^+^4RDjm+>i!a_Je z4jW{cngNKJ%X`_)D-a%NIXdHfTY%3M3ks02pSbS$)Fw*HL*6xZ{ zGkwvW^<9*wCoo{cQ9yXqJ}B>Q%FD(g5yV3i1F4z9DDNK1OCqcV`*LC;BI-&GrIdFs z<)spdi~$z~k&{{p<=sblhzd_cBY2v^)eE%~%DbQPV(CmY$&UwI9<>z8dw}xbP{vUZ zZN6q|E0p&j<>{GRggZvu;;6Au+C!9PWQ|m-lLS4fhrNlLYl8;R-?RsP#)G2aXf=bny+SFqrAr`FCNcD^9Z9S z^=o7^m<4#35i!IW{Z)Pn z<4~x}>Lo?Vg%bvz`4*4)4OZ<703?GJ@-Mu~3; z^XT5Iiqn>fqzs%rBQR*NIxHe8JGD8RULC+re*IaxonvY?*CGgcM zk%wB<>n&D7+EQWaDWp0#l*_gXL;BoVy;4{-&a|;_;Cb_QG)M z4p#RkB~ZhCOTpW)IWHtIZ*urZ55dzKyshv!AdZ=t1mbdRLJuzA@ifDC2qm7#r&AG} z`HC`zXgg5LeOFQ7LCN8nmNWvc1!Vy7xuhIwRqrWMTQq~y*#u^P&gmj}T9x+|J|D*O zmIfZ5u;uC+D$@p}2K52qn1ysanS~of6oTi6Nja4Bq2i#g<9Je!;sH8vhPwCf#*;lx z8`5t05n-5VJamUOkjs$68)bY<7}!te5y&Ad-7cfWql`}!BOgxWFn&VEP8ox^$!$d1 z7Olyriqi(4bP^3?caQG<5!UI^Jw8+Td>Ag72>fTlSolE>PPLV_&@w(J97H(bEDAB! z&=&Wd^>(@XqMX%)gD`6>h!F=wI8tMj^9A8#qIj%FM_e4?NS#s6mxPl>1b`9aar3Th z@??f`zET`K3Ta@eo`{GpjQVhUk;S^aLO8JIR5HN$FEV~~& zrO3)q%D05V<5l7Q7ZZv@k#(Vz?-Zp?kEUWKo>Fq;a@&RWu>ZRFSQ^81+>}j;Cwe^W z<$D(&jlsXeF9xvdjc3z5@ISctYywY<{g=Xe;C zA1F%3d=JJr!iXXEF&?qI)1VmPy>vC6Fm#+Tq@s4GwHaQznm`!IXfDHNL@t%h@Y2;9 zgpq>FKc9qmQZc-AwI*TUc?yi!I2lz8FI`O}jCdB|J~#$)8D6?ti!k7`$Nd_3o>G<3 z>Y?4W2_qlJ13Q_RuwA?6Z61tCih=W5Om1d6FUEJ9(JVU%9T6rI3ic+Zfx|#otY+Cm zC}kZ&$r(94lTDDCG|OhElqrOQRZ1qCi;}7|%XX)fbqNJm2c={Ays%%VF0$b%Wh$YV zh}eo4c=krAxLLM5rL0FNc(w$03gBTHmm-^u*XZW;BOL zLwEyRidXCZhEU*;Oc!v`5TSUr{%;Azh`}l&xDLoI#jEu$=>>u*jd ziF^csYW70S(U@23Z$T(&P;?_l1e@d4`hG&mKrkE)km}FzYW*3C(gv@zo{8geIMg0X zdOWV{j7W6G4!C&C*BB`fn=3!;g|kMsP)t%wJj*#c$=}@c>Rb28X)BOLL<5tzA5B z+Crm=9xKF=rbOY}xbP@k4v3HvmIOS)!#&jhI~SiQU~;yn0|EEa{4zTgzf%&)xj$L$U0(9l2?w}HwQpo4M?p&&3ECWo*i zVL^f-TY*yM5K4{@Wc=m@mm<3XrOYLiEFUgY_ENzSOtuB3Y)>e7I>LzV;?I-FYTZB^P6AEIJupvl^`PC6jHVUP*5(*x<*5kVETXHC}T_~kZQRXM| zi2`nP6NL=mK})AoOyoW#=K;j+@NxGMT6hs)NZ z@SR*Zzs=3GH?kZp8;+uPcF}kM5~tMmUYWyXqfz)SE<9moV>qG~QyhoO2BYv@T{y1e zNW)nrMn?{pjYZ*M7oN;#uy3_j+8iz$iozo<98n5|bk1I8bGU3I3Xi&Q+>VokYQ)-< z!{ro6;kpY)q;?+nHi~}3;d1(;@R)+PVfHg35k&03nmJspd+A6Tck!6|;3UU6wZzM2 zrTB!4$89Ltq>kHdBwjWw#V1`nz|jPMOhV#i%Tj#G#TRg|mysxlp-adwo0j6!F5Zmb zK99KVm=So{wiKUn@o5Aqrw~LT#3>`7$z$Tky6|WeXQ8;|PvO1PlXLNSUObQIJVXyH za4%XO=g|@`t)JpMTzno+6XEdA z>A8?cnm@%aPK1%2$1f0a@@Z7#*(vV5* z`Y2-|VIYVB)4jd$6|JT=eU!0?Fj6@jQ{(YlS1Q@il(7e4B(W7Wc$kXRtlIKX#-57N zme1fQDT0tT5V}S%RCslTyj6$B;ISJuv|P`mYHN_4Vos`?&Zt;!W{hE#kQFy_{)mBm*FZJ)M@bICc+eh)R8kfJ?(?vP}?J)ZhMg|YN zqVtPQoXwC;KpDM+fot9JsRC|uR%OUWpp0dNfoF%3aTD?UiXoeUGWrOkpeIx4%eF6D z)I)Xz%IGHyekN7GX`EYzYzoR4AdEc1LvlGp4=br;Yf#4igaO53EuIjoMO#<0Jt$*P zF$_GGz#}kiAH>MAng*fE-629r;ZP=@uze5?MYaf~3=;~Dw{e@B?N4zivPmdqIicXu zDFYf4jp$Hhn^4LKp`b-{T)V;54bSSb>C}jnq#1Os_$3~2l zB3p%04kQ$vpWo=Vo69LhHVdU3q$s#HG|v5^cC+w?q{lw=r05TXW8}H})ovHbkqtvR ze^eYEYL3ew@N}JLnqJk$9#Z(|~aq^%Xq9}Ow2OE4`h>;EVRI8=R zK+V(QRAq+}P7Jq9;(2#da_BSilyjKk;MBW-qhfv{$IBV0c|wlX=5R%U1>g~F#PjQd z!kdLek~r+*W~0;OxffSu!}#-A8pz1AC68JUnF( z!=<~TD4WKk2Bm>g+HsVIjXAt+xZ0VE=<=kPly|)16~cH%5;GJIxh5)YM?s-UEm zgp|gEcP7pl6p2U5dXY{hBwU4-OXC(Dht%A#PJbb!4BjHZ57+D}H8-r%DTIRU-f)S06P#Q_%b@C#eMMxQ3TnX2MB-zd6MLL_1 z5^(!uBe-G0F3D~uFVZ=Lge8K3`B*BVS=@T*MLL&|@WPA;Zq|`1x7*2!be@wMhBPk6(t{r=N?yvQl;PgrX<-9ou*y*QW3oS1-z62?a5Cs6XB?VpDj0s~6>RLP^4rshhZ>$ENVmRxipG zgp$c*BN^Q0?NE4Bs~6=;LP;Q|6+yzX6dus(MY&2*aFK5$i3?q@z_bMuq4JVLP4jBP z$;HfkR+k1N?j-f1Ttg^0r^gjGY1x({Lf(sWE#csaAq1&nh2@Aw4S|FvcR4uaP!pi#T(3BVa0~&iIfUUO47k$Uv#duvw&FEu{auj| z*8(pTq7Qh;c*VZMP%`L#=?2AUOW~;`bO0XQToHqY#M5=`jV>NnB}Y;)GvFJ)#NsA} z$5Zkt1SRL9Jow!qNM%upZdQyoJZXYaRz%s`1c|2--Jp)Am zl`ybUG4m1e{MJyRcm7ugmX&(?5wz(%sx8-f)A+H?gHy#- zIj_6SD6W;j)(;PShKJ^qb`9wXJmX#SkN6*Fzp&Hh44En<}3++)#o$Y7hh0 zGf*CC>2B^B@^FQ}rSP~o2bW7^lQ?u0gkHj+&Goiov>^(mVB(He+!>1?XM(2&@s7gd zjwIalhLak+ajCbvMae^tuikahc!yFviii0GdX6XhJ%yf^is$ugoL?eRCW5TVRqR}o z_r42G;;jdf93Dmn*p-8VKXAeM0&ZnB;86hB6@!95RN&TZ3YRb7Vc2kasHckvLQiu( zQtBqf_EzzsZ7reaf#eC(nN@O|gu0}~o?+moU{anXE(j*C!vC28AG^rtQwvpOy@ z#Q7yhyE>uh&s=mu=f@y8K<8*zDHQ#=LgUeSxP8;`RoaF!)J(0B_Mg>?(~38$AtEz| zyDZB!;!{O_q2TkQ$t>a#`0QsJyJPB9pf44=6&F`W^J&N--_h2m*j3_W<5fSb3ID~0~oh2mXwa5`fP%#GUv`n`hA!`0%kB%H#IX**!r z4}MT!C;=DoN3d}hhV4vQNJFK;sA&x3FjOc(xkYmO&4(#}jNC*90Rng=6P+!6J2aFn~0!txM8!o zd$yOnYq{8H3Kvx2R9|4d@?BeD=VkDUfOryXYcUSVjA>&`a>4vnN7z(x1!K^XIaBat z7mSe{-Z#ua9IQm9;B{PZ0mBvCsJuA<_R4u(1>QcF(s5Ne!oT{5miEf4MyX9qb+HB9 z(1_Jaj$?<0J=$(Pg`E?}ljSBJ;NVyXIi8Ox&YR(;DdhHuJ;T!u=+J!)Bv{|Y>QN(w zM}Z0)>nXto3Off=8tyR1GlRf-NU)(oZjUQ4viS`6#x#&%BNq!3)3G1IHl=|C8!PM_ z?1Au{3~Ulu4+*9#WJ?@DEO3Nm!>S3!ab=0Ol4`z9Tp;(2#tj?`soGQErYHW12{jSH3#6)~R@DB33Og6~xWMy-TLr3awWtD`6co#^93J4o-RwP>dX{@G zF}GCc?GfD@%_6eLMmqviA+}Q3xhD4f{B4lD6};;9I|W6kDJ~4qaRpCrS8wxv-Q5FD z&U6vItqV_NO$1)196X+ETIPY@&c&y7_&xC~g2=z6LH;vce4f9gF^jioad}!AO+z^$( zFXrI*2Kl$Rcm%%cm};=M1HO@d=D2vgkVLny@Zk6c`OkInxVy4|*JNOW3Vb8|Z13U` z30kl(`{4Kn`OkClIXE$+n5hSbh8wD9z6(zzVmJ^$P@up!$iCIZV+WCdf#R8GKs)KuUbl-3lk56U1|1aH?C@1>DD1iD#EDR?f73%}ttz|Ij(Qp=!?l2(j1 z#318c0$31Mdu#Dj!5M|0k9jMej^p|O94-^_sYzuOy3I`B-LjaD;x(~0EZ4%Re)0<5h6dvg_Ta4#)q{Gvi2PKbg2Ll* zeq6ktiSh+SS7~5z&0!mDWRpj-JpF zd51g798L@LEE}G3Itd5Y_#3#BN9dW$#$DcCoP~sgR~I6H5~0aXIsDMWi?fJw3>>QC zGAU4chRQYVNk!X(Pz(fBAZ%2qfO8tDU{At906oGzFb_NBG*ZD{gaa=N&i)YN=x`dT zph!5lxCh=DxQrc6BNbSLgZUfpJjAxg;c&0Nm)iDL9ANSG#*~ihSUIU&o;SCyFVIu_ z66F;PJ!j%x0m7sDqr81657*V>vZaJ=-YBoGS5RJ=@^B|1-UosBb4O0_8kJX}ybPX4 zNa1Bdl2_NIXn9r2<9DKDb9Mu8y@1!Kye^j)4dXpK;xxe#v)&fh<6A4?*4BL8lxLWD z*owaznGk7#l(?7@@m_Ph8Jve**bP`e08ru*O2pHw83S?Cl-Q`mrId(QbKqWqoai@P zHM~UH4`_)!ir9uoFv8BaMX&J zQOxl&q@Gq_xr;`aT`Hc!o3oKQ&@!N&qDK_EHG_Z#ekG}cR?+lSlmlFNn!mUW&P)lH zqb7x~aN&4^2JR}hpZkL>Dv+MS4|L(V7~E}f`>8?>mkmqd2Pyb`e)xoI62!wBfXim0 zHT{E&#>?;U*dHA8wqB&<6#YjRjVlmwoM4CeA#Z7t6#XX`ZD56f*KUefa-gN$6n(IZ z#@kczw0l-W90DyvM=AQxE*iHf>$q!NL{0)Nqedxu)J5a`8y8=|onY5e28>elAuc+L z2Ym4!5)s3XyytuDcMetPRybpE`zK-_khj=eIB?oLhbj1c9ATz$SEEqMK-Z8oaw^K< z3XS8(INrVlFDK8vt9zupc(H6y+V74a3?1&k0vx|CLpCa99H|)d@@d@s6~VF$MPP5_ zh)*4~M=5Y2tQ)v?1aFYyXm?xWkZ45B(Tar812164efT1VoY!KoDxHc{rehSNRnHcZ z2nx5u?D>-4L#f9qIQ9p*Opd>S!l^XBhtXls0*+IRR>VW&$xOT^64l^W?n`r{t#-T% zj}>rrCGPK&aA|K8eu4|fyP!?HRZa9kp1U+S3O~_><5kNDIuL!3qou)7^hqw7zcd|p zPY7e?aA^<}zS4!mHCDi7n4)<(Tv`K#pX|c%PL-I>4=xfq|Zy<;c2x1?ap==xoA5L`ecqrtlcSYDutYS(J5-V&V1MSzH@X;9DiI1_uVo zx{B^e&m|ND`K0m871n(`3{PzKrJgC}JVik)HC~R6CxN-*mX^93NBf;mIC#4gymENh zRd8&djVy<1?gGWZC=fAmX9}im9$Hi57NMiSg@l2L6|a=R9YlyHYRp)r7%&19fxt!a zUU2xThF6fK5S8l^#c9*ixR@k{SJq>CXy~iDRN?V@3$!DiXGSd!=;`CPBg$?<6?~Z@ zw5IuRiKoK2A&W9RM$5k{_&kG8oj85va0ujp>41N^0^<<{y#Ecaali%vCeqzsYmIck zzk-lr7{2*Tr%2QoDd|c@LMXfrClvxT1gWd$6-cz=S1AhOJ8_**p1%T@3pcc+ryJxWmz#zBIVeyc=)Y!20te-%T0X+*c~~_E+&flcC|Rp8nFnAYN^?xYR!|+|%DT z>IBQZO+!;f=!9naE3~?tP?rwKN>!M z530-D9Lz;E%z--QNu1d`9v>4ycbVIOInyuXv};#e;7U$gH60)OuB~V*HfJF}n-Zq9 zdPz^_#FkC*p-=MpHnHpI5GTw)c|(0;6|*fA^A}E>zcoGr>-l_Ja^eK8oM%wt2DL<5 z=GLH|!l}kK_;?A_tvGcJPW=?rl%UEYt3*4z&{H{c(suZ`cYU8PR8#0aHB47MoOc@M zy)zRZUvJ>^Z76swHG@sr7bMhCmglmX!8)C@uAhaE6F2nvHsGxBY#*?WuPKUFj~8|Z zr>)V9kM}mBLcWITT~foOjnA29a^~wT_}COp=~nLtFmDyi>R3re-SF`Mn7^%IZqmfN)R>;HgLVO@_3wp`wO}}IPy8Xorff%Pv^-9{kQ09?;^VCv z;)EtPWmih1O~Hv5apDPk6f<>8$VpiB zVy@!6j$wR!3!dBaIqwV38|oXQmki3gg!2|1ijNm|rXBw-@P48^HID89)}@@)cNjj7 z-9`1KFF;vyE1xQ~5$3ToyB5gBHyn++2JsKa^MJVw-5Q~B+wMdIJ!Mu_) zk2)3~??mY+_%fJ(7EE0JD<(pBRO$flD$d*e1bloJqaBv(Wn~SI%F3BnbLKiH;p6H! zWpY{1tYxZ}D1vtl=WV(YA6q7TzA3yVG`4apHs#Wq3ev%vtL9oxdx+Ea11%I5X!xYXR*Pp z_*l3HFBih1+`W)Rbt$Tb$Ay>fN9NvxLAjYz9^#b0ff5k98uv>lYhI+8i!hUxe35x` z^W|mTUFl`Zj53!RRqhyu4KER8`#^mb8QsD&TJ#@*b>-s!}eicQ(ytNg`-{mUE)j?^Y# zRplFf9$DSSv%2MJeC%5G`F2{$C159(*pv~kOoTpACrC3vNb@4HxSeOw{VYEIfh^YJ zmC$@st}XeN5BGD)j~+K}A}{W7VDI4AA34@n@%gesaxFhyNd6~LV#k3)?cGc2m3HWw z6OaX(8hPBw^Z5Jo__z#tjIPgw&}-b>IpO0@c5P|GttIWwvi5peo9O#t4!m0(rS^ET z)I7&G`U==bGOS$J^-c6m*&B^ymsZmA3pz{sf?O${o85xGK9w ze0IBU^fj5w{rW`T+x#~tmvpR@?ufL{MJ~<0(Klo!8{Eq?*^v~7r|w^+@i-Dn zBn9sKy3aSsH_uX;cJj_Oglck`@Hf%-#a{SP*GsttzR}aAD3icCa(bymy6Heae=F`F z=dNpWC;1Nf|AI{PCEc=1xaBF@*}lD9AElJ-Mn!!HuFw%%(7s?%9d1*ByPMz=W(V}A zGMe!U&*)78Fe2&px?H9{#6hnRkcmjF`~r@nn)~2Yj{C5-Ie5Dz+PRWxgKT#%haOF` z>@?Fco*`{}-y0lt>hB}%#=N=0gch}89V0dV6n-2xSD9A}sLH&itQVL2cvY8?vUyW?w&R&WVRFjU_ZAJYhzk&lmO9XN-;sti1v%_i zTS>FMpz{VGRxnl6AXi%wI;R*xVBD&t1)`*PYpaT4&9RmBi^~3%>tBvwda9HY4M8=$ z&wIRiDKm#(G2`GulncO_-XxGb}Zf*Y1dOEhhIbvK>|x-)J>1I z)9}N*s6$E37q*~9RL$?guR5udJNmc6O6V9ih|zzd@3S#&$1T;dC{@8W(Rd$>!N$fy zw-L~@I5by2uz&e*sWVqGKw1RU< z{jLUi5vd>AqGJ!dL=?@TT5PFku`BCP9ePL2Q1_)k?Lt&;#5#0mxKepd6BcgO=GB?5 z8-+BH*9IgnKDfp^(=pPU8I>$iqv%bMIYH>3~){zt}1YA zlM?OGYI`D8zYzUBg28==_QXhwoc<|qwhrE`7*p~cFkUsNtchO^;J=vd38RE}yyaRt z7PK3_(GO&kP6Fb>T9asjYLrRv9ImO=aYu)#r!kL_c0Epr`dBRvuM1nyjtZ$3YZv{x zi&V%SChI4}jnJ~1FH{NPz@*%RrOVN4_{NW)JvzfT`XS_=x@K2#+~OizQe;butf``H zS<$wtV3~JeZTXmy^mbUND*s|30-q5^)j8GpteQUh+FmI=0 z>44dS<%pUQ9>TA$)=DJiLadXN&2|fEHYKG&*L;}@k<}#d2*$5TzERQ9I}l{kt+orF zLKggCtwnO^j7GSqRLMS}`{wY5XVx z!>D9$VCZD!dz!0t8i66V$nFbL9Sb50c83M2e)X-$(Bz86)LN*STKOO_$sPCSK#ywJ z_v5!SN&b$l%pvtXb~P7bYoZn2EHKe_yzj8KRThd?xt`=_*NJAwzU0|$Nicj+YB!xB zN!4gCF(iFMigir1eiS@Z80jEw4@~81=(+}_^^nr+iF`gJr<&eH7-m=v%6vuHQoEw; zn&jJc`cTh7-FzPv^zmAJ>~v-`M>_Ka{BTgM*lD8!cbC%%ek)-_3!L^!ccgL{w$);2 zEoAYP^qRnK)IhNgei&C{$r#Vu zSiy->F$EE2oM&WP?C{ZcCH zdN>ZRtIfh$ThkU>CECBE78lulQQbyowtyuGOpWs`Ep;Qxh!|0JBDGu)kL&GlX4Ljy z-%73xjpBq)r5T-E4Jn(8f`4+i*v+sOH59Ig3~nPC2$w<6;QnMNoG#|p^9g9dg6NoO z#P=qb9_O{SJQI(2wZ9Q4 zI<;fvw8G~IE1F1f$PVjIkG) z+(yr(k~x-4XGPzA9QF7t*Q2~}PYiOZ{rI+MQr&dK7gl^-K=Vlo13sC^4AnYrGK#xG zsP=Fo73|Ukv@X9(gkAoDSkA&`3`9zc(V(3GjBA+fF@Tg}!kY!Hbo?nqqMJ1U}g{GCAE-a(!J zHwaCfM}OW$lZy_GMZ7s;qro*1jog-R^>nWC2wMz7@*&nk!?IU5b;#MHVTt zXp!kf7AvxNktK>OS!AgqOBY$D$g)MIRkU#xZG1(WP|?%fS0zm$2ecVUPy?sZ3U4F zgM>Y{(F`|6drb1}Y0IP>Kzy-@zlpv#h(M-M=)}&LZ%C-&eI=ZQ6A6$P6l;enmBLG+ z)!!%WVxQdMyrKT!Zfnst-_h*c6`N|C!$s}RC)Tp4nI5pd4D+2*3B{s_GU@3aB$hjh z{7E0p6({G5tWacTk?mGw?M2p6WDAOH_af^ovV}#qsL1vxvUMxk)QYxVMVnU9)~{$A zRJ08%+C~*^5(FPw8;KZWRDfu<3;vFkv&;t z|17enitOnkd#1>qEwbl|?D-;lp~zk=vX_eNUq$wEk-bu6|1Ppui|ju|_F9p>USw|+ z*_%c7R*}73WbYK&yG8b1k-cAJ9~9Y#MfOpVeOzRp6xpXm_F0jAUSwYu**8V@ZIOLf zWdAL)?~Ck*BKxt(ek!t`i|m&o`?bh?7GoCEEH=(!<1IG9Vry7zO^Z#m*jg4_+hUU} zHrZn9SZs>L*0tDFi>+s|X%<`GVjEa&LyK)>v5hS@-C~Rz=&pqLnJzJ{7H8(JB?KTG6^HT6aZTT+xhgG!0E7}ni?Z}FDR7E?wq8(Gwj;(0NRkY(P+6fiy#EN!OMO#_XPOfNwsc5HE zv{NhEX%+4CigrdtJF}vlRng9_Xy;V4b1T|;747_rc0onEkdHD|d$7g?(t+)r@(X+k zzrazoCTlP2`Mz5Xoc|J?=>yVDWM`sN-}G;IXF9)jq-ez%p*n@(p0#5=OQT+h)hLbm zcClP9fmcu8AAsGyRdZQVM^weHKic;Ge?ZdE@GjZijML&0Xe6wv@TP{ z3_VOhcB|K~TsIcF8K}cyab9m7BLY|wRm6I_)=l~hmeU8;8i&35rQ_Td!ZuE?g*na; zx|4oJ;2t3&DK{{!;V~ca)_RQkXtsQNWn zLad*zA=!zBsr9V*gh%jQ0+Pc$ZR6?K+)wn4cMXYqz?B_sg5S;{7PyE{D5_4+;@5p- z6Vyyd&tgK_m6VLuMx-YU9Q9RWoBvE+^u`3{43y}?N-2L617)I4DIy5Ah0g#q!{t!R zBwsI=h>t#MOT%MV@P}Qb{0WgQvD}=x$QIs2Pml&&RO4jhaV@_RF}P>R@n=zec8U35 zv^HMW4k2HT8}X}{BZh2o5S#h`12xgNR;_~SCXyw>Xoj|hZ%`br@bJa|q5yF&lZDLd z5Sd|1DqNW~#3sU=_Eh6OKWBjzsBwR1L~(t~Rp%Th8J%MflQy}REBJF#7#h<#-=O{E zBC)e>BX!z6QXsNyAlB)ZlHYA#EzLs{p8fCK~Vrl)Q^gGIGbdaiU@}(75t<(cwYAqP|WGL)Qq>F!3i1neudD?*qZ}>sA|d{|HIovKLCoecPUI{M9MNM`Iy)G_ zo;FqQUT2i!c2-8^#Mjgu-!UvGeD2W0j~!GqZV2|Mm)vxbd7%*dBVwDja{xl1$5rWv}PNKA5N!8JzQk^9y9*pXJI)Yv%`r2zVL~KMN zouoPXMUFocOUBfrR4@%$?4cCMdnJl+dnJ@NgA^bqi{|>-!bJBT{{x<2ty=-AM>Yr4 zDsT&o9MAayziaG*(Ro%(VH3bU59~zWLqsEda^x!`+J%l5Gf{J$tYQr3P-=(!h@q&T zWXKl^+&foiUVXy6{z#g0AwNb`?Rg92I*nvw#K!c-W8UDx|3W}^b2>*zv^h5w&ABgu z+G6oF8y)=XfVX>se zQWi^FEMu{(#c~!iES9%e!D6PxcC%Q!#X2muz+$^wtkYr(Ew;#Fdsu8wi|u8xqQxwW z?QOA=#rCmS*eirMs*fNXtS*+h;0~XugVuKbN zve>Z2mRoGZVh31kg~blE*g+QigT?-6u|HYtV2l0PVxty2#A1h9>@bTRZm}aQcBI9Q zve?lUJH}$iTI@KB9dEG{EOw&BPO{iai=Aw-zgX-Pi=Aq*(=2wn#m=zUnHD?CVrN_I z9E+W6vGXi;zQr!E*o79m$YK{G9MEEySnN`ZU1qVrTI_O*U16~+Eq0Z~uC~}U7Q5DB zf3w(i7Q5bJf4A5T7Q4}6H(Bgvi``|u*NVzEap_796aX0gXD_JqZrwAeo__LRk*w%9Wkd)8vlS?qa>y`RM%WwEa<_Kn59wb*wS`>(~mx7ZIB`_W=QS?p(v z{bI3SE#}*svAvnLHygJ%8^1T3us2&{Z?@*%Y~tSR{}A^dU{+Mg`#664Oans{Fo7sD z*D%JbFd!l(vZ5e4h-2UG3BX7iXNCdu0P12!U9+w^>l)To$A~%Y8rGaM=A0wHx2n$R zuD&yVzPt1MpXWc1a{H}QU8kx}4t-AN!0QrtT?4OM;B^nY9)Y)B;Pni=UV+y;@YWB! z4FYe&z}qPBHV(W#f!8W$$8xeRT18-E|jSjpqfj2hr_71##0&iU4?HhRe1>X3;n-F;W z2j0ZMn-qAH18+*;O%1$hfj2$yW(3~Mz?&6#2L#^iz&kMTDgy7IzzYH|A9!KlMS)it zcvXQ{9e6c?Hz)As2Hw2Ds|~z^18;udEeO1Yfww5|76)Ek;2jcp^?}zAc#VO#B=DL7 zZ)xBy3%o-E@36o-Jn)VPydwkesK7fq@R|c}dEl)Gyp@4>OyC_Gc*h0aUjlDc;2j@$ zCj{P!fp=2iog8?l1m3BEw>t1n3%t_f5zTLbT(fp=Tr-5z*%1YS$v-5Gdy1>W6(cTeEm8+i8x-kQL>Kkyz1 zyaxmCp}>1M@E!@gM+5J%zBJjQpysrZ9>%jXa@V*Va?*i}p!22Qaehj>y0`KR*`z7#x z4ZPn1@Ats_Bk{e5;!G z*2{Z6^IosK*E{d6pZ7M%dmHAxjq={cd9P32>znsB$$S0s-llnPv%J?o@0H}e(!7_= zdz0W}c6o36ytiZC+bQo2$a@3xUU}Xdl=lYby`A&k zki54`-W!_tTJq-3ytxZsoaW6vd2?^x+?O|N^5*`$c_42d%$tYu=Ha|~ByS$go5%9z z@w|B=Z=TGXf91`;^X93%c{*>N$(v{M=0AD!T;4pNH!tMPi+S@>-n^VQujI|EdGlJ{ zyq-62FAmgr;9;HVw^Yq3Iu*lF*cfCL5Z~L$gI_whYZyp(zW^)}h%ZG~0$|yU=VO znjJ!u3(bz9*(o#wLNhQl<)IlAn!%yjIW$8;vrA}(hGy5$3=7R}q1in&dxU1s(CihO z;h`B3nvtOy6`IkZ855eZq1ih$`-Em(X!Z@wexVs3nhBxVKQt3VGbuEaLo+2bQ$sT? zG}A*fBQ!HZGb=O)gl2YV4h&62XbuWZ5Sn~w!q7yasSHh3XsSa~6Ph`pnH!pUp{Whc z!J(NSngyX*7@9?)Ssa?W&>Rw)`p`6lrZF^2LemtQrJ-3CnnOc#SZEFp%@LtFGBihp z=IGEghh}+bR)l6{XpRZZv7tFGG=B-rs?Z!CniE2EVrWhZ&B>uTB{ZjoW_4&z3(e`F zIU_WG4b7RMIV&`0hvuBnoEw_+LUVp-E(pzqq4`^AE(*=Xp}8b9mxkuD&|DsxD?)Q+ zXs!y))uFj2G}ngay3kx7nj1p%_t4xJnwvs%b7*b}%|AkOYiRx%n%hEiduZ+mO-pF* z49#7kxjQuXgy!DR+!vZPp}9Xa4}|8y&^#2HhePv7XdVsCW1)FGG*5))$(G1?nr}n%U1+`! z%@3jZF*HAg=I7A-5}IE_^IK?s56vH;Sr?j2WW30j$P`7!k4%Tibc{?V?2d>`=g4%4 zOxMVCi%j>(^oY!Qk?9$kUXke?ne`*HL1Z?J%tn#fI5K@A(>F4kM5bS4HjT_?k?9|q zlE{=sCL5W}BeO+hwv5bHktvJJ){)sJGTTOGyU1)GnH?gNi_DIZ*(ovuA~P^D<&hZ_ znZc3SIWj{cvrA-#MrPN@42#Tek=Z>mdqif>$m|uF;gJ~;nURqh6`9eI855bYk=Z*k z`$T43WcH2Bevug;nF*2EKQa>|Gbu8YBQqs3QzJ7iGSee7BQi51Gb=I&L}qqm4vb7i zWDbf<5Se^r!pKCCsfYM`n3sRzzlHWR8imE4nG+&&Vq{K=%*l~CB{HW*W_4svi_GbfIU_QEjm(*mIV&<}N9LT!oEw?* zB6EIZE{M#9k@;I>E{e>>k+~!?mqzBY$Xp(oD*wyI4X znEo(oPs}{rn^ukHo%D2AFKFduhRI^wR9b`>`DdfTZD=`et=&&BX0qB(K&mWE$3r7A z+E=8f7dGQbl%vy(GRLLa&SAEf(*x`_cA<1xL-D?u7RTG-wcE?s?L!q;yiKEUq&S!7 zG`>@;E-lla`FzbH4^zX}nY1Y>9>4w*YMq~!Vy)DQ{mf=YX}%ewDch*2tdY$1pEMV5 zb4cxjn#wBeT#&h@6lSg`Idk2jG8fM@=!u=;2gs{mE0)xkLaCij%fBGr2NbWHRnms8 zVu_uUZZsu771vML4UF+rgyLRj<>BIgE@&8N=d?bZAqZ7l48Go&6#8)#pmW2X--OWj$yxSsuYJ#wB`-P z_3YRhDD^`!6{RPG>7(P~f|Pcjj_Euxnp64=rN=(4ru|mIe_b=5 zZi_9w3l~?{V5;U<_ym7AutmKn^G}8Aj$1avtIz)VTxvW!N;9c1my*!&1^$z@tHMg+ zaQ5JNlt+>cT7&gkHBAp5pK_kw_4W{|+aX-tV#(L-efzU2w+B_ZIb|%GjG5#1A0??8 zuYAAH+xwnT`Xg1PlF&{cgi4|-rnuq-qA3&Or8i1^{1s=eR+`T$*P6eF&|_5S%+xnH z_htM)W?ynI`lkN1754BwNhyA#t) zQnYAtIW8DKv9Q(3fo^NN_RI1$WcY(=X&j|q!iYG|e?)WyR(wQ8MRUSR~4tN!lT4X=taZ#nJ8W z9<16TGBn;BGH^fKYOM|zAW0{w7~O)Lc55@c^|Ew){3(D=?>jlRpOfl@JP@y}^gxDP z+J|dK`iv0&A>t=h#PWen%4@56g@2Y}qAFrkt10T8*&lyR>nE9rs=GK7-On0suRe?$ z3s=M+#_bG^PFKZZmfjNmZv@_vj)BroyL$j9-x4KZrY?0iLBe+`(_!EL)DhBWjI&%R z?+xgw;z6=v0lAG&Y&PLfY`Uabae|iR)#=xJ9XWeR-0Q`mH>%q^0bwsFy+)6kjU_#9 zZDPGTy-XF(X4|0#pHpAMAA&aD>MELnDuJj&FlOR7x6wGR*hX+O@xJ1;dsegqd-6uO zLll$be?G!P8*~&W_-ImE)-}rYy2kxg#hD|NUr>e0W)!{2WEaj0ccs}VMKx2%DY}(X zDE_*IDhsF-duSvZI6|p}&R@LLvIZ*srowZQnoMhwq9{uyF2OacMTQMRDehv{v-Rhh1xoy}2H1b!j?vxW>`R za|@^8+i5NyH)vPP;Y3{8%EH3K(sqJ{{`>a407FK69*q-2fa-3aB9(c?;VU(V>4t6FYWs!#bA;yRR4 zI6lv&aMurg%N-F1eU~v~#B{Z-_7&_S`!ubne3_<`{cTQAqu8i8O=@dXKu<1F4=Gme zPhoXiH{pk{z|M+G1lp=pCrNJ>I8^xw9l7x%rj0EepgqL{v~ndg&J2Z{s3Oh`HHwuo z!)Fn=|$$Pe8o1NuvP>eRlIE`d}p*kq1NVDB}QX*Ms24St!@ z>YIqk9ND$1fY~iJTKf!-9S5WwHZuLhttw%YYn+xC+9dW8pkUu;dQ;2H-lV7Yc0Kx$)1;0?9h_GNz*!3b1v?vxZoY?5XhIq%0Io< zk-QsKwD#+bRHWSbdQLIzGihwALuvf?NYr)(uEu;B^;xyJMeJ!m#fUBAdrz4(W`En3 z##PK5u40~0QQOX;vSBsnrxje$$RP>HbTtdq5ec-p@NgwV+O@)S7biBOj{Uri;bnY+ zd~&eUR!FkfxzhELEmSnG5%+R8%J{Fev5zM{O*yW=CqUF2Eb2g&U`W~=tiXIC6waH zcwHZjN1rs#;C6+#V5?(AXfk7-idedpg*#n_AS)DS_O}vnluYVq5~?@5CCNSr{)&@5 zi?E4F`p^t+>d=d!NS`Lv{f5o)tn>bO_YLJfDcTdJXxDY*qWu$TW;cXRu{}d*5m(tB z7n_69cG96mw$B%**+FdR`YIzx{V3nB>jW9arFMW4={opUX57J#IPxOJ2}5Y>62!$C zmT?YjBs=2XLE(UuQgO2a)li=lR3{ND_LhpyZaQtfr~Vtx%-5w|%zZ6Adi{k}do3k! zmOcBoAR~Xw^8&jnfpKF{*cQw~p6{9&lq8&O2yg&1DggX-&Fu8&fyJ5ol|DEEruCN8 z1|lzP@HIx|ozh@rUy= zm8D2jX&!Zl>?ZczmWs_)7Xu4BCR5=MFVpm24I}J9@_#ap=$aW%o*O+fp80y;x%8nO zVFgYC7CXp5w&UAmY69BFg_kni=gQCWxsR?64d?BR3o@nKs;kS(ew;18vHh;Sr>WU$ z+9ds&a*>qt^mua&mvdinQ4?-ka9ttv;=1%Sos{U%#!30Fj9-g+=-Ne1bSiot=ab`v zbDS`pUxbsU=Pb^w=;V`2nva8P-YTUuem%*Bd5jckOjg(tFh~Q`#|w)7-)N z_8H|s=_RCQax$M%B=0K2Ts5cr;aju$ofMatZ)ZPLlh~W>KR_}-e(C|LuBT68Cn{}F z*VEyqyJ1mDCxnxA1r2&FkHiNUF*y z6Bl;B_TlV4ojB#AG%RkWnzLbO&i0CfXGn9G+GgGd92H6*@){bV!kDJB*Us13IJKqt zMVPf;ff%fMqCVEeb398qF712UiPweZ8Lp-lQ>IC#Lkqr0fjggQqXTEFqNFQGTe06M zCAXWTPf)J=1REplP-WRnDiCoAy%nKdm1W2+Xe?1J#aUn}wDmHB)i7e}ls_9rTuQ@; z66Jun{w?f;?au}0b`>+7Ev8CVFa8u_v64j@S>~3t({t?1xmpl!8!wzy*^v`x-!vZz zWZ^#U(ad*tI$k@6tJ~>UINsR>@gx|m2+yHSnOM-$uY8kI z_}jEn_7fZ30KUV;dXrSyLb0CEY9%bs<$8kxMpp=R&9e`4Zd<^Kju2I3nsFgB*6Eyv zx*^VJ*TH~y)0I07_X{W7)?Y)Go|?AQmLa{%;9Pe9(aLkwmqyVptX~(i|Bp@z+tg{T zKL4T*PJUFn(N|7|tEn#80Z_4Sup0W&;N3w#UYMM>BD(WI8?Uej^b zpxF6q|GcS4zVM-@;{8%^_n4JQZqt!z+?x>g0mASNg;GqGBPoqwK&;t^Y`|LO*|>|L zE9TXlY04CvYYfV*#5hf-v#mcVzriJAr%W#JT!z^yRCcFRA=P(Ld!e;|T15!GWX)Rp ze+$-Yl#0xDr4XCezZ++u$CW!KjGp2?5s#hG%v@KcBjrJzo)UYNYpY9C-8hTd=(uux z9gaU&ho*M_JddwUw!sPKQ%9-;N7PwNx4zKB;Kv8{2{fUaA2;Nz0Lbsjg|B;lyc4v(ajp?z|3Xrv8e_ zS-G7LS89C{`+Ho%Zc~i=&mJ{HrAklk99@vgG3W=x`ROJ2`bA|l z(u^y0oxitaFaEB$s7@X^sZ}?86la0WTh&A~ZKZ3XIjD(>Gs{#a7}qKj(BSh76(tn2 zeJh=vS~xpZa9WJY&z>Om@c5TowMhW`4Be^HGZzRgaPlNwleq z!#?=aFx)Vdh|SAo7uxhyUy+vk$JHc%ew(f+x2nd0GD-;boiH{nr~!L4lb|}4pg7W_ zpj6YBb=xROG>jZG&Yg)KSCa>F-q=Z{8>W2aRCJvupXDjC6O_DotE$TVE7p)+TFxiv369c z%6&v$n4z4hdFP^Zn@m3(^`>wApthI~dCT;|*O$F!R}@!Ncn4K@L4}vE@WKi&s_-f+ zys8Rs(@L{hrRiU3N-9lhrO8&B%`43obj;F>w3ayLef;=><%?OI4Yo)rNHjK_hj9oL{>!=#y6s z8NAF+qEd$(e>j&ot+YGGMiuL)PUP}WTGOFWNXY4#W`nH31CpzYuxVH6;64e~+3a{; z2HIN1zbi!sAkx` za!WbFS#_8v(cz^`C>2N%_?s z|E2vpf&JP|8^qZd-i>R%quJ<2wc>`NAFsHLhvS}9R-ue0S4$ujk!fN{KdhuoGm5xn zr`f=nYFpR+qlzE2*Dw1|6y@8ZqwX+3e;RqF1ulUUKoNp7S2ywu2QDCQC7D-qIR zD4YP@znPT$DxLutf(#wc0N@a$%uviC@^+iie|kh)KN`m5(^1isZDG~5kmGtPo$t8C z)6+!jb1C{=i9_z*XNF8&>(uP~A*nt_iHqCzR(-ohF6$RkS|kg=1Bd7(U>fY~7kiUu zrukEvRQc_XUf8xuHSRkhU8DfVNq-P$wC5Eg?o*KL5tpuuA0+krrZVk5`3Z4HEM}a| z!uF0;;}znRR+~brNJWOECjS@Cryj}v9~}#tF{0oCxW33TP0F8C$@487y7lYC`ECxm z($&$VOk7K^LM{E2QfBO=F|$UsIuGX@EI#7$vbG}A74Lc++59vc^=jy|BF)$xj9oK_ z@~w?nzC$&%MTTOyIsK~LYp%zy*KrhICY7zOC@E81T_^%KVd-lBT^3NTOr~DYXm`hH zyv%*TBc#v*#V19w)zZccPN!!TW9!W`nfFN8L`ns@yC!vN9Ch&@POHu3OsAvaa@J2b z5vV@mCV~#7yHlya(}z)IqiP@eavC13DzTZVvwiPGitI=lrY}iG3qfb{;}4^)|0@`$ ztgF(2&2p{g#2{kY^Ts6BAdX&vZGz;d!eO{ z>zj_8`#%}9u(qzj_PQt`@rQ5Y)SGsB)~-OtuWz)57%x_u#(T+Ba(nj^*JYZE6GRt7 z!#o4qNH)#&7>^krQ;NYeIC75f+(7!pifzM(&W%%^DZF85GgN)ORZe%kJsN)K+&+RE zfKVxKD@p5%xVBx=OjaICy1APrM(nS)hEa_$RVkD@x|Zt7g6_Chm#N*RW1I%71h5h@s&OyTM>U?J$^r%ocgWt6{V z>-}_dmh!Ifc=SxOcAu~xKQD-mF8sp+8hilL|T%&bvb@Su4Je_!= z(syR6=6eMCeqyIGCg{WaDgRE^qGgXmVPD}0_Q&+J8DnOQ;niHae=aUC`>-XIY0ep= zr((ZB`YYCbnel@(qs%Ak6l>-bJ4>lJb@Uk7y`+a7$A3lb$3cCTR?Um*slCr;sAT!- zJ*g*YUOui+c4QqsPa1o~95;E?T5PZ0mr99mJO^9cj#H)Ne=4_(*xi|&HHV{NdkR_e z(^68TUqNY_fp1-HH!*hIcrH&*Q6{ieJ2J5CC&nsg){wYTr5Eff9DM)C1LwgiPWrCA zRaNl>R~1hyS$4yXO3w`UOSe{{q%z>S4V{JOv-Z=7(Jp1C#vi+)Ga056d&am)v=EWb z7MpOAtW-MT{w2=uy2-epnY{3XauttK35^|{qH(IkLL>ErzFeK7gTYcqYoO!kv4YiAvH#PxC&Qd zDaS}+=~9sSmfZ4((u4Y*llatW?Y;q6g6*2wmLf`b#`3f;q;}C<0ck$OXQ}*Am zp-oY-Qe7{Vua5OJF3OLj`DA%dWw_qVHAC4cO><$(ycH+zc$ME;-7r^zp3(uW1Qpix zdq9xCKQ_6ct5mnRzA;}PEt*?XHLs>>{+y_G!IJtK-sJ`^-sSdLDf#%jBmwngOlSD3 zn*23xRJ@sxhC=u&&P+>N?yAoLy80ZBoaFcX^SgnQ#bDZpiQVRqduZB3^eGEX+^d=R zc2M!V{8>({I)5I>`ST>jio~?DL3*Rga?bL9(JfB7Uch<)5#F7aLaTsqR$SlJaY|pR zM9fO{RNjDyeUu2&Sw6s~sRXU`Qdas~nQ;+Yk^JtoF4<#)w9WYbhoOhO|xuoRl36iVX z!tZx)z+T`gJG!I~pYex&iF(_m9#1@JcTZ$>mQcoto8^H8yC>;z|9))=E6fY~vaoLy zD{Qlkk5>Cxwl14aJ?b~<{@^<9H~pcqG=$Mb!Kk9+`k@c!gUQ4s!=BVu1KMUZUBx10 zr*Q6bvu4UByHYkuUDXxm7uu1_9{pR|GTykMyB?>rHZQ6evF9f_Gh6%p9bW7EcUmB4 zKt0W0#E!bZkPGu`I@%G;wV8?*o}xoTv^(Eocm6#s%FelIVP~)nYn9ujCTZi|+w2<3 zX5S>OFVZ;fJ<&1m^GFKKMDpjL@igQ${csq2GPy;ESj4Z<4Y>O$CF6orUU(YwVVv1c zQ&zjPBeXfo-zFXVD=zqkvKkU2&P5-xZ$`R`B9GbE^!2!XNBeKK9{k4VJ|`Q9OORE* zD5WS5C)=e+VUJ{Ck)q34*GnsfTeU}w9jn!Pk=6R#t$JgMEIuTMyt}h{pSqT~YIT4e zp~M5CJXgF=Du=>+&Stv*P{|qSPNqWU+J2l^>Kn<3G# z#ZG^ktvg>a*`uX(C;Hs4NYbx5H@dG&V?o7iV<(lNU|XD_HbvP!wNHKeqU-0+q;t^dw*RVt0PqSh1aYCwZHJ63mq%4&WGj%@oc*3?ZEr}*RQ)8Ry9N&?t zzJl)P-2rE&ho(gyx98 z}&ko367w-gY!19r=tlj_@CPF=dl`ltrA)u^(M^LOf1}9F=n0<;1R;xIY&6 zgkR!;_(JVt6w0_ib~PfZNJlieVA$N5{rg2yFCyE=`H_yd>Y(x}a$Ov@3Bry{TT7GD zg*%DzT)dW~mEgRhi_Sr;#Vl2+rFSjuF&dl4l$EpeBIi@kWdF1#^tp}gO2)pbW=*zH zF0~U9#Hh2}g0+-D-`T2cguY+C2Lj$o+rlMCzdn|e?x<9iTDT*U4q3l2Er%OuI6v0+ z1op`;N?**yjKL4jmd2YRaQlUl_XyWv&#G*UFMXv$8&^->%VhdDiU-?0 z(59wWq_^hn9>bN(Cr%xM%`F9rm9xX2O)DnVm-g2v_{-n+|0s>g(3MK#SEZ!lgDUd) zoH#9Y6>mxZC>^=X66%b16DQVCC2bN-)5nRhJ|;YhGd&A;h+}nC?GUG2(Nl>)d6ouJ zHz9Ab`>$7Qb|<~oI>R;VRf=f_Eup}%nydI7Qfkk*w76}4sm0t5)%d)mwfR*1Q@M;C zaG@?+v`ZweLS9Bp_(m(4n=4Pn(igD|SFyyEbF0q#Vy>J!s@g>N!1^JYqm&XeQ%ba8 zWOEzOlrF4U$jAR=R{0r&%^F^Y4*|jgc!3hAV)%m`-H+XeRrr^Rh7MnfO{LGPw{JsC ztKQsfmeWO!+<)en7lQ(lm~`*Qu`DNSHZe748{ofCTU z2~0n$^6HueyG9=eI3 z4@|yF!cgww)`Lbn`%;{CzLMs$;-iWl!F*-4G9TqhRz7rM`dmH!oMsz`8P+MNu;cQ3 z441m@DX+^XhlLH*IPRI%r{!@&rDGk#u^vI1$NlBPnPIxY{VSKqLgBrYc1H zWGnW`>1jUc%F(o3oEA4T-yJH_QA_IUYZf(*(J9s&HLl5Qi)~!E%}Z_KYA*FKk&2C6 zK5gXMYC%QsMHSxS3a_rhJEX#^ukacwyv7P|Nrl%`;VrH3mQ{F%R(OY1c!yVbM^t!6 zR(MBMct=-w+f|zFE6om-CRb^8tTa1SngNw&V5KRqG=nP5;7YS|r5RFbcBwQ&E6uKz zW>}@!jkbjynNIV9X$RU&H&}TfPR+s@$13*xGF6;rrmk1}2Lx?bAP7F6(kfRRz=AT0 z6>Lc@q5R$xoLw_lkp8ZO*Hq!;ECFyTUGj;)u9>s{pFG8xMJoMdMAfRNHK&={r)`yL z)oZjUZL&xTmpzGJAB)_jx1R0a& z5YTYNx%WQKy@TUj8+0^lylaC#MmUZWR1R+8>&QNbXx<=7-QHC?h01k{_+X|B6v=oM znWCbaLo%H*Mf9|&22UO6XaD#dzvWPYY}D)Rms<7T~EnJv9;Edi+#{r(X0l zkNDQ7rv((cAwA6{$s04R5l?-YMo;~iMxmS0Q$&(W=xI?Cp8k#}f5)Mfc)W=p2hYRf zE&Nzc!f)lrfz^1t4UZjm95{rS?_ly!V!o3f2NUz%{8&!R_u{c=M`B&WPsI5EKM~_Y z{6u_r{1wLxwmI5EM za0h{pTR2$Y6Bh0+@JS0t3;dUb;|2cP!f67Zvamwn(-u|>e8$2B0-v?8QQ&_pJVM}e z7V^Zqk6RiZY5P5g5gl0m4iv@ZXE){4jJX&Cp zh0Uuoq?K>s1rpl9!pjAAwD6IY%-qRBzUJ1)EhQ3f<{1v{?BLrByI9ykU{?#9*KlYz z2R~xi-9cgQ;ow&sx}Js0<=vhR3Ue<9g}JwdD};G{2PL8nEL`f{VY6H;HDPxJg1KvTCD5t&rmA#ckp9|B@VvBu++h?8D=fy zy?{P$cM(yZyt{>i^6r)v@}@u^H^2z95#}-ng?VcSC8BLC&`zRPe&2ftyslZD;`3-Yy)8WcfeeY-$3b~_oP+Z2z7EQ}`&q~b_xZThM-1dMo_*Z#W1+me zzk~AbL<@PtxsO|bgqe3a`M43t!cQ}#)f5NcV>s2pZy8RrkPj~Oaf6V&%NzN9+$JQD z4-4>dvyebugY$9Akid6oNzTWOLjw7;VIQ{-3H(4p547+jffW|=;bA^*C=zD=lF!F& zMFPJP=DdYpKa`<}LJPkU7+LtOFjrdGlO_gzQ{~|2467adfMJb;-!q(JA>T>uo4F3k zyYn2BcWWJ#cMrCZm+XBr-@z|3q{adV*D_q_;13KJS;!}A`M7yW%;!C|O33;D27AGbnDXz`aEdZdHGe3XSW8ieGd9Tetf2ZedLgX@@ig@wK3 z-IWds^D!3khcv!9)*HoBfxSfXDhv5EEgv^lNoa4;>I4TRq7xmI zcTcjgk7#wWgYxbv7WS3UQyrAh)fR3dp{F@0p{HBO`$c?nhK0QO+sCb0q9mUi;Nu1@ zf%MTX9DA09eAc9oo3$i#jD((JAz$Y1vydk$ecZ$)q5Ms!Z!WNqcP{w2 zp-V#f+fX03bqVBsg1))PLOuq;$1PqG%7-ucxY0}CM2YuO3nvM@%)-e6FSl@tz$+}I zbM#>El@`)x?|@fX$On7)xFt*?;*TVK+!!WsrZ8V?;VgmIS$KfJ>n)ru@CFNcqnVG} z#zYivl=gA+n81UC`6dekfj3)tw7^>|3f%jU-dvY-TwU9UW`?y6-v|1$0_gl!5 z?il}CSSO(mT6l=Shb*iY_^^cy0w1xEKYjDfqZTfa(8nxn68N}0sL7WlG-0|dTe;c$VkTF86ZG5)oXKO6VW>lTK>{Dy_| z1ioouoxry&=4HLO-;SciH>6B~RYvuPuDsm?zK|=1(l-bHRP{sfGMef{$DEgqaUn@NvVQK)z5N z<6jF$i>NOx>>%(f3+a12B-z&%ZYb~@3;7Z-A2;=hWS)rjaciGIJ|E7<4SoW7uQkTM z7V^y`82?&0MkN1aA%FPnzz!B(EU=@6wEYgA>}26h0*fuY zLttkM*9h!l;bQ{3TKJ5>ZWg{Qu)BqC3+!RxM*`Qg@GF5mE&NGfFAI5du#ejj#a`aS ziHO?B!fOO>Y#}c`__$?JnE9L;A2%)vykD3%vG8$$ z{VaS|;HDP7B5*Sc-x1i~!jA=(SopQTQVV|;n6+?)z|Ae>C4V0`J&IPmMbF2rj{^Cq zC5(S9yj0#Tv+!DhTU&UGz-=tNQ{c81J|J*A3!f0Uy@me~xPyhS3d~vfuD~5F{6yeR z7JegefQ7#Z9B3h*qvGRsO0nof2_0l1Z|B4K*TVB9bY}}M6F9^|{@xbjUkm>sp+ha? zo1ZZLweWHY9cCf#cJ^@-rl`^LcrF^dTUaV^4+{qf+|$D00{60TlEC2>h5|=eSSN6# zg}kc=<6jGVN$6+`vjWFh$lGdt+{P(Nj*!s3Eu1WH9}6Ra<19Qx;Jy~}H@d#r&qDrE z0^?r`Hy7p!7V>EcjIPx5`-8Y*xL zVV-Uw-6)0%YKDchEd+3;g;NF2vam|v0Twn0oNb{m@IVXsyel8Kl1jXzCG;Q*s|5xY z^64AC$y>+=Ao{q)RNfsU%#npP0xK=#L((z+wXjS=t1aY>K|XFk6;X2}bdH6c1kSaP z4n&U^u))I91U6cDiNGZm-Yl@m!utg-weVSi%Pf3H;Gq_NE$}c4R|q`Z!V?4@Vd3cl zkF=2QO7+cA7V?e&jDIcUT~R)6krhAl$uT}|loeR@2xr0-7LF3Q(n9(g3R(0R3#%pc zSOx{X+inGpk$6wFaIC=97Va(ZGzy*a{_O*kUy{Yaf7jl;zQLi{&nzu7InLY{7I;fTaJa9FNgJU zgwjArf7V?%wtp8fb7Zv%PGA(&5S=U92uy}kYJuZo80UfKvMco!RR5#YwFU!{~ z7zoncF{#m!?jcfRO-)rj&Il2%dx^BLx~i&nQKKc@2U3@X)eTkkmVkBRqOR4Ib0Hm+ z0g!z^Q5HAURK+}4Jud1Fo+c~199$2A)(y1EruqR^)I$krpe11`*>O3g9!W@pEEkrP z9oJw>!m_d>?QBU{T6Ux%mW1VHN7}`bu*B?0LoEr*%#O6HC1I(VErRwqHAK9H_2!u7 z^v9xeOmhZc$!qT?Bo`}|wH=p>bZtU%abkJfak(h5#O+8fMl5qXlJgpt zx*f@R4a?n*(7K=kUQlnV ziVh%9hODcP>&T8E^#rMEK~%f2p{CJtcGBdkSU@qzU8@=zYGO)fP`WhL)mBp+RKa#3 zmZpV@(v?_n3t{|DH)4qi^ip@tLWCZgFbIV8h!80uJvD(|>7@zuN^c@m)!{4_Yt;H6 zbd3r0&IX_q&tnFH8xoW@h6HQ`*ct7RGi_sfzoEKDJWL#Yh@+~G+aMCqS78d@gz&tE zIJ_TY(TMmrC2V6L{>^~9G&WYowQPS7y2b>0r9`t3p;Qw{NY)WtUfbLWVFJCgg=Qhb zmLL>2#-7>=u(O2}T$ThA+&Y02;WmI>nn+8V2ezfxo8*1s-wwEIHO%HFo+#TBM?+nM zOPU=>gu}#;Qw)T6RG8x23Ai}Ph65Yuv0@Fw55*2;22RCW#<^t zi$j1qLNDA7*D13LK!-(#RnacJq4ZoG)y~25u6XWJC0k;daTo|vWRxv?GfWSwZy+CaECc{RrPq@OP(9(c{rZCR9iQZ>LWlXmhw$-Bw*LtISq-Q zN6{M*D6Y3Knpk22nK(wX5Mit)kh}JF1ec-qaYEt@HBPgTkbO0QgzN`GaZQ}y;{iKc zNcsp8U zmFqy_IuMj@kO+|!DUm8f+_IV`x;))c4+6DE-9k_mYaqlW4K>(??Kt!DK03`#Ny^Wm zq9zr21ga>Rm{SQ_=Y>(Nb3zqx7l+A7)rx^|jl$&BIrKv0-T+}P2wh_Wy)sX;5TRBR zNXWq;bZ)AQlVUzGI81LWPz;0@Dog?v0T|T(+!H+A#82 zJ*Yj?RC>3e6*EyALG99L+dE3fC7M7SO`1TlE(M_*zf!;0CjK(bLpmG^LRTdDoccp7 z%VG2uC{2s!%mIlcA8twW(J+EU?;QbBcW^lpu^nmI<_Q~-jsmF%*y{3)xaiBqa5RYP zrHI7ZY^n2NUZO5{ybVqQ#l8YmioGr`QIS7Zf<{r{{UrWl9I;6ekF_%Afhby0Ovfcu zt1D6eVg=y9yTtfaj_BT}_>Z^mBYJBpy?=s}8k327qT_{BVJ53ivSOQ@sU-Gf%bE~L zz$u`T1DsjJd20N+bqX=APKZeYoEFQ}s-8})bql2ipo*M?o}r0U4-@gPnpkd$XKEt# zD~aRA%;98IMDF%i$zMCu_E@jOkWJ~9!{*F@?i6Y&BNQJ;!MJh~w2 zg(<4D>2E2jGwPxg)me3Mit5a|Bt><0U7Dgg!!Aovon@D&sLr%2QdDQ#m6}@alIyAz z)!BA+it22;CPj6&U7Mmh+pbGdoo&~rsLr+<{7U$o4(qw1dy=k&D@4htI*|#Q5b_U*`COZosNRyq352ne^ z#)r~mXXL|ava|A$6gkexkEY4a%E!`VXXWE*va|AuG}&4CWSZ=({8yUnto(PH?5un$ zO?Fm3ohCagpGlG9JpC-lofj;|fj82u{s*`Va7|eDbbQ;_O(|)>4Dd3n()aTXak7t)dJ!` zBEAMjWnX#A5-KY#;cXB|@y7b7 zss`O8yz~x8ok2Rpvb<~GX{xn^_v|}OwYB(Yjg5UjCN(%^J^+bqYpSiow1VYZ>tt11 z!iOM`T}{;ukyG-cn1)k{EZ@hVk;@xu4ynPM8`S(HMWMF*(-fr~l+Uaryj9=Oh!;Wo z95nJ8Xc)bN@P%cfejUB3VCzLN%rOTz-l|adk*hD6Wnv3dPka zMWMKgQxuA;bBZz)lrAaCuAp=Uh0;s(!Ev#jGTqW7@=*6QiPY|qCXwFjrAefC&oqfN z@0BKz>b=t>(tZ6jiIm?UO(N|#Op(e-`;F2h(thJKiL~#NCXx1i(9M^gkRCf|0_l;{1kz(iO&~pX(gf0DfF_V0 z13{o1+t5%~RVyATPm@TOL1_|cGdN8meRfWhNTVTX66v%{nnYR+O_NBkT|p{_UUisk z1sn!QjZ0J|b=PhRlY+Y|Oxo?CFsZhu!lc(;3X@X96()^FC`{^%RG9MLD1|BWjRvM{ zMf!2EAEODR;aE)|75CNz(s3V6ASK6X0%^H#Oo$pe)9j}S6w7!`pjako0>!ewCQvLB zHGyK8qzUAV$(lgkn4$^fj;WeJ{+I>=H55@5G-ZcOPfNV%>yY^=3Td(+MIludrYNM#q7;Rc zS)8JfHgzcqsdGq*Li*H$LRC!D!dRh(G>J57Op{2ZC211r)RZQXQcKe$(rQ_nL~0$H zCXrr;fkb^s@{{Xb9bP~q&5i(#d!(elV?45uNSsH3NI9_ zoT7ZzJY!$@+*YE7g;BoR+bhy!Dpr)#23n%O|Use**~_YhHd~EibcB zEEhRilPqQs?P4dd2?IzsnMm)9&(wlMxEe}keq1OBdP&Vm~i z&6#kMqB$FG1`RV`l?!SY*7D33Wy@PY#9~jSEDICmAE0yrC0_lyRS3y;rhm#imO$#? zrdfz^yJbPY4OWxbI~=9nQCcizPRw&BC|GA|sA-zxnC=1zYd;MOA}lUgQFlifbC2EC zwR#Y-_^E}P%DbOgxS520 z?x2Kz;h;$V(!%}{`jv$x^6u9bW+n6+3%3&Zt%XB{`8x+C^m_*-q8}{WRhWNtP?&#m zP?&$VaF{UvV&QHAf3T1s^!F&3SPu)tD~%2={nh&d=rKspx{6D;R9kj?@JF+@5Sb!v(%FOr#&up*Ti z2`3V{sB_d%TWxuf%0!M<7It)iz7j<@q10%5^QOpKJVi$E}qXCfA0;v2Tp^G|@!FWb0^D~ujBr!h| z57M`&lb8yG?ocqJ&->bw)eKz&ijN&3$)Yy_Yv1DUN@5!cWfu|$9WA0Ts3?eEgN7DS7|wb(a4tE!n{###ID0*@ z!^3Xmp7Ln$*h?OZ@Yq`(JK%ABdF+VC4dk&C9ygT7&UoBN9=qUiV|na~$3F7d9gltG zu?HSEk;nC@)`t>B9TzvuTRxs!H03RWEgd#;97g;8#!ho5eOp%WeFhQB3 zjM&p?C{*Ml1WZr}XJ%1c(5I+~gP{(d4h3xpJO$4=!^|D_ae33Ioy zTC6H!`^qf5THw|eUek|4F<}LX#kDBvOSpOkH#|=eQG=J2rsrJ|8>CZgMJ~2&5Sz{o z!@vU?@p$0j1lSfl+ew_XaejMwq+Gj$JW{UB$s^@j963hT_;}n&9w`G4kjG*?4wOgA zwdL|ixpt5|Qm!2=kKORNvpiA;#;Io{7dqk4KYr|mM;x3+)ZTd9RUX&J<1l&L0FS%L zc+ z3kB+4UKUuaEc{Z4!A}LE*3b*5-bPYBm@@= zoMj1?V>e_7WB|$#z2W9k^5X8u5JN(CJEiO%;^6*x+*2M)@Q7~&TrR*j0`!QyfvG!0 zP)z&iun!6D#tQ;vth_s7gLI0m1K!~5y%%B|E^?ds<`$eS8CtKJ>;1mnH3Y=@IM+g*^n$uy8$rGcDXm;4BM! z3OvBVUIJ%Z*jwO%7OpR_!om#%9%SK$0s{+61?DZx3JfjWMqp&&wgM|H+(BTKg*k!M z77h?tW8px7b1WPxaIS^B3Y=%*FoCre^10c*IoQHJ5<1_)z5*9mxQW1p7J83xW?1Cl zT84`q{DEPeg?!6^Zw_&xZ*ge7g+^e5g?(0WXrqO62Pn$f5(|3>Y_f18flDpyFL0TK zWdaYikZ;MusWlevEun{7I8opc7Sg@%i1$bf^8$~uaIV0kEnFw^vPP6bO2|e9HzC8tB?ODhdhTy9` z3%?ZRGcEj4;8_-~6L_|Tq2#)AEF3QITnj4&o@e1mf#+Lzpuh_(JYX$*@KuD4 zt1zH+^B}0vv6Xv4LO`8fRE+suD*<&nRJ5BtX~>0Iy{Kz_O;hp)Ds~J~6O5W2o3^VC ztF5*&P`6|1t~y^gC!VxK{q9JlD+xv&&!p;v3-vscqJ)IH9ur^H`GpG;8Y=vl=A@z4 zk7?yL22}kqjV8V*R@DD7jV8W`hDLyCwGC0MFj|6`=Hfte5Yt>7XcJy$xjlcGC*G&?D}^B&qC-gJbh#U*Hgko_=~=Vs>71_{B5LMtQ$ zCj;$JQI~qRff{Z_OOz03q5y4CLZHb4v_=>}#Dxy65${B>vQlEi{Mk;=(zKRCPXs0+{2(G1} zG8!t!K|2sZL0iQfR5OuTXslvPcA>S3F&T#DD#m0P+N&6o;%Km9OlqUWiZMAAO;(J_ zt7x+rV|9%eL(yo(nBGUL6=QlI%~p)*eY9IB|FrNF#fxHSykeTm?`Xk_)+4@oxV1Fq zL_?;iju-72s!Q{G`I=K zp^@Wx{)Dn~MaC;C&X~Qp`74e(WiG{Fg3j;A|=^AAIHk)z*ROR+JZjhlY zuO=+5T|^rri3bXEN}^0e^}x_rGB_hBENg)^i<9Jn+6mF67L=FNs*XQEfdO_Qac=EE z=XIDNX&p5vDy)fF2RPQjHaU<8G=l8fX}tq!NcjK9zlkNyexHk*CzdwrFI=^q=U>p6DGgHG|)&nX-odW5-YIMd-kZUPW0`{}HQJ zUe+x$tg$~x2Te26ylv^R_ukVo)0)@e@4t_xdZJfFf~yhDvN)QWiQb&D!(B9oQZ#cp z8hZR+qp5>6&4axRgfwrDABv7KqAV{Nn;TG)+p#3KLrHGC5^H7i&R{EBzvQ0dMl@!c zi+g4=Edxqct^BInbo!@d$C9g89$$**V@q3h!1HQ)URm0*9iC64=jEkv**)x|=8f?7 z_yMa{Y%v}Gj~_u2hYczr6^0-ZHi}@oj2bCM4Rb~jhEc;{)XeZNUR!7&QS#?N^c;SCZR1wx|+8uvR61-09%%^EqEXdqe2)Jl;kQ(aW5xg6-1$6i9%=$FahAAPmiGq50gBTun)?D%Si|1f|RM+(h%18mNf0 z;DTM1s9v_5YNzF;ndVJV6AVI~V5EG)^*j}5s1^t2%h6GLUo)sAD@WgmkupV7u(N1`?qDC9FOk2*ZwLu%oFY z*I1IPk4?E2LFvNXl$g@esM4hVf3xLKw&gmAXIlui%a%JJ0VdqcCg6cEY&iVatgnx#MF)UIaaD z$cc#|I!%uM-|RSr?RW{&*$#s3vg18Sfcmeo`gkA=JI;a~e=W(KUXoiKoASP}ejq<< z@k3Qn^Bd@k4qwr!sO7JcDyuTbmzJGdf_~M7rQ`R5$Pd9;c1}sUwm3KOf_ssxz0(sn zw5-N6I%r(Wl_M$=_7Mp?w*;R1s#~U<{vCw4GovZ&V}!MwQvy!ux1G&C`UF(=5y5u( z=zBk8n{X-c3xe@-k zp(J-*N$#51MV*DUi~MxOPufK{z$EI8P#(HPxu_dB%Wf`7*KW5YE^4taavr)){LDVO zrVSr;Cte`(M{~5^+07G5p0)_HiZP_p$+lFJ|YYs-3cGvQIfkYcF<>tAL&tveb!9Q=5->~R_BUFDwxz*+WAK|TF$;-41#B4?o2#L48K|GWS0TDI9F{oS@b zb|Au9-bp<6HhZiBRQ4Fbc6n?LB*0@Ke%ND#;jxe4v9+tJw}eNy1APZM|P>||y9_uiUM!ar@>TMH1@@=4;YkJ(!bL1k|dY?rr|K?1yW2!7aG zgyF64;H_^;a$m&`J5=}%lb^%!lXloQDu4Z`9Cida%YG=R!+%U1)?#1e{PorUn!k=D z=|8sZv7->y@Moh(16;3w^_ zUse9f(0rZkSDp&avULUS%9O?ve>#6z8UKC$T1~<;rI69OpLrU>TGl1r`h&f7I;iX| zg6;CwMUVh*or53t7GZd+bLrSzr_x-9Qa9asvG83YKbPVs?XXUzN&VGLIqWiUmUS&n zH-Oy|hqc%jIe&G45X_YR_a3{Pq<3rEV^<)orE6*2Gw)JLhF%FOdyHVaJa!W#K+v`L zVUH1p$9ltKJ!5y>EKIk^&p+^!c2`fal$*m1mAh^QXW0e??%FVMm(E{S#((dvf0FPG z+xFIN2y59O@z(n6t=mCmZxL*lx1NIpc zTb8Ox_3abeTeh`%j3(8$whp98^{w#iCe@eyUz6%PvQaM~5;lrpyNr4d5@6J8YzrO; z!>FBM)S%Mbz|!1Ku|@AA2-d1;!$FBfIyDE1L6n*;JBdMRs%;2s{sDxs<^I zaty*6hlf>?c%@?moAv{uV$%q=%QPQ5jbYJm&NRX>Z6BC6wlp`oG&eG~s{?{yvr3e) ziCsETMvGaTC?mxzl_=v_^NtY4niFi7=Ie{*U0Gq6Kp2`&hUODXa}!E)`^B1XfS`1C znwV(bG65Mw4 zNEY<8A=48>bP`Pc-|U#hc5DvmYzM)1*|8%eK>adS9}k3KM+iHD(p*JpZgyG zRQ_*v%w;?Ff^@cnV7u&?00~fk46Ba^!mwj8>{wWun_rr%jZN8KSSQNQB>be?--VJY zJm*ud+TY3GEIXt$oipnbFSOVfxrohA+|W{s=fZizDI~1E?e=ym!debV+S@wz(KJxm zM+DpDqdX+QHM8);?JZ&W=rH(bS!u2*c2FpMk^EHRC+(nRVjFi*j#Lh+0%zF~1r9ng zagfd?RtDFeO>Ow6nq(c>wts36)^bGRpTpTdb3kSP5Nwx!>LCICIT%0eAHwj@D){HP z(%dnnxfQXC8ich`ewN@T?V{sgk{hz0s9e+p&ax9q(OkMb1OVh@aUYZ&ayKL9CTLVAf1P-4EE2dZTROzl66+w{y7O@EoUbF`78V9 zWKh{Z1l#4G^B@5RpMf9t4`KM{BKYUR(%kv6f6f=a3*_fQ{G|PJA?$G(=u+jMzk##t zl7cdJY2u$2`yywc^To;Jp#Qs_cXK`$k@QR3_SnS;Yq=!x*v0IzOF(6h5p0*ou7d=4 z>Ox{(69<-`=*z9zNPx$lzz=(jFg$h-Ja$*?u4jemKl1Y&e$wu`OXaUM%3aTcv+TYCcdbd>rSq4S z@!#jK7fAS;w!QTt!dmW2ymc>o>m^XxTLjzXt*w0aRzLi(w+O>q9kOF{McJH}&8;iV z{a%{;HTGN?7|J?j%bvAErc&A*R+Nory;{7i)MPXiTxZ=#BlF)&uU>HpT)AS4mR~{U zO781!ZR~tgqr&nlM_g7)ORL)<)|O6Lf|O91&FSBDmNIH&CL=4Z9kZ15+k=_CLa<$4 z*$omPXaIiLD}>>d4d9jD*<8zg``vALTW5;w!9*e>8=RV>wbL^erh`ME?R^Aax;++lIJ0rl%-XYj7?@WROcxNnr z*gJ&boh-allFe!>&QFYgjfnG@Bce%?*x?IvAlSCt}nN zWYn;>jT#E_N}0)Q8Inc*pUyT72Kno57@)^??9O(~hg`OUV7u&C2?Q{j)v+1$izZbCMA;t0;H6I2G>PduR#b{ZRUE(Eh71lwiE)sO%~{>J*_fiMgSVMvh8 zRb+Fsv$+>F?kYrv4UB}i;(seqzxifFbnW|lH$Mk`|?Hs)GLW@8Ap%a}VL0XE#o zHsFCUj5!#_%**EHWOLQoTxD!Y3qoP2N|kxak~zwf>ckRiN!Ceet88V*e756G$YnbS zw#$x3Apz>&$LiyOFzjf69fxFdi?g|fu@R3UC~d?ci4i($EpF3>g{^F8WE&obShj&+ zyKHy~5}^81tU4YD!-k__!;#tC;o01w+1%3DjF%Cb&Q(XYZN}k=87+sZOtrL?ALUz)oDF}Rna!P%&7GFbofG^_`{?_EhnNs`}1hL)Jks z8$z&MhV<#chV;M>8$uX{Tn7sgkUy=V7m<2 z4H96;Al4rbgki`XFyyvu?$&JXme`8j5ma_(K{w^L#E_O-p`}aGTf`DdQXVl-55!vf zC+SJ8g^|^$q-TvNTkdR?szOOpwS}EA0?h0Tg6(p~1W14n#^Q%ll`x#K2F|!Qo4Y&q z#QvbeMUtL7QQ!04#0@$@vdk})ko-8Pek0uJYJgm~~!T+D6TZAZEo@|wFLP^r?33f&$nAsTw+vSW!kN_Xd z#Sf<&VL0PiIOFMT?%%N|7K08KsdRffaf42`f454v|FEic5WuPuY?rD>LIPA>!W!a% zFjRdNs=l1fy_n5CA8UJ*upTWx&G?~`lx(ZhB&a&6D=*o$q<&;6+ zNDOVUFH&J`c`>oH<#{|~%*(Zmo1$Dn!rsWjIjuLstVCGL>)Ci)$7}4PV?bpe5p0)_ zPKN}z=6L*YauSA*K8BAz%;rAG=HAQZ-ih6GhH(E?e$K>C+D#uSH+`nubQU1zoU3Lz_T0Tu&_6fV}Tu|9%|6gn80Ut%x{r%k} zbWm)l_$a#@GrJ31q$)&07ij__B|s!b2t{d9MIJTM1?*r&6jZuCU_nPf1qE!Nq9Q7G zeXxt7z@sSd@0>e(=g#KNDEoi?eB{o#=gcYJd#3DUGa)e}WRJiDkS)f*$VdjVUxDnG zsMxPyEt7W3<*)*S7uGMbPX0N;Ar00_SXu|udg_o1OFwuVAAAwpZ{V|vd>u0LSq+_i z(B<%p zxJb+h*T?VxNAF@_TqFZmUEoT@gcTEK$3!fadi3^*wEk2MpJDJ4OMn>N7to1HXv98; zrBy%Xz2y}yG27XZk3dUeXJlu`_>mny$BAJ+{iO8;ITmJQUqWZscaha&WM5&Hk&&1Y zvIFn{WZz+6WF!OGc|g`ICYr=VBgN}iY5JQS4r1`~YNmBqzQ*eiEUgx4yz*UMdWSha z7*`VwS0e+i!{j&LjO%~U*)3dL%^BD4m}OifW`yg6ij1o=2F67)a9s#o7sN#Sm}nal ztrf8orS(a2I2nVN*afI6)nQ#UVyD2;>Kyaldv|e(+0KsKVeKV$M%GqC*4luq7CG)> zMs_N6c4rq^Cq{M}W*HfY86nGq2Xxq(7#JDJK-L?`dc{P~nCPx}S<*BvhXe*MuU@iL zK8N+wcqL(J^-bf|&*i0enB#+S_0({6H{hyEe*2km)q~FN>*DIexawn;agmr2u6%d^ zu0|Lb7s$5h)kB*0l*7dsyu8N9Qn|w>XuNvC(i)$}Yl6#5?=Z&);~J&my3&B_67oC2jH@?v z_IMZ9IL6fnvy6+xjBpKx2jCijfpL)xTsHvM^)Yd6OiYc5DT>$-XhjV%%<;jv=El^|hUUOJ^|PVW2ca@@d#jn&4ba)QxU_C&TGKGgv`EZ|)@|?r zTC*`QEs{a&0W{eCF>zl^+!GUb#l%9z>~^`s9dcNJ!OQG^t;d#X%of7ZS`zdAkZ`HX z%yxF<9=lKLv3s;0yGz?%Xy~^)DacYY!MmWdm$(EUWP*2NmI;!W5y55f0D|{pV1gur z;A0@TCMH(J#EO_$rtmG7)+^+&5`!1t8d*7?)YfVER>9I*n}%O=c+DptCo+P&P1> z?U-dKBxVF<7d!yU>lhdc$$;`Aplnt|-j+u1$l+ZKULu>dPTHms*$qo;YZ{SlE)l(x z93LJa@6rC-%s}=)XK!_Zyu?7>$1DROF(V*f!2^JNjDdlW3?Od+$c~tJO)>eewA&|# zuQ7O;?9jSom&W89SXytzybtbnxlC+lNA8l>3|;aqIoM@}@*Q;cTP~D08OryVWhf+O z1mzGs0Lsr87z)XNvIkIhD4$L;-{GSL6I2(t@V9O zKEP~74=@k7<=HKrFap(5?-?zXc!CvoQYz!_&wVn&%i4i89p1t*LRl972GWPWC@I3rh_ zo-0nx6{o2DpMZgPfzEXEx6eSLbRnh%I^A6h`_x>1phkzzDekmkiTH~|^2>e^E^$5L zafu{mRN_{6KxG@aGHj5H66>MFWUh$kio9Hrn=7KK#BDI}mYCE^jB6$4xwY82Zi!KM z+E8M-F09XmzJjP+D2W*rx*Hx)-%hR%8ziI9CMdK~t~e)G2vy>H(sYj;-pAm*Ff>BJ zGwHL>%!qX^-c^|To#+o>X*J9Bo?gz?=r}v_rScq!fjd~Z+v?`(LvnU5{nWPnkAC(- zXE)1L51yMcqmMAlj7ZFg(Kqk_G@oPOs|3kl)C!DR=8Aj;=v!&`ogBW$;04suSz>xf z-&Oa>VlF|H|0GvL}6H3-E+Ms!5%Im+u4zOsFTaZ z?&xl-9?BwTJo>f4ar-DPwUGs?j%Ga@k~Mkm4p7*)f-j7SEfeqhumS6re1oh0o} zmcuC+ygk%M*2ACn255k4!P4rV255i_Nbe!X2lvn=20o{fuK{L0r$J};cli`DpVKkR zd`QfQPZA!$CxU_bkPJS|BU>A*DB2U!(!<}MxUbR$1a(smuStID|5iYXfjI1$c85xNg zA!`i}Kz1GmMn*D_O#rfSxngXt7_E4Hd`Y$0G8IQT-+&W9X8t~W;;7_hn2Z#?CUgS|90n9 zhYcjhv(3ngptEPW$YwIKOEJsHNX!V?74QILmt$aLBm>!PKz2*6xG7i6Q@pN}rX%Gr z3WJx|EwUu;umu{g(Xh1cNaMA@<)wF+4dir6P$JM}J$z!yZ<&ZAsrAqW>mVn#*LD`enkF4uw$l2KF? zMb*g@XXc4BR7H0{g=%F*9jKx@ZbkY+o+%5Ws_ZjlLE38*Vx0K`IOEJo%qa6E@PLHX zt7}L`=Jk;>M&_-Nc|o2yKTovC6X&VqUxe1GsV_%?o4kEKvP>;U z3zeV%BmDtZelRI42w z7q}Ja%h6sI#LLlE7NjjlC(e8qoN?wPW|aBI@PLGObHdml8JYJ)=H2r|w>;5BW&R0N z-s8Hvo4MT$DPk??AG?d2dih^AF8_k)i@BCh;ht+DF{4_(g9nuGC6|B=l2J=v)Y3ao z^iqX3eCFpf*b@bypet>tbgT##L_#ZqV{hv8~Y>N6!Wn9Z2aL=`nm{Bd2@oT6kA&h}9h9skwQq(dyPn4)as$kw* z$Y8e+eN9S^t&X8wM^$*|I!Mf@j?>@)b=2hau|YEG7>znc=7}rv#Bfy#z0}5ggpYJf zv9Hk9WcabwGKOoZ4fk9Ni5bI~VoIKvtV(GrO`FMqUUB2SFP$n^g}(+^ zmghdSIuDlC^?Ba2MVU*%c6Q{`-V_&uJsI2SFM4TC&dTyYuKYu*7SP$(=c$KQ*D<4f z%rYYqGh%cBJOE8A41D~N3`TRnXjYz>p#XK1b{EQ_69zA!S+ce{q0JF%o(8BhEUmd| zfabY?^fqyP@D*)_fln9mHP6haD|Gf;m(PvNryFLO4~ZG^83YgD(-#BtAsKw`1D|{H z#9et}p+ZFO$bqT$N*phudr(s9v*2P45xq6Xxs>}qF{7I?%Zy0Oh|xXpfQoO&z&%7V7(EY0oASg41;}}6j`mI* zFQ84bHtwM<8X$UYjK4MJdA<)kPJSrfzK;>V!PtAM%wwl{pJu+|NiSg@icDTe|XJU_|4kkuoM#MHs66+Zh(2)#c?||4Yh0A$I&U4b1 zUV-Cnr(Ie*y{F-#x8zv6({R1#;?mp6@$t`T@r!ldGt;8i;@G=gTJJI~dLa(eA~7Rc zJK+J4wqxM_A{n$k1+9htS>gmM^-w(ttyR;~AF8{x+oxFa8p#jUv8^7e zV>|UwJ@A`ZwJpk}K7w#jBxY1pb9jIw^)4xrQB)K~)v?5xmN-LI)PgEH-Kj`ERCg=V zSMy9+5LIQLAq&zT8^$>E{8Z*7W|aAbGV@lPFiId9nb$|=buE#wgk_1dRq~yn^)5$U zH+egOEa{eomcx?S%ZKVRdwz;remTm06-IDrT@i{Gg~W_X8vqZeh~62+oklWBYl_ku zTcV*Q8mPJkLWP>OXSt2ty7Wb9D9hqSX&}qe7Nr?yUIb^HIf)r%POqIp=9hEA*dQ61 z7a;TVEz!af=c&x;O;X-=I^WIQZh;iBB781A&rQAjyOoj)P zFqTWe2Fa+UJ!)xdiPox+t1<5_q^({#}s(yI!Mf@j+yX)^snXgu|YEG z=!QDFSfZ09I;v7;LFMhHE^aAyCv8nS9$PIJaV@jqo@*g7qgocg14_7wOTY%nsHGQb z>1m1Xs*r`4_ZHIAEks|F?#EWgC0xgy@XmFRm{A=M!voS^#OY&$WYjSbb@aDHKTGsc zr92`{m&su{2JiK^zg!i5Za7H0{;q(fb*bg;%t0;%+u4y1v3@QFyAQV0pBt_uXM@bw zTYA}+eW`oBEn-HiG0Tid%!tu?cmNvp3NDhtXebyBvBc#H(9_cH89C6axV(Ud$lCbx z`UnjWy@%b4ZQ1`bOm=DR|GY@=jw8U)1=ND;rKo0c6E-#-OQBSIYZr1qx221Ovv}5dM zmyhl2$PF}GLMA}L*ZI^lpM&K6W;3xv(AhV+#O5=x!_imA~7Rc zW8eX_N-;1kl0oZd(E7;|KUm^BOMGLAeTp2tqRKj8S(}`XOc&CZ!+vrJ*grU(Mjr*g zb1>4^-M+EtE4TCu9`-&=zf7MN_nTfOt9>eLoO(g@1VptDSm`f_mNV_!rCt#I3sad0 zW2Qo4MpUN51E^esfvJ!TDn~%&cS{_$#6e5^s*undsX$DAgzQQ@es_839dTIV;0xG6 ziG!Hfze*ki#rgf7Ke>>ZaLk2}m{B2%;Q@s#NfZYlx){$JNpv{oAEYe+S<~2x?b}r!TFXahJAooC+11~MfAaW9joDdhs$3=~}s1{E>gn9y6@6w*&;;@eggVbm28j=S=p$2x| zOIr=I=yYvmPv$zFgkP?M#Ek0L3=gP7zGw;?B%_Xhp^n;daavr|QblZm%3DNjw+OvI zPczm~t6U9dat$x0Y9KMA8g|JVUgp$M1IehNE^0``g%uZP$3-kIBC3+NVPMsdTd(RT zpM+bCZ6Q~>jiQs!*|Hk$(3sny5m}DU$;bO9>-P}Pu3xS<<&4{#^_a&V81tHvm=TY! z;Q<)veOKI@B!fpY@MsbjjpE{*xDX1)H_(EWcG_v;lF*m6kp#h~opU4zKJ5reLTk=* zxsY$+mqe8Or>%1t0Uhc$&kc>jwp^!Fl(JC%l#zlTyG*`9cz`*JdxBjayY#X;6 zyA^UxEo@6!4=-%KyRgk=Isa&3Dlh0E_%mBuej)`%HfwY4T@XuJ8RpWu8;%VitIw9n_Anx zvLs&H-tOA=ayNU*;{MSxH$Zy!pmNJBXWV7Jl={{Ow~m)*6VuIb!}Wsjf*L&q6tu0H>BMfUF#NQPeqogCY~az zq9&$~6(P^diGA;R({GHfMo9aHa?LAe+~zG~7*k-(%}ZiNFlN957WrBXyvQU2#%#ct z85h$PiJ6!OBDuD`sb^=p81$Z z<6?eX%vIUm0hM)o+J)t2H(`6ewr+F(zpUF`2x;G5Zr$XJyKc8JjJsjXFi6Y@#zXJ` z28%H8x{(YRcLT7Pr20@?EQyN;;^O|exKHK$Bn+(OX-C~dZrb(|ZS@{-SI@p*oVc?}B89dg4$76A^CN5UR#R>)EWoW@l zyDfOkC800i8g~KhRoaPkg(RU}Al7jqufQ=ELSjaR&})TI$WG258ziF;8-+X_7f;2- z6RL{$r0E_xypO^A!zGH91tr;H9(|Ri)bK zGmTOWSX!UPy`P&tb1B)*j@(8cNYspJk9HvKHXu8W9Dim;c06?Ur!KNj7+FosGBOe~ zLRJSJ&{C&jU}Pi%*>^zpOl;}rch!#?uUuGKKcw;c(dDIg zmE(hP?bC35Wx#bd`Tfz1D-SyR2N&1(jLX6-<03I5Tm|p|Tum`BE|P)k58(P=TpWsv z-{RtcBGyV;x0XX23|?aYLsh8``%5F%7M9kZaqkDXzg%Lrvmu45R(k^$v4Yd_U;ystI+DuaclD3o*;MNX!V=P{XGiX^lO=XWcA|!?rUBU~a(spv z*=XqO+Agxw8QB=jGBOe~LN*&70O5KJjErO;%LB69goq|Y9mR`Y)CJQUj%_8d9x zWk&WqboRwAvYw3W1GfSf~7SmjaRYDOFy|gJ{VV_hO4gu*Dmr~Y{vCAboL+@*QJc>9n3N=5;MZ} z1w4Qfy)BJ9jAY;%4O}A=;);YAo)AM5Vu*tFrQG2wIs6xc7urY^mTI!AG-&%^X^l;I zAD~_3LbIJ6xyi1OfOjP*(C#`>%!yg#D_@>Irx#!9>d`DnuU7v=p%*Chooa2M( zP0@%=*0v`a=>17C%FOisg3i9)rFR|EJBnGRM`A|w=sjbgm;T|NObMUBsrMT3%f{xLq43Mb=DASjG8FZ)F%mO^ zk}IK{iGf>+WVF=nfO4xMa<(+elY@o9+ex=-owQIR5{IR=AdSdEmx$g;jt>uz1ns}j z420f_W-oAo+`&NTZD`yjBxVGp89bm%==Ep}gk%6&3?PdV;$Fq%TxmzI9D{jt3|=OS zv@ThqF=+uy>%oNgN#YWhiS6vjU2?CXOY+IV5;K(Zp|c-!p*+A)T4I)=keCq^dPy0o zq<5z=6p{gDIiNhEh+HU*==EfvSpIUar!JI6Hb; zqbu#S%1ogfboNS@!V0E9Z#!cOBxXcmI6R=TVhl`yWKeh!6gDTs^9ivjAvP!+BcQdO zO~{%qqnb8rH9haN2mPRZlLLl++`(UcpvSHo+)2YrQ2DW|e9!AkTphh_jH@Ftqw21P z2UJII1mo&RMs=^Fx>pn8<%HO#N}B=|%9f=KrqW(@OVbbPmt_%rdD!M|J3r3Y!I@tJ zXPh~S8D%~j9+3HUoG>;>M&|D!^LG>C?SyzMA>L5Q&w7q$5;LlC5j>!@1zZ|7NJfpHqQ;LCVsAoxpbESnDip7+ z&c|+n`s(a;SH%9n-F8;zGtPW5oN?wPW|a9;@PLFL<%F?8GBW=LneR)8uM*-5mHB#U z`m`LL!QefE>_d{NEARK(8N`OA^U+s=-BPW{TQ)c(TVR#)L?$=UbjGs_0( z?C;z&%eTyEBW9Tqi5W544i7-{0tPbs)fPRtn@GadT z4bW?_v<{{LI^+V5Wf#GeODioX)#h(h$CG~FwQk1%)fqkR~d5y@aw1B|LA zMU`agIpa^#ZoeFU#^4214S-V58Ea~Q4#3hnK8aI~JhKd?^L|YYkh3Et@TbF4b5?|w9ZO;uPSvkG^riws&bmcm%jK}E2+Ntd9pigxUR?_v!Z9ZVu??r zaCOWePlC=q%LRERgFG3t43fl*Kt|vJp-;oWAV~(uBtXWKA}=X&6~(ADjmaSwgO_65 zsgxdM*VicK!P2UiMzOw2(K$)+r8(t;Am+IcbN@NSBt@%lhFBLmyPgZNE<>z`S%yer zMi5)T10XiUzz|6W#1?>fUQ#qmiY7_XNO8=U*5}KiB?d3Y^H6N+YS>ca*b0```Dq+m zx*YA)j?|6KTw-<;7i1%M+R%;KT~6w!1??zkOEb>)(Anp^IP)222h1`~5;MZt6CQxG z69&dfGH`YT&JIb@E-Bh5mKRIYUUIkugO_Cor(WvG&Kk=;u(Ud*vFz-!)O#}JgL<-^ zi?YqJqU=vGJDX7sfX?pZqP&n%4#X^@B=J~L{?WHbctDSEA3`_)_!<><6z3EQQ7Gya zI@gTLY*Co{e)-Yd=1mGi+CV!1SP%e**GAXa@9;Ap)xf=s_3dtz- zT$I{0Rb<({n6#U!LfhsxZ;nFUi2+fXfSdbLZWej>_%vH)d>&if4<+i6yDWAsb(;ss zCaZTiNxNiJ*;05wN=qy6*{+2LWcwdZ5*s8V+YZRKoyv9{Chc}A+lINC z&?5RTnb8HD(c>`Xj7ZEVqo?2ji9E@PV1s02)Cn1NR2i+uBn|_4M|UON(RJkX`q1I- zd=Tu+2|W!eJmvs4-o5=}zozDD7U*+=wSPIL+Z( z2R}v{&Y3=s4EIMuZTa8)i#g$UV9W`Vm{G!?zyqRwfPoJQl9BL0B;3DH^eYs7RN7xa zW%uXIT3pKEzfA4*6*h2|mxw3Pn)h=N+kM<^>#x4}(_BACLS4J;I_#I8I$5&=DKa5ziKiX9~soLh)p( zDH_<%7Sd<7CiG9JPV<+j#&c+&hFUtCXtoiOWpxvHd#=!a5}hSBs6T5vOgMRw+AFHk;);&bL z;0ALtdps|hUcDPmea(^Y=0ZE-`JO%;;ZyLV2Ha0`TavCvyaZi?ND9Oo6E zI59tVF_&G1B=)8_Exk~CgbT2Epw%PXiXqW`h8L1cOEv`2a&Q3B+-N$m*0h6jOUv!i zhC7uuGwIaMJ;Lp24LbwSE_CXfg<@x+c)d`(n(EXp_M4tgeV?l7O8anYIjOu&vlpRQ zR`-CncM9!SO`ZA<)BeDR_TP0X;-FKpH+5=HgxOta@6_5=HP3Di^Wpy~4ECll7bDD` zLi=@j3`iQPdG>Iey*_dNu6blR*qh>9!YxtChkdr2R#k{;4N|bU$ym=}&*nk~647pYQS3^ZuJ? zEW3$L)$RIYn+uSJlysyUf2E&{@-OI55$MAJ=S*ToIUkTYtIIRV$aySs9^GGzR5{aS z+qx1N;tzp`%5Fo7oI29FIcksYPk$JPQ?y57dns-IT)i7^$6%d*73WGW6gC0 z@g0v9$1ny1^CcO%wjYT1a}5-&2d4N=z`Wghp!#(thi|KalJ5fI+jd}zuQWu$n{>V% z22!Yr@WeTj_%}K8N088QMJHzWtsXkQN7nE7oFDBGj!>#mr1=8Ud@hw^%zkd*tacO6 ze{mqGbCWL(WS(X8F|I8Xq5RF1z}d;Ij$)-(k(b=&DCqN=wuhD6?kMQQ9rrEQLOVSL~^I2pbuc0 zs|Lw89K{n}#W~409mSJgMZ@Gx1*p>S(@V9^SK51!+^OAcU1%0s66wQx++q{Z)$uFd$f`+4g@=G~cQJd`0J3D_19Uw95#epqxyg;DyQMkZ~nN{G# z$SH7qRw{7(lx;`Ug46-`G6|`J>=hDH2iB`3qzie2 zJ_)JDq))L0sb>6;gj56WB_Y*xACZu1w2w(hH5YyQEl4%grzE7B=ra;hjq^DPsb-;% z#RX`PZau;slDuLU$}^v~n4S0xOXs@`&ai{={F6?hgK>ua9cS3XsWa>l`|!Y7ZSRco zv(NMY!KO$k{|{=Sp~+AYUM^dt&kajvVJ_Pavm^IJBYHfj{05ZXAd0NK;V@dZd34LB*uNlxZ=qlM3)-LB~o zo+#>9CEr+Jf3__P#xEaAc zNgf7Dfn}tz0%_SkOkr0u)ahl?qTTZB#Bmd9+cb0QJyD z)dCbi8`TPsF*>-6Qc220&ZVsA*$X9kjO|o#8tzMbgzHde;QrLQq8NXOv{;lCi|dM= ze#V_^44Rq66hG7$m)NfPbBaUBS;ca)-Nf+mG?~PtJ+l~__4x^neO>XK>5K79p16W>pF_#TJiOio=|nGk9`2*gt1-o;W~-E3DddOt=u#G>9-B+oJ2TBd#;u* zv#X>1OPgW(i0jZj&tBhm&WtCc@?qSQl!q(|zT{J}7WS>hSo^m4Ka_t9rJv9IX)^=< z1$Zz;$3y`LUIqS(ip9Of;_lQEwCWLV4b21kF|ibtKM1fisg4Ou+7D>Q#NDXca7-+b zt=tA{y@@I)dzwnTmls6ha(C1Z7U{a&!J_pu@7=BW!!kfydl7tkkCk@zG5Mxv&CY=+ z@7xv>?DjZR5CiviI8;C(iHfKPI%)w^i+LgODLab)Gzaq5k9=jYT4?nyv|4z^W=+Cs zEiV?2q?W3iy`1>lk0|mr-3nr+o|8SalB&5#o>w!=suw>8>k;mStR6#FYl_9HR92Vt z2=}(u6LxpcN zSdXWlbmIQ8OOnExNzbucd*ZD!C+Ws|e`?rIVSzF{I6OL#4oa7&4J zp+r1al6t;$wKSa~hil|Oe|i~L=<6_Gw>L}V5}*gW=D%GMO1@PhC)GIullGe>(ANho zT1PgmO9}0Pv&eq_;X~OC@Rt8l2^BaEn>g$d2f}m`a`I7J5-HQ6UpCtb9B#hXNo5XZ z(vj@O9`B?h!DOmZ2T3^A{9VV(jqqY^EJ+#s0~8-Qd(z*JPDA1E=WkKWgEt4od~Eiv zm_!`ZeG>^4@=;V0Dbvq5%5J8q>?AlqaQ=9;r!n4#@q6hMFzFO2Z>XNbT5RVVs+#%@ z)gGrh`peh0YeP3(shcXNz5W5Jj~!?9m#@93j?MMo(p!iC4!t{xPK6{wgU($fTZzq$O-UVBmHy4H#y6wb=Uy_{t{GHggG$QaJ~DV&GpNJ{$18(HWble+ zkez05KN-BL8Mw|LAk}LnILABpW3S`lO$mnj;5=tXwr*@Lvl>%MzzFTckU z+GB_B9xs>Qga4HHPTxIVDZdB(U2y9S-#uO}zsEA#V{3`^U0?dqa+|U@=&t1r=Zq2B zU)|oRZST;wUw5~yPfGY6g`2Gm=RE#Vhkn{gebI3_qS;$Z5Q#5-bU`blKS5sp-taZY zy>o9^w#sOgN+M;o+Gv$ZJ7u-TXq757W%a1hDupIx^%$)9Qbi|J_fnM|o^V#3P&iy8 zTqCPe*2J@ldyJhhV$A6AmrNKlu4Gtg2&d7?IicK1XN4+eho@+!*Z7%EWz!~gq}On` zVVzKM+i}CXjTk>6gg*+Iol_a#6(}29F@&fMpzAhfaLGsnQmQIg*>Jc%R2|2R8&#t3 zRg+b9p}J(kxYCkQ+FmC>RU->Yp06S|4~TrOzx$?v?mH^??E~Dmh0dq2*8Y(T0wZ@< zk-G*&?(FaW!a(=^mHWN{?t4S$Q&=zm$UOrim#D~t0wNdryB`qf{tD%OSb+Od=zIzr z>=&8)ZLD%XD!~1ffj*`vACm%nOn}ZO#c_e|uUGE>9pL_&Kp%6IkC_2JrbFkG;thfB zZ&vQ-1-QR4(8pcM#{&N}ZufH$4&Mru&v_-BbvKl~O2;;4C&FoOKVT zwX<6oXSXGx%JTe%lhIO@(gXf+?+=RmkU8$d!Ex8BxR1inXGK;+<#UQ%36(F3bx;~m zJdWuA6dP1Z&-lk(9~5_^Iqs(5xUZQb(sFdFF zkNZYY+;`1!cL&G)RK@)WhCV1hgvyAbMpiiMGjrU}gX4aq;{G?t`L|~0-vvAWO*#Js zhCW5@4~l!x9QROg+`m-ZKZ2YeH9HSQ0z0H?Bz5~#35GsJRe;KOrK&+`=*;TDaZgfl zYX&(#+3ft3VCM~#^Lk!G&plxhI-i2$P#Fsjhx4HFIZAOFK37F<5)iqOzx#6n-M3Zl zTLrjp37t=2`Tmic2S)C!B6kdk+`->{yFmB7l=~h5?k|GQr?9Smk@?oCP`U3D;Qo?8 zA0^7ipa365(D|e|Akh6V<$g$j`^y7;j8#5H`KNKEpNnvK1XMn~9nQK6O2ctJ4$}cw zps6aQtNr6n3X1!0bKGl# z%*4@n){&KZLK4LTjd1u6rPrQy#Gs-EsDzN|4PTZEB`$fVsH9H}NV=wf(#Jt%Y`t)} zI#d^xTy4&{DwIJLRaSaKMYW*xt0<-_ssk(Si1sYQnb7&9eFjv%X`c>dP}-*|eYvzj zyQRu4A9jAZHHWTTZrQxf=PLJURCB}Orb?%Uz6uY}_#)a_h3*&-x&w4R-PsPRa#_hI zZEaNKw5-ZxceYY`Ewfa2c7f7wEqkk^FNT#LuO86(WOk8?Y|gB!(wEB&%T=Pn4+;oh z1f37F0Z{p5R;VJIGwZALrp&HXnGJ`XADE%g`D8W(Dxb_Q4~#rPMZPK^@)&>jqXONR zDfia~xS#6peu{E$<~mvFOno=zKD}O+_|mc8k)N%M3@!BP#sTfbb7O=fi9-K+HFG7D!d zgVK-LT9x#pu<~QJ8akiMR;tM6%$6&Cxy-=KR^itNgntq`A7+n3Wz38&_|HP=SNLWX z`MH3|8~xoQ`&X5Z?EyZvLg$nHi~jDzS+7Cqm;Ejk`Hg_cJN(@v`wx|mJ+Sl1aJQd} zaQGdlfrS7srG2ggQ z2k@w;@=CzaX9+F;l+T7LXbEFVZ%Da5l!lZArUO!Lu2OCWL!TvVqT-rSHd1;+UM-+B z5h15zHRQXT_CpS(t? zxMq}BD!n1E@lYD_nti4P#RL6f$4yhZ&oSK zhhe$A&}^D(>ze=O37ze;DlipmKh|Yv_5J^)qxn1^)zOQVguBTT$g;jvgr?70Od(wkPazRD~KJMHw~K^}+BC$l`Le30j=$mYzV zN^i=nsmiR8DS8Ed_IZwfbm8wkoYf3U!zuDyOlu6%Ka#apDYf*En;#UnjX7@H;J6p5 zxLsiAvk;x2@>z(EQ2F$JIIBC91{6Io9e|=xrPRki?j=ES`# zYXPPM@~WMex^SJE=P~r0MNfgwr(;ios$4m3`4o2oR6akq#)GSvid-ik@|phb&j@rc zl>52??i0}Y6lVEHK07dSGZndUK;(x0?i&QUZ=>871h_vRI-kN?_(wi3Fmfjq`GSDR z?fu=i4Rn98a^F3`eK+WQ3hUw*nQzhhDfhht-1iFfahdXQX@HM`(D|g;KhXV9<$iF0 z`;tH(W0a4P0Y0vP&L_p;f$k?N_u~TGj}7#3o$@i&KaDAVF2do-Q2Cr!!dcftX*dm* zVLIS6c%w>bmVewCL2>7r@dgO865Xr6?a#V^WA3W?*%*mOgaA;hCW5@4T}4@Iqnz1 zalch@_XRos&g}gAVCM&w^8+ySDeC8-xQEPf4+qCRs^T6AavrjbZ6C&TK-<^0)IFis z(0fk^oln6hL1k>saQFnMe2!AOCsdK^1Vld5-~AbZ?uBw+H^6-YI-kNU|Hx+tMsB7e zHx7v0(BFN7K=-Yb`||_bw}8&4u=D&P^Q}_{<-Toz`__RzE>b?a1o-F#ollA#1KnSu z-1iJ{-#ySrk@C^sKaGBVF2dnHQ2F$BIO|d<4OgH+m<~7;hpCi?_{Y6GDDH4`+!4WX zC#tyPVCb_VW1;dn%tu4zi((R#1{9Mq9e|=trF5--+^IovZ!pK5794lJihCmreNfDX z%7}t4#y6Sc-W(ivp^AHZkn=mu&hH9#zC<}+3`3uy76rv!YL5F*aNJcY?(!h#tIf{W z1UvslIseIP=(%qF0G&_4-$7+u#c=o=sDd6D?NfT~(M%`)@jy810F>zspZd!3pDO9! zVWsuIC+Wk``DAubMK(V)`c>)6Wrizm<#_5^Um@-vJ{vlp@L{Nez#R1tAI_?Ro&CU^ ztTHn==ziUoJDWX?qpEO+ffo(D^WH36)P~ z`6{wGv*t=)F0*h}2PplRbyrDug_R$(&d~W}cA<)F&g=rEFP9mZU8=$l2nb&Yoe#6V zQ2Aum8!F$g0Q7<~=#C2@Z&Kd-zAJ8jQMZ;j_2ecGApR@-<<(qa1ltF11D}A}N zL3^^wZ3684avKMoPi|wO^383uif!(MkxFmMtxV;1E$sYqn+lyzCrp9Lm^R(s+yJHD zip^1xX9h%`?(ZICZ&N;Q4)8G_I-l(4`nwNj-43N+_V=jBcLqdW;O`#UFH=4q3h=Q6 zI-l$x@N*vy-w#z#$KI#(<+>uAwH!*n!q=&!AA^-&!>obM*cIXMDizt>uPcxjzhe=zhxc?c?>lz)RN2;~8#H>CV0l!lc5!gN5&RT8PY^NI=IyzmC!z`U}Q z-jG*SC=Gd4!*oDir>neb!O#cg$x!*AJQ1oOlr@#!kaBG(4Jn_2>420im2xf&ee#N` zxaO{`qx6Qn;!qm$N?W41M0a>)iV`_K1ol3$~WoBPzEJE zQRxjyUk{}r=`u_QBt2IpJsXBTi!c)^V?A`AJI@?~4((HUyu=AIc^UYpE&l9odq4Ozt6I8}k42L&BB^ys` zEc&(*|D0ooiu`Io(Px4>+d;h}UdpPSmC=G}E_m~bi+<#Lk{o)^Ye^A_m=D3G~<7OvQcWj}gFN(kX zQ#ulqQVv`iP*lKl0E**OO4VTKb6`|~%IClcXB}^jTQfNBnJR8=82WU@X;As3R12!0 zi^R!FU+!2AXPpJ50aYDL2cW8}QjWvWC$Bse*L(+&tMrDv>OpD9t3IX!^2%3vod-i7 zl+B>>Nx2DBK`0w3y&>iEp){o264L=GU#L><07IX=+Nro^lx>vWkXI)t4S99ObU z3+sfk!r56(3eUn=BODH&Q%H9zG=!Zm`txlMgc|eON(|XfXG_=EB~5b`4Z)RP#M>=4-`JcOA#O&0fusb?5tr- zK09l;3V6AHz{~ss4)O_DBb%3blN0nM88myV6MUO9Zl^ITJLhF7=e)urt@N{Se94%J z;|7;rGU6J3U$t{@B;Qc;j8bcGZUoA3cs*1dO2gD+oAHltUCJxXZ+9^_bLi+!b<>!ol31$ zASt{K)!$Kg)oY{q&?&qFD<2Bs?A<}iJ$_0$VEd3021AEWTgtZkr>#cP?V-$%Pj zIT#JQ4y7YUj2eN1P&1Xke>#%9Oc*y}^e{~&e}xojbQqXQqwPSSG+IMZ&OrgU2^?&O z13Ij>3_OvK-xmj-5X#QV&VFg&NhD`)b;fPZxZN3FcE(qn@l|Jh%^6>J#vRVM(;44z z#y6euEoa>2jBh*RJI?s7GwycA_ndK$GrsSPA2{QO&bZeZKXS&8o$(WA{L~pgbH>k| z@e61Cl1Dm{pBotJRXQv*i{5}nZ&#k^Tmt@Z$Q=Q>FbMwXkUKi?WF{CYk_5AyF~=Dz zI%8#Ltm=%_o$)wltm%v=I^)UCSj!ntbH>`v_%CNXi$}`*@W4=e{cL)tb8f)0=i;^H z@-!VO3bh|IM89@QGZ?Le5%tEZB3a?;BH0^{I+6b4jO(2731@uD8J~7W+Zi`F<0fZ( z-WfMLrb~n{NT^v)$O5vSlm%q1=ftzKo>m2{ zLE!P-afkv~wgW7@syI~WzO^uyus+UM=}qbBAlDU#aPQr70-t>~l37`6S%cRghNe{n z{95uY>d(;fG3J*__z=l{t3-C-t`gaSZ)ZdbuRjzSn52$HQ4WX=+q?(^uJr$8oIBL`s?e+sNTq3)MzZIQhxO%86pWQ>DYNJm%<-8GH^7}Pu z+kU~0x91Oy3~Y-(E*ZKYzv!DK_P+ZbD;hF!@Rh}5E+0B^{NNJ&HIj1j;F7W9CyW_g zDn^xz#|6D;)c8q*i>^MmX;H7zk)2cj#YTcfW;`LCd7pA^k)ICjFs>D3>qzP9@Q>OWU6i`)>IjvZ!3W=G~k zZj8*suD3>RgOi1kJ0o{T?u$GSc`&jhvNZBg8=^C!v!b)3^P{&$?}*+Ry(@Z8^xo)w z(M8e4DCVK)!_h~g%TUzH=&I=I=%dlcqHCk;qEANGN1u*96SbqyMmIz^MmI&Di#{KH zA-XxbCHi9YB_P-i2(Lw7kM4}V5q&edEBa1!cXUtmgXrGq$I(xtpGUup{x|w{^qc5+ z(I28eM)ya5i5`gl8vQMLFnT!pzvv&)Kch#ZWwB|o>9HBH(?hjGwaUtH6dd1X@R(6! z8;lsTWnxbF=+RIpJJe=qX~~2J4IAE?9mb#L#Avq3VVgfM zWkLIgZA!1^nF?%kDg8BT&wp$)ehSawnul0phIkAhunpRg{;P!lv%?3{(+N=yRsSC} CCDIQ7 literal 0 HcmV?d00001 diff --git a/white_patch_detect/pe/pe.cpp b/white_patch_detect/pe/pe.cpp new file mode 100644 index 0000000..224f6c5 --- /dev/null +++ b/white_patch_detect/pe/pe.cpp @@ -0,0 +1,269 @@ +#include "pe.h" + +#include +#include + +pe64::pe64(std::string binary_path) { + this->path = binary_path; + + if (!std::filesystem::exists(binary_path)) + throw std::runtime_error("binary path doesn't exist!"); + + std::ifstream file_stream(binary_path, std::ios::binary); + if (!file_stream) throw std::runtime_error("couldn't open input binary!"); + + this->buffer.assign((std::istreambuf_iterator(file_stream)), + std::istreambuf_iterator()); + + file_stream.close(); + + std::vector temp_buffer = buffer; + + PIMAGE_DOS_HEADER dos = + reinterpret_cast(temp_buffer.data()); + + if (dos->e_magic != 'ZM') + throw std::runtime_error("input binary isn't a valid pe file!"); + + PIMAGE_NT_HEADERS nt = + reinterpret_cast(temp_buffer.data() + dos->e_lfanew); + + if (nt->FileHeader.Machine != IMAGE_FILE_MACHINE_AMD64) + throw std::runtime_error("huoji doesn't support 32bit binaries!"); + + this->buffer.resize(nt->OptionalHeader.SizeOfImage); + + memset(this->buffer.data(), 0, nt->OptionalHeader.SizeOfImage); + + auto first_section = IMAGE_FIRST_SECTION(nt); + + memcpy(this->buffer.data(), temp_buffer.data(), 0x1000); + for (int i = 0; i < nt->FileHeader.NumberOfSections; i++) { + auto curr_section = &first_section[i]; + + memcpy(this->buffer.data() + curr_section->VirtualAddress, + temp_buffer.data() + curr_section->PointerToRawData, + curr_section->SizeOfRawData); + } + this->buffer_not_relocated = temp_buffer; +} +bool pe64::delete_section(std::string section_name) { + PIMAGE_SECTION_HEADER section = get_section(section_name); + PIMAGE_NT_HEADERS nt_headers = get_nt(); + if (section == nullptr) { + return false; // Section not found + } + + // 计算要删除的节后面的节的数量 + int sections_to_move = nt_headers->FileHeader.NumberOfSections - (section - IMAGE_FIRST_SECTION(nt_headers)) - 1; + + // 如果有节位于要删除的节后面，将它们向前移动 + if (sections_to_move > 0) { + memmove(section, section + 1, sections_to_move * sizeof(IMAGE_SECTION_HEADER)); + } + + // 减少节的数量 + nt_headers->FileHeader.NumberOfSections--; + + // 更新OptionalHeader中的SizeOfImage + nt_headers->OptionalHeader.SizeOfImage -= section->Misc.VirtualSize; + + return true; +} + +bool pe64::rename_section(std::string old_name, std::string new_name) { + if (new_name.length() > IMAGE_SIZEOF_SHORT_NAME) { + return false; // New name too long + } + + PIMAGE_SECTION_HEADER section = get_section(old_name); + if (section == nullptr) { + return false; // Section not found + } + + // Clear the old name and copy the new name + memset(section->Name, 0, IMAGE_SIZEOF_SHORT_NAME); + memcpy(section->Name, new_name.c_str(), new_name.length()); + + return true; +} +std::vector* pe64::get_buffer() { return &this->buffer; } + +std::vector* pe64::get_buffer_not_relocated() { + return &this->buffer_not_relocated; +} +bool pe64::redirect_code_section(std::string new_section_name) { + PIMAGE_NT_HEADERS nt_headers = get_nt(); + PIMAGE_SECTION_HEADER new_section = get_section(new_section_name); + if (new_section == nullptr) { + return false; // 没有找到指定的新节 + } + + // 更新BaseOfCode和SizeOfCode + nt_headers->OptionalHeader.BaseOfCode = new_section->VirtualAddress; + nt_headers->OptionalHeader.SizeOfCode = new_section->SizeOfRawData; + + return true; +} + +PIMAGE_SECTION_HEADER pe64::get_section_by_rva(uint32_t rva) { + PIMAGE_NT_HEADERS nt_headers = get_nt(); + PIMAGE_SECTION_HEADER section = IMAGE_FIRST_SECTION(nt_headers); + for (int i = 0; i < nt_headers->FileHeader.NumberOfSections; i++, section++) { + if (rva >= section->VirtualAddress && rva < section->VirtualAddress + section->Misc.VirtualSize) { + return section; + } + } + return nullptr; +} +bool pe64::set_section_readonly(std::string section_name) { + PIMAGE_SECTION_HEADER section = get_section(section_name); + if (section == nullptr) { + return false; // 没有找到指定的节 + } + + // 清除可写和可执行的属性 + section->Characteristics &= ~(IMAGE_SCN_MEM_WRITE | IMAGE_SCN_MEM_EXECUTE); + + // 设置只读属性 + section->Characteristics |= IMAGE_SCN_MEM_READ; + + return true; +} + +PIMAGE_SECTION_HEADER pe64::get_section_header() { + PIMAGE_NT_HEADERS ntHeaders = this->get_nt(); + // NT头后面紧跟着是节头，所以我们需要计算它们的起始位置 + // 计算方法是获取NT头的地址，然后加上它的大小 + // 由于OptionalHeader的大小可能不同（特别是对于PE32+格式），我们使用FileHeader中的SizeOfOptionalHeader字段 + return reinterpret_cast( + reinterpret_cast(ntHeaders) + + sizeof(DWORD) + // Signature的大小 + sizeof(IMAGE_FILE_HEADER) + + ntHeaders->FileHeader.SizeOfOptionalHeader); +} +void* pe64::rva_to_ptr(uint32_t rva) { + // 确保RVA在展开后的PE内存大小范围内 + if (rva < this->buffer.size()) { + return static_cast(this->buffer.data() + rva); + } + return nullptr; +} +// 获取重定位表的指针 +PIMAGE_BASE_RELOCATION pe64::get_directory_entry(uint32_t directoryEntry) { + PIMAGE_NT_HEADERS ntHeaders = this->get_nt(); + // 确保请求的目录项在范围内 + if (directoryEntry >= ntHeaders->OptionalHeader.NumberOfRvaAndSizes) { + return nullptr; + } + + // 获取目录项的RVA + uint32_t rva = ntHeaders->OptionalHeader.DataDirectory[directoryEntry].VirtualAddress; + if (rva == 0) { + return nullptr; // 目录项不存在 + } + + // 将RVA转换为文件内指针 + return static_cast(this->rva_to_ptr(rva)); +} +PIMAGE_NT_HEADERS pe64::get_nt() { + return reinterpret_cast( + this->buffer.data() + + ((PIMAGE_DOS_HEADER)this->buffer.data())->e_lfanew); +} + +PIMAGE_SECTION_HEADER pe64::get_section(std::string sectionname) { + auto first_section = IMAGE_FIRST_SECTION(this->get_nt()); + + for (int i = 0; i < this->get_nt()->FileHeader.NumberOfSections; i++) { + auto curr_section = &first_section[i]; + if (!_stricmp((char*)curr_section->Name, sectionname.c_str())) + return curr_section; + } + + return nullptr; +} + +uint32_t pe64::align(uint32_t address, uint32_t alignment) { + address += (alignment - (address % alignment)); + return address; +} + +PIMAGE_SECTION_HEADER pe64::create_section(std::string name, uint32_t size, + uint32_t characteristic) { + if (name.length() > IMAGE_SIZEOF_SHORT_NAME) + throw std::runtime_error( + "section name can't be longer than 8 characters!"); + PIMAGE_FILE_HEADER file_header = &this->get_nt()->FileHeader; + PIMAGE_OPTIONAL_HEADER optional_header = &this->get_nt()->OptionalHeader; + PIMAGE_SECTION_HEADER section_header = + (PIMAGE_SECTION_HEADER)IMAGE_FIRST_SECTION(this->get_nt()); + PIMAGE_SECTION_HEADER last_section = + §ion_header[file_header->NumberOfSections - 1]; + PIMAGE_SECTION_HEADER new_section_header = nullptr; + new_section_header = + (PIMAGE_SECTION_HEADER)((PUCHAR)(&last_section->Characteristics) + 4); + memcpy(new_section_header->Name, name.c_str(), name.length()); + new_section_header->Misc.VirtualSize = + align(size + sizeof(uint32_t) + 1, optional_header->SectionAlignment); + new_section_header->VirtualAddress = + align(last_section->VirtualAddress + last_section->Misc.VirtualSize, + optional_header->SectionAlignment); + new_section_header->SizeOfRawData = + align(size + sizeof(uint32_t) + 1, optional_header->FileAlignment); + new_section_header->PointerToRawData = + align(last_section->PointerToRawData + last_section->SizeOfRawData, + optional_header->FileAlignment); + new_section_header->Characteristics = characteristic; + new_section_header->PointerToRelocations = 0x0; + new_section_header->PointerToLinenumbers = 0x0; + new_section_header->NumberOfRelocations = 0x0; + new_section_header->NumberOfLinenumbers = 0x0; + + file_header->NumberOfSections += 1; + uint32_t old_size = optional_header->SizeOfImage; + optional_header->SizeOfImage = + align(optional_header->SizeOfImage + size + sizeof(uint32_t) + 1 + + sizeof(IMAGE_SECTION_HEADER), + optional_header->SectionAlignment); + optional_header->SizeOfHeaders = + align(optional_header->SizeOfHeaders + sizeof(IMAGE_SECTION_HEADER), + optional_header->FileAlignment); + + std::vector new_buffer; + new_buffer.resize(optional_header->SizeOfImage); + memset(new_buffer.data(), 0, optional_header->SizeOfImage); + memcpy(new_buffer.data(), this->buffer.data(), old_size); + this->buffer = new_buffer; + + return this->get_section(name); +} +uint64_t pe64::get_image_base() { + PIMAGE_NT_HEADERS ntHeaders = this->get_nt(); + return ntHeaders->OptionalHeader.ImageBase; +} + +void pe64::save_to_disk(std::string path, PIMAGE_SECTION_HEADER new_section, + uint32_t total_size) { + uint32_t size = this->align( + total_size, this->get_nt()->OptionalHeader.SectionAlignment); + + uint32_t original_size = new_section->Misc.VirtualSize; + new_section->SizeOfRawData = size; + new_section->Misc.VirtualSize = size; + this->get_nt()->OptionalHeader.SizeOfImage -= (original_size - size); + + std::ofstream file_stream(path.c_str(), + std::ios_base::out | std::ios_base::binary); + if (!file_stream) throw std::runtime_error("couldn't open output binary!"); + + if (!file_stream.write((char*)this->buffer.data(), + this->get_nt()->OptionalHeader.SizeOfImage)) { + file_stream.close(); + throw std::runtime_error("couldn't write output binary!"); + } + + file_stream.close(); +} + +std::string pe64::get_path() { return this->path; } diff --git a/white_patch_detect/pe/pe.h b/white_patch_detect/pe/pe.h new file mode 100644 index 0000000..880f306 --- /dev/null +++ b/white_patch_detect/pe/pe.h @@ -0,0 +1,50 @@ +#pragma once +#include +#include +#include + +class pe64 { +private: + + std::vectorbuffer; + std::vectorbuffer_not_relocated; + std::string path; + +public: + + pe64(std::string binary_path); + + bool delete_section(std::string section_name); + + uint32_t align(uint32_t address, uint32_t alignment); + + bool rename_section(std::string old_name, std::string new_name); + + std::vector* get_buffer(); + + std::vector* get_buffer_not_relocated(); + + bool redirect_code_section(std::string new_section_name); + + PIMAGE_SECTION_HEADER get_section_by_rva(uint32_t rva); + + bool set_section_readonly(std::string section_name); + + PIMAGE_SECTION_HEADER get_section_header(); + + void* rva_to_ptr(uint32_t rva); + + PIMAGE_BASE_RELOCATION get_directory_entry(uint32_t directoryEntry); + + PIMAGE_NT_HEADERS get_nt(); + + PIMAGE_SECTION_HEADER get_section(std::string sectionname); + + PIMAGE_SECTION_HEADER create_section(std::string name, uint32_t size, uint32_t characteristic); + + uint64_t get_image_base(); + + void save_to_disk(std::string path, PIMAGE_SECTION_HEADER new_section, uint32_t total_size); + + std::string get_path(); +}; \ No newline at end of file diff --git a/white_patch_detect/white_patch_detect.cpp b/white_patch_detect/white_patch_detect.cpp new file mode 100644 index 0000000..0a2ef7b --- /dev/null +++ b/white_patch_detect/white_patch_detect.cpp @@ -0,0 +1,356 @@ +锘// white_patch_detect.cpp : 姝ゆ枃浠跺寘鍚 "main" 鍑芥暟銆傜▼搴忔墽琛屽皢鍦ㄦ澶勫紑濮嬪苟缁撴潫銆 +// + +#include +#include +#include + +#include "pe/pe.h" +#include "capstone-master/include/capstone/capstone.h" +#include "capstone-master/include/capstone/x86.h" +#include + +#pragma comment(lib, "capstone64.lib") +struct _functionDetail { + uint64_t start_address; + uint64_t end_address; + size_t size; +}; +csh capstone_handle; +auto calculateEntropy(void* data, size_t size) -> double { + if (data == nullptr || size == 0) { + return 0.0; + } + + unsigned char* byteData = static_cast(data); + std::unordered_map frequencyMap; + + // 璁＄畻姣忎釜瀛楄妭鐨勯鐜 + for (size_t i = 0; i < size; ++i) { + frequencyMap[byteData[i]]++; + } + + double entropy = 0.0; + for (const auto& pair : frequencyMap) { + double probability = static_cast(pair.second) / size; + entropy -= probability * std::log2(probability); + } + + return entropy; +} +auto Init() -> bool { + bool status = false; + do { + // 鎵撳紑鍙ユ焺 + if (cs_open(CS_ARCH_X86, CS_MODE_64, &capstone_handle) != CS_ERR_OK) { + break; + } + cs_option(capstone_handle, CS_OPT_DETAIL, CS_OPT_ON); + cs_option(capstone_handle, CS_OPT_SKIPDATA, CS_OPT_ON); + + status = true; + } while (false); + return status; +} +auto buildFunctionMaps(pe64* pe) -> std::vector> { + std::vector> functionList; + cs_insn* insn = nullptr; + size_t disasmCount = 0; + + do { + + auto textSection = pe->get_section(".text"); + const auto codeAddressInMemory = reinterpret_cast( + pe->get_buffer()->data() + textSection->VirtualAddress); + + disasmCount = + cs_disasm(capstone_handle, + reinterpret_cast(codeAddressInMemory), + textSection->Misc.VirtualSize, 0, 0, &insn); + if (disasmCount == 0) { + break; + } + std::vector backTrackCodeList; + bool isEnterFunction = false; + bool isFirst = true; + size_t currentFunctionSize = 0; + uint64_t currentFuncAddress = 0; + size_t offset = 0; + + for (size_t index = 0; index < disasmCount; index++) { + const auto code = insn[index]; + const auto codeMnemonic = std::string(code.mnemonic); + const auto opCode = std::string(code.op_str); + if (backTrackCodeList.size() > 3) { + backTrackCodeList.erase(backTrackCodeList.begin()); + } + backTrackCodeList.push_back(codeMnemonic); + if ((codeMnemonic != "int3" && codeMnemonic != "nop") && + ((backTrackCodeList.size() > 2) && + (backTrackCodeList[0] == "int3" || + backTrackCodeList[0] == "nop") && + (backTrackCodeList[1] == "int3" || + backTrackCodeList[1] == "nop") && + (backTrackCodeList[2] == "int3" || + backTrackCodeList[2] == "nop")) && + isEnterFunction == false) { + // printf("杩涘叆鍑芥暟 寮濮嬪湴鍧: %llx\n", codeAddressInMemory + offset); + // printf("address: 0x%llx | size: %d code: %s %s \n", + // code.address, code.size, code.mnemonic, code.op_str); + currentFuncAddress = codeAddressInMemory + offset; + isEnterFunction = true; + backTrackCodeList.clear(); + } + else if ((codeMnemonic == "int3" || codeMnemonic == "nop") && + ((backTrackCodeList.size() > 2) && + (backTrackCodeList[0] != "int3" && + backTrackCodeList[0] != "nop")) && + isEnterFunction) { + //printf("閫鍑哄嚱鏁 缁撴潫鍦板潃: %llx 褰撳墠澶у皬: %d \n", codeAddressInMemory + code.address, currentFuncAddress - codeAddressInMemory); + + auto func = _functionDetail{ .start_address = currentFuncAddress, + .end_address = codeAddressInMemory + code.address, + .size = (codeAddressInMemory + code.address) - currentFuncAddress }; + functionList.push_back(std::make_shared<_functionDetail>(func)); + //printf("閫鍑哄嚱鏁 缁撴潫鍦板潃: %llx 褰撳墠澶у皬: %d \n", func.end_address, func.size); + + isFirst = false; + isEnterFunction = false; + currentFunctionSize = 0; + currentFuncAddress = 0; + } + currentFunctionSize += code.size; + offset += code.size; + } + if (isFirst) { + functionList.push_back( + std::make_shared<_functionDetail>(_functionDetail{ + .start_address = static_cast(codeAddressInMemory), + .end_address = static_cast( + codeAddressInMemory + textSection->Misc.VirtualSize), + .size = textSection->Misc.VirtualSize })); + } + } while (false); + cs_free(insn, disasmCount); + return functionList; +} +class super_huoji_tracker +{ +public: + auto print_asm(const cs_insn* code) -> void; + super_huoji_tracker(uint64_t startAddr, size_t sizeOfCode, uint64_t current_function_rva); + ~super_huoji_tracker(); + auto track_gs_access() -> void; + +private: + std::vector> ins_list; + cs_insn* insn = nullptr; + size_t disasmCount = 0; + csh capstone_handle_i; + uint64_t ins_ip, ins_ip_address, current_function_rva; + auto get_next_ins()->std::shared_ptr; + template + auto match_code(T match_fn, B process_fn, std::optional num_operands, std::vector> operand_types) -> bool; +}; +auto super_huoji_tracker::print_asm(const cs_insn* code) -> void { + printf("0x%08X :\t\t%s\t%s\t\n", code->address, code->mnemonic, + code->op_str); +} +super_huoji_tracker::super_huoji_tracker(uint64_t startAddr, size_t sizeOfCode, uint64_t current_function_rva) +{ + if (cs_open(CS_ARCH_X86, CS_MODE_64, &capstone_handle_i) != CS_ERR_OK) { + __debugbreak(); + } + cs_option(capstone_handle_i, CS_OPT_DETAIL, CS_OPT_ON); + cs_option(capstone_handle_i, CS_OPT_SKIPDATA, CS_OPT_ON); + + do + { + disasmCount = + cs_disasm(capstone_handle_i, + reinterpret_cast(startAddr), + sizeOfCode, 0, 0, &insn); + if (disasmCount == 0) { + break; + } + for (size_t index = 0; index < disasmCount; index++) { + const auto code = insn[index]; + this->ins_list.push_back(std::make_shared(code)); + } + } while (false); + this->current_function_rva = current_function_rva; +} + +super_huoji_tracker::~super_huoji_tracker() +{ + if (insn) { + cs_free(insn, disasmCount); + } +} +auto super_huoji_tracker::get_next_ins() -> std::shared_ptr { + if (this->ins_ip >= this->ins_list.size()) { + return nullptr; + } + const auto result = this->ins_list[this->ins_ip]; + this->ins_ip++; + this->ins_ip_address = result->address; + return result; +} +template +auto super_huoji_tracker::match_code( + T match_fn, B process_fn, + std::optional num_operands, + std::vector> operand_types) -> bool { + while (auto instruction = get_next_ins()) { + if (&process_fn != nullptr) { + process_fn(instruction.get()); + } + if (num_operands) { + if (instruction->detail->x86.op_count != *num_operands) continue; + bool operand_type_mismatch = false; + for (uint32_t i = 0; i < *num_operands; i++) { + auto& target_type = operand_types[i]; + if (target_type && + target_type != instruction->detail->x86.operands[i].type) { + operand_type_mismatch = true; + break; + } + } + if (operand_type_mismatch) continue; + } + if (match_fn(instruction.get())) return true; + } + return false; +} + +auto super_huoji_tracker::track_gs_access() -> void +{ + //const auto matched_gs_access = match_code([&](cs_insn* instruction) {}, [&](cs_insn* instruction) {}, {}, {}); + const auto isGsRegAccess = match_code([&](cs_insn* instruction) { + //@todo: other access gs reg code... + if (instruction->id != X86_INS_MOV && instruction->id != X86_INS_MOVZX) { + return false; + } + + if (instruction->detail->x86.operands[1].mem.segment != X86_REG_GS) { + return false; + } + /* + gs:[0x30] TEB + gs:[0x40] Pid + gs:[0x48] Tid + gs:[0x60] PEB + gs:[0x68] LastError + */ + if (instruction->detail->x86.operands[1].mem.disp != 0x30 && instruction->detail->x86.operands[1].mem.disp != 0x60) { + return false; + } + return true; + }, [&](cs_insn* instruction) {}, {}, {}); + if (isGsRegAccess == false) { + return; + } + const auto currentIns = this->ins_list[this->ins_ip - 1].get(); + const auto gsAccessReg = currentIns->detail->x86.operands[0].reg; + x86_reg ldrAccessReg; + bool isPebAccess = false; + if (currentIns->detail->x86.operands[1].mem.disp == 0x30) { + //浠嶵EB璁块棶鐨凱EB->ldr + isPebAccess = match_code([&](cs_insn* instruction) { + //@todo: other access gs reg code... + if (instruction->id != X86_INS_MOV && instruction->id != X86_INS_MOVZX) { + return false; + } + + if (instruction->detail->x86.operands[1].mem.base != gsAccessReg) { + return false; + } + if (instruction->detail->x86.operands[1].mem.disp != 0x60) { + return false; + } + ldrAccessReg = instruction->detail->x86.operands[0].reg; + return true; + }, [&](cs_insn* instruction) {}, {}, {}); + } + else { + //鐩存帴璁块棶鐨凣S->peb + isPebAccess = true; + ldrAccessReg = gsAccessReg; + } + if (isPebAccess == false){ + return; + } + //璁块棶浜哖EB鐨刲dr + const auto isPebLdrAccess = match_code([&](cs_insn* instruction) { + //@todo: other access gs reg code... + if (instruction->id != X86_INS_MOV && instruction->id != X86_INS_MOVZX) { + return false; + } + if (instruction->detail->x86.operands[1].mem.base != ldrAccessReg) { + return false; + } + if (instruction->detail->x86.operands[1].mem.disp != 0x18) { + return false; + } + return true; + }, [&](cs_insn* instruction) {}, {}, {}); + if (isPebLdrAccess == false) { + return; + } + printf("mawlare function detected at address: 0x%llx by gs access peb->ldr \n", this->current_function_rva); + this->print_asm(currentIns); +} +auto functionAnalysis(std::vector> functionlist, pe64* peFileObject) -> void { + double maxEntropy = -1.0; + uint64_t maxEntropyAddress = 0; + + for (auto& func : functionlist) { + + auto entropy = calculateEntropy(reinterpret_cast(func.get()->start_address), func.get()->size); + + if (entropy > maxEntropy) { + maxEntropy = entropy; + maxEntropyAddress = func.get()->start_address - reinterpret_cast(peFileObject->get_buffer()->data()); + } + auto tracker = new super_huoji_tracker(func.get()->start_address, func.get()->size, func.get()->start_address - reinterpret_cast(peFileObject->get_buffer()->data())); + tracker->track_gs_access(); + delete tracker; + } + if (maxEntropy > 7.0f) { + printf("mawlare function detected at address: 0x%08x + 0x%llx = 0x%llx entropy %f \n", maxEntropyAddress, peFileObject->get_image_base(), (peFileObject->get_image_base() + maxEntropyAddress), maxEntropy); + } +} + +int main() +{ + const std::string filePath = "z:\\huoji.bin"; + pe64* peFileObject = NULL; + do + { + if (Init() == false) { + break; + } + try { + srand(time(NULL)); + peFileObject = new pe64(filePath); + } + catch (std::runtime_error e) { + std::cout << "Runtime error: " << e.what() << std::endl; + break; + } + if (peFileObject == nullptr) { + break; + } + auto functionlist = buildFunctionMaps(peFileObject); + if (functionlist.size() == 0) { + printf("functionlist.size() == 0 \n"); + } + printf("functionlist size: %d \n", functionlist.size()); + + if (functionlist.size() > 0) { + functionAnalysis(functionlist, peFileObject); + } + + } while (false); + return 0; +} diff --git a/white_patch_detect/white_patch_detect.vcxproj b/white_patch_detect/white_patch_detect.vcxproj new file mode 100644 index 0000000..cfee0a1 --- /dev/null +++ b/white_patch_detect/white_patch_detect.vcxproj @@ -0,0 +1,168 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + 16.0 + Win32Proj + {a54c53b1-63c5-405c-9bb6-6426f1b9d00b} + whitepatchdetect + 10.0 + + + + Application + true + v142 + Unicode + + + Application + false + v142 + true + Unicode + + + Application + true + v142 + Unicode + + + Application + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + true + + + false + + + true + F:\project\white_patch_detect\white_patch_detect\libs;$(LibraryPath) + + + false + + + + Level3 + true + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + + + Console + true + + + + + Level3 + true + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + + + Console + true + true + true + + + + + Level3 + true + _DEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + stdcpplatest + + + Console + true + + + + + Level3 + true + true + true + NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + true + + + Console + true + true + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/white_patch_detect/white_patch_detect.vcxproj.filters b/white_patch_detect/white_patch_detect.vcxproj.filters new file mode 100644 index 0000000..a065cd7 --- /dev/null +++ b/white_patch_detect/white_patch_detect.vcxproj.filters @@ -0,0 +1,81 @@ +锘 + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;c++;cppm;ixx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;h++;hm;inl;inc;ipp;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + {86e1cecb-2a9f-4b6b-8f48-7404332f3c00} + + + {a77cfa70-f90d-4ed8-9120-a2fbb4bbe2c8} + + + + + 婧愭枃浠 + + + 婧愭枃浠禱pe + + + + + 婧愭枃浠禱pe + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + 婧愭枃浠禱capstone + + + \ No newline at end of file

      P7#ZB(pa5Jm!tYQK=mPnNegm7}3^wWR1UB4=kU^q`O}fVhHjx|M{tMj} zu>C`A7qCsV!gdixhRu~AU^62aP!T8&hcIA!%o%Lb-3e^?G%tfh4V!e24QwJex*d;h z3)qTN+XZZoTVX2!Bg1wH6zn!LLP@9yREGRR@3tqL!6x0Ez=n^+GDy_0N%z>mCUT?O zWzlT`TRCdGfbB^uY~^8O*eXB)Y-WUtP!XsK`GG7#Ygs5sn6{-M`C)7jdkyOXu!EmQ)Knv$ZKy61#34Ww1H~7GupzC`aG=_dD=n2;bt5{bqK$hI!koO z;jayc6GZ)~)&IN4GKl`yA=LLZ{0q@zrEm}YvZkm3&Fg^X39LF%7X?-?Sh2bVM#ic$ z6kugW=mOOit6O16o$be}D-@)=4TmtWdQo7de|u2;#s~ezgLIGJ?Li&O{w`8E8eVVv z+u7liu4YK&rK@B8PfAx1E6{cQ22;DI=pEI|tRs5{a@`Jc2`=A3EE8OwW99OlFfx~W zLjjisXozqZR9i0J4MXZ&KbQMJ!Q_58gu&%`&bTbyW5eZeN>>Au9&zdFSP^qMoYK`~ z^p~!uq}ts9mqpzmR~E=6xO^|MOmO)nE0+hr$Xw2b0xp{o212#v@*o&e=li)l7z)zm z;Sh?;xRdy@GcHT_*l;=XV23(eP>#uV(--2u=xnD*_Xz0r zFJ8ffQ@Wbn{*^~ix;j?GJ0+abH9JMR$6%+(#8K}Q>F#8w;Pa6P0)meM!NpD)LrfPt zs|g-?>FQWfmLBzHkt=tyS@6yxf`H?* zz;UrzW)s=PW?5q0EHA>yn`I6ZY!)-ZT&M{23i*fLEK8kj7U>?F%@R)OYJ#UnT)H|| z#Ec84bTz^KrN`hJOx7LsPLb|Tb_(vGiy$EQA`o2cl*Pn!u~U{=cghkNd8aIef}LVU zSO(Sh)Bkc9QkT=tK%Ny)a9D*ysQrX}yh7|JeTURnSAKVWhZOGq&vW>t7+Hh<&aj%y ze)kCWv^tjk#*iOKZSM?=($VeJ=(YfN4Ygf>`!1K!Gr}8C5$G-Q4{;g< zY%86?Cf%LDhU+C6Bx=~Cdu(76xzX*n(QN_SJJfao+bSz;8)0PFHbDVwW`xa95ojCv zhlXvnGuWiN6WB`DNtZ#QhE2N11~!o!-F_F{7O=fXZ5Ob;ZiQ_Jj11dOD1gn3@IF)o z+D-nUVO!%2HtFsJHoT3FxwvyaUQ0QG+YpV*{?pjc)Hpw*|NdsO0xANXCjZc|z3mJ(>FxwJyaUQ0QNt$PV*{JWjc%Vow*_ox zsqF%`4OZB`hmm3X0SaIA%j!}dEAz-C7H1FG#i;GZz0ZX%eF=K>TQ{=p#(a5oEZqi(Epk4nK67|_by2plKA~(8S z8Qm7(R;9KJaCcb2tp+25TOA6(H6zr3ia@o=KlHolPG_)5cPFsn+EoUL8aC-38`wl{ zbo(-NTfpX}whP$ax5AbHBg5u{0@%z5iBJ(Jh5SRqw#yl8(%lJcxOSC6qJ~Yn#|Ac$ z8{NJf-4?K=QriV=A6Q|#5=MsYDky->jF1Kuf&N4Op<&zY3^wWR1U6i|${*cgV?Jp>c-G=YLcQyjto_akTE zN_QvV;_i(M5;eHeJvQKq+~{^QbX$OXJ+)nc`>_?=8(?H`Z-fGH%?Qn*B2X*x54|V% zI)hERJAn=FfHFwbuu1pWz$S8|+pW=U0b5&YyMXNzD{SpxWY}(k0@%z5?V%!2NAeF1 z+o#T8lkQGn!#ki15;bhnJvOk3+~{^EbX&mInc6O3`^*Yk7Z@3~TcH3pGeTFW2-Ji8 zL&LVu8En$s32b-=ltH3~O}fVhHjx|M?ul*-*lwq`3)nul!qy8$hV2e0fX$3>Csf;a zz}_&VenBuH&s|V(xCe(Yz}+vvjk>YYJvNP%x%D4k6}MmLt!S4I=;0d-8yQO}}=V(ri1@_^#PvIV*j;H~M4+i3bIztJ1L7jtE>g2%4)ENc^)G;I62Ni)vkbh|E z9CAh->F$I&xOkF5qNa{?j}3LgX`cdnqE0yNQ@97HBZ2_&`+>Ni&I1I!pw3|{bsmI~ zsq+vNP{)k$FjNE@MgF0wbHo{Sq`MR9-~vttiJCgnJvP({r+o_Si8|r5PvIV*jtBz8 zM+0#|ov{SHpw3Y%b;iNS)EN&2)G;GWfQmp*l7DFG9CJn;>F$I&xQLWNqNa{?j}3Lg zX`cdnqE0yNQ@97HBZ2_&NkCjs=V^joQ0FTvbtc2e)R_VW)G;GWg=%{tI}L`^<3ttY znGOYq890PNu&)Kdq6SyG#|B)PTYoX9K!?DU?)trbwF4)G;G0f{H-P$Uii7PCBEGbaz4> zT*%5GQBy~{$A&uLv`>LOQ74@CDcl3p5kY|Xav(0K^BO@fsB_9nos}>$byh(Eb<7B> zp(4;5baz4>T*%5GQBy~{$A&uLv`>LOQ74@C zDcl3p5kY|XHXtsjvz?$9)H!RV&U-L2b#_1jb<7Amq1s-^zEAT!>^8h264Y8@xUR!f zqH=I_(SyGpx_+1`K79Q=Q~dAsdrk4t>pide=N61|xm?#bVs$jBS*(sB^;uTOlKLL2 zUy}Mes|QHE!0JI#|6%nIsm4k(?_pBoSUo~&aaNC#T9Vacq?TdzYf{UxdVT7POK33O}n#}4(QX8|nh15~3?j&_As~?g&fz^*moyqE6 zQfIOH38^o#`WdP7Sp9<3ms#CU>MN`sBy};X7fC(Os>=iQXI4F={>Ew?seiKCgw(%T z-Arl~Ix!Kg3bv41oz?B6)?#%BsR^v^B{hZB&q%$B)qSMaV|72N4Ou-xYGYQr#6i85 z)muruj@53Y-pFcqQd_c`O==rfN053mtM`-Ii`5569l+|Nqz+6`ztj;w(m|n$((f%7F3#l$454Qr^E~ z!^AP?O1lb{mvgz+)5&e(m<`?@^wO~bSvp|)Zkk>Rw)Nygqip&Rrf#m3%2s33ff&PA zwbQGxH=H=CqH&FgnJR4S$&2)QqstFV&!&muJi7-m3)#{@SHW3tooj!f)!SPysgwRa zSyROv5$dDhP}CJy1LUGLeN1bj0)ooI@Lmiz6{SG=1WNb#R1p;Fr=-R;6)Q>=bGmyl z{24_$+H1q;;vQE)d7Q%6Q>$oQqK)gz2yJR2w5f?5Dfd2j6k0<1IjUP!{CUx6DMOYU zE>)y2FdOZ!f)pH3V$*a8#_(P2^eXH@>r554_2k9vA50TP1^cPGU>mnTsZRQNF7!(( zl%|QmmkM05wgXD#{-HSK!}sk0Mn7i?1o!0YSm$1#y(h61>NFSAI&ahDzUv(5WIcGJQ*G zd{e=nR6&mJaTq>9!=6;ZSEwhU@=2iualqBIJQ_qNnNu{?-Q7r)0~OkJcXcngh<_eq zTD3YZ!zg2vaTj+_uhysYu>9n*T#%*o6cj6`g@1ZO|P=m=BW zoZKN9!CvKr>1LR^<>zK)3<>fo4^tU8ioBCE->%8rQysp$Hhg~$pQ#C-0h?lBebkxn z(qE=6YQxXr@Goe>Kd+6kh+{0!#F!78qQrUH z@XI;;5>5D5wK3LljMvp=tWt$AjMrdNoL3C@8!&dw${Rj7-!BhI@U6BUT;f=O|T-3gPj6(7TB(~7+q z*0kaPm-K}??>=4LgZ6n3>GPiAyx(G?q7`4mq-e!gFezJc8b+H|oWZcB6+d%H=hbdd!mGiP(={+i7F)ZzPT!{>7N98LHkuqhTcNR?S!I*sJ;!!_aav@u3;j7Kyv z9)?X(;)B}o6FB@>P59B;7?U~1By|~2s6rUVV=yVWZMdhvX!8y<6~me{@+>ZCraJGl zy1Xyg=bf$3`zq&Mh=~eBUWQ4r&0m5^*^0$5+O%Q`hBd8tol9D&&bvaFca44Cwfel9 zIPV5bRJ7tPm~2}?Z^oPL^KQ}S-N|{k>w>>;AAFZS_-7n^FD5D$^^q>`KKs0%>+>Gw zya#l_kJtx4st=x0)4Xg-tXYUkh2FOkU{fr(4otQv8b)oHS`P2uKP$IY&hVkQ*Wotr zkR*tE9W~h=bg#oF?sXXM%V8`^_<}?j@s@WD7u^7}g7{yk=z6dzimnTjqUbc3I%SNs zulPzBbt}4p?KUfF45MmAEqO&ZVwP$}*TbeLyBSQ%vaf|vS9TM&Tgpbadvk4fV4kYB z+hMcR<`Fpebk00Qllf_N_(|IEb2r@Xv90 z`@YU#yIo(Gar(uY^ow9q^mQRjioU+gne8ikiS3rk4EJ&vRlDR3E_w}SsmQPzHbrGC zIkSCbE7)$S47=oAPQOKyeiLkpp1lK;qO!L+vwdZ6vfWad;oc6Ts%IZ@(YrBA)w5l& zDJt8^ne8ikkL{Mq(6jxVexD}&r?4q{wihPb%IJ#kOBhuPKgO94Ycd~Hhe!3NImQW1 zjBj95RDWC@-f*9RQC0nqocRY$=CkVXsQv=S_#N{U75=IUVHiKdBrgFh$QtgyU@TfZ z?*IOc;UJO~z5iRXmU-z|yq2=0c$jPuhDiru zOSapT+!02bk~?8oQ}XRxat};Y)YXmi+PCsnw%gRz3r3r|?!d67t^r(E7A7iMnF*7k zx+==w=vg z*0Tk}n)U4A^?ZPdilX0#Nm=v`7?$4EnO|jrhVX{RLzsv=bBwi4)XqSl_Ms+xIEluVccH!lTrJ7xMGKuh4 za`?+N;gexgEG*G3vph#6*k$I0HRR0oG@0wF!>4J(H|OxzYr;2!O|h_R)tQ@c<|5~6 z|Bbe5*lvetN3N_r<^`P|3UR3&Y>LX-z@*?(E6!|RSqrw?Ro0y=yVWjxytwz-S)IL; zI=bQR0i(?+vL}XvdQkKuSsyN`w>s|~y1e(;=grXP9m07BVxj_w0Wc|m=ns=(QycD~ zFxs>t2g90HjO3DrtMlgR@;+dn_d$K$iJW&FCMsGn1|~%-M!}?eV||qE7ET)O$6&N+ z)#Dh}wCWiyc`7C<>YB`X?f1%4Y`3ZFSr~2Vnt@?WT?@FbmoQP$%DFHpN`4V0T`ON; zyG_XpVYDgv6%1=iUd1J^z(hq|%Q&xnE0?g{rmod6+SK(rhBb9Ht7E<+r`IVovCvtx zF>H!9H-gEsoEG8~*8nEP&#iIesugE$uE~6ZI{bCo@V9XI4w~@oVN)!uojP+HZRVbw zxtk{Qt?KZdwc#^3{N0-Hy<)G2+qIdqIdgwa=6>q%eYN3pIed;L{1Dg_3mc@$ zEPwBY!w=Vl&(p>j#W5by#CRAsMTrk;!%yJwV>RJNYhz627?U(Ho`6kJ;$zzI&vN)_ zn($M!G3IcL7u01uuL@xpGhtGkR}A-D7;R32^DwMA4KC)AUQy>=pv$|&KJQX}-VL1h zO-xiE@&-(bQ|wxpl&yFNMw?b_#IU9nJGi8G)p@t-^6s?H`@TN!KF<3ICMsI-F-(e9 z?14$yiqB!RX~h>9*0kanmvmU2_n+_!Fyr(fy(TbBW*|vgiXnb#<_XmC6 zUpenjy5PUr2mf6k-0d~5G%jMIVo`tV@_M|sAjV->17a!8TLKf69V=}gyo^40RSsSW z6BUc9pvzm$K5un>UN7gZtqY!DAKa%8-i(8%7oJ%7nh-X{f*ZkP+i1gR0Fz>u(lsGx zZm!9EgF5_m+VHn<_zs%z?O{_aterY@8*S#EoVlAO^R4ReowecnaQNPu@OQwbSlI2V z%;M51i^KQTguh1{V<^WMq=}IYo1(;fwc+zQ{C%46IocTi?8YX2cX259EikTSJ zv|=8Y^rAZN3%a~7+2@_F&%2ECF2+PfD;B|I+X{L!UT&Xvg+A|E&bwL{e4TypH}t`` zaPWVbiqHc558L;ykdfRg;6e{5S0qOZ3tmDKE0Rimh^`EN*Gm*xrQrifLW@>)PqfdW?h&RJxhbha$8xVg`V8N znVV@cU#kw^L>s;%hi|V5-wrm#!rG`ax8lt9XtZFv4H}(bRH1Pj7u_ARRA_XCP0{i$ zoY}szTi9-?43PBW^ckA;ePC1c>@JuTmEFmi?JMiWc1vZ3I}1it&vLlv!I-7$*+AG7 zl?~v`_LcQ#yQMPp>=91?kS6^Duqk?WKTL|shQp-%6@WY#b?3_a*lsD?a6by8s-aKt ziY8)~s-fdyQ9Vbqmfz;;X7==Mym?HSBd)iw<_MQu}HQr7k~=eB3UB(~et zHjit25%W~Fy#Skn3D3i1TQ`AZ-N|-KW$4)fPLFT5SM_C|I{T;U==fb97>lkOztfDbX%Aj#(I23H z%OxFG=RKy&i*FFO%X?Cv*X1*>Y5&GV1w}5vqyXX%m~<5RjqMg7@ZbZVZOLv72XUfk ztIBZ6_&QltT_s@B)m4n`Hg(}UXYE>fDTXz5)#kctV4|Xx)nHPzvIbctx^rE(Vxpq1 z&Yai2E_~IRx-NWunq6HzF|4WUKCTPj_oIRs-wC8Dc_2(WhzGFUrj@xc+O#qc!nb>%v!3s9O01Op1~pgGqU1H~~gopYhcw z>h(;4(PlkUF|1k799|E;QbAQTzL!B=^h_9aML)}S8*@12_B9y>p89Fs4fNYe;^!RSbLKOe%%{}h z@o-8__&+%OubS{b!=|9;kLt|lw3*$B=2hfHP3FJV;V)>zm*Vgx5|zalgGq6Mi-Sp? z4uZD3M8$BIhS6rbm%*@RyI0|oDys9A*X6BhpSPMmZxZKCz(fU(bzoAoqBcy*RwTn{ z(~1-fYg+LiE-6i&_ex#fdiHti>+{~gd7ELPq7~P|q-aGGm~?Lv*Rb7&H8;X&)2ike z*0ibvmwXc@D(Y&>dF?O8TC?4zu8uI;)YS>Yn!4`fx^BlrMJs#4q$s&NOuANfWxGwu zy1VO&305bI=N87e0h3R2M!dJSQkda2NJr zmZA%W=L?>=6tS-C+| zn@E?#t<0ePOe5V0GF*w& zN;tbvLI+WT$J3EZX-!^PLvnH-2wJ;LYq)PRLy9`(<7S5wvk`LDe8XinW(8zd&y2yt zgLWZm!mM>cvtC!udM9YsTQqBA;1N_nc|8r?64WXYdP|VgMw%fD2sBj8+8#7(YhV^X z;YybIe$cG<0<((5`Y>qLuE4A!vGxYd+7p;nB-TDL%Z(G>en_S16zBO8QYmo~JOByU z0kK1n#ECKPFiS`L5|QB($TllC+@F&{p2d;ckDcNEf`+>d$nK9P2=lN!Ssf%(_aVcA z4e@2-f#PvkOstR6EZbI}@Xzvi&Onl9^Y8o;mHKtSGq`1j`y?5PmP%*WQ)IX)JGh`Y zI&+?;@s2q`<0$eR2F)VR(ga&V{v0&xd|*~EI>p_;z|bkDU&AIXv-7*;sQR7eeh>cz~AfxV%9%Fvn~W?1^1!2`yvcT+qg-goaL|-b%JKq3d|}JE7?EG<4%DjHk`#UKC_>ueO{ zU7x*!mua}urT2L9j&lj`iqiYKAn$8wR_mPMed&t~;{8wXYe8=f&87dupzM{Tf9oLs z7Bs8v;2eC}!FY0~cctd!ev@<$PG4EN-xB2Bfo2tMVtX1Y+(fLnYmifC+Zne9&FCR! z49>oHXi!THqZmV^(m7~&ssQ3R4cm~#aGxg2 zkfB)uR(VzyU+hAs>oa8Qb`#Ogh$Gs04bKlEQkz0!=V@$sURJl^eetOd*^C>Wzimco_C*@c7@VDfccNklRL(WeHPKbjj7o|xQw*o! zbig4$dS45vg4oJUA(eN58lGm5DhcU2NEO8?=X#cIVChDdnzPh`rIswUVyQJtZCGl{ zQahGzVyQh#H?!2iFAjqS14*7s zGa!iu#Px+F8W5MsQa_gZvve;@16Uf!(jb-wvow^Y9F~T$l*>{cOZhB~VCjCAMzZuE zOAoR1FiVfH^e9UOERAMqj48RtL6Uu$V2;I2Wa%-M9%tzZmY!s35=&39^fXJ8S(?Jq zRFtLQ?a)z#vc4f2?w(|6mD4XP@CGeDhx^})m%uDP;4g=I8nr#=E+q?p2;>_BIIFw~i!5aWBw5NkEN%2lRLVNY zHl?f)!$nJ3O{2D@yhRq8xL(#(x9Zrj+AixM(TIXw?1|QJK{s+mu;F3>QV95{)Vls6{p#1g^xm z{6ujTBy)>gPP46BBv}j>O`AxgwrO$hYXGB+-w2XK_!^d)_$69uJ;*jW>x$u`In!v= zCa2+UNS16+t1 zxK%3{3cYCpr$w+xnl6SUi(TTEsMrPMX=TKGF@N# z(hin(vh+SAv2M>U9{a#QM%8YDETGF668zjoKh#xIdNigFXVjOLsKT#eHNUj`|ns z|AZ(m5S~tC?e->O5AH$7-2lahI86adpfwj~9}> z8J7S_-i-4>5;x=G5>0DdlCa_iSzNMd^;`}~o_4Q*BzMr2ETyqjm!*0vHDIX`ON~v* zoet?TaguM!(sia3cfC0;?go}_WU09+d0Ik}`?ZxRxmyc~&ID~)y2+H{+C!2bj&EkE z14|uE$#V-N8M(75xw{Ankv(0_F;6#Ba(8EIPjk$3n<=?(XKOEW%yWk+#q~C&_`4yA z`r`YrbPr1zrWDr~lBh2})0E=+nUcG|kiaI-z2;clK$Zqc2{+URn`7}qS;{e`V#8Rv z&o2>y<00eLq|L1`4_P{Qv)l_aXxwHu8}3WV(gi=s&hM0!KOm=H`+njMu>a$U;Vwyb zdjAaEq!M>P-4#U0uHv(&|J<~e?z_1!Aw$kE@!2!rB+gszvSjN#tZ0%_G~6O@2;D-n zBq~S7ep#8V@N@3K84bTx=6C8m3^%O!4w@{kJlTe3W%X;7Gh|3cA-6JQ3clwiJxb7U z9&TsTt*-)Hsk-Ftue&SAJ96@_Tvg#5TnF8OleQWfTWvcVovv|Xjcx{t81hK3#mW>H zH{2eCo4nyR4w5`2jfW&oN$v?eHj&33=U-$2?OY$YEjiu=9mcC-?I7?r%^bJejvUI|f+$SN4)3^JSDS1vqk`0xz9n8@y`1tI#rK^?CK=XlJvV~`0>)M;-?cM$Y8ya&lmHpH}s0TAA$vEPCDz; z?-jgVRs4+qX55{B7?wE0J(^tc>j!!DgMQd-xJS`&&alkFw*n3KSaW*N?Bec6F^Us0 zel-a{c|)34uM}xIAWZ>GMsfFlagcR1aE--`!==QGj+pTXO!$%E7#u_)4T3_;vt;2{ zT$lZfx#o4*kK{*JyutT4%eafXe}e(zsH=1T{&`vXBJV()qVY=(osjo;*fH%F9D-}_ z?GZC>!Hi#FGLX(#VP5{aA;}Y}2a>$Ti-RQLkB1~rcEwmK&Qb}ME@7#pUn0;iBAea2 z@ZU6E^u0FdBKLyulkbi}!++4Q&6~Hl6fcjw@-3n!B)OtmkmQO6K$2IU*^uOw=RipE z%5#uujT=UMuRrC(V3jio%kEL~*D zc+F(C2a;TQ9FG-asRTRELCBt8cQ`;s>RY}EO}Y-v6RG83QJe8 zbR|n^EY)SH9!m{aY6MBH{2Cr>!qT-YHDl>|mTqLJ1xu}1YQs`HmfEw_fu&9?b!O>S zmb$UjgQeS8>c!HXEZxOYAC@v$%48`El3aOz9vi^YK$ZrxG?b-bEakG4&(a8%MzZuE zOAoX32ulSljb>>qOXFFZ$kO91J;~BjEKO!F&1Pv1OY>No z&(Z>xUSa7~mX@%zjHMMUtz>C6OKVtK$I^P1-ePG3OB-3*%+gkt-eu`MNOI*ncFH4`Yw2!4PSo)HsgDf3p=_pHIvGg@d-?DU)rPC~Z$I|yKonz@omVRdG zSC)Qj}_;!5786GRkW94|P zJdai6u}VBvg~zJ$Salw&!DF>}tTvC;;W00d`FJdm$C7z0g~zU7=}MN;SgOlXJ(e1< z)QF|VkR%FCcW>%hIDPje;b5KbptJ z^4K^Yo4{iedF*kPo@D7MmL{__m8Iz{J@z~2e zwt&Z8;ju+LwwTA3@YphzRsfk>r41}?WN9-?TUmOSrT19c$yp*mcC)>1WTt_I>XXgmVRLAJS2(lk39A> zkNv`9zwy}bJoYD#UEs05dF&q^bFDJZz;2e}SSrR+36@H-RGOu-ER|!a0!x)xssc%_ zs49hFu_TsK*m^mSrLuGtThn-~E=%>;TA#-n@>nAtYs_O! zcl?>o6IgnTr6*XL#M09&O<`#oBpGiyk3GxMOqQPKd9!$IHjll? zV{>_I9*@oEv6p#lAxn!`TFlZ?mX<@3^{wEsl`O4hX$?#3AW4rmc z9-Db=E01mCvF$we9*^y0X%|boS=s|hM*fJ$_OkRTOZ!;*0+RID&tnHzI>gcumX5J> z9Fp|?n#aCn=_E_1S^CbD;=UIW-39wWO8EKQIdd%jJWD^CQn8;{`q?kh{l80bSHb@0 zb7jb4^Ygh@7`=tKAUk(1%0(Vt1 zTYp4X$?s+RBf83dqur0<} z62~WQNScy(IB9<3=A=c5(~_1aj!!zBxF+el#2rcJ6VE1%O`4Q6H|dY0SCd{#UYT?t zX=l==8(t z)Kk8qHzBd!u>9d;N>3|2xAgqdua!Pm`h4l1OaD^3z&px22JINz}WJJUPMJI6cMJJ0))cfNOlccFKYcZqkYce!_^_jT_Y?>g_B-nYFQyc@lnyqmpS zz1zL-d3Si<_wMrU_I~L7$oq-+Q|~_Se(yo=5${p&SKi~^Z@eeG=e=VS#wR?PFgamb z!iT=;mw4%65dYOknm2z#)M4?n-jJqY)#mf@KM5- z3120gOZYwELc+y_alVPZ$9+%up7c%fJ>`4aH^aBow+wKu_Pq`;*8nd>;eS z&wQT)+JnBMzGHy;YXE!7ciMNx_nq&o?|a`5zH`3wz8`%*`F;lIzxgis{`Ot;jY%8_ zASWh1p7>^V76K5yRNt~PbQsVr?1&Iq2UrAh)xGZsb;>yIe ziJKF*CT>f7H}QkS-H9J2?o0e4@mS*V#BUN$B%Vqg0iCoKXcmL|QHv@&UR(wd}oNgI+jC+z?|K1lj7>7%5NlRiz_m$V;* zIh=GP=~&Y7q;HZy&ZIL*XOqq){hahm(r+Nug`~fdE+&mi9-BNqc_L`@c=D6UPbE(V zai)VpGn1cBegOoUlROU;nh*LcOkR|{IC*LE^5oY*rPq_!f==r}v<;xtCJ=2~^7iB% zpw_PB-N}2BKTiGxr29O1fARrP?GR{o6lD7v1Uw1iol8ESd?ESoMZX*_g5^<;#=~dY&JTqs=u)5j(whWImE?&e&aW(Ism62b!UcJd4qrg8hB4=>j zA^lwR3pR43Zok~D%={5q7{ITG!^?Pt#6th-W@Zmg>VK~oBTtVpjiwg*C+6HcSd8H( zznHV)gF+Lah&kCq#c-UMb0V#1ATcLvq?i*g=B$5=<_7;0bMhV#L--p+&Rq`d7b6y=xn!*Q;NzLC_$?`t|BHZrs@GZP27% zdi`{=-BXg9Xt?@~@BhTHtn`0YmtL@cNvEZ=_O11$blb8eA9aKwiwCtUNJJgacb{Q*_pXHc{%;_y*;z@hGz`+cFP~$FFU7q zgL?I^?M=UJHhgGy{sX;xw(8wICueY8?@rwy)^Aj|!L@Z8)~nyJVeh`#Lwnzplb3&c zdSmhCn%SUkzrllj-b$$K>ih?WW%bJ*?7F%?y>IXNe%nUNyL8caaq~^teAmv%%^c9X zOV0gSxm{ZI?$V`I>+HOYyu7R-_#6M+x|y!4`{m@huD&DNb@gqohOVpg`VGckqGh?R z?tCx)&&U6L8@R4+a}(xt>h8L_T{ryyfa~hE+4-IO4s1JoC;~{ibw+*$(}euerV?4;r+58)~#2!L4$hraO^!iGdI6?W)9Abx%ub~7}h5H#BY1) z{t8_p3mJ&CdESL>H~hEFxzjg)bM2u$7phknk{Z>jhhz=O9QHt;JW*a;@5HThUQX=t zT(c`*?K%Iq`zl!_b^9sBon?G`UvSn7`ogCdI=6l%`MvXdG# z?cDHc$SzK7v~SgObxtlEb875uGyAT5vBK`9hJz0X9ow|5-ymI7{p!s>ZYn#s zb+1nr{yl5;H|3wI@PVVqMNeYwvW5nq$GT_WY?fCy8>gdk#y=I(#tm*c;rQb0S)UJi z;_BQA*H??aVMP-MXT{mGoH6O~qZIhJ=$yxCL*WJ*)1R+}suCo?6XlSluX_Rmdl= zPhqd8$m ztKnrJu4w#jGpZS_YZztk33e-5=@fEoPy;Wm@N0Y5~SD`Ue$+5{5 zc=6$~D1{v3sX6D7u~A{i;G9>$bsD*LO2y0PaJ`&di;-)Ynnu|H!qrTf8Ppw0I-NXA zrQu~$MVBk7P||`zo`Lp|-!tU*_0@R!8CMCFg`Y71=^lp@)@bGnc-4p3v*fk1E?%C( z#d#(2iZcq}wX{&G;N?-W8RS;1K3=}XFHQ!E{0E)cR>(6LeDcJ%zqtyIG{8#@KpF6? zft+6m&rEBjb>a9NIlj>dFSk_pJ96JG954(3hi+D6&bV7K7zkR!gG&Q-Af7QA#xak*-Wrn*5ma=cME4z(m~ z3cuOpcUu>{q+afF)sWEp{W=u#3(iQMFOp}|Tk*0Lp0x^jHpO?Xj_7aM`K{nKhum`R z#LFchPGBe2tb?5x>=vAl9OshbKfUqtRUyX|INlTN7z_nD&LhW3cjM(PkS>t1J{+6k zYu`rnFNy?ty+mHya`95T345V2^}VPw$g60X^U1GUK3;x>Uts5xUj=+426n!sFE=CK z%j9?aXuN!OeelLV48PjJetaJ71+N90P2QiTMg>=g+v&Q!=_A$c?zi80M9R6sGt;ub zZtz<|emy4P<@?sb8n3sJj*AFF(MkJgv-Q z{0`~G0ARb-lcWB&*9ZJCA z6>?ZX4!wdLO40MP#G@TMW@YrlwfY@d_`n@pT}k*ZBHy^pcsUQ>M1Qhc_P)p)+=f@l z*Vu}eZFjj`SKLHx@KDPPYK1`sxXX&i@`*CK=VoLNR@JeXVpVw;FWGmyTopte20h-- zUA7??Q#eAAYL-xhF5B^P6cNhH2#rOANfeE$E4ML$ZeE{1?91fY4fApFpEa}}Qcg6a&vIM~;6cT%f;OMx4SQKsqp@Ukk?<%$=Dy2{ohFZ^{LZX)1MG_vUj2dxI< zh69KyiB}v~5wBkfud1KpjfKslAM{my>sE;oYihSNh9)n+RnPVGTvN;S0R< z>IZU(2<|v|8&rT%wtjG+mhHRiVy&fE<@V!cPasx&AXc+LthSAGf!0x=(-f#p78g}4 z5U5R1pmbfJHz?4yFY)r0ZJ^G9Ks~i>T2FyqJb;(_{kfvzfr@$s1?r}&=uHYV@*rMb z2?Qz;2$UHdsI4y2TNJ75A-vSSmrJ@N5NSvtQoAm?KyOo^w8MCr76?=_5a|BGf%@Fi zxobT&p*B#oVn^_D$p9{^R3O@@plDj`-l0H8DbS;VK&1nLo(KfGRokeI6zI*Pc=;s| zs7xTx3<@N7S`R#`r1P+>+>D|9c%PNTF4;sOrXR!0plqB=XqUtr4YAMW2YkCJd^eMC z@2~LkBYdk0UpIW|RAQ8U5g+IM$?@#xuI>HV1KYeD(r=*7Bhoe4w%C0XG^LE>yTPbMw6L?uU$mPng3+fg%%Ah*}L0fgjIjmFBK2f3D zDCUo+@RBna@9iR{2j?R?WgFtGQg&}3P7isXgHML7aWY(;0OxDZ;3aN|%T>>R3O!Cv zc&gXner<98u>DZnAsU`Zw*mSD-hr-zcR>>VU;iCm*1)?qd3#)C&y#oNfUL|x@{E|< zB^Nh?@w3`2e%ovZXM9WrN6rKlcq>7{AE=H7Vi=kx8a8v1zko%$~CC0_+oeVGUyG- zARLNQKsU9=pk*3m|3kl1g14%msJzrFh`F6&78G~83T_?;X}?P>HLi0n_Zjm4j$WuZ zciDIDaN#y{pCYkFyKyrYjx*4<_b66Y8N|vPj|<%asIIs{1sG*lNat+a@pp|b9uE(^ z!NFw*xy&sKms=*_0)t$P_^EdoUC8TJdg)3p^v7>T30LPPo!WQl)~9Qmc75tML;zga zjmIB!x-Z3F>780&i27P}ZQSD)S3z~GP1qX2Z=&DUv)fG#>jl|9!Qc6H@06L>2S2Ys z9p9rM{43?U!7^6D^&`g@XI}Bn-M+P}pr)B99**Ox_31;mp~X$EtUkkXaDOWce;k6s_r1HEeFq{(9Z^U^ z!~+E~1|$SRU;#o2fdCawS5^I^iW@S*@hw#>74{AWXx^_HFc$_a z5)Bw#4Iq@M1W;GGY}L_n*)|h)*AiCl+SA;%SiR!5!T?jfuh;z;$vM00*zI@OdJnAy z%5!Cn-d0%JsQWmD_mrVqIE7Yn3N0i-FKoK5`t90dxpO}^Q>U%)&nm;<^}GqoiQ}nd z_E5m}>kG>sing}GMON|fA$?bHb$=pUU&F2J5P#B|nCYSCxZX}D6bSLRS(vxH{l3pZ>lPp29BuQIg{i?5IVx_TXlI>K>Xf~`ST*nLZ zaKw!6>)kSk#Qi9P;ZY#_L1aBK6(f^SJ{*P!bzkHfILt@?%yKi|5BD6T6%!w6x3u)f zzn`g{OPPNk#lMe{JWlci$&(~ckvvWE7m{a4o+WvXUr|uo_KI$tH<52Ct{?S_zwFg*?mnh7YM30^gA`OjJEpn|h7@ z@QZ$viQ%(6`$AdA>825=YoVo=wgoE>DR*F1`oiGGTa8MsVFfA<1D|&qa%@Z;%A~G91&o;um8ZiTh^{JT;7FUFR5$)S}khgpdaWPy4dA`4n7Gl;h z8w^}~>_(WbR~H5`8R~bQTM@iosjpv6eM_pot*XJpLZcEp-Ng64`Ff}ySo#Tb zcf_n!gPBp7*D7`Ot*L8?Vwb|2U3b%8W@4!C5!}jH87!(9owk>h${hB4J1?eo68b$=4*`kbFz> zZ<6mw2(aQ0B>y2{@lyPWg!Q<7hEqw2WCoHJlHZX0mZX)Wjbz4fR=7osxNI$T!OBF+ z412WjAVz6Ibf_1FdMu(w*SL9Zx$^J|)8M{-Tz*bm_Ze5sLTYBM?f1(xDzc$tE| zeAa8_Z+c0H>hD4Qzik^+UVO$G$CMu{%rvI_=nP%Pln*M-GNwG&46}`q$?rtnvx)kPUh*@Ac`C!~+ZKITX znCY|qtgNl@d}Zn%G~AE<9SZK1%*Wh+S3G=Bq2=-(g^80VX!|Ah>l@Vt^ar5TqK6vG z@WFlktp1E}n;WinfV@noQw^oa^43oijwLUC8RQ3{1%&v?n6jd38aD9 z4Rp3@Dbb8G$S0)|w>HIFN!ki)n6#Q1^+?sTy&f3#^ zZ)ITyRR=6FRR(s}8;?eTqieP<=8}Hg>mY7e4Q4m-EMrRev1%{bJ{;TGJkAVX8^e3D zT3u1jUTIFS9wL2PNd72^!*tQ&8(!N8&0?X#O^fkI)? zuvlZr&mzGu8CDSSd(76^Zm3kh-n#X>^@`gHo0w*UYC7bFg_b^gBOtkV$lfZb+&gfa z@l2Sdb_qkP76bL~M7hr^{+?tA3G0*Mh9n!23?HBS}V)pk;A132Xl% zw<^UkB=rB{79?Aej3r@FS{z5RHOY7q?$?SFNLXMNwjYdcf4| z?JOe2Ul@a3Axw)S%6?j_PbItUR_w`@1 z&zfu2eg50O|0?}g;YL`quETwjCs9P(P$f{#_GAvSjMaH zjH;^EY^e2Ayv;w-EYi~4PZiIr8a9-$c390ad!jnpn#}sV#3;Q^$hw)ds`$;1-K$6t z?HSyrvBQtv9}CBVD|*{c;p+%R%tW@Do13?U+qCKeL{>b&cE}DDzQNw4TZH;&M8#)- zKcD27b$6@s`_b%fp$Js7#E(872*=(XxSD;N&E%~uHHK;Ya?hN#&0>So@Mg%5hG=(v ztlq01tG^;tD8FN_KDeUB;F>^uT53GH?0{h#gqyx$(*9cwRN%t#t&i9J0AYGm zZdnKTF0@~%OW`H%ElmB&J;r6G%8+V9AhpsEGfV3AvA)rM?ec>Ve>6pO8|-lp3pXc| zg8Q0aY_^ZUA}ts~3ypM@%E(Hk^9aY#Vo~E|zpIw$$xN`*F1xL`!rtubFJnu&Me3Hf z72b-n1`g|8v-Dh6qs}m=gCe)0!<^FLZZo`Q^)sWmxEVpajR$$%ekUGA`=Ixrn!BV6 z3N7>N<-}w`o9lB&=S67BP%Z7Vzy^%*!~m|qZL z!~%U4NGmQMLTNNN8*f@Harg3B#WnUG#Lqj^45Irq(uIMjW<*j<{hXyFmJ!agQmW$F zxeG0$Dk~Rlk4>1od+*BHrB&nXNsD39GZoENSZ8Cm(q2IBXEzro530G#>8{XNF+R7_ zosJ@71&fTO>lL>ZZi{t{t{IqS(ALsK*Pp{)rrvC_zCN}gPB(UyZaZX{>$WpVwfQ$u z)K1uwn~#-DuX%q~rWJf8wrcim)|XFatE{w=UAb1t|KqZ{vl+XmK9AdFGWU05`94UM z&6icCF*;hy^j5dkW>FPGYzWz;X4mTy?Rs&`odtc(z_X^fR*j-Z)oh0yD$G?C7rQq6 zT8QouF|6huVJ8_fBp5P&(r!EHJt4EA-K@B&BG8Y1KNVVL>RDiqXXjn?7Jaq}afl-Q zh0s6Vj!fDitr-E9Q!xF$8mE2`>LN|HW`aZux$%1m)4wi-{y#5lE8JYs%Fk8WR`^_R zq&MjGm3~a0e<|q6!;UPloww$ew^+V~VP*IbZ}tm9vB(UlK{X4VDOyDAn=J|l`{m36 ztQ!`K8wO8T{L-(cleNn)JZ=fP__=;wN!_IW(j;4Vu7&t{)L5nN+)pi9y`So$x_-3} z%6dgd46E6+-Bs>=qOvTlc@*7Kj{$bY5gKxb4O}@hKD~=(Sk_=N&j!r@flsIuFI9yHYLLUY5mQs}Vy1Z(Wp<0en$@6_pev-Q{A zWBq#bpk~;(N0GEwh)?;i{yoc5M9k78+|3s|NR}m8j-)q9ACkT#{YY3E6;~i(v$Duu zO>t$CRY(}6imQ?Qj%0O`HAvPZ=}$6%WG#|`Bx{qbLo$eDU6R2h>yfk-9~0HnzCksk~~JD zeg1S+H++xr<0tI4TekZa7Irhp^sOr$qk6wmWMFtY-mlCjaYWj%nn2rHvGhcEfWI<9 zsS#0;hnkR%uGz2XB4xN$1*5xOzvy{QOpBTPn*Fv(x`jKdYhlf?8)ctc4cAOLZrcf= z&((gGmAyb6zskybp8k5W-lXleXrV`2VJ;J|38S(FxTWgFb(yk$T{ydx8O{!sY3l?{2QP=|;P+->&F<%E^6<76Tv<4!yI9q5x>6#3-7z(;Vr0!- z<<)X0{VlX`%_jLt!tk6vxU+_5DPicDfv4t1_!RkUe|)y_T7ELDc~(Ai4)f}3oXmCPLA&+jvY8z?^^TT zw0^QbE^waG_D zOKADZ>nwrG2g`zDV#_SF^zb1yo8Dh2!uQGAQ|rC@6Y8(MF*J4&$!)wV8cgq(RAaPe#QaS0JH&8<{9t#w zFb~H%2M+Tcg(v&ts;$hZUTNh;h5L`m%RW)~`Ci2AB6`BD(^PF`owlKHyzP~l>Nh-> z7G@(8J;*;yJxiD$A|_k>*B$eD)vKUj$oi_fWL>JcL^ZNw;P9~6U8nQMP4)}-ER%U26~aMYZYwNqHP);*CTrPvYNwWs z@gv5D>qcH^458-l;RylWGt6Sp+uEV-Ho4O7D_1+)3{2AZhP8B;LVI8B`)GqNvxVKg zV9ROdBt1R$J?#xu$21$`vSwBNgmBzLfE!)2G%slhJGj~l{Z1*bFa0etY3!_dp{RSY zWjp<1!S*}vIc~@8w;4NWoPHr^g5IhbyR+U4*B>XcXXS@U>wk2k33%ay>Nl?GbE^vT zW~GjmYTg9vkZRl|1*LsJ{98;5+jds%gZ#a;oyEJN@C>TCE#$(dm|HeGJ zU94o(pqh#IMsd8}!QNZg-CxLVd|CJ)pBrC)JAJ>@x;NIX{U~<_!7`EeQG-@Bd(Mj& zT0W{XoyB;o&SvZgzY+YnNwu-qMyw2(^Qn$f)J*T{dVg(DXgO&!EjZO@!b1-F_1N|F zy+UnKrP2PX4u4j7!J$hOSYyp7)%0vc=#zw+Idws`8F#Fq&1%B4D9n=;u0Azf^9jd| zZN}xtBy4>ac{E$xlw>oKF(jLlY(cUm2`|_bw<2NQF0vm|WDQwl^;Dcd!uy9s zZsUvm-K`>ja;wN++bXheROD}L6?r|r$P?)zuO}4wHl@g(W06Ur$jw`Ecal9wcoV$H zhFXzNK#JT76xshR@@7DhSI3HfBH=E$NZc38By9z5ykdJZQdIUc9#>0YU{8G-$2YRo z>1T1KpC#fJGOxqKUOOoEQAo@h1rPHPwy6+1`JnZycHT{V(d5-UlVPRD&1O{8&ysft zwRU9*rFYXROQ%wc!taC8m0M^<)swbJdB0w{#tQV@0#Vp!dk&TwoK&%9t{|UmMtpJ3iaJxe0BD)QnoC9 zK&^Rpn1NodNL;B#;$m|BmKHa)U#(mr=hMBz%V5>ucJEb`3UsfqK~lxnyl^?RBHBmf z*$TVW?TO=ro%Ojpznxtu54N@VO3jc@ZW14Dj~%y-e(iF%$`hz1GWM2!`cTiFOTOc&wu}>kmWr;!ZN%J=sG_iFFZm^gq_$)YKXSNnr3XxFmaSH zyr7GejcdMXSxuO)E0~&Det=NysE6)c^T_2yVb}l)7`-p)S58j~H%G+P+#_zTreqKd zU&8#aPUVBm>YCN%$+G#nh#BpJ?E6B?%=#^$BoN{+7**n6dBwqdii4IV>ux1hAH4Gx z`g!U~r2-RO=o8IeIO1smO*Fb@Nj0l_+waVbn#IH6GK1H%vnZ(<+6OAsMvbU`sTpr% z7+LkNOJRnUc?i4xB)%aXVm+wv^TM_QTQDJR!bXjY=2q3teq{_QzY4rvsB-&Yd;ba*jnmr3@JyLVQD zKKQE6ki1z_S-sCCrh&ZW!e>QNX}nEmtNpxC_sNx6apR$*-LyEnq@2Z5Y+eV~o!K5d z-@YUh)mAv6>J1-nuM}GP{XB;B`vBD#T2mq}4#V*-Rs9DH)Qnd#U^%&)=X0SYYMxh@ zrBqvdb9*v>8z6gyR3Xq-_-*9S3f`|sHx`P;9m0P8psnt$KkqYbVf7EHd7bcbp?*`X z$nQZ7m2R7K-E-X79d%jZ$ow|Ts@Mmx#G&bc@1k*>mHZaExmoyq52`)q5R&V?*H-Plq}*(1%7j+ z=O{TsH?rYP$+Dcw8q%T0{fV-z&HkYj8b< zn^e_pz(B=UrR(;VDK~8D8}L*cG8Xh}45qKj8iNkHbNI`O%%#FRHkwNH8j2cxj15LT>z20__N<5+T(dI0Pt~vofLc5&uG_zO zLG_r5fFb^tjzx8EL;3mhkA;>g{CMj)ejP(Uk1%#3Kag!tau<+^A9TaUS0b}sR;}?@ zFZqkF&QYxPo14Bef6q;a58qu6h_QW3vwgRp7q+bZ^Y_svWIOt!eR3G)4oSL_(&(ZL~E}QK?WzW6(GZTKMP>EZ#>~R*^FfQ_< zL-A>nzmPmb@+=8U^CDXgMdrjJZYaJ;!c&XlOC(H)MfMPibid-OB(IUYPVx^D#HzD4pj$vY(PlDtR4CQ$JMk`GDrtgzZ5e(}1l%;N{ixYer8R%NwsvhtY;G3>Da zYG0n*pc;ep57zk|rkbx%bx)Ihh+1kXZ`PW*Z5cKt`4IKO;*4Xu=`++*^>x~wvy9nOpP-fs zY_x_q@@!#MYUzPK&&IdX){&D#Jl8z5K0%SbUe!W>J2s;Necjq06UtsZ-^l`gKohLq zsE!qe=el)g8tz=z?N6uIuF5pHMlas$I=v@qdW;;I(AzZu{)Eug2N~%mWA1D?D$w zDEHdF8y?W88GtrSO*j zByd1@k2~zkTw@Dyo=IlnsxPiLe$)6WY4t08ah?9CE;O*(6Z|rT@7p%3qPQ2Wbdvey zRUYt$U9kEq&|mv*f?j~IxqhvhZ@M4hDzOlYb&g7mDOwm9U=Ggz&-S~MjN8@ifDwf*S@iHzEG^oLq{C8V$DtSGHUfR zjZH5?`TN+n#W!cf4fD2dQD|AON&l^`rs%()g{kiO%5?4b0v1sXyH;u+>^H0KR9x{| zLG?jP7F=ofs(wDjk4OEwZv*BrXV%=nZY3v7NS~drH(Uc|<=HuJo$$H_EyzB8-SKuN z5$#`fX3gtSj|ulLzX!?uUD<k3>}X@V4@1#hkhq;pL0)=25k;)O?IE)+ww>t1=)FQ;S5Y!)i80{~%0{ z3dTqJ&cb|eN;c|YGy-?USvTrevqP|`y3x?8LOi~!D8$Npohr`n81s9u@8~@XetB0z z$g0`AqE}Jtls&d-_*#6YFaw=oYZvZ)QD~U=`AF5sFF=B*c}uXXIu$=V&J+8}8oXR* z1NaXT`~QE`ARnBMBc_mCKyo3;MI;xK@EUi6AM034DEvRFX6N=;walFnGrH!HSgRrk zuLqvtgMD+}ET&m1i`(o+o!rmI5JXdXSZTjoHFo^gAxP%PW~8>l{88?(ntP=Q3I<-Z z3XcPteBknHpT5_Zb-(6^0bL5GucqhYTDiup_tR{pa7x|sQsFn*Z89&FReNb!3;bl` z>({=ur%%ECYYP-y$52y8K z%qNZAdh*z9w%=`%V(bP(9@-4Kzunem=1euFy&9BH3wPdp;=T2F{Xulq)6ZDWv2HMa zGLOmcu<|n+ln>4H%KUqQQQsQ;wKYH0Gt|ny9l+f<=0zvoWSDis7Mgx*Qh(3Ikb4>O zr**q_t)1KUp)=YvLYWFEoyCOT8{VPpKNLHXiIkBxr)gYn&1x%tU__kWsvC|(1}yfV!YCp1Dl8NQd;ZM*F!Y9~uhnPeQ3s?if`Im=K- zkF+Wj3;aO+n}#`}A!d<2*|#xaSeRh+-((M$E7relh%Xx<_FT()TGk@(8pp1U5Nr06 zPqNBGFFVc_ze_ekOv*%Mjd+Vy@I{>m;av*nM!WVL$9qzLG}*;iTy^XLhC06LqX~P{ z{oc14j%kRwv+^ctrqs2@GI514t|srNUT)~mvvDan{f|~S-{|U~ZbQ=5hCIBg!}i-S zN`7dV0~%s3jRBeI7B}v-2g;^l_O$`FcPShjLn@;?#{{3B*)V?69%EzA{EMOXuhtoZ z@b8AYGULiNO|#$EdCG7XTchxU2!-;W%=IV6@=5&JYKDL#3^Q}Ys6{kThn{e-;nt|c zV$|U-tLKtThly3qpEcBtQDFQXj;uQ#V_?;7*oF<&y~i^jY?=6zzm zRLr}_eEyjCjrr0s?-BC_V%{(2%f!5A%omLL@-gp-`C>6&DCR3DZw+61;06MM2FCd` z9)UxE(AYEp4Ms4~Xv8;-MWf?%oKHj0I5Z$ZKp+x;1RDWFBNH?v&6Jvf-%ukN_Da!SnQ+Jku{DoNjV$Ai|1Vi~t zG1s5r3)lK9dLh>z!3(+mhF!?@7wAH+KOh%!{l&JBPmB2*F@H1WZ^iuWn7{+d{j_hHQSx52{o$1(qB%s+|wr!oI5=AXy>Uorn8=3mDA=9u3S^IKznTg<1% z{PvjN5%W7^epk%zj`=+?zc=Rh#r*!5KM?Z=WByRgACCDWF@H4XkH!4)m_HHoCu9Cp z%%6_=Ut<1D%%6??*)cyS z=I6%zyqKRK^C>aEAm$gw{Gym&9P>+Jere1vi}~d-zar*W#{8<7Umf#nVt#GR{~Yt{ zVt#$hZ;1JgF~3Q9Yk0c}vqlO=2{sXo7HlfmOfW{UxnK*ymV&W@tpwu)TMNbuwh>Ga zOcZP@*iNv$;17Zw1Um|L66`G4MKDRQt6;KVH^J`uWyClrFu(m5)!>IgLL+|_o%D6g zzlr&`G5>eWzl-_zG5;av|B3mJG5;y%>~qV+axvzmnDa+>DQ}7SZ({!2n778fE#@=E ze5ROpiTTVipC#tA#(cJz^P_asGe^wljQLzKpIdor_;V1Dtsq!Yz{-YI2CI-&1*-{u zCs7%W&%u)g5;f+2zp1RDxA5)2h=EEpyjE*Q}o z{-%M{C>8~pbBkKogo84zX0+v6D$XDP&vjYA@t#0)Zt*t)O`L%)!<33G@fzGW0tH;) z2aha|KSI}9pj8fV{}7-DbyC0A>Bd+Fj&kbYfX>T3LD$HoJ`U(T{$yQyJTxAEYJyMo zJ}JSYi|0Q&!Q%suKQY0hi^rdm;PJi3pO)aY;;g|Ro8V_j@W&7;@r(D(GYKAh zJpQ=^pZ1NvCivEb|Jeke_MK@7KJ7biB>1%NyqVy;=-TW5a)M9$)~g9V?OU%W__S{^ zzWMf>P1nBu*Ajf%_s&W1Y2Q0H!KZ!iyaca%u$ubMOz`t0__Gpx+BeTm@bn$pfY>J1 zu!or8dZb{nczuy_YfEC5KGld%(_Mw{l7x@G)`(BjYlZL9gl`dD_lfva&!rvT#R(s@ zny%~i-DbAqH?#d1om-sd*-n2jKE`p+*Ua|sMB7vF8v*0H=fn1Y3Baeee;muG1{B+#9Cc#^*n|*&y@aAX3U!UO9aqIE~pN?BsB=~gPx+=k^`3FCDjNUyo16t#TqiT{AqE;L~yKr$l}_t{s^0r{mgx68`yg?c;}W*S9}w60T`K zVwLu?Yj}GKh{1KiW0^F+S!wc!*PubPe-_%Dg`p(DlCsJp}MwD?l!F za3F`d8GY%ST$@gmd0UAUFB^J~Czd@P`5sR!dptUL{1pj4?Q1tC__VLxli;b#%YPuj z;|Gs_D8bWq9)EL!Py5=f2|n#>cO>|m7r#BV=Ay}p&kKJ$d+#A3M(f=|bd&l7w)Zm@>){!9BEvE#@5wBOM$JwEMs#J$I-{fcqd z3oLesEssZ6u89-+fuD0W)V1;bpmT2*JU0qD6LZHTylKoK$LmCUdYu?si6iP- zQeZlrpmXS;=YXaWAAQXD&Wv=%hs}-nXn*5-Qs?-<_!v_f@%<#+q5^b!O5pj3=|+6S zm+_qx>8w6vG~#>9@tu{c=SJ1(3#kNJK-(r+SmO~f~S6u ze>cH{^Z54?Job3}`w2cBPd`ZT>3Djf@U*eD4Sw+QFG}#xdi-Sx9^d(xA%@TyU#==J zpI@wV=+K9Qm}tbejBv(xNu)DAVxyEe2Q{ zb&J;zMml715POaIt`g4p9*T6v2TvnD?g@?Wk%X_=_;$SGdorTM52rg8yfN zUo63YnBaRQ_)il2;tBrK1iwUr|0uyPnczQ8@Jl85vviIB%s)#f_=6HW;}7)smv-Tt zK5YKR|M>kp0XTqTS%LTa)4HZk;*MiE0qfC41n~bT@c6W!VHb479|!%+%YQkR86G|6 z5}+sg&LgmcGSB-DT|-0ca&V5mrrT?=Y*ytQ*w9(oZ-^Fo#J9=j{@i3U|AHspInWaomhwszY=F z<~~P*kKPp!FYE_$!2e5paDL=z=7Sp(nzF7_-LFh&rqrRiDxtyNRL2aG}3 zToB+7XbpDOIlh7K9|Fb{8^alE78Sq;J-HnwiyYp)1?;7BKlMRM zzMjBzVqJth!_z;pk22ET4O`gfh&>rm*Yj&#{$}fy)%wQ z1&~|IQ+0To`OUZWr3vp8T{q+HEJjpVW}F}e7`%iXXEAO14FyAr-_n(%!q+=2q^xLe@so2ctXdVVOJ@zLKr z-$APr};FYnWAg%qp+J8qmFbgIVR$<-^Q1+&hbI&%aY2FOh`8z1;j}2%bofBmUI+Ss^>Ndcyq-Nzs}#S^AMwx) z6jT>p76UjKE~SpmUFBJ6ve_5$c;=s31^5iV zlVdZvZ{P2AO}mFR5BzTj=f3^#(>1)^A_epw ze}95Uj>kWc;IV7Cz;t^s!K34if|&)>W%9_;ZM~R-BkpN)!@&y;I9u}@&X1kYSb1-q znJ&|G4)3A?o1HHa@#yXOy2o@w!kK_*9plR7QQ^ zUlpXf3{aW*#ruqQVvYfaOwQru`a=OSDW}Zf?O0A-jJ^1^hk%1J?`Pv7XPhw|8F!)U zDd6DT^O>K)(VvZv`yA?6Ou)f-d9T3q^nAC+a_E^uJRiJ_^U$N4_X%Z;^M>;>Ilow7 z^)aWhUMve(XCVupLPvdv31)QHhsWz)%I!EoXC}|;B0nmYBj;;Dn_zJP2W`Sw1zkP; z({aPgufQ(-U6gj}(|})+uS-jbdP3$9HPNhc6oO zt>XC3NciwWBfg~_-<>+g_vQn1Zp6o2XZGEd@DXE;_=q9nV~y_XW9)6jM|&9GJqaJN z*@*88;aDeN%b77Z`{+}COknJSj@Wre03SZ*nuGiw0+aWH&e3a00SC4<(u48C`0mxY zx10H$7`OVo9uK&3uLnLidCYmVvFXA2yaIFs(mvlqWyk_&GR;2UXBfNCb14A_^dA3$ zu00+akAF+o_>&mpz?a7hOz*dK?(xX)Y@hp!Xno!A?k(`LJ)Zg-$xiitQ?y<$^d9GA z6B{Ys&&R1xeM}Im@Io_0VETR&%NeUVuxD)nc4U+Tm^_3T7f(}h?SWbXV$RM|a^F}`ZRJg7J ze8&30%QRi!PksJ|%8ZXO!1GbB_v?qcM!t`G`oHmil;9bM8nsy}`$y5Dr2zvV5@lg>_ZWczwo_3d>=S4V!Z5IRA#adN$|wf1c9}u@3S+h8~}%o)NS=& zpmURXte~#I!trr zW*0oz0zGo>ig{nxupE66kb(50IIev6B&rYzk=<;VnQZ4IU@;Gq5B zMfUA6x7eGa>y+kZM+472@p`d9nbpA>xt>0hneT`d^kHtHoG}VLk@>9v8!5K~`G&t= z=g?W5GwZyOPwC(Fe9HW5^1jhI@nJrlMdztJuXjCp{}InT0`&SyfV>q29J30#39zSL z8`1ya?MxfJC_3tB)<%yz8fagQ*DERKz~|mR-wsa*hc2{_`JeouSdKi#G3+yZqxlwl zZWWkc?$tT`)+guIx%Vsd23P3Z`0mp=d@Bezm~XxQMu$FU3%E}8KQ)#k=X(M1wWNT9 zd1Gk-{M2uDf#aO^BS)sM%lDnKaP)0tQpbVudMV``$o2FG=^A>&Lqq>J-LVfj)Jy-j zdcW4WkJW`D4!U}}ZxZq7?%Ubx!abbzH|pe`jq8;K9IP7_5j3h}4dG1hMs*w_8tg>| zx?rERz1QUjl~Xr;2VD*oz-PLkM|XkM=jG6jR!%(}9+v`o-!M94_%=j6{h;ho_7eK$NfP=csejlsgJ`@<=dpd`2HGv)V_|TDlZhUX) z+}Fo>Jw9YU?f5R$IsP#{(Y+Dhy^ima$oD(t9Pl*ar*af{EM>xKdbdH{@M=bi+(-Z!E1!ms`I`{r0*6Q(5C;i{} z?udL=A7fr4zAYUeK0?o>1RTu8jrfKNXZ0PXbI&(_6TY<^-zz%DpH|-jP572~eD5TD z^xZ~!_Huj=>KuPseG4_=!)In6>uS%(nAWI1%8l>Lgpcuu1H6wj%69m96do=P5P|opNL1%TkNVMo=<0||kB0u%xGp{pi zis^|5+TQH^x6aeHVa;iH#%$^|dpMt-I=efW%&}>mj9pge(K^T8RRkQYB^vpj`v~JZ zQs?klJitS}_2Pjt_zX9n&WSq?%6zOG9?RE?IXKq;%tO?7tboJtoWCnDd|Bt-9>$gK z0;`+c4$eEP7xr?j6?61@RABYuM~~otw;qbxtgM-pw7JenFjU3pn6o?rK!0_npNr zwChG*e1|Tk8-6!kKF~RBxQ@UMd|~)6bdD~AA{M`z9N#AJE-f&=f9V`Pbl_ml?QEMo zAX*<+#&5F!9PtB{a}Y0$bYk2!zH4=k+`$5lX6rfHfVL(^t`xv$KETJFjR7CaZ;8)j zeyMXGv*^Qm%D-So=t;X+>{xstlQJJWK1S%<$naxC; z`UyVh(2pG5@wM5;^>wlQ_sTio*-K!ym=5H-#&Y;*N90;;G+RTDcYLgcJYS@Pm^`x81x7rz!<+2OC!xsQLwqTUgYpDf1F2YpljTX~PjgWtXr zz-x7Kj_-ReMe8ksS0rgT&e@DLYc6Q8R{m(jTNaRJ1H)6^ zS=lEhyvUv=Fxkv;UN(Kbv$Bs&c#-{>z+@kj;E9#{A|6`&W(ViKj~u0I^x7a&Ku`Rc z?4xz=@y!3r37`Ygwg6}Cl-BEGriU&$~$lXxD!FeOTBZM=)_ad$F!Rzh( zR@b!sMgk7Tg}nvFPt18d_0k7^sV($>lli93kuy}l!TA^gc_WFjv5eim9gfvC@#Ncq zIofPLA;JHWesXBSiw}PiU@v+TFTQU2NvbzI9QelTeVDG{-B`c@-TMNQeYnm&p0R#< z;^(hU=5soy9jx7`^NEO0!fw zC!RYin=zcjc#+*rV6x8)*eZTTU3XSCeS)~~vf($`w5!L@tn1FoK2)^cX7v7-fY`uS zM+iKA7F~B%_CX0RvR@IHY+~BWro6MVzYuNOmJd4FUnh8cb!Ws|?9yJu@GY?%c`pgj z(|irzwE}d5Z@!qrNB_5S?0^>D3tc&MR?j)HoO+%S&}QohIEWP=s~74Tx?uv2MFk#z ziLO1qdxHOayf*$G3I5dt-!sAAr)%Qh_!mp?4=4Cu3I6m1zj%UY4D|AsNbrZ~+S|8e zf@i+*_@xs3ck$ZvUpm46kl>d|@QnRlzm5cdQ-WVM!JnvWuitVB{`Q2wcY-H=Y470z zjy?k4{@=uF!}m?_pT+AD$~pSQYvK{TK9ARiUp~QKt!wNz`70#&YZCm53I4K(H~EaS zUjNGz{HnTMK!ASqA?r8j&bjA(GhVZ1yk{3rnjYXIg0@G0NPu^c%cM7;5(>zK~! zvcHr0ULq4+_Kf&cmr0KA!-TJ=uD$K13$}0V_{ut`Z8i~bEGB5gN35974%E5lV|-}D zH^}ilnD8-fG~!#?@jaCAE!Bh%oay<7&heYs$2ildK4QuE-c0xye~6!YvBVr>vEuzq z|1^2`>KuQK7I1V38p-=kxS0j$?d5$L%Za`F1YTZmT{n{VZsbelO^fBoyHMceF`hM& z_gv&l-qN_C-1f>&)SRewUIn@t|#vZCvR#ZkJv_E?8ok-;`L_AIaZ0+hCe!98-CRUe@KF7 z%=GdPP4K@<@aHA?)f4>r34VBRUAesci_?a*1-KZ-V$ja-xcVZ@tkZ0M}) zPwUA3N@dn({+Y;b{ROh$uOs_)C;O8`Hto|{y@^3|+(Kafek7LR+sotmmI0eRf9kAk z#++0({oj0YWg?rl>8$LV>d0pPH`!K?=}mcOWnWrH_CZee4e{J$6F;4meQ+JwJ2=^_ z@zB*|GZ%GM_Op@Kw*|Yru*_YIj-OI_oK9N25 zFOdC_XwyEAZl?FYBHsG^JikEp$8}_X8_VcBU&M2hJ+H1i>+gR=UOx`L5zCPMWjr_8 z^Tlh%Q^r>tV;MjH8gcM3CgBg`>#Fn4>U6be@tcpYJ9UjbWZy0TZ}HWx^Ulh?Hu8Ge zm#EBSQ;(ND|1XezQXSdM|0etHMD_v^SI?Ja$9HeSx1g>&YwuN&*W0_jlg--0+q=*& zkbO-Z*~6UdI}+Io{{q=3){(uMlYLhroBOuGC)dlEk4mNAzcU@o?UcG*Ti z4$fj7JZ0Tu4i5R`hVyHUw^fRd$3{GK%$>%=xgE&$ynoX*yuSVZt?L;D^o3UhDgN__ zw|dZjv}P~)>#>}=I7jEL1a^2`4_B$z1z8?{XoAPr9)CoFXYE3t zF-hYlu^ECdYpS~*ae3UifdsjH)dpY5w{p<0eCvk6l z$0U5j#WN9)t>$a^9*^bdbd53P@vX13oPX_5I4ftN`c^OVUlUGUjuu^gJe z3p^j~u$O>((FI>X$3Yo$5i-E}gEH?k;s8F%j~1BE-qtyETMIal(}?d+!WrM!kVg&?fH~jl`c~(@F7Pi#JoWhX#51nk zbRmB{mQyeGA#W=I2fmn|entN`9naA@e%wZ2c2Ea(r+&OlWybfY&OINzjrh)Vd`~BQ z)WQ6Z+_b)!0tA73A1{`B;#J)O+65}CA5BOA7Jd`~8P*iM_&vtcvG_ejD=T>}L8 zn!5c#StDK65zgA-Vx4=xG_zqP$M;0SN8M?xQwMr1DKOhiSMnaQoc1BE(PM&ugSMpq z8y~WvgO9j3{U6i0*PruM1y&Do%r}(zH3{{2TqA$c|7|{+qH|v#{H*`Mr}6huEJyFh z1u5TK5f7j5%dBBdp4mapy@~1Zyv~s~QNS^?V0!xU{o*s3r|Ue`v5`-1a(wqCeCX4N z?^4J2RKkZJ&WrfemuEP>za)H&_tVpt4|Xz7O=QxpjcnM%@jaCAVf#)IpW3jk<9j&a zn^o5X1lHcjv4gTkx^Vw*?RSyRJKKJ1JH7`KKI(1Mmzn>m58F&v^4_tWSbsr)9uou{ z&@Le`KHrzS$8z}Y7kK^I&-;J6FQbF`>-?lX+WbcWx}0iaLyV4O7lGU{v$dnT5HnKx$_*57Azwv#hbMKe=bUi(~(Em;5yNOJ6SwG@aUFiSD$Nc4W>8k7L(PcR& z^K6}`ePr>7Pjy+;@tvITwd;C%bYVU;`&d7wy0k=mstf(!a0exP^Xqzgbos!^yfBeT z8@&B;>2gcLw}7svN0*14Oy=6uFLy_Ls>^MTk8{trpsuG!my4Xt(-N8Zg&4yA zRF_j@Iql21;B{F@*VCg**~vU5k%=yQM|`TwWXE@4!nd%lr$?79oXiUnndmYy;!|BV za(p)@eCV-m#3REW&E^2+UyH$Wb?$wQoW2pC>avXEyEWm1wx`3t74eLZ9BT;X5}+4# zklVpI`jFH9Qv}?{;u8+&XAzjr7wg>P*VHw9;7vB`0S;s?7IScvLu)w3NNCW1o=}=y zGk#JA?I-b^`#n48|KL-;w_G`XZ51G&^}orxLFdS2e&AqS>kvR^I-34mdmW*jG15M& z++^BX;rA-DqY>Zjj*oRWx)>imL_g#La|qA{-L4i`eb4C}zU>7Zw9o7U^QGrwOfq@M z0;q?6Zt_?!d3mgznJ2tYz;nzg@V4P+yFOUwCX+D@o<9gUSR4FNVEAWs4t@s#2W!*m zsdJ+EOy*Rbr*&@W@GnHX)rrs0sh*vb;U{urT1;-DbB;7NkOdv|0|chi={iTwXn`H( zFK9epKV2K&;X3zxoHycI%<(bbdp`PVBR=|o)%SWlH$92uc8b=w|idC+zD?+aKll7?XT`&DwrH$A_(+uUXsg z?D(!r_-K3jKS$d3Tg7tP{&In@udA-P)kM=t-;#1oh zZ>_#B6TU@sJw3M5|4rt95}D0xXRI^6?-Raewy*E_zDfA7eXWR3ZU3F)`zqn=M?UKDettfdqsKi0?6I-4L+6d;VJmv1^6ri0 z$h%+Q<R=+JB5m~(xs0KQ!W9ISsE@zECMuM>3c`IgspBmK9Ge5wBQf0K7> zlxOX|LKAuGH;}islgAkE{lQ$%wbjS?$@L@w$0`DkKPFxqe$@njaDr#t^!$e_%#yznF)T)1W&A)ec>Lwwea!P#RBFtM3B?*L(`uF!c}-&`s)zZjqS z#WxwZAn;BWaDbyOlg;g^$8+9U*`Fo6$o@E%;onaae4DO)cQd`=dp**k8#-8fzZ9>L zM|T6an}7qKb4y@;00%z@WsTb80pXxU=1K8z1IsoAN13s%f?P7LyMP*pVo``RF{E{@5+P^ z8H_9FRL|#){KC`>kHtW$ORtDeb?N5#F4ei`BgTkzYa^47ZM1zOUEnj?3w7>gqF*Dv z{|E;jI8WgDkk^Qher|kcC49(e#P^2dJ1yaxy9wW49Uo(Y*K?jGd=ELk8xp>GoA6PG z*>_dKH=nNQ|KQWMy&{%_yG-EqoLSd>1=hCKSFCM)-~Nl}@V|}W^cBV}Wcd0Ra~k=@ zZUJb&izDA3m2)u0G~(M|IIHh4o%{M0Xu>zi@g0)zEv)P9B0e1(w|0EjBz&{!dV0o? z4V+BoGTOE?W5}A0@B4%gzcun%AIJCags<5c(!=q6lkm|7jp`%Ltc|AV+_zD)F$6l} z;}*;FH5)^)2|JL@I@I%V-bl}ngfqTV624|*$ZL-8=!CD?7{dH$^|9vldNvzF?sI$x zC49}skQ*IeIpJ$IhFs$KZcg}`jUkNRX5V!QU$Zd;Ul<>25$~5~V+iAg@u9QlYc_`L z3eSCTl(F z+E2iN9ONR?>jK}hv5azP=rhnQAuxH5=p1=}64=p59(KZ)$|Jr^-km!4^3bD^Jm~7l zGh5L2p+sI=6M6pkPzmQ&Xa0_w89i|&o& zEiGID64&+@U@bd66W2E`Qd=5Qje(v`1_k(cw4w>f( zyi9DS?ZKz*^+_y;?_7cBTS(W9Y?~JOQh6`Oa^zhr@bZ`wo{RW;{h*O;4@DkiP7!#S z*mhUMr@Gu4%i%j;;Q7#HxWN1j4m$I5BfBpYMLj>#|IPob5qw?EV(z#G@{VxwZc5}e zi@ALp$lKk?yDpJOJMZZDEauRAqAU0DwpA?0XWSood%NqpvoYL7w8)?xelIW|5|_w4 zK)``60|n-L&$oIkN6tS5o{xFFo50%HY(pkx$RQ_o;4@v|GhN<`xNXwxi>uh(|~7%RjhsFK?Szj=a|eUf#;Oo;%{}`4S#REiTpKwfqeQvJ^g7j z)BiCipL?f5Yhmc0!{gSHNCK3n{iHKFxB_6**a6!Xb1m*N>II=Je+y5RYU!6@?xn0- zyjspmgY^FKYQ30uS6-e{(O?#2a#bF#fhjwiR5?4ba&|-I?9m^L?$sad?Cr|g$Ca}$ zDra9-&elNBP}_*g*~rS-R+Y1xD`(GE&R(dTyudJe*CTw_!?k03%#Wg@9j;o^Ou@Q-nS|C<)+wGGg}+ze07Gk*2vmDSQ#T@ z+vo`mMX^Oaw){cn5%?NVte4r{gyM=^iWxHto5A3i|6{{@LY=baw*o$ z^~Ghm6s>u_C~uof@p2x;I?et0NUlFG&T3dQ%3*BPvM`RV<;$z}TTduY3Eqq2%|y`; zjJ%roTFM)T(Y(}>jll0`^*5myoV7(0ipz5;+OoE2B4fK;ibr!PmdJe3q?RLcDZbC6 z!2eBZI4IYjExF#>CYR#DT#BB#-Z~_g;_Y0Dwe!4HzBP|R>(OTZyg1jNy>fkVST4o8 zxfFwPeQ{|n#c%U`QJ$Df@%KE6wVV6%;XHrtBYs8_Z8v4>lU=j%BCdSD&-j~AjLCf2 zgyN1|iUl%XHj(kiT#8q6DOSsT*`$^$aw%r1u8r$^Om}b1{CP&MKj+W&*1owEFXvLM zn(M8zaw)#crPwUjpHJmcXd9!MKX1?V=kIcTaZWD954jYZ=lbH#T#5zrd{N#nm*Uer zip`q)^VK|m?kE1a1lo&enL$vF<3(Iw{Fw1Kq1ZC>WfO|Kb14?ieAz_C{<##d=TfYZ z`LanZ*XL5qo{blcWoT=+nLp3T_2wNm*S^93U<_*)NpvN zKWEJK=k~c2kL6MC$-&nt5Mxpb~Cj?Sg{D3{{*xxTn6 zm!eCaFUmXQQoNo=VSB<2dh-)`{@hvZF=uR(u=k#g__lxXS;pUlVrb^eCKT7@Qp}$D zvWbjIxfIXjQuNMz*`$^eaw%rW))$Rs==F_e{yZkvpR?wAYv){wr*kQm&GpuCxfGw| zQf!#(&-?NymTB(KYjgeCJJ%N{jrc*@WWeT#9)zUpA4kM=r$+xfCm8zHCynCH&}#J`$=@q)em@`<5Fd%jZ4Jk^9^TrS0Z zxfF|LzHCyfK>_!MPa9g5vE8IfY!T#B7?DR#@H*e93b zfLw}0b16=$Qs~{Z;I;CI8f(wUr8qB_;^JJ2D|0EX%cZy_m*UP`iuS6*tjK9-{@D3iObsG)AzwU<-jZVM}8LTM5PqbkkFsEZ9}R%OSf6v~g0} zNuX~AN;?R&@mktmu$@3Jp_TMvNNIv#8^L&i2FB9vf{}tz0=@pIkNyfHGIhe|;#wbt z*IS$A(?s)=gGE{kBmc`5RjiRkZLNh-&LWM`xfb2)tidu_w8^iCz$X5z+-h+ApNbgtTW! zvzM8d59b{rT`Z&vg>;3GE*{cFLONeamkVjHkS-k3c|*FaB6YLq3A6OSou{5&v$ZfL zdRmYFN_tnmG>?GSyR|u5(gV~|yFd>BOA83}%4A8e6qK}}E-fPHCeY1eNehosZvn4) zFDuX#Qqm?=NkeC8DZ!EgeHT;GMs}%}U@-x&-1ZQ37cAOZ*gWynw@HMzwidRCnrgeS z)I~6xKwAN&IRrBc^!jUQ*4Dz7PSOvOGDB-&Y~(Dp7PgAmme#_!SSo_8W2w60_*kk6 zw~3|Y*208X`d{^u>?@zH5Gs|=2GdJKE~I}B>9rxfCZtz~^s10v8PY5C9{a@T zQ5A$S?q{tW%MG8GPfMaiJ zlTvxEkj@#>IYK&nNM{S_tRW2_E0kvr=UqZNQ%GkFXC`#oSLOORy z!{-*|uYwL=lWLh>nz6O8o%2|!j(7A$M(%7OannsR?dKle{(srSRo~JA^Jt9z!++Vs z_a+|Jn7qUPH$2>0*zs59Ta6DpMc@8cNAlLf&dxLR&!3Hit%Y4I3jVjp{7H$W|2Lx% zywj5YqBh+%dTP$r!sMhj&GWmNA72oAsr+I{{}$4hLi+cRz8un5Li%b*UkmB$A^k^4 zr-k&5kiHqxFGKo8NdFbm&qMlINIwnfCn5c3NIwqgM02SaHKezNbZSU%59!Szy(Oe~g!Imk-WAfjLwZk0?+xjFA-zAO4}|o=kUkXBheP^E zNFNR9^CA6fNS_Povmt#Zq<;zN(;{pbRuQZ!&=zn>FK3lj7px&zQ_x>9K(LlT8~df?in>V1K~@f^u1IDwPim=|LeqIHZS!^w5wV7Sh8*dPGQ13F*lpJt?Fo zhV+Dx9v{-z>S%tzuS4_lFW3A)SW00JvaJ;M{&dsR z!d@YJ2kZi<;lkdaZmY6?rLe!(Rto!SP|xV7x!+~X-s{s`2q6-uv7*ym^~g?$XD*(p^X z&gm+3|-=nP*_B`NVch;z@8fA_wl)`>UTPf^? zKs~@w>pIaU?31*W!hJr}%#Qs9>?Y9$aOkEu`&SD0>TRWPj|(;PF>T7e5W76J)ZxCf ztrYIppk_D9sM!yyr4IK{ZKZGr0yXRXMFq%ax2Tpn+!eHy!m1o-VS-emX6<%CKz>Zf2 z=Ebn8X)A?Q1stpe&>f$!H&#m>RuXNcFh4`h>H%u}Gw08!!<^ez3Ue0J?D|8^ZXg`B zvco*nRtn=Z)LTVr^k#3dmO6~3ZKW`lLCwm`^qwc4YvVV@N*KS|N@4tfnl+YDvtP-1 zg}QaNF~M(g-GAxdMvIhNx=tx?)UEtuVWWPtOq_GUwiy;{E%UB!Vb;y(oMF_=h1oVL zozQio;$|BaHyvJ3KD^NDq^^U8Y%~W~V>T*o-s{w^1CBWOqL~Y;p4?SMTa3^GbV*L< zTz5oaMENKE>wGoaY*ZYN;B8dR>6L0GY*d`s>nyA0464~SRKw{nt>$=HQ(j(!wK85g zrn+#gDu=ZX>KNMIv0;11koJ!C+oP4`6-3snU;AB$4cNU%Xa(-Ypx$Lgsqw>7s9@6`WgL;e<3>kpLRfo5u z0WIuBtcseC37YewM9`ee>C${-NstTpVmdSj*V24~G#}sIF|NI1YU^M%kH zTubx4rTL!i9lN)8Om6R(R8f96VSBCTn`6(a@>6%0mew4TGwnljOv<#+Z;pL}QM~FH zjN)>-j4DfljM_Wcq7$xVR9Qyt-`=rbd&j;Niw+b@*1G1{ziN?hj{P!&LUZh!8RVMd zz@Yg-5*9S)a=J7>P7n;98m=Da{XW?>Mx*pLyr}Y8L$0bC;@jkkUuMU(!H&O4da#4b>9XT3Nst|{1od^owd}Y>cHGq7aYK8@ zbrnV*z2mNmgLwH|bl+szx5{cAbWdj65rq@F z^?J}b=-;C3^+4jF2dfV9VG?D88SSn*{`n4B57zh3_rgtmpz5FdgMawsKlq2s>GBUh zf+M^67C88aYx(Cd^3PN49Z$4(JXUehj2Y=nS=L2at&5(LNvuYQq34{7_^!3rv+cE` z+jCVHO^u8phMvg$9DMXx9Usktu;=RgXjb8-K3nzCGr>o*sWkYA%jxpbf|4K~@%>Ej z5!dq3%kt4n?Hw;x9JEkIw{Vs%qO8_IFJ-oc7<$b)sGBHzy_z`awW@=B3`H5iKQGqt z4=?Tadab^Hx(he;)vAA93I6G!(%>I1r^`QmBtib+Yuex+uH~Qi<)3%kJKk>Zc(dZ7 zz8Pu1EaUysS{J=5lPrclaxPjyl)XM|uN{p)s=8=uWDGI%cIM~cqc`jLXhnp5RNqG{ z2{-k_s*gShK3Z9&!AD$9myZTYf_(HlWx+>W%ST_xN1wNMd|GkP+8NzCS;i0i)H>+% z%(f6iUpoi!(__89N*wfc)j>XnqKx35PwV(+FtWa`@1OOAoBCDNKVJs_tgq7GA1gfJC=RmW@_c>!1I~9t)t-{MCtUQ&ILR&R;u` zmFBPRG(^S_K;LIh#zD>3?>4h-hV;_>b!WCQ!c8sCUzyno^JBo~|A)NufRmy~|NiVQ znFSG*u(Rv#%u3@Tr3j+1Fp^{u0aql5hyfKO2ndKMDlQr2P%(ju0YyX*F`})af;q=S z&z$3V=B&s2d!Fj*FjGCf+YEE-|MfoCRrOT$Q@`h1PlxH5ZD3_$)C@&zEIh!`2`HEt zwLz>wL4~MSpq{RrA_t9=#ds86T=fblNSw0~X=4|z2^eWKO2XCH!R1aT%SZKTO(f@y z^|a^}2WBIORzs#W309^>%}}(?ga^=?ih^lT8?<%@t>y)ynGNhLIc}CL=!H&RV9fzc zJvMcytmX7n~grRg+pu)CUzdIOpKbLh%JE! z5TiFhGBIj{SP_UtZCwA5gO`T09q?hFfD3>RvBouEf8&NVAsoWt7Jic&gBKx)|FrF zUBGU{NMoM@?**{E1I)B`xT<-j`d{jTb?jh%$^|a^@ zP|X7zTAi5Iy|6MZYKEfqDm;MJGborAwLxnTXbmV3{R>3D0@2sT_8NMPLke6E)dx7S zoBgdEqlfDKEP(V-y)WwOq5AT457iInpkBu$927M}1@#d;ASik%9tTBj1T_pn4Ji`odS@*wr)DVS-@^lxf5C!Lp*EDC z0OiLOh*1S%WPuoAi~j+=-sL#X5pRxyO1h-ba*UMf`6=!Qsh*$WrY=V(e8-W4Z%OQL zI!1G7KVvEmjhdlCtAjr!L_~k8(5Q{j#v!z^1>)oaaiSepU34L4*P@Jd;&Ly_$ucZn zloMrGu0l!_uG3YZ_I()8XKJ-do=0nX;e5Szz_)I{-e5egRYr$ttfmmH2Zm*R?KR@6Fbcc+Mb7+$b z&;=N2+>-=olLN?|LzWNbvr)rm3HjQj=R+?9H1Bcv+|7KJ!peN88Hx|Rv;YBLih}u2 z8+;xHpUnm00h`a&a@>6TOB^8wIe6c0}?U;N`IYK z&wQ>U?_2f6u1BA_#Ub_x6I%r<6QgD*V(Z}n#BM^t#HbBoPl4DIHZJg1FcsI#7j1?hvc}2W$_3KFR)i!`SrRB*cOa5wj~{ZuRFj@Ye&wnmui|{ zTgm(DdSZ{F&)nt^`zI573|1ya%}~T%f(HHaa0sVMKr3O#?l)jjJ8qZJL@A;3H>;%H0nHrjz#5}j6Mn$ zqpp7LRuo-3cNIP&&Mh^gFyBC*7Qf5a{PNB9sj%akUN@G|SF7zXtJyY6OCrqqJ31fi;BH%Fx@f6 zI5287iOSEC27&450@J|-W?vVW_70eKPId3JjQBINO{XWOHV;gpBP|Y{&P=Bl1~VOM zhN46NY!&EKpkO-G2Ay7@(<3SpQPC|bx<pK6bXXYb&@MVCrT2og*}}Exe|^!5Nd`BWGy@(5PD@32SRNGQiVWf zN5wf&F)J$0jEXbtSZ=`pZ!EK&Sj=-ER6Qb^(5$?MO`YB2d?=EOte*&=tviClb1nY?nvd+>|($a2)r; zFULX6P;op750L*b%SVOUh~rYku`DVsii)Ln5cKvbZxG9zAl#{Skv4{04jyVu&h6?0!ct9ZUvVK&kjX-WiAnT%HZB(p@iq%nZgB{Bk7+~BMHU8_qomuCE zW3Gi(b?RFq_ajhUf2hng}q;fQ>}$9!hGfvDGMtt&cZ&FGgKhm-~oYj zV*RL48-cumK(nHdUksxc1~Uw5hJrB&9>Aai1+OZ#0poqZcsDBEwn-cgI}pkB z+>h=(-*qs!*Yj;>J*}JN4_Im?9I#YshLSo89w2onD@29bkopCreijv-KfZx_!@5PlE%NO3hGG&xHp_oxuuGp*E!c4ynIJ#m`ak zqpfzf9D1HCs!-68NReI%D`VrOKBxRCYMAp3|M57Hz17=7kI2iX8d_6e+vjGCd4{QwU@_7w_7 zMr|NF3dn{PiXnw!u+8g7IrJx4{EWiOYnTj`55kcyUcX?ZadZ-|kq$5SL1_74Tti&A z25WHrN`6P`as7rq^JoXx2*&k0tc;7Ap>XY5k8w3X!MLamT&Donm_l(VS*|b7&TA`S1^D^YnwzAk8g_qYf87gPk zOc$>*j5N+j;x*IZ<<2n62je=;g=?|~S3B}MQ;%yO^qFTkxMnb}_OLQ8YKFp94iCV! zKMKZ0ZQz;@TyqOWRiT(&D9*8ob(5pJ%OZioOKdKpQW>_$MeJaVG!`bE^%ptBOlwEZ zuquh2k zP%N=|Rm!19$YL-GFRzPasGMP!xp*Ckk;bJ-ye@Nixiif2!MK*Xa4pf`8bW?A)8iV7 zKJ!us*CmW=7_5wonxSx=1P{P95(VR;HgK&1uImcLHHG5pLUE-{>|{B5j4Z~Y@DjTY zQK<}D?IJb~BaIsiz29}Lc8HnQj+|lFNbHR4Y8SFAHOMBAYHECh@x6;pNUS%Ln6HS7?7Xv=*b)cSGufP!+koT~BKc`pk_Et=pK^Tv(YFHAB%_ z1`nXM2nExkHfTMJ1lwFF9w-!Mp}4nD++#DlMDB2@EG|RgWwzOsV_RL!F2_h?OQH8m z!mSQ7)7p`9>;YGfnXVkW*HynqlW$khBwO_am!r?z;t+g<39f*Z2~sl@!8Pyzg4dv6 zg471V7eMg2Lh($Yc&bo5VdJ}5j$SK^TTpoMJtrgQliJHJeCsgMcqs|r%MLzw%2_@* z<(_d7d&*URLPKvo&GE9H-mT~}UvlWZ$n-YA%Jiriirype0D2}0rblhidlU5DC=}al zZd>HIt+IF&g_qkKh)12;-f?kz3?q%V3%!rh-f_5@){dNZ+a!DfH&7jvkCTIU^iZBa zpZT@}KtB&-aDnxUY)0uO-l914a)Z9w@5P(HAUyebF1CX0Wf@DlmJl}Vqvh-|}1 zoL7_rzM7JlRD=ZQPMWU4*+6;6dY#CY?3a!uy z&AoC3FsmP~v~ud!7YW6z{0ul_<39y8I-pz5^ah^X_1K8;uoOT zyDn`V@n##>x|BLg;H*o`F>2O@#(Dl8sU63-7;|!r)C?8la(F;!7jbB)P#ZCJM2sDZ z#J)wMy&d2RbRl@x>U3}dbg$07G89Tav%OQdR;LpyzY@+^IWvm1ocg_sVUuFhJR2Nm%nZ8~&1J7&!i@ehgQ zkNtXbh?_7Uhe*v(AwCWdi0lE53>9i4!~qDgf05`{B>EPKK1HIJ9pV!h;0>|AE5v@T z5c@i@n0=fOdpTxJh$&e(kOO@hvvQ!+3>D}$ctCtFaD1px8-Wf%po5Ds}y&}W|oCC2a~=R1uzG13@TjBS2cY>71z#no4MxX-(WoLZ(gyUU9QTzh z{*A&5Xq2_Y^iqP+E_YrRSU_K)?eEvheM(g=}gFf>FhtKiM=UZ5r z4>d#a`3oMv=O+}*huYwCD)>w&661=*SR2uQ<Gyx&0oAN0xL^&8~OfK@C z1gAKNOlwEZp>YlubF5Rhb10XbP0=&TL!UX>VKj*u)q#~6Q8N^y=I{VUjZrWoYJ<^C zFq%;$rrUsaljC-m#U3cUIW$AY!=LtMxd64mNaL&|K(ib`?i{jwa1Kq^@M%fDX6gB~ zLZ5k-!{DH#YJ<-r@L5nK<`s!KMdCc0Qad?%A6c|V;ia?y zQK>Y#z(r|aj5N+K!li06&JvNTZgi(}fkVl(cH}gg=b$m?$P+bxy?UNww^OPEIle%T zY=88b=R3$2GqR4bGBRq0Le>Kwfb1X?jEveqb{UXeQY0=e5*OOMddi`_WYHUim)9jS zB+jbkE?$RVq;W+OujLLecUDDkKJy9(*X4}sP*@okHACSV z4iCUJ2nFM!HgK&5t{aNP^+n>^BC*mYc9a}FLKa7(@DjTLQK<~O*+pz5MjC61aHrtP zu$vuXrnMty*!2z?^I8|Om5$xcuw%&a&3a^`&}Xi3kln<{j)j$xQ8N^>3Ge`9C!%0v z)CRIUfNW!t*iaqp{L4X5(+P`jWQ(8u)AHnCS#;=R}!zg9bWDXvwU!dZE)dQ zufa8i{NAm{bsGB2yBu71GOnqxGA?S?6xR{-g6R2pwEzlwxenu^HgJ^}SBNgf;=p2Y zK(XjptUgWB3uugJu}qVmbRz0f?0lL$uvq37-4q{y`WCuD-dtjKL|whhBJB&JyA_j` zg_wkcqGqU|=oK<>bOFbL3bhebZv@q|SR7m|y4w+5iY`PeBRYg4>ghz}UdV%GKophP zT?XWOZ9*Sbei@vxa%zTBz6u^7*nV{lwV`|vln*Et{fkAvV$s(YPp_;o4EJ&jaKxMa zp;CQD=_l3ma`ctz7tfm$@V@TDIVgJD4F^TdP(fKQj=6mEWb5Q!|wEt?&TBCJRP|+E9K1lpj|tMiq;Z z#bSgl{!#QA`@5IpI7hrW3M$odjFjqmIYvnJ!OJn4gL({;@N!TyR8TL$17dlKV?l-5 z2x=UH8e1$*E*2-+5xtBqMC&>_#ySzXm*Zp^5HH7xG9cG-jA!Mqz!@v2W+>(F!UF_v zW5K9U8_K6b`IKTYsaQ<3mA{8B?{PiFQEpCxM63mE%!!Wl)IT;(eL?gzj^%y0=UAv2 zDweO{0U> zJC=_MwGl@Z;+S15&M6kN>`;D3m-pbF?Sx{U<64thHH&2q$MOf{p5O!}M^PNE4YcjWHaV+9E8o@iqLCsKcw1Nl3(TwGzLT$ux z5#m@{ES40D^X*XRr8eFpe5n(Pxx}?5=hrNji#e78xaU}?87h`G@PH8Z=desEs(TMI0-O#Z|>( zg&oQPa%g8+&?|1d_oXZ4s_@SMR~0)Ctq#ISp5_X=3@{E80yOK8KO7TlIVfpwC?I@L9)v z2ExjGs2PgSaqs{>!%;9FYJ<;%;B$YmxUX1jvJufcaxm2ON*phu`w^1*Ecmbs5xq6X zc&ONWc6-=CWLi6N4&5g?Gowu!M*L!(hxLr;MLFg}4x`P?Xbh~(h?=1oSuewx2uIAw zdKu1>VDxygc+>_o9RmQ!_f0sD%h))Fo^b&>1N#|ICjolK0p!jh%Lns$RKtf~g!7D^ z55EZKX@}2K%*TEa4mCsZv0iXvzX*rg$f19N&#T4ajh}vNEJ{Y}QEZ(*OSuf3Ty%Wa^=v^5b=g>zkK=j%iBIb``@ zK5uLITuZ(_((|F$;+P*gd_G`4^g9Z(s}wDhmUFP$O-hhgiL_a-@mKhy7237zR?ro*WdidA@(&ByHgRP zW+-A0N@AN7F=~U@PayV#jmvsR&O>r6y#mLZPCvNP=~ovndP|P+OA@YM9bE2ovV2sZ z7Qa~MS3NCyEspt%L+fXzMK8qR{Gw(kS}(u@^6NfmnkQ_4MvTIp`xl2JL@{@2iad5fw%kokE{Q8ufH__Aj41H$4L#r{<`W#lKMa@vOeu4+k`VR`G zMQzY(0b0A4h~_r1pXIn;WbrEsFRtS~9UeVP#^}3`MLS{_q{dBK&9fs8Ackib1T%##LVqY9Nb-D7?6e zT=^Au;cA4DMl1uX*DM2aXqbk^qDb-RteK;0xQ#^W++;F!vi1{qu~6a zHfWWDR+kcSV2L=OM0B*Vm7&+zzr_7e-HF{i(8@7>sBQt|hw7-Shw5p6nbnPhYL7`c zC~AfZstY_IDEnPf)J9Of5me6-ad3&~Zb#IWA}Y5ck`L9Lh}^4rundS+)9fw-ay>Te z!^+E*a%zTB-cKq&m<1yQYD4)TC?8NF`j?1)C8Dn_{!sLKmt%k<-s}&RbjZ_k^poo4 zLv^X1pW>!2N6JrO4(HGYU@Be|YK97JBs?G@dS?`88nqGHFoZUwL<}wwm3CampbIg( zp5+d4;&Ly_U>O!KN~H|TwJ5_``6xJJ<*cOS=@}m zd;OgySB0M&p69y$uEj`Wc8NDL&vPi4){cCLo#|jO&p^%MTmR`1H&UUW1 z=Q5-9urecRhGMh{9)QMv1sAo!Xb~7KC=v5)K=;aV_sN1@#pMOGK*q*5z!$gx(aW_A z{LQuJl6HXu$ekvZ4?cU&)9`tKd|jaD^C0@n^Bq2mna^fenGZEX@p&2^z-J2zKCY<^ zK9_^fr6poniMYr{^o$((tSp{G;YD;QLQ=Q9D_n@4$4Fy&iT6la;UF@t9XW@VNzTmZ zA`K&Yf0waB&*(+;nadqUS1_ZOU}Z+s48`ajcmShqD3}qo!RUH0y0%2Dv;om8xiIcM zS-g+J3+P%I8|ToCEPK`vraGZ4R*wOzc-!nHV)g5zDR1#QuaMCPr-# zy9dPXvT^0fL3LzN7ljwsU9NPx&xNZVMjH1f;kwVkeI*F_9k=jbfrfOg$~5S5z6h$BcKak4*jO$6?K4 z&O^ecF?lAVkAnHAtDn0yiqTJQ=?^^21~5NGRKKn63!+cQtmf{q2nEVJifOte59`1~2EpZSN zv!%pAOw2tb4}xO-eb1g8$O1U#K&TlikZa)qfn1J)1EDqo*&BfvF|k)n#ABkw4&*xY z8tszS)<}tkKjrV`TH3g?v?YN{oBR&G8!@TbE@f$@#aY@iCbAlXnFuvQ5xEl{K!jd6 z#YCtLA_ss-$C&646Z^(Qdz;8z==CmbM+b-50l})z*!xNzw6^l^(RgLsOB}A1?aXo9 z4Zj=*HABU*1s)KGe9;st)J7Z$#L+D#y2ivob`V?9>SkrD)-c8+kJb`F;$T*-M92l6Exb0E|V z6-XZboEL%6%bhq7Y9o-75Xk75I6fwhjfrDo;%GaTIv8M#i5c~+aQLb++6l)z9$MAH z9xLPFg+0bu*rR1Q)mqpFn9m%Ovar(PEbPh5qag+}4{C!3ZHu8?Ot5t(N}u3FofG9+Hx z8P3{HcdAomaMfDoeId_0FJ+mf#aZUrOlLm~W;)aiMdx660F(n53M$kFoeMx`aZD_X ziTN=xHzulVH2e~#bFGygOk5T_T-+l(`ZrRT5t% zqoO3Hj};Nm%ZYvOd6RF9&cu}F4JpYhEl%>TVi;#(FfTGSL&2C24_M@LQ7{Z@1IAjw zSQ8VgZ4wJ$2O_z)Ln&w1I2hbHyV_Y>>#p_|mbwrQSSmF`Nwr=>bb*peZAiTXQa8rL zhL~7ytEE>J8FwXJST;I>%?++~Tc442TaGEsyHeIoTAX#elVPmDV1_}>P%v(U2dvvl z6ufTK1`HE0?v06iY!a(s2O`(H-Rod*uiHH->vlg&y$KFjDm6n%y$c>7^%ho$3bi5i z2}pe`Cbq`JBQfz%Ogw07z8eFKr;?7k#~j(_R@dr1;;f$ekUW3Ths_6J_W!Wyz2CbJ z^O;YjESEmik+ychP6Q9kYLn^cFLE4_0PG%}|W!O+Y~NF$!L6YJ<@yVDwQ; zd|(5jcLQPE*RuEz3NN6KWNiE-{c{(fZ!yyNED6x(4j^}iSU&i6;sXtz@5$HadOkm( z&-~2c^C|QB5mx3y%}{(A*5|k*D3}km!Dl=8{1p>_#Kdng@rzBVksRGv7WpW=l>S0g zDvfgEP8v1ANFyii{oIrrr$pfAQKq#cr_mo0HDmhCbs+tsLDrNU=f<@uwF~;poVcA* zkvOezGguiJHA5jQh6gxmiGq<)8_4qG6{1mGG>D6OarM})L=KI~B96k#t5KYyls|IY z#l@=>BaNm>ymoPTxwFdh!MGa4`Dq_N1gQt#I0N%}M;(ECk>6ePxZ0r4Z0g`@!nh1r z85cD};Yz>*a2<}}p9XZ2VN$iZQg$vp48f3l6aj_m*AM}}fI>?F`*&(npGHQlGHW(g&tUn4y zMr|M~1G2Vp(IzfRZC*#pp+jUb6or>pTNx^!x7xdS4Z}!dpCn%G9bWDXvwSeFHZEMH z8eGH4Z+ktiqtIvW~kB>>xy?GOW9c*hGvpy2ZVZ^twC5OlwEZu+9=YBkSZsw!a41By!wck8Cpf z%x(^{az-`rW^r9{dJzo|Vpz!iKM25;4 z*5Acz2}T-+#_`l!-a3q=TZjHGUe=DxsJDwzPYt7gkhA`JMoZCW9_lda$BZt7l^Ibp z6r-!*0fAqNf*Da8jD~>G;JB!ai$OM{m2&7cvbYw7m(gGsqv0+_*I}eFERL@@T#Sah z7+E_qqe>T}K^jKale6J^Myt?g4s#d{Wkxr^%8aNPijfHqV01eQW<+f;It`2_$Hl2} zF(EF-*_iH^qv@q!*y%wOUQCk_l{)mMyD)9WNMl;udmBF8g~{5H54}?*YeqJ~g>0M# z*+b-bx*plX=rgA|$fh!~M_^@S)C`5}d3Zqd@`Y%qP#eh31+uf_;;gusY4dtP4t-G; zFQM@AI$MUyhhCM7*UK1boR`F_%Hiccxm!LM*I6!HGc~wgA-`36T(6?fJkP;3n{mAc zE90VOC|n=G11Qnk(m2DY4O|xi*V4FH5*O#k#iF=aU_<*@?(m5$K1Jb$wiJP>B)h}~ z?K6xtmc_jf&@OSHnbwY+WJ@G@rgpxI+9FqdfrjAcG|44;f?uG|T;>qGm4L zLlOKH9zc*@Ud9Be4T9H#;L5nTDlS&U#T7Qb-{k1uW$_0JFTRyBa?ZI`E_{Dtq;Y)` zzEuuBcg|TpnBG+`Vk=zrD>U@}qB&OS>CubP%5-m!I{w>B=; z*xZ8NJGK__sI=SQ;>PbCyEX28wzt9IW?DOP+O3iB37q|2BYxS~20avh+1RZPl=Te7 ze%Tl`LqRFUtA3DDMJPC>sEw4m3sCN`iR>i@wULE^!kbBVxH4&zi%46HH10_vvdJOh z&Lqo+2gu&E|0X>UdMlcFj|1dx210K`<1C?OC?K8T0YK>WXbgnf0P-+^Y>tZuY$gZF zarDYD4DW)%%Ve`FOSZb0bj3(xOWgY;ajV0`w07hyc|emT<>X+i9!fX#nOhtvk1&+( zurd^ChJr#bDMOU>?lgu%Z9sVnP@b@f^pk_=^<)^^ABC656Rs?I)+6jFu<}`O#>%M~O8Fvqfb!Wa7!_(m`L9s^b6orw7vIOlx3>7j==HA4 z&yINWN2sKeJFUz2&JsB5@~vaktV_yYj9 z)wuX8F8;6syarte-nBa0odDgd^Ov(C<{wVoTAkcdn($gUW98HgrTiXvfTIm87!_(m zc_S!qP%7$`iaMq0A=@T7^j=xqhr)XXX;A81d7G3v4<${EH1bQmDcPjdc_?Y^$mi60 zaDpdwoRf8&x_uSCpPV(Je+)JC+4ckIGxJOB2a%1L(SxuuBWi|X^dvk0%_AuI*rPTW z?Eyx+m5N<$Ku^hWPs`#N6kb5P$$0pdu9XYWvlwZ#Oaj!(0p!jK%Lnt>Rm0~w^3_Vu z=Xvy*Ege2Bn9mEaG9PM&;`1gvfX^!^m=CqVrxbi*rJ}f06xoR0l0)B?#XBgxh++sy z-MtwuMDJpx(WcaU;1~`f)7p`9sMz6R7CCi0hu$M+hMv*;=rh|mjP_ziAHd3ts2PgU zf8YU(K10Ebs0~K@f>HZY(ar|+jU4x_EWShG1=L=~!#T9S3(yZ3X>=&XDMy}J#?pCz ze-|KYM^2n}8Yn-JgZ=eTeny|!!GW?LL-_?(hCe(KM2y8_Oaeg%?dXM5S`4rwdI}j5Kr)C>i(1RgMTD-;Zp+5mYNKpt8u zDoVv6HpQ468ka>W3NOV&twMNX<|XyTSt?c0j=psSSuD0dYjB7+xxdmWm^7j^%Q6H(7K? z;pI32!K!RL*2VE)j5J0iaXi-HXsR748;3i@%%Kj*BOS9Q8(nuf>iekPH0iN=oPE$| zj&g7w!#EFtm2pxt6wV{y0XPpu!8oZ6oTmWim{M_4sTggu94v<(DT^T}ye!99@lsAs zaIqYQk;eEWmJ=M7?wnLUC?`*HP>!xC%A;w{33`+x(Pxf#P>y4i$H2-csaaE$lgcV{ zL}gA}LMVXmp|T3`V41kTOx#x{HkDcTX8W2CmeIMY6Kx{JU7jez@cn3?4n#5{KZ`s} z*8PX(m2r0`czdMG+*G!9-aPs)d|rN}q@aK^#(bmHEJ+B~;@UZiRf*#~fkJw6s@60`w&P@0brX^n#VQoE z?A!*Digx%)w4LbPPJP^5g8^pmb~v<4SOMNfHMcZk^lG=6%BrPwgL_Cj)Hwh-kVKaZ z?9)3E=|zLe`?aGPZiXk;OwCZ5e~_BLQJSd@&C{Uyw02^$t@%gTjY&|5e*iO5wG0wj zI%HiKGf!(rFN9}_=48}wp!#?D1AFo4^69MgCwO43)U2u2iNtq0Rvg6?6wH^}(Au|s zh3L~>^lGp8o({X&tG)d*UW;$f_LA>q#J5j-#a9l5VEj?0!?&V6O*I3aSTi+is`;o< zl{v>%<{V2}kAu$BM&T>XQR385md@kNQ%BM1z02vNFyaInHrg^l`%n4!M^HvB>^-9+ z{*Md5iN>j;oL)R4=(KpwZq0H#k_U93gi{LpIoTQn_PFkqPbJ@DI0mYQiD6u2&M72r z9AcP>7-pyd#v5miGG~keNJ?PRGPe{`CYWcDP4?_18=T<|-7`tmL{>%BFsiDSBcHHD zS8&3jLTxBK2MT8?g;gu$pes?Bvn1^~G|d8W;0PO>U{0!znwrd51{(j~E0d z9a*AmgpinEiNC;Ch4=|uOWnaHHK0M2JbA8aHI}jp{nh;{)%9R?vJpbvA*}8XR`;8u zuCGZAVrP}aE+<#D8uP(joJQTBQe6eBlZ_DSa4&^4-p=a&a?}kp2)ra2#Nt=Y$JK~M6v7{V zuZyiEqG|!Ua3!WIBP|BsHygzmz?Ukit_i85op8ADA!9MGT8+I-8Vs>rVko5#y0td; zBp*o;T0=QN<%2J>b;{$kcbVhk7V=R-KIqyNpkuw?gyaC)ctTF=Ts19yw#9{>r$yNG zJb)6QY9lHpX~%9d35rM=dgz+Y>mUtb)?pJ|@H(`C&k9kBty+hB(Phx`xI(3VAa5#9 zQ=AY6OeE$$B}N*;hJ?w-o$D|Pu(KJ`p_=?!3UVGdF z^NnzwI(tVV9oF=|B__$W!w%%rmBd!*dJRZ=3R7QlFv!gfw1!h$D|Rokh!YHSL;6Y=+i?ov;#1f zTzsi?N<$c(-zuG5;S)ci##ZV4js%i?SGrMuQo5DHL}I>IVx%FAm|v8b1bpHP7;Kf8 zKS)du7)-Ka-BihW*NC=N!|-3@JazQ`Y41V1VGkbD3I8=VU6x$AFWc=S|1a#T2C0&E zuhS@(z3hVjIJ2vA@LwIWwQ3|2`d~~(IJUzDp9-WQ430c_;!{Cy_{7^zu~j(gqsur1 z29vB<5ml0uoJN#VjKe~LCa!B$4eY&WR~UI5g--u9HkB1VfQ5X>9`vctj8zSjeYp1` zKC~P0q5m3NpERo)VJ~|ijUaCHAG7OXvFig>#4aBNvy+A}>~@6 zB22}}mmV5~JmC{Uo?OlTmZII1B54StsHIXgkQE)~Qq;;))Fb)qPJ=*;PwtkYL6)M{ zN|7{#QM9L0bOb9p+@*+~*%70XWJWZ|I+k+s+@uCux=NHTX$YfhFQscJd{&4fu~lo= z#?sX@nG_8IDatT?QFU+CWw(zVf$5jQ~#5b>}ux-Sk90W$!w6H$9k7>26?m)6@2p?q+uP z8M^KgyL%?OZPAdMlPkF`MjXWLOccDV(h!E*JhRi%zpcOgcRx&=y|G=x!ifl_xVd{&5M*oup=QRfj(rW3aE zYcYh7U8(d*Ll}M6D1EEp6aQ2;w&Hqhl)h_89~rQEbh!33X^7OvACNt^M!m>ZeiMd} zzU!1eX$Yh57U^j%3ce?yHXhI2f*J5H-C?VQu9E}TqcCoToz8eA9qCg$om*}t^9Gnr z>LaVVJl=*LlN=!s3NRAyatB&+wvDK;QQlgwqYikx9RD5TEv%VXiJ4sfXjb6BUn);x2bmXE_fk<2t6g3nq@E6P6(7Kx`4eLJIfo`^BoHbmo1pOP?tMCyL#q}uc=WbZ8 zW@~7qd;ACE6}e0=uG%cBDsdEI}H=NT6@D;EA5ru>@*ELX;)6##XeX%^tMb z4I8D19?h9#g({QAQO4u{b?TOO*%M9aZ5>7tW%|j*P4P&1A@yK7dRB*&;DKn;b2y{y zX!(`g06H7eq>JaRi>WE-B;-6Kp^qgdsaZUa|NLr0oPLGk1?pfoE`J^{|IKGIFCLBX22@b%&AkJgOp-hA@#mB_n&B z1A!Hqn8@(s3i2c$grh=jM0OHpz)MQ8701)&SlS$ejf#vOj|WHA5PP^I zBR48C@|F_W$uN?h_f%xk5GJyZWn>?4KyXQIL^cUC;2*5PR*a|3DYO}bjf(6OjMGL| zg%0|U*Q^ota7RXNRAl5WC9=sdQe>aP1FxAhgo*4cxPYh6QE)a=8LMS&EGckG~=5WZg9Oq?<+>!qVsLX3|JUI^7-8cO&k* z!xb1oanSc29EUW7iKB`1)EEUHRn$ftH)4hgu?kyp9c`|m&DFHI5*roAE*NaM<1pyM zM1vUO<}BZcVkG^cKU)1 z|Jh$L#W2hyFXRCKFDdP^8ZA;3M?pT-=Zx#fUZ#5YLc=)rX!$MYW0WZ*&Z4%ZbYQm| z(d30|L%ZEXJD1-;TevpJw8m<*rN+%xV{dA#wHjsAxW#JF_XuU{tj0dnSZ_7>y8!nm z9fQu9PE;wMa$HKSPdW5ufvt|dASk=la!y|ilx?sY`%~jKtI?4f8?8nsYTRx$4nV^g zZXHDpc1L61qw&+?$MNgu7eK0J^6)9bhZCvV>DvWcJAI#kFEug=9*+(VnYXmbZP z>U_`#m#N-k(eSdXgDU}zudn>&X?|42Ck|5Uz39^yZ*Gh{7c|f}ag0$K zYKZZ9%u|`ux-zE~0c;I;ufS3vUcy$qfQ^N$z<3P}lPrtpt&QX7`fKAj^+b(-!omow zOMRiS&9(p-#uSzP3l?6WJ$bn8rNa%)Z;snf_0MZee*ov>QQOD``=w-$7x8&cG1f={A zFtZYA2!*`r$X#e=%)OoG{)^`RgEqg><`>%hM4KP5k*h#Wfa#XEf$k;C>Y#{})upXT zgXrd}x_@qEnkrT8{io!X8*asP|Q}sy}xl?B?sg})wYUOQBs#^LG zZmDewwSFQYta>6F=tZ*GPb6#Ozr?n)cGM*hp+EA~S&HCJEM0@xJ^1sWC#`-|m z9H`bWH|U{SCUYZSFOtoEBL8=}(L}G7&HCJEx87IX1)H_)za^Go0RE;v_P+)&4EeoceuHzND%vry)4}n?WGsVW_`N0p*;fiXX|=l==HNXP^9068x8>6i7>-JBPN;hoFo+B0fN`pUr->?bB?wQlhh7B%A$22Bw7O zq9)_n(dXC)>eaGYpArYvs+8!W*Ux4@+JPyN>901r>P52IPvrkDCCc?`*{n~AZnY{U zy6g3`*^hQ$N@V)Nkry?!?P(Y8}U zp2JdqfiN?}x0i?NMY7pXP50yf36sk z4zhjpW&K<+R38YN{b<{2vvsZ*rWeU(KaqT>(5c_=(d3RDufum}IWv7SJxULV&3=Hg zzKSFCBH0`$(r*t7Wr3 zC8q9BN@V)GrfGWpZ1$sVe+u?XiA;-}t{2H>7RgI5|8_D5V>N$s$>$0hmU_}4Yu$$Y zkH-W?oO%}Lsja;=Stie@JDO#u>jAL2rT}>LJRb#W0wDDYkrewho2)dXa3_XTpM7l?e;=`q>-^ z*)J0^eHXV#FOtoHBKt}NyWWP+9nc?4;uF#8QbD&7SOvv>8 z!IgTEY}RMORn^J_KggNZf3;pen`;f^m3onE)=HiurfOy4@K(~D$tph&+XIMd0sUN4f(`sBK`wk6j|8BVSZdL(QPTsOayLZ*}J zHoZtT2a3#Aa&6R$WV1fGZnu+5^MeihIaKP&X6HO~xI?d>&4G}!l?iw1MY1_iWVSNl zF1<)L2Z~Jnfr(u1O#ji!-FlI1)~D+|w1=Pm26RECt6+Z0l~wAm?jujX39^1XY|;Z_ zvmVgBI|PXSP50ypM{TA3v#yfKd#r$X1)F=Z2iF>-P0^bO+LD(X1n{Ndv#9= zfjN_{oAxL5%-O7G{*=wUHhk!KTCbnYfsj+za_4+9dPXmj&3+>7>yO{jSKU<8ui~?{ zY89W;17fouAp3asTg6O2M0j2=lFfl4{Z=v4PpDqdi)6Dt6JFe*Ovv;z@|X1b*&GNt zTbb~(UL>0XMP@4#UeSwWvpy4EtyP)unqEJf10iQC6aJ|e$>v%ka+_Wxn*&8=D_vjL zi)6DtUEiQR0`+Gr6aJ;w&*ngpes_DBKD)lD7s=*8k=Y{omR=;A14U*lUEkJ=WV1e9 z-=RGM_4{Q)rtcHp)$3<-ph&+=$h64!^di|DDAF$zmOEd7W%l0&eP6GZ&H9x1AYDq> z&sY3XqPiad0!jHTXQpqUKhy(abD&7S<;-->eWVx3X8kIDoNg7f{wd`Xy?!>=8pxmO zMY35B`Lk+4_B&KEog|;@^|Lt;a<&e)FZ3eWTx&#rsTaxSK#|!xCw!$B$!2}J{+sp) z)Ss9=2M>X!*S z?T+eueIRW1QyX}}&Gfb42fau(2a3#AO8lr7$!2{@{FE*wY{-5o(apKZ&d9%4^s`<+ zn*$+d>*Vl@UL>0XMP@4#e$|U)vpy4kt5uosyIwz=10iQC6aLVPWOJ<%`KMkan*&8= zD_#H6i)6DtUH?ma_~{S4mR0vdwSMmH>E;eRY4*+VNi%XANbtAQy%zSmDIO`0ki0TB z`vI~=X6sPN(TikrpvY`xVXj^zoAsHHM|%Y7_q%*%Iuq*X^|LupWVSM)u3jXYYmLZy zdXa1n6q&7bt*;l!W_`LgpgjWhXDbsL>h-fZP^8~6mFZj3MtYHK4iuR!l8yBu*&HY` zTj`pw7s+OQx;CLb0`+GLa#Ov2HV2CIOV>{lH7s=*8k=aVuUG*Z_ ztWVeGw1=Pmz+2Lt_IPDCeIRVs2eNy*K-^+3&c^bS4z)MY1_iq+cfN zw39=TUM-vTDY0j*N{M2`6&kTdy?!?PWf^N@ zx;}q~er<;T%6ebDNH*&s@3%vcGyNE>gI+(IYYpW6^&;7C;75 zy?!?PLAD=tq+SOlt}NyWWR@Ana+fSUL>0XMfznzrbQmC z7s+OQCiJLPnb1?OpUt%faxc9|HtQkxu2qox==HNX5OTH-w?p(I*&Ha+@10VaKHU21 zMY36+2^F;}6Z+}(vpEoQwld*Ry+}3(ip*9f^w*1IbD+p`%nSRsuFg+4B*EH^(c?e`W?&12l*<91Ocjh6G>9~*5$IWK_Au!_q`XO+%9toRk znhJlXLw}?`ZZ_96?!VKae~dnEHrF)nztf>VN*_0y^@skkv`0;m{GASgq;NQ`6bqxFU)rA5Aa6Y$CzgBtpDrGC+Y#Q zxu%J+GY^PNKNL7gA2*w88u!jTATk~I$@;k2tiL9VvGcW-JP*wD9r9Q`5;oVSRLFGP zr|9EmbKto#_0eU`{s|0yu8pg0xt8g}Z@iv4n`=|9WjgK&`ncJwPlbtgD%6I{CqDR8!+LQ{JzFeH9kDJZx`Tz2| zP1ncGX8pRIUaQt^hF(9LYr1Yb^Ak#@kGC`QakIImaqrAeD4C9Xrao>q>+|(YJ752g zUUJUTBVlt*Q{nG)2+Y#Q&E}fM{dYP9&eq4x=9ay?!?PiL`$??)Qm0(?4K5PcM?qfg-c@v$ZO{ zNH*&;VNR{egt>bCZ1#g}zfFB-{qv%H3Z&!LFV%MJ!S=j#D`2O&-(S{c`VS=L>sNry z`V3l-PQU#RTJGxeM|ag_=ePPcAiqN_(|{K00kPRnq@6*ncM=7Af}NA1i_$Hzy#m=v z(Z%`|V6)!}*dnu)Cg*6lFfl4{n9nlA}`U4WV1e9 zFQq*K^=IqqaG72|n*&8=D_t+wi)3@4NWXN=^x5?ay+}6eGhunH%7hhq{cH||oUKf_ zQZJItfg-b&30LVwvN=$s--#>J>3X$ZB%Af=x{~$?)bDrVT9V;+dS9d0&*ngpe(9QN zk=N=)vN=$sUnXQ)(lin+9ObZwoY7Y^!nKxC^B2=db3_6n*&8=D_z&>MY7pXr2Y7_zR$BI z%}d1OlhVKN0-MG2E{F}Ijrj+)=9UgyJZCpE2mhJ`zNr|7w)q>6+7QR64e^2P@fcM8 z!xP0_Zqch{vp#Rv(H?$**pFzkmAC8l`q>;PGFy3jt6n6V14U*lZ#U>gve{3h{d4h# zK6zW+C&T(wyRBBG+D1JfHv0jxkB4lf+UH)FY4-lVf>B}R( zG~a2b=ezW3*{nZi?ygm|@6qdLvmfoiV`gTCKeTPqi)3@4NWar_rr(x%uU;gZ^_g&A zt;z&bub<6*N62Y*<5QxKB5=N=0K6zO4luVk!;qd>sHz$P=B^E;ZePQHV2B#)-m;%UL>0X zMP`fS<9d;74iuTKbbUfElFj;beUkPF)SoTLPwDluIZ$M_()DS*NHzzG%ofRK^di|D zC^B2=`mA0goAv4X9PJUPKU14a5}LZ+WUzn~Y%=0K5tnUHCbFX~0IS)U0n z)v8Q*S+AeXwFdGldXa3_Lw>bZL4HlIpUt%f@;~(=*{p}WtyV#PU9X?bfsnIxPJ2Ty zlFfl4v-Q>Azw{#6tj~luYgHz^rPt5qK*-t3gtzq~*&HY`TUWPt^di};&xChtRVKWr z*U#oa$l1z-_w^##94Indnec&LB%1?8X6wZDp-DoaP-M2! z^%K2FHV2B#RwjI^7s+OQCVW<_GU0Q*el`a}&Q>OTp%=;KK#|!xaeb*5$>u1 z^di};P1m7$<+=DdOvK2;wmW_mQ-@mo=e&u!s+yCir>eP$Myi^ZXsW7p63tb$ZekBr zt(R!2s`V4CRkcB)NL3pqN>sH`qK&FHPP9|i{KS5$+9c6QRhuRbQq^4&-Bh(%qKB&P zn&_jd%@Y->x?AEfRoy)?Kvnlh9ImP@5|ygjGI4~ewn_|9)z*pOs#=g3sjAV$XjLst zoT92liAk!uXJV?V7AMY7)snWD-SRXsY-@KO_C!45f_nYde7&rIB>s%IrOtLm%-e+@=s&ra}H3{*WQ!H;jLdTxTB z-%)jTf}b)`^}GZ>3!!RNRU{Hg@CRaU&Y>oMD&po`YVuttH|J54Z#@Q<@dd(fG%13J{G+r#t!7@wg}rWy4;T_DZ@dvP zlr`in*M~$*azwj#xS{#YasJU}wD|Yz9PuX$U^D)v3C&8-2X{@UsKZvJOxuWdq*$_8f=PHvTQ2y!EOy^Xb z&~J(lbe~>v8Y{s-qFFax$j(WK&rCH8yk0ujVQDsiQx&mE;t_3QWoT;BoMegeC8e0R zw8`nyI}(uzNgj}pU1BIBhPr;`$m>@bTkV{S)0iQt*QcTNhSrsX47!eW#|-v`EGNMi zFPb$s!B-2a<|X)CO4T|EKHjNXH^Es=)p`kD5~|iu@Vo=dn@R^?M@k&g4@u>t6rj2<>vdD(&Xfqe>!p?PKO0?ldU zfF`G7gf8Y)C3$rB6N$84Jn!2!9Tv~q#O69}7tXu0w8O$)f5hzTU=>DHHRef5x^%Vt zPlrQee>6;ri!QC?)w=%f9f??XD7aG5j;$JchUL)MoI1`h>#t9mHO%*n%k>%8AZc8l z&$vj#e0kGRPO8h4_A|8FQ=I6v`)Nwn?iXXS_7r65FL5mGWvm@bcvi|1HglHn?Kqb3 zZeD|`Z)sWaA6E8bGJg>7(v9NhOqzuXtw_}djOe*|-aJkxyw9iC>6CRznz`w`%tm zGDQ3d6{OQqh*O7y$ugRR zJ`KuqVhukH@=5-3xPZP(QSi}2ZJgvE8d)I*0DQspaorZYZzR^^-IUG>l;l&GAoCQa_#0ol2G zH6}J`Vo&bo$*XzNHN6+zhn5e*UvW>IkNgxR=c zq`b9z4S6q5I*aFhS3)&@(U>t9JAl!5CB#T}P;GOGafGf1hq&_cuQ=6O(tWfsM~;1+ zkMY;Jga5G}Io8^#>OctM;YZ5hukrBL;wGu46~e@uO8I!aA48ead~~@VH{|79+NwB` zlhY)pNpAhz%UT^@dD`jYr%awcY?0c{wXwL$CB3dKC{H z(pq}W$vL8RKcfy ziYe13jdt(VjJpm)*O1evjTt@3wb!obYLW|)$JjHENHgSvx*u!1KPip-(dhFD z?0El~k4-!CWP9d`X=Wbp@BWmu?$5H_pOMD>>FDzbY?}Yfr=^{Fjy?12G&7&$?|xQV z_ZQgi7o~B(0DV4z&GVa?^X+2W{n9k`>WFW zSZn*ZDUFXC(dQ#^Ra*DA+3we;aeqr%ANSfm?)H~)r=N?QoZHdmb6&~Gy$_v7j+s8= z)YBsib0Rr)>fkJPdQPqhv+L}ZgR|SJNCSC(!^vo?E$LzZc{it<_fh@4kENgYC41iI zG0DfVe}`J#9kof;Icz?=rfTehS({O8@4Zr-=`^S+aQ-Y@KVKgB>F6d$9@ z2gQfz@7DOkJ8zDGK0!50H*X95ye-quyQe*GG@bKez4Mav z&fD3}+hU+kP;Ju9yN`a}_UY&CWY60no$~|q&O4`fez@&?fOnwhp0Gdqd;;!=E^YSY zM+|Nzx z<6_&#Qhyms{9NSZoR2P_+|J2ehEB~D=n|OIoRP1#C9UwE_lk7$uGG(aP5OCnvFBZb zfj%p;8eKkz`3>muMX?T@8WihcPJ`lZThbl=^KMKx?>+i?H>IEV5qsXv80drI0d#3m z(8YL*e%`I==Y86q_lb1QpV2#iHofzI+Rk6WK%byqN;mH|{k*TIpZ8sR-nY^@e^2lH z{q)X_sJd+`je1habKQ!e&nMtwbZJ*HC#MKqy=ROaJ7!v+DKjSHSx2sVLK5R=9Z|dA z^{gY#&pL8)+oCf$;j2o~iA!E*TXaW^a^=5AbO-eLh~5`nKBC*BYtZO3^@`h}GhIY` z+x?n|4n(J4M7`~ZdSH}aL<#iy$nJ(NU)f#JnNIdWc7KX&&>m%L8;Nm#+D4!+MOz-P z^KjdJ64lb2oS}A~YwD?ZfW{Zm@%GeX(@cFb`g|7pM0BO7l26)BuxCzERVB0Yxc^7o zcYs$>bYbsJf}j*ZL_vkz9!eJJO{G`q9WfF^5+Jn16pC0v6+xPG1(71sETE#RqJX_( z#a<8_U;!H_D*t|3A;q_k4HGoO9-!^S(1XyLazqWxGHkZmKaAxPq#<9IjWtgt%oc)c zJkoE0&4t&^FuCx$i8DJ_wt?+sD)S{h2&3Ck@&p(C7`)sT!y~Y{RJM~dJ6HA)+sjmj zqvQonzuzPMUf5hXdj=+#%AV%T&XqmM_A-_El3s+-jkCA7=r`cy#@TDIxm5NFXLhda zCAOET44i$$=?{9Oe-Abn&fbB^u`;^i`xr(y;DCs_B|w>(^(FlcV|?+r|N9Tr z$|8%u|9jqL)}>?l%Unw;2b1HJ`+UhTd0mzG*zQnrMHn4Qt^~D5$u+p-3*hKdS5>dP z7dhv>*gJ2C^ZMQM*5SO)2j^vMcihmrCEv*T?;s`GnMn%?oiiK7#-?b2DL|B8@R4@ zaCD(^Ele&Y-wl%&m8;qAQ1V6?9ZKE=wMWSha>+a3Sf(!dm2w;BjiVA@DYvjqsY!mN z^d&t6qeD#(L+w%1Uan~m99?L93Z^pU%I}&6Os?O~ABWM44W-WDt&84y~FuAOyPMq1fvJPx_s%#Kf*54_6IdSi^uY301?$Lco zgJE>oB8Nb&a1j5MER##haL+s3EARErd9%FpPT;&_;pj3EV_is>+Uomg*Wdzm%qOS&CK2dd^l z?LpOYF8NM4y41Cp^Ew|Z3)${a*9sUN>RJi4M_u=ET^r!&Lgl?Mxs-elOkPy3VY@@g zn_+Y)`F^N9O5VjKKLkgYx*p)X&Qxw^yF*=%!01rdqfmR)bw#RmMsAfF;~2Axwt&rr z=4LRJfzv^3aZO-y`P~{ft~zn%_8ytrx`)5gGkhNo-_s*}57=CQb#u?$#WV8|&OFc~ zbAR{neLcfxarhA);WJ=!0XEz{^DxiMd7OEaN9G*&@FP9L7jpP~kMI**_=2GJAp5a$;_@y4< zmw3il$1&EpmvNU{2%m2iOfLJ1FX>(w9k#*sPJ=|gPiwWIJ!{rHcT#5 z9DvD{iVt9PpyETQJ*YUuC4KIm_fxODUpePJ?49>V&U+M&E>wIElOq*$L*pmsygz&A z{e$!V>J|K?bMRB%!IS*fmBtx3x`6t}D{r#jaS~IY_L#(qoVNlTT^Xz79K5o3@QXS4 zg>ZBMb%9sjn$CG^dFSqikMKQUa{<=PJ#!b&%tJWyK#$D*-NX0w44=v2Gd#i%hs_1p zFt^O&(kYk2kMszCy=RPx9AlhEj6B#}N*wJOzL>+`;1NFGGsevv<3{%~rnrUh`6j{S zvbKFmx4`Id2D%k$kIic?mo(cw?@X_}w>#&Z=bd*2=Uoa%ml;_ClgnYg2qsr5R>J5& z#VV*hs94V>-Q%8jjaS|c&UrU_=Y4?lZiAx>6vnjxM0~c;$W0Iq&n{d0*qaFM9=l-8uLh-odK}tSgMFftaNfbKa@~n+xDd zFgebm&vzb7Ubl=YuwA(|(;c@#XaQUZWBh`*9$Bu#MPCXpW&Ot#T?;ms$}Z;2&Nq!} zu)R!WIOEpi^ihxWVfXYw4)2`a&-OCueM$9UbR(uYSJnhxZp1W#&1E(l!sNnPI!tA5 zE6dpeCv7?N6&{&eyN7S-8NL^X@8J=?8*DDXy0~ZV#F?FEqXXL=W}`QZZnH6ziyj0o zx7io~n+xUrIJ0wQeb`>6GE7Mhr_b_8p9z}_XV<~xQrWef*}1Z7*j}bGUs5iNZk*+F z(c|Ie#@SfdTq+yGnVl;e#r86lfwNmU{WOpCQ(<%AY%)wPm6gEc`UpS~j9z=?4Qww{ zwlC>c7~Ke+&xq#2%Z<=Eu(^~y3ntgHXTa!Hb}8G-lnu65ac#@t=T_TN*j#E`0+VZP zi#WIQN?5>lr`pzYZTG;>t+q9=xvYe{U~(**&TboEbeplQoO!cH=1uP5!R#)M@sLN1 z2Virle!F{kU(zEmx>f%qXMWrx^JDJeQT}2pYIu%yjJYfY%jAa zd`U0E=mz{9F8Tnx+!o9musN;@pYJu!?7UuIVSAa%z}Y99{zLe=@N&>S`+M%u@vIMw z@wo9!^Jh>iK;wTv|CUQS?4I|KSKjZO^M3E0R|{I#wEw`-g^JTKxlF{LFnKMJlWZ?D z5qR-I(2=Sns6D8v%q5=(N0+)Pz~oieIc#^Rs|t(`Q+Phq9(C2`x-NmE3zaotaw+*D zn7m59knIj7*MZTYJLYky83cn=el~c-J!0*FgnyV1Zt1EZs58m!qH`l$HU}O@>rO>rg#k79ZD{Q(V^rb zs69%)g-f0WN0+*$a$aXDC$rt5u3KSrsH+rekGd9fT?^poLgjpzTuQzjCf6&&+hFwK zc{bY}@GODR0neRKd*E5ec-FwtrRck0axHolj9x{rV7o)n_rmB<^m?d0ir&se<0YbQ zldu^kM?7?$yTdu}1KxQb<-9w+fq{Q(k%ZIp^K)o%a>a`=VFy zSDk~u<{kVS4*pfFW6T|~FJW^5{5edHv*`1E3X@!T%EF?jmBjBHKXK+`9+{80hyTtq z{GS~D50CJ_!R7+&7x&D^Ju@eTtgFZ~9-04f4}aP-d_@jlA>>;8IWW1*N(xLav*Jst z1f#>@UKwhS!~G&Isk(dKYF>FScFtSVJ8zit2H@y2kEt-ZP*EEuS1KYfI#3aX+JlPA zxukUWy!E~EHge9}*gJ1q&U*zMU8raclM59sVe&djG-rF6W7(I~4n_y6+C%L@RZlLt zI~-l=>dJYYuOK?J-Jz~tFgn!L8)}cbuI0Lh!O?}vAuzd=JP0N)DhIILq2vr09ZJ3q zYLAk~aLKuFbg3(w^Ey+R#de3f@?dnRYb?|rbv;`zRZI3IC%ss&4qmvMocxk(lU_F4 zSEx-&PI*=KQ(hBoWuMRYbUpm0nO{C7y`Y17Giqli&}FTA=;DJaaGlr>&?C1>Rnm{WWy&$*b(k?{pL zBks7oZ?f`ZAc_YIZ?RcHAX#`5rvJsl>#;sc43&k0@N!|nm;9lZ z@nbh5IOta2I!Sh}?{w{ozaZ=gg9NWs#(xAlZrEFh11HNm_dOG$Dx)v^r|I# zjcbX|Hy-MK#cF-Y;{7_6lTpSL5rsyVz%6#khUjv5sueWHGSWRWpBBR4n=x2J3DZRh z$;mUglpASO?u7ipsS0+P7SBjnAw`|?b+aY3vJvw8jXupH<{QY`kgV|~%29}#;Ps>8 zb=1}CH^u7&c}=ljL4{fVnN)ogszm5h%AnuLLl$5YD!l$yy#BPk_zhRGOl^}5<{#TD zE>?=-<%8@Dxq{+V&i0CnRY`ayVZ%EgQYG5rlB+_hC^o@rkT7?cvFeb-#+Y&;OEpZ1 z7Q?xa9gzEyDw9F(;z(`IoiC{hsRxe98-+Irvs!Le7m#VtgaXx2u5vldVl7y#xxR?J z9I38tdL<_ZAj#c4Xi8M-CH6>_eqT}@GQ^ikyK5>Ly633{rO?jlCw;GcMUNt*P+CQX z$iZpjJY%g_o$|p5|p?7{x)0Q3ciu>gk<55lW0YbAoUw9j%J|9T)pdM6{$mGoXgHmf+SBk`-KPxNP38p9)=`O5j!EtQ^YP)qBVU#WK@sW#LL=>X(k^aWwv<7BZ}se!VXf8q*cq>(yer* zoV1-R*ns(E^K{uO&i~am+pE3`WNlP#R&hyTu9Z>KkP)+eneao!Np&DuS3tFB#DLt< zMZI!k=k;RCpj?h@6Bq3@OiQ2qn1xWC)IBD~{C7QctWG*!k-jd>*1;Je*Uq`w`8oDQ zApTQb^F;U%89U_U6y_H3!K-Pw`UsE#rN-q=CADK-WNiYYmGyFRbjzxf(J5;KGL+3) zkJN5iuY}Rc+L|2QvbH3nQ`Y8WD4Vq@sok=6h0)5|i5%Usb|9lu)^=nloAoMEyJhVM zqm{KcIl5)-Nk*rvJ;+ctYd2E6WgQNqm31gNx@8?qMyIR;$xt?He^R?;&4JO%nnjLo zSu@G#l=V6?l+AiAsokx=8@4U>u55R&6-PUx2#iOw6d0vqg&P@GCF0w zfedA{=9Ahj>kJsJthbV*Th^P&=#+ID8OmmzN@};Pcfe?6y`3E0vff5Ur>wKdP&VsK zQoChc1*4U9IXUt-D~-N{E+v&)Axp@}g~$`5rd9X(7LlRH1pK#WvnMhE<=15UPmgoGS-sOsf@eH5MRb>p>!!@-3}^)PEQ*kT_A2nZG==!OHN8o z+5|~{k+~1jg``W~45>PeNWPz?Ei7$iX&X!1S=zzU11vqr(nBmgY)W(@Ujx~diMz0IfnWE-Aan6F%Jm7u71p_i0?0I9sVVe=s*+yes5A3-Wdw+WIy zg=Cfd7Gw=qQ2gI5DUPx8cP?jUv<`9$WjfqUc|bKSyz*FwODrv>n>&KGL~wyUmez^vgBuLfOSEZLM(+@ zia?V5MOl}|QeBqnu~Z+D9MOPv=`86iHDu{>NOD9Y)-`6S2}@1cuNmu_v($p6mh9Jx zb*))y!_pP(cO~ntVyP`l?bxq9>pHO1k)=-T*O_%)SnA5wZmjFhQV*7{X1|^+^d$@ySQ^OIL983h(h#-|W!*5Au3>37`(4Yr43@5AX#`7|EM3o179=_6 zBUzWtQVvVGERAAmG$c884D0e(8q3l+md3L*0g@a$k#+ej6|i&z`xUaTh^1ndN?4i% zNk*Q`x+yG8W$8wirm=JrBsunG*4@I=tt^$YG#!#0F@tq8S(?StZ1$VOy4zTq%hK)a zH;;AmS$79Z3)s4lb&FWHn588w-N}ASS+|U(_>ocr-mUVksw~uxES@#@E&$IOf*1gEO zmss~Q>t12qt1P|7*4J7021{?Ubb$TdV%^&;y~EPG?Drn)-e>6`OCPZGAtcG}N38pp zrB7J;l%>xg$q}Ek?hBT_Wa$w5eZ{)NEPc(^Z&>#&OW(2ed)6Ic=_pIbSo#5ytm;SB z{lwDGEFEX*1SC1)7uNmC(r+yN&VGNe?j%d6So)Lw{$kx}mi}hxAC~@wBr7<>lJ=l= z<>q54iKS#nazqO2%CU3~OXXRr07;HGmv!f{RFS1hELDaiM^s_m`7BjssTxZcK$0V> zv+hFH)nMI4th<*e{iJewG4k4YDr8QkbO(`$buo#!_9j z)?;0LmKv~>&VD-U8nSdbTN|;iF-uL@+LU$8SZdDJ7OZQ@QY*H$W?dVWu3+nxthBYL5C9V8if1nV+cx}K#h_8ZB%Y?g9Z%4NS% ztQ*bJ7`EoIZY)dV*gBqd6Ihza)_m3#uyg}k3t3mhQZZXgST~8K$t+D_zp1Rdk)>%Y z-Ne$(kR*S%u4f+ z7PGX3r8`+#3Q1yH#=7M!tzc;-`>kT#YL@O|>28+RK$4NyvhE(1*0FRi`>ki)29`Fm zw27trAj!y^S$986TUgr4(l$tP#CF#0VCeyt9%R3VSobhXJK4I6b&s(0C|e(6-ENj1 zXXy#{Gg$W|OHZ-%G)sFR$?BhB-Low1WoaKv`yt5@&#~@#mR?}#MV4NIBuBi=x>s0w zm8I8MdL5D+@doSOWa$7)Z?WIotb2#0ciH+L>)vPSAX`6R-G?lF#L~y?_X+DhW$81P zK4-r#SobAMhgkZGrNfXU%CA}X4NKp$^d0+s&$=Tl9cAg5DbWqRf9O71+)a6(^#kf@ zGV%>l7P;=lDO|z?qW#dzF)bT zkOY_IYFW}bmp~Ht{mNa+y31Hsn{{--!Eiv z;`TTh%5eA-X&o5?Sx%l|$2#rkr z;+Ulz{ngQ_uxmwvMBq6_+7#mB1@UoOuq^=AqyVZ zC>f8nW<8=}a@v?|){$Y(rFeLSXrnEnHyo^=4SGuFQFye33#Nx)eZC%K$%=g}1kcp^ zeBH=UBpy8HArfO38LTMgNnW|-bt01^{0^2ysX)SSN0yQt>z7shph3|4kQP6o6qn$q zl^E!NHVa02;Fo4^201FThy9vn55Ip@(#{jl25DNwi8X4p%)7eH(54+aEqmkLJ4X4h z?SN5Qmo^zk)*Ij5{a{8;N%pwR{E?$din6nc^9#%Lv$G0{it{Jt>Jzex@Q8KBgrZ5= z8B^jl3vxzkHMPsM+FJPaw{5yhA26qNu4?Pk*9DFRe zGjt&MN${QEhoSd_2SZ;5{|J5`{3&!K_~ z9-I|95j++8CHPVJ*Wlyf--0{BCxZ(^b3%Kms*DRz&7So{B7qycSs-*&o>uc|Ni+@_uAfWLM&t8=aKItrMaLpxmtC9Ak?U!xMXIf^_4bOI$r5SrQa)+`ltJ6f`r-r+x&C=w}Xtu z{w1JgxqpR!mH%%4I{&@?_5Kb1jsE-moBdn-+xod2mcA43C;}7#-z;+%?sTT zS{Pa!S`u0wS{Ygux+}CcbZ=-wXk+NU(EXt;p$9?_hIWQ_g?5LY2pOS$q31%+hh7N1 z9(p76X6W6}d!d7&4?`b^4uuYfz6pI7Iube>`XTgF=y>Qv=u~KWcqS%(PIw+Be@S?0 zczJkbcy;*h@Y?V?EQXEYEm#ga!Viach93z(7JfXuC%iBGT=-=yj@QF)hTjUm9eyu- zF#Hjg%je-Q!iU0#!{3ClG{eWjKZcKoe+&N}K8YoDI{bI|On7=^R%A|OE*8za$Q_Y| zk;Pax%dmh}Med5M!SY!bS&s#@5sPPYWJ_dQWJlz|$irAjk4AQ5F&S89d$6GPVwpW3 zc`@=b7S?N#HzEfjZ%5w6lKUX?QREXWw9l}}zQj`d8q4o{EW6{8+v?7(d!+8C^&V{S zP=mb<-e~YjT<#l zln@&?YSf}d3%|crlg753CX_A~h>Yh<^k)pzqV=Yah74a3FYVUp~B9M7Bwvfx~F3h zofdH3_}s!a!Om?m`W5DnF3g(X?+Q(kzwVS)E$U_T&dbIV8u_D&{X_DKO0vfL2Nsv) z?RF!#*YvBFGOW}@zjFc99*F4qv#}i;HT%GEptkZKjm6yQ0o+%RhT^n zRTdyMKJa$~CF64&W@~y5o-5IZ=V|&-t*NFL<&1|ZSJV5B#{Y})|B+2Jy-Roa^d6+? z-3H?SQ#HM7UUA=%W4o42L;xvw&MMA=od17$4PaHBN!KcQvDXAj-T5QOB3aJ=WirkT2Z7d{=^@#0O7#ny_s}$AIGBd~LXJ?H!`6|F4>lKg6 z%rBt7%)#T@$>l2e@wKD|p5&fSLMdiYODSE9jnOx$PEwUA@d0odJJEUk9e#}e4#OLm zaWCuY*LXRz7=FV~kosqjomL z$3k2dT}Y!+eAi>t9Wkj?c$5q;T-Hj@X^f9=FH(#A9Pl>9j8rF|M&g~!TIm-}@No&I z(uVgJMm`}%W|ytBAqK9dfloBUN1s~ez+`JOUWpy3=A@x_(a?ex_^5Pm=i@yoyVJbT`5buoEN{v4F=oi(rO9iP(Sa39u z-qb+rCO%;sj9W|NhW5ipy);d`L{7aqu0hN=H6xA03#_%$HvRGO97bLiGqP3$8Ap{l z@;hPJIvSRLEk4f0!m*FUzrwyM>FO{w9}T>h2L79YkFR0|mW%kRv{MJFQ$YjQ)4&BI z@bMHDot?2N2G)vFq4C7fs0}pg`9gfuZpouSOw}mrR7S;@xsk>VEXKzl7-t{(H0}hA zE1Fn_m#dL)6O9`-10U~Sr5^ZuFz#=49PgvoVAOpyYT`_M%xlZX(g_SHpQdr9m=T+4 zM9W$DIJX_H9_2#8EIOg?>E;JNiTQA*4QnkH2trS-Cw1`Lrr` z4%O(2H*@s({E@hl$;0;tk%~sWjg!^GH0l`|RS#cqI*p-G6&@Ml8$Q&RH`I5-P~YUC zzFUU+W)Ahu9qOyH+KeWzfjH2+2(*&|Wj=Lshqu;>H0bROf zHg2kwehh%Pd6<%PK7JUPQ!_J@u1LjoR&HiNJ}$9x3yTote7NCXMQ!^3a;cytH{%RV znkX4+V)#vUGV}6BmW)Ek>M~>nt%Bm;Qt_`%>4tR6E$-1dlXjrB)kF;yv{m+i?mg5D zm*eM$-)(%YlwjwqFqeWMoKMy3~5)B?kW@L5WFjBJ+B(r zufu>&V$ufo(@KvcxR|uTa9%bfy9760Ctw8Dq0Ca*%JR3(M&ss6mTDMyW>9ufCcYJ+ zstuCbirUW(x*KT@`eaQI1(n`q&B6*BK=&Rh0v)mQ>LWJRWo8k6&A=g&g(THwQ5CgZ zcVo&8=9(6}S`Yf`i5ca=y&r#gkHpKdtSe|IY*5Vj(?fc9 z>NjR;5&lF<(*mHgqPBD}io?D6l5AR5J1y*YI;*QvwG*<&)(y z^q|GXKVZ$pSV1dl&|yGtu^0!m)=E!VIC^R+lT93jxuY{DV#VNV8D2o**Gg9-@cjT$ zQJY1p$qLP@>VB)@llI&;Ru@$zu&CK+8Y3}pT{U3)M;Qll*>-`J@)y3^#7z`m%j1_e z^Vm)WjCV0vDSOJ!t9cQ@zFpz_o|xDd8-j`!%>)_4nxLq!EH>!pSlByc&Mt- zk5}+ygZ&RJ_Rn>-RnVF+`Mm}x#qumOw_C*m{lmtq&QC?att^frI!nrxk0Yp} zc8u1nICZiz$7u!aPrIbX>Zzg% zYz>rcwX3?VHixlRqCH9EI_ zyT#on@z7Z>Ioi}vkXw{K0q=p`jr@CUR|%8w4f`D?X(4vGN#r^pJ7_TkV(Jyb5z zQa*B6!+eR!H1B9pZmVfsP|@k8oE(wzs>2kSx$ViO zjpmS_;wRZN)I^=3i(xxH2*-Vw0RuAo_LQe`an#eOTK1?8oz!6sQP*U#iW|3}WlSf= z3R+FoU0qT-j6d@^tSOcOpS@CGD&K!lZ=BT{b!yRUnAi%tbi&?r2E~g?%4sRzx}&wX zU_$#f(56(!-LJSE+q(0{lU*Lp-wJBhT(0cFjln+e!5;u+VLj_mEda)pA8@xKF0^^? zf+IIWRhNh*X2kstmdSw%<(vNV?h<1V^&nG9H^K)K2Uq1+T%QV zEpW-ilSj*Q)DXODsJI{9PR%V8S2*`tB~KMA1dAPc1*;bubagUf zh?-!z1@a~J^huY&JatKk*pvbF>!jeJ)5+1M6X<)CJP7GzkAErC=@xGmeSyJujLcE= zONO}q07;j^<%pl=G&p1+-qV(wMHk~EtlcWLtTH8Bc0V?6tMW>rHF#7+y{_iu>@it_ zK6xnpXcMI#NCfMYZK5*^U#e7w?Kj(|E~;~Jx#|7|#Xf>)2gG>(a79hmz4SJ#8A*7y%deHL#BA)rDZZli`;|onxP&xmrEeMdS3E=v6lQ68pq z?MZK<=w(_;9ryhp)7~s;HhxB^irOOe8nZ)o zHs0qV7WM*FdaDx@N<_idqwALj`SZ%x;H8!iUU;2$|Zw)cM@OHaPL%dTTxr=peq@IKfuo_njmIjmF1a37_Bdenb{+S zwVFI8D`?I5=%=r|yqi@*+HYtp&B-mM=litMNmjhKoYhmrF4nXOg)b50{yl_V0!dFX zVfYPlnOD?aY=EdZxkDGSHijo1bO$KSg#4lw&8JL(Z@T6Cs*C=Gf$-0rL~&bMzWW?> zQE|~S3C~C57t&YeOmj_KYz;bDpRQ`M3ySEH*|OHMtX~N$T?&uPDlE*)EkwRl%XqsS zO5ZYSTe{_#sJ;c@VPX!{uUjlGb5>6tWJ1m~ABD3n-0NEL9&ARuU|UACUY2sZlX6%q zcoyJUPOWs1Md+aYh!)S?^Vd#mMJ-$~h{A3Uef@56AN zWw~~B)RxfojXXuu-ceEOZxShsy2BdX-C3P;6%|FhK2j~SoHHG@9a~|}5SG4g!Fz?} z-Ofedg$tIotm6T0hBG|~cq{s$=_hMF9&ylV{o!X{o5B5*<^C(hb~d#Yb;@goxmGQm zttBFB+-B)px#;s+nk1M<=NxOmE6U+7V?At{o^v;SZ=Q0qiT{PxfTm5b>hZK?LFUN9 z%p7|6idMSIGB)xu*0a`=EWxk_1zq&rthviBq=W1!%fFM0{&ZtenIv(&rRxrxPyzMQh-_F8UFC%u9M+ zvjz-xGhE9HQ9J~#mA-2Y8RBZG#}>)y`__=!ZiaPbzspzDE@N+Vac#EZ47o~P!!qy> zEXx2_%Wvka+4JzSHK^MFY$xIrBw6{=GF;(iD5ecrUTt6rU_<`iT3)#m@!U7PVp=Qh zZiV^E%Q#scDD5U`TIo^CQs33m-#jEGUh@lQMXgBSmC8dF*djWvt|mxfD?1aUuBsOdz%eWFm3OG?C-3a z2g_RIuX*wt-WyiPzSf$ew~cD0H(O)obF7is_)7|ynp#7yG>701E%2)|EOV_vkDDtI zYYit=v02QtY)9n15_`(_Sn>MF@xO>?A7W!`VCsEs%4vr)~qihIstsW5j`ZgKV)S^GR`J`YRh z{A)`~(ft4W*Eh8^rRKe*ef_2XYJHnl9(BQG6_O+6OSe)*RWdF}9#Tm=zi-kFb^7{- z_w`*fP(wRVix$=C+N*Ch>RsE{ml2&*r^DQt8!KsTit9ji-JqmFzIr5H&~1=52#>0s zIrHDsjPBKF?u^i2{J&QRirA)UDwWUzNdzeBCIqUZ1l7g@ zMSXy315m9}^%kjmGe*=2CZLswY7wGVHln5|zmhhXP#G;GAVOs{lYj`7S@{*B^3Dh* zDyMEjmG?&kP|#fz41xNnybCJtl&W_~)!U`&S8?$JV2##Mr=ycyywL$wTGP=^RxhUG zDp~#io{p{p)IcN=ps1S=s4PSPmTLqS2-F9t-T>7zRqv6icVk2&VFFrZI(piO)amFU z0g378CIKna(MMFCjbNg3>LyfqAtIpQJW((N>Z9^usC-DOJ}6ZmkgE6N;)`I7)>Efr zh+Vuf2vu6sF+f%?rlX&%{(n!$H3Af#Y?q*@n-Hi{L;#j40t*D{1Jv~ZH6m5dNY#fk zqUkUJtuh@WY((mGWJo|_I)+O?%5-Fj%4Z;$m=5YDRQWc<)c&e z+*CcAD_;at>~THXuH48)iI@vI26V;Fy%E7pLll42AxDDfZx=WJ58El{qOqJ1kQLmhA{HuuwN4EKeW; zAnX(nAW$DzZUL5?QuP}dhyi^pkeh5E>YUtob~tVoIG#jwfrGjU;dmJlQ2t&~J_PCm z$8EqdJ5`^Vs!wMqufP<0gwM927&DbQnSORy<_avYBD}yt-Gs2bj|hP9rhou}`oOXP zSmvkdw=1L!HaFe0G*Pel0;s1F<~fMZ#zerKw_ zn4x?vUB8jdw`gc9D*X)CqU~ptPd1jxS(&Td?vJic#dXzMf3Kbh`5io?t5Rcki`6y@ z)h#;R0!%Imh3f}^9* z3XZ6o5J$fw0>b}(;wGRCJMX@$H^K%+DW24Q_2EotY&rXreHiXH$Yx*DN1v`e9=5?IKv57UbMv)e(IqS{7@hKybOL`Ox2%H)%P<+O{8m6*)&5FOVNvfWUZms6pEU|Gx}<3 z>~8#;O_5;^6l>^t$+O^SzXL}tDA;Sx9JPeac-7|U6~R#}Xaz^qO^BmThyaeRL?bw& zJ~(<89KD^YA7FwyOTR9%>53+nptmJ9v4##R1a*UF^!+%34%!5%Ysict_&MOfPj`xS z(3zheuo>^${Jbalxf)u*4|NmbXD}jwpFU^=Khy_5Ux1&_QuR-mpCQt3sBDIziRI@r z;IS6aR|-GZz%zO%ZlC_j=EpDxiUstEB$){EzJ9mPY{Mz~SI&%G3!8DsX6#GBSO&C$ zG3qA7*eFB*W7ne*j8PwqeGkUIWx7U7r!lh0LlaBax5{!lrqDGOp3$RmbRDzlQkRn% zL$e4d_(|av(X5~s1L^e0b{3`t~;dD0@*A?6HC`=WqoOMzs|g_Tm;YPnK-&MKi~LM z*OwXNzpt;w6kPKoM%nAkC9oN1Y_|RtY~2a1V2ip5v9%5nz}6}>f-UNUt#kcd_40nb zoZq_Ld9Us>?uTd$%K zY*8O<>0qmYU$5ua)BJjbX?qXWXxOjZRBvEoH|m*djBcu@nFP{J^$29^rur1Go9Yb( zs1J}tfTC_fpbjGfKz$;xK%hQAH3z7se!a0@znl?$4HM8Rw+)-xh}79^ECJDM8kb8z z%B{8*qVjJLOjJ(Ygew095m4|EQ7{DRqw@Bsysclq(yzDi>#ex>Utx`%j<$C3#+9g& zE?H~u86ZyY}SO2WT%bP&+~Kq>)^x(Pu`NfyxlwxCfT(7FR! zSHIrbuXkizc*^PKKWymMnp#5yA^B)J+J>RfqrxEd&Gz)CZPPz>?$F zM>3GM(8mJFv4N;_GV<(jj21ZBA-cdp-Gp%TMg)}KMU)SL`oNJ7925NdIKQ69Q2I#M zzOw0uCieV0LC%V}=ToShfBVBTdV@c9Wfs~j80J86h>f#pF!CVB-!~jU!3v$vw*z4_ zZm`d{1%jhN&>Vu;j!O;}IK8XpsUixLpW+a+ef~H7p;sWJn zg`jMBMsJEE=w_QBb(xqk#O^uCfu9_Tb+a=+xv&{G+5Ais{EUKD@I&2%_$fpL@G};T z;D`F)XD;}e%h-izkWCKbGP(cBb&8oV)DnQk9+1t0XkzKY+hyt7p;%7a6}ldRXLMT}UE6KC)a7Kx`0s2zOu@H1 zv$Yd8W1G#^R>9UTXa!r;O^B^Mhyb>BqY-RTA8b7ews!gThncWvq~Ei$*^4HYuwBaf zdR!rFA3USG3lYHB zt7rsc)CXgGz}Qnv*W1$R9of8#CYG+Jl=Zb&q3b<(MxTwNYp+e0y1vX9|9ySEPr>&( zvvm+Q<5`=nX9QaxKr7gyZbEED@XivjbtxLb7WKhaxjH_yTe#qpyNzOd9E%`9Jz2~-;tCwpO$f(KL_qmdMfnh@4;x#$K;I1RuA< zS@1#Kg!ovA2%uph8nIrf4?YHhkNyF@Z$R%I(0ei&t6&9J%DncsnNSyNUrB^mti6>5 z+EX&2Oza>5WHkZ{Ak<9=$QDEZkb6Y^5U39z*8|9ifSwW1hX?dw0euK#*$RhPEF)|z zMg|JCZV?SvzzkEs3@HO9OMuyi$N~&?69V%DA^^if0s{o<1I$=}857V)1@xSNK9Z3b zumY$uD`ONSqZA}LHWE6MoRLS{$TB#_2^>!%uE0UvgmAos2q^zqQ9cCf14j{X+z`<7 z1NsC8@iI)YAa1Zhs7ou~5yONs7>WgkR}fZUpl(7KK0pMN{-!7$0`-C6R$#a}pic|v zQv>>BhVdb+v8(E4XBg9L7{*j(QB5ubq*MU;2!RC<>Lvu_dqhC}pNsk-P#-|<0FZeB zeQrRX6VPV`^cjrh2ppmd1JTdb%b9sL9AhqOwYI)F5|7yWX4zZc3<>8yZGAr?pRusa z)+aUg*0(_L@e`Z{AJk2VkADyWH2j7}Y<<)RA1lGf@_@cHpf3sNi&LFS=LfwRb)GQ}}R6!$vP#-`x0mz1ces4g(C!nth z=yx%eT5yPN4n+S_Cw7Ak$G8`@S`&MZ#3LqljXkk{W*rA+JtHWTW^ZkI%eiQTG9 z?ER7nWnv!|KpG;j07Bh_fLwtH0Mb;{4}tms@&thF4(N{t^j(bNN|>Tg#$BfDwt*Or zqDpH@cS$5PrQ#a{U4fWLUFMU{7D@8gDErD9DUBz~%&OGbvuX%3I>1?wLEVJN=#2>A zpeq_NtJDV>dqKuC0sU!aq7U?-NY3ZwbnW?!O@lh0PuufpUM%kurS?StQ7Uy4Dm4QU zQ0gF2Aq489)K^gIO9B0bfc_j;dmT*C*WwPvm+XR#7nFH>?*GZWWg(^UTA6v18hhSe z6=aNrvmk@I36U`o5x~J{G-BSU4>H~c83zLT8_YyL^q@$Yw*xi}>b$*CX5QWrr4}H7 zD3!Vim3lKGpwtpkAq489)Q?f>hXMUyK!1;`y+yj-Dw|R?bR^jiTz_az8$B%hS-^fU zW;#5hp9XL#CxJGh1^Sr{)G!Cq!D<||ks9wo#&=$^%UHK4XHc-u0wAaCgD^8;Gd>NV zDEamO6T#6eXaz^qO^BmA5dqZPjz&x;^}*2*aP(b3|0bXx4(NxNrlrz*nQWG$iKXc~ zg{B`AnpVIwdMproCG~?slQ~e(^o>H(VP#`JZDDU zdhnPr#7XS913%j+)=6i6w!>!pVe|95;AaQ4f*9?{Y!=u-gOAXi6}4J(UacojH{vGlrn(Uu8M{?LgNv z6t`T^@d$htHX|j-M__W0Q0|3R&_&&Z==vNH5a@k0f-dTVuKJ*>ZcvW~^>9!R2CZ9f zUr6sSWpfBkEMs-S7+n|8Mx`r^eFe{GdNB5qSGO56%z@$vj7r)CW#OQ>Whd_A1fh@L zv<_2X-I=nlVKdTg${GmDzJXRyM%{!c`xOyD*)cSNGU|h}mY}S8P;VO48#7D=;{*GI|cO)LA@O_c7gP+E}IL{#4^?esH_!swZd2p zct(2!W3Rohwiz?bfntSqlC%rTIw+L2bD-=Z3VgLQWf#L{^sp)GE-0%Bt)Ps$2~ie7 z1W;BRji8MBpllE*8xYj{1@%76S5&&D$)+xvSiS~GsA8KRs_<10p3xz3d=0hvQdgK6 zL(tVvp{tJrUG*vMP-nUtz-A1w=^8BPN{3d^McstxYJ&)%t1%iu7xh6`4(J*g)UOZf zBZ7JcGj@gazEU<qRL|Gq10A*d#2+F7r%5DH<`9Xa`P#?#9^_8yuWYZr_ zEMNH&s#syg3SR@@87+$AtJvmCU14SnLDvL@u5k`@4Wzim&U6ie%_y?zDim}LhE~u; z-Gu1MMg-6`9F3rh`k-q%=(;ti-yGDZ1@)=SSdR40mCYzLv5egcRMrZcr7$)Ip3#}X zXv}XNvuwr;bD&sZH%rC8G^F$&cj}nf~Zvg|A!S8C?{|*J7J5 zb%mKR1YPrj{M*o6cw4^>Szm-oDePirwx+{oEV9{JDA<|-tze6~39+>V5x~}MXarl- z2V3i~z}5!!yMy}bpuRGwFK5o~lmnK^W*M4T&ekexY=gqta(G792V;LE++cHNm;=Qc zyIWaftCcmjQjwQCthW`EWP>wKB7i*ujbM-ZVDCw=_e4NO=yV>|;jWl}_);=6y7=jOO6Q_|^A+5CkjmXU+XD)~fV+~^f{@{81R>N1A-{u=UxWII zp#F1E|B;!=fi?O=P~O07PB$=rwc!~j%#}jVIQ?vLL_ai$-<$Da{Aerjo-&Vjd;KBM zjYc+sj=BkE%Lta!B`utXn;^VU3-a@*%#% zWt0oaeV*ne8M66^l|3&$Tj?+_@JU5J2!w}^rvP#=}2 zqVn1y{nC(LE2Li>(ra-2kH8^zf@<6K8<(O`IuX+Z)w1WpxHu$ksL`QQ!&W;?k$8|u z-tG4bh`W(bK%{O$5MMw9AbUz6gFt;iYygP$LV8+AkA(D4NDnZ?7vT^Kv7Q1kO@SD( zu^1s6V!&2AKrFKg(*@91kW~PsZbCp0A_DNeDeys{K7cj_(8eMC@{q1G#1EwFhqCzy zP3(!GF#yk|?>@8r(H3}Dq4hV>AHy@+JQTaVv{2YF2Z~eW<&p-mf^}Qwi>ps4SPS~q zw(L(opTcG|5AluXW`d*7pcNcZHzAIWAOfiQ3XM2RP#+w%1xHtg^fpY;QR#O~Hb0<= zCFn|Xis@ZD9Tb9oglDvU96=pyg4842j3M}GA~c z3Gwp}B7mRY(FlI14}N-qpQ}T9_mJL|Df(Bso{GE z>?YXPrpPb{iZ#^T=Edl0%e;p0pIFnPeVsWbJSaKlme~bh`I@JbO9oOql#z* zN7M&LL&4GDkUo$JsxJL5luZpZv1@3s#3R1#4Oa-d2%gbv;s_dU6Qr&oGlp1010DFe zm|_ig=BFlX#x*uS!vsIIpcVX3Hz9uNAp-dEqY?a2AN-64Ke-`2JEUiY^h{={zVvP& zn{+g>Ead`~wT#9pEH#8@G%tixl{}YTL039sZI%pkpjbxPHZ?|;+^EHmJDIkgmsBGP zJl2`A#;_TAHf3W3Wlf+JlutepU-@aldj`sGXYI3UyCFpvBH)qd`*OBbZH!4%WS^X6=uc| zD{O&6*L(-M@+s~zXSxbtGnU$P-6`n00a`&9b>*ulo2h331}sv&V(q{Mx;(;Z3&1_ z8J9{x%4-vXqVi=3CMu_HLY1#a1Qg7#uAx3EPeE}mXl6D?;JFQ%iu zUA$2jRa)OsqOy819bsAh+?mt=$NRc<0cxWKinH}0WfNB!a8%6Yn zjA$1jN>`_&iH%5|jz$uYn2v@LkTM<3MdgoJl~XsN%J(Az3N}Q+5U7vJ+oAHSBKj2( zy>&!y$;CehYqY959aq`K8&{x8YdTuX>cw=ll-2+5>1Z!NJ&z<}jZrrtP;Vguu)Hj= zK%hQAbpxm_5xrAH@4$%Oh6!kuqoa$BNS%&O5|EgV4ibphhwO~@gt%O9Mnw+$DfFR z@=u8JAy6MUGJ)f|h<M z@SzbWL+S%dF0f=r^ehH)F7&ZLvTY#hoMfFHj!^=~d5A7>P&XkQH4y}7>J~pC{VJP%co7f|KybZ+|tIWxmv%``vuv~)h0tVu=r z;Am4s-@pVFNxx#*l%R>IB z2xp7U&;5d*smLz)p>9I_m@l~D7vWGJ{5%SNc184uBl?3(k@6B8EG2rwO)N#b0LfZI zk1G_-CyI7QVt3=mZHf$Ypjbl>OP&Qs4?1vk2L*fFnIn4bjj`M2=rO_3LTCj?)J=$^ z)rbJZccKw%i2C5@S#Y!`qCdq1nJ>*z-iZ@S&>o3RtfBo1LG;?3=)O3D_S*!hYsict z_<72KpL;0QerJB@wK&E;o1eXcA9^8<;D@>i@v|Kfz|ST$f*FTvL5 z5&csp?11z$-;_h|!igp9b7g%URtS3sp3$%3_VB|tVTL(Stglbcc744|(GNQ__8x4; zS2kmZ1Y_?*D;T40LW~_k1Tgjq8o?O#!PpTn_8rspm2^5Ro3GKt()FFPzJ5^X`UalS zV{vr-VAG|pFEhq}Utix+@E@Gn`VKbZn9bHv!PfWC3bv@55L>?^0@(TqjbMxVVC#3V z^=m{w!G!%G{Z7i}6q;DVepS}jDTS~<;Tb&{x4)mV2{X)rVtt)B+x7JqML*@t*lE~| zlQv_22*&<~Rxn20gcv&qfA|i@H1TKm5U3Bv{sm)yGhOASQw7pm*s2VzV2ip5u~iol zKvF6ivA(DewrWLjQ$4EJi0aj&dbOx^Q@tLn(W+7Prn-&Ys1cRtNO4mgGT&5(Y~57% zd@}2jDAkgVBmxw569Ux=5fF&qB}ILJ3IJ4URIeS?FJ(ln2~jN*k-VvHBT{Fxwgg0| zj7udT<+fo^RNls_oVp2B-c45CRul{f)JNs%sJwnuuN&2)Q9aDXcZW50I_lfS8+B17 zU9!-0L}m5zrn;FjrxGr4A7cH^+r*> zA>+ChCSX?X>zdhHY{A1MlkKz&qx6)L|X zs<)2nExB@flT_?-y27s9XpIsvBVsRYX_sF1TCnU3qT32A;}Kq9p>9H0CL;nM6bJ|q zs1GcifTcrJZ^uBUKpzXFgAGKTf_7(zqqD#<710F_>L!F^HX@+>n??B$s1F>yfaB_@ z-aV>!WhirCid{`t+fa<|%A9mPJ1o5gmfH|sV4-e8Se79IAS@6NAW$Dz1^`RHsNRQx zEQdZ8NIx5hIwyV34#z-&V+EoM9Mnw+$0kHT`D;Y^5U39v*8;~iQGIAsAIwnhldhX( zb3dBc^Y1lsR>Xb75z6^@3p}IOMPpay2%81N94HR4p*9W1V94?J4YyLT5zgmZdfAq7 zoqfK|5FBlXR&Ye!ggDxb2%v^v!9{&=GzuK$MD>wO(BsnY3E9xAxMB&)k=Vrd^*n_j zdbw6~OdLUZHbLq#F=L3`bEE@5Pf@HqXMUcB%@||zGg|Po2U@`obra&}6+{3(`_PE9 z1ogpBG59Hr>IG4KB2)CLbbU=WucL{js1T5>uk4c*ir#={bW$|-NSbU@WS9fR8Y+-H z3yvl_a76F#icWUs=m2cSB%7lW!O>gL3XZ6o5J#UO0ysK|MsP%ZaC9p;x;d&(V}j_F zT=4rsHeaHNCFo{}O{}3A3PFe98J!+S&N+ zh&#p>+WZ*iK(T;slOz*C-sgGip3ff?eW5dBCt))d*o@sF7&`^6V2rv6F_u(LF!nbB z3C5@o#+HGxJDILz>69Xya%f`dx>H$BD;2uVfoF6@99=7Iy42-l#`y1Sm8akcyu z81=!}Rxoxy(^XeG)sszqG_iEuudJ^f3SAB08QmU7*AAO5b$yvJ{`>l(m%K%HIJ2e0 zW^A|F+9ud)2(4g?x(TtBj|gBZ7mZ+x`e5q>*!nrD{}|PeMfD?5{X1rkUQreOH5%Px zer4)L4~PA1GhqB^t~B~8c+8}c9(OwurAKb*4?K+TpnjRYEgpAznXK}yu!;48=wf6w zevQVzAX;iVb+ld({fl6w1kQpL>L$d>Ohf=HH=+@&P#>)P4Oae&>ZhXmA5r}`ri9)| z1;*r8$ezTNHPDu=N|!NHUbME)J+J;J%|7x%SHVV zs1G3J)4J;A()8ps-Iu1HVIb>Zjh>qpJGbT1;_o<#Z~4h-1Os!3sr9At)SmgDQyc#d zzKuv~oSPOuwNhhGZG|)fvI)+D5$Yzy$Sy=cpsi@c)KVXeR0ku~()9Dw^vY>^#Wd?C z)FZIQPHi=t4&!`qV137~EcqZ(XaSq=rL71pR=P5?7YZDYBCfze-Gp%LLj>TEFPeft zec-qZI4()kYo_TJF^K&z#e%rR2BEIcnvNJQDubc6!0?=ffw~D{ct>J*S(FY8)CY$8 zz)&|$kEZG2G(DK6`x(i*aEPX-MPF4npSm^}BZ^w-GKw~zutXzPXwY7vehJ5A^ND?v z^#{mjq?cKnQe&^p27-?d;VkBqx(V^|JtBYxdf$~;o74v%&A~_0G`(?}etDX%GZ{x< z1y{21>VR*WSD4$;nO(Qnm>ZEwRd+M-r#Vy~2V#Kg9-C$^P@^PeWR0`eK1 z%S^1)*c01H@Nq7j1s~K+h>wdA0en&rZ{`()3KGM!bY6!<^~< z#LH-#7j>p{B`sp6vz3|7QshiYj56zE1+MlMF6t(Pi{3y4IP@|mv3%tliK3H$t2j+B zOw$X}^oeQuc*b=tJh3R`3KqDEopBW^xC#_36BT)U8C;VEt_%wobrZr>Byo+ia8V!g zbt`b)oTmRD*3JVwj_T_ByRr=igE2M61dt`IBm?VM+9KN!*gD&H23O)3gsfuAs97sn zHiTfB0n<#c#u!r#A(Q|SCG-vYx<$^|2nq1PrT8%OO?-zl zE`&4Auk)Tup12av;UboA=Sw&6d^>kUzFlORdKCniri!myWa_Pu08_6sEyO>>cbIw= zOx;-L-B9OUU*}y{=e>k%{sVy8Yc{KO8>QL98(8kGm$^5*uGoHvm(5G?*#2d+e7yHZ z=o`LfMAj9b$gI2C^v5t@(;wpN7WqS576do^2_I(GiSO{oP4LH!b>185yqoI0*OD_H zLnwU3h6OiDPw))9L1y6aCf1N%Tl56$AZ|7j@;C&W2@zknC?VonAtdC_rv3Pb_>P1O zBO!Oxd2g%p-b$(Xdl7xH`0)>Xl+V1}0V72_DlT)qyAC7y($BHK46^pFI=rYA9WYb&=ngFY;B9~D17#z(n>9w?^GoJoI_Ip|Z6wU2D(phu;H zcnK-VFozTODg5)fkoBnAKVKkh_z~%!hfV){iKnK2#MdqI&o-rt1n^<{M|_8WUW0#L zsq?;6=Y6rx`vQ4s+af)#_^};6%DwaoQe_pRH<_2V2U+_@UHN;{o6<|erHE!Rda3AY z(@ih3iu8iQW#fh5H`OlN0b#>$NSD2Cx@-cTnl2Mxx5#CCLjsD_&+uWoOnisSK7h;K ztMk5F=Y5C#RarzQ7eA`-QSPtzib*v~)yK?V)gWs>+RR@cOMmfFRgz)4>s{uqcNFfb z5pq9PyUT;H;g6)dJ~Z7`i>Ic$#Mdoy*DoOf?(*ZqbeH%JcYOzU{in|RO`Z3vI`0?c zu>*_rLB)>{KFU4zAEe4EVLvjDg+bQ-P*?r}_oMXKa4Di$!oDfG-E`Sk%w=CFTow_6 ze^k3Him>4yq|3fHT^7Sr(`Dl87P;(TNPx>y_%K~2zQbi>>oxCI_1@9--imr_s%%yf zon8ExgO755ZB;K)iH80D%Gz=DvSFVKvUc10a(|7h7fmyuPq*VGtR%y9*XVk4($SpB zsDNy1n$2qC=Lxyv>XmK$e1r{eTTgBLHuWNvhv2E{F7b7X+|>aI5OgR$Om~UzaMwh* zYqxsuF7@7>>b(=lW8zvc&`XLRo%ksC*ltLbRl@dQ9yzfJ{NTUU=+@8Zy5ffzc}Gk=vLnm(G$ ze6+X1N2dv4^=coTj7!cHM`z%v=_B!Vi+pqmBp~7E;KTHh_zoX6!bj8Uy;JMG z`;m_>Eu!m+AD7{y+(*-xj{?j`>p|A~>#@Yad=y|lDn&GXG?n>iKZTDj7s3K+A8kO` zuwVMfXZq+0JT-kJzHX6^h9Lnyx(OeqkHmNQNQaMd_1;XqH&yRVkelu-(svaSc<)HeHrtE=wp}_9r2DmfB_aB5e3z=`zD~ z*?o9wx=eiCB9}c432<5QLNxqCe22>x!etBUy@%9$=aIkuTtuHKe*6U=<^EbwOsZM+ znwh_z1zCI8X8vlH{^E^$NrvgJLzuhfDcto}A-7rWuICUoe3*3Cp{Be3hNq^x#Mdoy z*ISSPFNxdI%n~NP!(BaaS697vX}xzzy|<&@+eS`%yBOh};>W-6QSP)ZB+M#g%b3&N z1zFoyUp|4hOge426wxeXON*X2y|#pTt%Lo$P2s_R3nk0c9()gB!+p|&y`~4>$5YdT z;_DW9@LNcL2S34w=|S-w9y}TzJgVNivfevX?;Rxf{ijI(xA^fLKFZy9R59gdnOnu& z_dUqkV>WZ&D(OC6=1MY5@2zAW8)E++RCw9X${N!tblI5rx zKFUkdT2_+IV;-pkS$png9yw2XgqNg}j53GRi}>fM9U^W;8$MS$;x;t1l!&ie z$c_a<8_PTn^xE6;_hl=6lCgzb+#ImB15s@~jy^uxN z@O9D)*P31sx1E_@5MQ^*3ripYDQm`u=>_o}UU(2*xWC?eZ@u@PdhcE2j!uNu-dSHv z)8Qgb_p>zJTPhx6q5YncW5jZYx%ELzyWS-qDlS1ar(KKpygp>6PTV$TrcQj_qSUQ` z1f)*f2xg{Ed`Ie@Lh7EV_dZtdeT0&>5@QD0(X*uI* z)AA!B%(Ps5-6G3Rf&^IpThn0tLwtwje~0DI*L$C<_dZ+ieTIxb8KLF*^1L*D_&Hc9 z8h4Q|&&n*2`SOf>sK^(#_o|pXFPdpQ6*|o{imzLg#!DdqNjuj}8vY@^BaLq$jjz>v zU#a)LLlXRwQAmJm?!$*!_r!Pj=u7zM z^Lp>6DFb6#evi9rE9Q2KJ5HA%a8D^dRRN+-eoroXxrn|} z{CE`~2j@*DdnV$B+O)@8ZMsk@yZDZ4V!fo8sMOiZ##pNs;@s z`0*J&${jQg4zlJMCol(n0kU?7DQI$vElY=J_a`t1l_Hu2XPcrB@o#d_Q_m`-uw!*q)H4yXJaPMI{tJ8_D4w<+FT$Tiy*>2bx6 z?eJ0Vnn|qe?9E&=9%SuaQ_6dly_svQh@w}SSn{vf__^B@+W5JPe5~kKip#7hGZ|#@ zPD0(@YDeyju;IO=Blk2NxeK0}jucq;pV6WRMQFM2@M?z@>6_mf^MHBx5RY{?K#^hhUG|KB@tiqN*7+KKxh zY=dDc%P1BgmiYQ8BKzeN0Cmq=!A1g{D8|7H51ree20JS@# z2pisCx^t%K&KRDW?i63Q$ejixz@15anC=wc;Z6f9uL$37sjmD;FSaI4ND3FkSg;JT+Y@ zzWxucTy>KR|BYX`)2MmdxpvSiemPNh@1VQK3lHu9?_D}y^Ikl^)LBdzzIguX@OP8< zL(5}&EHrNVW%EsM?^t{BeBr~zgUQ$%mT%Z-6!j6e=7pliNGor zIIS4-c#2ug0;d-PPo_W*3!I3+$Lnf4Mc{=(Y@NtC7c%IIYS+vSB7^G93=;p`f(+VM zckd%IXkTQ|MaZCQ=6kQ2@7-u+(|*HOp%gt+N2O@g-qSY~OObbYBRPI_-Rk3SsYU_B z_yPrI)tKFoQP<2zR?Za<#5lq%Xj4(p5M6gqRD@-FTU)xIh=R7k(8=xI4?$XQe|HOyHNgzp z2SKw3`rBK&S*#rqw0#AP+@Ca0chDTP7w>lzuaWqugZMDQY!Y^mz2;v!YR;49jDzNs zz4(Nq_+OFuc@E;|Aj~FVv+Ok+j+$FY^I;B}7ut(o;3$46iC^p>z8zsU32U{}Y?ik^ z65s70{s>1ID@n$32N?qhvoW#XQT#C^{x=Tdk93rAGRZj6LB{b2voY~lNAYKn_){Ik zpW-Ov0+MmAy%}fQiEz8uBFLs)aaUZ3z*+5u!L9+Av4boAMkYOLulE@z zz0a%lzTm9)4buB6KpR)Qj3A{ewy$tkys6gvPiMXFk=}nf34dQL`~zpU(mTOP z_%3SUyE+S>O2YRo2g}BUQxIm8;5q~;6YO?-5M)zJ(F_Mkv(G_ugT44)IEoLG_yZlp zAAm5Mgw3?qJl#=qiZp8unq&6jBaY%{k$Bxfd=6nY3Cq}NHiu4!kodU{;%7U`XdxMg zImlRuFdGvWIEr6P;@cd=FLIR8M>4wY%{anNgxlSTAe*x7u2_aZMLqAwV}~B-C^Bh< zz24fHpaD0)lL+`Edxcb;TM4DqL|Y9y_?=Tr%k_d%b5m={--a z_k3r)my_Og0Bu}x34)Za5S{S`wcab7^ zT2`nn-WGvQDH==RiWKdJK)V!GQHu5k#cFg}HtdNo8?*O7kgeIfBhbn0pHcV-v*GOn z$hMi_>};Ekuo1S6GV?h|;y3eZwcG8dFs6DLCeX}IG)1a42h}lz*_6%*f<{apWaHNpNVD3q<0yQDW$ubI5NKCRE+nJR z17%kj&Ow-sWoMCQwPj~g_z25TORggIS2(D@9AP#-y9_}#mR(Ak)s|gM;Ug?_S6q!i zJD=S|M*j|!ozJdEn2lxEk!H1J*HHKf%iyzNQh&RH`adAd#%H%6NNJhq@b5&RUBd4t z&3|&xe7C)LSpNjcc+^40!w9pn{y}^3?usW7XlMOjN%J!fnxD2859?nh883pfvG4^u z5pMV25L6rjjL2Dc#VZKh+<46YzKX}JkZnHy`#zcUE*^?u{5cT|-%%63)R>iv=Qsw?OB6t3{cXvkIg zV+m4_q9#^l2g@?fe1+I{ElK3TNrDUPLz_P?4T1@Yo?ezo+!v0MN$hO$f3z`dS1!8GSW{D~!Gg zfeNE<#$yMg?;@lB2+$@IZby(ZJz|J?w_5K#&Uzmrz4to_e^@R25oh6lA>mI0v`N&H zPI{kJ>;0><-hYtZ7o3E@q!#|Nv+%D;_!s41*=*Kl2(wA>CkRsJqTBruf{F!?6)aK9 z%n75PNb~m&n*Xa3Uu;;uRf!itruc2Et#RDe)n#S1EMa31W|Oc{2(n3-8$tF7+nF>^ zaL_#7Ui@~B;wwq~o(|&oK$uO!cDL93Gt#_STV0xH+m*sqIl3QNHU%7O9?D!^hcFw< zJP5LJc{OQPTQ-@(RhIe5vIdp*G3MOoFYL8@?WMab0ti$zkwH9WKG^(~>>x7f0DHYN zo%Dv(dc)3obEG#7&?Y022(rlt4M8?#-(8VMpu!b89y_?=5He}5z24bQdVi(XyTDoR z64Kia(8d+52(ocS3xb?F)@BMHQ6}9Lod{I8YAGH&xN4A0?gwaNS0CwB*OeX$SJ<^2 zfeO2Z@Yunw6UnaQ0NS{66@qL`{w;!>T=^RcSD3sSfeMpP!ea-M&nA=41ZZQ|>7-Zf z%2O#^Vb?hbRM>Sc9y{1I$zyd~Kl7Axy*B0_-#Y94iS&N&Bpg3> ztt$3zJa#DdlWJ*9SPqtt2@z(K;GGeqEShfjjtH`;rD9A-n)i0lyr;eRJsib*N&G$z z;_DG+ldxKQ%{7ji1EjgpLGv_w@lzeeA4uZ&cMv}VVKxbCveRr1onj>&OiM;SSi zk#>-gM3{|N9?mjSd%)TK^(uTbmV z=&W}W>Al8D`1NYxH#iIboP>W;4wm&>A0f;p!5<(u`3Exkzo1z8FEjdEgxOg3HEC8)8huIOBP>IYJGRd1>&MjDs~?3h8})7k zIXUJhd-d*$Z4lYcF}sjuJ33gl1Hx=_b9)5Y7(EU_MWanE zQBogrP=6r8Y{bNXn%#mxC$pO=e1zHX_7K@N0M5>~euUZB)`uWl+j>a1x+HW_xXQLwWZTi;>})#< zVKyaUC4!V@i{Z_&2(-(wlS%W54w{d*7Z1;#MKaECkZ~HqY^+~nFWy~oHUjOezlb!S z@1Xfyd-1UTYLcwWpp7fPL6D8fUm?iJm0wV}!sH(is4)3Q zJa#a7n|f<>zE!=gU851?WLE`+E9}}9feO3E;jx2VyOUkJ0km=DE(o%5k*K!wSB;IV_rwPbQNKpVRzlU{YH+?&D`cGV$JVOKpKJJ{tTyQTrOv1=;nRok^6 zg)8jxBT!*i0FNE)GRUqRK$|SiAjrn#6oQhGlMhCq!sJ|pYtWby)lHg+9C zdeyF+N8t*)4nv^Au4X)Tu&bBs>H=uv%B2XhF?k7sY)6J22z2su8-**<(}zGsdY0j_ zLwbHo={X9ZjnOL+WNY*g0-cN=q;Q4N#~@H)^eQ}dFnSFceG)*MOgIri%JhhF?x||M zr#b6AhxD#>5`L~)_<7F4*OTx|0oo+$Vkf(c2hES!i+{vX{EH<1c?a>&AT|r1>=m&9B&tf5}n&`y~Eda5l!jV=w(Jd+F|q4-lxR?jPc@Lv{a(O#0kj z@25_BzgFx0##!&EDb|S1HO1ByKiZr0y^~3!AyVOrF?j6Yit%L9IDj@4V;cn7R19~; z4r;vbM4-a16dpU+wQjzspra}-o4*%6w|BeU7teQf_qMf*8!ktgH(ajz z&g>AjABCxi4JIzI_48eWZOn||j-uCaS6qSU{hcB}%o*U8-`f#@nAepQZ6Zb2%y%ts z=^8Ze7cTZ?IFxqPeAmFrKCb;4+(zwoZ=CO1($dq`#V-jis)SwJxwbWJb-Bj%?7C}H zXL{y*UpRX1)6bpOQTgkz8@GAKXD)ni!|=P8+_{i=;M zA5^_n^I_FfH6K;|t>)vZb3LC_{Z#X5)d`-@s=lrMyy_n{UsT;u^JUcyHQ!X7QN6nQ zo|?0&U#r^dByX-=T*-?J+FEG?O8Pr?i{t_&Xtp^ z`vwM&-)`e}pKkZrcB?9ntvnv-Ke6(p%9ATkfgjdZo&}GbS9yNrg_W07uCKhjazo`6 zl^ZLss=T`L+RE!IZ>YSn^5)7vRNhv3N9CQB_f+0nd0*xIl@C@vQu%1*W0g--K3Vy6 z<)176Qu$ov-zs0I{72<0m9JO6QTflxw<_PM{H*e&$^V@E>Ev%Ge>eH3$v42?x5C%A z!}HI;*U!V_Z@~Niu6nQP{i+YDKCJqv>f@?Usy?mytm^ZsFRH#oE__qMN=@R$oUXN&t$wfi{pt^^Kd%0)`rGOgYE~mJ&Z;@5=7O4w zYA&f+SF;{Dv$5t{^JdLkHSg4*l+=7s^HI&GHDA_zRr3vU_q&?!YksOZ)^mbqwdZ8y-x|+po-;ga zk%Q+VFE8|5?70*K?CqqVCDM zXX>7(;{Z8C(ch@A>ZmWE|x?DSiT6??urgpYHFgV)%(@!WTu24sN%fQrW)7Fl1 zuPQxR-rF^`yUkUBT3LKDwXMIsbzpfr9-zHIEcb84Kg<4`+S=Jw)3MlmCSs0qpDfU_ z|4e3am-%cI{*H2gGo=i`7nAAiF&~dMnGs@&O#2Fx8Dlb@+s!ZRk140H(tLtTn4s(a zLs+o+Pm@6#A^zJM|HEcsR@r~ThF{E>Hm#EV*U&U=M&tBp4bvLgL;SO0+O%LWSXtRP zBiPvB6JdvMD}3m7wXNS3|7IyAuH<{c?ceEk z-S~C6K;laN7u-<~x?JxymkT7Wlm~)4aiPoARxLa#|0AxH4@9*vJ zZ}02vADG$KkK7+{?WpZJX_4Q3PaATi5oKlPJy$(2=vt0aE&iK0Z+o<46Zdh6zpKVz zfP>F{&Ao z=9UQ_G9{ZL?=_nCj~=@14;6t|4;=H*6+=52|2vUV()}C0d+5NUaQ&6l#zp(@bKSg+-z?i{O3fAtMT+}HB@kZR>w>li zkNxuC6Mi@#vFUeLkNeL~Xa4UDWun%v7=L=>Ox^d#M<&jG@bSdYD_l!kJO>@r91S&3 zYm8*lMlz94hx%GWuH&|HjdqW!^te`CAWni+xQ-yuAB$Tqe6AR1he^ESdZp1p%$M4EJ!ew3y1UJbTl-e zvT;CyX)Th~Bl%cpKxN~g1haZ9k&Q;ep#hbR%O#jeM)Rqd76}cgY#frHo=W5*S~?LL z@GBCtLV`vlnT*Es$` zpVl(zOlV-b!r>=KP|N3{iEKU_8knH~Pn2Lfo6N-Gc_Va$DrZ(pFcnQi!dhAn9ihsZ zlO&jkM$)NhRu3)iQ>Z>!g2{9&kxED4M-_OA1QW4*R!^nUp$-+eMuO376g4}hh5B0* zs!t_wdM1&HWTGhHZH2y8^oMOFd>he7-dk)WPm_2$9*@RTG2O&l`ukTZ@Y4wort|5T zD4qgu@8~SSTMOCu6=k16a5j|9WU{$v%A|V-2Rgc17MEg-6EW^8#yFE=pzX+Nk%*zA z{eps0l!jn)gO$}2M7(>7@zzqjd?=pF7zy3TvS^J~u5T~m++B=w7K@{4*|=t8xvEC1 z0Pr|xvp7jToet-cX|AWSlqMeM92O^$Ohsd8ym=g}!tyxhQk-C1%cSy=L`+2K>n$kU zd>+9wvbm%l4rk1?7h1)Y$R&PTk?=c<2|u5BUoK@Nj9AzRwX|9;8ZF3+i{u58%tv%o zwzv+`attRgl%$c#h0~E#9;D?CPF^HQ9VI>!&gDQ_PT=Ill1xMmBbH6YL#;|XFOg(2 ztH;BcoCZ>5=cSU=!nw4T4ktjW>|7_wcsd_Vq~b}CDmyQeWFj3i^i&w2)w=Qot(RcL zNTqT{E&|eOUO9QWBxCW6md=HvAg%V5lN%%%Mf;J-$73L^29}do5ZRcHWulp6Di`Xo za-9#cHcBv+$)?kZTt3ucIg^7|N-z^i$8%a(4|Q0+-YCgb)X-u&lHFkC4F`WO!AK+)PejprbTn9*!^xW@sp(10h$m2h8m!#m zdSEos!gYF*F?*C3G~Zvgj^J#$GeZb>He zFxYGoq$-QaHwOEL=W`8b;P4xg$PJwT*C9n-UEvu4UZh`((Lqk?p@uu-f38s@;9yKo$8nSYV zgHK5igP?FY7f*+Vtjff}rzM!t64_WD(*i?QUE<)MC8(pj#PHP!4Ovx*gU?9NK);dB zr1a2`Rg*aQ7YXK5=nm5Hd}zq3NF01tg1JaIiEb+w8nWsU2mdO;IA$dDcrF$ivZ@gW zpOYYb7|&~|XlTf)MI8Jafxdh+n+r!UEik0)i=LNcE}Kcl!k8BrQuakJNKy}{GKm-l z_e09g=m6#mvBvvNL*7lG#LFWOo9jl|8(f{f8toMlNe;m>U>Uc1ABrG8NYo znFL;)hLoMr%aTmzjXa8`2GYtQuKg8BMluO4mBkCwkg_v+Rg$r!p3UI3c1YP5y(YnY z*vMp&C=_+8_HgB|OEQ<%BPm_f9%Wzjh9og%l*{MM>SNU(F7r)E8rghO&x!h@?2P^? z$tF0ELLch0$`J=Yl3+R-iN@1- zW9(D4!XHa8i&vpY1}}GgRw?2VKOxYc$>*{WOs0mq`?@UUys!9FqS<&p9Mv&W0cxq| z=w}j58%92v$4~{RWdKLFTVzc*2jhu6P`m>#DlBU*C|7(pEaETj6Nqn$U@#Cy zO)2qK3c2(hC9NeeyMf7_B25!|oZd;&`D{EJHxd@zSMms_cP2WJ$tRI3*{G1cY)OgT zN~H4sVk&nbwkev)rE_8~!(^NL6_R%)+OJ`rGLjF6O}d2gEZmLIpb<|RS`k#{;LivR zz}R>`k4akCP_R}QxV;mJ4d$caGzJrxlLy;u&9?C=uH7Y^$rvbaXthmPRgNY}*vMs) zm}tZ#iI6;4N*$NHhlJzdd?c$SOn8v`BM$$Z;6Nsm%qLR`vm_0w@?%e8oAQR)E}Qu= zxI~#BdlBuA#kG7Mt)8&ivY6+`-h>8I2HxaSVbjTj${eXAIFOA*!$vZh5OSAW4I0mp z$;A322C@SKJd;(Fi7G+^@k}_M)X+CV?2sy>s~M{&v~V~Q5iI31H=%}De?A(`q%;jH zI;g4&6Fh_l;^Al>0|_%_otDeE*jmYAJ{eP7cujBV>RjAYlFQjTVuKh6r^SpI*uhR} zT6lq|C)gL!jkGy}#3rzkSl(n!Au^DSp|jA$T2)UQ6*F$aKEwu%Y)VUFs36!*g1HI% z670`ngp|-?D8PUfF58dLpbJ%;kC|90_N`*%<15VQ`VMluebamekN4 zWg%F=R%UR)zaZF$@dBoiu~gAAXxYnsHjT)D9?qn~S_UPDyS3GAUjZ1Z&CVY=Bsw9>XGD zB%2N`qAccq2of1cq)>~o7P|2Cj3P|b$_Z|4m{@;0mx`k;3k!BYAvQv2Ad49tJraR)fvUtti4Ed) zFpS!xfo*7Cc4SE~&$SrAeqGB(W64Zhz^bIh2@RkuB#a1pOo6Iw(1;CUg{<^m&@)G@M6piHdaN01m)dk z&qlR0_J|bWQoZAzSW0YA$Bv~GwnCXK)qF1a2!aE6kItl$@Gy+9YCf0SMQAXS)pGfa z$qw|lFIRMi-2^vfuu&tDO`yPGU*u4W>LtC0Xn!n>p=S6ZR)yBN5)Z z1**=xKB5EhTng)Em?IXnD)W{}7SlXh2Jet2tIE87V*S~KkxXN<0PKJzme)5ckr)~a6IE9KLt9IIu zq!YPZ7Lz?FKqhUuf>-DjlE#W~1U;QmqE*#@CDDOQ9Bbw&EFcTnmgjhZJ5sVyRFHH$ zQ%s^|1!s?vtcD#&hMqw!?e00!s!W{y4YB@I+{h%wqMBe8z1`6gHS|~}ri;qoO;UM2 z|CUf+K7+Z@1g52cDmunvBpK1PWFjFdb5Fa1Tt%cmg3YFROdJ8Ue8sgNOJpFQ5(}yt zT9cmk#j5llN31^q_2?C0DOg4NkC!NNDw@KZzd)@V;1--fXfTVn%&dmhWT5Jf`9y;8 za)EIwhCL>%E|9B<4#X1iyq?9XvJh=Kf@khY#EKahyzz=0>sfB0+~Si7^v?zr ztfEAmNoYXBB3?2dN8?avA5ayvwZ!@}3DijJOfp%8*s}<2Ok=YZHj<&BS(S&sK%Pw? z-nnC9{RPdbd=ugMdk&!uIyNon@hH%e?g}yO`-`2;$?bEA^QW;5F&4+xW>LHpW}ZiA zAcdEvXfz6RK&t0XJzuieT9Ux48`KX-xtzT~vXL03?ZO!MwYIb_u^I)=UPvseuaVB9 z+YYt1cd9b$B8g_QS*$%`V_5q#E33G#E+*2KLIH@SlQ2LztiOavKjtj;JjPm~)(+aj z#)V!=Xb|&-2HpW6w4=4VpqigvM=*xIG0ZvZ=};?%B8ptNjL={rrek!0Eqnr{8pcOB z>j}n$Iwo2*48L2uS_+n6?%K^u=WAiMh()BGMc_j-Z@c`Xu7g!3p6fK?{kK&&6T ziLfjjhkLvGER+}a-x2CdV}4Id1-biE+bBn1|60gv$z2Zbn3Fg-RUcyEe z?F}}p7GcW<4&OwuKV_i7!&FVEbwF7+ZzeQ|4RR4IsUl?qHg)qBf_+#;Pv*lBxNNyK zL&4K_E0GOG*hu8Do)@zEUf$;ZfjECoM~T5CiSU-HX}V3K@M$K61?5m1=57@Y!|jA( zppY@ry4YXL7C(6Dx`WstwyI??)Xo=Km1F-%a3CMX3u6rX#e`ss<${NaMQ0k;!!cw+ zTMMm!^D=WMp}}Mni|To-f4AAq3g1PrAEzSl5{QPk4d?0VVIwRy3IL@A0&c=R zgiep*AVV0FoT0YzH#I(9`4i#(yn*-ecm|vBWrM>d-z!la)2z{`*t9O|FGuf_C>Hus z>7FzV;>|MG3-rm?{BvXF3+_GiS?sjPhgil zOlV(Wq1=Rr2n}GkkjW;*E_tBcrJUemAC@fMVIomXE19gy+((FQG_vT~H3J35%3eMO zdXzxFhNYrR-oVy=byxWqp#hu>N@8(c$m}VoY<*m^*aL%|H5n9guqs=hAQt@&_T}k# zkCPe3TZAWx#5)X{8nG#pjy&XJY+& zPMiuu#p$9!2)E!FA_G{}3dgfpP-^S$psoDeg1<->J3Vl02a~aaRV}7GD_Kp$`6pok zP-~5bi~TF1{=6Q;EIxLywBfQ2MKynp&_FI4P2)5oG7PB72Y+L1J{iu(GidI*2b3v$ zUb0w3$m*Jo<^!xMWiLn;yX6yEoPRJ`Rnq=WtREdZCa|%b($-B&|2!jJBs74P|D>Kw zh>RFqqDtC7h{cFBf@LjKvF<_Dc=#nE13Fg5le&Qd2GpwMJRe>rHmIkP*zc4R*$dV( zfp@&G5G;mwdK~rFge{f}ewA1(Dq*cx>_%+s9q6NC&IP|FVQdb^oDgP@OxTjl;nxXn z(lXgpGMtEp+WOEkjm?70pzScsKD+ z!kgf{B=!uU(iibkIp)IOl5{#3i{!BwWzteMr{5+zh$D4a;6b+n(UeB+k#~soN8xA< z(=7tFQpii(za*LtXJXN8#FV>2QSaU*)EAG6!VyM^>$6^Jc;okPBK=xakEe22o^9*v zwMK<9zd-#eh19{+;a zrg$cTN{uBJlcl#(p0Y2A4yKSY^x`mANVdj2ycB;$us@ecW6lA4G}{V`tSwW#6n!nx zL>3FB*gpVtiK_SbMxq%kR^-B%RckABsoKqN2@NK(5na!SY6O&$#;yGi!2ulIisIB! z*o3W=@wV{4#QL$V3h$0+-3oMAlqc*vB7+*{g0Y~0q5xEB!uJFR(ot+b#X__Rt4#QT zSigBf3I|&St8&ASga$F070bo4$TXlz8-5}2D5$Vrn;@AX?rA&~jR&r}XQ4H{I zg?CI7ZL?rr62}tU6vd)v0#_lFU@H@NmE4Bt0Jb7y1p%||!U~J!p52z%>1n*%B*fY_ z*#70s{Z>1|yTfsWHyOATArZlfV+mI@*4s&1k7?NMhl#@?ZOP_lZ%;IKFzBe9Slcn_ zl4Nf7cw(Ed)ebZNQ4^I$bHO_h9K@1!1p7{kf@$+5cl87b8<;Obvx=eyhbVjH9SQbh z_Cv$gkD@yi#eFA<;z*N@c>>cHmLqt1+nLay9@W!mRx`o`^{n771p6X5@rZ+R*z2~) z63Ywcu0;CvXc7}Pn1$+4Pe1G?(PS=#WeU8%bhNgpHi-O;p?Wx;#-I@>O}O%OO(Ya6 zeTkGf>jIR`VDfy}onXI)ZXO$Ogb7{NJTjL%Nus$-RLda~Kw3j#PVON|%tzuJM-)di zTWQ6Lqd#Y83i}dpj09+})nRgUPeKC;>}JX6rU8TG172|Vl58AJ1Xd1(y9Oy;oZVZp zkyH|u&2+7LkY6cTy!D5%6&Ob#TL&p=T<&CI%}p{`3oNpVQd`AP4acYB;^3`(J?37h zCKT^*I5CO4LvWwkiZ*Ksms?OHSq8b*2*@{))CvJ<1lChhuuRR9i2ULzLz&5^^(qFF)SNL>r|wz4vW)Mh{jn9 z+*uIEShAx-xesU`i6+z7<^bsewJhc?-dCb}Bpi?8{8^}@Q#sJtkI;Z2UT4t}b#(PE zZdA0TUWP`}IOmJ$IIvXId1g$NEUp22hJnkgPifW;LsSgtBOXX4;cK7B(lH>+7 zNiq@9qnbFOE7!d_Ih{yY~qM8fdOj{^!oEmJvqkVJ760#5nC1qEtEIT?~94#r1t?i?i58BT_Y z4CojVWBE{|NxF*rH9{<^0k&Of7-}+;Lrcp5L7mgU{$Bl(FzU0I0yu@)n47XBYxKgAoGdQgi9mL&KcoD`H z;3a(0j8{rS!nk%Sm&rzOv{As8WDXxJ;WUPLaUErC2}%$d&EZ)R&Y`~R7@iklmE_q3 z2QU~)XQSBV(%H3~w&L;Jo9C1f<6@q$UlZF971xYlZZx#CR5kb#=0f6pILL+#|EbVY+I`0p zbtr*;oLR!g9nB+|sf-YIhQ*}78=uILS z9ZSA~wNUP?7K!Ezl-UI4$AGE^6^jTJ<0b4t#-!=ePPvPVThL0ZFNO6}46h8Z*5WXC zSR0XzS_p)PAehNo;Pfj9z$ z1->jQZPy}sq>>9gf>?h%qGOK&j;(@KJ~RY4l8+S_pr!J{^Pro^Ml51u?H1GQ zUDh-rx3q^qKTh*tsvrGyR~xMr@jU32C~9E_Q>0OWTBB=@_DM8hWH4C6l`}wniY{sy zp;(Hmcd;BDZvaP#>;Wz$F+s zi`Ug=l~yivkjOyNFmP`I_L+6HtsqzNJY7y~BQ7NpM}`xjE^ESn;dN|6~HAIDkd-QmTVsBj{n#Hs+P*r_8L84LYV8QuPIDbf4pH3tcCwy>!t5`zl z8nQBqCx11Ofe6l7rExqBWH%*?7wD5Do5bxNDZHczmZr`*dor5{}YdAucxIyI!KeP<9E!1NhFbgCe!2yp#p5{pAt;UwO_MP{u~b?a*hZ4^6q za$?(im(@)2!g>~geq3&v!QFPan?g=j@Dg}7p#dz2r1G&$&P1&#Pj2ct#5Sd4*n*J6 z&S4?8zu6k{^QoY7i4GXJCIAbZx=CBE<&w{nEN&djekZg?vIeR{_LEOliibpVg zC0H_okI65PFh)U1Oa&N#vD9p>^>X+^f&)5c=F%x_eKX-wVc=F=M64hC^dj*T?i9eZ zjU|@5_+moE;Y-Z&m||C`_ibJxVYHk&-fp8pZm06~HU`D;<|R;76S|R591l$5Dkm%kcXupNR?91i^=ISa z@=kHRONVj~;8haUu^O%=bmRgi5=*6q8+)}xaSsL77jVb}lX9w3a}A+EEI1_-m_ZY$ zy3|}NVO(mE&tW>g2wVBUi}`f~2e74G^tq@LY#Nd0?*pGtlF>6|(XdSO7GLTQ; zzFKi5oRF$2H8)5$6^_PZ;!--nTGnz4en+eiLvtL{L>DPHQ}NF1Mj~*nsy;-u@?1QCi99$NxDrL72 z>&M;lsAr-+^e(sFXt@cu5*oukG)u3~+w@EY| z#wAnYI$5BqX{6gFip?^(;YXC*UfMy-rQRXYEG9wnIQ1k@Yuh(R|0q%Hw2fn^h#Dy~ zjHAPZ2Cxe>j4cFcaDiIs;x4$8*e2Xwg+UGaf5ECds=J5|M6ep3NuwkHR%O}U5{+Uv z3uY|PDu7k>Q}+;yD}&Pca4c6eSlLhgiD2v>FvOVw)JeIwk2~UCiN?aZZs^#`&9?S& z^gfA3u)LDV<5Un(Roi$!p#kjA&SEDbio$@pZG3=Oe_Y2KlQ{kc)*6X$3mzmim`P!> z4TmfQ+SO^5TwW(1A{ZyXQnr!V*}mO6m9M!62+kuZ0o^{ zHBf6SB)9faiAEwg+Kfwm1gi4aV-k&F6I4Db`u_pC(Tq!dT%y=(hUu7?kV4QvhojQC)8!>sa_!N=;2<}I~g(#@GavvsF|1_aZMg)8R)5V3D zcDXf=5AgmhY0=)tb-a;b*`{4y!o=xkBpty#s*WoP1iehXb>S~W2eA!H$5{wrG-#_k z;pOI82}cav91<0M^04{zM#bFTdoKiNQTYir4KpHnc>S?U3nz&+2 z_%~wxdN_>P859Y*YRw(}Jdpuh|ATvOF|RC8Rh#nyvHnOBr!vK;AFPFPv458+-g^>Z zym|`MYMnUxBB2;MYPdWYhlzkvFqcv+&!bULkJi3}*63FYW3gyQrDZsx--nNSaVqv003D%k|i+(r#t@YEw3X+@5` zMyyZ61*CXe&V+hsF^kut*NMc9B-piu1Hyt-wRvw48o>H58ZpeP_w)`ZU#j0E)|bcj zZ*&p@RSd8GNnoRfdrPwD*F$6|fA@QfKtHwtU>O1f40+u?{I$N#tyBz(1 zP~=uDoYXK>kb8l-!#*UkDTjNkvCA1gz)wcCFSF_`ZyP@%I+(*LZLBOKWhPxJ3EaIO zOBffeU=K#*Nu%s=Y5Q7dV(rA*;&_+FwIpk}o+R&m)z36B0C(R4D2qYT)W z#r9ou^hZJixZ?=FeUUOu)atglu|G*Rheh%X1}Odb=@DyLgQKoCYfCOJ&cjh49G?yq zTI41t&blRw^Dns!HU^ulRi!vvL2P3r7d5b85Gq)G3vY-=5r;joXs|H&1W3IA_rPdE z8*vgE_n+ZCjP48NGRF{zW1O)F_6EYvRx9gKZRP7c8ZUSA%Vc_T#<>tSezdLqWZ+w5>#Oy&&dmaRLaa zYT!FgqWG;EtSg~l0re@0>vn|tqLEB8fqQI$s^-DBm!zTLeojoog6uEJTC7tx{$s2%4#0JIWN+N~XE0eVvEbi4k2o7L3 z4X(Gu6{3YDUCNgD=fpPQf-epG2Z|^Sw0Z5?lVHDrDR2$d(WDjiU@t<05e=I|6Iizw zHjrFy@ZJOm(wOnX?;8oYzr{)%_e3SJO<3eX=Y<;|OqTjvZt-NIag-{9liir96|}B_cWX&KF?*Vw%5nB#GD$DjvV*R*1M7;K* zCFoZc?)?c3;D{vl$>E43P^AkFAl4trU@Z(67MZNV1;3PNQpYXvc+nB4$^{1!8o*p< zTvV}8q0mF8MR_J1L~J8kxJ(>()rSgJapC=4h(OUG<2O?9a){Xs<^A_zVw*7B#E+e# z6bh8uP2L_y2u5AN&lq8)*rXLch!PsaTO{tj!EB=ttn5Kz1W(W7q8c3BLiP?WDh$fY z=lKjB*coizbR)fRqa8klJ zrHunnm>GoKawiUlQv?UZcpU>)luN+Yh=pf$n%E}n*iPc&57T6uTktbP`*D3XmPxTE zLr7L+OP0_emZfl!m*`G_Dt(b7IDoBoS{A3$1gyLTKToV58|Sej43`}VR$+rqD5mDH zq=_9wK-B|cgV;uNJxQ$cqhzRd+Z;@wAH!Dcw!!*uLA~2%mPCy_uBJ$dHd4LYX0}Ad z%|%h%rzKF;TgDuT<}h@|q7Vkd>fJVT3H4!DN;0Wo;-R42Z8ML^0Pgh+V@sOQuikAl zU$XcWBV25UpVI-W+--9Rv6z<1hH=jk%9nBr&95Yh4FkA$OpL2&0)e;D3y2gqJ7YV9 z82;F7Vfi(&xU(7~=NR@R7FPDC=6n|t8o<#3{Lr%Krhr;q8m~5o65E6!T^f}gE#%5V zYYPpScx!eT(KynNCMN-daj#pc#PXyy6Y0<6$LP}7@+nBm1U|4hoKTP*lW0)1FVH|TiYax z6dK?4KQGJvORDWN#+kKaLxh+hS_8D1Vi zEH>3+%dI$$4p!yaE<$~YFh-X+zYxMTfQq8kO{5L1FU_27WJtjE7y4=UsfOyB$N3b8ilZxx-a5>5HZsp48GC~7cv_~k68c?~k z#BJy&)*p{$5^>!58CovirFkwCB#Nz3Vp9QrF0G~0%3F>O5Q-Dqxj0tu@EdIX>gmrx zV*R+?5mR+Pl8vmlj2(G|q{vG)zl zEJ_SmRpzcF)Q6wS!|%Cc1A-g|as!Se(x1aM#290X18u5OcodOM7$RYtIC=!JOZ_1K z5^G9{w}-zWJP^}x@JAfPSju6ZyQ>NI=gs5rC<#jkyRA7uo@FOV6#JU7K!Ef6tV!nR z$%OjEc2y&fANQ4acX2PAB1!z5vysEkj^lKPRbn`~hDfxtsRSBNoCA?Ux%yKH&4zF~ z*~o^`(D(IsF7NDWU)*lJp7WmsKaFCb;XqG@^+R#(e}79)D~8bR;@yw7=kT8dKb_)D z$6fOH!4ceofg9NPk7Dy7>=}gPH@=eM4kK}4h2?CX+B1n1zd{hky$a&4h`xSn$ink* ztz^Y7a^gS_4tn)$ z&LKRA>7Bfo6*BRlztpbrrs`aRryH2}#t#Q$4+CTe{Yu&A5#EI3w>Zurh8gXhJ^gg? zF)#n;6CI4la2=`G>{l3QYo}oex8wqXvBr*{Xv0(;Mmu!VIWJWg5;`M+;}7^*LM+{P zw)Xc5%S(ym3sV;npA99`F>FN_8y~O^=cyqID%;pYP|qQV=AV z(|HNe`4D~t4r>D9Ol)sYOHZMrue)WydLiLI`F<(I$%c$fLi`4GUaUKpYvDGnqZmdA zzju!%cG8g(YX+=-^?aN z3kSSZ+=8XV^Ci5?Srq)(CQi6wt9vO5N|7qc28t5I#x>*i#?lW=~v-b5gx##6@G0D z*X9dc)f8MU*$ny=bk-$HN-pG0!8OEA&)|ArjDy6!O(e0I63MN;mhfySjjfxwz_D1v z1y9wM7oF=U#&nF`qL{}kD)6fnY$7}x!u@WTM8VCq!XUvb6iW3TFDJ%lE_`pp@Vl4XxUg-o^@!%) zMID29XBp`2AMw4lrLQp1+tcptZYd13_b+VeZ(Xu52gA)jIs7VFXV2oPt*!~~oBPgq zGun0UEtmeK?fGZI-ybyo?1`@CW^Aiz!6g1bTW4=G`n8^cj^^IJfzIBZg6rf_W5!mx zT&s3PMLbpfW0ed4jb61jahvbGdderm+;!vj_AQdPX{CUpVG$5wWQrf2wwLxoSnkF~T{YL8HGs zBG*}usON~NxheSbcSNldQMVFNx8K7(eu){?QrXJ9Bb1&iVvgGnf9~7a<*F%Dx~eRu zbdQL4o{0Ch7k|Fo#pT-7jOShgb!!j_X|(joSPh7EzKC`6RQx$(SC?xS5o@%26=K~` zriv#|D7!#J+o}P7{@mOYt&g@wi42^D+^0=E3;$AY%T!EauF;MU@&+^P`BiUPSBtHU4aaf+K6<9($uE z@@QP2hc^iwn(@+UJS**>?+$iGB9>AZk5l_~95pSo-X3Zbrmo)TUDdHV+9R582OJ4C` zL%cnCJZeXOg;-aKSUtz%&zb|NF6}hgJ-&Xj3vEnMQ(26wMU18s@MoKYTrN+sprDly zdi`B;1YuuyeKbj z?rG_6HwPgua2M@}BDN3y;kpxlURmIB?R>cDk0mYc@xLy`THHR+jJqFtnmgNE$89|Z z@sJusyjDbfT|}HD+LiZQON7GFdo6JL7E}Zmxc}3#?fAn>GR*iRR9`0~%(xGK)&p7CMh$5#gv#G4P|vZzJ**BJ#!u@F$MQ6NI&H_g!rjV_k1G zo9>;J%Fk(zxmMi{c(og&tHCj2U8Bq)V{o2N zs_(6+2f4<&^d>WORy@(%;6qxG#irOD5H@(IsZz_$&6Y{sdem6gHYJrgBN3b196z}E z;0QD766l@#YcqBvF=s)R1-%Qw`yOTnWs`#};2ua_RMLnIQ?r`qH_v9lU&05u!_9cJ zv$5tR3wj+cc%&FJm7SMu=9U}+sfU)-%|B#zb1ugseu6-42DwL@b1?Hx7-@LAq;PIz zUaCxG^HyVBM;FCn<9Mt&=4&h$y~F6SuH8#|W2xr(OzZW~diYGzIwu>MpJIA{jf8$# z%(N?%$azS$2+xRoNG?5wa~m`x)`{8jH-qI z#<>n0@ocQ?(^9(hc_?W?Khu6367{O|mp-c@$dtbbhpjE9D>2Jx#*W}{em3Ue!*h^X zKU#(E44AmTOhF_%Z4Q$WMCgyjtW1|XbS=F0wk)ifX{@mR9I>92cA>n^V=|wDU6)I{ zgyY4#;jBhx)n$-ypv;rmb0f3o&TgK|q|89JY%CS&+3`84vTO-J#f7D^GAlc)thVff zqOwUEK7R%?d@0m=s3tYfo{NgaEB76c`;v@1n z+}b}-d{b<1?(4-%VtaorZ;DEYZ88EM8yo$bzzvU%JP+ z=FUNB8|cPl$+Xs>e+86&YZbbrUC>z9Y}sgpvr$&`-a%@&mRTG>WX>#}#}#l?l`K^_ zOu({kPsDArnvOZ0ywUj@Y50AqyyHUJveF(#Y5%*F8Pn$&qD7+0_E(5Kyu86GuP&dX z$Q&aJUTRhxMV%_b7({=w)Traa`DTMRX$9DIPRa4J;?elQa}ka@c^174UEJO zUQkvcbI_1t;ZYxN{bLAyQhF4XW>zzA{~m!$ueMy1MENRD+;n*7-^HREn;lCbGyV@{ z?;R&a(fp6|u3It)lA}Zeib$U6QNiQ5;|`AFxWK_q+?fSLKr#X%VnTvskR%G2FksF( z=bUrS*~grJHM_GjJ?r!QKCkcnd9~eLxvQ(Hd%`Vg3DZ3>(%OM+XyLxnfmeMk7*<(5 z-mWgR%VXa0Bp!UYWQpZ9WwIIeWbh#pxU`Blmrx`f8Txr3>AI?zG*4~Nw4OGRbuvA9 zernnb*2jf8eLVEP{hQGY{a|rr+_+9++E+vbmc(|>5~gr}fJ05pEHw56a{~o0uSv$x zOE9+^1*5plC~v`?Ea?Uk)gxu1!9+hB6J(9du_t)uO9C~mt}QQ)aeF9x)%gLPypOR4 z#J~*_P3!IIU{9OnE||g`Yn^o)jp`jA%*S%~w?0Ys&oVOiW}&6*Mf2j3@x0vIq4fU+ zp2dT^OJtVIR@|9^r4gAWHC440MKKp$#FWko`73)5FvN@mHc*i?()SL}CNqIWp^tHV z!%Z>t;>d=I%9E11`MbuQ0r$!(%9vPrpC8N2du7t7$@9xb+Ww(&cUIpT)w?B-bFj(8 z0*g}Cksl)}tJpKhe(qZ)q<=8Hw7h&m+-p3*YH~qNniH848J&Ktw1ok8*i*#a>x)du z(yYH3S2azN=RrK>*AeGR%Vc9dhDYs=kmZMtiUvsR+0Muwka#D7_VdW55r|c+S|DX3OZqo7v71O;^pCMuYuAgMrC zU??yZSPEtzfc(DGH`4I8nhg1t%$(u3(0OnF>x;FiXK~1#=Y4RWMJ% zd<6>>EL3ocf<+1zD_El7R0T^FoTgxzg3}c&S8#@cGZmbr;A{owC|IH3Tm>r?tWvOA z!5RhUDOjsuor3iWHYnJrV3UH)3brWNs^EMD+Z1e9utUL41-lenpkTLx3l&_XV2^^m z3ic_uSivO&=ug3A@`S8#=bD-~R&;A#a26kMa=S_RiBxL&~x3T{+zlY*NS+@j!C z1-B`g1Z&mqu^cz_bIqv!2=2&RPd03hZQ`c;86vSF>_KhJw-E8G&4mf zr)XA+W~XRQisq(hUW(?YXhDh=rs$LuElSbi6fH^7sVQ2TqSI2eEJdfMXnBgxNYR-o zIx9tIr|6s%tw_`Gz> zr#BgXP;R#>8faGym0ZRib{UfcU^$0dv3>3r20j+~6K=1Q9m+~}3lk%U!e6SXs*Z&; z)x7YS$Zw1&8YG_{{H^!sU~4KG%h6i?sq9`Rd3AP!@sB9g#bp(I@|A)zAAx_eez1B( zoaT*;`LrykVq847_=8<*n;bhh6qlHB8IS52c-^7_>~|&DO}yBr5ihDMrCq5T!%mk7 zttifV>@d_>!ao=t4OXSGO&IiCmJNI!u8Qq1F7Lo|qAhk}-WhHNGw7_`4#MYJ`2^mU zsk}DeZq4}Etc5(Q9#F}NhWHWuYer{Z#Pm^>LkEv2lOy3h{DXTVQtAfD$DGp{czB?S zzDWHDMm{3l&Kj{LSh^x<%W>#o47yXAcOYwN7>J(A^KOe6%u&9avt?i5Tx)O zj{!sDx;cTti9i91;?{URE8tC1j1muTN?4|yvrv84SeB_e03=V6>Itdm<;m-+kvpPpJ2PYN;;3 zxUM=cPX3&cekB@O;pb+gvCs2ZH$rPkI-%g9^|G_-@Inn5n z0kY>R=79xSv_{XZO8HJJJP&Q)}>4(*A|j@amK3_UUDOlqp@ z3fV7)Lx1O~dqn=Lx?Da9bzx?`njOhIT0HAEjVawONpBE)=}_zwc~&!(IRmgqjOTW~ zWkN?qEDX*ava=Y$Q{NSkQ&wRY#!R|`sVU3?%WLBdev$R!jcDeIaW%2M?q!~KV8H)O ztY00Mz(Z`=y@HvG3vE{QSZd>Dp8bk|jhwKGvG`b?`lW~&HL@l*V_viiv^9Gkif#S- znVvb((4r#QSr6c`4+hRHlP-xx6}2p$J0+jNr$^ao+`@y4a`aa5*(R1!ewnGgIOjJj zs^v895T5t?NKxZlDq``i$dbb;tl|kVj5_e7lOt`aDUY3;9iI2*fP;K%wrWw?Om5eg zlyMZZv4zB{e`SI9GP7Qi6jDyfPT|3=0<8V>e5m4=FjA+4dyAhDjGeF>Gge89l2FPK_JRW>eG(A@;6L-A<$dOXt+fn}7|=5LmFuwmRQ5m7UiRXD`r4kqE#KrD56+sonx zi8r~RmWM^QP8OnIGYXGoP`F!OgkM3BvoBCfPViOP)m4Rd6{~JcKL@ia91|#5 zt*j&WvtliX7+q8}Sd!xqCjW!LR4S_{W;O*$zvi<7H4XGDTfX7CQOwqMGjfvx#rMOx zciE_<>P+N+OnxSQ_^z&w6rz4hJiFzNa3W&M$#K%b0Hr-BrBi`H@ch zXG&IRS#6KtwVP&V_cQo0UEj^bHk0TnF6T3kgjqu_VSP0zQ{wnOtjX{x6nO|-ugf@DvINn^bC%JDWSNQ z`IW6$NL+b{x$=H6zE0MQdAvz~lErCc)woP)C)^Gfv0hvlAe4zmqzU^oLI;9znZuN9 zAj5g!m>jn8($(9H?3#cF{MGu*&OR}=wRh#gW~7ZZql#tuO=PGZ;KZ*342-GP*9?3v zFp}aju5RRo^e%I_b%57MIat4xvAQaBG1WKdovXE1YU zSU~Bx%1M0Qlv(r~qvAx{NbKO% zuPVr^)@L=iEK*R;)X2Qu%j@13$kgvVh~<{5n74n1X6YZL;>Xf;JoVgY+bu7Z9l4*? zS{YEpyRGcSJ24Nx%xZ7dxY~-5zR+S(*J(_0lSm(`itZh??J)&smqlR%Qewp|?eb{FvIn{u2h@wbD} zh)Q_yV*%gzh!WR=Br~mP7NJ7_gBn$f{vGP>W~sOV(i{@-UL@BReq`w0EO-38+NjDw z{FITL;<<=_@Ib^Ne{T-M&NCTyS0I+`5m%N>1xsdiPP_Azy9+D#1Cg}H)>O)o+}+HM zQzB@2ERvnez#fqf7M9oY4NFO+eoH|?c3Ix3DmhvRdAXH&`9Y|I+0$)Y3+FRKrw2H5 z`hrh{GPC~T@#lnU7~cfjGqtBimJ>g%H0NpW&B?d6oQ)>LX*|z)RZV9~e%D0IvPzhuhQYqT?psEB z2M@h7^mhv+a{S8mCBceuMIOpyhD1UwsV-djH-?yUDnyoNFP`^{fCF_^@x6E{Q-54wv|0Bn^X?f&_l1ZU-`kCs zbns~g{}HS@p_q>dF)zB7m%Tm2DR%T9!=SICc`N+`hBWV|Ja1V@Yo2p{lS!?K48w0K zknLg|Pu(QuD=Ixc7RNWw3;0JLJ#)xb`Ybh(oH4Ltk*5%WMv~HEZZk8z-1Cl3R$jY%Sa&O#%C#5SB zJg{EmDI|P0F}{0FsIDxm;+(9XOyphrJ3bv|8tiI$*y_*=#3b8=TNOT^1Vh z^3du4XFk@&?EGWq(J|5nSyfmiN1aD9FUABuD08fn-O$^N@6o}$r6n=rx|gRN6X|L! z7lliWsKF$(qP~F z%Y#Sp;D@5YmGZW7Hjix?x)ML?SX{Lv7KHEP$f;-2Z|U{x|9s-Ritn)SU(y*) zSQ|*Kl7mi0M0U~^Qz-)d5)3{Q%jOI_-VQaB?>sg2&q4d2cDDVdN#Kx zD?@wc`L+OGs^2Dg&0wjsUC)Ex|$b%BT$HO6Y@(? zGr0MrZ8CdW&aiG{j&;rd%YPfyQzQCIs>@|_7{m-%7BQe?h{S+ljDr!499@>_DhW}n z|kEEN#Ft5CrpTW-3!?6r$z&%08ZA^!+DA$ zV#^oDHcmh1xg>|Xf98*G3e6b%H?mCi8wF$~pTQ$H1~TM_JS38PvG{fco*|QM3uD!z zd3&qzTka;$oy#`8FV_~;I8vlca!B5^{Pwu65xk^$;z&M1gtFCo2*1YHo5fes^tu2)|kf(WB zJ*;u%2W4L~A9hNsmiTp@kiY&t0xz1Huj^OKF`Hj0ye4q2@e=$AJn;Ky;K+Er?ko1> z&-xv56~2r2d*pWJl;JR0U0LbmaLmu0w+ohwx3TSKM9$7_l79O_T-fc{S}L+Em@tT= zZDvo%z4w>_N?-#;zJ1EO$Kx!M$-#>L={IHrzwn}8MmAVlCY#>T4D26RFQ>(FHCj3P zd4RF{Hc-JJ_mGG887$d~05^VvFO#m6QD^Kv&Volv|2~D)vm`*8(^qnF|24*HU!b|w z72_(UQG=Ne-6KU{ORKGvEwM8*|1C+P*&>moE3fk0&9m6#%FQ8@FJesVf_1rjQCjwM zCh@Om+3FFon!>NVs1XI1oQ;b$1=sPk@5FKP6(&^Q*BPbz0=3}dxNMA7iNr~V)tfhe z?#VMIpImPxu`E~(H*=K!Om}}XX`da&F+ptD70la)In(EM-F$P}!Q|8iD$MES{1l*n z0{bnuxA`3by!pu*zJ}3QmvgIJ*OeI6ooQ_qv7)+EKH@ZI;NYC6%Uml7S^o&j_4rT` zYdB1cC9I$270=CC&VSR=j{E~9nmX^C`#8^jTA*uVlkt;53nupDoWH9W#r`g~&(~v| ze+sm>Ojgo!na3vt<7#3}RWI<210#8lh({g1$z2fOQeB*POzFo%*TsYI0YkY2!j3d- zKsk>mxI*^c@|pcu25yhm_WOo>azb6(%<#hkrIB~a+nAc&fk=z_CP3UX9m7mGHL!3$ z4In$8<~(w&ZE6 z{8(B>=NCrx`GAnhLe3=emMOb4kKucR!T-9@GKdkfB1al0^gAZy)6gpXn#;cm>Wdk( zwvn4C;qSdjylBb7ofhKFg-^+D{$R9T3WUmGRNgsd3NQV47BBx6UA)A%fv0^z8X6B{ z(>(NvkRO?YhwNYsURMpdoSzDRg6a7rpJWN^MGU_$l6~xCawji*WH56k^BLOuT|BCO zG^(s(LLq-!RAQ9x+0M)kWf4~A6_DDnVw@Z5zl4q7yLNb>PQ~M8uXH;P*&fhQ$V~&% zpd%TXk&?sWV{NG|?4E!S^r=_09_ zjL|hbX-y#0>`oq&=_icS!vTLYnjLGTsAI`=%$aEZ6}_vN3Bv;B`WN_Or-0{}5yu5U zz9SXOdp*OjX9Mo}{k^ihQw)17!Y6*5NisUqBZ-YDFZQqIhVt^AV6$NC$b4)stlzZW zJxBAYjUSn@=S`nBJDr-J;!vq|HYwS(-W~rN$lZSOmRnTC&(~EllfxZ%4X=!>a0>a@ z9(TX~j#?P$LUFXF)EplBQA9DfsroHV63y@O5AKgf`$yO?y>kY` zysQ)9u0Yw{{ltvy9w>#M3&=a5+`uTU4Rnp0804VFx8o19BN>@YN=Q=w1*~lA1HW8W zG$y`Z_h4fc5iNXkRu26JGqRdw9JM3HbNCU;*6)!UEDh%JoP5CZZ}R*Sy2NZi%B%=? zlvS*&r$lTjDw30c3J?A@tB<4Ojq$5l8yiM)jh7w$gy$&|N*p&z2+w7x8n8HyYT`2c+h&wF_wRllK9 z#z!#hqF~Lccz$&Nuedxw)y{OU#~es27EEnc_CmL>_IKO=WiK$ahAh5GO(kJ}vR z3-9;wV)~(+d+dA+yNc9YzfGrC&O@~L*Z(+xi4>qPuLOH2<9<`5b9Dpco73|dSQ>2b zng0Ad#=OB?KPan{dlc%B9FbXFj_?#O%- zwt4)9NWnPNiG`tlgZT+Lr!Tvd7uZxfN|Gq$UNT7%ZFt&eB4!lI!A=97b74-y{DhLc ze>LKP2Sqx~d1h(W#;iWy1oF*e;Bsc*;y~NE$3u?Fn)0Xt0ss6i1v$)qke73#<@_5w za{18Yp+`mFl1z16Ldd_e(LY!bw&u}RG}?deLK-`X$Bv6Em@6y!SCZam ziYG-J$y|AoCaCdw9q0=`dl8ER9%Pj%4^@?S&Da(4cNnpq0V}Kc3HAIGMPHt|UyjuS zc}ERdeIFzJQ$Vo)2t-~s>Rg^U6^K80s3T@1Kd=f63TWodF|VibVP5vLEYf~?H*Q}` z*sa_aF=K2^EDPzU*hfXo^gGvNO@E!iUq+JP?N#FACrr~_63{<_OW<1>Tof?FuXxAN zdYPep12f_JqJNSX0G9p0hUKqF<7ecau+4?ZoLxn!^uwfK!J1&f#YD#vd>UY3E&nDl?L zeBrH6;`c^Yt5Ja*GR+U6#rp};hqB6;t&GXcn!tkJ8w}%oTI`CQUmR2=y0XdSP=JGY z#r_hQn*t;O9>vhH**(10e@P(bMc(Bq(Pw^@h;y?GJij(@eeS)6PygG$IW`M4+rNb# zpG&Yb&x}l>L=GfIFzMR@>MF-ok1CEuXMLEyO*xCnRP^O-r8m!8B$4MI044f{F?|OG z#x!C<9Hl+X)Ui23Qk z#Z(nl#+0NruirIt(%eQB17FK@e;z8B-^n0r#HkG36>^2uPX->%t6mhdJXtyY8$vB5 zmdX5T%KW-InAUHpj_JcNp7!0yCvx~D$L4SFw6AB$@y~dSlJD6hrcUR%hlB~Cy1dCB zWqbNaA~$YO3z^(O63$iSF+bFgr#>pspv(hXp;_I{SXD^_`7y@mL^hU(seyF3@jrg6 z^$7-6MV^n7B*j&1%AsM6Wt6^&G`h5GkhBBz=Vfn=24||#a$i~Ic$(E3zx5?1y>9HN z&X=SYkL>+UzzYJL{UmC-whnD_$ixPKWSW5p?v7< z!{dIJEIpGt3^o5JM(FE6PwM{l?A7T!^R?lw$&H%v(@7zNf6kJcy?z!8yH+xXHcR3j zC?`3pdEHwB=j6Zj5>KR-F(+OLCiZWh%C6@`p7uH!CwU7Q!5HdMyH7@LR#FXaB3Y)9=r3 zkY&VZ{zydmw3DY-O`aOdDs1P~M@JImR~r1Rez=H#SGv6miro`vLQmHBt}D}Pha3dsz;Q@=lqiA{4-c@vRkz%rh@AjhyYk5 zTg_&6poM|KaaB1!<%>+--4QZ%1Lgaxr!g{r1XJ>IRg1?>nKE{AUhDH(UiZzwfsc%r z*k|&}e@f0L9#gI3rTa>bfRD|xtG$Q8KSUG(s%O#=3?)2^BvF}AxRm*P8 ze~<0b2v#R+!eoa1oki*273&SGma7AQSU9mThHMx1hNDAivr>kh|1Ex&aIrSiuQ_LW z6Q}x*ukz05n*#sw{uMBo@8`tAzpl*Jagm8s``5=phccRR=^ydVPqNCqdw}Vm5HW}C zR~kE>fnx(R33_W}b$OQ$W?z=`tC{w^d6R9=V_ZMZ?c(W39)3quEOTlzEfaGrh<7G` z!5Y6OqAqOfLm$|`mTutT!LX7PR2HzpEJ=1|0n#9fATKBr&TE}~H=9%HJ#qRQ) z`mV_7V3-MFPK2v>U}F1Zz10YAr;J;p-+FLUq%ZyngVV7RAN}*=q(H27T;7nMYxt6x z(KSNcuj|Wi4EP?YJd$0ktlx}bF9uTg&mZvyd*5Gm4!B&Lw^4H z`8>8T&{97ak(cv)k(vEquy93O4*o@sE|ES}bK*YM-q4vZg>UVORO=g2SBq%EM4;*3iO$==oX{Fz^Dv{QZ#dLelP-kx}vnpE953|F=LMw(1liX(9H9kj)p~-rg z58?6a)AOeJAJ9|lt)N8at(J>8$MRez$8u}5^hj<@$UgZLu7871Q}heJ!WM7%^b;}X zg%;{RBpP><{wb+f-~lo>H{$2$n_0q@()`8a<%*>rbv+VM&kq*LrB~nMT^>Q}WZq0= zSZQt#j493=Y`$j%ic?W6w}-Swq7#38CNK9Jer;!VnE&m@QQ?c-{fPPPAn3@X2xGD2 ztb)Wl|4tpKjOZWGu)3Q#3TV!HhxdpqT zha#sC&k|2yf3i0)D^C7|R_s>{Dzgeafx{u*qC?OJjENIEy|{?~!)twzMZ0hi~A zsL};YrJWn?M|QEn-}B%_IiALBxCv8YMbl;P3FO zTt?VpT3ShAR$L&LFixEUOO8F&bv5(t^$6J-MRJV?^Kyse2IaT+UB?5rM1=6QDv1pL z`tH^MnQH&E7Wb-$^Vr|B>XE(2F2@|_v4$ifB7=;#yrKQWvk#T{&n-XF+5?!>R)J=+ zujIxy*;f1(sG5l0*z;a(c-}K5?UT!&ZCLxJMB}1sYTT3%3sL-o+m0-9QaYc#YPef( z<6nHAWey+Y`FW4fKb*yUxiV1VOaw1)x5qJES4a%cboNSgU&7NqEITWCa2-c5LxV46 zaQ`C*FhgR4vts_eYkk1@z{ z@67Y|jp*Zeqbhd3Ih^UcCXzs1?8*9*8Q48L^H@Lfi-#jOu&d_NRB%rqURHa9VRm5X znG{GYq5eJ3yEDMpzXBV4#6aF&`ZC^+h7LC7?EK!Db>X(2|NdlmhW-}lK~<*rICh_9 z4J*T;f%WAcM~rV7xAHH}4Kppi5rml*{{h{1a_%sD&XjpQn?-a}V4uM&^f3=t!bz@9 zbsX?cUg-C~DLGwf_pkr)Q7V#2Nz9!5xT9}m$bP4kq^^gvAr6+HRlc8);Kwk0W~2_> zLE_*43LT|iHJg(aOvU7>|LO|l&qvm4nR8vSv*A8w+QMkv^4JUgb9m7gBcPw`ksXi! z+QpQBZJbr+ra{@Y{K`x{JAh^$V34h*9WOgKuuhhBNi4mWU>#f(=pc8>$l+8IF2J4I zkJ}LKg_Ax02&dn(Y|mdjdoqiqeO4@7E{OOvk|&q50tc8+SBEOd_c&#whB0uTL~iB_ z01}gTGrbEUyfTN5&{_G%ijC32MTJGB@=X^13ev;~oP7yTn%fUQ9*N8*mKB)DFfAKG z@q?CSdD)kz*o$kLTDK3+ePK=z6Z4{o{w#>o!W|&atQNfN z`W!6pPF4?w9T^~;z1bJC=`IFs4+T)oIwKq6kv-;k z!*SJ_Cl6%Fj^%M_$*aW_^=DqRG~y6{Q_DYVhNe}-;4cE-k-6;}(z28_{NTu{VzKhY zjM0dI1^Mr}y~Nl&7cJ=LSLJ}|NnUV9&aCooH~!5_wg`p&@9%W&Wof^aCA27>1Ui`^ zr$x$LUKd+)5kpr;D2?Exi^PI+7^AbIO+2%kg!{MOR9~K@)NlHcr1B2a*)EVuu^c_@ z=c@g#bW7$n6X16I!d@zU&3?%)6r3a`WJsCa2p0& z5qPv5C{1G6i-9F@wl^;m$(A6ZfhEko^okGSHK}EaqKIO*)F* zGUhGeYg1xNuX_Hy`jcmctqf;#{QGj|e0NQtmYJ9GWPLw@)ns#^@BD_kY+{EpGK+HB z#ST5@X__!Pt0F?m`2%YbHfQtDl0c_}7VUUg{Td5=Vq|9Q732-UPc$wHbT@OuA|3@d zVVs{1J>axBVt)1I>S$-J8!$i$%xCbYMVh$1!_NiE-xlf4-#hicEmDuaL)&usN1Uff zsLSV4eH9H+Nx-$qP>a^Dmtp@ zq@uHmE-JdJI7CG^72Q?zP|;IGFBQF29IE0l6^E-hLPZ}HN2)kVMPC(1tLUfV7#00h z3{Wvp#UK@fRSZ!vRE45KRUuSpDvnigoQmUB3{x>&#R)13Rg6$kq++CsVihGSMyV)O zQKn+FiZLq6Rg6_pp<*|QKO<(#RL^~DkiF!q#~(8S7E3yRah!)6^@FO z3Ri`vBCTSwiYY3lsyI=_G!-YQn66@mikT`-RxwM(Y!!1<%vCW@#e5YDR4i0+ii$-l z7OPmI;#3t&Rh*_`nTpd@ELU-ciZfN5rQ&QA=crhr;#?IgRjg96TE!X_=c!n$Vx5Zh zDmJLtsA7|f%__F2*s9`u728y7SFuCIP8GXUT%cmNiVIa-q+*YXy(;#pxLCy{DlS!V znTpF*>{oGxiYrxIrQ&K82UJ|6;#w8gskmOn4JvL_ag&OhRotTDRu#9YxLw5^D(+Nq zmx{Yp+@s=N75AyQU&R9|9#rv=iicG^qT*2%kEwWE#S74NBdU&RM1K2-6MijP%%qT*8( zpQ-p<#TP2RRPmLHuT^}b;#(EpsrX*Se^mUS;zt!fsrXsNFDiaj@tca@Rs5miPZfWu z_*=z4D(VS9fCLHz5(4!F8VEGxTP^~P1)2yn6=){VT;L#q76L5=4i;!7&|094KwE)! z0__Dl2y_(aB+yx)i$GU_Lj<}BbQkC$&{Lq7KyQIV1r8H9T;K?SJ_1Jy93{|K;Anw< z0>=pS7Z@NgP+*Y2V1Xe5Lj@E8RX_-60>=s*Cvd#LFoEF$CkPY@j1VXi7%5OJP$Do& zpj4ntV6?y(fpUSd0u=(|1S$o_3sebI3)BeI3QQ2F6PPG4Ngyep3m5{XfF)oHI07jF zSHKfU3rrT6A~03pM1g4nCkad!m?1Dz;ADYW0<#6?2+S3jCoo@Nfxtq6Qv?5PI9uQxffWMh3ak`ZC9qmxjlg*VYX#N`tQXiIuu))> zz-ECh0$T;n7uY7SU0{d6PJvwl7YOVYxKQ9Cfjt6y1@;MCEO3dyr2>};TrRL*;0l2& z1+EgfTHt`dH3HWPTqkh7zzqU73fv@cv%oC^w+h@QaJ#@A0(T1BC2+UEJp%U%+$V6q zzyksg3Opq6u)re%j|w~{@VLMe0#6D&CGfPsGXl>FJSXtHzzYH|3cMunvcM|>uL`^- z@VdYo0&fbuCGfVuI|A@ei8Up;5UKa1^y8DQ{XRwzXkpgsHXuMNJD{!gogSW8fa*! zp^=8h8k%Tms-c;N<{E!z8Z9)m)NrtdRvKDsXrrO6hISg-Yv`b%qlQizI&0{np{s^N zG<4I@T|*BIJvH>w&|AZy8V=KNxP~J%^wDsnhNCp})o`?iej1L^&|kv<4Ffd{(lA)V z5Dh~$C>m4^LW8E^SPjQ%I9|gr4Z}5@prKI12n|IVMrtV5P@-X!hEfe>8b)gvqoG{G zSPc~##%ZY3FkVBIhH4Ep8frC6&`_sgqJ~Ktk{Wakh6YoErNP$VXh>;rHFz4*8YXL) zqG76r6E#fJaFT}U8fIviso`V|voy@sFh|2&4f8b2*RVjtLS~>#&0RXkr4}x=bm?H1 zTDjEPr8X|Lb*Y_8?Op2NQb(6MxzyREE-rO-=@6H?xzydI9xnBCsh3N=T{_gI!(2Mt zr6XMGr#bF<6NqAX}n8SE>*i! z<5I0l6I`luX`)M$TuQp6yJWazx@5UzyX3f(a>;ecb1Ci8WS6G6G}WaOU7F_7NiI!y zX@*NPT{_vNSuV|XX^u;CU7F|8e3uruw9utfTw3JPVwaYB`#g+(q%4P?$Umju5jr}m#%W@ zYL^bUbd5{bx^$gO*SmCsOEED^o~pKy7Zn)@4NJYOCP%QkxL)D^odKKy7ZY#pS$#h zOJBP5l}lf{^o>j3y7Zk(-@Ei5mws^RN0)wb>1UUIap_l=esk$}m;P|+PnZ63>2H_* zajBk1@Q6Gr@F?L?eUBP=)R5oC@TjpzO+0GqQ8SO4dvuUTEj()J(ZL?I@~E{(Z9Ho0 zQ9F;?d(^?BjvjULsIy01JnHJvAs%(}sJll!JnHFDFOPbAbf`y%d33l(M|jl7qa!^! z%A>v>9qmy+kB;%EzefW+8tBm=j|O`*#G|1eDITdF36C_7j`ip`kB;|fm`B4sI>Dnt zk4AV@FRsz)b!G|i)vJeuy&43B1dbh1aY zJeuv%9FOLDG|!{?9xd=_p+~29w8*2y9xd_cRF9T=bec!YJUZQ@RYv+NP;pn%bwS zLz+6KsZ*Ldr>RStx~A!nG<8c;_cZlLQ_nQ@N>lGN9h#=Y(sX#5j!09VG##0yqtetj zO-HAxUz(0dQ~xv#NYlVH4NBACG!049&@?G&Qqv^Tq^0TDG#!_w>_YMM?=)3h|5l&0xvnvtfN zX*xMgv(hv>O>@#TH%;@>G(SxX(zGy5r=)37nii*NNt#Yg(^CIC@h?T^asNKKbRK_} z&*Q&D(Cp*7VczOL3>_04ndRQ+rhJ;dAxy&MUG^Tyz_w8;$WNg9^^9=dmJDAV)BrM{ zkd_k$k+`IYa8S3s=Q0Ik8mRAj=W5voE|A}kodmS|E$-CHFm#R|5_#o z^LE7I>OoRc!tc%LnM)4F(#$t;lI7Acb0g);{HB}lBF>MjF6Hz|$oDUK!c{?js*wA0 z<%n~iujcbtk7C8CDh8SXJNVA3EXr?vQD(C}{$m;Oe9SML z=_!g-kDu_6iy6as)=wj---#8=(tW`2#{*J0!5MFu)tQ#Fqrv5V^Fqjk(|Kf7ki9Ay zA4m8jX5acyt20+cVwvzB%)ocEW4W>=Co1Q#L~aWt!pT_9Ert5zcOw59VH14IBE-k< zH=7jkPfl`v$^0{=WLPW<_bubHESi?Hv8+4ctc!WpeF1;sS=_IcHbvSJq>Q`>z-64-ogC7m*E? z51#eLM~r5Dl-OL(z^{U3{Toq|Ixb_o+ZxfE&GCow*}(J;3=*{EBiL?2HGYW4-5T14 z{7i-a;B!jOK#zzSod4R{fSkf*ZvBLFKFA}vxiu&w$Dgr%nT2+0Fl=l^-ur>gnZ7URc@x+emTWyP1+eLF*M z4%9Du5loiUD5m7`z&B)`p^jfa(wRR`1x_W?B`$9!79&*|t?PfgRa$opuRArTewp&A z?0$daiIb9CM#=Z`|Y^6y)m5oz6siV1QUvXu3pO<)Gu4ii@9aM8 z@OD;*sz!3db8MHN#i~#d4UP3h9>h8S-%^>J|Gau<^T)*#%lo~KOsXH8>aSRSCtv&I z&xn`s2fmwn3Z<3A6s7r8rPYZ_lW9tmlaxl&l}4GbdpFvl)PGQE^pMi%VWrU{3O%aO zV+uW~RD7T`|5T~}g>uN3O7Cx#-ds0m*`R@1&`@pINTtTHq5&PGQVYLmKnMFpgG6gJ z(MC|ZhUHqa!;t-X(sZF~FMT7dif}%mjq4GJczG%3GmP+&(zgM_Ch(rRL| znwSz44GN~^7Yzz#sWkiluV_%P#4j2oma2)?@#06?%x0<+6Ex1Tc>`@bY)x@bO+2C|9#s>Msr2~&Q8XZ_Xi)H)TJXAB@P=9tFB;JQC>j)erWSmz(*GzL z(En95pubf5Tcv+gs`vj;G^pP~P)k7v3u+~(wV*bF+6rnXsJ);Lf;tN7B&f5XE`quW zIz&)6LEQ!Q5Y$spFG0Np9V!xs2|8RfJVH<(K}QNYN>E=xM~nLX1RW!&zi2!_G#Dso zkf6bWh6oxeND-t85`r{A#|k=5)IVO(Fwt;}>3MnN|Tx>*$5A`-U>$`lPKQ#2^JOC&NygT((X8qi~c9vAe4peF_8 ziUtMGih@khAn}5rOwl0mvPirl>c1-Lza|n=(V%{&XpqPh4d{K5_&_8+6p4=nWr_xg zPX&D@5}Bd_#ft_7QqiE`M?pUc`dQE~f_@eBn`rpENcwkcC{r|`VOnCimN-F66l#ePQPH4&iAJNeM5&f2(+Wmw z4KhUo8mm#JXiy*(4GL;Bs?{h{G@ywZP0}c-k*<-Uk*SfTk*$%VQA#6MBTu8WMw2y~ zqR~{1PShGoMT5jljWR_8nyuB(6b%yDa=~J4`NNHuYK@j@bcQzLEN#x&TE7+A@-}p? z)_$edY?W4jjkf$?TB|Mpke_%iTCW|yL2Iy48?Z_1x>;+mMO%Jjy{+2voB6%Gj@z^r z+qH!|w1anQ$L!L2UZ551*62d5%SBqNJz8R~M*Fn-Gn2f5pPj@xNvufX+$2^eu_}qx zNvuiYyd>5pu`Y@ANo+`BV-lN^*qp?cB(^4TeiGY~*q+3WBz7jTD~St|*qy|MNnDh~ zo+S1ru`h{>lei>_OOv=PiOZANpTreOT$#jGNnD-8fh4X;;@TvxOXB(@Zb;(BByLLL z<|J-O;?^W?OXBtg#BrqoIyQIvVR}qNAyfW;&YdI7mke9W8YntfRG#HagnsXs4sSj*dDy>FBJZi;k{3 z4$;v~M|T}PboA8GOGj@Vhw3;?$Kg7T(9uW7kvfjj(O1XOI{N82Mn``g19S}3F-XT? z9Yb^s)uHH6bqF1rj$?Hkr{j1X!*mSSae|IQ9V2uU=@_Y_SVxJDQ94R>l<63)V~mb+ z9be!@X zvyLq~w(2-v$2J{1bnMizOUDH|_UgD;$0a&0)p41Q%XRG6afOa6bzG(6Y8?l3T%+S! z9oOr)LC1|cZqjkHj$3rxs^c~t_v*M$$D=x)(D9^>r*u56;~5>#>Ud7a^EzJ8@uH5G zbiAzN6&iAB__d5Qg;|Co->i9{=&pLk5@vDyCbo{R44;_E%_)Ev%I{wj7 z&j1XNfdT^w1N99wFwoFIBLj^MG%?WBKr;i)4IE^kg@Kj^4mQxrKx+eS474@S&Omzu z9Sn3d(8)k&16>SsHE@W5ZU(v==wYCzfnElB8#vU!VFnI2aD;(A297jvl!3kmjyBNG zz%d5;8yH|6*u*Sez1M3W|H?YCL zMgyA+Y&NjPz*Yn28`x%GyMY}Bb{g1a-~t1?4P0p8A_IF2>@~2@z{LhGF>tAY%M4s@ zV84MY3|wj8Dg##=IAGu!1J@e3&cO8sZZL48ftw86Y~U6Hw;H(3!0iU^FmR`VyA0fI z;2s0_8o1BE{RSQ|@SuT*3_NV$5d)7Jc+9}#2A(kRq=BalJZ<0^1J4?G&cO2qUNG>Y zftL)tY~U3GuNrvG!0QIyFz}{&cOEu{$t<=13w!0$-vJBelhT?f!_@LZr~3Ce;WA9z~2V` zF;LG0Opu8J6A2UbO*Amk&_p8>jZHK$(bPmU6U|K=WTKUc)+XARXltUKi4G<@n&@Pr zvxzPyx|%q|L^l)NP4qC)(?l;5y-gfy;xH43n>fNm9}`EKILbs{6GxlqXW|$W{Y?xo zG0?;y6N60*F)`GHVnQ_`OlT&KHF2DY<4p`RG2FxnCJIfAFi~V;q={k^qfC^U7;R#V ziEfeB3KQp=SZQLFiPa|7m^jbGS`+I`tT(a2#6}aFOl&r> z#l%(<=bPAOV!MeQCU%kZ;vy4!OzbtW&&0(hE-`VbiOWn}ZeqWQD@b+N8WY!=xX#4&CT=isqlueL++yNZ6StYT-NYRx?lf_iiMvhQW8z*D_nElg z!~-TCH1Uv$hfO?U;!zWinRwj96DFQC@sx?DO*~`bSrgBhc;3VdCSEl0vWYiMylvuL z6YrUL-^2$dJ~Z)>iH}WuV&YR1pPBgF#8)Q1Ht~&#Z%uq>;(HVSG4X?mA5HvZ;%5`T znE2JiZzg^>@rQ{&P5fozZxjEp_F70-sBfWxg@$}T%R*xdO)NCE(9A+}3kO+fVWFjk zgDteO(Aq*93vDg5v(Vl`2MZl7bh6OdLKh2NEgWK@n}zNcdRXXbp_hf;77n#=n1#bF z9ATl4g(EE-WudQyqb>BaaEyii76w=tXkn0rV=WwK;dl$fEDX1Bf`vj0BPOwV=Yuz7-yltVUdN!7M55z)xuH> zr&(BL;dBejEu3NDObcgOINQQG7FJj|*TPB*t1PUxu*Sl97S>u=XJNgC4Hh<9*koa| zg)J7gS~%arHVfM=?69!Y!Y&IJSlDghLJJpJ*kfU@g?$z-ws47sOD$Yx;c^T6EnH#Y zN()z6xZ1)23)fh<*1~lbuD5W5g&Qs0WZ`BDw^+EHX7P!WTUZ-CN`SdXlA3ije~5ou+h@S!8TgiXl?{J#6%}(aT0}8;9CB%*Nq1jieh47H)yP;CesnvG*^9B1Qr8^df2w{e1vLK`D&6xkSQqu54?jZrpAZIsy< zZDWj$avNi9RM;42qtZsLjR`jDY)rH<$wtzKZo{x)+OTZcHXIu%8?Ft{M%uadFEVOZojYT$=+BnU|G8?DcSZ?DC8)w=$%f{I@ z&att=#<@0D+E`^{wT(44&a<)B#yT78ZEUcy(Z(hln{8~dvDL=;Hn!Q=Zexdyoi=va zxWLA48yDKR$i^NUdu{Bqaj}g{Y+P#NG8=E$c+x4hA_G>|lt4p$-%WssrIbb8xJK;~X6CV3>p94o+}T=wO6{A_pTK z6gwz!Fv>xxgE9xB9gJ~M?qIBg3J2pHR5}>%pvpnDgBl054kkFLb1>1tBnL?cx&y<3 z>A-SeJ8&GN9JmfV2WbbB9ZYdB)xn7lra3st!E^_69L#kv&%t~L3mhzTaEgOP4i-CD z;^0&VOC6l%V3~u{9V~ZnhJ!O5oaNwb2j@6g;ow{cD;=zIu-d^I2j@9h>tLOO^$s>T z*yv!BgUt@MIN0jodRu61yogXX~@AvWkHg}(yot>SXEoXN&xVt8}rzW_!Cb+LAxW6WNpeA^*CU~eOc(^8bq$YT@ zCU~qSc)TWfq9*uXP4Hw*@KjCkbWQL~P4H|@@LWysd`<8|P4Hq(@KR0ia!v3`P4H?> z@LEmqdQI>~P4H$-@K#Omc1`e3P4I3_@Lo;ueogQ}P4Hn&@KH_haZT_^P4HPw@Oe$} zMNRN!P4HDs@O4e_O-=A^P4Hb!@O@42Lrw5wP4H7q@K;UncTMmQOf(g2nhG{c1zV(o zty00(sbJewuw5$XoC><6f*n)APN`t$RIp1b=$Z<;rGlQRV7FATdn(u?74%94d!~ZD zQo-J-V4qabI~DAk3ie9{`=^3Fsi1Ev=$8r(NCo{QkqRnP!RS;_l?ukBg0ZP!Tq-y`6&#TYj!XqdrGn~IP@4+sQo)2&FfoOX zSO2Qdrs4vw^%0joxBh6po0ZA%aQds+Hy|!#U(FComftHI4C*}f`Hun=@o#u9RbXsj=Kf1|`#n0Wla%%;d| zVCoVv()oAB$p9Ro52RRpzr{DtjSMZ00Tfr#u?Jn54xoKU3Ps<{?a%zvQPaH{wRoDH z5z`&^XB9C*w^ZA~Y~jDN-Za#RV@%N)82Kw8zr+CYhnEhq?xe0mex3TJT`z*pT1Rw# zg+4b`?Lg--EJIm`rubHUyQawgc2l$<_j}n;xLO}O{jdOh4_16DOH}B1*2>R-_|53U zH{F@GqijrpiEeIcg-Y{#cy!^qg}szsg!^#%rS$&DT&Q|go`~&iozvM4+1cvjb}V?- z*|<0uii?9&Crqs#pK5HZpU{YNWL=|sgR9K}6gvI_6VNA6&IQ{CRedN5kzJi~ROe5v zNW7O5Q{^&fqgvU#dLzNs^$%chnLc4rX`d7sfU@5(Jq_=-^Z2+g!-AgF7uU<^ZkxWj zJ{**5jG7U4%DRG0!4oc#jfhiLMYdfZi0|izm{Mam%0ra;uC8$rJz2?GzXA2#P}Y}1 zPQ=3Qo{!32&ZHX7uRC4@nHHGLyb(O27{%PIH68$0N%M2d%EmG`wJQ)^BEMrr*|`QX zZDZRge-FyGH*5Yp|e=rtK0z5 z#u(A?mN*lOtoa5;3)jGMuf{3Nr}mkNpg{v@Am}Crf>LGNB4nn0BJV?R`@?V(ajY4; zpCL&-Yi~GxJDgJ;YH}8-3S_QOW#d+@HNbX&TGnB zdlU#~M+0L8bY$0OLrCq{dWn(L=e zYbr;?hSbp$1`p~pXi#@_NzA~9O+ zx-ZoKKixK!aoWR?U1%I@%^dykrbW2DjB+?O9ZC1I4uf4`?$JIv1_6jWSEj6KArl%Rsd) zQ#K;U^8?3QKs$KLRv$6thWQ!{=tR{L6ehxI<1HZTPD*h&lNcM;uY=;gkZk3n4Dlew z$3fx?6mOdPTDn4f8Fgz255v?JoV z@ytC@$uUYC8C2RfpD$5l%5)=&e#y55jzDc*k0iq3Z=3iSNVQ0nEJ8$Cy?%QXy>ZkB zWAD#i0F(Yl*M}B3+zqWjjTT#cxq)^D-#4TZagoC+ax!YOnd+g`Q|v|2da(UZvK^M1 zVl8V=2hV2HqWN?ILQjkjfD$G!9nnz7hTa-v|0-2n5Q{mp6z%=9DzR8hL$!r1Mu{I8 zrt0ZfK8d3EuEPx?k8W77VuvF8)5vY$;ThKR=Rmvbl>SH!v9)#|6uq12YJno!oSuhse=!Z0p1lF^p;wo5+@gr{*1d zEwqU#VpJtutg))}0a#8o>MAL)94fsT(;|uGquh3suB~7{?<NoQ1k1mCa&cwqMOy1(9yjMn%s6SbIYSXw@^7o^mU=2ipx?Pge@I z0-o-QiX0ww5qYseSCY19FEn;m#jhr$P=|4DlBI_Z@5g_bjR4%tq zc&DXl!h^~c)0+gWoy%cFzsW*}!Mtqee=Bt->|r1sFI78225Yyx%+HW{N2Ms5WmuD?YoV!Cs=@N<+KtwI zFXS{C9p=+kj~)Q}L7p#7U8L({@_qu5?pKR18IxY~rDgU?Q_(y;zQZ@5PDS=VCYvVX zT1USlZ(F%sET7U`KQnzZ_Hx+Y!pNBDHDP;3z8&gxqf$lmSP`E$<)a0^*A6!pZEpeU zbb&H`JUPw1>3%5oKqGV>_L#7i(sK8K+&?O-K?qg51s0;ru1co-*sFjyLf(n0$dZcs z*y8PX^qlEYWk(E&S2h6gJY_T1Thd#iB3CK<#v0aIa32C=$!9fD(?DGniosZ*%9Q)r zR>yl4tnV{j$BrIY3f_M!HI!8k&9m>pE{7g&GA2ca%v4BW5??UZnA?vTE_5pa#KeP^J%kX;PL7v zeJy%7taaZOYu(XCmwmZcrOo|R|FM0#N1*>4WufvNdp>=58j9RdDmjuF9ibV$JUk zRB|ih?$W*8C6MJpMF|b@5wIV!4rl#XK9|6nYBc28*O+NhtiSCEJyn@(e4gSHe7cri zXmX3h`j*dJ1_RJViQbqRV+~i=K(st28Xmjhv+aQpEWs>{HYB3P~MEh&C_gK2>h*tk{@t@(C0 z3eGK!z4A;-dWwC|LaF+D7EO-Mjs}f!mar58`5@LX+yxx~-Hm2>V@Kq3w>Jvej~R*R zb2^_HJ%~cTG-@E1Vzua*+Q#vECm(lrL!&HpZ(4YcP|DdNMEbV2Cuyh?Iw~ zB20y~kmw{MQIYj1Qa&=jjf|{vL;;?@1!rv!Eojv4rfG`gBWH~HPEh0!Wrl@gO6@($ zH%ODpv&A16`W$htKOakPmEp~f=2Y{{CVX4XmETr3&iW)n4x-hXnqa9`oBmEe=(Y-&o$OZ zfbUU!jjD0RXa0VKSFbhANr6~d5l2D3VOpb=c#ndc!rRC#lg?;#Ii8c}1M9~ylTB3N z*8b936nLVMI!|m)u_Ec);O3^zMfQAsBh>jrWtdg=Ytzjr@j1hoq6_o6;*;RJqxPJ$ z(n5t_3-a@%@yWe@42-lGMW4|YxOa!-j$PA&q)d#xLqacFRB!q5_mDToSXO?1$ZU$fXKkU!uC!WQgjy_B4MtC4^XBRT&99F-b!>3&3%Yqx zUT*9y-z|~3#xw~&cEPi0uXqlcseG}E7Kxq$#Uy~G&=dRt+J5gSfi#U)oJg`Q9z(V<$8x$kJP*dj{7M( z?3UAWi`<4E1mS(AA*$#R4&Av=%nGv3_WH)B=3yB>@|~otF8{DXJD9|_aCkF~-mSee zdg66IlUF2O+|zBc7joAd$uV?t8>&IIb5&!@@E+VuUP7sLQq2_q##+Vv3Pm5Jnm~98 z-2_kJmHQp~B0xP}ERk(S&y|QaJ5zrwOxxDj4U)Vkt52`p#GVeD0ZHD_U8vA{Q(-b} zYpAIq-xtR&MAlJ}HP{~&zK32GYcuDYGo4Yhrih5%DC8qg2RORGC>uK)*xF%T;BS;T zSoJzJ25ZH<2-=5~21XRbw>Ib$z+T4v;vfKbzqGe=Rn(iY%gLMR5cKACMyBCKR%{On ze)P6cPdT3e(fcM{l@i46msQsrq4bR-$88Ts7of;pMD}&ccA%QL-Uq{c z-d2W3@i&+=nFa;iuEcGekeY1y=HehZsdE;de4Uk=QeRiykZQzZ>&+7ytEWw`pEhxN z)`E_Rv<-)~7{>ozH}Y8DDNSSM#tNB_y0w`0DdOF8FsROsjFjGS;_IwEK#1)z^<^-v zLp_0d?WBaK%@S+F>N+r9XjGP0I;ZVK%5F?i&h(b3X|H_IBt9DaXADTq@*ky z#rG{<0Kbcj0&tGXI|#mZv)q*dIpFA@YFR zss_Wpgw@wBM{6xKl`pcQyHh;6_hdEl@d1Mw&kR)XaiviljF#zW zy6LT^f(2qHSq~aFpuk2WO+HPZ^l;Y~nSG4L#TFnF>0yX8PjxrwEf!vDOVsl!Q*ORJ zGrJV$bKmVvZ<~l$iFc09G|pF5#0y~dhy1Nk#V-vze9*${NxB-JK+@fn!YR_1HKV=* zlH8``lrfKZ=NgLKEaOv2e~j^8V7wvo)%3K3E;R|&UL5(G_}9z+cy=i{U@CQ53f2$P zAUga9$H*Ac;+V1A11x`0?iQ9alc{?Nvc@V)q@&Q>-F}5i>}o1egm7_;DfQAXl$;~Q zii1z2jsxu!qglMR!#|GGJAi|jyjc3tizAGC4&<6_5bEJOt)z*_elaSXw!pZbs6*K= zDto8X#`fZ`4s!3O3}R?;$w)qSKL{UkUNlV7Gh>|X-f$KDRAxQ}E904uLZGGEp$)M- zZ5Nc-P37h9kA~6Rh~9BLS@ngf4QX@m9l>-5MF<~^T|iBFH7J`^E#y`Rmu3Ul^^Kx1% z<=9?K+g+sR7eDAmHXWKe6qT3o_+5QbhbrS@tj|Z=gK~uGw-cvKw}gKm@_nG>6X!1Y zG`$HeytS-ZNr826_EO~Bqi3J7U4Gh;c}R6Hc`ll}f(kU^0%IBW_Q*D<#t>uX=$xbZ zv@H*`7nxdCaX&g9rS2D*BaVIY_J0s`do#AeLRjzG9r=fw{0clV#B%99+2c*AMOaU1 z?|leLUBdGE9KbS%AhRgyTDH4<9X)G?Y0Z+Mc1YAI(8F>?SymDs5WB%9cTl;7T(?() zYtjsf_7r^;ntHOL8c|r!I?q2K+efwY(3#e{4O^pyDp~wYhbcgZ&qVz5JqQd(Dr*;7C@z5%=W#uO^_Os`-w^3PH5ImQL@R@xKPml$gMjk2>Mf=x7tS=VKtw2Bv$KRoi3cxtPp6El$y+!(*D;UCd)HSLKNJ zDmk}H@G@JubMi^1BF~Vgj2Hp9lj@Y8(do+iml6_6v(Q=EM z+an+zpjuw6)2+ioPr~4SQwCR`zSDg&Eba{HuIOo6EM<#F3@^?v8%a0E*g5o-kYQ^h zKdv3|soZ7|p-g#kafVi#<;Sp(g5LS~z&)~{P#kTiaOaDItYjhymW`@^VR{??2%ZGx zNv1@c&1H>uA_}}%)wz7c$k_Sq{xJ4cQO~6{fVJ%F1;!PIu{gWSSdRqjt)r2yS>8po z$Gc0x{yW0}HebZ(zXW|hrHc~#d*Y)g`G|^&;pP4M?w^0)0b|5-&N$DQ)$(7Y6uP7N zoU$N1z-J#uOu>l0Rc$FoGp*(pG~@fqgQG&0y*5IigOoP%D`V5lr$E?bhAXI&Rb?77 zuQojsOLcMaMRy@Oxc;}42L~rDB`*i*hq6$iU~87u3_XlA3KYA9tk_`?_$O5v>$KD& zWb}$Gopr9eVB<+y7)^_CJI!8Au7WVXnR?I-8CKknS;>yw(>~;=2j#2H;TQ4p@u9Gs9rs43_WT2dqV!RRS{y*$VaX{!2f7d zIr&XS8_IZ8?O{bqhyARvv=XGvvh0y*$Ne@yp+_2}(37#e?Z%+m10~~fLP_pGp z%&ZW~c~OuX26erZ8v@gPCD4D-33b!JIId z8zzqpvyTgt$A{S`gvk@b?0I3bCCr{5CKrU+Cxyv{VfLahxj4*T5+;|1*(Zm|Q^M?1 z!{o9s`?N5*Jj`AZCRc{pr-#Wi!t67{E)3R(!G&RPQ5akt2A71vrD1Sc7+f9(SA@ZpVQ^I#Tpb42gu%68a9tQ&9|kvs z!Hr>XQyAPF2DgO4tzmFm7~CEPcZ9*6VQ^O%+#Lq@gu%UGa9#aqNf6(-rrOhh zpWt8?L}k*Pv0Go}|Y&cMb(mc>| zFLd~MC#%pZzM!E^wK7GEW2H7N?K^y8EU46)2)vKXNzA*`!?&yz@BmoWHOl3wTUgxd z9STJ?8ftt<=H@jO#EXm??YZstiH)-c4#!(L6tI87wA$%)_0#AKz|iPCPMA5fQ`WIY z7dTqNC7uaY%rqj=N*iZoS(O?f)$>Lj_@d6&Bv0Y;_|sKWr#Btgf6kohR9#);geLu- zPp{~k#oLB{B<6V9XkUXiuQqv@8CzQ-^jN_DOmf%`FMDr@zIQYUDzcUz_rh=%sCFpJ zFSTrA8#KZvkp~dhTzD^@jWP%7Z?Bd1T<$q^@uQ;_qS25W`X52E-wtWBr-|xVtUeUm z5tFA+#pLNKd@Rr{k&jkBR_4;`r+CEZ+>&CD>#NXQO!7<1mry2v- zBY4SQ;}hWH`$X{t8ZdmL51CfS?ldNcT9R7S@jKl-u?-G-y5mtJ1x^)kgLnXpXGQZT zdvCfE4B~S}h+8#zmaTmR+Fk~b8_%aW6i*pfM4zPe#y~dmR!0*ZT6?p(;yzIO9x9K% ztn$1&q4a**D;Lr>mN;F7E~2MskHS4)XOxBIAzxzAcEw0(t)qtz=igL5fT`YV>QjK_ z08{cEkoYatT2+?IoeH|uDyIy-fE(sM$m^s=gFK6BHEMaOF=u=GGK7$SnJUn^RNiV7 zRbz8iqJ7@!LNwYsYkDf)@3Lg-1I#g|OU4GDzrlMyJ@vIa^Mk0(cWNrGg5}tN`A~gA z36@`A4~%D_*uNqx#WVt&P^{5TL$UKsZ^|pn9g#m2J(iC7j>dL@?o}Pp4(I4kF*pZi zvDp*3zp^&ON|*Q9ACSGuWFwN1y(m2$`OV7o#6=z6mK&hO&M@{|)VDt~=rU0Djf_@2 zWyC7?2(0!o)0~J8z+00}hwWj668(tJQ+j~)3Pw%y0cMyq0sAo0D;=5U9+s{%+^DP! zx02FNsOJN4nKl@C4q5l40c0sMlOpa|RyVoJRq*g?t;KK>L#LTgwCRqx!*`N z(YP7AyD$$L-cH({xjtl1oUWh_C5z3)wQ2i02u%qGsYamVQ`WA+3uuI1+OU~ScY)Z_9uu zLaimrVNd`bt+{uhn?9yMT-aweun&s6NwF**VRwlFaO}xOF*`s&SJdzpRm1wJu~}*n z*xqT%j2(o%1-UnIqOAn6`})M=lI#TT`zlKi@m&PNH!F5i})?KD_ICr=Q&HYxC-E1mGyC=MhOh?VOH^fDBAc|3M z1?sJtJ9ij@bstu8E-#mE!aT0cA~tr8gDt89ocMYk%%kTzP?4v81r#9i!OYMON;N?GYmw>*zh?UtRhH$uWvRaGxgED&n zwjk)p9=0AzqOFIl^dB+PV71Qg!xt?FLA<+UORDdvd_qxzmb_CdB|fu03|d*D-3lUH zST?u=nqoOCSM&-k|H&wKvQZhnkm9H>oAuIu!Y67Zpc5gs{mq8`-KaVv#mBVbbkXv; zT$-=A^TR9j2?)Cft#SNF9-r_SjCv7R=CVm?+*^Ac9><3OCv5Trl87+i_` zKb30~VRS9cFT)AvXG>^5b9zH{^V|k{0(}2y%dpv~3#$XpbUKuIvFXNDaP)d7rWT4Q zH+fbB&8?9)Q1vvr-(wvPcn)3SHr2ba4TP+{w}7x;q(&^i$fQ_p9)%*$ zHNHW7>gY?pQoDv#V4h`Kw;Y{O8}eT;m||6M;TXDE$-C-XDEcK?;e2%#+Sb(ske5cz zH0|W&hY)QuRP< zP6oUL${nNS%ut+;w?~F+(J?<$wWV-O_EE375a>iTG*pW%8fzq^P1rZgI0J(fa;m)%fV%+;Db;raQ25#Wtfhx-67?l2#?{(OPXt zL4ChhJy-6)=}x@>S$|1$MR-K|Y@)MH!yva*7D;0y^#f`k-3t~&k6WukF?6GoS^nr! zRA!p8Dtt_|wVZ{_dyFQAi+Jq1I=3TtL#yfK3W}*J37=Bcc~+`=3cj_&oiyMByO{h9 zjXDnkY;py@iLTQ_n`%ih&c^7P-hy`d(y~+T4~~a42Q$^<6exB=nJfoFhu5>pU;t#f zSAo1t=>ehfEF1qADx6~|)v*VyhbE97rF@Bq(QWVAe2;R!iJDbxBk3B=L)MhYAaJrZ zHp~1MjQ__18ldm!fChB>*0~@ zmRNfI2CCab6^LGDxvM)-=H{}@5^nAnLT4XKg<@yJrkRDjMM`0qnb>!*wueq~OyA4P z7rS!WBq`MW@hsck_neK~YNa+2pwn*UA5i@YT}Qireu_#yrrJUtrsaKb4BBHfD|SdB zwX>FL6w1v}jMeo<%NIQj=AUZwVm*HjR8eCLWLO!7nc~WFI0wxeuZU*#i<&zx7DDz> zsQ)KJFP?m7v~;|5t*Vsxe5GxAe^lsaZ7cSN^2JcoLCRHCqL10Lm#2_>nkkah36R;Wa6tCg`;&17o)0csp4b%YZEEaPiX zESFUg$EP{BZYb*`ZKC*iz%yrpV}F^6&5YPy)#Fg!mP*RB?+O=#?R9!uXrCY-3_E$+ z%nL^IIRhPGO(>U%5!9Zm(A9>qDw9S!dwl&0+X~lI(ze2Z1NNVT(P(V6$hyMuD>l8@ zXkuMtpb&DsOw%DkWdS<1Hbpv;d=l@tyvJ{g%yBAHZf0_QevR?+?y;rQo0>}-@f{l% zn`zWsA5Fsllyxgaj4{i-EQ3JnjREsTMPDo`o)y;x;O4+=S26tVs_Ygg-kBNP3Y#r3 zdgtpMQu|hs1B>6UyaZNokW#x0O~q^c6l(mAG6T%RY{{p?^44fGz*jiSrP39c)yAJ- zHEv(8IUD(hM4i5ZSNmD;?G_nkED*;{(AGDy3FP{o4=M8??F%YXPW>%S)1iTjwY-%S zqJ$}s-0mDzRdLaYx9vs{skhP+MpiMEX0-Q%bA!sp0Z7}|&{pc1W|D_9<0EqOvBRfl zd8eb~(W>MU?2z+ z<;aHt@V$zYrT}O#_LOS{klG&-U#%pzkEIMmEQ_1R@(yrz)B&zCy^hZC@L2*)WFL?% zu0r1NW-Wt>ZlZKBiLQ*gj+d>48g}BRUi!iF=u*O@|LP{OwIMYO%IInOUhaqjyb8d)TvyN+sR~tMb1K5;?z* z{mFn%gv>IYRV`<<^PB-a{SkFeacq(^rs&}vl+e5~=b);uNX^5k7UKQ^&pjHAf2XO6 z44$D&yafXFFm@&5TJa?;1?#>}Yl>DC_7Z9^G}T?@iwFzW;^F2F$z8@}(Uwm2#QJG< zSql@%1blGIvaPeSUW7Ns)WdWUTtn&47RW~-_hch@9u9Evb9@Vt{kO@+u)x~qH)PH- znR(ddWVthtyR|V#OkQ|zxfGj`KZUgWt~Tvy$&UXv#(C)UUvb<^wKaB?th&F6Qg+jJ z0Bhmqc{?&Y7`@BSS$x5kh4Ff?;cD9s4=+J!hesoJPv`I0#MTxWn~%K>lRVpW2EP2* z1A^>e9CPes&(-9Y)fCY7e+jVMTa7+A?jGBrxEEG&xpD^ObO(f6z9!?(dfIxde$d}%+AU`PH9d*7JLhw6V=BzYL<;qUebhAqr zcO6*1Wc7Al-~{OCm1xdR2SqsJqrvzGDJhNpcIHVzay_EURHteio2%=mkFTCMb6Tx_ zP-92*fiJpIhdsk+QG7sWqS1k@5vl>ifnR$HN~d}!Dn-Fj*{9xq2kSRjrNxVGe29A) zfEAKC9l5EW$(%iXntxV1DMUr*ZnFk@9;Gr%5VlR+3e$%15uE1%%HG5zo?Gf;;CsBO zZ;8E=Mu%80RJyi5Dffe-A7_=pxgzdUA3{}rQWD7z{i1c~>GWTJhD_*b%fAlFgS zV6m35iN6PNaa3JwFmVHT3zh9-hM(9;H`*ef&T3mAF1TpJI|kLwHQt(rX}y^lphkBa zQtXvkdycnJ%c}{r>xSF!u-YS3epTB03*RCj+w8IB<;{qQM1Jt7$PYHB|A-sus_r;e zY4^9?p_r-6eOPBD{)2=Ckp%IR60btM-A(OqaA^pZ2U;=RLA%(rc3xRw?qSw!VLr6; zgaH)To8Av2w^!8KSk-acy$emUiISPZ_0zh}nsn2~(lFMdAl7mfCXxkR($3XPjGe2Y zlhR*`o_&QLA=0jT=Rn4;tQb5E#0u&HDKAzvpd(I}x9<<-ov3;V`fbc-Z-Jgt!5CBP zGtMKifV;K7T(wR{)7M5#e`ETOII9wAF*e{l0QtUV`lnMKtdP%8xx%RJts(q1$o{Zt zczmhn!rcemXEWLD6W0G?0DnV#cbkI`Zz8(TN6}2aQQ4@x-oiaj5=J^u`N+aimN3sj z%yLtUJUr!MKlwHSfPKu6Y`cZ~z<5hjl_FfcXDZkPRk>0*S8M``#Px6u1Ugpf0q02Ux{$O(q6UjEs^37H zohn;}J_(dp6cp0s5xq{K^9jX95#nqFA7=`{d}qa6dO$r^To2Z>r6S^9cSG{5s#WPd zCA*hCjNDBX&pbPN$U5*mO?N!n*R$(ND~%?mLnwo*cp9dqM|7TDJ1Hf0OJqERrxd>t z1@&x@q=!f58vk9yHp^IwT0WKFbD&?SGNxb3FNxYK9s_Hh$P}tRA?y4U zsHezA#sOyQY{b9NLA4Qy9*bZyjU$;9p*YT&Hf;X_`dyUN*t2GBa{~(9+6V*r2j6;XQsR6YoMrG3~52GeDgso>UvPW zWm>Nsu2Ihi=oG;3O5Vz1nkwi{bPBQt8@6~f(LO&!A+oR3g9*+aG1`M+OApCBaeCUC zYgZuiJ*9@K{J!?lp&4+0og*JcLyVT^Dl|%kY7~6?;-Y>EQ7$l|ia9e=-?`{}Mg1^1 ziO8cEohC)2(_qK1*uyfWgRnIGyZ3UK&Z|oF*tOzG5d06NNqM+~oBFAcFwdAe?X6fg zIS_5Q&a@F$*sxgLO4XqLT=rX>^`i*T_JZnIsAi`~Y2wqlH6UGw?C#N!OB>Eit2d+I zjZJ-Neaker0qVQNUN%0o__Qjz@F#B}s4GQU@? zE@P`}x&>(UPcpML^=&RywEVfUZ1@$y#_2Qxu0{Jb?0cQTitj$64M0!jZB-gr)=M2TkvUhF%CxgFN~||jI8`~avZAOY zcZl^G$DSb1SJf>XQ!vsRCSE~(KVbc;lzX7JLD`}Uj>Uc53WaZ{G=&u<*TfZ2)Bj|N z6l2Cx@ZrdtZ)7gwhrn}D-Y8}yoaaXey&=T;Gjb~8q8S%x8K&|>D&XkZdEV&_aQIUrho9R@E-X+9Bm*9E}Bc_moyP)}+q=U9T!glD8?2|FNJqwCL@$J76 ztJPPTjIry|FF?YbnS^+0hHuz)hJ^nr2@&R!US+h#wUv9&FoQT%YA2OlsEAQ`MGO;fXAWn+DQvRS?9wUR@15Sb&_cwg#T`F-L zP76UFm;O=I6Y#yqnvSmk_21Tfg8RhfAnnI`SL_zgzA&t}wB|&hDqFUxP~8*J;6o1A z-rOAr^(HO zSG|VT>}>`=HelS3oB^iPJich8`(f{!x|HTtmhDBj1C^}2oCZB4b0k*&C z1p})GE!Y1u<(227Rkfv4@WU4)gUOXIIP$qp9kjP4vzVcl!EA!uWlTl(` z!AB}`kTC#k7CEeS48yPif=b;hMIh9geeejaiBnQXM;9x0loLXD4&Br^sll7N3v^y*W(b%*6c(XZ z=!Ira$n=cVk2rlFKNee!s!lQHODilU*wJXWyH$(IkO5kS!;!VUX*OC>+DC-9Ldn~! zmWfY$u0&pqA*T1U`G7(ZBOh1A$`5x|oyVf+O?B(xD+WB8^%Y|sD%IC0y9mK#SfzR+ z_bkO-T$a>zqM+1osnv%(`M?czDjI*S;W}JI$ke^&JaFwGTZwk-=m;YxJ_p_@OUaBe z+4do4fc6LN*6_X(Gu4woI7toX6n&UC{-2O{p;ECp)yhlU4oojImQmH8S;a&s_;79D z*8bHu_&PRha1&kwsa59{zQ-IH|6%AeEr#YU=PkAgvZpGB(d9JzSk!;e-epXCIMTys zEf+%CiPGVXncj#)ML1SuO*DT;2Rc-BF1iS0HTd)B1zoj8hzI1ko^Ay5I#V{j)>{KN z^?~!1LCD}V+9GHxW>;2idi92x(k`fWjcNe;1Z^+4enjqhiZ9-nv3C&n2Ip%P={U<& z20@%=l_Ms9d}2deU6*SQB!kZ|YoU$z6U;H)5)qj=sT7p-w^_RW?CJOa?s*| zwfl$ARxeg=Nd>p%T~X*N#d_pu-g>>j_%7AaX`jnJGEsusu43(Dz0pN)ajsVlMB?y) zr!V@}2ikvNEVGCECh$$lZ2F#(vij93&~B^vVi{wNgO{TsKbS^k+B*q3OO1wbn2KMK zrdjzjrXr*HvXvslmaFoLM%gzlJ^|Niqt=R&Jj}keho#ltnUMx4EH3ZjyP+EMrKtJx z@iS{mNrsY;O(M?-aoV#W(puf8;^Dbz`8!p$CNA}$p4vSBL)K zi&IUzH%#FZY4q~@vCf$dXZE$M=P(LT6W>Za5mmiS=F6{*mLi5C_XMRSvTJ+VxH)nc zC`+OBw0$CK8yL!~s=ehSk7*&tCqa>ToLb%z8EKzx{gQgC>FDARJ8QqKQR7{e2bYg0 z@j2J6sP!F2mpE6*uj}6oMQ&~^12I+5m$hYV1fhl)d*dTrM-X;ac7fR=W(w9V3A(AY zNHx8Tvtf-Z+k^Tx)qc|^$k;`;-x~@BgV?YXJI?q5YIT&6tnUEka%u2*)TqmjTk!z+ zE{TjC(^GD*JD?HwQ&Q#kr9hh6b{@=1{+oVAqbdEB=dKvkzZDx_&qfWN>w49*2CCgj zI?(dQ*ux3e!G%6Pp$N}IPnx+;nq0{9(-JX3xdRA0<(bKKF zeY>On|ENZjS7`ZG<_Zwsth9r0LYA{DgjP3Htwq3t6|C;u{h4BtskLKz;xm#=L5oB*_ zvW53y*>t<=IN4=r=VVyraE$kQE)ZaUaI^j7$3|RI#^&?fX!H5+eH}mJE{N%V6?XTd z_hp_mb}+863|&{xEa_N;gctm{8*mb5W#?E;(* zv%FTByV|(t7C#8}dNrb^qn}(elR!IK(H6%dM}Ce&R!@kNN-{{v2hlO5lUO^7d672d z6R8h9u%rDjpoPcValm`dWG`Hzkc$ImPSDEMfacwz}b84qI zQh0=g5%he=uke#*oT80A2yn!h;w|^a36%a-55ue z^(B^WnO-2fx_G06E}mN*azBXORRZW{xi!k%hz31GiA8q@c`tt!Lj7VYL@(E}#{M1^ znxPB@9>$)AWP|NOX?`@oVC$)j??^9z$Tuq`i&um!c?;1Mo@C0v*oMi2*5sogE;Vk` zc3dB3B@fLUv$wiQ$9SW&sNac6&Z$aw^qviOEjvSP>r5SJW1S9kTNSwgCViQT93zLy zWs#*`;QASh*~kXuVQXexcSGGLtIpD1$FKZ;H^?Z+cD|wI(@fgbct90d z5<44KhP-2q`PwlsH-R#*S4GA~MtaI(oGGp^F0E@xyMX7diVWB0Sld!0j8D~YE-qJE z20sT1?rjWStU{T=_X6Adm8f*t-=ZA_QJ**RfHKUlXbmicHc`rHvb?YH@A|hI0?#!2V6s2=F!}4aSH>YhiCgBvO z8F?x29Fw;m#8;>eF76`np(Y3No~wKf`v}FCXnTSC*~)o5}_fuVzxMT=z29LHr+#8=%|&d=&Z`ZMDc`msC~KX-n;w zTaf*Pth_j%!^g&PsQdUxI+{&cbEcm`d7n`#g|^0&L^HlKE0MLZuIJH>(`PnRPs2mh z)p%E=DQl^CN@OK2`L%SU#XWjVoVIl=OrU`0-_GAB4aCpaS~I5Q_W zDseoRbrrn-iRu6Rge&&d&+f2--S>Jn$xCC;i#oL!e#RhKxYE^%&M;=H=V z>bk`Fb%`}~i3{oyYwHs0>Jsbg5*OAbE~-mhT$i|{E^%pH;JnGhC9bMV zTwRyArY>s)yk+J#-4@hfxJ!Z&M*g$$l6;sYf-7|jfbeR9ul3Nl`L*$j$xivqB+L*Vvg~j z8inMR1n(Jip}e~k2f;^nMa|M>MB+-DDStC@PHnCFDP@6yJ;uJlg=q zg87g9iaL!h`ilDNpuJYvJdO=A^$vn9?=3r{yuzaue=l+-7{!}om2AM?4SWwb7%PPP zj>sElRDto3e|4yYy!W%(!i93zeHVy#)?0PyZ{=MNJ)`H**6m39Va|?d+2IRP`3htW*t8p%i$p_za~Up&AEkAvb5jksE zT`(TdYpV95cwf|Kk_6%E38VfKX1X*QsbdE!xp@rhhtX9yz&|F7VPd>3e4|O~)YA8(jY_Ga0sP`i35)0qf+{k0ZtyQAuDmWw2D-7j`HnP!F;=?(O>hjR}A z>v61Tu?Njph?P{fY6hHGcII+$;}tJ6`^Al?Rj=s5{p7M&3PM|GpTxUsLm`%Z&-L~$+8xsf~r zTFb`jIvTlflGWO8tcQ9wQw=+1O8P`(J@WTA-V+ARgr@J}hp9%Z8WQvQ@1ViD7)pF$ zw!Q>VJg^ImK7_&;>or-)e&e!gr_Y?$T-`9eslK^>)`YCZiDVKR!Y!+?E&K|0-SJsW zghNTqnj>#ne-`=fjg(Yk*G>2QH4y1`WrGM{k4-I|MF(KlTjJP(md{7~EHU|Xh=MP= zXan`9sQY2f7ISrr(0zV1)CKAzg>LGCv6i_+)kyA9>l#tm&y#gzCGvnevJ#yDJ3Z>Cxai7V_O8&;<1$a|8t}Za$orI4 z1LqEC6w}q96UbwtNd+!KTc5DLgb}aSUkl{s?7GN&&vIwr)3WRn;*_vnNV9g^9V5)O z+AWN>WN&iXb4RxGMVnv<$yLBjU&*5(hR4XOG@ zP(Bg?PHqeESHxNh`B+5wONQU~hz$Ztug64mH|u?5sk^75jB7Gw+@P(DK6XO*mm-p@ zGv=JAbEMd>L?n%wGJY2IktRbV;2x@l7V zLA(Mgv_D%vwsMuTJ}ZQ!=3fD2R&W~Jykl;a{Uf%@5~ za9)(P!f0c{9O|c^N4%D0%(+KDuPTebE+U!OUpU~{qpMd$**{1JCY<(h(U04YG2TD& zUDrgJONvRJjB@5>%(+Ziu9Qt3@W!bPvMNjzQAeu###yH+$cH1IiSjOq8U>#dQH2vC)t|0@Z)j>xHIuJc8s%)F za?m31=)&etit-NCR;OgRH!9~+DZ@k~`3q6j&5GgpRAXa3g2f6WTNbfwR`rsacq=06 z)i1J0<@5(eIXyGx?5c7kE81@qx_(fVZ@m7ZsPN8xWho7f6DCe*uAL-hJ4I%1MC6lF zSwSM1)hQWZI)zlwDVaDXmDLH!1d@|wG8@S$GMPkjs!Vo3a+*wTfaG+U?1*H8Om;$Y zhD>gVWTQ-Ogk+OUZj5BJOm2eYOqtvi$yqYF8IrSQa&si-$mAAC&Xvh6kvvu=w?gtb zncN!5<7ILiBu|jZZIL`tCbvU!o=k3!WQ$C8MsmJP?ttV1ne2k(Niw-3k_%;WCnOii zH4J70G2X*%QgrWO6qom&@etNUo5{ zJ&;@}lf95UT_*QL@(h{W3&}HOa&IKhlF5CLJX~-CXOudu6f`$@^q-G?MqrWEGMR$mAF#AC$?lNIoQ! zwa z$=76ZI+Cx;WCN0K$m9$p-;~KlB;S(BCM4gM$z~+qk;$1zzAKZnkbF-jXCwK(OwK{_ z1DTwQcmFKbOgt7IO&%}#Lt_WpYcJhW7g@h-$=|eV!x46 zFeF&Cq#le7LJVwb;V%pi*&Bg-li2CP4;Un}lc`!N1%m`7i8%%dN)k^D5|kuX7$mZj zwE~Mlf|7*AAVEpOVvwLDVKGQhl9~mB1SP3mFi2368U}*|C8=dFNI<(J0>%iWh%1H& zq=+d-2&9N71_-2xCB_G&h$Dsvq=+F#2c(GKRU$<#eYHrDTCYJWIk68Fa;;2KDc8v) z6?45zQaLxsBo%a{Oj1cV$s`qpp@EoDSr{59Nrho(pd^)sp#e$Jb{HBcNu^XVU8YoGnVQ4@SG1NO|VQ8Qvm4=}q zyTe4;To@ZfntsRNAkriTMhB55IWRnkGzo(7L8M6%3=kqsqF{s&X_Dnhq_byJp-+hv z@qSvQi1RZdMSPzXDdPH^ND1`?Bs0GY8V(ONu^+5 zpd=N8fq{}#4h9BFQb8CPC`lz@V4x%wg@J*RR2BvXN>X7M7$`}lVPHT~v>FBmN>XVU z7$`}lVPK#nm4<{7WS0_dw)PY7dd>3DkUn+<+ms&wyNzhU}aHna*lPwqPhanu}xGrAh1S5I~i@H zYqvWP8@7q+;f2~2sJ2UlJtQ{LCAMZGy8*Sa7ZR4}iKOy2(L71wtWItV?S;HeHBwsp z!nD@k(+jni7iw=W)ILCMhJUzh1%B(wVxMif1ozUzt-jITv1JUE-dhd?VyiY$ArM<@l(F!1egiTf(|y}PKyKs3GbaNwo#(+oZmW4_ zvhYK^Py@YChkBs~0VREw@m%Q^KG+MD>xIhmLgfQRXsB-KE!} z&&E-6>rxKQCa~zxA5-rO-ai@9WmV4q>5Kemi)>@=xr6=xmPuv-v zxHAbyGuJlsca|saY){-OPuw|#+p}%?&h^Bd=ZRbGi94Tg@iA&y+L+R^#uImeCvL4L zZk;D?eT0)E0nJrp3Vk+k)aSx>;x8h6eC&1by_j(E5yXMJlyJ04l6IRdQY33f{F7dt z<_Gj2AzLn^|J_^T<=B5#dOKZCxP3HEjsy{3k^CUeQv3f)aacVPSJZYDZfx3#mpTZoQUagwf0ecVcTTFbSw zoZETZRlC2I|)y##7wefXydzxZeS~Pt<>r6 z*2;9$=^nz<>eI7M_Y!`P#(UfCeMC37{dD&eU9P5U(~ce>e4fU8%l9DB<+q>iA)+g2 zKi$JbM{C@6+QuV9N2}g;(mhIaL)uUG7}3$nnA^v~^zr0zPuvrpxc_ST>;&$Sc(JmC*(g}+>PSmXE$L{riVO)LK8MWUts1y_9> z{^cdY(@ulLd(9bMCYq6&CcO_k>hwx$G!D65C48oKao}Ggd};e+dYx!!|HP%M4D*6F zh=z7jGSS5B<;`~D-y%Hizhr6;drXSHU$wkVbQP`8IojkMqM^N+Ol76pnJ({Lq8*)q z*0hhtzt>v59QgMMPkTL?^z5k52ShWb6`J(=&}4(CT0W%z&D5?&K8^o~@U(xFNxqmJ zeB4g_CxjoT`Fr)tPl@JmP2<%sKO>qWTA^u0XP>uLCx_0yAUy4+Nu9~Lf@7@u(i8WU zC+=%c+&6@yJ-jyL`_>cpohR;lPuvfLqus+cJgs;>5z5KwxL_<5U zQvP(A9KQ2EqM`lROf;?d0XX^0I&k;_IMGDn=vK;d$R|!`&>n9l`5ZJ@m?skTt^!n(rcN3z`)UHN8jo*~;4Z5t1N`0BwVw`rRy(dr(3lXzct}!w!+_GZ`%;fEKQS9XWM$>w)4bo?}_V7 zxY=#Xw}U6HizjYJPuxy~o1^7RZ_`%nduO7Zn}OD0-@6e0SdH&4Qrr(Y+P5pw9H(j0 z<#W(ez$hwcW)L6qM4^@%pTo*G54|bvo~RJWFws}K<+D$ z3*tOwJ6b&Z3FJv0$o>Mk&;xm(H!}1_4)8`EB#?_dyr%b?Yh3fhG(6zHX%yo=g}9wN}<E(U)a3$%yO7Oi*pt7TlF@=&*0pIm@_-18P#rzGC?8EV|bP^w%rs*2nunQ zgKLz$Gn!^FD+GTU zZ8ZP!ty4&eEQ(q;g+niOZY1f2q>0sZf*bANJ5eCTSsJcE$GCH}H*%6Uvfdkcj6jOB zJZ;E1*&8{<8#&b*IZYtNSt2f{V-_*pjdZk8gFuRNN1Ugljb;d>IC;d8X9)|jW)Y17 zDb60Xfou{;ar%fOGxW&jcA;kqv^cTEc{^%0%Nse{8#%`tIaeUXiK#Z^Jk}d|oHz1# zZ{!IADNby)A?JzS$a&t#7H{NyffOgk+K_XBH}WKJ+bKvN!S+Z{(@o$Yla4&gHcs=V{)^<=)5@-pG{#Db5A9 zA?NAd$TPf=XL=*g5=e0_u?;!T_C~JqMxNu1JXavaxkxT&8@=T`HpF<$Za(&{wnzePz4QSH;n-*7E8&y46}<(=PP2 zadfMaTo*^TD#`WjLf_CX^o{L8-_$Pj&Fwj}Kh!St!|g&p(k}F)?Lt4+F7%TEEp96CnTBH~ z{8VP-Vln=9;5#@^XGX`q0X*Z4d{!VYiH~{?S)a>{bjbRAW^_!}7rc=#3Z%H%!SzZb zbd2XqZlq(@_Od{V+aH{#qyDc5q`3dVkyN_eZL`|y)pns@bE6&dzV1en6plT`H`;}M zvt8)7+-Qf)Z@ZBs^ZBCfEX}>+MmzYv>qcha`<@%^;QPKCnW3dWaHAc3KXfBAwB1MT zLVuhY9qSvPxRDNdKXoHB=;5=>XoqEf?nXPL_`;1ODPlGI(v5WR{7N9jy{vd&j&@CC zpU&p~_v^N)WKAuqZ`!6p95!Cgw{256r2DRIDu;C6w@nq3?uWK19Mb*RHkCuVpW3F1 zN%wQx6b|WrX`9L+-LGv^#iaYKZ3>5Uzqd{0knWGRsbbRo**1kky1&|{a!B`g+f*^> z{%M=SA>F@iQ#qvjuWhQBbXf^HpV3~A0w2~El|woaZKL(FV$x-|U5-O{$+oE+(sgK? zDkj|qZBsa;>)1AxL%L3FQ^lm)ux$#5bQ`rz<&bXUwy9#$ZPGS{L%L1drgBKPS=&@G z={9eh!Xe!jZBsd<+p=w{m~>mUP2rGk>$a&J(rwc=RZO~V+oo_xw_V#*4(YaUn<^$< z=e8*v((TYTl|#BNZBxah+fh)kyd}}9x7B}wYY_L`I&h0{X73izt z>uZ|5o+oCo*4n3=K#M#5@p&nsqq%8TCu@e;T~LXe{VuB5>5Co$E$;Pupm!B$ajQR$ zJ||uNo&qiI^n0Lp6KHXx-vhn7K#P0)9_T#;THN0EK=%@8ac4h{roD|bMNO?a`kt97 z9D3PHpvB#OPyTynrf~4zN1#P4fH;2#y0<`!2ml`FeFa+F`H!RND|5`c_H&~hYq0$V zQp5&`^IeqAw~s)J$N(Pbz5*@c0eGPM3ABg+;DJ6spvC=v4|IQl7PtRB&<6^%xbyFU z4h34=^pB(EDRIlU3=rrCT%O2*K1iS+jH4au`SfE7&1kT$b#V~;sF%UR1L+uU|Xb}m4qaA!p z1X9F8;K&T}4i{(<5y1mJLZC%l1c~mAwIls&5vT22#7X)Vbxs}e1Ovypx{-p1h?QXT z$m-Ms6jA*%%ri;_wTPVXf1n;Es6`9~kJ^?AG^?%og6pvBa)A~x7C3K*x2o_)R(c~x z3#5qH&_?N1-pDcD$gu(`Vn4J|`Z#ao;oit21X4tiXruHay^%+GBdY~c#H5g=?~eW; z<1a6OJ;(NkYXn+Er0_te1X{$Rh@le?3<`;s*6rY1=Z%~okZ;9( z<$`osCkmv9Ouh{qMxfs}H8ZX3(AZ>w z{=gGGMW8=4XxS1D&oR{-In5h6T_8X5D80cOIl~*-D3Bk=OLyqB$s5@$ke|ePE=ae+ znF1+dV{qGYAZH1rh={?FG+HeYe64xzY=QnfED)sAkZQ*hX?v3ffn&OJkSdTT14saKra$#5v#)ky;z`s@zmfFffjK)Ja{h^ zXtwTempz^=sM%`MrgrSBogygMinC3MQw4>HFA}d$%+i**k&gA$X#y!?k;HjA_8FGD z(GI>V1X9EtS^Wb@hH}Xz_+}wlbUEavM1(Ka>7%MCl zK3wb;MLR`~Z+-Vz^2_&0wn>|p+*zkO2v}1I5!Hss<{)=v;V}y9gjdbvQSs;CM@QOfo_R!X= z-pJPkat9BdZ+Ii$638wdJm2<4z9W!3dhmSL8~L6W%zNAiH_+{5&&Keo34p=O5n4KLv6(51xN{BmWl2-932z5!mnX0$^GTe#5U9Xi;`jdbwb zS|EGJYv!=6ZM>1&3go^XJh$^kZZDAgdGPG)jod*X_xIr0#T&V!K=$$Axsx|?XMybN z!E+aHWLJUg=fSg^H?q4x9^k>Vhc|Lpf$ZAGin%LKjz1(OA-@OIWM<4qLc+MG5ffY4xW7l(nkmV1TrVC1BbQ_@J99*$b&t29_Wn>1@aINo&&s*2MOdr z51u*R$b$v)P!FDmcq0c2Uk8#z=U3p{uhdn1Q=BM%eELXXl*yphAbks}1M$fNX;-pEpK1}j#D5L1bTQJ?U)T5of+xag`Aoh9ovPR?v0!wkRwRez431! z{LAXJmH1zr>kQ`OUyOI7pcv^eMc=KH185m`9pwwx@G z}g&GS@&JluolGJ!n819@8J($m{f%e-7r&2ZVI(V9lDaF^lG#Y%y6dJ%)x ze&KY1cG`#I?B>~SDGXA}yGkI_wC6yc3Pls;T2xLthIUkb7yuk(T(j7e43S=tI(~J+gM(ezh>)l94=@$y*cvtC; zliU{xbgc_bJ2LY7SmbrZn09ey3fh%%P+a1saL9hCK-RgWA->UBA{q&^I^lpP#!WSL zUY42C^i++$T%adpDo66SYJG*Em>8#U%+s#)MqcHOyxJRijX)k9my>LdT0hcYEDpi7 zf@+eB%5i7!I)Sctp<5~AdO>xJi;67m0wx{l|8)G5?WJ1yhRpP2cbqxGT zyPLd`H+v&*@kZWCNEyLmJK;5HR_*W_w+W8Us1Y%rb-RnBqu<>jI8Ju8O^oB6-pIQI za!Q=1qx8E4a%vnopDdu0b?W#Ycj*qE_X^~+I8TQ*@AF39??yUGe?TCo$4hr09~8)j zI5OSaStlnS5>zwdRBiO~hci<-eB>i;$sBcf)Qu!*9DJV<=*GD0j^6mJ8<~Oca{}EI z=SyhvFKh8H@_xd%;5>^M(qp&0TFH_}o1n*uq<#WQMcSv#x$yp@^C zVX5$?BfjllQg#-DaKpyXb z{8%7Qh$A!f+)o7h#5md^!KVT_FOFNsnmFsK0enI;8ndAQ#5Va3H@INFUApAdqRg zAh{i@m>&f?Z4GHwvU=wKlR&28vO17I3uM}y$btMtAk*d=4&<)_xyYmR-@TFl3S^p2 z9i{*0jm%2Y-i{B?z#zMdIV;^_lq-0L1POs&O!e=r{>dF=^H&eFFtu{}u8eNOY{6wo zT#FfcRkB^^4g$S2&U+ywij7elcq2OsV# zy^*^KdM)vha_7ljn<8nr`l-LQ&0|a`N3muz5^mij2p7TI~Jja7)D3Is6kaYS$ zp0c#olml9)ps_CY#rYsNg+uNffjp0-q46!NlbId1vSvFtGnJ!^Lo%bOg<9E>9%v}} zcsD=2pB!qC@p?EU8YIxG+gaE@FX>KHyL35v0%9x&+ z(x$T3%ME^1>rr;BPBYw;jyg5EkyNKvBx`b0IrujVD=1VjC4vY+x4^v0(4L_wxUqvNN-r8=UO_eV>=-8SeSaJ@?E#-+O0v%I;)F^)3Hn z-pw?(G-x=>?CE3PT~d9^BWO4~rdF4lTN(11WA^-yIXBnb$`F4Zd+spJx&IiG`R0~} zZ7eW*`WTai)wevtm@M+w$}mG0n_C)kT4MJ6k8xRQZe@tSj6H8Njmv)=3zk>k@(7w; z7E`Mg{#wa5=_8(l{jd6#|1s}Ynp+w)yxi>RW8ST*zU2`#ydtJntIe$p`K&Q}{>PkK zYi?zTe*?>U!32q;BGtcl#Krn|*uU;`Sz5)yQlk&WpF1TNxC+ zl|6Sw_n8!>r^ZqDW4E*SJtps{`>{LBo`xRW#-8{3hZx=6>uQM{co_GmN-{ zyVKml(C<6h^M1ECa^!4@n53S2Efo>}t|PZP!X4JTqg%?8v-zAu#8Gfpw5QuMLmv0A z_XBPo?f4U*CE^-l-^<>%>+QxqLe}>kxz!P}zCXHUwOKz9?dkT+khRU;54w5GTf*PS zH~bZu=1{`$Cg2A-!b6@2OKTY6A&&5{C&IECMtGPb?Dj<9{>$%?41M0s{*QS4`S0aa z>;DM*@A3HSU)E`9)?^R+KkE7)@#*fP?ERQe@5k7?o$F2GD`V{AdoFvq^)75(~sCt~($KFqxVjH~o*U0-B_I}EZEi++J)m}X7 z+w(d0eAs@Ef00{05!==4(bHmdb}IodO_ zH-=-`f#_aDwm8CZ`IRHLG;HftZt-k%#&llb7M2kgL=htVxJwNyD`Gs%KFWK`YAN~Bwx98Ws zJ-_ko`7L|C9NkZvThZ5Wm$SyT@Xz@!>38PVhP~)}vnOq5B^K|MjbS@KRNuO4%ZMw@ zAI&WdJ^YD155%a%&*s*K?fhc)^r^(J)wli+C4MuvH1zNf_I$;pMAS9kpT0f+V$WBj zV=m%36>%-|w>hSvpZ}OW4KZsc;@ofEYtdUb#EfUp_R*e(V^#ut9`xav$eyo9d(wy- zegTuj-iM;S4Sh|nK5o=FrLgB4(J>85)iK93Y`w18(-8A0^VTW)6maj z%>6WsXe0J~Gg_tjRr`4?d%hLzNf|9>??mrWva#9Q(AVSG^X=%k22Gpz_H63gvzc$t zRQ5dVqn~NMJp;Zy(|vnpu;)8I`q|vKXQpq@EZ?3%_I#K6nax+J?l=ABSDk&?HS%u3 z-tR?gV7OP%l0Dy#_B8aMm2c0GZ_n1gJ&$M44}A2qjc?Dk?D?UOnC*Ofw)gF6`S$F< zo*%jWY;&Z$8Yi&#$F6s^*PtDJdv;>aPu!SC>_KPt{?zrB9vH5iy0GVGK0Ld!=jT2= zyRqjN(VldiroUC^UgJmHOYd%OWjJ1+X!fM|hHK-K*!#=q-WaqfV$ZLlJ?B?F78JAR z*FHQ;*z=ocPwH#br|=Zto~33_gHlu3^V{gH8!{^M?OD#A-}#7H;oGy4J-?5RSXdohnf#96}(_WseQ_e`_5VI*dmdtvarggt*U^?U;BZj@&|e6!GL`uDOLF(|Kl38g+RiPsGT~H+vi6E@97~qZKrq&n@-sxy-lc za^IepvF9&7`nkfl=l^_ruJrABIeY#Z-A}_YY!!R{7VT*mqbq#JTy6F=#9YIkzejKV zKi*5SmRtQ1-HNh1!t=5#t8Zoa47$qPGeZtnn?0*J60T$KKdb9|)Ujecd;ewfKEf}T zui;jIN4GNc{aSN;gXeW-&uX&Vz~28v_kg_Vh$Y90h-1+8)wiG{mZ8N)a|=V?Z(z@V zO}(i)(<1JQZK}SdVa{x3@3`80rrCu555HT9wj=j2BC_7XEj)k0%|a_$+`jkL=wM_L`fxmGSS79--CE+$!F*t?0X@q)L^yaNSaUdzua2J9tsw zUf#wn6HHrPjFwUR*R3`3-fs3bXuX3y6MgpLwi} zz6E_d)X?J2>RX6+#2LX|HS)fjy_0Lu|6SF$sHXq-RNunT|9flXeII+{4T4qoI796F zYvla^d)JAMZMa)uvu9l&o)5BTy=YH5YDZo9Jj9;$qdg6C@L}IEce7`M=$M9cz(;(0 z?(yyUD0?0iz4iH3bAOCI8~X6v%brKOo^5z0v_wop+{bI={RDd-<1_Y?HS&Iny&L(A z{dA4I_p$e}K4b5%k@qv~-Pny??OmK_&7KRYj`nlxd7O`!&zn6BF<&ry8s@}{?AgS} z)?YGv8n*s2dp7kE^MKjY5c3tYry-+P*|S;n)(tUVGkY3h9%Ro{A2DAydm3UMV$Uka zLcvnw|slP?c4J(dj@>;^Bv!w@A~$9&$s9M?3o_jPx=%xJO%uK zy)&Y{4de7-^>L#<-9GZ|`7wJokKVdr>_74C`KfQu&wP7+&Yqdk{WN^Ce_{4C==mjk zRv9Nl?qB)#{MxtYH)c;mKfg758v6MiduI7i>3iRvKbSoY{rr(VgFd$YlW)(T&7Ov> z|H7WxKDPd=Z_nS%o`$Xe&YmrNZ2b@4o`0G>4O{< zaAZhh&nmOdFqZm`fdfdv@~e+1c!A=w}zRr=g!+*|UoemAaWd4O>5jJ-bH7G;F|LxzFr^p zKFOzd-x_)MWABsQ*wuc^zrSzKvwV9F@a=gvd!FK>p96h+4)X0e*th2p_Uz%KpF@3n zp5xndm~YQ>+4EE%{T%MwbA)ftk-j}gvFB;g{WKiS&STHhqdgZ?-Sb(uIFJ$lDZtQCJ>Wh4Pj`Qt#v2V{D_B_)^KXZM1 z=K1y<@7ptfZNs2kIeVWS?H$>hi0APY<`xEBD$Sk-U8b?;!028W zJg2kgARnGH*>kWD&spp_B---`8eC#-VbEZ<+0&5OrR-T{#v456u;kTEMV_pChx`Qf7Ewj7Mf!l`n!ld&o#wOs2X>%*_+}T zyjQY!m2WN@euZ>7dsg|TkHK>ldsg{2j=^&ydscbsXYjm%J*zzZFnDfa&nnMe44zxq z)ARg6{z_j{;dRhQaer_N;Q|VDP+)J*ymh44!xU_Pmchhr4sZJ#Ue3 zPDXqS>wfkgQJr`ASRD1&J0CE&G8`Xlb8ifu53=XT>Ut7&gnEd*M^)!tO}`)JR_E2Q z)oybuLk^Fadu8z4!=9t7>q%6$kD9#=aUWyPDk>U0_p;~trXEC{kv(qqG{k&@J;(Tn z`J~y?5c4Vayue4yr_G**nETjstdE%c&7Ovs&#>o(rkIBP?pgM}s5E@n%$Z;mPajLzG^pS7Rk9~W7;@k66_M8~qPq}`M zc;m%qW>3Qie$JkS(J>A8+P+}VNztA(8x7Y;Uz)uQJ@|?}C!69L?hJg*-bK;ghPdBU zA2;d~{9E=cj*e+~KJ=YAreW*fn>`INe>QKObdBogFTOp0HG3NR`J1_)QRmpnadmTX zKuMq%(j+W&@bb#5@XSs+bL7ripnp%z&83z)Tmj5zGuRkA>M>%*HS? z#XJsXmY7Xo2E}X&Gh57NFk6V33bUn{X)s%f8GsoQGaY7YF*9HuFJ^O?ZN$uk*;dRf znC-+2!fY>QHcU&*7BD-A*%IanVzz?WQOpp`PGYu(*;&lvVRjL-4a}}$wuRYE%yuxl zi`gFLiDFtXPZF~O%#+1D0p=-Uc7)kO%uX;*6|*zU)5Poo^K>!0!aPIFZZLa_*&Svt zF;9fqTg;PSo+;+ZF#Cvk3e3J@_JG+>%u`|Z7xOfjXNh?_%mHGa0rPAzd%_$jW-pk7 z#Ow`ou$X7U93o~Pm_x4uW}} zn1f-C7IO&9^TiwrbBvhhz`Q`rVKB#vc`nQg#T*XvA~8q694F>Tm=}vV3TBR&=fTVs zb2Q96G0%rNUd%Bt^ToUXW`USvVNMY9LYNc9ya;BYnB!nh67yo1lf}$|StMpI%wjR~ zV3vqE9_AD=^I?{XSpajYm=j=@i8&EwxtN78E5w`xvr^2-FsF%G1arEW#V}`xSpsvW zm{VZR60;QMC1Os6Ia|y!n3sxK4s(u}6)@+DSqXEVnA2d+7jrty1!B&CxlqiRFc*nA z3+7@mFM+v4%-JxPig_u_Wn#{Oxm?V-FfS8x-n_Ut9D-}FP@FILKg9)tD-{!7CJ(2(DIKD!4{*nc!N*<$_l#UM6^z;tIj575^u=PI0B+dd15HuTfkjc&*|U zg4Zdo7Tln?M(}#YwSpTJuN1sN@hZVhidPG6R$M2zMRC30jf&R@ZdJTi@FvCU1aDT{ zAb5-7^@7_JHwxaWc!S_}#Z7`c6gLarrnp7$cEuY7?@-(-xKr^a!8;Xi7Q9RG7Qwp} zw+Zf2yjAcX#qEOkD((=xPw_Uv`xS2&d_eIIL0fUB;Dd^H3O=NGm*B&ScMI-T+$H#k z;yr?U6z>&$RPjE+#}w}u+^hJ2;Nyz6;1h}u3O=d$kl<5_4+}o6xLa_a;v<6l754}} zqxh)cvx<)iKBu@>@Oj0@1z%8nLhwb!Ck0WDZVWDw&DT7!-}s6zN7f6;Jb>i3BIRzQ1E@l z*9AXNJS6y`;v0e=DZVNAvEo~TpD4a9_^IMy!Os-m5&T^7UBNFD-xK^&@qNLs6h9FB zTJb}{ZxlZg{8sT}!S5755&T~9Q^6k;KNI{>@pHkS6u%JsS@BE3UlhL*{8jO5!QT|W z5&T{8TfsjRzZ3jZ@q59)6n_x>Tk%K1e-wWb{8#a3!MHrWrkMAOU@gU81#2t*CK#{y zyI_LiAA*UBe+nik{w0{K__tt+;y;3Q6#o^hs~A^{KY!~f;=QHxaa>;!7i@$L6ypVt zQcMtRsF)~tv|^IrF^b88jTBP^k5#NA*jTZy;Bkue1e++<7i_B7K(LwOQG%(84F%H_ zj}{Cl9wV5p*hnx#@mRs;ij4&`6^|3lQfwj^RBS4kt=LSkg<`5;OT{$7R*C_^kYc)E zYsCz~;}x3=wo%L!Y^#_h*iJDh*j_PP&{Aw6*g>(S;0cPY1Uo8*1Uo6V7VNBeykHl_ zHiBIh+X{A5Y$w=VvAy7lik9F>iX8+`Ry;xQ6vd8$Jrp|$o~qbc@HE9Pf~PBX6+A<+ zn_y4H?t;A(PZaE}c#`0miYE*9Q9MPkuVN3ueu}3G_E$Vj@GQmC1qUdeA$Yc8Pr-qT zy#xm-_7)thc&6YG#Xf>V75fUFqu5Vym|}mya~01L9IiM(aD?L7f+H0N3XW17BzT_U zV8PLfLj=!P94a_Q@f^Vm6o(0pRXkVlLdD^N7b%Vq9H%%^@M6VLf;o!k3Faz}7R*yT zUvRwQ7{PqS3j_-k#|lnRyijnW;zfdmisJ+)DPAl%SusbjNHJHiSTRqqL~*>}6vceO zQpEznsfrT>%M>RHmMaztRwzyqtW=yVI8CugaJpi#;0(nQ!I_Fv1ZOFh3SOc(RdBXq znc$_0<$`k*D+K2%RtnBjoF+J5ak}6F#TkMN6=w=AQk*5YSn(3UC5p2JmnvQ=xJ+@5 z;Bv*ef|n`I6I`Jf>$g4PjH>$O2PGtmkVB_xJvL^#VZ7_Q(P^$L2-@X^@?i+H!5B!c!T0qf}0et z7Tm13PH>CjdchkNuMym;c&*?~iq{F=thhn&7RBoYw<&HEyjAfA!R?Bh1a~NI7Q9Vy zi{R~wHwxaNxK(hc;!T2gD&8!3m*OpgcPnla+@*M{;5~}l1@BedA$XtSZG!hJ-Y)on z;vIsv;!eQ_74H;$NbxSghZXM@+^x7v@Das(1otT3EBL75eS(iE-Y>XU@d3fd6>Y&M z6dx3PQt=_drxYI+d|Gk0;6BAi1otcM5qw7RQNd>w9}|2|aj)R>ijNDvp!kH~i;7PQ zzNGk+;LD0n3m#D1C-{oue!*82pAmdb@maxxiq8qYuK2v*A;lL2-%xx}@J+>+1m9A8 zS@3Pe1A>PYUlDvq@m0Zh6<-s4Pw}AO`--m%exP_r@I%En1V2)IQ}AQOw*)^?d|U8S z#lwQ1DZV54x#GKmUnssO_@(0ef?p|qAo#W7hl1ZIekAy<;>UvDDSjgOz2c{WKPY}C z_@m-W0 zM6teLQ^f{?%@mIkOjT?sn5KBNU_kL0!F0t&f*Fd(3N}}4ESRZyoM4t>6TzTjQ^9P- zW`ZpgQw3WprU|xE3TibaCc6^jLD zD3%D$RGcC>OR-e&62+;4vw_KR^>gFmlXG&*r;aO+OO9&*O31+oB*z^EGX-X0WoaI; zA+RoES*P++tT@`KFY63E#=-J#z(y{T^Rd7rw4OQ<&{*rHP8?STJPw#hb+DVjP9~ds z(^OlPQwN%9Rr$CaP^v@J?KFofK>?-8PTfK2Alh^#Z8`%$Nma_Gn*(Xn)G9OFiZ`95 zt)>;CDyVMLU}tN^bm~(J1@2Ny^`aK7w4#tAhZu?qCzJqM1Cn!!DhpZF<3R~Im|Mwl zZP=@1Ja@V+dzFkYWNHUWgcn6_&o!l``P|52DzD7tPIqvKHhTgnA*YfWb%dD&legK4 zy{6@tahuK#QJXI8I4z&6x`u&jx&ab$xjWryeXh!OBCpRWg3C!T6LWKlNSTviC&QMc zPvI81g%ur9)dP@{OVEWT&Z*(LPJq+Gb)C5GbYOfg#XAF5Vs2i?0@yvd1#H@AFRiG6 z-CHXvsNzgOa&BIy{He1*eZ;L3weKr#ow$8Jbt}myxBluz(ausgjy6EtI!m;(#jP_% z8z^p_Iocp~lW2q0jiL=vH;y(`D!NenbEKjRw;!ez)Z$#N;1M~GJu?L8x5 zC*kZLCZhRZvB_R8+8R6*I7@&OfyG%Wt)@|C%U~zua-Wv->M6YXGT3!; zOQ)1i$mczM1vn|UEI(&5+WZfY!oV|jCD)bb^C({qNX!MmZ#Ox7zV1@3P{K+nga7CX;L8pZgz;=Zjm+>9D7?BsODAx0+3qUxk+*91pY+a z!CoNpx($$+S6oW=?cAc6_Ln=j#gx*S9CxQfd&wS;PZ-$u!A>HZD((j)GtdSe2v-r<(qGP1(@GN;)Z2nZ- z4ZF^Gci(@6>qN>uYLhCDvOT_#4i}HXPC{R%(I)pYpzE$O_hf? z^#vFmV@CCtVU$gM1;nQG6#Hwf)N{6PT%?VE3q(iC$^K4l>d5!7(Gg1I2bf9Y%cfM& zhuM#S6b3$?`~*y9q{;d-C~z zc$o3|v3E_PP>K+Bstz!Tkf1K04xnt>xH3|( zp8664>$^y`4YX+)H9aa^CoLNSX`5x-@Mwpq-7%mhJl)ADRBEBAQ5foVkMhxIsCL>r~Db?>650VLTP6}D?oBV{*1~}ngSt*s0Xb< zDFp?ECGx>@yo)sSZGedd1yiYATeYcGJGKjXg0_d9R8TZ!0&U7t;Osgu6pMf-0Fn!e zb7t_hSVvGI5!!T;n!*yU=`1yclwKFu3B^-roV&tIDk#R31auRhO6pd3_F?lxGI5fG zwI{JhSsu;2lVK+nlp#gHDS+gHvht~AL_OH8oJaLkv3V#?6PrikbhXL<46%6}dWy}N z_JW;Mph0_6h1zF|6Zg6g>;y@mulUQj_fz1l^$!DW?kok~-T**iK{=26*|1XzD#D{S z&_x=xLBNE93cBPN46{x_MOkG@9v?@Cc$i#=f|DnP57_58M0LZM!q=|nIz)BDK}m&0 z)A$s91RxPW!!c4T_`_PNeAj@mTWa@na+&WZB?36l!xEM=iAsq8HX%@U3XF$GRlFqp0LLP8Tj>B~g zt)|}Nss@`MKZ7IUL>|4O4;S1F!Rm?9s~PM*kvcU~OzIRa3=mN6XIuh1o_Frq?0`FO zxME?GKe^|?Oe(6Bt<2^1e8M&lW_;0fIM0WbSTvngTp%`gX`$Mb=j+P^OolhR)y?s7-$f3lvETPY@`e7U$t-&X<9%^5UJ zu7DlSmoTeotsb`4kUQCQ;9m9Z?&SdD5dc8Qx zdCfHdY-$EoTq|xfj4RJ?A#b$PZ``025PYhkf^7Yo7JW>!!2sl z2;9gG3MTTuL zv7D9fQJbWHRBe*}G1y7P6(ap!sbJ|Jhng)mm~2gi$wQ{_DCC15g~#rI_; zk?8=a4(iJF-2D}B5;HdbDj*R+WAK_*@I}T!tsre*SDU0gq)x2t8)2Zi^d@h&34db0%MGUR-KY21XG#Shao!gn>fZ-2>mKU3hT{y8AAG>^|lzF@mBk8Y}b z2|J;bFJHcbnNnJokNXxR$JfAQLC`l2QQfzox>Q#-RR-$2aCO;KRDbVQ%fS7B6-n%m z+8>?Tapim!@e@|m=UQ69=g>c6RU%f={_qQI>X+W!{uP)+pN`a#-x$V^=g-OC1tv}} zL(Lxy`K5f7@h2b=5lFDV*p~CMzuA^+rhm8rY#RT61uFS=I=)sApH!YB=c@QpfdFkD zUnz)>FXw9%Sc&CwCp>}I(xkw*2ypU+Ct1mH_yz%7$-?gG0$?1XauJjS;L$fSIaf{Cc|3Dc0*=Tpb<9RaxH)8{e19}u66 zdt`D~3ttallG|FxiW>=pZw62c8c2LA0A0xEds_HP01}`$_%;C6PUH^bs{nAGNaKXB z0iXvH3;D2tF99Gr0m+H)08o`&K;jz!NST25aeM=SqVWem9{*FTq9U%r(|>9u*OPem zPptqvLGbLKTJikBgMVtJQwPuexfKt5OLe2X@W>xc zGd$%dcm8a~BYw6i7d+o5f7(^s%WA%bga`Z7wt}DSbkGW#BPXywpG@O_4R}tEv8TS_5j|E{=JF#u zJfO#z5b&7b0X>=n;fJU5NDnrTWFJr+P9M%=7lC)u3=Ij)fkI7LX_qOniJU(Ft zf0E+)czhB}-m&p?JU$UX$>GsBeKymW;ITM9*z@_eHlB&gMP3KK0flGcxauksSTw%s z%N&--Gjw{H!%{KnWe&^4q?b7?7n5G*aG99&GKUpn(#stFC+56)@|&rZit`08S6m>t zN>P8Le1+m7sa>t8KT=+!s6SF(tEfLxzEV+tq0c4W6XP?v05PpCHcc%oKVkvFB1gJ34%jxnDuVHVNt)>8hW2Idg%C6yMAr>j-W zAe^i7bt7gEPOA$`ahsC;Fnw?e4({F+j+i}C+r2B-V*21Pm0ws=#`nW8eQ+SJ7@yDk zIc5(XF!_NhrcQj_;=;VLDHIElFnQwZk=>~~F2U#shWUfLO{LwtqW3_|pZEqPQ%Z75 z$_q-1b1LXW1d}MfUdfaS*9-F~z9H5WmUx3>I>o18ZAnfZeavGz#n%UFTHUb30TMvZ}dr^H`L%AHwnpD60y|5QVUBEOC}cb3D=V^)#Ghh2_3MU zfTbfAiq#2AXDnT?bj8vQOLr_MVmS#5#UVf1Hf<+5W?ihShsCd7efT!Oauk+^SdPYW z43Xa#%W+tmU}=h_8J1Kmct>bL01MuAm5_mj^q@RR8_N0rR@{>jy9buju$+OV z7nU=z^u^L2%K$6`u?)sC6w5Fy!?BFSavqk}SdPci21{Ek6z>!)6!TOp6!&y26uT!D zir*UxZKDqs+D<<#w5_wS(Du&8LfagKg|<5c3vK%xEVTV|u}~jIV4;4D!a{u+jpckS zW3XI+Wh|Bpv0Q{@9F~i*{J$PY8qfdN8qwT}-dEzV&bw5%AN=2%hv9i2-LH9c@_@e0 zqq7Do>2!fgIs>7SPCclka}JcWul(1(M*CHGzpgHy@ctM+F65w1E|xqj%joVP&uzs90Qk6*}@y^$DOja8CG35qV|YdZOClYe?;7fdH>>{|ILgaS}TtNkH==# zIh)BJTB{&*ZFn>5X)_aeGi26uGpmrzysr2~35s?oXmiZib7$qzGe5s<$L{N;oNEBsB&}jZU>j zrCKALjLt+AvXzWdDWlPDMqSYT`f(#ED|?hAL|NG*Bq7R5dwv1;ybpqL&k1Ad`7lI) z1ZQ!FVGyI|`RI9Gs+E&!jZ3vIbUJ@7YD1@cha=DJyq$wyhKFOE^qz;~Lh1c~4@Utf zH5?n^qzGe5DhCme%lVuO3}PfzjHD)~T7{|B1Sg|hR3Tf>a7=bH@(xF#B*eopK@#!| zM+x^l55c(SgfaEJ3=z=bLhdjOV)T3ldOj`Hsz|lUQms;_^W~@w4e$=fG`I711$r4C zjxy;z4@ar={=bJ~CMQ*ajc`(gF(pO6+D0xjI2RbiNNOIEnv-hHPPJw^8O=u(vh@td z95*BHaLks3csOQBLZ0E6&pls&VBB-Un0ijX&PIpn$KiaiB1X@bqvuOgt;MO^=G`mgtu;<6^uz7Qo%?Dx75hrhn5?N;F4u4_^h0pYg)pXE=y%vi z;Vw=A1~GEkh+H&=0gD6WQP<;vJJ~YnI0ioCp2hoAV%yDG&O6HM&nf@8kJnrB;=m*`L2VqQk(9f%p$6MTe7{tiqKICyv zs&#j&b*GaG{q!0h^pk58^iyj(6wRYopY>dj9BqB*)qt1RH z6`pe5c0X%Gzw2g=2xHQSesqoS^doN`Yhq~h7&O|GYVCFe`bGTcSJ-f;UtdQGv`2DV z7I#Hf=n0QN^uz4X<52=V;R@uPCK`i3(RLg3pa&;i`3q}VAHtaQ zNvX{V$Dv?-h@sDm(C7J7>)BLmzavo{ajh#wJrt1=J&%;=Y=q{}0gpuW;Td{4HS*|o zz?I0>hCGL!6`fh5{RWL1P_P4LjgCT{{j#gkORP~ttYwV|W6~%c5ilu^L%|vmL!&pL z(Vd(w5h>9pNGUvr zzVt}c4W6MdQX`MXU%C?6+K}haN1`)p^npR6?iB1xvqmSP&i=yH=yTTSB&=nP2xHRd zOhkZ2r=nnuh@sJs(CGVA>sv>lKH}F`ihd{}1^Qlc<2m$;N1*=j4E-D>&@Zk)-Z`W( zSf6hV`kY0velhDa0Co1yu0B7pK4)Vs>q8imJ|htU`V2wA`Vd2(f1%Icsn(y4KBL6% zJSj$_h}7qAz0;r#c>?_@B9lNzK7S8?vW=nWwbP78 z?h8<7*Gh9f+2YbD(Xm*|iV?=7SOFp+(8VZNF=8l|lGe{kN(lqZR z7BSQs47CQPSp(9n{%KZUN48f{8|sthxv4(T&D|cLbBu1P_g4Ywrg~r4;hXB~j&xIf z2q*PAHo{2}#+1~Dh=8Qt;#^=5BdL){YIvG8EX^9~Wb_fLkgeyo;cz!2?`RH_glIJF zp^}j2R@*4<`Ns&xJtvH*=RY6SKxIvic_jH4Ewk~mK~ayYeLuqjTBFs9TJ;yJay!l@A> zwTVcrAk7+|X5~70C87#Bdj_Sz&C5F|<0UN~lw3*6Gbn}J^CSf0o)gB@^JAsw^|-?r z6k_yzDtbO8%_>f_CObWEjH<}#G{x;Y5L9CBVq|!~qI|Su5%VP%Tk&Wn_2VqQkbU*}jKg8XK zL5w`+A&)s}*6cKEmXpc}sEV9TbKF$y*`6_(RkK{?b1oebo^v6LDVNg_0V#Cn6kre| zmnFz$QJS^DN#t~_k4$8dn}~Nz7St?{rJTnZh|YNs#+1ikL_qiZa`#~nBac!i2&`p|2xHP{93nuP(J1)ymKYjc3ys#NSywv(T`Yb%QsknD z6llHV#ur%Edj!gZXJ|u|K-aqhd8diS;G^f&27Sg;tn1DCr;TWtPf#K z`jjC8^qGW$^&y5n+n~?QY1Y;>Yl|aMxwuwHQHdf_qMMOY_>yXeN1|!)3~f(~+>>^= z64~02=g?NsnKjyC&}cdZ+hNvd2I}nXu12@AMl-RNH6n~jqa}y{jpm|YjfkPqE@*UD znzhprXsP%ulVUlFNP+H>+;|S%=Mm^Kc!utc66iixAnzQ~7_84ugFY)L)_rDu{)amI zURR%cSf7m^69N5pTB6px~a6zqU! ze!cDy>@j$T4o2;Nue*ZT+K}hhOEsNednx+sX2l*yoqf<%>@`;G39Mzs2xC(0B}9N? z&!Aw%h@seFDE5{k*URE`K#EsTM9TG+XMVlsk?U1>hTe^m>pfR4@BGpj{^!?g6#PB2 zS_e^Qzw4^?4y*M#*0NfJF{#xmfz=A2V6}*$R;xfit3|*H2CU40l@YK4f$-hf5FA3S z1EKHrk|~S69M&S>-h>VY>U>;Ph3L*8v1r{W>pAdQl$qXAW%mXtO_wy z=?Yak2ds_(t3$wQAF$d6tm7SFPK8gXdmz*xAlH&15~j09n2sJ{I(UR>?+Vk_HIF}{ zMtsfesM8ahw!2qRN7lINbYpdT!I{+|j7gny5CQ7+L&540L!Dkw=Zt`LTEOZNuucwG zCpyv$g9F49UD}W?XSlj}cbU^f7Me7657B}qjeWAmK2e0B8KmDb?9F+di;ZwzgfZn+ zhzQ8*VonDJG4dLYyv78q(E)2zz#8EsH3_xYPb8`Kl++k=QlqhYAzg_hsZjyU|B;;2 z2(13TK2|$mcyC#AdE?m zb%+2NE=R%hl^A-ILyxHeYf8W>4p@^NG1j9NT6xBGs;h)|vQ7~pcwCD;6LhjD;ThNp zPUIQ{=0pf%N@N=%Ad!vSe;C9_WF8Wk6R>6ntXTnTM!=fp$uAN5i*> zW_gmC;Yns%m1O2~GTRZElOc>LnFkO7Iqc*dU=Smj%aF{nfVCuGEeco*oJ?%gB2mw% zEc0Zt#FNP)Hxv3K`B(O~1y%A`!FfE0xSR)JOnE$w2CGr^}p#Sf1|6vd#k=u~S_JFl5 zVBH+Bwg#*%PA;FrA#_I|^pE#+X1kk?y$yX0ANp>VeE86})jjlWk#u|=`o6~Y>^rI) z`ecoJ=)0Zu_y*3b2VqQl{EY~Z;U^S)=p%+6_d}0+1J4@-aufupDgAy^NIWIRuxbI*5N8NB29wmY7Bviv@GbtnRGR|#Y4 z>R3cTS4VIUVGyIMpQEdv2CR<*)`w1SFGN-7%cx!PQ@6wR$DVQf@c+oT`*6ZCI4QCl0*&T9YSW@`Tg8}|kHC=RL=fCb;RADgI^Rj*tH@edA1&EB z3S2+kDA{_{+4a&L$?B$4rq^ICOGX%zWH%uK0&PUWk`Y6)#*nO0x^=W8*3IH~ixk^X zM2gi&^5o|PO+8}W3eQlJ^vF5Y)D_FS^Jom#>S%*L+bLF4vpzdeXE$;6Iga(Y4Qp8+ z!kF~25dr$#g@W}VhCbQQCoA1*o^GW(5B`lD<$4rrSuVnu?g9bWPLo6 z^)^WMAq5_6mh2%+`iH!}3ISmMq63**Jq_O(^grvt&(CXBWDXO=QWMVJ%BW7?WhJ z5CJnR0|iS)49O}WSy{SOnr@XidWFQbwG_vrh}5f0Qso&o-J@3h#}V^$h9EdnwM_P zNw;P@iuDlhQ>8c!MWkX2kX3kwE%hjNIy^&5qK^7YUBzr|$TMu7$j*|@@kln?AlVrd zc&S;ko~W~zxRNbq$$DWeOGX%zWJ3@ElJ!Huk`Y6))sSpey0tRhTH)w5R9w%IVi<}@ zy;e!8Jj1T^=yfhULu;e-y3*ClJHs>v%eB%Y*9wDN!zu2SX1PY7&R*-vwT9&yiM1>j zVN7!6Ap+zYgM#HEhFqH=*A3~`_374i>DD!lV&la-Uy1@0k&4}btim&Ft4Fbk@C@CU z9{H?etE-r;4S9xLFS4^_*Lftn#vs`w3cS@U*<{q&H@cE-VabZHmL(&MNwS%U0LiAJ zV9AIf+1a@Kxh>t=o^EY(^qM8Emq;-iMWkN0K>|G2Sr)f2D|DwvuQ~7x?TpgvPFFAQ z4AU4a*Y%Pr?lf@03qcfWu}{ogWxQjsD6gr!0bjhFpte}@5~*OA;%N?j#ER}`W+{E-i%LiyMenB?Ms4J{ zw01jhxAKfj3wH?IaS6IB4dX(75x+-j%Q-H?HaSPam~vc)2uN)erv`%l9W$&B z8CH8I!S$#@@}AM@=qBhLoeq);O+LH5YwPHA;htZEVBB-Un0kIUBA~= zi|ZjN-arxg!7vO7FQ#js#aW?I8SXQUH{lr?nGtz-8Rbz&8}dixP?3RW@L<<=POjdf zV52fH>8n2ac^h^1$PDK>#t7EvFxIk0gfVIKIU+!s4^Z%@1Ti$a2pWyeu*Nt7eIb5d zO7RtnNP))c5YtNuay$Zk4bRZUQ3B<-0(tjvjlueiG3fIR#mX`3^DXM^i(P%ju|D5n zE$c%VlRkeV0`&PA1?xi$eTtyZqzr3fhE?E5^pCjyD@9yNv_zATQuw5NibtYa@C=n? zL>>gExDwggkmt}uR~Ng$wVgRsn}SU-YZQ+#TnMZ3~PRdHP=z8t$4SSqCJX8 zl@=qb@HD#2qf!TWhL&gGqiQ#f5^?i-(3#FU8SI&3$hB&uv%L@&at1yIn-byzN9$aP9) zKkKASt9z!^HPh;x8NQmN7tn+PnKDg!(t+rtO!sQCd#21UIw|f7`!PB}-koK4h8=#F z#Svc+-6NCwvIHC9qzGe5ie4duK$meYFo=;guVI@QT&Evk^MWYmW;>gi_W z9mvxqANHsMU}`IQL9JtvH*=bI4$9d=$_LyVpeM$ZRkS_3kz{+U)^r}Om6 zno!6)90T3X+XK+c@HI+*={*leU+Mj_h4cU8eceMiDSF!tCq)=jQu^YUTR9hGM~tLK zBB|k-*04-#sFTs%l+j@Ca13`d@(#x^Nr;DIs3hbWj#1q6UE!V+#?{Ntz%b@C3!MQ-QqvFK%ZIL1itc{oN(@Be!^ayY3cun`^( z!kChJ2@#OXKF$ROF_M~yqzW>v@tIbxlhMnlLbjg0qrlC`I~?OBAs&ugNysxCh1~N4 z2*y1pjH&1EAObpkkUI>67(Jhgo=?fNiZiXrPS4*(Rpfp>#qGIWj4om<=s$b1+x4nH zHm>@D=rYdbJ%s062xH3SOGH2lA8`sWh>^>5dCcHE zzD9J;gD|E%en$j!|9kE}3}WOl4|&YVv}R{ovz%1^Kvm?!yrZ;tB}XaOlw7^wcJUCUTPD$hp%)~u~&G;WO>bUxq@>^LwL@GFs58u zAp%lp&MCkkMlM$&m$jMJYA2Bp)<-6?)=k7aCaY_f$JLxiYeeTf2xH2l3nHNV?YR3e zh>^!esx;E2V@1)XIT)Rm@uegakFWn%c!e0a2oax@QIuV|sO_`BLi_NYIwl?I$ z-nFg__IlXSFM2tNf^E)(a#e3yos2qrQ>Js%>IT;66s%>92xHQyFCsu1dS?&sf5gz} zR%mofrgf7eP(ShOFU46XA_clda$6SnSXSsZk3a+98QKvg&~2_j-f5yS_!I3WgFa_d ztlP}`3`Cv1!_{Xy>oW*zSs%if^tlKTpwB22tPe5tc^LXUm}xzbY2D{YMDNIftLK$C zkrF+Kl)~47dpr`+TXRB>WJVs{_P7$++K}ha1EMo)be};ZezDFTvqtoy9QzShqus1g zKGw2EgfVHPFTxFb+G93W7&Z^C&}a^pGlj7OkpXcyWaCD1dj zK;Ai|F<76+4f^nlaGo*i!!N?w@9MLU^>JQ=Ll~1j`hpwhML5KmL$5)fS2C@aGp!dL zi99dCfl~B_o5(rz3Q`Ksp+g>tR**!mXGR{454jTA+K}ha%c3)D^rAr{df`pzkXa*o z?T!7qtIum{S3u^bmY=^GY## zI{oI6i{6qG`ZY?f-(0!8(@A6aSBqb)^P5>MdM%FqtE<*8tQNfxhvyezOlrM=2$)|_ zqu}{P47F-y^|SuXwElJkdr|!KO*!-~oJhg`^~|pXx*4T^N#g)KL-ARWA94vX0BpQS+T#cmK7t6NwFmS@EwZ9 z@z3sI5JRy{D3;;Kl`KvvQq(~aDOZMPer0>)steChFiNg$S1#}T(ir~Lsz<@I&1%(0 zogH-5%3`$|U@faf7?WDZBLYOqM8Wfm7;2pYwNA>ix@TEkv#idJY;8~*>XhZZsqW@( zch@<_H`P@@zNrp7d{h01-^}X4NwvpDI4Q!Ik~#?ykd*T-DPknm8%g!dvQE#kPIWRm znKC*>Gm@L?ZbshGJY5o^(X>yMggmzm&*Yw;67D%+Og--}JwKg0j1-8`^TFu(z$|M( zmeoJY>g#m=EYwC0$3VC9_5k#fc6l0({?dE7sV=?eySP<{qsmudhHz>Fu_+!D!kAJU zg9ylo-WkO+jTotoL~6sctYKN!P$#boP=%a5_i~53d3gtAn54ynGE~y?49Y0(`B((w zo)gB@b9(I*dY;Q2hCz&;Uxc2I&9cU1S)-kv)0?Csr_)%s=k^$M5hKFK($Q|$tDXy1 zeL?g%&ZP+9ITym1a+!_@NTHNdfI*C0#v_;9EbC$?kr`MYnMkgih<6Asu2~-WoX1Q= z=R62w%40Dip!=7i;MqisJc^OWV( zkaw{et_=1x*wOb5Z>3;!&7ZgQvMqa#`+0jQYqSGvStG)jG`bHFAdT}1E@Ei36dEng zvKBf5-7kI*NI|dSiWF$E=w98z9ywgNu@X>RjL7#^x)@5dW z9!8zL+|_3p>$4kcSs%if^x2OH(C0A}yk8STpR1tH+AM2zmbJ=}=oxW+R*L6PL`t+4 zDTPmY*Lx&-9-g6fS&@6vdRHP_8}b}lEjqJCs|*^^`@2Hx%^JOkI(wa~(bcTcOIXVq z5yqs^VMKsN2T`y_#L#FHG}@SDZEyslS8~DcT`Ar}5h>6{$&KgGjUIvChi7O@lt4GS z0(s|<#$bIm81(soV&M&9z)4f<@) zvbH(;{2+cmNc>-+{kx8HdV!vT6D@GWTVzm=lvA+B8M;48t_NJXywgcz_*W~LfsqKFi1k7s^8;Sr2pv=(|iYX5t}70lL#Jim6=bbh5$^e4=U zrJ>G#+*NEZD;B_7R*Wzv#abf*6bqtY#fYKUGf-@wBiHfb)JBT7C?e(B=b2y6d*o^d z&(L#Gay{?L<(*#|!~guEm%N3ZH>*Xjc(b2#)q0lIa^BBI7?WC45Ep9YqhPg&p;n_{ zKkMkAbyU!*AGGQQt(0K+ZW+CzD%3a_dPgsr`qP)gjt;sv36BcOk&G?{>%$Iz-K}nr zzH&=H@UT;`dLOC!o!=KkS757l<6!g)qGgTy!mne4luRX@c@7cAqzb)x3V~*!U{#2r zN(NL31g+Gd)ih`w=SV_tq=I5{2|1AT2)KH9XGE&VL7Lc2MGn%$K2G!?QS|pc%{h_9 z2+WBP#+1lLL_i`}q2NS_k;w5#Bowq-2CeL%mE|OI18PHUqsBH=B^SQRZ|ND@YJYTr zJBsW=ZRF5)cIB`;BH8dYb_dae##Vlh#v|Kah>^oU zD{u%64u-z;9()G4$=LnTS2~TNgHK<{hVMh2>CVtzl1?=T zpU5{^zmDzMgR9Iw*lL9E9iIP;hi#-zt*hyWSreOEj;iJ`|R=rJN_og1{y30gxO zF+N8vwDKHwMz~6NhxJ?$f)6|Acn&*5Ldenh4>p>Wk9!(JedK`s<^&o~GCD5ZNXiW-Q6N6TPBL=<730ipu zw#Ze&JFt^P2p-spo`Ee8B|HN=g%e3dU`~WErbOrkPDrFV_a6o^61fzKToSZq2CeBq zt1@Vn2d$}2I{b2`xxvsMy3-D!PsmH$jO>}{Zg^~`OG-SpmG0PYR=U5Tz@N0)rUpTn2TP1+67PYf;cz5VYnw((p@|F4d79 zM!GC>b@7h$5|M>RdXZB8+F$S8!hRHYd)DFs8id4Ma$XUdF`JSKdezT8F%@ z3R-J}*6N_ODrl{A^11+?m=rRDIj^hCd9C&2wc3-*Dv!OgN?z+Zud(602xH2tT=Jrq z5piC`7_UvpYh%#b5VWp!GO9pTXiL6oOzH5V-jN#B4Cg&MZsbaLyT<@sBt=!cm2*6z>jH#>o8lua>T_r|W??P912CdtJ)()q)^s1uJuBZ=| zooa90Uq>gp~;Kv!?&9>O3-SD!*xp9oregVv)# z>ye=Ku+!&z;1Jpuwbwo2cH7?T8NEl{(X$_s;|E=AK8)4XUu;I6?>&I++54&tovd+( z?rGM;hBNCy7?U3KvLMLt2nrrLV(9TQ^ms97Js-554O;shG4`PrT6s z6p?pc4xy8D9Hp1J9uB%+PI?QTp|^v$P!j>pqa)8@R{&cZQfvF5M}b#8S%>d?9;RT2 zgAlFicah#fo&9#u`7Y91tkJtz%Nh~Jq!GOd2-19nf(M%z8hs3nJ`7s#I|9+Wf#CPG z6yKnT6zD_Ajqjv?<`L*Sc!oZW66iBmAny#(7<@YMzCoWKDAs3YeSSop{i&sLpmy5e0=iux!bRr(uQg{M*NY;2>g-zC&XkJFrV&0G zYgsbFm?XDAEH%R8$y2FsO_&3F6wCP)%u;|R>ho$wymlHxWr%hd{X_ED}}4Op%a*0NlL zG0AlrB0#RLC|E9H$dwMc(z2~)*;bQmtFfcl>EeBc6g^QyDwc+qgXF^hMH$b zUchC#irLzbXIL|loh57Hk*u*nvfdOp(=6GUsI!~9l4Y=DeXy1#BaBJ1VTb_92B2Wc zh#^@UNY*;rYL#uZaP&G?T!%|B0!5@=ttC}HZngL5H4>hoc2Rn@clGklFpa@-werZ- z!XVcuird~S*LkS3+qrVJWw}OUEz3n1lUxOe0J$zi!EzBpu9G3xiP=`SY^zJQ)yYwe zUJC~AiBc4zh*a!EWEGxar+O5d49`%H?8sYsr@D&S+K^{hH<6ts>*A5DlR>g#3VfvAbBLlLQ0 zA4!#G*Z_}SE8rPAD;syc<F5ksR= zXjGDI6=hqKvaN}ZOb?1Ty%Y?M9!3!LRF>>ftYygvW0LH7L_qfPLNpk}knB=Oc1gB1GuxW( z==FlQz9_{@C?fT`L{jBlZ=Of5m*E+j8>QDgS1<3uU1P9ZGd*%mH^_B>;?6V6^$P0j zxvpGuSgu#GmgORhNv;nO0V>hk(s+guL#|bjYh|{zBHLP?Z7t2V7CWMSBn>{6;u92+ zqOC+?;Yqf}Big6%46V+Nyn(jH70uR$Jjqsw@~ql&k7`Rj_F{vApV3Cvm=*jSb@pmk z!7ErndM6qyNEnlXzaat?q?ebmg2Yg8BNW__ZC#sftcWnFr$KIR3M^S8j!#$G#kpLpNASz5UGl>YnkN{y(vhOPdkVGKPBohddg)D%} z#jpy3ih_zP?jnldf}+uj3wqsgy%*d?M8y?QToL*HRduSSr_gt{jqPHPBZoP`zAH8>M1N@O`w@DW_{@$^BqeJ)hHU;C>MvOe|){Ee?z^V5d z@t2KlG7k!W+1S0oplswpQ7;=~r^gf&H(vFFlsW@|rxZI!N^L<<9#9eS2qLclF#w^N z^nfmtw(24h3(A;>4H4NIjEFvyNJdCN&Sd;s%>%;Tiq`gUFdz@{fUvir@hoAd#}tqu zkbr=&*Q4=(uyX|DNd#nDbll@ACPM`sd*v9&hXI7fWScHaw(DXt9F#FnM~ChtZV$$! zjTm{BJZ_RDBbb2g=0O<=T-(#ZpghHcat>N~P}u1)1%ozZk-} z!`EdLpn{}>&2C_3)D=(q#Q_{G46_REh!{K9=)3Z2|Xc6v-cu7w1+wvxMs19lD{9d7(~H9GD{blhR(;5wk- zysmeS1|8J*&XHh`v>gr}Q|~z4OyNxs#w};3$7K1#kN`oOxWPDJ=dippERS%!EM+m`A9nZ<|;IW#8 zA7jG0vOk8}esBA6;M%&l)kb6_kI~=J%45V%k10maLjpqc6aXK4>>M#V2{G#FjypjG z=mkOdq5v-ega)Xm@P{wydg%i6GALtCF$AbrFhKgOAQ?P9Cz!zczoD7;^RhqqTF$P-En8A5WOcz-xuHmfY1;{!6mtR zi_wMXLr}(e-Jt^~CK#eNV&pm0HyD?;GlIt|hdyG$V$5T-8@M)aFh(98qmR+bW5iC6 zDMsHy0%G(z0FMznM~ns{Mg!b&XQ=?~7jy>%I0z6LpaH@ko92zNJWZI%~A#n zVpcGS8Gk;A{g}2w^B|rDTw6gfi1|E-{n5&U$WD(bh{GWPL5v6BL1gC$VmX31!5uf= z9XHk;H%7&AgrFWNz&QY+ahw2WWj0RI#c>oUV z6)dgqumeo-*^DQiMN$*jB44o9L1V-EadaZ2ed%u7jR4GN_rm9Q(OkWI^NeZxlKC+F zpqq8rO82(K^AB~=S{GtUDPZDG=0q`5du^N7DNJj_(fg z9&63{T?$Zqhr!-&+#wp3Pv3B#4*eTGb?67~vEjvz;ZU>R9qNW##%@2?^Mi$+Xsg&o z2V>WvAGn#Gb3%h!>^K*lhiDZ$M)4rs+b&4KXo-a27ptNJ5Tq-ji~&pLp;W4i9Vt9h zS*9FIrsftq(pewoB0#?*Q-5>E{pybU*&X+z%+$QL-$F9Ag9qgKjEAQdW$IDpVu8Vv8~IkrrN9%L%GS*DgijnmWit1ewt@;JGgPXCq~a5FWdp(fnZ z_OloRA{r`r!nvLZ3q607Ji;AtGd-m|Mfy67<0zOSLN`wl;j~B*5oa}~#_Cdp_sck* zBJA+5rbs^zCWJeYv;emPux{t)2uXtnx3WBO(>?NXb3F*!rh727UEBh^jcT4-i@DIV zjltF{*#fuDgJbT1AY?|n3ewXwEtL_Cn8C8E^)5)_HnY=XviW;q^L}YFJBQ6{Ve@KF z+$v@BA+*Qb01NR4FtyfeU?MjiW?dE4w%Ws92+vJyTZQA>*zv(G1*x2R#5!*450JoZ zWv74D)~ns{wh28BP!GW4%g$kIeN0wdZA{#SF*3f*Xm7hPMm@$$@tqbU;=7W?w>Cz` zR}jKr{3tUR--Z~bss)m`&Fu6KY;L_D4r<*d_6Qr_MLWLOc`kb&{Yz*9coBe`%+6u* z*z&BnL%z80eA47s(B5{)wG?yc7+sVg~YeO#@&OYV{-2k2!NbD0Ng!x z4)@N7dq;h7M|^RIm4|x;>1O~jPJc|F@@)&Eqmb-9;rLa=D4TMW#arK+l!mdv~2fEGaXB;SOOhqzY&e#R>Z|xEf1EuIMnS`L37eK;6Z~UUvJKe)N zk&>@L!t}O=%w0}4nX_hbfPU@8MzxLda47$!KMO&W&gRww5YPT0KzpO(7tjBgTv;%G zC5x9>CA5A6ia+LZ#m<|5OP83$@@ z9)JI*JT4U;52Zf7#lDY~K^vk&`?FJ&DgaJ?V<%z#P;+o{gq=9YI{GdFWUurD?j?Yj ztyMAoFxZfHt(%#_TdJ5nD9z&TTI&pS4g1F}@9bx@okPviAcF^Tws{5e+P2D0J?aV` zYkY;WDD~YaZN$Ue(H)@Wjgek14xos#cNOIHjPbsaeA-qr>or=NwvV1C}2SM-gxZ^_9NqP^3`DVLj<^ z6abY~-&pI@b9LvaJfKRO8w0*t9oGp!b#=nX^OfcaHk!v3MKw> z8}SQ)vv6#_m1drA%a!;mZNx9Nm2snzalMUF90huM^ES{vN0Fb_AiN z@XqGKBkhHsq=feXp@mc3?ev~(uJ;ssy?vD4)9i%zH5cx(7k-u!9t%PXr@VH0` zV6Qh(>5aD&KG=7dQ)tvwsF167-+FE?E zt$3djKiNk7MBpqOE4S7>!B%sP(p+t$xyo9+-&TC15?^m4z7{wO$1b$e%$H8HmG~AL z@lCce<|-L;Y-C&toP~)O+ls$jiCq`9nNcjG?{^} zMYBysUZYG}Wv%ymJH2bo^{%tmd$-cN9)uP>atBZr!~8a&EJJY*kS3wnh-RBmJfuu| zz*_Hpc6uK+*SpnT?^891izsA*mEHZ$$xT;c#D|OncGc zI0LA(mg?$2V|sl{9rik$a)%^}?{%D}@VdQ@Xuj9saK-{@O!!tekeKp@D5DcVrOW>i zqvL_IFnS@k+cQs&0p4titJ3&%g#6pG0ev>S`O+Rlr$v zv>&K;R*9Xq3zTMqRjndBCo8S-{EbSyd0cN$c(b@}QtI!qQNIB=i@2@_$|A0JD9z@U-KOyE zEOR(F18Fr%9#uv^3@WQ+*aDn|We+IL=9b;3@a-(aDEWs{zuiXtQ@~lo>ua2A%ms5F~f_PoNkvkWnNN2%XwqyC@3S;Xv3 zpiC`eE53Juv~v7orTIe}&F@=_hxK178K2w8_!Kw`>p!s;?{Izvq?PsGDb4$BG=F0) z9@ZaLGJXb~g@r#_iEua$0VS3I?RwVX{0&H>@!0=8f@WQk8TWrXpDveOzr_f3%k18={?z8?^T5lhv*L-lE zuJ9)D@BnEN4=b;Y~~~0Mf+dLNwc$JVBW}4ulqV zl`6gFp&YI7CU%tpX<}D7nr-Zws_Y7Y&?1zTKv|gV1IjLx6$)=+at)9sCQn1Njma&_ zD&i59LyYH?eC4kS2DmM6-=uw<)`B2BAeL*8yc=@*1G*LV2UY zo0xn%kR~SIfo2<%H!G9x1z|h8#3kiDO0OZ5xTM^ma5|gBC8fi8ACM+C-H&D)o1RiO zZ3Cf27#|0!ow?##vkfTAtMf;Iw2Se>3a|4=UWh&oq=`S<(QM<-Ys#NjKxkp~OF&r~ z{Q{77Mn9+UCPu#wq>0gQpxMUg_mt6ZgV3TAb^>MU4_jisZ?5+Pd%b&=-jD5se`+rL zGkf6&l<;prXyMdXc6tw*>;2AN?=MR4k9NX;H5Y!^Uiisp$dzHwGeWvFWPk1i;4BF&)e7cS1-e%%OVd-Tio}sw-vy}K)8}VM?EF5#2X%;mi z%1pCzEKzBWx6wS%TKoW8@hM9Dxi;cQ0%zgaaBIy;O0%I>(?;76g*WTb0%ch)=yc^F zB$u**v#=}^D2rT5SDMW&OI3I?%f>3pMw@Bx!1q3jt+f|gOLsWO0clbq$D>&n1LGxG zg)(WPwcc_&y%(74_1WvKReGm^(4r%z0%g$=)j(McYKOB9NRv?1quC}Dvz19L)_R-l z^j>7H_hNg!iY{WO&%9yKU z%(0PiDR34hUTiD=awUF&jre)CGL|bDSK7!}3Y>+BOKinouf(sg5r2)XjGL8=wbo{= zwi4lRtOClSt~i{x0BKSNZ$-0B8N5fCbeFZ>JMHvtG}n8tz20p~?_(ge=#fW(vM8}z zfwBz66F{1T;z=~ygyIEd(m$;AK4Yi%MRUC`+3Ve@^u7f`i%`4)ltn0B1IjWKyMQza z#oK7M3B||Cqz|q2zHg^@kGbAY?Dc-5^nM9Ki%{$X$}|*gL*rX>z5DI;{;2eRZzudG zbKyVR3wOHYO5-R9Eu1=Hr#H-H+KJ(4w&}!3r8feEmJ#b>F1)L~@KcoV6G3RCF4RH88yIJm^j5&e6tci!$y3)t&G1Z85didG22Rn!!Z*mi`;fN=KyIk z16_t@o8q-tnY7Sa?|eJGOU(6NVXyakrFR7gEqde{pe%;@)j(N>;szj1La_?XHlesx znRJu2-nDjmZ!_0>yS?5`O7A@&vyH)AkVki6&bK#HL3*WAU zKM6t$r|?5~Yp0$u*ZZu!-j|i$7wm+;VlI4#z3`qWm;=aSDMX}Aywf`dZQ3XtKK+I89f$MR=qI> zIE#>%D9z@U6)Ai>%g`lNO1;lUeFbn9F`ERGg=Oa}&E}SsDSSK29L@lcRxztrMo$No zRm`RVXJOe?rP#{a29;Gn7XfEs_5z?R&7KFOo!PAl-_C4AdzG^7I?!3!wgNZ{+pYo1(zdIW zZu3mIQsK>PyH(kC6X>jLTML{;Caea^)ND4p-3FvpkKL^_ueZ^BhqZV__CY1%J{uXE zfU~fEqqTU4a|@7G)<32+KVqZ#VQcZQ{&^+iSsNMKfwQpwDJ$^~#}h!=W$fP-zFk&0 zoG$=r<@lS*=+{7Hl`uPiGtCNz<7K7UJYQc__;!{dX74HWZ-dSvE<3HY|I=DJp7jCJ z=r^8e{s7H7M~yeoKT{@sVy*XMJH4Nq>)mIsSBsWw+9M#e2*qKbEIQ&BpzKoQCxvg< z5qR-Iv}vfEXtoJeS7mZ%5L(z30hFCx9Tnchu5Lh@bm8%6wz2CBWmj(yT7>8o$N&=xp zD2D)LVR9l+cA*@k@FpgY1k%LhbI@#Ka<(!#1B4cKr76AUp-fSD6T5PNG_fle%{F$8 zRd$UAp@m(=O0T(Hg$i$C*Ek?e>>7_|8@pyGyXrt_(Z$n&vM_lXPO;6(6a@N4PDG?+BDduY?0- z(JKyT7a&cBdsj5u4EK|jNj@Pu;IlG~;Vy17p?vIuAq?eg^7~qVQuVjZTI>3Yy0<3g}ro zWVjU)F___zlVlyJ+OJ*l3&QC@2M-q%=3y z)J@T$#P9ZCMnjA=qc+CEj0=HiC*WMUiuuvkS92l`Kl@l;vOYWH(;5R)v_$mcm^-AOdso2r+YDewB3KvMQshzg1b- z{~(x!*Y~$$+HA%2uwvR$rPcXr^>5}DadkMiLY&T8*x5#Q{$1JmNR`&8iwJwW_+wSI zz6NbkN3Hctyu2t}YyI^kO?$j5yki%wGw%*fi>y28q@5$7eQrmx)b*0O5X`Kj!E z=$RuXesOEt=W8}ktZJ#eu%g~y-O^O)!#m2`omcuAnwsnD0&%szCS=^i+NPP66K4+{ zJaJ55dcfBdm?#MbHdOhwUfSu}8Cs{4hPS#_xE8pscHJBOSo8zYuei5Fe-iz0^aJkQ z(LYA-i~iRAMf5(;m(jO-zKZ_D^L6wqo^PW6>G?K#rFVbyQO|+s1>S?vKfAw+e#i5D z^dp`_(f4|OioVLd$i2;Tjr&8-?e3>N8{8{Ao85~%U%DUmeC>Y0bI|>bXMyKR&n=!` zJa>EU_deix&-0?^DeoJeW!{~h-QJHp_jo_{yygAMv&#E}=Q;0ho;L4X@6FyN-s`2j_X+P_?~C4D-uJy56j4H#E1*?{Z6*Tf5xe<^C=Qx*Y8CLzh<9T-SWWV4>@B*J9Ta z#A3PY8bswf*Y&Pdt~IWkUAMSyb=~H=-F2sHy=#MOqw8MRX4eC*hg=W49&tV9+U9!F z^_1&r*E6o?T+h2+aJ}Su*|o#fNY4Q3s-ajyfE5 zG-^Ziz387U(GQ__wxX|gM}Lf-+KWE=BKphducE(>{wDg{=>5?Lq7O!Y7yW(oA@tu* z(TAgtL?4Zw?_P*LS?s>Tz07@;d%61>_jT@7?i<~!-D}svfxf#89yJrLX z@m|mUo(DWzJP&&w@oe)v?Rf!x`ikdO&+DEyJpc6U^t^*!{?PN0=VQ+&o=-iY3|Z;9cZhjK03YyUcr)cR6}{CHj4pceQsddi`eat?2jL z(dX;E8@%^;@AYo>-jDu&$h#Fe(1z^ThCFx*+3~FRIqwU|hnKxOysvrR@V&lxJ`` z=CH$%e*-IPrhBTV@HWO7=8%6hAxOq)rcCDz_+ty8x%hh~Pydh8)YS1N{CNb>jI1%G z3C!j+9XQP;&+rr77njp?5pO|dgPesEb!dLbX;5+4zfSmsId(F$LjExuI-fl}VVFzz zZ%|S^TH*)AC+He+I4C}T=+L1qR|4QL&T&C!7DR_uwWxaO$AMwLZ|QR9I~xn{U9)p* zbWG{?*N+d=dUolgG2H5IVH##0{!brp*1*C&z!-(j-8Jq21)b4d3z~ZjbSYZ*6i!Eh zXLNa`ns$!CRYga^XLOhUrfG}Dv!mcYMMoXLFd2Cct!rthVns)t!01k_)wI#;Sb7Bi zDLU#1h8cpW2Reru$mkH_IF`XR(*unoqBBNJENQHt(&(#oWuc|Xb>{40L;FoEtf_3Q zZ>q0uc8#xTYVl2Xl{U9j)znW+h#xe3VtRdTZA)EE^FsK>THJYBq88UwHNCLD zDxk#`Pr;`dAAf=tmze{a!m(Ohb}2p=X>nOK&Bgv{SuJ%CAdWM9%|0C0|C^JvG`*s! z8P^7(leW?LdjB+Ntok=KS}qIX0*#IJjg5hZ`o`uF4UNcxX6=NmGkW_6JBq8(GYLqS zo@cafZ_%=l-Rxhl@m*2UdYz@Q@750Z3nzg6`S$?P79rYNn>p<9P9LPyc{O!a^|P8> z`8CZ=69>gl%&n`O-cl97;lTKT2^iUc6I&`9nY6D7r)u3D z@4mMDl6On;4o6n~Fv8RS-OqZweQbhfamifdlO;(b(FHY!KRfDgnFqei`*ipRuN^+M$J_mm$?MucZDqqn6;0f{@QLncZob1^a^uLe?jC>p zPcwQ)J zN}qW#`*f!kfSEQ#@#1G0X%1ukhe<{@|+PschIDVvcC;M{|XZK{Yom1WDT>(B8lpg2cs{1$o)|X-sm! zoOooAxTqklsHmuzNwy#!rHB);)JZclDyo4ObC{=2EnC@HZdbNuP`l_$+hUc@*r(tK~70Q zc0p!}C)typ)nxA9t%`ndaY%m-=-K6vI}!k(@V0lQW$v)ksEB^ zqR0moXXF%QX5{BH@?4@e46TQP)EEM(Iq66zQ0JLbZ&TC>`I*^81x1CRj!zz9Zppif zI9g?V}TML8*cpGCU9tB42Z6=h~;=H!65a*#|G zgCQRTsf)7;(lc`MGa0oUk_PJCLF$aG)U=}FtlX4ozUhtTPJX7S6N~cl^HMVkQ|jua z9fnAMrDzA|pehvQU@+9y&y>T#V8?)f?3W~z$n4boj2zzWo`yTWfd1?rl%uNs2RzF;Y`6`W(@nV>{Err z;7p#9k(im0T9RE@z)D(HkuLcRS_>4%pn|lFjKboyJkDX>J0*%bsi-79GcPw4nZj(U zo?frg#gN{mL7w8&)SSZHEQ|^1hpcY~p0SE&NM2@s79uCgr>A+Cc@~r@hLRL4d*DSn zl9ICEPmH07iho#IR!MGZT1h51(%+0ysXRMQbnugudXs}p1w~mIC8_B}#Dt1z#pF{= z7^JzWC3)$vmW@^$V-2IVQi(uG&&|lr&xQabN@4;9$5535ihfvbW>!urv~oLrRaG@D zR(4h^ri8rQ{G!~PJR}B+5vefDr8SB=u?V3kC`?Buv-*>(I1Gt5O>qp)!^)vJFPBFF zGitIYqd;*PT$!%85{ojjGBZ_qGPUlS1L%9s8{l4N#O3O*lD#%F9XIz+v z^yV2uX;^MXKAV5sG|RNlrmYRuR^Zenu|(HjTIpBdV+7N+>DFD#^=&X;n2u zYpAB(b+q|;MI|MLxhVk)+MbGbNFlDYi_SArkTNkUW%n41!X;>Frzq!FPD=C zPxXg#Mv4OTI2EAN6lY>~UP*RVRz@zC&T?gDD879Z@sO7-%c94TQau~NUGE%uAGUq7vf|Rtvg5s>qg2I&M z=`;@8%~%HI$%?xW+<9#MpT)TUr1CVyj<{igRg_+kk`W|pV#yNv=chU(1um$|_IIoSIX|0m#QueO?5J&V+`=Xg4VGrC?- zcqKb1a%kH4Q(jn}qJ=x(>*KhjucO+o}X*eSdVRk)n7-QEjd({TTd*mn1EEOR-!v3DUTHlwB2Fvf)5 z_)3q|v{QwT#8`{pBF${7Yaf{Y2+XyNG3iWvMdL~}hB0pruKv=Wxt=B*(5oG;bDA;oYuNG z4qu0GPwOPk=eQs0-UO2=*C23R&$u2Kh_9D^<>ZeVO32jT0p zll4YsfwK#q+YK72?|jCIH*RRHA0^oTrCy&h^5>>UJYP9c(uF{N4J%FHoZQ^cnf3v z9rxZ__k=Lkg7GdrqrNK`XYGY3@uG<*bvyJ#VBS~=~ zFtcM|r;f{L=IxBHv>9JNf-gAo8DCi}>-f5MamjQ{QwYa;#*wrDU&keDnpY$Wssz(>3D?ukyzx+U7h}s^ zh_BnhMuV0qx>nDl4+e7zH4^?T!q=rK`jM9a#(VUP`aWZfcQeM#i}7`Ts-Ce3jL+($ zQK45^0?vCF=jB)6Yj2vq3Z{bdbIw`W&cRafZDf4ouEf{38TtXs;_`C{pWar+c`xJa zdNsc8&D3);TeUM;k4uesK#u0XiQwDB_mauAE7xiN08~(BL&Y zTI)X;+cdBRs~I!2e?O+qn9hE1-N(2x*5hj}hHNk`qx(6!CF{8K;beUGGrsrl!dJ@} zeO+OEIsK4hLRpjYEC8kl7}HZ5@U#9LeD5?$??E%@w%iTj8s$3^X-q^E!oT z_}5yFi3dLy(OR{~@b!MVrd^uC0-|+04UbPYjlpxB^PFLr^|jWoF>73V77oU2!`C2` z5^oOE5O#Qiqf?oqrp(!`uU}(N6=bESkF8fvkcLGt?$5!!f^la(fv=0eox~J5y2tpP z{rt`We&^YKXM*23#P1yDcaHQsNBNzperJZ?neBJx`JIJ+XNlig>UVaV;MaI2!L}my zETweiOt`X=Y3Q;YUt3YJdNTW*VROnH;eJOsSRX9o_Em6xwvq#L2Ofu&CtzA-%-b0A zw_whg%AD&osm$RobM!2C>?n79Snl|w+!5(_bZaIXiW>shO|McmcwxgYES$6cfv?Sz z@HNuGqZENC{muh*Jd2g%+A`j{8dS;gQReWtg zG5s5t)&ZiV97i*RtRjPSLWYG%xq(T!@(p~AsKD3N8kf^a$(d8;gq&Ob&f5^Ddq`Sg zpw{RivuG8QRrxP`y$@N%LJ|Tsz05Jc%-P)!NzN^P=R=V6csog%sUddV$Ykx`#ROh} zVZ~*I%`byf&TZg-miUoUW|pjG+#TP+*Zts*;@sgPFp$v~fq9h#AX{qK!>c8}n#K?V z)-Vyyck$KJhi6WN0X(01@4QX?snctGO@pv{7wP;Z!myTczQQ;!0H=#_hKD2BQp;JF zybJ3;)iWn3=KWw^$C&^19=@Ihb3ex1A)Nc|*yeY<4a+~Fyx^J@?+4($iSeHF0lvoh z@s+|e%-Iz^aGJl{+y0K9`a8W`<=jyf_GVSst}5rdRn8BpoV%;SKC24*s><2z`zken zct{HH9TJk8nf%3{v~iQzoF116O@=a(h!D(}?n_pI`V-Q(}L#qW5??|7U^MV~uf^*g?=a&!zhBLdFO z0q1}~*ua1@J`k1|a1IGLlLFzx1J02F=cs@)Ip9nSIP(Hw1%a@VfU`8<92;gU= zR6CQaooUt1%xY(DwX+DkT1ir2Zb@myn9S^oL5W)HyO@j?IdFM-ycVgAE39m)z>|G& z=3B%S|01)caeiA*iQtDngsA)19Q#eFo@1EXxiw=Vnx}b?rK#IYRq3$dHq( zxAtsstm@T*xFseqmKGkg4(D@=((CK0(%G|!!X%E`D~xTAiqOI?;9Nz;V}=gKY$}~N z93G+N2lWrr+1nWpT^&~`bfw2@ty?4yer}<440w`@8*=Na>r;{kB`2#1n2JV9%J7uo z>}L$&;jQ~lgNaE0L*NgGOoy;vM6{@2tS+Rd1N}|Vnw;E0I(r6c;jfpA`5wQKsA!}K z0G$yY4)0s{LjG+Sq2aZ-ict>%*4Eb71+Ssl`btnIqr0AWfjSziHUqU-j49FzkiG!Y zNbOKr4SujvQCkdPDJ@AIlg>wLX^GZ)0QT|> z9S8jf%PM(MgArBI@UGJEgZktS>4`4Ts_8o_yFk}ZrvW=A==7i=I;YvN7{|sEo)1Nk zZj}=j7@`8mEPC9H3!xs+%6bFNd5+ zUx-@)aj&}2nW^O(Gy`4L(ts)~u$zE=4cG|n3E@#%`k*YhqXxlNpqwGjX6l?hL&H3- zm16xH@YS-%O7Wwbc+83{>9p4FDDiipYa_G|NqFYy&@S4EfIJxov#?`W(R5)=Llt`# z7zIQ0LZtS%H8Mh5NnP)o8JI9=sLtqR9mD-t{-(1Trvg_4#SN9H1|=?IjtX#4Mer?Qre|iAlhCRe^g7m?2d>H_J1}6j!j6R%Id| zDV-hcN1)We=m?uW>yw42?pPc|E`)bt-q5sLA!c&?I7*Dx2t@fF?#hJn!t|1<7x60@ zEebslseR6}O{`ZS?g5!_pP4m>&&HmEVYrKZ3pLzXWq6&Z%RiLU`fzN6)BA&d<>cxo z$avV3!upf#GQ*nXGNbqFhgxaoXkCJJ1`i%DVbe@~Lj`-F9gN##KaH@!L}=wfBNFsB zoC}yg{Zael#wa7Lw;R=xxJ#PDNs>a38qh_11}Ct9aG3_%$VVrgb^fO zWAdTwV>XDTHZ_>I|u24DW!fI0?U3D@I96W`{(=52)v3XtQ)+r>;eNI!D<3fzvy0l+Wg8PB zVf!LJZy|}oz1Z_Gl8cQKMVkfMfAWMIIf;*@j9lFqOLT@Go}e2U@*+Omf#h#J0w?d| z<>&MS^v}@2yoV+vAU1ns7dhb2IGscKN&ZB{Er}Ly$UaCMBEvSotT{saPM^p{+4@S^ z6~bzDxrLwavJ`q-=3TWVE<#(Z(yIWAER|ktY@Bu;`ZX|vi!ZC>519&|L9RS4QG@igz6~awT*zvJZ|3X@K9_tU zNBDuzoX{^7A|bFi==mW1`nDTH&hEwI#ioD!58}DH)l8OtH8TX%!+7x7zL($E*jN*2 zM8Nur*uy22LSqJD;iz(`5R6SMnAME|vCeo%#`t=^x*o=~BVy2=MbquLG~Ey!)zP7S z(nm|KC>HnpN|9hbJXy|GzM=O9#V#J*8Wf9Q{9xJ{7U7E0+!5NjA`rzT6}fB`$7(z; zqE2Yur;p*dkO?A83xE48ZB`{NPA^o6wH!XY%e(nHQ8hC4RpUxr#N8sgzceE)4RKVH z_NopM_|Y;iG^OLx^h?d^j^UfJ!d4RpTi(-5Eanh7SduXsw(zR+sorYLlIrS+1#=l` zDJxA+Ezpu3FgjgBq!OaK&;5 zib{m$51NvwzvhVo?iF2HWAv!BE<#!#C}Wdy?$}cN9IS=S@u^}kL~7qyU?Q|5e%|+E zQgv&!o{)8^t~#@xhqUu$<*u{Dh5Ie9wv?Z2MfD-#6si4< z`^3)RwEhSNSfsYNm)t->jcV;6+=|pbieqyfU!k2L>)&J2pLl)Ueh>!!5@JTkoPDAe zo?w#f6zyQHvqj3s+}jDkh$iTB^%N*tL6N}KO31~^QpDm{y%EJBMw|rJ`k>gjo9dgHcw4$!Slhlp4)g;#`XA1W4OYp#mVSy_jR#63@6RiD=C(n2K zRVqsnwMyLuGq3H1y)Hf*H}H*Ewg)qAXhzM$EcUfNqsE2IAe|8E&-LiykQtRt zxIgI8`jXup$nA104GOt7c#NS$j*n#-tR~gRkl<(0>fNw`6OF0(kX~0&wqD!u5ZNZR z#fMa)2Y~uf&32({xNkdzv)42kB2Q04sK5_K;6LYqe?_WD)E9?mv6VL$TX}fk3i}&P zd_^NJz4@I4b}c6=E&Cy6cx%2Bc@u@wjfsn0Rm=?zOI<833Ug}nArx1HkXu|`jok@r z$qTsT9$}D-O~Rib*@;XzZ)|YSmr6PtBls7oh0AM3uoTE7cC>Gd&@Q8LbY3AgP($|3 zW_1kTqF?Ip^$pwH!M1Q6Zl_WmJ_ie($9NsyJQ54YhK5S$94mEhXxA2@9oF~sxR9Pc z84-JjlBY^A_13H}dHW3mL=@nFsBe!D#Da&GyoFDqqLxoP8C} z&ImH4rt5cy*bdd>WqQ@u3DptW8T#VPcCuA*X7zH3>cSE%b5swq3%s3FTv&}&A%7K! z-}G@U4jBz>x$wIl9eN4CHn9$gE*2{~wg-cM*j_Vj?awbwF@8jvoG;_=HEj?7f<2V! zW4EVp|E8jvy{SQ7+?)nQU$|J{mxfF~q1&(XJ49+T%V<{^9X?qqY--;az6{Se8Y(qC zD5)wnnD&4-IIIGs+{U;3@)Y8gK4B+NU?l)RL&^z`rXm{AtgHz9`MyTT$n0dNHuAV(29Zz z*hRbAY3m9NUx>m`(Ehf^$GB^s7v$8}#p7T=PUxLMv9VPv4N0@XMrd6{r?XpqDwR8Q z2%l|vnNty5m9Yz*Z_tSdkGemWU~_{^%&NblNV2)_M?R}YYG)G%!lkUG?i3i$f|jD}*`0WYFJ?V#~mvLpVcHz9-NXLCysI&S)RtUX<}k2w4R_ zt%YZqY&OV;UxOD-ec|@EF6Q^`w2WhWF%@I<_i@%>Av>djU)~fJkIyvT;HwFb)Q+cH zH6o8Ml6ib&pcrN$%@JB^(4pL-@u>xDqEf?(+42c_m7Q6hs^67)58d`6FDatpek|+B zq@ctE{YCWYU|8O(QGbIoQd^J)tMEgSi;)hONmEfwbvtWtlV@pK)#st^+@(h~s)69JHSp!G$N_4-fxgc%o-FxdZJ zWPQC;5$t(Z&iC`4KSu-)mx*|qLbvDVK=AIO1*GV~WikXenKyr}zs-`$pZnuWhfT7d zGJ^f2FQx3V^ZXzx0gE4%550j4*M}oyj_wQW9JTgIOfX&hM8J{9Qdp<60guqHlzu#H z(i+bG*mt|RkhU9wm6XNr0FU3}aty|YjKM81t=f1kom;BEmhPs7PuE`^7q!Tz-_TEV zW074VKgDb4_xi;TTWPDs&)ZNnQ5Qdbfnj&T7m9}@@JJh`NOk*j4X%)S^4rmDyP9o1 zYm37*CoTq2>e&V~Zbwtu4p}yBMb*AQr%ivafc3`#!E|0~?%2>vntfn&iZX+zJapyr zS4!;ZIV51DZIznU_o_R58d$TN~rpeb-%ky!S%*Uf5 zFk@0fZw#O0K*F%A4tX=YqSDV9PmqbTY9y|-Feqp-cfD-C&Z0e4f3>LCR!O$ucIXK0 zEB$yc4%tRvH>!_UH$C_&>vQ2<_`Q5bKIAckW$4v|JZY~`Yi0I8hFUALrz*bJYYS1v zZilQ<)lbxfo23ueSs_;Pn23tKSW>T+%S9pO9@&1CMf;N@DByJWd68u3%PuD64iLXT zc)vuQYKF-`nx+P1)q@hb$PRg#oIZp*ZIWrWMf=Bm z7Gw9R{FQjcDfA>tmUS|PDjV5#+T*hQMvL~*!Y&ctTP5|QJYIfwhrdL&{gTRNJ?0(- z@ga%H;fpEkf&}WSByyHSZV{qb;VhDED@*yb$YhDjne7sDwIwElVm=j<9b_$+9O+zn z(5hyMxKfu3Y?+3gZahkh=T{}c6@NtVn-ndKd`>d{XwiPAVH{GNrb)hs)O;cO`DKaN zWQBM@Wer<|!1%W$%e|JE%M?bK{V&PVWQF*F`y*0-?pj1@jf$GwSTE(=OFf}_Z*Rj`m4eS6X7WsV#D$ezRnm zGK3dA!^ZgriT+L$3?8gYWMi)h!D=gO#k~@_IA}vn6)Rs~N=&OI<}S)CVH;hDMQSTp zj)@|tHEU1%`=N*aKD7eIxfq0;4hs50}JB9sj zMQi<=4E?p#j(1c0n%P)hEHPaPgC0Qz#CR<+9>NGwY~9Esx}Ed~Ywtp-{8YMG+0YoM4m4Lz6}DX=(4853 zj9&|LR^v6e{csT0Qir1f>?kk;M`z9gf0b zSQ8VPilYwfeSSF3U<7zu9}ctGA)0ZR$7s2%Lea=bOL!wYDiw`PZ8q8#g?g-MiZW8CMPY}E%6dyvnb}Z*@t;rIwhflyWi?s;IY@L}c&Lup0o;W`% zRp9gIE@1LnM^3NQqP=LWfIBJ#Oqnd8o7xu<{QUyaenYl^)6xVyF-O41$d1z| ziStnz0*=GZJk$62XaVDW0-ls9;F(1N9vLIxn|=XbBfCE(y3tvp{R^_^F*<*c&M%|$ z%5>~&LEq_l0$y7p;6Ek{SV{7hk=}fY!_Z10{|WMM0{Q14|2B|+$B}!{yGk^J(fyYT*z=Tj&SJJW>yvb|R5k@7gt%VdiY7Le?J zrVE`L^94+%J{e1WyOH{A4xSZfF|43IIaBnBUf2J|ackmuVb>Ij*;!;ScAvPtFOol} zQ;s>PuTP}D{(}5@f^zHt#p4LYVTx$Ne+l-Mfvlt0ZP8E#CHe5wYaEaag(r;?C($fv1ETM`6KcFAp9)COa8Y>o`l6j z_c6hRL@)7Ly0(Pre=%3Un93(r_=c=I-f@MPr{zk4yvj5Q@+JezLinFJwbE8s$7v*-AV*JKy$#e zRFA%-ygHZcd&>Z&-UmtV(oB(0$I*CbDi!B9Q=Df}d>$qG=TmqM;5nE=vBDqI2|52f zjpqVu(|=ko6*1tnqiK9~rn#||{M|zSE~R?+BGuDms&_9@JzYq4|57CEttGp!CA(*k z-ILQq&3dL%>&5aCkn5kEChDNXZy-D%$FK4T_(o+fetzgY&Bgd5#tXRZd;w$Vyx&A| zUP$nbN}+dakpE2L=MelHf}cb1a|nJ8w+eoyo9nMEc9_DEdBV=0$^?9i;$eitDSsvG zO!ez6%BNh)r%P$gbqC>{RNo?~zAdM<**PgfpM-eGf!kMHCGyfu@R0)1ekXpm&;0*| zl?CbJK1#u*)^K@rxO3K#Gg+2I+*7FY?}X1r?uWevg--T zJ0t8#YsrU*{|Y*fBDkH}SJC-ET9dy<`|0z%O%K%!tUr;X2bE*GtFB9jRXpQ+S zji<5HzK8t!7x6zy{O1$@CZg*>{nAAEH%Z$ZETM5Rh{opxyl;WYmoS@Zs1YyEOK5yc*oDTCgtz4jc}7@5 za`P_`cnSAWeK5izst*$GC%qC*AiZh1LY{C#_|P_pAV;Xdn~OZo~7%o-gK?^ zJ+0Y4xo!cczmwLRuIt5l0<9BXA^BSja2wSj1xc=tV1$?KBIu(!pF>=JACZ69 zKjQJ)P3zsMwBB7p>)kDdVja17jDVB;0(!``$@uYruIzYdxzRzqV^*+Pku<_Nk?ReTQ%`!kQ+$Tg`ORd34uo%j>g zvrH+Ma^?flYlP`k2PK@5BkEJlBmw(S{9`D-2Puv<6sOLF??L!`DE|Fq9+BRy26#H@ zl`xz1CX?RPBxj8U^wRoI!c$4#jWpjI;kz`COZYj(Cy(NuNAvq{)KArP-i!LFn(}Nn z`FRHA=?$d!1B$~6!beb^zDs%9m-rth{4C<{MR`Ao^i8&a9VlKB9#3{9lim~ycovO+ z36n^F5$WGR_ID%u?jZbdvi~cxKc4W<5q=l-%W&eql=A#Mir@Lv-yNtPA5V4g0iu72 z^1O-id>#3X+dVwLkB-xF*?8DVc1|Y#%P3xVlYMij{^I5jpNAhN`dp%)O!SM1zJ};= zkBZYb)4F6G<@H2bmt<3ZuT2+pw~@b(QC)~4KklIUYX!ys5Uoq*QJh{O{?%kx64{kb zc9qaPuqI;z{+_TH+ogr-SdMoITZ_jiTx$n^@c7_FzW>|0DecTK7PsNK0v;(A@U=+- zN`2?jp73OX2PTNPAE0|WbguN?PkYMOQXbw!*Qb*2;`7CNaVhPaNGRods6L%a@N3d@ zyWFd$^Wg-q%@*=*$P9&&FKGV&o-dQf#}gFvlWD!Zlhy${2p%B&9AY1=^{&iT9xn-> zN)_kVRBEGH9A*1E=ZkhD98oOV<5SGx&(tnqBFTR(O~m_ds#krfo{yn={@8dS&qwjP zXM#9yND+2PcwL%kUyviE^KaoWl=5 zIv4)nyo|NS(HehNu2?HPT_)i7bkE>ox@Yh!)eJyhbLF`|Q_wFh5)glKmfw3AQYl~~ z)l?&dUM@%K{}<_-Ncu+7oG0ODbWQURt?iw(wtt<@lSq$?_)f_X@;$W1y_ahC4yxJT z(q7_Ew3qk_?Iq$-gT*W^&6K}=N$#^`Z!FCT-_cxi9>t@c^sOa*ZknU!(cGIwb5uR? z4Wv2hRGOnYrwDt~Q$#;W*dbN4=Tf^7enHnn?V*q(+uP0)HMKnybh7&+(MNHNB)Jbz9D7n6H`1IufYyRhq;DYU+e-RACVf8> z-a&EPNparj=W${=&hva6={Zc-nohd*`;g}HuV^lBBKa#x{=+2y30iBcAo){;{ML(T zynMQ=1O9?2@`Tpv%V}+8gzLx-BYczME8#~JhfS2%5|&V0B;E)moe@et31^Z&M)(%x zuMu{ob_sivAA2cZC2S-*i8n$?XM~bZ!Z50%bySBQr8=~a>Owu$g-@vt0rL7G&&#L| z&7(S$N_A)e)u9~9KO=-*E=THrne>ezef_APBs_t}>15iYlCTSn(~_se-m?+zr*W#_ zb%IWwe|>{Ee~!kff`;}pXw9>lU>{n0x#|2Cf*xvrl=gg1r2L;s`E@+O52$`FrTTga zoxe!W(OgIM>l!+bp!45p4ZV=o(C3q$G=eWsKb4bSobx#A+W9yIp2Oip_cyAOn`wLp zs7_9xyp#6#AbUO{JF3YJiJw7uWBrrkS3+se3u_ke@ht5rUn|ZRqzU`VXixc{H2!nw z9>Oxh`w0I&;Y$dAG3A{Rj-b4fu!QK0@Jym3$Yb>*^^t^ebRSoqFA%Y0wDQy1Mr*y> z$-Y;qe|{oa_t0}j@_Zo4l;;agWS&MjV}#)0&$)D>KG;L+b_p+}K3++ETuOaBiu!mB z%^6ovOunMpa}muMD>6i%q{-{eG2;A?Pry$|-hR^aEA6x1Lu;eX)Mu;ddZ|C1A0qsA zYF|U=zf$a$Qu}E{zlHQf(0=VII*+CE^>qF-*?khV-$3_~jWAvKDf`R_TRYJj;18gY z@Bg;**01P(X#WXf&5AcPG86*e5I<#!HTYP% zR*~ltuD<*n9*^j&L!oS!u$->fcG8@&nw|lX=MoO3YbGQ7o!TWFPWH%scnP1R>)89~ z`gImv+emmV?IRfBBD$YogfG%Km#{mH@2NCLY$m*fM=6ez313FfHJwy0t})7}hIONQ zv}K%#uaEqZ=Z~a`e&|HcxqLB6oIgqR;SHLLextgzgVv7Q=zJFS@7Ho%Q$JS|eiyAF zzoYYKh`*f9C(-#HnyaoRIU7k%648wyx<`qwJI$#dQ~U44*O|_xf3K!#53q5xAy>dY zB?69~Ea1vCZ4krH&k=BMv4D+}1ROzYf;p*TuEzNVj9$V66u&llKI&|Wqo1A^dX~nW zgbUM!oEfyXy`AQ2spkOILp+DW*9Jz2=W=+v5#l)=-fo0=ZilxUVLj#7E)hrLc;;g* zJ6$|GpydfTvqZqVCkr?)LyKpzc&b3ap<@Jm+9%+-G-o|WF}j6fbTY*#mtxd|V)7nc zFN`Mq0*b{(!k2A?4eCU4 z-ltk#PIJNKG#7-?^`f6@#bCnc6aE8=Qw-rFNq!%a|2^@)K=Plb{(6t-GRdFaWak5P zeixlL(|I|q-+I!seM_kS{!aZ{PV(lH-Zb(nu2PI48MlvUY)ZJ0YQGWAqy4(QRCDF| zG@4^1>_vD9GwHmM_UVjp1?|)AqkXznv`<$|`*S^MU(N`n{uN}egt9%6p5fRwPVDo^ z^FB0}5;Ut7vaMCl*I&|p^p6Cexjl{7lnn$A-QcWcwIkws0k^FYFow?itrh2m1VP_I z^c;eoL(p>wdJaL)p{)P1uA=_(_4l?l3py}4sH@zbnCrzk>M7q-1mx}g){1u2Q{E29 z+Y6~3^)%#M))v$tu1AhxjCFo4b4A8_p4e+-GUTUqGR@g1(*Cc6vVAhuu{UU6GkT&} z^GPV%BdE?uDEYplIwIi_I+t)ColEHS3LhohPI*6o?29M;^1PJvN+{`@$?gxxZV9QK z$I(mc(2r>yx{cPMM(Cz~lTg|qpO26*iEKF~MU34nI^UWm)<>2?X zBXr*fLmWD9?vbjgjX|g7+?eAFU1fY;Lv~m+XwdXW3l>Aj*&iB*s<}yKf?b{$4=TH;s3P!KO>LnHqx=U z7~B36&av2Vu+M*jum4*17{TS0rRI z z<`$_-e=OVn3xo0bKN$;|2NLRa$uW?M;e=5|+&hGgCM0{93$j|=? z`NtyD%%1<`e9`-^KmIeZ)yGmEOBoXW89D!3G_r;qtA4%DR{k1k^mG!(^y9(okPluO z?LI3}>cO@245wOsAxi&`9&|$TZ6O?|E=u{l6_1R{d{hr{s~) zidK(j$NF>0Biqezl14%!jh5V?>am-G}GZi1B9_fo2j?v1v=;cXWW;o{0EE7Gy{{||X1?m%^)~C^eJhR`do#|(>VY%wV=R$mpyi6zKXCE^h<2S>xHkprRe0DhI zJF|^_Zbb6(EI(*x1Z0`x9Ze6b?UtDIaS^F-r)+J)`M?8eKW6lI&$S( z(>Kl-h=Vyj$TN?6>h{UelW(mF?orw@u7S9yW1Q@BK7BFv3NEc{-+bEsw?3-PXT1My z3|Sw{7xU^HCuZs@xD+?J(zB3fl~1qdp-)d=S|dB5PnkTo;nFoYkNcSU&9kXMr+yei zo*jMBmU|}8#>JnFg)xu^?iXUu)3XMBdiv&k#+seW8sZ$DNA&NrArG9-XUA$bjFW58 zj)qCZAq$`t%jdp?_lZ>9gzS*)R^q$hCYn)KgbY z&sxvZGY(2r^Wokv^5WpQV$So! zSXi@+rGkt5JkK9($xogQ^*rmy0c+Fer-E_a<9Rlm&ppol=kuX@V#~APe&Af<;x!N# z=hfok`#r{5O-H_b^XP+ql~$~-p)f1P-o;Tl(-)G~- z@6%VXhMQ}i!IZPHFo$}+<=H3})>WQO1v+wB&Bpb^`15?Z_n~Tb>Q8IEnm@+J{aDSP zyKbH@`ca(ZJmybM~Y+O7Gc;(saeS?_uY{**$m)`5S zMz+ov8|#ec*nzn6d~t5}tjqf1{-T|pb6LIK-zUO`d}Z~l0qWET^XRjq-Zx%}=IS|0 zEbM33$?h$mjpj`Ejn9VbY0c%W<@(VY_xW;byqcZ*BmQc3Ztgp>qn^CyVW>c-ICXFN zFfcD1*E*=?FT1xou+Hxt@G#PUw#@c4pq(&gqQ3TLZMuzUNj9 z73j1Ms@V}E^G(dG2_G)yjM#bkY{(~hp}#yE^+Ve{n`+$CKXc_pyP9n_N7;R) z_vSt~^xUD|H%=eSquNo{??STU6QSe2b;tP`t)5e^j|#@gpU>8( zbJyiPD9?sI8ACN2jkB7KoxA=Z zm-WH>TDmdCBID_34gPAZrY)D_2K9%1d@!Ym0GZbvnnVV@|nuvU6DT+3^a- zG&XXOoue@@uUQ>q(E7^i+`7u@lsBJGw~n&&6mxbSKgXet_&9$su7S9SOKXTWT$k?= znM?#E?*Wv3et15xmWVOWt^%FAuKYUolkksq0RJ?`k|$(=#rvQO!nU&9l)n zi*~F{Uo2V+jCmj~x306?RG|0SDc(GN)(_*!v!$ldM5a6$OrxK zx!0#xUTEXfa}B+}`t*!V^TPd}<(7W+{AQkfde$H@`1D!-J{ztxngbc{en;LV&!^18?Hq^j3v)T{ZzBb#$3%8&r$lS;No*?UR+$4`0{M1=U(O7 ztSg_N3dXe_^K9s!@#?%gby`ufa}XUBEuD^E|I>ql$e7ZZI|)4OM9 z-h6V-H8pNGXNp1Od3s%sIjCmiu2;=g@l~_onyx?1 zTi*JLp_)(nVE!smo6QgR4cBG8>lx$bSLf&H6_x&jw!{^uvp1gHNB` z|2`XcfBW?0!97QbJ3&}6;^wnVXY4qK`>Hdx#P7Q=Rg0m5Ib4HRo}I?f z8CyLss`=A;VqWvsU) zdCs$|K&O1LHuLP8&m=GhQ4^TwQI|7L+})Z*fES_K!+0mhjA4Q)OvJ@!xN0_BCr?jq7z=&n*}1s#{BS<`%k#l_-L=R;o-Nm_rdRB& zi##9M^{Uw_zG^mEe~ho1y<(_lL*D6^IrQ;LA3Ph}eM6qzdQ=_bVXe?U&lhd(YFZE$? z*UgKKJZ0~tK3`l<`CxwY{JC|)ex4ouacy4J?6UqCTSxX4*pS1#wOyX`Y*@>@G;h`X zY2A0mmUwBW_fj9%ZhrIPBZlm~G|!jIA=k~G1-hQ*!)K%CX!dWEIHwjD@7u)1eWi8c z^Fyv&4t%i?hx+m9_591~d}j}B^m}wSR@N~6aIJ~BsLQh@*E}l}U!EPYF>d6830<~$qv)7)^c)6T`f^PS%-eHMtz?h=Tq;~xjyKN_cWg!BN?iq-YaxLld} z)bGD^Ul4x<7h7WB`l{0$xMTFGc~d+3&5mh2y5H26KDpK)T&$t&_zF4WgLB4*WX4@S zUH@)8?zqNHUNn{p`s9rl&$tS%fw;(z+R)#4T%4b0Q-MzXkheTL`l7AAKVd(+9_O=8 zd^*OUdz;*5=c=B2z^A8gt<~&Y^2s^b?_gan$OGpy*W7Q!ob{tzaV@QhtPRJhr*Gyc zt7q*@#Kn4KzOs6kBd+JuD^8z2>)&UiT+vUSo_WgCa}CZT4)x{pL(YklXPZy&V&!^1 z8?Hq^j3v)T{ZzBb#$3%8>xI55xOgt)#l>}rFVBX0-v78Z>%!-!f^pqnc{Z#g&Sgxz z@@gVar@73|%W~qIuj?{4pPsRi1MYj`;NHou!?VHVf@cV8!e>{(xbjiWPM=|_*|=+x zgKDJY}}mt^cDDZ zxh1cZvup7T?2H}r%{|u{Tl%cva%;r5w)*Uht=?BTCl8Bq&RWm2;ac1$)offpS)V#^L)Ad=GkQ9;`zWU&z`X{r{pHjCd)}RTjs2SOP{?MPj)X72Xn@JWj`Bs zpMy9zd;iP&;u%6a#z^k6dd}y16La*$PM!K-&V7EU_l;Mgx#XC!kVE#farn+3pB?kT zn7LkOd{$tm^_91_`s|Et_Wbe1sCB4ki_eB@>3++L%k`t@iqDsO4pg&Kf6P-gJGVwV zvZJ2$k%xiYX3rlVh6?PI4?S0Wc5dF;&s&%NH1E~yvi`VcNA~nh4)fM_dCs$8Y~)VQ z3LjQC4|#sLR`#sO^W|dYy4gLb>nU$O8$B6n^u>Izug{BY8Bb^D z(Qa<%(4JhfMi_5LJ{TkUXWXbA zwr;%HJSx0&H*&5|K`uvxTJB!h`eg*SgY(5*s z#JFg$_Z8oIS?oT4^uxWy`Ha6Kf3&Y=$N1^1f{W|vcP-iYTsv~@z8C21TyinDbKM%| z{LZdLJFN-MtA@?DMrY?LFN)3GV@0^E7H4)XHwT@a*BLuXCGL)FY2%&=#G#zK zP*x_7!_}%stE8n21g9z3w>U@r^Tgd=}?9 z;o2)^&U44#~A}-)>t(zcZ_RSaM6A| zF1Luj91Wz2}ZIHobTH=4d|LIgE|*Gj8e?Uj=>c zJzbOIYD;@pN6vXa9^+PiTs`q~zB{J=iNhVQK&Flt@o+D*=2^px z-?deKDj26d_c_<%MZe60j)`0sQ>EfA)*mbX|t@{kFW6B?GS(C00_Nix0=>F1qx*uG7-4E^<`5BLk z@l{|50G1}^LN1hGwv;KX0 z#>;x5u9_Y76LE2^j_jD9YBuhg#9hsn>$>$v+2x8nxc=tGR`b-+`n(@^v~C49ow4JZ zdA8Zw@%f_-=WAW~Y_vAGmQPO~%n|F*r)Qp7FU)lox9&UgOgmkR9A<5~x44elY90G* z>4$4_|EXSEH{XnxlY{aQ`pT$TnwdQ;}Jx{Va^{w3a z^z^NJv$J-@lV|JZeIo39YjTWy=>5dyo-w;IRkKsy)off}nuok~>5sTN>u+vsm9sqG z6|Bp%oOX&!?+N6DwNt@GeVz^HO~l1I;vVw(;TV18>0Q36+0hU8Ml~DP7h|qwOMm3E znvLskZfv=BHGA%F-9tWJIG;5`JD;9$kqh@6;2g~#&m{V%KARJFZdS*&xF%zth)ee~ zpFOg+v||ivtLLE4mVQ`=jEQ{Hm(MQm9Q4`Jr;FcbL#!2Ce74EPPreuv;~`e|`Chx4 zo$e){oy)6F?>;BGx#Aw={?YX-=rg9Qjn*lB`)pkQ%#AyrbIA{RaL2hec^rg`x!3y9 z@fC8$2j`3r$&7Q&3NGf|_0Jd-kFH65c8oPeUfsQ<_RJaU&-Lr(z#XSwVxk|NPv4A# zV_6;j4^qHqqoWzs$NgP@q?pnme_XX~l`r(*QSHU=KcrhpLTz8$U z&dpa=$9bB!td9G02rf5=?wW4A^x^6_H*cOBk2}YW#U0PCL%XbAIpMmlj&ZS$-LVQ} z)*t8ayx^Q#T>L(RG3(jPJ)PCFei%P>^qtkyFXwX)XLauT$E=Qi_1tme;W%T;({a5# z9p~lgiJdqYX9ZVwP1XW=rk+?`J?FZ7D|hOXyzt7-(e<)Aj zlk2c`{by}l9qoyOeif6e=ep#Hak%5|{fv8fFfQhe^`x=UM%QLcKAQ^083QkVrc%M> z^TT{;EO~aEtG*a-o*m<&zX~pLmuIIrp`9-#>bZAVhdw>msAe+}dd;c(Jfi%mo;B># zXP*;@-4{m%JF7j-&)@jFmmlq4ys^B7j197>$bByyVxO{s0rJm=D zPtUs6__)Wj{+W9{0~rVV+)MPyegzlj(2i?#X1>0koSQk>H7RrbB5UhhVyHHsdfoes z*@v%!aotmSHZE7pd6pyUb?^D~*&O+7)Cc|K>B(1~o@;R4L|p32=Z7`GIwe-0-o?uG zd^TK*ei%!hjryr(la0BWFV-4;RdDehm=_na`}gw|sso7}uJ}v!R|b(Ux3l zeN$$AFxG6H=p4q-**ViZJTXVS|M}J+2V93dX7$$93IaVd7+y2R_A&kxrk-#$HY==q?SvsiQ;eGiq@yXTN^4e~^;IiGX6 zPS!^y8YdRU#2otUm}`!AWar*9IFib5P$um9cS; zI2X(t4`qPxoVIY_oXDIj_7ph?#!%?C1RKS;R57{;Ju!HJ!I6`C$#R{<8n} z+I>&!s~P6n7i0EJ=GvXLRXln2}IiPrbUz%gQCjaP6nr&%twwi&Na@2-`n=Q>;? zPtRC&ujSd$M>QMbpdX(7c|OROTa#I=s^eP3OZz-uwBdfQW~2G3W=B81H7Xca%*+An zgZQ&C`|hVcJMJ5D)ES?;e;Gf0kyCP8Erts8dLHH3X$+mQEjA zck|+M{jdh|>=={QNHsh4$GldvbI+cR>~!6{*vM`6KG_i;%x|7Qw@%p4v#UU-d9P-d z^~cycvZrryn76jebDj-rnV0fc&7anNXKaa?c6t{3xOVfK7auWX?=5-0Tn@Qz_AJo# zG#@@2JtwpOR^Ppk5f{&E-8Vizx1W_euw79&+&;l zI>zJLl2ccvo@Xl8tHs6d7Txdo-ErD-E#l0M)2BN|JN-VHF{^Km(+~N`juS(6obhsu zb9{RGV~zWC%$M$&>{|56`;xp1BWL2d=%wzNvIT*Sw?RL{PrcmB zKa5q!xxTA&$6Y_<&(*neTpeqKv8{m1t$&@XdU9J$&-q+K_k(Y~PtUceO#j=d9z67{et70<5~|F=d6QkD_lB8AGD#4Hq>u`i*vWe zwKgu=aE{t_X5EpnXFO};+A`{M4W5InqzURgW(;u!t#VvcF2B{su1ed#}D_0yH``m_V%ej=ZW2)!zqkSIbd*fnUI!0Oh+&bDP z2JQ2f3O&QY#ZR<2a0o?NM1$@IyK>RhheG3}Ep?Yms* z*xrtwTi|tpt8oGGUqY|m8sW0*U&!gwBOl%!MY?jd<>qC4Dh)?fr1kKU88 zM$kTOweO3Se#sww(U!hkF8&UgF{`eEKG)9Ljl`Jps@Q#Yw5j0Yn!Jb)4_VXjz%pIeZPWqq8>p&S9DzAT&*M9PP4(D!$OQcQ3wx_%p-?Jm~ zS}*qV@wExp-qhbFwqNtL1=l2w-6><=$*V+YFgk^rdu8lrd0kR`4wKjIqrdF?CKIBPLJT3!$4YtcI8-2WSSZgR^pZ1a zmh_jEekaa~|64g&5xGAcmk-Y>7;m2{756Y-SEqc8$dAkGtBiV0jvg=aQ}X(kyp{z2 z+Va{auhZmJPV99!=OnRvR$k@oX>Sw@+`FK~-3+fs%j-q*`UGFs=jf@NvmtwD$m|#7 zwYyja@`{hYpvB!1ugA&jrSkeTU%TNNLCtwG?{#_YC3+*To69TinXoxkUPHbviE9kU zZju?F%j=?|UrAoKmRH>WVRMeWKE&60ToX7}^*;6g+&;KM5dO$lt)ljBtoOOAi2u44 z=Bs%bpW^hAk93ypf)AqR!PCfV80yis%b;;qd;?-F#R*n^J5o=!;(L*La-{yZRj&}u z{?Mvd(AghH>S*?7ky>YeY1Mg6)6sdLguU0)In*E1W57F5*;{@1{ zXm(eK05(Kt&kK3pwtdG|_5cYzL`k8vEFaMpfZTP=c=Q%#Z!CL#IAQmFEf0Mm%)fhO z!oCA{YqKMN!$>##xnnzs@f+W<-}==y(j4`B%Km*b!aE z1+#UT_qoijvJAU(yUZ-0X2>Dxx(H?aN-zr! zuA6!E+LLSAdn{a26P{Cd?6j|YZN-=Hth%eG9alpCs8To`{ZrYWRtir?|1|cGD1ow> z!cqI;n7!$sW2ZK5g=^Eb>2cWkbqrx;EFz#N76P@71vN}TQ3j|>0qWv9b77siAV#z< zR6uJHElETdCy0h1{9ZL%5mk7h1w>Tg1r`udMUh`7k*^155;?^}k#7MHpkPA@7#+%p z{02mRU7fk6&RkVzu84!*658NsHyzg{!H3r%N=?UAHhM|N6*l^g({ZDK8i_>&6vaZI zD)0a-+X@zRC!Er$oLBoJr&q z3q`&!JRsol5->WH5&46N{Qf#~U!A$9&fFabKMC64G&ddhC&7pJAxcfhJvMqt$K5vi zj??jwfSQa&1Qf+WpxWU9Sf-$nEl(Mso&c!F>dYf`=HVF85l{iGla9v{L~c4Bv4A8U z4_iP^I-Zosr^1;;PO(trC&L3GKN^ihP8pHEh{&I>GtbtUr{l;^fhxVPpHCtWpGAns zg>3AnlhA`tcsdCOFa0wsLg$;q2@hvj|2avj_Y7K(+i+zk(aaEm}dhcdAI2UtF+Gyjf( zgcwf)`5*z}=H%aVhvOr`aSyx;4vK|vJOK{~|3L{K9m>G*6>xk}XFjVlpTtm}getwm zzeu2jpE)`CWbUwhEm)p{d%;4n5SCZr0T7-;BYU1Qu>1fl-_@CKVj!`<7$_Li;L)-iZ4UeMscknE_ z*3|jBhQHga99wf-Dd@uIsu`tCH-YbuU>Veu(x*k2Qu2TnO_XEr*Mx@fXY}!aCa2tB zEJbG@(^;1inESd{&0xL`!P+(JQTGXSVND5^_POmZ;pkJ03P%(Rar6T`!2OqKgd@t} zsJ1lR%vUnqOZpi4qqY0VHb0|D6Et7RK77`kS_*nO1pNZbVEzn2y%K`lGKqZ19j!b3 zW%>D)zIyrj`3<^o{)8X=kpy7s3gP$e9&tfIhr(_n1DXO)m zJ#8~Tnlwd=0TQ1^SVK!W6!n5-uw*HHx-FGZ6h;%JhWc2Zg`-7094$a+OZhok5V~;5 zgrmN~(Lxv%jwlx5XlZx=*^8kOjwpkp25?j=nSL=r%UHX9wy8stCa7ew9m^VOatJEH zGFUc4P*XyXTSJi#;isR6pL+Ug^7GRGUASz*PowbDh*9B(Vj+H3fCunXMkD-C20w$q z&%lxyP%`~viUwQLA+}i&O`4*CfTT4v#Gz;C<>fLQxn^lo}dfc@~cPdpKH| z&W89oS_QgraKh0F!qHHS3P%(RakMTxfTPvX2uGB`(Q4pm)sk5yCTKltx4vzLqe&CA zs>LQXw1z{_2CxiTGX$-X5aiZSVz)-RcLV}7=_cK@)=HfYlPtPea|KpQ*!Yzxa^qs%$Ial%g+O_Ty! z*OE+vsz1N$oozI|Z|rAmJLtlV62>+Z#ffjO~m@7^4iv{tm`AkLlXg z8trDA@o3U?ZSIuQNQbW7VHs?hp=)G9ms?JekIu8T2c3`fvo!&_aLa_PErhK-F)D0P zEX39ncmP}bpb@qxgRSks*65PiCMN7aYj==s4n~tEY_wBfJ2`|M0?S~>%o)B@LRc70 zl=|9cZtLq%df&;<*kRCxJ0^_nAdDT3QDKZ?A;wOC2QYRN8exnw7#j=5c8Tda(Hfm( zo0HL`>DtAquiYHFPJv~xYlg1f61v>_ihOjwzD}j{-TZ8w23@#o!qzxp>vW6?TNDei zbrC#(t#i-_Ta>}pK45FFlG!sR>|$$oiES=LlO}90r@kgTgk1*9U{dCMpPUdDMiZsJ z_MF@Lx}4r8`x(0ex^Pm$*uKKpl^7MqC>CPuW_SQ&*P;=|D1)(sz}S?Su3N0pt+u%h zO`5JLPJJEf&~-a3gF`ZO9h%VP)>q`C^YwKHogeCF>rUvxLlU+Q7PjufsIWz`5L++9 z1K4^Bjj%--Y@G?V&M2AFO6HW3IVq;?6=;JKOU{StXC&Ce)1n&Vhw7(91oA`mlhD@> z)&EuPL-n%+)azJ8Kv66NYBoFo)LViD9m)VT1E9_?nR83#>=@ApPywy;vElg%A~&1o zT0qQZc(w&3Z$jA2KJFQ4LGY@?S?apz3O5PZkc1>cgy-*j9f(0;^H0*zuJXx+LB zwBHpPWk9r3X^7*}_wfZ0jPjR`I{Dc4(Al9X#LEGH?qNaXXvnM6*pP~?4V zM@=MGBW|AF_h(@N>|fk36$^=Cnpcj9hN5r%OJQHEEEf2X@v(sSXm&T zLm60}1D0n>=BXIS8W>Llc_snk=H#il!|}Y}SQFj_2gO1-HiHL*zrKWz4rSnY9XMVs znU_oE#Td%w)^vnz{*ESn|9#bFMLzR+)4Bg{0n6ZxQo1tVOjrn`iL%9BPG|^UL_hnv z*p_tmrvH9B61wn>AOOm=NTaN#sLL&v!lijG?a&{rrrDF8mk z#X|h-3lHFDcQnEeW$^Pg`1!JAJ};S1V~QqO)5*5k4^5h)F9Av4vVZ4Lv_C9^Z%gT& z^j$(x7)_KK`rPs?9DVBH=m0wV&d<>l=)!Lkj=m9&4#cQ%M6nP@N5ca+IvkB~L>V0Y z29ACynV({Ujem?{G5bQ;fG=&e$Imj@N)(l;fFH#nXi7h>0WQT*6U~U=UclAY%>E*nxF3V zNdfh&Prkgk5SBr0efkjUS)Y7)5lxf=>Ix_L>k__Hzt8JuJ{Qq@&w7wN=eHRbLl@T8 z$KPi3s3*`%Fe;2uEX3G#@Bl|wpb^F>gRzCd*n%-#*IT0-Y;z-;G+hf?q*6|O9J+3T zWzaiASD%C~x11s$ooDN2I`89W>lWz3-U(Za2wS&eRM?_eh^?9M0JiQ#BWzIyTT6qj zrRq)Jn6Ue;-2=9H5KWq}rJVYza|n9~mO;Pz^Z`|u5Ee!grM~*kZGAmV?{$90{s~>! zFJWvMVeAo%3S$%tG4=vHfU&302xFANSQ8j)jOlvO8ogwjm(ir@YIN$W#i8pJSO(1* zx>^#t-1>@qbiTe`rSld)TdzSEHYaQa!q)2;6}BiAVymf}u=O`I!WLz)wI|rxquz|K zH@nuGvGrz`n7IH3!Cv*js`d6QQ)yuYwnxH1I6kU0z7^axqLJ^+$JSpx^%9)?Qyarw zFnlR*0^juV{N`YhPC4SF8Q8YPeTDMJB4IfvBkQhHQ?oWlhfNe#mV>dd zLa`7ltHA?S9fU?$p$t|I0V@a9n<@2X|9UgI-t1d%_Kt~J9X7#X^}$vVF#(A=$RTEm zL(KjTF_RNw_D#BbSLI0FGso<#g{8y8=3vK;BmKau0 z^jC(*3$87(h~T1F2-kRc0Ir<{4my;9>wMt4wBB4?Z!WAi7sQ};hZg(9f*L?jm-<0n zjNxhat{h%ikNV$AFkOJ*Z+hWo9pkuMaO?rUf`eiq9Mj+d;U6gBqeB@uZU&AU>&^A` z=GuC5b-lSVhH@kff?G3t`o;uJcs)4Rk9V%MIg*ceu1@OpN}HCPJ)N%CW3gU%>m2oJ zN0NHIMff-l#=-~1LVTPJ51`>>G*YjW!Nhty~8Qc+bk1KV($|m=fbf7p;!pW)$jly7fSr-PzI1E0OYZH^GLmUxZXTiZ|;w= zTmyqNmd6q-;UfrCKO%bA0rQ{(=KeXrJSkwVg=Yanu@IQM;Q<(K5)9~22AG!s=7oCm zT)law-aHi}384j0Co3;FNSa93Bw<0}?(u zl!4Z!+JBj-n?IL-iu+(f;L@MANpa;PGE%ZJ4N;096&x6AaB620HIh2$j9)2_}`WI z(V+|=-vh|E_2%n(^JTsHyxx2oWBCLI!H@O9@Tj!papv0uPWUxq)uZoAi${*W&y%C? zQwyh4N8cA%FZ^+iqtA{cN8b;^$Coe`J}4IA;}3WM4d0`YqmMH9_zQgeQEz^$H^0=I zpJFopgce*mo9vH-3Aa9fvqZ?z_luL*pDYv3(O1*J_5Xrn0Yb45kiOjo$bx7D2xS22 z)iB)jY%o0<%)AYzTZ5UWLEmsM34>t4hM>(&Y|n<|jdPENB(d|Num3EgTSNSuIuC~P zpHtKKv}LefxL`x}3Du4yiCsYW=m%rrgJK~*2EYS|ZA2q{PzE1MfRDu*OrHj`NP}4@ zCc{7ruAIa!mN4NawvQ!361#{cLLOEYvP?LM?JGbA!m$9MSO~~!@Bkn~Bz|-#14s!# z`ZbuP8_ZHMiq)YC8XD4XJ^Cd;!le7p2D5C;#O4?WMK+(y^Vu^sC&bKgi5hcsE5J>LfuayM29j$T?e7A)nL|WFssMW9%fAsw@o`5 z?xf@ouGfmv#y^%_zaja|@(5T4>owp}&H^3G0$o1=8b%YjS;I9Fq~Yr5HOiqWnkY1F=Fqf>b1-k@q3mor9_6R( z9O%N431wRfW#?j4D5F@2vMb;LlwF8MD5DI@wg+XS8_YH_Syx)St88;MnlxFXEl&Ah zcPEFeYhW4dn5n6q60+RQ6Zw#v*ft)1uBES?{QO)8UASYy&kn-R^%xa?C>G);ga`0* z3mV~vGWgjY{Os0X#x32^*T@OGPPDtq5L+E-Cqe2(OLUg?g51{K+G(s0;&~-ZKI<>)^++a>@FvrJ? zy=SfeWt;cWq!~LEsQ6sKgX&C&v46udnBI_ns$|AKhy7}e!6~vF1#e6>tdnnSBwf> z6bsR{$h<;V4>Up-WzcmK=(?f7T-RW(X)ssCjPG)PZWlKO8-jYyuvryI-qe2$FSo)XA41ow4qY#M=o(4CZ~N&Q1zq@7Lf4x@*H#!6x+oT+ zYZrI`U8B(mU6euBC!p)22J>NqncZOCj~N?dt;gDC9GWy^9|4tC*yj#oyTLN}tRekf z$L9%SVKh-H>_bbtP&V74?0pYqyVLRKe#-WMF8nN^>{Fp^0!D>0iiIdU5FS9;K4^q8 z%Ao9Yd?5CHgZZ|>d>!+3kTpHnHiw`|^YuL_!1p@G)=Vn}KRbLK2Fu{53|~Jde7O}C z`4GCkZHT`c`Wn{y-H^T!YNy+u{cIfpUHDVN){ny0RE!E+6brF+8a#llW6%g&l)=_~ zjri-9M$@&?bZInyHJCqQ&Q7-z&almNG-=MdHzqaK6Tfky|3>#rSO&F?=`RU;HYT6e zMH8jQy245HXD(rvM)|Z(KBW4~skc8o^>!8)>B&!l=6ox8HgsWaWBgXKMDAMzdg}erS1>wZ7Um*Puz$x2Q!fhuV@3eb>S= z=$oN$$%H<)>{gSfV zR5#_LbkO7{>M9NF>08*YoBcxCUDa(PBa?Hrf*60=6yox5x zNZF~Rfes_D!7?xzMg}H~xRn(7U?s(byw3Rp{e;YdE;I=t1B8$_Fe-#lEJVnM@Bl*I zMI(ez1|h3}kd+$EkeHMISi6sG^D&wm5<=D%LjJ_45JIsKA-l{cgp5Wb zgir<{JAjbw8qKzi<{yn_tC*QF&<3L#?FX1E@dM255_sXZQKj&2occE=*=Y7?G~?so zkAgOxm%WnU!#$n6?2)7($;stSJ~N7Q%QoJOJ7$0u3F?z<3Za zPH8mzH=4;Yz;mDicqcnk5`b=Y_P0>vK0Z0=N7*@8B0m?-Byx&{BEJhEClp5cmTfV1Rpw-0rY$TJ-5-E-Du8?A---+ zXW8ZrH0c||xd40=-}@X@3NCbR3~$0Rn9-O%UM_Uli6+Xe@@z|kRPdQeKYo^Yi_R|e z-zDCLE}W6vB`y$--odDFM6nP@pTGmC`8OK5OHc+!SAwI<8_lILL7!T?&usHKnlwR| zM=9p-q+H_=^aU(~t1|>$lMv+Y@W_YobE$`)FX`(VKR;hV7haw4bCvM(HAaOWiiP<3 z10KN74`_rR%HZdA@N;XUxw+BY7*q78HT}yrH9fKv-3mzhdBa@}MO|PS+}W5u1n){H z3ZscqLpLY9gf}MrxQ6DTv%CBpb%idxGvVkC;iwx%g(HfEIO+`#;Anm{!VzU~^Z+=T z*=X*K3F>3*7PZY{Xwo$_)8dhLdk;GVEe^}zp$tI}Cj_}Q6#0-Ey4STj)=v&{fBX_lS^ zDlMaz9F_*cGI+5Ow<>!tU5!sVFC{F6(L^burxR+zC!IIKk0;}CNe!aom;98i0A2WE zLfH#K*uqeaEt)iAp8}Ou*jEl?qhT3**@!0vr^3EU z7z?9`Qeht_)P(k8qIexUwc^73AWi2O`5NtEF`J0-yOat!ZP?R!`JT#Uv7m(KBU5aaOnEZ zL)TvP`@5g6y`c+#OX&Jl=-LOPLKnrkrR#P6K=hILX#q3`qY=6&gRUc*hMU8i%%M%@ z;3jimlYXwpAD{`^nrxY@#e?YZrsT8DLz`@U@uB!&^dI5_^2}0rAo}`S7FB;BdTJA6 zIU0)yD2jzZoemFhbi80ehcZAN2T;c}nWLJ_v>4GDPyww)v>p*1lOS>vd6Wf2RN*uW z$obiX<0bOxa3+ycEEM@A@PL5hpRS>d$fqOn)0@nxP3Gh#b7CAkf3han(@n?eN$}yR zh*IC9oNS|)bew3TKX%#?9sFMRnF5Nxb|auD76KLhaLhG=1?VUP)CB-_UXwYe$($7< zx|N8gyXiPDLFA_691BR&ah3(-q+^Ceew#*4u~6g>!vg{iC17+YBl4>d`4vs(vL1?|1q;PO zSU!UXK=?o)phFp0?gy6pn#?^hkk2um26A5l#7)6HbBE&r!SMyW3l55faQp%f2>%-i zA05iT@i=fi+GPIOWFCs4{0dcib3d9u3IFNj|tFAZ|`(%^i++1V=Nx3l55fa14P5guk4Gj}B$v_z*Z|H<|aF%zH7E6|Lz? zwpkfX`nhzr&5HaP;KxnLm(Q!fGWe(|eOi2+unUHDN`{3Y{$gri{?6^?=*uSac}&o7Yqx=IHbj#q z=u3<3*qVn*!FLWp8^JR8Hbc;N2|;d|L_Xw>_PK|jjp^$vJtm)3Ssh~+y)FrS_Bm7g+d4r^e_^UZV z_aJ?`%^M^S`O!qFp}(9O`oqJK{IJfvfwzYELpfphAg-Zq0ilh>sBlEF5J%CE;p_oN z!cp{NI17TKUV-Tu=v$ddFu;P7ZL=SmG(o*U5Z}PCh8A%M+8>s|!Wn`VNeFUlDDojS z)D!-)drW=^XAwU?@WU)yN^>+xGfq6kW zLs0*OAh(7hAHq+gho1}StG}P0i=Ye32|q2u&&3!Oekc~==Q?-*KbNBsekg;VA>e0) zz$_p0bG^08{q>s_fJZ-&TG`=8e*I>pAblfSIpHUaCQ1PZ(Zc)Z&vm* zCO?0(Qo`7Z!q~0AA&gNh#Mph7i93ZTP)8Yztq#V9#dPsEaiF{3HV>dlm(wt(oYr*c zdJvYu8X3CQOz3jUDe}>IwjQGMHT`VyXK}(c61G}}E&d>mutl*DThGA*hrF!k)Kw(J$rjw{X&g4R`8m6Nj*uU>R(jIm0(e2n(Z$QeW%MZGF8=@0<7; zdj-01CPt2Y3KmU!oDVD1)sX zz}9ww*)}HZM{DhOY4mU2c6vK004t^V9iwKU=+^3wKM{+Ev(E0HeYd#X@YgzynCCLnHM?8EhQ^ zwhj->p@BI#FbBr8m7xu$1n!6G3HI>NsK(?&^@u?EP#t~!P`&D3W=$1P1F(pIqF4yj zP>qe_Cs|Wy?ly0 zXFBHiQ9Qp9 z@DhZmpXFYZgg)o9;G91YeWhTT0QZ80Vj(OCzyl!cEfCP53@q0H%Qb>!u$E|_6IWRZIP>zNwT}`(pP{Ny? zoZL8fSnd!k$H2W{p;!pZba()SlLP`fl!4_QV7WUmcg8@@#CRIW-3bskCwI;rj(Y{i zS@146C>FwTIXocz3nYAWC6Ny*3QhX{`;g6wd~W!dbN{^> zmcgTV|KJ`Dk0mUG(L{M%c_5)7oQZz+GmUHL>@olSmOr)?KAPNb9}$kO!>DjXu@Fah z!UL#@e}aoLIC>5oJrkIxVuJ3nc6Zx`KgE?M=oyPm-mkyt5X2wX3SP(%^kPDgTPBeY zIX$29@N+MHz3AuXKIp<15`LZ+er94+_@P*cpC{n~{5*t4?h=&2&)eYV&A`kG%xf`4 zPg&EaZSxG8G(~R$lD=hs&!Om9SO)LnJ%U?9?V{Qa)rJwHd! zLl?fAaP*FF^a4hOBZ`GMdIuiB(Q9agBg)|DBXIO#U}nbz@h7=p_nvM3g(gkVhZdXE z(5DVT@53_qBty`r2|;cRMLvX|*&crWO<$k-`I!w}_({Ug$HLDC7!`gf7UJg{cmVEC z(Fi}3!OwT#=bONM74!40wfoLC{K2j?Ki>e47SN9lKR>`S_#v~$eoXiYqlr>LUs;k# zQ1$z~e&+Kdz5nQE>?i2L9}>pC7sh_Zs4zyc5M%Rn7sh^vBVmj(82cTJ{TkEN)f#oP zO?NbDx_))a=`V+_d0`p+nW5{igf6$7A|IV+Yd$*v%guy1 z=H!cwXrk0tH#otE|D9)SNqV2Z8LZFwZP`-Lg*}_&Z#rt53G{Cm6~-tQVyqb+;HVyr zFh&`SEds_Cis@>xMrGUdN0X*&A&XRwt3@5UmV;%`Cqvhw30-b|MLs&u7JuX|Sk%uJ zf8s6dld#oW*ouFjjbb6T_JUuqH5QGqMHy^u3%35zY_@7PBb&_@&1OW*9DkxJ*seKf zYPN5gHsBwJ{Uc!@+$yTHY4~%ukr9o2XTC)<{}nI)fk!w3!%y(9;J)tc4@6JKs^NCc z*`MFDBkQiCKM*}ySlJK8QbQCAu`&%Fz{){rgcZtQWeiwpYc@MKn;o0Y_Aw>=MJh06 z`PhVfv?YAF6|u9WgB20(Xz3s);r5mfk`n#&wKW8Qae6L?XDfBHv1cVmtoOxpE*)%N0QX; zEsR_aV_}41Ax3V62QYFC8exPo7&#b>9N26QXg2#bn@KSvw?Ugu?STm$;Q;`v@3Hr@ zd@#56-=j%pCs{h2%pM{*ZiipNL9q~yhu{G?><>+$Lm4=Z1dgfAroGu57K3;gsx*kH z2?)17+r1bLn*+m9g5jTvfnp&HFIfyvNa(;o85m9nhEto($<5}(W^;VAIW|V}G7N(0 z&B0*z@HsUB6P}D%`548+=R}J}K8HF!snBCBoSefa{i~m^W4&ko6XtH=FFIkPoM=?&arcT!i1aFb1e~a?40c! zJ7-!ZoZ`GtfP4za0)%2AAYJj#c>#n!?j%4c1IV=ia&@!0ve{hTY%Xm!7spt-!63N4 zIoRAy?9~aJ@Jht0iM`z7k;Gn_B=%wpr&EdTf%U@c=SZv_NfLXV@KFn6;e%o!K9+z7 z@Ub8o;e#^xxC4CL)@*KRHa9h!8)7o}Q%>N@N$hP26K-N}u|!B>Z*mfQgJr@=?41H+ zNjMfD6bk_7^zl9{Zy)Vh_JxTX&3$9aX9*FS5$L2`09ZAyssIap9 zLJB&R!On|d=lN#yY_oZ~**w{79*?P!A7OeV;$;i+@_fRJo9SmQEt2V{olHOJ^dGmx zI9Y#5aPili1Q*3ZxJFxC{4pjeU&_GsE^xiwY~E}(vzpCo&E}OD*LE;KQP>I=TyOhv zz3JeZAx}uuJ;7j_E+k)(J(7BUWmv5-Nr5E)0p z12{MojU<^e$oL9me9>$^iE`U(yZ!xtkX1*5Fy~T8G(N8sQhe5DVOZv^`{4G5D<=tag z+mh_M`Ow#YTh+ZKezVyX!})JE)6aW%W4&;pmh9V1JCdYsLE$5WvG75$5Fh-pAkc6> z8c7{x@X;51EZ$-kZ85!D%)&7lPe2QAKi|^V@_v54gDxDH@MDCZ?=dR;P%OkxZS+F|XoMfi;Ac4a zS+B*c(_+?YF>Ayu^|aRW+ol(qG)wCNm6p*)4oeHbGT5*s{l00VgrzW=C}p&crCMlO z%h^b4cqm(tjyLjCwh(mTh6!aG2xSXnR4AiZh_X6(K&dQ&Mku2U%0_~+En3Wo7PDE* zSIL^z+ol0cny)P^RH>@19ljc28Elo|YwLtBx2hr^Le~g~uFX7jEla;!`{`>l&Ar8OOCn^9=ed`+}arNSmTd~F5GVBZX1lM=q% z3X6OQT@xI-cK6V=HT_QV)AbMN!hI9E_7S?a!Klzhu@GJ3-~n{)fJW$|47%Du*I_N@ zkQQ@LishgjN$vV$DT zrg$jZla8nPDVqpgI5nZ{2%&5*j0$BG3sH6qJb;A5(FkRfLD@;5?1UC`T#Gp-=IdB% zdYo;JN0a931PfIv>{N%Z6JQyf(t=OD?W4nJK02K0@D)uIj*fFUI>y7%iF9_VpQDqY z3r|TnI$1b68Kc4x#X=mN4-eqz3^c+KWpH#JI69}roYi8c#~fW?O=sBVLNsZP&T%-J z;c#>jEQ1SL@D+!{(F}*9Xrgd*mc!9>4@Vc%*$h8Nmp~U@kZ^RqaC9j~g(HfEI11qb z9NmmYIHC-W?gB@5w3ypk%q=bErkJLCto6ONxera6raOR2x86MtO*3H`ge~dE@OvDZ zqKUHgZnInqWw$t#-Q=O{emcI#PuT;|g<(S3-9p)e7!}GW7NYD~cmQSg2hq@>49Xq> zWe>NQ2V2bjF<;MF)8}pT0-7{m4_m0R^&WTldJ&evV;R04Pxx{V_sECP^`Jx7{T{kr zqTk2;biE8+_*g>Mqe9m!7!|rG7NTo5Jb)$sTAEZCWzh8+=z68aywqY|Xfe;Vm}g?r zKClx$w9S9eq)B@Pz_iHTa7g?2KnP> zUs&=QI6@?&G)`$>@>8~ZLHo{;@HNg-B^c&?u>8&`3#9MoIk&QhtsZS=Jgg z*(N}fuB4xxO8UcLq#2gM?-@q^NEmS|De{pbq=obU@DsvcMGJpV2>DG2;jf`dl~621 z$V%`4LiqD&LI`CLGH-df=~g!Ll=Y*vm8~6rat!7}(WE))R!*v7M24G<+5omo2Ig9jOiE; zZO~A*n06+nvV*BPDi40q-V_nTuRHMPJ%7pH_%tSio*zM#k6rEWybcg_{IxMbN3jsP zDewSv{6#Q9M;Yi=1iHaxGpK9^#?TIg3a~A-T?lP(0?pmjgDePUE*zNjqpveolE@E& zGl`sHp~#Pc2Sk3D1dI-4M7|~>Z!MeE%4XHFStSnsSZLFEX-$F;S3{IM+?khElN2O* zStS|t!`*2+Lq(IbD*Y63}5ZQO?xO5~SfKNk2Yc@1e6%{*&ci=)#f7$+D$z zbRR~ABZ`GMdK?}=&4XxU?@OgWwT98&=c0~N!vVyCQZ<2i${*wog9LmhGnp0 zhM=7ig50Wze8`^N#>3Au^tF?ppJ$;9cTD)%LHKzNqrwlxLj1f558&q|G{O&M@UuJk z*{y8GmCcx#qPMK++qQWJO`4+J07+|TPluv+VHr#)r#H@?2}NNvQEF&h!b>Blwn z9-Zy!=jdP1g%c8v_7INV$Ea{bu@FaJ!UH(^2#s(=8652gjwY4OJ~2UGS-Y=o^9`Cb zL6a;Vsi7$jLEphLIG~Ip$DS1nO!w@oiJX=#b>nZ5q*}Sv(~|TJumTnC`IH1k2!z z42#nf7NbK-Zq4e0B%YLzctYn%EOWK#eiHjb7oL%jc)F0d97csiiiJpA6&^t1AT&ZE zWsrCYNW7?QW|YnOWpi%K<1lNznr&7`ljiXvfYoZe+~IKzSO%A6c)UE}G1Q5y#u*7? z;rR)X=O)9RYIL4*^c&%Ixaj46I@g6Ryey&fQlWD_j0&9;3(@&^cmSOnq7gbNgU%a4 z=k;ZCZP{EMbGd~z-O@HA(WJS&KElhIyv5;iD_90MXSlp2;nJ;1^}(9FHlgzBxutSj zu6c`}%F)n;Hz!oyBvfvPQK6FJ+)_EKJfe#k(WRLb8qinnKio9;H%!Z@bIu?#S!3Ue^ylabqq>$wJp|sC>mSzlzk1rVddpO4simZ1 z!sYs7)~bX1GhvgL#Qy>2`(8EeN8y&TDcvnDM#1iVXHK23Yfbwx9N$C~@j9crl`(r% z*AZP-44bgRanTBOtFG7|e}5psMlm-G9n!z1jNuVoR${~}OYU!|si|2D{|A>|l<?mQ z*JlY^Q>cuW9?@kjsZ>@?6|K~b!`4)#4kwyT zI7dn=s?@bOx*5QVdIY?!-9KE#SE*|Y+Z*Jt-BG1t9aJi2vr_+#W!CK5@vA%|zMf)UV9L-*6gkQ>t_2vP?&5Z-h^#k-H(#aSPuOATq8E?ez zbptHF)5-6R1C(EDh=6Ch{N6HvOYH|w5;MgPVs5_~0BaW9zIWHHd(|v7VxHE%Bf4xm zqRTc6bz6kFaNBURV4LaH7KJ%F?A3Pcv>Wh$4n3kzdkH^j#Q*r0olS#|opz@TPiUSx z?dD$Lf^AcK4;qXM_kry@p0#uH(bK+Z8g%s9S2Pab?SzTyS{mBB4T0=1Y>~E_vUGQ{ zeuwsH6E=5t9rLGlqj27CKsdMCD8II&jPe5xzc0f(L!7l-;py7|KhXa|6f z8gkONTMLSe67amSoS?uhW@Zyus1#o9|L?qV>ksY=Bh%V!~qjtxR z`WtrCl5J**HnW&+sy%|=wwZ~YQq%rtZyZ?Tx5a_=D9+U97QvohqV4E)_S*_qxR~rb z?D-oSHpT02O`8VuZ95a1n)cd0b2Tqql1}TEjt+9&Z(Zc1W+20sCgwc_GrI*&k-bNB z*^8L>2Ie|oUPjUG6E4$s^xAJPCmUzAhBg}QTW)N#XERRUnWdUxC9XfIyeyl^<)*fp zAZT+{`<0ui+P~ZaRXL?PpxmFTDdpv$8jw;QST_byTSqNh|7twcDi?Rlv?Xt;o3?wynr8JKb85PjVB@Xhm7D)3+7LXJ^S)q?nzhT9HV0{?>|gv9ok5 zlETh1t)QNreyt#wow`=gxGAcU)Rl#}_UUACo>5)O+)xE}ar@bD0GDT>;YJl1J9-=J z=&jq#DBaZU=fEI1Y+JqsU8}ttkE3pFIL5G-+ppp=wzVE(IJ#q8bEgUViKKR9Lz+oyJ~scD4+5%@y@t#Bd23G+h0f+Czq0ZTI5bXm3zuR%9xYYW~T z4eIfQcY7ZsBHRgRrtzP!OzRcykkFl=#QkJ2?aBYOa1pk_>g!&s?qMIY+OLb;&Q`bY zE(W6xUGeR(x|$HV;^zp#{B8D=iud6r{!Hk_hFp(~>qbn(dqenva1({DWyA;JmSmZs zdq&IL#%0>18f)4&K}v&XN8^L|H|uNKXESySP%3a!xwpm{2NzuKb~^1d`q(3HueY(@ z&gbuVn*DgA{SF%kR>hP%DR8SX(?zyg2nXZv z6YkBO6;70r<&$T(^rLCx&;upBnXnzUAD)t|_yELU|F+D-hWHXftUoYhi{sHovhpA& zxz8%${#f==ZeKi&3_U1f{~?+k(3W~SNm&j?#Ps(t4Y!G^q0Cx6K#z%V-=tC{Bmaz? zzMzTxkco`#@okdz`3USBHgeviIBz$G9ukH9Xs2e{w>Nn5A2jsPXyRj;iACOsB>9v7 zWe7a-4NJ%GV>)~zVxR3TQTlM-{y5x^>OSl+l!JnJ;(r-L@@}e&zME=)@_#vCFY8bJ zHxbYI-lY9$$zmB<#9n%aLbo!C8N#y^x(+)S`NgIT{&e16q&DKv!=n;@4ikbYZNWl# z?}0b3?OnJTc$*uqIK>iDhyCScEj@HYHmlOTa` z{tkt1Wz-FXcPVr&W4o7eC}7|{4)AFOj|7FDR{jkK@bf+zd0L^2r!lPnPb|_ zQSsBtY^Z`0v(FmG;8TFf@~m-`JiBC`H9p{^)WLP4`>b(FRHPr$?4-=W6>F$}+qHsRR%q+5JoQ3CVdWVk!zCH8l|8l_5o{>Zi zII^K$Kk#e+?7xZHvvEF$KkOA`5heWvg|5R+#a=;`Vc<&);4$335eRsnatbE&*YPH0 z%*R}QMF-h`}Uc9 zN0QoS=ehfAMpW28(D(V7eHL3{pADGWyHtbE`}wJ9`;V{=&&M|a_TzEBXRTd!=taWF zPxRz|Qs5YFb#%?-;F9R0fwSCQIqYJj!#en-BL|oI9F*Yzk^RcZED@dD+LuKP{Fa$H zS9>%11m9VBuBI2-+Q0uV2OMo}sS$m){Nuj~*t4tugg@+RBoK-Ji$d377ov<%(-^4f zlHJu#!G-=^vq>5AF}Dlm%C0^aVv+ay-QWOzx}uR?O&PoTTI}kp+su`1=JI$~&kt4l z8|=qZyGno9xUwyn z;C>S3F2!9uPggu`$=}uWfqAsbqUeHJyQGABgM6rkaOBe}{*Q24v4{x#AKbQA%!01*f?gV?Qj6Ci zjYVp)1P7p;f0`h*NEx+wFKRJtGk3L_JK|bwgepyN=n#C@|Hs^Sz(-N7Z_jK3gciC2 zifocibO}KcI=TuZ1P~$!D57Xg*+4WQm;}Ujje?3D6)ScW8={D!U_->NfKo&d5CKJO z*t>ksbLPz1+1)b}f&0I|k9$33-t#_hIqxZRW@e*SnrH0@l^qixUzBTKl7>6@g=^F6 zm*D8aSUDNs?*F0)=Oa-RZejI6+|mUAa7z%Ga0}~j%SyOqMRC^h;;fgITQWh)cq4Y< zU9Q~mvcnxXX|)d1x{@i%C!OsR^W8YwioO+p0|?@rjVmpmp7DLFPcr!&5HHZJh;)K* zViura{C@!xO&z<(zo6aHfz{@a23-6f@2&y?El@r=Or=;ivEQl6s2 z6I`yBl?v_xvi90eH}Es3x^^5GEQr6Ivs9sBYVG?@sYiS9 zchlqAL*i(PiSExO&`~~yqbO^Ebco7$x76xN>D1>-jUa>rY>cPQ8XevfY-7o`%Z{nN zj47QCTDvpek5|S*JsGIh6Qzir(D4*p4z3b%Pt~bg$Ii6ftWkNjU>#4^|Dwtk>S;jL zsC+su2iFL>XHc$dRA|)wK(L*8FzS97?_mqIP_OP;RCleATdY&JJ`b-GtR??tl`Yg# zy~<&#yk5wis8iW%+-(qSlgQ>dj^a8e72>ApG;QPI z&uxP3yaUkk(|9c{u<3d&&!?8#g}4iKTGqA0RS!)+6Ra1Jbw6WNqp1aUF~Btb{0}Y% zcL;Hpu((qcFQsJHX)A7p8PRu_V7rWLp0lhNRQiSC^LQUys55}7(R?P={X)pSLZ@!j zw53sbw_v^UzpS!_I!mweRaE&)A@>@c%4*uusJln7U3)O|DJmY(}Ad5$O=ZCsQi(L3IbbH{$vHQA}W8g zf;bnI27FHkUBZJ48Wprmnoaxohy|Oa1KM)l3;;mhgiLH2S;v<1$5Q;cr_!wNO0&LE zyUsaQ)7z~UKbJ23t`sihSxv?-rO`(^-#E6TRNp$%$s6AP5A5lF!-n$bQeHM&AQ>LS z#ic(JYw0gc{e6EgwUoI7q9jGg^7s8ybmX15uHWK+AK7D$7#_4*&t>ahOTF$Hg>=qy zOO@u>`dasl_F>drggMpuBFV4RR&Yg$g*)%2;uh4uJOTbontV?T=YAdG$`fFR;QeCX zj}zd?D-!qq|E#clMM88G`cb@fUU%QYXskH`z8`paB8nbF&p*IQVt>SV5K+vJa_Z*s z636II`#(niE*)vM7-=SRY_`C-Y>HcHUpUJMXZ>T3%a#z)ypb5iO_N17t~DaHX*i={ zIQk~>AIGRvUlSzqYl80c2R)jSgAYG=WN<3kn}suy{tde+*dJ*9aH`Edp6t!>f_xZw z9OeGTOPjLX%x*D(Eu!wwn}nA(7tPVEZr|~kQ}M4UhmM)(6Ip_|HC$?h)jg!R6)y&q zWQC;UCj4NiMbl$igvDf50&1{hnEg`9;$fm#hGPFjQJlzPvM5esgTqDfY!su<1sq~& zk+la_?vw|R=S09N2-Zn}O|B2j+P}wwRgo>qNA@X(Ll@zKDG{;fQtS~zY)yS)t))9w zZ0)}mJ2fJ98pU=NVyBb;b~#D@$UAO_y3%!+=VQg5PcW-XE{Nb>NL;_by_mQkon}2A z)#1V%4eo!)_OHBn30pq4--_3PO)7pVi&iXMhGH;9C_a<8D?M=aieDZ9yMkb;0&Et+ zek^tO0s>Rxg{#Q+ue@+|MC>&bn(+LX+Aq;R952S%A?$vD#Un-WK@|U8Og)5_ z{aXsA`Q$%J6dxhKmkagt)1wiv#|Rb_U<-KFnm(S0G+4+6T||SYQ1q0hpM)1haG#Fg zE+%fKzQ~S=BDilxaNiJroP`e^fpA+g>0kxY@UW*vKrCFT6jNtBx;C@Bikih+hxKZ9Z&PBy< z+0rW@^!@c+oPgt91nfmi>CW$2w0iaj6oUhVu0IjV%Ln>}{O1VnFA>~di91l>{!ZK| z9}IF)@ej7#e;@oAC%|n`{8gU-{lfJ(*re8nnIHQ%=24K16Vr_)5 z*s@@Tuxhg43t`1$At8j7jfKPzmLe7!gs>v8&@hDgoP|aq%*HGvg)n`x&^UxihJ_{} z3`G{2hA^gBXcoeVV4-;k@ytSU2m#1Kix7I3g_a?72R9GYJ7{Um@9-j-!DW|iLmlyQ&M>^S}rUy60`DU%B z;`*KYk#PdtR;;7yvmjCHdVZJ|ZNUf^*LOin>BCGGEgyD8F<2mc*o{zLbFe;=j*j4V zkKkq#_e6o)gSb&ncAFx5vZYsa=$+h)Vy!XKn?=jAJ}3r93Jv-ZH%fz1E>7ytmR=g@ z_n*g5tfj%RELs|bPz;_VG&sIKT=Xsukz;TC21LLH5^S^p%OzNpIb&SR$*WJS-kia4 z0>-)s$VW?Q_z)H?!-t}X)yb-e@2%U2)d}-CR|6xIXBEs4W@29Pg)rl?kPyOb$wFcX z(;Ev7LYSIZXc)p!XQ5FD@ybF{2m!`I;}H6pg(e}mn}wz!xQYu7RS8;(6rdPca1OH< zoOafNb0Qm_Ec`o?#ZyG_Bow86qgiY#u8v`YaiVxKiqU=H7Tl*q_{Wj|RKY(!j(@z1 zt4|}p6=QtSRH`z8P^Sr~GvlD#Zo>*AP-jJ;iU@VOfGUZDn&6^UDO-9C82yAErdZ3E zG8QerPDC+yhR~p#xKS~Fri%t=v*rG4a1O;<8dR`oX;6t`uuy1FMcgP2+@|g+5&m<@ zf0p2{iQ_MFv7naxmMT*tP}2xiETE>xL6x{bogaa^AOdwEp-KhR#c@z!7pVWRrI%mz zHwBl(32-~vsH;zaezwQ_5z{YaE*4ydmeQ{?ShTu$CW^s{!Wmb@LD?@=JC5bVS^1T0 zx&O|X6(_)cr#e=^RcI-7y_!W!*K1G=P7=Ca7Y9}DV)pfHx&OM}5GUYl7Xh=;QtEmm zi=(;CIz0KtI*p z4L0emdswu*buWs+Dq-UN#EqJ0rns2+09)?AiSyzFxS9B1eFF3*J_I&t;(Qh@6CXwq zy8x@g#W$m!*acvbmeAxG`C;R zM!=R3tX6)GtM9YH`J%WQ#pvPfHu}~?_&*^31%iKV9KYKg z-a7JI`-t@ss0}E>SC(G1Fr$O;6)d42j1cT#!3;rP7JMNHrf0|*wD>lo81YO%c*bnn z_rkCt#>N)H?thPN1)EfO8;a2KqAJ`BHnENaOxwj6Vxjd zKJgC3gQ;J{{7@s_UBD~iFZqrBmk8DG1&mOg)dNv|zNOBC$b{;wL-lLJ`B_(ovu1^} zt_Ww%R5mc?o=Lk22vu200u2-@aSWTa>vV~UmB(jXV!b@+$ zOB*wq;b%veq~YsoqOt3D-I|%%8B7^|(c%#eRcC4UK*s&qjj@LktcC17Zc0e>Z zUq?k_#~ZjD{7AHT6UBP%*m$sZ007#&1zEz5cPJEgd>m`XyC6tA-a`>~Se);pqOoHY zE(bRW?A0jNYscn;wF3aKV+~{pJ3gdP*zrlM9cw|5cC14Yc37P2QPJ430hfbY1olTL z)@#SsgS7(yuwx@+2|G4XDD2o4YsY2~q#d822s+=Pbk6`i}PnxG`9SL%fT-N_OB?`Ys;ShhAjYrEx$pYu;mX5hAm&k z+VUp|(w4tage?~5->7J8`3IMSUkmJgDAsGsHwR@4))N504g+sh3Ojr#(2j3o?MMJY z+L4GN?65c+prWy(Aub2M6WEPVtk;gc2WtlaU`G;U2|JolDD3z?){dqiNIROL2s`0|h*zrfK9cds)I|3-e4vRA#6^$JkxE%abU>}KMy>|R{uyz0d zb{qv+!j3K!3OoLewIdS*X-8KSVTZ+;g^I?GZnzx$M_?a~V!d|kJ6Jma06V%vmarp- zLSctd7PF7<0fMxnCyKDc;_QWr#*W^&95l;_-3P^b?eLWyFE)u;kn7%?UG>q+qd=O+W3_%gS0Ik6}6cuE{$me-T zfLp&t_4-(=EPtSwtOsQ$0HEdxP*d1Bg8IVFq*yx(K#+Exh$8H?I7gzQiMCO=9BeGG zPeKtQPDbYK2^^O+fjQ1!WB!*RLr;+P|LnLV&F#3PeuZ7TZa)=v!_gm?cq;6D%;0rg zBEB9L-Gm-J1wAT)=2Uhqf+p_BWIPBmXih^BK?9?~c{(bZpqYTn!KR|c87O*3i`ltv zGjzGPEnY_^IQjtqv^f*9gdJy5DC}q+8~jBeNIQyAgdG-V2`U;pN^v=uEU?2U)@w(L zgS7(yu%isJgdLM86n3;HBK<$pQE337maK-T}WK5(7bAQcX}01gs;a1lMF>w}9ykbUqU z6wwD3=Ow6U`k)S%gNF$0OHqV~8OZAGgF_Fh588C@OMnCPKUx3J{O>vjAQjG;3Fip^ zUqLUy|LtSPz?C3K|Ib1Z{@2YF zMiC_fub;CmsMndSV`m@Px(rASxP9JcP@^6oEY- zMTmG5nYSmf*-nKy2eo~wAE2HwLICfmblZ#y<-Pkt%NmJF$cCdHgQG-WETG49q5q)8CK8cE^FP_5XV4A>Qgd#*dgRI`Z2pnu*)DKWkUl8B``+}?o)fWJOqn?GM zL|;5dkLmj2c@Sh@EJYE0VR0@)Mbj5A;BqisV84hWL@Y;EZ(n4<9Pg!9JK^yrl&t%) z^t$2f=k}9Qy$5nVeP6%D+QD=H7Q5l>zs2aySJ9gyU|wUlB4Cb;T~bzpAOq%g6cI2m z6`XINq6wHcaXEODXz><`X!stodIKhS-~mI{|9!wv>Oloe{T91*bl?57*bQet0|rvj zoA0AHMZm0Pw<2J=#0Jb75M;o7fFc6M;`|U5O~9A`oa_4V?FU12+|WfP=qHe&Yh@eJh2OxgV_T6 za}*)sD`eiDz-}xD<{aRvL)QQOBvQY^ZmW*4bw3n#!`aU{fC_t$I=9J2DC`|;TGq&@ zgKPxC*9Zg=Yu_>=5NkbRW9>T-WUTE)5wT`*evgVK)_%a{U{8VlBZ?658?t(1t=ECa z8d>+F>$H;*_6_^lb@eOk79)N4Q(-rp15o$?V~q+QRIC92f$%#5LB!ghj0nV9@7P%T z3j`T!f1`+4vpD}jMH6fLa5>mVU>k>sSZjc+-dO8<;IT&5|9!00udrK;^xaQ|-Ej6Z z)+qG=V~wl_6>9)MtTjX+h*(QvL?G7s#l~7=5M-=1K@qWLaW+Lo6KlARl_yW#9-tWoL##u`}h*-%o?ftedqT?^xl4j< zsM#B83QzQEVPaMlO_(OT(1wrv8*u7!?EIYsS!Z$z# zA$-@xLfupN9pDhY*%6gRtl+~JQF)pbd_5v6i&?=Z7^3nlEBKBB$Wa77=Ly5AI>O-Zmtn^?7ui6Nn>sZ12DxxBOJ0356h>G~_c)Woi zDs}uJc{~aim2&=EJf6#n%I*BQcs!I8mAS0oxtyqMXC*~ezGVf^Mg-+J{%t%Q&WlPJ zD>!%+l}lN{p_-`7WCiC+qOyb)9Ic4TGFEW!D=M$Bf}0ajd50D39z|spD_Gt|G;`oD|MRNuy1uD6H9m$SV@^B}G+yPHbKm?j{BT&AHFyR^0B9}#kZG$aR4$h~N2!2|dAQggqEQ@-B7R>SP^jdylGqTvtgxnXoSm%pWVs*>}g zK?cDXAdGF)zX0(9LvUd%A)~&9X0uNXx6TD&n;Q+V2dkW#B{z7gH zBqN=2*0)iB&G5&0x zY0d#DzpA>j$jQ}GkZuBLOl@_zsM5jJ3Z&*fC^=6_zRyGQJ?`*#dBQJL@Q-`IKMI@K1WezpCJ0_JDs8G#A5`xl4ZDQ}WwN@*5tKSGvQm@Pz+R z!LRm!e;+g#!`^k1EaGjWf?w|ezt$6DyTaJ&f$<4wE-G&Fg#SXp@AQEG%oAg;!uZAm z<15fyRQ%Et{uc%RqX+!=o*4TS#$WDg{NV;+n!kbMGOw6E!*3Lh4%bYrs5S71rOd=c z%wn~s&%|ZN>}FziyWdE%<~K}6P5kyW*a!_>=CcMMxyo&-m)p!+ZhIxS9U8jyNE?t` zRB8p1t4bX})VQJ}E_=8lO{wH}mwSYl+<;zgy0_eHCAS+Iy11e%NG`7E0+OpMazNC$ zq6aQ}xZ+r)Qa^XOeZ1s`^m32$mOE6*9gK!9uE+&R>x$++(>F{n_XKabCn>ondV!DD zgOBkBKSP0^hK4Rio$4j`OugJfZ@FbkZiyH8L_PQv@q#DD+X~|i4~&(dxv03p6MnUVf6oK{9Z!sn3S+&y8f)DkO!EVfTw>eweGH;z z1=@tm9xKoerP8PFa<_WP-Km$m%UkaEO76F4=+Yx!gXA*I_kiT;iXTAKxZ+1#_He~t zN~Pc3<^Jj=_iw%2f4t=;rPy1;1}UztNB~Le3NFTtLDbmW1eZPRZKdQUdx5vsgSYVp z@1(#xqM=Lww)c{IgkElEZ@C#tZkiYPk$Ui>yul|c@N=RYMom-Ypt%@45hQIdnr0ZJ zK~u}h!qvG|QzzrB!)Kq6q~JiqG)olSan_Lv5(A(L#Ml6+O9K&0-o;Ak3((3D4^c`_ z2hBz4X&|{MT?qKyp?4QV_k= zzC_XE)P}boRJuKYc5b@e2U?tN38J6xQSdQdO*75A6wM*}TpXZ@MRbu8z0gDS0?=GK z`Z18=w6adx9#N8Gw5qeBbH1WGG_#}gX%OA|@Q&>;1Y-(RF_PS&9F_L;POQT>SbiNG^W;T1nPxwnx$9 zG&6m_fao?#j8uDz@Hbky1;d}9xoGw~NM4iLuZkY08AeHSCB8|jyZ9u~Tzu9LBp1yR zLGsefr|5B-nZ9HY-F((wDcugO+pmE=Ail6$$sL;GBX zF#zpcG(64?!ZeQs$%@Iio;7`WAjT?>^WVX^>U!iUN3{F(d!jl_R#BnrPn)X=;F$^Kyp#}4UoKCxl++JDz5@jqw;E8 z_E33~QW?L*?WWgyC0FmtwTiCMYcq%%y*|NZ554v%y}m$07gz2A$;FjBK=N|sc172y z{1u2AmA}Si50!sWD*uFrae7&|ls_oBF|Ncd*dlxA;M z8>G3qF#)7Fb*+0%6C~HW^L^6#V5L@H0SjG3-)z$(Ja}`uXi*Mc4J{9HrTfXy=$7qGIU=&|EaT4kVXY zx<*OXYj%~Q>omJdX?BNBdINFxd7HcRTinr2-`yZ;rpSA6+2MoOTe63hN)NireZWiZ zBYL@yddq!Q$$c6PT{_|^kX$-qAxJKR+VtUXz35!=94>pfV!2Z3C3m?mc*%WLFL#Bv z+%-z>`)KImig!VBamCvpc`dAODtcT@n!XP})I`mPxa{GoElTB0Xy~HXMkQB2RyHWQ zMz5_PYV_KM%N}}tqx9N?hAyt$4U&t>pM&J(%AJa?QTbaCH7b9H%N{EKp;Z1A4PEs5 zS;^JA@<&D2==CRv8omC)We>eBOSd<$m!wBEjG9F+2F=CI7lIUL&OkB6oez@Bb88%2 zU9BWv=^^=Ycla5e@V6-Vn>^rWgXUt`_3o0d^^|=cF1^=iA{KK9Y&nk?k zJusdE%|*q9p71Xy_~$*~mv~~VR2Z+itMQ5(glWD6l1prxzSlw2tUzzzvd0RvTB-D& zyWDrYF`38_&U9lBJjVrd{vWF{nE0uP+%iZB6_e;Ip zJ>GJEQgXjXLl;+k2a?tmT#SF#%l*Y$?%zu8A70@9=)w1SgEv0X-gh=U($%O$kX(&w z0-~l9o8q!ZC$?5{TX=!D(Sx`320u-KkBe>?wQijZnoBQ^0ZD7HX`Td<*OAdkMRy#{ z3>A+DOyB7s#`?;BWjU;rE=DVd>!OrC3p5wa&Qy~1hei_=Jx(*MxKot)N)PepxQj1W z@OtqR6+KS8={pxhH^*G0G&>)y+#GWrXfC}u6(kp*)qoUttZelbd~&&xe3^&jI(PX0 zc*5VT;AeZlUk{p#Vb{7#zFJAv_r@$m*Yw655Z!v?9;NhLv~uf>J3w=B`E5$FUb9;i zJx()p$>U1=BOc=CgXZG12SIYt>;WZNui1Ty9;cb}8N#Gp`DvvR6+9xZFrboH^zAwD8|0Fqb4CMbGbRG7XNAi5de zK`DI*TDb*GThLrIYpo>f;v>HrBWAnxkq`)?WUJ|w71+LN^Tw+y0~HxNG=^Q03@#vIZn~zI>Ph~1ySRwVYuw! zsGdBpbaCZHAi1b~0Z3l1 zoUZ5^l`jKPqw)+~_E7nHrSdgs=%UwEO0M3OS1P(juNy$r=rtRcJ@lHZ^tv4lUG%zD z$<^yMN6|HU-36jXue)*CL$BwRUeBVTOBXK&$wlQwAbEB1lZviUc`1k*m6zeNhsv)j zl~T)it_R&rGtt(CZ_m*E%$Gapi{~xv0DbB-fqcDiFQ={GOs~ z?AZvS#-5LH*~6aCl|4Jq&_(I(Ah{~N4MZ=cwQps)Z z1>Q;z-r5_ys{#*3H;g(FI}$XPUQ7o`Yp`jifn)`qBe3|kl6cP1OG(c0klfuJzMCif z00kfNfIkK_7sL9wOYY+-d6<%%?;$zQ9e$7}{AdL~675`+FK|a6?v8Hy#(=1a(6PAe z5us-&l}>Y)d#ab*Gxc%{z2%;x8k)yPlSpaMevpTE>8b#OWbu)+>z2@Muhh7gTz3xRr7gyd5l8ef7LGp6t9g40|c^-%wl^?`q z50#%(Dlb4o7rh=+a`mo!MA0>RJq4mhuSK}*p;wnKos9%D!I$0T2>jAaLPCy}`+CT{ zCv#syVlS(n*jwbyP18KG3!Z6KO|32ok14-E{7A4|kgT5tNmpctu2+c{Vbeg$3)j?^ zPcGu`3~Sj_qT4tyW{Bmfc|vojorzY1r%$OaoK{rf_({&@i6AGMiQQbt4M^Tm%{<_^WiXyXd<@z-Fdn&zR!#>gorRz+QF zr^Nz}A2=L-DaEaYlBvb5j09goLRxWKkq3&~7(NWkbeSJ1^P^A>HKP)-cvLIKH0^VX>3c&r6sSk4-oL@6&uyzi5w%=uP9H2X$|l{ zkfy_jm9U;auuSXQ2olJ!{2I~Y3BDUFO?|ViJmE&A@l`sFuPipIrkpsnG7?6$rg^!G z%Gct$=&Tr(uZ!0U8r>l^x?5^=kJRX1ncpY#c_ODzZ`ElyN2lRUE*jqHqTyUiLrh|( zn8f_e6QSYbQo{v^c1|@<$Y@_Eqy0%4-A~DUk<6bKIW>Mnr}2E9#t&*W7D4->2wK7| z)xkZdgL_sB2b*3OHW6%v4s5v&>}4$&p0H}X2@$K6i1&0N-qDG8ODh6kA1mWG04#P= zGR<|k8oOqEr~xz0HN^&&I>%h1*16A>j2&7T+btQ{Q47;H>tgq)i(9mkH|r(i6N6%- zw$eGsr(n*5(a)D!YunONYi(OrYOQT=m0D}s+cJNr^a!!Wy@#Az&{gvKYFS?+>mSJa zT3KHw>+5BGgRF0q^^awJv#ft2>sw`go2+k__0ME|hpg|E`7U|=3t8VS>tD+H9$Ejo zlxsGFa!IMKlbPV_?O5j;(Lg2 zM1i%Ud{?TO=f2U3#gC4a8ezwt89(_@YR$=xU$+0b)F^kf5i1bq;l!}jwaH;?PH7Pq zUF&Np>#bzHwXC<1^|rF!PSy{R^+RR7y{vbz>Iogg);8#{uoW_g%e<4!kC1t1nfqm) zBJ)(4r^!4Z^K_YKNcRnKI9k`Oz}ZmU)iMd&<1G%=^l`zs!%7c}V61 zWIj;lxl*4zSsyI(e3=iC`B0e;llgF&7s&iXnU9qDNirWT^OL2VQ)GRd%ukj1X)-@u z=4Z&fQ08aJyjbR?GM^~(Nisi2=9Mz9lKHt(ezmOE$h=nOQ)NC)=I6=w(`Eg9nO|V# zz6-)*)wce1`$)_;)oA7%Y#S^q`W zf0Om!W&KZC|4Y{Yk@bDDZkAb-r?1SiH&NCbpiX}@l6hl!y@{+hmGx$lFIm=G$a*VT zZ!O!mmGySAeu%6eD(f9&y`!ujF6*6Sy|b+QWj#gKQ)N9()&sJhF6$Yxew3^SWj#~Y zyUKbuSwC9Vvt>O;)_cl&FIn#+>wRUtzpNi4>mgY`PSyv=`aoIFmGwNUo|uoE@i~OK zFTpp|sy8@6=EJSL;Ru-*h@6wzO=10QEL^n)mg$=tKSmu({jFim zF3$AbrRGt2JG6xJsPC4rVa;mt)J77y88v-(s^RXyzfEuy#NXJOzS{+9_HN7Px#;bAMdPj^C{AX%^Nju*sz(=M4UJnM$^gd+Vv?vq5rrZ19RuR zzxLWP|LFrw{DsNE{U>~R|I#n!E}T$0wd9<_s^YS#H6=y(lWB4FlANf_XYN*&P@M4^|!PiQa=v-nEG7cr_=?3UsJD7yCUtSz>R5J1M|{e4Lp)| zb6{cG6@fiz&j!9udn@pL+Bbojf$IYI1%3}a8h9#wQDAf6?ZEQ%4+7VwZwP#vzAf-r z`u4!u^sfT9r~e#yBmJ+y()3Hy?@hld{nqrW(_cuxG5y{2yVF;sKajpMeO~(d^as3h<*q<@yaHGOw_T`}C5(5j6;C9V6E+Nm>|-Q4WHX7ido z)ogFG@0->6FZIuW8!q=>>7V7l3htQgzY&hP#eb{+cK=-ez5e_B_xm64&+|XzpYMOf z|G0mFf1!Vo{~7VM7uhW}0fTmEfGB@SXlqXUaraY6fH06bqmr`C% zc_ro5loctPQa(%BoAO)ApDFuN9!_15`UJXYaq2VZpe5+8cT(R?U7h*?x@mptN9e9k zQn#jlnz|hwxD(y=W$K>PuTsBG{U-I>)bCRFrhcFLL+X#IKcOpsP5m?V@6>&%Gtw?c z_smMWI_=uD>(geZ-I#V$+MKjo(r!Jx zucp10wleMYwD;29Pg|9?A#G#Y_Ou;oyVAZ$`!a1$+Sh5{rhT9GTiVRP73kI*12+e5 z3)~Ty8@M}gFFJW%;1P85g1}ROMS;bEX9Ld#UJAS#cne+rUSL&VP2hvTy1<6O#|VP0 zfo*~9fgOQe0R&v&tH3vby@8(sKL>tAp!^y5E3hwcY5L6cE7E5n6s}IcHvRha*$9R? z2#ed(?@Yf7L2+;T{RoSB2#NXWkEB1Az94;J`cnvxXVRA-M3y3WUP72GNARpne@29U${~&!W0_mglkJC3Je6}ETK1BfSL{RNUFzrqMKK;-1ztjIougkbJV@Afz zj9D31Wz5dFG2^C;n=|gtxF_SjjQcYl%9x+=NXDZXPiDNB@lwVs8Ot*^Wo*vao3S`^ zN#^sJ8#6!7+?4rA=9bK@nV)8E&-^TNN9NAVU725G?#|qk`BmoEncrl7m$^6dhs+-{ zf6Dwh^OwwDGk?qMV01JNsms7tsl|Yjs>&(d%1c*FO*HrILr@z7%ECpp-MV+5onY3< zE7Phfx>c4M*kKvgm2Rcg;gZ^EVO+p*7r4y-uo(5PTS<9EplqVJM$QEDCN_=wC)!M` z5ZAD~Lz@%EL^VJ~v?-q~E+>jMSN^4K6P_+EHxO;|PKXsIaB9vMZ7@?qR@+KZaU`M* zCN%zQg#QxEUKAPij~9;a*Sovl@h`hi_kKBjyJvULaa=?(yL{bzBrhdzG1V8PrCOHwn&tXTM5L!(WzMh0oq@n>_faEX6TfAa#p z-8I(0CM_*rNuRUb9JF~XrriLe=W!j;9asauJWRa#YJWSv%SWQ{X=7+E!?6$MqLVIyngMEqBa|B7>rtieOkreLg* zHDnC_JKxC4FRvY0e0KiS$pEm*c}2BFC|4ci9>CVUkdL3rqxS@H+E*2y4Uwe>DbjV@ zkrl44uBxsMPpPV|?LVa&aZqct%J0;%xTm@JdGt*VBDzhdx)oE69}wUC*Z!2|nA6&K zF__jhz)ll+rbxS5*OIJjb+saIJ-a=EYFzo`(yH@n{KIkcJR!ULgkh6QDyEi(QS8>e zTTV{*?#L%hEvc@ZP*R0?vAPz{L4XyOR81}`pV)1Z(bC+sdiI5zMxF3y)6$>&2QoK( z-ui|E13ph63&>YS^*JW@j3$5kdTlwb!O92DYdvcJAR|bx-v8&y<1QY&ch3pC`fXYL zXNT4|rX7&gmEp>gDd!i~2=x*tq`h|UgK4AgIHt>^r_B5H+}6Rs0fE9|K4%q}N8DEW z+ND38H1qFchdlPg{HDLRzG43qbwJ%aJ^8wv{v&%l|3>>Uuf09w@YcqJ{Zg;8sG_2( zL}*o>ao49M$L>D;*PZLmxwhl&(^|iB+JQ%WK~e3b!P9H2i!3kB>bc?RJ38;4KjX`p z<8CirbWiJc51R+EjUO?1Pz$aB`OshXahzVxEjq4o#vu4u7NnV33Tn)hXldbI1u z8&2=}+V~GXuQ;Mx@=fiH!a{UhQH30%Q+NbaR#;{I`Dom@HAwQ~h^QUz3a??I4zq@l zST}nB?h9{e?@PWd763O;llA=9`oaGN*fS;no!}qc!6=+ocAgZ=H$WOBvR!)!#2*7R z>Q2OReafM4%^qMR`fh4(_UK?Hhog9E3ZuEMC)XCNwRJ~>HNtruIHyN(PKn{f-z7Ba zDzLQHC4oJ{ISiZy9fh8jbLbMCCX_Yh2al88g&h`k$irLQ^|kenUztT z&dw+2?d05+gQO$6GGbmw$lNG6OX4-{2F5$c_FO9mC0wm|9JL9HVCo?(dWOI6ljCYZ7>4`{2Wf;a` z!l^z492t)njFaO8_6OhHA|vsz&KQYKHm5u?-bcoNCLsANiZKI>XE_<2T|vhC$#~tF zNM1nDMI>f}u|NI-;Iy*Xo*>r)YV~X50h=!yUh#=Nz!~%c3Ygr>^8&K+fhjAXzZj$w^)Lx6`K8*b=9xo|pi> zC&<@vHj<2d!$@XN_{>FM;$J*domc3btmzv38Cj$5b+Vlew#aNoMR(#y_NUdvhI28v zo+MY^d?a^a$VS3)bE=ulKO10kIo(OVr^xro!$_u%cFrs0!`}l?Y|64Qm==*~`6Eca z15+znmSFw{j@k3DZVxRl?2&^fPzhL$F+H|I?5Ch`#fwOu#>9{`0PRg9`4%=FQ5D<2WF2plHoxIL+_r7Aqfl* zli^7+jCU|RLk98Y?}%_wDfa27g>kR#)UFA5@%Q+Qy2MwJd=K6q*E5qVXVxaS-_;ZFv z-Kr0e-~~=2ne09zIiH+k&>kEA@Z?g)0iL;#rweuvU! zaYk}Sa+QWlaO!Zfb^oB4^1y_@SZLH8xe3XTQp4yj)$1lj72`xDDvX|C^M^Mh`3=pR zOBp@cykt_iP>VHDhOSda0;YtRqb7a?hWIg-}5A@SXZr0!PZQDiNjM$+a5B!QJkQr}17 z+km9uHYDb5B#Gbi+8;>TCp=^tO`0Jw+c7x;N$^M{ncb0e?S~{|5E9>TB<5Ho&Cg(| zj7b%f=}azVay1g)%`Dx;+5tC1u ze90scJ!7(K>mKtZcYa)TQ&j)T(ee;_>Us9m>@_~4uFbV5)tI8E8lFDhWb~U1=0=P* zf$3wvo5>%HH+XbaSdMc*#kyxINew)F# zf=lX^23Zr04yv^M>08zNsvhw zCYem=`$n|Uq`to7Po>jhgk9!q0F{io+u**JD6Dihg!RA4Fb2|njZCU+CjUak!HSnW z)bJdH+pL$#;@<<7?3=OkX6ND0o{l$@87hV~ISe~-%qfEl^YRO^P{^LY1E#$~)s?^2d)^>(V#6NeeH=$7$C1f#WO5vd?oUi+>`BytrKROVs;j0>8B|>~xnxod_;P~Z zwin<(&OzxK2_78p>oMLueS89^V}Y4K%Y4a8WSb1O=->eHDc&qkhD>xKLpk<Tqdm~P3@LxF}hUZq`d_F4l z-XQvINkAVpS8mlXIJq=Pj3J{&_wMP=|0emnGzR}0;P;Eb^##Y9j3qOf3rhs2pg?G& z(c~@+g13ltZWAD#epfuw^>IktuIcq6+S^2XzA4c5YS6gWMe9{iH7z{K9qt{%?P~_O z%kPd?j;m$_u1Ag@ha>%6;^Zd-r{g{GI9zrm&ZydIca-;ta$O6cJPDK|EvK{3Olo2# zbLEyed1FS6b_aT&Kn+>}=;(W~s}w*IgA2dJ$RFYv0;>qJksuENBsK)NcZlG4`DQh7 zI=2B%|NG)`xc!hgxw#%DtszQTTcE7gpm6_UYXcb9VetV`o@fV@();6e;RYz8iz~>7 z1o`O@fc&lj;Rec9WyokRW!4hsnD)TA{(*R9xJi;Y1^AA|xvs1u<7FMdm^Kd!ytS$X z$0uOoKV!Vfy}PxSuqJ+Pv}~)2u%pGNBsLgF)Ov#5dN{xuKWG@E1Xu%%bgWX*NMG-m=n^- zc)do{R77sfh`E`V&mIlT>mJ2paA7cf#vK8DCT-=m+6gv0kf z7b3y(V5B2Zr}C4w#6Q?9A=Nc?|DB)O}qa4sV4VI6b09!Dqy2GY~ir zF04l%-c31ha;v7~#Ei-v1iL5~U=yCK2aI=R5^T(ra7lSlMUN2`V@i~6booxg?HUZY zwoe&Gt#ElmdnWU#y_M`j-j+(lq2mx}9{ZnN1U82OcsqdG3SbknM>6kfCC0#d7QoMm z@eeVI7U2k1U_|ynyfe0ea&vq4l1M)m0IAF3c%68MB9W{KagfG3zfs3t+(V@PBZ2ga28p*hQAk7G zk-j3*rK5l}_L+E{c&`+N#2|>>c1oSTCem9c0qIK(5^uPokn-G-z9CYJF+lpyv++9d z^do|lTU%YBK>`5%^evH284IK~OX87ugd&l0M~?E?Y<@?WyH5tpBN`YU!blkFzHw|( zHEwI8hTUEw>^ubsq2~-E#fofunoH&hjzl6RFTUx{$| znLrrzf?*t?oGMoTWFC=81fDHSt>}{}48FsJ&fI+_^9WD!kt=%p z^e4HlET*)V4C4@GsaUC#dGP08jalgbBJac!O4RW3ywFy6%s`l`{KG!_o4i9x!F%@0 zQC9MVQL^EvOZ*&%Gu;0nU&}D~wt=sk&^NIKx7lX7++QT~d{RQ-+&vCrA0aBrX!0vK zD2_3i=bBEF`$csSRj=!U|E5d?f0N~S@hpa)N1{&tzTl5+B*=d$`A?Zd`5JznraJih zjTxo<#<;qS%*U34`6n=E#|Y;stYjW|V&1Uq-cGlZeFoW!&jI`DR}JF=!A{>L-yh** zSoW%j-4o9w=i!sVS-m2v!?;0|GBIV3z&bK=N*E_?rAluaeL2~8k^Kv>Uufx#EwweG zxMS5~I3kYfUqO_VYM^}k8Xl~~pzuUlqS)sZql(I_l^#U6k_ctBK-j(#rF*PBFSa8s zElqfOEipJ)a(YB{KM`gT;i2<^uno_fV!A)ccw>QSojH%mDa5mzy2Vr*&jNhY%_L)F zpMqhd#uSboJftwY2Tr0}N?Hpe$@mP%u;Q>fKc|<2Z4O8UHYT=fIXMpEKBK8IwxFb@ z5U;~Rt8Z~Mi+@dx-oCJqFGz}4u)>8?s_^zz7~dIU&4-mjtGfD{_>4ggB}E^) zXt~zbWo(QpmqV44$HF7El{Gzbx|j6sIUOqeW;8IegW>VUn@H7L%9VBRW#fgq*qU3(KpD zrW6ls;(O`*4b|++;N7(9eo_`=!9XC zf7%c{P{}K-g(`Pj_WFz-^fGQ~hW5x23XCi*#T+cU$xn~t15m@)iXLy-h8}OnkBW6O+zNQkbMMNoR5-lOU5!CRt35W|GY$$++I01h{q0cFqF>VCS=FB)TszCuVY) z2;NHNg~2Dq1n^oge-m-U&|%KNI2xY#DPt4AfT$V4^<)QPqx zV=#@WDXs&8v>V-L-Bw1%ZYmwORL(FxY~G>6x;vOT$Qs+E{M_h~^a6-gHgT*|n-p07 zlT8__Zu{Z`r6V9ti1+}rn;IHT@T~qE>Mc(53(qUBom5yewHPlu;K^a38oX8zw4^PC z9CnQv1W9*7xH*@}T}kEYdcYn-G=XXelW%VcLBYAZf4Hy6i!*a5`r6M{bXD%(en>XGg2 z_me>Ft|pV*LY$ODX5L#HAg&c_u9L4b_-5Evj*Eiq1!pf-ToBm9$ruLX1rBP|a@!Te z$8FTS?3iJ827vq9R0O#*_`e3{Vw;wi6XW(UI4^MsjnXI^teiYVhvgRz9fpZY4XSrR z{5lf1Lx*KMBDWiezu2%CG|sqs#Nb~rEmWT@R903^j=ZMG=Uj=280vM$V-kMT&oMuC zkS0;!fEA`YbF!S|?9~yfSMv(7a;ja; z)9BF*8;ntx;~XU$;g4$~{>ZZ?zX2Tk<(&LdIQjX{r@q4e3t19QxR@p3iAz`#?zogC z;S&y7%Q2U;B)oGaOTtB0u_XL-4NJmV*Rdo##yyzjwi{UzzGKi>4!ngW;l^T47narLbMsZ#1YIZY8KA0hI1Lcd z7ny>Ors^-sDfq0&O*>6$L=nwMnP?6dhfj-7V~i{NJJESxzeW|MqAmgp`7w|1cs>`ugfSz!B& zi$z@IjvYMm#6r10ZAf|TjW@0pQnQIn?qCQ>hl;B{YcTG zY`6+On5w!sGGE5*n&Ng6Rxrfg@Bi1-4&?^zZ<4-G@iXTU)L=>0W(`a*R8ub~YsEXWRM&uqrm%k#r z`##&fdD+pMuF>#trA-{`oMt|;~?8Sl}Ra+Fq1MSyh|}BF)3$qHj{Ih zurJKXOn6gaa#)z>GO1=#!=#qUR3@Abqwd3J(Si{pd-sflLDYnNQe;BrEu5N=TOsPK1QpB?EoOnKg4)54v@||nKMW8f=WkP|Ga$eE)BDbrz*%+J|qYgcWfx6nJ<~w(Z zm!kJiq3;kQqXz;y;=cqAqvdiKv15c5W1af>&BW93W}s5~O!ezQNkiNKC9duCcX;dX@dw=nQOS>KgdYMAo*D<(rMOkeyM)a-C6ZWu?d< z_k24*7(UMU%w%jSeWUJ@hJkNbR_>U>f{}TH3k!zjjvi^${b^6_EseypGw{>N)srj2 zlkpxqey$bT-3;<7KcnJPTVj5WbM3ncB=&^x4@XP3bM;#f>UW9}kEb0Y@_x`}+nnQ~ zKnFq7yKOdF7-h#uFgCLpu`$STN_-i9?-_|lvEs#S{v5l2B;!Gcm>yBxdkT<_6G*wa zk%88Z18s#IXz$w0`OcN_V(7QW)=#ay+L@pwnqF-;9T(-gW8s4nZ4xItr`LI!c`J3Z zP7NaJWm3J@gnB+BpDi#I@@a6SNz_!a#g+gs_t2`C02R3+hz=g(oKOyh5*Jd0oa_ol zjj)D)>^ABQu$yNxDP)pl%(3ytMfF`iNF3jhSaR-=c?Nff?Qk(`I-_Ygs5@+Ge$@T% zEtvXW&cf7>PnipA&MBW#${&2d;i5~m_%byTo_2D{F4NQpW;4}v(~LF^F~L8pSs{ki}i8?#5g z6xx4mv*zP5QDmvS27E8se0e=$4q~dX4xEii$eP#2SUAabo5m)quo%Injfs4IVu*Is%6ScBakA2y_mY-r#+~CgwT&w-S{6$a;sc zRjVEEm&egsdlzaA=-4MEVmp~+a4A($o8!DS{}e;+?)Le^MhxaSvv*bdRC~Vh8}X%f z-bsflL#T>ycjWG9Qh8JvCrj9Q*n8pFv*jglfXVX*a~YEtnY_$|_x0uqCX5aE@mgEA zaZyKJ$AQFE*gj*(<(F9b{FKUZ%8&qSYsMGkj+%5nPf7453zp8N#uwafTHjj13ybUl z^11G^&zL}4d3zKILdQatn2m3UV@~j_?~v6A9*-f{V5#;Q6@>CW2#*MfI*m>Qr|3~F zH!j)_Keb)f1%cJT6G5$p&O1@pM^oI(EVTOtLpM75&qCJ>cWh@yjltXBh;y~0830#= z=!$&&%>nWJDKnS8_KTPEDNn0uKd8NB}yjv3<|V~1e{>_rLxCPwi* z%+ezEDH!j1%?Fq~$Yef~N0>auWC0U;!F-Cz(@dUWvV_U=OqMZuk;%(Ud=SN zL+a579X+b5rkr2<4LCmg_~XSFsj;7e4j9mHKtCSrVN*JX+ddPYVIp1=(E;B^W(q{7 zW3K29_jaQ3IFYsti@g*5p1$Kztob98pP2m2geUIiuS|GsV)B5`{DaA#O#Wi>HGT~m)Y|bQ^Ned<|nP3}fM=SPGE+>#V z@Ig6L5WPPz*ST&ThCzNj_YVB66?kp7HN=w)s%K4%IJR=mi_Ze=6Pw6AjCLIP(CTzs zB$kVUqA89=p*g7Zr!By_U_1ocDjR=n%)^&DL`DreOc;x|JFQ-eJxH2Ff74>~Y$oS0 zNitruQAdo7*$_+x^&Xo#FgJ!e3e-(DRSXlY$-KiDABi+>cGaT9Bh_PU2<(KN`>bz3 zJH+lpxC)QZ#tohpp3HeT{xtbmw9bk=Dsvv@-;4)kbud+Um20W9qZtDq+QfY4sl!ZA zI7P_L$aSvz4}jLv){Vy? zh4{&|!jcli=Po-wOKo`rom;3wpvgR&B3$6~^vM|ReHcAz4j)x9wZ;yj*4!_>j@_)U z2~SQNiyZ>R#GW-pPMFR^ms)RTBpHk};lhEr&Tu{)8kx2St=FXM*)<#qj<>oE99^P=vk&II+bD5^66CViNeP zAl+h<#zpOshG5q_j0Y-q->QR^hpm3{8N;Id9lK^)!#A0pKb>dRN%VXpozumMp3~pg zMO1P|!10(N3Mms?D!h9o*38&R{a&z|V#&InC9!VJV@WJt53wXxu!mU^%h;nViM8x; zmc)Yg1WRI7dy*xwv@K#utZ$215{ulkEQyuwIhMq7x0EHZ=Dom@SonCqVy%97UKg21 z_*7fXBiv|jM?0$%#S1Fh5!ndsKC;`L5_1xL73Q;cc1T(i&Y;MK)bXfO3w;cr|FNOf zd;jqh6<=v6w4)JHPM%yDwFdAclpP^V$%~nCPlAdQtv##b2NMgeM`OHC6T^Ws?gm># ze$+#|Ss?XN4?PFPJ<6V&;4^Mwn0VPA*t=!oMgVkgvUMRdraPE zvWf{$YRxrFK48LC!d%N_9TPq)G3jOVBPJV}@UGk3#AGv*Pnc|BvX#j;COm61w=?;S z3C}gmolJHy`JBlYOm;I#GB_ZtNXY3O?T>Rn<-W)Yc^s8FXV<0hfck_w7CmvW^Hj7A^x<;{A#$Konf69vNBl%q%q@=kNicpZ zn8<_by3Ux-*WxxOacle?k^Ffe)ixh(*NI!A3)snCH#OpIATh(L^(}V3jYM?RJ<|r; zzo*2E!&xx)FPkW4RBf=Q!e5*stscyd0XZEYvu%%Ydk}TRGYGsrZC>$ai&}X;2kEdJ ztb~}8_#E$4E?J-1iy_}s4cd(2A&2vLaWklgJE>7`2d%u}uK#>5_B@s0(%opW911r^+}(|~^4btm!WGP#S% z-ArC*!s)?&f$=$8;XJ1k%Zp&mC-OQFGlBAP%u1 zIe|G<`5lfZ=KVjNfR5tH6aFrJj`!mouaWJ*?;PQ`L0wipwU%+++bB%j z;n2tW_%zn#U2J)~MzfpZqB_aVFQhPkje+y?Z(jw8%88UMn#@Wi)V;^F_x`o z(oNJ{;p0iTj}wNE6NXPt7(B?c2aj`jJPNVLaDG)&sWo-Rp2F(xSart)O^s>o#jxia za`-=d(aH9Oc=GI=5?6!zlC4;tGfb+WR;BB-?+jnPx_ltx{`#DAy61-8a!l0YuGvtn z&hds-{wT*AR=q$xT7_zE^ozi^;E;;9)B-fGU-Vx8G%T5Y#I%fG8!s#_s;({%S0i*f z+p{unH!O9c&LppcMBcktB&Vllz*AZD6viPY8p|EAw@3evy0;FOt4RL1?}RL52`ugw zVmJhXdmseYgap~$YzV;?30a&40)db~2=4CgzF2T~cXxLdSa`pmGgUJ+mA*jU=l93^ z-hS##pYHlrS5;Tbk(s*;?qH8sTaLr>99H14B8QbYtju8*4y$tL!(lZJt8?hfVGR!b zI56AR*5behu*UAC#{QK?uQy%wN2P?H0~^|uR5;z%(-z`9-^u@yb)akv@_REE;jCbR1*3w zo_cm`8F8G;XWDBCr+&h2ui>aYSiIctzx&Xk!}M!R)sxxkik~O>fAL0GR^vUa30k(k zs=masEW=9+jkxKqN+ktAWd2Hlu{nWJtseEb$Q!JUq_FgU!bJ>NvNc=}s@2*~nYC?| z!5h|pV7$L}c|*1xRz0L>{UP%D?~~f^kk@C%F&*0U>x^CIZR@6&zPtrJ5sov!v}&D; zYwMM$|9IIp!C`ver&Y5N+86HfdlLi?t$t&E_ygO)4sF}D+el-^%vV+|SDq&}b`^9oDI^Dm~K-_`$Qq${(?Nj`M-qpJMH3w~1JA!%)3}<_NKexY^<0kB~fAqO?bz7;r zqg35Ys_r9Iw~(s4N7ap^>Yh<`yQsQTRNW-1?hjSBhN`9;DCqjksK82K{uaUclFtbL-RP@MyV@P=N*r-geHt8op+q!sV zwY7>*f}WDxTfDaK5(&GLu_Te0ap=_6y`d#9OvWwObMo!gVygPA z>d{y`RJGT|+Ll>%8`W~txE?7jp>V9K+N66`rSQ}}!S=qSSzmE{RJ43mxTie8FS=G= z2WpO_>gsctelVFE4I?L5$33Wy>oQWm-O=`yCbEL`LEUTt~~+%Kuk$bm;oH6Cc!_+n^{b*9D_m}|-1n_93Tn%9;PS4vA_rcysqwmOZ50lya_GZ>UnHol z&Ve6LsI9@F9|vCUs;$L=$DFlwIIPQIJr3)0*nq=^9Qg7`ZDS6baOls04M1&E4g)z1 z;=mBEu{Eu2!GQ&(#+y~Ozj63G2Oe4u^9X$KePL<2fA3;V2GAb2x^>u^f)$a6E?- zIOt2g3iWD+7!+64g;g`F*RUAGYy5{av0UMEPBmY}HT@r|<@s(Uw6AWvwEUpQ5N+b< zKBnaA>kQ>pzxo18r?#nG4p%O5QoKWroaU8%(lWP!+Tb^v3oDK-G-oYUUuYg`E;Pqa z#X>WpT4?^NWiHCbQ*cac>vDv`ogjt2cGwc~;}!_%y#h+(Y}| zSE_yRz~=oM?&3G@-^|?B@yEi$F8{|MO;PJh)T@=K+r3Zv#zk0+R|4*y8((EsudZh~W<`KgES-eznfMf(p-F*m(Q= zTUB!F!7F3k$Eq9B^eR2n@anv(V`Zsux-@V3y^5k5Q^`&SX8i@K<_4l88{h#MhpNy`=1_o_VIEBmCkxi?hbJsj>%$OnzP6B|ft=AJ+J_|rD8&FkCz ze%Q%UB0t*b&^9YAptvmSyZtuX@H<9!$7tk_+`*KK9@Y@+ATthdGX}+}WO3QBjo0*# zy*R6CHuT`@Gay7Bk1;oG?9x|Td(FXX=x3YyY|z}QSI>+)v@y%q9nkEya4p@TjV11n zzQ)-U5#Igo+_u>kymz$rfW|xVed>4K^n*I>)aaL2+~7XxJ(KliGc#Wm3!C%_HghLx zh{HCDGc`}w2Reqkij9ZCorIa+G0ashPwZdPy`K}qV^A)Q)MH!vBhs<$)@ge8_NvK0 z_U91wHH&)l_HTZY*7ReTDLT&4?r$zMo`vwLvmXD;sLS1`zKf^(OM~T%DZQ38BQ8w0 z3fdMbTfP=>jok6?>PG4aUgoYwQX7qNx6#LDi?|MIYuCojm^E8odEiGAxSi?1mgo0B zs`7gGVBdJ-a9eFUkN-or$L!w|wR3;0bK7i7=rO7`{B>h^1E4Zyt>(0-UTe&XM9NdH z?trvnAFS1sJt(jIHal-N#`YsDpTe@IuT0ggL4HPi;zv^*+d6Kie-*g>&U*~mar>tN)^w z?rM(wlUsjPL*(M=vGi7wc}Js5S{?@Os=#<{5gtlcuT#$DH`WI^`jKuA$`o`z~?Q@Zi9~U+U78T9C0q?@RS-Epiv*)>y-01pQ+B#l0(H)Yt z^`AeQmwMIA;2rd|=7&?N=h6?lnf+4-?JH;Q+-$CTeY(*ezrAvTyN*3Y%L|!nsrC|= zt6yJe-H-fLf=}?;K`nQ(*HW*4UERsnhEtu+moc=rZG_31YqY#+@P;ZoxFqfx#0Q7h zX%1tbU42`*ygj{JSal~mYI`59{sMBHy9;Aum>gxlc(pg&`*PTi11n+eKn|lg9KwM+ ztTpa?)(+=z1cxIz9L?ca4##sik%PXSqK|68Z4@JHda1U5n(hxr=JnSH>w=AZW^__DPCu6)sH8O6YICUq%7=Gs{KmbS-jTP zaSHvmq_#14pR6kH?-Q}#Mxmh4Fzr~ zRKF?MjN+CbYn#VqV?~Rno>U-z(X;WZaXirO&^8a^m<#J+kRP`0E?sJSaM+UrS7f!l zIqbt>Uk?A~upfv0IgI6S7>C0-jN@@}Q(8NX!|5D&`cu2iv*6kMtMt7*cxp}w7>8aIvaZ+P4)`P3~ z+Sf1Y4IbV4W~t>4{uCNA+=ZEF$TVFa<`{i#Um8_{=(u$`P+xXcGgcT=wIz=$FY`Q11$4fm5&Uv7nTPP*?Q{{dTi^j z6wP0UckHcySDfPA|5b7$+^0~uzgLC(m+`$%!oBg{C%e%L+`7JL>$8~*ye1gfyJcP7 zTH(o!Cq1BP=a)M=w|z!DR}YYfSK-VJJfG&9&*;J>X0z*B=6(XP;pUe6_xHcznMak7s!k%tS5ks&3Mz|BIq2({?k1SJ%JE+ijQv zp;zNNh#zJ-qnb9^0M^5-<>AiivhaW20z24f#g($+n@|}e;R4l-_BvFHiyK>no4vAc zeE#=OO?3kYG=Cr1t}NL(=&y6zWXtkOq;3Ui`diPZzqW}B^)`ySwlYW&QhX#;J*g`W z3tm&0uKA0J>uYn@@^g!O>J{x7++Wq&8>0MPf&bI6Ek^l{(*N=mr2p{Yd}D5atAF7{ zWu4l1ZeMBNFFJL9$!5K+YFNoz`g=vy-r5+=8w`x2xvTnd30HZ|jan~w-Vtys7prgG zHSg`rD3u?pzUa5haDNlGS6%N;ZT*{jd@gJnTl^UWTAeS%@Qa5sbg1v4S11*p!uzcJ zdWJ69cjryl^Xu%L+E#XbwL^^2^M%wM>gw{#1wmoH!E?3a`YxWH9}lf{>^<>_&`+v2 zN5m>>{k&>K?9w!^`sQH6K7Nyz7oF|bcQ&kok)H+BU#GT5z4ZZU{Ww6^j)P|1W5{6s zcaZEHK6!=c(8iM#yS!Vgxn{L|vuS!4O0>m^{vNeBrAK=6w^E8>-AlX=h8ww()3}kl zp6X6(#LjvHT7GYcTTr|QQV+U;7Qgb^#tTbvt*uu4qM5U5UgrT_{ROh7Lu*_kK4!O)*swN7QJmCPl43mPt!j0h zWB=}C;_C=PjYqi^V>QVX)#;{axolHrt)-Xk#h1o5_i=wwv2>v=^a}588;z)bqMdsT zBhT{j^KEtKL6ezE`4vaKhSiKw+0ckkUgce{(JTC{y=ogB!)nVmy=i}(fmc!O@TS=6 zEv<%NLg@L%c4a`ztKTbWR^$oL~COjLuDh)q>YinEB$N>Dl_$!^f3AGE7qTSl~(-d z)-x5A{Fm4CuyE*zT@ciGHDxLq)7#>=^n(~*4UQOX@s?nV- z_uto4yFB47@1FdHmGbUqNA;#AtyPxUNh;b(Oej>L*U!6}XJ&Dk`$1l~(JT8dk#3!D zuaV6Shf3SN@e*h|;m+}zYQBg|-v9;8g4KKUT8Z=$vfQ+#52WtJ@(yi0-S=OGtXr6$ zH}%FszT{S0iUV6R>DON$m3}g<<#F(zbd|`naQ|{@b8-o@b%!=yBdD(1b%U(Q5-#04 zo~4`AgNN`h8T4!WgSXjz=b?>P#O9ELKkUNw`h19~-s>%2u>XJk%cC9IczdJyh^Fa^ za6P74fcI6+MP5^dV7#>7LLqqlQuUeqpHgaR@WpD|w3ni_x}pEJPjLr% za1DyGmsHsC0#|(yxBS#YPbqa^qly>t!j!{f-Sb^y-*g{vkc4s*r7o14;IYXKWX@k_ z-E-)6Lq;@jWv|wp`Q@0#yw7}it4rz|H)A`irjskc{oFWc|D#G?eyR^9y?a@lhr5W2 z+e-~KnvG?8^S8IHglDEC;y4$-ZMJsv1`5fo$o1U=`kP7QJUC*|@;rpot zRw z8}C7`AY=EkA!2Lc-?*)QkZhw7!?xajsBRpDA0^Xc*2UX>l0LZkeR`gye_GAAkErP? z00*QugZ9@3V^LiKZs%KCtgJW(wYV6#BcuQ+l*pfxN)@+C;nq}W0ZHGD>19Le37K9K!X~)daivY zx+;Ctk^SN_aDagSZtgH9y6f|nzS_#Wdp*1K6 zzq6>+Hs`Pfhb=iUv)2B`;qM&yjTUv;cJ8hIQQ6s5!vmJO1Gp0u7tKC0Wsl~fncrP_ zMb&@)!~OW%-!drnGIvP&`?t8a*>T9We(z|G`YhY2t&dy9)kEBZeJ%I##;iSvse3O! z>AoJ{e>Gao}~u8gE_Hf0*%3ay($H-Ob@14tkkFAC)iZ zwf>ugC5`L7lf0H0v*lL!I6oQ+>s!(V#C+F3;}ovXTwy^f7)%k!cwReM&W`}OMwt^YBNUo+=HTqAZ`z-tJ+ zqAR7|iI;YtscvSkL*W>b52*64MyngP+Yp zHc@rqL|<4hP6PbwF1|-lIkLPgAE3r+{5D>VOPtz497b_Cm;?XQsK!%-8own}8^hsD z4m|Xzoy~ze2DNiJoX6pO4i|9X)?tGLbRX&LmxB)XE>C*AdnJ9{epCMH;^$B zHw=$R*k8jKQQ$Vl$efZke%2B3f6C~`@mx~>bkk=aZSqE~rfB=u-v8Q1muUxh2p%wT zp{{2e259`XtZRc5P<-(Nr#HTuSzcg=N=W3SuH61J_rc8xg!>hrYXa%e z)(fjA8g>YL_$64` z@)F8b(tEL@-t{i)#f18_Ce#kItuGm~RttKymh=3q{U205i_YUx`v2@VZTa$#->|Fe zmTwgDvSn=x4qI~gD+m44kN6Xd^?L)=9sA4cW2-}3PXt%b-KNhI@Pn)czL~`~s?3#%rW~tou*`hvj$w)@DE5c=wN6M11|N95Rhd-TM8h`e2-%i6Z;}Z1r5? z6seGZ6zd+!xW;YyWvuI5*}hAptKMy7%FpgRIj3cXze2W5-h2xn-*Mh?@(yj?u!FZ? z>w4xl>Nb?<|1bZyBt2t|&)ay2-+12kf~?;%%rS9iJ%{Q(Y`U%G8Q7_+`y|xG+rek3 z>u1Ad1Xcgtx6-g%d+WWzw|T1DfzPlaNXo7*rS(BtH&yaQ%KGofRSgA73Dx&%Qo5ICP#il8pso9=Y}>9}zsJElz&(it7gF>bpd`UA>*g z&0bzRFm5mwR1L$knl}2U_e|ziwu_5kHTH@Z-3*Ed-D%UPwU#>g1y;CS#ev9g-Z+5B{_LF?m%uG|a zG2PGHL)Qg-A=YmaH`l$EM}&OIxMdgn+jm*&K{h!-5dMW=iY2`j<63Rfr}Yh=ndFPt zeLVGRc|d%$Tua>eg+=|XmTjJ^eL<(TxxHETn=NmMJt5({ zc)P8yz!71)I&eVT9(R)q`TnrGu=>sQq964u!;Ra60|v)mgIH0sGhb(}UMQ`5FTdM2 zL5*tI8!fJumxLpASMpppsc*Ul+EiBYy>@-SscFlf z=+UcmwZQKlt{UHaYbbP*E41uyRqKcF-Oc@4zGX5_g8$O^{kiH<{VVhYx`9z*f7&6J zwp+7*qo%I*vkn>2Ud1<+J@t@b^3Y%Bwp|5ibcpHUcnjm&t+}=F zU6;C2S2$#wrK))~eFNqqul}+=FI7(8*9&LatU0OslysR_9@^Al`>mNJKk}Lb+O4_3 z0)$8E_ReibSV-0RPIJL$)@>L%eD}dNG9UM<{hMuC5WeVDm()@9 zJGJ#6xqj5^&ht*;#~j;6?&q#Q+RBIjOaFq8DPWA(Ol39d5lz(9NEqdHD>q`%bhypi zIlr#MHcic+^r~x3p#7$3eK?MDk-M2)bx*wPp!s`yoZ4KzlGk)^x2Bub)J1WfTlxA< zYri>}AL5PAYF}<2K4RE5!*(0GU0t`s>eW*M=YL`83%VVbBpE_>3iB$-PHQ*DAG63I!!0HlOmShRFFvsEBHaMLqrUVaEkTh(J|662y=1w;v&5T(y_Z}SrM-6CDMgN<*u&!oLAH~MfFSO zaz{-)RTH!(Z&pdF*CbB+%MLa5MpZ8tRp&CH_KHYiYjQ!AWL^tDrE*7u|3c*>zg*kG zPy2Ftga0e#)eQ~#az_h4^3eHPRN%fDA;F8@EuN84yC z`}yX;KTvs%$|`Au)zHuFp&!wSL|Jb4LX~;D2PuzkgcgbN%#Yul|5N4hCvAGldLF47 z=N}MwOZ|0l;2o_zy0~m?$hzzm_}^5XwlyPE3BPCl9aZMKe5X8p;{5n2#sheGNhQB+ zZuRhu716fGKDdoVe0n^rZ|Crj6GeXVlhU?kzJ?t?Dv$25ZOwcwZEFT>@c)wd@ey%} zjjn4~<arYkrhW85NAHs#l%pJd zE~`pA)U=XR$;T)4Zr3Num*l)><;Xc%1lHvcBd>{~oR{o8`{x-eN6z6Q`c*4Vm58$( zj}NHK^=E#9U#nY{@at?M>hYC-y6x~rovycY+SZC%)9PF$uvds8?e9{CVy1ySaw4VOPbd18n7tYUqN>I+a*(=4IKv`3=sHWA(FT^Z}PFdphC zr+XczO=g9s4)^*p%6V2Vn$K{<6xt@ycIJ=fk5fJEIzRc$AI(2b^-~%@<;d?Ta{WJ3 z9(}urNF{yUN3?Z~2z{L&Om3fH;_?Zf$WQy!L9P!noc~AV(bwhEWm!H;F1kRMi%9d@ zCv9bZhM@C#}^`MTjEbDodxh&-3yKW*<$#)N{-1(V4(a-t8Wchal z{*x0wzRUdA2LAslkMCSQ{;fh@pYH1mm3MvCQog&0L|NuN&C03UK;*pmDC==_;C)wl z>~#K8A086;-%tF=&hnY2(F1x>#5Td@lh3;Eq%!AcdUam>lVxuec*iOakMq;NnSWs5 zXS$2Jl;Url!2gBvY;|2e`7D3s!2gx<=-~W}t);ELqdtiVrewGEC*>nQOY(f8KN{am zlP(L}(5;7vRElr57tT)%;0xzRKXjqqb)}!2|8wOz?0r5I?Cvy2Sc7Y zhZv*&ZY#$=^2nu}giTq_jVg1QQO?y?j+}c%Q4X@Qob!zz-J%?}X>RlV%11fyW;w?i zf0lDZkb~_}4l$B_ePH1K!1x!?r|X{EWt&#=!!A~iAFi~#`;#?!TPt(yP&?21|INyg zbCifrmxI5u{#>TH-zF%Jz4MDmbBTyq@bqbn6)@R0#=q+~lk(p7vR2MH@d(d?A`)f2 zM3gy}@#Og^hw(-^nDO@Ma=Pd|+s69u{7)z!ZNtXQk3G)+c;ZK=OGPDLU`Lk4_@{5s z^%4>D$wDF$<(dC;D~JDbQRGLb%>Q=aA8mP;kBrRE`tSOjocNi0GXKMY{|n_A_xOM` zg(&m0{=58-mB-hv54@S5_22oQRGzW5h=^1gXBVp6`JXl(=SR0J|J1;LuJWBl&QCt` z9~t;xS04SHpSaKbqXPdiR`2{^Gyk4}e{A9>?lS*B1OIu-NB=M%47GY<1HTNmPx>C) zBR_gUrP!tK^Eh5lWypl$`0Hn7v@uGAor{V{=$~y^US-ID{}2)U3y4VMS^ueb8<6Gv zrzlT9IX`nmmftn-bL#<_^NUDJiPjaBY^E&Rj8ADBiZ0V%|Vk$6cem>u{iQ)GuUZ@LUq|$iBeNk@u^J*p2+)qh7?2 z%U?&i#lm@xCG>ONvy?*?F-M}E%sG@_zJr1b)hL+h3`S{zc|E5vjL*miqlY)j9uI<8ywnS^i6b|1HZqKjSI$KNk33 zPyF;<=D#cOk5r!I^06uN-=H$r|E!9;$zO^?#=rA_V0o91-?RKP0{^p#AKuJ=OyGZ1 zdE&`qvlQo}13zm)C?Dft2Ay&JPrc6r%qh_jqFbyZn!pkNVH4^Q`|dfuD7Vc=325 zmNGx%-{l{qJo1+jk>(b0PQB~H_;>y}l=pS8yYgA~E`b+cVymxnJqr9DXT-vDBI0E^ z5ouvjmOn^kuFDU~NBN5s_}2~mXDd%~`OF#FR^Pv%&tQ@Jk#c?f28unK`#*ryD~rh>-=9RkN)siKAEEWr&d(cC9{hr z7m+BtT*T0$j`LW@G~&3Kl*g5hW4Xtb;J~moA#onn0~5`^PUj3u$ZlK zbN;yq9aj)}8-xWobV3fHTav?a-#3zaPXBna` zY#{!|+d29jA&UIe&nKcC?022rf6+eb_Z7K)w1rHtyIVQuT(TjDsnK=XNjcXEA8v2w z^l_9k)XI@FQiQH92VB&LI+h{V$8|@ajjbFxM~bkMsh30?W;tu9tRx2v<;eL-L|?fa z`jB(l!`JXI{+<6|<);>{Dk723{P^DaFRi$mk8p{B$dCQRiSr+*JTm);NceFf5&D$+ z5`Do^=ROAqKe~I}EXva_UiXV~*oBSw4n4rY!@S{q)Vr+zD39)|i72P-PejO}t=mM@ zuP!1@C+aS0Pxn_<2NvDkkKQiZ71xits2}<|U)1j^l@b$-8`tk14Nz;pd z%eU97-u27Ay&}|Q-(F~S=etXGi5QCGk^B%5IuT>o$|w47DWcr%M6Z4#66@h_*}0zTqn*ek zAs1b!n-n`A6F+tm7vP9-WVn7$C{O*GBGPQ4-_nn|_Vk;}>Lx|Mr-aG+5o503<5utb z&93v<5A^r1q9sK5iuu*Y7IQr1^uswK{!4PswsPdWCyH{2lV}rjBICa#hqaG#8X5{GeTu0IXhZ8ay}7ZgUgvu`6vgTe~3zQwy<(|eiRYoE@wgIvz!f7R+6)pl_Td1 z5i#s?h`}s}J!eS{*IAS!hj9_*^wK%=m&YG#IyyQ(>m+_a7ZSH4GXLBvbAIOj$WM9Z zpFZ#t>ye+apZOWrF8{H_&z>Oj<8$=H-Wx|UgbN)A#kMiNo z{Fes)Ta?Ea>xf9iappf$WiJ0#`1pcQIKmLyV$Ql~>4^ck)e>$CI{y~AC*ogjT97KNFTQ~4ydz3$e&NBZhfgk@w z`P>(Ya|Hfke9>RT3i}#jme^iIpO zMIYus=cP}bH;+$jx-{^9t$gRePd@vR@$a&~OZ>!J*5%m1|2O3~5|OYe%O0aLmpxv2 z^mTsxn)&}7_`g*ina)3r^0_aD8$W#!$HER)jz5?auz_`kG_B|rk*^1iqmHuJ2KqAo zdx>ZRa-BD}a@x4o$|)le-&xKYDl5rh{8Nq`#x4Eta%ii!$aO_`Pn5YXw1=-27P+je zlqYsJ5s}De{w^wW{%efK`N3rV83X^-i67q(FUWI!z`J~W6!jq%nU~x)KBpCtMv5kg zvd)a_uSJWA-0!rtponyq$Z;Pk4;*6=A~wk*6pJ9@;3$S>MXx`AkIG)IQNY%3&P!5tZbu zVCBfUQG{IsMI>~Ka^OKmNzMXR4$mbb<`w2L5@k^i{+UZuk~52ygLz1V4x5Qc^kI|( z5B*b;LmlOOGJf#M<{}dFbCiRBxXxKrl>7Z_D@V@dBJA2iM8a3SMZ^a&;PVM}l*PCv zCf^Xz2C}Xff!R_-BA@x6QJM4KY&_2I?b8lEqU{Gn&d(Yi%sSsgRFX5?%8~P$h<3ITk$Q=uoT+ub zwaDcV|KR99+NPZIFGR>0Dk3c|%5pYQSxL@%R*oEeNdLN=C6v!{R#jO^&hl1{oKHnj zAJ(@lXHnyaFWNP~l_Q5SAN5&M=UL92#-HWT2ksyGG|E}3AZN;UT%X!1fkwa`pIm_xi%X!B5vz*7Q9694fQO8b_;U;o8+uqkh5Joa<&R`zD{yh(fJlukKd*i4Yc#zUmICD{dJHi z`k6I@dJ=O!^9*B?M81=Kf?>|Z58h{&Dv!*qMUKz>%uCLHx$?+%elVH8N8lfm_^~VV zv;MpM$CZ!zpmXdqt`YDP{K%SC1V47NzPX$Wlt<5DA`(1N4u1Ga#2zNg`PRz8oG0Sb z-uSaVPg*&0#*3nysdOIY;GcU%C4KI&a^(C^#N4@! zh=fnGoNHB9l0ytoj+_@nU|kL}vYfM3R+4k7l_Td(5y|D`{S=bv8r80+w}{=58f%EP~% zh?MtJ@U#9q{}0L|&-uG3AAL|%&haSqLLief4A!u<&m?!h}26I*1mF4`R zvIRx(MLGDEa^#*QqJLdZ-cO+qu~CwPPh8H&%13?jehN7+wIhf1-{lbZQ6Ksy+x0*@ za_$OpMkhH-73AE|j-0E4oa2+6r3-S-Yex?2zuPq`$yuf#=a_cnFm_xHJkdYP7UYa< zM-J=1%Ry$8vs^*W&h5xyOuC#Om5=?td_m4%+mSOc$YEZK`sDo-@v}}la{2~2%=J;9 zyq`i2K0|-_;hT+LNF{xKR`~)V^dUB)pJ{tO5%WvlPhm$Kd*DA5Aq!pNe&lT{hvyxuXZ|P6 zD|%T3j<%V*pSSZY=SeF^&T}H_hlohCidYlS6*=VZ6}fGfp{XOBSo zr+v<@&&<#I@BDWf-;ValTATUL4*a(p-%j>9XMvyj#pR!Ce6Igo1^%&t|9syV&A=^m}&CZ@k!jmngPF zKHEVIBOCsEM3KK_H|;zB-HAWOgxk%h^WPizX@_#=JQDdBCyZV6#~$Q%7NH}2w~8p| z{8P~sqMbz~>|l61ix67IREFy@ABD`Wcm2r`PoNA`OE2? zSfCz%BH#UhKiR)T{aNRue8%N>qWMJdKPh4?Y#<^rr)2(*RObArRa{N}nROoH1o^KS zKjV>e+M)kn5V@RRm8adcMWk6oS1;tb6to_myh4+bLU4N`m;T| za@z-r*JT}{JZVq+EZIiiIscKy=lo!IvU=Bb`@nxifqznT9T;TYraZ9`?asEb{=2TX z8~urifp;b4 z_cdN*XI|QMx#;_E<0VcqFLCF*D=NRA@w&a}?fGAo?;*mbS4FHjt}|uXw_mHw`Cm7F z*Bf7D{`Uj_8^-Utqj%(AaS%iksN-)Hr%|8xcZp@IJat9SjUFYq(xx;_tDz3V?ifq&h=f4|kc{xcT% zR|)(NS-tDen9KI|4*ZW;z3V@7fq%Zh|ESfw{vLV;A8Y)se`#!A6!^y(zw2Kb+ouKo z@y74^m&W!{fuA)Q|G568v3+phKf?H3|I*lI&2)c$t31i|FOBUT1ONBN@A{X<_CEsu z5618Mm&W#h!2g}`yZ)uIy;k7=ukpM7rLnzY;Qz_^UH{V9?iKidHh$Niv7O@wU%Eek zG=A5A)&f6e&QB~c{`VJ=W)o%k#GvzEqCETuh)A=G7&C36jv~i8|D`H}f24@Hfi#DR ze(WZ4%-43#9C5J-%z+}u(8fw45@q-eEQz+W4zH^W`N(6AV%!}ha(R3%EdooPe)BrY z+z!|8VU@YO50poq_X)VWt)4tF6J=%HZZckUdtZdCQ6k6id8LTkm1q%y}aUg_WH8`_u@-_V}RW4=IM^bL9H(dqYmv#ar94|5f= zMv2@WKDQGg&waDColmCE=$pS=IkLuykQIFcKKo{4l_49_M zzFErZ|A=oE46@EOS)=qBeKW7|U>h+!mz__h&*&TG5!dT%<+E?tb7$YM);Z>WpUA?m**ABq4B23A5RncNfhEB|DZXL+cNHOz`GOREbD_?u|0BLR&3KV@ zqllD!bF9jc=e}VabDn)O*294{grBy!&{XHAN482>KsMCD1* zH~+BuKjNEBjThZc5RtNP)>Bzmk^5#XJI}sZ&B~E=oQM>C!x+oHVf-T-%ts=0KEyu3 zv!7c=)ZRLk<;^Qzm-mVC$Qx~+$m5*#A0G0*H?C;k<$Y|JL+#V$;TL$^Kj_MN_78g# z^uyK>v?X5}%VY?hX^b%Nwga^5VEdHucE;J-_W~yy%9F$jakxXXA0d?O^BGZ(CbAvgk`> z9V|i*PdN?-sm5(NTzN3)?-<&c6yK~aewW9d3VG2tD_A}9f6q7U|6SHN<&l+rGoSIe zZ@SqzddIbl_1|UDf5?iy0iS&{ZNMC@Jo8rc4St>!-~258E+TNOGsug+VH{HbM||_4 z@gnOO5wfyx-Y_2b%`0}Eee;}^BkL#;vZ8M$*Ln8MgDP`dE-*~=%@it|U_989=c7(4 zYZJL{*BdW7TqMfAx!mgih;PmbvMw}P**7N}kGFrkooC;${=1#$o2=*?)`fFL=;d}| z0}1=G-?-j&c^@lJ9F7%%CGnXtjDN?l4uBzs9Rn_7hN#RjpDPdMaFJuMGh+s*%rT!R z4`!UmG59KD)>N5ePEnqI8!K`QzQ~y6Rpyw}lm`>-DaG3&0mFO_CfY;1<#uSp+d0)R z(H>$jW0*4>bERRTJ@97?`a0%n!$f{BP_DS3jzZvtC${h2E@kV<}`;&VE=264M{$YQT+hP6pb{;lNw1@dOV=fJt zo0TU;d#2NQ#t<*w&Mg(9HQuH#V3_Y6bE{#ZJ;X_Fhk3y<|1nIohxIOFSpOY!l3}7f z%$pgrL%=ZRNU?ur)_KPKO=aE=V}TUynMLOrvysXi!+c4K_OO4>nAKJ080ISC?Fjn> zKbt6HSVJAdTm@#leS(=?lrama%rRdW?~(QiW)4xt%&9WRd}h2y*(Vt4GlsZz%(uoH z?O|V$G01Yv_lAk~%w51Bn{wuZA4K>d+Jn4LMDX~U^?{v(`A!5T+QT?K)5@tMmf$6| ziSio!jLKYxRg@nq0!QLA^FN?6=kKF@j6pD&pK;{;t0^DjkM$_?UlsUQRX)aEX)QW0 z@V}}2RHA4Dw&%V&F<{;{Otho47E$kZyknSXOKC0IFJRs>Otc5vvu?u!=2GS1iT1#s zF+&69a>GP>rYv9v2Fw+PiS~3ZVAc+p%M26k!S`9W6$9ob%whq<+KLaN zJ;Zo!r)$7)EeR&t!DXm4szhj;?Oth!87GZ;9UNB6w2Onj>-5)S787A5@a{1+&_Z@<_W_@dx+nR*(6||G)%OIwP9 zVR7+ze}AMrX{^ZS3O+NYyUHB%iSndqE9V(QtU2b>3eh@Our6iHlmYXxVWO>!>5TcG z%IH(Z{ZS(1jup8*@Mp{yDs#*+%7cmaphw2M9WcZ)nAmrn3mE1hZ|7*kM0=(xU>*#Z z;|w!apKecSF26NkPB2Wgr!<#e88EEX*`Cr|eonv~Z;f){!@W}0p+9q@Miw|0{_CwNB#d?;Aj1J{TEd}>OW=KE0HW`ZJGZd(qeVmry?HPpoAA{R4k*<)i-0UzvYI;Ab6-`j_UeZ34fK zn`lF6?%F(HnEMzf(T>vGwO+vBGceJX(%i*$r2C3>0!*~0GHhnDK`3_L!5>e;r8YbGxI+HQm1eY!owXvS<1FwYn!+QXWYF?|B&S;Ito zSa&jJ$$)vD!l{w}S!$f;nlQQPTfO*s~(H_>Nj6t@y^RQvY>CL@HWQEA z#u%l)qkYJrEUtg+>fAA`9n?n~OLN=G0rP@kqMfC=ZSjD4&M?u|(%jZPV9*I)``U?K zrMV3syFJJU<7+3F(%d#>z#tzCae}`{Q;4$PxTa)pfDYIW#@8n>oM+4zDs#+fRv+zw zKV#kwm@}+C+Jo*HgMYo9Gp#<_)470oFknu%`e+YxL2l>PfVo+D`f#ks{l4?en1Eq_lkH*r<#zTB80N-oPiddJ zbHGe6Otgm>&g~2dnA;5#?ZKxRGaz8zRGyd|EAswfoMgtH-Zf0LXRZQ<*l>H^H%zprv`=M@aLfmWiT1EhW&G1m z^fx~Gubnd=uzph(?Lm)EMa;eUKhEWxXIrrk`N(@lL_0@|yziJ}GUf%9IfnTk%rPRz zl;-7!1LkSN92+pSpW7k+yq)I_6Ll-iu~!ESdS=~9bL@Em!<+^t>V{rfw-W>ACBq!2 zPxnD-z9b&po|g^7{Nb3+%I9|W3z!!Tb3(vOUBCQ>Du5quHLh3mEqQ-VSqo?jQD-jDL81Z5m?dzLtQA_Q1P>2;W04 zzrD3-{lG(vFgF|_^1kCU$H=NGbGh#-4`#f`F{QPscfh=7m?HzGv^Mn&n0E|wRKS$h zCSuKXJ5KqjM6vJiTeb%t$DCl87>oEgV}4Z`V;gzQ|Hz23SX!ID5|3k!H%#oi(%OW7 z9dof^qCM!9bz_cn%%z5j_Dos8JRC5W87A7(xq!JnU@kFCw5K#LUmY+HDvxiE7J2NH z=H>GO<{`rz6ELNDnLcqJJYbk(1BU+2e#1wOdBiYLx6&NDU%)(Sn5bK6jvXE__#Gca z-AeQ2(13Z|Fj2SCd^s>+o-j<*tu$Y*9Waj>ChAt2`&JB?rwkKyE6sh21fILRNn~CeFjFd@{k*=)z`)BV^6~SU zc24_`h^W6r@0i#4WNe6S*wTnRmgu zpUJzd=;x`e99bWW@ayFwmqj1uc*Z}-0>d0hd(qG6p8fo_${6$Tf<-=ZJ{3`ptS3a& zM?WK{n+RSozc+6%kGZ@jl}BFoGwr~GZ_t(g0fOMea8~vpv}F82SawIFVy$D`S`+9rLL2xgG4x7_R>rGw?Eway$4cW4=(CV^|w= zJDg|C+W~W}VWK_wIAfj*n0pNq{We7b^I*W-W0=@ZY2CRsVE$v6*baJS-5AI21LlnE zH~J!D&IuUw%zo=!z;K=A?L1(ZXwOsy%$R_=$uQBLsSB8W1Lj7<#CDixvpqWp%>9Om z?JyT)%#eV&&oHr_(wsaXU`|n>)(n9~ds?I~T`(YD)jYM~wG-mDw?JBD$Z?O~3|nE$GbJ|H$3r(mKzrTb@} zh{rK!87A5@o62%KuLlg*EV&)#*o=89V2JB%&m08|^M>n2T<3P?EMSoBm@^C$?I~SD zUK%i`8z%a#bPb7YZ|8#&x*L zc%!Yz$o()pVA$&+KiXPan}!C=HOl9{E3Hke|E}9*hKcQz)~2-s=7>T&=$h?WF<=fg zOl${TGiI@Xc}98UM!%KTrmg|=m|48y$Xm>CP0%LC?4)0mV7i$0XMQF0Z@t-Vb*xpKUG8eXPxn zAx5$erMZuB?U;uP?I0t^B7Mv_rS2j7jJ6Wb8S{n897D`!drEWP+W|AdFtMG|+{YO7 zc3xHp7b07L*OVs;aox8lvl^-ke_W8^@zZm%OJ>xZEXg6aX2^iKn>LaE!zuplr zUs^t5O7koGR<{K|l8z9$J@_o^cD~9S!`>)k=%b9m?~b{)fFX9D7U5^wX8%LmB+9b9 zgH`78-d7&p>qV}2sUP+Xn2!x}L%`5hZfA#p`NS|c22Ab;V)JhS^MPS*3YbzqY!oo3 zD^HAE9x$bTSUq6QG|bHbQ|gDM1LiElFweQ)O6%ML0dt07ZV4F1NA??IH}((p(H_n- zW}1Nc(CVW-_#|WKGjHc3tB>|{E?~Y@*;FEYO8+1;+CyD#2R_FTJJd&e&>>@(QylZD z)kk}Xm5g~TU_P_@Xb(QR*LZw>yE9-uF-){)HkA>7=t4jL-q^w}*PHQypP~+>u|+I7 zhH(fc>QEY6#|F$j$`h}#ojkUPv(W)_w_##CrLnblz}#n;*bchpe%LW!@He`}b~w)% z_W$mKOAQm-DUB`m|BgA|FtMG|*jgiCm{-vywu4?-w`Bu{bu-&j8e0nm4Ew>{PHAkh zmbyLkZ*GUWtQ*&@jyb_F(Vo)SqMsdeykVl>N@MGL@u4&Q&Di2Iw!_%Ux-q9XhA|8# zw!>J;m{$Xa{W=)-<37ihuG60gn3oN6Tfmg|#Kgbr_L^a0J2R*(>&AF?40@tlY^Ss* zzBpjsF-&Y{CY9xOP79c~4HMg$xqx9$=DNLSnApxN1#D_t5D&QO0yrS#F28bPRjvjOkv$ycjU}i+L;B)1!cSBw!c=8Pl_X zAzoZJVl-psQyJqQ9`7G)a18yDG4$!KBK&~=@iQ?=A|L%j`57XYceL{O7QMXhXg6cv zbId!+BWHrhG1M(6qCLu}M{Y?6^xse9@;*_XKDtxn^0E$KhKn47A2NnEw>2K{V20W` zx-j2m3_PqU=q`-JcZpnQ)|uXRUh)BBEw;0w&fOl?{<{r} z&%nn%K+j$x=YL6g$|45+a~s_PX8FXA9k~tWZ*Suj<#QX@oH6h_<{qn$dg1eo`Ja`c z!@UIzc0^m4v%WAsFw2Ny8_17s!2gbw!O!^4wxDxtgZk%1$N|$`6x(3#ifzFEu$93N zZ*GJ0*amvtF7h^(Q$Dtl_fhaO{+<72<#QYCqhcG>pC2$il#gxXJrw*W2Y&i6w?S;v zk1>A71dgo{FlgH~0#y^=p(UZPF&#gt? z<|oS2-`M8kmHkcDbCAj$(^GkGmvNExTrcq6t2{n){yD8K`fJs|&%8l9;9Q@)2S6V4 ziR*K>z?z4Qv(5GvNkO46d{7FQj?c68S zA#XB~ulex(D#DM{pDm)E_FOkUv#hUF1}4k;#LAI%uGL3b=$2)9JY`wT53bia1zGS% zKjX7U5{CG?TjaLj+l;v*V9rn;x%Y}3<9_r0q#ee;>vop%8AD&>cFqr&GYc5xW#4d} zTJrNTK^AgpKl+)rv#di518?mA1FRf7FBfH5_%O>FVVEpyM=M9xC88{=G+z%6n6s77 zeTKiYFE;b%=@p;DJm#o`D0dqwGldlzNhdILAxzaHA z>(gT}Un_!P{5$6A0w!O>(FXDFm{XOff9@4|J3i-ltb_Sp#GFi@o-WE5u2rHBzC*KHo&}BB*9%$E7W(EAk@J6}JbFDOat!kGn8LTEwokNjbookztcOJ| z3twbehpDV2>tHKK)_EdiMO!G(vi4M2N!G4b4(0+;mW8jgtgQ``{rh(-N7nhGEQ|KD ztc?wmWvy%F$huIJWzko$-|4TFMI{><|CA$(y-D;Ha&x~gtTN~K>*R-2=6%Kdm+c^~ zOKme2UDlV%(_ZX%^v<#&1MTW&KxW;IekTVM7W37kBG+jS<+DzV|B{@?tQv#hSeC`ST#|KskacN67I8Grc$gE2g)w%X`|uzu$HvP=S+5yX zhCKWTxed&9%!fJdcMd%FD^Hx$Ctyi@X3P+kx!mWK&lqqSGaz8@Hq7Jt^mec_W7Z6q zXA2m76*2S)*X6DoYfRP+zh%rK0rOM=gS?FC5-<-NCfdW8%^3Q|btA^nEn+$)3~>Oz zWA0Nv+d~_%9Waa|?1Ye?F~m&9d}91y?lMf&4H+5pdcZtXz@SUU;9uA60mH<2o4SCx zH(;JDVE$6T+!QeP7$({?O#yRhz&ujG%vivj5ik!LhPd;%F75x04w$D47}hIdf${3| z!NJPA-|z?h(OpDhUz7RwQknDP-^kDU6#Ip7vt!_Y&iG@$FsBbS9&`dT*v@H(`JFbR zk69O(Q?LVncpRfMWl?A3tt)b!mr|a2!u`l+)_Ik{&pbrDMGWoaHkJsOr4xUigV3pG z;D15++y?S<8~E4lV4jFNVMDfqn0Nj=l+SH2UUM7x&oT2VAKRcGavR^MjD7<%L6qCz zJY(KhnPa#|N_}i6k30MYpJQGtV5U_Wb0hkD95EL~$3ah82);Js7%C_9fyY&|pZKd3zZaa|abCtAJRd90n&2aJozPn@hM!Y{;n z94q*O`O1Ap-AEB~ClfKpAd~uiMDCxDlqa_EFEUB^Kg-%lWhGhLS~;>W5)oHX7UTQx zBCrs8ZDIMW7wf<4g`cymUMf3Mgr3=c>>}3Oetf^G$aTg>+M|AXD@W(|EWevRNyyD| z7FAhE&iq!6oNq1fa*&nfuumajwtHGIFE9OpQ}VAyDqVE1%__LgqtsFVbxAe8gGwVT?vxLe@b}ek>$f56|oEdeV<#aLrtk3LLj+~Q4 zQ4VuKmcw~TA8?c-=M+(t!@L{i5YIo0NLiontQRiRzr+y9+c?h7Y2#uMawBG0oiA_Y)G>#`OQP+# zW;5!uySM^ zBg%TgpJlCSm@KQ0l_TSLQPvBeXIV=cCd*pX%8|kSo2(b-S=PLU$+C!F5*X$pKBK?r z(=3Z|Q}P!v>atEzF6+hGm}UK>GWsU##r}nIWSn51Q7_^*%VJEGWW8nO$U0V(^Y@io@EWRa%5d6!Us{-3OZk3giXkT zZ*4nA)=XB0jjM-ppC2h-$;!cgCc^hGSQ+|u5z#KZ-bOFwy}y{-@Z*bC24-GS#&olK z+PO)TF=7!Jhp?6 zuMoLzA1j|RizW>1oEqTiO+dBos1{NR`` zlm`=aV_u3Fe8Ae_nA4O;x7g0gI*%B9fPRiSQ+Y7n4nAy~qHTc-Yi+R5WwVQz9!Zov zDxw_X-0Khr8_t4PT3Wys|q)A>(T9`jcfk&ri|D7O2J&S?+bsdx8%7Rsro9Q{AAa?Vc?fukEp z(}}WtTwjvUa_i+${u5S?{6j@iK0caB=k&3Nn){^h=i|)i;zJ(-9slcK}RK^~X!B^}T$ z>hM^=Fehis+$x(C9sU#KT~?5XAFehY_rv7@bAJKDJU=NqoE+pKJKKZ~M;VXn!1%{6 z&;z23Ve7y;;C}2Oz&bC$#?=_+* zhqziyM0@0YPNofX$?-WrWypcf718#aB9G7Ml#ljx*ZGN`2&S>RHZ;Kqm_|6z? zcFYsT`%b_xM}YHwryb-uW~`ml7bN^h9X^B4{YD*a=k`BSSw|6=>qKDQwNEfpi!$a- zl{toaE@Oy=6GR>xeBxsgby?n{Dsy?v*~Hms!&3 zqU}ZP#oHUIDam=s%8|oMQ%4Smoay$%rO@$pE1N;#?TLr zxu<|3_AWIZ`mVc(wZ$=v?c5IW!Wb#VA7xpGV^!wzF0%Z``gB|Q%$U&ub6)|2e=}z9 zfVrT6L5GalF<>SXF!&^61_#U)1q?BeF^qrr0sTNe`e5<`W{rUHK8l#qTD)w)+-3QQ zp)a#;3k3{gJ?jR4#t>_6&+P>a<0xa8w;Xd#0n@pF!T*k7&CR+of8=()R~doYv=Q^vYu&Qc!zqi!?nJjd^e0rQ6CKetbOP}(~l7BJ*VUsxIW z(%x}DtH*EbF-Z6ieMxhPqHaBOK3wGX-~;UZ%F4j7A7ah$7~#`nv5WHahdRbPF-C%q zc;eH2x2f{91&_xX^&5tAmreQFR*pSCTK-Y{thZ9X*NseXV@0b6Lu|il=kRwIEg(WR z7<}Q0vZybr%9c@f&=U~ngQT~mUfq{oO zL_T%hMYM+uK53sk_5ZU^WW6RLeJi4#)Ki4bQ5G@9IhYef#PfF|$IPdE#=NaE#~i18 z#w?|>tn+h*$vQs~WHIM5heVy1)_HFK?tr;hdB$zjc^RFvmxy-WVCUEgK4X?pS#Iaz zfVon6eDb}0;!kvA?8bJ`pL6Uao@meO`Q-di5$!K2@;)7}yw^XYJZ=48pR~n#mi0UE z|KaXD;G`(Fwm&-{y8`9_yR+-=?7|>ODT)bD1OteGD-u*h1v8+cV!nza8NH||Dk>@{ zD&`zo#eiPpHG9ngbGil$7?JOJPIYxv_x3PD-}k<+e(WpOU@wm%A zzxg@)(Z2>H>KJZ3Mw&i*qU`GTgq&oJOhv!w8Zm2$`4vd~Z`KHP@l|Ih=c`V-#9fpB zqq}4W)NO=B9fri|=Anc#Pc0@KE_>Qof@G$FINjZwwx|~C z=8i_-3f`a$#AG=hUToYp7IJL&f4!tCY%jX=8>EBS!enhAKVqf zakzqvy(uWuu4|7r7#ejr7SE9M$@JljMSb83iN?btnmMBypXlSaem%#Xh!h>a8g;I% zj*ve@a&4KT)H{AXZ9I=ezjzigY{(^Q>jl)s*?QWqr!DG4ZE?9pZ7uTqm^m|k-Q(BO z7Wd|;E$(qqTi5%2qP74rXfXb zZHv07t^R%=`sJSWcJb?JgZl_$`~%7G>W(tk7}>JU^ewdSZ4Mp!Ona03+_gs=8zWJN zW3k-Mm)VE=RMZEaC8P0hf256QJnQ)Nw3SCn?7xu$O}w@#4nMl$1YEHY%@Tm5?4e+-F!@wiSK{LlJpk=U1Qv~`s)(~fKFGQXaE zovLPTlGng5JuB$8pnW8Vm0W}h38n17CBcrtg#XP-tSGrozNw)^?@ zW_-r!+M*v(Tij>jY>_SNX=?^j)K-)+{pyGmXRE=lr!B7EXpEe9*DoH&H$*bFxOQ72 z%|kM}#sw!+Hlu!h?zhp#M89lo zar~$)?*AMk&ep4b8*QEAmyIp1QTNzn{9ycCyJTecSC+|OF_MXsF_Y(kNc?ZO@-7v1 zOrN`anLhBUnthB9tE0TCKFmiSE5;VjgXB07$^0kds6Bo{FJzC$S7YxDl-b|4w< zZKki0xDQT3GXH6tYmV)lC)#@3m!r10){U)+D6fv>+FBQK)UT)fK2ckb`t`JTHWF=3 zMl%0-T@kf)H|nS#wRNjs&o+KGV2rM@z1E=$f0|Ib5W+#H|nEc4iODUylx1C%-D zL?rW{{n$Rs&rQFXzRb1{k)r*wsOy9j=Sv>-v=co}o`gE%3)eDj9*D&M?8CNbpRs;D z+ulTS`xxJ8gYCxm{e78ruOqR~Xe9n`hvcqrGUEPEUFxxoOlh0;`XjN8=~E=?OhhvO zyP(8%nnI%fW=K7ej6HV^Z|l^XeTMzG|C=$m{yD}JB=diBl%iv_M_t?)Tpy<19i!5( zXWPX{^mPi7`A;9BWANB#Y`Jk5yY$nP83z;fnf{FwjiW2-qGNoII{HFgcZ{!`dUp)Y z0rfe?xqf*Ha`S&nl%ivB-NcQ->wi=4j`5sd&oQR?Wp|9NP!}EJ5nnGF$Nf&dJH}mp zJ;%7vFS}!Gjk@R<3w^!l7*{&=?ih3ZdX6#KFS}!GgSzM#=lFWjF=jaR?iiE&dX90v zUv|gfnvafgg0B}H<7lVe9b=4N&oOvh;+(l-bb}lnV?SRnI>ug3y*tJrzn)|8dW`+t zG5C2tI>yeZGwX+K?91~V_kUCGjzJczr{0-<*&U+?>Y`)t{BLZzW3+eb-7&cTn=$@C zIU2`ysEdxl^IhB+-2Y9zI|j>Uj2}^sjqX~-`#kkyy^2aB=dg_lw4c%t2a`dE$-8-r>)PC zxKFvZvXJSUnPd93DU#`PF3Oza=}6{3*Gsey?U+7S`t5EX`WWrAzSC!EOdlRs89VKA z4bV4oHRCKpnKs>V+WK`S9{Tz#691FIJS5thfn@$yqU8F<^~L?)^qG%Rv`-c4+&&y< ziS*Fp+=w!LeFLe?ug@Tl_IcTFqi;7OMf+5v?g}K@U}9Wmt&@Yh4tNdq5EB2h&0SNT zU(a!#Lt;Gi*Z9Ucj@n`jt}WAkjbBe&w9A-yJ~96(8(oe=zb^J$jbEnye7~Ny9zcrP zYKc0dYiv#R`$TQ!{d(G3gcP;KwG_2A-tQB&b);WUTMr^dZE-(}+8XKiiP{?O*VER0 zNKsqS{h7Q5`hB9d`ug>>#bbNa7JZ8P)!px7Y_Tub(UyKaNsB>*~g>2Sw)UV(CHrl!#iEHRAB=f&L zN>N*1qmK5Xwm$RgX=@=;)YitRb8T@R-$IJB^)J7kwzxl0$7RoRZPeD2zFyR?#eO|) z-HXI^?%LV}a@5vcsEhOK7Qddhen*Ph>Wn(hTMEhSk5{5>Y;n!7FWcuj_3p8VpEsya zy{nM8kMnwp{}qyZT}6gxBE{LC?9{vVC;0WW|0xpveAlnz7@Hz-zj0$Y#&2gI9@7~2 z-;vD!%}|Q=IT&>&j^!vv`_T7jA71~PK0N2~|4ct;nQJ-PXE)TDKHvGeZXfR7(LTHe zHhnHfnQ^&&dO+s>PaQLlJinSgJm*CF)S`}T$&Gr<$({cxyFRd<=PqOKHk3Ke*+}mH zXdkXq)8}@SqkXvcqkYWy^!L`7KCF-S`4M&WpKaV1ILBph z!(&0T&ormc)iHhI_PJA>J~yCDpUy=x|G6JT$2k&p#<#^NN8{Nl(uX!iI(>LtV;^(; z=U7`Kx#Q5+!ANGD8&Qt>#(N}gAF}S_^da}CZ*j+iZcd+@P>znX9qQb1Izr~08Q;!F zIXXW)#<+dRfX4{a=Q6*K%b;hZ4;ifM^x@iz`nE%)4;gTsnQ<;c+4YS)@WfWzo8;vb zX{brUGKTGNVq5+Q*5+HRh-q8jucIDzH|fvvhEBPSQ^v=SK&R3vS2^X3Q^p}O(64dI z8#!el4Rq?9a@Hx=JLLwaoWH_EC6RvaO4#iKE^Ni2M`WOsytSV*R<<)v=Jb;}ePo`m zrqx}Iw4*EK*xrdX{rvU={CuRJkMZ;T{j??a-U>=V-1(NABWc|_D3$+V>V^cR*+J>) zp!94|S{9W42uf?wJF(o}l-i>ve<7vASQ^h#ek;?O-z6wXi}als)J+RYX9cCd2c?-o z>Fl5+BZ-xHLEZeIG*epM4CH^al>Z`9`=!)=8L9n3YX2Rnl~s`cDpLEI=zblk{Zwkd ziPU}~wckc+KbG31k=l=>_Pa>!hf@1}r1k@;{UK8OzSRC0sa+zq%ObV!N$pRO+IOY) z=Sb~4Qu|A!_HC*CHBu|9B)_j5Dc+)nw9A^v?=7`5hSW-IQW8#55{^<5&Qg+@l+x0` z;&(x5g_O!umHuJOEPL*@Je1)GD7!3+)2UHrE_` zdvlEKrgW+TMw;heE9Xmnnxk{`J^eg?+ghwM8gE(+YB5DLwyp?l6wtV&X=B}4*ifTM!eK^#_5w`J|)i^v}V~wJtykKnvEW)EaT~uRPQH{<; z{m2&8_^{|G%ZqBnvd4L7%i@o7_DkOS`n?qC29R6<2T27Ac)aF z9^jZE$ANjaC0Ms-g!ZuGEx`gBS<9z@#uG&~{?MM9{><}XKPImh#9*`{8ZBBB)0kdN zqYuV4)?<9g6lL*kQH=|Wve>d&u{aJZ%Hs2)8e@yG$bVH-<3ziM8fuX_nOJmv?NyZ6 zdPRwOMKyLS%Jj6N#8wp5IHM@BW<`n3ET&=3+XaaKt0?j7ixS_XD9^8pYGjMjy0)lB z$D%xMD5}xE7*E`SSlK?0&zVJtzgAS^w4$^!Mc3!J8yBU0b5V^hMQPt&RHJjT`M@okmGNA?D6Myk zYD_LltG?*^9$J*vYehBoDN5_Dq8f)3<9YPTdG1n_)&jkP*YxekHQ)!rC+%M;o~&)G zQ&^+DCXRboGPf}{p3xe(qf|Jn@;WkjCG&2JToD(pX&+ z$9<$i8s}?`js-Qy61Or7_5V;4#}_<>H15^JajUYB#{QZoZVDID_+4vkTUcW=&9g^A zjS+rJ{z7|{%a2-}XCU*rd~>_L^0NzSwa~uEHSBo>wQh8@&Ml~Qt*|798#^Nw)_Ts-x~`zD)ih0sv9Q)zj@C^DZLMLC3;DuY=Qvuo6|~jb9zpVjwJvnD z?kZ#px6Ng>+?^SnEKC`=WxjQubJ$FRazo;r>WLTX&VDwT;95 z9|diBC24haxIb0Mmf1t|1vT<(J4Bx?WGDY|Nm^$)++QqctE0ocu+|8NsPkDMA6^gd zmZUY(A^Ju^zdk5Q>j;PYJB4hWXx4i{jr;(I==+82DQ&eLE zyBZ5Hy`q?gxhg8q|GT2ZpD0TF$f7)3*<(ThKYAAB`EXH<9gFgOtf)rMVmt@<`+k8q zvPEevE2=TKD9`Ric^+Am);C2pjwwp(`=T1B72}zoUUUWSSCrVt`uOGA;@yz^JgGN# zk*~KSdxO*jO^(cw^qLQ?>DTVtE#ksFv z64B2~(mJOk?y4m2BTFLsK}lK%mqhfFlC+L4h5O%%bKj#RqF?$)w!Gat={w8uwZo`H!7)S|TvV#F^I41T#`tV{1Em1vFkOs&R)MKUim* zhmM2Otsez6Hn*b`(0HKeD6@)=(!J;?ujw<=sXi?^8!ZW)jhwqt2O6g9grdFN`cXim zul1vV#>Yi9+S)y$fQ`$GYSh_1qJWJni)t*@#PIO9TmuWSl#FaXnf%kv+(<)g>6-5S z^!b)p0gc@(j{+K>71hXC9tCX7FRIaCc@(g5by1C4dz2|)rp z2cQ4T&(bsJe+Q;tY}tGz8Ur=;m1ulfRAVDeeI+&)6xGOS>MOCau&9Qqu_w$bO?mDt#=D9?Wu)!4l#&lien>{g8D-Ye&+iqgVY zcBz%ySXfk}Pf?yH7p3)EQH|4z(ppheV@5Ha=G)4Ztc}q{nZBcs_$PoX&(-9cKSM?~ zNBl!Hv6X1tQB>pOq8hD=`Y~49$WOFKOZ?iRdH!6PbMsCAv07_Cw)o#!$andpWX_D1 zSCZD3C26grJufoi<|SzjDoN{@lC)-(q;*?KTF;cEwMR+3E-y*zwUV@!m!#EDlJ`56 zq;*h9T9ZoBx~e3tMI~wNRT7D-OVWC`B(3Hp`PHc;t=&q}8dH+inI&mmUy{~iC28$n z60aLe(%M}g^?58l4vBewqT{!MuMrT8`Yk^ij@#7X5Tz(|M|2v>uV) zG??T2LnUcV32T|BB*b1_Xw<*^nwQw)v}nB_8ucF~X)P^DtBsze{K`k%rX;PsO42&9 zB&~}|(mKzNaqdcaJyVj_PbF#9_HHAc4wJ3^8Q*XzkC5&DvK=Yg17&-#Y!8*~ z;j$egTm2K_qojOvS$V2jBb1*g!<|*iheDre4?j1u`N^|uZyt26cM^W+w@PCfTSFpa zA%q%#738miQaZmtwpYvc8rfbe+l8{dPPW&}_6FJBDBGK4d$VkBk?pOry-l{a%k~c0 z-YMI=WP7)4?~(1jvh`$ppKRra!ubcJyhyeW%Jw1IJ}lcuWV;x@0^jIAmIy`h_r1j;l~>vs z?=ja|-}B930gt(+yCQ9gga=yFTO)0QghyA?c#A+9Zx=`pLc%Tl^k5_`oivtcdKl7P zNcd=+-Un$o(!NOeNSDS3iuC?S2Oy0^8ij-#d+CFaa3eW=2-2bDsrmw*n|b&Hp5qq) z!JJTL6sMP`8vF=0fF;=rJIb~bw;LkiQRj49B>pHrUn^~Ovdzl2UbYRgZ719IvdzhM zL)o^GZClw^%C<_j8QE6LwnnxcWV^9!SC_5)d>tR&((5DPhE{sL@>DxN+B70)hQt-c z+(i4onYX~W4+{7~Qr2e;{S$Y6?l?#4^%-QAl=XS!d@1X*$puo@=ah@2tj{bLOZgJ)^|>M| z35rEIb3VwzBrxglS7x&De}_p&pGp2Pp|8*Dk4ssf-Jg`QKF2>TWqqdqri{y8b@ zv;GTG*6040q^z$1UXilC4tQ0{`fA{HDeG&3H>Iqv4BnQqzCL(Y%K9o{iIm@$?FX{` zkbmFle}E2*6WE@jr_=Q6)v$o5Ow{#&+R$@Xj6 zek0p&WxG_i-^uoS+5RBgA7#5twm-@CXW9NDTm7<#-=zGzY?sUS581AeZA#7qe78+H zug_4;q|A@S>HKQ4Z6Vuo*;e4Ryy^eanuLQ*)~z|Wnxh}w+03WLz64k?RNkJNzF4yip-t~}K}5(O>fk?=XB$Eq+XPi+^m^f0XaiFj;pqPY|y zrt@=Udzox6m+cj@ohRG*vb_@5QavM4p&_80w9KnzBPxXp;^6;OF zZ*M;uUiszq=SwG+ypA#aiL*SlV<8tk0TJ(4h17pTm-LKXtdxPi_c42N zd208F?{!XJW8;4_&pYG8_eMkhV>pq{e5OqIu8%Bk$rOKdC%5*mxU0nwO`B{E7Ue?|Ekyu?B|ve&fF6u!yG><*B{= zR$RgD9cf*=JhhMCnl4Wb_gkBnr}p)0@fdJ z4O|Z}z73M~tUqxKma_h4YN(Wl$#yT<>Tjv`k+S}-O23p+e`B?u)a&o94v@0`_G*-r z50vdeven;Y9U^7@eb!-8*57K4ma_hCYpj&@H(WfkUCh0W zQD!FkGpdbv9Gouk&5-Q?*$$NL?y_x^?F8ALF5A3p&yejz*-nz}WZ6!U?Fq6yQMM<^ z_GHo_Eg!PCflj9ohIAyvOP|=A0ec4ej_PAD&-9@4+qA~Loa7Pk8(&V;|q+? z8330=A=%iiLw&CTZM>d0dM1Azb>@B(uAvU{=j1TN%Im1nNMn%3BJq3OBa!&s?l`2Q zk&Z#)cf8|~jzc;g>4fss!7)_Kh%3wUzBl+(cZgXX|J{26hbHuNWl{V$+hXns9A-$B zviG=q!$w%YhyMxV?-jF7$@JTp`iGr5tl!Z-iz1%^#{36S`=0^ECZS%QI^sVV`Mx4Y89$KCSOQGX!{(IYQOan+g6-&l3y3R5U_7CRC9-qC*{3UTL- ze0bkG#!x8bIK=pm{R_n(w=YEEAMeMH7r3P}NYzL+<*DOhqTH@Lb$lExv(J>LPKfEn zmG@Uk4?DhM4>{39+w?fWm2lEuDB8H=L1ZPIY@&7d1jc#FUntJFl@^KfZzj&QZpf3{Kfu!d%s zcs7xJwX1XZc1ziACEKlKyNztOm2EfKc9(4r*={G>?Pc3j zwmZnSmu!2>c1PLnB-@>3yNhi5$hNO+ca?2F+3tp!IP*_D6TGT3pZ=NS+rG2@|DgW& zzZUhG|9?#d)oc}+lpZnLMKFd(oM|6EG*GF-E{MJWqeazNJYki#7M`(R))<e0*%4|F`^DPk!IQU#6fleyho(|E1FMOQ4Fh{E|j`+^T;cRtGKfM-Ib1iM!dPxdV|-* z``Xt3vb6k?p&~8631AQYYK8XKN5YS)LiWqj9mH^2o|YH;*J?hd2YxCM=^;Bzlu5N!5Iw4Ax||`q~)n48DlNIrWgnJH$KA>?$KB86Y{hYd+;}6)FxFv zW#nq7((*)7MOvOW68qz{eeMg4n!m+zdz7W+*`JEEJmVuh#_KgpE%xBr4fl}eZ7S08 zWR3Lbtj91tcw7qikf&TK((*Km^mtOw1-1BnFYlCwd&rX~6=`|GM0&hndvM?5ebsOe zdHSOwEzf#L5B-NBgev3UUD$9BdG4YjEzev?k5_f%{KUq&;NIl+NTuajjEb~8hao+F z2=`zt;U4mQMnzhl&5$1RbsQXnsW#H1EG^G&RHWsp4ffdB*Q7T*R=M`e((;5wMOvP% zptkb0$%x0ou(mw&P>~*K*6S(IpiLeL*aH@j{C{crUcMqN-)z%1et8xg|F{Ypn)Hxw zjVsdftuK3=3=QtfT&wMxXv;Ud6>0hARqQv@G|jPzPyC|Z@#rwUFUWV5(xZ#+!6Pv} z;yj0Y$oGI1Y5AT{df?7EkAKvnR~?%4kni&<((?VB^mxPWp&Vo5COzc4uZpyMmnA*U zwqvkI$0j}Gd!mZ8eD5PY?hTL8sYws{PNgC(-;_v?8M+7eYmTu=lOFOdL`7P@b&wvf z+dYV@qH~iT@=ZiVTE20R9{cM!sLe6BwovcPhuqDtNXuP&>Cr}eWqNGdq=(!QuSm=N zZ|Tub_u&4~TgV>D71$-xBbAmrycKD=pDR6v>Nq$Cd+?XG z?ii`G+-I#w=goe>ryaO=nmAnTvb5ZDtw_t=Rjv0alM^0}iT zEuT1~hkn_o%mw$k?V~-)*VVAG( zRP8qeKQ-^j;<|l@q=w{I;9u#(9NbuT5Dg!UVJ-@WIi#`d(A*_vm^mEgFd2r$RUPIW zM3dhV(~oQuWE@Up47q1zAGJrN+PzW@s8qXE`cdY$f?BR?<)W#*k4xn%)=s6oJu0V9 z`nL5@ZoJ(q7fzZ{hw_vhM`CUdedU} z!IgAjYYZYmQA`xnjykCBCMe1XYB+-0yHX9SR6~M@c0v=P)e%)PqP=ZIUEzM~)KEs{ z4buTJDsPAmh*9~T?<=0~3}fOs#YCPDf(0PhRUAfvGCV&7o*z`HMpdc^#>8`q zi9F{uA{?G74x>OBp3i{i(<;@JN;N6){2Vle_v>lab8iY<#9YXZJ;}PBo5!Qm8Fi_A zHI4*baZD;3I(5h62S72{)6bMx&V_l2g<_&uE`QxIbUqM}acpn1eVjtW>ir)p~yp_nKZ{^3M~aGQjH0%gQe1%CZTY+T+Id?+U3!#@xKJ{^$>AIjkK8TfossXnSy9|VZD z(5hW^wk5JKqE8T#Swmksh_-@e?u*Ls(fCV?$n!hO8v00c7DgY$FybH9$bA{lXdAS7 zUsy(;3!`mOD~u>6Vzd)1fYElygb`&h`W}pyR;q6TKs#%_U3At5Ss2h#9hAob9d!1 zt#r7~Mk5R3YEi`?am+@ftsGoqpqXnK!PUy*a+i~DqjXwhX}ncDts~IpwY0QW7h3#7 zpF)dbB3dWG0%#qBOlVOCt@S}`-72+q0E~aa0eYwC>~F}zz}5vYv%cCmz)po`Zo{hZ zNv@3r=J_3EeXXsjmrm?7T5l6iYy#T64K1+^gxKk*6=D<<5jzVOKw=6qAx0U*YCtR# z;QG5(nyIt1k%e((ob^@b;Nsuw%hg73)mdEb`tog*PK$p+AXgVpYZltPT1#sqp>-Z= zg%-s`w61^!(3*oxXi)~Oj-b_{O0^Gw&C`1Gb;du?6$aM9SznzUU{^siw@Fp_1lZXE z^ZbsozS^(q`dUEio#TmJjW%x+ORSR+y9TvFjA9~Ux55I5U5`wNQ3kOsK&(rE>o%=) zyUy-F7RJ@ZSzlW@xbB2zZp#R+tt>8gefc&@Utf38_*U_>?naxprKQzXXx)Qap+zwf zE&ka<(0Uq~(4q`l13{~QmFice`c|o30&K6KHMet>b5p&)jos_#uQA?K@9P8PP4!(+ zHaFETTG>tY-6g2kFo*<2F;P$-!UBTgpT(A-C?lw$2x@SZ8dRkkgNQyt6QXr)8xFP+ zxwAP)2gKR*8g)RVK1ia)ah0`%ydoOo!_txIaUEHSA(G}lul;K;F;G2$76528hC81GF6dM0H zEh75eghm;m9gffrtx^Y9sRM(!RznkFb|&Re8<#sN2kWq8QV!H%Ig>J4JZ}MG;yJ}c zp0B4p=imI6*vDWpb*Mg}g_i~Sw zST=xpiG^aKSn6N_vrs7^pgXaaq&CnEHO%rS=-l@)Z~d?BM4=8t=gzF{zahh`FEzC6}jhgo^$>k1kK#6s_@D@&r$X=+>^%6i$C8EMw>Uwo^Q_;Mnh05j3_2zbO0;>&ECl5SV9?$E&-!CRqDb3 z&`7N}N@oWm3j>;?W0Mb9mpOnAf@W@R1khy`kh@HL8*=o#Fow^;v~^iLpF_~*&9!_k z6+VZeR`^g%#D{;F3w*{P6F!u|XCe4pQ>7MEsVf6SIy)X&7|}Hd$$X@`!9jEa zG;`Nih4-WzEF#bEC~Ihe<}8e^jA3*ljolE>h<}2|yWTRoP8gkxT46*n5u>TF07j=H z6GoK5=ngQttxDYz0Gg)trt545vM`|AbZoMQ?sfp33C-MH5kPlaK<*myZ3v%RV)&dz zTX)Cv;hzBV?y`LD6h1RiD|{#>;&TZsfY15Jgb!u#c?f(KRjK;}K9_2}xjMTHS(wiv z#A6oFVuug^G+FME$Ue5%^6~tRvViW_kO^qz=XrC_=L%Y198YW>+Pp_Bv4@4&eAEgt ziiwEb01F^?H8LSa8N{9hvBv{k{L55Ox=Cj@BMakt+*wY~IJjo&A`Pg`0~39Z{vE3_ykqO}MX0OD?BLW?qJy#iVlY~NxVj^1Yn+u2xGNDBowAyF-sD_NnW>jrP)nrsAWA4W0 zppfg3$u0FiGS%_nu!fAi37yU8BN;ym)}m}4cdN-PoH!pJ5hpfy8B|}%Pm4=i$2|Gw zd@9`Hn%-B{@vGHN7}e{Lp~#6!)pNVTui0tGR7!v2n#*ujH-WNHp_qtD4_JVqF35xm zWl-4?RJO>dE*Z6HMs?1pP8qdv0A@SrI+Du{mW#W~Y_G9!(Re*H3oaV3n^WFKgW(GDpEBH0;@T5~NL&;X#Wflh z5EuWpp~OWQaScXX!!v5{j2f0vLxQ0ArysGO=%6|?sNwNJ?TzY5{3MQ`hGnq+he}LC zP`$J@s)IO2NE~BfSK^?UC=ULqPsDMuxQ_y5#Bn&{I5eXU&Zq-3YGg+3AA~X)3b`?n zefm%vjdw7Zo7+1F>N%3zJ0tCS-Cs{jfqgo>UZ-O`Z%mW*s%z|e9W6X&Kv{TDOvHnK z^bi=%Mke!089c^=$1xc-E~AdjsIdWzIcNndXI_u7B;3V1PJ@tnJJn9VvmzR zE{0(VgkqvV7QzAoxm^55fieQgBajIhb!tYPl2IpR)CoZ>*Fhm1%LE&XcPbn;w}?)0 zf;q_v=7c7}oFT#RkCjR=6cYt=FDxL2TOdeY? zCz7d7B$I6=@d)ve&ahxS_+y}c72gO8jJOK-E{~>W71M)3yW&3zlo7~{2;};VT9{GS zWYmI;x-y96b139)&gA}ZFK4c|;dl$-t2y*tqvMf7-vWE+yHbZ!(xLAwjOX3lX1qozR7?waNCJLknEFh4s;y((M5yMKhgs8$+JaTe;Z}5tTCkbW|LXfHFj3t5E#9oEHEf0f-w*lz@QH@ znN`Ywu>>&Q&8W8n61$@wi1d7J#%s@aEe3Z!-?sDVUo5{bt~SDexJogRt0Q0mt_~3o zQJ@T0KZmQIX4Jl8QB#-wGMk9JM;G8|H!pc# zfk815jH6%y3=Tsk^F|pkmIB5%8TC~_VjSv$$eFiqECzSpzG^aW--)Y7!+^L-F_EjM z!2(=8UOYsBGF<%?uKt`+%QEVRz}pF0^>m%(k#SG54_yE3Pa7YWU7oSesht7M-0vA& z%IQG2-~wH41NHol+*!S4Hd5~glyP4`jxy#JvM{FdYJF59rq*`o!bI|6sst%B~ ztY)MaqgIenOoZ%eSb(9+kqI)&K(;=Rty`_u4q#oQ^{&;~LS$iB>*_e=dxAC&tm~ke z+ps#krrKCo?#|=e5LRo)@VTD0+Qjp@0d3xfmd^&l=SI{DABu_ic(4FIw;>Zgl)Im@X!2G@hM+ddxG zLum8bSzHZ*>tWOiE{ch8y$cJ#^)FhQJq7)#9aJIV?>NMjdd zqa0)h#30*{hR4JsYlAj#v_*EfAZv?SK}InVvi7im6;^{xkWmJ*w`>?Q3kSEKz2^Gnpv&R3V1bY)jf1J2w9ldIXYBXVY3}xdqOjJeuUR-%gbG1z74@O z)4_FC46ebnJ3AiN5VU#cTU_S}uA!(EToe=GItUhkYdA8&MH#r}1J@PR>auEeX|=jI zAa=0UK164SA`26{0#TV2w!k5FI5cxtRfoUpSYU~Hen(khmuc*R>{18W#WBdn(C~tI zWMk3hU1gD7DaejMtstYA2-(T70A$A?6J(TuY&U%Txv^SZU#%7fyiU=of798i$ilpC z1Oj}oGd(q_E_bWLYXUTLw?uf|YI(UU%(o%9uCETh8(Ii$^WBj7Ae5)sTjOb+fi~|J zOY3H#H4(K!i((>LvtR+VrXdqrltJquEU-n@>i%lwRjYfd)m;Iz^K^&vbv7GWnAsv{ zjV*SVT>#D8Bh}$A2^U*tp5IZ{*!|8L^PDwyk5j%YX1!g=K^Dgoya;XHBbMO9LU0ah zg&@U51h0Vw5WEbT5Tp!(&w=1StJTxh>d9*Lc!2L(t-VlZ*C7kz`=^dv4r(tt_^yX$ z?u7`x7cD+_$@w;9$vy25d(tUC9z*X2j`3nVy&KWyyO8ZgJ$mS>hP_!cPuy0?(uk0V4ru|(XJkf^6cYjY7#0BJ zU1S1;GJt#oAYWChF9Rl@XuVH$_8GD;ldqgr@}0xvb7W-0p({vSr!oaSu6dbvtN;gi7azg z$!`vk-=LZMHA3V!OT=9zzKzf-`JMfLiwCkCZQidI$S(rq57Y_}iiv<6R4zb4g#EmCIs)yP8S=XJ3E`|P`LQK&bI8&PFL~#Vi*(8DJJs#c36PJ z3&mj+D8us|;Q977sz;6LR-?A5QCkK6-vNd21Z{8q_j#3rk7fCTy!MwLJ*CJOXbSU`NwNqi_!MxcWc=%54K=T1IIZIFmqy52XM2#9A z0Qy4feW|m5BMSo>;ZHGNN-)X+^c6I7BO`!DSwQX{?%NPP!(;e-OnTzsq4x%z> z=8mcf9|Xr)M4sPK*3jXWi+89k2Wu!zW8>l(HA9s9 zv~@~6pSEc8PPTkb5ZMhC>ug74 zVP5CykYrU|KRFjxStfye|GW#C!>Tvyhpc{S?t8Z|c{wwKo4TW9+q3lqB%QJEEXtwU@$G;`O~ z;7Y++Vb@w>p5IYc*gT8IyWBxG*VYFsY+o9_HXhjsw0YN9WLFEa{ZK2&C?-NS1{Q$q zKxBf9GLYQ{WVh6)n`+bz0k5%I^$49Ei7d?P79EnTusa=IM?o`pM}*g%mY2K2d>gXD zZgOzl5QA$R?cN!W>u9ujcUWAv3$9~OE4V1GDy}{Fg6PS3wE!}{Tt{$G2CnY4eblzK zYU^6HWv$wx)_j`e3utngTD?qq@j$d~t^G8)b*)}syeQrh8rh$>DWbkKYh{}Mc&uFy9C9z-AGUr69whJIOaNu1<_GPP(u;a;951P zRy76@-Oh*xy3;Y(M&wS%ARUlQN23nNnT}!N`5ne{iitd53=44B6Ngct49`cx^Zjep zh*~wgR_z@)|0r5>o4eDozjfXl0WZyT4A5UsO!9BLzSr{iE9kW9ycIv{5{MvLb!!I*eXF_Gu* z!U7zARUAfvGCV&9o{y_lN7kybf#>g`DZF2gvz~iL!bQvlH{Mw5dea{pH+@0$u@cJ? zn3q^6CW_@tSU?CLNeC!VMl2^Hmg8&H_#lvfqdpwS@iq{53dXNm94AQ}U%|S>K`~Jr zzrX_AUn=gSKpAo55yymDb!x3TB?#qLG=+EW2{sh(RA)|3S+!WskXU|$d5MK$qF5^M zGgO37hD=U|lo88R#4@>7O$-8A9rfWrCfh*VIhnX>aZHmqTEe=-K`~JrZD9d%tS#=N zKpAnIgE(f^sOcX~~Sb+PRi2Eo|MjV$Tj=8n! zl3Fz<2xUvHx|PoOikt9t>0CW4@)+R!T6@!K8))X{)rOB2^DPC>?6Vzdh^01e;SBl{m^FuD$muB}y92Y~u$ zy}mlz6;!&MR@ki0(s3=Cj~K4kEra zC--1&_~`bKMdbM%Wewe{ISZq^V;IScbsmam#24jw4_ZcxgwY|W6-E>jG4fxAGZuz~ zk^eHBC&1_*wd&CT(0C{SP{B9h{6ohkYv^eQ&^ zHT1fJ=qw_7tu}l#e%&JS{Eo7QUeuh0(ep8k_`;jq>+y{E+8ggR%ji{MbT(>b4N*+Q z=wetv#OEQCHAESVmVnW_wd(BvkpI#g=bboVK=10Ysj}D zeBO@Xb2)8&7|(~V#qmC{eBKv6d?AkTp_quz4X^+{3y=vP%HZ>F@cE)veHQR3_V$}E z5RX|v-#C2a?KfXXj?>>*KAzuE7SLxJG6Ajp`rSP1BCo&sCZ3qQ{^n~->?Ca&kXKaQ$p?xy#A7Q93Po zvChx&wD?*a?^tpnPGD5Tlrg*!!>mLvJAyVw6FwC5TnjnY(u%Xr&Kz_7So$u8KM?3w#-hJ!uUG z*T>MzwT|Fg!{Tz+mv5u=_4NsjuMtn{Q?z-lEv;5U>oe2}EsBX~{Rj)7^))h~MH#d< z1g-V!)Vcw%Wm@kio&Ag~3~YS>Gsmw=2iPyr%(blxp8zW@FwgHO>uX(2y>w!~(t2e) zvER_an(5MtKPxY z5}LVe1XsPq<*qN^M(MO#(Rh74t=4GsvX)kz&{_kvLW^P|S{uUxAk`w1^+g%9x`WoX zb!zK6wPl^!BEZ%Wt+~zX+?(n)c5iEcjmb@QAE4Y+N7>v|U+I%sJtU~k7({}im?)@i zVF5t}?~|HKMQeCE`djC{e(;jJJg1|t_Fmsq*WSxr z+@{mf$x`^E@DRHSh}}$z3H`J(-%Y^Ah8?)^AZciM6sL*3kcz82>}Jlh~;3!a$ubr83b|? z>cfE?XajMlVC1UBafrlmGOSA+6cfcU1s34`X~<+XQAQj`B95_jYIL1CEC^*Pn!>AT ztPRB*?aawxs}{>q63aB0mslt!ie)w|AeNaD0t%E7%Xq|cOr07R1ablD!+{)Q199hM z+^WTKoWyYZdd@C;1yhy!Dt#7O{r6p0zmg@y?b@WS8;^_P0_K*1@M^;Aii8Hhu>U>PHAUa zK<+Z}ZOGAcQVgH_Y3s~*J`bSHn_>A(7e0$nD|{#>;`0D7eT?=U39D1+EtAa+N9tC?16 zuCvvUg>l{CET?-NTrHrPyC;I{UW?0JPQH!OX_eFXz45dv(B|D^Y27WfR!6PSqL_%* z`mliYwFWYwMH#dn0j-DX)S>{`23l`JowY$02KJD%z8-Uc@kML7M)_f1nz?^Qa6M~rx$DcfQTqDgOWtzN#?#^}-n@TWTF(fr;QeeA6VVz6yP$Ol zGNDBowARh`QEO+_npxF4t6FANMb_Lc<14Ci>t}QC`X8D4^5L+xv-T$8npu4$<43{P zD4WOKT4wpkEq~zQRiOGwQvJ5n7epV2QN8uE(HBJP8vDYp^|B1+cqq#nqL_#Z-#i6F zryvt5ltHBiR5DprnN@AFYJ&g?-$(^w`Xgk2^2k^o?uw|?ILO3nqj8Xlw}IwCDE{wz zHj+T5z_0{DF;O6w!vX@i0GR|r8G&q!Kyq2tF01OZsxAoR3bf`rMdmiwBo_IU-_DuZ zdONjsMW;6U4!)}}sMo2<)an{LwH<}X0w@a+iiwEa4htZ{7fuNg${?~Oh-{HnU9xJ^ ztm+&PxdW}?solcj@VX#a^BH?n&4Y8Re~%_J+gamqW_Bxy<4)L>I4CBH;}KXu9Qs95 zC{RWm+ar!1S=BA8wh4k*jHYl9J!}x}`s@}P!!}J~=qWKgYGR<6D2A7G3{Q&dh=DR< z=#LosWmVs-+9j)Y%BtQ$BriiDH!z#~(mnX}v%z?M;VUnrc<|XpM(?-zH?Yat)HQZ(4iFx%Ls{mOVj>=&!2&SweOIzJDTBu_@EDR+duG)hS+#or z<8!ovm2=n`VoA8ux~B#qhn+o~!_MxSgtIvJl0d$IVF`p{qClGA=e!7nFL#naC?k-A z5Xh*kIv}g|%c^~|YM&sM=1|BTlFgO-;mBEKlnuu_0KS@u-A~6O6T7dS*nM<3B~5Gv z#`6woGO@bGPVB+LV|6GC4~mI+w1EZiSQDA>pbQ>IfyWV9H72VL&#FTM7<`ozSUD4W zgeBol>=+F~CiZY=Vh`0MoQWMLfmFh<1VS-UAbf!n0@+CXM}aZ|ISqmQEvrt>suQ#7 z_^cYARmTM3$jg~d&*pyhciP=~hWwk2$U7PCnz=nuha_`*yq(+ews?#VuB2(+6z+Ma zH<@N#W2bq7(Af;iLWg1^Iz3?lP_`5(C{PBSGeKv1R!z;S$yqfqtMUOFc?r{L{!9-d zm+6*^JJVA&7MbbE&P-2q%6SdOnf0?IF22o4;-Z)+F1~>X;qYZlvV8R$iE(-rp_daEyylHw7@dS6 zy(^n6UR`4s?|gxAGL&VKDJFt385S_fry&y42Y`~6S?ZYhUiS=DrLBO8(h65t8U7w8v<|ns-oN-krT@;)?x1^ zXWnl3ADOp{Fr;@!lX=rMcHV9m7;~U3FeoO1aTP3J-sU2cd7}&%9$?&)Rd)p>7N8!8 zoO!#)VsPi}t|s$#pSXH842Y`~6S;Z^EWp+4#6uJ)!_~*(>SI~8IIAAcst2>`fxzcG zp^$qrve!Lk-S!qcv-hx_J?}w%{NRVp2T)!3!)Ew;?_P}OJ=tXHbd8<5CxnLwW#K_F z5f8pB2pAqjCR0ZlJYEEk=dJ^o(f<*iB_<3E(@NwB-{yn)=r@JjB_A;N|SI- z5HCp}PrmY1P+t_6D->otM|)B#)zf znd>`Q`*6}*(9FG^#RoMFU@snd-mw5Yzax8luQ~)?aiTW&J>Q|Rcd~%i^jV~L(dNCK z4W31MOBlU}T46*n5hK0{2xvY+CX-DWj6MdV53}n101)2|1ii0x_BFCFpbvFyawq*W z2hg|B%zYXG^qB?Zt`OgbTu!_n!{+LdH1Dd(A`tawbbUhb>+>i47 zj-s*bWxcAXS1szzZM!s{xw1H6y&%vb@|?<=YTk74>qr zPi}&=fNdOs<+x+^z;?8|Ry?luX!F*zxYiI{In)X+iivP-4-3GxB{IQ98Mvx}tEyhL ztyde?tMvn7J+<}@I_rfjOson~nH5&+5bF)i+(z}`4{)`XnCEwt71mZ`7i1ec$kvZR zwj&MK#v|JaZQe!}S&bmu8MT6pVj^UNU;)VbAroYjfvh8tb*NYE>s3R*Yfr5@SZ70! zg?V+*p~`Wqv%_mBG;^Cocy+eC+!f~A5M1pYTn#a}hS6^4cwBp-&D+G{>Lj@KMy=qY zm)#d>)z7`DHhwE%KvM{l25S3YB+d0I>LNnK+ zK731WJ4?*-JIV^%N@EvfT^(eb#~?eBhPR7Hb`;vY9u`@5K{gJxf{bD!WYb^)5Kc!X z$S4C@A0XSgUhP<~dIh}rqAsY;(Ak;D!n}6Yp~?#D=kPiUnz>!;ao1a4It=HfLqCU? z-%%Lt=rHOP!|3lc)-RsXOtg8sT1I_^(b=dKMidh1eg6v_`3Nng` zkUa|vh+e-C4F$?Tb{dfVtzMm6uTBhjJ*QQl*Vzlm!o2>bLzP`G@9=sNnz_>>yz-Wp zdvNz{2(FVITqnlhdWm-P@wi?_n|Hd!H9>H_f?B~vF%hm0VF8r*wlrB`l!5CU;F?*l z&Z<{4>eaM*H6?)dk?!!Z&OSjFhBgy{nMHP<1MO32=4RE0Z=juLp?Q8sS!8Ev@z!uaOu$YssVckulV&D^{QzWElPyXJfwLhllX*c_*PVGO000>`?CO{|y$U^|Ks9xP4Fxgt`@s(px-xgVz$s%W!EOwZ5gJ$lL`tY5^ z#g>WZca&9ff6OZBP6LbMq4YqT_lSk^ut3=kwE~4=A}D-G8KUI7(*z1-KzR~S9uJ80 z)k=Il8Fc$03ln+VStZXnM0SH_?&*5man+Yj`|>-^*W}JjOha>rX~LJ z;1})h`e68V2kyA8kY{|}wv{n2L6zIC`aQ27OLTnOm_$c0QFJH40;1y^!6Z7$i0&&y z_hr5Myk318gmyBT5Vj8OAcpp(4b9!DKi5IX>ETmb_P@^fT0B1m#>8`qi9DYM3-Ek` zIE(^ic>XgyUskVvs8`?Bt8WA6r=vAIFUzd+-VgAS2Y1fPcXkTwynJgbW9FsFFLHj7 z7|+6(5+lV#G0uergf?43LxD14ENj4TSL@aCdi7fn;ALn+@XqY4umQTWv)s;z_nR&I zvy*P%fS1FVcup~q=Xb#Z4BaFSqd*y+w}j^v4XQ?yB%@2%mLg`23T$+Q##F7HwV|%V$I3^Bii055+`$-h>74c?p^Dp$t9^ z;FE1owGFB!K=hVYeOqVmAPXbPA|!M5mU9rj3(Z{nhVYJ)vxq#uqpYD?%f+j)D~u>6V)QjEfYGPOgb`&h+7ygBH>gelpl`I^w>n#jEDWf# zjz`we<_@6mp_%K_fJ2TxvK-3e{^kxKzoRUiPBBn^q=C)jp)5n2*Tq8FOrZRPT7g0_ z5tP+e7bq!Y0);Z5Y!4_s8dSFiwM~QCDnQdxYq!!_Yh+yJG~q`yyTJk=c0nc(DFfng zK-{}Q4Qo(C8q}Tv$L?CYht9S`7UsA&f;FpgKZj#aXy!&lIPPaTdZr^+<1kCi8)8B3 zX{%#aqjQyGzK`0GgYFlPb0@TUBP`B+1?SGF6`T|k;oJijfOA)5f|D|E9tNC;G^m3b z)Tn^vAg#Km&ITh3vpmF)muqs2!*VDzbE6|H$5@u`nlv`JCJ(YGN3AN#eK_Wrc$CA@ z=8d)}4;PgCqE=8+Tve2_8XC(~V_63xRKWKc@O{#tK59@OG^izp;HKUu5>i(luu`?# ze#?P3W1lW0nbMy{K46Qdp>--h1*en&G`FEBP4q0;f0*NkMn!+Sj#&6up4#Sdt7Ty zYCQl4-)-UVR}G;NgP6XOn11*VVp^>udJk#dSk?{0eA5sPqrtHIM#lNEz&Q1V*wtHh zt93+gj z)P9X+J8=&C0ni^c;)%b;6}cF9&M#=%NOZ?4omFig6g_p7s9gT<4UVaorbVbGhy48kzY+j&3h zeL&L)7Ef~-r=q|(#TJha2faDYU|AxyWzqe}E)hMpED;^FULu-vuulzfmWa&DP+1}@ zuIdu$*bXOztFdU2%}2&*7a2&7Zilb3+NmSjnU9;-K*2kr9d_+H@c?h5n%I!ajcvDx zd447@aF1$-vIL+N>2%$Iopwy6dQ++UF@rCf>qBjTSD_LIJdO&Z{?tYp0`XeleuM}6+ z*K-;W?Rd;MvT?|SFJ<^TF4spLnNwqPhVOBx_r~Ue$9R3dV{)4BZ1O!aXZUJGIE)`< zTE0i;IMng5BtBDIRi9HM8q4-?EZdL1?hijJNAyu`MyL%&_CaA0nO5w;b#2)a%`W4*Q0ThIcU55gfu>>TVXfj!Q9 z-K%K(5Q%}sBrzP`SauklI~+08A%=}i0HbsDBfO1903;VMeVNz*SH^httkW&+v>+?o z(#_JVvEmhrNxaHmg!P0ex=2@g!xrPyb zE5IAH%?#T7T&i?%R4_MP?9AjZqxBA)EAA8dciu_iLS+*f=5jO46|`|o2Yp>}Cs&|$ zhdYg&;PdmKfkU?LCp&htj@s9SY)KC(>zFIfDt{}KQ)`Y`x7o1PskIu@4-IcDYd@G^ z&b_KE)kmF;t-tptnrrbx^=m4itB^kiZ>W?ZBNIVGFN}z}BD2 zJ#*xz-C3RPunoL~Su-Qyq1A~EzB@NT0qzVIceIeeoxQ}JTVbn@x*1#FoxME@Tv?G^ z<7rj3l4-k5JGPHFriBEK9UzX~DURK49UF-gN@Lk*k5zE5+XEboPSxpS&|Q=}N-a() zxw|3C^7l`NM}Yl3e%;zq*Zn@}aWA()Q`v^F-M^zWdDMrvtw$A}(T>dBkD_tGw72w! zILc!yJ1jCC#^va)srU7c9AZ zcu{-2#}J|Egx^?pg0L4B#m8;KMDfW1EIQEYuD@>9@+GcnJMoD8{c&OHeQIaO)z)}VLn zgxy7U8J~H60eX2!E;v; zKW->AAPvAb8BmsW+6>Fjwm8wtun3#?1GoV4x1iwBcXZQ>;Bg2f!*jaKgRV$24|l_a z%)@iAi9d3Vt(k{=(3Io!IH9r~$k)_|DOnKDql(VlYn;&)Nt}7mIP(&0_E9fjYn)k( zCJgd4efk&b`TVk*I~1ddKFva?923$F*v&t+v%#aE4_g#I`fKgMpqku-Qi~!PfY>ln&B; zXSuOGvfMsI6`lFcIHN0)IP;Tn<`dZLqdvmcIP)8w`3w~vYcX#omvz^Y+x$@cYt_u` zy}t)N*bO~Irz`%o@|>Eq?kn}dp1&M@jgraPy?M*DSXm4IWM${e@UJ=R+P2gS`cn)> z94lZ#4h6a*365s4B!_}8VY83=99x5<98I~eP~ou_Gh%YOQr417N^tl{AmY51uLydv zD=I~gq4QrW&(y*Ou+WBXL7Vx^m|s0=!|g>r>_$HP*UJB-nQw_+fg&}?jsJw*wm!Rm z!z;3DjZE0-iX`mTfeB%^6gK;)Z?HA&);bjVXN#vN@eV%jQ()?Fn6x1i@A?A-h#e*u?WW z*qYsHYduIeopnc+TMNxRf2BJ7Kjy9jK#F49&ISpBf+$K7aM8h0MiC6_YAc|w0gPbI z`I!|lr&SD?bIuug=G^9-bI$3RbI!^?=XO_Z_sp&7VWxNf`X1GNPgUJIb?R1ibx+Ui zw5gZ(^jSK>e!0RT5B3~6?WnP1@h{WT17*p1c^rgu093+x3|t83KJbZO-9lLv}u72b_<_qdlLc5%1=r(pp&Lfu19eUS-T!{L8e=jk4stDh|Rq04m|UCR_;T z0r1(H?}yZIUMpy1-Qchu4%s2dHab7p(`RXjI12x`>Q5{zayfK9VptFx15uWoC*dHR z1E3Plo4|!|Zi3I&{7|HZ^QJ)~TLgzKamWrww$b^4o<2)M#8LQ1&RZ20`2{+g-S#k) zCFiYi5Y7Qm3FqzMLO73r&({1RNb?ILF~oO4zE6PjlDRncltrcpowL42AZZ@ONN-m| zF90f`x2K^u5HCYw*>i)uI8Y(AJT%I;>f z`Lw+#ySL5WSIZu1v-d-`B@McD^?`0npdZw2e;j031E3P!rox2`>(cPqnqLxWeiRZT z-jSq00L}Z%#Zh)Hbq&Ux&73p_?3O_(vOCJK3xG=49cS1r51+017Nq%RB!=Db$j_2_ z@G(d~-deK|Nb<_&vut=i!59qzOAlFOd4gdX0F|&j)vz1`pRM^7kQ#!gAq()>6ihSxddMIhXv4E0$AMnm@z*vtew z8jE4m39MyR6rp728h!y#3BL;szct|#Kk|<>zd91b?;`RefYIZ09pke|z)x zE#VCS`^+P1E|1qE$EPE7gdNN@HE#kdXzd1^2pDXwCo%)xZo~nfiAgz_H%amAB;-ci zyyh3K)aH2bE!sBo-;WHN|od3o>V#T<(^AHi7O_ zhx#7PJz)hr!fodq1abmLi#GOXp3@fPW;DWK=3g-mOGI;jGi{HGqHU<~4=b76(FM7O zG1KNQS&%#PyJ#+Vuh=j565>KKO1xW-=H8Y#ce8Hd%M|3sn`th{J&YVIMQ)HmVlE*e z4Ms_f>CxQBl8{Zb8P~Q<2LH!@<{B>hXPY~-KwEB{Z3nEjUKFLaF@07j%#A6(q7css zy<9*)P*MT`A;sNvv@gATG|z4OGA`yj=t+BDR*L1$JdA?1OSW=6S6H>@a@&ptM4AGN zRbl#+1%V!16uXlIa#mwOPRRh6#VOerUe>Pbzjj?ePR9P2hy#FNZ;muSFOqOJ4#*CI z;S-rQb$Sy%oSxo<2{$l1KM+~}!U;MkJJ=$@+B1J{0U$ET21{}4W#naju5Pl|u)}(c zKxVl1{^3VkjFinwdu7)<^^XSRKYSpmwD2@rST1bgnaWzo)Q2q$nuUg+Wy8yd z4L_IAa9hxTs?qaw0n&w;H}aQK+uR^KrtNiLgtn9=xq{ODJ1kxwS<%)d6x~W95(P?VgsfR1wFQd62pVS z2p)AQc%Ln=61Mz7>6YuY!TOL6T0;jPm3H7BEYqXH(Xw4qMEf6GUNvm_B^ zCWA%WF`+)8-_=6DpO*Fu-g@}i)lnh-85>wVY~b^18;A|I*?rF1jQxUy)(8oGSs|fd zzUgb!S8QN>*ud8b4M0=*uZOmrenU?aLQmf&cybL+Fl0K_@7TbaVFTY+*nnNHql42; zpMgKH!L`B$f2^oMhv%Q@dF{~i&lP!Y3wxq#^$QzVCv4!?3LCI9r3|fpV}t944gOwH zgVZY8Qd?$B7;Xh{rY(%ZLcG+P^aly97ZUulB7$f(vE^t79E1NCnM@3s{9PfFfJi#q zf`3S8Qb_3EiU<{tUBv{W3but_9GA$MB))z~JTrHh8~fOPyqI{neNJV=RR>PF4MKwT zDG{t#S>=M)K!O{F1RF~eY}7Uxv(dpup@S}^9e{YSzW0a?L0fnekWMgnC83Q&Lfw)G znI$e3bh9|k6N0om32hP*nmvh-L!nt)coG=(Afrt~Mm;NHR6K2rlG=^X9Bgp2u)#Si zYOu|5SDWrw^&-*DL!!MaBx=S=Q(`VQutnHFpGq4DuX9=hbF+ah!v^N5sDYtH*Wpq< z>dOYV3LBia!UhX3sL{G^e*A5Hqf69Y!fyxpuz?k(FFcWw-ajde{rq&aUFc|VqNAV>g=@8A1Fgm45Vp5{*xt~J+Uuqc(E@b5L+H4v zBFB#PL~m~x+uJd0Z^4S%gX8!$W{d<#IuWuE`TZy4m#v6j+bk}mx=_POWT%kG!W9uI z5(>=tU!i_xO)9)+2%pI5cXT=O+d1U7NILw|+%GOle!GPHMwI4Pr)|gbbg*maV6oB; z+FaW)`v@i;u_cvVoDJ_5HaxPThKokN)RtliG=Wb6mkwLxrvO<#{a+p*1ITlK`LM#1 zr~W*x^W?cbPwPE-z|PYKPab*mw9%7?);yifljqAk?c&J;VxD&O$@wAsGPqcX2+mmNcJe|vvr#?LG zlbcYU z4)o;qkEeq?xuN3e{GQyp@N}>zHwio);>mWOr$as2X!CRdPqw%`ZSrJq$5`sA^8|c;#8}IjNE^k# znc26UQE=Q20LiKJ+V{m9ts> zV%9vU4*BLcot*}|HGeeH{E3HnYGbe1~-$BCKTi8y3(Co%O|=;*Om z@~1YgY|6A8D_JKq%^rtT1P#7#;o-F}c3s}G=1DicZtb%@9Ocz(ks^CAUO&MvZoysK zd416Y3G&Oz_{Q>!O+K08vq5gBe6|qQ^+|r(RQY+@>zXFmkCyR;=u?mrd{7-DDX`A} zRMzM;{7=*Q3*2c)p01M=SQq&WD>8#26O6qhX6hLpHh5w&BWQQ|remTQvlT_0G#%Ey zB;~j}Q*IE|9XDliH=2QR@lRXib9DX!>-^6x#osPY5^=FW z>zKvqJe|M5i9u4U74&?aq`-+Jizi*jD0zWSQeZt2E-Wh&Y9;bTI)8yXjmQ`4Bn8$* zzNAx$e5uY~;6#yY6$zK=Bn3_+S*z)GxlU4GJrb_4k&t}BmtIJ*qU&JvlI_?o*xJ3- z+C55d7rK~hSYNgFY+>z5SEjp7y;2ucU|rCwtf0!3*j~wM6%beJ`~}wePZ$0JuCh8_ zSg_r{eOPR}AGuX1vE9E$=OM7pV@6pzb}fpA;5v3x`?fKGe|fhn|JC^moH+aOvySSv zF>R99>LdkDBq^IjWp9->$?J5I0_%}*y+p!G?K3-JM9YiF8+0B5>pX509!aa4Yi6gt z$G%DDFR*K{?Gjw88-bg3k^<`@-%?6syL{Ga+TW`47uY4TC0VN(b(>C7;6#$HwQ2Om z!H?68;r9Z~8i`l?3)cAY`Y7JssYdY*T_AxI1*+93-l>xm*hMn&#{QhLFXLv2d8Kkc zwexk70_%}*S6PuDbEXCtpSyMb0=q=E^Vzj%rhSFHM<*$;F7mydO62=={sMOzk?+?@ z3YB9c?hiYc&aQNYqej0TIVmYYr(ODT`Q8$ z=p+Spk+ieHwUt~a<%oP%Cn>NV3D1>^gzo0al8gVzDf53`=P$6%{{`Xyamq95MV*Jh zI**r1>1g*!wYoWbS?4dXD_AYbT5aoJ(MbxNNYWLNOQjr-+_F ziEJMzyF^|gWs%>|NeZls{AN`mH==g<#zw*ev-0l!-qQIC>=M~dHjg`57_QSiim|FW-c<%R3}I!S?bkv}LU z^6X}p;JRlyJZ1hL>ih-P`F~W3znzJ-3X=cn`~|K!NLEdGP5xLXDX=c`C#6KT`}N`v zDT5$S`^NTDoxi{?kuAyM&tW@;b&>)nlC0IF{Xr)wupS9N zcB)ADN#`$crxE#Qout5tBx@C}zvv_d)+6E9P8A8i>HGyw6uDN@?RTA|z=F=*H98IdzjgisCz5o9>ox69f>PPc{G*c;IFY0)T+=4`uTD~6 zJrZV?6$vi>X>VpS{FP^UsxvnFRWpGTMRr9(+9d0Ak^(1^{D0frPf2-mU$3hmupVj+ ztdS^Ctwym?=Pz&~$y&{a*>sWuyGYv4PvwtNrv5abOQ}(`Pa<5SSlyF|uBFLdl$MebFW z$gWi&?JII`oxi||BG+oV&83qRSQoiZRU%in)XrU2+qKee9$h3fQP@`}DX@#A za4YpO=Ef;++ve3t3am%rd=d#W+dqy>xScBR>oWax9s=t;`U{U=Q|2*1=OM7pW1#T3 zqn$^>+YsgHF-Yeju+C$C;lU5Dl`jU?{5m~Y=Pz)@!GB!4$O%DL-e>qjbdmz=A`k6U zA}^rx7r0`PtGiA#l_gNEt`oy_fdqC5RP(8_piWX?7s+RNLnRpHEDA?NrClMc@fsgo?iCVp}b4*qB;+O zbsi&xhvO1#2YWupV5j{(ue{D*VAo&^w^IAh8SVSegndqVm*B;8k^<`@FJ4My8?3e3 zHG!mG$OC8lN4ANd6iBja;wf?;7%j* zsya!56G_%;O+>;kpKExcJY*?G5i>U2Af6PsYZVYTK@-9n*yo})mpC8O60yNi@d(hU*Jw7@&-Cdfpw8LEG4oH5?3Ve zo${mejdcD3S1fYcBsbPc3Y8X{r)stEZlRMDIFY0)T+_ZfY^jqJSdWCQN<~7=Mc!KHFL0+3c^jRi zz%G*Z{+fFr#+vx%c>=H<3NU0C=(*8B`?RAm@>r-WiP9^e=I)8yH7P-18 z{7)%?YCga_=>iF?5Ae>y|AF=$Z^Ea><$W~2i_Sw}oyV@iWAk<%3D0B8r1Mb}Mg+P78*=_Cbqk+knIxPBTQsCn>Nl@<~;Roc3~evd&-NibYQQ!f}dDQea)= zQ>zj=?d9$?oxi{pi=6g_<8+;*z`Dq1R3&oS%iWnee}NN4cCBe?lRQf&DR3gmTCHhk z>m&u%BjKD)nl5|}i(!Te(PA4gFBFS2X>-9QGf%R~` zfi)`TpZ2}ajXHmU6G_%8TyN4z3apEKb5$az{XFLuoxi}HM&w&{k^<`@-&U5$wF;8k zb^Zb;itJj`(%$jjp_3F?7x~VzM0PEAX)hPP&R^g}kzJ9HHp#nmk^(1^bVWkiB=6Qq z3am%MJ)J5N?$!AVoG5awBH=!rq`-+`oG$KEulN8uRvgS9KkLn}^c9BfH!AyI&AJa(+tcUC4tkG%sKcVv%IFV$n7Tzay zk^(1^bX|hezQKG-Cn<0u$y)8Wp4LeUtcU9}tWh!lwC{bM)%gpYNYWLqX_I_TCn>Nl z^7Cbh?BbvHn)ZUuU*JTMUDGXXk}v8c1=dA=sVtFQ{D-If;o8eOe}P>h3%6Q+)9V$T zq`RT(*8SS@9HE4P9*7Cc+)2No=#F=JrdrpDiYGZ@O_~37dTPm zT1CQ#I!S>ON!BV7KGI1FtVhEC%8CTnJ}vDv;bWb@z=zIout5tBx@B3U+N?U)+6DovLc~Y`-HD`{sJe8?23f6 z7p`w~k^(1^tkvrJtxi(lM3Sy>OLdkDB?RZyrY+w{euT<{d zzpUEDBNnZl_PG6}OCoS$M_mhc+9dzhNeZlw+dp>PO8r$m*Htm?FJAns^A|W#r%6KWM|^*Tv` z6G_%8)Eab>0=r0daHus_6>4dJm^7O%kiag1Y^b?LF>R7vbdmzQNOtfjcCBg@)Bd!o zn=X*RE`bt9F>R9Fb&>+RNOtfj&R*3hrhQ%Pp$jCiOQ6J2Oq*m+out5tBs=EfJx5ie znD$~dr!J7di2~JXMeU`N6gZJ&$Bbg{szx#G#cD2HAb}GFa*blzB>U(j1x_T{F{3zl zRil{p3kLJ(0tuWbkZTmvCfQdfDR3gmjv2*ys~W|$FFEt+0txIA$o}@XYZR-yU+htGE`bt9F>R7rout4nlJ<*I9Wxh)S2c=hFIEfd0txIA$d01xA$Qs&b2>?Z z6G^(Zo@tX@L?=Gz3)Y2xI*GUSTNYWK*X_H(`Cn<0u z$&Ojo7OyJQ(!O|))CCeaQ6Sf{xqtJNqjtCJKs zk)-R|ly<1K=p+T!Uocv(sz^wCRbF1_FL0vBu1H9mq^FYb9EBU*JTMU3WielU!XVDR3f5SGcB4at)oN zz=CfQ8j1W}k&yN!cuk$Zz@3KVS~^LA6G^(lHEku=)=3JSNYWLq zX_H(>Cn>NVuIsW!B7ax7roB&CPvh$~q`-+JUE!KG$@O)T z0_)+r0c#}kcZF-(o0$!D{sMOzk{jtH1x_UC3fHui+*l_ma3V=pxTZ~V6P={Mdbn=N z8j1W};hOfyfZ!RgsYP!n>8uU*JTM zU6GJ>xNfbJ6gZKjD-zNsxs6UzU_BDHttt}IUemVI`3syVvMUnO4%h88?wv$d$;6#$Ha83K_u(M85;6#$Ha7~-!E;>np z^>E#lH4^!|A|dVRwwumh;7&twcb%lbi6mX&n)bxsLnkS4B1u=crcH8Bout5exbDRo ziTqvRn)Y>evd&-NPD65Uout5tBwgW}_Qao}lN30Sq$^z0Cb^GJQeZt?_hpSl{;qIM z`|7Zt&R^h8Lvnweq`-+JUE!Lxk_YG{1x_UC3fHuM6y`vkq`-Q(9>f}n{9WOi_SNBF zoxi}HhU6hSNr4kdy23SWB@fj}3YPEue!T-#V9k-sZk)4njdlq`-+JYZb0X>Ldl$!}TcENaXJd*R=PpN9+6r?ldHi(MbxNNYWLq zX)8HRCn<0u$y$Z$u{ueC^>96oH4^!|!Zqz3*YP@kffGr(A|Y*(C+H*vP9#~YNH|d^ zDX<<1Csh>*X>Vpu*7*yZD6%UO(k6L|PEz1RlC_G2Q+1L8>ydC;RgsYPKH+qozrcwi zyCNZNl4s~71x_Sct4KIgCn>NV31?Lm329$~&(`@1oG7v@64EAlj!shGM3S|NgmZP0 z0_%}*UR9Bh_9ggyoxi||BG+m&bAe7$;6#$Ha7|mu3w4qLyGVBM7a1?AD%8@x#$T)p zB(O^$`|UDUsHIKv5}l;Li6mX2mNv;tb&>+RNOtfS8853U)Y9HWT&@cwuuGuCP)nQS z6*@_Q6G^&4Ep3ul>Ldkrk+eU<@45(A_oHlARTXM!?^3ST1rpdLP-3X1O>(+UQs6|A zu24&xghw<5K=Rn*Y@W64)h>4K>#&ru`|}wK_?G^$qcLRf(MT zHtu?zzrYoXoHofDbdmzQNOtgE^Tw)1G3_1FO}an=y97#{Dru9vStlv5i)06H<8G;H z6w}^(+^P#CuuGuCQB0fUZ8}MTT_ihrhje>YqnP$}{SI9qfn5S6j$+y*@6<^O>>}C0 zn-9OLQB3=~ewQwgz%GFjM=|Xk(%m{qf%VPDJ)KJAdv*Q-S1fYcn~(c+k^;L(cJSuo z{!TTD59k63>=Gz(s-(U7cu*%Pu#02|Z$2LCRHOK?E|9=3ff7eC?ajv{I!S?DBs+NX z@n}_}xc3!xnS150p|zdYHrb2dVv~O)ts{o5kAMDgILF^V>SBTG}Mv)JY1QNYWK* zY46(K(n$*JBH6(k;)5+mp7kZcpCPJ1VfgXM9(9@aCtIKVhBrHS#^3zre16 zvLWw^rnFbr_jQs2Cz5o%!;m(~4|I|O>yhwbRgsW3|BrP30w;>>iiETmzyIkZ1x_UC ziiEUDeyo!eSdWBHs)~fPZ_z&0`3syVvMUnO{y5_^out6J$e&jwa@q^;7dn4|JB`R+ z>Ldl$MgFQPk<(t&zSj8*+-XGqMkgt-F7mfkiJbOw_nppP;EF{~dqeuYPEuf9Fj7r0`P(~g9h zI!S?bkux*+J@_Zfe)qY&2PJj%%D-Qn87rR-w;YQnAeo%NI*)qck@TR%byJu2{YHb% zU*N>S?kgX1M}(R%3ZHt9&!$bXQ70*IB1zZBGUa~RBe4P3t>KiipUIW?%D`;83Igk) z)}>R0T34OFz=|q`-+JU2`gJlJn{$ z1=b^BzN#W2?MUvY^A|W#WY=^{Tjc&aNr82d2Xrct2kQI6&h7 zlUz_IDX<<13zZcKF8*m>II=o_ffGfpRU{18NeY}u(lw`2d+g*Is2Vl(hjvnbp8S-j-pHCv`H?ilN4ANc|@lYIj{2<*d_Ap9s3(8i*+i27S{z5*d>sC zA<-3uX;1Z$I!S@`C|sf{k<;csO6MLdkDBwK# zk^(1^bd6%#^V!o$3am%M3ROiy+Wc44`3syVvMUnOCOJkYDR3f5S0q$7pU0LpinS7G zoGy^S6$_O1D6XWF6gZKj>!z&SQA}*0RztP2u7be&g0V`c3bj_9zrZe$?Ux!|qu5aP z%TMLKk+P~zQeYQJdsEXf3&v`lY7|%31rpdLP|Zhi4V|RGE|Q6(nD(kRUMDHAKA$I) z6$!4Xk~aS}b^ZdoMDE}RBx{u=kZYQzEzsJ!KmsQU9;xWDjm|@0oyWGqBk3y?uJ}%S=dzv7U*N<^SgY;T_Bu&{6G_%;Iom-eDX@#A zy=GMV^1U8vJ608HX@A}KKe|8yy9Bc9y(`qxCb^SNQea)=ojaAtyXgD{?ldCrs*@Br zk)&%rryU8q=_Cbqk?i34ynCk#wLNr!1a=8j^ZC4|PEz1RlC=u8y>yZS>x<6hvLc~Y zi{{=se}NN4t`*5CI!S?DBqad&2qIIXM-cnyBn8$ZVPA=aFWR@Y3BT}M-u8Mworl0W zkNt(m2PyM7K<6Q_&f`GgaZk!T4$^rDtn)ZncqDD}T`SDpDc{B(qVpHH;^3dues7r& zbme^_bEr;IU|rFOxK2{wM3Sz%(zKO4LMJJ3 zB1zYrN}J?Vout5exE{$GiTquWkT(CLbp8T&8j?rrBn3_+S*vh8Mkgt7BFS2X>olFD zzONxH%{ZIUPIBn8&P z^(59vNVu4l7GB7avTq15JOtKxTp>K3Yv+;hIIX;A zxL4{t1lD<6B|KhFna9;S4}o10#^B34P3GL%W z*GiH0r>58HBn5VnOk63_e$n$fout5eBwSxsB)G15X^VV=&R<}c$Tg3I8+DQb>muLO zsYJe6=Pz)g$hBG%ZqZ2!oJg`(Yr?HMNr7D??Vr!F5 zU_IpT5FR5^zS7;P^AK3);R_GPm2QCftqa$u;Cr;|n6Psx?}Na*bp8VC{O>Ns-!6Tw zS()}rmG|iU1$G6za4WT4-XUd?@6|~Ptc!eKrxN*ooxi{?k>^f|TJ4mc)JY1QNU~N}x2JTH0_&0RbXk$$;-B`K_KeP7;6#yY z6$#JkBn8$*ey%K$Yc<`T*ZB+FX+(ZOCn<0u$&R@(d9kcftW^}gqzfc)qCm9@wU>30 z0=r1s+e_CiO?9`IuT(XPY40yy)ddpRC6K-JxkfSVk4RqANeZklc(0cwa;^Bkq4O8G z(}?`0PEz1RlCDK3?QnfdCn>NV32&Db39bb@?T>xm(fJFUC~~dB^u#2RkPEue! zT>r-!oreF%I)8x^N!Dsj_(Ufua3aZCT^&BvNeY}uvR2{xnNCt*JzPI$jYR&nii9t8 z{sJeGbVWkiYr>a0Nr82dzbZ@QS_R41I)8x^MRq+bN&BypeWQ~UIFY0)64EC5txi&4 zJrcevD-voo-M-iP3!Er&ts>zEout5tBx@B3Kk6g})+6DkvLc~YYr@Yue}NN4c11$k z3-2#FNr4kd)@n}us*@Brk)$hJ(^m2~out5exc<%>74uK~QTiV`e}NN8y23SWl7H$X z1$L2?04VioeA=(1{iTx>SdWCi%Zh|riTsbwUtpd8zm~t~9Q^TZ#~Ud2ezSP>kjmZr z%b)H}s$D#-qqWnHyP3Kq0=weQcC=RGmiaH%6H#Go^iRMGtdCnAYb5e7mO2>Vv_-Dh z`3sy#vQ{ED=p+Spk+i>`>)Lu$_X$N~ry9lCbb$nR2~_i`(nTjJa3aZSM=`O1;*~L& zaMguL*G?5C-SiO=iPo2NOiKAGn zP@6+1DR3gm|F=-vCFM|?Q&&OYL=|eaPwAzT6j+}Ry;&oXf2~4oE}g%?i6mVjmwRn; zH6VUv^Xm9{wzR)u*hg1EV09EHHMAUmHOKJ;q|4(b~sV=5%iFVRJf<_ozAT>pf;p=k=a2r}KGFnbUsWbLOp#8=CsNC!kiBCzBQ){ zdOw=eg}h(QY1aG8oDTP9n$v~7hUwuD=DaTEbP=zsIbGE2ZcaydJt#+C^ZJ<6 z#l5-B=}2!rbGn4r-<*!}2Ab2+-u&itNpGk*UCL`Rr%QVanbT#wMa*flH^Q7Q>n(0h zTfEWcbUANnbGp2@oH_NpG3ImyZ=5+@(Obowj`7wor(?bG=5(Al!JMw-tz}ME_SQA0 zt9X;lX{)!PIbGG;%$%;~ZDmeZ_qH{sYj``D)A8Pa%;^MgXLGuyx2ri_%iGNj9^U)r zbWiVp=5#ObGjlrG`^uc|?R{@fr+B}Z(|x=@&FQ}0Kjw5lFLO;e$@cde&FKMNS95xx zH@i7K$eY8Q9_;ltr-yiRo6|$RdClozUO#i%)|Sa+yaCocoaP{F9zk=kHK)>Cz?w(W zT+o_F(Hw5gqiHT`&0}aTZp~>lM_cn)n#)-8IGW2@^LUyoTJr>&D_QeInyXs#B$^Yf zc{0s)t$7N~4Xk-8%}uR&8qF=Oc{GPpo-6&CjiQ2hFdnc_+

      g>3LG2C#b>5X4BDJ9vAbh52A}z!;Vac5!PU& z0^xirmZdC2|I=BFs0Jev2xhWTToNg9w$E|5rO z7_ZbPbQWZ?0D{wZFqRHy!tC_Tx)xIyU7tBcfXSol%>+Z?G-exFw_*ySYn~bb1is{h z@l-s6n-Y{MRw3zpnI^#G{1HsbrNR;Fnb4n@x}s~KS^*;%^oP>fa3F%YI$=;F%;$*1 z8eKnGrv*YwC+T8Qx$0p4bPlLq1Pb{>v0xC_OYF*wcatVax(;`?h!pha^SMwYk;G*e zIBq}FWf5D076?~Gp;$Ig!}t<`=88Zee?EkTaFVV_g!5$Q zkeWm!WI!m1VE~Qa)j^U8kS+rjia;TMDwqfa;;BsWV#g{4bPd-cB873zO{aqS02+>_ z9Xe>bedT_AfpQmjkq8y?$Kv5!JWdlw^7T*&PMxkr!bt`wd7jV2A|c!YlRF&?99>jvwK%z8JQRsgRIJD8JkAXw z4zBVOv0O3`fj`vUSitDmS*L}`<+2%!RFOH<*K{6cg9sD!L zAOj#>({IrN;XZH}4@qExSbM7J80ZcWDCCcX(D`I&V5S=e86fFmyGx6dkEdgS1f7(1 z!=R3lwu(r|fDmBfc{=J#Y`A+wAk1L|lX$d-MjX@&S?7{2xcfw;us@!|6KLqvl#a+6 zN;gh;K!ghUv++039K|c&Ka7x#F+qFp95T?bl8H~+z!=R3l zo)VC7b_^wO%OeEJtpn4Y9iP#FWFo;3=%#*K?I#U9(Shs`KyZqUq@%bCo>1-)6}wvl z7+tUZoB)HFl5{AACu(qr2xA5V5S=eCXh34ANF*G=bgDQE>KNoD0ffd3;Vk-Dy8ac1 zK?X3ofL_tUgtMVYiXJJ_41+p`c};-9csClyjkGv;5r#nqAUa2N+2ad20OW(|XR z_#+O34BXL$^|2NPonIDne#jhg7}PP$ry@***okGbcphoi{HD`pYM(5kF;GZ^7mV)gBnl9LHv}mbpC=;Zc{0t7y6m;aA4(>YJU#C z>@F={Dw4vj=mh2*DO!w{O2zw8#Ebaj;cOzE4~JzuJc&|bxIc?G22Rj^ju3v zcsd7nYw?13evd8?6+Ao_QX<|TB3=xG#Za7XEz5Z9S(uIhbpijW1q_Dr`A9s8I}sEx zdrGE6Ks#QiE53aZjMAO7WFit*GMb*B=?G89V1*Vhk&5FfmtqE@-zycbtB4oz2NSV$ z3>TAfz)I&QbfN8f7u^BeT?-e<u&JZ$xvUerG^$_83faGGSXaG|rN^^9Kr(>_D zh!?@25_b`k8KpB-x`Ptj>#c>uqcy=a#^ADhO7B+!+}frT z?W4sDhl9Z=UcXS>>qNLZy!}MHh(8yJMe(q&a&RcUpOt&MTsc65!$5?MQK#a@ObZM1*q!``iX!zcJX{@2HlGcSnU0*@N^CyqQy&4 zvS37~;3>y$33!K!criaF?C??*J)cjV74QA50CfR7wSb9e1hd$9Mp`-CI+4*jK(`2p z^G7lj3E`%@3|Q>_tQ^!a=+)u{vzb^rRm{L*?^gm|wTOq_4^Nz7vO#X)g{2Su25R9V z@lYU_4apg}u=Jtd5h7gFk0<>T30z?@_7;{g^piw9^nS@~Btloi)VvEjF&NSvzej4} z!kG5Ury_XTgy2da`wbQ0qW)kukx1dm2pO)}`zdb+7>>hrxiVaf7r~VZ&X#g-wXlq_ z-v|*8y&oR@h-Q?r%fiyfexpRVsGoJt%0#1L$5dY5C%#*!fv?&AQ$tEy6|p z*<>_?7XfARihZ9IoQ}M#2#2FLmdvFhN=M&`k&w>0ycR7L%jKi#ta7w<;xws)J6?o~ z`V*;eG!Rh6kqe7mUkSlZ)Z%3WIlRr0lh5P4>nj0ol8A@PUW{Dw^aO|8xpX{G(}g=( zgu{6)lE|cSWiG=N`@Ry~n+fVv~MMg+u>8w*9#c(O+ZEcSg? zc)H}9rp1eeFfzbgm4a9L!0!|h57+s4s0$NlN;dPp&&okvz%#UfkvyJ0!h4&tgS_u6 z0dS@Wh_gp3nvMp7%Fw0Q_gUfT7@VcW%jd$lY{MOQxi2l9!3GfzL!n3@5hxCYT1p@I z&DFwXfR;%_iJr4RfT zYT?qcdYSE&Y703Jg%JHjoekH(NCc@FcFO^K=VnN&aS>fqU z9VR*(_gUfT_*hJCt+UGC6gMe#UB zG!TyySSJR3IcIu~-`U*6~SO7w5wwSQzi#;H9PvR;VG@I&o`P=h`+Ajc(hgaYc%gETgRxaJr88 zF%d58N8X0hX{@sWxXz65bk1$pqUG?UODK}gF|+6wxqMlTKsRC6;WwgR>gk z=^}kvix$Jn?+Hv0kZ+wD+Uel_F2aTJ=n9U}1fEs`TxSM$x=^3hqG27Jd%?@PE`2}Hf@SbXXFiCByNI`r&-*&Ck3=vW3%E&|$Y2#M)(9P= z=~&w-qTylFd@dV}<3=CQlw;oNe4umfQ!Q9J9!uw9c(@N>ojCdFz&;nj@RAGOzDgyr zx*))cotu?wx;VeoqGd1xn!pH$xz>q5b!cCUXm}|onaoE5cy*q9>$nMYfqo-`p%V|{ ze1HRixz>qcoX)lHM6`%Mlf^ja$c7~Lhp;TXkoB|&r{1Xt|bN@#^2wP;w8 z1kZqnvJ9;g6HmHOe-_c`9vs%S#F&uKc<*NAoG#Q~wQ%`pHixwv0|du=w-Vrf7vXSP z$R`7NOq3H`v3IjV)5W@5ilUNh zPtYF~PlOV952P6%hrtTG%8E_8RZI>R6!4a45K9XNuu_q~wS8wAWCu`Mb|j?0=^lFQ zFTiE|(Reyb`~J8y{JEb#<>4A6=W=@u)i763p{CW<>y z0o;CX?W8}t1{)~AW&An3@`GhmgGOjYe{>CYga814@Ww|LYv?5Xt?f@NhWzOKkp#Gm zKb?=@X#k?TJ(`I>M+yLFuqYOS!7MNm$l%;$=#Z|#h6;FDdWszHmgBuXBe7XBxSI? zQ5rW){H+G3dqbCWi5(H}vUubgPlQKtIb#G@^hn22OhAA~SYaT8=gJd+Xn*4Cj7JFp zFH83f@NziDZbon>9;E~Xv>UCCkxb#@pw(#DVd#>s-7*3o77xM8!HK9DUePCAyX6E3 z_>{`UXq{@XWHff^j8Df2fH^;&UjtL&v@xEEPZIg4g}fNg51*3|-RY(g^|{ zI>~GV>sdz8B^kgKJ<{dUi2?#;H)c5UDXhxgTAcYWu@5*&z{~n0;WQ}1jI$A(iAQH^ z5b)Sn5Z5J`GsJ?$GnFw=@g<3{aWB#)AYhr5L^hShdkDo!ZMZ-$Zag0cmC%|c-ZXK!4xAh_#E+De0Kmd=P$h36`rpwz6A{fRc;XpPW z#Iem+Z`et#;b@m7RoApQBy}?x;Fir z77XvpVwqLt_8vW+ZQTeuu)DQjc+)*WOK39M==sEw!0y$8Wz%>FhAuU!4HlN#vE8o) z!*pg2v+*)khexO`$_GWPus<6~M?&%9ql6{*YY&NNxIRmS==wu_@UJA!9udK4S}u;o zPnEn~SaQeqs1_}lL6?ii>SWeR?${pJqTzxD>sKiERoSEV){*LtsV77j1~ZT)nK7J zyx$=o?F&oq*q#&Nu=WGy+oD*YM`_biLw!L+i(oCkbUc_-o-0GXbqJ^Hbzc(UFnbcs z<#3LX&!h`W?b%+{f<^GqLLN`SvPkI>9P4z`WytGVuvjvPE*C4cQD;O?AC?66Pc2wD zl}&^rSX_jGmD;ntsRhgBuxLg+s63xhYS;EJ5sb1U97@KNm-kvq?%LiF(QvaYlEOHv z_|#m9oV_Pv;o2Gt^^l-#p@q(uuybCD3{dX?np@F36~ z@H<5`4B0RUPh!n<8LdMwUEY2wg5j(IS{#3dZT1ImLYI5Kh;#eJ8@v z9AhGYx1N>GsMMbA2N5hlM`<#g53~Em9rkOw^&NiFLPgW~`cMkr*Fd+{VXvlx`b7(c z!5`LxVz(&Et_%V0GC4=-m3B2o?0>eQ-<<;qh*At3xcETejQPn|5^1Dw&Jn0cH8lZijT~ zupC+}yh??YZ}1rkN{0?pUWZjFVg>x^OahOUrPwXv4xw~(brqqo#vI9Bf;ShVbFfEF!c8PSRUOV?HR6v42nY!YvD1n~JrO0QCb z>@8xUyUF6KF=2dfkmXm0U^>V47QwKh9+s#LD-VEm*mLO`vPys&8q4P*(HL%x@K2-Z zzO7X))Ez$?n6TZ#p-c9Es=}j5qQkp8do1IR3CCmi`6#-dwb+ zd1Ier`u_j3Cw>B$jAhntuitQb=C-r0*gbXR___0YU(we#eL6m$T02kqQtkr!-0`gG zO$%BZni^YdODno`ciL=i`{P#mCGvYBJJlhg`mrAPF7Y3KpA6dK2HtE0}EBv-f#}$3;!w<6euGi?a zOxJ2%Mq2OTL+5Su-D_3zSZJQ1(OjU@yqq-WRpO^R)K$#{G&B8}pK^3sgDXgFLtp%y zif@W5YODI%!~N{NPZ8Dho~|UtVg2wE+S6t`NRClatU4I>S{mCEa|DRFf)qy`h9CDn zHk*$WyAV0MVDTueqGo8)t)bAmhP1X0#?NK@+id%h zR;9fSTDNOViQ$p4RixH+D1JUWKy>ndVCE@}rr7wTxtcUT7>1vIXi7D_ez5r#)2wUn z>0l^cONtL3g`ey}ieg2vF}~C)iZ)4g4XG{|iJzXx0%nt`lFj}5Qv#f>Pq7AIz&%kP% zt)JZVie5^iCt4)U8%T5Park)>nulmK#}1%Fs@;(vg4&Iw)^sv{_CVsON8-T)a3qRq zqCHYvM~eTe!OzDUMIRJT5f#OzAjS2hxO^IZ9!Aos7KcJ{tdktow*+b3L|RWZJe7cIljCqc0n{0~g7W14mC0-ON7Eu?qCa{PQ777tkBWvfO{^p!Mk zC(T}$s7bySw3@snYM^%q>GfNIA79jF>rE};uy2LZGnxR!&YGyXlhmFjwNs&{ z_GaYhCvHkGeLBy8)?K6(-h`jEIAqnde8+9?{hOdA(n)%MBfWQT!Ox=O#eRkK>>lKp zY^;SxRu84Er1bb^{Co$ceJHXD`)|;=as$rW@rLQchuM}mDsVbR_qY#o--SPxJc6IQ z(J^%QqrTnNdo@)~H|Z;Hq{@F#<+o6|t5SIbRc>g>)V9neh4UR1DBIe)0DTiF?DHso zhNJh`S5de{P#Ad>SLhCfTS(z9QaDLacz_f_O^X^^)AhA88yaU%sc&v-5xwgH-OZ$1 zxg9^dpzBeL?J(AbU6F=cN!R`)ex90YvmF*E8Y+k~J5gaL2OPcs$)P4T*EY;E^W!$c zI^b#iG)%ME`Y=E2Z!v@qOb~S5Y$1gFGx+%s2>ZwgA2Wn8_@uS%cu+C(gas3u0`nSX zH_oqbY_%4!dRUqN51ub{8cJLu!`4*F!gVXS$EL4(;f6pbO(Lv+(BP3chHB)9rV3%2Yp4{@ihJP{sh0a2@CM~?&-BNXHK7k zp||b)ZWUn1)|Lc4>&e@>@8V}nz0KBF3H58OR&)JqjnYk|RQDc!&WF9uur^(`%2YYN75zqq0B$Org&4qAUzwE9j_+{3d>t#D<1J^3kq?t{)jl){dR4^MLJ zfRA?iNV%i;Vtj*I24M6cdum(gVg|;QgZ8&R=n}~IfuG^$M*y|Wu`{Rxc29QvZ?e7H zNfmpYWS@GHW5!868cymq?b8SEqwS#YVmo@1vg}!IL49*=<4hjf4;ZL!B##<*;pf^p_<56gRI$hI z$#&+E9Ue8DWdH6YJLP!A8ThdiR~TY)*i8L=J@RSD+)adhlihA>n>H7JEw@pum3!)t z!6G?WLCxKT9JbTfxgGSyZAb5Y@GHBH*RKqmzlBWP-vuUm&9m7~A_Em&7>DHahbP(T zAhY)#%3)<@+So-X!P1&CP^S*aH~;`8HcO%A*Qf@0WRWtPvO0(bXj4@2b4uBpM+#dgrxbFb7qR865(=*B_K}AJo?u>J< z%2kwBG9oGk{JfUfFmMe&WegTp%~U|>zZ8`%xTTK=D6y*ySloD{onUg zRabT29)$aR-}lcm-PNZ~)v0sdbE>*J+-e$EM6*h$RMGy}c?WXGPlkK^2Drx$dl&P2 z-5$Te?eUx19zT=q@srmczg_L|`_mpjBkl2%&>p|-?D6}|9zV0}@w>?$KY{G=o5o%% zMrmrsv_**Qx_Vs4OL&_x<_2_$+uOl_w(Vd_&3tnz@y=r1b40);*lRa5;4S$%65Mfr zWYABpCMF+I(2EcxSfX!T9aeXGg=xPvs$I?j^2i*j4P1buy7L9f#${;rhW6gi6B_5C zdo0;$B*WE`~W%9?#|$j-&XPXWfYHJHu3mf5|1Ah@%Tv)k012#)^Nv9X?Rz0 z$In=J`~-!^&qsJSamTMVc>Lmm$B!j={LX>LZxnd^ynx3K19)81-{W%p9v9O0xCFk( z)$6?{x#Pm|-g@qy=I&YUxNN$|MbAAhS?+PkagPgzdtB|?<67O`JKS-ZZ0~*UxI(qZ z^`$+o3hjNt9T#BsxNfq?)s8(bQS5PDVUMc;dtAcT~cZ@wn`WcOrKuad$FzTu8&?>K7gt zt?;@h9BH{N;5qe=%Kr4|n{9axs5cT+AN?7xQ<##r*Yc@nhUQ!5x31TFf7o7H{B= zKjSRs&o7HV;O-;t_$$R?{<^UE3-0(^zT&UB<4@;``GdD&{!XpFMx`7<*prf{P|3Ad+zwdm16$fqg5f-0>aw;vwAe-Sc9;FJ3%?JHDk|%=fH| z`EqnI-)}DFOUcE@W9RYJVDBXE_$&3_c-~Fi@qIUsZ>f2FyUgQTVIJS+^7s~($JeJkzV+nsZ6%K{ z8F_p+$m1(L9$&@r_y&!~7hgQSuHx}66OZqPczmbB|Ls zYsGvnR?G)l#e5W1%x6f&eE3t$hc?B0+EUD?B*lEb;qkGB$A=LfA2E2Xwh5=syra%( zPdIPB0F#89I8W+uZwco2r{ZW?(M-;iS`Kepw5EMguMRvVPnlS>Y*Nv&Jn=5WuJ}am zR$#X!r&C3oA{TKofLlMNEnG!lS`s#NIA#Mkv!U~!KtorZj>`c~(7jY?YGe=mZemRJ z=mCSOJ9SAlzJ&|&m6%3(+kiJ8Gtx05s}CAEbW+Xyxwr$1d7Ut8!92dt7+z&b&4K;; zbxbw>-PG-rYMvT5thT;-$-dpu=r=GEf6Y_96Y@@OTU}kdaFKfUFs*w2Jb*N9VLhsC z194KV@%M_9rarzwG#%e_V83A_2aIu4eZ8o8YW!H}vS?0ym(Cq)yLVjz**_YUhBU=0 zO-;1ObnfgR(-xNWngEGYr!B%YHKZ*z(sD`JrK!mVN8seBHUcOf;jsD+AM0>Op_$9t zR@cp&(!gt)?G+lR;i%QaQL7T=hfKmud`SOl-cY<;DOH;K##R_S#5H6e)Ofx_0|4*R znN=Eqc4?}Y_G`a>)lj#3=m6-{TKm1Ss5CXzXgnwu6o;bnOMO*P3>nUlf;s1ykl7Jc z53!o;>uA0;Dt3*wI&P@b>h^Hqfqm-b^0*dP>!OcDMnyty3A=~BTAfofpGF{POXT*^ zDrj>X`ax-`bF95VPJ25Rc`05&?ACk4{2_Cv&+F5>Q}5n#5$jyE^y$;HPtVlKEmI{W zjel$gr7+EIg!mE&-^B_a0tj8%TLXqq++ZDrh7CqXz-9u4oZ8cN^-bytsl?T z&YLr5-duazoVV1JjlB^lf6hRWw{fE`R$ASE3yW5x=z0__O%1>pf}TDIy?C0@W)Sj! z)Rxen>{|UDkM0lt-qunEOJ4`YwlHRyiIqunqXWnS)a_vF5~cC%8Ya-Tfy=8W)y=J+ zTRms)G+qd92^RiJQ#BT#E>JfdurlDai;8rEs2J+3SLzHLHe!7LYP9J<{~&7r*$G}5 zM_g;0L!;hp>+6o0#;$@ZD^&QvbtDRhj(io3ouHV~3qr<1Fpf5$3@0j!oN7lw=GEE+ z4#;ChI)mys^w!CfYUN51T1+*-v^2mJ#neY+g}rY8&2z1fjzkZDeS%RduGK;?M_bT4 zb#p-94oZ#Vpf_#dLOAIfGv*wx;%U^tkvI+2W9v7&roMg%Fq&h+YfDsJG?5R$Yw!zk zR9;|4xX(ja;iys4fi1Le1Hms%0q|kS!a4`Tcj2dlI1KV~Tn55RjZ%NJMhqU}hK`>q z>C+*Fn@V$MPn(PTk|lCq@_gv?e1?9WVxSo`ARfr$QYCBJvuf?kg}A|}YF>}Klefz- z^QqC4@#LPC-h>%Lw5vyqtR6OCSgLV7Jh_tR-eR=bJ{rpXSlRHmC@Q%@8s&X3)96k( z$KQasEKO~Q1p?29VI;If!_U}Ah{OAEs^peQDL53Or#8$FrQZrLUJx*995ABcJ2qAF z{>0RnF^d*XtC>?>J8y1n&7zK&gK+3gHEs+2ZiIf#Q;+zNj~5H7>u1%?pIWo12Hfpo z8~&Q79&DOfnwn$U9y$OgAGhlqnJSqwF*U3oN9bzY-W)N%7Po#!HcScI=Y7<*f=@>a zEeEY}4zfD|oewNJ9Q52#;#DYEu@AJbS;#SISEKZ{d3mL&H*_l;I{Wn=cLCosaqG1-HONM3SEr}3yIkIO;1HaT!^uENGn%aL7*(rVQFumBBImkN z&iTaN1EThhaO|x@Z>gU+tl!9)OW8|PsjN8RGj?f20PfGBwL4S?YM%NuDZ8W-o^Qs^ zGwK;>c%I=Y>BUS6^G!Ze*sb@lc~iUeIH+#X$a(d3ya6aDSb10ye@fw=WiNngJj=F% zIy}pMYk?X(q>BSpM?lqwVTAkXy!m>L(!VryqVg=>)8d)I3`C0{Ym$}K*%eg=QH{U{ z*vLIT8O9*;H3Lb*#+ZK_iV1Laef_j*nYMgl^f=0dG0s8JN#EhnWy9WmM-P)}_2{0M zsRBD06b=DvyspUetWkdmR2<3y&*&Hqd^ei*hFR-6x#M07h}_Kvhs;&n>0Wd6hVf2a zs1u%UcSPNz)#x^2bYuiR3Nh7=kuqmqefMrlINk1GI!Y!nzce+*X{EcX>T6Nu z4HNn&HpweZtqNm!=x8T~w}t}gLlGL&7IXaUVOrlQFRwJU$e1xacAYT;Ha@2T;^2zK zMxC*hGm_)>#`s*lcv>wc7CgUHFIqZ(8rs`QwO5*&XJq3%5}SifNtM)vClU;)=6<|6 z%{~Y7FUCM!^6f-*?|#VKMSLQx$MH&xy4T`%ee={XQKEK!{T!T#j0R;&gOaUxOL59H zcV2jcU4hv63&O5>s=vOdk*9#L%z)H8F~2mGiw4Ue_k7j@u`<*Kn%jY!1IFQgzcJPL zg4BTO@nHRI!gE`&hB|>gWcc{LLpga1ukfj7Er(bd2V_|lf6Y^U^D|3R^&#AGw5O*^ zzQdbwP4wWfPqP2MA>cfyLExnU+U2wce-M43OxZ0u02N37Ev40HQw za|aI@KDK(~a0R=JyCtxy%`gt+HH(*2%X$9`)djp1A8^a*tb32&JC}9u>YmHCg}OYK zZ39U>myNJK>f~Ocw?gBK+e)NxE{lH@KGAW_K=%@%8%pmhVaJENQ)(72tiw~c zZB@NsqTgCoh_CW+Tfa1uP3>BmI#dCG>js?cB4@3G0l^Y=)v}R`77pB&promy#)ktCQ|_L`g2U|`tvWTk_{Yo%t@U09rTP&%{k2Y(;EZK zU2^I<-oP1~3eQJNwT7pzSlpR1&rEw-6L``eIl{fVXaywpvju45xIyl;paKPEng&qc z38cePCB4*@RPFqwAp$GV1MiR?_*r-^2L}CPv+K7YcW2u$HRD7F!7ClH6ztiiS-Ajk zZ%J0etiIZRayK%(kI@gDI#Ulq-O1DBR0(gSIzxwyx@PD&4T|3h#YTT#Ox>Rl0ajIyf#M#7R8jOS|PI1>@4goE_} zbjG{;pa-j4Xma9z#++4dO=jSt*ILlUy$_W|TN5;#97tU_IY)ig8AmXbh2zL@XmQvi zPHl&b9kZxrQA0gOroKjv2~BWtKT?GZ&hkSeW7gi7W?t+}LD*v;@h~$zIkib%NxI4V zXyF-$mn@hpLg(XUKwZd-BQYkGN)@Fp+@!%s%`DA3^zqTCd8)iK<|&vUD&d?R;t%%) zEb{JLxD>2iqunENbJhbOx9HR3y!m{;2O7U_0AAY!r(`Bx+^?IvxMp_U)N0&f#a$EJ zlBu4H`|!ZiOlwv`x4&l45q^tKiigaZgSS5Hr1(CJOwCg(+nU??82cNyP{nh8R zOfH2gm0GwZ7r$5G-nHWF<#lbbx{T(9TX-uYohtb%p)YCFZCB!q{sSnFxV6Z3c4K-c z@SamK&B1w8HBOMusP-sqI@sc;XOp~LgTLmf0Zp+m(XEkKh4!l@%(%d=BQ&X&HI5Z;u4`=2!(^7EwZ($s|%G-Bk~>JgZA zU5~;t*mFeNCuX&CF4z_t96omJurYX~)31Bi3381!px@|Jx~~@;WlNxOd!>Lv+xxzHB2v;2Rj`(P0!*5O3VW|^;=*fh7UyDN!3)` z+u}=IyY9c%xAj8n^XK#W zf2?VIZ9?7)a>om2A3a8PRE06t*`cPB`_yuK2=C9ELi&QP){GYWCuLs7>k!^K#_6ho z*PR?M1fKJo;FP9bcFr((7~`Hm+MuJ&w~F=chmkD2!L<+ky?=BB8W%a=?u^1TR$_z{xmoO?t2I}_!ZJ!?Ol)ASv zc<|RewU^v52xno38OYlu=9gT>A5YfsH3&TJub$q3AB39gy);CAks+ErqE2?_0A*0* zm5KVv3p{p&Y464S%#!~3H(aKxUwef^DTnwkrP1-q`~>5Npv`-`skoYjHfv3rcP3@N zB?H3}AR_a>kBrxzRbErGuIRPoBfxQT+oNk|)<_ttnNU9)8SaFIW7ME7P(~)y&}OF5 zrf)(nZhToWyx9?U`j)`?Bja&-28{V=c&q)jqLShC)WT`==fPKa>3hbs+L_a8XHCa@ zAPo!E)0{@M>^s1iyoAL+-G*74#h(ef31$key@nK4>G{l1@!tz*O7G2`^#3h7!$F z`(SXygAjJgl5Kc;a2^?P2EVFEJ-1BZwD7Q;7N)Ax!U%V2IvvHtF!woU}s!#<@eU`0f)WBse;AdWH?G3ZdAZv~H<(4xhYgJIt~=W1bQYt>vi_zP;$&YU6Nk?zHjEth;cht$FH! z@P-tiy}+1pPeN{K>R97C28=$;sj@-gb7nKaz2>5moCHQ{__$B;_j-xx` zTCNyE1D3#myI}wx?1j*BzTiST7~|yh_*LtWF{7QU)>aTuWff;P#bt4L4>VO>Xhf z9Nu7lBZRR)Kltb6<)bo+|I?lHaM~SCdfq@Yo-;Alucw5!RtADU*>R*hV5M;>v`pR+ z;Zp{Ai(yp>eyUN5{6;<-C{0Z>e&IWU?jSh<%p)DS?gObR@VZ#j=`%j2M+C^2vID@& zShgVJj$m7XKgx>kKVm_X^t1~mu zY4U=Ny{NByDH%#%ZKU_yID4D$d6&%AK2xTa^p$5Dk(Z>-fWNY)A@;O&5>&k`9Ea7=b)`}A!loD(2sY}}vdWac)J!{-l$%ZdSxw|WvY!TCU#hM& z6{>jUY3`HA&GJ7OR$0@mQ@i2%Y8D+iWnuNyy88JDraMi&l^bK8V9sbt@xWAC(nS6T za$@Df$SJio60}`RmCH@g)Gp+e-h(Fpk|y#;DZLbuSDVuJ3o=vq>dZ)!_fubu$ptEOR&9?Z7W|4fANjOzlf7d4VKAK5FuR>XDp(muk8eO%FF^FBl`IZnmxNX+Lf_ zXE({|CrVju7nv$&I?=$3Hr(>ATZq=4GzCuky#l`&(Mp-8OvN9X$loK@)ii!bnR<7G zvBB97RC&d4ZfTNpLda1{{KZtMZ;J7~Xr~;_zKOr)sfA%_t<()h&gJ9iAKoxfj(guQ z&TWeEoZQ^6pIJ8@w+&#$d{bkAb&_u7Qo}l9oM{5C;EVJh8qTRrax$INGZPt@rkV0T zs;lrYL_Ri*@0(&AeUJ%g1>vWr#=@o;eYyY>)wl%nS>^<=XH$#?N|ZwVUemz867LvX zq3v2+Qx71HHL^XOZGk<(u+Fgiz=yu_m+a1UpKao_~vBuChARP32(prQtL-$=Sf!vwH49BXLQfV@D~w#z?qIDO)?g zp<4Hu7YyqJD_lq0n})Sc)l%0O>V=@^4DWh_K7S6MYCPUxe4fsqUymo2?3}9%r={iq zdJKFL@+TQy?=a}J4iA}jZcsW*x0=6XSa)lI`n3(!@6IqH8?;>tiMLIq_FYUs>ap)oTov~G5YmSY)me@+LHN&sPdB{aDa5w{pTnYmvW;2^B zV&HfNkGU`gip<90l{&it$5+d72|ir}f~#eqJVudbsq6J|J&tcwg|M~+2(F=lU)$jW zH6XZ_25Ky34KAs{V;17d8fc9|xxNOn8(5snZ19*`aJ3B_&t^Us-C#Zy<=PvNj};n0 za19O;V$Pq0@a7?(i%&p)I~?-2?kKWw+9DAA%{$gY0Kq1>U<9b6=FHy;6jzSGF9flK z-s}uWt|5^sZYEzDA)CudXnHDXt}LPH1*Eyi1b$nnK8?Z*E;wN_qy`tCFd0&XOCP|j z4s4DqAfWXcEGak>Bo}&s0ej()KV@RzZ_d_u!B&wvjb|#l@d}+bM)|I6nKYukFm1P! z$Z9m{br_?_Hz}vdqzCGB{qLmrX7O7`l;5D!rC2tCbh8~)dZ?~%(z%*8>4CajJZ*tn zHk8v;dJzUZ@~_1FiRo>M=JEgZ)>yTRvhkOmt);DBdTuZ2&;3=~Cf%TQ{<){8_&tkt zDmpd(+;a<|Yj(>>`b}1)*J*n7?uuTj>C`TYzF*TnYW^=h+erOidN$K3F86`KFFm)C zbdE0nZ!P~eO>fZkS7^Fa%YRJMyX~RcJ6qG+YW~xj9;x}i^eoryHP>kiowk(pQeD2S zuK$Xr7wGy&Yn*=ARpI(Wzm(K7>A%Wa3H^aix6`pzmr>3%NYH!e z{N`HTwz~bby4>xWeqGbPuJ^N!v!8XG?Wy%TVAqVuJwVgTb^Vc=zEIQu(&Ok_xt^G zsz0yLa+r@kL+ z+&XLeEluyC+{bmgpDtIe_2bf79vNI=w{Wd6A~C)^v9*udkN3 zSnK=wZpvR1wckpQRPu`!DSw#s!KFJ(yC!{1(Ht7~xk8N~n^-|;7o_f46`3LFtOxjwHqkLY+I56pAO`G&>eSV9lC+oOq zDt%VR%lo?iEqWX&(&y<@bo`riYI}w69G$*0Q0ZmTb98x=^0^uHHt8&FpGiN_?VEIE zsVe`yP9N5(uja>%Z)$q5rmxZTcACCS$Gu6n()g9=w3}|^A&B<7cNq?NiWiTlOA!Q;+u5(#fmnm zsb|vOT2GT!X+2HKdqK3rq?o=4-BkLj?w=-Itnoiqr$1}InskJgXVN`xzDVSobbaeS zyn%q7KE4O}qC+ zo=N*^z1L}dj@Npc^c>yKyBSYEZ5Vw$9jGJ?4XEnFefA zur*bt20ZG@Ena4t&Yyvl$8kQfAO>@=vAx;YHl-ZxYN{ON)L^6BS=i!jn)XfhWz=A!K1pr4vWO+)AzrQqdDMp+j~RFIGOpf~8TUEs z5!-m|#ml*I73U?zUc8L)k%^n`XtOIeH~xslLTokI82c>a@+pI5Onf#~rUqq9JMl8~ z3wb6!l*NAUs4(4M-!iM8HP{%SSE?jc4lh%Y=?a? zsT}i(Qw=uSl~l&)?8bUhIkw}*dQurzmWlPGa@32yr@Vc!Ey4DC<>+gcHT5>7&gPak zZJ5~H)HXI&z6Ltem!?0kZ^vzo$1?Rc{l#EfgFLpwm~#2dkIQ%YS@8Q}>yPbVZ2hqH z#WqxLV~~!;))yOjhhSsb5!epJHXNJLC5z*}*fvMjIFuiW&B$PU$NPU5P#`x@K8{;>{t3f@ZZ#|ApyqG-V z#xiWb4jc7kTa4KnY&@?pHRUOTd9>ZlGh?pFV;Pn;`L#IaX81KYW*gkt9}M3uW7;<5 zOc_^((KXIv+wOP}=TonZ@oT_0vYE!~yXUkxkM^*RDU-x+ibuU^FMY8XTf8py-WcD- z+{M+!%;1^CXCI<&OxgCv>KUFnw-{ejzRTk|#nsE@*MMjAaqGDGZh5vvc^l&s`%Njc zF&VU-@j)ESIO^)hHki-;64%d-t2i$nmvMd#qPi}sVriq0) z?=p|}a$_vGsZwgPwW>aMh1{*6wyj*^brfG+p-&Fgwb7SR<4!>8< z_|=ug_#$p5hTOSQ2jtT)N#)rV_1)C+l)tHEDSK1PQnyVlyQ$^kSZpc=O_g(PZ>o%I zb5mtpTbn9lY>e~G`04tRWf+6(W9&a1w_HB^J>}8Qj1kH({lGm(nLPF@)~7u7JIXga zx1XCl%4fT*$2eSo&E?gAHvK)$bK9qWaX$56KCzGUDAOGm;{1*ASl5j2@p`noDW1WX z7{=>yEN!ZuYiGP(4eAj$%8v6)9{onyF5l?l=Ft}>7I;35^N0y`kMo#MoS9OW8fnYYdt>9cDN7wpoVt1RWl}zI+ZZoi=V+97bu;nDJmTC58?kZQt^v(9h>dBBcqWzo zJ-*TB_sX%~)L>(q+`3@vj4iGkX`_1*zXtpy-IL0?IwkRwbWbW5*PS?Z$CjkK>GyFS z=U&WfieCes!6vEh#`v_8@_(<)#`xqJT;uICe`9>&$TI9R@w#qbPvV<;9Mj@;-7zc9 zi;v-PKCv|8Pn_qDX>lIMh^FefV_LkPYiFFtv0`I<6NmA7#HJ};e4L2aCBLb!!gc{jeSAW zUehmYaLj&Yz1Qj`jA^ZpL)deS;qB`TZi(g zi^0IeeTZx+cjs`EGgUu^ki7E-xM%E|2ZFx)KA*;h1E6(Nr0C9=@@% zv@xkH`z_l`;>C4JDwCuaaoE(dw3Gg3zx+LWX+u(3V?z=zZbMR;rfk^Mvb2HrZi@c# zaz^)feq8T3zbTzJrJTWhQ}iVUZaJfGJU^~)oZpnbn^KPYa-4VdNRr3+h?g_^#`EL) z#`#I|8P}Uqj(WJd8Xercc>6A|skYrRz0d~x`xtBkunpB|Kcr)^Rb%5ZHy-!LHW1rL zP4n3BDTnz+);Juq{0MAWY$AU~! z_FUinZ?_fq-R8Czzem#!zNo|21KVEM*jJLuaDL{NVeHgkW8dq7jrH8TZaRX4iIS3p3u*oxH19>b%{vd3uJ04qKY%Ie%l*MwJ(k{mf>eCn7 zXnoAOv$0LZR*#KiUk2M@*j!%2MtH27R3|BqZJ1{mNo~Y=EYG=b4K~hIlVo!IcJpgN z*I;8^H{Z3>%%|fzn0cPbcV)$S(;=UDrLghXJx34|=2Hj8TMahyO&;weri>w$WxP=* zj#DhdlzFr{Nj_~hvM7Uk)L`S>FsVHCU_Q$-b#*o6i4S#RS?Wi9@LD53T#TO`cE}tC zf*&x(ulWwgAwOe`L;mECA2Vi=8WQ}dF@8?ip{B$9xup4hWBfKzQ~b~|emau<^($v?bP5W-1 zIcEFjnC+Wmwr`HvzBxAS6C<~MmuCAeO}t#1c)2w3a%rQln`e%xuQ{f^=9v1LW9n;; zjlR^$)z_s>dv2aNW_#wC?U`e?XO7vPIX3OlX16_;W?7f!u}c#lmo~@L#T-)?b4*># zF?BJ=Mi50vi?b7C$x|(=2 zW#{X9^+?SzUnj&c#)X6N^1Ro$8-7~oHSWzle)aFwkydxodGE=- zH91(}z&jEfb;K$KO3#ypue5zcj+M^;lw;AnG0WPdu`Ytxumq{L<31^;tocfg#iqtG z)}dus$3Uz*j&+oU4@x;@=eKe!);3nM4sFKT2p-mN@URwwHx*lBBTHql^}#lqIjf}J zI@v!i`%h&51NT@r!Rv=@9!s7s`M1gbPqN>G?KJ+xW31@l4aByPIcEv?4%x4l{pYg( zg?p?k;SIsoz>?=m{@t>FM)sHP=1?T@9$1thPD}xR|VRU2kzHslw!h)v6?C z+v!sP4<~!OVOa@5DQg&jDZ<#*FraaS(atcSK!mZoFt(dMr6JB~Z>j*INR_?9Dshf) zIJ4uz_Awm#F(R##X(rC-VyZO6Io%A0?u-cQA)MBmB53m%vk ztJ6mqt>_xpF$bCKxsmMtCc7b$J}|v)uJD6R@!65$L&M_H{NW}a&Tz$y zH2H9an?Kr!k7kcG#o-3G_;`~Kq}}`pk`Kt}0+%t#Q~=6u{^YPijB$i8fbqOY`5MXI z&U6ZO1ti^~R&#W(a5&S1(^^Im3UgR9bR``X4yR6YbSyiZSz4Tl7l$=RvrPOsta)0V z?llf)fvKdst;4Dp*7j-;imBe9t8p}nv5qz@3??zwQY}%&rx@>8&69yD#yeh%o6`5#&+VHsInL7D)3B{vDz@|V~k6+EP5qcWsT<0CsEE7S{OVM zWn5(#aaq@DS^9+1POkT*?_6(M(ayD;8-?Ta9m~2&S2BIaa@J{%={uHls}>jb9m~31 zv%5He4EK7v0Q@2Zb}PIASdqyWBj{TM9Syu8IfaqEd$m??#zhJ96pW zD7S@EHILcKVZxed&21gI^lp^f+Tqf>QSJ_oV0bsmY~xmi`=Z>o!gahGWtTgZ>D?%| z!sPu~e??s!LVUf-SIR?X|XlZ5MdHwwjMr*eMZJ;LSY^`Iji(FuKbio;Im zyHg$6`F(e~%gt-KPPpRT`ny9*pEZLd#rH9yY&fu_jspre&0R8<>vLE6CKeBefK1XozQnrc4X)G-BVm{ zUdyKmH}q~aV9#)vd42aRM{a)KJ;$k<*LTlzn0bBo0!MCs-@VA;=J(yzj^Mn$d#PJB zukWrAuH)S(6jwNv^ZV{qE;p|SUE_#O=)2cB?1a91gCje?@2+*Zc`dIKZfi`L^Lp;B zAuF%n-Y%@|Q7gaK-Vs*I>$7)-th^q3Pbe|Jzup(}@_TC#ip=Y)587&ZJ@p~s?EnK3 z`spKK#r$6SnC0d5lqW)=2|e^rAv2+W{yCJI-#a&0US5mu3Qv148jgPrS$X~PgHU3A zuly*ime(gg30ZkP^0QE4et-NTj@w%{pEUHAfKI2M0SyUMW5^yNF-jYL-e%#&(O) zJ(ZnBc&TGI51dNjw6GjzR_WrQ)5GFfT|DHl_^y)KdXWu;uzWjVwRBjlu)CHYMn_n_ zy_O$xSbQ&CJdBvIxUY+c92Vb4GFvaQQ52T%B&?PWixs-)3O2OD3f*)C%VLEdlDpla zFy6xQJ%!W4a#*~VksrojSpEPbKV-2&Z^_*rYKGZijlRNbjipKim3Ygl7|Zo{%z zVUVd1MpRf~h^Y{=Sm6-K-F}f1*kO%f!fWO7SY?E+;)HuxWt6Vs@K|MxWVc>qJ3&}u zoUmFtELJ$wR0x#~D@-&MLKZ6=uX4HC`&9G++}SBcZlmP3k~QF+?30}A1-A4`CmYW= zjgV8VXs7TQHrFY8w&b?f_nDLkeV6H6hlR(1B3-l2cUX9Q>#{C%Sa>e$vMv_Z_R>~E zjCYAsZFaQUWp1???{bGXJ0|i#$;2-Y+b1-GaF5 z9&oC~-1A4bT8#Iw!;8D_QHK|I-Q!MkF(jXKs>NORl*5aAXT9*$C4HXjo^~q6z4NSF zG0uEmnBuwxG1t9hS-8rKxb78)6?5HR99GPAuRE-m>)sTWxUN3#y0@KbG55UdR*Uie z>hR*O`@rGFUH6gGT+DT!IMw2=`^@3RUH66X)D>Nx>%MX-#=Y~kTQSc3R+!?t`k3qf zA*^lXA|v9se}#;g+kOZcF{k|)GGZ?Kk1)1F8*zvI5>|=1@J5T zxJ3%0y&^E>1hKae#qDss&0%;Q?EmNAh^oetwpTTd$Ta?z8quZY^wt%n#qF9k-b9^R zO>SL0zC~)A5#Bj%M-)vOQ8aN(3h9_s?!2}GhmP2e)L|ovCg(0}+jrGT*S1LQcYa%B z9X=NC`L*X^>p^2vV;ldAzfEsu>WHFR3Z9B)E)JWSHlk>H?o!jtYBn=Nn&IK*Hgh(t zY3z!SM6wqWHYYTi99=fhA6e!PFY||%`3IM2D;v9^SguRiLo55@OQNM%hdvltw(6w6 zw;0D=FuZK-NvCFTd~zljisN&5d{QPj7{}-G_{0n#dq^;9#G>n|p&eH(-*p_ep?xWF zzcFQ0p*tE8qevEH)IrLq{ftqhVbmlTHKEKOU*?YuE$RmrtW_43(V_{~qApOsMQR+a z3dSpgXjL#)8APkJ=7)*q{UJ;=Cs~l@qaXng3>JlPKpL7)gXXnmeodKQUFIJiDnAi&10Hh!{n(Afsv^0k%vOTW~-cM$Lgyv&#Is zGJi&B(G;*?t>cba)*{y(b;=-d#|&kV1%dADNJC0KZi93!_2089HQ8Zr;VWK(7f;2x1 z5}+`?K@5d)KpL8#3e8U`^G`1GPYN|Z8?0!*KE-MtoD3D=3+dP=S=Dn_adbK{lWMHM zNYDjiQqj1T2Q>^u!LX;FCbpad@nQ?ff^4}A5@5mwVge3G!7gNOkRLVV zOlyeig3~w8j&sD0%OPFtAX$(dd^8XBuNL)jKpJ+eh8-7``4^P==Y^*5rd70aUt~=Q zE^vHu-sahIiP*wJn`g^f zvE^xq7h6acWXoS50VX^zCg6ZHY`GP-tSj?x3JrM;`B6jGSwmc(+_ZUi+$MIs4(VbC z$%5?o2oj+F+oC=WNW+eMVaMHN{+(t1A3{?;Rz*Ki$)`v-6g9q!xoDr|&5DD&l~-1! zPR-2}WNcS1=-35Jula0>poVM8$8kenGC_L$V-zNML!$r$wjFZj}8 z^o3xwFLDJVk_BPZ4-$aU{zwEP(!l7S!05X&|Jx9t{;J#nl?+4@1?W3vo5au$4nTuY zGWUH9pdTziZVYJ|g3q@J_zb43ACmDI0$%XF#phpw&%wwQd`K3A&p1c`KEsg+KBR%q ze}T`hW&Y10KI2unLsc>XNfe)7VUGzQuiT!2wJ3p)($|cb-BN72-s3p?iiIEizEtIYXD~AYbOV=<4`i!raXF* z+sOhJ=!z0w+bYyI9kJsneWzr^mVpew(7F;5fYxdxf);6@)gEZ=UhcOG0lP|-yILjJAc+FDyAxj>9Kfzc$=qJ$(Gy?? z3s|5lN_@53-1xeV(mNz0c0G8(UKX)E1+g2DD~ORS2(dpv0uZ|yi6BNAh;;^H9YeV8 zP=)SP$z4dIaCLOztD6JY-6)ys8iT8wh0BdEEo0N;>mCa4mW@ixv75f#%`()7o%QBBVrWEf{gkI5@6KZVhavP!>DmEYD~F5s@xwDTJ$kku-3V4 zIL2D!dUKRAh~5lFD1)3^ZR17rPasS*Cs~l@|9}K2{Dmlt1Jcm^NN9dUxj(twpH%Ko z2$laQxKVc;VU-UiLrb1g=#EKBd%24{L1`~{ar52L1H4j#3@shS&mccMDr~nOf)B1 zkmlPf&6|tDa0+Q?z5trfEBEJ=`?EsLcK|CIPV=nh!5pXvkH}a$%c`C~7fj{d%Uvk8 z>i`FSd{@$d&^j z0VZ@86L3HpwycCLE6V-lp&s)64x+LsN#Uq9ar?5=r#@d#3V=-19llIscAA$=tc+(a1c{q7dkc(#1}< zFa)RKIDX%7G=-g)e7+q6UU05G-<~5FjYY0tM6w`^sv!Z;Oh6*%ThhSjQed>Y+`lLU z=txzrMkP~_L;+f@Y?BMD%N>AfQ8KqC2GHdeAU9033>iHyO2B6-WnG?(&ouCYH5Q-C z1fS{16?{k*gwH}q06s?{5qwAkpS8f}hI0S9a{rnTqIy+ykxCknL?OBXCYejBbq+*} zQ8IUPd9)|3vk(QkqQua33TMISngooFrm%I%7%c%WxY=TKlVG$Ixq=bNf-qVM3Bc$C zB!UrXV00HSx})5`Jp||!Rc@6^PDK(0=niF@#L&GCK&PQ(?w%Mx_gaA57}7EXpW74g zIi0fZO~&U8@Pd0RK6eW~XChbdAz2VUmqG&YIUkAOLmK!z0(>4S_a6-LxlEN?qms*! zMDckD_Lu;A+`;Dxl*~OA>tl~wd;(oj0_Z^nG6CB7dEVUfxsuW!Pe$x2@PfxIVvh=9 zS0h&tBUun)>mUJ$U5`W%BMrpX1F@$*aF)#SpNE zRk=r0@+guhU@trI^|}MtVE!O{Dw}1t@qQuvWn;Tz`Q~K-4h&=&b@R~*JFM`;U z$Q8s$7KGS~kO0J>J?yoVp-nVeM z@ug*KdVKwb!rxCu>oxF#zgo236SQ7OuAoJ-Ahg<*2wG_*f);6@)h<2I-!<)L(|%Rj zuT1;tw7DCbLxJ4x>D+hvk}1QN!*)&Eo6y;`8p(JmScPNrx?5#>?eeQ}iMV{%AdT#6 zc(wRli-b4doU6jlH}t(W!$+%oqSavcG)X!twF~$E)j9nRN~P2j*Ib&e-wTBW6_N#^ z(hCwGs3Q_Vg)~s<3RF6${f=pW@3h|`?eCfP_XvU6A7ygg)47&ubuF1AFr6J>Iy%7Y z?Eurk0<)(*++(8{$u)C`P9HQKbk9Ramo z@3enF+V7S2d#3#!AvB{<0N^QH+7p-F78ke69H3xf&;-2{77Uu8r*qsx0mBH=Zy6pW zc8x|OVi(DR?5cwV*mb0sg9FmAYYgm~l=dg2{qbpkY-rR`;G&->qdL&2Ny$b{K=w(z z5{FUa(}@3ZV$)b;f7b%pp&gUOj#-c^c91N{j*}n(>Ms@baX=b&%!D1&)Be=7KPBxS znf8weO<92gxuarzdb+hHm^Zm`Z%K!{)G zH~~6KA>lZ7kr;9b1dAag3o>LaB*2g>M1LHRh9QkGWLerjF6|$a_Lrpn#i1=Xp+MA@ zW!9G9I4Ejv5gp?gv&1oGah@?JiZM4svKT|MAY<-_1lVx9*nk7lFy=HEvnuVcO#3U+ z{_@b009+XAcx9Di$x6qP71k1-N&c&P+wwd+P8T~KfLyVIWI=ZP84{rWBceVINW+fv zVaK^?|LnAXW@yBEu%bqsYmIP2>+D1u&djsn0f$^@t`bAugkUj*WI={}4hhizJ<%Tr zq+!S{Fy!X6zc%gPkoK=j``3iFe1QVF+tRt;-095C)|_B1bTvcY4ay!F`mVD>-!;md zO&a>XMti|+c|)Jdu|wajg2y)~EO?MC2#;SO0Wkavi41+DfyaHo4 z_6IBXR&1K`nl&VN6vOXZ4zGZ1ZQ6aM7c!c$M9?93WX25;qgRpnT(zA0ez zMPUJhWIkx@~$OlA@-@dglxPJRO z&u{+_Rps7kURRgZ@RsM;VJ;(#<%{SQ?AG4215_Wu=XyG#{5K_!hy*puuF*FS2v z@nzXx)Al{J6HzkvOBz!-WoTyx=&#n$Kv!gE4Suke2LHk_?hD8$V{TC{r?6ks04M*2 z>yy9>eo2R~rTr`ztw63|M6w`^&VvL%b1D*XCuv}`RmDKRS%tqvgk3+W333H8k_AC_JtRQT6-Wd!(tvCSK-Rj#-!=s62377x zm8?Y)1*^5PQ=Sv-qAw0`R#5iQq#T`0N6FG8O*L6@Ens(F3aJgDUwWk|;zO2cmWkL=T~4Zns!G zwM&Lb%MgfmcEYJ50j`HBw_P$^kAN5KX5rdZ;Cd9f0vE}G;Cc@d0M}oT2wbEA*TH~m zaD_jx!tY<<9~2_?S5^9bm3)9Cir8RS#d!gH;4lZV4^c8Vv?4m?9cB>=bVccb0~PE7 zS$_wzgAyS7h=PYDL-sLv!B7j?Ap+Sa$Q8&)76jQpApwwmg+w4D4ag1!WaBFQF%|x( z5U+o!qTj3J2P9Fv#wk;!6HapQ`Zr4ECdTlZWbtx4p_Upa|lshRIuAjgQ zCR(^A2weX`uE0gIAh@>MQs62@B5;ugTr&XIv?UQlNtn<{MI5{W=Y8jvjlWD6_&`4#@$5U-pny1PpDKoZ4kp)yq>>}UtC_9&TK9K-8q zigNReFDw9DpQ>*m789BJ30gu>(;uw=y>BpJEXUbVZ4A-b*0$gJ#_kv`&#)21|Z{a#m z;2MWqfs158aMeNr;F^R);35sUt_ECJR`{1!_?K1qmxPE-Ri&q?WIB>4VpqZ{6Jggm zh|NUF+_e?aXC2pB!~$JWBJ6SnyFhlC1KA}BkR3(A*Cj(X3%uZ33)wXS*=*zrWF!lM zY$+rFvIR&4GSYzTU|jy(QsLiR;jazxIz|;eRwc(FiQ;t&Ai#5-RjHFQxj#5~EknuN z?J>OmVDWMzOv@0sZmtNQ4Xs6K^K8gm2sKjdACl2J5xn4bi`H#|)^g+uS|kfX>s&|x zTBjfpv`7Q3M-X5SRrn89_(6q#Uxj~9h}n6n!ucw>07(?HhnyID+`;TZl*~O=5q(Jb zxWz2c6(zm*H`#Yh49^|O0QMPO-Q2fJ*zC2LG2|6zMD}p_hJmbmn?j4$Y~i8 za!)&mt#^)}N@)1D!AVlO9Rp?cf`~^uAkq?|m`qV+> zHI&SK5<}!ui-;RZT1Etr*IED5WI)~kFZjd)^05H&CUON3k_7?s2_yiJ_mBu6qyfmc z0Oacm|Emy_PgS|kRPs5JC?;P!QSuK5lP^#*_gzKw#@#Lx{+as?bj=`45sPB0o4$^0R}; z&nTJuPYjWtEh27|Xc>_x`Gxg=P6p&x@PhwXKz`0lEB);%{cS4!mX+qF-c)dNEh^Ow%x=7axqYR*Gq+u(8c+C+(>6HP?>MRF%{Yq( zEo~;&DSN2twY}O@(n~YYnpj7&AnO)E0tC$#qi{eP*6j@IDk}Z*O22JrS_4=xTbZ^m zO{=h`xt=RWws~=-tv%Kc5~@V=#SkW%lPpN{6_5ahj}?V+KpL92hvvIi`t2(HT`T=; zsQk&`M*Xt8RX%9v_+?k?0_&Ho%}nqM%SC>Vw5Qm(3T=vwBnz_fVn~2#XNze#APpNk z!^V!4{@#^-htR;)V8M9DI~}cou6OoUrZD(|4)$1kr;BKQ351E}Bn#5~PDp^lYeiuk zkcQ^Hq4@!oey>WuXQkhx((e}Pe-{cw9dv-zKj;NTc_L=V>1llt^r)0u+Uz>rY<7Z+ z^aoV>{VM&wp@~nSK-9z` zj){XD69-sZf_~P-zBW6-#JngRDu!-At70h0f((5P5@6r+Vjm7j!_YA>bX283qS7B0 zn)tdZ`i4s0L=rtQjDo=@^V;X+Om2LoeWvjiO6JB@Mu(U24m!G`oGM2s7$ky++2e3> z^)`i#uSC%2Kl*tGykJ~q_#9)bVDv6>1tXFLVe|zg0Gbbx$XS9kFggMlO|JAOg#dl2 z%6+AhzafbNG+DctixSj00DX;;xg%o$)mVVs9TSPqpCl zcjO8_Bn!glS4aRp-y;!xNCThQz~`t+e`cjWJ%s2tRrJ3qNtMPSItnJ4N%=enq9T;c z&8>_Mg7YjyfvzYqG}Gb|Ot;5j40#kbFBzj^@PfG(qd9_6333G^k_BPZ8WMm}b0mTh zX<&3TFlwmu>qCIHSLJq4$&N^(G1Q>!k*mF99Dv%OWNv8;pkpjRZVYJ|5<~R~`0PYk z$0Xy^7QA4o#b=4&Q-)l@hh#zcw1))XlR+Z*kOn@d0H2d9{gW#F6D$1_LX`GYrT0=v z2P9FHPKH$`j81b<+8ZTvr&i)r^$>;Ti;9aFK=ULV;^A zas@7u1;I5Q5&+jQBmx&{z;zwqx~9^nK_wHBL=n3NR+$L9(Lrny zO6G2;#7x17up2F6fvzYKc9n%DxWa*Kjm-}u>@W(xF&VPS-~~5W$gUU24o9v)MzSEt zj)DY0HU)`5MjDXa0myEz^lz>7*M)e^QblL0WDb%jUbicgB*N}?@S2N~xw~R`-EHx5 zBTUPX2)osRYh40d^CMjOIN8d>BE6&-zs}G*}Y1|7bnGCar_u3$PZ&OF@L9{B^Um4^qo6t`*zW~BSbCLyVel;XO;c)31($IVuG(V)uA5!HHs`3Yf%5%w@ zT+VgJAy)Zd2(&cUD1(&t;*J4I`&B2M_&e)$4;Q1j+Km`RvLK`M!ZA0AEwGL>j2Z`{ z##H&Es{9e5MR(GoVXiyISc_bDj8X=PJ4Psj9CwTt&F?arlPpN{#~}d<2cj?zNJH}@ zq4^P2{^TluQk6d;RQ?HYbDdmw9AT9YCPPc(j!8;;amNIu{qMV@MvQtAjfgu)7G%_m zkN{iOi!C@H4WnklsOeSy)GB{UXwgex!CI$xOt%)f?wG0!5_e2d208Ai6U|?SFwvZ3 zL7Kk@2~hYoQ5XlLq4@%6KCjB3Q{~SJHUBGE(SAM8Y97piitq(@!7QtK{*R6G7l>Xc zw!9DVVhhQFZ21ZjV8X{@0uD&SmZM=yLzQ128uB;fM-6GPhPW=M-#j~(h#g-;y4XRo zAUl471gQU=sE-5Eu%i)nEUWU5tMZQtP5BR4(aychni3r6_~e+)v*kpw7YNCTfg0-pz}{QIl?dqar0Mh=QPOX5T!dH^Pw zYr#hxh`4G_?%}HF==O+(D9{xphVEB53r6=QU?dCcJd%tN7s?49wirDm7)?X2U_`PY zjPznSvmi(?(u?8z85sSk%6}pRs2&9XP?Ia+{7Km+G4!+p&|=ifZHNK%v<1kGAuU7j zc_INHSqSIpWPD^HoDCMA^@2~h5Dv+L@X-t0gbU%2MhyK0_`Fi(zf|SF5JKcEf&-+u z!c8=WUV%v_hTd=>I-L-`UKJgU->?t`x}wC;OA2Sf=!FD~xZq9hjbx0t>`m~x#ppG` z=q%()43R7dqe~zG7N3ViVu&;_dLJ0QSLMGG0;Ctsan{6%0`#7;O=9RH2Out+llw3R z&_@;^H-@wf!RMU>e6FCZkCO4>vN*wq7M~9UA1;U^_>e3JpLLJ`e6B+x_>cxZe*->W zR{5WY`261LH($aY6F}cO_{i!v-^9l0Z!JE7t|$TYxdNF0ZG8T2-gS}XZ@x`NOqRd- z#v=B$Aa1fHqIzJ|(#bt4Ve_OPE5VW`;j>H$qg3x*%5)fa1Mk4V=8fX<|2KxW4 z@_!8hdqI`cE9G!4oG4)bb>gdpH>32IG+su@TyZ9Pk}JvBJ6XD-#MiHz8(&<7Cs&dI z>iIJ#uDcTyXTq72m!Y9tFh>w0SrB3$Kmr84jYJS54aBwvVx<{#_wGYg=p&VUj3f$I zX@+5ehoR_6EgiT%LCIW;7+ftaTyA`68JiwopHg_sWVAj5FKA)WYA$Gfj$A>DWIBQGA4qRKKWG)+nYZnWb8(&(+rlZxI!gonVs|9#L)}oaWv|1up&>~q7 zT6;hOK&nC_@kJVF?FY2>&G_9je%FlOIfSh}xVcUl_olkFJ?O4uOm3=c0Oh7Sj?GQ= zjlP-HON{D(M#LzR1sSz3B*3U}Eh*A4>L3`^C*vQO@%Ilc>Pd_C(-x_l>eeFHn+Ga` z=*?h%Wsq~*u%BqYpV6FTL7ERznja_%!vxaMd>Ax8B;yas_=7V3fKd6t;6~kXh*drq z0xj9)>5f54dv#M?X)kwi^WBm6D$H;(?GQ92P9a&4X_FuU7IDoei8RtMZ5&J+lkrDo z{1KsDhk*r~oqM@stX-~CMk%wzDI=6wj#I{q=93{zG$&b*=3I6PnokjhaX=cH9|6rL zXZ%SSe?q7^SCWc`(`2i8FbOKcBQlmwu&U?J1@jk(t`=KnL%i5RvLIWIh6I=}UrfLO zY1lFqwoJ+RM}~$hL4MSbDb^6z1xIe49n-{)rI0RmkSxfKlOX}>ACE+$i8Sn(13PAA z{JM-kBQ#|tSkY*jWlag{9G}eCJX_|9EvG=d*g~=(TP}bE*m9IKNb{q#gj>-5-GXCPwl7bh5HdCcvjT z0C91x9DZ{hIi;Ou0dm7c%aGCYqy&5(q^#4D@%bZo!KoIXRf5k$$Q67@7KG0RNB};M zA(4Jf8u(lYe9q7K=Vtt~Lx`SMMW0d0vq+*4oez`Dly|iQ(Q_!7yEqf=NvkbHfvzYq zbgsf#FgiN{Bd*_-Tb+#23*ZG8TZ}Fej9x^pU_`PYjNXL=VDuUi!H6_4x(XOwk@44r z0C7n!l>4hn-bWGz=n7?<#L%@4Kp&uF?wS}t*IIzw7}7EXpEU{id`MYXK{V+K^CR$r zYb-uj3qBtsSMVWO5I)~Q0_^@0iQq#T_}l_~ZqE2?Lwx?B%KcL%T(B#O&&{yM1kmjc zKHsBc?zUJTyWQdw=!z0RYZb@@XyfO3bI<1oO20iBv44XX+-4EGRS^3Txq=wUf)Mkz z5X63gAVG{Y5W5G6-4()BtO}K=WD6uwxbAYo>3#>UEm1OeUktAMEnIFmX&IZ2Rx=8} zKN+o3@Phj+TK5WCTOn7_B3TexJ3s>Bt0fXai!{)B3}`))@gE8S+fkKkqmrGFL;-um ziLWOez_`#_?ul6cd(r|H=!z0w4{dIIl~MYW$%vJM7d&ARdt4ApBUcb3SrB5oLjn-X zA`!$$1F@%p*!mEzJyfCgD%lfB6t4A7d_CvDwHHd}o{hovoQ2DcFD+x!?I);!1sTGNmSTBLzi>+C>(+pOOz>$k}ITW9^!thrmpC8}~e zWOMK7OQu15Ic(dky-CPSYn7|L8x%$DF`|SiJ(Fns8j-#bk;A+`a5O)9YaXCA{7u*mym}L zkF>?ZjfgS@2QdkDQg9HHU`K@qLD9eO*;x!Z8G^+Sk_8!Z1th?b3z3K+q+!S&FeI1t zcgy;_Wc^HN$d%yc_Kf*9muHJy{eD@$Z)nLYD3BYL&3)w# zK0~ZA!64|$X%q*a0m>S=57o~`XkTSc6N685CF|GGUN9^#HdT&|&7p$F8z?M3C0P(2 zpF;v*;CfdQo1}rqc;GQM>yOU*BeVYS5R5Ot1y;_mGu9&Ex^=VyLWZ4@&ag9FA>jn) zp<>9F5G;m}EXa^z{G1ntaB(LwgftAPg&{RrzdGw5p7jsQ`V&K2N>Cs-Et_km&5^T8 zjWs8zhOWl3hbw!;v4>g5PE_V>l4DEJUN9}su`0(pcBiIX8q|Q7+lH;SUHZJZIN&tdz1n~96Qr->~w{M7o3piW|d>zyiCy92ZaS4k_Dl2AS3{kt^x`UNCTbI zfX=F{zcTBu$ok8(eq#uYEW&iW_Vg&?vdZG(dU~aTMLfO2@$_=%xKRP)c>Q#-i>o<_ zT_g*#iz^Vp94^Kr;j308%3Tb*F3kGpXZ>@t{@Gdo%+RjGP!d6*B3SIYFxjs29lOqT zY&qLGJ~Pj*)neCVV;9MS?5bCGaWNvXi!}Uo73{hq>#xcBmxdNC0xNe-Y-)6cH7ZyG zElm(#s;puV^RglpS)91ZId6Pov;<8C*W?AS%CW(FwSch{g~iDv3j$*WB*4kXBM~r2 z1B|r*;11fT&8cAXW7;M5h^5Nki2; zpz7^e|JJO(F4UGw73J=Vomg(S3J143ep~lH;d%?qM{NTmrACcYk z#b$KAcR$(-*5|oS%W%uUk$BzT@`&pC2t~$-g$ZB|1ozKU~*L1-=2vPLxTiOGD8|Vq?ZWNBs3(*APEeT zpuu4mcV89;g1as5?rsf)#ocX@1cxBI5ZvK=&pCB#x>H@LuDaj<>E(Io>QlGQ?;d%( zx~uw5halxVDnI5rZBXapq_;UTH+2vfYF2=a<;*j!vjFA5QM}8qS5)BDimcsz&uJny zZ4gC^u0?u>vGUYG;aa4(wMOr7DiY zMCeAAQ(d-K{c5GwGW}ffLi({r$>tE@E-f{Ynv=0|b4!R+ zQ;T$XF7|54#LQH(0Vp7}02?it*p#eqOIx9LOQB~=p+}3mZ8y*k9b}spHr4g&-6C1q zBDXm!>eb4TxjAO4*PNa8s-!B=&~o)`(Yt+m6Ql>)oPqVc<6eP_i|(AY%Qcv>@*JJz znqAA4W3QG=%uMAfp+LEoVWZ^|n{q8exfW_E^lvH5-%^-2tk_C+^vbpw!=}1o3z3y0 zY(PcD#&TqCv6ku!xB;CND+i8BSbr6o3K~QC1$2_{S^huwFMh3 zm)MkR1%5ROEyYNwg-E)WMXD2*)b?kgu~cq$;75) zZIo=amclA6g)w2hEf0UagUsnQC-C3M7688?BMp)M!I$w0=vW zy``{DSfdN<&=>5mUOQTT z6bz^P*;JQlcd~LXy?rXmG=(E`d$&}74Bw}sOo5}m^mescYsq%5DA|rRO7?&V?^C;E z|6;7XcW24=(vm&MUM-oJnM(E?3S@6Th{hAKDcL_L+230V2elLq2XGCT1)i}w9`9_Rt_8$vJV`DegE{gux*bSXUxn7GB{@9q9nTpcNPyK+@qHGi?u|eu~igIgMk;Uzx!M4e< zsV3>x3X<-ssK^o=nY(kQirm#%kxG&RjjDnyDgJlWE{OapTKUe-g5046kzYeoO2o`m zkY!PzAoBBQS`e`*$iFDal$OGMVNI5^ z)}$ObDkb;Tpk$N?JY2gdqZund)LE1VwJ0mHSBoNMrlQD?l#!+UcA6GNY>M(EMR`1| z$QpK#{5%=QuEnOhB9B*4@=QfV*5=6E(=FU_wU16)$j8fPDk>5U1H9PsWG0jfQOxYcX0@=wg zf@yYQlih#G?u(YfXDx;4VQL34MB0|xc9Pl`ovBs6s6VqL^zC7K=kws}j4w6vgAvon z#mp4>F(?rEp&Bqx#3u5ei2R3^!gno&Z(0g7!r+f(w7M@pbOvAkjwt2iE`9l?vjv@f znbEnkMqeU-k@K_Wcmi{3j$&rY@d6Y`?MzLLCt{Ohb1Q$l+EVzvrSNN*;Drp4d_{Nu z>`bt-JHK~!r2K2=^PoFjT4lnE5Yx!T%oO>ZC?IsB2Fw$&iM%(F_iQcnXf1SWbvN1W zvP18-%{^?Y&mcWpJKuR{Z|%G(S?0)G-_~j*XK(GiDH%BGIkg8O+^JJ0yLCPf--YiL zvDxJxLyg|szK^kT-`4O(WFM{3{p{5miJ7TJPoO|)9%Q4hJ+Z0LeAK94YhmuNKu_9n zPub>aHq`~{XZh$yy8aafdWIu&3(QoY{+$J?q$1GJ`pjLUKF^9)|JwC=j+?K&wLW5Is?S>}P@k9CXnn+{KCRSeP-|g8Yhlr_L~q-nQ*ASiO?8O|k&^rLma8by zI~-cH>{OYj-6TlD(C&- z6$J_$6`Ub8it@b(46j|39~dhS>nzIBT9hBzt3?qrQ&D>L(xNo6(V~b=QA!kLbZcRS z*240wg=NFi^tPk>*rqR=>e7rRE62{5iqg!%k-3#ytKU_|RFuX!%Dc)6L4D<~ZI^G= zyZrjQ?wz}9ysy~Ttekho(c*bzx-qp2*^jaE%AJK=NeekId$o{aW-8=B6qvd{8!e>R z6mo3}xn^sjt+lXPSj9nhXp3!H*;H3?%^=gJhgb(*QN_U=nHxV-71!ykVsMhuw`Qjy zMQrOV;%fC5F)y>NQ@e;m7%PwOEaEsV;!^C@B8r)*h%2B#5r?tSB8p8BH=~G~v=%mM zElg-FY!KFQlpQ_VHY>8JuHz;o>uB7fqK+$ZWNy+-b=;z}j%DX4G;Y*cvGRn@LT=Ex zy9SLFpK{#yQLD(LThuP+s*IHm%1vd? zooknJGsen0b(V5RE#>Cy)l!O?wv@Z&+nWpR%}YoL3zYAHd|ToEeBs`F;hucqu6*#> z>@Vf}^Kz~lDGyBpijU_xd};9+CY5ZmYmtA+-r*Cv=5=@^Y7geicjd2{JXyXApWL@; z;6e*2G35vIc&+e6UK-YW@hQhn{;qFR$5Fhcj2F52^`P92{ihr;Ti2$JV`Tq09SG-{ z&@GSmgs$z)%areBhU0=62CVQ@zNvhV1{=iOQhYMslxKH)^Rg20a@zYFo0^)&NKj(& zgPddc4ZP%BEBpAvZuVL9eAb-YcRVNGBJnGcohD#MQ2)vv%F{c*{I1Ru{FsxkU4*R(tbGTBI8yMe3}U0ihSG)&Poh z{Ggc&wz8HooVvYvjFKv(WFd8}_U2Wkhig%wS0VM~eBs4>;rV>wSx4&H<(I2SeOs~_ zCq9Z+KqeBVT^80@o0pH*}h5 zUen+$)2z=lZ{^F++iSq85yJD9&ht*pJW23aI(W-G8!93LnrD6;bs}POD5lT4RXJa5YLAvzVD;{?=mt z%Ec@;G4D;xdk!h=9>)9~`*XVyA^!koQ^#q9sG$?q$%D#!4v`;(*AUCQ^ZYV-{&nB+ zWA*4!`)I7+qoA>hnKss4q`v#maW;Ff(fW!_tg8=gE37)SFm|Y`@4oCWj~yB=;|=ON zW~kNoOsVgxLtTCCKmz8EGCS+rHdLnC4<(IR%(O9goz&jEWqb1$66==4xyU5et4u2N zpA^KoRk{BpIlUJLPU48I<*;pnUBv!<-=^|Hla5|xzY+Y;8^E@?{*yXKxkWJY*u(qH z)n$YzFuWb76xG>2IEdQwzBg)7(cVFGkf&L4*s;C&ZxY;&^R2` zI+sm3XVosq+#TmRxAS?D%S{SKDZDFfS6AAO3*?X?6^GE9VV#}nxKPxGNU!8I(J^gW z6CYImqSIXDrny)&u4%Q;6?X`M7LL4V^bNk_5{}@MZGQT~?wYq)uaS{16Pok+Q#peHqZl&8&#>=E+}YZ`S42T_v|8lo8)LM&;Bm!s8I zxRl2rx|Pae5QE$5T#bu zhC|KsqdhLKLuEN0vv|K8BJXIsETiJ^pmW$GC*ivN!Et*|=sxNp zIU*k(x0lB21Q(PT+MD;D&^@omwKwlGq1z}8G_SG9huZzhk|IY|q~G4Wzt&!Bk@PNE z>lA#5*8Wk1+X@f!7(nrloU~&KlQnhp5k_SUYYuyn$o^4}v5OKNssWghq4^z0@@}L- zJc%CP+VU6#(Qy<*yc5eiqclT5H|L(=0DY^n=w_Gb#EF-SzGQ-$cU*y2Sq>)H;&W_G zLq1yPo)(RnG7JvY1f7Py$#xs{ym;q3HLewnXGKHayAtBKK5jx0AU2&)vF_rgm1|qx z=yh7smiqw$K*!BIDNF3Q83a#ZNM+2ZdW?Nwzk1m*Z7-Eu7C8iJ9uWvYIIYJuQ#XZw^ z>s5Qm)x*q1dyiv9;&T_L?Z^`63>W9eX!3_LJi0i)mH;LE3fyFTCfq(@mjv^T3&wV2 z3Fb!^%x7q}6{hp(g85Z~`GOr~*-PKtR=Mjfj~x^FuTNL^>isSB5H~#Zn34R~r(Ch8 zi}~vQ@Rk2NzV0Bm758qvyQs>X{HJ7hH1l6K+1J0f0sT3XNjd&RLQe&@BTG5DqNJyS zFVSo({D((Zj@cN>&0t4a_R+9lh}i50oRMZt|bjt{BwrE25Ix^<|^AvmIG# zH#ZVmyYJ9!D}2MFtKB>dNtp)B{MI7}!HJ#_x>`5C4B3i&j^pi&PLq$aW zgNRn1`RpzSQ7t{W2NC@oM6{rb$aZ9jXfYSjZyM1r6%oljJE_sYnQJ5m1+S&%u9cPg zJ&0?di_3OoiED8eSJM^JyFV)88XUwmX68!CK~zfUBQ74t2lZ-3Lzv3BxNJw3xQ4j6 zdT3nTcr0|`!GX0Df}9O6DZy|#Ty9U;jw~fu772Y>&5mYUp%0HP z`{its6>Kw#O>Q2B<^8K^iDM^U-nT4AS42O0=0hIpJM7q_#*XFxrcrZnti-$`8;#j^ zWQlnU5*qV-XtG|0M;G&0n`AZHtj;F45W^Pp(cIcA%hB-e-c;IVKIFl^!;W5k%vk*1g<)6chx(S~Xo@(3|K+T| z;mn6zPMwcvH8vLGSc!Q88;#j^WQln*BsAv1Xtotvd2}&vZj)?jo2}U7hA`~v{9xa* z98D2N@V~^o^~{HSPo3ST?HtES%-gWhm~BUvn0G)zV_q7~wnBl&!csiAz;|K1EIZ_N zDWh!r>PaTDcaAQ7tfa#@Ov2mMg=agmgtw;)ZzP&+h2cE9$o66=Cp*gWKv?$9zaY<~ zfP2>(?$X;0%N_ZMceij@Zp=r9dxpbuw>>gES2(J;;@Bs{mK@)Cs7pvPcJRk3jt`_AOh9t@p zU6i&XOO&U%C|5L0aQ5YibgB-@cCq_bT} zYiUSp@K{)#2N%~l5|``D>@G_waIQ}49&wNlTb5_ab{&Oedo%w~_5zYnf0}eGd)f*|^B6Q~!Lk@f zk3D&?vOW3)EID|g{7F2cW%9KmUoK7=*fi=m+0)*XAkAr|QUQka zr|ZZWk&(snXX?m5BO?RyXX(hPWQKBl36Y z$lVd2k@AVu3{?KYIYM-nN_p9n2MvCJ;YSf)RenFC51>$xvf*uSGJmRho*G8gsG<7 zdMWAaQO!PL>Pt<{zGCXDNX^;B)E9`FbBL+zt2w8binW?^iK$$wIk%YFa5d)~n1b9oDJkYUDz{5Y`btq#?u3*SCp8xmQyEfoVKEgP zH5U<6X;E`gF%=Ot<&H>6xlmK?f|L}7@vMZ)2dyvZY28k#DNpMq&gjG3vPe$qACV$| z8^&YdJsyHH`|z?D$4-{N^gO&@$3XrSE%}d&=oy2D9Xnb6-tq8$TQ70+X=Ku>Ts91-wqX`nknm(Qr1x(^Znlk+!GYO z8(NnB7z#7wbKhu>n5{-5sZsN?JfOz8G_U=WC8hE?=|9rUEMSdkZ(doz8UtA0AktQt z!DHb|9s;n&mc^(aEbXK8tLwnxcX%Sc%BXMUNj@-Ft4DEHz__JvS)yS%!wCK-?>1)_ zzZXFXe2r?cEc908mr5W7y?nJ|^sf0o9dJ*5JxcqUsJXDV*8g<8edX1ri_DuSuv~4d z&F73C6t|F(@g6BeUwpEzStn?3URPgy3U`(l-}<^}*_IUd-;7_9BkaPj^6;}f{K!M_ zBHW-X1{abn-MgzrPmC4sVU;hrE?4SHZo^T3;?R^2%#F&T=-$MdD4N|9ltwQypx9NM zjK=JuwmH{Yk%tic#2Blj+5QnciA2mFCcRHYIvCh5H(L;1FKJ#1>Cwj`EydVBf2K?_^9=3H2ju^0vmcoI zW0vuEiH*N_mMG-rBxCNKbu`zEF~Cvp}qMZ`SYSP zonQYOHa=WtT|pFTN^X(7Z@EC+R{t z9j_|2E|SY%DCOpuqa$ftG>bHjsg=gUF=-t8|0#{*(5aEe@$BY4=P{PZemQy3N-x8g z>>4F~kyLP!2P*eG9i~KcOlB%=Nwd|_#au`1@ z@+xbqh3BY~0)6>2j{J2|{p;)2UvZZD@<$>08>0F*)~&z#EcNAYP4YKI^>40QzeDb% z&2kR;W0m|Z(K&9de-62qH_JKX4_@-OMd!G^{yF3Z;VkEnzntNW;aaam3UzYUP~HUI zj#rT>DG_SECZ;B@=Idf=oNE4COfA2fZ-}YgR`X3U6<#^>$n<$Px&HCayWu(h+xa+W zRK1^yK-`J_5|pand+vxU6Z2jwM<-3iCk_5WIQkxP8O|C?#cLYP%h}DP-%--A_U2u4 z^6^p17=C!{ki|kJ{iLX+kd;9t{RF9|7Fo}=YHE@7oT{c4Syh9`58J_?+Ew z4Ts<&YrffB$0qjx!_}Wa%i>1K6Fb+0QJs1@|p*okUv}C zFK?dFv^t@ZKToLUITaKC_fW|#rkQTrca;CvgAQ)p2i@R)qTagixYsZ4=pDq4`?RZh z?J7;aU(9ZKJ>g)=AC8Q=FL){bOUC%sh`@XZv+4qWrW0!Mc{xzu7vzsja`$6aUC~z_ z&qcd_%pbuOfn1$Eg+~=tQV_dQIQkKURQ72O%D)hVBY%0Kb5yx?^zZ!c%+^cJ8O-n; z$B%kAaDGXYUJQ(v#ds+&UJ>Kvz>q&E$-fd9uZi($V7xBIYk~1^FFy0p9t-zQn#@m6xUpEKETg%>F_HF7|YF_)`(NEu!q_SkCf8Q%Rc$2g$ z%AcszQ0-PW82X1Y z3PCiF`DdNSXXtq3@j32c9{-h?-Vb8>Qj8A*Lw=JX|6yRr{pS2ff$_B%9|y)aVtf)9 z--A%D7(|28mWQA7T_z>p;k`R@Zm7Bu942n<=ykpD3-x{2{q zV06c@*Ko9bbIrPavh2a5eY4>nwoevGaGBy>xN@Gz$q7L|U+Yf!*t=FqL6xU#mlRWZ zIvlDJ}AJLP=SXrxQy`iagz@q@2jp zjY~?2Jl&+EjL6eXOG=15-K?a1$kWYBdcu*XlS+EJk*8af^kgGXw=C(YMxJg}Qj+B9 z)+Oago^Df8isb3GC1psSZdX!*0e9Ajy(NaNy(9?JC>9idAd_c zsgb8Umy{WKx=Tq24)G(aF=@OM04*mh==ZPxbCbNzWc?%KeR!oYyjobyO$GhTV_b;KdtiGvs{vZ2;HP zzB46RGW0*4Qs;+0{ut1{?e36;P5;wD_hbpn8GT(J+`F(W!14&Y#%DfR!^O>dZ7Q!T zS;NI=KBXN~zL(%*o_>16TmUot2q;Uo^q#?e0z{VY6+2`h7qYUvOJ7=IbI(BT=(iQR zu%@}tBoBWuLE$$Z+>HZS@r9o(?b78Tc6q)zuY5UGG*9GGw=BnZ-YSsKk+Sq_=G!}> zA6~(iWg-Oh4o}p-1^=={CEr&Td+i+B< z%xO+lvFP^_i`N^mrfqkoqHzxvm2c$pqJB%_%G4B7Ci$znQQagvYPJL$0MG<5^CH!q zv6=4C1ch^9@aeF%~T&DbF49-sK;qZhl)e}>B;T3 zFg>~1MtUkndc#Dj@_WjeqwA&7Relv&c|`DSBR@c-$7yuK(?vI;GP;o#or)3NvLaQ* zPH)1AV`q6edZwG1RfIX(UDLR$S=}^w%@jqY{^G765zERi<0s2~MEUDLCLYa33n(_{ zgt{=)=RuN<2z*tp`MFL|rF%}Js)x}sW zFywC&^8*574KW6akslQ7T2qV`-PIcGT1$2YyVjOnIo-8Huxp&`T2goAgI(*e zORHFxQj)$FL*Ct6D)-FQ#aZ(AK(0*da#)ylI|lc>T@|#1QYQIat_2e1_L8PAPuDAH z^73^3l4dJUHz;WpU=tbE=qHRW+xHsdZQL9Wk{t@(ERnkas0mAEWxED}VbDEPOdc zZVv}F=f=m$gZXlXM_InXugVJY;X9PRD{P2Zh;W^EjfbEjL{5nKruzK333pz8A6gwO z2%J24T;9zvks0(9Fpo}|kownh-3O z7{QRFyEz*T#&)C(W+W=@&HdV&=aDe_5yA^}t*ua$*_V@tWq1fen3w5h>!P!+#C@jR z$_(XJl!vObhj?_ZCJGl8cm5oR`)**Yh*X{JSHiU{vb>BGxIgD?YU&e8GxZrCAC{ijCBKJ9LA_ofiYf;F@dp;9M&Ef z?HDt^=~M-xJ<`ut6@>^^VXRjvyS~V-7szf{kF30E_AN(cCsfK#6xsCy*^Nb3-dOB| zk$$yUceI;S%5EyM8w9eOi){R=l*kNmflrbdT+O$roNh~*Zo^=@t!28TEcjiAn#I|s zQg&OBoe;=wFS7EIvsGt@$w{hK=)9dqYrccXy3qexImh2*j)}n>JINd=DrH~uMyK1k za)w=GhK+(5c8ktX@i9G;Puv8%i%ivvvGZelm5838_mHD!`sh`4l)MV!y1pmQVd?e~ z!@bh>#>j6RB(`robJ!I@v|js(b5%N;e|RB^>RD%Dg+*E3ZdDaYU(_WoEgT06UL?NZXW6M5RTw7&FNo^~tgX>N34>)^2SFsi4U6}#tG>Rcc?+XOlnMRc}hB<>V* zu^cUbIcM+0Ze1+Y*L-`qq;lFzW!mk6X)ljVyZtPty`uKC-D9S`QVvggrN+H{u8Kr9 zt3F;`&s1?QpKEXqTYaq1&YzP*eQ934$yi@dQ_|C$JndW3SH3)*y`(P+c{)c) zd6B1cmbB$^VIoQ8T}ppqR9=|Os~09+`;15KrVJ(1ovm9!)Bw7I0I$X{?%9{Ng^bF5rB#~2J6 z=hBi&=cKCAIIX8OPOE8+)1<9&8k=-WRPs(^tVqf?>_$qaZ?rnrL<+2l@UICm-!WjT;UH1MwB*HB&bUjw+JW%^7%ox|5t!SB&j^$H8+K+kOz?%}Tx1n!kfXXM^mE8CpHtC$?}n)oN@{*GVn=I)a_Yl>8akY6Wc&HW9D zU2}gon){m!hPl6mLGDiBZA^rwihpwM@A>6!?moHq8cO)B|HvWX=6MiCuG_9?kuG2E*Kcz#w<0@FONdKZ$>G?w|VQZtgz0 z_Zd)B5kmf%kTv&TC3emIvuN(WF&O6lI|jKsg+DM6`cwRqbN}2gcXRj2z3YIYiV$*B z_aOH!Jh9xri00mv!7%r380790x?>{LL;RC-|Bqkp=I)bw-vLDxA>`QzS^M5gV%NU^ zH=28I2E*L@V3500=!=Qa?BbuC`uB!%84Pn@5QE&E!a|q` zEiC@YxqsuAySe-1-hDt(MF@EjLe|_Dlh`%)Z=<;nU@**mAO^WRg+Z7IwTORm?%(<4 zZtgz0&oQ8=B81#Z$eR0LiCuI5KAL-u!7%qFFv#60EQyIwUi_1D|G_VJbN9);$AF@W z5b_X0*4&3m?3(+J(cB9RhPnR*gWR3M(wGPh6aVDgfAY)S+<+{_8eq7_<=!LUNBV^ATd(1wZ78seW!$De+=o4Zf$T;;0>A+Jfun)})kyXM|>ZR8He zI0nPq$77JYQ&@SSIrnD7J?`$9yHD<1<*NuGw-d7FzP`k+xp#@?z5#<_?i*r| zyHl8eiO@vxPtLuoU+(7alRH=WDniH`5whmKiNvnCcZ=q}DT86|n_-Z>`@Ryp=H54& z`+f|Dx$lob?oQzVOoR>;|K!|f_siYfeRAh2UquM{AVSvM|1Pm>?sG(QKZL@+@S#v*CV%OZ~jplwDgJJHcW01R3I0F-*GsQnS_xb#CH+P@hxyn}&LjETq zYwl-D?3(-h(cI5rFwFg2403l0=V2mrzW68SzJOou=I)a_SNSSJ$QKZ@=6;dHuDSP* z=6*4QVeXe;kh@d36ceG##6LOr1^se2cc0w3%2yFWzMPOX_bVlK&3&P0?pHAw=6*E> zxjThxFcG>|{F8HE*e`c;_sN~Bd=(+&>j+tMzd>Tx+!u-Fej|fn?l)nOyHmIsv*uO) zEezxrm0X$URtz?Gut};ApFS4ztB|?-RER5G6RG?ykm!N{mJadPB{kO*nEUhm>eD>K znmS7S_Dj{ThNRJwNpergzo_un%f+yT+%-os$n+%g8u)#y>U7n98t@lODowhi=ao4Nb6jhizjlDTc>-k7%O z+*JDks;zB%P|B`t8x(EZLkxy(dl-YZIfX|s5qezwliSwf*EVzaX&dJw6Up2*b8k%B zbZ)Bs1l88IJtbw=wzWpv_B4ZG+n&LoZBF4?OoUz#|KzqU?$TYisrH*xTif=wlwI4lM6_*F84TMt4TH8hg?BI!dSCpL+qR@%+sxgkZCsq2NanVg zdt=(Bb5rdPsJ6E4BPqMKEgx;$#|(yT`vilwIfdz%2z@U8$!#0r*EVzaX&WDlOeAyL z%)K#f)48ek7gSr@_FpNxwr#0s+rDHlY};2Dw9P5Zz(nX<@lS5sP`|dByHDG=^=%@V z+h*>KX`9YXwZEg<+O{90?Ao?Mv~52!7`E*v4BF-te#S)TH}Owy+h6?JX6`<1F#g+wf@HdNCNj+InNqHmA@B6QMc8Kl#-*!mn-S?$b8D z8#R&4Z8P`Av`y!x+H+EEZQI;Zc5U0pXxrvtFl<{t4BF-t=EX#40r5|6+cJJ_Gk2f1 z@zth@WNw?eH>PbmH`VS>wY6;vN!hh+%SPL_FoR*+7QvuxPGM0@ga(R#a@&^kYn!?I zw2f~jO(b*M%)K#f)48ekAgZlxYn8HV+m?^EZE*&}whhLhZB8MFiBMkrliODGYn!?I zw2dzoO(b*M%)K#f)48ek5UQ=e{$PK`L)g5 zecHzNf+mu=ZRXyXw&~nddnDD?wk<1V*S3w0wrx2E!?rDtLED@{5fh=&;-B2M75&;~ z?mlhfYdsUm+%|J>OxtvBs=XrB*0!xAW!JWqqHSB5!LV&(Fld`o7>il+Te(#j$gd=A zVxCno*tD^!qq!^lHP_sIn#;FxCX%_i=H8g*>fBU&4XUlpT}#TY%^eeM?%E87%^in9 zbDhF?OoZCSKlwE|)~{{m?$b8Dl{1mdZ8P`Av`y!x+UrqmZQBM?c5T}#(Y9^KVA!?^ z7_`kPOvFTJ6Y)=O+p2zTGk2f1@vWSRWNw?eH>PbmH`U&hYHQmzm$GZyR*SZ65`$se zw!olmPGL(-gtig?FU?mlhfTR9WS+%|J>OxtvBs=W)<*0${?W!JW?8ExC{ z42Esn1B13Xg*`D5+DH78+qRZp+sxgkZG0MwzZ>e zJAlEkZ3kk|Hm7h9CPIgZe{$Q#`L)g5ecHyiawd|wZRXyXw&~nd`yW(W+jf|gUE4N3 z+O`e`!?qocLED_d5ts-aCH~26TgR_$=I+xrzLhhP%xyFG#g1y->+@v?$b8Dl{1mdZ8P`Av`y!x+UHPhZQFTL zc5T}R(YBq>VA!?`Fld`oxDXSeOT<69Z5#Tv&D?$3#-k7%O+*JEgs;zCi zT*|I(n-Fc=6%2-LyAp%8Ifbh*5xQ3VliN1YuWjb;(>A`9Gm*?~Gxx@{P3NZC*HLY4 z+YM57ZQDlCw%y2J*tVN6Xq!{G855z~#6P)h8~e4*+g3I+^=os?$b8Dl{1mdZ8P`Av`y!x z+K*9fZQB!4c5U0FXxpA-Fl^gX7_`kPJdKIabK;-ewk`bHX6`<1<6Ais$=o(`Z%o^C zZmRt})z-GXC}r2SZ5eIbOALl>dl`eaIfYj+Ykn*DDg*hgq)p888U~x!*(5cW3*xQ) znrrSp&E@MI6(Qt*6S7w5O^IDAv`w@^Z!s8F=xq!t6Tl|-ZT)gLcc0w( zMp8ux`5i*m+~1SfHTUhJxxdd~nEMA9GdeRAiHhKdmKe+XG~|59St-2WEM z{VN8;+-G2ryHofY6QOU!KRNdu{c<;VpWL~=R1re{mXI~~?2Dv+h9+(KtCjQBN-`y{FbN9)e z?+a9fkb4rc=H6Rk*WCAr=H7?FF!#O~5&z`e z5A@63+B@A+R3M*kEw6gdo=YFVP?&j{3J8RukgpkJ&vgW>u#ICs?7R`NC z2E*J}!ytF3usUYVtNbZ^Q?ivW=%GAROoQO3Yoi4g}BOB5kg*zkhMbNBzCRP z5zz{bXE3bLIv7;QDXfc$P`mgi(=pjEcXRj2ovVBmA>{Q4S##e&V%OY{jOM-}gJJFy zFv#60OvFTJBk@np{V2cO&D|$=uJTockT)h|&3#jeU2{J=n)_x9hPiK!LGDgr5+*`h zh<|eK$N1%L?moG5m9HX%yd@!P?psUjn)|WQ+_zyc%zax7a(4>bVIs7>_$TLnoL}zd z?vp!L`6@!lI}ozw{x^wTb3ZAAmvbPT@dIgbot_1*@=YE=B?&j{3J6HKCLdb^`vgSTnV%OYHkLG?PgJJGRVUW91I2se7 zW5ho>_cQ!*H+P@hxyn}&LOzy|HTUBscFq0FXznL480LN=2Dv+hlQ0oFS^Sf8|EFK> z=I)a_SNSSJ$fppp=6;&QuDPET&HZ!+!`#onAa|#5CMH7v6#wMh&-TmR+PV8FC=8m{bGq- zb3ZSd`y~v9xnGJw?oQz{OoT2M|K!}y_siYfeRAh2UquM{3PRT0uaej`_Y0!AU(H~c z`!yKk?i8-YMCdy4PtN^9zue8;CwH#$RfLeQCuGh2Mu}Z>zbKmfO$>&)-;6=-PT>|z zgl-l8&D|$=uJTockl!I>&HX)zU30%Nn)~|6SAa(4=!Viz zKDl$1uOfu}Eg@^}-%IS8`|Z)(e_$}o{YMOPcM3mYBJ{KPC+B{LU+(7alRH=WDniJ= z5VGd}o5ZfU-x5xLQOsE%Ka|C+|Au5cdqhPgpivFS#$3yv1{&k zM|1DSV3>P%403l0JunfPP5hJleve=7=I)a_SNSSJ$UO;JbMGy&YwqP}?tK^xbMK2m z?oMHLOoZkT|K!~7^~>GdeRAh2UquLcPD0k)=a$$t_xqx`&%RJ3utLKzsE|__fr-#a@lU4XF~8i+-6wah@>PV8mmy@$eL0C; zbALRV`|=Eixfe0W-6^bqiO?wVPtN@bzue8;CwH#$RfLd76SC%BlGru(C!@Kq#9)~F z${6JC6vkj8G*>sES#w`aV%OZCj^@5PgJJG%80790*1$w) zP4Q38{TaX9&D|$=uJTockk=w)&3&B2uDL%O&3!zBVeac-kh@b@7Zag&@lVeEIltV^ z-6wah@>PV8*CS-jeFKSIbALXX`-TjLxlh0#cc(BB6QPa7KRNdo{Bk#UpWM01R}n(q zn2>^NS##fAV%OYXkLJDygJJG_VvxI2*b5V( zy~RH{_ka84Ztgz0bCs_mguD+SYwr6=?3()<(cJfEFwFe`403l02Vx?0koYI({-$5< z=I)a_SNSSJ$OjX$=6;C8uDQPz&HWz?hPfY#LGDiBFieCx#6LOrxBYTAcc0w3%2yFW zKAey>_sJ5w<~}u=`;iQWxgUi=?oQ!oOoWaR|K!}K`Q>izKDl$1uOfteEFo*|$4l&* z`#aIxPhc?2{X`6McM2zAB6PC&C+GgIU+(7alRH=WDniJo5VGcen#8WTzZcE@bOyuR z&%hver*I}FLjM&1|c)|NYo{ zLT^_0|39I}Yh?`mk4@~K-Th-8TD6n>%ejxWHg!BdH(fq@?7p-3S9>kafN~R{C~>z4F-qL@C~>zk7!r3I2E;jq+c6Qk zNBonC`_zv(b5GH>|BvUmdP0wu0ObWhQQ}?_VwAZ5Mu~fw!H~FDFd)t;yo!m?o8q5L+?RgDnR{c1 zt0(k$N{XpNkJm~~oXwq?ICJ+Qj&CYd1W?`r6eVt|5TnF>6(w#OgCTM6U_hKxco!3) zkHkNjxEX%LnR{c1t0(k$N{XpNkJm~~oXwq?ICJ+Qj_-$51W-N(6eVuD5TnF>9VPBl z21DXL!+_KLIPOxY2%yXW z6eaE(Ax4S&HcH&L42HyghXHX;;d@Mkei8p<;=c1E&fFVATs@)3Q&LPFdc0O@;%x5B z#F@JfaeNo5B7pKMpeS*_3o%OE_fg{hU@#=^PYj523QfI~xbAG~Anpf0;>^7<#MKje zJSD}{p~q{bCeG&0Oq{v<5XU#rDgtpm07Z%GDa0soKSqh`#b8KWZw!cY3VkpUnoInX z&v8Hb5ohj=A+Da#<0&bo4n1BgHE}j~X5!4BHxL8joWdYXgmU7aOx$mN#F=|zh^r^`cuItNPgMYk>k`EEiO^R#2InZTwF zF1!12Y3_~TvYyc6St_OuJzgs{mo|51F3sJCOIFdT2%t;^6y^7<#MKjeJSD}{p~q{bCeG&0Oq{v<5XUMy6#^7<#MKjeJSD}{p~q{bCeG&0Oq{v< z5XUMy6#^7<#MKjeJSD}{ zp~q{bCeG&0Oq{v<5XUMy6#50D`bLR6h{2G!gE1h^Df}H1p$_p+CT?~= z;>^7<#MKjeJSD}{p~q{bCeG&0Oq{v<5XUMy6#ZBhK6#LtH(f$5T>F9eTW0 zYT|6}%*2_y4{@xbQxQP93{aG~D})#&Zr&(yS27q9cNGT2Ifbh+5xPPAlZl(pk2rI0 z3~}{@9#2Uzb?EV0sfn|>GZSa-KE$z#PDKFaMnF;GZWdycxcQ^R-NIl<+^rZ8=M-+k zMCfkuPbO{wKjO^2F~rpqdORh?)S<^~r6$hi&P<%S`w+(}Iu!wwdjLg=yH|)&;`&F4 zyN|(;xcf06&M8d6MCf7hPbO|bKjO^2F~rpqdORh?)S<^~r6$hi&P<%S`w+(}Iu!ww zM*u~MdrXK?;ueY$_c((gaZg}CoKtub6QSqCKbg3N{fIO7#t>Ie=<$>kQ->a}m6|x4 zJ2P?S?n4}_=u`wyo(B{q?nNO+iCZK}+)E6G#J!9GaZceCOoZML|77A8^&`&Q8$(<@ zp~q8FOdWc>R%+sG?##rQyAN@!qEit-c@t2SxVMEEC2p}OaZ?!#iJOK2aZceKOoToZ z|779@_z`FBjUld{(Bmm7rVc$`D>ZR8cV^1{{D?F6#t>Ie=<$>kQ->a}m6|x4J2P?S?n4}_=u`wyz5)~_ z?rR}NiED`x_YH#~ao=JZ;uen*_dA0jaerVyoKyG{v*s$grrxZg8!Ut|PcsIa9&GC1 zGUvyox&I$>*+Y6>zV4dlrei1H)jILm$uG5x=kebylpv(p+%4IJhM!8%f%4Kf`LoWMZz@<~@i;2+O;-7pbT+)v?b5GH>w7(2C zi?-DhdORh?)S<^~r6$hi&P<%S`w+(}Iu!wwc>qO;n^%ZY;_^}A=3_7GZSa-KE$z#PDKD^Q9x1R1_&`q+)`2E z1~M2DHwXjboI(pGLQ9B$GI2xwh%@)b5LZv=@st!(haRt$nmC&~GjZnbLmaEPz;E33I$ArMu>khaewh6&fFVATs@)3Q&LPFdc0O@;%x5B z#F@Jfajc?K5kMIUC`#P2LW~l(bdLJ1LB;*s+b6^DgMdC zjqoGR+#5q&J)y@_QcN9syjE)BZ0^j&nY#~htfEs9Kv@e=l(=z1j1o68O5At`L*mxK zfHlpiBT1C2k`j zMu}TCO5DZ_hQw`x0dY=YQ%r=m6#r!6mh&Ud+#5q&J)y@_QcN9syjE)BZ0^j&nY#~h ztfEs9K-mgVl(=n#7$t7`C~?~|7!tP~2E;jq?J*JBN&J(EEBX;lpzI7NO5CnOj1sp(l(^j(42jzv1LB;*9+(L2EB?vEjq)ST z+#5q&J)y@_QcN9syjE)BZ0^j&nY#~htfEs9K-mval(++g7$t6Wl(+*K42e4k1LB;* z!I%ggCjQC9t>{Obxi^NmdP0wJC-itqim5}7*Gf&C&7GMzbN3;RRdgx> zC?^1l5_ggiqr|NoCGKPfL*h=sfHlpqvFLO58a@j1o6CO5C{&hQytR0dY>@d`yHc5&vZ3R`Daw+#5q& zJ)y@_QcN9syjE)BZ0^j&nY#~htfEs9K)Do9l(@@<7$t7iC~;RX7!r3S2E;jqt1uC| zUi_1ZTg{I+b8ifB^@JWzNilWk@mi^gv$-=9XYM}4v5HPb0ObZiQQ~eAVwAYmqr~0J zU`X687!cF9eTW0YT|6}%*2_y4{@xbQxQOU3s97} zsX~krw{DcUX$*$My@LU9PT^flggz4gWa8TWh%@)b5LZv=@st!(haRt$nmC&~GjZnb zLmaEx@LSKo0GI8ts5ohj=A+Da#<0&bo z4n1BgHE}j~X5!4F9eTW0YT|6}%*2_y4{@xbQxQP<6;PD8--Q?@ZbFo}KNt*&`x67= zoI+C{C9XT0I*6O-N1VAghPZk{kEf)VI`nw0)Wq4`nTa!ZAL3X=ry>y715lK>ogA93d17~<*)J)V+c>d@o0QWIx$XC}_veTZWf zor(a;+<>CQ^%G*0xJ{zO&C6g&+yCH-N#AxPcfD=M)BEB9s&VWa2jWBhK6# zLtH(f$5T>F9eTW0YT|6}%*2_y4{@xbQxQN}0#KB=ybz{au^Wj6qd(CXhrc)CT=S~;>^7<#MKjeJSD}{p~q{bCeG&0Oq{v<5XUMy6#!aA4;Z6N;1#BJwCoVhoKxOzg5 zr=*xV^mwh*#M#`Li8FT};#fteB7m|XpeS(@g%~An`zUc6F&GlJF$Tmrg-tLK+Cu!3 ziQB=CICF0darJ~APf0O#=KvCkh7GjjRzeb7MhQW}y zZ80FuDQt&Xa~0k84CMbNgfY(!7;JWCQwNtj`f+LQ|A$-}3^jj?uAb22St_OuJzlFe zmx-Zg=F&p<;gVH!Dgr3G0E%+Cn-HU1?iA&6cLqZ)_rQQlr?4j`Li>q-@|kdFKjO^2 zF~rpqdORh?)S<^~r6$hi&P<%S`w+(}Iu!ww{Q*UZJ5Y#G;&zD=cMyXiaR*~SoKyHa zCPE$JpG@4Ye#Du3V~DFK^ms~&sY8#~N==;2otZdu_aTl|bSeTUhXaZdH(7{L;&zJ? zcO-)$aYtc5oKrX&6QL8tKbg4Q{fIO7#t>Ie=<$>kQ->a}m6|x4J2P?S?n4}_=u`wy zP6QMs?qnfGiQ6Me+$ju(#GQ%(aZcehOoYx7|77C!^drvP8$(<@p~q8FOdWc>R%+sG z?##rQyAN@!qEit-IU7)vxO0UVC2p@Mapy4@5_diZ#5sivFcG>`{F8~>+mASNZwztu zgdR^xF?HziTB(V%xib@I?mon^icUoUDO#9hf?NZeHz5a$%G#zg1_ z@lPghUq9l^y)neq6M8%)#nhq4Yo#X6=FUuiMv^dQR4QC5_b!O zA#t~2K%7&!4HKce#Xp(2{r!kD_r?%cPw4TK6jO&Dua%lOn>#ac=I%ortLRh&Q0@T~ zCGK7!Mu|HhO5A-6hQ!^E0dY=Y3MN7ii+?h42l^3b?u{X?p3vhdDW(oRUMn?mHg{&? z%-x4LR?(>lpgaO7O59^Yj1qTHl(@$k42gRJ1LB;*lb8rSC;rLA9qdP(xi^NmdP0w< zq?kJNc&*gL+1#0lGj|{2SVgBIfbu+`C~+?eF-qLuqr|<$U`X7{7!cVnCcz_zn}HpT$3!xFh_CGxx?2S5N5iloV5k z9w67 znR{c1t0(k$N{XpNkJm~~oXwq?ICJ+Qj#YFj0w~=9MTwhDh*9E>iW1k8!H~FK7!cP?WfNgcv36 zm?&}m7z~M<7X#v)!hD!DSJBPSK>k=EjCmHoV6zCDI=DQ}k4tlJ443tU9?w!Sb?EV0 zskyYdGjnO~K3uYjPDKD^Q9w~H2M96B_c=8zRIgaVJKJTZ+MuxS<#j=M)N< z2#pZ`Wa3WpBhK6#LtH(f$5T>F9eTW0YT|6}%*2_y4{@xbQxQNJ2`Eb3vO)apv9_;_3-Ko|0nf(BrjI6K8X0 zCeGY_h+`F6ofRc+TLweo zw!?rpr?5RHLOY3nGI3}75ohj=A+Da#<0&bo4n1BgHE}j~X5!4d@o0QWIx$XC}_veTZWfor(ZT2cRf%M+h-W+yznMCNmfkcO(YHIfbJz5jtM{lZm^~ zk2rI03~}{@9#2Uzb?EV0sfn|>GZSa-KE$z#PDKFa1VB;ZP7-32xQn91oy=fJ+$k6k z=M+xGMChO5pG@4ve#Du3V~DFK^ms~&sY8#~N==;2otZdu_aTl|bSeTUX90>5ca9LF z#9b04?py{#;?Bc>IHzzvCPJ5pe=>2G`VnXDjUld{(Bmm7rVc$`D>ZR8cV^k+~q=y5_egYxGNY8iMtX5;+(=&mj8$?nj)tH-@-+LXW4Um^$=$ zt<=QX+?k0pcOT+dMW-Twas!|!aW@GuO57Du;%;UzB<>arh;s_JVj^^x_$L#0r5|zT z-WcNQ2|b>YV(QT2wNevjb7v;b+!Zzmk-@OJFJaJJr|>c+La&K`^6BITzqXlsW7=kO zXKtIh`?QVqTq;7fU#HsIwl}2g+O`{`ZF`f!ux)Q)&^D*=HYP&vh<|e1Zt`oJxi_Y5 zHh1Q>nY&NhSQMoqRQp}3t!;Z>%C2p@Ioh@l7!2F?AqH)83Ljx2G+q3Y+jfgz+swT& zZL_&Ex6Ryr+Q!Nv6`|UnQf+P9=TdfU+pW>IeZgSZw*O$zHmC4kOoV2Le{$Py^J|;A zH>PbicjmU4yHDF#o}(gE`)jJLZTnWru5G(L+P3c)4BPfS25oZ+KVTyCv-l^s?GC@T znR{c}W^-q5o4Nb6jWsSRLbZRP+S<0?r0m+ZJELv;ox!kee_+ryr|>5xLS1IBt8I7r zwawfc(>9wsbKA__r)?}0Q4y-$m1=9-x=Y!$ZFfi8)`P*YZL?v}HmA@N6QMrhpZsdO z$FFVX-k7%8+?m^E?mlf}wS|gM?Y>l7+ct-kUE5ZUwrx%Z!?w+ZLED_d+?WW>EB?uC zyVtL6=H8gL+1#1iX6`<1W66SwQ0@7swzh2nDZ94qzG&O}GZ?mQK@8gF6c)lnXi@P` zZrlBSZ8P`Aw9V$u+%|LfX&c}Bs|eLzjB0D!21?nrZBwFc8^mDPwiXQ9<`h~n5z2{w za@!v8Yn!<@rfoKN=C+x;PuuwNTt%q%5>#8;mY1??+x``8+YkoBwk?H0+nmBsOoWye z|Kzqk=+`!LZ%o^4?#yj7cb~TL4YZ0-?O{|~+crYVu5EiL+P0AlhHYC0gSI(^Wib&d zihpw39`nY&Nh_!?J5sP+m}TiZ5T%C2pDB-*wW84TN2!k}$VVI@q2 z#)^M(+aC36o4GfpZ8mr2wwb$6+xRY2MX2^FR9oA&nv`AJ_E@xSt1}q3tqp^=IfXSa z5n5aPliT*VU)#*RF>SNCGq=s$ecHwsiYh|2$5Cx<+d5KqZQB#kwyn!x*tT{I+U6A2 z!$fF9@lS5slYVV8_r|o%=FZ$UbN6W*-^!^7)t*4LwQUlfI6Z342!DeeVbu{-Gzvh~IW13q}=<(n17E^~FuT}fo;#qv5Xme-g z(%gNxEu~I;>^7<#MKje zJSD}{p~q{bCeG&0Oq{v<5XX0+Dgr3G0*Vs1yAY$q)%Y%S4+cZx_QZfVr?3|$Li>w< zGI7uO5ohj=A+Da#<0&bo4n1BgHE}j~X5!4d@o0QWIx$XC}_veTd^5XcYmJBLGE- zJ5q>I;%a;YeH4QsaYti7oKrXk6QL8uKbg1}{D?F6#t>Ie=<$>kQ->a}m6|x4J2P?S z?n4}3o~sC;oCGLJ+$lng5?ABP^HUiNi8~Dg;+(?imj9>=trEnH-@-+LXW4U zm^$=$t<=QX+?k0pcOT;T-d{xkJC-itqim5}7*Gf&C&7GMzbN3;R)fOrOC^rF$5_gLb zqr}x%ZE-7uA#t~1K%7&!9TTB@#6Ow1SNw=G_r?%cPw4TK6jO&Dua%lOn>#ac=I%or z3q@1}P|AR!#N8*vC~-9wirmj&NZb?*h;s@LU?TL0_$L$hsvmLY-WcNQ2|b>YV(QT2 zwNevjb7v;b+wd(Udt->JC-itqim5}7*Gf&C&7GMzbN3;Rl|?E7C~pCZ5;s+dQQ~T> zESkn(NZdOZ5a$%$#YE^M@lPi1-+siIdt->JC-itqim5}7*Gf&C&7GMzbN3;RMNujO zC?5lg5;t9lQQ~SWiu#nnkhsqJC-itqim5}7*Gf&C z&7GMzbN3;R^;{|fC^G;>iTg%~QQ~T>=lYhxkht$KAkHa#kBQJP;-5_1n|{QZdt->J zC-itqim5}7*Gf&C&7GMzbN3;RrD!SwD8B-V68F0hqr}x%iuMPCA#s0VK%7%(nnQ`} z&ZZ9H-tr^P+#5q&J)y@_QcN9syjE)BZ0^j&nY#~htfEs9i0c6;N?cDNMv1Gjimn%f zA#uGiAkHcD!K}H8t}g@mw}mj~nH_`8Tx{y#a;hJf=H3`CZSKs?HFuxpvJ_24sP^1c zTbtWY%C60wMrDT{F`2)^9&zmCDFerG)VvIa&7BW}<~oJ>F*#&G@lSpOd&jSB=H8gL z+1#1iX6`<1V?CFOQ0;}Nwzh2%DZ94q-DukuWiV{pVi>f|DGb0ws73sf+xDJc+swT& zZL_&Ex6Ryr+Qy1E6a_3G3MjJ4W+Tyn2#70+(h&hsL2M{e0!D!#35w-vC?dr|QBkp=6cG_Sii%yY zii#Br7VKRCu_E$)&pdmEP4;=7Jtg5oO#dt%)IC9X0sb8Kl9kW3^q2E zo}IC&+P=r8(u0f*Z_i;6bo)?ro5yw-wVlWIRr=Tx2+G(Fhl8;>2p!=9s1xO99^2Q! z#-`G z&?%Ikd2Bxh8=Fec&e&9K-(yqhLB@u+EHDVVeJZ-mV>_MN&SU#2eQbjfl(C%w2V-*( z&V&n~p_HF_Y(EDZn@Z2l*i>!bV^irt#)jYfGYGmp4Bh6jji9#k*nUYLTM2?Pwvli! zHV0u8TmYRz`I*PIDcIOldUnR9YWp6WN)IwN{PLVZ(Cu^4Z64bgYCDf@bNblEA}C`k zgM+a-2;<-asGRaMk8Mk^v8nXzj7`<{JvNmdWNi2iG=req73emP?R;uGkL}m=v0Z?m zjBO$ujLku~5H5f&q5RBa+Zt?aDm^=6Q?-4MO{E7J8-9(;An5jg&}|;uWz=>a+i&S( zt3*)7HVF>K<{(Ul3!uv>Kl9jr4>mTHo}IC&+P=r8(u0f*zYAp$bbA`Q&10KRZRfH5 zkv_H=2+G)I!ok=agjsL_bT#E?9^0S6#-`G^5ENbB1qZrx5SGIQ z(7lwO`F8SeFvY3#>?qC+b+bwmo~fI$JS$Gs_N_RT9z=2YT_}SSip@ic__HD^8^cQ5=4a z%ODWS;}8lfZVf4h6{q<%?vn_L;+}#7#W@I1!v)X_l%H8~p}X-|T)6F&HIo~*303~v z5Kif-YoX!uq+&!KINYLljuudeBBoBn^5W5QJfp9@5!ZUR@1VZ@+LSe;yM~Y#^Y2LE%J%XaRAK*Z74#JOc0koO&Gb=7PnBr7=b`+R&&(zIWo)xER`&OJv5284{+k!zLlr0bnD{d<(h83rIx5aM=isF8U1I0NAf4~LM zKa`(YakYXePNio@ac-!aRg&;b-Hhc~ajLd&#i{flio+X47z9Gu4xzB(c93FNahf-Z zgmzC+To?`%=O9Gj0;mqYxlml~V2V@e*-@Mu>SmQBJX1Ggc~+dN?OSmwJ&5A)9v23I zQ0hV`thilCF|0VvdtB-vDEGMfaG*E`p#fX~HKhE^_qaO26sOX&qc}Iz%_>QFrf$aa ztT0vABdDL=E~>IPGs zO3#ks+)y{GB;lF58OyWcRBhjiQ|Unzhj$h+2!ygfgu;r8l44kKns*lEAt;K=hXchq z2r;+-YDxK-6}L+;#i{h{D9#Oavq}=4shhDpD^At+tvHn)L~(di6oWu0MGy)r?jTYO zD^ByKsA2>~ajoD$aSlRjxBzNL`I!~BYcR#B^z10k4Ry0h5}v7>u{!r^cMbQI-hR$RScic{&?QJfpZ(zByDH`L84NqDAi#`3H18-Gb>-rDsQ%s&<`I*Wld=|r2Dm^>XQMCh3$IbPte~3%_ZWPbgZ^rU`>*3m%^jVlR3u_pS+$5~w z2#T;qz=5zFgc7(~VU0wfs9{oAqu`)iDZaT7RwEXceLCj1`6PG84M@fXbOT}@ODYpw z{W-XLZuV$u12=mwTxqo}9)qAXdn_C@n`r={46e4>;}9rnoNV@aaB%W?e9P2qyt8I+ zZnphV$lUB?y8Thekp4ofZ@cM}8sR;&%mI|kL76)=fw*&rZoD(CL+2wX9l8JxI^-Zs zgsbh)g$NYwlkCt%a8T}Id~?yECc!$S(gSvgK|uKuQ05L@O5C|a3(`Au8G_QGN;v3{ zgD?rMwnLKUkL_-1JC7}vKDHGI%GmCKgRwaXE8zm@KFZHLwt||_y#n#wK$RY_feeD{ zz8}}k4SbLqzzvM2H}D|@rGXE_K?5CxRd4~cn({L@urQeJReE-GuWI`qn@SHdHvFi; zAn5jE=r)h-32Hl!?SS;LtwB)6_9PsP%|UnyE`Xk){LEu(SrfWfAif)@(gQY-L2%vA z;<~wk&r<`qfko*Jd;vje;EQn3KnLN!Z~^oR>)>E)4#FF70rVE-XC7N|P3T^M_->#|57*fZ&OAX)#wn}f{dIY6`@4-O>9fbGc0%!x}XKrBYV7gc7+0nhK?R#u0J;>Pbfd&Ra zw?9I+d2F9h+j(pUr;qJZ1Z8X+;b3eI!e?*+^abT-9$TB5(7gij-9VKduz?JM>;4kg z%?Oy#n#wK$RY_feeD{{teg7 z4g7-|zzsY!y@7usC=L7z4jSkn{0$dC+bKVD13LuMy-LrH?p1ByV^irt#)g-H83f(_ z7v1Kuh4yg9c3Aq@!U)RPB5*J^2O$S8fND{G=CLJeLiY;9cLP;=zy>l1uDdp_n;Te{ z8o;_gJiURtASeyo6%HEcAk>2kpxr1xa|1gD)4fX1j_y@$-(yqhLB@uUm@o*sy*s+i zW80J3&SN_weQXU8l(98}gRwaXd%*?J-jtttY)96F?iGmd2CDRc4P+2p_dd98ZeUYt z05`BxdIOswC=J{f4jSkn><1S>Ehs;81CI)(dzGFY-K*NZ$EMPQj13=jVGwjXif;4R z@~Q1SwxiR>7DG_RRsaWMa}eTi0dxT6XC7PUn$W!h@!dd`9*fX?NDbfy zc1dsGK?q6%i{YSw4nixq0BS?|nH$(OnC?}2c66_5`yQK04>C4<+=fBW?L*LQ9$PzV zJCChf`q1m$NQTlbpKy#n#wK$RY_feeD{J{;H04LpJxzzyt? z-oPUflm>Q!g9bVXN5KV97s}7vz@EW$uhO%ldsW-_*i?FuvEf5M41#WVMYnlu-Kp(7 zwqEID>w%z*ttT9e%|Yk|7eKu!Kl9j*sR`XH5Z?_{=>Z$aAh_;haoya&zSID2VDIz> z_Crt_cpMxw&_U=A7eFUce&z-q8%*~qJv+KrwSA9Gr3V=sK6=C;==K0~o5yw%wVlV- zCw**#5R|c<3h zrGew%pn(p;d2j(#LHU^*cw#W!tMu&XUe)$JHkBS^Z1@-!gP_|J&}|;u1=MyP+ko`3 zO+-+}b|D;$%|W;bE`Tnf{LEt;SQENeAif)@(gQY-L2%vw!F6*3FQW!<15ZkCU?qam zz)5h>KnGzmTmW58`I#FyD46b5dUkZLYWp6WN)IwNd>D*D(CumHHjiyOwVlUya{Ab2 zASh#-2?t|y5N5#z&{dS5d2FZDgzgoH?*^*$fDL32T=&(uZf@XgY5+Iz)bs|=C*hg88O!rW ztyFE_x>V^wbcxT`FbIUQ077A1-a?9DUGAH%%Ucl?UET%1jBE);#HcN>-NVQhvEnc?q#dmft`>SmQBJX1Gg`K0b!af*5n#o=Qe3<9Ct z2cfXy9w5cA;xr%Yco0ER+(U4nI0xZjxByyB`I!}WW=-5}6o~J;jY{_*+Zvp`s_lFB zDm~!r83ZGH3?t*&KS8tO*=s(LvIaq!{gZGodk5huxBz;d@-xqVNU*z&O7}3f8ob-M zp>9@5!ZURTs_k2GDm{qe@L?JTflyw6P*`#QCB?AfG#{pU2|-cZ%W$AL2jLaC z0D7JBGb`?_nz-925Z`wjmF_{dH8^`!+xP5MdcfH;2u8LJBjee>NweeGYd#0`7J@SS zx8Y#+4#GQd0rUaoXP*7gV0Rmp?qO^-c(-vw-K>&?XX<7w&vzSD+qdFWdJx6oBTNhe zp?nCTu;M-<#jxTuA7T0!K~dZ%aG*E`;ZwK(`hxN^D{fd#+-($y@4Jmk_aNIEoV}{; zd-f_l;OrR$Bl{8~-NVQe*c zw{b(=tdfLh>Sip@cN=i`)xEkp1tNXZ~q`D zv)>K}vv&~wg$tk@`~zt&W?vHQZllsYjI9RmHg2e!Rg&;b-Hhe=Zlh}ZR-8%?qBwk9 zk3k@mTnL2~SDO^Wiqm{tuMUEuxVmtlI0s=DxBzNE`I+xFBWvPrqdZ=^kWTgR@t)ea~K{2b?{FU}Q0jjAtLG+41Z(pYJS0 zP-cGs9L(N9XbBfUttdb9>`Q~)ZB)94vDM(+#tn6|N)n!_o3T9KZB%XFic{%96o-$d zG6;my8bV>kwIRi@;xr#kJp@5fTw6F$oP*E~E`ScB{LG3wrzY+;3dHx_Mx}d@Z4J&| z)%HDml^$^R41$p*FfyKfN17eaUh}EiBM_9?9|;GucMv+k1yEPY&pi8cgWYXZx`(mV z;N8Xzb+bwmo~fI$Jl}0pZQqJh=|L2S4+Jv^gwhQ{Va4?z#jxUzfGDc{LC>BDisE{~ zf#Mv5W8ea)FXd-e+~}IP+b9s-NLAEtGdsW-_>{WWe*)s@6)(<1&+4rZ}@$5UL z&;ED>W%eh)!R#G`6X62rWXjJx`!T`pHY(l2*lO@@_2weF=gx`;l-kdk0|@TmX%x{LHg23wF0r z=^n;bgLfM@)XgeMc&2W~@_e^ZwS6m2r3X{V^wvsdW>XU`xQ*_9X>&;Dwf9nZdZ`s}YkP-Z_H4rcEl%z+D_>nT6;?8}4Q zZB)94vDM(+#tn6|N)n!_o3T9KZB%XFic{%96o)_bz#tIHd>Y%qZ~=5TO@2!yf%LSeccYAQ;&yjErahD9w&%e?t1~S0gC1e+&+0?;t!57eG%_e&*R< z5bSQF(mjl=2Jbd*sGC)i@J!u|<@s)-YWr54N)Mtq{81AIfl!`-P*`!#kz!bJ1JV`u zJc6RQ7vMl~4#JCY0rU#xXI9+Anz-925Z`wjmF_{dH8^`!+xP5MdcfH;2u8LRBjee> zMziDDpOilP*AbN2uY-fxI|y&U1<<>cpLzBd2D{s+bPr>z!Mlwc>SmQBJX1GgdA{4I z+P)R1(t{`te@ccyAe8kG3M=k?QVc8Z4*T3j}5MU&6uc9fYsoYX1t( z*9a6{OtVIvZ{XnD5BTOnA(sSJNVgUV1>##FD*b<`kQ};ctX{q>9GX65RqUkcQ{K$) zi?8qH_jN_x@GsWlZ)qgcJy17e>2GYAsAJMUV$v+EpK0VQtpB77>lXw?SexKLSloCZ zY=)~9))oYcE=>ySS2#HN4}5bWtjlUbSPI0quvEH->3F^MSf=BKx>*bf&(zIWo`uD= zG3h@sX%^PsG;$VJWxBAoAt=K72M&bgAZ&-L71qB96irGBYX=;Z%W3FJSd(i)SPI0q zuvGg0P*}CicPuy5&0+#wRc0^EQW+<>Sipxurg7{q+4Rr zEUW`*xh&wH2k*(pPlEUG&x7;>ol5sW-HfHDt}a#k0PKdkS%TiF zo3ZrNGj`qnLW@ebblv_!iy{4mSl@QjCpE$!TIBXY~iKOD_avS&o5&WpNOC!v)asl%IK7 z<_239mF_`tHMlHpsG9|z@J!u|rB|F~S=>-J3*0+(GnSsZWmyz;-^-%XgDeYveZwHo z_zBQBFUtTDJ1@(;^ko@{pe)NtaIh>6!XUT+I)m~vFUz&TmPMs!XIb1(Hw!%BnYtNE zuQSipx;w;PJhPqkc-l?0h^wcfOqNw{` z7L^`kS@3}l27$)Ug~oYV#*o-~S>~rN%UA?uS<2vGSsa9MZ~=4yXv0u)O|0DN)NIu_(7XNpz(>&I4{dZBz9hw z8`GENVgzMbE`ft(aS;9k7eG@fKl8HO6l_^kdUlq@4Ry1?6P~G?vGj_wEQ=fJW`TRB zZpPA6w=9dI?t58OdXQzopLk*rX#8?$oR{Sa5<4%;g7jsXj-V{d3^-U82Vo{$0L`KN z%*%3fuw_x{*;y7h)Xf4y<&E z@ww1AFUz$gc3zfS(wF5r1Z7#Shl6Et5az=L(5;l8d0B1^wk#?=JImsRx>?`}&(zIW zdc|3m#SL|{z`av9W9g||mPJwby(}s{$gC18lg0d`& z;9yxCgvD?HbT{Q^UY3QymPMs!XIb1(Hw!%BnYtNEuQqw&rf$a4E6%bkZm63D?wz_BOHbXhEQ-4CWl`xtmIeR72ZKQ4tD$jTmd8o# zyex~-m*oirWm(q1!Lm3APr?Pz3zVOESr!Ld7L}fzWpP8@EbxS9>Sipx;w;PJhPqkc z-l?0h^wcfOqNw{`7L^`kS@0L*83Y=C5gO-Zd5Of%%d#YWSzbm^mgN;VSQZCiEnEP- zMfsVRWofWwQR&%P7B|$*0#A6RZpP9p&ay0SsG9}uow^xIPu;RCin{M*QRzXJ1%HB= zL7?%sp>bZ8cS-ELEO(|a%X$Q5S>A(#WpNPRhYO%jDL?bFEDN?QDm^>P;)c3e;0e#v z%~*QHS(e2Ob+f>|Q#WJjsauvsQTM$pDm}=u;BQ(o2sFMC8s}yCoW#z{a##AYe1V`W z%a?GlEDpj~Z~^oqSioGb<46S z>b{pnr3YCS{E;*UfyRG=#(7zOA+hta+?~EGn-G*`*$fBE;vj5+3!uL!Kl8Gz2(~OL zJv+f)P=mAW_BN~!e!;YwLP zr{;#bc?}YtshhF%y0om68|vmY@J`)~rKg^;>%Lb?U3rj|!lzys1RCE38t0X&M`Gud zx-WgD>LVyC)c_7w%0bu-E`SXv0u)O|0DN)NIu_|yx7K;wHuEgDs0n&(5;Ap>7sQ#WJj z6=zu%H`L7n_fFl6rKfIL7De6nvZ(YR%Ysk6FbFi>1{&vOX-i_~Wm%QJEbS1KWoZuw z%i9r*2smMcwzZ zsPrJqf=|6L2sGXa8s}v>n#9h_@@V?9bVg8?r3)M^i-XV=E`WMde&%Ia9c)=tdUlq@ z4Ry1?6P~G?vGj_wEQ=fJW`TRBZpPA6w=9dI?t58OdXQzor(PHY8b1~q=Vj?jV&`Rf zEPYw}At=jo92_i*gU}x?fCf>1=4E+2*s`ef>@15L>Slo_JX1Gg=@n;L7B|$*0{2ec zjHRb;Sr$dz_p+$;Aj^VJy)Xzgelj%9%W^7-otNc_^kq2>L0Oj5;b2)Dgu!qDG@SA? zFUy)>%c9b=vn+0?n+2ZmOx=v7SDa;8+)y_Q+>MmY%w0Srm2O%c9bQEDJvM!XVK2 z2xy#_Wh9B6m*vUyWf_H_EX&z&uq+NjDO>=Jqx{Uv@>H;8QR&%P7B|$*0#A6RZpP9p z&ay0SsG9}uow^xIPu;RCin{M*QRzXJ1)q9h5NP~7Xq=a&oW#z{@^t#LR3IqJG64>j z#X&e9E`a_+`I(pHnPAJJ(zCNHZm63Dp72cFjHOqcWm()%Hw)Z5bu*Tpx@B1ub>GXP z(t|7uKJ~&N(DU+>$wER*42Ssa8ZZ~-)v@-r{XbHSEHrDtbZ z+)y_QJmHzT8B4D?%d)tkZWg$A>SioGb<46S>b{pnr3YCSeCmZkpz&GII4{dpBz9hw z=hK(vY6RtxDgHpH`L7nPk5$o#?mX!vMg?>n+5Kj zx*1DP-Lfo-y6WEOo3ZrNEz6>)`(7569%NbYsTT%; z#+N|jyexN;*m+rAN?(>`2+FeD1qaLGAS{Oqp!+F5^Rm1gY*|!#c9z8rb+f<|o~fI$ z^op}AiyP`@fqSQJ#?n)_EQ_MOrJ)Xi9W#aWic4Ry1?y;C=1>8V?mMN#*?EGj+7vfxuM3<8b63XSu!yiQ{0 zWqCb)S=J#a%kl;sEQ^EiCS2{OUfx2WXdNvF>bwmH-#)}Q7c2Efu$5Bj|HGA1I@bP! zDQ>8n*C64Ux*1EaOUp{Rp>AFS@6^p$dg>Xw?t7)wl?PcVeCmZkpz#gRIIq;lBz9h@ zH`7<@69i?YK81soau7Dc1<*H?pZW3UtzgTd(zCNHZm63Dp72cFjHOqcWm()%Hw)Z5 zbu*Tpx@B1ub>GXP(t|7uKJ~&N(D=8|I4{fhBz9hwx6_y92LxqVeuRT%aS(oj3!tr( zpLto{3AQXMJv+)D-7N5gXX<7w zz2Yp(;)c3e;NGd5vGmj}%c7|JUKW)eWLfa37Y2dGBhWZ6OD>6>m*u_mWvPXrEK6-T zSQZDN4qO23M){c^S>6w}EGj)a%i@N*S>OrJ)Xi9W#aWic4Ry1?y;C=1>8V?mMN#*? zEGj+7vfxuM3<8bs4vq7&>`7whW%(d|SsEfJ%hCuAmc>EX3od~6rTomx@?o%LQR&%P z7B|$*0#A6RZpP9p&ay0SsG9}uow^xIPu;RCin{M*QRzXJ1)q9h5NLcqXq=a2e-b+{ z%ZBu2X@Q_DOB4>4#X-n}3!s*ipLtn63brgNJv+)D-7N5gXX<7wz2Yp(;)c3e;NGd5vGmj}%c7|JUKW)eWLfa37Y2dG zJ3!;SEC~`jFUzOt%W^n^vMe3pU|Af5Bj5t4E9GZimW{!dMWttFS=>-J3q0YOx*1Ea zILorQp>7tqcj{&=J$1{nDC)kKMWqK>7JTZ3L7?$&&^Rwk4-z{s%V+7!(i1^hmR@kM zEDpjkZ~@ex@-r{X=fRdmrDtbZ+)y_QJmHzT8B4D?%d)tkZWg$A>SioGb<46S>b{pn zr3YCSeCmZkpz-6OabA`aN$k8VU!*U~00d=O2ExIzI0z@f1<+v1&%7*O23r=Do}FcJ zL)|R!glFnzEWP3^%i@N*S>WEOo3ZrNEz6>)`(7569%NbYsTT%;#?OGpd0B>#*m+sL zN?(?<5R_#Z3J1&LAPj>Gpi;`uyewY_TNag`on>)D-7N5gXX<7wz2Yp(;)c3e;NGd5 zvGmj}%c7|JUKW)eWLfa37Y2dG&w<8ySw@rCd0DSipx;w;PJhPqkc-l?0h^wcfOqNw{`7L^`kS@5YB27$&e zfW~=QE+nz@vV51mEEgdt%W^RsEQ^D130we8q5RCt@_n#nQR&%P7B|$*0#A6RZpP9p z&ay0SsG9}uow^xIPu;RCin{M*QRzXJ1)q9h5NLcVG|tO1jl|B&@DgHpH`L7nPk5$o#?mX!vMg?>n+5Kjx*1DP-Lfo-y67s(a7Ps&?XX<7w&x%vEeJf6-2T>e8 z#K0gB$}I2c#HQ+~4Vn`w&4< z+y*#MoP+QYTmXGW`I!~BEtuj|dUh1&hPqiL3D4BcSe_N9YWr54N)MtqyeFMOAe7G` z6jt1qq!?D*Kk1753PDla*KnXX2jLsI0Q!;gGb?U;FvY3#>?qC+b+bwmo~fI$JS$Gs z_N_RT9z=0?V>g39C_h0cthirDF|4?M(-pS~K~dahI8dB}umvuF{-FHKirW!PaVkAK zigQEVtdfLh>Sip@ic__HD^8^cQ5@bK%^(oUpAZTw?r%~ID=xGm94ekXWmEl7+v!u* zMEl^ZZ3v3u{(%F~ZSBeV*JXE;tlr@tZwh2|zKlWT$dg_|#Q(lOLDqr6d zum4T!QlVa0TCgk}nm*;8{FCTQUwqvb@0(ER*-@Mu>SmRAr*6jbtT;v8x8hWK5XIpw z#tZ_X?qC+b+bwmo~fI$JS$Gs_N_RT9z=0?vnzu@C`}<0R@}a%7*<^Ebj9t5peU|6 z94O8~*dH!{Vw9g*admg9F7m2<_nl=y1xQFrf$aatT9@5!ZUR18hQV~H z(zByWH`L8qN_eJj#`3I7H`L8)D-7N5gXX<7wz2YoyIdwzb zEO77C%~*QsmSs`YeJ_hj53($H?;?Xh8|r3(d#7&3(o?rAi=ys(SyXzEWx?An z83Y=?5E|!YxtPSx%c6PPE16fS@+r~J&z(m2?%sPybCiyP`@fhRmu zH)H7)XIU0E)Xf6-PTh>9r*2smMcwzZsPrJqf_IEE2sAzo8s}x1PGaX}(Y#}H27?}f zshhF%)Gf=RsQX?Pl^$eS@D^hRfyVEF#(7!pC9(6eXx?IcAA+(h_rt-mI0z5G1<-2B z&%7*6gDs0n&(5;Ap>7s6!c%Yo^djYFUY2ITmPMs!XIb1(Hw!%BnYtNE zuQq+dqESmSEzlWeK%lmM!EDpj4Z~?TD@-r{Xe!-SSrDtbZ z+)y_QJmHzT8B4D?%d)tkZWg$A>SioGb<46S>b{pnr3YCSyq%swpz+V3abA`$NbI~U znzz$`iJ&aYS8%W_4#L-P0rV5)XI_@(!Inj(XJ=X5P&W%a;hDM_ORqS~vbdpc7Pxon zW-L8*%d#lyzL!O%2U!+;5`aOV@t>h_UY1QHc3u|ECjmAiD9f@14wl71_!TaI{-*rQ z%d&s4Wl`zbSr#|c%>qw&rf$a4E6%bkZm63D?wz_BOHbXhEQ-4CWl`xtmIWVTU=V10 z8#K<#vYo`v%cA)Z!@mg1vh09^WpNNfd-Jl?!8aGn(jwThsPybCiyP`@fhRmuH)H7) zXIU0E)Xf6-PTh>9r*2smMcwzZsPrJqg3n(t2$rQTG|tPiD~X+#Mf3TKdI-w0)Q5v* zaS$571<+oUpZSp`8f;lqdUlq@4Ry1?6P~G?vGj_wEQ=fJW`TRBZpPA6w=9dI?t58O zdXQzoM@JY08gC4Z^RnziV&`Sid~~DQ#WJj6=zu%H`L7n_fFl6rKfIL7De6nvZ(YR%Ysk6FbFiB4~_G(6p+|?Su~$| zi6bb>QV0jj;vgIVSNo}#mULc@q`i`h0{7rg%N#ka>x2*So&Vy@v7I(JW}i;~IOYkR zn%|W?;lxfyIp!IihB)S#ohlu3OsCr&b8M$)9kcTBP$<;t3vr(yH+OjwwDKu(&cxi?y&&rbeFh&$bCiJ)5+Z+?qG8N5%(N&8_?f=qCdA&c`mtohp*<2v(F&S5oCDz$E{0RM;xznKBK!@c z%9VSBLaRxV^v96!XNcBB`{M5+ZK_Xy7wI56eFbRus@D_~ZM71Li!qHBt_I6OuV0Qx9ich0A1 z5ud|Qty7`+k1n-EExM+I>6(Z@3N0LNgToz}3Yt_4JkFDN`%r*lNlWF}+78azBp%W|f$T zsh~yTK;p`$9Z75nf`NBum7-UjjM+O{B#I^bD1G+Pba)v+^#sB>ZP9cRL}z_|7dm{G zi~O#1;*B^_4K=dAv z&Z-qiZNIcQoTHsLV*|AZm8#wGATG6Y7Couh241MnmAP~+Y2YVK3sn@hMxJRgdNFhn zL!;6$@49vyh-gG#ph_?^!v2f)U*M&3?>Uam5MO)K{PK^u<7pVgcdkqW? ztlWYB`nRaeZL+Ykf3))7Q2%xfMmF59Zce=NK0J(tb{pILE!y~;+^9?G6RWeVMI zrqo|eFm$VdH#fGL@OJ)vIk|6-0@!K-BbY=d7-|nnsmKwU*vS| zd0_%M#Y_VJruuwiqet8YIQ2-xDDPdwfir?*tMs1V({yVJUiCX$DtM&ZrQt#2v*JRjZ1ib-$|w>43vkDZTXW01L;GWoKP zhC#C(n|gHTqePJtFQa#`{?RCxt@lva@UtZM6t_&5SOYU_9&rOQDBprHYQq(o+RFKmx=}aJ}d(t_doE}N% z0&;pLor&c1N;((95fU`5%4iNrHxxPmEsD39K4n!t9X{)TX;U`G+f3`SB$haaa+&4D zY1w=1%>F1J*$;7cZfiwJ=tem%gUXEhuCtoc3ISsD#^9ndceUmMmPENn1GlQJt zlFm$W`X`-PYq-Fb=fl1S~s?T6{uyWpJFbBmj1HM?y zU@lyl!8|xc1ClMgmYjh}=Q?suN;=n*GbriIhvT)=CsQtW`o^^En(TB=^-kXutem$_ zFF-MLnlBcez8S7``W84vrzBf=D>;#*2cL z^VVG4->A8Kv1slRxYFFEaEb;eTX-iqXCxhZBImWAXG%ZmRfVeAHQCQJvC|Ja7&7~G;-@fV zp3sROJjpz<6F+p4c}6FGT0`cUo%l%&nPWQfQyMbIcH$>AWU7~(_#uN`e#wa+G}z^r zocLjb-KX*NqZ2=Hu*)ww@k0l@>nX|)9_${A>*~ZeLU#L*%eO*y`6Va58M4bSIq~g~ zU4EU2pJ=hmuM_c8Eq3|U9A12O`PCd=eRlcP9A18Q`PCd2GQ0e04ojI{&7s~GInPG! zhqL<9)22^-C{I0?eu!Snah}}cIn)&O?EC?oht~*?qG1;8e9HeI+`=hX74^re|H2=u zw*Cxp_*qFcJVc4>=*b4Z^g(Z5Qm;*-6oTJUrw5wV3o1#`D^j_<8LU|9>Z4 z7o@iqucldnICyW$qbL7sg7H?pYKLBh55*Tkd=iNG>7VBb_bGBodL=aA{yU|Y6Q0+k zMJOC@5N;5u6S=m@kpAN;O3TKU52z>`KXg<{XnG`6H#Zc!u1TnNPWXnDQ*Sh#dJ~^I zps7L)hmUU>8q#I_sJ^A;6`|=lp`6^hp>U{jT|)T})?bSy#xD#n)#9g~u^CqfM(AbGk}KE+abkQsiU6@H|^54XS%Ma*zvL(G-W zuvQ)`mCv1ES}Kn)!w<8S8;sWLxxnkeuSEb!%4j7frVsRiQ_ z#0(TKvcg{>@KY`DldTxD1>-6+jaep$aCinn25pBUa}d-#0?ox?%N==vP`bff_j+61 zoAq^XvDdvz>Mq5JhKVdj$gt*jAY^RCas)N4xEqHpt$0W%-EXdYudVLG`ns#^b)S~H zYjC2W6^|pNZ3R6TKclbvtiA5bQujq0_$zwwwRZ4#1^g|XXt=01Y<1V`>%M2N`-#-u zU<3bD55Cb3UbwIGv?;c46)9DD+{#1DaKSAQ(oQiPZjMmb2_r|AjPF)9VJu$jh&Zp1 zzS+aP8j-5MbS>0*TX4V|cG zd?13hD{3im%@uV(&~!yz<%*8RS*9!MgqVT$5eOM+AC91n_F)oFqm6D47H+5EJQKH5 z5KH5h!*d=a@YT8+3x@|vET!~$cma(cL`$XgNK5Gvh#3Yw452hu>Xo*$q;fS@l}epw zN<4*`qt0^>G|jR?NS}wZO#LcD%)o4nRMs;)SK?{RFs?~b{!&Z%OAs^k>>`8=%qB`@ zJ+t#Au46V!m`%rdrp8P|%)o3aLI!4&t(C8p%5yB0uQ9`4WrbfT@V8jt7ntF16nK4K z=Sy7I*L$S=a!dJTh#C626d^-j7fWS5vpXc7#w;9JiJ)mq9u?9L<1CXH9z@K*?0%`N zXLhf|)0kmPUXb$7TFO6-n4xD+B4l9pgjCiudrabK%)*fu5j6Ge4I%v+&NB6EEn)^{ zFH2=Tv;RswjTw6Ofs|iwDgO>)hMv8Jkd_%eTgu_TLM}Hx`Vq z5Hqm2~UW_YmQCK!L>JOjhuO%UPmR)o}3fV9bmBmW>+ojhLu z-HyX4BCG!T@2>kfPaW&*XQWgMA??V+;T(i)&q~4)*HEs9poVgN9JWwyER-AKL<6rq zY<2h6*WJfnHzswX=DPb!UHx+ICviY2ma6CmP!LI6`T3)z6x%5isuxQKp1)~;Hc|S|#W;%FvV`-v;rx3#*DDVeZ z;NyrHE-a?2tnLwcy2^54?WA%WOXb#P_+l%3XMyizfjK}{>l zaM;p{i9%_Dxo)|w?uGig7uoAhm%5kZL_;g4AY^F8B!p}atd~hVO_Sls3Iuh~*pzbjWuT*K>n1U0_Y@z&sP`(!@8hG6!b@i>hTjCmC47q;h9V<)h5-M_S>J6Zk$B_}+*aF07Ziat~|eK~i~urSb`8 z`2JS-p#p!V1%5DMh6_8*T=^7hVSYX1K6(O_kOAZUlaU z1-{&hF-b5kwP0L=n1SL&R`@FfeyRn2vK3>tU|eOvn1z^u;tVVN^#VW70zb!!ahqV= zY^HIO2_hW60U^VEB^+6ZpyoDsI}TfJgUf}|o#whrY<2I}*Ii++yGH6hh7%1Fc@!bT zEp`<`##TIupr#d1;jpC@FA1d=%ypl$)qPoC_Z55H^-}k3oM>ppn+O?Nu?`_)E8as; z(~9?T*wTv6gwiMGx*yr!$aABvID)UpP5`iCP zfj`TNF;+0nwP2JYW}rCA3Xi`e#~yn{9RP(AQmLuX~TwU5*nCtyqSTwiWbXyi#BHUVGhDQujd{_#=AoNA2Lx3iwkv z(Qr}tYg^`vdQM;Wd3)WpQuier_^W#G*X-bp@|=6X9(h%yRONANH^dAVTpuCr6vN?N z5wg8xR9E6DFU=f-mqADXdm&g|@XlM7_ZQOp;;aJDPLeNpD*zG@==MWl@CV_M9|cjLxoveoMmcE8^jFLY>kkiXT=Dmy{xRJg`ONG zm5;DgKHLm{m=(US!1uPm_d?8YVLi;1yGdpJG`dJ!GmU--nx=8GkRFJ$Ow%|KF+nXJ;T}V0OAx)-yX*;%UsnkrD(=Ju4H^qj8q0XXhYh zV0N}t)-xL^@ib=W*`-qcVoUi85i|7c0)!0ACLm;d3qU!7wtMAy5>KNYj$DSIsiCvv zil*Z%Q$wdAW}rP4AtUX{2-;{@N<57=x_yIiyAJ1>xXnY%z-wadd`;ETtxAwZBeCIjscARKv#WsWtgZK*}n?(MQc-kQFhY#|#t%~5VrBw}t z@~$}1z^g7oHeR(QuHm&Cf|?QTj>8sS&4pJpoM>oe6NC(u_eRJ@c`u1;DDRJ;hH?uW zwopD$C?9|m4ZPw~SHEj9iEDTrgrJ63F%DaJbrfEQ;Y33#4@Jm8xgA2bRvsd84do*c z)KESWhb@$Q3FYoM(ZH*#)YZ4Lv&1#LjzLhvt2Yi?cnuU@C*VW_ul`b3&#RxrHM~wj zP{V5w4qJGgC%neuM8k+jBV?d_4nnpOpDl3>$y#? z=VqK}Abk@;M$$JRXd`{S#5JTBBB&vKI}Te&-z}t<;Y7m_mLjCR9(ta;LSOeDd)MOZaO7wNHLdE5!BqPxU3y!s-j;nfd^ zExb+_UZ>zhLn{X%WS~3{AzLd?l(>fSU<5Uk&%j{|<+Fuy2~ITd8ZLG9tsE+G4X;uJ zHN4KjVGFOPiduwn!a0!_i}uGajB|4StG-8GN`8NtzDII$Ur~PUTK?W391cHGgx_hF zO&CACWI*Xf{6~V54@m0If;=YS6s|My&=L+mict5G@`}>2L+S4fYtvU%JtqZY3O_tG z$Y}uDPvfi}6UU7oa{kcKDSwi)K`z3%;oRp8;aU`Y!4$+RF7GD0vO!&S&PU1bA1A+m zB3*b3D3&g~A>ouOP+fQ(p-f$Pwdy%37^z)YkFyM22 zs4(RPbm+L0Rx$MAl%(6~3`JmPL;0*_DQ7L&d6xWzD@Aif%2{{qJgXYkeJN+%v-7NK zSP!L~b^p$@s$o6KXGL(sdmL7My2a%@0jnP01lPdA>@cyXVDXJH_i3@7Nm?X^hhb~3 z9Dfs-0_rY~(#hF{BahMH0cV$v#9t7W!|G=BB!vc!8J8NU)u0xp_yQu%te>T`w5@(Q zc~(x&Yp~Sa{Pm;-8o;S<9*9gj)UY|IOvdE zM<-|nxjyBrw|AbEI-NR^_Ymk;Hlp2OT}vyDFDoyl2Z_+M+M&v8@ef(#hAMZ%KP>h> z&Y?Z{CZKW1DArDyQAjkIDu+@or3m-9t~%G zpK{hWJI_kJRQx#<3Y=fHlfR@S{!d&*gV?>ws-Rv7;{hBNekcb-)Zt4{K)oJd_*yljzOV9~OXGIL>vx>mX8MCeeL zltT?7q{v!&cY*6IN8cZ{D5+7${D@rjIOji@)+KO4xN&6 zh?7o8Njfe)sjo_^rrJTAL=O?C!BP(qr^BijqGN+$sfUO&V5x_QGm{o+dH`&&$DfH; z+$w02r_#aU{5Kv!S{@Wmp~J&SwQ{ubE_$XMIhi830m~nor>DLA_&);?^~`-HtcLtx zH4E0Bp&UGvT?K0|wyuWNh#AioYpz(=igmqMH;8qUST~Dxt5^%gxp`&|7HgGQkBaq}SdWYKgji3C^^{o8i1n;k&nGRKgr zl<_5_s^ENM!}*nQ=&8%rBu-A`H?e+CT6A5TV28>phE_}{4^5^Og2+N`!r`CkxRxeg z@eYLPcAFE4EJ+GKl9RLub~~ky8D8pKW++riml+Okqd@7{^07mPmdiidf~fjeVE%HV zP9FY!nD(6a2Sp}~NV)waTeb_TQtzp1ZP=j`OGX{X&r0NWkV}XA4@kkB%Pq&`rrzl+ z(B-hy0!@RZ7U&A+Sk83kSgjd+49j0@rgJRkDn5osrktzg*fp@!^38^&mT!(&b783` zXY(8@_gYw-k$atUUhefAMYY=VooMYFoM`Qv94q%0$I7`)tc7CTF4i4lEfQ<7SW93j zR!iB!O(geDSc=s$=e*qIVyzHsrC9fg^+3|1*-U~R>R)XJ;qYa2Sg*6(2DKX0=G)xk zIH?8SzMh5EkY1|Dc@7p&De@95#rkE(%6&zwwT@NmRk2=ktjOz*mAeiWPbv2evECHx zEwSDf>m9M)6>Gg%?}_!kSRaV>p;#Nl`beyg#rj07PsQ3O)@NdUF4h-feJR#gVtp;v zH)4G&)^}okFV+uY{V3K?V*M=EFJf&HYqMBe#QIgNtz!Kq*6(8dA=aOcmGc)Yo^La2oh{sIa+f)`n%c1TCpkyzinUA9qRWWDrk_DdN0wH3 zp@d${2!}%yO<$yciAMTG{==7&{%{kH)Z!}DFOr{H&|_Ldgwh9JImb$y`E7pEuH5Y4tv08`~6)R7ye6eC;6^IoVt5B>1#A+#4kz+*;ghiU6#_kSV z)4B$9IK6fC=&)8FjVPj?3@8~?@PlGo9Cm&NIhan7Dd7Q*9&*CrR&+R7Nz2(@ka;%RW>+2lL=?6>A z^*C5+uKmS2UaS+uI#H|vVht4QB(VmGb+TBeiFLYIXTVYn&Xi+A#5zl?p<)det3<3( zVwH+@u2^HlDiiBGvC74oAl3z9T`1PYuoTlvT&oVoeom8Z3o; zg&dnM){LY@icY`|^*d4a8_GF>h1P)rqCY&1Qu=Gp=ga9huAY6?i5!7Q|8c#?j>K~( zyvXuI9e%;16907gk%;8tmq(O}*J4tBKABJ_(g{bql#js+uXz55y!N|t-X!E5g-}@C zPv|S|DOci%vmi4GuKIH|`j-c)`A+JEH8@{)?sRKWhIUh_E#&$(wKj?=Efx75OI z0Ebs-CZq7x2!&DZCVY3E8qSBE@*GeW@;W+xJYIIL=vPv4cG-yDBkwXaysVJW8j%dx0f z`C=7_RVY?Vu?`fgSgh7!wGpeWSnb8?AXY-Gj$$1t)={t&)1&2B7qPmD)kCaaV)YiQ zk68W0>Mzy_Vhs@MB(Y8w>r}B$7wZhMhQLxx&yr)q#2O*iNU_cq>m0F0i#1lPabk@Z zt3s^v#hNJAMPgkd)}>-q!ct5p$+0P7T`txYV$Be1mRMJbb&Xha#F{78bz;pI>qfB_ zh;@rtw~2K-EXDK=Iks4=rD81;Yq?k}#9ArVePTTz)C)>^S%6KkDVZ;JJ{SnrDUo>(7r$~Q#hNVERI#Rs zH64~>Izx`l66-3lt`TdFSo6fXPOSN2-6+-qv2GFTHnDCOYmrz>#JW?gyI?7%%jMV# zu~v$8pI8rw^^jPr#ClY$$HaOtd}F z>kYBq6zeUq-WKZ}vECJHy;$#w^}bjii1ndZ8(=A>AIY&##M&s<=VE;+*4JWvE7td7 z{V3MYVr>#@i&$I5`dzF)#rj*Ue_$!5+vV85V(kzsbhmRa4vQ5LD@Uwcv1*A`TdX=_ z)fH=w8Y5+?y-A#_|A;FIES!5@K}}>qxPV605UVUB&7yR!^~x5$jm7 z`iga&SjUTXqF4jP8YI>!Vx0y{P3v?yHdw4P#5z-~A!3~+)=;sAi8WlT5n`2yHBzim zVx28ksaWTTb*@;W#Tp~lSh32)8Yk9yVvQH8T&xPQCWv*uSQm&jQLGEax=5^xVX01D zBF8S3W0%RXNpftm9Gfb~E|+6h$g$~iY^EHWCC9FkV^_sqm{7wZPGZW8Ne zv2GP>p;&i_wOFjBVl5MExmYX2S_w;a=w3N?zgQ27^{`lvh_za*$HiJB)>C3VBi3_b zy&%?q#d=w+wPL*{);d^<=^JwFEwSDaYrRkqO15^I}S+r`=;R(OT;NRlH~EwSo|wToEw#A+bc?qcl; zOEGOI#~O*XmspL(+FPuB#A+f|Q?Z(fwXazFiPc=J{l#h_R#dD!$I8uTi(b=;DJzl_ zDR7SE6pGc-v1%PC)TVn@~tA3^bX2!_!f$!{q`4c zXr$viU&51@Lc@`}C{q13LHgwmy%`6eie60d3cN=TrINoN;$L4!mNTS!H8vSo#lJXO zL;>|`W%3QK$uR#)C$fyfc=459drYabB$?H3YzhCWyh^R5$zcC+c$-r-9(Ph~c(udH zUq<1*d;j;p|Leg2b>RQA4ya!StFN^i)M-!~znVA{w=VweYR=)X)H@nF!cxE0>y*5) zP@s`r*-$BNZQqJ8C9Ke3Jz ztG`&si*zGYV5)MFY+JGzdyDve?$IT`R~Wx&0ine znE!kJxA{NEzRUl%;QRbV1wZ6}QSf8_s|7#hzfanX$9ZM9xnJX_EN#-*iQvh3$7|y zSnyZDT?O~W?=RR;@N&V^@iz;ujIS@)82_|jdHl12x8pw)+z|h*;Kleq1*_we;+*(a)n_M8ArD6Wtu0nl~-) zio7fHX6Mbzo1b@6-h#Zl^6tr7nfGAcLwS$ptKQPHb-M+Sqlm8)7%bZi(F%TNt||wkWnFwlsEU zY+3A{*vi=bu?J$SV$Z~$i#;EEA@*wQwb<*i^|AM3pT)k2eHHsA_Fe4z*pIQFW1C}t z#-&Ef5C$V4;MUAu%_Udf|nqTR|{S* zc%$IWf_DnuEm&Xh0p#*Y!KVeE6?{?fRRN?~@I%2*1)B=C7W`K52PCzv;GcpW1(V`a z%29RgYe@hpumi!YC_h_8&_2O&KaUj;F( zhRoJLP)|c<&&OYkzXV~ejlULO7k@MUHYE36{Db%g2<>BtY$K%hCFJ)lWVb24IsRw- zulTn3_V~Z?%EC#7QwpaRPA{BMIJZc*20B_w-+ueysPlu!Y2yX z6h2k>bm51E8wx)z{G@PG;g-U!h09ys-Ev9M(xQzAeRj~6gMK~etKy%EHx+Lw{Tur`OcO|&_rO_ih3=pk*|bm-6l-xKW*J)|uq zoQ3yd?AQ?wjhHrS)@LP&e;=&Bf1TQ%Viqt~aOV*~JhlaKy1(%L4 z8Q(F#d&j}Yk1rcFe(0EJPaG+aww##gP&Bw->G1Jok4@Stvk2bPtME+5=)0L(+$w{ClQ>vnApY1eM>u+p)Ek0~p! zI3>}6A4rF{Z9QW2==|tjVAiVQ!f_=dN=JuUjikrubw5A{1OoSqZL0zlc_hgJ-QT^8`Egu{Lay+ggU z>Qf88h${5UhMj|&BLdbmK7DCbGJbs7`0*v<%Eni895)_Ps0i)Zvw5>&?Zc-m!+6?4 z)Qy@~K06__1QMtJnha`y`&yF&L-e(>7G7e&_k;Lru{u^)9jmP1?+s@+fv!$29Xq1z zg7Rn|yw_^*A#Dct9y@&Wgb^h$TeoT5wr!g>_&#{T@bMLchnL~rIKBeifyRamFB?0u zbX4oJLwkfjTsQmT505`~TfGs#bu2jO!>=1&;}7@(MrO#Tjz8>(ZfESeJ#y&BN7Z`% zjtd$d?+tP%(lfVjd;X~Z^w{+Mv0okj@w#nI8;&XRb=6}^#ta{K;gE8smpeH2+--|v z$KQCwfp-mB^v8J(clZOv71L*s8FT;nBc7YI^@OS0kLxhsa0|R+#~$xQH4#;JN@-#-?v=;PoL797Q4-D5*jiD!y7s} zxu@gk-G(EFl#QcLw9<=rweW9ngen{3-QBausKlKklv_EwGhPb3u1RFK`PBjN!`N7T z{*_VWe}nXclKD3w|HP)DA?J_0AX%3FLPD)vItj4bRvwJhotZ}=b7Gauan&;MC-6g+qwxq^Sr_R$GkYVmUo+;Z zuC8jq*_5`Z3BH_z=QPQ*`Ax#zn}v5fD>bb;(>avbwi&*3s}~A2Ro9qIjPHwjAy8p`zDPX1!v3dAd<3R8Xa8WtGgG?V-HuDDTTw__7tx6B=_~_-vG$i6mU3Q*US1 zA;`L(vhHtFv^{o%~11w&K#c3v^5fMq{K(tNo#?)O`n-6vfu|%reL-LB+)G?7D-% zC`v0yPz>Zn1SBI#SHdDef+R8F0D>4WXT>ZknDeNZbB>sE)~jCcy@qT2-}h8i_vzjq z!aU#q{NHa|UE!QMbm5MX! zG}s08RKb$UTu^lRQ z!9QX!e^Rt3SnDd*dVDr+m7V=s0H$3Ada7DcHLqs9p>uKj8TEpZ&w5SqeOHY9I=CE& z_O4;Qk&AJAV?RCcKR~@oUC*CKN1@iWtTkf^Zl~<;kEN!~lTCJMp72`=)mX(EolnGV z^R9_RE8{4bCD=|!X{U~QBhb)wtk!oaZdaq49kgtypRS|9pi%gjIAG5*+>Yy}N8Yz+ zY=W++`-~NDV8xr4<92IzU9kaLJYJ(wqnjLrnyXp!q*HMFtcRWje?ya3NX-d#3>=Dj zYglji3f#W$r3Wl=xh+&r>&lupvS#BmaJ#X$u1Q_<;hKI=j77bhSg-s{+_Ke)L=*Nz zN%A&SdNO37o~#MY&8+qWt4&3R$yE3B7n0UtAs;g2)y>RyXVx3SX0cs9xXfJ$4_vUMSFys@58~DVv&S~J!tbg=r;dJwQdGE(6>edLQL2J` z-9bK7(!X}xMC{c^*W!^|YqtgJUeCIzM{xTQbz9iRD)?8#b?c&C4Z{trn|utn#}7#) zb~%7B)FWg`LXo5bB~4oUqK3^LH|2;zdaS0b?VrGH%AtuwQ_&;YMkI77AR(g78cG=S zByJx;!q!GYCy~HE@J|fEmjosbpEYb|cYdE?dM*Cme0fQ|Qlh>CfVh#>Uwj3(Cgb7V ztX`66vXV82f*+gz+8Gn+2Y4;dI=f;A@ns7nu6+%+)u^+jtuy#q)H%F%ZZ!_==FP5^ zKLv6vbw^9Lv!!#_;dc839HWS$i6&!Nt5@v=93%9dF&BT>GY4S`-xl;d0w)iq-3)e; zkg#|+RIc|XZf`=ujs!kc(t1?#K*+$}NlEI|v4AAhrKBa4wB=j49Wk-4q`85l>Olnr zWsIN`DJcCmZpm6LsGq2m3k3Drkff!Qw8uNRogb3aUnHFtNE*B$Ny{i{!n?TbHYt(V z$%koxNV+JHRNb>@0qdv=U^5FHon<*9Y&?; z+Ew(*?dVWtbcPD{V^em)=GWksyotBFd3%Vrr+IsYw|98^l(&EI_7iUP{$i>D6iRNz z8x6}{lW5YDf5K~2j96#2yc1e37VCzi#=_aqa!yjT+-%IKB!_L1UD<$Gi_{WYooq6n zf@fnARbtglP=oFLaym%cLm>97d5OfH7PJRPC*<_42K}t+qQ~k(Vj_0|6grtT*BpwP z|3=LrlL10XsS1`)5AveoLCsXG&5P^!bIB)xQao1v(`mYD|mH8Yxwti0>kcCV?hjnMpK;6E_B@!9a?eHG@ zOtJ~bn`^o6fC23~gzBElx+l#<-B(c8OtAHw=NSPUt5(2)0|xaERX>l_SIt88QO6^7 zp15u*vFJLDMM%5%@BoSo)D&dP=OKA4ygk|F~j)r7N!Gv?s#VGp{1 zGM-of8IPT?eqC;HgL(>HQ6v^OsE?7H$i0IRbRlJQKOQm~EW&(IUi5676Au^l`B+PAdZj+&#U%$-~_XWsal+WECJWRr(qr=(I% za?P=PV{@2<{2#5N?e|oQ?h67xyd)i`%Il*AI!H@dGq54S_f9A9kIYL_xm_BhEDQO|rP4-9m^RCIZs?8nHCO0uH%@)Y+E#z33EvHgj<>1bTqt#UX zJ0T$TD{e`Cekl1HZ~ROVeEA=NItTQHFZv4Yj)q?akJ#EtHC&lUWpN1Nzml0g9UBq< z2!`8T{E8GdcSScol|l3G;-N3XZJy+%*T|G<`O z1zQ6dF2gM~Cekx}Tq88OJYZp`Ohue*P&y`eeErSGEZAa9E>+TSOzy5kqcOSL5{<{? zE>3Pa1|U6Qao}k82kTa7p5K`QK-C?zUfn@xGG;)}UNr*;^~85$C(W(q;K*&!)DH8_ zz;IZAJ1hIJXQ2GvLATD~w*gYAQYt$Q%9a%F%Z7=r&F0_>#dLZ+-Jp%u#-9d<)Se5% zyH0IoP8Q`?bQ?OT`;eY8vke`T$o&)jA`{ba5Vr%QW=~`vk4Ef`M?UBz94T<{^H`iB zFjjq(4nldUDetSNj-e=TW%Yv`pMMt02M5@+!&vaK*&5hXqmCQM!O-23`1At49JOu8=sk&)9(0p@hzK_+M-&UhLwbMwoOQgEB!3WG{ z&p4u%A1A~Ic+loK(Cftv+kDfS+d;1+JAuHlPH8=RYDzCq-m?_l%+4s^)&Mk6dvguS zpS4YdX6@}@QdgQ}p9_trcB4K21Ry2NIqPKj#kypkH%^>MeylF}0B>t~<9F(k{6t;y zVcz(Ox+K3&mwb#jew{AKv6p<3x2Je}nm6`vl1e3?FDYf@DBXfFtKHwvefl05|d`v2CjGq+yejF z4AkMb`KV4i-I*Q;EsXwy_2`&^^6J2M;TQg({nc z{fVz9A9<_!)T*YwdXP4F^njj&CLhgHl0>4pSoS4%3+AyFt=#6|`68}3)edLkk@du! ztNZH-m!6k1M1h_MJ$va9z^STPoyn~4P)zRrbjE482c5gGIfn@bY-2iji5;-?T8h`Z z8GP|1!Q-!%U8CRj?bfwj*RFCl7d=qx)@|=@dz)ojKK{$4n_vH>s^16wazJ0b-E0di zyL#d#6Y#vBJJY~cniv(-Xs;`jp~9g6AHb{QsYGs_!+YrZh~M_dwzdYpq^X&JqpRHK zt~CxfV!)>S0Z|UcpWeOukO8um41t&YiawE*q95?-MQH83QD{3>k3bKR?O4OaTci5a z@@P%;K4{!@S>Vvxw!jcrz_qG^`r38<>GrAXDanzjSxp zl6&yhmbZ4iwdbt^Z(K-{d-BGmI@yJ{eR$&(pWKhP{dwc`nC!+|ci!kw$)3E?{$y|7 zxSl2Z@Ww4FrX$W-0;isjDgfv9F)ph-7Rzj6D~Led{(4>?gYu>vloN;)SrAP1%v=V2_zhAJszXm< zdx4N{58v(7QM`8~C%I3Y`*Me|lfikgHg7u0hbi;)=6+jX*vUQw;#U!Xa8C!}Zt=yF z)JT+v3A}@FqqL?Vtu(<8snVc!dUo#!)woa+f_8es-X4UL{88F}h#IAQ9{I`%({^@% zE#(KpA8O}waq8?0*}hI$X<|!%F^KGd8$de0%PQDwZ`}uk_bovWfL&0|9Rp3!NYC9O!N)!B6thA&-*&kB_Pu*MML`k05xTTw|o}Y5L z1cYEBPC`z~>}L3QB42(@{>2o(5u4L^vdz?ObFUcf(9YG zSRw87WHJYOZ#RGo^ zvT=X*Y=Xw;Hxu~z@Q44QC>J2>+j9!+UUJ=n$32{j29J9@km)Sljb9+vj2}09Hb2vu z$W^%!^{hW>3~7h0mA|$RfR@`v7n`B;CQPWEGskRuWxe4p@Hsi7*^3IJ&rpv}h)x@< zw`!9yye@8*=vp(-{FIDGz~c_D75KtGIWsSZ?Jv#@i1^Mq-V$b-Ct8#yxRi4WaPPwE zKKXH8r_WObJ;NMnPj^x|Cy~7(H)suW)OLAIF^1LJYA#eQ3c9N|mxzkU6%G+nWea;)7B$NDr zc9N5LlFLGpXK%@GdHV-%T>IoB*vTK5;&hzksaKM#can2v@;|(BtDodSN0MKt#twzk z98Bw@R|R%Fr$mje>Z zGY;Om{l@{qBQCbov!{OO=?MyFR#5uuJ?dzb^Vt*Sz4T16MIzNWW;5ddj4n9hYK888 zPr7?VFf`li4e0iX)Ne6675BrOK-2(;dLN=n65KwzfgA54|Jzrg(ggR*gmpdRtsc`l81)LU3uG$w}y%1WFeT% zhjjrv!Be*LHfmC~KYuDXEAvE0`d?4DO<_N08rmN^)9Qf^D{GIv9`@x%9d63;Uuoii zz+d!Z1?H**pS;{t{Qs}RiCZ(eubx?_BvO;{v*{@_=8rpK%ETJ{y$ha-ac)^N184C)K zZ00iXSPbDzKxkwt+xepDjxtphUuk= zg9HEIqn@lO7Kk!p9WB?uU>~npq$SOEZ4XWLphH(*-Cpo)1}dA&&#%|T_^6V zn#@M`*9z%H%LB2O*K=sifPuYw^JizWH-DnS}kJh=75uLTi?*YQtVZ#Ot#Y@eeojQ(`hx6V&hv4sw z(9xn^{Y0t(e$p6yQm~#893#*(K9fQ5OdJ1AA@|Lt2|lZ#X`ZzCXbpkY`?&}8+8KCK zoPd%veTqNlz@Po-M(RgxV*H9hg`q`9@2f7<$!3|}W*CX)=!W?yK;`Rp`e zSnz7!E`=Nd_^)B2-d=p9o`P@YBy#PCm>*;cBop^e^CyUXU=kG32ohQ7#d7WJje1UN_rtr zR;aXwWFUm~N#}+hGE_Q z!as%)^jBBZzef6NW}tZYo*2x&=KN7YseRWoo8L1suSBH74sJGoT+II)|g2r$+1oJ;97aIghA_rXIS3pzDpp z=|r9OYRlu^QLb~Zk1f4#6#gB-xr6v8U)X)niYpxcFUn$s?HWqWE9qVVLK+`Fyv+(o z-Fss8^}*wNj@w7+2F`OmR-xxSzDM`xJbLbOAH+dD6^7`F1UI+@D)gpx9=3}-t#@xG zf@72V+-2_%9QZ-|uAMo&?6{+r(qnvM35mTz+bEvQ>?+4XaC4lc0Gu%n&6cs{sVn%m zaO3z3Ap9PtW)lD6*d3{*(bm@)y2tN!F78R7{8_pht<4`bbm&~nDQxOc*VLT4g(Zmr zwA5_OHZ%$U-+8o1^{RWQH_80zkUwd1dHV(?H%#2Mr*X+?Fl>S|?6$bVw`E>g0K{eQ z`l<8AvCWQ}FnOG~sM#6y2s{q1+lJquMOQh(JQ z-~KDT;3=&N27WKI+BS7gj{ViM(@SpKE=EZpDvdzQCA9i!~jV=xUGf5gOb+g>|9 z2Vjk=q+hXBfyUPX94w(90k#E!Zvup%Ur}_z7N{R=Gp{H%v@b9(Mc;y;|J`pa1_k(V z!{<8>f5O>2py^F#efZVqIMLuAf55A{xJ|@oF=fw;k{?%07iYfEIWyn#0^h#cMff|) z#{Rrx;8nklVxt%AgGVZiKf7H#-?{U-vE`)+{!)eA=>H*9-KRKipStNsMqm1cPWoQ! zCpYn5ZOWGFOJifIySxAk{Vwq|43QsYh@9;2zWGy9{|TlMl)2cSyv#&%xl`lZLWFa~ zdNUC(cib1b-Jg-N+Lf;;Q2qwzpT51Mn^w9GeXxtg+x}``nUk_3A0FMwjr?fiR!3@9 zn6#f=yagxz1G@OHVPg57c$mU>24~fbpItL?%A8qnsoNcK>H3J@j^aaYjeKg zz8W=Q9^O1o$M1b7I$~o-Tf%gXKkH<^Ry?Vpsf;EQox^ zJ$?c{h=>{;ob(6XbM>5QQ)cmZ7$9!ri1)3Jc&T&k3A6dUdB3Z4VS(~N1~B6dS32%{ zq$9`kmvDnz*{|KX#1ePgyLUQDAK543x4ih;i0t@Fq~sf-`=xf(r0*}#gqj&PdtbnX}N8eqz7Xz{pX zIC(=1zdO-J$tPXKp9+-k9GNIAu2WsTJN#AGVE3FO+*pWktMC5YAwl`qT$MEiDGPmy zQTq*7Wp*LLf5aZ+GMtNKSRUzfTQgQUIcscB_`Ub0qg+>z(l?-3aZkHSmky^x@jS(# z@{uE)S%~nwynLB6dCDYgO##X*S7TP-J+_sL9qH8Jt_k=8{~G5LM_FEwQq|79P?Pzp z*75&hjyQblKXZit6e7&;;YOP2kuO}0BMT9_b^s=(aT#T&yE&$HA;K&p%5>u0u7Q8Y z9LL}%%hs;><9OJ1tdpIz#R0GhZYh0J{$3ltR@vdXevgP;?FaKydkz4L4jVuNIg=t*I$r4A~-}h9j;abHj?%IqrG=#!QT9D{!^9)D{a~tJ z>Kbom-+a%ST|23E?u5xkw^IxmpNzsMEU^#APXJRH1jhJhmQ&>jB?vnpq!CzN4`C~W zW(YeXR3J1&AgwV%3ZVhQ)(9*sL)adn3SmoxN`x&C8X;_kK%VUonjmbBP#J;EkX+f!nG4Za|C=7mA^X#93{C)f8h>L{J>HuDtY0! z^lw#?`-nLR@#zrir*kVwbtSnEm_y?}9g6ws+-0P?lH7aD!7!f=koF7W|ox6%uSCV_3Ie_ic(K&uP zcQvW5B=;(FaDsr|izP%|5WXgqyEc?t70O)~%3UAI-4M#H4&~N_a)0O?27zcX%*MlQ zJi^8Y+jyjnN7;C^jmOwH_cEo9b-7pS<_>W*!NbqJM$T~VP{%1K`?)vB8P3%>PU$;8 z_a-^Rxx*Z%c!ZyOo1Ed?IL9e|=I7oeXE-udpEI(64pq+*OAx12+R<2sxu^v50ju(Fhf!6gKgKHHWdwwz za_1WkRFp|j%DOj}*~4;NydjR}sLKg3_Z$`r#0Wb( z57!-ri&JYZUr-jl%0eADNw0^izOgGqu3HPr+SPEiSU=Z5!^LGHcU?hQ_*5$F00a!(sdzx8wdXt;)u zYgs{A<;HsYqvH~vY-jw*`eawdwZzDZ;hMNnT=+Tz(UcY!6_V9xgB(39#|en*>at+H z)Z8l5E_FCQwtnvQ4RZV$a2y*iW2eB<0vvq;j-%sc;FBZ{tpXfN1CFC&WpEQkOXH~r zTI#&mx-Bg=_k!xFq@J&^a+$t-wh%{dd4N>zse)X0E3U^2a^b5?4v$=6E_|%o=X#`| zEKhMgSdeRo;<~>e*HIhAb*AFFw~#FM6$8FsAXbQXhcM?BS2%7j#4&4w9Bw8PIkyy& zlY8D!gzLtFTt6wU8wzsmsH`u{)l+fVaatFF96nU!_wdyPTU?~Lt|-LChZM1|AV;<1 zSXoHMagM{z;4vDnHg%>R@T}oXJJ|t2GgHW66If-jtVQMaCG+PhH%^Tw2LvP{w*nh8w znzP6huJ3kH>*4rhLmK8927N&}by3Q--5>|P(&lQZucRd91#xL)oFV_7!7?)Qf3@Q>8p!RYJu4H4?ThT1D$@;F0vb8@8aF@}os46z6g z%&FXv`b4K>3-iQ#j^V(`Mgb1ugmZ`jR6bLUD@dIS%EW@y+*JmZ!wYk~Y&fPC=J>DS zm>$p3K)&)sb9*8H!jj$y)eYnaVkpK>D%KwsG?2d~r35_m$`Kw9?$FJ0D958W9=Ktm zmBTb1nem{E$6-7KLx-2(q_PC3nk8_$5}0vxL3U<9~M$tVOoNR+@yk`0**;ac0g!`P=-*BkVe3OE~!M=5upkpgU}pdrv~yf zWojFPG5_F=8vZ}VxQ9_=gMOT=i!pztNeeJ3$mv;87&nlQ%xH|@fBgGNO2)u0nT&u* zwFE=BWE#Q|2pFs-GZ1DX%tAO4VK%}X1WXwvc-SqO-#|V>M#-BRa@JP(QJ;;`q=9_5 za8p|$KU+d8{PsP3X-O|9I{^-kILf8`Ft>O@X-T!?<_t`3j#DgElHSVKM0%^VgrDdU zy*Xkjk0YBSpEZ5%2J&4IG@rsWmO22TF9N2q6i?m&Pzuvn3e#As2H`LSOj9XLQz=YS zvMSXgo`isDE`@0>g=sE@X)eXJa4Z6*Ia&EI#8ZP1FpZ`#jixY-rZA1BFpZ{0G>{+i zQH>S|EfHEFV11A`Z@VCFjj$`iZV13u4m@{9yaz&Cgmwt+5jr5iXXMQo)(1Jz+zT<* z2YG9T^+Ddi!BgZYvn%3m2;C8|KJc%-s0KPhUgn|efRz`1 za5y;|#&jw#)-a{Y%eY2}F*V9dKunMF5)V_Pyhy|}DK8H*h%wd5i#ANRDNLFCdk3n4 zv7f^DPT^lF@Pn5qhR2p90fv9E3}aC)(%`vCbc9@_0bH5J zScbJHiB6IH)riT<{A&oLlb;vm07c0&y$ynvNjXjzbdd0~9?Q_l62l23J{hrV2P?PF zOSy|J&G9Z&ychx@-c4x}J>j>BAr+ESYiX{{af%m1&*vo_4pz`khZpffPx|#}SAPU& zGkV{rk+-*{kuQp!mI*KO>ya0GHeV*~W0||KpD3tjBTJ)fVo19%0R8@^PJI#BcT69M z;4ZeoI?k4UKE>3>=5M$Povz8l{rq; zqs*@moXqixMm;uGX0576nH)1tCZ=*!@CB~P@ak{a34p;Rk^IQZcbA+N%-p0zr4DIVenI|APnV6-08YcIRmRY0fQ6@2T zG7nQU`s2pxIYHH*w>b?Yk{4u1!~;ZCrpr9(OT)9fGs_LZqW~;_dol zF4Dx!UGy!EL)M|cI2_1Ne{$G!AL8V)Y;#LZx@(g@Q%sx0(_wnMm8sk0p2N{^vvk)c@hYYte?dL^9_w>%)9w9J z(RM}JwM9QI#=iHIyf2WB_T%e{{<)>QHaTvJY4af^^Gl?o{dkX}Qzz10o5Z3ROs`Th zsk6rP5=Co*8)4p1`BvNAQUy%qgTOLuK@+!WI$=QU^NjaH^^a~DNlW9hC<&TYlC$@W~E z&smweKZ&2CKWphMm^R;5GXF%Hm&TTU z<8=DN(p{TdAz#e6d_c)$ecj$&ipIT^Yinzyi)rghC2wb>bz2uJS{7;77VRwt%VkR5 zCrC%J*E_`8Co}pBbm9Av2KLpys z_NX`MEN7lE^W5uj%rm_jA*x#!lx;}Hap2(?ri>d9D8uQ`y?QY|QGt4{A6g^r?BYC4 znU1y#(ylG~Vln+gnNHqkNJo9*zbK(^)4orI8nj8waM}n z0^4I-ry!8deHinn*}Suh`-}f+yEy)xT^HH*G|uA{{Q^tZc8#|5_1Sg4t>^3_R^)ef zaZmL>ZC6LgbatI*+tYTnQS@^xUE9^t(${C#*|wgu>s*_6cI|?EX9V^y`;EAW#>UYk5D~a`Ihl=}sQ!+pjI%`Qqm` zAC=E%QfKRvNb{mDymmuydp#%THIzAhw4N`ha_Y%>k}=nRC!h0(8y}R<{yG+cd=5*- zyjZrEjak+dLDRVJB9GHc94Bm_7ctfSN%;=z4oEwhza!0yyu4VS zKI`beNomk;yCcu}K=&EP3i*ix+i`U2=Hz^jG%r2_@Y(}``#Q>Dn{1!>@^X37oJ`7f zZ91863b$#`)U0c>tH<@9dNKb>q#oOdV&&?61)8h(TBII%3e|f@)q5jSk8@q2de5tR zFGcEc%`H^#K~<0Q2ruf*i}SAYUFy6}O3nKe(kWBZUyjf@W;OlQ2%UbX>90rV)I-x> zjL_Mirz4P$`Vj+OoS%5LMQDZKd?o7VoNJx0==t<$lvAejA?N>dY&qNd$kH1j=0)F| zhT!UHd9}8j^*HBKE_LD65#b4&rVR49^)Bkq&Q9vg@$d5VFY@ky;4ae0=kV)=wA0Pi zBYl5c&UW(%l+z4>7xj$FX>ZFMjrAy}jV)(>Edu2b170lC{-@jL`s?yvBCYM9zen5W z+|06Q`|JlN=X0dB9rXXG9O@h=hw~QuhB|+NpzUD46td$Vpt*Xd*?O)&SSQ;4N0vWo z2gkpYbBdMY`h(*sD(A%la-LRlPPKAef3!xvkRA7_dgma`%h|Cj(uL~X2%6LTEU6Xv z(QfOhcbTepwyo#%?2f$iU-rit2<(q?1YSK5G<^l~q^A*h^+eG0(~&2g&;Go6BWU_n zw%p0Dj?k~LbSJ-0gnp%^JNbPhboRN{|G)^H`x32xzX+Xkht_{Ugnpf+JN*xe(66<0 zr~kkReU+s<{RboO=04)YwmJS?KYwD&oV+2(NBOgg|KkY%s2G0g?&NHH!82-Bz|5p+Iqht72EB=2)_!rsy z7Kl0jM(4guQ08>wvjH#e5qT{}pst1Lo(7t$d!yxb^X8Hb)YWI=oGW={Yom9V@(t9jQFS?Xc{!bF&-&Ws`tRChzw_G3#*ZUjU)}DYySjH;UN^@-xq-SI z|E}&D%j@iYY6Ep!sJf>h&5LEco<>-o&U{XC?cQ#Aoo_s|fw~;KuI{Bs^Kx~cLwbGf za{M<$pbYjWFXtQ2BfY-5UxM!H-eGxLBIfmi%@^|Lw?KDwxkmDGbzek!eeDttS9i7L z-3c+TS8TpeyZ3?a>aLU;!TSH|2I{U+bvYKOV{-&vZjX8u(v%+^`|KCj?#W2=a=x)A z($%(%GT9fKseC`AIiHZmxt%dDmT|6hw5CXF+6lJJE9?Ed~l0M9qQwKg5Ivq?a=J&sG^@tnG zS#MoTy?!Wj_-qPxZBdVMo!%RR9es;>@2u)^t#bOkgEZ~l1;JsrJyN7^40hyWh+;?E zT^sjXS=7N@eco zP^VoHc#)U$G3iXxes@vlsNc~(@`tRC!2x+H-lXY`}dR&uSy@w<9s4w?W4m;Op zPVZ7nbNHNxypzSbjXLaxz>E5>Kp@@mbN+DrPa>`PId5!A+w+wy;;Ch^?HQKt+McTT zACK@iKz>u&K3K_mIwFg0bN{aGrawBnpNQ~pZE3`ubsgrkXFp40zr2k=dK&~@oP#Jc zuHGJ&#(JC=S5HU0KYdv7KNjKV+O;XR-K1o_9FY}g+m(v{*$97}Z5;p3wihD&>=TZEZQIF; z|B(nk=lw;NPTkx%V7qbs#_{jkc6%q+53C>UhpCGHIi$(s_~UFlRPnzU;iqjQEZz0n z5XJv!gufH=9Iu??*e?B+y2shZvaXg+zGVok!?D0CY8!Q-PdF@yvF2wTjRo_>+VP(h z;io*!&phWw$G<$nPy0E4vX7YNwIzb%Ux>8Ro%Td!vyS6kgtXS3ctvIZYGqIs_lZt6 z`J%GFQ@lB(wQTZge(L?P;$Ix$r;eJRxNy#58Fg8Tpyg99%}@Ey*fR1jLD2m4cg;`v zYi$|%PejoCTOl9C<~GGopK#c4jnTZ6vr6$+C|>%h=B3`3DBgC8cbf<=<({c{xyN@p z@HsImmzX*H+AH4eZMpL)$~{K$axNo2PBzzyCJ36J>px|ak2GRP`eX#x<`YQs;(E!e z8A4RYu_$x=Es=I@@+?&IvYo+-_aMbv9^qwM)rz;3;^kN)uG*G;EHB$&yUvz9Rk^m2 z_Bfr7MY=5lFZOd(XWHa==OE4Yd9m-Jda!NsM)e?{E7y87w&m3KXauK671B}JY}3im zHvWNf>KyIIpKUp1(>I*#4APY2@T1&s5h#Pamm|=h=*PU8BWQloK16W*rz6eF;j$Cb znxC}S5FG!NNNf2mBK)L1rT8yKTFZC+q4mFC@n32$*7CE+X@1hK zMsWIHg|wExbA+F?3l#q)NNf4KAQzQ?s^VXXw3gpG!cQ9Kb*Im1NNf4KA{UiENAXi1 zEuU+=<|plN#eXi+T0ZyJnxC{W2u`2Nkk<0O2tR296+ibtTK?|HMdkNY{FfrF<-4)$ z{DHL2il2KhEuVfJl}`+u{%<2q8EFJw9T1}Y9G{N=U8FU?n{%8#l){-YHCMM!J; z2SoTOYntLeGs535hQCJfQ#Y;80OX?mGSu=%`-Qv?hntYr{W1u7jT_tOuK545{H|Zz z-a`8o$D)(}cZ8qMBT@OBYaM?MX>Av6i1Jq|{zVafo_j|5w^sZoM)-%v@Y7$NK1(C~ zBVzdfi!#<>ScahWKNz{FKJ-<`e^P}1Fyy%>)p&kv`J?^#t|})#Wio!lrkP)jz>E7> zUgHp=^11&fZ&dzcs$9!oYs*<@4FazYHXe^SYVU0*BQFETbrQk(&jh5S{MVw)@e?cZ zmm~0+h!ExHSabYbH?{oQ82%NC|2)g@{Uo za(=XOc0kN)GD6heLr~`IJsW9lFJ(pfIYu4-IhNnqI~Dn;y}d0z?bZFxIoQeh9%;7Q z5rG%yvZx&T1o@+KJX=m0*F?(UoWbh|gsA?_QRdpcR=5KHnI6Nxo#J0*`JKHpV)!># z{GTGN@noMx_2F8UvUNVQ{7(L?7=HGt<3G#tJO4j2hW~TLf4=2+@@L2JzpePMMw*wC zKL_ck{x6`+>2r;62jgol^3i^L#PUb`@qQ(Tdh&AqFc0adoLf-FcB67`u;uLI3lMlY zf0&PSRR5JIbNc^^wC*pi!BKu8}G*;9o2sv${hdCNNamJ2SxdZEB;?Bzq9wa82-MB|0m1u z{O9->{{0mHZbncIY-9u;rBX6aueKHs*Na z6_v&DA190BpXHSGHiDLQj?G79@p&{(7Uv-+>n&T?>2;pX>+wPx9TsfgVeQV-+>wTnob+++EHjc^~i}E;GBWyWsdB@guvR<+Is4aa} zox71HCZ6Se)yCZrvpxC?>HFF|+quh@xjK6xPd}yak(c9*F)x-8C&msxr_au+>}I5S zQ5G-OuR?HjZj#b~zBlr%5DK-qm8G#hb)()+7nV7>P8T3nN*TectK(Kfv)Z4R(?DDy{~)@}Ay^ncp4Ym+v! zU0!UHYpnL+VlZee(hRPT+BETWZ8TT(M`Gy3wAo0>AJKHCi)r%*)FWoZ z{XqmRljUC`IQrTMo%$5hCg*P_^LnJC{r9Y*Ul*ZM&tlqi>jCRu8j(p|ICndpE{V|T zOU1N#p^|x3L?+uhQ_-)C(CPcdw0W$Oc^}fz{^VTm?94~#98blxd8m@fxh&e|2t{W< zXgcS|V%qGkWV(4?kCnX@{T^vC7)uR{Y_p}3`EW!gF|APahaz;&{l(bXK*?N%babrz zjWW*f^y_OQ^evGurp<3q&&j;g%G@6@FWUJDf}`JoG<9(*S#XP$Z!H;y&tZ?rMXXg9BJHm2Nb5VV{tY@YnY zLG!mjt{5CnMLo7bnYSYF>TYA|umr);`RtK$bv^9d0wE$__$BW~Lb0TSR^;qWW9ffo?0_TWC zgDuC%Kg5K8UE}}Je*>#>sb*K?24-@9B?fkAJgI3#X}wkra{QOc5>3W7tv8}kV#|Rg zXEqy{96c~OYG?xS&_wp^X4U-%Zq3}7fyuGi^O|*EzU1mgi7w|fL(w6_@XuegX0mCY zVTob#iSdnZX5zr)1PY#rW-joXsU4V{l)czBb0M2KT$*8WQ=2&h*5o?k6XS?>L&WAJ zk0ytdReOWVyo1WT{$<{QW!B2vo?y#%C|kR%``kpXbgM)nKd5Z^l7BWD&RhPVvg?f(%I9!8CZQ6tN|5oO*m-y;4CbFkJ}R7Q(N1{QUI`i&C9X;prNF^E>>hZ%!t zmDPNVXx7SQ zXz9A6#%M3yafs1=!`(4Sj2enY#3*KqGK&9d5NsJGwjjYgjG7Lkrj>b9%DlsUi^hWl zYgKnl3oO#zF~t}p-Ep`vNOi{y(R>1giRR1}rTJ_~fWlKmVI-J`<_nD%2h?m|-5v7-<@0l)rR$E_MtkXwSw{N}cgN9U6#pSxF^buujLJa*Y*`?-Ai+G0 z%E73GW!`aR-Z8#Ki$H?4syh}27U}Ld&KM-!af~rYb;lynd@+QH=FAqQ`RR}Vg_nuK zNH7o0Plo0vm3d3cyd}QoXMhwQ*Cz#<=a)i7^o0!UC4uVMD>yqX$|Q0Xmc&FIHY*Dsc0tqnTTrmL&=3&bjuw_M=cdBp5r6>;@vLY}SJD4rXjvF8W>R&19Bf&iExDa-nU*?@#=AG@EvKplD;66VvC4a8!le0I? zmW#xeH4rbhFk6%@_d)_pxJ^tzf_d0-8Em<<%)8h(B#-j2A(sY*=svl4)9koh?6?oo z#SUhRvg2t;fcg)M`baPjJFbHr*Oqx#mw8wEraS{uc!XaYn3BI*^~sf+X3OqOn6aDK!SPLauaM>Q|8^^8?p}NVMEpghUh-IVbkomS?qWd(!~yDi?ZWW zNPzn9iuy<}4?FIL9e0*_x0iXh`lftlSU)$>7l=3&<=)3$wAYWJWHZVFjj|q($LDv@@{a}hJSzD7 zfl|ST*`n|%EfIVYhy)+zfzM08=Y=xwxiaq=AEM0->lP+zh$sxv3owbh5&F=p3Zh2f z%)U|O^7R#$(hOwEQ;#Mqdj? zd!bY?VzwxZdO`v)+82>v#5^$iH!%9K%=^IysF&gEZK7&KVSs)#wuuk@tN`i*&g@SS zfPM}D(mrHm2tGf=;Bx?F{Tz=^U(oVD1^E0&@Hr5rf)BGr;WHc(fX_jQ1Rv&s&)>l3 z&ob|KADPFD^$Op{GC z1yLBT&B|#c=4@EnP{B17oY^fRa5W6z((YtsY&=@iD7;}jT1SAE-y%S3b3to5N(C)u zi$ZGwBmk`=5eZt%1Fda=R?~8CD<80<4c{>)Iu=nFu%-aa`PU8#u;aj)-M&1$$n6jS zmbVqfzqT@{Z#-hhQ~D0^h%E#yzkPt%c7oUmC>6w*Eef$yApwXjMI?wZ55y{gSlWl{ zG{dyQM5iMP!+j z-9&dF3d7Y_`PZHbt~c30lkptpPx*U%A(}-0M^B_4Z+V9n@^Ea&@TQFR(q|*ZLR_)%#cgd8pnS zX?Li8!TJu>4-%u^L?dDpvqc&8DI~zCcf}SYn1@lrVbsuaZ*aLc(6{I_kYKGkHXIsQ zqu6mImNBp9UbtFBZ;>p{+o_*V%pDWN=#$6DAQ8) z#I!%0Y0Sg4$uMnFxi_)g8}HjyA0*hUI%QH|m+q8_#w_WS@y0CGDN{uA%^*xPXSOKK zw=tSG6ot_#%tP}dq4~^mZ+f{m&DVTekizaXGtfLg9V((nWGJ6mko z4&ucYW{a{V0|_vpOiVz6dDwCkY?)W?&G8Lsj`FY}^8!P37tGl-I~Ir?J3+eG!E8}> z><$S~KP&1Z!9489!H$LH-f`vLF}^8#fE4zog@Gyg<5Zs>IK_%EN}77#O1aWbvliagx~471G5HW{a|803<;D-l9Gd z%)^c|V8@Db@6>YdWZ#s74C_D>4MG%Ne^;1Zku#sO)%rUaoY}L=!=8C|fI{9@lp%I% z07L#{q@(ACLn!R*`1N)uX!)~(_4Z7`Xc$TbBW8=js0I=M%}7MD-ZBr2E(S&ymV4*> z03Bxd#+hh5qA)-g8r$RnYo!8c0ywjmMgUqF0Hoc-%8=Rf{1|*DQr60Nd}=|S&{D}_H7kJfFV<)01EdPdN?9i@U6vqhn`77~Eg-G~G&=7HAhKb&>J+W&l{;Ruunwc~kxCQA&R^9Fkg8ktxF;hqXuthtSQ_W+vmKU=`Bt=Wdnh>la^%N5sV~@@W)b z#izv|8^!$cO+6L1U)BBU3}3D8idOSGrK}bh@GGe5X3-n34dUJq4ZaU>0$7G>8INPu03i8)9x54(oKuF+|4WZD~%_J;XJO$8O>#2D3vMvaa)Y9xx6 z@JSp-jYz})hl@?aQ2b*f6#I6J6+5OuuGqnBQFbhW1gL+ssE-8muwydpn3VP=roHiL z@36FYsBg-NV8~95jOj^%HTj9a+#T|>JBJ1SdZ_7^0%JPtuglS1erg?mH6?++ zP7yp#2D9M7Y*Bbz011HMbVTB>%ma@(z~jiYH#6-`PkYmRFfIfYSgC$JGC)E*>r4ZL z^y_rxpwkQzs$=JhAs0cg7{Y8(hFlK`Fyu1P9|`7RNDhW9Onb+ry<^heg0wf^x8(*f zgl$Sq;fz46{WUb1x*ohFio2B$$UWr@)xyX>VED zJ2CAo_ASYS3PV+|ELWB+Q_>LbBC z>^KK@oR#*@NP8=MBc28+Y{XfC5!$uRh_zuw9UIOS8=iq!v4Pp5YP z=#K>RFyuxUvO4WupY~Rzy=&6mRlY4>gCTo!I{TO2&a4j1$zKm$-PE_r*dtTlHNn(( zl`&_droQjcUjF7fQ=cgbroNj5kMF@OcraTO9)CgtVE7LrnfjOq9`^u`yVBkrY45hQ zcZ(0kU!VdjHOTG?kkI~lhXF#SzS~sC-eQnYQ{TN}$lnkwhA>-{AK!RL8z7hU^Z(VhFQE8L|%~z>p52KN8HtkhfsSy0rIt z+I!WvVqcK5??kpK>jFdauR}}MrLP)G*roEsz#WLSv_OAywJ0%fqk^3^n#{jbr&mo$ z(5r6?7~R1vU@%)07y}>y7*r#YUS%F&d;~B)NPF-3NF0Q6KxF!J5AHob2w>3t`CibU zcC-Aks5%e=L{(;sQgtjOK-FQQArj0()vuxImuc_wwD+m6?I9p#zl{vVF9U`1pR0cR z^naw^#-Yjlw{`l>lmz|ujes#8%mN0pMS(E`5`e+sh@{_`2N*vBj33h8cRms`Q4WYy zzx@!vp!@B+I{o%9QFRssh^ovMrRwpJ09EIShDb0EReyu3zoxyP)82o4Z5JBW6HJst z#E}&I;QCkFZTzw9pXuOtYKy>`{UeR7oH4XL9rVw@(7dh4!J7X$ur&W4q;W1Fvy3~U zTufnqrU6dfA6zd1E&oT_|5@7ag3*a66^xiI3Zt_j0nnU`NV=1GV6=Hfwb!7+t6$;O ztMHN)?nLAq!+oxa&O;Q2sX>LAl?YR#iU6kb!I^DX5#C8Pst8U}Y(;^oK7`;TMJDEY z6>^dyPmxKKM}z9Q^XI|N|q!DD3zR$Im3vzoGYh{tCQ zX!-2}e6|yOZbYfz!)#Ib=STi`&WdwyaNKn z^0uOkz-j}#K-Nn^)*}Y8PbqjnJY=7NmhT@x)=wb&9HjyovqeGnZ%6=S-y#yom2-p~qfu#eY&4C_xO`WaCeui?g28HA%1UcZ1dJ1T*U zKsH$*Ylc#RjM<_fYXu4Luu4P%8S{W_E+Cs-;mxY>X83qz4eQP(+67SN$Db*12w;vwq>T7Fpo*;0Y5J4yvIW{ZOCAV>gY)rbT#<^kDRfb5J4 zZ$*W7s*l$|!#c=BgAs-CI>VSM9(Jz6YX~^A=S1*2H^57Kn3W-Ltx#~C8Uxo*$~`w8 zu3@0%&k5iat$;a%h-Hqmg`nrITD zFk+X(D(7L>D8wd%GkbMK_+7^}0b+SuQ9Nv=fn6ZGL_u~@3}jO&_?mdgrh%5fI)Lmd zf$RvB3S`U{1=-P%0LYF+B#I(0AAFpE!>#-&}4pA7d8vy~{>nu+! z$z*R;cr65H_Lc}mfMU+6wRf3NK&b-BaP+o&P5c)Y_0OKM-^u0 zfiwF^MffG*qXA}lTTy)Me&u6%VNC0|yM1mgk zK<^!(_g00s&d2Q$!}q9(9zzty?Jd~jrndJLZjXaA`(8!(DDC|Kx4f+=Znw^WPvH8y zLHPs)ydMwBlc43_3qW~SKzRzK0t&N5f$}OO0F>tu2`J11lurT5$37yj8K&1w^ai3Z zA|ESH`a&VH4xHJ~BZzzvAfi3V$_N4SChLC@56D}fIpWvqb^&IV1p( z4-g3;%ma`g0LXV0-nTv`Ul_hGP4pF_FecwAFZq|kU&Mbjz*({#_3quBj$rCE@+FA}Om^Z5`anloFJ<|je|6h2lIMuK^0-WrKD zy`Gg`ci+S(!4NjFuQIWZGO>4HOTK4dV)vjp#>6^a*k25N2Ca&r%ob(nI!J(hFN%Fg zFb_kA!qCB$-oQ$4fN$cPhV?BIy^ScmFbsylOZn`xG?N`s8NAbY2b|gAmEq}SghIzw zl%;Z@fk8ZYK#=w~SMO5Th)Otp-B&;FftDX$>A%MqCK$bsQo)GXqA>az5&+F7h-8&u z9vB@8jK)@aqkVwBF?`>e=pTr}0FAX>%#RX`QviJj&g@|kfW`#?=@D*a2tK1@@cEvy z#>M0F18Dif0(@!&pMRoM@L{$neEx(4;PVqA!H0R^a|H02TIo%$^d|Wb{bgAHHc_H9 z3ei-U?!e+)}R1dWLi~ytQf>8>k zf)TStVbl~7fKfw4f)Vq;=qO+`uhN_21GJ6d+tx(eAqxA@JY$bM?H!{4+8&(Qqay$v z69A-r$jT5OniGT14wQ9FJU-1p%O4%!vq11EL#g1yY*F~Mh6Lb~K_vJv4}4AnK1(aT zC6(TyO78?8rCkm8ZYFAjD2&olSmoU46ou06;LM&}iKS{SW{E^@AMSKc2~f)0isD8~ z0%-D!%tS4(S5FAaeV1xW!KcJS)(*7%$pK``1+w-i708$^3bL+{0LVHc63CbbWak31 zvn#zbE4|Zwyt*0I?k4JiD2&(H#w78o3lv_xz?nTig4YEBUfQdy4DqTn6?D z(I`Y=#IAx>&cm)#h>Zqkc2y;I3d+N-3lPiOisE5c1kmI!Q;=O6l=~hwhJvq)hioip z`BedA*9v5Zpj04ZwkXJ^LINNgk4PY69+2Gz$Zo0hZmRUw_;^h-tVft=I-)RMw-}Se z!|qgg%>ZZijtE|N26$-?vogfPZc=cqiGgb-<=z<&*DTQTcLZ?VE^r-*Qh|%vO@(U^ zKM;K)J}rQVAJ-AMm4s;a%cs=Q8BUdJl0eU*EfxlvJ8!gQOp))6h9#YL8piv%!qy6$Fi#G7R?t{cAe(gq# zVzwxw?1y7+5L;j!^Dt^Sj2c?y4X*MA`WD?ziw5ZK7#dilyJN61NV;R7F-UdC2+{lw zr#Z7lY5piAK;gV7j0E%0{4i*KXq7j%${Stfjr5g&4Ag8p-5rMp%IC*IOV=HvjrP(V zBaQYO?v8O{)Z=JGx`WxGjCvUoV9V2D3lhx3sL3#DQk6Hc${X)n^a@C@R*jBHfknDI zCK`jJJH{J>RCi1f&0mEu(VW?$H2(k+pzu0T7zyT~`H|3kW|cR+%A4kE{vk-=aXmB8 zJU<;OqAz&MPYYD9`^Uz0KM*}zZ21V{#TI6ZvgKPyfC-<82}m#xTaJP)^Qyc#z9IiW zdDxJ7fg!pJ=4_fB3&f7^AYJTWwkSLP3kgvFM^PUM=3z$;b}X#&j;r#H@lE*+r10Qg z7?_ejPW8z#n`X-*vE_G&7h9Mu%9c|687fRjB9g_BdDyZHwwzeyE%puB9OYp{P7Dmu zeX@Ad>^Mp6*aFhU4rYt8qZuT?j;%y}B$$UCXTXjXRo|nMiJ32rD)Zb0iM}m3SaT)Bmw931<%Dd1vrK4fp(?tBlO?Y2=sp%E@8Q_&w z!J$=WaAvQl3eOf-1}NlhMVa<44q(V%h;;NrFMCngl~q8l?xEG*pyjWq@(-;p7mT`~ zR4`(;D2#eT0-)hHdu04E4~%XAM%Pt&*ZKfe8@@g!Isj1^pzDln%M*`evNtM#`hqjN zCIZln0YKVKtPEMvu8qOxK+3u?9-n@o<<|uGtQLIwqg3!=wkUiKg#_R;0+HauJn(q{ z_}o|J-CO0|?L)+GQ55;4|59Q<^3@}#LwR3-wZHXCm5ZMQt=^Xi^Aw4NPxv>BN88C9vFQDj6SIH z-tz&nAI(wU#0dlRfw4_|=u-s{Kbw>NBm&T<0YKV^tPH{Dy%>BhqpVNk@!@B2@}C6w zd@T6zgE)c@vqj;v1`>eJHHZWs=7G;YfX_Eo-d8?88~XaqH?YS!&<_e9`TEWGk$L)u z0H3_AC=T?M0hs`;fB)`&>mr}O`5_)L`TWiI0b<_?Vz)cQm@Nvi2Ml6&JH(g=Vm|?~ zfBSIRZ{$2^c=-vOusi)*xzn!-E`B8^`%46_Ujw+bJ6RbUkCuE`=ht|&_*tC%F9BLV z3tIdjj`$a|MWOW~B*4F(LL~mhJkUyJs=dFfygz-wUNU_4OF8@&P8hJim4Bsp7-jz@ zjaR{$t(OTea;Z#kl4UE3fBm_s{>88GWK$WSUU%oj@9yO5W&E8}Nrr~2KO4SZ zO!OKl*PZtk}LZUK}-b)?;)`g(tvwT~Fp291bO%ob(TUXTEz{BKDy z52Jd(sBRf=|BSbE7Jm7{uPp?`sTF$A&#c^Da(vW{c9ikI{U8 zQ5YsL56uTa^L`nxZ^rAB@p}8p9{_5&JNgC6=leoS4taJ*AEUiFR5#koDQ?~FsPj{p zgT%CcXi7ST*`iDv4GFM_-;5GZV;-grhiOAI-r$Tk(6?(0NU&L*1)m}Nrl~MY@m65G*m>7 z$Xq%yP`&P6uz5!H#1x-hzxb-#6u2!@9~u*C7h8zsHzfk#oZn)cSip zII{~gVb44vKp}4{$`D%+z>uGhboAWt1`0bNe!b<#w(<*u_4atdXbnmQBW8=j=x#^= zH2x>JmE9;25) z%U=*+biQEpGD-y_W{bk;eMkUC>ktV>%mbq~PvFen92sM`1o-4_MRB0( z4afv&{p-9t^ZA+5Z;40j7tr!I2Z-Gyi2aIEL5$g=5G$!Ki2VUUf*A8a>@Fa7hYwdh z!;~^neMDin?ojS@uYzkcaAxm`z;$l`mv$#BW8=|kK;iesqg4u8{+y9KSyQ7ULL zTNGN`LIV7&F(N^Wd7$+O(0b_qaQ7W>QWQ(vJ9|ey5CIWTVACxu+~5I{4p)h%NI1d? zsHaFc;1D>xAVI|y5D`VeoD~s80ki0;D56hM^cf!}%sJ=u)aUoF>Y3iz-R?PERzANE zf6jDQRagD%-!(m9_hxoEsm^rE%!qbbMVV+q3I)TI-I^7*4&?XNZ8CT zRx-L3%tPD$x?5vEedU(^z$4xe;vK~5*MIf}(KUz~Z{<&YL9~!0Uij70Ps!B6m}`i- z8L>ido`R!A*fA^A2P^Ht$^m|}t>4_=Z|)~4p*K>2F>wnyocK5(!H2UV+6p>|llcCE z4&o%fpWuT?vHrfN11EAO9CISn%_xy;-~owTj2$OJeI(KuiG=-T$ZrPxrcWkvEwte- zDRUc6%Z2aqLyoBpB&OC^=hUXYgKr&z#=E3Vt&k+9Ho}bD0Apr^x*0KYCp>@=df^l^ zLVYlDFc|6KHw*n{H@{gR8MzDE|7WoNWw*%>96a1`eRPUKTK=0vEQ zQ6f3`b6zAuFL&ZZsE~SI=p4ej(6MM8s=TA*+L&S@hr%kMoBqnwm^U(;#%m;Nd;$we!03Xe;V?L-4KIVdt z*?x1D-<;_;r%N*ERZif_F|o4~OgJZYmLP&BcBW%urwb+=6I;oNw1s0%gt{3eLN9Pa zA{`h%8q`N3ry-G3{N_TxIp1&A`ps&;d6GHlvlOLi(W>=c~Kwpbsh4$#&2HbH?NQx)j$=#KIPKrnnY6Z ztANrj;wwZ}RK#>!;YoTqvG$rb^}=WYLdLI8D_$W<6z^IlV zOa}Eq#s-jaqu;ziGI1v4ph(PZDb?(a2^yR=dqZMwt*hFb8R~L4V5rp12&(lOqLnsO z>I3Q>fO?zX-0U|uO0@K)-+Nb`^F!Z`21FagcGZ-@HdMaRcO_$T4sCCTMWZ+dXOXc0WU14+jjDx*0*e z3myRVW=4nx^#S#9Kz+<_Zugtp{N_V`^FfLEZWx4jq#SjRC1A(5J7#ZNV)o(>iS>hS zHXnpof3ul}nt#doAloscA^?g{224rAtnx*737FAD+<4`IhsM}6?|JotFlZ$9HU zclymIB^f)Q1y_#Cf@c#|Vt#`N_*G07>g8z0CCuf8xtYufsCD+m9PHLBIrB zdEQ765Vr=>==d%N11~wUwx4^xLC)UrgS7PTBE1P+e79eI7wL88=q*T@BkE?v5xofr z)Vz-!Pd4?z(Ffq@J-_*mB#7P(1iLT9?n~^F33^ZD#!u2eb`bP6EW;nA5cF|^AZLYG zKKOFt9R)w%lCO`|{Co#p{G$XvA2L7RL(2S6HzR%;HQ>BG*fBrU2S0y+pWprFuYU6v zzxk77sj;wbB6fM$CA0K9va-v_8%UH1r6@r+xeoq&|FO1?F|f zJ_1AJcONxf`Ow9iCFp9(bcG>hx~Q8GT~T-dT?b>wbWtC49SFMG1K1F%bGtR1qlE3Bh~v4OA*cL*fkz;#S87Pkg+g|!j1Gi9wEl(kY&Hi#T|R8uw> zx_E~KW$l@=A&@d<)Xj*pG4KG&hGEB)Q6H2=Kv}1NnIABNlCQDCbe!0gVwcQUCy^?z zTLlijj)G;lYYJZl3BH^aX8B;c@*Q*q6?Ba!zXfW#CO{YOnxLx-(=`!Nri;26(KQ_& zK-Y2DFk3yT|wC#a(sxIvboU3`zI(XV#+EZWy+|V5oKq=14uX>JEn~K zpsW~_4GEZo0_Fh87rm$pre}-YO6-#P8X{8V3LEC&>l|2yj|kwYx43jThAth3Iry>$ zGDm|P91T!#bS^m?rsilBbnzn+939Raod+p%MBR)yx)L6c_=VUpN7M&Lb)MSp)gdn=QCz%4Rtzo2j7eA#z-;rtD$p;#CRCPGZWo zLCTa-HzUfPfd^zSUWkSU^+DNbpzM@@xiDbPmwf$Om_93Z&taF$*C`@ZKJ;P^zMh9= z`1BOMVhO&Si@W86>00QZYrcZ67szi+P1lRi#ZOPrwV3I82~wtux*5^+9z1|0dRrP- z81+Hd`Jii6z&s~lo*gjH3Ycd~(%u&XJ`lSPu}dax6%w;eaAAHg!bCXoC9?Scep zacdwK**SuFX6x*4&jdGFXQU~fafyixL2*L%k{ zARoKzHamFZ_l|7}BtP5RoZu~P4dk-BQIJo>$@d!Z%f>dVN#U1`ZAy@`kx7v+8>4PU zqy+J*ACy#k?6{<;kCM6zq}(AH2??Wou?u6DTuFC0Drt*@kxsA--;=_~mINctO0s+; z5z?8)Z&4FMZ$*pWlOW`7CWPLG##KVyj0ouk42~xH(DThGH zq);~_Qs^aR$dcZj#-vamr0f7Gk4r`l7e@4YGT08oE}44NNMH;WTKcnuQV2#h*&B@FcT9Z#!casGAWBGvNW5O~Q^@pgvf5A1u5Z zFy9WCZwAcWl8y>!!>cgN+bR$Gp#4pY82Y#aPh9`t@A&La2o*0u<;Sk# zJ+B{dcJ#I}&W^enWw!txkR81djI*OYvikzreHJi3378+r)D}X8v_)!DDYefMsW}ho zPec-YdiW^Owm#1Il94ZhGe%C`jF6uN4?w<{0i!{EApaT2e+-!42h48+=GPMZ3TTt( z<;Mj0`1e3bi#yHBw}~l8%*)pap<-Ur{vziW&hZ??A$iB_{E&o<5vKQw-F?_4uOJPBi8F80VB(=<9G2m{U~)+|4JIB+S_64a ztq&)7QpYu!n`q0k@crbhDg78~`m^l^po`}P<%7s3%+Z68GDp@ zZPffc16_Ro1V62rpMOKj{7^R|eqMtI@bdz8%n$X!PZ0e0gJ#E|*c5h&p zOpzZc*;j922SsnfGMpbwK5)VbisIHluAzVuRh zNa-Im`vuKDL9>^nrm?VYB6fM$B~#NMS=qHSz(GwjScVS^CZAOXIH<7)(pjaS#V`G} zZJ!`N<>&XhC&Y^Liujln>&|dYaSIAJKuu&z=;DVZh&+^uYy~M3N!^Ty^uYr{x518y zq&|o|5=0&mG>e1g5XqunmMp(9W3U3fJRXVi}Y8;oSL9=@?WL$Xo@*YP31Ar#VZn2 z&SWZ&g_NnJ?q8*HPNc*zON>rLp$YmPiWHjlS}7LTgn|+ITwl zeLMp5gJ?`4G3gQaA`g?adudLD)ji>DTO__EvSH~``Ye2Dp2yd&9al_zTLh!}JrSV^ zYaH6TV(IsJp4gct1`sIf;f0(7YphYU){+c=*bSLLk891P zc_Xm+_66QYBS{fuPLFalG6y<-2IE=?9{{w=(r0cxT_bz zXo_=4GN~m-6q5(GN{mC9q)llgCD;-L!8fa70zlGAe=1>zF_kiOi7|jHl`18ZN*z{W z45m3827+EfrM?g`pNp9Pj+jr|m3n0Sg``S-ow6BDW4N@eO8pN>Mr$RAkD zV(U?~*saBmrk(qsq__({676CR>SEt+-Ux&Epe{JHeT)EaqgoR5ga>xnO8eLBp=XEjXO3dFw9-ae) z_yJ5$Yz-hXbig{#AD`ESUI@<+<8#rzp4#8!jTp$*Mb(V;2Y6tt)cvbiPb7Y;G2_@( zV#oYaA6SPL6q|z!%z*_qzcrA@2NuY$@ml;2C=mQ!MEnjeu=y2+0E|D%Oz>M=K%r{k zi7`|6uVS81R$?4qVjM?Uj|a|qW%x+5%$!|j;hYqoT}I1$-*l31CWic3DD;M+7}roYAtmw+DHEdMcI__A|{g0{1xY6`e%B%Q**XW|G6q z5@QB|n~5CeBZpc$fr{|LvUqJ7h@=80EK7obGAq82WI_`X9j@>My9)@_iHwSxnV^bY zih9BnUBU&62K9mPR3KbrBaB@pj4sD6zDTfr2E~qDVGp|!jqsu}OAF#{YIAIAV^@*M zVuuOlrZ6!xv8&1ZVwx*DCSq^A;lYK<5)N~X9p+l{u^}j~EAFNW6maOE;S+r9I#^)I z7UTH9&WQ-D8%X0VH6o|g%~kAn7<-zPwa6Kt=h>&k+xplNBYzwb^U*rPQ*3^KtyO>F zICW_DfZEr%0Qhl|!lvkB$U#yk4k|izOpz*V7Y_S5hy64WwriX^2p(rap9Q+Z7@g>3fNlt*`<2oC zl0Y{!P95UT+7ow%*X}jpgS(>(y59u4Vn!!A8KA?p6w3GyM)!LH-H0&Jxs@g=d=;Apw$@aR4HJI?P9uUtI`GAu z<=8!ZX?01^f|D!YjAJ;WlL4Fw45tCZsh5B=F-{$-tdzZ=r%5}PX=^Be9nHW*Cj(%U z7+4bq)+hn&1e{PxjEXpk0Iy$53PzxOVhzfpeuSksrG%TJ%jIvK4rhb=W|piu%Zm2p z5&O_qs*Kj~Jv_pyIN77yw>g>68EsCu1)4SlTi@6UF*iqXeE#HcRKEn=V%#zGghwQ))jmX7pGjFXvr=Ay2%q-qI1 zmAP*N$HiuAY^@qSElks~6~R2QCRC%OL$8@QNJw7P79vozm;s1R29qCKhO-faI1v8u zeO+uV5V13%!kL)Pj5Ha1-5l-+13py=bWI5z4Z`8Vhm6H}>;{aAlQF>d^_ z1NlhF&@$x&Z6AD+%`FPh=t#oH&E&&JKIq(42ab)pfaCz!I3Sm`*A7efwm8vqSfowQ z1E>IEx1kXy>=-7BpgkdjhR*3c4?>X1JZymro`-z+EH;DK+VgNPRAHJPN2;U;<;}!0 z#RU9t#YwjNxc?jBM}I~ca) z;!_)^5M+Y$Ya3@j_{5i}v9)o2LjVcBqufZJQf@^M5twgnFhY?r(el4BpezsV6a3?ta4C;l~wJ0xB)mgVxu{~cp(BYRK7 za~pfv%RczWl^rwiFPCI(8jFHH6v2p&Kj4Cw0wKtRjvRR6rC<$L>+8IqZ!dC2O@fAM;!T5IU*zLSTb^)OpUQ{`D|Q5kO{7kjjI$si_Njv+H;q0 z;Tn+26d8djsy^Vtc7(;(QBY7#g>76ykO{6XHm+kB*F>{q@xP~N3Tz4UA=oiyA;<*t0Jvbx74TVX&cN2jJWvD~B6dTu3(tjG zU|x<#dvUTxz1t_1;#8Aud4x%OPCMGjxh^CCYVRU1!F!5KJhDa*xHy! zi6CRdZY*};lcBbGek3nW)*!J5{-;%cT&l@B@Vq1_YNHCagt-(u#w-MxU_J&e81q8- zEH>w3YhylE1UX*pCSey|47JVkw!Ao5gTx;ApD>@0YVrekwy(Aq!Im&j#*Q%yK_-~X z;es(Qh0kL13~bHQv9W=l2z{IcbX<}a`#fG`(xlD2O$4ROU`Fs}+wg=S6L|A%cxS;U zUMh>NjqD_-!X${(2C#banZGSsL|~Ol?QLwU>4|*W=v=9$2lHv_hEh#W+tbv|rTS!* z+9%cXp_ZTl*YFD7Rv-`JZ2@*XtwN9qZ%g5Vr*##47Mtf_Yo3jbP2MtsKmvr1lNNiv zaxrr3Zauq^E6|+>D?)dsjZO$MLATOIcOiThn`^K&&&S3_cMkMnLM}cAX+yWxWCW0O zW{Z=p)gEDYas z0~4a`avPrzWP*P+Omnnn<0*q zj->YK@m6T!WydmzQLKoOnY@S~u6A&wIj7@VBeeKdeBwnUzPak`@TjqFljR#m<46{XF8+)kYsgPAkQ^Jv>#Yb?%Y4xL#2u1fB zae}d8DgRy7<^X-;W*UXW)qWzR{Xr_n|ErHnl!f{PQ;0~d3gTvU)OVreSFv(Ob>SVQ$(%uD8iM%r8uj3h3qoLq27dWKD9 zC^{L`#e6*Srn;C9E@}|3*sQ|VoJX6vw3&^K#l?aWV^N%h2`=WNhta1vxu_*s#L}D= zJ{jHcaBS?MdM*|xb3r3*E(k^v7qJ)~!8rNgusD{_upi9`K?a=IkHnY46R$Y*h#dUH zfC0ZhjIDVpZ5GjH0X7ytvE{G>f)&`sNtxhjDSD(j8!9JPXOKK%YtMl;yab}~2yAQ@ zdcI=k(txC6iALL;5wv8^&a=YX#}kJKtn(q~Iue3RIJ*!o;AstZ%o+8;*}1?_Y_7!C zTtS=Vv{{CY&Dlj_9DRQvPRayl=c7k1=^F)3&Q_5;Vr%I;1>y4`3XjCbcHzPqedQod z131#4+SniX*Rk(v@``BmMTGQdwwAtQkW9Gci5D-*E17WmRK;1Oj2%&~gPaK$f=mdf zk6z&EdhD2R>VxphfuY#E6kGFR+FVGRHQ3mMuZLZnq!!aTp}tq5N51G|8)xoUkUU~* z>H7~!xrawVZ@W@3&YV!_WKM3eqS!^qQ4pOz!(mQ@;4gA=z>Nk{Xj@{mAvW5A2_GcI zW(RD|1F^C4Zx;@r6DP@vr5ghHcFBeSPBRCDgOG6Y*7KJG!yzdFRj_Fv=>!S0-GR-e zm%{5?+!T-(p{F;YZ#8-1G#(=x?SmeMca#nr>?0idaAlNFF2e+euC@syJmz{&M&`9(?kRSmwbvlg?To7wvV(Spl#ys)lMwumQ8d1)dn%*cQr)Ex+F^mAI#ttlT8H6hcCr)TuGl;Z zTXP(3#?YpOHX~^>92=24bpfaUvDlBpgKq3Rk>h9^J{sFFu_it$jN+P|@@q}&J2m(x z(BkA20utg6;jmzads-Ly1Lz{3oRAueT%15S&IxfsK^OSeRsKYDJ(1&StBc(-Td{Qk za_sMCb=b-HDdoSC3k{ba`kLt`J;ISv2;ham2dZAg;Y3HyY!a@_=+a}ynu=r zYbie|vrCF5D7mEMsTkh?olI!BOq0rs#Y_`Z}(n^U& zH?v0X+0inEvQ!^PQ%R)*C#OSK=k%~3o6|8(Jsm98fy~+gp(d!@jiCQ`RvI09F7+p> zo^BbkImOe}Q_N!Z49swwfe!ZZqdU)ho@M+q)%aPg#$Vxvf3F{6v()%mtSb@;QnxH; zdmT7Y4U)xmg49()wn5HTgJiL~66XA)Dq*e~Ka1-md2dxhr5YrQbs(G8wI=+KUjfsARj;7O6q9SbeCR z@{c0qxG%3bTD?I!z6d#cGll|0$AnH-y<FkVb=`WD?UU9DHGUTBCRl>pTZj7DYLG0h6Xf1va-|w1i*+F7b9deGyl02X zIsd3qJ6BB*i**Far+H1%o+kf2PxDr(L9$o}a<3l`=cz%mxK5CJ>v%X{4U)w=kbm>> zu$mz0V#`_FTLi696U1U2NIneIpUwQWPa$;y_Bsm}s99jK4&>ilCKvvr%H$$7K`ho0 zwAYu-i`5`mtONP~UoBsvW`V^z7XId1zVshe%a^GMVzG`OxgzbYtIf;RAX%)wq`zX1 zNY3`%`;}_^EUuGe-GykjL0+W>$zmPI#((dP<<)yMi}ZE!Y<{eKjhY}9>jeZICysL9$p~3AgM~C1iWK z*r>+O;yOvzRYJBwZc>9}ah)J_m5^ANQ-fr2ogj6UkZq80HAoh#E8+eF?ZfRsHAoh#N#6R8BKaXTeimm;a<<9kGMwk!DwHGURnOmem>VTT$di`67Q zxkn^t8~;;k{4CCx>jMKKG9*wdd6Yu~p<@Hk8@sBgJf}?Aotes@RAxNi*+FX z=HuZ%1W6ZL&Z3T>Y+q^aQWM1DIzjHOyXTkHAX!`|$i2nnD{7D|)`9$+OYPNvRH?nD zCWys4g7*5-`??w=i*+F7LA$q(huvzBEUpve-Z~!MP=jQ#4&>i_JiJMebg|_u>IlmA zt;Jhvf>>N9NL{IA8|2$+kSwkfp=d^rS|SWs?^?76U1U2L3@4aeP0cd z#X6Akpxs-?!v|`REUpve-Z~yWRD)!(4&>i_JbXlubg|_u>IlmAZSu!zf>>N9NZkip z+5Xn!Cu)!^t`ns0c*r)BpQ=H!SpDefvpuSWY`>7_b2WYz*GaOj60%M57iy3!t`p?m zs)R4qAX%)ggs=WlmGHG1Ka1-mSyu_!zFq%D4U)xmg49()wn2WY2FYS|C4Bdfs)X;= z_*q;h$+}9&_J#QmYLG0h6Qr&ZvJLV_HAoh#E8(X-s)THxf`3-yXK}_PXB*@%YLF~e zll&HGUSW@&ERx@arxnvyK0EHGUS?StPpUBHL^7|I{E^Tqj6fC1e}q zA8L>+R#$@Oraif>$Toh1(C{DJCcRIU#dVUbE7xp;^r}I!SWR-y9+8~wi{V@~eimm; za<)O%Q-fr&n&kR>L~^!^q=6bgi|ZtLZ>?z!)gW1{Cb`ibk(})!X{^T2;*3eoHpnJw zkStb{oVQ0LXZ!5jRE?j-b&|ZdPJGSOAX%&?d7nKZIor!cb2WYzXH0UoD`8(XNEWL} zZowq~?@#}UV+pQb=tchSZ(VPx#=&AWj#iAL0lfdYKehaGIQCQHV6hrUYsPUja43HB zKt9CPE&thm8`b`5{4CD6=&}v6jT$72bs*)Vc-_mt`DX z)HqnI#?h5=yq0Ag1!^2DR^u=kM_tzgy0ciePqp3D_*tx5==b_X%Ry?8EUpuz?sg>G zOcts^vbau=duzJ8t3k3@U9LT7M8^2DeLK=qji1GJg4A7OXB*_fYLG0h6Qr(OvkkJB z8YGMB1gR_6Y=i8r2FYS&x#BkikHHm@Cwwfn^kac#)Z?ei(c|o<5k1~+dZUx(Q>=lAUeZtHjGx-%|_8VcC&HxB)i!pT5C7+q6_S1)95L7vsrYp z-P|X-#BMf^o@qDtjh-){P%TkWPly3K9|qL13mV3hw7 zkV1r_{P$|q%#ZS4RZ%k>ea^P+6y-1cleBa6Ra+W~zG*kRMESddWY9IrUz4I{L6pBI zLrpWvUzDI`w5}~pP?Rt8s5v;wS6b8@66K2>Y7UL^^#(PIqr8@n zi0~1@zkfNA_{{JpAwRc&5^^vOQvCiUw&r29iPEM&ZTius4>tUhkl~?d@o&>_rQc_b z4WeJ;qhY{y6#gH$92@^wnh7D%OnEZR6=>8&Guud-XVD1IJQDkV zbh6=6LU=Gu2mQ=(>uxrqJ6qxo3tr*elAR|MYTCr(SU!_p1mR9f; zOP>!Q9)2B_mU5frq>*vQS{0`ZZ2z=0lRGTv>jNX4%PW?#IZzUtW3m66*c|8PI#V`} zf>S%=IDtpDO>9B4IK?E%0enhH`NeTjkmLac*>^7Xp0IuXGQ{~S!ctjtm1Hw6{rpr~ zzqFn(3e$P)5S$O?iOh)d$%_DZqkOiYW=@pXQflT#`FN*hy(m{THS0%tN~qZ&%5g_T z#5pIoNSsV35SY>&zFOe3Z1-$hVx>x23xa=HuJEt ze<=NVn8Znn`lH{@&JFZkh#vhw`ioEzWRF!|^GP1DwYz8_`J{7VoLth0kj}|Dd}7Y+ z?C}&{-{Pi#Ja>5-C7F3OW(^x9yE8O)%~R~e^?)Pnpjw9CrcoZBT#?c1Rz^9_j3D0) zIaALmW<>qlZ~;$mV#m}|AJji|OtHBf+?dN~vxGJ=+AOBcskB*yjXfFf2q*7~-TT;u zS3=DbXssS6w1)6(2(fa2ck*Me9ORDXK&)Y+<^kygxQUY+S}GEg(XsFOkP+q&VIbz2 z*8QRtB#zk1k7+bPrqzsQBGx1|y^Qec9N^t!T_^}PvVETP%hC-SQ!y^5qc_W4+u}|T(G$+C^(ES`;!6#ix zTYTPw)i@E6riz9atXR4wNEAOGh||p36ch3G5^R$KtIdIMS1j-twIM*Ga6u^P{}NFZ z^!xg*fiJ<%S7bu9v0~|3CMLJXvVfm5AW{jPF)%ST5Pt(P5@QeOerH*ElC8ccD{rY0 z;Tg@Ss(*tE1o#Czo=57Vs&4|;VskyV<~rJ}rOmapxtcatVq=%|@500XunXS;dCJuy zB`2SAipL$~!s1w5o&&%iG<;(n!^Lwa)o>4(4sTKqH|)>r_!pPr&f#1aKHjR%Ho#?& zuUyZ6zk10V()O`DrL8VsUK- z_J$YTP7xw@oCXw!fGYe+{>3vfr$5dp!ma?e5uC(n!YPA0$UhfFWAc47x^b$A70Yf9 zIKK%%wUPK8cq$V6V4`xc4<;&^#PyOqc$!c|a-Fnx<@oyE2^sO1=QOZZ^$nzp*cMIE z!Lh<{F`zlR3^ttlU|J893a<{J`#N#RMHWEsvVgX58YBU=E%qY|yFTu=hP5WRNgt_G zT@e^8#qng;h8NvKqaya${n6nGYC}$l#lMg<)k+;Xw}o5f!?eO6y=J`BL-R@yv3n>aT18XSQgui4gdIhC#-P$GHkYCb=FYJek;WuGB}a^!azO zxdU;`$7%BzZMI`$=UNE6v|QZQ6g9JXy;0f?Oe%!TCPt)NV)dFj&l`)Omgil zJROW3=SqF#N}p{Po6jST`7CXoq0LTg>|Fc6E-hF3`kXRXa+JuGJleUEV>?&!pO)*3 z5K^xFu;W~XAd_69!c%|jI9KW;SNc9dvH2R}n6J=g7j0g`#?JLn*rnx4e-fn3l^i8< zC69Kln$#|lrQ zvEy8+k6h_H55?vWh+}?7n{R0I6*hLR<6xJTtKxVSxsszquH@0ql^ol-lK-?^e}a&5 zJqkO{RR}W4^=RQ~0(P7$^^q%m&!pJ=AL5w5(dNIj`57BK*JEIpmaF1;6}gh5M6Tq~ z&XpY7xsw01Ts<2E!ZPeQS0TtG*As-NO$ZU&MWMR*GXKUDb1UKpErD`EC zw74bHG`uK6qaya$^U>ksY&ALgi?cx$P)E*d;8r;sT`ceyI1Q3=wkU4m zbe(GtPaWi!kQv<)3PC1o&lPY1PnTiGoKPQY5B)htvDqDf&4XxT(xxjm_S$o$7?!TF zwrS>zhZC1$@hGAQ5j)O0ibFu%XcCKu)1O#8*cHHHO7QV2IZ0hSXr2;_2Thp0c+k|? ztJ$;s~etwvTX{ zS-aY4_7z9?6L1?Rx2Z??Xvm199ZmzQ+7BmP#J1Rp&R<1FMNtn59&lB9F%LA$w0z+$0GEKva#?h#VJ@y53_&9r!oczVvpbDrX=a=AC zIUA)G`2RQ!l5(~!cEJK`597x4y@IZD?cu3|{8ciewMPgtS$lTF1w6fu9dkl`tUb5k zQ|Y4s*IsHqg*be{FbvN1t#C1+}*N!o5`* z4B>+wCa?0-W&Xps@GxQfGJj6`GAsD761LW$`5dsXFnx(lUkbztF?}uzk6VKL0q?iK z%?wRo?h_2<7#Ftb=rN3@MpJJC??r7UmCUQDsGM6puBNhT@{DrN3a_VOt|xeL8&CZl z<1&ZoXSljwDBYjz;=TqtO=4C0$n#typCKbJc8Pqd-u)t1 z_ba9Qvs~Pt37safrMk#mZ>y#IRW9z&arJSz^l^!ckBgwwK)k@!{k78lRW9zYaP_f4 z`dIJcV;yuFh-+Ql-zwd2ba8*PtB-r7kGu6S?$o(3jN75otSg51J}AeQSJ%$2@hmqy zMs6-vu^Pi0huE>Y8Cc!cdK!xL4U5rs3F%>d+^ueLA63VF%suXNGVU`l)Xd0Es5DFL zlTc}?cpgdx6)!;SLdEM6(kuG7yWHaLR>ytAJ?i5;VlJkd3Bg^WDiCGs@A`zfyOtEBr%7x#0Z(A$PG|w4)g1w(o%5?lnN>~LhM4t-4fCr z`nb2b#l1%zcZ+-6Z8Gjw7;30^04gOFbTWQK9e2BX+$Uw+$K9MirFOp4-T8l{^A}*K zN$NSbxVzMGUv`iCri}Z#oAbBS&fj)-9zMXnYziKbR7y$bEkAUcggZi|oJGTE57nUB z>C?-r23OY3#j_5t{e;BN&pHl}ddIVl06*(6yq%y-E%;avN}Td~NzgrD<*5H8(1p-x zKzD;m1G)gJk&_pw5qE*oEu+p-ugIu3l)8)t$&3zzl`f+wbQ;+Gq0++c2c;YAK2o0s z8*GO5ZR9mwqJoCT$BE^8#{lVGLes}ed5vN}07|Av;GRTLC*AG0UOTAX^5N2H6tV$QQ}TYg{6quXn%7)%|tS z{nak+uhhH0T)J2Dda2Z_c-<_+-{KN}19Tc*Z-h$2>kTrp8rk(ypN7ov-U_AeD7jC9 zz6VyiVz>)B4YE6AWHqweq&^K9j*@@L@Y`L&Z-Y+5*+WoikUc0PtC8I=^=Zfq@8eMF zID1Zleg;-L&UQklLH4AKtVZ^P)Tbc>XRpfeyIjJ*1f7Pn7obuiqbt7GpwuP)j*R@K zOXS^p_dx%t^zo64j}M^Jpnp&A-tc|~r4IeKGV)h0k-yNp2l`*7kDpOrNPa>K}h%I&Jeka`8=CQvFM z=RxcOc|Qrc1q?N~n!Ckqt&Y3Dd)%Om>(j^WAmgeJ&I6@h!AA&61t0kkyYMkw;yMC` znyM;>N<-BUsNAM-kkl(6kAPAEc_hRxkS9vWN5N2oYn+U$rgDtbD{vhRr2^M65WC=- zDRGs`qT_E2oA#Z|V8ZL25d5esj zLM3h~H%OfWlenccythHAz;rvrE||7SOj}{7q45Ez(%_1F%{WxryYqXYbmRCQsdwaK z--tc}r6Qm05WD2_tjyy1jj6*s^`nlqNl&+ZQ@b!uvp_oJD+@3o21~j>4j&j2{?vl#vf~iQG=*UMwta zRPIT|?z>3$om|}KL#IhBsERDs2)`<_OsuDjT<8+Ho8EnatNQ`cebmK$f9N!c_0vc0 zBO|A*)z*WyUQ(}`(Ge2aFxWYkhoo9M96AlMp-^dRX|Rl}MmA9DRme&uvN5XY_4wIm zi9Y&By?4WV6qJf3ay-Ni4pMK)CP_$T`nboq#XUhCcd~ojIWq1n7-}YBCRCbA>*D2Lk$&6q0&%s22^e**3+dvttJic z*-$E|S_!cWRToRh7r;=1YqgB4K32|?dIhdapj6m{!1VW^?|uYt;q z%B!Sa0r^HK6_9U&*ah;P67p>@)Zp4IyhS-IQ9TL*N^l=|`i~FQH?o;k@cgeUf!carS z^H6E1cor%x6)!`npyCyXU8s0RLV8mlceh*IchzybSO5+b0YLfchEpCoaIf=OtyG&ve8Mh$}wT$Jdoi}xN zzQ1(d3Wl1bTDZk+qmJ9wJ+4p2ZSUsXuXY}Acivw*@0)Cxd`$?QCgFpjQW9+#J)qJY zrF2awBM)$ie5l_2A+GL6N%zBD+z*3Jli1<<$U|KtkC&0hxkMhLcVFV_ev))w=HmVs z=roB<)J5h?r*i3jii`UbTz$-yK2CJ;Q30I>;tW^!HPZb_F77K`eVitJEYibRpmSju zCqt#FZNs}5O2rxIbckIRuN4x~nfka(-Qu3Dj=R!5?jHoGMsTEGJM!2d`KTYAl<9O`=mZCyy5KvrH+_h5?K#e>4+(WPBWX`pwe(w09D#! zWieaeZZ;-J(50}_ z&Bj>hG?b5)k=4jXNqrhJOvyAEezHsWNziFHI}R!hvSVdrHL|0nJ`I`SEr(LaS)~L$ z8&*2bWvgB_FlG}vJKGKuYC*y*rc2%QGo8mP3`&X=*( zm9R?cRoK=_Y}dd}hwUopG?j1#R7%)%cDo)*-HhEVBj4x}`3AjvFng!;ahr>e&CqGk zZ`8XtymvvVLw~=Fe6LI7d-U#s{t4;hF&7`(q0^w>rgLu?4?*Qtu@6dpT2&a{9Z>2L ze?fwN7FN1~c?LRVRT#!j8ChMgPfC3nGH~{~4F3x3G`#H6M}JB09pCkVGBs~}r}+(t z9f_uXfc~L`^qxNMJ8p45Qpf$+J+3EUU(@~$Lk$(bLZz9AU!Za;k)NbKZ6fgEgMgAM zFT^fXHIPx)>S2HLTQ@9VrF1XrDTJ^YX zK&gP-5n>m}T_ogAFx246mvPm{T2Sg0xVl2Az*PXT3$7xGs}Bq{RQ7^O1Gy(uZd7)c zdIjYEP%0oF0kF7hI(h*BBUTaFxioYFs0w zUV-Z6NIL+paJ_+7hf;wn2C)mS)e_e#7;30I2PzHZv!T*n8J-2D8_#D-y&|7AP%84d0AiPX zu9f**1w#$!E1=SXz6?q?(3eQP0`zrIDnPG=*ah@P2^v4brkjKtp;G2U*SVY2aW}ii zy<5h;!_E0UYUf+roo|!Qx57|USr53yeMB91yL;RxW!%TzoIj;@zSG_L2h#bw$%aW! z#NLKZlkl5RDQD3zc0(l!&rw+PZ6*Gk<4YO&GndGp=-q$h>i!q${zn)0-$SQK>|1^0 zuU#X1gZ5SAA1;x9*Sr7K)qNA`zF|-czCKi%S;>V;Gb@HS4@$-1-V|b&!@aeH)KVXJ zU$?mXtK+tDj~kM4{V>$bV@IeoRJ4amOGQ4E3M#@7yHIhEgjAr9+r=$zp*n7N_qd13 zxcyM+A@k@fO6Owo>$o*37zCYl zO#yowtcEU_S2gM6$+I1=7s776nl>gEx@x|j930-oK1mMgqPlj)Ul0z0 zLL~1%CjSViS~{2qyCLPXE9O+xlvg=S#UJ#{B`-Bq6?11eRO0XU0He6ThB3H617jc* zX%3?HRm@5F?k_6aTT@0APL(^ij2u;+2rSF#RZH|5*IL7v4e{t2C%znhzfRK}z*xXu zXml;il1ny7m%|Hfr_*dDJu@>rK@2_(gFS$721CfnSt6k@#T(Gsh9z-kfHc8QTr z`VDUfQlvtq)wLrjj;L?~%B7XlNAeMs4mm)EA+$jT$v|0ZT|p-a&+_`7*hTo2*IZAm8Q!^H02?|E3LOqjwL@4P?6B&duyXRyz}pK7 zgzeoYDQ0t|f|&atW^Wi!%p!-kK5B2UI@Dp+KVjue71w2?I60Zg!H$6g5(AxJ4et;! z5W>VVGt4otI5E%}5x7P=td2}rIo-o*jKgYF!YakrQ4XuI39A%e$68i7-ZHfKVDlb_ z79DIRE5_8%U>ylg0QI zj_9q#_(hKK^U11sb|rr7U^xw^v(f+>zE})*hTl&NU*;Ho23aMOcshxaNkqmg9D~kO zTAb&wIEO7}SIn5}pcJnoC9(1dzsNCoje79;+QFAO24758I1?Ebl`Z*%a*e~{O0pP4 z2ai05UrwTl4iOJp?-+D_`k?E?pp>e;g$L0o;#Rc8DdIM?ns`WdJ6hrtaR*xB6mh53 zqME)5ZJ@_%;sv%En#s*1oXYQb1Za6u*hJzfRJBqXyP2+(y&Fk`1z5gpo-TX&{6BVm zqUuY~_ROiAR&Iy$cn}U#eH z)HG76KusYV>B4r&33HK3MQLy|$Qf>hixo{tuR%JHtYT2%NeX_OA$ z3R0@zEhj}fyk#WTz&pJ`2cdiesVYRiqbN&_jaWXtm(v`k=M1 zCkI!}ebH*gt$t{=^w8p1BwPJu>kz9&HPQoZ4=(QH3WM7u!zd)_uxVH{<$_LUePA2{ zjUaUxTB7ETv|8kEAdQ?`JBM8+MjOUqq^Pc$TvY>=!>?gPNmDVm8W)z1Xohzv$){J8 z&z?4Na`lPHwKWksQToTAC5Si{EkQ&XT7rn<&=N!(FI$sj>jc@Fj20)8Geyd#%GNZg zEtj(CQZ_@%W=dIwl+BW|6J=|*Y|W8&bET|Ow&uy!Nz$%L%Bp3nMz(6D-N{lmU$z!V z?LsMABwMFQ?Wt0BnrtnW+S8?sei~A+c7|*%k#?|o;A!TRF)=Jqr zN7|h$WvgWCJlQ&5wpODhW`B*8T_9T*O6^5bcCl<-B3qYAyUV2Pa@o2Ct7PkH zsl7(Zu9dCpq;{>8T`ybfr1l0WTQ6HTO6^Tjwn4UTmaSW)-9{sD!Zo0Q!y zTX)FTozm_uDZ5*??vbr6((Ya_vUR_-dqBz_l&!5&`;e49EL+>8_7N%DE?bXE z?PF5*FWGurYM+p@9kTVL)IKF;J7w!>seMMu{w-V2%GPtz?s+MDLAG9$t(Ro$KWK@H z-6dr&%hoHh^{TXcP0C)Et=+QqhHSlwmhk+Rl)Wum@5t7>((XMedtbIbkgX48>m#&; z=Z~fA6WRJywmy?~pG(;nvh}5GeI@O_ma=bT>s#6SPTGAhWk1N)kFxcXwEJ1gevz&J zO6{*w_M4RbE@l6dtv_VTbCaF9ftFYay|R@fwYgGOPqykyZ38K5C|ixBwy~5ok*z$b zZ7OBWWNRO(Z7yZ|%2o@hZ7F4~q-;MaYb|B_OIaJ)YAdzvr0f7GJ5b8nOIZgg>nLSD zDf3HNK+1wr7Lu}jDGN(kCn@VJWf3XsB4u5rtU$_4DeER>2gz2UY;~8d9%zYb?TR{?qUb18OzJf+esodX=8Yp|$~7-vgpDD^$YGAFPP&^jj1rQkTrU~MNRlRB zvKhv35{~mMw{Lx8`POyo(WIzJe!|I@cRtK2!LBCvAYj}?& z@i@A2PO?6n#Dik{*(1v#uX-no!P4ZaGL&V1}Np~_w zk)n8V#q6XU#*uVX`3!t=sEANPT0xCfmGU9WNRE>#J%Xh8?5uohO}QeUp`^BNROHRn zFp_eC3-4UuhIa&sN7c?LtsHk^h4V4K;T=ONC1>e>+Y=BaLExSxj=mIw>`aQ*DhSJm2dYi%3&D z&CVH*spzTG*(7C>tje@1dL_wIKOh%t6CSF8kqs~qjNFEnVB~h$y2Ebe+-bMGcgfb> zvUQK$%GqMKy!YCzocpX6@wy&ut60Yl@vO+To^!?ud9heW+KTECm6Q1(&an<+V{KxT ze0nFB^=nC~T4AncZ^^g2hH)iH(AU1HViH?N>$Kj zNRbwFCrNcdcSC6heT@utL0=)ID(Eg!qy>G6q`IIVKxqekj|_D|-yx+c=v$;n3;G60 zbwR&`(hmAL8R~+5N=jAGk4cdh^h1*Bg8l@h9rOn>)CK*Hl&YZLkRmPUS0vR1_25^& z?V$g23;LTb=zo<#e|8Jn$Pu&w+Nqh!&l&2GG9^>~oFRu4X_*=%RjyQxNmDb!d6|Mk zwerT(DcSG|d4E!*WwReimDvPIqgem_?1$HX=XGBPHdn9z0n(+e z|2`p1UjI9?FnRsQT=s-maM%wm!C{eX^_Q(fWGia7at^gx#9Vi@wagtvN)>Y^Dbkqh zN>U|reMzHWt~dKhWA0!!S2Nd#bg9hs5<(|)eD!iTQT9iXN%CFX7QTmU!RI2izf6OIQXJxUOacY@7RG} zd`D$yQQ0SJ;~!mlYuU8gsV7dVoHD((dg|nw%Br;f)XDRzYbxiKn{y^tW!X9KSXUI@Gr{7+z4@a@2lfsX@U20saW9Qrh{F7#R8z0l`@r$b)^UJ88~xG4Xt zz#pNn1IzNi3H%)VHt=fbyTHAn?*p4cKLySUE)Q-EtqHyvS{HmIv>|w5=+@x!(5JzB zLZ1hBguV%W5n2{n6}m3;OX%j%?fG|vUJpGP+Lr%(=-m8Wp||tj3f+?bPUyw_&q9~w z{}6gS|F=*)|BU==^Uuz|B!6Z81Nm$6cjjN6zdir@{KxXw<^L!DhWtD8@6G=(|DpW% z^PkLrIe&Nlr}=N>znlMN{>S;TBQXg%`?mD?gN5^IYM17%&0ClEb>265Kjg)HXZV(a zgfo3-`BwPO1{te;Ye37zzDs$}dk)_1*coo~JGM&AbCM&Bmit-d>acl++~ z-RryGx7GKsZ=3HC-=n_AeNXsy_@46Z^gZMIx9>UMi@uk9yL_+ucKhD)z3qF~_nz+q z-#5Nx{^kCa{&W4S{TKRg_TS}y&Ht|dYyZ#wU;Tgh&kU>xoE=yhI45v!U{&C}!1;ko z1M34f1vUgW1vUq63*3%Lx+`!urs)2_gMqDqhXdOJj|8>{9t->{@I+uo;HkjQz%zk= z2c8W)kLi0U@SniTfmbn=y8~|r-oezqkBR&w@M++)z~_N40$&Ec3Va>-Ch%?GyTJFD zhT!Jl zt-(8jcL(nYZV5ged@=Y^a98k^;A_Emg6{=C2!0g&B=~9Y^Wc}kuY=zNe-8d0jD^k! zEy0v853R(suL)fkx-@io=*rO5p=(hD>p~k)2Ae{+hwcd76}l&MZ|H&0*3d(tM?#N< zcAzkx4*fgyTFZcuUYl$D@dt|3Gk~52bt^1fonyo-$;p+oyUm&Ap(Q~`y5V~jQ)^Bx zhX9XcFv?g=&7^f+R3?5BDm55+A!VjXmb(hn9W`iIZFVN;JnCjBG9L4A7l@j3o=?^D>X zN8iHkg*_ZXG`klT_U_%==j+>}um^VdcS2+0(C|!KKK-0`%KQHBuDtcHZXCJk%3WIm z;c?rK9Drwkc?~?IYjqes8x;SXe3OLOE=WzVadW|y#W~rX4Vzn1>;`z64{-8Mc5g>K zo}M%Tj(^h5;+|CGs-@{LLQ~pV{F8R~JswXhot-rYWOv0xkLT-msg?LA{aN!snw7w| zvVU?SWCub`D&UIQ!YgE2r1^##dC= zPM+->S5rH!qOz<M^HPR(s52Dm>-{Pfw3oJ#98rKyRaI71mCviJswtXRg~_k+>|5Nv-IRlkhbCY`dZ1KV zwvTPE_3TDb)4w+3n_?kr)5SyESUuciVBeLu1wz(P$YM3TZ*fuwRMLcsxzj4=SNn$J z>m6m?3(JPhojSXAS~;5C3cK~_QCNt5S?$!SnzE^tSPZLbzzV8r($vbi(<^3lo9St8 zy!PzsQ(hZ=Q=XIqTT!=FslOrKOakG>y`uhQhyYv{v$?SA+k-#OHXVGcdHvDH``jgvcg zn=MFnfNRpZ>hb6LF#aP9?`n-d1>@=c^(RlCZ-u45x2cy)c5M)F6*Wd-p&7sbj@1J^ zx!&pyM$3*yGkP_AVodd<ZX-dSWASFvecS&`vb8 zJ`Mc>LyzF0cF3s?b|~mYG_pwnHrrZyJfWnZCnSwb&_m-crg87%{1f{gYxI6R&N#wv zG^3Yt0jeD@F{(R8T|%So=!VUCxH4)*qjHTCFzVc-P|oxy7+!nniPi6p&4;a>Am2oK zHzbX8PCkvqn=w7Hw|ZdH4pW&(@4py%ACH`xj-W4^_Z1c__vF0e=k)a#9Pf4~AVy!~7$$nV;{ho6iGAvqt#KJUPtC4h_Vc zJ3X=ZC~QWDJ)Q%YR4)pS2GZZlQr)BmEW)^}Y21X-*hD&cJnh8PTjRPWjdMn%k$8=$ zCss5Dn@2J7z@(9F^AT}++L1pP!>*-amB(V!2!)e468{@AniV*QIpfj5>uBKr%CLDi zX<)s4quF83fzGL*foo~ts^hVF07aLG*c=1fh6!jYF*NFW8ueHeHtqY!Q6Q#y7&slH zQem#6apP*R`4Qt1M?Q`FhQ?LTP2=TA#JhpUObs5W!4irYb7@C4|1-8uVUosJaTGUg5xl5BaJ(16*gZEaUQV5%j%?YPOLO?6OC+o zJ~o?%I!6-L%aTXRnJB}!%`~pvYHY&A9#1ox39qrblhJH_Qi9IKnyA6+a6Peq(Xd$< zmRQXQ=%bx!0#nO*3P#;VqlVmw%~d#L6J>dSXQSE6j!{lJY258JZud>t)Q)woD>Uxy z&ZsdFj6TK_XZLapx`PI7+knki7_={CmSen(5jRfo-~x8ijMr_@eI%$6c%Lr+78eIJK?d%`pR@ba2rLnhI3b2TF1 zUqjDji2+9pb4EA_${!L0^mRCE4ArI1aorutZl2tFSYYLa_nbMEa}&!uO+CH`0tANv z@)JH>L*9>qO0gDoB26d3bO%hEcrG1J4}T}knOi;wF6y^{BTAx40!+{UL)>{lS5a+o z|K0$Kf{F!2d6-*r=O(~G2t`DcgoG3zB+^9$LkJM1nS>^yp@;~Gs9*&VumF~a`b0PfeQSMLOV8}H_w2L(zjLPC$<5Hws3nA5dbOgj z3Xte1$M!p8P+9K4Jf77-Wr4cANY1l51i>qYR!qYq(@EH4tTW0H&M5mejZR&SQI5ur z2L@NvjK+r`RJBf`Z5H^>rSBq|g8`Upo`sv7S-4IMC@MA;h(O~D+1^yUXl2R`3_zcIP|R`%ZezViwz#A+n+_|U?j*zW~CUj($)P8d_2vRZ=N zpGMMdhVPg_U=Q@Bww=T?K zcs7dq)B!1EdxPdA!V^0!rU?z#r!6YZ}N_-1`qSxYKE?Tid)rqf5&M zk1i?A?-Quoh6Tt6Kb`J>(WRK^nxT>-c;V7xo;w*(Ha-;cFRavc0RBJG4Z((^h{>Ful`e>^!4KV=v5TyZx zUe4L(ad3Q~@p~?7P~GM!)+I>w5vOXdQ*}14S78h@-Jk``iq-(ox^^fX#KnX0bw&CD zQlKu^Ik7JH^rRb$vzWfy7N|SNS-3}g`WpY9(cmadd@NFW=sfr_^fU{^+m%;O8eL7N zVlJ3xa{Awz$;2(K$5b{8JktTGam32xbhzTDY2Zh_7|qiMF28}xTRAsEbQx$O_h|f* z%M>NX){{*qiX9=!pQdLh+nk{j;M+SG$8Dd114ozklUG0j zox0IlrwdloKr1ucTv7tg@3Jroof$@V#xkG-orh@**P&+(E*aE0yJKFrF2ng$)+Z0= zmIF>mlR)Dyz18YdD5?D%Y8xMmCs6gyxX#lrHQ9$E_)A8!>J;M~+6na4IrJTR{+Di@eVn_K>HLb3K;7*!ylLPhbEeFb-zgYi zc&q8uhphs$UwMN5Frb-aS|Imc?K95}O`zoJAtibI$qtW5CI4oDxpfZjj>xI_iP$FCvuQ$?|IoW z_5y@fIH4omI=?>!k$j(s&Zbgf4JG3tW4r(Jhp`&eQp&S>UV$NLkcUXYV5S?y+Z3 zQFH;pP%E6^(XPF{yJOCfmOl3(`Z_1Nmq&jeRj{mOjoQJ>aiExlccuGP-*NLll1@T|z?9e$Is~+EwoH}|;_2{uxHMG3$cbpyloLSC#k|o&AP7#m(LTBzO zs_7tm)QQjY=>MY=S0*8@b)v^Glri-1s?6zIeP zx!|92b~w$`^KD`}C*YvO$jhBQo?unw)A3n^4xOEjs&5#DW>o9!aH_HV=+on(B*#x+`*RgmZ+9?A4= zXO}i!jx`M*7c>j}Lq#VR*Bwrtp=Ze3VI}+>$1~8=^HXBh^gO)a>{K`qrxU&eNh+T> zj?=vywRA$3cNJ9tMBOS@{*9xQ}|GKmaEmNS_9i}UHVeG%2$toX<3w-s=r2k< zSDIctte2p%ki}J z^qiGAB&FWOXV+$d8rCa2cQ|5e=(v&(#Hg!TpnKvVka4S=(fUd#6;r2;PMnsuIj$^S zNaC=0&vET8)AtNuk~rhv;J82YciUVro!%MtS5D1CWG(Xdc=A)=t4_*NXHC&7^;hKrn?9!ji4tTkLz`D8KQ@$HlkT=bM}b@G+T z^2TXYuRE?$iJ=moCFC+$>ZD9hfRyMzaCUn06nVN({LXMZ+dMsQ)FYdinDd=IUrX#M zhe|xsZ5EiAs86f9%qi|^hf;OrxXRj!39|OZ(tS9V&Qa&o)uH+S_fwi)*SOWKb)})Y zzXGM5j~I8%Kbkg*9a^`MDmrrHF^z^c4;)pRcHzmT!4ajwvj+vx4hmQ`Cl~ZDJ({d@ zN`oV<=_ltdn!mnzphxY==sI_B+TdUoZ5~rNI4~IBNj-4j?+-J!G+052$6}b7YM9E> z;5cixGt4X+W;_o=n+H40RH&)z62zMhf_3fC&~R*H$n5k2(J@_gNEhwXMced*%DS!y zvyM&Qx-hpEUueX~bh~5vqWOE95263r9nv?T2W_|-#jpcRN396AW~&_k%CB7qVm(Z@_Z!Y%E?Tr^0SZu2#UC1Y>IhiR{ zUX2VWxQYwL2HB{5I4U2SE(WKIf$5@56<-6dm1R!HP+hz|7*#scF;G^|(@`d?|KHPb zHjBbn*rg~kQxa8&4A3%@wP1s6h&m6VMx~39>0*RZG#4(YHKt>fR%A}cNGXV?V}ulB zOh-9aJ`c%wI>=0^@@2??g7J$q6pRhBQF#?AAD=EN(?x}<{3^JTkL&Tea=Q{GVlMc= zuF$1hbLs3fHx#J*2hIeYaZU;jS=f78e*~%{{e0H49O+pLnJH`Z?m~LjLS{-@9!3U8xQ``ZgKTKI1X?am7Z)iZHu{r= zT&#tdb8^wa>9~}2Jc8`3gUpn4ynqZS{|PQ18)QSr<JTB%I7ll3)y^$hE7FwAK_j!XWpTW z>=klW76q;dSvRKRzG`)-e?O%B3X#?g>B(n{8#M)IM?URcqcPaav5gxvKFeieC`$G< zCA%>l zAMn}hHJ^3NXFqzG51A?Pp+6x4ANo68=0i64{1bfcNf&pei;W7=VKVe^*)&6wjOZRn zqPr1VL-!kqnj_M>FFpC}cE3hsCwAmDbeH7Jj5fM3I)akj@6PB*`0V>Mqs`3dDD*NT zGE-vo4`cwNmS~s}*EfAm@svW8 zEkirYrVE;6M9)EzvxZ(a5OqbQ^-_BB+4yCR$WH9YYv>utnHfFh!l)Z1d)b}Qsqon^ zX+|$HqweTsMr5YMC=VIHs3#g`L^c?`2}ZA{i){)}zKrW5n*ub+fL@o{cnxhg02LzA zdb=K=?HZ7|h7viL&o&o6MU-p1JD+0s?6)Iq=y#G_g;Z*hus;F)~vkHVzp;>^w9~jBF758pOU-xW>z%39_j|lZ@+2V>#_M zaGj4xYgav7yEQIzIVE!ZeOeb#^4;#VCcz5?{TE^%LZ z6(X$z^>773>cOA6z7je9{`y)@$pazeXn3D_HGK8~P3teFbq#u%7MUs0T7wLrbpslv zMK)+17Ag>jhD4K)^SJX?8Mjt8>(C?vJ2a%vU(F3*>k(-+3ngCwn`>ZpVn<$IO^^gn zO8-8w+bDZ;cVf50XEzI}JM+UsB=ipSGBGk!BDNVBkZ2PcCPp@h9Rp%56t4SZ(EYM` z08KKk7E&o+4qFv47E!}BtfzLip(>j)EJ%nDSMP^F0 z-b4n_dI=5FA{(>>XtfK8tdNL@L`-3O3tlTDWIR-Fr?uNzi8V$K)#C|(^iVy9ZRer- zOuvWf9az*m7=%TUnUbi_kO87TU@h1n8=|^GROgWB6cVQ>MW4e3wZ>z^&RUT&R?kmy8%{@O{Ej1t-;$``bmX$MUoaF)BQqswjT^DF{f;!U zA*~3~3PK`3Bzh}dP2hrNV^RvVE^|`yr7WJ5-cpt^DaBm*AxOrRlbKTG$I8l^alx1r zvQhb2sJt{JNSm-f@8H@p`NG<~(M+am;`4*Rt4YHx* zJm?q|5+g%mgpzU!T*<3xl$K(TH0ET)!D%UHEgg}bwUC*TmNSq661uSjY>*8tMr5YMXdyCy(WPjZ5!qmLEf`%L5?3iem&-W(8+a6c z1)5|)S4(ZYhORRJ(HripmGuB!rvaI3D3OEtT;;-N3FW%ZozGJE?3J1iUa^EauS75N zAu}aDHz5NOU5keKkPSX-z-M(x+^qQAEaO(mW;L2*KC7X}SwQOyKDQv!T3hcJTc`Qh zi5+{j^fwVK$iOl&QBnHZTV5xWZ+Kgj=xW9GbO*voz{Ku*_$-2 zjZEu)^fE0nQ=+vM89-|b8m2`yX#ESc?hlF03fRA8+~cx&0!=co`;GPWkOAyTL|R+w z9e)pLV0L0hUSFFJc6~iX*&lKz_B4F<7ESCyCiV<^nHZTV5&I7^fY?iDm>Ah0wiU!4 zRk&W4L2tp-*1wt7 zJLqLvWTr$bh8LZHR%NX}J;3H+1?F(Q*%T4pjQBINqLYK6 z?c*EJkv*DDOQw^HV5UQ6N_5JQ0dxw`Fdec%Ck#62VbLZmT8G7nVR3>&a~1*sPkzSE zA};Bgi+RYjkywb0-CD9BHuj0e_6ZUU(Mf#EFv7Y9Vi49vW=guMkO8{RV>#F$8@f6} zSC6ph9v0ogqKguBKD;oZp!``}J~qgPjw0wN2#fr%=p7b0VR5FCvH$^A-+IS%fmUPZgSqo~r?;FV ze!P>T*Xx;bT1b=2F`c|#@eY=N-M7Jdl|6dB7Bi145X?NtOo_+!$N&t>(C~UC8$1Sq z$5~-f8WtsC(NDp+0bZ~&=JhO1!d$GS5(F>S5@Uh(lO&9Z9n3;*L}C^~W=cXfAOnQl z!u4Z=YzR3ILPmwf$gmg@7Q@40sM4|#0m)iMX)X3h6zV)88exbTZipG$KukG{*@Vn2 zhRl@2Jd6y`@K4r&4YDETe2AG47URNVY*>s@N^E!`)R>hChLUlHlCfF|T}ckeqiswB z9T%{UN066wkeQN>=aB*BKhEW2gKX%ifsPBqVoF#{QX*b}D_O*aT7XSYC)ORKG_!hy;gUpn8{D};}@Dmz7 z^^px8*MrB(u(&oXt`3W<6pX*%1uNqqTd7Hy>+@O(f=_){8xwn#Bw?KTZeSq?keG## znUauJO<2g0Xjll@5ON!YtP6`@=z`7%B{ccX|IxWY(6}37OdyCY= z6T3=J>`hY6-s8Mqe++(dzS>k6T8uv*gGW&V`4Y6kPb-9LdZ->$mz%cA)UE?Y>*8h z4@1b7u=rP4+^i1AOjc_py6318!(;#jDLs4V~WH8^aGKc&r|5$^WPeS zIiHW|`Apm_Kgp$*A_135W=f@wLPm@C8v*(mizl=^&FJR25It7^}M%X+!qq4>Nm z*nZZSx2OM~%v(8zv|ny8Z?Z?v+e-{%41yU3nJK}Tj0|8f9u3bM*?{pnU~CJER~3mV z=m#QW-nMBB=DfYyVBX%~Ql}yTmr7v@m&njd zWmAWSjwJns>vt2=MqifwD6GF2GZ&H8hhf~xNuk-aKtIw#?Zl3Bu-eNp^C;OzVZdqlMVR^U*&l{cl>GSr0W(^FUS>pQN{p^S2B5hD4NoW8V6+pAz6y&k z!s4^A*r708E2CG)W+j?rOkWw8_86G1L!`AkoO~y>$H0`>kuiN?VEW8BG4F6ec0DED zj$Zm zAMEZkU~NRC^-H}qwNJw`51vF0zKHF0;j@Wy?Q`dI7ku_Fn$OS7=Wg^eA2L(oV%}tL^eCnBooU7F}g3H6O}NCeTqn{eI)soS7>5(Vn;p#Es33x zWkmRq9Y4p3puhe}>oZC$+>w0_pWR*~YsbjGKrbUBGbLm{A_I`^M#IR+2C`FutZPJc zj)+c**H1F^XW9IMCYe`PV}ah zXNC1Oh_ytdRUApa_wK8S*@+!_h2=@?j4anc*2@Li@szl)JF*ktvx_ydB1YBab84> ziinYl*y%F5r)ebyg}?tL|WtOo%P3SVs>IjUSa1+?2K%bfo!A;vR;&U zygRZS`0Q~SStTROMK2>GGbLmLkO9aF&@eKxf$Tycn-UR|BH{wYt5k-T$>uCH$-JgW zsl38!4PFBgY1P!@RjYZKD=d+NaZNICUEqRi5aq3P$2Ax}yGG-xW?Vzi%ecr)30DO& z0M`gKjEijGnhRW)M#P+mm>m(b6tS@~x>7dd&?FPP6snvRw!k1Z0g=}Hh?Vrajs=>S zo!F6A*c^$Skf@&=4Gz1L=MKaIHGsTFaQ$JoGXxGE<^;H8OzK}68crOUv9TA%%VnamSq43=) zqc_NABbsDwP^$=n`>9_Q4y)!_CF zBCW?F$&b>uYHoI7M_zVYBzywb-#I9sr372up*#nl{g{UGC_{N3y$prSl%TwU41n?q z8iqnPpgavIPbwmB%AmJo^ER4fB2OAC={bYQc0^jw)+6$qCStCnM2;jN@6i6wxdV9@ zKKoe>AqeYyjB?Ag@Nm%ZkaDGVUwce2pfV$*aaHdBb3` z6Oq>Ik>m$=Z)hfVVn<#jFT1RgU6kMrcPP8zvtQRx{=-oApqHVLnG%$J$N(tcqhTmy z1IoLAvRx7RRR;Ygo8QqS6WMO8k`D|be<0F&zaEhfG!b)^ByuFJlKr&*2kt=rgwK9o z19^{u{DocyLS{-pDh_2JBhWAqvH|300QoT@zK@9SBH|lGW-Pqco``&a*_9q({;1{I z-zQcIeaGp$1S9%I1OL7m|Fgf*op?`~&%3>TVRhp%8ml8SC3UsPfa#vdqOd_W)cpl@ z`y=A_i1<}Wn+6wTOKIIn+I}s~oVnl8?R;_NSG}G1MZy8Dd^(bG!Lzww zY>jyOMCEy&=A{v~6JN2?^AgmZF7rZh zNq>)Yc$7+8gfUqonJH zB+_oKw-d8-ELVObl5yo^rd0X;$bf=3aKYFh8v&xi2YU8Cy3a~Edx5qg;snJF>a zi3~vVDH^^?kPSv>f>FH8e!(;ZJ)b3_!;t z(mJ~ypb;97xrP!scnuA5;d27z8sW~T6@2#Dn$K|Nb0T_~51A?P$wCJ3387&=WP{Im z@TrW7il``$iqVQvTN&L>Hto?QQ>uh2XBnMuQ0jn4t1601mAsaoPIo%zYf5%vM_xu1 z8jW2pPt^R&ozc2qEvb%__L|W79@tUD|nX4+1gICp51J`61Tm_VOhC8l8 z`0VK#*EGgegkHu)W=gn*A_H)hpkZ8O1J?rJnimyyQE^FBT&#!}S{TKhg0aFb*Tn3^j=aL^G#dL71KGv8U#+lnDDma)$VS3vFVx5`V`S%| zmywZ~60-A=0m#OnVPs?j+0{UHRa9IV6-yMa3uNd-*-S!{%dyTFhFoK{iB%Au2s4+QdX_rRZ9?pjIl%Cq?O6 zkvWlVq##mdx0Zs8*Cs@`@)bzNm6MrL6JBB zlSJ`69c^{-b|$KHKBHK&dY+C9S^c8UoK|CEDq#$EDx^m?YIF*x`Qsqw}0}8geU~G_$%6p;m zGh*WOm^dvaPF2M}4X@S0oQ^Ye@%HJc(wUCaWc559r^@R8_jKg2sAn(;uQ4)H67?Ts zfR-0n3pU7xs6vS96BBtck*gHF4j0rKM@Jv6$efNmDTt>dR|+zwqlhbi1If5@GE=Jj zV`M+0Zf+S_a3&KqX`k`jdqW)Pc21q!WC18VWXsLyk z>X?|SgjncL7E-N+m~%4q;B-u59dTr59b~4Yqcbv~{B~SEHpqsKInXgXCT7LN3?-$D z4DBi#dc{rhed%mDEBrOUx|n`wbt)pQOJm7ri#kogPVC61y;&NAJp(&=L*ETqcPed_`N}!ly6gTH?;9AAI&=&F2c{(;vOehs>1t zj6w$R8H$GakPSXJgU^jIaeYjzREX#uIS4ggiIa@zMo4l#3*KTNqPON)t7FM$w_7wK zJFz3Lq3b1QX0+0U5x-dH7I#MUq8xj*X0(bKRic*}k(m;sYAO5zG|Y%>FuDVbZi|U^ z3Q&!VtCh_(G|7N&liGL{$_(eDyG@m<} z&n%42e8^0RPvQkP>P0wYgU`Rf=l+=39255{M8->Su$1TxH_3?Zha_hWJ!BwSLWs7+ zlF!BuX+(BnM_xmlC1+-IuM4B4lpQN{ntq1}MG;4X+`x z!RT=?+8Ps&DnN;s<{0n9Nd~l4YU4HZlmUodn`1p$571K@khz8uIhfC*E_`mGTu-_4 zq1WQrPij6-Fdup$4)Y;1B|di{1NhvAhWU^UJ}-mMi!t%M;&Zo*^L+cwi_qgNpw|pO z{Pvqy>z$`x(|qj2j=X@LmyijN|NXo3T^D}+&1>$&`1LohYGSW2vHPKeiIJHSvBxBd zEes0i$Of^uKME#j&?*T5mHgdLa(eA~PjguOR~_Ny+!P z)A|ZNd$*>wi)nq0UZzE6O0<4P2GIHz4bvhUw0;JyA7kQs1?(3Yw@)^|qDcn!qp`kz zHGutwNNZoc^ZTzFn4Q>>*Vp$4yS{#>?7zAb`vX3EpCqKdpIZ(`q!qA|?-zoWda!J+uSAZ&zrLDL z@}Pwr4L`>;htI~ZKAgY1JixS$KrhoGGbLJ?$N)&`Xn1{*4O%B!c&KiPmXYo+KkQgmWMk$kAG6`8ZyMhYTTc55lfcx)Kq%6mAKlbKTGg|hN9xnM{j z8QLepW%>g7XqSv^0+Z8#kbz6v8)T0acM zlR{=n(ncTy6wy1Qc%_jIXe^7O;X9r>2zJWeHu!{jPSYiR9$+* zd%=b;h(43GOhkItLS{-@W*`G3Ol1k!ARAippe5H5y_Ard=uZ}stA&_T(CgrI4e< zd~A>n9p^yD*_Ie)i6KhL?K1QZ+1!aH`TBddoE3gjdH)<(#y8&bM^IhBs01Tz08Qrlo)M62B1-|;36B0#(~jTON>!~ z9+Ghn%Z6UXl?-UC)W)CJs|-N&axH5@JwR0&khx3}Ir!{3#)Z$Ll&i{}&tve}6EvUk z%x5clnGcyM@p%y$z~@Oce3c*@d}_g`+7eSOFK;{}si$CE#;~B`#NdevolL%7$LpmCWY~ z=y4X%GK0_0h_tS(cZ@C5eC))Iynrs3kO`3gb>4aA^9yBP=1y!MeD;-^*it6;D|(q2 znJE!VYr@3#BM}oL8^l(C*fk1QBN^0KHcikZm*_?nT z8Q3kx`dV)QqZh4N>*^hU>oqVtu_LdqRR_DiPNeMX-HDw9pS?~KTg${+qnC-1nG&%$ zGJseZ4HF|9#5RK1oeEc`49b#CTQteI?ljid-3G39h_vpihwE;Q%UoZH9Djd((M#T} zyWMFC`0TqhtxZg;1A3VjnJLklf()QliH2#B4O-uW)_0cp#uB?NvC|S?DRT6RD(gqf z+M4*tR7hVA`%V+Eze%h#`Y5<5+KE%B=*ezC+)3JJZD z3dH0`$bQ7*cg@3G5x+_td;$AK;vgpWPm%{gN&J1!pDg4uBxWIGrX=JRWPp&BTt7C* zhLA(!1)@n@G>VI0TpUnB*1&5W7EhkrCh_`DocL3Iqd3XH9AavNaW%CE{^!)ze+S=s z3~C=1uRpc2M^A0jI0?B8!AykAl!)Aq3`n#Q4NooEAaX2-932-&#l;bE(Jbyfgn9tp zs=Br-sUe9;s($cB!8 zK*vdO(JC&ES0bK*D_O)zT7MYY;_)>y00X`6iq|ID;L#O4I>$w)xHu&)go3dXUa&GwJDoKN zb6Pt|5PaG>MS|edj*ujb#o3L8>_TD|LS{-r8sX1*A%tG;#6rl1klqlI6BlR3MbEhC z5f|N+mc|IM^5fQ*=EUY`Irf>T)tT6yQV&mT4?VHnrJTPtu}v|ao!?+$WsjcNJmzs2 zf|&=IDe*V~8NlO6G|Yo+@F)R~esNJ87lm=rN5P<1If0civHdg&b7G4n2%gwNV`BSA z62`<1U?C?WF$*CxB_Z?zCkQ#2>&FJ!5Hb=%M#RPNxELB2gX3agT$Cv}{BovIaqGRr z+zy~C9dH-c+JI}=}L)(XS%|e>2hOx zv;#nQX&^6W2GTGRk*g)3|)-}@6MP^F6YNW0U99?8%zAlBXIdL&NE@ml3wQyN;>)jg7 z(W30xsM1-)v!p6o#PqQuko0n5&wJkbH%2otq&>I6;*~vm@zybnSqSFEOJ+(i79ayA zc@7$$WU>L{a=^GOF6Ju|m!Ths z%=4HAU?+B@z3m4L0uLCfo#&n(QL@M4fY$Ka43h_s%o2k3bX$Xp?b9DFNizv_n&}6Fc%UdS9YuOz#>8(smbQM^fS)?#PaU z&;CRs`!6GFfnG*NW=hD?kpWBU1T>6{Y#`eWWIN;HtGM_=@e0Y%uxuh|l6mcvQh8N< zYw(I9()y+zuWvOkb5$jBFs`o*Twl20%Ama8y5ow$XMdw{?O|LNdKnj)Dd9Q;8Gx$` z8pcI7aQy*Xzs1GAxcE6PepJNHl+nFplY=Ii*l$qftgycfV!4R4{){Jofcr}mvlBb= z3fm{KGqRrzWIwtf>rILOaz~a2pZ%vswx5yZqnDA9nG&+IkO9bw(J(Tyfvjm}fjA^n zG|m)hna-oKfiiTEYzCuA=5$&l47Q=iy}AksQKGnrSjOgc3qXm4|Kg(Y$@ zuEv@C(2<{Hq#?KSn9VuI52d`#GF{K{!{D4e4jGW>Tr`Y} zY~X4IT*qgM<1)oDnWBXvMy~}!^aR;dp-CooJXAR=thGVx0z_ITWhOt;Ypsddi5+=` z9Vf9fvSSQnEnJXIqQtG;kxhorK1m}xk&#V7FC!x}C1jT)10Y z-5Fg8pB>kXEM~L}z08Qrlo;KN3=n=T8fHW`7-fS|$4t>7Q?yr%R>{!SvbhCKGNX!YQkILpTG|8AspvpP)1{#>QBGNi5Gx;`rpn)l| zBOiMGBx^=iY#=LiLH2J-JkTB4J2y#wfFdSs?V zkKQu|diCEsb_M8No+&O<-2T^l$1aB+XW1<^xbb_(mSiSB+gqx+*@+!_*HK_N*gr1q{zmSx&}~|DVP4Y@wZmgu0 z29Y=-trhi%tkguzm6XVl1SFI8U+E5n-il_g&_J$bAoMmgUL|Cv1f(l6V3pA8(HIEX z0CEd}tjZKODJI=y9KCW3;oZ?BGg)Pkj_v13h+q zRCl_(1eG7V%J;lJ!|Ld5W2}zMl+?{c2B@Pqg0VWXq3#u^dnr@AkSU&1(q_R0*-}~s zNqb34GY{$)qzJw|Jg2u4zs`7-E58WIxNv{_Gylm5*F7sl1_e##ryR2~u#$=6TrlfHdGC@0$0NY@y6_YtOc60^P!#*`+dEgn4KM5`7KDsm6MrLw1+$!CzSP^5F^-D8|VY(!eSGn1F(9xd8V z?8xWTFSJtoGrg^@!jDk0J?>|gN8z(~>odzPX7m_(nGu;OF?t>ufaVD_eC&}8Mn8ek z51C@G0`!86dr>wop-BexgVe*fbo&fIFC)_Wr5>Pt8j!gv5;^#o-Rr{V70R{GozJWA z*}rH$KQo`#(93+tOo`9?$N)ZXpkY2_gHKu({&~PG@mHqUuMmA8LqC+wM`)4}1+w%S zYLcZNqkW7>t8rHHfzu>QJw~$=JMtR(OLMXJ>ut4${!7W4WC3f#-;aC(pWQf1Jv(cZ zMbdVlml=_n5~FXC0g1js!;HuVqa(nmS(Z2~%X!ZDos8QnoA1#i18N39&U3~V2B04i zX&se?Q;s~djHB~@3jK!p5NWlmN3p%8m^exCrP;|r z5Mvr*^zTE=qS4yBLu?D5-A+Sn%Mjb4mm!jw62#Mx0T4T)VTfb{;%R_*YL@7lB|2w` zPKsj>8GX8JdZJ0@cq+s?SHqqL$1@RWonDV)PtDPGcBIwVRTHy2Yml9Ex65iY?sA;p z7WAe;d%EMygU>!)Wub4@xqXifIkD02=L<=Hf5u{+8U@YzKgWg(+H2fd7v z%>RM1ZgT)XM~*zE(a`3Bqe|1xXjK|KvNU)E5j+y~?ihwIPYg?3ERHG-wy^FSWAt@ z*)7rj@E&X5OC9)!ZRQ@^6u;4XK5kt&EPK&{m9*<|hO-5nFT@kOBlrB~2xw^pgxms- zHv(EA;KjIAMd@##^d}h3A~;`(TNjb@R&t(bIO*%qFU74oa^6JFlME+)rS|2xbvZd# zle4wq>?rqKs`mVc;p{G*S1aeqv;qV8l&~%u=&^Yi@Tc<}(q;;C7%2^gX$~Wp!+S7? z4-FF!4igVJGa0oX9JVlbTf99DN+So;yFW&QX4ns?Ihhb&IRB^S_Cv!kyBx?zcNWK4 z^%FEo@4j^yA9!&iMPsD6KdMsv5e^{7A7PNn9NZ`iJCp|7n!;`BX~)88QwwhttUWnB z5DXp>JRM;@i_!v38waA(PYxW?C^*Xqy~rzcHivdj zmsx|sj_HBXxz*$QSJl)8@J_Nu_?HcWfx4;qB1SOS0lxlID#|BfAmus?cRayhd$9P{Dx zC~>ZD`eiEp5}))}_~y7?_#M;2ZU?AAIG0tMO z!L%FEZJgbLIJ>P4G?nK!oQ&3~lGb>SyV`Hu_3q=|=0EOcHSRqK^q7&m;PN=dZiLGd z#eHzPptv91J}4elB|Ypt?iRmsA9EjftN*w!s&St~pa+U);POE66kMJtUV_sF#mngS zLGhL<>2>dMxA~3xw)?o-{m1=8jr$P-Jy3iAmn(`R(t>F_+{gXYf83pF+%Nr-?{ZJR z+duiwD)|ox^bobzZ`@zp$KB^Y?q6!$Km3v(a8Dix`L2+|L(c8fp$PO4)dVijnQ8{7 z%gSu-Kkl(=+!lVxk8@An(m#0zmAqYYVA4Hd7JMFp<8ZkO4hCazc^suU4R=!`clH^% zlXv=4eADNu^k@2{?+KrWupZtcclRB+SdCoZGjhIn`rf|j2dea?KIu!~^AOh0Yh=E4 z8m`h0@ku|(H%Gb3G0G>$NccQT9O0XOyh=aTC;b@T98*<}N#12#;FTg6tb)s9Z3ojX zgwy3XuSU1e6==39X{PtM)BVQ1*nQkN{^MSu#$AX&j~Q72m&ai~4=zs>i{W%Zu>{>d zC|0PFuJ#`HD!*}8x{rIE|G2lRaaSYI1I5j7xuT$p@mlwB*ZGgTQH^_tU-C`v$?x({ z{-8>JKLR~OZT1^?i~G0_`H%Z=HSVK+$sc!5{)B(>L&DC*xKTK1DJ5OEg7A3=KHybT zF!(22y{C;ES6Q7mW!hvs>qv8+kc9C-BN+Tc`Hg2C5x8gp9Eu_9FZjABoVet*R7D@- zQ*;aOqK|~jb?F6z&EYC3pXpxl;c)sXYO4G$ijIfVOHo8AN=KA&L?=x{8~8lRZVi`b z*(bv3SM~|Y-=J*J?x||)fjF<)y2IC?wnjY9-BkK|RHMOQ7v(dCz7P-4_##@YhA!|K zIv+ld)!7@a235%?Z8>V>dR5iQ)p@4!8%7&|v-76ca{BD(9pembyI4>~c;Pa?#ELBVfbD*7Hoc`>^SK99;as*&9*yHoiaR0d|Y8h(q<@c)9( zgW3IXxmHFO{72yQ68@wb`QJVxKjxht)xV^2Jnxg^S@=Avf7&~JFzsbHy{dmhjl9ig zy46v5zIaLHSM1~VH>`w-6h#pC(!N9Z;dS^ej~yHrVEA<(0w zFW_>W@?h{Yxcu%)b|}9~$-CinDR~dNeMhxw^78o%ML_5 z$Nfu<>wa+VSAG{Bjgi-dM-z1W@Mx#%%0!^Y6k6UTXTaq*g%RaW zmE0A99#hy^jq8rGlk&UNbsC&5b@f2EPhCZ-u09C#K$!=ZN6EQx`JwEk{4OOI!|76T zUv&GFJVcc|5P=?bm8o&vQ4Uakm%4_+=~CA)boYAtOx)gyPDCfZCQSxlK z{7}wPewUKx!|77;0(AS7yiAq66oC!uk{>A-t8we0#7D|S%4gIhKT-zMu7cC0rse4N zsp(c#(`p2IV7wWw2Ib1nnm5Ab`RV+6IQdU;~`)h#`_IQ`*K=RWSxXwq6u64nGh z4`Geq@(>n;%Ujs7YUCC^BOmFVzPWGukV@aiCw*)9JcOO-J@N@^!K>_c#k{CZ``xp#~tB6?gTY%B?3KARKVqdq8u*23+rg*Z?GnVX;pB#pgJGjKB%Ut zlB*HuQP)&8uKTevS@~V+nhvK+T{F<_Q`cpxu6YRbKv@TuN6DAK<%jZO<##E0A)GEH zUyg2{lCM!EUxh%Ax~^2?x}#j8{4RA}3#Ut6E70vz*GVzw!gWF{DKP0Q+7dnw%*Vpj zKu#{7;*N&Pd{h2EL=|1UC zgU>_Qsa_-Vty8{ApX-ypmv4>|m7}jujw1LxN-XeAKS-r7^GQFzH^)eo<81FThIyq3 z28Y1qv9^P0=fdf71sa8JpF?rHDrv0uxMTdro!~xhmH)WY)VS3M^q7&UaCsc&li~72 zF&$196f@B6gQ8BAG{<|~*?!~Bbsu-0|F}!lxK|+11I6WVxuT$p@s;l5F7qFEr5g7d zzvS1sC%@i5`C66y76f{TTIDzHI`?tc`;WUxjeDnG^1IxV-|e6L2bKK0nsL?JK^$sWb~Et8;@p+_}2r$v>)NDzu=v(EdQyB{vA=q`cEqQSNJ?C`$diH z{?O?rs=X7dQR zJc@1xmn_eEE&Q-&Y@ELwMd>+h(!sSufV7NTL0x%Fx zzf(e)@;4|um^KPdFQDfuMdK0W1+)@AkFqP^@+`X?PQS88D}RHsL3@U(trl@!wN=CC zQQK6wJZqb*#&%x`6P4eswmMbY9K?CmHXA;Vl`sn~*RtvMW-gpwGqy;Le3{S4^S#r9 z?A0pAGM^kv;q$0|v3L4l+BI-`Rez%z`8uDGS9qsK^>?To>wR*ph0mkk(f1Xn!L&!=tgjp2X?_gdhS2)IKz~-1^py9wPxy`docp-X`;YryHSUK9^g!`GTpkng zE?j;~WV`Y=n22E7Cvdu;+JSB#RC`p(I}zwn*H>y>_XYBW^1Iaa4V*4@eT#0Ny7sHO zenX%K%6)Kol>9SXekgxbewUK}gwv(uztHVd@?n|I-T5Jzo^>^b%df69<#(y;a5!D+ zYKCr~x=vJe9gjc{l*hs4f$|u*{7P=2{4OP*1gA^Mtj|UFyn2w@+Q2Rb3qs=uuY(HLiPI?Umo9t}bx8)YTQ;K6RC;x=Ik}F~$Ah@+i3& zF25-*RDPF|&w|sXyC1$^1IYE3Qm{0Mx)!Ot|_Xni3s#S zc|KeoB~O6M^UiP_oPM0gD!+@Ksc^dJxe(nxdM;6VW+Tv}=vi=i7Ci$_zoMrpze~}V z!s$|U9lCvrUaX3~9DyE_a2Z^#dgwlPiTk)q{l~pljl0}0`3m>sEB%wNQOQ>!&_mQs ze&gQiKJHroaW|-OZ}&^S(LMPl|K!i8PZ7Rd5M@t1c= z`~6C4jFc`YnxNYU#gVF{W(f2+Fb;#ukVA_4d0+Xt%$UzSQ@Y>!jaNwzg&3iUVdu-Urct=g6w5{A8 z5ex<&8WxydK5-hqI9Oh!@YiM!4hz)Inp#OO&TPal&aB&p*H#CE4-5-TD4#rbqWSh; zIrI^Y4rv}ZoTCGQW|LdCJhiHCk71p2^H#k2=F)MYb8>@tyLO)*BX_Q~zq+u= zrj8vGXchQJpiSV=mObi1*M=5^t_s~9c_eaQk$u`9AZV|V1Uj6IQ8GQNqtmGNz4MeMuCfsDP81+niVzeazEyqED~ z!$ue=|14c4WL6+nsSk?B|T#XgOF9Q!&} z*Bm$-9er#l9GzM_ZGQ9h&G$C{zWGnh>q2uw^FiRU(B+{;p({XQdFW~|SsA)6bVKOo z(3;S#p|zoPq4lBLLwAHWgzgI69lAGkU+7<<2SX2q9tmv?Jsx@@^knGi&~u^ZLobA0 z3cVb9HS}8OKcP26Z-usp-V1#g`fuoy(5Io#LSKZw54|7$G`u(bYxs}wf$-fR{s3ri z0sC#B{Wh3?0{&k|c1CtZc1QL^zKMJr`7W|I@_poo$d8eqFc148e?06_?~UFUy+67o z`budYmoIr~llRL$Aye=)!wVqNHmtaqEgBJt?l{eCC>K_%C;7^`?&*NV%XhWp* zkBUpo0eRM(8whOv!Xqv*4;1%1YAem7nbkj(4?qPi;Hrt0)jcBlJw}#QPZ?ibJ}Fdy zo|;hR%w5n!W`NYtm+G%5}ri{$)*y*&9c~d4$nl`zrcGk$D zc_Rl;nKH3vWXT|GcIwh0`?L<7J9g^adE}U?$s>!V)YJ~|-i-}bj{lK?K6)zxI)#xf;kr?=ZaNcT`^%~*_0WT)n$1j%gXXf%BN1PnmoQk zML>+5QWFp(ssdtIpmRXfjGb6AWo%_Yl#a)LwfJvLc0lwgLQKivfG8Y<|7Hb5K~-(( znDYy!O-2H_onKyCj_oP`mseG%@X}L zQ>Rqd_Ly3Y>8}kOUC`#FFu%{Zp);8N;LPpPeN8DyGgFUBl%y9vOXl&27=L8&7Y$ap?Me7ao(9ky279uBKyvD4u-%*r(_I zbk>4DdlqiG=Z6kfGxNwRvwM_we)zdogPwk|@E>V`^UsU*>NPqqXLQHx z{KAsHxqXZBaw^Jm0`m?DG!8Zj#R7HL(_eX|1ujs5or}tP_s3zHpHorYF%j9AB5#tB z6Ln-^VQy|oelb#3cXElGq$B$b$Q#f%w@+_GX1hdA){zB$@(cU*&do(+XP3w+IoESW-|{oSU25FK3*C+zgzp0|%6p=I8hB(?4gNL);9! zSO*sLFY2E+ptw)Yxb6wyX5bth*e9L;Bq#%!0kTX4IPVbja{Ko$%tfR#LuTaVI;v zSx}On-=|+bmRz>m6kVw!`xN9A7xgc~D$aJBqGdX=urwF3{fiLkHbqzI$fBa&rM>&& zTr@7*ZHkub$g47^?k_V3rfe@SV-yc~5&GXrnXf&KDPVp(Z^j=G|mfj8>F(vs5N zg?;n-}Hc}He$n$1;yTb@7>of2x9MI?+vkcvEl!Fo|${@S-JWB@%_w) zmweBCZZGGabFK%=^-?!qt<xv+HX-S^qll5A@oGW)|p5W~I zI!`u>%v+TL?Gv0`U+>9Aqfo3=D>P7Wc71~<3+*NgV1pJ4&aQ9tB&Erf8XcM_IJ>^d zlbvdT-9Z;JIJ>^tll1d$wbSJ5!P)gKo@|%%g+ja9gbYouZ}nuWm8<9Jo{*vG^=+Q4 z6-%{RquYiIO|NhFWW7-?HW|Q>q3QJcc(MaoD7W}}aC&{OC%b$-U#d}};Pm=FB{$Z( zH8#23*3_z-vF#v!zXzE!yTx*|J+@V-5Fiu$!am*ELWQqNY^%&yw;QDTCtKNtB|g7Ecppfmhy#mv0S7)!CCVphsSR;%?wvjFLu$C97)WU*ClwDQ$Fq-!5b-r&hXxs>nbiaAKvK$iTJ zCmWnkJFPCgEjVd@+LO!~g?7712M$h}pYdd+R;sjX4e9EkCi<)=tNC)fQ}6Kg;H3FE zPnH|9o);L9!AbM;p5z?etTii)$l#>;1y8mLjeNU7Zx7CyU-V$UT+A0*9lCpP&is-m zi=BL{+GUrp8k{q~?8!nkS1oneCaebM%&&N|k*jyh1@}@ zHBVL`n}s@G56+oi_hgl?*NSaQ6r3|}R5HV!tJ|p+=<-X;{ngpw$?`B!p^K{SU&>;SvCrhXs>a{jqemOLVzwgO%h23tw&M;aI z4dNeovQ4LJmdi{G%Wj&rCHkQ!TeWtpR?0ImEW3Hul0Q;1)nars*y=;-M0<#|2vFBn7X771OWk52 z-(Zj|>x65`n?0FtcVz3$!mz9}u0?<4QFK$Se3^4No!<>7i~ic9ZI+utiNif;sIh+I z(Jt!^v~(7obZx4?^=O9$hp9(;pw7A${hdb}Ea2@NXK~O_WBuNvO;+#@>P|sJjr9kQ z)};vwXbnI^jrB*5)>y-9MN|=>p~m`?M=Q;8z1x+Jty8Zp)t^0??=k>7&1Cv+H z@n{RQO5KvGPQDiXt4G^ppwvO52O4Uuzj?IV=JeG@bpRR~S%3Fvr&KGViINr=4UMc@ zJlbH!kJX*_jx}ADXdiH3j zvHtB*x@xzKav0Lhg0@=!s>zTRqxph-#uFrAmcH)_*j;l_>-lme-<7&bhZ^fhk9Kl76n#x; zfpn;`Zs*ZPm*ZunD(#vMHP%rcZC1*qZnY@AB^_$4qdi)0SL+S*PlART>llx+W)|vY z4%ncf#yZxcbnIFkMF3=|v2O3lJj10~LlXcRYOLct+NxJLHx~rWgc|F3kG6AFj=Gg( z&lGB`J9v~MWU<|C$k5J&8tVj)b_%6hhwB{c1im11jZuj@<}yrT!(tvV-Y&W3wkSF+&g9&B*|!g-=Iwbykd3*O0tr9!?? zuW^Fi>-v!e&+s7qvfik3fZgkQkp<6GaI{OA(H-z<-KE+M?OC4ebXs(w9Hr4sswMC2 z$yT|OFSc4#knT|}c^6M|_tD6;Yt*@JQ7w5_Pu5Yo)te=nQFo}8Jlm5sHc0#*JwrFB zmORIkjXdXwdP_Q+YamPB&6CX<*QT`^{a3fAmb|+sQ51E!fv7;bCbHzYo-9=IsCsi% zNY_S|yoV<_=H)xNJfv<;EqPB*c3QPYo7oo9jUP+i%adGxRBOy%kZu53^4^|ocbY9W z=Osutf-HF-PuBC@cA=avLb@Sj$@_Y;R_j#qTvS22F=WZ}JlQC=nx$%;9xc}&4nsfdc9z_fs=fa`U3>o%_FXs6rYKDsXV zUXHY1pHMPgEp~FHPP2=p!uhj%hZ#6jPO#S=n`k2@mEG8^7Fs2_b6j(s$xb&HDL9%( zEnRK58&m!5+lNWo&tI%$s!(f{EA4hs$eAH(%k&_RRy*}>t5Gfs>eMC{y~LyKLZMMB zqc#EE6-f2Lil)mg=I&-QpP()Ww)~fRHeacdiB2wImjiY65YM(nFOM#a94xrp+GHQ< zQPH)R^7)RimxtJG%8uqcT@+2Z))eODftu|pnJQJQ+-Y(ugmmSy)zw#&IzStjFHr}( zx955K({M;KDFBJlnUjk=^+5ZjIF)U+$Q?WsGIOE_|HV9;Rff(XFDA%NK-P3RKf&il&Q=a)+YmbsCIx2S` zoHVDm@4h@xu0=)D^?Hl>ib-8i*Rr-;dp%odp+%IbP1sOomz2$PQFXMrIT)}mVcTNM z96u$8u| zWQy$}_d9HOAzglLtL^t_w^J(D%3R!ly6;0&{jxcDyk~3lLJU_}zZVwg zUAmTig0h)>w^FL+^UVS461L6tM1|9xCR>9xSGJPy{^9tw2|r2MOg@KM87J=q4W;{J zWmEY^t<`9^u;5%+bjjL!xKhz{fn||vFHB8AU9vU{Pf<40>Q*Y)W|D{9EAyATim+vS zs)tbl)$=9hn*?^bu<+9qPSb3d6&A!eb$0J+pdy~`*(SDlwQinDTUy)Wx}?qVRi3RC zbLZTP&wF&V~X9 zbNno2Q`H(%QzIuep{Q-TXDga6)@4y)unX$)YYX=rWtsCz^;W6SnA$$0%eqbWxdzSE z$^~>0kaK}0<$0d06)`C8VB!Pnx{gis`HH4%-5d?v?FhQ;7B!pK7bu&mwz{oC0nH7p zLv6AzR5Vk=TDa8WVoFd=*EYk86i#&tRSw;#nSk9AVbguFqUk~liw5pag>+My&FxD( z+D0KJ1~;%XGp-ga`%-07G(fA}Y{2eXb;HNz;AM)Y^NnULU*!r@(0zds@p5HTg(3!` zV$lfe2AWOw6^f=&cIPlGd4mXMXfL}Ox0!jr!Rv);t%$MN0KYth|DWPx^?W;zVx`bgNoxic)V#yPRA4gG#4M)Hye9k`+JpY~z1O*|BcDUE*p&@-e%%vg~$=Hsud{ zx>!UH)h-O-ox{1+!XHsM%~f`t4X|W-UKK4i8y{6RQ^3}!RplxxVb_KU+dlX)h0|!G zFqvaRC$P(eP59%=X4qD<9-`<<*igdPD4b>oT*>FTcM#Y$piTH%Wiv&tN!wz}l(3sX6^5T5oO`moix=uyfQ&o=httyI4BjP@Dl#HK`493s(MyAGf z6iZ5yshvCbEZgr`nNO-rX9~XD%~cPSaUVKbK6KsSLpP{UdkT}lc(B zXQE~;XxAMbO8kq8H>WtNmlLbRq?oqmkCfK>@SwH6q!O*ER#B`n2Q|NcXCmP~Vte10 zRirtEYg)0?<>)9M*}vXLzM>MXsY<0#s5}}WLRYfMSi>g;S`y;V1yR>6=r`rP_ zA?5hcpd4RQzBSb-6F7wEMuWP$7Pz zJRPyq<~pIB^mP`D_4brMwIcN0PJtu)un;svs1QF>k#VLp%mT0r9Y`#PTH@!5PjpKh zY7kI7RES?F-#o1L=GVnr;_ggDcDYJCAs!9f4NaS}$1ch@B#m8`Htb6SEy%k{&ZE{K;7M$7* zR@EPjNQDy`)7zl$?pb$6{G$=+FzGOf4!YJrBs7cs$%qu|T{PER&Pj`iNO(s4vk_@_ zu)-;0;p;_0U-^p>;jXg8^fu^Rdy?tRHKm;y{%S-jwPK4&bkJ1>BB8JRO-075c;n&b zJuFIiM*O?t6P>cy{9ss-6hjuAKrys0@|)YZ)XD?ni2o2_(T~uaRL*#iep8*+h^m7= zOY&iTL}VnoIFL04o1}q6upMF}QKJxSwFe6(A6ciO4zeQcdaK?ZPFIOY@GA$a$T+5- zIDun?o|Gg!A0DFkL?vIt0JJe|ymjWoLzU;mgzZkP&}N8 zj7X=9aW*wPEX8_Nb+{Gjlv)k6=w2jPRY#~uy2i#h-)bixS#ll39xIPjb{uE@W-f=f z0@cb^J-9czo#GRfI(}3wjOHEglDEsuQOb`uF`CX}yYKkW7(H6?30(3Tg{Hwn$seQq zcma2*8pCIpd~oy}tM~++E>{{(dlWW2dTy`$c%A!*QV~0`q_p8acbwuAop!#_?j(8w z>T;bvcf9fp&H|ou+{Gp7&#$}Zx`P#|H!D?)=DkR;H=JNZs!c8hb9l)~DdyK5o+nz7 z9Hv4TOn8ytS58uqac;qDoid8$4HP#Rvpf zlvAxp13r)0i+&?mh|`Qn9uqB;Q-kh3zwUPBj#i|IhnaZd4ZgD8cI9*x8LQT?MaXeq zAQFDWS+&8Plpb%3i3{#Oj&>Dg4=-mZKGCk#3k*`F9d5_xnI5k-2$<0*4+@+tx`FlN zEak_@3G-wpnOexZ8_qWGcUF45jTQry=AZ@4ifi+J7sXlJ7!DPT#s?MSw^ugvclA8$ z8kS8Mc{|?idMtmo@?*ICVx>9k5Pqq(nLkJA@d{T(;+r-|-Om*^^LJBx0wchB4ufmO zLp6VQ&zH+Bsy#h_PcCKRBsL!5wdF@?M@V6`Gj&4*I0vp}gN)@k}kp!Edl2t#bu?ABEHHF7~lv zel@$gdv?dLJKELjzMk!%9c~rybAZ)5Sj(QLEZ4Q|dcBtHQWUjUN#`rdjb63FEso5X z;p^Isp2c?qKVV$=XIGbkh5@6>W~%udaaWQygmr_*Y8O);&f{^EFC=Q7rQNC>ws2bE zG-jCSREg{{ySg0AMMl|7sfFWx9-o_p4dr4?;R&>snB2FeH4>%Voa1fJ7*~G0#%`k0 zNLKKKcew3%6N--&E7(SslLdTvX}?1$H`0Tf_${ zjX!LY7-4nkPSEbM!6rSWFlJYn&@{Ot9>Afbb4q9O#ZJ8@9$X3SPVP48yuxF&db5jT z*nkbCT<|a!LM<##2DDe3+aeZ~9xs;aGJgzm4eb)QU8JP=Sh<68t%{X{WCdmTa7M6+ zmz5spbVOv9$BV5FOGt8TCh`5joYxc|D`7#0 z8&)#Vz(YB&D?MJ!SL>a6GU-U-dqO#HDBhl88(u?AnPh$6^xOfvM|=0uG&1FKwM0;d zq?e0~J%3o4mXX08lZ{kT2t<;_!Sx+0(l#Olr6ZCW_6RhY$gKC7j>?SHutv+Xn;(j} zFW83YDm`9l5aFdf7*qSEcg;E6cA*OtPjh0%RvII#+10Qe(k9R1HpjhcnH`R~p0rEK zX3r*p@|tZ%6s#MomfhmncCmmih;a?-vTM-`Jz8is2?r}}$z6_u;r@}ZE@3+bJ=nt}+9k3ULCPfI(3E_s!ejLg$7J!08^A7U+kYOS zbh?INL$!?K?Ho7rE@hkNhbo&PFjBLes|&lhyu=I;e!FOcK?o>7->enL9$OG0TY^!aT!lU(e7kv%^YUUP}hS{|iL=RJv3NF?0yb+QK zZphj!T&8TMUMyiqhT(AiHVcc2X7Z&f+aQ*cx!tBIZ0+t`ST zkF8v#DbvZ)uEoFzdbmfctrABIG^(I(T-sDG_h=of=Te)9FLO)Fp;RBC=orc`)aKG3 zmzMV~t+@KKjrK^T$I+IRixn)jhqS9RyDUFS@f5xYm_MUnpIe>{b@oRqn(olmFnuN; zl8wNCdyKM~GB=-Vbu~a9(YKwz|pe|WE={;T9RH@O- zaTe$Z>rk8QRf=xJI)DX*Lzns&*cy0-g6T>Jf8;K91oPYbOD<9S{bzc%+9H0aXc6YO zPY2nnJlx_!*18gvNiA= zMX?LU^^$|fydGw4n$PuMr%=mPiG(pVKj$`vmVBO)DJ~Uo5aUW6GSsZkS2WFN&EwCQ zPtZ`czChVjo0CYR!LE>G9cl~pLPax0QO6Ow26Wf{zJqNqe36Iox)N<1O$)3Y#=tq6VK>FcjoAz}IvsY>qiONZ**%_RTUax4nP|sJfWKMDrY_K;dn<`*uQ7&Q(?y@@z*pj_V(NW?l2Om{b zhIg}p_4(BN+OjS+HrbCUn<3&*vq+F!*wyVDUBY&X`M8J4E_<$OE`fFWw(vC`uC;T7 z-;=($wz@wRO8HuaQ&?)YiXCRUh3S5%kAK3W#InRBl54+(nI&hTVk_c0MbixeDmNRF zDyUoUY(-qJYzo_V!q2crU6`8*<=~TwrfUSmC}CtNs5)@lWN+{+p_e7L9q4vV)}o(M zG}Wm#WS0u6d9~&Gv?uczxD*?7+=V&yuC?fA6lLRwfpwuSsV?a3VKeYqWi!_6tg8Sn;_4#;#OQJ&)Qf zd{JS%;&KE(CA{Lo+=^3s*mS?7Xok3+=9$C#XU|3iQ_nNOOo9PreS5(UMg_XJG z>GOuiQCqkhJ#t4t zTMDN-xlV;}2~usr?)z;;(_9f?mQ7rfg_Usk{f@Gkas?e`i`#*Ob(?&fhwpkAH4Q!{ zoc9-2*6HovQy5QNLi5#Fs}@$mz5V;jrn+cfN}M8v4R!Y)D4HPz2>VuIo(mf6?mzT! zDTif#MMm7pI-U4O3a4oeu|2L%p^n?>YQi?%kCn}Ed)O>CuyIXTw_@39`-#G7>}0Te zBha+KZbxPl{;9GVf&~!JQaYQkp@e^?aGHo`b+%+pf%PzJ6aKkpOI+{Os#WGRSl8Dq z`wP$330lrWBuVLlm(e#Vn_`y0F%5TeV;Ep(lwT@3%4vfT)x4eI^^$g@b+aLPwF5&* z$URQKWyxQ8vfSaOqsaoWXUP@HlD{@&lZ!uI3Ls6_#Vq+7B{!BksNskML7Kyv!EVWa ztKcYGTnwFARlSjcP4ah2rX*ZNxxs8oHr<+PYw7ojj^%MHz=^#+wYX;yKSI|Lt;X&T zp2p4r2X3_g1KRa2OaD>n@j?mzN@C0IATaZb?`e(CB~|ya=9YG23PGBoGt7Ig~#hf;*6sUb+qfjHaCYWo~CXZ zgrFi$9f`XM)GjnfC`+w(I395mD6H4t+l(Bk^mwJ*>K5tnjt*tyc8U|tr-|WgXMpQv zoSk8gQh2P5(Fs#|(nPF~E@_*Sqdi^9^Hdiv#7Iueg`B02Q98q2Cy%)iA696!h_e|v zR^f5t`gC|6A(>z7rJSwp+bcdn*jG$0*)K@ia);+~ZoAfT%8wHnFxP0|=b!Mt%5Cz; zD?U+XG9rXiG6N*{c%kI)p!}G;2h$ZtR+3+w)d+yLVop#x-KY~h96Lv$^(xPHl@pcC zU~k;!q?z<_f0<`1@gxu9bY8&*FlkMHooC^bJ&X+&Y9)zdN-lys%2PaCYVhh?MdBa| z>^3Jhgei#b9d4XQd3a4l)4h&!o7Cf~-qVmN2{3n-hNGdzreGaZ~qG|7(dQx-l`VXSz0 zbp?IbfOXlhUF0l@5LbchtT9gvGh;JuS zOr90OwL3|DZD!Gqe`~6BHA7>lK!Bg(`lciNx+j^AYO=cTW{*PvLmY1DZSZpPn{*~Yk!;uAblQ>YWBN^z&g zwUu;V<;RG@ox^>^CGS*swr8BD^mvIlwiOPi!_?PY;x;qqdz@DmI^1nZ1CV!rUu5x( zicfGbXi~s1cT&5c~2=l&O420*OM)(q#n$BTJbUVF{u5L zNnY*-Ly2dU9>>@g)mK5L%!GD1wF6WAqf zn`lDm@fNrLO+w5iNt+u*o0Cb!nURTJLhvBPUGlchv&xSX0f?evaw|DEcaS#u`zb!r z=yIXbNwx(8Je2(Xl^-K8p+w6XbYI_LY*`$xVPceLFmO9e?M(&CGT+z2`VVSlVJp|d9irG z1DIUdQ9sa5b`>LtY|np`7Qxy%7yUa>Qb?Ez)wn^R($ z)Xd@hpaQN@?X+4k5_R4dYhaeE0`5d^1*$4QjE!2Ecxh6d!z`&IiJgXPDluN_bek3S z%}&A%S6fAO#V7C)&XovquDC0KEpx;3Y|HQ)HOadISiY%zlc)w2adDFFlaydh3t)@f zQi%y>;R+V5(m6%IcYXVXw(`xXJa)a^W?uTxP{5VJexYL|+Rbhk3oMr>KH*AXCAum> zR56~t-<;x6=XOEvuT{W(!8Y21RAP*)5~8&5=-)uVHGrMC zE>U_M4;zC0CHe!&zh>VS_rV^om+`4>B>Tt&ce%ItrHW6~31;8qnBwxHy~mdJAAkv5{-KIbU_Q*|i_7YysNk+@Z1UTbCmu@$v#25NN0?2$r}PBZO}y2R z91bX}SzT=Eeb3`h)T(G<&FHfHwDN==!UI2#0%VYV5pempO*^9!V?-IQO4N{{K&WZA zD?MJ%aYNGON++qE@P233xXWXBU6rCG`)pn(T)uNn}rKUwJ)JNT-{& ziC(5CSL&?h*w=tAXkP8{e%`Z{VhsfxM~o$m;@q*yvJ0MV5=^;5%#4H$X_$6Fb_FXPip-p#>vc%lQo>lJ664qtHZYCE!%o{0egRpZ-V3!LE@AWY6zR-oZs1aD5 zZY{jzVIrOp=vAJQ#>FrQFMGIKub0YLs3-7lXSi%rUQsyBBEeW8$|or+Yb#@)vKz6A z;gJzK&$6pEdkM0tU>a`%O#e}zEYDBtz_W?&_bk_I@?2UYVVy0qW!ID)BOFY=StJrP z=`PI8I@->^4_7)PZjRMFTO*;>%-Pn%ur333v^_>q%qodU z-eOV{G?eTW%8nA!SzZ*7WL;)$u^#J5@y27gNx9tjE%`W4Hi|hmYuwo_t7U;DAFpJF z*%56%u9}cx3%w^OoT~C-caiwd0=v5wTLVv2R7@&~=8T1hpl(vP75gM*Q!RWWi8w?T zSW#;>o9vSn9i>@0AWH|=%Q#!GE0yG2#Gy`}eSq|aRJId7#luAW$rpH;THtUkJXPT| zPZVG=ORy(_Lq&U$zG*ws)fgA@(41lLv4*c z!=nWhU);7Pra_6p60pf0zz&8}9K2%05{!8l}H9&GhKOW`yxqG2$J z_CMKQ4Oc&#@UxZ8@GLA(JQEZJ)^C<76<;Js`u~_eCDYbd*<8Ssqq)hI{Xel}%v?LI$uK0e013tL!C;rtw6?ewc%a zprMkzRN0h#ztt)yd2pyr_GKRBI+#}oSlX9Y)F#%VFIP0p#E5k`)*3{@4$h;mP&U)$ zeLVcPWoj^1v9{4(X<**;b5wx=e$%2kXbe&hps`4DNz^-gIzi(7FRmri@BT|mAp>FmjMbmgIV+O}|Q_xVd zZ&o&i;YOn%UQVzMwSDI;ie|7c$<=Y{2Q^ltw$;|EFZSP-EKZ zpcPnIXK(xg&z4#pF^J&vu%XKRpt2dBk;g5D?whb~7~3lNkiugGcHluathoeURa#(;vzM9(EL3cgMDkKjK*)vgg@8Y!ZcaRbknWdKQI8tB%W!u)(|Dk9ihL4>8A1 z@(^6!KCbK-alKI~;^|Jhrj2dsu2DKoJfkZ5=pOZg`RV{wH@LHg~zY~lE)c&hF9zb)DzMs{V7A^PsGJLFSZK3(`|Vy{b^4# zxpR`|eOrMwW{ZVCW8gA&=`?gg@0)g~S4)4^(?t{yIo!;KbSNXA^E8_XoLTAhl9PSg zLur5B(6t&~+wzRG&^tr)7d*`~p~-$?NQZLrMNfBm92rM?p4^qR_lMH{lBd~T5)_-e zxB(qX`^!qFaD~RI948O+YJ=^gUr{to6mUY-5uQZQ&_w@LWiw)cPt-r@e5*T_ouRnx zPG9qI8E--+@B!<#n3nyzXIq5E;aOqHFA2L&ZQ&a|EL!`$D<+hKKX4jx{U< z6E>8KZ+f=XYVejOVVn{;l#6dEoJOxs#3y+;ekQ!v{Dvn3B^fNlfk1Oidz-&k35b}ld~NvkpZr4 zZSfy_9GeZIT@yWKh`SoG_)k1u#t4%DPA)V1T%}n2ryj4Dd7g!LkzDGoVl4hMk7L!0 zKN31E$;^(~U{QbWah_4)?G$-hUhtJ5{tJ(Hn&l=7%b;d>55;v9o0*$D-ekK&#~RcO zc&KK6>2V%UD`BNEs2T83&D`v9%-A|r{KAKM*YRsJ^DB?DpQ&)=KCGFQV5|Px<4uBF zl`y>?roJzf_uqJ2mJSN*Dl*urzx6m?)Ww{b5D)5I7gU?~-zlDv`GJwo+%vPXyyj+M zJ5l}K!#wqfb($=wGb{Uo@E;ULrH2XwU$-gq){337|ETDAlSmWX>@f|`t}U*FyVjo+ z$I^l)y6Q|m*noQ2j?h1Qn5bDbtRqQVY;&|5TKX?aXQ;Y1PpD9P3;i{PZFT(B!{izR zX)x!VuFhLxfGG+t~<@jG7zQR zb_WYOvfY_yXV|fHnP#PFcI^&!kjTS4QClGtrsRFs?qCOrJ&fwLRpi0K0UWCDgFK9? zt6t@*bO49y`(O`al~k;jx!6mx5vuP)JWO9|cEkrisSP&`+a7YLhq-ksE!A}Tuf39Wn+WF6YX-L(d6Ax;Cb0j>Q>b@`{BxG2{x^H)j-@)Srp3;@~^c)__%n6DU zw(5{IreX^(Xm_`-} zQ8u7;Dz@|~o+fBqt<5W*Lpqd`Q$1Zk2TVv-_PdgA-2&LOPxEvY?Jh3qgM9A^*2x_` zT|=u-DspQpY3~Wv$?2XZ6h6bA(53@AR3~@xG_Qyd_zyF;gbvop8J;FK9tvJu!UlAx zPR{f+?mcKwxF8?Up`4uMX`D6 zaW>4jIbfN$I&h$LOOx$(8$F&UoSe)d4tLuTi;sG|iGeziHJB&|sk^ag@s!7_5<`&( zW*zPZqs7yTr>k9bs)WdzT3zznecP`xp2bXr!xe7`tYWw0YS6M{p2hn&pU0UmVV%E) zWyd|sBW_&aikgjdo!-&16P_i)9%h8Z%@@}Bv{`miSptGoyJCw9tJ?)T6tf;};b6(- z6P1j0&9HA+^nM-{!{tV$O7ktvySA|C{XN-9?laMfCx=e3&1YF7Op8g z&V4(tILJ5_c$e-4?7*yhyxu6}^Ld$62DnSz;th|Nt1R%0Wrw?BTD++^5fF+z)-1bp zN!`IV=PiXt+Z+~{u%usv7QeQV>23k_4#8)H?7PadqqE~#QJ`o(;Dfq~u;>LIMU%~gJffo!8>T?Ao0LrzxkzCNk>0lCa%=m=W{;vn&SRP@{X)&1 zEV{*`E!>xhl#t}WW!9n>dX(oCi8vxN-||wZ4{!BoUhHge41jc{vWZ@#BrYmkwp4R6 zHSC)X-}+pvbf!@x^ge-}6Iy2-+Y=t7@ECW(gbv4ZQIZbd`dnh@4%biRrgUNG;H}St zJ&lU8UMK3?fDT^!Tu=E+26p{9&Ip+kFxhkCkPAxeG= zyOe|uUi)k_G?8TU#BdnUdcLzc>3NzEMwr-P_nf31tdqW{3CCFM=DX5A$anDCXWG-m znJ=)A$)FZGRLU8p$1!t2*O#md`xZ9(dp0{`Z1*^3GQ1qlg*AyUq+fX!>R7*m;@owqMJk6?EZgZ2D(DT8Z%zGLi5meup zz)9Nk!JI63T9%6{(Zq*zC?~s>PVue-Q<^AxeK34GpX~8y7u6C+F^qwD@mUGYxSDyQrk$u(SQ`@k&pW z8YNzKCPdZRvRuUUmA9!s!SfQ`9o^1=UI@}pRC){tLjogn$t?Vu(l#$o@-$lnVuy0% zhu-CTo28$u^aM9T%r3a*L$hdwbAF}gn|S7zyIjZ&_;B8zqWoBc@IbVa)FaBKVBVjq zG|%m#m6W((Ys(UmLvh;)o~AhN+5`hHCYd25htjsFPgfc@MB>j9+F$xW;*{?TYy16G zMgr5QB9WOYPQn-0N<70zu=DK5D-nsr0TpT`o@pf7+%r_DQzsGr#?>m3VZp<0EcwLJ z_C+_v+708g6dtSQu=T@2htvgj3Nc$n&-OI#bvzfrD;opasTeH%98YucOpL3fr%BqO zG4fnbqqpF#QS{A&w4Lg}ru{snGi(>}edBxtJ*zEi3;BG7n^UM~Ftw^m9S% z#l`8In@E{ERu0IEojYEl_!vPznaMCFSX;G2#OCFto+i{uEnk%pCA2OkmVTM1G1Xz} zkhMw-mxASdxu@BZaL%E#2pmlM6$(#qt;j>qye+aeu=mi!Z82Zzd14RawoSODA+PCM z{#Blr7+r*)%?cbo8f&-27hv%<5ejt{2)2Ia>K#P_R~2I;T2t$3s2 zO?h`YUzE9WHQ9xPSNt~_0p9rJRb397P9nJCzu8FCN_bGo3+@Anb#@hRF%mrYlE9|0I=h{Bd%nOk zUQL?Y@xjjY9?xUU&#M+3=aXt$+aDYZ@AW*PMz}iW-K`-XO#gkJ$1bcwtny?qtgg3P zd%x!iAkr;!8JDCl6&f1M|L1wp3!~{sCJWLJ=l=tqZ&olrZ}7U7P^mCtgMY zk3-%M#3#Tk0Cv{>kf-Hlsf0J zb6Ji%VAAoSHEl~@>uE0IF{H&5gtXV$`F_IF9U{q8UemYyCp|9#bMg(@GbDVt-f!@Hr_|w|6aD{?52pVq<;PHD)GNFM zBK$i0@K1ZXQ^h2iP;CQR)3){g8KsGWLo~WtUHaI%yY|m|yhUWxYMaR516)(L+oR7Z zj^_j6Nr#sNLlN_@>o6j>Q@&6WLLA`vdf*Np_;f>_>gL+m7i<+xELGR-PV zsU~5j)>hX!+I&OdG0tUqw3bq@>m6;r>FFklS!@)g*9jdu+I-8?xEkU#l1wG*9c{kt zX^j2xV8M=Hkap;3^Btv$7+xu1=Pn(3oukcnJoAH|!pWx9F!rdn`_xeZGUwOVvD2~!#VMusQ z-!6i`Rz5?-82nJA9@pmaZy6rQY-j(C!dyXATkO5*1_>PMzrR&FQy>NRXW9b(#n6N% z#?3|QP7FUo^k0=8FYxp#rYDT%HLAnm44d74mmw$9UU? zXQ>E020Oo9o$qY6Z}Bv7qj4-}D6nz#SL_!4hr*-0`pgwKfh(tHT-+ghzwu8cQ!R;6 z(!z#wdPZO0v-cbS@@T%u`;Pc#NZ=8tr?cq4J=!P|UaTa6BzRIiaL4l>kD`Yl=okLG zgrNzLw<qzvPtcweC z(@WDx7*}^!RrxoYqQSi#MasEl+6@y3MRyS8+K`B#yRcVMn1~JynaTcBMwpt z9P)ZT+QU5iL^!#;wA}Xa`!&ZXJeIGwv7+R~2Z48~rHmc$$10s}p=2WXpGZ zMR_}zpe;P;1iQSXox+yyI1kqdP|H3^$_MOvg@upzFwYLj@kVknGpE_G@EsIR^MW$h z5e)o=xqdJv`w5McP|nD6LTbrnGjWoKi|7&v{UAAB zncnH<9}AzX@K_5=`f`nhgG!$6uehFJTjUf^m$~G|R8EGI(5`D(`czL7j)X{{Eh*uy zb<#e~)14N+2)x2Mq(f=nQRxhKI2Cl;yh6m=Rl#SIPWLcNe}&MiJex#>gdlt;4`XP_ zH8!UZQl1Sq_!$bPc@l+C)tDqM%*|?dwvBkEvJ;$nn{6Itf?Zymo%4gmZne%*K8>vh z?kdU4P`uz2m<#Ug*#br?G`dtrKbViZc$R=jJY1dB#^P!y-Mf00+lC^MKBU2YSSVY* zvz1Lrz%d$79v9N=+NJayMbn)wN-wnCpy8$AZl3L8gMrdW-WCck4R`l!n|Zd4QYT?U zOT)RIZK0XRqE+5a3NH=!@GJpD%2=N=g~NuHhI@Lp&bzA^BQu4=hL(nVd6uX}#e4-* zPGLh!!@WJrq{Rh_%*wE#rQtrFm9XFvQDI>vyfWNZ(M-9)evPmzuvK zp#%=k-{&ix&R68MLt-hDv<@WOc{VDWAp|hx)Y+8oT5MpI zih}8;_~0|eO)c$NQ7-`d^{TQNVux}VMCX>Up^Zq*!wsB1376QJ;#}cRO|~o7Jc(Ygwcv77GV50sn2Yu(Ux++Cn_ zs)hp&v6H*RQ_>fyY%Vr=6t9V5rOVch&b~L0;msbcp|e3*+5y#Pv23baJWALl-1n+^ z(B1B!Y0(Q6O>^yE$jQ@5!N{!b#tq2vx}8X zv!x99F^@QDGtW zQe`v5a^jghtSgclbFl3=5Akr9=$Y*ncY;Zkh2V!OoT@Oj6P1K0SljnG)Hd5TMaQtF zz_cHC!6f>W9zJY`?0Fi$&u&XL@d>Tx8cX**O*n^Ag(DvD{@GyC(;hB&OUa8f13H-W zjM6E2-Vql(GO}Mgn=RpXk8VDk#*14G)Y3&+-^00i;XxU+OEA?rvo> zjS9|lOns7HpJ6*N_IOwVQ{#0l%}b5Blr6lda0-(QLILv{09EEt+rWDj9YfEF86M^s zVj#Y>?6ljqt1l@%-sX7LE;FwSy=!67ZF;PNc3JUMsahSx`9_3js!<)4n=2F7C5R#UCw6duZR#Kvv znBK0WZRN*!5<@<;v^Z6Qx(rzK3Pndzr1GK;&%961g%r?_RWd`!<$R$?41lCq4z@$% zaUPb3$}lFRR;64a`0)y-u_^CjGe*slUB}u=c!Fnntrj~BLVidsgxDu~wvsENjg!h< z=UM9~dA7<`D{e$(>LL6D_LG&(&<~n*bmoI}-Qct}aixKAHRi#sLAoLKDawv=Of7YZ zLr%huw7Zk1dXi^CDtHJ;XAF@~Q!;~@YZr$asa$%agKcJ??qRIt+XUB^+NIe-@Kp+@ ziGIe72xigJY>u_f_6*PRqBZd@nXskVLhLh@B|JbK`{{~Qf@@&gd9U_lw@$Q^7MIx6 zLI{19qGJVCSI&FQVKq3~PEODEbelMjO?ha2P!A#cIZ9`E`hW+I@cv0E!ojwRpX*^> zJ7OC==DHg5@PyI5LgkK|nzDMh|1_rPg3s4tMt7oh21&WRlVUGBiJghV5 z5{|ZY@j|6DG+n8UqG3=v2ipw4$itl0OT>F87t+ol_{9pRiL={bZBDxTQm9kB#Iy1~ zCI_xgQoIoRQf0>*Z5}2nCUb;zc}?0bpD*(`!2<}B&k1JG*g^c|ijRq%Lb)mxE!|#e zTYInYH1{3crf`2Ss1TQPOTSWSHu2n2cU#Fbqv7lIS9!QjAX5DH1~2;t>-yCSkFlMo z7Tc&Kc=pc(rnLEZji>2LEi#=vygIWo=Z?3Qey!4(d=VvEjoUDJQc$nVZ4Y^!!fE1< zVAX_v3s_k@YrI}rGzeJX}8@{)HgNMcc4)^Zl3Cr2NZVzj7@kS4G2rJ=@kW{qS zj#&6j9>y+@^8_uPWZ50yE&OJM$4c!gaT;)e0dzW_r(_%iNjYw)VBkj(6Jxf)J-S z8pPsu*nUFsQF)P`n2N-wUUUiD#qv5&7I;+xgCuc3c41*GdA*V;?)R$&UIw3FL>~`E5_)J;?omEDk$DX@19(rFxlgLb5T|W42B6 zyPo8RpGSqU!JO7pwk5ykNn#o0IE1l8?sJh@Ecty;q7LA0NcLB|-JD~|A9#|T9kK0l zjj8Enr>eK)4?W41bDJRWBu z#G{;E3h3zB{mkwSp+EH~S7@asH#gEsA@pY+B?xY=O7sG0rV#pbk1}=1gOF0E!Bl_Y zQS{b%qGi$b_U#U(dXq=l0usv|!**IKg#OZ_gwUyV%RCE6Q-#o*JxY8}HUr!_(pVw% zSBhqcM#>co%NecZ4;gmK__c=#&Xz>UkoF40zwt2Ja9**H-O=pcF#KB&a~i;Z0H;9O zEDZn7!&Qn$I3wCDjQ-xB4IJicB^r45I_dtw!#GA^87zC|eY?Xc|Ix#|CX1Pg%rCq5 zh2cMWm{{FtHVOPn+lApjd$?XE*g3~)X}vJ~7lrZEER{+v{1FE27uw7H)zf%zcj|aY z3>z>+|IN@C(bUn<4_h!q|J~52omzyo9yVc!zQxnk0@utuur+MO5d9BN7qI84wPeSd zG-HVVr=d~)b7M)qlXeWz|1vZ|yIJFzgp!5~(f{^zt=1|MhclTlX`B%KA5RnfP$JMJ zv*tSVtxBi3ckkB3`<=FQ3EP?TzaAxMHV@ZxOV3CQp(At7@J>`T_|NhbALB5DMjpkZ zw9z7Tq%>g&jXlaCsgomusY{is7)(%=L#2(>Ue7dl>W2Ys}6=IL{Ebq7Eit@asv{#6|ooBgWDs$scH>bfu z>`|W06GaEtzGS!s*`qy6e;;<%)@b>Mf23)>39Y(?dFsLw%v~REILzWSBgfnh0r^Al(Q`6U$Qx) z*+T3Io+Z)=(LF@HOS6U86FrM(X@j>c=ngbnh&{=(L{-BIRhoi<7Gh8KEYaeL_A5RBG>!6KOFpk%Ox*wYM)uen-cTUjX9$?}~&jP?eb5}e$VwhN_v7Z2Cv(K_A%BISMIY~0nuxB?MM zkPak`7fSeS&+_OcSAMvH$)F3s$KC(r(&VK#zv_cGz2xneZr?X^*|t5?bNiNO`Wy#u z^Z(EE7nfJ|?4G^%LVtN>cIndo(#+0FyLD+qTW`nd#4Olh6r!wkQ=+4150F{jcA(TV zMC$u7Kleq{OFjU}wF4v<|3~tfA~}CBKN}GDk~Jh-rzZIvlGp2Urqt6w|Bk#q} zHOG&P-1UHuUU7h=uO5+mp2+>|-u(RK4kIHcBy!PCKKE3FD5LwHmpUJ*=Zn<4?!(VB zP8b=vgGe15U4hhF5BQWVo_y>DB6jHc{QTlXo5@?Lnd=Xbw2d#4FBHiiZsg}wn$j2V zRKEGGL~`b~IlT{pFA~8Ir1)u{G88<>HO9>c3fgaq=!->kF~iU8=mp6)6H)o*38za3 z*#EyBZVa)Ph}c;ze)gYj`_1i6kB&aqirLx`!Iz5Q2iyE~&lwpxEveL)4kv;SOayn| z=7W>Sy-egT>hg2$-9|=E9W?z=u5o~z{h~;|TqGwi;O9Cd?|6XZ3`T5BKg6AOEvx2rMMDSH2c-2Gs`7oW%fAM?- zC(o3O{%=c&)T>46`Xzo&A5$qR=KM3sr;+;KY`#Y1Hm~sWH{|@t7rEokN=E)|>ZQ*2 zUMq4JKaQUp?{5eG50E?E%IQ4%Af#R=QoA3|&r=_uW9hiFqNDGA)(CUV;7bQcyj~>6 zp1{xH4;&ded(cssCFDD)v*17Zg!iQK7I z^K(vlWaMaRi8y)}LN^>xKs#AW)x2HAJ}F`kL(I=+lF^^tSvuJNcIRoN-XT)O*YopI zhOF@4c5mCYedKY69fBBTLGBij`=Q94DznPL(N6i?A=h6V-RY8O^pZGpNtEv& zaddBxN|M5DzWonL;~UrT^HI{+n0!0Fuphm3Ha>cG`1z$h`xbAT>wk*mV?M#peVLk$ zk#EQGd6z^Vnq|=)NG|jjrNp~r3zt-ro}h$m8Ne*zt^9F^O$M*zWnw6gKFYWl`R)m zZ85H=rhb{EO3PF`n{m+1*_zzLS5MU3Zax1zQp{#%`B}9PEE7h7WZ&qnq69^KO95PP5Q$X|9{Aakw*@?2TG`- zN&g^v=1toDF5cX3G1PL!u4$EV3izu;7$ur*=Dl>z3%AfYR~D8>H=Z|>Nv)BmTU;Nl zuJ@-6BS&ggZ#tk;HK>X=4>|yS%4GBWLpF>&v?uL%@x_~|WBa$C^S5Z&6B)6aH~&w+ zxRN$lG;P0ycZf{!uBCWqB$LbqTQ_f^gctKy?aHs`uX{AN7uas`4l;X^RvjaEGYzMG zc_$S+YFnN+nVC#-Im0}G6mE7M>*9;?J(Je4{b!NS_XZWx+C=;=le3!`4)HMG%`&}) zlr`H=L2kR|Z7Z@>+vVOz=B^%oxI}&Cw$zr5^hrqHFG-q-tgy-a9H4 z5Pb3d-Gp+%)+Y8vMce+rCRZ2xb!Hd&OcneT~uY}G1Ybj8T^h83*s1Dvc>kzdmen` z$mGQg?(MTH{ay3qWz`MrvqS%R!^mNSekwh=*O+|+jv|9(C&Rc~CI6Q{&^2|dyhTQYj`Ppaz3$|@7X>KW z$#W0=q-^tFElKx1U;%gmpWc>?j2(G)4LXQ_LD}~t%~vesZPWb?fhS}oN3x(_uyNEZ zR@d{l8{KHwwAqfaOUdd(OqU!pUGj9q-sy`$Z!cVEXN-t-=rFN98EkfU$hMOjmx|?| z4I|&s3X+~wHWhR?s_)FCvzNARY8UOy{RX<=TYTkQyk#>JoYw5WN%rQXl*wLUQ@dm9 zeUhgC#)B%eE4AV_Io7^x&^tGbJVtZU+LGUNo=Nb_l>f=5+A^lvKE=nPq}rO*OD-HY zt#BnRc)E^sOlEB^c2j~az65SxVm|sh624&2uLwNxzhmQDR8Gn#zNJ&xWb5vUB>#I& zemGfZ1x@kS2`$go&F3@6=)UgZeD}A$v8y%ys1uNEw4Rc*Nx5}l({8ekrL_M}28eX6 zP3PM>x*t+EXzgyf2!**R=t&31BRhL{b%&^JoG;Mk9y)UH!B?Dl6b*FN$Q4`ZEyrH* zT8<1KpSzBw6vYcl%wWb~cM=)05A_a>w7PewnO zjD9#7{b(}!@nrOq$>^t((a$EMpHD`=n2c_kjD9&8-8>onYBKuuWb~WK=(m&6?^_>(cdPczfVTDOh*5hjQ%+p{cAG%_hj^+$>`R}=)aTE zNH&VHQJjqq%0>rgqeHUMq1ouLY_uU89iEMj$VNwIquXVpqq5P_+31*TbZj=deKtBS z8y%mG?vRa6$VMk-qm#1H$=T?XY;1>qA zMq}A%JR419qseTP%|`djM)%J~56DIj%tlk$D3^`$*{G0>irJ`?jmp`ml8vg_sFscD z*{G3?n%St8joR6$la0FB=z?stDI0ChMq9Gch1qCpHo7PqU7U>`l#MRQMi0(Lmu91f zWTS^>qixx!myP<_XgV9sWTWlbXf_+oWuqP0XlFLsm5m;jjV{YZ^Vw)28|}_Ud$Q4D zHrktwma@@uHd@I>`?Aq$Hrk(!*0RyVv(e?*=n>iIk=f``+33;P=rP&oifr`QZ1lKn z^!RM_glzQ0Z1kjT^yF-GWj1)#ZT|WSM}m&^x|js;;Vb{ zvwHEfd+~F6@pF6e^Lp{~d+`f;@e6zLi+b^kd+|$p@k@L0%X;z4d+{rJ@hf}rt9tRP zd+}>}@oRhW>w59)d+{53@f&;bn|kq^d+}R(@mqWG+j{Zad+|GZ@jH9*yL$1vd+~dE z@q2sm`+D*Fd-4DE;t%xV5BA~@_2Lir;*a#=kM`n^_2Q5B;%j>GwY~Tgz4*Fbe0?we zWG}v<7k{c3f4UccrWb#<7k{o7f4&!gp%;I#7k{Z2f4LWbr5As-7k{l6f4vvq*o(i> zi@({6ztxMs-HX4|i@)28zt@Yu-;00Hi+|XQf7FYA+>3wGi+|dSf7XkC-iv?Hi*M@1 zzwE^~_u^mm;$QdT-}K_&_Tu05;@|h;KlI{1_ToSF;y?G|zx3k2_Ts_2Yy4@ge>A(0+VaKi<%f5AVlE^y4G@ z@$LHYQT_Pnetb+nKDHm*pE-| z$9L+-XY}JU`|(-*_|E^UTR*;gKR&k~-=iPjvmf89AK$wl-=`nn zw;!L^kI(PN8~gESKTh@IbU)7Yp6?8x#VLcW6|JZxaD65L*UwD3XjtN9T0TYtMEJ_B?PQwf{q#43w z&K`uFR8)e1fEiIS2TUO5oC7K-WDp^-WAvx7@VVHT46A>W7GhJnSwx`Q^_gik&N&;6@qf@XkLV zai0I2MK?l{!`7h3X&acBL4{a?qazhbG-1$crHqDZ#vCdFcqO0?Jl`4>P?R&S3Q_iE z+-H+k#K%}&D@~cA-s%^XHPuxE_4AE5*$j6#U4r?nRGyv4ED zEBcJ8si+>MA&Nlo!q^ao4drjG)#zvL-C6A4NwIS*ri*+M6MB&xvR`#gO)s_(CGb6% z$PZ$ilB|w1nsHu=XQ~}GxI!#2g;dTHJ(6D`LpUR-7Dqp(uUZMbuCi}KEw3FV?z?%= zAxdJLuM#1r2EUD|nWCZBRty#CNQJ+Y@&Aw_WtUQ+A3Dxvhq7H^@=;FY8O8ZR;SOV& z|EyG9rLXv|Om(A9R%y+^dOZOrQiiQep)V2am(^8>ER`Dhct$@Y7FF!17^r0R2oqMO z7HC65g=nDDkZ)kJ?u(JDt8~PpS;!+sia9H5>Z+>y)|E}shTXuDxIiblp@G{^b`a;g zOm-(Jt~hxleW0T3A)fgk#gsT$Xk-m#)c2%?3XV%E^kc=L%&)6tU02D!(8cjEleVw` zW*1m1PTWddO?cjPjw((KB{D;oG3;4ssVrp935ev6#&ut&YHkk9a?~Il7~)ELb6I5l zXmAq~e3RmoGr~3f>e-$ZMc*;}7o{W43YRDNEoBuRuIo3E_%>9#Ymnk;wm>WjjA-EiBi1-Km&tFc0Kq*Dv7! zy0CPbtKG6rqyp7$Ig^=xKo?FeUwhOS-Ddv5QYl(#3Z<+NB{`8Rx;aM=Cq6lOrOfLf zCg%z#zh)|HO3VA|M)V2ucxXXk-Fj=T_XHmGE45V1yYFsMxOz!p$b)#sG)BYQ!SBP*1 z3}l6>80TmvcxTOySQ7f`t!HpuPD-((Rj|EPjN4rMLBD}@^|~kb z7(QBZ%c(&Q#bF)j^3u`+? z&BH5J)|+&WUts;dtbS3&P1_nNEtr%eW7arPrmxs181g~E-nw!GrsB-~c+#H>ZmF8B zCJ~~Ru!ngpCri%q3k4{_^kQMoj764+9h$MgUeU-*947W+VrFNBUt&`!)iuzzDE$$) zHS8d*xLZMqY7~oVnG{un5_@SCFHTJo4=~N0)clp@)x-4FcNz=vp!_0X8j_3TLFQ?L z+HT@lUuj!JYPaXsAA>4HnN&&RP#*UY>AlLU24<^u$JT>+ek6xiAvb@8)q}C#P@FW> zRSvC7#EtD(mSsvmqDCM}zZ$bQ@Ywe#X5&L)zvOZA51yk|@|25CbdPgA^R$x!Rwd4& zWehtmW~r1P5Y(96$V0AEvsTye<0QPRD?xQ;qBf|dTcMwQyE5h;(r9wDCJ(UJv+i!l ziHeo;ucP^ajNTC2qlo-;@3)>sHM}6od@WQFbtexUDtKjiLz!+C^BMX`Y|J$SbiMZA zVJ|CaAU^o$5$8H)cC*Bkb@n9gHd6%#ruwz%PS ziEwvc9`=HG*kOZf>uYu2*OXP)T?)TahU;oUKg+B&m4J%sL_~fK1Fncit11`TP$(^V ztVIQF@PT(gqS&)HEAycklijndJt^F7jC()~D=n{W7{yCl!R}c1)nS`f+IftrNyjq^4=(azYR1cW#(xwixpQ!0KM{uM#3mo- z7c^{<`f4i|QhZ=cmhJCh%rB*2*_<0VL8D=gW!UwxX~;UMzR21zr&US{j4NE3(52$& zF4i+iYm{{zQI1yoV+qsrM{FJ3DWFFgXEWAjH7*AYWrT!`Mp2cvR2HX(S;zh zJKM2}G21h2WnKp&?Bzsu4Dppa8oF&V&h_d53 z%;g|yi6VJcIZ(H!w^+P)=co}OslHbn$Wr5DQi#3~!!O^-rf<3WdM zRwdV{&gLDA+#(?&y%W%95#61)tE6m?`cYri_cE2w#pWh9sYEDU!fW~p zDYy6_uM4gvia1#z4nzuV6N|Ks5~X zFT?X0Ypfz=VwG`{L*Ee$Mto7p ztERrcuCYCt%%%z`mnK*1czr1zMdwv_SJ;ARh^|VsL_f>qHp{KO_ym-w^j*iI+eeD0 zVC}kSZ{?xKjuJ!H@wQne&drM5-rtAt%^Iv1WiA2azQq`*YdpOd4C`hj%6ak zQn;&l-gZh<^nf3jW|#k9!`ywd1E#$Fix+H;jg z_hGcrl4!1ZR%GjShQ4ChF$H#OlI$*Ec6&%EiDRNJrsr5p4e^+w)1SSxB1Rkz<`51->t4;YC=u0 zB2QbX=V|A&Nq5YO3p%2&jZf;sPhYPWF#|8;OtD^O zl$1>Ru^>mqg5=V?9_ffS<&UHS;_WETk|;!uVtj)j*-|`(CtQ;kr%aJ3yexwt z^;1&1L$~(DERmxM>q6XG(KB))3hJX-M6JG8y~KRnk=IdWV&6NA`^_Rv6ka zX0u|k%0vTk$P9w_F()OAOx!L?wgQXp z-Gg&Hb7?R?O=h?{l(4N|BFj^<{eA??M*i&H31(EO87xh_QavWF&HpY9aPxa*Tpy z$&_It+j}|xph;fu@-maYxy)iIJdo3?zSnhOaylxDEE}Ha;dy|8!wVvZY$H;QNrU8R{oxmR1nDR5EUm3I_%I5?Mq-%6m^!%C|XC1!(xEeqq;iQ~EM zw1f=4mo7uN<-WR4n9S;`)I=*T+vr4zC~HYcdJSs^q>N{iC+AGVGE^oi0z1X zYdsPu<{>w^LYwNasL5y|t7M%bNaQ?ND{2jOW=$V2H6SAG#5J4mS-4x(^5S4L?>QB6 zB~Lt5nL=)l)ds(vr!I~aSXxuvpwqmRt>I14bU#GwgreTUkTnM%yV6ZO647*?TJ=A6V1 zcQ9^Y8s;ilR`S6((I>Hq<7vwST?N4_{`~L%A=Rp?Pwn;7cw; zSbwT{>;fM2cDVw$SW>BL_E475W13OK9S^$A74a{YNe#&Gkt^t$dPIqJd+b4~`s(g_ zCeyl~qLpiZ@usGX@g$~oyJS>`a^55{JZ8gPJ4B%U#vZ0BW zwwhr)|H{{XB`%QVf(7-PC;2x&$K=PENu}LsO#dhOCCn>W(@?~uAFqjQ$F$|sypFDs zw3iL9(_O}X44AECQduJ|qw4zmng^b)Q!H15u8X&d(kC5KG->k0ai>J%iY_K5lGoz3 ze6)L`z1XrJS9;>Lpvgj9e;TMrjt^0~o14p&wUoFrNY*`X4WoXph~m7LzNd={Z@J=# zTkx1;ZQ9w)(3NUhzAP8tdQ;+G&*&A>2&8>5MN0l_n6;)ch*_!arxyUPVc2d3Scwk1 znqe~&Q^sMjnsY7BX~)RYMJ6f;uQB%2k-|62#)pjTux^mV-tQ(USK zF7Kady19x9m&YU<+6}x^+b&KKI`;og(vRdmvGOFLOqu$Y9lEss}q~F z5}_zW9a3=CLaB+~#i=~!kOExz3tn_;+}jwuQcW9IE;O(xgbi2V+}@^J>YY6O<&q_4 zHNnu{tn;2Dg$yfsuhvO^o(FwTLU=$fBu>)U8OdTeBOb3Jab^Y&_jt}!3XVy`?9G&% zr<2NssN`yWn}0DUHqmO4mrycn$6j$*3=sXl`g&Q*(>~@1E`*n^>BpIVO*};mZKj}c zrm8-XsXC7N*&_8;AyRJIq%&9w9i$XE)U8b<^SE6Q)O*j5tYhSQ+8wa z4wbm_+%d2|k+XP|3G(vcCMOCslD=k=1{G9S-R)RSd6zOp?Q+o%*A5b=*?SrB*#a*^ zlDvo>!TC~hGKE&AtIuS`-j#Q=iMGun7;BL-mSiDREN@S@!8i;My@g5&PcZ&ug&)5X zp>NEuu^ifIV~BNKo9m!fgG}H-PLnH$8)rHDqX}y(Q@%w~&iR%^f_w%etyR+CW^jGl z!x%V3Do6OcA(eV8@h+3}SYA*AxNt1`xpisv;yLe+ts>4H_kSe~*0VwU zCb{4OSRajtGZ}DgUiy9b@`MK4p9%d!H!|Jx_GH9Q6^p#*ihQ7wn#f>mQ&7G{!Ph7> z@DK*?nzJOiT_GCvB+i4R3k|wWI7iNTO@0g0G?vm9W2o}mC8?;=&U@hUojd_Jw@c3KViJ)ic* zWW}9t`Q#5rm`47(_i`l~ai2{OMT8CfZsz&O6{{2zd#@XL zb0*})&YXncMU zfQK`1Q64k*wt^n)iFbsqDfo(-8vaIvX0V^LE-scriaP;%Yi@BFizuaFRf&{ADZ^&T zMai*-e2qepyDtwpH#RHrMv(e@2R4i#{(Ic^ql@laCUa?Q6T-#nAhD+QRk~n5+b>aY z9>d^9MJ2x)q_c1{1Ji1y$6a7bkD^6;XJx6?H4Sz3J$T(Ics&!mRT^D`NWdntN9XfW zK0+s|p5v3)r78R~dGg29_+sg5gBP)smMXn)t3ySi)nQ*Y_;(bzM9=Xb%%H`JCvGLv zPfnsip?yIbiHh}TrspVy$oYlD69J-!s&@giI`J;iR7QPYv0I+=UW!v;ghMpk?%g#r zx{`4>NWE7iGyW$qt*0q^WXvkcdzz4z@VIZOUsP9=@D~epct;*#NxTwSd$KK3nVY!& z@o_p6K!!%mcr!zzwqE zsN{4Y11oen>Gv_j%N|EaW@Ky=Uolkdhzp!wNobA8eI}!uaXjv8iklrOO08LlH%U$e zv0@j{7G*~s_5?*PmrrF{OcDGHgWD(tRL0Hh3ObfY9;UOSN5rCQ){q2?$9WQuH!R{& z7ir|`q4M55<~w<6xeTNqVqC^MR$5ZBrl^GUG9%xrxEV53-Fxt5tbobW_cp-E1oBLQ%xe0SDHz+XX>UYVX`u0o<>P? zIfHl4#}1;!SkF&g%l>ALWIcBkLHCgD*d#ZM5)_HD+m25boxrH~<`xN0sVQHiXOD3O zo+$VCouGjhFeBed)rt_F-*wR!kHx?@3KGy4`yLD$B}vIY=A@MKCC}DHu`gf4(<7_% znEfU(F}$M2X|&AZF_*^-@PR=O@`mw{Es6yLq6AjP-!jrFU>7mkVaga9>I!*HCGykR zCi=$I$`o>kus#9|gXJs9#pkiZ@ zm-iH0^vT!-G1XRx+pP+E6-#MGOfmOC4@mSu@5YKYq|V~faU%IFHlr_ zKOoh~dDsf}uPP7QiIGgX7)5iTF8Rew<)8u=Wevk>l40OY{DURZUW4{N}tIp@QFekHO8%i=FHrl-; zixtVMMmI8<8zq2Os!Vz4arY@~Ihg__xhv{Qq?a)*wGx>xgNrLKiu-ju>}sV4_7Hmd zUff;1N-{6re+rjtQe?kNyOqC6qS6M)&$*^VIQgi#a$^y zqsPNdR5XgsQC5HxXVAqg(A(pHjnDUbPolV&d9s?6g(vS$X){01T!wOCl~%=fpw-Nq z7#~Xl)s7y;^nL(wndwQCIyjv(&!Wkz?bq+(F>{v3grx(rAbDH=DHjGOw3%^!4mxsZ5Xy)TDI&q(FvZ( zpl@=P^soNY39Q2vR$g-AY1KsX@BnTpxn*De0qTzCQQ6NQlL_)>yChQ&EjK}F~$ zo+8kTS&y<EYT4b_Q# zdIj_IY~B-P*<&an^kuZ#ynqtf{dFv!=7rgKRjE}!jFEm)3qU@DlL+wp@^t+aJbuPO zTOZ=m+?P2M5v6qbMyaA`>`qOKz7}l?TodCje6c0W%fD9m)qnakM{a7WWVHAv&-0*y zaSXx>PT9^D2DU5g&KzS@CmxKPKTA#JL8AkRcDR33AE?_SRxM0WT-VVA z+>Ynzpo}8EeWi#HtpO|48k62y3AqUi`TP8++JhBJP?LG&F|L?aG*9Rb@h3)YR7NJ_ z_-q2Q9sCaf2d!GEiNb+Ky^>u1ny$=Zn;QYMvX}&E@b2BrQzz9I)zck z$L^8WYd<}!Dz1LcD=3B4nRtPbn4)L%B9ToPx<~8FP+xH*?tyW8kK*P@hW-*SX+8II zIup|&$A_rd^i3Qo?q@cNiu3-8wae*2ZOq|p=L<#&u;|~cOCYlw7VbP^oY5yD-`*1p&!KU!vgf0=vYcVvt@MiY+063GYJl<`N?n`88svcK;7@yS zB00U+v}}uCviLoVEm^d3(b~m6F7|V=zl#H09PZ)>7e~4{+Ql(0`nniB8sTW3uX(~8 z+1L~{vl+TUQB&Sc&jYn*PPlH+D3d zG7P>ewkE!HtVbb7Fe_hc640HfC?weuEB8RXlAEY(9VbZ@Ya($#+Q{txl;a|9F4kS) zR7RYu=;S9&^kV%cM*S$Jl5IYltVsGy=uJ7p+Tpa)k+pb3UgG*5CDK5CPK9xYp5ove z9_~TOHy^e|Do!1?D;TMZlUHs-oe-s-K01$C7*X&sA|0<>jOc4>Eq%F2gbeFbS5{gh z0v^>4ERu_-7WkJ}Fmw?tViDX`fOEiHGce&7e&Zi(Q{vsBE%5>-ZM&5xU1U5GPY?`a zTwix{OuAZpcQR$O3p2;|nb;Y>X7nNPQWBk#35Osaw(42H<|mPLXEu{DOSFj->rB)# z4^$3c+?>)~^WD5CEKM6S<;_1(F7`_1`ON~)JKPj)&oehG%&f2PN}l)90?D!e({=F? z<8Dz)qe^rED`|<|(G#UCavxC8oXU?Zi&qrM^7f=g?_O+p8*_Fn?}6=b=})9jHc5)* zVJwci6t^bN`$l2=<5#S-q1!QPd4VIbH`j=64~0FOIXWRnb>*-`(&`7sJy!{8cp{tn z5>HxR7`Jjjm55{$Z8)N(!_BRdu*3IaTh369svRr&?TKLB1!TTWCuj^m3&$@p51l zFAgQRj~Tp+l1^3PZ7lIL!=?)U;Kry)lcG^Uz#;stDdhuX!znz=nRD~p6=H5wT7`@%wv~T^)C}| zovOLZ7(w!361aVmo^kaCEd z=oJx7nZ#-FY{{m7N z5tw{8|0U)yqZyU>&W$oEk&>9Frj^mhjwuIX+5H}iRDM54k$e^dUXcR}cb305q)c)z zUOXR&4)Lnor-f9f_82^ z(T@vNlQfEJ*+x<_oDjlecw7TjZhE6dsN`6+SH`KWQ~7em}mscsss9ydBRIWXyaxB>ad>%xZr9 zGXBNEQur0IP8Hn`^ZebEXzQx=&3__eU71r^?sF)b(ps@}FN_5x(g(V)*qsNhb@Bv> z9wLnv@#&b|lsLqWs2|F+j5<%Diae8!D>}NnS3CALG$8xRjNL6CG0(UWwuw$ao2xsg*X{0 zJ3p0?kI6eP&M_w<#089e^>IR|oVwNYun)^*lGGB{aC9wfW?ENElZ;J5ys)Q8sb_n= zNHJ2EFYYN)#G941+EV8IP%Y(FY!~M#n;D*H`gnz5DYZ)C?}VvIFXc&pQ2g^_mwF}6 zVLt2~te9`RXyOsievgS|D-INi%TqsbFH|Ry(i}T}Qm>xV#21&2%2(9e{l~xa0VK9w zabZ@M+Y!wA+`Mbh^Sd2*{==mP;*)9ek)p?0d2MnYfM2cFi*O>r*QS8TZ-VRI?=D7s zFIFrs25wN*)HITXGAPF~w|whv{w)Sgj`g0nX1;~V9~^5SzUZaIFB+%s%&lk9nNd;W zYf~N0WSni~7cD#C_@O0b5pOW|BqjZ!iLh!j)AC%*LQTC+e+dJcXiAl_dbOrgmqk-7 zG3D92VpR8TqZ02#FJ-cJSH@PyTZ-DR#R>KxWlmgi&n+26vdHRIX-3Quq%z{Y7U>C4bA=mdESTm5ds7X^?+y7Dhpd|U4 zuz1X}xn_ll{K#w}=Gb~m6R*)-%X0EGS@i6tY2Xe9j*3^2$knrAm9c%vGCau6o0IH2 zNYn%-Q+j{?DDMt60re5$392s8j>GUZTo*`x^6wJDB=yPESo-Ds+jnFQVX$U&;&yK? zL8}BUI`yuJDVHgCjq?3?0nJD(gnT((VXtB4J|88R)1DPlte?bcdM92Dyr2grQkO0( z;d~{|;fV*wM18VaT1{o{i#KY>4+TvHY33hiDGrhvpT(@@StF_4(kgieNe%oR z&$(Da9;d3P?j>8juCq0;=OQneFI19~*B{gIV7EhC$ z9r8Q;RS7$s#df$(F&axZ`Q5$F{ENl0bZf-3Yiis<%;b9oR%Ex80*Yh98ERay^CsJ1 zRx-IohR~>}6;>tov|?uTq5NtVWl?R?ZcNRG%GN}UTK8_^QLv}gdaUVJs|Pc?GQE## zKyJy@mhyHUc)cQ+1rc`=D2;bv_-C;gWW`)@I);b+UQ>(g!BS{8^LaowKIZo7AvtXj zHxoX~pLD^To*xfd)i?1lMH3#iuOhagt|oVJK@EHj)3ZsRmM=?a?3g_7Ho4yT=^Rad z7x3R}G#AaAhjP&(1F%Z!M4qX{w;&Q10NOJAB1KbWP4ZPwaTBXXngee-;vHHgp^q5v zZY5g2e<6~OtW?E|Nc$h9l*$VuK3XR_na}1y=ES0^DM?)WX~&}aMU%vUWOh=VBU)&K z?|4A-dEh4%dVC5^+-ghn01qX9z!8NWD2WRdncOZCXUG-rukhlVCG{Y$#OZO*zC7*| ziZEGx)nt-F)1rIj*YO)&e7wpR>^PQH6FtMF=U$Z@kco^DKfPTvy=Oii zJMusMnGdt^+7(wM)hMEw^k$9MyuVPY`ksIAL5wKQJ^!l1h`LBx*+^Wv+TqnIar&I2 zej@sm6OGE>F!)ntExZtUjmvFW(I9-l1xj#iF5(_n;)|B=vY_^r#v=8}>e6_;jnN$m zj6)y|w1hz=lDiUqPe=nS=K)8?#x0+v(Li4?=!{XqlkL#j16KXy1eq1$#&4p{>NQ3# zSMrvXaK)x5B2_9uh%2dy!_}>9K8GvR${qT6L_O@J*zV#lWM~xs%&@nV0_4M!i8FFX zUQmy#kyTzsGfwc_ye39|LRD_FG~v(UHaZJ58*DvU?p zV`j2^Ru$wU9*RyJ8{0B}pXG>`b@v4IW0?8_3$~Z+iNBlqelRyRUv$uvA|7iVs9TE+ zqRJCyJ(mf8CKfy2lIbCvKGf26c;2^Ts&;(!as-2V$XR8wB=Lox=XlJ!lgcjTN3Atw z|IU;xma>dfZHZH)*fY+K?M#S5k4S~zJYLRPTD3!y{r8MDASQ@UgL-N0O@>s)EQ&j& z`oa4hK60LUG0ni2(*$4?ZuZ$?c%eL}>BuutAS9-~;19mpCR)0vGoM+%dW39%uX z?CV%7OB5n|g@i-ehxyoBvM5}QcoBkqzY@E+t3Fy8yC~@IWRzmN?>aL2Z6<;0E69gYH;$uc$o$3=83RUdh^Wvovr$=?E_hICYRvtNb^;@A% z;#unytDMo)MSCCfIZ@6lLh0dpM)3)Dmlbl!1QRBW9Ut;zDe-#QFTY-nE_kZs2YTl7 zsCOvQ%b-oq`~Sl9HjVXJTH&2C)jNHXCc|r()x&a2hSQO{cpqa{W-CTz4mtUVz}NhP zkJS%E+oUG`qj}n=G^#lKPrQgJ`d+6N;C$>DDtw3%&qa%C6-C4%XjoFO>JNvWgv_^x4MHAEZ?buj@ZdyzZ-(;%Q9L6e(nWmRh&_ zZGzO;9K;z%H+%8Xx+|1M#cT5_2eXQ2x-mDC>cCW!wdXNsDZ~anb?_D=b}KL-g13C} zOG)Q^PJh>WaiffA_0d0`I$HF#asqsW{CMiaESg7+>2>MH3_NaNo`EL}JZa!51M>|m zFz~d2XACSf@T`I73_Ne(1p_Y{c*(%a23|3+$iQL)uNrvGz!C#X4Ji zpBwnXz(xaK8u-e<*9N{Z@U4MO2EH@!y@4ML{Al1O13w%1#lWuyelzg9fji9Jm; zH_^hxUMBW7(b7aK6Rl0`V`5(u`pCJr}ogoz_f9A%=jiK9&%W1@?Rt|q#f=x(BiiJm5UndohzkBMVVWK0+)OcRy~ z+k|7H*hF6wB_>Ku^fOUrqTED(69Y^PG%?7;U=tN4DoqSAG1SB`6T?kZnW#2VW1`kX zor!uA4JJmI$eM6XG@2M`;y4qdOpG?+nea^nCPEXDiQ`S2VB$m*V@#Z6;$#!2m>6qf zoQd%!CYU(Y#6%O5OiVU$nu#eUrka>$;&c;dm^jnKStialagK>|O-wg&o{1SI&Np#^ zi3?54G;xuMi%nc&;!+crnYi4<6(+7Uag~XyP0TWJjfrbbTxa5X6E~QcZDNjz8%@kL zag&LgP26JQRui|GxZT7ZChjzGmx;Sg++*Ti6Ze_8-^2qZ9yIZgiHA)*V&YK~kC}Mf z#5@yEn0V5}Qzqt{SYYC56VI4fXyRED&zX4M#0w@~H1U#&mrcB4Vv&i(CSEo1nu#SQ zmYP^*V!4SGCRUnw-NY&rZxCf1sG-^2$dJ~Z)>iFGDE zHt~sx^(Ho$_|(K_CO$Xug^7(OzBKWbiLXt3W8zyAn@oIX;(HT6nE27ePbPjg@r#LH zP5fr!cN2e@_|wE+CjK_D*~AtTTTN^;@sEk^CW7TR0r zV4)fQ%1xW>Y@7Ot~! zy@eYr%(gJc!i^T@TDZx=%@%I4aI1yeEZlD44hwf$xXZ%b7VfcduZ8<8+;8Cl3lCa& z$il-G9$H3m;ne$ig}cA6xju!g>oEEPQI=GYg+v_`C0S@_4ob_+!|V1sO=Y@}`M zWMgL=yV%&(#%?y6*l22FcN@)Y>|tY18_jLBu(6koy=}C#(aJ_^8~fPU*T#M}_P23> zjW#w8w9(c^I~(n7bgi#uGN4wDFXU`8F2Vc-qD@HWu1=*2Z%- zp11LWjTddaWaDKUuh>{*W3i1_ZMJ2u|6@t%#fHr}`KfsGGsd}L#tjgM`7Vq?9H4K_Zt@tKX!ZG2&4qm3_Zd}ZTn z8{gRY*2X3q-`V)y#t$}rwDFUTpKbhN<5wHM+4$YYA2$B9@t2LiZEUu&#l}_}+id(} zW4nza2XH_RQV!A%c5<+@gIyf#>R>kqO&m0Ju)Bk14)$=cr-SAWS~%Ft!QKv9I%wsf zwS#>e?CW4Z2m3oXz(E@a2Rdl$pq+#E4mvpK=-?m+og5tO;1CCgIylV1;SP>)aHNBy z9CUVYw1Zy&d#%aIAxj1H*yoz;a+aa2ymn=0wFvG$54lZzTp@W$YE^=_OgG(G- z>fka5mpiz^!IciKa&WbSSq`poaIJ&u99-|<1_!ep%yDp|gSifFa&WVQTO8c#;5G-h zJGjHaoeu7DaJPed9Ng>RJ_q+Zc)-Df4jyvwu!Bb&JnG;v2ah|L=imtkPda$Y!F&e` z96asd83zj;JnP^&2hTfr!NH3TUUKlVgI63ZaqDn_ap>0;D-)ZozwkFp-Q9yNM2(xc-%8s*Vwk35fj zj{=WEk0Otb_vi$VPV{JuM<;o7vPY+QG}fbW9*y^Cf=8!%G|{6;9!>V>G>@iuG}WVN z9-Z#d86KVK(ODjy?a?_No$JwbkIwUGhDYanbb&_~dNk9ci#)p6qf0!x)T7Hhy4<5H zJi5}Ot30~eqgftZ(!6bfZUeJ-W%Gn?1V4qgy??&7<2ry2GP8 zJ-W-IyFI$cqkBEN&!hW2dcdOxJ$lHahdp}4qene@%%jIWn&;6I9zE&NQy$ItXn{vh zd-RM)3q5+)qvt$&-lG>hdeNhoJbKxqS3Fwe(PEEY_2@N^mUy((qh%f~_h^MjD?NJM zqg5Wg;nABOt@h|GkKXoZjYscz^sYzmd9>D}_dWW+qYpj$$fI>0eeBUE9KD9{uLg?;ic( z(Vrgu<eKE% zHS=i?pZ4^rxlb*8+RLZCeQN1bE1z2Xw2x2w`m~=<`}=f&Pi=fU(5JROwezXHPaS;f z=+i+yb@J(8pAPZqP@fL->2RNp@aagOj`FFqPe=Q7j89#B>grQBpSt_h!>67;_428= zPknqk)~Ae5hEJwXmQS`%j!(rt_4TR5r&6E#`BdgpxljFl8sO7Fp9c9f*ry7gDt#K_ z(@>v=`83?8Dxa!-s`07Tr#heNeQNM&gil$YT%Q_!8tKzZT1IG@J*G{L7+eVXXgB%dbxbed07e46UhG@nlQ=?tIF z^yw_0&i3gXpU(AZx=-i%G{dL!eY(J>3w@gD(?vdA?9(MaUFy?iK3(q96+T_*(^WoQ z?b9ruuJP$wpRV)idY^9aX|_*ue7e!6xjx=)7?JZ z(g^SJ@3;CKE3GEOFq5q(eDixmix5Ar+>C;y}eeKgXK7H%cCZE3Z>3g4k@aadNe)8#OpMLS_SD$|K>35(0@aa#V{_^Q> zpEmon#iy-4ZS(0LpSJr{6c7TUfKmaa1KKH|oden>pj`vnEuba=H4SL@fSLugM?iZ9 z)I6XT0qqsg-T}1?s8v9%1KKB`eFNGrp#1|nAfPq@9T-sCfZ7GrKA;W(bqwgBfI0Jd=SfO-YgJD@%R9UD+4 zAR{0%AS)m{ASa;Wfcgeh5>RPC{Q@crs63$l0SyRfU_gTc8XQnXK$QUv3210Q!vY!} zP*p(H0o4Rl8&F+9^#L^mG$NpEKyE;d0gVjkxPV3lG&&$JAU~iWpfI2)pyLBNA)pfj z8WYe-0i7JsDFKZQXk0+!1DX)fsR2z4Xi`9v13E3BDFIClXj(w02Xsb2X9jduKxYSZ zPC(}dG(Dj60-6!f`2k%J(1iib4CtbOE)M9DfG!Q_vVblR=!$@@4CtzWt`2BcK-UCx zZ9vxrbbUZK1T;IKIRV`m(A(#|3664I_A?G{p#keY_Hdq~Yf+9RYrLuwvUi;(sT zY44C)hSVyg)*7t;PA9S~BRkPZx~ZAk4xY9CUEkUEBRP)MCZIyj_5LOL|0 z!$LYdq$5H)GNhwI>KxM1AsrJ^myo)K)Geg$A@vBUXGpz5>K#&_kd6&06Os{<8Il!} z9g-7LaY%hbDha7Hq<$flg;X9=|BwcRG%%z=Aq@_xBBaWYhJ-XUq+uZq52-4o>X2$e zstu_wr23E=LK+cLHY7Ks#*jvabX-WILK+>C7m^=R5Kh_oexSy z>6DPhhBPju@gYqJ>C})WhBPUp$swH<(v*;HLr`2g!EuY z4~6t_NRNc{Xh@HR^ms_~LV6;kCqsHFr1>E&284hV)WM zFNgF>NQ**R9MY>Hy%y4vkd}tDETrWjtq5slNUw*qDx^0;dNZWeA-xsS+aaw9>79_? z4e7m*)`s+cNFRjsVMrf^v@WENL;577^&xEt>C=!t3+eNaz6fb!NMDBZRY+fl^i4?L zhO{Z9??U=Mq#r{1F{GbD`Z=UuLi#nN-$MF5q(4IXGo-&l`a7h}A#Dk1Ye?Hd`X{9A zAr(c0h$x~|MCpijifHGEc8O@$h<1ypNkmN}+C8FX5$zGto)I;Vs6|A3MYMNBEhB0b zQR|5IiD=)5_KRr$hz^LTO+*Jq)Hb4a5w(w~Lqr`TIw+z}5gi=SArT!K(P0rC9?=mI z9U0M45p|B}=!lMqs7pj$BkC4W_lSB#)H9-95%rF!PejK?l!?fQ$c)H}$d1T~s5qj& z5tT$#8d1N9$|5R{sDDHQA{rRcpoj)XR1r~SL_;DP8qu(bhDTHtQFTN$5!FUi7g2pg z4H1oqC>xO*QDa0SBRVdkQ4x)f$cxC2D2OPGD2nL#h)#&;#E8a3bW%hoM|4U=Vc z7esVnL^C70D58rax+J1YBf2c2%OkoXqAMf1Dx#|+nibJC5nUV6brD@3(G3yJj%ZFq zH%2r!qMIVRIig!4x;3KPBDy`IJ0iL>qPrrxJED6cx;LWxBDz1K2O@efqK8=5MZc-4 zl6YoQE4GRIP=gD-W_n9|Q?5pRqOM_-Ctd>)ZD#!oHN4!%A5@WQ4o}%y)k4Kn{<*eY z^$YP_lBu<0>CKRfx$OJADggGaso_2Vh1iT|o~gJg;|Av;T;NsUwG4hNF6HretGOzy z>TbQbRM=IcNi>1!7Y$}GML&-c)!q0CwNBAArl>;IJGnQ3yQ;NGZ($)Gph|jmiQA$s zmv?<}_g<8CxjeUpOO^buX;JaN|Hv0P3NjVf^z;V2^H`=k%UYypaZuj_Qv6-PM66d* z6RqrtD<&-9b43Fh_=e*9lk{D-Xg zvvQp4#oZK>H(Do;UuYIL4RxW5Ck-BTg;DUMr};ONwXu7$(0|g5MsJgu$|SYaB&6Dq zlz<|p;6bTUzWtTeX%;VomBu>ZMuO5Rz4E+*u^uVdNp+Q8^B12TSehePl#eAx8o@)D z;A3Ms$*!>EC8d{HRPCjxdSevkg1Cfi#WYZyD`ULzskY!HR2Y)Io_zjYDf~1Z^&P2j{whZD zi*7E1CR+LC650Nwv$~kM`7Ot4?z1F`ez-FkJ|Mwu*}pzrawAi>qwYc3su)uKgTOM;6*eR(#VKxP6@VM&>8%(0VTzm!N z7L6Z%&|rXg+Fc?4z&|)p`+@%91ofkF{G-ofj>U_unifxDem5z?mB&|@;!es$1y|q8 zRB-Y5Vn1#AT%WB*;PpIrH;sF--{?<=ozF95bhvsIL``xT|Ku|D6L~Y8+eH+39fMEM zO=d`PTY3gmv?l80@Mj2%ovw}?i2pxoV(z|eaq+Rm$BLI$C_VjszNsT#Td5YWtxR9V zJJd^=>0R(j28%LSoWZLZyq3X|43=iFEQ944tjN&H3|`M*RR(Wl@MZ?9Gk7b5w=-Ci z!8;keo56b-tj*y43_i%oeGp!KWE~mci#4e38M%48F|Zs|>!* z;F}D-&0tf8zRT?NeJ1roCiP<`^;0JGb0+mmCiQD3^;;(OdnWZqCiQ0~^;ahKcP6zt zliHF=ZOx>%Wm5lSQrk1BA|nMOMMf%Rq|!!eCnL49k=n&b?P{cUGg3{AR8u3hyMbl~ z_As!gf#wEU7}(3e-UeD4Xl0<9W5CexAILyG|297Xrq=BOhbT)9bfnyAGG0@dOHv`=b^f1uVKraKm4fHW^tbvRH z!+>ePGGH5U3=|vaYoNqHseyh5$_$hn=x<f&@h9B8&qXb zwLvuo)f!Z1P`yD728}Q%YmjSDqd_ALI?kX`28}kzGsrh6Feo%AGU#}NPB7?1gT@$i zl0hdMbc#V^4U97|-oOL{ry7`OV3L8!22L|D#lTbp(+r$$;0yz28aT_q*#^!raIS&r z2F^1u!@&6lE--MRftdy_GH|hhOAK6U;4%Z38|=7t)fQ6xzKgQ)5yB7170j1u^d7ZN zynxS_4vRZ!`)Dh>NvbKgJ&C92#bZKj)nY9E$GeR5pW@wS{r6&>zND=pb%$2b(45!$ z%^Hc)7isJ8dyeK>Rf?W|Z_2b$^5x=h@;BIjPg31?i#@BJj-(OSj4 zO_Id+D-~Z2SDtt?)B0Uu7m$6fdRMgQLHttj!V=Rxrnug{IG#~_ZLf(i0>D_K*C&VpmSytMR>HlyG8~dRk^-88}QKoirrsuLu>lK-BQ>OD3#`ITl zrP1mtqs7$*%`(8PZuU-(8@tRi(oY!aCk=YaNX<8BfsuaNNIzqw7aHkj4SLR?=S81e z`b8uCl977Z*y$Bxr$t73v5|V!NWEt4yu?T^6@6~$e_UN_RKjMN)O`b{IX z+DN@+q~12tYmC%8#;)%g>GzD(T7%vfeQxyOf9-Rl&yDmKMrxyx`tpCR&yD^t=ud3Nf0FzH2;UNY%rlU^}tkx7e9dex-YOj=^nQZv2GOfNTSg-I(- zdflW|CcRQ9IG+Mjb5bDEi!}la)Sr$38bY(n=py=yOYTv8by>-Ew_y)YD4!D)hNg z#v;Qa(;~|v+akxJVk_O(N|%T}w{$-%U1p`rt#p5j2ITtOQiH8jg+-O3&y9v!G_26) zma4H*wN|RmqI!!O{&SyOYP9HcBi~8|qR)*Y(dR}dSahOAV?>`DohiHs+FE5`rPOYD|P1oPM;fHQRs7{|I+7{%J;d^|4N@5{g*yB z`d6PDX?oC#k5!Pu6q|# z%VM-DZr{2%wNLT%`--MzIY_=Li>tGkmBlq#T${ypSzMpR4Oz_2Vonw}W-&L5o3gk$ zi(9g|HH+J_xIK$IvbZygyRx`Div?Lcoy9X*EX?BBES}5a`7B<@;^iz}$zo9!i?et& zi`TMPlEu<2mSwR#ixpYCnZ-|8{G0_p=K5# zve=$QkqfvW7bzEM7dyGw*~Km{c6G6vizY6by4c-CGZ%Zf*waOG7cE@uvIsdq97Z+V!baT<& zMGqG}UG#F%+eIH2$GXV4FkF}}EEl#5$3?MxkG8}`sf&It%3PGY=x}8eNQZah!`${GzQ3&xP+Ia1pwQTpaJ>1Q#c|7~|q37bm+o z#l=_`<6Mk)F~P;DE+)E|8!^N2{&T?_Ki*sC@>tec#^IXhu zalVTSTwLg4ri+VQT;<|w7qeVkGD^_qe#%#eFXBckzIW2VFem;$at$xOmjXV=f+dG0(*lE}nGpl#BT; z7PxrY#WOAzx_H*bb1t5D@q&vNUA*MtWf!lwSma`{i&tH|=3G1>-gWVwi?uG^ckzLX4_$oZVx5bRU3}tVy^9SlK6UY# zi_cwr;bNnUFI{});%gV*xcJt^CKuni_};}2E`D_JlZ&5S{NmzQ7r(jq-Nhd+{&ew| zi@#lLcCp39Ru|h`{NrM~i=sxL5!8rOBhro7sS!IjVwXnj+KAm6(WDVg8?k#Mnl)mN zM(o*$=8b64h`k!IcOzOhqE#bWH)5Yg?AwU_8nJ&P4roN1MjY6PwvA}li1v->(1?zW zIH(bw8gXzV4r#=pjX10khd1JgMjY9QqZ-k<5l1)Tm_~GIMAt@iYee@(^k_uSM)Yb# z??&`##IcRYG{R_v+4%o3_8#C>70>^0<`M(}K|vI-q1Z*GgCH#pA_;^fBmqvj0d5qf z1VXa`c2rap>;=1shy^=E^eZZgV#D6W-W3I`|Ih56GiNr)?|pfEeCA~C?$qtGv((q4 z0*?lHG}xm;k52Gth(|>p6?-()qhTJEcr@IjQjf|!D)(rFM-?7bdQ|1nNRLK&G}

    • ~d&CoBq|4gm=xVWZP zy;=9>J1)}i#%c|n^xbUqd(&b4A-3GTJ>2t*Y|kO()|~B!en#(dwodpQt^I5*hL4L0 zi6O49tqarczDI3V(nqrG=F9lfoGjTubYq-mShZMyN9&(W-G_J-D$HS^QKO!(Z%@}&RaEORMXe3MdMTGm!zv^yrk_-DPP)B z9M$9it89n} zr?EA?erv9SNd63iaOk+wd085x8m^kYs4r-|5+{w(mUO7k5?84%XFkt1e+ZwC7RId18oa)<@PJrCi$G|Oa?07Uy(VNYAH^aw7qI# zOZ%2SAIedUn0su>iTBLT)#vIm^uOM`f0}tTJbzDUD$$#o4EK+g(%HPxcwRo;=NKAa zDz#^7+^usvze(s@`g`cr+P5`o=fLFNJY%xozq0k)+OnxR>x+4B{gl2dHodgl9N4+C z^0b;0v-WNMnK^Dv+5N7n88=t(#pFJzHamZ^cH>7&_)^YhrERU5muhOT z()h~to1S9N6!soBAJyti{z7|34s}U#?meOz$JjReEAKz%*lGYr&*xT0ANDbTr`-R})+^fuR1i#{$!>wmab+8Q6{r`5Y_v>IJC^_cdp z?%LBD`9o_1^(AS0=(tmgYwPi%{-K=BbGScFZF+Zqw7#dh(tTj2%5(Fyl2deDq@2k> z(|hr$Q8%sB?v#qd%(>Z1?dK6wS~kAedwBbv{;vN{jpmsaSFK;SZK=)pXRoz3pBfqd zcLjuhlc3tMljx7uu)PnpIjTl>a~9e`{XsdqKiWAZ*?V@{+IrOQmf&oxWV`r107+-( z#N{Mi+PAcKG?%Nklt0OrROer#GIU*#)}Y-_+qS7E<8t$s&Ufiqpu4Yxd3W2=e8%U@hm^(QW_IKBB?M9ODD-^BmIzjxXs-h#df-yz0+ zLEnULL;je&*t3#(@A`_!=KOE-WcDc2r!{ps8qfGoetTob=?&Xjeunog)+aN5*yiRi zY%ABVTw7{WKJS&wS-G}pE}!)4X)>AFiuds*J{zN1PdTC8<|nQ_?O)oDn#*5?@@@VL z^PZGmvya$$llCS%=i0W^X1f2BtwCXbu{9I7zt~!gYft;Po&Cq`W3*@R{^rhGl6td$ z+Iur&x15~oG}>J7_0feoPKrT`tgt?dB_UuFkx-J{RxbjSOw^ zmDHV^Cohhef2TZKh}W`aj!~U=?P)=gn;KJQ`b`y>e|adDA}c z%oXA_`L%srAFNK|B%Rb3)k*eHois)@eIA3MKZA)W_&NF5|nbzmQtR=g~%~{dDH-ASg zlZp8^)Z0*-@juc1VV+E_`KZd+HS54zcP-Fn$0_d9!THtdXCYtg+?e;)FLNCZWp_@^ zd$SK%-qdtk)7km6K9cO+|5mHF@uPOMe4PJD*-6TNQvOt9Cs(LrnhUQE&D?}-ZrtVC z%(`f*>7pR)_*M@=YLXmlCqzaKh@X?*MMs)Y;)r-*XGu$+sDGHRs*bUQ*W_cW-Y?HtqVNS8tCs`l-E5s=cXRyoCCe=C%7y=%49tb5`{R`0X^!~0zukkH z%bS+B>oc^Ul%1sPC*@Byc5LlZuDEtxTVb0UceysC=G}2xf_Hs&?Q6%4voodiTK~0t zTwF=nNy>gw{#0WpTm!DHu+5FTT$@{~ZXZ|gj^pZ+;#=BIoPDicn}^o4AI`DsYuM)c zRjy5%Ys-_3RyljPaY+7z*IYL?gs;ZF%|%OJ%j`Hwi+ zt+Iy>jCPU?$tQeR1j+Cw>M3`vLDLpf;-Nr&1?Ig`Dn&j+TryqLY* z{Mdbna^kJwP_N}}K0`Y;_o2S6*>7w9v~)fzjo0)ud%LY4>*w^Yw{>pwYH~#Hy)`y9 zx25wO&1IU0G!N^_H%ibls%&Fzua9 zD!q=D>zD2o>0S}HS0L9|Q(NX<*3^+b-y!`>pRg{`ewy*(Vw+m@NKVo@h-%Q*1?7yN zwM;E@Jhl6Y)To&oJ3sU~RXq!v+UF|xW=`f&H(G_Gl5AFcE{TCQJO8`DN@r1O~0V_Vzv(=%FnMoZ6VrGKNt zKJQDVW+OnTh(W~lv>0wo(c_ zyVC1uxqj&!B|AscQa+LEnyD@OoB?_M^_H%ibls%&FzuajD!q=D>zD2o>0S}HS0L9|Q(KkZkA`)LjAzEuj29Q%)S^dn zlFmU?6SgiWXNf-VvU6beN~#<0SxsBf*|pT1e<YLkVtc|w9H@63)ex`Ps?s=xZnyZJnd(F6fYWbG7la&25 zuJZMhRDR;-tEKf?|FwLa|4G?N%6?M*BxPrMiz_bPIDK2ob8Go&&!se8le0W>U5oQG zPM_wvvOJr)=os@1z-^1md#bN2@7la+>s!mm`ID5Lr0gf zXHs^OvY(VcN!gj+;);tmPT$t@+**F7=REm2c+&MyZJyn;oP8$eKC3kCR(4riM@C06 zd1v{S)Y<2pNsS@dlXOzNb}p0hMY1R9Bwr+*6o;gf`c^Y8YOk6xq&OrU>WjpoIw=lG zhuTBqXiN4`pR37>6t84Y(n)6o;gf>{T-^YOk6x&^RPtBwcIRL&vBlFH&rh zJxM3^m2^@Zl1}Pd&A6z&YQ~V_kaVao5{K%fI3yivPl`j*N%pE47qwT-7*ZUP4)sOi zP@NQqq(kjVaY#DJUNz&Q_No~}ibK+&zDOLZlj4wcs68nTNhjH>W?a->HDgF|NIKLP zi9>Z#9Fh*TC&eM@Bzx72i`uJZ3@Hvthx#IMs7{JQ(xLXGI3%59ubOdDd)17A#v%D4 z>5{f*$1rxyvkQ{F&n!ZHx$&!E+nOKla~$hiTh&Q(lIr}=8EFl3T}ye9=66bQk}uWh zq&Os9xiJin>69tWI2*O|Eks7dPMDL`8fZRvXhkk zr2MJIPFU}*t+36FyIh;8#pY_p9j7ID*H_oRcHB5SQ%bM(U(3hEm6V;N>?h?f?B=z8d>B7j&-RT)4KvHrKCmZBmSuCmU7e+}I``JsXwiOrN;3pBtwX3wj2d z(snAzi}g9}8{K;(QESs$PN$aoPyO^i@1ix)A{2=pdpI=bzdCwk9Ew)4(a-P=4ujS+Nl9ZjK>?h?AbXs{U@!%v<|1|I!x+18)pYuU-sHhHkv#$jhmaaPwC8*=B-_qGzV!8%wCb! zL7IcK4x-OP(zTGTg>)^XYau-=r)Ool78IYcrq_k^x{zKM((6KcU6^uvqS=qlk6DNG zT}yuMg?{HU?c1&f%~ksR(PSX1HCt~aH+jyQ?gh#21@5}G`FC|_{i0koV@Q1^9qJ3p zRWpX|Yihb&?Y2alnMWGG$r`FgZ*vx|(NynW8`JzWzn42}La5TT)!jQP&4%4q!hIl4 zAJ(nwgS2nN*@@Gq_T}%9HJ9hOyv5}?P9J9{P9J9{DSh0yQ%avyTyb{LxYFxsdOdab z+e+)f*r2}N8PL^PyROdeMXoO8Ojas?7Ls)S%syg%;`W(P-`04W%g|4&kJ~5Rnrx1p zmTX9Iw(R4-RtSScOID*+M3IA(${}` z?Q_RP$B_C;I@BJ@RWpX|Yih;(n7E}nO54)BWT-x-WWAW$r16{Vacx;|*OgsA&H3Nf zcz3?5$+O+d&^*MAo7yQ~|4HR1F8?j9*ZQyJhtPOtS-%O^E%oSitm)=w>;)VOhWwEDK@f9g;9>$rA)wS1cY^7(IT`O(gAQoJ?~ zT0YLtr0gVRKPi8bvNOHK6&G)uUYlnvpVYWP=U2<8`7fXUww535{3gX~^PuJ9{7lMDQudSbCn-DATU>GR#_6?r*78Y> z8)qj@uk};QCpB)IojASLPc5I+xN&y0`nKkO>QDLefOdYhe479A`EP6a(avvDyfzP7 zKF-gi>?CDBDSwi(Grh$X7jK+in`bSb)VOhW;`CZSwR}?J#@UI}YyH&nNsSw4N2_mZ z{-^$wKM%ysul+uo`R*9ykiWYp>1=Lh!T z4z(w7l08W$^+k1(JxPb!lQ_wqq?7uhI?0}-L+weNWKYsbeNmlcPtu|GQqE)m+c#1! z&6WH22`ahnPs=qV?L(5TnjA>>Bwad2w5OTexOJLzuByp%+SgGR#_6?r*78Y>8)qj@uk};Q zCpB)IojASLPc5I+xN&y0`nKkO>Q8zeGxyC@$8GXls;y5gAGdy!vXhkkr2I+BP8wJF z^^#Pcld_Y}*R(NTar21i?L9obHreYdX|uoEjK*$aPr9aPdFxYXUu#Fpr{lKlvksGA zn`7GFxOS@1A+;~nqxB)IuTZ5wo<{@3D<=3e;pK-i4&!HWAh7I+0 zA3*h$+6n!)c0#@N2h~?akYNN z@s;`?`k9oSI6srpC*@~ScAASTsXA%vc5FW5{6zJY+G(kJw*G|nr_{V#f6#ndKSRD! zJ7FHIoltMbMfFM9nNs6Uul|R1rOm(PTiQ;X{Wv{Zw{ia4dWf@+>MOMq`fu%odh0)` zuhdRlyy&>r&z7=dMOMq=E2$t^)?TvzEV4J@uK5u{fy%)^*{78DLZj~CZ$ix z&!p@$7gthsl9Zir-kbA3gw{v>5*dW$PA z-lX)}dC~H5ekNrnDf>zJla!t5Ev~qDQ+@gCY+K7uQuUwODL?N?<)^LHPg4GvbH6?N zQ?AnQn-ub4b3%EBzQ2|7b5eHF z`IQP_CLWq`s04^#$ds8AIwT z=}=!#u9`8VzLF001?8$4!}e|Ib9GYtO*J{OvAVvX_E1h5L(-x4P)-^{(xLWH&W;h* zkL@4o<9MxJYhTO9`ID5Lr0iGfkGlq}FKtN|S2xC&(xLWHu9`8VzLF001?8$4L+UH(P+w54nlYrlk`DC+<*FG&>MQ9`Ur?@^ zF>GIReUzpXU7QZ#P$#MalBTq zwXfyl{7K4AQuZtL$6b5Ym$syfs~dYBBcHuL^Fd#_3Gl9UP{$WyDWAM~1aI zp!ZF3khZn!qRC5AHE-8pbM{cq&bMo?n!eT8t7hD4`c5l8OL0`ALvxC9k}uWtt;Sw8 z<5tsmTJhP&VXrA9d)EkieF*h&yjGu-{iN)~`H$MS{q6anx%^tb()`*QM(t?%IRBHf zla&3W{Hex{tr40FUPG>}u+5FTT${O`H&+|(I4!}uzPk3ctyQ;=t9Qq7^-1w9Z70sYRNh#d2Yr`rZJPrgn6O7c9|C1GKFVSwr)&Z zZA};EzLI$~F{O4|XU|FVoNS)WzTL5~F75kV=6l+e=zmnzRu{gvYuer?YGv1Mt}u?Z zW!qLEy}8DiAEPt-M_baFoP@rIa_GP5Gp*`!wa*vpCaecLrzZZS-{!Bs;tej1>&F-NtU#-sFldN5PJ<`hNjAHEB z{;e&$u{8HS*Cn%)xd$=%E6aAybU(F*F_RAZX*YND%I|y7`@(g+pW>I)3DwQF$n zjgEePdQYh`KkXKB-Y;BWj6Un=7j^WD74%(*S<-pGRDm)2r5*jUj()kqdlSn_&ij>} z_vW}^<6X^pzdF4y{MT-M`;P2vP+&~F10DTFj(!lmxAAV_yx+3Gn0U8x^xHW4Z3}u6 z*DlWcT?>rS@8;-kW&$citc1yg$%+f3WlZ5PDzuuU+m&Q!GX4CL@^~(SPl7 zH+yZjdTqBE$wr>bd(vH&G|}ho_Sz%>^Q09#X(dlu#gkU^q%}NgEl*m< zlh*U34LoT>Pa5P&n|RV@p0v3qZRtr{d(yT>DpuBBp46?_VrFb6BNf`)P&TFf;5_#S(H@_z>;7R>GX(3Nq z*h=);E_XB?NlTeH)=C`FP)|D1NG22P=SbVe(kWisX8&3d(vv2 zw5BJm<4Nm#(uPJVM!TJrI4|3KMk|$l|N!NPP4W4wf zC*9^rcY4y@o^-E~C=2GNUG6?ly5C5Ylc>rc@T3QgRIKYaJn3yude4(S^rTNb>2pu| z%9FnJq#r%$7f<@#lm7Cge?6&YMmL5Ip48b$#TxA9Ni$iJ+UYv&wax0a&1R%xcIWh@ zxh%<9x&c+qgb^dr}`ua$Bv}R_C?VTZwm~`8{a?PwMYU3whGQo^-e;9py>K zc+&BnG}Mz$^rR7TUYzuRAhG}nYGFFIlI?3r`I-@k&5*>k0 zUR!Ukt&eTv8m#xE21{~VKd)_muWbPrrj>Xe&ax7dW30q&V~teY zlgD||xt?^MC!Oy}<2~sDBNel>b)9{0>TDY$73*wUuWfs;Z3iP2v$TsR?P^JmVK=XB z53g-c+s3i)<4OBklH2z4+79sA4zv>2*`c0vm?s_XNk@9pQFWbX**2FmPno9J{|5ER zb?7l6H>fuEZ)VVdnfB;DZ_x4+K%gi#U-RK^JYO;fB=HDzsubX8W zKkKn}_LCmjk9uT3=#hP|$G}0enU+QJpY*tL=q0rS%paLP%YN5`l#7~{#Riqh#Avk z@`zzScgy5Xr02H-jk&oPYTT>G1&SZrz&FV*q?e2?l7okIU45M9)1}0Hh16hI6udXQx})J zx>D{s_NU%voE80~4ysv+CXcc;sAgqO(zQ*JRLWLV5GGrNbWoB`>06lYV!~G8R2GLG zRI}>fc7tpBn@Z`v&fv`8+<){xyi(U2RI`Se!}TaZ|4^m=)g${ykL+(fvcK3$T|fVq zSE(I(625`y!=+WI)PGHk8&a^`Jcz9Q*CYRnRH^@QwmbH$tWs$ls#NN2Ds^KTrlx29 z52sv<#Z%LhN^ZGMRSiSE%`ltLFztKhe~Z>Yl#OEXwC8a;$Bffl@kHTJZ!^wjTq1qw z3Aw+HN+lAF%_R~A9hFFw=VFNrc1ncjWpgeO^Hy6T3-laRle?UXmR>HQ7c=cFQ%Vl# zxpsEHp4okR7Phq9Bm(mL^rWR-%O3O@K((A{9MW^LdCiTYT_?X^PkPS*M4)lHcHkPT zXELi9X!!$8b>*%gOYE}|EAsiL$mj2@&qgMn$CJQh4?hu-BdO3hz zIKM_FU-$2|c6Q%h*&)4beh(#men_to!zO$A-Md$m-?1jY`}VT=jX-jEvYX!ndYPdP zBTMYF5w$))+ILXRHiK%mHok5{em>rJ?ShBf4yxI%@u|L)p3AyrmVcrz0o(I1=4~az z>^7)oS2N6RG|V%_VRj!>vq$6ec9>_)FnjVa=B;*^M<|-yl9Ug6S%?!~kZH)1>(+^cS~xu)g1n5>^zH)7cL-6+@Jcgqi}ql>30loM<7C(wIa zK*!VjGmZX)T1pue9OWoC7xf;vSYgTrM!WimI^)aIc8ZKxQBbQ#K`n2CGBO2q1_d>$ zE_-TSc4RT4HK>WAjUwu4A{teSC^~6uZlcPc8U{&(UH>K9bL)_^&x8!{O9P-jm$Joewv*qN^ zio9=rI>vKQo6#T~lo2ZmYG<-Qv24w;&>JIDP?u6r6Y8=T)nzXzMzjkxQMAr`isq8;TK~Kur{_Gaa{-B66qWrYInujvJzYoawloJs(QO*mEORoGy-+ zIgY!?I>%weisE>jERg&6v-|YM$P~xh6vvx&+1Kl`uNFgjf|~pl{$?qZ{Oit~ysC@k z9ggKmGS9IXv7%UBAqy13vm64wF*3#SA;t23UH08#Ag_|%59Iw)Anu&JtBd0!j^j15 z&T$yAqBuSx3*`P=>^{9QGR5%~#qmX5_OrU|C&f@cj?hn{mrv=%Y(=?u=(xQqJ;lg> z5zWeo%*fitZ|mq>bz!Y}ppg5F$i{E#{N3W)QWk7S-u6B#r6Ka&^p?7zhn z%@Cn8MlW6I#ZOVY`sg%bYN#{amf9NXMr32BdVhE8Twglm7dmncWylB}@;OKU3OSm| z80%aw*3ityD*&vvc1w=(lZ zT<_?m554#ankkBnYpA=EpjsjuXA2V4y_6ugh6*+~KV8XQxW@V#TixaS)KOc0wo-m( z<^0r>mh)r8it@8KS)ly%rx(tTktsj(QGR;WXM5IX=Pssbi3lAKy(~#Deu{cIHB{@Q zXelBa`_%ipacwC@`9epop`K0+%`N0;X=AKb&e1Z|mhV%_QE$%CvZUo48L^@qtw9zj zM=R0`=g7#EqXj5OjrG}vVuIF;xV55}wduuAP-7Gu*U&;vg4Q9jals%#3zZV&)=|(|I zY!Pu=MlV~@i=Uq*C?0c5WHzB?ocwG}WaHBH{)KFrQhxG3nd((@b zt`(eeTGdI{5F#5_3DUJ{DP3+k6>Q+y+Q%4QRnFGF)RteRl&zIHTljBQ*@*J%+n zDtbAcUi@@z?9|uhPP)z@vT<;buFXs7a_g&L1Fx^q#`xxPw$7xs{NPfyHsfraMOx05 z5i82p#bkl9buPVdwv0^K+JUmQU43?&V!|dw+$GV=rS#$_Y&)mEc6JhW8Ig@U1^fHX zrG(`R9l5@?(bm^QV|`~iW0zA~ey38#cI1prA}wdkh!th*MzTN|yP94&V@9To?MWHi zy_l|>BIxGmaPsvlEGpm~aWG`+VE)t@Q%P<6qIs64X zOmB=#o}W#gkEzd|S)VgTA!Uz^n4C# z^2=#r$@BcB>b5G zRwlh4NWK(^J12MO;<$(7ScR-}97e1tjt$8IxxW^>Pj8G&aXd_MJXoK-zdn0!F_euW zbWrrNF}?WL-v^^v;oGgpoa^r@oRz zyBW3RA1z&PAK@GgCN1a4h!y2%N3uYv*@|BHdTV6L(Q}leXX>+06%({m#O)lt>_RVo zf}V+D^x~)JEegrrvcK=7=x`z% z->dgm()*emqCKQDkaFRp@I$0 z&&NW3PBpf^lJj#KwdKDo<>w2|&nVJzevDXAe$FQgl%Fy5!uc^W<>zP0&yV%l?~C~v zA8{8%FBj5_pPwHo9$P@aIr+JW$i`oTHTGL6KlwsOE}-wDB%1`4zs}odJ{KG7zsVV! zKyCS7OBwrxGj<7SIb%kwC}Y=<1~? zB`ja)$o18cj1)fD!0PKkW4)W4v4^NF-?gFmNym&0CeVjT%Na9bMHzdZERdlm>4h_9 zWXf1~%Gj*MbiEKkFGepf(Tkt1S))jKyPDHU*ULmU&Jm<*&QiME`YPDK>+2O`d`>xA zuToonj#9Q}=WM-3TF#acE6P^C4xFuC^upOPGG%KU%GOp5*)1BfgB!A&He@$0X0DNd z#_bv!8yliqrdspmu&qiN$Zt`oG;?P@xR6G3XTE8}mGsSa{-)=~q%M4QQuyYZb62>; zq}48~H6N`mNTcSrYcQgjs7#&t^S^?IzbtCB%WunBS%_fHiV-Wy$_iwGMqP|vI4ee` ztn5u$*|Q4)$5pOT1-sBn)d5; z1dW%!xJkW6no_-9#Q7LWFz3UF73E_bS)eqWPA^=qMy7mRN%@%6ke%3&y|f`ap_q(w zsg-i&%^-`xmCq$WWCiW^09sSCeH9#)uUK zb0=A#7;fMg=#7ynnENQ0$qm`N8?yO^>>b5O^3+O!I0%hKQ>$N9FUny& zUkW4ttW#7^Hwokw4&)6o%z+rOqCh?;3*`U1>_5FRG6nJh1@c})_ML|8TMgMa8nUky zWBG!B#*Z2r2NX(+k2CL;!pXlwzS^ztttcMe`rasQeXm8~KwIB8G+zFrCR<;mDQ$fp zaz4H#nDb%8it_OfS)erhOfS6k8JY6&HRa>WhV17J*-sm?9~YDHFSSyxoJIC!DHCpe zejX))x4uuEiTyargtPU1!-4!qhB*);Ruo8&jvUC$^umD{nF9HP0{N{W`%6Rir-tkg z4cYICvGgRM@vnx)LGHx5h4m7dz(Rlg4noMk@DNXF3 zoR8iFb3Tk%Q9c$X3pBCy^uqZtGUcN~Kl;vFzig&o_TPr=-^FBPsg-i&Ol-S;;yrPu zpPAFbSJ#}0{X5EpGqD}}nei7P!yJeaD+*)bVN$P~y-6iC;8*%|s}JNL8q zxGPdq<1GFBTaT`#K=Lz?_jXDFTC%F zG^JUcnUk>^!JG^uR+Nkl$pYnIZF=EZH8Le*PD;k?{j#$aGqDlrDMitIE^5x6vzOA~ zF4Wmd^I147&&93|A_MHI5i4?aJF-Bo4rUMOjgiUK-sI}M{j&4)%l0UGyFE2E*7oz4 z;=Cn?^Yb|K)+3R5+nI*U*EX5ANK=}(KAenQ25Y-e)kVqGY`^S6 z{j&Xw-X0gB$44(YdNC`h^o8qeVcN|1)RyR1dI)y{k&TP@qoZ6D=n|$tmna3AFLX4E zHNQ|P(tLk8Oaj-*fKFotfR4AzA(Ze((Fok9+UA=iF1i=ggh5le<+Iqrn(ujEGDKqnDup z&@OkmBmjkWBzjt7bxW7eh7?qYN352|+dk8UWc8Gz=Nhfb2d% zRx7ODE5Uk8$jubZEHrkoYKb`c!CO5GShFFi)QzdBdL~%bgGblFS10#6;PW==s^^T) z9PqTdCO&l-pSc)ie27d49}OCS&pb4Y57EHqA>i|1SZy3u8%l_l2+@y3vlNXTq6aMy zHMc;t43f&jG4<5k86sT=L)6$(P7NL4T26YKJHxdCJndlKB z0mz1j)uOOERN{49h@KG5Ni=r6hKo@7ARJ}E>l7rFkui9UGV!t=gt`uftH=V^PzShv zC%vPb;ratSZKMg;iwxJF7-hJKObD)vOEFxf(J)*@1FlJc>(#J2A*_xMt79c%<%RSm zqPY}}9kEvtl~G|+Er?wPNo7jde(gQgL`>5sa)nJ0urp-iEs%|MfUE*3p6U$Q<=|;k zOvolPWLIF6AtN#&$imQo3cD5!Lq;?pn+?cjhSeEib-Kh$5u%kulZnQT*Gv&ASJ+$& zUJ*ztb7JtCYvN_CFkJ`3HNyhebO*Siq<5|}Tv_00b4_bFlRM=7rVs}DP`6y=9Uuq(z=@Yra zJ`k`oWD6{i&2xb4E>gVI8M12NX&;%8EnW0WByG9k$BhXz1a6AeQ~G$8vNkbM?b zKMAWJOS~Eg(Fa7+5RDzL&qSzPVQVaSHG-t_MGRhROuVcWrt4t1KC!^{u>)LtMKcgynZbKS0{}ZpgS1Dj>B#IiocYJZ+DO)^0{?5Jnj- zA`?PuG&BIM=g}})L<6nkD6pep^>A1{6jl$0)%_B)m&JrJq8W?Ej@eO5jh(V!HV%@? z$*}!P!c!(@nm&<6wRB!x^_+0R`R7Kv1rzjNkI~Zm3h)f8*kD&pI zG&GDJ(LnDapjTE=%P7W^!IeVp6VZH%#*SNA;ASjsKO;+DpFA18I;e#(=IkaDaW9!#wdeAWI~{9fChlF77c?!G(fompj42Ed?SQ5 zie?iUJ0cY49WrUG{poZ%%B{^D1$;|LZF<227qz|4TC~7Kv4lomPF)tA@ql6{zPL( zB+F7IRV;{{hNMzC29YWzBGxL=b=a!pFPdM)8IUvJX_ZYtu4h30#wY_qWI}+nIgbHp zj)nmt8i3RRAhi{>rlQ`Xs5K-qZNXKlE8+p>E%X4hwi%vQQ?C?y$LSs&Bl@C&zi-Be zR>K^`K4l(zd)4LWo`5xuj>v?f>j@1=cP9=C9ikCkV?@_bQ5z^~eHmIWun@KgEr&vD zXohCZTmuXnFRs)#`}!9NP1y6Np^QBzG9k|gLjxS{#}1=IG(3L{p0`lc=8D=(QJYHV zhk$F(OAFI^t+^#H&CC>-d1-16I^>1qY=4i`l4C4_O^%VsgkpRJ8W7qj4h^YGMc|IQ+;P5PV7#*VF zc~5xWT~WI!Y8OTAq^M6y{}({Oo}lig|5`UVN+)7EaJrbe&^jsnNSh9wC(U7p6!D8h z;%R>`4sj9eafn1F6yhpqKx7|rWato$5DO6EbBg+`qCTUjeH8U+8RF*Lj&Sl$MK;1{8vBW1C;}cr7otM~$_thg!*`HWhAZ~vL>}&ej#^2GzZbx0UE8R zn6A{vTLAhMlFGOkfX15uS&wjC2jer!0iQ#pYrHc)zk#QXGw~VA_#DP4<3nUZ_?&?T z;Bx{E<3lv?c^&vnRn*Cf`kI93Zy|bCG``ZY5KTo$#zpy?7Kr?iRHiHTMet1%B2Ayj zH8k18MSIQc%NoKD+xnC@oiR!VPn&LH^af*;f>FkZ$b>K|4-LSm3>wCWXkauK7`?5i zvm`*52)Ro|a~T?Y4ZSVm;k&)}EC5x2r1EYIK<}9VS!+nw!8J6?0iVlB*L%+RTmhc; zu8Ge(jL(%AWqgQC2%iWv0G|LF#)oL&vlRF&QPjnXx=2wMN|d5PI!iR!XzVC0K~zQ= zt+1eUJtURo3QkqxTzUsx>8vnO()5X3MvF~ov_)c}=C4;5n&Yyhs*vIp&XC;zp0?bC zY#Bp#BSslAA`^n_E@%K`x1nLkhz4Y90NH9qU8Sg>O1!EG(dwe9fyR#4Y7r7w)mjT) z_drtlDh98$CSKO6(sgiEt+K%NsRLX!N$*-`xN3o?ePzP+CBs!4qYM|33BlDA8UR;) zGz=HffNLw@+M=kN6!jZL{aPaSkdSUBnupQY5!-^Oj0)RkL996>mG2c?DOf6On~9jF zPvi>QWJ05TV}a~zb6i%~BcynnGh{8m)4n$$`;H-d6r&6okqJTeBs2iB$I&okL<6#) z0ofi!{ZUbOO1wG>(N3c2jK+@F9uX2(*ggwhT_CCKjlpZ5iI=s)bRAq_KU(10=>S(( z(!0+Yu5RFIdri20VYr^cD8of$N#Xj8Hi#aKtp(7~<~j@)(SWNED5z##qQBN}>Ya+XgfG8@hn+V9V zZ9;GMd@Pi)=R_vt`RmXChvn8aM8ore@O(g~+CNk6m#OxZ&eN7PN^@&E2AIxk{o$o? zkJ3+g&*|tZye}#o7;yUw2XSLEh=ZctZa63+6ADV-IA%7-g6N1wP{R<^^O@?9Otnx( zG@l|GXidlSW<=I>3=siwItoQVmUIkf&leb;6Pb|bpFjf~*4SZmh=%85;rYv%>PwmG z$V_#FbpBItm3(VDUN)WAUV@iKIz|fbIUOT}_vcQ>I1cJF7~ymfnNU#cp#iac!Lgu2 zG=iFhpkB>XCuFMQWkg?tg=j5D$E#*U)^tn|0dYFUi-0WYn9QDUfHL-+$b>xK4h?X4 zGdqk9(eQi*JfEJazMiR0m7eba%YIx>H$B&0hl|JseP~ln*W>>f6hHS8v#H2i9Lr9q z=U9kLD3$}zfDra@2*_rB08OTA5+XI>;8Oonv*$?jdW+>YGmYlp>vRFRgSWZJd$3kR6v6RN2 zp&|r78a^2kjaZf-mc^OsA{of}7`F$q*bKy)lSL(q<0Fpa0%+$rh)gJsE1&^!lwz zh-D38S)Hk_l7T1~w+FJ?48)p~RV9n#OOB%wv~wIpCKSg_&;a+d*nM<}MjRUu$NEfl zU8cHLhH|qIy+t&%#f|;CbiK$5zXrG|)BN`IHb^QPGwrLzCKClspUBJJIuizME&8z= zz2uOxO_@M0{%g|P!P7Qo%CAYkVT^Jy$`}!u5JvYx1E8Tjd-(Vx8W{ZmjK0rQw@QF& z3b|UMsg1@C(Dx#?BHzk@veN?4eUMak!~nF@1jt$@x(+_0ZFRt>4(ZzIj89$gv>hfs z+ZmsF7-f8jObDOHpaJ+aMZ@?I4SWs*pF^4I!Ay0(gs7zuwQPxFhv*POGVTSBSsl|~&h&Ia6j+z)9VT|%I$`}!u5JviDI31yg zG151~ISq{d$W%{BfO{$YlmkAz z5zgPv`0z$JXH0zlVtnLAI7B9dkG{dp00SSQQA6iPun|W@O^v9@5#w&JNMJ*o-~cJw z;l^G==S9pKN{g85&apNsBnHL$vLU zRwg3Xp$j79=tzum4H20TMiZd{ie5&;HAFNpx)d0dkErD&K>DURmOXLo0F@W9aSdH= z0f@HEQ7Xg$bh!zTwT5&Zj88cSe5R1D%boF=3Z7QM#OE@`hc?7ve27d4pE=L~eBMOE z_z(?z0>J0Ghlx=~F zcF9q)V&KX);j)&KuA}&9@y0sY&S=rLI9is8R+Q1A4RN@>h)f8rb&AGcgmr?aO{BHWT~$l3t$@{soWN^pX72(z%+d#*VhdttuNYzN6B$U zjP~8pZZi?Pl@X&2a~Lrq6GChkGyt*h(J*2}1F<`SSXBwvk3wj-X!fA7!&TK%U)3#e z{RBy+S`1v(O}MP}rRykuef>u?10s_)K`5AV1GbTsTZ@p*Ea#v^od+wHA`Awf0Fk4&WN1` zPpfAlR+ka`3!{t}kqIGI3V-+x#C-f`_vjD}#2N#!h7zvxgivYGoR7v1S3^sEHMPKX z0VI_NW8i9P!ey;5T}Scjs|+b`>Wo$zc-n&|T1^Au z0Ig0D^~s3ZKBBghutmUC@*~!V>SpZPlX{KuLv=bA)N?FECKO9=Xg~oRtC}s ze7Q2$gh6{7{n-2U*`#cN^ZAxG+tTKn=i7OV(Hx92 zMnoor(IRL7G;#|rqJhyzz(|XzA4-5e6mpA2LtAm#0n$Wle80Zj0uXJkr7Vj9Xt@cH zwM=v!yn24K%OTp8YnfNSae3oI9@gXuHeAYk%@L7q5&k{rfpEbZ|bwphi zQ9qRseJMo063tpPc8FFZB;%HStp%e0KvMY%_XyS+T5Ce2=@YqzRtcOLqfZ?$qW!y+ zways*7d-7N6QeH~qxBeNjEGDKqaUCF7;Q$w7!eJOHUgs!5p}%;h_>W{+z!#~L}LeN zgNTi5Xp04)U652Z#{jg&1jt%Lx(>!?y#qc!lCCYz`0NHx+ic>qiSgNkQO1YJgzz~6 z4TyU`8pelc;Ik9>Y>%khBtA!l+%eJ6hFx}iwj&;+fOcE(IRQ!K$CzVmw~3FYPvipH zCO{^DywCH-GoO>BeYZ1Wr@+&GG!fgyi2aUHMvTaW5KBsB#QuUJMvQ16whxH?BH>CF zLMft2MPrBS7fU%Ew7^vglFES?xDJ|dS<6Y+QGB${BjpF3(JBp|cEChyKcjU%Mj0(4 z6GH1!Xh40HMZ;(j4YW=Gtz!}Ohy?61Ay+{(m!q)*cFa;=zgqyKjnQ9_sx_i&wWxY$RIM5{zWtyrs+8JMrF>M}GS#A& z!|pK=&}u}*N>+&1-KwE)yzX{qlwP@|Kk(41V)zSs3+}MfX0n#M!W)eZqI<%sRy!KI zQJWYsH~gvi(-K&2s2X%JQGN7cGf^*#v+?MMa01Riw> zj|L_l){3Yv;2=!2x&jWuM7vMmL7?b=-_wW#83M%|2$2Z|LK`+Aka1`@5TX%C3k1?U zsy2(NO`~cP8OT&{mB(Uo+dM87{_~z@mee*iQ`_X6sg2!(Z#s->kHw`{jF_o?lo5Fo z!i)%!2_Z5c8h{9GIK_w%4Mf@lk#yD&on!bEYB>fX6N+I2G$4jA*mZP>MhpWGL;tASFRJ#9s=cFXFB!=<5Ksn2 zm5SEIr@tAD)(^hYWfUzweML0<9ICfjp}j;nE{l(SC+jV+rwxp&O)+BDW&z{zErb~l zA``-6FEjuK+V6^UN;L2o4m^sY>d>e6AC05f6j|QXmckHglGiv3IZ7yRmVit(NT3&RDDs#k^%u`VpO@q zn%Hq>INBKaY9w~Fh=&t9%1rEwBAj9+wlwT%6XOyqM$E)cU_8!;FyldFLU>#b4Z!0< zG>iw)z~c?zF)gZ2iK>&L>Z=lrE5HR-mc&jok+3FqiU5KWJIRvRR|OK5#7^fxu7qL^ zgvf*fi9iDaxsLruhiC*c4}rWFRo{uKbE4|(s5&#M&XD0mA)_paD%a}~-A`x8_sod2 zci^s(+c_d6&h2b7w=>P|3=v$h(tJHkYYXDiEJn;U&u4ThLzvMaG9h&Cga&|eGa61a z(LiT8&{-N)mqgXYQFT#NT_~a9O_=8CxHKeOmYTR&GrdH>!kJ!d$@C&if1v=zlJylF zS2ZIpA`^;>b|6Arv>6k}C3YlIzCv7UqU!3Xx+K|CYa`;?5LMSl)patWo?t1PV=j$0m_cdl z;iXZ;>qJyk#B^KXvu#f7dd(YqVbljEwaszGD@M%X-Naz@g)kQ{kqLn@7#fh|{%APK zL<5X%0OPx;`mID_2*v@C$ZZp<+3!pktTp?snOps;_6K%#C={@(L?+~_z75fE!&Rc; z>Q8WWcU0XKRd+~lX{#dTmzWdFZqs3HmnCmI{*}DF0+ZS=ad{IXX5M~gFeX5l!5}gr zFs4HT@-_(#=Z$E9@hiYM5LNd{B;Le0AhP7`fC+;&Z~Nl%c8Fb_0R`+TkqNoF02<)x zZ1xZxqT%YFaP{}7dNQgWkE%zb>S5{gLI@~-#T<3Nn{I0-E!jJ6W=}gR)(^VbJd9!Y zn@#)m-eTC({)$VT7%@|Kn(@#e%y$=+C0_gm`!GtYslRBapD1AWCJC{WVa`fe@KcAhfLz6s=?b z(IFavT!=u@veXN*)Y4hT^Mfry^jpzvMPq;Rk_P8#9i`1&FU~TbynGKyrCb(n)C2$z z(aLkN34o?gq}kd976eM8kNk7g#&gdfNZG|%04@GW%XaXza#`|8%SDXQ4vaEJL?(n0 z?F0m9_MqWp6Ag^61V)!DO2QIt)qW>KK5oF#)nx zh^~V#CoXfq=P2pA#u=Yu;AvNz_*}*K9LFf*Lu5kuoUd;rfQIoQ8u;7uwV-YgOqw7_O=oxN;rf3X$Hso#6_Dr`0gws?KmJ z7-hJKObD(#XaHO{qhYv+23!vSuKTmpdRc0nEVZ^o>`ozlmuRY?u_JarqB1J1u?4Z} zkW?CF*>B()n}})pM6R%U0(OS1js>#X4v^I##f_aIyBj>MkqKEthU^}UGGs(11X)99 z0A%-}VaSLEWRC)}N3zt1v($$qUX6rkW6?B0W5??e5h_<$D+^u^LQ-iNgI6mPFKdPA zIvB2pEpR>L09RAe+sYZPhrrWXns7bFa5cjy!$o95aJ7R5!1X8^hKp#x)fsSg%u+jK zsZV67`4TbO77WtuMbiO|9kGsx%BZkz7Q{M2Qt6syf27yVL`>5sa)oseurp*&SRl)H zfUGkq?&b_x7x1*MCS+Y0vaT3q$cRh`vge@zAPhjmkP!{Yo&jWivec)u)SePA+NcYn z!$dP2jUBH(B2=!h{uaDmfTZ$l7M^;GONZuk>CoSTmp+j(dfI|fPX~-fkh1>H7`+Id z_N<9fKgMVzMj0a_6T;{LNKuvJIwAUB(X2;f$Ll>2Dj#|aEqHwmNo7F{UJFgUtc$y@gW-C|0@oY| zxHgd9h0bt&1D>|Pglj&-wGpEX7m*3UwHq3M678186-G4R`V?@j%u-imsmrp|kFr!v zg0@FY_(?QBqp^dw5`h^-_PGVLUm&Th%CbK|``iRg(XE%lFG&y_%@mFS!+($!RW2CAhy=h|Iz`yGh}0vGkUZ!nzqqI z?;A$%EJhhUA`?Q7_89|uWzaBsL<7C;KyO=?`kln>T>Fk~Lp(;=?Xuuj0s54kS@vgp zyG-0PeIl3LcLIC@PVQ^On~m*q28A~p+i8NbgF%s-jS-m;C_w?rwFW3e1C(C?%1;uJ zkPr%sMnPk*q@OI6wBLeAB}gj!Vi4JHB4Vv1U55>jOq##n84%hPP1|PzvX=p&-O#v7 zh)f8OTc80|LffNpl@JX;jscJ(S?X^RlUs!xZ8-+<95i-Jj##SXqy>}PA*r0mvOh^Y zX=0-36S+!$bEuMBQgG54lsmxFPMDw^XHcqQltCdfAy8N)1!2GdDeo6KG9Yhb!pOBXB6szr~PfB zaE4K!-Od;VA`?QPJv1P)mS`9SqJhE{+1Ob;TfH<}EuXEH%Qha=bpThnC|ktTiejpe zEgv^(mu8DaguZAmkG}qvk9hTg9=nz^2OTy+<;SjKJEbeL$tl`xjH4qmq3HTR0~FDY zU>qIMh%Oz`Rm@he%~r3Lq4fm|VT;h(P-qp+(5wgbwIT=#PrKUe>tAPNu;vW*h(?UJAjX@r)f=+a$}+&oU?F%*c5X5Qv}Wf9 zGb37Mv#)38R`z@fl(FYTCgk}C&;WUKLSsymMx!c z-^Ca$#VBJ$WI`CNh6X_MF&aMhhz3UY0i#;k>b(-6FNEA0(R_)<4p1!-4`0&NvjFrJ zB$c``0M#=AvQ~wzgOAyJ9q?I8y6QRO^B?fEx+Xq#7@u_*WqgQC2%qnu0r+e{!}t&l zd>#Tm4`!>4v(<(YqVI+1Hqrcm#tzYg2+63S<`#&yLsEG-+kW6QHzCsWiCjaCO;tXYT@U+P$l#>|BM=;7z5_t|N3*PtP--Rv8CpS&=UDO~c?}`Tg+70}* z2*KJw@1o{4)xItDo0$8Qt}V5`EwS!o7Y)3`cN0ERQZjwMDsNT)xiT(rcLja9{aRvX z9X3zh1kBfO;IBvK>%)9`n19wVf4|bZrS`11`RB-d12#|H1k5*T;BQFg8^Qc#Fh9UB z-&pC>QXAlHeju4|!se-)fcb(uu#E=FnD)8jGA0_XTm@Hpw^DnxGHxjIFs?k)O6%1M z_lGFKMH#*u>619Dx6V$O4|gfDj!oQxh6FDk2jpzd|U0o~T zDv^n}`W_U()pyxLbclwl)ra|gHPyTDspiqg9rSTKK8%FCFXqh`;&+2XiSgYysC=Mq zZcUKB$UXF_FbkvpTZk25mPUghx!^U@Z4enb_tGpzZ2@#^WV5L7^)%ZQnaU(yIR|Hm zLq{W5X$57y6?1AyRSS!$N~4HL!;R2Mi@*n%n9DAKSOlU;YJ}B-{E*0$Tn;nBGEI^( zyqJdRn5aSK6H3Z5sDP%WXc!5ik(6}QPdzAA>(EDSd>GkS4gsYB29!HnE`#g7f)}Zn zNW@rYy5SHWSqUXHypl#rsLbeaqGhd8x>(j|K)DS})Y~www_%m!4cH3U(8vbz%()Ka z z7fgOZCiNuV(FmY$m8`*Nh@w$=rrI6#pSy+UvwRa>iO;DGuk~(iL+$kUYcsU(6^@sr?Tixt^T29%U}2_Aes& zHB2@smHQ;Y5ivp8P)tv#7KT@%O9;M>;Psloyu?^wzbUaIKWUSSt}qmBET$rX4KEUW zvcj>liDQg#j376Il*O|JM5Lo$Jl~RyViZp&Sv*@YlIcM?wP+~>);;CR1&-M~4N^-8k9mP~+R$;PHg*!2|NvQ~fg(}ee+H4;R44Wlr>jovBchv5>?h(Woj3r(^KiN2VMwyAgEX%@&C6}3&;FH$dg#O< zQdNxNrE|5@dXsizk+`7yt(c0$*_v?l8womG%&Bf=n`Ttokzy(`i$wZx6jLQa$3R4S z>IfY#rcyVADi{czD5fF@giaQ7svAP`csx~1MGgr4j;Ru%KR`r!=?MKrJDF#BP zi>b%~p}&eb)eRxVsG&2(ROEor-9Itv0zv~keUA*;|)SrwJf$0HpANqKx6Qa2@! z3y!*_^B7rLTu4jA(2;aO%&}@NE;Oy6F^=*;&eN0?KK7GiuVCNh;=)43EzhnX;d(9iinB1 ziED`{(247a7^o8!i5R340U`=@BAtlAI*|dw``~&Ml6-IlY2FZhUI;{P3!MlPXQ)mn zARG>^3uU2P{y%tdRr>dw`R9d_X~ir;m_4s!7Ik*B(*Fu(S^u6h{~WVyD`qMP99%}( zQSB;Jo^)_=VTyx`D^VO=3@{yBG&N#Oyq=UA2Uiv16zPe$frw!`aU&7Kb>b!>UeJk~ zi5Q_1w-E87PTWewNS(Nih*3I`1H$`AYY9m{(r%}DFX{7gLF7KB6L%12v`$n7@qf*c zmiO;D^Utg1PG@KScTVtk{d>;*b7ZQ)8Cgx$K}25GtEq;woBum&(B1!@Gyfd3dz_v5 z-?{X;_uq5opCeNf&d6%21p=$Hu~gA|r_ho{t1~ZVVs+-#ORUaZdbB#z)QB;$HYqh$ z=Q_k0qnBu15Z+5@Ye@1ET94+9)#ufxdBu3*;dZB3*|<}@znF^5+bjE{+RDc5RRbu> zZKb>S0QovjCmI&hgqyF|8NN0urXn|AuQPmYZ1uGX`8r|%6}kDE zZTR|-)z@YqP>=@9R6Pn62o)rUAPSPJgt{qtoCGRJni?@CJ`AEbB__8J$rnjXen%u>n7nCwO*-|;Z{6p?&4#3cP}a~|IU zG5IEud=tdv3?lh9h{?Bz2*1rBzdZNzm*+^L zJm}gM)3!kOCTJAzVxVC1F%@q#a5NyFI5%kYBuM|tp8dL`Es$Uc+GBELBH;o}9f){U zC!QqYHJ#`PqB!vvOf$cIKcLEQ5UUvP4$vz}W74YNyFlX2ub4B546r9%ifQ6sOh$_F zAhByPZ962R8>ZqJB*y^=p8}cNMn|m&h{$A}=xOEjqFJd@kW)xGp%VsA;5C4DCdlJ_ zFiATG;Nl$~cM!MzuL^RbPlEoh%&BG8C`0Ehn$i+Y+k%uY$LH z7Q>3V2p>k=vxMwyG|DoJQ`&sSJ2P+7=yDpxa^Bq-og=2agGO5l=AiObZvPamF!nBn zIrrx{I~26V8HWDxSzI_X(JddP8dlNP%w^tR1HjG_QJ5Ri*Vh-S+LBF$JJ%yJN~nGu}0 z@(A6&3LP;?BhWA=7uR!5&dB+UCP!EW%zp^;oV&&7a8C3$c$bhE1T^6;&jR@o$jD0K zX_Q5nHe5*0`Gkg9*-}U;D?r8yC6S4wR3pR7NREQnNVsHid@ijmCoSZSp@s2IGK{PM z8*jO-Ciw`@O3Y-%oG+xwkD*he8ZRn5t>%0w$5&d%&taxC-rG5?;=Qon!gyi+w=lmv zM!u#-SRv5<6y!Oy(Az)1l9pY;n9O}fx>9o2aNMTrtH?ziZccc`oUcd(<~|22m$Mi# zhE|gYRAkmE{$vB&FW5#z*kFXAW(^G{=W>-qSRDq}V$i9+{zJmF0E>c4WEoly6|nGM zG+cc|V;QQ3WoRQjS2xhddiq#LA8YYptV&;tso#hhTfku-IlSEOK>8xz(x)O=HG27P zL6z2xFiWFBE?WKV>e3lGTS=O|*a)4<+aOIb{T-r9-41Z_4EieOd@r?Zf)i zq0UkYD5zaQDyYpgp8zPvd@4x2l;r#^G@r2JLf=MyLF>2H(Q|l}7F*^KL(5juLK$M+ zKj^x@vyPraceyy-hL-Q4g_nWqSayB6n|0;eFpT4i@kJaz5Sfz8DUNXJ_yyRV`edJd z@-C95QWe?~Db=5#0(SSH;UXa#rCJxI`ZHWq_t3|W^s$pZw&TMn)t|-Gy<)~ba4e;I z5Tq}%pFS1AlBLQljRs>%^#Dn;7yF=7AT7ntRjT9}m+G%l%K>Q7$ZfOKT-7<1+CiF6 z02E`sQ>p(-^9egHr$giypgv?BJx7r7QT6;9>#}Jo2P~B86k2497}EfP60(u(x)O=vNoBe(V(?9+hydOB55}JH*_kqK$>ED zZMt6SkY`+*e@HE7p+zINIe&lBIAZgqSw_!cB<^e-F|_!h^$b4M)A%qF zohGEqqEV8D$G)vkl1^{ylNuzXWN+(V2pbyNz!f9M9>_@rCA_?d9PpC^w?VfdCa;3M z-p?;bdTA;=x+4WGhkY?dBc(_`z$gzwz|AKQpFVsk$(*MXml07~Cn^wezD`_0#05HW zB@tzG;wmE2bmAH!%Id_mL|mv7*Aa1%P6UW3rxWQ!T&xorM3mQwAQ6}7M3{(6bwVNH zGM%VILEZmVopV!eXE0th{3!~XX?wIq5pQ$AJ7%##_G?*lgElV={oxk zC;bMqsf};I3Hx^fh+HoS@FG=A_?XR(IB41H(A{lXVqTstT1TJ#gmYB%E61 zaSc+pbsiTTbsx{;Vq_q{#ocZm=aR|qiR1(_xs6CpE|dH?nhT6cejLqJ#UwwD=DK2% zA4hWmGRaSvxrUkKC(N8)Ciw|7*D;g)gqdrc$s;({^0<&50l4;l5;oZDmlVy5_mO1(v+BrtVL3^LW>ejWQDE|6);c_4KGzhV};H{UDQ++e5xUQ z7%TMsLb?GOB@5&Bzo#Nerxlvilz4@H05&wTfv`FBK+g4`gqID;fhb6^LhEA1TA>?} zUYbfPw2GF)Zj8}LWzr8Ynt-sN9npvJ*UP?06`gp9h#PdG84)+?#KT0~q!Z1FxLGG2 zA>tODXhFoSI`JqGx9P-VMC9m1OCoO9iB?49>O^ZI?$C+HiKwa*ZHUOziMB-CsT27` z+@%xkh^VF$PY_XEC)yKHLnk^Aakox%B;p>O=tRW5I?F!>OXoE}iWVL*kjTRG3{=2CUo?CK5{-qY9x9-wS_hwMZG0FD zPd_33EE=T&#_bCaNjfb&q^86RPk-3Z$OgjZ&;vP*KnX9OBM0sWsec(J#EP}>3?RKU zl@^|cXgTZxj7A!RA}|Jmu%KOEA1)-BCOR>ghzE6I2oX(n;&~z-(upD>n(4$aA|BR> z7l>%C6C;RtL?>P(qJ>V3BH~e%@2v6q&vT z7?Hh7GHrC3*Fb1`%1BnfWNWLlCpoBy7|h8!Q?FA)|5VbSuPc}qtN#W(yRVqjPG`UF zq~Bn^;jI5n(*K06U`DL|!+gosUT44Mq~Bo9bk;u$!&oC9&{a?gDO5VNMsm?GPJBhi zsbZ3^$T&Yt@)a59j!C{E<0@g2ugDl7Ci#ktD}_nEBI7DzlCQ|P5SipFGR_{8d_~5^ z$RuBpaiKEFS7cl$O!5^OR|k`PMaGrGBwtl=jWWqsRSYwed{xDD$|PS^aShXIMvz4e zz-AME$q_z&!J7+`ro>dqJ0wM`nJAk?RPqhO+jMZ$u zkY0dB>4tIpYDSVys~M>&@oKgZHZ-zfu4X+z2`@h&2fBh3tC=oVtkrB0>7}W(nsrCZ zVSk9xNKeuaFcyQbpxs3uUP3axbmAi-p4N$_MD*5)RM z!eSU%MKb+#na@FJI(l3&;$H1poxR#YMZ{o!p)>W8G4y{)`upn&zKYc^?$w^t*=wEj z8_fSW>tBaq9QaS^DhO?bP^JT)@ufIg`awuZB^I!5VIl_em-Ug5~B?hB!NQw?C0a_x5)wfUq16$B= zeG!erY9Nrnt~vNLj;O6*Xf#k%_zrJFP!Pc0EA$WVK^zWacLK4UjCH$&!4MZ}zY}J* z6;la4aEslOCaFx$5Yh*4e}EdL5Cmb8Ccf;*9ZJlIA+r4+SiTBZ)Ja#hyRFOBOrOp5&bVz z_xv+&^|$f{S>E#b`JZVNZ$kcq_|12AJ>$ol7WAFlFaOM2{e?zr{ClAhM>8J|FtCqE zI&24Vl_hf69)b#J`V|cywnXEwZHTA)FF>g}3?Igk`UDRH2K4-=TFizPSh5hq3g{U#Y+l#~9QPyV&wvhWqu1wt%!F{J3r25A%!>u_B_6KpA%>=95I zk~T_SzQL1*QG92^Ucku~nLriaI&VtE`E9#3bFO;eRH zEK7zKu7cv$X%@|luhSVaifr;Lu1+s=uTzyK*b?=YN7&bsbX=WQ#whBPy+GmJKx9fp zM9ta4U>*i#o!&_j$&#d{U7>}V-o)f3nvX8pR4R|xWhQAy!8~4GnLI`$*E(I3lE#R! zpjQWB$2We>B-pK2fHMg~D5`%`425jOT0p6zawOwj}+nf?LnX=(DJLEiPsSEy-U zhJz~Ag&)_=?}zA|QTP9~AjG>c8s!p!i0gmEQSbk?IK*|kJ?+lbXDyVSQQW=E$}qy0 zITqK8ZzVZ4}L{~rQkD=OO`5!?^WxV+{A0mwfPYp9gH4yoR774j|}HxO^=EdKuy z5D~*{BXXK<0_L(GiL5LSLInb7f`*TOqOr0(ij`#^l&bIH!&q6Gf~V0y309Vc8I! z)15FtRm*E)?qWhJV&L`I{~z#D&4&l#%+HZVI8xL^OT>tKjYS+d*CPg7#Ri^=_4<9@ zPgUHrMOYq^tz#t%N|qnn>R~&DJWh@!M|j19p|-JxoKGQ|Uh4VI;`W8k1sX#~JMw_e z2MbtfBIkn+Pyy%Lqv2JXXq*q8!1-V)l&VYcVVn=11W%)Z5}XfKkY}v9W8CZ#CE{5u zO@}IL$v~NAfPz2ERPAn*Op)zmAul!gW;I#f=E!qaZ=fqa=r0_59-0T~As&@>he141+ac^rUjgHrW7d>Cap9z2Z(N`T4^@{Bc4 zh?`w9RP1GGbE9O6N>-L3oN13%)(DKD)fa?tFSLN4vP?ucNCn3S0AD4NQn8%^PH1tM z4;9cf4-ErGG*VHBRP2XRbuWGVj1MCp3m~BUiUIq(86;wSmu&sX0Gh9VaZ~)C3|I&o z8ri_Y$hRkfoZmnR4?iF#`BqdoJx$qzjv*=!?{em!`jJo-Je<4{|I=;QB68n*QfaIS z$13CJGVoqh?m@DPc^_gPkY_hQY9Qs0hgjv7kQ}8%Oibi@a0OJr#8Nbz5~7ikkx0q! z@J2mJAIItAD198phmo9*#nhFe`2>yfH`p4<6cxUWznsS7b<58aEU1LvW|_}l7dERj ztMCN&>?u56nQ;1y=KfX8xq(V==uZrdr$(!2`k7)*uM;=@3rwfP7ucRV+kd7(Bku-b zn+s%?|AIY9JcTYstiDQbifu{pP?|8L9}2-EYW)w<*A&M%#g>@y3>fEaNMW2(X*a$W z#*ysPU~uJ&TTcHAsKUru4C*YH)_)jvyCe+4zAvgnD70Tm^Pn#%_{VJ8nI?UH-J`M0~Gd~x`ql@=L?8qIdV6v(ILNro} zEMwmK*m>!8ANgEeCg(g7SGu$m-)Jqym(Mn1mcM1>FCF!2;GJnLImKSDx3ebp<7+Z) zaAg4zXfj6ea)mW4izQ=&hz-!gM~Cfh^c##~BMvr)I5!p}PP`pcx@2+cg~xGP%7@}) zO&sSYGHq}*qgG2E=VpqNrrYA&BI0Coi1S;JxhZ;bw}ObAuM^*ca7!9jh`zXAK=SPP zHk$D-B0%D^K86Cy&=C>L%xL5!1J+G&N$>_kPlolFLhRgx6C3Q_+JM z*65r}R}IF(Vw?)L^`ep87maC2}wD~Y2+E^E9FU^CV`MEG5@?FomZ0N20eUK;*S*}DXd*gS|~_@ zR$Pz;astE#Amy#hbJ+07a}XycV(7S(!tr*`FQ?*5=zuTx3f=r=n2K-y*;#mVIeC*% zz!^E|y2>la8v@+`i>p@b3zC~bLJ>psDiWnU*+j+mED;ukPgj$R$+?`=2DImF)2%!ChWdT}loWW-vuq03DgKm$F6>ld z9&%%rO7{P)qmpu^KqXagOX=--+!6|>p~VA*KP1}{fk5FDSm#3Fgk8p>!-~RLNV%Zk zPxfEw!Ay2z0)uW>Rzw;p#?Fwc-@4D;U3+!uY34cT_jd$C1aI*ynezh$lca))kh>?p zQ-{tSdggbxh?e7Wc!jj|?B1cv6Bbs6p{489h8vx(c5&lLFya*C84A{<3k7A9&P)0- zy=8-LRC7HV_w3re^%GpSrBi&tuhM<+c%4P`ziy)IS+pp_aBE10uVwY_Pt@zs1K`L? z?^cQqfb#2qS6AVe#`5g5?uxfVg-nq4PmH=b`ScoUTb!W@0i;Z|*l9pfeu>69% z`eB~xUz6%5c&Hx_o=ae3-7UZDX?eP|JPmSgkWO(|Kgm=5yHfoe5B0Oba|vvwyX6_4 zmKRCO3p^~(b65YKr}`CA{ZbG0OTcppY_Xf=vPn27R!Q}rc&Pu_Q^z`~<0}sxYru1H zakZ!VjZ*#B9_s(=spAK!<2w%>--74j;$~0vyQTV_9_qJy>NqHM?1P+(8^5@zz!@7X zmvzOT^edQ+@_Y2^)YEbz^(P&|u;ozn;}rk8ue7g#);AQ#De2O2ce_Wu?Eda-_YZHo zsX=4;O$xd~;RDNMiT&HlrBayZ0L6J2_JE?Cbg8Vn-7;Xgrr=^{yXC#@UMKBd4MCTx zxDqTEC@u%f)uoDHIzSP?um=5}4ZH{@kE>TEa5+wLvW?u`(1fuagnj!=|M@+aNu zZ1*;AyLU>vcX%nk%UO9fZ{>BQ@>&pd3F=-iyLFxI*7LU8SlWHSOL-G#mS6L*JkeeKE1v3SO7(Ag zsDA@Im%ygES>{Wpccl8aJ=D+g)UinFSm2>!9(XP;zUQfasZ_6dsQ=JY$117g6L&X0 zc2nW^F9*w|w*5(;gXwSvT8&|kGtheJ(tq6Te&uENYiGL~yzOq6cE5+9OGdVW<#L#B z0m~JN9bh^@u@l1{Q0$W~{p@ackC)y3&UO!Y+dU!e9)+L_6ozK|!F7le%K&hsGX5>zT!u0fRn(;5=r%f;!|V8uW1(mieordLFdO1?ux9l>;qsJD!$C#2jW>JFZZ z+ugu&b-N3gUT$}i{5ZFP_GszbD9E|__9A$3zR~kQzyAfPKBf-v7;%{7Sxi5L8%#cl zPLZZx^DsRTJeNej0#=+?;z`>$X*tF#J=bF--{P53om0Vd%jIn8^jnZ}!|P4(Ts(V2 zT6Xqqn&iiMhIB2G<`;OFp9h``X77RJ;@LaWva@G%B;U!ikELhJAm;|mN8q`5rh(<+ z*@vE%*GS8sdszO=UHvDX>NiRC8$8sncUQkos&~e9t>io5`lB?z!^8X!;JM)XJy924-VZ6aV%Q6wi)TMe%g&zdk^DH%aFqNh&7blxe*!!g z%#MNO;@J^t+1az-BtOnGf6{3%-7rfH8&@DnVRy`Y;JJAAx3ui+*{2WIT^-@BwsRUzo& zQZ867#h3$@*Hy`_lJDShH834qu8v_3m+MHEYeCS(uY0}h)^)a9&)aS@Y4<^QyN#t? z=YzAM+99tF~`{t$FYVLz~3py~^jR|6-m3!P!5%R2fs#w>EPEW414%BS^D)V1YMw<0G5l(5}i@*Bme%{F;kl55Ja3zdnSZ3zQ##<>K-Ju)Lt0C;1L8 ze*~t3%S$or;qq$f@@Eiq@#_<5*BQ!>CEvlXFTiy0YYm1y{MsV@+6X}xC^vxR;_`a1 zyr5hs`3^3B3#Nn1TQTh6@^0z!E(pf?C2lEqNV_pm;+FCU$+P$*ZYljqd%$$?=_d?( z_;f=0bQFRvFdhag&Rub@c?c}myYqu!dSSd@@-6WgH=-xObcp8^hCSj*QH%>ozvAlj zS?F+e`iyicCIR~0^J&R@ zfaP*1)c{KzEtbNfql_OIHIbGZdRT7Yq+Tp6^_|oci`BQ3>RWiIZw{VIV9lH?i#4LD zlVurLduch}!*UyU^{qYC_mb+nd#LXQo=ad|+%0#KmYtW1Cneu0qXVU9&q23*TIwS$JA3xD_?``)DX?H3FT@o=FESE&Q2A0b~?N6ExrUMjjV%P(Ucce>iyW5@R zW%pfYyYG41T_)`=fuIW%i@|b%Vi8zgR|5+rKdvVINz1`>fNBMXJ)rthy1W{KE`F_& zcAbxvPbJ^Mudl##@M|rGJ^cDk`n3guE>La)%f;ny!199fYsq(T`Fk)OT;7IZ50`(D zF7JV$i(fxVyUtMVlza!j_JZl)*FFq;_|-MjxZvxQX%n=qqECY70&{z?;=-xUOI$m! zT)wx)gR9=sa!(J--QCr9^He`bsvqE?zCU;_f%S8@+}G3caB2B@56eT`)falIA1Bqn z?4kZ8@LU2L>27(1r{&4g@~a+}C%CI0@2UPRseZbL`q#m832dsHWxhn4E7i~TP(RaC z#|Ki!d=DM(gXiMnyPoPllIjScF_v)!HEc8^HAhal*Zk%M5l zEV28+a)sh3m<~`J!>|Vwe@U1AaJPHP%kCLxyMKGzy&z(oiO!3-LXirV3lzyC*0X5Ok@EYrt}Zf*xpOINJ?++l@-QmAsT^ zIV;chR(`8geiH;;g1W)W?rqL?bG+@|CGA%AQeMqjd3A5)b*1v!5OfKurkCA%&UWj2 z+ifE4HuO^dptJI(-pad5<(=$;_G?1$Tmo(nmSbu9{q4YVIZEl8P+IQkVY$1z`fi@; z2TAnpJk`&V>SuVUpYEw+p49QKyBl-eRQUaGgXL1&{-pU}I-G$P zVA$gfv{bsJx!e8F%kDB~yUV@pektv)hM-GER)OVmn12eED->UW=>WxA40}MaNxHPb z-R^oXyPKWuZt=FeOWNHIK^G{tf#nDVos55Uw!7Qg?tW?a7cb=poRuH+R(?_{KL$aU zppJOiJ>_iocW=9ArQN^0l>4HN72?ORM}^di8ds3_*adCpts3CD1Y8X)$1M8&cY@{h z$f&C1TOQ5S=C23*NwvX@EqLRV)Pah~Cf`=~VE z+{1h`ck@l9dS~-ZBtOo)Kj|?r-GJ#JJ!=OkH(=U==aS9G!E(W@6>wsxOf0`+KPG2cAn{ecdhhmX@8f(M$3jvM~@$w`{y1oi2iuTQ-J*=K}d) zY1!GcL6RTm8B#Jqnjhz3ehhdnn2iR@#j{b;va@F|N`9PY{-lXux?wh5Iz0_iZkSC0 z&&9Jz(z3H>uS$NLXTWT}H2%k>q2nP7UYl`|wi&TW6v0x;bG zT_Gb{3Mn^0mw@Nu_F}MH-ChKym)i>^KhABSy;l0R26Aq`tp?A{-knX#>S0z znlHw%<;aNr0{trK(&g@UFY~f{wX@x8yzSmB?cM-E7bq%&<&p>$EUyyDlKi+t_>*n{ z(*demG3)_Vb?Ne*5OndYsGC5Gbn)w9Y1bLbha}&@ua;ms_|*!-9)5L^eszSP3zQwe za&h?yu)LtmmwX48yMpQ9ayJZnxZF>=+y{a#emyPiIz!o0@*Vto7EA}f`eWF`uOjK! z5D2>XRVeK``!!JV9sC*wrh{L@G3?>j4C&V!5OhiLG_YJ;o&uIviYH0FgUfG$>EQBA z412gdU%LDr1YP`kN7{9Ua*pIX__Y8`2fr3#*u$^Sq+cr`=mO;muv}bT2A1oU;YVP4 z;jBr%Lp-a%bcpA3412`$jf`hK1YMk72bQbTYr*t#`b)`oaC#${4o+{vu!qw-q|@6V z=#qr*z;cX-u5))f+uh}DcdxYjlb7;+&dT?DD?cukAAz7tP``QEJ>hKkq_^EO((a#L z%Kvs&e%4$0mD$F{XN7EAN^MWXE(Ome;PPNOX3_622bL&2OJUL5O8h-XhO}JK!}7K6 z>aX@xuS)e%5A~Vgxdf)TTMl_zzExVj$;0vu?&>Rhs=rIBuL?OA=X2e)=eTS4CshN} z;c%~xVUNSTj&!M(yWM-e?ACR*ThH5WGimoh2)aPg7%Z0pZ3vc2f%=mk2GaqG<{0*X zqK$N^mAl=?yzI7hwwv#5x4X346@o5MbOy@>ijH7;og_L)e%!I_PwD}t15`aR>;csP z>GHD>bn)vMY1jD*qL1V|_*DR=gI@zN?BUla>DLGdxSe)VfAp=n>! z=Op)82kt=09pJ$2+e+-3-MhnPjWL$e))-65M^Ef1-p=TyK7rn)*zV+3RKWQlCbTJx%Q`$NI=# zU)g)c=#}b+9(z#gSvl6<=%qd89mZM$9z5XV~_eeJl3U07t5M?Gaq%eiPPRP%&Q4jnFc(? zvd6DDjLMeM|4WrU8cD@}rErMN!z^PRd6zUiZc#m){{&zz4Y!UNrgd#TF*^AM(}9cs zed+$Bg*4RNG6WM#FeX;jmFV%Blk^FCyyhf*iXNkw^qK6f5o#rjd-Sllf4Ty#UWOe1l(h3^x zETr|p^O8QoV23U}^E!$a%EEh z&}Inni6Hq~^u(gP6}>XF6eoX&o>-K>M^7BO+hp$ty+`40L|+g0#<+Ml5EG7CIlnRz z>&|HH;*T~+rvUi>ARYXr<5RhZ(ax6oR1@$q?&>6zJYqvIC+vXGK^4jk-jXN#N zeoWTWCYO^W9*bG3afn1PE>f0_o=BOBo=DmC=m~c#qbE{U1wE0n8)WZB*}F;hZkD}U zWbanlyG{0TWbby_%ay%5WUs31<;mWivUiv4Rg=ByvR6a)?v}lKWbaAsTl|K$IA^rQ4sB#bfaasE=`xfCtbM322C(NI)a>L;@P4Clb&EJ&}M1Wv{91 zJtTY0Wba|wYc6|_$X*NCdsOxwlf9O**Gl$U%iiO%*GBf*q9=ULmt*bZ*b{QBy*@?| z*FoP2;@ULs1o8dEh=I5PkHtgW1>*wZr_d7+cSlb^+ygz~Zcp?C#J$iH5I-$@y=AYD z?DdtsXJoIR>^+N~(A-~+J*SUR&>hit3c3T0I|bd97%@S2$8IDK zk-ed^_q^;C={<670Q$cA_gT)(D&0Zir;_~1g~V&q$27?|XIM*K1cNT@l9OISkMEt5 zMx)0#C%=pyqnkViJw`Wqoa~K9PdNFC>`j!tSB+lEB%_x+1wEl;oi*JHWFj-v7I`8~|r$}0Lb7hiSZ22sJ;wSB#!q zwtr%jizoRkdg8*BeoIkYxY94$iVIiz(M9njhJLD%SCdrwg+@O5Q|WhBuj3~j^h>0o zM?cyqxb!2Re2AseuV4x;{Y<3j(N8|onncC_JNd}BRlU38x5Zkv5kFBTe`+hhVV|^1 zS(XiYw&eF8mwf!@R$CV(M{PoJIt~-NgZ)nYZC-x;NoR;>bg%%pmfMO=`>q27p(v-TDZFgG+5;31T1 zoh`Q^{v`UHLtm%-cJ@1I`k_Q$_YP0Aw+>T~rP6#C@a446SEkElm)+K(PVPfDRlj@e zf4&*fF7Qb8B>d>*y}2#+y{`T8+Pf{<_G;6yW!J~s_3F{4HGc0cj&9SsTaTVyyX32# zaqFGmy+!99Pq%5&=hmBBG|KOk-?~SB3q#=gZfzg;UE#aNcdhTd%kl~WV*-N%qXKg? zmSoJ!SQ}iBu{+~~jCsMG87DLLW*iFc%h(&*pD{gjAY*svV8+_euNfOdhcd>7f6F)< zI-D^$d?e%d;L(h&p<@{zhK^^<4V}su85|m178)Jg9-1Cp8JZOw6M8o|G_*hXLFi!c zi_nqauc5)A7emuRe}ra--Ve_UeIHsA`Z)Y`Xhe8(XlHmw=X&^O@&p$Xv=q0hsA zg|zU%@YL|I@c8iX@JHd%;jhAz!=HrT2!9ry9^MpwGdw^1Vfg3p^6;MUn(&tJw($P& z58)rf+rxXq&sQ2<>CH-WDlM-xqRRftzg8YtWpI@tRf?(<3_?PZFTNy@9<0)>XRpGv zF=^A%UQe5z_I}#ov?FQ9(@vxn1O^5Q0nCuV^MRtkFaY#YU^Ji_7Z@Ly5O^&xH83sk zdf<(~^uUb3TY*`DIf1!>cLVbR3j-enJ`5}gEDNj%d>mLA_%!f&V0GY&z?Xrq0{;oD z3#<=(6WAEo9M~Gz7T6Kk8Tc``=NQE1)&c@ABL8NR))SnDXa~x3#|`*9oiV$9NLQF*dE#u+7;Rz z`YD7$3>^sl8af<09y$>^g#tPq`YUucG%!3kJTzQ{5*Z#I5gr+S2}Lp%MMhlLR7Q z2tx~~7#ZSXBy6pc`D70Wn_vh@fK*6g0ti|q;;407!BMno>%zJRYPA(dt=8RIaTI6u z>uj-BJFNPDpK(8*``qXG7>2*^@BibapLfo^=bU@)x#!N$cpe-1_{b*^Mo*1=X5@1t zUl{pE1lYEbuZ(;RVYMA0^(F%AF9^2x5oCWGxnty~BmXt>w1ZDSc>BRW8ujB*XOB8} z)On-MN6=k7YQv~YMqN7U@=-q>b;YPFM_o1QY6Rl-qi!6v8R2;6sJlkpJL*1!BF8q?773@nw! zd3nq$W8NG4{@4%3emM3cg!5m={%!1zv7e6p``FLM{$uRtWB)n!Ut|A0_RF#V9sAYT zug88fwrkv}<#hu?Ro>FY2Vz&wiWGTTAChNl^Xfx z8*~aUcS&=@$}!`{U6>N-(v;P0%g3x}@@P1clrc>m&5bKpH`A~3q9=K{|3rVr{TtKR zvV6pnrJP2RDUlx$YurEPS-PClQgBU)yw=h)j>Geqr=^usQ<>-0uDz1+G_T>*H0Js9 z5pH3ur*kdyV4_4>ceOKNU6==hBmE;gQX;2Pk#YYhVeI&v30c;^?8)P%=1duvJ#M^} zh(EK(jhi%SQdZXZ$>X!90JE|d^&%feyrwgkp7U1ol&|mVbKNVyth{;COIwB=T>Hq+ z?@03o^y%qQ-tybiu+or!w!bNbyq!?NUYX)6^*Qlf4kz5?I3m}}%(eYad>v@X0%`#3 zpUui-jC%JhvzYLw&!_&U+##7!@3qW$g+8CQ0r7otwGMJ*Qm^ZB$LD2H0% zqhBWS!J(rmfLoR~cN{sa@W{HFj<%&84J)!@Na@Tv1S^q4>nd9sJK8$imaNR0-O{0vZvM+w5?dNslZs<$l?i+!ZXl7If%jm z2XsBM%4|Zkoku|5KwW;ld&aCp5 zm7R6jq#*N9z88;4Cx2myYWnCkM#F%AXX5`In*PS-K^(Q%#`wn}% zb>rM``nL|*HBD_8W;<5G(}-8B*7K6l|suhx`(*}LiUBS#$m>U;fH?4IHi zSTn19sAlp}1q*w96`i>Kn6$@!enS7{yQVVG^zb!bK6cE>MLRw$dw1&g=e``=KX&+T z)p|wqipKV}^_^^9YTfWhuex@4&E-cOwt4n1{&{@=mv>JoYD~Y)%sPi&+VtqD|CoOI zSKlwb>6Ytz|GR(TuIaQ?U9~3TyqqJe$KUt(pxQ^DEZ#rroxE=3v}yGPx%J~FR2P>Q z7L}Bg=eDoxm^LxjTi?S=jig1^K0Um6f@R*RE`yHqjR9 zB|^Vaq1ywY%7Wsen!@tZ+!NY5n!Z)&eqX2}x4gW#sIsQCG`A^Hthbc)fR^=$B~}uv zjFp$<<>wyXt=Ln(SXFLyVO3sbQE_GNniVS&1^1Tn9@O$)v;+&Qi;DBBs>^cM?u6iW zOR%)Cw6Y|>pd|Oioe=!Q7p%xFDX%IiDTUz5#71x&liC&WOjB3nR+pBRm6aCdu1Tz* zBX_tZms3(&T3lRGmY>^vyv9e0xZ_fF$7q|oydbZ{D&_>WcjGs#rlqZeY5@USqLOEQnPW*Ax{N zz~}X=jN6^M&aec=$6!r$L0M65>(UT&X4>q9rDc`*2!+>ZURu`1VU=hcCy|F1>-1!@I=Q2xT zQZ*v8s-_CTN%3POoCf%TErH>$y11|!eFfFbHTlKGHDx7*(jQDk9Os^BNldJ+ ztg0z0fOAn1zXLfn|Di2Vksqt6sYLss9$^BfSOSxaiz-TEl@;78f)H_n>MBcON@aOP zUaYz*ciM=OijLN4Q#%`)@n@BG5vTsw*plU?RTZ&vbU_wv>PGYzwrFu#NkL^*Rhfvc z>PGZBTeJ*oj*6nqWJ~6RW;=W`NdUvxl^!uw*M{D`u3OheoWi@B};r# zQAu$uzoNQ0ciglQ1+nGJ*BBwE$+uZT6DzSos>~~v@BLrRjx9t z)HY{$`->$qsiv@`qM$IZJa^n0El7nN+dj2~CRbI(N{cH?igTw;b*tn=%-=1sNk#d^ zmDR=7r4Vx}7t+&0r14v;2m zA0W%xZ!G!A#brgsv7$0~a;obXr-oxs4c1iIWfi40g@q+(wDDRW-i}Nc=igKGfr;WGDaN;3` z6K1n29A8zFAImE!sm`4?5p7iA?*W|kK#47bxuv|g7;9`ulvB%^7IK89+d?!?mQ-Ww zfP$um6*J3{$S%$=&a0}ZDa;+0+*fa$7StoByr{UUq6!1rv~j+2XIaqe^nibINli_0 zc{vR%;O|_CT9i^~muXQ>qxZ2y#}}X`u~IBV+nc6MR(_}E88&}mK}~*jRbfqTduJGb zW*k2zv6_;CqTJ3<{rzqJg1n+4OcwdMouT^ovG^wx#;S{JVpZa*rZrjvCrG{*Cs9~X zRainpDV)_1A~D#Km>8=nE33}0#B2eHW?#hV!u#1GWqGlZ(&}n4t0PS0083;-epP8< zbspC2Y}fMSH963d7++alR8x{)Si%z7$s6w=OJG8NbzVtfQJz@U7*fP=OJaOgd8|CY zs0I=f$*kmMjI<iScD+WyP@q>;b8Surdy{B&J}spI==@ z5?qE(-j;#R1b((v_7ihw_WSpoUZOP=6l^4{M7F3t#F7|`osnOUt_G<7~ z$FSWGW6!qPON)wX%4#YLbB_;WA8)ab&o8a4s46PL-Z8MoF@9nkKh6TmOKVDVR|V!c z{F80|;_`~hvf{$rRe?DU`&65~prE)Sh7P;x1mAjx{V0n)hxQlMg(dm90lVYMqb>Fc zHI+40`Gqw+q}w6r^zb%IW^!p2j)5wQc(GI^A#$SA*v^o6yd^%RtRhxfRFj7V0tEGRbp{aRH7w$b1M+vE-cP%4wF|gu=>_>ikmEH@?N+XIN5GP~Ecpk}`~3PK9j+ zPM7?VrC?H7ennw*NfG+9n41%B?vLZ-VujV%n{&Zb%?aUh_gZq3O9~6i%1ZLFmZK3T zXqM!jeZUf(QeIvei{)dJrKWO`)+pjs^Vha)aZOD#DPW z>#+yogqzmVYf-$LQ=cg0;o?{8)Jm>z4f7h6Zy^<#g`}Hao_e zlDwjlQn0T`K3hz-*z>VD!PdK^s5mdTarMg1rku`}X_H4x8yly}k}T^{~@Z|jA*xbvOyEGy}3 zY-y=q*|xmxgl2lpQUrbgfxAec9=B6Z$k=*&t{3q#{%8xVYHxQ0?k0h$xcS|6ElM#$ z@B5~bjcRTaZqC)WcQh|)S%U|j($Y!tM3i|C{jn+ymxU-egA7HvpFu_AGE}Lhsd3qH z^~-%TPl3o55;+*RxV!Fw$gn4n&LLH2;ck1^IjBWy*M+%wv$1nXG-H*k1kWV3Cf9K;>G&Jz*b?Yi10Cb` z^XgYGIYEmL>M#fepGQKod*SjHguX|0NR74+iS*kql2H&R*J;(BB+n^RAGNAd!aT)8(c7vpwwAUO(>hwsm}N-g6}y^zFyc@Qq2_wmJ64T%ifKaz2b zE#_K!5eXhS9G7QN=wPX%3Z@)@@;X}+opU&<_!APGmW|6T*a06*f@$QO=TKt*ctN|& zLm+xFiO$NwWijqvk0Q|?B>E9VV=QWlY_z;Xg>E3p0TXd4$8#ei;tD-BPBL&0$!#RL zk0;@>?t7lM56eYj2ShTKK?rp;(RKpvY!g3 zn8x^Byr5ksiT;#C*G$9Z(*12wD)Y0U6aXi<0XG?9n@H@?*|M+mSKTdMcL6BUM(EAG@b`^=8(1go|v3{3Al>R#lJ<%4k%Ok<7NwCKf zTvm*;1yc_~U$h17rXay@~LErBS!9l~wP`4#W>gOc&^hvnfIMtVeWBLw* zotBhq<}XNY!O6IsidYSLKFRGMxz5%Ezm%c8Ye{a=IdsXjJN|=^`_h*4=Yx5Wx{jn) zpNq>rd46Bo0g)cVJ-?(liR(#X+IhHafW$}%6!@RY=|7z8OE7OX3c7*Brk{_?nEbec z4z*=$XHcbXB&qEe;L@|e?s-q5usmDPZZi_xOoCf3!sVz!Tku^7E?`09MZ3rvNZv$} z7hH@>Tai5qz6{AzSh6vpg0+zQCCM$k1edkNc84XuTo5N`+e(r*ljJ^^;WD|zmLyv* zjhFOWq7HJmkle7#ak&F>8PpQd$OXeA8P~>D&>pPGHMf%3GbHx8DUN3dGW3xV)PQa{ zFNV}@Bvo-6E~94JVR`?ENXAQ+l~2#&mG-Yt{^*J4on> zJ8(G>Lj9;_cqteXOV)XvSQp{x53J|-E#~z-F_VLFK4!ZwhT)I&M{!xY5TTh%4)HSD z*LmDvZS4)muWE*4G_H52xd=mCGRB3tDnNXcsoS@qM}O@opc{bw!eVOiIA+|hDm#Re&p}- zqiEFo*F`>o{C|vmqO0yF`3GObC1F29Fp*GPg^^CwYy ztRza$ibUxNkSIOa5v9j9q8YikigWX3&vnXqh|0O*bzFYlgiC&uTXuvgC+qyWEGj2L zxN>3(4>2ZT- z6J6-BfGFMRkJ8QiDBX{b(k=EV-8PTXt?=kdy3if#DBXgN(p}}~59va8f1?>^;41Z- zTV3PSZ!6WW=@VR9Xqj@Q>&Mf@k5>J-YGizb?2eG#5wbgyaXGG1&J4UM)P%>{3ffv% zcC;;zYq^K1#1}usB^T?PPWIQXPSOQn0zQM#QRr5nT1>*$hkE3T@(d1+O{ zie_K!AsAFQU_sY4=yP2D2DSZ2Z8VA@bu*+Q8F!LwYjbl`{fW&TZDwP;KAM7LjNkn{ z@6plt<2jNaz0AWS$&km!cB@}z>55GByaDgULv=*DC;BOQ14JXnVfa5XmX_>PfZ zN18YuA=ljvo4bxU&hujIx}HCnA6YR!vU+|*d`Mo3klB%p?~yjz)3>#|Q`g`2MU6?@ z%W2T|9JJN3{gJEdA{nDdj*Y18Xe@2QH-vP;BO4wgsY~gJ)Z3QhuT5O$_U*Njb_Ary<+#2IKv+&#a9f4;(@L9NOi-y2vsNmAo=^UApc;TJmv-||5!(U(u6qqCrSSCgCL*TX4{YHLFAYC z^5WL`>i?d^UmOPUrZ{m_pV}jm(dvjh)qjfQ-yRP6`{LwLeUV@7$UD`4n&fwkfP9~J z+k8}CQyYcUpUBuh(8K>b*5I#uC35?7OAmsi(32fedQu}w4_`zxj>T0**QbG^nT0$ecpMYswN_qBPP)X}F5g zm=mSmJcRmUggR7&Iz@y6J3=uOA=gCi!L5quy>z*sF7yz}PA{aEJL}J+(ncgrHIng5m9>HAxcj$MCqY~C_QM9LeCCF>2ZJ*y2Br(oAyz<`QC%>rbp=> zd6e#aN9lfclx|W->CSVM?k7j-E^(CZ{YL3#Zj^4xM(M_Clx~Ukpxc{0=w4-%Zaqfn z_F)>`3rwRMdnt5_E`{#3rO-{Y6uSA9l0hpZS|-eBUfM!0>hjX+tdx{=>Vemz2i`Uk ze`Mk7VqG`=2rsYj(kS{3WTTNYaLMR}tHeRUD%?<7k+;01q0{XsSqO(~XpQy}DH?nh z6j3mwM*f3HqK+#XSeC;H2mfM1e@I?Qfi$`YB=3i0*AdcR2XYsS^4dpwL66twr*cP# z-moAtur4yVjus4LV1(}0Md=<~l4sR8Zg55EzEw2c`}LH{(wf@(8AZkQ+2g&g zS2I1F58#x)ub1vEtfEm0yMy|Ig8GV?IGKf8I5&znyC11)?5tmdm(0Dczaky~dV4n~ zNjqaueZ6%@sJ#u#yylKhi1kHbEY{UM%cHYU+R7E3<8#I}PMSai!oN(RTf(x^y`#7W z)iw2%MU`IHxc+K>3M%(_Q1P4`tKx%@x4xQ(=c?NJ*xVVlGplEKUA?gQ<*NS%)x2>Y zjA?3K*?>3Bu!}Q>T%0_4?U4GGw#BPxqcK2gobEkkl|I=j{Qzh$Tu|J+vb3;%B?PV% z-Ra(fseU_^l-l-=g+%WmtKih}IV6IC9W}Tw&_Bge-^)vFmAMDEo{q!oT6o<*6+sAZ z!Z)vC$ith3=;kA)RkxS6E@{i1mOX76uZgX(E;n~-?o{tgygrlKHTP`DVxap1E9+F0 zTf`2>hKoWbmRC_*4ACc5Fh7U#U$R?SQMEQD{Y6I&>LRFzjW`M2C62WG8v!Kfn-z3ms3+Os`F@L($ti< zdd+<7%BtJ(p@8Ese~^WkG2pE2Xoqy~*`Nu>kFzS9g}g4`Q8Oy*$xj~`A5+hqHi$l- zK*50V1Kh{?+-Q`UGiISp{GObN{Ka;DRfV11(@R}t48}<5o4F99)9Y+zMt*Hg-i!hs zL27F-S;KMM+OuHEoCS?MHo}}H5Qoh zlNE+tjP?u~P{@X`T3#Tmu-dtvj%u=&|6s(OEpu(HaUdW;5sfYqn=_NuDZz^@If z*VHd=q|ZNk{NWc!_x4J{veLboYzB^;sOQeA;@kZ;TU@i<5}bWrykZUjzFNK5zb4q|D76-qr& z_(?-zcz26R)R0*{-@|iia#lglI8fI(Gb+)U4x4X+&FNl~9WN9vaGKxo_JZEuET}A~ zS+=&5#Jz*Kg=WteKVn&l^6oH!J1bdoYG2%Ka)vRvL*{oC8u6azCip$Q*Ib{MS2(2w zGlCy5--DfXc6i#0fN`+#mND$U#$_<)LKD!d?V42;&y26ye$d$*&tZ=#y^#I8z}Y!= ziGz{1$`OrMJ_I&B1;4>(ylyMNCr)WG@se@X)^E$4#~q-v6QA{Igb)QdyS+LjeO>&@ zM4k^>wRm|8Nq0&#AU<}2E8UwkE{{fQth8oK#e@rC9w*CD<(^{;YU`_OX4covtD2cN zx4ts37VDMkU>&ni_bd0kl3$QlJF^}!O5bzhd>ZtNY3MOd@rR%rOpE<0aCo*o0`-CF z*_9L;WLQz&Ts-SxiXDKwpH@>|DV9Q|Rn{u#C1mBYMLHnRtl>|LQRKGy_L}je-X1Ln zg5^=mCV0eOd(uey6B@l&v~^CJxP}&cN0^>_Uefe*Z%B=?b4Jn3m}TkgNV>PxDrk~b zP=7D=UwAge=|cX)5bb_9IuMQZM|7jq2NQdo-i7sfW8i&}cz<9I5-r@x&7ATTs&gBU z5kDS}pung|-k+NTFT8Eyg1&n7h-J9FjwA0?`75b>d{&5tkYF)IBj&Zb7RRUw2Tn8& zygYgGAFWKEHz{HQgb4>uj8h{DNg-jJZjj2 zX8^sf1Eposy(z)an~jZwAEuQMe3M+gq@!8ZYD_^^dvt<$loxZ`lD){*RWEXYeM?Lz}n_yfN|FoYDtaDO>R=Ougl zAyW}wtI|m7M@c%b|6pOTLmdeh{h3|#SkNwZM!#FNWr&{yQsS z?$;;bd?(WS`E@w4xA!5BFCDZ}=lXaax?tx{bwNHr@gK`g?1St4sG@F;WtP92rxS)B zjmPYV6@nB^%LDvN_qGI0V=rmaz0}jqXf(I2o$q@G) zY2}BS>)RXf6{lwGnCn|{Y6riXQ;IWT#T!`|`BucQad`aGeKW0b?nMvn?VUNuJYS6g zvnx$%(A%q!$&{8F2bh8SSU)%_3i2w@pZ(bQDe7FvhU<#6DsB&o)2JttbPIKT(7|YR z_7*Hp_kJ5VFvpH=%}2D0Oub!CG*+y@N3k04 z4O9M{rdfQxi;?ba4un~3kj_5rPk;JJLz%DH2H9f}9b4Qv23wZO>cS#y=w;!eTb174 z-1+|I7}bB;^u#&IlGAbUuX~?rM83b}q3Q4Uvu0M-;=s3H(uBFPJt@E%^Bc4v7eyw< z?1+$~Eq@n+uJCSnNCb;}3W>jD!EGB%$HCEDZ3Eqn3eM!-VTWDghi7S(-3r^i)TiSY zq5746ITCmjF4%-MXm9VAX7!ERU2XKN2pm*m2Dt0KE%V5Ex*MXiLwsG@Uo##e;;H@c zSiQ58F^~28!&y&M^*vNI-K(Eq?K^12?e9CbA$P4Esl`R{3*n)tN7@h^$?*cHokP3M z7NCylPmHvU+3#4I?x{n!H+D2Hr{etCcp3WBJ^mD4I}>r{Z$LY|)DQ6lwo@y89^0?f z1XSvOP^qX#cV|XS!%HzZPU_^fketogP|wezCS`o68pzT6AeFpG__zjyn~JibnI<3gU{w5j-`YpsOf_t#1l9-avc z?iHAa%lNB2AkvvAy`Yz`8uDER;wf&Ge6mpZMjH5G_d8SqN zO_G|r&ax%HqphKd&z6lL|3G}d&ux9^f*O3Jv4$Sz!n%PRakXiKK0HrhDT7pmCQQ3C zaHj1_I`7J3ujyP*OKpE#r>S9)AJnv$j~j4kT6jIsn^$0;FVczTK?`i_Hi~tKZ~G*M z?zs3PBCY)I@cm1p7wyya6Im&E(r*_0{$%*#0o*mMPTdbugf4 zV$aO+XBwPmS<8=$p*26wHCRCVuA$SC%S@l5CmOI2Hm&-Tr0Jw)la|QqF#dQ?lh}tSu(vmSvV<=lvt}ids~dDehZ(4Dsd$$J>XRnlK%)fgAtmHL3%v@&7yfsN`y7xe! zh7KzH!DVk0@gv-rrFpb?#-s_DgLvR4!}^%Ji-&>f-avspZqnU`d*bht%emkRW6y2h zlAG==O$cObitpp4_6@)N8Z5MEGxbRpO@#DNiMhv|vx_&GdwW;l#0Iw`WC*FZEz|o} z{^BDQk!$Zz5aqN*Ig37ukH)}n19-oIn$+{H!OfY$KIGxGI5@BhSZD zjmzrkMlRmm#Ka#h!IGkDZ!}DLx;KL@G-o{M%>E*q2A1P(`>`pAKb71U9P51!+8)lg zwujW+A2vsl^z#g6g56JA6=$n{92eM!BX|zr6ZftgFL!g{l@xg8A$SFr2Zuw=OII|v z@_nx0l$naZFRv53#6}&y=;kl}VMP~&p?zPL=DRh1b!6y{9}y1#$J2puj(zGq6ps@p z4iElueXz+p5N7-}i|klw7v|ovrJGILnSt(a+SEkD&iZx7^{pQ>Mca+ zMr%zs`a!Z}Jnx}*-zwwpzR|-bt+t6cm5w`f9sn0l;xS6L|Fks5zusPcq8DCWZhI9CA2;px^HTQ@-!0V#fkacy-?GTx19e3#&3&$^X7A+5GwhpjdHntq zFNJO~i;X*ima>O=TG~7jWaVHf=T8B2<8xF#wF-4ORDXjpVpx*YbniT~UY|6HHl)CIF=))wZ}mLlJtt~>Bl*b>`&xW8)+_PxE-QQzXbV6-RS?SSvny&8WQDQ#_P zUW2*II%B3W@Q?0BzqEFSwb7?r4xP3|IKzy)nK;Nxea+r}SFKv1w}H@hyfhT|u6`mQ6!I%*2@rbrFQak!EP9O_DZc0Uoz% z=v={3c$wiGMY|mHKt+AyV$SU+VTIemTpfSkVozLjT(!)vtr^GdZU5ddF70S+D`{0J zE740#yhf9zV|1uCcLgf&T#GdrZ-TO0?VYo)^D?9J`ftzvA&;T-OboC8Xn}x#czi2q zdg>6q>k;?l&ADjePdS|b>96YM1{J-k$DGC%va%#Y2qA!grigx(EF?`7hnv4i%d4;cO)A?d%7!o`W#819km zl*RPiN{vZdQb1E0%rFb3yG_nLyo|!z6V0tnCi4W7xne50k#=e9!>uNLNl1E@6itJ4 zmEn!d;yIGamhSL~$@%Zhu$()zA(mlsgRTpW#O-WsP>Yo&<3Cn_(Bc3m_$?ife9SQX zvpa^CadfZUH}Y{K*cg(&(dl;@fj=;E2l;c8`0go_F(fQw=wuUTd}{4={n3aF4$b-4 z4?pqkpNz>Q79C^YQp@5<0ND0_wElY6Df+lV^Dqau5No(;_llAY}eAYwF zi(^;_y=`*72+cV!M{YmyV9;#%o2P1b&|vYY%)I&Y-qvDi(c1dV4)6*5q~))xEd(rG}L7U11dOE&Z{veU;o`!Yh>~>*JtI4Z>GU)*z9R z&4@h6^Nh*sZyJSuHXUz(8P|WKt%9Fc!|g2OoMm!O)Eu-3MsDs2rEjlHPU4 zyM6l6dnC|%?^-4vf#~VcEAT|~2kSx8+we@&x8Fh2i}6s;ADahBugGgvNxDP1`AhMj z>AiW9=I_9RrdQ~_l)bpZVlKT;ujRA(^lCj6@)z16@Ixi(`|BX-b$ggkHOJ@GkwEXU zL*Ypst)uaA%#)EqFST<@lS!dB+&N{HNx9CXoM=+$RdO$-zx$2rWl%^jn8U(xBk7al zpy^$6SZGLk>l}>%auqWFqReY38#KL%4uePg()3n3w2e06^nyCH5l!;+s=AjlAn|M4 z$fGydS(i~xFX7>rM2|!sy*rCP7vN8NUmJfe#Gl9TpJ~mVM^Xm8n26BJI-I&Jy`Tu< zu#r?My{JezqbY}8ScLpI{7LWU;HNxOcjf=CzN6w~y3&R2s!{y%;JAEScUQgge6NUk zx;kqFOYmMB?C7cyjFWkNq~wL+XAP2nH6D>99SQhYCVtuz=>ew3(S?$K(qh$<+E4Vj z7|0uaJ(B6^i?uqZ7pfi?6ZNDg({r9*FV%CpgNb^2CDT*2D3k33vfV%~&(QzXayrfs z|0UpWMXp28v`rUi_M?^F)lnq8XQ(eb(!}Nj4A;rFCet}s{n}BaI$aFxBipF1+z$Ag z>l>G*c3$GwU3FrDBp-GdjJK2YvX51lU*D@sGW)RaOVn3$h3=Ru^t0ue8I*4!w*_d% z>IIpZly9L)XRKHKK&G=*KalC;e~b4sA%A=to-6>KaE8R-32Bm^I$h}FrQZ?H?)=|% zd{GwbAEy1--~^=&E?Sh?pX>k*RNU95FR9BML^P1?zrIjtAk)9ld?3>=X+DtYX9_ci zkUWs}KU$ahQ=)+z2-6lzeJ{Y%Wke_7fxAm^<1U#dcm2h$HhcF9IvjPTWiEmVR&Y##4nKR)ih6NAk!~sJOY{i zg~lV0=}CC9m;64dhTF%EwXUOQXa0opfZSHVOC0)J^AD_%*aC9f139(~-M?D$ft(NI zd_!+3lzbrP13BN&e^q%P=L0$4&N#I%Ak&9v{eY|=$odU^tJ(+Td?4o=`qx@NAm;-)-_T#EJdpE&oNwquw0=M-U+ZV+ zhhkEHAj@4fn( z8<_@8x{sP)XE0v=9bHHGsD6CMpsowvF=*0#6us~0yzk3t{+LU|ejn8jV+`&q@?#8| zbRRW;wn4Gq$bY>_^!vC#^1n8?pU8b}(4_mQ`FQS`+SQlS{6W>ye}Nk)A9#r((}ORR zv3Ibx+u%%@gM7Ni&@xvA>4p|ug(v7q@4NU!DPjE~f>$S5BVMcX&tr;TD5hK>Wv#hF z@DHlv&x-%ib?0(C?MG!ip>oIN%i0FWeGN=C^3(H}rn0AISVb=C^3(H}vaC z{PIwew8^R$$a;aS*P>akp}$F@<5jH-kaYlAhefjvLob{zbq6v(kohf|`3)UQ(mv?AhsRVOwASqG4HSTyS} z^aCSgELg33!?P8i)AXMyeZA5RN>5k%B*k|WhiU#2rT?WkS<^34dT*sG6tfnK9V0H1 zF*gCH%h)?2K%Oftn&-gZ8a@4F%pKukAkX}e=Q-2WGey^#Bc`jK1Wd4p=UP|K?Yhn! zagpkAG0~o(G=92zuH2l%`=Xzf${Og(4|2GDL9ZwND>vtJ{^|2fem>`e=KL)wcsq^x zX7K)Ld`0H@On)$g`9L$@_zK~>b%Wtw%=@XE7i3;2{EL|%H1nVOhVcDR_lUQhFYR}m zu3>J=kb3)cRXlxGzRVZ5;YI@KH++$b%q*gT+)nEk2n}TVNZp6csg}4Is<=ky%GZ<3 zZ98;M`jO6qRa>R60J)C32W6P#}HuZ*XA>plg@ zan)bd;JCw0eK`~tk5(ub&?LC?3d zKL^#wnOFj?=@VWMz6sNXFM-zdL63`H&v`*`&GU+xV(*cfeq=wPAJ?(#Pl_*Veg3CX zV&)XxGn}G(g}jR-J+GhW-L7&EYx@n*c0EM<)HkYcz1H`~if?Lu?h&Hz5cS`~s_zNa zcd@2l{05ijwr?`JYrg6zP#mCTHYnXsW9ul@{pp{iE@wR}SgN*FEB`xMhyAo}$7uS$ zXGvSUm@9Z;mEiA{?xFh6Q_NC3_V5hH)VZsoM8^Ar=L$ZgXG1{lW7p}~5RmC|qI@%0x~^W{kux}fSg{ed_bo6)|lE` z#+0tTb*%B}h0^{$ePuj-_?Z%`hxd^5!()u5J-!XQmS{g(qU(tzx|RoCLF0jiY%Ayu znl7mQ&ywdg2KauWd)zgy=d}mq`HaBAKy9Re!i6Fr|TSQ=*_2{PX6xNHc!@(!1YA;`jfOZkm&=S7QU4Sp27Te zbvoW?U%XK99PQHwYTsW{Cu=Q(51udfe50|JsrBj+6F!4|l{T26`~y^Prj8|7={S0o zj-yvi-}zX2@CvEJgZqn3m#MDHRM%y@pzF%bvVOl(*X>tsmi76SAIQ4AyLB_xhP?g< za@=4o$Z-WUG{>o-u@>ZfAm;-)-_Tea^8NtG`R-bJdovG`fSw)Dn2{ z_U|fvx5@)q-lZ?qwK$OTca?rd<$)~k(xbILVfe86D-6FWmpK&3`dzw9+ZV|BF1@8v z)>AI#=1aPZzgK=2-&1}U?_4B$eyP~IN@y4Vs(M|#Px)Q!tLZKdtP%Y#j@7YdtgfNP z>X_rxGWK)@wCEYD>t%z(wOkjU)pA{&uJSIPI$QL+_pcb_pU3#LK09FO11crHfV_A1>Am~${AK7i z-Dd##oG74$&(MeKeO@4+Z~64qa;{?N{}f2Mck1}|v|$X*CRu9A2$>qh9Q21 z(_I``Cwm_k*C@Y>S<3I?5xTZHLf2`{SBd@2_?{sh!}sK>ad_fC&-@pRFDjAE+ZOHDw%cbe*=-ZM>g@ewiPn*2s7OhBBm>;cH-uF$gw zAk+J+oj|6qP&{dQ<^!32MfZWrb-pn;v{K@IsICKi)cGGY$Ah0Q)Q>=>%ajH(ovZRdrZ=fPkm<~N{MrZn0bEZwLHU6qUnzFx>hliw zYCe$j%e9?>Om}ELkm00$4km-|^1~UDlTCoer^#9Bf z8p!kvttXJ_m$W^BOpiWR&cT2isNTc1eSn;Quf_wA>ASRiAk#Uq%!5e|$mbhCPJgIY z(t(@~h? zKu*6#{Q+dUR?7!6U7-CD$n-|_50L3HZ7(3xztMak(^qIdkm+l+9zdpBl?F0>x0VNF zx=iB^$n@#T4`h0)@&lQkt^7cyQ)Wwjfkg8he3*{GlVt9vG)^xWhWEYEmIiZ_9(ARx zl@joP%b0(ZV(q?4FO=9G6(H}yESkqoi;m0xbg|fB@D-&kevv;w#`sYNjhzc`6uT5_ zXEUv73AT|gH;?C#mYCO zRP+y=Cs?F*jbD8O{cBAJa{41P2alt4*S`0}_OAC9 z$TJi`F3;d?2kw(Ya#t>r*aNb@Bs7mXNz$4BR$Yf8pZP#@Y#4OqEPj^%r~3Y%rBYv@ zq$_@{ZSwUz$p>=2LG)36pTP80w=Z9-^#ih85}NH!l5Y6FHGlfT%*)7+!1aWS^giAq zy^ps@@5}kL-e>b^y>DjddAjcba(hkFeGic70lM$8(4;eN(0!1FCY^EqB3ZwLVg2)R z{(xzisD9Kuk?QN`y16R7ZdgHvw5zb?w(oLUUwnK^_3de+v~1o`j0-n zmFchboa4;laxQgIqu>?q2x4E&Be zd~3hWw6))6+S+e3ZSA+2w)WdhTl;OMt^GFB)_$95YrlON^&4xy&H2`Tn`yJ(K3V;T z{WhnYefJBxuK;pAvH#|Lvk#xC^#*eO2ReQO*HiiX)yjAdWE%T*mbdopOq+fCgqfN@ zQ}ki~&iT5Jr?%$yZmE{{+<+T2jng;QNIHXeiz_{|R(ei*?UY5pX@99E^;oJItUKpN!nmo^Ty53K@wU^Mh>V1{-X9|73-d`Dh zRc05}*PL4z{H93OO~8Sazu;J*flQyJ=L0~lf4lBOflObo`&l55vd;rD zU99ia0-1hL&v}4MAFDKw=?k=cAk&vB4P<(3uIL8}ztR^d{gu8G2ITro)qEiHpIayO z1#)qqSVIZxv9tn(zXN89gh?H@p{ z|C$Q1AILP$nV8=?Z(`bR zvsFKk>3dZ_km)N_KalBbRX>pFpQ(Nz)347EKLEL2IG1BT_~&zae)OrHAK{#i^R4qb zrpg|weCs@wY3n?dX>*>Mq4GeM$GIx!oAcE^`o4^h7s!6Y zr``O%5~rd0E`N1A|1#~@due~0rTxd?LZuBZSK8qH+Hc>{e*1yyIZ63kJX_OU{7BOc zy7j?%Gy6%;ox6Hn_&oR9UKhTpC}(%QYBaq@({(-4EAs{6%X~{w_BWyYHOgP3{59S1 zU#R>SDnEYylg5KE{j2nx#zKxi(2UpWc@&WEs{&0r$IVk4rJhf1lzKj;`_HFlY5FWp z*Y(g-`-pu{?IZR*rTfcJ{#nXDOZjzQ8Opy=`8O)R?i<7SV|spJaK6$8b2J{F*0|cB z&)>NCKSdt<*~M2>?m~^nJM?|Voy8}Ve|Pby5n|V8s%KZ}owd{O&C`Ck!T3vYFHJYt zL;ZT1_Irbus-MnQIfLIQZScR!w^rp1PSNue7yBxoi|^_4S=ri;v$Y>*>vuJ>wI63| zKhD;EoUQ#hTl;Z#ru4H=e(lHE+K;ofABXa5KhD;EoUQ#hjQ?ZphaYP{{8;*sX$IQI9ucAZ5{tC97yt@8Go(gACSjC zph@TP?{1CjG>xA$jh{4)pEQl1G>xA$jh{4)pEQl1G>xB7evO|rjh{4)pHO~{pEQl1 zG>xAy{)e=GZP7T|qH(lE<7kV<(H4!PEgDB#G>*1t9Bt7!3gy>0+M;o^MdK)xU*l+t z#?cmyqcHw;8b?5m3n0glq2JPT#ZBvFo=(6=WIePgKt4D1X}zDmbg_)9o1)V16EKkH zIDtH$m%4hsG7V6>BIPW z)voJw+%|ZT#{X%GUX%D`wBmtH(qEoz6wFlmZ+cGrzKWhH$i=_P7x{p2c5~0u3=L6qX{Pp*=DAk)3`#O5hUme%_>bTZd z$F;sXuJzS%t*?%2eRW(5<=1houa0YdbzBSO*Kw_{j%$5&TnpnLsn7iayQuyn^}GVe z{ursx0|S%i>vO;(W6ASp>Uaa>@dn7_jiI;cc)Cr;(``DQZqxB}n~ta3bUfXr3AB(-+s1?lR)-QyFUL0WdF7Il5qx@Jikoy z%aZ4xq5cE1|A6d2L+_{Wc>}q;PxKpKK&B7Ye&XU%ncqEYyy$vD*MK>C?=46BoR3cW zar&(Kar&&fi|^_^a3HS<-qE!Lkm>3A>;RCTSp}N(D8=G$bZr6TwFQv#ft+6;_Qus= zv(D3RC=S-~Vw>W7iU;a@3Adg07|C}X{`9qsH_W`B@x%i+GEUKPDgpI5=X?Jw@AbdaRCwxD7LFS9sE3>$qpGm)c55d+(+8((T(DVNB5C7U8Qr? zgR?k&XWNI{{lQsTjCbgFIW6R}K{MuPAF$A*Gamhz*m88L*jS+NSrq7d7GLQ6dUW9~ z+i2IP>*zwU_i|n5jMRO?K}wI+F~r~ir42r&-vk75Uk2_={m;iZ4Bdv{XL zL*?9?eK%J9f2g2sul;w|F&e*j=y&^k)HB693|=8?Izzu_BDn6sJ zRoYFvo}sb5RLA@g`pglK`^FdApMgwQX+DtY3HnSDkm(y5Gk->Q{Z{wV0q)o!=?1;i zg!cAPbm%ZXlWuTN^|RCd7B6sOrgQEA+x#ABX`y-&k_)NM% zSI(uw__|9E%imf3nd}c!|2Op=>^I9r@0;bK2gvczeSUXxQeL1(=!OLbMZRHylndl? zyU*`V&ghTF7VQsVc$CIR7;e;OE(~5*DEbZlT=Nb7N%IXpt>0P(^7!(Ierp-X?Q)C0 zTYF1vhtlGgTVmpuVfw7bu$huSY^LM`*>7i*ik>iR)NdPw;mhiuFuY0q6NcLwrTpVd zGxw(P1jzL`zSP?&w2y3Wl6;dsc@O2M?umT$Jh30h_E*mnyDelpljNIpwm(V!MzRZf z44eS8!kB&($CDdTztCQ zeEHVPFLge-X0t=ORfw>ON@+SWxmCKtWazK^?vYbV;oS|peN=~<{jOr6fh-5)ax9w5G4xv*gS*HNZ&it%Z=F9Rp3dkW zN4IJHfUF-VcIZ3E=jwh0$mQ%TZN6O;h7YSgAeZaXyZWu8UH!I^tKXG3-#QAzU+6c6 zfNcM+(yyvKkmX%^iN@<9jT<2I0duK+Et=CywH<*>cc~oE&@5-sS)|9%i&Y*d{MtVM zuYTj{2JI(6uFtvJ&w+;CK=pUO0p))4sk{7M`b=|xJ6Lb8GJ`U%_9~Nc70CO#fDYp` z=>}anmk#6WE$+t70+HXY>r5b*+kJj_a&9?7 zU!vuTo~@9_X76Pdj%i;jL%rRJ~~$L;^G}VZUrd*ySP~D0p$1z=p6&8Ute6D zRUqi*$J1-(i2eX2f6W}x4`lrTE&A8Y5&enz@%+z}2o03=*>_A|rRPLI*8g48k49uY z@o1j3@4ia!nvy^xof2;_bTM-CayA*|DDd5uo@pwZu!2 zbeA^#@#&FbNe@u+BgLWz$Z;IdhCe<%up@anu#5Es_9f>F>_}eD|9N|o+vVE-UD?@P ze5LB|NQGfU<1`G{>$%D9;_Gw79|1}`zCK6d1IXN zgD>ba9tJCPy|SzL{(PyA!3&i(XwnVN*L;KfYrorB{7C(`vskC|!|vjfI<5yO{pd*@ z*MZ#M0$SqBO@BNl=>dw|<1y*CK-Lq`hCe<%up@anZn*(}yq$p^$;oa9xI7a7(-Nj$%{1BkD*DrK_0CIc;wD`|W->CCLfFie1=LaC`324#d zrU!N;FUKu6;E%U6up@anZn*(}yq$smUA1TD_=9ry%+Bt{rC;d$5QZCdd<(-PG){LG zzf^rYi^ZycXK`Px&(7jcbv)i({D+Rm0ZN?wL&swv$9F(Wd%EeL>UbQW$bG8gF_85H zwCHiu13QwJLo`4oTZhBxx@^ajA1O9kB13QwJ zDTFa7NE#or{fur^#ru& zanl1kl9%I_8}P^58Q77$9JkznKi$tmgJPX6?bUX{gTlM^5 zSFupf8w`G|=L-f+y1^})Z*Z)hKkO<#qvr_*S1E1Kq#K;3`39S`U+yf9SO4xT{z~VE z-Nk--J{_RMZ9hGq26BH3Xo)X3JwxZ207WiC=NTaD324#drU!N;FUKu6;E%U6up@an zZn*(}yq$smUA1TD_=9ry%+BuOtDl}vhhc`sX&9cX^TY1qM>;PDUB%@(KNuXSv_X?@@O7OZ49?d1VOQ~U9q$cZskA|pZg8pQ z8=R{BZf7xF{kyaHBb^_17vIxyJwS=u_jFtba(@eGi7z+(9o;_!D01)U{sG8(0$TLA z>46=|%W=yM_~Y#i>_}dYTW-J~Z)c!?SMAw3{-E4Fv$MPSdQamp4ByfHLm1A}`C)f) ztIiJril4XY`~c+m2x#$#n|`Ox4*`nYojN}NSx-QV9ydL(BY8P)xdDH?oq-+6%W=yM z_~Y#i^zW)YJI5cCyJvQGH!f|}@hc4P)cGL{@6-8VS8=+|2L}JG2b-XvYUTK3S-C%|08$7s7o(~4{bHPA<{>k9z`H~Ohd?4o=JWJn$0CM{0`kn%i zY4?2|_x&CBeI57xoZsm4U z5~3fU>lF(MU9o)J0HU8)Jb(GP?-AX9h2RQJ|5Wid%^$D%*OiL?>q@0OL!UEG^q(_N z(hYrs&fj6UR>$2iT&eP57*qK$d_kY%GB{Fcg9qwwHyXS=SDqs?*slBr)0N*~zUCVo zt@#FTP<;l^Q+|UlX*`AD`*rdj0+8P`7^vSi*rD(38ti|zJlED=pZD$GOP-4}^x&UL z{$PFnb?^|$H}p`I3&W8r7lvK>9I3%ibi6T`s8^oP8>-JC57p<6f&AQDB5n9(UJ3Y2 zxuu_5;-ITS_`CGEVj$PE`~0k@$dBQ2QeL1(XcKRr=yS!N=ySzDF1P!9 zDK}isEl22~`ab)Ov*a5Ff6({U&)4}Q43}&F55wWwuMBR|eq}IG?+$K<^Ggj%`<<`v zUjcdj7|>ySCf%Sb=h9((Cf%Sb=h9((nOZNwM1P6g@_7bD?{a-#49N8k=rBH$ZqSu; z=`cQ%ZqSu;=`g-buD7YLiG$(VuZC;C0&;wJpD*zpE+^#$dW1Idwn_WdChb>1F1P!9 zDK}isEl21l^_xC7>bFMTP~2Dh+iLyBH;~`ov*>{|ez@u7XASWvy}U%$n?UCCQGdUx zJYC*9M0%F+OM8{;bMijFFYo7boCSR1AHUqQhhknixR-Y2v^PxyLs zzY}|nAN=~q+coksDR<;tsRxk#=%fD5*T_NQN2IeKN9y|kK#m)q-xSuKKal+g;V-)l7V2>s0} zAoK4kUEs;@n-zGe{2p#WuBegJZWpAp{s8@a_FurK{N8>Z#a)5d+vw%@Yxh`h zuIkP8_40eTd#d*y^}{{thkMiy_oyF$><6T?9|9CVB=RZ0`r#h+1LW8biTt~$SN(90 z`T=^`4|}S&Ix7CH&KEm@Twfpc_wqpV{=-jKzMCTwPd7&-o^ICf8QiSz!2sEhNN2qP ziXRjCls_VN-5im2haCGck$)HU=BeI1UoZP{Pxa2yc$%g0G)v=Ymc|p1{eX1#LxAFk zL_X!$c$%g01UdFYBL6Px)p(kv@dUl>hdtHnX*_ru51z(@r||$}KOmj`5TN)Wkx%(G z9z2Z)$gv+1`FByT#)GHv0KM#oJ=MF9_M3g8(l7SW{>^ zwZHBYmH34m`(cmu=1afWC*Rl0e%MpJU+ph?ztVFIAlKJN{k=`lLumf+)0Jq>3e?8#PtM!|x z!MeB~&(qQJt_G=$eHR_hDET zlk=_@>jd{tlksJL{VlKki{j}T-Ov9<_wk=A-lh1V;#?iC1Kh#=Z?2we&DA&sa=Rwd zhF{t@;4|q4-F%l0V3liB~EVC{Q{8ddt?6pt#pY)W8ZoD zTYCYDUFQ`Ulzx3)k=PC7c`%^E_)NM%SI(uw_)NM%SI(uw_%b(8+?je_GehVAMedpz z21V~RGo;=?u6IC(@tJgkuAEDU@tJgkuAEDU@nv$oO+ByF-^vZcx_aRc!{4cV7+$CH zVfc#nuK>mFR~AZrfZRV`S@?e|UFvV_`|~WJ!|)32Cjm-5uF(DhlM&aUU+&~{{OC? zoAtM~!|)Rw*8&v#KGE?F$n_3rsaJSpCBY;Y9r{*)Y6K=f^PY zS&%uH=9QiWvYr9*_=R+~D@l6gF7j9J3je~G*aPJ97skXc3)#LT`6iw1OOn5l?0_D_ z=ju1;5l5H($y_K95@g->#;|>wQ&j_MSl-qQv&Vqf3Sed z_xW9YE}fvyE$=(mA8+60Z`VIw+cgoTeS`GxnwIf(tUmu5j#BQ}GJ{6WrQLKl-=%kt zf4u(QML0@1_Ak#sd1kYgu*X zPZc+48mDilk#r!XckR%4OhmCSNdK;BDgS4Bz8Q{E?$0U=8abDC)7^ZR-aY;|G#